From 8939ab257fd2ff82fbbc8cf0308caa5c9e638bbb Mon Sep 17 00:00:00 2001 From: Alexey Date: Wed, 16 Oct 2024 16:03:37 +0300 Subject: [PATCH] =?UTF-8?q?=D0=A1=D0=B4=D0=B5=D0=BB=D0=B0=D0=BD=D0=B0=20?= =?UTF-8?q?=D0=B4=D0=BE=D0=BA=D1=83=D0=BC=D0=B5=D0=BD=D1=82=D0=B0=D1=86?= =?UTF-8?q?=D0=B8=D1=8F=20=D0=BD=D0=B0=20=D1=82=D0=BE,=20=D1=87=D1=82?= =?UTF-8?q?=D0=BE=20=D0=B5=D1=81=D1=82=D1=8C=20=D1=81=D0=B5=D0=B9=D1=87?= =?UTF-8?q?=D0=B0=D1=81?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- DOCS/Doxyfile | 26 +- DOCS/html/_m_c_u_8c.html | 141 +- DOCS/html/_m_c_u_8c__incl.map | 12 +- DOCS/html/_m_c_u_8c__incl.md5 | 2 +- DOCS/html/_m_c_u_8c_source.html | 331 + DOCS/html/_r_e_a_d_m_e_8md.html | 1 + DOCS/html/annotated.html | 61 +- DOCS/html/arm__defines_8h.html | 1092 - DOCS/html/arm__defines_8h__dep__incl.map | 7 - DOCS/html/arm__defines_8h__dep__incl.md5 | 1 - DOCS/html/arm__defines_8h__dep__incl.png | Bin 6546 -> 0 bytes DOCS/html/arm__defines_8h_source.html | 247 - DOCS/html/classes.html | 47 +- DOCS/html/core__cm4__matlab_8h.html | 1426 - DOCS/html/core__cm4__matlab_8h__dep__incl.map | 7 - DOCS/html/core__cm4__matlab_8h__dep__incl.md5 | 1 - DOCS/html/core__cm4__matlab_8h__dep__incl.png | Bin 6580 -> 0 bytes DOCS/html/core__cm4__matlab_8h_source.html | 1594 - DOCS/html/darkmode_toggle.js | 222 + DOCS/html/dir_000002_000001.html | 84 - DOCS/html/dir_000002_000003.html | 3 +- ...004_000000.html => dir_000002_000004.html} | 7 +- DOCS/html/dir_000003_000002.html | 1 + DOCS/html/dir_000004_000003.html | 7 +- .../dir_30f2d142c55236add84215456f0e2b1c.html | 16 +- ...r_3a36e4bca13e6b41578f51df425c6641_dep.map | 10 - ...r_3a36e4bca13e6b41578f51df425c6641_dep.md5 | 1 - ...r_3a36e4bca13e6b41578f51df425c6641_dep.png | Bin 4230 -> 0 bytes .../dir_5bc05bcf5fafad3c8688aee149210d07.html | 22 +- ...r_5bc05bcf5fafad3c8688aee149210d07_dep.map | 4 +- ...r_5bc05bcf5fafad3c8688aee149210d07_dep.md5 | 2 +- .../dir_9609623a411adcd586e91350a30aa9d5.html | 37 +- ...r_9609623a411adcd586e91350a30aa9d5_dep.map | 19 +- ...r_9609623a411adcd586e91350a30aa9d5_dep.md5 | 2 +- ...r_9609623a411adcd586e91350a30aa9d5_dep.png | Bin 4673 -> 6150 bytes .../dir_afe59ba76eea2f90e4e37233dbf4f6f2.html | 15 +- ...r_afe59ba76eea2f90e4e37233dbf4f6f2_dep.map | 12 +- ...r_afe59ba76eea2f90e4e37233dbf4f6f2_dep.md5 | 2 +- ...r_afe59ba76eea2f90e4e37233dbf4f6f2_dep.png | Bin 5246 -> 1729 bytes ...dir_df8c7f866fb3beabf246989867a8aa90.html} | 48 +- ...r_df8c7f866fb3beabf246989867a8aa90_dep.map | 7 + ...r_df8c7f866fb3beabf246989867a8aa90_dep.md5 | 1 + ...r_df8c7f866fb3beabf246989867a8aa90_dep.png | Bin 0 -> 2470 bytes DOCS/html/doxygen.css | 8 +- DOCS/html/doxygen_crawl.html | 267 +- DOCS/html/dynsections.js | 7 + DOCS/html/files.html | 43 +- DOCS/html/functions.html | 87 +- DOCS/html/functions_a.html | 114 - DOCS/html/functions_b.html | 115 - DOCS/html/functions_c.html | 133 - DOCS/html/functions_d.html | 151 - DOCS/html/functions_e.html | 93 - DOCS/html/functions_f.html | 113 - DOCS/html/functions_g.html | 97 - DOCS/html/functions_h.html | 103 - DOCS/html/functions_i.html | 110 - DOCS/html/functions_j.html | 93 - DOCS/html/functions_k.html | 86 - DOCS/html/functions_l.html | 92 - DOCS/html/functions_m.html | 132 - DOCS/html/functions_n.html | 87 - DOCS/html/functions_o.html | 105 - DOCS/html/functions_p.html | 126 - DOCS/html/functions_q.html | 85 - DOCS/html/functions_r.html | 124 - DOCS/html/functions_s.html | 117 - DOCS/html/functions_t.html | 111 - DOCS/html/functions_u.html | 87 - DOCS/html/functions_v.html | 87 - DOCS/html/functions_vars.html | 87 +- DOCS/html/functions_vars_a.html | 114 - DOCS/html/functions_vars_b.html | 115 - DOCS/html/functions_vars_c.html | 133 - DOCS/html/functions_vars_d.html | 151 - DOCS/html/functions_vars_e.html | 93 - DOCS/html/functions_vars_f.html | 113 - DOCS/html/functions_vars_g.html | 97 - DOCS/html/functions_vars_h.html | 103 - DOCS/html/functions_vars_i.html | 110 - DOCS/html/functions_vars_j.html | 93 - DOCS/html/functions_vars_k.html | 86 - DOCS/html/functions_vars_l.html | 92 - DOCS/html/functions_vars_m.html | 132 - DOCS/html/functions_vars_n.html | 87 - DOCS/html/functions_vars_o.html | 105 - DOCS/html/functions_vars_p.html | 126 - DOCS/html/functions_vars_q.html | 85 - DOCS/html/functions_vars_r.html | 124 - DOCS/html/functions_vars_s.html | 117 - DOCS/html/functions_vars_t.html | 111 - DOCS/html/functions_vars_u.html | 87 - DOCS/html/functions_vars_v.html | 87 - DOCS/html/functions_vars_w.html | 87 - DOCS/html/functions_vars_z.html | 85 - DOCS/html/functions_w.html | 87 - DOCS/html/functions_z.html | 85 - DOCS/html/globals.html | 85 +- DOCS/html/globals_a.html | 576 +- DOCS/html/globals_b.html | 12 +- DOCS/html/globals_c.html | 3619 +- DOCS/html/globals_d.html | 878 +- DOCS/html/globals_defs.html | 236 +- DOCS/html/globals_defs_a.html | 660 - DOCS/html/globals_defs_b.html | 89 - DOCS/html/globals_defs_c.html | 3694 - DOCS/html/globals_defs_d.html | 933 - DOCS/html/globals_defs_e.html | 1379 - DOCS/html/globals_defs_f.html | 1369 - DOCS/html/globals_defs_g.html | 1129 - DOCS/html/globals_defs_h.html | 86 - DOCS/html/globals_defs_i.html | 435 - DOCS/html/globals_defs_l.html | 85 - DOCS/html/globals_defs_m.html | 89 - DOCS/html/globals_defs_n.html | 105 - DOCS/html/globals_defs_o.html | 86 - DOCS/html/globals_defs_p.html | 159 - DOCS/html/globals_defs_r.html | 1554 - DOCS/html/globals_defs_s.html | 961 - DOCS/html/globals_defs_t.html | 658 - DOCS/html/globals_defs_u.html | 1468 - DOCS/html/globals_defs_w.html | 142 - DOCS/html/globals_defs_x.html | 104 - DOCS/html/globals_e.html | 1308 +- DOCS/html/globals_enum.html | 86 - DOCS/html/globals_eval.html | 239 - DOCS/html/globals_f.html | 1306 +- DOCS/html/globals_func.html | 61 +- DOCS/html/globals_g.html | 1046 +- DOCS/html/globals_h.html | 4 +- DOCS/html/globals_i.html | 381 +- DOCS/html/globals_l.html | 85 - DOCS/html/globals_m.html | 33 +- DOCS/html/globals_n.html | 27 +- DOCS/html/globals_o.html | 7 +- DOCS/html/globals_p.html | 82 +- DOCS/html/globals_r.html | 1476 +- DOCS/html/globals_s.html | 927 +- DOCS/html/globals_t.html | 602 +- DOCS/html/globals_type.html | 50 +- DOCS/html/globals_u.html | 1398 +- DOCS/html/globals_vars.html | 29 +- DOCS/html/globals_w.html | 61 +- DOCS/html/globals_x.html | 104 - DOCS/html/graph_legend.html | 1 + DOCS/html/group___c_m_s_i_s.html | 106 - DOCS/html/group___c_m_s_i_s.map | 5 - DOCS/html/group___c_m_s_i_s.md5 | 1 - DOCS/html/group___c_m_s_i_s.png | Bin 2240 -> 0 bytes DOCS/html/group___c_m_s_i_s___c_o_r_e.html | 810 - DOCS/html/group___c_m_s_i_s___c_o_r_e.map | 5 - DOCS/html/group___c_m_s_i_s___c_o_r_e.md5 | 1 - DOCS/html/group___c_m_s_i_s___c_o_r_e.png | Bin 2505 -> 0 bytes ...up___c_m_s_i_s___core___fpu_functions.html | 142 - ...oup___c_m_s_i_s___core___fpu_functions.map | 5 - ...oup___c_m_s_i_s___core___fpu_functions.md5 | 1 - ...oup___c_m_s_i_s___core___fpu_functions.png | Bin 1583 -> 0 bytes ...c_m_s_i_s___core___function_interface.html | 105 - ..._c_m_s_i_s___core___function_interface.map | 5 - ..._c_m_s_i_s___core___function_interface.md5 | 1 - ..._c_m_s_i_s___core___function_interface.png | Bin 2092 -> 0 bytes ..._c_m_s_i_s___core___n_v_i_c_functions.html | 952 - ...__c_m_s_i_s___core___n_v_i_c_functions.map | 6 - ...__c_m_s_i_s___core___n_v_i_c_functions.md5 | 1 - ...__c_m_s_i_s___core___n_v_i_c_functions.png | Bin 3076 -> 0 bytes ...c_m_s_i_s___core___sys_tick_functions.html | 109 - ..._c_m_s_i_s___core___sys_tick_functions.map | 5 - ..._c_m_s_i_s___core___sys_tick_functions.md5 | 1 - ..._c_m_s_i_s___core___sys_tick_functions.png | Bin 1564 -> 0 bytes DOCS/html/group___c_m_s_i_s___core_debug.html | 1039 - DOCS/html/group___c_m_s_i_s___core_debug.map | 5 - DOCS/html/group___c_m_s_i_s___core_debug.md5 | 1 - DOCS/html/group___c_m_s_i_s___core_debug.png | Bin 2396 -> 0 bytes DOCS/html/group___c_m_s_i_s___d_w_t.html | 1243 - DOCS/html/group___c_m_s_i_s___d_w_t.map | 5 - DOCS/html/group___c_m_s_i_s___d_w_t.md5 | 1 - DOCS/html/group___c_m_s_i_s___d_w_t.png | Bin 2328 -> 0 bytes DOCS/html/group___c_m_s_i_s___device.html | 7582 - DOCS/html/group___c_m_s_i_s___device.map | 4 - DOCS/html/group___c_m_s_i_s___device.md5 | 1 - DOCS/html/group___c_m_s_i_s___device.png | Bin 1158 -> 0 bytes DOCS/html/group___c_m_s_i_s___f_p_u.html | 1005 - DOCS/html/group___c_m_s_i_s___f_p_u.map | 5 - DOCS/html/group___c_m_s_i_s___f_p_u.md5 | 1 - DOCS/html/group___c_m_s_i_s___f_p_u.png | Bin 2320 -> 0 bytes DOCS/html/group___c_m_s_i_s___i_t_m.html | 665 - DOCS/html/group___c_m_s_i_s___i_t_m.map | 5 - DOCS/html/group___c_m_s_i_s___i_t_m.md5 | 1 - DOCS/html/group___c_m_s_i_s___i_t_m.png | Bin 2462 -> 0 bytes DOCS/html/group___c_m_s_i_s___n_v_i_c.html | 155 - DOCS/html/group___c_m_s_i_s___n_v_i_c.map | 5 - DOCS/html/group___c_m_s_i_s___n_v_i_c.md5 | 1 - DOCS/html/group___c_m_s_i_s___n_v_i_c.png | Bin 2514 -> 0 bytes DOCS/html/group___c_m_s_i_s___s_c_b.html | 2705 - DOCS/html/group___c_m_s_i_s___s_c_b.map | 5 - DOCS/html/group___c_m_s_i_s___s_c_b.md5 | 1 - DOCS/html/group___c_m_s_i_s___s_c_b.png | Bin 2556 -> 0 bytes DOCS/html/group___c_m_s_i_s___s_cn_s_c_b.html | 325 - DOCS/html/group___c_m_s_i_s___s_cn_s_c_b.map | 5 - DOCS/html/group___c_m_s_i_s___s_cn_s_c_b.md5 | 1 - DOCS/html/group___c_m_s_i_s___s_cn_s_c_b.png | Bin 2423 -> 0 bytes DOCS/html/group___c_m_s_i_s___sys_tick.html | 427 - DOCS/html/group___c_m_s_i_s___sys_tick.map | 5 - DOCS/html/group___c_m_s_i_s___sys_tick.md5 | 1 - DOCS/html/group___c_m_s_i_s___sys_tick.png | Bin 2493 -> 0 bytes DOCS/html/group___c_m_s_i_s___t_p_i.html | 1345 - DOCS/html/group___c_m_s_i_s___t_p_i.map | 5 - DOCS/html/group___c_m_s_i_s___t_p_i.md5 | 1 - DOCS/html/group___c_m_s_i_s___t_p_i.png | Bin 2214 -> 0 bytes ...p___c_m_s_i_s__core___debug_functions.html | 3489 - ...up___c_m_s_i_s__core___debug_functions.map | 4 - ...up___c_m_s_i_s__core___debug_functions.md5 | 1 - ...up___c_m_s_i_s__core___debug_functions.png | Bin 1109 -> 0 bytes DOCS/html/group___c_m_s_i_s__core__base.html | 92 +- DOCS/html/group___c_m_s_i_s__core__base.map | 6 +- DOCS/html/group___c_m_s_i_s__core__base.md5 | 2 +- DOCS/html/group___c_m_s_i_s__core__base.png | Bin 3295 -> 1198 bytes .../group___c_m_s_i_s__core__bitfield.html | 182 - .../group___c_m_s_i_s__core__bitfield.map | 5 - .../group___c_m_s_i_s__core__bitfield.md5 | 1 - .../group___c_m_s_i_s__core__bitfield.png | Bin 2306 -> 0 bytes .../group___c_m_s_i_s__core__register.html | 108 - .../group___c_m_s_i_s__core__register.map | 4 - .../group___c_m_s_i_s__core__register.md5 | 1 - .../group___c_m_s_i_s__core__register.png | Bin 1623 -> 0 bytes DOCS/html/group___c_m_s_i_s__glob__defs.html | 87 - ...nfiguration__section__for___c_m_s_i_s.html | 194 - ...onfiguration__section__for___c_m_s_i_s.map | 4 - ...onfiguration__section__for___c_m_s_i_s.md5 | 1 - ...onfiguration__section__for___c_m_s_i_s.png | Bin 1473 -> 0 bytes DOCS/html/group___device___included.html | 94 - DOCS/html/group___device___included.map | 4 - DOCS/html/group___device___included.md5 | 1 - DOCS/html/group___device___included.png | Bin 1089 -> 0 bytes DOCS/html/group___exported__constants.html | 107 - DOCS/html/group___exported__constants.map | 6 - DOCS/html/group___exported__constants.md5 | 1 - DOCS/html/group___exported__constants.png | Bin 3595 -> 0 bytes DOCS/html/group___exported__macro.html | 470 - DOCS/html/group___exported__macro.map | 4 - DOCS/html/group___exported__macro.md5 | 1 - DOCS/html/group___exported__macro.png | Bin 1108 -> 0 bytes DOCS/html/group___exported__macros.html | 2044 - DOCS/html/group___exported__macros.map | 4 - DOCS/html/group___exported__macros.md5 | 1 - DOCS/html/group___exported__macros.png | Bin 1211 -> 0 bytes DOCS/html/group___exported__types.html | 213 - DOCS/html/group___exported__types.map | 4 - DOCS/html/group___exported__types.md5 | 1 - DOCS/html/group___exported__types.png | Bin 1106 -> 0 bytes .../group___g_p_i_o___s_i_m_u_l_a_t_o_r.html | 47 +- .../group___g_p_i_o___s_i_m_u_l_a_t_o_r.map | 6 +- .../group___g_p_i_o___s_i_m_u_l_a_t_o_r.md5 | 2 +- .../group___g_p_i_o___s_i_m_u_l_a_t_o_r.png | Bin 1190 -> 1162 bytes ...up___hardware___constant___definition.html | 119 - ...oup___hardware___constant___definition.map | 4 - ...oup___hardware___constant___definition.md5 | 1 - ...oup___hardware___constant___definition.png | Bin 1324 -> 0 bytes ...oup___library__configuration__section.html | 239 - ...roup___library__configuration__section.map | 4 - ...roup___library__configuration__section.md5 | 1 - ...roup___library__configuration__section.png | Bin 1380 -> 0 bytes .../group___m_a_i_n___s_i_m_u_l_a_t_o_r.html | 251 +- .../group___m_a_i_n___s_i_m_u_l_a_t_o_r.map | 14 +- .../group___m_a_i_n___s_i_m_u_l_a_t_o_r.md5 | 2 +- .../group___m_a_i_n___s_i_m_u_l_a_t_o_r.png | Bin 6160 -> 6155 bytes ...020a77f89d6c0ea99c7559cfa7e3ba0_cgraph.map | 4 +- ...020a77f89d6c0ea99c7559cfa7e3ba0_cgraph.md5 | 2 +- ...f389f4df35953d82d9d30ae161a8cf9_cgraph.map | 5 - ...f389f4df35953d82d9d30ae161a8cf9_cgraph.md5 | 1 - DOCS/html/group___m_c_u___w_r_a_p_p_e_r.html | 556 +- DOCS/html/group___m_c_u___w_r_a_p_p_e_r.map | 7 +- DOCS/html/group___m_c_u___w_r_a_p_p_e_r.md5 | 2 +- DOCS/html/group___m_c_u___w_r_a_p_p_e_r.png | Bin 1158 -> 2248 bytes ...5045e0feba8ddf08e20958fd1e36cd5_cgraph.map | 5 + ...5045e0feba8ddf08e20958fd1e36cd5_cgraph.md5 | 1 + ...045e0feba8ddf08e20958fd1e36cd5_cgraph.png} | Bin ...4429d6d68b1d72ce16bab374e3ffa08_cgraph.map | 11 + ...4429d6d68b1d72ce16bab374e3ffa08_cgraph.md5 | 1 + ...429d6d68b1d72ce16bab374e3ffa08_cgraph.png} | Bin ...f04b162923bada308d9668743425b92_cgraph.map | 9 + ...f04b162923bada308d9668743425b92_cgraph.md5 | 1 + ...04b162923bada308d9668743425b92_cgraph.png} | Bin ...def5b45f3d1646f248304e02b00e54_cgraph.map} | 28 +- ...cdef5b45f3d1646f248304e02b00e54_cgraph.md5 | 1 + ...def5b45f3d1646f248304e02b00e54_cgraph.png} | Bin ...c4ea41584d0367dfbfb697f5e57456_cgraph.map} | 38 +- ...3c4ea41584d0367dfbfb697f5e57456_cgraph.md5 | 1 + ...c4ea41584d0367dfbfb697f5e57456_cgraph.png} | Bin ...6b7bb9233d746d7709276f9ea1914c2_cgraph.map | 5 + ...6b7bb9233d746d7709276f9ea1914c2_cgraph.md5 | 1 + ...b7bb9233d746d7709276f9ea1914c2_cgraph.png} | Bin ...r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html | 519 +- ..._r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.map | 6 +- ..._r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.md5 | 2 +- ..._r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.png | Bin 1301 -> 1526 bytes ...heral___registers___bits___definition.html | 208536 --------------- ...pheral___registers___bits___definition.map | 4 - ...pheral___registers___bits___definition.md5 | 1 - ...pheral___registers___bits___definition.png | Bin 1560 -> 0 bytes .../html/group___peripheral__declaration.html | 1446 - DOCS/html/group___peripheral__declaration.map | 4 - DOCS/html/group___peripheral__declaration.md5 | 1 - DOCS/html/group___peripheral__declaration.png | Bin 1234 -> 0 bytes ...pheral__interrupt__number__definition.html | 522 - ...ipheral__interrupt__number__definition.map | 4 - ...ipheral__interrupt__number__definition.md5 | 1 - ...ipheral__interrupt__number__definition.png | Bin 1454 -> 0 bytes .../html/group___peripheral__memory__map.html | 1875 +- DOCS/html/group___peripheral__memory__map.map | 9 +- DOCS/html/group___peripheral__memory__map.md5 | 2 +- DOCS/html/group___peripheral__memory__map.png | Bin 3713 -> 1186 bytes ...p___peripheral__registers__structures.html | 214 - ...up___peripheral__registers__structures.map | 4 - ...up___peripheral__registers__structures.md5 | 1 - ...up___peripheral__registers__structures.png | Bin 1456 -> 0 bytes .../group___r_c_c___s_i_m_u_l_a_t_o_r.html | 50 +- .../group___r_c_c___s_i_m_u_l_a_t_o_r.map | 6 +- .../group___r_c_c___s_i_m_u_l_a_t_o_r.md5 | 2 +- .../group___r_c_c___s_i_m_u_l_a_t_o_r.png | Bin 1182 -> 1170 bytes .../group___s_i_m_u_l_a_t_o_r___c_o_n_f.html | 31 +- .../group___s_i_m_u_l_a_t_o_r___c_o_n_f.map | 6 +- .../group___s_i_m_u_l_a_t_o_r___c_o_n_f.md5 | 2 +- .../group___s_i_m_u_l_a_t_o_r___c_o_n_f.png | Bin 1198 -> 1236 bytes ..._f4xx___system___exported___constants.html | 94 - ...2_f4xx___system___exported___constants.map | 4 - ...2_f4xx___system___exported___constants.md5 | 1 - ...2_f4xx___system___exported___constants.png | Bin 1734 -> 0 bytes ..._f4xx___system___exported___functions.html | 156 - ...2_f4xx___system___exported___functions.map | 4 - ...2_f4xx___system___exported___functions.md5 | 1 - ...2_f4xx___system___exported___functions.png | Bin 1697 -> 0 bytes ...m32_f4xx___system___exported___macros.html | 94 - ..._m32_f4xx___system___exported___macros.map | 4 - ..._m32_f4xx___system___exported___macros.md5 | 1 - ..._m32_f4xx___system___exported___macros.png | Bin 1710 -> 0 bytes ...t_m32_f4xx___system___exported__types.html | 177 - ..._t_m32_f4xx___system___exported__types.map | 4 - ..._t_m32_f4xx___system___exported__types.md5 | 1 - ..._t_m32_f4xx___system___exported__types.png | Bin 1692 -> 0 bytes ...up___s_t_m32_f4xx___system___includes.html | 98 - ...oup___s_t_m32_f4xx___system___includes.map | 4 - ...oup___s_t_m32_f4xx___system___includes.md5 | 1 - ...oup___s_t_m32_f4xx___system___includes.png | Bin 1439 -> 0 bytes .../group___s_t_m___s_i_m_u_l_a_t_i_o_n.html | 25 +- .../group___s_t_m___s_i_m_u_l_a_t_i_o_n.map | 8 +- .../group___s_t_m___s_i_m_u_l_a_t_i_o_n.md5 | 2 +- .../group___s_t_m___s_i_m_u_l_a_t_i_o_n.png | Bin 2518 -> 2622 bytes .../group___t_i_m___s_i_m_u_l_a_t_o_r.html | 372 +- .../group___t_i_m___s_i_m_u_l_a_t_o_r.map | 6 +- .../group___t_i_m___s_i_m_u_l_a_t_o_r.md5 | 2 +- .../group___t_i_m___s_i_m_u_l_a_t_o_r.png | Bin 1157 -> 1131 bytes ...5b798408f2179ae27731f231cf4b620_cgraph.map | 4 +- ...5b798408f2179ae27731f231cf4b620_cgraph.md5 | 2 +- ...128cf64eeea541a8e25a72ce10da335_cgraph.map | 26 +- ...128cf64eeea541a8e25a72ce10da335_cgraph.md5 | 2 +- ...fcb4dd48557c21fdd6c379ad16bd229_cgraph.map | 24 +- ...fcb4dd48557c21fdd6c379ad16bd229_cgraph.md5 | 2 +- ...3dc3b53fe4b165b4c70e4d600258d50_cgraph.map | 14 +- ...3dc3b53fe4b165b4c70e4d600258d50_cgraph.md5 | 2 +- ...2b3ab4507a894ffa6e4487d42054e67_cgraph.map | 2 +- ...2b3ab4507a894ffa6e4487d42054e67_cgraph.md5 | 2 +- .../html/group___w_r_a_p_p_e_r___c_o_n_f.html | 128 +- DOCS/html/group___w_r_a_p_p_e_r___c_o_n_f.map | 6 +- DOCS/html/group___w_r_a_p_p_e_r___c_o_n_f.md5 | 2 +- DOCS/html/group___w_r_a_p_p_e_r___c_o_n_f.png | Bin 1163 -> 1189 bytes .../group___w_r_a_p_p_e_r___s_f_u_n_c.html | 552 + .../group___w_r_a_p_p_e_r___s_f_u_n_c.map | 4 + .../group___w_r_a_p_p_e_r___s_f_u_n_c.md5 | 1 + .../group___w_r_a_p_p_e_r___s_f_u_n_c.png | Bin 0 -> 1123 bytes ...dd07daf338cf84d1aee4bb8b6771720_cgraph.map | 13 + ...dd07daf338cf84d1aee4bb8b6771720_cgraph.md5 | 1 + ...dd07daf338cf84d1aee4bb8b6771720_cgraph.png | Bin 0 -> 4454 bytes ...43acfd8b3b5308d6c94bbf40efbbac5_cgraph.map | 11 + ...43acfd8b3b5308d6c94bbf40efbbac5_cgraph.md5 | 1 + ...43acfd8b3b5308d6c94bbf40efbbac5_cgraph.png | Bin 0 -> 4170 bytes ...2f81157111c2436496e1a9630bdce5b_cgraph.map | 5 + ...2f81157111c2436496e1a9630bdce5b_cgraph.md5 | 1 + ...2f81157111c2436496e1a9630bdce5b_cgraph.png | Bin 0 -> 1186 bytes ...3d5b495abad2acd2ae68febd1d2c5ec_cgraph.map | 65 + ...3d5b495abad2acd2ae68febd1d2c5ec_cgraph.md5 | 1 + ...3d5b495abad2acd2ae68febd1d2c5ec_cgraph.png | Bin 0 -> 63575 bytes DOCS/html/group__stm32f407xx.html | 113 - DOCS/html/group__stm32f407xx.map | 8 - DOCS/html/group__stm32f407xx.md5 | 1 - DOCS/html/group__stm32f407xx.png | Bin 6911 -> 0 bytes DOCS/html/group__stm32f4xx.html | 113 - DOCS/html/group__stm32f4xx.map | 8 - DOCS/html/group__stm32f4xx.md5 | 1 - DOCS/html/group__stm32f4xx.png | Bin 5941 -> 0 bytes DOCS/html/group__stm32f4xx__system.html | 117 - DOCS/html/group__stm32f4xx__system.map | 9 - DOCS/html/group__stm32f4xx__system.md5 | 1 - DOCS/html/group__stm32f4xx__system.png | Bin 9919 -> 0 bytes DOCS/html/index.html | 152 +- DOCS/html/mcu__wrapper_8c.html | 503 +- DOCS/html/mcu__wrapper_8c__incl.map | 12 +- DOCS/html/mcu__wrapper_8c__incl.md5 | 2 +- ...5045e0feba8ddf08e20958fd1e36cd5_cgraph.map | 5 - ...5045e0feba8ddf08e20958fd1e36cd5_cgraph.md5 | 1 - ...ea76a95b9b28061fb34ece9f6f0a85f_cgraph.map | 4 +- ...ea76a95b9b28061fb34ece9f6f0a85f_cgraph.md5 | 2 +- ...4429d6d68b1d72ce16bab374e3ffa08_cgraph.map | 11 - ...4429d6d68b1d72ce16bab374e3ffa08_cgraph.md5 | 1 - ...f04b162923bada308d9668743425b92_cgraph.map | 9 - ...f04b162923bada308d9668743425b92_cgraph.md5 | 1 - ...cdef5b45f3d1646f248304e02b00e54_cgraph.map | 53 - ...cdef5b45f3d1646f248304e02b00e54_cgraph.md5 | 1 - ...3c4ea41584d0367dfbfb697f5e57456_cgraph.map | 63 - ...3c4ea41584d0367dfbfb697f5e57456_cgraph.md5 | 1 - ...6b7bb9233d746d7709276f9ea1914c2_cgraph.map | 5 - ...6b7bb9233d746d7709276f9ea1914c2_cgraph.md5 | 1 - DOCS/html/mcu__wrapper_8c_source.html | 307 + DOCS/html/mcu__wrapper__conf_8h.html | 556 +- .../html/mcu__wrapper__conf_8h__dep__incl.map | 44 +- .../html/mcu__wrapper__conf_8h__dep__incl.md5 | 2 +- .../html/mcu__wrapper__conf_8h__dep__incl.png | Bin 36706 -> 33303 bytes DOCS/html/mcu__wrapper__conf_8h__incl.map | 10 +- DOCS/html/mcu__wrapper__conf_8h__incl.md5 | 2 +- ...4429d6d68b1d72ce16bab374e3ffa08_cgraph.map | 11 - ...4429d6d68b1d72ce16bab374e3ffa08_cgraph.md5 | 1 - ...4429d6d68b1d72ce16bab374e3ffa08_cgraph.png | Bin 3934 -> 0 bytes ...f04b162923bada308d9668743425b92_cgraph.map | 9 - ...f04b162923bada308d9668743425b92_cgraph.md5 | 1 - ...f04b162923bada308d9668743425b92_cgraph.png | Bin 3633 -> 0 bytes ...cdef5b45f3d1646f248304e02b00e54_cgraph.md5 | 1 - ...cdef5b45f3d1646f248304e02b00e54_cgraph.png | Bin 57178 -> 0 bytes ...3c4ea41584d0367dfbfb697f5e57456_cgraph.md5 | 1 - ...3c4ea41584d0367dfbfb697f5e57456_cgraph.png | Bin 62656 -> 0 bytes DOCS/html/mcu__wrapper__conf_8h_source.html | 275 +- ...b_2matlab__stm__emulate_2_r_e_a_d_m_e.html | 228 - DOCS/html/menudata.js | 138 +- DOCS/html/mexing_8m.html | 7 + DOCS/html/mexing_8m_source.html | 111 + DOCS/html/pages.html | 88 - DOCS/html/run__mex_8bat.html | 106 +- DOCS/html/run__mex_8bat_source.html | 186 + DOCS/html/search/all_0.js | 94 +- DOCS/html/search/all_1.js | 623 +- DOCS/html/search/all_10.js | 178 +- DOCS/html/search/all_11.js | 17 +- DOCS/html/search/all_12.js | 1529 +- DOCS/html/search/all_13.js | 981 +- DOCS/html/search/all_14.js | 663 +- DOCS/html/search/all_15.js | 1425 +- DOCS/html/search/all_16.js | 5 +- DOCS/html/search/all_17.js | 74 +- DOCS/html/search/all_18.js | 22 +- DOCS/html/search/all_19.js | 8 +- DOCS/html/search/all_1a.js | 7 +- DOCS/html/search/all_1b.js | 5 +- DOCS/html/search/all_1c.js | 4 +- DOCS/html/search/all_1d.js | 9 - DOCS/html/search/all_1e.js | 4 - DOCS/html/search/all_1f.js | 10 - DOCS/html/search/all_2.js | 42 +- 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DOCS/html/search/classes_d.js | 10 - DOCS/html/search/classes_e.js | 4 - DOCS/html/search/classes_f.js | 4 - DOCS/html/search/defines_0.js | 61 - DOCS/html/search/defines_1.js | 36 - DOCS/html/search/defines_2.js | 6 - DOCS/html/search/defines_3.js | 4 - DOCS/html/search/defines_4.js | 5 - DOCS/html/search/defines_5.js | 9 - DOCS/html/search/defines_6.js | 22 - DOCS/html/search/defines_7.js | 8 - DOCS/html/search/enums_0.js | 4 - DOCS/html/search/enums_1.js | 5 - DOCS/html/search/enums_2.js | 4 - DOCS/html/search/enumvalues_0.js | 4 - DOCS/html/search/enumvalues_1.js | 4 - DOCS/html/search/enumvalues_2.js | 11 - DOCS/html/search/enumvalues_3.js | 22 - DOCS/html/search/enumvalues_4.js | 14 - DOCS/html/search/enumvalues_5.js | 6 - DOCS/html/search/enumvalues_6.js | 9 - DOCS/html/search/enumvalues_7.js | 4 - DOCS/html/search/enumvalues_8.js | 4 - DOCS/html/search/enumvalues_9.js | 9 - DOCS/html/search/enumvalues_a.js | 5 - DOCS/html/search/enumvalues_b.js | 8 - DOCS/html/search/enumvalues_c.js | 11 - DOCS/html/search/enumvalues_d.js | 18 - DOCS/html/search/enumvalues_e.js | 10 - DOCS/html/search/enumvalues_f.js | 4 - DOCS/html/search/files_0.js | 5 +- DOCS/html/search/files_1.js | 3 +- DOCS/html/search/files_2.js | 14 +- DOCS/html/search/files_3.js | 5 - DOCS/html/search/files_4.js | 16 - DOCS/html/search/functions_0.js | 20 +- DOCS/html/search/functions_1.js | 9 +- DOCS/html/search/functions_2.js | 5 +- DOCS/html/search/functions_3.js | 4 +- DOCS/html/search/functions_4.js | 17 +- DOCS/html/search/functions_5.js | 7 +- DOCS/html/search/functions_6.js | 9 +- DOCS/html/search/functions_7.js | 16 +- DOCS/html/search/functions_8.js | 12 +- DOCS/html/search/functions_9.js | 18 - DOCS/html/search/functions_a.js | 5 - DOCS/html/search/groups_0.js | 6 +- DOCS/html/search/groups_1.js | 4 +- DOCS/html/search/groups_10.js | 4 - DOCS/html/search/groups_11.js | 4 - DOCS/html/search/groups_12.js | 5 - DOCS/html/search/groups_2.js | 15 +- DOCS/html/search/groups_3.js | 8 +- DOCS/html/search/groups_4.js | 7 +- DOCS/html/search/groups_5.js | 8 +- DOCS/html/search/groups_6.js | 3 +- DOCS/html/search/groups_7.js | 7 +- DOCS/html/search/groups_8.js | 8 +- DOCS/html/search/groups_9.js | 2 +- DOCS/html/search/groups_a.js | 6 +- DOCS/html/search/groups_b.js | 7 - DOCS/html/search/groups_c.js | 11 - DOCS/html/search/groups_d.js | 8 - DOCS/html/search/groups_e.js | 22 - DOCS/html/search/groups_f.js | 11 - DOCS/html/search/pages_0.js | 2 +- DOCS/html/search/pages_1.js | 2 +- DOCS/html/search/pages_2.js | 2 +- DOCS/html/search/searchdata.js | 33 +- DOCS/html/search/typedefs_1.js | 17 +- DOCS/html/search/typedefs_2.js | 5 - DOCS/html/search/typedefs_3.js | 17 - DOCS/html/search/variables_0.js | 7 +- DOCS/html/search/variables_1.js | 39 +- DOCS/html/search/variables_10.js | 44 +- DOCS/html/search/variables_11.js | 4 - DOCS/html/search/variables_12.js | 46 - DOCS/html/search/variables_13.js | 47 - DOCS/html/search/variables_14.js | 50 - DOCS/html/search/variables_15.js | 14 - DOCS/html/search/variables_16.js | 6 - DOCS/html/search/variables_17.js | 7 - DOCS/html/search/variables_18.js | 4 - DOCS/html/search/variables_2.js | 37 +- DOCS/html/search/variables_3.js | 76 +- DOCS/html/search/variables_4.js | 92 +- DOCS/html/search/variables_5.js | 20 +- DOCS/html/search/variables_6.js | 43 +- DOCS/html/search/variables_7.js | 24 +- DOCS/html/search/variables_8.js | 27 +- DOCS/html/search/variables_9.js | 35 +- DOCS/html/search/variables_a.js | 21 +- DOCS/html/search/variables_b.js | 5 +- DOCS/html/search/variables_c.js | 12 +- DOCS/html/search/variables_d.js | 65 +- DOCS/html/search/variables_e.js | 33 +- DOCS/html/search/variables_f.js | 29 +- DOCS/html/stdint_8h.html | 1749 - DOCS/html/stdint_8h__dep__incl.map | 7 - DOCS/html/stdint_8h__dep__incl.md5 | 1 - DOCS/html/stdint_8h__dep__incl.png | Bin 6475 -> 0 bytes DOCS/html/stdint_8h_source.html | 433 - DOCS/html/stm32f407xx__matlab_8h.html | 26117 -- .../stm32f407xx__matlab_8h__dep__incl.map | 5 - .../stm32f407xx__matlab_8h__dep__incl.md5 | 1 - .../stm32f407xx__matlab_8h__dep__incl.png | Bin 4501 -> 0 bytes DOCS/html/stm32f407xx__matlab_8h__incl.map | 11 - DOCS/html/stm32f407xx__matlab_8h__incl.md5 | 1 - DOCS/html/stm32f407xx__matlab_8h__incl.png | Bin 6768 -> 0 bytes DOCS/html/stm32f407xx__matlab_8h_source.html | 15592 -- DOCS/html/stm32f407xx__matlab__memory_8h.html | 261 + ...stm32f407xx__matlab__memory_8h_source.html | 273 + DOCS/html/stm32f4xx_8h.html | 161 - DOCS/html/stm32f4xx_8h_source.html | 334 - DOCS/html/stm32f4xx__matlab__conf_8c.html | 126 +- .../html/stm32f4xx__matlab__conf_8c__incl.map | 12 +- .../html/stm32f4xx__matlab__conf_8c__incl.md5 | 2 +- ...f389f4df35953d82d9d30ae161a8cf9_cgraph.map | 5 + ...f389f4df35953d82d9d30ae161a8cf9_cgraph.md5 | 1 + ...389f4df35953d82d9d30ae161a8cf9_cgraph.png} | Bin .../stm32f4xx__matlab__conf_8c_source.html | 484 + DOCS/html/stm32f4xx__matlab__conf_8h.html | 299 +- .../stm32f4xx__matlab__conf_8h__dep__incl.map | 44 +- .../stm32f4xx__matlab__conf_8h__dep__incl.md5 | 2 +- .../stm32f4xx__matlab__conf_8h__dep__incl.png | Bin 37124 -> 35293 bytes .../html/stm32f4xx__matlab__conf_8h__incl.map | 10 +- .../html/stm32f4xx__matlab__conf_8h__incl.md5 | 2 +- ...f389f4df35953d82d9d30ae161a8cf9_cgraph.map | 5 + ...f389f4df35953d82d9d30ae161a8cf9_cgraph.md5 | 1 + ...f389f4df35953d82d9d30ae161a8cf9_cgraph.png | Bin 0 -> 1304 bytes .../stm32f4xx__matlab__conf_8h_source.html | 273 +- DOCS/html/stm32f4xx__matlab__gpio_8c.html | 85 +- .../html/stm32f4xx__matlab__gpio_8c__incl.map | 54 +- .../html/stm32f4xx__matlab__gpio_8c__incl.md5 | 2 +- .../html/stm32f4xx__matlab__gpio_8c__incl.png | Bin 29971 -> 29405 bytes .../stm32f4xx__matlab__gpio_8c_source.html | 182 + DOCS/html/stm32f4xx__matlab__gpio_8h.html | 119 +- .../stm32f4xx__matlab__gpio_8h__dep__incl.map | 46 +- .../stm32f4xx__matlab__gpio_8h__dep__incl.md5 | 2 +- .../stm32f4xx__matlab__gpio_8h__dep__incl.png | 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group___m_c_u___w_r_a_p_p_e_r_gad3c4ea41584d0367dfbfb697f5e57456_cgraph.png} (100%) create mode 100644 DOCS/html/group___m_c_u___w_r_a_p_p_e_r_gad6b7bb9233d746d7709276f9ea1914c2_cgraph.map create mode 100644 DOCS/html/group___m_c_u___w_r_a_p_p_e_r_gad6b7bb9233d746d7709276f9ea1914c2_cgraph.md5 rename DOCS/html/{mcu__wrapper_8c_ad6b7bb9233d746d7709276f9ea1914c2_cgraph.png => group___m_c_u___w_r_a_p_p_e_r_gad6b7bb9233d746d7709276f9ea1914c2_cgraph.png} (100%) delete mode 100644 DOCS/html/group___peripheral___registers___bits___definition.html delete mode 100644 DOCS/html/group___peripheral___registers___bits___definition.map delete mode 100644 DOCS/html/group___peripheral___registers___bits___definition.md5 delete mode 100644 DOCS/html/group___peripheral___registers___bits___definition.png delete mode 100644 DOCS/html/group___peripheral__declaration.html delete mode 100644 DOCS/html/group___peripheral__declaration.map delete mode 100644 DOCS/html/group___peripheral__declaration.md5 delete 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DOCS/html/system__stm32f4xx_8h__dep__incl.map delete mode 100644 DOCS/html/system__stm32f4xx_8h__dep__incl.md5 delete mode 100644 DOCS/html/system__stm32f4xx_8h__dep__incl.png delete mode 100644 DOCS/html/system__stm32f4xx_8h_source.html delete mode 100644 DOCS/html/union_a_p_s_r___type.html delete mode 100644 DOCS/html/union_c_o_n_t_r_o_l___type.html delete mode 100644 DOCS/html/union_i_p_s_r___type.html delete mode 100644 DOCS/html/unionx_p_s_r___type.html create mode 100644 MCU_STM32F4xx_Matlab/Drivers/CMSIS/stm32f407xx_matlab_memory.h delete mode 100644 MCU_STM32F4xx_Matlab/Drivers/STM32F4xx_SIMULINK/stm32f4xx_matlab_gpio.c delete mode 100644 MCU_STM32F4xx_Matlab/Drivers/STM32F4xx_SIMULINK/stm32f4xx_matlab_gpio.h delete mode 100644 MCU_STM32F4xx_Matlab/Drivers/STM32F4xx_SIMULINK/stm32f4xx_matlab_rcc.c create mode 100644 MCU_STM32F4xx_Matlab/STM32F4xx_SIMULINK/stm32f4xx_matlab_gpio.c create mode 100644 MCU_STM32F4xx_Matlab/STM32F4xx_SIMULINK/stm32f4xx_matlab_gpio.h create mode 100644 MCU_STM32F4xx_Matlab/STM32F4xx_SIMULINK/stm32f4xx_matlab_rcc.c rename MCU_STM32F4xx_Matlab/{Drivers => }/STM32F4xx_SIMULINK/stm32f4xx_matlab_rcc.h (75%) rename MCU_STM32F4xx_Matlab/{Drivers => }/STM32F4xx_SIMULINK/stm32f4xx_matlab_tim.c (68%) rename MCU_STM32F4xx_Matlab/{Drivers => }/STM32F4xx_SIMULINK/stm32f4xx_matlab_tim.h (72%) rename MCU_STM32F4xx_Matlab/{Drivers => }/STM32F4xx_SIMULINK/stm32f4xx_periph_registers.c (74%) diff --git a/DOCS/Doxyfile b/DOCS/Doxyfile index 231ae8f..56d6d24 100644 --- a/DOCS/Doxyfile +++ b/DOCS/Doxyfile @@ -378,7 +378,7 @@ TOC_INCLUDE_HEADINGS = 5 # The default value is: DOXYGEN. # This tag requires that the tag MARKDOWN_SUPPORT is set to YES. -MARKDOWN_ID_STYLE = DOXYGEN +MARKDOWN_ID_STYLE = GITHUB # When enabled doxygen tries to link words that correspond to documented # classes, or namespaces to their corresponding documentation. Such a link can @@ -951,9 +951,10 @@ WARN_LOGFILE = INPUT = F:\Work\Projects\MATLAB\matlab_stm_emulate\MCU_Wrapper \ F:\Work\Projects\MATLAB\matlab_stm_emulate\MCU_STM32F4xx_Matlab \ - F:\Work\Projects\MATLAB\matlab_stm_emulate\MCU_STM32F4xx_Matlab\Drivers\STM32F4xx_SIMULINK \ - F:\Work\Projects\MATLAB\matlab_stm_emulate\MCU_STM32F4xx_Matlab\Drivers\CMSIS \ - F:\Work\Projects\MATLAB\matlab_stm_emulate + F:\Work\Projects\MATLAB\matlab_stm_emulate \ + F:\Work\Projects\MATLAB\matlab_stm_emulate \ + ../MCU_STM32F4xx_Matlab/Drivers/CMSIS \ + ../MCU_STM32F4xx_Matlab/STM32F4xx_SIMULINK # This tag can be used to specify the character encoding of the source files # that doxygen parses. Internally doxygen uses the UTF-8 encoding. Doxygen uses @@ -1060,7 +1061,12 @@ RECURSIVE = NO # Note that relative paths are relative to the directory from which doxygen is # run. -EXCLUDE = +EXCLUDE = ../MCU_STM32F4xx_Matlab/Drivers/CMSIS/arm_defines.h \ + ../MCU_STM32F4xx_Matlab/Drivers/CMSIS/core_cm4_matlab.h \ + ../MCU_STM32F4xx_Matlab/Drivers/CMSIS/stdint.h \ + ../MCU_STM32F4xx_Matlab/Drivers/CMSIS/stm32f4xx.h \ + ../MCU_STM32F4xx_Matlab/Drivers/CMSIS/stm32f407xx_matlab.h \ + ../MCU_STM32F4xx_Matlab/Drivers/CMSIS/system_stm32f4xx.h # The EXCLUDE_SYMLINKS tag can be used to select whether or not files or # directories that are symbolic links (a Unix file system feature) are excluded @@ -1171,7 +1177,7 @@ FILTER_SOURCE_PATTERNS = # (index.html). This can be useful if you have a project on for instance GitHub # and want to reuse the introduction page also for the doxygen output. -USE_MDFILE_AS_MAINPAGE = +USE_MDFILE_AS_MAINPAGE = README.md # The Fortran standard specifies that for fixed formatted Fortran code all # characters from position 72 are to be considered as comment. A common @@ -1193,7 +1199,7 @@ FORTRAN_COMMENT_AFTER = 72 # also VERBATIM_HEADERS is set to NO. # The default value is: NO. -SOURCE_BROWSER = NO +SOURCE_BROWSER = YES # Setting the INLINE_SOURCES tag to YES will include the body of functions, # multi-line macros, enums or list initialized variables directly into the @@ -1207,7 +1213,7 @@ INLINE_SOURCES = NO # Fortran comments will always remain visible. # The default value is: YES. -STRIP_CODE_COMMENTS = YES +STRIP_CODE_COMMENTS = NO # If the REFERENCED_BY_RELATION tag is set to YES then for each documented # entity all documented functions referencing it will be listed. @@ -1434,7 +1440,7 @@ HTML_EXTRA_FILES = # The default value is: AUTO_LIGHT. # This tag requires that the tag GENERATE_HTML is set to YES. -HTML_COLORSTYLE = AUTO_LIGHT +HTML_COLORSTYLE = TOGGLE # The HTML_COLORSTYLE_HUE tag controls the color of the HTML output. Doxygen # will adjust the colors in the style sheet and background images according to @@ -2153,7 +2159,7 @@ USE_PDFLATEX = YES # The default value is: NO. # This tag requires that the tag GENERATE_LATEX is set to YES. -LATEX_BATCHMODE = NO +LATEX_BATCHMODE = NON_STOP # If the LATEX_HIDE_INDICES tag is set to YES then doxygen will not include the # index chapters (such as File Index, Compound Index, etc.) in the output. diff --git a/DOCS/html/_m_c_u_8c.html b/DOCS/html/_m_c_u_8c.html index 6fc87e9..2df8ee1 100644 --- a/DOCS/html/_m_c_u_8c.html +++ b/DOCS/html/_m_c_u_8c.html @@ -14,6 +14,7 @@ + @@ -76,10 +77,14 @@ $(function() {
-Macros
+Macros | +Functions
MCU.c File Reference
+ +

ИÑходный код S-Function. +More...

#include "mcu_wrapper_conf.h"
#include "cg_sfun.h"
@@ -89,22 +94,22 @@ $(function() { -
+ +

Go to the source code of this file.

+
- - - - - - - - - - + + + + + + + + + + + +

Macros

#define S_FUNCTION_NAME   MCU
 
#define S_FUNCTION_LEVEL   2
 
#define MDL_UPDATE
 
#define MDL_CHECK_PARAMETERS   /* Change to #undef to remove function */
 
#define MDL_START   /* Change to #undef to remove function */
 
#define S_FUNCTION_NAME   MCU
 
#define S_FUNCTION_LEVEL   2
 
#define MDL_UPDATE
 Ð´Ð»Ñ Ð¿Ð¾Ð´ÐºÐ»ÑŽÑ‡ÐµÐ½Ð¸Ñ mdlUpdate()
 
#define MDL_CHECK_PARAMETERS   /* Change to #undef to remove function */
 
#define MDL_START   /* Change to #undef to remove function */
 
+ + + + + + + + + + + + + + + + + +

+Functions

static void mdlUpdate (SimStruct *S)
 Update S-Function at every step of simulation.
 
static void mdlOutputs (SimStruct *S)
 Writting outputs of S-Function.
 
static void mdlInitializeSizes (SimStruct *S)
 
static void mdlStart (SimStruct *S)
 Initialize S-Function at start of simulation.
 
static void mdlInitializeSampleTimes (SimStruct *S)
 Initialize Sample Time of Simulation.
 
static void mdlTerminate (SimStruct *S)
 Terminate S-Function at the end of simulation.
 
-

Macro Definition Documentation

- -

◆ S_FUNCTION_NAME

+

Detailed Description

+

ИÑходный код S-Function.

+

Данный файл Ñодержит функции S-Function, который вызывает MATLAB.

+
Note
ОпиÑание функций по большей чаÑти Ñгенерировано MATLAB'ом, поÑтому на английÑком
-
-
- - - - -
#define S_FUNCTION_NAME   MCU
-
- -
-
- -

◆ S_FUNCTION_LEVEL

- -
-
- - - - -
#define S_FUNCTION_LEVEL   2
-
- -
-
- -

◆ MDL_UPDATE

- -
-
- - - - -
#define MDL_UPDATE
-
- -
-
- -

◆ MDL_CHECK_PARAMETERS

- -
-
- - - - -
#define MDL_CHECK_PARAMETERS   /* Change to #undef to remove function */
-
- -
-
- -

◆ MDL_START

- -
-
- - - - -
#define MDL_START   /* Change to #undef to remove function */
-
- -
-
-
+

Definition in file MCU.c.

+
Generated by doxygen 1.10.0 diff --git a/DOCS/html/_m_c_u_8c__incl.map b/DOCS/html/_m_c_u_8c__incl.map index c5fcf86..48ee16b 100644 --- a/DOCS/html/_m_c_u_8c__incl.map +++ b/DOCS/html/_m_c_u_8c__incl.map @@ -1,20 +1,20 @@ - - + + - + - + - + - + diff --git a/DOCS/html/_m_c_u_8c__incl.md5 b/DOCS/html/_m_c_u_8c__incl.md5 index ebc7a53..5035837 100644 --- a/DOCS/html/_m_c_u_8c__incl.md5 +++ b/DOCS/html/_m_c_u_8c__incl.md5 @@ -1 +1 @@ -ad218c17ac7a45037c4547c026a854fa \ No newline at end of file +f2a5f97f943f4a05da982fbe5376cfc8 \ No newline at end of file diff --git a/DOCS/html/_m_c_u_8c_source.html b/DOCS/html/_m_c_u_8c_source.html new file mode 100644 index 0000000..1aee8c0 --- /dev/null +++ b/DOCS/html/_m_c_u_8c_source.html @@ -0,0 +1,331 @@ + + + + + + + +STM MATLAB Simulator: F:/Work/Projects/MATLAB/matlab_stm_emulate/MCU_Wrapper/MCU.c Source File + + + + + + + + + + + + +
+
+ + + + + + +
+
STM MATLAB Simulator +
+
+
+ + + + + + + + + +
+
+ + +
+
+
+
+
+
Loading...
+
Searching...
+
No Matches
+
+
+
+
+ + +
+
+
MCU.c
+
+
+Go to the documentation of this file.
1/**
+
2**************************************************************************
+
3* @file MCU.c
+
4* @brief ИÑходный код S-Function.
+
5**************************************************************************
+
6@details
+
7Данный файл Ñодержит функции S-Function, который вызывает MATLAB.
+
8**************************************************************************
+
9@note
+
10ОпиÑание функций по большей чаÑти Ñгенерировано MATLAB'ом, поÑтому на английÑком
+
11**************************************************************************/
+
12
+
13/**
+
14 * @addtogroup WRAPPER_SFUNC S-Function funtions
+
15 * @ingroup MCU_WRAPPER
+
16 * @brief Дефайны и функции блока S-Function
+
17 * @details ЗдеÑÑŒ Ñобраны функции, Ñ ÐºÐ¾Ñ‚Ð¾Ñ€Ñ‹Ð¼Ð¸ непоÑредÑтвенно работает S-Function
+
18 * @note ОпиÑание функций по большей чаÑти Ñгенерировано MATLAB'ом, поÑтому на английÑком
+
19 * @{
+
20 */
+
21
+
22#define S_FUNCTION_NAME MCU
+
23#define S_FUNCTION_LEVEL 2
+
24
+
25#include "mcu_wrapper_conf.h"
+
26
+
27#define MDL_UPDATE ///< Ð´Ð»Ñ Ð¿Ð¾Ð´ÐºÐ»ÑŽÑ‡ÐµÐ½Ð¸Ñ mdlUpdate()
+
28/**
+
29 * @brief Update S-Function at every step of simulation
+
30 * @param S - pointer to S-Function (library struct from "simstruc.h")
+
31 * @details Abstract:
+
32 * This function is called once for every major integration time step.
+
33 * Discrete states are typically updated here, but this function is useful
+
34 * for performing any tasks that should only take place once per
+
35 * integration step.
+
36 */
+
+
37static void mdlUpdate(SimStruct *S)
+
38{
+
39 // get time of simulation
+
40 time_T TIME = ssGetT(S);
+
41
+
42 //---------------SIMULATE MCU---------------
+
43 MCU_Step_Simulation(S, TIME); // SIMULATE MCU
+
44 //------------------------------------------
+
45}//end mdlUpdate
+
+
46
+
47/**
+
48 * @brief Writting outputs of S-Function
+
49 * @param S - pointer to S-Function (library struct from "simstruc.h")
+
50 * @details Abstract:
+
51 * In this function, you compute the outputs of your S-function
+
52 * block. Generally outputs are placed in the output vector(s),
+
53 * ssGetOutputPortSignal.
+
54 */
+
+
55static void mdlOutputs(SimStruct *S)
+
56{
+
57 SIM_writeOutputs(S);
+
58}//end mdlOutputs
+
+
59
+
60#define MDL_CHECK_PARAMETERS /* Change to #undef to remove function */
+
61#if defined(MDL_CHECK_PARAMETERS) && defined(MATLAB_MEX_FILE)
+
62static void mdlCheckParameters(SimStruct *S)
+
63{
+
64 int i;
+
65
+
66 // ПроверÑем и принимаем параметры и разрешаем или запрещаем их менÑÑ‚ÑŒ
+
67 // в процеÑÑе моделированиÑ
+
68 for (i=0; i<1; i++)
+
69 {
+
70 // Input parameter must be scalar or vector of type double
+
71 if (!mxIsDouble(ssGetSFcnParam(S,i)) || mxIsComplex(ssGetSFcnParam(S,i)) ||
+
72 mxIsEmpty(ssGetSFcnParam(S,i)))
+
73 {
+
74 ssSetErrorStatus(S,"Input parameter must be of type double");
+
75 return;
+
76 }
+
77 // Параметр м.б. только ÑкалÑром, вектором или матрицей
+
78 if (mxGetNumberOfDimensions(ssGetSFcnParam(S,i)) > 2)
+
79 {
+
80 ssSetErrorStatus(S,"Параметр м.б. только ÑкалÑром, вектором или матрицей");
+
81 return;
+
82 }
+
83// sim_dt = mxGetPr(ssGetSFcnParam(S,0))[0];
+
84 // Parameter not tunable
+
85// ssSetSFcnParamTunable(S, i, SS_PRM_NOT_TUNABLE);
+
86 // Parameter tunable (we must create a corresponding run-time parameter)
+
87 ssSetSFcnParamTunable(S, i, SS_PRM_TUNABLE);
+
88 // Parameter tunable only during simulation
+
89// ssSetSFcnParamTunable(S, i, SS_PRM_SIM_ONLY_TUNABLE);
+
90
+
91 }//for (i=0; i<NPARAMS; i++)
+
92
+
93}//end mdlCheckParameters
+
94#endif //MDL_CHECK_PARAMETERS
+
+
95static void mdlInitializeSizes(SimStruct *S)
+
96{
+
97 ssSetNumSFcnParams(S, 1);
+
98 // Кол-во ожидаемых и фактичеÑких параметров должно Ñовпадать
+
99 if(ssGetNumSFcnParams(S) == ssGetSFcnParamsCount(S))
+
100 {
+
101 // ПроверÑем и принимаем параметры
+
102 mdlCheckParameters(S);
+
103 }
+
104 else
+
105 {
+
106 return;// Parameter mismatch will be reported by Simulink
+
107 }
+
108
+
109 // set up discrete states
+
110 ssSetNumContStates(S, 0); // number of continuous states
+
111 ssSetNumDiscStates(S, DISC_STATES_WIDTH); // number of discrete states
+
112
+
113 // set up input port
+
114 if (!ssSetNumInputPorts(S, 1)) return;
+
115 for (int i = 0; i < IN_PORT_NUMB; i++)
+
116 ssSetInputPortWidth(S, i, IN_PORT_WIDTH);
+
117 ssSetInputPortDirectFeedThrough(S, 0, 0);
+
118 ssSetInputPortRequiredContiguous(S, 0, 1); // direct input signal access
+
119
+
120 // set up output port
+
121 if (!ssSetNumOutputPorts(S, OUT_PORT_NUMB)) return;
+
122 for (int i = 0; i < OUT_PORT_NUMB; i++)
+
123 ssSetOutputPortWidth(S, i, OUT_PORT_WIDTH);
+
124
+
125
+
126 ssSetNumSampleTimes(S, 1);
+
127
+
128
+
129 ssSetNumRWork( S, 5); // number of real work vector elements
+
130 ssSetNumIWork( S, 5); // number of integer work vector elements
+
131 ssSetNumPWork( S, 0); // number of pointer work vector elements
+
132 ssSetNumModes( S, 0); // number of mode work vector elements
+
133 ssSetNumNonsampledZCs( S, 0); // number of nonsampled zero crossings
+
134
+
135
+
136 ssSetRuntimeThreadSafetyCompliance(S, RUNTIME_THREAD_SAFETY_COMPLIANCE_TRUE);
+
137 /* Take care when specifying exception free code - see sfuntmpl.doc */
+
138 ssSetOptions(S, SS_OPTION_EXCEPTION_FREE_CODE);
+
139
+
140
+
141}
+
+
142
+
143#define MDL_START /* Change to #undef to remove function */
+
144#if defined(MDL_START)
+
145/**
+
146 * @brief Initialize S-Function at start of simulation
+
147 * @param S - pointer to S-Function (library struct from "simstruc.h")
+
148 * @details Abstract:
+
149 * This function is called once at start of model execution. If you
+
150 * have states that should be initialized once, this is the place
+
151 * to do it.
+
152 */
+
+
153static void mdlStart(SimStruct *S)
+
154{
+
155 SIM_Initialize_Simulation();
+
156}
+
+
157#endif // MDL_START
+
158
+
159/**
+
160 * @brief Initialize Sample Time of Simulation
+
161 * @param S - pointer to S-Function (library struct from "simstruc.h")
+
162 * @details Abstract:
+
163 * This function is used to specify the sample time(s) for your
+
164 * S-function. You must register the same number of sample times as
+
165 * specified in ssSetNumSampleTimes.
+
166 */
+
+
167static void mdlInitializeSampleTimes(SimStruct *S)
+
168{
+
169 // Шаг диÑкретизации
+
170 hmcu.SIM_Sample_Time = mxGetPr(ssGetSFcnParam(S,NPARAMS-1))[0];
+
171
+
172 // Register one pair for each sample time
+
173 ssSetSampleTime(S, 0, hmcu.SIM_Sample_Time);
+
174 ssSetOffsetTime(S, 0, 0.0);
+
175}
+
+
176
+
177/**
+
178 * @brief Terminate S-Function at the end of simulation
+
179 * @param S - pointer to S-Function (library struct from "simstruc.h")
+
180 * @details Abstract:
+
181 * In this function, you should perform any actions that are necessary
+
182 * at the termination of a simulation. For example, if memory was
+
183 * allocated in mdlStart, this is the place to free it.
+
184 */
+
+
185static void mdlTerminate(SimStruct *S)
+
186{
+
187 hmcu.fMCU_Stop = 1;
+
188 ResumeThread(hmcu.hMCUThread);
+
189 WaitForSingleObject(hmcu.hMCUThread, 10000);
+
190 SIM_deInitialize_Simulation();
+
191 mexUnlock();
+
192}
+
+
193
+
194
+
195/** WRAPPER_SFUNC
+
196 * @}
+
197 */
+
198
+
199#ifdef MATLAB_MEX_FILE /* Is this file being compiled as a
+
200 MEX-file? */
+
201#include "simulink.c" /* MEX-file interface mechanism */
+
202#else
+
203#include "cg_sfun.h" /* Code generation registration
+
204 function */
+
205#endif
+
SIM_Initialize_Simulation
void SIM_Initialize_Simulation(void)
Ð˜Ð½Ð¸Ñ†Ð¸Ð°Ð»Ð¸Ð·Ð°Ñ†Ð¸Ñ ÑимулÑции МК.
Definition mcu_wrapper.c:145
+
SIM_deInitialize_Simulation
void SIM_deInitialize_Simulation(void)
Ð”ÐµÐ¸Ð½Ð¸Ñ†Ð¸Ð°Ð»Ð¸Ð·Ð°Ñ†Ð¸Ñ ÑимулÑции МК.
Definition mcu_wrapper.c:162
+
MCU_Step_Simulation
void MCU_Step_Simulation(SimStruct *S, time_T time)
СимулÑÑ†Ð¸Ñ ÐœÐš на один такт ÑимулÑции.
Definition mcu_wrapper.c:53
+
IN_PORT_NUMB
#define IN_PORT_NUMB
number of input ports
Definition mcu_wrapper_conf.h:56
+
hmcu
SIM__MCUHandleTypeDef hmcu
Хендл Ð´Ð»Ñ ÑƒÐ¿Ñ€Ð°Ð²Ð»ÐµÐ½Ð¸Ñ Ð¿Ð¾Ñ‚Ð¾ÐºÐ¾Ð¼ программы МК
Definition mcu_wrapper.c:16
+
OUT_PORT_NUMB
#define OUT_PORT_NUMB
number of output ports
Definition mcu_wrapper_conf.h:58
+
DISC_STATES_WIDTH
#define DISC_STATES_WIDTH
width of discrete states array
Definition mcu_wrapper_conf.h:59
+
IN_PORT_WIDTH
#define IN_PORT_WIDTH
width of input ports
Definition mcu_wrapper_conf.h:55
+
OUT_PORT_WIDTH
#define OUT_PORT_WIDTH
width of output ports
Definition mcu_wrapper_conf.h:57
+
NPARAMS
#define NPARAMS
number of input parametrs (only Ts)
Definition mcu_wrapper_conf.h:54
+
mdlStart
static void mdlStart(SimStruct *S)
Initialize S-Function at start of simulation.
Definition MCU.c:153
+
mdlTerminate
static void mdlTerminate(SimStruct *S)
Terminate S-Function at the end of simulation.
Definition MCU.c:185
+
mdlInitializeSampleTimes
static void mdlInitializeSampleTimes(SimStruct *S)
Initialize Sample Time of Simulation.
Definition MCU.c:167
+
mdlOutputs
static void mdlOutputs(SimStruct *S)
Writting outputs of S-Function.
Definition MCU.c:55
+
mdlInitializeSizes
static void mdlInitializeSizes(SimStruct *S)
Definition MCU.c:95
+
mdlUpdate
static void mdlUpdate(SimStruct *S)
Update S-Function at every step of simulation.
Definition MCU.c:37
+
SIM_writeOutputs
void SIM_writeOutputs(SimStruct *S)
Формирование выходов S-Function.
Definition mcu_wrapper.c:122
+
mcu_wrapper_conf.h
Заголовочный файл Ð´Ð»Ñ Ð¾Ð±Ð¾Ð»Ð¾Ñ‡ÐºÐ¸ МК.
+
SIM__MCUHandleTypeDef::SIM_Sample_Time
double SIM_Sample_Time
sample time of simulation
Definition mcu_wrapper_conf.h:83
+
SIM__MCUHandleTypeDef::fMCU_Stop
unsigned fMCU_Stop
флаг Ð´Ð»Ñ Ð²Ñ‹Ñ…Ð¾Ð´Ð° из потока программы МК
Definition mcu_wrapper_conf.h:82
+
SIM__MCUHandleTypeDef::hMCUThread
HANDLE hMCUThread
Хендл Ð´Ð»Ñ Ð¿Ð¾Ñ‚Ð¾ÐºÐ° МК
Definition mcu_wrapper_conf.h:79
+
+ +
+Generated by doxygen 1.10.0 +
+ + diff --git a/DOCS/html/_r_e_a_d_m_e_8md.html b/DOCS/html/_r_e_a_d_m_e_8md.html index d4ee738..102f2b3 100644 --- a/DOCS/html/_r_e_a_d_m_e_8md.html +++ b/DOCS/html/_r_e_a_d_m_e_8md.html @@ -14,6 +14,7 @@ + diff --git a/DOCS/html/annotated.html b/DOCS/html/annotated.html index ddfea04..c7a4eab 100644 --- a/DOCS/html/annotated.html +++ b/DOCS/html/annotated.html @@ -14,6 +14,7 @@ + @@ -78,62 +79,10 @@ $(function() { - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + +
 C_cortex_memory
 C_memory
 CADC_Common_TypeDef
 CADC_TypeDefAnalog to Digital Converter
-
 CAPSR_TypeUnion type to access the Application Program Status Register (APSR)
 CCAN_FIFOMailBox_TypeDefController Area Network FIFOMailBox
 CCAN_FilterRegister_TypeDefController Area Network FilterRegister
 CCAN_TxMailBox_TypeDefController Area Network TxMailBox
 CCAN_TypeDefController Area Network
 CChannels_Sim
 CCONTROL_TypeUnion type to access the Control Registers (CONTROL)
 CCoreDebug_TypeStructure type to access the Core Debug Register (CoreDebug)
 CCRC_TypeDefCRC calculation unit
 CDAC_TypeDefDigital to Analog Converter
 CDBGMCU_TypeDefDebug MCU
 CDCMI_TypeDefDCMI
 CDMA_Stream_TypeDefDMA Controller
 CDMA_TypeDef
 CDWT_TypeStructure type to access the Data Watchpoint and Trace Register (DWT)
 CETH_TypeDefEthernet MAC
 CEXTI_TypeDefExternal Interrupt/Event Controller
 CFLASH_TypeDefFLASH Registers
 CFPU_TypeStructure type to access the Floating Point Unit (FPU)
 CFSMC_Bank1_TypeDefFlexible Static Memory Controller
 CFSMC_Bank1E_TypeDefFlexible Static Memory Controller Bank1E
 CFSMC_Bank2_3_TypeDefFlexible Static Memory Controller Bank2
 CFSMC_Bank4_TypeDefFlexible Static Memory Controller Bank4
 CGPIO_TypeDefGeneral Purpose I/O
 CI2C_TypeDefInter-integrated Circuit Interface
 CIPSR_TypeUnion type to access the Interrupt Program Status Register (IPSR)
 CITM_TypeStructure type to access the Instrumentation Trace Macrocell Register (ITM)
 CIWDG_TypeDefIndependent WATCHDOG
 CNVIC_TypeStructure type to access the Nested Vectored Interrupt Controller (NVIC)
 CPWR_TypeDefPower Control
 CRCC_TypeDefReset and Clock Control
 CRNG_TypeDefRNG
 CRTC_TypeDefReal-Time Clock
 CSCB_TypeStructure type to access the System Control Block (SCB)
 CSCnSCB_TypeStructure type to access the System Control and ID Register not in the SCB
 CSDIO_TypeDefSD host Interface
 CSIM__MCUHandleTypeDefMCU handle Structure definition
 CSlaveChannels
 CSPI_TypeDefSerial Peripheral Interface
 CSYSCFG_TypeDefSystem configuration controller
 CSysTick_TypeStructure type to access the System Timer (SysTick)
 CTIM_Sim
 CTIM_TypeDefTIM
 CTPI_TypeStructure type to access the Trace Port Interface Register (TPI)
 CUSART_TypeDefUniversal Synchronous Asynchronous Receiver Transmitter
 CUSB_OTG_DeviceTypeDefUSB_OTG_device_Registers
 CUSB_OTG_GlobalTypeDefUSB_OTG_Core_Registers
 CUSB_OTG_HostChannelTypeDefUSB_OTG_Host_Channel_Specific_Registers
 CUSB_OTG_HostTypeDefUSB_OTG_Host_Mode_Register_Structures
 CUSB_OTG_INEndpointTypeDefUSB_OTG_IN_Endpoint-Specific_Register
 CUSB_OTG_OUTEndpointTypeDefUSB_OTG_OUT_Endpoint-Specific_Registers
 CWWDG_TypeDefWindow WATCHDOG
 CxPSR_TypeUnion type to access the Special-Purpose Program Status Registers (xPSR)
 CChannels_SimСтруктура Ð´Ð»Ñ Ð¼Ð¾Ð´ÐµÐ»Ð¸Ñ€Ð¾Ð²Ð°Ð½Ð¸Ñ ÐºÐ°Ð½Ð°Ð»Ð¾Ð² таймера
 CSIM__MCUHandleTypeDefMCU handle Structure definition
 CSlaveChannelsСтруктура Ð´Ð»Ñ ÑƒÐ¿Ñ€Ð°Ð²Ð»ÐµÐ½Ð¸Ñ Ð¡Ð»ÐµÐ¹Ð² Таймерами
 CTIM_SimСтруктура Ð´Ð»Ñ Ð¼Ð¾Ð´ÐµÐ»Ð¸Ñ€Ð¾Ð²Ð°Ð½Ð¸Ñ Ñ‚Ð°Ð¹Ð¼ÐµÑ€Ð°
diff --git a/DOCS/html/arm__defines_8h.html b/DOCS/html/arm__defines_8h.html deleted file mode 100644 index cc55e03..0000000 --- a/DOCS/html/arm__defines_8h.html +++ /dev/null @@ -1,1092 +0,0 @@ - - - - - - - -STM MATLAB Simulator: F:/Work/Projects/MATLAB/matlab_stm_emulate/MCU_STM32F4xx_Matlab/Drivers/CMSIS/arm_defines.h File Reference - - - - - - - - - - - -
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#define __disable_irq()
 
#define __ASM   __asm
 
#define __IO   volatile
 
#define __inline   inline
 
#define __INLINE   __inline
 
#define __STATIC_INLINE   static __inline
 
#define __STATIC_FORCEINLINE   static __forceinline
 
#define __NO_RETURN   __declspec(noreturn)
 
#define __USED   __attribute__((used))
 
#define __WEAK   __declspec(selectany)
 
#define __PACKED   __attribute__((packed))
 
#define __PACKED_STRUCT   __packed struct
 
#define __PACKED_UNION   __packed union
 
#define __UNALIGNED_UINT32(x)   (*((__packed uint32_t *)(x)))
 
#define __UNALIGNED_UINT16_WRITE(addr, val)   ((*((__packed uint16_t *)(addr))) = (val))
 
#define __UNALIGNED_UINT16_READ(addr)   (*((const __packed uint16_t *)(addr)))
 
#define __UNALIGNED_UINT32_WRITE(addr, val)   ((*((__packed uint32_t *)(addr))) = (val))
 
#define __UNALIGNED_UINT32_READ(addr)   (*((const __packed uint32_t *)(addr)))
 
#define __ALIGNED(x)   __attribute__((aligned(x)))
 
#define __RESTRICT   __restrict
 
#define __NOP()
 No Operation.
 
#define __WFI()
 Wait For Interrupt.
 
#define __WFE()
 Wait For Event.
 
#define __SEV()
 Send Event.
 
#define __ISB()
 Instruction Synchronization Barrier.
 
#define __DSB()
 Data Synchronization Barrier.
 
#define __DMB()
 Data Memory Barrier.
 
#define __REV(value)   value
 Reverse byte order (32 bit)
 
#define __REV16(value)   value
 Reverse byte order (16 bit)
 
#define __REVSH(value)   value
 Reverse byte order (16 bit)
 
#define __ROR()
 Rotate Right in unsigned value (32 bit)
 
#define __BKPT(value)   value
 Breakpoint.
 
#define __RBIT()   _byteswap_ulong(_rotr(value, 16))
 Reverse bit order of value.
 
#define __CLZ()   __lzcnt(value)
 Count leading zeros.
 
#define __LDREXB(ptr)   (*(volatile uint8_t *)(ptr))
 LDR Exclusive (8 bit)
 
#define __LDREXH(ptr)   (*(volatile uint16_t *)(ptr))
 LDR Exclusive (16 bit)
 
#define __LDREXW(ptr)   (*(volatile uint32_t *)(ptr))
 LDR Exclusive (32 bit)
 
#define __STREXB(value, ptr)   (*(volatile uint8_t *)(ptr) = (value), 0)
 STR Exclusive (8 bit)
 
#define __STREXH(value, ptr)   (*(volatile uint16_t *)(ptr) = (value), 0)
 STR Exclusive (16 bit)
 
#define __STREXW(value, ptr)   (*(volatile uint32_t *)(ptr) = (value), 0)
 STR Exclusive (32 bit)
 
#define __CLREX
 Remove the exclusive lock.
 
#define __SSAT
 Signed Saturate.
 
#define __USAT
 Unsigned Saturate.
 
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Macro Definition Documentation

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- - diff --git a/DOCS/html/arm__defines_8h__dep__incl.map b/DOCS/html/arm__defines_8h__dep__incl.map deleted file mode 100644 index 9458314..0000000 --- a/DOCS/html/arm__defines_8h__dep__incl.map +++ /dev/null @@ -1,7 +0,0 @@ - - - - - - - diff --git a/DOCS/html/arm__defines_8h__dep__incl.md5 b/DOCS/html/arm__defines_8h__dep__incl.md5 deleted file mode 100644 index 7f5f5df..0000000 --- a/DOCS/html/arm__defines_8h__dep__incl.md5 +++ /dev/null @@ -1 +0,0 @@ -b319a6ccaad9080d246bebc45c65e140 \ No newline at end of file diff --git a/DOCS/html/arm__defines_8h__dep__incl.png b/DOCS/html/arm__defines_8h__dep__incl.png deleted file mode 100644 index ad45d94c5932ebe90de57e42a1664b72525affe4..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 6546 zcmb`McT`i$zQ+RyqI6I|O6Y=RW z0Gr8W1FOTD0szo~nVAk-08BIU;hhO$YHR>F_<22VFHZ*mP8pjR=vqI>TggWcJN4e^ z9p2MI-s9pI8#SmE5aWKvEWmqP<=>*X9_x2TiZI3ts*(=ebk*#?;BDNYewkCvbia zDgw0fGGHwoee?eK)S`3tjks)C8~1{kh>kjlgoQh5Fw_cJvdZGXGAWfY%so5E{Yd2T z9sIIO%sq|xO}89%^L&LfmzuoHf!di*!H(|j9u}~RK|7A-8BXf&<4|`k2f~_*V&uuU z?8QiMnHBca{e=?CGjK2T6mjT%T+m&~>PBd9g(Ch|3tGk4oK_yv(ZGss!?JegJ)}|) zNMRL9g{^e|E869tnrAoUBT;_#x|kq24Lh!-J~gb>2BOjVT-8_4#}n0KZCK1%V2Ul z@AE7nh?Gxi9JFiCWdl6uJd0nh;+lrBchbcMG3svD;_LONop=r=OmhvDx9zNq)5Q}yyJw+G3A#_UyqVYT-*YvI2X6wx`!_N zt1=wlV{FlV=fv(;TZbe~%ElIL*jri=riit2iqgqXU8 zBEy1~Uh?_ljSXV1MXTSGRN=Vxj-lN8citx7h(=J_LlYoSIzOalg4ansG0A$ckra+g zZD=Ak6dMWs!0Bo#0pdgpP60%F@^bNMS%RyqG4r-QQLuo$-#`Ua7Ia^m&HD-81I#j%B2Nt`9f^V-f9Za-W zghFV|!txvVtZ6!MR|U)m*x0{y`mKu?PZv5V4fpKGVi%r~>0K6Ay|ulB*UDVd(~gT@ zM((ki@#-)R;VYwTbx-2PJj0wj7L{EH~X{=2PUJoRZ_ZT zU}IZJo}UWREfDzbByo?Tr_D(dca-Nd?#ToZpj z6r?%d@6#D)tjCura2-9yghUY3FLuDUH6ttg(MEq70D4hX17v*a(+4sej*V3s8qlUW z;sfvj0gNKE=+3``b}#Q-O*_uqhgLv7bV`f%G&Pk(HV1k*#H8XXPrgTIgFEq>!}zP> zW`(&>vmf*Zk@C6x+1E$aC3*+!xKu}6c_73T+-QJ~c=b$Gfufa9+ZxHAqnY~QSq}Y= z0l$doeUSlG(8^^q6G-fOV<9uF z!l*?BK*BHgGZ&;IjdHl2RGqBqK_MBjwvWh+=T`>;UtM?G7mwuh6f8nejmca~n%ucU z*`BSQYKl{(?sj43@z09CZ1$`tIJ}ohd;kSl|MXv-q0@M;Z_M4g({vERMb1j$&(ME5 ziGTN9G;gQ&)>odEz$Kg4zXA9kO*i?f%DzTq(RTKn@Q1y&u_zwbOMwRWeerAFJvP~8 zjwr zb1HLMgK%Cu3IPqQ#yaMbV&pd^R>ulDCO(KhXYWuF{JJDE=JCZy9@%f{ijznc=m>z>t6z+`#B-o6=Xo3oVhM%P zEnCHukQPcdg-V>9&0F25<(*)HfH2=TwqPMIeAi+fHTT|8^M5Y+|Fkcs(yv`Y|1X2_ z?=JBFH{|8!O;HPTb4S7&E#j8!rE7@72aDHtoVI^cSl%b&Bgzi;e%ScJI_H+*t(RKh zE4WJ&eM?spug1o1?(Ef%EAQ=>nr3>q9P_wG5?y~;3t}X?xHtMrs;b)e|GQl#* zIo@xfHl)7-M!jJ)uhPxRF-?wxP?rxz1!Ml1TP0p5c)k|iSElC*r8+XDj$8ua{||rx z4kZWh!TMi3-SN}sa2Ts?*2An^!wFwayJY+kwenG5C|hL2VMs#aUX_Z5c_O)I%)466 zzvU91QtIMH^yZ3Hd-ONJ06Q-*p65%F?Nh69F_wi0tC8$pY1hINN}q*#r{HenG~I{> zW_z+oV<#sbDEfIL@R?=V~J>zS(XZ+WW zu@)G{1SkH~93p+Rnhgw5IXs0$F(W>kQ?V;*M@1RCH90vIW$6Aqn>is<`%oD~HGT4k zSF-hO)1heV&RCl_Lkp~8L|g)O#Hh}YC2_60h~jhp7${lO{JtWMV9AI}-x+e&*y{v9 z;P)I9oMvj)!hO#9p3PrtnSdwBjj3N5e43G}ZvKpqCHnJJg)&^=aTi1Mj&frHR%-pI z=9AxG*TD+gF_aI0WM~&{WL)E5gih(d)p>Op z$m!agYOA+uU$H6l`X;CT66!^X=8*Gry`AEYy&5{;OmOovIb#L)){O@5*8#A4Pwhy8 z1eLk?nyH{a?;`spm~%OPX|PRAb_UG3>tXz#38VQ&3j!sXG<9DnJ|Ar+U8HQT-pjOd z!4xM)6Y2$p)~zc|+=l{mv|k6-gSlb)jf8!zfg?*y5a@`$Cg-^ndR4(+JblMabz0Te zepPj|3;%d|`fb~gelYrea*d{(WMFl6&DW0iTD2tb`;02Z$}D}3A^hjU7S(4K%fP1h zr5%DWjoY#p12O1gklO55vAdW2>d&mvtR8DNw{}M6O(Ja1R&yaY?-^fl%JW;e7+r!% zMZ%3YvciP|a147-LBVrx%A6+MyFPBl=l}aa0dC#ny@N zankcs=TjFe?Wjo?$D=)6IV|3Q4hdUXRT_(iMQpEssmy5#s8<=^5LNYaY1r?*6ZpT= z$8Q&w`|Rr~o*UT?q9sxB_KGv+&C5?~JsbU&h1OA#}E9mkpa^bUH+(3RufcazYTQ~S{qM^>2hST{T$>j*Rm zGSmHOo7lOEKJZrz(V*mnNO(;DR`_wG z>3v1m;0^=T*ekBo)owQj00fLw-T3N$0Pr zV~Jc$d0%FhabLa02Tgc#fPM~;CLywbUSIgi=(L=xt>d!Yai8hS(=(Y7i?`~u$EO?D z&JxE4U>XS){Au1f9m;2>OQ&^ELGu`rXYxRf-}GthX>xrjVnHLK^2_vRO51ZtI30)sNQEt6l@xH*b*&O~xyCb1C^>X%2>b;4X zWrF!d``R$f3!B$lcLq);vgZz@gMFLkfU8Xt2*i0k9<~K27JgG-f`PdNtx6}|?(NjJ7uF>HFr{5TgR<Z6NZTO}1tNq>zn=vpd{xIbUYHZs&d!YNYic;iAxy6U;Uoe}eu$;tS)O^z?L` zEj@tWnunq}9ARNlGc~|5;oL#(sWB7T-1-W7z|lGxS~-zM*bY~u+?fP*M>Ziq%sJbF-s)ySoP`Y_i!t7*2dutj5> zOV`hSs?sIZ4a`D z82JfF-Cj=-3v4;$WoKzubyJ?O(sUD@Q?Z{!ox*(g4aI}MAXqqrR{03Q5#hD9CeP^( z@d$2AbrEk7Yz{pnyvB^pNRZCZR2GT+g(X@H7K8GMDXNC=UP6kn=O=_zyH?v1@{zo142? z=Ds}$>;W*A36Ew|3}`+)=pDjTi|y^;AVfM3%ru0GzPk;6*Kw6BJX0 z_7W&7K(sI=OVRZ(vHZi|{_?sfXCVb;(whZu#<#|Rm=D#H4RSV)=GiL!XQmIa#(WGp ztTv1e=|(yU;*E&zIc^26Ii&2pPIhfSf!8-^&G9j4=%PYb~y>Ey?puthsN1*cEApNhx>^0$i9 zP?KT>k&=IdENH%Oyf04^Q&XF#a)ir!0-VVptdJVMaCK|!f-;3E`Qwu;{Z%go4G-e= zdh?>xd(^frhMXEG?B8o5U31E({v)%DR)`a=AH!}Uo%Q0$!veoy@tn0G{YBhi*3pJ9q; z@oJj+=#Hs3OsG%rfULF`A8(MRW%t6jABI}bERRgL82uej#J)o$SMoiaGsixoPe07}-j742T{one=1i~{%OUGU6E1@}%U^2d9;Wk_fZ^fMuYI%k#yeu*Cw ztl0^SL*1)%>a4Zyl7EptfW+FRqSmai>O5%639XrdjN;4&d@zpb?uph{5xqH4!iH(UsLCw-W;uhLRKh22hz={?N0Wg9S3}({{|K(Yai0lSpU^e3Q=ukO;W{Phc{A_c~-% z49LveK>r8({qD3AAI>36(1>vVnh)z&pGkiTnu0hRSGk=xQGQ0%_L+VJ$`Z)F-kPSP zbx0gK8ZG}#98m-DiQy;-iPXx!5C@+CISlz@{qki0*~P-LV6WamIp3{shk+<8B<)Z{ z5JOlJODMwFx^^fls23x*GVimV|B0_O{ofG>a#))d6+@n6$nh1Z*ee^>Rk|%cY1_CU ze6NfRi;+7DeHs4`;y@&x)0+9IcJ#5?pQ<`=uWOlH&XTdpSEO|TiG?u{F|ewXHs%In zH-xYi-PFsuJ_Skd9EC^}3H)@vWn*N zrPu}jX8#%`+6+HTJQx7GCz6M1)dp;4Q-nr*o`cT51u>WCwm!uD#c>}E%(^BSe)hu% zV_?<4)?8*3qC{Vg51oC4^6m?hPcu7Jw2lh8vi*b#bPq!9xjbdAnmh=DdeyC2xH(^o z`#5z|?i?+%%m;3+%z9rnop+|HxMH;a2qrp{up((#7pV00&J&E>FqU6MznI3nHy1g; z{sstM^dB6=NAt5x53-TL6dMCFVKHxqy|*GV7(FP`~VLMfuLHdhve9%aXU3tDDLYxhoxJAw{P?bFx5W&cL3) z(^KjK)$05yOSPTW#c$nc$x>$_z$(hTa*i)MZ;nEgjc%!)P!--|4yK~!ZufTL;$Ero z!DYpXSyy(hkoZyo39NP#kMLOXSF5ehR}CBZ1|)?i+Eta0R-0ArUw|CA)d7eFzLrz| zT$1-wWutdSGR5N@;zwWLo8!Ht;9rlc2g)Hoe<-~XF}fgfW`bT$lA{2o4bSs@Tta8M zeCAAfcha?Rsg-wC;8n;8nw^P;8#U8rPl5>vqrd&cY|jKs=(ZmwP~_f(ixQ)C-stfB z4J?kj$hCG&K}fv6Ld=ll356v`nge+C?D~hs9{OV?x=cm>R`3|F_<64B^da~7r`}@V zFKj=$%Foah$psCrJg9IsFR1WTgO@FK_77`qdK*3!A|bCY5~?1h+Uod_D%zjbmb3}D zUoo(L-NCt@e*129cVD$rh4;*7R`;N>P+g%|6t~3vZULl;{mcv(Z#C?cUp=Frab9YK zn66imSx#ArCOWj~xDk}D8r;n4J{ZWSA2cNnovvFJxc4Cq8H;ZfD*cjH{xB=*vhy9- zTs+L#vGn_3>G!_0^@deOj>z2hJD*?S=p`unQ{0~RI?G&iW$yZz|D E01_0OMgRZ+ diff --git a/DOCS/html/arm__defines_8h_source.html b/DOCS/html/arm__defines_8h_source.html deleted file mode 100644 index 4d434fe..0000000 --- a/DOCS/html/arm__defines_8h_source.html +++ /dev/null @@ -1,247 +0,0 @@ - - - - - - - -STM MATLAB Simulator: F:/Work/Projects/MATLAB/matlab_stm_emulate/MCU_STM32F4xx_Matlab/Drivers/CMSIS/arm_defines.h Source File - - - - - - - - - - - -
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arm_defines.h
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1#define __disable_irq()
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2
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3#ifndef __ASM
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4 #define __ASM __asm
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5#endif
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6
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7#ifndef __IO
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8 #define __IO volatile
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14#ifndef __INLINE
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18#ifndef __STATIC_INLINE
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19 #define __STATIC_INLINE static __inline
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22#ifndef __STATIC_FORCEINLINE
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27 #define __NO_RETURN __declspec(noreturn)
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30#ifndef __USED
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31 #define __USED __attribute__((used))
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32#endif
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35#ifndef __WEAK
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36 #define __WEAK __declspec(selectany)
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37// #define __weak __WEAK
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38#endif
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40#ifndef __PACKED
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41 #define __PACKED __attribute__((packed))
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42#endif
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44#ifndef __PACKED_STRUCT
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45 #define __PACKED_STRUCT __packed struct
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49 #define __PACKED_UNION __packed union
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52#ifndef __UNALIGNED_UINT32 /* deprecated */
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53 #define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x)))
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54#endif
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56#ifndef __UNALIGNED_UINT16_WRITE
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57 #define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val))
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60#ifndef __UNALIGNED_UINT16_READ
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61 #define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr)))
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64#ifndef __UNALIGNED_UINT32_WRITE
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65 #define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val))
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68#ifndef __UNALIGNED_UINT32_READ
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69 #define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr)))
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70#endif
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72#ifndef __ALIGNED
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73 #define __ALIGNED(x) __attribute__((aligned(x)))
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74#endif
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76#ifndef __RESTRICT
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77 #define __RESTRICT __restrict
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78#endif
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79
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80#ifndef __weak
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81 #define __weak
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82#endif
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83//#define __ASM()
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84//#define __DSB()
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85//#define __ISB()
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86//#define __NOP()
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87//#define __WFI()
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88//#define __SEV()
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241#define __STREXB(value, ptr) (*(volatile uint8_t *)(ptr) = (value), 0)
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252#define __STREXH(value, ptr) (*(volatile uint16_t *)(ptr) = (value), 0)
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Data Structure Index
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CAN_TypeDef
Channels_Sim
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CoreDebug_Type
CRC_TypeDef
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DBGMCU_TypeDef
DCMI_TypeDef
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DMA_TypeDef
DWT_Type
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Channels_Sim
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EXTI_TypeDef
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SCnSCB_Type
SDIO_TypeDef
SIM__MCUHandleTypeDef
SlaveChannels
SPI_TypeDef
SYSCFG_TypeDef
SysTick_Type
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SlaveChannels
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TIM_TypeDef
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_cortex_memory
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diff --git a/DOCS/html/core__cm4__matlab_8h.html b/DOCS/html/core__cm4__matlab_8h.html deleted file mode 100644 index 9c8ab13..0000000 --- a/DOCS/html/core__cm4__matlab_8h.html +++ /dev/null @@ -1,1426 +0,0 @@ - - - - - - - -STM MATLAB Simulator: F:/Work/Projects/MATLAB/matlab_stm_emulate/MCU_STM32F4xx_Matlab/Drivers/CMSIS/core_cm4_matlab.h File Reference - - - - - - - - - - - -
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Go to the source code of this file.

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-Data Structures

union  APSR_Type
 Union type to access the Application Program Status Register (APSR). More...
 
union  IPSR_Type
 Union type to access the Interrupt Program Status Register (IPSR). More...
 
union  xPSR_Type
 Union type to access the Special-Purpose Program Status Registers (xPSR). More...
 
union  CONTROL_Type
 Union type to access the Control Registers (CONTROL). More...
 
struct  NVIC_Type
 Structure type to access the Nested Vectored Interrupt Controller (NVIC). More...
 
struct  SCB_Type
 Structure type to access the System Control Block (SCB). More...
 
struct  SCnSCB_Type
 Structure type to access the System Control and ID Register not in the SCB. More...
 
struct  SysTick_Type
 Structure type to access the System Timer (SysTick). More...
 
struct  ITM_Type
 Structure type to access the Instrumentation Trace Macrocell Register (ITM). More...
 
struct  DWT_Type
 Structure type to access the Data Watchpoint and Trace Register (DWT). More...
 
struct  TPI_Type
 Structure type to access the Trace Port Interface Register (TPI). More...
 
struct  FPU_Type
 Structure type to access the Floating Point Unit (FPU). More...
 
struct  CoreDebug_Type
 Structure type to access the Core Debug Register (CoreDebug). More...
 
struct  _cortex_memory
 
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-Macros

#define __I   volatile const
 
#define __O   volatile
 
#define __IO   volatile
 
#define __IM   volatile const /*! Defines 'read only' structure member permissions */
 
#define __OM   volatile /*! Defines 'write only' structure member permissions */
 
#define __IOM   volatile /*! Defines 'read / write' structure member permissions */
 
#define APSR_N_Pos   31U
 
#define APSR_N_Msk   (1UL << APSR_N_Pos)
 
#define APSR_Z_Pos   30U
 
#define APSR_Z_Msk   (1UL << APSR_Z_Pos)
 
#define APSR_C_Pos   29U
 
#define APSR_C_Msk   (1UL << APSR_C_Pos)
 
#define APSR_V_Pos   28U
 
#define APSR_V_Msk   (1UL << APSR_V_Pos)
 
#define APSR_Q_Pos   27U
 
#define APSR_Q_Msk   (1UL << APSR_Q_Pos)
 
#define APSR_GE_Pos   16U
 
#define APSR_GE_Msk   (0xFUL << APSR_GE_Pos)
 
#define IPSR_ISR_Pos   0U
 
#define IPSR_ISR_Msk   (0x1FFUL /*<< IPSR_ISR_Pos*/)
 
#define xPSR_N_Pos   31U
 
#define xPSR_N_Msk   (1UL << xPSR_N_Pos)
 
#define xPSR_Z_Pos   30U
 
#define xPSR_Z_Msk   (1UL << xPSR_Z_Pos)
 
#define xPSR_C_Pos   29U
 
#define xPSR_C_Msk   (1UL << xPSR_C_Pos)
 
#define xPSR_V_Pos   28U
 
#define xPSR_V_Msk   (1UL << xPSR_V_Pos)
 
#define xPSR_Q_Pos   27U
 
#define xPSR_Q_Msk   (1UL << xPSR_Q_Pos)
 
#define xPSR_ICI_IT_2_Pos   25U
 
#define xPSR_ICI_IT_2_Msk   (3UL << xPSR_ICI_IT_2_Pos)
 
#define xPSR_T_Pos   24U
 
#define xPSR_T_Msk   (1UL << xPSR_T_Pos)
 
#define xPSR_GE_Pos   16U
 
#define xPSR_GE_Msk   (0xFUL << xPSR_GE_Pos)
 
#define xPSR_ICI_IT_1_Pos   10U
 
#define xPSR_ICI_IT_1_Msk   (0x3FUL << xPSR_ICI_IT_1_Pos)
 
#define xPSR_ISR_Pos   0U
 
#define xPSR_ISR_Msk   (0x1FFUL /*<< xPSR_ISR_Pos*/)
 
#define CONTROL_FPCA_Pos   2U
 
#define CONTROL_FPCA_Msk   (1UL << CONTROL_FPCA_Pos)
 
#define CONTROL_SPSEL_Pos   1U
 
#define CONTROL_SPSEL_Msk   (1UL << CONTROL_SPSEL_Pos)
 
#define CONTROL_nPRIV_Pos   0U
 
#define CONTROL_nPRIV_Msk   (1UL /*<< CONTROL_nPRIV_Pos*/)
 
#define NVIC_STIR_INTID_Pos   0U
 
#define NVIC_STIR_INTID_Msk   (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)
 
#define SCB_CPUID_IMPLEMENTER_Pos   24U
 
#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
 
#define SCB_CPUID_VARIANT_Pos   20U
 
#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)
 
#define SCB_CPUID_ARCHITECTURE_Pos   16U
 
#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
 
#define SCB_CPUID_PARTNO_Pos   4U
 
#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)
 
#define SCB_CPUID_REVISION_Pos   0U
 
#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)
 
#define SCB_ICSR_NMIPENDSET_Pos   31U
 
#define SCB_ICSR_NMIPENDSET_Msk   (1UL << SCB_ICSR_NMIPENDSET_Pos)
 
#define SCB_ICSR_PENDSVSET_Pos   28U
 
#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)
 
#define SCB_ICSR_PENDSVCLR_Pos   27U
 
#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)
 
#define SCB_ICSR_PENDSTSET_Pos   26U
 
#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)
 
#define SCB_ICSR_PENDSTCLR_Pos   25U
 
#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)
 
#define SCB_ICSR_ISRPREEMPT_Pos   23U
 
#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)
 
#define SCB_ICSR_ISRPENDING_Pos   22U
 
#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)
 
#define SCB_ICSR_VECTPENDING_Pos   12U
 
#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
 
#define SCB_ICSR_RETTOBASE_Pos   11U
 
#define SCB_ICSR_RETTOBASE_Msk   (1UL << SCB_ICSR_RETTOBASE_Pos)
 
#define SCB_ICSR_VECTACTIVE_Pos   0U
 
#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)
 
#define SCB_VTOR_TBLOFF_Pos   7U
 
#define SCB_VTOR_TBLOFF_Msk   (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)
 
#define SCB_AIRCR_VECTKEY_Pos   16U
 
#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
 
#define SCB_AIRCR_VECTKEYSTAT_Pos   16U
 
#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
 
#define SCB_AIRCR_ENDIANESS_Pos   15U
 
#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)
 
#define SCB_AIRCR_PRIGROUP_Pos   8U
 
#define SCB_AIRCR_PRIGROUP_Msk   (7UL << SCB_AIRCR_PRIGROUP_Pos)
 
#define SCB_AIRCR_SYSRESETREQ_Pos   2U
 
#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
 
#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U
 
#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
 
#define SCB_AIRCR_VECTRESET_Pos   0U
 
#define SCB_AIRCR_VECTRESET_Msk   (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)
 
#define SCB_SCR_SEVONPEND_Pos   4U
 
#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)
 
#define SCB_SCR_SLEEPDEEP_Pos   2U
 
#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)
 
#define SCB_SCR_SLEEPONEXIT_Pos   1U
 
#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)
 
#define SCB_CCR_STKALIGN_Pos   9U
 
#define SCB_CCR_STKALIGN_Msk   (1UL << SCB_CCR_STKALIGN_Pos)
 
#define SCB_CCR_BFHFNMIGN_Pos   8U
 
#define SCB_CCR_BFHFNMIGN_Msk   (1UL << SCB_CCR_BFHFNMIGN_Pos)
 
#define SCB_CCR_DIV_0_TRP_Pos   4U
 
#define SCB_CCR_DIV_0_TRP_Msk   (1UL << SCB_CCR_DIV_0_TRP_Pos)
 
#define SCB_CCR_UNALIGN_TRP_Pos   3U
 
#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)
 
#define SCB_CCR_USERSETMPEND_Pos   1U
 
#define SCB_CCR_USERSETMPEND_Msk   (1UL << SCB_CCR_USERSETMPEND_Pos)
 
#define SCB_CCR_NONBASETHRDENA_Pos   0U
 
#define SCB_CCR_NONBASETHRDENA_Msk   (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)
 
#define SCB_SHCSR_USGFAULTENA_Pos   18U
 
#define SCB_SHCSR_USGFAULTENA_Msk   (1UL << SCB_SHCSR_USGFAULTENA_Pos)
 
#define SCB_SHCSR_BUSFAULTENA_Pos   17U
 
#define SCB_SHCSR_BUSFAULTENA_Msk   (1UL << SCB_SHCSR_BUSFAULTENA_Pos)
 
#define SCB_SHCSR_MEMFAULTENA_Pos   16U
 
#define SCB_SHCSR_MEMFAULTENA_Msk   (1UL << SCB_SHCSR_MEMFAULTENA_Pos)
 
#define SCB_SHCSR_SVCALLPENDED_Pos   15U
 
#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
 
#define SCB_SHCSR_BUSFAULTPENDED_Pos   14U
 
#define SCB_SHCSR_BUSFAULTPENDED_Msk   (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)
 
#define SCB_SHCSR_MEMFAULTPENDED_Pos   13U
 
#define SCB_SHCSR_MEMFAULTPENDED_Msk   (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)
 
#define SCB_SHCSR_USGFAULTPENDED_Pos   12U
 
#define SCB_SHCSR_USGFAULTPENDED_Msk   (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)
 
#define SCB_SHCSR_SYSTICKACT_Pos   11U
 
#define SCB_SHCSR_SYSTICKACT_Msk   (1UL << SCB_SHCSR_SYSTICKACT_Pos)
 
#define SCB_SHCSR_PENDSVACT_Pos   10U
 
#define SCB_SHCSR_PENDSVACT_Msk   (1UL << SCB_SHCSR_PENDSVACT_Pos)
 
#define SCB_SHCSR_MONITORACT_Pos   8U
 
#define SCB_SHCSR_MONITORACT_Msk   (1UL << SCB_SHCSR_MONITORACT_Pos)
 
#define SCB_SHCSR_SVCALLACT_Pos   7U
 
#define SCB_SHCSR_SVCALLACT_Msk   (1UL << SCB_SHCSR_SVCALLACT_Pos)
 
#define SCB_SHCSR_USGFAULTACT_Pos   3U
 
#define SCB_SHCSR_USGFAULTACT_Msk   (1UL << SCB_SHCSR_USGFAULTACT_Pos)
 
#define SCB_SHCSR_BUSFAULTACT_Pos   1U
 
#define SCB_SHCSR_BUSFAULTACT_Msk   (1UL << SCB_SHCSR_BUSFAULTACT_Pos)
 
#define SCB_SHCSR_MEMFAULTACT_Pos   0U
 
#define SCB_SHCSR_MEMFAULTACT_Msk   (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)
 
#define SCB_CFSR_USGFAULTSR_Pos   16U
 
#define SCB_CFSR_USGFAULTSR_Msk   (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)
 
#define SCB_CFSR_BUSFAULTSR_Pos   8U
 
#define SCB_CFSR_BUSFAULTSR_Msk   (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)
 
#define SCB_CFSR_MEMFAULTSR_Pos   0U
 
#define SCB_CFSR_MEMFAULTSR_Msk   (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)
 
#define SCB_CFSR_MMARVALID_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 7U)
 
#define SCB_CFSR_MMARVALID_Msk   (1UL << SCB_CFSR_MMARVALID_Pos)
 
#define SCB_CFSR_MLSPERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 5U)
 
#define SCB_CFSR_MLSPERR_Msk   (1UL << SCB_CFSR_MLSPERR_Pos)
 
#define SCB_CFSR_MSTKERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 4U)
 
#define SCB_CFSR_MSTKERR_Msk   (1UL << SCB_CFSR_MSTKERR_Pos)
 
#define SCB_CFSR_MUNSTKERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 3U)
 
#define SCB_CFSR_MUNSTKERR_Msk   (1UL << SCB_CFSR_MUNSTKERR_Pos)
 
#define SCB_CFSR_DACCVIOL_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 1U)
 
#define SCB_CFSR_DACCVIOL_Msk   (1UL << SCB_CFSR_DACCVIOL_Pos)
 
#define SCB_CFSR_IACCVIOL_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 0U)
 
#define SCB_CFSR_IACCVIOL_Msk   (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)
 
#define SCB_CFSR_BFARVALID_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 7U)
 
#define SCB_CFSR_BFARVALID_Msk   (1UL << SCB_CFSR_BFARVALID_Pos)
 
#define SCB_CFSR_LSPERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 5U)
 
#define SCB_CFSR_LSPERR_Msk   (1UL << SCB_CFSR_LSPERR_Pos)
 
#define SCB_CFSR_STKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 4U)
 
#define SCB_CFSR_STKERR_Msk   (1UL << SCB_CFSR_STKERR_Pos)
 
#define SCB_CFSR_UNSTKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 3U)
 
#define SCB_CFSR_UNSTKERR_Msk   (1UL << SCB_CFSR_UNSTKERR_Pos)
 
#define SCB_CFSR_IMPRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 2U)
 
#define SCB_CFSR_IMPRECISERR_Msk   (1UL << SCB_CFSR_IMPRECISERR_Pos)
 
#define SCB_CFSR_PRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 1U)
 
#define SCB_CFSR_PRECISERR_Msk   (1UL << SCB_CFSR_PRECISERR_Pos)
 
#define SCB_CFSR_IBUSERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 0U)
 
#define SCB_CFSR_IBUSERR_Msk   (1UL << SCB_CFSR_IBUSERR_Pos)
 
#define SCB_CFSR_DIVBYZERO_Pos   (SCB_CFSR_USGFAULTSR_Pos + 9U)
 
#define SCB_CFSR_DIVBYZERO_Msk   (1UL << SCB_CFSR_DIVBYZERO_Pos)
 
#define SCB_CFSR_UNALIGNED_Pos   (SCB_CFSR_USGFAULTSR_Pos + 8U)
 
#define SCB_CFSR_UNALIGNED_Msk   (1UL << SCB_CFSR_UNALIGNED_Pos)
 
#define SCB_CFSR_NOCP_Pos   (SCB_CFSR_USGFAULTSR_Pos + 3U)
 
#define SCB_CFSR_NOCP_Msk   (1UL << SCB_CFSR_NOCP_Pos)
 
#define SCB_CFSR_INVPC_Pos   (SCB_CFSR_USGFAULTSR_Pos + 2U)
 
#define SCB_CFSR_INVPC_Msk   (1UL << SCB_CFSR_INVPC_Pos)
 
#define SCB_CFSR_INVSTATE_Pos   (SCB_CFSR_USGFAULTSR_Pos + 1U)
 
#define SCB_CFSR_INVSTATE_Msk   (1UL << SCB_CFSR_INVSTATE_Pos)
 
#define SCB_CFSR_UNDEFINSTR_Pos   (SCB_CFSR_USGFAULTSR_Pos + 0U)
 
#define SCB_CFSR_UNDEFINSTR_Msk   (1UL << SCB_CFSR_UNDEFINSTR_Pos)
 
#define SCB_HFSR_DEBUGEVT_Pos   31U
 
#define SCB_HFSR_DEBUGEVT_Msk   (1UL << SCB_HFSR_DEBUGEVT_Pos)
 
#define SCB_HFSR_FORCED_Pos   30U
 
#define SCB_HFSR_FORCED_Msk   (1UL << SCB_HFSR_FORCED_Pos)
 
#define SCB_HFSR_VECTTBL_Pos   1U
 
#define SCB_HFSR_VECTTBL_Msk   (1UL << SCB_HFSR_VECTTBL_Pos)
 
#define SCB_DFSR_EXTERNAL_Pos   4U
 
#define SCB_DFSR_EXTERNAL_Msk   (1UL << SCB_DFSR_EXTERNAL_Pos)
 
#define SCB_DFSR_VCATCH_Pos   3U
 
#define SCB_DFSR_VCATCH_Msk   (1UL << SCB_DFSR_VCATCH_Pos)
 
#define SCB_DFSR_DWTTRAP_Pos   2U
 
#define SCB_DFSR_DWTTRAP_Msk   (1UL << SCB_DFSR_DWTTRAP_Pos)
 
#define SCB_DFSR_BKPT_Pos   1U
 
#define SCB_DFSR_BKPT_Msk   (1UL << SCB_DFSR_BKPT_Pos)
 
#define SCB_DFSR_HALTED_Pos   0U
 
#define SCB_DFSR_HALTED_Msk   (1UL /*<< SCB_DFSR_HALTED_Pos*/)
 
#define SCnSCB_ICTR_INTLINESNUM_Pos   0U
 
#define SCnSCB_ICTR_INTLINESNUM_Msk   (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)
 
#define SCnSCB_ACTLR_DISOOFP_Pos   9U
 
#define SCnSCB_ACTLR_DISOOFP_Msk   (1UL << SCnSCB_ACTLR_DISOOFP_Pos)
 
#define SCnSCB_ACTLR_DISFPCA_Pos   8U
 
#define SCnSCB_ACTLR_DISFPCA_Msk   (1UL << SCnSCB_ACTLR_DISFPCA_Pos)
 
#define SCnSCB_ACTLR_DISFOLD_Pos   2U
 
#define SCnSCB_ACTLR_DISFOLD_Msk   (1UL << SCnSCB_ACTLR_DISFOLD_Pos)
 
#define SCnSCB_ACTLR_DISDEFWBUF_Pos   1U
 
#define SCnSCB_ACTLR_DISDEFWBUF_Msk   (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)
 
#define SCnSCB_ACTLR_DISMCYCINT_Pos   0U
 
#define SCnSCB_ACTLR_DISMCYCINT_Msk   (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)
 
#define SysTick_CTRL_COUNTFLAG_Pos   16U
 
#define SysTick_CTRL_COUNTFLAG_Msk   (1UL << SysTick_CTRL_COUNTFLAG_Pos)
 
#define SysTick_CTRL_CLKSOURCE_Pos   2U
 
#define SysTick_CTRL_CLKSOURCE_Msk   (1UL << SysTick_CTRL_CLKSOURCE_Pos)
 
#define SysTick_CTRL_TICKINT_Pos   1U
 
#define SysTick_CTRL_TICKINT_Msk   (1UL << SysTick_CTRL_TICKINT_Pos)
 
#define SysTick_CTRL_ENABLE_Pos   0U
 
#define SysTick_CTRL_ENABLE_Msk   (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)
 
#define SysTick_LOAD_RELOAD_Pos   0U
 
#define SysTick_LOAD_RELOAD_Msk   (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)
 
#define SysTick_VAL_CURRENT_Pos   0U
 
#define SysTick_VAL_CURRENT_Msk   (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)
 
#define SysTick_CALIB_NOREF_Pos   31U
 
#define SysTick_CALIB_NOREF_Msk   (1UL << SysTick_CALIB_NOREF_Pos)
 
#define SysTick_CALIB_SKEW_Pos   30U
 
#define SysTick_CALIB_SKEW_Msk   (1UL << SysTick_CALIB_SKEW_Pos)
 
#define SysTick_CALIB_TENMS_Pos   0U
 
#define SysTick_CALIB_TENMS_Msk   (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)
 
#define ITM_TPR_PRIVMASK_Pos   0U
 
#define ITM_TPR_PRIVMASK_Msk   (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/)
 
#define ITM_TCR_BUSY_Pos   23U
 
#define ITM_TCR_BUSY_Msk   (1UL << ITM_TCR_BUSY_Pos)
 
#define ITM_TCR_TraceBusID_Pos   16U
 
#define ITM_TCR_TraceBusID_Msk   (0x7FUL << ITM_TCR_TraceBusID_Pos)
 
#define ITM_TCR_GTSFREQ_Pos   10U
 
#define ITM_TCR_GTSFREQ_Msk   (3UL << ITM_TCR_GTSFREQ_Pos)
 
#define ITM_TCR_TSPrescale_Pos   8U
 
#define ITM_TCR_TSPrescale_Msk   (3UL << ITM_TCR_TSPrescale_Pos)
 
#define ITM_TCR_SWOENA_Pos   4U
 
#define ITM_TCR_SWOENA_Msk   (1UL << ITM_TCR_SWOENA_Pos)
 
#define ITM_TCR_DWTENA_Pos   3U
 
#define ITM_TCR_DWTENA_Msk   (1UL << ITM_TCR_DWTENA_Pos)
 
#define ITM_TCR_SYNCENA_Pos   2U
 
#define ITM_TCR_SYNCENA_Msk   (1UL << ITM_TCR_SYNCENA_Pos)
 
#define ITM_TCR_TSENA_Pos   1U
 
#define ITM_TCR_TSENA_Msk   (1UL << ITM_TCR_TSENA_Pos)
 
#define ITM_TCR_ITMENA_Pos   0U
 
#define ITM_TCR_ITMENA_Msk   (1UL /*<< ITM_TCR_ITMENA_Pos*/)
 
#define ITM_IWR_ATVALIDM_Pos   0U
 
#define ITM_IWR_ATVALIDM_Msk   (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)
 
#define ITM_IRR_ATREADYM_Pos   0U
 
#define ITM_IRR_ATREADYM_Msk   (1UL /*<< ITM_IRR_ATREADYM_Pos*/)
 
#define ITM_IMCR_INTEGRATION_Pos   0U
 
#define ITM_IMCR_INTEGRATION_Msk   (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)
 
#define ITM_LSR_ByteAcc_Pos   2U
 
#define ITM_LSR_ByteAcc_Msk   (1UL << ITM_LSR_ByteAcc_Pos)
 
#define ITM_LSR_Access_Pos   1U
 
#define ITM_LSR_Access_Msk   (1UL << ITM_LSR_Access_Pos)
 
#define ITM_LSR_Present_Pos   0U
 
#define ITM_LSR_Present_Msk   (1UL /*<< ITM_LSR_Present_Pos*/)
 
#define DWT_CTRL_NUMCOMP_Pos   28U
 
#define DWT_CTRL_NUMCOMP_Msk   (0xFUL << DWT_CTRL_NUMCOMP_Pos)
 
#define DWT_CTRL_NOTRCPKT_Pos   27U
 
#define DWT_CTRL_NOTRCPKT_Msk   (0x1UL << DWT_CTRL_NOTRCPKT_Pos)
 
#define DWT_CTRL_NOEXTTRIG_Pos   26U
 
#define DWT_CTRL_NOEXTTRIG_Msk   (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)
 
#define DWT_CTRL_NOCYCCNT_Pos   25U
 
#define DWT_CTRL_NOCYCCNT_Msk   (0x1UL << DWT_CTRL_NOCYCCNT_Pos)
 
#define DWT_CTRL_NOPRFCNT_Pos   24U
 
#define DWT_CTRL_NOPRFCNT_Msk   (0x1UL << DWT_CTRL_NOPRFCNT_Pos)
 
#define DWT_CTRL_CYCEVTENA_Pos   22U
 
#define DWT_CTRL_CYCEVTENA_Msk   (0x1UL << DWT_CTRL_CYCEVTENA_Pos)
 
#define DWT_CTRL_FOLDEVTENA_Pos   21U
 
#define DWT_CTRL_FOLDEVTENA_Msk   (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)
 
#define DWT_CTRL_LSUEVTENA_Pos   20U
 
#define DWT_CTRL_LSUEVTENA_Msk   (0x1UL << DWT_CTRL_LSUEVTENA_Pos)
 
#define DWT_CTRL_SLEEPEVTENA_Pos   19U
 
#define DWT_CTRL_SLEEPEVTENA_Msk   (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)
 
#define DWT_CTRL_EXCEVTENA_Pos   18U
 
#define DWT_CTRL_EXCEVTENA_Msk   (0x1UL << DWT_CTRL_EXCEVTENA_Pos)
 
#define DWT_CTRL_CPIEVTENA_Pos   17U
 
#define DWT_CTRL_CPIEVTENA_Msk   (0x1UL << DWT_CTRL_CPIEVTENA_Pos)
 
#define DWT_CTRL_EXCTRCENA_Pos   16U
 
#define DWT_CTRL_EXCTRCENA_Msk   (0x1UL << DWT_CTRL_EXCTRCENA_Pos)
 
#define DWT_CTRL_PCSAMPLENA_Pos   12U
 
#define DWT_CTRL_PCSAMPLENA_Msk   (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)
 
#define DWT_CTRL_SYNCTAP_Pos   10U
 
#define DWT_CTRL_SYNCTAP_Msk   (0x3UL << DWT_CTRL_SYNCTAP_Pos)
 
#define DWT_CTRL_CYCTAP_Pos   9U
 
#define DWT_CTRL_CYCTAP_Msk   (0x1UL << DWT_CTRL_CYCTAP_Pos)
 
#define DWT_CTRL_POSTINIT_Pos   5U
 
#define DWT_CTRL_POSTINIT_Msk   (0xFUL << DWT_CTRL_POSTINIT_Pos)
 
#define DWT_CTRL_POSTPRESET_Pos   1U
 
#define DWT_CTRL_POSTPRESET_Msk   (0xFUL << DWT_CTRL_POSTPRESET_Pos)
 
#define DWT_CTRL_CYCCNTENA_Pos   0U
 
#define DWT_CTRL_CYCCNTENA_Msk   (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)
 
#define DWT_CPICNT_CPICNT_Pos   0U
 
#define DWT_CPICNT_CPICNT_Msk   (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)
 
#define DWT_EXCCNT_EXCCNT_Pos   0U
 
#define DWT_EXCCNT_EXCCNT_Msk   (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)
 
#define DWT_SLEEPCNT_SLEEPCNT_Pos   0U
 
#define DWT_SLEEPCNT_SLEEPCNT_Msk   (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)
 
#define DWT_LSUCNT_LSUCNT_Pos   0U
 
#define DWT_LSUCNT_LSUCNT_Msk   (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)
 
#define DWT_FOLDCNT_FOLDCNT_Pos   0U
 
#define DWT_FOLDCNT_FOLDCNT_Msk   (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)
 
#define DWT_MASK_MASK_Pos   0U
 
#define DWT_MASK_MASK_Msk   (0x1FUL /*<< DWT_MASK_MASK_Pos*/)
 
#define DWT_FUNCTION_MATCHED_Pos   24U
 
#define DWT_FUNCTION_MATCHED_Msk   (0x1UL << DWT_FUNCTION_MATCHED_Pos)
 
#define DWT_FUNCTION_DATAVADDR1_Pos   16U
 
#define DWT_FUNCTION_DATAVADDR1_Msk   (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)
 
#define DWT_FUNCTION_DATAVADDR0_Pos   12U
 
#define DWT_FUNCTION_DATAVADDR0_Msk   (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)
 
#define DWT_FUNCTION_DATAVSIZE_Pos   10U
 
#define DWT_FUNCTION_DATAVSIZE_Msk   (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)
 
#define DWT_FUNCTION_LNK1ENA_Pos   9U
 
#define DWT_FUNCTION_LNK1ENA_Msk   (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)
 
#define DWT_FUNCTION_DATAVMATCH_Pos   8U
 
#define DWT_FUNCTION_DATAVMATCH_Msk   (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)
 
#define DWT_FUNCTION_CYCMATCH_Pos   7U
 
#define DWT_FUNCTION_CYCMATCH_Msk   (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)
 
#define DWT_FUNCTION_EMITRANGE_Pos   5U
 
#define DWT_FUNCTION_EMITRANGE_Msk   (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)
 
#define DWT_FUNCTION_FUNCTION_Pos   0U
 
#define DWT_FUNCTION_FUNCTION_Msk   (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)
 
#define TPI_ACPR_PRESCALER_Pos   0U
 
#define TPI_ACPR_PRESCALER_Msk   (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)
 
#define TPI_SPPR_TXMODE_Pos   0U
 
#define TPI_SPPR_TXMODE_Msk   (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)
 
#define TPI_FFSR_FtNonStop_Pos   3U
 
#define TPI_FFSR_FtNonStop_Msk   (0x1UL << TPI_FFSR_FtNonStop_Pos)
 
#define TPI_FFSR_TCPresent_Pos   2U
 
#define TPI_FFSR_TCPresent_Msk   (0x1UL << TPI_FFSR_TCPresent_Pos)
 
#define TPI_FFSR_FtStopped_Pos   1U
 
#define TPI_FFSR_FtStopped_Msk   (0x1UL << TPI_FFSR_FtStopped_Pos)
 
#define TPI_FFSR_FlInProg_Pos   0U
 
#define TPI_FFSR_FlInProg_Msk   (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)
 
#define TPI_FFCR_TrigIn_Pos   8U
 
#define TPI_FFCR_TrigIn_Msk   (0x1UL << TPI_FFCR_TrigIn_Pos)
 
#define TPI_FFCR_EnFCont_Pos   1U
 
#define TPI_FFCR_EnFCont_Msk   (0x1UL << TPI_FFCR_EnFCont_Pos)
 
#define TPI_TRIGGER_TRIGGER_Pos   0U
 
#define TPI_TRIGGER_TRIGGER_Msk   (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)
 
#define TPI_FIFO0_ITM_ATVALID_Pos   29U
 
#define TPI_FIFO0_ITM_ATVALID_Msk   (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)
 
#define TPI_FIFO0_ITM_bytecount_Pos   27U
 
#define TPI_FIFO0_ITM_bytecount_Msk   (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)
 
#define TPI_FIFO0_ETM_ATVALID_Pos   26U
 
#define TPI_FIFO0_ETM_ATVALID_Msk   (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)
 
#define TPI_FIFO0_ETM_bytecount_Pos   24U
 
#define TPI_FIFO0_ETM_bytecount_Msk   (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)
 
#define TPI_FIFO0_ETM2_Pos   16U
 
#define TPI_FIFO0_ETM2_Msk   (0xFFUL << TPI_FIFO0_ETM2_Pos)
 
#define TPI_FIFO0_ETM1_Pos   8U
 
#define TPI_FIFO0_ETM1_Msk   (0xFFUL << TPI_FIFO0_ETM1_Pos)
 
#define TPI_FIFO0_ETM0_Pos   0U
 
#define TPI_FIFO0_ETM0_Msk   (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)
 
#define TPI_ITATBCTR2_ATREADY2_Pos   0U
 
#define TPI_ITATBCTR2_ATREADY2_Msk   (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/)
 
#define TPI_ITATBCTR2_ATREADY1_Pos   0U
 
#define TPI_ITATBCTR2_ATREADY1_Msk   (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/)
 
#define TPI_FIFO1_ITM_ATVALID_Pos   29U
 
#define TPI_FIFO1_ITM_ATVALID_Msk   (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)
 
#define TPI_FIFO1_ITM_bytecount_Pos   27U
 
#define TPI_FIFO1_ITM_bytecount_Msk   (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)
 
#define TPI_FIFO1_ETM_ATVALID_Pos   26U
 
#define TPI_FIFO1_ETM_ATVALID_Msk   (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)
 
#define TPI_FIFO1_ETM_bytecount_Pos   24U
 
#define TPI_FIFO1_ETM_bytecount_Msk   (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)
 
#define TPI_FIFO1_ITM2_Pos   16U
 
#define TPI_FIFO1_ITM2_Msk   (0xFFUL << TPI_FIFO1_ITM2_Pos)
 
#define TPI_FIFO1_ITM1_Pos   8U
 
#define TPI_FIFO1_ITM1_Msk   (0xFFUL << TPI_FIFO1_ITM1_Pos)
 
#define TPI_FIFO1_ITM0_Pos   0U
 
#define TPI_FIFO1_ITM0_Msk   (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)
 
#define TPI_ITATBCTR0_ATREADY2_Pos   0U
 
#define TPI_ITATBCTR0_ATREADY2_Msk   (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/)
 
#define TPI_ITATBCTR0_ATREADY1_Pos   0U
 
#define TPI_ITATBCTR0_ATREADY1_Msk   (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/)
 
#define TPI_ITCTRL_Mode_Pos   0U
 
#define TPI_ITCTRL_Mode_Msk   (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/)
 
#define TPI_DEVID_NRZVALID_Pos   11U
 
#define TPI_DEVID_NRZVALID_Msk   (0x1UL << TPI_DEVID_NRZVALID_Pos)
 
#define TPI_DEVID_MANCVALID_Pos   10U
 
#define TPI_DEVID_MANCVALID_Msk   (0x1UL << TPI_DEVID_MANCVALID_Pos)
 
#define TPI_DEVID_PTINVALID_Pos   9U
 
#define TPI_DEVID_PTINVALID_Msk   (0x1UL << TPI_DEVID_PTINVALID_Pos)
 
#define TPI_DEVID_MinBufSz_Pos   6U
 
#define TPI_DEVID_MinBufSz_Msk   (0x7UL << TPI_DEVID_MinBufSz_Pos)
 
#define TPI_DEVID_AsynClkIn_Pos   5U
 
#define TPI_DEVID_AsynClkIn_Msk   (0x1UL << TPI_DEVID_AsynClkIn_Pos)
 
#define TPI_DEVID_NrTraceInput_Pos   0U
 
#define TPI_DEVID_NrTraceInput_Msk   (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)
 
#define TPI_DEVTYPE_SubType_Pos   4U
 
#define TPI_DEVTYPE_SubType_Msk   (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)
 
#define TPI_DEVTYPE_MajorType_Pos   0U
 
#define TPI_DEVTYPE_MajorType_Msk   (0xFUL << TPI_DEVTYPE_MajorType_Pos)
 
#define FPU_FPCCR_ASPEN_Pos   31U
 
#define FPU_FPCCR_ASPEN_Msk   (1UL << FPU_FPCCR_ASPEN_Pos)
 
#define FPU_FPCCR_LSPEN_Pos   30U
 
#define FPU_FPCCR_LSPEN_Msk   (1UL << FPU_FPCCR_LSPEN_Pos)
 
#define FPU_FPCCR_MONRDY_Pos   8U
 
#define FPU_FPCCR_MONRDY_Msk   (1UL << FPU_FPCCR_MONRDY_Pos)
 
#define FPU_FPCCR_BFRDY_Pos   6U
 
#define FPU_FPCCR_BFRDY_Msk   (1UL << FPU_FPCCR_BFRDY_Pos)
 
#define FPU_FPCCR_MMRDY_Pos   5U
 
#define FPU_FPCCR_MMRDY_Msk   (1UL << FPU_FPCCR_MMRDY_Pos)
 
#define FPU_FPCCR_HFRDY_Pos   4U
 
#define FPU_FPCCR_HFRDY_Msk   (1UL << FPU_FPCCR_HFRDY_Pos)
 
#define FPU_FPCCR_THREAD_Pos   3U
 
#define FPU_FPCCR_THREAD_Msk   (1UL << FPU_FPCCR_THREAD_Pos)
 
#define FPU_FPCCR_USER_Pos   1U
 
#define FPU_FPCCR_USER_Msk   (1UL << FPU_FPCCR_USER_Pos)
 
#define FPU_FPCCR_LSPACT_Pos   0U
 
#define FPU_FPCCR_LSPACT_Msk   (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)
 
#define FPU_FPCAR_ADDRESS_Pos   3U
 
#define FPU_FPCAR_ADDRESS_Msk   (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)
 
#define FPU_FPDSCR_AHP_Pos   26U
 
#define FPU_FPDSCR_AHP_Msk   (1UL << FPU_FPDSCR_AHP_Pos)
 
#define FPU_FPDSCR_DN_Pos   25U
 
#define FPU_FPDSCR_DN_Msk   (1UL << FPU_FPDSCR_DN_Pos)
 
#define FPU_FPDSCR_FZ_Pos   24U
 
#define FPU_FPDSCR_FZ_Msk   (1UL << FPU_FPDSCR_FZ_Pos)
 
#define FPU_FPDSCR_RMode_Pos   22U
 
#define FPU_FPDSCR_RMode_Msk   (3UL << FPU_FPDSCR_RMode_Pos)
 
#define FPU_MVFR0_FP_rounding_modes_Pos   28U
 
#define FPU_MVFR0_FP_rounding_modes_Msk   (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)
 
#define FPU_MVFR0_Short_vectors_Pos   24U
 
#define FPU_MVFR0_Short_vectors_Msk   (0xFUL << FPU_MVFR0_Short_vectors_Pos)
 
#define FPU_MVFR0_Square_root_Pos   20U
 
#define FPU_MVFR0_Square_root_Msk   (0xFUL << FPU_MVFR0_Square_root_Pos)
 
#define FPU_MVFR0_Divide_Pos   16U
 
#define FPU_MVFR0_Divide_Msk   (0xFUL << FPU_MVFR0_Divide_Pos)
 
#define FPU_MVFR0_FP_excep_trapping_Pos   12U
 
#define FPU_MVFR0_FP_excep_trapping_Msk   (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)
 
#define FPU_MVFR0_Double_precision_Pos   8U
 
#define FPU_MVFR0_Double_precision_Msk   (0xFUL << FPU_MVFR0_Double_precision_Pos)
 
#define FPU_MVFR0_Single_precision_Pos   4U
 
#define FPU_MVFR0_Single_precision_Msk   (0xFUL << FPU_MVFR0_Single_precision_Pos)
 
#define FPU_MVFR0_A_SIMD_registers_Pos   0U
 
#define FPU_MVFR0_A_SIMD_registers_Msk   (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)
 
#define FPU_MVFR1_FP_fused_MAC_Pos   28U
 
#define FPU_MVFR1_FP_fused_MAC_Msk   (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)
 
#define FPU_MVFR1_FP_HPFP_Pos   24U
 
#define FPU_MVFR1_FP_HPFP_Msk   (0xFUL << FPU_MVFR1_FP_HPFP_Pos)
 
#define FPU_MVFR1_D_NaN_mode_Pos   4U
 
#define FPU_MVFR1_D_NaN_mode_Msk   (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)
 
#define FPU_MVFR1_FtZ_mode_Pos   0U
 
#define FPU_MVFR1_FtZ_mode_Msk   (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)
 
#define CoreDebug_DHCSR_DBGKEY_Pos   16U
 
#define CoreDebug_DHCSR_DBGKEY_Msk   (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)
 
#define CoreDebug_DHCSR_S_RESET_ST_Pos   25U
 
#define CoreDebug_DHCSR_S_RESET_ST_Msk   (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)
 
#define CoreDebug_DHCSR_S_RETIRE_ST_Pos   24U
 
#define CoreDebug_DHCSR_S_RETIRE_ST_Msk   (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)
 
#define CoreDebug_DHCSR_S_LOCKUP_Pos   19U
 
#define CoreDebug_DHCSR_S_LOCKUP_Msk   (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)
 
#define CoreDebug_DHCSR_S_SLEEP_Pos   18U
 
#define CoreDebug_DHCSR_S_SLEEP_Msk   (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)
 
#define CoreDebug_DHCSR_S_HALT_Pos   17U
 
#define CoreDebug_DHCSR_S_HALT_Msk   (1UL << CoreDebug_DHCSR_S_HALT_Pos)
 
#define CoreDebug_DHCSR_S_REGRDY_Pos   16U
 
#define CoreDebug_DHCSR_S_REGRDY_Msk   (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)
 
#define CoreDebug_DHCSR_C_SNAPSTALL_Pos   5U
 
#define CoreDebug_DHCSR_C_SNAPSTALL_Msk   (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)
 
#define CoreDebug_DHCSR_C_MASKINTS_Pos   3U
 
#define CoreDebug_DHCSR_C_MASKINTS_Msk   (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)
 
#define CoreDebug_DHCSR_C_STEP_Pos   2U
 
#define CoreDebug_DHCSR_C_STEP_Msk   (1UL << CoreDebug_DHCSR_C_STEP_Pos)
 
#define CoreDebug_DHCSR_C_HALT_Pos   1U
 
#define CoreDebug_DHCSR_C_HALT_Msk   (1UL << CoreDebug_DHCSR_C_HALT_Pos)
 
#define CoreDebug_DHCSR_C_DEBUGEN_Pos   0U
 
#define CoreDebug_DHCSR_C_DEBUGEN_Msk   (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)
 
#define CoreDebug_DCRSR_REGWnR_Pos   16U
 
#define CoreDebug_DCRSR_REGWnR_Msk   (1UL << CoreDebug_DCRSR_REGWnR_Pos)
 
#define CoreDebug_DCRSR_REGSEL_Pos   0U
 
#define CoreDebug_DCRSR_REGSEL_Msk   (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)
 
#define CoreDebug_DEMCR_TRCENA_Pos   24U
 
#define CoreDebug_DEMCR_TRCENA_Msk   (1UL << CoreDebug_DEMCR_TRCENA_Pos)
 
#define CoreDebug_DEMCR_MON_REQ_Pos   19U
 
#define CoreDebug_DEMCR_MON_REQ_Msk   (1UL << CoreDebug_DEMCR_MON_REQ_Pos)
 
#define CoreDebug_DEMCR_MON_STEP_Pos   18U
 
#define CoreDebug_DEMCR_MON_STEP_Msk   (1UL << CoreDebug_DEMCR_MON_STEP_Pos)
 
#define CoreDebug_DEMCR_MON_PEND_Pos   17U
 
#define CoreDebug_DEMCR_MON_PEND_Msk   (1UL << CoreDebug_DEMCR_MON_PEND_Pos)
 
#define CoreDebug_DEMCR_MON_EN_Pos   16U
 
#define CoreDebug_DEMCR_MON_EN_Msk   (1UL << CoreDebug_DEMCR_MON_EN_Pos)
 
#define CoreDebug_DEMCR_VC_HARDERR_Pos   10U
 
#define CoreDebug_DEMCR_VC_HARDERR_Msk   (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)
 
#define CoreDebug_DEMCR_VC_INTERR_Pos   9U
 
#define CoreDebug_DEMCR_VC_INTERR_Msk   (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)
 
#define CoreDebug_DEMCR_VC_BUSERR_Pos   8U
 
#define CoreDebug_DEMCR_VC_BUSERR_Msk   (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)
 
#define CoreDebug_DEMCR_VC_STATERR_Pos   7U
 
#define CoreDebug_DEMCR_VC_STATERR_Msk   (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)
 
#define CoreDebug_DEMCR_VC_CHKERR_Pos   6U
 
#define CoreDebug_DEMCR_VC_CHKERR_Msk   (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)
 
#define CoreDebug_DEMCR_VC_NOCPERR_Pos   5U
 
#define CoreDebug_DEMCR_VC_NOCPERR_Msk   (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)
 
#define CoreDebug_DEMCR_VC_MMERR_Pos   4U
 
#define CoreDebug_DEMCR_VC_MMERR_Msk   (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)
 
#define CoreDebug_DEMCR_VC_CORERESET_Pos   0U
 
#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)
 
#define _VAL2FLD(field, value)   (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
 Mask and shift a bit field value for use in a register bit range.
 
#define _FLD2VAL(field, value)   (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
 Mask and shift a register value to extract a bit filed value.
 
#define SCS_BASE_SHIFT   (0x0000E000UL)
 
#define ITM_BASE_SHIFT   (0x00000000UL)
 
#define DWT_BASE_SHIFT   (0x00001000UL)
 
#define TPI_BASE_SHIFT   (0x00040000UL)
 
#define CoreDebug_BASE_SHIFT   (0x0000EDF0UL)
 
#define SCS_BASE   (MCU_CORTEX_MEM.CORTEX_PERIPH_BASE) + SCS_BASE_SHIFT
 
#define ITM_BASE   (MCU_CORTEX_MEM.CORTEX_PERIPH_BASE) + SCS_BASE_SHIFT
 
#define DWT_BASE   (MCU_CORTEX_MEM.CORTEX_PERIPH_BASE) + SCS_BASE_SHIFT
 
#define TPI_BASE   (MCU_CORTEX_MEM.CORTEX_PERIPH_BASE) + SCS_BASE_SHIFT
 
#define CoreDebug_BASE   (MCU_CORTEX_MEM.CORTEX_PERIPH_BASE) + SCS_BASE_SHIFT
 
#define SysTick_BASE   (SCS_BASE + 0x0010UL)
 
#define NVIC_BASE   (SCS_BASE + 0x0100UL)
 
#define SCB_BASE   (SCS_BASE + 0x0D00UL)
 
#define SCnSCB   ((SCnSCB_Type *) SCS_BASE )
 
#define SCB   ((SCB_Type *) SCB_BASE )
 
#define SysTick   ((SysTick_Type *) SysTick_BASE )
 
#define NVIC   ((NVIC_Type *) NVIC_BASE )
 
#define ITM   ((ITM_Type *) ITM_BASE )
 
#define DWT   ((DWT_Type *) DWT_BASE )
 
#define TPI   ((TPI_Type *) TPI_BASE )
 
#define FPU_BASE   (SCS_BASE + 0x0F30UL)
 
#define FPU   ((FPU_Type *) FPU_BASE )
 
#define NVIC_SetPriorityGrouping   __NVIC_SetPriorityGrouping
 
#define NVIC_GetPriorityGrouping   __NVIC_GetPriorityGrouping
 
#define NVIC_EnableIRQ   __NVIC_EnableIRQ
 
#define NVIC_GetEnableIRQ   __NVIC_GetEnableIRQ
 
#define NVIC_DisableIRQ   __NVIC_DisableIRQ
 
#define NVIC_GetPendingIRQ   __NVIC_GetPendingIRQ
 
#define NVIC_SetPendingIRQ   __NVIC_SetPendingIRQ
 
#define NVIC_ClearPendingIRQ   __NVIC_ClearPendingIRQ
 
#define NVIC_GetActive   __NVIC_GetActive
 
#define NVIC_SetPriority   __NVIC_SetPriority
 
#define NVIC_GetPriority   __NVIC_GetPriority
 
#define NVIC_SystemReset   __NVIC_SystemReset
 
#define NVIC_SetVector   __NVIC_SetVector
 
#define NVIC_GetVector   __NVIC_GetVector
 
#define NVIC_USER_IRQ_OFFSET   16
 
#define EXC_RETURN_HANDLER   (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
 
#define EXC_RETURN_THREAD_MSP   (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
 
#define EXC_RETURN_THREAD_PSP   (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
 
#define EXC_RETURN_HANDLER_FPU   (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */
 
#define EXC_RETURN_THREAD_MSP_FPU   (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */
 
#define EXC_RETURN_THREAD_PSP_FPU   (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */
 
#define ITM_RXBUFFER_EMPTY   ((int32_t)0x5AA55AA5U)
 
- - - -

-Typedefs

typedef struct _cortex_memory MCU_CortexMemoryTypeDef
 
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-Functions

__STATIC_INLINE void __NVIC_SetPriorityGrouping (uint32_t PriorityGroup)
 Set Priority Grouping.
 
__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping (void)
 Get Priority Grouping.
 
__STATIC_INLINE void __NVIC_EnableIRQ (IRQn_Type IRQn)
 Enable Interrupt.
 
__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ (IRQn_Type IRQn)
 Get Interrupt Enable status.
 
__STATIC_INLINE void __NVIC_DisableIRQ (IRQn_Type IRQn)
 Disable Interrupt.
 
__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ (IRQn_Type IRQn)
 Get Pending Interrupt.
 
__STATIC_INLINE void __NVIC_SetPendingIRQ (IRQn_Type IRQn)
 Set Pending Interrupt.
 
__STATIC_INLINE void __NVIC_ClearPendingIRQ (IRQn_Type IRQn)
 Clear Pending Interrupt.
 
__STATIC_INLINE uint32_t __NVIC_GetActive (IRQn_Type IRQn)
 Get Active Interrupt.
 
__STATIC_INLINE void __NVIC_SetPriority (IRQn_Type IRQn, uint32_t priority)
 Set Interrupt Priority.
 
__STATIC_INLINE uint32_t __NVIC_GetPriority (IRQn_Type IRQn)
 Get Interrupt Priority.
 
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
 Encode Priority.
 
__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t *const pPreemptPriority, uint32_t *const pSubPriority)
 Decode Priority.
 
__STATIC_INLINE void __NVIC_SetVector (IRQn_Type IRQn, uint32_t vector)
 Set Interrupt Vector.
 
__STATIC_INLINE uint32_t __NVIC_GetVector (IRQn_Type IRQn)
 Get Interrupt Vector.
 
__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset (void)
 System Reset.
 
__STATIC_INLINE uint32_t SCB_GetFPUType (void)
 get FPU type
 
__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
 ITM Send Character.
 
__STATIC_INLINE int32_t ITM_ReceiveChar (void)
 ITM Receive Character.
 
__STATIC_INLINE int32_t ITM_CheckChar (void)
 ITM Check Character.
 
- - - - - -

-Variables

MCU_CortexMemoryTypeDef MCU_CORTEX_MEM
 
volatile int32_t ITM_RxBuffer
 
-

Macro Definition Documentation

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#define __I   volatile const
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Defines 'read only' permissions

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◆ __O

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#define __O   volatile
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Defines 'write only' permissions

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◆ __IO

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#define __IO   volatile
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Defines 'read / write' permissions

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◆ __IM

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#define __IM   volatile const /*! Defines 'read only' structure member permissions */
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◆ __OM

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#define __OM   volatile /*! Defines 'write only' structure member permissions */
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◆ __IOM

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#define __IOM   volatile /*! Defines 'read / write' structure member permissions */
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-Generated by doxygen 1.10.0 -
- - diff --git a/DOCS/html/core__cm4__matlab_8h__dep__incl.map b/DOCS/html/core__cm4__matlab_8h__dep__incl.map deleted file mode 100644 index 89acb12..0000000 --- a/DOCS/html/core__cm4__matlab_8h__dep__incl.map +++ /dev/null @@ -1,7 +0,0 @@ - - - - - - - diff --git a/DOCS/html/core__cm4__matlab_8h__dep__incl.md5 b/DOCS/html/core__cm4__matlab_8h__dep__incl.md5 deleted file mode 100644 index f37dc11..0000000 --- a/DOCS/html/core__cm4__matlab_8h__dep__incl.md5 +++ /dev/null @@ -1 +0,0 @@ -f50414d23ce36504fffb24ac4e3f1846 \ No newline at end of file diff --git a/DOCS/html/core__cm4__matlab_8h__dep__incl.png b/DOCS/html/core__cm4__matlab_8h__dep__incl.png deleted file mode 100644 index 7011cc76f8ba10d81e121fbee62b92a275ed34d7..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 6580 zcmb`McTiK?_Q!)tQRD(DD$=AY9l_9xgepx@5$OhL0s#pGL&pL^n)Hx_CS7WT03m>= z2uK1*Z%IUjgceYOARzd|d++bQcVGGMoinrcnLTS}?{n6kwLa^6;;&ela2+{w1ONbV znVA~e?2k+UfW?7>ZT|_--^{UZ*}&!|hJc^H?t-?mbO3<$S+7TizIZ;)+p=~%Dh2MMa;_a`gQPf~B9ex&pF3Od!py_l$CWM_v^%o#CL&BY zZsSyLce=U44a6Raahxlc6cCf;DtFjbM_>AoUPEK?AN}2zrG{wPXq=91!W>4pBvo*9PQz@wzmFI>(qmvV&&oWYns-hGGO_BS5E?p zu#>*+=7xGM1dJ3|>KQ|2KpT{;=mNPe2yhEv(k!>5 zM08t}DVA3`qcm2?w$4_BSY<uL@T~97Sv)^Z zA6@cL)JmMbbvLE7;`7K>+8UHdoBaqi!_Q@onTMg?yqn$(eDPz5-(u*8zgaKEQhH&B~Xx8{1P z$?(Se9V{IuM4*aKe`UrdB1HlbHQe}!F$c;AvJP`5f!n$P?rBjQTklb<~;W- zW;gIbR2V%sB(K(KY?0y%=m6O+c!-?A>d*npG02+$!=vgQeSgN|v^@#;lK=9v$`0|n zjV3a6k{%!#*J9f`(z&DZ9)8B5UgDEB31>dUgXk33G!RAmLKX6><+m?A5j1RWWL#$* z7a3t z95ciOj?g3BHTF1+he|RuY-`WPjzNvg;BmkdzjzJh9Y;KB!Dc-`)*;z>2)5*n4vvM^ zUlh?_QC}d3l{9`I8l5+_uhH2Y zPA+cqvC>lg)G_|sryQ1Yj(r0Flkk)B@%Ta5n!alJG)xd>BnStHnmvgFg5+dd*8#p`bm$0fU& zF3QDUwJKpcjk|hV_vpI7MYST}#fz#(DxvjZzTHH5MPOO-$Cj_U<2tlOpR@5-X~j$- zpUJ#*>-b#p0pd+*53!#H*Q^dgAHRYl3zK$5LxYc4<(h9m>5hut2@|?IJv85x^XC$;}!k(2~=KB+{Y<=X-DE{JX}>xdb|%BwY~PS3e^-;?^C)IQ%o8AO+N7!=m~cr}w)>V_KRe>lt@>we(qqz_$Tf zA75PSs`36f=J4V`zZsn>P-IMKf#37Hm5xrj?*Wi`uy3M~AIZxTg6?-tm8p5DDPfR< zU)S^rEX|XDW|m6c`c)N^yPzmYB$n%YnyRD27>Oe|J$!hqA1V=xR)NkyBIyve)Y1V< zw4d3-~H|RN_XGi*=6On}dud@{5A#{&NDe%5h_&65+)7rU zO78oyYxsX2^Z$Ztj+C4o`^q!b700ifjW`#wH_q&%R4%{&;WRCrALgi%%Npwp_*~-% zB~Olh`kYZVI%uElssqL<8!+wm6Niu+>bQ7yYFAs6Q6d8chB|a#-`r?W)z?-5@Lk$B z`Xm{O?~F9iWV!8iJM0vUOP>@wFOQ_oiD(AYvnUFd-1JTQG0E@IET2}R?f(+3t0C<}O^ z7J|i|!Aon`8(BwK!9dbYf6`6FJbd5j8J!yHzc<$}74u|&!;_@-DT|9oBHm;>Pw54)VF7^ z2q7lVq2=3v1D*;S;wyv6?IXV?!##mL<9f&ez3+m6X%is0^Vyt{Vmr8x?Y6NCOuSdNARU|^T_ zAnyE}zn|B$_;zyV+4o1ACu5uUnwa>Xt)LG`HBSK}gcoXI$Ra3MEHo-_ek`Sbb$-QD zVF*1Q1#S7zZC}9E>5C~6VA5fRAE-QS_qQJ}Xtgm|zD1+C{t??l|FJ~>E&TsumrIOV zePI!im#x!`y(_YM1)bK~-zq4I5noRMf3C0S4gZV`Cp2ly+ykQfL~=2h9}kV4>8ck* z#ikgr0juHlotrg|gT2SR?rn<1JKx{Xc;*@Aa6nM^#~0AP!|Jg?J1`X*9$u9z36L5b zJ3{+c`1tG13iiA&zgFGatRgWc!={2e@rPF;GH|tgUz6PE`8~u(-81o)~V^SiHjN#5pRNHE`?$@z?_q^a^C-#hd2b zk_|7Erd6)udA%lID`DO23>Su$QuG1<0LGq4|bJp#-)Z7#btbrx5t>R)+O=YkKX^!RAiSMbc# zF@j=doWGFh4QK9#_7lyC*I(KO@j;)z!plx8i_TI7G_z)Nd=h5chgzWhW>aDrR$yuN z8m_p`yJTO0KBkbe3=(go3r3&dVe0F5799F3dxH@84K#!g>T*2Iw` zS^T-8omG9N+DIbo%z6peIp94DUITq5KP z5YhXgRKVrBB{U=tT_|xcPQEtx_JL?~uuM{Jm+P0OA9XF|KL^MEVBs$OP97N}UTL|q zg-I5}J$C5ET)0T=sdigDJyN*TBN&JVcULgaOE~aAQ~#ilLjDWNBts$l_OZVYdnA1O#9ePt zzX4^>6SCY87LlXo`FMxt(95aR$q3i9xbFSBCyRTVU1MxA6v)8m!z36^(5XURc1R`! ztPo%HO{g2}2^}^&mz3U*ErjJrGP1&w-2`-RZSgN^sQ}LAkGA~5C)7Qi-a|`lV2|JV zB)5%T^L7v@ay3w$X_grHiv-!s!wfdIdO0T-h~hWO2KmSOR%Wo?Xv zaZY-FNR@k-m98YL=AN@|6*B$@r=CKAQ#$JEN`%p-TI}< zvNrbQf1s1eH^)aj_92``n{9!wSi9(AZZNYTu)ZLj9xg}z>Yw-QCzJ|2t9mn7>|fn{DjiS4*u_s zs7vRD`6r%XEYjZMSRpWXiOSa)Ce{riJhWuLG23Va$+2Gm(|tzcp_b4~0VjUz+Q)27 ziZN{;T^Rm7r~-;UqA=2r$MhlWpy-UpLD%0i>rpI9X!=nH#pYe#K(@cv8)G@H@hlr~ zKEx(J*ucT{8l(P)T+^MTn#iP8a*>}LzX3^s%(Y79IyBUSZ`jqzTXcY{)+Oi+mhEXkCU>TQ$5mReKA1&AF zgc9cDhzU;SulxkO(K~C_Lgr(hp@a>mw~qF3NZi-Mpcj_I*;4L=Ac1pgwdAeVjdI81 zkm=bei3p(m=2+K{o>mFEe6Lx$3d&~?YKUkvb-2%gUtw@Su)s>BO15ga)f9PcL&2G7 zq?K$J&b;z2{He;PI9mP1>DR%PQ1X56mO=i-RTaA2T^vfJ)c5(|?Q8JBB?gSVyPKt{ z%xmoRjD_Os7jjYcLVz=mq_=AO;P$ee!qLYyJ{hU6tB2Q0&g@6jhj8cYOfhuTa!&0C zh|NAjLD=kMw!t`b`Ey>jAYEb4ba^1++TBG?*Y57_sappCr_1BvdGwdk&u-$@4u+C$QorLC-st@# zP+`&18pBCPV8GG?isMwYq7(W3OaG?zeYD#r<&Ho4A+ObVe5o8KbGJa zWRi+rftv7Mob#&hk@BNt-#4whdp}0nav;YBvk=0V{P{Jln`J3s)2xfpsgp_}@y@wY zsCb0bvn{H{K2aSWIk-<$4Ml1&6~A}{%y2rV-x1<^ta;KHzT{8KFOiQ(5svC&stz)v zV8PqYiUfTfr3(V?)S-*}O!H}d7j6>u{!eZ?J}96%ywz>hACxDxeOWqP-+do}!oRg` zor<4-EUlm&)a-J9X?N>wmsAX!K8bD8cY$aaq!_TZqB`s&&tUP3Mpi2i3{SG9GGnw9 zNXOgEn2B$#-SkOa>f0yVEDZDGsj9^y`D?mhz|X$ z^Zlhn`~?HQDEEJiIe(Kp{Am8m!NEbcP|6ZE0x~J zs~g@LS{Zm-<2`j!R&GO!o6bi6XXfdTD@GKH~>apR^`I7$jd&!NFR^y(r|XJB@( z>>~jAQsA1eFiMIXvDGK#Mf;Cy|H3OxW&!NT4EMNuTIP&F)nJUKi%leC5~ICgK&tTZ zZVPuG@88!|M-g{K5Q}uDt{y2POEF^ay!tJA=4+I zZIzyS%RwDqvNj5(AD7 z5}TQ0xlpU2lZ8RYv@`PS+;1BR9&$H~4%^64t_wpahQAd+S|V0+Nv*t;nxT!U zf2}@|tXZ1;%C3C(H>H)aSCS>u0BG&_xgukeaRrddoeL+GjuY5NZX+zk|E`T7yKCZB zz#I6$i^C=JA8i{2+lm=u!@#pe6MbXhfHsqPUgN?n;H=yTBZ}5#MHtV9Lv5QyzbjEp zJT_y@goXFZUG2z8mzFa^W<(r4aw@eUq|ZCfSWx{w2CSUjIk=tdhONghNMv-G(I>7D zNNKR)##(n&pyhwYHK)Jtl;4b7JF(iGJ)P61(!$v#ukf{U`*a59Cp1^2kFVp++&O;}$5gT|#ZHwCd zV>gWWH$4R26T?6HRvU#*U!vjlBDOk>vxNT%I7aUTS5E$eH#UE6(CtOxyd%Pek}y-& z@~gji1Lxfipyl~r%~~2G=v`#|S2-jG?UXare8a3tPK|pZSUxOpTCB;UIta_eEq3Bd z@n@T1wsen!fFCDPNLY>D!gf)O0!lRS#-Fq?^|!QVkoj^zFrnikW;&nlm@t31^7u2UL^T<|QnGK+%y`kq(ogFYMKw`j^s3Dx1@_7AbIA@gz0x!xVSAO_!IY*!L@I@BI z)d$Pu`J;f5Bu*$UId3{StjMgr#dRGxTzrXbU!sD=`6kTqPN$Q+6Egfn9X@h>e^qv# zrBEJDWZbWCv&yUR(SVgMcDx(V+3+*U5TrL=TcmW5zepR<++H_8*o5VBbfM$6Q>b6nZlT%B@;XE@OUE*Jr(Op=R2 zl1Wy^%_ZkAJk68rM;&iCxZcrqlgDoK+>+0zEd9(ljzm4BV9@ - - - - - - -STM MATLAB Simulator: F:/Work/Projects/MATLAB/matlab_stm_emulate/MCU_STM32F4xx_Matlab/Drivers/CMSIS/core_cm4_matlab.h Source File - - - - - - - - - - - -
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core_cm4_matlab.h
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1/************************************************************************
-
2Данный файл ÑвлÑетÑÑ ÐºÐ¾Ð¿Ð¸ÐµÐ¹ core_cm4.h, только первые ~160 Ñтрок, которые
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3определÑÑŽÑ‚ компилÑтор ÐРМ, удалены.
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4ÐœÐТЛÐБ компилирует через код через комплилÑтор MSVC Ð´Ð»Ñ Ð±Ð»Ð¾ÐºÐ° S-Function
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5Также добавлена Ñтруктура Ð¸Ð¼Ð¸Ñ‚Ð¸Ñ€ÑƒÑŽÑ‰Ð°Ñ Ð¿Ð°Ð¼ÑÑ‚ÑŒ Ñдра (~1360)
-
6**************************************************************************/
-
7#ifndef __CMSIS_GENERIC
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8/* IO definitions (access restrictions to peripheral registers) */
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17#ifdef __cplusplus
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18 #define __I volatile
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19#else
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20 #define __I volatile const
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21#endif
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22#define __O volatile
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23#define __IO volatile
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25/* following defines should be used for structure members */
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26#define __IM volatile const
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27#define __OM volatile
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28#define __IOM volatile
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34/*******************************************************************************
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35 * Register Abstraction
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36 Core Register contain:
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37 - Core Register
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38 - Core NVIC Register
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39 - Core SCB Register
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40 - Core SysTick Register
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41 - Core Debug Register
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42 - Core MPU Register
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43 - Core FPU Register
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44 ******************************************************************************/
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-
60typedef union
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61{
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62 struct
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63 {
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64 uint32_t _reserved0:16;
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65 uint32_t GE:4;
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66 uint32_t _reserved1:7;
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67 uint32_t Q:1;
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68 uint32_t V:1;
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69 uint32_t C:1;
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70 uint32_t Z:1;
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71 uint32_t N:1;
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72 } b;
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73 uint32_t w;
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74} APSR_Type;
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75
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76/* APSR Register Definitions */
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77#define APSR_N_Pos 31U
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78#define APSR_N_Msk (1UL << APSR_N_Pos)
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80#define APSR_Z_Pos 30U
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81#define APSR_Z_Msk (1UL << APSR_Z_Pos)
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83#define APSR_C_Pos 29U
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84#define APSR_C_Msk (1UL << APSR_C_Pos)
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86#define APSR_V_Pos 28U
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87#define APSR_V_Msk (1UL << APSR_V_Pos)
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89#define APSR_Q_Pos 27U
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90#define APSR_Q_Msk (1UL << APSR_Q_Pos)
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92#define APSR_GE_Pos 16U
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93#define APSR_GE_Msk (0xFUL << APSR_GE_Pos)
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99typedef union
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100{
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101 struct
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102 {
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103 uint32_t ISR:9;
-
104 uint32_t _reserved0:23;
-
105 } b;
-
106 uint32_t w;
-
107} IPSR_Type;
-
-
108
-
109/* IPSR Register Definitions */
-
110#define IPSR_ISR_Pos 0U
-
111#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/)
-
-
117typedef union
-
118{
-
119 struct
-
120 {
-
121 uint32_t ISR:9;
-
122 uint32_t _reserved0:1;
-
123 uint32_t ICI_IT_1:6;
-
124 uint32_t GE:4;
-
125 uint32_t _reserved1:4;
-
126 uint32_t T:1;
-
127 uint32_t ICI_IT_2:2;
-
128 uint32_t Q:1;
-
129 uint32_t V:1;
-
130 uint32_t C:1;
-
131 uint32_t Z:1;
-
132 uint32_t N:1;
-
133 } b;
-
134 uint32_t w;
-
135} xPSR_Type;
-
-
136
-
137/* xPSR Register Definitions */
-
138#define xPSR_N_Pos 31U
-
139#define xPSR_N_Msk (1UL << xPSR_N_Pos)
-
141#define xPSR_Z_Pos 30U
-
142#define xPSR_Z_Msk (1UL << xPSR_Z_Pos)
-
144#define xPSR_C_Pos 29U
-
145#define xPSR_C_Msk (1UL << xPSR_C_Pos)
-
147#define xPSR_V_Pos 28U
-
148#define xPSR_V_Msk (1UL << xPSR_V_Pos)
-
150#define xPSR_Q_Pos 27U
-
151#define xPSR_Q_Msk (1UL << xPSR_Q_Pos)
-
153#define xPSR_ICI_IT_2_Pos 25U
-
154#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos)
-
156#define xPSR_T_Pos 24U
-
157#define xPSR_T_Msk (1UL << xPSR_T_Pos)
-
159#define xPSR_GE_Pos 16U
-
160#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos)
-
162#define xPSR_ICI_IT_1_Pos 10U
-
163#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos)
-
165#define xPSR_ISR_Pos 0U
-
166#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/)
-
-
172typedef union
-
173{
-
174 struct
-
175 {
-
176 uint32_t nPRIV:1;
-
177 uint32_t SPSEL:1;
-
178 uint32_t FPCA:1;
-
179 uint32_t _reserved0:29;
-
180 } b;
-
181 uint32_t w;
-
182} CONTROL_Type;
-
-
183
-
184/* CONTROL Register Definitions */
-
185#define CONTROL_FPCA_Pos 2U
-
186#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos)
-
188#define CONTROL_SPSEL_Pos 1U
-
189#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos)
-
191#define CONTROL_nPRIV_Pos 0U
-
192#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/)
-
-
207typedef struct
-
208{
-
209 __IOM uint32_t ISER[8U];
-
210 uint32_t RESERVED0[24U];
-
211 __IOM uint32_t ICER[8U];
-
212 uint32_t RSERVED1[24U];
-
213 __IOM uint32_t ISPR[8U];
-
214 uint32_t RESERVED2[24U];
-
215 __IOM uint32_t ICPR[8U];
-
216 uint32_t RESERVED3[24U];
-
217 __IOM uint32_t IABR[8U];
-
218 uint32_t RESERVED4[56U];
-
219 __IOM uint8_t IP[240U];
-
220 uint32_t RESERVED5[644U];
-
221 __OM uint32_t STIR;
-
222} NVIC_Type;
-
-
223
-
224/* Software Triggered Interrupt Register Definitions */
-
225#define NVIC_STIR_INTID_Pos 0U
-
226#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)
- -
265
-
266/* SCB CPUID Register Definitions */
-
267#define SCB_CPUID_IMPLEMENTER_Pos 24U
-
268#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
-
270#define SCB_CPUID_VARIANT_Pos 20U
-
271#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos)
-
273#define SCB_CPUID_ARCHITECTURE_Pos 16U
-
274#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
-
276#define SCB_CPUID_PARTNO_Pos 4U
-
277#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos)
-
279#define SCB_CPUID_REVISION_Pos 0U
-
280#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)
-
282/* SCB Interrupt Control State Register Definitions */
-
283#define SCB_ICSR_NMIPENDSET_Pos 31U
-
284#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos)
-
286#define SCB_ICSR_PENDSVSET_Pos 28U
-
287#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos)
-
289#define SCB_ICSR_PENDSVCLR_Pos 27U
-
290#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos)
-
292#define SCB_ICSR_PENDSTSET_Pos 26U
-
293#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos)
-
295#define SCB_ICSR_PENDSTCLR_Pos 25U
-
296#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos)
-
298#define SCB_ICSR_ISRPREEMPT_Pos 23U
-
299#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos)
-
301#define SCB_ICSR_ISRPENDING_Pos 22U
-
302#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos)
-
304#define SCB_ICSR_VECTPENDING_Pos 12U
-
305#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
-
307#define SCB_ICSR_RETTOBASE_Pos 11U
-
308#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos)
-
310#define SCB_ICSR_VECTACTIVE_Pos 0U
-
311#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)
-
313/* SCB Vector Table Offset Register Definitions */
-
314#define SCB_VTOR_TBLOFF_Pos 7U
-
315#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)
-
317/* SCB Application Interrupt and Reset Control Register Definitions */
-
318#define SCB_AIRCR_VECTKEY_Pos 16U
-
319#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
-
321#define SCB_AIRCR_VECTKEYSTAT_Pos 16U
-
322#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
-
324#define SCB_AIRCR_ENDIANESS_Pos 15U
-
325#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos)
-
327#define SCB_AIRCR_PRIGROUP_Pos 8U
-
328#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos)
-
330#define SCB_AIRCR_SYSRESETREQ_Pos 2U
-
331#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
-
333#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U
-
334#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
-
336#define SCB_AIRCR_VECTRESET_Pos 0U
-
337#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)
-
339/* SCB System Control Register Definitions */
-
340#define SCB_SCR_SEVONPEND_Pos 4U
-
341#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos)
-
343#define SCB_SCR_SLEEPDEEP_Pos 2U
-
344#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos)
-
346#define SCB_SCR_SLEEPONEXIT_Pos 1U
-
347#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos)
-
349/* SCB Configuration Control Register Definitions */
-
350#define SCB_CCR_STKALIGN_Pos 9U
-
351#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos)
-
353#define SCB_CCR_BFHFNMIGN_Pos 8U
-
354#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos)
-
356#define SCB_CCR_DIV_0_TRP_Pos 4U
-
357#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos)
-
359#define SCB_CCR_UNALIGN_TRP_Pos 3U
-
360#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos)
-
362#define SCB_CCR_USERSETMPEND_Pos 1U
-
363#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos)
-
365#define SCB_CCR_NONBASETHRDENA_Pos 0U
-
366#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)
-
368/* SCB System Handler Control and State Register Definitions */
-
369#define SCB_SHCSR_USGFAULTENA_Pos 18U
-
370#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos)
-
372#define SCB_SHCSR_BUSFAULTENA_Pos 17U
-
373#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos)
-
375#define SCB_SHCSR_MEMFAULTENA_Pos 16U
-
376#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos)
-
378#define SCB_SHCSR_SVCALLPENDED_Pos 15U
-
379#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
-
381#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U
-
382#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)
-
384#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U
-
385#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)
-
387#define SCB_SHCSR_USGFAULTPENDED_Pos 12U
-
388#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)
-
390#define SCB_SHCSR_SYSTICKACT_Pos 11U
-
391#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos)
-
393#define SCB_SHCSR_PENDSVACT_Pos 10U
-
394#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos)
-
396#define SCB_SHCSR_MONITORACT_Pos 8U
-
397#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos)
-
399#define SCB_SHCSR_SVCALLACT_Pos 7U
-
400#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos)
-
402#define SCB_SHCSR_USGFAULTACT_Pos 3U
-
403#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos)
-
405#define SCB_SHCSR_BUSFAULTACT_Pos 1U
-
406#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos)
-
408#define SCB_SHCSR_MEMFAULTACT_Pos 0U
-
409#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)
-
411/* SCB Configurable Fault Status Register Definitions */
-
412#define SCB_CFSR_USGFAULTSR_Pos 16U
-
413#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)
-
415#define SCB_CFSR_BUSFAULTSR_Pos 8U
-
416#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)
-
418#define SCB_CFSR_MEMFAULTSR_Pos 0U
-
419#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)
-
421/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
-
422#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U)
-
423#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos)
-
425#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U)
-
426#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos)
-
428#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U)
-
429#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos)
-
431#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U)
-
432#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos)
-
434#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U)
-
435#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos)
-
437#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U)
-
438#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)
-
440/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
-
441#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U)
-
442#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos)
-
444#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U)
-
445#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos)
-
447#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U)
-
448#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos)
-
450#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U)
-
451#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos)
-
453#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U)
-
454#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos)
-
456#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U)
-
457#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos)
-
459#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U)
-
460#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos)
-
462/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
-
463#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U)
-
464#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos)
-
466#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U)
-
467#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos)
-
469#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U)
-
470#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos)
-
472#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U)
-
473#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos)
-
475#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U)
-
476#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos)
-
478#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U)
-
479#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos)
-
481/* SCB Hard Fault Status Register Definitions */
-
482#define SCB_HFSR_DEBUGEVT_Pos 31U
-
483#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos)
-
485#define SCB_HFSR_FORCED_Pos 30U
-
486#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos)
-
488#define SCB_HFSR_VECTTBL_Pos 1U
-
489#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos)
-
491/* SCB Debug Fault Status Register Definitions */
-
492#define SCB_DFSR_EXTERNAL_Pos 4U
-
493#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos)
-
495#define SCB_DFSR_VCATCH_Pos 3U
-
496#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos)
-
498#define SCB_DFSR_DWTTRAP_Pos 2U
-
499#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos)
-
501#define SCB_DFSR_BKPT_Pos 1U
-
502#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos)
-
504#define SCB_DFSR_HALTED_Pos 0U
-
505#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/)
-
-
520typedef struct
-
521{
-
522 uint32_t RESERVED0[1U];
-
523 __IM uint32_t ICTR;
-
524 __IOM uint32_t ACTLR;
-
525} SCnSCB_Type;
-
-
526
-
527/* Interrupt Controller Type Register Definitions */
-
528#define SCnSCB_ICTR_INTLINESNUM_Pos 0U
-
529#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)
-
531/* Auxiliary Control Register Definitions */
-
532#define SCnSCB_ACTLR_DISOOFP_Pos 9U
-
533#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos)
-
535#define SCnSCB_ACTLR_DISFPCA_Pos 8U
-
536#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos)
-
538#define SCnSCB_ACTLR_DISFOLD_Pos 2U
-
539#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos)
-
541#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U
-
542#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)
-
544#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U
-
545#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)
- -
567
-
568/* SysTick Control / Status Register Definitions */
-
569#define SysTick_CTRL_COUNTFLAG_Pos 16U
-
570#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos)
-
572#define SysTick_CTRL_CLKSOURCE_Pos 2U
-
573#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos)
-
575#define SysTick_CTRL_TICKINT_Pos 1U
-
576#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos)
-
578#define SysTick_CTRL_ENABLE_Pos 0U
-
579#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)
-
581/* SysTick Reload Register Definitions */
-
582#define SysTick_LOAD_RELOAD_Pos 0U
-
583#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)
-
585/* SysTick Current Register Definitions */
-
586#define SysTick_VAL_CURRENT_Pos 0U
-
587#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)
-
589/* SysTick Calibration Register Definitions */
-
590#define SysTick_CALIB_NOREF_Pos 31U
-
591#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos)
-
593#define SysTick_CALIB_SKEW_Pos 30U
-
594#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos)
-
596#define SysTick_CALIB_TENMS_Pos 0U
-
597#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)
- -
647
-
648/* ITM Trace Privilege Register Definitions */
-
649#define ITM_TPR_PRIVMASK_Pos 0U
-
650#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/)
-
652/* ITM Trace Control Register Definitions */
-
653#define ITM_TCR_BUSY_Pos 23U
-
654#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos)
-
656#define ITM_TCR_TraceBusID_Pos 16U
-
657#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos)
-
659#define ITM_TCR_GTSFREQ_Pos 10U
-
660#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos)
-
662#define ITM_TCR_TSPrescale_Pos 8U
-
663#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos)
-
665#define ITM_TCR_SWOENA_Pos 4U
-
666#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos)
-
668#define ITM_TCR_DWTENA_Pos 3U
-
669#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos)
-
671#define ITM_TCR_SYNCENA_Pos 2U
-
672#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos)
-
674#define ITM_TCR_TSENA_Pos 1U
-
675#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos)
-
677#define ITM_TCR_ITMENA_Pos 0U
-
678#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/)
-
680/* ITM Integration Write Register Definitions */
-
681#define ITM_IWR_ATVALIDM_Pos 0U
-
682#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)
-
684/* ITM Integration Read Register Definitions */
-
685#define ITM_IRR_ATREADYM_Pos 0U
-
686#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/)
-
688/* ITM Integration Mode Control Register Definitions */
-
689#define ITM_IMCR_INTEGRATION_Pos 0U
-
690#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)
-
692/* ITM Lock Status Register Definitions */
-
693#define ITM_LSR_ByteAcc_Pos 2U
-
694#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos)
-
696#define ITM_LSR_Access_Pos 1U
-
697#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos)
-
699#define ITM_LSR_Present_Pos 0U
-
700#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /* end of group CMSIS_ITM */
-
703
-
704
- -
741
-
742/* DWT Control Register Definitions */
-
743#define DWT_CTRL_NUMCOMP_Pos 28U
-
744#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos)
-
746#define DWT_CTRL_NOTRCPKT_Pos 27U
-
747#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos)
-
749#define DWT_CTRL_NOEXTTRIG_Pos 26U
-
750#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)
-
752#define DWT_CTRL_NOCYCCNT_Pos 25U
-
753#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos)
-
755#define DWT_CTRL_NOPRFCNT_Pos 24U
-
756#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos)
-
758#define DWT_CTRL_CYCEVTENA_Pos 22U
-
759#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos)
-
761#define DWT_CTRL_FOLDEVTENA_Pos 21U
-
762#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)
-
764#define DWT_CTRL_LSUEVTENA_Pos 20U
-
765#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos)
-
767#define DWT_CTRL_SLEEPEVTENA_Pos 19U
-
768#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)
-
770#define DWT_CTRL_EXCEVTENA_Pos 18U
-
771#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos)
-
773#define DWT_CTRL_CPIEVTENA_Pos 17U
-
774#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos)
-
776#define DWT_CTRL_EXCTRCENA_Pos 16U
-
777#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos)
-
779#define DWT_CTRL_PCSAMPLENA_Pos 12U
-
780#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)
-
782#define DWT_CTRL_SYNCTAP_Pos 10U
-
783#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos)
-
785#define DWT_CTRL_CYCTAP_Pos 9U
-
786#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos)
-
788#define DWT_CTRL_POSTINIT_Pos 5U
-
789#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos)
-
791#define DWT_CTRL_POSTPRESET_Pos 1U
-
792#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos)
-
794#define DWT_CTRL_CYCCNTENA_Pos 0U
-
795#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)
-
797/* DWT CPI Count Register Definitions */
-
798#define DWT_CPICNT_CPICNT_Pos 0U
-
799#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)
-
801/* DWT Exception Overhead Count Register Definitions */
-
802#define DWT_EXCCNT_EXCCNT_Pos 0U
-
803#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)
-
805/* DWT Sleep Count Register Definitions */
-
806#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U
-
807#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)
-
809/* DWT LSU Count Register Definitions */
-
810#define DWT_LSUCNT_LSUCNT_Pos 0U
-
811#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)
-
813/* DWT Folded-instruction Count Register Definitions */
-
814#define DWT_FOLDCNT_FOLDCNT_Pos 0U
-
815#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)
-
817/* DWT Comparator Mask Register Definitions */
-
818#define DWT_MASK_MASK_Pos 0U
-
819#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/)
-
821/* DWT Comparator Function Register Definitions */
-
822#define DWT_FUNCTION_MATCHED_Pos 24U
-
823#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos)
-
825#define DWT_FUNCTION_DATAVADDR1_Pos 16U
-
826#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)
-
828#define DWT_FUNCTION_DATAVADDR0_Pos 12U
-
829#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)
-
831#define DWT_FUNCTION_DATAVSIZE_Pos 10U
-
832#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)
-
834#define DWT_FUNCTION_LNK1ENA_Pos 9U
-
835#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)
-
837#define DWT_FUNCTION_DATAVMATCH_Pos 8U
-
838#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)
-
840#define DWT_FUNCTION_CYCMATCH_Pos 7U
-
841#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)
-
843#define DWT_FUNCTION_EMITRANGE_Pos 5U
-
844#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)
-
846#define DWT_FUNCTION_FUNCTION_Pos 0U
-
847#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /* end of group CMSIS_DWT */
-
850
-
851
- -
889
-
890/* TPI Asynchronous Clock Prescaler Register Definitions */
-
891#define TPI_ACPR_PRESCALER_Pos 0U
-
892#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)
-
894/* TPI Selected Pin Protocol Register Definitions */
-
895#define TPI_SPPR_TXMODE_Pos 0U
-
896#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)
-
898/* TPI Formatter and Flush Status Register Definitions */
-
899#define TPI_FFSR_FtNonStop_Pos 3U
-
900#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos)
-
902#define TPI_FFSR_TCPresent_Pos 2U
-
903#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos)
-
905#define TPI_FFSR_FtStopped_Pos 1U
-
906#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos)
-
908#define TPI_FFSR_FlInProg_Pos 0U
-
909#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)
-
911/* TPI Formatter and Flush Control Register Definitions */
-
912#define TPI_FFCR_TrigIn_Pos 8U
-
913#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos)
-
915#define TPI_FFCR_EnFCont_Pos 1U
-
916#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos)
-
918/* TPI TRIGGER Register Definitions */
-
919#define TPI_TRIGGER_TRIGGER_Pos 0U
-
920#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)
-
922/* TPI Integration ETM Data Register Definitions (FIFO0) */
-
923#define TPI_FIFO0_ITM_ATVALID_Pos 29U
-
924#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)
-
926#define TPI_FIFO0_ITM_bytecount_Pos 27U
-
927#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)
-
929#define TPI_FIFO0_ETM_ATVALID_Pos 26U
-
930#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)
-
932#define TPI_FIFO0_ETM_bytecount_Pos 24U
-
933#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)
-
935#define TPI_FIFO0_ETM2_Pos 16U
-
936#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos)
-
938#define TPI_FIFO0_ETM1_Pos 8U
-
939#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos)
-
941#define TPI_FIFO0_ETM0_Pos 0U
-
942#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)
-
944/* TPI ITATBCTR2 Register Definitions */
-
945#define TPI_ITATBCTR2_ATREADY2_Pos 0U
-
946#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/)
-
948#define TPI_ITATBCTR2_ATREADY1_Pos 0U
-
949#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/)
-
951/* TPI Integration ITM Data Register Definitions (FIFO1) */
-
952#define TPI_FIFO1_ITM_ATVALID_Pos 29U
-
953#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)
-
955#define TPI_FIFO1_ITM_bytecount_Pos 27U
-
956#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)
-
958#define TPI_FIFO1_ETM_ATVALID_Pos 26U
-
959#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)
-
961#define TPI_FIFO1_ETM_bytecount_Pos 24U
-
962#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)
-
964#define TPI_FIFO1_ITM2_Pos 16U
-
965#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos)
-
967#define TPI_FIFO1_ITM1_Pos 8U
-
968#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos)
-
970#define TPI_FIFO1_ITM0_Pos 0U
-
971#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)
-
973/* TPI ITATBCTR0 Register Definitions */
-
974#define TPI_ITATBCTR0_ATREADY2_Pos 0U
-
975#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/)
-
977#define TPI_ITATBCTR0_ATREADY1_Pos 0U
-
978#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/)
-
980/* TPI Integration Mode Control Register Definitions */
-
981#define TPI_ITCTRL_Mode_Pos 0U
-
982#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/)
-
984/* TPI DEVID Register Definitions */
-
985#define TPI_DEVID_NRZVALID_Pos 11U
-
986#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos)
-
988#define TPI_DEVID_MANCVALID_Pos 10U
-
989#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos)
-
991#define TPI_DEVID_PTINVALID_Pos 9U
-
992#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos)
-
994#define TPI_DEVID_MinBufSz_Pos 6U
-
995#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos)
-
997#define TPI_DEVID_AsynClkIn_Pos 5U
-
998#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos)
-
1000#define TPI_DEVID_NrTraceInput_Pos 0U
-
1001#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)
-
1003/* TPI DEVTYPE Register Definitions */
-
1004#define TPI_DEVTYPE_SubType_Pos 4U
-
1005#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)
-
1007#define TPI_DEVTYPE_MajorType_Pos 0U
-
1008#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /* end of group CMSIS_TPI */
-
1011
-
1012
-
1013#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
-
1024typedef struct
-
1025{
-
1026 __IM uint32_t TYPE;
-
1027 __IOM uint32_t CTRL;
-
1028 __IOM uint32_t RNR;
-
1029 __IOM uint32_t RBAR;
-
1030 __IOM uint32_t RASR;
-
1031 __IOM uint32_t RBAR_A1;
-
1032 __IOM uint32_t RASR_A1;
-
1033 __IOM uint32_t RBAR_A2;
-
1034 __IOM uint32_t RASR_A2;
-
1035 __IOM uint32_t RBAR_A3;
-
1036 __IOM uint32_t RASR_A3;
-
1037} MPU_Type;
-
1038
-
1039#define MPU_TYPE_RALIASES 4U
-
1040
-
1041/* MPU Type Register Definitions */
-
1042#define MPU_TYPE_IREGION_Pos 16U
-
1043#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos)
-
1045#define MPU_TYPE_DREGION_Pos 8U
-
1046#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos)
-
1048#define MPU_TYPE_SEPARATE_Pos 0U
-
1049#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)
-
1051/* MPU Control Register Definitions */
-
1052#define MPU_CTRL_PRIVDEFENA_Pos 2U
-
1053#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos)
-
1055#define MPU_CTRL_HFNMIENA_Pos 1U
-
1056#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos)
-
1058#define MPU_CTRL_ENABLE_Pos 0U
-
1059#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/)
-
1061/* MPU Region Number Register Definitions */
-
1062#define MPU_RNR_REGION_Pos 0U
-
1063#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/)
-
1065/* MPU Region Base Address Register Definitions */
-
1066#define MPU_RBAR_ADDR_Pos 5U
-
1067#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)
-
1069#define MPU_RBAR_VALID_Pos 4U
-
1070#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos)
-
1072#define MPU_RBAR_REGION_Pos 0U
-
1073#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/)
-
1075/* MPU Region Attribute and Size Register Definitions */
-
1076#define MPU_RASR_ATTRS_Pos 16U
-
1077#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos)
-
1079#define MPU_RASR_XN_Pos 28U
-
1080#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos)
-
1082#define MPU_RASR_AP_Pos 24U
-
1083#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos)
-
1085#define MPU_RASR_TEX_Pos 19U
-
1086#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos)
-
1088#define MPU_RASR_S_Pos 18U
-
1089#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos)
-
1091#define MPU_RASR_C_Pos 17U
-
1092#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos)
-
1094#define MPU_RASR_B_Pos 16U
-
1095#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos)
-
1097#define MPU_RASR_SRD_Pos 8U
-
1098#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos)
-
1100#define MPU_RASR_SIZE_Pos 1U
-
1101#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos)
-
1103#define MPU_RASR_ENABLE_Pos 0U
-
1104#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/)
-
1107#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */
-
1108
-
1109
- -
1129
-
1130/* Floating-Point Context Control Register Definitions */
-
1131#define FPU_FPCCR_ASPEN_Pos 31U
-
1132#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos)
-
1134#define FPU_FPCCR_LSPEN_Pos 30U
-
1135#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos)
-
1137#define FPU_FPCCR_MONRDY_Pos 8U
-
1138#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos)
-
1140#define FPU_FPCCR_BFRDY_Pos 6U
-
1141#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos)
-
1143#define FPU_FPCCR_MMRDY_Pos 5U
-
1144#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos)
-
1146#define FPU_FPCCR_HFRDY_Pos 4U
-
1147#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos)
-
1149#define FPU_FPCCR_THREAD_Pos 3U
-
1150#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos)
-
1152#define FPU_FPCCR_USER_Pos 1U
-
1153#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos)
-
1155#define FPU_FPCCR_LSPACT_Pos 0U
-
1156#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)
-
1158/* Floating-Point Context Address Register Definitions */
-
1159#define FPU_FPCAR_ADDRESS_Pos 3U
-
1160#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)
-
1162/* Floating-Point Default Status Control Register Definitions */
-
1163#define FPU_FPDSCR_AHP_Pos 26U
-
1164#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos)
-
1166#define FPU_FPDSCR_DN_Pos 25U
-
1167#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos)
-
1169#define FPU_FPDSCR_FZ_Pos 24U
-
1170#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos)
-
1172#define FPU_FPDSCR_RMode_Pos 22U
-
1173#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos)
-
1175/* Media and FP Feature Register 0 Definitions */
-
1176#define FPU_MVFR0_FP_rounding_modes_Pos 28U
-
1177#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)
-
1179#define FPU_MVFR0_Short_vectors_Pos 24U
-
1180#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos)
-
1182#define FPU_MVFR0_Square_root_Pos 20U
-
1183#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos)
-
1185#define FPU_MVFR0_Divide_Pos 16U
-
1186#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos)
-
1188#define FPU_MVFR0_FP_excep_trapping_Pos 12U
-
1189#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)
-
1191#define FPU_MVFR0_Double_precision_Pos 8U
-
1192#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos)
-
1194#define FPU_MVFR0_Single_precision_Pos 4U
-
1195#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos)
-
1197#define FPU_MVFR0_A_SIMD_registers_Pos 0U
-
1198#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)
-
1200/* Media and FP Feature Register 1 Definitions */
-
1201#define FPU_MVFR1_FP_fused_MAC_Pos 28U
-
1202#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)
-
1204#define FPU_MVFR1_FP_HPFP_Pos 24U
-
1205#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos)
-
1207#define FPU_MVFR1_D_NaN_mode_Pos 4U
-
1208#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)
-
1210#define FPU_MVFR1_FtZ_mode_Pos 0U
-
1211#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)
- -
1233
-
1234/* Debug Halting Control and Status Register Definitions */
-
1235#define CoreDebug_DHCSR_DBGKEY_Pos 16U
-
1236#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)
-
1238#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U
-
1239#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)
-
1241#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U
-
1242#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)
-
1244#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U
-
1245#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)
-
1247#define CoreDebug_DHCSR_S_SLEEP_Pos 18U
-
1248#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)
-
1250#define CoreDebug_DHCSR_S_HALT_Pos 17U
-
1251#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos)
-
1253#define CoreDebug_DHCSR_S_REGRDY_Pos 16U
-
1254#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)
-
1256#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U
-
1257#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)
-
1259#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U
-
1260#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)
-
1262#define CoreDebug_DHCSR_C_STEP_Pos 2U
-
1263#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos)
-
1265#define CoreDebug_DHCSR_C_HALT_Pos 1U
-
1266#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos)
-
1268#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U
-
1269#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)
-
1271/* Debug Core Register Selector Register Definitions */
-
1272#define CoreDebug_DCRSR_REGWnR_Pos 16U
-
1273#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos)
-
1275#define CoreDebug_DCRSR_REGSEL_Pos 0U
-
1276#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)
-
1278/* Debug Exception and Monitor Control Register Definitions */
-
1279#define CoreDebug_DEMCR_TRCENA_Pos 24U
-
1280#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos)
-
1282#define CoreDebug_DEMCR_MON_REQ_Pos 19U
-
1283#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos)
-
1285#define CoreDebug_DEMCR_MON_STEP_Pos 18U
-
1286#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos)
-
1288#define CoreDebug_DEMCR_MON_PEND_Pos 17U
-
1289#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos)
-
1291#define CoreDebug_DEMCR_MON_EN_Pos 16U
-
1292#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos)
-
1294#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U
-
1295#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)
-
1297#define CoreDebug_DEMCR_VC_INTERR_Pos 9U
-
1298#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)
-
1300#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U
-
1301#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)
-
1303#define CoreDebug_DEMCR_VC_STATERR_Pos 7U
-
1304#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)
-
1306#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U
-
1307#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)
-
1309#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U
-
1310#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)
-
1312#define CoreDebug_DEMCR_VC_MMERR_Pos 4U
-
1313#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)
-
1315#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U
-
1316#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)
-
1334#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
-
1335
-
1342#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
-
1343
-
1354/* Memory mapping of Core Hardware */
-
1355#define SCS_BASE_SHIFT (0x0000E000UL)
-
1356#define ITM_BASE_SHIFT (0x00000000UL)
-
1357#define DWT_BASE_SHIFT (0x00001000UL)
-
1358#define TPI_BASE_SHIFT (0x00040000UL)
-
1359#define CoreDebug_BASE_SHIFT (0x0000EDF0UL)
-
-
1361typedef struct _cortex_memory
-
1362{
-
1363 uint8_t CORTEX_PERIPH_BASE[0xE0100000 - 0xE0000000];
-
1364}MCU_CortexMemoryTypeDef;
-
-
1365extern MCU_CortexMemoryTypeDef MCU_CORTEX_MEM;
-
1366
-
1367#define SCS_BASE (MCU_CORTEX_MEM.CORTEX_PERIPH_BASE) + SCS_BASE_SHIFT
-
1368#define ITM_BASE (MCU_CORTEX_MEM.CORTEX_PERIPH_BASE) + SCS_BASE_SHIFT
-
1369#define DWT_BASE (MCU_CORTEX_MEM.CORTEX_PERIPH_BASE) + SCS_BASE_SHIFT
-
1370#define TPI_BASE (MCU_CORTEX_MEM.CORTEX_PERIPH_BASE) + SCS_BASE_SHIFT
-
1371#define CoreDebug_BASE (MCU_CORTEX_MEM.CORTEX_PERIPH_BASE) + SCS_BASE_SHIFT
-
1372#define SysTick_BASE (SCS_BASE + 0x0010UL)
-
1373#define NVIC_BASE (SCS_BASE + 0x0100UL)
-
1374#define SCB_BASE (SCS_BASE + 0x0D00UL)
-
1376#define SCnSCB ((SCnSCB_Type *) SCS_BASE )
-
1377#define SCB ((SCB_Type *) SCB_BASE )
-
1378#define SysTick ((SysTick_Type *) SysTick_BASE )
-
1379#define NVIC ((NVIC_Type *) NVIC_BASE )
-
1380#define ITM ((ITM_Type *) ITM_BASE )
-
1381#define DWT ((DWT_Type *) DWT_BASE )
-
1382#define TPI ((TPI_Type *) TPI_BASE )
-
1384#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
-
1385#define MPU_BASE (SCS_BASE + 0x0D90UL)
-
1386#define MPU ((MPU_Type *) MPU_BASE )
-
1387#endif
-
1388
-
1389#define FPU_BASE (SCS_BASE + 0x0F30UL)
-
1390#define FPU ((FPU_Type *) FPU_BASE )
-
1398/*******************************************************************************
-
1399 * Hardware Abstraction Layer
-
1400 Core Function Interface contains:
-
1401 - Core NVIC Functions
-
1402 - Core SysTick Functions
-
1403 - Core Debug Functions
-
1404 - Core Register Access Functions
-
1405 ******************************************************************************/
-
1412/* ########################## NVIC functions #################################### */
-
1420#ifdef CMSIS_NVIC_VIRTUAL
-
1421 #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
-
1422 #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
-
1423 #endif
-
1424 #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
-
1425#else
-
1426 #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
-
1427 #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
-
1428 #define NVIC_EnableIRQ __NVIC_EnableIRQ
-
1429 #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
-
1430 #define NVIC_DisableIRQ __NVIC_DisableIRQ
-
1431 #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
-
1432 #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
-
1433 #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
-
1434 #define NVIC_GetActive __NVIC_GetActive
-
1435 #define NVIC_SetPriority __NVIC_SetPriority
-
1436 #define NVIC_GetPriority __NVIC_GetPriority
-
1437 #define NVIC_SystemReset __NVIC_SystemReset
-
1438#endif /* CMSIS_NVIC_VIRTUAL */
-
1439
-
1440#ifdef CMSIS_VECTAB_VIRTUAL
-
1441 #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
-
1442 #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
-
1443 #endif
-
1444 #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
-
1445#else
-
1446 #define NVIC_SetVector __NVIC_SetVector
-
1447 #define NVIC_GetVector __NVIC_GetVector
-
1448#endif /* (CMSIS_VECTAB_VIRTUAL) */
-
1449
-
1450#define NVIC_USER_IRQ_OFFSET 16
-
1451
-
1452
-
1453/* The following EXC_RETURN values are saved the LR on exception entry */
-
1454#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
-
1455#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
-
1456#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
-
1457#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */
-
1458#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */
-
1459#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */
-
1460
-
1461
-
-
1471__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
-
1472{
-
1473 uint32_t reg_value;
-
1474 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
-
1475
-
1476 reg_value = SCB->AIRCR; /* read old register configuration */
-
1477 reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
-
1478 reg_value = (reg_value |
-
1479 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
-
1480 (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
-
1481 SCB->AIRCR = reg_value;
-
1482}
-
-
1483
-
1484
- -
1494
-
1495
-
-
1502__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
-
1503{
-
1504 if ((int32_t)(IRQn) >= 0)
-
1505 {
-
1506 NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
-
1507 }
-
1508}
-
-
1509
-
1510
-
-
1519__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
-
1520{
-
1521 if ((int32_t)(IRQn) >= 0)
-
1522 {
-
1523 return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-
1524 }
-
1525 else
-
1526 {
-
1527 return(0U);
-
1528 }
-
1529}
-
-
1530
-
1531
-
-
1538__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
-
1539{
-
1540 if ((int32_t)(IRQn) >= 0)
-
1541 {
-
1542 NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
-
1543 __DSB();
-
1544 __ISB();
-
1545 }
-
1546}
-
-
1547
-
1548
-
-
1557__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
-
1558{
-
1559 if ((int32_t)(IRQn) >= 0)
-
1560 {
-
1561 return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-
1562 }
-
1563 else
-
1564 {
-
1565 return(0U);
-
1566 }
-
1567}
-
-
1568
-
1569
-
-
1576__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
-
1577{
-
1578 if ((int32_t)(IRQn) >= 0)
-
1579 {
-
1580 NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
-
1581 }
-
1582}
-
-
1583
-
1584
-
-
1591__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-
1592{
-
1593 if ((int32_t)(IRQn) >= 0)
-
1594 {
-
1595 NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
-
1596 }
-
1597}
-
-
1598
-
1599
-
-
1608__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
-
1609{
-
1610 if ((int32_t)(IRQn) >= 0)
-
1611 {
-
1612 return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-
1613 }
-
1614 else
-
1615 {
-
1616 return(0U);
-
1617 }
-
1618}
-
-
1619
-
1620
-
-
1630__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
-
1631{
-
1632 if ((int32_t)(IRQn) >= 0)
-
1633 {
-
1634 NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
-
1635 }
-
1636 else
-
1637 {
-
1638 SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
-
1639 }
-
1640}
-
-
1641
-
1642
-
-
1652__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
-
1653{
-
1654
-
1655 if ((int32_t)(IRQn) >= 0)
-
1656 {
-
1657 return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
-
1658 }
-
1659 else
-
1660 {
-
1661 return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
-
1662 }
-
1663}
-
-
1664
-
1665
-
-
1677__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
-
1678{
-
1679 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
-
1680 uint32_t PreemptPriorityBits;
-
1681 uint32_t SubPriorityBits;
-
1682
-
1683 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
-
1684 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
-
1685
-
1686 return (
-
1687 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
-
1688 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
-
1689 );
-
1690}
-
-
1691
-
1692
-
-
1704__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
-
1705{
-
1706 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
-
1707 uint32_t PreemptPriorityBits;
-
1708 uint32_t SubPriorityBits;
-
1709
-
1710 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
-
1711 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
-
1712
-
1713 *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
-
1714 *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
-
1715}
-
-
1716
-
1717
-
-
1727__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
-
1728{
-
1729 uint32_t *vectors = (uint32_t *)SCB->VTOR;
-
1730 vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
-
1731}
-
-
1732
-
1733
-
-
1742__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
-
1743{
-
1744 uint32_t *vectors = (uint32_t *)SCB->VTOR;
-
1745 return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
-
1746}
-
-
1747
-
1748
-
-
1753__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
-
1754{
-
1755 __DSB(); /* Ensure all outstanding memory accesses included
-
1756 buffered write are completed before reset */
-
1757 SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
-
1758 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
-
1759 SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
-
1760 __DSB(); /* Ensure completion of memory access */
-
1761
-
1762 for(;;) /* wait until reset */
-
1763 {
-
1764 __NOP();
-
1765 }
-
1766}
-
-
1767
-
1770/* ########################## MPU functions #################################### */
-
1771
-
1772#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
-
1773
-
1774//#include "mpu_armv7.h"
-
1775
-
1776#endif
-
1777
-
1778
-
1779/* ########################## FPU functions #################################### */
-
-
1795__STATIC_INLINE uint32_t SCB_GetFPUType(void)
-
1796{
-
1797 uint32_t mvfr0;
-
1798
-
1799 mvfr0 = FPU->MVFR0;
-
1800 if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
-
1801 {
-
1802 return 1U; /* Single precision FPU */
-
1803 }
-
1804 else
-
1805 {
-
1806 return 0U; /* No FPU */
-
1807 }
-
1808}
-
-
1809
-
1810
-
1815/* ################################## SysTick function ############################################ */
-
1823#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
-
1824
-
1836__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
-
1837{
-
1838 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
-
1839 {
-
1840 return (1UL); /* Reload value impossible */
-
1841 }
-
1842
-
1843 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
-
1844 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
-
1845 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
-
1846 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
-
1847 SysTick_CTRL_TICKINT_Msk |
-
1848 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
-
1849 return (0UL); /* Function successful */
-
1850}
-
1851
-
1852#endif
-
1853
-
1858/* ##################################### Debug In/Output function ########################################### */
-
1866extern volatile int32_t ITM_RxBuffer;
-
1867#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U)
-
-
1878__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
-
1879{
-
1880 if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
-
1881 ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
-
1882 {
-
1883 while (ITM->PORT[0U].u32 == 0UL)
-
1884 {
-
1885 __NOP();
-
1886 }
-
1887 ITM->PORT[0U].u8 = (uint8_t)ch;
-
1888 }
-
1889 return (ch);
-
1890}
-
-
1891
-
1892
-
-
1899__STATIC_INLINE int32_t ITM_ReceiveChar (void)
-
1900{
-
1901 int32_t ch = -1; /* no character available */
-
1902
-
1903 if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
-
1904 {
-
1905 ch = ITM_RxBuffer;
-
1906 ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
-
1907 }
-
1908
-
1909 return (ch);
-
1910}
-
-
1911
-
1912
-
-
1919__STATIC_INLINE int32_t ITM_CheckChar (void)
-
1920{
-
1921
-
1922 if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
-
1923 {
-
1924 return (0); /* no character available */
-
1925 }
-
1926 else
-
1927 {
-
1928 return (1); /* character available */
-
1929 }
-
1930}
-
-
1931
-
1937#ifdef __cplusplus
-
1938}
-
1939#endif
-
1940
-
1941
-
1942#endif /* __CMSIS_GENERIC */
-
__DSB
#define __DSB()
Data Synchronization Barrier.
Definition arm_defines.h:131
-
__NOP
#define __NOP()
No Operation.
Definition arm_defines.h:98
-
__NO_RETURN
#define __NO_RETURN
Definition arm_defines.h:27
-
__ISB
#define __ISB()
Instruction Synchronization Barrier.
Definition arm_defines.h:124
-
__STATIC_INLINE
#define __STATIC_INLINE
Definition arm_defines.h:19
-
__OM
#define __OM
Definition core_cm4_matlab.h:27
-
__IM
#define __IM
Definition core_cm4_matlab.h:26
-
__IOM
#define __IOM
Definition core_cm4_matlab.h:28
-
SCB_GetFPUType
__STATIC_INLINE uint32_t SCB_GetFPUType(void)
get FPU type
Definition core_cm4_matlab.h:1795
-
__NVIC_SystemReset
__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
System Reset.
Definition core_cm4_matlab.h:1753
-
__NVIC_SetVector
__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
Set Interrupt Vector.
Definition core_cm4_matlab.h:1727
-
NVIC_DecodePriority
__STATIC_INLINE void NVIC_DecodePriority(uint32_t Priority, uint32_t PriorityGroup, uint32_t *const pPreemptPriority, uint32_t *const pSubPriority)
Decode Priority.
Definition core_cm4_matlab.h:1704
-
__NVIC_GetVector
__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
Get Interrupt Vector.
Definition core_cm4_matlab.h:1742
-
__NVIC_SetPriority
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
Set Interrupt Priority.
Definition core_cm4_matlab.h:1630
-
__NVIC_ClearPendingIRQ
__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
Clear Pending Interrupt.
Definition core_cm4_matlab.h:1591
-
__NVIC_GetPendingIRQ
__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
Get Pending Interrupt.
Definition core_cm4_matlab.h:1557
-
__NVIC_EnableIRQ
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
Enable Interrupt.
Definition core_cm4_matlab.h:1502
-
NVIC_USER_IRQ_OFFSET
#define NVIC_USER_IRQ_OFFSET
Definition core_cm4_matlab.h:1450
-
__NVIC_GetPriorityGrouping
__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
Get Priority Grouping.
Definition core_cm4_matlab.h:1490
-
__NVIC_GetActive
__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
Get Active Interrupt.
Definition core_cm4_matlab.h:1608
-
__NVIC_SetPendingIRQ
__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
Set Pending Interrupt.
Definition core_cm4_matlab.h:1576
-
__NVIC_GetEnableIRQ
__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
Get Interrupt Enable status.
Definition core_cm4_matlab.h:1519
-
NVIC_EncodePriority
__STATIC_INLINE uint32_t NVIC_EncodePriority(uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
Encode Priority.
Definition core_cm4_matlab.h:1677
-
__NVIC_DisableIRQ
__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
Disable Interrupt.
Definition core_cm4_matlab.h:1538
-
NVIC_SetPriority
#define NVIC_SetPriority
Definition core_cm4_matlab.h:1435
-
__NVIC_GetPriority
__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
Get Interrupt Priority.
Definition core_cm4_matlab.h:1652
-
__NVIC_SetPriorityGrouping
__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
Set Priority Grouping.
Definition core_cm4_matlab.h:1471
-
FPU_MVFR0_Double_precision_Msk
#define FPU_MVFR0_Double_precision_Msk
Definition core_cm4_matlab.h:1192
-
FPU_MVFR0_Single_precision_Msk
#define FPU_MVFR0_Single_precision_Msk
Definition core_cm4_matlab.h:1195
-
ITM_TCR_ITMENA_Msk
#define ITM_TCR_ITMENA_Msk
Definition core_cm4_matlab.h:678
-
SCB_AIRCR_PRIGROUP_Msk
#define SCB_AIRCR_PRIGROUP_Msk
Definition core_cm4_matlab.h:328
-
SCB_AIRCR_VECTKEY_Msk
#define SCB_AIRCR_VECTKEY_Msk
Definition core_cm4_matlab.h:319
-
SCB_AIRCR_VECTKEY_Pos
#define SCB_AIRCR_VECTKEY_Pos
Definition core_cm4_matlab.h:318
-
SCB_AIRCR_SYSRESETREQ_Msk
#define SCB_AIRCR_SYSRESETREQ_Msk
Definition core_cm4_matlab.h:331
-
SCB_AIRCR_PRIGROUP_Pos
#define SCB_AIRCR_PRIGROUP_Pos
Definition core_cm4_matlab.h:327
-
SysTick_CTRL_ENABLE_Msk
#define SysTick_CTRL_ENABLE_Msk
Definition core_cm4_matlab.h:579
-
SysTick_LOAD_RELOAD_Msk
#define SysTick_LOAD_RELOAD_Msk
Definition core_cm4_matlab.h:583
-
SysTick_CTRL_TICKINT_Msk
#define SysTick_CTRL_TICKINT_Msk
Definition core_cm4_matlab.h:576
-
SysTick_CTRL_CLKSOURCE_Msk
#define SysTick_CTRL_CLKSOURCE_Msk
Definition core_cm4_matlab.h:573
-
FPU_Type::FPDSCR
__IOM uint32_t FPDSCR
Definition core_cm4_matlab.h:1125
-
FPU_Type::MVFR1
__IM uint32_t MVFR1
Definition core_cm4_matlab.h:1127
-
SysTick_Type::LOAD
__IOM uint32_t LOAD
Definition core_cm4_matlab.h:563
-
SCB_Type::CFSR
__IOM uint32_t CFSR
Definition core_cm4_matlab.h:251
-
ITM_RxBuffer
volatile int32_t ITM_RxBuffer
-
DWT_Type::CYCCNT
__IOM uint32_t CYCCNT
Definition core_cm4_matlab.h:718
-
TPI_Type::SSPSR
__IM uint32_t SSPSR
Definition core_cm4_matlab.h:864
-
TPI_Type::CLAIMCLR
__IOM uint32_t CLAIMCLR
Definition core_cm4_matlab.h:884
-
DWT_Type::COMP3
__IOM uint32_t COMP3
Definition core_cm4_matlab.h:737
-
FPU_Type::FPCCR
__IOM uint32_t FPCCR
Definition core_cm4_matlab.h:1123
-
CONTROL_Type::FPCA
uint32_t FPCA
Definition core_cm4_matlab.h:178
-
ITM_Type::CID0
__IM uint32_t CID0
Definition core_cm4_matlab.h:642
-
DWT_Type::CPICNT
__IOM uint32_t CPICNT
Definition core_cm4_matlab.h:719
-
TPI_Type::FFSR
__IM uint32_t FFSR
Definition core_cm4_matlab.h:871
-
CONTROL_Type::nPRIV
uint32_t nPRIV
Definition core_cm4_matlab.h:176
-
DWT_Type::MASK2
__IOM uint32_t MASK2
Definition core_cm4_matlab.h:734
-
_cortex_memory::CORTEX_PERIPH_BASE
uint8_t CORTEX_PERIPH_BASE[0xE0100000 - 0xE0000000]
Definition core_cm4_matlab.h:1363
-
TPI_Type::FSCR
__IM uint32_t FSCR
Definition core_cm4_matlab.h:873
-
SCB_Type::DFSR
__IOM uint32_t DFSR
Definition core_cm4_matlab.h:253
-
SCB_Type::AFSR
__IOM uint32_t AFSR
Definition core_cm4_matlab.h:256
-
SCB_Type::BFAR
__IOM uint32_t BFAR
Definition core_cm4_matlab.h:255
-
ITM_Type::TCR
__IOM uint32_t TCR
Definition core_cm4_matlab.h:625
-
SCB_Type::SHCSR
__IOM uint32_t SHCSR
Definition core_cm4_matlab.h:250
-
TPI_Type::ACPR
__IOM uint32_t ACPR
Definition core_cm4_matlab.h:867
-
ITM_Type::PID4
__IM uint32_t PID4
Definition core_cm4_matlab.h:634
-
ITM_Type::u8
__OM uint8_t u8
Definition core_cm4_matlab.h:616
-
ITM_Type::CID1
__IM uint32_t CID1
Definition core_cm4_matlab.h:643
-
FPU_Type::FPCAR
__IOM uint32_t FPCAR
Definition core_cm4_matlab.h:1124
-
DWT_Type::MASK3
__IOM uint32_t MASK3
Definition core_cm4_matlab.h:738
-
TPI_Type::TRIGGER
__IM uint32_t TRIGGER
Definition core_cm4_matlab.h:875
-
APSR_Type::Z
uint32_t Z
Definition core_cm4_matlab.h:70
-
DWT_Type::COMP0
__IOM uint32_t COMP0
Definition core_cm4_matlab.h:725
-
DWT_Type::FOLDCNT
__IOM uint32_t FOLDCNT
Definition core_cm4_matlab.h:723
-
ITM_Type::PID2
__IM uint32_t PID2
Definition core_cm4_matlab.h:640
-
APSR_Type::Q
uint32_t Q
Definition core_cm4_matlab.h:67
-
ITM_Type::IWR
__OM uint32_t IWR
Definition core_cm4_matlab.h:627
-
xPSR_Type::T
uint32_t T
Definition core_cm4_matlab.h:126
-
ITM_Type::PID0
__IM uint32_t PID0
Definition core_cm4_matlab.h:638
-
DWT_Type::MASK1
__IOM uint32_t MASK1
Definition core_cm4_matlab.h:730
-
ITM_Type::LSR
__IM uint32_t LSR
Definition core_cm4_matlab.h:632
-
SCB_Type::ADR
__IM uint32_t ADR
Definition core_cm4_matlab.h:259
-
DWT_Type::PCSR
__IM uint32_t PCSR
Definition core_cm4_matlab.h:724
-
APSR_Type::C
uint32_t C
Definition core_cm4_matlab.h:69
-
TPI_Type::DEVTYPE
__IM uint32_t DEVTYPE
Definition core_cm4_matlab.h:887
-
ITM_Type::PID6
__IM uint32_t PID6
Definition core_cm4_matlab.h:636
-
DWT_Type::MASK0
__IOM uint32_t MASK0
Definition core_cm4_matlab.h:726
-
DWT_Type::FUNCTION2
__IOM uint32_t FUNCTION2
Definition core_cm4_matlab.h:735
-
CoreDebug_Type::DHCSR
__IOM uint32_t DHCSR
Definition core_cm4_matlab.h:1228
-
APSR_Type::_reserved1
uint32_t _reserved1
Definition core_cm4_matlab.h:66
-
TPI_Type::CLAIMSET
__IOM uint32_t CLAIMSET
Definition core_cm4_matlab.h:883
-
TPI_Type::ITATBCTR2
__IM uint32_t ITATBCTR2
Definition core_cm4_matlab.h:877
-
TPI_Type::ITATBCTR0
__IM uint32_t ITATBCTR0
Definition core_cm4_matlab.h:879
-
FPU_Type::MVFR0
__IM uint32_t MVFR0
Definition core_cm4_matlab.h:1126
-
SCB_Type::AIRCR
__IOM uint32_t AIRCR
Definition core_cm4_matlab.h:246
-
ITM_Type::TER
__IOM uint32_t TER
Definition core_cm4_matlab.h:621
-
ITM_RXBUFFER_EMPTY
#define ITM_RXBUFFER_EMPTY
Definition core_cm4_matlab.h:1867
-
APSR_Type::GE
uint32_t GE
Definition core_cm4_matlab.h:65
-
CoreDebug_Type::DEMCR
__IOM uint32_t DEMCR
Definition core_cm4_matlab.h:1231
-
TPI_Type::DEVID
__IM uint32_t DEVID
Definition core_cm4_matlab.h:886
-
DWT_Type::SLEEPCNT
__IOM uint32_t SLEEPCNT
Definition core_cm4_matlab.h:721
-
CoreDebug_Type::DCRSR
__OM uint32_t DCRSR
Definition core_cm4_matlab.h:1229
-
SCB_Type::CPACR
__IOM uint32_t CPACR
Definition core_cm4_matlab.h:263
-
SCB_Type::HFSR
__IOM uint32_t HFSR
Definition core_cm4_matlab.h:252
-
ITM_Type::CID3
__IM uint32_t CID3
Definition core_cm4_matlab.h:645
-
TPI_Type::FIFO1
__IM uint32_t FIFO1
Definition core_cm4_matlab.h:880
-
APSR_Type::N
uint32_t N
Definition core_cm4_matlab.h:71
-
xPSR_Type::ICI_IT_1
uint32_t ICI_IT_1
Definition core_cm4_matlab.h:123
-
TPI_Type::CSPSR
__IOM uint32_t CSPSR
Definition core_cm4_matlab.h:865
-
ITM_Type::PID5
__IM uint32_t PID5
Definition core_cm4_matlab.h:635
-
ITM_Type::PID3
__IM uint32_t PID3
Definition core_cm4_matlab.h:641
-
ITM_ReceiveChar
__STATIC_INLINE int32_t ITM_ReceiveChar(void)
ITM Receive Character.
Definition core_cm4_matlab.h:1899
-
SysTick_Type::CTRL
__IOM uint32_t CTRL
Definition core_cm4_matlab.h:562
-
APSR_Type::_reserved0
uint32_t _reserved0
Definition core_cm4_matlab.h:64
-
ITM_SendChar
__STATIC_INLINE uint32_t ITM_SendChar(uint32_t ch)
ITM Send Character.
Definition core_cm4_matlab.h:1878
-
SCB_Type::SCR
__IOM uint32_t SCR
Definition core_cm4_matlab.h:247
-
ITM_Type::LAR
__OM uint32_t LAR
Definition core_cm4_matlab.h:631
-
APSR_Type::V
uint32_t V
Definition core_cm4_matlab.h:68
-
TPI_Type::FIFO0
__IM uint32_t FIFO0
Definition core_cm4_matlab.h:876
-
SCB_Type::ICSR
__IOM uint32_t ICSR
Definition core_cm4_matlab.h:244
-
SCnSCB_Type::ICTR
__IM uint32_t ICTR
Definition core_cm4_matlab.h:523
-
APSR_Type::w
uint32_t w
Definition core_cm4_matlab.h:73
-
CoreDebug_Type::DCRDR
__IOM uint32_t DCRDR
Definition core_cm4_matlab.h:1230
-
DWT_Type::FUNCTION0
__IOM uint32_t FUNCTION0
Definition core_cm4_matlab.h:727
-
IPSR_Type::ISR
uint32_t ISR
Definition core_cm4_matlab.h:103
-
SCB_Type::CCR
__IOM uint32_t CCR
Definition core_cm4_matlab.h:248
-
ITM_Type::CID2
__IM uint32_t CID2
Definition core_cm4_matlab.h:644
-
NVIC_Type::STIR
__OM uint32_t STIR
Definition core_cm4_matlab.h:221
-
SCB_Type::CPUID
__IM uint32_t CPUID
Definition core_cm4_matlab.h:243
-
CONTROL_Type::SPSEL
uint32_t SPSEL
Definition core_cm4_matlab.h:177
-
xPSR_Type::ICI_IT_2
uint32_t ICI_IT_2
Definition core_cm4_matlab.h:127
-
SCB_Type::DFR
__IM uint32_t DFR
Definition core_cm4_matlab.h:258
-
ITM_Type::IRR
__IM uint32_t IRR
Definition core_cm4_matlab.h:628
-
SCB_Type::VTOR
__IOM uint32_t VTOR
Definition core_cm4_matlab.h:245
-
ITM_CheckChar
__STATIC_INLINE int32_t ITM_CheckChar(void)
ITM Check Character.
Definition core_cm4_matlab.h:1919
-
TPI_Type::ITCTRL
__IOM uint32_t ITCTRL
Definition core_cm4_matlab.h:881
-
SysTick_Type::VAL
__IOM uint32_t VAL
Definition core_cm4_matlab.h:564
-
DWT_Type::LSUCNT
__IOM uint32_t LSUCNT
Definition core_cm4_matlab.h:722
-
ITM_Type::u32
__OM uint32_t u32
Definition core_cm4_matlab.h:618
-
DWT_Type::FUNCTION1
__IOM uint32_t FUNCTION1
Definition core_cm4_matlab.h:731
-
ITM_Type::u16
__OM uint16_t u16
Definition core_cm4_matlab.h:617
-
TPI_Type::SPPR
__IOM uint32_t SPPR
Definition core_cm4_matlab.h:869
-
SCB_Type::MMFAR
__IOM uint32_t MMFAR
Definition core_cm4_matlab.h:254
-
SysTick_Type::CALIB
__IM uint32_t CALIB
Definition core_cm4_matlab.h:565
-
DWT_Type::COMP2
__IOM uint32_t COMP2
Definition core_cm4_matlab.h:733
-
ITM_Type::IMCR
__IOM uint32_t IMCR
Definition core_cm4_matlab.h:629
-
ITM_Type::PID7
__IM uint32_t PID7
Definition core_cm4_matlab.h:637
-
DWT_Type::COMP1
__IOM uint32_t COMP1
Definition core_cm4_matlab.h:729
-
ITM_Type::PID1
__IM uint32_t PID1
Definition core_cm4_matlab.h:639
-
SCnSCB_Type::ACTLR
__IOM uint32_t ACTLR
Definition core_cm4_matlab.h:524
-
DWT_Type::FUNCTION3
__IOM uint32_t FUNCTION3
Definition core_cm4_matlab.h:739
-
DWT_Type::EXCCNT
__IOM uint32_t EXCCNT
Definition core_cm4_matlab.h:720
-
TPI_Type::FFCR
__IOM uint32_t FFCR
Definition core_cm4_matlab.h:872
-
ITM_Type::TPR
__IOM uint32_t TPR
Definition core_cm4_matlab.h:623
-
MCU_CortexMemoryTypeDef
struct _cortex_memory MCU_CortexMemoryTypeDef
-
MCU_CORTEX_MEM
MCU_CortexMemoryTypeDef MCU_CORTEX_MEM
Definition stm32f4xx_matlab_conf.c:9
-
SCB
#define SCB
Definition core_cm4_matlab.h:1377
-
ITM
#define ITM
Definition core_cm4_matlab.h:1380
-
FPU
#define FPU
Definition core_cm4_matlab.h:1390
-
NVIC
#define NVIC
Definition core_cm4_matlab.h:1379
-
SysTick
#define SysTick
Definition core_cm4_matlab.h:1378
-
__NVIC_PRIO_BITS
#define __NVIC_PRIO_BITS
Definition stm32f407xx_matlab.h:60
-
IRQn_Type
IRQn_Type
STM32F4XX Interrupt Number Definition, according to the selected device in Library_configuration_sect...
Definition stm32f407xx_matlab.h:77
-
SysTick_IRQn
@ SysTick_IRQn
Definition stm32f407xx_matlab.h:86
-
uint32_t
unsigned int uint32_t
Definition stdint.h:64
-
int32_t
signed int int32_t
Definition stdint.h:58
-
uint8_t
unsigned char uint8_t
Definition stdint.h:62
-
uint16_t
unsigned short int uint16_t
Definition stdint.h:63
-
_cortex_memory
Definition core_cm4_matlab.h:1362
-
CoreDebug_Type
Structure type to access the Core Debug Register (CoreDebug).
Definition core_cm4_matlab.h:1227
-
DWT_Type
Structure type to access the Data Watchpoint and Trace Register (DWT).
Definition core_cm4_matlab.h:716
-
FPU_Type
Structure type to access the Floating Point Unit (FPU).
Definition core_cm4_matlab.h:1121
-
ITM_Type
Structure type to access the Instrumentation Trace Macrocell Register (ITM).
Definition core_cm4_matlab.h:613
-
NVIC_Type
Structure type to access the Nested Vectored Interrupt Controller (NVIC).
Definition core_cm4_matlab.h:208
-
SCB_Type
Structure type to access the System Control Block (SCB).
Definition core_cm4_matlab.h:242
-
SCnSCB_Type
Structure type to access the System Control and ID Register not in the SCB.
Definition core_cm4_matlab.h:521
-
SysTick_Type
Structure type to access the System Timer (SysTick).
Definition core_cm4_matlab.h:561
-
TPI_Type
Structure type to access the Trace Port Interface Register (TPI).
Definition core_cm4_matlab.h:863
-
APSR_Type
Union type to access the Application Program Status Register (APSR).
Definition core_cm4_matlab.h:61
-
CONTROL_Type
Union type to access the Control Registers (CONTROL).
Definition core_cm4_matlab.h:173
-
IPSR_Type
Union type to access the Interrupt Program Status Register (IPSR).
Definition core_cm4_matlab.h:100
-
xPSR_Type
Union type to access the Special-Purpose Program Status Registers (xPSR).
Definition core_cm4_matlab.h:118
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- -
-Generated by doxygen 1.10.0 -
- - diff --git a/DOCS/html/darkmode_toggle.js b/DOCS/html/darkmode_toggle.js new file mode 100644 index 0000000..b9c7364 --- /dev/null +++ b/DOCS/html/darkmode_toggle.js @@ -0,0 +1,222 @@ +/** + +The code below is based on the Doxygen Awesome project with some minor modifications +https://github.com/jothepro/doxygen-awesome-css + +MIT License + +Copyright (c) 2021 - 2022 jothepro + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in all +copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +SOFTWARE. + +*/ + +class DarkModeToggle extends HTMLElement { + + static darkmode_cookie_name = ''+'prefers-dark'; + static lightmode_cookie_name = ''+'prefers-light'; + + static icon = ''; + static title = "Toggle Light/Dark Mode" + + static prefersLightModeInDarkModeKey = "prefers-light-mode-in-dark-mode" + static prefersDarkModeInLightModeKey = "prefers-dark-mode-in-light-mode" + + static _staticConstructor = function() { + DarkModeToggle.enableDarkMode(DarkModeToggle.userPreference) + // Update the color scheme when the browsers preference changes + // without user interaction on the website. + window.matchMedia('(prefers-color-scheme: dark)').addEventListener('change', event => { + DarkModeToggle.onSystemPreferenceChanged() + }) + // Update the color scheme when the tab is made visible again. + // It is possible that the appearance was changed in another tab + // while this tab was in the background. + document.addEventListener("visibilitychange", visibilityState => { + if (document.visibilityState === 'visible') { + DarkModeToggle.onSystemPreferenceChanged() + } + }); + }() + + static init() { + $(function() { + $(document).ready(function() { + const toggleButton = document.createElement('dark-mode-toggle') + toggleButton.title = DarkModeToggle.title + toggleButton.innerHTML = DarkModeToggle.icon + toggleButton.tabIndex = 0; + + function addButton() { + const titleArea = document.getElementById("titlearea"); + const searchBox = document.getElementById("MSearchBox"); + const mainMenu = document.getElementById("main-menu"); + const navRow1 = document.getElementById("navrow1"); + let mainMenuVisible = false; + if (mainMenu) { + const menuStyle = window.getComputedStyle(mainMenu); + mainMenuVisible = menuStyle.display!=='none' + } + const searchBoxPos1 = document.getElementById("searchBoxPos1"); + if (searchBox) { // (1) search box visible + searchBox.parentNode.appendChild(toggleButton) + } else if (navRow1) { // (2) no search box, static menu bar + const li = document.createElement('li'); + li.style = 'float: right;' + li.appendChild(toggleButton); + toggleButton.style = 'width: 24px; height: 25px; padding-top: 11px; float: right;'; + const row = document.querySelector('#navrow1 > ul:first-of-type'); + row.appendChild(li) + } else if (mainMenu && mainMenuVisible) { // (3) no search box + dynamic menu bar expanded + const li = document.createElement('li'); + li.style = 'float: right;' + li.appendChild(toggleButton); + toggleButton.style = 'width: 14px; height: 36px; padding-top: 10px; float: right;'; + mainMenu.appendChild(li) + } else if (searchBoxPos1) { // (4) no search box + dynamic menu bar collapsed + toggleButton.style = 'width: 24px; height: 36px; padding-top: 10px; float: right;'; + searchBoxPos1.style = 'top: 0px;' + searchBoxPos1.appendChild(toggleButton); + } else if (titleArea) { // (5) no search box and no navigation tabs + toggleButton.style = 'width: 24px; height: 24px; position: absolute; right: 0px; top: 34px;'; + titleArea.append(toggleButton); + } + } + + $(document).ready(() => addButton()); + $(window).resize(() => addButton()); + let inFocus = false; + $(document).focusin(() => inFocus = true); + $(document).focusout(() => inFocus = false); + $(document).keyup(function(e) { + if (e.keyCode==27 && !inFocus) { // escape key maps to keycode `27` + e.stopPropagation(); + DarkModeToggle.userPreference = !DarkModeToggle.userPreference + } + }) + DarkModeToggle.setDarkModeVisibility(DarkModeToggle.darkModeEnabled) + }) + }) + } + + constructor() { + super(); + this.onclick=this.toggleDarkMode + this.onkeypress=function(e){if (e.keyCode==13) { this.toggleDarkMode(); }}; + } + + /** + * @returns `true` for dark-mode, `false` for light-mode system preference + */ + static get systemPreference() { + return window.matchMedia('(prefers-color-scheme: dark)').matches + } + + static get prefersDarkModeInLightMode() { + return Cookie.readSetting(DarkModeToggle.darkmode_cookie_name,'0')=='1'; + } + + static set prefersDarkModeInLightMode(preference) { + if (preference) { + Cookie.writeSetting(DarkModeToggle.darkmode_cookie_name,'1'); + } else { + Cookie.eraseSetting(DarkModeToggle.darkmode_cookie_name); + } + } + + static get prefersLightModeInDarkMode() { + return Cookie.readSetting(DarkModeToggle.lightmode_cookie_name,'0')=='1' + } + + static set prefersLightModeInDarkMode(preference) { + if (preference) { + Cookie.writeSetting(DarkModeToggle.lightmode_cookie_name,'1'); + } else { + Cookie.eraseSetting(DarkModeToggle.lightmode_cookie_name); + } + } + + /** + * @returns `true` for dark-mode, `false` for light-mode user preference + */ + static get userPreference() { + return (!DarkModeToggle.systemPreference && DarkModeToggle.prefersDarkModeInLightMode) || + (DarkModeToggle.systemPreference && !DarkModeToggle.prefersLightModeInDarkMode) + } + + static set userPreference(userPreference) { + DarkModeToggle.darkModeEnabled = userPreference + if (!userPreference) { + if (DarkModeToggle.systemPreference) { + DarkModeToggle.prefersLightModeInDarkMode = true + } else { + DarkModeToggle.prefersDarkModeInLightMode = false + } + } else { + if (!DarkModeToggle.systemPreference) { + DarkModeToggle.prefersDarkModeInLightMode = true + } else { + DarkModeToggle.prefersLightModeInDarkMode = false + } + } + DarkModeToggle.onUserPreferenceChanged() + } + + static setDarkModeVisibility(enable) { + let darkModeStyle, lightModeStyle; + if(enable) { + darkModeStyle = 'inline-block'; + lightModeStyle = 'none' + } else { + darkModeStyle = 'none'; + lightModeStyle = 'inline-block' + } + document.querySelectorAll('.dark-mode-visible' ).forEach(el => el.style.display = darkModeStyle); + document.querySelectorAll('.light-mode-visible').forEach(el => el.style.display = lightModeStyle); + } + static enableDarkMode(enable) { + if(enable) { + DarkModeToggle.darkModeEnabled = true + document.documentElement.classList.add("dark-mode") + document.documentElement.classList.remove("light-mode") + } else { + DarkModeToggle.darkModeEnabled = false + document.documentElement.classList.remove("dark-mode") + document.documentElement.classList.add("light-mode") + } + DarkModeToggle.setDarkModeVisibility(enable) + } + + static onSystemPreferenceChanged() { + DarkModeToggle.darkModeEnabled = DarkModeToggle.userPreference + DarkModeToggle.enableDarkMode(DarkModeToggle.darkModeEnabled) + } + + static onUserPreferenceChanged() { + DarkModeToggle.enableDarkMode(DarkModeToggle.darkModeEnabled) + } + + toggleDarkMode() { + DarkModeToggle.userPreference = !DarkModeToggle.userPreference + } +} + +customElements.define("dark-mode-toggle", DarkModeToggle); + +DarkModeToggle.init(); diff --git a/DOCS/html/dir_000002_000001.html b/DOCS/html/dir_000002_000001.html deleted file mode 100644 index 6aa360c..0000000 --- a/DOCS/html/dir_000002_000001.html +++ /dev/null @@ -1,84 +0,0 @@ - - - - - - - -STM MATLAB Simulator: F:/Work/Projects/MATLAB/matlab_stm_emulate/MCU_STM32F4xx_Matlab -> Drivers Relation - - - - - - - - - - - -
-
- - - - - - -
-
STM MATLAB Simulator -
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MCU_STM32F4xx_Matlab → Drivers Relation

File in MCU_STM32F4xx_MatlabIncludes file in MCU_STM32F4xx_Matlab/Drivers
stm32f4xx_matlab_conf.hSTM32F4xx_SIMULINK / stm32f4xx_matlab_gpio.h
stm32f4xx_matlab_conf.hSTM32F4xx_SIMULINK / stm32f4xx_matlab_rcc.h
stm32f4xx_matlab_conf.hSTM32F4xx_SIMULINK / stm32f4xx_matlab_tim.h
Drivers / STM32F4xx_SIMULINK / stm32f4xx_periph_registers.cCMSIS / stm32f407xx_matlab.h
- -
-Generated by doxygen 1.10.0 -
- - diff --git a/DOCS/html/dir_000002_000003.html b/DOCS/html/dir_000002_000003.html index b0928a7..4986495 100644 --- a/DOCS/html/dir_000002_000003.html +++ b/DOCS/html/dir_000002_000003.html @@ -14,6 +14,7 @@ + @@ -75,7 +76,7 @@ $(function() {
-

MCU_STM32F4xx_Matlab → MCU_Wrapper Relation

File in MCU_STM32F4xx_MatlabIncludes file in MCU_Wrapper
stm32f4xx_matlab_conf.cmcu_wrapper_conf.h
Drivers / STM32F4xx_SIMULINK / stm32f4xx_matlab_gpio.hmcu_wrapper_conf.h
Drivers / STM32F4xx_SIMULINK / stm32f4xx_matlab_rcc.hmcu_wrapper_conf.h
Drivers / STM32F4xx_SIMULINK / stm32f4xx_matlab_tim.hmcu_wrapper_conf.h
+

MCU_STM32F4xx_Matlab → MCU_Wrapper Relation

File in MCU_STM32F4xx_MatlabIncludes file in MCU_Wrapper
stm32f4xx_matlab_conf.cmcu_wrapper_conf.h
STM32F4xx_SIMULINK / stm32f4xx_matlab_gpio.hmcu_wrapper_conf.h
STM32F4xx_SIMULINK / stm32f4xx_matlab_rcc.hmcu_wrapper_conf.h
STM32F4xx_SIMULINK / stm32f4xx_matlab_tim.hmcu_wrapper_conf.h
Generated by doxygen 1.10.0 diff --git a/DOCS/html/dir_000004_000000.html b/DOCS/html/dir_000002_000004.html similarity index 72% rename from DOCS/html/dir_000004_000000.html rename to DOCS/html/dir_000002_000004.html index 7c2354e..4dcb975 100644 --- a/DOCS/html/dir_000004_000000.html +++ b/DOCS/html/dir_000002_000004.html @@ -5,7 +5,7 @@ -STM MATLAB Simulator: F:/Work/Projects/MATLAB/matlab_stm_emulate/MCU_STM32F4xx_Matlab/Drivers/STM32F4xx_SIMULINK -> CMSIS Relation +STM MATLAB Simulator: F:/Work/Projects/MATLAB/matlab_stm_emulate/MCU_STM32F4xx_Matlab -> STM32F4xx_SIMULINK Relation @@ -14,6 +14,7 @@ + @@ -71,11 +72,11 @@ $(function() {
-

STM32F4xx_SIMULINK → CMSIS Relation

File in MCU_STM32F4xx_Matlab/Drivers/STM32F4xx_SIMULINKIncludes file in MCU_STM32F4xx_Matlab/Drivers/CMSIS
stm32f4xx_periph_registers.cstm32f407xx_matlab.h
+

MCU_STM32F4xx_Matlab → STM32F4xx_SIMULINK Relation

File in MCU_STM32F4xx_MatlabIncludes file in MCU_STM32F4xx_Matlab/STM32F4xx_SIMULINK
stm32f4xx_matlab_conf.hstm32f4xx_matlab_gpio.h
stm32f4xx_matlab_conf.hstm32f4xx_matlab_rcc.h
stm32f4xx_matlab_conf.hstm32f4xx_matlab_tim.h
Generated by doxygen 1.10.0 diff --git a/DOCS/html/dir_000003_000002.html b/DOCS/html/dir_000003_000002.html index 5f73831..38a8d55 100644 --- a/DOCS/html/dir_000003_000002.html +++ b/DOCS/html/dir_000003_000002.html @@ -14,6 +14,7 @@ + diff --git a/DOCS/html/dir_000004_000003.html b/DOCS/html/dir_000004_000003.html index 1e09c27..20755e3 100644 --- a/DOCS/html/dir_000004_000003.html +++ b/DOCS/html/dir_000004_000003.html @@ -5,7 +5,7 @@ -STM MATLAB Simulator: F:/Work/Projects/MATLAB/matlab_stm_emulate/MCU_STM32F4xx_Matlab/Drivers/STM32F4xx_SIMULINK -> MCU_Wrapper Relation +STM MATLAB Simulator: F:/Work/Projects/MATLAB/matlab_stm_emulate/MCU_STM32F4xx_Matlab/STM32F4xx_SIMULINK -> MCU_Wrapper Relation @@ -14,6 +14,7 @@ + @@ -71,11 +72,11 @@ $(function() {
-

STM32F4xx_SIMULINK → MCU_Wrapper Relation

File in MCU_STM32F4xx_Matlab/Drivers/STM32F4xx_SIMULINKIncludes file in MCU_Wrapper
stm32f4xx_matlab_gpio.hmcu_wrapper_conf.h
stm32f4xx_matlab_rcc.hmcu_wrapper_conf.h
stm32f4xx_matlab_tim.hmcu_wrapper_conf.h
+

STM32F4xx_SIMULINK → MCU_Wrapper Relation

File in MCU_STM32F4xx_Matlab/STM32F4xx_SIMULINKIncludes file in MCU_Wrapper
stm32f4xx_matlab_gpio.hmcu_wrapper_conf.h
stm32f4xx_matlab_rcc.hmcu_wrapper_conf.h
stm32f4xx_matlab_tim.hmcu_wrapper_conf.h
Generated by doxygen 1.10.0 diff --git a/DOCS/html/dir_30f2d142c55236add84215456f0e2b1c.html b/DOCS/html/dir_30f2d142c55236add84215456f0e2b1c.html index 12c1548..c8a5c04 100644 --- a/DOCS/html/dir_30f2d142c55236add84215456f0e2b1c.html +++ b/DOCS/html/dir_30f2d142c55236add84215456f0e2b1c.html @@ -14,6 +14,7 @@ + @@ -92,19 +93,8 @@ $(function() { - - - - - - - - - - - - + +

Files

 arm_defines.h
 
 core_cm4_matlab.h
 
 stdint.h
 
 stm32f407xx_matlab.h
 
 stm32f4xx.h
 
 system_stm32f4xx.h
 CMSIS Cortex-M4 Device System Source File for STM32F4xx devices.
-
 stm32f407xx_matlab_memory.h
 Ð—аголовочный файл Ð´Ð»Ñ Ð¾Ð¿Ñ€ÐµÐ´ÐµÐ»ÐµÐ½Ð¸Ñ Ð¿Ð°Ð¼Ñти МК STM32F4xx.
 
diff --git a/DOCS/html/dir_3a36e4bca13e6b41578f51df425c6641_dep.map b/DOCS/html/dir_3a36e4bca13e6b41578f51df425c6641_dep.map deleted file mode 100644 index 7327ab7..0000000 --- a/DOCS/html/dir_3a36e4bca13e6b41578f51df425c6641_dep.map +++ /dev/null @@ -1,10 +0,0 @@ - - - - - - - - - - diff --git a/DOCS/html/dir_3a36e4bca13e6b41578f51df425c6641_dep.md5 b/DOCS/html/dir_3a36e4bca13e6b41578f51df425c6641_dep.md5 deleted file mode 100644 index 81d9ea2..0000000 --- a/DOCS/html/dir_3a36e4bca13e6b41578f51df425c6641_dep.md5 +++ /dev/null @@ -1 +0,0 @@ -ce35e947ba90c2e5d27c945482285b79 \ No newline at end of file diff --git a/DOCS/html/dir_3a36e4bca13e6b41578f51df425c6641_dep.png b/DOCS/html/dir_3a36e4bca13e6b41578f51df425c6641_dep.png deleted file mode 100644 index 86b7e4c1b8e2d92a89b7b91d33745066c441e38f..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 4230 zcmZ`+c{CJW`yY{1BOJGPO@HX3S#7DNVRiEJ}=#!kpE$YgxU z8ehn^L(D?em;rUZA^KOi5&v~0KDdAMmGQe z4ny|5nTMNgdsFjU*#ozirKu6%;7`XA%F_V=eqD2;tM>Qu81s>6_r)mE_vL)Tbo+K% zueV$K7ll~(}ypMNDz{(;`lPi;_SXQ(2Q}Wzz!`oJBDzAN?e|UW~&O{+V-ahwT zB913EjmN9bO~y*C)8Gzg;q-~i?@m9cB-AG+XAuTFSl$pdT|JoJa2|L$@71s9lFW$Z zIjZQl``b|?kxNRTRTy_v}#(XU=G_oc2`*uZ4 zXV1o?Ba-(JyIUzj9`omr<*12v|3o^zFGX^!Hec60s|iBs3*Ga9<<^C9H4`I5q65}D zgr;Iv-(PJ$k|5MmA1YrI1mJgK@3+&*@4P|_mzIc?`Q$Yf}?YhhoX7%|0nf|nvKcB5_%^(ZcNIXZl= zb^7;@C(YA(Nj1k|9h{}1YE~&PENTT`9(&&-eO{>Ap!i25e26yR?s)>I!aH&<`^VFX z%vh%e=Fw}PMh=X$q2`Zcg)V_@J_D9_;;aZrbK`Gn>*zjO}R7O?70i2u(#)mCQ5{#rQt1|=il zh~6~_k#tSu(1i-vv@?$(fS(EEFcA1_h(3VlMk0qE%J=XC(F7qfBXwEX1_v!rfGTLN(Rc@^Qe3eE)Dun54LbSh&a1Yn%1RR#rPhHAYwUecoiKj;E$jfA0a-lO=HN{-y8Rg`DM>)o{sm7`JQjnSZ|9(M0&&#$X;}m1ML@S0r^9D zonaW5$hd=8=oj5?zNFd*3b$^^-iN*!A8nt$PMFXmv?!eDxZ?Df|7sF)L@gpvEh5c+ zR(F6e!Ar?*;d|cYKuniMB|QmRv4sTfAfLH9PpMb3nbaNK9T+prrg=^`voMr zLks~G$ihjmgv6EpzKgOq9{6d@#iE8n*btg+jj+vr8Y@LIn>3j}CVk2ZJMsK>SY3uZ z;b1ALP$GEPNs>Gr`E7-8I;Nsw=fqQlm9%nU?85xc+-VY&Mtz@nIITos29Aq94=Qf8 zZldOdH4pC*M?k)*@LCAgW^WHCC7y8YEc9M)rqk2VZ2V5HmYck}(;)9Mv*U(f@mENf z_;}M(7<_Z}LR67lm2VhHvkMFov;Y;QSHZGv%3Dq6h3%z?KBs)qcW=WSv%*tojGIRT z^*&Tftpz$nw3Eq|p-e@v#l&spB{H}}f!2cEd!31`D#}pxLUB(At z6)sN5RC=l(Y+}HpsshS;bAO`aH7+-yzs^m- zFYlDm86NYM*xAQoVDD#SjQi!XJ(THP#*!un)`%onL= z)KLr0O`bZ`5=A+cg8Z>%d>?sCY~)t44@^92nwy>4g#$wdx3a{hCcjwEqN>exQ*6f` z` zs3QZw{-5|Y<<>-3I#BWc0ARXZ*gd|BxVKIs1vRiYvK1tNry6InG`pxG7ubPb&(^}V z3!^I{T^()LgU4ELy(&`a%eiQASUuwrRD*U5JX&!|@GR1AXuHx*OGfzFkO2mJOiN-E zTrJ17&^BDz!?J1movAz*Vjwb^s7WcOQLn99^GHDqFIJzWa$2wSo@N5aHW1)Z8w@8Q zpgY`jUN4sDG@|A-QXesvhMna!B2^xXFhRA)bn8KDe&3!)G^tj2FW%BBX%*oErhC&y zS7TH1UOh=&(c2yv7mN)>>WnK+ z98LZxUd3REGm5q=QZKx7%7q zM1t@sN~n1C?ZlL7J;#!I1JfjO+!^4D;w{$VQY*dFe?35KJdQ-uCDBHPhYjj(wT%sj z&H4pm)Zu&R+h?YLAXaBgG3$LjB{}TZF=7)F_$1)?F%k15KR=151J)+HTh%~gEAP(@ z;zRuh?m-_IE<+6;l+7{Px}2=7Gr84Y%r$09x-87beYXhg$2t9LZNfnlCC&MQ!2_4? zo&bk`M#+3$9HS5Yi`Q%V{g{!XTAYi%sH?8dNhpm;C)iDjnd8Hrc=knYRYxNF`B6Qm~I<4 z3hehKT)37-t?1;#-os#$wTY`nt|zqS-ys87sjcO#cL}m_H{w;llQufD!34g0WUW;; zAiz)#2=DH35%t~Fc_a$*Ae~1H-R~G#bEUw7GRJOF676QRvmPX8zSv@Bim&Y;3}d6{Cbm>~g@zr(>pNy~DTWq&hv zGRd__z(0VGC{ha|h;iO{Tv7p>I@ZE|l9R(4XN7jdy*vV;bBM4EfF(J1aKKo@VS1?W3 z?8dG( z7ueAIB`rE~+tPY`IQaJJS`d6aJBm8p{xk-EXQpvHvqea-x;gdA!Tx5tVjqtoU-F@)!vSA!d%sm)K^!2^6=61hK z1{<;1WcBoYb}a+^f8P79Mzin@!!j%SCuc<&*kBzRd9T;*15`Eh zR3qjsc2=MMC9fs1PHKq4%!4`#O1tejNGK%p&J)`EF3HnR3(MUipEZv&*hJW=vHC+4 z>M9#7S;t>n#7|gZv0{%qU%J#p34hLka_w7T?Hg4DFEP)dA8sg5!3U!bE5u;PG>Bll zgMELAS*45y&9+ho(I%)8t>k0T+(*Ao4U~QNem8n@^V!i1<>ROyJ&egb#G%RemlCpi zupq6=#7^#4F%QZ^F1ULRH`W&jLPZX#ri*9pyAOZo(fh{!n*Rs{><;4;S8sH9WOZJY zQ<3xZOV_%ISPO;pvz}6QTx{`kmv57i@NVL$@7wBgrQw#_ zLs>1sF1x#Ro~#@SK7Se0#b}{8v2rPh7TDh9V7~t;$Jq@zpE LF{-`x&*T3C!i*~T diff --git a/DOCS/html/dir_5bc05bcf5fafad3c8688aee149210d07.html b/DOCS/html/dir_5bc05bcf5fafad3c8688aee149210d07.html index 16321c5..3a5fc61 100644 --- a/DOCS/html/dir_5bc05bcf5fafad3c8688aee149210d07.html +++ b/DOCS/html/dir_5bc05bcf5fafad3c8688aee149210d07.html @@ -14,6 +14,7 @@ + @@ -78,6 +79,10 @@ $(function() {
MCU_Wrapper Directory Reference
+ +

Папка Ñ Ð¸Ñходным кодом оболочки МК.

+ +More...

+ Directory dependency graph for MCU_Wrapper:
@@ -85,8 +90,8 @@ $(function() {
diff --git a/DOCS/html/dir_5bc05bcf5fafad3c8688aee149210d07_dep.map b/DOCS/html/dir_5bc05bcf5fafad3c8688aee149210d07_dep.map index 4005f83..8c540a3 100644 --- a/DOCS/html/dir_5bc05bcf5fafad3c8688aee149210d07_dep.map +++ b/DOCS/html/dir_5bc05bcf5fafad3c8688aee149210d07_dep.map @@ -1,6 +1,6 @@ - - + + diff --git a/DOCS/html/dir_5bc05bcf5fafad3c8688aee149210d07_dep.md5 b/DOCS/html/dir_5bc05bcf5fafad3c8688aee149210d07_dep.md5 index 24f2d89..e62c0b1 100644 --- a/DOCS/html/dir_5bc05bcf5fafad3c8688aee149210d07_dep.md5 +++ b/DOCS/html/dir_5bc05bcf5fafad3c8688aee149210d07_dep.md5 @@ -1 +1 @@ -0e852b66b9923a48f1e90c8ee50df39e \ No newline at end of file +8968987f0c27ecbf57ecf6f640d2c2e1 \ No newline at end of file diff --git a/DOCS/html/dir_9609623a411adcd586e91350a30aa9d5.html b/DOCS/html/dir_9609623a411adcd586e91350a30aa9d5.html index aced45f..6ffadef 100644 --- a/DOCS/html/dir_9609623a411adcd586e91350a30aa9d5.html +++ b/DOCS/html/dir_9609623a411adcd586e91350a30aa9d5.html @@ -14,6 +14,7 @@ + @@ -78,6 +79,10 @@ $(function() {
MCU_STM32F4xx_Matlab Directory Reference
+ +

Папка Ñ Ð¸Ñходным кодом Ð´Ð»Ñ ÑимулÑции МК.

+ +More...

+ Directory dependency graph for MCU_STM32F4xx_Matlab:
@@ -85,15 +90,16 @@ $(function() { @@ -101,14 +107,25 @@ $(function() { Directories + + +
 Drivers
 
 STM32F4xx_SIMULINK
  Папка Ñ Ð¸Ñходным кодом ÑимулÑтора МК.
 
- + + +

Files

 stm32f4xx_matlab_conf.c
 stm32f4xx_matlab_conf.c
 Ð˜Ñходный код Ð´Ð»Ñ ÐºÐ¾Ð½Ñ„Ð¸Ð³ÑƒÑ€Ð°Ñ†Ð¸Ð¸ ÑимулÑтора МК.
 
 stm32f4xx_matlab_conf.h
 Ð—аголовочный файл Ð´Ð»Ñ ÐºÐ¾Ð½Ñ„Ð¸Ð³ÑƒÑ€Ð°Ñ†Ð¸Ð¸ ÑимулÑтора МК.
 
+

Detailed Description

+

Папка Ñ Ð¸Ñходным кодом Ð´Ð»Ñ ÑимулÑции МК.

+

Ð’ данной папке ÑодержатьÑÑ Ð¼Ð¾Ð´ÑƒÐ»Ð¸ Ð´Ð»Ñ ÑимулÑции МК в MATLAB:

    +
  • Драйверы МК - они переделаны так, чтобы запуÑкатьÑÑ Ð¸ работать в MATLAB.
    • +
  • СимулÑтор МК - он моделирует работу нужной периферии в MATLAB
    • +
diff --git a/DOCS/html/dir_9609623a411adcd586e91350a30aa9d5_dep.map b/DOCS/html/dir_9609623a411adcd586e91350a30aa9d5_dep.map index 984015c..a035a3c 100644 --- a/DOCS/html/dir_9609623a411adcd586e91350a30aa9d5_dep.map +++ b/DOCS/html/dir_9609623a411adcd586e91350a30aa9d5_dep.map @@ -1,11 +1,12 @@ - - - - - - - - - + + + + + + + + + + diff --git a/DOCS/html/dir_9609623a411adcd586e91350a30aa9d5_dep.md5 b/DOCS/html/dir_9609623a411adcd586e91350a30aa9d5_dep.md5 index 6905821..9c8e54b 100644 --- a/DOCS/html/dir_9609623a411adcd586e91350a30aa9d5_dep.md5 +++ b/DOCS/html/dir_9609623a411adcd586e91350a30aa9d5_dep.md5 @@ -1 +1 @@ -1cd66b9381977000674e64e9e97c1f04 \ No newline at end of file +e6f61ee8219fbd3292fce4ebb5612313 \ No newline at end of file diff --git a/DOCS/html/dir_9609623a411adcd586e91350a30aa9d5_dep.png b/DOCS/html/dir_9609623a411adcd586e91350a30aa9d5_dep.png index 441267572e5cf039d0f587bddd6d26d03912d9aa..b54056c0287bc1173f39456303c24adcb92749aa 100644 GIT binary patch literal 6150 zcmai2byQSuw;qNrX+e;NA(WO*0SPJT9$KUZL1I8uh8|jpp}PenWatu*?sfo40g0hQ zaJcjP?zir}Ykhy*bJjZNtn==(-@V^=$8#R|3te?`5=IgL06?y(p=tmC;K*a2Cx{5J zS6>OFFZM=YucfXExcleKYcEX#0O(saRi7F`vksO6(rCA`36Id0??$?paEYYWlHHVO z;?!o2G@g8XDouMFJ;^I(FJV6V)JJmh9d*651ciRRh@SR+hEI8!`^sGGyd#^85+X_x zB8=oiRBR6m*g}P^#H_8)4_U?H#B^9^XJ@U?P2MSvi&6N@pYIiR{Ove5F~wE=e~>AKTr59iuVOWpeikId{(Kt>UDt6plNNu^eF_fR^j{} zna_*DiUsseP&o*1wa>R$t4%U1G%;D)TM~#MyGgxThl-ie`CqaXk+!)a+ zvFSE&uczZCZ$Q6*n#STX_+%`5IPw`s>?akz=_jRJUnIR`Q4-Svh~Iv-indEWm-}j! zK^L=ase?YUs5bD%ZYqnguw&ban$CVO{Kr1>VWk3c^Pu=sbJiEt z3`IAw8w1YKBq-u??bEl?M*!s6$*=HK6?SBHxv}wp2{>e#;uD*%HR-6Usra=ShsyY~ z@CA|fsUO-khI$na4!bQO<#TAYOJw4(zH4(BeQV>rVPvSeywYKKcc^1JizPC94suZ5 z(%#2%R%;<^88o-WC;`8pk>VuU@W+UuZD(9kK>jl>+4ViuBH3z_s0odRD$MdO=1#_3 z{Z8rmy)y0Ttf@P%?UScYPR*Fp3PEZ2EO+azDJQ4PIref3mvl&J>-bR1n-sL4cYwRe z{Kq|?(%-c=Rtw7|hQsA!t~Ffahy!Gb%PxVMQNHSBYSaKm2@_jD~=XT$xh-t9P} z?g_1L%rh(so<$^np74Li-Ty`lq38frsSm8KCJeMxt!iDW$I_E?@WHP&wm>%MwZDF2 z|HLV5`yxW05m@aJ)oRl7+nVa(;r%8gdwk3uc|co!A&umC{cr*VZ_Aqaw!flQutMqW70-4AT$ZZ;Jd&2=BQH#B}mAQq_Kimw7s}Z}Rw$?3(}RwU?Dd z*fQ9gRb`woa9v4rVL26Cr#g)O5g{ePLgsMr^KB3MkG>3}n|9-HA;4khIv8OQIOtkH zEg3&2;-LD_{D>feRhx{|R2 z^dNETyV+De7d4$)eSH&#RtfBEYZ#>nV{$r>f&_O&>Y&I&nX0wg&Scwz6{0Z)h^gAs zZmgKUjTyAzZRXgOD@|@o8KGqC%<&WzxfYnen^ax-1!s$7gtc&E1un9`KXr6v1FcNh-;h=JlJ{DRc}n&OG@Eg?-}+X#`bY1{e1Tc3 zD=fR|C-H^F88EG7D4Kt-wik?MAKr zlwIh;HGG@L1k`Jz?)&U{TBSXAlwHsSQGsIYal^gA&Ap-Y7q+h1a8^h{fyW01QRuav zG|7wpf!wy&vyPI_p4fJqF*`ick*ntk2`zoHN-11u3a->6M>1T`54pir${X?DbK1w|Tw!VIOl?^nqypTbK^=38+I`yIZ= z%f?Bew2;L%&obChRIj0IVbp^z5BePyROdB z;&QQb6BftDXzsF(QDY|5BbIC69EzdCqgBzfTaM_g&afim9MV~uFLOX^!tQ=NfDLlu z!g>y?IO4OY7QCgxK2iR`aNWzAp`7Eo$ewt?nCgt)#+MLd(udfusWK0PW9(-ktH@dz zJVHreXntu_1vPy8=l;89Jb(t<@y)`|MMimNOde~`@Jpj&c!F;1+6}6Zm-G_D$b^rp zqDQ4q&S246fq$)-mkM(#`AGvn1kZx{JHRDT1o2cae2}2EsY`8qn z*I0xeqZPkM$&}-OxsP2otb_oTi;l}fsut9y7Bao>S6L-VH}Y_lJE|tO{c|MM2}voW zz*eo|Q1aVX&a_{0*9F)7gTm=Vi?j=5dYmRzfK5>0)>nQbte-cm=|DL@sJeHh6eVtB z^GnnC8bHc?;D$s3E1BL^I#YKN;#F*(aRuKk(yh^@z57Q*bCzI)HZq%xCe07rc7=bf z5n#4Hb}Zw^GGBAdM&W-$r=lmaQ8DhZ>jF?S&0qkJ{nG4EGf7Jm7mdHbwcG!_ez>L{ zWK2gh8C+}pD_Dyw9iZ3vdg3OsPo(*KSB3S*dU{{BJKG(;vf7ucIa0ijMT%43mKx#( z<2!6j=&UxkQ#B5=M~a-$J}IA*d;9yj24Fhk0nurS&rDuaZ%C~S2K|}{6@NT5M(9KB~?n$r)`U?-2(u$rgrNB<<-s1lQNS){;z$%x%UY&AQcy{&$gZ>=!X z72rgzcq2PqRIYS#?xZD^LWCZvGHh+IC~W8 z$D)ZudHGI$u8sYO}uA|)oiHcFnSigJ~X*FNhA1O z{0;hz!?ddN!6L@lr_vGWasHj(XX1SheyxDWB{!2-As%uW~-E@`W@}ECK zh~ckBr$s-&>`s9z2D2acP93*uoh(Xc15VAI^R+8PYU{OnDnmTsS--9)hLN0`tzu^s z5k{w6hr>?O)u2rhAWpMHi`DE%$!{M+8y(z&_;`cyDswn}LZPq=7g zbE|}Q^Lhf;fP!HmpwN<>QkHPOes=Twn9F5AJ=51dlgf?QT_ZIZjYvd}YqDD=4}s89 zP!Bx^ktlvF&DuuzwgCO2>w#k8)|^8Hkyci$*qPDB^~C89U00qU>V&n!#W-9{u4{Wa zi)V?;B68QX{2mUirIYG<5%_G>AV-chPH_P2H$TJKfR+6< z(oX#5*NV~pD8XC@4P(cp1+AfAJ45{noqy}YpHk50JyG7s6Qka7zFa1A7yE7oW+oeo z4Q`B51E)6e?ccDjo#zob(NJ%1fR$)(7tD~+1RZbtx?EKS-+wNs?fvtf^rkL+;~*B} z-c+#C2urbpRSG;smP4xibc*fz3gtykM+MK{l2fbThyW|S0yb>`nc2y&*5ZlQ-HR5G z*c=ISoyKrS4;YiR1Nca_9%nK1sCfbKO<5Ft%Nw$)|S0>;Zt5#U#=cF9T{M2^SxFnTj?N3sCw6T z;5`6RSN6O?&S#mC)1@z*5N6$dfn=H)t@@c7xc2B^tqPZ+t2OX ziwM(VFIPv!ZIoWUU>?gn4ZsZP+@D1^S8X$1Xu#Xd6uigPx>bc>y^);NjW7nj6442AJFnvS?<&RCD#yu~U#}Rr!-X!XTR;-@L ze07(0H!%zywFkA?tYpXohM4z!pNo5)0dknXdwrJwD6!kow@8rV(0)7wZTjTddw>CjY%7F)vJVB)Yq|`l1=`*=$Wp)m+wW{T|t@ z!zjSCd2YU~L*>nn_p{yO;5lwFNDx9^`NLBAh(mkBcjCesw+A7 zWtT46)s{1$$V}jeC)}980#eD!4&$P~-BB283!z3#2Fj5+*dr0z;+uLEi#mU?R#U7l zZTW+1B^ZVeOw%`xi=F@J=0VMIyuIZRsB8DYBID{TI$%8vtItm4Yyde2I;IWg$;&_QAU_dp+^gLfJFg=FJ_1yF zWOJLeT2s)ms3e?B&4%|G*cb90B_%Wr=fiJq{GI3<2GR0qO2vaH0Dr36ZY_y500t2vV^x1HIw+=bthn&! zgxr&IBa_#2?wLD04>AQjn#RvT5P}C3B3PvDceQJE0Ic}0{oiEXMpJ!{p=?qH0D)ct z@v_Sm0!3?n01@I>j7MAH2T;M8I1_*cSG-=aMFecyhD_dj9(t61BU8V?fDH!bkVDpm2J9~3TKM|%>o^00eIy5LmF@*Nv?UTZ`#}+)paYQ+U zuf68d@#DjPi}>souP;&Z2fvkZbSWcL2apZP)OY=<-bk}F4u=+`^xw}_tSwd#Fqcu! zO6_U~UU33w+6x=_H1jO{>|fTplJ-q-;fsO~%mE-SFfB*{u`AoV$$Cr6>8!zbAGslj zBZrgsaEGavf%hIP7db}Tc)zeHmE5~wMi{*xJftKOsPZSq+8XL}UiD2w(tda@r}L^ z_H!OT&q4hvo%L64Nl>MvCdRIx051Or;?rHX%JWnyX*{saFFCu3QUvg~CRRKdqWCP= z*rg}24@kPQRv{L|t1$yE1K)9$Q7Z#4?_+DC>?G*&U6ID4OWC*FS6JaJv+UmZoJ4Z;_NJ&IWAq z;m-$#E}&$zme_(b0d4GDVW8tRWe*|Ro*)g?FeNLX%_B*XbeKA^`>wwJIk|8UPM2?$ z4#!RNJBcTagEks@{CH1<+^8){Ysn4hRmRm{j-=&}JQE&P0~^uF)}dp){-hQ1@Vjx- ztz`^DSgtS7xhtH-Yr8Q7MC=m&K0b1Xe#}pMzN}mghY-{7`4v9&6(1 zeF!Hiu$oJ+02R1nJ2Zmd(VLh?C``8igGu1DmTbFgYu2uB(LGUkPaYSP|KSBsq+bcj zq;#uJ_e27D_DacZoK)7cB~WxW{qSyg&eJ(#+4oZ;cF{YGqN+iyUoc%0g>BG$r?kh$ z^V7uOw^@!9t&MoA+0_m$%&6bN>K(Y8i@yg=oa=mWshdY~$AdQI-FH7a4Z>cEv&Aec z|L**2#GWO$JoKcIl?K~^=xxjWuC%cvt+UgzpCiev`>7MtLXBA3$GyLsI#@iXpNF0L z8Dba8V5wvDicFqgMl!UDa(m~a#X>vxe{jp+4uAvFVlPJ$A@fSo*MnGk8{5dE^44~$ u5{TF#Z(0fJ#-5D+#SZ=tUB2miNAczk)rzxU=hZ+EuM?wYV!Fy-001mUCWd;}VFkO3(Shun(KP!%1K^=qx~#0^d`pbf zadl7oKRQjU99a7=;*Wr3Aq*GegOAOE)L)oPDyNn2id1V%mhqSGLDxmS{Q}vR#|=Wu7$;`v!Nef*P~imI$B!J-~GNE@!IK#4li^) zjwCh`_jbt*|4Ttfu?FM!_V%bM&&K5>4HWH?K2&r?9&3Z#=1`c#$}Qu&Un?-fY-S!p z4QxH%1c&e6nn_IZVQ(#!!a1)m-dlPc4XhG^G#S6&Kh2wAfq-*D?K2*$EVB+)Cb8~j z%6@*&9OC#7V;_u_8-*27U^Fms1ER7%$T8l|bOu6%`sC1tC};5hb3k4h{d)J)cfWum z&FcAW$j`Q}pPmlg8{xU%aHBpO;g?YV$8;~2cYojnT4o$_?&Q{Ef0s0Nac{~nJN{W} zOX>S({^kbyiD>O4crKOMz0K(*1Ln&wivxshb&)jVOTr`Hv^bn~Y&Y?Nm)7vhU0aW~ z4T7199r*ZrE(8+#4y@1K)H(5*NX)UjB~^+I%ID0U_`~S{mu#FsZa5fUQhk4RfK7D~ zqqQuL>rDr}ad6Pd|C0Xg=sn`~+F8r*U%BzqRr5&E9SsK{2r`+w{|S-NP?cD=RHWj? zHTk=yg3AbGHC-vd`=KdKK!k5#$m3=DWHO==;y%5-T-@5R)zTs0rZy=egm!2Tb)dcp z1wIhpIGU^6{jIm{(7Dc;oe=>W@m(x;Nm27|uXUht^5K75@mc?~Yq<>EHYl|1q}zGA zL{+Yo3`qjMM%>*@`8uRvI^=#_nxq~6 zndheFr|wGOXEUQ6pvbInAc0aXaM}po5r5RwLNQ=-hra;Caj^z@>G3kP7be<2Adjy% z<@EnG3nA}`CZSUeoE~hV9{9t*WFQW(9Ssh9kSn)vpAJKR(L@}~n^T+B zjx3hcKz{FXS-k*v)R~YR?HMOy;4-4}jS9AB$Zk^e@`v$t_Q?2I%Ax7@d+m5my|2#yP`lBhCIV%T=DcpM zP~7pQb?=BTARm$mdL%~HlC{cQ(0qWkQ+wkxYbh;0(CN*b{@`nnJF6U;T0_li^|dqJ z>``1x7M1-jX=CM^Il2Gs_%4z^3*O08lfF8@9Ur3O;-pTmm2jCWm`Ujypti7u^r*_{ zKhi!yV}6n(YoaRrEzhx6waZ54PkA-^xD}cy?T(CeNpt5SUZXG0l)I2ep2NT!*d5BXzuj(2!^9aF z6`Q|gy`Vr%hYTg_w&awHX^&s$+mYvNN!5${*U;^U%u6c+KL*#bJ^)kBQ*Enec zkaa_UEl9BNN<89&w|4Yw@$AX0%oN)WeCdnJ{GKe50VE`8MaZSq@>fh`QMV4p8^Ee75nX7h zVZ*#-a=OvLM?HpNk9|*J(bXBZ{)Tjn9QsanU;pL3?#EJzT3t-71<@^$h+5kQCySK$ z7ddSVuTawN{SCL{tJ)4`F8ksZ%X#*9eo#jRdN6lu$`)uax7vMPThSpZ>So6DljT0e zraqT=Q1oucOPkM_Mym7kGVRJ%=1d)8G_g9F^m9&G^gP)>r+)M(1^v=$H}T91{!cM2 zlJSYsaM0#diKIqo9))S_ogC?44wLcWO*l`Y zw0pwBUYamq?>>5fK+jb&HBTO_D6Wl*Vzhxey6eU43aR5}-;HSSNW$Mp;C{bAez(eo-R}(iGZbwbYf{I=ht>Iyu;!HU? zJ!U9f@>44zA=39H>!_6}j5>qOaRw_iP{Q_=!`1xt_1p_&>kd_6al<$GlHV!42dSFH${%&3S{=Q5KhZc1@o=RMnW52IjyQvZntrBAa zXx`=4z@hI#`fhq`e=RrVfgjtj!<5nWuHd2Y#RJpLs-yYgCJ2SGMPvV^MKn88h@-c@ z`5_kztP=>ylgr{zRH~~;zjDytl2!we>O}-*{@S$&!=d4BnShy%MbBL@9(&?{Zoh9Cu2g8sc)!K5dCHr!D7~-{yaGHwl}1Kl1*; zs-4=-kB4$w>XZ1?9!@77V@KB^*x<@^xZMLFM`y%n!8B4%*vn+&rT%E(6PMa4o*rrbbXsg-WuwN?@92y z^4idqft|CdH!VuRs73k%_P8Oj=th4xH%dWQ(!e_bHfp8awY^*)vwWRUUnwruyyXye zDds&AHE_N@wvGKMT!il-7WQH9oV!-jB(f8PpE=%eRkE_2%-@v1cD+u>S?1~4uYkK& zCOUm=@9yEP?MlKLTp-gB7nfz?{$EG*7>gn}cDJ8s;M5hHMiOS3J}@5**wRFB5h2`8 zUv50^68>J#?hEQRU^cYBnijBUSP>Jt*AU%RkklU4&VztZXg+ziW4jW2|D;isz%@V) zm@hC0;Mrs7``KF7BZa~~;SS0(x%{2U z*vo}va|kYAvs=ZLCmI06UZm|Z$a^mNu8Tan%n8hd{K5L3X{B{{1rHv!aT1Spwa7Mk zDUYU}YqLWF1gQ5l5Jls6Svb2sTkvJnX(I73p25PzT8i%+3`Ob1osltbUIXT(@w^sj z<0*MGD%>y4&3ZqH9;Y={@@U)MK_aCTurkY7Dh`BDsCjELujn(MSW^y2Q#@~*9z?L9 z?+TFgz}bAY0{IGvENbnkz54LOrE0Cpff%yn4zeC1sNJSPZws=T-xS(t+CFF$*f)7AwnWrt`^jrvtLG-CDH|s!-;Q`I@^)p;{{*dR1 zgk6Ob*sK@E1Eq4Le6G*a?U?arxy3jiAXN{9l#oDt3F;`|!t120Oy(C(e1jZvfUM5E zwXC?`0i60O`3SK?71k7}iC|>`7Ci)l7iXL2KC~;8sH1ahg3p%h!#)0u+HcN+>!j!L zKY#cuT_OY!7C33evvoPl?{qs>IHNif`f9s$o+PtYXa%SP&Au=uL`0H*eAeJMqtpYI zNld^(V`J=O%K=er$vQD!8Ri9p62Y=nuZJmP&kM(=+|y0r^fckAeTQf|XN{An(cZ3d z<2t&YZhf03nq$9Ri%(>;^DlHRsy?^RalW6QPHsj-{;rd_g2%!I@4ZXzD?My@naX95 zdoyEEJYZqDMB~=U4sOv$t>ZuqU=OgSS`K&V@L z0?w@idq&q{*#>BelS!&GY^6MpaI~&OhWi>Dkfc8p5Ge|is=#%E)2jq2Ff6(T?TJ6G(9YngCd!MF>U>G&haYu%jz(QtXFl1n{xETYT@}Al3O%*C>NRi~784@yr)aSxyzE&(3hG?#;zRJ&hEaSVDa)+s&L^ z=?}X5Q){}Gnm|ar(&qj$z=0JSY$I78(fDdpx$j=tuh&%8nBvx~`h&I!Z@=3mLolA5 zaSiw16N1Wb*X#f_I@Ojm3=3sC;am}9sW022^Jo$&ku1_uN^gMoMJ>wNc}3Bf&- zsT>EaI^=UX4D?%9E$*md60J)V|N&tf~WEn|`D?K?exIsru z0LEdVNj~`BtdO8UXzgCF2j&FHN0h}9NP@ot2-SnI&)6cCSomalnk~p`+<5nM{=Ai> z8iI*J=bR)Asb*~KRbv8Xe)mhRWT>{f3ZN98hWKaKdnZR?P7Y3VnGCgp9jgx}h3Jhr zWc?k9cz!lgWMYGCrv#{LpHe&wMhpt{1*H}pvJVX1>IKR3CSjp<#hizB00qAeN8SBd z>NcS`ZJQ|fq1V5VhEpO%ByJ^}Ucq*LDUeqsN1L;0^WI$q10D2j-gI-rUT$TQ+|SHN+4LwXSc5YV{5}{_|j0B`366*VA(f^ef+Y z?p$-kIvO(_Y@ES2*!Ji$2woxsB(U--FU9{Gdxt8$P413438;%%e)R8F81%nJ-P4%H zuC@3&3G<(R0fi@rjiWy9RQ5~T5#s8M?r9f0JEXWfbn84dyeCtX>o9S zj(1Q@nTRvk7v}#gIMV)ymh3ijuk`P!Z&k|sY;JW!KhLc=I%-LY2h&_#{~=eu$5|Oz zC`L6Np797Btn`2K71}t=U!kEYMfxwLu5qD1m&}6TLVkSF(n3OrwHk`>P1Vtg)@|MY fj@%*Tga9UY%?)exo#Orn?Cj9z diff --git a/DOCS/html/dir_afe59ba76eea2f90e4e37233dbf4f6f2.html b/DOCS/html/dir_afe59ba76eea2f90e4e37233dbf4f6f2.html index 64ffd94..e5494f7 100644 --- a/DOCS/html/dir_afe59ba76eea2f90e4e37233dbf4f6f2.html +++ b/DOCS/html/dir_afe59ba76eea2f90e4e37233dbf4f6f2.html @@ -14,6 +14,7 @@ + @@ -85,15 +86,9 @@ $(function() { @@ -101,8 +96,6 @@ $(function() { Directories - -
 CMSIS
 
 STM32F4xx_SIMULINK
 
diff --git a/DOCS/html/dir_afe59ba76eea2f90e4e37233dbf4f6f2_dep.map b/DOCS/html/dir_afe59ba76eea2f90e4e37233dbf4f6f2_dep.map index f1bce0f..92e73cc 100644 --- a/DOCS/html/dir_afe59ba76eea2f90e4e37233dbf4f6f2_dep.map +++ b/DOCS/html/dir_afe59ba76eea2f90e4e37233dbf4f6f2_dep.map @@ -1,11 +1,5 @@ - - - - - - - - - + + + diff --git a/DOCS/html/dir_afe59ba76eea2f90e4e37233dbf4f6f2_dep.md5 b/DOCS/html/dir_afe59ba76eea2f90e4e37233dbf4f6f2_dep.md5 index 4270c60..faa175c 100644 --- a/DOCS/html/dir_afe59ba76eea2f90e4e37233dbf4f6f2_dep.md5 +++ b/DOCS/html/dir_afe59ba76eea2f90e4e37233dbf4f6f2_dep.md5 @@ -1 +1 @@ -9080d033a514984a6f89124aeda3a481 \ No newline at end of file +8818a3371f5e32165b9e177200a07e98 \ No newline at end of file diff --git a/DOCS/html/dir_afe59ba76eea2f90e4e37233dbf4f6f2_dep.png b/DOCS/html/dir_afe59ba76eea2f90e4e37233dbf4f6f2_dep.png index c9be3d884b949b7f8c74a143086bf3d8d381bddc..83fbda458dd5382804b54906aa076ff959c23095 100644 GIT binary patch literal 1729 zcmZWpd0f)j7FRx%l!`dbsF;~VGcLW{l}g18Q8P!!wf7QJiQF<5TnH5$pJj{I%Ow{^ zEHxAjokSfq(MC)g%E;Wp2GEQ&R1(n=8OHhb$ISb@dG~(KJ)e8eIro0gJ>So{8u+cZ z_8!AMYHDiQzCP$6K+gk`2i^s&3aPLgP`hIMywPggpXVKRV<~Wu>5Fy`A^xx;;3eyM z8I8y;(ujAi+BoP$7HNAw8gPR*Fp)kx55^mo#>6}_=-cga@Cz%9&b0{kCSuNP6LI3r zgMi0+kTe^vPI3VTvQ@bdw$W~!{!3<6jX)t=CTD$AouHLvW@VmJE-zH^1(2360Th29 z=$3_GBANXA*^)!N>M0nc@H$;gAP_3d0u%;ZQ{S}cjEs%y_}o(O2u+K76I?F$5|T&r zJGqo2+sGOgFNi49r!>UoqRVU3Q)Qz0TZ%8GFmQb%}K@ceV!&(%HDs%LKkuYxHHtXl3 zqgacF0k}kK7d$)1+GS%F&l+v-J-P9AY5d4IGq_7tw^B9p-PCZP^24B5rS$+ST0#E2 zMBi@EqBl;&^)XZz`Mq9vQ$Br+$V%JSyiC1NvmQ&wGc1&67Tgo$GIe#UmC!c6?PB5?c=MS=Wib#R<8( zrV+A#E|qCTdBM-Q@|AX>|5Fe1<6^TG)^f<#O7`2i)+e;@7)*_UvNKVnsD>nhs)5;? ztk_Dwc3Hv?=Wk^+wewn6EDnc{{NA4{eP+jEv4&wM@r$tizMBm-XaPMku7n+v@G?By zR9sO@AvKFW@XT)hb6-q0=0GVCS50QgBRp=cR9$<{Y4;qfJ8ru1@Cn2(sZeYwZjeb} zg`BwY%hTOv=%*lNKOh?8%k zrY6hx>%|USKJV>lrkJg~eW^r{Og;Q#C>K9ner>>iCnze-26_t!^0cW*^f8{XFBY9X zS|Fns9lfy0RxP}e?VWa2Y$D#-fktsC1XMd!4*R~fE_O$O$zN6XfMQJYpmNx51k~*u zs@`r842F|Xh!rg zRBJZTe#=wPliRYkrJ)B&GQvjAtTI?1t!c+|yQCKCi9kGa&;TTdsl$){9|$!7rAI*} z@5#2A&<60F+?x61kE~C%I*=Wzz3Vmg!m!@6*yYOXPtxXnNODMk^pzkz*ign3Q5Yhr zFv!o!a^x#a$9VlsmsXn7=85sqxFKTtnOp_m$sg%?od9qcNX^|q9S#OEy`m^8&;`#v z8oXOPm$K+kd&?T+K@`mREZFs@zGDWiq}FA(=9G_|)}c2NwKBb|jyS7kMfz>OPFPN> z`rF({j&!W&>V(iln{|?T?7%})YZt#XQYJe!F zcU9!q#&McTFS8aC$?V^FFDv4y^bB0xQgJ%G^L)t^_dYCwkR%wOX>OYTl zHkz^cKFxgGu|~7r(%}7n9F>z<)X>|H&9wbLCXSI9_Gj_x1oPmEbkw{=B5{~bO1CU( zZH63^FEnE{>#y4fT6+G=TtCHD4y)n3Vh}I~>Sgb4hfikUT$0y&^5%oOH1&)629Fv+ z^r`(Lr-m}SyMm+7d*h7JC_N?+y!_7npFT) zgwuFFK=Ftu;BuEgAIO7tiejD9h!jC6i0Q@y?|{aja7SF`pJQd)$m}cO<*qeOKc>XZ zFRqnL=M2*VqVJU%79)E))tiLkpVzy*YL8gg0=@5l$nhCF2*7ND21p`Aswiy2X>oG0 zGi7yWCt+GTXe%Pi%XsKNot#Z q9o+H5T3Iqq(Vq7AUJvYFL~n!Uf4cFq&#yG*v)R|{TXd^ORQ?~jg*-t3 literal 5246 zcma)A2{e@L+kY(Km0co26cQprXeev;E!mj}8CkN$%!{e46@|grm62tvV_(LSELkFq zeMzz#N@K>}_vrtBzweyyeCK@s=Q-zo?(;m?ecji6UBByk?%y3_Vx+^&$jb--0JH8L zO)~(XDhK<$40K@2I^CH8KIokEbu@wBCwC4$KM?@V$mwd{z8jQ5oC!hQUA*7*b1pMA z#9};YB0}pr>^c(LwrkdLYNOP%r;`yDJ(5WBDS{eLIol-i3=da9GOE64(kKyESCuS; z3O&=zg}FLD452?~6*m@N5?x|$LthYn)=Fou@@#PZlg&Pg-)Dhw z#FpQd+;i2I;H-nbkV~L-|Nm9Mcu&M=a%_yE>)aR15>p*o&VRDhVbDF|)AT``)fp zq_0KI1U$QiB&6ICk3b+0%PkEE%lb8H0O=ue3XL&_9Q1YK?$QE)v>vkz08rmXQUU5Q z01Xh%K}82Jp z2xvqHh}E)_FZ#T|XAMJS#U?aRf$a%K?dZif-Z$z7AT7{>%&yl0 zdb-0kukH9AOioW*_A0(gGd9`EOCPg)gl9~`M*a>&!qkz3df2X}V~htkBU-Oz)+uU_ zM}T&E0Rgor=7_bfmVeVht4qdX{-z}15W0J%)`b*dMEBtO8~1CANVpbqueF~oJ^d3E zLFTb=%CLvT8Mcm5NMrl}ih}s?GG)t~D|b@$VR%RPk2lFPp}mng>r`Pf;Z`EkMx~bn zIJBFybVR6IH*M-2eXa(+i%i_``NYhZAF`Nm)PVnc#mD^WfmP0IQq_vBxA)dzRLkxn z(FlvBMmkyz;+o3^cz_Ei9`)jDURf^Dl|P%Q<~5K69^R>MKfrFgq$Y6dGCLGNnm94A z-|B}#%JCb1lw$ba4u=9T zy7i|7?#-tsFy1*CeAf&q!Vy!gpFC??+5iAwc{QTJRsCZbDCJHHaQ#(j>_I8bylqKy zgZPwQjnAKp&5YJ6a{}*?AG(_>i1k|%xovqWU~}fT%6koOqWHR!PGnTo(w8WOJGdUW z(_InjVwQl+FI%dp%AItzp8srLIJAUC$W_#f zb|T2)o#_+Cm%g;R@=e|jXNo+?m$J&6L`MXu`|>KB7u*i(APO5o_dH|GuiZ`vW|r_G zsxE8=E>|P)MhA@cmG>r?E2%@V6TmO!Gb=8;gW{+U0#->&BkAHJ3}>fK_mIxu@{cUn z%k3i5?~m#klYej+5ICGJwrkh~9!T*$E2Td)m7}!!KF`gdWceb@A~u8TAqq^}@&-u^ zK%>WEXj}bw46hN6?|AyF&*bvQ*OY#uX1v*&sX?^GK@`nMT*5smB9WN+`v-SRQwTYu zKCbJecE>WY>Lw_7P1^K`n7)&SYzOn-*!DPErTLY-ah%1Go_%>-G{{{|)bhdT*RK~O zWXGufq>x!ZlMr>N?=Pl1K#~@cO6vj!`IWG7lE}*@z zol|8Sei@bK{}WYpHZaeBu?i)8lbKCE4xmvl7QZqh1Ib%gF^3aV*zrCx@5_#=ZV#t9 zH-y6Vez{#Da4{^oo^B+JLD1)s#L>1m_SQg!WTv)%{j z7+w}{h5zdZoWfW_PuCjOZ|Z*EQtz}YhSa0N&MX+cif!a2d~q6)yI8oMpFh%_%f#jc zmfMjVy$KCd!wr<}#D=h0U3+Dbk`nLhD_f4RQ8@&kKZ*9}S~#ah^euj+7WopFEko?@ z517F7aj=870&NxrcQ1s^>Ba=OqpkAF73xxU=q-Nb{I-IvLyT8i>WFbDJK<&2JNRLe zcII5#Xso@s{cyY)P5a9NUs@iMu6N1TrL%^bg7gl;_`j@7nL>WSpVN^${6pOI6a(`{ zW~~k?x!H}tN~Swh>?az@&FzRDdBUP2@9XpJ^pK@NdXOC#s7isB2Pv1KqSRDZAW@j9 zleE(W*m%g)BX_-BUqht-u|BOCf6^q@E5|m%dyJ(uX`ld|>%$*;SXX8tW z=sLlgWlJy|uh#g~JO+~$ozm1Gd0FSgGly@by~TkA8?3(C6ET=TaONLv1svWTCqD8X zFo3yA+>Y$I&4=}Kk$vkt%~ExMx(qg zhS%)XoWH5Klw5e*yCeyE_M$dyiEyvl&ksc_qs#jT5j6 z0kzzs_?#NrpA*V^r0(G!?2+^R=&riDdGJWH?SP|yrFzbuYvLLXy0XG6Y+%L8bXo2LR;D+N$Ds-FSr_6%_^TfxU9vp) zYIS}~-eX~a&p#;Rn1|7sf&FqWsCB3Na3LH`pDCqXYwxf3Qu;>TmOvbA<(7d8i{dJ- zkhA?IjzMnxVk=S>{^0m$4wlX4|H3&}BY6R)GF#}_e3-EnV50>6jCR45W?wH61;J9} zWNr2YVKYM%tNuO44k4?RNz5Y3-b*#u4s3W18rth-j@{jJ-<6<$^@&-s(UZX_>FNsr z;ACab+MlePJQ#Sgx=ueZo`J#f6bCu9|u>9g~j!%A&27$rA+$i6pKy)8$ZAO=t4f487 zP})|KEVw~GGX{Y$WtlKo4?XTjYtO}H9nat}jaOCj3U5ZtaMydFJhSa`i%UNJ{cYCM z_4mTdl6YS`F_o%1`g`_zjO8Fm$%Xl~#p0GONSMFZ^DpG$oSq=W^w3mdo2&abch2yX z-?AR4oy_c!&$*_alf#4Y3cLA zFMR=RwAIr00 zPvR6s8_)J9_#fB1cci;-74`4WRn8_}XSvb};l6!6#^V@31O@!D} zx?Wpc+1%ZPW<4T=hcUHAu=-;jY?E3g^&8@5EiDdU*#UotwCsFu2wgwwd>AizG@UTI zrScY!tw|$DWGOyw^j+VVlK6GeeYuDVQm=e}_p74_gG_5gA+t7jrbo;7sCY0N$&GsD z*JN*ETx#cVZL8=VL7anC?YNDAp+_7hOfLDjNvKfKk_9bh=_O}5nPgqvKP_2ko2&L9OJxmN)*H zuR^PQvBCEj@A)lf^7XA2=69|n;{1CI`o{KVY6^LK#yp;ffjQ>mK3hey=2ViLpy&JG zeB?P=mSyz_5;$K_dVPpKHZK=P$~Mo3QF^F;r6Ls4v6n*bXfr2jIdu*-MVj+kS4{LV z;x>2Uzyg?JbC$u?{;GjSvs2yqi2UA-7Jlb zCeeygd349DMb;9v?iCn)sfkd;H-lth+{ix_ZPg=YW!`6hmyY~ytfuNOcV_*{^Z$d7NzUaAkq;_8pF~V9B>|u z&YjxjfC;QW74jz&r?3ZV$6{^wggJ&6+^2L__FVVu1&0NvccPw-3iW~ib^EY`L&5-s z%P(eNhfEGFML#Rw8TtD4Yvu$W82+~b8gsJMSqO(g0>j6+w)|(M>V|azpNMI4wJIQA zK=uzDr)&tMwXq4SdyIC>z+Mk9HSj*&ZCeSWw~t7Zar3H$pOs{6;Jpleusc;VmHLtD zf71y0_I^0Dfd3Dx04Myz)FK-yzKwcy&B;w|)Jzfmlt1^%XV&DxKTg@6@%DaV;_80)bQqD{?l$N-!V3bO7=m z?#i-pKR9?S;gayzTc=1qJnD8Rx3=WPpXAXTEXS23^z?jJIQ!<)x1~w4F}Y}* z0dJu<;l^p1VU^xPls;KWf}k%Y-YPmqBVlQed?D`Yr2TeYW28*IJ<3ZAfl?O7n1nR3 z_`x&bjy?XreW4JUkyu~joNh(tIm63v@#j80%ph%Ara-DU)~8OvHbWH;4&jE=G#d6l zW!v7N=Vt6)mothrc22EQ{+^o7Xyh@XvRGJ zq4p3A)7^>-8bus)R1#v5Y*Zsm|K9&xK>ZWElQE)?FI16Rn$2}ypJxE^aO3gKUA~oS zDCKH%A~&70v(BShPAEeOHz(=XG;LYId&n;x+?X?;i2*cL?1JXCChOci1_`&i!NVY% z+hbID_s^ct^OdLn=Hp=JKOo894l0qXyp6gYvO z -STM MATLAB Simulator: F:/Work/Projects/MATLAB/matlab_stm_emulate/MCU_STM32F4xx_Matlab/Drivers/STM32F4xx_SIMULINK Directory Reference +STM MATLAB Simulator: F:/Work/Projects/MATLAB/matlab_stm_emulate/MCU_STM32F4xx_Matlab/STM32F4xx_SIMULINK Directory Reference @@ -14,6 +14,7 @@ + @@ -71,48 +72,63 @@ $(function() {
STM32F4xx_SIMULINK Directory Reference
+ +

Папка Ñ Ð¸Ñходным кодом ÑимулÑтора МК.

+ +More...

+ Directory dependency graph for STM32F4xx_SIMULINK:
- + + + - + + - + + + - + +

Files

 stm32f4xx_matlab_gpio.c
 stm32f4xx_matlab_gpio.c
 Ð˜Ñходный код ÑимулÑтора портов.
 
 stm32f4xx_matlab_gpio.h
 Ð—аголовочный файл Ð´Ð»Ñ ÑимулÑтора портов.
 
 stm32f4xx_matlab_rcc.c
 stm32f4xx_matlab_rcc.c
 
 stm32f4xx_matlab_rcc.h
 Ð—аголовочный файл Ð´Ð»Ñ ÑимулÑтора клока.
 
 stm32f4xx_matlab_tim.c
 stm32f4xx_matlab_tim.c
 Ð˜Ñходный код ÑимулÑтора таймеров.
 
 stm32f4xx_matlab_tim.h
 Ð—аголовочный файл Ð´Ð»Ñ ÑимулÑтора таймеров.
 
 stm32f4xx_periph_registers.c
 stm32f4xx_periph_registers.c
 Ð˜Ñходный код Ñ Ð¿ÐµÑ€ÐµÐ¼ÐµÐ½Ð½Ñ‹Ð¼Ð¸ региÑтров периферии.
 
+

Detailed Description

+

Папка Ñ Ð¸Ñходным кодом ÑимулÑтора МК.

+

Ð’ Ñтой папке ÑодержатьÑÑ Ñ„Ð°Ð¹Ð»Ñ‹ Ð´Ð»Ñ ÑмулÑции периферии STM32 в MATLAB. Структура файлов Ñ‚Ð°ÐºÐ°Ñ Ð¶Ðµ, как в библиотеке HAL:

    +
  • название Ñерии МК, который ÑмулируетÑÑ (stm32f4xx),
    • +
  • идентификатор, что Ñто Ð´Ð»Ñ MATLAB (matlab),
    • +
  • перифериÑ, функции Ð´Ð»Ñ ÑмулÑции которой Ñодержит конкретный файл (gpio, tim).
    • +
+

Пример: "stm32f4xx_matlab_tim.c/.h"

diff --git a/DOCS/html/dir_df8c7f866fb3beabf246989867a8aa90_dep.map b/DOCS/html/dir_df8c7f866fb3beabf246989867a8aa90_dep.map new file mode 100644 index 0000000..048b15e --- /dev/null +++ b/DOCS/html/dir_df8c7f866fb3beabf246989867a8aa90_dep.map @@ -0,0 +1,7 @@ + + + + + + + diff --git a/DOCS/html/dir_df8c7f866fb3beabf246989867a8aa90_dep.md5 b/DOCS/html/dir_df8c7f866fb3beabf246989867a8aa90_dep.md5 new file mode 100644 index 0000000..a7db796 --- /dev/null +++ b/DOCS/html/dir_df8c7f866fb3beabf246989867a8aa90_dep.md5 @@ -0,0 +1 @@ +3dd5c2b9029a39c4bd6a040ec2534660 \ No newline at end of file diff --git a/DOCS/html/dir_df8c7f866fb3beabf246989867a8aa90_dep.png b/DOCS/html/dir_df8c7f866fb3beabf246989867a8aa90_dep.png new file mode 100644 index 0000000000000000000000000000000000000000..ad831ac45b5f84a44c60019ad4c8ead6c15e8315 GIT binary patch literal 2470 zcmZ`*c~lZu7ss7cGMrMxl)|M^gYnhh ztj6+BpJJllKqK&2XWTBsx6KFbER0HiK9;d(8`mZO>vKQuM$^Ba-c# zJ;+Jv)KlA=X#=(iI>6BoP!!-@DUAlNk2=16{dvceG4cXwflMYP(P2RC^H^H6`RXib zVXFKgPz>o`tq(e>)!*9Ms_!*>OsC0bbYvtUXQh;AMsvOr9~k(Tm!01;s2n?Fk>1lH zc;BrWgq_+Gn5&?gJvlI!f8BJ(4rVQK$6_xZr+(vhcXu1AVacC#7&xS`lSnt@de^JV zu#4^IA%HL zlwN#(L<&F(5vP55{B=&K+WaW?12R7cxj{Qvq1Q{I+!yq!KR5i~R!f|(o?K>?MRD9} z&pXA^2V%{+9rdAGNEwh(Iv@APhvDHJ74pv9)9k%@Gw`Dyn*6EZU3KG_*2&H2ZY`U% zJ9zu@c}^p-&NbWF=0M^I@S@w$1JU~qUC$B#m(6Yvq$>D_xg;0wyWaRKh6D6vU5N_| zubOw_)2?vnK|a67{(LM^m}&UpWmj>u4L5LC0v=M5pfv;E_a)0chUlhiDt#CllLflS zMMD?dA9-T(9<X|A_3uu#)w4kbLiQ?s6B^G??{ z=3^h!p~1()_)p*;!S8#x zsRR~XWJ=OoZs9M$k;0em#Mb`tx*guNkyZOKqN#$7GeZb z#P5}my@?XL0&Q&V0hZFi*0t+gfSwc^ila{;+NgQ(QVI z6rn8&jZxBw`==QceKnPe+aaRPg^Q0`^jau!E`!x!iIqoO2HP<*XY-=IWIUgzJMhD- zD~ILuz0+=|cCc7_rV*I;n5UhRKhfQKFCjh7df*Yw)T`;Kez_$38xn0+yj8XV4Jtx3 z-lrwO!Af9HeDjzUZ-0-sw~y-l*>N^hhJ6$HxN?=r|K_E|D$$-$DP-r`8zuo4Ag^82}>Ch*8o8J01}+nl*WL zir8Go7rOgzjZ7KRL+zJG7ZI@{|Lu+TyAE7C|NO0r?ehM`((STRk8OG>_GzwmL1Cf! zF^Hlg&wtn}BK+DlsD6mOt%$#(KPx%~PH#GY81W=vb3H@T>=lJvs4l1Wo?#{?>p#T( zPIKx1t5zpCoqzc<^vPyC#_og&Zt}qrx5{{%JG6#76bBj&#IvQOotwqzweH}}GH6OA z?gS}`AuUePgr>nxMX&^MnhAeJDKjsBn1J}kw?(0jRL)jj_8;)tqEkz^Mm#6cX#m1Q zx1+lcn-6yb=Z+deuS~AWbbXgdsHc?9*Wl72g?^2#wurO+S)pU^;?32_;r>ksn zIu_?UBT%q4XU4-Jepr<}6DpB~3r3dsxqEGup#(N4LPiVuNO{xK+0-l29`M=>e?kXc zIrg9z`7T*$ZWsFAP2q)tL3m1{PWy^Qfs!w*2z#V*CXID9PAl3BO^oP2fYNUy*Df({ zSjDZKVsC70s688a)VCVKt^RBAi844=ICP6Z=cFI6SbgPPe=Ynj*_Io}Ndd{G{Ny#; z-jl!SGEHLqDHsY@Q=l0Pcozp24a9`CAM7L0eT zj1$imxCRY6MC2J#t#LsO$4A5~zX=v#ThW6J?UTyqLiaJQKuq`su(UCq-s02y5t0Ta ze^@phAAvxH4O^VQj6gv(>(sEC?w`!INdu*C{dV(J@#0*rZ{(etnP%Rg&^#1DtuBR> zxZEU@N&jH)QN#g|8C!bE*e4Jeau;ybNzu&D@7+=bs9GcVB?PVlQEEAt)*-lbrvI+4 z>uNbExM1c|Dr?I@kcV19pO{Q(KM84~^MhH2^1_Xnyzr+)JsoLwa&eohpnm2=Ui0ih zg-@hSl4jgMY~Q#@R2uNT_$sM*a5fcamLgyk!%8-t*vp9A{ohw$3I9*>#%(?*>D}&A y4xJ9dg;vx*boSrrtHkd2iby3(egD$z3*VM=J;+@_L}?Sg>vlGdD6$p$*S`V&kGKK= literal 0 HcmV?d00001 diff --git a/DOCS/html/doxygen.css b/DOCS/html/doxygen.css index 7b7d851..7dbff89 100644 --- a/DOCS/html/doxygen.css +++ b/DOCS/html/doxygen.css @@ -193,10 +193,7 @@ html { --invariant-color-text: #265532; } -@media (prefers-color-scheme: dark) { - html:not(.dark-mode) { - color-scheme: dark; - +html.dark-mode { /* page base colors */ --page-background-color: black; --page-foreground-color: #C9D1D9; @@ -387,7 +384,8 @@ html { --invariant-color-bg: #303a35; --invariant-color-hl: #76ce96; --invariant-color-text: #cceed5; -}} +} + body { background-color: var(--page-background-color); color: var(--page-foreground-color); diff --git a/DOCS/html/doxygen_crawl.html b/DOCS/html/doxygen_crawl.html index 45e0e9d..7d202f1 100644 --- a/DOCS/html/doxygen_crawl.html +++ b/DOCS/html/doxygen_crawl.html @@ -8,23 +8,24 @@ - - - - - - - - - + + + + + + + + + + + - - - - - - + + + + + @@ -32,191 +33,67 @@ - - - - - - - - - - - - - - - - - - - - - - + + + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + - - + + - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + - - - - - - - - - - - - - - - - - - - - - - - - @@ -228,7 +105,6 @@ - @@ -238,9 +114,6 @@ - - - @@ -267,47 +140,21 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + diff --git a/DOCS/html/dynsections.js b/DOCS/html/dynsections.js index 8f49326..24dfe9c 100644 --- a/DOCS/html/dynsections.js +++ b/DOCS/html/dynsections.js @@ -192,3 +192,10 @@ let codefold = { }, }; /* @license-end */ +$(function() { + $('.code,.codeRef').each(function() { + $(this).data('powertip',$('#a'+$(this).attr('href').replace(/.*\//,'').replace(/[^a-z_A-Z0-9]/g,'_')).html()); + $.fn.powerTip.smartPlacementLists.s = [ 's', 'n', 'ne', 'se' ]; + $(this).powerTip({ placement: 's', smartPlacement: true, mouseOnToPopup: true }); + }); +}); diff --git a/DOCS/html/files.html b/DOCS/html/files.html index f3c4e5e..b7e3890 100644 --- a/DOCS/html/files.html +++ b/DOCS/html/files.html @@ -14,6 +14,7 @@ + @@ -76,32 +77,26 @@ $(function() {
Here is a list of all files with brief descriptions:
[detail level 1234]
- + - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + +
 ▼ MCU_STM32F4xx_Matlab
 ▼ MCU_STM32F4xx_Matlab Папка Ñ Ð¸Ñходным кодом Ð´Ð»Ñ ÑимулÑции МК.
 ▼ Drivers
 ▼ CMSIS
 arm_defines.h
 core_cm4_matlab.h
 stdint.h
 stm32f407xx_matlab.h
 stm32f4xx.h
 system_stm32f4xx.hCMSIS Cortex-M4 Device System Source File for STM32F4xx devices.
-
 ▼ STM32F4xx_SIMULINK
 stm32f4xx_matlab_gpio.c
 stm32f4xx_matlab_gpio.h
 stm32f4xx_matlab_rcc.c
 stm32f4xx_matlab_rcc.h
 stm32f4xx_matlab_tim.c
 stm32f4xx_matlab_tim.h
 stm32f4xx_periph_registers.c
 stm32f4xx_matlab_conf.c
 stm32f4xx_matlab_conf.h
 ▼ MCU_Wrapper
 MCU.c
 mcu_wrapper.c
 mcu_wrapper_conf.h
 run_mex.bat
 mexing.m
 stm32f407xx_matlab_memory.hЗаголовочный файл Ð´Ð»Ñ Ð¾Ð¿Ñ€ÐµÐ´ÐµÐ»ÐµÐ½Ð¸Ñ Ð¿Ð°Ð¼Ñти МК STM32F4xx
 ▼ STM32F4xx_SIMULINK Папка Ñ Ð¸Ñходным кодом ÑимулÑтора МК.
 stm32f4xx_matlab_gpio.cИÑходный код ÑимулÑтора портов
 stm32f4xx_matlab_gpio.hЗаголовочный файл Ð´Ð»Ñ ÑимулÑтора портов
 stm32f4xx_matlab_rcc.c
 stm32f4xx_matlab_rcc.hЗаголовочный файл Ð´Ð»Ñ ÑимулÑтора клока
 stm32f4xx_matlab_tim.cИÑходный код ÑимулÑтора таймеров
 stm32f4xx_matlab_tim.hЗаголовочный файл Ð´Ð»Ñ ÑимулÑтора таймеров
 stm32f4xx_periph_registers.cИÑходный код Ñ Ð¿ÐµÑ€ÐµÐ¼ÐµÐ½Ð½Ñ‹Ð¼Ð¸ региÑтров периферии
 stm32f4xx_matlab_conf.cИÑходный код Ð´Ð»Ñ ÐºÐ¾Ð½Ñ„Ð¸Ð³ÑƒÑ€Ð°Ñ†Ð¸Ð¸ ÑимулÑтора МК
 stm32f4xx_matlab_conf.hЗаголовочный файл Ð´Ð»Ñ ÐºÐ¾Ð½Ñ„Ð¸Ð³ÑƒÑ€Ð°Ñ†Ð¸Ð¸ ÑимулÑтора МК
 ▼ MCU_Wrapper Папка Ñ Ð¸Ñходным кодом оболочки МК.
 MCU.cИÑходный код S-Function
 mcu_wrapper.cИÑходный код оболочки МК
 mcu_wrapper_conf.hЗаголовочный файл Ð´Ð»Ñ Ð¾Ð±Ð¾Ð»Ð¾Ñ‡ÐºÐ¸ МК
 run_mex.batБатник Ð´Ð»Ñ ÐºÐ¾Ð¼Ð¿Ð¸Ð»Ñции оболочки МК
 mexing.m
diff --git a/DOCS/html/functions.html b/DOCS/html/functions.html index 5953605..7003c49 100644 --- a/DOCS/html/functions.html +++ b/DOCS/html/functions.html @@ -14,6 +14,7 @@ + @@ -73,9 +74,89 @@ $(function() {
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diff --git a/DOCS/html/functions_a.html b/DOCS/html/functions_a.html deleted file mode 100644 index 5544dcd..0000000 --- a/DOCS/html/functions_a.html +++ /dev/null @@ -1,114 +0,0 @@ - - - - - - - -STM MATLAB Simulator: Data Fields - - - - - - - - - - - -
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- - diff --git a/DOCS/html/functions_z.html b/DOCS/html/functions_z.html deleted file mode 100644 index 542f07d..0000000 --- a/DOCS/html/functions_z.html +++ /dev/null @@ -1,85 +0,0 @@ - - - - - - - -STM MATLAB Simulator: Data Fields - - - - - - - - - - - -
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- - diff --git a/DOCS/html/globals.html b/DOCS/html/globals.html index 391384b..1e1e57a 100644 --- a/DOCS/html/globals.html +++ b/DOCS/html/globals.html @@ -14,6 +14,7 @@ + @@ -74,92 +75,8 @@ $(function() {
Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- _ -

diff --git a/DOCS/html/globals_a.html b/DOCS/html/globals_a.html index 07e797d..e0fc371 100644 --- a/DOCS/html/globals_a.html +++ b/DOCS/html/globals_a.html @@ -14,6 +14,7 @@ + @@ -79,585 +80,10 @@ $(function() {
  • ABP2_TIMS_Value : stm32f4xx_matlab_rcc.h
  • ABP2_Value : stm32f4xx_matlab_rcc.h
  • adc : stm32f4xx_periph_registers.c
    • -
  • ADC : stm32f407xx_matlab.h
  • adc1 : stm32f4xx_periph_registers.c
    • -
  • ADC1 : stm32f407xx_matlab.h
  • adc123_common : stm32f4xx_periph_registers.c
    • -
  • ADC123_COMMON : stm32f407xx_matlab.h
    • -
  • ADC123_COMMON_BASE : stm32f407xx_matlab.h
    • -
  • ADC1_BASE : stm32f407xx_matlab.h
    • -
  • ADC2 : stm32f407xx_matlab.h
  • adc2 : stm32f4xx_periph_registers.c
    • -
  • ADC2_BASE : stm32f407xx_matlab.h
  • adc3 : stm32f4xx_periph_registers.c
    • -
  • ADC3 : stm32f407xx_matlab.h
    • -
  • ADC3_BASE : stm32f407xx_matlab.h
    • -
  • ADC_BASE : stm32f407xx_matlab.h
    • -
  • ADC_CCR_ADCPRE : stm32f407xx_matlab.h
    • -
  • ADC_CCR_ADCPRE_0 : stm32f407xx_matlab.h
    • -
  • ADC_CCR_ADCPRE_1 : stm32f407xx_matlab.h
    • -
  • ADC_CCR_ADCPRE_Msk : stm32f407xx_matlab.h
    • -
  • ADC_CCR_ADCPRE_Pos : stm32f407xx_matlab.h
    • -
  • ADC_CCR_DDS : stm32f407xx_matlab.h
    • -
  • ADC_CCR_DDS_Msk : stm32f407xx_matlab.h
    • -
  • ADC_CCR_DDS_Pos : stm32f407xx_matlab.h
    • -
  • ADC_CCR_DELAY : stm32f407xx_matlab.h
    • -
  • ADC_CCR_DELAY_0 : stm32f407xx_matlab.h
    • -
  • ADC_CCR_DELAY_1 : stm32f407xx_matlab.h
    • -
  • ADC_CCR_DELAY_2 : stm32f407xx_matlab.h
    • -
  • ADC_CCR_DELAY_3 : stm32f407xx_matlab.h
    • -
  • ADC_CCR_DELAY_Msk : stm32f407xx_matlab.h
    • -
  • ADC_CCR_DELAY_Pos : stm32f407xx_matlab.h
    • -
  • ADC_CCR_DMA : stm32f407xx_matlab.h
    • -
  • ADC_CCR_DMA_0 : stm32f407xx_matlab.h
    • -
  • ADC_CCR_DMA_1 : stm32f407xx_matlab.h
    • -
  • ADC_CCR_DMA_Msk : stm32f407xx_matlab.h
    • -
  • ADC_CCR_DMA_Pos : stm32f407xx_matlab.h
    • -
  • ADC_CCR_MULTI : stm32f407xx_matlab.h
    • -
  • ADC_CCR_MULTI_0 : stm32f407xx_matlab.h
    • -
  • ADC_CCR_MULTI_1 : stm32f407xx_matlab.h
    • -
  • ADC_CCR_MULTI_2 : stm32f407xx_matlab.h
    • -
  • ADC_CCR_MULTI_3 : stm32f407xx_matlab.h
    • -
  • ADC_CCR_MULTI_4 : stm32f407xx_matlab.h
    • -
  • ADC_CCR_MULTI_Msk : stm32f407xx_matlab.h
    • -
  • ADC_CCR_MULTI_Pos : stm32f407xx_matlab.h
    • -
  • ADC_CCR_TSVREFE : stm32f407xx_matlab.h
    • -
  • ADC_CCR_TSVREFE_Msk : stm32f407xx_matlab.h
    • -
  • ADC_CCR_TSVREFE_Pos : stm32f407xx_matlab.h
    • -
  • ADC_CCR_VBATE : stm32f407xx_matlab.h
    • -
  • ADC_CCR_VBATE_Msk : stm32f407xx_matlab.h
    • -
  • ADC_CCR_VBATE_Pos : stm32f407xx_matlab.h
    • -
  • ADC_CDR_DATA1 : stm32f407xx_matlab.h
    • -
  • ADC_CDR_DATA1_Msk : stm32f407xx_matlab.h
    • -
  • ADC_CDR_DATA1_Pos : stm32f407xx_matlab.h
    • -
  • ADC_CDR_DATA2 : stm32f407xx_matlab.h
    • -
  • ADC_CDR_DATA2_Msk : stm32f407xx_matlab.h
    • -
  • ADC_CDR_DATA2_Pos : stm32f407xx_matlab.h
    • -
  • ADC_CDR_RDATA_MST : stm32f407xx_matlab.h
    • -
  • ADC_CDR_RDATA_SLV : stm32f407xx_matlab.h
    • -
  • ADC_CR1_AWDCH : stm32f407xx_matlab.h
    • -
  • ADC_CR1_AWDCH_0 : stm32f407xx_matlab.h
    • -
  • ADC_CR1_AWDCH_1 : stm32f407xx_matlab.h
    • -
  • ADC_CR1_AWDCH_2 : stm32f407xx_matlab.h
    • -
  • ADC_CR1_AWDCH_3 : stm32f407xx_matlab.h
    • -
  • ADC_CR1_AWDCH_4 : stm32f407xx_matlab.h
    • -
  • ADC_CR1_AWDCH_Msk : stm32f407xx_matlab.h
    • -
  • ADC_CR1_AWDCH_Pos : stm32f407xx_matlab.h
    • -
  • ADC_CR1_AWDEN : stm32f407xx_matlab.h
    • -
  • ADC_CR1_AWDEN_Msk : stm32f407xx_matlab.h
    • -
  • ADC_CR1_AWDEN_Pos : stm32f407xx_matlab.h
    • -
  • ADC_CR1_AWDIE : stm32f407xx_matlab.h
    • -
  • ADC_CR1_AWDIE_Msk : stm32f407xx_matlab.h
    • -
  • ADC_CR1_AWDIE_Pos : stm32f407xx_matlab.h
    • -
  • ADC_CR1_AWDSGL : stm32f407xx_matlab.h
    • -
  • ADC_CR1_AWDSGL_Msk : stm32f407xx_matlab.h
    • -
  • ADC_CR1_AWDSGL_Pos : stm32f407xx_matlab.h
    • -
  • ADC_CR1_DISCEN : stm32f407xx_matlab.h
    • -
  • ADC_CR1_DISCEN_Msk : stm32f407xx_matlab.h
    • -
  • ADC_CR1_DISCEN_Pos : stm32f407xx_matlab.h
    • -
  • ADC_CR1_DISCNUM : stm32f407xx_matlab.h
    • -
  • ADC_CR1_DISCNUM_0 : stm32f407xx_matlab.h
    • -
  • ADC_CR1_DISCNUM_1 : stm32f407xx_matlab.h
    • -
  • ADC_CR1_DISCNUM_2 : stm32f407xx_matlab.h
    • -
  • ADC_CR1_DISCNUM_Msk : stm32f407xx_matlab.h
    • -
  • ADC_CR1_DISCNUM_Pos : stm32f407xx_matlab.h
    • -
  • ADC_CR1_EOCIE : stm32f407xx_matlab.h
    • -
  • ADC_CR1_EOCIE_Msk : stm32f407xx_matlab.h
    • -
  • ADC_CR1_EOCIE_Pos : stm32f407xx_matlab.h
    • -
  • ADC_CR1_JAUTO : stm32f407xx_matlab.h
    • -
  • ADC_CR1_JAUTO_Msk : stm32f407xx_matlab.h
    • -
  • ADC_CR1_JAUTO_Pos : stm32f407xx_matlab.h
    • -
  • ADC_CR1_JAWDEN : stm32f407xx_matlab.h
    • -
  • ADC_CR1_JAWDEN_Msk : stm32f407xx_matlab.h
    • -
  • ADC_CR1_JAWDEN_Pos : stm32f407xx_matlab.h
    • -
  • ADC_CR1_JDISCEN : stm32f407xx_matlab.h
    • -
  • ADC_CR1_JDISCEN_Msk : stm32f407xx_matlab.h
    • -
  • ADC_CR1_JDISCEN_Pos : stm32f407xx_matlab.h
    • -
  • ADC_CR1_JEOCIE : stm32f407xx_matlab.h
    • -
  • ADC_CR1_JEOCIE_Msk : stm32f407xx_matlab.h
    • -
  • ADC_CR1_JEOCIE_Pos : stm32f407xx_matlab.h
    • -
  • ADC_CR1_OVRIE : stm32f407xx_matlab.h
    • -
  • ADC_CR1_OVRIE_Msk : stm32f407xx_matlab.h
    • -
  • ADC_CR1_OVRIE_Pos : stm32f407xx_matlab.h
    • -
  • ADC_CR1_RES : stm32f407xx_matlab.h
    • -
  • ADC_CR1_RES_0 : stm32f407xx_matlab.h
    • -
  • ADC_CR1_RES_1 : stm32f407xx_matlab.h
    • -
  • ADC_CR1_RES_Msk : stm32f407xx_matlab.h
    • -
  • ADC_CR1_RES_Pos : stm32f407xx_matlab.h
    • -
  • ADC_CR1_SCAN : stm32f407xx_matlab.h
    • -
  • ADC_CR1_SCAN_Msk : stm32f407xx_matlab.h
    • -
  • ADC_CR1_SCAN_Pos : stm32f407xx_matlab.h
    • -
  • ADC_CR2_ADON : stm32f407xx_matlab.h
    • -
  • ADC_CR2_ADON_Msk : stm32f407xx_matlab.h
    • -
  • ADC_CR2_ADON_Pos : stm32f407xx_matlab.h
    • -
  • ADC_CR2_ALIGN : stm32f407xx_matlab.h
    • -
  • ADC_CR2_ALIGN_Msk : stm32f407xx_matlab.h
    • -
  • ADC_CR2_ALIGN_Pos : stm32f407xx_matlab.h
    • -
  • ADC_CR2_CONT : stm32f407xx_matlab.h
    • -
  • ADC_CR2_CONT_Msk : stm32f407xx_matlab.h
    • -
  • ADC_CR2_CONT_Pos : stm32f407xx_matlab.h
    • -
  • ADC_CR2_DDS : stm32f407xx_matlab.h
    • -
  • ADC_CR2_DDS_Msk : stm32f407xx_matlab.h
    • -
  • ADC_CR2_DDS_Pos : stm32f407xx_matlab.h
    • -
  • ADC_CR2_DMA : stm32f407xx_matlab.h
    • -
  • ADC_CR2_DMA_Msk : stm32f407xx_matlab.h
    • -
  • ADC_CR2_DMA_Pos : stm32f407xx_matlab.h
    • -
  • ADC_CR2_EOCS : stm32f407xx_matlab.h
    • -
  • ADC_CR2_EOCS_Msk : stm32f407xx_matlab.h
    • -
  • ADC_CR2_EOCS_Pos : stm32f407xx_matlab.h
    • -
  • ADC_CR2_EXTEN : stm32f407xx_matlab.h
    • -
  • ADC_CR2_EXTEN_0 : stm32f407xx_matlab.h
    • -
  • ADC_CR2_EXTEN_1 : stm32f407xx_matlab.h
    • -
  • ADC_CR2_EXTEN_Msk : stm32f407xx_matlab.h
    • -
  • ADC_CR2_EXTEN_Pos : stm32f407xx_matlab.h
    • -
  • ADC_CR2_EXTSEL : stm32f407xx_matlab.h
    • -
  • ADC_CR2_EXTSEL_0 : stm32f407xx_matlab.h
    • -
  • ADC_CR2_EXTSEL_1 : stm32f407xx_matlab.h
    • -
  • ADC_CR2_EXTSEL_2 : stm32f407xx_matlab.h
    • -
  • ADC_CR2_EXTSEL_3 : stm32f407xx_matlab.h
    • -
  • ADC_CR2_EXTSEL_Msk : stm32f407xx_matlab.h
    • -
  • ADC_CR2_EXTSEL_Pos : stm32f407xx_matlab.h
    • -
  • ADC_CR2_JEXTEN : stm32f407xx_matlab.h
    • -
  • ADC_CR2_JEXTEN_0 : stm32f407xx_matlab.h
    • -
  • ADC_CR2_JEXTEN_1 : stm32f407xx_matlab.h
    • -
  • ADC_CR2_JEXTEN_Msk : stm32f407xx_matlab.h
    • -
  • ADC_CR2_JEXTEN_Pos : stm32f407xx_matlab.h
    • -
  • ADC_CR2_JEXTSEL : stm32f407xx_matlab.h
    • -
  • ADC_CR2_JEXTSEL_0 : stm32f407xx_matlab.h
    • -
  • ADC_CR2_JEXTSEL_1 : stm32f407xx_matlab.h
    • -
  • ADC_CR2_JEXTSEL_2 : stm32f407xx_matlab.h
    • -
  • ADC_CR2_JEXTSEL_3 : stm32f407xx_matlab.h
    • -
  • ADC_CR2_JEXTSEL_Msk : stm32f407xx_matlab.h
    • -
  • ADC_CR2_JEXTSEL_Pos : stm32f407xx_matlab.h
    • -
  • ADC_CR2_JSWSTART : stm32f407xx_matlab.h
    • -
  • ADC_CR2_JSWSTART_Msk : stm32f407xx_matlab.h
    • -
  • ADC_CR2_JSWSTART_Pos : stm32f407xx_matlab.h
    • -
  • ADC_CR2_SWSTART : stm32f407xx_matlab.h
    • -
  • ADC_CR2_SWSTART_Msk : stm32f407xx_matlab.h
    • -
  • ADC_CR2_SWSTART_Pos : stm32f407xx_matlab.h
    • -
  • ADC_CSR_AWD1 : stm32f407xx_matlab.h
    • -
  • ADC_CSR_AWD1_Msk : stm32f407xx_matlab.h
    • -
  • ADC_CSR_AWD1_Pos : stm32f407xx_matlab.h
    • -
  • ADC_CSR_AWD2 : stm32f407xx_matlab.h
    • -
  • ADC_CSR_AWD2_Msk : stm32f407xx_matlab.h
    • -
  • ADC_CSR_AWD2_Pos : stm32f407xx_matlab.h
    • -
  • ADC_CSR_AWD3 : stm32f407xx_matlab.h
    • -
  • ADC_CSR_AWD3_Msk : stm32f407xx_matlab.h
    • -
  • ADC_CSR_AWD3_Pos : stm32f407xx_matlab.h
    • -
  • ADC_CSR_DOVR1 : stm32f407xx_matlab.h
    • -
  • ADC_CSR_DOVR2 : stm32f407xx_matlab.h
    • -
  • ADC_CSR_DOVR3 : stm32f407xx_matlab.h
    • -
  • ADC_CSR_EOC1 : stm32f407xx_matlab.h
    • -
  • ADC_CSR_EOC1_Msk : stm32f407xx_matlab.h
    • -
  • ADC_CSR_EOC1_Pos : stm32f407xx_matlab.h
    • -
  • ADC_CSR_EOC2 : stm32f407xx_matlab.h
    • -
  • ADC_CSR_EOC2_Msk : stm32f407xx_matlab.h
    • -
  • ADC_CSR_EOC2_Pos : stm32f407xx_matlab.h
    • -
  • ADC_CSR_EOC3 : stm32f407xx_matlab.h
    • -
  • ADC_CSR_EOC3_Msk : stm32f407xx_matlab.h
    • -
  • ADC_CSR_EOC3_Pos : stm32f407xx_matlab.h
    • -
  • ADC_CSR_JEOC1 : stm32f407xx_matlab.h
    • -
  • ADC_CSR_JEOC1_Msk : stm32f407xx_matlab.h
    • -
  • ADC_CSR_JEOC1_Pos : stm32f407xx_matlab.h
    • -
  • ADC_CSR_JEOC2 : stm32f407xx_matlab.h
    • -
  • ADC_CSR_JEOC2_Msk : stm32f407xx_matlab.h
    • -
  • ADC_CSR_JEOC2_Pos : stm32f407xx_matlab.h
    • -
  • ADC_CSR_JEOC3 : stm32f407xx_matlab.h
    • -
  • ADC_CSR_JEOC3_Msk : stm32f407xx_matlab.h
    • -
  • ADC_CSR_JEOC3_Pos : stm32f407xx_matlab.h
    • -
  • ADC_CSR_JSTRT1 : stm32f407xx_matlab.h
    • -
  • ADC_CSR_JSTRT1_Msk : stm32f407xx_matlab.h
    • -
  • ADC_CSR_JSTRT1_Pos : stm32f407xx_matlab.h
    • -
  • ADC_CSR_JSTRT2 : stm32f407xx_matlab.h
    • -
  • ADC_CSR_JSTRT2_Msk : stm32f407xx_matlab.h
    • -
  • ADC_CSR_JSTRT2_Pos : stm32f407xx_matlab.h
    • -
  • ADC_CSR_JSTRT3 : stm32f407xx_matlab.h
    • -
  • ADC_CSR_JSTRT3_Msk : stm32f407xx_matlab.h
    • -
  • ADC_CSR_JSTRT3_Pos : stm32f407xx_matlab.h
    • -
  • ADC_CSR_OVR1 : stm32f407xx_matlab.h
    • -
  • ADC_CSR_OVR1_Msk : stm32f407xx_matlab.h
    • -
  • ADC_CSR_OVR1_Pos : stm32f407xx_matlab.h
    • -
  • ADC_CSR_OVR2 : stm32f407xx_matlab.h
    • -
  • ADC_CSR_OVR2_Msk : stm32f407xx_matlab.h
    • -
  • ADC_CSR_OVR2_Pos : stm32f407xx_matlab.h
    • -
  • ADC_CSR_OVR3 : stm32f407xx_matlab.h
    • -
  • ADC_CSR_OVR3_Msk : stm32f407xx_matlab.h
    • -
  • ADC_CSR_OVR3_Pos : stm32f407xx_matlab.h
    • -
  • ADC_CSR_STRT1 : stm32f407xx_matlab.h
    • -
  • ADC_CSR_STRT1_Msk : stm32f407xx_matlab.h
    • -
  • ADC_CSR_STRT1_Pos : stm32f407xx_matlab.h
    • -
  • ADC_CSR_STRT2 : stm32f407xx_matlab.h
    • -
  • ADC_CSR_STRT2_Msk : stm32f407xx_matlab.h
    • -
  • ADC_CSR_STRT2_Pos : stm32f407xx_matlab.h
    • -
  • ADC_CSR_STRT3 : stm32f407xx_matlab.h
    • -
  • ADC_CSR_STRT3_Msk : stm32f407xx_matlab.h
    • -
  • ADC_CSR_STRT3_Pos : stm32f407xx_matlab.h
    • -
  • ADC_DR_ADC2DATA : stm32f407xx_matlab.h
    • -
  • ADC_DR_ADC2DATA_Msk : stm32f407xx_matlab.h
    • -
  • ADC_DR_ADC2DATA_Pos : stm32f407xx_matlab.h
    • -
  • ADC_DR_DATA : stm32f407xx_matlab.h
    • -
  • ADC_DR_DATA_Msk : stm32f407xx_matlab.h
    • -
  • ADC_DR_DATA_Pos : stm32f407xx_matlab.h
    • -
  • ADC_HTR_HT : stm32f407xx_matlab.h
    • -
  • ADC_HTR_HT_Msk : stm32f407xx_matlab.h
    • -
  • ADC_HTR_HT_Pos : stm32f407xx_matlab.h
    • -
  • ADC_IRQn : stm32f407xx_matlab.h
    • -
  • ADC_JDR1_JDATA : stm32f407xx_matlab.h
    • -
  • ADC_JDR1_JDATA_Msk : stm32f407xx_matlab.h
    • -
  • ADC_JDR1_JDATA_Pos : stm32f407xx_matlab.h
    • -
  • ADC_JDR2_JDATA : stm32f407xx_matlab.h
    • -
  • ADC_JDR2_JDATA_Msk : stm32f407xx_matlab.h
    • -
  • ADC_JDR2_JDATA_Pos : stm32f407xx_matlab.h
    • -
  • ADC_JDR3_JDATA : stm32f407xx_matlab.h
    • -
  • ADC_JDR3_JDATA_Msk : stm32f407xx_matlab.h
    • -
  • ADC_JDR3_JDATA_Pos : stm32f407xx_matlab.h
    • -
  • ADC_JDR4_JDATA : stm32f407xx_matlab.h
    • -
  • ADC_JDR4_JDATA_Msk : stm32f407xx_matlab.h
    • -
  • ADC_JDR4_JDATA_Pos : stm32f407xx_matlab.h
    • -
  • ADC_JOFR1_JOFFSET1 : stm32f407xx_matlab.h
    • -
  • ADC_JOFR1_JOFFSET1_Msk : stm32f407xx_matlab.h
    • -
  • ADC_JOFR1_JOFFSET1_Pos : stm32f407xx_matlab.h
    • -
  • ADC_JOFR2_JOFFSET2 : stm32f407xx_matlab.h
    • -
  • ADC_JOFR2_JOFFSET2_Msk : stm32f407xx_matlab.h
    • -
  • ADC_JOFR2_JOFFSET2_Pos : stm32f407xx_matlab.h
    • -
  • ADC_JOFR3_JOFFSET3 : stm32f407xx_matlab.h
    • -
  • ADC_JOFR3_JOFFSET3_Msk : stm32f407xx_matlab.h
    • -
  • ADC_JOFR3_JOFFSET3_Pos : stm32f407xx_matlab.h
    • -
  • ADC_JOFR4_JOFFSET4 : stm32f407xx_matlab.h
    • -
  • ADC_JOFR4_JOFFSET4_Msk : stm32f407xx_matlab.h
    • -
  • ADC_JOFR4_JOFFSET4_Pos : stm32f407xx_matlab.h
    • -
  • ADC_JSQR_JL : stm32f407xx_matlab.h
    • -
  • ADC_JSQR_JL_0 : stm32f407xx_matlab.h
    • -
  • ADC_JSQR_JL_1 : stm32f407xx_matlab.h
    • -
  • ADC_JSQR_JL_Msk : stm32f407xx_matlab.h
    • -
  • ADC_JSQR_JL_Pos : stm32f407xx_matlab.h
    • -
  • ADC_JSQR_JSQ1 : stm32f407xx_matlab.h
    • -
  • ADC_JSQR_JSQ1_0 : stm32f407xx_matlab.h
    • -
  • ADC_JSQR_JSQ1_1 : stm32f407xx_matlab.h
    • -
  • ADC_JSQR_JSQ1_2 : stm32f407xx_matlab.h
    • -
  • ADC_JSQR_JSQ1_3 : stm32f407xx_matlab.h
    • -
  • ADC_JSQR_JSQ1_4 : stm32f407xx_matlab.h
    • -
  • ADC_JSQR_JSQ1_Msk : stm32f407xx_matlab.h
    • -
  • ADC_JSQR_JSQ1_Pos : stm32f407xx_matlab.h
    • -
  • ADC_JSQR_JSQ2 : stm32f407xx_matlab.h
    • -
  • ADC_JSQR_JSQ2_0 : stm32f407xx_matlab.h
    • -
  • ADC_JSQR_JSQ2_1 : stm32f407xx_matlab.h
    • -
  • ADC_JSQR_JSQ2_2 : stm32f407xx_matlab.h
    • -
  • ADC_JSQR_JSQ2_3 : stm32f407xx_matlab.h
    • -
  • ADC_JSQR_JSQ2_4 : stm32f407xx_matlab.h
    • -
  • ADC_JSQR_JSQ2_Msk : stm32f407xx_matlab.h
    • -
  • ADC_JSQR_JSQ2_Pos : stm32f407xx_matlab.h
    • -
  • ADC_JSQR_JSQ3 : stm32f407xx_matlab.h
    • -
  • ADC_JSQR_JSQ3_0 : stm32f407xx_matlab.h
    • -
  • ADC_JSQR_JSQ3_1 : stm32f407xx_matlab.h
    • -
  • ADC_JSQR_JSQ3_2 : stm32f407xx_matlab.h
    • -
  • ADC_JSQR_JSQ3_3 : stm32f407xx_matlab.h
    • -
  • ADC_JSQR_JSQ3_4 : stm32f407xx_matlab.h
    • -
  • ADC_JSQR_JSQ3_Msk : stm32f407xx_matlab.h
    • -
  • ADC_JSQR_JSQ3_Pos : stm32f407xx_matlab.h
    • -
  • ADC_JSQR_JSQ4 : stm32f407xx_matlab.h
    • -
  • ADC_JSQR_JSQ4_0 : stm32f407xx_matlab.h
    • -
  • ADC_JSQR_JSQ4_1 : stm32f407xx_matlab.h
    • -
  • ADC_JSQR_JSQ4_2 : stm32f407xx_matlab.h
    • -
  • ADC_JSQR_JSQ4_3 : stm32f407xx_matlab.h
    • -
  • ADC_JSQR_JSQ4_4 : stm32f407xx_matlab.h
    • -
  • ADC_JSQR_JSQ4_Msk : stm32f407xx_matlab.h
    • -
  • ADC_JSQR_JSQ4_Pos : stm32f407xx_matlab.h
    • -
  • ADC_LTR_LT : stm32f407xx_matlab.h
    • -
  • ADC_LTR_LT_Msk : stm32f407xx_matlab.h
    • -
  • ADC_LTR_LT_Pos : stm32f407xx_matlab.h
    • -
  • ADC_MULTIMODE_SUPPORT : stm32f407xx_matlab.h
    • -
  • ADC_SMPR1_SMP10 : stm32f407xx_matlab.h
    • -
  • ADC_SMPR1_SMP10_0 : stm32f407xx_matlab.h
    • -
  • ADC_SMPR1_SMP10_1 : stm32f407xx_matlab.h
    • -
  • ADC_SMPR1_SMP10_2 : stm32f407xx_matlab.h
    • -
  • ADC_SMPR1_SMP10_Msk : stm32f407xx_matlab.h
    • -
  • ADC_SMPR1_SMP10_Pos : stm32f407xx_matlab.h
    • -
  • ADC_SMPR1_SMP11 : stm32f407xx_matlab.h
    • -
  • ADC_SMPR1_SMP11_0 : stm32f407xx_matlab.h
    • -
  • ADC_SMPR1_SMP11_1 : stm32f407xx_matlab.h
    • -
  • ADC_SMPR1_SMP11_2 : stm32f407xx_matlab.h
    • -
  • ADC_SMPR1_SMP11_Msk : stm32f407xx_matlab.h
    • -
  • ADC_SMPR1_SMP11_Pos : stm32f407xx_matlab.h
    • -
  • ADC_SMPR1_SMP12 : stm32f407xx_matlab.h
    • -
  • ADC_SMPR1_SMP12_0 : stm32f407xx_matlab.h
    • -
  • ADC_SMPR1_SMP12_1 : stm32f407xx_matlab.h
    • -
  • ADC_SMPR1_SMP12_2 : stm32f407xx_matlab.h
    • -
  • ADC_SMPR1_SMP12_Msk : stm32f407xx_matlab.h
    • -
  • ADC_SMPR1_SMP12_Pos : stm32f407xx_matlab.h
    • -
  • ADC_SMPR1_SMP13 : stm32f407xx_matlab.h
    • -
  • ADC_SMPR1_SMP13_0 : stm32f407xx_matlab.h
    • -
  • ADC_SMPR1_SMP13_1 : stm32f407xx_matlab.h
    • -
  • ADC_SMPR1_SMP13_2 : stm32f407xx_matlab.h
    • -
  • ADC_SMPR1_SMP13_Msk : stm32f407xx_matlab.h
    • -
  • ADC_SMPR1_SMP13_Pos : stm32f407xx_matlab.h
    • -
  • ADC_SMPR1_SMP14 : stm32f407xx_matlab.h
    • -
  • ADC_SMPR1_SMP14_0 : stm32f407xx_matlab.h
    • -
  • ADC_SMPR1_SMP14_1 : stm32f407xx_matlab.h
    • -
  • ADC_SMPR1_SMP14_2 : stm32f407xx_matlab.h
    • -
  • ADC_SMPR1_SMP14_Msk : stm32f407xx_matlab.h
    • -
  • ADC_SMPR1_SMP14_Pos : stm32f407xx_matlab.h
    • -
  • ADC_SMPR1_SMP15 : stm32f407xx_matlab.h
    • -
  • ADC_SMPR1_SMP15_0 : stm32f407xx_matlab.h
    • -
  • ADC_SMPR1_SMP15_1 : stm32f407xx_matlab.h
    • -
  • ADC_SMPR1_SMP15_2 : stm32f407xx_matlab.h
    • -
  • ADC_SMPR1_SMP15_Msk : stm32f407xx_matlab.h
    • -
  • ADC_SMPR1_SMP15_Pos : stm32f407xx_matlab.h
    • -
  • ADC_SMPR1_SMP16 : stm32f407xx_matlab.h
    • -
  • ADC_SMPR1_SMP16_0 : stm32f407xx_matlab.h
    • -
  • ADC_SMPR1_SMP16_1 : stm32f407xx_matlab.h
    • -
  • ADC_SMPR1_SMP16_2 : stm32f407xx_matlab.h
    • -
  • ADC_SMPR1_SMP16_Msk : stm32f407xx_matlab.h
    • -
  • ADC_SMPR1_SMP16_Pos : stm32f407xx_matlab.h
    • -
  • ADC_SMPR1_SMP17 : stm32f407xx_matlab.h
    • -
  • ADC_SMPR1_SMP17_0 : stm32f407xx_matlab.h
    • -
  • ADC_SMPR1_SMP17_1 : stm32f407xx_matlab.h
    • -
  • ADC_SMPR1_SMP17_2 : stm32f407xx_matlab.h
    • -
  • ADC_SMPR1_SMP17_Msk : stm32f407xx_matlab.h
    • -
  • ADC_SMPR1_SMP17_Pos : stm32f407xx_matlab.h
    • -
  • ADC_SMPR1_SMP18 : stm32f407xx_matlab.h
    • -
  • ADC_SMPR1_SMP18_0 : stm32f407xx_matlab.h
    • -
  • ADC_SMPR1_SMP18_1 : stm32f407xx_matlab.h
    • -
  • ADC_SMPR1_SMP18_2 : stm32f407xx_matlab.h
    • -
  • ADC_SMPR1_SMP18_Msk : stm32f407xx_matlab.h
    • -
  • ADC_SMPR1_SMP18_Pos : stm32f407xx_matlab.h
    • -
  • ADC_SMPR2_SMP0 : stm32f407xx_matlab.h
    • -
  • ADC_SMPR2_SMP0_0 : stm32f407xx_matlab.h
    • -
  • ADC_SMPR2_SMP0_1 : stm32f407xx_matlab.h
    • -
  • ADC_SMPR2_SMP0_2 : stm32f407xx_matlab.h
    • -
  • ADC_SMPR2_SMP0_Msk : stm32f407xx_matlab.h
    • -
  • ADC_SMPR2_SMP0_Pos : stm32f407xx_matlab.h
    • -
  • ADC_SMPR2_SMP1 : stm32f407xx_matlab.h
    • -
  • ADC_SMPR2_SMP1_0 : stm32f407xx_matlab.h
    • -
  • ADC_SMPR2_SMP1_1 : stm32f407xx_matlab.h
    • -
  • ADC_SMPR2_SMP1_2 : stm32f407xx_matlab.h
    • -
  • ADC_SMPR2_SMP1_Msk : stm32f407xx_matlab.h
    • -
  • ADC_SMPR2_SMP1_Pos : stm32f407xx_matlab.h
    • -
  • ADC_SMPR2_SMP2 : stm32f407xx_matlab.h
    • -
  • ADC_SMPR2_SMP2_0 : stm32f407xx_matlab.h
    • -
  • ADC_SMPR2_SMP2_1 : stm32f407xx_matlab.h
    • -
  • ADC_SMPR2_SMP2_2 : stm32f407xx_matlab.h
    • -
  • ADC_SMPR2_SMP2_Msk : stm32f407xx_matlab.h
    • -
  • ADC_SMPR2_SMP2_Pos : stm32f407xx_matlab.h
    • -
  • ADC_SMPR2_SMP3 : stm32f407xx_matlab.h
    • -
  • ADC_SMPR2_SMP3_0 : stm32f407xx_matlab.h
    • -
  • ADC_SMPR2_SMP3_1 : stm32f407xx_matlab.h
    • -
  • ADC_SMPR2_SMP3_2 : stm32f407xx_matlab.h
    • -
  • ADC_SMPR2_SMP3_Msk : stm32f407xx_matlab.h
    • -
  • ADC_SMPR2_SMP3_Pos : stm32f407xx_matlab.h
    • -
  • ADC_SMPR2_SMP4 : stm32f407xx_matlab.h
    • -
  • ADC_SMPR2_SMP4_0 : stm32f407xx_matlab.h
    • -
  • ADC_SMPR2_SMP4_1 : stm32f407xx_matlab.h
    • -
  • ADC_SMPR2_SMP4_2 : stm32f407xx_matlab.h
    • -
  • ADC_SMPR2_SMP4_Msk : stm32f407xx_matlab.h
    • -
  • ADC_SMPR2_SMP4_Pos : stm32f407xx_matlab.h
    • -
  • ADC_SMPR2_SMP5 : stm32f407xx_matlab.h
    • -
  • ADC_SMPR2_SMP5_0 : stm32f407xx_matlab.h
    • -
  • ADC_SMPR2_SMP5_1 : stm32f407xx_matlab.h
    • -
  • ADC_SMPR2_SMP5_2 : stm32f407xx_matlab.h
    • -
  • ADC_SMPR2_SMP5_Msk : stm32f407xx_matlab.h
    • -
  • ADC_SMPR2_SMP5_Pos : stm32f407xx_matlab.h
    • -
  • ADC_SMPR2_SMP6 : stm32f407xx_matlab.h
    • -
  • ADC_SMPR2_SMP6_0 : stm32f407xx_matlab.h
    • -
  • ADC_SMPR2_SMP6_1 : stm32f407xx_matlab.h
    • -
  • ADC_SMPR2_SMP6_2 : stm32f407xx_matlab.h
    • -
  • ADC_SMPR2_SMP6_Msk : stm32f407xx_matlab.h
    • -
  • ADC_SMPR2_SMP6_Pos : stm32f407xx_matlab.h
    • -
  • ADC_SMPR2_SMP7 : stm32f407xx_matlab.h
    • -
  • ADC_SMPR2_SMP7_0 : stm32f407xx_matlab.h
    • -
  • ADC_SMPR2_SMP7_1 : stm32f407xx_matlab.h
    • -
  • ADC_SMPR2_SMP7_2 : stm32f407xx_matlab.h
    • -
  • ADC_SMPR2_SMP7_Msk : stm32f407xx_matlab.h
    • -
  • ADC_SMPR2_SMP7_Pos : stm32f407xx_matlab.h
    • -
  • ADC_SMPR2_SMP8 : stm32f407xx_matlab.h
    • -
  • ADC_SMPR2_SMP8_0 : stm32f407xx_matlab.h
    • -
  • ADC_SMPR2_SMP8_1 : stm32f407xx_matlab.h
    • -
  • ADC_SMPR2_SMP8_2 : stm32f407xx_matlab.h
    • -
  • ADC_SMPR2_SMP8_Msk : stm32f407xx_matlab.h
    • -
  • ADC_SMPR2_SMP8_Pos : stm32f407xx_matlab.h
    • -
  • ADC_SMPR2_SMP9 : stm32f407xx_matlab.h
    • -
  • ADC_SMPR2_SMP9_0 : stm32f407xx_matlab.h
    • -
  • ADC_SMPR2_SMP9_1 : stm32f407xx_matlab.h
    • -
  • ADC_SMPR2_SMP9_2 : stm32f407xx_matlab.h
    • -
  • ADC_SMPR2_SMP9_Msk : stm32f407xx_matlab.h
    • -
  • ADC_SMPR2_SMP9_Pos : stm32f407xx_matlab.h
    • -
  • ADC_SQR1_L : stm32f407xx_matlab.h
    • -
  • ADC_SQR1_L_0 : stm32f407xx_matlab.h
    • -
  • ADC_SQR1_L_1 : stm32f407xx_matlab.h
    • -
  • ADC_SQR1_L_2 : stm32f407xx_matlab.h
    • -
  • ADC_SQR1_L_3 : stm32f407xx_matlab.h
    • -
  • ADC_SQR1_L_Msk : stm32f407xx_matlab.h
    • -
  • ADC_SQR1_L_Pos : stm32f407xx_matlab.h
    • -
  • ADC_SQR1_SQ13 : stm32f407xx_matlab.h
    • -
  • ADC_SQR1_SQ13_0 : stm32f407xx_matlab.h
    • -
  • ADC_SQR1_SQ13_1 : stm32f407xx_matlab.h
    • -
  • ADC_SQR1_SQ13_2 : stm32f407xx_matlab.h
    • -
  • ADC_SQR1_SQ13_3 : stm32f407xx_matlab.h
    • -
  • ADC_SQR1_SQ13_4 : stm32f407xx_matlab.h
    • -
  • ADC_SQR1_SQ13_Msk : stm32f407xx_matlab.h
    • -
  • ADC_SQR1_SQ13_Pos : stm32f407xx_matlab.h
    • -
  • ADC_SQR1_SQ14 : stm32f407xx_matlab.h
    • -
  • ADC_SQR1_SQ14_0 : stm32f407xx_matlab.h
    • -
  • ADC_SQR1_SQ14_1 : stm32f407xx_matlab.h
    • -
  • ADC_SQR1_SQ14_2 : stm32f407xx_matlab.h
    • -
  • ADC_SQR1_SQ14_3 : stm32f407xx_matlab.h
    • -
  • ADC_SQR1_SQ14_4 : stm32f407xx_matlab.h
    • -
  • ADC_SQR1_SQ14_Msk : stm32f407xx_matlab.h
    • -
  • ADC_SQR1_SQ14_Pos : stm32f407xx_matlab.h
    • -
  • ADC_SQR1_SQ15 : stm32f407xx_matlab.h
    • -
  • ADC_SQR1_SQ15_0 : stm32f407xx_matlab.h
    • -
  • ADC_SQR1_SQ15_1 : stm32f407xx_matlab.h
    • -
  • ADC_SQR1_SQ15_2 : stm32f407xx_matlab.h
    • -
  • ADC_SQR1_SQ15_3 : stm32f407xx_matlab.h
    • -
  • ADC_SQR1_SQ15_4 : stm32f407xx_matlab.h
    • -
  • ADC_SQR1_SQ15_Msk : stm32f407xx_matlab.h
    • -
  • ADC_SQR1_SQ15_Pos : stm32f407xx_matlab.h
    • -
  • ADC_SQR1_SQ16 : stm32f407xx_matlab.h
    • -
  • ADC_SQR1_SQ16_0 : stm32f407xx_matlab.h
    • -
  • ADC_SQR1_SQ16_1 : stm32f407xx_matlab.h
    • -
  • ADC_SQR1_SQ16_2 : stm32f407xx_matlab.h
    • -
  • ADC_SQR1_SQ16_3 : stm32f407xx_matlab.h
    • -
  • ADC_SQR1_SQ16_4 : stm32f407xx_matlab.h
    • -
  • ADC_SQR1_SQ16_Msk : stm32f407xx_matlab.h
    • -
  • ADC_SQR1_SQ16_Pos : stm32f407xx_matlab.h
    • -
  • ADC_SQR2_SQ10 : stm32f407xx_matlab.h
    • -
  • ADC_SQR2_SQ10_0 : stm32f407xx_matlab.h
    • -
  • ADC_SQR2_SQ10_1 : stm32f407xx_matlab.h
    • -
  • ADC_SQR2_SQ10_2 : stm32f407xx_matlab.h
    • -
  • ADC_SQR2_SQ10_3 : stm32f407xx_matlab.h
    • -
  • ADC_SQR2_SQ10_4 : stm32f407xx_matlab.h
    • -
  • ADC_SQR2_SQ10_Msk : stm32f407xx_matlab.h
    • -
  • ADC_SQR2_SQ10_Pos : stm32f407xx_matlab.h
    • -
  • ADC_SQR2_SQ11 : stm32f407xx_matlab.h
    • -
  • ADC_SQR2_SQ11_0 : stm32f407xx_matlab.h
    • -
  • ADC_SQR2_SQ11_1 : stm32f407xx_matlab.h
    • -
  • ADC_SQR2_SQ11_2 : stm32f407xx_matlab.h
    • -
  • ADC_SQR2_SQ11_3 : stm32f407xx_matlab.h
    • -
  • ADC_SQR2_SQ11_4 : stm32f407xx_matlab.h
    • -
  • ADC_SQR2_SQ11_Msk : stm32f407xx_matlab.h
    • -
  • ADC_SQR2_SQ11_Pos : stm32f407xx_matlab.h
    • -
  • ADC_SQR2_SQ12 : stm32f407xx_matlab.h
    • -
  • ADC_SQR2_SQ12_0 : stm32f407xx_matlab.h
    • -
  • ADC_SQR2_SQ12_1 : stm32f407xx_matlab.h
    • -
  • ADC_SQR2_SQ12_2 : stm32f407xx_matlab.h
    • -
  • ADC_SQR2_SQ12_3 : stm32f407xx_matlab.h
    • -
  • ADC_SQR2_SQ12_4 : stm32f407xx_matlab.h
    • -
  • ADC_SQR2_SQ12_Msk : stm32f407xx_matlab.h
    • -
  • ADC_SQR2_SQ12_Pos : stm32f407xx_matlab.h
    • -
  • ADC_SQR2_SQ7 : stm32f407xx_matlab.h
    • -
  • ADC_SQR2_SQ7_0 : stm32f407xx_matlab.h
    • -
  • ADC_SQR2_SQ7_1 : stm32f407xx_matlab.h
    • -
  • ADC_SQR2_SQ7_2 : stm32f407xx_matlab.h
    • -
  • ADC_SQR2_SQ7_3 : stm32f407xx_matlab.h
    • -
  • ADC_SQR2_SQ7_4 : stm32f407xx_matlab.h
    • -
  • ADC_SQR2_SQ7_Msk : stm32f407xx_matlab.h
    • -
  • ADC_SQR2_SQ7_Pos : stm32f407xx_matlab.h
    • -
  • ADC_SQR2_SQ8 : stm32f407xx_matlab.h
    • -
  • ADC_SQR2_SQ8_0 : stm32f407xx_matlab.h
    • -
  • ADC_SQR2_SQ8_1 : stm32f407xx_matlab.h
    • -
  • ADC_SQR2_SQ8_2 : stm32f407xx_matlab.h
    • -
  • ADC_SQR2_SQ8_3 : stm32f407xx_matlab.h
    • -
  • ADC_SQR2_SQ8_4 : stm32f407xx_matlab.h
    • -
  • ADC_SQR2_SQ8_Msk : stm32f407xx_matlab.h
    • -
  • ADC_SQR2_SQ8_Pos : stm32f407xx_matlab.h
    • -
  • ADC_SQR2_SQ9 : stm32f407xx_matlab.h
    • -
  • ADC_SQR2_SQ9_0 : stm32f407xx_matlab.h
    • -
  • ADC_SQR2_SQ9_1 : stm32f407xx_matlab.h
    • -
  • ADC_SQR2_SQ9_2 : stm32f407xx_matlab.h
    • -
  • ADC_SQR2_SQ9_3 : stm32f407xx_matlab.h
    • -
  • ADC_SQR2_SQ9_4 : stm32f407xx_matlab.h
    • -
  • ADC_SQR2_SQ9_Msk : stm32f407xx_matlab.h
    • -
  • ADC_SQR2_SQ9_Pos : stm32f407xx_matlab.h
    • -
  • ADC_SQR3_SQ1 : stm32f407xx_matlab.h
    • -
  • ADC_SQR3_SQ1_0 : stm32f407xx_matlab.h
    • -
  • ADC_SQR3_SQ1_1 : stm32f407xx_matlab.h
    • -
  • ADC_SQR3_SQ1_2 : stm32f407xx_matlab.h
    • -
  • ADC_SQR3_SQ1_3 : stm32f407xx_matlab.h
    • -
  • ADC_SQR3_SQ1_4 : stm32f407xx_matlab.h
    • -
  • ADC_SQR3_SQ1_Msk : stm32f407xx_matlab.h
    • -
  • ADC_SQR3_SQ1_Pos : stm32f407xx_matlab.h
    • -
  • ADC_SQR3_SQ2 : stm32f407xx_matlab.h
    • -
  • ADC_SQR3_SQ2_0 : stm32f407xx_matlab.h
    • -
  • ADC_SQR3_SQ2_1 : stm32f407xx_matlab.h
    • -
  • ADC_SQR3_SQ2_2 : stm32f407xx_matlab.h
    • -
  • ADC_SQR3_SQ2_3 : stm32f407xx_matlab.h
    • -
  • ADC_SQR3_SQ2_4 : stm32f407xx_matlab.h
    • -
  • ADC_SQR3_SQ2_Msk : stm32f407xx_matlab.h
    • -
  • ADC_SQR3_SQ2_Pos : stm32f407xx_matlab.h
    • -
  • ADC_SQR3_SQ3 : stm32f407xx_matlab.h
    • -
  • ADC_SQR3_SQ3_0 : stm32f407xx_matlab.h
    • -
  • ADC_SQR3_SQ3_1 : stm32f407xx_matlab.h
    • -
  • ADC_SQR3_SQ3_2 : stm32f407xx_matlab.h
    • -
  • ADC_SQR3_SQ3_3 : stm32f407xx_matlab.h
    • -
  • ADC_SQR3_SQ3_4 : stm32f407xx_matlab.h
    • -
  • ADC_SQR3_SQ3_Msk : stm32f407xx_matlab.h
    • -
  • ADC_SQR3_SQ3_Pos : stm32f407xx_matlab.h
    • -
  • ADC_SQR3_SQ4 : stm32f407xx_matlab.h
    • -
  • ADC_SQR3_SQ4_0 : stm32f407xx_matlab.h
    • -
  • ADC_SQR3_SQ4_1 : stm32f407xx_matlab.h
    • -
  • ADC_SQR3_SQ4_2 : stm32f407xx_matlab.h
    • -
  • ADC_SQR3_SQ4_3 : stm32f407xx_matlab.h
    • -
  • ADC_SQR3_SQ4_4 : stm32f407xx_matlab.h
    • -
  • ADC_SQR3_SQ4_Msk : stm32f407xx_matlab.h
    • -
  • ADC_SQR3_SQ4_Pos : stm32f407xx_matlab.h
    • -
  • ADC_SQR3_SQ5 : stm32f407xx_matlab.h
    • -
  • ADC_SQR3_SQ5_0 : stm32f407xx_matlab.h
    • -
  • ADC_SQR3_SQ5_1 : stm32f407xx_matlab.h
    • -
  • ADC_SQR3_SQ5_2 : stm32f407xx_matlab.h
    • -
  • ADC_SQR3_SQ5_3 : stm32f407xx_matlab.h
    • -
  • ADC_SQR3_SQ5_4 : stm32f407xx_matlab.h
    • -
  • ADC_SQR3_SQ5_Msk : stm32f407xx_matlab.h
    • -
  • ADC_SQR3_SQ5_Pos : stm32f407xx_matlab.h
    • -
  • ADC_SQR3_SQ6 : stm32f407xx_matlab.h
    • -
  • ADC_SQR3_SQ6_0 : stm32f407xx_matlab.h
    • -
  • ADC_SQR3_SQ6_1 : stm32f407xx_matlab.h
    • -
  • ADC_SQR3_SQ6_2 : stm32f407xx_matlab.h
    • -
  • ADC_SQR3_SQ6_3 : stm32f407xx_matlab.h
    • -
  • ADC_SQR3_SQ6_4 : stm32f407xx_matlab.h
    • -
  • ADC_SQR3_SQ6_Msk : stm32f407xx_matlab.h
    • -
  • ADC_SQR3_SQ6_Pos : stm32f407xx_matlab.h
    • -
  • ADC_SR_AWD : stm32f407xx_matlab.h
    • -
  • ADC_SR_AWD_Msk : stm32f407xx_matlab.h
    • -
  • ADC_SR_AWD_Pos : stm32f407xx_matlab.h
    • -
  • ADC_SR_EOC : stm32f407xx_matlab.h
    • -
  • ADC_SR_EOC_Msk : stm32f407xx_matlab.h
    • -
  • ADC_SR_EOC_Pos : stm32f407xx_matlab.h
    • -
  • ADC_SR_JEOC : stm32f407xx_matlab.h
    • -
  • ADC_SR_JEOC_Msk : stm32f407xx_matlab.h
    • -
  • ADC_SR_JEOC_Pos : stm32f407xx_matlab.h
    • -
  • ADC_SR_JSTRT : stm32f407xx_matlab.h
    • -
  • ADC_SR_JSTRT_Msk : stm32f407xx_matlab.h
    • -
  • ADC_SR_JSTRT_Pos : stm32f407xx_matlab.h
    • -
  • ADC_SR_OVR : stm32f407xx_matlab.h
    • -
  • ADC_SR_OVR_Msk : stm32f407xx_matlab.h
    • -
  • ADC_SR_OVR_Pos : stm32f407xx_matlab.h
    • -
  • ADC_SR_STRT : stm32f407xx_matlab.h
    • -
  • ADC_SR_STRT_Msk : stm32f407xx_matlab.h
    • -
  • ADC_SR_STRT_Pos : stm32f407xx_matlab.h
    • -
  • AHB1PERIPH_BASE : stm32f407xx_matlab.h
    • -
  • AHB2PERIPH_BASE : stm32f407xx_matlab.h
    • -
  • AHBPrescTable : system_stm32f4xx.h
    • -
  • APB1PERIPH_BASE : stm32f407xx_matlab.h
    • -
  • APB2PERIPH_BASE : stm32f407xx_matlab.h
    • -
  • APBPrescTable : system_stm32f4xx.h
    • -
  • APSR_C_Msk : core_cm4_matlab.h
    • -
  • APSR_C_Pos : core_cm4_matlab.h
    • -
  • APSR_GE_Msk : core_cm4_matlab.h
    • -
  • APSR_GE_Pos : core_cm4_matlab.h
    • -
  • APSR_N_Msk : core_cm4_matlab.h
    • -
  • APSR_N_Pos : core_cm4_matlab.h
    • -
  • APSR_Q_Msk : core_cm4_matlab.h
    • -
  • APSR_Q_Pos : core_cm4_matlab.h
    • -
  • APSR_V_Msk : core_cm4_matlab.h
    • -
  • APSR_V_Pos : core_cm4_matlab.h
    • -
  • APSR_Z_Msk : core_cm4_matlab.h
    • -
  • APSR_Z_Pos : core_cm4_matlab.h
    • -
  • ATOMIC_CLEAR_BIT : stm32f4xx.h
    • -
  • ATOMIC_CLEARH_BIT : stm32f4xx.h
    • -
  • ATOMIC_MODIFY_REG : stm32f4xx.h
    • -
  • ATOMIC_MODIFYH_REG : stm32f4xx.h
    • -
  • ATOMIC_SET_BIT : stm32f4xx.h
    • -
  • ATOMIC_SETH_BIT : stm32f4xx.h
    • diff --git a/DOCS/html/globals_b.html b/DOCS/html/globals_b.html index da3d6c3..c9e3898 100644 --- a/DOCS/html/globals_b.html +++ b/DOCS/html/globals_b.html @@ -14,6 +14,7 @@ + @@ -74,12 +75,11 @@ $(function() {
    Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

    - b -

    diff --git a/DOCS/html/globals_c.html b/DOCS/html/globals_c.html index ae64bcc..9badf29 100644 --- a/DOCS/html/globals_c.html +++ b/DOCS/html/globals_c.html @@ -14,6 +14,7 @@ + @@ -75,3631 +76,27 @@ $(function() {

    - c -

    diff --git a/DOCS/html/globals_d.html b/DOCS/html/globals_d.html index ac01de2..e176d88 100644 --- a/DOCS/html/globals_d.html +++ b/DOCS/html/globals_d.html @@ -14,6 +14,7 @@ + @@ -75,899 +76,38 @@ $(function() {

    - d -

    diff --git a/DOCS/html/globals_defs.html b/DOCS/html/globals_defs.html index babeb4e..76b8a09 100644 --- a/DOCS/html/globals_defs.html +++ b/DOCS/html/globals_defs.html @@ -14,6 +14,7 @@ + @@ -74,78 +75,173 @@ $(function() {
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    + + +

    - n -

    + + +

    - o -

    + + +

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    - t -

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    - u -

    + + +

    - w -

    diff --git a/DOCS/html/globals_defs_a.html b/DOCS/html/globals_defs_a.html deleted file mode 100644 index 4926ac0..0000000 --- a/DOCS/html/globals_defs_a.html +++ /dev/null @@ -1,660 +0,0 @@ - - - - - - - -STM MATLAB Simulator: Globals - - - - - - - - - - - -
    -
    - - - - - - -
    -
    STM MATLAB Simulator -
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    -
    - - - - - - -
    -
    STM MATLAB Simulator -
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    -
    - - - - - - -
    -
    STM MATLAB Simulator -
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    -
    - - - - - - -
    -
    STM MATLAB Simulator -
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    -
    - - - - - - -
    -
    STM MATLAB Simulator -
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    -
    - - - - - - -
    -
    STM MATLAB Simulator -
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    -
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    STM MATLAB Simulator -
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    -
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    STM MATLAB Simulator -
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    -
    - - - - - - -
    -
    STM MATLAB Simulator -
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  • spi3 : stm32f4xx_periph_registers.c
  • status : mexing.m
  • syscfg : stm32f4xx_periph_registers.c
    • -
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  • SystemClockDouble : mcu_wrapper.c
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  • SystemCoreClock : system_stm32f4xx.h
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  • SystemClockDouble : mcu_wrapper.c
    • @@ -200,19 +197,19 @@ $(function() {
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    • diff --git a/DOCS/html/globals_w.html b/DOCS/html/globals_w.html index 47b6bf2..095c455 100644 --- a/DOCS/html/globals_w.html +++ b/DOCS/html/globals_w.html @@ -14,6 +14,7 @@ + @@ -74,68 +75,10 @@ $(function() {
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    - - diff --git a/DOCS/html/group___c_m_s_i_s.map b/DOCS/html/group___c_m_s_i_s.map deleted file mode 100644 index 0a3f1de..0000000 --- a/DOCS/html/group___c_m_s_i_s.map +++ /dev/null @@ -1,5 +0,0 @@ - - - - - diff --git a/DOCS/html/group___c_m_s_i_s.md5 b/DOCS/html/group___c_m_s_i_s.md5 deleted file mode 100644 index aa2d897..0000000 --- a/DOCS/html/group___c_m_s_i_s.md5 +++ /dev/null @@ -1 +0,0 @@ -3b761744840b4e6c18904451a6b0f9dc \ No newline at end of file diff --git a/DOCS/html/group___c_m_s_i_s.png b/DOCS/html/group___c_m_s_i_s.png deleted file mode 100644 index 98ecac6c109c9c54b3252d0ecd768915a397d8f1..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 2240 zcmV;x2tW6UP)a5FRUIe2C0L*n$vj7D09uA#vc~TM!%| z7^IwnG+A-Ufde9kNL(T%9HJy#=!|knI1ua;MoEyc5E3uN+7PfIG2pBegW-V85(vhu zGtHs8v%Njl)sOAx^zS2$JY79KT{GVQzpJWyszF3VL_|bHMEYpZbOofFMx)XGrt2_k zhQr}W&+}fbd%s)i-l5Ef!C>&mrt2_kCX>lQ;NH6Tt0W+WjYcCD7Z;nZ#!T=$kLBg% zM)o~yWUnI98cG5pJ*Olf(sN1zB0Z-hAkuS60wO)9Q-o5R!C?B@G~f3tdGF}^y4FS4 z+sezTUz;fjNG*~ADq3DN=xp1CWv+E;_38_C2c+{{iK7ok^375bkVZw1$kBh}W%2Sd zj?}h&hRa!62e!HjI%RDwL|-4@&b6-Xlmw(U zwt!6w7F)8&`u=HS5H?*4;4-K?AdT>Sf2ws*wK4+Sb)@fND*%)Pq$W-Gk+TG+Z44r5 zyukK(TOSQ1fB|>{~h=kV8@Of-Rbm-lafF` z>|{O2!+^gYI1g9@-o*s@AAsfH`3j&w?*S!&*>V{hkLr7Yn}Lgi^&et_{1EVq;Q2p+ z|J7boX^p8QFdB{a>&6n``~H37@%ZVSn|%X#2=EA+%@w&6_!cI}!(d+oz8S3l1b7=0 zL*NI%W0*jE1$d!^s%!zSX8P#mu z0q3w2c0IF(!(r|BAq0&HY{qrK z&w;x!K{^N?6U^zgB-?`ZVUX{^^xJm?>p#Q<`OCm>SP%F!rGJ7=7>~!b-!o6Dp(K#s zcHm)5-#@e^_Iv@@is`qLMs7$(S{C3Xrk5$zx96fsUTHsO4(ci~>R}i<=B#Rj3a(Z_v^)&% zw7@R1jYyw$=InsydDgB(+1rTpO{Ga-Gr?D6TLrsFex)RVB7=Q1cJ?6d0^C0$5^0Un z#stb9luK&HXGtu1w%H`tDZ=AHxk#%`-4Z68S!iKlp^5sm!t(NRd}g6bfEzGDy@z1h zZA`F-KOg=I(*hV^E*g3oxWDGAi{#eYQ-n{3q-Ga-8AH`fA943Gv>qmQ+^HCCzj!+VC`zvrO=1RbmkAmC4ubLfZqZK**LwJEg8Iy zX+gxN7kiNP>BYi3{DgA|YI-qggpxphr-4U+-?4F`(eS%GhneqxjrAZu5ZT@~(dgYw zPc$0dH=vahjmqp$5-9Fn;2x%@9QSemcxV-PDR@N1ryRcx_z}}njz<%Nb;|M4XmlW6 zCIV(!bIwBmKO~=+je1@Yh7Bsx~h%IOWgsfl=Ov{PnK)chxCtYa#mj_;#*!F1F8*W!t3fZ2Ql%oc0|Tr6eGLeXuU=56qS - - - - - - -STM MATLAB Simulator: Status and Control Registers - - - - - - - - - - - -
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     Nested Vectored Interrupt Controller (NVIC)
     Type definitions for the NVIC Registers.
     
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    -Data Structures

    union  APSR_Type
     Union type to access the Application Program Status Register (APSR). More...
     
    union  IPSR_Type
     Union type to access the Interrupt Program Status Register (IPSR). More...
     
    union  xPSR_Type
     Union type to access the Special-Purpose Program Status Registers (xPSR). More...
     
    union  CONTROL_Type
     Union type to access the Control Registers (CONTROL). More...
     
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    -Macros

    #define APSR_N_Pos   31U
     
    #define APSR_N_Msk   (1UL << APSR_N_Pos)
     
    #define APSR_Z_Pos   30U
     
    #define APSR_Z_Msk   (1UL << APSR_Z_Pos)
     
    #define APSR_C_Pos   29U
     
    #define APSR_C_Msk   (1UL << APSR_C_Pos)
     
    #define APSR_V_Pos   28U
     
    #define APSR_V_Msk   (1UL << APSR_V_Pos)
     
    #define APSR_Q_Pos   27U
     
    #define APSR_Q_Msk   (1UL << APSR_Q_Pos)
     
    #define APSR_GE_Pos   16U
     
    #define APSR_GE_Msk   (0xFUL << APSR_GE_Pos)
     
    #define IPSR_ISR_Pos   0U
     
    #define IPSR_ISR_Msk   (0x1FFUL /*<< IPSR_ISR_Pos*/)
     
    #define xPSR_N_Pos   31U
     
    #define xPSR_N_Msk   (1UL << xPSR_N_Pos)
     
    #define xPSR_Z_Pos   30U
     
    #define xPSR_Z_Msk   (1UL << xPSR_Z_Pos)
     
    #define xPSR_C_Pos   29U
     
    #define xPSR_C_Msk   (1UL << xPSR_C_Pos)
     
    #define xPSR_V_Pos   28U
     
    #define xPSR_V_Msk   (1UL << xPSR_V_Pos)
     
    #define xPSR_Q_Pos   27U
     
    #define xPSR_Q_Msk   (1UL << xPSR_Q_Pos)
     
    #define xPSR_ICI_IT_2_Pos   25U
     
    #define xPSR_ICI_IT_2_Msk   (3UL << xPSR_ICI_IT_2_Pos)
     
    #define xPSR_T_Pos   24U
     
    #define xPSR_T_Msk   (1UL << xPSR_T_Pos)
     
    #define xPSR_GE_Pos   16U
     
    #define xPSR_GE_Msk   (0xFUL << xPSR_GE_Pos)
     
    #define xPSR_ICI_IT_1_Pos   10U
     
    #define xPSR_ICI_IT_1_Msk   (0x3FUL << xPSR_ICI_IT_1_Pos)
     
    #define xPSR_ISR_Pos   0U
     
    #define xPSR_ISR_Msk   (0x1FFUL /*<< xPSR_ISR_Pos*/)
     
    #define CONTROL_FPCA_Pos   2U
     
    #define CONTROL_FPCA_Msk   (1UL << CONTROL_FPCA_Pos)
     
    #define CONTROL_SPSEL_Pos   1U
     
    #define CONTROL_SPSEL_Msk   (1UL << CONTROL_SPSEL_Pos)
     
    #define CONTROL_nPRIV_Pos   0U
     
    #define CONTROL_nPRIV_Msk   (1UL /*<< CONTROL_nPRIV_Pos*/)
     
    -

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    Core Register type definitions.

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    ◆ APSR_N_Pos

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    #define APSR_N_Pos   31U
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    APSR: N Position

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    ◆ APSR_N_Msk

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    #define APSR_N_Msk   (1UL << APSR_N_Pos)
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    #define APSR_Z_Pos   30U
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    APSR: Z Position

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    ◆ APSR_Z_Msk

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    #define APSR_Z_Msk   (1UL << APSR_Z_Pos)
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    APSR: Z Mask

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    ◆ APSR_C_Pos

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    #define APSR_C_Pos   29U
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    APSR: C Position

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    ◆ APSR_C_Msk

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    #define APSR_C_Msk   (1UL << APSR_C_Pos)
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    APSR: C Mask

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    ◆ APSR_V_Pos

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    #define APSR_V_Pos   28U
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    APSR: V Position

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    #define APSR_V_Msk   (1UL << APSR_V_Pos)
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    APSR: GE Mask

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    ◆ IPSR_ISR_Pos

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    #define IPSR_ISR_Pos   0U
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    IPSR: ISR Position

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    ◆ IPSR_ISR_Msk

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    IPSR: ISR Mask

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    xPSR: N Position

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    xPSR: Z Position

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    xPSR: Z Mask

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    #define xPSR_C_Pos   29U
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    xPSR: C Position

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    #define xPSR_C_Msk   (1UL << xPSR_C_Pos)
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    xPSR: C Mask

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    ◆ xPSR_V_Pos

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    #define xPSR_V_Pos   28U
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    xPSR: V Position

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    ◆ xPSR_V_Msk

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    #define xPSR_V_Msk   (1UL << xPSR_V_Pos)
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    xPSR: V Mask

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    ◆ xPSR_Q_Pos

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    #define xPSR_Q_Pos   27U
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    xPSR: Q Position

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    ◆ xPSR_Q_Msk

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    #define xPSR_Q_Msk   (1UL << xPSR_Q_Pos)
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    xPSR: Q Mask

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    ◆ xPSR_ICI_IT_2_Pos

    - -
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    #define xPSR_ICI_IT_2_Pos   25U
    -
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    xPSR: ICI/IT part 2 Position

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    ◆ xPSR_ICI_IT_2_Msk

    - -
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    #define xPSR_ICI_IT_2_Msk   (3UL << xPSR_ICI_IT_2_Pos)
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    xPSR: ICI/IT part 2 Mask

    - -
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    ◆ xPSR_T_Pos

    - -
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    #define xPSR_T_Pos   24U
    -
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    xPSR: T Position

    - -
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    ◆ xPSR_T_Msk

    - -
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    #define xPSR_T_Msk   (1UL << xPSR_T_Pos)
    -
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    xPSR: T Mask

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    ◆ xPSR_GE_Pos

    - -
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    #define xPSR_GE_Pos   16U
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    xPSR: GE Position

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    ◆ xPSR_GE_Msk

    - -
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    #define xPSR_GE_Msk   (0xFUL << xPSR_GE_Pos)
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    xPSR: GE Mask

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    ◆ xPSR_ICI_IT_1_Pos

    - -
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    #define xPSR_ICI_IT_1_Pos   10U
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    xPSR: ICI/IT part 1 Position

    - -
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    ◆ xPSR_ICI_IT_1_Msk

    - -
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    #define xPSR_ICI_IT_1_Msk   (0x3FUL << xPSR_ICI_IT_1_Pos)
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    xPSR: ICI/IT part 1 Mask

    - -
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    ◆ xPSR_ISR_Pos

    - -
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    #define xPSR_ISR_Pos   0U
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    xPSR: ISR Position

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    ◆ xPSR_ISR_Msk

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    #define xPSR_ISR_Msk   (0x1FFUL /*<< xPSR_ISR_Pos*/)
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    xPSR: ISR Mask

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    ◆ CONTROL_FPCA_Pos

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    #define CONTROL_FPCA_Pos   2U
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    CONTROL: FPCA Position

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    ◆ CONTROL_FPCA_Msk

    - -
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    #define CONTROL_FPCA_Msk   (1UL << CONTROL_FPCA_Pos)
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    CONTROL: FPCA Mask

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    ◆ CONTROL_SPSEL_Pos

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    #define CONTROL_SPSEL_Pos   1U
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    CONTROL: SPSEL Position

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    ◆ CONTROL_SPSEL_Msk

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    #define CONTROL_SPSEL_Msk   (1UL << CONTROL_SPSEL_Pos)
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    CONTROL: SPSEL Mask

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    ◆ CONTROL_nPRIV_Pos

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    #define CONTROL_nPRIV_Pos   0U
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    CONTROL: nPRIV Position

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    ◆ CONTROL_nPRIV_Msk

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    #define CONTROL_nPRIV_Msk   (1UL /*<< CONTROL_nPRIV_Pos*/)
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    CONTROL: nPRIV Mask

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    -Generated by doxygen 1.10.0 -
    - - diff --git a/DOCS/html/group___c_m_s_i_s___c_o_r_e.map b/DOCS/html/group___c_m_s_i_s___c_o_r_e.map deleted file mode 100644 index 16fa9c0..0000000 --- a/DOCS/html/group___c_m_s_i_s___c_o_r_e.map +++ /dev/null @@ -1,5 +0,0 @@ - - - - - diff --git a/DOCS/html/group___c_m_s_i_s___c_o_r_e.md5 b/DOCS/html/group___c_m_s_i_s___c_o_r_e.md5 deleted file mode 100644 index e19e367..0000000 --- a/DOCS/html/group___c_m_s_i_s___c_o_r_e.md5 +++ /dev/null @@ -1 +0,0 @@ -61d1ab852aa1976990b852e55959ffbc \ No newline at end of file diff --git a/DOCS/html/group___c_m_s_i_s___c_o_r_e.png b/DOCS/html/group___c_m_s_i_s___c_o_r_e.png deleted file mode 100644 index b623166a4a5f74182756b342e1564064ecfa7007..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 2505 zcmV;)2{!hLP)kxO6&2>F79KuCxc@*4RP0f&_jHYZCv7Dfg_GQ**FOuM(M zyQ;got9ttTkw)I>N7cV)#?$}ldb9)p000000000000000!%06;U7$>dV#7!Zfi zXmn>bo9%~=qmJox`q|}j`Aq0I02}l9{HOV4?+p>-MbR2ao zm&+?jl3WNK2VjYW3fM&B@mO11TcN{1K!=BiS}Yc!!)WCE`SY4ir=i0Dj1CSCG@s84 z*Nr-k1pokG+TGA`008>wL_(D$$qUSDg8_O`1@nq*s-mIkv)L>_B<-6{r?cd2e{F~nY_EXF>>-zMWcRQyNAPz-I}8`Ft8yWHhu-uDxKK7OCa)A!dV zc5R-(`<5IKZ}=GKLj_>4iV~jLY&N(gyRTNOm6D`CcTg*fH--cQ&5%$5kfg`1PG$dH zn@*>X9@%C2ZHxA+D#ygMZMNQ`a%{^tF^V+Cx#}t^$ajD`71D{D>P-zVC&~a+m>-@UbBs%>Te(F#A14F z%9>VbB6PRD>SNolC;QyAuBc4ga;i?yRb_V(Z{0fUCRO>en#No7+(!&ekx&5xls}2* zmz8bbRvfN%+QigV^PS7*(t zk(g9n9c!abY(AT-RAu{RpO^8KC}ranYGg4PqIzn_#kD)_+3^6p}rBiygBUzJTKH_Rn#%Lj;7yT zwtaX)e1FF9z3elFu8zms6{@03mM+<5e*3;>s#$eA(zO{!omlF=M`g#~!}s|KNneum zlBBOl`oQt>*Mmjm$keZ>tn+kspQ2R{$ra0s@n^{&#I0i)N#i09>w@RPp4C@R;w51^SNoJ^pVnE?iVG!ENM&9 zf0ZUzYoC#H&}yItmoHyljmKkcZEc099+5aaJk(;b*qhJi7fUw#q@-_2dR5X>lHSqd zKde75>38i#X*QWmezvo-bAf(y@X7Z%=iuN#^Z8s?uUSHC(soctX4mN>4r)m7aXICA}@_$>ViTn05jp z^9f0pBz;HHvwHkmOP2Qt5 zn~^w8-vd+K4xW|tbx9LRAJgL}pC?T_0g-t|X}_qKC4E|aj)B(o=GTdjs}4;@Z`jmd zx2-vwXqXa_K4?46I(@cm-MV$_IZ1z#^n7lW?aAkcbETf_@9%3o9*3$P5xIN!?nfm3 zL1`0p_RGljbNpNHL0P(f{rcZ`c6LHlj}6u3`7>yfU)yE6c5;hhWP__NU(Z-I>CCux z?%cV*-MDe%Cz8G)=@m)ON&1hZ_gNP4eMyJT6?<^z%o$VPFAU7~_Vz;36{S~Mzpb>{ zI(v1h$`2&H)lPKf&YnH{JxL!8Q8(a2=LuCC*`n>0C)ehtKIr=OjFqP*zuS_2bo^NN zpZcz()2cox{YHU0rJp)=Dnzx2*Bwc396vs;bZU=RB#m`)Fh$<)6{u7C>C>k#g{T+s zrL~00c76@tC-16$Jho+Yt*n2M?Qt}n2Ej*}A+!|ZTgQ*rB<(0YA-$yHkx?j7Hid$( z@&`6=l#9P8{S3dR|NltXReB|;D!D>NO9NjT@o~PZD%<9~WZS>CtgN**r!{Dsx06EA z+#h*9nr2+ebg3^tg3LCls@reMg=utK()imKx+Tkq1<#-^^Ac}b{% z0s6P3pDUd${b@;m4I9p8m`Q2+-{w4WP*n4q{IjVvem!?60i}ozekB$#nIost=X#`kI!D zek!`(8ok*xgqtTt^a=CZ&=FJfC06~mKqdTEvfEj(30L1P@ zLN%Ms_Lbi62>_x%lN->Tm`3Tv5{C`?Pyy%#k|>}%u_Q6E#9@O`egFUf4Utd*001;Z zLInT-&=3g~002NkbV>&{z`c9-v{)=chk<||K71HDgvM^)zRlnRMD70l`^I%7R6x(I zR;#@S4<3XL0}&XFM*E>-sB1JD?H?T->FDSvbSMA-000000000000000z|sEzhSp_+ TjUyW|00000NkvXXu0mjfja}e0 diff --git a/DOCS/html/group___c_m_s_i_s___core___fpu_functions.html b/DOCS/html/group___c_m_s_i_s___core___fpu_functions.html deleted file mode 100644 index 1a1b3a5..0000000 --- a/DOCS/html/group___c_m_s_i_s___core___fpu_functions.html +++ /dev/null @@ -1,142 +0,0 @@ - - - - - - - -STM MATLAB Simulator: FPU Functions - - - - - - - - - - - -
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    FPU Functions
    Defines and Type Definitions » Status and Control Registers » Nested Vectored Interrupt Controller (NVIC) » System Control Block (SCB) » System Controls not in SCB (SCnSCB) » System Tick Timer (SysTick) » Instrumentation Trace Macrocell (ITM) » Data Watchpoint and Trace (DWT) » Trace Port Interface (TPI) » Floating Point Unit (FPU) » Core Debug Registers (CoreDebug) » Core register bit field macros » Core Definitions | Defines and Type Definitions » Status and Control Registers » Nested Vectored Interrupt Controller (NVIC) » System Control Block (SCB) » System Controls not in SCB (SCnSCB) » System Tick Timer (SysTick) » Instrumentation Trace Macrocell (ITM) » Data Watchpoint and Trace (DWT) » Trace Port Interface (TPI) » Floating Point Unit (FPU) » Core Debug Registers (CoreDebug) » Core register bit field macros » Core Definitions » Functions and Instructions Reference » NVIC Functions
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    Function that provides FPU type. -More...

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    - + Collaboration diagram for FPU Functions:
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     SysTick Functions
     Functions that configure the System.
     
    - - - - -

    -Functions

    __STATIC_INLINE uint32_t SCB_GetFPUType (void)
     get FPU type
     
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    Detailed Description

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    Function that provides FPU type.

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    Function Documentation

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    ◆ SCB_GetFPUType()

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    __STATIC_INLINE uint32_t SCB_GetFPUType (void )
    -
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    get FPU type

    -

    returns the FPU type

    Returns
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    • 0: No FPU
      • -
    • 1: Single precision FPU
      • -
    • 2: Double + Single precision FPU
      • -
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    - - diff --git a/DOCS/html/group___c_m_s_i_s___core___fpu_functions.map b/DOCS/html/group___c_m_s_i_s___core___fpu_functions.map deleted file mode 100644 index 9c57db7..0000000 --- a/DOCS/html/group___c_m_s_i_s___core___fpu_functions.map +++ /dev/null @@ -1,5 +0,0 @@ - - - - - diff --git a/DOCS/html/group___c_m_s_i_s___core___fpu_functions.md5 b/DOCS/html/group___c_m_s_i_s___core___fpu_functions.md5 deleted file mode 100644 index 1f4cc21..0000000 --- a/DOCS/html/group___c_m_s_i_s___core___fpu_functions.md5 +++ /dev/null @@ -1 +0,0 @@ -246de77d25a6433d0695910b549ab9cf \ No newline at end of file diff --git a/DOCS/html/group___c_m_s_i_s___core___fpu_functions.png b/DOCS/html/group___c_m_s_i_s___core___fpu_functions.png deleted file mode 100644 index 5771fba95633b80a069599f18e04e7dfa6be2961..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 1583 zcmV+~2GIG5P){LYK~#90?cGgi9AzBG@$ZbaD$ybZOQ01SJycA+BzUlj;z0#3D)t4d zMUZUvDD)zDQb9#TQ1G(dTs&3-dJsepLVHLLwgS~Ic_@!G3UDOTCdl;U^|XHy4~)RgTdfI+i^%U^!xp9!pnAr7dVb{ z#BrRn^@JofIRR|@ zZHG|U)YKGv_wKbFhGev|vcks3hV3v4nVFdxi|>x)ck$vy`u%?7I=ALnL_|bdO^H)P zM8tp+r-+D%0VPfm5fKAQoFXD329!8OL_`e4-i~6zaU49)OI#lJneb%dpQdAs3c6L$+iaC=qS`rtEBw`0XE&sujK(qe45-N1|Z$K2Pz zPjpL`rVIf!$!-_+Qyi)MQS_Km6AB2+8qs-owcsIfAQhCn*4{4aR=}ma1#IK z^?QfQ7pz5;Lt5g*yA&)F=UR7<3+RkL9 zCC;SYV%qwo?V{GD)g{KJfm6WSzyrW-N<211B243-oXr9Ifm^_xRwEM0sI}KP%N_<9 zeINYnI8NlSMX)?>o1{9T%FI(=2_6I92QCA@1E=wmCMaoEB0Q8k`abx%+wDdU`3B45 zwn?fZs?0p~mEa)oF0g`s%)N)7G+_*rX1K>VDr?)2CT}@K+7h*$B{z_HdYx4d@rLU+ z**5ArLR|c5`<}MnruF4?0C)|5SnLVlCjNCL7^8+O+}PKBjWKWCqrWwcFNBOld^Dl54bDJSc;b;p{gzN=TS?g4%Qo@MLER@P(g zJL5`Aa_-!@KW1lVjkbyEU52mOrA>g0DyxVh*Im_iCM!L0n)Et#oibg~vsr-Y>FLW$ zOG_v5pOW$x@Hkt~{L_2{{AOHn3HI&VSNbH87EYk4RnU_ieQ#=Va`GSG9sCJDr+^vE zu48@%{Ayfr2@V}P)BzsNyS?d**D}82S(H6o*>qL@UR&Ga+(}8dq~V4uz~{r)LHr~- z4?IkIgLWSHIZvfUO-xMKsCLIIX{h#Z;EUnwA>b9DgFi7S?Zj;f_&!giMNLjl8a)HH zjJBwb%U7leeH>Kvd#z-0P&m`atT$xs8S+T?=^}PE~#lD9G z$J__NQ~3Yz;3RNAExauyt}UtiJD#l*`}ObOEKMU7tixf z^!t62YlXXk7w~67zKlP_W@V^$etzE5gRI+S_#o@We!qXrV6$Do^Y{t$Rp3o54b^r! zoo{DnXOC9V^KQ~;nIsDyWPRq$nQeKpwbwYMQa6DghOY@))&r1Mx()m|eBA@wZ8sc| zcuJg-=3mh@HIA~Zc&l;QsNX5shASxcxmmw+!GNIu|bJbL`1}Z5~qlWhyf)| z5fKpsv6F*zAEz|MwQJYd*x0ZghGcZ(#tqvc6t=p$sy1+kyMFz8?7D4<({ z>C&Z2gOd8VuDh20sb=y#Z*g;T({>nQ$aUQdwqwZ4b=?c=>+7tquiFkqL_|bHL_|bH hL_|bHL`0;p{{i%8IX2i6?UVoj002ovPDHLkV1n~s8ukDH diff --git a/DOCS/html/group___c_m_s_i_s___core___function_interface.html b/DOCS/html/group___c_m_s_i_s___core___function_interface.html deleted file mode 100644 index 817bf30..0000000 --- a/DOCS/html/group___c_m_s_i_s___core___function_interface.html +++ /dev/null @@ -1,105 +0,0 @@ - - - - - - - -STM MATLAB Simulator: Functions and Instructions Reference - - - - - - - - - - - -
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    - - diff --git a/DOCS/html/group___c_m_s_i_s___core___function_interface.map b/DOCS/html/group___c_m_s_i_s___core___function_interface.map deleted file mode 100644 index 5096583..0000000 --- a/DOCS/html/group___c_m_s_i_s___core___function_interface.map +++ /dev/null @@ -1,5 +0,0 @@ - - - - - diff --git a/DOCS/html/group___c_m_s_i_s___core___function_interface.md5 b/DOCS/html/group___c_m_s_i_s___core___function_interface.md5 deleted file mode 100644 index ec2c29d..0000000 --- a/DOCS/html/group___c_m_s_i_s___core___function_interface.md5 +++ /dev/null @@ -1 +0,0 @@ -7112a69ab1f7ca68b878458cda220e85 \ No newline at end of file diff --git a/DOCS/html/group___c_m_s_i_s___core___function_interface.png b/DOCS/html/group___c_m_s_i_s___core___function_interface.png deleted file mode 100644 index 6c6ccfae502d04e28815060a30c0f2879631c338..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 2092 zcmZ`)c{JPU8vfb0K^Id+loloE=2}X|G9@L7L2I2-ZO2kXYHJ80)smqoQCzpJC~2bh z3RM#k9W6sjB&ofnXb>uCBbB0L(tGZ`|K0aH=lS0Ap7*@p^S$Re=gIZnL57eM^|R8dJK0H81jbNTr~%7e9cv-O}z-Tu!E zk5!+$Ss>)YSz5~2!2|I099@pP|b{f;DVKQ!G__( z&$An?4QByRxYB!w{zm;_^@ zc|6Se62lP$Wy17c^b{DvW;(CW{h20tXaw{wPBg%b63WfS_f(>3V#*|A5r;9!^GZN$ z4BDDqi(6=}j_bI;nc6&FZNR3=DlnS(^TfPY|Zy(i~s73f_g|GZGiEuPFBfyVFFM9Ux z4kt_mgag&}cIzD_KE+1+jmemt*$2o*SFokJ8wXEr)io#-^{-^#^wHQ6`;oY)@+X<7 z$<}a^AvZCpXn|ta$}_Ik;&c8v{L+-KA>2i6iK_Z9O8m_ThK>k{?@l z#)|4UP9=Brdaf!gYKtVA(uFdiCAtoXt8YpbCu(QUHY6K6geOr#j9>}YtMSEG)!nxK zAn3tRXIaKZ1%3Em(t}ysUNS>Z$>fr@X?T0^F}+clQq}Jo>!qS;nZ&SX3>eCvb=N4v zkL7CT-tCG**IR;{LrCn-r1_V*?C|}sVA~zFy@McgNwLs)%~GE>2PjALSjX)^77R9xt1K4=!Sq(5GE?*; zZ2|grK7kLmUlHdJT)5)j44c>%SGIc^V=0am4mz&ATT(D9{`I3;)pyt`so@df%}{#8 z5T!Q1ZZ&Q*EyaVS1#>JGwh+>A)_v@#bO7n_sI6Dr%`y;|dOp`|&kjGU68kTE<4a#G z<121-9^UE6$U(vX`1PJdaD$lJqiX@H&-bbmeDAFuJ1 ziN8~C>P+)Z920&T`9OVgp5#SMTj(pe1crNu772@ZdUAmuz{!w0RSp z-ud+iqO$8m!|PWdvLHghXu@*0^FaV#_1c2hrP^#A1FG;7x5w?!s=A= zOu$2Ag+=kIUbjq7w1E;JeJ?q_itfcG#Fj+zWfXN_z#jb){NCgA(JlwNYzqhn=wA=& z-Da~r2IEgPGc2UcvC}lnk9((TotO#v%E09?Lm&#%zywNWDM%~CB&V)Ssi(1%WSC_4 zaLpv|cpMzQ`MW|{2n`(q!#!9NZ5O1=i-(83SaBVr(e3G2>4RE7$ZM-%({|9}e12fv za*|znaN`*F24xMRVb1;Z$=e1o^M=RcUBo-u?Az1-xse&whFqI!M^)cSj0epMbY(CR zxeH$hU%a@frluwth?RIsXfqPZMGVUTV;7pow=4Ju-yhPHmj+sh|HrlRuyTh}IuNsC z*G~&|<-n+a diff --git a/DOCS/html/group___c_m_s_i_s___core___n_v_i_c_functions.html b/DOCS/html/group___c_m_s_i_s___core___n_v_i_c_functions.html deleted file mode 100644 index 285bfb8..0000000 --- a/DOCS/html/group___c_m_s_i_s___core___n_v_i_c_functions.html +++ /dev/null @@ -1,952 +0,0 @@ - - - - - - - -STM MATLAB Simulator: NVIC Functions - - - - - - - - - - - -
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     FPU Functions
     Function that provides FPU type.
     
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    #define NVIC_SetPriorityGrouping   __NVIC_SetPriorityGrouping
     
    #define NVIC_GetPriorityGrouping   __NVIC_GetPriorityGrouping
     
    #define NVIC_EnableIRQ   __NVIC_EnableIRQ
     
    #define NVIC_GetEnableIRQ   __NVIC_GetEnableIRQ
     
    #define NVIC_DisableIRQ   __NVIC_DisableIRQ
     
    #define NVIC_GetPendingIRQ   __NVIC_GetPendingIRQ
     
    #define NVIC_SetPendingIRQ   __NVIC_SetPendingIRQ
     
    #define NVIC_ClearPendingIRQ   __NVIC_ClearPendingIRQ
     
    #define NVIC_GetActive   __NVIC_GetActive
     
    #define NVIC_SetPriority   __NVIC_SetPriority
     
    #define NVIC_GetPriority   __NVIC_GetPriority
     
    #define NVIC_SystemReset   __NVIC_SystemReset
     
    #define NVIC_SetVector   __NVIC_SetVector
     
    #define NVIC_GetVector   __NVIC_GetVector
     
    #define NVIC_USER_IRQ_OFFSET   16
     
    #define EXC_RETURN_HANDLER   (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
     
    #define EXC_RETURN_THREAD_MSP   (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
     
    #define EXC_RETURN_THREAD_PSP   (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
     
    #define EXC_RETURN_HANDLER_FPU   (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */
     
    #define EXC_RETURN_THREAD_MSP_FPU   (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */
     
    #define EXC_RETURN_THREAD_PSP_FPU   (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */
     
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    __STATIC_INLINE void __NVIC_SetPriorityGrouping (uint32_t PriorityGroup)
     Set Priority Grouping.
     
    __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping (void)
     Get Priority Grouping.
     
    __STATIC_INLINE void __NVIC_EnableIRQ (IRQn_Type IRQn)
     Enable Interrupt.
     
    __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ (IRQn_Type IRQn)
     Get Interrupt Enable status.
     
    __STATIC_INLINE void __NVIC_DisableIRQ (IRQn_Type IRQn)
     Disable Interrupt.
     
    __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ (IRQn_Type IRQn)
     Get Pending Interrupt.
     
    __STATIC_INLINE void __NVIC_SetPendingIRQ (IRQn_Type IRQn)
     Set Pending Interrupt.
     
    __STATIC_INLINE void __NVIC_ClearPendingIRQ (IRQn_Type IRQn)
     Clear Pending Interrupt.
     
    __STATIC_INLINE uint32_t __NVIC_GetActive (IRQn_Type IRQn)
     Get Active Interrupt.
     
    __STATIC_INLINE void __NVIC_SetPriority (IRQn_Type IRQn, uint32_t priority)
     Set Interrupt Priority.
     
    __STATIC_INLINE uint32_t __NVIC_GetPriority (IRQn_Type IRQn)
     Get Interrupt Priority.
     
    __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
     Encode Priority.
     
    __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t *const pPreemptPriority, uint32_t *const pSubPriority)
     Decode Priority.
     
    __STATIC_INLINE void __NVIC_SetVector (IRQn_Type IRQn, uint32_t vector)
     Set Interrupt Vector.
     
    __STATIC_INLINE uint32_t __NVIC_GetVector (IRQn_Type IRQn)
     Get Interrupt Vector.
     
    __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset (void)
     System Reset.
     
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    ◆ NVIC_SetPriorityGrouping

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    Sets the priority grouping field using the required unlock sequence. The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. Only values from 0..7 are used. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.

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    Sets the pending bit of a device specific interrupt in the NVIC pending register.

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    Clears the pending bit of a device specific interrupt in the NVIC pending register.

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    Reads the active register in the NVIC and returns the active bit for the device specific interrupt.

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    Sets the priority of a device specific interrupt or a processor exception. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception.

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    Get Interrupt Priority.

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    Reads the priority of a device specific interrupt or a processor exception. The interrupt number can be positive to specify a device specific interrupt, or negative to specify a processor exception.

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    ◆ NVIC_EncodePriority()

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    Encode Priority.

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    Encodes the priority for an interrupt with the given priority group, preemptive priority value, and subpriority value. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.

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    Decode Priority.

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    Decodes an interrupt priority value with a given priority group to preemptive priority value and subpriority value. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.

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    [in]PriorityPriority value, which can be retrieved with the function NVIC_GetPriority().
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    Set Interrupt Vector.

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    [in]vectorAddress of interrupt handler function
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    Get Interrupt Vector.

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    - - diff --git a/DOCS/html/group___c_m_s_i_s___core___n_v_i_c_functions.map b/DOCS/html/group___c_m_s_i_s___core___n_v_i_c_functions.map deleted file mode 100644 index 71ddd69..0000000 --- a/DOCS/html/group___c_m_s_i_s___core___n_v_i_c_functions.map +++ /dev/null @@ -1,6 +0,0 @@ - - - - - - diff --git a/DOCS/html/group___c_m_s_i_s___core___n_v_i_c_functions.md5 b/DOCS/html/group___c_m_s_i_s___core___n_v_i_c_functions.md5 deleted file mode 100644 index e6c9863..0000000 --- a/DOCS/html/group___c_m_s_i_s___core___n_v_i_c_functions.md5 +++ /dev/null @@ -1 +0,0 @@ -116078c4ea7d22f16422fdbcff1a0faa \ No newline at end of file diff --git a/DOCS/html/group___c_m_s_i_s___core___n_v_i_c_functions.png b/DOCS/html/group___c_m_s_i_s___core___n_v_i_c_functions.png deleted file mode 100644 index e0b580a7f952569957232135cd1281474684aa06..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 3076 zcmZuz2T+sQ77hgIpokz^*-1VxZ4 ziAXcFKzyJgAfX6>K#)Z#0kQ%C2_!GOJ8$03n>Y8)z2BTO^Uawv_k8zDJnv|yAgdt@ z0)Z3&dutaENQ^JSx1=RSCr{BMS#(KWbFi}p3IANrnoBZ4Ai1}I^=Y^8yaiVDdk9vn z^N%&NwLD_jT;ON*LQ+^BDRMe7Ok1EY<9N<+@4WSWec7c)0)x`nq+d#R#3s#=Nw}h4 zX41``8$A?{JK6_x;?s4?uujFQrR?AYt;wz7h4iJWUTW{B#ZR11Jsb{y8+~E%Q&j83 zNONOvRO_-F1R(xryQmblZC|9$S0xwfQ=cbw*xSs6n5IvJP2kBFSc*V-^3S&IqRif; z!mI9mYGuEKiLbe{q(yNgYT^xrV)P-@KJHfSCFF_I#M{1AbCUMNq9Ao15n`N&f&wn| z|An4=Q93rxoZ~=d6Yx(1jt|_%F;Uz zwOMZLv)*Vhx);D6LHbVRXqQHGk|;b(%;AyqsfKrkyM2BPWz^<1jhdAsumTa) z3&fyN3k3MsL&<@ZP0Hf{qQ*aA?p%mMf#mV!O@7o8tVYp1lV8&l9 z%roa}eO=@Z2~&7QxNn`TW%JpLdZ0_ON3(9cG=f+(;yvt}HT`ojqF|QfGZOeQ3(_qq z;u!-Xed4c=UtU&4zJ#Dn)Oh%6vvHGG)sJ3Pp92^nM>xvw6uQ=WyIdUAyDoTqlYb0m zB2QQmldcV?msL6}|JZX?$9NxVom{yW2kKfu6*vxP0ZGr}k z)Xe|%TSp$graM3uvyk=_x2B=30tAQHugf*`0UskyBf|pMtk`ukLcl*Hx%nYe?+eIX zSsbrNso-yHF769Z7A%ryFTYv~nB2wX+_+>2WTJ*E0=@42oL&J$KPH!iVZON*-x47WGF^OETXOG?bON{z>>eU)(rVb&@T~FE zD9w_(+7j~hU82^Y1LJNYs`YQ(Kt?DxXs*j}wXMjF`o1wQShLRw5t`C%6QeT2iesVQ zQu3pKe_dAL1qTO{YepBONRhWGnfnk4Z{NOk531xDQd(!~g+k4?lX1yIb zZVkvk>A4b<@em@UOsuIa4Kmn|rC~(xvD9>%jR|S>iBnHUcO>~)hDx6m9}|KvEQ`28WIe_U?%0MsqINzr z>KzY;wR2wS`2mpm6Je(L$YtV3%~cBo-o}WdtKy$`{#>KKGu+T;C~RY8)|j?H^OZSm z>D1tQ{b`AzEzOH9_@uI%&7Gv@EHG;i_M5)AZ%|c#$?b8ft0NPu#~Ruf_DHKEM`K^t zYyMH(Dx#0ya#o|G0BH6K6c(v8D}fXK&_((`3f=^RAB?9reCYV|(T}{^{qWgB6aauZ9LR#{Ll6g%iJa#vo|B36{!M zTW)>Xh!a{JMVC>Wg40>U4(%=}ByaT9sav@%(({8-~3^OQtgRS2&kn4XrMO@+*+_Xa4mhH<#bn-rlZ! zM%BY1TzuF()}b%5ciqAU7Hp0g{!*877{H#-r3BQE?zVHTSz_KHzoHr#()yh&5sfSh ziFa{ZT3j?+DwZGJ$r?lRY5b4r#SV;`a>Vf3`scWtYCquP@|%x$4D5*3NB_!o_9kTC z8JMba5Q4d`R*zeywV=;ti36}&Ih^qjHkP!RdMdZ?d$OlhgIKqy^|XnYoS0}7^a}Cl z5e~Ahf`B7jCXCnGqe&l(q{bA(g%<&h%qqpZKShH>An)?96kyVtXnqQ_OwT)UmWZ4kK#3o>tcS$uv$|PLz_q{wR zyvR;u8TB4Oltf^M^%CbtY(;u;d_6)~K!2od=lKM{c6RFwE*2dn&h0@8D60^l-)Ao2 zkA5}dfeB$t3SAuVd3n;-vJzvo0gE2TkTs%IzD&>G0n@Z7GQB7fn;3K)2B#eLc{(Ww-WO58UtQxq^5v!SNbr zVph+<8mC|Wgs(cW$27`ZEoo|~z@6b}J5JT^$SL~vc!QD?FV|{1cM;w-CDj gwaP>Y`oNZsUHEs~Pi(Oek*x;-HjdU+R^Ipj4T5zk`2YX_ diff --git a/DOCS/html/group___c_m_s_i_s___core___sys_tick_functions.html b/DOCS/html/group___c_m_s_i_s___core___sys_tick_functions.html deleted file mode 100644 index ffb21f4..0000000 --- a/DOCS/html/group___c_m_s_i_s___core___sys_tick_functions.html +++ /dev/null @@ -1,109 +0,0 @@ - - - - - - - -STM MATLAB Simulator: SysTick Functions - - - - - - - - - - - -
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    Defines and Type Definitions » Status and Control Registers » Nested Vectored Interrupt Controller (NVIC) » System Control Block (SCB) » System Controls not in SCB (SCnSCB) » System Tick Timer (SysTick) » Instrumentation Trace Macrocell (ITM) » Data Watchpoint and Trace (DWT) » Trace Port Interface (TPI) » Floating Point Unit (FPU) » Core Debug Registers (CoreDebug) » Core register bit field macros » Core Definitions | Defines and Type Definitions » Status and Control Registers » Nested Vectored Interrupt Controller (NVIC) » System Control Block (SCB) » System Controls not in SCB (SCnSCB) » System Tick Timer (SysTick) » Instrumentation Trace Macrocell (ITM) » Data Watchpoint and Trace (DWT) » Trace Port Interface (TPI) » Floating Point Unit (FPU) » Core Debug Registers (CoreDebug) » Core register bit field macros » Core Definitions » Functions and Instructions Reference » NVIC Functions » FPU Functions
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     ITM Functions
     Functions that access the ITM debug interface.
     
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    Detailed Description

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    Functions that configure the System.

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    -Generated by doxygen 1.10.0 -
    - - diff --git a/DOCS/html/group___c_m_s_i_s___core___sys_tick_functions.map b/DOCS/html/group___c_m_s_i_s___core___sys_tick_functions.map deleted file mode 100644 index ceadaf7..0000000 --- a/DOCS/html/group___c_m_s_i_s___core___sys_tick_functions.map +++ /dev/null @@ -1,5 +0,0 @@ - - - - - diff --git a/DOCS/html/group___c_m_s_i_s___core___sys_tick_functions.md5 b/DOCS/html/group___c_m_s_i_s___core___sys_tick_functions.md5 deleted file mode 100644 index 3c97cee..0000000 --- a/DOCS/html/group___c_m_s_i_s___core___sys_tick_functions.md5 +++ /dev/null @@ -1 +0,0 @@ -a25e3c5fbfb7577107e53229550974a6 \ No newline at end of file diff --git a/DOCS/html/group___c_m_s_i_s___core___sys_tick_functions.png b/DOCS/html/group___c_m_s_i_s___core___sys_tick_functions.png deleted file mode 100644 index 4294ad9f3f77b96f5e5d8032b0d0d43982cc56cf..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 1564 zcmV+%2IKjOP)zR&y4Er^JSh=_=Yh=_=Yh=_>%&x>z3e*E}Dp64BK5sXw5 zhT%`EtE<1dj-!lDr*p`44AKt1?{D;ay|b?4D5Kl$J{<(XKG$)`c>R9=>-e_2;u}2A zJK%ZVS~DSuWru-nZ}Lu{b50^b5Uc|SUB^*I5Crdgp10yU4#{PFLX7l!y?R3ttGeB; z>kukiTwG*+e%^H$;?U*Gml+HOuEVHg|Ni|G@%K2X&YwR|zu!-M%x^dr5fPDAQbH6F z5kU!2L_`EoLKG1Z0hAC$L_`23L=h1YAmg%&B0O)~_5A>ZVVLXj=yyi%kK3NN?Iw(i zvE?4bT=TU8EIW>+kff#URWBFHS}q?QyW8#NYA5gSWwqPnkgt z+CEurBptI%dlmV>Gr;G-@4&a1^61@|L^yHDFh0T?m2^M46;bv$RsMTP)^mw|PKzNa zzR`WM+DJNPnf5H$gBb;W2mAqi0X&KMf6P;r48t%?>|3gizNWmd1T2mawSCu81nM%Mj2?UnQxrW|?MOG~Hiwv$$!$G}D#yvYZ_}}sY47yu z)6W8*VCGdu<$0fH0A~gMYuB!^xEK#RTheGSJ|`A+$m2R@Tk~gC<~422eb&`RQ|)bS zZOs6m0qB}IOG~x4Gn#CQBn0)9*&3TeZ2M%YYwJ`j(EOD?qD`F!P$WfAVbOb)B7^y$yT>oB>`3 zUc!tH1M>A*KLei@ZrFl_g@w0Wv^z~~^p$C}sHR0Ml>yETZyy2&fJ2z_=^nBdAB4cE zG7Z`=H#b-4_ibDvV6n6}wv7q6q#-v;uj^mHH^bXKz>Am><8zpKLyz<|5F0o;m-p`7 ztMBz}KwTx%)-0;2Yogc|+mp8q96tbl1l|Mg$IQj70k<&8@3!p*+bFGETGz;}?IXgv zHFZZ+VZCXCAXiJGSD>y4JGH>(f9fdH{Si zyzRp*xH*bhNES^G)Y~IZDD{;ICr+o+IplfX+O(8+CPlZ~B@DyE{eHj5T-<$_1qerg zCoq>|IC0{{iLkCO2%e^Li|444iyxeW%kowY0Rf()LQh zG>g6<_~glx+w$Lz8ySdIe*!(swTcfrjzy%3Ux1H+1K8C?Z9uWGW&ef)b*LhzOvBC?X;PC?Sf7hyWRjYP29hns)W-RR)8B z>oCNjn>TN|4xzFuSFWi4Y_aRtuctn?Eg|~8zYzq%`h^P@Y7I*4^L>BAbqr;NVYq(d z#tqkDNDKJBf7W#jW%<5;c5`!+&CN~Mp@@ixh=_=Yh=_=Yh=_ - - - - - - -STM MATLAB Simulator: Core Debug Registers (CoreDebug) - - - - - - - - - - - -
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     Core register bit field macros
     Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
     
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    struct  CoreDebug_Type
     Structure type to access the Core Debug Register (CoreDebug). More...
     
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    -Macros

    #define CoreDebug_DHCSR_DBGKEY_Pos   16U
     
    #define CoreDebug_DHCSR_DBGKEY_Msk   (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)
     
    #define CoreDebug_DHCSR_S_RESET_ST_Pos   25U
     
    #define CoreDebug_DHCSR_S_RESET_ST_Msk   (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)
     
    #define CoreDebug_DHCSR_S_RETIRE_ST_Pos   24U
     
    #define CoreDebug_DHCSR_S_RETIRE_ST_Msk   (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)
     
    #define CoreDebug_DHCSR_S_LOCKUP_Pos   19U
     
    #define CoreDebug_DHCSR_S_LOCKUP_Msk   (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)
     
    #define CoreDebug_DHCSR_S_SLEEP_Pos   18U
     
    #define CoreDebug_DHCSR_S_SLEEP_Msk   (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)
     
    #define CoreDebug_DHCSR_S_HALT_Pos   17U
     
    #define CoreDebug_DHCSR_S_HALT_Msk   (1UL << CoreDebug_DHCSR_S_HALT_Pos)
     
    #define CoreDebug_DHCSR_S_REGRDY_Pos   16U
     
    #define CoreDebug_DHCSR_S_REGRDY_Msk   (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)
     
    #define CoreDebug_DHCSR_C_SNAPSTALL_Pos   5U
     
    #define CoreDebug_DHCSR_C_SNAPSTALL_Msk   (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)
     
    #define CoreDebug_DHCSR_C_MASKINTS_Pos   3U
     
    #define CoreDebug_DHCSR_C_MASKINTS_Msk   (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)
     
    #define CoreDebug_DHCSR_C_STEP_Pos   2U
     
    #define CoreDebug_DHCSR_C_STEP_Msk   (1UL << CoreDebug_DHCSR_C_STEP_Pos)
     
    #define CoreDebug_DHCSR_C_HALT_Pos   1U
     
    #define CoreDebug_DHCSR_C_HALT_Msk   (1UL << CoreDebug_DHCSR_C_HALT_Pos)
     
    #define CoreDebug_DHCSR_C_DEBUGEN_Pos   0U
     
    #define CoreDebug_DHCSR_C_DEBUGEN_Msk   (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)
     
    #define CoreDebug_DCRSR_REGWnR_Pos   16U
     
    #define CoreDebug_DCRSR_REGWnR_Msk   (1UL << CoreDebug_DCRSR_REGWnR_Pos)
     
    #define CoreDebug_DCRSR_REGSEL_Pos   0U
     
    #define CoreDebug_DCRSR_REGSEL_Msk   (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)
     
    #define CoreDebug_DEMCR_TRCENA_Pos   24U
     
    #define CoreDebug_DEMCR_TRCENA_Msk   (1UL << CoreDebug_DEMCR_TRCENA_Pos)
     
    #define CoreDebug_DEMCR_MON_REQ_Pos   19U
     
    #define CoreDebug_DEMCR_MON_REQ_Msk   (1UL << CoreDebug_DEMCR_MON_REQ_Pos)
     
    #define CoreDebug_DEMCR_MON_STEP_Pos   18U
     
    #define CoreDebug_DEMCR_MON_STEP_Msk   (1UL << CoreDebug_DEMCR_MON_STEP_Pos)
     
    #define CoreDebug_DEMCR_MON_PEND_Pos   17U
     
    #define CoreDebug_DEMCR_MON_PEND_Msk   (1UL << CoreDebug_DEMCR_MON_PEND_Pos)
     
    #define CoreDebug_DEMCR_MON_EN_Pos   16U
     
    #define CoreDebug_DEMCR_MON_EN_Msk   (1UL << CoreDebug_DEMCR_MON_EN_Pos)
     
    #define CoreDebug_DEMCR_VC_HARDERR_Pos   10U
     
    #define CoreDebug_DEMCR_VC_HARDERR_Msk   (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)
     
    #define CoreDebug_DEMCR_VC_INTERR_Pos   9U
     
    #define CoreDebug_DEMCR_VC_INTERR_Msk   (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)
     
    #define CoreDebug_DEMCR_VC_BUSERR_Pos   8U
     
    #define CoreDebug_DEMCR_VC_BUSERR_Msk   (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)
     
    #define CoreDebug_DEMCR_VC_STATERR_Pos   7U
     
    #define CoreDebug_DEMCR_VC_STATERR_Msk   (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)
     
    #define CoreDebug_DEMCR_VC_CHKERR_Pos   6U
     
    #define CoreDebug_DEMCR_VC_CHKERR_Msk   (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)
     
    #define CoreDebug_DEMCR_VC_NOCPERR_Pos   5U
     
    #define CoreDebug_DEMCR_VC_NOCPERR_Msk   (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)
     
    #define CoreDebug_DEMCR_VC_MMERR_Pos   4U
     
    #define CoreDebug_DEMCR_VC_MMERR_Msk   (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)
     
    #define CoreDebug_DEMCR_VC_CORERESET_Pos   0U
     
    #define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)
     
    -

    Detailed Description

    -

    Type definitions for the Core Debug Registers.

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    Macro Definition Documentation

    - -

    ◆ CoreDebug_DHCSR_DBGKEY_Pos

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    #define CoreDebug_DHCSR_DBGKEY_Pos   16U
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    CoreDebug DHCSR: DBGKEY Position

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    ◆ CoreDebug_DHCSR_DBGKEY_Msk

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    #define CoreDebug_DHCSR_DBGKEY_Msk   (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)
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    CoreDebug DHCSR: DBGKEY Mask

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    ◆ CoreDebug_DHCSR_S_RESET_ST_Pos

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    #define CoreDebug_DHCSR_S_RESET_ST_Pos   25U
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    CoreDebug DHCSR: S_RESET_ST Position

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    ◆ CoreDebug_DHCSR_S_RESET_ST_Msk

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    #define CoreDebug_DHCSR_S_RESET_ST_Msk   (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)
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    CoreDebug DHCSR: S_RESET_ST Mask

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    ◆ CoreDebug_DHCSR_S_RETIRE_ST_Pos

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    #define CoreDebug_DHCSR_S_RETIRE_ST_Pos   24U
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    CoreDebug DHCSR: S_RETIRE_ST Position

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    ◆ CoreDebug_DHCSR_S_RETIRE_ST_Msk

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    #define CoreDebug_DHCSR_S_RETIRE_ST_Msk   (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)
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    CoreDebug DHCSR: S_RETIRE_ST Mask

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    ◆ CoreDebug_DHCSR_S_LOCKUP_Pos

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    #define CoreDebug_DHCSR_S_LOCKUP_Pos   19U
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    CoreDebug DHCSR: S_LOCKUP Position

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    ◆ CoreDebug_DHCSR_S_LOCKUP_Msk

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    #define CoreDebug_DHCSR_S_LOCKUP_Msk   (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)
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    CoreDebug DHCSR: S_LOCKUP Mask

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    ◆ CoreDebug_DHCSR_S_SLEEP_Pos

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    #define CoreDebug_DHCSR_S_SLEEP_Pos   18U
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    CoreDebug DHCSR: S_SLEEP Position

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    ◆ CoreDebug_DHCSR_S_SLEEP_Msk

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    #define CoreDebug_DHCSR_S_SLEEP_Msk   (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)
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    CoreDebug DHCSR: S_SLEEP Mask

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    ◆ CoreDebug_DHCSR_S_HALT_Pos

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    #define CoreDebug_DHCSR_S_HALT_Pos   17U
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    CoreDebug DHCSR: S_HALT Position

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    ◆ CoreDebug_DHCSR_S_HALT_Msk

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    #define CoreDebug_DHCSR_S_HALT_Msk   (1UL << CoreDebug_DHCSR_S_HALT_Pos)
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    CoreDebug DHCSR: S_HALT Mask

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    ◆ CoreDebug_DHCSR_S_REGRDY_Pos

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    #define CoreDebug_DHCSR_S_REGRDY_Pos   16U
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    CoreDebug DHCSR: S_REGRDY Position

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    ◆ CoreDebug_DHCSR_S_REGRDY_Msk

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    #define CoreDebug_DHCSR_S_REGRDY_Msk   (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)
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    CoreDebug DHCSR: S_REGRDY Mask

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    ◆ CoreDebug_DHCSR_C_SNAPSTALL_Pos

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    #define CoreDebug_DHCSR_C_SNAPSTALL_Pos   5U
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    CoreDebug DHCSR: C_SNAPSTALL Position

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    ◆ CoreDebug_DHCSR_C_SNAPSTALL_Msk

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    #define CoreDebug_DHCSR_C_SNAPSTALL_Msk   (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)
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    CoreDebug DHCSR: C_SNAPSTALL Mask

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    ◆ CoreDebug_DHCSR_C_MASKINTS_Pos

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    #define CoreDebug_DHCSR_C_MASKINTS_Pos   3U
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    CoreDebug DHCSR: C_MASKINTS Position

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    ◆ CoreDebug_DHCSR_C_MASKINTS_Msk

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    #define CoreDebug_DHCSR_C_MASKINTS_Msk   (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)
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    CoreDebug DHCSR: C_MASKINTS Mask

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    ◆ CoreDebug_DHCSR_C_STEP_Pos

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    #define CoreDebug_DHCSR_C_STEP_Pos   2U
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    CoreDebug DHCSR: C_STEP Position

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    ◆ CoreDebug_DHCSR_C_STEP_Msk

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    #define CoreDebug_DHCSR_C_STEP_Msk   (1UL << CoreDebug_DHCSR_C_STEP_Pos)
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    CoreDebug DHCSR: C_STEP Mask

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    ◆ CoreDebug_DHCSR_C_HALT_Pos

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    #define CoreDebug_DHCSR_C_HALT_Pos   1U
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    CoreDebug DHCSR: C_HALT Position

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    ◆ CoreDebug_DHCSR_C_HALT_Msk

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    #define CoreDebug_DHCSR_C_HALT_Msk   (1UL << CoreDebug_DHCSR_C_HALT_Pos)
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    CoreDebug DHCSR: C_HALT Mask

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    ◆ CoreDebug_DHCSR_C_DEBUGEN_Pos

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    #define CoreDebug_DHCSR_C_DEBUGEN_Pos   0U
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    CoreDebug DHCSR: C_DEBUGEN Position

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    ◆ CoreDebug_DHCSR_C_DEBUGEN_Msk

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    #define CoreDebug_DHCSR_C_DEBUGEN_Msk   (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)
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    CoreDebug DHCSR: C_DEBUGEN Mask

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    ◆ CoreDebug_DCRSR_REGWnR_Pos

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    #define CoreDebug_DCRSR_REGWnR_Pos   16U
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    CoreDebug DCRSR: REGWnR Position

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    ◆ CoreDebug_DCRSR_REGWnR_Msk

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    #define CoreDebug_DCRSR_REGWnR_Msk   (1UL << CoreDebug_DCRSR_REGWnR_Pos)
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    CoreDebug DCRSR: REGWnR Mask

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    ◆ CoreDebug_DCRSR_REGSEL_Pos

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    #define CoreDebug_DCRSR_REGSEL_Pos   0U
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    CoreDebug DCRSR: REGSEL Position

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    ◆ CoreDebug_DCRSR_REGSEL_Msk

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    #define CoreDebug_DCRSR_REGSEL_Msk   (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)
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    CoreDebug DCRSR: REGSEL Mask

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    ◆ CoreDebug_DEMCR_TRCENA_Pos

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    #define CoreDebug_DEMCR_TRCENA_Pos   24U
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    CoreDebug DEMCR: TRCENA Position

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    ◆ CoreDebug_DEMCR_TRCENA_Msk

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    #define CoreDebug_DEMCR_TRCENA_Msk   (1UL << CoreDebug_DEMCR_TRCENA_Pos)
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    CoreDebug DEMCR: TRCENA Mask

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    ◆ CoreDebug_DEMCR_MON_REQ_Pos

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    #define CoreDebug_DEMCR_MON_REQ_Pos   19U
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    CoreDebug DEMCR: MON_REQ Position

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    ◆ CoreDebug_DEMCR_MON_REQ_Msk

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    #define CoreDebug_DEMCR_MON_REQ_Msk   (1UL << CoreDebug_DEMCR_MON_REQ_Pos)
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    CoreDebug DEMCR: MON_REQ Mask

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    ◆ CoreDebug_DEMCR_MON_STEP_Pos

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    #define CoreDebug_DEMCR_MON_STEP_Pos   18U
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    CoreDebug DEMCR: MON_STEP Position

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    ◆ CoreDebug_DEMCR_MON_STEP_Msk

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    #define CoreDebug_DEMCR_MON_STEP_Msk   (1UL << CoreDebug_DEMCR_MON_STEP_Pos)
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    CoreDebug DEMCR: MON_STEP Mask

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    ◆ CoreDebug_DEMCR_MON_PEND_Pos

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    #define CoreDebug_DEMCR_MON_PEND_Pos   17U
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    CoreDebug DEMCR: MON_PEND Position

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    ◆ CoreDebug_DEMCR_MON_PEND_Msk

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    #define CoreDebug_DEMCR_MON_PEND_Msk   (1UL << CoreDebug_DEMCR_MON_PEND_Pos)
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    CoreDebug DEMCR: MON_PEND Mask

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    ◆ CoreDebug_DEMCR_MON_EN_Pos

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    #define CoreDebug_DEMCR_MON_EN_Pos   16U
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    CoreDebug DEMCR: MON_EN Position

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    ◆ CoreDebug_DEMCR_MON_EN_Msk

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    #define CoreDebug_DEMCR_MON_EN_Msk   (1UL << CoreDebug_DEMCR_MON_EN_Pos)
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    CoreDebug DEMCR: MON_EN Mask

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    ◆ CoreDebug_DEMCR_VC_HARDERR_Pos

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    #define CoreDebug_DEMCR_VC_HARDERR_Pos   10U
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    CoreDebug DEMCR: VC_HARDERR Position

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    ◆ CoreDebug_DEMCR_VC_HARDERR_Msk

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    #define CoreDebug_DEMCR_VC_HARDERR_Msk   (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)
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    CoreDebug DEMCR: VC_HARDERR Mask

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    ◆ CoreDebug_DEMCR_VC_INTERR_Pos

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    #define CoreDebug_DEMCR_VC_INTERR_Pos   9U
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    CoreDebug DEMCR: VC_INTERR Position

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    ◆ CoreDebug_DEMCR_VC_INTERR_Msk

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    #define CoreDebug_DEMCR_VC_INTERR_Msk   (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)
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    CoreDebug DEMCR: VC_INTERR Mask

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    ◆ CoreDebug_DEMCR_VC_BUSERR_Pos

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    #define CoreDebug_DEMCR_VC_BUSERR_Pos   8U
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    CoreDebug DEMCR: VC_BUSERR Position

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    ◆ CoreDebug_DEMCR_VC_BUSERR_Msk

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    #define CoreDebug_DEMCR_VC_BUSERR_Msk   (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)
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    CoreDebug DEMCR: VC_BUSERR Mask

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    ◆ CoreDebug_DEMCR_VC_STATERR_Pos

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    #define CoreDebug_DEMCR_VC_STATERR_Pos   7U
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    CoreDebug DEMCR: VC_STATERR Position

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    ◆ CoreDebug_DEMCR_VC_STATERR_Msk

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    #define CoreDebug_DEMCR_VC_STATERR_Msk   (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)
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    CoreDebug DEMCR: VC_STATERR Mask

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    ◆ CoreDebug_DEMCR_VC_CHKERR_Pos

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    #define CoreDebug_DEMCR_VC_CHKERR_Pos   6U
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    CoreDebug DEMCR: VC_CHKERR Position

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    ◆ CoreDebug_DEMCR_VC_CHKERR_Msk

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    #define CoreDebug_DEMCR_VC_CHKERR_Msk   (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)
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    CoreDebug DEMCR: VC_CHKERR Mask

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    ◆ CoreDebug_DEMCR_VC_NOCPERR_Pos

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    #define CoreDebug_DEMCR_VC_NOCPERR_Pos   5U
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    CoreDebug DEMCR: VC_NOCPERR Position

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    ◆ CoreDebug_DEMCR_VC_NOCPERR_Msk

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    #define CoreDebug_DEMCR_VC_NOCPERR_Msk   (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)
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    CoreDebug DEMCR: VC_NOCPERR Mask

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    ◆ CoreDebug_DEMCR_VC_MMERR_Pos

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    #define CoreDebug_DEMCR_VC_MMERR_Pos   4U
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    CoreDebug DEMCR: VC_MMERR Position

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    ◆ CoreDebug_DEMCR_VC_MMERR_Msk

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    #define CoreDebug_DEMCR_VC_MMERR_Msk   (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)
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    CoreDebug DEMCR: VC_MMERR Mask

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    ◆ CoreDebug_DEMCR_VC_CORERESET_Pos

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    #define CoreDebug_DEMCR_VC_CORERESET_Pos   0U
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    CoreDebug DEMCR: VC_CORERESET Position

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    ◆ CoreDebug_DEMCR_VC_CORERESET_Msk

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    #define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)
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    CoreDebug DEMCR: VC_CORERESET Mask

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    -Generated by doxygen 1.10.0 -
    - - diff --git a/DOCS/html/group___c_m_s_i_s___core_debug.map b/DOCS/html/group___c_m_s_i_s___core_debug.map deleted file mode 100644 index c2f9be8..0000000 --- a/DOCS/html/group___c_m_s_i_s___core_debug.map +++ /dev/null @@ -1,5 +0,0 @@ - - - - - diff --git a/DOCS/html/group___c_m_s_i_s___core_debug.md5 b/DOCS/html/group___c_m_s_i_s___core_debug.md5 deleted file mode 100644 index ed075b4..0000000 --- a/DOCS/html/group___c_m_s_i_s___core_debug.md5 +++ /dev/null @@ -1 +0,0 @@ -14a88c01a6b561b27f0e78c0c648cd76 \ No newline at end of file diff --git a/DOCS/html/group___c_m_s_i_s___core_debug.png b/DOCS/html/group___c_m_s_i_s___core_debug.png deleted file mode 100644 index 9c049ef93a5b82ac0844849de03d203eb25a2d65..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 2396 zcmV-i38VIjP)fuu;3dm?8G>dHLS#CSKf0^i<)ONh zN=^NFtLlC0t$OSCfo7(ws^9nN>7Ms}`hDN31`!bv5fKp)5fKp)5fKp)k?=*?4Hqt4 zcsz=t(>{Wceu?AwPnR!We#3VhO>A#(pYNI;ZGh=_f+haeROO`gdDgm6^x19$PULl~bpD7k{5INS_kd$BykGbfSL0k29 z@f@U?bo)5Ow#7%ASXO7A?Hc$*0R#Qeh_B ziFMtnW$Wr|rAXz(e$hUYIiaF*vcI=gXNWH^jym&Ob>k`fk7CJ`oamDN{N#(Jd2^zTqsf8Kp*rmAf;Y3ohOHZ8ZTy|2^P z)V*IPcBpQntM;45W4kX*>(v^GHf5NuVKB{pZN$~}Je&CEyF+SQzsYopjfJ6g>T6p^ z)nk3XW@F*Heb0N0X@}`Dwm!Dewx_17B@(vy9)j=Vi!Q_EV(8rWaJ=cK`L=OplZ>hk zzfMBp>+BqPpiNufwx7s$q*d*{?|!L@@A!I^NaPLCi1^fY*xN-X)u)axZ<-;!&qn!c zRj);z`ZTrCUfU^CUysczqw2Zz{R5`&_dyd6e z-VnR(4yNuWbd&mRk50H6?I>Fq>LM0b<+c<7r-7dU&-)6Zt}fam7o!tZYb0#f*B3tG z>wH9_Y)C1+&(@o_s?56T4v7^p$$)LtV_IKJ?*KjtoF_>lj;*%;)K!Hpm<)N>85VCl zG~cBDqJ3p+5z_mboN}5sDp3}vX?-Tob-m5y>tex2fG+~i0`FgK`=RSfZ8B+(>aGD#RO04@T5Ci(w(ktB(L2T6oD zr1svA;2VD1Qv@Sb_UTFubf%@c=EvAyLTS}egT{T9sy!us zKq9sUok;i`6>xbKu^xL1_$|pgipPMz`VFW5Oh0+&9W$Ly@87c9(?83Ots84u8D+7Q z-Or0R&}8N>z_)?-k&IS|CF`~}ilT?w-R%AB_B#90b+jobM57yi&c3LDPe1si^DiB$ zGaX`Ms-#VQCS?YgG?ZBa|MVS1XtL|nfZTO!d0!4`vd?BYp$U3KB2OI058blTS>*Z_ z@*6nN40t_+^hCCuF8j_2+hx`*Cp4oQk*E^-3ohei;}ieLMhzrjuBRKuc7;tP z5+Vc8_ACY)pZGOuAR)+`c5p#c8&b&D*PDyv$y;RT;yMjg`|Ez?d0QIo5Fe_Nh^9%# z7#3KjX+)xdu?<^Ew@kj&s?HZ*RUMn{#GBMtw6E;!i}b!g&(e?{O1Iy6ZMkXNUUux* z`iP(tiR^`;np}*k>9HE65EDfgUut?vXwmjM$J(gRbbrylfnShHI##tPvh04FMVeKK z##m@-LqxpL2!u!&f*z3oKbNc4XoS=ez$Kv@DVi=BvB@t5BSUb)- z(=Z~^Pny~g5fPEblt_q(h)82fBt%3+q%kEDA|fKvSm9zzEqIclyLs~_i^als7!sI! z_wM-)p|$JRud9uhT5jFCRk-g^A~BgvZY-C}ovT-`It@ztZ!($O@Et=_aUAd5zJ1$w z7!s(-WU}i!hNdQy$?n0y0S5;MzC#fa5fKp)5fKp)5fKp)5fKp?jQ<0|;+S(H8Ow$M O0000 - - - - - - -STM MATLAB Simulator: Data Watchpoint and Trace (DWT) - - - - - - - - - - - -
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    -Topics | -Data Structures | -Macros
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    Data Watchpoint and Trace (DWT)
    Defines and Type Definitions » Status and Control Registers » Nested Vectored Interrupt Controller (NVIC) » System Control Block (SCB) » System Controls not in SCB (SCnSCB) » System Tick Timer (SysTick) » Instrumentation Trace Macrocell (ITM)
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    Type definitions for the Data Watchpoint and Trace (DWT) -More...

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    - + Collaboration diagram for Data Watchpoint and Trace (DWT):
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    -Topics

     Trace Port Interface (TPI)
     Type definitions for the Trace Port Interface (TPI)
     
    - - - - -

    -Data Structures

    struct  DWT_Type
     Structure type to access the Data Watchpoint and Trace Register (DWT). More...
     
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    -Macros

    #define DWT_CTRL_NUMCOMP_Pos   28U
     
    #define DWT_CTRL_NUMCOMP_Msk   (0xFUL << DWT_CTRL_NUMCOMP_Pos)
     
    #define DWT_CTRL_NOTRCPKT_Pos   27U
     
    #define DWT_CTRL_NOTRCPKT_Msk   (0x1UL << DWT_CTRL_NOTRCPKT_Pos)
     
    #define DWT_CTRL_NOEXTTRIG_Pos   26U
     
    #define DWT_CTRL_NOEXTTRIG_Msk   (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)
     
    #define DWT_CTRL_NOCYCCNT_Pos   25U
     
    #define DWT_CTRL_NOCYCCNT_Msk   (0x1UL << DWT_CTRL_NOCYCCNT_Pos)
     
    #define DWT_CTRL_NOPRFCNT_Pos   24U
     
    #define DWT_CTRL_NOPRFCNT_Msk   (0x1UL << DWT_CTRL_NOPRFCNT_Pos)
     
    #define DWT_CTRL_CYCEVTENA_Pos   22U
     
    #define DWT_CTRL_CYCEVTENA_Msk   (0x1UL << DWT_CTRL_CYCEVTENA_Pos)
     
    #define DWT_CTRL_FOLDEVTENA_Pos   21U
     
    #define DWT_CTRL_FOLDEVTENA_Msk   (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)
     
    #define DWT_CTRL_LSUEVTENA_Pos   20U
     
    #define DWT_CTRL_LSUEVTENA_Msk   (0x1UL << DWT_CTRL_LSUEVTENA_Pos)
     
    #define DWT_CTRL_SLEEPEVTENA_Pos   19U
     
    #define DWT_CTRL_SLEEPEVTENA_Msk   (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)
     
    #define DWT_CTRL_EXCEVTENA_Pos   18U
     
    #define DWT_CTRL_EXCEVTENA_Msk   (0x1UL << DWT_CTRL_EXCEVTENA_Pos)
     
    #define DWT_CTRL_CPIEVTENA_Pos   17U
     
    #define DWT_CTRL_CPIEVTENA_Msk   (0x1UL << DWT_CTRL_CPIEVTENA_Pos)
     
    #define DWT_CTRL_EXCTRCENA_Pos   16U
     
    #define DWT_CTRL_EXCTRCENA_Msk   (0x1UL << DWT_CTRL_EXCTRCENA_Pos)
     
    #define DWT_CTRL_PCSAMPLENA_Pos   12U
     
    #define DWT_CTRL_PCSAMPLENA_Msk   (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)
     
    #define DWT_CTRL_SYNCTAP_Pos   10U
     
    #define DWT_CTRL_SYNCTAP_Msk   (0x3UL << DWT_CTRL_SYNCTAP_Pos)
     
    #define DWT_CTRL_CYCTAP_Pos   9U
     
    #define DWT_CTRL_CYCTAP_Msk   (0x1UL << DWT_CTRL_CYCTAP_Pos)
     
    #define DWT_CTRL_POSTINIT_Pos   5U
     
    #define DWT_CTRL_POSTINIT_Msk   (0xFUL << DWT_CTRL_POSTINIT_Pos)
     
    #define DWT_CTRL_POSTPRESET_Pos   1U
     
    #define DWT_CTRL_POSTPRESET_Msk   (0xFUL << DWT_CTRL_POSTPRESET_Pos)
     
    #define DWT_CTRL_CYCCNTENA_Pos   0U
     
    #define DWT_CTRL_CYCCNTENA_Msk   (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)
     
    #define DWT_CPICNT_CPICNT_Pos   0U
     
    #define DWT_CPICNT_CPICNT_Msk   (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)
     
    #define DWT_EXCCNT_EXCCNT_Pos   0U
     
    #define DWT_EXCCNT_EXCCNT_Msk   (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)
     
    #define DWT_SLEEPCNT_SLEEPCNT_Pos   0U
     
    #define DWT_SLEEPCNT_SLEEPCNT_Msk   (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)
     
    #define DWT_LSUCNT_LSUCNT_Pos   0U
     
    #define DWT_LSUCNT_LSUCNT_Msk   (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)
     
    #define DWT_FOLDCNT_FOLDCNT_Pos   0U
     
    #define DWT_FOLDCNT_FOLDCNT_Msk   (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)
     
    #define DWT_MASK_MASK_Pos   0U
     
    #define DWT_MASK_MASK_Msk   (0x1FUL /*<< DWT_MASK_MASK_Pos*/)
     
    #define DWT_FUNCTION_MATCHED_Pos   24U
     
    #define DWT_FUNCTION_MATCHED_Msk   (0x1UL << DWT_FUNCTION_MATCHED_Pos)
     
    #define DWT_FUNCTION_DATAVADDR1_Pos   16U
     
    #define DWT_FUNCTION_DATAVADDR1_Msk   (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)
     
    #define DWT_FUNCTION_DATAVADDR0_Pos   12U
     
    #define DWT_FUNCTION_DATAVADDR0_Msk   (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)
     
    #define DWT_FUNCTION_DATAVSIZE_Pos   10U
     
    #define DWT_FUNCTION_DATAVSIZE_Msk   (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)
     
    #define DWT_FUNCTION_LNK1ENA_Pos   9U
     
    #define DWT_FUNCTION_LNK1ENA_Msk   (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)
     
    #define DWT_FUNCTION_DATAVMATCH_Pos   8U
     
    #define DWT_FUNCTION_DATAVMATCH_Msk   (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)
     
    #define DWT_FUNCTION_CYCMATCH_Pos   7U
     
    #define DWT_FUNCTION_CYCMATCH_Msk   (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)
     
    #define DWT_FUNCTION_EMITRANGE_Pos   5U
     
    #define DWT_FUNCTION_EMITRANGE_Msk   (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)
     
    #define DWT_FUNCTION_FUNCTION_Pos   0U
     
    #define DWT_FUNCTION_FUNCTION_Msk   (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)
     
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    Detailed Description

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    Type definitions for the Data Watchpoint and Trace (DWT)

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    Macro Definition Documentation

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    ◆ DWT_CTRL_NUMCOMP_Pos

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    #define DWT_CTRL_NUMCOMP_Pos   28U
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    DWT CTRL: NUMCOMP Position

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    ◆ DWT_CTRL_NUMCOMP_Msk

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    #define DWT_CTRL_NUMCOMP_Msk   (0xFUL << DWT_CTRL_NUMCOMP_Pos)
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    DWT CTRL: NUMCOMP Mask

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    ◆ DWT_CTRL_NOTRCPKT_Pos

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    #define DWT_CTRL_NOTRCPKT_Pos   27U
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    DWT CTRL: NOTRCPKT Position

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    ◆ DWT_CTRL_NOTRCPKT_Msk

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    #define DWT_CTRL_NOTRCPKT_Msk   (0x1UL << DWT_CTRL_NOTRCPKT_Pos)
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    DWT CTRL: NOTRCPKT Mask

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    ◆ DWT_CTRL_NOEXTTRIG_Pos

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    #define DWT_CTRL_NOEXTTRIG_Pos   26U
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    DWT CTRL: NOEXTTRIG Position

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    ◆ DWT_CTRL_NOEXTTRIG_Msk

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    #define DWT_CTRL_NOEXTTRIG_Msk   (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)
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    DWT CTRL: NOEXTTRIG Mask

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    ◆ DWT_CTRL_NOCYCCNT_Pos

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    #define DWT_CTRL_NOCYCCNT_Pos   25U
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    DWT CTRL: NOCYCCNT Position

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    ◆ DWT_CTRL_NOCYCCNT_Msk

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    #define DWT_CTRL_NOCYCCNT_Msk   (0x1UL << DWT_CTRL_NOCYCCNT_Pos)
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    DWT CTRL: NOCYCCNT Mask

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    ◆ DWT_CTRL_NOPRFCNT_Pos

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    #define DWT_CTRL_NOPRFCNT_Pos   24U
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    DWT CTRL: NOPRFCNT Position

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    ◆ DWT_CTRL_NOPRFCNT_Msk

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    #define DWT_CTRL_NOPRFCNT_Msk   (0x1UL << DWT_CTRL_NOPRFCNT_Pos)
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    DWT CTRL: NOPRFCNT Mask

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    ◆ DWT_CTRL_CYCEVTENA_Pos

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    #define DWT_CTRL_CYCEVTENA_Pos   22U
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    DWT CTRL: CYCEVTENA Position

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    ◆ DWT_CTRL_CYCEVTENA_Msk

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    #define DWT_CTRL_CYCEVTENA_Msk   (0x1UL << DWT_CTRL_CYCEVTENA_Pos)
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    DWT CTRL: CYCEVTENA Mask

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    ◆ DWT_CTRL_FOLDEVTENA_Pos

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    #define DWT_CTRL_FOLDEVTENA_Pos   21U
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    DWT CTRL: FOLDEVTENA Position

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    ◆ DWT_CTRL_FOLDEVTENA_Msk

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    #define DWT_CTRL_FOLDEVTENA_Msk   (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)
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    DWT CTRL: FOLDEVTENA Mask

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    ◆ DWT_CTRL_LSUEVTENA_Pos

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    #define DWT_CTRL_LSUEVTENA_Pos   20U
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    DWT CTRL: LSUEVTENA Position

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    ◆ DWT_CTRL_LSUEVTENA_Msk

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    #define DWT_CTRL_LSUEVTENA_Msk   (0x1UL << DWT_CTRL_LSUEVTENA_Pos)
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    DWT CTRL: LSUEVTENA Mask

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    ◆ DWT_CTRL_SLEEPEVTENA_Pos

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    #define DWT_CTRL_SLEEPEVTENA_Pos   19U
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    DWT CTRL: SLEEPEVTENA Position

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    ◆ DWT_CTRL_SLEEPEVTENA_Msk

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    #define DWT_CTRL_SLEEPEVTENA_Msk   (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)
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    DWT CTRL: SLEEPEVTENA Mask

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    ◆ DWT_CTRL_EXCEVTENA_Pos

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    #define DWT_CTRL_EXCEVTENA_Pos   18U
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    DWT CTRL: EXCEVTENA Position

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    ◆ DWT_CTRL_EXCEVTENA_Msk

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    #define DWT_CTRL_EXCEVTENA_Msk   (0x1UL << DWT_CTRL_EXCEVTENA_Pos)
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    DWT CTRL: EXCEVTENA Mask

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    ◆ DWT_CTRL_CPIEVTENA_Pos

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    #define DWT_CTRL_CPIEVTENA_Pos   17U
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    DWT CTRL: CPIEVTENA Position

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    ◆ DWT_CTRL_CPIEVTENA_Msk

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    #define DWT_CTRL_CPIEVTENA_Msk   (0x1UL << DWT_CTRL_CPIEVTENA_Pos)
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    DWT CTRL: CPIEVTENA Mask

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    ◆ DWT_CTRL_EXCTRCENA_Pos

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    #define DWT_CTRL_EXCTRCENA_Pos   16U
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    DWT CTRL: EXCTRCENA Position

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    ◆ DWT_CTRL_EXCTRCENA_Msk

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    #define DWT_CTRL_EXCTRCENA_Msk   (0x1UL << DWT_CTRL_EXCTRCENA_Pos)
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    DWT CTRL: EXCTRCENA Mask

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    ◆ DWT_CTRL_PCSAMPLENA_Pos

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    #define DWT_CTRL_PCSAMPLENA_Pos   12U
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    DWT CTRL: PCSAMPLENA Position

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    ◆ DWT_CTRL_PCSAMPLENA_Msk

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    #define DWT_CTRL_PCSAMPLENA_Msk   (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)
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    DWT CTRL: PCSAMPLENA Mask

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    ◆ DWT_CTRL_SYNCTAP_Pos

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    #define DWT_CTRL_SYNCTAP_Pos   10U
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    DWT CTRL: SYNCTAP Position

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    ◆ DWT_CTRL_SYNCTAP_Msk

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    #define DWT_CTRL_SYNCTAP_Msk   (0x3UL << DWT_CTRL_SYNCTAP_Pos)
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    DWT CTRL: SYNCTAP Mask

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    ◆ DWT_CTRL_CYCTAP_Pos

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    #define DWT_CTRL_CYCTAP_Pos   9U
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    DWT CTRL: CYCTAP Position

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    ◆ DWT_CTRL_CYCTAP_Msk

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    #define DWT_CTRL_CYCTAP_Msk   (0x1UL << DWT_CTRL_CYCTAP_Pos)
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    DWT CTRL: CYCTAP Mask

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    ◆ DWT_CTRL_POSTINIT_Pos

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    #define DWT_CTRL_POSTINIT_Pos   5U
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    DWT CTRL: POSTINIT Position

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    ◆ DWT_CTRL_POSTINIT_Msk

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    #define DWT_CTRL_POSTINIT_Msk   (0xFUL << DWT_CTRL_POSTINIT_Pos)
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    DWT CTRL: POSTINIT Mask

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    ◆ DWT_CTRL_POSTPRESET_Pos

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    #define DWT_CTRL_POSTPRESET_Pos   1U
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    DWT CTRL: POSTPRESET Position

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    ◆ DWT_CTRL_POSTPRESET_Msk

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    #define DWT_CTRL_POSTPRESET_Msk   (0xFUL << DWT_CTRL_POSTPRESET_Pos)
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    DWT CTRL: POSTPRESET Mask

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    ◆ DWT_CTRL_CYCCNTENA_Pos

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    #define DWT_CTRL_CYCCNTENA_Pos   0U
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    DWT CTRL: CYCCNTENA Position

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    ◆ DWT_CTRL_CYCCNTENA_Msk

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    #define DWT_CTRL_CYCCNTENA_Msk   (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)
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    DWT CTRL: CYCCNTENA Mask

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    ◆ DWT_CPICNT_CPICNT_Pos

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    #define DWT_CPICNT_CPICNT_Pos   0U
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    DWT CPICNT: CPICNT Position

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    ◆ DWT_CPICNT_CPICNT_Msk

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    #define DWT_CPICNT_CPICNT_Msk   (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)
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    DWT CPICNT: CPICNT Mask

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    ◆ DWT_EXCCNT_EXCCNT_Pos

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    #define DWT_EXCCNT_EXCCNT_Pos   0U
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    DWT EXCCNT: EXCCNT Position

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    ◆ DWT_EXCCNT_EXCCNT_Msk

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    #define DWT_EXCCNT_EXCCNT_Msk   (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)
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    DWT EXCCNT: EXCCNT Mask

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    ◆ DWT_SLEEPCNT_SLEEPCNT_Pos

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    #define DWT_SLEEPCNT_SLEEPCNT_Pos   0U
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    DWT SLEEPCNT: SLEEPCNT Position

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    ◆ DWT_SLEEPCNT_SLEEPCNT_Msk

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    #define DWT_SLEEPCNT_SLEEPCNT_Msk   (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)
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    DWT SLEEPCNT: SLEEPCNT Mask

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    ◆ DWT_LSUCNT_LSUCNT_Pos

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    #define DWT_LSUCNT_LSUCNT_Pos   0U
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    DWT LSUCNT: LSUCNT Position

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    ◆ DWT_LSUCNT_LSUCNT_Msk

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    #define DWT_LSUCNT_LSUCNT_Msk   (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)
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    DWT LSUCNT: LSUCNT Mask

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    ◆ DWT_FOLDCNT_FOLDCNT_Pos

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    #define DWT_FOLDCNT_FOLDCNT_Pos   0U
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    DWT FOLDCNT: FOLDCNT Position

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    ◆ DWT_FOLDCNT_FOLDCNT_Msk

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    #define DWT_FOLDCNT_FOLDCNT_Msk   (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)
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    DWT FOLDCNT: FOLDCNT Mask

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    ◆ DWT_MASK_MASK_Pos

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    #define DWT_MASK_MASK_Pos   0U
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    DWT MASK: MASK Position

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    ◆ DWT_MASK_MASK_Msk

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    #define DWT_MASK_MASK_Msk   (0x1FUL /*<< DWT_MASK_MASK_Pos*/)
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    DWT MASK: MASK Mask

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    ◆ DWT_FUNCTION_MATCHED_Pos

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    #define DWT_FUNCTION_MATCHED_Pos   24U
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    DWT FUNCTION: MATCHED Position

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    ◆ DWT_FUNCTION_MATCHED_Msk

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    #define DWT_FUNCTION_MATCHED_Msk   (0x1UL << DWT_FUNCTION_MATCHED_Pos)
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    DWT FUNCTION: MATCHED Mask

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    ◆ DWT_FUNCTION_DATAVADDR1_Pos

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    #define DWT_FUNCTION_DATAVADDR1_Pos   16U
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    DWT FUNCTION: DATAVADDR1 Position

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    ◆ DWT_FUNCTION_DATAVADDR1_Msk

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    #define DWT_FUNCTION_DATAVADDR1_Msk   (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)
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    DWT FUNCTION: DATAVADDR1 Mask

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    ◆ DWT_FUNCTION_DATAVADDR0_Pos

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    #define DWT_FUNCTION_DATAVADDR0_Pos   12U
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    DWT FUNCTION: DATAVADDR0 Position

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    ◆ DWT_FUNCTION_DATAVADDR0_Msk

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    #define DWT_FUNCTION_DATAVADDR0_Msk   (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)
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    DWT FUNCTION: DATAVADDR0 Mask

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    ◆ DWT_FUNCTION_DATAVSIZE_Pos

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    #define DWT_FUNCTION_DATAVSIZE_Pos   10U
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    DWT FUNCTION: DATAVSIZE Position

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    ◆ DWT_FUNCTION_DATAVSIZE_Msk

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    #define DWT_FUNCTION_DATAVSIZE_Msk   (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)
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    DWT FUNCTION: DATAVSIZE Mask

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    ◆ DWT_FUNCTION_LNK1ENA_Pos

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    #define DWT_FUNCTION_LNK1ENA_Pos   9U
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    DWT FUNCTION: LNK1ENA Position

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    ◆ DWT_FUNCTION_LNK1ENA_Msk

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    #define DWT_FUNCTION_LNK1ENA_Msk   (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)
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    DWT FUNCTION: LNK1ENA Mask

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    ◆ DWT_FUNCTION_DATAVMATCH_Pos

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    #define DWT_FUNCTION_DATAVMATCH_Pos   8U
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    DWT FUNCTION: DATAVMATCH Position

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    ◆ DWT_FUNCTION_DATAVMATCH_Msk

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    #define DWT_FUNCTION_DATAVMATCH_Msk   (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)
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    DWT FUNCTION: DATAVMATCH Mask

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    ◆ DWT_FUNCTION_CYCMATCH_Pos

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    #define DWT_FUNCTION_CYCMATCH_Pos   7U
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    DWT FUNCTION: CYCMATCH Position

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    ◆ DWT_FUNCTION_CYCMATCH_Msk

    - -
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    - - - - -
    #define DWT_FUNCTION_CYCMATCH_Msk   (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)
    -
    -

    DWT FUNCTION: CYCMATCH Mask

    - -
    -
    - -

    ◆ DWT_FUNCTION_EMITRANGE_Pos

    - -
    -
    - - - - -
    #define DWT_FUNCTION_EMITRANGE_Pos   5U
    -
    -

    DWT FUNCTION: EMITRANGE Position

    - -
    -
    - -

    ◆ DWT_FUNCTION_EMITRANGE_Msk

    - -
    -
    - - - - -
    #define DWT_FUNCTION_EMITRANGE_Msk   (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)
    -
    -

    DWT FUNCTION: EMITRANGE Mask

    - -
    -
    - -

    ◆ DWT_FUNCTION_FUNCTION_Pos

    - -
    -
    - - - - -
    #define DWT_FUNCTION_FUNCTION_Pos   0U
    -
    -

    DWT FUNCTION: FUNCTION Position

    - -
    -
    - -

    ◆ DWT_FUNCTION_FUNCTION_Msk

    - -
    -
    - - - - -
    #define DWT_FUNCTION_FUNCTION_Msk   (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)
    -
    -

    DWT FUNCTION: FUNCTION Mask

    - -
    -
    -
    - -
    -Generated by doxygen 1.10.0 -
    - - diff --git a/DOCS/html/group___c_m_s_i_s___d_w_t.map b/DOCS/html/group___c_m_s_i_s___d_w_t.map deleted file mode 100644 index 9055d83..0000000 --- a/DOCS/html/group___c_m_s_i_s___d_w_t.map +++ /dev/null @@ -1,5 +0,0 @@ - - - - - diff --git a/DOCS/html/group___c_m_s_i_s___d_w_t.md5 b/DOCS/html/group___c_m_s_i_s___d_w_t.md5 deleted file mode 100644 index 1b75188..0000000 --- a/DOCS/html/group___c_m_s_i_s___d_w_t.md5 +++ /dev/null @@ -1 +0,0 @@ -cf7b06f25271d5a032ce6b5988a32066 \ No newline at end of file diff --git a/DOCS/html/group___c_m_s_i_s___d_w_t.png b/DOCS/html/group___c_m_s_i_s___d_w_t.png deleted file mode 100644 index 31d17427367c5b4d15484087f5cc6dcd17985523..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 2328 zcmaJ@dpHve7oVtfQ>5wQQo_{B%H%TD6w@LbB{7U%mrBJ7GnYw3uS=1M<$itTzD&$z zoAsJzExca0Mwpe$-nq;rx1n$S`F($U=RD{9&htC}obx>Ad44C}9);Mq`{-@}0I<*c zD*OfjuuVl;8_DmG<^@fTn-q3zq@s^&4hU%bEvG>~c3utx*9eojesevo##UdJ?+U$>HpZ`yacC zxg7j4?KdZwlH3Qh%7^yggu9@taK;mKfhZ@dzBQTo7{(# zng*@b3Fz+V{6|Vu>BK2zT@=61RCGO7^01W}LJ&O2>BZYdsFU|kQeQaftHAPfOI19A zhjkMw+Z3(3f4-%43Hk{z^K*T4T^?h~B>qFND)LQI-8VDTd^5_1O|(Uljp`${>UsU7 zMORkEcMI=hM)U?e8bu6>iwi19{jSMrPssFJ$b9?Hka7oiw&LFKG@<8k`LctuWsaAx z%M*;1LGMKkM{aQ=%@xFHskOEsQPB@Srcm|hWZF!^GFmy=Ivd9=O+XGVHloTMG)#Oy z_y=Azc-cw{%+OWcYOX5gl}wKcyR01?>oY*uT;GgKRfj)$b|sQ$Yu>zeI`lxTg#9%r z;~dEkdKCt$+8@eIfJu}P>$O6P89SYdanCMcJA;h14+pP0gK!uPDn0iNYmD1yE1Is4 z^L^?l>Vy70-GsCwR(;8$)Qv7Z8O%o1kWm5l_~9k;y!Q}g4e3MGA0oZkWBi z{}a5iLX^!Cx zlg`ldXkQYN+S;lLD9&7g5Zb@8%|kYK2jh|(htcg5g=u$ZE`TS5umhpVuYf;D?>3zu z^q3O6kX%ld2R_g0@vSt!u&wp5n2?hI*gnFZRb%m1$A;7T?tCnx*BZBSx3-Qx73Qgg z$UHL%nQ2c8Gs|(`8_f^J-Bvnwr}oHoWsHj+@QiZh0+@e_pT!)A!f#W=f*4rA)Uq0L zcGmxWZEdSJ=-jIr)&E7DUSiTx^#I$dzI2ynxEK*BZU74WxAFFrDIBBzfbHAXPCI^-0fvrgsiE zJpQ)G9F1y`F+YjYW9l_tyh6xgae^evGbMlMAM>JV6P>}NIhif_jh(A%VyIxKTZa=Q zzoCQ}-4qRwBg;B!xD93F7H0U_uZ<*WEV>Fh?~~&5uijio9tGv&kL*0Z0Mpa-w^yMeas=?L`0~M;pS_q#PxzK zEqP%Js3`W-kePr!*=VRJ^a-c!-Uu^{IBaV7Br>s5e)YE`#!rx4E^VsNji)f8t>T!x zws(9Oh+`Mo^>f0_ZPa@rCT9j}jKrjlrIUPBv7UGze>iKLoozK)LvfeDzJ}?B)5DD! zg`lgSCP)UM>^RWY_6<+N8~|9RnaPgJQ@B2Q5>fsfT3SwO4l(b26-siuG#~lVcz^nh zbLv<6%zU^Dxwz%&Yg;SVP~TWA_qpqU91d0|MrtBVg9IiC!fpQ8IPDGWSGjN zL~)Plaf3EuqO|uSXJpM~VDPV*E8+Zto;bLR7}8j3IOwyE#Fuc1UBWfwvP0eHn3pg5 zmk7M0WAAs8w*?A1z0W6k9eKT!W!JMvJcZrV;Zj6v0rPXAH#@+U@qf@pwf#SQ2|U^% zztmlRHos}$=oxI{n}AJ*q#VLZh-_B4eeWL?35^t7htZ*jsx{1+$*1Vh9yUI0&B(RR zlS|z+8t(rXj4_0IKooo;G;FCN%cit~DK#CN`z(YIDDu9M6aFRN70iqP*$s>*-t-O2 zy3MDmz|D%_g@gI2iN`m6(nY#mcKO}@~TX} z5Pu{!DFaD0I@LVgx9BQ%E{iMP+caJ%JU`7{PQ_4#5Jin*$(frM6*6ZkuD|~bH$HNm zcpL)$brou7xUj6?!O9`%dk%%tKoR}vdhB0Twn@u$t&34TqPwl>zPOAAjBfJzUPYRD zg+}CfmARDkE0k4~wo&~tZuOmqMeby5qEx`z#k!5+OB%A3FAM_Hw^q-Fq`Bx9mw`q6 zntr+s_(C^Z{;?(|AmVpChOyVx3HRMu zH#0lj+yuN@uyenxCvL$lka`uud}pCv*#s+x`W}X;sViG?|dmE rlrmCibOWQoq-sm4=>E4IiKPPkf%Cb44-tscR|jBig@RXG+>ZVaY@4E} diff --git a/DOCS/html/group___c_m_s_i_s___device.html b/DOCS/html/group___c_m_s_i_s___device.html deleted file mode 100644 index 139279c..0000000 --- a/DOCS/html/group___c_m_s_i_s___device.html +++ /dev/null @@ -1,7582 +0,0 @@ - - - - - - - -STM MATLAB Simulator: CMSIS_Device - - - - - - - - - - - -
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    -Topics

     Stm32f407xx
     
    - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

    -Variables

    uint32_t SR
     
    __IO uint32_t CR1
     
    __IO uint32_t CR2
     
    __IO uint32_t SMPR1
     
    __IO uint32_t SMPR2
     
    __IO uint32_t JOFR1
     
    __IO uint32_t JOFR2
     
    __IO uint32_t JOFR3
     
    __IO uint32_t JOFR4
     
    __IO uint32_t HTR
     
    __IO uint32_t LTR
     
    __IO uint32_t SQR1
     
    __IO uint32_t SQR2
     
    __IO uint32_t SQR3
     
    __IO uint32_t JSQR
     
    __IO uint32_t JDR1
     
    __IO uint32_t JDR2
     
    __IO uint32_t JDR3
     
    __IO uint32_t JDR4
     
    __IO uint32_t DR
     
    __IO uint32_t CSR
     
    __IO uint32_t CCR
     
    __IO uint32_t CDR
     
    __IO uint32_t TIR
     
    __IO uint32_t TDTR
     
    __IO uint32_t TDLR
     
    __IO uint32_t TDHR
     
    __IO uint32_t RIR
     
    __IO uint32_t RDTR
     
    __IO uint32_t RDLR
     
    __IO uint32_t RDHR
     
    __IO uint32_t FR1
     
    __IO uint32_t FR2
     
    __IO uint32_t MCR
     
    __IO uint32_t MSR
     
    __IO uint32_t TSR
     
    __IO uint32_t RF0R
     
    __IO uint32_t RF1R
     
    __IO uint32_t IER
     
    __IO uint32_t ESR
     
    __IO uint32_t BTR
     
    uint32_t RESERVED0 [88]
     
    CAN_TxMailBox_TypeDef sTxMailBox [3]
     
    CAN_FIFOMailBox_TypeDef sFIFOMailBox [2]
     
    uint32_t RESERVED1 [12]
     
    __IO uint32_t FMR
     
    __IO uint32_t FM1R
     
    uint32_t RESERVED2
     
    __IO uint32_t FS1R
     
    uint32_t RESERVED3
     
    __IO uint32_t FFA1R
     
    uint32_t RESERVED4
     
    __IO uint32_t FA1R
     
    uint32_t RESERVED5 [8]
     
    CAN_FilterRegister_TypeDef sFilterRegister [28]
     
    __IO uint32_t DR
     
    __IO uint8_t IDR
     
    uint8_t RESERVED0
     
    uint16_t RESERVED1
     
    __IO uint32_t CR
     
    __IO uint32_t CR
     
    __IO uint32_t SWTRIGR
     
    __IO uint32_t DHR12R1
     
    __IO uint32_t DHR12L1
     
    __IO uint32_t DHR8R1
     
    __IO uint32_t DHR12R2
     
    __IO uint32_t DHR12L2
     
    __IO uint32_t DHR8R2
     
    __IO uint32_t DHR12RD
     
    __IO uint32_t DHR12LD
     
    __IO uint32_t DHR8RD
     
    __IO uint32_t DOR1
     
    __IO uint32_t DOR2
     
    __IO uint32_t SR
     
    __IO uint32_t IDCODE
     
    __IO uint32_t CR
     
    __IO uint32_t APB1FZ
     
    __IO uint32_t APB2FZ
     
    __IO uint32_t CR
     
    __IO uint32_t SR
     
    __IO uint32_t RISR
     
    __IO uint32_t IER
     
    __IO uint32_t MISR
     
    __IO uint32_t ICR
     
    __IO uint32_t ESCR
     
    __IO uint32_t ESUR
     
    __IO uint32_t CWSTRTR
     
    __IO uint32_t CWSIZER
     
    __IO uint32_t DR
     
    __IO uint32_t CR
     
    __IO uint32_t NDTR
     
    __IO uint32_t PAR
     
    __IO uint32_t M0AR
     
    __IO uint32_t M1AR
     
    __IO uint32_t FCR
     
    __IO uint32_t LISR
     
    __IO uint32_t HISR
     
    __IO uint32_t LIFCR
     
    __IO uint32_t HIFCR
     
    __IO uint32_t MACCR
     
    __IO uint32_t MACFFR
     
    __IO uint32_t MACHTHR
     
    __IO uint32_t MACHTLR
     
    __IO uint32_t MACMIIAR
     
    __IO uint32_t MACMIIDR
     
    __IO uint32_t MACFCR
     
    __IO uint32_t MACVLANTR
     
    uint32_t RESERVED0 [2]
     
    __IO uint32_t MACRWUFFR
     
    __IO uint32_t MACPMTCSR
     
    uint32_t RESERVED1
     
    __IO uint32_t MACDBGR
     
    __IO uint32_t MACSR
     
    __IO uint32_t MACIMR
     
    __IO uint32_t MACA0HR
     
    __IO uint32_t MACA0LR
     
    __IO uint32_t MACA1HR
     
    __IO uint32_t MACA1LR
     
    __IO uint32_t MACA2HR
     
    __IO uint32_t MACA2LR
     
    __IO uint32_t MACA3HR
     
    __IO uint32_t MACA3LR
     
    uint32_t RESERVED2 [40]
     
    __IO uint32_t MMCCR
     
    __IO uint32_t MMCRIR
     
    __IO uint32_t MMCTIR
     
    __IO uint32_t MMCRIMR
     
    __IO uint32_t MMCTIMR
     
    uint32_t RESERVED3 [14]
     
    __IO uint32_t MMCTGFSCCR
     
    __IO uint32_t MMCTGFMSCCR
     
    uint32_t RESERVED4 [5]
     
    __IO uint32_t MMCTGFCR
     
    uint32_t RESERVED5 [10]
     
    __IO uint32_t MMCRFCECR
     
    __IO uint32_t MMCRFAECR
     
    uint32_t RESERVED6 [10]
     
    __IO uint32_t MMCRGUFCR
     
    uint32_t RESERVED7 [334]
     
    __IO uint32_t PTPTSCR
     
    __IO uint32_t PTPSSIR
     
    __IO uint32_t PTPTSHR
     
    __IO uint32_t PTPTSLR
     
    __IO uint32_t PTPTSHUR
     
    __IO uint32_t PTPTSLUR
     
    __IO uint32_t PTPTSAR
     
    __IO uint32_t PTPTTHR
     
    __IO uint32_t PTPTTLR
     
    __IO uint32_t RESERVED8
     
    __IO uint32_t PTPTSSR
     
    uint32_t RESERVED9 [565]
     
    __IO uint32_t DMABMR
     
    __IO uint32_t DMATPDR
     
    __IO uint32_t DMARPDR
     
    __IO uint32_t DMARDLAR
     
    __IO uint32_t DMATDLAR
     
    __IO uint32_t DMASR
     
    __IO uint32_t DMAOMR
     
    __IO uint32_t DMAIER
     
    __IO uint32_t DMAMFBOCR
     
    __IO uint32_t DMARSWTR
     
    uint32_t RESERVED10 [8]
     
    __IO uint32_t DMACHTDR
     
    __IO uint32_t DMACHRDR
     
    __IO uint32_t DMACHTBAR
     
    __IO uint32_t DMACHRBAR
     
    __IO uint32_t IMR
     
    __IO uint32_t EMR
     
    __IO uint32_t RTSR
     
    __IO uint32_t FTSR
     
    __IO uint32_t SWIER
     
    __IO uint32_t PR
     
    __IO uint32_t ACR
     
    __IO uint32_t KEYR
     
    __IO uint32_t OPTKEYR
     
    __IO uint32_t SR
     
    __IO uint32_t CR
     
    __IO uint32_t OPTCR
     
    __IO uint32_t OPTCR1
     
    __IO uint32_t BTCR [8]
     
    __IO uint32_t BWTR [7]
     
    __IO uint32_t PCR2
     
    __IO uint32_t SR2
     
    __IO uint32_t PMEM2
     
    __IO uint32_t PATT2
     
    uint32_t RESERVED0
     
    __IO uint32_t ECCR2
     
    uint32_t RESERVED1
     
    uint32_t RESERVED2
     
    __IO uint32_t PCR3
     
    __IO uint32_t SR3
     
    __IO uint32_t PMEM3
     
    __IO uint32_t PATT3
     
    uint32_t RESERVED3
     
    __IO uint32_t ECCR3
     
    __IO uint32_t PCR4
     
    __IO uint32_t SR4
     
    __IO uint32_t PMEM4
     
    __IO uint32_t PATT4
     
    __IO uint32_t PIO4
     
    __IO uint32_t MODER
     
    __IO uint32_t OTYPER
     
    __IO uint32_t OSPEEDR
     
    __IO uint32_t PUPDR
     
    __IO uint32_t IDR
     
    __IO uint32_t ODR
     
    __IO uint32_t BSRR
     
    __IO uint32_t LCKR
     
    __IO uint32_t AFR [2]
     
    __IO uint32_t MEMRMP
     
    __IO uint32_t PMC
     
    __IO uint32_t EXTICR [4]
     
    uint32_t RESERVED [2]
     
    __IO uint32_t CMPCR
     
    __IO uint32_t CR1
     
    __IO uint32_t CR2
     
    __IO uint32_t OAR1
     
    __IO uint32_t OAR2
     
    __IO uint32_t DR
     
    __IO uint32_t SR1
     
    __IO uint32_t SR2
     
    __IO uint32_t CCR
     
    __IO uint32_t TRISE
     
    __IO uint32_t KR
     
    __IO uint32_t PR
     
    __IO uint32_t RLR
     
    __IO uint32_t SR
     
    __IO uint32_t CR
     
    __IO uint32_t CSR
     
    __IO uint32_t CR
     
    __IO uint32_t PLLCFGR
     
    __IO uint32_t CFGR
     
    __IO uint32_t CIR
     
    __IO uint32_t AHB1RSTR
     
    __IO uint32_t AHB2RSTR
     
    __IO uint32_t AHB3RSTR
     
    uint32_t RESERVED0
     
    __IO uint32_t APB1RSTR
     
    __IO uint32_t APB2RSTR
     
    uint32_t RESERVED1 [2]
     
    __IO uint32_t AHB1ENR
     
    __IO uint32_t AHB2ENR
     
    __IO uint32_t AHB3ENR
     
    uint32_t RESERVED2
     
    __IO uint32_t APB1ENR
     
    __IO uint32_t APB2ENR
     
    uint32_t RESERVED3 [2]
     
    __IO uint32_t AHB1LPENR
     
    __IO uint32_t AHB2LPENR
     
    __IO uint32_t AHB3LPENR
     
    uint32_t RESERVED4
     
    __IO uint32_t APB1LPENR
     
    __IO uint32_t APB2LPENR
     
    uint32_t RESERVED5 [2]
     
    __IO uint32_t BDCR
     
    __IO uint32_t CSR
     
    uint32_t RESERVED6 [2]
     
    __IO uint32_t SSCGR
     
    __IO uint32_t PLLI2SCFGR
     
    __IO uint32_t TR
     
    __IO uint32_t DR
     
    __IO uint32_t CR
     
    __IO uint32_t ISR
     
    __IO uint32_t PRER
     
    __IO uint32_t WUTR
     
    __IO uint32_t CALIBR
     
    __IO uint32_t ALRMAR
     
    __IO uint32_t ALRMBR
     
    __IO uint32_t WPR
     
    __IO uint32_t SSR
     
    __IO uint32_t SHIFTR
     
    __IO uint32_t TSTR
     
    __IO uint32_t TSDR
     
    __IO uint32_t TSSSR
     
    __IO uint32_t CALR
     
    __IO uint32_t TAFCR
     
    __IO uint32_t ALRMASSR
     
    __IO uint32_t ALRMBSSR
     
    uint32_t RESERVED7
     
    __IO uint32_t BKP0R
     
    __IO uint32_t BKP1R
     
    __IO uint32_t BKP2R
     
    __IO uint32_t BKP3R
     
    __IO uint32_t BKP4R
     
    __IO uint32_t BKP5R
     
    __IO uint32_t BKP6R
     
    __IO uint32_t BKP7R
     
    __IO uint32_t BKP8R
     
    __IO uint32_t BKP9R
     
    __IO uint32_t BKP10R
     
    __IO uint32_t BKP11R
     
    __IO uint32_t BKP12R
     
    __IO uint32_t BKP13R
     
    __IO uint32_t BKP14R
     
    __IO uint32_t BKP15R
     
    __IO uint32_t BKP16R
     
    __IO uint32_t BKP17R
     
    __IO uint32_t BKP18R
     
    __IO uint32_t BKP19R
     
    __IO uint32_t POWER
     
    __IO uint32_t CLKCR
     
    __IO uint32_t ARG
     
    __IO uint32_t CMD
     
    __IO const uint32_t RESPCMD
     
    __IO const uint32_t RESP1
     
    __IO const uint32_t RESP2
     
    __IO const uint32_t RESP3
     
    __IO const uint32_t RESP4
     
    __IO uint32_t DTIMER
     
    __IO uint32_t DLEN
     
    __IO uint32_t DCTRL
     
    __IO const uint32_t DCOUNT
     
    __IO const uint32_t STA
     
    __IO uint32_t ICR
     
    __IO uint32_t MASK
     
    uint32_t RESERVED0 [2]
     
    __IO const uint32_t FIFOCNT
     
    uint32_t RESERVED1 [13]
     
    __IO uint32_t FIFO
     
    __IO uint32_t CR1
     
    __IO uint32_t CR2
     
    __IO uint32_t SR
     
    __IO uint32_t DR
     
    __IO uint32_t CRCPR
     
    __IO uint32_t RXCRCR
     
    __IO uint32_t TXCRCR
     
    __IO uint32_t I2SCFGR
     
    __IO uint32_t I2SPR
     
    __IO uint32_t CR1
     
    __IO uint32_t CR2
     
    __IO uint32_t SMCR
     
    __IO uint32_t DIER
     
    __IO uint32_t SR
     
    __IO uint32_t EGR
     
    __IO uint32_t CCMR1
     
    __IO uint32_t CCMR2
     
    __IO uint32_t CCER
     
    __IO uint32_t CNT
     
    __IO uint32_t PSC
     
    __IO uint32_t ARR
     
    __IO uint32_t RCR
     
    __IO uint32_t CCR1
     
    __IO uint32_t CCR2
     
    __IO uint32_t CCR3
     
    __IO uint32_t CCR4
     
    __IO uint32_t BDTR
     
    __IO uint32_t DCR
     
    __IO uint32_t DMAR
     
    __IO uint32_t OR
     
    __IO uint32_t SR
     
    __IO uint32_t DR
     
    __IO uint32_t BRR
     
    __IO uint32_t CR1
     
    __IO uint32_t CR2
     
    __IO uint32_t CR3
     
    __IO uint32_t GTPR
     
    __IO uint32_t CR
     
    __IO uint32_t CFR
     
    __IO uint32_t SR
     
    __IO uint32_t CR
     
    __IO uint32_t SR
     
    __IO uint32_t DR
     
    __IO uint32_t GOTGCTL
     
    __IO uint32_t GOTGINT
     
    __IO uint32_t GAHBCFG
     
    __IO uint32_t GUSBCFG
     
    __IO uint32_t GRSTCTL
     
    __IO uint32_t GINTSTS
     
    __IO uint32_t GINTMSK
     
    __IO uint32_t GRXSTSR
     
    __IO uint32_t GRXSTSP
     
    __IO uint32_t GRXFSIZ
     
    __IO uint32_t DIEPTXF0_HNPTXFSIZ
     
    __IO uint32_t HNPTXSTS
     
    uint32_t Reserved30 [2]
     
    __IO uint32_t GCCFG
     
    __IO uint32_t CID
     
    uint32_t Reserved40 [48]
     
    __IO uint32_t HPTXFSIZ
     
    __IO uint32_t DIEPTXF [0x0F]
     
    __IO uint32_t DCFG
     
    __IO uint32_t DCTL
     
    __IO uint32_t DSTS
     
    uint32_t Reserved0C
     
    __IO uint32_t DIEPMSK
     
    __IO uint32_t DOEPMSK
     
    __IO uint32_t DAINT
     
    __IO uint32_t DAINTMSK
     
    uint32_t Reserved20
     
    uint32_t Reserved9
     
    __IO uint32_t DVBUSDIS
     
    __IO uint32_t DVBUSPULSE
     
    __IO uint32_t DTHRCTL
     
    __IO uint32_t DIEPEMPMSK
     
    __IO uint32_t DEACHINT
     
    __IO uint32_t DEACHMSK
     
    uint32_t Reserved40
     
    __IO uint32_t DINEP1MSK
     
    uint32_t Reserved44 [15]
     
    __IO uint32_t DOUTEP1MSK
     
    __IO uint32_t DIEPCTL
     
    uint32_t Reserved04
     
    __IO uint32_t DIEPINT
     
    uint32_t Reserved0C
     
    __IO uint32_t DIEPTSIZ
     
    __IO uint32_t DIEPDMA
     
    __IO uint32_t DTXFSTS
     
    uint32_t Reserved18
     
    __IO uint32_t DOEPCTL
     
    uint32_t Reserved04
     
    __IO uint32_t DOEPINT
     
    uint32_t Reserved0C
     
    __IO uint32_t DOEPTSIZ
     
    __IO uint32_t DOEPDMA
     
    uint32_t Reserved18 [2]
     
    __IO uint32_t HCFG
     
    __IO uint32_t HFIR
     
    __IO uint32_t HFNUM
     
    uint32_t Reserved40C
     
    __IO uint32_t HPTXSTS
     
    __IO uint32_t HAINT
     
    __IO uint32_t HAINTMSK
     
    __IO uint32_t HCCHAR
     
    __IO uint32_t HCSPLT
     
    __IO uint32_t HCINT
     
    __IO uint32_t HCINTMSK
     
    __IO uint32_t HCTSIZ
     
    __IO uint32_t HCDMA
     
    uint32_t Reserved [2]
     
    uint8_t FLASH_BASE [FLASH_SIZE]
     
    uint8_t CCMDATARAM_BASE [CCMDATARAM_SIZE]
     
    uint8_t FLASH_OTP_BASE [FLASH_OTP_SIZE]
     
    uint8_t SRAM1_BASE [SRAM1_SIZE]
     
    uint8_t SRAM2_BASE [SRAM2_SIZE]
     
    uint8_t SRAM1_BB_BASE [SRAM1_SIZE]
     
    uint8_t SRAM2_BB_BASE [SRAM2_SIZE]
     
    uint8_t PERIPH_BASE [PERIPH_SIZE]
     
    uint8_t BKPSRAM_BASE [BKPSRAM_SIZE]
     
    uint8_t PERIPH_BB_BASE [PERIPH_BB_SIZE]
     
    uint8_t BKPSRAM_BB_BASE [BKPSRAM_SIZE]
     
    uint8_t FSMC_R_BASE [FSMC_R_SIZE]
     
    -

    Detailed Description

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    Variable Documentation

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    ◆ SR [1/10]

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    uint32_t SR
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    ADC status register, Address offset: 0x00

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    ◆ CR1 [1/5]

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    __IO uint32_t CR1
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    ADC control register 1, Address offset: 0x04

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    ◆ CR2 [1/5]

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    __IO uint32_t CR2
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    ADC control register 2, Address offset: 0x08

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    ◆ SMPR1

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    __IO uint32_t SMPR1
    -
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    ADC sample time register 1, Address offset: 0x0C

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    ◆ SMPR2

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    __IO uint32_t SMPR2
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    ADC sample time register 2, Address offset: 0x10

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    ◆ JOFR1

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    __IO uint32_t JOFR1
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    ADC injected channel data offset register 1, Address offset: 0x14

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    ◆ JOFR2

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    __IO uint32_t JOFR2
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    ADC injected channel data offset register 2, Address offset: 0x18

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    ◆ JOFR3

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    __IO uint32_t JOFR3
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    ADC injected channel data offset register 3, Address offset: 0x1C

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    ◆ JOFR4

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    __IO uint32_t JOFR4
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    ADC injected channel data offset register 4, Address offset: 0x20

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    ◆ HTR

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    __IO uint32_t HTR
    -
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    ADC watchdog higher threshold register, Address offset: 0x24

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    ◆ LTR

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    __IO uint32_t LTR
    -
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    ADC watchdog lower threshold register, Address offset: 0x28

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    ◆ SQR1

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    __IO uint32_t SQR1
    -
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    ADC regular sequence register 1, Address offset: 0x2C

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    ◆ SQR2

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    __IO uint32_t SQR2
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    ADC regular sequence register 2, Address offset: 0x30

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    ◆ SQR3

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    __IO uint32_t SQR3
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    ADC regular sequence register 3, Address offset: 0x34

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    ◆ JSQR

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    __IO uint32_t JSQR
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    ADC injected sequence register, Address offset: 0x38

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    ◆ JDR1

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    __IO uint32_t JDR1
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    ADC injected data register 1, Address offset: 0x3C

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    ◆ JDR2

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    __IO uint32_t JDR2
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    ADC injected data register 2, Address offset: 0x40

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    ◆ JDR3

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    __IO uint32_t JDR3
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    ADC injected data register 3, Address offset: 0x44

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    ◆ JDR4

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    __IO uint32_t JDR4
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    ADC injected data register 4, Address offset: 0x48

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    ◆ DR [1/8]

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    __IO uint32_t DR
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    ADC regular data register, Address offset: 0x4C

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    ◆ CSR [1/3]

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    __IO uint32_t CSR
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    ADC Common status register, Address offset: ADC1 base address + 0x300

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    ◆ CCR [1/2]

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    __IO uint32_t CCR
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    ADC common control register, Address offset: ADC1 base address + 0x304

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    ◆ CDR

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    __IO uint32_t CDR
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    ADC common regular data register for dual AND triple modes, Address offset: ADC1 base address + 0x308

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    ◆ TIR

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    __IO uint32_t TIR
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    CAN TX mailbox identifier register

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    ◆ TDTR

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    __IO uint32_t TDTR
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    CAN mailbox data length control and time stamp register

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    ◆ TDLR

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    __IO uint32_t TDLR
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    CAN mailbox data low register

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    ◆ TDHR

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    __IO uint32_t TDHR
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    CAN mailbox data high register

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    ◆ RIR

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    __IO uint32_t RIR
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    CAN receive FIFO mailbox identifier register

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    ◆ RDTR

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    __IO uint32_t RDTR
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    CAN receive FIFO mailbox data length control and time stamp register

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    ◆ RDLR

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    __IO uint32_t RDLR
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    CAN receive FIFO mailbox data low register

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    ◆ RDHR

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    __IO uint32_t RDHR
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    CAN receive FIFO mailbox data high register

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    ◆ FR1

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    __IO uint32_t FR1
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    CAN Filter bank register 1

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    ◆ FR2

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    __IO uint32_t FR2
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    CAN Filter bank register 1

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    ◆ MCR

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    __IO uint32_t MCR
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    CAN master control register, Address offset: 0x00
    -

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    ◆ MSR

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    __IO uint32_t MSR
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    CAN master status register, Address offset: 0x04
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    ◆ TSR

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    __IO uint32_t TSR
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    CAN transmit status register, Address offset: 0x08
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    ◆ RF0R

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    __IO uint32_t RF0R
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    CAN receive FIFO 0 register, Address offset: 0x0C
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    ◆ RF1R

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    __IO uint32_t RF1R
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    CAN receive FIFO 1 register, Address offset: 0x10
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    ◆ IER [1/2]

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    __IO uint32_t IER
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    CAN interrupt enable register, Address offset: 0x14
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    ◆ ESR

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    __IO uint32_t ESR
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    CAN error status register, Address offset: 0x18
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    ◆ BTR

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    __IO uint32_t BTR
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    CAN bit timing register, Address offset: 0x1C
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    ◆ RESERVED0 [1/6]

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    uint32_t RESERVED0[88]
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    Reserved, 0x020 - 0x17F
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    ◆ sTxMailBox

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    CAN_TxMailBox_TypeDef sTxMailBox[3]
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    CAN Tx MailBox, Address offset: 0x180 - 0x1AC

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    ◆ sFIFOMailBox

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    CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]
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    CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC

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    ◆ RESERVED1 [1/6]

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    uint32_t RESERVED1[12]
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    Reserved, 0x1D0 - 0x1FF
    -

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    ◆ FMR

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    __IO uint32_t FMR
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    CAN filter master register, Address offset: 0x200
    -

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    ◆ FM1R

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    __IO uint32_t FM1R
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    CAN filter mode register, Address offset: 0x204
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    ◆ RESERVED2 [1/4]

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    uint32_t RESERVED2
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    Reserved, 0x208
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    ◆ FS1R

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    __IO uint32_t FS1R
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    CAN filter scale register, Address offset: 0x20C
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    ◆ RESERVED3 [1/4]

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    uint32_t RESERVED3
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    Reserved, 0x210
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    ◆ FFA1R

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    __IO uint32_t FFA1R
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    CAN filter FIFO assignment register, Address offset: 0x214
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    ◆ RESERVED4 [1/3]

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    uint32_t RESERVED4
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    Reserved, 0x218
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    ◆ FA1R

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    __IO uint32_t FA1R
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    CAN filter activation register, Address offset: 0x21C
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    ◆ RESERVED5 [1/3]

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    uint32_t RESERVED5[8]
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    Reserved, 0x220-0x23F
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    ◆ sFilterRegister

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    CAN_FilterRegister_TypeDef sFilterRegister[28]
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    CAN Filter Register, Address offset: 0x240-0x31C
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    ◆ DR [2/8]

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    __IO uint32_t DR
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    CRC Data register, Address offset: 0x00

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    ◆ IDR [1/2]

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    __IO uint8_t IDR
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    CRC Independent data register, Address offset: 0x04

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    ◆ RESERVED0 [2/6]

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    uint8_t RESERVED0
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    Reserved, 0x05
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    ◆ RESERVED1 [2/6]

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    uint16_t RESERVED1
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    Reserved, 0x06
    -

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    ◆ CR [1/11]

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    __IO uint32_t CR
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    CRC Control register, Address offset: 0x08

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    ◆ CR [2/11]

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    __IO uint32_t CR
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    DAC control register, Address offset: 0x00

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    ◆ SWTRIGR

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    __IO uint32_t SWTRIGR
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    DAC software trigger register, Address offset: 0x04

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    ◆ DHR12R1

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    __IO uint32_t DHR12R1
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    DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08

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    ◆ DHR12L1

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    __IO uint32_t DHR12L1
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    DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C

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    ◆ DHR8R1

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    __IO uint32_t DHR8R1
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    DAC channel1 8-bit right aligned data holding register, Address offset: 0x10

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    ◆ DHR12R2

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    __IO uint32_t DHR12R2
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    DAC channel2 12-bit right aligned data holding register, Address offset: 0x14

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    ◆ DHR12L2

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    __IO uint32_t DHR12L2
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    DAC channel2 12-bit left aligned data holding register, Address offset: 0x18

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    ◆ DHR8R2

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    __IO uint32_t DHR8R2
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    DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C

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    ◆ DHR12RD

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    __IO uint32_t DHR12RD
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    Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20

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    ◆ DHR12LD

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    __IO uint32_t DHR12LD
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    DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24

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    ◆ DHR8RD

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    __IO uint32_t DHR8RD
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    DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28

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    ◆ DOR1

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    __IO uint32_t DOR1
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    DAC channel1 data output register, Address offset: 0x2C

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    ◆ DOR2

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    __IO uint32_t DOR2
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    DAC channel2 data output register, Address offset: 0x30

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    ◆ SR [2/10]

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    __IO uint32_t SR
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    DAC status register, Address offset: 0x34

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    ◆ IDCODE

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    __IO uint32_t IDCODE
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    MCU device ID code, Address offset: 0x00

    - -
    -
    - -

    ◆ CR [3/11]

    - -
    -
    - - - - -
    __IO uint32_t CR
    -
    -

    Debug MCU configuration register, Address offset: 0x04

    - -
    -
    - -

    ◆ APB1FZ

    - -
    -
    - - - - -
    __IO uint32_t APB1FZ
    -
    -

    Debug MCU APB1 freeze register, Address offset: 0x08

    - -
    -
    - -

    ◆ APB2FZ

    - -
    -
    - - - - -
    __IO uint32_t APB2FZ
    -
    -

    Debug MCU APB2 freeze register, Address offset: 0x0C

    - -
    -
    - -

    ◆ CR [4/11]

    - -
    -
    - - - - -
    __IO uint32_t CR
    -
    -

    DCMI control register 1, Address offset: 0x00

    - -
    -
    - -

    ◆ SR [3/10]

    - -
    -
    - - - - -
    __IO uint32_t SR
    -
    -

    DCMI status register, Address offset: 0x04

    - -
    -
    - -

    ◆ RISR

    - -
    -
    - - - - -
    __IO uint32_t RISR
    -
    -

    DCMI raw interrupt status register, Address offset: 0x08

    - -
    -
    - -

    ◆ IER [2/2]

    - -
    -
    - - - - -
    __IO uint32_t IER
    -
    -

    DCMI interrupt enable register, Address offset: 0x0C

    - -
    -
    - -

    ◆ MISR

    - -
    -
    - - - - -
    __IO uint32_t MISR
    -
    -

    DCMI masked interrupt status register, Address offset: 0x10

    - -
    -
    - -

    ◆ ICR [1/2]

    - -
    -
    - - - - -
    __IO uint32_t ICR
    -
    -

    DCMI interrupt clear register, Address offset: 0x14

    - -
    -
    - -

    ◆ ESCR

    - -
    -
    - - - - -
    __IO uint32_t ESCR
    -
    -

    DCMI embedded synchronization code register, Address offset: 0x18

    - -
    -
    - -

    ◆ ESUR

    - -
    -
    - - - - -
    __IO uint32_t ESUR
    -
    -

    DCMI embedded synchronization unmask register, Address offset: 0x1C

    - -
    -
    - -

    ◆ CWSTRTR

    - -
    -
    - - - - -
    __IO uint32_t CWSTRTR
    -
    -

    DCMI crop window start, Address offset: 0x20

    - -
    -
    - -

    ◆ CWSIZER

    - -
    -
    - - - - -
    __IO uint32_t CWSIZER
    -
    -

    DCMI crop window size, Address offset: 0x24

    - -
    -
    - -

    ◆ DR [3/8]

    - -
    -
    - - - - -
    __IO uint32_t DR
    -
    -

    DCMI data register, Address offset: 0x28

    - -
    -
    - -

    ◆ CR [5/11]

    - -
    -
    - - - - -
    __IO uint32_t CR
    -
    -

    DMA stream x configuration register
    -

    - -
    -
    - -

    ◆ NDTR

    - -
    -
    - - - - -
    __IO uint32_t NDTR
    -
    -

    DMA stream x number of data register
    -

    - -
    -
    - -

    ◆ PAR

    - -
    -
    - - - - -
    __IO uint32_t PAR
    -
    -

    DMA stream x peripheral address register

    - -
    -
    - -

    ◆ M0AR

    - -
    -
    - - - - -
    __IO uint32_t M0AR
    -
    -

    DMA stream x memory 0 address register
    -

    - -
    -
    - -

    ◆ M1AR

    - -
    -
    - - - - -
    __IO uint32_t M1AR
    -
    -

    DMA stream x memory 1 address register
    -

    - -
    -
    - -

    ◆ FCR

    - -
    -
    - - - - -
    __IO uint32_t FCR
    -
    -

    DMA stream x FIFO control register
    -

    - -
    -
    - -

    ◆ LISR

    - -
    -
    - - - - -
    __IO uint32_t LISR
    -
    -

    DMA low interrupt status register, Address offset: 0x00

    - -
    -
    - -

    ◆ HISR

    - -
    -
    - - - - -
    __IO uint32_t HISR
    -
    -

    DMA high interrupt status register, Address offset: 0x04

    - -
    -
    - -

    ◆ LIFCR

    - -
    -
    - - - - -
    __IO uint32_t LIFCR
    -
    -

    DMA low interrupt flag clear register, Address offset: 0x08

    - -
    -
    - -

    ◆ HIFCR

    - -
    -
    - - - - -
    __IO uint32_t HIFCR
    -
    -

    DMA high interrupt flag clear register, Address offset: 0x0C

    - -
    -
    - -

    ◆ MACCR

    - -
    -
    - - - - -
    __IO uint32_t MACCR
    -
    - -
    -
    - -

    ◆ MACFFR

    - -
    -
    - - - - -
    __IO uint32_t MACFFR
    -
    - -
    -
    - -

    ◆ MACHTHR

    - -
    -
    - - - - -
    __IO uint32_t MACHTHR
    -
    - -
    -
    - -

    ◆ MACHTLR

    - -
    -
    - - - - -
    __IO uint32_t MACHTLR
    -
    - -
    -
    - -

    ◆ MACMIIAR

    - -
    -
    - - - - -
    __IO uint32_t MACMIIAR
    -
    - -
    -
    - -

    ◆ MACMIIDR

    - -
    -
    - - - - -
    __IO uint32_t MACMIIDR
    -
    - -
    -
    - -

    ◆ MACFCR

    - -
    -
    - - - - -
    __IO uint32_t MACFCR
    -
    - -
    -
    - -

    ◆ MACVLANTR

    - -
    -
    - - - - -
    __IO uint32_t MACVLANTR
    -
    - -
    -
    - -

    ◆ RESERVED0 [3/6]

    - -
    -
    - - - - -
    uint32_t RESERVED0[2]
    -
    - -
    -
    - -

    ◆ MACRWUFFR

    - -
    -
    - - - - -
    __IO uint32_t MACRWUFFR
    -
    - -
    -
    - -

    ◆ MACPMTCSR

    - -
    -
    - - - - -
    __IO uint32_t MACPMTCSR
    -
    - -
    -
    - -

    ◆ RESERVED1 [3/6]

    - -
    -
    - - - - -
    uint32_t RESERVED1
    -
    - -
    -
    - -

    ◆ MACDBGR

    - -
    -
    - - - - -
    __IO uint32_t MACDBGR
    -
    - -
    -
    - -

    ◆ MACSR

    - -
    -
    - - - - -
    __IO uint32_t MACSR
    -
    - -
    -
    - -

    ◆ MACIMR

    - -
    -
    - - - - -
    __IO uint32_t MACIMR
    -
    - -
    -
    - -

    ◆ MACA0HR

    - -
    -
    - - - - -
    __IO uint32_t MACA0HR
    -
    - -
    -
    - -

    ◆ MACA0LR

    - -
    -
    - - - - -
    __IO uint32_t MACA0LR
    -
    - -
    -
    - -

    ◆ MACA1HR

    - -
    -
    - - - - -
    __IO uint32_t MACA1HR
    -
    - -
    -
    - -

    ◆ MACA1LR

    - -
    -
    - - - - -
    __IO uint32_t MACA1LR
    -
    - -
    -
    - -

    ◆ MACA2HR

    - -
    -
    - - - - -
    __IO uint32_t MACA2HR
    -
    - -
    -
    - -

    ◆ MACA2LR

    - -
    -
    - - - - -
    __IO uint32_t MACA2LR
    -
    - -
    -
    - -

    ◆ MACA3HR

    - -
    -
    - - - - -
    __IO uint32_t MACA3HR
    -
    - -
    -
    - -

    ◆ MACA3LR

    - -
    -
    - - - - -
    __IO uint32_t MACA3LR
    -
    - -
    -
    - -

    ◆ RESERVED2 [2/4]

    - -
    -
    - - - - -
    uint32_t RESERVED2[40]
    -
    - -
    -
    - -

    ◆ MMCCR

    - -
    -
    - - - - -
    __IO uint32_t MMCCR
    -
    - -
    -
    - -

    ◆ MMCRIR

    - -
    -
    - - - - -
    __IO uint32_t MMCRIR
    -
    - -
    -
    - -

    ◆ MMCTIR

    - -
    -
    - - - - -
    __IO uint32_t MMCTIR
    -
    - -
    -
    - -

    ◆ MMCRIMR

    - -
    -
    - - - - -
    __IO uint32_t MMCRIMR
    -
    - -
    -
    - -

    ◆ MMCTIMR

    - -
    -
    - - - - -
    __IO uint32_t MMCTIMR
    -
    - -
    -
    - -

    ◆ RESERVED3 [2/4]

    - -
    -
    - - - - -
    uint32_t RESERVED3[14]
    -
    - -
    -
    - -

    ◆ MMCTGFSCCR

    - -
    -
    - - - - -
    __IO uint32_t MMCTGFSCCR
    -
    - -
    -
    - -

    ◆ MMCTGFMSCCR

    - -
    -
    - - - - -
    __IO uint32_t MMCTGFMSCCR
    -
    - -
    -
    - -

    ◆ RESERVED4 [2/3]

    - -
    -
    - - - - -
    uint32_t RESERVED4[5]
    -
    - -
    -
    - -

    ◆ MMCTGFCR

    - -
    -
    - - - - -
    __IO uint32_t MMCTGFCR
    -
    - -
    -
    - -

    ◆ RESERVED5 [2/3]

    - -
    -
    - - - - -
    uint32_t RESERVED5[10]
    -
    - -
    -
    - -

    ◆ MMCRFCECR

    - -
    -
    - - - - -
    __IO uint32_t MMCRFCECR
    -
    - -
    -
    - -

    ◆ MMCRFAECR

    - -
    -
    - - - - -
    __IO uint32_t MMCRFAECR
    -
    - -
    -
    - -

    ◆ RESERVED6 [1/2]

    - -
    -
    - - - - -
    uint32_t RESERVED6[10]
    -
    - -
    -
    - -

    ◆ MMCRGUFCR

    - -
    -
    - - - - -
    __IO uint32_t MMCRGUFCR
    -
    - -
    -
    - -

    ◆ RESERVED7 [1/2]

    - -
    -
    - - - - -
    uint32_t RESERVED7[334]
    -
    - -
    -
    - -

    ◆ PTPTSCR

    - -
    -
    - - - - -
    __IO uint32_t PTPTSCR
    -
    - -
    -
    - -

    ◆ PTPSSIR

    - -
    -
    - - - - -
    __IO uint32_t PTPSSIR
    -
    - -
    -
    - -

    ◆ PTPTSHR

    - -
    -
    - - - - -
    __IO uint32_t PTPTSHR
    -
    - -
    -
    - -

    ◆ PTPTSLR

    - -
    -
    - - - - -
    __IO uint32_t PTPTSLR
    -
    - -
    -
    - -

    ◆ PTPTSHUR

    - -
    -
    - - - - -
    __IO uint32_t PTPTSHUR
    -
    - -
    -
    - -

    ◆ PTPTSLUR

    - -
    -
    - - - - -
    __IO uint32_t PTPTSLUR
    -
    - -
    -
    - -

    ◆ PTPTSAR

    - -
    -
    - - - - -
    __IO uint32_t PTPTSAR
    -
    - -
    -
    - -

    ◆ PTPTTHR

    - -
    -
    - - - - -
    __IO uint32_t PTPTTHR
    -
    - -
    -
    - -

    ◆ PTPTTLR

    - -
    -
    - - - - -
    __IO uint32_t PTPTTLR
    -
    - -
    -
    - -

    ◆ RESERVED8

    - -
    -
    - - - - -
    __IO uint32_t RESERVED8
    -
    - -
    -
    - -

    ◆ PTPTSSR

    - -
    -
    - - - - -
    __IO uint32_t PTPTSSR
    -
    - -
    -
    - -

    ◆ RESERVED9

    - -
    -
    - - - - -
    uint32_t RESERVED9[565]
    -
    - -
    -
    - -

    ◆ DMABMR

    - -
    -
    - - - - -
    __IO uint32_t DMABMR
    -
    - -
    -
    - -

    ◆ DMATPDR

    - -
    -
    - - - - -
    __IO uint32_t DMATPDR
    -
    - -
    -
    - -

    ◆ DMARPDR

    - -
    -
    - - - - -
    __IO uint32_t DMARPDR
    -
    - -
    -
    - -

    ◆ DMARDLAR

    - -
    -
    - - - - -
    __IO uint32_t DMARDLAR
    -
    - -
    -
    - -

    ◆ DMATDLAR

    - -
    -
    - - - - -
    __IO uint32_t DMATDLAR
    -
    - -
    -
    - -

    ◆ DMASR

    - -
    -
    - - - - -
    __IO uint32_t DMASR
    -
    - -
    -
    - -

    ◆ DMAOMR

    - -
    -
    - - - - -
    __IO uint32_t DMAOMR
    -
    - -
    -
    - -

    ◆ DMAIER

    - -
    -
    - - - - -
    __IO uint32_t DMAIER
    -
    - -
    -
    - -

    ◆ DMAMFBOCR

    - -
    -
    - - - - -
    __IO uint32_t DMAMFBOCR
    -
    - -
    -
    - -

    ◆ DMARSWTR

    - -
    -
    - - - - -
    __IO uint32_t DMARSWTR
    -
    - -
    -
    - -

    ◆ RESERVED10

    - -
    -
    - - - - -
    uint32_t RESERVED10[8]
    -
    - -
    -
    - -

    ◆ DMACHTDR

    - -
    -
    - - - - -
    __IO uint32_t DMACHTDR
    -
    - -
    -
    - -

    ◆ DMACHRDR

    - -
    -
    - - - - -
    __IO uint32_t DMACHRDR
    -
    - -
    -
    - -

    ◆ DMACHTBAR

    - -
    -
    - - - - -
    __IO uint32_t DMACHTBAR
    -
    - -
    -
    - -

    ◆ DMACHRBAR

    - -
    -
    - - - - -
    __IO uint32_t DMACHRBAR
    -
    - -
    -
    - -

    ◆ IMR

    - -
    -
    - - - - -
    __IO uint32_t IMR
    -
    -

    EXTI Interrupt mask register, Address offset: 0x00

    - -
    -
    - -

    ◆ EMR

    - -
    -
    - - - - -
    __IO uint32_t EMR
    -
    -

    EXTI Event mask register, Address offset: 0x04

    - -
    -
    - -

    ◆ RTSR

    - -
    -
    - - - - -
    __IO uint32_t RTSR
    -
    -

    EXTI Rising trigger selection register, Address offset: 0x08

    - -
    -
    - -

    ◆ FTSR

    - -
    -
    - - - - -
    __IO uint32_t FTSR
    -
    -

    EXTI Falling trigger selection register, Address offset: 0x0C

    - -
    -
    - -

    ◆ SWIER

    - -
    -
    - - - - -
    __IO uint32_t SWIER
    -
    -

    EXTI Software interrupt event register, Address offset: 0x10

    - -
    -
    - -

    ◆ PR [1/2]

    - -
    -
    - - - - -
    __IO uint32_t PR
    -
    -

    EXTI Pending register, Address offset: 0x14

    - -
    -
    - -

    ◆ ACR

    - -
    -
    - - - - -
    __IO uint32_t ACR
    -
    -

    FLASH access control register, Address offset: 0x00

    - -
    -
    - -

    ◆ KEYR

    - -
    -
    - - - - -
    __IO uint32_t KEYR
    -
    -

    FLASH key register, Address offset: 0x04

    - -
    -
    - -

    ◆ OPTKEYR

    - -
    -
    - - - - -
    __IO uint32_t OPTKEYR
    -
    -

    FLASH option key register, Address offset: 0x08

    - -
    -
    - -

    ◆ SR [4/10]

    - -
    -
    - - - - -
    __IO uint32_t SR
    -
    -

    FLASH status register, Address offset: 0x0C

    - -
    -
    - -

    ◆ CR [6/11]

    - -
    -
    - - - - -
    __IO uint32_t CR
    -
    -

    FLASH control register, Address offset: 0x10

    - -
    -
    - -

    ◆ OPTCR

    - -
    -
    - - - - -
    __IO uint32_t OPTCR
    -
    -

    FLASH option control register , Address offset: 0x14

    - -
    -
    - -

    ◆ OPTCR1

    - -
    -
    - - - - -
    __IO uint32_t OPTCR1
    -
    -

    FLASH option control register 1, Address offset: 0x18

    - -
    -
    - -

    ◆ BTCR

    - -
    -
    - - - - -
    __IO uint32_t BTCR[8]
    -
    -

    NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C

    - -
    -
    - -

    ◆ BWTR

    - -
    -
    - - - - -
    __IO uint32_t BWTR[7]
    -
    -

    NOR/PSRAM write timing registers, Address offset: 0x104-0x11C

    - -
    -
    - -

    ◆ PCR2

    - -
    -
    - - - - -
    __IO uint32_t PCR2
    -
    -

    NAND Flash control register 2, Address offset: 0x60

    - -
    -
    - -

    ◆ SR2 [1/2]

    - -
    -
    - - - - -
    __IO uint32_t SR2
    -
    -

    NAND Flash FIFO status and interrupt register 2, Address offset: 0x64

    - -
    -
    - -

    ◆ PMEM2

    - -
    -
    - - - - -
    __IO uint32_t PMEM2
    -
    -

    NAND Flash Common memory space timing register 2, Address offset: 0x68

    - -
    -
    - -

    ◆ PATT2

    - -
    -
    - - - - -
    __IO uint32_t PATT2
    -
    -

    NAND Flash Attribute memory space timing register 2, Address offset: 0x6C

    - -
    -
    - -

    ◆ RESERVED0 [4/6]

    - -
    -
    - - - - -
    uint32_t RESERVED0
    -
    -

    Reserved, 0x70
    -

    - -
    -
    - -

    ◆ ECCR2

    - -
    -
    - - - - -
    __IO uint32_t ECCR2
    -
    -

    NAND Flash ECC result registers 2, Address offset: 0x74

    - -
    -
    - -

    ◆ RESERVED1 [4/6]

    - -
    -
    - - - - -
    uint32_t RESERVED1
    -
    -

    Reserved, 0x78
    -

    - -
    -
    - -

    ◆ RESERVED2 [3/4]

    - -
    -
    - - - - -
    uint32_t RESERVED2
    -
    -

    Reserved, 0x7C
    -

    - -
    -
    - -

    ◆ PCR3

    - -
    -
    - - - - -
    __IO uint32_t PCR3
    -
    -

    NAND Flash control register 3, Address offset: 0x80

    - -
    -
    - -

    ◆ SR3

    - -
    -
    - - - - -
    __IO uint32_t SR3
    -
    -

    NAND Flash FIFO status and interrupt register 3, Address offset: 0x84

    - -
    -
    - -

    ◆ PMEM3

    - -
    -
    - - - - -
    __IO uint32_t PMEM3
    -
    -

    NAND Flash Common memory space timing register 3, Address offset: 0x88

    - -
    -
    - -

    ◆ PATT3

    - -
    -
    - - - - -
    __IO uint32_t PATT3
    -
    -

    NAND Flash Attribute memory space timing register 3, Address offset: 0x8C

    - -
    -
    - -

    ◆ RESERVED3 [3/4]

    - -
    -
    - - - - -
    uint32_t RESERVED3
    -
    -

    Reserved, 0x90
    -

    - -
    -
    - -

    ◆ ECCR3

    - -
    -
    - - - - -
    __IO uint32_t ECCR3
    -
    -

    NAND Flash ECC result registers 3, Address offset: 0x94

    - -
    -
    - -

    ◆ PCR4

    - -
    -
    - - - - -
    __IO uint32_t PCR4
    -
    -

    PC Card control register 4, Address offset: 0xA0

    - -
    -
    - -

    ◆ SR4

    - -
    -
    - - - - -
    __IO uint32_t SR4
    -
    -

    PC Card FIFO status and interrupt register 4, Address offset: 0xA4

    - -
    -
    - -

    ◆ PMEM4

    - -
    -
    - - - - -
    __IO uint32_t PMEM4
    -
    -

    PC Card Common memory space timing register 4, Address offset: 0xA8

    - -
    -
    - -

    ◆ PATT4

    - -
    -
    - - - - -
    __IO uint32_t PATT4
    -
    -

    PC Card Attribute memory space timing register 4, Address offset: 0xAC

    - -
    -
    - -

    ◆ PIO4

    - -
    -
    - - - - -
    __IO uint32_t PIO4
    -
    -

    PC Card I/O space timing register 4, Address offset: 0xB0

    - -
    -
    - -

    ◆ MODER

    - -
    -
    - - - - -
    __IO uint32_t MODER
    -
    -

    GPIO port mode register, Address offset: 0x00
    -

    - -
    -
    - -

    ◆ OTYPER

    - -
    -
    - - - - -
    __IO uint32_t OTYPER
    -
    -

    GPIO port output type register, Address offset: 0x04
    -

    - -
    -
    - -

    ◆ OSPEEDR

    - -
    -
    - - - - -
    __IO uint32_t OSPEEDR
    -
    -

    GPIO port output speed register, Address offset: 0x08
    -

    - -
    -
    - -

    ◆ PUPDR

    - -
    -
    - - - - -
    __IO uint32_t PUPDR
    -
    -

    GPIO port pull-up/pull-down register, Address offset: 0x0C
    -

    - -
    -
    - -

    ◆ IDR [2/2]

    - -
    -
    - - - - -
    __IO uint32_t IDR
    -
    -

    GPIO port input data register, Address offset: 0x10
    -

    - -
    -
    - -

    ◆ ODR

    - -
    -
    - - - - -
    __IO uint32_t ODR
    -
    -

    GPIO port output data register, Address offset: 0x14
    -

    - -
    -
    - -

    ◆ BSRR

    - -
    -
    - - - - -
    __IO uint32_t BSRR
    -
    -

    GPIO port bit set/reset register, Address offset: 0x18
    -

    - -
    -
    - -

    ◆ LCKR

    - -
    -
    - - - - -
    __IO uint32_t LCKR
    -
    -

    GPIO port configuration lock register, Address offset: 0x1C
    -

    - -
    -
    - -

    ◆ AFR

    - -
    -
    - - - - -
    __IO uint32_t AFR[2]
    -
    -

    GPIO alternate function registers, Address offset: 0x20-0x24

    - -
    -
    - -

    ◆ MEMRMP

    - -
    -
    - - - - -
    __IO uint32_t MEMRMP
    -
    -

    SYSCFG memory remap register, Address offset: 0x00
    -

    - -
    -
    - -

    ◆ PMC

    - -
    -
    - - - - -
    __IO uint32_t PMC
    -
    -

    SYSCFG peripheral mode configuration register, Address offset: 0x04
    -

    - -
    -
    - -

    ◆ EXTICR

    - -
    -
    - - - - -
    __IO uint32_t EXTICR[4]
    -
    -

    SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14

    - -
    -
    - -

    ◆ RESERVED

    - -
    -
    - - - - -
    uint32_t RESERVED[2]
    -
    -

    Reserved, 0x18-0x1C
    -

    - -
    -
    - -

    ◆ CMPCR

    - -
    -
    - - - - -
    __IO uint32_t CMPCR
    -
    -

    SYSCFG Compensation cell control register, Address offset: 0x20
    -

    - -
    -
    - -

    ◆ CR1 [2/5]

    - -
    -
    - - - - -
    __IO uint32_t CR1
    -
    -

    I2C Control register 1, Address offset: 0x00

    - -
    -
    - -

    ◆ CR2 [2/5]

    - -
    -
    - - - - -
    __IO uint32_t CR2
    -
    -

    I2C Control register 2, Address offset: 0x04

    - -
    -
    - -

    ◆ OAR1

    - -
    -
    - - - - -
    __IO uint32_t OAR1
    -
    -

    I2C Own address register 1, Address offset: 0x08

    - -
    -
    - -

    ◆ OAR2

    - -
    -
    - - - - -
    __IO uint32_t OAR2
    -
    -

    I2C Own address register 2, Address offset: 0x0C

    - -
    -
    - -

    ◆ DR [4/8]

    - -
    -
    - - - - -
    __IO uint32_t DR
    -
    -

    I2C Data register, Address offset: 0x10

    - -
    -
    - -

    ◆ SR1

    - -
    -
    - - - - -
    __IO uint32_t SR1
    -
    -

    I2C Status register 1, Address offset: 0x14

    - -
    -
    - -

    ◆ SR2 [2/2]

    - -
    -
    - - - - -
    __IO uint32_t SR2
    -
    -

    I2C Status register 2, Address offset: 0x18

    - -
    -
    - -

    ◆ CCR [2/2]

    - -
    -
    - - - - -
    __IO uint32_t CCR
    -
    -

    I2C Clock control register, Address offset: 0x1C

    - -
    -
    - -

    ◆ TRISE

    - -
    -
    - - - - -
    __IO uint32_t TRISE
    -
    -

    I2C TRISE register, Address offset: 0x20

    - -
    -
    - -

    ◆ KR

    - -
    -
    - - - - -
    __IO uint32_t KR
    -
    -

    IWDG Key register, Address offset: 0x00

    - -
    -
    - -

    ◆ PR [2/2]

    - -
    -
    - - - - -
    __IO uint32_t PR
    -
    -

    IWDG Prescaler register, Address offset: 0x04

    - -
    -
    - -

    ◆ RLR

    - -
    -
    - - - - -
    __IO uint32_t RLR
    -
    -

    IWDG Reload register, Address offset: 0x08

    - -
    -
    - -

    ◆ SR [5/10]

    - -
    -
    - - - - -
    __IO uint32_t SR
    -
    -

    IWDG Status register, Address offset: 0x0C

    - -
    -
    - -

    ◆ CR [7/11]

    - -
    -
    - - - - -
    __IO uint32_t CR
    -
    -

    PWR power control register, Address offset: 0x00

    - -
    -
    - -

    ◆ CSR [2/3]

    - -
    -
    - - - - -
    __IO uint32_t CSR
    -
    -

    PWR power control/status register, Address offset: 0x04

    - -
    -
    - -

    ◆ CR [8/11]

    - -
    -
    - - - - -
    __IO uint32_t CR
    -
    -

    RCC clock control register, Address offset: 0x00

    - -
    -
    - -

    ◆ PLLCFGR

    - -
    -
    - - - - -
    __IO uint32_t PLLCFGR
    -
    -

    RCC PLL configuration register, Address offset: 0x04

    - -
    -
    - -

    ◆ CFGR

    - -
    -
    - - - - -
    __IO uint32_t CFGR
    -
    -

    RCC clock configuration register, Address offset: 0x08

    - -
    -
    - -

    ◆ CIR

    - -
    -
    - - - - -
    __IO uint32_t CIR
    -
    -

    RCC clock interrupt register, Address offset: 0x0C

    - -
    -
    - -

    ◆ AHB1RSTR

    - -
    -
    - - - - -
    __IO uint32_t AHB1RSTR
    -
    -

    RCC AHB1 peripheral reset register, Address offset: 0x10

    - -
    -
    - -

    ◆ AHB2RSTR

    - -
    -
    - - - - -
    __IO uint32_t AHB2RSTR
    -
    -

    RCC AHB2 peripheral reset register, Address offset: 0x14

    - -
    -
    - -

    ◆ AHB3RSTR

    - -
    -
    - - - - -
    __IO uint32_t AHB3RSTR
    -
    -

    RCC AHB3 peripheral reset register, Address offset: 0x18

    - -
    -
    - -

    ◆ RESERVED0 [5/6]

    - -
    -
    - - - - -
    uint32_t RESERVED0
    -
    -

    Reserved, 0x1C
    -

    - -
    -
    - -

    ◆ APB1RSTR

    - -
    -
    - - - - -
    __IO uint32_t APB1RSTR
    -
    -

    RCC APB1 peripheral reset register, Address offset: 0x20

    - -
    -
    - -

    ◆ APB2RSTR

    - -
    -
    - - - - -
    __IO uint32_t APB2RSTR
    -
    -

    RCC APB2 peripheral reset register, Address offset: 0x24

    - -
    -
    - -

    ◆ RESERVED1 [5/6]

    - -
    -
    - - - - -
    uint32_t RESERVED1[2]
    -
    -

    Reserved, 0x28-0x2C
    -

    - -
    -
    - -

    ◆ AHB1ENR

    - -
    -
    - - - - -
    __IO uint32_t AHB1ENR
    -
    -

    RCC AHB1 peripheral clock register, Address offset: 0x30

    - -
    -
    - -

    ◆ AHB2ENR

    - -
    -
    - - - - -
    __IO uint32_t AHB2ENR
    -
    -

    RCC AHB2 peripheral clock register, Address offset: 0x34

    - -
    -
    - -

    ◆ AHB3ENR

    - -
    -
    - - - - -
    __IO uint32_t AHB3ENR
    -
    -

    RCC AHB3 peripheral clock register, Address offset: 0x38

    - -
    -
    - -

    ◆ RESERVED2 [4/4]

    - -
    -
    - - - - -
    uint32_t RESERVED2
    -
    -

    Reserved, 0x3C
    -

    - -
    -
    - -

    ◆ APB1ENR

    - -
    -
    - - - - -
    __IO uint32_t APB1ENR
    -
    -

    RCC APB1 peripheral clock enable register, Address offset: 0x40

    - -
    -
    - -

    ◆ APB2ENR

    - -
    -
    - - - - -
    __IO uint32_t APB2ENR
    -
    -

    RCC APB2 peripheral clock enable register, Address offset: 0x44

    - -
    -
    - -

    ◆ RESERVED3 [4/4]

    - -
    -
    - - - - -
    uint32_t RESERVED3[2]
    -
    -

    Reserved, 0x48-0x4C
    -

    - -
    -
    - -

    ◆ AHB1LPENR

    - -
    -
    - - - - -
    __IO uint32_t AHB1LPENR
    -
    -

    RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50

    - -
    -
    - -

    ◆ AHB2LPENR

    - -
    -
    - - - - -
    __IO uint32_t AHB2LPENR
    -
    -

    RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54

    - -
    -
    - -

    ◆ AHB3LPENR

    - -
    -
    - - - - -
    __IO uint32_t AHB3LPENR
    -
    -

    RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58

    - -
    -
    - -

    ◆ RESERVED4 [3/3]

    - -
    -
    - - - - -
    uint32_t RESERVED4
    -
    -

    Reserved, 0x5C
    -

    - -
    -
    - -

    ◆ APB1LPENR

    - -
    -
    - - - - -
    __IO uint32_t APB1LPENR
    -
    -

    RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60

    - -
    -
    - -

    ◆ APB2LPENR

    - -
    -
    - - - - -
    __IO uint32_t APB2LPENR
    -
    -

    RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64

    - -
    -
    - -

    ◆ RESERVED5 [3/3]

    - -
    -
    - - - - -
    uint32_t RESERVED5[2]
    -
    -

    Reserved, 0x68-0x6C
    -

    - -
    -
    - -

    ◆ BDCR

    - -
    -
    - - - - -
    __IO uint32_t BDCR
    -
    -

    RCC Backup domain control register, Address offset: 0x70

    - -
    -
    - -

    ◆ CSR [3/3]

    - -
    -
    - - - - -
    __IO uint32_t CSR
    -
    -

    RCC clock control & status register, Address offset: 0x74

    - -
    -
    - -

    ◆ RESERVED6 [2/2]

    - -
    -
    - - - - -
    uint32_t RESERVED6[2]
    -
    -

    Reserved, 0x78-0x7C
    -

    - -
    -
    - -

    ◆ SSCGR

    - -
    -
    - - - - -
    __IO uint32_t SSCGR
    -
    -

    RCC spread spectrum clock generation register, Address offset: 0x80

    - -
    -
    - -

    ◆ PLLI2SCFGR

    - -
    -
    - - - - -
    __IO uint32_t PLLI2SCFGR
    -
    -

    RCC PLLI2S configuration register, Address offset: 0x84

    - -
    -
    - -

    ◆ TR

    - -
    -
    - - - - -
    __IO uint32_t TR
    -
    -

    RTC time register, Address offset: 0x00

    - -
    -
    - -

    ◆ DR [5/8]

    - -
    -
    - - - - -
    __IO uint32_t DR
    -
    -

    RTC date register, Address offset: 0x04

    - -
    -
    - -

    ◆ CR [9/11]

    - -
    -
    - - - - -
    __IO uint32_t CR
    -
    -

    RTC control register, Address offset: 0x08

    - -
    -
    - -

    ◆ ISR

    - -
    -
    - - - - -
    __IO uint32_t ISR
    -
    -

    RTC initialization and status register, Address offset: 0x0C

    - -
    -
    - -

    ◆ PRER

    - -
    -
    - - - - -
    __IO uint32_t PRER
    -
    -

    RTC prescaler register, Address offset: 0x10

    - -
    -
    - -

    ◆ WUTR

    - -
    -
    - - - - -
    __IO uint32_t WUTR
    -
    -

    RTC wakeup timer register, Address offset: 0x14

    - -
    -
    - -

    ◆ CALIBR

    - -
    -
    - - - - -
    __IO uint32_t CALIBR
    -
    -

    RTC calibration register, Address offset: 0x18

    - -
    -
    - -

    ◆ ALRMAR

    - -
    -
    - - - - -
    __IO uint32_t ALRMAR
    -
    -

    RTC alarm A register, Address offset: 0x1C

    - -
    -
    - -

    ◆ ALRMBR

    - -
    -
    - - - - -
    __IO uint32_t ALRMBR
    -
    -

    RTC alarm B register, Address offset: 0x20

    - -
    -
    - -

    ◆ WPR

    - -
    -
    - - - - -
    __IO uint32_t WPR
    -
    -

    RTC write protection register, Address offset: 0x24

    - -
    -
    - -

    ◆ SSR

    - -
    -
    - - - - -
    __IO uint32_t SSR
    -
    -

    RTC sub second register, Address offset: 0x28

    - -
    -
    - -

    ◆ SHIFTR

    - -
    -
    - - - - -
    __IO uint32_t SHIFTR
    -
    -

    RTC shift control register, Address offset: 0x2C

    - -
    -
    - -

    ◆ TSTR

    - -
    -
    - - - - -
    __IO uint32_t TSTR
    -
    -

    RTC time stamp time register, Address offset: 0x30

    - -
    -
    - -

    ◆ TSDR

    - -
    -
    - - - - -
    __IO uint32_t TSDR
    -
    -

    RTC time stamp date register, Address offset: 0x34

    - -
    -
    - -

    ◆ TSSSR

    - -
    -
    - - - - -
    __IO uint32_t TSSSR
    -
    -

    RTC time-stamp sub second register, Address offset: 0x38

    - -
    -
    - -

    ◆ CALR

    - -
    -
    - - - - -
    __IO uint32_t CALR
    -
    -

    RTC calibration register, Address offset: 0x3C

    - -
    -
    - -

    ◆ TAFCR

    - -
    -
    - - - - -
    __IO uint32_t TAFCR
    -
    -

    RTC tamper and alternate function configuration register, Address offset: 0x40

    - -
    -
    - -

    ◆ ALRMASSR

    - -
    -
    - - - - -
    __IO uint32_t ALRMASSR
    -
    -

    RTC alarm A sub second register, Address offset: 0x44

    - -
    -
    - -

    ◆ ALRMBSSR

    - -
    -
    - - - - -
    __IO uint32_t ALRMBSSR
    -
    -

    RTC alarm B sub second register, Address offset: 0x48

    - -
    -
    - -

    ◆ RESERVED7 [2/2]

    - -
    -
    - - - - -
    uint32_t RESERVED7
    -
    -

    Reserved, 0x4C
    -

    - -
    -
    - -

    ◆ BKP0R

    - -
    -
    - - - - -
    __IO uint32_t BKP0R
    -
    -

    RTC backup register 1, Address offset: 0x50

    - -
    -
    - -

    ◆ BKP1R

    - -
    -
    - - - - -
    __IO uint32_t BKP1R
    -
    -

    RTC backup register 1, Address offset: 0x54

    - -
    -
    - -

    ◆ BKP2R

    - -
    -
    - - - - -
    __IO uint32_t BKP2R
    -
    -

    RTC backup register 2, Address offset: 0x58

    - -
    -
    - -

    ◆ BKP3R

    - -
    -
    - - - - -
    __IO uint32_t BKP3R
    -
    -

    RTC backup register 3, Address offset: 0x5C

    - -
    -
    - -

    ◆ BKP4R

    - -
    -
    - - - - -
    __IO uint32_t BKP4R
    -
    -

    RTC backup register 4, Address offset: 0x60

    - -
    -
    - -

    ◆ BKP5R

    - -
    -
    - - - - -
    __IO uint32_t BKP5R
    -
    -

    RTC backup register 5, Address offset: 0x64

    - -
    -
    - -

    ◆ BKP6R

    - -
    -
    - - - - -
    __IO uint32_t BKP6R
    -
    -

    RTC backup register 6, Address offset: 0x68

    - -
    -
    - -

    ◆ BKP7R

    - -
    -
    - - - - -
    __IO uint32_t BKP7R
    -
    -

    RTC backup register 7, Address offset: 0x6C

    - -
    -
    - -

    ◆ BKP8R

    - -
    -
    - - - - -
    __IO uint32_t BKP8R
    -
    -

    RTC backup register 8, Address offset: 0x70

    - -
    -
    - -

    ◆ BKP9R

    - -
    -
    - - - - -
    __IO uint32_t BKP9R
    -
    -

    RTC backup register 9, Address offset: 0x74

    - -
    -
    - -

    ◆ BKP10R

    - -
    -
    - - - - -
    __IO uint32_t BKP10R
    -
    -

    RTC backup register 10, Address offset: 0x78

    - -
    -
    - -

    ◆ BKP11R

    - -
    -
    - - - - -
    __IO uint32_t BKP11R
    -
    -

    RTC backup register 11, Address offset: 0x7C

    - -
    -
    - -

    ◆ BKP12R

    - -
    -
    - - - - -
    __IO uint32_t BKP12R
    -
    -

    RTC backup register 12, Address offset: 0x80

    - -
    -
    - -

    ◆ BKP13R

    - -
    -
    - - - - -
    __IO uint32_t BKP13R
    -
    -

    RTC backup register 13, Address offset: 0x84

    - -
    -
    - -

    ◆ BKP14R

    - -
    -
    - - - - -
    __IO uint32_t BKP14R
    -
    -

    RTC backup register 14, Address offset: 0x88

    - -
    -
    - -

    ◆ BKP15R

    - -
    -
    - - - - -
    __IO uint32_t BKP15R
    -
    -

    RTC backup register 15, Address offset: 0x8C

    - -
    -
    - -

    ◆ BKP16R

    - -
    -
    - - - - -
    __IO uint32_t BKP16R
    -
    -

    RTC backup register 16, Address offset: 0x90

    - -
    -
    - -

    ◆ BKP17R

    - -
    -
    - - - - -
    __IO uint32_t BKP17R
    -
    -

    RTC backup register 17, Address offset: 0x94

    - -
    -
    - -

    ◆ BKP18R

    - -
    -
    - - - - -
    __IO uint32_t BKP18R
    -
    -

    RTC backup register 18, Address offset: 0x98

    - -
    -
    - -

    ◆ BKP19R

    - -
    -
    - - - - -
    __IO uint32_t BKP19R
    -
    -

    RTC backup register 19, Address offset: 0x9C

    - -
    -
    - -

    ◆ POWER

    - -
    -
    - - - - -
    __IO uint32_t POWER
    -
    -

    SDIO power control register, Address offset: 0x00

    - -
    -
    - -

    ◆ CLKCR

    - -
    -
    - - - - -
    __IO uint32_t CLKCR
    -
    -

    SDI clock control register, Address offset: 0x04

    - -
    -
    - -

    ◆ ARG

    - -
    -
    - - - - -
    __IO uint32_t ARG
    -
    -

    SDIO argument register, Address offset: 0x08

    - -
    -
    - -

    ◆ CMD

    - -
    -
    - - - - -
    __IO uint32_t CMD
    -
    -

    SDIO command register, Address offset: 0x0C

    - -
    -
    - -

    ◆ RESPCMD

    - -
    -
    - - - - -
    __IO const uint32_t RESPCMD
    -
    -

    SDIO command response register, Address offset: 0x10

    - -
    -
    - -

    ◆ RESP1

    - -
    -
    - - - - -
    __IO const uint32_t RESP1
    -
    -

    SDIO response 1 register, Address offset: 0x14

    - -
    -
    - -

    ◆ RESP2

    - -
    -
    - - - - -
    __IO const uint32_t RESP2
    -
    -

    SDIO response 2 register, Address offset: 0x18

    - -
    -
    - -

    ◆ RESP3

    - -
    -
    - - - - -
    __IO const uint32_t RESP3
    -
    -

    SDIO response 3 register, Address offset: 0x1C

    - -
    -
    - -

    ◆ RESP4

    - -
    -
    - - - - -
    __IO const uint32_t RESP4
    -
    -

    SDIO response 4 register, Address offset: 0x20

    - -
    -
    - -

    ◆ DTIMER

    - -
    -
    - - - - -
    __IO uint32_t DTIMER
    -
    -

    SDIO data timer register, Address offset: 0x24

    - -
    -
    - -

    ◆ DLEN

    - -
    -
    - - - - -
    __IO uint32_t DLEN
    -
    -

    SDIO data length register, Address offset: 0x28

    - -
    -
    - -

    ◆ DCTRL

    - -
    -
    - - - - -
    __IO uint32_t DCTRL
    -
    -

    SDIO data control register, Address offset: 0x2C

    - -
    -
    - -

    ◆ DCOUNT

    - -
    -
    - - - - -
    __IO const uint32_t DCOUNT
    -
    -

    SDIO data counter register, Address offset: 0x30

    - -
    -
    - -

    ◆ STA

    - -
    -
    - - - - -
    __IO const uint32_t STA
    -
    -

    SDIO status register, Address offset: 0x34

    - -
    -
    - -

    ◆ ICR [2/2]

    - -
    -
    - - - - -
    __IO uint32_t ICR
    -
    -

    SDIO interrupt clear register, Address offset: 0x38

    - -
    -
    - -

    ◆ MASK

    - -
    -
    - - - - -
    __IO uint32_t MASK
    -
    -

    SDIO mask register, Address offset: 0x3C

    - -
    -
    - -

    ◆ RESERVED0 [6/6]

    - -
    -
    - - - - -
    uint32_t RESERVED0[2]
    -
    -

    Reserved, 0x40-0x44
    -

    - -
    -
    - -

    ◆ FIFOCNT

    - -
    -
    - - - - -
    __IO const uint32_t FIFOCNT
    -
    -

    SDIO FIFO counter register, Address offset: 0x48

    - -
    -
    - -

    ◆ RESERVED1 [6/6]

    - -
    -
    - - - - -
    uint32_t RESERVED1[13]
    -
    -

    Reserved, 0x4C-0x7C
    -

    - -
    -
    - -

    ◆ FIFO

    - -
    -
    - - - - -
    __IO uint32_t FIFO
    -
    -

    SDIO data FIFO register, Address offset: 0x80

    - -
    -
    - -

    ◆ CR1 [3/5]

    - -
    -
    - - - - -
    __IO uint32_t CR1
    -
    -

    SPI control register 1 (not used in I2S mode), Address offset: 0x00

    - -
    -
    - -

    ◆ CR2 [3/5]

    - -
    -
    - - - - -
    __IO uint32_t CR2
    -
    -

    SPI control register 2, Address offset: 0x04

    - -
    -
    - -

    ◆ SR [6/10]

    - -
    -
    - - - - -
    __IO uint32_t SR
    -
    -

    SPI status register, Address offset: 0x08

    - -
    -
    - -

    ◆ DR [6/8]

    - -
    -
    - - - - -
    __IO uint32_t DR
    -
    -

    SPI data register, Address offset: 0x0C

    - -
    -
    - -

    ◆ CRCPR

    - -
    -
    - - - - -
    __IO uint32_t CRCPR
    -
    -

    SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10

    - -
    -
    - -

    ◆ RXCRCR

    - -
    -
    - - - - -
    __IO uint32_t RXCRCR
    -
    -

    SPI RX CRC register (not used in I2S mode), Address offset: 0x14

    - -
    -
    - -

    ◆ TXCRCR

    - -
    -
    - - - - -
    __IO uint32_t TXCRCR
    -
    -

    SPI TX CRC register (not used in I2S mode), Address offset: 0x18

    - -
    -
    - -

    ◆ I2SCFGR

    - -
    -
    - - - - -
    __IO uint32_t I2SCFGR
    -
    -

    SPI_I2S configuration register, Address offset: 0x1C

    - -
    -
    - -

    ◆ I2SPR

    - -
    -
    - - - - -
    __IO uint32_t I2SPR
    -
    -

    SPI_I2S prescaler register, Address offset: 0x20

    - -
    -
    - -

    ◆ CR1 [4/5]

    - -
    -
    - - - - -
    __IO uint32_t CR1
    -
    -

    TIM control register 1, Address offset: 0x00

    - -
    -
    - -

    ◆ CR2 [4/5]

    - -
    -
    - - - - -
    __IO uint32_t CR2
    -
    -

    TIM control register 2, Address offset: 0x04

    - -
    -
    - -

    ◆ SMCR

    - -
    -
    - - - - -
    __IO uint32_t SMCR
    -
    -

    TIM slave mode control register, Address offset: 0x08

    - -
    -
    - -

    ◆ DIER

    - -
    -
    - - - - -
    __IO uint32_t DIER
    -
    -

    TIM DMA/interrupt enable register, Address offset: 0x0C

    - -
    -
    - -

    ◆ SR [7/10]

    - -
    -
    - - - - -
    __IO uint32_t SR
    -
    -

    TIM status register, Address offset: 0x10

    - -
    -
    - -

    ◆ EGR

    - -
    -
    - - - - -
    __IO uint32_t EGR
    -
    -

    TIM event generation register, Address offset: 0x14

    - -
    -
    - -

    ◆ CCMR1

    - -
    -
    - - - - -
    __IO uint32_t CCMR1
    -
    -

    TIM capture/compare mode register 1, Address offset: 0x18

    - -
    -
    - -

    ◆ CCMR2

    - -
    -
    - - - - -
    __IO uint32_t CCMR2
    -
    -

    TIM capture/compare mode register 2, Address offset: 0x1C

    - -
    -
    - -

    ◆ CCER

    - -
    -
    - - - - -
    __IO uint32_t CCER
    -
    -

    TIM capture/compare enable register, Address offset: 0x20

    - -
    -
    - -

    ◆ CNT

    - -
    -
    - - - - -
    __IO uint32_t CNT
    -
    -

    TIM counter register, Address offset: 0x24

    - -
    -
    - -

    ◆ PSC

    - -
    -
    - - - - -
    __IO uint32_t PSC
    -
    -

    TIM prescaler, Address offset: 0x28

    - -
    -
    - -

    ◆ ARR

    - -
    -
    - - - - -
    __IO uint32_t ARR
    -
    -

    TIM auto-reload register, Address offset: 0x2C

    - -
    -
    - -

    ◆ RCR

    - -
    -
    - - - - -
    __IO uint32_t RCR
    -
    -

    TIM repetition counter register, Address offset: 0x30

    - -
    -
    - -

    ◆ CCR1

    - -
    -
    - - - - -
    __IO uint32_t CCR1
    -
    -

    TIM capture/compare register 1, Address offset: 0x34

    - -
    -
    - -

    ◆ CCR2

    - -
    -
    - - - - -
    __IO uint32_t CCR2
    -
    -

    TIM capture/compare register 2, Address offset: 0x38

    - -
    -
    - -

    ◆ CCR3

    - -
    -
    - - - - -
    __IO uint32_t CCR3
    -
    -

    TIM capture/compare register 3, Address offset: 0x3C

    - -
    -
    - -

    ◆ CCR4

    - -
    -
    - - - - -
    __IO uint32_t CCR4
    -
    -

    TIM capture/compare register 4, Address offset: 0x40

    - -
    -
    - -

    ◆ BDTR

    - -
    -
    - - - - -
    __IO uint32_t BDTR
    -
    -

    TIM break and dead-time register, Address offset: 0x44

    - -
    -
    - -

    ◆ DCR

    - -
    -
    - - - - -
    __IO uint32_t DCR
    -
    -

    TIM DMA control register, Address offset: 0x48

    - -
    -
    - -

    ◆ DMAR

    - -
    -
    - - - - -
    __IO uint32_t DMAR
    -
    -

    TIM DMA address for full transfer, Address offset: 0x4C

    - -
    -
    - -

    ◆ OR

    - -
    -
    - - - - -
    __IO uint32_t OR
    -
    -

    TIM option register, Address offset: 0x50

    - -
    -
    - -

    ◆ SR [8/10]

    - -
    -
    - - - - -
    __IO uint32_t SR
    -
    -

    USART Status register, Address offset: 0x00

    - -
    -
    - -

    ◆ DR [7/8]

    - -
    -
    - - - - -
    __IO uint32_t DR
    -
    -

    USART Data register, Address offset: 0x04

    - -
    -
    - -

    ◆ BRR

    - -
    -
    - - - - -
    __IO uint32_t BRR
    -
    -

    USART Baud rate register, Address offset: 0x08

    - -
    -
    - -

    ◆ CR1 [5/5]

    - -
    -
    - - - - -
    __IO uint32_t CR1
    -
    -

    USART Control register 1, Address offset: 0x0C

    - -
    -
    - -

    ◆ CR2 [5/5]

    - -
    -
    - - - - -
    __IO uint32_t CR2
    -
    -

    USART Control register 2, Address offset: 0x10

    - -
    -
    - -

    ◆ CR3

    - -
    -
    - - - - -
    __IO uint32_t CR3
    -
    -

    USART Control register 3, Address offset: 0x14

    - -
    -
    - -

    ◆ GTPR

    - -
    -
    - - - - -
    __IO uint32_t GTPR
    -
    -

    USART Guard time and prescaler register, Address offset: 0x18

    - -
    -
    - -

    ◆ CR [10/11]

    - -
    -
    - - - - -
    __IO uint32_t CR
    -
    -

    WWDG Control register, Address offset: 0x00

    - -
    -
    - -

    ◆ CFR

    - -
    -
    - - - - -
    __IO uint32_t CFR
    -
    -

    WWDG Configuration register, Address offset: 0x04

    - -
    -
    - -

    ◆ SR [9/10]

    - -
    -
    - - - - -
    __IO uint32_t SR
    -
    -

    WWDG Status register, Address offset: 0x08

    - -
    -
    - -

    ◆ CR [11/11]

    - -
    -
    - - - - -
    __IO uint32_t CR
    -
    -

    RNG control register, Address offset: 0x00

    - -
    -
    - -

    ◆ SR [10/10]

    - -
    -
    - - - - -
    __IO uint32_t SR
    -
    -

    RNG status register, Address offset: 0x04

    - -
    -
    - -

    ◆ DR [8/8]

    - -
    -
    - - - - -
    __IO uint32_t DR
    -
    -

    RNG data register, Address offset: 0x08

    - -
    -
    - -

    ◆ GOTGCTL

    - -
    -
    - - - - -
    __IO uint32_t GOTGCTL
    -
    -

    USB_OTG Control and Status Register 000h

    - -
    -
    - -

    ◆ GOTGINT

    - -
    -
    - - - - -
    __IO uint32_t GOTGINT
    -
    -

    USB_OTG Interrupt Register 004h

    - -
    -
    - -

    ◆ GAHBCFG

    - -
    -
    - - - - -
    __IO uint32_t GAHBCFG
    -
    -

    Core AHB Configuration Register 008h

    - -
    -
    - -

    ◆ GUSBCFG

    - -
    -
    - - - - -
    __IO uint32_t GUSBCFG
    -
    -

    Core USB Configuration Register 00Ch

    - -
    -
    - -

    ◆ GRSTCTL

    - -
    -
    - - - - -
    __IO uint32_t GRSTCTL
    -
    -

    Core Reset Register 010h

    - -
    -
    - -

    ◆ GINTSTS

    - -
    -
    - - - - -
    __IO uint32_t GINTSTS
    -
    -

    Core Interrupt Register 014h

    - -
    -
    - -

    ◆ GINTMSK

    - -
    -
    - - - - -
    __IO uint32_t GINTMSK
    -
    -

    Core Interrupt Mask Register 018h

    - -
    -
    - -

    ◆ GRXSTSR

    - -
    -
    - - - - -
    __IO uint32_t GRXSTSR
    -
    -

    Receive Sts Q Read Register 01Ch

    - -
    -
    - -

    ◆ GRXSTSP

    - -
    -
    - - - - -
    __IO uint32_t GRXSTSP
    -
    -

    Receive Sts Q Read & POP Register 020h

    - -
    -
    - -

    ◆ GRXFSIZ

    - -
    -
    - - - - -
    __IO uint32_t GRXFSIZ
    -
    -

    Receive FIFO Size Register 024h

    - -
    -
    - -

    ◆ DIEPTXF0_HNPTXFSIZ

    - -
    -
    - - - - -
    __IO uint32_t DIEPTXF0_HNPTXFSIZ
    -
    -

    EP0 / Non Periodic Tx FIFO Size Register 028h

    - -
    -
    - -

    ◆ HNPTXSTS

    - -
    -
    - - - - -
    __IO uint32_t HNPTXSTS
    -
    -

    Non Periodic Tx FIFO/Queue Sts reg 02Ch

    - -
    -
    - -

    ◆ Reserved30

    - -
    -
    - - - - -
    uint32_t Reserved30[2]
    -
    -

    Reserved 030h

    - -
    -
    - -

    ◆ GCCFG

    - -
    -
    - - - - -
    __IO uint32_t GCCFG
    -
    -

    General Purpose IO Register 038h

    - -
    -
    - -

    ◆ CID

    - -
    -
    - - - - -
    __IO uint32_t CID
    -
    -

    User ID Register 03Ch

    - -
    -
    - -

    ◆ Reserved40 [1/2]

    - -
    -
    - - - - -
    uint32_t Reserved40[48]
    -
    -

    Reserved 0x40-0xFF

    - -
    -
    - -

    ◆ HPTXFSIZ

    - -
    -
    - - - - -
    __IO uint32_t HPTXFSIZ
    -
    -

    Host Periodic Tx FIFO Size Reg 100h

    - -
    -
    - -

    ◆ DIEPTXF

    - -
    -
    - - - - -
    __IO uint32_t DIEPTXF[0x0F]
    -
    -

    dev Periodic Transmit FIFO
    -

    - -
    -
    - -

    ◆ DCFG

    - -
    -
    - - - - -
    __IO uint32_t DCFG
    -
    -

    dev Configuration Register 800h

    - -
    -
    - -

    ◆ DCTL

    - -
    -
    - - - - -
    __IO uint32_t DCTL
    -
    -

    dev Control Register 804h

    - -
    -
    - -

    ◆ DSTS

    - -
    -
    - - - - -
    __IO uint32_t DSTS
    -
    -

    dev Status Register (RO) 808h

    - -
    -
    - -

    ◆ Reserved0C [1/3]

    - -
    -
    - - - - -
    uint32_t Reserved0C
    -
    -

    Reserved 80Ch

    - -
    -
    - -

    ◆ DIEPMSK

    - -
    -
    - - - - -
    __IO uint32_t DIEPMSK
    -
    -

    dev IN Endpoint Mask 810h

    - -
    -
    - -

    ◆ DOEPMSK

    - -
    -
    - - - - -
    __IO uint32_t DOEPMSK
    -
    -

    dev OUT Endpoint Mask 814h

    - -
    -
    - -

    ◆ DAINT

    - -
    -
    - - - - -
    __IO uint32_t DAINT
    -
    -

    dev All Endpoints Itr Reg 818h

    - -
    -
    - -

    ◆ DAINTMSK

    - -
    -
    - - - - -
    __IO uint32_t DAINTMSK
    -
    -

    dev All Endpoints Itr Mask 81Ch

    - -
    -
    - -

    ◆ Reserved20

    - -
    -
    - - - - -
    uint32_t Reserved20
    -
    -

    Reserved 820h

    - -
    -
    - -

    ◆ Reserved9

    - -
    -
    - - - - -
    uint32_t Reserved9
    -
    -

    Reserved 824h

    - -
    -
    - -

    ◆ DVBUSDIS

    - -
    -
    - - - - -
    __IO uint32_t DVBUSDIS
    -
    -

    dev VBUS discharge Register 828h

    - -
    -
    - -

    ◆ DVBUSPULSE

    - -
    -
    - - - - -
    __IO uint32_t DVBUSPULSE
    -
    -

    dev VBUS Pulse Register 82Ch

    - -
    -
    - -

    ◆ DTHRCTL

    - -
    -
    - - - - -
    __IO uint32_t DTHRCTL
    -
    -

    dev threshold 830h

    - -
    -
    - -

    ◆ DIEPEMPMSK

    - -
    -
    - - - - -
    __IO uint32_t DIEPEMPMSK
    -
    -

    dev empty msk 834h

    - -
    -
    - -

    ◆ DEACHINT

    - -
    -
    - - - - -
    __IO uint32_t DEACHINT
    -
    -

    dedicated EP interrupt 838h

    - -
    -
    - -

    ◆ DEACHMSK

    - -
    -
    - - - - -
    __IO uint32_t DEACHMSK
    -
    -

    dedicated EP msk 83Ch

    - -
    -
    - -

    ◆ Reserved40 [2/2]

    - -
    -
    - - - - -
    uint32_t Reserved40
    -
    -

    dedicated EP mask 840h

    - -
    -
    - -

    ◆ DINEP1MSK

    - -
    -
    - - - - -
    __IO uint32_t DINEP1MSK
    -
    -

    dedicated EP mask 844h

    - -
    -
    - -

    ◆ Reserved44

    - -
    -
    - - - - -
    uint32_t Reserved44[15]
    -
    -

    Reserved 844-87Ch

    - -
    -
    - -

    ◆ DOUTEP1MSK

    - -
    -
    - - - - -
    __IO uint32_t DOUTEP1MSK
    -
    -

    dedicated EP msk 884h

    - -
    -
    - -

    ◆ DIEPCTL

    - -
    -
    - - - - -
    __IO uint32_t DIEPCTL
    -
    -

    dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h

    - -
    -
    - -

    ◆ Reserved04 [1/2]

    - -
    -
    - - - - -
    uint32_t Reserved04
    -
    -

    Reserved 900h + (ep_num * 20h) + 04h

    - -
    -
    - -

    ◆ DIEPINT

    - -
    -
    - - - - -
    __IO uint32_t DIEPINT
    -
    -

    dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h

    - -
    -
    - -

    ◆ Reserved0C [2/3]

    - -
    -
    - - - - -
    uint32_t Reserved0C
    -
    -

    Reserved 900h + (ep_num * 20h) + 0Ch

    - -
    -
    - -

    ◆ DIEPTSIZ

    - -
    -
    - - - - -
    __IO uint32_t DIEPTSIZ
    -
    -

    IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h

    - -
    -
    - -

    ◆ DIEPDMA

    - -
    -
    - - - - -
    __IO uint32_t DIEPDMA
    -
    -

    IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h

    - -
    -
    - -

    ◆ DTXFSTS

    - -
    -
    - - - - -
    __IO uint32_t DTXFSTS
    -
    -

    IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h

    - -
    -
    - -

    ◆ Reserved18 [1/2]

    - -
    -
    - - - - -
    uint32_t Reserved18
    -
    -

    Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch

    - -
    -
    - -

    ◆ DOEPCTL

    - -
    -
    - - - - -
    __IO uint32_t DOEPCTL
    -
    -

    dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h

    - -
    -
    - -

    ◆ Reserved04 [2/2]

    - -
    -
    - - - - -
    uint32_t Reserved04
    -
    -

    Reserved B00h + (ep_num * 20h) + 04h

    - -
    -
    - -

    ◆ DOEPINT

    - -
    -
    - - - - -
    __IO uint32_t DOEPINT
    -
    -

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    - - diff --git a/DOCS/html/group___c_m_s_i_s___device.map b/DOCS/html/group___c_m_s_i_s___device.map deleted file mode 100644 index a17e9f9..0000000 --- a/DOCS/html/group___c_m_s_i_s___device.map +++ /dev/null @@ -1,4 +0,0 @@ - - - - diff --git a/DOCS/html/group___c_m_s_i_s___device.md5 b/DOCS/html/group___c_m_s_i_s___device.md5 deleted file mode 100644 index 5848773..0000000 --- a/DOCS/html/group___c_m_s_i_s___device.md5 +++ /dev/null @@ -1 +0,0 @@ -33eaf1b5bada71581eb1b67a841aedc6 \ No newline at end of file diff --git a/DOCS/html/group___c_m_s_i_s___device.png b/DOCS/html/group___c_m_s_i_s___device.png deleted file mode 100644 index 09ada90229daf7e58faeed4a75b2db83b611985b..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 1158 zcmV;11bO?3P)DR^F#b zp69*vUGBH3u3T>_x9P|9yiEOFreI0KG~itlM|Hruw)bsQWlBP!2Kqn~#v1S*@CooP zaP7Q&G^^0+05p}?9plsYvaG4DEiT)0v?ZGug1j(H11rli$tX z<452Q@GQk=ke&&7q9Ld*@yj!OxvW}VcS+#Fbk5~t-(*v_BB^`aRM$n&J&lm6$;D>i z`?T?4dnxAIM~MDQUZeQzz#ZTf;9nlECbi*XqFD~^@}G6bEiIEl+u-qO6N>Hgs%sn4!NI{Bz+K?=N|o&;$nQY|a&UTj z>fFXOz}p6iDY@A8-?oQh5_**p%V=hrx>-1M8(V$vb9C*0YisN0!^6XGDDH&Z243aj zDx)<7;H*;+p4QjbJAFF0>*lAAn1i}$CDF%Ww3@=^7pCl^91VuSBllfU5d+; z+rVeQ3&4Lg?_>M`{1GAuS8Ho)PRGZdg>BAXx36Lox9tkX^-hnkARD1Ro0~pM_!w+r ztnQ=uCOn@y2fqMc051Y>0bc=s135(k5rekPL)*c)ynR}}jXIRe4OhWd8lg8K>uz=0 zBqEnKRn_)3cYu8F=+yPm^M>vM`04!TbKo7|W8i%ruRKQc9t~LC2rZYF`OLPazMJmK zn9kef9Bsp1y=QYJ3G0)geSi9FX7pn&1M(AxocE2iuCFq;9H87$4kIpal?_J8qM945SsP|hQ7CQ z$sWcIK!)o|B@HD8k?wSPA|g(dG(^OSl7@&lQPL0*C$$@)M@L7O8HdOP`}_M(#DDrU zX2-|J#`2Y - - - - - - -STM MATLAB Simulator: Floating Point Unit (FPU) - - - - - - - - - - - -
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    -Topics | -Data Structures | -Macros
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    Floating Point Unit (FPU)
    Defines and Type Definitions » Status and Control Registers » Nested Vectored Interrupt Controller (NVIC) » System Control Block (SCB) » System Controls not in SCB (SCnSCB) » System Tick Timer (SysTick) » Instrumentation Trace Macrocell (ITM) » Data Watchpoint and Trace (DWT) » Trace Port Interface (TPI)
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    Type definitions for the Floating Point Unit (FPU) -More...

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    - + Collaboration diagram for Floating Point Unit (FPU):
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    -Topics

     Core Debug Registers (CoreDebug)
     Type definitions for the Core Debug Registers.
     
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    -Data Structures

    struct  FPU_Type
     Structure type to access the Floating Point Unit (FPU). More...
     
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    -Macros

    #define FPU_FPCCR_ASPEN_Pos   31U
     
    #define FPU_FPCCR_ASPEN_Msk   (1UL << FPU_FPCCR_ASPEN_Pos)
     
    #define FPU_FPCCR_LSPEN_Pos   30U
     
    #define FPU_FPCCR_LSPEN_Msk   (1UL << FPU_FPCCR_LSPEN_Pos)
     
    #define FPU_FPCCR_MONRDY_Pos   8U
     
    #define FPU_FPCCR_MONRDY_Msk   (1UL << FPU_FPCCR_MONRDY_Pos)
     
    #define FPU_FPCCR_BFRDY_Pos   6U
     
    #define FPU_FPCCR_BFRDY_Msk   (1UL << FPU_FPCCR_BFRDY_Pos)
     
    #define FPU_FPCCR_MMRDY_Pos   5U
     
    #define FPU_FPCCR_MMRDY_Msk   (1UL << FPU_FPCCR_MMRDY_Pos)
     
    #define FPU_FPCCR_HFRDY_Pos   4U
     
    #define FPU_FPCCR_HFRDY_Msk   (1UL << FPU_FPCCR_HFRDY_Pos)
     
    #define FPU_FPCCR_THREAD_Pos   3U
     
    #define FPU_FPCCR_THREAD_Msk   (1UL << FPU_FPCCR_THREAD_Pos)
     
    #define FPU_FPCCR_USER_Pos   1U
     
    #define FPU_FPCCR_USER_Msk   (1UL << FPU_FPCCR_USER_Pos)
     
    #define FPU_FPCCR_LSPACT_Pos   0U
     
    #define FPU_FPCCR_LSPACT_Msk   (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)
     
    #define FPU_FPCAR_ADDRESS_Pos   3U
     
    #define FPU_FPCAR_ADDRESS_Msk   (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)
     
    #define FPU_FPDSCR_AHP_Pos   26U
     
    #define FPU_FPDSCR_AHP_Msk   (1UL << FPU_FPDSCR_AHP_Pos)
     
    #define FPU_FPDSCR_DN_Pos   25U
     
    #define FPU_FPDSCR_DN_Msk   (1UL << FPU_FPDSCR_DN_Pos)
     
    #define FPU_FPDSCR_FZ_Pos   24U
     
    #define FPU_FPDSCR_FZ_Msk   (1UL << FPU_FPDSCR_FZ_Pos)
     
    #define FPU_FPDSCR_RMode_Pos   22U
     
    #define FPU_FPDSCR_RMode_Msk   (3UL << FPU_FPDSCR_RMode_Pos)
     
    #define FPU_MVFR0_FP_rounding_modes_Pos   28U
     
    #define FPU_MVFR0_FP_rounding_modes_Msk   (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)
     
    #define FPU_MVFR0_Short_vectors_Pos   24U
     
    #define FPU_MVFR0_Short_vectors_Msk   (0xFUL << FPU_MVFR0_Short_vectors_Pos)
     
    #define FPU_MVFR0_Square_root_Pos   20U
     
    #define FPU_MVFR0_Square_root_Msk   (0xFUL << FPU_MVFR0_Square_root_Pos)
     
    #define FPU_MVFR0_Divide_Pos   16U
     
    #define FPU_MVFR0_Divide_Msk   (0xFUL << FPU_MVFR0_Divide_Pos)
     
    #define FPU_MVFR0_FP_excep_trapping_Pos   12U
     
    #define FPU_MVFR0_FP_excep_trapping_Msk   (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)
     
    #define FPU_MVFR0_Double_precision_Pos   8U
     
    #define FPU_MVFR0_Double_precision_Msk   (0xFUL << FPU_MVFR0_Double_precision_Pos)
     
    #define FPU_MVFR0_Single_precision_Pos   4U
     
    #define FPU_MVFR0_Single_precision_Msk   (0xFUL << FPU_MVFR0_Single_precision_Pos)
     
    #define FPU_MVFR0_A_SIMD_registers_Pos   0U
     
    #define FPU_MVFR0_A_SIMD_registers_Msk   (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)
     
    #define FPU_MVFR1_FP_fused_MAC_Pos   28U
     
    #define FPU_MVFR1_FP_fused_MAC_Msk   (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)
     
    #define FPU_MVFR1_FP_HPFP_Pos   24U
     
    #define FPU_MVFR1_FP_HPFP_Msk   (0xFUL << FPU_MVFR1_FP_HPFP_Pos)
     
    #define FPU_MVFR1_D_NaN_mode_Pos   4U
     
    #define FPU_MVFR1_D_NaN_mode_Msk   (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)
     
    #define FPU_MVFR1_FtZ_mode_Pos   0U
     
    #define FPU_MVFR1_FtZ_mode_Msk   (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)
     
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    Detailed Description

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    Type definitions for the Floating Point Unit (FPU)

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    Macro Definition Documentation

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    ◆ FPU_FPCCR_ASPEN_Pos

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    #define FPU_FPCCR_ASPEN_Pos   31U
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    FPCCR: ASPEN bit Position

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    #define FPU_FPCCR_LSPEN_Pos   30U
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    FPCCR: MONRDY Position

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    ◆ FPU_MVFR0_FP_rounding_modes_Pos

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    #define FPU_MVFR0_FP_rounding_modes_Msk   (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)
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    #define FPU_MVFR0_Divide_Msk   (0xFUL << FPU_MVFR0_Divide_Pos)
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    #define FPU_MVFR0_FP_excep_trapping_Msk   (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)
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    ◆ FPU_MVFR0_Double_precision_Pos

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    #define FPU_MVFR0_Double_precision_Msk   (0xFUL << FPU_MVFR0_Double_precision_Pos)
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    #define FPU_MVFR0_Single_precision_Msk   (0xFUL << FPU_MVFR0_Single_precision_Pos)
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    MVFR0: Single-precision bits Mask

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    ◆ FPU_MVFR0_A_SIMD_registers_Pos

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    #define FPU_MVFR0_A_SIMD_registers_Pos   0U
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    MVFR0: A_SIMD registers bits Position

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    #define FPU_MVFR0_A_SIMD_registers_Msk   (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)
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    MVFR0: A_SIMD registers bits Mask

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    ◆ FPU_MVFR1_FP_fused_MAC_Pos

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    #define FPU_MVFR1_FP_fused_MAC_Pos   28U
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    MVFR1: FP fused MAC bits Position

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    #define FPU_MVFR1_FP_fused_MAC_Msk   (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)
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    #define FPU_MVFR1_FP_HPFP_Msk   (0xFUL << FPU_MVFR1_FP_HPFP_Pos)
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    ◆ FPU_MVFR1_D_NaN_mode_Pos

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    #define FPU_MVFR1_D_NaN_mode_Msk   (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)
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    MVFR1: D_NaN mode bits Mask

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    ◆ FPU_MVFR1_FtZ_mode_Pos

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    #define FPU_MVFR1_FtZ_mode_Pos   0U
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    MVFR1: FtZ mode bits Position

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    ◆ FPU_MVFR1_FtZ_mode_Msk

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    #define FPU_MVFR1_FtZ_mode_Msk   (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)
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    MVFR1: FtZ mode bits Mask

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    -Generated by doxygen 1.10.0 -
    - - diff --git a/DOCS/html/group___c_m_s_i_s___f_p_u.map b/DOCS/html/group___c_m_s_i_s___f_p_u.map deleted file mode 100644 index 95837e8..0000000 --- a/DOCS/html/group___c_m_s_i_s___f_p_u.map +++ /dev/null @@ -1,5 +0,0 @@ - - - - - diff --git a/DOCS/html/group___c_m_s_i_s___f_p_u.md5 b/DOCS/html/group___c_m_s_i_s___f_p_u.md5 deleted file mode 100644 index 4abfb86..0000000 --- a/DOCS/html/group___c_m_s_i_s___f_p_u.md5 +++ /dev/null @@ -1 +0,0 @@ -17e98aaae6d27a20688ecf2eb61ec177 \ No newline at end of file diff --git a/DOCS/html/group___c_m_s_i_s___f_p_u.png b/DOCS/html/group___c_m_s_i_s___f_p_u.png deleted file mode 100644 index 2bc6ce813f4d7c207698c144e2f50d7069ca085b..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 2320 zcmZvedpHyR7snT3WGX2lQ*w)k+ zTeVz5TSK{I=9&$;{`C9(_4_@)bDrmO&iS0@JkR@|^Sn;HmBl5Hn5-B8001EoCN=(%jDk1;?KswUI$SyQ{mW_IJ#8eu03rUs>8{ES$Wzwb^fL`QXui z8)C(Tqgsxx|7{{=DjhC#+%0}=HH5`tMJ~!;k|%VIr_9T=HTU@70(6ON-p*GahgUxl z_{VzW4kGf?uO+=c1}r^7F(H4CwNz7&1wyheBg#YMDiHT%PfK7uRRaBYrhDRdjaq^; zPyQkA#=YK3ZQ`fzaf(Jniz3=ZAIy1hbyd|51Mx-AkdO?z`wxRBW}kBnM;uY@Vir;(lY69!H#Dp(rjOcORswa2Us6; zS;?ik^?sY!x7FqAPj%PDq-9k>Tm_oH!EufBhBM3!4619I2?t9K%G)&@z+H7Ad~Pt8 zUkm$l`RK<2RuY9pz&SZ#8JJ~x6)$hjG_8jty8qd(j_H`6`kF^h-Tf4@Y2&1UY@L32 z-B3SYEsWO@hR?wUdvvP@z$QyqQC+BJ!%b?Legj!+q5}uT^G<)GtexZ5^Op0q`{t|V zn~_&2V;v>ON#L?4*DZ%@r^(C3Gc~BxGzTfio^9^iiQuu1Bu2sJtzOILZ38A_eFq8$ zs=wzSBR8SzfEBaOI%HS!))bnCg4h?Q}e;m`2q`uN*+VO^1|+!M9JzE6k0Y znsi9P*H6nORL06XCsV>qZ6f}}@+#QOUiGAIz0alaT2$dkFY!aBg<98Ise0$7v_R5A z3d9qX^IYu2{^IuoU!|BC>~tNT)=%5MJb&p~LVWbGToi$^T$Fe6F$lupmU6AAfx0$r>0Xb$f3k#?=W z`xoT=+sJj#s`|pY6pvFseQ;dZ=o7B~61pi&2b|Q7!C+R!-etDXs_s`eHg>yL)xmQa zT8F4JqA4*ek6Tou9=3G0V&?@1qXM8HNV})@J^!GfCAyVaMnl0YiEi8o#d>=`{1g7U z#((hX1aR2W5>b&2fD3L&u8J&Zj4ml1zoGhNaWV!9;(}EVqgFu+-lOX+XCJaGCaIU8 zrL(r*@UUPBaK(${VVPahQRXcf2-)x3w{e)91*t*TA@HO^@!nmzyJ=?H#)rya@X<4x zRWB#{s>%ijRg^(CtVB7z7a|cCv|}1SkJm8))J2z~H&v}a==SZ~l0(9p z1SN?xhl{X5CM|jr3T2JK+yMn$Jw3dgd;!H^4z4W5O@$z^j*gD=n1F!oC!T>r8cMIk z=RKA`&E&QmeE8!a^!_qt7%hG{*|x|6Cgi+30;L`BS`>UY`L!XYL7raKLDwUdl;DOYy#?Lb?a^bTiKh6umQGRQ? zZ%TY)26FOOn^ODj;i=Z#1>BL`b3v0SNnu_?!nu%C)b$gNhEz`06zsRlmf?dT0cVxW zd*y#XPs_@mcMzo0Gs$7K}4i4OKX#yCyZWjS-> z#_J5l{w=pJkpPG0x_pxpS&kGnr!_U)uWI?~8B43H7d?*nM9Sj;umD{gOun=91BF z$0QRB1x9wi5c(`=D7-bNlYhZ0I6e3f+An{0ZOyY1c~Q>cg~UgXEwkPsxS$WSb~n6v zmUSJkZPhG7L!}5sGJ;O#crynk6UWQJoL__6r^2vbuRrcmOL#rC?XVcfG!$Rs#f0+9 z=K*W#>}M+*QvX<*k5S3Jt$lnWTJTMg{xknV` z!_|y|l9LMy@&uHDy&{+Q6(nJB9r&q!C)>Z67}m-0zBy)|Lz79Dn=wJ`@4U%PXDd38 z<2X*G(N>hEX)KjE-K`d9CTlV-!xl0}YuD%5rV-(3O}cEi!8cj~jy>pDJ~pdwUmcaM zQ*v^~ZaK?JdOrDffwV(Ob)_wP(2r+y#SZI_awZIN>`%P%#TT-cD6ve#DPGJDtOW5g z4hT71?`UA1TK`F#_hTN{KUqnBk0 zO7bZ2S1n%0xPCeQZ}M6EU-HE#XH6;LL$WM+=S|gWO%2bE^63&feOJ zn4@?gTYVr6wP?+X5gMN5Yb8nBK|3QvJeYnbeDhtj2(5J=!|YWLYUE76j%?zsx!KvO k+S*?RQv3hcDz-$T@()b+EneX7oHziasf9_ovFkto0=(IlC;$Ke diff --git a/DOCS/html/group___c_m_s_i_s___i_t_m.html b/DOCS/html/group___c_m_s_i_s___i_t_m.html deleted file mode 100644 index 26f9261..0000000 --- a/DOCS/html/group___c_m_s_i_s___i_t_m.html +++ /dev/null @@ -1,665 +0,0 @@ - - - - - - - -STM MATLAB Simulator: Instrumentation Trace Macrocell (ITM) - - - - - - - - - - - -
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    -Topics | -Data Structures | -Macros
    -
    Instrumentation Trace Macrocell (ITM)
    Defines and Type Definitions » Status and Control Registers » Nested Vectored Interrupt Controller (NVIC) » System Control Block (SCB) » System Controls not in SCB (SCnSCB) » System Tick Timer (SysTick)
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    Type definitions for the Instrumentation Trace Macrocell (ITM) -More...

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    - + Collaboration diagram for Instrumentation Trace Macrocell (ITM):
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    -Topics

     Data Watchpoint and Trace (DWT)
     Type definitions for the Data Watchpoint and Trace (DWT)
     
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    -Data Structures

    struct  ITM_Type
     Structure type to access the Instrumentation Trace Macrocell Register (ITM). More...
     
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    -Macros

    #define ITM_TPR_PRIVMASK_Pos   0U
     
    #define ITM_TPR_PRIVMASK_Msk   (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/)
     
    #define ITM_TCR_BUSY_Pos   23U
     
    #define ITM_TCR_BUSY_Msk   (1UL << ITM_TCR_BUSY_Pos)
     
    #define ITM_TCR_TraceBusID_Pos   16U
     
    #define ITM_TCR_TraceBusID_Msk   (0x7FUL << ITM_TCR_TraceBusID_Pos)
     
    #define ITM_TCR_GTSFREQ_Pos   10U
     
    #define ITM_TCR_GTSFREQ_Msk   (3UL << ITM_TCR_GTSFREQ_Pos)
     
    #define ITM_TCR_TSPrescale_Pos   8U
     
    #define ITM_TCR_TSPrescale_Msk   (3UL << ITM_TCR_TSPrescale_Pos)
     
    #define ITM_TCR_SWOENA_Pos   4U
     
    #define ITM_TCR_SWOENA_Msk   (1UL << ITM_TCR_SWOENA_Pos)
     
    #define ITM_TCR_DWTENA_Pos   3U
     
    #define ITM_TCR_DWTENA_Msk   (1UL << ITM_TCR_DWTENA_Pos)
     
    #define ITM_TCR_SYNCENA_Pos   2U
     
    #define ITM_TCR_SYNCENA_Msk   (1UL << ITM_TCR_SYNCENA_Pos)
     
    #define ITM_TCR_TSENA_Pos   1U
     
    #define ITM_TCR_TSENA_Msk   (1UL << ITM_TCR_TSENA_Pos)
     
    #define ITM_TCR_ITMENA_Pos   0U
     
    #define ITM_TCR_ITMENA_Msk   (1UL /*<< ITM_TCR_ITMENA_Pos*/)
     
    #define ITM_IWR_ATVALIDM_Pos   0U
     
    #define ITM_IWR_ATVALIDM_Msk   (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)
     
    #define ITM_IRR_ATREADYM_Pos   0U
     
    #define ITM_IRR_ATREADYM_Msk   (1UL /*<< ITM_IRR_ATREADYM_Pos*/)
     
    #define ITM_IMCR_INTEGRATION_Pos   0U
     
    #define ITM_IMCR_INTEGRATION_Msk   (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)
     
    #define ITM_LSR_ByteAcc_Pos   2U
     
    #define ITM_LSR_ByteAcc_Msk   (1UL << ITM_LSR_ByteAcc_Pos)
     
    #define ITM_LSR_Access_Pos   1U
     
    #define ITM_LSR_Access_Msk   (1UL << ITM_LSR_Access_Pos)
     
    #define ITM_LSR_Present_Pos   0U
     
    #define ITM_LSR_Present_Msk   (1UL /*<< ITM_LSR_Present_Pos*/)
     
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    Detailed Description

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    Type definitions for the Instrumentation Trace Macrocell (ITM)

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    Macro Definition Documentation

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    ◆ ITM_TPR_PRIVMASK_Pos

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    #define ITM_TPR_PRIVMASK_Pos   0U
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    ITM TPR: PRIVMASK Position

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    ◆ ITM_TPR_PRIVMASK_Msk

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    #define ITM_TPR_PRIVMASK_Msk   (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/)
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    ITM TPR: PRIVMASK Mask

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    ◆ ITM_TCR_BUSY_Pos

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    #define ITM_TCR_BUSY_Pos   23U
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    ITM TCR: BUSY Position

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    ◆ ITM_TCR_BUSY_Msk

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    #define ITM_TCR_BUSY_Msk   (1UL << ITM_TCR_BUSY_Pos)
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    ITM TCR: BUSY Mask

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    ◆ ITM_TCR_TraceBusID_Pos

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    #define ITM_TCR_TraceBusID_Pos   16U
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    ITM TCR: ATBID Position

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    ◆ ITM_TCR_TraceBusID_Msk

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    #define ITM_TCR_TraceBusID_Msk   (0x7FUL << ITM_TCR_TraceBusID_Pos)
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    ITM TCR: ATBID Mask

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    ◆ ITM_TCR_GTSFREQ_Pos

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    #define ITM_TCR_GTSFREQ_Pos   10U
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    ITM TCR: Global timestamp frequency Position

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    ◆ ITM_TCR_GTSFREQ_Msk

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    ITM TCR: Global timestamp frequency Mask

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    ◆ ITM_TCR_TSPrescale_Pos

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    ITM TCR: TSPrescale Position

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    ◆ ITM_TCR_TSPrescale_Msk

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    #define ITM_TCR_TSPrescale_Msk   (3UL << ITM_TCR_TSPrescale_Pos)
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    ITM TCR: TSPrescale Mask

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    ITM TCR: SWOENA Position

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    #define ITM_TCR_SWOENA_Msk   (1UL << ITM_TCR_SWOENA_Pos)
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    ITM TCR: SWOENA Mask

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    ◆ ITM_TCR_DWTENA_Pos

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    ITM TCR: DWTENA Position

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    #define ITM_TCR_DWTENA_Msk   (1UL << ITM_TCR_DWTENA_Pos)
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    ITM TCR: DWTENA Mask

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    ITM TCR: SYNCENA Position

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    ◆ ITM_TCR_SYNCENA_Msk

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    ITM TCR: SYNCENA Mask

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    ITM TCR: TSENA Position

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    ITM TCR: TSENA Mask

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    #define ITM_TCR_ITMENA_Pos   0U
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    ITM TCR: ITM Enable bit Position

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    #define ITM_TCR_ITMENA_Msk   (1UL /*<< ITM_TCR_ITMENA_Pos*/)
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    ITM TCR: ITM Enable bit Mask

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    ◆ ITM_IWR_ATVALIDM_Pos

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    #define ITM_IWR_ATVALIDM_Pos   0U
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    ITM IWR: ATVALIDM Position

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    ITM IMCR: INTEGRATION Position

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    ITM IMCR: INTEGRATION Mask

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    ITM LSR: ByteAcc Position

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    ITM LSR: ByteAcc Mask

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    ITM LSR: Access Position

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    ITM LSR: Access Mask

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    ITM LSR: Present Position

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    ITM LSR: Present Mask

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    -Generated by doxygen 1.10.0 -
    - - diff --git a/DOCS/html/group___c_m_s_i_s___i_t_m.map b/DOCS/html/group___c_m_s_i_s___i_t_m.map deleted file mode 100644 index b3e2087..0000000 --- a/DOCS/html/group___c_m_s_i_s___i_t_m.map +++ /dev/null @@ -1,5 +0,0 @@ - - - - - diff --git a/DOCS/html/group___c_m_s_i_s___i_t_m.md5 b/DOCS/html/group___c_m_s_i_s___i_t_m.md5 deleted file mode 100644 index c755c55..0000000 --- a/DOCS/html/group___c_m_s_i_s___i_t_m.md5 +++ /dev/null @@ -1 +0,0 @@ -a6a464b5c93a384e95479517ab527a4a \ No newline at end of file diff --git a/DOCS/html/group___c_m_s_i_s___i_t_m.png b/DOCS/html/group___c_m_s_i_s___i_t_m.png deleted file mode 100644 index 3dfd9fe29c86ce3adeb1840bb5d53c948a4c4ccd..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 2462 zcmZvedpy&N8^^!O{XRw|BqWlFv?KQ%ti3REYDi{IIOTquMsv&EI-*v&Z@J&;xb3vH zk;pBVl4)~o(#2e6oz$8*`u%xczvp?qp3Cd`{PXZgsQIH6(bg@A}5ds~%P7 z9+ewq(vKaFfS9-@z`gZ5T(cKqb_GbDjf#@mVD+?*z5HX{fyC&+=EVYuwR-x!-ZaG{ zZF;r7vbPK%%};sE*Y8x6@Kb4|Y%9yVe>mxk{<$T*Db~94Vq14(Y;puSi__6b+p+(<{0-`nWJ${ zx?uFq!1YA_NTBCbVEYb(tMfI%%>~O*rgX;pEVm`tUM)EvT7aE-53#sGG)3b+HpJ3y zPl_7HD}wHHRs8z3o}_5`_UI?Ga>ZRWV+#y(OWG-}&;fd6Ns_5`R z7ZY8wZVon%;pOY=IbR!GNn00O^M<_-?O0~?mrpL3 z-LGdeMmVpVD-EDCO+I|Z(}P{VBKz^I{0Cz~ZM~8h<>HkH@AUD7?gn-IgF)3-$iGj{UV>rk#|5!Gs!HdheXzf(? zCiJ)p(@CE|M3zdLOhmtWiLGEK)b%CO*6nBry@1%l2crQM)>DYuAj`5b=UHaQQo9Px z;PP_u*jvBe3F|Vb6Ylb*U3bdtJp?|a(sixD+S6eAI@xaxl4m*x5}5HzBAp(CCyWqq;SeITsc>6R2L!-#mz?k5sNu^GBtKi81J8jl3&D)szJhb0D%e z>SP)3ugOjjF>e4>ZNQ{{vDW+m2W-W7Fu-=b@fD=bXKC7?5sun@X|`ZT(fB7Y-7(8J z3TtZ6{$w^_mntlqK>%USok^4Us+q{daM1;T7XuUkPttGdDP`0+YsTuRav11-WUV^p zvHGP@)BuOm=7w&H-TX&AM0U{;=oWt@x45~qj7NI}mxTJ3*3F6!ea~ps0j=q`^Hti{~zijTpbm{apXiY>bE{6JQ}nQNn3?*$+!{mIJ& zxgLMOBhI`iPP8WtvA_9Idpj|A!2eGtodZ*oDJNBBP8N*(Fmt5@L-FE0swpD?NtCCO z0(0hK#CRXpE1IBX2wRei-T`~HoBYw5t-#L$^`PP_I2_I>`D4IudSUkt_MCkO?>h!8 zh(;d4{8E~xS)`?8CAX-Zq5&)nJcIXDst6V3>?5QyLcOw6w`BRE916hL4=wF@OcIS0 z5gg0?ke_@2q1n2Gy9srQkP=hQ`Q6;y{M*qK9I$QYRn3l^ryRaRt*q4XL`?#7j6`7+ zkSr0Yso)lAYp~!yN^X*c#1+W1+OVf=r{2wYda^3m^=1xb?=+6=W_dFkZ_8uo2{DP(-$sdNBEUUREiUBkDHw zE8A9FaC5zoPT=f`=erwbqc4$2-N``QVL@HL4A262X|@W7-CgE?3kpGlA{5Six=Ju@ z=nAvgL4MEiQrCRh`2i_p?XgPFS}5bMGwWy|$u?EiLJAkK*TOHNHW}e%V_jh@T82BgZEd+W=Q-%KyXCpt$ieLCj(~1U%vhu_ zuGoMmrF4I{xTVDZ;RVts26T&CJS?af{oNvYbon&7fpplkkKw1N1J<5{WqF0_8Y45GYOmLxLDGhNlR=p+mU}QO| zxaKn5BXkIB@gvT($S2bJJ9r<4eHFtg{7F?XjYbO*Jaa!bMAvA9n^}QHJ#j zhkT3jOhBxO0R==NkVkwdlPz3Nl~u`~ zAQq(kUmhcd-vu03tFXka|Bvly`*2w7JBxH?`23Th>!gl3I-U|e=WP!f*leB(?o9si z{R<+k;#7ZB!bq%aP20(tZrlcmd+M4N$DHxrLi|FMI>yq - - - - - - -STM MATLAB Simulator: Nested Vectored Interrupt Controller (NVIC) - - - - - - - - - - - -
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    Nested Vectored Interrupt Controller (NVIC)
    Defines and Type Definitions » Status and Control Registers
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    Type definitions for the NVIC Registers. -More...

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    -Topics

     System Control Block (SCB)
     Type definitions for the System Control Block Registers.
     
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    -Data Structures

    struct  NVIC_Type
     Structure type to access the Nested Vectored Interrupt Controller (NVIC). More...
     
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    -Macros

    #define NVIC_STIR_INTID_Pos   0U
     
    #define NVIC_STIR_INTID_Msk   (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)
     
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    Detailed Description

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    Type definitions for the NVIC Registers.

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    Macro Definition Documentation

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    ◆ NVIC_STIR_INTID_Pos

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    #define NVIC_STIR_INTID_Pos   0U
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    STIR: INTLINESNUM Position

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    ◆ NVIC_STIR_INTID_Msk

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    #define NVIC_STIR_INTID_Msk   (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)
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    STIR: INTLINESNUM Mask

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    -Generated by doxygen 1.10.0 -
    - - diff --git a/DOCS/html/group___c_m_s_i_s___n_v_i_c.map b/DOCS/html/group___c_m_s_i_s___n_v_i_c.map deleted file mode 100644 index 7af7a8d..0000000 --- a/DOCS/html/group___c_m_s_i_s___n_v_i_c.map +++ /dev/null @@ -1,5 +0,0 @@ - - - - - diff --git a/DOCS/html/group___c_m_s_i_s___n_v_i_c.md5 b/DOCS/html/group___c_m_s_i_s___n_v_i_c.md5 deleted file mode 100644 index 7654f8e..0000000 --- a/DOCS/html/group___c_m_s_i_s___n_v_i_c.md5 +++ /dev/null @@ -1 +0,0 @@ -3462f04095f544804a3d76d775b9de53 \ No newline at end of file diff --git a/DOCS/html/group___c_m_s_i_s___n_v_i_c.png b/DOCS/html/group___c_m_s_i_s___n_v_i_c.png deleted file mode 100644 index 98c85372ffd1488268f8112afb34be529ca7858e..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 2514 zcmaJ@X*kpi7ynO~iMsZEA4H2ip|RB%##qKWvXiJwqwExuDYtBq8d;iz$vQGJmWd)F zlW{F;!Gl5GZ&xYpNwpZCjqKfJ&5Jm+`LmvcUx=lsq|b3!A36Oa`E0N^*24Z;Ng z4rv|4XAXl8eC8Uv=77L~c1Q%U|F;#lRuBMyKLv$2?-u`*J8pMh9w`G^Npke#J)3Ip zG^wnki+p+q~F26Mw-mZGwl*mjwUz#eUE3Fq>t73KbtRGZZ6hgPv?r6L3 zm}+CA==r+{M3ZZ5tRFFHA2nC_YTOm$JM24-8Q$GTsV0;sklW_DRa@m`B|zjKc<4`> zJaT2=nVG27M}Db}?4(Zytqt|{YdRwlZh8gwhQ9Q3rI&Q2ISv&=y_Bg+m8_|$-kHeG z7d_laB6n}{h_iTMDrwHg1nLa*10L)Mc>8WXyv|2E4)iou0V&ZtvpRe{9o?Lj z468B?@hm`B^xcDh&6paEIoz0Ot$H-Ya^#{gs&6(*Q}W2jMP?*tv<}@MHJ!r3-cv*U z(F@k1!x0FC8$Ur(MMXv6(Ep)3jitxZNsY)0^NEH^v}DJ+O`BLoxll!4BfePRm>D+CY!sGQ84%9l!03kBFW z;$$7X+>@BYN-hRRG4jtuYrG8;gY^*?4As<6RV)byL_lgqGeX(o{%c_$s8=VA_c$f> z*!BI%E!fN-!nMEes+)VaDH4A$_OvMe$H1Qm*Hx<<{!-tykH9%^dv2U&R=wRk>(jJG zz8QV#rOfl6`g`i>GUb{)T1z>kSyBv!!8qe-wC}T?BuDO2VH;9CtOlyaLVv;yZJm8` zleE3nPrA~cQqeD8a11AFysiv)m3g?2$6F1Ab)8#eY-Q-H<5EIQh!5!2?DhGBGo)VXeptc|v4C zKGXHH|Fjs9impX(Yi!*fSC`@@y3!jO9=-%}t-aEtPh-607;0B%bNJ^6Wx||Wb@qMU ze|CeL`#Fzkmun{GtN(z4T}~^o0*FfY%9~z4E-kY)JSOW!Cinkz@-}uD(jo_S1u;r$ z{5jgz;6&-n6)3nRFSBVdD73UMHjlgGYgoZrePf(ZiC%SDZ*@4PNh)blT>9V-UWo#d zA{1;CTCRwu33k6AEmh)|^dz(?8IzrojHf)B*cRN|1=^*EnJ(9^UOlCdX)P_7LV*_xQVVnb{Cndv z#??^hQ|@xA+vis-0ZSk*eEC8D6_5{AGUs+rP~U`nUU8|NfhCkQ3bot%gBO~2Yb;J4vFS3sw6oK7X zoo1VunAGxYe(jjj8#7^$RxJRFYr3Xoohd@SS?{5%jPCAkbNom)j_wCui2-OJ(^Ai_ zT43jS!5lM7(M*A2OeBL~wc0vUq>#5_B<_<|t34AFcOpr0mOK3HOz z;)8K;dv5{S`92XL&f4H0fwuHjC4uGkkGEeTv*cOP&N}M^sgV%9$8S-tVn&&h65?gK zz*n9XSHKb2G^CbJs{%!erZ$9ydv_?KE#L2xv7XK9F^f56EuNQvuaK3ifWKudws#ru zvG9ncJJ{spEo($?s}g2NF)Sm#Ck;T~xWz?GQ`WQPb2QM73`+*#2*mTXzy2UfGzpK_ zv^%_N#Hz=Qiz=A}f9&HYQtX<-h;PvLmV1H|dB8J7Y}#!jP+}^_q?@-J#L5)J>^eu7 z4L8z*f?1qdxCHhS-0v?PyixX?VMuEJPdDMkE_PRXvTBN0R%~6lE=`tFlMH=(56bxez|N&OPV;uqxp*~t_6_-O=(tQ#l>AS9ee+=3a=U`uvf4?a_=Pq1X&OyWEj)T{#TinBj zx}kjgseI;0@;p?3BB6p4g$+*p)+A1Wg&DDNQH2)5MvgJp-pnT~FfY)21c-CWgM%;( z@wxVa4$WhWw6Wd`io+)cgUZEJweax`R%iI0CoCnf4A5<8!U-j`(7JbBltc^}w)kPr zzBxa~TSHR8aNv6g%$;QFx$hjCUf%=#jia>W#fA}jf=;KCqHx=!(~G`R|J4Rm_Qne9 z%NJYZbCG+UC5uis2WTG!izW*OW<4||U!xu!Tx&ZCLeKP0ys5dw=80)*pI=hAx$4XH zGLO_ce*OC8mG!B5zQhzgAS@zsw~U7B4XwPkK6mrG?err@si?J(oV)L)7Y<$LRKud} z?IdvfQ(}!hd5DfY ztnsG#q&Tq~ua1mf$v$IrZ7f^c+s+G|-0?NCd8{>Z#`gJnXX%6V*`hSrb|`w|dmoX~ zseJN`^il2CStaC-fbbhhNlM$>+Z4-#zW+ez_&!LZ3L6*JI#hh{qyZ=^G=c&Txbts= CjI#Uy diff --git a/DOCS/html/group___c_m_s_i_s___s_c_b.html b/DOCS/html/group___c_m_s_i_s___s_c_b.html deleted file mode 100644 index 015a57d..0000000 --- a/DOCS/html/group___c_m_s_i_s___s_c_b.html +++ /dev/null @@ -1,2705 +0,0 @@ - - - - - - - -STM MATLAB Simulator: System Control Block (SCB) - - - - - - - - - - - -
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    Defines and Type Definitions » Status and Control Registers » Nested Vectored Interrupt Controller (NVIC)
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     System Controls not in SCB (SCnSCB)
     Type definitions for the System Control and ID Register not in the SCB.
     
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    struct  SCB_Type
     Structure type to access the System Control Block (SCB). More...
     
    - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

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    #define SCB_CPUID_IMPLEMENTER_Pos   24U
     
    #define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
     
    #define SCB_CPUID_VARIANT_Pos   20U
     
    #define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)
     
    #define SCB_CPUID_ARCHITECTURE_Pos   16U
     
    #define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
     
    #define SCB_CPUID_PARTNO_Pos   4U
     
    #define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)
     
    #define SCB_CPUID_REVISION_Pos   0U
     
    #define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)
     
    #define SCB_ICSR_NMIPENDSET_Pos   31U
     
    #define SCB_ICSR_NMIPENDSET_Msk   (1UL << SCB_ICSR_NMIPENDSET_Pos)
     
    #define SCB_ICSR_PENDSVSET_Pos   28U
     
    #define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)
     
    #define SCB_ICSR_PENDSVCLR_Pos   27U
     
    #define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)
     
    #define SCB_ICSR_PENDSTSET_Pos   26U
     
    #define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)
     
    #define SCB_ICSR_PENDSTCLR_Pos   25U
     
    #define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)
     
    #define SCB_ICSR_ISRPREEMPT_Pos   23U
     
    #define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)
     
    #define SCB_ICSR_ISRPENDING_Pos   22U
     
    #define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)
     
    #define SCB_ICSR_VECTPENDING_Pos   12U
     
    #define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
     
    #define SCB_ICSR_RETTOBASE_Pos   11U
     
    #define SCB_ICSR_RETTOBASE_Msk   (1UL << SCB_ICSR_RETTOBASE_Pos)
     
    #define SCB_ICSR_VECTACTIVE_Pos   0U
     
    #define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)
     
    #define SCB_VTOR_TBLOFF_Pos   7U
     
    #define SCB_VTOR_TBLOFF_Msk   (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)
     
    #define SCB_AIRCR_VECTKEY_Pos   16U
     
    #define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
     
    #define SCB_AIRCR_VECTKEYSTAT_Pos   16U
     
    #define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
     
    #define SCB_AIRCR_ENDIANESS_Pos   15U
     
    #define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)
     
    #define SCB_AIRCR_PRIGROUP_Pos   8U
     
    #define SCB_AIRCR_PRIGROUP_Msk   (7UL << SCB_AIRCR_PRIGROUP_Pos)
     
    #define SCB_AIRCR_SYSRESETREQ_Pos   2U
     
    #define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
     
    #define SCB_AIRCR_VECTCLRACTIVE_Pos   1U
     
    #define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
     
    #define SCB_AIRCR_VECTRESET_Pos   0U
     
    #define SCB_AIRCR_VECTRESET_Msk   (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)
     
    #define SCB_SCR_SEVONPEND_Pos   4U
     
    #define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)
     
    #define SCB_SCR_SLEEPDEEP_Pos   2U
     
    #define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)
     
    #define SCB_SCR_SLEEPONEXIT_Pos   1U
     
    #define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)
     
    #define SCB_CCR_STKALIGN_Pos   9U
     
    #define SCB_CCR_STKALIGN_Msk   (1UL << SCB_CCR_STKALIGN_Pos)
     
    #define SCB_CCR_BFHFNMIGN_Pos   8U
     
    #define SCB_CCR_BFHFNMIGN_Msk   (1UL << SCB_CCR_BFHFNMIGN_Pos)
     
    #define SCB_CCR_DIV_0_TRP_Pos   4U
     
    #define SCB_CCR_DIV_0_TRP_Msk   (1UL << SCB_CCR_DIV_0_TRP_Pos)
     
    #define SCB_CCR_UNALIGN_TRP_Pos   3U
     
    #define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)
     
    #define SCB_CCR_USERSETMPEND_Pos   1U
     
    #define SCB_CCR_USERSETMPEND_Msk   (1UL << SCB_CCR_USERSETMPEND_Pos)
     
    #define SCB_CCR_NONBASETHRDENA_Pos   0U
     
    #define SCB_CCR_NONBASETHRDENA_Msk   (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)
     
    #define SCB_SHCSR_USGFAULTENA_Pos   18U
     
    #define SCB_SHCSR_USGFAULTENA_Msk   (1UL << SCB_SHCSR_USGFAULTENA_Pos)
     
    #define SCB_SHCSR_BUSFAULTENA_Pos   17U
     
    #define SCB_SHCSR_BUSFAULTENA_Msk   (1UL << SCB_SHCSR_BUSFAULTENA_Pos)
     
    #define SCB_SHCSR_MEMFAULTENA_Pos   16U
     
    #define SCB_SHCSR_MEMFAULTENA_Msk   (1UL << SCB_SHCSR_MEMFAULTENA_Pos)
     
    #define SCB_SHCSR_SVCALLPENDED_Pos   15U
     
    #define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
     
    #define SCB_SHCSR_BUSFAULTPENDED_Pos   14U
     
    #define SCB_SHCSR_BUSFAULTPENDED_Msk   (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)
     
    #define SCB_SHCSR_MEMFAULTPENDED_Pos   13U
     
    #define SCB_SHCSR_MEMFAULTPENDED_Msk   (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)
     
    #define SCB_SHCSR_USGFAULTPENDED_Pos   12U
     
    #define SCB_SHCSR_USGFAULTPENDED_Msk   (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)
     
    #define SCB_SHCSR_SYSTICKACT_Pos   11U
     
    #define SCB_SHCSR_SYSTICKACT_Msk   (1UL << SCB_SHCSR_SYSTICKACT_Pos)
     
    #define SCB_SHCSR_PENDSVACT_Pos   10U
     
    #define SCB_SHCSR_PENDSVACT_Msk   (1UL << SCB_SHCSR_PENDSVACT_Pos)
     
    #define SCB_SHCSR_MONITORACT_Pos   8U
     
    #define SCB_SHCSR_MONITORACT_Msk   (1UL << SCB_SHCSR_MONITORACT_Pos)
     
    #define SCB_SHCSR_SVCALLACT_Pos   7U
     
    #define SCB_SHCSR_SVCALLACT_Msk   (1UL << SCB_SHCSR_SVCALLACT_Pos)
     
    #define SCB_SHCSR_USGFAULTACT_Pos   3U
     
    #define SCB_SHCSR_USGFAULTACT_Msk   (1UL << SCB_SHCSR_USGFAULTACT_Pos)
     
    #define SCB_SHCSR_BUSFAULTACT_Pos   1U
     
    #define SCB_SHCSR_BUSFAULTACT_Msk   (1UL << SCB_SHCSR_BUSFAULTACT_Pos)
     
    #define SCB_SHCSR_MEMFAULTACT_Pos   0U
     
    #define SCB_SHCSR_MEMFAULTACT_Msk   (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)
     
    #define SCB_CFSR_USGFAULTSR_Pos   16U
     
    #define SCB_CFSR_USGFAULTSR_Msk   (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)
     
    #define SCB_CFSR_BUSFAULTSR_Pos   8U
     
    #define SCB_CFSR_BUSFAULTSR_Msk   (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)
     
    #define SCB_CFSR_MEMFAULTSR_Pos   0U
     
    #define SCB_CFSR_MEMFAULTSR_Msk   (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)
     
    #define SCB_CFSR_MMARVALID_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 7U)
     
    #define SCB_CFSR_MMARVALID_Msk   (1UL << SCB_CFSR_MMARVALID_Pos)
     
    #define SCB_CFSR_MLSPERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 5U)
     
    #define SCB_CFSR_MLSPERR_Msk   (1UL << SCB_CFSR_MLSPERR_Pos)
     
    #define SCB_CFSR_MSTKERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 4U)
     
    #define SCB_CFSR_MSTKERR_Msk   (1UL << SCB_CFSR_MSTKERR_Pos)
     
    #define SCB_CFSR_MUNSTKERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 3U)
     
    #define SCB_CFSR_MUNSTKERR_Msk   (1UL << SCB_CFSR_MUNSTKERR_Pos)
     
    #define SCB_CFSR_DACCVIOL_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 1U)
     
    #define SCB_CFSR_DACCVIOL_Msk   (1UL << SCB_CFSR_DACCVIOL_Pos)
     
    #define SCB_CFSR_IACCVIOL_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 0U)
     
    #define SCB_CFSR_IACCVIOL_Msk   (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)
     
    #define SCB_CFSR_BFARVALID_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 7U)
     
    #define SCB_CFSR_BFARVALID_Msk   (1UL << SCB_CFSR_BFARVALID_Pos)
     
    #define SCB_CFSR_LSPERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 5U)
     
    #define SCB_CFSR_LSPERR_Msk   (1UL << SCB_CFSR_LSPERR_Pos)
     
    #define SCB_CFSR_STKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 4U)
     
    #define SCB_CFSR_STKERR_Msk   (1UL << SCB_CFSR_STKERR_Pos)
     
    #define SCB_CFSR_UNSTKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 3U)
     
    #define SCB_CFSR_UNSTKERR_Msk   (1UL << SCB_CFSR_UNSTKERR_Pos)
     
    #define SCB_CFSR_IMPRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 2U)
     
    #define SCB_CFSR_IMPRECISERR_Msk   (1UL << SCB_CFSR_IMPRECISERR_Pos)
     
    #define SCB_CFSR_PRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 1U)
     
    #define SCB_CFSR_PRECISERR_Msk   (1UL << SCB_CFSR_PRECISERR_Pos)
     
    #define SCB_CFSR_IBUSERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 0U)
     
    #define SCB_CFSR_IBUSERR_Msk   (1UL << SCB_CFSR_IBUSERR_Pos)
     
    #define SCB_CFSR_DIVBYZERO_Pos   (SCB_CFSR_USGFAULTSR_Pos + 9U)
     
    #define SCB_CFSR_DIVBYZERO_Msk   (1UL << SCB_CFSR_DIVBYZERO_Pos)
     
    #define SCB_CFSR_UNALIGNED_Pos   (SCB_CFSR_USGFAULTSR_Pos + 8U)
     
    #define SCB_CFSR_UNALIGNED_Msk   (1UL << SCB_CFSR_UNALIGNED_Pos)
     
    #define SCB_CFSR_NOCP_Pos   (SCB_CFSR_USGFAULTSR_Pos + 3U)
     
    #define SCB_CFSR_NOCP_Msk   (1UL << SCB_CFSR_NOCP_Pos)
     
    #define SCB_CFSR_INVPC_Pos   (SCB_CFSR_USGFAULTSR_Pos + 2U)
     
    #define SCB_CFSR_INVPC_Msk   (1UL << SCB_CFSR_INVPC_Pos)
     
    #define SCB_CFSR_INVSTATE_Pos   (SCB_CFSR_USGFAULTSR_Pos + 1U)
     
    #define SCB_CFSR_INVSTATE_Msk   (1UL << SCB_CFSR_INVSTATE_Pos)
     
    #define SCB_CFSR_UNDEFINSTR_Pos   (SCB_CFSR_USGFAULTSR_Pos + 0U)
     
    #define SCB_CFSR_UNDEFINSTR_Msk   (1UL << SCB_CFSR_UNDEFINSTR_Pos)
     
    #define SCB_HFSR_DEBUGEVT_Pos   31U
     
    #define SCB_HFSR_DEBUGEVT_Msk   (1UL << SCB_HFSR_DEBUGEVT_Pos)
     
    #define SCB_HFSR_FORCED_Pos   30U
     
    #define SCB_HFSR_FORCED_Msk   (1UL << SCB_HFSR_FORCED_Pos)
     
    #define SCB_HFSR_VECTTBL_Pos   1U
     
    #define SCB_HFSR_VECTTBL_Msk   (1UL << SCB_HFSR_VECTTBL_Pos)
     
    #define SCB_DFSR_EXTERNAL_Pos   4U
     
    #define SCB_DFSR_EXTERNAL_Msk   (1UL << SCB_DFSR_EXTERNAL_Pos)
     
    #define SCB_DFSR_VCATCH_Pos   3U
     
    #define SCB_DFSR_VCATCH_Msk   (1UL << SCB_DFSR_VCATCH_Pos)
     
    #define SCB_DFSR_DWTTRAP_Pos   2U
     
    #define SCB_DFSR_DWTTRAP_Msk   (1UL << SCB_DFSR_DWTTRAP_Pos)
     
    #define SCB_DFSR_BKPT_Pos   1U
     
    #define SCB_DFSR_BKPT_Msk   (1UL << SCB_DFSR_BKPT_Pos)
     
    #define SCB_DFSR_HALTED_Pos   0U
     
    #define SCB_DFSR_HALTED_Msk   (1UL /*<< SCB_DFSR_HALTED_Pos*/)
     
    -

    Detailed Description

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    Type definitions for the System Control Block Registers.

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    Macro Definition Documentation

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    ◆ SCB_CPUID_IMPLEMENTER_Pos

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    #define SCB_CPUID_IMPLEMENTER_Pos   24U
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    SCB CPUID: IMPLEMENTER Position

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    ◆ SCB_CPUID_IMPLEMENTER_Msk

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    #define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
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    SCB CPUID: IMPLEMENTER Mask

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    ◆ SCB_CPUID_VARIANT_Pos

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    #define SCB_CPUID_VARIANT_Pos   20U
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    SCB CPUID: VARIANT Position

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    ◆ SCB_CPUID_VARIANT_Msk

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    #define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)
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    SCB CPUID: VARIANT Mask

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    ◆ SCB_CPUID_ARCHITECTURE_Pos

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    #define SCB_CPUID_ARCHITECTURE_Pos   16U
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    SCB CPUID: ARCHITECTURE Position

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    ◆ SCB_CPUID_ARCHITECTURE_Msk

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    #define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
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    SCB CPUID: ARCHITECTURE Mask

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    ◆ SCB_CPUID_PARTNO_Pos

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    #define SCB_CPUID_PARTNO_Pos   4U
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    SCB CPUID: PARTNO Position

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    ◆ SCB_CPUID_PARTNO_Msk

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    #define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)
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    SCB CPUID: PARTNO Mask

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    ◆ SCB_CPUID_REVISION_Pos

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    #define SCB_CPUID_REVISION_Pos   0U
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    SCB CPUID: REVISION Position

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    ◆ SCB_CPUID_REVISION_Msk

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    #define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)
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    SCB CPUID: REVISION Mask

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    ◆ SCB_ICSR_NMIPENDSET_Pos

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    #define SCB_ICSR_NMIPENDSET_Pos   31U
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    SCB ICSR: NMIPENDSET Position

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    ◆ SCB_ICSR_NMIPENDSET_Msk

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    #define SCB_ICSR_NMIPENDSET_Msk   (1UL << SCB_ICSR_NMIPENDSET_Pos)
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    SCB ICSR: NMIPENDSET Mask

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    ◆ SCB_ICSR_PENDSVSET_Pos

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    #define SCB_ICSR_PENDSVSET_Pos   28U
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    SCB ICSR: PENDSVSET Position

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    ◆ SCB_ICSR_PENDSVSET_Msk

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    #define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)
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    SCB ICSR: PENDSVSET Mask

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    ◆ SCB_ICSR_PENDSVCLR_Pos

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    #define SCB_ICSR_PENDSVCLR_Pos   27U
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    SCB ICSR: PENDSVCLR Position

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    ◆ SCB_ICSR_PENDSVCLR_Msk

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    #define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)
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    SCB ICSR: PENDSVCLR Mask

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    ◆ SCB_ICSR_PENDSTSET_Pos

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    #define SCB_ICSR_PENDSTSET_Pos   26U
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    SCB ICSR: PENDSTSET Position

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    ◆ SCB_ICSR_PENDSTSET_Msk

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    #define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)
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    SCB ICSR: PENDSTSET Mask

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    ◆ SCB_ICSR_PENDSTCLR_Pos

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    #define SCB_ICSR_PENDSTCLR_Pos   25U
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    SCB ICSR: PENDSTCLR Position

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    ◆ SCB_ICSR_PENDSTCLR_Msk

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    #define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)
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    SCB ICSR: PENDSTCLR Mask

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    ◆ SCB_ICSR_ISRPREEMPT_Pos

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    #define SCB_ICSR_ISRPREEMPT_Pos   23U
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    SCB ICSR: ISRPREEMPT Position

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    ◆ SCB_ICSR_ISRPREEMPT_Msk

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    #define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)
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    SCB ICSR: ISRPREEMPT Mask

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    ◆ SCB_ICSR_ISRPENDING_Pos

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    #define SCB_ICSR_ISRPENDING_Pos   22U
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    SCB ICSR: ISRPENDING Position

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    ◆ SCB_ICSR_ISRPENDING_Msk

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    #define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)
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    SCB ICSR: ISRPENDING Mask

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    ◆ SCB_ICSR_VECTPENDING_Pos

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    #define SCB_ICSR_VECTPENDING_Pos   12U
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    SCB ICSR: VECTPENDING Position

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    ◆ SCB_ICSR_VECTPENDING_Msk

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    #define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
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    SCB ICSR: VECTPENDING Mask

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    ◆ SCB_ICSR_RETTOBASE_Pos

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    #define SCB_ICSR_RETTOBASE_Pos   11U
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    SCB ICSR: RETTOBASE Position

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    ◆ SCB_ICSR_RETTOBASE_Msk

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    #define SCB_ICSR_RETTOBASE_Msk   (1UL << SCB_ICSR_RETTOBASE_Pos)
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    SCB ICSR: RETTOBASE Mask

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    ◆ SCB_ICSR_VECTACTIVE_Pos

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    #define SCB_ICSR_VECTACTIVE_Pos   0U
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    SCB ICSR: VECTACTIVE Position

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    ◆ SCB_ICSR_VECTACTIVE_Msk

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    #define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)
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    SCB ICSR: VECTACTIVE Mask

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    ◆ SCB_VTOR_TBLOFF_Pos

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    #define SCB_VTOR_TBLOFF_Pos   7U
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    SCB VTOR: TBLOFF Position

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    ◆ SCB_VTOR_TBLOFF_Msk

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    #define SCB_VTOR_TBLOFF_Msk   (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)
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    SCB VTOR: TBLOFF Mask

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    ◆ SCB_AIRCR_VECTKEY_Pos

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    #define SCB_AIRCR_VECTKEY_Pos   16U
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    SCB AIRCR: VECTKEY Position

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    ◆ SCB_AIRCR_VECTKEY_Msk

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    #define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
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    SCB AIRCR: VECTKEY Mask

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    ◆ SCB_AIRCR_VECTKEYSTAT_Pos

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    #define SCB_AIRCR_VECTKEYSTAT_Pos   16U
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    SCB AIRCR: VECTKEYSTAT Position

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    ◆ SCB_AIRCR_VECTKEYSTAT_Msk

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    #define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
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    SCB AIRCR: VECTKEYSTAT Mask

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    ◆ SCB_AIRCR_ENDIANESS_Pos

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    #define SCB_AIRCR_ENDIANESS_Pos   15U
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    SCB AIRCR: ENDIANESS Position

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    ◆ SCB_AIRCR_ENDIANESS_Msk

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    #define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)
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    SCB AIRCR: ENDIANESS Mask

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    ◆ SCB_AIRCR_PRIGROUP_Pos

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    #define SCB_AIRCR_PRIGROUP_Pos   8U
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    SCB AIRCR: PRIGROUP Position

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    ◆ SCB_AIRCR_PRIGROUP_Msk

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    #define SCB_AIRCR_PRIGROUP_Msk   (7UL << SCB_AIRCR_PRIGROUP_Pos)
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    SCB AIRCR: PRIGROUP Mask

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    ◆ SCB_AIRCR_SYSRESETREQ_Pos

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    #define SCB_AIRCR_SYSRESETREQ_Pos   2U
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    SCB AIRCR: SYSRESETREQ Position

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    ◆ SCB_AIRCR_SYSRESETREQ_Msk

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    #define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
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    SCB AIRCR: SYSRESETREQ Mask

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    ◆ SCB_AIRCR_VECTCLRACTIVE_Pos

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    #define SCB_AIRCR_VECTCLRACTIVE_Pos   1U
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    SCB AIRCR: VECTCLRACTIVE Position

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    ◆ SCB_AIRCR_VECTCLRACTIVE_Msk

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    -
    - - - - -
    #define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
    -
    -

    SCB AIRCR: VECTCLRACTIVE Mask

    - -
    -
    - -

    ◆ SCB_AIRCR_VECTRESET_Pos

    - -
    -
    - - - - -
    #define SCB_AIRCR_VECTRESET_Pos   0U
    -
    -

    SCB AIRCR: VECTRESET Position

    - -
    -
    - -

    ◆ SCB_AIRCR_VECTRESET_Msk

    - -
    -
    - - - - -
    #define SCB_AIRCR_VECTRESET_Msk   (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)
    -
    -

    SCB AIRCR: VECTRESET Mask

    - -
    -
    - -

    ◆ SCB_SCR_SEVONPEND_Pos

    - -
    -
    - - - - -
    #define SCB_SCR_SEVONPEND_Pos   4U
    -
    -

    SCB SCR: SEVONPEND Position

    - -
    -
    - -

    ◆ SCB_SCR_SEVONPEND_Msk

    - -
    -
    - - - - -
    #define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)
    -
    -

    SCB SCR: SEVONPEND Mask

    - -
    -
    - -

    ◆ SCB_SCR_SLEEPDEEP_Pos

    - -
    -
    - - - - -
    #define SCB_SCR_SLEEPDEEP_Pos   2U
    -
    -

    SCB SCR: SLEEPDEEP Position

    - -
    -
    - -

    ◆ SCB_SCR_SLEEPDEEP_Msk

    - -
    -
    - - - - -
    #define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)
    -
    -

    SCB SCR: SLEEPDEEP Mask

    - -
    -
    - -

    ◆ SCB_SCR_SLEEPONEXIT_Pos

    - -
    -
    - - - - -
    #define SCB_SCR_SLEEPONEXIT_Pos   1U
    -
    -

    SCB SCR: SLEEPONEXIT Position

    - -
    -
    - -

    ◆ SCB_SCR_SLEEPONEXIT_Msk

    - -
    -
    - - - - -
    #define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)
    -
    -

    SCB SCR: SLEEPONEXIT Mask

    - -
    -
    - -

    ◆ SCB_CCR_STKALIGN_Pos

    - -
    -
    - - - - -
    #define SCB_CCR_STKALIGN_Pos   9U
    -
    -

    SCB CCR: STKALIGN Position

    - -
    -
    - -

    ◆ SCB_CCR_STKALIGN_Msk

    - -
    -
    - - - - -
    #define SCB_CCR_STKALIGN_Msk   (1UL << SCB_CCR_STKALIGN_Pos)
    -
    -

    SCB CCR: STKALIGN Mask

    - -
    -
    - -

    ◆ SCB_CCR_BFHFNMIGN_Pos

    - -
    -
    - - - - -
    #define SCB_CCR_BFHFNMIGN_Pos   8U
    -
    -

    SCB CCR: BFHFNMIGN Position

    - -
    -
    - -

    ◆ SCB_CCR_BFHFNMIGN_Msk

    - -
    -
    - - - - -
    #define SCB_CCR_BFHFNMIGN_Msk   (1UL << SCB_CCR_BFHFNMIGN_Pos)
    -
    -

    SCB CCR: BFHFNMIGN Mask

    - -
    -
    - -

    ◆ SCB_CCR_DIV_0_TRP_Pos

    - -
    -
    - - - - -
    #define SCB_CCR_DIV_0_TRP_Pos   4U
    -
    -

    SCB CCR: DIV_0_TRP Position

    - -
    -
    - -

    ◆ SCB_CCR_DIV_0_TRP_Msk

    - -
    -
    - - - - -
    #define SCB_CCR_DIV_0_TRP_Msk   (1UL << SCB_CCR_DIV_0_TRP_Pos)
    -
    -

    SCB CCR: DIV_0_TRP Mask

    - -
    -
    - -

    ◆ SCB_CCR_UNALIGN_TRP_Pos

    - -
    -
    - - - - -
    #define SCB_CCR_UNALIGN_TRP_Pos   3U
    -
    -

    SCB CCR: UNALIGN_TRP Position

    - -
    -
    - -

    ◆ SCB_CCR_UNALIGN_TRP_Msk

    - -
    -
    - - - - -
    #define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)
    -
    -

    SCB CCR: UNALIGN_TRP Mask

    - -
    -
    - -

    ◆ SCB_CCR_USERSETMPEND_Pos

    - -
    -
    - - - - -
    #define SCB_CCR_USERSETMPEND_Pos   1U
    -
    -

    SCB CCR: USERSETMPEND Position

    - -
    -
    - -

    ◆ SCB_CCR_USERSETMPEND_Msk

    - -
    -
    - - - - -
    #define SCB_CCR_USERSETMPEND_Msk   (1UL << SCB_CCR_USERSETMPEND_Pos)
    -
    -

    SCB CCR: USERSETMPEND Mask

    - -
    -
    - -

    ◆ SCB_CCR_NONBASETHRDENA_Pos

    - -
    -
    - - - - -
    #define SCB_CCR_NONBASETHRDENA_Pos   0U
    -
    -

    SCB CCR: NONBASETHRDENA Position

    - -
    -
    - -

    ◆ SCB_CCR_NONBASETHRDENA_Msk

    - -
    -
    - - - - -
    #define SCB_CCR_NONBASETHRDENA_Msk   (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)
    -
    -

    SCB CCR: NONBASETHRDENA Mask

    - -
    -
    - -

    ◆ SCB_SHCSR_USGFAULTENA_Pos

    - -
    -
    - - - - -
    #define SCB_SHCSR_USGFAULTENA_Pos   18U
    -
    -

    SCB SHCSR: USGFAULTENA Position

    - -
    -
    - -

    ◆ SCB_SHCSR_USGFAULTENA_Msk

    - -
    -
    - - - - -
    #define SCB_SHCSR_USGFAULTENA_Msk   (1UL << SCB_SHCSR_USGFAULTENA_Pos)
    -
    -

    SCB SHCSR: USGFAULTENA Mask

    - -
    -
    - -

    ◆ SCB_SHCSR_BUSFAULTENA_Pos

    - -
    -
    - - - - -
    #define SCB_SHCSR_BUSFAULTENA_Pos   17U
    -
    -

    SCB SHCSR: BUSFAULTENA Position

    - -
    -
    - -

    ◆ SCB_SHCSR_BUSFAULTENA_Msk

    - -
    -
    - - - - -
    #define SCB_SHCSR_BUSFAULTENA_Msk   (1UL << SCB_SHCSR_BUSFAULTENA_Pos)
    -
    -

    SCB SHCSR: BUSFAULTENA Mask

    - -
    -
    - -

    ◆ SCB_SHCSR_MEMFAULTENA_Pos

    - -
    -
    - - - - -
    #define SCB_SHCSR_MEMFAULTENA_Pos   16U
    -
    -

    SCB SHCSR: MEMFAULTENA Position

    - -
    -
    - -

    ◆ SCB_SHCSR_MEMFAULTENA_Msk

    - -
    -
    - - - - -
    #define SCB_SHCSR_MEMFAULTENA_Msk   (1UL << SCB_SHCSR_MEMFAULTENA_Pos)
    -
    -

    SCB SHCSR: MEMFAULTENA Mask

    - -
    -
    - -

    ◆ SCB_SHCSR_SVCALLPENDED_Pos

    - -
    -
    - - - - -
    #define SCB_SHCSR_SVCALLPENDED_Pos   15U
    -
    -

    SCB SHCSR: SVCALLPENDED Position

    - -
    -
    - -

    ◆ SCB_SHCSR_SVCALLPENDED_Msk

    - -
    -
    - - - - -
    #define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
    -
    -

    SCB SHCSR: SVCALLPENDED Mask

    - -
    -
    - -

    ◆ SCB_SHCSR_BUSFAULTPENDED_Pos

    - -
    -
    - - - - -
    #define SCB_SHCSR_BUSFAULTPENDED_Pos   14U
    -
    -

    SCB SHCSR: BUSFAULTPENDED Position

    - -
    -
    - -

    ◆ SCB_SHCSR_BUSFAULTPENDED_Msk

    - -
    -
    - - - - -
    #define SCB_SHCSR_BUSFAULTPENDED_Msk   (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)
    -
    -

    SCB SHCSR: BUSFAULTPENDED Mask

    - -
    -
    - -

    ◆ SCB_SHCSR_MEMFAULTPENDED_Pos

    - -
    -
    - - - - -
    #define SCB_SHCSR_MEMFAULTPENDED_Pos   13U
    -
    -

    SCB SHCSR: MEMFAULTPENDED Position

    - -
    -
    - -

    ◆ SCB_SHCSR_MEMFAULTPENDED_Msk

    - -
    -
    - - - - -
    #define SCB_SHCSR_MEMFAULTPENDED_Msk   (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)
    -
    -

    SCB SHCSR: MEMFAULTPENDED Mask

    - -
    -
    - -

    ◆ SCB_SHCSR_USGFAULTPENDED_Pos

    - -
    -
    - - - - -
    #define SCB_SHCSR_USGFAULTPENDED_Pos   12U
    -
    -

    SCB SHCSR: USGFAULTPENDED Position

    - -
    -
    - -

    ◆ SCB_SHCSR_USGFAULTPENDED_Msk

    - -
    -
    - - - - -
    #define SCB_SHCSR_USGFAULTPENDED_Msk   (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)
    -
    -

    SCB SHCSR: USGFAULTPENDED Mask

    - -
    -
    - -

    ◆ SCB_SHCSR_SYSTICKACT_Pos

    - -
    -
    - - - - -
    #define SCB_SHCSR_SYSTICKACT_Pos   11U
    -
    -

    SCB SHCSR: SYSTICKACT Position

    - -
    -
    - -

    ◆ SCB_SHCSR_SYSTICKACT_Msk

    - -
    -
    - - - - -
    #define SCB_SHCSR_SYSTICKACT_Msk   (1UL << SCB_SHCSR_SYSTICKACT_Pos)
    -
    -

    SCB SHCSR: SYSTICKACT Mask

    - -
    -
    - -

    ◆ SCB_SHCSR_PENDSVACT_Pos

    - -
    -
    - - - - -
    #define SCB_SHCSR_PENDSVACT_Pos   10U
    -
    -

    SCB SHCSR: PENDSVACT Position

    - -
    -
    - -

    ◆ SCB_SHCSR_PENDSVACT_Msk

    - -
    -
    - - - - -
    #define SCB_SHCSR_PENDSVACT_Msk   (1UL << SCB_SHCSR_PENDSVACT_Pos)
    -
    -

    SCB SHCSR: PENDSVACT Mask

    - -
    -
    - -

    ◆ SCB_SHCSR_MONITORACT_Pos

    - -
    -
    - - - - -
    #define SCB_SHCSR_MONITORACT_Pos   8U
    -
    -

    SCB SHCSR: MONITORACT Position

    - -
    -
    - -

    ◆ SCB_SHCSR_MONITORACT_Msk

    - -
    -
    - - - - -
    #define SCB_SHCSR_MONITORACT_Msk   (1UL << SCB_SHCSR_MONITORACT_Pos)
    -
    -

    SCB SHCSR: MONITORACT Mask

    - -
    -
    - -

    ◆ SCB_SHCSR_SVCALLACT_Pos

    - -
    -
    - - - - -
    #define SCB_SHCSR_SVCALLACT_Pos   7U
    -
    -

    SCB SHCSR: SVCALLACT Position

    - -
    -
    - -

    ◆ SCB_SHCSR_SVCALLACT_Msk

    - -
    -
    - - - - -
    #define SCB_SHCSR_SVCALLACT_Msk   (1UL << SCB_SHCSR_SVCALLACT_Pos)
    -
    -

    SCB SHCSR: SVCALLACT Mask

    - -
    -
    - -

    ◆ SCB_SHCSR_USGFAULTACT_Pos

    - -
    -
    - - - - -
    #define SCB_SHCSR_USGFAULTACT_Pos   3U
    -
    -

    SCB SHCSR: USGFAULTACT Position

    - -
    -
    - -

    ◆ SCB_SHCSR_USGFAULTACT_Msk

    - -
    -
    - - - - -
    #define SCB_SHCSR_USGFAULTACT_Msk   (1UL << SCB_SHCSR_USGFAULTACT_Pos)
    -
    -

    SCB SHCSR: USGFAULTACT Mask

    - -
    -
    - -

    ◆ SCB_SHCSR_BUSFAULTACT_Pos

    - -
    -
    - - - - -
    #define SCB_SHCSR_BUSFAULTACT_Pos   1U
    -
    -

    SCB SHCSR: BUSFAULTACT Position

    - -
    -
    - -

    ◆ SCB_SHCSR_BUSFAULTACT_Msk

    - -
    -
    - - - - -
    #define SCB_SHCSR_BUSFAULTACT_Msk   (1UL << SCB_SHCSR_BUSFAULTACT_Pos)
    -
    -

    SCB SHCSR: BUSFAULTACT Mask

    - -
    -
    - -

    ◆ SCB_SHCSR_MEMFAULTACT_Pos

    - -
    -
    - - - - -
    #define SCB_SHCSR_MEMFAULTACT_Pos   0U
    -
    -

    SCB SHCSR: MEMFAULTACT Position

    - -
    -
    - -

    ◆ SCB_SHCSR_MEMFAULTACT_Msk

    - -
    -
    - - - - -
    #define SCB_SHCSR_MEMFAULTACT_Msk   (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)
    -
    -

    SCB SHCSR: MEMFAULTACT Mask

    - -
    -
    - -

    ◆ SCB_CFSR_USGFAULTSR_Pos

    - -
    -
    - - - - -
    #define SCB_CFSR_USGFAULTSR_Pos   16U
    -
    -

    SCB CFSR: Usage Fault Status Register Position

    - -
    -
    - -

    ◆ SCB_CFSR_USGFAULTSR_Msk

    - -
    -
    - - - - -
    #define SCB_CFSR_USGFAULTSR_Msk   (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)
    -
    -

    SCB CFSR: Usage Fault Status Register Mask

    - -
    -
    - -

    ◆ SCB_CFSR_BUSFAULTSR_Pos

    - -
    -
    - - - - -
    #define SCB_CFSR_BUSFAULTSR_Pos   8U
    -
    -

    SCB CFSR: Bus Fault Status Register Position

    - -
    -
    - -

    ◆ SCB_CFSR_BUSFAULTSR_Msk

    - -
    -
    - - - - -
    #define SCB_CFSR_BUSFAULTSR_Msk   (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)
    -
    -

    SCB CFSR: Bus Fault Status Register Mask

    - -
    -
    - -

    ◆ SCB_CFSR_MEMFAULTSR_Pos

    - -
    -
    - - - - -
    #define SCB_CFSR_MEMFAULTSR_Pos   0U
    -
    -

    SCB CFSR: Memory Manage Fault Status Register Position

    - -
    -
    - -

    ◆ SCB_CFSR_MEMFAULTSR_Msk

    - -
    -
    - - - - -
    #define SCB_CFSR_MEMFAULTSR_Msk   (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)
    -
    -

    SCB CFSR: Memory Manage Fault Status Register Mask

    - -
    -
    - -

    ◆ SCB_CFSR_MMARVALID_Pos

    - -
    -
    - - - - -
    #define SCB_CFSR_MMARVALID_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 7U)
    -
    -

    SCB CFSR (MMFSR): MMARVALID Position

    - -
    -
    - -

    ◆ SCB_CFSR_MMARVALID_Msk

    - -
    -
    - - - - -
    #define SCB_CFSR_MMARVALID_Msk   (1UL << SCB_CFSR_MMARVALID_Pos)
    -
    -

    SCB CFSR (MMFSR): MMARVALID Mask

    - -
    -
    - -

    ◆ SCB_CFSR_MLSPERR_Pos

    - -
    -
    - - - - -
    #define SCB_CFSR_MLSPERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 5U)
    -
    -

    SCB CFSR (MMFSR): MLSPERR Position

    - -
    -
    - -

    ◆ SCB_CFSR_MLSPERR_Msk

    - -
    -
    - - - - -
    #define SCB_CFSR_MLSPERR_Msk   (1UL << SCB_CFSR_MLSPERR_Pos)
    -
    -

    SCB CFSR (MMFSR): MLSPERR Mask

    - -
    -
    - -

    ◆ SCB_CFSR_MSTKERR_Pos

    - -
    -
    - - - - -
    #define SCB_CFSR_MSTKERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 4U)
    -
    -

    SCB CFSR (MMFSR): MSTKERR Position

    - -
    -
    - -

    ◆ SCB_CFSR_MSTKERR_Msk

    - -
    -
    - - - - -
    #define SCB_CFSR_MSTKERR_Msk   (1UL << SCB_CFSR_MSTKERR_Pos)
    -
    -

    SCB CFSR (MMFSR): MSTKERR Mask

    - -
    -
    - -

    ◆ SCB_CFSR_MUNSTKERR_Pos

    - -
    -
    - - - - -
    #define SCB_CFSR_MUNSTKERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 3U)
    -
    -

    SCB CFSR (MMFSR): MUNSTKERR Position

    - -
    -
    - -

    ◆ SCB_CFSR_MUNSTKERR_Msk

    - -
    -
    - - - - -
    #define SCB_CFSR_MUNSTKERR_Msk   (1UL << SCB_CFSR_MUNSTKERR_Pos)
    -
    -

    SCB CFSR (MMFSR): MUNSTKERR Mask

    - -
    -
    - -

    ◆ SCB_CFSR_DACCVIOL_Pos

    - -
    -
    - - - - -
    #define SCB_CFSR_DACCVIOL_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 1U)
    -
    -

    SCB CFSR (MMFSR): DACCVIOL Position

    - -
    -
    - -

    ◆ SCB_CFSR_DACCVIOL_Msk

    - -
    -
    - - - - -
    #define SCB_CFSR_DACCVIOL_Msk   (1UL << SCB_CFSR_DACCVIOL_Pos)
    -
    -

    SCB CFSR (MMFSR): DACCVIOL Mask

    - -
    -
    - -

    ◆ SCB_CFSR_IACCVIOL_Pos

    - -
    -
    - - - - -
    #define SCB_CFSR_IACCVIOL_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 0U)
    -
    -

    SCB CFSR (MMFSR): IACCVIOL Position

    - -
    -
    - -

    ◆ SCB_CFSR_IACCVIOL_Msk

    - -
    -
    - - - - -
    #define SCB_CFSR_IACCVIOL_Msk   (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)
    -
    -

    SCB CFSR (MMFSR): IACCVIOL Mask

    - -
    -
    - -

    ◆ SCB_CFSR_BFARVALID_Pos

    - -
    -
    - - - - -
    #define SCB_CFSR_BFARVALID_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 7U)
    -
    -

    SCB CFSR (BFSR): BFARVALID Position

    - -
    -
    - -

    ◆ SCB_CFSR_BFARVALID_Msk

    - -
    -
    - - - - -
    #define SCB_CFSR_BFARVALID_Msk   (1UL << SCB_CFSR_BFARVALID_Pos)
    -
    -

    SCB CFSR (BFSR): BFARVALID Mask

    - -
    -
    - -

    ◆ SCB_CFSR_LSPERR_Pos

    - -
    -
    - - - - -
    #define SCB_CFSR_LSPERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 5U)
    -
    -

    SCB CFSR (BFSR): LSPERR Position

    - -
    -
    - -

    ◆ SCB_CFSR_LSPERR_Msk

    - -
    -
    - - - - -
    #define SCB_CFSR_LSPERR_Msk   (1UL << SCB_CFSR_LSPERR_Pos)
    -
    -

    SCB CFSR (BFSR): LSPERR Mask

    - -
    -
    - -

    ◆ SCB_CFSR_STKERR_Pos

    - -
    -
    - - - - -
    #define SCB_CFSR_STKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 4U)
    -
    -

    SCB CFSR (BFSR): STKERR Position

    - -
    -
    - -

    ◆ SCB_CFSR_STKERR_Msk

    - -
    -
    - - - - -
    #define SCB_CFSR_STKERR_Msk   (1UL << SCB_CFSR_STKERR_Pos)
    -
    -

    SCB CFSR (BFSR): STKERR Mask

    - -
    -
    - -

    ◆ SCB_CFSR_UNSTKERR_Pos

    - -
    -
    - - - - -
    #define SCB_CFSR_UNSTKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 3U)
    -
    -

    SCB CFSR (BFSR): UNSTKERR Position

    - -
    -
    - -

    ◆ SCB_CFSR_UNSTKERR_Msk

    - -
    -
    - - - - -
    #define SCB_CFSR_UNSTKERR_Msk   (1UL << SCB_CFSR_UNSTKERR_Pos)
    -
    -

    SCB CFSR (BFSR): UNSTKERR Mask

    - -
    -
    - -

    ◆ SCB_CFSR_IMPRECISERR_Pos

    - -
    -
    - - - - -
    #define SCB_CFSR_IMPRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 2U)
    -
    -

    SCB CFSR (BFSR): IMPRECISERR Position

    - -
    -
    - -

    ◆ SCB_CFSR_IMPRECISERR_Msk

    - -
    -
    - - - - -
    #define SCB_CFSR_IMPRECISERR_Msk   (1UL << SCB_CFSR_IMPRECISERR_Pos)
    -
    -

    SCB CFSR (BFSR): IMPRECISERR Mask

    - -
    -
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    ◆ SCB_CFSR_PRECISERR_Pos

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    #define SCB_CFSR_PRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 1U)
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    SCB CFSR (BFSR): PRECISERR Position

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    ◆ SCB_CFSR_PRECISERR_Msk

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    #define SCB_CFSR_PRECISERR_Msk   (1UL << SCB_CFSR_PRECISERR_Pos)
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    SCB CFSR (BFSR): PRECISERR Mask

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    ◆ SCB_CFSR_IBUSERR_Pos

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    #define SCB_CFSR_IBUSERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 0U)
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    SCB CFSR (BFSR): IBUSERR Position

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    ◆ SCB_CFSR_IBUSERR_Msk

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    #define SCB_CFSR_IBUSERR_Msk   (1UL << SCB_CFSR_IBUSERR_Pos)
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    SCB CFSR (BFSR): IBUSERR Mask

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    ◆ SCB_CFSR_DIVBYZERO_Pos

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    #define SCB_CFSR_DIVBYZERO_Pos   (SCB_CFSR_USGFAULTSR_Pos + 9U)
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    SCB CFSR (UFSR): DIVBYZERO Position

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    ◆ SCB_CFSR_DIVBYZERO_Msk

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    #define SCB_CFSR_DIVBYZERO_Msk   (1UL << SCB_CFSR_DIVBYZERO_Pos)
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    SCB CFSR (UFSR): DIVBYZERO Mask

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    ◆ SCB_CFSR_UNALIGNED_Pos

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    #define SCB_CFSR_UNALIGNED_Pos   (SCB_CFSR_USGFAULTSR_Pos + 8U)
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    SCB CFSR (UFSR): UNALIGNED Position

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    ◆ SCB_CFSR_UNALIGNED_Msk

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    #define SCB_CFSR_UNALIGNED_Msk   (1UL << SCB_CFSR_UNALIGNED_Pos)
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    SCB CFSR (UFSR): UNALIGNED Mask

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    ◆ SCB_CFSR_NOCP_Pos

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    #define SCB_CFSR_NOCP_Pos   (SCB_CFSR_USGFAULTSR_Pos + 3U)
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    SCB CFSR (UFSR): NOCP Position

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    ◆ SCB_CFSR_NOCP_Msk

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    #define SCB_CFSR_NOCP_Msk   (1UL << SCB_CFSR_NOCP_Pos)
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    SCB CFSR (UFSR): NOCP Mask

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    ◆ SCB_CFSR_INVPC_Pos

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    #define SCB_CFSR_INVPC_Pos   (SCB_CFSR_USGFAULTSR_Pos + 2U)
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    SCB CFSR (UFSR): INVPC Position

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    ◆ SCB_CFSR_INVPC_Msk

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    #define SCB_CFSR_INVPC_Msk   (1UL << SCB_CFSR_INVPC_Pos)
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    SCB CFSR (UFSR): INVPC Mask

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    ◆ SCB_CFSR_INVSTATE_Pos

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    #define SCB_CFSR_INVSTATE_Pos   (SCB_CFSR_USGFAULTSR_Pos + 1U)
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    SCB CFSR (UFSR): INVSTATE Position

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    ◆ SCB_CFSR_INVSTATE_Msk

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    #define SCB_CFSR_INVSTATE_Msk   (1UL << SCB_CFSR_INVSTATE_Pos)
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    SCB CFSR (UFSR): INVSTATE Mask

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    ◆ SCB_CFSR_UNDEFINSTR_Pos

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    #define SCB_CFSR_UNDEFINSTR_Pos   (SCB_CFSR_USGFAULTSR_Pos + 0U)
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    SCB CFSR (UFSR): UNDEFINSTR Position

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    ◆ SCB_CFSR_UNDEFINSTR_Msk

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    #define SCB_CFSR_UNDEFINSTR_Msk   (1UL << SCB_CFSR_UNDEFINSTR_Pos)
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    SCB CFSR (UFSR): UNDEFINSTR Mask

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    ◆ SCB_HFSR_DEBUGEVT_Pos

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    #define SCB_HFSR_DEBUGEVT_Pos   31U
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    SCB HFSR: DEBUGEVT Position

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    ◆ SCB_HFSR_DEBUGEVT_Msk

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    #define SCB_HFSR_DEBUGEVT_Msk   (1UL << SCB_HFSR_DEBUGEVT_Pos)
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    SCB HFSR: DEBUGEVT Mask

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    ◆ SCB_HFSR_FORCED_Pos

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    #define SCB_HFSR_FORCED_Pos   30U
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    SCB HFSR: FORCED Position

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    ◆ SCB_HFSR_FORCED_Msk

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    #define SCB_HFSR_FORCED_Msk   (1UL << SCB_HFSR_FORCED_Pos)
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    SCB HFSR: FORCED Mask

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    ◆ SCB_HFSR_VECTTBL_Pos

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    #define SCB_HFSR_VECTTBL_Pos   1U
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    SCB HFSR: VECTTBL Position

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    ◆ SCB_HFSR_VECTTBL_Msk

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    #define SCB_HFSR_VECTTBL_Msk   (1UL << SCB_HFSR_VECTTBL_Pos)
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    SCB HFSR: VECTTBL Mask

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    ◆ SCB_DFSR_EXTERNAL_Pos

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    #define SCB_DFSR_EXTERNAL_Pos   4U
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    SCB DFSR: EXTERNAL Position

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    ◆ SCB_DFSR_EXTERNAL_Msk

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    #define SCB_DFSR_EXTERNAL_Msk   (1UL << SCB_DFSR_EXTERNAL_Pos)
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    SCB DFSR: EXTERNAL Mask

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    ◆ SCB_DFSR_VCATCH_Pos

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    #define SCB_DFSR_VCATCH_Pos   3U
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    SCB DFSR: VCATCH Position

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    ◆ SCB_DFSR_VCATCH_Msk

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    #define SCB_DFSR_VCATCH_Msk   (1UL << SCB_DFSR_VCATCH_Pos)
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    SCB DFSR: VCATCH Mask

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    ◆ SCB_DFSR_DWTTRAP_Pos

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    #define SCB_DFSR_DWTTRAP_Pos   2U
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    SCB DFSR: DWTTRAP Position

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    ◆ SCB_DFSR_DWTTRAP_Msk

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    #define SCB_DFSR_DWTTRAP_Msk   (1UL << SCB_DFSR_DWTTRAP_Pos)
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    SCB DFSR: DWTTRAP Mask

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    ◆ SCB_DFSR_BKPT_Pos

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    #define SCB_DFSR_BKPT_Pos   1U
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    SCB DFSR: BKPT Position

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    ◆ SCB_DFSR_BKPT_Msk

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    #define SCB_DFSR_BKPT_Msk   (1UL << SCB_DFSR_BKPT_Pos)
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    SCB DFSR: BKPT Mask

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    ◆ SCB_DFSR_HALTED_Pos

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    #define SCB_DFSR_HALTED_Pos   0U
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    SCB DFSR: HALTED Position

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    ◆ SCB_DFSR_HALTED_Msk

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    #define SCB_DFSR_HALTED_Msk   (1UL /*<< SCB_DFSR_HALTED_Pos*/)
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    SCB DFSR: HALTED Mask

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    - - diff --git a/DOCS/html/group___c_m_s_i_s___s_c_b.map b/DOCS/html/group___c_m_s_i_s___s_c_b.map deleted file mode 100644 index 1682d2f..0000000 --- a/DOCS/html/group___c_m_s_i_s___s_c_b.map +++ /dev/null @@ -1,5 +0,0 @@ - - - - - diff --git a/DOCS/html/group___c_m_s_i_s___s_c_b.md5 b/DOCS/html/group___c_m_s_i_s___s_c_b.md5 deleted file mode 100644 index 10517f7..0000000 --- a/DOCS/html/group___c_m_s_i_s___s_c_b.md5 +++ /dev/null @@ -1 +0,0 @@ -feb8fa248fec8725d9611b82081f05d0 \ No newline at end of file diff --git a/DOCS/html/group___c_m_s_i_s___s_c_b.png b/DOCS/html/group___c_m_s_i_s___s_c_b.png deleted file mode 100644 index f06d7755324e673eec3a56befbe677202cc459e1..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 2556 zcmV=TL_pO{Wj1zP-tmQ38jbB zKawVCOYy#22+1M&D{={>r>^&H3%wD6lWSm-z?J@fhe z-TJf#>JzdoJCkMEJKcmtWbGn=BRh5q_&p;ZR;$$&0Ov!;VPdsfy`E*+xzKS?lG+oT zjoEDGHxwdE)9EyH2-e2qF-D_N=rE`!_V)I$TrNY0VdeDc)4lj^Q#W>ZcQK#Oh4b=` zV<93UBJz$24iOO%^$rspA|fK{9VR$LL`2j(OmK*Zh^Tj%;1CfJQSUTfCaxpPG89Fj zJiSY%vBeO38(EAg#83J}m(QknONZ)u#1j8>I&F-l>9XbO^0Lpnh=Ihi?8yCUlWhB{ z>k&)*sUJt2BshTI4UyVLX1r;}5WA*>Uup-|dR;E-_PHLuwmq5i`Qy6FHmP2h%eqr) zTV2QM>=ac|6v9k8R>ZLMo^Z)wt zD&?dQuV{H6>sGDDWxP%Q)|WSlfz;G{L#jmYH?R6KD$CZFua{$*s5JGC=+<9fkEUrh zv8s~QqZ$JfKQr~-kSdk7&Zb=ywdJ#bD)oz&6U8Gd$H#HN*(oaEAnQ~e z7gBxSG*48fYB_Bis;%rU;x(<)G|8!#WgD;Py^9#=sCrL_?x~TcQ$w3_Wv7i~?>8}3 z-@86#)>ePhdNeKDRBl^Lb+R!#ZSl6nz|&vt>OCF0ZHUiyyc&;-_RZut($u!99&>c+ zmo0C4?6l=H!EwpON_N@JXA`fT?yFuOx)YjU7>MO?6uJz}a>Hb=i)0-PU#84!4yNLtF1W!BOeOk$tZEUdC18(zf%5 zIBgQcshSvKAUWM06Wtylo*oH<+ufXQk4dQGPKs=M%R=b92S+t~_L*tx2=PaZVaJIf z20F}jZ-LJq9$oCQINy+bi9el)VQ>RO&@z%A)Se-B1W*&?H zoCEMOfM)uUXVwz;h%d&XokxsYYqJ460O zMSi$WV5ZY4ilVqUpU>ZISmbK}ehA=K0Dg*cf6s8xbGZ-TQD*^Z+TPwS#^W(YqmlEn zhu$kPRC{}SST2`W=JWY^$zo3exPbC|@i>6{03KS;`x3yb0D|m1lgZ@0t*xzdK6=hwx4mk$kck5T@u3fwK$=24E(=wUZ3>Om|O4`}8XFu54+1WukQ1S(oy*FP%tuem~ zVB#@6snKZEG24uF6({9@5uV3E+a1p>ZfNw*+w=+pLZIk9VyL$5F5*$C(?vaP>)pliB)J5~=0T6TWyiqh`s&uDdPBrW{0HSYg!ciwg7ONI zmr)M3Yq*vGWjIbVW+dBaMfb#P3lK|cT z@DG&Z5-4J#q@?MFhotTADDUX~4FEp?@F$ex(nvvUZDv>T#J1itNhLTrt3JIt zUo^dKny6eEl~|fS7rM73l^t2b=Ky{S;5+LVbwuZ(pe~jXeTIpV&skFx~+HBRf-((q+?ci&@eIHMH)g8H^)1B7VT_)=$RM`n#cOe4pr;0@L zV@Q@F^jYWthRpTjAZ#9EL0`EK;ET{f_@X*q(e+~)Y#t}!D<08yh;6-X^)kU}qq}4I z#H53UtUk7;KFzeOYMD%OXv4Jax4l`Q$rzljw)K`tZVZmfASj!GQmzM{xgNCD zR=&%!V%%Y=KblTQwOtn8l-zKTF}c#zuC`rOD!UCwTUlMk(^WkjWNg6Zk~PsEN@bo- zxhmzzrdQ|JN4V>jqx%`%tHOv>iEg&1nt-$|r&11keul@ST~?j%x}5rF>TRvBcyzam zX+0vm(H{{J5s@Y)IFXBK1Uq|g$X2MUq}Y2ysfnrW_o0j92@{+I#FA9R5(lL%M54ju zhEmk$Hn)p)V}e6OL`1#A1c!)-h45Ukz2d6UN?6VD>rW3@ER163wfU33LS%~qA0H1 zy?Zxw7}PU)o?j0ggQ+~vuP+u0EEbEj1g{ diff --git a/DOCS/html/group___c_m_s_i_s___s_cn_s_c_b.html b/DOCS/html/group___c_m_s_i_s___s_cn_s_c_b.html deleted file mode 100644 index 6a13cbb..0000000 --- a/DOCS/html/group___c_m_s_i_s___s_cn_s_c_b.html +++ /dev/null @@ -1,325 +0,0 @@ - - - - - - - -STM MATLAB Simulator: System Controls not in SCB (SCnSCB) - - - - - - - - - - - -
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    -Topics | -Data Structures | -Macros
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    System Controls not in SCB (SCnSCB)
    Defines and Type Definitions » Status and Control Registers » Nested Vectored Interrupt Controller (NVIC) » System Control Block (SCB)
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    Type definitions for the System Control and ID Register not in the SCB. -More...

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    - + Collaboration diagram for System Controls not in SCB (SCnSCB):
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    -Topics

     System Tick Timer (SysTick)
     Type definitions for the System Timer Registers.
     
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    -Data Structures

    struct  SCnSCB_Type
     Structure type to access the System Control and ID Register not in the SCB. More...
     
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    -Macros

    #define SCnSCB_ICTR_INTLINESNUM_Pos   0U
     
    #define SCnSCB_ICTR_INTLINESNUM_Msk   (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)
     
    #define SCnSCB_ACTLR_DISOOFP_Pos   9U
     
    #define SCnSCB_ACTLR_DISOOFP_Msk   (1UL << SCnSCB_ACTLR_DISOOFP_Pos)
     
    #define SCnSCB_ACTLR_DISFPCA_Pos   8U
     
    #define SCnSCB_ACTLR_DISFPCA_Msk   (1UL << SCnSCB_ACTLR_DISFPCA_Pos)
     
    #define SCnSCB_ACTLR_DISFOLD_Pos   2U
     
    #define SCnSCB_ACTLR_DISFOLD_Msk   (1UL << SCnSCB_ACTLR_DISFOLD_Pos)
     
    #define SCnSCB_ACTLR_DISDEFWBUF_Pos   1U
     
    #define SCnSCB_ACTLR_DISDEFWBUF_Msk   (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)
     
    #define SCnSCB_ACTLR_DISMCYCINT_Pos   0U
     
    #define SCnSCB_ACTLR_DISMCYCINT_Msk   (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)
     
    -

    Detailed Description

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    Type definitions for the System Control and ID Register not in the SCB.

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    Macro Definition Documentation

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    ◆ SCnSCB_ICTR_INTLINESNUM_Pos

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    #define SCnSCB_ICTR_INTLINESNUM_Pos   0U
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    ICTR: INTLINESNUM Position

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    ◆ SCnSCB_ICTR_INTLINESNUM_Msk

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    #define SCnSCB_ICTR_INTLINESNUM_Msk   (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)
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    ICTR: INTLINESNUM Mask

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    ◆ SCnSCB_ACTLR_DISOOFP_Pos

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    #define SCnSCB_ACTLR_DISOOFP_Pos   9U
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    ACTLR: DISOOFP Position

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    ◆ SCnSCB_ACTLR_DISOOFP_Msk

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    #define SCnSCB_ACTLR_DISOOFP_Msk   (1UL << SCnSCB_ACTLR_DISOOFP_Pos)
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    ACTLR: DISOOFP Mask

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    ◆ SCnSCB_ACTLR_DISFPCA_Pos

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    #define SCnSCB_ACTLR_DISFPCA_Pos   8U
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    ACTLR: DISFPCA Position

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    ◆ SCnSCB_ACTLR_DISFPCA_Msk

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    #define SCnSCB_ACTLR_DISFPCA_Msk   (1UL << SCnSCB_ACTLR_DISFPCA_Pos)
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    ACTLR: DISFPCA Mask

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    ◆ SCnSCB_ACTLR_DISFOLD_Pos

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    #define SCnSCB_ACTLR_DISFOLD_Pos   2U
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    ACTLR: DISFOLD Position

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    ◆ SCnSCB_ACTLR_DISFOLD_Msk

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    #define SCnSCB_ACTLR_DISFOLD_Msk   (1UL << SCnSCB_ACTLR_DISFOLD_Pos)
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    ACTLR: DISFOLD Mask

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    ◆ SCnSCB_ACTLR_DISDEFWBUF_Pos

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    #define SCnSCB_ACTLR_DISDEFWBUF_Pos   1U
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    ACTLR: DISDEFWBUF Position

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    ◆ SCnSCB_ACTLR_DISDEFWBUF_Msk

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    #define SCnSCB_ACTLR_DISDEFWBUF_Msk   (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)
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    ACTLR: DISDEFWBUF Mask

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    ◆ SCnSCB_ACTLR_DISMCYCINT_Pos

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    #define SCnSCB_ACTLR_DISMCYCINT_Pos   0U
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    ACTLR: DISMCYCINT Position

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    ◆ SCnSCB_ACTLR_DISMCYCINT_Msk

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    #define SCnSCB_ACTLR_DISMCYCINT_Msk   (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)
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    ACTLR: DISMCYCINT Mask

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    - - diff --git a/DOCS/html/group___c_m_s_i_s___s_cn_s_c_b.map b/DOCS/html/group___c_m_s_i_s___s_cn_s_c_b.map deleted file mode 100644 index cd35632..0000000 --- a/DOCS/html/group___c_m_s_i_s___s_cn_s_c_b.map +++ /dev/null @@ -1,5 +0,0 @@ - - - - - diff --git a/DOCS/html/group___c_m_s_i_s___s_cn_s_c_b.md5 b/DOCS/html/group___c_m_s_i_s___s_cn_s_c_b.md5 deleted file mode 100644 index 15ba6a6..0000000 --- a/DOCS/html/group___c_m_s_i_s___s_cn_s_c_b.md5 +++ /dev/null @@ -1 +0,0 @@ -5e61e0e08f29e75264415ef523c575fa \ No newline at end of file diff --git a/DOCS/html/group___c_m_s_i_s___s_cn_s_c_b.png b/DOCS/html/group___c_m_s_i_s___s_cn_s_c_b.png deleted file mode 100644 index 152538941b8064416c08fc4437d2e6663410635a..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 2423 zcmZ`*X*3&%7LKJ9RUKnmwdGK2RS9KCEVWaKQc^Yctu-Z-5L*asHK={97SU>Tnh<-e zL5oSNYH5g&5@RW$5~)F~edfIP=e={@ch9-^e&^mF-=BNFo9^UjD=sP{3IG7a?d_~? z008__$G!eZq2ql1mq?%EBINI2YX$i6PgIg$7XSbvm+Y;~U1Q7EXB;x+Y~?B3@ErTa zd%eStuuhWwkqu6#?Y#Xp4D38}&+sevO8k^Bcb|fsOYY}8b2448%#fXJB#5;4&z;LO z^h5h50#dYtgG7+^^^E}w@4Mbz!B*rYBoN~99eCX4zTJhm+wu4#69{qdx=H+1tN%g% zyudkaZ?vj?J{2K&p|7}_#kuU$eb7o;_`}~=0T&JtV&TSuqY@Gl_Tw25uAow=_mh$3 z5t2MMiW&t@tm4r-GbEJlBf<9hlg~u#X+tOGMzQr0e`750$9rxmNCd@s0B!o?cE0i* zMz$q5B-)~(nN0QyS8u$jT42vm6l8q)5*QFrwXXA0ZF_tB$*0>0>`#k}9||7udNjG; z*lgW$$E=YonQZH0DCIY5HsHp+rOL- zh=|IM5umlTe07o3_5OWY-Y;tz?lI-d&XWn+6I0+WX?eeb^4}YXPoj4;G*(<{5G zq0x!CMbL+!ESp8(#~4=vxF&aa=n7&?8Mo)(Pr{#45!!N}OsY&L>C%iQcD=0})W4(k z%$Y+s`_|V-_r1$GX~~?E6tDyZn=NE-LTd*GLrA36y66(D1WvJ3wMTJHcK1T!?C^NA zwB@2{9}k9l;U#xe7owKYCL3usM_4B{*6vh~c_{>ih~P7d(o0cMH3^g{R5AIU98YE= zWbQ+8Ksqs0%N*WdqX~t8JLv8b_o8kKqDAR^mr1hM&|Ylez27jUssV%`=i5izi*?!_ zUD6#JYRcK8dmkkWMx2oFJ_i5zD!FzXLSI zdpWnqVM=kUL`9vr^d}gD+v!pT3U^y?qHXfIWVhsVDKP?@0}Bq<`Sx3c?nbaazluU4 z3$n7ZR)S)<9z72k3`T&#Gp};T*UQ&V@9W&-YZF8Z^0ad#S1)qL5ldHcQ1a$CFr-&1G?49HQYwUo`F&1Q2ppzzkseTkK$qd7|dss|xHd?R{Ur-X7O2vOC2*+~2_gl1`&jYRIq; z)la?7_5=Bn+S>HlgGHJWtt8Tm;x|dY^ean>Sw_gOL!9v0u3ed_cTH}|cMJ`|4TFSU zhJLEsDv!HBY5^+Uq-4wQt4-~tY3C(=H8VE=gZ!g!fP|BT4)DX$2*+~pmiQc0Hrl~V z<9TlNp$Knwep_xscZxK+!_RR#Dm_rq(i$|5|2tTAVo+x&8Fwk{I-ifKL-zHEd#hFI zCyq{bOv+ zAo`Y+A_U^uT1A|`_PYm}BU!@QF}GNVc%x@yLKyD+>h)`Qo|limFz?KUwJ)^Tb3c=2 z?^r})w4!C1B=q~9yq6FCpMRskp_H~SJ{L6!S&4)4SA>%~+Y-fim!?E{BYB@LbPgNs z*x2bhF9|n>)*&?r-*)NTw(;{-6^)HD2cY^MelzbcrZyzs&7iplfge(*?+C-E!+hY3 zI3{>+_S`9aURXX$BD}NyaqRB74Y5YQzjpG(#eX~s?YEG70=8tNk{(H2pB!dTfyv1 z6cux^k=@)`#%`PE>vWg%ZmbM6;A@@-gDa|6$5ckKesD&)4`Fm%`zg@@So!c>3M$af zO}|<1t-A|1YQ5{#Gce)O(##H>oQkCuwl&w*Eugmj{2Kf^%N%q4aw zcv5fNE6JnK$u)3KCs@$3qqn)T{!{pO*Z{RyPYpUUVHY zJz>yFh}a!H`G0M8s6*XFtibAYN5anKrm32LY+Jz;O-G%48#dGNs{88cwir&uR=cIh zK=73g6WmDMY+FPXtupX1)251npg6&wR=WX>V@FZapY^K7R^k~TSACf*B8S6i>gi#k h)Q_$Fzd`0=I$!6=0t2qq9)D5*duvB4qJ{7Me*w@V&Da0{ diff --git a/DOCS/html/group___c_m_s_i_s___sys_tick.html b/DOCS/html/group___c_m_s_i_s___sys_tick.html deleted file mode 100644 index 689ce29..0000000 --- a/DOCS/html/group___c_m_s_i_s___sys_tick.html +++ /dev/null @@ -1,427 +0,0 @@ - - - - - - - -STM MATLAB Simulator: System Tick Timer (SysTick) - - - - - - - - - - - -
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    System Tick Timer (SysTick)
    Defines and Type Definitions » Status and Control Registers » Nested Vectored Interrupt Controller (NVIC) » System Control Block (SCB) » System Controls not in SCB (SCnSCB)
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    struct  SysTick_Type
     Structure type to access the System Timer (SysTick). More...
     
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    #define SysTick_CTRL_COUNTFLAG_Pos   16U
     
    #define SysTick_CTRL_COUNTFLAG_Msk   (1UL << SysTick_CTRL_COUNTFLAG_Pos)
     
    #define SysTick_CTRL_CLKSOURCE_Pos   2U
     
    #define SysTick_CTRL_CLKSOURCE_Msk   (1UL << SysTick_CTRL_CLKSOURCE_Pos)
     
    #define SysTick_CTRL_TICKINT_Pos   1U
     
    #define SysTick_CTRL_TICKINT_Msk   (1UL << SysTick_CTRL_TICKINT_Pos)
     
    #define SysTick_CTRL_ENABLE_Pos   0U
     
    #define SysTick_CTRL_ENABLE_Msk   (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)
     
    #define SysTick_LOAD_RELOAD_Pos   0U
     
    #define SysTick_LOAD_RELOAD_Msk   (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)
     
    #define SysTick_VAL_CURRENT_Pos   0U
     
    #define SysTick_VAL_CURRENT_Msk   (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)
     
    #define SysTick_CALIB_NOREF_Pos   31U
     
    #define SysTick_CALIB_NOREF_Msk   (1UL << SysTick_CALIB_NOREF_Pos)
     
    #define SysTick_CALIB_SKEW_Pos   30U
     
    #define SysTick_CALIB_SKEW_Msk   (1UL << SysTick_CALIB_SKEW_Pos)
     
    #define SysTick_CALIB_TENMS_Pos   0U
     
    #define SysTick_CALIB_TENMS_Msk   (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)
     
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    Type definitions for the System Timer Registers.

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    Macro Definition Documentation

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    ◆ SysTick_CTRL_COUNTFLAG_Pos

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    #define SysTick_CTRL_COUNTFLAG_Pos   16U
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    SysTick CTRL: COUNTFLAG Position

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    #define SysTick_CTRL_COUNTFLAG_Msk   (1UL << SysTick_CTRL_COUNTFLAG_Pos)
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    SysTick CTRL: COUNTFLAG Mask

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    SysTick CTRL: CLKSOURCE Position

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    SysTick CTRL: TICKINT Position

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    SysTick CTRL: TICKINT Mask

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    SysTick LOAD: RELOAD Position

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    SysTick VAL: CURRENT Position

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    SysTick VAL: CURRENT Mask

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    SysTick CALIB: NOREF Position

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    #define SysTick_CALIB_NOREF_Msk   (1UL << SysTick_CALIB_NOREF_Pos)
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    SysTick CALIB: TENMS Mask

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    - - diff --git a/DOCS/html/group___c_m_s_i_s___sys_tick.map b/DOCS/html/group___c_m_s_i_s___sys_tick.map deleted file mode 100644 index 102a0bb..0000000 --- a/DOCS/html/group___c_m_s_i_s___sys_tick.map +++ /dev/null @@ -1,5 +0,0 @@ - - - - - diff --git a/DOCS/html/group___c_m_s_i_s___sys_tick.md5 b/DOCS/html/group___c_m_s_i_s___sys_tick.md5 deleted file mode 100644 index 9492a0c..0000000 --- a/DOCS/html/group___c_m_s_i_s___sys_tick.md5 +++ /dev/null @@ -1 +0,0 @@ -3fbe3eccfd3d56a8d5a1af7eed29bad7 \ No newline at end of file diff --git a/DOCS/html/group___c_m_s_i_s___sys_tick.png b/DOCS/html/group___c_m_s_i_s___sys_tick.png deleted file mode 100644 index a1085f39296c2b29912df8b062ccfbc9b7555f1a..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 2493 zcmV;u2}1UXP)PfyjadnZ-DuCDF|h=_=Yh=_=Yh=_=Yh=_=Y`Y)+2IC${jjwDI;h6skbEz7d+ zj~qGjTj)4U42Q%0p<|#prD=L*JRTnp9fyh0XmtNc+2z#*Ns{bM zlH{nLkf>*#2C(Hv)&=~{lgMl~I|g81=r~NwX0tbvBzY=y9Mmh#i9}&M9=i>NdSx^k zg$|*$!C-);rKQkeP(;?&)-at;Lx<7I?%lh4@&A*;T3ubmWHPD!EcF}<5fKsf2onh+ zA|f)zM1qKjh>S6jAR;0nV@xE7h=|A-6A2^2mzU!m#VsArq;;XJ}bGuyiH@@-I#$4SW zG0QS(#z;g&wCJ2B64h+0tnPjBs;;B5Zgu@?Ii?ALXrx8A{_1v!mZ`+5vtC_1vT{WG zoYYj0zRT*~7q99%D(hC)ua?v1ZicG$H+|2fKHY6n**9dyRvS`XChHG$+i@H1vB|cW z)~`#quQ2_r4J)TMsz>g+!!x2&3PriH;UC%iBBt_t+oxKZ>KAQ?XkAgcs`bm(SE)}F zD_v?l9$(Ty=?=|Thxm*4MY*!m0kZc+Og85pG}YggUgikv4*@&&F3?>Bb)Qvurmz9%( zrVg!5XIK5M>yFcP5>Z!&Y1vF7+EZ;qY_>(V+HqU4o3d4|=^PDT?Z34|qD(gf(;d-R z>sN(vAX*Ec)e;vcJ9oStv`6(6&f*i z(lP(Q4P67^1pr?I*cmt$>qMtDY)*vqEp+`d5yf@|fJXs*1mN+&u{aT9TVx}q7`IEL zDOTC%Hn-EsWXtk$lkdwW>9`zDQz^Sm{j$VFwOm`k^G(S=))7ZK>9;G8e?Q(EFw$1@HiXXXmeL=gYqg7Lh}3+7MBnVLJvH zQNN;dP#NO%jx1JLJT7D1@|PSAhx?NxIqK>^WQ<4o)ZS<`LY8GuPbQPk1goR~_5#?C zd<5be0RJLCax2^h;8&M%iX1w0C>sn0SXx@LUN)~B=&rT3HB6_|W0T2bpJcT=0qg_t z3VElMACa2@W4Vyd`gNGTD--Z1^d+Lm-3s6t07C$`n;hUPP+;D$iuS$?gMZUo4;o!545nnHR?o*e-)F^4g$CtdE+aa7x5JWO}2C~$&z~I zcK{#EUpoOjiF|V9U1(00e*o~g>j3L)+qP|ghtJ4vMkVxImv~{zSnB$3UyEXg` z;0tUvwg-?;WcxQ{P(&?d0KNzCI)EFHC(9oL*a#UEkq=%HiE`&w{5wg^pNX#eAh5P{ z9y+GGj>&#-wcP;|kUx<(wvPa~5&3y&s-g2Ru=01RWmMl6FWp#7%BkLgvd1?`x`;eE zei6X-`M(#I&YdEQ_OPx!5`9)~OWTyw^qC4<&z(})Uojmx2AOQBdcMi_Ej`=Z#@kgq zb^9T2&o@*-mD<++~{L|Bw z2FiTJ6WexEd~~m<@b$2(9-qD-2SN|khpxY?qMmHo=8x*)2jMH8*tVPEW21u}kH`PN zTy^-a%cuS*Ur83~fT>(R58Bj4ok*zAnaIUf5fKp?VTLg)}$ zJAL{z+jDB|{Q2|3&$c8IX_}sy&1T0=o;>L^DC(ayP0xgm!Bm!I$2K-LLWe;SO4Ias z=on0;X?lEpeI4uT>!Cv-A|fIpA|fIpA|fIpA|fIp>a_m=ZW`m@n(Mh000000NkvXX Hu0mjfvzW~X diff --git a/DOCS/html/group___c_m_s_i_s___t_p_i.html b/DOCS/html/group___c_m_s_i_s___t_p_i.html deleted file mode 100644 index ea6855b..0000000 --- a/DOCS/html/group___c_m_s_i_s___t_p_i.html +++ /dev/null @@ -1,1345 +0,0 @@ - - - - - - - -STM MATLAB Simulator: Trace Port Interface (TPI) - - - - - - - - - - - -
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    Defines and Type Definitions » Status and Control Registers » Nested Vectored Interrupt Controller (NVIC) » System Control Block (SCB) » System Controls not in SCB (SCnSCB) » System Tick Timer (SysTick) » Instrumentation Trace Macrocell (ITM) » Data Watchpoint and Trace (DWT)
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    struct  TPI_Type
     Structure type to access the Trace Port Interface Register (TPI). More...
     
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    -Macros

    #define TPI_ACPR_PRESCALER_Pos   0U
     
    #define TPI_ACPR_PRESCALER_Msk   (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)
     
    #define TPI_SPPR_TXMODE_Pos   0U
     
    #define TPI_SPPR_TXMODE_Msk   (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)
     
    #define TPI_FFSR_FtNonStop_Pos   3U
     
    #define TPI_FFSR_FtNonStop_Msk   (0x1UL << TPI_FFSR_FtNonStop_Pos)
     
    #define TPI_FFSR_TCPresent_Pos   2U
     
    #define TPI_FFSR_TCPresent_Msk   (0x1UL << TPI_FFSR_TCPresent_Pos)
     
    #define TPI_FFSR_FtStopped_Pos   1U
     
    #define TPI_FFSR_FtStopped_Msk   (0x1UL << TPI_FFSR_FtStopped_Pos)
     
    #define TPI_FFSR_FlInProg_Pos   0U
     
    #define TPI_FFSR_FlInProg_Msk   (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)
     
    #define TPI_FFCR_TrigIn_Pos   8U
     
    #define TPI_FFCR_TrigIn_Msk   (0x1UL << TPI_FFCR_TrigIn_Pos)
     
    #define TPI_FFCR_EnFCont_Pos   1U
     
    #define TPI_FFCR_EnFCont_Msk   (0x1UL << TPI_FFCR_EnFCont_Pos)
     
    #define TPI_TRIGGER_TRIGGER_Pos   0U
     
    #define TPI_TRIGGER_TRIGGER_Msk   (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)
     
    #define TPI_FIFO0_ITM_ATVALID_Pos   29U
     
    #define TPI_FIFO0_ITM_ATVALID_Msk   (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)
     
    #define TPI_FIFO0_ITM_bytecount_Pos   27U
     
    #define TPI_FIFO0_ITM_bytecount_Msk   (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)
     
    #define TPI_FIFO0_ETM_ATVALID_Pos   26U
     
    #define TPI_FIFO0_ETM_ATVALID_Msk   (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)
     
    #define TPI_FIFO0_ETM_bytecount_Pos   24U
     
    #define TPI_FIFO0_ETM_bytecount_Msk   (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)
     
    #define TPI_FIFO0_ETM2_Pos   16U
     
    #define TPI_FIFO0_ETM2_Msk   (0xFFUL << TPI_FIFO0_ETM2_Pos)
     
    #define TPI_FIFO0_ETM1_Pos   8U
     
    #define TPI_FIFO0_ETM1_Msk   (0xFFUL << TPI_FIFO0_ETM1_Pos)
     
    #define TPI_FIFO0_ETM0_Pos   0U
     
    #define TPI_FIFO0_ETM0_Msk   (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)
     
    #define TPI_ITATBCTR2_ATREADY2_Pos   0U
     
    #define TPI_ITATBCTR2_ATREADY2_Msk   (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/)
     
    #define TPI_ITATBCTR2_ATREADY1_Pos   0U
     
    #define TPI_ITATBCTR2_ATREADY1_Msk   (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/)
     
    #define TPI_FIFO1_ITM_ATVALID_Pos   29U
     
    #define TPI_FIFO1_ITM_ATVALID_Msk   (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)
     
    #define TPI_FIFO1_ITM_bytecount_Pos   27U
     
    #define TPI_FIFO1_ITM_bytecount_Msk   (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)
     
    #define TPI_FIFO1_ETM_ATVALID_Pos   26U
     
    #define TPI_FIFO1_ETM_ATVALID_Msk   (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)
     
    #define TPI_FIFO1_ETM_bytecount_Pos   24U
     
    #define TPI_FIFO1_ETM_bytecount_Msk   (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)
     
    #define TPI_FIFO1_ITM2_Pos   16U
     
    #define TPI_FIFO1_ITM2_Msk   (0xFFUL << TPI_FIFO1_ITM2_Pos)
     
    #define TPI_FIFO1_ITM1_Pos   8U
     
    #define TPI_FIFO1_ITM1_Msk   (0xFFUL << TPI_FIFO1_ITM1_Pos)
     
    #define TPI_FIFO1_ITM0_Pos   0U
     
    #define TPI_FIFO1_ITM0_Msk   (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)
     
    #define TPI_ITATBCTR0_ATREADY2_Pos   0U
     
    #define TPI_ITATBCTR0_ATREADY2_Msk   (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/)
     
    #define TPI_ITATBCTR0_ATREADY1_Pos   0U
     
    #define TPI_ITATBCTR0_ATREADY1_Msk   (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/)
     
    #define TPI_ITCTRL_Mode_Pos   0U
     
    #define TPI_ITCTRL_Mode_Msk   (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/)
     
    #define TPI_DEVID_NRZVALID_Pos   11U
     
    #define TPI_DEVID_NRZVALID_Msk   (0x1UL << TPI_DEVID_NRZVALID_Pos)
     
    #define TPI_DEVID_MANCVALID_Pos   10U
     
    #define TPI_DEVID_MANCVALID_Msk   (0x1UL << TPI_DEVID_MANCVALID_Pos)
     
    #define TPI_DEVID_PTINVALID_Pos   9U
     
    #define TPI_DEVID_PTINVALID_Msk   (0x1UL << TPI_DEVID_PTINVALID_Pos)
     
    #define TPI_DEVID_MinBufSz_Pos   6U
     
    #define TPI_DEVID_MinBufSz_Msk   (0x7UL << TPI_DEVID_MinBufSz_Pos)
     
    #define TPI_DEVID_AsynClkIn_Pos   5U
     
    #define TPI_DEVID_AsynClkIn_Msk   (0x1UL << TPI_DEVID_AsynClkIn_Pos)
     
    #define TPI_DEVID_NrTraceInput_Pos   0U
     
    #define TPI_DEVID_NrTraceInput_Msk   (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)
     
    #define TPI_DEVTYPE_SubType_Pos   4U
     
    #define TPI_DEVTYPE_SubType_Msk   (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)
     
    #define TPI_DEVTYPE_MajorType_Pos   0U
     
    #define TPI_DEVTYPE_MajorType_Msk   (0xFUL << TPI_DEVTYPE_MajorType_Pos)
     
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    Detailed Description

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    Type definitions for the Trace Port Interface (TPI)

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    Macro Definition Documentation

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    ◆ TPI_ACPR_PRESCALER_Pos

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    #define TPI_ACPR_PRESCALER_Pos   0U
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    TPI ACPR: PRESCALER Position

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    ◆ TPI_ACPR_PRESCALER_Msk

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    #define TPI_ACPR_PRESCALER_Msk   (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)
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    TPI ACPR: PRESCALER Mask

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    ◆ TPI_SPPR_TXMODE_Pos

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    #define TPI_SPPR_TXMODE_Pos   0U
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    TPI SPPR: TXMODE Position

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    ◆ TPI_SPPR_TXMODE_Msk

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    #define TPI_SPPR_TXMODE_Msk   (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)
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    TPI SPPR: TXMODE Mask

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    ◆ TPI_FFSR_FtNonStop_Pos

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    #define TPI_FFSR_FtNonStop_Pos   3U
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    TPI FFSR: FtNonStop Position

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    ◆ TPI_FFSR_FtNonStop_Msk

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    #define TPI_FFSR_FtNonStop_Msk   (0x1UL << TPI_FFSR_FtNonStop_Pos)
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    TPI FFSR: FtNonStop Mask

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    ◆ TPI_FFSR_TCPresent_Pos

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    #define TPI_FFSR_TCPresent_Pos   2U
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    TPI FFSR: TCPresent Position

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    ◆ TPI_FFSR_TCPresent_Msk

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    #define TPI_FFSR_TCPresent_Msk   (0x1UL << TPI_FFSR_TCPresent_Pos)
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    TPI FFSR: TCPresent Mask

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    ◆ TPI_FFSR_FtStopped_Pos

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    #define TPI_FFSR_FtStopped_Pos   1U
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    TPI FFSR: FtStopped Position

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    ◆ TPI_FFSR_FtStopped_Msk

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    #define TPI_FFSR_FtStopped_Msk   (0x1UL << TPI_FFSR_FtStopped_Pos)
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    TPI FFSR: FtStopped Mask

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    ◆ TPI_FFSR_FlInProg_Pos

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    #define TPI_FFSR_FlInProg_Pos   0U
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    TPI FFSR: FlInProg Position

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    ◆ TPI_FFSR_FlInProg_Msk

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    #define TPI_FFSR_FlInProg_Msk   (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)
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    TPI FFSR: FlInProg Mask

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    ◆ TPI_FFCR_TrigIn_Pos

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    #define TPI_FFCR_TrigIn_Pos   8U
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    TPI FFCR: TrigIn Position

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    ◆ TPI_FFCR_TrigIn_Msk

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    #define TPI_FFCR_TrigIn_Msk   (0x1UL << TPI_FFCR_TrigIn_Pos)
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    TPI FFCR: TrigIn Mask

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    ◆ TPI_FFCR_EnFCont_Pos

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    #define TPI_FFCR_EnFCont_Pos   1U
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    TPI FFCR: EnFCont Position

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    ◆ TPI_FFCR_EnFCont_Msk

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    #define TPI_FFCR_EnFCont_Msk   (0x1UL << TPI_FFCR_EnFCont_Pos)
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    TPI FFCR: EnFCont Mask

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    ◆ TPI_TRIGGER_TRIGGER_Pos

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    #define TPI_TRIGGER_TRIGGER_Pos   0U
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    TPI TRIGGER: TRIGGER Position

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    ◆ TPI_TRIGGER_TRIGGER_Msk

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    #define TPI_TRIGGER_TRIGGER_Msk   (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)
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    TPI TRIGGER: TRIGGER Mask

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    ◆ TPI_FIFO0_ITM_ATVALID_Pos

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    #define TPI_FIFO0_ITM_ATVALID_Pos   29U
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    TPI FIFO0: ITM_ATVALID Position

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    ◆ TPI_FIFO0_ITM_ATVALID_Msk

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    #define TPI_FIFO0_ITM_ATVALID_Msk   (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)
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    TPI FIFO0: ITM_ATVALID Mask

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    ◆ TPI_FIFO0_ITM_bytecount_Pos

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    #define TPI_FIFO0_ITM_bytecount_Pos   27U
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    TPI FIFO0: ITM_bytecount Position

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    ◆ TPI_FIFO0_ITM_bytecount_Msk

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    #define TPI_FIFO0_ITM_bytecount_Msk   (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)
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    TPI FIFO0: ITM_bytecount Mask

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    ◆ TPI_FIFO0_ETM_ATVALID_Pos

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    #define TPI_FIFO0_ETM_ATVALID_Pos   26U
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    TPI FIFO0: ETM_ATVALID Position

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    ◆ TPI_FIFO0_ETM_ATVALID_Msk

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    #define TPI_FIFO0_ETM_ATVALID_Msk   (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)
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    TPI FIFO0: ETM_ATVALID Mask

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    ◆ TPI_FIFO0_ETM_bytecount_Pos

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    #define TPI_FIFO0_ETM_bytecount_Pos   24U
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    TPI FIFO0: ETM_bytecount Position

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    ◆ TPI_FIFO0_ETM_bytecount_Msk

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    #define TPI_FIFO0_ETM_bytecount_Msk   (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)
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    TPI FIFO0: ETM_bytecount Mask

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    ◆ TPI_FIFO0_ETM2_Pos

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    #define TPI_FIFO0_ETM2_Pos   16U
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    TPI FIFO0: ETM2 Position

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    ◆ TPI_FIFO0_ETM2_Msk

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    #define TPI_FIFO0_ETM2_Msk   (0xFFUL << TPI_FIFO0_ETM2_Pos)
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    TPI FIFO0: ETM2 Mask

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    ◆ TPI_FIFO0_ETM1_Pos

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    #define TPI_FIFO0_ETM1_Pos   8U
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    TPI FIFO0: ETM1 Position

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    ◆ TPI_FIFO0_ETM1_Msk

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    #define TPI_FIFO0_ETM1_Msk   (0xFFUL << TPI_FIFO0_ETM1_Pos)
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    TPI FIFO0: ETM1 Mask

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    ◆ TPI_FIFO0_ETM0_Pos

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    #define TPI_FIFO0_ETM0_Pos   0U
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    TPI FIFO0: ETM0 Position

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    ◆ TPI_FIFO0_ETM0_Msk

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    #define TPI_FIFO0_ETM0_Msk   (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)
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    TPI FIFO0: ETM0 Mask

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    ◆ TPI_ITATBCTR2_ATREADY2_Pos

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    #define TPI_ITATBCTR2_ATREADY2_Pos   0U
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    TPI ITATBCTR2: ATREADY2 Position

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    ◆ TPI_ITATBCTR2_ATREADY2_Msk

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    #define TPI_ITATBCTR2_ATREADY2_Msk   (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/)
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    TPI ITATBCTR2: ATREADY2 Mask

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    ◆ TPI_ITATBCTR2_ATREADY1_Pos

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    #define TPI_ITATBCTR2_ATREADY1_Pos   0U
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    TPI ITATBCTR2: ATREADY1 Position

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    ◆ TPI_ITATBCTR2_ATREADY1_Msk

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    #define TPI_ITATBCTR2_ATREADY1_Msk   (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/)
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    TPI ITATBCTR2: ATREADY1 Mask

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    ◆ TPI_FIFO1_ITM_ATVALID_Pos

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    #define TPI_FIFO1_ITM_ATVALID_Pos   29U
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    TPI FIFO1: ITM_ATVALID Position

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    ◆ TPI_FIFO1_ITM_ATVALID_Msk

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    #define TPI_FIFO1_ITM_ATVALID_Msk   (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)
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    TPI FIFO1: ITM_ATVALID Mask

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    ◆ TPI_FIFO1_ITM_bytecount_Pos

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    #define TPI_FIFO1_ITM_bytecount_Pos   27U
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    TPI FIFO1: ITM_bytecount Position

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    ◆ TPI_FIFO1_ITM_bytecount_Msk

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    #define TPI_FIFO1_ITM_bytecount_Msk   (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)
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    TPI FIFO1: ITM_bytecount Mask

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    ◆ TPI_FIFO1_ETM_ATVALID_Pos

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    #define TPI_FIFO1_ETM_ATVALID_Pos   26U
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    TPI FIFO1: ETM_ATVALID Position

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    ◆ TPI_FIFO1_ETM_ATVALID_Msk

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    #define TPI_FIFO1_ETM_ATVALID_Msk   (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)
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    TPI FIFO1: ETM_ATVALID Mask

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    ◆ TPI_FIFO1_ETM_bytecount_Pos

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    #define TPI_FIFO1_ETM_bytecount_Pos   24U
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    TPI FIFO1: ETM_bytecount Position

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    ◆ TPI_FIFO1_ETM_bytecount_Msk

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    #define TPI_FIFO1_ETM_bytecount_Msk   (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)
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    TPI FIFO1: ETM_bytecount Mask

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    ◆ TPI_FIFO1_ITM2_Pos

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    #define TPI_FIFO1_ITM2_Pos   16U
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    TPI FIFO1: ITM2 Position

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    ◆ TPI_FIFO1_ITM2_Msk

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    #define TPI_FIFO1_ITM2_Msk   (0xFFUL << TPI_FIFO1_ITM2_Pos)
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    TPI FIFO1: ITM2 Mask

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    ◆ TPI_FIFO1_ITM1_Pos

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    #define TPI_FIFO1_ITM1_Pos   8U
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    TPI FIFO1: ITM1 Position

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    ◆ TPI_FIFO1_ITM1_Msk

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    #define TPI_FIFO1_ITM1_Msk   (0xFFUL << TPI_FIFO1_ITM1_Pos)
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    TPI FIFO1: ITM1 Mask

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    ◆ TPI_FIFO1_ITM0_Pos

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    #define TPI_FIFO1_ITM0_Pos   0U
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    TPI FIFO1: ITM0 Position

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    ◆ TPI_FIFO1_ITM0_Msk

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    #define TPI_FIFO1_ITM0_Msk   (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)
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    TPI FIFO1: ITM0 Mask

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    ◆ TPI_ITATBCTR0_ATREADY2_Pos

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    #define TPI_ITATBCTR0_ATREADY2_Pos   0U
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    TPI ITATBCTR0: ATREADY2 Position

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    ◆ TPI_ITATBCTR0_ATREADY2_Msk

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    #define TPI_ITATBCTR0_ATREADY2_Msk   (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/)
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    TPI ITATBCTR0: ATREADY2 Mask

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    ◆ TPI_ITATBCTR0_ATREADY1_Pos

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    #define TPI_ITATBCTR0_ATREADY1_Pos   0U
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    TPI ITATBCTR0: ATREADY1 Position

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    ◆ TPI_ITATBCTR0_ATREADY1_Msk

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    #define TPI_ITATBCTR0_ATREADY1_Msk   (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/)
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    TPI ITATBCTR0: ATREADY1 Mask

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    ◆ TPI_ITCTRL_Mode_Pos

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    #define TPI_ITCTRL_Mode_Pos   0U
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    TPI ITCTRL: Mode Position

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    ◆ TPI_ITCTRL_Mode_Msk

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    #define TPI_ITCTRL_Mode_Msk   (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/)
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    TPI ITCTRL: Mode Mask

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    ◆ TPI_DEVID_NRZVALID_Pos

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    #define TPI_DEVID_NRZVALID_Pos   11U
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    TPI DEVID: NRZVALID Position

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    ◆ TPI_DEVID_NRZVALID_Msk

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    #define TPI_DEVID_NRZVALID_Msk   (0x1UL << TPI_DEVID_NRZVALID_Pos)
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    TPI DEVID: NRZVALID Mask

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    ◆ TPI_DEVID_MANCVALID_Pos

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    #define TPI_DEVID_MANCVALID_Pos   10U
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    TPI DEVID: MANCVALID Position

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    ◆ TPI_DEVID_MANCVALID_Msk

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    #define TPI_DEVID_MANCVALID_Msk   (0x1UL << TPI_DEVID_MANCVALID_Pos)
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    TPI DEVID: MANCVALID Mask

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    ◆ TPI_DEVID_PTINVALID_Pos

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    #define TPI_DEVID_PTINVALID_Pos   9U
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    TPI DEVID: PTINVALID Position

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    ◆ TPI_DEVID_PTINVALID_Msk

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    #define TPI_DEVID_PTINVALID_Msk   (0x1UL << TPI_DEVID_PTINVALID_Pos)
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    TPI DEVID: PTINVALID Mask

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    ◆ TPI_DEVID_MinBufSz_Pos

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    #define TPI_DEVID_MinBufSz_Pos   6U
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    TPI DEVID: MinBufSz Position

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    ◆ TPI_DEVID_MinBufSz_Msk

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    #define TPI_DEVID_MinBufSz_Msk   (0x7UL << TPI_DEVID_MinBufSz_Pos)
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    TPI DEVID: MinBufSz Mask

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    ◆ TPI_DEVID_AsynClkIn_Pos

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    #define TPI_DEVID_AsynClkIn_Pos   5U
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    ◆ TPI_DEVID_AsynClkIn_Msk

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    #define TPI_DEVID_AsynClkIn_Msk   (0x1UL << TPI_DEVID_AsynClkIn_Pos)
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    TPI DEVID: AsynClkIn Mask

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    #define TPI_DEVID_NrTraceInput_Pos   0U
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    ◆ TPI_DEVID_NrTraceInput_Msk

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    #define TPI_DEVID_NrTraceInput_Msk   (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)
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    TPI DEVID: NrTraceInput Mask

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    #define TPI_DEVTYPE_SubType_Pos   4U
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    #define TPI_DEVTYPE_SubType_Msk   (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)
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    TPI DEVTYPE: SubType Mask

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    ◆ TPI_DEVTYPE_MajorType_Pos

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    #define TPI_DEVTYPE_MajorType_Pos   0U
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    TPI DEVTYPE: MajorType Position

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    ◆ TPI_DEVTYPE_MajorType_Msk

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    #define TPI_DEVTYPE_MajorType_Msk   (0xFUL << TPI_DEVTYPE_MajorType_Pos)
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    TPI DEVTYPE: MajorType Mask

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    -Generated by doxygen 1.10.0 -
    - - diff --git a/DOCS/html/group___c_m_s_i_s___t_p_i.map b/DOCS/html/group___c_m_s_i_s___t_p_i.map deleted file mode 100644 index e797b54..0000000 --- a/DOCS/html/group___c_m_s_i_s___t_p_i.map +++ /dev/null @@ -1,5 +0,0 @@ - - - - - diff --git a/DOCS/html/group___c_m_s_i_s___t_p_i.md5 b/DOCS/html/group___c_m_s_i_s___t_p_i.md5 deleted file mode 100644 index 2564368..0000000 --- a/DOCS/html/group___c_m_s_i_s___t_p_i.md5 +++ /dev/null @@ -1 +0,0 @@ -cd23aa62ba3b51b29eb20375f60e8580 \ No newline at end of file diff --git a/DOCS/html/group___c_m_s_i_s___t_p_i.png b/DOCS/html/group___c_m_s_i_s___t_p_i.png deleted file mode 100644 index 40e734e7bed7ffdcf358a491d0d7100ec134f017..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 2214 zcmV;X2wC@uP)xtp2_!f` zSVMpiFdok-mne!NPy|;F`2*JD6DI=}33rrS$Xc@27le^=SXt3>bF$;ak_7~2IP?te zt?ifUm+I=5-$xqR+b>m5&-Ol5-Cf-cA|fIpA|fIpA|fIpA|fIphXv+@lP6E!69mDA zk6@%57K_F9nKNg;^c_bL>+M4e$q@i|qcbUy*zQZWx*s)`s_*<1?c6N4{PN%W+1~tbb zA|fIUrA~o}h=>5{6o`n3$dWn*A|fIJs8b*!A|gxb6o`n32#|71Vje+o=ov^X7KuDsK$th;GtmeI6$nk4O(E}ysbCdK6{rpaVd+xD)uO}9+fCoaFkjU3;WJeai| zHtSarQx$EK%e-7krvMIrv3Y}b(O4HL(|04-gq=d{L>s0$8%7&(u@sH5%55uCR@1)Y zK5?CE%zWmmzA}w*lX7#k{Hp77cKKk{D7%)Y9yO#QA|lBuJ5yjQ+JHw-Kdt^XdqC#0 zO^jnTKd$!{H!rQsXx&L=B*kg7jd@~I2dcc)(QWi7H+p*CJn}6%uV`#>nH_?p%ML~7m5nKH-FeGj{om{ym5rk*-(??| zxxgl0nLp>ryJ_XR%vW{f=A!Y$m0NXvP;;jsPvCi%jT=XhHod60UyALrRn%A2dbZcl z)G;V8+Ti4Ae9AWZWy&ktNLJOzrj=9Y_Vk_4TxPqjO}?sfP<$O{Qhl7Q^?LcB%4J=~ z(N=xf#x^SYBAPtwwW$#-^J1PlzDuc&@0_GdqS?G(KB!_@mvOXJAGWcL(yobTX;VX= zM^$$t=(}t-<)n6ScK1P^L2x!@Wl6fWl6B1`?~d7&GaY#}C5{X~0Zss)0KIr`aaJRi zHovP!x~`7=8}eP=4r~G+0Y9&+(k60|lUkDJVlQ(v>CU*y&J@@TL@`HFrhPG4%a&0z zj@8da>xrA5x6GtCv+B0}{%Rgaa69k}@CxuGaLaOfJN~*0Fh}K^qu`T9#iz|H8;4DK zuAWs;X1kj5U1qo$_yzD1@Eq`?<@7(htkjpZ+?FTr7OAg_+*L79) z^)>J2wX?IsbUNkq>C=b$0JRS^l-^n;$yW$35B#4SX9jLcT1liu9wfXx@H%iW@C|V5 za-MRn1L_1+Pdlo(v`UgEfOQTg$y<_E5^0fpfoFk}z(X9|$8SwqNvcuxX?Rhmz?nYp zoZH*m4+C!l4;Zs-ljOgvjmX}G3l|s;hrX(pme||dTLZQUFNHC$_^uLv(0+{3{ms4Q;)*BphH>d28JNn;^Iez3m2 zz7PB!coFywa6j-haGPZje**sLCc1Q^(df6pV?OGZ=2NFYT=^V$Yx#K)_%-2Wgu6IA z=*sjlo(39ffT85@FW}wf=KI259k~Sj5qJ~WAWWXG0zW3~AZUDn2U(-f<6httH-EKEnRg|0 zz!$(f%TL};u#}XRhvD!Gi<0I?%Sx&vZJ91;{Elk-ata^Jcx*cXamyqvo3;Hd>KH(H z>*1%%&mVxN2=7LCn(z*U0EZ9Mk{jY0?zF}{ZhF%4aW6jVnN=tFE#Ps&TW>cBpHc7~ zEy%lVl9h)|c@E6d%4kvE%|!{=p}3K;wh!0n>JAt274R3}mxM=CCxE{Z9#x5S!FPmD z=sZFA?2YGuzY^~IB8}9EPQj|7jW)PJ5d83oTfWFVbGfE8+8ubC;s1d5fG2>vmp_Xm zbsWW;PYo2lChQPw0zU&j^BYb#_{_r{$h)yRa~jL$z1?NzNo}t94nV{)FL&1Th0P=P zC0S=W1$nM1C9PM7=(VW0cPw=IT9vd{+);mz#|%h=*^J}LyH1~Urc+=ldRnK8r-MYw zQU^e~LLGo~o$M5pd2hFN7!eWat4<6wOk*=(u;{urb*H^Ty5+YQiimVhRj+k!t4^LN zNPEY&?fbsXc{Vh_MMR|i`uw7$R-GwG`o$z2jYkLZ#m!4w&*lLb=1yaNs@j&Ud41}| zN_k1Q3+8!nQPwg&e|VA9ByZ!LcMy77F7ImIZB?g0L_|c~QKz7UCOo{NtG!im%jLs` zbe2HsTFPJxJsh%Bj7AR;0n zfI0;tA|kSs`0yeP7LvZYa^(uM+01ts(oom0U-unCX_qfwR*vtnt5>fk&O6j87z_q` z^ZEST#ful61|{7!7!3A&$57N_u{d|_n%-~(rdEYS - - - - - - -STM MATLAB Simulator: ITM Functions - - - - - - - - - - - -
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    STM MATLAB Simulator -
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    -Macros | -Functions | -Variables
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    ITM Functions
    Defines and Type Definitions » Status and Control Registers » Nested Vectored Interrupt Controller (NVIC) » System Control Block (SCB) » System Controls not in SCB (SCnSCB) » System Tick Timer (SysTick) » Instrumentation Trace Macrocell (ITM) » Data Watchpoint and Trace (DWT) » Trace Port Interface (TPI) » Floating Point Unit (FPU) » Core Debug Registers (CoreDebug) » Core register bit field macros » Core Definitions | Defines and Type Definitions » Status and Control Registers » Nested Vectored Interrupt Controller (NVIC) » System Control Block (SCB) » System Controls not in SCB (SCnSCB) » System Tick Timer (SysTick) » Instrumentation Trace Macrocell (ITM) » Data Watchpoint and Trace (DWT) » Trace Port Interface (TPI) » Floating Point Unit (FPU) » Core Debug Registers (CoreDebug) » Core register bit field macros » Core Definitions » Functions and Instructions Reference » NVIC Functions » FPU Functions » SysTick Functions
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    Functions that access the ITM debug interface. -More...

    -
    - + Collaboration diagram for ITM Functions:
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    -Macros

    #define ITM_RXBUFFER_EMPTY   ((int32_t)0x5AA55AA5U)
     
    - - - - - - - - - - -

    -Functions

    __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
     ITM Send Character.
     
    __STATIC_INLINE int32_t ITM_ReceiveChar (void)
     ITM Receive Character.
     
    __STATIC_INLINE int32_t ITM_CheckChar (void)
     ITM Check Character.
     
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    -Variables

    uint32_t   _reserved0:16 
     
    uint32_t   GE:4 
     
    uint32_t   _reserved1:7 
     
    uint32_t   Q:1 
     
    uint32_t   V:1 
     
    uint32_t   C:1 
     
    uint32_t   Z:1 
     
    uint32_t   N:1 
     
    struct { 
     
       uint32_t   _reserved0:16 
     
       uint32_t   GE:4 
     
       uint32_t   _reserved1:7 
     
       uint32_t   Q:1 
     
       uint32_t   V:1 
     
       uint32_t   C:1 
     
       uint32_t   Z:1 
     
       uint32_t   N:1 
     
    } b 
     
    uint32_t w
     
    uint32_t   ISR:9 
     
    uint32_t   _reserved0:23 
     
    struct { 
     
       uint32_t   ISR:9 
     
       uint32_t   _reserved0:23 
     
    } b 
     
    uint32_t w
     
    uint32_t   ISR:9 
     
    uint32_t   _reserved0:1 
     
    uint32_t   ICI_IT_1:6 
     
    uint32_t   GE:4 
     
    uint32_t   _reserved1:4 
     
    uint32_t   T:1 
     
    uint32_t   ICI_IT_2:2 
     
    uint32_t   Q:1 
     
    uint32_t   V:1 
     
    uint32_t   C:1 
     
    uint32_t   Z:1 
     
    uint32_t   N:1 
     
    struct { 
     
       uint32_t   ISR:9 
     
       uint32_t   _reserved0:1 
     
       uint32_t   ICI_IT_1:6 
     
       uint32_t   GE:4 
     
       uint32_t   _reserved1:4 
     
       uint32_t   T:1 
     
       uint32_t   ICI_IT_2:2 
     
       uint32_t   Q:1 
     
       uint32_t   V:1 
     
       uint32_t   C:1 
     
       uint32_t   Z:1 
     
       uint32_t   N:1 
     
    } b 
     
    uint32_t w
     
    uint32_t   nPRIV:1 
     
    uint32_t   SPSEL:1 
     
    uint32_t   FPCA:1 
     
    uint32_t   _reserved0:29 
     
    struct { 
     
       uint32_t   nPRIV:1 
     
       uint32_t   SPSEL:1 
     
       uint32_t   FPCA:1 
     
       uint32_t   _reserved0:29 
     
    } b 
     
    uint32_t w
     
    __IOM uint32_t ISER [8U]
     
    uint32_t RESERVED0 [24U]
     
    __IOM uint32_t ICER [8U]
     
    uint32_t RSERVED1 [24U]
     
    __IOM uint32_t ISPR [8U]
     
    uint32_t RESERVED2 [24U]
     
    __IOM uint32_t ICPR [8U]
     
    uint32_t RESERVED3 [24U]
     
    __IOM uint32_t IABR [8U]
     
    uint32_t RESERVED4 [56U]
     
    __IOM uint8_t IP [240U]
     
    uint32_t RESERVED5 [644U]
     
    __OM uint32_t STIR
     
    __IM uint32_t CPUID
     
    __IOM uint32_t ICSR
     
    __IOM uint32_t VTOR
     
    __IOM uint32_t AIRCR
     
    __IOM uint32_t SCR
     
    __IOM uint32_t CCR
     
    __IOM uint8_t SHP [12U]
     
    __IOM uint32_t SHCSR
     
    __IOM uint32_t CFSR
     
    __IOM uint32_t HFSR
     
    __IOM uint32_t DFSR
     
    __IOM uint32_t MMFAR
     
    __IOM uint32_t BFAR
     
    __IOM uint32_t AFSR
     
    __IM uint32_t PFR [2U]
     
    __IM uint32_t DFR
     
    __IM uint32_t ADR
     
    __IM uint32_t MMFR [4U]
     
    __IM uint32_t ISAR [5U]
     
    uint32_t RESERVED0 [5U]
     
    __IOM uint32_t CPACR
     
    uint32_t RESERVED0 [1U]
     
    __IM uint32_t ICTR
     
    __IOM uint32_t ACTLR
     
    __IOM uint32_t CTRL
     
    __IOM uint32_t LOAD
     
    __IOM uint32_t VAL
     
    __IM uint32_t CALIB
     
    __OM uint8_t   u8 
     
    __OM uint16_t   u16 
     
    __OM uint32_t   u32 
     
    union { 
     
       __OM uint8_t   u8 
     
       __OM uint16_t   u16 
     
       __OM uint32_t   u32 
     
    } PORT [32U] 
     
    uint32_t RESERVED0 [864U]
     
    __IOM uint32_t TER
     
    uint32_t RESERVED1 [15U]
     
    __IOM uint32_t TPR
     
    uint32_t RESERVED2 [15U]
     
    __IOM uint32_t TCR
     
    uint32_t RESERVED3 [29U]
     
    __OM uint32_t IWR
     
    __IM uint32_t IRR
     
    __IOM uint32_t IMCR
     
    uint32_t RESERVED4 [43U]
     
    __OM uint32_t LAR
     
    __IM uint32_t LSR
     
    uint32_t RESERVED5 [6U]
     
    __IM uint32_t PID4
     
    __IM uint32_t PID5
     
    __IM uint32_t PID6
     
    __IM uint32_t PID7
     
    __IM uint32_t PID0
     
    __IM uint32_t PID1
     
    __IM uint32_t PID2
     
    __IM uint32_t PID3
     
    __IM uint32_t CID0
     
    __IM uint32_t CID1
     
    __IM uint32_t CID2
     
    __IM uint32_t CID3
     
    __IOM uint32_t CTRL
     
    __IOM uint32_t CYCCNT
     
    __IOM uint32_t CPICNT
     
    __IOM uint32_t EXCCNT
     
    __IOM uint32_t SLEEPCNT
     
    __IOM uint32_t LSUCNT
     
    __IOM uint32_t FOLDCNT
     
    __IM uint32_t PCSR
     
    __IOM uint32_t COMP0
     
    __IOM uint32_t MASK0
     
    __IOM uint32_t FUNCTION0
     
    uint32_t RESERVED0 [1U]
     
    __IOM uint32_t COMP1
     
    __IOM uint32_t MASK1
     
    __IOM uint32_t FUNCTION1
     
    uint32_t RESERVED1 [1U]
     
    __IOM uint32_t COMP2
     
    __IOM uint32_t MASK2
     
    __IOM uint32_t FUNCTION2
     
    uint32_t RESERVED2 [1U]
     
    __IOM uint32_t COMP3
     
    __IOM uint32_t MASK3
     
    __IOM uint32_t FUNCTION3
     
    __IM uint32_t SSPSR
     
    __IOM uint32_t CSPSR
     
    uint32_t RESERVED0 [2U]
     
    __IOM uint32_t ACPR
     
    uint32_t RESERVED1 [55U]
     
    __IOM uint32_t SPPR
     
    uint32_t RESERVED2 [131U]
     
    __IM uint32_t FFSR
     
    __IOM uint32_t FFCR
     
    __IM uint32_t FSCR
     
    uint32_t RESERVED3 [759U]
     
    __IM uint32_t TRIGGER
     
    __IM uint32_t FIFO0
     
    __IM uint32_t ITATBCTR2
     
    uint32_t RESERVED4 [1U]
     
    __IM uint32_t ITATBCTR0
     
    __IM uint32_t FIFO1
     
    __IOM uint32_t ITCTRL
     
    uint32_t RESERVED5 [39U]
     
    __IOM uint32_t CLAIMSET
     
    __IOM uint32_t CLAIMCLR
     
    uint32_t RESERVED7 [8U]
     
    __IM uint32_t DEVID
     
    __IM uint32_t DEVTYPE
     
    uint32_t RESERVED0 [1U]
     
    __IOM uint32_t FPCCR
     
    __IOM uint32_t FPCAR
     
    __IOM uint32_t FPDSCR
     
    __IM uint32_t MVFR0
     
    __IM uint32_t MVFR1
     
    __IOM uint32_t DHCSR
     
    __OM uint32_t DCRSR
     
    __IOM uint32_t DCRDR
     
    __IOM uint32_t DEMCR
     
    uint8_t CORTEX_PERIPH_BASE [0xE0100000 - 0xE0000000]
     
    volatile int32_t ITM_RxBuffer
     
    -

    Detailed Description

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    Functions that access the ITM debug interface.

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    Macro Definition Documentation

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    ◆ ITM_RXBUFFER_EMPTY

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    #define ITM_RXBUFFER_EMPTY   ((int32_t)0x5AA55AA5U)
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    Value identifying ITM_RxBuffer is ready for next character.

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    Function Documentation

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    ◆ ITM_SendChar()

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    __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
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    ITM Send Character.

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    Transmits a character via the ITM channel 0, and

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    • Just returns when no debugger is connected that has booked the output.
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    • Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
      Parameters
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      [in]chCharacter to transmit.
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      Character to transmit.
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    ◆ ITM_ReceiveChar()

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    __STATIC_INLINE int32_t ITM_ReceiveChar (void )
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    ITM Receive Character.

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    Inputs a character via the external variable ITM_RxBuffer.

    Returns
    Received character.
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    --1 No character pending.
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    ◆ ITM_CheckChar()

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    __STATIC_INLINE int32_t ITM_CheckChar (void )
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    ITM Check Character.

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    Checks whether a character is pending for reading in the variable ITM_RxBuffer.

    Returns
    0 No character available.
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    -1 Character available.
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    Variable Documentation

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    ◆ _reserved0 [1/8]

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    bit: 0..15 Reserved

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    bit: 0..15 Reserved

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    uint32_t GE
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    bit: 16..19 Greater than or Equal flags

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    uint32_t GE
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    bit: 16..19 Greater than or Equal flags

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    uint32_t _reserved1
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    bit: 20..26 Reserved

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    uint32_t _reserved1
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    bit: 20..26 Reserved

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    uint32_t Q
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    bit: 27 Saturation condition flag

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    uint32_t Q
    -
    -

    bit: 27 Saturation condition flag

    - -
    -
    - -

    ◆ V [1/4]

    - -
    -
    - - - - -
    uint32_t V
    -
    -

    bit: 28 Overflow condition code flag

    - -
    -
    - -

    ◆ V [2/4]

    - -
    -
    - - - - -
    uint32_t V
    -
    -

    bit: 28 Overflow condition code flag

    - -
    -
    - -

    ◆ C [1/4]

    - -
    -
    - - - - -
    uint32_t C
    -
    -

    bit: 29 Carry condition code flag

    - -
    -
    - -

    ◆ C [2/4]

    - -
    -
    - - - - -
    uint32_t C
    -
    -

    bit: 29 Carry condition code flag

    - -
    -
    - -

    ◆ Z [1/4]

    - -
    -
    - - - - -
    uint32_t Z
    -
    -

    bit: 30 Zero condition code flag

    - -
    -
    - -

    ◆ Z [2/4]

    - -
    -
    - - - - -
    uint32_t Z
    -
    -

    bit: 30 Zero condition code flag

    - -
    -
    - -

    ◆ N [1/4]

    - -
    -
    - - - - -
    uint32_t N
    -
    -

    bit: 31 Negative condition code flag

    - -
    -
    - -

    ◆ N [2/4]

    - -
    -
    - - - - -
    uint32_t N
    -
    -

    bit: 31 Negative condition code flag

    - -
    -
    - -

    ◆ [struct] [1/4]

    - -
    -
    - - - - -
    struct { ... } b
    -
    -

    Structure used for bit access

    - -
    -
    - -

    ◆ w [1/4]

    - -
    -
    - - - - -
    uint32_t w
    -
    -

    Type used for word access

    - -
    -
    - -

    ◆ ISR [1/4]

    - -
    -
    - - - - -
    uint32_t ISR
    -
    -

    bit: 0.. 8 Exception number

    - -
    -
    - -

    ◆ ISR [2/4]

    - -
    -
    - - - - -
    uint32_t ISR
    -
    -

    bit: 0.. 8 Exception number

    - -
    -
    - -

    ◆ _reserved0 [3/8]

    - -
    -
    - - - - -
    uint32_t _reserved0
    -
    -

    bit: 9..31 Reserved

    - -
    -
    - -

    ◆ _reserved0 [4/8]

    - -
    -
    - - - - -
    uint32_t _reserved0
    -
    -

    bit: 9..31 Reserved

    - -
    -
    - -

    ◆ [struct] [2/4]

    - -
    -
    - - - - -
    struct { ... } b
    -
    -

    Structure used for bit access

    - -
    -
    - -

    ◆ w [2/4]

    - -
    -
    - - - - -
    uint32_t w
    -
    -

    Type used for word access

    - -
    -
    - -

    ◆ ISR [3/4]

    - -
    -
    - - - - -
    uint32_t ISR
    -
    -

    bit: 0.. 8 Exception number

    - -
    -
    - -

    ◆ ISR [4/4]

    - -
    -
    - - - - -
    uint32_t ISR
    -
    -

    bit: 0.. 8 Exception number

    - -
    -
    - -

    ◆ _reserved0 [5/8]

    - -
    -
    - - - - -
    uint32_t _reserved0
    -
    -

    bit: 9 Reserved

    - -
    -
    - -

    ◆ _reserved0 [6/8]

    - -
    -
    - - - - -
    uint32_t _reserved0
    -
    -

    bit: 9 Reserved

    - -
    -
    - -

    ◆ ICI_IT_1 [1/2]

    - -
    -
    - - - - -
    uint32_t ICI_IT_1
    -
    -

    bit: 10..15 ICI/IT part 1

    - -
    -
    - -

    ◆ ICI_IT_1 [2/2]

    - -
    -
    - - - - -
    uint32_t ICI_IT_1
    -
    -

    bit: 10..15 ICI/IT part 1

    - -
    -
    - -

    ◆ GE [3/4]

    - -
    -
    - - - - -
    uint32_t GE
    -
    -

    bit: 16..19 Greater than or Equal flags

    - -
    -
    - -

    ◆ GE [4/4]

    - -
    -
    - - - - -
    uint32_t GE
    -
    -

    bit: 16..19 Greater than or Equal flags

    - -
    -
    - -

    ◆ _reserved1 [3/4]

    - -
    -
    - - - - -
    uint32_t _reserved1
    -
    -

    bit: 20..23 Reserved

    - -
    -
    - -

    ◆ _reserved1 [4/4]

    - -
    -
    - - - - -
    uint32_t _reserved1
    -
    -

    bit: 20..23 Reserved

    - -
    -
    - -

    ◆ T [1/2]

    - -
    -
    - - - - -
    uint32_t T
    -
    -

    bit: 24 Thumb bit

    - -
    -
    - -

    ◆ T [2/2]

    - -
    -
    - - - - -
    uint32_t T
    -
    -

    bit: 24 Thumb bit

    - -
    -
    - -

    ◆ ICI_IT_2 [1/2]

    - -
    -
    - - - - -
    uint32_t ICI_IT_2
    -
    -

    bit: 25..26 ICI/IT part 2

    - -
    -
    - -

    ◆ ICI_IT_2 [2/2]

    - -
    -
    - - - - -
    uint32_t ICI_IT_2
    -
    -

    bit: 25..26 ICI/IT part 2

    - -
    -
    - -

    ◆ Q [3/4]

    - -
    -
    - - - - -
    uint32_t Q
    -
    -

    bit: 27 Saturation condition flag

    - -
    -
    - -

    ◆ Q [4/4]

    - -
    -
    - - - - -
    uint32_t Q
    -
    -

    bit: 27 Saturation condition flag

    - -
    -
    - -

    ◆ V [3/4]

    - -
    -
    - - - - -
    uint32_t V
    -
    -

    bit: 28 Overflow condition code flag

    - -
    -
    - -

    ◆ V [4/4]

    - -
    -
    - - - - -
    uint32_t V
    -
    -

    bit: 28 Overflow condition code flag

    - -
    -
    - -

    ◆ C [3/4]

    - -
    -
    - - - - -
    uint32_t C
    -
    -

    bit: 29 Carry condition code flag

    - -
    -
    - -

    ◆ C [4/4]

    - -
    -
    - - - - -
    uint32_t C
    -
    -

    bit: 29 Carry condition code flag

    - -
    -
    - -

    ◆ Z [3/4]

    - -
    -
    - - - - -
    uint32_t Z
    -
    -

    bit: 30 Zero condition code flag

    - -
    -
    - -

    ◆ Z [4/4]

    - -
    -
    - - - - -
    uint32_t Z
    -
    -

    bit: 30 Zero condition code flag

    - -
    -
    - -

    ◆ N [3/4]

    - -
    -
    - - - - -
    uint32_t N
    -
    -

    bit: 31 Negative condition code flag

    - -
    -
    - -

    ◆ N [4/4]

    - -
    -
    - - - - -
    uint32_t N
    -
    -

    bit: 31 Negative condition code flag

    - -
    -
    - -

    ◆ [struct] [3/4]

    - -
    -
    - - - - -
    struct { ... } b
    -
    -

    Structure used for bit access

    - -
    -
    - -

    ◆ w [3/4]

    - -
    -
    - - - - -
    uint32_t w
    -
    -

    Type used for word access

    - -
    -
    - -

    ◆ nPRIV [1/2]

    - -
    -
    - - - - -
    uint32_t nPRIV
    -
    -

    bit: 0 Execution privilege in Thread mode

    - -
    -
    - -

    ◆ nPRIV [2/2]

    - -
    -
    - - - - -
    uint32_t nPRIV
    -
    -

    bit: 0 Execution privilege in Thread mode

    - -
    -
    - -

    ◆ SPSEL [1/2]

    - -
    -
    - - - - -
    uint32_t SPSEL
    -
    -

    bit: 1 Stack to be used

    - -
    -
    - -

    ◆ SPSEL [2/2]

    - -
    -
    - - - - -
    uint32_t SPSEL
    -
    -

    bit: 1 Stack to be used

    - -
    -
    - -

    ◆ FPCA [1/2]

    - -
    -
    - - - - -
    uint32_t FPCA
    -
    -

    bit: 2 FP extension active flag

    - -
    -
    - -

    ◆ FPCA [2/2]

    - -
    -
    - - - - -
    uint32_t FPCA
    -
    -

    bit: 2 FP extension active flag

    - -
    -
    - -

    ◆ _reserved0 [7/8]

    - -
    -
    - - - - -
    uint32_t _reserved0
    -
    -

    bit: 3..31 Reserved

    - -
    -
    - -

    ◆ _reserved0 [8/8]

    - -
    -
    - - - - -
    uint32_t _reserved0
    -
    -

    bit: 3..31 Reserved

    - -
    -
    - -

    ◆ [struct] [4/4]

    - -
    -
    - - - - -
    struct { ... } b
    -
    -

    Structure used for bit access

    - -
    -
    - -

    ◆ w [4/4]

    - -
    -
    - - - - -
    uint32_t w
    -
    -

    Type used for word access

    - -
    -
    - -

    ◆ ISER

    - -
    -
    - - - - -
    __IOM uint32_t ISER[8U]
    -
    -

    Offset: 0x000 (R/W) Interrupt Set Enable Register

    - -
    -
    - -

    ◆ RESERVED0 [1/7]

    - -
    -
    - - - - -
    uint32_t RESERVED0[24U]
    -
    - -
    -
    - -

    ◆ ICER

    - -
    -
    - - - - -
    __IOM uint32_t ICER[8U]
    -
    -

    Offset: 0x080 (R/W) Interrupt Clear Enable Register

    - -
    -
    - -

    ◆ RSERVED1

    - -
    -
    - - - - -
    uint32_t RSERVED1[24U]
    -
    - -
    -
    - -

    ◆ ISPR

    - -
    -
    - - - - -
    __IOM uint32_t ISPR[8U]
    -
    -

    Offset: 0x100 (R/W) Interrupt Set Pending Register

    - -
    -
    - -

    ◆ RESERVED2 [1/4]

    - -
    -
    - - - - -
    uint32_t RESERVED2[24U]
    -
    - -
    -
    - -

    ◆ ICPR

    - -
    -
    - - - - -
    __IOM uint32_t ICPR[8U]
    -
    -

    Offset: 0x180 (R/W) Interrupt Clear Pending Register

    - -
    -
    - -

    ◆ RESERVED3 [1/3]

    - -
    -
    - - - - -
    uint32_t RESERVED3[24U]
    -
    - -
    -
    - -

    ◆ IABR

    - -
    -
    - - - - -
    __IOM uint32_t IABR[8U]
    -
    -

    Offset: 0x200 (R/W) Interrupt Active bit Register

    - -
    -
    - -

    ◆ RESERVED4 [1/3]

    - -
    -
    - - - - -
    uint32_t RESERVED4[56U]
    -
    - -
    -
    - -

    ◆ IP

    - -
    -
    - - - - -
    __IOM uint8_t IP[240U]
    -
    -

    Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide)

    - -
    -
    - -

    ◆ RESERVED5 [1/3]

    - -
    -
    - - - - -
    uint32_t RESERVED5[644U]
    -
    - -
    -
    - -

    ◆ STIR

    - -
    -
    - - - - -
    __OM uint32_t STIR
    -
    -

    Offset: 0xE00 ( /W) Software Trigger Interrupt Register

    - -
    -
    - -

    ◆ CPUID

    - -
    -
    - - - - -
    __IM uint32_t CPUID
    -
    -

    Offset: 0x000 (R/ ) CPUID Base Register

    - -
    -
    - -

    ◆ ICSR

    - -
    -
    - - - - -
    __IOM uint32_t ICSR
    -
    -

    Offset: 0x004 (R/W) Interrupt Control and State Register

    - -
    -
    - -

    ◆ VTOR

    - -
    -
    - - - - -
    __IOM uint32_t VTOR
    -
    -

    Offset: 0x008 (R/W) Vector Table Offset Register

    - -
    -
    - -

    ◆ AIRCR

    - -
    -
    - - - - -
    __IOM uint32_t AIRCR
    -
    -

    Offset: 0x00C (R/W) Application Interrupt and Reset Control Register

    - -
    -
    - -

    ◆ SCR

    - -
    -
    - - - - -
    __IOM uint32_t SCR
    -
    -

    Offset: 0x010 (R/W) System Control Register

    - -
    -
    - -

    ◆ CCR

    - -
    -
    - - - - -
    __IOM uint32_t CCR
    -
    -

    Offset: 0x014 (R/W) Configuration Control Register

    - -
    -
    - -

    ◆ SHP

    - -
    -
    - - - - -
    __IOM uint8_t SHP[12U]
    -
    -

    Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15)

    - -
    -
    - -

    ◆ SHCSR

    - -
    -
    - - - - -
    __IOM uint32_t SHCSR
    -
    -

    Offset: 0x024 (R/W) System Handler Control and State Register

    - -
    -
    - -

    ◆ CFSR

    - -
    -
    - - - - -
    __IOM uint32_t CFSR
    -
    -

    Offset: 0x028 (R/W) Configurable Fault Status Register

    - -
    -
    - -

    ◆ HFSR

    - -
    -
    - - - - -
    __IOM uint32_t HFSR
    -
    -

    Offset: 0x02C (R/W) HardFault Status Register

    - -
    -
    - -

    ◆ DFSR

    - -
    -
    - - - - -
    __IOM uint32_t DFSR
    -
    -

    Offset: 0x030 (R/W) Debug Fault Status Register

    - -
    -
    - -

    ◆ MMFAR

    - -
    -
    - - - - -
    __IOM uint32_t MMFAR
    -
    -

    Offset: 0x034 (R/W) MemManage Fault Address Register

    - -
    -
    - -

    ◆ BFAR

    - -
    -
    - - - - -
    __IOM uint32_t BFAR
    -
    -

    Offset: 0x038 (R/W) BusFault Address Register

    - -
    -
    - -

    ◆ AFSR

    - -
    -
    - - - - -
    __IOM uint32_t AFSR
    -
    -

    Offset: 0x03C (R/W) Auxiliary Fault Status Register

    - -
    -
    - -

    ◆ PFR

    - -
    -
    - - - - -
    __IM uint32_t PFR[2U]
    -
    -

    Offset: 0x040 (R/ ) Processor Feature Register

    - -
    -
    - -

    ◆ DFR

    - -
    -
    - - - - -
    __IM uint32_t DFR
    -
    -

    Offset: 0x048 (R/ ) Debug Feature Register

    - -
    -
    - -

    ◆ ADR

    - -
    -
    - - - - -
    __IM uint32_t ADR
    -
    -

    Offset: 0x04C (R/ ) Auxiliary Feature Register

    - -
    -
    - -

    ◆ MMFR

    - -
    -
    - - - - -
    __IM uint32_t MMFR[4U]
    -
    -

    Offset: 0x050 (R/ ) Memory Model Feature Register

    - -
    -
    - -

    ◆ ISAR

    - -
    -
    - - - - -
    __IM uint32_t ISAR[5U]
    -
    -

    Offset: 0x060 (R/ ) Instruction Set Attributes Register

    - -
    -
    - -

    ◆ RESERVED0 [2/7]

    - -
    -
    - - - - -
    uint32_t RESERVED0[5U]
    -
    - -
    -
    - -

    ◆ CPACR

    - -
    -
    - - - - -
    __IOM uint32_t CPACR
    -
    -

    Offset: 0x088 (R/W) Coprocessor Access Control Register

    - -
    -
    - -

    ◆ RESERVED0 [3/7]

    - -
    -
    - - - - -
    uint32_t RESERVED0[1U]
    -
    - -
    -
    - -

    ◆ ICTR

    - -
    -
    - - - - -
    __IM uint32_t ICTR
    -
    -

    Offset: 0x004 (R/ ) Interrupt Controller Type Register

    - -
    -
    - -

    ◆ ACTLR

    - -
    -
    - - - - -
    __IOM uint32_t ACTLR
    -
    -

    Offset: 0x008 (R/W) Auxiliary Control Register

    - -
    -
    - -

    ◆ CTRL [1/2]

    - -
    -
    - - - - -
    __IOM uint32_t CTRL
    -
    -

    Offset: 0x000 (R/W) SysTick Control and Status Register

    - -
    -
    - -

    ◆ LOAD

    - -
    -
    - - - - -
    __IOM uint32_t LOAD
    -
    -

    Offset: 0x004 (R/W) SysTick Reload Value Register

    - -
    -
    - -

    ◆ VAL

    - -
    -
    - - - - -
    __IOM uint32_t VAL
    -
    -

    Offset: 0x008 (R/W) SysTick Current Value Register

    - -
    -
    - -

    ◆ CALIB

    - -
    -
    - - - - -
    __IM uint32_t CALIB
    -
    -

    Offset: 0x00C (R/ ) SysTick Calibration Register

    - -
    -
    - -

    ◆ u8 [1/2]

    - -
    -
    - - - - -
    __OM uint8_t u8
    -
    -

    Offset: 0x000 ( /W) ITM Stimulus Port 8-bit

    - -
    -
    - -

    ◆ u8 [2/2]

    - -
    -
    - - - - -
    __OM uint8_t u8
    -
    -

    Offset: 0x000 ( /W) ITM Stimulus Port 8-bit

    - -
    -
    - -

    ◆ u16 [1/2]

    - -
    -
    - - - - -
    __OM uint16_t u16
    -
    -

    Offset: 0x000 ( /W) ITM Stimulus Port 16-bit

    - -
    -
    - -

    ◆ u16 [2/2]

    - -
    -
    - - - - -
    __OM uint16_t u16
    -
    -

    Offset: 0x000 ( /W) ITM Stimulus Port 16-bit

    - -
    -
    - -

    ◆ u32 [1/2]

    - -
    -
    - - - - -
    __OM uint32_t u32
    -
    -

    Offset: 0x000 ( /W) ITM Stimulus Port 32-bit

    - -
    -
    - -

    ◆ u32 [2/2]

    - -
    -
    - - - - -
    __OM uint32_t u32
    -
    -

    Offset: 0x000 ( /W) ITM Stimulus Port 32-bit

    - -
    -
    - -

    ◆ [union]

    - -
    -
    - - - - -
    __OM union { ... } PORT[32U]
    -
    -

    Offset: 0x000 ( /W) ITM Stimulus Port Registers

    - -
    -
    - -

    ◆ RESERVED0 [4/7]

    - -
    -
    - - - - -
    uint32_t RESERVED0[864U]
    -
    - -
    -
    - -

    ◆ TER

    - -
    -
    - - - - -
    __IOM uint32_t TER
    -
    -

    Offset: 0xE00 (R/W) ITM Trace Enable Register

    - -
    -
    - -

    ◆ RESERVED1 [1/3]

    - -
    -
    - - - - -
    uint32_t RESERVED1[15U]
    -
    - -
    -
    - -

    ◆ TPR

    - -
    -
    - - - - -
    __IOM uint32_t TPR
    -
    -

    Offset: 0xE40 (R/W) ITM Trace Privilege Register

    - -
    -
    - -

    ◆ RESERVED2 [2/4]

    - -
    -
    - - - - -
    uint32_t RESERVED2[15U]
    -
    - -
    -
    - -

    ◆ TCR

    - -
    -
    - - - - -
    __IOM uint32_t TCR
    -
    -

    Offset: 0xE80 (R/W) ITM Trace Control Register

    - -
    -
    - -

    ◆ RESERVED3 [2/3]

    - -
    -
    - - - - -
    uint32_t RESERVED3[29U]
    -
    - -
    -
    - -

    ◆ IWR

    - -
    -
    - - - - -
    __OM uint32_t IWR
    -
    -

    Offset: 0xEF8 ( /W) ITM Integration Write Register

    - -
    -
    - -

    ◆ IRR

    - -
    -
    - - - - -
    __IM uint32_t IRR
    -
    -

    Offset: 0xEFC (R/ ) ITM Integration Read Register

    - -
    -
    - -

    ◆ IMCR

    - -
    -
    - - - - -
    __IOM uint32_t IMCR
    -
    -

    Offset: 0xF00 (R/W) ITM Integration Mode Control Register

    - -
    -
    - -

    ◆ RESERVED4 [2/3]

    - -
    -
    - - - - -
    uint32_t RESERVED4[43U]
    -
    - -
    -
    - -

    ◆ LAR

    - -
    -
    - - - - -
    __OM uint32_t LAR
    -
    -

    Offset: 0xFB0 ( /W) ITM Lock Access Register

    - -
    -
    - -

    ◆ LSR

    - -
    -
    - - - - -
    __IM uint32_t LSR
    -
    -

    Offset: 0xFB4 (R/ ) ITM Lock Status Register

    - -
    -
    - -

    ◆ RESERVED5 [2/3]

    - -
    -
    - - - - -
    uint32_t RESERVED5[6U]
    -
    - -
    -
    - -

    ◆ PID4

    - -
    -
    - - - - -
    __IM uint32_t PID4
    -
    -

    Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4

    - -
    -
    - -

    ◆ PID5

    - -
    -
    - - - - -
    __IM uint32_t PID5
    -
    -

    Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5

    - -
    -
    - -

    ◆ PID6

    - -
    -
    - - - - -
    __IM uint32_t PID6
    -
    -

    Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6

    - -
    -
    - -

    ◆ PID7

    - -
    -
    - - - - -
    __IM uint32_t PID7
    -
    -

    Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7

    - -
    -
    - -

    ◆ PID0

    - -
    -
    - - - - -
    __IM uint32_t PID0
    -
    -

    Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0

    - -
    -
    - -

    ◆ PID1

    - -
    -
    - - - - -
    __IM uint32_t PID1
    -
    -

    Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1

    - -
    -
    - -

    ◆ PID2

    - -
    -
    - - - - -
    __IM uint32_t PID2
    -
    -

    Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2

    - -
    -
    - -

    ◆ PID3

    - -
    -
    - - - - -
    __IM uint32_t PID3
    -
    -

    Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3

    - -
    -
    - -

    ◆ CID0

    - -
    -
    - - - - -
    __IM uint32_t CID0
    -
    -

    Offset: 0xFF0 (R/ ) ITM Component Identification Register #0

    - -
    -
    - -

    ◆ CID1

    - -
    -
    - - - - -
    __IM uint32_t CID1
    -
    -

    Offset: 0xFF4 (R/ ) ITM Component Identification Register #1

    - -
    -
    - -

    ◆ CID2

    - -
    -
    - - - - -
    __IM uint32_t CID2
    -
    -

    Offset: 0xFF8 (R/ ) ITM Component Identification Register #2

    - -
    -
    - -

    ◆ CID3

    - -
    -
    - - - - -
    __IM uint32_t CID3
    -
    -

    Offset: 0xFFC (R/ ) ITM Component Identification Register #3

    - -
    -
    - -

    ◆ CTRL [2/2]

    - -
    -
    - - - - -
    __IOM uint32_t CTRL
    -
    -

    Offset: 0x000 (R/W) Control Register

    - -
    -
    - -

    ◆ CYCCNT

    - -
    -
    - - - - -
    __IOM uint32_t CYCCNT
    -
    -

    Offset: 0x004 (R/W) Cycle Count Register

    - -
    -
    - -

    ◆ CPICNT

    - -
    -
    - - - - -
    __IOM uint32_t CPICNT
    -
    -

    Offset: 0x008 (R/W) CPI Count Register

    - -
    -
    - -

    ◆ EXCCNT

    - -
    -
    - - - - -
    __IOM uint32_t EXCCNT
    -
    -

    Offset: 0x00C (R/W) Exception Overhead Count Register

    - -
    -
    - -

    ◆ SLEEPCNT

    - -
    -
    - - - - -
    __IOM uint32_t SLEEPCNT
    -
    -

    Offset: 0x010 (R/W) Sleep Count Register

    - -
    -
    - -

    ◆ LSUCNT

    - -
    -
    - - - - -
    __IOM uint32_t LSUCNT
    -
    -

    Offset: 0x014 (R/W) LSU Count Register

    - -
    -
    - -

    ◆ FOLDCNT

    - -
    -
    - - - - -
    __IOM uint32_t FOLDCNT
    -
    -

    Offset: 0x018 (R/W) Folded-instruction Count Register

    - -
    -
    - -

    ◆ PCSR

    - -
    -
    - - - - -
    __IM uint32_t PCSR
    -
    -

    Offset: 0x01C (R/ ) Program Counter Sample Register

    - -
    -
    - -

    ◆ COMP0

    - -
    -
    - - - - -
    __IOM uint32_t COMP0
    -
    -

    Offset: 0x020 (R/W) Comparator Register 0

    - -
    -
    - -

    ◆ MASK0

    - -
    -
    - - - - -
    __IOM uint32_t MASK0
    -
    -

    Offset: 0x024 (R/W) Mask Register 0

    - -
    -
    - -

    ◆ FUNCTION0

    - -
    -
    - - - - -
    __IOM uint32_t FUNCTION0
    -
    -

    Offset: 0x028 (R/W) Function Register 0

    - -
    -
    - -

    ◆ RESERVED0 [5/7]

    - -
    -
    - - - - -
    uint32_t RESERVED0[1U]
    -
    - -
    -
    - -

    ◆ COMP1

    - -
    -
    - - - - -
    __IOM uint32_t COMP1
    -
    -

    Offset: 0x030 (R/W) Comparator Register 1

    - -
    -
    - -

    ◆ MASK1

    - -
    -
    - - - - -
    __IOM uint32_t MASK1
    -
    -

    Offset: 0x034 (R/W) Mask Register 1

    - -
    -
    - -

    ◆ FUNCTION1

    - -
    -
    - - - - -
    __IOM uint32_t FUNCTION1
    -
    -

    Offset: 0x038 (R/W) Function Register 1

    - -
    -
    - -

    ◆ RESERVED1 [2/3]

    - -
    -
    - - - - -
    uint32_t RESERVED1[1U]
    -
    - -
    -
    - -

    ◆ COMP2

    - -
    -
    - - - - -
    __IOM uint32_t COMP2
    -
    -

    Offset: 0x040 (R/W) Comparator Register 2

    - -
    -
    - -

    ◆ MASK2

    - -
    -
    - - - - -
    __IOM uint32_t MASK2
    -
    -

    Offset: 0x044 (R/W) Mask Register 2

    - -
    -
    - -

    ◆ FUNCTION2

    - -
    -
    - - - - -
    __IOM uint32_t FUNCTION2
    -
    -

    Offset: 0x048 (R/W) Function Register 2

    - -
    -
    - -

    ◆ RESERVED2 [3/4]

    - -
    -
    - - - - -
    uint32_t RESERVED2[1U]
    -
    - -
    -
    - -

    ◆ COMP3

    - -
    -
    - - - - -
    __IOM uint32_t COMP3
    -
    -

    Offset: 0x050 (R/W) Comparator Register 3

    - -
    -
    - -

    ◆ MASK3

    - -
    -
    - - - - -
    __IOM uint32_t MASK3
    -
    -

    Offset: 0x054 (R/W) Mask Register 3

    - -
    -
    - -

    ◆ FUNCTION3

    - -
    -
    - - - - -
    __IOM uint32_t FUNCTION3
    -
    -

    Offset: 0x058 (R/W) Function Register 3

    - -
    -
    - -

    ◆ SSPSR

    - -
    -
    - - - - -
    __IM uint32_t SSPSR
    -
    -

    Offset: 0x000 (R/ ) Supported Parallel Port Size Register

    - -
    -
    - -

    ◆ CSPSR

    - -
    -
    - - - - -
    __IOM uint32_t CSPSR
    -
    -

    Offset: 0x004 (R/W) Current Parallel Port Size Register

    - -
    -
    - -

    ◆ RESERVED0 [6/7]

    - -
    -
    - - - - -
    uint32_t RESERVED0[2U]
    -
    - -
    -
    - -

    ◆ ACPR

    - -
    -
    - - - - -
    __IOM uint32_t ACPR
    -
    -

    Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register

    - -
    -
    - -

    ◆ RESERVED1 [3/3]

    - -
    -
    - - - - -
    uint32_t RESERVED1[55U]
    -
    - -
    -
    - -

    ◆ SPPR

    - -
    -
    - - - - -
    __IOM uint32_t SPPR
    -
    -

    Offset: 0x0F0 (R/W) Selected Pin Protocol Register

    - -
    -
    - -

    ◆ RESERVED2 [4/4]

    - -
    -
    - - - - -
    uint32_t RESERVED2[131U]
    -
    - -
    -
    - -

    ◆ FFSR

    - -
    -
    - - - - -
    __IM uint32_t FFSR
    -
    -

    Offset: 0x300 (R/ ) Formatter and Flush Status Register

    - -
    -
    - -

    ◆ FFCR

    - -
    -
    - - - - -
    __IOM uint32_t FFCR
    -
    -

    Offset: 0x304 (R/W) Formatter and Flush Control Register

    - -
    -
    - -

    ◆ FSCR

    - -
    -
    - - - - -
    __IM uint32_t FSCR
    -
    -

    Offset: 0x308 (R/ ) Formatter Synchronization Counter Register

    - -
    -
    - -

    ◆ RESERVED3 [3/3]

    - -
    -
    - - - - -
    uint32_t RESERVED3[759U]
    -
    - -
    -
    - -

    ◆ TRIGGER

    - -
    -
    - - - - -
    __IM uint32_t TRIGGER
    -
    -

    Offset: 0xEE8 (R/ ) TRIGGER Register

    - -
    -
    - -

    ◆ FIFO0

    - -
    -
    - - - - -
    __IM uint32_t FIFO0
    -
    -

    Offset: 0xEEC (R/ ) Integration ETM Data

    - -
    -
    - -

    ◆ ITATBCTR2

    - -
    -
    - - - - -
    __IM uint32_t ITATBCTR2
    -
    -

    Offset: 0xEF0 (R/ ) ITATBCTR2

    - -
    -
    - -

    ◆ RESERVED4 [3/3]

    - -
    -
    - - - - -
    uint32_t RESERVED4[1U]
    -
    - -
    -
    - -

    ◆ ITATBCTR0

    - -
    -
    - - - - -
    __IM uint32_t ITATBCTR0
    -
    -

    Offset: 0xEF8 (R/ ) ITATBCTR0

    - -
    -
    - -

    ◆ FIFO1

    - -
    -
    - - - - -
    __IM uint32_t FIFO1
    -
    -

    Offset: 0xEFC (R/ ) Integration ITM Data

    - -
    -
    - -

    ◆ ITCTRL

    - -
    -
    - - - - -
    __IOM uint32_t ITCTRL
    -
    -

    Offset: 0xF00 (R/W) Integration Mode Control

    - -
    -
    - -

    ◆ RESERVED5 [3/3]

    - -
    -
    - - - - -
    uint32_t RESERVED5[39U]
    -
    - -
    -
    - -

    ◆ CLAIMSET

    - -
    -
    - - - - -
    __IOM uint32_t CLAIMSET
    -
    -

    Offset: 0xFA0 (R/W) Claim tag set

    - -
    -
    - -

    ◆ CLAIMCLR

    - -
    -
    - - - - -
    __IOM uint32_t CLAIMCLR
    -
    -

    Offset: 0xFA4 (R/W) Claim tag clear

    - -
    -
    - -

    ◆ RESERVED7

    - -
    -
    - - - - -
    uint32_t RESERVED7[8U]
    -
    - -
    -
    - -

    ◆ DEVID

    - -
    -
    - - - - -
    __IM uint32_t DEVID
    -
    -

    Offset: 0xFC8 (R/ ) TPIU_DEVID

    - -
    -
    - -

    ◆ DEVTYPE

    - -
    -
    - - - - -
    __IM uint32_t DEVTYPE
    -
    -

    Offset: 0xFCC (R/ ) TPIU_DEVTYPE

    - -
    -
    - -

    ◆ RESERVED0 [7/7]

    - -
    -
    - - - - -
    uint32_t RESERVED0[1U]
    -
    - -
    -
    - -

    ◆ FPCCR

    - -
    -
    - - - - -
    __IOM uint32_t FPCCR
    -
    -

    Offset: 0x004 (R/W) Floating-Point Context Control Register

    - -
    -
    - -

    ◆ FPCAR

    - -
    -
    - - - - -
    __IOM uint32_t FPCAR
    -
    -

    Offset: 0x008 (R/W) Floating-Point Context Address Register

    - -
    -
    - -

    ◆ FPDSCR

    - -
    -
    - - - - -
    __IOM uint32_t FPDSCR
    -
    -

    Offset: 0x00C (R/W) Floating-Point Default Status Control Register

    - -
    -
    - -

    ◆ MVFR0

    - -
    -
    - - - - -
    __IM uint32_t MVFR0
    -
    -

    Offset: 0x010 (R/ ) Media and FP Feature Register 0

    - -
    -
    - -

    ◆ MVFR1

    - -
    -
    - - - - -
    __IM uint32_t MVFR1
    -
    -

    Offset: 0x014 (R/ ) Media and FP Feature Register 1

    - -
    -
    - -

    ◆ DHCSR

    - -
    -
    - - - - -
    __IOM uint32_t DHCSR
    -
    -

    Offset: 0x000 (R/W) Debug Halting Control and Status Register

    - -
    -
    - -

    ◆ DCRSR

    - -
    -
    - - - - -
    __OM uint32_t DCRSR
    -
    -

    Offset: 0x004 ( /W) Debug Core Register Selector Register

    - -
    -
    - -

    ◆ DCRDR

    - -
    -
    - - - - -
    __IOM uint32_t DCRDR
    -
    -

    Offset: 0x008 (R/W) Debug Core Register Data Register

    - -
    -
    - -

    ◆ DEMCR

    - -
    -
    - - - - -
    __IOM uint32_t DEMCR
    -
    -

    Offset: 0x00C (R/W) Debug Exception and Monitor Control Register

    - -
    -
    - -

    ◆ CORTEX_PERIPH_BASE

    - -
    -
    - - - - -
    uint8_t CORTEX_PERIPH_BASE[0xE0100000 - 0xE0000000]
    -
    - -
    -
    - -

    ◆ ITM_RxBuffer

    - -
    -
    - - - - - -
    - - - - -
    volatile int32_t ITM_RxBuffer
    -     		-extern
    -
    -

    External variable to receive characters.

    - -
    -
    -
    - -
    -Generated by doxygen 1.10.0 -
    - - diff --git a/DOCS/html/group___c_m_s_i_s__core___debug_functions.map b/DOCS/html/group___c_m_s_i_s__core___debug_functions.map deleted file mode 100644 index 64407dd..0000000 --- a/DOCS/html/group___c_m_s_i_s__core___debug_functions.map +++ /dev/null @@ -1,4 +0,0 @@ - - - - diff --git a/DOCS/html/group___c_m_s_i_s__core___debug_functions.md5 b/DOCS/html/group___c_m_s_i_s__core___debug_functions.md5 deleted file mode 100644 index b0ea85a..0000000 --- a/DOCS/html/group___c_m_s_i_s__core___debug_functions.md5 +++ /dev/null @@ -1 +0,0 @@ -262f5a34489b1ae5e742eaa74ce5ee1d \ No newline at end of file diff --git a/DOCS/html/group___c_m_s_i_s__core___debug_functions.png b/DOCS/html/group___c_m_s_i_s__core___debug_functions.png deleted file mode 100644 index 8bd9cc3163ee8d996122470a66fd5eda1a1e00ec..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 1109 zcmV-b1giUqP)v2Z=;RN)?~? zB_K+=ltEOh^9xA89W;o-T|(myI=jI^isZtDB`XQKTZ+9So4wt={WH5W=lgx6mG0KJ z^E`Ljc|0?>+5-_05fKp)5fPDYOn%4C&dv>E%xxdZNO+PYd9t^+_sn-5ZHz{vJHB&} z<*c(vra41%C3KL>oGfSHpBV-3PwT?pr8Kb8#H^o{)qs ziXz`Bbhf#<$;QTp?=+;u@$oTdXJ-rht%qDhL@KE;iAZo%m_#HvDoi3092F)J362Vr zhydl5c>n0$%{zz$4&Szvunm?Zx(7IF7 zs^@j$b>(a-S2Q}xubIp{#13m`+ zrT!@CA@HPeU6bdms1`*a1ES zUIN!Dj{O7pxlPcn*6kmWFMUkq2ED+tY#P_s2^9K?*>`?Dwf{Hp1Mm@PVR|sz2kAF* zYpLlpZYX`?r(E^+tEzjcIvEiHHqUYzp87s+I&6(Op*VZZQlc*kS>gW z18k5^_pZ7QxGsvm?Q3&fzEGAG&$d&tzNT^uy=ycY-7&^I?yK^z(==+;MNveOBzMQ- zag(*0E5PTZ1?nr(DW8`+N$&3MCc05v*k(71+aHg|_3mIP($WO@ZMH?gb-(GzDjKXX z6FH_V4=PF+ zE-o$#_b(JCYwgK&I^91!JnTIw37@t0#CHyDB}uY>etzyd4Ozlk`_y+1A|fIpA|fIp ba{2rRz00000NkvXXu0mjfN4ORo diff --git a/DOCS/html/group___c_m_s_i_s__core__base.html b/DOCS/html/group___c_m_s_i_s__core__base.html index f63c92a..e3c8a65 100644 --- a/DOCS/html/group___c_m_s_i_s__core__base.html +++ b/DOCS/html/group___c_m_s_i_s__core__base.html @@ -14,6 +14,7 @@ + @@ -77,7 +78,7 @@ $(function() { Macros | Typedefs | Variables -
    Core Definitions
    Defines and Type Definitions » Status and Control Registers » Nested Vectored Interrupt Controller (NVIC) » System Control Block (SCB) » System Controls not in SCB (SCnSCB) » System Tick Timer (SysTick) » Instrumentation Trace Macrocell (ITM) » Data Watchpoint and Trace (DWT) » Trace Port Interface (TPI) » Floating Point Unit (FPU) » Core Debug Registers (CoreDebug) » Core register bit field macros
    +
    Core Definitions
    @@ -90,19 +91,14 @@ $(function() { - - - - +

    Topics

     Functions and Instructions Reference
     
     NVIC Functions
     Functions that manage interrupts and exceptions via the NVIC.
     Peripheral Memory Map
     
    - + - + - + - + - + - + - + - +

    @@ -138,23 +134,23 @@ Macros

     
    #define SCB_BASE   (SCS_BASE + 0x0D00UL)
     
    #define SCnSCB   ((SCnSCB_Type *) SCS_BASE )
    #define SCnSCB   ((SCnSCB_Type *) SCS_BASE )
     
    #define SCB   ((SCB_Type *) SCB_BASE )
    #define SCB   ((SCB_Type *) SCB_BASE )
     
    #define SysTick   ((SysTick_Type *) SysTick_BASE )
    #define SysTick   ((SysTick_Type *) SysTick_BASE )
     
    #define NVIC   ((NVIC_Type *) NVIC_BASE )
    #define NVIC   ((NVIC_Type *) NVIC_BASE )
     
    #define ITM   ((ITM_Type *) ITM_BASE )
    #define ITM   ((ITM_Type *) ITM_BASE )
     
    #define DWT   ((DWT_Type *) DWT_BASE )
    #define DWT   ((DWT_Type *) DWT_BASE )
     
    #define TPI   ((TPI_Type *) TPI_BASE )
    #define TPI   ((TPI_Type *) TPI_BASE )
     
    #define FPU_BASE   (SCS_BASE + 0x0F30UL)
     
    #define FPU   ((FPU_Type *) FPU_BASE )
    #define FPU   ((FPU_Type *) FPU_BASE )
     

    System Control Space Base Address

    +

    Definition at line 20 of file stm32f407xx_matlab_memory.h.

    +
    @@ -198,6 +196,8 @@ Variables

    ITM Base Address

    +

    Definition at line 21 of file stm32f407xx_matlab_memory.h.

    +
    @@ -213,6 +213,8 @@ Variables

    DWT Base Address

    +

    Definition at line 22 of file stm32f407xx_matlab_memory.h.

    +
    @@ -228,6 +230,8 @@ Variables

    TPI Base Address

    +

    Definition at line 23 of file stm32f407xx_matlab_memory.h.

    +
    @@ -243,6 +247,8 @@ Variables

    Core Debug Base Address

    +

    Definition at line 24 of file stm32f407xx_matlab_memory.h.

    +
    @@ -258,6 +264,8 @@ Variables

    System Control Space Base Address

    +

    Definition at line 32 of file stm32f407xx_matlab_memory.h.

    +
    @@ -273,6 +281,8 @@ Variables

    ITM Base Address

    +

    Definition at line 33 of file stm32f407xx_matlab_memory.h.

    +
    @@ -288,6 +298,8 @@ Variables

    DWT Base Address

    +

    Definition at line 34 of file stm32f407xx_matlab_memory.h.

    +
    @@ -303,6 +315,8 @@ Variables

    TPI Base Address

    +

    Definition at line 35 of file stm32f407xx_matlab_memory.h.

    +
    @@ -318,6 +332,8 @@ Variables

    Core Debug Base Address

    +

    Definition at line 36 of file stm32f407xx_matlab_memory.h.

    +
    @@ -333,6 +349,8 @@ Variables

    SysTick Base Address

    +

    Definition at line 37 of file stm32f407xx_matlab_memory.h.

    +
    @@ -348,6 +366,8 @@ Variables

    NVIC Base Address

    +

    Definition at line 38 of file stm32f407xx_matlab_memory.h.

    +
    @@ -363,6 +383,8 @@ Variables

    System Control Block Base Address

    +

    Definition at line 39 of file stm32f407xx_matlab_memory.h.

    +
    @@ -372,12 +394,14 @@ Variables

    @@ -183,6 +179,8 @@ Variables

    - +
    #define SCnSCB   ((SCnSCB_Type *) SCS_BASE )#define SCnSCB   ((SCnSCB_Type *) SCS_BASE )

    System control Register not in SCB

    +

    Definition at line 41 of file stm32f407xx_matlab_memory.h.

    +
    @@ -387,12 +411,14 @@ Variables
    - +
    #define SCB   ((SCB_Type *) SCB_BASE )#define SCB   ((SCB_Type *) SCB_BASE )

    SCB configuration struct

    +

    Definition at line 42 of file stm32f407xx_matlab_memory.h.

    +
    @@ -402,12 +428,14 @@ Variables
    - +
    #define SysTick   ((SysTick_Type *) SysTick_BASE )#define SysTick   ((SysTick_Type *) SysTick_BASE )

    SysTick configuration struct

    +

    Definition at line 43 of file stm32f407xx_matlab_memory.h.

    +
    @@ -417,12 +445,14 @@ Variables
    - +
    #define NVIC   ((NVIC_Type *) NVIC_BASE )#define NVIC   ((NVIC_Type *) NVIC_BASE )

    NVIC configuration struct

    +

    Definition at line 44 of file stm32f407xx_matlab_memory.h.

    +
    @@ -432,12 +462,14 @@ Variables
    - +
    #define ITM   ((ITM_Type *) ITM_BASE )#define ITM   ((ITM_Type *) ITM_BASE )

    ITM configuration struct

    +

    Definition at line 45 of file stm32f407xx_matlab_memory.h.

    +
    @@ -447,12 +479,14 @@ Variables
    - +
    #define DWT   ((DWT_Type *) DWT_BASE )#define DWT   ((DWT_Type *) DWT_BASE )

    DWT configuration struct

    +

    Definition at line 46 of file stm32f407xx_matlab_memory.h.

    +
    @@ -462,12 +496,14 @@ Variables
    - +
    #define TPI   ((TPI_Type *) TPI_BASE )#define TPI   ((TPI_Type *) TPI_BASE )

    TPI configuration struct

    +

    Definition at line 47 of file stm32f407xx_matlab_memory.h.

    +
    @@ -483,6 +519,8 @@ Variables

    Floating Point Unit

    +

    Definition at line 54 of file stm32f407xx_matlab_memory.h.

    +
    @@ -492,12 +530,14 @@ Variables
    - +
    #define FPU   ((FPU_Type *) FPU_BASE )#define FPU   ((FPU_Type *) FPU_BASE )

    Floating Point Unit

    +

    Definition at line 55 of file stm32f407xx_matlab_memory.h.

    +

    Typedef Documentation

    @@ -536,6 +576,8 @@ Variables
    +

    Definition at line 14 of file stm32f4xx_matlab_conf.c.

    +
    diff --git a/DOCS/html/group___c_m_s_i_s__core__base.map b/DOCS/html/group___c_m_s_i_s__core__base.map index 8c89e0d..5df0e03 100644 --- a/DOCS/html/group___c_m_s_i_s__core__base.map +++ b/DOCS/html/group___c_m_s_i_s__core__base.map @@ -1,6 +1,4 @@ - - - - + + diff --git a/DOCS/html/group___c_m_s_i_s__core__base.md5 b/DOCS/html/group___c_m_s_i_s__core__base.md5 index 8ee8dd7..b41a02e 100644 --- a/DOCS/html/group___c_m_s_i_s__core__base.md5 +++ b/DOCS/html/group___c_m_s_i_s__core__base.md5 @@ -1 +1 @@ -b694b6884d1ef5ebdc87aa78d9220595 \ No newline at end of file +f2c243b44cbe2e3b76862dc4cf826d57 \ No newline at end of file diff --git a/DOCS/html/group___c_m_s_i_s__core__base.png b/DOCS/html/group___c_m_s_i_s__core__base.png index bd448f70d62dd7158e0e6900cb894b3c9867f582..cd8e6e599199d15f26913bdbdfd718320b032109 100644 GIT binary patch delta 1196 zcmV;d1XKIp8LkN-iBL{Q4GJ0x0000DNk~Le0003^0000b2nGNE0LCD@N0A{Ee*|Mm zL_t(|obB8@Y~(~7$MLUCAQGa0{v?E`&|QI)txnJ)Djo%Q;>2A;98-aiXy~A$ro!5k z6da0lElnyA*ThP56d*+@f&>+*f`F6O6uX;SIeyHHA7k(SKGG^#Kj#1UCjRftc-J5z zA|fIpA|fIpG9E#G!S3$vwIB#?fBHy9x{+ns&-?rPzx&R^MHEH1eCHsWD-6T4BuO5w zF5Aj)6a>M|APDaFmzMP4Ht@agBwXl!QGA-sW(UA~tIMtw&83~4oz4@I?xkt!JB7xg zC}J|1_)bGMOp+vp=TGP%7ZH)sQqdFEUgUBiwe}Tx8{rQ_#+YmuK`~Je*zDHcX?7UMPx;% zbDBjxtvHS^ANl30KdZKFqNvTX*hTB>@-AzmEOuS{Rr@t`9rz0P1Nag62zZ|P{Rp0J zGtdwPL2&uVFE9F;Usl%RDO+b6uWH*mS(X*HU)E!*%cm$O*W)T%fA8a1nrd}UvrgR* ze)V}5!~L>0P3ADGa)bJLP}gH``E_`O`S;N80WSfMc~T(PzECdZPrkb6W&2j`XS$v3 zwr#M@2WWg;U1{>#y6UxP)*12~VAr|1%%Pe(Iy$-md=9*tTV+}(f3*(Ul8cKA>wSuP z6*ebJ)wZtdOye~@f2o%}wAG(Y@@bM&{Hbn9p^j)ep);}1Kwc% z8O`NKjxyk>e>MXSLH^3D%SmjrpG~}c`(2#$O^&~dcABVrypRZxlSc{twA55oH zvpcuTM*AE1Zt-{l_{VQLBEzAgDRs_$Cm`e3_7K@8e-%v;L+fzD`{HZ9vkSU4oQQ}8 z6-^Nl3o4o-A{JCMMMNx=UI;ol8O4pdWdj@@9+IZ1?=)n?oSvQ*F27PV!!SIX&1MJZ z=lZ0{x(LJY%y$m1vMf8$8@TuqhT%isIf#geh=_=Yh=_6%v*H}}F7@}fGL@!Yh zQz=ahA>~%hS7WR(s;Z*IP~{rxrSHdE@5ftjowN2iYn`+9-skLf_WAbH-z-f|2%QrG z001WtriRu408pAY_Z9&0WHU?gF>e6fGdD2=9Q|z18RaH_O2!!Gw7*Ii=DUQtgKhnCh@lJL3IN9C1 zgia@fS%hYeM`}YbLf;-So{o+CG^$d9S=+Fl^>CD3Q|Qr&2lH7FMA^0ZEV3eOdPJW- z6Kg<~lBcG5trO|+lHPtB*XdBKjftI6tUYqy*l&Cr*4?2hhA0Gf!cw3ED+v}`rL!mf zcOEe&{2wEi7OQKk;G6O?Mp5>d7BuHT%EPlm7GZOjNVqu}oYuT?2I*=oiQ#;iYj|~q z)6%=|Jhlw$?&TfX7ThWL3u~ap(#q2V%c$vX6&4jnSo@_9msvN~H_ORaSFHpNQ6P%B z^#Pp7zS>*$>J<{4Jt?vqI0a(Sq~|VHGH9;5t{(6z3cm%)9C#QV*`8Ll=p_j`ch;sT zHlgaaHl$*nC7gA8E0Pt4TDqJo20Laq3$MrL>=fqQqizLcB{?hMAQd6<(*IlPm&qZh zPSfsxMD}7hWXIwDe>;st+{72C67*V@pfAmhaFEGLAW4qp%8cx^;Xu%T{QlMRb`cXCG=H= zvAncy_!`kex)8`Sl`1l7q(N6R*YT8g^enJgv{B+&r#kwYOh>+&ot%G;L|CgBH9kD9 zufm$MgtvcjA139|`Y}IacD9*sS73MeA1epifqa3N0vCFFd+{>5VYgrIaj?yj_m`~; zM(Pk#n4N)hyhsVP0rZ5Y1rMG*6v?PgB!2|4KgaKk16A14>)%_rZTl{Qq2{?7^I4iJ z`X}^&U*)IQe^2zdSi8;CVqRy9v-d`KXh8d_^T8qx$Ap3H0O6{(Sh3we-YeLTUv>ZU z;%J6oN`uc|q#LiJEwf!}cbv+HKga}kd$DEN@uREaFa5U<@7vf0T|TQIMgxqW27M~# zo0Wx#@W&liT^8rR=9H=_CS29Qr90);K#Ac zU*4Az;h{bwYkl$i@hO6WUCmG2Yxq>r(Vm#G_y3(Lw1cj2WMYkDxjqtg9IY@BC>~0Y=YL|ferbTvSmA; zyk1IKa_RT`Xj27hKXgf0m6@Z-Jq(mIf}YakoclP4r3UX#SB>MY3s=m4jte+uz+WTR zaEH8M!VXU)-}|SwjadjQJ^zbDhTK`!Q)S)05?!>rOnChBs=8YbeUYpm4IAV`e=?{E z9FaaGhI=c?4q(=TGffMTjpsDsgYDEUqOP8z`TNE48?=mSL3Eo`MMefMwmNRpZ(Rjv z6zxTuO$J3shUg2ykHGYbuM!K=@Q^2EWo1gYvNUufH$QbpH=1cDV}m=TcDxEglj+TK z#Fg{Kwhb19>x`2J9_&&qa|z@^JAFRZ`DBP-^|`#d?+s>!3Meym7;NX`#=<+Dn1cwE ztZ9<6*1SackT+_{I5#^)CG!^HbA zOY=pCUD~RG%;7jCl9Q9s6Z`-l%)f)RISLFnpLN*xEYpDn&`c+HlQRi%eFBKC7`DW^ zd56bs?0bKjJ52!{PTEU*5{?_!`}OG9kGP&>+x(k(r3znFJwj2e-e<#8ai3*X?|^{JTgch#f>U@#Rdsld@~bJmq4 zd1(tayQlZTrQ7sx0qjV&OGkQU!Z5-riJ}0WT>bv{`1(@9kyQ9s?UG(;RQSjbGTkIs zow`QeTo}w5x!o9JR(2d+tpDD@AGCI?%_LuG59-_Vw*PQM9D9fW-=4;(Xe@4q2^Y!4#p!(3LTFW)AbOCtPdE zMSiC8OkZVQBJwqQqrScW{dQB4GU%+k|;Go(pJ+Kau#UG~0?w#_avYx{=kW z?6%vb=YJT9H4E7s^UF)sj8=VQ91;|?v1V7fU3J87Z?_soaH$Qq;^m9H&1ZdawIaC8 z+S8ys|MC*m+#A1t|0XUjo?l#CTk=TE+tV{iRKZejd^se{UM7vqR24%l$1(#1RAdNo z-1@OaIn=TeTX`2|t<>KiQt@qR_KSgtRHMwc{z@Ct(@XKbaS@PI0~Z(|(%(*H0E#K9 znwaMP+a1SxhGP|?^(_m~ec85jXx}hjE9%#D)<|JR;-$3u@?XNcY$}}IWyrKhN8}IP z3z7=dk}c2%f1?K;l62Vad{g)1+pXlSG1n&yB>$LWAU^`Vm`UKWrmi&Gs((MXRx|Gb zdU7K^Efk_AKEdarrUu7+&kux{n*C!_UPxYoWvIs=1)@vso?S=wZjJHLfO8(zQ${R_ zuhvhmPJBEyx}E)68M5ZkVoQFy4BU^O1MZx*Q)zqrsXf+Jz8^Ow*Dn?<5Rovnx$&8^ zKfd0hq?lWP(8htnyZkb*O=v30A{kNZZ}?Fu&w)hUvpU(Ul6TeCj|UpKMZJTUC=}^} zqlD;*Lo%JX3mn8yh{{b@Pk#VSn>)a~GlrBl2bq5-^mM8*o9Lw4C=Er)k$Q!}Wr8-+x;1vh~A8NN|w=Edon9%-7}c{ZfB zf{3bebbnflZ%oXOnxv#8xm24ZOOjsCn}lsn(@&HFGk*KE$g?q3TCQIaH`&qAVN`jl zG7_JcXQ2&26pS>Z49)s}a-L!h%0t-=*(?=Du$!CXcj}vLl?xF4d`8EhwtIQFyoi0f zOtK&ls-|Y8!NZCm;o3IRg*`ng>eE51oEqaBi$I%;*@rBQ9Ov!g!2qI57NO+&pt75n z%t?@jRMVuEEAwA?q!|}2_9qWt2IsL-upczeMNNiNtHn=R;W_cFkAkY@H?V5?80LgN zw4cl`amo4Q!+sxSW`uj@SUIZXC)+z;KRl+joTQ$z@X&40`!x?iAFgaasyiyloVt+r zi{Yv{)qI>ZA(peMfd=nXJm|IZZCjW}ZN1FJUzD|nAMW5IY z&gz}p_jPEo2b7(JDa1G_WCp$BtHDDFmaXJc7xDXaiT{tBnp!hn%D{EuJ)!S34}2L9 z4!ORC&9*$4LtxcaU~`&#&ew-E9L9dK*pr58Y0L#b>^To~9zMHXG!A2WHCZQ_w~{Y+ zq^0j{-N*j|8d6(L diff --git a/DOCS/html/group___c_m_s_i_s__core__bitfield.html b/DOCS/html/group___c_m_s_i_s__core__bitfield.html deleted file mode 100644 index 78f97c6..0000000 --- a/DOCS/html/group___c_m_s_i_s__core__bitfield.html +++ /dev/null @@ -1,182 +0,0 @@ - - - - - - - -STM MATLAB Simulator: Core register bit field macros - - - - - - - - - - - -
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    Core register bit field macros
    Defines and Type Definitions » Status and Control Registers » Nested Vectored Interrupt Controller (NVIC) » System Control Block (SCB) » System Controls not in SCB (SCnSCB) » System Tick Timer (SysTick) » Instrumentation Trace Macrocell (ITM) » Data Watchpoint and Trace (DWT) » Trace Port Interface (TPI) » Floating Point Unit (FPU) » Core Debug Registers (CoreDebug)
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    #define _VAL2FLD(field, value)   (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
     Mask and shift a bit field value for use in a register bit range.
     
    #define _FLD2VAL(field, value)   (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
     Mask and shift a register value to extract a bit filed value.
     
    -

    Detailed Description

    -

    Macros for use with bit field definitions (xxx_Pos, xxx_Msk).

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    Macro Definition Documentation

    - -

    ◆ _VAL2FLD

    - -
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    - - - - - - - - - - - -
    #define _VAL2FLD( field,
    value )   (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
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    Mask and shift a bit field value for use in a register bit range.

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    Parameters
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    [in]fieldName of the register bit field.
    [in]valueValue of the bit field. This parameter is interpreted as an uint32_t type.
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    Returns
    Masked and shifted value.
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    ◆ _FLD2VAL

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    #define _FLD2VAL( field,
    value )   (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
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    Mask and shift a register value to extract a bit filed value.

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    Parameters
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    [in]fieldName of the register bit field.
    [in]valueValue of register. This parameter is interpreted as an uint32_t type.
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    Returns
    Masked and shifted bit field value.
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    -Generated by doxygen 1.10.0 -
    - - diff --git a/DOCS/html/group___c_m_s_i_s__core__bitfield.map b/DOCS/html/group___c_m_s_i_s__core__bitfield.map deleted file mode 100644 index fd2440e..0000000 --- a/DOCS/html/group___c_m_s_i_s__core__bitfield.map +++ /dev/null @@ -1,5 +0,0 @@ - - - - - diff --git a/DOCS/html/group___c_m_s_i_s__core__bitfield.md5 b/DOCS/html/group___c_m_s_i_s__core__bitfield.md5 deleted file mode 100644 index 1de1e52..0000000 --- a/DOCS/html/group___c_m_s_i_s__core__bitfield.md5 +++ /dev/null @@ -1 +0,0 @@ -55d6c6071ea79d7bf0c9494dd61cc076 \ No newline at end of file diff --git a/DOCS/html/group___c_m_s_i_s__core__bitfield.png b/DOCS/html/group___c_m_s_i_s__core__bitfield.png deleted file mode 100644 index 2ddc2d29c6b13fd84d3144251fc7f0ae7734dfa5..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 2306 zcmV+d3H|noP)~0&F0D$r8Xi$Aqd_HiJBb9jfxk?sOd!^?b%3Tu(jRk z#q5~LoOyZX<(X$*ejiwJc4y{!{<|mH=ReO|Ktx1DL_|bHL_|bHL_|bH1ia)6Cr_R{ z=y~2z7s1Fl1VM2A%$YN2!L+bqvx^zVBb1&*v9h$03sCeaRO*&pYaQ-pek6 zkNjLq=jYo4F35w#j6|#>R&0Fr-Iz zc6L}Um#)JQ$>qBaKtx1D+*3jzA|fJ62t-6gL}Z}BS!|YkI2|vx^#)fVv%~RkvRlu4NMRO znRmo(a9zI$q&HU4U8;ykmsp)tm~}TCJ(91-|I9nLj-oR2V#|A;7Qd}Hv+B!=EA1SU zbF&a`1VokfQ?EA`k4@K8zl~MJ*n8qP8 zB&|*=EE-mbKesUiQKx>BGMh{WOybI`FRP5G=fw1L$g4l?xl~g$tPp=*b_l}s+T_n= zV@(^MFZ;Yq>`*)>py;@1Jf@$GNS}3T*`e!(rEdME2}JTywcaw<)p>7u*Sh|ljYXYt z?<&`pxyEK}T^#T4VoV}U==8Ef8(q?_ySYv8uIt8`oI_F6aGTawwp_8J&RuHVJKW?P zh@u9v>vz;$k58m6Ruh7{-N`l@n=UnAY2EknV@;GFDf(Sh?QPJIK{a(}xt&F1g z()By)uE!_RmPUpQ(q{BG-B6UhV>YS3>D~fcy$^X4AZ^5AtK6DC2s{q_2Dsl<5M`yU zC}?_Vo{ipuqB#Uj*Vh#tjL!oe0)7H~+i@(Vxtf5SHZ)tOoakrMYpNXUg2s9XOuCZG zbT`-S@~%>U*0H=LjPYYtmO7^O66D2cTA#^#jb5|)d#UODz{9|ofG+@dtzUoEW~EIt z>0&R_4PUm)-t^k|vAm^`MfJxMo;tBcWtm)CHOVrK&%sjB`++Y4Ujgn}zxG_40o3Js z0&?BGY0|!z%hp@93|IEFCe!Kkgy(rLs~fGFw*S)it;>Ekn-K)TV`vg$4>KkvG_I=#xE589q}Kd@Q;_Y%$vm;#^R&O4&PeHnIL-R^xcb~o@S z;otp-*ROf&$EcED*L$Fp*{>z<+O%_v%BcF@Z4SjKA!tC`jdIVE04`s?yb1gf_;lis zX%cX$*@(=YKYyOdWa6rN>y!l8bMxlSeZWh=F<>7MkTPtW!3UmNKU#P0+_`^kZEdw) zZ=`nQ%hky@V?WUI5-$AA849 zOd_`J0zU&jOPC0MkK4mxZ##;q5!#!^9-A@tJ|W1P6jEhhfU@FswNal*Jg#G?X&d+! z@Dbn<;OD@92=9=T9LP|;2K<ab!F?$yRNQY&ml0)jiF}tpUWI;vYe567kJ%u z5Hf6o8Zu}~-}V(4P)~q3l5BAE_VjPM%(CT(h#jNsAtXX^;zCg}P&HZ5f3hUv#^8DgOty6_ zv-M-qxyi=3N_|ekhQ$7>Qcn4*UOyS zM17{mvyKgH$)Q+QH2E*@d7a6KMG1p+%atov^m`eA>({Sm9_w{NFlK7>MWijh?_b#6 z-DP)o*L5gjQSTFi0dB%$Bx@LAjGu*w*fpQef8;s_v9I?D0gQJBf0^M85fPC*gIZ-E zA|fKyC?OCL5fLQ>A|fK9gg`_@M97&`sP(2I>8@S7#&WrI9ftJCty{NThaggDPeS1P z{?*lLb#{Au+eJJw0>1BGbsa-hK@gn1apQ*TFr(^b diff --git a/DOCS/html/group___c_m_s_i_s__core__register.html b/DOCS/html/group___c_m_s_i_s__core__register.html deleted file mode 100644 index b8dae3c..0000000 --- a/DOCS/html/group___c_m_s_i_s__core__register.html +++ /dev/null @@ -1,108 +0,0 @@ - - - - - - - -STM MATLAB Simulator: Defines and Type Definitions - - - - - - - - - - - -
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    - - diff --git a/DOCS/html/group___c_m_s_i_s__core__register.map b/DOCS/html/group___c_m_s_i_s__core__register.map deleted file mode 100644 index bd7145e..0000000 --- a/DOCS/html/group___c_m_s_i_s__core__register.map +++ /dev/null @@ -1,4 +0,0 @@ - - - - diff --git a/DOCS/html/group___c_m_s_i_s__core__register.md5 b/DOCS/html/group___c_m_s_i_s__core__register.md5 deleted file mode 100644 index 2854755..0000000 --- a/DOCS/html/group___c_m_s_i_s__core__register.md5 +++ /dev/null @@ -1 +0,0 @@ -ba61c521b1934b774702a65b745c0853 \ No newline at end of file diff --git a/DOCS/html/group___c_m_s_i_s__core__register.png b/DOCS/html/group___c_m_s_i_s__core__register.png deleted file mode 100644 index f6e95a03e997d1a465f797075e145db23e45a560..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 1623 zcmV-d2B`UoP)>dKMOLD_$Y&71tcxREMPq3Kk-Fr-FiT z*|D~>(n7@6&ahY7oGeyXdX?ZJYv3#_ERI#q!a`WEQqhUU%pAE)-sF8VZ}KLY?+1q6 z$)ERqCSjh*JW1Y>0000000000Kp&#e0RY%ek|Z}m$ADpokmLbi!btJ}FkvKl z0GKe6JOE7C#?>{qZryq=ilS>Ff&oIw^ZdKpw{QOzIu5|MjU*pM(KW8S#SXeD>8sE| z^d*Wm?}Nc*;!4qd46q!T3r> zp_JqI`Fe)1ZK%lu*jZIcIM4ISZ#rW|k_RA3j~&Gq|E@(*^ypEXR$jJhy{2|dOv@Jg zt!l@%eG}6+9hX?@woQ53w(-_sSOZ|kl#f(RN3wM#jP>)XW$U<nf`rn5(v6!|^ zU0JM)@(xKJ*g@sQQl3_~d{=R}_GuGSU!@n9?bCOSo+JwK+;t>* zV8^s62~?F8+S;aE)0ZJ!72}JSBtM_eH>Ra&+Pa-IO*Nm-TeT5dRoqqEXRWW-7;+!g zEjQNvyz;c9*Cf3q=_5%$h7G45+a%kz$+N2jZ*%@(?7SVxS0y%=H*b0Q5x?;_6kkio zq!wx))xG`^?&ouoUY7K>q}L@~SWW*VSVWFYb?UkkgvE8L);BHN)OS-&zOGN3_1Y|7 z6_ab3si^KlW1Dtub#@8m`bZDM#XhnYOL|e#=aPPxbXUt?-?>n?(vYpM{wO}G=9{J! z=hZFSG|x89sy@rh+4f)8Pt%8v>GhbNmzOtvfY`L#R`1uz&*$?;kK(lAU(^5P_3GNR znPXiV@bbC`c~5WlAc}7JLj__pewze zcrAZbUq830?-u8q{&$&Y8=Fi2T^$v-dF?*>Dn8$4AFVaD;bR||`gU+p(wmYJNiRtH zN7DJ#yz{1&fT0@A9j`uWw{>kawQtjZ+Zc;w6H{^=gRbLja}L1P{rmSXN%~&WFOojf zGQmssiTy-U9^!F)eC+&su{(OdgtCjHT~nLonsd{ee~k6%KDXykx$fsGSFT+7`Q+r} zOD(UIc~{aUNq+!Npm2V{d(5BOE?d|P_=oTZ1{|wQW4E zafjMRzI7DiPgT`n!`<1)l@Y^J_l6Lw$ws45PhefJP^wt9RZ=_M_%k$*$Wo1y*_caAq|8o%Cm z+f}A^lasBDkH92JZbVUZhaU~;Usdw+am5VkWm%>?&u<-LG}S^_JTxj^p06Y;if$u*GBgupr3~KvgLQqw;6y0H(lYym;3(Y{sau?Z4{z zkdfpEV4LgrfibWdE60}WI5usC7+=2&BzXXxa~WQE+kUzjufC6g#JWO~2hgjk(n)ci zkM`G^$|`Mt(P>QOn$Zkv0ARP6jCct(@FBc$mMx{#LbJ4q&SX`L&pFB00000006+Q`X3*o VX&+l?xxN4Z002ovPDHLkV1gW5LUjND diff --git a/DOCS/html/group___c_m_s_i_s__glob__defs.html b/DOCS/html/group___c_m_s_i_s__glob__defs.html deleted file mode 100644 index b8a0b52..0000000 --- a/DOCS/html/group___c_m_s_i_s__glob__defs.html +++ /dev/null @@ -1,87 +0,0 @@ - - - - - - - -STM MATLAB Simulator: CMSIS Global Defines - - - - - - - - - - - -
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    CMSIS Global Defines
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    IO Type Qualifiers are used

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    • to specify the access to peripheral variables.
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    • for automatic generation of peripheral register debug information.
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    - - - - - - - - - - - - - - -

    -Macros

    #define __CM4_REV   0x0001U
     Configuration of the Cortex-M4 Processor and Core Peripherals.
     
    #define __MPU_PRESENT   1U
     
    #define __NVIC_PRIO_BITS   4U
     
    #define __Vendor_SysTickConfig   0U
     
    #define __FPU_PRESENT   1U
     
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    Detailed Description

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    Macro Definition Documentation

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    #define __CM4_REV   0x0001U
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    Configuration of the Cortex-M4 Processor and Core Peripherals.

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    Core revision r0p1
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    ◆ __MPU_PRESENT

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    #define __MPU_PRESENT   1U
    -
    -

    STM32F4XX provides an MPU
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    STM32F4XX uses 4 Bits for the Priority Levels

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    Set to 1 if different SysTick Config is used
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    -

    FPU present
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    -
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    -Generated by doxygen 1.10.0 -
    - - diff --git a/DOCS/html/group___configuration__section__for___c_m_s_i_s.map b/DOCS/html/group___configuration__section__for___c_m_s_i_s.map deleted file mode 100644 index 217a8c0..0000000 --- a/DOCS/html/group___configuration__section__for___c_m_s_i_s.map +++ /dev/null @@ -1,4 +0,0 @@ - - - - diff --git a/DOCS/html/group___configuration__section__for___c_m_s_i_s.md5 b/DOCS/html/group___configuration__section__for___c_m_s_i_s.md5 deleted file mode 100644 index cac4b9a..0000000 --- a/DOCS/html/group___configuration__section__for___c_m_s_i_s.md5 +++ /dev/null @@ -1 +0,0 @@ -37f59a82b7b609696c08a277ff6d2f4d \ No newline at end of file diff --git a/DOCS/html/group___configuration__section__for___c_m_s_i_s.png b/DOCS/html/group___configuration__section__for___c_m_s_i_s.png deleted file mode 100644 index 3a6631615ac760d9af647e9d08e506a20ce3bc14..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 1473 zcmV;y1wQ(TP)o7!2cSSm5ur&6nlwoj3ZxV(6bOF=YYMLq$2*=G+cTaS@AH#Z z7kliP*U9dinXxkm5D^g(5fKp)5sjPh9RQ8jbUMB7I|dq$BuOr^EIX?1d)ikpG=4&e z$G&5r@mMSt2LSF>_c4KyQpahK2U1myvMuYCtG zq%=*Re4S;Ple)7kLz<@6>u(#2&-QKbeGQGzfyMrf9fRrzd0o^$5H>#`^}2?BkNa-l zhS08ob6^w@ifKKrhU_EY7>`foS|KV4troUI(XBWS&1-XH6TlR}cK~jCj>VYlj-!v{Wh?3UPF`)=R~_s7I#jImz=ROU z^IW;V>6k8cm-|#@y0}c+P}LupX92to;C%pZ;Qya(@Y%LXH|#Mzrcb-F`b|H?s(OIt zgzWm7>UDN41BSf@os~EDbUM8+gm~PhahD0KO?#$omI+LCoXIu0mZmB4Jby5o&6=LX ze+s~B06qfnE`VnMESCFA8vuTH8fb&Py}dlv1r1{wwyuNaf`$jP+3d!OtWNJjRue?^ z-}*k;kgYFSo8@-b1k{x1nzmJCJtP2j0DJ-962P|r-a|1|6u6nZ$WX|`Bx+`52w4v2 zs@t-1-EgmZZvA*w{i>K;_m-;d)Z0^)b?_33^}s&{a0kHO0B$YIcr&IaAH$!%R7p36 z_-(NE#+M}<-3L~d=uGSHGQ6|h`x?UG;o&O)J_qn(t>~8IaGBriMr7{n>mJ z#rC0(EnXL#{N{Es@1^5&a$VKK>f8I;+1dH=^z`&A01p8?0`LNE_P%r;0r;y^<2`L{ zZLQTR8ZAP4(;UfSNokt6P#t zcTOyvOyXDfS9M7mvbt4wH)ZYiX+x)aP4%9Zs?36a0UR!0p8$9Zzy|={M3KY<__wZ| zxO{}dbiFgxe$(Sj|LEG}oKRVNgO?9|R$sF6>UO=nX}hUjS(~ahbnU5PZ&Qy+nPqh5tQ@Bu9bZdS~|WH}v@Y3gAlsucLU};!nTf#6`B|Rk^KO=c+4{r`pRl zOnXROdQ!3VzJLhkz^IpBdxPf(j&oo{8a5}rZBL*# z4gE}#Vw-b9)wmwm_V%`qc&Os!w<>4=hQNi^XDbaD03`Ty)eZ zNs3o=Nca8z-aA+{C_u6JG=`?MA2dbBcf - - - - - - -STM MATLAB Simulator: Device_Included - - - - - - - - - - - -
    -
    - - - - - - -
    -
    STM MATLAB Simulator -
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    - - diff --git a/DOCS/html/group___device___included.map b/DOCS/html/group___device___included.map deleted file mode 100644 index 65d5a82..0000000 --- a/DOCS/html/group___device___included.map +++ /dev/null @@ -1,4 +0,0 @@ - - - - diff --git a/DOCS/html/group___device___included.md5 b/DOCS/html/group___device___included.md5 deleted file mode 100644 index 8a43e73..0000000 --- a/DOCS/html/group___device___included.md5 +++ /dev/null @@ -1 +0,0 @@ -0386b8a2c46ee04034c9ef68f96cfb2a \ No newline at end of file diff --git a/DOCS/html/group___device___included.png b/DOCS/html/group___device___included.png deleted file mode 100644 index 23c8bd7783fa9c14eabc5d40f6f37e1bc828d083..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 1089 zcmV-H1it%;P)B52#9(>ean>r{4#J z(JSfIBRD;JUP*Tb5fKp)5fKrQvoraIwY9a6jWJh31hdGjwU0J7HvSDAhl^gXcRh3r z(vB#K_L3xdoNimnuVjq5VvM;zy|6mt2Jn06AYAD4u($?;!6tAm-8PmKMv^3HJ)o|L z<2ZB(jjgP#u)Mq+It=k>cXyYAgM+d5C_pSCGQ*S!f3u6q{ z+S2w(>$vniYAah-71s=V7x)Ue1$+s-bJ9LnRbBo)mpG2Sz5AkfXxcUNAGESW;*w-$ z)LX!(z%Rga;1A$yP7}i1OOj+EUgGM4R+B>dik<$OZ_Bs)xRMv`b2MM4dMJu@(tHD# zfuDf?frr3d;5~-lN%2y}&AOr?Mm~AenV&RF@iBxMZQEoYb&p}vwpIJ~$;$_CRLZC4 zizDOk7E|47BE5coyRu~tE;4-A{4VebaLj2%(1}Dak{?pI3^B_3@X>!& zzrK&5C|T4wKA(xfTcu#FeKXa)+7~5{y8RcaI$=GW(9X8Dwk`oXz*FEyh6w@c4-x(Y zY>4Uj_}J~B9i@jFXFbWybrtr-Y(hp0r1Rq$4x|0d$*q2ev+^VPb#K;3^V`qp=uaX_asdZKSt{Z zetPjY@ICM$@EPzk@RDK4{wiQxt*A2$NM8|0LkO4gxyv$N7NPQKi zQ;nki){%}aUlEio^I!n{buxVid;xp|T;;TKnEB+Lm;dk$~ z>$xr~J3e2=&g5RNcik9se-X;ASrNxE*4i8We*Y|E^K%Rn!!6)*hBqdI3?J6l*R6hJ zW$~Q+$jWBF-_QK=(%fBvI^+=ejbY{R5%3~xIMNlJdM-Z4o`()#k(8C(s*sfwq=R(g zm(%b;L^6~VL?lB=K}0f?6htIL{|rWI+27wU{Kp|OzmATM3fsq$LKH=NgTY{PdwaX} zpt>ZAqP@^DxU$x69v&Ws4ntZHMbYExwM0ZjL_|bHM5?_8BV-)zlh$s#00000NkvXX Hu0mjfw~rEj diff --git a/DOCS/html/group___exported__constants.html b/DOCS/html/group___exported__constants.html deleted file mode 100644 index 6ee3d73..0000000 --- a/DOCS/html/group___exported__constants.html +++ /dev/null @@ -1,107 +0,0 @@ - - - - - - - -STM MATLAB Simulator: Exported_constants - - - - - - - - - - - -
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    - - diff --git a/DOCS/html/group___exported__constants.map b/DOCS/html/group___exported__constants.map deleted file mode 100644 index d9ae5e6..0000000 --- a/DOCS/html/group___exported__constants.map +++ /dev/null @@ -1,6 +0,0 @@ - - - - - - diff --git a/DOCS/html/group___exported__constants.md5 b/DOCS/html/group___exported__constants.md5 deleted file mode 100644 index 4264c26..0000000 --- a/DOCS/html/group___exported__constants.md5 +++ /dev/null @@ -1 +0,0 @@ -38739ca634556304f272f4cee6ce203b \ No newline at end of file diff --git a/DOCS/html/group___exported__constants.png b/DOCS/html/group___exported__constants.png deleted file mode 100644 index ef38c31f08d212b4dca512e7a87103f990c247d7..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 3595 zcmZu!do+~m_aB!?9hc;Aj_aw$r8G^hX*7IGgCRr>Aq_DY5s_TRwNolI7%@qR1{uw` z4RRZE;w0B`7`KseDW**0ni-<}-Z|^H*7x_vZ@uq&pLeZiKl^z;dp~>c&wg~#(MEQk z>OK$%B#X2??*ame`vCued!>MH6GoQ|3{uzaZO(&sMbC@2@@znofjocqa`bcll;>-W zF?Yu5Zs)Dw*%UKr)qjTH7bLXD-a0q_wiP$c_hC?wkw zTzfejPAJ0pTle5CTM2(f9pvIW-wgOWKSLRf6k|OV=ruoBL78UDOYRjw?LFjEFw#Xq z#|PLz?CCvVpFQ5d5`t3FzY`!}g2X{MfA^Sm-=2K!t5>2I8{moQeGJzyrOM#V^uhT>)K`!lQ3~(ed(5#u;n2f(7&Mv5zFiM|MPR+m)_?3 zQ)$2k*umPAnxT}kwSmgDrl9x`uo4z-gt?BaH0L+JE^Z}9Ue-{2T@w7ky({hKKyA-^ za?7ioGIjhD@E+%d{glA*n_CfU%t&AIB{Z8`_KXJSw<4A=O&HeoIOv!63UVu;RX_gY z^Si@OPJXrS1%guN-2OW;_U7fU(o25yTA|aRgP*u%8}}~;T)RACn8MmDZ3zH0 zQk3N;E7YReTx;2$V}kxg3u_DU%JBb!Ar%W-ju=H)|f%c97zyrw{vniMf&1 zkwqXm2NM1Ob0u>M0$7MRtdmqjUXn?k{20-YFI%7>_^a?Fa>yH^dmPcLN~`&LHv2o7 znvc32GPRaQwYRq(rs}(B-@1@H>5r>?pW2ksJS_4@tegM2cs9KR`3AtU&HZE+-ARPLS3&IE^LlGH6KO-+zApvV3m{{>O}IlSl#y^!zCl`B89fW}VTPRQ2tu&}T++rI^p>zf@CG zdu|>@(;pqF;0OW95&s)8Qu#r8_0;b}j%OXQ86O|t3up@p2+(cfotSY;o|eYDoOvJwtqhfz z2@X~!dVF8ko;!pm-1Ly=)0icHREmyl;h z@m=4<5u=xgGEa>afj~4?08HzaTy)6st){f2xD!ZATeGm$WO~W2X-9dr_5i{9E#S|T zdF7R&bv~54y#y}wP7J5V|FZc$Zui8=Bbx7a!lwVSBQr%(p(@b{^!P~n@*gX{Uv>SR zGTYAICy5!#48x+KVX2$Fyx5s5q=pZYbc<=_<$ZQk4IM1QBPKaYsTA5;RNoHqB2K$$ zEOt&Ypb|_)OTsQU{qz1H!@PTPVu8wC7ulIC*Q*jC)BS^Dw#S%-Cn*Fg22;F!?~eLv z`!bvipMxS@pdMdj^z~Cqq8dK^q!o3?$G~r5yLv{6Q8(S)Z<#)#P{MN)buu2@blblK zvXI+3y3)?D1X()md>hwzy^?55fE)A{sU#L&(5Zl%ru}fo9M=+s_6Jx9_Q+@nkKAyy z5)Ttv69}=}cT-CqP6WGtj~K0w8OwoJEjC56-`E_K+LL zuiagaG48;})Y9KG3(SQB%x=FmYEd^&WxMw0)o)EpO(;Spbz=C!*;-tlSIYX-iIOA!Lto@CFQBM$s&9;MuF0@;s)6 zCGuX=UD8@{D{B!mTd9 z$lfb|Yo7+ox`o1h(j>jNA_{KwUUMs@`)zsYA{>?wD)Y3`&laOwxZ^(Zn~ht7NfOlA zphp*+rn3MQ(nuRA5cv!Y-$}DK^@zI@yFQYej5=D^qh8(0t7TuVm&GhU2A4KLCddCb zMX2>aGwHE6M-i{KCup2*zqf$7gJ1>M^kTY!YYA$X+)-Nf@QFGYXtvguXH@sGE2FNa z<{$fbx%-cql~weffq?;|;V<7Vf4&0VI5HkaV%0PzwM!+aMr*COtCz7BJs-`xlOhdz ze4Z(+rRa4HULuKb+ThvOm94XI98VRAOBTw`)MTDT9t&MTj$c$vF79-8 zo2qYXrlO~Qa|t&hU9tY^IH!A8MP{rkDWgxgtZ11TuCUp4QB1)9_GMUT&enRO77YKFt`C9cF9(vB$f%p{*l?b^|0uM-u_bo^y`$MK*E)oL>H|nSDItpD zK4saM#chUt4l_PXJmJM|N%-+yTa?z7COI67eLK>(6r~!g5~Gs7stjp?uJKPa`@kX> zm4HN2+%fp@IUFZg$kBH@_dv|d08Nncjfhx3w(^ltB@vprCW*tFKhm-|%{m)MfQd*! zN4UnO(VXyQg4Cwm{B#U#4^=EwTqSuwLkkp;lp$d=Dd*}EpVyHEP>ioea@hH{AA-qZ ztHC7x5+^rc3N#>*xc|8nU2^A-iT1`&u?&zF$g!`{Ci&8Od>Zdg(wJdGs3J7%c!e~O zTyMkp|7uu$rv_*+Ym?oPSwYQhEG0;r_3>}qZIf#~Gfj|F6uvI74K4yDC`B`OTGbes zp@TG)q~%7I4w3}+S^u@Wmuh#S;@&!!Dcp5&p*&j_OSJu9E{K^q^(ea%VVIj62l?P< znP(RPZPX1+1M@qFVyX_dH=5+V5EZ1LKS`0?;Vgpj33G<~Ohz&kRCJ^;eb=SKu-#&s zu%<|puid5jb53#-4^&}vu#bQ$`*=9&VRkiC0!?Z$c?(FiByA&|1~sJ;yc0Mk-uXX# z`sX>c&;!f>-qlgHbBiZ*yaWYr;#=z)?T%yFsZ1f<%@?rqM}Z|HRFb?cHJ@@?OFJPD zsKW;t<;l1OE|88LV&&QPogLK_q`ktTj-0Q9DZ5n~)8pt{t84_+^vKesliXW^F2e^QMLIf{9&=`0uxMlOggG5aHAC(bpmKmghNVmY9T(@16{k*K**wTs$1XmymMwX%)@w`2PF{?1^{q0Wir?rBOq$L z)o-Q-$9Km^>hQ-Xl{Zg^u*OC%eo-(}KZ+#Sd6v#H2EPKRu!v9Ewjmpul%X*1KoOHR zF@AEMRArVj#HooebNMgB5;50`vexBnNk?B$iFMUo*f%0x=<-L1z$FJc^YvFXW!zgZGU&zP+lp?J z&P6#J9bP}~w-=6EsJXo;;dmavJTG6$>nsU07^dp31Qg^8Xuc!9G29UfuHaw0DJ6-T z0nGb+s}any!>ia4s0fnbJ-g@&w9!8S7XAM>B947T@Z-^8Crb^OpxAK{JGSPo x%yvxE@9^1|fD{_&wNE1n{C|2SFt&cj(w8<#$b3~D19W#FB*O7L^_=(J{{ii<5BLB8 diff --git a/DOCS/html/group___exported__macro.html b/DOCS/html/group___exported__macro.html deleted file mode 100644 index 25c57b9..0000000 --- a/DOCS/html/group___exported__macro.html +++ /dev/null @@ -1,470 +0,0 @@ - - - - - - - -STM MATLAB Simulator: Exported_macro - - - - - - - - - - - -
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    CMSIS » Stm32f4xx
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    #define SET_BIT(REG, BIT)   ((REG) |= (BIT))
     
    #define CLEAR_BIT(REG, BIT)   ((REG) &= ~(BIT))
     
    #define READ_BIT(REG, BIT)   ((REG) & (BIT))
     
    #define CLEAR_REG(REG)   ((REG) = (0x0))
     
    #define WRITE_REG(REG, VAL)   ((REG) = (VAL))
     
    #define READ_REG(REG)   ((REG))
     
    #define MODIFY_REG(REG, CLEARMASK, SETMASK)   WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
     
    #define POSITION_VAL(VAL)   (__CLZ(__RBIT(VAL)))
     
    #define ATOMIC_SET_BIT(REG, BIT)
     
    #define ATOMIC_CLEAR_BIT(REG, BIT)
     
    #define ATOMIC_MODIFY_REG(REG, CLEARMSK, SETMASK)
     
    #define ATOMIC_SETH_BIT(REG, BIT)
     
    #define ATOMIC_CLEARH_BIT(REG, BIT)
     
    #define ATOMIC_MODIFYH_REG(REG, CLEARMSK, SETMASK)
     
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    __STREXW
    #define __STREXW(value, ptr)
    STR Exclusive (32 bit)
    Definition arm_defines.h:263
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    __LDREXW
    #define __LDREXW(ptr)
    LDR Exclusive (32 bit)
    Definition arm_defines.h:230
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    __IO
    #define __IO
    Definition arm_defines.h:8
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    unsigned int uint32_t
    Definition stdint.h:64
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    #define __STREXH(value, ptr)
    STR Exclusive (16 bit)
    Definition arm_defines.h:252
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    __LDREXH
    #define __LDREXH(ptr)
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    Definition arm_defines.h:221
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    unsigned short int uint16_t
    Definition stdint.h:63
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    ◆ ATOMIC_CLEARH_BIT

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    -Macros

    #define IS_ADC_ALL_INSTANCE(INSTANCE)
     
    #define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE)   ((INSTANCE) == ADC1)
     
    #define IS_ADC_COMMON_INSTANCE(INSTANCE)   ((INSTANCE) == ADC123_COMMON)
     
    #define IS_CAN_ALL_INSTANCE(INSTANCE)
     
    #define IS_CRC_ALL_INSTANCE(INSTANCE)   ((INSTANCE) == CRC)
     
    #define IS_DAC_ALL_INSTANCE(INSTANCE)   ((INSTANCE) == DAC1)
     
    #define IS_DCMI_ALL_INSTANCE(INSTANCE)   ((INSTANCE) == DCMI)
     
    #define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE)
     
    #define IS_GPIO_ALL_INSTANCE(INSTANCE)
     
    #define IS_I2C_ALL_INSTANCE(INSTANCE)
     
    #define IS_SMBUS_ALL_INSTANCE   IS_I2C_ALL_INSTANCE
     
    #define IS_I2S_ALL_INSTANCE(INSTANCE)
     
    #define IS_I2S_EXT_ALL_INSTANCE(INSTANCE)
     
    #define IS_I2S_ALL_INSTANCE_EXT   IS_I2S_EXT_ALL_INSTANCE
     
    #define IS_RNG_ALL_INSTANCE(INSTANCE)   ((INSTANCE) == RNG)
     
    #define IS_RTC_ALL_INSTANCE(INSTANCE)   ((INSTANCE) == RTC)
     
    #define IS_SPI_ALL_INSTANCE(INSTANCE)
     
    #define IS_TIM_INSTANCE(INSTANCE)
     
    #define IS_TIM_CC1_INSTANCE(INSTANCE)
     
    #define IS_TIM_CC2_INSTANCE(INSTANCE)
     
    #define IS_TIM_CC3_INSTANCE(INSTANCE)
     
    #define IS_TIM_CC4_INSTANCE(INSTANCE)
     
    #define IS_TIM_ADVANCED_INSTANCE(INSTANCE)
     
    #define IS_TIM_XOR_INSTANCE(INSTANCE)
     
    #define IS_TIM_DMA_INSTANCE(INSTANCE)
     
    #define IS_TIM_DMA_CC_INSTANCE(INSTANCE)
     
    #define IS_TIM_CCDMA_INSTANCE(INSTANCE)
     
    #define IS_TIM_DMABURST_INSTANCE(INSTANCE)
     
    #define IS_TIM_MASTER_INSTANCE(INSTANCE)
     
    #define IS_TIM_SLAVE_INSTANCE(INSTANCE)
     
    #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)
     
    #define IS_TIM_ETR_INSTANCE(INSTANCE)
     
    #define IS_TIM_REMAP_INSTANCE(INSTANCE)
     
    #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL)
     
    #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL)
     
    #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)
     
    #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)
     
    #define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE)
     
    #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)
     
    #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)
     
    #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)
     
    #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)
     
    #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)
     
    #define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)
     
    #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)
     
    #define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE)
     
    #define IS_TIM_BREAK_INSTANCE(INSTANCE)
     
    #define IS_USART_INSTANCE(INSTANCE)
     
    #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE)
     
    #define IS_UART_INSTANCE   IS_UART_HALFDUPLEX_INSTANCE
     
    #define IS_UART_HWFLOW_INSTANCE(INSTANCE)
     
    #define IS_UART_LIN_INSTANCE   IS_UART_HALFDUPLEX_INSTANCE
     
    #define IS_SMARTCARD_INSTANCE(INSTANCE)
     
    #define IS_IRDA_INSTANCE(INSTANCE)
     
    #define IS_PCD_ALL_INSTANCE(INSTANCE)
     
    #define IS_HCD_ALL_INSTANCE(INSTANCE)
     
    #define IS_SDIO_ALL_INSTANCE(INSTANCE)   ((INSTANCE) == SDIO)
     
    #define IS_IWDG_ALL_INSTANCE(INSTANCE)   ((INSTANCE) == IWDG)
     
    #define IS_WWDG_ALL_INSTANCE(INSTANCE)   ((INSTANCE) == WWDG)
     
    #define USB_OTG_FS_HOST_MAX_CHANNEL_NBR   8U
     
    #define USB_OTG_FS_MAX_IN_ENDPOINTS   4U /* Including EP0 */
     
    #define USB_OTG_FS_MAX_OUT_ENDPOINTS   4U /* Including EP0 */
     
    #define USB_OTG_FS_TOTAL_FIFO_SIZE   1280U /* in Bytes */
     
    #define RCC_PLLCFGR_RST_VALUE   0x24003010U
     
    #define RCC_PLLI2SCFGR_RST_VALUE   0x20003000U
     
    #define RCC_MAX_FREQUENCY   168000000U
     
    #define RCC_MAX_FREQUENCY_SCALE1   RCC_MAX_FREQUENCY
     
    #define RCC_MAX_FREQUENCY_SCALE2   144000000U
     
    #define RCC_PLLVCO_OUTPUT_MIN   100000000U
     
    #define RCC_PLLVCO_INPUT_MIN   950000U
     
    #define RCC_PLLVCO_INPUT_MAX   2100000U
     
    #define RCC_PLLVCO_OUTPUT_MAX   432000000U
     
    #define RCC_PLLN_MIN_VALUE   50U
     
    #define RCC_PLLN_MAX_VALUE   432U
     
    #define FLASH_SCALE1_LATENCY1_FREQ   30000000U
     
    #define FLASH_SCALE1_LATENCY2_FREQ   60000000U
     
    #define FLASH_SCALE1_LATENCY3_FREQ   90000000U
     
    #define FLASH_SCALE1_LATENCY4_FREQ   120000000U
     
    #define FLASH_SCALE1_LATENCY5_FREQ   150000000U
     
    #define FLASH_SCALE2_LATENCY1_FREQ   30000000U
     
    #define FLASH_SCALE2_LATENCY2_FREQ   60000000U
     
    #define FLASH_SCALE2_LATENCY3_FREQ   90000000U
     
    #define FLASH_SCALE2_LATENCY4_FREQ   12000000U
     
    #define USB_OTG_HS_HOST_MAX_CHANNEL_NBR   12U
     
    #define USB_OTG_HS_MAX_IN_ENDPOINTS   6U /* Including EP0 */
     
    #define USB_OTG_HS_MAX_OUT_ENDPOINTS   6U /* Including EP0 */
     
    #define USB_OTG_HS_TOTAL_FIFO_SIZE   4096U /* in Bytes */
     
    #define FMC_IRQn   FSMC_IRQn
     
    #define FMC_IRQHandler   FSMC_IRQHandler
     
    -

    Detailed Description

    -

    Macro Definition Documentation

    - -

    ◆ IS_ADC_ALL_INSTANCE

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    #define IS_ADC_ALL_INSTANCE( INSTANCE)
    -
    -Value:
    (((INSTANCE) == ADC1) || \
    -
    ((INSTANCE) == ADC2) || \
    -
    ((INSTANCE) == ADC3))
    -
    ADC1
    #define ADC1
    Definition stm32f407xx_matlab.h:1161
    -
    ADC2
    #define ADC2
    Definition stm32f407xx_matlab.h:1162
    -
    ADC3
    #define ADC3
    Definition stm32f407xx_matlab.h:1163
    -
    -
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    ◆ IS_ADC_MULTIMODE_MASTER_INSTANCE

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    #define IS_ADC_MULTIMODE_MASTER_INSTANCE( INSTANCE)   ((INSTANCE) == ADC1)
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    ◆ IS_ADC_COMMON_INSTANCE

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    #define IS_ADC_COMMON_INSTANCE( INSTANCE)   ((INSTANCE) == ADC123_COMMON)
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    ◆ IS_CAN_ALL_INSTANCE

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    #define IS_CAN_ALL_INSTANCE( INSTANCE)
    -
    -Value:
    (((INSTANCE) == CAN1) || \
    -
    ((INSTANCE) == CAN2))
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    CAN1
    #define CAN1
    Definition stm32f407xx_matlab.h:1152
    -
    CAN2
    #define CAN2
    Definition stm32f407xx_matlab.h:1153
    -
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    ◆ IS_CRC_ALL_INSTANCE

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    #define IS_CRC_ALL_INSTANCE( INSTANCE)   ((INSTANCE) == CRC)
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    ◆ IS_DAC_ALL_INSTANCE

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    #define IS_DAC_ALL_INSTANCE( INSTANCE)   ((INSTANCE) == DAC1)
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    ◆ IS_DCMI_ALL_INSTANCE

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    #define IS_DCMI_ALL_INSTANCE( INSTANCE)   ((INSTANCE) == DCMI)
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    ◆ IS_DMA_STREAM_ALL_INSTANCE

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    #define IS_DMA_STREAM_ALL_INSTANCE( INSTANCE)
    -
    -Value:
    (((INSTANCE) == DMA1_Stream0) || \
    -
    ((INSTANCE) == DMA1_Stream1) || \
    -
    ((INSTANCE) == DMA1_Stream2) || \
    -
    ((INSTANCE) == DMA1_Stream3) || \
    -
    ((INSTANCE) == DMA1_Stream4) || \
    -
    ((INSTANCE) == DMA1_Stream5) || \
    -
    ((INSTANCE) == DMA1_Stream6) || \
    -
    ((INSTANCE) == DMA1_Stream7) || \
    -
    ((INSTANCE) == DMA2_Stream0) || \
    -
    ((INSTANCE) == DMA2_Stream1) || \
    -
    ((INSTANCE) == DMA2_Stream2) || \
    -
    ((INSTANCE) == DMA2_Stream3) || \
    -
    ((INSTANCE) == DMA2_Stream4) || \
    -
    ((INSTANCE) == DMA2_Stream5) || \
    -
    ((INSTANCE) == DMA2_Stream6) || \
    -
    ((INSTANCE) == DMA2_Stream7))
    -
    DMA2_Stream6
    #define DMA2_Stream6
    Definition stm32f407xx_matlab.h:1202
    -
    DMA2_Stream0
    #define DMA2_Stream0
    Definition stm32f407xx_matlab.h:1196
    -
    DMA1_Stream0
    #define DMA1_Stream0
    Definition stm32f407xx_matlab.h:1187
    -
    DMA2_Stream2
    #define DMA2_Stream2
    Definition stm32f407xx_matlab.h:1198
    -
    DMA1_Stream4
    #define DMA1_Stream4
    Definition stm32f407xx_matlab.h:1191
    -
    DMA1_Stream7
    #define DMA1_Stream7
    Definition stm32f407xx_matlab.h:1194
    -
    DMA1_Stream3
    #define DMA1_Stream3
    Definition stm32f407xx_matlab.h:1190
    -
    DMA2_Stream3
    #define DMA2_Stream3
    Definition stm32f407xx_matlab.h:1199
    -
    DMA1_Stream5
    #define DMA1_Stream5
    Definition stm32f407xx_matlab.h:1192
    -
    DMA2_Stream5
    #define DMA2_Stream5
    Definition stm32f407xx_matlab.h:1201
    -
    DMA1_Stream6
    #define DMA1_Stream6
    Definition stm32f407xx_matlab.h:1193
    -
    DMA2_Stream7
    #define DMA2_Stream7
    Definition stm32f407xx_matlab.h:1203
    -
    DMA1_Stream2
    #define DMA1_Stream2
    Definition stm32f407xx_matlab.h:1189
    -
    DMA2_Stream4
    #define DMA2_Stream4
    Definition stm32f407xx_matlab.h:1200
    -
    DMA2_Stream1
    #define DMA2_Stream1
    Definition stm32f407xx_matlab.h:1197
    -
    DMA1_Stream1
    #define DMA1_Stream1
    Definition stm32f407xx_matlab.h:1188
    -
    -
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    ◆ IS_GPIO_ALL_INSTANCE

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    #define IS_GPIO_ALL_INSTANCE( INSTANCE)
    -
    -Value:
    (((INSTANCE) == GPIOA) || \
    -
    ((INSTANCE) == GPIOB) || \
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    ((INSTANCE) == GPIOC) || \
    -
    ((INSTANCE) == GPIOD) || \
    -
    ((INSTANCE) == GPIOE) || \
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    ((INSTANCE) == GPIOF) || \
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    ((INSTANCE) == GPIOG) || \
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    ((INSTANCE) == GPIOH) || \
    -
    ((INSTANCE) == GPIOI))
    -
    GPIOG
    #define GPIOG
    Definition stm32f407xx_matlab.h:1180
    -
    GPIOC
    #define GPIOC
    Definition stm32f407xx_matlab.h:1176
    -
    GPIOF
    #define GPIOF
    Definition stm32f407xx_matlab.h:1179
    -
    GPIOB
    #define GPIOB
    Definition stm32f407xx_matlab.h:1175
    -
    GPIOD
    #define GPIOD
    Definition stm32f407xx_matlab.h:1177
    -
    GPIOA
    #define GPIOA
    Definition stm32f407xx_matlab.h:1174
    -
    GPIOI
    #define GPIOI
    Definition stm32f407xx_matlab.h:1182
    -
    GPIOH
    #define GPIOH
    Definition stm32f407xx_matlab.h:1181
    -
    GPIOE
    #define GPIOE
    Definition stm32f407xx_matlab.h:1178
    -
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    ◆ IS_I2C_ALL_INSTANCE

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    #define IS_I2C_ALL_INSTANCE( INSTANCE)
    -
    -Value:
    (((INSTANCE) == I2C1) || \
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    ((INSTANCE) == I2C2) || \
    -
    ((INSTANCE) == I2C3))
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    I2C3
    #define I2C3
    Definition stm32f407xx_matlab.h:1151
    -
    I2C1
    #define I2C1
    Definition stm32f407xx_matlab.h:1149
    -
    I2C2
    #define I2C2
    Definition stm32f407xx_matlab.h:1150
    -
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    ◆ IS_SMBUS_ALL_INSTANCE

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    #define IS_SMBUS_ALL_INSTANCE   IS_I2C_ALL_INSTANCE
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    ◆ IS_I2S_ALL_INSTANCE

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    #define IS_I2S_ALL_INSTANCE( INSTANCE)
    -
    -Value:
    (((INSTANCE) == SPI2) || \
    -
    ((INSTANCE) == SPI3))
    -
    SPI3
    #define SPI3
    Definition stm32f407xx_matlab.h:1143
    -
    SPI2
    #define SPI2
    Definition stm32f407xx_matlab.h:1142
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    ◆ IS_I2S_EXT_ALL_INSTANCE

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    #define IS_I2S_EXT_ALL_INSTANCE( INSTANCE)
    -
    -Value:
    (((INSTANCE) == I2S2ext)|| \
    -
    ((INSTANCE) == I2S3ext))
    -
    I2S3ext
    #define I2S3ext
    Definition stm32f407xx_matlab.h:1144
    -
    I2S2ext
    #define I2S2ext
    Definition stm32f407xx_matlab.h:1141
    -
    -
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    ◆ IS_I2S_ALL_INSTANCE_EXT

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    #define IS_I2S_ALL_INSTANCE_EXT   IS_I2S_EXT_ALL_INSTANCE
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    ◆ IS_RNG_ALL_INSTANCE

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    #define IS_RNG_ALL_INSTANCE( INSTANCE)   ((INSTANCE) == RNG)
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    ◆ IS_RTC_ALL_INSTANCE

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    #define IS_RTC_ALL_INSTANCE( INSTANCE)   ((INSTANCE) == RTC)
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    ◆ IS_SPI_ALL_INSTANCE

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    #define IS_SPI_ALL_INSTANCE( INSTANCE)
    -
    -Value:
    (((INSTANCE) == SPI1) || \
    -
    ((INSTANCE) == SPI2) || \
    -
    ((INSTANCE) == SPI3))
    -
    SPI1
    #define SPI1
    Definition stm32f407xx_matlab.h:1168
    -
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    ◆ IS_TIM_INSTANCE

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    #define IS_TIM_INSTANCE( INSTANCE)
    -
    -Value:
    (((INSTANCE) == TIM1) || \
    -
    ((INSTANCE) == TIM2) || \
    -
    ((INSTANCE) == TIM3) || \
    -
    ((INSTANCE) == TIM4) || \
    -
    ((INSTANCE) == TIM5) || \
    -
    ((INSTANCE) == TIM6) || \
    -
    ((INSTANCE) == TIM7) || \
    -
    ((INSTANCE) == TIM8) || \
    -
    ((INSTANCE) == TIM9) || \
    -
    ((INSTANCE) == TIM10)|| \
    -
    ((INSTANCE) == TIM11)|| \
    -
    ((INSTANCE) == TIM12)|| \
    -
    ((INSTANCE) == TIM13)|| \
    -
    ((INSTANCE) == TIM14))
    -
    TIM12
    #define TIM12
    Definition stm32f407xx_matlab.h:1135
    -
    TIM14
    #define TIM14
    Definition stm32f407xx_matlab.h:1137
    -
    TIM1
    #define TIM1
    Definition stm32f407xx_matlab.h:1157
    -
    TIM2
    #define TIM2
    Definition stm32f407xx_matlab.h:1129
    -
    TIM10
    #define TIM10
    Definition stm32f407xx_matlab.h:1172
    -
    TIM7
    #define TIM7
    Definition stm32f407xx_matlab.h:1134
    -
    TIM5
    #define TIM5
    Definition stm32f407xx_matlab.h:1132
    -
    TIM13
    #define TIM13
    Definition stm32f407xx_matlab.h:1136
    -
    TIM3
    #define TIM3
    Definition stm32f407xx_matlab.h:1130
    -
    TIM4
    #define TIM4
    Definition stm32f407xx_matlab.h:1131
    -
    TIM8
    #define TIM8
    Definition stm32f407xx_matlab.h:1158
    -
    TIM6
    #define TIM6
    Definition stm32f407xx_matlab.h:1133
    -
    TIM11
    #define TIM11
    Definition stm32f407xx_matlab.h:1173
    -
    TIM9
    #define TIM9
    Definition stm32f407xx_matlab.h:1171
    -
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    ◆ IS_TIM_CC1_INSTANCE

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    #define IS_TIM_CC1_INSTANCE( INSTANCE)
    -
    -Value:
    (((INSTANCE) == TIM1) || \
    -
    ((INSTANCE) == TIM2) || \
    -
    ((INSTANCE) == TIM3) || \
    -
    ((INSTANCE) == TIM4) || \
    -
    ((INSTANCE) == TIM5) || \
    -
    ((INSTANCE) == TIM8) || \
    -
    ((INSTANCE) == TIM9) || \
    -
    ((INSTANCE) == TIM10) || \
    -
    ((INSTANCE) == TIM11) || \
    -
    ((INSTANCE) == TIM12) || \
    -
    ((INSTANCE) == TIM13) || \
    -
    ((INSTANCE) == TIM14))
    -
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    ◆ IS_TIM_CC2_INSTANCE

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    #define IS_TIM_CC2_INSTANCE( INSTANCE)
    -
    -Value:
    (((INSTANCE) == TIM1) || \
    -
    ((INSTANCE) == TIM2) || \
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    ((INSTANCE) == TIM3) || \
    -
    ((INSTANCE) == TIM4) || \
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    ((INSTANCE) == TIM5) || \
    -
    ((INSTANCE) == TIM8) || \
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    ((INSTANCE) == TIM9) || \
    -
    ((INSTANCE) == TIM12))
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    ◆ IS_TIM_CC3_INSTANCE

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    #define IS_TIM_CC3_INSTANCE( INSTANCE)
    -
    -Value:
    (((INSTANCE) == TIM1) || \
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    ((INSTANCE) == TIM2) || \
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    ((INSTANCE) == TIM3) || \
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    ((INSTANCE) == TIM4) || \
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    ((INSTANCE) == TIM5) || \
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    ((INSTANCE) == TIM8))
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    ◆ IS_TIM_CC4_INSTANCE

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    #define IS_TIM_CC4_INSTANCE( INSTANCE)
    -
    -Value:
    (((INSTANCE) == TIM1) || \
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    ((INSTANCE) == TIM2) || \
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    ((INSTANCE) == TIM3) || \
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    ((INSTANCE) == TIM4) || \
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    ((INSTANCE) == TIM5) || \
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    ((INSTANCE) == TIM8))
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    ◆ IS_TIM_ADVANCED_INSTANCE

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    #define IS_TIM_ADVANCED_INSTANCE( INSTANCE)
    -
    -Value:
    (((INSTANCE) == TIM1) || \
    -
    ((INSTANCE) == TIM8))
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    ◆ IS_TIM_XOR_INSTANCE

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    #define IS_TIM_XOR_INSTANCE( INSTANCE)
    -
    -Value:
    (((INSTANCE) == TIM1) || \
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    ((INSTANCE) == TIM2) || \
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    ((INSTANCE) == TIM3) || \
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    ((INSTANCE) == TIM4) || \
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    ((INSTANCE) == TIM5) || \
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    ((INSTANCE) == TIM8))
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    ◆ IS_TIM_DMA_INSTANCE

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    #define IS_TIM_DMA_INSTANCE( INSTANCE)
    -
    -Value:
    (((INSTANCE) == TIM1) || \
    -
    ((INSTANCE) == TIM2) || \
    -
    ((INSTANCE) == TIM3) || \
    -
    ((INSTANCE) == TIM4) || \
    -
    ((INSTANCE) == TIM5) || \
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    ((INSTANCE) == TIM6) || \
    -
    ((INSTANCE) == TIM7) || \
    -
    ((INSTANCE) == TIM8))
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    ◆ IS_TIM_DMA_CC_INSTANCE

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    #define IS_TIM_DMA_CC_INSTANCE( INSTANCE)
    -
    -Value:
    (((INSTANCE) == TIM1) || \
    -
    ((INSTANCE) == TIM2) || \
    -
    ((INSTANCE) == TIM3) || \
    -
    ((INSTANCE) == TIM4) || \
    -
    ((INSTANCE) == TIM5) || \
    -
    ((INSTANCE) == TIM8))
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    ◆ IS_TIM_CCDMA_INSTANCE

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    #define IS_TIM_CCDMA_INSTANCE( INSTANCE)
    -
    -Value:
    (((INSTANCE) == TIM1) || \
    -
    ((INSTANCE) == TIM2) || \
    -
    ((INSTANCE) == TIM3) || \
    -
    ((INSTANCE) == TIM4) || \
    -
    ((INSTANCE) == TIM5) || \
    -
    ((INSTANCE) == TIM8))
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    ◆ IS_TIM_DMABURST_INSTANCE

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    #define IS_TIM_DMABURST_INSTANCE( INSTANCE)
    -
    -Value:
    (((INSTANCE) == TIM1) || \
    -
    ((INSTANCE) == TIM2) || \
    -
    ((INSTANCE) == TIM3) || \
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    ((INSTANCE) == TIM4) || \
    -
    ((INSTANCE) == TIM5) || \
    -
    ((INSTANCE) == TIM8))
    -
    -
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    ◆ IS_TIM_MASTER_INSTANCE

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    #define IS_TIM_MASTER_INSTANCE( INSTANCE)
    -
    -Value:
    (((INSTANCE) == TIM1) || \
    -
    ((INSTANCE) == TIM2) || \
    -
    ((INSTANCE) == TIM3) || \
    -
    ((INSTANCE) == TIM4) || \
    -
    ((INSTANCE) == TIM5) || \
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    ((INSTANCE) == TIM6) || \
    -
    ((INSTANCE) == TIM7) || \
    -
    ((INSTANCE) == TIM8))
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    ◆ IS_TIM_SLAVE_INSTANCE

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    #define IS_TIM_SLAVE_INSTANCE( INSTANCE)
    -
    -Value:
    (((INSTANCE) == TIM1) || \
    -
    ((INSTANCE) == TIM2) || \
    -
    ((INSTANCE) == TIM3) || \
    -
    ((INSTANCE) == TIM4) || \
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    ((INSTANCE) == TIM5) || \
    -
    ((INSTANCE) == TIM8) || \
    -
    ((INSTANCE) == TIM9) || \
    -
    ((INSTANCE) == TIM12))
    -
    -
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    ◆ IS_TIM_32B_COUNTER_INSTANCE

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    #define IS_TIM_32B_COUNTER_INSTANCE( INSTANCE)
    -
    -Value:
    (((INSTANCE) == TIM2) || \
    -
    ((INSTANCE) == TIM5))
    -
    -
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    ◆ IS_TIM_ETR_INSTANCE

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    #define IS_TIM_ETR_INSTANCE( INSTANCE)
    -
    -Value:
    (((INSTANCE) == TIM1) || \
    -
    ((INSTANCE) == TIM2) || \
    -
    ((INSTANCE) == TIM3) || \
    -
    ((INSTANCE) == TIM4) || \
    -
    ((INSTANCE) == TIM5) || \
    -
    ((INSTANCE) == TIM8))
    -
    -
    -
    - -

    ◆ IS_TIM_REMAP_INSTANCE

    - -
    -
    - - - - - - - -
    #define IS_TIM_REMAP_INSTANCE( INSTANCE)
    -
    -Value:
    (((INSTANCE) == TIM2) || \
    -
    ((INSTANCE) == TIM5) || \
    -
    ((INSTANCE) == TIM11))
    -
    -
    -
    - -

    ◆ IS_TIM_CCX_INSTANCE

    - -
    -
    - - - - - - - - - - - -
    #define IS_TIM_CCX_INSTANCE( INSTANCE,
    CHANNEL )
    -
    - -
    -
    - -

    ◆ IS_TIM_CCXN_INSTANCE

    - -
    -
    - - - - - - - - - - - -
    #define IS_TIM_CCXN_INSTANCE( INSTANCE,
    CHANNEL )
    -
    -Value:
    ((((INSTANCE) == TIM1) && \
    -
    (((CHANNEL) == TIM_CHANNEL_1) || \
    -
    ((CHANNEL) == TIM_CHANNEL_2) || \
    -
    ((CHANNEL) == TIM_CHANNEL_3))) \
    -
    || \
    -
    (((INSTANCE) == TIM8) && \
    -
    (((CHANNEL) == TIM_CHANNEL_1) || \
    -
    ((CHANNEL) == TIM_CHANNEL_2) || \
    -
    ((CHANNEL) == TIM_CHANNEL_3))))
    -
    -
    -
    - -

    ◆ IS_TIM_COUNTER_MODE_SELECT_INSTANCE

    - -
    -
    - - - - - - - -
    #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE( INSTANCE)
    -
    -Value:
    (((INSTANCE) == TIM1) || \
    -
    ((INSTANCE) == TIM2) || \
    -
    ((INSTANCE) == TIM3) || \
    -
    ((INSTANCE) == TIM4) || \
    -
    ((INSTANCE) == TIM5) || \
    -
    ((INSTANCE) == TIM8))
    -
    -
    -
    - -

    ◆ IS_TIM_CLOCK_DIVISION_INSTANCE

    - -
    -
    - - - - - - - -
    #define IS_TIM_CLOCK_DIVISION_INSTANCE( INSTANCE)
    -
    -Value:
    (((INSTANCE) == TIM1) || \
    -
    ((INSTANCE) == TIM2) || \
    -
    ((INSTANCE) == TIM3) || \
    -
    ((INSTANCE) == TIM4) || \
    -
    ((INSTANCE) == TIM5) || \
    -
    ((INSTANCE) == TIM8) || \
    -
    ((INSTANCE) == TIM9) || \
    -
    ((INSTANCE) == TIM10)|| \
    -
    ((INSTANCE) == TIM11)|| \
    -
    ((INSTANCE) == TIM12)|| \
    -
    ((INSTANCE) == TIM13)|| \
    -
    ((INSTANCE) == TIM14))
    -
    -
    -
    - -

    ◆ IS_TIM_COMMUTATION_EVENT_INSTANCE

    - -
    -
    - - - - - - - -
    #define IS_TIM_COMMUTATION_EVENT_INSTANCE( INSTANCE)
    -
    -Value:
    (((INSTANCE) == TIM1)|| \
    -
    ((INSTANCE) == TIM8))
    -
    -
    -
    - -

    ◆ IS_TIM_OCXREF_CLEAR_INSTANCE

    - -
    -
    - - - - - - - -
    #define IS_TIM_OCXREF_CLEAR_INSTANCE( INSTANCE)
    -
    -Value:
    (((INSTANCE) == TIM1) || \
    -
    ((INSTANCE) == TIM2) || \
    -
    ((INSTANCE) == TIM3) || \
    -
    ((INSTANCE) == TIM4) || \
    -
    ((INSTANCE) == TIM5) || \
    -
    ((INSTANCE) == TIM8))
    -
    -
    -
    - -

    ◆ IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE

    - -
    -
    - - - - - - - -
    #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE( INSTANCE)
    -
    -Value:
    (((INSTANCE) == TIM1) || \
    -
    ((INSTANCE) == TIM2) || \
    -
    ((INSTANCE) == TIM3) || \
    -
    ((INSTANCE) == TIM4) || \
    -
    ((INSTANCE) == TIM5) || \
    -
    ((INSTANCE) == TIM8) || \
    -
    ((INSTANCE) == TIM9) || \
    -
    ((INSTANCE) == TIM12))
    -
    -
    -
    - -

    ◆ IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE

    - -
    -
    - - - - - - - -
    #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE( INSTANCE)
    -
    -Value:
    (((INSTANCE) == TIM1) || \
    -
    ((INSTANCE) == TIM2) || \
    -
    ((INSTANCE) == TIM3) || \
    -
    ((INSTANCE) == TIM4) || \
    -
    ((INSTANCE) == TIM5) || \
    -
    ((INSTANCE) == TIM8))
    -
    -
    -
    - -

    ◆ IS_TIM_CLOCKSOURCE_TIX_INSTANCE

    - -
    -
    - - - - - - - -
    #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE( INSTANCE)
    -
    -Value:
    (((INSTANCE) == TIM1) || \
    -
    ((INSTANCE) == TIM2) || \
    -
    ((INSTANCE) == TIM3) || \
    -
    ((INSTANCE) == TIM4) || \
    -
    ((INSTANCE) == TIM5) || \
    -
    ((INSTANCE) == TIM8) || \
    -
    ((INSTANCE) == TIM9) || \
    -
    ((INSTANCE) == TIM12))
    -
    -
    -
    - -

    ◆ IS_TIM_CLOCKSOURCE_ITRX_INSTANCE

    - -
    -
    - - - - - - - -
    #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE( INSTANCE)
    -
    -Value:
    (((INSTANCE) == TIM1) || \
    -
    ((INSTANCE) == TIM2) || \
    -
    ((INSTANCE) == TIM3) || \
    -
    ((INSTANCE) == TIM4) || \
    -
    ((INSTANCE) == TIM5) || \
    -
    ((INSTANCE) == TIM8) || \
    -
    ((INSTANCE) == TIM9) || \
    -
    ((INSTANCE) == TIM12))
    -
    -
    -
    - -

    ◆ IS_TIM_REPETITION_COUNTER_INSTANCE

    - -
    -
    - - - - - - - -
    #define IS_TIM_REPETITION_COUNTER_INSTANCE( INSTANCE)
    -
    -Value:
    (((INSTANCE) == TIM1) || \
    -
    ((INSTANCE) == TIM8))
    -
    -
    -
    - -

    ◆ IS_TIM_ENCODER_INTERFACE_INSTANCE

    - -
    -
    - - - - - - - -
    #define IS_TIM_ENCODER_INTERFACE_INSTANCE( INSTANCE)
    -
    -Value:
    (((INSTANCE) == TIM1) || \
    -
    ((INSTANCE) == TIM2) || \
    -
    ((INSTANCE) == TIM3) || \
    -
    ((INSTANCE) == TIM4) || \
    -
    ((INSTANCE) == TIM5) || \
    -
    ((INSTANCE) == TIM8) || \
    -
    ((INSTANCE) == TIM9) || \
    -
    ((INSTANCE) == TIM12))
    -
    -
    -
    - -

    ◆ IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE

    - -
    -
    - - - - - - - -
    #define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE( INSTANCE)
    -
    -Value:
    (((INSTANCE) == TIM1) || \
    -
    ((INSTANCE) == TIM2) || \
    -
    ((INSTANCE) == TIM3) || \
    -
    ((INSTANCE) == TIM4) || \
    -
    ((INSTANCE) == TIM5) || \
    -
    ((INSTANCE) == TIM8))
    -
    -
    -
    - -

    ◆ IS_TIM_BREAK_INSTANCE

    - -
    -
    - - - - - - - -
    #define IS_TIM_BREAK_INSTANCE( INSTANCE)
    -
    -Value:
    (((INSTANCE) == TIM1) || \
    -
    ((INSTANCE) == TIM8))
    -
    -
    -
    - -

    ◆ IS_USART_INSTANCE

    - -
    -
    - - - - - - - -
    #define IS_USART_INSTANCE( INSTANCE)
    -
    -Value:
    (((INSTANCE) == USART1) || \
    -
    ((INSTANCE) == USART2) || \
    -
    ((INSTANCE) == USART3) || \
    -
    ((INSTANCE) == USART6))
    -
    USART3
    #define USART3
    Definition stm32f407xx_matlab.h:1146
    -
    USART6
    #define USART6
    Definition stm32f407xx_matlab.h:1160
    -
    USART1
    #define USART1
    Definition stm32f407xx_matlab.h:1159
    -
    USART2
    #define USART2
    Definition stm32f407xx_matlab.h:1145
    -
    -
    -
    - -

    ◆ IS_UART_HALFDUPLEX_INSTANCE

    - -
    -
    - - - - - - - -
    #define IS_UART_HALFDUPLEX_INSTANCE( INSTANCE)
    -
    -Value:
    (((INSTANCE) == USART1) || \
    -
    ((INSTANCE) == USART2) || \
    -
    ((INSTANCE) == USART3) || \
    -
    ((INSTANCE) == UART4) || \
    -
    ((INSTANCE) == UART5) || \
    -
    ((INSTANCE) == USART6))
    -
    UART4
    #define UART4
    Definition stm32f407xx_matlab.h:1147
    -
    UART5
    #define UART5
    Definition stm32f407xx_matlab.h:1148
    -
    -
    -
    - -

    ◆ IS_UART_INSTANCE

    - -
    -
    - - - - -
    #define IS_UART_INSTANCE   IS_UART_HALFDUPLEX_INSTANCE
    -
    - -
    -
    - -

    ◆ IS_UART_HWFLOW_INSTANCE

    - -
    -
    - - - - - - - -
    #define IS_UART_HWFLOW_INSTANCE( INSTANCE)
    -
    -Value:
    (((INSTANCE) == USART1) || \
    -
    ((INSTANCE) == USART2) || \
    -
    ((INSTANCE) == USART3) || \
    -
    ((INSTANCE) == USART6))
    -
    -
    -
    - -

    ◆ IS_UART_LIN_INSTANCE

    - -
    -
    - - - - -
    #define IS_UART_LIN_INSTANCE   IS_UART_HALFDUPLEX_INSTANCE
    -
    - -
    -
    - -

    ◆ IS_SMARTCARD_INSTANCE

    - -
    -
    - - - - - - - -
    #define IS_SMARTCARD_INSTANCE( INSTANCE)
    -
    -Value:
    (((INSTANCE) == USART1) || \
    -
    ((INSTANCE) == USART2) || \
    -
    ((INSTANCE) == USART3) || \
    -
    ((INSTANCE) == USART6))
    -
    -
    -
    - -

    ◆ IS_IRDA_INSTANCE

    - -
    -
    - - - - - - - -
    #define IS_IRDA_INSTANCE( INSTANCE)
    -
    -Value:
    (((INSTANCE) == USART1) || \
    -
    ((INSTANCE) == USART2) || \
    -
    ((INSTANCE) == USART3) || \
    -
    ((INSTANCE) == UART4) || \
    -
    ((INSTANCE) == UART5) || \
    -
    ((INSTANCE) == USART6))
    -
    -
    -
    - -

    ◆ IS_PCD_ALL_INSTANCE

    - -
    -
    - - - - - - - -
    #define IS_PCD_ALL_INSTANCE( INSTANCE)
    -
    -Value:
    (((INSTANCE) == USB_OTG_FS) || \
    -
    ((INSTANCE) == USB_OTG_HS))
    -
    USB_OTG_HS
    #define USB_OTG_HS
    Definition stm32f407xx_matlab.h:1213
    -
    USB_OTG_FS
    #define USB_OTG_FS
    Definition stm32f407xx_matlab.h:1212
    -
    -
    -
    - -

    ◆ IS_HCD_ALL_INSTANCE

    - -
    -
    - - - - - - - -
    #define IS_HCD_ALL_INSTANCE( INSTANCE)
    -
    -Value:
    (((INSTANCE) == USB_OTG_FS) || \
    -
    ((INSTANCE) == USB_OTG_HS))
    -
    -
    -
    - -

    ◆ IS_SDIO_ALL_INSTANCE

    - -
    -
    - - - - - - - -
    #define IS_SDIO_ALL_INSTANCE( INSTANCE)   ((INSTANCE) == SDIO)
    -
    - -
    -
    - -

    ◆ IS_IWDG_ALL_INSTANCE

    - -
    -
    - - - - - - - -
    #define IS_IWDG_ALL_INSTANCE( INSTANCE)   ((INSTANCE) == IWDG)
    -
    - -
    -
    - -

    ◆ IS_WWDG_ALL_INSTANCE

    - -
    -
    - - - - - - - -
    #define IS_WWDG_ALL_INSTANCE( INSTANCE)   ((INSTANCE) == WWDG)
    -
    - -
    -
    - -

    ◆ USB_OTG_FS_HOST_MAX_CHANNEL_NBR

    - -
    -
    - - - - -
    #define USB_OTG_FS_HOST_MAX_CHANNEL_NBR   8U
    -
    - -
    -
    - -

    ◆ USB_OTG_FS_MAX_IN_ENDPOINTS

    - -
    -
    - - - - -
    #define USB_OTG_FS_MAX_IN_ENDPOINTS   4U /* Including EP0 */
    -
    - -
    -
    - -

    ◆ USB_OTG_FS_MAX_OUT_ENDPOINTS

    - -
    -
    - - - - -
    #define USB_OTG_FS_MAX_OUT_ENDPOINTS   4U /* Including EP0 */
    -
    - -
    -
    - -

    ◆ USB_OTG_FS_TOTAL_FIFO_SIZE

    - -
    -
    - - - - -
    #define USB_OTG_FS_TOTAL_FIFO_SIZE   1280U /* in Bytes */
    -
    - -
    -
    - -

    ◆ RCC_PLLCFGR_RST_VALUE

    - -
    -
    - - - - -
    #define RCC_PLLCFGR_RST_VALUE   0x24003010U
    -
    - -
    -
    - -

    ◆ RCC_PLLI2SCFGR_RST_VALUE

    - -
    -
    - - - - -
    #define RCC_PLLI2SCFGR_RST_VALUE   0x20003000U
    -
    - -
    -
    - -

    ◆ RCC_MAX_FREQUENCY

    - -
    -
    - - - - -
    #define RCC_MAX_FREQUENCY   168000000U
    -
    -

    Max frequency of family in Hz

    - -
    -
    - -

    ◆ RCC_MAX_FREQUENCY_SCALE1

    - -
    -
    - - - - -
    #define RCC_MAX_FREQUENCY_SCALE1   RCC_MAX_FREQUENCY
    -
    -

    Maximum frequency for system clock at power scale1, in Hz

    - -
    -
    - -

    ◆ RCC_MAX_FREQUENCY_SCALE2

    - -
    -
    - - - - -
    #define RCC_MAX_FREQUENCY_SCALE2   144000000U
    -
    -

    Maximum frequency for system clock at power scale2, in Hz

    - -
    -
    - -

    ◆ RCC_PLLVCO_OUTPUT_MIN

    - -
    -
    - - - - -
    #define RCC_PLLVCO_OUTPUT_MIN   100000000U
    -
    -

    Frequency min for PLLVCO output, in Hz

    - -
    -
    - -

    ◆ RCC_PLLVCO_INPUT_MIN

    - -
    -
    - - - - -
    #define RCC_PLLVCO_INPUT_MIN   950000U
    -
    -

    Frequency min for PLLVCO input, in Hz
    -

    - -
    -
    - -

    ◆ RCC_PLLVCO_INPUT_MAX

    - -
    -
    - - - - -
    #define RCC_PLLVCO_INPUT_MAX   2100000U
    -
    -

    Frequency max for PLLVCO input, in Hz
    -

    - -
    -
    - -

    ◆ RCC_PLLVCO_OUTPUT_MAX

    - -
    -
    - - - - -
    #define RCC_PLLVCO_OUTPUT_MAX   432000000U
    -
    -

    Frequency max for PLLVCO output, in Hz

    - -
    -
    - -

    ◆ RCC_PLLN_MIN_VALUE

    - -
    -
    - - - - -
    #define RCC_PLLN_MIN_VALUE   50U
    -
    - -
    -
    - -

    ◆ RCC_PLLN_MAX_VALUE

    - -
    -
    - - - - -
    #define RCC_PLLN_MAX_VALUE   432U
    -
    - -
    -
    - -

    ◆ FLASH_SCALE1_LATENCY1_FREQ

    - -
    -
    - - - - -
    #define FLASH_SCALE1_LATENCY1_FREQ   30000000U
    -
    -

    HCLK frequency to set FLASH latency 1 in power scale 1
    -

    - -
    -
    - -

    ◆ FLASH_SCALE1_LATENCY2_FREQ

    - -
    -
    - - - - -
    #define FLASH_SCALE1_LATENCY2_FREQ   60000000U
    -
    -

    HCLK frequency to set FLASH latency 2 in power scale 1
    -

    - -
    -
    - -

    ◆ FLASH_SCALE1_LATENCY3_FREQ

    - -
    -
    - - - - -
    #define FLASH_SCALE1_LATENCY3_FREQ   90000000U
    -
    -

    HCLK frequency to set FLASH latency 3 in power scale 1
    -

    - -
    -
    - -

    ◆ FLASH_SCALE1_LATENCY4_FREQ

    - -
    -
    - - - - -
    #define FLASH_SCALE1_LATENCY4_FREQ   120000000U
    -
    -

    HCLK frequency to set FLASH latency 4 in power scale 1
    -

    - -
    -
    - -

    ◆ FLASH_SCALE1_LATENCY5_FREQ

    - -
    -
    - - - - -
    #define FLASH_SCALE1_LATENCY5_FREQ   150000000U
    -
    -

    HCLK frequency to set FLASH latency 5 in power scale 1
    -

    - -
    -
    - -

    ◆ FLASH_SCALE2_LATENCY1_FREQ

    - -
    -
    - - - - -
    #define FLASH_SCALE2_LATENCY1_FREQ   30000000U
    -
    -

    HCLK frequency to set FLASH latency 1 in power scale 2
    -

    - -
    -
    - -

    ◆ FLASH_SCALE2_LATENCY2_FREQ

    - -
    -
    - - - - -
    #define FLASH_SCALE2_LATENCY2_FREQ   60000000U
    -
    -

    HCLK frequency to set FLASH latency 2 in power scale 2
    -

    - -
    -
    - -

    ◆ FLASH_SCALE2_LATENCY3_FREQ

    - -
    -
    - - - - -
    #define FLASH_SCALE2_LATENCY3_FREQ   90000000U
    -
    -

    HCLK frequency to set FLASH latency 3 in power scale 2
    -

    - -
    -
    - -

    ◆ FLASH_SCALE2_LATENCY4_FREQ

    - -
    -
    - - - - -
    #define FLASH_SCALE2_LATENCY4_FREQ   12000000U
    -
    -

    HCLK frequency to set FLASH latency 4 in power scale 2
    -

    - -
    -
    - -

    ◆ USB_OTG_HS_HOST_MAX_CHANNEL_NBR

    - -
    -
    - - - - -
    #define USB_OTG_HS_HOST_MAX_CHANNEL_NBR   12U
    -
    - -
    -
    - -

    ◆ USB_OTG_HS_MAX_IN_ENDPOINTS

    - -
    -
    - - - - -
    #define USB_OTG_HS_MAX_IN_ENDPOINTS   6U /* Including EP0 */
    -
    - -
    -
    - -

    ◆ USB_OTG_HS_MAX_OUT_ENDPOINTS

    - -
    -
    - - - - -
    #define USB_OTG_HS_MAX_OUT_ENDPOINTS   6U /* Including EP0 */
    -
    - -
    -
    - -

    ◆ USB_OTG_HS_TOTAL_FIFO_SIZE

    - -
    -
    - - - - -
    #define USB_OTG_HS_TOTAL_FIFO_SIZE   4096U /* in Bytes */
    -
    - -
    -
    - -

    ◆ FMC_IRQn

    - -
    -
    - - - - -
    #define FMC_IRQn   FSMC_IRQn
    -
    - -
    -
    - -

    ◆ FMC_IRQHandler

    - -
    -
    - - - - -
    #define FMC_IRQHandler   FSMC_IRQHandler
    -
    - -
    -
    -
    - -
    -Generated by doxygen 1.10.0 -
    - - diff --git a/DOCS/html/group___exported__macros.map b/DOCS/html/group___exported__macros.map deleted file mode 100644 index 20b6235..0000000 --- a/DOCS/html/group___exported__macros.map +++ /dev/null @@ -1,4 +0,0 @@ - - - - diff --git a/DOCS/html/group___exported__macros.md5 b/DOCS/html/group___exported__macros.md5 deleted file mode 100644 index 615a3b2..0000000 --- a/DOCS/html/group___exported__macros.md5 +++ /dev/null @@ -1 +0,0 @@ -512c30e590009b084939e1342187e05c \ No newline at end of file diff --git a/DOCS/html/group___exported__macros.png b/DOCS/html/group___exported__macros.png deleted file mode 100644 index b7154df0f7a7a14b7cc2fc9ae270c219028bbf78..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 1211 zcmV;s1VsCZP);|DSa7-M-8` zbM`(rJ3D&@h=_=Yh=_=Yh=`~wgt}m7XXmOAVlzcBMDs`~Uk!)DH>u-r(d+fLQ^!E@ zWLb7p6vgZ6vPh>YC<@GNx@E_h5Wm+^SK2jI8rvYBK%RTM?=fQU@x zd7e6i);2aau)e;YIt&Wz@bD0$(P(CQmLL`)qNT%ROGFd_lPwWZ1WdL>L=iCA5)nnf zWJ^R8fp+Sb4IyUkjQ{{hDV@tR+1GTtHe%F4L0v^TKleI-UlPY+Y~ED2MVXeF=lR0K z8iSW)3)Cl8*F?qSMlG!a_!Ynd0GlZ9lzg8wA_rYaR7{xucuTfKiG2g$27resd$6MN zAWAOkn5_`v{Gl$d`>8I|4Oi&anbtRNTT{9?+r;Lpoa#??ed>0#w1P6hJ_YbMfIk7; zLfMH}!3Do2p$;`vUr(Rsd0smtFj{*FktTOpKz6>DQ#ekEO6YG829^kI~`$#O)4*=IX zburk)W?H6gIj(|UAX9lfeKcZIUzcNBBq7_iwYBwPI2;ZE+y!tCz;^)t0kCSY`v(C1 zV8Jz5TU!hAZDqP%ZAhuV6ex84>IX&VlC6o@vkXk@t2^Bd?IO;&2>m_^AtZp8lgA?f zKck#+a1X$@0LIV{BYXz%+-pDkRbTwSM&L#?N7U)yn77iyc-SWMex(+*!f`I)TJ>-DyU5W8KO$jm#q{7UtHwyihM zb4V%g3BZ2%a~st&YKa^nS6Qp-e55J>OVDH=y`~=^xgq@ z0^mmgKP8TZmK^UOGc<2#VG(-Xy3_YXZJ07h=_=Yh=_{j$d>B6oHK+gp002ovPDHLkV1k1rJ*)r# diff --git a/DOCS/html/group___exported__types.html b/DOCS/html/group___exported__types.html deleted file mode 100644 index a78dbdf..0000000 --- a/DOCS/html/group___exported__types.html +++ /dev/null @@ -1,213 +0,0 @@ - - - - - - - -STM MATLAB Simulator: Exported_types - - - - - - - - - - - -
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    -Macros | -Typedefs | -Enumerations
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    Exported_types
    CMSIS » Stm32f4xx
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    - + Collaboration diagram for Exported_types:
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    -Macros

    #define IS_FUNCTIONAL_STATE(STATE)   (((STATE) == DISABLE) || ((STATE) == ENABLE))
     
    - - - -

    -Typedefs

    typedef enum FlagStatus ITStatus
     
    - - - - - - - -

    -Enumerations

    enum  FlagStatus { RESET = 0U -, SET = !RESET - }
     
    enum  FunctionalState { DISABLE = 0U -, ENABLE = !DISABLE - }
     
    enum  ErrorStatus { SUCCESS = 0U -, ERROR = !SUCCESS - }
     
    -

    Detailed Description

    -

    Macro Definition Documentation

    - -

    ◆ IS_FUNCTIONAL_STATE

    - -
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    - - - - - - - -
    #define IS_FUNCTIONAL_STATE( STATE)   (((STATE) == DISABLE) || ((STATE) == ENABLE))
    -
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    Typedef Documentation

    - -

    ◆ ITStatus

    - -
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    typedef enum FlagStatus ITStatus
    -
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    Enumeration Type Documentation

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    ◆ FlagStatus

    - -
    -
    - - - - -
    enum FlagStatus
    -
    - - - -
    Enumerator
    RESET 
    SET 
    - -
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    ◆ FunctionalState

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    - - - - -
    enum FunctionalState
    -
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    Enumerator
    DISABLE 
    ENABLE 
    - -
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    ◆ ErrorStatus

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    - - - - -
    enum ErrorStatus
    -
    - - - -
    Enumerator
    SUCCESS 
    ERROR 
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    - - diff --git a/DOCS/html/group___exported__types.map b/DOCS/html/group___exported__types.map deleted file mode 100644 index 374720e..0000000 --- a/DOCS/html/group___exported__types.map +++ /dev/null @@ -1,4 +0,0 @@ - - - - diff --git a/DOCS/html/group___exported__types.md5 b/DOCS/html/group___exported__types.md5 deleted file mode 100644 index ffa2181..0000000 --- a/DOCS/html/group___exported__types.md5 +++ /dev/null @@ -1 +0,0 @@ -e9c9278bd7f85728c7bdd0ec75c54f19 \ No newline at end of file diff --git a/DOCS/html/group___exported__types.png b/DOCS/html/group___exported__types.png deleted file mode 100644 index 3c9c546490f5021edac67321fbb0610e8844b3fa..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 1106 zcmV-Y1g-mtP)EK5JCtcgb+dqA;dZol>@uGyRSu2v>igsI+JDDqy7E;Uqb8fVQ+8m)6g13 zH{v)xOVjkR8GEL@QxrwpQ51c@I$5*fGvHxp5kBaAm_Ezp@&Ne6jNLGQL7Jw63z`c_ zl7yDfnZ;tk=H_N-8N!3p(^D=kE^fr*09u3)BS7XCVy4LaLd+DIUx=9^^9wOkWPTxL zO69G-wnWj5=Y`0!Y>>9icI(Q_a$CGFeFO3m@G)=?cn|nHtQJ^(%^H~g)za{L&BaaLjADGw68&HO`AH(*R)=62;4 z@GkHb@DcDFuw(SYkqSEHvg7m<#-=6v#rl!+a(*YX|3A!BnIvP-vYk@KaxKJ z{5<(P7i(?&@}+^fU3^cH#Ci!)#H-pc%WV5JwcGX>Y})%guBI|ydYSo)6x`gll{cm6 zX5I4sb?w(_a?K9R{mb?0$~<_J{2A+A;8oxs;P!Rd?W#&sqv|9rQsgvE|4*51sk0fY z`rfqdyRWOksnxD9**yiqE0HT+-w zDst!e_?X3F(W*|@lhe0;AEqcw-KB2Tz|fbzJ{aVhzw08O4}J7iH?w!0^>=o59-W+= zJRo1W{{nc0eD(fW$0qIp|9W-ak*%$*LEc96nK`>M=9jGMvL&-@ROSzT+svi^s&xlj zM$z^TLkoVs{(KF*1$;@qs=vw8>A#I12z0A&V`F2GcI#%yp&0YZe4Vx-(*Dsu&9%?EMZ~@sWWmpjoA}I{ zwzli;BG~$M!PHis;p@tJ;0f^4_2)kDK6y59mwa%Jn7|-irfI>?G>6SBW~y5iFPBy6 zDEDKl+vPgH%}nfbT%%6=q5I-q-F8*mZTsx2{{b_GKgs{w&qLrv;6w6DgF8cYI0P;y zr^`ZERXeWnHf=VQt)fof+M1Z$j4~sB2fhQ|0bVE2VxL%FM*oDL0N~fq0_IBF_Y`a? z{aBIt#poE5aoTEGb?V*)rTs$86q#R$nIiKGF;irIA!dqxv_m*?etvHK;Ri8(uCA`E z@f+rk7G!vFvP diff --git a/DOCS/html/group___g_p_i_o___s_i_m_u_l_a_t_o_r.html b/DOCS/html/group___g_p_i_o___s_i_m_u_l_a_t_o_r.html index fbc47a6..e911bae 100644 --- a/DOCS/html/group___g_p_i_o___s_i_m_u_l_a_t_o_r.html +++ b/DOCS/html/group___g_p_i_o___s_i_m_u_l_a_t_o_r.html @@ -5,7 +5,7 @@ -STM MATLAB Simulator: GPIO_SIMULATOR +STM MATLAB Simulator: GPIO Simulator @@ -14,6 +14,7 @@ + @@ -73,39 +74,39 @@ $(function() {
    Functions
    -
    GPIO_SIMULATOR
    STM_SIMULATION » MAIN_SIMULATOR
    +
    GPIO Simulator
    STM32 Simulation » STM32 Simulator
    -

    Simulator for GPIO. +

    СимулÑтор Ð´Ð»Ñ Ð¿Ð¾Ñ€Ñ‚Ð¾Ð² ввода-вывода More...

    - + Collaboration diagram for GPIO_SIMULATOR:
    + + Collaboration diagram for GPIO Simulator:
    - - - + + + - +

    Functions

    void SFUNC_to_GPIO (real_T *disc)
     Write S-Function inputs to MCU.
     
    void SFUNC_to_GPIO (real_T *out_buff)
     Ð¡Ñ‡Ð¸Ñ‚ывание входов S-Function в МК.
     
    void GPIO_to_SFUNC (real_T *in)
     Write S-Function disc ports from MCU GPIOs.
     Ð—апиÑÑŒ буфера выходов S-Function из GPIO.
     

    Detailed Description

    -

    Simulator for GPIO.

    +

    СимулÑтор Ð´Ð»Ñ Ð¿Ð¾Ñ€Ñ‚Ð¾Ð² ввода-вывода

    ОпределÑет взаимодейÑтвие портов МК и оболочки (S-Function)

    Function Documentation

    - -

    ◆ SFUNC_to_GPIO()

    + +

    ◆ SFUNC_to_GPIO()

    @@ -119,14 +120,17 @@ Functions
    -

    Write S-Function inputs to MCU.

    +

    Считывание входов S-Function в МК.

    Parameters
    - +
    disc- discrete array of S-Function. Outputs would be written from disc.
    out_buff- указатель на буфер выходов S-Function.
    -

    Ð¤ÑƒÐ½ÐºÑ†Ð¸Ñ Ð´Ð»Ñ ÑÑ‡Ð¸Ñ‚Ñ‹Ð²Ð°Ð½Ð¸Ñ Ð²Ñ…Ð¾Ð´Ð¾Ð² S-Function в МК. Можно абÑтрагироватьÑÑ Ð¾Ñ‚ ÑÑ‡Ð¸Ñ‚Ñ‹Ð²Ð°Ð½Ð¸Ñ Ð² GPIO и запиÑывать напрÑмую в переменные МК.

    +

    Ð¤ÑƒÐ½ÐºÑ†Ð¸Ñ Ð´Ð»Ñ ÑÑ‡Ð¸Ñ‚Ñ‹Ð²Ð°Ð½Ð¸Ñ Ð²Ñ…Ð¾Ð´Ð¾Ð² S-Function в МК. Можно абÑтрагироватьÑÑ Ð¾Ñ‚ ÑÑ‡Ð¸Ñ‚Ñ‹Ð²Ð°Ð½Ð¸Ñ Ð² GPIO и запиÑывать напрÑмую в переменные МК.

    +
    Attention
    Тело функции пишетÑÑ Ð¿Ð¾Ð»ÑŒÐ·Ð¾Ð²Ð°Ñ‚ÐµÐ»ÐµÐ¼!
    + +

    Definition at line 49 of file stm32f4xx_matlab_gpio.c.

    @@ -139,20 +143,23 @@ Functions void GPIO_to_SFUNC ( - real_T * disc) + real_T * out_buff)
    -

    Write S-Function disc ports from MCU GPIOs.

    +

    ЗапиÑÑŒ буфера выходов S-Function из GPIO.

    Parameters
    - +
    disc- discrete array of S-Function. Outputs would be written from disc.
    out_buff- указатель на буфер выходов S-Function.
    -

    Ð¤ÑƒÐ½ÐºÑ†Ð¸Ñ Ð´Ð»Ñ Ð·Ð°Ð¿Ð¸Ñи диÑкретных выходов S-Function из GPIO. ПоÑле в SIM_writeOutputs из disc формируютÑÑ Ð²Ñ‹Ñ…Ð¾Ð´Ñ‹ S-Function.

    +

    Ð¤ÑƒÐ½ÐºÑ†Ð¸Ñ Ð´Ð»Ñ Ð·Ð°Ð¿Ð¸Ñи буфера выходов S-Function из GPIO. ПоÑле в SIM_writeOutputs() из out_buff формируютÑÑ Ð²Ñ‹Ñ…Ð¾Ð´Ñ‹ S-Function.

    +
    Attention
    Тело функции пишетÑÑ Ð¿Ð¾Ð»ÑŒÐ·Ð¾Ð²Ð°Ñ‚ÐµÐ»ÐµÐ¼!
    + +

    Definition at line 20 of file stm32f4xx_matlab_gpio.c.

    diff --git a/DOCS/html/group___g_p_i_o___s_i_m_u_l_a_t_o_r.map b/DOCS/html/group___g_p_i_o___s_i_m_u_l_a_t_o_r.map index 1ef0d64..565dfa5 100644 --- a/DOCS/html/group___g_p_i_o___s_i_m_u_l_a_t_o_r.map +++ b/DOCS/html/group___g_p_i_o___s_i_m_u_l_a_t_o_r.map @@ -1,4 +1,4 @@ - - - + + + diff --git a/DOCS/html/group___g_p_i_o___s_i_m_u_l_a_t_o_r.md5 b/DOCS/html/group___g_p_i_o___s_i_m_u_l_a_t_o_r.md5 index f37905e..6c56dcc 100644 --- a/DOCS/html/group___g_p_i_o___s_i_m_u_l_a_t_o_r.md5 +++ b/DOCS/html/group___g_p_i_o___s_i_m_u_l_a_t_o_r.md5 @@ -1 +1 @@ -87e6aadad6d310d5fd1f2120c4380462 \ No newline at end of file +453732ef4d6dd97fee37263657e2b6f8 \ No newline at end of file diff --git a/DOCS/html/group___g_p_i_o___s_i_m_u_l_a_t_o_r.png b/DOCS/html/group___g_p_i_o___s_i_m_u_l_a_t_o_r.png index 1ccd6e6afc048069fb063d14dfce83d794355a36..f5e7197c00a19ac4e3d99444e3de6d91a743f959 100644 GIT binary patch delta 1158 zcmV;11bO?W35p3JiBL{Q4GJ0x0000DNk~Le0003d0000b2nGNE0PiP6z>y&pe?Lh? zK~#90?cKeLBt;m<@o%?pupsEf2Qp@|1_m1)nu?Jxfp_Q~m$)Y~m#+d&w>+EV#kKA|6Z|%rw{bRM&J@S5MW<{XQ@-UDaLn1X~YX)iu2! zA|fIpA|fIp(oIq=*xlW|mL$pbe-OdQ>g9R<+y4IkS?D-ij7Fmyp<|Hl(lk9CkH`1R zWzSYmN|NMyk|cLm7nTHe6Zk1~5H9q0x*4X^=>hOzxojaZ6~^On?*U0zS(b$kp|jy| z$Y3xC9fmkMIXU6t;$opZ4G@cnh?NqPh(t$;NkpQf#3UloQDPF2=qNFXe@Jv{w+pnD zBnx{r$@9Fn&U8-ky{`Sb_R81U>e|NLBrX?yw7Ft00`CDI0iOYn!iLjMb(=(WYfRlX zit>3`mKnFyENi<-JWc!RqK`Ix@{*Y923k?xbfDYXv7J+t+3H;4hUJN^Pmv|C7l3zw zTfn>XV}LJ$MdZLVAWda;e@VwSn47lUq`q7pGJ%9jU~4y(vklaU2Jxmyfj5EgfWLry z!23K&N^7NVkd4RV&YMm9Z2M`{Yhr4fD2ltDvJiI-byLIQdy*sz<)*l8$JIJhn|1Bj z`m^=Z!Zz?Nvt;xO@G0;Tv)@)e=c9wz#5S#|PUWiKvn*REuO`4{f5+82Q=4_|*!uI4 zh`mhZstIKkiNr^LE^(XIx|*(&Eo-lQY?_+3J#OhWX1|-e0}O%3JV`TGurR`%L04 zZ5?u5}!C=totq8V66l!YM z<<6&z*w(>%eJU49(|BTt+cX^u;34qM{IkvM6%?NU*MNV4f9EaN{tW!lcYr2aTU#Nz z^(uzP_NM7rXi+|uvrXfc4cr)#jjND%P9+b3uYp&9w}9_~zvp$21I6S;-4ik&$)V4- zS1E?11U)T&m&<)K^;KPrZo0{`&$#Q_ww<@^spN_uGE9MA=btZuw}Fp=514Hi$bo12 z44@CD1mY`kf4H<=m(YB~)O4#t`8?A#)jd^h7wcUtjGWPEbR$WUyX%zY#Z8uF2!KBxM}O@%J<5p@keFf+EPlf~}Q>5VSD}T8JW;<3wVU&35AdVQsOui=D-3 z8nI0&rV9BBQbk0}!NLW?iRX^R?BL#Hem&1TGtbQ4=LIQlem&oP_U5zm%rm{WUg#QR7@{b;m`&srq zZe)zvF~&UXt}NLA_kbTm7vVzx*QKuIa(M)NzP{{6fTpI?Y3l{a@J%L@&?PiB8jaZA z-VR-c^w|0NIg7>O#_}jYEg~WtK>;cv;z$81BH~B^Dk9=Y0V*QmNC7G$f8wa{F(wvIkN zw&e9q-4M=Om$%Hv2axOWf?}3fM4B^v2kzz#w7`X3V0zL+Q0R99X0Pphu|Gh!IsYNGW8U%ek_9p35KY0t# zypyzpE1Jft>Kp3o3hWk1NIn1_0Y8&`-SfrOx?AB&YfqoQy;oIRe_r_byi(g#-iGit zvP09lfn>97(Z1{d?jzT}>4~>VhUZ@b+rU4-?bW)C49&jD24P(Df6( zk0*ZKq>OEF_wjYPsG3l-aeRFI0q`wwH?!(?&gNM!1Hn4d`*I}`*5UZL!520z_*l>9=pvdm-?(uv+{~ovxd;z?| zvsa&Go&aAtH{Q@_G-~uKQe}bJhXAUYJr5!6r!H<8xI7tPBghcG>sjse_4%arCI(Jcf8PK*B#$WV19yO@6o=_k;3ubsJ=ogX3e|KgfBF=ZWxAg6Puuj}Ki+5I z%TC6!lhkIWIK-@SRme1*Z1T}JMcZ}!;jsjM1-=Ge13n=M$S1(RB!M|tMKirVPRurs zZCgW8drc>sY>#cTU5F2lAXlJ1*oJ7)_CAB9?nG6a;h*<9ySz1$@i*|x>hBKlDai!W z`y}^02RX5ne|G}=I&qsGyC__I220(Esy44EUHi%RRp^Z~c|0EP8Dky}VHhCcO(qlK zIKDTV&1~)^zDn}T-uu9tB=<~%I6ORz^@GY%W%Yx~N3+@NnO~$I%!Bl@QT_tH1Kt7N z3S5hbv%wDGvuwUAF1_+c=mLhs=DXt3zKsb`g`_+WcodTTq9MG9h$984h=?NvsECLo z1*nLKqryof-K>`9#pUHCi^U>z8Pa3d*VnnrZv - - - - - - -STM MATLAB Simulator: Hardware_Constant_Definition - - - - - - - - - - - -
    -
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    #define LSI_STARTUP_TIME   40U
     
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    LSI Maximum startup time in us

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    - - diff --git a/DOCS/html/group___hardware___constant___definition.map b/DOCS/html/group___hardware___constant___definition.map deleted file mode 100644 index df0a5c6..0000000 --- a/DOCS/html/group___hardware___constant___definition.map +++ /dev/null @@ -1,4 +0,0 @@ - - - - diff --git a/DOCS/html/group___hardware___constant___definition.md5 b/DOCS/html/group___hardware___constant___definition.md5 deleted file mode 100644 index 28b479f..0000000 --- a/DOCS/html/group___hardware___constant___definition.md5 +++ /dev/null @@ -1 +0,0 @@ -ca5f137e06e1841848aef6c043b10388 \ No newline at end of file diff --git a/DOCS/html/group___hardware___constant___definition.png b/DOCS/html/group___hardware___constant___definition.png deleted file mode 100644 index 8f2e31f7e7cf297fcf43365465c9e6ae0f7fa977..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 1324 zcmV+{1=IS8P)unip*6%hqQvsIzg@h2>LWslu!lD7Y2jIupLAc<1oJegxpC19ZTVJ;{Su7Mq z5j-Fot~}3UhtSz*G{V-_R_ri{k}{o6F`Lbn)@Ko7AtIuI;bcKXL|U9Ih=@pwlLZkG zX>qb3A|fqL7DPm(xGHm1XIxDQ7~6B;xSN*O(%2n_B=r1#ln0ho}xx{*4t3*~|0% zrO#e9m;36suXdVcZRYF{%1+**1a{X9&s`P~{CDB&SX4$qsA3HwTk*-NBvc6^YR4E+WK5SD#HcaDIy{`M6 zsoGHWt!uvvZ)qsi4rh`2D9iFiDnynNsjpK#*Dbr2wb@yQ>R(n)wyj+HaB0WVy8s>l z_#D7(09W|`z4fYVqp30Z!_%c}>dVdNt}(gvCtL2S%h+Y*7Dw}@ZK~RpwG(o@CjGUI zAAq)vF28qI$y~E=t?wfbzu1|E?%%X*TRB}DeQw9&L!3_7g5g6 z&M+E{tm>$aq;+LXUazM)>N^V6&#wK&;F7nuZ6l@ewh0|)i1xir7A90@6(J4bE~n;X zrQ1F}#$?;4%+Aiv@pL-<9>8a)&MIC9@C?;NpmPP_3+qlj+1%U=_TO^*&TZTDmtx+% zc|Ab4qf2QFDa8_6uaiYv8Y+~b+#O|_5|X8lLiefh$Mxe8fNcP~0KPACL?Q`coj)=W8>=D|b6C%Y5K=S0!vdQD$U#v6O$3az&b z-1Q?@+1W)sEuvcAd`%TcvmaSq*XtBEZQ5L;Xsf3hlkFHxw~YtS0Q_?O_zKm;aUZ}( zs3wk;y(>y~?ZKpMjQ(stcc825+PQ>qZ0Nw%cT9Duj?CqCTwK4szYb>kHFRL`0;;$%2T8v^ZH15s?-r3nC)YQeNQZMIc&r=jZ2`&1SK~ zAWF*R<)w7}(qxfk+39>fKRP)%2_6&;Tb5;~v14#mmgUjK#YOBeh?10L+2hzT5D^g( i5fKp)5fKp)$@~XQ{|`nf7zg_R0000 - - - - - - -STM MATLAB Simulator: Library_configuration_section - - - - - - - - - - - -
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    -Macros

    #define STM32F4
     STM32 Family.
     
    #define __STM32F4xx_CMSIS_VERSION_MAIN   (0x02U)
     Comment the line below if you will not use the peripherals drivers. In this case, these drivers will not be included and the application code will be based on direct access to peripherals registers.
     
    #define __STM32F4xx_CMSIS_VERSION_SUB1   (0x06U)
     
    #define __STM32F4xx_CMSIS_VERSION_SUB2   (0x08U)
     
    #define __STM32F4xx_CMSIS_VERSION_RC   (0x00U)
     
    #define __STM32F4xx_CMSIS_VERSION
     
    -

    Detailed Description

    -

    Macro Definition Documentation

    - -

    ◆ STM32F4

    - -
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    STM32 Family.

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    - -

    Comment the line below if you will not use the peripherals drivers. In this case, these drivers will not be included and the application code will be based on direct access to peripherals registers.

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    < STM32F405RG, STM32F405VG and STM32F405ZG Devices

    -

    < STM32F415RG, STM32F415VG and STM32F415ZG Devices

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    < STM32F407VG, STM32F407VE, STM32F407ZG, STM32F407ZE, STM32F407IG and STM32F407IE Devices

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    < STM32F417VG, STM32F417VE, STM32F417ZG, STM32F417ZE, STM32F417IG and STM32F417IE Devices

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    < STM32F427VG, STM32F427VI, STM32F427ZG, STM32F427ZI, STM32F427IG and STM32F427II Devices

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    < STM32F437VG, STM32F437VI, STM32F437ZG, STM32F437ZI, STM32F437IG and STM32F437II Devices

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    < STM32F429VG, STM32F429VI, STM32F429ZG, STM32F429ZI, STM32F429BG, STM32F429BI, STM32F429NG, STM32F439NI, STM32F429IG and STM32F429II Devices

    -

    < STM32F439VG, STM32F439VI, STM32F439ZG, STM32F439ZI, STM32F439BG, STM32F439BI, STM32F439NG, STM32F439NI, STM32F439IG and STM32F439II Devices

    -

    < STM32F401CB, STM32F401CC, STM32F401RB, STM32F401RC, STM32F401VB and STM32F401VC Devices

    -

    < STM32F401CD, STM32F401RD, STM32F401VD, STM32F401CE, STM32F401RE and STM32F401VE Devices

    -

    < STM32F410T8 and STM32F410TB Devices

    -

    < STM32F410C8 and STM32F410CB Devices

    -

    < STM32F410R8 and STM32F410RB Devices

    -

    < STM32F411CC, STM32F411RC, STM32F411VC, STM32F411CE, STM32F411RE and STM32F411VE Devices

    -

    < STM32F446MC, STM32F446ME, STM32F446RC, STM32F446RE, STM32F446VC, STM32F446VE, STM32F446ZC, and STM32F446ZE Devices

    -

    < STM32F469AI, STM32F469II, STM32F469BI, STM32F469NI, STM32F469AG, STM32F469IG, STM32F469BG, STM32F469NG, STM32F469AE, STM32F469IE, STM32F469BE and STM32F469NE Devices

    -

    < STM32F479AI, STM32F479II, STM32F479BI, STM32F479NI, STM32F479AG, STM32F479IG, STM32F479BG and STM32F479NG Devices

    -

    < STM32F412CEU and STM32F412CGU Devices

    -

    < STM32F412ZET, STM32F412ZGT, STM32F412ZEJ and STM32F412ZGJ Devices

    -

    < STM32F412VET, STM32F412VGT, STM32F412VEH and STM32F412VGH Devices

    -

    < STM32F412RET, STM32F412RGT, STM32F412REY and STM32F412RGY Devices

    -

    < STM32F413CH, STM32F413MH, STM32F413RH, STM32F413VH, STM32F413ZH, STM32F413CG, STM32F413MG, STM32F413RG, STM32F413VG and STM32F413ZG Devices

    -

    < STM32F423CH, STM32F423RH, STM32F423VH and STM32F423ZH Devices

    -

    CMSIS version number V2.6.8 [31:24] main version

    - -
    -
    - -

    ◆ __STM32F4xx_CMSIS_VERSION_SUB1

    - -
    -
    - - - - -
    #define __STM32F4xx_CMSIS_VERSION_SUB1   (0x06U)
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    [23:16] sub1 version

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    ◆ __STM32F4xx_CMSIS_VERSION_SUB2

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    #define __STM32F4xx_CMSIS_VERSION_SUB2   (0x08U)
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    [15:8] sub2 version

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    ◆ __STM32F4xx_CMSIS_VERSION_RC

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    #define __STM32F4xx_CMSIS_VERSION_RC   (0x00U)
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    [7:0] release candidate

    - -
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    ◆ __STM32F4xx_CMSIS_VERSION

    - -
    -
    - - - - -
    #define __STM32F4xx_CMSIS_VERSION
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    -Value:
    ((__STM32F4xx_CMSIS_VERSION_MAIN << 24)\
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    |(__STM32F4xx_CMSIS_VERSION_SUB1 << 16)\
    -
    |(__STM32F4xx_CMSIS_VERSION_SUB2 << 8 )\
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    |(__STM32F4xx_CMSIS_VERSION_RC))
    -
    __STM32F4xx_CMSIS_VERSION_SUB1
    #define __STM32F4xx_CMSIS_VERSION_SUB1
    Definition stm32f4xx.h:111
    -
    __STM32F4xx_CMSIS_VERSION_SUB2
    #define __STM32F4xx_CMSIS_VERSION_SUB2
    Definition stm32f4xx.h:112
    -
    __STM32F4xx_CMSIS_VERSION_MAIN
    #define __STM32F4xx_CMSIS_VERSION_MAIN
    Comment the line below if you will not use the peripherals drivers. In this case, these drivers will ...
    Definition stm32f4xx.h:110
    -
    __STM32F4xx_CMSIS_VERSION_RC
    #define __STM32F4xx_CMSIS_VERSION_RC
    Definition stm32f4xx.h:113
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    -Generated by doxygen 1.10.0 -
    - - diff --git a/DOCS/html/group___library__configuration__section.map b/DOCS/html/group___library__configuration__section.map deleted file mode 100644 index 1e66d08..0000000 --- a/DOCS/html/group___library__configuration__section.map +++ /dev/null @@ -1,4 +0,0 @@ - - - - diff --git a/DOCS/html/group___library__configuration__section.md5 b/DOCS/html/group___library__configuration__section.md5 deleted file mode 100644 index 7337e22..0000000 --- a/DOCS/html/group___library__configuration__section.md5 +++ /dev/null @@ -1 +0,0 @@ -b0a1c122348dfe70ec4e9aceb3a94c1f \ No newline at end of file diff --git a/DOCS/html/group___library__configuration__section.png b/DOCS/html/group___library__configuration__section.png deleted file mode 100644 index bc1c0a03d806b4e30f8fdfb52a4faa71a1811341..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 1380 zcmV-q1)KVbP)q+_7?BuR3fW!X`6-BVJ*P&|}UkELUv z_$(HS0{|aX*D>LclgVU)&CN~eFenmdXJ?qt=S%Aofmn!Wq?mAsC>SOjA_|5Hhlqk< z!XctymhMvR?(V*-l-iaEW}W4E{`>y^{)KcLM3R;gj#6ry&t3H5A%O3tg9sr_Q)F3Y z-PW|o(K!sk7muNTW_!-PXoFg5q75YuPltxKhpT6*Kbyg0X(&Elv2p^ym5WqK3&Q#*EMak#Wi5h19%U>BLHs!xCfy92Pe#Q;+ro1 z>VCHI9Q^@0-}G|p#)WLLcB#))zUwjCKAXD4+s854EM0li>GXk8>T#RO`%E}(>T|8L zOgO&cu}RYud7eL<&1Q8^8b1r*9RME!c>i{Jfg;%eMZysq;NRQZ%VV5?OZutWwqlF7 z$?XJO2eaAi&WwM(p2XD)zxuDfPG9e%1!AhRTy|;om}0G4?kEB927s>t{0ZPk6w@(2 zhvE;xz52J(Iv9HQrw?AbRAu+3x@_8R>;6>VtMA`bep5`Yt(fZm`um!;b?`cXPXK(1 zVvOcr{QrA+dX<8yQ0-or)|*JQEF`)#(!AZJG9?Gwg=tDmuI1aha3(&xb!{CU9=-|S zD*&%)n_PYe3WDP}7Z(?pOeRv*w^n!I4)KB>VoZJN<+gYq<2E)v>S}7itlGNS+1dH! z^z`%_03V?k5PliJKLDO_EJEzRYPo;^{wTiXPW|ikE>$Ql_1BFfnOaV5?~Ju@eEa$m zz&45`@(92SxZAbTwDa z+W@`;aE&6l+(-pRevNTpxQUm9Q~u@GU#3=qkFrg7zgB(Vuv)G@2;Q{KgBt)pp%_Sh z3Bbnyo}g&)+#tedaK=neFk>5|vGLZz(OVFv0b%{lkG{QbxvpGOolSMP)@Q1}X-;w^U9q9eKQlD7^Wki5ZArwlmQGGiZ1dp^TCDTokes^t zaF$v)Ns^o|7K?-9 -STM MATLAB Simulator: MAIN_SIMULATOR +STM MATLAB Simulator: STM32 Simulator @@ -14,6 +14,7 @@ + @@ -72,73 +73,50 @@ $(function() {
    -Topics | -Functions | -Variables
    -
    MAIN_SIMULATOR
    STM_SIMULATION
    +Topics
    +
    STM32 Simulator
    STM32 Simulation
    -

    Stuff for configuring, initializing and deinitializing simulator. +

    Ð’ÑÑкое Ð´Ð»Ñ ÑимулÑтора STM32. More...

    - + Collaboration diagram for MAIN_SIMULATOR:
    + + Collaboration diagram for STM32 Simulator:
    - - + + - - + + - - + + - - + + -

    Topics

     SIMULATOR_CONF
     Configurations for simulator to simulating MCU.
     Simulator Configuration
     ÐŸÐ°Ñ€Ð°Ð¼ÐµÑ‚ры конфигурации Ð´Ð»Ñ ÑимулÑтора МК
     
     GPIO_SIMULATOR
     Simulator for GPIO.
     GPIO Simulator
     Ð¡Ð¸Ð¼ÑƒÐ»Ñтор Ð´Ð»Ñ Ð¿Ð¾Ñ€Ñ‚Ð¾Ð² ввода-вывода
     
     RCC_SIMULATOR
     Simulator for RCC and Clocks.
     RCC Simulator
     Ð¡Ð¸Ð¼ÑƒÐ»Ñтор Ð´Ð»Ñ RCC и чаÑов таймера
     
     TIM_SIMULATOR
     Simulator for TIM.
     TIM Simulator
     Ð¡Ð¸Ð¼ÑƒÐ»Ñтор Ð´Ð»Ñ Ñ‚Ð°Ð¹Ð¼ÐµÑ€Ð¾Ð²
     
    - + - - - - - - -

    -Functions

    void Initialize_Periph_Sim (void)
     Ð˜Ð½Ð¸Ñ†Ð¸Ð°Ð»Ð¸Ð·Ð°Ñ†Ð¸Ñ периферии ÑимулÑтора МК.
     
    void deInitialize_Periph_Sim (void)
     
    void deInitialize_MCU (void)
     
    void Init_TIM_SIM (void)
     
    - - - - - - - - - - -

    -Variables

    struct TIM_Sim tim1s
     
    struct TIM_Sim tim3s
     
    struct TIM_Sim tim4s
     
    struct TIM_Sim tim7s
     
    struct TIM_Sim tim12s
     

    Detailed Description

    -

    Stuff for configuring, initializing and deinitializing simulator.

    -

    ЗдеÑÑŒ дефайнами задаетÑÑ Ð¸ÑÐ¿Ð¾Ð»ÑŒÐ·ÑƒÐµÐ¼Ð°Ñ Ð¿ÐµÑ€Ð¸Ñ„ÐµÑ€Ð¸Ñ Ð¸ подключаютÑÑ Ñ„Ð°Ð¹Ð»Ñ‹, необходимые Ð´Ð»Ñ ÐµÑ‘ ÑимулÑции

    +

    Ð’ÑÑкое Ð´Ð»Ñ ÑимулÑтора STM32.

    +

    ЗдеÑÑŒ дефайнами задаетÑÑ Ð¸ÑÐ¿Ð¾Ð»ÑŒÐ·ÑƒÐµÐ¼Ð°Ñ Ð¿ÐµÑ€Ð¸Ñ„ÐµÑ€Ð¸Ñ Ð¸ подключаютÑÑ Ñ„Ð°Ð¹Ð»Ñ‹, необходимые Ð´Ð»Ñ ÐµÑ‘ ÑимулÑции

    Function Documentation

    ◆ Initialize_Periph_Sim()

    @@ -154,6 +132,11 @@ Variables
    + +

    Ð˜Ð½Ð¸Ñ†Ð¸Ð°Ð»Ð¸Ð·Ð°Ñ†Ð¸Ñ Ð¿ÐµÑ€Ð¸Ñ„ÐµÑ€Ð¸Ð¸ ÑимулÑтора МК.

    +

    Эта Ñ„ÑƒÐ½ÐºÑ†Ð¸Ñ Ð²Ñ‹Ð·Ñ‹Ð²Ð°ÐµÑ‚ функции инициализации периферии Ð´Ð»Ñ ÑимулÑции

    + +

    Definition at line 23 of file stm32f4xx_matlab_conf.c.

    + Here is the call graph for this function:
    @@ -161,186 +144,12 @@ Variables -
    -
    - -

    ◆ deInitialize_Periph_Sim()

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    void deInitialize_Periph_Sim (void )
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    ◆ deInitialize_MCU()

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    void deInitialize_MCU (void )
    -
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    ◆ Init_TIM_SIM()

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    - - - - - - - -
    void Init_TIM_SIM (void )
    -
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    Variable Documentation

    - -

    ◆ tim1s

    - -
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    - - - - - -
    - - - - -
    struct TIM_Sim tim1s
    -     		-extern
    -
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    ◆ tim3s

    - -
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    - - - - - -
    - - - - -
    struct TIM_Sim tim3s
    -     		-extern
    -
    - -
    -
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    ◆ tim4s

    - -
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    - - - - - -
    - - - - -
    struct TIM_Sim tim4s
    -     		-extern
    -
    - -
    -
    - -

    ◆ tim7s

    - -
    -
    - - - - - -
    - - - - -
    struct TIM_Sim tim7s
    -     		-extern
    -
    - -
    -
    - -

    ◆ tim12s

    - -
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    - - - - - -
    - - - - -
    struct TIM_Sim tim12s
    -     		-extern
    -
    -
    diff --git a/DOCS/html/group___m_a_i_n___s_i_m_u_l_a_t_o_r.map b/DOCS/html/group___m_a_i_n___s_i_m_u_l_a_t_o_r.map index f492ece..5cb0183 100644 --- a/DOCS/html/group___m_a_i_n___s_i_m_u_l_a_t_o_r.map +++ b/DOCS/html/group___m_a_i_n___s_i_m_u_l_a_t_o_r.map @@ -1,8 +1,8 @@ - - - - - - - + + + + + + + diff --git a/DOCS/html/group___m_a_i_n___s_i_m_u_l_a_t_o_r.md5 b/DOCS/html/group___m_a_i_n___s_i_m_u_l_a_t_o_r.md5 index 949e56e..bd384cf 100644 --- a/DOCS/html/group___m_a_i_n___s_i_m_u_l_a_t_o_r.md5 +++ b/DOCS/html/group___m_a_i_n___s_i_m_u_l_a_t_o_r.md5 @@ -1 +1 @@ -957cce6beaaf02c68ed5f159dd4a47f9 \ No newline at end of file +5d02ce0e8740d2ed3c5fd9acaa38c462 \ No newline at end of file diff --git a/DOCS/html/group___m_a_i_n___s_i_m_u_l_a_t_o_r.png b/DOCS/html/group___m_a_i_n___s_i_m_u_l_a_t_o_r.png index 610d56387c7d027d3cb0047588fb08af6a47273a..4dda60b2c2d716dd337729fbf40dd5f48f5dfa3e 100644 GIT binary patch literal 6155 zcmb7|2T;>%kib(Q5Sk!Gn$#dwsnV+;5IP7*hdiW7?;V1~f+%7_uYv&uq)3fO38TjSssOWa(aL?ATv_3fCT zX_pwa?mSEo;cMjkS>M1?p~-Ubr2)Z4@AV^wv77AnckP@-CUU;grSyd;Lrl!MRW1*j zybxiSVM&MSd^F~35lQ%QjSqo%Go?}B7*@BpGFd0-L7IF!OX^DrCrxelTCH!Zki_+| z2;{#nJc?!hA{tQ^uB)qSlAV{QDzL6N()#)H=iEc9vA#G~1hQx5$B!TL<}CTS;oM7b z92jZgks;|k@bRPm4C8w^cooFCDjcTq#zTgDX?iz^!4 z6FAe-D&bY*T%i@)%5u}s!q%%xA;d1O>0tpi`V$Zx6N~x6n zX6Jem8n`D{6*;(u?k<)F^puo8Q;F3TPIpz=tmjnC3JX9Dg(Bx0w)=`}b2YJeevkh% zqCmW`_wttM^oQi?0_SwCtDW-0*_Q_2zt@@VmE%aod*Lm`rdvaotsDKOmFK?}s71T0 z?voR%qxQeuf0C!*KeH=4pg5PQgb_hv4}Idv4rDeLsv6pT{s5B#EhHB2(+?Ve_)!#4 z?n1)Bnc(|B*fW8YFoP@76WAhXM4+x13bK__mk<&w6DGh9j<}NwdPP-5k(4FpP_C>;p{ysT9yl-l=KJ7R$4;XKT+2+?R^NCo@` zq_E<6B?knY39d`nrp|?=Cs3iq(TUr123UmKx@V^x@dezTVpbNg4a*Z+$(+f4k%CTgCz0ntmvKU8b<`2%N2;@@o@XJt2RSE|f zcb2yfU_7`EenjzAFN-zc0xART2tKo4jaXqL+?5h1>pF00Y7@OAu@u4}-b?i`RjL>+ zLW-2O3)vxN^TT~T^WQryb7mgJBF$d?Iad|->WsoaVC7yJ5bfcvpc(Kn=RON6m7J{9 zHQFHZa6!*JWG%4!Vt1ZWRg|j!Shcgp8}IR|owM|I^SlxO-UuYykWI+kNzX)jkfl7c*9}Ox82%^q`k;W6od|s*jlwHtpkbC%eB7Ef${}2*X@0MV4*_wJ;S;qN>eTd}D#*i5 znIWbsdtrww_+>kxtNF)V$sYkb)sDtC7p2y!*Nm>wcF4GBYb09K;%Qp*=klG#2h?^J z?df@pR0vYPn(lCo&mB zetD0C?TP2nS}pOTEn0Samq5j{zg}YT>z&g3aF);`;;$HF+gL3H@&bMo+wjTsqQo1liph_BEw;J z8|awLo8v?)>Fy?GcepB@4~0DViKY4ztg{d|co7tDXfwLeqn@skyurqMbFw|hF7uNi z(RD=ZKxHW|4z%ZLrdx`DUT}`t{08*y96c$ql%O}qxCZZW^^9=te4B>b>50RKEwXSL04vbyZ34Zi1O#sD}1_`rGn zbNDv3?%i5!jc6ZnGrs-g^8SivXbyDk%MQKhL^DC#;=EA_2n!v!a#Zcs(d_mIvTj$-#`$crV6Ez9GQ;kB7 zTkh8kiM)_#v2OQ~eCMGbZPzhP2VFgJqEgjC{eIUJ^c{jvtErE~f2@^Pe2)sS45-@{ z8Igu!OLK7vlAw5<%kT$B_DyIh=y$2x&woEbgm{3A7{&JJG4yF|RtJ&LBIov+{)6C! zzR8y0#eww5?xK{+_3#AXiIpagGr=fMl^QtcDo?u{!Kykhe**zoZ9C-9A9oC&4yN-| zDBMEH@Ocfk7Ss%M6k2dGOH~}qONs-v5CI-C3#Pn=gf1ru7i5|KJRc#5+L$qNxlmN> z@21dNXwFBEu!kY&UtLdTQ#16H@8}?IViFSl!7~)ce)C^>I>{Y}cb^L6oD)d9_Yg?+ zUw=Ue6)(jKb2%Rp86JhpnrSBxG}Gl*BIw;Xv)SBXfnW zn}a$o;EgNfYuAQ-bRx95*!#trmNx6ty@!IaRb@PYUgX!*^(cNy6Ha++b%n)?4=h=r z^;rWI{25$ybAxloh?sJ|FKoG z6Qzg6qTO@fP5vDUdrX@pMF+0*^GPf>!y;h&>ZniOC)0yvb7qyZ{_|vnir?AE$XmB= z^=uLdxc{o(3Ky;0(_rSNb}&xy%{a@MR*`BPVXo^6{^H)?QsmBTZfJCUbG2=r<8gS9 zKoKqZ1asLr{6_9Owae$xT?Q?@>EV(+%ZN3?Yg(^vwfZQhlRbjpldyKfrNV+x=J&0} z;TGW0n|F}uHaUURUSb_#bAGDhzTa_H-$z!1*9mheP0)DLiLeHzoDUA=&l`dRNospF z5u4u|*OH=h*YJOpS5x4`n&i@5a(Z4*6SzpB_6NJQTk=e)TeweI2|TS&!%A?q+YjH~ zH$G4cUdZ;CX$xEZ!iC<0T##z8;`@|Lq>`bN{QOyucY0Lj)pU#Ko`JC2B5RZJ(Ga;e zL|)5jsOtuXFqgBJ%=fTZW&_u=DAT!Hec}B1L@0GKLC%ma3^%908Wt`tVYeOfCE_7t zxWkQhe8-KC^AB*%)OJ=G*I$xVtkQJ&x)3P-Ohfc6c!1w>R|W3fvF;nUyn$R2@U*gJ zE4s6umV}lg$Z%-d#J7xp@43xAm>Kr1NMg=!7ibAzvW=g1KkI+!Nc2r7#gOwc9e4eO z5cE)mmr{OgnmZ91|3luczx1Q)vr>FW>4pf{Wn`|sad1*nR{ml# zd&G|!rIJLv+Sq+)bjR=;*6@m`q*DuFbqzwFLC+;$1C$keT|GULckB+!5mTe86V0)q zzaS1qB3@R;cSg|=+O}-df+Z|kvoZ9KOb`-UF=7D@^ZO(zj#ML9T9WVU@COpRT zRj9pP@aB*ia7x-SG6-3Rc-n(2E zI-#r2@LfHZ`jd_r5aVXx&IRB2(~IY^t#j{BbEC|;1g(;Nrq$@y%hu>Sl@ZR~GnjHw z1#6;lU7w~69&?^hAJo!T;=flK=A6+7E3tI>#f#c6 zdgiw-Pc`|IR33TxZ!h%IHu=xC{b`BZ4&#p5=uiRL-P?-Uv&Qz;-l3LbpM8U#Op6(n zsW`f=npK-MJtDTF%M`%QucTPMwhbdYbi$l1d%nIn`gVG>uHkdAHJ=wUgcN<3+B`17 zA+qw89}0$*C3&rf(!Y>a{11u-z3R zVu8oW6L_*SP6{%m+UcE`V1NGn`D!S$z6Gr$qwd@+xaH}fq;st7jJ9t=;Sz6w8quHn zQ%5x%`7ZO9|D6rK4IZ*Tb+q>_U#^;}t;z1|7aV`9ksV_nXx;t<3{47+P=Dwtu4XL0 z!BlFMn-)#aeNl;@j~tub+9?RCYOyxnI5oiD%TZ?5bd#y-%Ma_&F= z74X9e{o7I74>r4aJ&FDQj|h^R~t%1f?*j9puMHC)R=)a!P@&|ecXD5R^V!`Kf4>Ew#mKoQjAMNI(W`F6 zb?6_8n7mXG2c+*@VbKi?P04Gx%9Aas>oe^YVE~8`D}O-^Cz@j_A86=$itf{(UTDsX z^gdLokcO=;jkX6eV%dSmdVP-$b@WXzK@xI-aZH*3jxbIM+_9PibsmBfTI0fUmUAAj z`0w_a9M0NL&jL~H@s)3tUX6HM-(G>2IZOuuhB#TK;FXZ%1S?`Lwd1)aCN|}q-KE_8 zxtu~Atfu6EXYZ@~_=oh&-+lPnT;y12Gf54NvM6L6vADLxH3=_F%?bNfd-f^R#43HIl==UN(=)2EE?!>$ zsDZOh`cMhwiYGB+?>u4L)gmO-5I)D+Qc0<+7wl8nVG%pyKApecA5nX=f2GX3pUjTL z%B7hIN_fh_Rduq8BV4MO06ya&A@s_81A=nzY#=hd(FI6J&?XHzn25tk=5-zd^}iHAUWa zn-?zUP@BaSfy5#NQu~)wr!LZz>3rf8b<&+^egN*>a%XO)^Air?SEY6UOZ3SC=F*-h zFgBXS@k}tpR0J8FSzkiGqk3sx2=2gUZ`zE21g9l5!5i zdhW@;THJ`^)Ur&wkUx|$=u|0v0EEdTN?qL41zeD{Sk?{D5(L0kAB1c{?#B3GgwfTI z-oIhZysKycYs35#-d8d4#(yKM7zsg%$YVu*X&Y0Ug8;7-X&`LeY3O0JcfzchAzc-S zZT@el)j@aduNuxQzCL|Ia?Rjp@!&^>Sj4=GJZiV&G3M^$UB>f?hUf#Ou97=}RF{!C z3x5;StSp7s1&7Dmr1sNii42_fZ-VB>w^NKee*XMv9GRgZOX?ItPUhz2 zwZxnrA1oHc9sUBXd}&B_d>fVzV1n@N$3|!AhMcr(i%}936a>~8*gt4>;UcW01)7RL z9-L9i{|%}FNev*t8?-`5$>ib%@6YMI^O@CUr`&sLYuS|p3gY7ZC;1-%`q6hw6Z^Z? zMEslk_$8qWm1`9|09NJ6z;^(9E}-Cyb9&DQMH+}}D)^5+zRdDiL(g1pKEmMuIm<=* zpjI~-jP3Cr<+RWVW7fw84QJ`#kvvPdM@y~!U9$MkK6E-)8}U`Rux?Y9^fO(;OX8$3 zu@3}mG(P%2CsCgFI%iDulsPsOsn4{$&an!qgl#ma5UcaITg8B1&sP5hzSsXRZpt`8 z2owZ%+5r{1t65oDA5|y-s(~$SwI~bO8>_URY!3CFDf(~398sou$}3E{(0b$ru>t5l O2zlK^r|O!^o&Nx}4}p9D literal 6160 zcmZvAcQ~8<_diLk)>gGg38}p+TBEj@HETU)jiSURHJ_$bi4n7A6}4A2rDkfjW{Vgt z8mrU{8lyb?ZlCA#`(EEazE^T3x$fL&-shb6dA$ceYJ}c34u|i1PVF|n7X`IHZ^7?VDr#D@q;=2K`x{~O?Q#Oq)`bb)1+Ck7%CS#4E&Cnz9bf3AJ`{unzK4-b#`?c#fPIn1cdb2b#g;xK&V_fK#YbX*XJ#f<5b{i2Q#`%pb)~76`~!aY zi?Z3$4l5S62{WlU7|Ci(Z9Ur|UObvgm;qC2ohx)r+cUzh7V}ASHE_@+r?h~Te_Iv^ zg;XjaL^JZR<86tVM{ZF{ATI=I6bn6J>b}d!|F1m5oXs%qsaWr6S&z|t!;Ot>7Kle~ zLPCN~Z5{9+N;zIxh;Co;<>BHoz!nzV4IPan#8M^Cy?ZpV=s``Wj<3$^>4# z4!U@)hjDLz8aoubOMV*j7#B?jUE#=pz(upj3A9dh(&WlUdc2ZUKYy}k0~d3aV;RVo z@6oV>7Z}8cWrX1v3+Z_B2cRP|b6g3Igxgns3e;bpEOk3)3*8Le8GQ>4j4S)Z08=VD zK+Xq_GRQd#gF5r}+zh7_f@5B|(Ic3gyItL^m+m+{DpZGKN|$Ut{`N|k$2C*KQBTN# z3m)9YIcF`g4Yo^bC_MAnsN5~UrZ^atklf6OWDk*5IWfgResLtmGO+xVHY5)PXOkZU zBmphJI;@U6!EFOVT@bxhmCJA>tPPR`D9p6~8!|Xv82pH-F2X@i|lU{r#`nCidf74Vew#l?SnM0cbtI z$8ipnThJg{r*P+FroYM&v&SCy5O=4|5D zh(#h1!HciPg>21yJU$Mq@iyXxRG!`d`CVBs%;_P53Cx5|R8Liag0k}Pr%!qd&J|8m zwRRprZ!5tl!nhDOoulK%$cu!2!}KD108@A5uC#N8Q6cUi)SPpcx~OSTlc9!yN|nsw zgl5nfc_&>v^KlgLNNuEnf_&(3#h$`m2S#~nfP=<3u5x5#2m$TtRg1*;&f>s0Dw;JT zAuBGFT^<2obP(pQU{;e0e=l1pOgPZ6&BU|^TQ_f0>`onKl^@^=^-vR9+>|~>m znp_yeu@FMRS+ks@!%M(e({}fRuVOcR$SAb~^!hmtFD#M9(hqExo39B0E z2}}z4cl{HxY!^^1>-B`p>7tOl4@l~xH#X|*xh>acG_2jjRT@;rUR`&5>{@hq9M$F( zFFMYv{|N)k1SFoBP#{y!1Cj*o2y(|pf{39w7lLLEOrBNyD|t#g*GIF;-@_%$=5wc_ z(>E3)gEV=&_<$)wdd(8k78{OZiz%S1s}{#bFif=FE2N*xL!u%}(?6qaJhA!$40sy- z?SuJbnUo(XfZNEC#8^I1Jh+KwNW@zuMf&<47ojNTdyF$7!jSt8CMfFOocF{nIX`@d zV5aVkVE4U~9A&)?At*SMJf0D0Oci?sY8tFBB9BM}$~zoYmX$~y$j$rt&dkfw^h{Qp zBldT>(O(`V!GQt)mnrfA_xsdIF$Z<_kQ@qb3(}c}hE$J1EDKEsb2gbH)u9{ra?+QI zJ@nnQ#tE7fH0PA>?J9p)!vnjhjw6mW6?Yk>i4}D-DHz`|=gmhI)2>KX=gQU1*ozU# zn)7LKa=rbCwrT8>=xTJvlFz%0cgZbPyPNNljiVX117tVA% zo+oI)#i+$YDvEVoSoYO?2cHGm^vEW}Sy)N-3`) zd}%&za-1(f%E1)q0vAVIf zt3`aHqF;oKp%67GLC9^UV$&b(M)4I88 z_uj`wRbD=5;LDdUb+b(#Cd0t7vDO}bApCQzNX>t}IDW^r1+l1==+b)L#>37&)9yZ! zdunTcs6pT))YAk?JGF)$v3D=9_z#1U1t1jI6xZ03)y+dj=5l{RIZko#LdBtOGn90- zNX}z)A;({j4scEj@auB*U`j%c3ZW#w7B2tTbGdUcEO$U(Tn7v;I~oty$pcXL2|FIH zx!qN3Fsl}xqdC*=#o=7Ny>Z1^X5!S^$K%e;V^xGEeypoIQamF)uIGmLRLy5udQuKB zB-=IDXNW}UYd6F{-KAxn>qm3Vc6RK1uo;T+j-6)2#61VcTi@zBq$kL}iDy5rIQypR zBzKczhI-ECyh(Php~P;tF$Kcp#Ghs2 z^T!_4V*D^IEp3F0mzUS$tl+8(pcu@Q#{_9j?Dca}VfWfuy`SPzV!HGt-d-6DRJ0xW zk(wJ&`38b*@E9vp?G+FdwOHy~^8n9ht%(>#WS9SYL4WZY|vo31HtGNYg>W+isWb`X9 z7lNG``=~i9(wx~FmKRSCsP*+Vr!n#F9@UC>hfDwDx}Ro2mGav0O1oG$p~|+eSon}n zh@+stOGRj8bZWz1o(Sqr`SrxPn#}21_cw{o?~+)tweLoXYz> zJ=%P@p+vSFb>OF%`SJJLaq;miKOU$UJNEjm zk%amC6B^fdt9fdLQ}n$YMGX{|>t21*NOP&IfXIi_rw0kD+jd5rJXJg2OX&i&-)PBi zSiA6b3KeKjACwNaaHGd_)dDww0Hj9#yPYsW_{m*2H0IT}V z2X-q;K3}SKjG z5SV8MI=Z^)!#p{3XF^0IL0Q8rZK$Cy^MQj6Coix2$G<6RrKXbJ`!DOf_xlmGxxT)x z9X=qy`s~MfM%g?n^1{#c501a`#|UK>c-fF)8Lm>hhKYxHs8v9>2Jgl=qyxM7s{0M+ zl6TpR^gVab4Of5h6T%F6C!t8maB1}~hHih~hh?H(1$g~@gi7evMA3Ac8`j^>6{s=9 z{LvT_0{Sw2O{U;hKB)aULVrtDlu+5~%5%u_k$}c13HmDO%cn2w44g>xJZ&Rd{Z= zZ_8pF*h*C1kT*ZSEUGzp(+WsXAprPV$_tTI3lnYB@ZMX*5W+4ET&pA6oQfu)-B2H8d zbTc3y;jL_<*2&mF)%g?elh&HYf)J)6q2YwEz>||f>AtXnCteB$;_l!coSBA3u0~1Y;Y(@ia)}ekG}?Cea~9b26UKp z!R>T$Liqzc`dM-gtW4R?a_m9yBIpy2P`$5M+F~6u_(+qR*f4V9#_4WX^!YQkJFDvR zZu|U|o`qx%SLf7c%!@;0U9^@<7Sz&Q?BQpeVPeh>S~ny@dmIw4NwyHYQEqR{rUCG6 z#$?3U|7TZt0rQEO$WJV|?&>ulxRU>cmY$whno46M16XxlBd>tS+kW5PtFc&5=S|v&~C?SG1jb_4HCdBlNv*Cf8Au@7lrU<#Oe4U!caNrFGQX z9QO;wBH4BAOw1YIPr{knP*f~1X`9Zo@m7gYnf+xZ$JTmzRz@1n>~m-#p4ORsvalZdHy?pz**FWJm3N8f#d5E_)Kr)|Vt2y2? z3!6v^aq9%jBcvMWTe!0;6fNPPTsrOR>cK8%D8D6}#Dl`>=#=^M2mln2UXPLak#)kC z(dmbbqv^0`4Sv0_MMM>_*0S8TGUF*T`}I;66Ib4{F-XQ8Kf)F7> zQS;)vQ1NR86GUSL%STRJ3O@^sYYc5eFq`A-nCGWa-_auV3seBKlABfSZhtNp!v?;f zJG)D?>oyxJIk+alhh-6-U|*}REis)XE$NBHwd^()^xxSz-G;oWc?pahgqpMl`*=%o z!(<@$@r}iNG)DY-&^Es( zO;mMaLU1@^`y&nO$8)mn9-3u`x8_5Fr+vFc(OBG7jU|K%(VqaoR2s3{vQ4f7^Z*Rb zcFWuVFE20CIRb#7^mh%^N12p@GQamj17>_ig)0Y8s%~PrS42enBTaw|d*Mw6D{A;P zd7a3(7)GS{57mL}@kcEt{e|PBu2wu3pMDN-5hkzB!E0?)WRv@6luyM zRrP05HR&!1 z^p^AH=Ab@$1hrb!^IuDQhPy5wQc~~R(+`jQhpUOuMBPlXqqcMQgVOqok6m7yFexA~y=OmPaMpZ+Tb*|I+& zbGCL(LJY1gak~Q1s<==r+M{bxc+Mln_n%Z@|I$1o?nrDuuM-r(!ppWWeb%QxPK))z zS7}0_(6Mc+@D#Q4E;`n+63o58hpRE(klCOHEV;aMp01;x5|sdPk$(s+htw^UwNTcc94R<`kyw zdtPfN?$c{3S$7~wJGFMr!kvEn&#ZwQ@&OeD5TyV-z?5nMwF);A5N5yt>>tpx0IzDG zAOsYG>2f56LD{(6w8eSb!We1L=MY)_Cl8-lx}!5KEYUO@iJr`Q@Z@pzG}m9*!hoQe z__qA(k-EoIuY^TP3RWQSdAQ|9P2Jrcj|aP0G*Ap)3Q%e$O zmv5wjucc0I@YqAZiPG-s|3#h}!vG#DqxIiqwqB83##m{-qRrFRh}S3&5U*T&XDgHz zum7~LPa58q{-CW7=t+w(ZGGn4&qz1jve6nfzBM37*|fC=_3GBU1=cU$Z9%44W&Ga) zdM(2K1@+iq`R|E0B}fY%P z7I4d|wWbQ>E4Ns` zY}}YI)!5kBu4$V5`qsWw%>S_F5O^-rIUoJs*{@<^R}%q>pA4>TtW~Gs^!NV*Gpm*; diff --git a/DOCS/html/group___m_a_i_n___s_i_m_u_l_a_t_o_r_gab020a77f89d6c0ea99c7559cfa7e3ba0_cgraph.map b/DOCS/html/group___m_a_i_n___s_i_m_u_l_a_t_o_r_gab020a77f89d6c0ea99c7559cfa7e3ba0_cgraph.map index 738f3cf..8062c59 100644 --- a/DOCS/html/group___m_a_i_n___s_i_m_u_l_a_t_o_r_gab020a77f89d6c0ea99c7559cfa7e3ba0_cgraph.map +++ b/DOCS/html/group___m_a_i_n___s_i_m_u_l_a_t_o_r_gab020a77f89d6c0ea99c7559cfa7e3ba0_cgraph.map @@ -1,5 +1,5 @@ - - + + diff --git a/DOCS/html/group___m_a_i_n___s_i_m_u_l_a_t_o_r_gab020a77f89d6c0ea99c7559cfa7e3ba0_cgraph.md5 b/DOCS/html/group___m_a_i_n___s_i_m_u_l_a_t_o_r_gab020a77f89d6c0ea99c7559cfa7e3ba0_cgraph.md5 index 7ddfaaa..c20bd43 100644 --- a/DOCS/html/group___m_a_i_n___s_i_m_u_l_a_t_o_r_gab020a77f89d6c0ea99c7559cfa7e3ba0_cgraph.md5 +++ b/DOCS/html/group___m_a_i_n___s_i_m_u_l_a_t_o_r_gab020a77f89d6c0ea99c7559cfa7e3ba0_cgraph.md5 @@ -1 +1 @@ -758cad9e58d2bc75e7811114f915bd69 \ No newline at end of file +7fa2ae74969543d99abd5288ff5816f1 \ No newline at end of file diff --git a/DOCS/html/group___m_a_i_n___s_i_m_u_l_a_t_o_r_gaff389f4df35953d82d9d30ae161a8cf9_cgraph.map b/DOCS/html/group___m_a_i_n___s_i_m_u_l_a_t_o_r_gaff389f4df35953d82d9d30ae161a8cf9_cgraph.map deleted file mode 100644 index c341873..0000000 --- a/DOCS/html/group___m_a_i_n___s_i_m_u_l_a_t_o_r_gaff389f4df35953d82d9d30ae161a8cf9_cgraph.map +++ /dev/null @@ -1,5 +0,0 @@ - - - - - diff --git a/DOCS/html/group___m_a_i_n___s_i_m_u_l_a_t_o_r_gaff389f4df35953d82d9d30ae161a8cf9_cgraph.md5 b/DOCS/html/group___m_a_i_n___s_i_m_u_l_a_t_o_r_gaff389f4df35953d82d9d30ae161a8cf9_cgraph.md5 deleted file mode 100644 index e840459..0000000 --- a/DOCS/html/group___m_a_i_n___s_i_m_u_l_a_t_o_r_gaff389f4df35953d82d9d30ae161a8cf9_cgraph.md5 +++ /dev/null @@ -1 +0,0 @@ -ad676e63ef76152dbe0862deab1ab2ae \ No newline at end of file diff --git a/DOCS/html/group___m_c_u___w_r_a_p_p_e_r.html b/DOCS/html/group___m_c_u___w_r_a_p_p_e_r.html index 3f68898..9d4a981 100644 --- a/DOCS/html/group___m_c_u___w_r_a_p_p_e_r.html +++ b/DOCS/html/group___m_c_u___w_r_a_p_p_e_r.html @@ -5,7 +5,7 @@ -STM MATLAB Simulator: MCU_WRAPPER +STM MATLAB Simulator: MCU Wrapper @@ -14,6 +14,7 @@ + @@ -72,36 +73,180 @@ $(function() {
    -Topics
    -
    MCU_WRAPPER
    +Topics | +Data Structures | +Macros | +Typedefs | +Functions | +Variables
    +
    MCU Wrapper
    -

    Stuff for running MCU app in MATLAB. +

    Ð’ÑÑкое Ð´Ð»Ñ Ð¾Ð±Ð¾Ð»Ð¾Ñ‡ÐºÐ¸ МК More...

    - + Collaboration diagram for MCU_WRAPPER:
    + + Collaboration diagram for MCU Wrapper:
    - - + + + + + +

    Topics

     WRAPPER_CONF
     Configurations for wrapper to simulating MCU.
     S-Function funtions
     Ð”ефайны и функции блока S-Function.
     
     Wrapper Configuration
     ÐŸÐ°Ñ€Ð°Ð¼ÐµÑ‚ры конфигурации Ð´Ð»Ñ Ð¾Ð±Ð¾Ð»Ð¾Ñ‡ÐºÐ¸ МК
     
    + + + + +

    +Data Structures

    struct  SIM__MCUHandleTypeDef
     MCU handle Structure definition. More...
     
    + + + + + + + + + + +

    +Macros

    #define while(_expression_)   sim_while(_expression_)
     Redefine C while statement with sim_while() macro.
     
    #define sim_while(_expression_)   while((_expression_)&&(hmcu.fMCU_Stop == 0))
     While statement for emulate MCU code in Simulink.
     
    #define native_while(_expression_)   for(; (_expression_); )
     Default/Native C while statement.
     
    + +

    +Typedefs

    typedef void * HANDLE
     MCU handle typedef.
     
    + + + + + + + + + + + + + + + + + + + + + +

    +Functions

    void MCU_Step_Simulation (SimStruct *S, time_T time)
     Ð¡Ð¸Ð¼ÑƒÐ»ÑÑ†Ð¸Ñ ÐœÐš на один такт ÑимулÑции.
     
    void MCU_Periph_Simulation (void)
     Ð¡Ð¸Ð¼ÑƒÐ»ÑÑ†Ð¸Ñ Ð¿ÐµÑ€Ð¸Ñ„ÐµÑ€Ð¸Ð¸ МК
     
    void SIM_Initialize_Simulation (void)
     Ð˜Ð½Ð¸Ñ†Ð¸Ð°Ð»Ð¸Ð·Ð°Ñ†Ð¸Ñ ÑимулÑции МК.
     
    void SIM_deInitialize_Simulation (void)
     Ð”ÐµÐ¸Ð½Ð¸Ñ†Ð¸Ð°Ð»Ð¸Ð·Ð°Ñ†Ð¸Ñ ÑимулÑции МК.
     
    void MCU_readInputs (SimStruct *S)
     Ð¡Ñ‡Ð¸Ñ‚ывание входов S-Function в порты ввода-вывода.
     
    void MCU_writeOutputs (SimStruct *S)
     Ð—апиÑÑŒ портов ввода-вывода в буфер выхода S-Function.
     
    void SIM_writeOutput (SimStruct *S)
     
    + + + +

    +Variables

    SIM__MCUHandleTypeDef hmcu
     Ð¥ÐµÐ½Ð´Ð» Ð´Ð»Ñ ÑƒÐ¿Ñ€Ð°Ð²Ð»ÐµÐ½Ð¸Ñ Ð¿Ð¾Ñ‚Ð¾ÐºÐ¾Ð¼ программы МК
     

    Detailed Description

    -

    Stuff for running MCU app in MATLAB.

    +

    Ð’ÑÑкое Ð´Ð»Ñ Ð¾Ð±Ð¾Ð»Ð¾Ñ‡ÐºÐ¸ МК

    +

    Macro Definition Documentation

    + +

    ◆ while

    + +
    +
    + + + + + + + +
    #define while( _expression_)   sim_while(_expression_)
    +
    + +

    Redefine C while statement with sim_while() macro.

    +
    Parameters
    + + +
    _expression_- expression for while.
    +
    +
    +

    Это while который будет иÑпользоватьÑÑ Ð² Ñимулинке sim_while Ð´Ð»Ñ Ð¿Ð¾Ð´Ñ€Ð¾Ð±Ð½Ð¾Ñтей.

    + +

    Definition at line 96 of file mcu_wrapper_conf.h.

    + +
    +
    + +

    ◆ sim_while

    + +
    +
    + + + + + + + +
    #define sim_while( _expression_)   while((_expression_)&&(hmcu.fMCU_Stop == 0))
    +
    + +

    While statement for emulate MCU code in Simulink.

    +
    Parameters
    + + +
    _expression_- expression for while.
    +
    +
    +

    Данный while необходим, чтобы в конце ÑимулÑции, завершить поток МК: При выÑтавлении флага Ð¾ÐºÐ¾Ð½Ñ‡Ð°Ð½Ð¸Ñ ÑимулÑции, вÑе while будут пропуÑкатьÑÑ Ð¸ поток Ñможет дойти до конца функции main и завершить ÑебÑ.

    + +

    Definition at line 106 of file mcu_wrapper_conf.h.

    + +
    +
    + +

    ◆ native_while

    + +
    +
    + + + + + + + +
    #define native_while( _expression_)   for(; (_expression_); )
    +
    + +

    Default/Native C while statement.

    +
    Parameters
    + + +
    _expression_- expression for while.
    +
    +
    +

    Данный while - аналог обычного while, без дополнительного функционала.

    + +

    Definition at line 114 of file mcu_wrapper_conf.h.

    + +
    +

    Typedef Documentation

    ◆ HANDLE

    @@ -117,6 +262,397 @@ Topics

    MCU handle typedef.

    +

    Definition at line 71 of file mcu_wrapper_conf.h.

    + + + +

    Function Documentation

    + +

    ◆ MCU_Step_Simulation()

    + +
    +
    + + + + + + + + + + + +
    void MCU_Step_Simulation (SimStruct * S,
    time_T time )
    +
    + +

    СимулÑÑ†Ð¸Ñ ÐœÐš на один такт ÑимулÑции.

    +
    Parameters
    + + + +
    S- указатель на Ñтруктуру S-Function из "simstruc.h"
    time- текущее Ð²Ñ€ÐµÐ¼Ñ ÑимулÑции.
    +
    +
    +

    ЗапуÑкает поток, который выполнÑет код МК и управлÑет ходом потока: ЕÑли прошел таймаут, поток прерываетÑÑ, ÑимулируетÑÑ Ð¿ÐµÑ€Ð¸Ñ„ÐµÑ€Ð¸Ñ Ð¸ на Ñледующем шаге поток возобнавлÑетÑÑ.

    +

    ВызываетÑÑ Ð¸Ð· mdlUpdate()

    + +

    Definition at line 53 of file mcu_wrapper.c.

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    + + +
    +
    + +

    ◆ MCU_Periph_Simulation()

    + +
    +
    + + + + + + + +
    void MCU_Periph_Simulation (void )
    +
    + +

    СимулÑÑ†Ð¸Ñ Ð¿ÐµÑ€Ð¸Ñ„ÐµÑ€Ð¸Ð¸ МК

    +

    ПользовательÑкий код, который Ñимулирует работу периферии МК.

    + +

    Definition at line 73 of file mcu_wrapper.c.

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    ◆ SIM_Initialize_Simulation()

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    +
    + + + + + + + +
    void SIM_Initialize_Simulation (void )
    +
    + +

    Ð˜Ð½Ð¸Ñ†Ð¸Ð°Ð»Ð¸Ð·Ð°Ñ†Ð¸Ñ ÑимулÑции МК.

    +

    ПользовательÑкий код, который Ñоздает поток Ð´Ð»Ñ Ð¿Ñ€Ð¸Ð»Ð¾Ð¶ÐµÐ½Ð¸Ñ ÐœÐš и наÑтраивает ÑимулÑтор МК Ð´Ð»Ñ ÑимулÑции.

    + +

    Definition at line 145 of file mcu_wrapper.c.

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    ◆ SIM_deInitialize_Simulation()

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    +
    + + + + + + + +
    void SIM_deInitialize_Simulation (void )
    +
    + +

    Ð”ÐµÐ¸Ð½Ð¸Ñ†Ð¸Ð°Ð»Ð¸Ð·Ð°Ñ†Ð¸Ñ ÑимулÑции МК.

    +

    ПользовательÑкий код, который будет очищать вÑе Ñтруктуры поÑле Ð¾ÐºÐ¾Ð½Ñ‡Ð°Ð½Ð¸Ñ ÑимулÑции.

    + +

    Definition at line 162 of file mcu_wrapper.c.

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    ◆ MCU_readInputs()

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    +
    + + + + + + + +
    void MCU_readInputs (SimStruct * S)
    +
    + +

    Считывание входов S-Function в порты ввода-вывода.

    +
    Parameters
    + + +
    S- указатель на Ñтруктуру S-Function из "simstruc.h"
    +
    +
    +

    ПользовательÑкий код, который запиÑывает порты ввода-вывода из входов S-Function.

    + +

    Definition at line 88 of file mcu_wrapper.c.

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    ◆ MCU_writeOutputs()

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    +
    + + + + + + + +
    void MCU_writeOutputs (SimStruct * S)
    +
    + +

    ЗапиÑÑŒ портов ввода-вывода в буфер выхода S-Function.

    +
    Parameters
    + + +
    S- указатель на Ñтруктуру S-Function из "simstruc.h"
    +
    +
    +

    ПользовательÑкий код, который запиÑывает буфер выходов S-Function из портов ввода-вывода.

    + +

    Definition at line 102 of file mcu_wrapper.c.

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    ◆ SIM_writeOutput()

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    +
    + + + + + + + +
    void SIM_writeOutput (SimStruct * S)
    +
    + +
    +
    +

    Variable Documentation

    + +

    ◆ hmcu

    + +
    +
    + + + + + +
    + + + + +
    SIM__MCUHandleTypeDef hmcu
    +     		+extern
    +
    + +

    Хендл Ð´Ð»Ñ ÑƒÐ¿Ñ€Ð°Ð²Ð»ÐµÐ½Ð¸Ñ Ð¿Ð¾Ñ‚Ð¾ÐºÐ¾Ð¼ программы МК

    + +

    Definition at line 16 of file mcu_wrapper.c.

    +
    diff --git a/DOCS/html/group___m_c_u___w_r_a_p_p_e_r.map b/DOCS/html/group___m_c_u___w_r_a_p_p_e_r.map index a569c11..802852e 100644 --- a/DOCS/html/group___m_c_u___w_r_a_p_p_e_r.map +++ b/DOCS/html/group___m_c_u___w_r_a_p_p_e_r.map @@ -1,4 +1,5 @@ - - - + + + + diff --git a/DOCS/html/group___m_c_u___w_r_a_p_p_e_r.md5 b/DOCS/html/group___m_c_u___w_r_a_p_p_e_r.md5 index 53acb56..8443c4f 100644 --- a/DOCS/html/group___m_c_u___w_r_a_p_p_e_r.md5 +++ b/DOCS/html/group___m_c_u___w_r_a_p_p_e_r.md5 @@ -1 +1 @@ -d464576bb1566257b21312a5eac955a7 \ No newline at end of file +405c128c2f9d6e355618c6289fec2756 \ No newline at end of file diff --git a/DOCS/html/group___m_c_u___w_r_a_p_p_e_r.png b/DOCS/html/group___m_c_u___w_r_a_p_p_e_r.png index 461b1507b95f750ce05420184e3a38cff13a2f22..cc00b06414fe5980bca49b5ee957411a680aec60 100644 GIT binary patch literal 2248 zcmV;(2sihMP)`;SY>Ajgp=nlHN?VWwyio9> zYI>`1JU2o??3EM|!BQ2Wy&KPML0Y}2iUrYJ3C5cxDkRouvdSU|EfE#8G3-t+-ZP%r z*?G^*J7@l#cYYr@?4J4azR#T9d3fJ<=FAHsA|fIpA|fIp(xjm60HlA0!{PmH#~^+h z3oCnv$G|cuh%8M7*XXCn8=`l9Nsgg6#X%U6*%J5Cq@9>MA?_ zy-jV`uOuf6CkO(fC~E!WnMZsK@vF*XNtO+K|FbFSV`;knG$lFdG?xSrpWI!S73ZQS z?JiT26Ypeo(`;SC1$o$rDSU<-Ex}s zzUVraGOIX-qOrv-LR;PGeagmTi^Zk>qQ^8ZwdADpl3lsvKfY~wye{i^Tlr z^VZ?IzsqM@RvqQ4B`3X5*A>h@Ta@Ehk`wP`b&0A_b*p1hE}TGppJ^S`U6qAk8|%p% z14^@9KycZ9p6wv}N@^PkuByb;CNv|)mE?rKU@vXf5=dB~J-mLPA zCak>A)RwgCIHo*Gad`m*&FDa&=cGRK_vc~o_*MKAOet=}b17wWEx z^hnpcmUU1|PNYZL=q|QRNltpLj(g;~&e!9zQFm2Dyrv}AKR*C|*kb+aJxHVU57!@8 z1CIia01pCn&wY9ga0vJbu$*|^vazvIbJZeK+mhUHIJ{qz|8`##MaReE@jnV|dO7eg z@EEWg(|SKpQ5e?&H&4oof5xv}lWo2LKAOB<2A&08sHlFCT-KJ{{{8!#j6)o(t*sT= zYzOcF@FcL8>EC(-w9oxs!E>YcWBqE)r?y4WwC$Co$%dW+Y z(fw@l`Z*>U2ADB9wdAB1Drw1$Mk7X}QQ>uY?`_LwEzc{*r4CR07kC3RW_KL83G=Oo z-vGY{-fb;1kp?y1T^)@^gkiX4Sr~?uBpjD=vf}80uYtFKzXE@1ITn#dRF>qj5{yeC zX)EDmwe;fFr>({5x~^!MB2qn#$+0yVrxWw6_eIyalqn+BsW+%EqccgaD_yp%u4EOuaBL!dRQc7_xLasDsf%8qnCC)< zErz_<(p+ylak;W9BF$)}C6`WMMH6BZt)XO{S&25izR0>ZjzdI@ZBMI+pA3BD$dNYU z>9kp`z$UxftE;OnPXXU6V3 zfRAepP^2UDsHFupdDPMqn0Xe!JWgpR`A-D~^LIa6Q)nWcqL$oZdmH#Q+aG^k<*d7W4S?v*_{X;vpqDKfH;#xKMN=oBshHV4f*=H)c!^rW4sD6JO;M*@!erNzN~C zVlF()nvxJq7x$sW`>ZJm4+3|QJtg6JOe?U|l!SSP!{Linl_h=|3|8+6Z_=Sr&Ie}WSYEQO|83z?enl60)9vK|5qQgfH<$M9GPF`ur1Q@phj{&z} zZZ?khPba-I!27^gwn~p4J<7_;ibI&mz`lL^-fK1_@tJN0mM-}g zcz@^4tS@PZl%pgkB3@IH6A`azOisKI1lzBrL{a3lecnD*3xc4Q`r>1&vh2EIZGw`V zEIiu@n0I0}ebT1msVl)%QEn5lHbvc45%HRmoOo-V)MsH+hT+a|p{?|t3-<*h4IZqvtDCv{gv#A`}&BH}eAIT7)ilAMTmO-W8fyrv{4 zB3@IH6A`cJJ~`>6@p#O5JZ?J-@qm(?bWRjS$J>rUx@j;NXi{Dg5fKp)5fKrQj{851 WW<$L|Ryg?p0000b(%8?-ye*`;8 zL_t(|obBDQZ{uVf#_{iK9Vc$7#M%SF)&VBk>5yPTtRO*8$AMVt=1)Lkf{B3zMk`$y z4^@H@l043@ zyRq2F7<0!M^Ps!3q^Irz--Ry1hyH%0%xpG020qBITMEK!ySuw9FG%`nGMR)fp|LoQ z+1uL-U54~bk|fr@?3 zNRp)1F2*XQfXt9yLc>#O=|(k9=|r|uQF3A_W`1HJ`*>T>5k zj4`BXT6?`QOW#ERux{hhXH{QK+T`2$)LkUsSJiQs?aTFd&}Qw6S_wj^7Y2)MUBj)Z zeAt!k&o@AAkGu5c+onm~e=UlDH-Y=WKCqRoU&{|;!?R&m_9F8QP}}1!efhR&Qg;zs zNV)dwy3VGJ(6j0M)Y$gIEE|dWs?%pzLA+sJ1wIFU2Yv=V;r|d^8)c)rMRmhsQ`w#e z+w)i!`nFM`>+fL|S_?v3@YD$y1<_h~1^5)W0G)S%;8vd2Xt%H~MNd2=igk zhttiXdaCNQg^usBxb)@H#&v?IsvlS9=jSg04}rIM_RQg?eTyaEd+oRdXJ==%+UH+@ zMWI!6UCY*&50}1Nf7-b0zs=bslN>(UoPgTd*_oc6p5AAE z7n+ZO*O`w7T}Odm0l#<`(7^Wgb|(`xu9F4%e~a38IZ@zJcPOhKF&F7g5cXjNY2z~^ z+y^a<%Krqu&X$*fcY&DsM9EXiM~9DqADZmk*Vb0|b2dIRf5LsxX7KbaRO@Jc*0|~g z=sKy=bn>ODo+d$2_xLu%Z@@ReYuWN8FwGu&8mg$a6a_+)peWle^ekx;t~10%$LR90 zq^_TvAS1%Xuy75PP$R}ZT=VpqELmaQzh=u9z#GgzKz$E*fqJLU8zt0fU7pWmiBH{& zVO1yaT`vQ4e;I~Ldy3zH-NW+4}tf9j|g;Xe0X@6 z>c*^Mliis0csw4v-Jx2frhkARv*i}>eAseC+^uyGx_k#$g7_<2WDU7|XL-}Cbr34- zMB2BhVOK`C;S!O-QxJ;C;3)`2WbhP(A~JY|lO-1ySr=W_A=0Xolar13kLsmemzS5; z^-Dn*MbUINn;l8~h?rq!+bDNWO3y^%|iD2g73u0cdZL_|bHL_|dTZO;Gz002ovPDHLkV1mcmK}!Gt diff --git a/DOCS/html/group___m_c_u___w_r_a_p_p_e_r_ga15045e0feba8ddf08e20958fd1e36cd5_cgraph.map b/DOCS/html/group___m_c_u___w_r_a_p_p_e_r_ga15045e0feba8ddf08e20958fd1e36cd5_cgraph.map new file mode 100644 index 0000000..6caed67 --- /dev/null +++ b/DOCS/html/group___m_c_u___w_r_a_p_p_e_r_ga15045e0feba8ddf08e20958fd1e36cd5_cgraph.map @@ -0,0 +1,5 @@ + + + + + diff --git a/DOCS/html/group___m_c_u___w_r_a_p_p_e_r_ga15045e0feba8ddf08e20958fd1e36cd5_cgraph.md5 b/DOCS/html/group___m_c_u___w_r_a_p_p_e_r_ga15045e0feba8ddf08e20958fd1e36cd5_cgraph.md5 new file mode 100644 index 0000000..7a94a42 --- /dev/null +++ b/DOCS/html/group___m_c_u___w_r_a_p_p_e_r_ga15045e0feba8ddf08e20958fd1e36cd5_cgraph.md5 @@ -0,0 +1 @@ +f432da35519c2bcdafca9513ff5bca6a \ No newline at end of file diff --git a/DOCS/html/mcu__wrapper_8c_a15045e0feba8ddf08e20958fd1e36cd5_cgraph.png b/DOCS/html/group___m_c_u___w_r_a_p_p_e_r_ga15045e0feba8ddf08e20958fd1e36cd5_cgraph.png similarity index 100% rename from DOCS/html/mcu__wrapper_8c_a15045e0feba8ddf08e20958fd1e36cd5_cgraph.png rename to DOCS/html/group___m_c_u___w_r_a_p_p_e_r_ga15045e0feba8ddf08e20958fd1e36cd5_cgraph.png diff --git a/DOCS/html/group___m_c_u___w_r_a_p_p_e_r_ga54429d6d68b1d72ce16bab374e3ffa08_cgraph.map b/DOCS/html/group___m_c_u___w_r_a_p_p_e_r_ga54429d6d68b1d72ce16bab374e3ffa08_cgraph.map new file mode 100644 index 0000000..17a8f7f --- /dev/null +++ b/DOCS/html/group___m_c_u___w_r_a_p_p_e_r_ga54429d6d68b1d72ce16bab374e3ffa08_cgraph.map @@ -0,0 +1,11 @@ + + + + + + + + + + + diff --git a/DOCS/html/group___m_c_u___w_r_a_p_p_e_r_ga54429d6d68b1d72ce16bab374e3ffa08_cgraph.md5 b/DOCS/html/group___m_c_u___w_r_a_p_p_e_r_ga54429d6d68b1d72ce16bab374e3ffa08_cgraph.md5 new file mode 100644 index 0000000..ffa9870 --- /dev/null +++ b/DOCS/html/group___m_c_u___w_r_a_p_p_e_r_ga54429d6d68b1d72ce16bab374e3ffa08_cgraph.md5 @@ -0,0 +1 @@ +6eeb81c01ba17b7ede05c0ffa30907e7 \ No newline at end of file diff --git a/DOCS/html/mcu__wrapper_8c_a54429d6d68b1d72ce16bab374e3ffa08_cgraph.png b/DOCS/html/group___m_c_u___w_r_a_p_p_e_r_ga54429d6d68b1d72ce16bab374e3ffa08_cgraph.png similarity index 100% rename from DOCS/html/mcu__wrapper_8c_a54429d6d68b1d72ce16bab374e3ffa08_cgraph.png rename to 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a/DOCS/html/group___m_c_u___w_r_a_p_p_e_r_gaccdef5b45f3d1646f248304e02b00e54_cgraph.md5 b/DOCS/html/group___m_c_u___w_r_a_p_p_e_r_gaccdef5b45f3d1646f248304e02b00e54_cgraph.md5 new file mode 100644 index 0000000..a6644db --- /dev/null +++ b/DOCS/html/group___m_c_u___w_r_a_p_p_e_r_gaccdef5b45f3d1646f248304e02b00e54_cgraph.md5 @@ -0,0 +1 @@ +3ef605b5f7376aae8cddd36e29bd6593 \ No newline at end of file diff --git a/DOCS/html/mcu__wrapper_8c_accdef5b45f3d1646f248304e02b00e54_cgraph.png b/DOCS/html/group___m_c_u___w_r_a_p_p_e_r_gaccdef5b45f3d1646f248304e02b00e54_cgraph.png similarity index 100% rename from DOCS/html/mcu__wrapper_8c_accdef5b45f3d1646f248304e02b00e54_cgraph.png rename to DOCS/html/group___m_c_u___w_r_a_p_p_e_r_gaccdef5b45f3d1646f248304e02b00e54_cgraph.png diff --git a/DOCS/html/mcu__wrapper__conf_8h_ad3c4ea41584d0367dfbfb697f5e57456_cgraph.map b/DOCS/html/group___m_c_u___w_r_a_p_p_e_r_gad3c4ea41584d0367dfbfb697f5e57456_cgraph.map similarity index 68% rename from DOCS/html/mcu__wrapper__conf_8h_ad3c4ea41584d0367dfbfb697f5e57456_cgraph.map rename to DOCS/html/group___m_c_u___w_r_a_p_p_e_r_gad3c4ea41584d0367dfbfb697f5e57456_cgraph.map index 9e45408..4f944f7 100644 --- a/DOCS/html/mcu__wrapper__conf_8h_ad3c4ea41584d0367dfbfb697f5e57456_cgraph.map +++ b/DOCS/html/group___m_c_u___w_r_a_p_p_e_r_gad3c4ea41584d0367dfbfb697f5e57456_cgraph.map @@ -1,36 +1,36 @@ - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -56,8 +56,8 @@ - + - + diff --git a/DOCS/html/group___m_c_u___w_r_a_p_p_e_r_gad3c4ea41584d0367dfbfb697f5e57456_cgraph.md5 b/DOCS/html/group___m_c_u___w_r_a_p_p_e_r_gad3c4ea41584d0367dfbfb697f5e57456_cgraph.md5 new file mode 100644 index 0000000..c657aa1 --- /dev/null +++ b/DOCS/html/group___m_c_u___w_r_a_p_p_e_r_gad3c4ea41584d0367dfbfb697f5e57456_cgraph.md5 @@ -0,0 +1 @@ +ced1adab79d1ba1360fdc32759530d09 \ No newline at end of file diff --git a/DOCS/html/mcu__wrapper_8c_ad3c4ea41584d0367dfbfb697f5e57456_cgraph.png b/DOCS/html/group___m_c_u___w_r_a_p_p_e_r_gad3c4ea41584d0367dfbfb697f5e57456_cgraph.png similarity index 100% rename from DOCS/html/mcu__wrapper_8c_ad3c4ea41584d0367dfbfb697f5e57456_cgraph.png rename to DOCS/html/group___m_c_u___w_r_a_p_p_e_r_gad3c4ea41584d0367dfbfb697f5e57456_cgraph.png diff --git a/DOCS/html/group___m_c_u___w_r_a_p_p_e_r_gad6b7bb9233d746d7709276f9ea1914c2_cgraph.map b/DOCS/html/group___m_c_u___w_r_a_p_p_e_r_gad6b7bb9233d746d7709276f9ea1914c2_cgraph.map new file mode 100644 index 0000000..dc0d646 --- /dev/null +++ b/DOCS/html/group___m_c_u___w_r_a_p_p_e_r_gad6b7bb9233d746d7709276f9ea1914c2_cgraph.map @@ -0,0 +1,5 @@ + + + + + diff --git a/DOCS/html/group___m_c_u___w_r_a_p_p_e_r_gad6b7bb9233d746d7709276f9ea1914c2_cgraph.md5 b/DOCS/html/group___m_c_u___w_r_a_p_p_e_r_gad6b7bb9233d746d7709276f9ea1914c2_cgraph.md5 new file mode 100644 index 0000000..8a392db --- /dev/null +++ b/DOCS/html/group___m_c_u___w_r_a_p_p_e_r_gad6b7bb9233d746d7709276f9ea1914c2_cgraph.md5 @@ -0,0 +1 @@ +a2100a7c7b153ddfe6fc83318d5059f7 \ No newline at end of file diff --git a/DOCS/html/mcu__wrapper_8c_ad6b7bb9233d746d7709276f9ea1914c2_cgraph.png b/DOCS/html/group___m_c_u___w_r_a_p_p_e_r_gad6b7bb9233d746d7709276f9ea1914c2_cgraph.png similarity index 100% rename from DOCS/html/mcu__wrapper_8c_ad6b7bb9233d746d7709276f9ea1914c2_cgraph.png rename to DOCS/html/group___m_c_u___w_r_a_p_p_e_r_gad6b7bb9233d746d7709276f9ea1914c2_cgraph.png diff --git a/DOCS/html/group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html b/DOCS/html/group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html index 46c2775..71ed801 100644 --- a/DOCS/html/group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html +++ b/DOCS/html/group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html @@ -5,7 +5,7 @@ -STM MATLAB Simulator: PERIPH_VARS_FOR_DEBUG +STM MATLAB Simulator: Periphs Variables for Debugging @@ -14,6 +14,7 @@ + @@ -73,197 +74,197 @@ $(function() {
    Variables
    -
    PERIPH_VARS_FOR_DEBUG
    STM_SIMULATION
    +
    Periphs Variables for Debugging
    STM32 Simulation
    -

    Varables of peripheral registers for debug watches. +

    Переменные Ð´Ð»Ñ Ð´Ð¾Ñтупа к периферии в дебаге More...

    - + Collaboration diagram for PERIPH_VARS_FOR_DEBUG:
    + + Collaboration diagram for Periphs Variables for Debugging:
    - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - +

    Variables

    TIM_TypeDef * tim2 = TIM2
    TIM_TypeDef * tim2 = TIM2
     
    TIM_TypeDef * tim3 = TIM3
    TIM_TypeDef * tim3 = TIM3
     
    TIM_TypeDef * tim4 = TIM4
    TIM_TypeDef * tim4 = TIM4
     
    TIM_TypeDef * tim5 = TIM5
    TIM_TypeDef * tim5 = TIM5
     
    TIM_TypeDef * tim6 = TIM6
    TIM_TypeDef * tim6 = TIM6
     
    TIM_TypeDef * tim7 = TIM7
    TIM_TypeDef * tim7 = TIM7
     
    TIM_TypeDef * tim12 = TIM12
    TIM_TypeDef * tim12 = TIM12
     
    TIM_TypeDef * tim13 = TIM13
    TIM_TypeDef * tim13 = TIM13
     
    TIM_TypeDef * tim14 = TIM14
    TIM_TypeDef * tim14 = TIM14
     
    RTC_TypeDef * rtc = RTC
    RTC_TypeDef * rtc = RTC
     
    WWDG_TypeDef * wwdg = WWDG
    WWDG_TypeDef * wwdg = WWDG
     
    IWDG_TypeDef * iwdg = IWDG
    IWDG_TypeDef * iwdg = IWDG
     
    SPI_TypeDef * i2s2ext = I2S2ext
    SPI_TypeDef * i2s2ext = I2S2ext
     
    SPI_TypeDef * spi2 = SPI2
    SPI_TypeDef * spi2 = SPI2
     
    SPI_TypeDef * spi3 = SPI3
    SPI_TypeDef * spi3 = SPI3
     
    SPI_TypeDef * i2s3ext = I2S3ext
    SPI_TypeDef * i2s3ext = I2S3ext
     
    USART_TypeDef * usart2 = USART2
    USART_TypeDef * usart2 = USART2
     
    USART_TypeDef * usart3 = USART3
    USART_TypeDef * usart3 = USART3
     
    USART_TypeDef * uart4 = UART4
    USART_TypeDef * uart4 = UART4
     
    USART_TypeDef * uart5 = UART5
    USART_TypeDef * uart5 = UART5
     
    I2C_TypeDef * i2c1 = I2C1
    I2C_TypeDef * i2c1 = I2C1
     
    I2C_TypeDef * i2c2 = I2C2
    I2C_TypeDef * i2c2 = I2C2
     
    I2C_TypeDef * i2c3 = I2C3
    I2C_TypeDef * i2c3 = I2C3
     
    CAN_TypeDef * can1 = CAN1
    CAN_TypeDef * can1 = CAN1
     
    CAN_TypeDef * can2 = CAN2
    CAN_TypeDef * can2 = CAN2
     
    PWR_TypeDef * pwr = PWR
    PWR_TypeDef * pwr = PWR
     
    DAC_TypeDef * dac1 = DAC1
    DAC_TypeDef * dac1 = DAC1
     
    DAC_TypeDef * dac = DAC
    DAC_TypeDef * dac = DAC
     
    TIM_TypeDef * tim1 = TIM1
    TIM_TypeDef * tim1 = TIM1
     
    TIM_TypeDef * tim8 = TIM8
    TIM_TypeDef * tim8 = TIM8
     
    USART_TypeDef * usart1 = USART1
    USART_TypeDef * usart1 = USART1
     
    USART_TypeDef * usart6 = USART6
    USART_TypeDef * usart6 = USART6
     
    ADC_TypeDef * adc1 = ADC1
    ADC_TypeDef * adc1 = ADC1
     
    ADC_TypeDef * adc2 = ADC2
    ADC_TypeDef * adc2 = ADC2
     
    ADC_TypeDef * adc3 = ADC3
    ADC_TypeDef * adc3 = ADC3
     
    ADC_Common_TypeDef * adc123_common = ADC123_COMMON
    ADC_Common_TypeDef * adc123_common = ADC123_COMMON
     
    ADC_Common_TypeDef * adc = ADC123_COMMON
    ADC_Common_TypeDef * adc = ADC123_COMMON
     
    SDIO_TypeDef * sdio = SDIO
    SDIO_TypeDef * sdio = SDIO
     
    SPI_TypeDef * spi1 = SPI1
    SPI_TypeDef * spi1 = SPI1
     
    SYSCFG_TypeDef * syscfg = SYSCFG
    SYSCFG_TypeDef * syscfg = SYSCFG
     
    EXTI_TypeDef * exti = EXTI
    EXTI_TypeDef * exti = EXTI
     
    TIM_TypeDef * tim9 = TIM9
    TIM_TypeDef * tim9 = TIM9
     
    TIM_TypeDef * tim10 = TIM10
    TIM_TypeDef * tim10 = TIM10
     
    TIM_TypeDef * tim11 = TIM11
    TIM_TypeDef * tim11 = TIM11
     
    GPIO_TypeDef * gpioa = GPIOA
    GPIO_TypeDef * gpioa = GPIOA
     
    GPIO_TypeDef * gpiob = GPIOB
    GPIO_TypeDef * gpiob = GPIOB
     
    GPIO_TypeDef * gpioc = GPIOC
    GPIO_TypeDef * gpioc = GPIOC
     
    GPIO_TypeDef * gpiod = GPIOD
    GPIO_TypeDef * gpiod = GPIOD
     
    GPIO_TypeDef * gpioe = GPIOE
    GPIO_TypeDef * gpioe = GPIOE
     
    GPIO_TypeDef * gpiof = GPIOF
    GPIO_TypeDef * gpiof = GPIOF
     
    GPIO_TypeDef * gpiog = GPIOG
    GPIO_TypeDef * gpiog = GPIOG
     
    GPIO_TypeDef * gpioh = GPIOH
    GPIO_TypeDef * gpioh = GPIOH
     
    GPIO_TypeDef * gpioi = GPIOI
    GPIO_TypeDef * gpioi = GPIOI
     
    CRC_TypeDef * crc = CRC
    CRC_TypeDef * crc = CRC
     
    RCC_TypeDef * rcc = RCC
    RCC_TypeDef * rcc = RCC
     
    FLASH_TypeDef * flash_r = FLASH
    FLASH_TypeDef * flash_r = FLASH
     
    DMA_TypeDef * dma1 = DMA1
    DMA_TypeDef * dma1 = DMA1
     
    DMA_Stream_TypeDef * dma1_stream0 = DMA1_Stream0
    DMA_Stream_TypeDef * dma1_stream0 = DMA1_Stream0
     
    DMA_Stream_TypeDef * dma1_stream1 = DMA1_Stream1
    DMA_Stream_TypeDef * dma1_stream1 = DMA1_Stream1
     
    DMA_Stream_TypeDef * dma1_stream2 = DMA1_Stream2
    DMA_Stream_TypeDef * dma1_stream2 = DMA1_Stream2
     
    DMA_Stream_TypeDef * dma1_stream3 = DMA1_Stream3
    DMA_Stream_TypeDef * dma1_stream3 = DMA1_Stream3
     
    DMA_Stream_TypeDef * dma1_stream4 = DMA1_Stream4
    DMA_Stream_TypeDef * dma1_stream4 = DMA1_Stream4
     
    DMA_Stream_TypeDef * dma1_stream5 = DMA1_Stream5
    DMA_Stream_TypeDef * dma1_stream5 = DMA1_Stream5
     
    DMA_Stream_TypeDef * dma1_stream6 = DMA1_Stream6
    DMA_Stream_TypeDef * dma1_stream6 = DMA1_Stream6
     
    DMA_Stream_TypeDef * dma1_stream7 = DMA1_Stream7
    DMA_Stream_TypeDef * dma1_stream7 = DMA1_Stream7
     
    DMA_TypeDef * dma2 = DMA2
    DMA_TypeDef * dma2 = DMA2
     
    DMA_Stream_TypeDef * dma2_stream0 = DMA2_Stream0
    DMA_Stream_TypeDef * dma2_stream0 = DMA2_Stream0
     
    DMA_Stream_TypeDef * dma2_stream1 = DMA2_Stream1
    DMA_Stream_TypeDef * dma2_stream1 = DMA2_Stream1
     
    DMA_Stream_TypeDef * dma2_stream2 = DMA2_Stream2
    DMA_Stream_TypeDef * dma2_stream2 = DMA2_Stream2
     
    DMA_Stream_TypeDef * dma2_stream3 = DMA2_Stream3
    DMA_Stream_TypeDef * dma2_stream3 = DMA2_Stream3
     
    DMA_Stream_TypeDef * dma2_stream4 = DMA2_Stream4
    DMA_Stream_TypeDef * dma2_stream4 = DMA2_Stream4
     
    DMA_Stream_TypeDef * dma2_stream5 = DMA2_Stream5
    DMA_Stream_TypeDef * dma2_stream5 = DMA2_Stream5
     
    DMA_Stream_TypeDef * dma2_stream6 = DMA2_Stream6
    DMA_Stream_TypeDef * dma2_stream6 = DMA2_Stream6
     
    DMA_Stream_TypeDef * dma2_stream7 = DMA2_Stream7
    DMA_Stream_TypeDef * dma2_stream7 = DMA2_Stream7
     
    ETH_TypeDef * eth = ETH
    ETH_TypeDef * eth = ETH
     
    DCMI_TypeDef * dcmi = DCMI
    DCMI_TypeDef * dcmi = DCMI
     
    RNG_TypeDef * rng = RNG
    RNG_TypeDef * rng = RNG
     
    FSMC_Bank1_TypeDef * fsmc_bank1_r = FSMC_Bank1
    FSMC_Bank1_TypeDef * fsmc_bank1_r = FSMC_Bank1
     
    FSMC_Bank1E_TypeDef * fsmc_bank1e_r = FSMC_Bank1E
    FSMC_Bank1E_TypeDef * fsmc_bank1e_r = FSMC_Bank1E
     
    FSMC_Bank2_3_TypeDef * fsmc_bank2_3_r = FSMC_Bank2_3
    FSMC_Bank2_3_TypeDef * fsmc_bank2_3_r = FSMC_Bank2_3
     
    FSMC_Bank4_TypeDef * fsmc_bank4_r = FSMC_Bank4
    FSMC_Bank4_TypeDef * fsmc_bank4_r = FSMC_Bank4
     
    DBGMCU_TypeDef * dbgmcu = DBGMCU
    DBGMCU_TypeDef * dbgmcu = DBGMCU
     
    USB_OTG_GlobalTypeDef * usb_otg_fs_periph = USB_OTG_FS
    USB_OTG_GlobalTypeDef * usb_otg_fs_periph = USB_OTG_FS
     
    USB_OTG_GlobalTypeDef * usb_otg_hs_periph = USB_OTG_HS
    USB_OTG_GlobalTypeDef * usb_otg_hs_periph = USB_OTG_HS
     

    Detailed Description

    -

    Varables of peripheral registers for debug watches.

    +

    Переменные Ð´Ð»Ñ Ð´Ð¾Ñтупа к периферии в дебаге

    Variable Documentation

    ◆ tim2

    @@ -272,11 +273,13 @@ Variables
    - +
    TIM_TypeDef* tim2 = TIM2TIM_TypeDef* tim2 = TIM2
    +

    Definition at line 38 of file stm32f4xx_periph_registers.c.

    +
    @@ -286,11 +289,13 @@ Variables
    - +
    TIM_TypeDef* tim3 = TIM3TIM_TypeDef* tim3 = TIM3
    +

    Definition at line 39 of file stm32f4xx_periph_registers.c.

    +
    @@ -300,11 +305,13 @@ Variables
    - +
    TIM_TypeDef* tim4 = TIM4TIM_TypeDef* tim4 = TIM4
    +

    Definition at line 40 of file stm32f4xx_periph_registers.c.

    +
    @@ -314,11 +321,13 @@ Variables
    - +
    TIM_TypeDef* tim5 = TIM5TIM_TypeDef* tim5 = TIM5
    +

    Definition at line 41 of file stm32f4xx_periph_registers.c.

    +
    @@ -328,11 +337,13 @@ Variables
    - +
    TIM_TypeDef* tim6 = TIM6TIM_TypeDef* tim6 = TIM6
    +

    Definition at line 42 of file stm32f4xx_periph_registers.c.

    +
    @@ -342,11 +353,13 @@ Variables
    - +
    TIM_TypeDef* tim7 = TIM7TIM_TypeDef* tim7 = TIM7
    +

    Definition at line 43 of file stm32f4xx_periph_registers.c.

    +
    @@ -356,11 +369,13 @@ Variables
    - +
    TIM_TypeDef* tim12 = TIM12TIM_TypeDef* tim12 = TIM12
    +

    Definition at line 44 of file stm32f4xx_periph_registers.c.

    +
    @@ -370,11 +385,13 @@ Variables
    - +
    TIM_TypeDef* tim13 = TIM13TIM_TypeDef* tim13 = TIM13
    +

    Definition at line 45 of file stm32f4xx_periph_registers.c.

    +
    @@ -384,11 +401,13 @@ Variables
    - +
    TIM_TypeDef* tim14 = TIM14TIM_TypeDef* tim14 = TIM14
    +

    Definition at line 46 of file stm32f4xx_periph_registers.c.

    +
    @@ -398,11 +417,13 @@ Variables
    - +
    RTC_TypeDef* rtc = RTCRTC_TypeDef* rtc = RTC
    +

    Definition at line 47 of file stm32f4xx_periph_registers.c.

    +
    @@ -412,11 +433,13 @@ Variables
    - +
    WWDG_TypeDef* wwdg = WWDGWWDG_TypeDef* wwdg = WWDG
    +

    Definition at line 48 of file stm32f4xx_periph_registers.c.

    +
    @@ -426,11 +449,13 @@ Variables
    - +
    IWDG_TypeDef* iwdg = IWDGIWDG_TypeDef* iwdg = IWDG
    +

    Definition at line 49 of file stm32f4xx_periph_registers.c.

    +
    @@ -440,11 +465,13 @@ Variables
    - +
    SPI_TypeDef* i2s2ext = I2S2extSPI_TypeDef* i2s2ext = I2S2ext
    +

    Definition at line 50 of file stm32f4xx_periph_registers.c.

    +
    @@ -454,11 +481,13 @@ Variables
    - +
    SPI_TypeDef* spi2 = SPI2SPI_TypeDef* spi2 = SPI2
    +

    Definition at line 51 of file stm32f4xx_periph_registers.c.

    +
    @@ -468,11 +497,13 @@ Variables
    - +
    SPI_TypeDef* spi3 = SPI3SPI_TypeDef* spi3 = SPI3
    +

    Definition at line 52 of file stm32f4xx_periph_registers.c.

    +
    @@ -482,11 +513,13 @@ Variables
    - +
    SPI_TypeDef* i2s3ext = I2S3extSPI_TypeDef* i2s3ext = I2S3ext
    +

    Definition at line 53 of file stm32f4xx_periph_registers.c.

    +
    @@ -496,11 +529,13 @@ Variables
    - +
    USART_TypeDef* usart2 = USART2USART_TypeDef* usart2 = USART2
    +

    Definition at line 54 of file stm32f4xx_periph_registers.c.

    +
    @@ -510,11 +545,13 @@ Variables
    - +
    USART_TypeDef* usart3 = USART3USART_TypeDef* usart3 = USART3
    +

    Definition at line 55 of file stm32f4xx_periph_registers.c.

    +
    @@ -524,11 +561,13 @@ Variables
    - +
    USART_TypeDef* uart4 = UART4USART_TypeDef* uart4 = UART4
    +

    Definition at line 56 of file stm32f4xx_periph_registers.c.

    +
    @@ -538,11 +577,13 @@ Variables
    - +
    USART_TypeDef* uart5 = UART5USART_TypeDef* uart5 = UART5
    +

    Definition at line 57 of file stm32f4xx_periph_registers.c.

    +
    @@ -552,11 +593,13 @@ Variables
    - +
    I2C_TypeDef* i2c1 = I2C1I2C_TypeDef* i2c1 = I2C1
    +

    Definition at line 58 of file stm32f4xx_periph_registers.c.

    +
    @@ -566,11 +609,13 @@ Variables
    - +
    I2C_TypeDef* i2c2 = I2C2I2C_TypeDef* i2c2 = I2C2
    +

    Definition at line 59 of file stm32f4xx_periph_registers.c.

    +
    @@ -580,11 +625,13 @@ Variables
    - +
    I2C_TypeDef* i2c3 = I2C3I2C_TypeDef* i2c3 = I2C3
    +

    Definition at line 60 of file stm32f4xx_periph_registers.c.

    +
    @@ -594,11 +641,13 @@ Variables
    - +
    CAN_TypeDef* can1 = CAN1CAN_TypeDef* can1 = CAN1
    +

    Definition at line 61 of file stm32f4xx_periph_registers.c.

    +
    @@ -608,11 +657,13 @@ Variables
    - +
    CAN_TypeDef* can2 = CAN2CAN_TypeDef* can2 = CAN2
    +

    Definition at line 62 of file stm32f4xx_periph_registers.c.

    +
    @@ -622,11 +673,13 @@ Variables
    - +
    PWR_TypeDef* pwr = PWRPWR_TypeDef* pwr = PWR
    +

    Definition at line 63 of file stm32f4xx_periph_registers.c.

    +
    @@ -636,11 +689,13 @@ Variables
    - +
    DAC_TypeDef* dac1 = DAC1DAC_TypeDef* dac1 = DAC1
    +

    Definition at line 64 of file stm32f4xx_periph_registers.c.

    +
    @@ -650,11 +705,13 @@ Variables
    - +
    DAC_TypeDef* dac = DACDAC_TypeDef* dac = DAC
    +

    Definition at line 65 of file stm32f4xx_periph_registers.c.

    +
    @@ -664,11 +721,13 @@ Variables
    - +
    TIM_TypeDef* tim1 = TIM1TIM_TypeDef* tim1 = TIM1
    +

    Definition at line 66 of file stm32f4xx_periph_registers.c.

    +
    @@ -678,11 +737,13 @@ Variables
    - +
    TIM_TypeDef* tim8 = TIM8TIM_TypeDef* tim8 = TIM8
    +

    Definition at line 67 of file stm32f4xx_periph_registers.c.

    +
    @@ -692,11 +753,13 @@ Variables
    - +
    USART_TypeDef* usart1 = USART1USART_TypeDef* usart1 = USART1
    +

    Definition at line 68 of file stm32f4xx_periph_registers.c.

    +
    @@ -706,11 +769,13 @@ Variables
    - +
    USART_TypeDef* usart6 = USART6USART_TypeDef* usart6 = USART6
    +

    Definition at line 69 of file stm32f4xx_periph_registers.c.

    +
    @@ -720,11 +785,13 @@ Variables
    - +
    ADC_TypeDef* adc1 = ADC1ADC_TypeDef* adc1 = ADC1
    +

    Definition at line 70 of file stm32f4xx_periph_registers.c.

    +
    @@ -734,11 +801,13 @@ Variables
    - +
    ADC_TypeDef* adc2 = ADC2ADC_TypeDef* adc2 = ADC2
    +

    Definition at line 71 of file stm32f4xx_periph_registers.c.

    +
    @@ -748,11 +817,13 @@ Variables
    - +
    ADC_TypeDef* adc3 = ADC3ADC_TypeDef* adc3 = ADC3
    +

    Definition at line 72 of file stm32f4xx_periph_registers.c.

    +
    @@ -762,11 +833,13 @@ Variables
    - +
    ADC_Common_TypeDef* adc123_common = ADC123_COMMONADC_Common_TypeDef* adc123_common = ADC123_COMMON
    +

    Definition at line 73 of file stm32f4xx_periph_registers.c.

    +
    @@ -776,11 +849,13 @@ Variables
    - +
    ADC_Common_TypeDef* adc = ADC123_COMMONADC_Common_TypeDef* adc = ADC123_COMMON
    +

    Definition at line 74 of file stm32f4xx_periph_registers.c.

    +
    @@ -790,11 +865,13 @@ Variables
    - +
    SDIO_TypeDef* sdio = SDIOSDIO_TypeDef* sdio = SDIO
    +

    Definition at line 75 of file stm32f4xx_periph_registers.c.

    +
    @@ -804,11 +881,13 @@ Variables
    - +
    SPI_TypeDef* spi1 = SPI1SPI_TypeDef* spi1 = SPI1
    +

    Definition at line 76 of file stm32f4xx_periph_registers.c.

    +
    @@ -818,11 +897,13 @@ Variables
    - +
    SYSCFG_TypeDef* syscfg = SYSCFGSYSCFG_TypeDef* syscfg = SYSCFG
    +

    Definition at line 77 of file stm32f4xx_periph_registers.c.

    +
    @@ -832,11 +913,13 @@ Variables
    - +
    EXTI_TypeDef* exti = EXTIEXTI_TypeDef* exti = EXTI
    +

    Definition at line 78 of file stm32f4xx_periph_registers.c.

    +
    @@ -846,11 +929,13 @@ Variables
    - +
    TIM_TypeDef* tim9 = TIM9TIM_TypeDef* tim9 = TIM9
    +

    Definition at line 79 of file stm32f4xx_periph_registers.c.

    +
    @@ -860,11 +945,13 @@ Variables
    - +
    TIM_TypeDef* tim10 = TIM10TIM_TypeDef* tim10 = TIM10
    +

    Definition at line 80 of file stm32f4xx_periph_registers.c.

    +
    @@ -874,11 +961,13 @@ Variables
    - +
    TIM_TypeDef* tim11 = TIM11TIM_TypeDef* tim11 = TIM11
    +

    Definition at line 81 of file stm32f4xx_periph_registers.c.

    +
    @@ -888,11 +977,13 @@ Variables
    - +
    GPIO_TypeDef* gpioa = GPIOAGPIO_TypeDef* gpioa = GPIOA
    +

    Definition at line 82 of file stm32f4xx_periph_registers.c.

    +
    @@ -902,11 +993,13 @@ Variables
    - +
    GPIO_TypeDef* gpiob = GPIOBGPIO_TypeDef* gpiob = GPIOB
    +

    Definition at line 83 of file stm32f4xx_periph_registers.c.

    +
    @@ -916,11 +1009,13 @@ Variables
    - +
    GPIO_TypeDef* gpioc = GPIOCGPIO_TypeDef* gpioc = GPIOC
    +

    Definition at line 84 of file stm32f4xx_periph_registers.c.

    +
    @@ -930,11 +1025,13 @@ Variables
    - +
    GPIO_TypeDef* gpiod = GPIODGPIO_TypeDef* gpiod = GPIOD
    +

    Definition at line 85 of file stm32f4xx_periph_registers.c.

    +
    @@ -944,11 +1041,13 @@ Variables
    - +
    GPIO_TypeDef* gpioe = GPIOEGPIO_TypeDef* gpioe = GPIOE
    +

    Definition at line 86 of file stm32f4xx_periph_registers.c.

    +
    @@ -958,11 +1057,13 @@ Variables
    - +
    GPIO_TypeDef* gpiof = GPIOFGPIO_TypeDef* gpiof = GPIOF
    +

    Definition at line 87 of file stm32f4xx_periph_registers.c.

    +
    @@ -972,11 +1073,13 @@ Variables
    - +
    GPIO_TypeDef* gpiog = GPIOGGPIO_TypeDef* gpiog = GPIOG
    +

    Definition at line 88 of file stm32f4xx_periph_registers.c.

    +
    @@ -986,11 +1089,13 @@ Variables
    - +
    GPIO_TypeDef* gpioh = GPIOHGPIO_TypeDef* gpioh = GPIOH
    +

    Definition at line 89 of file stm32f4xx_periph_registers.c.

    +
    @@ -1000,11 +1105,13 @@ Variables
    - +
    GPIO_TypeDef* gpioi = GPIOIGPIO_TypeDef* gpioi = GPIOI
    +

    Definition at line 90 of file stm32f4xx_periph_registers.c.

    +
    @@ -1014,11 +1121,13 @@ Variables
    - +
    CRC_TypeDef* crc = CRCCRC_TypeDef* crc = CRC
    +

    Definition at line 91 of file stm32f4xx_periph_registers.c.

    +
    @@ -1028,11 +1137,13 @@ Variables
    - +
    RCC_TypeDef* rcc = RCCRCC_TypeDef* rcc = RCC
    +

    Definition at line 92 of file stm32f4xx_periph_registers.c.

    +
    @@ -1042,11 +1153,13 @@ Variables
    - +
    FLASH_TypeDef* flash_r = FLASHFLASH_TypeDef* flash_r = FLASH
    +

    Definition at line 93 of file stm32f4xx_periph_registers.c.

    +
    @@ -1056,11 +1169,13 @@ Variables
    - +
    DMA_TypeDef* dma1 = DMA1DMA_TypeDef* dma1 = DMA1
    +

    Definition at line 94 of file stm32f4xx_periph_registers.c.

    +
    @@ -1070,11 +1185,13 @@ Variables
    - +
    DMA_Stream_TypeDef* dma1_stream0 = DMA1_Stream0DMA_Stream_TypeDef* dma1_stream0 = DMA1_Stream0
    +

    Definition at line 95 of file stm32f4xx_periph_registers.c.

    +
    @@ -1084,11 +1201,13 @@ Variables
    - +
    DMA_Stream_TypeDef* dma1_stream1 = DMA1_Stream1DMA_Stream_TypeDef* dma1_stream1 = DMA1_Stream1
    +

    Definition at line 96 of file stm32f4xx_periph_registers.c.

    +
    @@ -1098,11 +1217,13 @@ Variables
    - +
    DMA_Stream_TypeDef* dma1_stream2 = DMA1_Stream2DMA_Stream_TypeDef* dma1_stream2 = DMA1_Stream2
    +

    Definition at line 97 of file stm32f4xx_periph_registers.c.

    +
    @@ -1112,11 +1233,13 @@ Variables
    - +
    DMA_Stream_TypeDef* dma1_stream3 = DMA1_Stream3DMA_Stream_TypeDef* dma1_stream3 = DMA1_Stream3
    +

    Definition at line 98 of file stm32f4xx_periph_registers.c.

    +
    @@ -1126,11 +1249,13 @@ Variables
    - +
    DMA_Stream_TypeDef* dma1_stream4 = DMA1_Stream4DMA_Stream_TypeDef* dma1_stream4 = DMA1_Stream4
    +

    Definition at line 99 of file stm32f4xx_periph_registers.c.

    +
    @@ -1140,11 +1265,13 @@ Variables
    - +
    DMA_Stream_TypeDef* dma1_stream5 = DMA1_Stream5DMA_Stream_TypeDef* dma1_stream5 = DMA1_Stream5
    +

    Definition at line 100 of file stm32f4xx_periph_registers.c.

    +
    @@ -1154,11 +1281,13 @@ Variables
    - +
    DMA_Stream_TypeDef* dma1_stream6 = DMA1_Stream6DMA_Stream_TypeDef* dma1_stream6 = DMA1_Stream6
    +

    Definition at line 101 of file stm32f4xx_periph_registers.c.

    +
    @@ -1168,11 +1297,13 @@ Variables
    - +
    DMA_Stream_TypeDef* dma1_stream7 = DMA1_Stream7DMA_Stream_TypeDef* dma1_stream7 = DMA1_Stream7
    +

    Definition at line 102 of file stm32f4xx_periph_registers.c.

    +
    @@ -1182,11 +1313,13 @@ Variables
    - +
    DMA_TypeDef* dma2 = DMA2DMA_TypeDef* dma2 = DMA2
    +

    Definition at line 103 of file stm32f4xx_periph_registers.c.

    +
    @@ -1196,11 +1329,13 @@ Variables
    - +
    DMA_Stream_TypeDef* dma2_stream0 = DMA2_Stream0DMA_Stream_TypeDef* dma2_stream0 = DMA2_Stream0
    +

    Definition at line 104 of file stm32f4xx_periph_registers.c.

    +
    @@ -1210,11 +1345,13 @@ Variables
    - +
    DMA_Stream_TypeDef* dma2_stream1 = DMA2_Stream1DMA_Stream_TypeDef* dma2_stream1 = DMA2_Stream1
    +

    Definition at line 105 of file stm32f4xx_periph_registers.c.

    +
    @@ -1224,11 +1361,13 @@ Variables
    - +
    DMA_Stream_TypeDef* dma2_stream2 = DMA2_Stream2DMA_Stream_TypeDef* dma2_stream2 = DMA2_Stream2
    +

    Definition at line 106 of file stm32f4xx_periph_registers.c.

    +
    @@ -1238,11 +1377,13 @@ Variables
    - +
    DMA_Stream_TypeDef* dma2_stream3 = DMA2_Stream3DMA_Stream_TypeDef* dma2_stream3 = DMA2_Stream3
    +

    Definition at line 107 of file stm32f4xx_periph_registers.c.

    +
    @@ -1252,11 +1393,13 @@ Variables
    - +
    DMA_Stream_TypeDef* dma2_stream4 = DMA2_Stream4DMA_Stream_TypeDef* dma2_stream4 = DMA2_Stream4
    +

    Definition at line 108 of file stm32f4xx_periph_registers.c.

    +
    @@ -1266,11 +1409,13 @@ Variables
    - +
    DMA_Stream_TypeDef* dma2_stream5 = DMA2_Stream5DMA_Stream_TypeDef* dma2_stream5 = DMA2_Stream5
    +

    Definition at line 109 of file stm32f4xx_periph_registers.c.

    +
    @@ -1280,11 +1425,13 @@ Variables
    - +
    DMA_Stream_TypeDef* dma2_stream6 = DMA2_Stream6DMA_Stream_TypeDef* dma2_stream6 = DMA2_Stream6
    +

    Definition at line 110 of file stm32f4xx_periph_registers.c.

    +
    @@ -1294,11 +1441,13 @@ Variables
    - +
    DMA_Stream_TypeDef* dma2_stream7 = DMA2_Stream7DMA_Stream_TypeDef* dma2_stream7 = DMA2_Stream7
    +

    Definition at line 111 of file stm32f4xx_periph_registers.c.

    +
    @@ -1308,11 +1457,13 @@ Variables
    - +
    ETH_TypeDef* eth = ETHETH_TypeDef* eth = ETH
    +

    Definition at line 112 of file stm32f4xx_periph_registers.c.

    +
    @@ -1322,11 +1473,13 @@ Variables
    - +
    DCMI_TypeDef* dcmi = DCMIDCMI_TypeDef* dcmi = DCMI
    +

    Definition at line 113 of file stm32f4xx_periph_registers.c.

    +
    @@ -1336,11 +1489,13 @@ Variables
    - +
    RNG_TypeDef* rng = RNGRNG_TypeDef* rng = RNG
    +

    Definition at line 114 of file stm32f4xx_periph_registers.c.

    +
    @@ -1350,11 +1505,13 @@ Variables
    - +
    FSMC_Bank1_TypeDef* fsmc_bank1_r = FSMC_Bank1FSMC_Bank1_TypeDef* fsmc_bank1_r = FSMC_Bank1
    +

    Definition at line 115 of file stm32f4xx_periph_registers.c.

    +
    @@ -1364,11 +1521,13 @@ Variables
    - +
    FSMC_Bank1E_TypeDef* fsmc_bank1e_r = FSMC_Bank1EFSMC_Bank1E_TypeDef* fsmc_bank1e_r = FSMC_Bank1E
    +

    Definition at line 116 of file stm32f4xx_periph_registers.c.

    +
    @@ -1378,11 +1537,13 @@ Variables
    - +
    FSMC_Bank2_3_TypeDef* fsmc_bank2_3_r = FSMC_Bank2_3FSMC_Bank2_3_TypeDef* fsmc_bank2_3_r = FSMC_Bank2_3
    +

    Definition at line 117 of file stm32f4xx_periph_registers.c.

    +
    @@ -1392,11 +1553,13 @@ Variables
    - +
    FSMC_Bank4_TypeDef* fsmc_bank4_r = FSMC_Bank4FSMC_Bank4_TypeDef* fsmc_bank4_r = FSMC_Bank4
    +

    Definition at line 118 of file stm32f4xx_periph_registers.c.

    +
    @@ -1406,11 +1569,13 @@ Variables
    - +
    DBGMCU_TypeDef* dbgmcu = DBGMCUDBGMCU_TypeDef* dbgmcu = DBGMCU
    +

    Definition at line 119 of file stm32f4xx_periph_registers.c.

    +
    @@ -1420,11 +1585,13 @@ Variables
    - +
    USB_OTG_GlobalTypeDef* usb_otg_fs_periph = USB_OTG_FSUSB_OTG_GlobalTypeDef* usb_otg_fs_periph = USB_OTG_FS
    +

    Definition at line 120 of file stm32f4xx_periph_registers.c.

    +
    @@ -1434,11 +1601,13 @@ Variables
    - +
    USB_OTG_GlobalTypeDef* usb_otg_hs_periph = USB_OTG_HSUSB_OTG_GlobalTypeDef* usb_otg_hs_periph = USB_OTG_HS
    +

    Definition at line 121 of file stm32f4xx_periph_registers.c.

    +
    diff --git a/DOCS/html/group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.map b/DOCS/html/group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.map index f7b24ec..e4713b9 100644 --- a/DOCS/html/group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.map +++ b/DOCS/html/group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.map @@ -1,4 +1,4 @@ - - - + + + diff --git a/DOCS/html/group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.md5 b/DOCS/html/group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.md5 index f043e02..62aff46 100644 --- a/DOCS/html/group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.md5 +++ b/DOCS/html/group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.md5 @@ -1 +1 @@ -b229d7a69c84afb1340e152c1be30423 \ No newline at end of file +a90e39ca536a1b2842adb8e67193a510 \ No newline at end of file diff --git a/DOCS/html/group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.png b/DOCS/html/group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.png index a15d84339093c983ad64c538cd409f35fc68817a..110a046a989c80d40434f4576b59946c6408671f 100644 GIT binary patch literal 1526 zcmVG&gM zVNuxBGOt7=F6FUvc#Kpx0mdoYV@*+YmL_}F&fg~bQV1XneQec53 zB2r+1BqCDS8pS?3I=Ux>*pHD6rK75oibX=}P&pBT3L@R7TZ*QJUJxc|SnP~HbQWD=AXRlyiD+26bCfu8fRlWOjv zif$KPgCxq>Y&KKAp~WgHW5NPSWT-65{~qn-vVYslbcIZ|PPM$$3}uAS+2ZJS=CNnD%QHtk$unC8*-`fOs^Vu2)rytiRqc)nt>KoY_1fEse}s(o$Iq*!fwO|ssTYwo^I?`3RXV+<^iM23bw zfPI}Z%1%E+wrex(L8myVD*)fe zP9!v&V&PI)T-vC5kA36zX{U>m!|h~VdXPd0R8^&1-dv~JwkwWqo6R!aI+wfwDBBL9 zonOpcG+seH$><{hZ=#;1esrI}>2o^RY-@AP(bwr`d;g||sjHnye!AD;>vw9~*2Y$s zWICN53Lzfb?9impm~0Eki-2yOE~e``T^k=vUF}qPI{uCd0Q;zm;v)br0r(rho%MPaM;bM6JxE#4#^s=F76#pc zZPGh4DGauGx7YQ3GYIu&(kE_JRX9C8y$|3U0I#-I-;p$FdksLe3#MmhXP8VTv3CDI zJiX3akW*|AJ(u2G_8lwl)JCU;5I8tE_;ImVEC75A;3L$%$G>1!Ab$t&MZgrb_V)H} z#VkY=UeHnOSW+JZ(dCdzu@pj70DfLSz69_tfKLH@fO?Qdcm44X0N)Lerqu54ZmeC? z$Rv5AxbF12tEi<=^jxJ<93}n%@YDJ+MLlx;8G!fk>`n+?k95%YBaWLGL!Qdtrjhv| zgEY<(LDcerzC1-e>iq_Qw<6~_HM`BG+D6 z&R8IcGLdU9EN48$CQ6LSHALUNNs}+l3Kc(P>_HMm)-E2pFRoH;V>;)eDyA&H%N&xX z@pGXpknGMAh3Dgo!TJoMxU6dzU|pNs>&RAtEQ;cCwOXB=pP$FbhZ0c~#bxXqC@j;j zstpl87s-D3m&jF0Gm59q<+R;b{FFqQQJjd<=HolNUE}9~qu4}53M`OBL<%gBL_`WK zkVHfZ9HgO9y1Kf;a=DD124&*r=0>`l1(HUms;ZOg>+9HQP-cpvcoI7YA|fIpA|fIp cBD!7v1#^J}?K%7#^Z)<=07*qoM6N<$f*O9v3zZ5XiBL{Q4GJ0x0000DNk~Le0004z0000b2nGNE0D}$GfRP~-e+0@& zL_t(|obBDeZzDw%2k`H%?kq@wL|Q;xXi`9hs16A#L<GVl`+pT7!EX(d@S@tkoT9mMR0KSi%gbn_U6Pa5smq!3Tu5Vi_B9-ZM>OCP!*JLt@ zokDLrJ3H9k-j1CHQ4-G1&ahZ4*0$#nav>t34Z$KpL`2qDM2LvU8jA=Ke-T+@5g{TX zYb+u}L}X37#Me}ot$l70MNw$?soGRO>(1Y{Uz&^RTqdz~ZB5VFcASnR2UYv7oJ_8* z10w+M1Go?1I{-h23fzZoNppQEeA}|;s-5IKRXfSKn{8A}^L5)z+o^KW#p}wot*!Lq z1t!rjRA5@e)X(dli+m60ZfpD#gtBWtmwQteW#pybiYMYB|D~Y3vC23>( zSWB;gEe>aG09|3I3RKrNk6s7x1%TfH`~u)}{9iz5V5*{^602DCf6>;7hxo8;s5osx zTmxsrSt_Qlc$=@vf$Oi6ftFJ>j0Pq@szX9AX_ubYUL-e22idCvyU1ujn zq}kC%7%mxPE^V4aSRsd*Jj8nmz(-gOSG|Q*;TVCy~cm&{GTpt=8sgGFm zgY%?>E-o&NkC8mFr4!g)=W!W7#*m8iKB_v-KJyT^LU!7r=R}(4FwLclm*FhwimMQY zluM;5Y|UY^)ZUHk?(WWykB=WTH9MoW1qRalSYMqK`c=2>W0D%_YC;oUS7*gAq+HsBUJ2&Wp8&ooZ?6LQ z0KgclN%d!Fe^>Gtz>mHYR2hw=ZMkgKy|4kvZRR!y|` zU5eXwZVBCSe_eTbSTyh(fNuf3QQp1+FfaE#a~X*IlFW^$+7F2?r%(mLXB^di(=A>0 zeGR-!tk<`P79tnvL_ka8VTE<-cO)mcPDlm-?NA|kTJ zB0@w&Y1UXoh=|CVc4D0qNwn$C&(E<~EMliYl!U9RE9LgJB9iC%e7Rg6ot&I_Pm0o( z=lQ(5)i4!Baddfk89NQ4q~v-2Bz6u&L_|bHL_|bHL_|a}{0lM72TO)z-PiyC002ov JPDHLkV1fmCc60y$ diff --git a/DOCS/html/group___peripheral___registers___bits___definition.html b/DOCS/html/group___peripheral___registers___bits___definition.html deleted file mode 100644 index 519392e..0000000 --- a/DOCS/html/group___peripheral___registers___bits___definition.html +++ /dev/null @@ -1,208536 +0,0 @@ - - - - - - - -STM MATLAB Simulator: Peripheral_Registers_Bits_Definition - - - - - - - - - - - -
    -
    - - - - - - -
    -
    STM MATLAB Simulator -
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    Peripheral_Registers_Bits_Definition
    CMSIS_Device » Stm32f407xx » Peripheral_memory_map » Exported_constants
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    - + Collaboration diagram for Peripheral_Registers_Bits_Definition:
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    -
    - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 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    -Macros

    #define ADC_MULTIMODE_SUPPORT
     
    #define ADC_SR_AWD_Pos   (0U)
     
    #define ADC_SR_AWD_Msk   (0x1UL << ADC_SR_AWD_Pos)
     
    #define ADC_SR_AWD   ADC_SR_AWD_Msk
     
    #define ADC_SR_EOC_Pos   (1U)
     
    #define ADC_SR_EOC_Msk   (0x1UL << ADC_SR_EOC_Pos)
     
    #define ADC_SR_EOC   ADC_SR_EOC_Msk
     
    #define ADC_SR_JEOC_Pos   (2U)
     
    #define ADC_SR_JEOC_Msk   (0x1UL << ADC_SR_JEOC_Pos)
     
    #define ADC_SR_JEOC   ADC_SR_JEOC_Msk
     
    #define ADC_SR_JSTRT_Pos   (3U)
     
    #define ADC_SR_JSTRT_Msk   (0x1UL << ADC_SR_JSTRT_Pos)
     
    #define ADC_SR_JSTRT   ADC_SR_JSTRT_Msk
     
    #define ADC_SR_STRT_Pos   (4U)
     
    #define ADC_SR_STRT_Msk   (0x1UL << ADC_SR_STRT_Pos)
     
    #define ADC_SR_STRT   ADC_SR_STRT_Msk
     
    #define ADC_SR_OVR_Pos   (5U)
     
    #define ADC_SR_OVR_Msk   (0x1UL << ADC_SR_OVR_Pos)
     
    #define ADC_SR_OVR   ADC_SR_OVR_Msk
     
    #define ADC_CR1_AWDCH_Pos   (0U)
     
    #define ADC_CR1_AWDCH_Msk   (0x1FUL << ADC_CR1_AWDCH_Pos)
     
    #define ADC_CR1_AWDCH   ADC_CR1_AWDCH_Msk
     
    #define ADC_CR1_AWDCH_0   (0x01UL << ADC_CR1_AWDCH_Pos)
     
    #define ADC_CR1_AWDCH_1   (0x02UL << ADC_CR1_AWDCH_Pos)
     
    #define ADC_CR1_AWDCH_2   (0x04UL << ADC_CR1_AWDCH_Pos)
     
    #define ADC_CR1_AWDCH_3   (0x08UL << ADC_CR1_AWDCH_Pos)
     
    #define ADC_CR1_AWDCH_4   (0x10UL << ADC_CR1_AWDCH_Pos)
     
    #define ADC_CR1_EOCIE_Pos   (5U)
     
    #define ADC_CR1_EOCIE_Msk   (0x1UL << ADC_CR1_EOCIE_Pos)
     
    #define ADC_CR1_EOCIE   ADC_CR1_EOCIE_Msk
     
    #define ADC_CR1_AWDIE_Pos   (6U)
     
    #define ADC_CR1_AWDIE_Msk   (0x1UL << ADC_CR1_AWDIE_Pos)
     
    #define ADC_CR1_AWDIE   ADC_CR1_AWDIE_Msk
     
    #define ADC_CR1_JEOCIE_Pos   (7U)
     
    #define ADC_CR1_JEOCIE_Msk   (0x1UL << ADC_CR1_JEOCIE_Pos)
     
    #define ADC_CR1_JEOCIE   ADC_CR1_JEOCIE_Msk
     
    #define ADC_CR1_SCAN_Pos   (8U)
     
    #define ADC_CR1_SCAN_Msk   (0x1UL << ADC_CR1_SCAN_Pos)
     
    #define ADC_CR1_SCAN   ADC_CR1_SCAN_Msk
     
    #define ADC_CR1_AWDSGL_Pos   (9U)
     
    #define ADC_CR1_AWDSGL_Msk   (0x1UL << ADC_CR1_AWDSGL_Pos)
     
    #define ADC_CR1_AWDSGL   ADC_CR1_AWDSGL_Msk
     
    #define ADC_CR1_JAUTO_Pos   (10U)
     
    #define ADC_CR1_JAUTO_Msk   (0x1UL << ADC_CR1_JAUTO_Pos)
     
    #define ADC_CR1_JAUTO   ADC_CR1_JAUTO_Msk
     
    #define ADC_CR1_DISCEN_Pos   (11U)
     
    #define ADC_CR1_DISCEN_Msk   (0x1UL << ADC_CR1_DISCEN_Pos)
     
    #define ADC_CR1_DISCEN   ADC_CR1_DISCEN_Msk
     
    #define ADC_CR1_JDISCEN_Pos   (12U)
     
    #define ADC_CR1_JDISCEN_Msk   (0x1UL << ADC_CR1_JDISCEN_Pos)
     
    #define ADC_CR1_JDISCEN   ADC_CR1_JDISCEN_Msk
     
    #define ADC_CR1_DISCNUM_Pos   (13U)
     
    #define ADC_CR1_DISCNUM_Msk   (0x7UL << ADC_CR1_DISCNUM_Pos)
     
    #define ADC_CR1_DISCNUM   ADC_CR1_DISCNUM_Msk
     
    #define ADC_CR1_DISCNUM_0   (0x1UL << ADC_CR1_DISCNUM_Pos)
     
    #define ADC_CR1_DISCNUM_1   (0x2UL << ADC_CR1_DISCNUM_Pos)
     
    #define ADC_CR1_DISCNUM_2   (0x4UL << ADC_CR1_DISCNUM_Pos)
     
    #define ADC_CR1_JAWDEN_Pos   (22U)
     
    #define ADC_CR1_JAWDEN_Msk   (0x1UL << ADC_CR1_JAWDEN_Pos)
     
    #define ADC_CR1_JAWDEN   ADC_CR1_JAWDEN_Msk
     
    #define ADC_CR1_AWDEN_Pos   (23U)
     
    #define ADC_CR1_AWDEN_Msk   (0x1UL << ADC_CR1_AWDEN_Pos)
     
    #define ADC_CR1_AWDEN   ADC_CR1_AWDEN_Msk
     
    #define ADC_CR1_RES_Pos   (24U)
     
    #define ADC_CR1_RES_Msk   (0x3UL << ADC_CR1_RES_Pos)
     
    #define ADC_CR1_RES   ADC_CR1_RES_Msk
     
    #define ADC_CR1_RES_0   (0x1UL << ADC_CR1_RES_Pos)
     
    #define ADC_CR1_RES_1   (0x2UL << ADC_CR1_RES_Pos)
     
    #define ADC_CR1_OVRIE_Pos   (26U)
     
    #define ADC_CR1_OVRIE_Msk   (0x1UL << ADC_CR1_OVRIE_Pos)
     
    #define ADC_CR1_OVRIE   ADC_CR1_OVRIE_Msk
     
    #define ADC_CR2_ADON_Pos   (0U)
     
    #define ADC_CR2_ADON_Msk   (0x1UL << ADC_CR2_ADON_Pos)
     
    #define ADC_CR2_ADON   ADC_CR2_ADON_Msk
     
    #define ADC_CR2_CONT_Pos   (1U)
     
    #define ADC_CR2_CONT_Msk   (0x1UL << ADC_CR2_CONT_Pos)
     
    #define ADC_CR2_CONT   ADC_CR2_CONT_Msk
     
    #define ADC_CR2_DMA_Pos   (8U)
     
    #define ADC_CR2_DMA_Msk   (0x1UL << ADC_CR2_DMA_Pos)
     
    #define ADC_CR2_DMA   ADC_CR2_DMA_Msk
     
    #define ADC_CR2_DDS_Pos   (9U)
     
    #define ADC_CR2_DDS_Msk   (0x1UL << ADC_CR2_DDS_Pos)
     
    #define ADC_CR2_DDS   ADC_CR2_DDS_Msk
     
    #define ADC_CR2_EOCS_Pos   (10U)
     
    #define ADC_CR2_EOCS_Msk   (0x1UL << ADC_CR2_EOCS_Pos)
     
    #define ADC_CR2_EOCS   ADC_CR2_EOCS_Msk
     
    #define ADC_CR2_ALIGN_Pos   (11U)
     
    #define ADC_CR2_ALIGN_Msk   (0x1UL << ADC_CR2_ALIGN_Pos)
     
    #define ADC_CR2_ALIGN   ADC_CR2_ALIGN_Msk
     
    #define ADC_CR2_JEXTSEL_Pos   (16U)
     
    #define ADC_CR2_JEXTSEL_Msk   (0xFUL << ADC_CR2_JEXTSEL_Pos)
     
    #define ADC_CR2_JEXTSEL   ADC_CR2_JEXTSEL_Msk
     
    #define ADC_CR2_JEXTSEL_0   (0x1UL << ADC_CR2_JEXTSEL_Pos)
     
    #define ADC_CR2_JEXTSEL_1   (0x2UL << ADC_CR2_JEXTSEL_Pos)
     
    #define ADC_CR2_JEXTSEL_2   (0x4UL << ADC_CR2_JEXTSEL_Pos)
     
    #define ADC_CR2_JEXTSEL_3   (0x8UL << ADC_CR2_JEXTSEL_Pos)
     
    #define ADC_CR2_JEXTEN_Pos   (20U)
     
    #define ADC_CR2_JEXTEN_Msk   (0x3UL << ADC_CR2_JEXTEN_Pos)
     
    #define ADC_CR2_JEXTEN   ADC_CR2_JEXTEN_Msk
     
    #define ADC_CR2_JEXTEN_0   (0x1UL << ADC_CR2_JEXTEN_Pos)
     
    #define ADC_CR2_JEXTEN_1   (0x2UL << ADC_CR2_JEXTEN_Pos)
     
    #define ADC_CR2_JSWSTART_Pos   (22U)
     
    #define ADC_CR2_JSWSTART_Msk   (0x1UL << ADC_CR2_JSWSTART_Pos)
     
    #define ADC_CR2_JSWSTART   ADC_CR2_JSWSTART_Msk
     
    #define ADC_CR2_EXTSEL_Pos   (24U)
     
    #define ADC_CR2_EXTSEL_Msk   (0xFUL << ADC_CR2_EXTSEL_Pos)
     
    #define ADC_CR2_EXTSEL   ADC_CR2_EXTSEL_Msk
     
    #define ADC_CR2_EXTSEL_0   (0x1UL << ADC_CR2_EXTSEL_Pos)
     
    #define ADC_CR2_EXTSEL_1   (0x2UL << ADC_CR2_EXTSEL_Pos)
     
    #define ADC_CR2_EXTSEL_2   (0x4UL << ADC_CR2_EXTSEL_Pos)
     
    #define ADC_CR2_EXTSEL_3   (0x8UL << ADC_CR2_EXTSEL_Pos)
     
    #define ADC_CR2_EXTEN_Pos   (28U)
     
    #define ADC_CR2_EXTEN_Msk   (0x3UL << ADC_CR2_EXTEN_Pos)
     
    #define ADC_CR2_EXTEN   ADC_CR2_EXTEN_Msk
     
    #define ADC_CR2_EXTEN_0   (0x1UL << ADC_CR2_EXTEN_Pos)
     
    #define ADC_CR2_EXTEN_1   (0x2UL << ADC_CR2_EXTEN_Pos)
     
    #define ADC_CR2_SWSTART_Pos   (30U)
     
    #define ADC_CR2_SWSTART_Msk   (0x1UL << ADC_CR2_SWSTART_Pos)
     
    #define ADC_CR2_SWSTART   ADC_CR2_SWSTART_Msk
     
    #define ADC_SMPR1_SMP10_Pos   (0U)
     
    #define ADC_SMPR1_SMP10_Msk   (0x7UL << ADC_SMPR1_SMP10_Pos)
     
    #define ADC_SMPR1_SMP10   ADC_SMPR1_SMP10_Msk
     
    #define ADC_SMPR1_SMP10_0   (0x1UL << ADC_SMPR1_SMP10_Pos)
     
    #define ADC_SMPR1_SMP10_1   (0x2UL << ADC_SMPR1_SMP10_Pos)
     
    #define ADC_SMPR1_SMP10_2   (0x4UL << ADC_SMPR1_SMP10_Pos)
     
    #define ADC_SMPR1_SMP11_Pos   (3U)
     
    #define ADC_SMPR1_SMP11_Msk   (0x7UL << ADC_SMPR1_SMP11_Pos)
     
    #define ADC_SMPR1_SMP11   ADC_SMPR1_SMP11_Msk
     
    #define ADC_SMPR1_SMP11_0   (0x1UL << ADC_SMPR1_SMP11_Pos)
     
    #define ADC_SMPR1_SMP11_1   (0x2UL << ADC_SMPR1_SMP11_Pos)
     
    #define ADC_SMPR1_SMP11_2   (0x4UL << ADC_SMPR1_SMP11_Pos)
     
    #define ADC_SMPR1_SMP12_Pos   (6U)
     
    #define ADC_SMPR1_SMP12_Msk   (0x7UL << ADC_SMPR1_SMP12_Pos)
     
    #define ADC_SMPR1_SMP12   ADC_SMPR1_SMP12_Msk
     
    #define ADC_SMPR1_SMP12_0   (0x1UL << ADC_SMPR1_SMP12_Pos)
     
    #define ADC_SMPR1_SMP12_1   (0x2UL << ADC_SMPR1_SMP12_Pos)
     
    #define ADC_SMPR1_SMP12_2   (0x4UL << ADC_SMPR1_SMP12_Pos)
     
    #define ADC_SMPR1_SMP13_Pos   (9U)
     
    #define ADC_SMPR1_SMP13_Msk   (0x7UL << ADC_SMPR1_SMP13_Pos)
     
    #define ADC_SMPR1_SMP13   ADC_SMPR1_SMP13_Msk
     
    #define ADC_SMPR1_SMP13_0   (0x1UL << ADC_SMPR1_SMP13_Pos)
     
    #define ADC_SMPR1_SMP13_1   (0x2UL << ADC_SMPR1_SMP13_Pos)
     
    #define ADC_SMPR1_SMP13_2   (0x4UL << ADC_SMPR1_SMP13_Pos)
     
    #define ADC_SMPR1_SMP14_Pos   (12U)
     
    #define ADC_SMPR1_SMP14_Msk   (0x7UL << ADC_SMPR1_SMP14_Pos)
     
    #define ADC_SMPR1_SMP14   ADC_SMPR1_SMP14_Msk
     
    #define ADC_SMPR1_SMP14_0   (0x1UL << ADC_SMPR1_SMP14_Pos)
     
    #define ADC_SMPR1_SMP14_1   (0x2UL << ADC_SMPR1_SMP14_Pos)
     
    #define ADC_SMPR1_SMP14_2   (0x4UL << ADC_SMPR1_SMP14_Pos)
     
    #define ADC_SMPR1_SMP15_Pos   (15U)
     
    #define ADC_SMPR1_SMP15_Msk   (0x7UL << ADC_SMPR1_SMP15_Pos)
     
    #define ADC_SMPR1_SMP15   ADC_SMPR1_SMP15_Msk
     
    #define ADC_SMPR1_SMP15_0   (0x1UL << ADC_SMPR1_SMP15_Pos)
     
    #define ADC_SMPR1_SMP15_1   (0x2UL << ADC_SMPR1_SMP15_Pos)
     
    #define ADC_SMPR1_SMP15_2   (0x4UL << ADC_SMPR1_SMP15_Pos)
     
    #define ADC_SMPR1_SMP16_Pos   (18U)
     
    #define ADC_SMPR1_SMP16_Msk   (0x7UL << ADC_SMPR1_SMP16_Pos)
     
    #define ADC_SMPR1_SMP16   ADC_SMPR1_SMP16_Msk
     
    #define ADC_SMPR1_SMP16_0   (0x1UL << ADC_SMPR1_SMP16_Pos)
     
    #define ADC_SMPR1_SMP16_1   (0x2UL << ADC_SMPR1_SMP16_Pos)
     
    #define ADC_SMPR1_SMP16_2   (0x4UL << ADC_SMPR1_SMP16_Pos)
     
    #define ADC_SMPR1_SMP17_Pos   (21U)
     
    #define ADC_SMPR1_SMP17_Msk   (0x7UL << ADC_SMPR1_SMP17_Pos)
     
    #define ADC_SMPR1_SMP17   ADC_SMPR1_SMP17_Msk
     
    #define ADC_SMPR1_SMP17_0   (0x1UL << ADC_SMPR1_SMP17_Pos)
     
    #define ADC_SMPR1_SMP17_1   (0x2UL << ADC_SMPR1_SMP17_Pos)
     
    #define ADC_SMPR1_SMP17_2   (0x4UL << ADC_SMPR1_SMP17_Pos)
     
    #define ADC_SMPR1_SMP18_Pos   (24U)
     
    #define ADC_SMPR1_SMP18_Msk   (0x7UL << ADC_SMPR1_SMP18_Pos)
     
    #define ADC_SMPR1_SMP18   ADC_SMPR1_SMP18_Msk
     
    #define ADC_SMPR1_SMP18_0   (0x1UL << ADC_SMPR1_SMP18_Pos)
     
    #define ADC_SMPR1_SMP18_1   (0x2UL << ADC_SMPR1_SMP18_Pos)
     
    #define ADC_SMPR1_SMP18_2   (0x4UL << ADC_SMPR1_SMP18_Pos)
     
    #define ADC_SMPR2_SMP0_Pos   (0U)
     
    #define ADC_SMPR2_SMP0_Msk   (0x7UL << ADC_SMPR2_SMP0_Pos)
     
    #define ADC_SMPR2_SMP0   ADC_SMPR2_SMP0_Msk
     
    #define ADC_SMPR2_SMP0_0   (0x1UL << ADC_SMPR2_SMP0_Pos)
     
    #define ADC_SMPR2_SMP0_1   (0x2UL << ADC_SMPR2_SMP0_Pos)
     
    #define ADC_SMPR2_SMP0_2   (0x4UL << ADC_SMPR2_SMP0_Pos)
     
    #define ADC_SMPR2_SMP1_Pos   (3U)
     
    #define ADC_SMPR2_SMP1_Msk   (0x7UL << ADC_SMPR2_SMP1_Pos)
     
    #define ADC_SMPR2_SMP1   ADC_SMPR2_SMP1_Msk
     
    #define ADC_SMPR2_SMP1_0   (0x1UL << ADC_SMPR2_SMP1_Pos)
     
    #define ADC_SMPR2_SMP1_1   (0x2UL << ADC_SMPR2_SMP1_Pos)
     
    #define ADC_SMPR2_SMP1_2   (0x4UL << ADC_SMPR2_SMP1_Pos)
     
    #define ADC_SMPR2_SMP2_Pos   (6U)
     
    #define ADC_SMPR2_SMP2_Msk   (0x7UL << ADC_SMPR2_SMP2_Pos)
     
    #define ADC_SMPR2_SMP2   ADC_SMPR2_SMP2_Msk
     
    #define ADC_SMPR2_SMP2_0   (0x1UL << ADC_SMPR2_SMP2_Pos)
     
    #define ADC_SMPR2_SMP2_1   (0x2UL << ADC_SMPR2_SMP2_Pos)
     
    #define ADC_SMPR2_SMP2_2   (0x4UL << ADC_SMPR2_SMP2_Pos)
     
    #define ADC_SMPR2_SMP3_Pos   (9U)
     
    #define ADC_SMPR2_SMP3_Msk   (0x7UL << ADC_SMPR2_SMP3_Pos)
     
    #define ADC_SMPR2_SMP3   ADC_SMPR2_SMP3_Msk
     
    #define ADC_SMPR2_SMP3_0   (0x1UL << ADC_SMPR2_SMP3_Pos)
     
    #define ADC_SMPR2_SMP3_1   (0x2UL << ADC_SMPR2_SMP3_Pos)
     
    #define ADC_SMPR2_SMP3_2   (0x4UL << ADC_SMPR2_SMP3_Pos)
     
    #define ADC_SMPR2_SMP4_Pos   (12U)
     
    #define ADC_SMPR2_SMP4_Msk   (0x7UL << ADC_SMPR2_SMP4_Pos)
     
    #define ADC_SMPR2_SMP4   ADC_SMPR2_SMP4_Msk
     
    #define ADC_SMPR2_SMP4_0   (0x1UL << ADC_SMPR2_SMP4_Pos)
     
    #define ADC_SMPR2_SMP4_1   (0x2UL << ADC_SMPR2_SMP4_Pos)
     
    #define ADC_SMPR2_SMP4_2   (0x4UL << ADC_SMPR2_SMP4_Pos)
     
    #define ADC_SMPR2_SMP5_Pos   (15U)
     
    #define ADC_SMPR2_SMP5_Msk   (0x7UL << ADC_SMPR2_SMP5_Pos)
     
    #define ADC_SMPR2_SMP5   ADC_SMPR2_SMP5_Msk
     
    #define ADC_SMPR2_SMP5_0   (0x1UL << ADC_SMPR2_SMP5_Pos)
     
    #define ADC_SMPR2_SMP5_1   (0x2UL << ADC_SMPR2_SMP5_Pos)
     
    #define ADC_SMPR2_SMP5_2   (0x4UL << ADC_SMPR2_SMP5_Pos)
     
    #define ADC_SMPR2_SMP6_Pos   (18U)
     
    #define ADC_SMPR2_SMP6_Msk   (0x7UL << ADC_SMPR2_SMP6_Pos)
     
    #define ADC_SMPR2_SMP6   ADC_SMPR2_SMP6_Msk
     
    #define ADC_SMPR2_SMP6_0   (0x1UL << ADC_SMPR2_SMP6_Pos)
     
    #define ADC_SMPR2_SMP6_1   (0x2UL << ADC_SMPR2_SMP6_Pos)
     
    #define ADC_SMPR2_SMP6_2   (0x4UL << ADC_SMPR2_SMP6_Pos)
     
    #define ADC_SMPR2_SMP7_Pos   (21U)
     
    #define ADC_SMPR2_SMP7_Msk   (0x7UL << ADC_SMPR2_SMP7_Pos)
     
    #define ADC_SMPR2_SMP7   ADC_SMPR2_SMP7_Msk
     
    #define ADC_SMPR2_SMP7_0   (0x1UL << ADC_SMPR2_SMP7_Pos)
     
    #define ADC_SMPR2_SMP7_1   (0x2UL << ADC_SMPR2_SMP7_Pos)
     
    #define ADC_SMPR2_SMP7_2   (0x4UL << ADC_SMPR2_SMP7_Pos)
     
    #define ADC_SMPR2_SMP8_Pos   (24U)
     
    #define ADC_SMPR2_SMP8_Msk   (0x7UL << ADC_SMPR2_SMP8_Pos)
     
    #define ADC_SMPR2_SMP8   ADC_SMPR2_SMP8_Msk
     
    #define ADC_SMPR2_SMP8_0   (0x1UL << ADC_SMPR2_SMP8_Pos)
     
    #define ADC_SMPR2_SMP8_1   (0x2UL << ADC_SMPR2_SMP8_Pos)
     
    #define ADC_SMPR2_SMP8_2   (0x4UL << ADC_SMPR2_SMP8_Pos)
     
    #define ADC_SMPR2_SMP9_Pos   (27U)
     
    #define ADC_SMPR2_SMP9_Msk   (0x7UL << ADC_SMPR2_SMP9_Pos)
     
    #define ADC_SMPR2_SMP9   ADC_SMPR2_SMP9_Msk
     
    #define ADC_SMPR2_SMP9_0   (0x1UL << ADC_SMPR2_SMP9_Pos)
     
    #define ADC_SMPR2_SMP9_1   (0x2UL << ADC_SMPR2_SMP9_Pos)
     
    #define ADC_SMPR2_SMP9_2   (0x4UL << ADC_SMPR2_SMP9_Pos)
     
    #define ADC_JOFR1_JOFFSET1_Pos   (0U)
     
    #define ADC_JOFR1_JOFFSET1_Msk   (0xFFFUL << ADC_JOFR1_JOFFSET1_Pos)
     
    #define ADC_JOFR1_JOFFSET1   ADC_JOFR1_JOFFSET1_Msk
     
    #define ADC_JOFR2_JOFFSET2_Pos   (0U)
     
    #define ADC_JOFR2_JOFFSET2_Msk   (0xFFFUL << ADC_JOFR2_JOFFSET2_Pos)
     
    #define ADC_JOFR2_JOFFSET2   ADC_JOFR2_JOFFSET2_Msk
     
    #define ADC_JOFR3_JOFFSET3_Pos   (0U)
     
    #define ADC_JOFR3_JOFFSET3_Msk   (0xFFFUL << ADC_JOFR3_JOFFSET3_Pos)
     
    #define ADC_JOFR3_JOFFSET3   ADC_JOFR3_JOFFSET3_Msk
     
    #define ADC_JOFR4_JOFFSET4_Pos   (0U)
     
    #define ADC_JOFR4_JOFFSET4_Msk   (0xFFFUL << ADC_JOFR4_JOFFSET4_Pos)
     
    #define ADC_JOFR4_JOFFSET4   ADC_JOFR4_JOFFSET4_Msk
     
    #define ADC_HTR_HT_Pos   (0U)
     
    #define ADC_HTR_HT_Msk   (0xFFFUL << ADC_HTR_HT_Pos)
     
    #define ADC_HTR_HT   ADC_HTR_HT_Msk
     
    #define ADC_LTR_LT_Pos   (0U)
     
    #define ADC_LTR_LT_Msk   (0xFFFUL << ADC_LTR_LT_Pos)
     
    #define ADC_LTR_LT   ADC_LTR_LT_Msk
     
    #define ADC_SQR1_SQ13_Pos   (0U)
     
    #define ADC_SQR1_SQ13_Msk   (0x1FUL << ADC_SQR1_SQ13_Pos)
     
    #define ADC_SQR1_SQ13   ADC_SQR1_SQ13_Msk
     
    #define ADC_SQR1_SQ13_0   (0x01UL << ADC_SQR1_SQ13_Pos)
     
    #define ADC_SQR1_SQ13_1   (0x02UL << ADC_SQR1_SQ13_Pos)
     
    #define ADC_SQR1_SQ13_2   (0x04UL << ADC_SQR1_SQ13_Pos)
     
    #define ADC_SQR1_SQ13_3   (0x08UL << ADC_SQR1_SQ13_Pos)
     
    #define ADC_SQR1_SQ13_4   (0x10UL << ADC_SQR1_SQ13_Pos)
     
    #define ADC_SQR1_SQ14_Pos   (5U)
     
    #define ADC_SQR1_SQ14_Msk   (0x1FUL << ADC_SQR1_SQ14_Pos)
     
    #define ADC_SQR1_SQ14   ADC_SQR1_SQ14_Msk
     
    #define ADC_SQR1_SQ14_0   (0x01UL << ADC_SQR1_SQ14_Pos)
     
    #define ADC_SQR1_SQ14_1   (0x02UL << ADC_SQR1_SQ14_Pos)
     
    #define ADC_SQR1_SQ14_2   (0x04UL << ADC_SQR1_SQ14_Pos)
     
    #define ADC_SQR1_SQ14_3   (0x08UL << ADC_SQR1_SQ14_Pos)
     
    #define ADC_SQR1_SQ14_4   (0x10UL << ADC_SQR1_SQ14_Pos)
     
    #define ADC_SQR1_SQ15_Pos   (10U)
     
    #define ADC_SQR1_SQ15_Msk   (0x1FUL << ADC_SQR1_SQ15_Pos)
     
    #define ADC_SQR1_SQ15   ADC_SQR1_SQ15_Msk
     
    #define ADC_SQR1_SQ15_0   (0x01UL << ADC_SQR1_SQ15_Pos)
     
    #define ADC_SQR1_SQ15_1   (0x02UL << ADC_SQR1_SQ15_Pos)
     
    #define ADC_SQR1_SQ15_2   (0x04UL << ADC_SQR1_SQ15_Pos)
     
    #define ADC_SQR1_SQ15_3   (0x08UL << ADC_SQR1_SQ15_Pos)
     
    #define ADC_SQR1_SQ15_4   (0x10UL << ADC_SQR1_SQ15_Pos)
     
    #define ADC_SQR1_SQ16_Pos   (15U)
     
    #define ADC_SQR1_SQ16_Msk   (0x1FUL << ADC_SQR1_SQ16_Pos)
     
    #define ADC_SQR1_SQ16   ADC_SQR1_SQ16_Msk
     
    #define ADC_SQR1_SQ16_0   (0x01UL << ADC_SQR1_SQ16_Pos)
     
    #define ADC_SQR1_SQ16_1   (0x02UL << ADC_SQR1_SQ16_Pos)
     
    #define ADC_SQR1_SQ16_2   (0x04UL << ADC_SQR1_SQ16_Pos)
     
    #define ADC_SQR1_SQ16_3   (0x08UL << ADC_SQR1_SQ16_Pos)
     
    #define ADC_SQR1_SQ16_4   (0x10UL << ADC_SQR1_SQ16_Pos)
     
    #define ADC_SQR1_L_Pos   (20U)
     
    #define ADC_SQR1_L_Msk   (0xFUL << ADC_SQR1_L_Pos)
     
    #define ADC_SQR1_L   ADC_SQR1_L_Msk
     
    #define ADC_SQR1_L_0   (0x1UL << ADC_SQR1_L_Pos)
     
    #define ADC_SQR1_L_1   (0x2UL << ADC_SQR1_L_Pos)
     
    #define ADC_SQR1_L_2   (0x4UL << ADC_SQR1_L_Pos)
     
    #define ADC_SQR1_L_3   (0x8UL << ADC_SQR1_L_Pos)
     
    #define ADC_SQR2_SQ7_Pos   (0U)
     
    #define ADC_SQR2_SQ7_Msk   (0x1FUL << ADC_SQR2_SQ7_Pos)
     
    #define ADC_SQR2_SQ7   ADC_SQR2_SQ7_Msk
     
    #define ADC_SQR2_SQ7_0   (0x01UL << ADC_SQR2_SQ7_Pos)
     
    #define ADC_SQR2_SQ7_1   (0x02UL << ADC_SQR2_SQ7_Pos)
     
    #define ADC_SQR2_SQ7_2   (0x04UL << ADC_SQR2_SQ7_Pos)
     
    #define ADC_SQR2_SQ7_3   (0x08UL << ADC_SQR2_SQ7_Pos)
     
    #define ADC_SQR2_SQ7_4   (0x10UL << ADC_SQR2_SQ7_Pos)
     
    #define ADC_SQR2_SQ8_Pos   (5U)
     
    #define ADC_SQR2_SQ8_Msk   (0x1FUL << ADC_SQR2_SQ8_Pos)
     
    #define ADC_SQR2_SQ8   ADC_SQR2_SQ8_Msk
     
    #define ADC_SQR2_SQ8_0   (0x01UL << ADC_SQR2_SQ8_Pos)
     
    #define ADC_SQR2_SQ8_1   (0x02UL << ADC_SQR2_SQ8_Pos)
     
    #define ADC_SQR2_SQ8_2   (0x04UL << ADC_SQR2_SQ8_Pos)
     
    #define ADC_SQR2_SQ8_3   (0x08UL << ADC_SQR2_SQ8_Pos)
     
    #define ADC_SQR2_SQ8_4   (0x10UL << ADC_SQR2_SQ8_Pos)
     
    #define ADC_SQR2_SQ9_Pos   (10U)
     
    #define ADC_SQR2_SQ9_Msk   (0x1FUL << ADC_SQR2_SQ9_Pos)
     
    #define ADC_SQR2_SQ9   ADC_SQR2_SQ9_Msk
     
    #define ADC_SQR2_SQ9_0   (0x01UL << ADC_SQR2_SQ9_Pos)
     
    #define ADC_SQR2_SQ9_1   (0x02UL << ADC_SQR2_SQ9_Pos)
     
    #define ADC_SQR2_SQ9_2   (0x04UL << ADC_SQR2_SQ9_Pos)
     
    #define ADC_SQR2_SQ9_3   (0x08UL << ADC_SQR2_SQ9_Pos)
     
    #define ADC_SQR2_SQ9_4   (0x10UL << ADC_SQR2_SQ9_Pos)
     
    #define ADC_SQR2_SQ10_Pos   (15U)
     
    #define ADC_SQR2_SQ10_Msk   (0x1FUL << ADC_SQR2_SQ10_Pos)
     
    #define ADC_SQR2_SQ10   ADC_SQR2_SQ10_Msk
     
    #define ADC_SQR2_SQ10_0   (0x01UL << ADC_SQR2_SQ10_Pos)
     
    #define ADC_SQR2_SQ10_1   (0x02UL << ADC_SQR2_SQ10_Pos)
     
    #define ADC_SQR2_SQ10_2   (0x04UL << ADC_SQR2_SQ10_Pos)
     
    #define ADC_SQR2_SQ10_3   (0x08UL << ADC_SQR2_SQ10_Pos)
     
    #define ADC_SQR2_SQ10_4   (0x10UL << ADC_SQR2_SQ10_Pos)
     
    #define ADC_SQR2_SQ11_Pos   (20U)
     
    #define ADC_SQR2_SQ11_Msk   (0x1FUL << ADC_SQR2_SQ11_Pos)
     
    #define ADC_SQR2_SQ11   ADC_SQR2_SQ11_Msk
     
    #define ADC_SQR2_SQ11_0   (0x01UL << ADC_SQR2_SQ11_Pos)
     
    #define ADC_SQR2_SQ11_1   (0x02UL << ADC_SQR2_SQ11_Pos)
     
    #define ADC_SQR2_SQ11_2   (0x04UL << ADC_SQR2_SQ11_Pos)
     
    #define ADC_SQR2_SQ11_3   (0x08UL << ADC_SQR2_SQ11_Pos)
     
    #define ADC_SQR2_SQ11_4   (0x10UL << ADC_SQR2_SQ11_Pos)
     
    #define ADC_SQR2_SQ12_Pos   (25U)
     
    #define ADC_SQR2_SQ12_Msk   (0x1FUL << ADC_SQR2_SQ12_Pos)
     
    #define ADC_SQR2_SQ12   ADC_SQR2_SQ12_Msk
     
    #define ADC_SQR2_SQ12_0   (0x01UL << ADC_SQR2_SQ12_Pos)
     
    #define ADC_SQR2_SQ12_1   (0x02UL << ADC_SQR2_SQ12_Pos)
     
    #define ADC_SQR2_SQ12_2   (0x04UL << ADC_SQR2_SQ12_Pos)
     
    #define ADC_SQR2_SQ12_3   (0x08UL << ADC_SQR2_SQ12_Pos)
     
    #define ADC_SQR2_SQ12_4   (0x10UL << ADC_SQR2_SQ12_Pos)
     
    #define ADC_SQR3_SQ1_Pos   (0U)
     
    #define ADC_SQR3_SQ1_Msk   (0x1FUL << ADC_SQR3_SQ1_Pos)
     
    #define ADC_SQR3_SQ1   ADC_SQR3_SQ1_Msk
     
    #define ADC_SQR3_SQ1_0   (0x01UL << ADC_SQR3_SQ1_Pos)
     
    #define ADC_SQR3_SQ1_1   (0x02UL << ADC_SQR3_SQ1_Pos)
     
    #define ADC_SQR3_SQ1_2   (0x04UL << ADC_SQR3_SQ1_Pos)
     
    #define ADC_SQR3_SQ1_3   (0x08UL << ADC_SQR3_SQ1_Pos)
     
    #define ADC_SQR3_SQ1_4   (0x10UL << ADC_SQR3_SQ1_Pos)
     
    #define ADC_SQR3_SQ2_Pos   (5U)
     
    #define ADC_SQR3_SQ2_Msk   (0x1FUL << ADC_SQR3_SQ2_Pos)
     
    #define ADC_SQR3_SQ2   ADC_SQR3_SQ2_Msk
     
    #define ADC_SQR3_SQ2_0   (0x01UL << ADC_SQR3_SQ2_Pos)
     
    #define ADC_SQR3_SQ2_1   (0x02UL << ADC_SQR3_SQ2_Pos)
     
    #define ADC_SQR3_SQ2_2   (0x04UL << ADC_SQR3_SQ2_Pos)
     
    #define ADC_SQR3_SQ2_3   (0x08UL << ADC_SQR3_SQ2_Pos)
     
    #define ADC_SQR3_SQ2_4   (0x10UL << ADC_SQR3_SQ2_Pos)
     
    #define ADC_SQR3_SQ3_Pos   (10U)
     
    #define ADC_SQR3_SQ3_Msk   (0x1FUL << ADC_SQR3_SQ3_Pos)
     
    #define ADC_SQR3_SQ3   ADC_SQR3_SQ3_Msk
     
    #define ADC_SQR3_SQ3_0   (0x01UL << ADC_SQR3_SQ3_Pos)
     
    #define ADC_SQR3_SQ3_1   (0x02UL << ADC_SQR3_SQ3_Pos)
     
    #define ADC_SQR3_SQ3_2   (0x04UL << ADC_SQR3_SQ3_Pos)
     
    #define ADC_SQR3_SQ3_3   (0x08UL << ADC_SQR3_SQ3_Pos)
     
    #define ADC_SQR3_SQ3_4   (0x10UL << ADC_SQR3_SQ3_Pos)
     
    #define ADC_SQR3_SQ4_Pos   (15U)
     
    #define ADC_SQR3_SQ4_Msk   (0x1FUL << ADC_SQR3_SQ4_Pos)
     
    #define ADC_SQR3_SQ4   ADC_SQR3_SQ4_Msk
     
    #define ADC_SQR3_SQ4_0   (0x01UL << ADC_SQR3_SQ4_Pos)
     
    #define ADC_SQR3_SQ4_1   (0x02UL << ADC_SQR3_SQ4_Pos)
     
    #define ADC_SQR3_SQ4_2   (0x04UL << ADC_SQR3_SQ4_Pos)
     
    #define ADC_SQR3_SQ4_3   (0x08UL << ADC_SQR3_SQ4_Pos)
     
    #define ADC_SQR3_SQ4_4   (0x10UL << ADC_SQR3_SQ4_Pos)
     
    #define ADC_SQR3_SQ5_Pos   (20U)
     
    #define ADC_SQR3_SQ5_Msk   (0x1FUL << ADC_SQR3_SQ5_Pos)
     
    #define ADC_SQR3_SQ5   ADC_SQR3_SQ5_Msk
     
    #define ADC_SQR3_SQ5_0   (0x01UL << ADC_SQR3_SQ5_Pos)
     
    #define ADC_SQR3_SQ5_1   (0x02UL << ADC_SQR3_SQ5_Pos)
     
    #define ADC_SQR3_SQ5_2   (0x04UL << ADC_SQR3_SQ5_Pos)
     
    #define ADC_SQR3_SQ5_3   (0x08UL << ADC_SQR3_SQ5_Pos)
     
    #define ADC_SQR3_SQ5_4   (0x10UL << ADC_SQR3_SQ5_Pos)
     
    #define ADC_SQR3_SQ6_Pos   (25U)
     
    #define ADC_SQR3_SQ6_Msk   (0x1FUL << ADC_SQR3_SQ6_Pos)
     
    #define ADC_SQR3_SQ6   ADC_SQR3_SQ6_Msk
     
    #define ADC_SQR3_SQ6_0   (0x01UL << ADC_SQR3_SQ6_Pos)
     
    #define ADC_SQR3_SQ6_1   (0x02UL << ADC_SQR3_SQ6_Pos)
     
    #define ADC_SQR3_SQ6_2   (0x04UL << ADC_SQR3_SQ6_Pos)
     
    #define ADC_SQR3_SQ6_3   (0x08UL << ADC_SQR3_SQ6_Pos)
     
    #define ADC_SQR3_SQ6_4   (0x10UL << ADC_SQR3_SQ6_Pos)
     
    #define ADC_JSQR_JSQ1_Pos   (0U)
     
    #define ADC_JSQR_JSQ1_Msk   (0x1FUL << ADC_JSQR_JSQ1_Pos)
     
    #define ADC_JSQR_JSQ1   ADC_JSQR_JSQ1_Msk
     
    #define ADC_JSQR_JSQ1_0   (0x01UL << ADC_JSQR_JSQ1_Pos)
     
    #define ADC_JSQR_JSQ1_1   (0x02UL << ADC_JSQR_JSQ1_Pos)
     
    #define ADC_JSQR_JSQ1_2   (0x04UL << ADC_JSQR_JSQ1_Pos)
     
    #define ADC_JSQR_JSQ1_3   (0x08UL << ADC_JSQR_JSQ1_Pos)
     
    #define ADC_JSQR_JSQ1_4   (0x10UL << ADC_JSQR_JSQ1_Pos)
     
    #define ADC_JSQR_JSQ2_Pos   (5U)
     
    #define ADC_JSQR_JSQ2_Msk   (0x1FUL << ADC_JSQR_JSQ2_Pos)
     
    #define ADC_JSQR_JSQ2   ADC_JSQR_JSQ2_Msk
     
    #define ADC_JSQR_JSQ2_0   (0x01UL << ADC_JSQR_JSQ2_Pos)
     
    #define ADC_JSQR_JSQ2_1   (0x02UL << ADC_JSQR_JSQ2_Pos)
     
    #define ADC_JSQR_JSQ2_2   (0x04UL << ADC_JSQR_JSQ2_Pos)
     
    #define ADC_JSQR_JSQ2_3   (0x08UL << ADC_JSQR_JSQ2_Pos)
     
    #define ADC_JSQR_JSQ2_4   (0x10UL << ADC_JSQR_JSQ2_Pos)
     
    #define ADC_JSQR_JSQ3_Pos   (10U)
     
    #define ADC_JSQR_JSQ3_Msk   (0x1FUL << ADC_JSQR_JSQ3_Pos)
     
    #define ADC_JSQR_JSQ3   ADC_JSQR_JSQ3_Msk
     
    #define ADC_JSQR_JSQ3_0   (0x01UL << ADC_JSQR_JSQ3_Pos)
     
    #define ADC_JSQR_JSQ3_1   (0x02UL << ADC_JSQR_JSQ3_Pos)
     
    #define ADC_JSQR_JSQ3_2   (0x04UL << ADC_JSQR_JSQ3_Pos)
     
    #define ADC_JSQR_JSQ3_3   (0x08UL << ADC_JSQR_JSQ3_Pos)
     
    #define ADC_JSQR_JSQ3_4   (0x10UL << ADC_JSQR_JSQ3_Pos)
     
    #define ADC_JSQR_JSQ4_Pos   (15U)
     
    #define ADC_JSQR_JSQ4_Msk   (0x1FUL << ADC_JSQR_JSQ4_Pos)
     
    #define ADC_JSQR_JSQ4   ADC_JSQR_JSQ4_Msk
     
    #define ADC_JSQR_JSQ4_0   (0x01UL << ADC_JSQR_JSQ4_Pos)
     
    #define ADC_JSQR_JSQ4_1   (0x02UL << ADC_JSQR_JSQ4_Pos)
     
    #define ADC_JSQR_JSQ4_2   (0x04UL << ADC_JSQR_JSQ4_Pos)
     
    #define ADC_JSQR_JSQ4_3   (0x08UL << ADC_JSQR_JSQ4_Pos)
     
    #define ADC_JSQR_JSQ4_4   (0x10UL << ADC_JSQR_JSQ4_Pos)
     
    #define ADC_JSQR_JL_Pos   (20U)
     
    #define ADC_JSQR_JL_Msk   (0x3UL << ADC_JSQR_JL_Pos)
     
    #define ADC_JSQR_JL   ADC_JSQR_JL_Msk
     
    #define ADC_JSQR_JL_0   (0x1UL << ADC_JSQR_JL_Pos)
     
    #define ADC_JSQR_JL_1   (0x2UL << ADC_JSQR_JL_Pos)
     
    #define ADC_JDR1_JDATA_Pos   (0U)
     
    #define ADC_JDR1_JDATA_Msk   (0xFFFFUL << ADC_JDR1_JDATA_Pos)
     
    #define ADC_JDR1_JDATA   ADC_JDR1_JDATA_Msk
     
    #define ADC_JDR2_JDATA_Pos   (0U)
     
    #define ADC_JDR2_JDATA_Msk   (0xFFFFUL << ADC_JDR2_JDATA_Pos)
     
    #define ADC_JDR2_JDATA   ADC_JDR2_JDATA_Msk
     
    #define ADC_JDR3_JDATA_Pos   (0U)
     
    #define ADC_JDR3_JDATA_Msk   (0xFFFFUL << ADC_JDR3_JDATA_Pos)
     
    #define ADC_JDR3_JDATA   ADC_JDR3_JDATA_Msk
     
    #define ADC_JDR4_JDATA_Pos   (0U)
     
    #define ADC_JDR4_JDATA_Msk   (0xFFFFUL << ADC_JDR4_JDATA_Pos)
     
    #define ADC_JDR4_JDATA   ADC_JDR4_JDATA_Msk
     
    #define ADC_DR_DATA_Pos   (0U)
     
    #define ADC_DR_DATA_Msk   (0xFFFFUL << ADC_DR_DATA_Pos)
     
    #define ADC_DR_DATA   ADC_DR_DATA_Msk
     
    #define ADC_DR_ADC2DATA_Pos   (16U)
     
    #define ADC_DR_ADC2DATA_Msk   (0xFFFFUL << ADC_DR_ADC2DATA_Pos)
     
    #define ADC_DR_ADC2DATA   ADC_DR_ADC2DATA_Msk
     
    #define ADC_CSR_AWD1_Pos   (0U)
     
    #define ADC_CSR_AWD1_Msk   (0x1UL << ADC_CSR_AWD1_Pos)
     
    #define ADC_CSR_AWD1   ADC_CSR_AWD1_Msk
     
    #define ADC_CSR_EOC1_Pos   (1U)
     
    #define ADC_CSR_EOC1_Msk   (0x1UL << ADC_CSR_EOC1_Pos)
     
    #define ADC_CSR_EOC1   ADC_CSR_EOC1_Msk
     
    #define ADC_CSR_JEOC1_Pos   (2U)
     
    #define ADC_CSR_JEOC1_Msk   (0x1UL << ADC_CSR_JEOC1_Pos)
     
    #define ADC_CSR_JEOC1   ADC_CSR_JEOC1_Msk
     
    #define ADC_CSR_JSTRT1_Pos   (3U)
     
    #define ADC_CSR_JSTRT1_Msk   (0x1UL << ADC_CSR_JSTRT1_Pos)
     
    #define ADC_CSR_JSTRT1   ADC_CSR_JSTRT1_Msk
     
    #define ADC_CSR_STRT1_Pos   (4U)
     
    #define ADC_CSR_STRT1_Msk   (0x1UL << ADC_CSR_STRT1_Pos)
     
    #define ADC_CSR_STRT1   ADC_CSR_STRT1_Msk
     
    #define ADC_CSR_OVR1_Pos   (5U)
     
    #define ADC_CSR_OVR1_Msk   (0x1UL << ADC_CSR_OVR1_Pos)
     
    #define ADC_CSR_OVR1   ADC_CSR_OVR1_Msk
     
    #define ADC_CSR_AWD2_Pos   (8U)
     
    #define ADC_CSR_AWD2_Msk   (0x1UL << ADC_CSR_AWD2_Pos)
     
    #define ADC_CSR_AWD2   ADC_CSR_AWD2_Msk
     
    #define ADC_CSR_EOC2_Pos   (9U)
     
    #define ADC_CSR_EOC2_Msk   (0x1UL << ADC_CSR_EOC2_Pos)
     
    #define ADC_CSR_EOC2   ADC_CSR_EOC2_Msk
     
    #define ADC_CSR_JEOC2_Pos   (10U)
     
    #define ADC_CSR_JEOC2_Msk   (0x1UL << ADC_CSR_JEOC2_Pos)
     
    #define ADC_CSR_JEOC2   ADC_CSR_JEOC2_Msk
     
    #define ADC_CSR_JSTRT2_Pos   (11U)
     
    #define ADC_CSR_JSTRT2_Msk   (0x1UL << ADC_CSR_JSTRT2_Pos)
     
    #define ADC_CSR_JSTRT2   ADC_CSR_JSTRT2_Msk
     
    #define ADC_CSR_STRT2_Pos   (12U)
     
    #define ADC_CSR_STRT2_Msk   (0x1UL << ADC_CSR_STRT2_Pos)
     
    #define ADC_CSR_STRT2   ADC_CSR_STRT2_Msk
     
    #define ADC_CSR_OVR2_Pos   (13U)
     
    #define ADC_CSR_OVR2_Msk   (0x1UL << ADC_CSR_OVR2_Pos)
     
    #define ADC_CSR_OVR2   ADC_CSR_OVR2_Msk
     
    #define ADC_CSR_AWD3_Pos   (16U)
     
    #define ADC_CSR_AWD3_Msk   (0x1UL << ADC_CSR_AWD3_Pos)
     
    #define ADC_CSR_AWD3   ADC_CSR_AWD3_Msk
     
    #define ADC_CSR_EOC3_Pos   (17U)
     
    #define ADC_CSR_EOC3_Msk   (0x1UL << ADC_CSR_EOC3_Pos)
     
    #define ADC_CSR_EOC3   ADC_CSR_EOC3_Msk
     
    #define ADC_CSR_JEOC3_Pos   (18U)
     
    #define ADC_CSR_JEOC3_Msk   (0x1UL << ADC_CSR_JEOC3_Pos)
     
    #define ADC_CSR_JEOC3   ADC_CSR_JEOC3_Msk
     
    #define ADC_CSR_JSTRT3_Pos   (19U)
     
    #define ADC_CSR_JSTRT3_Msk   (0x1UL << ADC_CSR_JSTRT3_Pos)
     
    #define ADC_CSR_JSTRT3   ADC_CSR_JSTRT3_Msk
     
    #define ADC_CSR_STRT3_Pos   (20U)
     
    #define ADC_CSR_STRT3_Msk   (0x1UL << ADC_CSR_STRT3_Pos)
     
    #define ADC_CSR_STRT3   ADC_CSR_STRT3_Msk
     
    #define ADC_CSR_OVR3_Pos   (21U)
     
    #define ADC_CSR_OVR3_Msk   (0x1UL << ADC_CSR_OVR3_Pos)
     
    #define ADC_CSR_OVR3   ADC_CSR_OVR3_Msk
     
    #define ADC_CSR_DOVR1   ADC_CSR_OVR1
     
    #define ADC_CSR_DOVR2   ADC_CSR_OVR2
     
    #define ADC_CSR_DOVR3   ADC_CSR_OVR3
     
    #define ADC_CCR_MULTI_Pos   (0U)
     
    #define ADC_CCR_MULTI_Msk   (0x1FUL << ADC_CCR_MULTI_Pos)
     
    #define ADC_CCR_MULTI   ADC_CCR_MULTI_Msk
     
    #define ADC_CCR_MULTI_0   (0x01UL << ADC_CCR_MULTI_Pos)
     
    #define ADC_CCR_MULTI_1   (0x02UL << ADC_CCR_MULTI_Pos)
     
    #define ADC_CCR_MULTI_2   (0x04UL << ADC_CCR_MULTI_Pos)
     
    #define ADC_CCR_MULTI_3   (0x08UL << ADC_CCR_MULTI_Pos)
     
    #define ADC_CCR_MULTI_4   (0x10UL << ADC_CCR_MULTI_Pos)
     
    #define ADC_CCR_DELAY_Pos   (8U)
     
    #define ADC_CCR_DELAY_Msk   (0xFUL << ADC_CCR_DELAY_Pos)
     
    #define ADC_CCR_DELAY   ADC_CCR_DELAY_Msk
     
    #define ADC_CCR_DELAY_0   (0x1UL << ADC_CCR_DELAY_Pos)
     
    #define ADC_CCR_DELAY_1   (0x2UL << ADC_CCR_DELAY_Pos)
     
    #define ADC_CCR_DELAY_2   (0x4UL << ADC_CCR_DELAY_Pos)
     
    #define ADC_CCR_DELAY_3   (0x8UL << ADC_CCR_DELAY_Pos)
     
    #define ADC_CCR_DDS_Pos   (13U)
     
    #define ADC_CCR_DDS_Msk   (0x1UL << ADC_CCR_DDS_Pos)
     
    #define ADC_CCR_DDS   ADC_CCR_DDS_Msk
     
    #define ADC_CCR_DMA_Pos   (14U)
     
    #define ADC_CCR_DMA_Msk   (0x3UL << ADC_CCR_DMA_Pos)
     
    #define ADC_CCR_DMA   ADC_CCR_DMA_Msk
     
    #define ADC_CCR_DMA_0   (0x1UL << ADC_CCR_DMA_Pos)
     
    #define ADC_CCR_DMA_1   (0x2UL << ADC_CCR_DMA_Pos)
     
    #define ADC_CCR_ADCPRE_Pos   (16U)
     
    #define ADC_CCR_ADCPRE_Msk   (0x3UL << ADC_CCR_ADCPRE_Pos)
     
    #define ADC_CCR_ADCPRE   ADC_CCR_ADCPRE_Msk
     
    #define ADC_CCR_ADCPRE_0   (0x1UL << ADC_CCR_ADCPRE_Pos)
     
    #define ADC_CCR_ADCPRE_1   (0x2UL << ADC_CCR_ADCPRE_Pos)
     
    #define ADC_CCR_VBATE_Pos   (22U)
     
    #define ADC_CCR_VBATE_Msk   (0x1UL << ADC_CCR_VBATE_Pos)
     
    #define ADC_CCR_VBATE   ADC_CCR_VBATE_Msk
     
    #define ADC_CCR_TSVREFE_Pos   (23U)
     
    #define ADC_CCR_TSVREFE_Msk   (0x1UL << ADC_CCR_TSVREFE_Pos)
     
    #define ADC_CCR_TSVREFE   ADC_CCR_TSVREFE_Msk
     
    #define ADC_CDR_DATA1_Pos   (0U)
     
    #define ADC_CDR_DATA1_Msk   (0xFFFFUL << ADC_CDR_DATA1_Pos)
     
    #define ADC_CDR_DATA1   ADC_CDR_DATA1_Msk
     
    #define ADC_CDR_DATA2_Pos   (16U)
     
    #define ADC_CDR_DATA2_Msk   (0xFFFFUL << ADC_CDR_DATA2_Pos)
     
    #define ADC_CDR_DATA2   ADC_CDR_DATA2_Msk
     
    #define ADC_CDR_RDATA_MST   ADC_CDR_DATA1
     
    #define ADC_CDR_RDATA_SLV   ADC_CDR_DATA2
     
    #define CAN_MCR_INRQ_Pos   (0U)
     
    #define CAN_MCR_INRQ_Msk   (0x1UL << CAN_MCR_INRQ_Pos)
     
    #define CAN_MCR_INRQ   CAN_MCR_INRQ_Msk
     
    #define CAN_MCR_SLEEP_Pos   (1U)
     
    #define CAN_MCR_SLEEP_Msk   (0x1UL << CAN_MCR_SLEEP_Pos)
     
    #define CAN_MCR_SLEEP   CAN_MCR_SLEEP_Msk
     
    #define CAN_MCR_TXFP_Pos   (2U)
     
    #define CAN_MCR_TXFP_Msk   (0x1UL << CAN_MCR_TXFP_Pos)
     
    #define CAN_MCR_TXFP   CAN_MCR_TXFP_Msk
     
    #define CAN_MCR_RFLM_Pos   (3U)
     
    #define CAN_MCR_RFLM_Msk   (0x1UL << CAN_MCR_RFLM_Pos)
     
    #define CAN_MCR_RFLM   CAN_MCR_RFLM_Msk
     
    #define CAN_MCR_NART_Pos   (4U)
     
    #define CAN_MCR_NART_Msk   (0x1UL << CAN_MCR_NART_Pos)
     
    #define CAN_MCR_NART   CAN_MCR_NART_Msk
     
    #define CAN_MCR_AWUM_Pos   (5U)
     
    #define CAN_MCR_AWUM_Msk   (0x1UL << CAN_MCR_AWUM_Pos)
     
    #define CAN_MCR_AWUM   CAN_MCR_AWUM_Msk
     
    #define CAN_MCR_ABOM_Pos   (6U)
     
    #define CAN_MCR_ABOM_Msk   (0x1UL << CAN_MCR_ABOM_Pos)
     
    #define CAN_MCR_ABOM   CAN_MCR_ABOM_Msk
     
    #define CAN_MCR_TTCM_Pos   (7U)
     
    #define CAN_MCR_TTCM_Msk   (0x1UL << CAN_MCR_TTCM_Pos)
     
    #define CAN_MCR_TTCM   CAN_MCR_TTCM_Msk
     
    #define CAN_MCR_RESET_Pos   (15U)
     
    #define CAN_MCR_RESET_Msk   (0x1UL << CAN_MCR_RESET_Pos)
     
    #define CAN_MCR_RESET   CAN_MCR_RESET_Msk
     
    #define CAN_MCR_DBF_Pos   (16U)
     
    #define CAN_MCR_DBF_Msk   (0x1UL << CAN_MCR_DBF_Pos)
     
    #define CAN_MCR_DBF   CAN_MCR_DBF_Msk
     
    #define CAN_MSR_INAK_Pos   (0U)
     
    #define CAN_MSR_INAK_Msk   (0x1UL << CAN_MSR_INAK_Pos)
     
    #define CAN_MSR_INAK   CAN_MSR_INAK_Msk
     
    #define CAN_MSR_SLAK_Pos   (1U)
     
    #define CAN_MSR_SLAK_Msk   (0x1UL << CAN_MSR_SLAK_Pos)
     
    #define CAN_MSR_SLAK   CAN_MSR_SLAK_Msk
     
    #define CAN_MSR_ERRI_Pos   (2U)
     
    #define CAN_MSR_ERRI_Msk   (0x1UL << CAN_MSR_ERRI_Pos)
     
    #define CAN_MSR_ERRI   CAN_MSR_ERRI_Msk
     
    #define CAN_MSR_WKUI_Pos   (3U)
     
    #define CAN_MSR_WKUI_Msk   (0x1UL << CAN_MSR_WKUI_Pos)
     
    #define CAN_MSR_WKUI   CAN_MSR_WKUI_Msk
     
    #define CAN_MSR_SLAKI_Pos   (4U)
     
    #define CAN_MSR_SLAKI_Msk   (0x1UL << CAN_MSR_SLAKI_Pos)
     
    #define CAN_MSR_SLAKI   CAN_MSR_SLAKI_Msk
     
    #define CAN_MSR_TXM_Pos   (8U)
     
    #define CAN_MSR_TXM_Msk   (0x1UL << CAN_MSR_TXM_Pos)
     
    #define CAN_MSR_TXM   CAN_MSR_TXM_Msk
     
    #define CAN_MSR_RXM_Pos   (9U)
     
    #define CAN_MSR_RXM_Msk   (0x1UL << CAN_MSR_RXM_Pos)
     
    #define CAN_MSR_RXM   CAN_MSR_RXM_Msk
     
    #define CAN_MSR_SAMP_Pos   (10U)
     
    #define CAN_MSR_SAMP_Msk   (0x1UL << CAN_MSR_SAMP_Pos)
     
    #define CAN_MSR_SAMP   CAN_MSR_SAMP_Msk
     
    #define CAN_MSR_RX_Pos   (11U)
     
    #define CAN_MSR_RX_Msk   (0x1UL << CAN_MSR_RX_Pos)
     
    #define CAN_MSR_RX   CAN_MSR_RX_Msk
     
    #define CAN_TSR_RQCP0_Pos   (0U)
     
    #define CAN_TSR_RQCP0_Msk   (0x1UL << CAN_TSR_RQCP0_Pos)
     
    #define CAN_TSR_RQCP0   CAN_TSR_RQCP0_Msk
     
    #define CAN_TSR_TXOK0_Pos   (1U)
     
    #define CAN_TSR_TXOK0_Msk   (0x1UL << CAN_TSR_TXOK0_Pos)
     
    #define CAN_TSR_TXOK0   CAN_TSR_TXOK0_Msk
     
    #define CAN_TSR_ALST0_Pos   (2U)
     
    #define CAN_TSR_ALST0_Msk   (0x1UL << CAN_TSR_ALST0_Pos)
     
    #define CAN_TSR_ALST0   CAN_TSR_ALST0_Msk
     
    #define CAN_TSR_TERR0_Pos   (3U)
     
    #define CAN_TSR_TERR0_Msk   (0x1UL << CAN_TSR_TERR0_Pos)
     
    #define CAN_TSR_TERR0   CAN_TSR_TERR0_Msk
     
    #define CAN_TSR_ABRQ0_Pos   (7U)
     
    #define CAN_TSR_ABRQ0_Msk   (0x1UL << CAN_TSR_ABRQ0_Pos)
     
    #define CAN_TSR_ABRQ0   CAN_TSR_ABRQ0_Msk
     
    #define CAN_TSR_RQCP1_Pos   (8U)
     
    #define CAN_TSR_RQCP1_Msk   (0x1UL << CAN_TSR_RQCP1_Pos)
     
    #define CAN_TSR_RQCP1   CAN_TSR_RQCP1_Msk
     
    #define CAN_TSR_TXOK1_Pos   (9U)
     
    #define CAN_TSR_TXOK1_Msk   (0x1UL << CAN_TSR_TXOK1_Pos)
     
    #define CAN_TSR_TXOK1   CAN_TSR_TXOK1_Msk
     
    #define CAN_TSR_ALST1_Pos   (10U)
     
    #define CAN_TSR_ALST1_Msk   (0x1UL << CAN_TSR_ALST1_Pos)
     
    #define CAN_TSR_ALST1   CAN_TSR_ALST1_Msk
     
    #define CAN_TSR_TERR1_Pos   (11U)
     
    #define CAN_TSR_TERR1_Msk   (0x1UL << CAN_TSR_TERR1_Pos)
     
    #define CAN_TSR_TERR1   CAN_TSR_TERR1_Msk
     
    #define CAN_TSR_ABRQ1_Pos   (15U)
     
    #define CAN_TSR_ABRQ1_Msk   (0x1UL << CAN_TSR_ABRQ1_Pos)
     
    #define CAN_TSR_ABRQ1   CAN_TSR_ABRQ1_Msk
     
    #define CAN_TSR_RQCP2_Pos   (16U)
     
    #define CAN_TSR_RQCP2_Msk   (0x1UL << CAN_TSR_RQCP2_Pos)
     
    #define CAN_TSR_RQCP2   CAN_TSR_RQCP2_Msk
     
    #define CAN_TSR_TXOK2_Pos   (17U)
     
    #define CAN_TSR_TXOK2_Msk   (0x1UL << CAN_TSR_TXOK2_Pos)
     
    #define CAN_TSR_TXOK2   CAN_TSR_TXOK2_Msk
     
    #define CAN_TSR_ALST2_Pos   (18U)
     
    #define CAN_TSR_ALST2_Msk   (0x1UL << CAN_TSR_ALST2_Pos)
     
    #define CAN_TSR_ALST2   CAN_TSR_ALST2_Msk
     
    #define CAN_TSR_TERR2_Pos   (19U)
     
    #define CAN_TSR_TERR2_Msk   (0x1UL << CAN_TSR_TERR2_Pos)
     
    #define CAN_TSR_TERR2   CAN_TSR_TERR2_Msk
     
    #define CAN_TSR_ABRQ2_Pos   (23U)
     
    #define CAN_TSR_ABRQ2_Msk   (0x1UL << CAN_TSR_ABRQ2_Pos)
     
    #define CAN_TSR_ABRQ2   CAN_TSR_ABRQ2_Msk
     
    #define CAN_TSR_CODE_Pos   (24U)
     
    #define CAN_TSR_CODE_Msk   (0x3UL << CAN_TSR_CODE_Pos)
     
    #define CAN_TSR_CODE   CAN_TSR_CODE_Msk
     
    #define CAN_TSR_TME_Pos   (26U)
     
    #define CAN_TSR_TME_Msk   (0x7UL << CAN_TSR_TME_Pos)
     
    #define CAN_TSR_TME   CAN_TSR_TME_Msk
     
    #define CAN_TSR_TME0_Pos   (26U)
     
    #define CAN_TSR_TME0_Msk   (0x1UL << CAN_TSR_TME0_Pos)
     
    #define CAN_TSR_TME0   CAN_TSR_TME0_Msk
     
    #define CAN_TSR_TME1_Pos   (27U)
     
    #define CAN_TSR_TME1_Msk   (0x1UL << CAN_TSR_TME1_Pos)
     
    #define CAN_TSR_TME1   CAN_TSR_TME1_Msk
     
    #define CAN_TSR_TME2_Pos   (28U)
     
    #define CAN_TSR_TME2_Msk   (0x1UL << CAN_TSR_TME2_Pos)
     
    #define CAN_TSR_TME2   CAN_TSR_TME2_Msk
     
    #define CAN_TSR_LOW_Pos   (29U)
     
    #define CAN_TSR_LOW_Msk   (0x7UL << CAN_TSR_LOW_Pos)
     
    #define CAN_TSR_LOW   CAN_TSR_LOW_Msk
     
    #define CAN_TSR_LOW0_Pos   (29U)
     
    #define CAN_TSR_LOW0_Msk   (0x1UL << CAN_TSR_LOW0_Pos)
     
    #define CAN_TSR_LOW0   CAN_TSR_LOW0_Msk
     
    #define CAN_TSR_LOW1_Pos   (30U)
     
    #define CAN_TSR_LOW1_Msk   (0x1UL << CAN_TSR_LOW1_Pos)
     
    #define CAN_TSR_LOW1   CAN_TSR_LOW1_Msk
     
    #define CAN_TSR_LOW2_Pos   (31U)
     
    #define CAN_TSR_LOW2_Msk   (0x1UL << CAN_TSR_LOW2_Pos)
     
    #define CAN_TSR_LOW2   CAN_TSR_LOW2_Msk
     
    #define CAN_RF0R_FMP0_Pos   (0U)
     
    #define CAN_RF0R_FMP0_Msk   (0x3UL << CAN_RF0R_FMP0_Pos)
     
    #define CAN_RF0R_FMP0   CAN_RF0R_FMP0_Msk
     
    #define CAN_RF0R_FULL0_Pos   (3U)
     
    #define CAN_RF0R_FULL0_Msk   (0x1UL << CAN_RF0R_FULL0_Pos)
     
    #define CAN_RF0R_FULL0   CAN_RF0R_FULL0_Msk
     
    #define CAN_RF0R_FOVR0_Pos   (4U)
     
    #define CAN_RF0R_FOVR0_Msk   (0x1UL << CAN_RF0R_FOVR0_Pos)
     
    #define CAN_RF0R_FOVR0   CAN_RF0R_FOVR0_Msk
     
    #define CAN_RF0R_RFOM0_Pos   (5U)
     
    #define CAN_RF0R_RFOM0_Msk   (0x1UL << CAN_RF0R_RFOM0_Pos)
     
    #define CAN_RF0R_RFOM0   CAN_RF0R_RFOM0_Msk
     
    #define CAN_RF1R_FMP1_Pos   (0U)
     
    #define CAN_RF1R_FMP1_Msk   (0x3UL << CAN_RF1R_FMP1_Pos)
     
    #define CAN_RF1R_FMP1   CAN_RF1R_FMP1_Msk
     
    #define CAN_RF1R_FULL1_Pos   (3U)
     
    #define CAN_RF1R_FULL1_Msk   (0x1UL << CAN_RF1R_FULL1_Pos)
     
    #define CAN_RF1R_FULL1   CAN_RF1R_FULL1_Msk
     
    #define CAN_RF1R_FOVR1_Pos   (4U)
     
    #define CAN_RF1R_FOVR1_Msk   (0x1UL << CAN_RF1R_FOVR1_Pos)
     
    #define CAN_RF1R_FOVR1   CAN_RF1R_FOVR1_Msk
     
    #define CAN_RF1R_RFOM1_Pos   (5U)
     
    #define CAN_RF1R_RFOM1_Msk   (0x1UL << CAN_RF1R_RFOM1_Pos)
     
    #define CAN_RF1R_RFOM1   CAN_RF1R_RFOM1_Msk
     
    #define CAN_IER_TMEIE_Pos   (0U)
     
    #define CAN_IER_TMEIE_Msk   (0x1UL << CAN_IER_TMEIE_Pos)
     
    #define CAN_IER_TMEIE   CAN_IER_TMEIE_Msk
     
    #define CAN_IER_FMPIE0_Pos   (1U)
     
    #define CAN_IER_FMPIE0_Msk   (0x1UL << CAN_IER_FMPIE0_Pos)
     
    #define CAN_IER_FMPIE0   CAN_IER_FMPIE0_Msk
     
    #define CAN_IER_FFIE0_Pos   (2U)
     
    #define CAN_IER_FFIE0_Msk   (0x1UL << CAN_IER_FFIE0_Pos)
     
    #define CAN_IER_FFIE0   CAN_IER_FFIE0_Msk
     
    #define CAN_IER_FOVIE0_Pos   (3U)
     
    #define CAN_IER_FOVIE0_Msk   (0x1UL << CAN_IER_FOVIE0_Pos)
     
    #define CAN_IER_FOVIE0   CAN_IER_FOVIE0_Msk
     
    #define CAN_IER_FMPIE1_Pos   (4U)
     
    #define CAN_IER_FMPIE1_Msk   (0x1UL << CAN_IER_FMPIE1_Pos)
     
    #define CAN_IER_FMPIE1   CAN_IER_FMPIE1_Msk
     
    #define CAN_IER_FFIE1_Pos   (5U)
     
    #define CAN_IER_FFIE1_Msk   (0x1UL << CAN_IER_FFIE1_Pos)
     
    #define CAN_IER_FFIE1   CAN_IER_FFIE1_Msk
     
    #define CAN_IER_FOVIE1_Pos   (6U)
     
    #define CAN_IER_FOVIE1_Msk   (0x1UL << CAN_IER_FOVIE1_Pos)
     
    #define CAN_IER_FOVIE1   CAN_IER_FOVIE1_Msk
     
    #define CAN_IER_EWGIE_Pos   (8U)
     
    #define CAN_IER_EWGIE_Pos   (8U)
     
    #define CAN_IER_EWGIE_Msk   (0x1UL << CAN_IER_EWGIE_Pos)
     
    #define CAN_IER_EWGIE   CAN_IER_EWGIE_Msk
     
    #define CAN_IER_EPVIE_Pos   (9U)
     
    #define CAN_IER_EPVIE_Msk   (0x1UL << CAN_IER_EPVIE_Pos)
     
    #define CAN_IER_EPVIE   CAN_IER_EPVIE_Msk
     
    #define CAN_IER_BOFIE_Pos   (10U)
     
    #define CAN_IER_BOFIE_Msk   (0x1UL << CAN_IER_BOFIE_Pos)
     
    #define CAN_IER_BOFIE   CAN_IER_BOFIE_Msk
     
    #define CAN_IER_LECIE_Pos   (11U)
     
    #define CAN_IER_LECIE_Msk   (0x1UL << CAN_IER_LECIE_Pos)
     
    #define CAN_IER_LECIE   CAN_IER_LECIE_Msk
     
    #define CAN_IER_ERRIE_Pos   (15U)
     
    #define CAN_IER_ERRIE_Msk   (0x1UL << CAN_IER_ERRIE_Pos)
     
    #define CAN_IER_ERRIE   CAN_IER_ERRIE_Msk
     
    #define CAN_IER_WKUIE_Pos   (16U)
     
    #define CAN_IER_WKUIE_Msk   (0x1UL << CAN_IER_WKUIE_Pos)
     
    #define CAN_IER_WKUIE   CAN_IER_WKUIE_Msk
     
    #define CAN_IER_SLKIE_Pos   (17U)
     
    #define CAN_IER_SLKIE_Msk   (0x1UL << CAN_IER_SLKIE_Pos)
     
    #define CAN_IER_SLKIE   CAN_IER_SLKIE_Msk
     
    #define CAN_ESR_EWGF_Pos   (0U)
     
    #define CAN_ESR_EWGF_Msk   (0x1UL << CAN_ESR_EWGF_Pos)
     
    #define CAN_ESR_EWGF   CAN_ESR_EWGF_Msk
     
    #define CAN_ESR_EPVF_Pos   (1U)
     
    #define CAN_ESR_EPVF_Msk   (0x1UL << CAN_ESR_EPVF_Pos)
     
    #define CAN_ESR_EPVF   CAN_ESR_EPVF_Msk
     
    #define CAN_ESR_BOFF_Pos   (2U)
     
    #define CAN_ESR_BOFF_Msk   (0x1UL << CAN_ESR_BOFF_Pos)
     
    #define CAN_ESR_BOFF   CAN_ESR_BOFF_Msk
     
    #define CAN_ESR_LEC_Pos   (4U)
     
    #define CAN_ESR_LEC_Msk   (0x7UL << CAN_ESR_LEC_Pos)
     
    #define CAN_ESR_LEC   CAN_ESR_LEC_Msk
     
    #define CAN_ESR_LEC_0   (0x1UL << CAN_ESR_LEC_Pos)
     
    #define CAN_ESR_LEC_1   (0x2UL << CAN_ESR_LEC_Pos)
     
    #define CAN_ESR_LEC_2   (0x4UL << CAN_ESR_LEC_Pos)
     
    #define CAN_ESR_TEC_Pos   (16U)
     
    #define CAN_ESR_TEC_Msk   (0xFFUL << CAN_ESR_TEC_Pos)
     
    #define CAN_ESR_TEC   CAN_ESR_TEC_Msk
     
    #define CAN_ESR_REC_Pos   (24U)
     
    #define CAN_ESR_REC_Msk   (0xFFUL << CAN_ESR_REC_Pos)
     
    #define CAN_ESR_REC   CAN_ESR_REC_Msk
     
    #define CAN_BTR_BRP_Pos   (0U)
     
    #define CAN_BTR_BRP_Msk   (0x3FFUL << CAN_BTR_BRP_Pos)
     
    #define CAN_BTR_BRP   CAN_BTR_BRP_Msk
     
    #define CAN_BTR_TS1_Pos   (16U)
     
    #define CAN_BTR_TS1_Msk   (0xFUL << CAN_BTR_TS1_Pos)
     
    #define CAN_BTR_TS1   CAN_BTR_TS1_Msk
     
    #define CAN_BTR_TS1_0   (0x1UL << CAN_BTR_TS1_Pos)
     
    #define CAN_BTR_TS1_1   (0x2UL << CAN_BTR_TS1_Pos)
     
    #define CAN_BTR_TS1_2   (0x4UL << CAN_BTR_TS1_Pos)
     
    #define CAN_BTR_TS1_3   (0x8UL << CAN_BTR_TS1_Pos)
     
    #define CAN_BTR_TS2_Pos   (20U)
     
    #define CAN_BTR_TS2_Msk   (0x7UL << CAN_BTR_TS2_Pos)
     
    #define CAN_BTR_TS2   CAN_BTR_TS2_Msk
     
    #define CAN_BTR_TS2_0   (0x1UL << CAN_BTR_TS2_Pos)
     
    #define CAN_BTR_TS2_1   (0x2UL << CAN_BTR_TS2_Pos)
     
    #define CAN_BTR_TS2_2   (0x4UL << CAN_BTR_TS2_Pos)
     
    #define CAN_BTR_SJW_Pos   (24U)
     
    #define CAN_BTR_SJW_Msk   (0x3UL << CAN_BTR_SJW_Pos)
     
    #define CAN_BTR_SJW   CAN_BTR_SJW_Msk
     
    #define CAN_BTR_SJW_0   (0x1UL << CAN_BTR_SJW_Pos)
     
    #define CAN_BTR_SJW_1   (0x2UL << CAN_BTR_SJW_Pos)
     
    #define CAN_BTR_LBKM_Pos   (30U)
     
    #define CAN_BTR_LBKM_Msk   (0x1UL << CAN_BTR_LBKM_Pos)
     
    #define CAN_BTR_LBKM   CAN_BTR_LBKM_Msk
     
    #define CAN_BTR_SILM_Pos   (31U)
     
    #define CAN_BTR_SILM_Msk   (0x1UL << CAN_BTR_SILM_Pos)
     
    #define CAN_BTR_SILM   CAN_BTR_SILM_Msk
     
    #define CAN_TI0R_TXRQ_Pos   (0U)
     
    #define CAN_TI0R_TXRQ_Msk   (0x1UL << CAN_TI0R_TXRQ_Pos)
     
    #define CAN_TI0R_TXRQ   CAN_TI0R_TXRQ_Msk
     
    #define CAN_TI0R_RTR_Pos   (1U)
     
    #define CAN_TI0R_RTR_Msk   (0x1UL << CAN_TI0R_RTR_Pos)
     
    #define CAN_TI0R_RTR   CAN_TI0R_RTR_Msk
     
    #define CAN_TI0R_IDE_Pos   (2U)
     
    #define CAN_TI0R_IDE_Msk   (0x1UL << CAN_TI0R_IDE_Pos)
     
    #define CAN_TI0R_IDE   CAN_TI0R_IDE_Msk
     
    #define CAN_TI0R_EXID_Pos   (3U)
     
    #define CAN_TI0R_EXID_Msk   (0x3FFFFUL << CAN_TI0R_EXID_Pos)
     
    #define CAN_TI0R_EXID   CAN_TI0R_EXID_Msk
     
    #define CAN_TI0R_STID_Pos   (21U)
     
    #define CAN_TI0R_STID_Msk   (0x7FFUL << CAN_TI0R_STID_Pos)
     
    #define CAN_TI0R_STID   CAN_TI0R_STID_Msk
     
    #define CAN_TDT0R_DLC_Pos   (0U)
     
    #define CAN_TDT0R_DLC_Msk   (0xFUL << CAN_TDT0R_DLC_Pos)
     
    #define CAN_TDT0R_DLC   CAN_TDT0R_DLC_Msk
     
    #define CAN_TDT0R_TGT_Pos   (8U)
     
    #define CAN_TDT0R_TGT_Msk   (0x1UL << CAN_TDT0R_TGT_Pos)
     
    #define CAN_TDT0R_TGT   CAN_TDT0R_TGT_Msk
     
    #define CAN_TDT0R_TIME_Pos   (16U)
     
    #define CAN_TDT0R_TIME_Msk   (0xFFFFUL << CAN_TDT0R_TIME_Pos)
     
    #define CAN_TDT0R_TIME   CAN_TDT0R_TIME_Msk
     
    #define CAN_TDL0R_DATA0_Pos   (0U)
     
    #define CAN_TDL0R_DATA0_Msk   (0xFFUL << CAN_TDL0R_DATA0_Pos)
     
    #define CAN_TDL0R_DATA0   CAN_TDL0R_DATA0_Msk
     
    #define CAN_TDL0R_DATA1_Pos   (8U)
     
    #define CAN_TDL0R_DATA1_Msk   (0xFFUL << CAN_TDL0R_DATA1_Pos)
     
    #define CAN_TDL0R_DATA1   CAN_TDL0R_DATA1_Msk
     
    #define CAN_TDL0R_DATA2_Pos   (16U)
     
    #define CAN_TDL0R_DATA2_Msk   (0xFFUL << CAN_TDL0R_DATA2_Pos)
     
    #define CAN_TDL0R_DATA2   CAN_TDL0R_DATA2_Msk
     
    #define CAN_TDL0R_DATA3_Pos   (24U)
     
    #define CAN_TDL0R_DATA3_Msk   (0xFFUL << CAN_TDL0R_DATA3_Pos)
     
    #define CAN_TDL0R_DATA3   CAN_TDL0R_DATA3_Msk
     
    #define CAN_TDH0R_DATA4_Pos   (0U)
     
    #define CAN_TDH0R_DATA4_Msk   (0xFFUL << CAN_TDH0R_DATA4_Pos)
     
    #define CAN_TDH0R_DATA4   CAN_TDH0R_DATA4_Msk
     
    #define CAN_TDH0R_DATA5_Pos   (8U)
     
    #define CAN_TDH0R_DATA5_Msk   (0xFFUL << CAN_TDH0R_DATA5_Pos)
     
    #define CAN_TDH0R_DATA5   CAN_TDH0R_DATA5_Msk
     
    #define CAN_TDH0R_DATA6_Pos   (16U)
     
    #define CAN_TDH0R_DATA6_Msk   (0xFFUL << CAN_TDH0R_DATA6_Pos)
     
    #define CAN_TDH0R_DATA6   CAN_TDH0R_DATA6_Msk
     
    #define CAN_TDH0R_DATA7_Pos   (24U)
     
    #define CAN_TDH0R_DATA7_Msk   (0xFFUL << CAN_TDH0R_DATA7_Pos)
     
    #define CAN_TDH0R_DATA7   CAN_TDH0R_DATA7_Msk
     
    #define CAN_TI1R_TXRQ_Pos   (0U)
     
    #define CAN_TI1R_TXRQ_Msk   (0x1UL << CAN_TI1R_TXRQ_Pos)
     
    #define CAN_TI1R_TXRQ   CAN_TI1R_TXRQ_Msk
     
    #define CAN_TI1R_RTR_Pos   (1U)
     
    #define CAN_TI1R_RTR_Msk   (0x1UL << CAN_TI1R_RTR_Pos)
     
    #define CAN_TI1R_RTR   CAN_TI1R_RTR_Msk
     
    #define CAN_TI1R_IDE_Pos   (2U)
     
    #define CAN_TI1R_IDE_Msk   (0x1UL << CAN_TI1R_IDE_Pos)
     
    #define CAN_TI1R_IDE   CAN_TI1R_IDE_Msk
     
    #define CAN_TI1R_EXID_Pos   (3U)
     
    #define CAN_TI1R_EXID_Msk   (0x3FFFFUL << CAN_TI1R_EXID_Pos)
     
    #define CAN_TI1R_EXID   CAN_TI1R_EXID_Msk
     
    #define CAN_TI1R_STID_Pos   (21U)
     
    #define CAN_TI1R_STID_Msk   (0x7FFUL << CAN_TI1R_STID_Pos)
     
    #define CAN_TI1R_STID   CAN_TI1R_STID_Msk
     
    #define CAN_TDT1R_DLC_Pos   (0U)
     
    #define CAN_TDT1R_DLC_Msk   (0xFUL << CAN_TDT1R_DLC_Pos)
     
    #define CAN_TDT1R_DLC   CAN_TDT1R_DLC_Msk
     
    #define CAN_TDT1R_TGT_Pos   (8U)
     
    #define CAN_TDT1R_TGT_Msk   (0x1UL << CAN_TDT1R_TGT_Pos)
     
    #define CAN_TDT1R_TGT   CAN_TDT1R_TGT_Msk
     
    #define CAN_TDT1R_TIME_Pos   (16U)
     
    #define CAN_TDT1R_TIME_Msk   (0xFFFFUL << CAN_TDT1R_TIME_Pos)
     
    #define CAN_TDT1R_TIME   CAN_TDT1R_TIME_Msk
     
    #define CAN_TDL1R_DATA0_Pos   (0U)
     
    #define CAN_TDL1R_DATA0_Msk   (0xFFUL << CAN_TDL1R_DATA0_Pos)
     
    #define CAN_TDL1R_DATA0   CAN_TDL1R_DATA0_Msk
     
    #define CAN_TDL1R_DATA1_Pos   (8U)
     
    #define CAN_TDL1R_DATA1_Msk   (0xFFUL << CAN_TDL1R_DATA1_Pos)
     
    #define CAN_TDL1R_DATA1   CAN_TDL1R_DATA1_Msk
     
    #define CAN_TDL1R_DATA2_Pos   (16U)
     
    #define CAN_TDL1R_DATA2_Msk   (0xFFUL << CAN_TDL1R_DATA2_Pos)
     
    #define CAN_TDL1R_DATA2   CAN_TDL1R_DATA2_Msk
     
    #define CAN_TDL1R_DATA3_Pos   (24U)
     
    #define CAN_TDL1R_DATA3_Msk   (0xFFUL << CAN_TDL1R_DATA3_Pos)
     
    #define CAN_TDL1R_DATA3   CAN_TDL1R_DATA3_Msk
     
    #define CAN_TDH1R_DATA4_Pos   (0U)
     
    #define CAN_TDH1R_DATA4_Msk   (0xFFUL << CAN_TDH1R_DATA4_Pos)
     
    #define CAN_TDH1R_DATA4   CAN_TDH1R_DATA4_Msk
     
    #define CAN_TDH1R_DATA5_Pos   (8U)
     
    #define CAN_TDH1R_DATA5_Msk   (0xFFUL << CAN_TDH1R_DATA5_Pos)
     
    #define CAN_TDH1R_DATA5   CAN_TDH1R_DATA5_Msk
     
    #define CAN_TDH1R_DATA6_Pos   (16U)
     
    #define CAN_TDH1R_DATA6_Msk   (0xFFUL << CAN_TDH1R_DATA6_Pos)
     
    #define CAN_TDH1R_DATA6   CAN_TDH1R_DATA6_Msk
     
    #define CAN_TDH1R_DATA7_Pos   (24U)
     
    #define CAN_TDH1R_DATA7_Msk   (0xFFUL << CAN_TDH1R_DATA7_Pos)
     
    #define CAN_TDH1R_DATA7   CAN_TDH1R_DATA7_Msk
     
    #define CAN_TI2R_TXRQ_Pos   (0U)
     
    #define CAN_TI2R_TXRQ_Msk   (0x1UL << CAN_TI2R_TXRQ_Pos)
     
    #define CAN_TI2R_TXRQ   CAN_TI2R_TXRQ_Msk
     
    #define CAN_TI2R_RTR_Pos   (1U)
     
    #define CAN_TI2R_RTR_Msk   (0x1UL << CAN_TI2R_RTR_Pos)
     
    #define CAN_TI2R_RTR   CAN_TI2R_RTR_Msk
     
    #define CAN_TI2R_IDE_Pos   (2U)
     
    #define CAN_TI2R_IDE_Msk   (0x1UL << CAN_TI2R_IDE_Pos)
     
    #define CAN_TI2R_IDE   CAN_TI2R_IDE_Msk
     
    #define CAN_TI2R_EXID_Pos   (3U)
     
    #define CAN_TI2R_EXID_Msk   (0x3FFFFUL << CAN_TI2R_EXID_Pos)
     
    #define CAN_TI2R_EXID   CAN_TI2R_EXID_Msk
     
    #define CAN_TI2R_STID_Pos   (21U)
     
    #define CAN_TI2R_STID_Msk   (0x7FFUL << CAN_TI2R_STID_Pos)
     
    #define CAN_TI2R_STID   CAN_TI2R_STID_Msk
     
    #define CAN_TDT2R_DLC_Pos   (0U)
     
    #define CAN_TDT2R_DLC_Msk   (0xFUL << CAN_TDT2R_DLC_Pos)
     
    #define CAN_TDT2R_DLC   CAN_TDT2R_DLC_Msk
     
    #define CAN_TDT2R_TGT_Pos   (8U)
     
    #define CAN_TDT2R_TGT_Msk   (0x1UL << CAN_TDT2R_TGT_Pos)
     
    #define CAN_TDT2R_TGT   CAN_TDT2R_TGT_Msk
     
    #define CAN_TDT2R_TIME_Pos   (16U)
     
    #define CAN_TDT2R_TIME_Msk   (0xFFFFUL << CAN_TDT2R_TIME_Pos)
     
    #define CAN_TDT2R_TIME   CAN_TDT2R_TIME_Msk
     
    #define CAN_TDL2R_DATA0_Pos   (0U)
     
    #define CAN_TDL2R_DATA0_Msk   (0xFFUL << CAN_TDL2R_DATA0_Pos)
     
    #define CAN_TDL2R_DATA0   CAN_TDL2R_DATA0_Msk
     
    #define CAN_TDL2R_DATA1_Pos   (8U)
     
    #define CAN_TDL2R_DATA1_Msk   (0xFFUL << CAN_TDL2R_DATA1_Pos)
     
    #define CAN_TDL2R_DATA1   CAN_TDL2R_DATA1_Msk
     
    #define CAN_TDL2R_DATA2_Pos   (16U)
     
    #define CAN_TDL2R_DATA2_Msk   (0xFFUL << CAN_TDL2R_DATA2_Pos)
     
    #define CAN_TDL2R_DATA2   CAN_TDL2R_DATA2_Msk
     
    #define CAN_TDL2R_DATA3_Pos   (24U)
     
    #define CAN_TDL2R_DATA3_Msk   (0xFFUL << CAN_TDL2R_DATA3_Pos)
     
    #define CAN_TDL2R_DATA3   CAN_TDL2R_DATA3_Msk
     
    #define CAN_TDH2R_DATA4_Pos   (0U)
     
    #define CAN_TDH2R_DATA4_Msk   (0xFFUL << CAN_TDH2R_DATA4_Pos)
     
    #define CAN_TDH2R_DATA4   CAN_TDH2R_DATA4_Msk
     
    #define CAN_TDH2R_DATA5_Pos   (8U)
     
    #define CAN_TDH2R_DATA5_Msk   (0xFFUL << CAN_TDH2R_DATA5_Pos)
     
    #define CAN_TDH2R_DATA5   CAN_TDH2R_DATA5_Msk
     
    #define CAN_TDH2R_DATA6_Pos   (16U)
     
    #define CAN_TDH2R_DATA6_Msk   (0xFFUL << CAN_TDH2R_DATA6_Pos)
     
    #define CAN_TDH2R_DATA6   CAN_TDH2R_DATA6_Msk
     
    #define CAN_TDH2R_DATA7_Pos   (24U)
     
    #define CAN_TDH2R_DATA7_Msk   (0xFFUL << CAN_TDH2R_DATA7_Pos)
     
    #define CAN_TDH2R_DATA7   CAN_TDH2R_DATA7_Msk
     
    #define CAN_RI0R_RTR_Pos   (1U)
     
    #define CAN_RI0R_RTR_Msk   (0x1UL << CAN_RI0R_RTR_Pos)
     
    #define CAN_RI0R_RTR   CAN_RI0R_RTR_Msk
     
    #define CAN_RI0R_IDE_Pos   (2U)
     
    #define CAN_RI0R_IDE_Msk   (0x1UL << CAN_RI0R_IDE_Pos)
     
    #define CAN_RI0R_IDE   CAN_RI0R_IDE_Msk
     
    #define CAN_RI0R_EXID_Pos   (3U)
     
    #define CAN_RI0R_EXID_Msk   (0x3FFFFUL << CAN_RI0R_EXID_Pos)
     
    #define CAN_RI0R_EXID   CAN_RI0R_EXID_Msk
     
    #define CAN_RI0R_STID_Pos   (21U)
     
    #define CAN_RI0R_STID_Msk   (0x7FFUL << CAN_RI0R_STID_Pos)
     
    #define CAN_RI0R_STID   CAN_RI0R_STID_Msk
     
    #define CAN_RDT0R_DLC_Pos   (0U)
     
    #define CAN_RDT0R_DLC_Msk   (0xFUL << CAN_RDT0R_DLC_Pos)
     
    #define CAN_RDT0R_DLC   CAN_RDT0R_DLC_Msk
     
    #define CAN_RDT0R_FMI_Pos   (8U)
     
    #define CAN_RDT0R_FMI_Msk   (0xFFUL << CAN_RDT0R_FMI_Pos)
     
    #define CAN_RDT0R_FMI   CAN_RDT0R_FMI_Msk
     
    #define CAN_RDT0R_TIME_Pos   (16U)
     
    #define CAN_RDT0R_TIME_Msk   (0xFFFFUL << CAN_RDT0R_TIME_Pos)
     
    #define CAN_RDT0R_TIME   CAN_RDT0R_TIME_Msk
     
    #define CAN_RDL0R_DATA0_Pos   (0U)
     
    #define CAN_RDL0R_DATA0_Msk   (0xFFUL << CAN_RDL0R_DATA0_Pos)
     
    #define CAN_RDL0R_DATA0   CAN_RDL0R_DATA0_Msk
     
    #define CAN_RDL0R_DATA1_Pos   (8U)
     
    #define CAN_RDL0R_DATA1_Msk   (0xFFUL << CAN_RDL0R_DATA1_Pos)
     
    #define CAN_RDL0R_DATA1   CAN_RDL0R_DATA1_Msk
     
    #define CAN_RDL0R_DATA2_Pos   (16U)
     
    #define CAN_RDL0R_DATA2_Msk   (0xFFUL << CAN_RDL0R_DATA2_Pos)
     
    #define CAN_RDL0R_DATA2   CAN_RDL0R_DATA2_Msk
     
    #define CAN_RDL0R_DATA3_Pos   (24U)
     
    #define CAN_RDL0R_DATA3_Msk   (0xFFUL << CAN_RDL0R_DATA3_Pos)
     
    #define CAN_RDL0R_DATA3   CAN_RDL0R_DATA3_Msk
     
    #define CAN_RDH0R_DATA4_Pos   (0U)
     
    #define CAN_RDH0R_DATA4_Msk   (0xFFUL << CAN_RDH0R_DATA4_Pos)
     
    #define CAN_RDH0R_DATA4   CAN_RDH0R_DATA4_Msk
     
    #define CAN_RDH0R_DATA5_Pos   (8U)
     
    #define CAN_RDH0R_DATA5_Msk   (0xFFUL << CAN_RDH0R_DATA5_Pos)
     
    #define CAN_RDH0R_DATA5   CAN_RDH0R_DATA5_Msk
     
    #define CAN_RDH0R_DATA6_Pos   (16U)
     
    #define CAN_RDH0R_DATA6_Msk   (0xFFUL << CAN_RDH0R_DATA6_Pos)
     
    #define CAN_RDH0R_DATA6   CAN_RDH0R_DATA6_Msk
     
    #define CAN_RDH0R_DATA7_Pos   (24U)
     
    #define CAN_RDH0R_DATA7_Msk   (0xFFUL << CAN_RDH0R_DATA7_Pos)
     
    #define CAN_RDH0R_DATA7   CAN_RDH0R_DATA7_Msk
     
    #define CAN_RI1R_RTR_Pos   (1U)
     
    #define CAN_RI1R_RTR_Msk   (0x1UL << CAN_RI1R_RTR_Pos)
     
    #define CAN_RI1R_RTR   CAN_RI1R_RTR_Msk
     
    #define CAN_RI1R_IDE_Pos   (2U)
     
    #define CAN_RI1R_IDE_Msk   (0x1UL << CAN_RI1R_IDE_Pos)
     
    #define CAN_RI1R_IDE   CAN_RI1R_IDE_Msk
     
    #define CAN_RI1R_EXID_Pos   (3U)
     
    #define CAN_RI1R_EXID_Msk   (0x3FFFFUL << CAN_RI1R_EXID_Pos)
     
    #define CAN_RI1R_EXID   CAN_RI1R_EXID_Msk
     
    #define CAN_RI1R_STID_Pos   (21U)
     
    #define CAN_RI1R_STID_Msk   (0x7FFUL << CAN_RI1R_STID_Pos)
     
    #define CAN_RI1R_STID   CAN_RI1R_STID_Msk
     
    #define CAN_RDT1R_DLC_Pos   (0U)
     
    #define CAN_RDT1R_DLC_Msk   (0xFUL << CAN_RDT1R_DLC_Pos)
     
    #define CAN_RDT1R_DLC   CAN_RDT1R_DLC_Msk
     
    #define CAN_RDT1R_FMI_Pos   (8U)
     
    #define CAN_RDT1R_FMI_Msk   (0xFFUL << CAN_RDT1R_FMI_Pos)
     
    #define CAN_RDT1R_FMI   CAN_RDT1R_FMI_Msk
     
    #define CAN_RDT1R_TIME_Pos   (16U)
     
    #define CAN_RDT1R_TIME_Msk   (0xFFFFUL << CAN_RDT1R_TIME_Pos)
     
    #define CAN_RDT1R_TIME   CAN_RDT1R_TIME_Msk
     
    #define CAN_RDL1R_DATA0_Pos   (0U)
     
    #define CAN_RDL1R_DATA0_Msk   (0xFFUL << CAN_RDL1R_DATA0_Pos)
     
    #define CAN_RDL1R_DATA0   CAN_RDL1R_DATA0_Msk
     
    #define CAN_RDL1R_DATA1_Pos   (8U)
     
    #define CAN_RDL1R_DATA1_Msk   (0xFFUL << CAN_RDL1R_DATA1_Pos)
     
    #define CAN_RDL1R_DATA1   CAN_RDL1R_DATA1_Msk
     
    #define CAN_RDL1R_DATA2_Pos   (16U)
     
    #define CAN_RDL1R_DATA2_Msk   (0xFFUL << CAN_RDL1R_DATA2_Pos)
     
    #define CAN_RDL1R_DATA2   CAN_RDL1R_DATA2_Msk
     
    #define CAN_RDL1R_DATA3_Pos   (24U)
     
    #define CAN_RDL1R_DATA3_Msk   (0xFFUL << CAN_RDL1R_DATA3_Pos)
     
    #define CAN_RDL1R_DATA3   CAN_RDL1R_DATA3_Msk
     
    #define CAN_RDH1R_DATA4_Pos   (0U)
     
    #define CAN_RDH1R_DATA4_Msk   (0xFFUL << CAN_RDH1R_DATA4_Pos)
     
    #define CAN_RDH1R_DATA4   CAN_RDH1R_DATA4_Msk
     
    #define CAN_RDH1R_DATA5_Pos   (8U)
     
    #define CAN_RDH1R_DATA5_Msk   (0xFFUL << CAN_RDH1R_DATA5_Pos)
     
    #define CAN_RDH1R_DATA5   CAN_RDH1R_DATA5_Msk
     
    #define CAN_RDH1R_DATA6_Pos   (16U)
     
    #define CAN_RDH1R_DATA6_Msk   (0xFFUL << CAN_RDH1R_DATA6_Pos)
     
    #define CAN_RDH1R_DATA6   CAN_RDH1R_DATA6_Msk
     
    #define CAN_RDH1R_DATA7_Pos   (24U)
     
    #define CAN_RDH1R_DATA7_Msk   (0xFFUL << CAN_RDH1R_DATA7_Pos)
     
    #define CAN_RDH1R_DATA7   CAN_RDH1R_DATA7_Msk
     
    #define CAN_FMR_FINIT_Pos   (0U)
     
    #define CAN_FMR_FINIT_Msk   (0x1UL << CAN_FMR_FINIT_Pos)
     
    #define CAN_FMR_FINIT   CAN_FMR_FINIT_Msk
     
    #define CAN_FMR_CAN2SB_Pos   (8U)
     
    #define CAN_FMR_CAN2SB_Msk   (0x3FUL << CAN_FMR_CAN2SB_Pos)
     
    #define CAN_FMR_CAN2SB   CAN_FMR_CAN2SB_Msk
     
    #define CAN_FM1R_FBM_Pos   (0U)
     
    #define CAN_FM1R_FBM_Msk   (0xFFFFFFFUL << CAN_FM1R_FBM_Pos)
     
    #define CAN_FM1R_FBM   CAN_FM1R_FBM_Msk
     
    #define CAN_FM1R_FBM0_Pos   (0U)
     
    #define CAN_FM1R_FBM0_Msk   (0x1UL << CAN_FM1R_FBM0_Pos)
     
    #define CAN_FM1R_FBM0   CAN_FM1R_FBM0_Msk
     
    #define CAN_FM1R_FBM1_Pos   (1U)
     
    #define CAN_FM1R_FBM1_Msk   (0x1UL << CAN_FM1R_FBM1_Pos)
     
    #define CAN_FM1R_FBM1   CAN_FM1R_FBM1_Msk
     
    #define CAN_FM1R_FBM2_Pos   (2U)
     
    #define CAN_FM1R_FBM2_Msk   (0x1UL << CAN_FM1R_FBM2_Pos)
     
    #define CAN_FM1R_FBM2   CAN_FM1R_FBM2_Msk
     
    #define CAN_FM1R_FBM3_Pos   (3U)
     
    #define CAN_FM1R_FBM3_Msk   (0x1UL << CAN_FM1R_FBM3_Pos)
     
    #define CAN_FM1R_FBM3   CAN_FM1R_FBM3_Msk
     
    #define CAN_FM1R_FBM4_Pos   (4U)
     
    #define CAN_FM1R_FBM4_Msk   (0x1UL << CAN_FM1R_FBM4_Pos)
     
    #define CAN_FM1R_FBM4   CAN_FM1R_FBM4_Msk
     
    #define CAN_FM1R_FBM5_Pos   (5U)
     
    #define CAN_FM1R_FBM5_Msk   (0x1UL << CAN_FM1R_FBM5_Pos)
     
    #define CAN_FM1R_FBM5   CAN_FM1R_FBM5_Msk
     
    #define CAN_FM1R_FBM6_Pos   (6U)
     
    #define CAN_FM1R_FBM6_Msk   (0x1UL << CAN_FM1R_FBM6_Pos)
     
    #define CAN_FM1R_FBM6   CAN_FM1R_FBM6_Msk
     
    #define CAN_FM1R_FBM7_Pos   (7U)
     
    #define CAN_FM1R_FBM7_Msk   (0x1UL << CAN_FM1R_FBM7_Pos)
     
    #define CAN_FM1R_FBM7   CAN_FM1R_FBM7_Msk
     
    #define CAN_FM1R_FBM8_Pos   (8U)
     
    #define CAN_FM1R_FBM8_Msk   (0x1UL << CAN_FM1R_FBM8_Pos)
     
    #define CAN_FM1R_FBM8   CAN_FM1R_FBM8_Msk
     
    #define CAN_FM1R_FBM9_Pos   (9U)
     
    #define CAN_FM1R_FBM9_Msk   (0x1UL << CAN_FM1R_FBM9_Pos)
     
    #define CAN_FM1R_FBM9   CAN_FM1R_FBM9_Msk
     
    #define CAN_FM1R_FBM10_Pos   (10U)
     
    #define CAN_FM1R_FBM10_Msk   (0x1UL << CAN_FM1R_FBM10_Pos)
     
    #define CAN_FM1R_FBM10   CAN_FM1R_FBM10_Msk
     
    #define CAN_FM1R_FBM11_Pos   (11U)
     
    #define CAN_FM1R_FBM11_Msk   (0x1UL << CAN_FM1R_FBM11_Pos)
     
    #define CAN_FM1R_FBM11   CAN_FM1R_FBM11_Msk
     
    #define CAN_FM1R_FBM12_Pos   (12U)
     
    #define CAN_FM1R_FBM12_Msk   (0x1UL << CAN_FM1R_FBM12_Pos)
     
    #define CAN_FM1R_FBM12   CAN_FM1R_FBM12_Msk
     
    #define CAN_FM1R_FBM13_Pos   (13U)
     
    #define CAN_FM1R_FBM13_Msk   (0x1UL << CAN_FM1R_FBM13_Pos)
     
    #define CAN_FM1R_FBM13   CAN_FM1R_FBM13_Msk
     
    #define CAN_FM1R_FBM14_Pos   (14U)
     
    #define CAN_FM1R_FBM14_Msk   (0x1UL << CAN_FM1R_FBM14_Pos)
     
    #define CAN_FM1R_FBM14   CAN_FM1R_FBM14_Msk
     
    #define CAN_FM1R_FBM15_Pos   (15U)
     
    #define CAN_FM1R_FBM15_Msk   (0x1UL << CAN_FM1R_FBM15_Pos)
     
    #define CAN_FM1R_FBM15   CAN_FM1R_FBM15_Msk
     
    #define CAN_FM1R_FBM16_Pos   (16U)
     
    #define CAN_FM1R_FBM16_Msk   (0x1UL << CAN_FM1R_FBM16_Pos)
     
    #define CAN_FM1R_FBM16   CAN_FM1R_FBM16_Msk
     
    #define CAN_FM1R_FBM17_Pos   (17U)
     
    #define CAN_FM1R_FBM17_Msk   (0x1UL << CAN_FM1R_FBM17_Pos)
     
    #define CAN_FM1R_FBM17   CAN_FM1R_FBM17_Msk
     
    #define CAN_FM1R_FBM18_Pos   (18U)
     
    #define CAN_FM1R_FBM18_Msk   (0x1UL << CAN_FM1R_FBM18_Pos)
     
    #define CAN_FM1R_FBM18   CAN_FM1R_FBM18_Msk
     
    #define CAN_FM1R_FBM19_Pos   (19U)
     
    #define CAN_FM1R_FBM19_Msk   (0x1UL << CAN_FM1R_FBM19_Pos)
     
    #define CAN_FM1R_FBM19   CAN_FM1R_FBM19_Msk
     
    #define CAN_FM1R_FBM20_Pos   (20U)
     
    #define CAN_FM1R_FBM20_Msk   (0x1UL << CAN_FM1R_FBM20_Pos)
     
    #define CAN_FM1R_FBM20   CAN_FM1R_FBM20_Msk
     
    #define CAN_FM1R_FBM21_Pos   (21U)
     
    #define CAN_FM1R_FBM21_Msk   (0x1UL << CAN_FM1R_FBM21_Pos)
     
    #define CAN_FM1R_FBM21   CAN_FM1R_FBM21_Msk
     
    #define CAN_FM1R_FBM22_Pos   (22U)
     
    #define CAN_FM1R_FBM22_Msk   (0x1UL << CAN_FM1R_FBM22_Pos)
     
    #define CAN_FM1R_FBM22   CAN_FM1R_FBM22_Msk
     
    #define CAN_FM1R_FBM23_Pos   (23U)
     
    #define CAN_FM1R_FBM23_Msk   (0x1UL << CAN_FM1R_FBM23_Pos)
     
    #define CAN_FM1R_FBM23   CAN_FM1R_FBM23_Msk
     
    #define CAN_FM1R_FBM24_Pos   (24U)
     
    #define CAN_FM1R_FBM24_Msk   (0x1UL << CAN_FM1R_FBM24_Pos)
     
    #define CAN_FM1R_FBM24   CAN_FM1R_FBM24_Msk
     
    #define CAN_FM1R_FBM25_Pos   (25U)
     
    #define CAN_FM1R_FBM25_Msk   (0x1UL << CAN_FM1R_FBM25_Pos)
     
    #define CAN_FM1R_FBM25   CAN_FM1R_FBM25_Msk
     
    #define CAN_FM1R_FBM26_Pos   (26U)
     
    #define CAN_FM1R_FBM26_Msk   (0x1UL << CAN_FM1R_FBM26_Pos)
     
    #define CAN_FM1R_FBM26   CAN_FM1R_FBM26_Msk
     
    #define CAN_FM1R_FBM27_Pos   (27U)
     
    #define CAN_FM1R_FBM27_Msk   (0x1UL << CAN_FM1R_FBM27_Pos)
     
    #define CAN_FM1R_FBM27   CAN_FM1R_FBM27_Msk
     
    #define CAN_FS1R_FSC_Pos   (0U)
     
    #define CAN_FS1R_FSC_Msk   (0xFFFFFFFUL << CAN_FS1R_FSC_Pos)
     
    #define CAN_FS1R_FSC   CAN_FS1R_FSC_Msk
     
    #define CAN_FS1R_FSC0_Pos   (0U)
     
    #define CAN_FS1R_FSC0_Msk   (0x1UL << CAN_FS1R_FSC0_Pos)
     
    #define CAN_FS1R_FSC0   CAN_FS1R_FSC0_Msk
     
    #define CAN_FS1R_FSC1_Pos   (1U)
     
    #define CAN_FS1R_FSC1_Msk   (0x1UL << CAN_FS1R_FSC1_Pos)
     
    #define CAN_FS1R_FSC1   CAN_FS1R_FSC1_Msk
     
    #define CAN_FS1R_FSC2_Pos   (2U)
     
    #define CAN_FS1R_FSC2_Msk   (0x1UL << CAN_FS1R_FSC2_Pos)
     
    #define CAN_FS1R_FSC2   CAN_FS1R_FSC2_Msk
     
    #define CAN_FS1R_FSC3_Pos   (3U)
     
    #define CAN_FS1R_FSC3_Msk   (0x1UL << CAN_FS1R_FSC3_Pos)
     
    #define CAN_FS1R_FSC3   CAN_FS1R_FSC3_Msk
     
    #define CAN_FS1R_FSC4_Pos   (4U)
     
    #define CAN_FS1R_FSC4_Msk   (0x1UL << CAN_FS1R_FSC4_Pos)
     
    #define CAN_FS1R_FSC4   CAN_FS1R_FSC4_Msk
     
    #define CAN_FS1R_FSC5_Pos   (5U)
     
    #define CAN_FS1R_FSC5_Msk   (0x1UL << CAN_FS1R_FSC5_Pos)
     
    #define CAN_FS1R_FSC5   CAN_FS1R_FSC5_Msk
     
    #define CAN_FS1R_FSC6_Pos   (6U)
     
    #define CAN_FS1R_FSC6_Msk   (0x1UL << CAN_FS1R_FSC6_Pos)
     
    #define CAN_FS1R_FSC6   CAN_FS1R_FSC6_Msk
     
    #define CAN_FS1R_FSC7_Pos   (7U)
     
    #define CAN_FS1R_FSC7_Msk   (0x1UL << CAN_FS1R_FSC7_Pos)
     
    #define CAN_FS1R_FSC7   CAN_FS1R_FSC7_Msk
     
    #define CAN_FS1R_FSC8_Pos   (8U)
     
    #define CAN_FS1R_FSC8_Msk   (0x1UL << CAN_FS1R_FSC8_Pos)
     
    #define CAN_FS1R_FSC8   CAN_FS1R_FSC8_Msk
     
    #define CAN_FS1R_FSC9_Pos   (9U)
     
    #define CAN_FS1R_FSC9_Msk   (0x1UL << CAN_FS1R_FSC9_Pos)
     
    #define CAN_FS1R_FSC9   CAN_FS1R_FSC9_Msk
     
    #define CAN_FS1R_FSC10_Pos   (10U)
     
    #define CAN_FS1R_FSC10_Msk   (0x1UL << CAN_FS1R_FSC10_Pos)
     
    #define CAN_FS1R_FSC10   CAN_FS1R_FSC10_Msk
     
    #define CAN_FS1R_FSC11_Pos   (11U)
     
    #define CAN_FS1R_FSC11_Msk   (0x1UL << CAN_FS1R_FSC11_Pos)
     
    #define CAN_FS1R_FSC11   CAN_FS1R_FSC11_Msk
     
    #define CAN_FS1R_FSC12_Pos   (12U)
     
    #define CAN_FS1R_FSC12_Msk   (0x1UL << CAN_FS1R_FSC12_Pos)
     
    #define CAN_FS1R_FSC12   CAN_FS1R_FSC12_Msk
     
    #define CAN_FS1R_FSC13_Pos   (13U)
     
    #define CAN_FS1R_FSC13_Msk   (0x1UL << CAN_FS1R_FSC13_Pos)
     
    #define CAN_FS1R_FSC13   CAN_FS1R_FSC13_Msk
     
    #define CAN_FS1R_FSC14_Pos   (14U)
     
    #define CAN_FS1R_FSC14_Msk   (0x1UL << CAN_FS1R_FSC14_Pos)
     
    #define CAN_FS1R_FSC14   CAN_FS1R_FSC14_Msk
     
    #define CAN_FS1R_FSC15_Pos   (15U)
     
    #define CAN_FS1R_FSC15_Msk   (0x1UL << CAN_FS1R_FSC15_Pos)
     
    #define CAN_FS1R_FSC15   CAN_FS1R_FSC15_Msk
     
    #define CAN_FS1R_FSC16_Pos   (16U)
     
    #define CAN_FS1R_FSC16_Msk   (0x1UL << CAN_FS1R_FSC16_Pos)
     
    #define CAN_FS1R_FSC16   CAN_FS1R_FSC16_Msk
     
    #define CAN_FS1R_FSC17_Pos   (17U)
     
    #define CAN_FS1R_FSC17_Msk   (0x1UL << CAN_FS1R_FSC17_Pos)
     
    #define CAN_FS1R_FSC17   CAN_FS1R_FSC17_Msk
     
    #define CAN_FS1R_FSC18_Pos   (18U)
     
    #define CAN_FS1R_FSC18_Msk   (0x1UL << CAN_FS1R_FSC18_Pos)
     
    #define CAN_FS1R_FSC18   CAN_FS1R_FSC18_Msk
     
    #define CAN_FS1R_FSC19_Pos   (19U)
     
    #define CAN_FS1R_FSC19_Msk   (0x1UL << CAN_FS1R_FSC19_Pos)
     
    #define CAN_FS1R_FSC19   CAN_FS1R_FSC19_Msk
     
    #define CAN_FS1R_FSC20_Pos   (20U)
     
    #define CAN_FS1R_FSC20_Msk   (0x1UL << CAN_FS1R_FSC20_Pos)
     
    #define CAN_FS1R_FSC20   CAN_FS1R_FSC20_Msk
     
    #define CAN_FS1R_FSC21_Pos   (21U)
     
    #define CAN_FS1R_FSC21_Msk   (0x1UL << CAN_FS1R_FSC21_Pos)
     
    #define CAN_FS1R_FSC21   CAN_FS1R_FSC21_Msk
     
    #define CAN_FS1R_FSC22_Pos   (22U)
     
    #define CAN_FS1R_FSC22_Msk   (0x1UL << CAN_FS1R_FSC22_Pos)
     
    #define CAN_FS1R_FSC22   CAN_FS1R_FSC22_Msk
     
    #define CAN_FS1R_FSC23_Pos   (23U)
     
    #define CAN_FS1R_FSC23_Msk   (0x1UL << CAN_FS1R_FSC23_Pos)
     
    #define CAN_FS1R_FSC23   CAN_FS1R_FSC23_Msk
     
    #define CAN_FS1R_FSC24_Pos   (24U)
     
    #define CAN_FS1R_FSC24_Msk   (0x1UL << CAN_FS1R_FSC24_Pos)
     
    #define CAN_FS1R_FSC24   CAN_FS1R_FSC24_Msk
     
    #define CAN_FS1R_FSC25_Pos   (25U)
     
    #define CAN_FS1R_FSC25_Msk   (0x1UL << CAN_FS1R_FSC25_Pos)
     
    #define CAN_FS1R_FSC25   CAN_FS1R_FSC25_Msk
     
    #define CAN_FS1R_FSC26_Pos   (26U)
     
    #define CAN_FS1R_FSC26_Msk   (0x1UL << CAN_FS1R_FSC26_Pos)
     
    #define CAN_FS1R_FSC26   CAN_FS1R_FSC26_Msk
     
    #define CAN_FS1R_FSC27_Pos   (27U)
     
    #define CAN_FS1R_FSC27_Msk   (0x1UL << CAN_FS1R_FSC27_Pos)
     
    #define CAN_FS1R_FSC27   CAN_FS1R_FSC27_Msk
     
    #define CAN_FFA1R_FFA_Pos   (0U)
     
    #define CAN_FFA1R_FFA_Msk   (0xFFFFFFFUL << CAN_FFA1R_FFA_Pos)
     
    #define CAN_FFA1R_FFA   CAN_FFA1R_FFA_Msk
     
    #define CAN_FFA1R_FFA0_Pos   (0U)
     
    #define CAN_FFA1R_FFA0_Msk   (0x1UL << CAN_FFA1R_FFA0_Pos)
     
    #define CAN_FFA1R_FFA0   CAN_FFA1R_FFA0_Msk
     
    #define CAN_FFA1R_FFA1_Pos   (1U)
     
    #define CAN_FFA1R_FFA1_Msk   (0x1UL << CAN_FFA1R_FFA1_Pos)
     
    #define CAN_FFA1R_FFA1   CAN_FFA1R_FFA1_Msk
     
    #define CAN_FFA1R_FFA2_Pos   (2U)
     
    #define CAN_FFA1R_FFA2_Msk   (0x1UL << CAN_FFA1R_FFA2_Pos)
     
    #define CAN_FFA1R_FFA2   CAN_FFA1R_FFA2_Msk
     
    #define CAN_FFA1R_FFA3_Pos   (3U)
     
    #define CAN_FFA1R_FFA3_Msk   (0x1UL << CAN_FFA1R_FFA3_Pos)
     
    #define CAN_FFA1R_FFA3   CAN_FFA1R_FFA3_Msk
     
    #define CAN_FFA1R_FFA4_Pos   (4U)
     
    #define CAN_FFA1R_FFA4_Msk   (0x1UL << CAN_FFA1R_FFA4_Pos)
     
    #define CAN_FFA1R_FFA4   CAN_FFA1R_FFA4_Msk
     
    #define CAN_FFA1R_FFA5_Pos   (5U)
     
    #define CAN_FFA1R_FFA5_Msk   (0x1UL << CAN_FFA1R_FFA5_Pos)
     
    #define CAN_FFA1R_FFA5   CAN_FFA1R_FFA5_Msk
     
    #define CAN_FFA1R_FFA6_Pos   (6U)
     
    #define CAN_FFA1R_FFA6_Msk   (0x1UL << CAN_FFA1R_FFA6_Pos)
     
    #define CAN_FFA1R_FFA6   CAN_FFA1R_FFA6_Msk
     
    #define CAN_FFA1R_FFA7_Pos   (7U)
     
    #define CAN_FFA1R_FFA7_Msk   (0x1UL << CAN_FFA1R_FFA7_Pos)
     
    #define CAN_FFA1R_FFA7   CAN_FFA1R_FFA7_Msk
     
    #define CAN_FFA1R_FFA8_Pos   (8U)
     
    #define CAN_FFA1R_FFA8_Msk   (0x1UL << CAN_FFA1R_FFA8_Pos)
     
    #define CAN_FFA1R_FFA8   CAN_FFA1R_FFA8_Msk
     
    #define CAN_FFA1R_FFA9_Pos   (9U)
     
    #define CAN_FFA1R_FFA9_Msk   (0x1UL << CAN_FFA1R_FFA9_Pos)
     
    #define CAN_FFA1R_FFA9   CAN_FFA1R_FFA9_Msk
     
    #define CAN_FFA1R_FFA10_Pos   (10U)
     
    #define CAN_FFA1R_FFA10_Msk   (0x1UL << CAN_FFA1R_FFA10_Pos)
     
    #define CAN_FFA1R_FFA10   CAN_FFA1R_FFA10_Msk
     
    #define CAN_FFA1R_FFA11_Pos   (11U)
     
    #define CAN_FFA1R_FFA11_Msk   (0x1UL << CAN_FFA1R_FFA11_Pos)
     
    #define CAN_FFA1R_FFA11   CAN_FFA1R_FFA11_Msk
     
    #define CAN_FFA1R_FFA12_Pos   (12U)
     
    #define CAN_FFA1R_FFA12_Msk   (0x1UL << CAN_FFA1R_FFA12_Pos)
     
    #define CAN_FFA1R_FFA12   CAN_FFA1R_FFA12_Msk
     
    #define CAN_FFA1R_FFA13_Pos   (13U)
     
    #define CAN_FFA1R_FFA13_Msk   (0x1UL << CAN_FFA1R_FFA13_Pos)
     
    #define CAN_FFA1R_FFA13   CAN_FFA1R_FFA13_Msk
     
    #define CAN_FFA1R_FFA14_Pos   (14U)
     
    #define CAN_FFA1R_FFA14_Msk   (0x1UL << CAN_FFA1R_FFA14_Pos)
     
    #define CAN_FFA1R_FFA14   CAN_FFA1R_FFA14_Msk
     
    #define CAN_FFA1R_FFA15_Pos   (15U)
     
    #define CAN_FFA1R_FFA15_Msk   (0x1UL << CAN_FFA1R_FFA15_Pos)
     
    #define CAN_FFA1R_FFA15   CAN_FFA1R_FFA15_Msk
     
    #define CAN_FFA1R_FFA16_Pos   (16U)
     
    #define CAN_FFA1R_FFA16_Msk   (0x1UL << CAN_FFA1R_FFA16_Pos)
     
    #define CAN_FFA1R_FFA16   CAN_FFA1R_FFA16_Msk
     
    #define CAN_FFA1R_FFA17_Pos   (17U)
     
    #define CAN_FFA1R_FFA17_Msk   (0x1UL << CAN_FFA1R_FFA17_Pos)
     
    #define CAN_FFA1R_FFA17   CAN_FFA1R_FFA17_Msk
     
    #define CAN_FFA1R_FFA18_Pos   (18U)
     
    #define CAN_FFA1R_FFA18_Msk   (0x1UL << CAN_FFA1R_FFA18_Pos)
     
    #define CAN_FFA1R_FFA18   CAN_FFA1R_FFA18_Msk
     
    #define CAN_FFA1R_FFA19_Pos   (19U)
     
    #define CAN_FFA1R_FFA19_Msk   (0x1UL << CAN_FFA1R_FFA19_Pos)
     
    #define CAN_FFA1R_FFA19   CAN_FFA1R_FFA19_Msk
     
    #define CAN_FFA1R_FFA20_Pos   (20U)
     
    #define CAN_FFA1R_FFA20_Msk   (0x1UL << CAN_FFA1R_FFA20_Pos)
     
    #define CAN_FFA1R_FFA20   CAN_FFA1R_FFA20_Msk
     
    #define CAN_FFA1R_FFA21_Pos   (21U)
     
    #define CAN_FFA1R_FFA21_Msk   (0x1UL << CAN_FFA1R_FFA21_Pos)
     
    #define CAN_FFA1R_FFA21   CAN_FFA1R_FFA21_Msk
     
    #define CAN_FFA1R_FFA22_Pos   (22U)
     
    #define CAN_FFA1R_FFA22_Msk   (0x1UL << CAN_FFA1R_FFA22_Pos)
     
    #define CAN_FFA1R_FFA22   CAN_FFA1R_FFA22_Msk
     
    #define CAN_FFA1R_FFA23_Pos   (23U)
     
    #define CAN_FFA1R_FFA23_Msk   (0x1UL << CAN_FFA1R_FFA23_Pos)
     
    #define CAN_FFA1R_FFA23   CAN_FFA1R_FFA23_Msk
     
    #define CAN_FFA1R_FFA24_Pos   (24U)
     
    #define CAN_FFA1R_FFA24_Msk   (0x1UL << CAN_FFA1R_FFA24_Pos)
     
    #define CAN_FFA1R_FFA24   CAN_FFA1R_FFA24_Msk
     
    #define CAN_FFA1R_FFA25_Pos   (25U)
     
    #define CAN_FFA1R_FFA25_Msk   (0x1UL << CAN_FFA1R_FFA25_Pos)
     
    #define CAN_FFA1R_FFA25   CAN_FFA1R_FFA25_Msk
     
    #define CAN_FFA1R_FFA26_Pos   (26U)
     
    #define CAN_FFA1R_FFA26_Msk   (0x1UL << CAN_FFA1R_FFA26_Pos)
     
    #define CAN_FFA1R_FFA26   CAN_FFA1R_FFA26_Msk
     
    #define CAN_FFA1R_FFA27_Pos   (27U)
     
    #define CAN_FFA1R_FFA27_Msk   (0x1UL << CAN_FFA1R_FFA27_Pos)
     
    #define CAN_FFA1R_FFA27   CAN_FFA1R_FFA27_Msk
     
    #define CAN_FA1R_FACT_Pos   (0U)
     
    #define CAN_FA1R_FACT_Msk   (0xFFFFFFFUL << CAN_FA1R_FACT_Pos)
     
    #define CAN_FA1R_FACT   CAN_FA1R_FACT_Msk
     
    #define CAN_FA1R_FACT0_Pos   (0U)
     
    #define CAN_FA1R_FACT0_Msk   (0x1UL << CAN_FA1R_FACT0_Pos)
     
    #define CAN_FA1R_FACT0   CAN_FA1R_FACT0_Msk
     
    #define CAN_FA1R_FACT1_Pos   (1U)
     
    #define CAN_FA1R_FACT1_Msk   (0x1UL << CAN_FA1R_FACT1_Pos)
     
    #define CAN_FA1R_FACT1   CAN_FA1R_FACT1_Msk
     
    #define CAN_FA1R_FACT2_Pos   (2U)
     
    #define CAN_FA1R_FACT2_Msk   (0x1UL << CAN_FA1R_FACT2_Pos)
     
    #define CAN_FA1R_FACT2   CAN_FA1R_FACT2_Msk
     
    #define CAN_FA1R_FACT3_Pos   (3U)
     
    #define CAN_FA1R_FACT3_Msk   (0x1UL << CAN_FA1R_FACT3_Pos)
     
    #define CAN_FA1R_FACT3   CAN_FA1R_FACT3_Msk
     
    #define CAN_FA1R_FACT4_Pos   (4U)
     
    #define CAN_FA1R_FACT4_Msk   (0x1UL << CAN_FA1R_FACT4_Pos)
     
    #define CAN_FA1R_FACT4   CAN_FA1R_FACT4_Msk
     
    #define CAN_FA1R_FACT5_Pos   (5U)
     
    #define CAN_FA1R_FACT5_Msk   (0x1UL << CAN_FA1R_FACT5_Pos)
     
    #define CAN_FA1R_FACT5   CAN_FA1R_FACT5_Msk
     
    #define CAN_FA1R_FACT6_Pos   (6U)
     
    #define CAN_FA1R_FACT6_Msk   (0x1UL << CAN_FA1R_FACT6_Pos)
     
    #define CAN_FA1R_FACT6   CAN_FA1R_FACT6_Msk
     
    #define CAN_FA1R_FACT7_Pos   (7U)
     
    #define CAN_FA1R_FACT7_Msk   (0x1UL << CAN_FA1R_FACT7_Pos)
     
    #define CAN_FA1R_FACT7   CAN_FA1R_FACT7_Msk
     
    #define CAN_FA1R_FACT8_Pos   (8U)
     
    #define CAN_FA1R_FACT8_Msk   (0x1UL << CAN_FA1R_FACT8_Pos)
     
    #define CAN_FA1R_FACT8   CAN_FA1R_FACT8_Msk
     
    #define CAN_FA1R_FACT9_Pos   (9U)
     
    #define CAN_FA1R_FACT9_Msk   (0x1UL << CAN_FA1R_FACT9_Pos)
     
    #define CAN_FA1R_FACT9   CAN_FA1R_FACT9_Msk
     
    #define CAN_FA1R_FACT10_Pos   (10U)
     
    #define CAN_FA1R_FACT10_Msk   (0x1UL << CAN_FA1R_FACT10_Pos)
     
    #define CAN_FA1R_FACT10   CAN_FA1R_FACT10_Msk
     
    #define CAN_FA1R_FACT11_Pos   (11U)
     
    #define CAN_FA1R_FACT11_Msk   (0x1UL << CAN_FA1R_FACT11_Pos)
     
    #define CAN_FA1R_FACT11   CAN_FA1R_FACT11_Msk
     
    #define CAN_FA1R_FACT12_Pos   (12U)
     
    #define CAN_FA1R_FACT12_Msk   (0x1UL << CAN_FA1R_FACT12_Pos)
     
    #define CAN_FA1R_FACT12   CAN_FA1R_FACT12_Msk
     
    #define CAN_FA1R_FACT13_Pos   (13U)
     
    #define CAN_FA1R_FACT13_Msk   (0x1UL << CAN_FA1R_FACT13_Pos)
     
    #define CAN_FA1R_FACT13   CAN_FA1R_FACT13_Msk
     
    #define CAN_FA1R_FACT14_Pos   (14U)
     
    #define CAN_FA1R_FACT14_Msk   (0x1UL << CAN_FA1R_FACT14_Pos)
     
    #define CAN_FA1R_FACT14   CAN_FA1R_FACT14_Msk
     
    #define CAN_FA1R_FACT15_Pos   (15U)
     
    #define CAN_FA1R_FACT15_Msk   (0x1UL << CAN_FA1R_FACT15_Pos)
     
    #define CAN_FA1R_FACT15   CAN_FA1R_FACT15_Msk
     
    #define CAN_FA1R_FACT16_Pos   (16U)
     
    #define CAN_FA1R_FACT16_Msk   (0x1UL << CAN_FA1R_FACT16_Pos)
     
    #define CAN_FA1R_FACT16   CAN_FA1R_FACT16_Msk
     
    #define CAN_FA1R_FACT17_Pos   (17U)
     
    #define CAN_FA1R_FACT17_Msk   (0x1UL << CAN_FA1R_FACT17_Pos)
     
    #define CAN_FA1R_FACT17   CAN_FA1R_FACT17_Msk
     
    #define CAN_FA1R_FACT18_Pos   (18U)
     
    #define CAN_FA1R_FACT18_Msk   (0x1UL << CAN_FA1R_FACT18_Pos)
     
    #define CAN_FA1R_FACT18   CAN_FA1R_FACT18_Msk
     
    #define CAN_FA1R_FACT19_Pos   (19U)
     
    #define CAN_FA1R_FACT19_Msk   (0x1UL << CAN_FA1R_FACT19_Pos)
     
    #define CAN_FA1R_FACT19   CAN_FA1R_FACT19_Msk
     
    #define CAN_FA1R_FACT20_Pos   (20U)
     
    #define CAN_FA1R_FACT20_Msk   (0x1UL << CAN_FA1R_FACT20_Pos)
     
    #define CAN_FA1R_FACT20   CAN_FA1R_FACT20_Msk
     
    #define CAN_FA1R_FACT21_Pos   (21U)
     
    #define CAN_FA1R_FACT21_Msk   (0x1UL << CAN_FA1R_FACT21_Pos)
     
    #define CAN_FA1R_FACT21   CAN_FA1R_FACT21_Msk
     
    #define CAN_FA1R_FACT22_Pos   (22U)
     
    #define CAN_FA1R_FACT22_Msk   (0x1UL << CAN_FA1R_FACT22_Pos)
     
    #define CAN_FA1R_FACT22   CAN_FA1R_FACT22_Msk
     
    #define CAN_FA1R_FACT23_Pos   (23U)
     
    #define CAN_FA1R_FACT23_Msk   (0x1UL << CAN_FA1R_FACT23_Pos)
     
    #define CAN_FA1R_FACT23   CAN_FA1R_FACT23_Msk
     
    #define CAN_FA1R_FACT24_Pos   (24U)
     
    #define CAN_FA1R_FACT24_Msk   (0x1UL << CAN_FA1R_FACT24_Pos)
     
    #define CAN_FA1R_FACT24   CAN_FA1R_FACT24_Msk
     
    #define CAN_FA1R_FACT25_Pos   (25U)
     
    #define CAN_FA1R_FACT25_Msk   (0x1UL << CAN_FA1R_FACT25_Pos)
     
    #define CAN_FA1R_FACT25   CAN_FA1R_FACT25_Msk
     
    #define CAN_FA1R_FACT26_Pos   (26U)
     
    #define CAN_FA1R_FACT26_Msk   (0x1UL << CAN_FA1R_FACT26_Pos)
     
    #define CAN_FA1R_FACT26   CAN_FA1R_FACT26_Msk
     
    #define CAN_FA1R_FACT27_Pos   (27U)
     
    #define CAN_FA1R_FACT27_Msk   (0x1UL << CAN_FA1R_FACT27_Pos)
     
    #define CAN_FA1R_FACT27   CAN_FA1R_FACT27_Msk
     
    #define CAN_F0R1_FB0_Pos   (0U)
     
    #define CAN_F0R1_FB0_Msk   (0x1UL << CAN_F0R1_FB0_Pos)
     
    #define CAN_F0R1_FB0   CAN_F0R1_FB0_Msk
     
    #define CAN_F0R1_FB1_Pos   (1U)
     
    #define CAN_F0R1_FB1_Msk   (0x1UL << CAN_F0R1_FB1_Pos)
     
    #define CAN_F0R1_FB1   CAN_F0R1_FB1_Msk
     
    #define CAN_F0R1_FB2_Pos   (2U)
     
    #define CAN_F0R1_FB2_Msk   (0x1UL << CAN_F0R1_FB2_Pos)
     
    #define CAN_F0R1_FB2   CAN_F0R1_FB2_Msk
     
    #define CAN_F0R1_FB3_Pos   (3U)
     
    #define CAN_F0R1_FB3_Msk   (0x1UL << CAN_F0R1_FB3_Pos)
     
    #define CAN_F0R1_FB3   CAN_F0R1_FB3_Msk
     
    #define CAN_F0R1_FB4_Pos   (4U)
     
    #define CAN_F0R1_FB4_Msk   (0x1UL << CAN_F0R1_FB4_Pos)
     
    #define CAN_F0R1_FB4   CAN_F0R1_FB4_Msk
     
    #define CAN_F0R1_FB5_Pos   (5U)
     
    #define CAN_F0R1_FB5_Msk   (0x1UL << CAN_F0R1_FB5_Pos)
     
    #define CAN_F0R1_FB5   CAN_F0R1_FB5_Msk
     
    #define CAN_F0R1_FB6_Pos   (6U)
     
    #define CAN_F0R1_FB6_Msk   (0x1UL << CAN_F0R1_FB6_Pos)
     
    #define CAN_F0R1_FB6   CAN_F0R1_FB6_Msk
     
    #define CAN_F0R1_FB7_Pos   (7U)
     
    #define CAN_F0R1_FB7_Msk   (0x1UL << CAN_F0R1_FB7_Pos)
     
    #define CAN_F0R1_FB7   CAN_F0R1_FB7_Msk
     
    #define CAN_F0R1_FB8_Pos   (8U)
     
    #define CAN_F0R1_FB8_Msk   (0x1UL << CAN_F0R1_FB8_Pos)
     
    #define CAN_F0R1_FB8   CAN_F0R1_FB8_Msk
     
    #define CAN_F0R1_FB9_Pos   (9U)
     
    #define CAN_F0R1_FB9_Msk   (0x1UL << CAN_F0R1_FB9_Pos)
     
    #define CAN_F0R1_FB9   CAN_F0R1_FB9_Msk
     
    #define CAN_F0R1_FB10_Pos   (10U)
     
    #define CAN_F0R1_FB10_Msk   (0x1UL << CAN_F0R1_FB10_Pos)
     
    #define CAN_F0R1_FB10   CAN_F0R1_FB10_Msk
     
    #define CAN_F0R1_FB11_Pos   (11U)
     
    #define CAN_F0R1_FB11_Msk   (0x1UL << CAN_F0R1_FB11_Pos)
     
    #define CAN_F0R1_FB11   CAN_F0R1_FB11_Msk
     
    #define CAN_F0R1_FB12_Pos   (12U)
     
    #define CAN_F0R1_FB12_Msk   (0x1UL << CAN_F0R1_FB12_Pos)
     
    #define CAN_F0R1_FB12   CAN_F0R1_FB12_Msk
     
    #define CAN_F0R1_FB13_Pos   (13U)
     
    #define CAN_F0R1_FB13_Msk   (0x1UL << CAN_F0R1_FB13_Pos)
     
    #define CAN_F0R1_FB13   CAN_F0R1_FB13_Msk
     
    #define CAN_F0R1_FB14_Pos   (14U)
     
    #define CAN_F0R1_FB14_Msk   (0x1UL << CAN_F0R1_FB14_Pos)
     
    #define CAN_F0R1_FB14   CAN_F0R1_FB14_Msk
     
    #define CAN_F0R1_FB15_Pos   (15U)
     
    #define CAN_F0R1_FB15_Msk   (0x1UL << CAN_F0R1_FB15_Pos)
     
    #define CAN_F0R1_FB15   CAN_F0R1_FB15_Msk
     
    #define CAN_F0R1_FB16_Pos   (16U)
     
    #define CAN_F0R1_FB16_Msk   (0x1UL << CAN_F0R1_FB16_Pos)
     
    #define CAN_F0R1_FB16   CAN_F0R1_FB16_Msk
     
    #define CAN_F0R1_FB17_Pos   (17U)
     
    #define CAN_F0R1_FB17_Msk   (0x1UL << CAN_F0R1_FB17_Pos)
     
    #define CAN_F0R1_FB17   CAN_F0R1_FB17_Msk
     
    #define CAN_F0R1_FB18_Pos   (18U)
     
    #define CAN_F0R1_FB18_Msk   (0x1UL << CAN_F0R1_FB18_Pos)
     
    #define CAN_F0R1_FB18   CAN_F0R1_FB18_Msk
     
    #define CAN_F0R1_FB19_Pos   (19U)
     
    #define CAN_F0R1_FB19_Msk   (0x1UL << CAN_F0R1_FB19_Pos)
     
    #define CAN_F0R1_FB19   CAN_F0R1_FB19_Msk
     
    #define CAN_F0R1_FB20_Pos   (20U)
     
    #define CAN_F0R1_FB20_Msk   (0x1UL << CAN_F0R1_FB20_Pos)
     
    #define CAN_F0R1_FB20   CAN_F0R1_FB20_Msk
     
    #define CAN_F0R1_FB21_Pos   (21U)
     
    #define CAN_F0R1_FB21_Msk   (0x1UL << CAN_F0R1_FB21_Pos)
     
    #define CAN_F0R1_FB21   CAN_F0R1_FB21_Msk
     
    #define CAN_F0R1_FB22_Pos   (22U)
     
    #define CAN_F0R1_FB22_Msk   (0x1UL << CAN_F0R1_FB22_Pos)
     
    #define CAN_F0R1_FB22   CAN_F0R1_FB22_Msk
     
    #define CAN_F0R1_FB23_Pos   (23U)
     
    #define CAN_F0R1_FB23_Msk   (0x1UL << CAN_F0R1_FB23_Pos)
     
    #define CAN_F0R1_FB23   CAN_F0R1_FB23_Msk
     
    #define CAN_F0R1_FB24_Pos   (24U)
     
    #define CAN_F0R1_FB24_Msk   (0x1UL << CAN_F0R1_FB24_Pos)
     
    #define CAN_F0R1_FB24   CAN_F0R1_FB24_Msk
     
    #define CAN_F0R1_FB25_Pos   (25U)
     
    #define CAN_F0R1_FB25_Msk   (0x1UL << CAN_F0R1_FB25_Pos)
     
    #define CAN_F0R1_FB25   CAN_F0R1_FB25_Msk
     
    #define CAN_F0R1_FB26_Pos   (26U)
     
    #define CAN_F0R1_FB26_Msk   (0x1UL << CAN_F0R1_FB26_Pos)
     
    #define CAN_F0R1_FB26   CAN_F0R1_FB26_Msk
     
    #define CAN_F0R1_FB27_Pos   (27U)
     
    #define CAN_F0R1_FB27_Msk   (0x1UL << CAN_F0R1_FB27_Pos)
     
    #define CAN_F0R1_FB27   CAN_F0R1_FB27_Msk
     
    #define CAN_F0R1_FB28_Pos   (28U)
     
    #define CAN_F0R1_FB28_Msk   (0x1UL << CAN_F0R1_FB28_Pos)
     
    #define CAN_F0R1_FB28   CAN_F0R1_FB28_Msk
     
    #define CAN_F0R1_FB29_Pos   (29U)
     
    #define CAN_F0R1_FB29_Msk   (0x1UL << CAN_F0R1_FB29_Pos)
     
    #define CAN_F0R1_FB29   CAN_F0R1_FB29_Msk
     
    #define CAN_F0R1_FB30_Pos   (30U)
     
    #define CAN_F0R1_FB30_Msk   (0x1UL << CAN_F0R1_FB30_Pos)
     
    #define CAN_F0R1_FB30   CAN_F0R1_FB30_Msk
     
    #define CAN_F0R1_FB31_Pos   (31U)
     
    #define CAN_F0R1_FB31_Msk   (0x1UL << CAN_F0R1_FB31_Pos)
     
    #define CAN_F0R1_FB31   CAN_F0R1_FB31_Msk
     
    #define CAN_F1R1_FB0_Pos   (0U)
     
    #define CAN_F1R1_FB0_Msk   (0x1UL << CAN_F1R1_FB0_Pos)
     
    #define CAN_F1R1_FB0   CAN_F1R1_FB0_Msk
     
    #define CAN_F1R1_FB1_Pos   (1U)
     
    #define CAN_F1R1_FB1_Msk   (0x1UL << CAN_F1R1_FB1_Pos)
     
    #define CAN_F1R1_FB1   CAN_F1R1_FB1_Msk
     
    #define CAN_F1R1_FB2_Pos   (2U)
     
    #define CAN_F1R1_FB2_Msk   (0x1UL << CAN_F1R1_FB2_Pos)
     
    #define CAN_F1R1_FB2   CAN_F1R1_FB2_Msk
     
    #define CAN_F1R1_FB3_Pos   (3U)
     
    #define CAN_F1R1_FB3_Msk   (0x1UL << CAN_F1R1_FB3_Pos)
     
    #define CAN_F1R1_FB3   CAN_F1R1_FB3_Msk
     
    #define CAN_F1R1_FB4_Pos   (4U)
     
    #define CAN_F1R1_FB4_Msk   (0x1UL << CAN_F1R1_FB4_Pos)
     
    #define CAN_F1R1_FB4   CAN_F1R1_FB4_Msk
     
    #define CAN_F1R1_FB5_Pos   (5U)
     
    #define CAN_F1R1_FB5_Msk   (0x1UL << CAN_F1R1_FB5_Pos)
     
    #define CAN_F1R1_FB5   CAN_F1R1_FB5_Msk
     
    #define CAN_F1R1_FB6_Pos   (6U)
     
    #define CAN_F1R1_FB6_Msk   (0x1UL << CAN_F1R1_FB6_Pos)
     
    #define CAN_F1R1_FB6   CAN_F1R1_FB6_Msk
     
    #define CAN_F1R1_FB7_Pos   (7U)
     
    #define CAN_F1R1_FB7_Msk   (0x1UL << CAN_F1R1_FB7_Pos)
     
    #define CAN_F1R1_FB7   CAN_F1R1_FB7_Msk
     
    #define CAN_F1R1_FB8_Pos   (8U)
     
    #define CAN_F1R1_FB8_Msk   (0x1UL << CAN_F1R1_FB8_Pos)
     
    #define CAN_F1R1_FB8   CAN_F1R1_FB8_Msk
     
    #define CAN_F1R1_FB9_Pos   (9U)
     
    #define CAN_F1R1_FB9_Msk   (0x1UL << CAN_F1R1_FB9_Pos)
     
    #define CAN_F1R1_FB9   CAN_F1R1_FB9_Msk
     
    #define CAN_F1R1_FB10_Pos   (10U)
     
    #define CAN_F1R1_FB10_Msk   (0x1UL << CAN_F1R1_FB10_Pos)
     
    #define CAN_F1R1_FB10   CAN_F1R1_FB10_Msk
     
    #define CAN_F1R1_FB11_Pos   (11U)
     
    #define CAN_F1R1_FB11_Msk   (0x1UL << CAN_F1R1_FB11_Pos)
     
    #define CAN_F1R1_FB11   CAN_F1R1_FB11_Msk
     
    #define CAN_F1R1_FB12_Pos   (12U)
     
    #define CAN_F1R1_FB12_Msk   (0x1UL << CAN_F1R1_FB12_Pos)
     
    #define CAN_F1R1_FB12   CAN_F1R1_FB12_Msk
     
    #define CAN_F1R1_FB13_Pos   (13U)
     
    #define CAN_F1R1_FB13_Msk   (0x1UL << CAN_F1R1_FB13_Pos)
     
    #define CAN_F1R1_FB13   CAN_F1R1_FB13_Msk
     
    #define CAN_F1R1_FB14_Pos   (14U)
     
    #define CAN_F1R1_FB14_Msk   (0x1UL << CAN_F1R1_FB14_Pos)
     
    #define CAN_F1R1_FB14   CAN_F1R1_FB14_Msk
     
    #define CAN_F1R1_FB15_Pos   (15U)
     
    #define CAN_F1R1_FB15_Msk   (0x1UL << CAN_F1R1_FB15_Pos)
     
    #define CAN_F1R1_FB15   CAN_F1R1_FB15_Msk
     
    #define CAN_F1R1_FB16_Pos   (16U)
     
    #define CAN_F1R1_FB16_Msk   (0x1UL << CAN_F1R1_FB16_Pos)
     
    #define CAN_F1R1_FB16   CAN_F1R1_FB16_Msk
     
    #define CAN_F1R1_FB17_Pos   (17U)
     
    #define CAN_F1R1_FB17_Msk   (0x1UL << CAN_F1R1_FB17_Pos)
     
    #define CAN_F1R1_FB17   CAN_F1R1_FB17_Msk
     
    #define CAN_F1R1_FB18_Pos   (18U)
     
    #define CAN_F1R1_FB18_Msk   (0x1UL << CAN_F1R1_FB18_Pos)
     
    #define CAN_F1R1_FB18   CAN_F1R1_FB18_Msk
     
    #define CAN_F1R1_FB19_Pos   (19U)
     
    #define CAN_F1R1_FB19_Msk   (0x1UL << CAN_F1R1_FB19_Pos)
     
    #define CAN_F1R1_FB19   CAN_F1R1_FB19_Msk
     
    #define CAN_F1R1_FB20_Pos   (20U)
     
    #define CAN_F1R1_FB20_Msk   (0x1UL << CAN_F1R1_FB20_Pos)
     
    #define CAN_F1R1_FB20   CAN_F1R1_FB20_Msk
     
    #define CAN_F1R1_FB21_Pos   (21U)
     
    #define CAN_F1R1_FB21_Msk   (0x1UL << CAN_F1R1_FB21_Pos)
     
    #define CAN_F1R1_FB21   CAN_F1R1_FB21_Msk
     
    #define CAN_F1R1_FB22_Pos   (22U)
     
    #define CAN_F1R1_FB22_Msk   (0x1UL << CAN_F1R1_FB22_Pos)
     
    #define CAN_F1R1_FB22   CAN_F1R1_FB22_Msk
     
    #define CAN_F1R1_FB23_Pos   (23U)
     
    #define CAN_F1R1_FB23_Msk   (0x1UL << CAN_F1R1_FB23_Pos)
     
    #define CAN_F1R1_FB23   CAN_F1R1_FB23_Msk
     
    #define CAN_F1R1_FB24_Pos   (24U)
     
    #define CAN_F1R1_FB24_Msk   (0x1UL << CAN_F1R1_FB24_Pos)
     
    #define CAN_F1R1_FB24   CAN_F1R1_FB24_Msk
     
    #define CAN_F1R1_FB25_Pos   (25U)
     
    #define CAN_F1R1_FB25_Msk   (0x1UL << CAN_F1R1_FB25_Pos)
     
    #define CAN_F1R1_FB25   CAN_F1R1_FB25_Msk
     
    #define CAN_F1R1_FB26_Pos   (26U)
     
    #define CAN_F1R1_FB26_Msk   (0x1UL << CAN_F1R1_FB26_Pos)
     
    #define CAN_F1R1_FB26   CAN_F1R1_FB26_Msk
     
    #define CAN_F1R1_FB27_Pos   (27U)
     
    #define CAN_F1R1_FB27_Msk   (0x1UL << CAN_F1R1_FB27_Pos)
     
    #define CAN_F1R1_FB27   CAN_F1R1_FB27_Msk
     
    #define CAN_F1R1_FB28_Pos   (28U)
     
    #define CAN_F1R1_FB28_Msk   (0x1UL << CAN_F1R1_FB28_Pos)
     
    #define CAN_F1R1_FB28   CAN_F1R1_FB28_Msk
     
    #define CAN_F1R1_FB29_Pos   (29U)
     
    #define CAN_F1R1_FB29_Msk   (0x1UL << CAN_F1R1_FB29_Pos)
     
    #define CAN_F1R1_FB29   CAN_F1R1_FB29_Msk
     
    #define CAN_F1R1_FB30_Pos   (30U)
     
    #define CAN_F1R1_FB30_Msk   (0x1UL << CAN_F1R1_FB30_Pos)
     
    #define CAN_F1R1_FB30   CAN_F1R1_FB30_Msk
     
    #define CAN_F1R1_FB31_Pos   (31U)
     
    #define CAN_F1R1_FB31_Msk   (0x1UL << CAN_F1R1_FB31_Pos)
     
    #define CAN_F1R1_FB31   CAN_F1R1_FB31_Msk
     
    #define CAN_F2R1_FB0_Pos   (0U)
     
    #define CAN_F2R1_FB0_Msk   (0x1UL << CAN_F2R1_FB0_Pos)
     
    #define CAN_F2R1_FB0   CAN_F2R1_FB0_Msk
     
    #define CAN_F2R1_FB1_Pos   (1U)
     
    #define CAN_F2R1_FB1_Msk   (0x1UL << CAN_F2R1_FB1_Pos)
     
    #define CAN_F2R1_FB1   CAN_F2R1_FB1_Msk
     
    #define CAN_F2R1_FB2_Pos   (2U)
     
    #define CAN_F2R1_FB2_Msk   (0x1UL << CAN_F2R1_FB2_Pos)
     
    #define CAN_F2R1_FB2   CAN_F2R1_FB2_Msk
     
    #define CAN_F2R1_FB3_Pos   (3U)
     
    #define CAN_F2R1_FB3_Msk   (0x1UL << CAN_F2R1_FB3_Pos)
     
    #define CAN_F2R1_FB3   CAN_F2R1_FB3_Msk
     
    #define CAN_F2R1_FB4_Pos   (4U)
     
    #define CAN_F2R1_FB4_Msk   (0x1UL << CAN_F2R1_FB4_Pos)
     
    #define CAN_F2R1_FB4   CAN_F2R1_FB4_Msk
     
    #define CAN_F2R1_FB5_Pos   (5U)
     
    #define CAN_F2R1_FB5_Msk   (0x1UL << CAN_F2R1_FB5_Pos)
     
    #define CAN_F2R1_FB5   CAN_F2R1_FB5_Msk
     
    #define CAN_F2R1_FB6_Pos   (6U)
     
    #define CAN_F2R1_FB6_Msk   (0x1UL << CAN_F2R1_FB6_Pos)
     
    #define CAN_F2R1_FB6   CAN_F2R1_FB6_Msk
     
    #define CAN_F2R1_FB7_Pos   (7U)
     
    #define CAN_F2R1_FB7_Msk   (0x1UL << CAN_F2R1_FB7_Pos)
     
    #define CAN_F2R1_FB7   CAN_F2R1_FB7_Msk
     
    #define CAN_F2R1_FB8_Pos   (8U)
     
    #define CAN_F2R1_FB8_Msk   (0x1UL << CAN_F2R1_FB8_Pos)
     
    #define CAN_F2R1_FB8   CAN_F2R1_FB8_Msk
     
    #define CAN_F2R1_FB9_Pos   (9U)
     
    #define CAN_F2R1_FB9_Msk   (0x1UL << CAN_F2R1_FB9_Pos)
     
    #define CAN_F2R1_FB9   CAN_F2R1_FB9_Msk
     
    #define CAN_F2R1_FB10_Pos   (10U)
     
    #define CAN_F2R1_FB10_Msk   (0x1UL << CAN_F2R1_FB10_Pos)
     
    #define CAN_F2R1_FB10   CAN_F2R1_FB10_Msk
     
    #define CAN_F2R1_FB11_Pos   (11U)
     
    #define CAN_F2R1_FB11_Msk   (0x1UL << CAN_F2R1_FB11_Pos)
     
    #define CAN_F2R1_FB11   CAN_F2R1_FB11_Msk
     
    #define CAN_F2R1_FB12_Pos   (12U)
     
    #define CAN_F2R1_FB12_Msk   (0x1UL << CAN_F2R1_FB12_Pos)
     
    #define CAN_F2R1_FB12   CAN_F2R1_FB12_Msk
     
    #define CAN_F2R1_FB13_Pos   (13U)
     
    #define CAN_F2R1_FB13_Msk   (0x1UL << CAN_F2R1_FB13_Pos)
     
    #define CAN_F2R1_FB13   CAN_F2R1_FB13_Msk
     
    #define CAN_F2R1_FB14_Pos   (14U)
     
    #define CAN_F2R1_FB14_Msk   (0x1UL << CAN_F2R1_FB14_Pos)
     
    #define CAN_F2R1_FB14   CAN_F2R1_FB14_Msk
     
    #define CAN_F2R1_FB15_Pos   (15U)
     
    #define CAN_F2R1_FB15_Msk   (0x1UL << CAN_F2R1_FB15_Pos)
     
    #define CAN_F2R1_FB15   CAN_F2R1_FB15_Msk
     
    #define CAN_F2R1_FB16_Pos   (16U)
     
    #define CAN_F2R1_FB16_Msk   (0x1UL << CAN_F2R1_FB16_Pos)
     
    #define CAN_F2R1_FB16   CAN_F2R1_FB16_Msk
     
    #define CAN_F2R1_FB17_Pos   (17U)
     
    #define CAN_F2R1_FB17_Msk   (0x1UL << CAN_F2R1_FB17_Pos)
     
    #define CAN_F2R1_FB17   CAN_F2R1_FB17_Msk
     
    #define CAN_F2R1_FB18_Pos   (18U)
     
    #define CAN_F2R1_FB18_Msk   (0x1UL << CAN_F2R1_FB18_Pos)
     
    #define CAN_F2R1_FB18   CAN_F2R1_FB18_Msk
     
    #define CAN_F2R1_FB19_Pos   (19U)
     
    #define CAN_F2R1_FB19_Msk   (0x1UL << CAN_F2R1_FB19_Pos)
     
    #define CAN_F2R1_FB19   CAN_F2R1_FB19_Msk
     
    #define CAN_F2R1_FB20_Pos   (20U)
     
    #define CAN_F2R1_FB20_Msk   (0x1UL << CAN_F2R1_FB20_Pos)
     
    #define CAN_F2R1_FB20   CAN_F2R1_FB20_Msk
     
    #define CAN_F2R1_FB21_Pos   (21U)
     
    #define CAN_F2R1_FB21_Msk   (0x1UL << CAN_F2R1_FB21_Pos)
     
    #define CAN_F2R1_FB21   CAN_F2R1_FB21_Msk
     
    #define CAN_F2R1_FB22_Pos   (22U)
     
    #define CAN_F2R1_FB22_Msk   (0x1UL << CAN_F2R1_FB22_Pos)
     
    #define CAN_F2R1_FB22   CAN_F2R1_FB22_Msk
     
    #define CAN_F2R1_FB23_Pos   (23U)
     
    #define CAN_F2R1_FB23_Msk   (0x1UL << CAN_F2R1_FB23_Pos)
     
    #define CAN_F2R1_FB23   CAN_F2R1_FB23_Msk
     
    #define CAN_F2R1_FB24_Pos   (24U)
     
    #define CAN_F2R1_FB24_Msk   (0x1UL << CAN_F2R1_FB24_Pos)
     
    #define CAN_F2R1_FB24   CAN_F2R1_FB24_Msk
     
    #define CAN_F2R1_FB25_Pos   (25U)
     
    #define CAN_F2R1_FB25_Msk   (0x1UL << CAN_F2R1_FB25_Pos)
     
    #define CAN_F2R1_FB25   CAN_F2R1_FB25_Msk
     
    #define CAN_F2R1_FB26_Pos   (26U)
     
    #define CAN_F2R1_FB26_Msk   (0x1UL << CAN_F2R1_FB26_Pos)
     
    #define CAN_F2R1_FB26   CAN_F2R1_FB26_Msk
     
    #define CAN_F2R1_FB27_Pos   (27U)
     
    #define CAN_F2R1_FB27_Msk   (0x1UL << CAN_F2R1_FB27_Pos)
     
    #define CAN_F2R1_FB27   CAN_F2R1_FB27_Msk
     
    #define CAN_F2R1_FB28_Pos   (28U)
     
    #define CAN_F2R1_FB28_Msk   (0x1UL << CAN_F2R1_FB28_Pos)
     
    #define CAN_F2R1_FB28   CAN_F2R1_FB28_Msk
     
    #define CAN_F2R1_FB29_Pos   (29U)
     
    #define CAN_F2R1_FB29_Msk   (0x1UL << CAN_F2R1_FB29_Pos)
     
    #define CAN_F2R1_FB29   CAN_F2R1_FB29_Msk
     
    #define CAN_F2R1_FB30_Pos   (30U)
     
    #define CAN_F2R1_FB30_Msk   (0x1UL << CAN_F2R1_FB30_Pos)
     
    #define CAN_F2R1_FB30   CAN_F2R1_FB30_Msk
     
    #define CAN_F2R1_FB31_Pos   (31U)
     
    #define CAN_F2R1_FB31_Msk   (0x1UL << CAN_F2R1_FB31_Pos)
     
    #define CAN_F2R1_FB31   CAN_F2R1_FB31_Msk
     
    #define CAN_F3R1_FB0_Pos   (0U)
     
    #define CAN_F3R1_FB0_Msk   (0x1UL << CAN_F3R1_FB0_Pos)
     
    #define CAN_F3R1_FB0   CAN_F3R1_FB0_Msk
     
    #define CAN_F3R1_FB1_Pos   (1U)
     
    #define CAN_F3R1_FB1_Msk   (0x1UL << CAN_F3R1_FB1_Pos)
     
    #define CAN_F3R1_FB1   CAN_F3R1_FB1_Msk
     
    #define CAN_F3R1_FB2_Pos   (2U)
     
    #define CAN_F3R1_FB2_Msk   (0x1UL << CAN_F3R1_FB2_Pos)
     
    #define CAN_F3R1_FB2   CAN_F3R1_FB2_Msk
     
    #define CAN_F3R1_FB3_Pos   (3U)
     
    #define CAN_F3R1_FB3_Msk   (0x1UL << CAN_F3R1_FB3_Pos)
     
    #define CAN_F3R1_FB3   CAN_F3R1_FB3_Msk
     
    #define CAN_F3R1_FB4_Pos   (4U)
     
    #define CAN_F3R1_FB4_Msk   (0x1UL << CAN_F3R1_FB4_Pos)
     
    #define CAN_F3R1_FB4   CAN_F3R1_FB4_Msk
     
    #define CAN_F3R1_FB5_Pos   (5U)
     
    #define CAN_F3R1_FB5_Msk   (0x1UL << CAN_F3R1_FB5_Pos)
     
    #define CAN_F3R1_FB5   CAN_F3R1_FB5_Msk
     
    #define CAN_F3R1_FB6_Pos   (6U)
     
    #define CAN_F3R1_FB6_Msk   (0x1UL << CAN_F3R1_FB6_Pos)
     
    #define CAN_F3R1_FB6   CAN_F3R1_FB6_Msk
     
    #define CAN_F3R1_FB7_Pos   (7U)
     
    #define CAN_F3R1_FB7_Msk   (0x1UL << CAN_F3R1_FB7_Pos)
     
    #define CAN_F3R1_FB7   CAN_F3R1_FB7_Msk
     
    #define CAN_F3R1_FB8_Pos   (8U)
     
    #define CAN_F3R1_FB8_Msk   (0x1UL << CAN_F3R1_FB8_Pos)
     
    #define CAN_F3R1_FB8   CAN_F3R1_FB8_Msk
     
    #define CAN_F3R1_FB9_Pos   (9U)
     
    #define CAN_F3R1_FB9_Msk   (0x1UL << CAN_F3R1_FB9_Pos)
     
    #define CAN_F3R1_FB9   CAN_F3R1_FB9_Msk
     
    #define CAN_F3R1_FB10_Pos   (10U)
     
    #define CAN_F3R1_FB10_Msk   (0x1UL << CAN_F3R1_FB10_Pos)
     
    #define CAN_F3R1_FB10   CAN_F3R1_FB10_Msk
     
    #define CAN_F3R1_FB11_Pos   (11U)
     
    #define CAN_F3R1_FB11_Msk   (0x1UL << CAN_F3R1_FB11_Pos)
     
    #define CAN_F3R1_FB11   CAN_F3R1_FB11_Msk
     
    #define CAN_F3R1_FB12_Pos   (12U)
     
    #define CAN_F3R1_FB12_Msk   (0x1UL << CAN_F3R1_FB12_Pos)
     
    #define CAN_F3R1_FB12   CAN_F3R1_FB12_Msk
     
    #define CAN_F3R1_FB13_Pos   (13U)
     
    #define CAN_F3R1_FB13_Msk   (0x1UL << CAN_F3R1_FB13_Pos)
     
    #define CAN_F3R1_FB13   CAN_F3R1_FB13_Msk
     
    #define CAN_F3R1_FB14_Pos   (14U)
     
    #define CAN_F3R1_FB14_Msk   (0x1UL << CAN_F3R1_FB14_Pos)
     
    #define CAN_F3R1_FB14   CAN_F3R1_FB14_Msk
     
    #define CAN_F3R1_FB15_Pos   (15U)
     
    #define CAN_F3R1_FB15_Msk   (0x1UL << CAN_F3R1_FB15_Pos)
     
    #define CAN_F3R1_FB15   CAN_F3R1_FB15_Msk
     
    #define CAN_F3R1_FB16_Pos   (16U)
     
    #define CAN_F3R1_FB16_Msk   (0x1UL << CAN_F3R1_FB16_Pos)
     
    #define CAN_F3R1_FB16   CAN_F3R1_FB16_Msk
     
    #define CAN_F3R1_FB17_Pos   (17U)
     
    #define CAN_F3R1_FB17_Msk   (0x1UL << CAN_F3R1_FB17_Pos)
     
    #define CAN_F3R1_FB17   CAN_F3R1_FB17_Msk
     
    #define CAN_F3R1_FB18_Pos   (18U)
     
    #define CAN_F3R1_FB18_Msk   (0x1UL << CAN_F3R1_FB18_Pos)
     
    #define CAN_F3R1_FB18   CAN_F3R1_FB18_Msk
     
    #define CAN_F3R1_FB19_Pos   (19U)
     
    #define CAN_F3R1_FB19_Msk   (0x1UL << CAN_F3R1_FB19_Pos)
     
    #define CAN_F3R1_FB19   CAN_F3R1_FB19_Msk
     
    #define CAN_F3R1_FB20_Pos   (20U)
     
    #define CAN_F3R1_FB20_Msk   (0x1UL << CAN_F3R1_FB20_Pos)
     
    #define CAN_F3R1_FB20   CAN_F3R1_FB20_Msk
     
    #define CAN_F3R1_FB21_Pos   (21U)
     
    #define CAN_F3R1_FB21_Msk   (0x1UL << CAN_F3R1_FB21_Pos)
     
    #define CAN_F3R1_FB21   CAN_F3R1_FB21_Msk
     
    #define CAN_F3R1_FB22_Pos   (22U)
     
    #define CAN_F3R1_FB22_Msk   (0x1UL << CAN_F3R1_FB22_Pos)
     
    #define CAN_F3R1_FB22   CAN_F3R1_FB22_Msk
     
    #define CAN_F3R1_FB23_Pos   (23U)
     
    #define CAN_F3R1_FB23_Msk   (0x1UL << CAN_F3R1_FB23_Pos)
     
    #define CAN_F3R1_FB23   CAN_F3R1_FB23_Msk
     
    #define CAN_F3R1_FB24_Pos   (24U)
     
    #define CAN_F3R1_FB24_Msk   (0x1UL << CAN_F3R1_FB24_Pos)
     
    #define CAN_F3R1_FB24   CAN_F3R1_FB24_Msk
     
    #define CAN_F3R1_FB25_Pos   (25U)
     
    #define CAN_F3R1_FB25_Msk   (0x1UL << CAN_F3R1_FB25_Pos)
     
    #define CAN_F3R1_FB25   CAN_F3R1_FB25_Msk
     
    #define CAN_F3R1_FB26_Pos   (26U)
     
    #define CAN_F3R1_FB26_Msk   (0x1UL << CAN_F3R1_FB26_Pos)
     
    #define CAN_F3R1_FB26   CAN_F3R1_FB26_Msk
     
    #define CAN_F3R1_FB27_Pos   (27U)
     
    #define CAN_F3R1_FB27_Msk   (0x1UL << CAN_F3R1_FB27_Pos)
     
    #define CAN_F3R1_FB27   CAN_F3R1_FB27_Msk
     
    #define CAN_F3R1_FB28_Pos   (28U)
     
    #define CAN_F3R1_FB28_Msk   (0x1UL << CAN_F3R1_FB28_Pos)
     
    #define CAN_F3R1_FB28   CAN_F3R1_FB28_Msk
     
    #define CAN_F3R1_FB29_Pos   (29U)
     
    #define CAN_F3R1_FB29_Msk   (0x1UL << CAN_F3R1_FB29_Pos)
     
    #define CAN_F3R1_FB29   CAN_F3R1_FB29_Msk
     
    #define CAN_F3R1_FB30_Pos   (30U)
     
    #define CAN_F3R1_FB30_Msk   (0x1UL << CAN_F3R1_FB30_Pos)
     
    #define CAN_F3R1_FB30   CAN_F3R1_FB30_Msk
     
    #define CAN_F3R1_FB31_Pos   (31U)
     
    #define CAN_F3R1_FB31_Msk   (0x1UL << CAN_F3R1_FB31_Pos)
     
    #define CAN_F3R1_FB31   CAN_F3R1_FB31_Msk
     
    #define CAN_F4R1_FB0_Pos   (0U)
     
    #define CAN_F4R1_FB0_Msk   (0x1UL << CAN_F4R1_FB0_Pos)
     
    #define CAN_F4R1_FB0   CAN_F4R1_FB0_Msk
     
    #define CAN_F4R1_FB1_Pos   (1U)
     
    #define CAN_F4R1_FB1_Msk   (0x1UL << CAN_F4R1_FB1_Pos)
     
    #define CAN_F4R1_FB1   CAN_F4R1_FB1_Msk
     
    #define CAN_F4R1_FB2_Pos   (2U)
     
    #define CAN_F4R1_FB2_Msk   (0x1UL << CAN_F4R1_FB2_Pos)
     
    #define CAN_F4R1_FB2   CAN_F4R1_FB2_Msk
     
    #define CAN_F4R1_FB3_Pos   (3U)
     
    #define CAN_F4R1_FB3_Msk   (0x1UL << CAN_F4R1_FB3_Pos)
     
    #define CAN_F4R1_FB3   CAN_F4R1_FB3_Msk
     
    #define CAN_F4R1_FB4_Pos   (4U)
     
    #define CAN_F4R1_FB4_Msk   (0x1UL << CAN_F4R1_FB4_Pos)
     
    #define CAN_F4R1_FB4   CAN_F4R1_FB4_Msk
     
    #define CAN_F4R1_FB5_Pos   (5U)
     
    #define CAN_F4R1_FB5_Msk   (0x1UL << CAN_F4R1_FB5_Pos)
     
    #define CAN_F4R1_FB5   CAN_F4R1_FB5_Msk
     
    #define CAN_F4R1_FB6_Pos   (6U)
     
    #define CAN_F4R1_FB6_Msk   (0x1UL << CAN_F4R1_FB6_Pos)
     
    #define CAN_F4R1_FB6   CAN_F4R1_FB6_Msk
     
    #define CAN_F4R1_FB7_Pos   (7U)
     
    #define CAN_F4R1_FB7_Msk   (0x1UL << CAN_F4R1_FB7_Pos)
     
    #define CAN_F4R1_FB7   CAN_F4R1_FB7_Msk
     
    #define CAN_F4R1_FB8_Pos   (8U)
     
    #define CAN_F4R1_FB8_Msk   (0x1UL << CAN_F4R1_FB8_Pos)
     
    #define CAN_F4R1_FB8   CAN_F4R1_FB8_Msk
     
    #define CAN_F4R1_FB9_Pos   (9U)
     
    #define CAN_F4R1_FB9_Msk   (0x1UL << CAN_F4R1_FB9_Pos)
     
    #define CAN_F4R1_FB9   CAN_F4R1_FB9_Msk
     
    #define CAN_F4R1_FB10_Pos   (10U)
     
    #define CAN_F4R1_FB10_Msk   (0x1UL << CAN_F4R1_FB10_Pos)
     
    #define CAN_F4R1_FB10   CAN_F4R1_FB10_Msk
     
    #define CAN_F4R1_FB11_Pos   (11U)
     
    #define CAN_F4R1_FB11_Msk   (0x1UL << CAN_F4R1_FB11_Pos)
     
    #define CAN_F4R1_FB11   CAN_F4R1_FB11_Msk
     
    #define CAN_F4R1_FB12_Pos   (12U)
     
    #define CAN_F4R1_FB12_Msk   (0x1UL << CAN_F4R1_FB12_Pos)
     
    #define CAN_F4R1_FB12   CAN_F4R1_FB12_Msk
     
    #define CAN_F4R1_FB13_Pos   (13U)
     
    #define CAN_F4R1_FB13_Msk   (0x1UL << CAN_F4R1_FB13_Pos)
     
    #define CAN_F4R1_FB13   CAN_F4R1_FB13_Msk
     
    #define CAN_F4R1_FB14_Pos   (14U)
     
    #define CAN_F4R1_FB14_Msk   (0x1UL << CAN_F4R1_FB14_Pos)
     
    #define CAN_F4R1_FB14   CAN_F4R1_FB14_Msk
     
    #define CAN_F4R1_FB15_Pos   (15U)
     
    #define CAN_F4R1_FB15_Msk   (0x1UL << CAN_F4R1_FB15_Pos)
     
    #define CAN_F4R1_FB15   CAN_F4R1_FB15_Msk
     
    #define CAN_F4R1_FB16_Pos   (16U)
     
    #define CAN_F4R1_FB16_Msk   (0x1UL << CAN_F4R1_FB16_Pos)
     
    #define CAN_F4R1_FB16   CAN_F4R1_FB16_Msk
     
    #define CAN_F4R1_FB17_Pos   (17U)
     
    #define CAN_F4R1_FB17_Msk   (0x1UL << CAN_F4R1_FB17_Pos)
     
    #define CAN_F4R1_FB17   CAN_F4R1_FB17_Msk
     
    #define CAN_F4R1_FB18_Pos   (18U)
     
    #define CAN_F4R1_FB18_Msk   (0x1UL << CAN_F4R1_FB18_Pos)
     
    #define CAN_F4R1_FB18   CAN_F4R1_FB18_Msk
     
    #define CAN_F4R1_FB19_Pos   (19U)
     
    #define CAN_F4R1_FB19_Msk   (0x1UL << CAN_F4R1_FB19_Pos)
     
    #define CAN_F4R1_FB19   CAN_F4R1_FB19_Msk
     
    #define CAN_F4R1_FB20_Pos   (20U)
     
    #define CAN_F4R1_FB20_Msk   (0x1UL << CAN_F4R1_FB20_Pos)
     
    #define CAN_F4R1_FB20   CAN_F4R1_FB20_Msk
     
    #define CAN_F4R1_FB21_Pos   (21U)
     
    #define CAN_F4R1_FB21_Msk   (0x1UL << CAN_F4R1_FB21_Pos)
     
    #define CAN_F4R1_FB21   CAN_F4R1_FB21_Msk
     
    #define CAN_F4R1_FB22_Pos   (22U)
     
    #define CAN_F4R1_FB22_Msk   (0x1UL << CAN_F4R1_FB22_Pos)
     
    #define CAN_F4R1_FB22   CAN_F4R1_FB22_Msk
     
    #define CAN_F4R1_FB23_Pos   (23U)
     
    #define CAN_F4R1_FB23_Msk   (0x1UL << CAN_F4R1_FB23_Pos)
     
    #define CAN_F4R1_FB23   CAN_F4R1_FB23_Msk
     
    #define CAN_F4R1_FB24_Pos   (24U)
     
    #define CAN_F4R1_FB24_Msk   (0x1UL << CAN_F4R1_FB24_Pos)
     
    #define CAN_F4R1_FB24   CAN_F4R1_FB24_Msk
     
    #define CAN_F4R1_FB25_Pos   (25U)
     
    #define CAN_F4R1_FB25_Msk   (0x1UL << CAN_F4R1_FB25_Pos)
     
    #define CAN_F4R1_FB25   CAN_F4R1_FB25_Msk
     
    #define CAN_F4R1_FB26_Pos   (26U)
     
    #define CAN_F4R1_FB26_Msk   (0x1UL << CAN_F4R1_FB26_Pos)
     
    #define CAN_F4R1_FB26   CAN_F4R1_FB26_Msk
     
    #define CAN_F4R1_FB27_Pos   (27U)
     
    #define CAN_F4R1_FB27_Msk   (0x1UL << CAN_F4R1_FB27_Pos)
     
    #define CAN_F4R1_FB27   CAN_F4R1_FB27_Msk
     
    #define CAN_F4R1_FB28_Pos   (28U)
     
    #define CAN_F4R1_FB28_Msk   (0x1UL << CAN_F4R1_FB28_Pos)
     
    #define CAN_F4R1_FB28   CAN_F4R1_FB28_Msk
     
    #define CAN_F4R1_FB29_Pos   (29U)
     
    #define CAN_F4R1_FB29_Msk   (0x1UL << CAN_F4R1_FB29_Pos)
     
    #define CAN_F4R1_FB29   CAN_F4R1_FB29_Msk
     
    #define CAN_F4R1_FB30_Pos   (30U)
     
    #define CAN_F4R1_FB30_Msk   (0x1UL << CAN_F4R1_FB30_Pos)
     
    #define CAN_F4R1_FB30   CAN_F4R1_FB30_Msk
     
    #define CAN_F4R1_FB31_Pos   (31U)
     
    #define CAN_F4R1_FB31_Msk   (0x1UL << CAN_F4R1_FB31_Pos)
     
    #define CAN_F4R1_FB31   CAN_F4R1_FB31_Msk
     
    #define CAN_F5R1_FB0_Pos   (0U)
     
    #define CAN_F5R1_FB0_Msk   (0x1UL << CAN_F5R1_FB0_Pos)
     
    #define CAN_F5R1_FB0   CAN_F5R1_FB0_Msk
     
    #define CAN_F5R1_FB1_Pos   (1U)
     
    #define CAN_F5R1_FB1_Msk   (0x1UL << CAN_F5R1_FB1_Pos)
     
    #define CAN_F5R1_FB1   CAN_F5R1_FB1_Msk
     
    #define CAN_F5R1_FB2_Pos   (2U)
     
    #define CAN_F5R1_FB2_Msk   (0x1UL << CAN_F5R1_FB2_Pos)
     
    #define CAN_F5R1_FB2   CAN_F5R1_FB2_Msk
     
    #define CAN_F5R1_FB3_Pos   (3U)
     
    #define CAN_F5R1_FB3_Msk   (0x1UL << CAN_F5R1_FB3_Pos)
     
    #define CAN_F5R1_FB3   CAN_F5R1_FB3_Msk
     
    #define CAN_F5R1_FB4_Pos   (4U)
     
    #define CAN_F5R1_FB4_Msk   (0x1UL << CAN_F5R1_FB4_Pos)
     
    #define CAN_F5R1_FB4   CAN_F5R1_FB4_Msk
     
    #define CAN_F5R1_FB5_Pos   (5U)
     
    #define CAN_F5R1_FB5_Msk   (0x1UL << CAN_F5R1_FB5_Pos)
     
    #define CAN_F5R1_FB5   CAN_F5R1_FB5_Msk
     
    #define CAN_F5R1_FB6_Pos   (6U)
     
    #define CAN_F5R1_FB6_Msk   (0x1UL << CAN_F5R1_FB6_Pos)
     
    #define CAN_F5R1_FB6   CAN_F5R1_FB6_Msk
     
    #define CAN_F5R1_FB7_Pos   (7U)
     
    #define CAN_F5R1_FB7_Msk   (0x1UL << CAN_F5R1_FB7_Pos)
     
    #define CAN_F5R1_FB7   CAN_F5R1_FB7_Msk
     
    #define CAN_F5R1_FB8_Pos   (8U)
     
    #define CAN_F5R1_FB8_Msk   (0x1UL << CAN_F5R1_FB8_Pos)
     
    #define CAN_F5R1_FB8   CAN_F5R1_FB8_Msk
     
    #define CAN_F5R1_FB9_Pos   (9U)
     
    #define CAN_F5R1_FB9_Msk   (0x1UL << CAN_F5R1_FB9_Pos)
     
    #define CAN_F5R1_FB9   CAN_F5R1_FB9_Msk
     
    #define CAN_F5R1_FB10_Pos   (10U)
     
    #define CAN_F5R1_FB10_Msk   (0x1UL << CAN_F5R1_FB10_Pos)
     
    #define CAN_F5R1_FB10   CAN_F5R1_FB10_Msk
     
    #define CAN_F5R1_FB11_Pos   (11U)
     
    #define CAN_F5R1_FB11_Msk   (0x1UL << CAN_F5R1_FB11_Pos)
     
    #define CAN_F5R1_FB11   CAN_F5R1_FB11_Msk
     
    #define CAN_F5R1_FB12_Pos   (12U)
     
    #define CAN_F5R1_FB12_Msk   (0x1UL << CAN_F5R1_FB12_Pos)
     
    #define CAN_F5R1_FB12   CAN_F5R1_FB12_Msk
     
    #define CAN_F5R1_FB13_Pos   (13U)
     
    #define CAN_F5R1_FB13_Msk   (0x1UL << CAN_F5R1_FB13_Pos)
     
    #define CAN_F5R1_FB13   CAN_F5R1_FB13_Msk
     
    #define CAN_F5R1_FB14_Pos   (14U)
     
    #define CAN_F5R1_FB14_Msk   (0x1UL << CAN_F5R1_FB14_Pos)
     
    #define CAN_F5R1_FB14   CAN_F5R1_FB14_Msk
     
    #define CAN_F5R1_FB15_Pos   (15U)
     
    #define CAN_F5R1_FB15_Msk   (0x1UL << CAN_F5R1_FB15_Pos)
     
    #define CAN_F5R1_FB15   CAN_F5R1_FB15_Msk
     
    #define CAN_F5R1_FB16_Pos   (16U)
     
    #define CAN_F5R1_FB16_Msk   (0x1UL << CAN_F5R1_FB16_Pos)
     
    #define CAN_F5R1_FB16   CAN_F5R1_FB16_Msk
     
    #define CAN_F5R1_FB17_Pos   (17U)
     
    #define CAN_F5R1_FB17_Msk   (0x1UL << CAN_F5R1_FB17_Pos)
     
    #define CAN_F5R1_FB17   CAN_F5R1_FB17_Msk
     
    #define CAN_F5R1_FB18_Pos   (18U)
     
    #define CAN_F5R1_FB18_Msk   (0x1UL << CAN_F5R1_FB18_Pos)
     
    #define CAN_F5R1_FB18   CAN_F5R1_FB18_Msk
     
    #define CAN_F5R1_FB19_Pos   (19U)
     
    #define CAN_F5R1_FB19_Msk   (0x1UL << CAN_F5R1_FB19_Pos)
     
    #define CAN_F5R1_FB19   CAN_F5R1_FB19_Msk
     
    #define CAN_F5R1_FB20_Pos   (20U)
     
    #define CAN_F5R1_FB20_Msk   (0x1UL << CAN_F5R1_FB20_Pos)
     
    #define CAN_F5R1_FB20   CAN_F5R1_FB20_Msk
     
    #define CAN_F5R1_FB21_Pos   (21U)
     
    #define CAN_F5R1_FB21_Msk   (0x1UL << CAN_F5R1_FB21_Pos)
     
    #define CAN_F5R1_FB21   CAN_F5R1_FB21_Msk
     
    #define CAN_F5R1_FB22_Pos   (22U)
     
    #define CAN_F5R1_FB22_Msk   (0x1UL << CAN_F5R1_FB22_Pos)
     
    #define CAN_F5R1_FB22   CAN_F5R1_FB22_Msk
     
    #define CAN_F5R1_FB23_Pos   (23U)
     
    #define CAN_F5R1_FB23_Msk   (0x1UL << CAN_F5R1_FB23_Pos)
     
    #define CAN_F5R1_FB23   CAN_F5R1_FB23_Msk
     
    #define CAN_F5R1_FB24_Pos   (24U)
     
    #define CAN_F5R1_FB24_Msk   (0x1UL << CAN_F5R1_FB24_Pos)
     
    #define CAN_F5R1_FB24   CAN_F5R1_FB24_Msk
     
    #define CAN_F5R1_FB25_Pos   (25U)
     
    #define CAN_F5R1_FB25_Msk   (0x1UL << CAN_F5R1_FB25_Pos)
     
    #define CAN_F5R1_FB25   CAN_F5R1_FB25_Msk
     
    #define CAN_F5R1_FB26_Pos   (26U)
     
    #define CAN_F5R1_FB26_Msk   (0x1UL << CAN_F5R1_FB26_Pos)
     
    #define CAN_F5R1_FB26   CAN_F5R1_FB26_Msk
     
    #define CAN_F5R1_FB27_Pos   (27U)
     
    #define CAN_F5R1_FB27_Msk   (0x1UL << CAN_F5R1_FB27_Pos)
     
    #define CAN_F5R1_FB27   CAN_F5R1_FB27_Msk
     
    #define CAN_F5R1_FB28_Pos   (28U)
     
    #define CAN_F5R1_FB28_Msk   (0x1UL << CAN_F5R1_FB28_Pos)
     
    #define CAN_F5R1_FB28   CAN_F5R1_FB28_Msk
     
    #define CAN_F5R1_FB29_Pos   (29U)
     
    #define CAN_F5R1_FB29_Msk   (0x1UL << CAN_F5R1_FB29_Pos)
     
    #define CAN_F5R1_FB29   CAN_F5R1_FB29_Msk
     
    #define CAN_F5R1_FB30_Pos   (30U)
     
    #define CAN_F5R1_FB30_Msk   (0x1UL << CAN_F5R1_FB30_Pos)
     
    #define CAN_F5R1_FB30   CAN_F5R1_FB30_Msk
     
    #define CAN_F5R1_FB31_Pos   (31U)
     
    #define CAN_F5R1_FB31_Msk   (0x1UL << CAN_F5R1_FB31_Pos)
     
    #define CAN_F5R1_FB31   CAN_F5R1_FB31_Msk
     
    #define CAN_F6R1_FB0_Pos   (0U)
     
    #define CAN_F6R1_FB0_Msk   (0x1UL << CAN_F6R1_FB0_Pos)
     
    #define CAN_F6R1_FB0   CAN_F6R1_FB0_Msk
     
    #define CAN_F6R1_FB1_Pos   (1U)
     
    #define CAN_F6R1_FB1_Msk   (0x1UL << CAN_F6R1_FB1_Pos)
     
    #define CAN_F6R1_FB1   CAN_F6R1_FB1_Msk
     
    #define CAN_F6R1_FB2_Pos   (2U)
     
    #define CAN_F6R1_FB2_Msk   (0x1UL << CAN_F6R1_FB2_Pos)
     
    #define CAN_F6R1_FB2   CAN_F6R1_FB2_Msk
     
    #define CAN_F6R1_FB3_Pos   (3U)
     
    #define CAN_F6R1_FB3_Msk   (0x1UL << CAN_F6R1_FB3_Pos)
     
    #define CAN_F6R1_FB3   CAN_F6R1_FB3_Msk
     
    #define CAN_F6R1_FB4_Pos   (4U)
     
    #define CAN_F6R1_FB4_Msk   (0x1UL << CAN_F6R1_FB4_Pos)
     
    #define CAN_F6R1_FB4   CAN_F6R1_FB4_Msk
     
    #define CAN_F6R1_FB5_Pos   (5U)
     
    #define CAN_F6R1_FB5_Msk   (0x1UL << CAN_F6R1_FB5_Pos)
     
    #define CAN_F6R1_FB5   CAN_F6R1_FB5_Msk
     
    #define CAN_F6R1_FB6_Pos   (6U)
     
    #define CAN_F6R1_FB6_Msk   (0x1UL << CAN_F6R1_FB6_Pos)
     
    #define CAN_F6R1_FB6   CAN_F6R1_FB6_Msk
     
    #define CAN_F6R1_FB7_Pos   (7U)
     
    #define CAN_F6R1_FB7_Msk   (0x1UL << CAN_F6R1_FB7_Pos)
     
    #define CAN_F6R1_FB7   CAN_F6R1_FB7_Msk
     
    #define CAN_F6R1_FB8_Pos   (8U)
     
    #define CAN_F6R1_FB8_Msk   (0x1UL << CAN_F6R1_FB8_Pos)
     
    #define CAN_F6R1_FB8   CAN_F6R1_FB8_Msk
     
    #define CAN_F6R1_FB9_Pos   (9U)
     
    #define CAN_F6R1_FB9_Msk   (0x1UL << CAN_F6R1_FB9_Pos)
     
    #define CAN_F6R1_FB9   CAN_F6R1_FB9_Msk
     
    #define CAN_F6R1_FB10_Pos   (10U)
     
    #define CAN_F6R1_FB10_Msk   (0x1UL << CAN_F6R1_FB10_Pos)
     
    #define CAN_F6R1_FB10   CAN_F6R1_FB10_Msk
     
    #define CAN_F6R1_FB11_Pos   (11U)
     
    #define CAN_F6R1_FB11_Msk   (0x1UL << CAN_F6R1_FB11_Pos)
     
    #define CAN_F6R1_FB11   CAN_F6R1_FB11_Msk
     
    #define CAN_F6R1_FB12_Pos   (12U)
     
    #define CAN_F6R1_FB12_Msk   (0x1UL << CAN_F6R1_FB12_Pos)
     
    #define CAN_F6R1_FB12   CAN_F6R1_FB12_Msk
     
    #define CAN_F6R1_FB13_Pos   (13U)
     
    #define CAN_F6R1_FB13_Msk   (0x1UL << CAN_F6R1_FB13_Pos)
     
    #define CAN_F6R1_FB13   CAN_F6R1_FB13_Msk
     
    #define CAN_F6R1_FB14_Pos   (14U)
     
    #define CAN_F6R1_FB14_Msk   (0x1UL << CAN_F6R1_FB14_Pos)
     
    #define CAN_F6R1_FB14   CAN_F6R1_FB14_Msk
     
    #define CAN_F6R1_FB15_Pos   (15U)
     
    #define CAN_F6R1_FB15_Msk   (0x1UL << CAN_F6R1_FB15_Pos)
     
    #define CAN_F6R1_FB15   CAN_F6R1_FB15_Msk
     
    #define CAN_F6R1_FB16_Pos   (16U)
     
    #define CAN_F6R1_FB16_Msk   (0x1UL << CAN_F6R1_FB16_Pos)
     
    #define CAN_F6R1_FB16   CAN_F6R1_FB16_Msk
     
    #define CAN_F6R1_FB17_Pos   (17U)
     
    #define CAN_F6R1_FB17_Msk   (0x1UL << CAN_F6R1_FB17_Pos)
     
    #define CAN_F6R1_FB17   CAN_F6R1_FB17_Msk
     
    #define CAN_F6R1_FB18_Pos   (18U)
     
    #define CAN_F6R1_FB18_Msk   (0x1UL << CAN_F6R1_FB18_Pos)
     
    #define CAN_F6R1_FB18   CAN_F6R1_FB18_Msk
     
    #define CAN_F6R1_FB19_Pos   (19U)
     
    #define CAN_F6R1_FB19_Msk   (0x1UL << CAN_F6R1_FB19_Pos)
     
    #define CAN_F6R1_FB19   CAN_F6R1_FB19_Msk
     
    #define CAN_F6R1_FB20_Pos   (20U)
     
    #define CAN_F6R1_FB20_Msk   (0x1UL << CAN_F6R1_FB20_Pos)
     
    #define CAN_F6R1_FB20   CAN_F6R1_FB20_Msk
     
    #define CAN_F6R1_FB21_Pos   (21U)
     
    #define CAN_F6R1_FB21_Msk   (0x1UL << CAN_F6R1_FB21_Pos)
     
    #define CAN_F6R1_FB21   CAN_F6R1_FB21_Msk
     
    #define CAN_F6R1_FB22_Pos   (22U)
     
    #define CAN_F6R1_FB22_Msk   (0x1UL << CAN_F6R1_FB22_Pos)
     
    #define CAN_F6R1_FB22   CAN_F6R1_FB22_Msk
     
    #define CAN_F6R1_FB23_Pos   (23U)
     
    #define CAN_F6R1_FB23_Msk   (0x1UL << CAN_F6R1_FB23_Pos)
     
    #define CAN_F6R1_FB23   CAN_F6R1_FB23_Msk
     
    #define CAN_F6R1_FB24_Pos   (24U)
     
    #define CAN_F6R1_FB24_Msk   (0x1UL << CAN_F6R1_FB24_Pos)
     
    #define CAN_F6R1_FB24   CAN_F6R1_FB24_Msk
     
    #define CAN_F6R1_FB25_Pos   (25U)
     
    #define CAN_F6R1_FB25_Msk   (0x1UL << CAN_F6R1_FB25_Pos)
     
    #define CAN_F6R1_FB25   CAN_F6R1_FB25_Msk
     
    #define CAN_F6R1_FB26_Pos   (26U)
     
    #define CAN_F6R1_FB26_Msk   (0x1UL << CAN_F6R1_FB26_Pos)
     
    #define CAN_F6R1_FB26   CAN_F6R1_FB26_Msk
     
    #define CAN_F6R1_FB27_Pos   (27U)
     
    #define CAN_F6R1_FB27_Msk   (0x1UL << CAN_F6R1_FB27_Pos)
     
    #define CAN_F6R1_FB27   CAN_F6R1_FB27_Msk
     
    #define CAN_F6R1_FB28_Pos   (28U)
     
    #define CAN_F6R1_FB28_Msk   (0x1UL << CAN_F6R1_FB28_Pos)
     
    #define CAN_F6R1_FB28   CAN_F6R1_FB28_Msk
     
    #define CAN_F6R1_FB29_Pos   (29U)
     
    #define CAN_F6R1_FB29_Msk   (0x1UL << CAN_F6R1_FB29_Pos)
     
    #define CAN_F6R1_FB29   CAN_F6R1_FB29_Msk
     
    #define CAN_F6R1_FB30_Pos   (30U)
     
    #define CAN_F6R1_FB30_Msk   (0x1UL << CAN_F6R1_FB30_Pos)
     
    #define CAN_F6R1_FB30   CAN_F6R1_FB30_Msk
     
    #define CAN_F6R1_FB31_Pos   (31U)
     
    #define CAN_F6R1_FB31_Msk   (0x1UL << CAN_F6R1_FB31_Pos)
     
    #define CAN_F6R1_FB31   CAN_F6R1_FB31_Msk
     
    #define CAN_F7R1_FB0_Pos   (0U)
     
    #define CAN_F7R1_FB0_Msk   (0x1UL << CAN_F7R1_FB0_Pos)
     
    #define CAN_F7R1_FB0   CAN_F7R1_FB0_Msk
     
    #define CAN_F7R1_FB1_Pos   (1U)
     
    #define CAN_F7R1_FB1_Msk   (0x1UL << CAN_F7R1_FB1_Pos)
     
    #define CAN_F7R1_FB1   CAN_F7R1_FB1_Msk
     
    #define CAN_F7R1_FB2_Pos   (2U)
     
    #define CAN_F7R1_FB2_Msk   (0x1UL << CAN_F7R1_FB2_Pos)
     
    #define CAN_F7R1_FB2   CAN_F7R1_FB2_Msk
     
    #define CAN_F7R1_FB3_Pos   (3U)
     
    #define CAN_F7R1_FB3_Msk   (0x1UL << CAN_F7R1_FB3_Pos)
     
    #define CAN_F7R1_FB3   CAN_F7R1_FB3_Msk
     
    #define CAN_F7R1_FB4_Pos   (4U)
     
    #define CAN_F7R1_FB4_Msk   (0x1UL << CAN_F7R1_FB4_Pos)
     
    #define CAN_F7R1_FB4   CAN_F7R1_FB4_Msk
     
    #define CAN_F7R1_FB5_Pos   (5U)
     
    #define CAN_F7R1_FB5_Msk   (0x1UL << CAN_F7R1_FB5_Pos)
     
    #define CAN_F7R1_FB5   CAN_F7R1_FB5_Msk
     
    #define CAN_F7R1_FB6_Pos   (6U)
     
    #define CAN_F7R1_FB6_Msk   (0x1UL << CAN_F7R1_FB6_Pos)
     
    #define CAN_F7R1_FB6   CAN_F7R1_FB6_Msk
     
    #define CAN_F7R1_FB7_Pos   (7U)
     
    #define CAN_F7R1_FB7_Msk   (0x1UL << CAN_F7R1_FB7_Pos)
     
    #define CAN_F7R1_FB7   CAN_F7R1_FB7_Msk
     
    #define CAN_F7R1_FB8_Pos   (8U)
     
    #define CAN_F7R1_FB8_Msk   (0x1UL << CAN_F7R1_FB8_Pos)
     
    #define CAN_F7R1_FB8   CAN_F7R1_FB8_Msk
     
    #define CAN_F7R1_FB9_Pos   (9U)
     
    #define CAN_F7R1_FB9_Msk   (0x1UL << CAN_F7R1_FB9_Pos)
     
    #define CAN_F7R1_FB9   CAN_F7R1_FB9_Msk
     
    #define CAN_F7R1_FB10_Pos   (10U)
     
    #define CAN_F7R1_FB10_Msk   (0x1UL << CAN_F7R1_FB10_Pos)
     
    #define CAN_F7R1_FB10   CAN_F7R1_FB10_Msk
     
    #define CAN_F7R1_FB11_Pos   (11U)
     
    #define CAN_F7R1_FB11_Msk   (0x1UL << CAN_F7R1_FB11_Pos)
     
    #define CAN_F7R1_FB11   CAN_F7R1_FB11_Msk
     
    #define CAN_F7R1_FB12_Pos   (12U)
     
    #define CAN_F7R1_FB12_Msk   (0x1UL << CAN_F7R1_FB12_Pos)
     
    #define CAN_F7R1_FB12   CAN_F7R1_FB12_Msk
     
    #define CAN_F7R1_FB13_Pos   (13U)
     
    #define CAN_F7R1_FB13_Msk   (0x1UL << CAN_F7R1_FB13_Pos)
     
    #define CAN_F7R1_FB13   CAN_F7R1_FB13_Msk
     
    #define CAN_F7R1_FB14_Pos   (14U)
     
    #define CAN_F7R1_FB14_Msk   (0x1UL << CAN_F7R1_FB14_Pos)
     
    #define CAN_F7R1_FB14   CAN_F7R1_FB14_Msk
     
    #define CAN_F7R1_FB15_Pos   (15U)
     
    #define CAN_F7R1_FB15_Msk   (0x1UL << CAN_F7R1_FB15_Pos)
     
    #define CAN_F7R1_FB15   CAN_F7R1_FB15_Msk
     
    #define CAN_F7R1_FB16_Pos   (16U)
     
    #define CAN_F7R1_FB16_Msk   (0x1UL << CAN_F7R1_FB16_Pos)
     
    #define CAN_F7R1_FB16   CAN_F7R1_FB16_Msk
     
    #define CAN_F7R1_FB17_Pos   (17U)
     
    #define CAN_F7R1_FB17_Msk   (0x1UL << CAN_F7R1_FB17_Pos)
     
    #define CAN_F7R1_FB17   CAN_F7R1_FB17_Msk
     
    #define CAN_F7R1_FB18_Pos   (18U)
     
    #define CAN_F7R1_FB18_Msk   (0x1UL << CAN_F7R1_FB18_Pos)
     
    #define CAN_F7R1_FB18   CAN_F7R1_FB18_Msk
     
    #define CAN_F7R1_FB19_Pos   (19U)
     
    #define CAN_F7R1_FB19_Msk   (0x1UL << CAN_F7R1_FB19_Pos)
     
    #define CAN_F7R1_FB19   CAN_F7R1_FB19_Msk
     
    #define CAN_F7R1_FB20_Pos   (20U)
     
    #define CAN_F7R1_FB20_Msk   (0x1UL << CAN_F7R1_FB20_Pos)
     
    #define CAN_F7R1_FB20   CAN_F7R1_FB20_Msk
     
    #define CAN_F7R1_FB21_Pos   (21U)
     
    #define CAN_F7R1_FB21_Msk   (0x1UL << CAN_F7R1_FB21_Pos)
     
    #define CAN_F7R1_FB21   CAN_F7R1_FB21_Msk
     
    #define CAN_F7R1_FB22_Pos   (22U)
     
    #define CAN_F7R1_FB22_Msk   (0x1UL << CAN_F7R1_FB22_Pos)
     
    #define CAN_F7R1_FB22   CAN_F7R1_FB22_Msk
     
    #define CAN_F7R1_FB23_Pos   (23U)
     
    #define CAN_F7R1_FB23_Msk   (0x1UL << CAN_F7R1_FB23_Pos)
     
    #define CAN_F7R1_FB23   CAN_F7R1_FB23_Msk
     
    #define CAN_F7R1_FB24_Pos   (24U)
     
    #define CAN_F7R1_FB24_Msk   (0x1UL << CAN_F7R1_FB24_Pos)
     
    #define CAN_F7R1_FB24   CAN_F7R1_FB24_Msk
     
    #define CAN_F7R1_FB25_Pos   (25U)
     
    #define CAN_F7R1_FB25_Msk   (0x1UL << CAN_F7R1_FB25_Pos)
     
    #define CAN_F7R1_FB25   CAN_F7R1_FB25_Msk
     
    #define CAN_F7R1_FB26_Pos   (26U)
     
    #define CAN_F7R1_FB26_Msk   (0x1UL << CAN_F7R1_FB26_Pos)
     
    #define CAN_F7R1_FB26   CAN_F7R1_FB26_Msk
     
    #define CAN_F7R1_FB27_Pos   (27U)
     
    #define CAN_F7R1_FB27_Msk   (0x1UL << CAN_F7R1_FB27_Pos)
     
    #define CAN_F7R1_FB27   CAN_F7R1_FB27_Msk
     
    #define CAN_F7R1_FB28_Pos   (28U)
     
    #define CAN_F7R1_FB28_Msk   (0x1UL << CAN_F7R1_FB28_Pos)
     
    #define CAN_F7R1_FB28   CAN_F7R1_FB28_Msk
     
    #define CAN_F7R1_FB29_Pos   (29U)
     
    #define CAN_F7R1_FB29_Msk   (0x1UL << CAN_F7R1_FB29_Pos)
     
    #define CAN_F7R1_FB29   CAN_F7R1_FB29_Msk
     
    #define CAN_F7R1_FB30_Pos   (30U)
     
    #define CAN_F7R1_FB30_Msk   (0x1UL << CAN_F7R1_FB30_Pos)
     
    #define CAN_F7R1_FB30   CAN_F7R1_FB30_Msk
     
    #define CAN_F7R1_FB31_Pos   (31U)
     
    #define CAN_F7R1_FB31_Msk   (0x1UL << CAN_F7R1_FB31_Pos)
     
    #define CAN_F7R1_FB31   CAN_F7R1_FB31_Msk
     
    #define CAN_F8R1_FB0_Pos   (0U)
     
    #define CAN_F8R1_FB0_Msk   (0x1UL << CAN_F8R1_FB0_Pos)
     
    #define CAN_F8R1_FB0   CAN_F8R1_FB0_Msk
     
    #define CAN_F8R1_FB1_Pos   (1U)
     
    #define CAN_F8R1_FB1_Msk   (0x1UL << CAN_F8R1_FB1_Pos)
     
    #define CAN_F8R1_FB1   CAN_F8R1_FB1_Msk
     
    #define CAN_F8R1_FB2_Pos   (2U)
     
    #define CAN_F8R1_FB2_Msk   (0x1UL << CAN_F8R1_FB2_Pos)
     
    #define CAN_F8R1_FB2   CAN_F8R1_FB2_Msk
     
    #define CAN_F8R1_FB3_Pos   (3U)
     
    #define CAN_F8R1_FB3_Msk   (0x1UL << CAN_F8R1_FB3_Pos)
     
    #define CAN_F8R1_FB3   CAN_F8R1_FB3_Msk
     
    #define CAN_F8R1_FB4_Pos   (4U)
     
    #define CAN_F8R1_FB4_Msk   (0x1UL << CAN_F8R1_FB4_Pos)
     
    #define CAN_F8R1_FB4   CAN_F8R1_FB4_Msk
     
    #define CAN_F8R1_FB5_Pos   (5U)
     
    #define CAN_F8R1_FB5_Msk   (0x1UL << CAN_F8R1_FB5_Pos)
     
    #define CAN_F8R1_FB5   CAN_F8R1_FB5_Msk
     
    #define CAN_F8R1_FB6_Pos   (6U)
     
    #define CAN_F8R1_FB6_Msk   (0x1UL << CAN_F8R1_FB6_Pos)
     
    #define CAN_F8R1_FB6   CAN_F8R1_FB6_Msk
     
    #define CAN_F8R1_FB7_Pos   (7U)
     
    #define CAN_F8R1_FB7_Msk   (0x1UL << CAN_F8R1_FB7_Pos)
     
    #define CAN_F8R1_FB7   CAN_F8R1_FB7_Msk
     
    #define CAN_F8R1_FB8_Pos   (8U)
     
    #define CAN_F8R1_FB8_Msk   (0x1UL << CAN_F8R1_FB8_Pos)
     
    #define CAN_F8R1_FB8   CAN_F8R1_FB8_Msk
     
    #define CAN_F8R1_FB9_Pos   (9U)
     
    #define CAN_F8R1_FB9_Msk   (0x1UL << CAN_F8R1_FB9_Pos)
     
    #define CAN_F8R1_FB9   CAN_F8R1_FB9_Msk
     
    #define CAN_F8R1_FB10_Pos   (10U)
     
    #define CAN_F8R1_FB10_Msk   (0x1UL << CAN_F8R1_FB10_Pos)
     
    #define CAN_F8R1_FB10   CAN_F8R1_FB10_Msk
     
    #define CAN_F8R1_FB11_Pos   (11U)
     
    #define CAN_F8R1_FB11_Msk   (0x1UL << CAN_F8R1_FB11_Pos)
     
    #define CAN_F8R1_FB11   CAN_F8R1_FB11_Msk
     
    #define CAN_F8R1_FB12_Pos   (12U)
     
    #define CAN_F8R1_FB12_Msk   (0x1UL << CAN_F8R1_FB12_Pos)
     
    #define CAN_F8R1_FB12   CAN_F8R1_FB12_Msk
     
    #define CAN_F8R1_FB13_Pos   (13U)
     
    #define CAN_F8R1_FB13_Msk   (0x1UL << CAN_F8R1_FB13_Pos)
     
    #define CAN_F8R1_FB13   CAN_F8R1_FB13_Msk
     
    #define CAN_F8R1_FB14_Pos   (14U)
     
    #define CAN_F8R1_FB14_Msk   (0x1UL << CAN_F8R1_FB14_Pos)
     
    #define CAN_F8R1_FB14   CAN_F8R1_FB14_Msk
     
    #define CAN_F8R1_FB15_Pos   (15U)
     
    #define CAN_F8R1_FB15_Msk   (0x1UL << CAN_F8R1_FB15_Pos)
     
    #define CAN_F8R1_FB15   CAN_F8R1_FB15_Msk
     
    #define CAN_F8R1_FB16_Pos   (16U)
     
    #define CAN_F8R1_FB16_Msk   (0x1UL << CAN_F8R1_FB16_Pos)
     
    #define CAN_F8R1_FB16   CAN_F8R1_FB16_Msk
     
    #define CAN_F8R1_FB17_Pos   (17U)
     
    #define CAN_F8R1_FB17_Msk   (0x1UL << CAN_F8R1_FB17_Pos)
     
    #define CAN_F8R1_FB17   CAN_F8R1_FB17_Msk
     
    #define CAN_F8R1_FB18_Pos   (18U)
     
    #define CAN_F8R1_FB18_Msk   (0x1UL << CAN_F8R1_FB18_Pos)
     
    #define CAN_F8R1_FB18   CAN_F8R1_FB18_Msk
     
    #define CAN_F8R1_FB19_Pos   (19U)
     
    #define CAN_F8R1_FB19_Msk   (0x1UL << CAN_F8R1_FB19_Pos)
     
    #define CAN_F8R1_FB19   CAN_F8R1_FB19_Msk
     
    #define CAN_F8R1_FB20_Pos   (20U)
     
    #define CAN_F8R1_FB20_Msk   (0x1UL << CAN_F8R1_FB20_Pos)
     
    #define CAN_F8R1_FB20   CAN_F8R1_FB20_Msk
     
    #define CAN_F8R1_FB21_Pos   (21U)
     
    #define CAN_F8R1_FB21_Msk   (0x1UL << CAN_F8R1_FB21_Pos)
     
    #define CAN_F8R1_FB21   CAN_F8R1_FB21_Msk
     
    #define CAN_F8R1_FB22_Pos   (22U)
     
    #define CAN_F8R1_FB22_Msk   (0x1UL << CAN_F8R1_FB22_Pos)
     
    #define CAN_F8R1_FB22   CAN_F8R1_FB22_Msk
     
    #define CAN_F8R1_FB23_Pos   (23U)
     
    #define CAN_F8R1_FB23_Msk   (0x1UL << CAN_F8R1_FB23_Pos)
     
    #define CAN_F8R1_FB23   CAN_F8R1_FB23_Msk
     
    #define CAN_F8R1_FB24_Pos   (24U)
     
    #define CAN_F8R1_FB24_Msk   (0x1UL << CAN_F8R1_FB24_Pos)
     
    #define CAN_F8R1_FB24   CAN_F8R1_FB24_Msk
     
    #define CAN_F8R1_FB25_Pos   (25U)
     
    #define CAN_F8R1_FB25_Msk   (0x1UL << CAN_F8R1_FB25_Pos)
     
    #define CAN_F8R1_FB25   CAN_F8R1_FB25_Msk
     
    #define CAN_F8R1_FB26_Pos   (26U)
     
    #define CAN_F8R1_FB26_Msk   (0x1UL << CAN_F8R1_FB26_Pos)
     
    #define CAN_F8R1_FB26   CAN_F8R1_FB26_Msk
     
    #define CAN_F8R1_FB27_Pos   (27U)
     
    #define CAN_F8R1_FB27_Msk   (0x1UL << CAN_F8R1_FB27_Pos)
     
    #define CAN_F8R1_FB27   CAN_F8R1_FB27_Msk
     
    #define CAN_F8R1_FB28_Pos   (28U)
     
    #define CAN_F8R1_FB28_Msk   (0x1UL << CAN_F8R1_FB28_Pos)
     
    #define CAN_F8R1_FB28   CAN_F8R1_FB28_Msk
     
    #define CAN_F8R1_FB29_Pos   (29U)
     
    #define CAN_F8R1_FB29_Msk   (0x1UL << CAN_F8R1_FB29_Pos)
     
    #define CAN_F8R1_FB29   CAN_F8R1_FB29_Msk
     
    #define CAN_F8R1_FB30_Pos   (30U)
     
    #define CAN_F8R1_FB30_Msk   (0x1UL << CAN_F8R1_FB30_Pos)
     
    #define CAN_F8R1_FB30   CAN_F8R1_FB30_Msk
     
    #define CAN_F8R1_FB31_Pos   (31U)
     
    #define CAN_F8R1_FB31_Msk   (0x1UL << CAN_F8R1_FB31_Pos)
     
    #define CAN_F8R1_FB31   CAN_F8R1_FB31_Msk
     
    #define CAN_F9R1_FB0_Pos   (0U)
     
    #define CAN_F9R1_FB0_Msk   (0x1UL << CAN_F9R1_FB0_Pos)
     
    #define CAN_F9R1_FB0   CAN_F9R1_FB0_Msk
     
    #define CAN_F9R1_FB1_Pos   (1U)
     
    #define CAN_F9R1_FB1_Msk   (0x1UL << CAN_F9R1_FB1_Pos)
     
    #define CAN_F9R1_FB1   CAN_F9R1_FB1_Msk
     
    #define CAN_F9R1_FB2_Pos   (2U)
     
    #define CAN_F9R1_FB2_Msk   (0x1UL << CAN_F9R1_FB2_Pos)
     
    #define CAN_F9R1_FB2   CAN_F9R1_FB2_Msk
     
    #define CAN_F9R1_FB3_Pos   (3U)
     
    #define CAN_F9R1_FB3_Msk   (0x1UL << CAN_F9R1_FB3_Pos)
     
    #define CAN_F9R1_FB3   CAN_F9R1_FB3_Msk
     
    #define CAN_F9R1_FB4_Pos   (4U)
     
    #define CAN_F9R1_FB4_Msk   (0x1UL << CAN_F9R1_FB4_Pos)
     
    #define CAN_F9R1_FB4   CAN_F9R1_FB4_Msk
     
    #define CAN_F9R1_FB5_Pos   (5U)
     
    #define CAN_F9R1_FB5_Msk   (0x1UL << CAN_F9R1_FB5_Pos)
     
    #define CAN_F9R1_FB5   CAN_F9R1_FB5_Msk
     
    #define CAN_F9R1_FB6_Pos   (6U)
     
    #define CAN_F9R1_FB6_Msk   (0x1UL << CAN_F9R1_FB6_Pos)
     
    #define CAN_F9R1_FB6   CAN_F9R1_FB6_Msk
     
    #define CAN_F9R1_FB7_Pos   (7U)
     
    #define CAN_F9R1_FB7_Msk   (0x1UL << CAN_F9R1_FB7_Pos)
     
    #define CAN_F9R1_FB7   CAN_F9R1_FB7_Msk
     
    #define CAN_F9R1_FB8_Pos   (8U)
     
    #define CAN_F9R1_FB8_Msk   (0x1UL << CAN_F9R1_FB8_Pos)
     
    #define CAN_F9R1_FB8   CAN_F9R1_FB8_Msk
     
    #define CAN_F9R1_FB9_Pos   (9U)
     
    #define CAN_F9R1_FB9_Msk   (0x1UL << CAN_F9R1_FB9_Pos)
     
    #define CAN_F9R1_FB9   CAN_F9R1_FB9_Msk
     
    #define CAN_F9R1_FB10_Pos   (10U)
     
    #define CAN_F9R1_FB10_Msk   (0x1UL << CAN_F9R1_FB10_Pos)
     
    #define CAN_F9R1_FB10   CAN_F9R1_FB10_Msk
     
    #define CAN_F9R1_FB11_Pos   (11U)
     
    #define CAN_F9R1_FB11_Msk   (0x1UL << CAN_F9R1_FB11_Pos)
     
    #define CAN_F9R1_FB11   CAN_F9R1_FB11_Msk
     
    #define CAN_F9R1_FB12_Pos   (12U)
     
    #define CAN_F9R1_FB12_Msk   (0x1UL << CAN_F9R1_FB12_Pos)
     
    #define CAN_F9R1_FB12   CAN_F9R1_FB12_Msk
     
    #define CAN_F9R1_FB13_Pos   (13U)
     
    #define CAN_F9R1_FB13_Msk   (0x1UL << CAN_F9R1_FB13_Pos)
     
    #define CAN_F9R1_FB13   CAN_F9R1_FB13_Msk
     
    #define CAN_F9R1_FB14_Pos   (14U)
     
    #define CAN_F9R1_FB14_Msk   (0x1UL << CAN_F9R1_FB14_Pos)
     
    #define CAN_F9R1_FB14   CAN_F9R1_FB14_Msk
     
    #define CAN_F9R1_FB15_Pos   (15U)
     
    #define CAN_F9R1_FB15_Msk   (0x1UL << CAN_F9R1_FB15_Pos)
     
    #define CAN_F9R1_FB15   CAN_F9R1_FB15_Msk
     
    #define CAN_F9R1_FB16_Pos   (16U)
     
    #define CAN_F9R1_FB16_Msk   (0x1UL << CAN_F9R1_FB16_Pos)
     
    #define CAN_F9R1_FB16   CAN_F9R1_FB16_Msk
     
    #define CAN_F9R1_FB17_Pos   (17U)
     
    #define CAN_F9R1_FB17_Msk   (0x1UL << CAN_F9R1_FB17_Pos)
     
    #define CAN_F9R1_FB17   CAN_F9R1_FB17_Msk
     
    #define CAN_F9R1_FB18_Pos   (18U)
     
    #define CAN_F9R1_FB18_Msk   (0x1UL << CAN_F9R1_FB18_Pos)
     
    #define CAN_F9R1_FB18   CAN_F9R1_FB18_Msk
     
    #define CAN_F9R1_FB19_Pos   (19U)
     
    #define CAN_F9R1_FB19_Msk   (0x1UL << CAN_F9R1_FB19_Pos)
     
    #define CAN_F9R1_FB19   CAN_F9R1_FB19_Msk
     
    #define CAN_F9R1_FB20_Pos   (20U)
     
    #define CAN_F9R1_FB20_Msk   (0x1UL << CAN_F9R1_FB20_Pos)
     
    #define CAN_F9R1_FB20   CAN_F9R1_FB20_Msk
     
    #define CAN_F9R1_FB21_Pos   (21U)
     
    #define CAN_F9R1_FB21_Msk   (0x1UL << CAN_F9R1_FB21_Pos)
     
    #define CAN_F9R1_FB21   CAN_F9R1_FB21_Msk
     
    #define CAN_F9R1_FB22_Pos   (22U)
     
    #define CAN_F9R1_FB22_Msk   (0x1UL << CAN_F9R1_FB22_Pos)
     
    #define CAN_F9R1_FB22   CAN_F9R1_FB22_Msk
     
    #define CAN_F9R1_FB23_Pos   (23U)
     
    #define CAN_F9R1_FB23_Msk   (0x1UL << CAN_F9R1_FB23_Pos)
     
    #define CAN_F9R1_FB23   CAN_F9R1_FB23_Msk
     
    #define CAN_F9R1_FB24_Pos   (24U)
     
    #define CAN_F9R1_FB24_Msk   (0x1UL << CAN_F9R1_FB24_Pos)
     
    #define CAN_F9R1_FB24   CAN_F9R1_FB24_Msk
     
    #define CAN_F9R1_FB25_Pos   (25U)
     
    #define CAN_F9R1_FB25_Msk   (0x1UL << CAN_F9R1_FB25_Pos)
     
    #define CAN_F9R1_FB25   CAN_F9R1_FB25_Msk
     
    #define CAN_F9R1_FB26_Pos   (26U)
     
    #define CAN_F9R1_FB26_Msk   (0x1UL << CAN_F9R1_FB26_Pos)
     
    #define CAN_F9R1_FB26   CAN_F9R1_FB26_Msk
     
    #define CAN_F9R1_FB27_Pos   (27U)
     
    #define CAN_F9R1_FB27_Msk   (0x1UL << CAN_F9R1_FB27_Pos)
     
    #define CAN_F9R1_FB27   CAN_F9R1_FB27_Msk
     
    #define CAN_F9R1_FB28_Pos   (28U)
     
    #define CAN_F9R1_FB28_Msk   (0x1UL << CAN_F9R1_FB28_Pos)
     
    #define CAN_F9R1_FB28   CAN_F9R1_FB28_Msk
     
    #define CAN_F9R1_FB29_Pos   (29U)
     
    #define CAN_F9R1_FB29_Msk   (0x1UL << CAN_F9R1_FB29_Pos)
     
    #define CAN_F9R1_FB29   CAN_F9R1_FB29_Msk
     
    #define CAN_F9R1_FB30_Pos   (30U)
     
    #define CAN_F9R1_FB30_Msk   (0x1UL << CAN_F9R1_FB30_Pos)
     
    #define CAN_F9R1_FB30   CAN_F9R1_FB30_Msk
     
    #define CAN_F9R1_FB31_Pos   (31U)
     
    #define CAN_F9R1_FB31_Msk   (0x1UL << CAN_F9R1_FB31_Pos)
     
    #define CAN_F9R1_FB31   CAN_F9R1_FB31_Msk
     
    #define CAN_F10R1_FB0_Pos   (0U)
     
    #define CAN_F10R1_FB0_Msk   (0x1UL << CAN_F10R1_FB0_Pos)
     
    #define CAN_F10R1_FB0   CAN_F10R1_FB0_Msk
     
    #define CAN_F10R1_FB1_Pos   (1U)
     
    #define CAN_F10R1_FB1_Msk   (0x1UL << CAN_F10R1_FB1_Pos)
     
    #define CAN_F10R1_FB1   CAN_F10R1_FB1_Msk
     
    #define CAN_F10R1_FB2_Pos   (2U)
     
    #define CAN_F10R1_FB2_Msk   (0x1UL << CAN_F10R1_FB2_Pos)
     
    #define CAN_F10R1_FB2   CAN_F10R1_FB2_Msk
     
    #define CAN_F10R1_FB3_Pos   (3U)
     
    #define CAN_F10R1_FB3_Msk   (0x1UL << CAN_F10R1_FB3_Pos)
     
    #define CAN_F10R1_FB3   CAN_F10R1_FB3_Msk
     
    #define CAN_F10R1_FB4_Pos   (4U)
     
    #define CAN_F10R1_FB4_Msk   (0x1UL << CAN_F10R1_FB4_Pos)
     
    #define CAN_F10R1_FB4   CAN_F10R1_FB4_Msk
     
    #define CAN_F10R1_FB5_Pos   (5U)
     
    #define CAN_F10R1_FB5_Msk   (0x1UL << CAN_F10R1_FB5_Pos)
     
    #define CAN_F10R1_FB5   CAN_F10R1_FB5_Msk
     
    #define CAN_F10R1_FB6_Pos   (6U)
     
    #define CAN_F10R1_FB6_Msk   (0x1UL << CAN_F10R1_FB6_Pos)
     
    #define CAN_F10R1_FB6   CAN_F10R1_FB6_Msk
     
    #define CAN_F10R1_FB7_Pos   (7U)
     
    #define CAN_F10R1_FB7_Msk   (0x1UL << CAN_F10R1_FB7_Pos)
     
    #define CAN_F10R1_FB7   CAN_F10R1_FB7_Msk
     
    #define CAN_F10R1_FB8_Pos   (8U)
     
    #define CAN_F10R1_FB8_Msk   (0x1UL << CAN_F10R1_FB8_Pos)
     
    #define CAN_F10R1_FB8   CAN_F10R1_FB8_Msk
     
    #define CAN_F10R1_FB9_Pos   (9U)
     
    #define CAN_F10R1_FB9_Msk   (0x1UL << CAN_F10R1_FB9_Pos)
     
    #define CAN_F10R1_FB9   CAN_F10R1_FB9_Msk
     
    #define CAN_F10R1_FB10_Pos   (10U)
     
    #define CAN_F10R1_FB10_Msk   (0x1UL << CAN_F10R1_FB10_Pos)
     
    #define CAN_F10R1_FB10   CAN_F10R1_FB10_Msk
     
    #define CAN_F10R1_FB11_Pos   (11U)
     
    #define CAN_F10R1_FB11_Msk   (0x1UL << CAN_F10R1_FB11_Pos)
     
    #define CAN_F10R1_FB11   CAN_F10R1_FB11_Msk
     
    #define CAN_F10R1_FB12_Pos   (12U)
     
    #define CAN_F10R1_FB12_Msk   (0x1UL << CAN_F10R1_FB12_Pos)
     
    #define CAN_F10R1_FB12   CAN_F10R1_FB12_Msk
     
    #define CAN_F10R1_FB13_Pos   (13U)
     
    #define CAN_F10R1_FB13_Msk   (0x1UL << CAN_F10R1_FB13_Pos)
     
    #define CAN_F10R1_FB13   CAN_F10R1_FB13_Msk
     
    #define CAN_F10R1_FB14_Pos   (14U)
     
    #define CAN_F10R1_FB14_Msk   (0x1UL << CAN_F10R1_FB14_Pos)
     
    #define CAN_F10R1_FB14   CAN_F10R1_FB14_Msk
     
    #define CAN_F10R1_FB15_Pos   (15U)
     
    #define CAN_F10R1_FB15_Msk   (0x1UL << CAN_F10R1_FB15_Pos)
     
    #define CAN_F10R1_FB15   CAN_F10R1_FB15_Msk
     
    #define CAN_F10R1_FB16_Pos   (16U)
     
    #define CAN_F10R1_FB16_Msk   (0x1UL << CAN_F10R1_FB16_Pos)
     
    #define CAN_F10R1_FB16   CAN_F10R1_FB16_Msk
     
    #define CAN_F10R1_FB17_Pos   (17U)
     
    #define CAN_F10R1_FB17_Msk   (0x1UL << CAN_F10R1_FB17_Pos)
     
    #define CAN_F10R1_FB17   CAN_F10R1_FB17_Msk
     
    #define CAN_F10R1_FB18_Pos   (18U)
     
    #define CAN_F10R1_FB18_Msk   (0x1UL << CAN_F10R1_FB18_Pos)
     
    #define CAN_F10R1_FB18   CAN_F10R1_FB18_Msk
     
    #define CAN_F10R1_FB19_Pos   (19U)
     
    #define CAN_F10R1_FB19_Msk   (0x1UL << CAN_F10R1_FB19_Pos)
     
    #define CAN_F10R1_FB19   CAN_F10R1_FB19_Msk
     
    #define CAN_F10R1_FB20_Pos   (20U)
     
    #define CAN_F10R1_FB20_Msk   (0x1UL << CAN_F10R1_FB20_Pos)
     
    #define CAN_F10R1_FB20   CAN_F10R1_FB20_Msk
     
    #define CAN_F10R1_FB21_Pos   (21U)
     
    #define CAN_F10R1_FB21_Msk   (0x1UL << CAN_F10R1_FB21_Pos)
     
    #define CAN_F10R1_FB21   CAN_F10R1_FB21_Msk
     
    #define CAN_F10R1_FB22_Pos   (22U)
     
    #define CAN_F10R1_FB22_Msk   (0x1UL << CAN_F10R1_FB22_Pos)
     
    #define CAN_F10R1_FB22   CAN_F10R1_FB22_Msk
     
    #define CAN_F10R1_FB23_Pos   (23U)
     
    #define CAN_F10R1_FB23_Msk   (0x1UL << CAN_F10R1_FB23_Pos)
     
    #define CAN_F10R1_FB23   CAN_F10R1_FB23_Msk
     
    #define CAN_F10R1_FB24_Pos   (24U)
     
    #define CAN_F10R1_FB24_Msk   (0x1UL << CAN_F10R1_FB24_Pos)
     
    #define CAN_F10R1_FB24   CAN_F10R1_FB24_Msk
     
    #define CAN_F10R1_FB25_Pos   (25U)
     
    #define CAN_F10R1_FB25_Msk   (0x1UL << CAN_F10R1_FB25_Pos)
     
    #define CAN_F10R1_FB25   CAN_F10R1_FB25_Msk
     
    #define CAN_F10R1_FB26_Pos   (26U)
     
    #define CAN_F10R1_FB26_Msk   (0x1UL << CAN_F10R1_FB26_Pos)
     
    #define CAN_F10R1_FB26   CAN_F10R1_FB26_Msk
     
    #define CAN_F10R1_FB27_Pos   (27U)
     
    #define CAN_F10R1_FB27_Msk   (0x1UL << CAN_F10R1_FB27_Pos)
     
    #define CAN_F10R1_FB27   CAN_F10R1_FB27_Msk
     
    #define CAN_F10R1_FB28_Pos   (28U)
     
    #define CAN_F10R1_FB28_Msk   (0x1UL << CAN_F10R1_FB28_Pos)
     
    #define CAN_F10R1_FB28   CAN_F10R1_FB28_Msk
     
    #define CAN_F10R1_FB29_Pos   (29U)
     
    #define CAN_F10R1_FB29_Msk   (0x1UL << CAN_F10R1_FB29_Pos)
     
    #define CAN_F10R1_FB29   CAN_F10R1_FB29_Msk
     
    #define CAN_F10R1_FB30_Pos   (30U)
     
    #define CAN_F10R1_FB30_Msk   (0x1UL << CAN_F10R1_FB30_Pos)
     
    #define CAN_F10R1_FB30   CAN_F10R1_FB30_Msk
     
    #define CAN_F10R1_FB31_Pos   (31U)
     
    #define CAN_F10R1_FB31_Msk   (0x1UL << CAN_F10R1_FB31_Pos)
     
    #define CAN_F10R1_FB31   CAN_F10R1_FB31_Msk
     
    #define CAN_F11R1_FB0_Pos   (0U)
     
    #define CAN_F11R1_FB0_Msk   (0x1UL << CAN_F11R1_FB0_Pos)
     
    #define CAN_F11R1_FB0   CAN_F11R1_FB0_Msk
     
    #define CAN_F11R1_FB1_Pos   (1U)
     
    #define CAN_F11R1_FB1_Msk   (0x1UL << CAN_F11R1_FB1_Pos)
     
    #define CAN_F11R1_FB1   CAN_F11R1_FB1_Msk
     
    #define CAN_F11R1_FB2_Pos   (2U)
     
    #define CAN_F11R1_FB2_Msk   (0x1UL << CAN_F11R1_FB2_Pos)
     
    #define CAN_F11R1_FB2   CAN_F11R1_FB2_Msk
     
    #define CAN_F11R1_FB3_Pos   (3U)
     
    #define CAN_F11R1_FB3_Msk   (0x1UL << CAN_F11R1_FB3_Pos)
     
    #define CAN_F11R1_FB3   CAN_F11R1_FB3_Msk
     
    #define CAN_F11R1_FB4_Pos   (4U)
     
    #define CAN_F11R1_FB4_Msk   (0x1UL << CAN_F11R1_FB4_Pos)
     
    #define CAN_F11R1_FB4   CAN_F11R1_FB4_Msk
     
    #define CAN_F11R1_FB5_Pos   (5U)
     
    #define CAN_F11R1_FB5_Msk   (0x1UL << CAN_F11R1_FB5_Pos)
     
    #define CAN_F11R1_FB5   CAN_F11R1_FB5_Msk
     
    #define CAN_F11R1_FB6_Pos   (6U)
     
    #define CAN_F11R1_FB6_Msk   (0x1UL << CAN_F11R1_FB6_Pos)
     
    #define CAN_F11R1_FB6   CAN_F11R1_FB6_Msk
     
    #define CAN_F11R1_FB7_Pos   (7U)
     
    #define CAN_F11R1_FB7_Msk   (0x1UL << CAN_F11R1_FB7_Pos)
     
    #define CAN_F11R1_FB7   CAN_F11R1_FB7_Msk
     
    #define CAN_F11R1_FB8_Pos   (8U)
     
    #define CAN_F11R1_FB8_Msk   (0x1UL << CAN_F11R1_FB8_Pos)
     
    #define CAN_F11R1_FB8   CAN_F11R1_FB8_Msk
     
    #define CAN_F11R1_FB9_Pos   (9U)
     
    #define CAN_F11R1_FB9_Msk   (0x1UL << CAN_F11R1_FB9_Pos)
     
    #define CAN_F11R1_FB9   CAN_F11R1_FB9_Msk
     
    #define CAN_F11R1_FB10_Pos   (10U)
     
    #define CAN_F11R1_FB10_Msk   (0x1UL << CAN_F11R1_FB10_Pos)
     
    #define CAN_F11R1_FB10   CAN_F11R1_FB10_Msk
     
    #define CAN_F11R1_FB11_Pos   (11U)
     
    #define CAN_F11R1_FB11_Msk   (0x1UL << CAN_F11R1_FB11_Pos)
     
    #define CAN_F11R1_FB11   CAN_F11R1_FB11_Msk
     
    #define CAN_F11R1_FB12_Pos   (12U)
     
    #define CAN_F11R1_FB12_Msk   (0x1UL << CAN_F11R1_FB12_Pos)
     
    #define CAN_F11R1_FB12   CAN_F11R1_FB12_Msk
     
    #define CAN_F11R1_FB13_Pos   (13U)
     
    #define CAN_F11R1_FB13_Msk   (0x1UL << CAN_F11R1_FB13_Pos)
     
    #define CAN_F11R1_FB13   CAN_F11R1_FB13_Msk
     
    #define CAN_F11R1_FB14_Pos   (14U)
     
    #define CAN_F11R1_FB14_Msk   (0x1UL << CAN_F11R1_FB14_Pos)
     
    #define CAN_F11R1_FB14   CAN_F11R1_FB14_Msk
     
    #define CAN_F11R1_FB15_Pos   (15U)
     
    #define CAN_F11R1_FB15_Msk   (0x1UL << CAN_F11R1_FB15_Pos)
     
    #define CAN_F11R1_FB15   CAN_F11R1_FB15_Msk
     
    #define CAN_F11R1_FB16_Pos   (16U)
     
    #define CAN_F11R1_FB16_Msk   (0x1UL << CAN_F11R1_FB16_Pos)
     
    #define CAN_F11R1_FB16   CAN_F11R1_FB16_Msk
     
    #define CAN_F11R1_FB17_Pos   (17U)
     
    #define CAN_F11R1_FB17_Msk   (0x1UL << CAN_F11R1_FB17_Pos)
     
    #define CAN_F11R1_FB17   CAN_F11R1_FB17_Msk
     
    #define CAN_F11R1_FB18_Pos   (18U)
     
    #define CAN_F11R1_FB18_Msk   (0x1UL << CAN_F11R1_FB18_Pos)
     
    #define CAN_F11R1_FB18   CAN_F11R1_FB18_Msk
     
    #define CAN_F11R1_FB19_Pos   (19U)
     
    #define CAN_F11R1_FB19_Msk   (0x1UL << CAN_F11R1_FB19_Pos)
     
    #define CAN_F11R1_FB19   CAN_F11R1_FB19_Msk
     
    #define CAN_F11R1_FB20_Pos   (20U)
     
    #define CAN_F11R1_FB20_Msk   (0x1UL << CAN_F11R1_FB20_Pos)
     
    #define CAN_F11R1_FB20   CAN_F11R1_FB20_Msk
     
    #define CAN_F11R1_FB21_Pos   (21U)
     
    #define CAN_F11R1_FB21_Msk   (0x1UL << CAN_F11R1_FB21_Pos)
     
    #define CAN_F11R1_FB21   CAN_F11R1_FB21_Msk
     
    #define CAN_F11R1_FB22_Pos   (22U)
     
    #define CAN_F11R1_FB22_Msk   (0x1UL << CAN_F11R1_FB22_Pos)
     
    #define CAN_F11R1_FB22   CAN_F11R1_FB22_Msk
     
    #define CAN_F11R1_FB23_Pos   (23U)
     
    #define CAN_F11R1_FB23_Msk   (0x1UL << CAN_F11R1_FB23_Pos)
     
    #define CAN_F11R1_FB23   CAN_F11R1_FB23_Msk
     
    #define CAN_F11R1_FB24_Pos   (24U)
     
    #define CAN_F11R1_FB24_Msk   (0x1UL << CAN_F11R1_FB24_Pos)
     
    #define CAN_F11R1_FB24   CAN_F11R1_FB24_Msk
     
    #define CAN_F11R1_FB25_Pos   (25U)
     
    #define CAN_F11R1_FB25_Msk   (0x1UL << CAN_F11R1_FB25_Pos)
     
    #define CAN_F11R1_FB25   CAN_F11R1_FB25_Msk
     
    #define CAN_F11R1_FB26_Pos   (26U)
     
    #define CAN_F11R1_FB26_Msk   (0x1UL << CAN_F11R1_FB26_Pos)
     
    #define CAN_F11R1_FB26   CAN_F11R1_FB26_Msk
     
    #define CAN_F11R1_FB27_Pos   (27U)
     
    #define CAN_F11R1_FB27_Msk   (0x1UL << CAN_F11R1_FB27_Pos)
     
    #define CAN_F11R1_FB27   CAN_F11R1_FB27_Msk
     
    #define CAN_F11R1_FB28_Pos   (28U)
     
    #define CAN_F11R1_FB28_Msk   (0x1UL << CAN_F11R1_FB28_Pos)
     
    #define CAN_F11R1_FB28   CAN_F11R1_FB28_Msk
     
    #define CAN_F11R1_FB29_Pos   (29U)
     
    #define CAN_F11R1_FB29_Msk   (0x1UL << CAN_F11R1_FB29_Pos)
     
    #define CAN_F11R1_FB29   CAN_F11R1_FB29_Msk
     
    #define CAN_F11R1_FB30_Pos   (30U)
     
    #define CAN_F11R1_FB30_Msk   (0x1UL << CAN_F11R1_FB30_Pos)
     
    #define CAN_F11R1_FB30   CAN_F11R1_FB30_Msk
     
    #define CAN_F11R1_FB31_Pos   (31U)
     
    #define CAN_F11R1_FB31_Msk   (0x1UL << CAN_F11R1_FB31_Pos)
     
    #define CAN_F11R1_FB31   CAN_F11R1_FB31_Msk
     
    #define CAN_F12R1_FB0_Pos   (0U)
     
    #define CAN_F12R1_FB0_Msk   (0x1UL << CAN_F12R1_FB0_Pos)
     
    #define CAN_F12R1_FB0   CAN_F12R1_FB0_Msk
     
    #define CAN_F12R1_FB1_Pos   (1U)
     
    #define CAN_F12R1_FB1_Msk   (0x1UL << CAN_F12R1_FB1_Pos)
     
    #define CAN_F12R1_FB1   CAN_F12R1_FB1_Msk
     
    #define CAN_F12R1_FB2_Pos   (2U)
     
    #define CAN_F12R1_FB2_Msk   (0x1UL << CAN_F12R1_FB2_Pos)
     
    #define CAN_F12R1_FB2   CAN_F12R1_FB2_Msk
     
    #define CAN_F12R1_FB3_Pos   (3U)
     
    #define CAN_F12R1_FB3_Msk   (0x1UL << CAN_F12R1_FB3_Pos)
     
    #define CAN_F12R1_FB3   CAN_F12R1_FB3_Msk
     
    #define CAN_F12R1_FB4_Pos   (4U)
     
    #define CAN_F12R1_FB4_Msk   (0x1UL << CAN_F12R1_FB4_Pos)
     
    #define CAN_F12R1_FB4   CAN_F12R1_FB4_Msk
     
    #define CAN_F12R1_FB5_Pos   (5U)
     
    #define CAN_F12R1_FB5_Msk   (0x1UL << CAN_F12R1_FB5_Pos)
     
    #define CAN_F12R1_FB5   CAN_F12R1_FB5_Msk
     
    #define CAN_F12R1_FB6_Pos   (6U)
     
    #define CAN_F12R1_FB6_Msk   (0x1UL << CAN_F12R1_FB6_Pos)
     
    #define CAN_F12R1_FB6   CAN_F12R1_FB6_Msk
     
    #define CAN_F12R1_FB7_Pos   (7U)
     
    #define CAN_F12R1_FB7_Msk   (0x1UL << CAN_F12R1_FB7_Pos)
     
    #define CAN_F12R1_FB7   CAN_F12R1_FB7_Msk
     
    #define CAN_F12R1_FB8_Pos   (8U)
     
    #define CAN_F12R1_FB8_Msk   (0x1UL << CAN_F12R1_FB8_Pos)
     
    #define CAN_F12R1_FB8   CAN_F12R1_FB8_Msk
     
    #define CAN_F12R1_FB9_Pos   (9U)
     
    #define CAN_F12R1_FB9_Msk   (0x1UL << CAN_F12R1_FB9_Pos)
     
    #define CAN_F12R1_FB9   CAN_F12R1_FB9_Msk
     
    #define CAN_F12R1_FB10_Pos   (10U)
     
    #define CAN_F12R1_FB10_Msk   (0x1UL << CAN_F12R1_FB10_Pos)
     
    #define CAN_F12R1_FB10   CAN_F12R1_FB10_Msk
     
    #define CAN_F12R1_FB11_Pos   (11U)
     
    #define CAN_F12R1_FB11_Msk   (0x1UL << CAN_F12R1_FB11_Pos)
     
    #define CAN_F12R1_FB11   CAN_F12R1_FB11_Msk
     
    #define CAN_F12R1_FB12_Pos   (12U)
     
    #define CAN_F12R1_FB12_Msk   (0x1UL << CAN_F12R1_FB12_Pos)
     
    #define CAN_F12R1_FB12   CAN_F12R1_FB12_Msk
     
    #define CAN_F12R1_FB13_Pos   (13U)
     
    #define CAN_F12R1_FB13_Msk   (0x1UL << CAN_F12R1_FB13_Pos)
     
    #define CAN_F12R1_FB13   CAN_F12R1_FB13_Msk
     
    #define CAN_F12R1_FB14_Pos   (14U)
     
    #define CAN_F12R1_FB14_Msk   (0x1UL << CAN_F12R1_FB14_Pos)
     
    #define CAN_F12R1_FB14   CAN_F12R1_FB14_Msk
     
    #define CAN_F12R1_FB15_Pos   (15U)
     
    #define CAN_F12R1_FB15_Msk   (0x1UL << CAN_F12R1_FB15_Pos)
     
    #define CAN_F12R1_FB15   CAN_F12R1_FB15_Msk
     
    #define CAN_F12R1_FB16_Pos   (16U)
     
    #define CAN_F12R1_FB16_Msk   (0x1UL << CAN_F12R1_FB16_Pos)
     
    #define CAN_F12R1_FB16   CAN_F12R1_FB16_Msk
     
    #define CAN_F12R1_FB17_Pos   (17U)
     
    #define CAN_F12R1_FB17_Msk   (0x1UL << CAN_F12R1_FB17_Pos)
     
    #define CAN_F12R1_FB17   CAN_F12R1_FB17_Msk
     
    #define CAN_F12R1_FB18_Pos   (18U)
     
    #define CAN_F12R1_FB18_Msk   (0x1UL << CAN_F12R1_FB18_Pos)
     
    #define CAN_F12R1_FB18   CAN_F12R1_FB18_Msk
     
    #define CAN_F12R1_FB19_Pos   (19U)
     
    #define CAN_F12R1_FB19_Msk   (0x1UL << CAN_F12R1_FB19_Pos)
     
    #define CAN_F12R1_FB19   CAN_F12R1_FB19_Msk
     
    #define CAN_F12R1_FB20_Pos   (20U)
     
    #define CAN_F12R1_FB20_Msk   (0x1UL << CAN_F12R1_FB20_Pos)
     
    #define CAN_F12R1_FB20   CAN_F12R1_FB20_Msk
     
    #define CAN_F12R1_FB21_Pos   (21U)
     
    #define CAN_F12R1_FB21_Msk   (0x1UL << CAN_F12R1_FB21_Pos)
     
    #define CAN_F12R1_FB21   CAN_F12R1_FB21_Msk
     
    #define CAN_F12R1_FB22_Pos   (22U)
     
    #define CAN_F12R1_FB22_Msk   (0x1UL << CAN_F12R1_FB22_Pos)
     
    #define CAN_F12R1_FB22   CAN_F12R1_FB22_Msk
     
    #define CAN_F12R1_FB23_Pos   (23U)
     
    #define CAN_F12R1_FB23_Msk   (0x1UL << CAN_F12R1_FB23_Pos)
     
    #define CAN_F12R1_FB23   CAN_F12R1_FB23_Msk
     
    #define CAN_F12R1_FB24_Pos   (24U)
     
    #define CAN_F12R1_FB24_Msk   (0x1UL << CAN_F12R1_FB24_Pos)
     
    #define CAN_F12R1_FB24   CAN_F12R1_FB24_Msk
     
    #define CAN_F12R1_FB25_Pos   (25U)
     
    #define CAN_F12R1_FB25_Msk   (0x1UL << CAN_F12R1_FB25_Pos)
     
    #define CAN_F12R1_FB25   CAN_F12R1_FB25_Msk
     
    #define CAN_F12R1_FB26_Pos   (26U)
     
    #define CAN_F12R1_FB26_Msk   (0x1UL << CAN_F12R1_FB26_Pos)
     
    #define CAN_F12R1_FB26   CAN_F12R1_FB26_Msk
     
    #define CAN_F12R1_FB27_Pos   (27U)
     
    #define CAN_F12R1_FB27_Msk   (0x1UL << CAN_F12R1_FB27_Pos)
     
    #define CAN_F12R1_FB27   CAN_F12R1_FB27_Msk
     
    #define CAN_F12R1_FB28_Pos   (28U)
     
    #define CAN_F12R1_FB28_Msk   (0x1UL << CAN_F12R1_FB28_Pos)
     
    #define CAN_F12R1_FB28   CAN_F12R1_FB28_Msk
     
    #define CAN_F12R1_FB29_Pos   (29U)
     
    #define CAN_F12R1_FB29_Msk   (0x1UL << CAN_F12R1_FB29_Pos)
     
    #define CAN_F12R1_FB29   CAN_F12R1_FB29_Msk
     
    #define CAN_F12R1_FB30_Pos   (30U)
     
    #define CAN_F12R1_FB30_Msk   (0x1UL << CAN_F12R1_FB30_Pos)
     
    #define CAN_F12R1_FB30   CAN_F12R1_FB30_Msk
     
    #define CAN_F12R1_FB31_Pos   (31U)
     
    #define CAN_F12R1_FB31_Msk   (0x1UL << CAN_F12R1_FB31_Pos)
     
    #define CAN_F12R1_FB31   CAN_F12R1_FB31_Msk
     
    #define CAN_F13R1_FB0_Pos   (0U)
     
    #define CAN_F13R1_FB0_Msk   (0x1UL << CAN_F13R1_FB0_Pos)
     
    #define CAN_F13R1_FB0   CAN_F13R1_FB0_Msk
     
    #define CAN_F13R1_FB1_Pos   (1U)
     
    #define CAN_F13R1_FB1_Msk   (0x1UL << CAN_F13R1_FB1_Pos)
     
    #define CAN_F13R1_FB1   CAN_F13R1_FB1_Msk
     
    #define CAN_F13R1_FB2_Pos   (2U)
     
    #define CAN_F13R1_FB2_Msk   (0x1UL << CAN_F13R1_FB2_Pos)
     
    #define CAN_F13R1_FB2   CAN_F13R1_FB2_Msk
     
    #define CAN_F13R1_FB3_Pos   (3U)
     
    #define CAN_F13R1_FB3_Msk   (0x1UL << CAN_F13R1_FB3_Pos)
     
    #define CAN_F13R1_FB3   CAN_F13R1_FB3_Msk
     
    #define CAN_F13R1_FB4_Pos   (4U)
     
    #define CAN_F13R1_FB4_Msk   (0x1UL << CAN_F13R1_FB4_Pos)
     
    #define CAN_F13R1_FB4   CAN_F13R1_FB4_Msk
     
    #define CAN_F13R1_FB5_Pos   (5U)
     
    #define CAN_F13R1_FB5_Msk   (0x1UL << CAN_F13R1_FB5_Pos)
     
    #define CAN_F13R1_FB5   CAN_F13R1_FB5_Msk
     
    #define CAN_F13R1_FB6_Pos   (6U)
     
    #define CAN_F13R1_FB6_Msk   (0x1UL << CAN_F13R1_FB6_Pos)
     
    #define CAN_F13R1_FB6   CAN_F13R1_FB6_Msk
     
    #define CAN_F13R1_FB7_Pos   (7U)
     
    #define CAN_F13R1_FB7_Msk   (0x1UL << CAN_F13R1_FB7_Pos)
     
    #define CAN_F13R1_FB7   CAN_F13R1_FB7_Msk
     
    #define CAN_F13R1_FB8_Pos   (8U)
     
    #define CAN_F13R1_FB8_Msk   (0x1UL << CAN_F13R1_FB8_Pos)
     
    #define CAN_F13R1_FB8   CAN_F13R1_FB8_Msk
     
    #define CAN_F13R1_FB9_Pos   (9U)
     
    #define CAN_F13R1_FB9_Msk   (0x1UL << CAN_F13R1_FB9_Pos)
     
    #define CAN_F13R1_FB9   CAN_F13R1_FB9_Msk
     
    #define CAN_F13R1_FB10_Pos   (10U)
     
    #define CAN_F13R1_FB10_Msk   (0x1UL << CAN_F13R1_FB10_Pos)
     
    #define CAN_F13R1_FB10   CAN_F13R1_FB10_Msk
     
    #define CAN_F13R1_FB11_Pos   (11U)
     
    #define CAN_F13R1_FB11_Msk   (0x1UL << CAN_F13R1_FB11_Pos)
     
    #define CAN_F13R1_FB11   CAN_F13R1_FB11_Msk
     
    #define CAN_F13R1_FB12_Pos   (12U)
     
    #define CAN_F13R1_FB12_Msk   (0x1UL << CAN_F13R1_FB12_Pos)
     
    #define CAN_F13R1_FB12   CAN_F13R1_FB12_Msk
     
    #define CAN_F13R1_FB13_Pos   (13U)
     
    #define CAN_F13R1_FB13_Msk   (0x1UL << CAN_F13R1_FB13_Pos)
     
    #define CAN_F13R1_FB13   CAN_F13R1_FB13_Msk
     
    #define CAN_F13R1_FB14_Pos   (14U)
     
    #define CAN_F13R1_FB14_Msk   (0x1UL << CAN_F13R1_FB14_Pos)
     
    #define CAN_F13R1_FB14   CAN_F13R1_FB14_Msk
     
    #define CAN_F13R1_FB15_Pos   (15U)
     
    #define CAN_F13R1_FB15_Msk   (0x1UL << CAN_F13R1_FB15_Pos)
     
    #define CAN_F13R1_FB15   CAN_F13R1_FB15_Msk
     
    #define CAN_F13R1_FB16_Pos   (16U)
     
    #define CAN_F13R1_FB16_Msk   (0x1UL << CAN_F13R1_FB16_Pos)
     
    #define CAN_F13R1_FB16   CAN_F13R1_FB16_Msk
     
    #define CAN_F13R1_FB17_Pos   (17U)
     
    #define CAN_F13R1_FB17_Msk   (0x1UL << CAN_F13R1_FB17_Pos)
     
    #define CAN_F13R1_FB17   CAN_F13R1_FB17_Msk
     
    #define CAN_F13R1_FB18_Pos   (18U)
     
    #define CAN_F13R1_FB18_Msk   (0x1UL << CAN_F13R1_FB18_Pos)
     
    #define CAN_F13R1_FB18   CAN_F13R1_FB18_Msk
     
    #define CAN_F13R1_FB19_Pos   (19U)
     
    #define CAN_F13R1_FB19_Msk   (0x1UL << CAN_F13R1_FB19_Pos)
     
    #define CAN_F13R1_FB19   CAN_F13R1_FB19_Msk
     
    #define CAN_F13R1_FB20_Pos   (20U)
     
    #define CAN_F13R1_FB20_Msk   (0x1UL << CAN_F13R1_FB20_Pos)
     
    #define CAN_F13R1_FB20   CAN_F13R1_FB20_Msk
     
    #define CAN_F13R1_FB21_Pos   (21U)
     
    #define CAN_F13R1_FB21_Msk   (0x1UL << CAN_F13R1_FB21_Pos)
     
    #define CAN_F13R1_FB21   CAN_F13R1_FB21_Msk
     
    #define CAN_F13R1_FB22_Pos   (22U)
     
    #define CAN_F13R1_FB22_Msk   (0x1UL << CAN_F13R1_FB22_Pos)
     
    #define CAN_F13R1_FB22   CAN_F13R1_FB22_Msk
     
    #define CAN_F13R1_FB23_Pos   (23U)
     
    #define CAN_F13R1_FB23_Msk   (0x1UL << CAN_F13R1_FB23_Pos)
     
    #define CAN_F13R1_FB23   CAN_F13R1_FB23_Msk
     
    #define CAN_F13R1_FB24_Pos   (24U)
     
    #define CAN_F13R1_FB24_Msk   (0x1UL << CAN_F13R1_FB24_Pos)
     
    #define CAN_F13R1_FB24   CAN_F13R1_FB24_Msk
     
    #define CAN_F13R1_FB25_Pos   (25U)
     
    #define CAN_F13R1_FB25_Msk   (0x1UL << CAN_F13R1_FB25_Pos)
     
    #define CAN_F13R1_FB25   CAN_F13R1_FB25_Msk
     
    #define CAN_F13R1_FB26_Pos   (26U)
     
    #define CAN_F13R1_FB26_Msk   (0x1UL << CAN_F13R1_FB26_Pos)
     
    #define CAN_F13R1_FB26   CAN_F13R1_FB26_Msk
     
    #define CAN_F13R1_FB27_Pos   (27U)
     
    #define CAN_F13R1_FB27_Msk   (0x1UL << CAN_F13R1_FB27_Pos)
     
    #define CAN_F13R1_FB27   CAN_F13R1_FB27_Msk
     
    #define CAN_F13R1_FB28_Pos   (28U)
     
    #define CAN_F13R1_FB28_Msk   (0x1UL << CAN_F13R1_FB28_Pos)
     
    #define CAN_F13R1_FB28   CAN_F13R1_FB28_Msk
     
    #define CAN_F13R1_FB29_Pos   (29U)
     
    #define CAN_F13R1_FB29_Msk   (0x1UL << CAN_F13R1_FB29_Pos)
     
    #define CAN_F13R1_FB29   CAN_F13R1_FB29_Msk
     
    #define CAN_F13R1_FB30_Pos   (30U)
     
    #define CAN_F13R1_FB30_Msk   (0x1UL << CAN_F13R1_FB30_Pos)
     
    #define CAN_F13R1_FB30   CAN_F13R1_FB30_Msk
     
    #define CAN_F13R1_FB31_Pos   (31U)
     
    #define CAN_F13R1_FB31_Msk   (0x1UL << CAN_F13R1_FB31_Pos)
     
    #define CAN_F13R1_FB31   CAN_F13R1_FB31_Msk
     
    #define CAN_F0R2_FB0_Pos   (0U)
     
    #define CAN_F0R2_FB0_Msk   (0x1UL << CAN_F0R2_FB0_Pos)
     
    #define CAN_F0R2_FB0   CAN_F0R2_FB0_Msk
     
    #define CAN_F0R2_FB1_Pos   (1U)
     
    #define CAN_F0R2_FB1_Msk   (0x1UL << CAN_F0R2_FB1_Pos)
     
    #define CAN_F0R2_FB1   CAN_F0R2_FB1_Msk
     
    #define CAN_F0R2_FB2_Pos   (2U)
     
    #define CAN_F0R2_FB2_Msk   (0x1UL << CAN_F0R2_FB2_Pos)
     
    #define CAN_F0R2_FB2   CAN_F0R2_FB2_Msk
     
    #define CAN_F0R2_FB3_Pos   (3U)
     
    #define CAN_F0R2_FB3_Msk   (0x1UL << CAN_F0R2_FB3_Pos)
     
    #define CAN_F0R2_FB3   CAN_F0R2_FB3_Msk
     
    #define CAN_F0R2_FB4_Pos   (4U)
     
    #define CAN_F0R2_FB4_Msk   (0x1UL << CAN_F0R2_FB4_Pos)
     
    #define CAN_F0R2_FB4   CAN_F0R2_FB4_Msk
     
    #define CAN_F0R2_FB5_Pos   (5U)
     
    #define CAN_F0R2_FB5_Msk   (0x1UL << CAN_F0R2_FB5_Pos)
     
    #define CAN_F0R2_FB5   CAN_F0R2_FB5_Msk
     
    #define CAN_F0R2_FB6_Pos   (6U)
     
    #define CAN_F0R2_FB6_Msk   (0x1UL << CAN_F0R2_FB6_Pos)
     
    #define CAN_F0R2_FB6   CAN_F0R2_FB6_Msk
     
    #define CAN_F0R2_FB7_Pos   (7U)
     
    #define CAN_F0R2_FB7_Msk   (0x1UL << CAN_F0R2_FB7_Pos)
     
    #define CAN_F0R2_FB7   CAN_F0R2_FB7_Msk
     
    #define CAN_F0R2_FB8_Pos   (8U)
     
    #define CAN_F0R2_FB8_Msk   (0x1UL << CAN_F0R2_FB8_Pos)
     
    #define CAN_F0R2_FB8   CAN_F0R2_FB8_Msk
     
    #define CAN_F0R2_FB9_Pos   (9U)
     
    #define CAN_F0R2_FB9_Msk   (0x1UL << CAN_F0R2_FB9_Pos)
     
    #define CAN_F0R2_FB9   CAN_F0R2_FB9_Msk
     
    #define CAN_F0R2_FB10_Pos   (10U)
     
    #define CAN_F0R2_FB10_Msk   (0x1UL << CAN_F0R2_FB10_Pos)
     
    #define CAN_F0R2_FB10   CAN_F0R2_FB10_Msk
     
    #define CAN_F0R2_FB11_Pos   (11U)
     
    #define CAN_F0R2_FB11_Msk   (0x1UL << CAN_F0R2_FB11_Pos)
     
    #define CAN_F0R2_FB11   CAN_F0R2_FB11_Msk
     
    #define CAN_F0R2_FB12_Pos   (12U)
     
    #define CAN_F0R2_FB12_Msk   (0x1UL << CAN_F0R2_FB12_Pos)
     
    #define CAN_F0R2_FB12   CAN_F0R2_FB12_Msk
     
    #define CAN_F0R2_FB13_Pos   (13U)
     
    #define CAN_F0R2_FB13_Msk   (0x1UL << CAN_F0R2_FB13_Pos)
     
    #define CAN_F0R2_FB13   CAN_F0R2_FB13_Msk
     
    #define CAN_F0R2_FB14_Pos   (14U)
     
    #define CAN_F0R2_FB14_Msk   (0x1UL << CAN_F0R2_FB14_Pos)
     
    #define CAN_F0R2_FB14   CAN_F0R2_FB14_Msk
     
    #define CAN_F0R2_FB15_Pos   (15U)
     
    #define CAN_F0R2_FB15_Msk   (0x1UL << CAN_F0R2_FB15_Pos)
     
    #define CAN_F0R2_FB15   CAN_F0R2_FB15_Msk
     
    #define CAN_F0R2_FB16_Pos   (16U)
     
    #define CAN_F0R2_FB16_Msk   (0x1UL << CAN_F0R2_FB16_Pos)
     
    #define CAN_F0R2_FB16   CAN_F0R2_FB16_Msk
     
    #define CAN_F0R2_FB17_Pos   (17U)
     
    #define CAN_F0R2_FB17_Msk   (0x1UL << CAN_F0R2_FB17_Pos)
     
    #define CAN_F0R2_FB17   CAN_F0R2_FB17_Msk
     
    #define CAN_F0R2_FB18_Pos   (18U)
     
    #define CAN_F0R2_FB18_Msk   (0x1UL << CAN_F0R2_FB18_Pos)
     
    #define CAN_F0R2_FB18   CAN_F0R2_FB18_Msk
     
    #define CAN_F0R2_FB19_Pos   (19U)
     
    #define CAN_F0R2_FB19_Msk   (0x1UL << CAN_F0R2_FB19_Pos)
     
    #define CAN_F0R2_FB19   CAN_F0R2_FB19_Msk
     
    #define CAN_F0R2_FB20_Pos   (20U)
     
    #define CAN_F0R2_FB20_Msk   (0x1UL << CAN_F0R2_FB20_Pos)
     
    #define CAN_F0R2_FB20   CAN_F0R2_FB20_Msk
     
    #define CAN_F0R2_FB21_Pos   (21U)
     
    #define CAN_F0R2_FB21_Msk   (0x1UL << CAN_F0R2_FB21_Pos)
     
    #define CAN_F0R2_FB21   CAN_F0R2_FB21_Msk
     
    #define CAN_F0R2_FB22_Pos   (22U)
     
    #define CAN_F0R2_FB22_Msk   (0x1UL << CAN_F0R2_FB22_Pos)
     
    #define CAN_F0R2_FB22   CAN_F0R2_FB22_Msk
     
    #define CAN_F0R2_FB23_Pos   (23U)
     
    #define CAN_F0R2_FB23_Msk   (0x1UL << CAN_F0R2_FB23_Pos)
     
    #define CAN_F0R2_FB23   CAN_F0R2_FB23_Msk
     
    #define CAN_F0R2_FB24_Pos   (24U)
     
    #define CAN_F0R2_FB24_Msk   (0x1UL << CAN_F0R2_FB24_Pos)
     
    #define CAN_F0R2_FB24   CAN_F0R2_FB24_Msk
     
    #define CAN_F0R2_FB25_Pos   (25U)
     
    #define CAN_F0R2_FB25_Msk   (0x1UL << CAN_F0R2_FB25_Pos)
     
    #define CAN_F0R2_FB25   CAN_F0R2_FB25_Msk
     
    #define CAN_F0R2_FB26_Pos   (26U)
     
    #define CAN_F0R2_FB26_Msk   (0x1UL << CAN_F0R2_FB26_Pos)
     
    #define CAN_F0R2_FB26   CAN_F0R2_FB26_Msk
     
    #define CAN_F0R2_FB27_Pos   (27U)
     
    #define CAN_F0R2_FB27_Msk   (0x1UL << CAN_F0R2_FB27_Pos)
     
    #define CAN_F0R2_FB27   CAN_F0R2_FB27_Msk
     
    #define CAN_F0R2_FB28_Pos   (28U)
     
    #define CAN_F0R2_FB28_Msk   (0x1UL << CAN_F0R2_FB28_Pos)
     
    #define CAN_F0R2_FB28   CAN_F0R2_FB28_Msk
     
    #define CAN_F0R2_FB29_Pos   (29U)
     
    #define CAN_F0R2_FB29_Msk   (0x1UL << CAN_F0R2_FB29_Pos)
     
    #define CAN_F0R2_FB29   CAN_F0R2_FB29_Msk
     
    #define CAN_F0R2_FB30_Pos   (30U)
     
    #define CAN_F0R2_FB30_Msk   (0x1UL << CAN_F0R2_FB30_Pos)
     
    #define CAN_F0R2_FB30   CAN_F0R2_FB30_Msk
     
    #define CAN_F0R2_FB31_Pos   (31U)
     
    #define CAN_F0R2_FB31_Msk   (0x1UL << CAN_F0R2_FB31_Pos)
     
    #define CAN_F0R2_FB31   CAN_F0R2_FB31_Msk
     
    #define CAN_F1R2_FB0_Pos   (0U)
     
    #define CAN_F1R2_FB0_Msk   (0x1UL << CAN_F1R2_FB0_Pos)
     
    #define CAN_F1R2_FB0   CAN_F1R2_FB0_Msk
     
    #define CAN_F1R2_FB1_Pos   (1U)
     
    #define CAN_F1R2_FB1_Msk   (0x1UL << CAN_F1R2_FB1_Pos)
     
    #define CAN_F1R2_FB1   CAN_F1R2_FB1_Msk
     
    #define CAN_F1R2_FB2_Pos   (2U)
     
    #define CAN_F1R2_FB2_Msk   (0x1UL << CAN_F1R2_FB2_Pos)
     
    #define CAN_F1R2_FB2   CAN_F1R2_FB2_Msk
     
    #define CAN_F1R2_FB3_Pos   (3U)
     
    #define CAN_F1R2_FB3_Msk   (0x1UL << CAN_F1R2_FB3_Pos)
     
    #define CAN_F1R2_FB3   CAN_F1R2_FB3_Msk
     
    #define CAN_F1R2_FB4_Pos   (4U)
     
    #define CAN_F1R2_FB4_Msk   (0x1UL << CAN_F1R2_FB4_Pos)
     
    #define CAN_F1R2_FB4   CAN_F1R2_FB4_Msk
     
    #define CAN_F1R2_FB5_Pos   (5U)
     
    #define CAN_F1R2_FB5_Msk   (0x1UL << CAN_F1R2_FB5_Pos)
     
    #define CAN_F1R2_FB5   CAN_F1R2_FB5_Msk
     
    #define CAN_F1R2_FB6_Pos   (6U)
     
    #define CAN_F1R2_FB6_Msk   (0x1UL << CAN_F1R2_FB6_Pos)
     
    #define CAN_F1R2_FB6   CAN_F1R2_FB6_Msk
     
    #define CAN_F1R2_FB7_Pos   (7U)
     
    #define CAN_F1R2_FB7_Msk   (0x1UL << CAN_F1R2_FB7_Pos)
     
    #define CAN_F1R2_FB7   CAN_F1R2_FB7_Msk
     
    #define CAN_F1R2_FB8_Pos   (8U)
     
    #define CAN_F1R2_FB8_Msk   (0x1UL << CAN_F1R2_FB8_Pos)
     
    #define CAN_F1R2_FB8   CAN_F1R2_FB8_Msk
     
    #define CAN_F1R2_FB9_Pos   (9U)
     
    #define CAN_F1R2_FB9_Msk   (0x1UL << CAN_F1R2_FB9_Pos)
     
    #define CAN_F1R2_FB9   CAN_F1R2_FB9_Msk
     
    #define CAN_F1R2_FB10_Pos   (10U)
     
    #define CAN_F1R2_FB10_Msk   (0x1UL << CAN_F1R2_FB10_Pos)
     
    #define CAN_F1R2_FB10   CAN_F1R2_FB10_Msk
     
    #define CAN_F1R2_FB11_Pos   (11U)
     
    #define CAN_F1R2_FB11_Msk   (0x1UL << CAN_F1R2_FB11_Pos)
     
    #define CAN_F1R2_FB11   CAN_F1R2_FB11_Msk
     
    #define CAN_F1R2_FB12_Pos   (12U)
     
    #define CAN_F1R2_FB12_Msk   (0x1UL << CAN_F1R2_FB12_Pos)
     
    #define CAN_F1R2_FB12   CAN_F1R2_FB12_Msk
     
    #define CAN_F1R2_FB13_Pos   (13U)
     
    #define CAN_F1R2_FB13_Msk   (0x1UL << CAN_F1R2_FB13_Pos)
     
    #define CAN_F1R2_FB13   CAN_F1R2_FB13_Msk
     
    #define CAN_F1R2_FB14_Pos   (14U)
     
    #define CAN_F1R2_FB14_Msk   (0x1UL << CAN_F1R2_FB14_Pos)
     
    #define CAN_F1R2_FB14   CAN_F1R2_FB14_Msk
     
    #define CAN_F1R2_FB15_Pos   (15U)
     
    #define CAN_F1R2_FB15_Msk   (0x1UL << CAN_F1R2_FB15_Pos)
     
    #define CAN_F1R2_FB15   CAN_F1R2_FB15_Msk
     
    #define CAN_F1R2_FB16_Pos   (16U)
     
    #define CAN_F1R2_FB16_Msk   (0x1UL << CAN_F1R2_FB16_Pos)
     
    #define CAN_F1R2_FB16   CAN_F1R2_FB16_Msk
     
    #define CAN_F1R2_FB17_Pos   (17U)
     
    #define CAN_F1R2_FB17_Msk   (0x1UL << CAN_F1R2_FB17_Pos)
     
    #define CAN_F1R2_FB17   CAN_F1R2_FB17_Msk
     
    #define CAN_F1R2_FB18_Pos   (18U)
     
    #define CAN_F1R2_FB18_Msk   (0x1UL << CAN_F1R2_FB18_Pos)
     
    #define CAN_F1R2_FB18   CAN_F1R2_FB18_Msk
     
    #define CAN_F1R2_FB19_Pos   (19U)
     
    #define CAN_F1R2_FB19_Msk   (0x1UL << CAN_F1R2_FB19_Pos)
     
    #define CAN_F1R2_FB19   CAN_F1R2_FB19_Msk
     
    #define CAN_F1R2_FB20_Pos   (20U)
     
    #define CAN_F1R2_FB20_Msk   (0x1UL << CAN_F1R2_FB20_Pos)
     
    #define CAN_F1R2_FB20   CAN_F1R2_FB20_Msk
     
    #define CAN_F1R2_FB21_Pos   (21U)
     
    #define CAN_F1R2_FB21_Msk   (0x1UL << CAN_F1R2_FB21_Pos)
     
    #define CAN_F1R2_FB21   CAN_F1R2_FB21_Msk
     
    #define CAN_F1R2_FB22_Pos   (22U)
     
    #define CAN_F1R2_FB22_Msk   (0x1UL << CAN_F1R2_FB22_Pos)
     
    #define CAN_F1R2_FB22   CAN_F1R2_FB22_Msk
     
    #define CAN_F1R2_FB23_Pos   (23U)
     
    #define CAN_F1R2_FB23_Msk   (0x1UL << CAN_F1R2_FB23_Pos)
     
    #define CAN_F1R2_FB23   CAN_F1R2_FB23_Msk
     
    #define CAN_F1R2_FB24_Pos   (24U)
     
    #define CAN_F1R2_FB24_Msk   (0x1UL << CAN_F1R2_FB24_Pos)
     
    #define CAN_F1R2_FB24   CAN_F1R2_FB24_Msk
     
    #define CAN_F1R2_FB25_Pos   (25U)
     
    #define CAN_F1R2_FB25_Msk   (0x1UL << CAN_F1R2_FB25_Pos)
     
    #define CAN_F1R2_FB25   CAN_F1R2_FB25_Msk
     
    #define CAN_F1R2_FB26_Pos   (26U)
     
    #define CAN_F1R2_FB26_Msk   (0x1UL << CAN_F1R2_FB26_Pos)
     
    #define CAN_F1R2_FB26   CAN_F1R2_FB26_Msk
     
    #define CAN_F1R2_FB27_Pos   (27U)
     
    #define CAN_F1R2_FB27_Msk   (0x1UL << CAN_F1R2_FB27_Pos)
     
    #define CAN_F1R2_FB27   CAN_F1R2_FB27_Msk
     
    #define CAN_F1R2_FB28_Pos   (28U)
     
    #define CAN_F1R2_FB28_Msk   (0x1UL << CAN_F1R2_FB28_Pos)
     
    #define CAN_F1R2_FB28   CAN_F1R2_FB28_Msk
     
    #define CAN_F1R2_FB29_Pos   (29U)
     
    #define CAN_F1R2_FB29_Msk   (0x1UL << CAN_F1R2_FB29_Pos)
     
    #define CAN_F1R2_FB29   CAN_F1R2_FB29_Msk
     
    #define CAN_F1R2_FB30_Pos   (30U)
     
    #define CAN_F1R2_FB30_Msk   (0x1UL << CAN_F1R2_FB30_Pos)
     
    #define CAN_F1R2_FB30   CAN_F1R2_FB30_Msk
     
    #define CAN_F1R2_FB31_Pos   (31U)
     
    #define CAN_F1R2_FB31_Msk   (0x1UL << CAN_F1R2_FB31_Pos)
     
    #define CAN_F1R2_FB31   CAN_F1R2_FB31_Msk
     
    #define CAN_F2R2_FB0_Pos   (0U)
     
    #define CAN_F2R2_FB0_Msk   (0x1UL << CAN_F2R2_FB0_Pos)
     
    #define CAN_F2R2_FB0   CAN_F2R2_FB0_Msk
     
    #define CAN_F2R2_FB1_Pos   (1U)
     
    #define CAN_F2R2_FB1_Msk   (0x1UL << CAN_F2R2_FB1_Pos)
     
    #define CAN_F2R2_FB1   CAN_F2R2_FB1_Msk
     
    #define CAN_F2R2_FB2_Pos   (2U)
     
    #define CAN_F2R2_FB2_Msk   (0x1UL << CAN_F2R2_FB2_Pos)
     
    #define CAN_F2R2_FB2   CAN_F2R2_FB2_Msk
     
    #define CAN_F2R2_FB3_Pos   (3U)
     
    #define CAN_F2R2_FB3_Msk   (0x1UL << CAN_F2R2_FB3_Pos)
     
    #define CAN_F2R2_FB3   CAN_F2R2_FB3_Msk
     
    #define CAN_F2R2_FB4_Pos   (4U)
     
    #define CAN_F2R2_FB4_Msk   (0x1UL << CAN_F2R2_FB4_Pos)
     
    #define CAN_F2R2_FB4   CAN_F2R2_FB4_Msk
     
    #define CAN_F2R2_FB5_Pos   (5U)
     
    #define CAN_F2R2_FB5_Msk   (0x1UL << CAN_F2R2_FB5_Pos)
     
    #define CAN_F2R2_FB5   CAN_F2R2_FB5_Msk
     
    #define CAN_F2R2_FB6_Pos   (6U)
     
    #define CAN_F2R2_FB6_Msk   (0x1UL << CAN_F2R2_FB6_Pos)
     
    #define CAN_F2R2_FB6   CAN_F2R2_FB6_Msk
     
    #define CAN_F2R2_FB7_Pos   (7U)
     
    #define CAN_F2R2_FB7_Msk   (0x1UL << CAN_F2R2_FB7_Pos)
     
    #define CAN_F2R2_FB7   CAN_F2R2_FB7_Msk
     
    #define CAN_F2R2_FB8_Pos   (8U)
     
    #define CAN_F2R2_FB8_Msk   (0x1UL << CAN_F2R2_FB8_Pos)
     
    #define CAN_F2R2_FB8   CAN_F2R2_FB8_Msk
     
    #define CAN_F2R2_FB9_Pos   (9U)
     
    #define CAN_F2R2_FB9_Msk   (0x1UL << CAN_F2R2_FB9_Pos)
     
    #define CAN_F2R2_FB9   CAN_F2R2_FB9_Msk
     
    #define CAN_F2R2_FB10_Pos   (10U)
     
    #define CAN_F2R2_FB10_Msk   (0x1UL << CAN_F2R2_FB10_Pos)
     
    #define CAN_F2R2_FB10   CAN_F2R2_FB10_Msk
     
    #define CAN_F2R2_FB11_Pos   (11U)
     
    #define CAN_F2R2_FB11_Msk   (0x1UL << CAN_F2R2_FB11_Pos)
     
    #define CAN_F2R2_FB11   CAN_F2R2_FB11_Msk
     
    #define CAN_F2R2_FB12_Pos   (12U)
     
    #define CAN_F2R2_FB12_Msk   (0x1UL << CAN_F2R2_FB12_Pos)
     
    #define CAN_F2R2_FB12   CAN_F2R2_FB12_Msk
     
    #define CAN_F2R2_FB13_Pos   (13U)
     
    #define CAN_F2R2_FB13_Msk   (0x1UL << CAN_F2R2_FB13_Pos)
     
    #define CAN_F2R2_FB13   CAN_F2R2_FB13_Msk
     
    #define CAN_F2R2_FB14_Pos   (14U)
     
    #define CAN_F2R2_FB14_Msk   (0x1UL << CAN_F2R2_FB14_Pos)
     
    #define CAN_F2R2_FB14   CAN_F2R2_FB14_Msk
     
    #define CAN_F2R2_FB15_Pos   (15U)
     
    #define CAN_F2R2_FB15_Msk   (0x1UL << CAN_F2R2_FB15_Pos)
     
    #define CAN_F2R2_FB15   CAN_F2R2_FB15_Msk
     
    #define CAN_F2R2_FB16_Pos   (16U)
     
    #define CAN_F2R2_FB16_Msk   (0x1UL << CAN_F2R2_FB16_Pos)
     
    #define CAN_F2R2_FB16   CAN_F2R2_FB16_Msk
     
    #define CAN_F2R2_FB17_Pos   (17U)
     
    #define CAN_F2R2_FB17_Msk   (0x1UL << CAN_F2R2_FB17_Pos)
     
    #define CAN_F2R2_FB17   CAN_F2R2_FB17_Msk
     
    #define CAN_F2R2_FB18_Pos   (18U)
     
    #define CAN_F2R2_FB18_Msk   (0x1UL << CAN_F2R2_FB18_Pos)
     
    #define CAN_F2R2_FB18   CAN_F2R2_FB18_Msk
     
    #define CAN_F2R2_FB19_Pos   (19U)
     
    #define CAN_F2R2_FB19_Msk   (0x1UL << CAN_F2R2_FB19_Pos)
     
    #define CAN_F2R2_FB19   CAN_F2R2_FB19_Msk
     
    #define CAN_F2R2_FB20_Pos   (20U)
     
    #define CAN_F2R2_FB20_Msk   (0x1UL << CAN_F2R2_FB20_Pos)
     
    #define CAN_F2R2_FB20   CAN_F2R2_FB20_Msk
     
    #define CAN_F2R2_FB21_Pos   (21U)
     
    #define CAN_F2R2_FB21_Msk   (0x1UL << CAN_F2R2_FB21_Pos)
     
    #define CAN_F2R2_FB21   CAN_F2R2_FB21_Msk
     
    #define CAN_F2R2_FB22_Pos   (22U)
     
    #define CAN_F2R2_FB22_Msk   (0x1UL << CAN_F2R2_FB22_Pos)
     
    #define CAN_F2R2_FB22   CAN_F2R2_FB22_Msk
     
    #define CAN_F2R2_FB23_Pos   (23U)
     
    #define CAN_F2R2_FB23_Msk   (0x1UL << CAN_F2R2_FB23_Pos)
     
    #define CAN_F2R2_FB23   CAN_F2R2_FB23_Msk
     
    #define CAN_F2R2_FB24_Pos   (24U)
     
    #define CAN_F2R2_FB24_Msk   (0x1UL << CAN_F2R2_FB24_Pos)
     
    #define CAN_F2R2_FB24   CAN_F2R2_FB24_Msk
     
    #define CAN_F2R2_FB25_Pos   (25U)
     
    #define CAN_F2R2_FB25_Msk   (0x1UL << CAN_F2R2_FB25_Pos)
     
    #define CAN_F2R2_FB25   CAN_F2R2_FB25_Msk
     
    #define CAN_F2R2_FB26_Pos   (26U)
     
    #define CAN_F2R2_FB26_Msk   (0x1UL << CAN_F2R2_FB26_Pos)
     
    #define CAN_F2R2_FB26   CAN_F2R2_FB26_Msk
     
    #define CAN_F2R2_FB27_Pos   (27U)
     
    #define CAN_F2R2_FB27_Msk   (0x1UL << CAN_F2R2_FB27_Pos)
     
    #define CAN_F2R2_FB27   CAN_F2R2_FB27_Msk
     
    #define CAN_F2R2_FB28_Pos   (28U)
     
    #define CAN_F2R2_FB28_Msk   (0x1UL << CAN_F2R2_FB28_Pos)
     
    #define CAN_F2R2_FB28   CAN_F2R2_FB28_Msk
     
    #define CAN_F2R2_FB29_Pos   (29U)
     
    #define CAN_F2R2_FB29_Msk   (0x1UL << CAN_F2R2_FB29_Pos)
     
    #define CAN_F2R2_FB29   CAN_F2R2_FB29_Msk
     
    #define CAN_F2R2_FB30_Pos   (30U)
     
    #define CAN_F2R2_FB30_Msk   (0x1UL << CAN_F2R2_FB30_Pos)
     
    #define CAN_F2R2_FB30   CAN_F2R2_FB30_Msk
     
    #define CAN_F2R2_FB31_Pos   (31U)
     
    #define CAN_F2R2_FB31_Msk   (0x1UL << CAN_F2R2_FB31_Pos)
     
    #define CAN_F2R2_FB31   CAN_F2R2_FB31_Msk
     
    #define CAN_F3R2_FB0_Pos   (0U)
     
    #define CAN_F3R2_FB0_Msk   (0x1UL << CAN_F3R2_FB0_Pos)
     
    #define CAN_F3R2_FB0   CAN_F3R2_FB0_Msk
     
    #define CAN_F3R2_FB1_Pos   (1U)
     
    #define CAN_F3R2_FB1_Msk   (0x1UL << CAN_F3R2_FB1_Pos)
     
    #define CAN_F3R2_FB1   CAN_F3R2_FB1_Msk
     
    #define CAN_F3R2_FB2_Pos   (2U)
     
    #define CAN_F3R2_FB2_Msk   (0x1UL << CAN_F3R2_FB2_Pos)
     
    #define CAN_F3R2_FB2   CAN_F3R2_FB2_Msk
     
    #define CAN_F3R2_FB3_Pos   (3U)
     
    #define CAN_F3R2_FB3_Msk   (0x1UL << CAN_F3R2_FB3_Pos)
     
    #define CAN_F3R2_FB3   CAN_F3R2_FB3_Msk
     
    #define CAN_F3R2_FB4_Pos   (4U)
     
    #define CAN_F3R2_FB4_Msk   (0x1UL << CAN_F3R2_FB4_Pos)
     
    #define CAN_F3R2_FB4   CAN_F3R2_FB4_Msk
     
    #define CAN_F3R2_FB5_Pos   (5U)
     
    #define CAN_F3R2_FB5_Msk   (0x1UL << CAN_F3R2_FB5_Pos)
     
    #define CAN_F3R2_FB5   CAN_F3R2_FB5_Msk
     
    #define CAN_F3R2_FB6_Pos   (6U)
     
    #define CAN_F3R2_FB6_Msk   (0x1UL << CAN_F3R2_FB6_Pos)
     
    #define CAN_F3R2_FB6   CAN_F3R2_FB6_Msk
     
    #define CAN_F3R2_FB7_Pos   (7U)
     
    #define CAN_F3R2_FB7_Msk   (0x1UL << CAN_F3R2_FB7_Pos)
     
    #define CAN_F3R2_FB7   CAN_F3R2_FB7_Msk
     
    #define CAN_F3R2_FB8_Pos   (8U)
     
    #define CAN_F3R2_FB8_Msk   (0x1UL << CAN_F3R2_FB8_Pos)
     
    #define CAN_F3R2_FB8   CAN_F3R2_FB8_Msk
     
    #define CAN_F3R2_FB9_Pos   (9U)
     
    #define CAN_F3R2_FB9_Msk   (0x1UL << CAN_F3R2_FB9_Pos)
     
    #define CAN_F3R2_FB9   CAN_F3R2_FB9_Msk
     
    #define CAN_F3R2_FB10_Pos   (10U)
     
    #define CAN_F3R2_FB10_Msk   (0x1UL << CAN_F3R2_FB10_Pos)
     
    #define CAN_F3R2_FB10   CAN_F3R2_FB10_Msk
     
    #define CAN_F3R2_FB11_Pos   (11U)
     
    #define CAN_F3R2_FB11_Msk   (0x1UL << CAN_F3R2_FB11_Pos)
     
    #define CAN_F3R2_FB11   CAN_F3R2_FB11_Msk
     
    #define CAN_F3R2_FB12_Pos   (12U)
     
    #define CAN_F3R2_FB12_Msk   (0x1UL << CAN_F3R2_FB12_Pos)
     
    #define CAN_F3R2_FB12   CAN_F3R2_FB12_Msk
     
    #define CAN_F3R2_FB13_Pos   (13U)
     
    #define CAN_F3R2_FB13_Msk   (0x1UL << CAN_F3R2_FB13_Pos)
     
    #define CAN_F3R2_FB13   CAN_F3R2_FB13_Msk
     
    #define CAN_F3R2_FB14_Pos   (14U)
     
    #define CAN_F3R2_FB14_Msk   (0x1UL << CAN_F3R2_FB14_Pos)
     
    #define CAN_F3R2_FB14   CAN_F3R2_FB14_Msk
     
    #define CAN_F3R2_FB15_Pos   (15U)
     
    #define CAN_F3R2_FB15_Msk   (0x1UL << CAN_F3R2_FB15_Pos)
     
    #define CAN_F3R2_FB15   CAN_F3R2_FB15_Msk
     
    #define CAN_F3R2_FB16_Pos   (16U)
     
    #define CAN_F3R2_FB16_Msk   (0x1UL << CAN_F3R2_FB16_Pos)
     
    #define CAN_F3R2_FB16   CAN_F3R2_FB16_Msk
     
    #define CAN_F3R2_FB17_Pos   (17U)
     
    #define CAN_F3R2_FB17_Msk   (0x1UL << CAN_F3R2_FB17_Pos)
     
    #define CAN_F3R2_FB17   CAN_F3R2_FB17_Msk
     
    #define CAN_F3R2_FB18_Pos   (18U)
     
    #define CAN_F3R2_FB18_Msk   (0x1UL << CAN_F3R2_FB18_Pos)
     
    #define CAN_F3R2_FB18   CAN_F3R2_FB18_Msk
     
    #define CAN_F3R2_FB19_Pos   (19U)
     
    #define CAN_F3R2_FB19_Msk   (0x1UL << CAN_F3R2_FB19_Pos)
     
    #define CAN_F3R2_FB19   CAN_F3R2_FB19_Msk
     
    #define CAN_F3R2_FB20_Pos   (20U)
     
    #define CAN_F3R2_FB20_Msk   (0x1UL << CAN_F3R2_FB20_Pos)
     
    #define CAN_F3R2_FB20   CAN_F3R2_FB20_Msk
     
    #define CAN_F3R2_FB21_Pos   (21U)
     
    #define CAN_F3R2_FB21_Msk   (0x1UL << CAN_F3R2_FB21_Pos)
     
    #define CAN_F3R2_FB21   CAN_F3R2_FB21_Msk
     
    #define CAN_F3R2_FB22_Pos   (22U)
     
    #define CAN_F3R2_FB22_Msk   (0x1UL << CAN_F3R2_FB22_Pos)
     
    #define CAN_F3R2_FB22   CAN_F3R2_FB22_Msk
     
    #define CAN_F3R2_FB23_Pos   (23U)
     
    #define CAN_F3R2_FB23_Msk   (0x1UL << CAN_F3R2_FB23_Pos)
     
    #define CAN_F3R2_FB23   CAN_F3R2_FB23_Msk
     
    #define CAN_F3R2_FB24_Pos   (24U)
     
    #define CAN_F3R2_FB24_Msk   (0x1UL << CAN_F3R2_FB24_Pos)
     
    #define CAN_F3R2_FB24   CAN_F3R2_FB24_Msk
     
    #define CAN_F3R2_FB25_Pos   (25U)
     
    #define CAN_F3R2_FB25_Msk   (0x1UL << CAN_F3R2_FB25_Pos)
     
    #define CAN_F3R2_FB25   CAN_F3R2_FB25_Msk
     
    #define CAN_F3R2_FB26_Pos   (26U)
     
    #define CAN_F3R2_FB26_Msk   (0x1UL << CAN_F3R2_FB26_Pos)
     
    #define CAN_F3R2_FB26   CAN_F3R2_FB26_Msk
     
    #define CAN_F3R2_FB27_Pos   (27U)
     
    #define CAN_F3R2_FB27_Msk   (0x1UL << CAN_F3R2_FB27_Pos)
     
    #define CAN_F3R2_FB27   CAN_F3R2_FB27_Msk
     
    #define CAN_F3R2_FB28_Pos   (28U)
     
    #define CAN_F3R2_FB28_Msk   (0x1UL << CAN_F3R2_FB28_Pos)
     
    #define CAN_F3R2_FB28   CAN_F3R2_FB28_Msk
     
    #define CAN_F3R2_FB29_Pos   (29U)
     
    #define CAN_F3R2_FB29_Msk   (0x1UL << CAN_F3R2_FB29_Pos)
     
    #define CAN_F3R2_FB29   CAN_F3R2_FB29_Msk
     
    #define CAN_F3R2_FB30_Pos   (30U)
     
    #define CAN_F3R2_FB30_Msk   (0x1UL << CAN_F3R2_FB30_Pos)
     
    #define CAN_F3R2_FB30   CAN_F3R2_FB30_Msk
     
    #define CAN_F3R2_FB31_Pos   (31U)
     
    #define CAN_F3R2_FB31_Msk   (0x1UL << CAN_F3R2_FB31_Pos)
     
    #define CAN_F3R2_FB31   CAN_F3R2_FB31_Msk
     
    #define CAN_F4R2_FB0_Pos   (0U)
     
    #define CAN_F4R2_FB0_Msk   (0x1UL << CAN_F4R2_FB0_Pos)
     
    #define CAN_F4R2_FB0   CAN_F4R2_FB0_Msk
     
    #define CAN_F4R2_FB1_Pos   (1U)
     
    #define CAN_F4R2_FB1_Msk   (0x1UL << CAN_F4R2_FB1_Pos)
     
    #define CAN_F4R2_FB1   CAN_F4R2_FB1_Msk
     
    #define CAN_F4R2_FB2_Pos   (2U)
     
    #define CAN_F4R2_FB2_Msk   (0x1UL << CAN_F4R2_FB2_Pos)
     
    #define CAN_F4R2_FB2   CAN_F4R2_FB2_Msk
     
    #define CAN_F4R2_FB3_Pos   (3U)
     
    #define CAN_F4R2_FB3_Msk   (0x1UL << CAN_F4R2_FB3_Pos)
     
    #define CAN_F4R2_FB3   CAN_F4R2_FB3_Msk
     
    #define CAN_F4R2_FB4_Pos   (4U)
     
    #define CAN_F4R2_FB4_Msk   (0x1UL << CAN_F4R2_FB4_Pos)
     
    #define CAN_F4R2_FB4   CAN_F4R2_FB4_Msk
     
    #define CAN_F4R2_FB5_Pos   (5U)
     
    #define CAN_F4R2_FB5_Msk   (0x1UL << CAN_F4R2_FB5_Pos)
     
    #define CAN_F4R2_FB5   CAN_F4R2_FB5_Msk
     
    #define CAN_F4R2_FB6_Pos   (6U)
     
    #define CAN_F4R2_FB6_Msk   (0x1UL << CAN_F4R2_FB6_Pos)
     
    #define CAN_F4R2_FB6   CAN_F4R2_FB6_Msk
     
    #define CAN_F4R2_FB7_Pos   (7U)
     
    #define CAN_F4R2_FB7_Msk   (0x1UL << CAN_F4R2_FB7_Pos)
     
    #define CAN_F4R2_FB7   CAN_F4R2_FB7_Msk
     
    #define CAN_F4R2_FB8_Pos   (8U)
     
    #define CAN_F4R2_FB8_Msk   (0x1UL << CAN_F4R2_FB8_Pos)
     
    #define CAN_F4R2_FB8   CAN_F4R2_FB8_Msk
     
    #define CAN_F4R2_FB9_Pos   (9U)
     
    #define CAN_F4R2_FB9_Msk   (0x1UL << CAN_F4R2_FB9_Pos)
     
    #define CAN_F4R2_FB9   CAN_F4R2_FB9_Msk
     
    #define CAN_F4R2_FB10_Pos   (10U)
     
    #define CAN_F4R2_FB10_Msk   (0x1UL << CAN_F4R2_FB10_Pos)
     
    #define CAN_F4R2_FB10   CAN_F4R2_FB10_Msk
     
    #define CAN_F4R2_FB11_Pos   (11U)
     
    #define CAN_F4R2_FB11_Msk   (0x1UL << CAN_F4R2_FB11_Pos)
     
    #define CAN_F4R2_FB11   CAN_F4R2_FB11_Msk
     
    #define CAN_F4R2_FB12_Pos   (12U)
     
    #define CAN_F4R2_FB12_Msk   (0x1UL << CAN_F4R2_FB12_Pos)
     
    #define CAN_F4R2_FB12   CAN_F4R2_FB12_Msk
     
    #define CAN_F4R2_FB13_Pos   (13U)
     
    #define CAN_F4R2_FB13_Msk   (0x1UL << CAN_F4R2_FB13_Pos)
     
    #define CAN_F4R2_FB13   CAN_F4R2_FB13_Msk
     
    #define CAN_F4R2_FB14_Pos   (14U)
     
    #define CAN_F4R2_FB14_Msk   (0x1UL << CAN_F4R2_FB14_Pos)
     
    #define CAN_F4R2_FB14   CAN_F4R2_FB14_Msk
     
    #define CAN_F4R2_FB15_Pos   (15U)
     
    #define CAN_F4R2_FB15_Msk   (0x1UL << CAN_F4R2_FB15_Pos)
     
    #define CAN_F4R2_FB15   CAN_F4R2_FB15_Msk
     
    #define CAN_F4R2_FB16_Pos   (16U)
     
    #define CAN_F4R2_FB16_Msk   (0x1UL << CAN_F4R2_FB16_Pos)
     
    #define CAN_F4R2_FB16   CAN_F4R2_FB16_Msk
     
    #define CAN_F4R2_FB17_Pos   (17U)
     
    #define CAN_F4R2_FB17_Msk   (0x1UL << CAN_F4R2_FB17_Pos)
     
    #define CAN_F4R2_FB17   CAN_F4R2_FB17_Msk
     
    #define CAN_F4R2_FB18_Pos   (18U)
     
    #define CAN_F4R2_FB18_Msk   (0x1UL << CAN_F4R2_FB18_Pos)
     
    #define CAN_F4R2_FB18   CAN_F4R2_FB18_Msk
     
    #define CAN_F4R2_FB19_Pos   (19U)
     
    #define CAN_F4R2_FB19_Msk   (0x1UL << CAN_F4R2_FB19_Pos)
     
    #define CAN_F4R2_FB19   CAN_F4R2_FB19_Msk
     
    #define CAN_F4R2_FB20_Pos   (20U)
     
    #define CAN_F4R2_FB20_Msk   (0x1UL << CAN_F4R2_FB20_Pos)
     
    #define CAN_F4R2_FB20   CAN_F4R2_FB20_Msk
     
    #define CAN_F4R2_FB21_Pos   (21U)
     
    #define CAN_F4R2_FB21_Msk   (0x1UL << CAN_F4R2_FB21_Pos)
     
    #define CAN_F4R2_FB21   CAN_F4R2_FB21_Msk
     
    #define CAN_F4R2_FB22_Pos   (22U)
     
    #define CAN_F4R2_FB22_Msk   (0x1UL << CAN_F4R2_FB22_Pos)
     
    #define CAN_F4R2_FB22   CAN_F4R2_FB22_Msk
     
    #define CAN_F4R2_FB23_Pos   (23U)
     
    #define CAN_F4R2_FB23_Msk   (0x1UL << CAN_F4R2_FB23_Pos)
     
    #define CAN_F4R2_FB23   CAN_F4R2_FB23_Msk
     
    #define CAN_F4R2_FB24_Pos   (24U)
     
    #define CAN_F4R2_FB24_Msk   (0x1UL << CAN_F4R2_FB24_Pos)
     
    #define CAN_F4R2_FB24   CAN_F4R2_FB24_Msk
     
    #define CAN_F4R2_FB25_Pos   (25U)
     
    #define CAN_F4R2_FB25_Msk   (0x1UL << CAN_F4R2_FB25_Pos)
     
    #define CAN_F4R2_FB25   CAN_F4R2_FB25_Msk
     
    #define CAN_F4R2_FB26_Pos   (26U)
     
    #define CAN_F4R2_FB26_Msk   (0x1UL << CAN_F4R2_FB26_Pos)
     
    #define CAN_F4R2_FB26   CAN_F4R2_FB26_Msk
     
    #define CAN_F4R2_FB27_Pos   (27U)
     
    #define CAN_F4R2_FB27_Msk   (0x1UL << CAN_F4R2_FB27_Pos)
     
    #define CAN_F4R2_FB27   CAN_F4R2_FB27_Msk
     
    #define CAN_F4R2_FB28_Pos   (28U)
     
    #define CAN_F4R2_FB28_Msk   (0x1UL << CAN_F4R2_FB28_Pos)
     
    #define CAN_F4R2_FB28   CAN_F4R2_FB28_Msk
     
    #define CAN_F4R2_FB29_Pos   (29U)
     
    #define CAN_F4R2_FB29_Msk   (0x1UL << CAN_F4R2_FB29_Pos)
     
    #define CAN_F4R2_FB29   CAN_F4R2_FB29_Msk
     
    #define CAN_F4R2_FB30_Pos   (30U)
     
    #define CAN_F4R2_FB30_Msk   (0x1UL << CAN_F4R2_FB30_Pos)
     
    #define CAN_F4R2_FB30   CAN_F4R2_FB30_Msk
     
    #define CAN_F4R2_FB31_Pos   (31U)
     
    #define CAN_F4R2_FB31_Msk   (0x1UL << CAN_F4R2_FB31_Pos)
     
    #define CAN_F4R2_FB31   CAN_F4R2_FB31_Msk
     
    #define CAN_F5R2_FB0_Pos   (0U)
     
    #define CAN_F5R2_FB0_Msk   (0x1UL << CAN_F5R2_FB0_Pos)
     
    #define CAN_F5R2_FB0   CAN_F5R2_FB0_Msk
     
    #define CAN_F5R2_FB1_Pos   (1U)
     
    #define CAN_F5R2_FB1_Msk   (0x1UL << CAN_F5R2_FB1_Pos)
     
    #define CAN_F5R2_FB1   CAN_F5R2_FB1_Msk
     
    #define CAN_F5R2_FB2_Pos   (2U)
     
    #define CAN_F5R2_FB2_Msk   (0x1UL << CAN_F5R2_FB2_Pos)
     
    #define CAN_F5R2_FB2   CAN_F5R2_FB2_Msk
     
    #define CAN_F5R2_FB3_Pos   (3U)
     
    #define CAN_F5R2_FB3_Msk   (0x1UL << CAN_F5R2_FB3_Pos)
     
    #define CAN_F5R2_FB3   CAN_F5R2_FB3_Msk
     
    #define CAN_F5R2_FB4_Pos   (4U)
     
    #define CAN_F5R2_FB4_Msk   (0x1UL << CAN_F5R2_FB4_Pos)
     
    #define CAN_F5R2_FB4   CAN_F5R2_FB4_Msk
     
    #define CAN_F5R2_FB5_Pos   (5U)
     
    #define CAN_F5R2_FB5_Msk   (0x1UL << CAN_F5R2_FB5_Pos)
     
    #define CAN_F5R2_FB5   CAN_F5R2_FB5_Msk
     
    #define CAN_F5R2_FB6_Pos   (6U)
     
    #define CAN_F5R2_FB6_Msk   (0x1UL << CAN_F5R2_FB6_Pos)
     
    #define CAN_F5R2_FB6   CAN_F5R2_FB6_Msk
     
    #define CAN_F5R2_FB7_Pos   (7U)
     
    #define CAN_F5R2_FB7_Msk   (0x1UL << CAN_F5R2_FB7_Pos)
     
    #define CAN_F5R2_FB7   CAN_F5R2_FB7_Msk
     
    #define CAN_F5R2_FB8_Pos   (8U)
     
    #define CAN_F5R2_FB8_Msk   (0x1UL << CAN_F5R2_FB8_Pos)
     
    #define CAN_F5R2_FB8   CAN_F5R2_FB8_Msk
     
    #define CAN_F5R2_FB9_Pos   (9U)
     
    #define CAN_F5R2_FB9_Msk   (0x1UL << CAN_F5R2_FB9_Pos)
     
    #define CAN_F5R2_FB9   CAN_F5R2_FB9_Msk
     
    #define CAN_F5R2_FB10_Pos   (10U)
     
    #define CAN_F5R2_FB10_Msk   (0x1UL << CAN_F5R2_FB10_Pos)
     
    #define CAN_F5R2_FB10   CAN_F5R2_FB10_Msk
     
    #define CAN_F5R2_FB11_Pos   (11U)
     
    #define CAN_F5R2_FB11_Msk   (0x1UL << CAN_F5R2_FB11_Pos)
     
    #define CAN_F5R2_FB11   CAN_F5R2_FB11_Msk
     
    #define CAN_F5R2_FB12_Pos   (12U)
     
    #define CAN_F5R2_FB12_Msk   (0x1UL << CAN_F5R2_FB12_Pos)
     
    #define CAN_F5R2_FB12   CAN_F5R2_FB12_Msk
     
    #define CAN_F5R2_FB13_Pos   (13U)
     
    #define CAN_F5R2_FB13_Msk   (0x1UL << CAN_F5R2_FB13_Pos)
     
    #define CAN_F5R2_FB13   CAN_F5R2_FB13_Msk
     
    #define CAN_F5R2_FB14_Pos   (14U)
     
    #define CAN_F5R2_FB14_Msk   (0x1UL << CAN_F5R2_FB14_Pos)
     
    #define CAN_F5R2_FB14   CAN_F5R2_FB14_Msk
     
    #define CAN_F5R2_FB15_Pos   (15U)
     
    #define CAN_F5R2_FB15_Msk   (0x1UL << CAN_F5R2_FB15_Pos)
     
    #define CAN_F5R2_FB15   CAN_F5R2_FB15_Msk
     
    #define CAN_F5R2_FB16_Pos   (16U)
     
    #define CAN_F5R2_FB16_Msk   (0x1UL << CAN_F5R2_FB16_Pos)
     
    #define CAN_F5R2_FB16   CAN_F5R2_FB16_Msk
     
    #define CAN_F5R2_FB17_Pos   (17U)
     
    #define CAN_F5R2_FB17_Msk   (0x1UL << CAN_F5R2_FB17_Pos)
     
    #define CAN_F5R2_FB17   CAN_F5R2_FB17_Msk
     
    #define CAN_F5R2_FB18_Pos   (18U)
     
    #define CAN_F5R2_FB18_Msk   (0x1UL << CAN_F5R2_FB18_Pos)
     
    #define CAN_F5R2_FB18   CAN_F5R2_FB18_Msk
     
    #define CAN_F5R2_FB19_Pos   (19U)
     
    #define CAN_F5R2_FB19_Msk   (0x1UL << CAN_F5R2_FB19_Pos)
     
    #define CAN_F5R2_FB19   CAN_F5R2_FB19_Msk
     
    #define CAN_F5R2_FB20_Pos   (20U)
     
    #define CAN_F5R2_FB20_Msk   (0x1UL << CAN_F5R2_FB20_Pos)
     
    #define CAN_F5R2_FB20   CAN_F5R2_FB20_Msk
     
    #define CAN_F5R2_FB21_Pos   (21U)
     
    #define CAN_F5R2_FB21_Msk   (0x1UL << CAN_F5R2_FB21_Pos)
     
    #define CAN_F5R2_FB21   CAN_F5R2_FB21_Msk
     
    #define CAN_F5R2_FB22_Pos   (22U)
     
    #define CAN_F5R2_FB22_Msk   (0x1UL << CAN_F5R2_FB22_Pos)
     
    #define CAN_F5R2_FB22   CAN_F5R2_FB22_Msk
     
    #define CAN_F5R2_FB23_Pos   (23U)
     
    #define CAN_F5R2_FB23_Msk   (0x1UL << CAN_F5R2_FB23_Pos)
     
    #define CAN_F5R2_FB23   CAN_F5R2_FB23_Msk
     
    #define CAN_F5R2_FB24_Pos   (24U)
     
    #define CAN_F5R2_FB24_Msk   (0x1UL << CAN_F5R2_FB24_Pos)
     
    #define CAN_F5R2_FB24   CAN_F5R2_FB24_Msk
     
    #define CAN_F5R2_FB25_Pos   (25U)
     
    #define CAN_F5R2_FB25_Msk   (0x1UL << CAN_F5R2_FB25_Pos)
     
    #define CAN_F5R2_FB25   CAN_F5R2_FB25_Msk
     
    #define CAN_F5R2_FB26_Pos   (26U)
     
    #define CAN_F5R2_FB26_Msk   (0x1UL << CAN_F5R2_FB26_Pos)
     
    #define CAN_F5R2_FB26   CAN_F5R2_FB26_Msk
     
    #define CAN_F5R2_FB27_Pos   (27U)
     
    #define CAN_F5R2_FB27_Msk   (0x1UL << CAN_F5R2_FB27_Pos)
     
    #define CAN_F5R2_FB27   CAN_F5R2_FB27_Msk
     
    #define CAN_F5R2_FB28_Pos   (28U)
     
    #define CAN_F5R2_FB28_Msk   (0x1UL << CAN_F5R2_FB28_Pos)
     
    #define CAN_F5R2_FB28   CAN_F5R2_FB28_Msk
     
    #define CAN_F5R2_FB29_Pos   (29U)
     
    #define CAN_F5R2_FB29_Msk   (0x1UL << CAN_F5R2_FB29_Pos)
     
    #define CAN_F5R2_FB29   CAN_F5R2_FB29_Msk
     
    #define CAN_F5R2_FB30_Pos   (30U)
     
    #define CAN_F5R2_FB30_Msk   (0x1UL << CAN_F5R2_FB30_Pos)
     
    #define CAN_F5R2_FB30   CAN_F5R2_FB30_Msk
     
    #define CAN_F5R2_FB31_Pos   (31U)
     
    #define CAN_F5R2_FB31_Msk   (0x1UL << CAN_F5R2_FB31_Pos)
     
    #define CAN_F5R2_FB31   CAN_F5R2_FB31_Msk
     
    #define CAN_F6R2_FB0_Pos   (0U)
     
    #define CAN_F6R2_FB0_Msk   (0x1UL << CAN_F6R2_FB0_Pos)
     
    #define CAN_F6R2_FB0   CAN_F6R2_FB0_Msk
     
    #define CAN_F6R2_FB1_Pos   (1U)
     
    #define CAN_F6R2_FB1_Msk   (0x1UL << CAN_F6R2_FB1_Pos)
     
    #define CAN_F6R2_FB1   CAN_F6R2_FB1_Msk
     
    #define CAN_F6R2_FB2_Pos   (2U)
     
    #define CAN_F6R2_FB2_Msk   (0x1UL << CAN_F6R2_FB2_Pos)
     
    #define CAN_F6R2_FB2   CAN_F6R2_FB2_Msk
     
    #define CAN_F6R2_FB3_Pos   (3U)
     
    #define CAN_F6R2_FB3_Msk   (0x1UL << CAN_F6R2_FB3_Pos)
     
    #define CAN_F6R2_FB3   CAN_F6R2_FB3_Msk
     
    #define CAN_F6R2_FB4_Pos   (4U)
     
    #define CAN_F6R2_FB4_Msk   (0x1UL << CAN_F6R2_FB4_Pos)
     
    #define CAN_F6R2_FB4   CAN_F6R2_FB4_Msk
     
    #define CAN_F6R2_FB5_Pos   (5U)
     
    #define CAN_F6R2_FB5_Msk   (0x1UL << CAN_F6R2_FB5_Pos)
     
    #define CAN_F6R2_FB5   CAN_F6R2_FB5_Msk
     
    #define CAN_F6R2_FB6_Pos   (6U)
     
    #define CAN_F6R2_FB6_Msk   (0x1UL << CAN_F6R2_FB6_Pos)
     
    #define CAN_F6R2_FB6   CAN_F6R2_FB6_Msk
     
    #define CAN_F6R2_FB7_Pos   (7U)
     
    #define CAN_F6R2_FB7_Msk   (0x1UL << CAN_F6R2_FB7_Pos)
     
    #define CAN_F6R2_FB7   CAN_F6R2_FB7_Msk
     
    #define CAN_F6R2_FB8_Pos   (8U)
     
    #define CAN_F6R2_FB8_Msk   (0x1UL << CAN_F6R2_FB8_Pos)
     
    #define CAN_F6R2_FB8   CAN_F6R2_FB8_Msk
     
    #define CAN_F6R2_FB9_Pos   (9U)
     
    #define CAN_F6R2_FB9_Msk   (0x1UL << CAN_F6R2_FB9_Pos)
     
    #define CAN_F6R2_FB9   CAN_F6R2_FB9_Msk
     
    #define CAN_F6R2_FB10_Pos   (10U)
     
    #define CAN_F6R2_FB10_Msk   (0x1UL << CAN_F6R2_FB10_Pos)
     
    #define CAN_F6R2_FB10   CAN_F6R2_FB10_Msk
     
    #define CAN_F6R2_FB11_Pos   (11U)
     
    #define CAN_F6R2_FB11_Msk   (0x1UL << CAN_F6R2_FB11_Pos)
     
    #define CAN_F6R2_FB11   CAN_F6R2_FB11_Msk
     
    #define CAN_F6R2_FB12_Pos   (12U)
     
    #define CAN_F6R2_FB12_Msk   (0x1UL << CAN_F6R2_FB12_Pos)
     
    #define CAN_F6R2_FB12   CAN_F6R2_FB12_Msk
     
    #define CAN_F6R2_FB13_Pos   (13U)
     
    #define CAN_F6R2_FB13_Msk   (0x1UL << CAN_F6R2_FB13_Pos)
     
    #define CAN_F6R2_FB13   CAN_F6R2_FB13_Msk
     
    #define CAN_F6R2_FB14_Pos   (14U)
     
    #define CAN_F6R2_FB14_Msk   (0x1UL << CAN_F6R2_FB14_Pos)
     
    #define CAN_F6R2_FB14   CAN_F6R2_FB14_Msk
     
    #define CAN_F6R2_FB15_Pos   (15U)
     
    #define CAN_F6R2_FB15_Msk   (0x1UL << CAN_F6R2_FB15_Pos)
     
    #define CAN_F6R2_FB15   CAN_F6R2_FB15_Msk
     
    #define CAN_F6R2_FB16_Pos   (16U)
     
    #define CAN_F6R2_FB16_Msk   (0x1UL << CAN_F6R2_FB16_Pos)
     
    #define CAN_F6R2_FB16   CAN_F6R2_FB16_Msk
     
    #define CAN_F6R2_FB17_Pos   (17U)
     
    #define CAN_F6R2_FB17_Msk   (0x1UL << CAN_F6R2_FB17_Pos)
     
    #define CAN_F6R2_FB17   CAN_F6R2_FB17_Msk
     
    #define CAN_F6R2_FB18_Pos   (18U)
     
    #define CAN_F6R2_FB18_Msk   (0x1UL << CAN_F6R2_FB18_Pos)
     
    #define CAN_F6R2_FB18   CAN_F6R2_FB18_Msk
     
    #define CAN_F6R2_FB19_Pos   (19U)
     
    #define CAN_F6R2_FB19_Msk   (0x1UL << CAN_F6R2_FB19_Pos)
     
    #define CAN_F6R2_FB19   CAN_F6R2_FB19_Msk
     
    #define CAN_F6R2_FB20_Pos   (20U)
     
    #define CAN_F6R2_FB20_Msk   (0x1UL << CAN_F6R2_FB20_Pos)
     
    #define CAN_F6R2_FB20   CAN_F6R2_FB20_Msk
     
    #define CAN_F6R2_FB21_Pos   (21U)
     
    #define CAN_F6R2_FB21_Msk   (0x1UL << CAN_F6R2_FB21_Pos)
     
    #define CAN_F6R2_FB21   CAN_F6R2_FB21_Msk
     
    #define CAN_F6R2_FB22_Pos   (22U)
     
    #define CAN_F6R2_FB22_Msk   (0x1UL << CAN_F6R2_FB22_Pos)
     
    #define CAN_F6R2_FB22   CAN_F6R2_FB22_Msk
     
    #define CAN_F6R2_FB23_Pos   (23U)
     
    #define CAN_F6R2_FB23_Msk   (0x1UL << CAN_F6R2_FB23_Pos)
     
    #define CAN_F6R2_FB23   CAN_F6R2_FB23_Msk
     
    #define CAN_F6R2_FB24_Pos   (24U)
     
    #define CAN_F6R2_FB24_Msk   (0x1UL << CAN_F6R2_FB24_Pos)
     
    #define CAN_F6R2_FB24   CAN_F6R2_FB24_Msk
     
    #define CAN_F6R2_FB25_Pos   (25U)
     
    #define CAN_F6R2_FB25_Msk   (0x1UL << CAN_F6R2_FB25_Pos)
     
    #define CAN_F6R2_FB25   CAN_F6R2_FB25_Msk
     
    #define CAN_F6R2_FB26_Pos   (26U)
     
    #define CAN_F6R2_FB26_Msk   (0x1UL << CAN_F6R2_FB26_Pos)
     
    #define CAN_F6R2_FB26   CAN_F6R2_FB26_Msk
     
    #define CAN_F6R2_FB27_Pos   (27U)
     
    #define CAN_F6R2_FB27_Msk   (0x1UL << CAN_F6R2_FB27_Pos)
     
    #define CAN_F6R2_FB27   CAN_F6R2_FB27_Msk
     
    #define CAN_F6R2_FB28_Pos   (28U)
     
    #define CAN_F6R2_FB28_Msk   (0x1UL << CAN_F6R2_FB28_Pos)
     
    #define CAN_F6R2_FB28   CAN_F6R2_FB28_Msk
     
    #define CAN_F6R2_FB29_Pos   (29U)
     
    #define CAN_F6R2_FB29_Msk   (0x1UL << CAN_F6R2_FB29_Pos)
     
    #define CAN_F6R2_FB29   CAN_F6R2_FB29_Msk
     
    #define CAN_F6R2_FB30_Pos   (30U)
     
    #define CAN_F6R2_FB30_Msk   (0x1UL << CAN_F6R2_FB30_Pos)
     
    #define CAN_F6R2_FB30   CAN_F6R2_FB30_Msk
     
    #define CAN_F6R2_FB31_Pos   (31U)
     
    #define CAN_F6R2_FB31_Msk   (0x1UL << CAN_F6R2_FB31_Pos)
     
    #define CAN_F6R2_FB31   CAN_F6R2_FB31_Msk
     
    #define CAN_F7R2_FB0_Pos   (0U)
     
    #define CAN_F7R2_FB0_Msk   (0x1UL << CAN_F7R2_FB0_Pos)
     
    #define CAN_F7R2_FB0   CAN_F7R2_FB0_Msk
     
    #define CAN_F7R2_FB1_Pos   (1U)
     
    #define CAN_F7R2_FB1_Msk   (0x1UL << CAN_F7R2_FB1_Pos)
     
    #define CAN_F7R2_FB1   CAN_F7R2_FB1_Msk
     
    #define CAN_F7R2_FB2_Pos   (2U)
     
    #define CAN_F7R2_FB2_Msk   (0x1UL << CAN_F7R2_FB2_Pos)
     
    #define CAN_F7R2_FB2   CAN_F7R2_FB2_Msk
     
    #define CAN_F7R2_FB3_Pos   (3U)
     
    #define CAN_F7R2_FB3_Msk   (0x1UL << CAN_F7R2_FB3_Pos)
     
    #define CAN_F7R2_FB3   CAN_F7R2_FB3_Msk
     
    #define CAN_F7R2_FB4_Pos   (4U)
     
    #define CAN_F7R2_FB4_Msk   (0x1UL << CAN_F7R2_FB4_Pos)
     
    #define CAN_F7R2_FB4   CAN_F7R2_FB4_Msk
     
    #define CAN_F7R2_FB5_Pos   (5U)
     
    #define CAN_F7R2_FB5_Msk   (0x1UL << CAN_F7R2_FB5_Pos)
     
    #define CAN_F7R2_FB5   CAN_F7R2_FB5_Msk
     
    #define CAN_F7R2_FB6_Pos   (6U)
     
    #define CAN_F7R2_FB6_Msk   (0x1UL << CAN_F7R2_FB6_Pos)
     
    #define CAN_F7R2_FB6   CAN_F7R2_FB6_Msk
     
    #define CAN_F7R2_FB7_Pos   (7U)
     
    #define CAN_F7R2_FB7_Msk   (0x1UL << CAN_F7R2_FB7_Pos)
     
    #define CAN_F7R2_FB7   CAN_F7R2_FB7_Msk
     
    #define CAN_F7R2_FB8_Pos   (8U)
     
    #define CAN_F7R2_FB8_Msk   (0x1UL << CAN_F7R2_FB8_Pos)
     
    #define CAN_F7R2_FB8   CAN_F7R2_FB8_Msk
     
    #define CAN_F7R2_FB9_Pos   (9U)
     
    #define CAN_F7R2_FB9_Msk   (0x1UL << CAN_F7R2_FB9_Pos)
     
    #define CAN_F7R2_FB9   CAN_F7R2_FB9_Msk
     
    #define CAN_F7R2_FB10_Pos   (10U)
     
    #define CAN_F7R2_FB10_Msk   (0x1UL << CAN_F7R2_FB10_Pos)
     
    #define CAN_F7R2_FB10   CAN_F7R2_FB10_Msk
     
    #define CAN_F7R2_FB11_Pos   (11U)
     
    #define CAN_F7R2_FB11_Msk   (0x1UL << CAN_F7R2_FB11_Pos)
     
    #define CAN_F7R2_FB11   CAN_F7R2_FB11_Msk
     
    #define CAN_F7R2_FB12_Pos   (12U)
     
    #define CAN_F7R2_FB12_Msk   (0x1UL << CAN_F7R2_FB12_Pos)
     
    #define CAN_F7R2_FB12   CAN_F7R2_FB12_Msk
     
    #define CAN_F7R2_FB13_Pos   (13U)
     
    #define CAN_F7R2_FB13_Msk   (0x1UL << CAN_F7R2_FB13_Pos)
     
    #define CAN_F7R2_FB13   CAN_F7R2_FB13_Msk
     
    #define CAN_F7R2_FB14_Pos   (14U)
     
    #define CAN_F7R2_FB14_Msk   (0x1UL << CAN_F7R2_FB14_Pos)
     
    #define CAN_F7R2_FB14   CAN_F7R2_FB14_Msk
     
    #define CAN_F7R2_FB15_Pos   (15U)
     
    #define CAN_F7R2_FB15_Msk   (0x1UL << CAN_F7R2_FB15_Pos)
     
    #define CAN_F7R2_FB15   CAN_F7R2_FB15_Msk
     
    #define CAN_F7R2_FB16_Pos   (16U)
     
    #define CAN_F7R2_FB16_Msk   (0x1UL << CAN_F7R2_FB16_Pos)
     
    #define CAN_F7R2_FB16   CAN_F7R2_FB16_Msk
     
    #define CAN_F7R2_FB17_Pos   (17U)
     
    #define CAN_F7R2_FB17_Msk   (0x1UL << CAN_F7R2_FB17_Pos)
     
    #define CAN_F7R2_FB17   CAN_F7R2_FB17_Msk
     
    #define CAN_F7R2_FB18_Pos   (18U)
     
    #define CAN_F7R2_FB18_Msk   (0x1UL << CAN_F7R2_FB18_Pos)
     
    #define CAN_F7R2_FB18   CAN_F7R2_FB18_Msk
     
    #define CAN_F7R2_FB19_Pos   (19U)
     
    #define CAN_F7R2_FB19_Msk   (0x1UL << CAN_F7R2_FB19_Pos)
     
    #define CAN_F7R2_FB19   CAN_F7R2_FB19_Msk
     
    #define CAN_F7R2_FB20_Pos   (20U)
     
    #define CAN_F7R2_FB20_Msk   (0x1UL << CAN_F7R2_FB20_Pos)
     
    #define CAN_F7R2_FB20   CAN_F7R2_FB20_Msk
     
    #define CAN_F7R2_FB21_Pos   (21U)
     
    #define CAN_F7R2_FB21_Msk   (0x1UL << CAN_F7R2_FB21_Pos)
     
    #define CAN_F7R2_FB21   CAN_F7R2_FB21_Msk
     
    #define CAN_F7R2_FB22_Pos   (22U)
     
    #define CAN_F7R2_FB22_Msk   (0x1UL << CAN_F7R2_FB22_Pos)
     
    #define CAN_F7R2_FB22   CAN_F7R2_FB22_Msk
     
    #define CAN_F7R2_FB23_Pos   (23U)
     
    #define CAN_F7R2_FB23_Msk   (0x1UL << CAN_F7R2_FB23_Pos)
     
    #define CAN_F7R2_FB23   CAN_F7R2_FB23_Msk
     
    #define CAN_F7R2_FB24_Pos   (24U)
     
    #define CAN_F7R2_FB24_Msk   (0x1UL << CAN_F7R2_FB24_Pos)
     
    #define CAN_F7R2_FB24   CAN_F7R2_FB24_Msk
     
    #define CAN_F7R2_FB25_Pos   (25U)
     
    #define CAN_F7R2_FB25_Msk   (0x1UL << CAN_F7R2_FB25_Pos)
     
    #define CAN_F7R2_FB25   CAN_F7R2_FB25_Msk
     
    #define CAN_F7R2_FB26_Pos   (26U)
     
    #define CAN_F7R2_FB26_Msk   (0x1UL << CAN_F7R2_FB26_Pos)
     
    #define CAN_F7R2_FB26   CAN_F7R2_FB26_Msk
     
    #define CAN_F7R2_FB27_Pos   (27U)
     
    #define CAN_F7R2_FB27_Msk   (0x1UL << CAN_F7R2_FB27_Pos)
     
    #define CAN_F7R2_FB27   CAN_F7R2_FB27_Msk
     
    #define CAN_F7R2_FB28_Pos   (28U)
     
    #define CAN_F7R2_FB28_Msk   (0x1UL << CAN_F7R2_FB28_Pos)
     
    #define CAN_F7R2_FB28   CAN_F7R2_FB28_Msk
     
    #define CAN_F7R2_FB29_Pos   (29U)
     
    #define CAN_F7R2_FB29_Msk   (0x1UL << CAN_F7R2_FB29_Pos)
     
    #define CAN_F7R2_FB29   CAN_F7R2_FB29_Msk
     
    #define CAN_F7R2_FB30_Pos   (30U)
     
    #define CAN_F7R2_FB30_Msk   (0x1UL << CAN_F7R2_FB30_Pos)
     
    #define CAN_F7R2_FB30   CAN_F7R2_FB30_Msk
     
    #define CAN_F7R2_FB31_Pos   (31U)
     
    #define CAN_F7R2_FB31_Msk   (0x1UL << CAN_F7R2_FB31_Pos)
     
    #define CAN_F7R2_FB31   CAN_F7R2_FB31_Msk
     
    #define CAN_F8R2_FB0_Pos   (0U)
     
    #define CAN_F8R2_FB0_Msk   (0x1UL << CAN_F8R2_FB0_Pos)
     
    #define CAN_F8R2_FB0   CAN_F8R2_FB0_Msk
     
    #define CAN_F8R2_FB1_Pos   (1U)
     
    #define CAN_F8R2_FB1_Msk   (0x1UL << CAN_F8R2_FB1_Pos)
     
    #define CAN_F8R2_FB1   CAN_F8R2_FB1_Msk
     
    #define CAN_F8R2_FB2_Pos   (2U)
     
    #define CAN_F8R2_FB2_Msk   (0x1UL << CAN_F8R2_FB2_Pos)
     
    #define CAN_F8R2_FB2   CAN_F8R2_FB2_Msk
     
    #define CAN_F8R2_FB3_Pos   (3U)
     
    #define CAN_F8R2_FB3_Msk   (0x1UL << CAN_F8R2_FB3_Pos)
     
    #define CAN_F8R2_FB3   CAN_F8R2_FB3_Msk
     
    #define CAN_F8R2_FB4_Pos   (4U)
     
    #define CAN_F8R2_FB4_Msk   (0x1UL << CAN_F8R2_FB4_Pos)
     
    #define CAN_F8R2_FB4   CAN_F8R2_FB4_Msk
     
    #define CAN_F8R2_FB5_Pos   (5U)
     
    #define CAN_F8R2_FB5_Msk   (0x1UL << CAN_F8R2_FB5_Pos)
     
    #define CAN_F8R2_FB5   CAN_F8R2_FB5_Msk
     
    #define CAN_F8R2_FB6_Pos   (6U)
     
    #define CAN_F8R2_FB6_Msk   (0x1UL << CAN_F8R2_FB6_Pos)
     
    #define CAN_F8R2_FB6   CAN_F8R2_FB6_Msk
     
    #define CAN_F8R2_FB7_Pos   (7U)
     
    #define CAN_F8R2_FB7_Msk   (0x1UL << CAN_F8R2_FB7_Pos)
     
    #define CAN_F8R2_FB7   CAN_F8R2_FB7_Msk
     
    #define CAN_F8R2_FB8_Pos   (8U)
     
    #define CAN_F8R2_FB8_Msk   (0x1UL << CAN_F8R2_FB8_Pos)
     
    #define CAN_F8R2_FB8   CAN_F8R2_FB8_Msk
     
    #define CAN_F8R2_FB9_Pos   (9U)
     
    #define CAN_F8R2_FB9_Msk   (0x1UL << CAN_F8R2_FB9_Pos)
     
    #define CAN_F8R2_FB9   CAN_F8R2_FB9_Msk
     
    #define CAN_F8R2_FB10_Pos   (10U)
     
    #define CAN_F8R2_FB10_Msk   (0x1UL << CAN_F8R2_FB10_Pos)
     
    #define CAN_F8R2_FB10   CAN_F8R2_FB10_Msk
     
    #define CAN_F8R2_FB11_Pos   (11U)
     
    #define CAN_F8R2_FB11_Msk   (0x1UL << CAN_F8R2_FB11_Pos)
     
    #define CAN_F8R2_FB11   CAN_F8R2_FB11_Msk
     
    #define CAN_F8R2_FB12_Pos   (12U)
     
    #define CAN_F8R2_FB12_Msk   (0x1UL << CAN_F8R2_FB12_Pos)
     
    #define CAN_F8R2_FB12   CAN_F8R2_FB12_Msk
     
    #define CAN_F8R2_FB13_Pos   (13U)
     
    #define CAN_F8R2_FB13_Msk   (0x1UL << CAN_F8R2_FB13_Pos)
     
    #define CAN_F8R2_FB13   CAN_F8R2_FB13_Msk
     
    #define CAN_F8R2_FB14_Pos   (14U)
     
    #define CAN_F8R2_FB14_Msk   (0x1UL << CAN_F8R2_FB14_Pos)
     
    #define CAN_F8R2_FB14   CAN_F8R2_FB14_Msk
     
    #define CAN_F8R2_FB15_Pos   (15U)
     
    #define CAN_F8R2_FB15_Msk   (0x1UL << CAN_F8R2_FB15_Pos)
     
    #define CAN_F8R2_FB15   CAN_F8R2_FB15_Msk
     
    #define CAN_F8R2_FB16_Pos   (16U)
     
    #define CAN_F8R2_FB16_Msk   (0x1UL << CAN_F8R2_FB16_Pos)
     
    #define CAN_F8R2_FB16   CAN_F8R2_FB16_Msk
     
    #define CAN_F8R2_FB17_Pos   (17U)
     
    #define CAN_F8R2_FB17_Msk   (0x1UL << CAN_F8R2_FB17_Pos)
     
    #define CAN_F8R2_FB17   CAN_F8R2_FB17_Msk
     
    #define CAN_F8R2_FB18_Pos   (18U)
     
    #define CAN_F8R2_FB18_Msk   (0x1UL << CAN_F8R2_FB18_Pos)
     
    #define CAN_F8R2_FB18   CAN_F8R2_FB18_Msk
     
    #define CAN_F8R2_FB19_Pos   (19U)
     
    #define CAN_F8R2_FB19_Msk   (0x1UL << CAN_F8R2_FB19_Pos)
     
    #define CAN_F8R2_FB19   CAN_F8R2_FB19_Msk
     
    #define CAN_F8R2_FB20_Pos   (20U)
     
    #define CAN_F8R2_FB20_Msk   (0x1UL << CAN_F8R2_FB20_Pos)
     
    #define CAN_F8R2_FB20   CAN_F8R2_FB20_Msk
     
    #define CAN_F8R2_FB21_Pos   (21U)
     
    #define CAN_F8R2_FB21_Msk   (0x1UL << CAN_F8R2_FB21_Pos)
     
    #define CAN_F8R2_FB21   CAN_F8R2_FB21_Msk
     
    #define CAN_F8R2_FB22_Pos   (22U)
     
    #define CAN_F8R2_FB22_Msk   (0x1UL << CAN_F8R2_FB22_Pos)
     
    #define CAN_F8R2_FB22   CAN_F8R2_FB22_Msk
     
    #define CAN_F8R2_FB23_Pos   (23U)
     
    #define CAN_F8R2_FB23_Msk   (0x1UL << CAN_F8R2_FB23_Pos)
     
    #define CAN_F8R2_FB23   CAN_F8R2_FB23_Msk
     
    #define CAN_F8R2_FB24_Pos   (24U)
     
    #define CAN_F8R2_FB24_Msk   (0x1UL << CAN_F8R2_FB24_Pos)
     
    #define CAN_F8R2_FB24   CAN_F8R2_FB24_Msk
     
    #define CAN_F8R2_FB25_Pos   (25U)
     
    #define CAN_F8R2_FB25_Msk   (0x1UL << CAN_F8R2_FB25_Pos)
     
    #define CAN_F8R2_FB25   CAN_F8R2_FB25_Msk
     
    #define CAN_F8R2_FB26_Pos   (26U)
     
    #define CAN_F8R2_FB26_Msk   (0x1UL << CAN_F8R2_FB26_Pos)
     
    #define CAN_F8R2_FB26   CAN_F8R2_FB26_Msk
     
    #define CAN_F8R2_FB27_Pos   (27U)
     
    #define CAN_F8R2_FB27_Msk   (0x1UL << CAN_F8R2_FB27_Pos)
     
    #define CAN_F8R2_FB27   CAN_F8R2_FB27_Msk
     
    #define CAN_F8R2_FB28_Pos   (28U)
     
    #define CAN_F8R2_FB28_Msk   (0x1UL << CAN_F8R2_FB28_Pos)
     
    #define CAN_F8R2_FB28   CAN_F8R2_FB28_Msk
     
    #define CAN_F8R2_FB29_Pos   (29U)
     
    #define CAN_F8R2_FB29_Msk   (0x1UL << CAN_F8R2_FB29_Pos)
     
    #define CAN_F8R2_FB29   CAN_F8R2_FB29_Msk
     
    #define CAN_F8R2_FB30_Pos   (30U)
     
    #define CAN_F8R2_FB30_Msk   (0x1UL << CAN_F8R2_FB30_Pos)
     
    #define CAN_F8R2_FB30   CAN_F8R2_FB30_Msk
     
    #define CAN_F8R2_FB31_Pos   (31U)
     
    #define CAN_F8R2_FB31_Msk   (0x1UL << CAN_F8R2_FB31_Pos)
     
    #define CAN_F8R2_FB31   CAN_F8R2_FB31_Msk
     
    #define CAN_F9R2_FB0_Pos   (0U)
     
    #define CAN_F9R2_FB0_Msk   (0x1UL << CAN_F9R2_FB0_Pos)
     
    #define CAN_F9R2_FB0   CAN_F9R2_FB0_Msk
     
    #define CAN_F9R2_FB1_Pos   (1U)
     
    #define CAN_F9R2_FB1_Msk   (0x1UL << CAN_F9R2_FB1_Pos)
     
    #define CAN_F9R2_FB1   CAN_F9R2_FB1_Msk
     
    #define CAN_F9R2_FB2_Pos   (2U)
     
    #define CAN_F9R2_FB2_Msk   (0x1UL << CAN_F9R2_FB2_Pos)
     
    #define CAN_F9R2_FB2   CAN_F9R2_FB2_Msk
     
    #define CAN_F9R2_FB3_Pos   (3U)
     
    #define CAN_F9R2_FB3_Msk   (0x1UL << CAN_F9R2_FB3_Pos)
     
    #define CAN_F9R2_FB3   CAN_F9R2_FB3_Msk
     
    #define CAN_F9R2_FB4_Pos   (4U)
     
    #define CAN_F9R2_FB4_Msk   (0x1UL << CAN_F9R2_FB4_Pos)
     
    #define CAN_F9R2_FB4   CAN_F9R2_FB4_Msk
     
    #define CAN_F9R2_FB5_Pos   (5U)
     
    #define CAN_F9R2_FB5_Msk   (0x1UL << CAN_F9R2_FB5_Pos)
     
    #define CAN_F9R2_FB5   CAN_F9R2_FB5_Msk
     
    #define CAN_F9R2_FB6_Pos   (6U)
     
    #define CAN_F9R2_FB6_Msk   (0x1UL << CAN_F9R2_FB6_Pos)
     
    #define CAN_F9R2_FB6   CAN_F9R2_FB6_Msk
     
    #define CAN_F9R2_FB7_Pos   (7U)
     
    #define CAN_F9R2_FB7_Msk   (0x1UL << CAN_F9R2_FB7_Pos)
     
    #define CAN_F9R2_FB7   CAN_F9R2_FB7_Msk
     
    #define CAN_F9R2_FB8_Pos   (8U)
     
    #define CAN_F9R2_FB8_Msk   (0x1UL << CAN_F9R2_FB8_Pos)
     
    #define CAN_F9R2_FB8   CAN_F9R2_FB8_Msk
     
    #define CAN_F9R2_FB9_Pos   (9U)
     
    #define CAN_F9R2_FB9_Msk   (0x1UL << CAN_F9R2_FB9_Pos)
     
    #define CAN_F9R2_FB9   CAN_F9R2_FB9_Msk
     
    #define CAN_F9R2_FB10_Pos   (10U)
     
    #define CAN_F9R2_FB10_Msk   (0x1UL << CAN_F9R2_FB10_Pos)
     
    #define CAN_F9R2_FB10   CAN_F9R2_FB10_Msk
     
    #define CAN_F9R2_FB11_Pos   (11U)
     
    #define CAN_F9R2_FB11_Msk   (0x1UL << CAN_F9R2_FB11_Pos)
     
    #define CAN_F9R2_FB11   CAN_F9R2_FB11_Msk
     
    #define CAN_F9R2_FB12_Pos   (12U)
     
    #define CAN_F9R2_FB12_Msk   (0x1UL << CAN_F9R2_FB12_Pos)
     
    #define CAN_F9R2_FB12   CAN_F9R2_FB12_Msk
     
    #define CAN_F9R2_FB13_Pos   (13U)
     
    #define CAN_F9R2_FB13_Msk   (0x1UL << CAN_F9R2_FB13_Pos)
     
    #define CAN_F9R2_FB13   CAN_F9R2_FB13_Msk
     
    #define CAN_F9R2_FB14_Pos   (14U)
     
    #define CAN_F9R2_FB14_Msk   (0x1UL << CAN_F9R2_FB14_Pos)
     
    #define CAN_F9R2_FB14   CAN_F9R2_FB14_Msk
     
    #define CAN_F9R2_FB15_Pos   (15U)
     
    #define CAN_F9R2_FB15_Msk   (0x1UL << CAN_F9R2_FB15_Pos)
     
    #define CAN_F9R2_FB15   CAN_F9R2_FB15_Msk
     
    #define CAN_F9R2_FB16_Pos   (16U)
     
    #define CAN_F9R2_FB16_Msk   (0x1UL << CAN_F9R2_FB16_Pos)
     
    #define CAN_F9R2_FB16   CAN_F9R2_FB16_Msk
     
    #define CAN_F9R2_FB17_Pos   (17U)
     
    #define CAN_F9R2_FB17_Msk   (0x1UL << CAN_F9R2_FB17_Pos)
     
    #define CAN_F9R2_FB17   CAN_F9R2_FB17_Msk
     
    #define CAN_F9R2_FB18_Pos   (18U)
     
    #define CAN_F9R2_FB18_Msk   (0x1UL << CAN_F9R2_FB18_Pos)
     
    #define CAN_F9R2_FB18   CAN_F9R2_FB18_Msk
     
    #define CAN_F9R2_FB19_Pos   (19U)
     
    #define CAN_F9R2_FB19_Msk   (0x1UL << CAN_F9R2_FB19_Pos)
     
    #define CAN_F9R2_FB19   CAN_F9R2_FB19_Msk
     
    #define CAN_F9R2_FB20_Pos   (20U)
     
    #define CAN_F9R2_FB20_Msk   (0x1UL << CAN_F9R2_FB20_Pos)
     
    #define CAN_F9R2_FB20   CAN_F9R2_FB20_Msk
     
    #define CAN_F9R2_FB21_Pos   (21U)
     
    #define CAN_F9R2_FB21_Msk   (0x1UL << CAN_F9R2_FB21_Pos)
     
    #define CAN_F9R2_FB21   CAN_F9R2_FB21_Msk
     
    #define CAN_F9R2_FB22_Pos   (22U)
     
    #define CAN_F9R2_FB22_Msk   (0x1UL << CAN_F9R2_FB22_Pos)
     
    #define CAN_F9R2_FB22   CAN_F9R2_FB22_Msk
     
    #define CAN_F9R2_FB23_Pos   (23U)
     
    #define CAN_F9R2_FB23_Msk   (0x1UL << CAN_F9R2_FB23_Pos)
     
    #define CAN_F9R2_FB23   CAN_F9R2_FB23_Msk
     
    #define CAN_F9R2_FB24_Pos   (24U)
     
    #define CAN_F9R2_FB24_Msk   (0x1UL << CAN_F9R2_FB24_Pos)
     
    #define CAN_F9R2_FB24   CAN_F9R2_FB24_Msk
     
    #define CAN_F9R2_FB25_Pos   (25U)
     
    #define CAN_F9R2_FB25_Msk   (0x1UL << CAN_F9R2_FB25_Pos)
     
    #define CAN_F9R2_FB25   CAN_F9R2_FB25_Msk
     
    #define CAN_F9R2_FB26_Pos   (26U)
     
    #define CAN_F9R2_FB26_Msk   (0x1UL << CAN_F9R2_FB26_Pos)
     
    #define CAN_F9R2_FB26   CAN_F9R2_FB26_Msk
     
    #define CAN_F9R2_FB27_Pos   (27U)
     
    #define CAN_F9R2_FB27_Msk   (0x1UL << CAN_F9R2_FB27_Pos)
     
    #define CAN_F9R2_FB27   CAN_F9R2_FB27_Msk
     
    #define CAN_F9R2_FB28_Pos   (28U)
     
    #define CAN_F9R2_FB28_Msk   (0x1UL << CAN_F9R2_FB28_Pos)
     
    #define CAN_F9R2_FB28   CAN_F9R2_FB28_Msk
     
    #define CAN_F9R2_FB29_Pos   (29U)
     
    #define CAN_F9R2_FB29_Msk   (0x1UL << CAN_F9R2_FB29_Pos)
     
    #define CAN_F9R2_FB29   CAN_F9R2_FB29_Msk
     
    #define CAN_F9R2_FB30_Pos   (30U)
     
    #define CAN_F9R2_FB30_Msk   (0x1UL << CAN_F9R2_FB30_Pos)
     
    #define CAN_F9R2_FB30   CAN_F9R2_FB30_Msk
     
    #define CAN_F9R2_FB31_Pos   (31U)
     
    #define CAN_F9R2_FB31_Msk   (0x1UL << CAN_F9R2_FB31_Pos)
     
    #define CAN_F9R2_FB31   CAN_F9R2_FB31_Msk
     
    #define CAN_F10R2_FB0_Pos   (0U)
     
    #define CAN_F10R2_FB0_Msk   (0x1UL << CAN_F10R2_FB0_Pos)
     
    #define CAN_F10R2_FB0   CAN_F10R2_FB0_Msk
     
    #define CAN_F10R2_FB1_Pos   (1U)
     
    #define CAN_F10R2_FB1_Msk   (0x1UL << CAN_F10R2_FB1_Pos)
     
    #define CAN_F10R2_FB1   CAN_F10R2_FB1_Msk
     
    #define CAN_F10R2_FB2_Pos   (2U)
     
    #define CAN_F10R2_FB2_Msk   (0x1UL << CAN_F10R2_FB2_Pos)
     
    #define CAN_F10R2_FB2   CAN_F10R2_FB2_Msk
     
    #define CAN_F10R2_FB3_Pos   (3U)
     
    #define CAN_F10R2_FB3_Msk   (0x1UL << CAN_F10R2_FB3_Pos)
     
    #define CAN_F10R2_FB3   CAN_F10R2_FB3_Msk
     
    #define CAN_F10R2_FB4_Pos   (4U)
     
    #define CAN_F10R2_FB4_Msk   (0x1UL << CAN_F10R2_FB4_Pos)
     
    #define CAN_F10R2_FB4   CAN_F10R2_FB4_Msk
     
    #define CAN_F10R2_FB5_Pos   (5U)
     
    #define CAN_F10R2_FB5_Msk   (0x1UL << CAN_F10R2_FB5_Pos)
     
    #define CAN_F10R2_FB5   CAN_F10R2_FB5_Msk
     
    #define CAN_F10R2_FB6_Pos   (6U)
     
    #define CAN_F10R2_FB6_Msk   (0x1UL << CAN_F10R2_FB6_Pos)
     
    #define CAN_F10R2_FB6   CAN_F10R2_FB6_Msk
     
    #define CAN_F10R2_FB7_Pos   (7U)
     
    #define CAN_F10R2_FB7_Msk   (0x1UL << CAN_F10R2_FB7_Pos)
     
    #define CAN_F10R2_FB7   CAN_F10R2_FB7_Msk
     
    #define CAN_F10R2_FB8_Pos   (8U)
     
    #define CAN_F10R2_FB8_Msk   (0x1UL << CAN_F10R2_FB8_Pos)
     
    #define CAN_F10R2_FB8   CAN_F10R2_FB8_Msk
     
    #define CAN_F10R2_FB9_Pos   (9U)
     
    #define CAN_F10R2_FB9_Msk   (0x1UL << CAN_F10R2_FB9_Pos)
     
    #define CAN_F10R2_FB9   CAN_F10R2_FB9_Msk
     
    #define CAN_F10R2_FB10_Pos   (10U)
     
    #define CAN_F10R2_FB10_Msk   (0x1UL << CAN_F10R2_FB10_Pos)
     
    #define CAN_F10R2_FB10   CAN_F10R2_FB10_Msk
     
    #define CAN_F10R2_FB11_Pos   (11U)
     
    #define CAN_F10R2_FB11_Msk   (0x1UL << CAN_F10R2_FB11_Pos)
     
    #define CAN_F10R2_FB11   CAN_F10R2_FB11_Msk
     
    #define CAN_F10R2_FB12_Pos   (12U)
     
    #define CAN_F10R2_FB12_Msk   (0x1UL << CAN_F10R2_FB12_Pos)
     
    #define CAN_F10R2_FB12   CAN_F10R2_FB12_Msk
     
    #define CAN_F10R2_FB13_Pos   (13U)
     
    #define CAN_F10R2_FB13_Msk   (0x1UL << CAN_F10R2_FB13_Pos)
     
    #define CAN_F10R2_FB13   CAN_F10R2_FB13_Msk
     
    #define CAN_F10R2_FB14_Pos   (14U)
     
    #define CAN_F10R2_FB14_Msk   (0x1UL << CAN_F10R2_FB14_Pos)
     
    #define CAN_F10R2_FB14   CAN_F10R2_FB14_Msk
     
    #define CAN_F10R2_FB15_Pos   (15U)
     
    #define CAN_F10R2_FB15_Msk   (0x1UL << CAN_F10R2_FB15_Pos)
     
    #define CAN_F10R2_FB15   CAN_F10R2_FB15_Msk
     
    #define CAN_F10R2_FB16_Pos   (16U)
     
    #define CAN_F10R2_FB16_Msk   (0x1UL << CAN_F10R2_FB16_Pos)
     
    #define CAN_F10R2_FB16   CAN_F10R2_FB16_Msk
     
    #define CAN_F10R2_FB17_Pos   (17U)
     
    #define CAN_F10R2_FB17_Msk   (0x1UL << CAN_F10R2_FB17_Pos)
     
    #define CAN_F10R2_FB17   CAN_F10R2_FB17_Msk
     
    #define CAN_F10R2_FB18_Pos   (18U)
     
    #define CAN_F10R2_FB18_Msk   (0x1UL << CAN_F10R2_FB18_Pos)
     
    #define CAN_F10R2_FB18   CAN_F10R2_FB18_Msk
     
    #define CAN_F10R2_FB19_Pos   (19U)
     
    #define CAN_F10R2_FB19_Msk   (0x1UL << CAN_F10R2_FB19_Pos)
     
    #define CAN_F10R2_FB19   CAN_F10R2_FB19_Msk
     
    #define CAN_F10R2_FB20_Pos   (20U)
     
    #define CAN_F10R2_FB20_Msk   (0x1UL << CAN_F10R2_FB20_Pos)
     
    #define CAN_F10R2_FB20   CAN_F10R2_FB20_Msk
     
    #define CAN_F10R2_FB21_Pos   (21U)
     
    #define CAN_F10R2_FB21_Msk   (0x1UL << CAN_F10R2_FB21_Pos)
     
    #define CAN_F10R2_FB21   CAN_F10R2_FB21_Msk
     
    #define CAN_F10R2_FB22_Pos   (22U)
     
    #define CAN_F10R2_FB22_Msk   (0x1UL << CAN_F10R2_FB22_Pos)
     
    #define CAN_F10R2_FB22   CAN_F10R2_FB22_Msk
     
    #define CAN_F10R2_FB23_Pos   (23U)
     
    #define CAN_F10R2_FB23_Msk   (0x1UL << CAN_F10R2_FB23_Pos)
     
    #define CAN_F10R2_FB23   CAN_F10R2_FB23_Msk
     
    #define CAN_F10R2_FB24_Pos   (24U)
     
    #define CAN_F10R2_FB24_Msk   (0x1UL << CAN_F10R2_FB24_Pos)
     
    #define CAN_F10R2_FB24   CAN_F10R2_FB24_Msk
     
    #define CAN_F10R2_FB25_Pos   (25U)
     
    #define CAN_F10R2_FB25_Msk   (0x1UL << CAN_F10R2_FB25_Pos)
     
    #define CAN_F10R2_FB25   CAN_F10R2_FB25_Msk
     
    #define CAN_F10R2_FB26_Pos   (26U)
     
    #define CAN_F10R2_FB26_Msk   (0x1UL << CAN_F10R2_FB26_Pos)
     
    #define CAN_F10R2_FB26   CAN_F10R2_FB26_Msk
     
    #define CAN_F10R2_FB27_Pos   (27U)
     
    #define CAN_F10R2_FB27_Msk   (0x1UL << CAN_F10R2_FB27_Pos)
     
    #define CAN_F10R2_FB27   CAN_F10R2_FB27_Msk
     
    #define CAN_F10R2_FB28_Pos   (28U)
     
    #define CAN_F10R2_FB28_Msk   (0x1UL << CAN_F10R2_FB28_Pos)
     
    #define CAN_F10R2_FB28   CAN_F10R2_FB28_Msk
     
    #define CAN_F10R2_FB29_Pos   (29U)
     
    #define CAN_F10R2_FB29_Msk   (0x1UL << CAN_F10R2_FB29_Pos)
     
    #define CAN_F10R2_FB29   CAN_F10R2_FB29_Msk
     
    #define CAN_F10R2_FB30_Pos   (30U)
     
    #define CAN_F10R2_FB30_Msk   (0x1UL << CAN_F10R2_FB30_Pos)
     
    #define CAN_F10R2_FB30   CAN_F10R2_FB30_Msk
     
    #define CAN_F10R2_FB31_Pos   (31U)
     
    #define CAN_F10R2_FB31_Msk   (0x1UL << CAN_F10R2_FB31_Pos)
     
    #define CAN_F10R2_FB31   CAN_F10R2_FB31_Msk
     
    #define CAN_F11R2_FB0_Pos   (0U)
     
    #define CAN_F11R2_FB0_Msk   (0x1UL << CAN_F11R2_FB0_Pos)
     
    #define CAN_F11R2_FB0   CAN_F11R2_FB0_Msk
     
    #define CAN_F11R2_FB1_Pos   (1U)
     
    #define CAN_F11R2_FB1_Msk   (0x1UL << CAN_F11R2_FB1_Pos)
     
    #define CAN_F11R2_FB1   CAN_F11R2_FB1_Msk
     
    #define CAN_F11R2_FB2_Pos   (2U)
     
    #define CAN_F11R2_FB2_Msk   (0x1UL << CAN_F11R2_FB2_Pos)
     
    #define CAN_F11R2_FB2   CAN_F11R2_FB2_Msk
     
    #define CAN_F11R2_FB3_Pos   (3U)
     
    #define CAN_F11R2_FB3_Msk   (0x1UL << CAN_F11R2_FB3_Pos)
     
    #define CAN_F11R2_FB3   CAN_F11R2_FB3_Msk
     
    #define CAN_F11R2_FB4_Pos   (4U)
     
    #define CAN_F11R2_FB4_Msk   (0x1UL << CAN_F11R2_FB4_Pos)
     
    #define CAN_F11R2_FB4   CAN_F11R2_FB4_Msk
     
    #define CAN_F11R2_FB5_Pos   (5U)
     
    #define CAN_F11R2_FB5_Msk   (0x1UL << CAN_F11R2_FB5_Pos)
     
    #define CAN_F11R2_FB5   CAN_F11R2_FB5_Msk
     
    #define CAN_F11R2_FB6_Pos   (6U)
     
    #define CAN_F11R2_FB6_Msk   (0x1UL << CAN_F11R2_FB6_Pos)
     
    #define CAN_F11R2_FB6   CAN_F11R2_FB6_Msk
     
    #define CAN_F11R2_FB7_Pos   (7U)
     
    #define CAN_F11R2_FB7_Msk   (0x1UL << CAN_F11R2_FB7_Pos)
     
    #define CAN_F11R2_FB7   CAN_F11R2_FB7_Msk
     
    #define CAN_F11R2_FB8_Pos   (8U)
     
    #define CAN_F11R2_FB8_Msk   (0x1UL << CAN_F11R2_FB8_Pos)
     
    #define CAN_F11R2_FB8   CAN_F11R2_FB8_Msk
     
    #define CAN_F11R2_FB9_Pos   (9U)
     
    #define CAN_F11R2_FB9_Msk   (0x1UL << CAN_F11R2_FB9_Pos)
     
    #define CAN_F11R2_FB9   CAN_F11R2_FB9_Msk
     
    #define CAN_F11R2_FB10_Pos   (10U)
     
    #define CAN_F11R2_FB10_Msk   (0x1UL << CAN_F11R2_FB10_Pos)
     
    #define CAN_F11R2_FB10   CAN_F11R2_FB10_Msk
     
    #define CAN_F11R2_FB11_Pos   (11U)
     
    #define CAN_F11R2_FB11_Msk   (0x1UL << CAN_F11R2_FB11_Pos)
     
    #define CAN_F11R2_FB11   CAN_F11R2_FB11_Msk
     
    #define CAN_F11R2_FB12_Pos   (12U)
     
    #define CAN_F11R2_FB12_Msk   (0x1UL << CAN_F11R2_FB12_Pos)
     
    #define CAN_F11R2_FB12   CAN_F11R2_FB12_Msk
     
    #define CAN_F11R2_FB13_Pos   (13U)
     
    #define CAN_F11R2_FB13_Msk   (0x1UL << CAN_F11R2_FB13_Pos)
     
    #define CAN_F11R2_FB13   CAN_F11R2_FB13_Msk
     
    #define CAN_F11R2_FB14_Pos   (14U)
     
    #define CAN_F11R2_FB14_Msk   (0x1UL << CAN_F11R2_FB14_Pos)
     
    #define CAN_F11R2_FB14   CAN_F11R2_FB14_Msk
     
    #define CAN_F11R2_FB15_Pos   (15U)
     
    #define CAN_F11R2_FB15_Msk   (0x1UL << CAN_F11R2_FB15_Pos)
     
    #define CAN_F11R2_FB15   CAN_F11R2_FB15_Msk
     
    #define CAN_F11R2_FB16_Pos   (16U)
     
    #define CAN_F11R2_FB16_Msk   (0x1UL << CAN_F11R2_FB16_Pos)
     
    #define CAN_F11R2_FB16   CAN_F11R2_FB16_Msk
     
    #define CAN_F11R2_FB17_Pos   (17U)
     
    #define CAN_F11R2_FB17_Msk   (0x1UL << CAN_F11R2_FB17_Pos)
     
    #define CAN_F11R2_FB17   CAN_F11R2_FB17_Msk
     
    #define CAN_F11R2_FB18_Pos   (18U)
     
    #define CAN_F11R2_FB18_Msk   (0x1UL << CAN_F11R2_FB18_Pos)
     
    #define CAN_F11R2_FB18   CAN_F11R2_FB18_Msk
     
    #define CAN_F11R2_FB19_Pos   (19U)
     
    #define CAN_F11R2_FB19_Msk   (0x1UL << CAN_F11R2_FB19_Pos)
     
    #define CAN_F11R2_FB19   CAN_F11R2_FB19_Msk
     
    #define CAN_F11R2_FB20_Pos   (20U)
     
    #define CAN_F11R2_FB20_Msk   (0x1UL << CAN_F11R2_FB20_Pos)
     
    #define CAN_F11R2_FB20   CAN_F11R2_FB20_Msk
     
    #define CAN_F11R2_FB21_Pos   (21U)
     
    #define CAN_F11R2_FB21_Msk   (0x1UL << CAN_F11R2_FB21_Pos)
     
    #define CAN_F11R2_FB21   CAN_F11R2_FB21_Msk
     
    #define CAN_F11R2_FB22_Pos   (22U)
     
    #define CAN_F11R2_FB22_Msk   (0x1UL << CAN_F11R2_FB22_Pos)
     
    #define CAN_F11R2_FB22   CAN_F11R2_FB22_Msk
     
    #define CAN_F11R2_FB23_Pos   (23U)
     
    #define CAN_F11R2_FB23_Msk   (0x1UL << CAN_F11R2_FB23_Pos)
     
    #define CAN_F11R2_FB23   CAN_F11R2_FB23_Msk
     
    #define CAN_F11R2_FB24_Pos   (24U)
     
    #define CAN_F11R2_FB24_Msk   (0x1UL << CAN_F11R2_FB24_Pos)
     
    #define CAN_F11R2_FB24   CAN_F11R2_FB24_Msk
     
    #define CAN_F11R2_FB25_Pos   (25U)
     
    #define CAN_F11R2_FB25_Msk   (0x1UL << CAN_F11R2_FB25_Pos)
     
    #define CAN_F11R2_FB25   CAN_F11R2_FB25_Msk
     
    #define CAN_F11R2_FB26_Pos   (26U)
     
    #define CAN_F11R2_FB26_Msk   (0x1UL << CAN_F11R2_FB26_Pos)
     
    #define CAN_F11R2_FB26   CAN_F11R2_FB26_Msk
     
    #define CAN_F11R2_FB27_Pos   (27U)
     
    #define CAN_F11R2_FB27_Msk   (0x1UL << CAN_F11R2_FB27_Pos)
     
    #define CAN_F11R2_FB27   CAN_F11R2_FB27_Msk
     
    #define CAN_F11R2_FB28_Pos   (28U)
     
    #define CAN_F11R2_FB28_Msk   (0x1UL << CAN_F11R2_FB28_Pos)
     
    #define CAN_F11R2_FB28   CAN_F11R2_FB28_Msk
     
    #define CAN_F11R2_FB29_Pos   (29U)
     
    #define CAN_F11R2_FB29_Msk   (0x1UL << CAN_F11R2_FB29_Pos)
     
    #define CAN_F11R2_FB29   CAN_F11R2_FB29_Msk
     
    #define CAN_F11R2_FB30_Pos   (30U)
     
    #define CAN_F11R2_FB30_Msk   (0x1UL << CAN_F11R2_FB30_Pos)
     
    #define CAN_F11R2_FB30   CAN_F11R2_FB30_Msk
     
    #define CAN_F11R2_FB31_Pos   (31U)
     
    #define CAN_F11R2_FB31_Msk   (0x1UL << CAN_F11R2_FB31_Pos)
     
    #define CAN_F11R2_FB31   CAN_F11R2_FB31_Msk
     
    #define CAN_F12R2_FB0_Pos   (0U)
     
    #define CAN_F12R2_FB0_Msk   (0x1UL << CAN_F12R2_FB0_Pos)
     
    #define CAN_F12R2_FB0   CAN_F12R2_FB0_Msk
     
    #define CAN_F12R2_FB1_Pos   (1U)
     
    #define CAN_F12R2_FB1_Msk   (0x1UL << CAN_F12R2_FB1_Pos)
     
    #define CAN_F12R2_FB1   CAN_F12R2_FB1_Msk
     
    #define CAN_F12R2_FB2_Pos   (2U)
     
    #define CAN_F12R2_FB2_Msk   (0x1UL << CAN_F12R2_FB2_Pos)
     
    #define CAN_F12R2_FB2   CAN_F12R2_FB2_Msk
     
    #define CAN_F12R2_FB3_Pos   (3U)
     
    #define CAN_F12R2_FB3_Msk   (0x1UL << CAN_F12R2_FB3_Pos)
     
    #define CAN_F12R2_FB3   CAN_F12R2_FB3_Msk
     
    #define CAN_F12R2_FB4_Pos   (4U)
     
    #define CAN_F12R2_FB4_Msk   (0x1UL << CAN_F12R2_FB4_Pos)
     
    #define CAN_F12R2_FB4   CAN_F12R2_FB4_Msk
     
    #define CAN_F12R2_FB5_Pos   (5U)
     
    #define CAN_F12R2_FB5_Msk   (0x1UL << CAN_F12R2_FB5_Pos)
     
    #define CAN_F12R2_FB5   CAN_F12R2_FB5_Msk
     
    #define CAN_F12R2_FB6_Pos   (6U)
     
    #define CAN_F12R2_FB6_Msk   (0x1UL << CAN_F12R2_FB6_Pos)
     
    #define CAN_F12R2_FB6   CAN_F12R2_FB6_Msk
     
    #define CAN_F12R2_FB7_Pos   (7U)
     
    #define CAN_F12R2_FB7_Msk   (0x1UL << CAN_F12R2_FB7_Pos)
     
    #define CAN_F12R2_FB7   CAN_F12R2_FB7_Msk
     
    #define CAN_F12R2_FB8_Pos   (8U)
     
    #define CAN_F12R2_FB8_Msk   (0x1UL << CAN_F12R2_FB8_Pos)
     
    #define CAN_F12R2_FB8   CAN_F12R2_FB8_Msk
     
    #define CAN_F12R2_FB9_Pos   (9U)
     
    #define CAN_F12R2_FB9_Msk   (0x1UL << CAN_F12R2_FB9_Pos)
     
    #define CAN_F12R2_FB9   CAN_F12R2_FB9_Msk
     
    #define CAN_F12R2_FB10_Pos   (10U)
     
    #define CAN_F12R2_FB10_Msk   (0x1UL << CAN_F12R2_FB10_Pos)
     
    #define CAN_F12R2_FB10   CAN_F12R2_FB10_Msk
     
    #define CAN_F12R2_FB11_Pos   (11U)
     
    #define CAN_F12R2_FB11_Msk   (0x1UL << CAN_F12R2_FB11_Pos)
     
    #define CAN_F12R2_FB11   CAN_F12R2_FB11_Msk
     
    #define CAN_F12R2_FB12_Pos   (12U)
     
    #define CAN_F12R2_FB12_Msk   (0x1UL << CAN_F12R2_FB12_Pos)
     
    #define CAN_F12R2_FB12   CAN_F12R2_FB12_Msk
     
    #define CAN_F12R2_FB13_Pos   (13U)
     
    #define CAN_F12R2_FB13_Msk   (0x1UL << CAN_F12R2_FB13_Pos)
     
    #define CAN_F12R2_FB13   CAN_F12R2_FB13_Msk
     
    #define CAN_F12R2_FB14_Pos   (14U)
     
    #define CAN_F12R2_FB14_Msk   (0x1UL << CAN_F12R2_FB14_Pos)
     
    #define CAN_F12R2_FB14   CAN_F12R2_FB14_Msk
     
    #define CAN_F12R2_FB15_Pos   (15U)
     
    #define CAN_F12R2_FB15_Msk   (0x1UL << CAN_F12R2_FB15_Pos)
     
    #define CAN_F12R2_FB15   CAN_F12R2_FB15_Msk
     
    #define CAN_F12R2_FB16_Pos   (16U)
     
    #define CAN_F12R2_FB16_Msk   (0x1UL << CAN_F12R2_FB16_Pos)
     
    #define CAN_F12R2_FB16   CAN_F12R2_FB16_Msk
     
    #define CAN_F12R2_FB17_Pos   (17U)
     
    #define CAN_F12R2_FB17_Msk   (0x1UL << CAN_F12R2_FB17_Pos)
     
    #define CAN_F12R2_FB17   CAN_F12R2_FB17_Msk
     
    #define CAN_F12R2_FB18_Pos   (18U)
     
    #define CAN_F12R2_FB18_Msk   (0x1UL << CAN_F12R2_FB18_Pos)
     
    #define CAN_F12R2_FB18   CAN_F12R2_FB18_Msk
     
    #define CAN_F12R2_FB19_Pos   (19U)
     
    #define CAN_F12R2_FB19_Msk   (0x1UL << CAN_F12R2_FB19_Pos)
     
    #define CAN_F12R2_FB19   CAN_F12R2_FB19_Msk
     
    #define CAN_F12R2_FB20_Pos   (20U)
     
    #define CAN_F12R2_FB20_Msk   (0x1UL << CAN_F12R2_FB20_Pos)
     
    #define CAN_F12R2_FB20   CAN_F12R2_FB20_Msk
     
    #define CAN_F12R2_FB21_Pos   (21U)
     
    #define CAN_F12R2_FB21_Msk   (0x1UL << CAN_F12R2_FB21_Pos)
     
    #define CAN_F12R2_FB21   CAN_F12R2_FB21_Msk
     
    #define CAN_F12R2_FB22_Pos   (22U)
     
    #define CAN_F12R2_FB22_Msk   (0x1UL << CAN_F12R2_FB22_Pos)
     
    #define CAN_F12R2_FB22   CAN_F12R2_FB22_Msk
     
    #define CAN_F12R2_FB23_Pos   (23U)
     
    #define CAN_F12R2_FB23_Msk   (0x1UL << CAN_F12R2_FB23_Pos)
     
    #define CAN_F12R2_FB23   CAN_F12R2_FB23_Msk
     
    #define CAN_F12R2_FB24_Pos   (24U)
     
    #define CAN_F12R2_FB24_Msk   (0x1UL << CAN_F12R2_FB24_Pos)
     
    #define CAN_F12R2_FB24   CAN_F12R2_FB24_Msk
     
    #define CAN_F12R2_FB25_Pos   (25U)
     
    #define CAN_F12R2_FB25_Msk   (0x1UL << CAN_F12R2_FB25_Pos)
     
    #define CAN_F12R2_FB25   CAN_F12R2_FB25_Msk
     
    #define CAN_F12R2_FB26_Pos   (26U)
     
    #define CAN_F12R2_FB26_Msk   (0x1UL << CAN_F12R2_FB26_Pos)
     
    #define CAN_F12R2_FB26   CAN_F12R2_FB26_Msk
     
    #define CAN_F12R2_FB27_Pos   (27U)
     
    #define CAN_F12R2_FB27_Msk   (0x1UL << CAN_F12R2_FB27_Pos)
     
    #define CAN_F12R2_FB27   CAN_F12R2_FB27_Msk
     
    #define CAN_F12R2_FB28_Pos   (28U)
     
    #define CAN_F12R2_FB28_Msk   (0x1UL << CAN_F12R2_FB28_Pos)
     
    #define CAN_F12R2_FB28   CAN_F12R2_FB28_Msk
     
    #define CAN_F12R2_FB29_Pos   (29U)
     
    #define CAN_F12R2_FB29_Msk   (0x1UL << CAN_F12R2_FB29_Pos)
     
    #define CAN_F12R2_FB29   CAN_F12R2_FB29_Msk
     
    #define CAN_F12R2_FB30_Pos   (30U)
     
    #define CAN_F12R2_FB30_Msk   (0x1UL << CAN_F12R2_FB30_Pos)
     
    #define CAN_F12R2_FB30   CAN_F12R2_FB30_Msk
     
    #define CAN_F12R2_FB31_Pos   (31U)
     
    #define CAN_F12R2_FB31_Msk   (0x1UL << CAN_F12R2_FB31_Pos)
     
    #define CAN_F12R2_FB31   CAN_F12R2_FB31_Msk
     
    #define CAN_F13R2_FB0_Pos   (0U)
     
    #define CAN_F13R2_FB0_Msk   (0x1UL << CAN_F13R2_FB0_Pos)
     
    #define CAN_F13R2_FB0   CAN_F13R2_FB0_Msk
     
    #define CAN_F13R2_FB1_Pos   (1U)
     
    #define CAN_F13R2_FB1_Msk   (0x1UL << CAN_F13R2_FB1_Pos)
     
    #define CAN_F13R2_FB1   CAN_F13R2_FB1_Msk
     
    #define CAN_F13R2_FB2_Pos   (2U)
     
    #define CAN_F13R2_FB2_Msk   (0x1UL << CAN_F13R2_FB2_Pos)
     
    #define CAN_F13R2_FB2   CAN_F13R2_FB2_Msk
     
    #define CAN_F13R2_FB3_Pos   (3U)
     
    #define CAN_F13R2_FB3_Msk   (0x1UL << CAN_F13R2_FB3_Pos)
     
    #define CAN_F13R2_FB3   CAN_F13R2_FB3_Msk
     
    #define CAN_F13R2_FB4_Pos   (4U)
     
    #define CAN_F13R2_FB4_Msk   (0x1UL << CAN_F13R2_FB4_Pos)
     
    #define CAN_F13R2_FB4   CAN_F13R2_FB4_Msk
     
    #define CAN_F13R2_FB5_Pos   (5U)
     
    #define CAN_F13R2_FB5_Msk   (0x1UL << CAN_F13R2_FB5_Pos)
     
    #define CAN_F13R2_FB5   CAN_F13R2_FB5_Msk
     
    #define CAN_F13R2_FB6_Pos   (6U)
     
    #define CAN_F13R2_FB6_Msk   (0x1UL << CAN_F13R2_FB6_Pos)
     
    #define CAN_F13R2_FB6   CAN_F13R2_FB6_Msk
     
    #define CAN_F13R2_FB7_Pos   (7U)
     
    #define CAN_F13R2_FB7_Msk   (0x1UL << CAN_F13R2_FB7_Pos)
     
    #define CAN_F13R2_FB7   CAN_F13R2_FB7_Msk
     
    #define CAN_F13R2_FB8_Pos   (8U)
     
    #define CAN_F13R2_FB8_Msk   (0x1UL << CAN_F13R2_FB8_Pos)
     
    #define CAN_F13R2_FB8   CAN_F13R2_FB8_Msk
     
    #define CAN_F13R2_FB9_Pos   (9U)
     
    #define CAN_F13R2_FB9_Msk   (0x1UL << CAN_F13R2_FB9_Pos)
     
    #define CAN_F13R2_FB9   CAN_F13R2_FB9_Msk
     
    #define CAN_F13R2_FB10_Pos   (10U)
     
    #define CAN_F13R2_FB10_Msk   (0x1UL << CAN_F13R2_FB10_Pos)
     
    #define CAN_F13R2_FB10   CAN_F13R2_FB10_Msk
     
    #define CAN_F13R2_FB11_Pos   (11U)
     
    #define CAN_F13R2_FB11_Msk   (0x1UL << CAN_F13R2_FB11_Pos)
     
    #define CAN_F13R2_FB11   CAN_F13R2_FB11_Msk
     
    #define CAN_F13R2_FB12_Pos   (12U)
     
    #define CAN_F13R2_FB12_Msk   (0x1UL << CAN_F13R2_FB12_Pos)
     
    #define CAN_F13R2_FB12   CAN_F13R2_FB12_Msk
     
    #define CAN_F13R2_FB13_Pos   (13U)
     
    #define CAN_F13R2_FB13_Msk   (0x1UL << CAN_F13R2_FB13_Pos)
     
    #define CAN_F13R2_FB13   CAN_F13R2_FB13_Msk
     
    #define CAN_F13R2_FB14_Pos   (14U)
     
    #define CAN_F13R2_FB14_Msk   (0x1UL << CAN_F13R2_FB14_Pos)
     
    #define CAN_F13R2_FB14   CAN_F13R2_FB14_Msk
     
    #define CAN_F13R2_FB15_Pos   (15U)
     
    #define CAN_F13R2_FB15_Msk   (0x1UL << CAN_F13R2_FB15_Pos)
     
    #define CAN_F13R2_FB15   CAN_F13R2_FB15_Msk
     
    #define CAN_F13R2_FB16_Pos   (16U)
     
    #define CAN_F13R2_FB16_Msk   (0x1UL << CAN_F13R2_FB16_Pos)
     
    #define CAN_F13R2_FB16   CAN_F13R2_FB16_Msk
     
    #define CAN_F13R2_FB17_Pos   (17U)
     
    #define CAN_F13R2_FB17_Msk   (0x1UL << CAN_F13R2_FB17_Pos)
     
    #define CAN_F13R2_FB17   CAN_F13R2_FB17_Msk
     
    #define CAN_F13R2_FB18_Pos   (18U)
     
    #define CAN_F13R2_FB18_Msk   (0x1UL << CAN_F13R2_FB18_Pos)
     
    #define CAN_F13R2_FB18   CAN_F13R2_FB18_Msk
     
    #define CAN_F13R2_FB19_Pos   (19U)
     
    #define CAN_F13R2_FB19_Msk   (0x1UL << CAN_F13R2_FB19_Pos)
     
    #define CAN_F13R2_FB19   CAN_F13R2_FB19_Msk
     
    #define CAN_F13R2_FB20_Pos   (20U)
     
    #define CAN_F13R2_FB20_Msk   (0x1UL << CAN_F13R2_FB20_Pos)
     
    #define CAN_F13R2_FB20   CAN_F13R2_FB20_Msk
     
    #define CAN_F13R2_FB21_Pos   (21U)
     
    #define CAN_F13R2_FB21_Msk   (0x1UL << CAN_F13R2_FB21_Pos)
     
    #define CAN_F13R2_FB21   CAN_F13R2_FB21_Msk
     
    #define CAN_F13R2_FB22_Pos   (22U)
     
    #define CAN_F13R2_FB22_Msk   (0x1UL << CAN_F13R2_FB22_Pos)
     
    #define CAN_F13R2_FB22   CAN_F13R2_FB22_Msk
     
    #define CAN_F13R2_FB23_Pos   (23U)
     
    #define CAN_F13R2_FB23_Msk   (0x1UL << CAN_F13R2_FB23_Pos)
     
    #define CAN_F13R2_FB23   CAN_F13R2_FB23_Msk
     
    #define CAN_F13R2_FB24_Pos   (24U)
     
    #define CAN_F13R2_FB24_Msk   (0x1UL << CAN_F13R2_FB24_Pos)
     
    #define CAN_F13R2_FB24   CAN_F13R2_FB24_Msk
     
    #define CAN_F13R2_FB25_Pos   (25U)
     
    #define CAN_F13R2_FB25_Msk   (0x1UL << CAN_F13R2_FB25_Pos)
     
    #define CAN_F13R2_FB25   CAN_F13R2_FB25_Msk
     
    #define CAN_F13R2_FB26_Pos   (26U)
     
    #define CAN_F13R2_FB26_Msk   (0x1UL << CAN_F13R2_FB26_Pos)
     
    #define CAN_F13R2_FB26   CAN_F13R2_FB26_Msk
     
    #define CAN_F13R2_FB27_Pos   (27U)
     
    #define CAN_F13R2_FB27_Msk   (0x1UL << CAN_F13R2_FB27_Pos)
     
    #define CAN_F13R2_FB27   CAN_F13R2_FB27_Msk
     
    #define CAN_F13R2_FB28_Pos   (28U)
     
    #define CAN_F13R2_FB28_Msk   (0x1UL << CAN_F13R2_FB28_Pos)
     
    #define CAN_F13R2_FB28   CAN_F13R2_FB28_Msk
     
    #define CAN_F13R2_FB29_Pos   (29U)
     
    #define CAN_F13R2_FB29_Msk   (0x1UL << CAN_F13R2_FB29_Pos)
     
    #define CAN_F13R2_FB29   CAN_F13R2_FB29_Msk
     
    #define CAN_F13R2_FB30_Pos   (30U)
     
    #define CAN_F13R2_FB30_Msk   (0x1UL << CAN_F13R2_FB30_Pos)
     
    #define CAN_F13R2_FB30   CAN_F13R2_FB30_Msk
     
    #define CAN_F13R2_FB31_Pos   (31U)
     
    #define CAN_F13R2_FB31_Msk   (0x1UL << CAN_F13R2_FB31_Pos)
     
    #define CAN_F13R2_FB31   CAN_F13R2_FB31_Msk
     
    #define CRC_DR_DR_Pos   (0U)
     
    #define CRC_DR_DR_Msk   (0xFFFFFFFFUL << CRC_DR_DR_Pos)
     
    #define CRC_DR_DR   CRC_DR_DR_Msk
     
    #define CRC_IDR_IDR_Pos   (0U)
     
    #define CRC_IDR_IDR_Msk   (0xFFUL << CRC_IDR_IDR_Pos)
     
    #define CRC_IDR_IDR   CRC_IDR_IDR_Msk
     
    #define CRC_CR_RESET_Pos   (0U)
     
    #define CRC_CR_RESET_Msk   (0x1UL << CRC_CR_RESET_Pos)
     
    #define CRC_CR_RESET   CRC_CR_RESET_Msk
     
    #define DAC_CHANNEL2_SUPPORT
     
    #define DAC_CR_EN1_Pos   (0U)
     
    #define DAC_CR_EN1_Msk   (0x1UL << DAC_CR_EN1_Pos)
     
    #define DAC_CR_EN1   DAC_CR_EN1_Msk
     
    #define DAC_CR_BOFF1_Pos   (1U)
     
    #define DAC_CR_BOFF1_Msk   (0x1UL << DAC_CR_BOFF1_Pos)
     
    #define DAC_CR_BOFF1   DAC_CR_BOFF1_Msk
     
    #define DAC_CR_TEN1_Pos   (2U)
     
    #define DAC_CR_TEN1_Msk   (0x1UL << DAC_CR_TEN1_Pos)
     
    #define DAC_CR_TEN1   DAC_CR_TEN1_Msk
     
    #define DAC_CR_TSEL1_Pos   (3U)
     
    #define DAC_CR_TSEL1_Msk   (0x7UL << DAC_CR_TSEL1_Pos)
     
    #define DAC_CR_TSEL1   DAC_CR_TSEL1_Msk
     
    #define DAC_CR_TSEL1_0   (0x1UL << DAC_CR_TSEL1_Pos)
     
    #define DAC_CR_TSEL1_1   (0x2UL << DAC_CR_TSEL1_Pos)
     
    #define DAC_CR_TSEL1_2   (0x4UL << DAC_CR_TSEL1_Pos)
     
    #define DAC_CR_WAVE1_Pos   (6U)
     
    #define DAC_CR_WAVE1_Msk   (0x3UL << DAC_CR_WAVE1_Pos)
     
    #define DAC_CR_WAVE1   DAC_CR_WAVE1_Msk
     
    #define DAC_CR_WAVE1_0   (0x1UL << DAC_CR_WAVE1_Pos)
     
    #define DAC_CR_WAVE1_1   (0x2UL << DAC_CR_WAVE1_Pos)
     
    #define DAC_CR_MAMP1_Pos   (8U)
     
    #define DAC_CR_MAMP1_Msk   (0xFUL << DAC_CR_MAMP1_Pos)
     
    #define DAC_CR_MAMP1   DAC_CR_MAMP1_Msk
     
    #define DAC_CR_MAMP1_0   (0x1UL << DAC_CR_MAMP1_Pos)
     
    #define DAC_CR_MAMP1_1   (0x2UL << DAC_CR_MAMP1_Pos)
     
    #define DAC_CR_MAMP1_2   (0x4UL << DAC_CR_MAMP1_Pos)
     
    #define DAC_CR_MAMP1_3   (0x8UL << DAC_CR_MAMP1_Pos)
     
    #define DAC_CR_DMAEN1_Pos   (12U)
     
    #define DAC_CR_DMAEN1_Msk   (0x1UL << DAC_CR_DMAEN1_Pos)
     
    #define DAC_CR_DMAEN1   DAC_CR_DMAEN1_Msk
     
    #define DAC_CR_DMAUDRIE1_Pos   (13U)
     
    #define DAC_CR_DMAUDRIE1_Msk   (0x1UL << DAC_CR_DMAUDRIE1_Pos)
     
    #define DAC_CR_DMAUDRIE1   DAC_CR_DMAUDRIE1_Msk
     
    #define DAC_CR_EN2_Pos   (16U)
     
    #define DAC_CR_EN2_Msk   (0x1UL << DAC_CR_EN2_Pos)
     
    #define DAC_CR_EN2   DAC_CR_EN2_Msk
     
    #define DAC_CR_BOFF2_Pos   (17U)
     
    #define DAC_CR_BOFF2_Msk   (0x1UL << DAC_CR_BOFF2_Pos)
     
    #define DAC_CR_BOFF2   DAC_CR_BOFF2_Msk
     
    #define DAC_CR_TEN2_Pos   (18U)
     
    #define DAC_CR_TEN2_Msk   (0x1UL << DAC_CR_TEN2_Pos)
     
    #define DAC_CR_TEN2   DAC_CR_TEN2_Msk
     
    #define DAC_CR_TSEL2_Pos   (19U)
     
    #define DAC_CR_TSEL2_Msk   (0x7UL << DAC_CR_TSEL2_Pos)
     
    #define DAC_CR_TSEL2   DAC_CR_TSEL2_Msk
     
    #define DAC_CR_TSEL2_0   (0x1UL << DAC_CR_TSEL2_Pos)
     
    #define DAC_CR_TSEL2_1   (0x2UL << DAC_CR_TSEL2_Pos)
     
    #define DAC_CR_TSEL2_2   (0x4UL << DAC_CR_TSEL2_Pos)
     
    #define DAC_CR_WAVE2_Pos   (22U)
     
    #define DAC_CR_WAVE2_Msk   (0x3UL << DAC_CR_WAVE2_Pos)
     
    #define DAC_CR_WAVE2   DAC_CR_WAVE2_Msk
     
    #define DAC_CR_WAVE2_0   (0x1UL << DAC_CR_WAVE2_Pos)
     
    #define DAC_CR_WAVE2_1   (0x2UL << DAC_CR_WAVE2_Pos)
     
    #define DAC_CR_MAMP2_Pos   (24U)
     
    #define DAC_CR_MAMP2_Msk   (0xFUL << DAC_CR_MAMP2_Pos)
     
    #define DAC_CR_MAMP2   DAC_CR_MAMP2_Msk
     
    #define DAC_CR_MAMP2_0   (0x1UL << DAC_CR_MAMP2_Pos)
     
    #define DAC_CR_MAMP2_1   (0x2UL << DAC_CR_MAMP2_Pos)
     
    #define DAC_CR_MAMP2_2   (0x4UL << DAC_CR_MAMP2_Pos)
     
    #define DAC_CR_MAMP2_3   (0x8UL << DAC_CR_MAMP2_Pos)
     
    #define DAC_CR_DMAEN2_Pos   (28U)
     
    #define DAC_CR_DMAEN2_Msk   (0x1UL << DAC_CR_DMAEN2_Pos)
     
    #define DAC_CR_DMAEN2   DAC_CR_DMAEN2_Msk
     
    #define DAC_CR_DMAUDRIE2_Pos   (29U)
     
    #define DAC_CR_DMAUDRIE2_Msk   (0x1UL << DAC_CR_DMAUDRIE2_Pos)
     
    #define DAC_CR_DMAUDRIE2   DAC_CR_DMAUDRIE2_Msk
     
    #define DAC_SWTRIGR_SWTRIG1_Pos   (0U)
     
    #define DAC_SWTRIGR_SWTRIG1_Msk   (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos)
     
    #define DAC_SWTRIGR_SWTRIG1   DAC_SWTRIGR_SWTRIG1_Msk
     
    #define DAC_SWTRIGR_SWTRIG2_Pos   (1U)
     
    #define DAC_SWTRIGR_SWTRIG2_Msk   (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos)
     
    #define DAC_SWTRIGR_SWTRIG2   DAC_SWTRIGR_SWTRIG2_Msk
     
    #define DAC_DHR12R1_DACC1DHR_Pos   (0U)
     
    #define DAC_DHR12R1_DACC1DHR_Msk   (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos)
     
    #define DAC_DHR12R1_DACC1DHR   DAC_DHR12R1_DACC1DHR_Msk
     
    #define DAC_DHR12L1_DACC1DHR_Pos   (4U)
     
    #define DAC_DHR12L1_DACC1DHR_Msk   (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos)
     
    #define DAC_DHR12L1_DACC1DHR   DAC_DHR12L1_DACC1DHR_Msk
     
    #define DAC_DHR8R1_DACC1DHR_Pos   (0U)
     
    #define DAC_DHR8R1_DACC1DHR_Msk   (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos)
     
    #define DAC_DHR8R1_DACC1DHR   DAC_DHR8R1_DACC1DHR_Msk
     
    #define DAC_DHR12R2_DACC2DHR_Pos   (0U)
     
    #define DAC_DHR12R2_DACC2DHR_Msk   (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos)
     
    #define DAC_DHR12R2_DACC2DHR   DAC_DHR12R2_DACC2DHR_Msk
     
    #define DAC_DHR12L2_DACC2DHR_Pos   (4U)
     
    #define DAC_DHR12L2_DACC2DHR_Msk   (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos)
     
    #define DAC_DHR12L2_DACC2DHR   DAC_DHR12L2_DACC2DHR_Msk
     
    #define DAC_DHR8R2_DACC2DHR_Pos   (0U)
     
    #define DAC_DHR8R2_DACC2DHR_Msk   (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos)
     
    #define DAC_DHR8R2_DACC2DHR   DAC_DHR8R2_DACC2DHR_Msk
     
    #define DAC_DHR12RD_DACC1DHR_Pos   (0U)
     
    #define DAC_DHR12RD_DACC1DHR_Msk   (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos)
     
    #define DAC_DHR12RD_DACC1DHR   DAC_DHR12RD_DACC1DHR_Msk
     
    #define DAC_DHR12RD_DACC2DHR_Pos   (16U)
     
    #define DAC_DHR12RD_DACC2DHR_Msk   (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos)
     
    #define DAC_DHR12RD_DACC2DHR   DAC_DHR12RD_DACC2DHR_Msk
     
    #define DAC_DHR12LD_DACC1DHR_Pos   (4U)
     
    #define DAC_DHR12LD_DACC1DHR_Msk   (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos)
     
    #define DAC_DHR12LD_DACC1DHR   DAC_DHR12LD_DACC1DHR_Msk
     
    #define DAC_DHR12LD_DACC2DHR_Pos   (20U)
     
    #define DAC_DHR12LD_DACC2DHR_Msk   (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos)
     
    #define DAC_DHR12LD_DACC2DHR   DAC_DHR12LD_DACC2DHR_Msk
     
    #define DAC_DHR8RD_DACC1DHR_Pos   (0U)
     
    #define DAC_DHR8RD_DACC1DHR_Msk   (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos)
     
    #define DAC_DHR8RD_DACC1DHR   DAC_DHR8RD_DACC1DHR_Msk
     
    #define DAC_DHR8RD_DACC2DHR_Pos   (8U)
     
    #define DAC_DHR8RD_DACC2DHR_Msk   (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos)
     
    #define DAC_DHR8RD_DACC2DHR   DAC_DHR8RD_DACC2DHR_Msk
     
    #define DAC_DOR1_DACC1DOR_Pos   (0U)
     
    #define DAC_DOR1_DACC1DOR_Msk   (0xFFFUL << DAC_DOR1_DACC1DOR_Pos)
     
    #define DAC_DOR1_DACC1DOR   DAC_DOR1_DACC1DOR_Msk
     
    #define DAC_DOR2_DACC2DOR_Pos   (0U)
     
    #define DAC_DOR2_DACC2DOR_Msk   (0xFFFUL << DAC_DOR2_DACC2DOR_Pos)
     
    #define DAC_DOR2_DACC2DOR   DAC_DOR2_DACC2DOR_Msk
     
    #define DAC_SR_DMAUDR1_Pos   (13U)
     
    #define DAC_SR_DMAUDR1_Msk   (0x1UL << DAC_SR_DMAUDR1_Pos)
     
    #define DAC_SR_DMAUDR1   DAC_SR_DMAUDR1_Msk
     
    #define DAC_SR_DMAUDR2_Pos   (29U)
     
    #define DAC_SR_DMAUDR2_Msk   (0x1UL << DAC_SR_DMAUDR2_Pos)
     
    #define DAC_SR_DMAUDR2   DAC_SR_DMAUDR2_Msk
     
    #define DCMI_CR_CAPTURE_Pos   (0U)
     
    #define DCMI_CR_CAPTURE_Msk   (0x1UL << DCMI_CR_CAPTURE_Pos)
     
    #define DCMI_CR_CAPTURE   DCMI_CR_CAPTURE_Msk
     
    #define DCMI_CR_CM_Pos   (1U)
     
    #define DCMI_CR_CM_Msk   (0x1UL << DCMI_CR_CM_Pos)
     
    #define DCMI_CR_CM   DCMI_CR_CM_Msk
     
    #define DCMI_CR_CROP_Pos   (2U)
     
    #define DCMI_CR_CROP_Msk   (0x1UL << DCMI_CR_CROP_Pos)
     
    #define DCMI_CR_CROP   DCMI_CR_CROP_Msk
     
    #define DCMI_CR_JPEG_Pos   (3U)
     
    #define DCMI_CR_JPEG_Msk   (0x1UL << DCMI_CR_JPEG_Pos)
     
    #define DCMI_CR_JPEG   DCMI_CR_JPEG_Msk
     
    #define DCMI_CR_ESS_Pos   (4U)
     
    #define DCMI_CR_ESS_Msk   (0x1UL << DCMI_CR_ESS_Pos)
     
    #define DCMI_CR_ESS   DCMI_CR_ESS_Msk
     
    #define DCMI_CR_PCKPOL_Pos   (5U)
     
    #define DCMI_CR_PCKPOL_Msk   (0x1UL << DCMI_CR_PCKPOL_Pos)
     
    #define DCMI_CR_PCKPOL   DCMI_CR_PCKPOL_Msk
     
    #define DCMI_CR_HSPOL_Pos   (6U)
     
    #define DCMI_CR_HSPOL_Msk   (0x1UL << DCMI_CR_HSPOL_Pos)
     
    #define DCMI_CR_HSPOL   DCMI_CR_HSPOL_Msk
     
    #define DCMI_CR_VSPOL_Pos   (7U)
     
    #define DCMI_CR_VSPOL_Msk   (0x1UL << DCMI_CR_VSPOL_Pos)
     
    #define DCMI_CR_VSPOL   DCMI_CR_VSPOL_Msk
     
    #define DCMI_CR_FCRC_0   0x00000100U
     
    #define DCMI_CR_FCRC_1   0x00000200U
     
    #define DCMI_CR_EDM_0   0x00000400U
     
    #define DCMI_CR_EDM_1   0x00000800U
     
    #define DCMI_CR_CRE_Pos   (12U)
     
    #define DCMI_CR_CRE_Msk   (0x1UL << DCMI_CR_CRE_Pos)
     
    #define DCMI_CR_CRE   DCMI_CR_CRE_Msk
     
    #define DCMI_CR_ENABLE_Pos   (14U)
     
    #define DCMI_CR_ENABLE_Msk   (0x1UL << DCMI_CR_ENABLE_Pos)
     
    #define DCMI_CR_ENABLE   DCMI_CR_ENABLE_Msk
     
    #define DCMI_SR_HSYNC_Pos   (0U)
     
    #define DCMI_SR_HSYNC_Msk   (0x1UL << DCMI_SR_HSYNC_Pos)
     
    #define DCMI_SR_HSYNC   DCMI_SR_HSYNC_Msk
     
    #define DCMI_SR_VSYNC_Pos   (1U)
     
    #define DCMI_SR_VSYNC_Msk   (0x1UL << DCMI_SR_VSYNC_Pos)
     
    #define DCMI_SR_VSYNC   DCMI_SR_VSYNC_Msk
     
    #define DCMI_SR_FNE_Pos   (2U)
     
    #define DCMI_SR_FNE_Msk   (0x1UL << DCMI_SR_FNE_Pos)
     
    #define DCMI_SR_FNE   DCMI_SR_FNE_Msk
     
    #define DCMI_RIS_FRAME_RIS_Pos   (0U)
     
    #define DCMI_RIS_FRAME_RIS_Msk   (0x1UL << DCMI_RIS_FRAME_RIS_Pos)
     
    #define DCMI_RIS_FRAME_RIS   DCMI_RIS_FRAME_RIS_Msk
     
    #define DCMI_RIS_OVR_RIS_Pos   (1U)
     
    #define DCMI_RIS_OVR_RIS_Msk   (0x1UL << DCMI_RIS_OVR_RIS_Pos)
     
    #define DCMI_RIS_OVR_RIS   DCMI_RIS_OVR_RIS_Msk
     
    #define DCMI_RIS_ERR_RIS_Pos   (2U)
     
    #define DCMI_RIS_ERR_RIS_Msk   (0x1UL << DCMI_RIS_ERR_RIS_Pos)
     
    #define DCMI_RIS_ERR_RIS   DCMI_RIS_ERR_RIS_Msk
     
    #define DCMI_RIS_VSYNC_RIS_Pos   (3U)
     
    #define DCMI_RIS_VSYNC_RIS_Msk   (0x1UL << DCMI_RIS_VSYNC_RIS_Pos)
     
    #define DCMI_RIS_VSYNC_RIS   DCMI_RIS_VSYNC_RIS_Msk
     
    #define DCMI_RIS_LINE_RIS_Pos   (4U)
     
    #define DCMI_RIS_LINE_RIS_Msk   (0x1UL << DCMI_RIS_LINE_RIS_Pos)
     
    #define DCMI_RIS_LINE_RIS   DCMI_RIS_LINE_RIS_Msk
     
    #define DCMI_RISR_FRAME_RIS   DCMI_RIS_FRAME_RIS
     
    #define DCMI_RISR_OVR_RIS   DCMI_RIS_OVR_RIS
     
    #define DCMI_RISR_ERR_RIS   DCMI_RIS_ERR_RIS
     
    #define DCMI_RISR_VSYNC_RIS   DCMI_RIS_VSYNC_RIS
     
    #define DCMI_RISR_LINE_RIS   DCMI_RIS_LINE_RIS
     
    #define DCMI_RISR_OVF_RIS   DCMI_RIS_OVR_RIS
     
    #define DCMI_IER_FRAME_IE_Pos   (0U)
     
    #define DCMI_IER_FRAME_IE_Msk   (0x1UL << DCMI_IER_FRAME_IE_Pos)
     
    #define DCMI_IER_FRAME_IE   DCMI_IER_FRAME_IE_Msk
     
    #define DCMI_IER_OVR_IE_Pos   (1U)
     
    #define DCMI_IER_OVR_IE_Msk   (0x1UL << DCMI_IER_OVR_IE_Pos)
     
    #define DCMI_IER_OVR_IE   DCMI_IER_OVR_IE_Msk
     
    #define DCMI_IER_ERR_IE_Pos   (2U)
     
    #define DCMI_IER_ERR_IE_Msk   (0x1UL << DCMI_IER_ERR_IE_Pos)
     
    #define DCMI_IER_ERR_IE   DCMI_IER_ERR_IE_Msk
     
    #define DCMI_IER_VSYNC_IE_Pos   (3U)
     
    #define DCMI_IER_VSYNC_IE_Msk   (0x1UL << DCMI_IER_VSYNC_IE_Pos)
     
    #define DCMI_IER_VSYNC_IE   DCMI_IER_VSYNC_IE_Msk
     
    #define DCMI_IER_LINE_IE_Pos   (4U)
     
    #define DCMI_IER_LINE_IE_Msk   (0x1UL << DCMI_IER_LINE_IE_Pos)
     
    #define DCMI_IER_LINE_IE   DCMI_IER_LINE_IE_Msk
     
    #define DCMI_IER_OVF_IE   DCMI_IER_OVR_IE
     
    #define DCMI_MIS_FRAME_MIS_Pos   (0U)
     
    #define DCMI_MIS_FRAME_MIS_Msk   (0x1UL << DCMI_MIS_FRAME_MIS_Pos)
     
    #define DCMI_MIS_FRAME_MIS   DCMI_MIS_FRAME_MIS_Msk
     
    #define DCMI_MIS_OVR_MIS_Pos   (1U)
     
    #define DCMI_MIS_OVR_MIS_Msk   (0x1UL << DCMI_MIS_OVR_MIS_Pos)
     
    #define DCMI_MIS_OVR_MIS   DCMI_MIS_OVR_MIS_Msk
     
    #define DCMI_MIS_ERR_MIS_Pos   (2U)
     
    #define DCMI_MIS_ERR_MIS_Msk   (0x1UL << DCMI_MIS_ERR_MIS_Pos)
     
    #define DCMI_MIS_ERR_MIS   DCMI_MIS_ERR_MIS_Msk
     
    #define DCMI_MIS_VSYNC_MIS_Pos   (3U)
     
    #define DCMI_MIS_VSYNC_MIS_Msk   (0x1UL << DCMI_MIS_VSYNC_MIS_Pos)
     
    #define DCMI_MIS_VSYNC_MIS   DCMI_MIS_VSYNC_MIS_Msk
     
    #define DCMI_MIS_LINE_MIS_Pos   (4U)
     
    #define DCMI_MIS_LINE_MIS_Msk   (0x1UL << DCMI_MIS_LINE_MIS_Pos)
     
    #define DCMI_MIS_LINE_MIS   DCMI_MIS_LINE_MIS_Msk
     
    #define DCMI_MISR_FRAME_MIS   DCMI_MIS_FRAME_MIS
     
    #define DCMI_MISR_OVF_MIS   DCMI_MIS_OVR_MIS
     
    #define DCMI_MISR_ERR_MIS   DCMI_MIS_ERR_MIS
     
    #define DCMI_MISR_VSYNC_MIS   DCMI_MIS_VSYNC_MIS
     
    #define DCMI_MISR_LINE_MIS   DCMI_MIS_LINE_MIS
     
    #define DCMI_ICR_FRAME_ISC_Pos   (0U)
     
    #define DCMI_ICR_FRAME_ISC_Msk   (0x1UL << DCMI_ICR_FRAME_ISC_Pos)
     
    #define DCMI_ICR_FRAME_ISC   DCMI_ICR_FRAME_ISC_Msk
     
    #define DCMI_ICR_OVR_ISC_Pos   (1U)
     
    #define DCMI_ICR_OVR_ISC_Msk   (0x1UL << DCMI_ICR_OVR_ISC_Pos)
     
    #define DCMI_ICR_OVR_ISC   DCMI_ICR_OVR_ISC_Msk
     
    #define DCMI_ICR_ERR_ISC_Pos   (2U)
     
    #define DCMI_ICR_ERR_ISC_Msk   (0x1UL << DCMI_ICR_ERR_ISC_Pos)
     
    #define DCMI_ICR_ERR_ISC   DCMI_ICR_ERR_ISC_Msk
     
    #define DCMI_ICR_VSYNC_ISC_Pos   (3U)
     
    #define DCMI_ICR_VSYNC_ISC_Msk   (0x1UL << DCMI_ICR_VSYNC_ISC_Pos)
     
    #define DCMI_ICR_VSYNC_ISC   DCMI_ICR_VSYNC_ISC_Msk
     
    #define DCMI_ICR_LINE_ISC_Pos   (4U)
     
    #define DCMI_ICR_LINE_ISC_Msk   (0x1UL << DCMI_ICR_LINE_ISC_Pos)
     
    #define DCMI_ICR_LINE_ISC   DCMI_ICR_LINE_ISC_Msk
     
    #define DCMI_ICR_OVF_ISC   DCMI_ICR_OVR_ISC
     
    #define DCMI_ESCR_FSC_Pos   (0U)
     
    #define DCMI_ESCR_FSC_Msk   (0xFFUL << DCMI_ESCR_FSC_Pos)
     
    #define DCMI_ESCR_FSC   DCMI_ESCR_FSC_Msk
     
    #define DCMI_ESCR_LSC_Pos   (8U)
     
    #define DCMI_ESCR_LSC_Msk   (0xFFUL << DCMI_ESCR_LSC_Pos)
     
    #define DCMI_ESCR_LSC   DCMI_ESCR_LSC_Msk
     
    #define DCMI_ESCR_LEC_Pos   (16U)
     
    #define DCMI_ESCR_LEC_Msk   (0xFFUL << DCMI_ESCR_LEC_Pos)
     
    #define DCMI_ESCR_LEC   DCMI_ESCR_LEC_Msk
     
    #define DCMI_ESCR_FEC_Pos   (24U)
     
    #define DCMI_ESCR_FEC_Msk   (0xFFUL << DCMI_ESCR_FEC_Pos)
     
    #define DCMI_ESCR_FEC   DCMI_ESCR_FEC_Msk
     
    #define DCMI_ESUR_FSU_Pos   (0U)
     
    #define DCMI_ESUR_FSU_Msk   (0xFFUL << DCMI_ESUR_FSU_Pos)
     
    #define DCMI_ESUR_FSU   DCMI_ESUR_FSU_Msk
     
    #define DCMI_ESUR_LSU_Pos   (8U)
     
    #define DCMI_ESUR_LSU_Msk   (0xFFUL << DCMI_ESUR_LSU_Pos)
     
    #define DCMI_ESUR_LSU   DCMI_ESUR_LSU_Msk
     
    #define DCMI_ESUR_LEU_Pos   (16U)
     
    #define DCMI_ESUR_LEU_Msk   (0xFFUL << DCMI_ESUR_LEU_Pos)
     
    #define DCMI_ESUR_LEU   DCMI_ESUR_LEU_Msk
     
    #define DCMI_ESUR_FEU_Pos   (24U)
     
    #define DCMI_ESUR_FEU_Msk   (0xFFUL << DCMI_ESUR_FEU_Pos)
     
    #define DCMI_ESUR_FEU   DCMI_ESUR_FEU_Msk
     
    #define DCMI_CWSTRT_HOFFCNT_Pos   (0U)
     
    #define DCMI_CWSTRT_HOFFCNT_Msk   (0x3FFFUL << DCMI_CWSTRT_HOFFCNT_Pos)
     
    #define DCMI_CWSTRT_HOFFCNT   DCMI_CWSTRT_HOFFCNT_Msk
     
    #define DCMI_CWSTRT_VST_Pos   (16U)
     
    #define DCMI_CWSTRT_VST_Msk   (0x1FFFUL << DCMI_CWSTRT_VST_Pos)
     
    #define DCMI_CWSTRT_VST   DCMI_CWSTRT_VST_Msk
     
    #define DCMI_CWSIZE_CAPCNT_Pos   (0U)
     
    #define DCMI_CWSIZE_CAPCNT_Msk   (0x3FFFUL << DCMI_CWSIZE_CAPCNT_Pos)
     
    #define DCMI_CWSIZE_CAPCNT   DCMI_CWSIZE_CAPCNT_Msk
     
    #define DCMI_CWSIZE_VLINE_Pos   (16U)
     
    #define DCMI_CWSIZE_VLINE_Msk   (0x3FFFUL << DCMI_CWSIZE_VLINE_Pos)
     
    #define DCMI_CWSIZE_VLINE   DCMI_CWSIZE_VLINE_Msk
     
    #define DCMI_DR_BYTE0_Pos   (0U)
     
    #define DCMI_DR_BYTE0_Msk   (0xFFUL << DCMI_DR_BYTE0_Pos)
     
    #define DCMI_DR_BYTE0   DCMI_DR_BYTE0_Msk
     
    #define DCMI_DR_BYTE1_Pos   (8U)
     
    #define DCMI_DR_BYTE1_Msk   (0xFFUL << DCMI_DR_BYTE1_Pos)
     
    #define DCMI_DR_BYTE1   DCMI_DR_BYTE1_Msk
     
    #define DCMI_DR_BYTE2_Pos   (16U)
     
    #define DCMI_DR_BYTE2_Msk   (0xFFUL << DCMI_DR_BYTE2_Pos)
     
    #define DCMI_DR_BYTE2   DCMI_DR_BYTE2_Msk
     
    #define DCMI_DR_BYTE3_Pos   (24U)
     
    #define DCMI_DR_BYTE3_Msk   (0xFFUL << DCMI_DR_BYTE3_Pos)
     
    #define DCMI_DR_BYTE3   DCMI_DR_BYTE3_Msk
     
    #define DMA_SxCR_CHSEL_Pos   (25U)
     
    #define DMA_SxCR_CHSEL_Msk   (0x7UL << DMA_SxCR_CHSEL_Pos)
     
    #define DMA_SxCR_CHSEL   DMA_SxCR_CHSEL_Msk
     
    #define DMA_SxCR_CHSEL_0   0x02000000U
     
    #define DMA_SxCR_CHSEL_1   0x04000000U
     
    #define DMA_SxCR_CHSEL_2   0x08000000U
     
    #define DMA_SxCR_MBURST_Pos   (23U)
     
    #define DMA_SxCR_MBURST_Msk   (0x3UL << DMA_SxCR_MBURST_Pos)
     
    #define DMA_SxCR_MBURST   DMA_SxCR_MBURST_Msk
     
    #define DMA_SxCR_MBURST_0   (0x1UL << DMA_SxCR_MBURST_Pos)
     
    #define DMA_SxCR_MBURST_1   (0x2UL << DMA_SxCR_MBURST_Pos)
     
    #define DMA_SxCR_PBURST_Pos   (21U)
     
    #define DMA_SxCR_PBURST_Msk   (0x3UL << DMA_SxCR_PBURST_Pos)
     
    #define DMA_SxCR_PBURST   DMA_SxCR_PBURST_Msk
     
    #define DMA_SxCR_PBURST_0   (0x1UL << DMA_SxCR_PBURST_Pos)
     
    #define DMA_SxCR_PBURST_1   (0x2UL << DMA_SxCR_PBURST_Pos)
     
    #define DMA_SxCR_CT_Pos   (19U)
     
    #define DMA_SxCR_CT_Msk   (0x1UL << DMA_SxCR_CT_Pos)
     
    #define DMA_SxCR_CT   DMA_SxCR_CT_Msk
     
    #define DMA_SxCR_DBM_Pos   (18U)
     
    #define DMA_SxCR_DBM_Msk   (0x1UL << DMA_SxCR_DBM_Pos)
     
    #define DMA_SxCR_DBM   DMA_SxCR_DBM_Msk
     
    #define DMA_SxCR_PL_Pos   (16U)
     
    #define DMA_SxCR_PL_Msk   (0x3UL << DMA_SxCR_PL_Pos)
     
    #define DMA_SxCR_PL   DMA_SxCR_PL_Msk
     
    #define DMA_SxCR_PL_0   (0x1UL << DMA_SxCR_PL_Pos)
     
    #define DMA_SxCR_PL_1   (0x2UL << DMA_SxCR_PL_Pos)
     
    #define DMA_SxCR_PINCOS_Pos   (15U)
     
    #define DMA_SxCR_PINCOS_Msk   (0x1UL << DMA_SxCR_PINCOS_Pos)
     
    #define DMA_SxCR_PINCOS   DMA_SxCR_PINCOS_Msk
     
    #define DMA_SxCR_MSIZE_Pos   (13U)
     
    #define DMA_SxCR_MSIZE_Msk   (0x3UL << DMA_SxCR_MSIZE_Pos)
     
    #define DMA_SxCR_MSIZE   DMA_SxCR_MSIZE_Msk
     
    #define DMA_SxCR_MSIZE_0   (0x1UL << DMA_SxCR_MSIZE_Pos)
     
    #define DMA_SxCR_MSIZE_1   (0x2UL << DMA_SxCR_MSIZE_Pos)
     
    #define DMA_SxCR_PSIZE_Pos   (11U)
     
    #define DMA_SxCR_PSIZE_Msk   (0x3UL << DMA_SxCR_PSIZE_Pos)
     
    #define DMA_SxCR_PSIZE   DMA_SxCR_PSIZE_Msk
     
    #define DMA_SxCR_PSIZE_0   (0x1UL << DMA_SxCR_PSIZE_Pos)
     
    #define DMA_SxCR_PSIZE_1   (0x2UL << DMA_SxCR_PSIZE_Pos)
     
    #define DMA_SxCR_MINC_Pos   (10U)
     
    #define DMA_SxCR_MINC_Msk   (0x1UL << DMA_SxCR_MINC_Pos)
     
    #define DMA_SxCR_MINC   DMA_SxCR_MINC_Msk
     
    #define DMA_SxCR_PINC_Pos   (9U)
     
    #define DMA_SxCR_PINC_Msk   (0x1UL << DMA_SxCR_PINC_Pos)
     
    #define DMA_SxCR_PINC   DMA_SxCR_PINC_Msk
     
    #define DMA_SxCR_CIRC_Pos   (8U)
     
    #define DMA_SxCR_CIRC_Msk   (0x1UL << DMA_SxCR_CIRC_Pos)
     
    #define DMA_SxCR_CIRC   DMA_SxCR_CIRC_Msk
     
    #define DMA_SxCR_DIR_Pos   (6U)
     
    #define DMA_SxCR_DIR_Msk   (0x3UL << DMA_SxCR_DIR_Pos)
     
    #define DMA_SxCR_DIR   DMA_SxCR_DIR_Msk
     
    #define DMA_SxCR_DIR_0   (0x1UL << DMA_SxCR_DIR_Pos)
     
    #define DMA_SxCR_DIR_1   (0x2UL << DMA_SxCR_DIR_Pos)
     
    #define DMA_SxCR_PFCTRL_Pos   (5U)
     
    #define DMA_SxCR_PFCTRL_Msk   (0x1UL << DMA_SxCR_PFCTRL_Pos)
     
    #define DMA_SxCR_PFCTRL   DMA_SxCR_PFCTRL_Msk
     
    #define DMA_SxCR_TCIE_Pos   (4U)
     
    #define DMA_SxCR_TCIE_Msk   (0x1UL << DMA_SxCR_TCIE_Pos)
     
    #define DMA_SxCR_TCIE   DMA_SxCR_TCIE_Msk
     
    #define DMA_SxCR_HTIE_Pos   (3U)
     
    #define DMA_SxCR_HTIE_Msk   (0x1UL << DMA_SxCR_HTIE_Pos)
     
    #define DMA_SxCR_HTIE   DMA_SxCR_HTIE_Msk
     
    #define DMA_SxCR_TEIE_Pos   (2U)
     
    #define DMA_SxCR_TEIE_Msk   (0x1UL << DMA_SxCR_TEIE_Pos)
     
    #define DMA_SxCR_TEIE   DMA_SxCR_TEIE_Msk
     
    #define DMA_SxCR_DMEIE_Pos   (1U)
     
    #define DMA_SxCR_DMEIE_Msk   (0x1UL << DMA_SxCR_DMEIE_Pos)
     
    #define DMA_SxCR_DMEIE   DMA_SxCR_DMEIE_Msk
     
    #define DMA_SxCR_EN_Pos   (0U)
     
    #define DMA_SxCR_EN_Msk   (0x1UL << DMA_SxCR_EN_Pos)
     
    #define DMA_SxCR_EN   DMA_SxCR_EN_Msk
     
    #define DMA_SxCR_ACK_Pos   (20U)
     
    #define DMA_SxCR_ACK_Msk   (0x1UL << DMA_SxCR_ACK_Pos)
     
    #define DMA_SxCR_ACK   DMA_SxCR_ACK_Msk
     
    #define DMA_SxNDT_Pos   (0U)
     
    #define DMA_SxNDT_Msk   (0xFFFFUL << DMA_SxNDT_Pos)
     
    #define DMA_SxNDT   DMA_SxNDT_Msk
     
    #define DMA_SxNDT_0   (0x0001UL << DMA_SxNDT_Pos)
     
    #define DMA_SxNDT_1   (0x0002UL << DMA_SxNDT_Pos)
     
    #define DMA_SxNDT_2   (0x0004UL << DMA_SxNDT_Pos)
     
    #define DMA_SxNDT_3   (0x0008UL << DMA_SxNDT_Pos)
     
    #define DMA_SxNDT_4   (0x0010UL << DMA_SxNDT_Pos)
     
    #define DMA_SxNDT_5   (0x0020UL << DMA_SxNDT_Pos)
     
    #define DMA_SxNDT_6   (0x0040UL << DMA_SxNDT_Pos)
     
    #define DMA_SxNDT_7   (0x0080UL << DMA_SxNDT_Pos)
     
    #define DMA_SxNDT_8   (0x0100UL << DMA_SxNDT_Pos)
     
    #define DMA_SxNDT_9   (0x0200UL << DMA_SxNDT_Pos)
     
    #define DMA_SxNDT_10   (0x0400UL << DMA_SxNDT_Pos)
     
    #define DMA_SxNDT_11   (0x0800UL << DMA_SxNDT_Pos)
     
    #define DMA_SxNDT_12   (0x1000UL << DMA_SxNDT_Pos)
     
    #define DMA_SxNDT_13   (0x2000UL << DMA_SxNDT_Pos)
     
    #define DMA_SxNDT_14   (0x4000UL << DMA_SxNDT_Pos)
     
    #define DMA_SxNDT_15   (0x8000UL << DMA_SxNDT_Pos)
     
    #define DMA_SxFCR_FEIE_Pos   (7U)
     
    #define DMA_SxFCR_FEIE_Msk   (0x1UL << DMA_SxFCR_FEIE_Pos)
     
    #define DMA_SxFCR_FEIE   DMA_SxFCR_FEIE_Msk
     
    #define DMA_SxFCR_FS_Pos   (3U)
     
    #define DMA_SxFCR_FS_Msk   (0x7UL << DMA_SxFCR_FS_Pos)
     
    #define DMA_SxFCR_FS   DMA_SxFCR_FS_Msk
     
    #define DMA_SxFCR_FS_0   (0x1UL << DMA_SxFCR_FS_Pos)
     
    #define DMA_SxFCR_FS_1   (0x2UL << DMA_SxFCR_FS_Pos)
     
    #define DMA_SxFCR_FS_2   (0x4UL << DMA_SxFCR_FS_Pos)
     
    #define DMA_SxFCR_DMDIS_Pos   (2U)
     
    #define DMA_SxFCR_DMDIS_Msk   (0x1UL << DMA_SxFCR_DMDIS_Pos)
     
    #define DMA_SxFCR_DMDIS   DMA_SxFCR_DMDIS_Msk
     
    #define DMA_SxFCR_FTH_Pos   (0U)
     
    #define DMA_SxFCR_FTH_Msk   (0x3UL << DMA_SxFCR_FTH_Pos)
     
    #define DMA_SxFCR_FTH   DMA_SxFCR_FTH_Msk
     
    #define DMA_SxFCR_FTH_0   (0x1UL << DMA_SxFCR_FTH_Pos)
     
    #define DMA_SxFCR_FTH_1   (0x2UL << DMA_SxFCR_FTH_Pos)
     
    #define DMA_LISR_TCIF3_Pos   (27U)
     
    #define DMA_LISR_TCIF3_Msk   (0x1UL << DMA_LISR_TCIF3_Pos)
     
    #define DMA_LISR_TCIF3   DMA_LISR_TCIF3_Msk
     
    #define DMA_LISR_HTIF3_Pos   (26U)
     
    #define DMA_LISR_HTIF3_Msk   (0x1UL << DMA_LISR_HTIF3_Pos)
     
    #define DMA_LISR_HTIF3   DMA_LISR_HTIF3_Msk
     
    #define DMA_LISR_TEIF3_Pos   (25U)
     
    #define DMA_LISR_TEIF3_Msk   (0x1UL << DMA_LISR_TEIF3_Pos)
     
    #define DMA_LISR_TEIF3   DMA_LISR_TEIF3_Msk
     
    #define DMA_LISR_DMEIF3_Pos   (24U)
     
    #define DMA_LISR_DMEIF3_Msk   (0x1UL << DMA_LISR_DMEIF3_Pos)
     
    #define DMA_LISR_DMEIF3   DMA_LISR_DMEIF3_Msk
     
    #define DMA_LISR_FEIF3_Pos   (22U)
     
    #define DMA_LISR_FEIF3_Msk   (0x1UL << DMA_LISR_FEIF3_Pos)
     
    #define DMA_LISR_FEIF3   DMA_LISR_FEIF3_Msk
     
    #define DMA_LISR_TCIF2_Pos   (21U)
     
    #define DMA_LISR_TCIF2_Msk   (0x1UL << DMA_LISR_TCIF2_Pos)
     
    #define DMA_LISR_TCIF2   DMA_LISR_TCIF2_Msk
     
    #define DMA_LISR_HTIF2_Pos   (20U)
     
    #define DMA_LISR_HTIF2_Msk   (0x1UL << DMA_LISR_HTIF2_Pos)
     
    #define DMA_LISR_HTIF2   DMA_LISR_HTIF2_Msk
     
    #define DMA_LISR_TEIF2_Pos   (19U)
     
    #define DMA_LISR_TEIF2_Msk   (0x1UL << DMA_LISR_TEIF2_Pos)
     
    #define DMA_LISR_TEIF2   DMA_LISR_TEIF2_Msk
     
    #define DMA_LISR_DMEIF2_Pos   (18U)
     
    #define DMA_LISR_DMEIF2_Msk   (0x1UL << DMA_LISR_DMEIF2_Pos)
     
    #define DMA_LISR_DMEIF2   DMA_LISR_DMEIF2_Msk
     
    #define DMA_LISR_FEIF2_Pos   (16U)
     
    #define DMA_LISR_FEIF2_Msk   (0x1UL << DMA_LISR_FEIF2_Pos)
     
    #define DMA_LISR_FEIF2   DMA_LISR_FEIF2_Msk
     
    #define DMA_LISR_TCIF1_Pos   (11U)
     
    #define DMA_LISR_TCIF1_Msk   (0x1UL << DMA_LISR_TCIF1_Pos)
     
    #define DMA_LISR_TCIF1   DMA_LISR_TCIF1_Msk
     
    #define DMA_LISR_HTIF1_Pos   (10U)
     
    #define DMA_LISR_HTIF1_Msk   (0x1UL << DMA_LISR_HTIF1_Pos)
     
    #define DMA_LISR_HTIF1   DMA_LISR_HTIF1_Msk
     
    #define DMA_LISR_TEIF1_Pos   (9U)
     
    #define DMA_LISR_TEIF1_Msk   (0x1UL << DMA_LISR_TEIF1_Pos)
     
    #define DMA_LISR_TEIF1   DMA_LISR_TEIF1_Msk
     
    #define DMA_LISR_DMEIF1_Pos   (8U)
     
    #define DMA_LISR_DMEIF1_Msk   (0x1UL << DMA_LISR_DMEIF1_Pos)
     
    #define DMA_LISR_DMEIF1   DMA_LISR_DMEIF1_Msk
     
    #define DMA_LISR_FEIF1_Pos   (6U)
     
    #define DMA_LISR_FEIF1_Msk   (0x1UL << DMA_LISR_FEIF1_Pos)
     
    #define DMA_LISR_FEIF1   DMA_LISR_FEIF1_Msk
     
    #define DMA_LISR_TCIF0_Pos   (5U)
     
    #define DMA_LISR_TCIF0_Msk   (0x1UL << DMA_LISR_TCIF0_Pos)
     
    #define DMA_LISR_TCIF0   DMA_LISR_TCIF0_Msk
     
    #define DMA_LISR_HTIF0_Pos   (4U)
     
    #define DMA_LISR_HTIF0_Msk   (0x1UL << DMA_LISR_HTIF0_Pos)
     
    #define DMA_LISR_HTIF0   DMA_LISR_HTIF0_Msk
     
    #define DMA_LISR_TEIF0_Pos   (3U)
     
    #define DMA_LISR_TEIF0_Msk   (0x1UL << DMA_LISR_TEIF0_Pos)
     
    #define DMA_LISR_TEIF0   DMA_LISR_TEIF0_Msk
     
    #define DMA_LISR_DMEIF0_Pos   (2U)
     
    #define DMA_LISR_DMEIF0_Msk   (0x1UL << DMA_LISR_DMEIF0_Pos)
     
    #define DMA_LISR_DMEIF0   DMA_LISR_DMEIF0_Msk
     
    #define DMA_LISR_FEIF0_Pos   (0U)
     
    #define DMA_LISR_FEIF0_Msk   (0x1UL << DMA_LISR_FEIF0_Pos)
     
    #define DMA_LISR_FEIF0   DMA_LISR_FEIF0_Msk
     
    #define DMA_HISR_TCIF7_Pos   (27U)
     
    #define DMA_HISR_TCIF7_Msk   (0x1UL << DMA_HISR_TCIF7_Pos)
     
    #define DMA_HISR_TCIF7   DMA_HISR_TCIF7_Msk
     
    #define DMA_HISR_HTIF7_Pos   (26U)
     
    #define DMA_HISR_HTIF7_Msk   (0x1UL << DMA_HISR_HTIF7_Pos)
     
    #define DMA_HISR_HTIF7   DMA_HISR_HTIF7_Msk
     
    #define DMA_HISR_TEIF7_Pos   (25U)
     
    #define DMA_HISR_TEIF7_Msk   (0x1UL << DMA_HISR_TEIF7_Pos)
     
    #define DMA_HISR_TEIF7   DMA_HISR_TEIF7_Msk
     
    #define DMA_HISR_DMEIF7_Pos   (24U)
     
    #define DMA_HISR_DMEIF7_Msk   (0x1UL << DMA_HISR_DMEIF7_Pos)
     
    #define DMA_HISR_DMEIF7   DMA_HISR_DMEIF7_Msk
     
    #define DMA_HISR_FEIF7_Pos   (22U)
     
    #define DMA_HISR_FEIF7_Msk   (0x1UL << DMA_HISR_FEIF7_Pos)
     
    #define DMA_HISR_FEIF7   DMA_HISR_FEIF7_Msk
     
    #define DMA_HISR_TCIF6_Pos   (21U)
     
    #define DMA_HISR_TCIF6_Msk   (0x1UL << DMA_HISR_TCIF6_Pos)
     
    #define DMA_HISR_TCIF6   DMA_HISR_TCIF6_Msk
     
    #define DMA_HISR_HTIF6_Pos   (20U)
     
    #define DMA_HISR_HTIF6_Msk   (0x1UL << DMA_HISR_HTIF6_Pos)
     
    #define DMA_HISR_HTIF6   DMA_HISR_HTIF6_Msk
     
    #define DMA_HISR_TEIF6_Pos   (19U)
     
    #define DMA_HISR_TEIF6_Msk   (0x1UL << DMA_HISR_TEIF6_Pos)
     
    #define DMA_HISR_TEIF6   DMA_HISR_TEIF6_Msk
     
    #define DMA_HISR_DMEIF6_Pos   (18U)
     
    #define DMA_HISR_DMEIF6_Msk   (0x1UL << DMA_HISR_DMEIF6_Pos)
     
    #define DMA_HISR_DMEIF6   DMA_HISR_DMEIF6_Msk
     
    #define DMA_HISR_FEIF6_Pos   (16U)
     
    #define DMA_HISR_FEIF6_Msk   (0x1UL << DMA_HISR_FEIF6_Pos)
     
    #define DMA_HISR_FEIF6   DMA_HISR_FEIF6_Msk
     
    #define DMA_HISR_TCIF5_Pos   (11U)
     
    #define DMA_HISR_TCIF5_Msk   (0x1UL << DMA_HISR_TCIF5_Pos)
     
    #define DMA_HISR_TCIF5   DMA_HISR_TCIF5_Msk
     
    #define DMA_HISR_HTIF5_Pos   (10U)
     
    #define DMA_HISR_HTIF5_Msk   (0x1UL << DMA_HISR_HTIF5_Pos)
     
    #define DMA_HISR_HTIF5   DMA_HISR_HTIF5_Msk
     
    #define DMA_HISR_TEIF5_Pos   (9U)
     
    #define DMA_HISR_TEIF5_Msk   (0x1UL << DMA_HISR_TEIF5_Pos)
     
    #define DMA_HISR_TEIF5   DMA_HISR_TEIF5_Msk
     
    #define DMA_HISR_DMEIF5_Pos   (8U)
     
    #define DMA_HISR_DMEIF5_Msk   (0x1UL << DMA_HISR_DMEIF5_Pos)
     
    #define DMA_HISR_DMEIF5   DMA_HISR_DMEIF5_Msk
     
    #define DMA_HISR_FEIF5_Pos   (6U)
     
    #define DMA_HISR_FEIF5_Msk   (0x1UL << DMA_HISR_FEIF5_Pos)
     
    #define DMA_HISR_FEIF5   DMA_HISR_FEIF5_Msk
     
    #define DMA_HISR_TCIF4_Pos   (5U)
     
    #define DMA_HISR_TCIF4_Msk   (0x1UL << DMA_HISR_TCIF4_Pos)
     
    #define DMA_HISR_TCIF4   DMA_HISR_TCIF4_Msk
     
    #define DMA_HISR_HTIF4_Pos   (4U)
     
    #define DMA_HISR_HTIF4_Msk   (0x1UL << DMA_HISR_HTIF4_Pos)
     
    #define DMA_HISR_HTIF4   DMA_HISR_HTIF4_Msk
     
    #define DMA_HISR_TEIF4_Pos   (3U)
     
    #define DMA_HISR_TEIF4_Msk   (0x1UL << DMA_HISR_TEIF4_Pos)
     
    #define DMA_HISR_TEIF4   DMA_HISR_TEIF4_Msk
     
    #define DMA_HISR_DMEIF4_Pos   (2U)
     
    #define DMA_HISR_DMEIF4_Msk   (0x1UL << DMA_HISR_DMEIF4_Pos)
     
    #define DMA_HISR_DMEIF4   DMA_HISR_DMEIF4_Msk
     
    #define DMA_HISR_FEIF4_Pos   (0U)
     
    #define DMA_HISR_FEIF4_Msk   (0x1UL << DMA_HISR_FEIF4_Pos)
     
    #define DMA_HISR_FEIF4   DMA_HISR_FEIF4_Msk
     
    #define DMA_LIFCR_CTCIF3_Pos   (27U)
     
    #define DMA_LIFCR_CTCIF3_Msk   (0x1UL << DMA_LIFCR_CTCIF3_Pos)
     
    #define DMA_LIFCR_CTCIF3   DMA_LIFCR_CTCIF3_Msk
     
    #define DMA_LIFCR_CHTIF3_Pos   (26U)
     
    #define DMA_LIFCR_CHTIF3_Msk   (0x1UL << DMA_LIFCR_CHTIF3_Pos)
     
    #define DMA_LIFCR_CHTIF3   DMA_LIFCR_CHTIF3_Msk
     
    #define DMA_LIFCR_CTEIF3_Pos   (25U)
     
    #define DMA_LIFCR_CTEIF3_Msk   (0x1UL << DMA_LIFCR_CTEIF3_Pos)
     
    #define DMA_LIFCR_CTEIF3   DMA_LIFCR_CTEIF3_Msk
     
    #define DMA_LIFCR_CDMEIF3_Pos   (24U)
     
    #define DMA_LIFCR_CDMEIF3_Msk   (0x1UL << DMA_LIFCR_CDMEIF3_Pos)
     
    #define DMA_LIFCR_CDMEIF3   DMA_LIFCR_CDMEIF3_Msk
     
    #define DMA_LIFCR_CFEIF3_Pos   (22U)
     
    #define DMA_LIFCR_CFEIF3_Msk   (0x1UL << DMA_LIFCR_CFEIF3_Pos)
     
    #define DMA_LIFCR_CFEIF3   DMA_LIFCR_CFEIF3_Msk
     
    #define DMA_LIFCR_CTCIF2_Pos   (21U)
     
    #define DMA_LIFCR_CTCIF2_Msk   (0x1UL << DMA_LIFCR_CTCIF2_Pos)
     
    #define DMA_LIFCR_CTCIF2   DMA_LIFCR_CTCIF2_Msk
     
    #define DMA_LIFCR_CHTIF2_Pos   (20U)
     
    #define DMA_LIFCR_CHTIF2_Msk   (0x1UL << DMA_LIFCR_CHTIF2_Pos)
     
    #define DMA_LIFCR_CHTIF2   DMA_LIFCR_CHTIF2_Msk
     
    #define DMA_LIFCR_CTEIF2_Pos   (19U)
     
    #define DMA_LIFCR_CTEIF2_Msk   (0x1UL << DMA_LIFCR_CTEIF2_Pos)
     
    #define DMA_LIFCR_CTEIF2   DMA_LIFCR_CTEIF2_Msk
     
    #define DMA_LIFCR_CDMEIF2_Pos   (18U)
     
    #define DMA_LIFCR_CDMEIF2_Msk   (0x1UL << DMA_LIFCR_CDMEIF2_Pos)
     
    #define DMA_LIFCR_CDMEIF2   DMA_LIFCR_CDMEIF2_Msk
     
    #define DMA_LIFCR_CFEIF2_Pos   (16U)
     
    #define DMA_LIFCR_CFEIF2_Msk   (0x1UL << DMA_LIFCR_CFEIF2_Pos)
     
    #define DMA_LIFCR_CFEIF2   DMA_LIFCR_CFEIF2_Msk
     
    #define DMA_LIFCR_CTCIF1_Pos   (11U)
     
    #define DMA_LIFCR_CTCIF1_Msk   (0x1UL << DMA_LIFCR_CTCIF1_Pos)
     
    #define DMA_LIFCR_CTCIF1   DMA_LIFCR_CTCIF1_Msk
     
    #define DMA_LIFCR_CHTIF1_Pos   (10U)
     
    #define DMA_LIFCR_CHTIF1_Msk   (0x1UL << DMA_LIFCR_CHTIF1_Pos)
     
    #define DMA_LIFCR_CHTIF1   DMA_LIFCR_CHTIF1_Msk
     
    #define DMA_LIFCR_CTEIF1_Pos   (9U)
     
    #define DMA_LIFCR_CTEIF1_Msk   (0x1UL << DMA_LIFCR_CTEIF1_Pos)
     
    #define DMA_LIFCR_CTEIF1   DMA_LIFCR_CTEIF1_Msk
     
    #define DMA_LIFCR_CDMEIF1_Pos   (8U)
     
    #define DMA_LIFCR_CDMEIF1_Msk   (0x1UL << DMA_LIFCR_CDMEIF1_Pos)
     
    #define DMA_LIFCR_CDMEIF1   DMA_LIFCR_CDMEIF1_Msk
     
    #define DMA_LIFCR_CFEIF1_Pos   (6U)
     
    #define DMA_LIFCR_CFEIF1_Msk   (0x1UL << DMA_LIFCR_CFEIF1_Pos)
     
    #define DMA_LIFCR_CFEIF1   DMA_LIFCR_CFEIF1_Msk
     
    #define DMA_LIFCR_CTCIF0_Pos   (5U)
     
    #define DMA_LIFCR_CTCIF0_Msk   (0x1UL << DMA_LIFCR_CTCIF0_Pos)
     
    #define DMA_LIFCR_CTCIF0   DMA_LIFCR_CTCIF0_Msk
     
    #define DMA_LIFCR_CHTIF0_Pos   (4U)
     
    #define DMA_LIFCR_CHTIF0_Msk   (0x1UL << DMA_LIFCR_CHTIF0_Pos)
     
    #define DMA_LIFCR_CHTIF0   DMA_LIFCR_CHTIF0_Msk
     
    #define DMA_LIFCR_CTEIF0_Pos   (3U)
     
    #define DMA_LIFCR_CTEIF0_Msk   (0x1UL << DMA_LIFCR_CTEIF0_Pos)
     
    #define DMA_LIFCR_CTEIF0   DMA_LIFCR_CTEIF0_Msk
     
    #define DMA_LIFCR_CDMEIF0_Pos   (2U)
     
    #define DMA_LIFCR_CDMEIF0_Msk   (0x1UL << DMA_LIFCR_CDMEIF0_Pos)
     
    #define DMA_LIFCR_CDMEIF0   DMA_LIFCR_CDMEIF0_Msk
     
    #define DMA_LIFCR_CFEIF0_Pos   (0U)
     
    #define DMA_LIFCR_CFEIF0_Msk   (0x1UL << DMA_LIFCR_CFEIF0_Pos)
     
    #define DMA_LIFCR_CFEIF0   DMA_LIFCR_CFEIF0_Msk
     
    #define DMA_HIFCR_CTCIF7_Pos   (27U)
     
    #define DMA_HIFCR_CTCIF7_Msk   (0x1UL << DMA_HIFCR_CTCIF7_Pos)
     
    #define DMA_HIFCR_CTCIF7   DMA_HIFCR_CTCIF7_Msk
     
    #define DMA_HIFCR_CHTIF7_Pos   (26U)
     
    #define DMA_HIFCR_CHTIF7_Msk   (0x1UL << DMA_HIFCR_CHTIF7_Pos)
     
    #define DMA_HIFCR_CHTIF7   DMA_HIFCR_CHTIF7_Msk
     
    #define DMA_HIFCR_CTEIF7_Pos   (25U)
     
    #define DMA_HIFCR_CTEIF7_Msk   (0x1UL << DMA_HIFCR_CTEIF7_Pos)
     
    #define DMA_HIFCR_CTEIF7   DMA_HIFCR_CTEIF7_Msk
     
    #define DMA_HIFCR_CDMEIF7_Pos   (24U)
     
    #define DMA_HIFCR_CDMEIF7_Msk   (0x1UL << DMA_HIFCR_CDMEIF7_Pos)
     
    #define DMA_HIFCR_CDMEIF7   DMA_HIFCR_CDMEIF7_Msk
     
    #define DMA_HIFCR_CFEIF7_Pos   (22U)
     
    #define DMA_HIFCR_CFEIF7_Msk   (0x1UL << DMA_HIFCR_CFEIF7_Pos)
     
    #define DMA_HIFCR_CFEIF7   DMA_HIFCR_CFEIF7_Msk
     
    #define DMA_HIFCR_CTCIF6_Pos   (21U)
     
    #define DMA_HIFCR_CTCIF6_Msk   (0x1UL << DMA_HIFCR_CTCIF6_Pos)
     
    #define DMA_HIFCR_CTCIF6   DMA_HIFCR_CTCIF6_Msk
     
    #define DMA_HIFCR_CHTIF6_Pos   (20U)
     
    #define DMA_HIFCR_CHTIF6_Msk   (0x1UL << DMA_HIFCR_CHTIF6_Pos)
     
    #define DMA_HIFCR_CHTIF6   DMA_HIFCR_CHTIF6_Msk
     
    #define DMA_HIFCR_CTEIF6_Pos   (19U)
     
    #define DMA_HIFCR_CTEIF6_Msk   (0x1UL << DMA_HIFCR_CTEIF6_Pos)
     
    #define DMA_HIFCR_CTEIF6   DMA_HIFCR_CTEIF6_Msk
     
    #define DMA_HIFCR_CDMEIF6_Pos   (18U)
     
    #define DMA_HIFCR_CDMEIF6_Msk   (0x1UL << DMA_HIFCR_CDMEIF6_Pos)
     
    #define DMA_HIFCR_CDMEIF6   DMA_HIFCR_CDMEIF6_Msk
     
    #define DMA_HIFCR_CFEIF6_Pos   (16U)
     
    #define DMA_HIFCR_CFEIF6_Msk   (0x1UL << DMA_HIFCR_CFEIF6_Pos)
     
    #define DMA_HIFCR_CFEIF6   DMA_HIFCR_CFEIF6_Msk
     
    #define DMA_HIFCR_CTCIF5_Pos   (11U)
     
    #define DMA_HIFCR_CTCIF5_Msk   (0x1UL << DMA_HIFCR_CTCIF5_Pos)
     
    #define DMA_HIFCR_CTCIF5   DMA_HIFCR_CTCIF5_Msk
     
    #define DMA_HIFCR_CHTIF5_Pos   (10U)
     
    #define DMA_HIFCR_CHTIF5_Msk   (0x1UL << DMA_HIFCR_CHTIF5_Pos)
     
    #define DMA_HIFCR_CHTIF5   DMA_HIFCR_CHTIF5_Msk
     
    #define DMA_HIFCR_CTEIF5_Pos   (9U)
     
    #define DMA_HIFCR_CTEIF5_Msk   (0x1UL << DMA_HIFCR_CTEIF5_Pos)
     
    #define DMA_HIFCR_CTEIF5   DMA_HIFCR_CTEIF5_Msk
     
    #define DMA_HIFCR_CDMEIF5_Pos   (8U)
     
    #define DMA_HIFCR_CDMEIF5_Msk   (0x1UL << DMA_HIFCR_CDMEIF5_Pos)
     
    #define DMA_HIFCR_CDMEIF5   DMA_HIFCR_CDMEIF5_Msk
     
    #define DMA_HIFCR_CFEIF5_Pos   (6U)
     
    #define DMA_HIFCR_CFEIF5_Msk   (0x1UL << DMA_HIFCR_CFEIF5_Pos)
     
    #define DMA_HIFCR_CFEIF5   DMA_HIFCR_CFEIF5_Msk
     
    #define DMA_HIFCR_CTCIF4_Pos   (5U)
     
    #define DMA_HIFCR_CTCIF4_Msk   (0x1UL << DMA_HIFCR_CTCIF4_Pos)
     
    #define DMA_HIFCR_CTCIF4   DMA_HIFCR_CTCIF4_Msk
     
    #define DMA_HIFCR_CHTIF4_Pos   (4U)
     
    #define DMA_HIFCR_CHTIF4_Msk   (0x1UL << DMA_HIFCR_CHTIF4_Pos)
     
    #define DMA_HIFCR_CHTIF4   DMA_HIFCR_CHTIF4_Msk
     
    #define DMA_HIFCR_CTEIF4_Pos   (3U)
     
    #define DMA_HIFCR_CTEIF4_Msk   (0x1UL << DMA_HIFCR_CTEIF4_Pos)
     
    #define DMA_HIFCR_CTEIF4   DMA_HIFCR_CTEIF4_Msk
     
    #define DMA_HIFCR_CDMEIF4_Pos   (2U)
     
    #define DMA_HIFCR_CDMEIF4_Msk   (0x1UL << DMA_HIFCR_CDMEIF4_Pos)
     
    #define DMA_HIFCR_CDMEIF4   DMA_HIFCR_CDMEIF4_Msk
     
    #define DMA_HIFCR_CFEIF4_Pos   (0U)
     
    #define DMA_HIFCR_CFEIF4_Msk   (0x1UL << DMA_HIFCR_CFEIF4_Pos)
     
    #define DMA_HIFCR_CFEIF4   DMA_HIFCR_CFEIF4_Msk
     
    #define DMA_SxPAR_PA_Pos   (0U)
     
    #define DMA_SxPAR_PA_Msk   (0xFFFFFFFFUL << DMA_SxPAR_PA_Pos)
     
    #define DMA_SxPAR_PA   DMA_SxPAR_PA_Msk
     
    #define DMA_SxM0AR_M0A_Pos   (0U)
     
    #define DMA_SxM0AR_M0A_Msk   (0xFFFFFFFFUL << DMA_SxM0AR_M0A_Pos)
     
    #define DMA_SxM0AR_M0A   DMA_SxM0AR_M0A_Msk
     
    #define DMA_SxM1AR_M1A_Pos   (0U)
     
    #define DMA_SxM1AR_M1A_Msk   (0xFFFFFFFFUL << DMA_SxM1AR_M1A_Pos)
     
    #define DMA_SxM1AR_M1A   DMA_SxM1AR_M1A_Msk
     
    #define EXTI_IMR_MR0_Pos   (0U)
     
    #define EXTI_IMR_MR0_Msk   (0x1UL << EXTI_IMR_MR0_Pos)
     
    #define EXTI_IMR_MR0   EXTI_IMR_MR0_Msk
     
    #define EXTI_IMR_MR1_Pos   (1U)
     
    #define EXTI_IMR_MR1_Msk   (0x1UL << EXTI_IMR_MR1_Pos)
     
    #define EXTI_IMR_MR1   EXTI_IMR_MR1_Msk
     
    #define EXTI_IMR_MR2_Pos   (2U)
     
    #define EXTI_IMR_MR2_Msk   (0x1UL << EXTI_IMR_MR2_Pos)
     
    #define EXTI_IMR_MR2   EXTI_IMR_MR2_Msk
     
    #define EXTI_IMR_MR3_Pos   (3U)
     
    #define EXTI_IMR_MR3_Msk   (0x1UL << EXTI_IMR_MR3_Pos)
     
    #define EXTI_IMR_MR3   EXTI_IMR_MR3_Msk
     
    #define EXTI_IMR_MR4_Pos   (4U)
     
    #define EXTI_IMR_MR4_Msk   (0x1UL << EXTI_IMR_MR4_Pos)
     
    #define EXTI_IMR_MR4   EXTI_IMR_MR4_Msk
     
    #define EXTI_IMR_MR5_Pos   (5U)
     
    #define EXTI_IMR_MR5_Msk   (0x1UL << EXTI_IMR_MR5_Pos)
     
    #define EXTI_IMR_MR5   EXTI_IMR_MR5_Msk
     
    #define EXTI_IMR_MR6_Pos   (6U)
     
    #define EXTI_IMR_MR6_Msk   (0x1UL << EXTI_IMR_MR6_Pos)
     
    #define EXTI_IMR_MR6   EXTI_IMR_MR6_Msk
     
    #define EXTI_IMR_MR7_Pos   (7U)
     
    #define EXTI_IMR_MR7_Msk   (0x1UL << EXTI_IMR_MR7_Pos)
     
    #define EXTI_IMR_MR7   EXTI_IMR_MR7_Msk
     
    #define EXTI_IMR_MR8_Pos   (8U)
     
    #define EXTI_IMR_MR8_Msk   (0x1UL << EXTI_IMR_MR8_Pos)
     
    #define EXTI_IMR_MR8   EXTI_IMR_MR8_Msk
     
    #define EXTI_IMR_MR9_Pos   (9U)
     
    #define EXTI_IMR_MR9_Msk   (0x1UL << EXTI_IMR_MR9_Pos)
     
    #define EXTI_IMR_MR9   EXTI_IMR_MR9_Msk
     
    #define EXTI_IMR_MR10_Pos   (10U)
     
    #define EXTI_IMR_MR10_Msk   (0x1UL << EXTI_IMR_MR10_Pos)
     
    #define EXTI_IMR_MR10   EXTI_IMR_MR10_Msk
     
    #define EXTI_IMR_MR11_Pos   (11U)
     
    #define EXTI_IMR_MR11_Msk   (0x1UL << EXTI_IMR_MR11_Pos)
     
    #define EXTI_IMR_MR11   EXTI_IMR_MR11_Msk
     
    #define EXTI_IMR_MR12_Pos   (12U)
     
    #define EXTI_IMR_MR12_Msk   (0x1UL << EXTI_IMR_MR12_Pos)
     
    #define EXTI_IMR_MR12   EXTI_IMR_MR12_Msk
     
    #define EXTI_IMR_MR13_Pos   (13U)
     
    #define EXTI_IMR_MR13_Msk   (0x1UL << EXTI_IMR_MR13_Pos)
     
    #define EXTI_IMR_MR13   EXTI_IMR_MR13_Msk
     
    #define EXTI_IMR_MR14_Pos   (14U)
     
    #define EXTI_IMR_MR14_Msk   (0x1UL << EXTI_IMR_MR14_Pos)
     
    #define EXTI_IMR_MR14   EXTI_IMR_MR14_Msk
     
    #define EXTI_IMR_MR15_Pos   (15U)
     
    #define EXTI_IMR_MR15_Msk   (0x1UL << EXTI_IMR_MR15_Pos)
     
    #define EXTI_IMR_MR15   EXTI_IMR_MR15_Msk
     
    #define EXTI_IMR_MR16_Pos   (16U)
     
    #define EXTI_IMR_MR16_Msk   (0x1UL << EXTI_IMR_MR16_Pos)
     
    #define EXTI_IMR_MR16   EXTI_IMR_MR16_Msk
     
    #define EXTI_IMR_MR17_Pos   (17U)
     
    #define EXTI_IMR_MR17_Msk   (0x1UL << EXTI_IMR_MR17_Pos)
     
    #define EXTI_IMR_MR17   EXTI_IMR_MR17_Msk
     
    #define EXTI_IMR_MR18_Pos   (18U)
     
    #define EXTI_IMR_MR18_Msk   (0x1UL << EXTI_IMR_MR18_Pos)
     
    #define EXTI_IMR_MR18   EXTI_IMR_MR18_Msk
     
    #define EXTI_IMR_MR19_Pos   (19U)
     
    #define EXTI_IMR_MR19_Msk   (0x1UL << EXTI_IMR_MR19_Pos)
     
    #define EXTI_IMR_MR19   EXTI_IMR_MR19_Msk
     
    #define EXTI_IMR_MR20_Pos   (20U)
     
    #define EXTI_IMR_MR20_Msk   (0x1UL << EXTI_IMR_MR20_Pos)
     
    #define EXTI_IMR_MR20   EXTI_IMR_MR20_Msk
     
    #define EXTI_IMR_MR21_Pos   (21U)
     
    #define EXTI_IMR_MR21_Msk   (0x1UL << EXTI_IMR_MR21_Pos)
     
    #define EXTI_IMR_MR21   EXTI_IMR_MR21_Msk
     
    #define EXTI_IMR_MR22_Pos   (22U)
     
    #define EXTI_IMR_MR22_Msk   (0x1UL << EXTI_IMR_MR22_Pos)
     
    #define EXTI_IMR_MR22   EXTI_IMR_MR22_Msk
     
    #define EXTI_IMR_IM0   EXTI_IMR_MR0
     
    #define EXTI_IMR_IM1   EXTI_IMR_MR1
     
    #define EXTI_IMR_IM2   EXTI_IMR_MR2
     
    #define EXTI_IMR_IM3   EXTI_IMR_MR3
     
    #define EXTI_IMR_IM4   EXTI_IMR_MR4
     
    #define EXTI_IMR_IM5   EXTI_IMR_MR5
     
    #define EXTI_IMR_IM6   EXTI_IMR_MR6
     
    #define EXTI_IMR_IM7   EXTI_IMR_MR7
     
    #define EXTI_IMR_IM8   EXTI_IMR_MR8
     
    #define EXTI_IMR_IM9   EXTI_IMR_MR9
     
    #define EXTI_IMR_IM10   EXTI_IMR_MR10
     
    #define EXTI_IMR_IM11   EXTI_IMR_MR11
     
    #define EXTI_IMR_IM12   EXTI_IMR_MR12
     
    #define EXTI_IMR_IM13   EXTI_IMR_MR13
     
    #define EXTI_IMR_IM14   EXTI_IMR_MR14
     
    #define EXTI_IMR_IM15   EXTI_IMR_MR15
     
    #define EXTI_IMR_IM16   EXTI_IMR_MR16
     
    #define EXTI_IMR_IM17   EXTI_IMR_MR17
     
    #define EXTI_IMR_IM18   EXTI_IMR_MR18
     
    #define EXTI_IMR_IM19   EXTI_IMR_MR19
     
    #define EXTI_IMR_IM20   EXTI_IMR_MR20
     
    #define EXTI_IMR_IM21   EXTI_IMR_MR21
     
    #define EXTI_IMR_IM22   EXTI_IMR_MR22
     
    #define EXTI_IMR_IM_Pos   (0U)
     
    #define EXTI_IMR_IM_Msk   (0x7FFFFFUL << EXTI_IMR_IM_Pos)
     
    #define EXTI_IMR_IM   EXTI_IMR_IM_Msk
     
    #define EXTI_EMR_MR0_Pos   (0U)
     
    #define EXTI_EMR_MR0_Msk   (0x1UL << EXTI_EMR_MR0_Pos)
     
    #define EXTI_EMR_MR0   EXTI_EMR_MR0_Msk
     
    #define EXTI_EMR_MR1_Pos   (1U)
     
    #define EXTI_EMR_MR1_Msk   (0x1UL << EXTI_EMR_MR1_Pos)
     
    #define EXTI_EMR_MR1   EXTI_EMR_MR1_Msk
     
    #define EXTI_EMR_MR2_Pos   (2U)
     
    #define EXTI_EMR_MR2_Msk   (0x1UL << EXTI_EMR_MR2_Pos)
     
    #define EXTI_EMR_MR2   EXTI_EMR_MR2_Msk
     
    #define EXTI_EMR_MR3_Pos   (3U)
     
    #define EXTI_EMR_MR3_Msk   (0x1UL << EXTI_EMR_MR3_Pos)
     
    #define EXTI_EMR_MR3   EXTI_EMR_MR3_Msk
     
    #define EXTI_EMR_MR4_Pos   (4U)
     
    #define EXTI_EMR_MR4_Msk   (0x1UL << EXTI_EMR_MR4_Pos)
     
    #define EXTI_EMR_MR4   EXTI_EMR_MR4_Msk
     
    #define EXTI_EMR_MR5_Pos   (5U)
     
    #define EXTI_EMR_MR5_Msk   (0x1UL << EXTI_EMR_MR5_Pos)
     
    #define EXTI_EMR_MR5   EXTI_EMR_MR5_Msk
     
    #define EXTI_EMR_MR6_Pos   (6U)
     
    #define EXTI_EMR_MR6_Msk   (0x1UL << EXTI_EMR_MR6_Pos)
     
    #define EXTI_EMR_MR6   EXTI_EMR_MR6_Msk
     
    #define EXTI_EMR_MR7_Pos   (7U)
     
    #define EXTI_EMR_MR7_Msk   (0x1UL << EXTI_EMR_MR7_Pos)
     
    #define EXTI_EMR_MR7   EXTI_EMR_MR7_Msk
     
    #define EXTI_EMR_MR8_Pos   (8U)
     
    #define EXTI_EMR_MR8_Msk   (0x1UL << EXTI_EMR_MR8_Pos)
     
    #define EXTI_EMR_MR8   EXTI_EMR_MR8_Msk
     
    #define EXTI_EMR_MR9_Pos   (9U)
     
    #define EXTI_EMR_MR9_Msk   (0x1UL << EXTI_EMR_MR9_Pos)
     
    #define EXTI_EMR_MR9   EXTI_EMR_MR9_Msk
     
    #define EXTI_EMR_MR10_Pos   (10U)
     
    #define EXTI_EMR_MR10_Msk   (0x1UL << EXTI_EMR_MR10_Pos)
     
    #define EXTI_EMR_MR10   EXTI_EMR_MR10_Msk
     
    #define EXTI_EMR_MR11_Pos   (11U)
     
    #define EXTI_EMR_MR11_Msk   (0x1UL << EXTI_EMR_MR11_Pos)
     
    #define EXTI_EMR_MR11   EXTI_EMR_MR11_Msk
     
    #define EXTI_EMR_MR12_Pos   (12U)
     
    #define EXTI_EMR_MR12_Msk   (0x1UL << EXTI_EMR_MR12_Pos)
     
    #define EXTI_EMR_MR12   EXTI_EMR_MR12_Msk
     
    #define EXTI_EMR_MR13_Pos   (13U)
     
    #define EXTI_EMR_MR13_Msk   (0x1UL << EXTI_EMR_MR13_Pos)
     
    #define EXTI_EMR_MR13   EXTI_EMR_MR13_Msk
     
    #define EXTI_EMR_MR14_Pos   (14U)
     
    #define EXTI_EMR_MR14_Msk   (0x1UL << EXTI_EMR_MR14_Pos)
     
    #define EXTI_EMR_MR14   EXTI_EMR_MR14_Msk
     
    #define EXTI_EMR_MR15_Pos   (15U)
     
    #define EXTI_EMR_MR15_Msk   (0x1UL << EXTI_EMR_MR15_Pos)
     
    #define EXTI_EMR_MR15   EXTI_EMR_MR15_Msk
     
    #define EXTI_EMR_MR16_Pos   (16U)
     
    #define EXTI_EMR_MR16_Msk   (0x1UL << EXTI_EMR_MR16_Pos)
     
    #define EXTI_EMR_MR16   EXTI_EMR_MR16_Msk
     
    #define EXTI_EMR_MR17_Pos   (17U)
     
    #define EXTI_EMR_MR17_Msk   (0x1UL << EXTI_EMR_MR17_Pos)
     
    #define EXTI_EMR_MR17   EXTI_EMR_MR17_Msk
     
    #define EXTI_EMR_MR18_Pos   (18U)
     
    #define EXTI_EMR_MR18_Msk   (0x1UL << EXTI_EMR_MR18_Pos)
     
    #define EXTI_EMR_MR18   EXTI_EMR_MR18_Msk
     
    #define EXTI_EMR_MR19_Pos   (19U)
     
    #define EXTI_EMR_MR19_Msk   (0x1UL << EXTI_EMR_MR19_Pos)
     
    #define EXTI_EMR_MR19   EXTI_EMR_MR19_Msk
     
    #define EXTI_EMR_MR20_Pos   (20U)
     
    #define EXTI_EMR_MR20_Msk   (0x1UL << EXTI_EMR_MR20_Pos)
     
    #define EXTI_EMR_MR20   EXTI_EMR_MR20_Msk
     
    #define EXTI_EMR_MR21_Pos   (21U)
     
    #define EXTI_EMR_MR21_Msk   (0x1UL << EXTI_EMR_MR21_Pos)
     
    #define EXTI_EMR_MR21   EXTI_EMR_MR21_Msk
     
    #define EXTI_EMR_MR22_Pos   (22U)
     
    #define EXTI_EMR_MR22_Msk   (0x1UL << EXTI_EMR_MR22_Pos)
     
    #define EXTI_EMR_MR22   EXTI_EMR_MR22_Msk
     
    #define EXTI_EMR_EM0   EXTI_EMR_MR0
     
    #define EXTI_EMR_EM1   EXTI_EMR_MR1
     
    #define EXTI_EMR_EM2   EXTI_EMR_MR2
     
    #define EXTI_EMR_EM3   EXTI_EMR_MR3
     
    #define EXTI_EMR_EM4   EXTI_EMR_MR4
     
    #define EXTI_EMR_EM5   EXTI_EMR_MR5
     
    #define EXTI_EMR_EM6   EXTI_EMR_MR6
     
    #define EXTI_EMR_EM7   EXTI_EMR_MR7
     
    #define EXTI_EMR_EM8   EXTI_EMR_MR8
     
    #define EXTI_EMR_EM9   EXTI_EMR_MR9
     
    #define EXTI_EMR_EM10   EXTI_EMR_MR10
     
    #define EXTI_EMR_EM11   EXTI_EMR_MR11
     
    #define EXTI_EMR_EM12   EXTI_EMR_MR12
     
    #define EXTI_EMR_EM13   EXTI_EMR_MR13
     
    #define EXTI_EMR_EM14   EXTI_EMR_MR14
     
    #define EXTI_EMR_EM15   EXTI_EMR_MR15
     
    #define EXTI_EMR_EM16   EXTI_EMR_MR16
     
    #define EXTI_EMR_EM17   EXTI_EMR_MR17
     
    #define EXTI_EMR_EM18   EXTI_EMR_MR18
     
    #define EXTI_EMR_EM19   EXTI_EMR_MR19
     
    #define EXTI_EMR_EM20   EXTI_EMR_MR20
     
    #define EXTI_EMR_EM21   EXTI_EMR_MR21
     
    #define EXTI_EMR_EM22   EXTI_EMR_MR22
     
    #define EXTI_RTSR_TR0_Pos   (0U)
     
    #define EXTI_RTSR_TR0_Msk   (0x1UL << EXTI_RTSR_TR0_Pos)
     
    #define EXTI_RTSR_TR0   EXTI_RTSR_TR0_Msk
     
    #define EXTI_RTSR_TR1_Pos   (1U)
     
    #define EXTI_RTSR_TR1_Msk   (0x1UL << EXTI_RTSR_TR1_Pos)
     
    #define EXTI_RTSR_TR1   EXTI_RTSR_TR1_Msk
     
    #define EXTI_RTSR_TR2_Pos   (2U)
     
    #define EXTI_RTSR_TR2_Msk   (0x1UL << EXTI_RTSR_TR2_Pos)
     
    #define EXTI_RTSR_TR2   EXTI_RTSR_TR2_Msk
     
    #define EXTI_RTSR_TR3_Pos   (3U)
     
    #define EXTI_RTSR_TR3_Msk   (0x1UL << EXTI_RTSR_TR3_Pos)
     
    #define EXTI_RTSR_TR3   EXTI_RTSR_TR3_Msk
     
    #define EXTI_RTSR_TR4_Pos   (4U)
     
    #define EXTI_RTSR_TR4_Msk   (0x1UL << EXTI_RTSR_TR4_Pos)
     
    #define EXTI_RTSR_TR4   EXTI_RTSR_TR4_Msk
     
    #define EXTI_RTSR_TR5_Pos   (5U)
     
    #define EXTI_RTSR_TR5_Msk   (0x1UL << EXTI_RTSR_TR5_Pos)
     
    #define EXTI_RTSR_TR5   EXTI_RTSR_TR5_Msk
     
    #define EXTI_RTSR_TR6_Pos   (6U)
     
    #define EXTI_RTSR_TR6_Msk   (0x1UL << EXTI_RTSR_TR6_Pos)
     
    #define EXTI_RTSR_TR6   EXTI_RTSR_TR6_Msk
     
    #define EXTI_RTSR_TR7_Pos   (7U)
     
    #define EXTI_RTSR_TR7_Msk   (0x1UL << EXTI_RTSR_TR7_Pos)
     
    #define EXTI_RTSR_TR7   EXTI_RTSR_TR7_Msk
     
    #define EXTI_RTSR_TR8_Pos   (8U)
     
    #define EXTI_RTSR_TR8_Msk   (0x1UL << EXTI_RTSR_TR8_Pos)
     
    #define EXTI_RTSR_TR8   EXTI_RTSR_TR8_Msk
     
    #define EXTI_RTSR_TR9_Pos   (9U)
     
    #define EXTI_RTSR_TR9_Msk   (0x1UL << EXTI_RTSR_TR9_Pos)
     
    #define EXTI_RTSR_TR9   EXTI_RTSR_TR9_Msk
     
    #define EXTI_RTSR_TR10_Pos   (10U)
     
    #define EXTI_RTSR_TR10_Msk   (0x1UL << EXTI_RTSR_TR10_Pos)
     
    #define EXTI_RTSR_TR10   EXTI_RTSR_TR10_Msk
     
    #define EXTI_RTSR_TR11_Pos   (11U)
     
    #define EXTI_RTSR_TR11_Msk   (0x1UL << EXTI_RTSR_TR11_Pos)
     
    #define EXTI_RTSR_TR11   EXTI_RTSR_TR11_Msk
     
    #define EXTI_RTSR_TR12_Pos   (12U)
     
    #define EXTI_RTSR_TR12_Msk   (0x1UL << EXTI_RTSR_TR12_Pos)
     
    #define EXTI_RTSR_TR12   EXTI_RTSR_TR12_Msk
     
    #define EXTI_RTSR_TR13_Pos   (13U)
     
    #define EXTI_RTSR_TR13_Msk   (0x1UL << EXTI_RTSR_TR13_Pos)
     
    #define EXTI_RTSR_TR13   EXTI_RTSR_TR13_Msk
     
    #define EXTI_RTSR_TR14_Pos   (14U)
     
    #define EXTI_RTSR_TR14_Msk   (0x1UL << EXTI_RTSR_TR14_Pos)
     
    #define EXTI_RTSR_TR14   EXTI_RTSR_TR14_Msk
     
    #define EXTI_RTSR_TR15_Pos   (15U)
     
    #define EXTI_RTSR_TR15_Msk   (0x1UL << EXTI_RTSR_TR15_Pos)
     
    #define EXTI_RTSR_TR15   EXTI_RTSR_TR15_Msk
     
    #define EXTI_RTSR_TR16_Pos   (16U)
     
    #define EXTI_RTSR_TR16_Msk   (0x1UL << EXTI_RTSR_TR16_Pos)
     
    #define EXTI_RTSR_TR16   EXTI_RTSR_TR16_Msk
     
    #define EXTI_RTSR_TR17_Pos   (17U)
     
    #define EXTI_RTSR_TR17_Msk   (0x1UL << EXTI_RTSR_TR17_Pos)
     
    #define EXTI_RTSR_TR17   EXTI_RTSR_TR17_Msk
     
    #define EXTI_RTSR_TR18_Pos   (18U)
     
    #define EXTI_RTSR_TR18_Msk   (0x1UL << EXTI_RTSR_TR18_Pos)
     
    #define EXTI_RTSR_TR18   EXTI_RTSR_TR18_Msk
     
    #define EXTI_RTSR_TR19_Pos   (19U)
     
    #define EXTI_RTSR_TR19_Msk   (0x1UL << EXTI_RTSR_TR19_Pos)
     
    #define EXTI_RTSR_TR19   EXTI_RTSR_TR19_Msk
     
    #define EXTI_RTSR_TR20_Pos   (20U)
     
    #define EXTI_RTSR_TR20_Msk   (0x1UL << EXTI_RTSR_TR20_Pos)
     
    #define EXTI_RTSR_TR20   EXTI_RTSR_TR20_Msk
     
    #define EXTI_RTSR_TR21_Pos   (21U)
     
    #define EXTI_RTSR_TR21_Msk   (0x1UL << EXTI_RTSR_TR21_Pos)
     
    #define EXTI_RTSR_TR21   EXTI_RTSR_TR21_Msk
     
    #define EXTI_RTSR_TR22_Pos   (22U)
     
    #define EXTI_RTSR_TR22_Msk   (0x1UL << EXTI_RTSR_TR22_Pos)
     
    #define EXTI_RTSR_TR22   EXTI_RTSR_TR22_Msk
     
    #define EXTI_FTSR_TR0_Pos   (0U)
     
    #define EXTI_FTSR_TR0_Msk   (0x1UL << EXTI_FTSR_TR0_Pos)
     
    #define EXTI_FTSR_TR0   EXTI_FTSR_TR0_Msk
     
    #define EXTI_FTSR_TR1_Pos   (1U)
     
    #define EXTI_FTSR_TR1_Msk   (0x1UL << EXTI_FTSR_TR1_Pos)
     
    #define EXTI_FTSR_TR1   EXTI_FTSR_TR1_Msk
     
    #define EXTI_FTSR_TR2_Pos   (2U)
     
    #define EXTI_FTSR_TR2_Msk   (0x1UL << EXTI_FTSR_TR2_Pos)
     
    #define EXTI_FTSR_TR2   EXTI_FTSR_TR2_Msk
     
    #define EXTI_FTSR_TR3_Pos   (3U)
     
    #define EXTI_FTSR_TR3_Msk   (0x1UL << EXTI_FTSR_TR3_Pos)
     
    #define EXTI_FTSR_TR3   EXTI_FTSR_TR3_Msk
     
    #define EXTI_FTSR_TR4_Pos   (4U)
     
    #define EXTI_FTSR_TR4_Msk   (0x1UL << EXTI_FTSR_TR4_Pos)
     
    #define EXTI_FTSR_TR4   EXTI_FTSR_TR4_Msk
     
    #define EXTI_FTSR_TR5_Pos   (5U)
     
    #define EXTI_FTSR_TR5_Msk   (0x1UL << EXTI_FTSR_TR5_Pos)
     
    #define EXTI_FTSR_TR5   EXTI_FTSR_TR5_Msk
     
    #define EXTI_FTSR_TR6_Pos   (6U)
     
    #define EXTI_FTSR_TR6_Msk   (0x1UL << EXTI_FTSR_TR6_Pos)
     
    #define EXTI_FTSR_TR6   EXTI_FTSR_TR6_Msk
     
    #define EXTI_FTSR_TR7_Pos   (7U)
     
    #define EXTI_FTSR_TR7_Msk   (0x1UL << EXTI_FTSR_TR7_Pos)
     
    #define EXTI_FTSR_TR7   EXTI_FTSR_TR7_Msk
     
    #define EXTI_FTSR_TR8_Pos   (8U)
     
    #define EXTI_FTSR_TR8_Msk   (0x1UL << EXTI_FTSR_TR8_Pos)
     
    #define EXTI_FTSR_TR8   EXTI_FTSR_TR8_Msk
     
    #define EXTI_FTSR_TR9_Pos   (9U)
     
    #define EXTI_FTSR_TR9_Msk   (0x1UL << EXTI_FTSR_TR9_Pos)
     
    #define EXTI_FTSR_TR9   EXTI_FTSR_TR9_Msk
     
    #define EXTI_FTSR_TR10_Pos   (10U)
     
    #define EXTI_FTSR_TR10_Msk   (0x1UL << EXTI_FTSR_TR10_Pos)
     
    #define EXTI_FTSR_TR10   EXTI_FTSR_TR10_Msk
     
    #define EXTI_FTSR_TR11_Pos   (11U)
     
    #define EXTI_FTSR_TR11_Msk   (0x1UL << EXTI_FTSR_TR11_Pos)
     
    #define EXTI_FTSR_TR11   EXTI_FTSR_TR11_Msk
     
    #define EXTI_FTSR_TR12_Pos   (12U)
     
    #define EXTI_FTSR_TR12_Msk   (0x1UL << EXTI_FTSR_TR12_Pos)
     
    #define EXTI_FTSR_TR12   EXTI_FTSR_TR12_Msk
     
    #define EXTI_FTSR_TR13_Pos   (13U)
     
    #define EXTI_FTSR_TR13_Msk   (0x1UL << EXTI_FTSR_TR13_Pos)
     
    #define EXTI_FTSR_TR13   EXTI_FTSR_TR13_Msk
     
    #define EXTI_FTSR_TR14_Pos   (14U)
     
    #define EXTI_FTSR_TR14_Msk   (0x1UL << EXTI_FTSR_TR14_Pos)
     
    #define EXTI_FTSR_TR14   EXTI_FTSR_TR14_Msk
     
    #define EXTI_FTSR_TR15_Pos   (15U)
     
    #define EXTI_FTSR_TR15_Msk   (0x1UL << EXTI_FTSR_TR15_Pos)
     
    #define EXTI_FTSR_TR15   EXTI_FTSR_TR15_Msk
     
    #define EXTI_FTSR_TR16_Pos   (16U)
     
    #define EXTI_FTSR_TR16_Msk   (0x1UL << EXTI_FTSR_TR16_Pos)
     
    #define EXTI_FTSR_TR16   EXTI_FTSR_TR16_Msk
     
    #define EXTI_FTSR_TR17_Pos   (17U)
     
    #define EXTI_FTSR_TR17_Msk   (0x1UL << EXTI_FTSR_TR17_Pos)
     
    #define EXTI_FTSR_TR17   EXTI_FTSR_TR17_Msk
     
    #define EXTI_FTSR_TR18_Pos   (18U)
     
    #define EXTI_FTSR_TR18_Msk   (0x1UL << EXTI_FTSR_TR18_Pos)
     
    #define EXTI_FTSR_TR18   EXTI_FTSR_TR18_Msk
     
    #define EXTI_FTSR_TR19_Pos   (19U)
     
    #define EXTI_FTSR_TR19_Msk   (0x1UL << EXTI_FTSR_TR19_Pos)
     
    #define EXTI_FTSR_TR19   EXTI_FTSR_TR19_Msk
     
    #define EXTI_FTSR_TR20_Pos   (20U)
     
    #define EXTI_FTSR_TR20_Msk   (0x1UL << EXTI_FTSR_TR20_Pos)
     
    #define EXTI_FTSR_TR20   EXTI_FTSR_TR20_Msk
     
    #define EXTI_FTSR_TR21_Pos   (21U)
     
    #define EXTI_FTSR_TR21_Msk   (0x1UL << EXTI_FTSR_TR21_Pos)
     
    #define EXTI_FTSR_TR21   EXTI_FTSR_TR21_Msk
     
    #define EXTI_FTSR_TR22_Pos   (22U)
     
    #define EXTI_FTSR_TR22_Msk   (0x1UL << EXTI_FTSR_TR22_Pos)
     
    #define EXTI_FTSR_TR22   EXTI_FTSR_TR22_Msk
     
    #define EXTI_SWIER_SWIER0_Pos   (0U)
     
    #define EXTI_SWIER_SWIER0_Msk   (0x1UL << EXTI_SWIER_SWIER0_Pos)
     
    #define EXTI_SWIER_SWIER0   EXTI_SWIER_SWIER0_Msk
     
    #define EXTI_SWIER_SWIER1_Pos   (1U)
     
    #define EXTI_SWIER_SWIER1_Msk   (0x1UL << EXTI_SWIER_SWIER1_Pos)
     
    #define EXTI_SWIER_SWIER1   EXTI_SWIER_SWIER1_Msk
     
    #define EXTI_SWIER_SWIER2_Pos   (2U)
     
    #define EXTI_SWIER_SWIER2_Msk   (0x1UL << EXTI_SWIER_SWIER2_Pos)
     
    #define EXTI_SWIER_SWIER2   EXTI_SWIER_SWIER2_Msk
     
    #define EXTI_SWIER_SWIER3_Pos   (3U)
     
    #define EXTI_SWIER_SWIER3_Msk   (0x1UL << EXTI_SWIER_SWIER3_Pos)
     
    #define EXTI_SWIER_SWIER3   EXTI_SWIER_SWIER3_Msk
     
    #define EXTI_SWIER_SWIER4_Pos   (4U)
     
    #define EXTI_SWIER_SWIER4_Msk   (0x1UL << EXTI_SWIER_SWIER4_Pos)
     
    #define EXTI_SWIER_SWIER4   EXTI_SWIER_SWIER4_Msk
     
    #define EXTI_SWIER_SWIER5_Pos   (5U)
     
    #define EXTI_SWIER_SWIER5_Msk   (0x1UL << EXTI_SWIER_SWIER5_Pos)
     
    #define EXTI_SWIER_SWIER5   EXTI_SWIER_SWIER5_Msk
     
    #define EXTI_SWIER_SWIER6_Pos   (6U)
     
    #define EXTI_SWIER_SWIER6_Msk   (0x1UL << EXTI_SWIER_SWIER6_Pos)
     
    #define EXTI_SWIER_SWIER6   EXTI_SWIER_SWIER6_Msk
     
    #define EXTI_SWIER_SWIER7_Pos   (7U)
     
    #define EXTI_SWIER_SWIER7_Msk   (0x1UL << EXTI_SWIER_SWIER7_Pos)
     
    #define EXTI_SWIER_SWIER7   EXTI_SWIER_SWIER7_Msk
     
    #define EXTI_SWIER_SWIER8_Pos   (8U)
     
    #define EXTI_SWIER_SWIER8_Msk   (0x1UL << EXTI_SWIER_SWIER8_Pos)
     
    #define EXTI_SWIER_SWIER8   EXTI_SWIER_SWIER8_Msk
     
    #define EXTI_SWIER_SWIER9_Pos   (9U)
     
    #define EXTI_SWIER_SWIER9_Msk   (0x1UL << EXTI_SWIER_SWIER9_Pos)
     
    #define EXTI_SWIER_SWIER9   EXTI_SWIER_SWIER9_Msk
     
    #define EXTI_SWIER_SWIER10_Pos   (10U)
     
    #define EXTI_SWIER_SWIER10_Msk   (0x1UL << EXTI_SWIER_SWIER10_Pos)
     
    #define EXTI_SWIER_SWIER10   EXTI_SWIER_SWIER10_Msk
     
    #define EXTI_SWIER_SWIER11_Pos   (11U)
     
    #define EXTI_SWIER_SWIER11_Msk   (0x1UL << EXTI_SWIER_SWIER11_Pos)
     
    #define EXTI_SWIER_SWIER11   EXTI_SWIER_SWIER11_Msk
     
    #define EXTI_SWIER_SWIER12_Pos   (12U)
     
    #define EXTI_SWIER_SWIER12_Msk   (0x1UL << EXTI_SWIER_SWIER12_Pos)
     
    #define EXTI_SWIER_SWIER12   EXTI_SWIER_SWIER12_Msk
     
    #define EXTI_SWIER_SWIER13_Pos   (13U)
     
    #define EXTI_SWIER_SWIER13_Msk   (0x1UL << EXTI_SWIER_SWIER13_Pos)
     
    #define EXTI_SWIER_SWIER13   EXTI_SWIER_SWIER13_Msk
     
    #define EXTI_SWIER_SWIER14_Pos   (14U)
     
    #define EXTI_SWIER_SWIER14_Msk   (0x1UL << EXTI_SWIER_SWIER14_Pos)
     
    #define EXTI_SWIER_SWIER14   EXTI_SWIER_SWIER14_Msk
     
    #define EXTI_SWIER_SWIER15_Pos   (15U)
     
    #define EXTI_SWIER_SWIER15_Msk   (0x1UL << EXTI_SWIER_SWIER15_Pos)
     
    #define EXTI_SWIER_SWIER15   EXTI_SWIER_SWIER15_Msk
     
    #define EXTI_SWIER_SWIER16_Pos   (16U)
     
    #define EXTI_SWIER_SWIER16_Msk   (0x1UL << EXTI_SWIER_SWIER16_Pos)
     
    #define EXTI_SWIER_SWIER16   EXTI_SWIER_SWIER16_Msk
     
    #define EXTI_SWIER_SWIER17_Pos   (17U)
     
    #define EXTI_SWIER_SWIER17_Msk   (0x1UL << EXTI_SWIER_SWIER17_Pos)
     
    #define EXTI_SWIER_SWIER17   EXTI_SWIER_SWIER17_Msk
     
    #define EXTI_SWIER_SWIER18_Pos   (18U)
     
    #define EXTI_SWIER_SWIER18_Msk   (0x1UL << EXTI_SWIER_SWIER18_Pos)
     
    #define EXTI_SWIER_SWIER18   EXTI_SWIER_SWIER18_Msk
     
    #define EXTI_SWIER_SWIER19_Pos   (19U)
     
    #define EXTI_SWIER_SWIER19_Msk   (0x1UL << EXTI_SWIER_SWIER19_Pos)
     
    #define EXTI_SWIER_SWIER19   EXTI_SWIER_SWIER19_Msk
     
    #define EXTI_SWIER_SWIER20_Pos   (20U)
     
    #define EXTI_SWIER_SWIER20_Msk   (0x1UL << EXTI_SWIER_SWIER20_Pos)
     
    #define EXTI_SWIER_SWIER20   EXTI_SWIER_SWIER20_Msk
     
    #define EXTI_SWIER_SWIER21_Pos   (21U)
     
    #define EXTI_SWIER_SWIER21_Msk   (0x1UL << EXTI_SWIER_SWIER21_Pos)
     
    #define EXTI_SWIER_SWIER21   EXTI_SWIER_SWIER21_Msk
     
    #define EXTI_SWIER_SWIER22_Pos   (22U)
     
    #define EXTI_SWIER_SWIER22_Msk   (0x1UL << EXTI_SWIER_SWIER22_Pos)
     
    #define EXTI_SWIER_SWIER22   EXTI_SWIER_SWIER22_Msk
     
    #define EXTI_PR_PR0_Pos   (0U)
     
    #define EXTI_PR_PR0_Msk   (0x1UL << EXTI_PR_PR0_Pos)
     
    #define EXTI_PR_PR0   EXTI_PR_PR0_Msk
     
    #define EXTI_PR_PR1_Pos   (1U)
     
    #define EXTI_PR_PR1_Msk   (0x1UL << EXTI_PR_PR1_Pos)
     
    #define EXTI_PR_PR1   EXTI_PR_PR1_Msk
     
    #define EXTI_PR_PR2_Pos   (2U)
     
    #define EXTI_PR_PR2_Msk   (0x1UL << EXTI_PR_PR2_Pos)
     
    #define EXTI_PR_PR2   EXTI_PR_PR2_Msk
     
    #define EXTI_PR_PR3_Pos   (3U)
     
    #define EXTI_PR_PR3_Msk   (0x1UL << EXTI_PR_PR3_Pos)
     
    #define EXTI_PR_PR3   EXTI_PR_PR3_Msk
     
    #define EXTI_PR_PR4_Pos   (4U)
     
    #define EXTI_PR_PR4_Msk   (0x1UL << EXTI_PR_PR4_Pos)
     
    #define EXTI_PR_PR4   EXTI_PR_PR4_Msk
     
    #define EXTI_PR_PR5_Pos   (5U)
     
    #define EXTI_PR_PR5_Msk   (0x1UL << EXTI_PR_PR5_Pos)
     
    #define EXTI_PR_PR5   EXTI_PR_PR5_Msk
     
    #define EXTI_PR_PR6_Pos   (6U)
     
    #define EXTI_PR_PR6_Msk   (0x1UL << EXTI_PR_PR6_Pos)
     
    #define EXTI_PR_PR6   EXTI_PR_PR6_Msk
     
    #define EXTI_PR_PR7_Pos   (7U)
     
    #define EXTI_PR_PR7_Msk   (0x1UL << EXTI_PR_PR7_Pos)
     
    #define EXTI_PR_PR7   EXTI_PR_PR7_Msk
     
    #define EXTI_PR_PR8_Pos   (8U)
     
    #define EXTI_PR_PR8_Msk   (0x1UL << EXTI_PR_PR8_Pos)
     
    #define EXTI_PR_PR8   EXTI_PR_PR8_Msk
     
    #define EXTI_PR_PR9_Pos   (9U)
     
    #define EXTI_PR_PR9_Msk   (0x1UL << EXTI_PR_PR9_Pos)
     
    #define EXTI_PR_PR9   EXTI_PR_PR9_Msk
     
    #define EXTI_PR_PR10_Pos   (10U)
     
    #define EXTI_PR_PR10_Msk   (0x1UL << EXTI_PR_PR10_Pos)
     
    #define EXTI_PR_PR10   EXTI_PR_PR10_Msk
     
    #define EXTI_PR_PR11_Pos   (11U)
     
    #define EXTI_PR_PR11_Msk   (0x1UL << EXTI_PR_PR11_Pos)
     
    #define EXTI_PR_PR11   EXTI_PR_PR11_Msk
     
    #define EXTI_PR_PR12_Pos   (12U)
     
    #define EXTI_PR_PR12_Msk   (0x1UL << EXTI_PR_PR12_Pos)
     
    #define EXTI_PR_PR12   EXTI_PR_PR12_Msk
     
    #define EXTI_PR_PR13_Pos   (13U)
     
    #define EXTI_PR_PR13_Msk   (0x1UL << EXTI_PR_PR13_Pos)
     
    #define EXTI_PR_PR13   EXTI_PR_PR13_Msk
     
    #define EXTI_PR_PR14_Pos   (14U)
     
    #define EXTI_PR_PR14_Msk   (0x1UL << EXTI_PR_PR14_Pos)
     
    #define EXTI_PR_PR14   EXTI_PR_PR14_Msk
     
    #define EXTI_PR_PR15_Pos   (15U)
     
    #define EXTI_PR_PR15_Msk   (0x1UL << EXTI_PR_PR15_Pos)
     
    #define EXTI_PR_PR15   EXTI_PR_PR15_Msk
     
    #define EXTI_PR_PR16_Pos   (16U)
     
    #define EXTI_PR_PR16_Msk   (0x1UL << EXTI_PR_PR16_Pos)
     
    #define EXTI_PR_PR16   EXTI_PR_PR16_Msk
     
    #define EXTI_PR_PR17_Pos   (17U)
     
    #define EXTI_PR_PR17_Msk   (0x1UL << EXTI_PR_PR17_Pos)
     
    #define EXTI_PR_PR17   EXTI_PR_PR17_Msk
     
    #define EXTI_PR_PR18_Pos   (18U)
     
    #define EXTI_PR_PR18_Msk   (0x1UL << EXTI_PR_PR18_Pos)
     
    #define EXTI_PR_PR18   EXTI_PR_PR18_Msk
     
    #define EXTI_PR_PR19_Pos   (19U)
     
    #define EXTI_PR_PR19_Msk   (0x1UL << EXTI_PR_PR19_Pos)
     
    #define EXTI_PR_PR19   EXTI_PR_PR19_Msk
     
    #define EXTI_PR_PR20_Pos   (20U)
     
    #define EXTI_PR_PR20_Msk   (0x1UL << EXTI_PR_PR20_Pos)
     
    #define EXTI_PR_PR20   EXTI_PR_PR20_Msk
     
    #define EXTI_PR_PR21_Pos   (21U)
     
    #define EXTI_PR_PR21_Msk   (0x1UL << EXTI_PR_PR21_Pos)
     
    #define EXTI_PR_PR21   EXTI_PR_PR21_Msk
     
    #define EXTI_PR_PR22_Pos   (22U)
     
    #define EXTI_PR_PR22_Msk   (0x1UL << EXTI_PR_PR22_Pos)
     
    #define EXTI_PR_PR22   EXTI_PR_PR22_Msk
     
    #define FLASH_ACR_LATENCY_Pos   (0U)
     
    #define FLASH_ACR_LATENCY_Msk   (0x7UL << FLASH_ACR_LATENCY_Pos)
     
    #define FLASH_ACR_LATENCY   FLASH_ACR_LATENCY_Msk
     
    #define FLASH_ACR_LATENCY_0WS   0x00000000U
     
    #define FLASH_ACR_LATENCY_1WS   0x00000001U
     
    #define FLASH_ACR_LATENCY_2WS   0x00000002U
     
    #define FLASH_ACR_LATENCY_3WS   0x00000003U
     
    #define FLASH_ACR_LATENCY_4WS   0x00000004U
     
    #define FLASH_ACR_LATENCY_5WS   0x00000005U
     
    #define FLASH_ACR_LATENCY_6WS   0x00000006U
     
    #define FLASH_ACR_LATENCY_7WS   0x00000007U
     
    #define FLASH_ACR_PRFTEN_Pos   (8U)
     
    #define FLASH_ACR_PRFTEN_Msk   (0x1UL << FLASH_ACR_PRFTEN_Pos)
     
    #define FLASH_ACR_PRFTEN   FLASH_ACR_PRFTEN_Msk
     
    #define FLASH_ACR_ICEN_Pos   (9U)
     
    #define FLASH_ACR_ICEN_Msk   (0x1UL << FLASH_ACR_ICEN_Pos)
     
    #define FLASH_ACR_ICEN   FLASH_ACR_ICEN_Msk
     
    #define FLASH_ACR_DCEN_Pos   (10U)
     
    #define FLASH_ACR_DCEN_Msk   (0x1UL << FLASH_ACR_DCEN_Pos)
     
    #define FLASH_ACR_DCEN   FLASH_ACR_DCEN_Msk
     
    #define FLASH_ACR_ICRST_Pos   (11U)
     
    #define FLASH_ACR_ICRST_Msk   (0x1UL << FLASH_ACR_ICRST_Pos)
     
    #define FLASH_ACR_ICRST   FLASH_ACR_ICRST_Msk
     
    #define FLASH_ACR_DCRST_Pos   (12U)
     
    #define FLASH_ACR_DCRST_Msk   (0x1UL << FLASH_ACR_DCRST_Pos)
     
    #define FLASH_ACR_DCRST   FLASH_ACR_DCRST_Msk
     
    #define FLASH_ACR_BYTE0_ADDRESS_Pos   (10U)
     
    #define FLASH_ACR_BYTE0_ADDRESS_Msk   (0x10008FUL << FLASH_ACR_BYTE0_ADDRESS_Pos)
     
    #define FLASH_ACR_BYTE0_ADDRESS   FLASH_ACR_BYTE0_ADDRESS_Msk
     
    #define FLASH_ACR_BYTE2_ADDRESS_Pos   (0U)
     
    #define FLASH_ACR_BYTE2_ADDRESS_Msk   (0x40023C03UL << FLASH_ACR_BYTE2_ADDRESS_Pos)
     
    #define FLASH_ACR_BYTE2_ADDRESS   FLASH_ACR_BYTE2_ADDRESS_Msk
     
    #define FLASH_SR_EOP_Pos   (0U)
     
    #define FLASH_SR_EOP_Msk   (0x1UL << FLASH_SR_EOP_Pos)
     
    #define FLASH_SR_EOP   FLASH_SR_EOP_Msk
     
    #define FLASH_SR_SOP_Pos   (1U)
     
    #define FLASH_SR_SOP_Msk   (0x1UL << FLASH_SR_SOP_Pos)
     
    #define FLASH_SR_SOP   FLASH_SR_SOP_Msk
     
    #define FLASH_SR_WRPERR_Pos   (4U)
     
    #define FLASH_SR_WRPERR_Msk   (0x1UL << FLASH_SR_WRPERR_Pos)
     
    #define FLASH_SR_WRPERR   FLASH_SR_WRPERR_Msk
     
    #define FLASH_SR_PGAERR_Pos   (5U)
     
    #define FLASH_SR_PGAERR_Msk   (0x1UL << FLASH_SR_PGAERR_Pos)
     
    #define FLASH_SR_PGAERR   FLASH_SR_PGAERR_Msk
     
    #define FLASH_SR_PGPERR_Pos   (6U)
     
    #define FLASH_SR_PGPERR_Msk   (0x1UL << FLASH_SR_PGPERR_Pos)
     
    #define FLASH_SR_PGPERR   FLASH_SR_PGPERR_Msk
     
    #define FLASH_SR_PGSERR_Pos   (7U)
     
    #define FLASH_SR_PGSERR_Msk   (0x1UL << FLASH_SR_PGSERR_Pos)
     
    #define FLASH_SR_PGSERR   FLASH_SR_PGSERR_Msk
     
    #define FLASH_SR_BSY_Pos   (16U)
     
    #define FLASH_SR_BSY_Msk   (0x1UL << FLASH_SR_BSY_Pos)
     
    #define FLASH_SR_BSY   FLASH_SR_BSY_Msk
     
    #define FLASH_CR_PG_Pos   (0U)
     
    #define FLASH_CR_PG_Msk   (0x1UL << FLASH_CR_PG_Pos)
     
    #define FLASH_CR_PG   FLASH_CR_PG_Msk
     
    #define FLASH_CR_SER_Pos   (1U)
     
    #define FLASH_CR_SER_Msk   (0x1UL << FLASH_CR_SER_Pos)
     
    #define FLASH_CR_SER   FLASH_CR_SER_Msk
     
    #define FLASH_CR_MER_Pos   (2U)
     
    #define FLASH_CR_MER_Msk   (0x1UL << FLASH_CR_MER_Pos)
     
    #define FLASH_CR_MER   FLASH_CR_MER_Msk
     
    #define FLASH_CR_SNB_Pos   (3U)
     
    #define FLASH_CR_SNB_Msk   (0x1FUL << FLASH_CR_SNB_Pos)
     
    #define FLASH_CR_SNB   FLASH_CR_SNB_Msk
     
    #define FLASH_CR_SNB_0   (0x01UL << FLASH_CR_SNB_Pos)
     
    #define FLASH_CR_SNB_1   (0x02UL << FLASH_CR_SNB_Pos)
     
    #define FLASH_CR_SNB_2   (0x04UL << FLASH_CR_SNB_Pos)
     
    #define FLASH_CR_SNB_3   (0x08UL << FLASH_CR_SNB_Pos)
     
    #define FLASH_CR_SNB_4   (0x10UL << FLASH_CR_SNB_Pos)
     
    #define FLASH_CR_PSIZE_Pos   (8U)
     
    #define FLASH_CR_PSIZE_Msk   (0x3UL << FLASH_CR_PSIZE_Pos)
     
    #define FLASH_CR_PSIZE   FLASH_CR_PSIZE_Msk
     
    #define FLASH_CR_PSIZE_0   (0x1UL << FLASH_CR_PSIZE_Pos)
     
    #define FLASH_CR_PSIZE_1   (0x2UL << FLASH_CR_PSIZE_Pos)
     
    #define FLASH_CR_STRT_Pos   (16U)
     
    #define FLASH_CR_STRT_Msk   (0x1UL << FLASH_CR_STRT_Pos)
     
    #define FLASH_CR_STRT   FLASH_CR_STRT_Msk
     
    #define FLASH_CR_EOPIE_Pos   (24U)
     
    #define FLASH_CR_EOPIE_Msk   (0x1UL << FLASH_CR_EOPIE_Pos)
     
    #define FLASH_CR_EOPIE   FLASH_CR_EOPIE_Msk
     
    #define FLASH_CR_ERRIE_Pos   (25U)
     
    #define FLASH_CR_ERRIE_Msk   (0x1UL << FLASH_CR_ERRIE_Pos)
     
    #define FLASH_CR_ERRIE   FLASH_CR_ERRIE_Msk
     
    #define FLASH_CR_LOCK_Pos   (31U)
     
    #define FLASH_CR_LOCK_Msk   (0x1UL << FLASH_CR_LOCK_Pos)
     
    #define FLASH_CR_LOCK   FLASH_CR_LOCK_Msk
     
    #define FLASH_OPTCR_OPTLOCK_Pos   (0U)
     
    #define FLASH_OPTCR_OPTLOCK_Msk   (0x1UL << FLASH_OPTCR_OPTLOCK_Pos)
     
    #define FLASH_OPTCR_OPTLOCK   FLASH_OPTCR_OPTLOCK_Msk
     
    #define FLASH_OPTCR_OPTSTRT_Pos   (1U)
     
    #define FLASH_OPTCR_OPTSTRT_Msk   (0x1UL << FLASH_OPTCR_OPTSTRT_Pos)
     
    #define FLASH_OPTCR_OPTSTRT   FLASH_OPTCR_OPTSTRT_Msk
     
    #define FLASH_OPTCR_BOR_LEV_0   0x00000004U
     
    #define FLASH_OPTCR_BOR_LEV_1   0x00000008U
     
    #define FLASH_OPTCR_BOR_LEV_Pos   (2U)
     
    #define FLASH_OPTCR_BOR_LEV_Msk   (0x3UL << FLASH_OPTCR_BOR_LEV_Pos)
     
    #define FLASH_OPTCR_BOR_LEV   FLASH_OPTCR_BOR_LEV_Msk
     
    #define FLASH_OPTCR_WDG_SW_Pos   (5U)
     
    #define FLASH_OPTCR_WDG_SW_Msk   (0x1UL << FLASH_OPTCR_WDG_SW_Pos)
     
    #define FLASH_OPTCR_WDG_SW   FLASH_OPTCR_WDG_SW_Msk
     
    #define FLASH_OPTCR_nRST_STOP_Pos   (6U)
     
    #define FLASH_OPTCR_nRST_STOP_Msk   (0x1UL << FLASH_OPTCR_nRST_STOP_Pos)
     
    #define FLASH_OPTCR_nRST_STOP   FLASH_OPTCR_nRST_STOP_Msk
     
    #define FLASH_OPTCR_nRST_STDBY_Pos   (7U)
     
    #define FLASH_OPTCR_nRST_STDBY_Msk   (0x1UL << FLASH_OPTCR_nRST_STDBY_Pos)
     
    #define FLASH_OPTCR_nRST_STDBY   FLASH_OPTCR_nRST_STDBY_Msk
     
    #define FLASH_OPTCR_RDP_Pos   (8U)
     
    #define FLASH_OPTCR_RDP_Msk   (0xFFUL << FLASH_OPTCR_RDP_Pos)
     
    #define FLASH_OPTCR_RDP   FLASH_OPTCR_RDP_Msk
     
    #define FLASH_OPTCR_RDP_0   (0x01UL << FLASH_OPTCR_RDP_Pos)
     
    #define FLASH_OPTCR_RDP_1   (0x02UL << FLASH_OPTCR_RDP_Pos)
     
    #define FLASH_OPTCR_RDP_2   (0x04UL << FLASH_OPTCR_RDP_Pos)
     
    #define FLASH_OPTCR_RDP_3   (0x08UL << FLASH_OPTCR_RDP_Pos)
     
    #define FLASH_OPTCR_RDP_4   (0x10UL << FLASH_OPTCR_RDP_Pos)
     
    #define FLASH_OPTCR_RDP_5   (0x20UL << FLASH_OPTCR_RDP_Pos)
     
    #define FLASH_OPTCR_RDP_6   (0x40UL << FLASH_OPTCR_RDP_Pos)
     
    #define FLASH_OPTCR_RDP_7   (0x80UL << FLASH_OPTCR_RDP_Pos)
     
    #define FLASH_OPTCR_nWRP_Pos   (16U)
     
    #define FLASH_OPTCR_nWRP_Msk   (0xFFFUL << FLASH_OPTCR_nWRP_Pos)
     
    #define FLASH_OPTCR_nWRP   FLASH_OPTCR_nWRP_Msk
     
    #define FLASH_OPTCR_nWRP_0   0x00010000U
     
    #define FLASH_OPTCR_nWRP_1   0x00020000U
     
    #define FLASH_OPTCR_nWRP_2   0x00040000U
     
    #define FLASH_OPTCR_nWRP_3   0x00080000U
     
    #define FLASH_OPTCR_nWRP_4   0x00100000U
     
    #define FLASH_OPTCR_nWRP_5   0x00200000U
     
    #define FLASH_OPTCR_nWRP_6   0x00400000U
     
    #define FLASH_OPTCR_nWRP_7   0x00800000U
     
    #define FLASH_OPTCR_nWRP_8   0x01000000U
     
    #define FLASH_OPTCR_nWRP_9   0x02000000U
     
    #define FLASH_OPTCR_nWRP_10   0x04000000U
     
    #define FLASH_OPTCR_nWRP_11   0x08000000U
     
    #define FLASH_OPTCR1_nWRP_Pos   (16U)
     
    #define FLASH_OPTCR1_nWRP_Msk   (0xFFFUL << FLASH_OPTCR1_nWRP_Pos)
     
    #define FLASH_OPTCR1_nWRP   FLASH_OPTCR1_nWRP_Msk
     
    #define FLASH_OPTCR1_nWRP_0   (0x001UL << FLASH_OPTCR1_nWRP_Pos)
     
    #define FLASH_OPTCR1_nWRP_1   (0x002UL << FLASH_OPTCR1_nWRP_Pos)
     
    #define FLASH_OPTCR1_nWRP_2   (0x004UL << FLASH_OPTCR1_nWRP_Pos)
     
    #define FLASH_OPTCR1_nWRP_3   (0x008UL << FLASH_OPTCR1_nWRP_Pos)
     
    #define FLASH_OPTCR1_nWRP_4   (0x010UL << FLASH_OPTCR1_nWRP_Pos)
     
    #define FLASH_OPTCR1_nWRP_5   (0x020UL << FLASH_OPTCR1_nWRP_Pos)
     
    #define FLASH_OPTCR1_nWRP_6   (0x040UL << FLASH_OPTCR1_nWRP_Pos)
     
    #define FLASH_OPTCR1_nWRP_7   (0x080UL << FLASH_OPTCR1_nWRP_Pos)
     
    #define FLASH_OPTCR1_nWRP_8   (0x100UL << FLASH_OPTCR1_nWRP_Pos)
     
    #define FLASH_OPTCR1_nWRP_9   (0x200UL << FLASH_OPTCR1_nWRP_Pos)
     
    #define FLASH_OPTCR1_nWRP_10   (0x400UL << FLASH_OPTCR1_nWRP_Pos)
     
    #define FLASH_OPTCR1_nWRP_11   (0x800UL << FLASH_OPTCR1_nWRP_Pos)
     
    #define FSMC_BCR1_MBKEN_Pos   (0U)
     
    #define FSMC_BCR1_MBKEN_Msk   (0x1UL << FSMC_BCR1_MBKEN_Pos)
     
    #define FSMC_BCR1_MBKEN   FSMC_BCR1_MBKEN_Msk
     
    #define FSMC_BCR1_MUXEN_Pos   (1U)
     
    #define FSMC_BCR1_MUXEN_Msk   (0x1UL << FSMC_BCR1_MUXEN_Pos)
     
    #define FSMC_BCR1_MUXEN   FSMC_BCR1_MUXEN_Msk
     
    #define FSMC_BCR1_MTYP_Pos   (2U)
     
    #define FSMC_BCR1_MTYP_Msk   (0x3UL << FSMC_BCR1_MTYP_Pos)
     
    #define FSMC_BCR1_MTYP   FSMC_BCR1_MTYP_Msk
     
    #define FSMC_BCR1_MTYP_0   (0x1UL << FSMC_BCR1_MTYP_Pos)
     
    #define FSMC_BCR1_MTYP_1   (0x2UL << FSMC_BCR1_MTYP_Pos)
     
    #define FSMC_BCR1_MWID_Pos   (4U)
     
    #define FSMC_BCR1_MWID_Msk   (0x3UL << FSMC_BCR1_MWID_Pos)
     
    #define FSMC_BCR1_MWID   FSMC_BCR1_MWID_Msk
     
    #define FSMC_BCR1_MWID_0   (0x1UL << FSMC_BCR1_MWID_Pos)
     
    #define FSMC_BCR1_MWID_1   (0x2UL << FSMC_BCR1_MWID_Pos)
     
    #define FSMC_BCR1_FACCEN_Pos   (6U)
     
    #define FSMC_BCR1_FACCEN_Msk   (0x1UL << FSMC_BCR1_FACCEN_Pos)
     
    #define FSMC_BCR1_FACCEN   FSMC_BCR1_FACCEN_Msk
     
    #define FSMC_BCR1_BURSTEN_Pos   (8U)
     
    #define FSMC_BCR1_BURSTEN_Msk   (0x1UL << FSMC_BCR1_BURSTEN_Pos)
     
    #define FSMC_BCR1_BURSTEN   FSMC_BCR1_BURSTEN_Msk
     
    #define FSMC_BCR1_WAITPOL_Pos   (9U)
     
    #define FSMC_BCR1_WAITPOL_Msk   (0x1UL << FSMC_BCR1_WAITPOL_Pos)
     
    #define FSMC_BCR1_WAITPOL   FSMC_BCR1_WAITPOL_Msk
     
    #define FSMC_BCR1_WRAPMOD_Pos   (10U)
     
    #define FSMC_BCR1_WRAPMOD_Msk   (0x1UL << FSMC_BCR1_WRAPMOD_Pos)
     
    #define FSMC_BCR1_WRAPMOD   FSMC_BCR1_WRAPMOD_Msk
     
    #define FSMC_BCR1_WAITCFG_Pos   (11U)
     
    #define FSMC_BCR1_WAITCFG_Msk   (0x1UL << FSMC_BCR1_WAITCFG_Pos)
     
    #define FSMC_BCR1_WAITCFG   FSMC_BCR1_WAITCFG_Msk
     
    #define FSMC_BCR1_WREN_Pos   (12U)
     
    #define FSMC_BCR1_WREN_Msk   (0x1UL << FSMC_BCR1_WREN_Pos)
     
    #define FSMC_BCR1_WREN   FSMC_BCR1_WREN_Msk
     
    #define FSMC_BCR1_WAITEN_Pos   (13U)
     
    #define FSMC_BCR1_WAITEN_Msk   (0x1UL << FSMC_BCR1_WAITEN_Pos)
     
    #define FSMC_BCR1_WAITEN   FSMC_BCR1_WAITEN_Msk
     
    #define FSMC_BCR1_EXTMOD_Pos   (14U)
     
    #define FSMC_BCR1_EXTMOD_Msk   (0x1UL << FSMC_BCR1_EXTMOD_Pos)
     
    #define FSMC_BCR1_EXTMOD   FSMC_BCR1_EXTMOD_Msk
     
    #define FSMC_BCR1_ASYNCWAIT_Pos   (15U)
     
    #define FSMC_BCR1_ASYNCWAIT_Msk   (0x1UL << FSMC_BCR1_ASYNCWAIT_Pos)
     
    #define FSMC_BCR1_ASYNCWAIT   FSMC_BCR1_ASYNCWAIT_Msk
     
    #define FSMC_BCR1_CPSIZE_Pos   (16U)
     
    #define FSMC_BCR1_CPSIZE_Msk   (0x7UL << FSMC_BCR1_CPSIZE_Pos)
     
    #define FSMC_BCR1_CPSIZE   FSMC_BCR1_CPSIZE_Msk
     
    #define FSMC_BCR1_CPSIZE_0   (0x1UL << FSMC_BCR1_CPSIZE_Pos)
     
    #define FSMC_BCR1_CPSIZE_1   (0x2UL << FSMC_BCR1_CPSIZE_Pos)
     
    #define FSMC_BCR1_CPSIZE_2   (0x4UL << FSMC_BCR1_CPSIZE_Pos)
     
    #define FSMC_BCR1_CBURSTRW_Pos   (19U)
     
    #define FSMC_BCR1_CBURSTRW_Msk   (0x1UL << FSMC_BCR1_CBURSTRW_Pos)
     
    #define FSMC_BCR1_CBURSTRW   FSMC_BCR1_CBURSTRW_Msk
     
    #define FSMC_BCR2_MBKEN_Pos   (0U)
     
    #define FSMC_BCR2_MBKEN_Msk   (0x1UL << FSMC_BCR2_MBKEN_Pos)
     
    #define FSMC_BCR2_MBKEN   FSMC_BCR2_MBKEN_Msk
     
    #define FSMC_BCR2_MUXEN_Pos   (1U)
     
    #define FSMC_BCR2_MUXEN_Msk   (0x1UL << FSMC_BCR2_MUXEN_Pos)
     
    #define FSMC_BCR2_MUXEN   FSMC_BCR2_MUXEN_Msk
     
    #define FSMC_BCR2_MTYP_Pos   (2U)
     
    #define FSMC_BCR2_MTYP_Msk   (0x3UL << FSMC_BCR2_MTYP_Pos)
     
    #define FSMC_BCR2_MTYP   FSMC_BCR2_MTYP_Msk
     
    #define FSMC_BCR2_MTYP_0   (0x1UL << FSMC_BCR2_MTYP_Pos)
     
    #define FSMC_BCR2_MTYP_1   (0x2UL << FSMC_BCR2_MTYP_Pos)
     
    #define FSMC_BCR2_MWID_Pos   (4U)
     
    #define FSMC_BCR2_MWID_Msk   (0x3UL << FSMC_BCR2_MWID_Pos)
     
    #define FSMC_BCR2_MWID   FSMC_BCR2_MWID_Msk
     
    #define FSMC_BCR2_MWID_0   (0x1UL << FSMC_BCR2_MWID_Pos)
     
    #define FSMC_BCR2_MWID_1   (0x2UL << FSMC_BCR2_MWID_Pos)
     
    #define FSMC_BCR2_FACCEN_Pos   (6U)
     
    #define FSMC_BCR2_FACCEN_Msk   (0x1UL << FSMC_BCR2_FACCEN_Pos)
     
    #define FSMC_BCR2_FACCEN   FSMC_BCR2_FACCEN_Msk
     
    #define FSMC_BCR2_BURSTEN_Pos   (8U)
     
    #define FSMC_BCR2_BURSTEN_Msk   (0x1UL << FSMC_BCR2_BURSTEN_Pos)
     
    #define FSMC_BCR2_BURSTEN   FSMC_BCR2_BURSTEN_Msk
     
    #define FSMC_BCR2_WAITPOL_Pos   (9U)
     
    #define FSMC_BCR2_WAITPOL_Msk   (0x1UL << FSMC_BCR2_WAITPOL_Pos)
     
    #define FSMC_BCR2_WAITPOL   FSMC_BCR2_WAITPOL_Msk
     
    #define FSMC_BCR2_WRAPMOD_Pos   (10U)
     
    #define FSMC_BCR2_WRAPMOD_Msk   (0x1UL << FSMC_BCR2_WRAPMOD_Pos)
     
    #define FSMC_BCR2_WRAPMOD   FSMC_BCR2_WRAPMOD_Msk
     
    #define FSMC_BCR2_WAITCFG_Pos   (11U)
     
    #define FSMC_BCR2_WAITCFG_Msk   (0x1UL << FSMC_BCR2_WAITCFG_Pos)
     
    #define FSMC_BCR2_WAITCFG   FSMC_BCR2_WAITCFG_Msk
     
    #define FSMC_BCR2_WREN_Pos   (12U)
     
    #define FSMC_BCR2_WREN_Msk   (0x1UL << FSMC_BCR2_WREN_Pos)
     
    #define FSMC_BCR2_WREN   FSMC_BCR2_WREN_Msk
     
    #define FSMC_BCR2_WAITEN_Pos   (13U)
     
    #define FSMC_BCR2_WAITEN_Msk   (0x1UL << FSMC_BCR2_WAITEN_Pos)
     
    #define FSMC_BCR2_WAITEN   FSMC_BCR2_WAITEN_Msk
     
    #define FSMC_BCR2_EXTMOD_Pos   (14U)
     
    #define FSMC_BCR2_EXTMOD_Msk   (0x1UL << FSMC_BCR2_EXTMOD_Pos)
     
    #define FSMC_BCR2_EXTMOD   FSMC_BCR2_EXTMOD_Msk
     
    #define FSMC_BCR2_ASYNCWAIT_Pos   (15U)
     
    #define FSMC_BCR2_ASYNCWAIT_Msk   (0x1UL << FSMC_BCR2_ASYNCWAIT_Pos)
     
    #define FSMC_BCR2_ASYNCWAIT   FSMC_BCR2_ASYNCWAIT_Msk
     
    #define FSMC_BCR2_CPSIZE_Pos   (16U)
     
    #define FSMC_BCR2_CPSIZE_Msk   (0x7UL << FSMC_BCR2_CPSIZE_Pos)
     
    #define FSMC_BCR2_CPSIZE   FSMC_BCR2_CPSIZE_Msk
     
    #define FSMC_BCR2_CPSIZE_0   (0x1UL << FSMC_BCR2_CPSIZE_Pos)
     
    #define FSMC_BCR2_CPSIZE_1   (0x2UL << FSMC_BCR2_CPSIZE_Pos)
     
    #define FSMC_BCR2_CPSIZE_2   (0x4UL << FSMC_BCR2_CPSIZE_Pos)
     
    #define FSMC_BCR2_CBURSTRW_Pos   (19U)
     
    #define FSMC_BCR2_CBURSTRW_Msk   (0x1UL << FSMC_BCR2_CBURSTRW_Pos)
     
    #define FSMC_BCR2_CBURSTRW   FSMC_BCR2_CBURSTRW_Msk
     
    #define FSMC_BCR3_MBKEN_Pos   (0U)
     
    #define FSMC_BCR3_MBKEN_Msk   (0x1UL << FSMC_BCR3_MBKEN_Pos)
     
    #define FSMC_BCR3_MBKEN   FSMC_BCR3_MBKEN_Msk
     
    #define FSMC_BCR3_MUXEN_Pos   (1U)
     
    #define FSMC_BCR3_MUXEN_Msk   (0x1UL << FSMC_BCR3_MUXEN_Pos)
     
    #define FSMC_BCR3_MUXEN   FSMC_BCR3_MUXEN_Msk
     
    #define FSMC_BCR3_MTYP_Pos   (2U)
     
    #define FSMC_BCR3_MTYP_Msk   (0x3UL << FSMC_BCR3_MTYP_Pos)
     
    #define FSMC_BCR3_MTYP   FSMC_BCR3_MTYP_Msk
     
    #define FSMC_BCR3_MTYP_0   (0x1UL << FSMC_BCR3_MTYP_Pos)
     
    #define FSMC_BCR3_MTYP_1   (0x2UL << FSMC_BCR3_MTYP_Pos)
     
    #define FSMC_BCR3_MWID_Pos   (4U)
     
    #define FSMC_BCR3_MWID_Msk   (0x3UL << FSMC_BCR3_MWID_Pos)
     
    #define FSMC_BCR3_MWID   FSMC_BCR3_MWID_Msk
     
    #define FSMC_BCR3_MWID_0   (0x1UL << FSMC_BCR3_MWID_Pos)
     
    #define FSMC_BCR3_MWID_1   (0x2UL << FSMC_BCR3_MWID_Pos)
     
    #define FSMC_BCR3_FACCEN_Pos   (6U)
     
    #define FSMC_BCR3_FACCEN_Msk   (0x1UL << FSMC_BCR3_FACCEN_Pos)
     
    #define FSMC_BCR3_FACCEN   FSMC_BCR3_FACCEN_Msk
     
    #define FSMC_BCR3_BURSTEN_Pos   (8U)
     
    #define FSMC_BCR3_BURSTEN_Msk   (0x1UL << FSMC_BCR3_BURSTEN_Pos)
     
    #define FSMC_BCR3_BURSTEN   FSMC_BCR3_BURSTEN_Msk
     
    #define FSMC_BCR3_WAITPOL_Pos   (9U)
     
    #define FSMC_BCR3_WAITPOL_Msk   (0x1UL << FSMC_BCR3_WAITPOL_Pos)
     
    #define FSMC_BCR3_WAITPOL   FSMC_BCR3_WAITPOL_Msk
     
    #define FSMC_BCR3_WRAPMOD_Pos   (10U)
     
    #define FSMC_BCR3_WRAPMOD_Msk   (0x1UL << FSMC_BCR3_WRAPMOD_Pos)
     
    #define FSMC_BCR3_WRAPMOD   FSMC_BCR3_WRAPMOD_Msk
     
    #define FSMC_BCR3_WAITCFG_Pos   (11U)
     
    #define FSMC_BCR3_WAITCFG_Msk   (0x1UL << FSMC_BCR3_WAITCFG_Pos)
     
    #define FSMC_BCR3_WAITCFG   FSMC_BCR3_WAITCFG_Msk
     
    #define FSMC_BCR3_WREN_Pos   (12U)
     
    #define FSMC_BCR3_WREN_Msk   (0x1UL << FSMC_BCR3_WREN_Pos)
     
    #define FSMC_BCR3_WREN   FSMC_BCR3_WREN_Msk
     
    #define FSMC_BCR3_WAITEN_Pos   (13U)
     
    #define FSMC_BCR3_WAITEN_Msk   (0x1UL << FSMC_BCR3_WAITEN_Pos)
     
    #define FSMC_BCR3_WAITEN   FSMC_BCR3_WAITEN_Msk
     
    #define FSMC_BCR3_EXTMOD_Pos   (14U)
     
    #define FSMC_BCR3_EXTMOD_Msk   (0x1UL << FSMC_BCR3_EXTMOD_Pos)
     
    #define FSMC_BCR3_EXTMOD   FSMC_BCR3_EXTMOD_Msk
     
    #define FSMC_BCR3_ASYNCWAIT_Pos   (15U)
     
    #define FSMC_BCR3_ASYNCWAIT_Msk   (0x1UL << FSMC_BCR3_ASYNCWAIT_Pos)
     
    #define FSMC_BCR3_ASYNCWAIT   FSMC_BCR3_ASYNCWAIT_Msk
     
    #define FSMC_BCR3_CPSIZE_Pos   (16U)
     
    #define FSMC_BCR3_CPSIZE_Msk   (0x7UL << FSMC_BCR3_CPSIZE_Pos)
     
    #define FSMC_BCR3_CPSIZE   FSMC_BCR3_CPSIZE_Msk
     
    #define FSMC_BCR3_CPSIZE_0   (0x1UL << FSMC_BCR3_CPSIZE_Pos)
     
    #define FSMC_BCR3_CPSIZE_1   (0x2UL << FSMC_BCR3_CPSIZE_Pos)
     
    #define FSMC_BCR3_CPSIZE_2   (0x4UL << FSMC_BCR3_CPSIZE_Pos)
     
    #define FSMC_BCR3_CBURSTRW_Pos   (19U)
     
    #define FSMC_BCR3_CBURSTRW_Msk   (0x1UL << FSMC_BCR3_CBURSTRW_Pos)
     
    #define FSMC_BCR3_CBURSTRW   FSMC_BCR3_CBURSTRW_Msk
     
    #define FSMC_BCR4_MBKEN_Pos   (0U)
     
    #define FSMC_BCR4_MBKEN_Msk   (0x1UL << FSMC_BCR4_MBKEN_Pos)
     
    #define FSMC_BCR4_MBKEN   FSMC_BCR4_MBKEN_Msk
     
    #define FSMC_BCR4_MUXEN_Pos   (1U)
     
    #define FSMC_BCR4_MUXEN_Msk   (0x1UL << FSMC_BCR4_MUXEN_Pos)
     
    #define FSMC_BCR4_MUXEN   FSMC_BCR4_MUXEN_Msk
     
    #define FSMC_BCR4_MTYP_Pos   (2U)
     
    #define FSMC_BCR4_MTYP_Msk   (0x3UL << FSMC_BCR4_MTYP_Pos)
     
    #define FSMC_BCR4_MTYP   FSMC_BCR4_MTYP_Msk
     
    #define FSMC_BCR4_MTYP_0   (0x1UL << FSMC_BCR4_MTYP_Pos)
     
    #define FSMC_BCR4_MTYP_1   (0x2UL << FSMC_BCR4_MTYP_Pos)
     
    #define FSMC_BCR4_MWID_Pos   (4U)
     
    #define FSMC_BCR4_MWID_Msk   (0x3UL << FSMC_BCR4_MWID_Pos)
     
    #define FSMC_BCR4_MWID   FSMC_BCR4_MWID_Msk
     
    #define FSMC_BCR4_MWID_0   (0x1UL << FSMC_BCR4_MWID_Pos)
     
    #define FSMC_BCR4_MWID_1   (0x2UL << FSMC_BCR4_MWID_Pos)
     
    #define FSMC_BCR4_FACCEN_Pos   (6U)
     
    #define FSMC_BCR4_FACCEN_Msk   (0x1UL << FSMC_BCR4_FACCEN_Pos)
     
    #define FSMC_BCR4_FACCEN   FSMC_BCR4_FACCEN_Msk
     
    #define FSMC_BCR4_BURSTEN_Pos   (8U)
     
    #define FSMC_BCR4_BURSTEN_Msk   (0x1UL << FSMC_BCR4_BURSTEN_Pos)
     
    #define FSMC_BCR4_BURSTEN   FSMC_BCR4_BURSTEN_Msk
     
    #define FSMC_BCR4_WAITPOL_Pos   (9U)
     
    #define FSMC_BCR4_WAITPOL_Msk   (0x1UL << FSMC_BCR4_WAITPOL_Pos)
     
    #define FSMC_BCR4_WAITPOL   FSMC_BCR4_WAITPOL_Msk
     
    #define FSMC_BCR4_WRAPMOD_Pos   (10U)
     
    #define FSMC_BCR4_WRAPMOD_Msk   (0x1UL << FSMC_BCR4_WRAPMOD_Pos)
     
    #define FSMC_BCR4_WRAPMOD   FSMC_BCR4_WRAPMOD_Msk
     
    #define FSMC_BCR4_WAITCFG_Pos   (11U)
     
    #define FSMC_BCR4_WAITCFG_Msk   (0x1UL << FSMC_BCR4_WAITCFG_Pos)
     
    #define FSMC_BCR4_WAITCFG   FSMC_BCR4_WAITCFG_Msk
     
    #define FSMC_BCR4_WREN_Pos   (12U)
     
    #define FSMC_BCR4_WREN_Msk   (0x1UL << FSMC_BCR4_WREN_Pos)
     
    #define FSMC_BCR4_WREN   FSMC_BCR4_WREN_Msk
     
    #define FSMC_BCR4_WAITEN_Pos   (13U)
     
    #define FSMC_BCR4_WAITEN_Msk   (0x1UL << FSMC_BCR4_WAITEN_Pos)
     
    #define FSMC_BCR4_WAITEN   FSMC_BCR4_WAITEN_Msk
     
    #define FSMC_BCR4_EXTMOD_Pos   (14U)
     
    #define FSMC_BCR4_EXTMOD_Msk   (0x1UL << FSMC_BCR4_EXTMOD_Pos)
     
    #define FSMC_BCR4_EXTMOD   FSMC_BCR4_EXTMOD_Msk
     
    #define FSMC_BCR4_ASYNCWAIT_Pos   (15U)
     
    #define FSMC_BCR4_ASYNCWAIT_Msk   (0x1UL << FSMC_BCR4_ASYNCWAIT_Pos)
     
    #define FSMC_BCR4_ASYNCWAIT   FSMC_BCR4_ASYNCWAIT_Msk
     
    #define FSMC_BCR4_CPSIZE_Pos   (16U)
     
    #define FSMC_BCR4_CPSIZE_Msk   (0x7UL << FSMC_BCR4_CPSIZE_Pos)
     
    #define FSMC_BCR4_CPSIZE   FSMC_BCR4_CPSIZE_Msk
     
    #define FSMC_BCR4_CPSIZE_0   (0x1UL << FSMC_BCR4_CPSIZE_Pos)
     
    #define FSMC_BCR4_CPSIZE_1   (0x2UL << FSMC_BCR4_CPSIZE_Pos)
     
    #define FSMC_BCR4_CPSIZE_2   (0x4UL << FSMC_BCR4_CPSIZE_Pos)
     
    #define FSMC_BCR4_CBURSTRW_Pos   (19U)
     
    #define FSMC_BCR4_CBURSTRW_Msk   (0x1UL << FSMC_BCR4_CBURSTRW_Pos)
     
    #define FSMC_BCR4_CBURSTRW   FSMC_BCR4_CBURSTRW_Msk
     
    #define FSMC_BTR1_ADDSET_Pos   (0U)
     
    #define FSMC_BTR1_ADDSET_Msk   (0xFUL << FSMC_BTR1_ADDSET_Pos)
     
    #define FSMC_BTR1_ADDSET   FSMC_BTR1_ADDSET_Msk
     
    #define FSMC_BTR1_ADDSET_0   (0x1UL << FSMC_BTR1_ADDSET_Pos)
     
    #define FSMC_BTR1_ADDSET_1   (0x2UL << FSMC_BTR1_ADDSET_Pos)
     
    #define FSMC_BTR1_ADDSET_2   (0x4UL << FSMC_BTR1_ADDSET_Pos)
     
    #define FSMC_BTR1_ADDSET_3   (0x8UL << FSMC_BTR1_ADDSET_Pos)
     
    #define FSMC_BTR1_ADDHLD_Pos   (4U)
     
    #define FSMC_BTR1_ADDHLD_Msk   (0xFUL << FSMC_BTR1_ADDHLD_Pos)
     
    #define FSMC_BTR1_ADDHLD   FSMC_BTR1_ADDHLD_Msk
     
    #define FSMC_BTR1_ADDHLD_0   (0x1UL << FSMC_BTR1_ADDHLD_Pos)
     
    #define FSMC_BTR1_ADDHLD_1   (0x2UL << FSMC_BTR1_ADDHLD_Pos)
     
    #define FSMC_BTR1_ADDHLD_2   (0x4UL << FSMC_BTR1_ADDHLD_Pos)
     
    #define FSMC_BTR1_ADDHLD_3   (0x8UL << FSMC_BTR1_ADDHLD_Pos)
     
    #define FSMC_BTR1_DATAST_Pos   (8U)
     
    #define FSMC_BTR1_DATAST_Msk   (0xFFUL << FSMC_BTR1_DATAST_Pos)
     
    #define FSMC_BTR1_DATAST   FSMC_BTR1_DATAST_Msk
     
    #define FSMC_BTR1_DATAST_0   (0x01UL << FSMC_BTR1_DATAST_Pos)
     
    #define FSMC_BTR1_DATAST_1   (0x02UL << FSMC_BTR1_DATAST_Pos)
     
    #define FSMC_BTR1_DATAST_2   (0x04UL << FSMC_BTR1_DATAST_Pos)
     
    #define FSMC_BTR1_DATAST_3   (0x08UL << FSMC_BTR1_DATAST_Pos)
     
    #define FSMC_BTR1_DATAST_4   (0x10UL << FSMC_BTR1_DATAST_Pos)
     
    #define FSMC_BTR1_DATAST_5   (0x20UL << FSMC_BTR1_DATAST_Pos)
     
    #define FSMC_BTR1_DATAST_6   (0x40UL << FSMC_BTR1_DATAST_Pos)
     
    #define FSMC_BTR1_DATAST_7   (0x80UL << FSMC_BTR1_DATAST_Pos)
     
    #define FSMC_BTR1_BUSTURN_Pos   (16U)
     
    #define FSMC_BTR1_BUSTURN_Msk   (0xFUL << FSMC_BTR1_BUSTURN_Pos)
     
    #define FSMC_BTR1_BUSTURN   FSMC_BTR1_BUSTURN_Msk
     
    #define FSMC_BTR1_BUSTURN_0   (0x1UL << FSMC_BTR1_BUSTURN_Pos)
     
    #define FSMC_BTR1_BUSTURN_1   (0x2UL << FSMC_BTR1_BUSTURN_Pos)
     
    #define FSMC_BTR1_BUSTURN_2   (0x4UL << FSMC_BTR1_BUSTURN_Pos)
     
    #define FSMC_BTR1_BUSTURN_3   (0x8UL << FSMC_BTR1_BUSTURN_Pos)
     
    #define FSMC_BTR1_CLKDIV_Pos   (20U)
     
    #define FSMC_BTR1_CLKDIV_Msk   (0xFUL << FSMC_BTR1_CLKDIV_Pos)
     
    #define FSMC_BTR1_CLKDIV   FSMC_BTR1_CLKDIV_Msk
     
    #define FSMC_BTR1_CLKDIV_0   (0x1UL << FSMC_BTR1_CLKDIV_Pos)
     
    #define FSMC_BTR1_CLKDIV_1   (0x2UL << FSMC_BTR1_CLKDIV_Pos)
     
    #define FSMC_BTR1_CLKDIV_2   (0x4UL << FSMC_BTR1_CLKDIV_Pos)
     
    #define FSMC_BTR1_CLKDIV_3   (0x8UL << FSMC_BTR1_CLKDIV_Pos)
     
    #define FSMC_BTR1_DATLAT_Pos   (24U)
     
    #define FSMC_BTR1_DATLAT_Msk   (0xFUL << FSMC_BTR1_DATLAT_Pos)
     
    #define FSMC_BTR1_DATLAT   FSMC_BTR1_DATLAT_Msk
     
    #define FSMC_BTR1_DATLAT_0   (0x1UL << FSMC_BTR1_DATLAT_Pos)
     
    #define FSMC_BTR1_DATLAT_1   (0x2UL << FSMC_BTR1_DATLAT_Pos)
     
    #define FSMC_BTR1_DATLAT_2   (0x4UL << FSMC_BTR1_DATLAT_Pos)
     
    #define FSMC_BTR1_DATLAT_3   (0x8UL << FSMC_BTR1_DATLAT_Pos)
     
    #define FSMC_BTR1_ACCMOD_Pos   (28U)
     
    #define FSMC_BTR1_ACCMOD_Msk   (0x3UL << FSMC_BTR1_ACCMOD_Pos)
     
    #define FSMC_BTR1_ACCMOD   FSMC_BTR1_ACCMOD_Msk
     
    #define FSMC_BTR1_ACCMOD_0   (0x1UL << FSMC_BTR1_ACCMOD_Pos)
     
    #define FSMC_BTR1_ACCMOD_1   (0x2UL << FSMC_BTR1_ACCMOD_Pos)
     
    #define FSMC_BTR2_ADDSET_Pos   (0U)
     
    #define FSMC_BTR2_ADDSET_Msk   (0xFUL << FSMC_BTR2_ADDSET_Pos)
     
    #define FSMC_BTR2_ADDSET   FSMC_BTR2_ADDSET_Msk
     
    #define FSMC_BTR2_ADDSET_0   (0x1UL << FSMC_BTR2_ADDSET_Pos)
     
    #define FSMC_BTR2_ADDSET_1   (0x2UL << FSMC_BTR2_ADDSET_Pos)
     
    #define FSMC_BTR2_ADDSET_2   (0x4UL << FSMC_BTR2_ADDSET_Pos)
     
    #define FSMC_BTR2_ADDSET_3   (0x8UL << FSMC_BTR2_ADDSET_Pos)
     
    #define FSMC_BTR2_ADDHLD_Pos   (4U)
     
    #define FSMC_BTR2_ADDHLD_Msk   (0xFUL << FSMC_BTR2_ADDHLD_Pos)
     
    #define FSMC_BTR2_ADDHLD   FSMC_BTR2_ADDHLD_Msk
     
    #define FSMC_BTR2_ADDHLD_0   (0x1UL << FSMC_BTR2_ADDHLD_Pos)
     
    #define FSMC_BTR2_ADDHLD_1   (0x2UL << FSMC_BTR2_ADDHLD_Pos)
     
    #define FSMC_BTR2_ADDHLD_2   (0x4UL << FSMC_BTR2_ADDHLD_Pos)
     
    #define FSMC_BTR2_ADDHLD_3   (0x8UL << FSMC_BTR2_ADDHLD_Pos)
     
    #define FSMC_BTR2_DATAST_Pos   (8U)
     
    #define FSMC_BTR2_DATAST_Msk   (0xFFUL << FSMC_BTR2_DATAST_Pos)
     
    #define FSMC_BTR2_DATAST   FSMC_BTR2_DATAST_Msk
     
    #define FSMC_BTR2_DATAST_0   (0x01UL << FSMC_BTR2_DATAST_Pos)
     
    #define FSMC_BTR2_DATAST_1   (0x02UL << FSMC_BTR2_DATAST_Pos)
     
    #define FSMC_BTR2_DATAST_2   (0x04UL << FSMC_BTR2_DATAST_Pos)
     
    #define FSMC_BTR2_DATAST_3   (0x08UL << FSMC_BTR2_DATAST_Pos)
     
    #define FSMC_BTR2_DATAST_4   (0x10UL << FSMC_BTR2_DATAST_Pos)
     
    #define FSMC_BTR2_DATAST_5   (0x20UL << FSMC_BTR2_DATAST_Pos)
     
    #define FSMC_BTR2_DATAST_6   (0x40UL << FSMC_BTR2_DATAST_Pos)
     
    #define FSMC_BTR2_DATAST_7   (0x80UL << FSMC_BTR2_DATAST_Pos)
     
    #define FSMC_BTR2_BUSTURN_Pos   (16U)
     
    #define FSMC_BTR2_BUSTURN_Msk   (0xFUL << FSMC_BTR2_BUSTURN_Pos)
     
    #define FSMC_BTR2_BUSTURN   FSMC_BTR2_BUSTURN_Msk
     
    #define FSMC_BTR2_BUSTURN_0   (0x1UL << FSMC_BTR2_BUSTURN_Pos)
     
    #define FSMC_BTR2_BUSTURN_1   (0x2UL << FSMC_BTR2_BUSTURN_Pos)
     
    #define FSMC_BTR2_BUSTURN_2   (0x4UL << FSMC_BTR2_BUSTURN_Pos)
     
    #define FSMC_BTR2_BUSTURN_3   (0x8UL << FSMC_BTR2_BUSTURN_Pos)
     
    #define FSMC_BTR2_CLKDIV_Pos   (20U)
     
    #define FSMC_BTR2_CLKDIV_Msk   (0xFUL << FSMC_BTR2_CLKDIV_Pos)
     
    #define FSMC_BTR2_CLKDIV   FSMC_BTR2_CLKDIV_Msk
     
    #define FSMC_BTR2_CLKDIV_0   (0x1UL << FSMC_BTR2_CLKDIV_Pos)
     
    #define FSMC_BTR2_CLKDIV_1   (0x2UL << FSMC_BTR2_CLKDIV_Pos)
     
    #define FSMC_BTR2_CLKDIV_2   (0x4UL << FSMC_BTR2_CLKDIV_Pos)
     
    #define FSMC_BTR2_CLKDIV_3   (0x8UL << FSMC_BTR2_CLKDIV_Pos)
     
    #define FSMC_BTR2_DATLAT_Pos   (24U)
     
    #define FSMC_BTR2_DATLAT_Msk   (0xFUL << FSMC_BTR2_DATLAT_Pos)
     
    #define FSMC_BTR2_DATLAT   FSMC_BTR2_DATLAT_Msk
     
    #define FSMC_BTR2_DATLAT_0   (0x1UL << FSMC_BTR2_DATLAT_Pos)
     
    #define FSMC_BTR2_DATLAT_1   (0x2UL << FSMC_BTR2_DATLAT_Pos)
     
    #define FSMC_BTR2_DATLAT_2   (0x4UL << FSMC_BTR2_DATLAT_Pos)
     
    #define FSMC_BTR2_DATLAT_3   (0x8UL << FSMC_BTR2_DATLAT_Pos)
     
    #define FSMC_BTR2_ACCMOD_Pos   (28U)
     
    #define FSMC_BTR2_ACCMOD_Msk   (0x3UL << FSMC_BTR2_ACCMOD_Pos)
     
    #define FSMC_BTR2_ACCMOD   FSMC_BTR2_ACCMOD_Msk
     
    #define FSMC_BTR2_ACCMOD_0   (0x1UL << FSMC_BTR2_ACCMOD_Pos)
     
    #define FSMC_BTR2_ACCMOD_1   (0x2UL << FSMC_BTR2_ACCMOD_Pos)
     
    #define FSMC_BTR3_ADDSET_Pos   (0U)
     
    #define FSMC_BTR3_ADDSET_Msk   (0xFUL << FSMC_BTR3_ADDSET_Pos)
     
    #define FSMC_BTR3_ADDSET   FSMC_BTR3_ADDSET_Msk
     
    #define FSMC_BTR3_ADDSET_0   (0x1UL << FSMC_BTR3_ADDSET_Pos)
     
    #define FSMC_BTR3_ADDSET_1   (0x2UL << FSMC_BTR3_ADDSET_Pos)
     
    #define FSMC_BTR3_ADDSET_2   (0x4UL << FSMC_BTR3_ADDSET_Pos)
     
    #define FSMC_BTR3_ADDSET_3   (0x8UL << FSMC_BTR3_ADDSET_Pos)
     
    #define FSMC_BTR3_ADDHLD_Pos   (4U)
     
    #define FSMC_BTR3_ADDHLD_Msk   (0xFUL << FSMC_BTR3_ADDHLD_Pos)
     
    #define FSMC_BTR3_ADDHLD   FSMC_BTR3_ADDHLD_Msk
     
    #define FSMC_BTR3_ADDHLD_0   (0x1UL << FSMC_BTR3_ADDHLD_Pos)
     
    #define FSMC_BTR3_ADDHLD_1   (0x2UL << FSMC_BTR3_ADDHLD_Pos)
     
    #define FSMC_BTR3_ADDHLD_2   (0x4UL << FSMC_BTR3_ADDHLD_Pos)
     
    #define FSMC_BTR3_ADDHLD_3   (0x8UL << FSMC_BTR3_ADDHLD_Pos)
     
    #define FSMC_BTR3_DATAST_Pos   (8U)
     
    #define FSMC_BTR3_DATAST_Msk   (0xFFUL << FSMC_BTR3_DATAST_Pos)
     
    #define FSMC_BTR3_DATAST   FSMC_BTR3_DATAST_Msk
     
    #define FSMC_BTR3_DATAST_0   (0x01UL << FSMC_BTR3_DATAST_Pos)
     
    #define FSMC_BTR3_DATAST_1   (0x02UL << FSMC_BTR3_DATAST_Pos)
     
    #define FSMC_BTR3_DATAST_2   (0x04UL << FSMC_BTR3_DATAST_Pos)
     
    #define FSMC_BTR3_DATAST_3   (0x08UL << FSMC_BTR3_DATAST_Pos)
     
    #define FSMC_BTR3_DATAST_4   (0x10UL << FSMC_BTR3_DATAST_Pos)
     
    #define FSMC_BTR3_DATAST_5   (0x20UL << FSMC_BTR3_DATAST_Pos)
     
    #define FSMC_BTR3_DATAST_6   (0x40UL << FSMC_BTR3_DATAST_Pos)
     
    #define FSMC_BTR3_DATAST_7   (0x80UL << FSMC_BTR3_DATAST_Pos)
     
    #define FSMC_BTR3_BUSTURN_Pos   (16U)
     
    #define FSMC_BTR3_BUSTURN_Msk   (0xFUL << FSMC_BTR3_BUSTURN_Pos)
     
    #define FSMC_BTR3_BUSTURN   FSMC_BTR3_BUSTURN_Msk
     
    #define FSMC_BTR3_BUSTURN_0   (0x1UL << FSMC_BTR3_BUSTURN_Pos)
     
    #define FSMC_BTR3_BUSTURN_1   (0x2UL << FSMC_BTR3_BUSTURN_Pos)
     
    #define FSMC_BTR3_BUSTURN_2   (0x4UL << FSMC_BTR3_BUSTURN_Pos)
     
    #define FSMC_BTR3_BUSTURN_3   (0x8UL << FSMC_BTR3_BUSTURN_Pos)
     
    #define FSMC_BTR3_CLKDIV_Pos   (20U)
     
    #define FSMC_BTR3_CLKDIV_Msk   (0xFUL << FSMC_BTR3_CLKDIV_Pos)
     
    #define FSMC_BTR3_CLKDIV   FSMC_BTR3_CLKDIV_Msk
     
    #define FSMC_BTR3_CLKDIV_0   (0x1UL << FSMC_BTR3_CLKDIV_Pos)
     
    #define FSMC_BTR3_CLKDIV_1   (0x2UL << FSMC_BTR3_CLKDIV_Pos)
     
    #define FSMC_BTR3_CLKDIV_2   (0x4UL << FSMC_BTR3_CLKDIV_Pos)
     
    #define FSMC_BTR3_CLKDIV_3   (0x8UL << FSMC_BTR3_CLKDIV_Pos)
     
    #define FSMC_BTR3_DATLAT_Pos   (24U)
     
    #define FSMC_BTR3_DATLAT_Msk   (0xFUL << FSMC_BTR3_DATLAT_Pos)
     
    #define FSMC_BTR3_DATLAT   FSMC_BTR3_DATLAT_Msk
     
    #define FSMC_BTR3_DATLAT_0   (0x1UL << FSMC_BTR3_DATLAT_Pos)
     
    #define FSMC_BTR3_DATLAT_1   (0x2UL << FSMC_BTR3_DATLAT_Pos)
     
    #define FSMC_BTR3_DATLAT_2   (0x4UL << FSMC_BTR3_DATLAT_Pos)
     
    #define FSMC_BTR3_DATLAT_3   (0x8UL << FSMC_BTR3_DATLAT_Pos)
     
    #define FSMC_BTR3_ACCMOD_Pos   (28U)
     
    #define FSMC_BTR3_ACCMOD_Msk   (0x3UL << FSMC_BTR3_ACCMOD_Pos)
     
    #define FSMC_BTR3_ACCMOD   FSMC_BTR3_ACCMOD_Msk
     
    #define FSMC_BTR3_ACCMOD_0   (0x1UL << FSMC_BTR3_ACCMOD_Pos)
     
    #define FSMC_BTR3_ACCMOD_1   (0x2UL << FSMC_BTR3_ACCMOD_Pos)
     
    #define FSMC_BTR4_ADDSET_Pos   (0U)
     
    #define FSMC_BTR4_ADDSET_Msk   (0xFUL << FSMC_BTR4_ADDSET_Pos)
     
    #define FSMC_BTR4_ADDSET   FSMC_BTR4_ADDSET_Msk
     
    #define FSMC_BTR4_ADDSET_0   (0x1UL << FSMC_BTR4_ADDSET_Pos)
     
    #define FSMC_BTR4_ADDSET_1   (0x2UL << FSMC_BTR4_ADDSET_Pos)
     
    #define FSMC_BTR4_ADDSET_2   (0x4UL << FSMC_BTR4_ADDSET_Pos)
     
    #define FSMC_BTR4_ADDSET_3   (0x8UL << FSMC_BTR4_ADDSET_Pos)
     
    #define FSMC_BTR4_ADDHLD_Pos   (4U)
     
    #define FSMC_BTR4_ADDHLD_Msk   (0xFUL << FSMC_BTR4_ADDHLD_Pos)
     
    #define FSMC_BTR4_ADDHLD   FSMC_BTR4_ADDHLD_Msk
     
    #define FSMC_BTR4_ADDHLD_0   (0x1UL << FSMC_BTR4_ADDHLD_Pos)
     
    #define FSMC_BTR4_ADDHLD_1   (0x2UL << FSMC_BTR4_ADDHLD_Pos)
     
    #define FSMC_BTR4_ADDHLD_2   (0x4UL << FSMC_BTR4_ADDHLD_Pos)
     
    #define FSMC_BTR4_ADDHLD_3   (0x8UL << FSMC_BTR4_ADDHLD_Pos)
     
    #define FSMC_BTR4_DATAST_Pos   (8U)
     
    #define FSMC_BTR4_DATAST_Msk   (0xFFUL << FSMC_BTR4_DATAST_Pos)
     
    #define FSMC_BTR4_DATAST   FSMC_BTR4_DATAST_Msk
     
    #define FSMC_BTR4_DATAST_0   (0x01UL << FSMC_BTR4_DATAST_Pos)
     
    #define FSMC_BTR4_DATAST_1   (0x02UL << FSMC_BTR4_DATAST_Pos)
     
    #define FSMC_BTR4_DATAST_2   (0x04UL << FSMC_BTR4_DATAST_Pos)
     
    #define FSMC_BTR4_DATAST_3   (0x08UL << FSMC_BTR4_DATAST_Pos)
     
    #define FSMC_BTR4_DATAST_4   (0x10UL << FSMC_BTR4_DATAST_Pos)
     
    #define FSMC_BTR4_DATAST_5   (0x20UL << FSMC_BTR4_DATAST_Pos)
     
    #define FSMC_BTR4_DATAST_6   (0x40UL << FSMC_BTR4_DATAST_Pos)
     
    #define FSMC_BTR4_DATAST_7   (0x80UL << FSMC_BTR4_DATAST_Pos)
     
    #define FSMC_BTR4_BUSTURN_Pos   (16U)
     
    #define FSMC_BTR4_BUSTURN_Msk   (0xFUL << FSMC_BTR4_BUSTURN_Pos)
     
    #define FSMC_BTR4_BUSTURN   FSMC_BTR4_BUSTURN_Msk
     
    #define FSMC_BTR4_BUSTURN_0   (0x1UL << FSMC_BTR4_BUSTURN_Pos)
     
    #define FSMC_BTR4_BUSTURN_1   (0x2UL << FSMC_BTR4_BUSTURN_Pos)
     
    #define FSMC_BTR4_BUSTURN_2   (0x4UL << FSMC_BTR4_BUSTURN_Pos)
     
    #define FSMC_BTR4_BUSTURN_3   (0x8UL << FSMC_BTR4_BUSTURN_Pos)
     
    #define FSMC_BTR4_CLKDIV_Pos   (20U)
     
    #define FSMC_BTR4_CLKDIV_Msk   (0xFUL << FSMC_BTR4_CLKDIV_Pos)
     
    #define FSMC_BTR4_CLKDIV   FSMC_BTR4_CLKDIV_Msk
     
    #define FSMC_BTR4_CLKDIV_0   (0x1UL << FSMC_BTR4_CLKDIV_Pos)
     
    #define FSMC_BTR4_CLKDIV_1   (0x2UL << FSMC_BTR4_CLKDIV_Pos)
     
    #define FSMC_BTR4_CLKDIV_2   (0x4UL << FSMC_BTR4_CLKDIV_Pos)
     
    #define FSMC_BTR4_CLKDIV_3   (0x8UL << FSMC_BTR4_CLKDIV_Pos)
     
    #define FSMC_BTR4_DATLAT_Pos   (24U)
     
    #define FSMC_BTR4_DATLAT_Msk   (0xFUL << FSMC_BTR4_DATLAT_Pos)
     
    #define FSMC_BTR4_DATLAT   FSMC_BTR4_DATLAT_Msk
     
    #define FSMC_BTR4_DATLAT_0   (0x1UL << FSMC_BTR4_DATLAT_Pos)
     
    #define FSMC_BTR4_DATLAT_1   (0x2UL << FSMC_BTR4_DATLAT_Pos)
     
    #define FSMC_BTR4_DATLAT_2   (0x4UL << FSMC_BTR4_DATLAT_Pos)
     
    #define FSMC_BTR4_DATLAT_3   (0x8UL << FSMC_BTR4_DATLAT_Pos)
     
    #define FSMC_BTR4_ACCMOD_Pos   (28U)
     
    #define FSMC_BTR4_ACCMOD_Msk   (0x3UL << FSMC_BTR4_ACCMOD_Pos)
     
    #define FSMC_BTR4_ACCMOD   FSMC_BTR4_ACCMOD_Msk
     
    #define FSMC_BTR4_ACCMOD_0   (0x1UL << FSMC_BTR4_ACCMOD_Pos)
     
    #define FSMC_BTR4_ACCMOD_1   (0x2UL << FSMC_BTR4_ACCMOD_Pos)
     
    #define FSMC_BWTR1_ADDSET_Pos   (0U)
     
    #define FSMC_BWTR1_ADDSET_Msk   (0xFUL << FSMC_BWTR1_ADDSET_Pos)
     
    #define FSMC_BWTR1_ADDSET   FSMC_BWTR1_ADDSET_Msk
     
    #define FSMC_BWTR1_ADDSET_0   (0x1UL << FSMC_BWTR1_ADDSET_Pos)
     
    #define FSMC_BWTR1_ADDSET_1   (0x2UL << FSMC_BWTR1_ADDSET_Pos)
     
    #define FSMC_BWTR1_ADDSET_2   (0x4UL << FSMC_BWTR1_ADDSET_Pos)
     
    #define FSMC_BWTR1_ADDSET_3   (0x8UL << FSMC_BWTR1_ADDSET_Pos)
     
    #define FSMC_BWTR1_ADDHLD_Pos   (4U)
     
    #define FSMC_BWTR1_ADDHLD_Msk   (0xFUL << FSMC_BWTR1_ADDHLD_Pos)
     
    #define FSMC_BWTR1_ADDHLD   FSMC_BWTR1_ADDHLD_Msk
     
    #define FSMC_BWTR1_ADDHLD_0   (0x1UL << FSMC_BWTR1_ADDHLD_Pos)
     
    #define FSMC_BWTR1_ADDHLD_1   (0x2UL << FSMC_BWTR1_ADDHLD_Pos)
     
    #define FSMC_BWTR1_ADDHLD_2   (0x4UL << FSMC_BWTR1_ADDHLD_Pos)
     
    #define FSMC_BWTR1_ADDHLD_3   (0x8UL << FSMC_BWTR1_ADDHLD_Pos)
     
    #define FSMC_BWTR1_DATAST_Pos   (8U)
     
    #define FSMC_BWTR1_DATAST_Msk   (0xFFUL << FSMC_BWTR1_DATAST_Pos)
     
    #define FSMC_BWTR1_DATAST   FSMC_BWTR1_DATAST_Msk
     
    #define FSMC_BWTR1_DATAST_0   (0x01UL << FSMC_BWTR1_DATAST_Pos)
     
    #define FSMC_BWTR1_DATAST_1   (0x02UL << FSMC_BWTR1_DATAST_Pos)
     
    #define FSMC_BWTR1_DATAST_2   (0x04UL << FSMC_BWTR1_DATAST_Pos)
     
    #define FSMC_BWTR1_DATAST_3   (0x08UL << FSMC_BWTR1_DATAST_Pos)
     
    #define FSMC_BWTR1_DATAST_4   (0x10UL << FSMC_BWTR1_DATAST_Pos)
     
    #define FSMC_BWTR1_DATAST_5   (0x20UL << FSMC_BWTR1_DATAST_Pos)
     
    #define FSMC_BWTR1_DATAST_6   (0x40UL << FSMC_BWTR1_DATAST_Pos)
     
    #define FSMC_BWTR1_DATAST_7   (0x80UL << FSMC_BWTR1_DATAST_Pos)
     
    #define FSMC_BWTR1_BUSTURN_Pos   (16U)
     
    #define FSMC_BWTR1_BUSTURN_Msk   (0xFUL << FSMC_BWTR1_BUSTURN_Pos)
     
    #define FSMC_BWTR1_BUSTURN   FSMC_BWTR1_BUSTURN_Msk
     
    #define FSMC_BWTR1_BUSTURN_0   (0x1UL << FSMC_BWTR1_BUSTURN_Pos)
     
    #define FSMC_BWTR1_BUSTURN_1   (0x2UL << FSMC_BWTR1_BUSTURN_Pos)
     
    #define FSMC_BWTR1_BUSTURN_2   (0x4UL << FSMC_BWTR1_BUSTURN_Pos)
     
    #define FSMC_BWTR1_BUSTURN_3   (0x8UL << FSMC_BWTR1_BUSTURN_Pos)
     
    #define FSMC_BWTR1_ACCMOD_Pos   (28U)
     
    #define FSMC_BWTR1_ACCMOD_Msk   (0x3UL << FSMC_BWTR1_ACCMOD_Pos)
     
    #define FSMC_BWTR1_ACCMOD   FSMC_BWTR1_ACCMOD_Msk
     
    #define FSMC_BWTR1_ACCMOD_0   (0x1UL << FSMC_BWTR1_ACCMOD_Pos)
     
    #define FSMC_BWTR1_ACCMOD_1   (0x2UL << FSMC_BWTR1_ACCMOD_Pos)
     
    #define FSMC_BWTR2_ADDSET_Pos   (0U)
     
    #define FSMC_BWTR2_ADDSET_Msk   (0xFUL << FSMC_BWTR2_ADDSET_Pos)
     
    #define FSMC_BWTR2_ADDSET   FSMC_BWTR2_ADDSET_Msk
     
    #define FSMC_BWTR2_ADDSET_0   (0x1UL << FSMC_BWTR2_ADDSET_Pos)
     
    #define FSMC_BWTR2_ADDSET_1   (0x2UL << FSMC_BWTR2_ADDSET_Pos)
     
    #define FSMC_BWTR2_ADDSET_2   (0x4UL << FSMC_BWTR2_ADDSET_Pos)
     
    #define FSMC_BWTR2_ADDSET_3   (0x8UL << FSMC_BWTR2_ADDSET_Pos)
     
    #define FSMC_BWTR2_ADDHLD_Pos   (4U)
     
    #define FSMC_BWTR2_ADDHLD_Msk   (0xFUL << FSMC_BWTR2_ADDHLD_Pos)
     
    #define FSMC_BWTR2_ADDHLD   FSMC_BWTR2_ADDHLD_Msk
     
    #define FSMC_BWTR2_ADDHLD_0   (0x1UL << FSMC_BWTR2_ADDHLD_Pos)
     
    #define FSMC_BWTR2_ADDHLD_1   (0x2UL << FSMC_BWTR2_ADDHLD_Pos)
     
    #define FSMC_BWTR2_ADDHLD_2   (0x4UL << FSMC_BWTR2_ADDHLD_Pos)
     
    #define FSMC_BWTR2_ADDHLD_3   (0x8UL << FSMC_BWTR2_ADDHLD_Pos)
     
    #define FSMC_BWTR2_DATAST_Pos   (8U)
     
    #define FSMC_BWTR2_DATAST_Msk   (0xFFUL << FSMC_BWTR2_DATAST_Pos)
     
    #define FSMC_BWTR2_DATAST   FSMC_BWTR2_DATAST_Msk
     
    #define FSMC_BWTR2_DATAST_0   (0x01UL << FSMC_BWTR2_DATAST_Pos)
     
    #define FSMC_BWTR2_DATAST_1   (0x02UL << FSMC_BWTR2_DATAST_Pos)
     
    #define FSMC_BWTR2_DATAST_2   (0x04UL << FSMC_BWTR2_DATAST_Pos)
     
    #define FSMC_BWTR2_DATAST_3   (0x08UL << FSMC_BWTR2_DATAST_Pos)
     
    #define FSMC_BWTR2_DATAST_4   (0x10UL << FSMC_BWTR2_DATAST_Pos)
     
    #define FSMC_BWTR2_DATAST_5   (0x20UL << FSMC_BWTR2_DATAST_Pos)
     
    #define FSMC_BWTR2_DATAST_6   (0x40UL << FSMC_BWTR2_DATAST_Pos)
     
    #define FSMC_BWTR2_DATAST_7   (0x80UL << FSMC_BWTR2_DATAST_Pos)
     
    #define FSMC_BWTR2_BUSTURN_Pos   (16U)
     
    #define FSMC_BWTR2_BUSTURN_Msk   (0xFUL << FSMC_BWTR2_BUSTURN_Pos)
     
    #define FSMC_BWTR2_BUSTURN   FSMC_BWTR2_BUSTURN_Msk
     
    #define FSMC_BWTR2_BUSTURN_0   (0x1UL << FSMC_BWTR2_BUSTURN_Pos)
     
    #define FSMC_BWTR2_BUSTURN_1   (0x2UL << FSMC_BWTR2_BUSTURN_Pos)
     
    #define FSMC_BWTR2_BUSTURN_2   (0x4UL << FSMC_BWTR2_BUSTURN_Pos)
     
    #define FSMC_BWTR2_BUSTURN_3   (0x8UL << FSMC_BWTR2_BUSTURN_Pos)
     
    #define FSMC_BWTR2_ACCMOD_Pos   (28U)
     
    #define FSMC_BWTR2_ACCMOD_Msk   (0x3UL << FSMC_BWTR2_ACCMOD_Pos)
     
    #define FSMC_BWTR2_ACCMOD   FSMC_BWTR2_ACCMOD_Msk
     
    #define FSMC_BWTR2_ACCMOD_0   (0x1UL << FSMC_BWTR2_ACCMOD_Pos)
     
    #define FSMC_BWTR2_ACCMOD_1   (0x2UL << FSMC_BWTR2_ACCMOD_Pos)
     
    #define FSMC_BWTR3_ADDSET_Pos   (0U)
     
    #define FSMC_BWTR3_ADDSET_Msk   (0xFUL << FSMC_BWTR3_ADDSET_Pos)
     
    #define FSMC_BWTR3_ADDSET   FSMC_BWTR3_ADDSET_Msk
     
    #define FSMC_BWTR3_ADDSET_0   (0x1UL << FSMC_BWTR3_ADDSET_Pos)
     
    #define FSMC_BWTR3_ADDSET_1   (0x2UL << FSMC_BWTR3_ADDSET_Pos)
     
    #define FSMC_BWTR3_ADDSET_2   (0x4UL << FSMC_BWTR3_ADDSET_Pos)
     
    #define FSMC_BWTR3_ADDSET_3   (0x8UL << FSMC_BWTR3_ADDSET_Pos)
     
    #define FSMC_BWTR3_ADDHLD_Pos   (4U)
     
    #define FSMC_BWTR3_ADDHLD_Msk   (0xFUL << FSMC_BWTR3_ADDHLD_Pos)
     
    #define FSMC_BWTR3_ADDHLD   FSMC_BWTR3_ADDHLD_Msk
     
    #define FSMC_BWTR3_ADDHLD_0   (0x1UL << FSMC_BWTR3_ADDHLD_Pos)
     
    #define FSMC_BWTR3_ADDHLD_1   (0x2UL << FSMC_BWTR3_ADDHLD_Pos)
     
    #define FSMC_BWTR3_ADDHLD_2   (0x4UL << FSMC_BWTR3_ADDHLD_Pos)
     
    #define FSMC_BWTR3_ADDHLD_3   (0x8UL << FSMC_BWTR3_ADDHLD_Pos)
     
    #define FSMC_BWTR3_DATAST_Pos   (8U)
     
    #define FSMC_BWTR3_DATAST_Msk   (0xFFUL << FSMC_BWTR3_DATAST_Pos)
     
    #define FSMC_BWTR3_DATAST   FSMC_BWTR3_DATAST_Msk
     
    #define FSMC_BWTR3_DATAST_0   (0x01UL << FSMC_BWTR3_DATAST_Pos)
     
    #define FSMC_BWTR3_DATAST_1   (0x02UL << FSMC_BWTR3_DATAST_Pos)
     
    #define FSMC_BWTR3_DATAST_2   (0x04UL << FSMC_BWTR3_DATAST_Pos)
     
    #define FSMC_BWTR3_DATAST_3   (0x08UL << FSMC_BWTR3_DATAST_Pos)
     
    #define FSMC_BWTR3_DATAST_4   (0x10UL << FSMC_BWTR3_DATAST_Pos)
     
    #define FSMC_BWTR3_DATAST_5   (0x20UL << FSMC_BWTR3_DATAST_Pos)
     
    #define FSMC_BWTR3_DATAST_6   (0x40UL << FSMC_BWTR3_DATAST_Pos)
     
    #define FSMC_BWTR3_DATAST_7   (0x80UL << FSMC_BWTR3_DATAST_Pos)
     
    #define FSMC_BWTR3_BUSTURN_Pos   (16U)
     
    #define FSMC_BWTR3_BUSTURN_Msk   (0xFUL << FSMC_BWTR3_BUSTURN_Pos)
     
    #define FSMC_BWTR3_BUSTURN   FSMC_BWTR3_BUSTURN_Msk
     
    #define FSMC_BWTR3_BUSTURN_0   (0x1UL << FSMC_BWTR3_BUSTURN_Pos)
     
    #define FSMC_BWTR3_BUSTURN_1   (0x2UL << FSMC_BWTR3_BUSTURN_Pos)
     
    #define FSMC_BWTR3_BUSTURN_2   (0x4UL << FSMC_BWTR3_BUSTURN_Pos)
     
    #define FSMC_BWTR3_BUSTURN_3   (0x8UL << FSMC_BWTR3_BUSTURN_Pos)
     
    #define FSMC_BWTR3_ACCMOD_Pos   (28U)
     
    #define FSMC_BWTR3_ACCMOD_Msk   (0x3UL << FSMC_BWTR3_ACCMOD_Pos)
     
    #define FSMC_BWTR3_ACCMOD   FSMC_BWTR3_ACCMOD_Msk
     
    #define FSMC_BWTR3_ACCMOD_0   (0x1UL << FSMC_BWTR3_ACCMOD_Pos)
     
    #define FSMC_BWTR3_ACCMOD_1   (0x2UL << FSMC_BWTR3_ACCMOD_Pos)
     
    #define FSMC_BWTR4_ADDSET_Pos   (0U)
     
    #define FSMC_BWTR4_ADDSET_Msk   (0xFUL << FSMC_BWTR4_ADDSET_Pos)
     
    #define FSMC_BWTR4_ADDSET   FSMC_BWTR4_ADDSET_Msk
     
    #define FSMC_BWTR4_ADDSET_0   (0x1UL << FSMC_BWTR4_ADDSET_Pos)
     
    #define FSMC_BWTR4_ADDSET_1   (0x2UL << FSMC_BWTR4_ADDSET_Pos)
     
    #define FSMC_BWTR4_ADDSET_2   (0x4UL << FSMC_BWTR4_ADDSET_Pos)
     
    #define FSMC_BWTR4_ADDSET_3   (0x8UL << FSMC_BWTR4_ADDSET_Pos)
     
    #define FSMC_BWTR4_ADDHLD_Pos   (4U)
     
    #define FSMC_BWTR4_ADDHLD_Msk   (0xFUL << FSMC_BWTR4_ADDHLD_Pos)
     
    #define FSMC_BWTR4_ADDHLD   FSMC_BWTR4_ADDHLD_Msk
     
    #define FSMC_BWTR4_ADDHLD_0   (0x1UL << FSMC_BWTR4_ADDHLD_Pos)
     
    #define FSMC_BWTR4_ADDHLD_1   (0x2UL << FSMC_BWTR4_ADDHLD_Pos)
     
    #define FSMC_BWTR4_ADDHLD_2   (0x4UL << FSMC_BWTR4_ADDHLD_Pos)
     
    #define FSMC_BWTR4_ADDHLD_3   (0x8UL << FSMC_BWTR4_ADDHLD_Pos)
     
    #define FSMC_BWTR4_DATAST_Pos   (8U)
     
    #define FSMC_BWTR4_DATAST_Msk   (0xFFUL << FSMC_BWTR4_DATAST_Pos)
     
    #define FSMC_BWTR4_DATAST   FSMC_BWTR4_DATAST_Msk
     
    #define FSMC_BWTR4_DATAST_0   0x00000100U
     
    #define FSMC_BWTR4_DATAST_1   0x00000200U
     
    #define FSMC_BWTR4_DATAST_2   0x00000400U
     
    #define FSMC_BWTR4_DATAST_3   0x00000800U
     
    #define FSMC_BWTR4_DATAST_4   0x00001000U
     
    #define FSMC_BWTR4_DATAST_5   0x00002000U
     
    #define FSMC_BWTR4_DATAST_6   0x00004000U
     
    #define FSMC_BWTR4_DATAST_7   0x00008000U
     
    #define FSMC_BWTR4_BUSTURN_Pos   (16U)
     
    #define FSMC_BWTR4_BUSTURN_Msk   (0xFUL << FSMC_BWTR4_BUSTURN_Pos)
     
    #define FSMC_BWTR4_BUSTURN   FSMC_BWTR4_BUSTURN_Msk
     
    #define FSMC_BWTR4_BUSTURN_0   (0x1UL << FSMC_BWTR4_BUSTURN_Pos)
     
    #define FSMC_BWTR4_BUSTURN_1   (0x2UL << FSMC_BWTR4_BUSTURN_Pos)
     
    #define FSMC_BWTR4_BUSTURN_2   (0x4UL << FSMC_BWTR4_BUSTURN_Pos)
     
    #define FSMC_BWTR4_BUSTURN_3   (0x8UL << FSMC_BWTR4_BUSTURN_Pos)
     
    #define FSMC_BWTR4_ACCMOD_Pos   (28U)
     
    #define FSMC_BWTR4_ACCMOD_Msk   (0x3UL << FSMC_BWTR4_ACCMOD_Pos)
     
    #define FSMC_BWTR4_ACCMOD   FSMC_BWTR4_ACCMOD_Msk
     
    #define FSMC_BWTR4_ACCMOD_0   (0x1UL << FSMC_BWTR4_ACCMOD_Pos)
     
    #define FSMC_BWTR4_ACCMOD_1   (0x2UL << FSMC_BWTR4_ACCMOD_Pos)
     
    #define FSMC_PCR2_PWAITEN_Pos   (1U)
     
    #define FSMC_PCR2_PWAITEN_Msk   (0x1UL << FSMC_PCR2_PWAITEN_Pos)
     
    #define FSMC_PCR2_PWAITEN   FSMC_PCR2_PWAITEN_Msk
     
    #define FSMC_PCR2_PBKEN_Pos   (2U)
     
    #define FSMC_PCR2_PBKEN_Msk   (0x1UL << FSMC_PCR2_PBKEN_Pos)
     
    #define FSMC_PCR2_PBKEN   FSMC_PCR2_PBKEN_Msk
     
    #define FSMC_PCR2_PTYP_Pos   (3U)
     
    #define FSMC_PCR2_PTYP_Msk   (0x1UL << FSMC_PCR2_PTYP_Pos)
     
    #define FSMC_PCR2_PTYP   FSMC_PCR2_PTYP_Msk
     
    #define FSMC_PCR2_PWID_Pos   (4U)
     
    #define FSMC_PCR2_PWID_Msk   (0x3UL << FSMC_PCR2_PWID_Pos)
     
    #define FSMC_PCR2_PWID   FSMC_PCR2_PWID_Msk
     
    #define FSMC_PCR2_PWID_0   (0x1UL << FSMC_PCR2_PWID_Pos)
     
    #define FSMC_PCR2_PWID_1   (0x2UL << FSMC_PCR2_PWID_Pos)
     
    #define FSMC_PCR2_ECCEN_Pos   (6U)
     
    #define FSMC_PCR2_ECCEN_Msk   (0x1UL << FSMC_PCR2_ECCEN_Pos)
     
    #define FSMC_PCR2_ECCEN   FSMC_PCR2_ECCEN_Msk
     
    #define FSMC_PCR2_TCLR_Pos   (9U)
     
    #define FSMC_PCR2_TCLR_Msk   (0xFUL << FSMC_PCR2_TCLR_Pos)
     
    #define FSMC_PCR2_TCLR   FSMC_PCR2_TCLR_Msk
     
    #define FSMC_PCR2_TCLR_0   (0x1UL << FSMC_PCR2_TCLR_Pos)
     
    #define FSMC_PCR2_TCLR_1   (0x2UL << FSMC_PCR2_TCLR_Pos)
     
    #define FSMC_PCR2_TCLR_2   (0x4UL << FSMC_PCR2_TCLR_Pos)
     
    #define FSMC_PCR2_TCLR_3   (0x8UL << FSMC_PCR2_TCLR_Pos)
     
    #define FSMC_PCR2_TAR_Pos   (13U)
     
    #define FSMC_PCR2_TAR_Msk   (0xFUL << FSMC_PCR2_TAR_Pos)
     
    #define FSMC_PCR2_TAR   FSMC_PCR2_TAR_Msk
     
    #define FSMC_PCR2_TAR_0   (0x1UL << FSMC_PCR2_TAR_Pos)
     
    #define FSMC_PCR2_TAR_1   (0x2UL << FSMC_PCR2_TAR_Pos)
     
    #define FSMC_PCR2_TAR_2   (0x4UL << FSMC_PCR2_TAR_Pos)
     
    #define FSMC_PCR2_TAR_3   (0x8UL << FSMC_PCR2_TAR_Pos)
     
    #define FSMC_PCR2_ECCPS_Pos   (17U)
     
    #define FSMC_PCR2_ECCPS_Msk   (0x7UL << FSMC_PCR2_ECCPS_Pos)
     
    #define FSMC_PCR2_ECCPS   FSMC_PCR2_ECCPS_Msk
     
    #define FSMC_PCR2_ECCPS_0   (0x1UL << FSMC_PCR2_ECCPS_Pos)
     
    #define FSMC_PCR2_ECCPS_1   (0x2UL << FSMC_PCR2_ECCPS_Pos)
     
    #define FSMC_PCR2_ECCPS_2   (0x4UL << FSMC_PCR2_ECCPS_Pos)
     
    #define FSMC_PCR3_PWAITEN_Pos   (1U)
     
    #define FSMC_PCR3_PWAITEN_Msk   (0x1UL << FSMC_PCR3_PWAITEN_Pos)
     
    #define FSMC_PCR3_PWAITEN   FSMC_PCR3_PWAITEN_Msk
     
    #define FSMC_PCR3_PBKEN_Pos   (2U)
     
    #define FSMC_PCR3_PBKEN_Msk   (0x1UL << FSMC_PCR3_PBKEN_Pos)
     
    #define FSMC_PCR3_PBKEN   FSMC_PCR3_PBKEN_Msk
     
    #define FSMC_PCR3_PTYP_Pos   (3U)
     
    #define FSMC_PCR3_PTYP_Msk   (0x1UL << FSMC_PCR3_PTYP_Pos)
     
    #define FSMC_PCR3_PTYP   FSMC_PCR3_PTYP_Msk
     
    #define FSMC_PCR3_PWID_Pos   (4U)
     
    #define FSMC_PCR3_PWID_Msk   (0x3UL << FSMC_PCR3_PWID_Pos)
     
    #define FSMC_PCR3_PWID   FSMC_PCR3_PWID_Msk
     
    #define FSMC_PCR3_PWID_0   (0x1UL << FSMC_PCR3_PWID_Pos)
     
    #define FSMC_PCR3_PWID_1   (0x2UL << FSMC_PCR3_PWID_Pos)
     
    #define FSMC_PCR3_ECCEN_Pos   (6U)
     
    #define FSMC_PCR3_ECCEN_Msk   (0x1UL << FSMC_PCR3_ECCEN_Pos)
     
    #define FSMC_PCR3_ECCEN   FSMC_PCR3_ECCEN_Msk
     
    #define FSMC_PCR3_TCLR_Pos   (9U)
     
    #define FSMC_PCR3_TCLR_Msk   (0xFUL << FSMC_PCR3_TCLR_Pos)
     
    #define FSMC_PCR3_TCLR   FSMC_PCR3_TCLR_Msk
     
    #define FSMC_PCR3_TCLR_0   (0x1UL << FSMC_PCR3_TCLR_Pos)
     
    #define FSMC_PCR3_TCLR_1   (0x2UL << FSMC_PCR3_TCLR_Pos)
     
    #define FSMC_PCR3_TCLR_2   (0x4UL << FSMC_PCR3_TCLR_Pos)
     
    #define FSMC_PCR3_TCLR_3   (0x8UL << FSMC_PCR3_TCLR_Pos)
     
    #define FSMC_PCR3_TAR_Pos   (13U)
     
    #define FSMC_PCR3_TAR_Msk   (0xFUL << FSMC_PCR3_TAR_Pos)
     
    #define FSMC_PCR3_TAR   FSMC_PCR3_TAR_Msk
     
    #define FSMC_PCR3_TAR_0   (0x1UL << FSMC_PCR3_TAR_Pos)
     
    #define FSMC_PCR3_TAR_1   (0x2UL << FSMC_PCR3_TAR_Pos)
     
    #define FSMC_PCR3_TAR_2   (0x4UL << FSMC_PCR3_TAR_Pos)
     
    #define FSMC_PCR3_TAR_3   (0x8UL << FSMC_PCR3_TAR_Pos)
     
    #define FSMC_PCR3_ECCPS_Pos   (17U)
     
    #define FSMC_PCR3_ECCPS_Msk   (0x7UL << FSMC_PCR3_ECCPS_Pos)
     
    #define FSMC_PCR3_ECCPS   FSMC_PCR3_ECCPS_Msk
     
    #define FSMC_PCR3_ECCPS_0   (0x1UL << FSMC_PCR3_ECCPS_Pos)
     
    #define FSMC_PCR3_ECCPS_1   (0x2UL << FSMC_PCR3_ECCPS_Pos)
     
    #define FSMC_PCR3_ECCPS_2   (0x4UL << FSMC_PCR3_ECCPS_Pos)
     
    #define FSMC_PCR4_PWAITEN_Pos   (1U)
     
    #define FSMC_PCR4_PWAITEN_Msk   (0x1UL << FSMC_PCR4_PWAITEN_Pos)
     
    #define FSMC_PCR4_PWAITEN   FSMC_PCR4_PWAITEN_Msk
     
    #define FSMC_PCR4_PBKEN_Pos   (2U)
     
    #define FSMC_PCR4_PBKEN_Msk   (0x1UL << FSMC_PCR4_PBKEN_Pos)
     
    #define FSMC_PCR4_PBKEN   FSMC_PCR4_PBKEN_Msk
     
    #define FSMC_PCR4_PTYP_Pos   (3U)
     
    #define FSMC_PCR4_PTYP_Msk   (0x1UL << FSMC_PCR4_PTYP_Pos)
     
    #define FSMC_PCR4_PTYP   FSMC_PCR4_PTYP_Msk
     
    #define FSMC_PCR4_PWID_Pos   (4U)
     
    #define FSMC_PCR4_PWID_Msk   (0x3UL << FSMC_PCR4_PWID_Pos)
     
    #define FSMC_PCR4_PWID   FSMC_PCR4_PWID_Msk
     
    #define FSMC_PCR4_PWID_0   (0x1UL << FSMC_PCR4_PWID_Pos)
     
    #define FSMC_PCR4_PWID_1   (0x2UL << FSMC_PCR4_PWID_Pos)
     
    #define FSMC_PCR4_ECCEN_Pos   (6U)
     
    #define FSMC_PCR4_ECCEN_Msk   (0x1UL << FSMC_PCR4_ECCEN_Pos)
     
    #define FSMC_PCR4_ECCEN   FSMC_PCR4_ECCEN_Msk
     
    #define FSMC_PCR4_TCLR_Pos   (9U)
     
    #define FSMC_PCR4_TCLR_Msk   (0xFUL << FSMC_PCR4_TCLR_Pos)
     
    #define FSMC_PCR4_TCLR   FSMC_PCR4_TCLR_Msk
     
    #define FSMC_PCR4_TCLR_0   (0x1UL << FSMC_PCR4_TCLR_Pos)
     
    #define FSMC_PCR4_TCLR_1   (0x2UL << FSMC_PCR4_TCLR_Pos)
     
    #define FSMC_PCR4_TCLR_2   (0x4UL << FSMC_PCR4_TCLR_Pos)
     
    #define FSMC_PCR4_TCLR_3   (0x8UL << FSMC_PCR4_TCLR_Pos)
     
    #define FSMC_PCR4_TAR_Pos   (13U)
     
    #define FSMC_PCR4_TAR_Msk   (0xFUL << FSMC_PCR4_TAR_Pos)
     
    #define FSMC_PCR4_TAR   FSMC_PCR4_TAR_Msk
     
    #define FSMC_PCR4_TAR_0   (0x1UL << FSMC_PCR4_TAR_Pos)
     
    #define FSMC_PCR4_TAR_1   (0x2UL << FSMC_PCR4_TAR_Pos)
     
    #define FSMC_PCR4_TAR_2   (0x4UL << FSMC_PCR4_TAR_Pos)
     
    #define FSMC_PCR4_TAR_3   (0x8UL << FSMC_PCR4_TAR_Pos)
     
    #define FSMC_PCR4_ECCPS_Pos   (17U)
     
    #define FSMC_PCR4_ECCPS_Msk   (0x7UL << FSMC_PCR4_ECCPS_Pos)
     
    #define FSMC_PCR4_ECCPS   FSMC_PCR4_ECCPS_Msk
     
    #define FSMC_PCR4_ECCPS_0   (0x1UL << FSMC_PCR4_ECCPS_Pos)
     
    #define FSMC_PCR4_ECCPS_1   (0x2UL << FSMC_PCR4_ECCPS_Pos)
     
    #define FSMC_PCR4_ECCPS_2   (0x4UL << FSMC_PCR4_ECCPS_Pos)
     
    #define FSMC_SR2_IRS_Pos   (0U)
     
    #define FSMC_SR2_IRS_Msk   (0x1UL << FSMC_SR2_IRS_Pos)
     
    #define FSMC_SR2_IRS   FSMC_SR2_IRS_Msk
     
    #define FSMC_SR2_ILS_Pos   (1U)
     
    #define FSMC_SR2_ILS_Msk   (0x1UL << FSMC_SR2_ILS_Pos)
     
    #define FSMC_SR2_ILS   FSMC_SR2_ILS_Msk
     
    #define FSMC_SR2_IFS_Pos   (2U)
     
    #define FSMC_SR2_IFS_Msk   (0x1UL << FSMC_SR2_IFS_Pos)
     
    #define FSMC_SR2_IFS   FSMC_SR2_IFS_Msk
     
    #define FSMC_SR2_IREN_Pos   (3U)
     
    #define FSMC_SR2_IREN_Msk   (0x1UL << FSMC_SR2_IREN_Pos)
     
    #define FSMC_SR2_IREN   FSMC_SR2_IREN_Msk
     
    #define FSMC_SR2_ILEN_Pos   (4U)
     
    #define FSMC_SR2_ILEN_Msk   (0x1UL << FSMC_SR2_ILEN_Pos)
     
    #define FSMC_SR2_ILEN   FSMC_SR2_ILEN_Msk
     
    #define FSMC_SR2_IFEN_Pos   (5U)
     
    #define FSMC_SR2_IFEN_Msk   (0x1UL << FSMC_SR2_IFEN_Pos)
     
    #define FSMC_SR2_IFEN   FSMC_SR2_IFEN_Msk
     
    #define FSMC_SR2_FEMPT_Pos   (6U)
     
    #define FSMC_SR2_FEMPT_Msk   (0x1UL << FSMC_SR2_FEMPT_Pos)
     
    #define FSMC_SR2_FEMPT   FSMC_SR2_FEMPT_Msk
     
    #define FSMC_SR3_IRS_Pos   (0U)
     
    #define FSMC_SR3_IRS_Msk   (0x1UL << FSMC_SR3_IRS_Pos)
     
    #define FSMC_SR3_IRS   FSMC_SR3_IRS_Msk
     
    #define FSMC_SR3_ILS_Pos   (1U)
     
    #define FSMC_SR3_ILS_Msk   (0x1UL << FSMC_SR3_ILS_Pos)
     
    #define FSMC_SR3_ILS   FSMC_SR3_ILS_Msk
     
    #define FSMC_SR3_IFS_Pos   (2U)
     
    #define FSMC_SR3_IFS_Msk   (0x1UL << FSMC_SR3_IFS_Pos)
     
    #define FSMC_SR3_IFS   FSMC_SR3_IFS_Msk
     
    #define FSMC_SR3_IREN_Pos   (3U)
     
    #define FSMC_SR3_IREN_Msk   (0x1UL << FSMC_SR3_IREN_Pos)
     
    #define FSMC_SR3_IREN   FSMC_SR3_IREN_Msk
     
    #define FSMC_SR3_ILEN_Pos   (4U)
     
    #define FSMC_SR3_ILEN_Msk   (0x1UL << FSMC_SR3_ILEN_Pos)
     
    #define FSMC_SR3_ILEN   FSMC_SR3_ILEN_Msk
     
    #define FSMC_SR3_IFEN_Pos   (5U)
     
    #define FSMC_SR3_IFEN_Msk   (0x1UL << FSMC_SR3_IFEN_Pos)
     
    #define FSMC_SR3_IFEN   FSMC_SR3_IFEN_Msk
     
    #define FSMC_SR3_FEMPT_Pos   (6U)
     
    #define FSMC_SR3_FEMPT_Msk   (0x1UL << FSMC_SR3_FEMPT_Pos)
     
    #define FSMC_SR3_FEMPT   FSMC_SR3_FEMPT_Msk
     
    #define FSMC_SR4_IRS_Pos   (0U)
     
    #define FSMC_SR4_IRS_Msk   (0x1UL << FSMC_SR4_IRS_Pos)
     
    #define FSMC_SR4_IRS   FSMC_SR4_IRS_Msk
     
    #define FSMC_SR4_ILS_Pos   (1U)
     
    #define FSMC_SR4_ILS_Msk   (0x1UL << FSMC_SR4_ILS_Pos)
     
    #define FSMC_SR4_ILS   FSMC_SR4_ILS_Msk
     
    #define FSMC_SR4_IFS_Pos   (2U)
     
    #define FSMC_SR4_IFS_Msk   (0x1UL << FSMC_SR4_IFS_Pos)
     
    #define FSMC_SR4_IFS   FSMC_SR4_IFS_Msk
     
    #define FSMC_SR4_IREN_Pos   (3U)
     
    #define FSMC_SR4_IREN_Msk   (0x1UL << FSMC_SR4_IREN_Pos)
     
    #define FSMC_SR4_IREN   FSMC_SR4_IREN_Msk
     
    #define FSMC_SR4_ILEN_Pos   (4U)
     
    #define FSMC_SR4_ILEN_Msk   (0x1UL << FSMC_SR4_ILEN_Pos)
     
    #define FSMC_SR4_ILEN   FSMC_SR4_ILEN_Msk
     
    #define FSMC_SR4_IFEN_Pos   (5U)
     
    #define FSMC_SR4_IFEN_Msk   (0x1UL << FSMC_SR4_IFEN_Pos)
     
    #define FSMC_SR4_IFEN   FSMC_SR4_IFEN_Msk
     
    #define FSMC_SR4_FEMPT_Pos   (6U)
     
    #define FSMC_SR4_FEMPT_Msk   (0x1UL << FSMC_SR4_FEMPT_Pos)
     
    #define FSMC_SR4_FEMPT   FSMC_SR4_FEMPT_Msk
     
    #define FSMC_PMEM2_MEMSET2_Pos   (0U)
     
    #define FSMC_PMEM2_MEMSET2_Msk   (0xFFUL << FSMC_PMEM2_MEMSET2_Pos)
     
    #define FSMC_PMEM2_MEMSET2   FSMC_PMEM2_MEMSET2_Msk
     
    #define FSMC_PMEM2_MEMSET2_0   (0x01UL << FSMC_PMEM2_MEMSET2_Pos)
     
    #define FSMC_PMEM2_MEMSET2_1   (0x02UL << FSMC_PMEM2_MEMSET2_Pos)
     
    #define FSMC_PMEM2_MEMSET2_2   (0x04UL << FSMC_PMEM2_MEMSET2_Pos)
     
    #define FSMC_PMEM2_MEMSET2_3   (0x08UL << FSMC_PMEM2_MEMSET2_Pos)
     
    #define FSMC_PMEM2_MEMSET2_4   (0x10UL << FSMC_PMEM2_MEMSET2_Pos)
     
    #define FSMC_PMEM2_MEMSET2_5   (0x20UL << FSMC_PMEM2_MEMSET2_Pos)
     
    #define FSMC_PMEM2_MEMSET2_6   (0x40UL << FSMC_PMEM2_MEMSET2_Pos)
     
    #define FSMC_PMEM2_MEMSET2_7   (0x80UL << FSMC_PMEM2_MEMSET2_Pos)
     
    #define FSMC_PMEM2_MEMWAIT2_Pos   (8U)
     
    #define FSMC_PMEM2_MEMWAIT2_Msk   (0xFFUL << FSMC_PMEM2_MEMWAIT2_Pos)
     
    #define FSMC_PMEM2_MEMWAIT2   FSMC_PMEM2_MEMWAIT2_Msk
     
    #define FSMC_PMEM2_MEMWAIT2_0   (0x01UL << FSMC_PMEM2_MEMWAIT2_Pos)
     
    #define FSMC_PMEM2_MEMWAIT2_1   (0x02UL << FSMC_PMEM2_MEMWAIT2_Pos)
     
    #define FSMC_PMEM2_MEMWAIT2_2   (0x04UL << FSMC_PMEM2_MEMWAIT2_Pos)
     
    #define FSMC_PMEM2_MEMWAIT2_3   (0x08UL << FSMC_PMEM2_MEMWAIT2_Pos)
     
    #define FSMC_PMEM2_MEMWAIT2_4   (0x10UL << FSMC_PMEM2_MEMWAIT2_Pos)
     
    #define FSMC_PMEM2_MEMWAIT2_5   (0x20UL << FSMC_PMEM2_MEMWAIT2_Pos)
     
    #define FSMC_PMEM2_MEMWAIT2_6   (0x40UL << FSMC_PMEM2_MEMWAIT2_Pos)
     
    #define FSMC_PMEM2_MEMWAIT2_7   (0x80UL << FSMC_PMEM2_MEMWAIT2_Pos)
     
    #define FSMC_PMEM2_MEMHOLD2_Pos   (16U)
     
    #define FSMC_PMEM2_MEMHOLD2_Msk   (0xFFUL << FSMC_PMEM2_MEMHOLD2_Pos)
     
    #define FSMC_PMEM2_MEMHOLD2   FSMC_PMEM2_MEMHOLD2_Msk
     
    #define FSMC_PMEM2_MEMHOLD2_0   (0x01UL << FSMC_PMEM2_MEMHOLD2_Pos)
     
    #define FSMC_PMEM2_MEMHOLD2_1   (0x02UL << FSMC_PMEM2_MEMHOLD2_Pos)
     
    #define FSMC_PMEM2_MEMHOLD2_2   (0x04UL << FSMC_PMEM2_MEMHOLD2_Pos)
     
    #define FSMC_PMEM2_MEMHOLD2_3   (0x08UL << FSMC_PMEM2_MEMHOLD2_Pos)
     
    #define FSMC_PMEM2_MEMHOLD2_4   (0x10UL << FSMC_PMEM2_MEMHOLD2_Pos)
     
    #define FSMC_PMEM2_MEMHOLD2_5   (0x20UL << FSMC_PMEM2_MEMHOLD2_Pos)
     
    #define FSMC_PMEM2_MEMHOLD2_6   (0x40UL << FSMC_PMEM2_MEMHOLD2_Pos)
     
    #define FSMC_PMEM2_MEMHOLD2_7   (0x80UL << FSMC_PMEM2_MEMHOLD2_Pos)
     
    #define FSMC_PMEM2_MEMHIZ2_Pos   (24U)
     
    #define FSMC_PMEM2_MEMHIZ2_Msk   (0xFFUL << FSMC_PMEM2_MEMHIZ2_Pos)
     
    #define FSMC_PMEM2_MEMHIZ2   FSMC_PMEM2_MEMHIZ2_Msk
     
    #define FSMC_PMEM2_MEMHIZ2_0   (0x01UL << FSMC_PMEM2_MEMHIZ2_Pos)
     
    #define FSMC_PMEM2_MEMHIZ2_1   (0x02UL << FSMC_PMEM2_MEMHIZ2_Pos)
     
    #define FSMC_PMEM2_MEMHIZ2_2   (0x04UL << FSMC_PMEM2_MEMHIZ2_Pos)
     
    #define FSMC_PMEM2_MEMHIZ2_3   (0x08UL << FSMC_PMEM2_MEMHIZ2_Pos)
     
    #define FSMC_PMEM2_MEMHIZ2_4   (0x10UL << FSMC_PMEM2_MEMHIZ2_Pos)
     
    #define FSMC_PMEM2_MEMHIZ2_5   (0x20UL << FSMC_PMEM2_MEMHIZ2_Pos)
     
    #define FSMC_PMEM2_MEMHIZ2_6   (0x40UL << FSMC_PMEM2_MEMHIZ2_Pos)
     
    #define FSMC_PMEM2_MEMHIZ2_7   (0x80UL << FSMC_PMEM2_MEMHIZ2_Pos)
     
    #define FSMC_PMEM3_MEMSET3_Pos   (0U)
     
    #define FSMC_PMEM3_MEMSET3_Msk   (0xFFUL << FSMC_PMEM3_MEMSET3_Pos)
     
    #define FSMC_PMEM3_MEMSET3   FSMC_PMEM3_MEMSET3_Msk
     
    #define FSMC_PMEM3_MEMSET3_0   (0x01UL << FSMC_PMEM3_MEMSET3_Pos)
     
    #define FSMC_PMEM3_MEMSET3_1   (0x02UL << FSMC_PMEM3_MEMSET3_Pos)
     
    #define FSMC_PMEM3_MEMSET3_2   (0x04UL << FSMC_PMEM3_MEMSET3_Pos)
     
    #define FSMC_PMEM3_MEMSET3_3   (0x08UL << FSMC_PMEM3_MEMSET3_Pos)
     
    #define FSMC_PMEM3_MEMSET3_4   (0x10UL << FSMC_PMEM3_MEMSET3_Pos)
     
    #define FSMC_PMEM3_MEMSET3_5   (0x20UL << FSMC_PMEM3_MEMSET3_Pos)
     
    #define FSMC_PMEM3_MEMSET3_6   (0x40UL << FSMC_PMEM3_MEMSET3_Pos)
     
    #define FSMC_PMEM3_MEMSET3_7   (0x80UL << FSMC_PMEM3_MEMSET3_Pos)
     
    #define FSMC_PMEM3_MEMWAIT3_Pos   (8U)
     
    #define FSMC_PMEM3_MEMWAIT3_Msk   (0xFFUL << FSMC_PMEM3_MEMWAIT3_Pos)
     
    #define FSMC_PMEM3_MEMWAIT3   FSMC_PMEM3_MEMWAIT3_Msk
     
    #define FSMC_PMEM3_MEMWAIT3_0   (0x01UL << FSMC_PMEM3_MEMWAIT3_Pos)
     
    #define FSMC_PMEM3_MEMWAIT3_1   (0x02UL << FSMC_PMEM3_MEMWAIT3_Pos)
     
    #define FSMC_PMEM3_MEMWAIT3_2   (0x04UL << FSMC_PMEM3_MEMWAIT3_Pos)
     
    #define FSMC_PMEM3_MEMWAIT3_3   (0x08UL << FSMC_PMEM3_MEMWAIT3_Pos)
     
    #define FSMC_PMEM3_MEMWAIT3_4   (0x10UL << FSMC_PMEM3_MEMWAIT3_Pos)
     
    #define FSMC_PMEM3_MEMWAIT3_5   (0x20UL << FSMC_PMEM3_MEMWAIT3_Pos)
     
    #define FSMC_PMEM3_MEMWAIT3_6   (0x40UL << FSMC_PMEM3_MEMWAIT3_Pos)
     
    #define FSMC_PMEM3_MEMWAIT3_7   (0x80UL << FSMC_PMEM3_MEMWAIT3_Pos)
     
    #define FSMC_PMEM3_MEMHOLD3_Pos   (16U)
     
    #define FSMC_PMEM3_MEMHOLD3_Msk   (0xFFUL << FSMC_PMEM3_MEMHOLD3_Pos)
     
    #define FSMC_PMEM3_MEMHOLD3   FSMC_PMEM3_MEMHOLD3_Msk
     
    #define FSMC_PMEM3_MEMHOLD3_0   (0x01UL << FSMC_PMEM3_MEMHOLD3_Pos)
     
    #define FSMC_PMEM3_MEMHOLD3_1   (0x02UL << FSMC_PMEM3_MEMHOLD3_Pos)
     
    #define FSMC_PMEM3_MEMHOLD3_2   (0x04UL << FSMC_PMEM3_MEMHOLD3_Pos)
     
    #define FSMC_PMEM3_MEMHOLD3_3   (0x08UL << FSMC_PMEM3_MEMHOLD3_Pos)
     
    #define FSMC_PMEM3_MEMHOLD3_4   (0x10UL << FSMC_PMEM3_MEMHOLD3_Pos)
     
    #define FSMC_PMEM3_MEMHOLD3_5   (0x20UL << FSMC_PMEM3_MEMHOLD3_Pos)
     
    #define FSMC_PMEM3_MEMHOLD3_6   (0x40UL << FSMC_PMEM3_MEMHOLD3_Pos)
     
    #define FSMC_PMEM3_MEMHOLD3_7   (0x80UL << FSMC_PMEM3_MEMHOLD3_Pos)
     
    #define FSMC_PMEM3_MEMHIZ3_Pos   (24U)
     
    #define FSMC_PMEM3_MEMHIZ3_Msk   (0xFFUL << FSMC_PMEM3_MEMHIZ3_Pos)
     
    #define FSMC_PMEM3_MEMHIZ3   FSMC_PMEM3_MEMHIZ3_Msk
     
    #define FSMC_PMEM3_MEMHIZ3_0   (0x01UL << FSMC_PMEM3_MEMHIZ3_Pos)
     
    #define FSMC_PMEM3_MEMHIZ3_1   (0x02UL << FSMC_PMEM3_MEMHIZ3_Pos)
     
    #define FSMC_PMEM3_MEMHIZ3_2   (0x04UL << FSMC_PMEM3_MEMHIZ3_Pos)
     
    #define FSMC_PMEM3_MEMHIZ3_3   (0x08UL << FSMC_PMEM3_MEMHIZ3_Pos)
     
    #define FSMC_PMEM3_MEMHIZ3_4   (0x10UL << FSMC_PMEM3_MEMHIZ3_Pos)
     
    #define FSMC_PMEM3_MEMHIZ3_5   (0x20UL << FSMC_PMEM3_MEMHIZ3_Pos)
     
    #define FSMC_PMEM3_MEMHIZ3_6   (0x40UL << FSMC_PMEM3_MEMHIZ3_Pos)
     
    #define FSMC_PMEM3_MEMHIZ3_7   (0x80UL << FSMC_PMEM3_MEMHIZ3_Pos)
     
    #define FSMC_PMEM4_MEMSET4_Pos   (0U)
     
    #define FSMC_PMEM4_MEMSET4_Msk   (0xFFUL << FSMC_PMEM4_MEMSET4_Pos)
     
    #define FSMC_PMEM4_MEMSET4   FSMC_PMEM4_MEMSET4_Msk
     
    #define FSMC_PMEM4_MEMSET4_0   (0x01UL << FSMC_PMEM4_MEMSET4_Pos)
     
    #define FSMC_PMEM4_MEMSET4_1   (0x02UL << FSMC_PMEM4_MEMSET4_Pos)
     
    #define FSMC_PMEM4_MEMSET4_2   (0x04UL << FSMC_PMEM4_MEMSET4_Pos)
     
    #define FSMC_PMEM4_MEMSET4_3   (0x08UL << FSMC_PMEM4_MEMSET4_Pos)
     
    #define FSMC_PMEM4_MEMSET4_4   (0x10UL << FSMC_PMEM4_MEMSET4_Pos)
     
    #define FSMC_PMEM4_MEMSET4_5   (0x20UL << FSMC_PMEM4_MEMSET4_Pos)
     
    #define FSMC_PMEM4_MEMSET4_6   (0x40UL << FSMC_PMEM4_MEMSET4_Pos)
     
    #define FSMC_PMEM4_MEMSET4_7   (0x80UL << FSMC_PMEM4_MEMSET4_Pos)
     
    #define FSMC_PMEM4_MEMWAIT4_Pos   (8U)
     
    #define FSMC_PMEM4_MEMWAIT4_Msk   (0xFFUL << FSMC_PMEM4_MEMWAIT4_Pos)
     
    #define FSMC_PMEM4_MEMWAIT4   FSMC_PMEM4_MEMWAIT4_Msk
     
    #define FSMC_PMEM4_MEMWAIT4_0   (0x01UL << FSMC_PMEM4_MEMWAIT4_Pos)
     
    #define FSMC_PMEM4_MEMWAIT4_1   (0x02UL << FSMC_PMEM4_MEMWAIT4_Pos)
     
    #define FSMC_PMEM4_MEMWAIT4_2   (0x04UL << FSMC_PMEM4_MEMWAIT4_Pos)
     
    #define FSMC_PMEM4_MEMWAIT4_3   (0x08UL << FSMC_PMEM4_MEMWAIT4_Pos)
     
    #define FSMC_PMEM4_MEMWAIT4_4   (0x10UL << FSMC_PMEM4_MEMWAIT4_Pos)
     
    #define FSMC_PMEM4_MEMWAIT4_5   (0x20UL << FSMC_PMEM4_MEMWAIT4_Pos)
     
    #define FSMC_PMEM4_MEMWAIT4_6   (0x40UL << FSMC_PMEM4_MEMWAIT4_Pos)
     
    #define FSMC_PMEM4_MEMWAIT4_7   (0x80UL << FSMC_PMEM4_MEMWAIT4_Pos)
     
    #define FSMC_PMEM4_MEMHOLD4_Pos   (16U)
     
    #define FSMC_PMEM4_MEMHOLD4_Msk   (0xFFUL << FSMC_PMEM4_MEMHOLD4_Pos)
     
    #define FSMC_PMEM4_MEMHOLD4   FSMC_PMEM4_MEMHOLD4_Msk
     
    #define FSMC_PMEM4_MEMHOLD4_0   (0x01UL << FSMC_PMEM4_MEMHOLD4_Pos)
     
    #define FSMC_PMEM4_MEMHOLD4_1   (0x02UL << FSMC_PMEM4_MEMHOLD4_Pos)
     
    #define FSMC_PMEM4_MEMHOLD4_2   (0x04UL << FSMC_PMEM4_MEMHOLD4_Pos)
     
    #define FSMC_PMEM4_MEMHOLD4_3   (0x08UL << FSMC_PMEM4_MEMHOLD4_Pos)
     
    #define FSMC_PMEM4_MEMHOLD4_4   (0x10UL << FSMC_PMEM4_MEMHOLD4_Pos)
     
    #define FSMC_PMEM4_MEMHOLD4_5   (0x20UL << FSMC_PMEM4_MEMHOLD4_Pos)
     
    #define FSMC_PMEM4_MEMHOLD4_6   (0x40UL << FSMC_PMEM4_MEMHOLD4_Pos)
     
    #define FSMC_PMEM4_MEMHOLD4_7   (0x80UL << FSMC_PMEM4_MEMHOLD4_Pos)
     
    #define FSMC_PMEM4_MEMHIZ4_Pos   (24U)
     
    #define FSMC_PMEM4_MEMHIZ4_Msk   (0xFFUL << FSMC_PMEM4_MEMHIZ4_Pos)
     
    #define FSMC_PMEM4_MEMHIZ4   FSMC_PMEM4_MEMHIZ4_Msk
     
    #define FSMC_PMEM4_MEMHIZ4_0   (0x01UL << FSMC_PMEM4_MEMHIZ4_Pos)
     
    #define FSMC_PMEM4_MEMHIZ4_1   (0x02UL << FSMC_PMEM4_MEMHIZ4_Pos)
     
    #define FSMC_PMEM4_MEMHIZ4_2   (0x04UL << FSMC_PMEM4_MEMHIZ4_Pos)
     
    #define FSMC_PMEM4_MEMHIZ4_3   (0x08UL << FSMC_PMEM4_MEMHIZ4_Pos)
     
    #define FSMC_PMEM4_MEMHIZ4_4   (0x10UL << FSMC_PMEM4_MEMHIZ4_Pos)
     
    #define FSMC_PMEM4_MEMHIZ4_5   (0x20UL << FSMC_PMEM4_MEMHIZ4_Pos)
     
    #define FSMC_PMEM4_MEMHIZ4_6   (0x40UL << FSMC_PMEM4_MEMHIZ4_Pos)
     
    #define FSMC_PMEM4_MEMHIZ4_7   (0x80UL << FSMC_PMEM4_MEMHIZ4_Pos)
     
    #define FSMC_PATT2_ATTSET2_Pos   (0U)
     
    #define FSMC_PATT2_ATTSET2_Msk   (0xFFUL << FSMC_PATT2_ATTSET2_Pos)
     
    #define FSMC_PATT2_ATTSET2   FSMC_PATT2_ATTSET2_Msk
     
    #define FSMC_PATT2_ATTSET2_0   (0x01UL << FSMC_PATT2_ATTSET2_Pos)
     
    #define FSMC_PATT2_ATTSET2_1   (0x02UL << FSMC_PATT2_ATTSET2_Pos)
     
    #define FSMC_PATT2_ATTSET2_2   (0x04UL << FSMC_PATT2_ATTSET2_Pos)
     
    #define FSMC_PATT2_ATTSET2_3   (0x08UL << FSMC_PATT2_ATTSET2_Pos)
     
    #define FSMC_PATT2_ATTSET2_4   (0x10UL << FSMC_PATT2_ATTSET2_Pos)
     
    #define FSMC_PATT2_ATTSET2_5   (0x20UL << FSMC_PATT2_ATTSET2_Pos)
     
    #define FSMC_PATT2_ATTSET2_6   (0x40UL << FSMC_PATT2_ATTSET2_Pos)
     
    #define FSMC_PATT2_ATTSET2_7   (0x80UL << FSMC_PATT2_ATTSET2_Pos)
     
    #define FSMC_PATT2_ATTWAIT2_Pos   (8U)
     
    #define FSMC_PATT2_ATTWAIT2_Msk   (0xFFUL << FSMC_PATT2_ATTWAIT2_Pos)
     
    #define FSMC_PATT2_ATTWAIT2   FSMC_PATT2_ATTWAIT2_Msk
     
    #define FSMC_PATT2_ATTWAIT2_0   (0x01UL << FSMC_PATT2_ATTWAIT2_Pos)
     
    #define FSMC_PATT2_ATTWAIT2_1   (0x02UL << FSMC_PATT2_ATTWAIT2_Pos)
     
    #define FSMC_PATT2_ATTWAIT2_2   (0x04UL << FSMC_PATT2_ATTWAIT2_Pos)
     
    #define FSMC_PATT2_ATTWAIT2_3   (0x08UL << FSMC_PATT2_ATTWAIT2_Pos)
     
    #define FSMC_PATT2_ATTWAIT2_4   (0x10UL << FSMC_PATT2_ATTWAIT2_Pos)
     
    #define FSMC_PATT2_ATTWAIT2_5   (0x20UL << FSMC_PATT2_ATTWAIT2_Pos)
     
    #define FSMC_PATT2_ATTWAIT2_6   (0x40UL << FSMC_PATT2_ATTWAIT2_Pos)
     
    #define FSMC_PATT2_ATTWAIT2_7   (0x80UL << FSMC_PATT2_ATTWAIT2_Pos)
     
    #define FSMC_PATT2_ATTHOLD2_Pos   (16U)
     
    #define FSMC_PATT2_ATTHOLD2_Msk   (0xFFUL << FSMC_PATT2_ATTHOLD2_Pos)
     
    #define FSMC_PATT2_ATTHOLD2   FSMC_PATT2_ATTHOLD2_Msk
     
    #define FSMC_PATT2_ATTHOLD2_0   (0x01UL << FSMC_PATT2_ATTHOLD2_Pos)
     
    #define FSMC_PATT2_ATTHOLD2_1   (0x02UL << FSMC_PATT2_ATTHOLD2_Pos)
     
    #define FSMC_PATT2_ATTHOLD2_2   (0x04UL << FSMC_PATT2_ATTHOLD2_Pos)
     
    #define FSMC_PATT2_ATTHOLD2_3   (0x08UL << FSMC_PATT2_ATTHOLD2_Pos)
     
    #define FSMC_PATT2_ATTHOLD2_4   (0x10UL << FSMC_PATT2_ATTHOLD2_Pos)
     
    #define FSMC_PATT2_ATTHOLD2_5   (0x20UL << FSMC_PATT2_ATTHOLD2_Pos)
     
    #define FSMC_PATT2_ATTHOLD2_6   (0x40UL << FSMC_PATT2_ATTHOLD2_Pos)
     
    #define FSMC_PATT2_ATTHOLD2_7   (0x80UL << FSMC_PATT2_ATTHOLD2_Pos)
     
    #define FSMC_PATT2_ATTHIZ2_Pos   (24U)
     
    #define FSMC_PATT2_ATTHIZ2_Msk   (0xFFUL << FSMC_PATT2_ATTHIZ2_Pos)
     
    #define FSMC_PATT2_ATTHIZ2   FSMC_PATT2_ATTHIZ2_Msk
     
    #define FSMC_PATT2_ATTHIZ2_0   (0x01UL << FSMC_PATT2_ATTHIZ2_Pos)
     
    #define FSMC_PATT2_ATTHIZ2_1   (0x02UL << FSMC_PATT2_ATTHIZ2_Pos)
     
    #define FSMC_PATT2_ATTHIZ2_2   (0x04UL << FSMC_PATT2_ATTHIZ2_Pos)
     
    #define FSMC_PATT2_ATTHIZ2_3   (0x08UL << FSMC_PATT2_ATTHIZ2_Pos)
     
    #define FSMC_PATT2_ATTHIZ2_4   (0x10UL << FSMC_PATT2_ATTHIZ2_Pos)
     
    #define FSMC_PATT2_ATTHIZ2_5   (0x20UL << FSMC_PATT2_ATTHIZ2_Pos)
     
    #define FSMC_PATT2_ATTHIZ2_6   (0x40UL << FSMC_PATT2_ATTHIZ2_Pos)
     
    #define FSMC_PATT2_ATTHIZ2_7   (0x80UL << FSMC_PATT2_ATTHIZ2_Pos)
     
    #define FSMC_PATT3_ATTSET3_Pos   (0U)
     
    #define FSMC_PATT3_ATTSET3_Msk   (0xFFUL << FSMC_PATT3_ATTSET3_Pos)
     
    #define FSMC_PATT3_ATTSET3   FSMC_PATT3_ATTSET3_Msk
     
    #define FSMC_PATT3_ATTSET3_0   (0x01UL << FSMC_PATT3_ATTSET3_Pos)
     
    #define FSMC_PATT3_ATTSET3_1   (0x02UL << FSMC_PATT3_ATTSET3_Pos)
     
    #define FSMC_PATT3_ATTSET3_2   (0x04UL << FSMC_PATT3_ATTSET3_Pos)
     
    #define FSMC_PATT3_ATTSET3_3   (0x08UL << FSMC_PATT3_ATTSET3_Pos)
     
    #define FSMC_PATT3_ATTSET3_4   (0x10UL << FSMC_PATT3_ATTSET3_Pos)
     
    #define FSMC_PATT3_ATTSET3_5   (0x20UL << FSMC_PATT3_ATTSET3_Pos)
     
    #define FSMC_PATT3_ATTSET3_6   (0x40UL << FSMC_PATT3_ATTSET3_Pos)
     
    #define FSMC_PATT3_ATTSET3_7   (0x80UL << FSMC_PATT3_ATTSET3_Pos)
     
    #define FSMC_PATT3_ATTWAIT3_Pos   (8U)
     
    #define FSMC_PATT3_ATTWAIT3_Msk   (0xFFUL << FSMC_PATT3_ATTWAIT3_Pos)
     
    #define FSMC_PATT3_ATTWAIT3   FSMC_PATT3_ATTWAIT3_Msk
     
    #define FSMC_PATT3_ATTWAIT3_0   (0x01UL << FSMC_PATT3_ATTWAIT3_Pos)
     
    #define FSMC_PATT3_ATTWAIT3_1   (0x02UL << FSMC_PATT3_ATTWAIT3_Pos)
     
    #define FSMC_PATT3_ATTWAIT3_2   (0x04UL << FSMC_PATT3_ATTWAIT3_Pos)
     
    #define FSMC_PATT3_ATTWAIT3_3   (0x08UL << FSMC_PATT3_ATTWAIT3_Pos)
     
    #define FSMC_PATT3_ATTWAIT3_4   (0x10UL << FSMC_PATT3_ATTWAIT3_Pos)
     
    #define FSMC_PATT3_ATTWAIT3_5   (0x20UL << FSMC_PATT3_ATTWAIT3_Pos)
     
    #define FSMC_PATT3_ATTWAIT3_6   (0x40UL << FSMC_PATT3_ATTWAIT3_Pos)
     
    #define FSMC_PATT3_ATTWAIT3_7   (0x80UL << FSMC_PATT3_ATTWAIT3_Pos)
     
    #define FSMC_PATT3_ATTHOLD3_Pos   (16U)
     
    #define FSMC_PATT3_ATTHOLD3_Msk   (0xFFUL << FSMC_PATT3_ATTHOLD3_Pos)
     
    #define FSMC_PATT3_ATTHOLD3   FSMC_PATT3_ATTHOLD3_Msk
     
    #define FSMC_PATT3_ATTHOLD3_0   (0x01UL << FSMC_PATT3_ATTHOLD3_Pos)
     
    #define FSMC_PATT3_ATTHOLD3_1   (0x02UL << FSMC_PATT3_ATTHOLD3_Pos)
     
    #define FSMC_PATT3_ATTHOLD3_2   (0x04UL << FSMC_PATT3_ATTHOLD3_Pos)
     
    #define FSMC_PATT3_ATTHOLD3_3   (0x08UL << FSMC_PATT3_ATTHOLD3_Pos)
     
    #define FSMC_PATT3_ATTHOLD3_4   (0x10UL << FSMC_PATT3_ATTHOLD3_Pos)
     
    #define FSMC_PATT3_ATTHOLD3_5   (0x20UL << FSMC_PATT3_ATTHOLD3_Pos)
     
    #define FSMC_PATT3_ATTHOLD3_6   (0x40UL << FSMC_PATT3_ATTHOLD3_Pos)
     
    #define FSMC_PATT3_ATTHOLD3_7   (0x80UL << FSMC_PATT3_ATTHOLD3_Pos)
     
    #define FSMC_PATT3_ATTHIZ3_Pos   (24U)
     
    #define FSMC_PATT3_ATTHIZ3_Msk   (0xFFUL << FSMC_PATT3_ATTHIZ3_Pos)
     
    #define FSMC_PATT3_ATTHIZ3   FSMC_PATT3_ATTHIZ3_Msk
     
    #define FSMC_PATT3_ATTHIZ3_0   (0x01UL << FSMC_PATT3_ATTHIZ3_Pos)
     
    #define FSMC_PATT3_ATTHIZ3_1   (0x02UL << FSMC_PATT3_ATTHIZ3_Pos)
     
    #define FSMC_PATT3_ATTHIZ3_2   (0x04UL << FSMC_PATT3_ATTHIZ3_Pos)
     
    #define FSMC_PATT3_ATTHIZ3_3   (0x08UL << FSMC_PATT3_ATTHIZ3_Pos)
     
    #define FSMC_PATT3_ATTHIZ3_4   (0x10UL << FSMC_PATT3_ATTHIZ3_Pos)
     
    #define FSMC_PATT3_ATTHIZ3_5   (0x20UL << FSMC_PATT3_ATTHIZ3_Pos)
     
    #define FSMC_PATT3_ATTHIZ3_6   (0x40UL << FSMC_PATT3_ATTHIZ3_Pos)
     
    #define FSMC_PATT3_ATTHIZ3_7   (0x80UL << FSMC_PATT3_ATTHIZ3_Pos)
     
    #define FSMC_PATT4_ATTSET4_Pos   (0U)
     
    #define FSMC_PATT4_ATTSET4_Msk   (0xFFUL << FSMC_PATT4_ATTSET4_Pos)
     
    #define FSMC_PATT4_ATTSET4   FSMC_PATT4_ATTSET4_Msk
     
    #define FSMC_PATT4_ATTSET4_0   (0x01UL << FSMC_PATT4_ATTSET4_Pos)
     
    #define FSMC_PATT4_ATTSET4_1   (0x02UL << FSMC_PATT4_ATTSET4_Pos)
     
    #define FSMC_PATT4_ATTSET4_2   (0x04UL << FSMC_PATT4_ATTSET4_Pos)
     
    #define FSMC_PATT4_ATTSET4_3   (0x08UL << FSMC_PATT4_ATTSET4_Pos)
     
    #define FSMC_PATT4_ATTSET4_4   (0x10UL << FSMC_PATT4_ATTSET4_Pos)
     
    #define FSMC_PATT4_ATTSET4_5   (0x20UL << FSMC_PATT4_ATTSET4_Pos)
     
    #define FSMC_PATT4_ATTSET4_6   (0x40UL << FSMC_PATT4_ATTSET4_Pos)
     
    #define FSMC_PATT4_ATTSET4_7   (0x80UL << FSMC_PATT4_ATTSET4_Pos)
     
    #define FSMC_PATT4_ATTWAIT4_Pos   (8U)
     
    #define FSMC_PATT4_ATTWAIT4_Msk   (0xFFUL << FSMC_PATT4_ATTWAIT4_Pos)
     
    #define FSMC_PATT4_ATTWAIT4   FSMC_PATT4_ATTWAIT4_Msk
     
    #define FSMC_PATT4_ATTWAIT4_0   (0x01UL << FSMC_PATT4_ATTWAIT4_Pos)
     
    #define FSMC_PATT4_ATTWAIT4_1   (0x02UL << FSMC_PATT4_ATTWAIT4_Pos)
     
    #define FSMC_PATT4_ATTWAIT4_2   (0x04UL << FSMC_PATT4_ATTWAIT4_Pos)
     
    #define FSMC_PATT4_ATTWAIT4_3   (0x08UL << FSMC_PATT4_ATTWAIT4_Pos)
     
    #define FSMC_PATT4_ATTWAIT4_4   (0x10UL << FSMC_PATT4_ATTWAIT4_Pos)
     
    #define FSMC_PATT4_ATTWAIT4_5   (0x20UL << FSMC_PATT4_ATTWAIT4_Pos)
     
    #define FSMC_PATT4_ATTWAIT4_6   (0x40UL << FSMC_PATT4_ATTWAIT4_Pos)
     
    #define FSMC_PATT4_ATTWAIT4_7   (0x80UL << FSMC_PATT4_ATTWAIT4_Pos)
     
    #define FSMC_PATT4_ATTHOLD4_Pos   (16U)
     
    #define FSMC_PATT4_ATTHOLD4_Msk   (0xFFUL << FSMC_PATT4_ATTHOLD4_Pos)
     
    #define FSMC_PATT4_ATTHOLD4   FSMC_PATT4_ATTHOLD4_Msk
     
    #define FSMC_PATT4_ATTHOLD4_0   (0x01UL << FSMC_PATT4_ATTHOLD4_Pos)
     
    #define FSMC_PATT4_ATTHOLD4_1   (0x02UL << FSMC_PATT4_ATTHOLD4_Pos)
     
    #define FSMC_PATT4_ATTHOLD4_2   (0x04UL << FSMC_PATT4_ATTHOLD4_Pos)
     
    #define FSMC_PATT4_ATTHOLD4_3   (0x08UL << FSMC_PATT4_ATTHOLD4_Pos)
     
    #define FSMC_PATT4_ATTHOLD4_4   (0x10UL << FSMC_PATT4_ATTHOLD4_Pos)
     
    #define FSMC_PATT4_ATTHOLD4_5   (0x20UL << FSMC_PATT4_ATTHOLD4_Pos)
     
    #define FSMC_PATT4_ATTHOLD4_6   (0x40UL << FSMC_PATT4_ATTHOLD4_Pos)
     
    #define FSMC_PATT4_ATTHOLD4_7   (0x80UL << FSMC_PATT4_ATTHOLD4_Pos)
     
    #define FSMC_PATT4_ATTHIZ4_Pos   (24U)
     
    #define FSMC_PATT4_ATTHIZ4_Msk   (0xFFUL << FSMC_PATT4_ATTHIZ4_Pos)
     
    #define FSMC_PATT4_ATTHIZ4   FSMC_PATT4_ATTHIZ4_Msk
     
    #define FSMC_PATT4_ATTHIZ4_0   (0x01UL << FSMC_PATT4_ATTHIZ4_Pos)
     
    #define FSMC_PATT4_ATTHIZ4_1   (0x02UL << FSMC_PATT4_ATTHIZ4_Pos)
     
    #define FSMC_PATT4_ATTHIZ4_2   (0x04UL << FSMC_PATT4_ATTHIZ4_Pos)
     
    #define FSMC_PATT4_ATTHIZ4_3   (0x08UL << FSMC_PATT4_ATTHIZ4_Pos)
     
    #define FSMC_PATT4_ATTHIZ4_4   (0x10UL << FSMC_PATT4_ATTHIZ4_Pos)
     
    #define FSMC_PATT4_ATTHIZ4_5   (0x20UL << FSMC_PATT4_ATTHIZ4_Pos)
     
    #define FSMC_PATT4_ATTHIZ4_6   (0x40UL << FSMC_PATT4_ATTHIZ4_Pos)
     
    #define FSMC_PATT4_ATTHIZ4_7   (0x80UL << FSMC_PATT4_ATTHIZ4_Pos)
     
    #define FSMC_PIO4_IOSET4_Pos   (0U)
     
    #define FSMC_PIO4_IOSET4_Msk   (0xFFUL << FSMC_PIO4_IOSET4_Pos)
     
    #define FSMC_PIO4_IOSET4   FSMC_PIO4_IOSET4_Msk
     
    #define FSMC_PIO4_IOSET4_0   (0x01UL << FSMC_PIO4_IOSET4_Pos)
     
    #define FSMC_PIO4_IOSET4_1   (0x02UL << FSMC_PIO4_IOSET4_Pos)
     
    #define FSMC_PIO4_IOSET4_2   (0x04UL << FSMC_PIO4_IOSET4_Pos)
     
    #define FSMC_PIO4_IOSET4_3   (0x08UL << FSMC_PIO4_IOSET4_Pos)
     
    #define FSMC_PIO4_IOSET4_4   (0x10UL << FSMC_PIO4_IOSET4_Pos)
     
    #define FSMC_PIO4_IOSET4_5   (0x20UL << FSMC_PIO4_IOSET4_Pos)
     
    #define FSMC_PIO4_IOSET4_6   (0x40UL << FSMC_PIO4_IOSET4_Pos)
     
    #define FSMC_PIO4_IOSET4_7   (0x80UL << FSMC_PIO4_IOSET4_Pos)
     
    #define FSMC_PIO4_IOWAIT4_Pos   (8U)
     
    #define FSMC_PIO4_IOWAIT4_Msk   (0xFFUL << FSMC_PIO4_IOWAIT4_Pos)
     
    #define FSMC_PIO4_IOWAIT4   FSMC_PIO4_IOWAIT4_Msk
     
    #define FSMC_PIO4_IOWAIT4_0   (0x01UL << FSMC_PIO4_IOWAIT4_Pos)
     
    #define FSMC_PIO4_IOWAIT4_1   (0x02UL << FSMC_PIO4_IOWAIT4_Pos)
     
    #define FSMC_PIO4_IOWAIT4_2   (0x04UL << FSMC_PIO4_IOWAIT4_Pos)
     
    #define FSMC_PIO4_IOWAIT4_3   (0x08UL << FSMC_PIO4_IOWAIT4_Pos)
     
    #define FSMC_PIO4_IOWAIT4_4   (0x10UL << FSMC_PIO4_IOWAIT4_Pos)
     
    #define FSMC_PIO4_IOWAIT4_5   (0x20UL << FSMC_PIO4_IOWAIT4_Pos)
     
    #define FSMC_PIO4_IOWAIT4_6   (0x40UL << FSMC_PIO4_IOWAIT4_Pos)
     
    #define FSMC_PIO4_IOWAIT4_7   (0x80UL << FSMC_PIO4_IOWAIT4_Pos)
     
    #define FSMC_PIO4_IOHOLD4_Pos   (16U)
     
    #define FSMC_PIO4_IOHOLD4_Msk   (0xFFUL << FSMC_PIO4_IOHOLD4_Pos)
     
    #define FSMC_PIO4_IOHOLD4   FSMC_PIO4_IOHOLD4_Msk
     
    #define FSMC_PIO4_IOHOLD4_0   (0x01UL << FSMC_PIO4_IOHOLD4_Pos)
     
    #define FSMC_PIO4_IOHOLD4_1   (0x02UL << FSMC_PIO4_IOHOLD4_Pos)
     
    #define FSMC_PIO4_IOHOLD4_2   (0x04UL << FSMC_PIO4_IOHOLD4_Pos)
     
    #define FSMC_PIO4_IOHOLD4_3   (0x08UL << FSMC_PIO4_IOHOLD4_Pos)
     
    #define FSMC_PIO4_IOHOLD4_4   (0x10UL << FSMC_PIO4_IOHOLD4_Pos)
     
    #define FSMC_PIO4_IOHOLD4_5   (0x20UL << FSMC_PIO4_IOHOLD4_Pos)
     
    #define FSMC_PIO4_IOHOLD4_6   (0x40UL << FSMC_PIO4_IOHOLD4_Pos)
     
    #define FSMC_PIO4_IOHOLD4_7   (0x80UL << FSMC_PIO4_IOHOLD4_Pos)
     
    #define FSMC_PIO4_IOHIZ4_Pos   (24U)
     
    #define FSMC_PIO4_IOHIZ4_Msk   (0xFFUL << FSMC_PIO4_IOHIZ4_Pos)
     
    #define FSMC_PIO4_IOHIZ4   FSMC_PIO4_IOHIZ4_Msk
     
    #define FSMC_PIO4_IOHIZ4_0   (0x01UL << FSMC_PIO4_IOHIZ4_Pos)
     
    #define FSMC_PIO4_IOHIZ4_1   (0x02UL << FSMC_PIO4_IOHIZ4_Pos)
     
    #define FSMC_PIO4_IOHIZ4_2   (0x04UL << FSMC_PIO4_IOHIZ4_Pos)
     
    #define FSMC_PIO4_IOHIZ4_3   (0x08UL << FSMC_PIO4_IOHIZ4_Pos)
     
    #define FSMC_PIO4_IOHIZ4_4   (0x10UL << FSMC_PIO4_IOHIZ4_Pos)
     
    #define FSMC_PIO4_IOHIZ4_5   (0x20UL << FSMC_PIO4_IOHIZ4_Pos)
     
    #define FSMC_PIO4_IOHIZ4_6   (0x40UL << FSMC_PIO4_IOHIZ4_Pos)
     
    #define FSMC_PIO4_IOHIZ4_7   (0x80UL << FSMC_PIO4_IOHIZ4_Pos)
     
    #define FSMC_ECCR2_ECC2_Pos   (0U)
     
    #define FSMC_ECCR2_ECC2_Msk   (0xFFFFFFFFUL << FSMC_ECCR2_ECC2_Pos)
     
    #define FSMC_ECCR2_ECC2   FSMC_ECCR2_ECC2_Msk
     
    #define FSMC_ECCR3_ECC3_Pos   (0U)
     
    #define FSMC_ECCR3_ECC3_Msk   (0xFFFFFFFFUL << FSMC_ECCR3_ECC3_Pos)
     
    #define FSMC_ECCR3_ECC3   FSMC_ECCR3_ECC3_Msk
     
    #define GPIO_MODER_MODER0_Pos   (0U)
     
    #define GPIO_MODER_MODER0_Msk   (0x3UL << GPIO_MODER_MODER0_Pos)
     
    #define GPIO_MODER_MODER0   GPIO_MODER_MODER0_Msk
     
    #define GPIO_MODER_MODER0_0   (0x1UL << GPIO_MODER_MODER0_Pos)
     
    #define GPIO_MODER_MODER0_1   (0x2UL << GPIO_MODER_MODER0_Pos)
     
    #define GPIO_MODER_MODER1_Pos   (2U)
     
    #define GPIO_MODER_MODER1_Msk   (0x3UL << GPIO_MODER_MODER1_Pos)
     
    #define GPIO_MODER_MODER1   GPIO_MODER_MODER1_Msk
     
    #define GPIO_MODER_MODER1_0   (0x1UL << GPIO_MODER_MODER1_Pos)
     
    #define GPIO_MODER_MODER1_1   (0x2UL << GPIO_MODER_MODER1_Pos)
     
    #define GPIO_MODER_MODER2_Pos   (4U)
     
    #define GPIO_MODER_MODER2_Msk   (0x3UL << GPIO_MODER_MODER2_Pos)
     
    #define GPIO_MODER_MODER2   GPIO_MODER_MODER2_Msk
     
    #define GPIO_MODER_MODER2_0   (0x1UL << GPIO_MODER_MODER2_Pos)
     
    #define GPIO_MODER_MODER2_1   (0x2UL << GPIO_MODER_MODER2_Pos)
     
    #define GPIO_MODER_MODER3_Pos   (6U)
     
    #define GPIO_MODER_MODER3_Msk   (0x3UL << GPIO_MODER_MODER3_Pos)
     
    #define GPIO_MODER_MODER3   GPIO_MODER_MODER3_Msk
     
    #define GPIO_MODER_MODER3_0   (0x1UL << GPIO_MODER_MODER3_Pos)
     
    #define GPIO_MODER_MODER3_1   (0x2UL << GPIO_MODER_MODER3_Pos)
     
    #define GPIO_MODER_MODER4_Pos   (8U)
     
    #define GPIO_MODER_MODER4_Msk   (0x3UL << GPIO_MODER_MODER4_Pos)
     
    #define GPIO_MODER_MODER4   GPIO_MODER_MODER4_Msk
     
    #define GPIO_MODER_MODER4_0   (0x1UL << GPIO_MODER_MODER4_Pos)
     
    #define GPIO_MODER_MODER4_1   (0x2UL << GPIO_MODER_MODER4_Pos)
     
    #define GPIO_MODER_MODER5_Pos   (10U)
     
    #define GPIO_MODER_MODER5_Msk   (0x3UL << GPIO_MODER_MODER5_Pos)
     
    #define GPIO_MODER_MODER5   GPIO_MODER_MODER5_Msk
     
    #define GPIO_MODER_MODER5_0   (0x1UL << GPIO_MODER_MODER5_Pos)
     
    #define GPIO_MODER_MODER5_1   (0x2UL << GPIO_MODER_MODER5_Pos)
     
    #define GPIO_MODER_MODER6_Pos   (12U)
     
    #define GPIO_MODER_MODER6_Msk   (0x3UL << GPIO_MODER_MODER6_Pos)
     
    #define GPIO_MODER_MODER6   GPIO_MODER_MODER6_Msk
     
    #define GPIO_MODER_MODER6_0   (0x1UL << GPIO_MODER_MODER6_Pos)
     
    #define GPIO_MODER_MODER6_1   (0x2UL << GPIO_MODER_MODER6_Pos)
     
    #define GPIO_MODER_MODER7_Pos   (14U)
     
    #define GPIO_MODER_MODER7_Msk   (0x3UL << GPIO_MODER_MODER7_Pos)
     
    #define GPIO_MODER_MODER7   GPIO_MODER_MODER7_Msk
     
    #define GPIO_MODER_MODER7_0   (0x1UL << GPIO_MODER_MODER7_Pos)
     
    #define GPIO_MODER_MODER7_1   (0x2UL << GPIO_MODER_MODER7_Pos)
     
    #define GPIO_MODER_MODER8_Pos   (16U)
     
    #define GPIO_MODER_MODER8_Msk   (0x3UL << GPIO_MODER_MODER8_Pos)
     
    #define GPIO_MODER_MODER8   GPIO_MODER_MODER8_Msk
     
    #define GPIO_MODER_MODER8_0   (0x1UL << GPIO_MODER_MODER8_Pos)
     
    #define GPIO_MODER_MODER8_1   (0x2UL << GPIO_MODER_MODER8_Pos)
     
    #define GPIO_MODER_MODER9_Pos   (18U)
     
    #define GPIO_MODER_MODER9_Msk   (0x3UL << GPIO_MODER_MODER9_Pos)
     
    #define GPIO_MODER_MODER9   GPIO_MODER_MODER9_Msk
     
    #define GPIO_MODER_MODER9_0   (0x1UL << GPIO_MODER_MODER9_Pos)
     
    #define GPIO_MODER_MODER9_1   (0x2UL << GPIO_MODER_MODER9_Pos)
     
    #define GPIO_MODER_MODER10_Pos   (20U)
     
    #define GPIO_MODER_MODER10_Msk   (0x3UL << GPIO_MODER_MODER10_Pos)
     
    #define GPIO_MODER_MODER10   GPIO_MODER_MODER10_Msk
     
    #define GPIO_MODER_MODER10_0   (0x1UL << GPIO_MODER_MODER10_Pos)
     
    #define GPIO_MODER_MODER10_1   (0x2UL << GPIO_MODER_MODER10_Pos)
     
    #define GPIO_MODER_MODER11_Pos   (22U)
     
    #define GPIO_MODER_MODER11_Msk   (0x3UL << GPIO_MODER_MODER11_Pos)
     
    #define GPIO_MODER_MODER11   GPIO_MODER_MODER11_Msk
     
    #define GPIO_MODER_MODER11_0   (0x1UL << GPIO_MODER_MODER11_Pos)
     
    #define GPIO_MODER_MODER11_1   (0x2UL << GPIO_MODER_MODER11_Pos)
     
    #define GPIO_MODER_MODER12_Pos   (24U)
     
    #define GPIO_MODER_MODER12_Msk   (0x3UL << GPIO_MODER_MODER12_Pos)
     
    #define GPIO_MODER_MODER12   GPIO_MODER_MODER12_Msk
     
    #define GPIO_MODER_MODER12_0   (0x1UL << GPIO_MODER_MODER12_Pos)
     
    #define GPIO_MODER_MODER12_1   (0x2UL << GPIO_MODER_MODER12_Pos)
     
    #define GPIO_MODER_MODER13_Pos   (26U)
     
    #define GPIO_MODER_MODER13_Msk   (0x3UL << GPIO_MODER_MODER13_Pos)
     
    #define GPIO_MODER_MODER13   GPIO_MODER_MODER13_Msk
     
    #define GPIO_MODER_MODER13_0   (0x1UL << GPIO_MODER_MODER13_Pos)
     
    #define GPIO_MODER_MODER13_1   (0x2UL << GPIO_MODER_MODER13_Pos)
     
    #define GPIO_MODER_MODER14_Pos   (28U)
     
    #define GPIO_MODER_MODER14_Msk   (0x3UL << GPIO_MODER_MODER14_Pos)
     
    #define GPIO_MODER_MODER14   GPIO_MODER_MODER14_Msk
     
    #define GPIO_MODER_MODER14_0   (0x1UL << GPIO_MODER_MODER14_Pos)
     
    #define GPIO_MODER_MODER14_1   (0x2UL << GPIO_MODER_MODER14_Pos)
     
    #define GPIO_MODER_MODER15_Pos   (30U)
     
    #define GPIO_MODER_MODER15_Msk   (0x3UL << GPIO_MODER_MODER15_Pos)
     
    #define GPIO_MODER_MODER15   GPIO_MODER_MODER15_Msk
     
    #define GPIO_MODER_MODER15_0   (0x1UL << GPIO_MODER_MODER15_Pos)
     
    #define GPIO_MODER_MODER15_1   (0x2UL << GPIO_MODER_MODER15_Pos)
     
    #define GPIO_MODER_MODE0_Pos   GPIO_MODER_MODER0_Pos
     
    #define GPIO_MODER_MODE0_Msk   GPIO_MODER_MODER0_Msk
     
    #define GPIO_MODER_MODE0   GPIO_MODER_MODER0
     
    #define GPIO_MODER_MODE0_0   GPIO_MODER_MODER0_0
     
    #define GPIO_MODER_MODE0_1   GPIO_MODER_MODER0_1
     
    #define GPIO_MODER_MODE1_Pos   GPIO_MODER_MODER1_Pos
     
    #define GPIO_MODER_MODE1_Msk   GPIO_MODER_MODER1_Msk
     
    #define GPIO_MODER_MODE1   GPIO_MODER_MODER1
     
    #define GPIO_MODER_MODE1_0   GPIO_MODER_MODER1_0
     
    #define GPIO_MODER_MODE1_1   GPIO_MODER_MODER1_1
     
    #define GPIO_MODER_MODE2_Pos   GPIO_MODER_MODER2_Pos
     
    #define GPIO_MODER_MODE2_Msk   GPIO_MODER_MODER2_Msk
     
    #define GPIO_MODER_MODE2   GPIO_MODER_MODER2
     
    #define GPIO_MODER_MODE2_0   GPIO_MODER_MODER2_0
     
    #define GPIO_MODER_MODE2_1   GPIO_MODER_MODER2_1
     
    #define GPIO_MODER_MODE3_Pos   GPIO_MODER_MODER3_Pos
     
    #define GPIO_MODER_MODE3_Msk   GPIO_MODER_MODER3_Msk
     
    #define GPIO_MODER_MODE3   GPIO_MODER_MODER3
     
    #define GPIO_MODER_MODE3_0   GPIO_MODER_MODER3_0
     
    #define GPIO_MODER_MODE3_1   GPIO_MODER_MODER3_1
     
    #define GPIO_MODER_MODE4_Pos   GPIO_MODER_MODER4_Pos
     
    #define GPIO_MODER_MODE4_Msk   GPIO_MODER_MODER4_Msk
     
    #define GPIO_MODER_MODE4   GPIO_MODER_MODER4
     
    #define GPIO_MODER_MODE4_0   GPIO_MODER_MODER4_0
     
    #define GPIO_MODER_MODE4_1   GPIO_MODER_MODER4_1
     
    #define GPIO_MODER_MODE5_Pos   GPIO_MODER_MODER5_Pos
     
    #define GPIO_MODER_MODE5_Msk   GPIO_MODER_MODER5_Msk
     
    #define GPIO_MODER_MODE5   GPIO_MODER_MODER5
     
    #define GPIO_MODER_MODE5_0   GPIO_MODER_MODER5_0
     
    #define GPIO_MODER_MODE5_1   GPIO_MODER_MODER5_1
     
    #define GPIO_MODER_MODE6_Pos   GPIO_MODER_MODER6_Pos
     
    #define GPIO_MODER_MODE6_Msk   GPIO_MODER_MODER6_Msk
     
    #define GPIO_MODER_MODE6   GPIO_MODER_MODER6
     
    #define GPIO_MODER_MODE6_0   GPIO_MODER_MODER6_0
     
    #define GPIO_MODER_MODE6_1   GPIO_MODER_MODER6_1
     
    #define GPIO_MODER_MODE7_Pos   GPIO_MODER_MODER7_Pos
     
    #define GPIO_MODER_MODE7_Msk   GPIO_MODER_MODER7_Msk
     
    #define GPIO_MODER_MODE7   GPIO_MODER_MODER7
     
    #define GPIO_MODER_MODE7_0   GPIO_MODER_MODER7_0
     
    #define GPIO_MODER_MODE7_1   GPIO_MODER_MODER7_1
     
    #define GPIO_MODER_MODE8_Pos   GPIO_MODER_MODER8_Pos
     
    #define GPIO_MODER_MODE8_Msk   GPIO_MODER_MODER8_Msk
     
    #define GPIO_MODER_MODE8   GPIO_MODER_MODER8
     
    #define GPIO_MODER_MODE8_0   GPIO_MODER_MODER8_0
     
    #define GPIO_MODER_MODE8_1   GPIO_MODER_MODER8_1
     
    #define GPIO_MODER_MODE9_Pos   GPIO_MODER_MODER9_Pos
     
    #define GPIO_MODER_MODE9_Msk   GPIO_MODER_MODER9_Msk
     
    #define GPIO_MODER_MODE9   GPIO_MODER_MODER9
     
    #define GPIO_MODER_MODE9_0   GPIO_MODER_MODER9_0
     
    #define GPIO_MODER_MODE9_1   GPIO_MODER_MODER9_1
     
    #define GPIO_MODER_MODE10_Pos   GPIO_MODER_MODER10_Pos
     
    #define GPIO_MODER_MODE10_Msk   GPIO_MODER_MODER10_Msk
     
    #define GPIO_MODER_MODE10   GPIO_MODER_MODER10
     
    #define GPIO_MODER_MODE10_0   GPIO_MODER_MODER10_0
     
    #define GPIO_MODER_MODE10_1   GPIO_MODER_MODER10_1
     
    #define GPIO_MODER_MODE11_Pos   GPIO_MODER_MODER11_Pos
     
    #define GPIO_MODER_MODE11_Msk   GPIO_MODER_MODER11_Msk
     
    #define GPIO_MODER_MODE11   GPIO_MODER_MODER11
     
    #define GPIO_MODER_MODE11_0   GPIO_MODER_MODER11_0
     
    #define GPIO_MODER_MODE11_1   GPIO_MODER_MODER11_1
     
    #define GPIO_MODER_MODE12_Pos   GPIO_MODER_MODER12_Pos
     
    #define GPIO_MODER_MODE12_Msk   GPIO_MODER_MODER12_Msk
     
    #define GPIO_MODER_MODE12   GPIO_MODER_MODER12
     
    #define GPIO_MODER_MODE12_0   GPIO_MODER_MODER12_0
     
    #define GPIO_MODER_MODE12_1   GPIO_MODER_MODER12_1
     
    #define GPIO_MODER_MODE13_Pos   GPIO_MODER_MODER13_Pos
     
    #define GPIO_MODER_MODE13_Msk   GPIO_MODER_MODER13_Msk
     
    #define GPIO_MODER_MODE13   GPIO_MODER_MODER13
     
    #define GPIO_MODER_MODE13_0   GPIO_MODER_MODER13_0
     
    #define GPIO_MODER_MODE13_1   GPIO_MODER_MODER13_1
     
    #define GPIO_MODER_MODE14_Pos   GPIO_MODER_MODER14_Pos
     
    #define GPIO_MODER_MODE14_Msk   GPIO_MODER_MODER14_Msk
     
    #define GPIO_MODER_MODE14   GPIO_MODER_MODER14
     
    #define GPIO_MODER_MODE14_0   GPIO_MODER_MODER14_0
     
    #define GPIO_MODER_MODE14_1   GPIO_MODER_MODER14_1
     
    #define GPIO_MODER_MODE15_Pos   GPIO_MODER_MODER15_Pos
     
    #define GPIO_MODER_MODE15_Msk   GPIO_MODER_MODER15_Msk
     
    #define GPIO_MODER_MODE15   GPIO_MODER_MODER15
     
    #define GPIO_MODER_MODE15_0   GPIO_MODER_MODER15_0
     
    #define GPIO_MODER_MODE15_1   GPIO_MODER_MODER15_1
     
    #define GPIO_OTYPER_OT0_Pos   (0U)
     
    #define GPIO_OTYPER_OT0_Msk   (0x1UL << GPIO_OTYPER_OT0_Pos)
     
    #define GPIO_OTYPER_OT0   GPIO_OTYPER_OT0_Msk
     
    #define GPIO_OTYPER_OT1_Pos   (1U)
     
    #define GPIO_OTYPER_OT1_Msk   (0x1UL << GPIO_OTYPER_OT1_Pos)
     
    #define GPIO_OTYPER_OT1   GPIO_OTYPER_OT1_Msk
     
    #define GPIO_OTYPER_OT2_Pos   (2U)
     
    #define GPIO_OTYPER_OT2_Msk   (0x1UL << GPIO_OTYPER_OT2_Pos)
     
    #define GPIO_OTYPER_OT2   GPIO_OTYPER_OT2_Msk
     
    #define GPIO_OTYPER_OT3_Pos   (3U)
     
    #define GPIO_OTYPER_OT3_Msk   (0x1UL << GPIO_OTYPER_OT3_Pos)
     
    #define GPIO_OTYPER_OT3   GPIO_OTYPER_OT3_Msk
     
    #define GPIO_OTYPER_OT4_Pos   (4U)
     
    #define GPIO_OTYPER_OT4_Msk   (0x1UL << GPIO_OTYPER_OT4_Pos)
     
    #define GPIO_OTYPER_OT4   GPIO_OTYPER_OT4_Msk
     
    #define GPIO_OTYPER_OT5_Pos   (5U)
     
    #define GPIO_OTYPER_OT5_Msk   (0x1UL << GPIO_OTYPER_OT5_Pos)
     
    #define GPIO_OTYPER_OT5   GPIO_OTYPER_OT5_Msk
     
    #define GPIO_OTYPER_OT6_Pos   (6U)
     
    #define GPIO_OTYPER_OT6_Msk   (0x1UL << GPIO_OTYPER_OT6_Pos)
     
    #define GPIO_OTYPER_OT6   GPIO_OTYPER_OT6_Msk
     
    #define GPIO_OTYPER_OT7_Pos   (7U)
     
    #define GPIO_OTYPER_OT7_Msk   (0x1UL << GPIO_OTYPER_OT7_Pos)
     
    #define GPIO_OTYPER_OT7   GPIO_OTYPER_OT7_Msk
     
    #define GPIO_OTYPER_OT8_Pos   (8U)
     
    #define GPIO_OTYPER_OT8_Msk   (0x1UL << GPIO_OTYPER_OT8_Pos)
     
    #define GPIO_OTYPER_OT8   GPIO_OTYPER_OT8_Msk
     
    #define GPIO_OTYPER_OT9_Pos   (9U)
     
    #define GPIO_OTYPER_OT9_Msk   (0x1UL << GPIO_OTYPER_OT9_Pos)
     
    #define GPIO_OTYPER_OT9   GPIO_OTYPER_OT9_Msk
     
    #define GPIO_OTYPER_OT10_Pos   (10U)
     
    #define GPIO_OTYPER_OT10_Msk   (0x1UL << GPIO_OTYPER_OT10_Pos)
     
    #define GPIO_OTYPER_OT10   GPIO_OTYPER_OT10_Msk
     
    #define GPIO_OTYPER_OT11_Pos   (11U)
     
    #define GPIO_OTYPER_OT11_Msk   (0x1UL << GPIO_OTYPER_OT11_Pos)
     
    #define GPIO_OTYPER_OT11   GPIO_OTYPER_OT11_Msk
     
    #define GPIO_OTYPER_OT12_Pos   (12U)
     
    #define GPIO_OTYPER_OT12_Msk   (0x1UL << GPIO_OTYPER_OT12_Pos)
     
    #define GPIO_OTYPER_OT12   GPIO_OTYPER_OT12_Msk
     
    #define GPIO_OTYPER_OT13_Pos   (13U)
     
    #define GPIO_OTYPER_OT13_Msk   (0x1UL << GPIO_OTYPER_OT13_Pos)
     
    #define GPIO_OTYPER_OT13   GPIO_OTYPER_OT13_Msk
     
    #define GPIO_OTYPER_OT14_Pos   (14U)
     
    #define GPIO_OTYPER_OT14_Msk   (0x1UL << GPIO_OTYPER_OT14_Pos)
     
    #define GPIO_OTYPER_OT14   GPIO_OTYPER_OT14_Msk
     
    #define GPIO_OTYPER_OT15_Pos   (15U)
     
    #define GPIO_OTYPER_OT15_Msk   (0x1UL << GPIO_OTYPER_OT15_Pos)
     
    #define GPIO_OTYPER_OT15   GPIO_OTYPER_OT15_Msk
     
    #define GPIO_OTYPER_OT_0   GPIO_OTYPER_OT0
     
    #define GPIO_OTYPER_OT_1   GPIO_OTYPER_OT1
     
    #define GPIO_OTYPER_OT_2   GPIO_OTYPER_OT2
     
    #define GPIO_OTYPER_OT_3   GPIO_OTYPER_OT3
     
    #define GPIO_OTYPER_OT_4   GPIO_OTYPER_OT4
     
    #define GPIO_OTYPER_OT_5   GPIO_OTYPER_OT5
     
    #define GPIO_OTYPER_OT_6   GPIO_OTYPER_OT6
     
    #define GPIO_OTYPER_OT_7   GPIO_OTYPER_OT7
     
    #define GPIO_OTYPER_OT_8   GPIO_OTYPER_OT8
     
    #define GPIO_OTYPER_OT_9   GPIO_OTYPER_OT9
     
    #define GPIO_OTYPER_OT_10   GPIO_OTYPER_OT10
     
    #define GPIO_OTYPER_OT_11   GPIO_OTYPER_OT11
     
    #define GPIO_OTYPER_OT_12   GPIO_OTYPER_OT12
     
    #define GPIO_OTYPER_OT_13   GPIO_OTYPER_OT13
     
    #define GPIO_OTYPER_OT_14   GPIO_OTYPER_OT14
     
    #define GPIO_OTYPER_OT_15   GPIO_OTYPER_OT15
     
    #define GPIO_OSPEEDR_OSPEED0_Pos   (0U)
     
    #define GPIO_OSPEEDR_OSPEED0_Msk   (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos)
     
    #define GPIO_OSPEEDR_OSPEED0   GPIO_OSPEEDR_OSPEED0_Msk
     
    #define GPIO_OSPEEDR_OSPEED0_0   (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos)
     
    #define GPIO_OSPEEDR_OSPEED0_1   (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos)
     
    #define GPIO_OSPEEDR_OSPEED1_Pos   (2U)
     
    #define GPIO_OSPEEDR_OSPEED1_Msk   (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos)
     
    #define GPIO_OSPEEDR_OSPEED1   GPIO_OSPEEDR_OSPEED1_Msk
     
    #define GPIO_OSPEEDR_OSPEED1_0   (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos)
     
    #define GPIO_OSPEEDR_OSPEED1_1   (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos)
     
    #define GPIO_OSPEEDR_OSPEED2_Pos   (4U)
     
    #define GPIO_OSPEEDR_OSPEED2_Msk   (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos)
     
    #define GPIO_OSPEEDR_OSPEED2   GPIO_OSPEEDR_OSPEED2_Msk
     
    #define GPIO_OSPEEDR_OSPEED2_0   (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos)
     
    #define GPIO_OSPEEDR_OSPEED2_1   (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos)
     
    #define GPIO_OSPEEDR_OSPEED3_Pos   (6U)
     
    #define GPIO_OSPEEDR_OSPEED3_Msk   (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos)
     
    #define GPIO_OSPEEDR_OSPEED3   GPIO_OSPEEDR_OSPEED3_Msk
     
    #define GPIO_OSPEEDR_OSPEED3_0   (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos)
     
    #define GPIO_OSPEEDR_OSPEED3_1   (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos)
     
    #define GPIO_OSPEEDR_OSPEED4_Pos   (8U)
     
    #define GPIO_OSPEEDR_OSPEED4_Msk   (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos)
     
    #define GPIO_OSPEEDR_OSPEED4   GPIO_OSPEEDR_OSPEED4_Msk
     
    #define GPIO_OSPEEDR_OSPEED4_0   (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos)
     
    #define GPIO_OSPEEDR_OSPEED4_1   (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos)
     
    #define GPIO_OSPEEDR_OSPEED5_Pos   (10U)
     
    #define GPIO_OSPEEDR_OSPEED5_Msk   (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos)
     
    #define GPIO_OSPEEDR_OSPEED5   GPIO_OSPEEDR_OSPEED5_Msk
     
    #define GPIO_OSPEEDR_OSPEED5_0   (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos)
     
    #define GPIO_OSPEEDR_OSPEED5_1   (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos)
     
    #define GPIO_OSPEEDR_OSPEED6_Pos   (12U)
     
    #define GPIO_OSPEEDR_OSPEED6_Msk   (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos)
     
    #define GPIO_OSPEEDR_OSPEED6   GPIO_OSPEEDR_OSPEED6_Msk
     
    #define GPIO_OSPEEDR_OSPEED6_0   (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos)
     
    #define GPIO_OSPEEDR_OSPEED6_1   (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos)
     
    #define GPIO_OSPEEDR_OSPEED7_Pos   (14U)
     
    #define GPIO_OSPEEDR_OSPEED7_Msk   (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos)
     
    #define GPIO_OSPEEDR_OSPEED7   GPIO_OSPEEDR_OSPEED7_Msk
     
    #define GPIO_OSPEEDR_OSPEED7_0   (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos)
     
    #define GPIO_OSPEEDR_OSPEED7_1   (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos)
     
    #define GPIO_OSPEEDR_OSPEED8_Pos   (16U)
     
    #define GPIO_OSPEEDR_OSPEED8_Msk   (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos)
     
    #define GPIO_OSPEEDR_OSPEED8   GPIO_OSPEEDR_OSPEED8_Msk
     
    #define GPIO_OSPEEDR_OSPEED8_0   (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos)
     
    #define GPIO_OSPEEDR_OSPEED8_1   (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos)
     
    #define GPIO_OSPEEDR_OSPEED9_Pos   (18U)
     
    #define GPIO_OSPEEDR_OSPEED9_Msk   (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos)
     
    #define GPIO_OSPEEDR_OSPEED9   GPIO_OSPEEDR_OSPEED9_Msk
     
    #define GPIO_OSPEEDR_OSPEED9_0   (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos)
     
    #define GPIO_OSPEEDR_OSPEED9_1   (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos)
     
    #define GPIO_OSPEEDR_OSPEED10_Pos   (20U)
     
    #define GPIO_OSPEEDR_OSPEED10_Msk   (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos)
     
    #define GPIO_OSPEEDR_OSPEED10   GPIO_OSPEEDR_OSPEED10_Msk
     
    #define GPIO_OSPEEDR_OSPEED10_0   (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos)
     
    #define GPIO_OSPEEDR_OSPEED10_1   (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos)
     
    #define GPIO_OSPEEDR_OSPEED11_Pos   (22U)
     
    #define GPIO_OSPEEDR_OSPEED11_Msk   (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos)
     
    #define GPIO_OSPEEDR_OSPEED11   GPIO_OSPEEDR_OSPEED11_Msk
     
    #define GPIO_OSPEEDR_OSPEED11_0   (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos)
     
    #define GPIO_OSPEEDR_OSPEED11_1   (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos)
     
    #define GPIO_OSPEEDR_OSPEED12_Pos   (24U)
     
    #define GPIO_OSPEEDR_OSPEED12_Msk   (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos)
     
    #define GPIO_OSPEEDR_OSPEED12   GPIO_OSPEEDR_OSPEED12_Msk
     
    #define GPIO_OSPEEDR_OSPEED12_0   (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos)
     
    #define GPIO_OSPEEDR_OSPEED12_1   (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos)
     
    #define GPIO_OSPEEDR_OSPEED13_Pos   (26U)
     
    #define GPIO_OSPEEDR_OSPEED13_Msk   (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos)
     
    #define GPIO_OSPEEDR_OSPEED13   GPIO_OSPEEDR_OSPEED13_Msk
     
    #define GPIO_OSPEEDR_OSPEED13_0   (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos)
     
    #define GPIO_OSPEEDR_OSPEED13_1   (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos)
     
    #define GPIO_OSPEEDR_OSPEED14_Pos   (28U)
     
    #define GPIO_OSPEEDR_OSPEED14_Msk   (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos)
     
    #define GPIO_OSPEEDR_OSPEED14   GPIO_OSPEEDR_OSPEED14_Msk
     
    #define GPIO_OSPEEDR_OSPEED14_0   (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos)
     
    #define GPIO_OSPEEDR_OSPEED14_1   (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos)
     
    #define GPIO_OSPEEDR_OSPEED15_Pos   (30U)
     
    #define GPIO_OSPEEDR_OSPEED15_Msk   (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos)
     
    #define GPIO_OSPEEDR_OSPEED15   GPIO_OSPEEDR_OSPEED15_Msk
     
    #define GPIO_OSPEEDR_OSPEED15_0   (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos)
     
    #define GPIO_OSPEEDR_OSPEED15_1   (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos)
     
    #define GPIO_OSPEEDER_OSPEEDR0   GPIO_OSPEEDR_OSPEED0
     
    #define GPIO_OSPEEDER_OSPEEDR0_0   GPIO_OSPEEDR_OSPEED0_0
     
    #define GPIO_OSPEEDER_OSPEEDR0_1   GPIO_OSPEEDR_OSPEED0_1
     
    #define GPIO_OSPEEDER_OSPEEDR1   GPIO_OSPEEDR_OSPEED1
     
    #define GPIO_OSPEEDER_OSPEEDR1_0   GPIO_OSPEEDR_OSPEED1_0
     
    #define GPIO_OSPEEDER_OSPEEDR1_1   GPIO_OSPEEDR_OSPEED1_1
     
    #define GPIO_OSPEEDER_OSPEEDR2   GPIO_OSPEEDR_OSPEED2
     
    #define GPIO_OSPEEDER_OSPEEDR2_0   GPIO_OSPEEDR_OSPEED2_0
     
    #define GPIO_OSPEEDER_OSPEEDR2_1   GPIO_OSPEEDR_OSPEED2_1
     
    #define GPIO_OSPEEDER_OSPEEDR3   GPIO_OSPEEDR_OSPEED3
     
    #define GPIO_OSPEEDER_OSPEEDR3_0   GPIO_OSPEEDR_OSPEED3_0
     
    #define GPIO_OSPEEDER_OSPEEDR3_1   GPIO_OSPEEDR_OSPEED3_1
     
    #define GPIO_OSPEEDER_OSPEEDR4   GPIO_OSPEEDR_OSPEED4
     
    #define GPIO_OSPEEDER_OSPEEDR4_0   GPIO_OSPEEDR_OSPEED4_0
     
    #define GPIO_OSPEEDER_OSPEEDR4_1   GPIO_OSPEEDR_OSPEED4_1
     
    #define GPIO_OSPEEDER_OSPEEDR5   GPIO_OSPEEDR_OSPEED5
     
    #define GPIO_OSPEEDER_OSPEEDR5_0   GPIO_OSPEEDR_OSPEED5_0
     
    #define GPIO_OSPEEDER_OSPEEDR5_1   GPIO_OSPEEDR_OSPEED5_1
     
    #define GPIO_OSPEEDER_OSPEEDR6   GPIO_OSPEEDR_OSPEED6
     
    #define GPIO_OSPEEDER_OSPEEDR6_0   GPIO_OSPEEDR_OSPEED6_0
     
    #define GPIO_OSPEEDER_OSPEEDR6_1   GPIO_OSPEEDR_OSPEED6_1
     
    #define GPIO_OSPEEDER_OSPEEDR7   GPIO_OSPEEDR_OSPEED7
     
    #define GPIO_OSPEEDER_OSPEEDR7_0   GPIO_OSPEEDR_OSPEED7_0
     
    #define GPIO_OSPEEDER_OSPEEDR7_1   GPIO_OSPEEDR_OSPEED7_1
     
    #define GPIO_OSPEEDER_OSPEEDR8   GPIO_OSPEEDR_OSPEED8
     
    #define GPIO_OSPEEDER_OSPEEDR8_0   GPIO_OSPEEDR_OSPEED8_0
     
    #define GPIO_OSPEEDER_OSPEEDR8_1   GPIO_OSPEEDR_OSPEED8_1
     
    #define GPIO_OSPEEDER_OSPEEDR9   GPIO_OSPEEDR_OSPEED9
     
    #define GPIO_OSPEEDER_OSPEEDR9_0   GPIO_OSPEEDR_OSPEED9_0
     
    #define GPIO_OSPEEDER_OSPEEDR9_1   GPIO_OSPEEDR_OSPEED9_1
     
    #define GPIO_OSPEEDER_OSPEEDR10   GPIO_OSPEEDR_OSPEED10
     
    #define GPIO_OSPEEDER_OSPEEDR10_0   GPIO_OSPEEDR_OSPEED10_0
     
    #define GPIO_OSPEEDER_OSPEEDR10_1   GPIO_OSPEEDR_OSPEED10_1
     
    #define GPIO_OSPEEDER_OSPEEDR11   GPIO_OSPEEDR_OSPEED11
     
    #define GPIO_OSPEEDER_OSPEEDR11_0   GPIO_OSPEEDR_OSPEED11_0
     
    #define GPIO_OSPEEDER_OSPEEDR11_1   GPIO_OSPEEDR_OSPEED11_1
     
    #define GPIO_OSPEEDER_OSPEEDR12   GPIO_OSPEEDR_OSPEED12
     
    #define GPIO_OSPEEDER_OSPEEDR12_0   GPIO_OSPEEDR_OSPEED12_0
     
    #define GPIO_OSPEEDER_OSPEEDR12_1   GPIO_OSPEEDR_OSPEED12_1
     
    #define GPIO_OSPEEDER_OSPEEDR13   GPIO_OSPEEDR_OSPEED13
     
    #define GPIO_OSPEEDER_OSPEEDR13_0   GPIO_OSPEEDR_OSPEED13_0
     
    #define GPIO_OSPEEDER_OSPEEDR13_1   GPIO_OSPEEDR_OSPEED13_1
     
    #define GPIO_OSPEEDER_OSPEEDR14   GPIO_OSPEEDR_OSPEED14
     
    #define GPIO_OSPEEDER_OSPEEDR14_0   GPIO_OSPEEDR_OSPEED14_0
     
    #define GPIO_OSPEEDER_OSPEEDR14_1   GPIO_OSPEEDR_OSPEED14_1
     
    #define GPIO_OSPEEDER_OSPEEDR15   GPIO_OSPEEDR_OSPEED15
     
    #define GPIO_OSPEEDER_OSPEEDR15_0   GPIO_OSPEEDR_OSPEED15_0
     
    #define GPIO_OSPEEDER_OSPEEDR15_1   GPIO_OSPEEDR_OSPEED15_1
     
    #define GPIO_PUPDR_PUPD0_Pos   (0U)
     
    #define GPIO_PUPDR_PUPD0_Msk   (0x3UL << GPIO_PUPDR_PUPD0_Pos)
     
    #define GPIO_PUPDR_PUPD0   GPIO_PUPDR_PUPD0_Msk
     
    #define GPIO_PUPDR_PUPD0_0   (0x1UL << GPIO_PUPDR_PUPD0_Pos)
     
    #define GPIO_PUPDR_PUPD0_1   (0x2UL << GPIO_PUPDR_PUPD0_Pos)
     
    #define GPIO_PUPDR_PUPD1_Pos   (2U)
     
    #define GPIO_PUPDR_PUPD1_Msk   (0x3UL << GPIO_PUPDR_PUPD1_Pos)
     
    #define GPIO_PUPDR_PUPD1   GPIO_PUPDR_PUPD1_Msk
     
    #define GPIO_PUPDR_PUPD1_0   (0x1UL << GPIO_PUPDR_PUPD1_Pos)
     
    #define GPIO_PUPDR_PUPD1_1   (0x2UL << GPIO_PUPDR_PUPD1_Pos)
     
    #define GPIO_PUPDR_PUPD2_Pos   (4U)
     
    #define GPIO_PUPDR_PUPD2_Msk   (0x3UL << GPIO_PUPDR_PUPD2_Pos)
     
    #define GPIO_PUPDR_PUPD2   GPIO_PUPDR_PUPD2_Msk
     
    #define GPIO_PUPDR_PUPD2_0   (0x1UL << GPIO_PUPDR_PUPD2_Pos)
     
    #define GPIO_PUPDR_PUPD2_1   (0x2UL << GPIO_PUPDR_PUPD2_Pos)
     
    #define GPIO_PUPDR_PUPD3_Pos   (6U)
     
    #define GPIO_PUPDR_PUPD3_Msk   (0x3UL << GPIO_PUPDR_PUPD3_Pos)
     
    #define GPIO_PUPDR_PUPD3   GPIO_PUPDR_PUPD3_Msk
     
    #define GPIO_PUPDR_PUPD3_0   (0x1UL << GPIO_PUPDR_PUPD3_Pos)
     
    #define GPIO_PUPDR_PUPD3_1   (0x2UL << GPIO_PUPDR_PUPD3_Pos)
     
    #define GPIO_PUPDR_PUPD4_Pos   (8U)
     
    #define GPIO_PUPDR_PUPD4_Msk   (0x3UL << GPIO_PUPDR_PUPD4_Pos)
     
    #define GPIO_PUPDR_PUPD4   GPIO_PUPDR_PUPD4_Msk
     
    #define GPIO_PUPDR_PUPD4_0   (0x1UL << GPIO_PUPDR_PUPD4_Pos)
     
    #define GPIO_PUPDR_PUPD4_1   (0x2UL << GPIO_PUPDR_PUPD4_Pos)
     
    #define GPIO_PUPDR_PUPD5_Pos   (10U)
     
    #define GPIO_PUPDR_PUPD5_Msk   (0x3UL << GPIO_PUPDR_PUPD5_Pos)
     
    #define GPIO_PUPDR_PUPD5   GPIO_PUPDR_PUPD5_Msk
     
    #define GPIO_PUPDR_PUPD5_0   (0x1UL << GPIO_PUPDR_PUPD5_Pos)
     
    #define GPIO_PUPDR_PUPD5_1   (0x2UL << GPIO_PUPDR_PUPD5_Pos)
     
    #define GPIO_PUPDR_PUPD6_Pos   (12U)
     
    #define GPIO_PUPDR_PUPD6_Msk   (0x3UL << GPIO_PUPDR_PUPD6_Pos)
     
    #define GPIO_PUPDR_PUPD6   GPIO_PUPDR_PUPD6_Msk
     
    #define GPIO_PUPDR_PUPD6_0   (0x1UL << GPIO_PUPDR_PUPD6_Pos)
     
    #define GPIO_PUPDR_PUPD6_1   (0x2UL << GPIO_PUPDR_PUPD6_Pos)
     
    #define GPIO_PUPDR_PUPD7_Pos   (14U)
     
    #define GPIO_PUPDR_PUPD7_Msk   (0x3UL << GPIO_PUPDR_PUPD7_Pos)
     
    #define GPIO_PUPDR_PUPD7   GPIO_PUPDR_PUPD7_Msk
     
    #define GPIO_PUPDR_PUPD7_0   (0x1UL << GPIO_PUPDR_PUPD7_Pos)
     
    #define GPIO_PUPDR_PUPD7_1   (0x2UL << GPIO_PUPDR_PUPD7_Pos)
     
    #define GPIO_PUPDR_PUPD8_Pos   (16U)
     
    #define GPIO_PUPDR_PUPD8_Msk   (0x3UL << GPIO_PUPDR_PUPD8_Pos)
     
    #define GPIO_PUPDR_PUPD8   GPIO_PUPDR_PUPD8_Msk
     
    #define GPIO_PUPDR_PUPD8_0   (0x1UL << GPIO_PUPDR_PUPD8_Pos)
     
    #define GPIO_PUPDR_PUPD8_1   (0x2UL << GPIO_PUPDR_PUPD8_Pos)
     
    #define GPIO_PUPDR_PUPD9_Pos   (18U)
     
    #define GPIO_PUPDR_PUPD9_Msk   (0x3UL << GPIO_PUPDR_PUPD9_Pos)
     
    #define GPIO_PUPDR_PUPD9   GPIO_PUPDR_PUPD9_Msk
     
    #define GPIO_PUPDR_PUPD9_0   (0x1UL << GPIO_PUPDR_PUPD9_Pos)
     
    #define GPIO_PUPDR_PUPD9_1   (0x2UL << GPIO_PUPDR_PUPD9_Pos)
     
    #define GPIO_PUPDR_PUPD10_Pos   (20U)
     
    #define GPIO_PUPDR_PUPD10_Msk   (0x3UL << GPIO_PUPDR_PUPD10_Pos)
     
    #define GPIO_PUPDR_PUPD10   GPIO_PUPDR_PUPD10_Msk
     
    #define GPIO_PUPDR_PUPD10_0   (0x1UL << GPIO_PUPDR_PUPD10_Pos)
     
    #define GPIO_PUPDR_PUPD10_1   (0x2UL << GPIO_PUPDR_PUPD10_Pos)
     
    #define GPIO_PUPDR_PUPD11_Pos   (22U)
     
    #define GPIO_PUPDR_PUPD11_Msk   (0x3UL << GPIO_PUPDR_PUPD11_Pos)
     
    #define GPIO_PUPDR_PUPD11   GPIO_PUPDR_PUPD11_Msk
     
    #define GPIO_PUPDR_PUPD11_0   (0x1UL << GPIO_PUPDR_PUPD11_Pos)
     
    #define GPIO_PUPDR_PUPD11_1   (0x2UL << GPIO_PUPDR_PUPD11_Pos)
     
    #define GPIO_PUPDR_PUPD12_Pos   (24U)
     
    #define GPIO_PUPDR_PUPD12_Msk   (0x3UL << GPIO_PUPDR_PUPD12_Pos)
     
    #define GPIO_PUPDR_PUPD12   GPIO_PUPDR_PUPD12_Msk
     
    #define GPIO_PUPDR_PUPD12_0   (0x1UL << GPIO_PUPDR_PUPD12_Pos)
     
    #define GPIO_PUPDR_PUPD12_1   (0x2UL << GPIO_PUPDR_PUPD12_Pos)
     
    #define GPIO_PUPDR_PUPD13_Pos   (26U)
     
    #define GPIO_PUPDR_PUPD13_Msk   (0x3UL << GPIO_PUPDR_PUPD13_Pos)
     
    #define GPIO_PUPDR_PUPD13   GPIO_PUPDR_PUPD13_Msk
     
    #define GPIO_PUPDR_PUPD13_0   (0x1UL << GPIO_PUPDR_PUPD13_Pos)
     
    #define GPIO_PUPDR_PUPD13_1   (0x2UL << GPIO_PUPDR_PUPD13_Pos)
     
    #define GPIO_PUPDR_PUPD14_Pos   (28U)
     
    #define GPIO_PUPDR_PUPD14_Msk   (0x3UL << GPIO_PUPDR_PUPD14_Pos)
     
    #define GPIO_PUPDR_PUPD14   GPIO_PUPDR_PUPD14_Msk
     
    #define GPIO_PUPDR_PUPD14_0   (0x1UL << GPIO_PUPDR_PUPD14_Pos)
     
    #define GPIO_PUPDR_PUPD14_1   (0x2UL << GPIO_PUPDR_PUPD14_Pos)
     
    #define GPIO_PUPDR_PUPD15_Pos   (30U)
     
    #define GPIO_PUPDR_PUPD15_Msk   (0x3UL << GPIO_PUPDR_PUPD15_Pos)
     
    #define GPIO_PUPDR_PUPD15   GPIO_PUPDR_PUPD15_Msk
     
    #define GPIO_PUPDR_PUPD15_0   (0x1UL << GPIO_PUPDR_PUPD15_Pos)
     
    #define GPIO_PUPDR_PUPD15_1   (0x2UL << GPIO_PUPDR_PUPD15_Pos)
     
    #define GPIO_PUPDR_PUPDR0   GPIO_PUPDR_PUPD0
     
    #define GPIO_PUPDR_PUPDR0_0   GPIO_PUPDR_PUPD0_0
     
    #define GPIO_PUPDR_PUPDR0_1   GPIO_PUPDR_PUPD0_1
     
    #define GPIO_PUPDR_PUPDR1   GPIO_PUPDR_PUPD1
     
    #define GPIO_PUPDR_PUPDR1_0   GPIO_PUPDR_PUPD1_0
     
    #define GPIO_PUPDR_PUPDR1_1   GPIO_PUPDR_PUPD1_1
     
    #define GPIO_PUPDR_PUPDR2   GPIO_PUPDR_PUPD2
     
    #define GPIO_PUPDR_PUPDR2_0   GPIO_PUPDR_PUPD2_0
     
    #define GPIO_PUPDR_PUPDR2_1   GPIO_PUPDR_PUPD2_1
     
    #define GPIO_PUPDR_PUPDR3   GPIO_PUPDR_PUPD3
     
    #define GPIO_PUPDR_PUPDR3_0   GPIO_PUPDR_PUPD3_0
     
    #define GPIO_PUPDR_PUPDR3_1   GPIO_PUPDR_PUPD3_1
     
    #define GPIO_PUPDR_PUPDR4   GPIO_PUPDR_PUPD4
     
    #define GPIO_PUPDR_PUPDR4_0   GPIO_PUPDR_PUPD4_0
     
    #define GPIO_PUPDR_PUPDR4_1   GPIO_PUPDR_PUPD4_1
     
    #define GPIO_PUPDR_PUPDR5   GPIO_PUPDR_PUPD5
     
    #define GPIO_PUPDR_PUPDR5_0   GPIO_PUPDR_PUPD5_0
     
    #define GPIO_PUPDR_PUPDR5_1   GPIO_PUPDR_PUPD5_1
     
    #define GPIO_PUPDR_PUPDR6   GPIO_PUPDR_PUPD6
     
    #define GPIO_PUPDR_PUPDR6_0   GPIO_PUPDR_PUPD6_0
     
    #define GPIO_PUPDR_PUPDR6_1   GPIO_PUPDR_PUPD6_1
     
    #define GPIO_PUPDR_PUPDR7   GPIO_PUPDR_PUPD7
     
    #define GPIO_PUPDR_PUPDR7_0   GPIO_PUPDR_PUPD7_0
     
    #define GPIO_PUPDR_PUPDR7_1   GPIO_PUPDR_PUPD7_1
     
    #define GPIO_PUPDR_PUPDR8   GPIO_PUPDR_PUPD8
     
    #define GPIO_PUPDR_PUPDR8_0   GPIO_PUPDR_PUPD8_0
     
    #define GPIO_PUPDR_PUPDR8_1   GPIO_PUPDR_PUPD8_1
     
    #define GPIO_PUPDR_PUPDR9   GPIO_PUPDR_PUPD9
     
    #define GPIO_PUPDR_PUPDR9_0   GPIO_PUPDR_PUPD9_0
     
    #define GPIO_PUPDR_PUPDR9_1   GPIO_PUPDR_PUPD9_1
     
    #define GPIO_PUPDR_PUPDR10   GPIO_PUPDR_PUPD10
     
    #define GPIO_PUPDR_PUPDR10_0   GPIO_PUPDR_PUPD10_0
     
    #define GPIO_PUPDR_PUPDR10_1   GPIO_PUPDR_PUPD10_1
     
    #define GPIO_PUPDR_PUPDR11   GPIO_PUPDR_PUPD11
     
    #define GPIO_PUPDR_PUPDR11_0   GPIO_PUPDR_PUPD11_0
     
    #define GPIO_PUPDR_PUPDR11_1   GPIO_PUPDR_PUPD11_1
     
    #define GPIO_PUPDR_PUPDR12   GPIO_PUPDR_PUPD12
     
    #define GPIO_PUPDR_PUPDR12_0   GPIO_PUPDR_PUPD12_0
     
    #define GPIO_PUPDR_PUPDR12_1   GPIO_PUPDR_PUPD12_1
     
    #define GPIO_PUPDR_PUPDR13   GPIO_PUPDR_PUPD13
     
    #define GPIO_PUPDR_PUPDR13_0   GPIO_PUPDR_PUPD13_0
     
    #define GPIO_PUPDR_PUPDR13_1   GPIO_PUPDR_PUPD13_1
     
    #define GPIO_PUPDR_PUPDR14   GPIO_PUPDR_PUPD14
     
    #define GPIO_PUPDR_PUPDR14_0   GPIO_PUPDR_PUPD14_0
     
    #define GPIO_PUPDR_PUPDR14_1   GPIO_PUPDR_PUPD14_1
     
    #define GPIO_PUPDR_PUPDR15   GPIO_PUPDR_PUPD15
     
    #define GPIO_PUPDR_PUPDR15_0   GPIO_PUPDR_PUPD15_0
     
    #define GPIO_PUPDR_PUPDR15_1   GPIO_PUPDR_PUPD15_1
     
    #define GPIO_IDR_ID0_Pos   (0U)
     
    #define GPIO_IDR_ID0_Msk   (0x1UL << GPIO_IDR_ID0_Pos)
     
    #define GPIO_IDR_ID0   GPIO_IDR_ID0_Msk
     
    #define GPIO_IDR_ID1_Pos   (1U)
     
    #define GPIO_IDR_ID1_Msk   (0x1UL << GPIO_IDR_ID1_Pos)
     
    #define GPIO_IDR_ID1   GPIO_IDR_ID1_Msk
     
    #define GPIO_IDR_ID2_Pos   (2U)
     
    #define GPIO_IDR_ID2_Msk   (0x1UL << GPIO_IDR_ID2_Pos)
     
    #define GPIO_IDR_ID2   GPIO_IDR_ID2_Msk
     
    #define GPIO_IDR_ID3_Pos   (3U)
     
    #define GPIO_IDR_ID3_Msk   (0x1UL << GPIO_IDR_ID3_Pos)
     
    #define GPIO_IDR_ID3   GPIO_IDR_ID3_Msk
     
    #define GPIO_IDR_ID4_Pos   (4U)
     
    #define GPIO_IDR_ID4_Msk   (0x1UL << GPIO_IDR_ID4_Pos)
     
    #define GPIO_IDR_ID4   GPIO_IDR_ID4_Msk
     
    #define GPIO_IDR_ID5_Pos   (5U)
     
    #define GPIO_IDR_ID5_Msk   (0x1UL << GPIO_IDR_ID5_Pos)
     
    #define GPIO_IDR_ID5   GPIO_IDR_ID5_Msk
     
    #define GPIO_IDR_ID6_Pos   (6U)
     
    #define GPIO_IDR_ID6_Msk   (0x1UL << GPIO_IDR_ID6_Pos)
     
    #define GPIO_IDR_ID6   GPIO_IDR_ID6_Msk
     
    #define GPIO_IDR_ID7_Pos   (7U)
     
    #define GPIO_IDR_ID7_Msk   (0x1UL << GPIO_IDR_ID7_Pos)
     
    #define GPIO_IDR_ID7   GPIO_IDR_ID7_Msk
     
    #define GPIO_IDR_ID8_Pos   (8U)
     
    #define GPIO_IDR_ID8_Msk   (0x1UL << GPIO_IDR_ID8_Pos)
     
    #define GPIO_IDR_ID8   GPIO_IDR_ID8_Msk
     
    #define GPIO_IDR_ID9_Pos   (9U)
     
    #define GPIO_IDR_ID9_Msk   (0x1UL << GPIO_IDR_ID9_Pos)
     
    #define GPIO_IDR_ID9   GPIO_IDR_ID9_Msk
     
    #define GPIO_IDR_ID10_Pos   (10U)
     
    #define GPIO_IDR_ID10_Msk   (0x1UL << GPIO_IDR_ID10_Pos)
     
    #define GPIO_IDR_ID10   GPIO_IDR_ID10_Msk
     
    #define GPIO_IDR_ID11_Pos   (11U)
     
    #define GPIO_IDR_ID11_Msk   (0x1UL << GPIO_IDR_ID11_Pos)
     
    #define GPIO_IDR_ID11   GPIO_IDR_ID11_Msk
     
    #define GPIO_IDR_ID12_Pos   (12U)
     
    #define GPIO_IDR_ID12_Msk   (0x1UL << GPIO_IDR_ID12_Pos)
     
    #define GPIO_IDR_ID12   GPIO_IDR_ID12_Msk
     
    #define GPIO_IDR_ID13_Pos   (13U)
     
    #define GPIO_IDR_ID13_Msk   (0x1UL << GPIO_IDR_ID13_Pos)
     
    #define GPIO_IDR_ID13   GPIO_IDR_ID13_Msk
     
    #define GPIO_IDR_ID14_Pos   (14U)
     
    #define GPIO_IDR_ID14_Msk   (0x1UL << GPIO_IDR_ID14_Pos)
     
    #define GPIO_IDR_ID14   GPIO_IDR_ID14_Msk
     
    #define GPIO_IDR_ID15_Pos   (15U)
     
    #define GPIO_IDR_ID15_Msk   (0x1UL << GPIO_IDR_ID15_Pos)
     
    #define GPIO_IDR_ID15   GPIO_IDR_ID15_Msk
     
    #define GPIO_IDR_IDR_0   GPIO_IDR_ID0
     
    #define GPIO_IDR_IDR_1   GPIO_IDR_ID1
     
    #define GPIO_IDR_IDR_2   GPIO_IDR_ID2
     
    #define GPIO_IDR_IDR_3   GPIO_IDR_ID3
     
    #define GPIO_IDR_IDR_4   GPIO_IDR_ID4
     
    #define GPIO_IDR_IDR_5   GPIO_IDR_ID5
     
    #define GPIO_IDR_IDR_6   GPIO_IDR_ID6
     
    #define GPIO_IDR_IDR_7   GPIO_IDR_ID7
     
    #define GPIO_IDR_IDR_8   GPIO_IDR_ID8
     
    #define GPIO_IDR_IDR_9   GPIO_IDR_ID9
     
    #define GPIO_IDR_IDR_10   GPIO_IDR_ID10
     
    #define GPIO_IDR_IDR_11   GPIO_IDR_ID11
     
    #define GPIO_IDR_IDR_12   GPIO_IDR_ID12
     
    #define GPIO_IDR_IDR_13   GPIO_IDR_ID13
     
    #define GPIO_IDR_IDR_14   GPIO_IDR_ID14
     
    #define GPIO_IDR_IDR_15   GPIO_IDR_ID15
     
    #define GPIO_ODR_OD0_Pos   (0U)
     
    #define GPIO_ODR_OD0_Msk   (0x1UL << GPIO_ODR_OD0_Pos)
     
    #define GPIO_ODR_OD0   GPIO_ODR_OD0_Msk
     
    #define GPIO_ODR_OD1_Pos   (1U)
     
    #define GPIO_ODR_OD1_Msk   (0x1UL << GPIO_ODR_OD1_Pos)
     
    #define GPIO_ODR_OD1   GPIO_ODR_OD1_Msk
     
    #define GPIO_ODR_OD2_Pos   (2U)
     
    #define GPIO_ODR_OD2_Msk   (0x1UL << GPIO_ODR_OD2_Pos)
     
    #define GPIO_ODR_OD2   GPIO_ODR_OD2_Msk
     
    #define GPIO_ODR_OD3_Pos   (3U)
     
    #define GPIO_ODR_OD3_Msk   (0x1UL << GPIO_ODR_OD3_Pos)
     
    #define GPIO_ODR_OD3   GPIO_ODR_OD3_Msk
     
    #define GPIO_ODR_OD4_Pos   (4U)
     
    #define GPIO_ODR_OD4_Msk   (0x1UL << GPIO_ODR_OD4_Pos)
     
    #define GPIO_ODR_OD4   GPIO_ODR_OD4_Msk
     
    #define GPIO_ODR_OD5_Pos   (5U)
     
    #define GPIO_ODR_OD5_Msk   (0x1UL << GPIO_ODR_OD5_Pos)
     
    #define GPIO_ODR_OD5   GPIO_ODR_OD5_Msk
     
    #define GPIO_ODR_OD6_Pos   (6U)
     
    #define GPIO_ODR_OD6_Msk   (0x1UL << GPIO_ODR_OD6_Pos)
     
    #define GPIO_ODR_OD6   GPIO_ODR_OD6_Msk
     
    #define GPIO_ODR_OD7_Pos   (7U)
     
    #define GPIO_ODR_OD7_Msk   (0x1UL << GPIO_ODR_OD7_Pos)
     
    #define GPIO_ODR_OD7   GPIO_ODR_OD7_Msk
     
    #define GPIO_ODR_OD8_Pos   (8U)
     
    #define GPIO_ODR_OD8_Msk   (0x1UL << GPIO_ODR_OD8_Pos)
     
    #define GPIO_ODR_OD8   GPIO_ODR_OD8_Msk
     
    #define GPIO_ODR_OD9_Pos   (9U)
     
    #define GPIO_ODR_OD9_Msk   (0x1UL << GPIO_ODR_OD9_Pos)
     
    #define GPIO_ODR_OD9   GPIO_ODR_OD9_Msk
     
    #define GPIO_ODR_OD10_Pos   (10U)
     
    #define GPIO_ODR_OD10_Msk   (0x1UL << GPIO_ODR_OD10_Pos)
     
    #define GPIO_ODR_OD10   GPIO_ODR_OD10_Msk
     
    #define GPIO_ODR_OD11_Pos   (11U)
     
    #define GPIO_ODR_OD11_Msk   (0x1UL << GPIO_ODR_OD11_Pos)
     
    #define GPIO_ODR_OD11   GPIO_ODR_OD11_Msk
     
    #define GPIO_ODR_OD12_Pos   (12U)
     
    #define GPIO_ODR_OD12_Msk   (0x1UL << GPIO_ODR_OD12_Pos)
     
    #define GPIO_ODR_OD12   GPIO_ODR_OD12_Msk
     
    #define GPIO_ODR_OD13_Pos   (13U)
     
    #define GPIO_ODR_OD13_Msk   (0x1UL << GPIO_ODR_OD13_Pos)
     
    #define GPIO_ODR_OD13   GPIO_ODR_OD13_Msk
     
    #define GPIO_ODR_OD14_Pos   (14U)
     
    #define GPIO_ODR_OD14_Msk   (0x1UL << GPIO_ODR_OD14_Pos)
     
    #define GPIO_ODR_OD14   GPIO_ODR_OD14_Msk
     
    #define GPIO_ODR_OD15_Pos   (15U)
     
    #define GPIO_ODR_OD15_Msk   (0x1UL << GPIO_ODR_OD15_Pos)
     
    #define GPIO_ODR_OD15   GPIO_ODR_OD15_Msk
     
    #define GPIO_ODR_ODR_0   GPIO_ODR_OD0
     
    #define GPIO_ODR_ODR_1   GPIO_ODR_OD1
     
    #define GPIO_ODR_ODR_2   GPIO_ODR_OD2
     
    #define GPIO_ODR_ODR_3   GPIO_ODR_OD3
     
    #define GPIO_ODR_ODR_4   GPIO_ODR_OD4
     
    #define GPIO_ODR_ODR_5   GPIO_ODR_OD5
     
    #define GPIO_ODR_ODR_6   GPIO_ODR_OD6
     
    #define GPIO_ODR_ODR_7   GPIO_ODR_OD7
     
    #define GPIO_ODR_ODR_8   GPIO_ODR_OD8
     
    #define GPIO_ODR_ODR_9   GPIO_ODR_OD9
     
    #define GPIO_ODR_ODR_10   GPIO_ODR_OD10
     
    #define GPIO_ODR_ODR_11   GPIO_ODR_OD11
     
    #define GPIO_ODR_ODR_12   GPIO_ODR_OD12
     
    #define GPIO_ODR_ODR_13   GPIO_ODR_OD13
     
    #define GPIO_ODR_ODR_14   GPIO_ODR_OD14
     
    #define GPIO_ODR_ODR_15   GPIO_ODR_OD15
     
    #define GPIO_BSRR_BS0_Pos   (0U)
     
    #define GPIO_BSRR_BS0_Msk   (0x1UL << GPIO_BSRR_BS0_Pos)
     
    #define GPIO_BSRR_BS0   GPIO_BSRR_BS0_Msk
     
    #define GPIO_BSRR_BS1_Pos   (1U)
     
    #define GPIO_BSRR_BS1_Msk   (0x1UL << GPIO_BSRR_BS1_Pos)
     
    #define GPIO_BSRR_BS1   GPIO_BSRR_BS1_Msk
     
    #define GPIO_BSRR_BS2_Pos   (2U)
     
    #define GPIO_BSRR_BS2_Msk   (0x1UL << GPIO_BSRR_BS2_Pos)
     
    #define GPIO_BSRR_BS2   GPIO_BSRR_BS2_Msk
     
    #define GPIO_BSRR_BS3_Pos   (3U)
     
    #define GPIO_BSRR_BS3_Msk   (0x1UL << GPIO_BSRR_BS3_Pos)
     
    #define GPIO_BSRR_BS3   GPIO_BSRR_BS3_Msk
     
    #define GPIO_BSRR_BS4_Pos   (4U)
     
    #define GPIO_BSRR_BS4_Msk   (0x1UL << GPIO_BSRR_BS4_Pos)
     
    #define GPIO_BSRR_BS4   GPIO_BSRR_BS4_Msk
     
    #define GPIO_BSRR_BS5_Pos   (5U)
     
    #define GPIO_BSRR_BS5_Msk   (0x1UL << GPIO_BSRR_BS5_Pos)
     
    #define GPIO_BSRR_BS5   GPIO_BSRR_BS5_Msk
     
    #define GPIO_BSRR_BS6_Pos   (6U)
     
    #define GPIO_BSRR_BS6_Msk   (0x1UL << GPIO_BSRR_BS6_Pos)
     
    #define GPIO_BSRR_BS6   GPIO_BSRR_BS6_Msk
     
    #define GPIO_BSRR_BS7_Pos   (7U)
     
    #define GPIO_BSRR_BS7_Msk   (0x1UL << GPIO_BSRR_BS7_Pos)
     
    #define GPIO_BSRR_BS7   GPIO_BSRR_BS7_Msk
     
    #define GPIO_BSRR_BS8_Pos   (8U)
     
    #define GPIO_BSRR_BS8_Msk   (0x1UL << GPIO_BSRR_BS8_Pos)
     
    #define GPIO_BSRR_BS8   GPIO_BSRR_BS8_Msk
     
    #define GPIO_BSRR_BS9_Pos   (9U)
     
    #define GPIO_BSRR_BS9_Msk   (0x1UL << GPIO_BSRR_BS9_Pos)
     
    #define GPIO_BSRR_BS9   GPIO_BSRR_BS9_Msk
     
    #define GPIO_BSRR_BS10_Pos   (10U)
     
    #define GPIO_BSRR_BS10_Msk   (0x1UL << GPIO_BSRR_BS10_Pos)
     
    #define GPIO_BSRR_BS10   GPIO_BSRR_BS10_Msk
     
    #define GPIO_BSRR_BS11_Pos   (11U)
     
    #define GPIO_BSRR_BS11_Msk   (0x1UL << GPIO_BSRR_BS11_Pos)
     
    #define GPIO_BSRR_BS11   GPIO_BSRR_BS11_Msk
     
    #define GPIO_BSRR_BS12_Pos   (12U)
     
    #define GPIO_BSRR_BS12_Msk   (0x1UL << GPIO_BSRR_BS12_Pos)
     
    #define GPIO_BSRR_BS12   GPIO_BSRR_BS12_Msk
     
    #define GPIO_BSRR_BS13_Pos   (13U)
     
    #define GPIO_BSRR_BS13_Msk   (0x1UL << GPIO_BSRR_BS13_Pos)
     
    #define GPIO_BSRR_BS13   GPIO_BSRR_BS13_Msk
     
    #define GPIO_BSRR_BS14_Pos   (14U)
     
    #define GPIO_BSRR_BS14_Msk   (0x1UL << GPIO_BSRR_BS14_Pos)
     
    #define GPIO_BSRR_BS14   GPIO_BSRR_BS14_Msk
     
    #define GPIO_BSRR_BS15_Pos   (15U)
     
    #define GPIO_BSRR_BS15_Msk   (0x1UL << GPIO_BSRR_BS15_Pos)
     
    #define GPIO_BSRR_BS15   GPIO_BSRR_BS15_Msk
     
    #define GPIO_BSRR_BR0_Pos   (16U)
     
    #define GPIO_BSRR_BR0_Msk   (0x1UL << GPIO_BSRR_BR0_Pos)
     
    #define GPIO_BSRR_BR0   GPIO_BSRR_BR0_Msk
     
    #define GPIO_BSRR_BR1_Pos   (17U)
     
    #define GPIO_BSRR_BR1_Msk   (0x1UL << GPIO_BSRR_BR1_Pos)
     
    #define GPIO_BSRR_BR1   GPIO_BSRR_BR1_Msk
     
    #define GPIO_BSRR_BR2_Pos   (18U)
     
    #define GPIO_BSRR_BR2_Msk   (0x1UL << GPIO_BSRR_BR2_Pos)
     
    #define GPIO_BSRR_BR2   GPIO_BSRR_BR2_Msk
     
    #define GPIO_BSRR_BR3_Pos   (19U)
     
    #define GPIO_BSRR_BR3_Msk   (0x1UL << GPIO_BSRR_BR3_Pos)
     
    #define GPIO_BSRR_BR3   GPIO_BSRR_BR3_Msk
     
    #define GPIO_BSRR_BR4_Pos   (20U)
     
    #define GPIO_BSRR_BR4_Msk   (0x1UL << GPIO_BSRR_BR4_Pos)
     
    #define GPIO_BSRR_BR4   GPIO_BSRR_BR4_Msk
     
    #define GPIO_BSRR_BR5_Pos   (21U)
     
    #define GPIO_BSRR_BR5_Msk   (0x1UL << GPIO_BSRR_BR5_Pos)
     
    #define GPIO_BSRR_BR5   GPIO_BSRR_BR5_Msk
     
    #define GPIO_BSRR_BR6_Pos   (22U)
     
    #define GPIO_BSRR_BR6_Msk   (0x1UL << GPIO_BSRR_BR6_Pos)
     
    #define GPIO_BSRR_BR6   GPIO_BSRR_BR6_Msk
     
    #define GPIO_BSRR_BR7_Pos   (23U)
     
    #define GPIO_BSRR_BR7_Msk   (0x1UL << GPIO_BSRR_BR7_Pos)
     
    #define GPIO_BSRR_BR7   GPIO_BSRR_BR7_Msk
     
    #define GPIO_BSRR_BR8_Pos   (24U)
     
    #define GPIO_BSRR_BR8_Msk   (0x1UL << GPIO_BSRR_BR8_Pos)
     
    #define GPIO_BSRR_BR8   GPIO_BSRR_BR8_Msk
     
    #define GPIO_BSRR_BR9_Pos   (25U)
     
    #define GPIO_BSRR_BR9_Msk   (0x1UL << GPIO_BSRR_BR9_Pos)
     
    #define GPIO_BSRR_BR9   GPIO_BSRR_BR9_Msk
     
    #define GPIO_BSRR_BR10_Pos   (26U)
     
    #define GPIO_BSRR_BR10_Msk   (0x1UL << GPIO_BSRR_BR10_Pos)
     
    #define GPIO_BSRR_BR10   GPIO_BSRR_BR10_Msk
     
    #define GPIO_BSRR_BR11_Pos   (27U)
     
    #define GPIO_BSRR_BR11_Msk   (0x1UL << GPIO_BSRR_BR11_Pos)
     
    #define GPIO_BSRR_BR11   GPIO_BSRR_BR11_Msk
     
    #define GPIO_BSRR_BR12_Pos   (28U)
     
    #define GPIO_BSRR_BR12_Msk   (0x1UL << GPIO_BSRR_BR12_Pos)
     
    #define GPIO_BSRR_BR12   GPIO_BSRR_BR12_Msk
     
    #define GPIO_BSRR_BR13_Pos   (29U)
     
    #define GPIO_BSRR_BR13_Msk   (0x1UL << GPIO_BSRR_BR13_Pos)
     
    #define GPIO_BSRR_BR13   GPIO_BSRR_BR13_Msk
     
    #define GPIO_BSRR_BR14_Pos   (30U)
     
    #define GPIO_BSRR_BR14_Msk   (0x1UL << GPIO_BSRR_BR14_Pos)
     
    #define GPIO_BSRR_BR14   GPIO_BSRR_BR14_Msk
     
    #define GPIO_BSRR_BR15_Pos   (31U)
     
    #define GPIO_BSRR_BR15_Msk   (0x1UL << GPIO_BSRR_BR15_Pos)
     
    #define GPIO_BSRR_BR15   GPIO_BSRR_BR15_Msk
     
    #define GPIO_BSRR_BS_0   GPIO_BSRR_BS0
     
    #define GPIO_BSRR_BS_1   GPIO_BSRR_BS1
     
    #define GPIO_BSRR_BS_2   GPIO_BSRR_BS2
     
    #define GPIO_BSRR_BS_3   GPIO_BSRR_BS3
     
    #define GPIO_BSRR_BS_4   GPIO_BSRR_BS4
     
    #define GPIO_BSRR_BS_5   GPIO_BSRR_BS5
     
    #define GPIO_BSRR_BS_6   GPIO_BSRR_BS6
     
    #define GPIO_BSRR_BS_7   GPIO_BSRR_BS7
     
    #define GPIO_BSRR_BS_8   GPIO_BSRR_BS8
     
    #define GPIO_BSRR_BS_9   GPIO_BSRR_BS9
     
    #define GPIO_BSRR_BS_10   GPIO_BSRR_BS10
     
    #define GPIO_BSRR_BS_11   GPIO_BSRR_BS11
     
    #define GPIO_BSRR_BS_12   GPIO_BSRR_BS12
     
    #define GPIO_BSRR_BS_13   GPIO_BSRR_BS13
     
    #define GPIO_BSRR_BS_14   GPIO_BSRR_BS14
     
    #define GPIO_BSRR_BS_15   GPIO_BSRR_BS15
     
    #define GPIO_BSRR_BR_0   GPIO_BSRR_BR0
     
    #define GPIO_BSRR_BR_1   GPIO_BSRR_BR1
     
    #define GPIO_BSRR_BR_2   GPIO_BSRR_BR2
     
    #define GPIO_BSRR_BR_3   GPIO_BSRR_BR3
     
    #define GPIO_BSRR_BR_4   GPIO_BSRR_BR4
     
    #define GPIO_BSRR_BR_5   GPIO_BSRR_BR5
     
    #define GPIO_BSRR_BR_6   GPIO_BSRR_BR6
     
    #define GPIO_BSRR_BR_7   GPIO_BSRR_BR7
     
    #define GPIO_BSRR_BR_8   GPIO_BSRR_BR8
     
    #define GPIO_BSRR_BR_9   GPIO_BSRR_BR9
     
    #define GPIO_BSRR_BR_10   GPIO_BSRR_BR10
     
    #define GPIO_BSRR_BR_11   GPIO_BSRR_BR11
     
    #define GPIO_BSRR_BR_12   GPIO_BSRR_BR12
     
    #define GPIO_BSRR_BR_13   GPIO_BSRR_BR13
     
    #define GPIO_BSRR_BR_14   GPIO_BSRR_BR14
     
    #define GPIO_BSRR_BR_15   GPIO_BSRR_BR15
     
    #define GPIO_BRR_BR0   GPIO_BSRR_BR0
     
    #define GPIO_BRR_BR0_Pos   GPIO_BSRR_BR0_Pos
     
    #define GPIO_BRR_BR0_Msk   GPIO_BSRR_BR0_Msk
     
    #define GPIO_BRR_BR1   GPIO_BSRR_BR1
     
    #define GPIO_BRR_BR1_Pos   GPIO_BSRR_BR1_Pos
     
    #define GPIO_BRR_BR1_Msk   GPIO_BSRR_BR1_Msk
     
    #define GPIO_BRR_BR2   GPIO_BSRR_BR2
     
    #define GPIO_BRR_BR2_Pos   GPIO_BSRR_BR2_Pos
     
    #define GPIO_BRR_BR2_Msk   GPIO_BSRR_BR2_Msk
     
    #define GPIO_BRR_BR3   GPIO_BSRR_BR3
     
    #define GPIO_BRR_BR3_Pos   GPIO_BSRR_BR3_Pos
     
    #define GPIO_BRR_BR3_Msk   GPIO_BSRR_BR3_Msk
     
    #define GPIO_BRR_BR4   GPIO_BSRR_BR4
     
    #define GPIO_BRR_BR4_Pos   GPIO_BSRR_BR4_Pos
     
    #define GPIO_BRR_BR4_Msk   GPIO_BSRR_BR4_Msk
     
    #define GPIO_BRR_BR5   GPIO_BSRR_BR5
     
    #define GPIO_BRR_BR5_Pos   GPIO_BSRR_BR5_Pos
     
    #define GPIO_BRR_BR5_Msk   GPIO_BSRR_BR5_Msk
     
    #define GPIO_BRR_BR6   GPIO_BSRR_BR6
     
    #define GPIO_BRR_BR6_Pos   GPIO_BSRR_BR6_Pos
     
    #define GPIO_BRR_BR6_Msk   GPIO_BSRR_BR6_Msk
     
    #define GPIO_BRR_BR7   GPIO_BSRR_BR7
     
    #define GPIO_BRR_BR7_Pos   GPIO_BSRR_BR7_Pos
     
    #define GPIO_BRR_BR7_Msk   GPIO_BSRR_BR7_Msk
     
    #define GPIO_BRR_BR8   GPIO_BSRR_BR8
     
    #define GPIO_BRR_BR8_Pos   GPIO_BSRR_BR8_Pos
     
    #define GPIO_BRR_BR8_Msk   GPIO_BSRR_BR8_Msk
     
    #define GPIO_BRR_BR9   GPIO_BSRR_BR9
     
    #define GPIO_BRR_BR9_Pos   GPIO_BSRR_BR9_Pos
     
    #define GPIO_BRR_BR9_Msk   GPIO_BSRR_BR9_Msk
     
    #define GPIO_BRR_BR10   GPIO_BSRR_BR10
     
    #define GPIO_BRR_BR10_Pos   GPIO_BSRR_BR10_Pos
     
    #define GPIO_BRR_BR10_Msk   GPIO_BSRR_BR10_Msk
     
    #define GPIO_BRR_BR11   GPIO_BSRR_BR11
     
    #define GPIO_BRR_BR11_Pos   GPIO_BSRR_BR11_Pos
     
    #define GPIO_BRR_BR11_Msk   GPIO_BSRR_BR11_Msk
     
    #define GPIO_BRR_BR12   GPIO_BSRR_BR12
     
    #define GPIO_BRR_BR12_Pos   GPIO_BSRR_BR12_Pos
     
    #define GPIO_BRR_BR12_Msk   GPIO_BSRR_BR12_Msk
     
    #define GPIO_BRR_BR13   GPIO_BSRR_BR13
     
    #define GPIO_BRR_BR13_Pos   GPIO_BSRR_BR13_Pos
     
    #define GPIO_BRR_BR13_Msk   GPIO_BSRR_BR13_Msk
     
    #define GPIO_BRR_BR14   GPIO_BSRR_BR14
     
    #define GPIO_BRR_BR14_Pos   GPIO_BSRR_BR14_Pos
     
    #define GPIO_BRR_BR14_Msk   GPIO_BSRR_BR14_Msk
     
    #define GPIO_BRR_BR15   GPIO_BSRR_BR15
     
    #define GPIO_BRR_BR15_Pos   GPIO_BSRR_BR15_Pos
     
    #define GPIO_BRR_BR15_Msk   GPIO_BSRR_BR15_Msk
     
    #define GPIO_LCKR_LCK0_Pos   (0U)
     
    #define GPIO_LCKR_LCK0_Msk   (0x1UL << GPIO_LCKR_LCK0_Pos)
     
    #define GPIO_LCKR_LCK0   GPIO_LCKR_LCK0_Msk
     
    #define GPIO_LCKR_LCK1_Pos   (1U)
     
    #define GPIO_LCKR_LCK1_Msk   (0x1UL << GPIO_LCKR_LCK1_Pos)
     
    #define GPIO_LCKR_LCK1   GPIO_LCKR_LCK1_Msk
     
    #define GPIO_LCKR_LCK2_Pos   (2U)
     
    #define GPIO_LCKR_LCK2_Msk   (0x1UL << GPIO_LCKR_LCK2_Pos)
     
    #define GPIO_LCKR_LCK2   GPIO_LCKR_LCK2_Msk
     
    #define GPIO_LCKR_LCK3_Pos   (3U)
     
    #define GPIO_LCKR_LCK3_Msk   (0x1UL << GPIO_LCKR_LCK3_Pos)
     
    #define GPIO_LCKR_LCK3   GPIO_LCKR_LCK3_Msk
     
    #define GPIO_LCKR_LCK4_Pos   (4U)
     
    #define GPIO_LCKR_LCK4_Msk   (0x1UL << GPIO_LCKR_LCK4_Pos)
     
    #define GPIO_LCKR_LCK4   GPIO_LCKR_LCK4_Msk
     
    #define GPIO_LCKR_LCK5_Pos   (5U)
     
    #define GPIO_LCKR_LCK5_Msk   (0x1UL << GPIO_LCKR_LCK5_Pos)
     
    #define GPIO_LCKR_LCK5   GPIO_LCKR_LCK5_Msk
     
    #define GPIO_LCKR_LCK6_Pos   (6U)
     
    #define GPIO_LCKR_LCK6_Msk   (0x1UL << GPIO_LCKR_LCK6_Pos)
     
    #define GPIO_LCKR_LCK6   GPIO_LCKR_LCK6_Msk
     
    #define GPIO_LCKR_LCK7_Pos   (7U)
     
    #define GPIO_LCKR_LCK7_Msk   (0x1UL << GPIO_LCKR_LCK7_Pos)
     
    #define GPIO_LCKR_LCK7   GPIO_LCKR_LCK7_Msk
     
    #define GPIO_LCKR_LCK8_Pos   (8U)
     
    #define GPIO_LCKR_LCK8_Msk   (0x1UL << GPIO_LCKR_LCK8_Pos)
     
    #define GPIO_LCKR_LCK8   GPIO_LCKR_LCK8_Msk
     
    #define GPIO_LCKR_LCK9_Pos   (9U)
     
    #define GPIO_LCKR_LCK9_Msk   (0x1UL << GPIO_LCKR_LCK9_Pos)
     
    #define GPIO_LCKR_LCK9   GPIO_LCKR_LCK9_Msk
     
    #define GPIO_LCKR_LCK10_Pos   (10U)
     
    #define GPIO_LCKR_LCK10_Msk   (0x1UL << GPIO_LCKR_LCK10_Pos)
     
    #define GPIO_LCKR_LCK10   GPIO_LCKR_LCK10_Msk
     
    #define GPIO_LCKR_LCK11_Pos   (11U)
     
    #define GPIO_LCKR_LCK11_Msk   (0x1UL << GPIO_LCKR_LCK11_Pos)
     
    #define GPIO_LCKR_LCK11   GPIO_LCKR_LCK11_Msk
     
    #define GPIO_LCKR_LCK12_Pos   (12U)
     
    #define GPIO_LCKR_LCK12_Msk   (0x1UL << GPIO_LCKR_LCK12_Pos)
     
    #define GPIO_LCKR_LCK12   GPIO_LCKR_LCK12_Msk
     
    #define GPIO_LCKR_LCK13_Pos   (13U)
     
    #define GPIO_LCKR_LCK13_Msk   (0x1UL << GPIO_LCKR_LCK13_Pos)
     
    #define GPIO_LCKR_LCK13   GPIO_LCKR_LCK13_Msk
     
    #define GPIO_LCKR_LCK14_Pos   (14U)
     
    #define GPIO_LCKR_LCK14_Msk   (0x1UL << GPIO_LCKR_LCK14_Pos)
     
    #define GPIO_LCKR_LCK14   GPIO_LCKR_LCK14_Msk
     
    #define GPIO_LCKR_LCK15_Pos   (15U)
     
    #define GPIO_LCKR_LCK15_Msk   (0x1UL << GPIO_LCKR_LCK15_Pos)
     
    #define GPIO_LCKR_LCK15   GPIO_LCKR_LCK15_Msk
     
    #define GPIO_LCKR_LCKK_Pos   (16U)
     
    #define GPIO_LCKR_LCKK_Msk   (0x1UL << GPIO_LCKR_LCKK_Pos)
     
    #define GPIO_LCKR_LCKK   GPIO_LCKR_LCKK_Msk
     
    #define GPIO_AFRL_AFSEL0_Pos   (0U)
     
    #define GPIO_AFRL_AFSEL0_Msk   (0xFUL << GPIO_AFRL_AFSEL0_Pos)
     
    #define GPIO_AFRL_AFSEL0   GPIO_AFRL_AFSEL0_Msk
     
    #define GPIO_AFRL_AFSEL0_0   (0x1UL << GPIO_AFRL_AFSEL0_Pos)
     
    #define GPIO_AFRL_AFSEL0_1   (0x2UL << GPIO_AFRL_AFSEL0_Pos)
     
    #define GPIO_AFRL_AFSEL0_2   (0x4UL << GPIO_AFRL_AFSEL0_Pos)
     
    #define GPIO_AFRL_AFSEL0_3   (0x8UL << GPIO_AFRL_AFSEL0_Pos)
     
    #define GPIO_AFRL_AFSEL1_Pos   (4U)
     
    #define GPIO_AFRL_AFSEL1_Msk   (0xFUL << GPIO_AFRL_AFSEL1_Pos)
     
    #define GPIO_AFRL_AFSEL1   GPIO_AFRL_AFSEL1_Msk
     
    #define GPIO_AFRL_AFSEL1_0   (0x1UL << GPIO_AFRL_AFSEL1_Pos)
     
    #define GPIO_AFRL_AFSEL1_1   (0x2UL << GPIO_AFRL_AFSEL1_Pos)
     
    #define GPIO_AFRL_AFSEL1_2   (0x4UL << GPIO_AFRL_AFSEL1_Pos)
     
    #define GPIO_AFRL_AFSEL1_3   (0x8UL << GPIO_AFRL_AFSEL1_Pos)
     
    #define GPIO_AFRL_AFSEL2_Pos   (8U)
     
    #define GPIO_AFRL_AFSEL2_Msk   (0xFUL << GPIO_AFRL_AFSEL2_Pos)
     
    #define GPIO_AFRL_AFSEL2   GPIO_AFRL_AFSEL2_Msk
     
    #define GPIO_AFRL_AFSEL2_0   (0x1UL << GPIO_AFRL_AFSEL2_Pos)
     
    #define GPIO_AFRL_AFSEL2_1   (0x2UL << GPIO_AFRL_AFSEL2_Pos)
     
    #define GPIO_AFRL_AFSEL2_2   (0x4UL << GPIO_AFRL_AFSEL2_Pos)
     
    #define GPIO_AFRL_AFSEL2_3   (0x8UL << GPIO_AFRL_AFSEL2_Pos)
     
    #define GPIO_AFRL_AFSEL3_Pos   (12U)
     
    #define GPIO_AFRL_AFSEL3_Msk   (0xFUL << GPIO_AFRL_AFSEL3_Pos)
     
    #define GPIO_AFRL_AFSEL3   GPIO_AFRL_AFSEL3_Msk
     
    #define GPIO_AFRL_AFSEL3_0   (0x1UL << GPIO_AFRL_AFSEL3_Pos)
     
    #define GPIO_AFRL_AFSEL3_1   (0x2UL << GPIO_AFRL_AFSEL3_Pos)
     
    #define GPIO_AFRL_AFSEL3_2   (0x4UL << GPIO_AFRL_AFSEL3_Pos)
     
    #define GPIO_AFRL_AFSEL3_3   (0x8UL << GPIO_AFRL_AFSEL3_Pos)
     
    #define GPIO_AFRL_AFSEL4_Pos   (16U)
     
    #define GPIO_AFRL_AFSEL4_Msk   (0xFUL << GPIO_AFRL_AFSEL4_Pos)
     
    #define GPIO_AFRL_AFSEL4   GPIO_AFRL_AFSEL4_Msk
     
    #define GPIO_AFRL_AFSEL4_0   (0x1UL << GPIO_AFRL_AFSEL4_Pos)
     
    #define GPIO_AFRL_AFSEL4_1   (0x2UL << GPIO_AFRL_AFSEL4_Pos)
     
    #define GPIO_AFRL_AFSEL4_2   (0x4UL << GPIO_AFRL_AFSEL4_Pos)
     
    #define GPIO_AFRL_AFSEL4_3   (0x8UL << GPIO_AFRL_AFSEL4_Pos)
     
    #define GPIO_AFRL_AFSEL5_Pos   (20U)
     
    #define GPIO_AFRL_AFSEL5_Msk   (0xFUL << GPIO_AFRL_AFSEL5_Pos)
     
    #define GPIO_AFRL_AFSEL5   GPIO_AFRL_AFSEL5_Msk
     
    #define GPIO_AFRL_AFSEL5_0   (0x1UL << GPIO_AFRL_AFSEL5_Pos)
     
    #define GPIO_AFRL_AFSEL5_1   (0x2UL << GPIO_AFRL_AFSEL5_Pos)
     
    #define GPIO_AFRL_AFSEL5_2   (0x4UL << GPIO_AFRL_AFSEL5_Pos)
     
    #define GPIO_AFRL_AFSEL5_3   (0x8UL << GPIO_AFRL_AFSEL5_Pos)
     
    #define GPIO_AFRL_AFSEL6_Pos   (24U)
     
    #define GPIO_AFRL_AFSEL6_Msk   (0xFUL << GPIO_AFRL_AFSEL6_Pos)
     
    #define GPIO_AFRL_AFSEL6   GPIO_AFRL_AFSEL6_Msk
     
    #define GPIO_AFRL_AFSEL6_0   (0x1UL << GPIO_AFRL_AFSEL6_Pos)
     
    #define GPIO_AFRL_AFSEL6_1   (0x2UL << GPIO_AFRL_AFSEL6_Pos)
     
    #define GPIO_AFRL_AFSEL6_2   (0x4UL << GPIO_AFRL_AFSEL6_Pos)
     
    #define GPIO_AFRL_AFSEL6_3   (0x8UL << GPIO_AFRL_AFSEL6_Pos)
     
    #define GPIO_AFRL_AFSEL7_Pos   (28U)
     
    #define GPIO_AFRL_AFSEL7_Msk   (0xFUL << GPIO_AFRL_AFSEL7_Pos)
     
    #define GPIO_AFRL_AFSEL7   GPIO_AFRL_AFSEL7_Msk
     
    #define GPIO_AFRL_AFSEL7_0   (0x1UL << GPIO_AFRL_AFSEL7_Pos)
     
    #define GPIO_AFRL_AFSEL7_1   (0x2UL << GPIO_AFRL_AFSEL7_Pos)
     
    #define GPIO_AFRL_AFSEL7_2   (0x4UL << GPIO_AFRL_AFSEL7_Pos)
     
    #define GPIO_AFRL_AFSEL7_3   (0x8UL << GPIO_AFRL_AFSEL7_Pos)
     
    #define GPIO_AFRL_AFRL0   GPIO_AFRL_AFSEL0
     
    #define GPIO_AFRL_AFRL0_0   GPIO_AFRL_AFSEL0_0
     
    #define GPIO_AFRL_AFRL0_1   GPIO_AFRL_AFSEL0_1
     
    #define GPIO_AFRL_AFRL0_2   GPIO_AFRL_AFSEL0_2
     
    #define GPIO_AFRL_AFRL0_3   GPIO_AFRL_AFSEL0_3
     
    #define GPIO_AFRL_AFRL1   GPIO_AFRL_AFSEL1
     
    #define GPIO_AFRL_AFRL1_0   GPIO_AFRL_AFSEL1_0
     
    #define GPIO_AFRL_AFRL1_1   GPIO_AFRL_AFSEL1_1
     
    #define GPIO_AFRL_AFRL1_2   GPIO_AFRL_AFSEL1_2
     
    #define GPIO_AFRL_AFRL1_3   GPIO_AFRL_AFSEL1_3
     
    #define GPIO_AFRL_AFRL2   GPIO_AFRL_AFSEL2
     
    #define GPIO_AFRL_AFRL2_0   GPIO_AFRL_AFSEL2_0
     
    #define GPIO_AFRL_AFRL2_1   GPIO_AFRL_AFSEL2_1
     
    #define GPIO_AFRL_AFRL2_2   GPIO_AFRL_AFSEL2_2
     
    #define GPIO_AFRL_AFRL2_3   GPIO_AFRL_AFSEL2_3
     
    #define GPIO_AFRL_AFRL3   GPIO_AFRL_AFSEL3
     
    #define GPIO_AFRL_AFRL3_0   GPIO_AFRL_AFSEL3_0
     
    #define GPIO_AFRL_AFRL3_1   GPIO_AFRL_AFSEL3_1
     
    #define GPIO_AFRL_AFRL3_2   GPIO_AFRL_AFSEL3_2
     
    #define GPIO_AFRL_AFRL3_3   GPIO_AFRL_AFSEL3_3
     
    #define GPIO_AFRL_AFRL4   GPIO_AFRL_AFSEL4
     
    #define GPIO_AFRL_AFRL4_0   GPIO_AFRL_AFSEL4_0
     
    #define GPIO_AFRL_AFRL4_1   GPIO_AFRL_AFSEL4_1
     
    #define GPIO_AFRL_AFRL4_2   GPIO_AFRL_AFSEL4_2
     
    #define GPIO_AFRL_AFRL4_3   GPIO_AFRL_AFSEL4_3
     
    #define GPIO_AFRL_AFRL5   GPIO_AFRL_AFSEL5
     
    #define GPIO_AFRL_AFRL5_0   GPIO_AFRL_AFSEL5_0
     
    #define GPIO_AFRL_AFRL5_1   GPIO_AFRL_AFSEL5_1
     
    #define GPIO_AFRL_AFRL5_2   GPIO_AFRL_AFSEL5_2
     
    #define GPIO_AFRL_AFRL5_3   GPIO_AFRL_AFSEL5_3
     
    #define GPIO_AFRL_AFRL6   GPIO_AFRL_AFSEL6
     
    #define GPIO_AFRL_AFRL6_0   GPIO_AFRL_AFSEL6_0
     
    #define GPIO_AFRL_AFRL6_1   GPIO_AFRL_AFSEL6_1
     
    #define GPIO_AFRL_AFRL6_2   GPIO_AFRL_AFSEL6_2
     
    #define GPIO_AFRL_AFRL6_3   GPIO_AFRL_AFSEL6_3
     
    #define GPIO_AFRL_AFRL7   GPIO_AFRL_AFSEL7
     
    #define GPIO_AFRL_AFRL7_0   GPIO_AFRL_AFSEL7_0
     
    #define GPIO_AFRL_AFRL7_1   GPIO_AFRL_AFSEL7_1
     
    #define GPIO_AFRL_AFRL7_2   GPIO_AFRL_AFSEL7_2
     
    #define GPIO_AFRL_AFRL7_3   GPIO_AFRL_AFSEL7_3
     
    #define GPIO_AFRH_AFSEL8_Pos   (0U)
     
    #define GPIO_AFRH_AFSEL8_Msk   (0xFUL << GPIO_AFRH_AFSEL8_Pos)
     
    #define GPIO_AFRH_AFSEL8   GPIO_AFRH_AFSEL8_Msk
     
    #define GPIO_AFRH_AFSEL8_0   (0x1UL << GPIO_AFRH_AFSEL8_Pos)
     
    #define GPIO_AFRH_AFSEL8_1   (0x2UL << GPIO_AFRH_AFSEL8_Pos)
     
    #define GPIO_AFRH_AFSEL8_2   (0x4UL << GPIO_AFRH_AFSEL8_Pos)
     
    #define GPIO_AFRH_AFSEL8_3   (0x8UL << GPIO_AFRH_AFSEL8_Pos)
     
    #define GPIO_AFRH_AFSEL9_Pos   (4U)
     
    #define GPIO_AFRH_AFSEL9_Msk   (0xFUL << GPIO_AFRH_AFSEL9_Pos)
     
    #define GPIO_AFRH_AFSEL9   GPIO_AFRH_AFSEL9_Msk
     
    #define GPIO_AFRH_AFSEL9_0   (0x1UL << GPIO_AFRH_AFSEL9_Pos)
     
    #define GPIO_AFRH_AFSEL9_1   (0x2UL << GPIO_AFRH_AFSEL9_Pos)
     
    #define GPIO_AFRH_AFSEL9_2   (0x4UL << GPIO_AFRH_AFSEL9_Pos)
     
    #define GPIO_AFRH_AFSEL9_3   (0x8UL << GPIO_AFRH_AFSEL9_Pos)
     
    #define GPIO_AFRH_AFSEL10_Pos   (8U)
     
    #define GPIO_AFRH_AFSEL10_Msk   (0xFUL << GPIO_AFRH_AFSEL10_Pos)
     
    #define GPIO_AFRH_AFSEL10   GPIO_AFRH_AFSEL10_Msk
     
    #define GPIO_AFRH_AFSEL10_0   (0x1UL << GPIO_AFRH_AFSEL10_Pos)
     
    #define GPIO_AFRH_AFSEL10_1   (0x2UL << GPIO_AFRH_AFSEL10_Pos)
     
    #define GPIO_AFRH_AFSEL10_2   (0x4UL << GPIO_AFRH_AFSEL10_Pos)
     
    #define GPIO_AFRH_AFSEL10_3   (0x8UL << GPIO_AFRH_AFSEL10_Pos)
     
    #define GPIO_AFRH_AFSEL11_Pos   (12U)
     
    #define GPIO_AFRH_AFSEL11_Msk   (0xFUL << GPIO_AFRH_AFSEL11_Pos)
     
    #define GPIO_AFRH_AFSEL11   GPIO_AFRH_AFSEL11_Msk
     
    #define GPIO_AFRH_AFSEL11_0   (0x1UL << GPIO_AFRH_AFSEL11_Pos)
     
    #define GPIO_AFRH_AFSEL11_1   (0x2UL << GPIO_AFRH_AFSEL11_Pos)
     
    #define GPIO_AFRH_AFSEL11_2   (0x4UL << GPIO_AFRH_AFSEL11_Pos)
     
    #define GPIO_AFRH_AFSEL11_3   (0x8UL << GPIO_AFRH_AFSEL11_Pos)
     
    #define GPIO_AFRH_AFSEL12_Pos   (16U)
     
    #define GPIO_AFRH_AFSEL12_Msk   (0xFUL << GPIO_AFRH_AFSEL12_Pos)
     
    #define GPIO_AFRH_AFSEL12   GPIO_AFRH_AFSEL12_Msk
     
    #define GPIO_AFRH_AFSEL12_0   (0x1UL << GPIO_AFRH_AFSEL12_Pos)
     
    #define GPIO_AFRH_AFSEL12_1   (0x2UL << GPIO_AFRH_AFSEL12_Pos)
     
    #define GPIO_AFRH_AFSEL12_2   (0x4UL << GPIO_AFRH_AFSEL12_Pos)
     
    #define GPIO_AFRH_AFSEL12_3   (0x8UL << GPIO_AFRH_AFSEL12_Pos)
     
    #define GPIO_AFRH_AFSEL13_Pos   (20U)
     
    #define GPIO_AFRH_AFSEL13_Msk   (0xFUL << GPIO_AFRH_AFSEL13_Pos)
     
    #define GPIO_AFRH_AFSEL13   GPIO_AFRH_AFSEL13_Msk
     
    #define GPIO_AFRH_AFSEL13_0   (0x1UL << GPIO_AFRH_AFSEL13_Pos)
     
    #define GPIO_AFRH_AFSEL13_1   (0x2UL << GPIO_AFRH_AFSEL13_Pos)
     
    #define GPIO_AFRH_AFSEL13_2   (0x4UL << GPIO_AFRH_AFSEL13_Pos)
     
    #define GPIO_AFRH_AFSEL13_3   (0x8UL << GPIO_AFRH_AFSEL13_Pos)
     
    #define GPIO_AFRH_AFSEL14_Pos   (24U)
     
    #define GPIO_AFRH_AFSEL14_Msk   (0xFUL << GPIO_AFRH_AFSEL14_Pos)
     
    #define GPIO_AFRH_AFSEL14   GPIO_AFRH_AFSEL14_Msk
     
    #define GPIO_AFRH_AFSEL14_0   (0x1UL << GPIO_AFRH_AFSEL14_Pos)
     
    #define GPIO_AFRH_AFSEL14_1   (0x2UL << GPIO_AFRH_AFSEL14_Pos)
     
    #define GPIO_AFRH_AFSEL14_2   (0x4UL << GPIO_AFRH_AFSEL14_Pos)
     
    #define GPIO_AFRH_AFSEL14_3   (0x8UL << GPIO_AFRH_AFSEL14_Pos)
     
    #define GPIO_AFRH_AFSEL15_Pos   (28U)
     
    #define GPIO_AFRH_AFSEL15_Msk   (0xFUL << GPIO_AFRH_AFSEL15_Pos)
     
    #define GPIO_AFRH_AFSEL15   GPIO_AFRH_AFSEL15_Msk
     
    #define GPIO_AFRH_AFSEL15_0   (0x1UL << GPIO_AFRH_AFSEL15_Pos)
     
    #define GPIO_AFRH_AFSEL15_1   (0x2UL << GPIO_AFRH_AFSEL15_Pos)
     
    #define GPIO_AFRH_AFSEL15_2   (0x4UL << GPIO_AFRH_AFSEL15_Pos)
     
    #define GPIO_AFRH_AFSEL15_3   (0x8UL << GPIO_AFRH_AFSEL15_Pos)
     
    #define GPIO_AFRH_AFRH0   GPIO_AFRH_AFSEL8
     
    #define GPIO_AFRH_AFRH0_0   GPIO_AFRH_AFSEL8_0
     
    #define GPIO_AFRH_AFRH0_1   GPIO_AFRH_AFSEL8_1
     
    #define GPIO_AFRH_AFRH0_2   GPIO_AFRH_AFSEL8_2
     
    #define GPIO_AFRH_AFRH0_3   GPIO_AFRH_AFSEL8_3
     
    #define GPIO_AFRH_AFRH1   GPIO_AFRH_AFSEL9
     
    #define GPIO_AFRH_AFRH1_0   GPIO_AFRH_AFSEL9_0
     
    #define GPIO_AFRH_AFRH1_1   GPIO_AFRH_AFSEL9_1
     
    #define GPIO_AFRH_AFRH1_2   GPIO_AFRH_AFSEL9_2
     
    #define GPIO_AFRH_AFRH1_3   GPIO_AFRH_AFSEL9_3
     
    #define GPIO_AFRH_AFRH2   GPIO_AFRH_AFSEL10
     
    #define GPIO_AFRH_AFRH2_0   GPIO_AFRH_AFSEL10_0
     
    #define GPIO_AFRH_AFRH2_1   GPIO_AFRH_AFSEL10_1
     
    #define GPIO_AFRH_AFRH2_2   GPIO_AFRH_AFSEL10_2
     
    #define GPIO_AFRH_AFRH2_3   GPIO_AFRH_AFSEL10_3
     
    #define GPIO_AFRH_AFRH3   GPIO_AFRH_AFSEL11
     
    #define GPIO_AFRH_AFRH3_0   GPIO_AFRH_AFSEL11_0
     
    #define GPIO_AFRH_AFRH3_1   GPIO_AFRH_AFSEL11_1
     
    #define GPIO_AFRH_AFRH3_2   GPIO_AFRH_AFSEL11_2
     
    #define GPIO_AFRH_AFRH3_3   GPIO_AFRH_AFSEL11_3
     
    #define GPIO_AFRH_AFRH4   GPIO_AFRH_AFSEL12
     
    #define GPIO_AFRH_AFRH4_0   GPIO_AFRH_AFSEL12_0
     
    #define GPIO_AFRH_AFRH4_1   GPIO_AFRH_AFSEL12_1
     
    #define GPIO_AFRH_AFRH4_2   GPIO_AFRH_AFSEL12_2
     
    #define GPIO_AFRH_AFRH4_3   GPIO_AFRH_AFSEL12_3
     
    #define GPIO_AFRH_AFRH5   GPIO_AFRH_AFSEL13
     
    #define GPIO_AFRH_AFRH5_0   GPIO_AFRH_AFSEL13_0
     
    #define GPIO_AFRH_AFRH5_1   GPIO_AFRH_AFSEL13_1
     
    #define GPIO_AFRH_AFRH5_2   GPIO_AFRH_AFSEL13_2
     
    #define GPIO_AFRH_AFRH5_3   GPIO_AFRH_AFSEL13_3
     
    #define GPIO_AFRH_AFRH6   GPIO_AFRH_AFSEL14
     
    #define GPIO_AFRH_AFRH6_0   GPIO_AFRH_AFSEL14_0
     
    #define GPIO_AFRH_AFRH6_1   GPIO_AFRH_AFSEL14_1
     
    #define GPIO_AFRH_AFRH6_2   GPIO_AFRH_AFSEL14_2
     
    #define GPIO_AFRH_AFRH6_3   GPIO_AFRH_AFSEL14_3
     
    #define GPIO_AFRH_AFRH7   GPIO_AFRH_AFSEL15
     
    #define GPIO_AFRH_AFRH7_0   GPIO_AFRH_AFSEL15_0
     
    #define GPIO_AFRH_AFRH7_1   GPIO_AFRH_AFSEL15_1
     
    #define GPIO_AFRH_AFRH7_2   GPIO_AFRH_AFSEL15_2
     
    #define GPIO_AFRH_AFRH7_3   GPIO_AFRH_AFSEL15_3
     
    #define I2C_CR1_PE_Pos   (0U)
     
    #define I2C_CR1_PE_Msk   (0x1UL << I2C_CR1_PE_Pos)
     
    #define I2C_CR1_PE   I2C_CR1_PE_Msk
     
    #define I2C_CR1_SMBUS_Pos   (1U)
     
    #define I2C_CR1_SMBUS_Msk   (0x1UL << I2C_CR1_SMBUS_Pos)
     
    #define I2C_CR1_SMBUS   I2C_CR1_SMBUS_Msk
     
    #define I2C_CR1_SMBTYPE_Pos   (3U)
     
    #define I2C_CR1_SMBTYPE_Msk   (0x1UL << I2C_CR1_SMBTYPE_Pos)
     
    #define I2C_CR1_SMBTYPE   I2C_CR1_SMBTYPE_Msk
     
    #define I2C_CR1_ENARP_Pos   (4U)
     
    #define I2C_CR1_ENARP_Msk   (0x1UL << I2C_CR1_ENARP_Pos)
     
    #define I2C_CR1_ENARP   I2C_CR1_ENARP_Msk
     
    #define I2C_CR1_ENPEC_Pos   (5U)
     
    #define I2C_CR1_ENPEC_Msk   (0x1UL << I2C_CR1_ENPEC_Pos)
     
    #define I2C_CR1_ENPEC   I2C_CR1_ENPEC_Msk
     
    #define I2C_CR1_ENGC_Pos   (6U)
     
    #define I2C_CR1_ENGC_Msk   (0x1UL << I2C_CR1_ENGC_Pos)
     
    #define I2C_CR1_ENGC   I2C_CR1_ENGC_Msk
     
    #define I2C_CR1_NOSTRETCH_Pos   (7U)
     
    #define I2C_CR1_NOSTRETCH_Msk   (0x1UL << I2C_CR1_NOSTRETCH_Pos)
     
    #define I2C_CR1_NOSTRETCH   I2C_CR1_NOSTRETCH_Msk
     
    #define I2C_CR1_START_Pos   (8U)
     
    #define I2C_CR1_START_Msk   (0x1UL << I2C_CR1_START_Pos)
     
    #define I2C_CR1_START   I2C_CR1_START_Msk
     
    #define I2C_CR1_STOP_Pos   (9U)
     
    #define I2C_CR1_STOP_Msk   (0x1UL << I2C_CR1_STOP_Pos)
     
    #define I2C_CR1_STOP   I2C_CR1_STOP_Msk
     
    #define I2C_CR1_ACK_Pos   (10U)
     
    #define I2C_CR1_ACK_Msk   (0x1UL << I2C_CR1_ACK_Pos)
     
    #define I2C_CR1_ACK   I2C_CR1_ACK_Msk
     
    #define I2C_CR1_POS_Pos   (11U)
     
    #define I2C_CR1_POS_Msk   (0x1UL << I2C_CR1_POS_Pos)
     
    #define I2C_CR1_POS   I2C_CR1_POS_Msk
     
    #define I2C_CR1_PEC_Pos   (12U)
     
    #define I2C_CR1_PEC_Msk   (0x1UL << I2C_CR1_PEC_Pos)
     
    #define I2C_CR1_PEC   I2C_CR1_PEC_Msk
     
    #define I2C_CR1_ALERT_Pos   (13U)
     
    #define I2C_CR1_ALERT_Msk   (0x1UL << I2C_CR1_ALERT_Pos)
     
    #define I2C_CR1_ALERT   I2C_CR1_ALERT_Msk
     
    #define I2C_CR1_SWRST_Pos   (15U)
     
    #define I2C_CR1_SWRST_Msk   (0x1UL << I2C_CR1_SWRST_Pos)
     
    #define I2C_CR1_SWRST   I2C_CR1_SWRST_Msk
     
    #define I2C_CR2_FREQ_Pos   (0U)
     
    #define I2C_CR2_FREQ_Msk   (0x3FUL << I2C_CR2_FREQ_Pos)
     
    #define I2C_CR2_FREQ   I2C_CR2_FREQ_Msk
     
    #define I2C_CR2_FREQ_0   (0x01UL << I2C_CR2_FREQ_Pos)
     
    #define I2C_CR2_FREQ_1   (0x02UL << I2C_CR2_FREQ_Pos)
     
    #define I2C_CR2_FREQ_2   (0x04UL << I2C_CR2_FREQ_Pos)
     
    #define I2C_CR2_FREQ_3   (0x08UL << I2C_CR2_FREQ_Pos)
     
    #define I2C_CR2_FREQ_4   (0x10UL << I2C_CR2_FREQ_Pos)
     
    #define I2C_CR2_FREQ_5   (0x20UL << I2C_CR2_FREQ_Pos)
     
    #define I2C_CR2_ITERREN_Pos   (8U)
     
    #define I2C_CR2_ITERREN_Msk   (0x1UL << I2C_CR2_ITERREN_Pos)
     
    #define I2C_CR2_ITERREN   I2C_CR2_ITERREN_Msk
     
    #define I2C_CR2_ITEVTEN_Pos   (9U)
     
    #define I2C_CR2_ITEVTEN_Msk   (0x1UL << I2C_CR2_ITEVTEN_Pos)
     
    #define I2C_CR2_ITEVTEN   I2C_CR2_ITEVTEN_Msk
     
    #define I2C_CR2_ITBUFEN_Pos   (10U)
     
    #define I2C_CR2_ITBUFEN_Msk   (0x1UL << I2C_CR2_ITBUFEN_Pos)
     
    #define I2C_CR2_ITBUFEN   I2C_CR2_ITBUFEN_Msk
     
    #define I2C_CR2_DMAEN_Pos   (11U)
     
    #define I2C_CR2_DMAEN_Msk   (0x1UL << I2C_CR2_DMAEN_Pos)
     
    #define I2C_CR2_DMAEN   I2C_CR2_DMAEN_Msk
     
    #define I2C_CR2_LAST_Pos   (12U)
     
    #define I2C_CR2_LAST_Msk   (0x1UL << I2C_CR2_LAST_Pos)
     
    #define I2C_CR2_LAST   I2C_CR2_LAST_Msk
     
    #define I2C_OAR1_ADD1_7   0x000000FEU
     
    #define I2C_OAR1_ADD8_9   0x00000300U
     
    #define I2C_OAR1_ADD0_Pos   (0U)
     
    #define I2C_OAR1_ADD0_Msk   (0x1UL << I2C_OAR1_ADD0_Pos)
     
    #define I2C_OAR1_ADD0   I2C_OAR1_ADD0_Msk
     
    #define I2C_OAR1_ADD1_Pos   (1U)
     
    #define I2C_OAR1_ADD1_Msk   (0x1UL << I2C_OAR1_ADD1_Pos)
     
    #define I2C_OAR1_ADD1   I2C_OAR1_ADD1_Msk
     
    #define I2C_OAR1_ADD2_Pos   (2U)
     
    #define I2C_OAR1_ADD2_Msk   (0x1UL << I2C_OAR1_ADD2_Pos)
     
    #define I2C_OAR1_ADD2   I2C_OAR1_ADD2_Msk
     
    #define I2C_OAR1_ADD3_Pos   (3U)
     
    #define I2C_OAR1_ADD3_Msk   (0x1UL << I2C_OAR1_ADD3_Pos)
     
    #define I2C_OAR1_ADD3   I2C_OAR1_ADD3_Msk
     
    #define I2C_OAR1_ADD4_Pos   (4U)
     
    #define I2C_OAR1_ADD4_Msk   (0x1UL << I2C_OAR1_ADD4_Pos)
     
    #define I2C_OAR1_ADD4   I2C_OAR1_ADD4_Msk
     
    #define I2C_OAR1_ADD5_Pos   (5U)
     
    #define I2C_OAR1_ADD5_Msk   (0x1UL << I2C_OAR1_ADD5_Pos)
     
    #define I2C_OAR1_ADD5   I2C_OAR1_ADD5_Msk
     
    #define I2C_OAR1_ADD6_Pos   (6U)
     
    #define I2C_OAR1_ADD6_Msk   (0x1UL << I2C_OAR1_ADD6_Pos)
     
    #define I2C_OAR1_ADD6   I2C_OAR1_ADD6_Msk
     
    #define I2C_OAR1_ADD7_Pos   (7U)
     
    #define I2C_OAR1_ADD7_Msk   (0x1UL << I2C_OAR1_ADD7_Pos)
     
    #define I2C_OAR1_ADD7   I2C_OAR1_ADD7_Msk
     
    #define I2C_OAR1_ADD8_Pos   (8U)
     
    #define I2C_OAR1_ADD8_Msk   (0x1UL << I2C_OAR1_ADD8_Pos)
     
    #define I2C_OAR1_ADD8   I2C_OAR1_ADD8_Msk
     
    #define I2C_OAR1_ADD9_Pos   (9U)
     
    #define I2C_OAR1_ADD9_Msk   (0x1UL << I2C_OAR1_ADD9_Pos)
     
    #define I2C_OAR1_ADD9   I2C_OAR1_ADD9_Msk
     
    #define I2C_OAR1_ADDMODE_Pos   (15U)
     
    #define I2C_OAR1_ADDMODE_Msk   (0x1UL << I2C_OAR1_ADDMODE_Pos)
     
    #define I2C_OAR1_ADDMODE   I2C_OAR1_ADDMODE_Msk
     
    #define I2C_OAR2_ENDUAL_Pos   (0U)
     
    #define I2C_OAR2_ENDUAL_Msk   (0x1UL << I2C_OAR2_ENDUAL_Pos)
     
    #define I2C_OAR2_ENDUAL   I2C_OAR2_ENDUAL_Msk
     
    #define I2C_OAR2_ADD2_Pos   (1U)
     
    #define I2C_OAR2_ADD2_Msk   (0x7FUL << I2C_OAR2_ADD2_Pos)
     
    #define I2C_OAR2_ADD2   I2C_OAR2_ADD2_Msk
     
    #define I2C_DR_DR_Pos   (0U)
     
    #define I2C_DR_DR_Msk   (0xFFUL << I2C_DR_DR_Pos)
     
    #define I2C_DR_DR   I2C_DR_DR_Msk
     
    #define I2C_SR1_SB_Pos   (0U)
     
    #define I2C_SR1_SB_Msk   (0x1UL << I2C_SR1_SB_Pos)
     
    #define I2C_SR1_SB   I2C_SR1_SB_Msk
     
    #define I2C_SR1_ADDR_Pos   (1U)
     
    #define I2C_SR1_ADDR_Msk   (0x1UL << I2C_SR1_ADDR_Pos)
     
    #define I2C_SR1_ADDR   I2C_SR1_ADDR_Msk
     
    #define I2C_SR1_BTF_Pos   (2U)
     
    #define I2C_SR1_BTF_Msk   (0x1UL << I2C_SR1_BTF_Pos)
     
    #define I2C_SR1_BTF   I2C_SR1_BTF_Msk
     
    #define I2C_SR1_ADD10_Pos   (3U)
     
    #define I2C_SR1_ADD10_Msk   (0x1UL << I2C_SR1_ADD10_Pos)
     
    #define I2C_SR1_ADD10   I2C_SR1_ADD10_Msk
     
    #define I2C_SR1_STOPF_Pos   (4U)
     
    #define I2C_SR1_STOPF_Msk   (0x1UL << I2C_SR1_STOPF_Pos)
     
    #define I2C_SR1_STOPF   I2C_SR1_STOPF_Msk
     
    #define I2C_SR1_RXNE_Pos   (6U)
     
    #define I2C_SR1_RXNE_Msk   (0x1UL << I2C_SR1_RXNE_Pos)
     
    #define I2C_SR1_RXNE   I2C_SR1_RXNE_Msk
     
    #define I2C_SR1_TXE_Pos   (7U)
     
    #define I2C_SR1_TXE_Msk   (0x1UL << I2C_SR1_TXE_Pos)
     
    #define I2C_SR1_TXE   I2C_SR1_TXE_Msk
     
    #define I2C_SR1_BERR_Pos   (8U)
     
    #define I2C_SR1_BERR_Msk   (0x1UL << I2C_SR1_BERR_Pos)
     
    #define I2C_SR1_BERR   I2C_SR1_BERR_Msk
     
    #define I2C_SR1_ARLO_Pos   (9U)
     
    #define I2C_SR1_ARLO_Msk   (0x1UL << I2C_SR1_ARLO_Pos)
     
    #define I2C_SR1_ARLO   I2C_SR1_ARLO_Msk
     
    #define I2C_SR1_AF_Pos   (10U)
     
    #define I2C_SR1_AF_Msk   (0x1UL << I2C_SR1_AF_Pos)
     
    #define I2C_SR1_AF   I2C_SR1_AF_Msk
     
    #define I2C_SR1_OVR_Pos   (11U)
     
    #define I2C_SR1_OVR_Msk   (0x1UL << I2C_SR1_OVR_Pos)
     
    #define I2C_SR1_OVR   I2C_SR1_OVR_Msk
     
    #define I2C_SR1_PECERR_Pos   (12U)
     
    #define I2C_SR1_PECERR_Msk   (0x1UL << I2C_SR1_PECERR_Pos)
     
    #define I2C_SR1_PECERR   I2C_SR1_PECERR_Msk
     
    #define I2C_SR1_TIMEOUT_Pos   (14U)
     
    #define I2C_SR1_TIMEOUT_Msk   (0x1UL << I2C_SR1_TIMEOUT_Pos)
     
    #define I2C_SR1_TIMEOUT   I2C_SR1_TIMEOUT_Msk
     
    #define I2C_SR1_SMBALERT_Pos   (15U)
     
    #define I2C_SR1_SMBALERT_Msk   (0x1UL << I2C_SR1_SMBALERT_Pos)
     
    #define I2C_SR1_SMBALERT   I2C_SR1_SMBALERT_Msk
     
    #define I2C_SR2_MSL_Pos   (0U)
     
    #define I2C_SR2_MSL_Msk   (0x1UL << I2C_SR2_MSL_Pos)
     
    #define I2C_SR2_MSL   I2C_SR2_MSL_Msk
     
    #define I2C_SR2_BUSY_Pos   (1U)
     
    #define I2C_SR2_BUSY_Msk   (0x1UL << I2C_SR2_BUSY_Pos)
     
    #define I2C_SR2_BUSY   I2C_SR2_BUSY_Msk
     
    #define I2C_SR2_TRA_Pos   (2U)
     
    #define I2C_SR2_TRA_Msk   (0x1UL << I2C_SR2_TRA_Pos)
     
    #define I2C_SR2_TRA   I2C_SR2_TRA_Msk
     
    #define I2C_SR2_GENCALL_Pos   (4U)
     
    #define I2C_SR2_GENCALL_Msk   (0x1UL << I2C_SR2_GENCALL_Pos)
     
    #define I2C_SR2_GENCALL   I2C_SR2_GENCALL_Msk
     
    #define I2C_SR2_SMBDEFAULT_Pos   (5U)
     
    #define I2C_SR2_SMBDEFAULT_Msk   (0x1UL << I2C_SR2_SMBDEFAULT_Pos)
     
    #define I2C_SR2_SMBDEFAULT   I2C_SR2_SMBDEFAULT_Msk
     
    #define I2C_SR2_SMBHOST_Pos   (6U)
     
    #define I2C_SR2_SMBHOST_Msk   (0x1UL << I2C_SR2_SMBHOST_Pos)
     
    #define I2C_SR2_SMBHOST   I2C_SR2_SMBHOST_Msk
     
    #define I2C_SR2_DUALF_Pos   (7U)
     
    #define I2C_SR2_DUALF_Msk   (0x1UL << I2C_SR2_DUALF_Pos)
     
    #define I2C_SR2_DUALF   I2C_SR2_DUALF_Msk
     
    #define I2C_SR2_PEC_Pos   (8U)
     
    #define I2C_SR2_PEC_Msk   (0xFFUL << I2C_SR2_PEC_Pos)
     
    #define I2C_SR2_PEC   I2C_SR2_PEC_Msk
     
    #define I2C_CCR_CCR_Pos   (0U)
     
    #define I2C_CCR_CCR_Msk   (0xFFFUL << I2C_CCR_CCR_Pos)
     
    #define I2C_CCR_CCR   I2C_CCR_CCR_Msk
     
    #define I2C_CCR_DUTY_Pos   (14U)
     
    #define I2C_CCR_DUTY_Msk   (0x1UL << I2C_CCR_DUTY_Pos)
     
    #define I2C_CCR_DUTY   I2C_CCR_DUTY_Msk
     
    #define I2C_CCR_FS_Pos   (15U)
     
    #define I2C_CCR_FS_Msk   (0x1UL << I2C_CCR_FS_Pos)
     
    #define I2C_CCR_FS   I2C_CCR_FS_Msk
     
    #define I2C_TRISE_TRISE_Pos   (0U)
     
    #define I2C_TRISE_TRISE_Msk   (0x3FUL << I2C_TRISE_TRISE_Pos)
     
    #define I2C_TRISE_TRISE   I2C_TRISE_TRISE_Msk
     
    #define IWDG_KR_KEY_Pos   (0U)
     
    #define IWDG_KR_KEY_Msk   (0xFFFFUL << IWDG_KR_KEY_Pos)
     
    #define IWDG_KR_KEY   IWDG_KR_KEY_Msk
     
    #define IWDG_PR_PR_Pos   (0U)
     
    #define IWDG_PR_PR_Msk   (0x7UL << IWDG_PR_PR_Pos)
     
    #define IWDG_PR_PR   IWDG_PR_PR_Msk
     
    #define IWDG_PR_PR_0   (0x1UL << IWDG_PR_PR_Pos)
     
    #define IWDG_PR_PR_1   (0x2UL << IWDG_PR_PR_Pos)
     
    #define IWDG_PR_PR_2   (0x4UL << IWDG_PR_PR_Pos)
     
    #define IWDG_RLR_RL_Pos   (0U)
     
    #define IWDG_RLR_RL_Msk   (0xFFFUL << IWDG_RLR_RL_Pos)
     
    #define IWDG_RLR_RL   IWDG_RLR_RL_Msk
     
    #define IWDG_SR_PVU_Pos   (0U)
     
    #define IWDG_SR_PVU_Msk   (0x1UL << IWDG_SR_PVU_Pos)
     
    #define IWDG_SR_PVU   IWDG_SR_PVU_Msk
     
    #define IWDG_SR_RVU_Pos   (1U)
     
    #define IWDG_SR_RVU_Msk   (0x1UL << IWDG_SR_RVU_Pos)
     
    #define IWDG_SR_RVU   IWDG_SR_RVU_Msk
     
    #define PWR_CR_LPDS_Pos   (0U)
     
    #define PWR_CR_LPDS_Msk   (0x1UL << PWR_CR_LPDS_Pos)
     
    #define PWR_CR_LPDS   PWR_CR_LPDS_Msk
     
    #define PWR_CR_PDDS_Pos   (1U)
     
    #define PWR_CR_PDDS_Msk   (0x1UL << PWR_CR_PDDS_Pos)
     
    #define PWR_CR_PDDS   PWR_CR_PDDS_Msk
     
    #define PWR_CR_CWUF_Pos   (2U)
     
    #define PWR_CR_CWUF_Msk   (0x1UL << PWR_CR_CWUF_Pos)
     
    #define PWR_CR_CWUF   PWR_CR_CWUF_Msk
     
    #define PWR_CR_CSBF_Pos   (3U)
     
    #define PWR_CR_CSBF_Msk   (0x1UL << PWR_CR_CSBF_Pos)
     
    #define PWR_CR_CSBF   PWR_CR_CSBF_Msk
     
    #define PWR_CR_PVDE_Pos   (4U)
     
    #define PWR_CR_PVDE_Msk   (0x1UL << PWR_CR_PVDE_Pos)
     
    #define PWR_CR_PVDE   PWR_CR_PVDE_Msk
     
    #define PWR_CR_PLS_Pos   (5U)
     
    #define PWR_CR_PLS_Msk   (0x7UL << PWR_CR_PLS_Pos)
     
    #define PWR_CR_PLS   PWR_CR_PLS_Msk
     
    #define PWR_CR_PLS_0   (0x1UL << PWR_CR_PLS_Pos)
     
    #define PWR_CR_PLS_1   (0x2UL << PWR_CR_PLS_Pos)
     
    #define PWR_CR_PLS_2   (0x4UL << PWR_CR_PLS_Pos)
     
    #define PWR_CR_PLS_LEV0   0x00000000U
     
    #define PWR_CR_PLS_LEV1   0x00000020U
     
    #define PWR_CR_PLS_LEV2   0x00000040U
     
    #define PWR_CR_PLS_LEV3   0x00000060U
     
    #define PWR_CR_PLS_LEV4   0x00000080U
     
    #define PWR_CR_PLS_LEV5   0x000000A0U
     
    #define PWR_CR_PLS_LEV6   0x000000C0U
     
    #define PWR_CR_PLS_LEV7   0x000000E0U
     
    #define PWR_CR_DBP_Pos   (8U)
     
    #define PWR_CR_DBP_Msk   (0x1UL << PWR_CR_DBP_Pos)
     
    #define PWR_CR_DBP   PWR_CR_DBP_Msk
     
    #define PWR_CR_FPDS_Pos   (9U)
     
    #define PWR_CR_FPDS_Msk   (0x1UL << PWR_CR_FPDS_Pos)
     
    #define PWR_CR_FPDS   PWR_CR_FPDS_Msk
     
    #define PWR_CR_VOS_Pos   (14U)
     
    #define PWR_CR_VOS_Msk   (0x1UL << PWR_CR_VOS_Pos)
     
    #define PWR_CR_VOS   PWR_CR_VOS_Msk
     
    #define PWR_CR_PMODE   PWR_CR_VOS
     
    #define PWR_CSR_WUF_Pos   (0U)
     
    #define PWR_CSR_WUF_Msk   (0x1UL << PWR_CSR_WUF_Pos)
     
    #define PWR_CSR_WUF   PWR_CSR_WUF_Msk
     
    #define PWR_CSR_SBF_Pos   (1U)
     
    #define PWR_CSR_SBF_Msk   (0x1UL << PWR_CSR_SBF_Pos)
     
    #define PWR_CSR_SBF   PWR_CSR_SBF_Msk
     
    #define PWR_CSR_PVDO_Pos   (2U)
     
    #define PWR_CSR_PVDO_Msk   (0x1UL << PWR_CSR_PVDO_Pos)
     
    #define PWR_CSR_PVDO   PWR_CSR_PVDO_Msk
     
    #define PWR_CSR_BRR_Pos   (3U)
     
    #define PWR_CSR_BRR_Msk   (0x1UL << PWR_CSR_BRR_Pos)
     
    #define PWR_CSR_BRR   PWR_CSR_BRR_Msk
     
    #define PWR_CSR_EWUP_Pos   (8U)
     
    #define PWR_CSR_EWUP_Msk   (0x1UL << PWR_CSR_EWUP_Pos)
     
    #define PWR_CSR_EWUP   PWR_CSR_EWUP_Msk
     
    #define PWR_CSR_BRE_Pos   (9U)
     
    #define PWR_CSR_BRE_Msk   (0x1UL << PWR_CSR_BRE_Pos)
     
    #define PWR_CSR_BRE   PWR_CSR_BRE_Msk
     
    #define PWR_CSR_VOSRDY_Pos   (14U)
     
    #define PWR_CSR_VOSRDY_Msk   (0x1UL << PWR_CSR_VOSRDY_Pos)
     
    #define PWR_CSR_VOSRDY   PWR_CSR_VOSRDY_Msk
     
    #define PWR_CSR_REGRDY   PWR_CSR_VOSRDY
     
    #define RCC_CR_HSION_Pos   (0U)
     
    #define RCC_CR_HSION_Msk   (0x1UL << RCC_CR_HSION_Pos)
     
    #define RCC_CR_HSION   RCC_CR_HSION_Msk
     
    #define RCC_CR_HSIRDY_Pos   (1U)
     
    #define RCC_CR_HSIRDY_Msk   (0x1UL << RCC_CR_HSIRDY_Pos)
     
    #define RCC_CR_HSIRDY   RCC_CR_HSIRDY_Msk
     
    #define RCC_CR_HSITRIM_Pos   (3U)
     
    #define RCC_CR_HSITRIM_Msk   (0x1FUL << RCC_CR_HSITRIM_Pos)
     
    #define RCC_CR_HSITRIM   RCC_CR_HSITRIM_Msk
     
    #define RCC_CR_HSITRIM_0   (0x01UL << RCC_CR_HSITRIM_Pos)
     
    #define RCC_CR_HSITRIM_1   (0x02UL << RCC_CR_HSITRIM_Pos)
     
    #define RCC_CR_HSITRIM_2   (0x04UL << RCC_CR_HSITRIM_Pos)
     
    #define RCC_CR_HSITRIM_3   (0x08UL << RCC_CR_HSITRIM_Pos)
     
    #define RCC_CR_HSITRIM_4   (0x10UL << RCC_CR_HSITRIM_Pos)
     
    #define RCC_CR_HSICAL_Pos   (8U)
     
    #define RCC_CR_HSICAL_Msk   (0xFFUL << RCC_CR_HSICAL_Pos)
     
    #define RCC_CR_HSICAL   RCC_CR_HSICAL_Msk
     
    #define RCC_CR_HSICAL_0   (0x01UL << RCC_CR_HSICAL_Pos)
     
    #define RCC_CR_HSICAL_1   (0x02UL << RCC_CR_HSICAL_Pos)
     
    #define RCC_CR_HSICAL_2   (0x04UL << RCC_CR_HSICAL_Pos)
     
    #define RCC_CR_HSICAL_3   (0x08UL << RCC_CR_HSICAL_Pos)
     
    #define RCC_CR_HSICAL_4   (0x10UL << RCC_CR_HSICAL_Pos)
     
    #define RCC_CR_HSICAL_5   (0x20UL << RCC_CR_HSICAL_Pos)
     
    #define RCC_CR_HSICAL_6   (0x40UL << RCC_CR_HSICAL_Pos)
     
    #define RCC_CR_HSICAL_7   (0x80UL << RCC_CR_HSICAL_Pos)
     
    #define RCC_CR_HSEON_Pos   (16U)
     
    #define RCC_CR_HSEON_Msk   (0x1UL << RCC_CR_HSEON_Pos)
     
    #define RCC_CR_HSEON   RCC_CR_HSEON_Msk
     
    #define RCC_CR_HSERDY_Pos   (17U)
     
    #define RCC_CR_HSERDY_Msk   (0x1UL << RCC_CR_HSERDY_Pos)
     
    #define RCC_CR_HSERDY   RCC_CR_HSERDY_Msk
     
    #define RCC_CR_HSEBYP_Pos   (18U)
     
    #define RCC_CR_HSEBYP_Msk   (0x1UL << RCC_CR_HSEBYP_Pos)
     
    #define RCC_CR_HSEBYP   RCC_CR_HSEBYP_Msk
     
    #define RCC_CR_CSSON_Pos   (19U)
     
    #define RCC_CR_CSSON_Msk   (0x1UL << RCC_CR_CSSON_Pos)
     
    #define RCC_CR_CSSON   RCC_CR_CSSON_Msk
     
    #define RCC_CR_PLLON_Pos   (24U)
     
    #define RCC_CR_PLLON_Msk   (0x1UL << RCC_CR_PLLON_Pos)
     
    #define RCC_CR_PLLON   RCC_CR_PLLON_Msk
     
    #define RCC_CR_PLLRDY_Pos   (25U)
     
    #define RCC_CR_PLLRDY_Msk   (0x1UL << RCC_CR_PLLRDY_Pos)
     
    #define RCC_CR_PLLRDY   RCC_CR_PLLRDY_Msk
     
    #define RCC_PLLI2S_SUPPORT
     
    #define RCC_CR_PLLI2SON_Pos   (26U)
     
    #define RCC_CR_PLLI2SON_Msk   (0x1UL << RCC_CR_PLLI2SON_Pos)
     
    #define RCC_CR_PLLI2SON   RCC_CR_PLLI2SON_Msk
     
    #define RCC_CR_PLLI2SRDY_Pos   (27U)
     
    #define RCC_CR_PLLI2SRDY_Msk   (0x1UL << RCC_CR_PLLI2SRDY_Pos)
     
    #define RCC_CR_PLLI2SRDY   RCC_CR_PLLI2SRDY_Msk
     
    #define RCC_PLLCFGR_PLLM_Pos   (0U)
     
    #define RCC_PLLCFGR_PLLM_Msk   (0x3FUL << RCC_PLLCFGR_PLLM_Pos)
     
    #define RCC_PLLCFGR_PLLM   RCC_PLLCFGR_PLLM_Msk
     
    #define RCC_PLLCFGR_PLLM_0   (0x01UL << RCC_PLLCFGR_PLLM_Pos)
     
    #define RCC_PLLCFGR_PLLM_1   (0x02UL << RCC_PLLCFGR_PLLM_Pos)
     
    #define RCC_PLLCFGR_PLLM_2   (0x04UL << RCC_PLLCFGR_PLLM_Pos)
     
    #define RCC_PLLCFGR_PLLM_3   (0x08UL << RCC_PLLCFGR_PLLM_Pos)
     
    #define RCC_PLLCFGR_PLLM_4   (0x10UL << RCC_PLLCFGR_PLLM_Pos)
     
    #define RCC_PLLCFGR_PLLM_5   (0x20UL << RCC_PLLCFGR_PLLM_Pos)
     
    #define RCC_PLLCFGR_PLLN_Pos   (6U)
     
    #define RCC_PLLCFGR_PLLN_Msk   (0x1FFUL << RCC_PLLCFGR_PLLN_Pos)
     
    #define RCC_PLLCFGR_PLLN   RCC_PLLCFGR_PLLN_Msk
     
    #define RCC_PLLCFGR_PLLN_0   (0x001UL << RCC_PLLCFGR_PLLN_Pos)
     
    #define RCC_PLLCFGR_PLLN_1   (0x002UL << RCC_PLLCFGR_PLLN_Pos)
     
    #define RCC_PLLCFGR_PLLN_2   (0x004UL << RCC_PLLCFGR_PLLN_Pos)
     
    #define RCC_PLLCFGR_PLLN_3   (0x008UL << RCC_PLLCFGR_PLLN_Pos)
     
    #define RCC_PLLCFGR_PLLN_4   (0x010UL << RCC_PLLCFGR_PLLN_Pos)
     
    #define RCC_PLLCFGR_PLLN_5   (0x020UL << RCC_PLLCFGR_PLLN_Pos)
     
    #define RCC_PLLCFGR_PLLN_6   (0x040UL << RCC_PLLCFGR_PLLN_Pos)
     
    #define RCC_PLLCFGR_PLLN_7   (0x080UL << RCC_PLLCFGR_PLLN_Pos)
     
    #define RCC_PLLCFGR_PLLN_8   (0x100UL << RCC_PLLCFGR_PLLN_Pos)
     
    #define RCC_PLLCFGR_PLLP_Pos   (16U)
     
    #define RCC_PLLCFGR_PLLP_Msk   (0x3UL << RCC_PLLCFGR_PLLP_Pos)
     
    #define RCC_PLLCFGR_PLLP   RCC_PLLCFGR_PLLP_Msk
     
    #define RCC_PLLCFGR_PLLP_0   (0x1UL << RCC_PLLCFGR_PLLP_Pos)
     
    #define RCC_PLLCFGR_PLLP_1   (0x2UL << RCC_PLLCFGR_PLLP_Pos)
     
    #define RCC_PLLCFGR_PLLSRC_Pos   (22U)
     
    #define RCC_PLLCFGR_PLLSRC_Msk   (0x1UL << RCC_PLLCFGR_PLLSRC_Pos)
     
    #define RCC_PLLCFGR_PLLSRC   RCC_PLLCFGR_PLLSRC_Msk
     
    #define RCC_PLLCFGR_PLLSRC_HSE_Pos   (22U)
     
    #define RCC_PLLCFGR_PLLSRC_HSE_Msk   (0x1UL << RCC_PLLCFGR_PLLSRC_HSE_Pos)
     
    #define RCC_PLLCFGR_PLLSRC_HSE   RCC_PLLCFGR_PLLSRC_HSE_Msk
     
    #define RCC_PLLCFGR_PLLSRC_HSI   0x00000000U
     
    #define RCC_PLLCFGR_PLLQ_Pos   (24U)
     
    #define RCC_PLLCFGR_PLLQ_Msk   (0xFUL << RCC_PLLCFGR_PLLQ_Pos)
     
    #define RCC_PLLCFGR_PLLQ   RCC_PLLCFGR_PLLQ_Msk
     
    #define RCC_PLLCFGR_PLLQ_0   (0x1UL << RCC_PLLCFGR_PLLQ_Pos)
     
    #define RCC_PLLCFGR_PLLQ_1   (0x2UL << RCC_PLLCFGR_PLLQ_Pos)
     
    #define RCC_PLLCFGR_PLLQ_2   (0x4UL << RCC_PLLCFGR_PLLQ_Pos)
     
    #define RCC_PLLCFGR_PLLQ_3   (0x8UL << RCC_PLLCFGR_PLLQ_Pos)
     
    #define RCC_CFGR_SW_Pos   (0U)
     
    #define RCC_CFGR_SW_Msk   (0x3UL << RCC_CFGR_SW_Pos)
     
    #define RCC_CFGR_SW   RCC_CFGR_SW_Msk
     
    #define RCC_CFGR_SW_0   (0x1UL << RCC_CFGR_SW_Pos)
     
    #define RCC_CFGR_SW_1   (0x2UL << RCC_CFGR_SW_Pos)
     
    #define RCC_CFGR_SW_HSI   0x00000000U
     
    #define RCC_CFGR_SW_HSE   0x00000001U
     
    #define RCC_CFGR_SW_PLL   0x00000002U
     
    #define RCC_CFGR_SWS_Pos   (2U)
     
    #define RCC_CFGR_SWS_Msk   (0x3UL << RCC_CFGR_SWS_Pos)
     
    #define RCC_CFGR_SWS   RCC_CFGR_SWS_Msk
     
    #define RCC_CFGR_SWS_0   (0x1UL << RCC_CFGR_SWS_Pos)
     
    #define RCC_CFGR_SWS_1   (0x2UL << RCC_CFGR_SWS_Pos)
     
    #define RCC_CFGR_SWS_HSI   0x00000000U
     
    #define RCC_CFGR_SWS_HSE   0x00000004U
     
    #define RCC_CFGR_SWS_PLL   0x00000008U
     
    #define RCC_CFGR_HPRE_Pos   (4U)
     
    #define RCC_CFGR_HPRE_Msk   (0xFUL << RCC_CFGR_HPRE_Pos)
     
    #define RCC_CFGR_HPRE   RCC_CFGR_HPRE_Msk
     
    #define RCC_CFGR_HPRE_0   (0x1UL << RCC_CFGR_HPRE_Pos)
     
    #define RCC_CFGR_HPRE_1   (0x2UL << RCC_CFGR_HPRE_Pos)
     
    #define RCC_CFGR_HPRE_2   (0x4UL << RCC_CFGR_HPRE_Pos)
     
    #define RCC_CFGR_HPRE_3   (0x8UL << RCC_CFGR_HPRE_Pos)
     
    #define RCC_CFGR_HPRE_DIV1   0x00000000U
     
    #define RCC_CFGR_HPRE_DIV2   0x00000080U
     
    #define RCC_CFGR_HPRE_DIV4   0x00000090U
     
    #define RCC_CFGR_HPRE_DIV8   0x000000A0U
     
    #define RCC_CFGR_HPRE_DIV16   0x000000B0U
     
    #define RCC_CFGR_HPRE_DIV64   0x000000C0U
     
    #define RCC_CFGR_HPRE_DIV128   0x000000D0U
     
    #define RCC_CFGR_HPRE_DIV256   0x000000E0U
     
    #define RCC_CFGR_HPRE_DIV512   0x000000F0U
     
    #define RCC_CFGR_PPRE1_Pos   (10U)
     
    #define RCC_CFGR_PPRE1_Msk   (0x7UL << RCC_CFGR_PPRE1_Pos)
     
    #define RCC_CFGR_PPRE1   RCC_CFGR_PPRE1_Msk
     
    #define RCC_CFGR_PPRE1_0   (0x1UL << RCC_CFGR_PPRE1_Pos)
     
    #define RCC_CFGR_PPRE1_1   (0x2UL << RCC_CFGR_PPRE1_Pos)
     
    #define RCC_CFGR_PPRE1_2   (0x4UL << RCC_CFGR_PPRE1_Pos)
     
    #define RCC_CFGR_PPRE1_DIV1   0x00000000U
     
    #define RCC_CFGR_PPRE1_DIV2   0x00001000U
     
    #define RCC_CFGR_PPRE1_DIV4   0x00001400U
     
    #define RCC_CFGR_PPRE1_DIV8   0x00001800U
     
    #define RCC_CFGR_PPRE1_DIV16   0x00001C00U
     
    #define RCC_CFGR_PPRE2_Pos   (13U)
     
    #define RCC_CFGR_PPRE2_Msk   (0x7UL << RCC_CFGR_PPRE2_Pos)
     
    #define RCC_CFGR_PPRE2   RCC_CFGR_PPRE2_Msk
     
    #define RCC_CFGR_PPRE2_0   (0x1UL << RCC_CFGR_PPRE2_Pos)
     
    #define RCC_CFGR_PPRE2_1   (0x2UL << RCC_CFGR_PPRE2_Pos)
     
    #define RCC_CFGR_PPRE2_2   (0x4UL << RCC_CFGR_PPRE2_Pos)
     
    #define RCC_CFGR_PPRE2_DIV1   0x00000000U
     
    #define RCC_CFGR_PPRE2_DIV2   0x00008000U
     
    #define RCC_CFGR_PPRE2_DIV4   0x0000A000U
     
    #define RCC_CFGR_PPRE2_DIV8   0x0000C000U
     
    #define RCC_CFGR_PPRE2_DIV16   0x0000E000U
     
    #define RCC_CFGR_RTCPRE_Pos   (16U)
     
    #define RCC_CFGR_RTCPRE_Msk   (0x1FUL << RCC_CFGR_RTCPRE_Pos)
     
    #define RCC_CFGR_RTCPRE   RCC_CFGR_RTCPRE_Msk
     
    #define RCC_CFGR_RTCPRE_0   (0x01UL << RCC_CFGR_RTCPRE_Pos)
     
    #define RCC_CFGR_RTCPRE_1   (0x02UL << RCC_CFGR_RTCPRE_Pos)
     
    #define RCC_CFGR_RTCPRE_2   (0x04UL << RCC_CFGR_RTCPRE_Pos)
     
    #define RCC_CFGR_RTCPRE_3   (0x08UL << RCC_CFGR_RTCPRE_Pos)
     
    #define RCC_CFGR_RTCPRE_4   (0x10UL << RCC_CFGR_RTCPRE_Pos)
     
    #define RCC_CFGR_MCO1_Pos   (21U)
     
    #define RCC_CFGR_MCO1_Msk   (0x3UL << RCC_CFGR_MCO1_Pos)
     
    #define RCC_CFGR_MCO1   RCC_CFGR_MCO1_Msk
     
    #define RCC_CFGR_MCO1_0   (0x1UL << RCC_CFGR_MCO1_Pos)
     
    #define RCC_CFGR_MCO1_1   (0x2UL << RCC_CFGR_MCO1_Pos)
     
    #define RCC_CFGR_I2SSRC_Pos   (23U)
     
    #define RCC_CFGR_I2SSRC_Msk   (0x1UL << RCC_CFGR_I2SSRC_Pos)
     
    #define RCC_CFGR_I2SSRC   RCC_CFGR_I2SSRC_Msk
     
    #define RCC_CFGR_MCO1PRE_Pos   (24U)
     
    #define RCC_CFGR_MCO1PRE_Msk   (0x7UL << RCC_CFGR_MCO1PRE_Pos)
     
    #define RCC_CFGR_MCO1PRE   RCC_CFGR_MCO1PRE_Msk
     
    #define RCC_CFGR_MCO1PRE_0   (0x1UL << RCC_CFGR_MCO1PRE_Pos)
     
    #define RCC_CFGR_MCO1PRE_1   (0x2UL << RCC_CFGR_MCO1PRE_Pos)
     
    #define RCC_CFGR_MCO1PRE_2   (0x4UL << RCC_CFGR_MCO1PRE_Pos)
     
    #define RCC_CFGR_MCO2PRE_Pos   (27U)
     
    #define RCC_CFGR_MCO2PRE_Msk   (0x7UL << RCC_CFGR_MCO2PRE_Pos)
     
    #define RCC_CFGR_MCO2PRE   RCC_CFGR_MCO2PRE_Msk
     
    #define RCC_CFGR_MCO2PRE_0   (0x1UL << RCC_CFGR_MCO2PRE_Pos)
     
    #define RCC_CFGR_MCO2PRE_1   (0x2UL << RCC_CFGR_MCO2PRE_Pos)
     
    #define RCC_CFGR_MCO2PRE_2   (0x4UL << RCC_CFGR_MCO2PRE_Pos)
     
    #define RCC_CFGR_MCO2_Pos   (30U)
     
    #define RCC_CFGR_MCO2_Msk   (0x3UL << RCC_CFGR_MCO2_Pos)
     
    #define RCC_CFGR_MCO2   RCC_CFGR_MCO2_Msk
     
    #define RCC_CFGR_MCO2_0   (0x1UL << RCC_CFGR_MCO2_Pos)
     
    #define RCC_CFGR_MCO2_1   (0x2UL << RCC_CFGR_MCO2_Pos)
     
    #define RCC_CIR_LSIRDYF_Pos   (0U)
     
    #define RCC_CIR_LSIRDYF_Msk   (0x1UL << RCC_CIR_LSIRDYF_Pos)
     
    #define RCC_CIR_LSIRDYF   RCC_CIR_LSIRDYF_Msk
     
    #define RCC_CIR_LSERDYF_Pos   (1U)
     
    #define RCC_CIR_LSERDYF_Msk   (0x1UL << RCC_CIR_LSERDYF_Pos)
     
    #define RCC_CIR_LSERDYF   RCC_CIR_LSERDYF_Msk
     
    #define RCC_CIR_HSIRDYF_Pos   (2U)
     
    #define RCC_CIR_HSIRDYF_Msk   (0x1UL << RCC_CIR_HSIRDYF_Pos)
     
    #define RCC_CIR_HSIRDYF   RCC_CIR_HSIRDYF_Msk
     
    #define RCC_CIR_HSERDYF_Pos   (3U)
     
    #define RCC_CIR_HSERDYF_Msk   (0x1UL << RCC_CIR_HSERDYF_Pos)
     
    #define RCC_CIR_HSERDYF   RCC_CIR_HSERDYF_Msk
     
    #define RCC_CIR_PLLRDYF_Pos   (4U)
     
    #define RCC_CIR_PLLRDYF_Msk   (0x1UL << RCC_CIR_PLLRDYF_Pos)
     
    #define RCC_CIR_PLLRDYF   RCC_CIR_PLLRDYF_Msk
     
    #define RCC_CIR_PLLI2SRDYF_Pos   (5U)
     
    #define RCC_CIR_PLLI2SRDYF_Msk   (0x1UL << RCC_CIR_PLLI2SRDYF_Pos)
     
    #define RCC_CIR_PLLI2SRDYF   RCC_CIR_PLLI2SRDYF_Msk
     
    #define RCC_CIR_CSSF_Pos   (7U)
     
    #define RCC_CIR_CSSF_Msk   (0x1UL << RCC_CIR_CSSF_Pos)
     
    #define RCC_CIR_CSSF   RCC_CIR_CSSF_Msk
     
    #define RCC_CIR_LSIRDYIE_Pos   (8U)
     
    #define RCC_CIR_LSIRDYIE_Msk   (0x1UL << RCC_CIR_LSIRDYIE_Pos)
     
    #define RCC_CIR_LSIRDYIE   RCC_CIR_LSIRDYIE_Msk
     
    #define RCC_CIR_LSERDYIE_Pos   (9U)
     
    #define RCC_CIR_LSERDYIE_Msk   (0x1UL << RCC_CIR_LSERDYIE_Pos)
     
    #define RCC_CIR_LSERDYIE   RCC_CIR_LSERDYIE_Msk
     
    #define RCC_CIR_HSIRDYIE_Pos   (10U)
     
    #define RCC_CIR_HSIRDYIE_Msk   (0x1UL << RCC_CIR_HSIRDYIE_Pos)
     
    #define RCC_CIR_HSIRDYIE   RCC_CIR_HSIRDYIE_Msk
     
    #define RCC_CIR_HSERDYIE_Pos   (11U)
     
    #define RCC_CIR_HSERDYIE_Msk   (0x1UL << RCC_CIR_HSERDYIE_Pos)
     
    #define RCC_CIR_HSERDYIE   RCC_CIR_HSERDYIE_Msk
     
    #define RCC_CIR_PLLRDYIE_Pos   (12U)
     
    #define RCC_CIR_PLLRDYIE_Msk   (0x1UL << RCC_CIR_PLLRDYIE_Pos)
     
    #define RCC_CIR_PLLRDYIE   RCC_CIR_PLLRDYIE_Msk
     
    #define RCC_CIR_PLLI2SRDYIE_Pos   (13U)
     
    #define RCC_CIR_PLLI2SRDYIE_Msk   (0x1UL << RCC_CIR_PLLI2SRDYIE_Pos)
     
    #define RCC_CIR_PLLI2SRDYIE   RCC_CIR_PLLI2SRDYIE_Msk
     
    #define RCC_CIR_LSIRDYC_Pos   (16U)
     
    #define RCC_CIR_LSIRDYC_Msk   (0x1UL << RCC_CIR_LSIRDYC_Pos)
     
    #define RCC_CIR_LSIRDYC   RCC_CIR_LSIRDYC_Msk
     
    #define RCC_CIR_LSERDYC_Pos   (17U)
     
    #define RCC_CIR_LSERDYC_Msk   (0x1UL << RCC_CIR_LSERDYC_Pos)
     
    #define RCC_CIR_LSERDYC   RCC_CIR_LSERDYC_Msk
     
    #define RCC_CIR_HSIRDYC_Pos   (18U)
     
    #define RCC_CIR_HSIRDYC_Msk   (0x1UL << RCC_CIR_HSIRDYC_Pos)
     
    #define RCC_CIR_HSIRDYC   RCC_CIR_HSIRDYC_Msk
     
    #define RCC_CIR_HSERDYC_Pos   (19U)
     
    #define RCC_CIR_HSERDYC_Msk   (0x1UL << RCC_CIR_HSERDYC_Pos)
     
    #define RCC_CIR_HSERDYC   RCC_CIR_HSERDYC_Msk
     
    #define RCC_CIR_PLLRDYC_Pos   (20U)
     
    #define RCC_CIR_PLLRDYC_Msk   (0x1UL << RCC_CIR_PLLRDYC_Pos)
     
    #define RCC_CIR_PLLRDYC   RCC_CIR_PLLRDYC_Msk
     
    #define RCC_CIR_PLLI2SRDYC_Pos   (21U)
     
    #define RCC_CIR_PLLI2SRDYC_Msk   (0x1UL << RCC_CIR_PLLI2SRDYC_Pos)
     
    #define RCC_CIR_PLLI2SRDYC   RCC_CIR_PLLI2SRDYC_Msk
     
    #define RCC_CIR_CSSC_Pos   (23U)
     
    #define RCC_CIR_CSSC_Msk   (0x1UL << RCC_CIR_CSSC_Pos)
     
    #define RCC_CIR_CSSC   RCC_CIR_CSSC_Msk
     
    #define RCC_AHB1RSTR_GPIOARST_Pos   (0U)
     
    #define RCC_AHB1RSTR_GPIOARST_Msk   (0x1UL << RCC_AHB1RSTR_GPIOARST_Pos)
     
    #define RCC_AHB1RSTR_GPIOARST   RCC_AHB1RSTR_GPIOARST_Msk
     
    #define RCC_AHB1RSTR_GPIOBRST_Pos   (1U)
     
    #define RCC_AHB1RSTR_GPIOBRST_Msk   (0x1UL << RCC_AHB1RSTR_GPIOBRST_Pos)
     
    #define RCC_AHB1RSTR_GPIOBRST   RCC_AHB1RSTR_GPIOBRST_Msk
     
    #define RCC_AHB1RSTR_GPIOCRST_Pos   (2U)
     
    #define RCC_AHB1RSTR_GPIOCRST_Msk   (0x1UL << RCC_AHB1RSTR_GPIOCRST_Pos)
     
    #define RCC_AHB1RSTR_GPIOCRST   RCC_AHB1RSTR_GPIOCRST_Msk
     
    #define RCC_AHB1RSTR_GPIODRST_Pos   (3U)
     
    #define RCC_AHB1RSTR_GPIODRST_Msk   (0x1UL << RCC_AHB1RSTR_GPIODRST_Pos)
     
    #define RCC_AHB1RSTR_GPIODRST   RCC_AHB1RSTR_GPIODRST_Msk
     
    #define RCC_AHB1RSTR_GPIOERST_Pos   (4U)
     
    #define RCC_AHB1RSTR_GPIOERST_Msk   (0x1UL << RCC_AHB1RSTR_GPIOERST_Pos)
     
    #define RCC_AHB1RSTR_GPIOERST   RCC_AHB1RSTR_GPIOERST_Msk
     
    #define RCC_AHB1RSTR_GPIOFRST_Pos   (5U)
     
    #define RCC_AHB1RSTR_GPIOFRST_Msk   (0x1UL << RCC_AHB1RSTR_GPIOFRST_Pos)
     
    #define RCC_AHB1RSTR_GPIOFRST   RCC_AHB1RSTR_GPIOFRST_Msk
     
    #define RCC_AHB1RSTR_GPIOGRST_Pos   (6U)
     
    #define RCC_AHB1RSTR_GPIOGRST_Msk   (0x1UL << RCC_AHB1RSTR_GPIOGRST_Pos)
     
    #define RCC_AHB1RSTR_GPIOGRST   RCC_AHB1RSTR_GPIOGRST_Msk
     
    #define RCC_AHB1RSTR_GPIOHRST_Pos   (7U)
     
    #define RCC_AHB1RSTR_GPIOHRST_Msk   (0x1UL << RCC_AHB1RSTR_GPIOHRST_Pos)
     
    #define RCC_AHB1RSTR_GPIOHRST   RCC_AHB1RSTR_GPIOHRST_Msk
     
    #define RCC_AHB1RSTR_GPIOIRST_Pos   (8U)
     
    #define RCC_AHB1RSTR_GPIOIRST_Msk   (0x1UL << RCC_AHB1RSTR_GPIOIRST_Pos)
     
    #define RCC_AHB1RSTR_GPIOIRST   RCC_AHB1RSTR_GPIOIRST_Msk
     
    #define RCC_AHB1RSTR_CRCRST_Pos   (12U)
     
    #define RCC_AHB1RSTR_CRCRST_Msk   (0x1UL << RCC_AHB1RSTR_CRCRST_Pos)
     
    #define RCC_AHB1RSTR_CRCRST   RCC_AHB1RSTR_CRCRST_Msk
     
    #define RCC_AHB1RSTR_DMA1RST_Pos   (21U)
     
    #define RCC_AHB1RSTR_DMA1RST_Msk   (0x1UL << RCC_AHB1RSTR_DMA1RST_Pos)
     
    #define RCC_AHB1RSTR_DMA1RST   RCC_AHB1RSTR_DMA1RST_Msk
     
    #define RCC_AHB1RSTR_DMA2RST_Pos   (22U)
     
    #define RCC_AHB1RSTR_DMA2RST_Msk   (0x1UL << RCC_AHB1RSTR_DMA2RST_Pos)
     
    #define RCC_AHB1RSTR_DMA2RST   RCC_AHB1RSTR_DMA2RST_Msk
     
    #define RCC_AHB1RSTR_ETHMACRST_Pos   (25U)
     
    #define RCC_AHB1RSTR_ETHMACRST_Msk   (0x1UL << RCC_AHB1RSTR_ETHMACRST_Pos)
     
    #define RCC_AHB1RSTR_ETHMACRST   RCC_AHB1RSTR_ETHMACRST_Msk
     
    #define RCC_AHB1RSTR_OTGHRST_Pos   (29U)
     
    #define RCC_AHB1RSTR_OTGHRST_Msk   (0x1UL << RCC_AHB1RSTR_OTGHRST_Pos)
     
    #define RCC_AHB1RSTR_OTGHRST   RCC_AHB1RSTR_OTGHRST_Msk
     
    #define RCC_AHB2RSTR_DCMIRST_Pos   (0U)
     
    #define RCC_AHB2RSTR_DCMIRST_Msk   (0x1UL << RCC_AHB2RSTR_DCMIRST_Pos)
     
    #define RCC_AHB2RSTR_DCMIRST   RCC_AHB2RSTR_DCMIRST_Msk
     
    #define RCC_AHB2RSTR_RNGRST_Pos   (6U)
     
    #define RCC_AHB2RSTR_RNGRST_Msk   (0x1UL << RCC_AHB2RSTR_RNGRST_Pos)
     
    #define RCC_AHB2RSTR_RNGRST   RCC_AHB2RSTR_RNGRST_Msk
     
    #define RCC_AHB2RSTR_OTGFSRST_Pos   (7U)
     
    #define RCC_AHB2RSTR_OTGFSRST_Msk   (0x1UL << RCC_AHB2RSTR_OTGFSRST_Pos)
     
    #define RCC_AHB2RSTR_OTGFSRST   RCC_AHB2RSTR_OTGFSRST_Msk
     
    #define RCC_AHB3RSTR_FSMCRST_Pos   (0U)
     
    #define RCC_AHB3RSTR_FSMCRST_Msk   (0x1UL << RCC_AHB3RSTR_FSMCRST_Pos)
     
    #define RCC_AHB3RSTR_FSMCRST   RCC_AHB3RSTR_FSMCRST_Msk
     
    #define RCC_APB1RSTR_TIM2RST_Pos   (0U)
     
    #define RCC_APB1RSTR_TIM2RST_Msk   (0x1UL << RCC_APB1RSTR_TIM2RST_Pos)
     
    #define RCC_APB1RSTR_TIM2RST   RCC_APB1RSTR_TIM2RST_Msk
     
    #define RCC_APB1RSTR_TIM3RST_Pos   (1U)
     
    #define RCC_APB1RSTR_TIM3RST_Msk   (0x1UL << RCC_APB1RSTR_TIM3RST_Pos)
     
    #define RCC_APB1RSTR_TIM3RST   RCC_APB1RSTR_TIM3RST_Msk
     
    #define RCC_APB1RSTR_TIM4RST_Pos   (2U)
     
    #define RCC_APB1RSTR_TIM4RST_Msk   (0x1UL << RCC_APB1RSTR_TIM4RST_Pos)
     
    #define RCC_APB1RSTR_TIM4RST   RCC_APB1RSTR_TIM4RST_Msk
     
    #define RCC_APB1RSTR_TIM5RST_Pos   (3U)
     
    #define RCC_APB1RSTR_TIM5RST_Msk   (0x1UL << RCC_APB1RSTR_TIM5RST_Pos)
     
    #define RCC_APB1RSTR_TIM5RST   RCC_APB1RSTR_TIM5RST_Msk
     
    #define RCC_APB1RSTR_TIM6RST_Pos   (4U)
     
    #define RCC_APB1RSTR_TIM6RST_Msk   (0x1UL << RCC_APB1RSTR_TIM6RST_Pos)
     
    #define RCC_APB1RSTR_TIM6RST   RCC_APB1RSTR_TIM6RST_Msk
     
    #define RCC_APB1RSTR_TIM7RST_Pos   (5U)
     
    #define RCC_APB1RSTR_TIM7RST_Msk   (0x1UL << RCC_APB1RSTR_TIM7RST_Pos)
     
    #define RCC_APB1RSTR_TIM7RST   RCC_APB1RSTR_TIM7RST_Msk
     
    #define RCC_APB1RSTR_TIM12RST_Pos   (6U)
     
    #define RCC_APB1RSTR_TIM12RST_Msk   (0x1UL << RCC_APB1RSTR_TIM12RST_Pos)
     
    #define RCC_APB1RSTR_TIM12RST   RCC_APB1RSTR_TIM12RST_Msk
     
    #define RCC_APB1RSTR_TIM13RST_Pos   (7U)
     
    #define RCC_APB1RSTR_TIM13RST_Msk   (0x1UL << RCC_APB1RSTR_TIM13RST_Pos)
     
    #define RCC_APB1RSTR_TIM13RST   RCC_APB1RSTR_TIM13RST_Msk
     
    #define RCC_APB1RSTR_TIM14RST_Pos   (8U)
     
    #define RCC_APB1RSTR_TIM14RST_Msk   (0x1UL << RCC_APB1RSTR_TIM14RST_Pos)
     
    #define RCC_APB1RSTR_TIM14RST   RCC_APB1RSTR_TIM14RST_Msk
     
    #define RCC_APB1RSTR_WWDGRST_Pos   (11U)
     
    #define RCC_APB1RSTR_WWDGRST_Msk   (0x1UL << RCC_APB1RSTR_WWDGRST_Pos)
     
    #define RCC_APB1RSTR_WWDGRST   RCC_APB1RSTR_WWDGRST_Msk
     
    #define RCC_APB1RSTR_SPI2RST_Pos   (14U)
     
    #define RCC_APB1RSTR_SPI2RST_Msk   (0x1UL << RCC_APB1RSTR_SPI2RST_Pos)
     
    #define RCC_APB1RSTR_SPI2RST   RCC_APB1RSTR_SPI2RST_Msk
     
    #define RCC_APB1RSTR_SPI3RST_Pos   (15U)
     
    #define RCC_APB1RSTR_SPI3RST_Msk   (0x1UL << RCC_APB1RSTR_SPI3RST_Pos)
     
    #define RCC_APB1RSTR_SPI3RST   RCC_APB1RSTR_SPI3RST_Msk
     
    #define RCC_APB1RSTR_USART2RST_Pos   (17U)
     
    #define RCC_APB1RSTR_USART2RST_Msk   (0x1UL << RCC_APB1RSTR_USART2RST_Pos)
     
    #define RCC_APB1RSTR_USART2RST   RCC_APB1RSTR_USART2RST_Msk
     
    #define RCC_APB1RSTR_USART3RST_Pos   (18U)
     
    #define RCC_APB1RSTR_USART3RST_Msk   (0x1UL << RCC_APB1RSTR_USART3RST_Pos)
     
    #define RCC_APB1RSTR_USART3RST   RCC_APB1RSTR_USART3RST_Msk
     
    #define RCC_APB1RSTR_UART4RST_Pos   (19U)
     
    #define RCC_APB1RSTR_UART4RST_Msk   (0x1UL << RCC_APB1RSTR_UART4RST_Pos)
     
    #define RCC_APB1RSTR_UART4RST   RCC_APB1RSTR_UART4RST_Msk
     
    #define RCC_APB1RSTR_UART5RST_Pos   (20U)
     
    #define RCC_APB1RSTR_UART5RST_Msk   (0x1UL << RCC_APB1RSTR_UART5RST_Pos)
     
    #define RCC_APB1RSTR_UART5RST   RCC_APB1RSTR_UART5RST_Msk
     
    #define RCC_APB1RSTR_I2C1RST_Pos   (21U)
     
    #define RCC_APB1RSTR_I2C1RST_Msk   (0x1UL << RCC_APB1RSTR_I2C1RST_Pos)
     
    #define RCC_APB1RSTR_I2C1RST   RCC_APB1RSTR_I2C1RST_Msk
     
    #define RCC_APB1RSTR_I2C2RST_Pos   (22U)
     
    #define RCC_APB1RSTR_I2C2RST_Msk   (0x1UL << RCC_APB1RSTR_I2C2RST_Pos)
     
    #define RCC_APB1RSTR_I2C2RST   RCC_APB1RSTR_I2C2RST_Msk
     
    #define RCC_APB1RSTR_I2C3RST_Pos   (23U)
     
    #define RCC_APB1RSTR_I2C3RST_Msk   (0x1UL << RCC_APB1RSTR_I2C3RST_Pos)
     
    #define RCC_APB1RSTR_I2C3RST   RCC_APB1RSTR_I2C3RST_Msk
     
    #define RCC_APB1RSTR_CAN1RST_Pos   (25U)
     
    #define RCC_APB1RSTR_CAN1RST_Msk   (0x1UL << RCC_APB1RSTR_CAN1RST_Pos)
     
    #define RCC_APB1RSTR_CAN1RST   RCC_APB1RSTR_CAN1RST_Msk
     
    #define RCC_APB1RSTR_CAN2RST_Pos   (26U)
     
    #define RCC_APB1RSTR_CAN2RST_Msk   (0x1UL << RCC_APB1RSTR_CAN2RST_Pos)
     
    #define RCC_APB1RSTR_CAN2RST   RCC_APB1RSTR_CAN2RST_Msk
     
    #define RCC_APB1RSTR_PWRRST_Pos   (28U)
     
    #define RCC_APB1RSTR_PWRRST_Msk   (0x1UL << RCC_APB1RSTR_PWRRST_Pos)
     
    #define RCC_APB1RSTR_PWRRST   RCC_APB1RSTR_PWRRST_Msk
     
    #define RCC_APB1RSTR_DACRST_Pos   (29U)
     
    #define RCC_APB1RSTR_DACRST_Msk   (0x1UL << RCC_APB1RSTR_DACRST_Pos)
     
    #define RCC_APB1RSTR_DACRST   RCC_APB1RSTR_DACRST_Msk
     
    #define RCC_APB2RSTR_TIM1RST_Pos   (0U)
     
    #define RCC_APB2RSTR_TIM1RST_Msk   (0x1UL << RCC_APB2RSTR_TIM1RST_Pos)
     
    #define RCC_APB2RSTR_TIM1RST   RCC_APB2RSTR_TIM1RST_Msk
     
    #define RCC_APB2RSTR_TIM8RST_Pos   (1U)
     
    #define RCC_APB2RSTR_TIM8RST_Msk   (0x1UL << RCC_APB2RSTR_TIM8RST_Pos)
     
    #define RCC_APB2RSTR_TIM8RST   RCC_APB2RSTR_TIM8RST_Msk
     
    #define RCC_APB2RSTR_USART1RST_Pos   (4U)
     
    #define RCC_APB2RSTR_USART1RST_Msk   (0x1UL << RCC_APB2RSTR_USART1RST_Pos)
     
    #define RCC_APB2RSTR_USART1RST   RCC_APB2RSTR_USART1RST_Msk
     
    #define RCC_APB2RSTR_USART6RST_Pos   (5U)
     
    #define RCC_APB2RSTR_USART6RST_Msk   (0x1UL << RCC_APB2RSTR_USART6RST_Pos)
     
    #define RCC_APB2RSTR_USART6RST   RCC_APB2RSTR_USART6RST_Msk
     
    #define RCC_APB2RSTR_ADCRST_Pos   (8U)
     
    #define RCC_APB2RSTR_ADCRST_Msk   (0x1UL << RCC_APB2RSTR_ADCRST_Pos)
     
    #define RCC_APB2RSTR_ADCRST   RCC_APB2RSTR_ADCRST_Msk
     
    #define RCC_APB2RSTR_SDIORST_Pos   (11U)
     
    #define RCC_APB2RSTR_SDIORST_Msk   (0x1UL << RCC_APB2RSTR_SDIORST_Pos)
     
    #define RCC_APB2RSTR_SDIORST   RCC_APB2RSTR_SDIORST_Msk
     
    #define RCC_APB2RSTR_SPI1RST_Pos   (12U)
     
    #define RCC_APB2RSTR_SPI1RST_Msk   (0x1UL << RCC_APB2RSTR_SPI1RST_Pos)
     
    #define RCC_APB2RSTR_SPI1RST   RCC_APB2RSTR_SPI1RST_Msk
     
    #define RCC_APB2RSTR_SYSCFGRST_Pos   (14U)
     
    #define RCC_APB2RSTR_SYSCFGRST_Msk   (0x1UL << RCC_APB2RSTR_SYSCFGRST_Pos)
     
    #define RCC_APB2RSTR_SYSCFGRST   RCC_APB2RSTR_SYSCFGRST_Msk
     
    #define RCC_APB2RSTR_TIM9RST_Pos   (16U)
     
    #define RCC_APB2RSTR_TIM9RST_Msk   (0x1UL << RCC_APB2RSTR_TIM9RST_Pos)
     
    #define RCC_APB2RSTR_TIM9RST   RCC_APB2RSTR_TIM9RST_Msk
     
    #define RCC_APB2RSTR_TIM10RST_Pos   (17U)
     
    #define RCC_APB2RSTR_TIM10RST_Msk   (0x1UL << RCC_APB2RSTR_TIM10RST_Pos)
     
    #define RCC_APB2RSTR_TIM10RST   RCC_APB2RSTR_TIM10RST_Msk
     
    #define RCC_APB2RSTR_TIM11RST_Pos   (18U)
     
    #define RCC_APB2RSTR_TIM11RST_Msk   (0x1UL << RCC_APB2RSTR_TIM11RST_Pos)
     
    #define RCC_APB2RSTR_TIM11RST   RCC_APB2RSTR_TIM11RST_Msk
     
    #define RCC_APB2RSTR_SPI1   RCC_APB2RSTR_SPI1RST
     
    #define RCC_AHB1ENR_GPIOAEN_Pos   (0U)
     
    #define RCC_AHB1ENR_GPIOAEN_Msk   (0x1UL << RCC_AHB1ENR_GPIOAEN_Pos)
     
    #define RCC_AHB1ENR_GPIOAEN   RCC_AHB1ENR_GPIOAEN_Msk
     
    #define RCC_AHB1ENR_GPIOBEN_Pos   (1U)
     
    #define RCC_AHB1ENR_GPIOBEN_Msk   (0x1UL << RCC_AHB1ENR_GPIOBEN_Pos)
     
    #define RCC_AHB1ENR_GPIOBEN   RCC_AHB1ENR_GPIOBEN_Msk
     
    #define RCC_AHB1ENR_GPIOCEN_Pos   (2U)
     
    #define RCC_AHB1ENR_GPIOCEN_Msk   (0x1UL << RCC_AHB1ENR_GPIOCEN_Pos)
     
    #define RCC_AHB1ENR_GPIOCEN   RCC_AHB1ENR_GPIOCEN_Msk
     
    #define RCC_AHB1ENR_GPIODEN_Pos   (3U)
     
    #define RCC_AHB1ENR_GPIODEN_Msk   (0x1UL << RCC_AHB1ENR_GPIODEN_Pos)
     
    #define RCC_AHB1ENR_GPIODEN   RCC_AHB1ENR_GPIODEN_Msk
     
    #define RCC_AHB1ENR_GPIOEEN_Pos   (4U)
     
    #define RCC_AHB1ENR_GPIOEEN_Msk   (0x1UL << RCC_AHB1ENR_GPIOEEN_Pos)
     
    #define RCC_AHB1ENR_GPIOEEN   RCC_AHB1ENR_GPIOEEN_Msk
     
    #define RCC_AHB1ENR_GPIOFEN_Pos   (5U)
     
    #define RCC_AHB1ENR_GPIOFEN_Msk   (0x1UL << RCC_AHB1ENR_GPIOFEN_Pos)
     
    #define RCC_AHB1ENR_GPIOFEN   RCC_AHB1ENR_GPIOFEN_Msk
     
    #define RCC_AHB1ENR_GPIOGEN_Pos   (6U)
     
    #define RCC_AHB1ENR_GPIOGEN_Msk   (0x1UL << RCC_AHB1ENR_GPIOGEN_Pos)
     
    #define RCC_AHB1ENR_GPIOGEN   RCC_AHB1ENR_GPIOGEN_Msk
     
    #define RCC_AHB1ENR_GPIOHEN_Pos   (7U)
     
    #define RCC_AHB1ENR_GPIOHEN_Msk   (0x1UL << RCC_AHB1ENR_GPIOHEN_Pos)
     
    #define RCC_AHB1ENR_GPIOHEN   RCC_AHB1ENR_GPIOHEN_Msk
     
    #define RCC_AHB1ENR_GPIOIEN_Pos   (8U)
     
    #define RCC_AHB1ENR_GPIOIEN_Msk   (0x1UL << RCC_AHB1ENR_GPIOIEN_Pos)
     
    #define RCC_AHB1ENR_GPIOIEN   RCC_AHB1ENR_GPIOIEN_Msk
     
    #define RCC_AHB1ENR_CRCEN_Pos   (12U)
     
    #define RCC_AHB1ENR_CRCEN_Msk   (0x1UL << RCC_AHB1ENR_CRCEN_Pos)
     
    #define RCC_AHB1ENR_CRCEN   RCC_AHB1ENR_CRCEN_Msk
     
    #define RCC_AHB1ENR_BKPSRAMEN_Pos   (18U)
     
    #define RCC_AHB1ENR_BKPSRAMEN_Msk   (0x1UL << RCC_AHB1ENR_BKPSRAMEN_Pos)
     
    #define RCC_AHB1ENR_BKPSRAMEN   RCC_AHB1ENR_BKPSRAMEN_Msk
     
    #define RCC_AHB1ENR_CCMDATARAMEN_Pos   (20U)
     
    #define RCC_AHB1ENR_CCMDATARAMEN_Msk   (0x1UL << RCC_AHB1ENR_CCMDATARAMEN_Pos)
     
    #define RCC_AHB1ENR_CCMDATARAMEN   RCC_AHB1ENR_CCMDATARAMEN_Msk
     
    #define RCC_AHB1ENR_DMA1EN_Pos   (21U)
     
    #define RCC_AHB1ENR_DMA1EN_Msk   (0x1UL << RCC_AHB1ENR_DMA1EN_Pos)
     
    #define RCC_AHB1ENR_DMA1EN   RCC_AHB1ENR_DMA1EN_Msk
     
    #define RCC_AHB1ENR_DMA2EN_Pos   (22U)
     
    #define RCC_AHB1ENR_DMA2EN_Msk   (0x1UL << RCC_AHB1ENR_DMA2EN_Pos)
     
    #define RCC_AHB1ENR_DMA2EN   RCC_AHB1ENR_DMA2EN_Msk
     
    #define RCC_AHB1ENR_ETHMACEN_Pos   (25U)
     
    #define RCC_AHB1ENR_ETHMACEN_Msk   (0x1UL << RCC_AHB1ENR_ETHMACEN_Pos)
     
    #define RCC_AHB1ENR_ETHMACEN   RCC_AHB1ENR_ETHMACEN_Msk
     
    #define RCC_AHB1ENR_ETHMACTXEN_Pos   (26U)
     
    #define RCC_AHB1ENR_ETHMACTXEN_Msk   (0x1UL << RCC_AHB1ENR_ETHMACTXEN_Pos)
     
    #define RCC_AHB1ENR_ETHMACTXEN   RCC_AHB1ENR_ETHMACTXEN_Msk
     
    #define RCC_AHB1ENR_ETHMACRXEN_Pos   (27U)
     
    #define RCC_AHB1ENR_ETHMACRXEN_Msk   (0x1UL << RCC_AHB1ENR_ETHMACRXEN_Pos)
     
    #define RCC_AHB1ENR_ETHMACRXEN   RCC_AHB1ENR_ETHMACRXEN_Msk
     
    #define RCC_AHB1ENR_ETHMACPTPEN_Pos   (28U)
     
    #define RCC_AHB1ENR_ETHMACPTPEN_Msk   (0x1UL << RCC_AHB1ENR_ETHMACPTPEN_Pos)
     
    #define RCC_AHB1ENR_ETHMACPTPEN   RCC_AHB1ENR_ETHMACPTPEN_Msk
     
    #define RCC_AHB1ENR_OTGHSEN_Pos   (29U)
     
    #define RCC_AHB1ENR_OTGHSEN_Msk   (0x1UL << RCC_AHB1ENR_OTGHSEN_Pos)
     
    #define RCC_AHB1ENR_OTGHSEN   RCC_AHB1ENR_OTGHSEN_Msk
     
    #define RCC_AHB1ENR_OTGHSULPIEN_Pos   (30U)
     
    #define RCC_AHB1ENR_OTGHSULPIEN_Msk   (0x1UL << RCC_AHB1ENR_OTGHSULPIEN_Pos)
     
    #define RCC_AHB1ENR_OTGHSULPIEN   RCC_AHB1ENR_OTGHSULPIEN_Msk
     
    #define RCC_AHB2_SUPPORT
     
    #define RCC_AHB2ENR_DCMIEN_Pos   (0U)
     
    #define RCC_AHB2ENR_DCMIEN_Msk   (0x1UL << RCC_AHB2ENR_DCMIEN_Pos)
     
    #define RCC_AHB2ENR_DCMIEN   RCC_AHB2ENR_DCMIEN_Msk
     
    #define RCC_AHB2ENR_RNGEN_Pos   (6U)
     
    #define RCC_AHB2ENR_RNGEN_Msk   (0x1UL << RCC_AHB2ENR_RNGEN_Pos)
     
    #define RCC_AHB2ENR_RNGEN   RCC_AHB2ENR_RNGEN_Msk
     
    #define RCC_AHB2ENR_OTGFSEN_Pos   (7U)
     
    #define RCC_AHB2ENR_OTGFSEN_Msk   (0x1UL << RCC_AHB2ENR_OTGFSEN_Pos)
     
    #define RCC_AHB2ENR_OTGFSEN   RCC_AHB2ENR_OTGFSEN_Msk
     
    #define RCC_AHB3_SUPPORT
     
    #define RCC_AHB3ENR_FSMCEN_Pos   (0U)
     
    #define RCC_AHB3ENR_FSMCEN_Msk   (0x1UL << RCC_AHB3ENR_FSMCEN_Pos)
     
    #define RCC_AHB3ENR_FSMCEN   RCC_AHB3ENR_FSMCEN_Msk
     
    #define RCC_APB1ENR_TIM2EN_Pos   (0U)
     
    #define RCC_APB1ENR_TIM2EN_Msk   (0x1UL << RCC_APB1ENR_TIM2EN_Pos)
     
    #define RCC_APB1ENR_TIM2EN   RCC_APB1ENR_TIM2EN_Msk
     
    #define RCC_APB1ENR_TIM3EN_Pos   (1U)
     
    #define RCC_APB1ENR_TIM3EN_Msk   (0x1UL << RCC_APB1ENR_TIM3EN_Pos)
     
    #define RCC_APB1ENR_TIM3EN   RCC_APB1ENR_TIM3EN_Msk
     
    #define RCC_APB1ENR_TIM4EN_Pos   (2U)
     
    #define RCC_APB1ENR_TIM4EN_Msk   (0x1UL << RCC_APB1ENR_TIM4EN_Pos)
     
    #define RCC_APB1ENR_TIM4EN   RCC_APB1ENR_TIM4EN_Msk
     
    #define RCC_APB1ENR_TIM5EN_Pos   (3U)
     
    #define RCC_APB1ENR_TIM5EN_Msk   (0x1UL << RCC_APB1ENR_TIM5EN_Pos)
     
    #define RCC_APB1ENR_TIM5EN   RCC_APB1ENR_TIM5EN_Msk
     
    #define RCC_APB1ENR_TIM6EN_Pos   (4U)
     
    #define RCC_APB1ENR_TIM6EN_Msk   (0x1UL << RCC_APB1ENR_TIM6EN_Pos)
     
    #define RCC_APB1ENR_TIM6EN   RCC_APB1ENR_TIM6EN_Msk
     
    #define RCC_APB1ENR_TIM7EN_Pos   (5U)
     
    #define RCC_APB1ENR_TIM7EN_Msk   (0x1UL << RCC_APB1ENR_TIM7EN_Pos)
     
    #define RCC_APB1ENR_TIM7EN   RCC_APB1ENR_TIM7EN_Msk
     
    #define RCC_APB1ENR_TIM12EN_Pos   (6U)
     
    #define RCC_APB1ENR_TIM12EN_Msk   (0x1UL << RCC_APB1ENR_TIM12EN_Pos)
     
    #define RCC_APB1ENR_TIM12EN   RCC_APB1ENR_TIM12EN_Msk
     
    #define RCC_APB1ENR_TIM13EN_Pos   (7U)
     
    #define RCC_APB1ENR_TIM13EN_Msk   (0x1UL << RCC_APB1ENR_TIM13EN_Pos)
     
    #define RCC_APB1ENR_TIM13EN   RCC_APB1ENR_TIM13EN_Msk
     
    #define RCC_APB1ENR_TIM14EN_Pos   (8U)
     
    #define RCC_APB1ENR_TIM14EN_Msk   (0x1UL << RCC_APB1ENR_TIM14EN_Pos)
     
    #define RCC_APB1ENR_TIM14EN   RCC_APB1ENR_TIM14EN_Msk
     
    #define RCC_APB1ENR_WWDGEN_Pos   (11U)
     
    #define RCC_APB1ENR_WWDGEN_Msk   (0x1UL << RCC_APB1ENR_WWDGEN_Pos)
     
    #define RCC_APB1ENR_WWDGEN   RCC_APB1ENR_WWDGEN_Msk
     
    #define RCC_APB1ENR_SPI2EN_Pos   (14U)
     
    #define RCC_APB1ENR_SPI2EN_Msk   (0x1UL << RCC_APB1ENR_SPI2EN_Pos)
     
    #define RCC_APB1ENR_SPI2EN   RCC_APB1ENR_SPI2EN_Msk
     
    #define RCC_APB1ENR_SPI3EN_Pos   (15U)
     
    #define RCC_APB1ENR_SPI3EN_Msk   (0x1UL << RCC_APB1ENR_SPI3EN_Pos)
     
    #define RCC_APB1ENR_SPI3EN   RCC_APB1ENR_SPI3EN_Msk
     
    #define RCC_APB1ENR_USART2EN_Pos   (17U)
     
    #define RCC_APB1ENR_USART2EN_Msk   (0x1UL << RCC_APB1ENR_USART2EN_Pos)
     
    #define RCC_APB1ENR_USART2EN   RCC_APB1ENR_USART2EN_Msk
     
    #define RCC_APB1ENR_USART3EN_Pos   (18U)
     
    #define RCC_APB1ENR_USART3EN_Msk   (0x1UL << RCC_APB1ENR_USART3EN_Pos)
     
    #define RCC_APB1ENR_USART3EN   RCC_APB1ENR_USART3EN_Msk
     
    #define RCC_APB1ENR_UART4EN_Pos   (19U)
     
    #define RCC_APB1ENR_UART4EN_Msk   (0x1UL << RCC_APB1ENR_UART4EN_Pos)
     
    #define RCC_APB1ENR_UART4EN   RCC_APB1ENR_UART4EN_Msk
     
    #define RCC_APB1ENR_UART5EN_Pos   (20U)
     
    #define RCC_APB1ENR_UART5EN_Msk   (0x1UL << RCC_APB1ENR_UART5EN_Pos)
     
    #define RCC_APB1ENR_UART5EN   RCC_APB1ENR_UART5EN_Msk
     
    #define RCC_APB1ENR_I2C1EN_Pos   (21U)
     
    #define RCC_APB1ENR_I2C1EN_Msk   (0x1UL << RCC_APB1ENR_I2C1EN_Pos)
     
    #define RCC_APB1ENR_I2C1EN   RCC_APB1ENR_I2C1EN_Msk
     
    #define RCC_APB1ENR_I2C2EN_Pos   (22U)
     
    #define RCC_APB1ENR_I2C2EN_Msk   (0x1UL << RCC_APB1ENR_I2C2EN_Pos)
     
    #define RCC_APB1ENR_I2C2EN   RCC_APB1ENR_I2C2EN_Msk
     
    #define RCC_APB1ENR_I2C3EN_Pos   (23U)
     
    #define RCC_APB1ENR_I2C3EN_Msk   (0x1UL << RCC_APB1ENR_I2C3EN_Pos)
     
    #define RCC_APB1ENR_I2C3EN   RCC_APB1ENR_I2C3EN_Msk
     
    #define RCC_APB1ENR_CAN1EN_Pos   (25U)
     
    #define RCC_APB1ENR_CAN1EN_Msk   (0x1UL << RCC_APB1ENR_CAN1EN_Pos)
     
    #define RCC_APB1ENR_CAN1EN   RCC_APB1ENR_CAN1EN_Msk
     
    #define RCC_APB1ENR_CAN2EN_Pos   (26U)
     
    #define RCC_APB1ENR_CAN2EN_Msk   (0x1UL << RCC_APB1ENR_CAN2EN_Pos)
     
    #define RCC_APB1ENR_CAN2EN   RCC_APB1ENR_CAN2EN_Msk
     
    #define RCC_APB1ENR_PWREN_Pos   (28U)
     
    #define RCC_APB1ENR_PWREN_Msk   (0x1UL << RCC_APB1ENR_PWREN_Pos)
     
    #define RCC_APB1ENR_PWREN   RCC_APB1ENR_PWREN_Msk
     
    #define RCC_APB1ENR_DACEN_Pos   (29U)
     
    #define RCC_APB1ENR_DACEN_Msk   (0x1UL << RCC_APB1ENR_DACEN_Pos)
     
    #define RCC_APB1ENR_DACEN   RCC_APB1ENR_DACEN_Msk
     
    #define RCC_APB2ENR_TIM1EN_Pos   (0U)
     
    #define RCC_APB2ENR_TIM1EN_Msk   (0x1UL << RCC_APB2ENR_TIM1EN_Pos)
     
    #define RCC_APB2ENR_TIM1EN   RCC_APB2ENR_TIM1EN_Msk
     
    #define RCC_APB2ENR_TIM8EN_Pos   (1U)
     
    #define RCC_APB2ENR_TIM8EN_Msk   (0x1UL << RCC_APB2ENR_TIM8EN_Pos)
     
    #define RCC_APB2ENR_TIM8EN   RCC_APB2ENR_TIM8EN_Msk
     
    #define RCC_APB2ENR_USART1EN_Pos   (4U)
     
    #define RCC_APB2ENR_USART1EN_Msk   (0x1UL << RCC_APB2ENR_USART1EN_Pos)
     
    #define RCC_APB2ENR_USART1EN   RCC_APB2ENR_USART1EN_Msk
     
    #define RCC_APB2ENR_USART6EN_Pos   (5U)
     
    #define RCC_APB2ENR_USART6EN_Msk   (0x1UL << RCC_APB2ENR_USART6EN_Pos)
     
    #define RCC_APB2ENR_USART6EN   RCC_APB2ENR_USART6EN_Msk
     
    #define RCC_APB2ENR_ADC1EN_Pos   (8U)
     
    #define RCC_APB2ENR_ADC1EN_Msk   (0x1UL << RCC_APB2ENR_ADC1EN_Pos)
     
    #define RCC_APB2ENR_ADC1EN   RCC_APB2ENR_ADC1EN_Msk
     
    #define RCC_APB2ENR_ADC2EN_Pos   (9U)
     
    #define RCC_APB2ENR_ADC2EN_Msk   (0x1UL << RCC_APB2ENR_ADC2EN_Pos)
     
    #define RCC_APB2ENR_ADC2EN   RCC_APB2ENR_ADC2EN_Msk
     
    #define RCC_APB2ENR_ADC3EN_Pos   (10U)
     
    #define RCC_APB2ENR_ADC3EN_Msk   (0x1UL << RCC_APB2ENR_ADC3EN_Pos)
     
    #define RCC_APB2ENR_ADC3EN   RCC_APB2ENR_ADC3EN_Msk
     
    #define RCC_APB2ENR_SDIOEN_Pos   (11U)
     
    #define RCC_APB2ENR_SDIOEN_Msk   (0x1UL << RCC_APB2ENR_SDIOEN_Pos)
     
    #define RCC_APB2ENR_SDIOEN   RCC_APB2ENR_SDIOEN_Msk
     
    #define RCC_APB2ENR_SPI1EN_Pos   (12U)
     
    #define RCC_APB2ENR_SPI1EN_Msk   (0x1UL << RCC_APB2ENR_SPI1EN_Pos)
     
    #define RCC_APB2ENR_SPI1EN   RCC_APB2ENR_SPI1EN_Msk
     
    #define RCC_APB2ENR_SYSCFGEN_Pos   (14U)
     
    #define RCC_APB2ENR_SYSCFGEN_Msk   (0x1UL << RCC_APB2ENR_SYSCFGEN_Pos)
     
    #define RCC_APB2ENR_SYSCFGEN   RCC_APB2ENR_SYSCFGEN_Msk
     
    #define RCC_APB2ENR_TIM9EN_Pos   (16U)
     
    #define RCC_APB2ENR_TIM9EN_Msk   (0x1UL << RCC_APB2ENR_TIM9EN_Pos)
     
    #define RCC_APB2ENR_TIM9EN   RCC_APB2ENR_TIM9EN_Msk
     
    #define RCC_APB2ENR_TIM10EN_Pos   (17U)
     
    #define RCC_APB2ENR_TIM10EN_Msk   (0x1UL << RCC_APB2ENR_TIM10EN_Pos)
     
    #define RCC_APB2ENR_TIM10EN   RCC_APB2ENR_TIM10EN_Msk
     
    #define RCC_APB2ENR_TIM11EN_Pos   (18U)
     
    #define RCC_APB2ENR_TIM11EN_Msk   (0x1UL << RCC_APB2ENR_TIM11EN_Pos)
     
    #define RCC_APB2ENR_TIM11EN   RCC_APB2ENR_TIM11EN_Msk
     
    #define RCC_AHB1LPENR_GPIOALPEN_Pos   (0U)
     
    #define RCC_AHB1LPENR_GPIOALPEN_Msk   (0x1UL << RCC_AHB1LPENR_GPIOALPEN_Pos)
     
    #define RCC_AHB1LPENR_GPIOALPEN   RCC_AHB1LPENR_GPIOALPEN_Msk
     
    #define RCC_AHB1LPENR_GPIOBLPEN_Pos   (1U)
     
    #define RCC_AHB1LPENR_GPIOBLPEN_Msk   (0x1UL << RCC_AHB1LPENR_GPIOBLPEN_Pos)
     
    #define RCC_AHB1LPENR_GPIOBLPEN   RCC_AHB1LPENR_GPIOBLPEN_Msk
     
    #define RCC_AHB1LPENR_GPIOCLPEN_Pos   (2U)
     
    #define RCC_AHB1LPENR_GPIOCLPEN_Msk   (0x1UL << RCC_AHB1LPENR_GPIOCLPEN_Pos)
     
    #define RCC_AHB1LPENR_GPIOCLPEN   RCC_AHB1LPENR_GPIOCLPEN_Msk
     
    #define RCC_AHB1LPENR_GPIODLPEN_Pos   (3U)
     
    #define RCC_AHB1LPENR_GPIODLPEN_Msk   (0x1UL << RCC_AHB1LPENR_GPIODLPEN_Pos)
     
    #define RCC_AHB1LPENR_GPIODLPEN   RCC_AHB1LPENR_GPIODLPEN_Msk
     
    #define RCC_AHB1LPENR_GPIOELPEN_Pos   (4U)
     
    #define RCC_AHB1LPENR_GPIOELPEN_Msk   (0x1UL << RCC_AHB1LPENR_GPIOELPEN_Pos)
     
    #define RCC_AHB1LPENR_GPIOELPEN   RCC_AHB1LPENR_GPIOELPEN_Msk
     
    #define RCC_AHB1LPENR_GPIOFLPEN_Pos   (5U)
     
    #define RCC_AHB1LPENR_GPIOFLPEN_Msk   (0x1UL << RCC_AHB1LPENR_GPIOFLPEN_Pos)
     
    #define RCC_AHB1LPENR_GPIOFLPEN   RCC_AHB1LPENR_GPIOFLPEN_Msk
     
    #define RCC_AHB1LPENR_GPIOGLPEN_Pos   (6U)
     
    #define RCC_AHB1LPENR_GPIOGLPEN_Msk   (0x1UL << RCC_AHB1LPENR_GPIOGLPEN_Pos)
     
    #define RCC_AHB1LPENR_GPIOGLPEN   RCC_AHB1LPENR_GPIOGLPEN_Msk
     
    #define RCC_AHB1LPENR_GPIOHLPEN_Pos   (7U)
     
    #define RCC_AHB1LPENR_GPIOHLPEN_Msk   (0x1UL << RCC_AHB1LPENR_GPIOHLPEN_Pos)
     
    #define RCC_AHB1LPENR_GPIOHLPEN   RCC_AHB1LPENR_GPIOHLPEN_Msk
     
    #define RCC_AHB1LPENR_GPIOILPEN_Pos   (8U)
     
    #define RCC_AHB1LPENR_GPIOILPEN_Msk   (0x1UL << RCC_AHB1LPENR_GPIOILPEN_Pos)
     
    #define RCC_AHB1LPENR_GPIOILPEN   RCC_AHB1LPENR_GPIOILPEN_Msk
     
    #define RCC_AHB1LPENR_CRCLPEN_Pos   (12U)
     
    #define RCC_AHB1LPENR_CRCLPEN_Msk   (0x1UL << RCC_AHB1LPENR_CRCLPEN_Pos)
     
    #define RCC_AHB1LPENR_CRCLPEN   RCC_AHB1LPENR_CRCLPEN_Msk
     
    #define RCC_AHB1LPENR_FLITFLPEN_Pos   (15U)
     
    #define RCC_AHB1LPENR_FLITFLPEN_Msk   (0x1UL << RCC_AHB1LPENR_FLITFLPEN_Pos)
     
    #define RCC_AHB1LPENR_FLITFLPEN   RCC_AHB1LPENR_FLITFLPEN_Msk
     
    #define RCC_AHB1LPENR_SRAM1LPEN_Pos   (16U)
     
    #define RCC_AHB1LPENR_SRAM1LPEN_Msk   (0x1UL << RCC_AHB1LPENR_SRAM1LPEN_Pos)
     
    #define RCC_AHB1LPENR_SRAM1LPEN   RCC_AHB1LPENR_SRAM1LPEN_Msk
     
    #define RCC_AHB1LPENR_SRAM2LPEN_Pos   (17U)
     
    #define RCC_AHB1LPENR_SRAM2LPEN_Msk   (0x1UL << RCC_AHB1LPENR_SRAM2LPEN_Pos)
     
    #define RCC_AHB1LPENR_SRAM2LPEN   RCC_AHB1LPENR_SRAM2LPEN_Msk
     
    #define RCC_AHB1LPENR_BKPSRAMLPEN_Pos   (18U)
     
    #define RCC_AHB1LPENR_BKPSRAMLPEN_Msk   (0x1UL << RCC_AHB1LPENR_BKPSRAMLPEN_Pos)
     
    #define RCC_AHB1LPENR_BKPSRAMLPEN   RCC_AHB1LPENR_BKPSRAMLPEN_Msk
     
    #define RCC_AHB1LPENR_DMA1LPEN_Pos   (21U)
     
    #define RCC_AHB1LPENR_DMA1LPEN_Msk   (0x1UL << RCC_AHB1LPENR_DMA1LPEN_Pos)
     
    #define RCC_AHB1LPENR_DMA1LPEN   RCC_AHB1LPENR_DMA1LPEN_Msk
     
    #define RCC_AHB1LPENR_DMA2LPEN_Pos   (22U)
     
    #define RCC_AHB1LPENR_DMA2LPEN_Msk   (0x1UL << RCC_AHB1LPENR_DMA2LPEN_Pos)
     
    #define RCC_AHB1LPENR_DMA2LPEN   RCC_AHB1LPENR_DMA2LPEN_Msk
     
    #define RCC_AHB1LPENR_ETHMACLPEN_Pos   (25U)
     
    #define RCC_AHB1LPENR_ETHMACLPEN_Msk   (0x1UL << RCC_AHB1LPENR_ETHMACLPEN_Pos)
     
    #define RCC_AHB1LPENR_ETHMACLPEN   RCC_AHB1LPENR_ETHMACLPEN_Msk
     
    #define RCC_AHB1LPENR_ETHMACTXLPEN_Pos   (26U)
     
    #define RCC_AHB1LPENR_ETHMACTXLPEN_Msk   (0x1UL << RCC_AHB1LPENR_ETHMACTXLPEN_Pos)
     
    #define RCC_AHB1LPENR_ETHMACTXLPEN   RCC_AHB1LPENR_ETHMACTXLPEN_Msk
     
    #define RCC_AHB1LPENR_ETHMACRXLPEN_Pos   (27U)
     
    #define RCC_AHB1LPENR_ETHMACRXLPEN_Msk   (0x1UL << RCC_AHB1LPENR_ETHMACRXLPEN_Pos)
     
    #define RCC_AHB1LPENR_ETHMACRXLPEN   RCC_AHB1LPENR_ETHMACRXLPEN_Msk
     
    #define RCC_AHB1LPENR_ETHMACPTPLPEN_Pos   (28U)
     
    #define RCC_AHB1LPENR_ETHMACPTPLPEN_Msk   (0x1UL << RCC_AHB1LPENR_ETHMACPTPLPEN_Pos)
     
    #define RCC_AHB1LPENR_ETHMACPTPLPEN   RCC_AHB1LPENR_ETHMACPTPLPEN_Msk
     
    #define RCC_AHB1LPENR_OTGHSLPEN_Pos   (29U)
     
    #define RCC_AHB1LPENR_OTGHSLPEN_Msk   (0x1UL << RCC_AHB1LPENR_OTGHSLPEN_Pos)
     
    #define RCC_AHB1LPENR_OTGHSLPEN   RCC_AHB1LPENR_OTGHSLPEN_Msk
     
    #define RCC_AHB1LPENR_OTGHSULPILPEN_Pos   (30U)
     
    #define RCC_AHB1LPENR_OTGHSULPILPEN_Msk   (0x1UL << RCC_AHB1LPENR_OTGHSULPILPEN_Pos)
     
    #define RCC_AHB1LPENR_OTGHSULPILPEN   RCC_AHB1LPENR_OTGHSULPILPEN_Msk
     
    #define RCC_AHB2LPENR_DCMILPEN_Pos   (0U)
     
    #define RCC_AHB2LPENR_DCMILPEN_Msk   (0x1UL << RCC_AHB2LPENR_DCMILPEN_Pos)
     
    #define RCC_AHB2LPENR_DCMILPEN   RCC_AHB2LPENR_DCMILPEN_Msk
     
    #define RCC_AHB2LPENR_RNGLPEN_Pos   (6U)
     
    #define RCC_AHB2LPENR_RNGLPEN_Msk   (0x1UL << RCC_AHB2LPENR_RNGLPEN_Pos)
     
    #define RCC_AHB2LPENR_RNGLPEN   RCC_AHB2LPENR_RNGLPEN_Msk
     
    #define RCC_AHB2LPENR_OTGFSLPEN_Pos   (7U)
     
    #define RCC_AHB2LPENR_OTGFSLPEN_Msk   (0x1UL << RCC_AHB2LPENR_OTGFSLPEN_Pos)
     
    #define RCC_AHB2LPENR_OTGFSLPEN   RCC_AHB2LPENR_OTGFSLPEN_Msk
     
    #define RCC_AHB3LPENR_FSMCLPEN_Pos   (0U)
     
    #define RCC_AHB3LPENR_FSMCLPEN_Msk   (0x1UL << RCC_AHB3LPENR_FSMCLPEN_Pos)
     
    #define RCC_AHB3LPENR_FSMCLPEN   RCC_AHB3LPENR_FSMCLPEN_Msk
     
    #define RCC_APB1LPENR_TIM2LPEN_Pos   (0U)
     
    #define RCC_APB1LPENR_TIM2LPEN_Msk   (0x1UL << RCC_APB1LPENR_TIM2LPEN_Pos)
     
    #define RCC_APB1LPENR_TIM2LPEN   RCC_APB1LPENR_TIM2LPEN_Msk
     
    #define RCC_APB1LPENR_TIM3LPEN_Pos   (1U)
     
    #define RCC_APB1LPENR_TIM3LPEN_Msk   (0x1UL << RCC_APB1LPENR_TIM3LPEN_Pos)
     
    #define RCC_APB1LPENR_TIM3LPEN   RCC_APB1LPENR_TIM3LPEN_Msk
     
    #define RCC_APB1LPENR_TIM4LPEN_Pos   (2U)
     
    #define RCC_APB1LPENR_TIM4LPEN_Msk   (0x1UL << RCC_APB1LPENR_TIM4LPEN_Pos)
     
    #define RCC_APB1LPENR_TIM4LPEN   RCC_APB1LPENR_TIM4LPEN_Msk
     
    #define RCC_APB1LPENR_TIM5LPEN_Pos   (3U)
     
    #define RCC_APB1LPENR_TIM5LPEN_Msk   (0x1UL << RCC_APB1LPENR_TIM5LPEN_Pos)
     
    #define RCC_APB1LPENR_TIM5LPEN   RCC_APB1LPENR_TIM5LPEN_Msk
     
    #define RCC_APB1LPENR_TIM6LPEN_Pos   (4U)
     
    #define RCC_APB1LPENR_TIM6LPEN_Msk   (0x1UL << RCC_APB1LPENR_TIM6LPEN_Pos)
     
    #define RCC_APB1LPENR_TIM6LPEN   RCC_APB1LPENR_TIM6LPEN_Msk
     
    #define RCC_APB1LPENR_TIM7LPEN_Pos   (5U)
     
    #define RCC_APB1LPENR_TIM7LPEN_Msk   (0x1UL << RCC_APB1LPENR_TIM7LPEN_Pos)
     
    #define RCC_APB1LPENR_TIM7LPEN   RCC_APB1LPENR_TIM7LPEN_Msk
     
    #define RCC_APB1LPENR_TIM12LPEN_Pos   (6U)
     
    #define RCC_APB1LPENR_TIM12LPEN_Msk   (0x1UL << RCC_APB1LPENR_TIM12LPEN_Pos)
     
    #define RCC_APB1LPENR_TIM12LPEN   RCC_APB1LPENR_TIM12LPEN_Msk
     
    #define RCC_APB1LPENR_TIM13LPEN_Pos   (7U)
     
    #define RCC_APB1LPENR_TIM13LPEN_Msk   (0x1UL << RCC_APB1LPENR_TIM13LPEN_Pos)
     
    #define RCC_APB1LPENR_TIM13LPEN   RCC_APB1LPENR_TIM13LPEN_Msk
     
    #define RCC_APB1LPENR_TIM14LPEN_Pos   (8U)
     
    #define RCC_APB1LPENR_TIM14LPEN_Msk   (0x1UL << RCC_APB1LPENR_TIM14LPEN_Pos)
     
    #define RCC_APB1LPENR_TIM14LPEN   RCC_APB1LPENR_TIM14LPEN_Msk
     
    #define RCC_APB1LPENR_WWDGLPEN_Pos   (11U)
     
    #define RCC_APB1LPENR_WWDGLPEN_Msk   (0x1UL << RCC_APB1LPENR_WWDGLPEN_Pos)
     
    #define RCC_APB1LPENR_WWDGLPEN   RCC_APB1LPENR_WWDGLPEN_Msk
     
    #define RCC_APB1LPENR_SPI2LPEN_Pos   (14U)
     
    #define RCC_APB1LPENR_SPI2LPEN_Msk   (0x1UL << RCC_APB1LPENR_SPI2LPEN_Pos)
     
    #define RCC_APB1LPENR_SPI2LPEN   RCC_APB1LPENR_SPI2LPEN_Msk
     
    #define RCC_APB1LPENR_SPI3LPEN_Pos   (15U)
     
    #define RCC_APB1LPENR_SPI3LPEN_Msk   (0x1UL << RCC_APB1LPENR_SPI3LPEN_Pos)
     
    #define RCC_APB1LPENR_SPI3LPEN   RCC_APB1LPENR_SPI3LPEN_Msk
     
    #define RCC_APB1LPENR_USART2LPEN_Pos   (17U)
     
    #define RCC_APB1LPENR_USART2LPEN_Msk   (0x1UL << RCC_APB1LPENR_USART2LPEN_Pos)
     
    #define RCC_APB1LPENR_USART2LPEN   RCC_APB1LPENR_USART2LPEN_Msk
     
    #define RCC_APB1LPENR_USART3LPEN_Pos   (18U)
     
    #define RCC_APB1LPENR_USART3LPEN_Msk   (0x1UL << RCC_APB1LPENR_USART3LPEN_Pos)
     
    #define RCC_APB1LPENR_USART3LPEN   RCC_APB1LPENR_USART3LPEN_Msk
     
    #define RCC_APB1LPENR_UART4LPEN_Pos   (19U)
     
    #define RCC_APB1LPENR_UART4LPEN_Msk   (0x1UL << RCC_APB1LPENR_UART4LPEN_Pos)
     
    #define RCC_APB1LPENR_UART4LPEN   RCC_APB1LPENR_UART4LPEN_Msk
     
    #define RCC_APB1LPENR_UART5LPEN_Pos   (20U)
     
    #define RCC_APB1LPENR_UART5LPEN_Msk   (0x1UL << RCC_APB1LPENR_UART5LPEN_Pos)
     
    #define RCC_APB1LPENR_UART5LPEN   RCC_APB1LPENR_UART5LPEN_Msk
     
    #define RCC_APB1LPENR_I2C1LPEN_Pos   (21U)
     
    #define RCC_APB1LPENR_I2C1LPEN_Msk   (0x1UL << RCC_APB1LPENR_I2C1LPEN_Pos)
     
    #define RCC_APB1LPENR_I2C1LPEN   RCC_APB1LPENR_I2C1LPEN_Msk
     
    #define RCC_APB1LPENR_I2C2LPEN_Pos   (22U)
     
    #define RCC_APB1LPENR_I2C2LPEN_Msk   (0x1UL << RCC_APB1LPENR_I2C2LPEN_Pos)
     
    #define RCC_APB1LPENR_I2C2LPEN   RCC_APB1LPENR_I2C2LPEN_Msk
     
    #define RCC_APB1LPENR_I2C3LPEN_Pos   (23U)
     
    #define RCC_APB1LPENR_I2C3LPEN_Msk   (0x1UL << RCC_APB1LPENR_I2C3LPEN_Pos)
     
    #define RCC_APB1LPENR_I2C3LPEN   RCC_APB1LPENR_I2C3LPEN_Msk
     
    #define RCC_APB1LPENR_CAN1LPEN_Pos   (25U)
     
    #define RCC_APB1LPENR_CAN1LPEN_Msk   (0x1UL << RCC_APB1LPENR_CAN1LPEN_Pos)
     
    #define RCC_APB1LPENR_CAN1LPEN   RCC_APB1LPENR_CAN1LPEN_Msk
     
    #define RCC_APB1LPENR_CAN2LPEN_Pos   (26U)
     
    #define RCC_APB1LPENR_CAN2LPEN_Msk   (0x1UL << RCC_APB1LPENR_CAN2LPEN_Pos)
     
    #define RCC_APB1LPENR_CAN2LPEN   RCC_APB1LPENR_CAN2LPEN_Msk
     
    #define RCC_APB1LPENR_PWRLPEN_Pos   (28U)
     
    #define RCC_APB1LPENR_PWRLPEN_Msk   (0x1UL << RCC_APB1LPENR_PWRLPEN_Pos)
     
    #define RCC_APB1LPENR_PWRLPEN   RCC_APB1LPENR_PWRLPEN_Msk
     
    #define RCC_APB1LPENR_DACLPEN_Pos   (29U)
     
    #define RCC_APB1LPENR_DACLPEN_Msk   (0x1UL << RCC_APB1LPENR_DACLPEN_Pos)
     
    #define RCC_APB1LPENR_DACLPEN   RCC_APB1LPENR_DACLPEN_Msk
     
    #define RCC_APB2LPENR_TIM1LPEN_Pos   (0U)
     
    #define RCC_APB2LPENR_TIM1LPEN_Msk   (0x1UL << RCC_APB2LPENR_TIM1LPEN_Pos)
     
    #define RCC_APB2LPENR_TIM1LPEN   RCC_APB2LPENR_TIM1LPEN_Msk
     
    #define RCC_APB2LPENR_TIM8LPEN_Pos   (1U)
     
    #define RCC_APB2LPENR_TIM8LPEN_Msk   (0x1UL << RCC_APB2LPENR_TIM8LPEN_Pos)
     
    #define RCC_APB2LPENR_TIM8LPEN   RCC_APB2LPENR_TIM8LPEN_Msk
     
    #define RCC_APB2LPENR_USART1LPEN_Pos   (4U)
     
    #define RCC_APB2LPENR_USART1LPEN_Msk   (0x1UL << RCC_APB2LPENR_USART1LPEN_Pos)
     
    #define RCC_APB2LPENR_USART1LPEN   RCC_APB2LPENR_USART1LPEN_Msk
     
    #define RCC_APB2LPENR_USART6LPEN_Pos   (5U)
     
    #define RCC_APB2LPENR_USART6LPEN_Msk   (0x1UL << RCC_APB2LPENR_USART6LPEN_Pos)
     
    #define RCC_APB2LPENR_USART6LPEN   RCC_APB2LPENR_USART6LPEN_Msk
     
    #define RCC_APB2LPENR_ADC1LPEN_Pos   (8U)
     
    #define RCC_APB2LPENR_ADC1LPEN_Msk   (0x1UL << RCC_APB2LPENR_ADC1LPEN_Pos)
     
    #define RCC_APB2LPENR_ADC1LPEN   RCC_APB2LPENR_ADC1LPEN_Msk
     
    #define RCC_APB2LPENR_ADC2LPEN_Pos   (9U)
     
    #define RCC_APB2LPENR_ADC2LPEN_Msk   (0x1UL << RCC_APB2LPENR_ADC2LPEN_Pos)
     
    #define RCC_APB2LPENR_ADC2LPEN   RCC_APB2LPENR_ADC2LPEN_Msk
     
    #define RCC_APB2LPENR_ADC3LPEN_Pos   (10U)
     
    #define RCC_APB2LPENR_ADC3LPEN_Msk   (0x1UL << RCC_APB2LPENR_ADC3LPEN_Pos)
     
    #define RCC_APB2LPENR_ADC3LPEN   RCC_APB2LPENR_ADC3LPEN_Msk
     
    #define RCC_APB2LPENR_SDIOLPEN_Pos   (11U)
     
    #define RCC_APB2LPENR_SDIOLPEN_Msk   (0x1UL << RCC_APB2LPENR_SDIOLPEN_Pos)
     
    #define RCC_APB2LPENR_SDIOLPEN   RCC_APB2LPENR_SDIOLPEN_Msk
     
    #define RCC_APB2LPENR_SPI1LPEN_Pos   (12U)
     
    #define RCC_APB2LPENR_SPI1LPEN_Msk   (0x1UL << RCC_APB2LPENR_SPI1LPEN_Pos)
     
    #define RCC_APB2LPENR_SPI1LPEN   RCC_APB2LPENR_SPI1LPEN_Msk
     
    #define RCC_APB2LPENR_SYSCFGLPEN_Pos   (14U)
     
    #define RCC_APB2LPENR_SYSCFGLPEN_Msk   (0x1UL << RCC_APB2LPENR_SYSCFGLPEN_Pos)
     
    #define RCC_APB2LPENR_SYSCFGLPEN   RCC_APB2LPENR_SYSCFGLPEN_Msk
     
    #define RCC_APB2LPENR_TIM9LPEN_Pos   (16U)
     
    #define RCC_APB2LPENR_TIM9LPEN_Msk   (0x1UL << RCC_APB2LPENR_TIM9LPEN_Pos)
     
    #define RCC_APB2LPENR_TIM9LPEN   RCC_APB2LPENR_TIM9LPEN_Msk
     
    #define RCC_APB2LPENR_TIM10LPEN_Pos   (17U)
     
    #define RCC_APB2LPENR_TIM10LPEN_Msk   (0x1UL << RCC_APB2LPENR_TIM10LPEN_Pos)
     
    #define RCC_APB2LPENR_TIM10LPEN   RCC_APB2LPENR_TIM10LPEN_Msk
     
    #define RCC_APB2LPENR_TIM11LPEN_Pos   (18U)
     
    #define RCC_APB2LPENR_TIM11LPEN_Msk   (0x1UL << RCC_APB2LPENR_TIM11LPEN_Pos)
     
    #define RCC_APB2LPENR_TIM11LPEN   RCC_APB2LPENR_TIM11LPEN_Msk
     
    #define RCC_BDCR_LSEON_Pos   (0U)
     
    #define RCC_BDCR_LSEON_Msk   (0x1UL << RCC_BDCR_LSEON_Pos)
     
    #define RCC_BDCR_LSEON   RCC_BDCR_LSEON_Msk
     
    #define RCC_BDCR_LSERDY_Pos   (1U)
     
    #define RCC_BDCR_LSERDY_Msk   (0x1UL << RCC_BDCR_LSERDY_Pos)
     
    #define RCC_BDCR_LSERDY   RCC_BDCR_LSERDY_Msk
     
    #define RCC_BDCR_LSEBYP_Pos   (2U)
     
    #define RCC_BDCR_LSEBYP_Msk   (0x1UL << RCC_BDCR_LSEBYP_Pos)
     
    #define RCC_BDCR_LSEBYP   RCC_BDCR_LSEBYP_Msk
     
    #define RCC_BDCR_RTCSEL_Pos   (8U)
     
    #define RCC_BDCR_RTCSEL_Msk   (0x3UL << RCC_BDCR_RTCSEL_Pos)
     
    #define RCC_BDCR_RTCSEL   RCC_BDCR_RTCSEL_Msk
     
    #define RCC_BDCR_RTCSEL_0   (0x1UL << RCC_BDCR_RTCSEL_Pos)
     
    #define RCC_BDCR_RTCSEL_1   (0x2UL << RCC_BDCR_RTCSEL_Pos)
     
    #define RCC_BDCR_RTCEN_Pos   (15U)
     
    #define RCC_BDCR_RTCEN_Msk   (0x1UL << RCC_BDCR_RTCEN_Pos)
     
    #define RCC_BDCR_RTCEN   RCC_BDCR_RTCEN_Msk
     
    #define RCC_BDCR_BDRST_Pos   (16U)
     
    #define RCC_BDCR_BDRST_Msk   (0x1UL << RCC_BDCR_BDRST_Pos)
     
    #define RCC_BDCR_BDRST   RCC_BDCR_BDRST_Msk
     
    #define RCC_CSR_LSION_Pos   (0U)
     
    #define RCC_CSR_LSION_Msk   (0x1UL << RCC_CSR_LSION_Pos)
     
    #define RCC_CSR_LSION   RCC_CSR_LSION_Msk
     
    #define RCC_CSR_LSIRDY_Pos   (1U)
     
    #define RCC_CSR_LSIRDY_Msk   (0x1UL << RCC_CSR_LSIRDY_Pos)
     
    #define RCC_CSR_LSIRDY   RCC_CSR_LSIRDY_Msk
     
    #define RCC_CSR_RMVF_Pos   (24U)
     
    #define RCC_CSR_RMVF_Msk   (0x1UL << RCC_CSR_RMVF_Pos)
     
    #define RCC_CSR_RMVF   RCC_CSR_RMVF_Msk
     
    #define RCC_CSR_BORRSTF_Pos   (25U)
     
    #define RCC_CSR_BORRSTF_Msk   (0x1UL << RCC_CSR_BORRSTF_Pos)
     
    #define RCC_CSR_BORRSTF   RCC_CSR_BORRSTF_Msk
     
    #define RCC_CSR_PINRSTF_Pos   (26U)
     
    #define RCC_CSR_PINRSTF_Msk   (0x1UL << RCC_CSR_PINRSTF_Pos)
     
    #define RCC_CSR_PINRSTF   RCC_CSR_PINRSTF_Msk
     
    #define RCC_CSR_PORRSTF_Pos   (27U)
     
    #define RCC_CSR_PORRSTF_Msk   (0x1UL << RCC_CSR_PORRSTF_Pos)
     
    #define RCC_CSR_PORRSTF   RCC_CSR_PORRSTF_Msk
     
    #define RCC_CSR_SFTRSTF_Pos   (28U)
     
    #define RCC_CSR_SFTRSTF_Msk   (0x1UL << RCC_CSR_SFTRSTF_Pos)
     
    #define RCC_CSR_SFTRSTF   RCC_CSR_SFTRSTF_Msk
     
    #define RCC_CSR_IWDGRSTF_Pos   (29U)
     
    #define RCC_CSR_IWDGRSTF_Msk   (0x1UL << RCC_CSR_IWDGRSTF_Pos)
     
    #define RCC_CSR_IWDGRSTF   RCC_CSR_IWDGRSTF_Msk
     
    #define RCC_CSR_WWDGRSTF_Pos   (30U)
     
    #define RCC_CSR_WWDGRSTF_Msk   (0x1UL << RCC_CSR_WWDGRSTF_Pos)
     
    #define RCC_CSR_WWDGRSTF   RCC_CSR_WWDGRSTF_Msk
     
    #define RCC_CSR_LPWRRSTF_Pos   (31U)
     
    #define RCC_CSR_LPWRRSTF_Msk   (0x1UL << RCC_CSR_LPWRRSTF_Pos)
     
    #define RCC_CSR_LPWRRSTF   RCC_CSR_LPWRRSTF_Msk
     
    #define RCC_CSR_PADRSTF   RCC_CSR_PINRSTF
     
    #define RCC_CSR_WDGRSTF   RCC_CSR_IWDGRSTF
     
    #define RCC_SSCGR_MODPER_Pos   (0U)
     
    #define RCC_SSCGR_MODPER_Msk   (0x1FFFUL << RCC_SSCGR_MODPER_Pos)
     
    #define RCC_SSCGR_MODPER   RCC_SSCGR_MODPER_Msk
     
    #define RCC_SSCGR_INCSTEP_Pos   (13U)
     
    #define RCC_SSCGR_INCSTEP_Msk   (0x7FFFUL << RCC_SSCGR_INCSTEP_Pos)
     
    #define RCC_SSCGR_INCSTEP   RCC_SSCGR_INCSTEP_Msk
     
    #define RCC_SSCGR_SPREADSEL_Pos   (30U)
     
    #define RCC_SSCGR_SPREADSEL_Msk   (0x1UL << RCC_SSCGR_SPREADSEL_Pos)
     
    #define RCC_SSCGR_SPREADSEL   RCC_SSCGR_SPREADSEL_Msk
     
    #define RCC_SSCGR_SSCGEN_Pos   (31U)
     
    #define RCC_SSCGR_SSCGEN_Msk   (0x1UL << RCC_SSCGR_SSCGEN_Pos)
     
    #define RCC_SSCGR_SSCGEN   RCC_SSCGR_SSCGEN_Msk
     
    #define RCC_PLLI2SCFGR_PLLI2SN_Pos   (6U)
     
    #define RCC_PLLI2SCFGR_PLLI2SN_Msk   (0x1FFUL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
     
    #define RCC_PLLI2SCFGR_PLLI2SN   RCC_PLLI2SCFGR_PLLI2SN_Msk
     
    #define RCC_PLLI2SCFGR_PLLI2SN_0   (0x001UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
     
    #define RCC_PLLI2SCFGR_PLLI2SN_1   (0x002UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
     
    #define RCC_PLLI2SCFGR_PLLI2SN_2   (0x004UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
     
    #define RCC_PLLI2SCFGR_PLLI2SN_3   (0x008UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
     
    #define RCC_PLLI2SCFGR_PLLI2SN_4   (0x010UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
     
    #define RCC_PLLI2SCFGR_PLLI2SN_5   (0x020UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
     
    #define RCC_PLLI2SCFGR_PLLI2SN_6   (0x040UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
     
    #define RCC_PLLI2SCFGR_PLLI2SN_7   (0x080UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
     
    #define RCC_PLLI2SCFGR_PLLI2SN_8   (0x100UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
     
    #define RCC_PLLI2SCFGR_PLLI2SR_Pos   (28U)
     
    #define RCC_PLLI2SCFGR_PLLI2SR_Msk   (0x7UL << RCC_PLLI2SCFGR_PLLI2SR_Pos)
     
    #define RCC_PLLI2SCFGR_PLLI2SR   RCC_PLLI2SCFGR_PLLI2SR_Msk
     
    #define RCC_PLLI2SCFGR_PLLI2SR_0   (0x1UL << RCC_PLLI2SCFGR_PLLI2SR_Pos)
     
    #define RCC_PLLI2SCFGR_PLLI2SR_1   (0x2UL << RCC_PLLI2SCFGR_PLLI2SR_Pos)
     
    #define RCC_PLLI2SCFGR_PLLI2SR_2   (0x4UL << RCC_PLLI2SCFGR_PLLI2SR_Pos)
     
    #define RNG_CR_RNGEN_Pos   (2U)
     
    #define RNG_CR_RNGEN_Msk   (0x1UL << RNG_CR_RNGEN_Pos)
     
    #define RNG_CR_RNGEN   RNG_CR_RNGEN_Msk
     
    #define RNG_CR_IE_Pos   (3U)
     
    #define RNG_CR_IE_Msk   (0x1UL << RNG_CR_IE_Pos)
     
    #define RNG_CR_IE   RNG_CR_IE_Msk
     
    #define RNG_SR_DRDY_Pos   (0U)
     
    #define RNG_SR_DRDY_Msk   (0x1UL << RNG_SR_DRDY_Pos)
     
    #define RNG_SR_DRDY   RNG_SR_DRDY_Msk
     
    #define RNG_SR_CECS_Pos   (1U)
     
    #define RNG_SR_CECS_Msk   (0x1UL << RNG_SR_CECS_Pos)
     
    #define RNG_SR_CECS   RNG_SR_CECS_Msk
     
    #define RNG_SR_SECS_Pos   (2U)
     
    #define RNG_SR_SECS_Msk   (0x1UL << RNG_SR_SECS_Pos)
     
    #define RNG_SR_SECS   RNG_SR_SECS_Msk
     
    #define RNG_SR_CEIS_Pos   (5U)
     
    #define RNG_SR_CEIS_Msk   (0x1UL << RNG_SR_CEIS_Pos)
     
    #define RNG_SR_CEIS   RNG_SR_CEIS_Msk
     
    #define RNG_SR_SEIS_Pos   (6U)
     
    #define RNG_SR_SEIS_Msk   (0x1UL << RNG_SR_SEIS_Pos)
     
    #define RNG_SR_SEIS   RNG_SR_SEIS_Msk
     
    #define RTC_TAMPER2_SUPPORT
     
    #define RTC_AF2_SUPPORT
     
    #define RTC_TR_PM_Pos   (22U)
     
    #define RTC_TR_PM_Msk   (0x1UL << RTC_TR_PM_Pos)
     
    #define RTC_TR_PM   RTC_TR_PM_Msk
     
    #define RTC_TR_HT_Pos   (20U)
     
    #define RTC_TR_HT_Msk   (0x3UL << RTC_TR_HT_Pos)
     
    #define RTC_TR_HT   RTC_TR_HT_Msk
     
    #define RTC_TR_HT_0   (0x1UL << RTC_TR_HT_Pos)
     
    #define RTC_TR_HT_1   (0x2UL << RTC_TR_HT_Pos)
     
    #define RTC_TR_HU_Pos   (16U)
     
    #define RTC_TR_HU_Msk   (0xFUL << RTC_TR_HU_Pos)
     
    #define RTC_TR_HU   RTC_TR_HU_Msk
     
    #define RTC_TR_HU_0   (0x1UL << RTC_TR_HU_Pos)
     
    #define RTC_TR_HU_1   (0x2UL << RTC_TR_HU_Pos)
     
    #define RTC_TR_HU_2   (0x4UL << RTC_TR_HU_Pos)
     
    #define RTC_TR_HU_3   (0x8UL << RTC_TR_HU_Pos)
     
    #define RTC_TR_MNT_Pos   (12U)
     
    #define RTC_TR_MNT_Msk   (0x7UL << RTC_TR_MNT_Pos)
     
    #define RTC_TR_MNT   RTC_TR_MNT_Msk
     
    #define RTC_TR_MNT_0   (0x1UL << RTC_TR_MNT_Pos)
     
    #define RTC_TR_MNT_1   (0x2UL << RTC_TR_MNT_Pos)
     
    #define RTC_TR_MNT_2   (0x4UL << RTC_TR_MNT_Pos)
     
    #define RTC_TR_MNU_Pos   (8U)
     
    #define RTC_TR_MNU_Msk   (0xFUL << RTC_TR_MNU_Pos)
     
    #define RTC_TR_MNU   RTC_TR_MNU_Msk
     
    #define RTC_TR_MNU_0   (0x1UL << RTC_TR_MNU_Pos)
     
    #define RTC_TR_MNU_1   (0x2UL << RTC_TR_MNU_Pos)
     
    #define RTC_TR_MNU_2   (0x4UL << RTC_TR_MNU_Pos)
     
    #define RTC_TR_MNU_3   (0x8UL << RTC_TR_MNU_Pos)
     
    #define RTC_TR_ST_Pos   (4U)
     
    #define RTC_TR_ST_Msk   (0x7UL << RTC_TR_ST_Pos)
     
    #define RTC_TR_ST   RTC_TR_ST_Msk
     
    #define RTC_TR_ST_0   (0x1UL << RTC_TR_ST_Pos)
     
    #define RTC_TR_ST_1   (0x2UL << RTC_TR_ST_Pos)
     
    #define RTC_TR_ST_2   (0x4UL << RTC_TR_ST_Pos)
     
    #define RTC_TR_SU_Pos   (0U)
     
    #define RTC_TR_SU_Msk   (0xFUL << RTC_TR_SU_Pos)
     
    #define RTC_TR_SU   RTC_TR_SU_Msk
     
    #define RTC_TR_SU_0   (0x1UL << RTC_TR_SU_Pos)
     
    #define RTC_TR_SU_1   (0x2UL << RTC_TR_SU_Pos)
     
    #define RTC_TR_SU_2   (0x4UL << RTC_TR_SU_Pos)
     
    #define RTC_TR_SU_3   (0x8UL << RTC_TR_SU_Pos)
     
    #define RTC_DR_YT_Pos   (20U)
     
    #define RTC_DR_YT_Msk   (0xFUL << RTC_DR_YT_Pos)
     
    #define RTC_DR_YT   RTC_DR_YT_Msk
     
    #define RTC_DR_YT_0   (0x1UL << RTC_DR_YT_Pos)
     
    #define RTC_DR_YT_1   (0x2UL << RTC_DR_YT_Pos)
     
    #define RTC_DR_YT_2   (0x4UL << RTC_DR_YT_Pos)
     
    #define RTC_DR_YT_3   (0x8UL << RTC_DR_YT_Pos)
     
    #define RTC_DR_YU_Pos   (16U)
     
    #define RTC_DR_YU_Msk   (0xFUL << RTC_DR_YU_Pos)
     
    #define RTC_DR_YU   RTC_DR_YU_Msk
     
    #define RTC_DR_YU_0   (0x1UL << RTC_DR_YU_Pos)
     
    #define RTC_DR_YU_1   (0x2UL << RTC_DR_YU_Pos)
     
    #define RTC_DR_YU_2   (0x4UL << RTC_DR_YU_Pos)
     
    #define RTC_DR_YU_3   (0x8UL << RTC_DR_YU_Pos)
     
    #define RTC_DR_WDU_Pos   (13U)
     
    #define RTC_DR_WDU_Msk   (0x7UL << RTC_DR_WDU_Pos)
     
    #define RTC_DR_WDU   RTC_DR_WDU_Msk
     
    #define RTC_DR_WDU_0   (0x1UL << RTC_DR_WDU_Pos)
     
    #define RTC_DR_WDU_1   (0x2UL << RTC_DR_WDU_Pos)
     
    #define RTC_DR_WDU_2   (0x4UL << RTC_DR_WDU_Pos)
     
    #define RTC_DR_MT_Pos   (12U)
     
    #define RTC_DR_MT_Msk   (0x1UL << RTC_DR_MT_Pos)
     
    #define RTC_DR_MT   RTC_DR_MT_Msk
     
    #define RTC_DR_MU_Pos   (8U)
     
    #define RTC_DR_MU_Msk   (0xFUL << RTC_DR_MU_Pos)
     
    #define RTC_DR_MU   RTC_DR_MU_Msk
     
    #define RTC_DR_MU_0   (0x1UL << RTC_DR_MU_Pos)
     
    #define RTC_DR_MU_1   (0x2UL << RTC_DR_MU_Pos)
     
    #define RTC_DR_MU_2   (0x4UL << RTC_DR_MU_Pos)
     
    #define RTC_DR_MU_3   (0x8UL << RTC_DR_MU_Pos)
     
    #define RTC_DR_DT_Pos   (4U)
     
    #define RTC_DR_DT_Msk   (0x3UL << RTC_DR_DT_Pos)
     
    #define RTC_DR_DT   RTC_DR_DT_Msk
     
    #define RTC_DR_DT_0   (0x1UL << RTC_DR_DT_Pos)
     
    #define RTC_DR_DT_1   (0x2UL << RTC_DR_DT_Pos)
     
    #define RTC_DR_DU_Pos   (0U)
     
    #define RTC_DR_DU_Msk   (0xFUL << RTC_DR_DU_Pos)
     
    #define RTC_DR_DU   RTC_DR_DU_Msk
     
    #define RTC_DR_DU_0   (0x1UL << RTC_DR_DU_Pos)
     
    #define RTC_DR_DU_1   (0x2UL << RTC_DR_DU_Pos)
     
    #define RTC_DR_DU_2   (0x4UL << RTC_DR_DU_Pos)
     
    #define RTC_DR_DU_3   (0x8UL << RTC_DR_DU_Pos)
     
    #define RTC_CR_COE_Pos   (23U)
     
    #define RTC_CR_COE_Msk   (0x1UL << RTC_CR_COE_Pos)
     
    #define RTC_CR_COE   RTC_CR_COE_Msk
     
    #define RTC_CR_OSEL_Pos   (21U)
     
    #define RTC_CR_OSEL_Msk   (0x3UL << RTC_CR_OSEL_Pos)
     
    #define RTC_CR_OSEL   RTC_CR_OSEL_Msk
     
    #define RTC_CR_OSEL_0   (0x1UL << RTC_CR_OSEL_Pos)
     
    #define RTC_CR_OSEL_1   (0x2UL << RTC_CR_OSEL_Pos)
     
    #define RTC_CR_POL_Pos   (20U)
     
    #define RTC_CR_POL_Msk   (0x1UL << RTC_CR_POL_Pos)
     
    #define RTC_CR_POL   RTC_CR_POL_Msk
     
    #define RTC_CR_COSEL_Pos   (19U)
     
    #define RTC_CR_COSEL_Msk   (0x1UL << RTC_CR_COSEL_Pos)
     
    #define RTC_CR_COSEL   RTC_CR_COSEL_Msk
     
    #define RTC_CR_BKP_Pos   (18U)
     
    #define RTC_CR_BKP_Msk   (0x1UL << RTC_CR_BKP_Pos)
     
    #define RTC_CR_BKP   RTC_CR_BKP_Msk
     
    #define RTC_CR_SUB1H_Pos   (17U)
     
    #define RTC_CR_SUB1H_Msk   (0x1UL << RTC_CR_SUB1H_Pos)
     
    #define RTC_CR_SUB1H   RTC_CR_SUB1H_Msk
     
    #define RTC_CR_ADD1H_Pos   (16U)
     
    #define RTC_CR_ADD1H_Msk   (0x1UL << RTC_CR_ADD1H_Pos)
     
    #define RTC_CR_ADD1H   RTC_CR_ADD1H_Msk
     
    #define RTC_CR_TSIE_Pos   (15U)
     
    #define RTC_CR_TSIE_Msk   (0x1UL << RTC_CR_TSIE_Pos)
     
    #define RTC_CR_TSIE   RTC_CR_TSIE_Msk
     
    #define RTC_CR_WUTIE_Pos   (14U)
     
    #define RTC_CR_WUTIE_Msk   (0x1UL << RTC_CR_WUTIE_Pos)
     
    #define RTC_CR_WUTIE   RTC_CR_WUTIE_Msk
     
    #define RTC_CR_ALRBIE_Pos   (13U)
     
    #define RTC_CR_ALRBIE_Msk   (0x1UL << RTC_CR_ALRBIE_Pos)
     
    #define RTC_CR_ALRBIE   RTC_CR_ALRBIE_Msk
     
    #define RTC_CR_ALRAIE_Pos   (12U)
     
    #define RTC_CR_ALRAIE_Msk   (0x1UL << RTC_CR_ALRAIE_Pos)
     
    #define RTC_CR_ALRAIE   RTC_CR_ALRAIE_Msk
     
    #define RTC_CR_TSE_Pos   (11U)
     
    #define RTC_CR_TSE_Msk   (0x1UL << RTC_CR_TSE_Pos)
     
    #define RTC_CR_TSE   RTC_CR_TSE_Msk
     
    #define RTC_CR_WUTE_Pos   (10U)
     
    #define RTC_CR_WUTE_Msk   (0x1UL << RTC_CR_WUTE_Pos)
     
    #define RTC_CR_WUTE   RTC_CR_WUTE_Msk
     
    #define RTC_CR_ALRBE_Pos   (9U)
     
    #define RTC_CR_ALRBE_Msk   (0x1UL << RTC_CR_ALRBE_Pos)
     
    #define RTC_CR_ALRBE   RTC_CR_ALRBE_Msk
     
    #define RTC_CR_ALRAE_Pos   (8U)
     
    #define RTC_CR_ALRAE_Msk   (0x1UL << RTC_CR_ALRAE_Pos)
     
    #define RTC_CR_ALRAE   RTC_CR_ALRAE_Msk
     
    #define RTC_CR_DCE_Pos   (7U)
     
    #define RTC_CR_DCE_Msk   (0x1UL << RTC_CR_DCE_Pos)
     
    #define RTC_CR_DCE   RTC_CR_DCE_Msk
     
    #define RTC_CR_FMT_Pos   (6U)
     
    #define RTC_CR_FMT_Msk   (0x1UL << RTC_CR_FMT_Pos)
     
    #define RTC_CR_FMT   RTC_CR_FMT_Msk
     
    #define RTC_CR_BYPSHAD_Pos   (5U)
     
    #define RTC_CR_BYPSHAD_Msk   (0x1UL << RTC_CR_BYPSHAD_Pos)
     
    #define RTC_CR_BYPSHAD   RTC_CR_BYPSHAD_Msk
     
    #define RTC_CR_REFCKON_Pos   (4U)
     
    #define RTC_CR_REFCKON_Msk   (0x1UL << RTC_CR_REFCKON_Pos)
     
    #define RTC_CR_REFCKON   RTC_CR_REFCKON_Msk
     
    #define RTC_CR_TSEDGE_Pos   (3U)
     
    #define RTC_CR_TSEDGE_Msk   (0x1UL << RTC_CR_TSEDGE_Pos)
     
    #define RTC_CR_TSEDGE   RTC_CR_TSEDGE_Msk
     
    #define RTC_CR_WUCKSEL_Pos   (0U)
     
    #define RTC_CR_WUCKSEL_Msk   (0x7UL << RTC_CR_WUCKSEL_Pos)
     
    #define RTC_CR_WUCKSEL   RTC_CR_WUCKSEL_Msk
     
    #define RTC_CR_WUCKSEL_0   (0x1UL << RTC_CR_WUCKSEL_Pos)
     
    #define RTC_CR_WUCKSEL_1   (0x2UL << RTC_CR_WUCKSEL_Pos)
     
    #define RTC_CR_WUCKSEL_2   (0x4UL << RTC_CR_WUCKSEL_Pos)
     
    #define RTC_CR_BCK   RTC_CR_BKP
     
    #define RTC_ISR_RECALPF_Pos   (16U)
     
    #define RTC_ISR_RECALPF_Msk   (0x1UL << RTC_ISR_RECALPF_Pos)
     
    #define RTC_ISR_RECALPF   RTC_ISR_RECALPF_Msk
     
    #define RTC_ISR_TAMP1F_Pos   (13U)
     
    #define RTC_ISR_TAMP1F_Msk   (0x1UL << RTC_ISR_TAMP1F_Pos)
     
    #define RTC_ISR_TAMP1F   RTC_ISR_TAMP1F_Msk
     
    #define RTC_ISR_TAMP2F_Pos   (14U)
     
    #define RTC_ISR_TAMP2F_Msk   (0x1UL << RTC_ISR_TAMP2F_Pos)
     
    #define RTC_ISR_TAMP2F   RTC_ISR_TAMP2F_Msk
     
    #define RTC_ISR_TSOVF_Pos   (12U)
     
    #define RTC_ISR_TSOVF_Msk   (0x1UL << RTC_ISR_TSOVF_Pos)
     
    #define RTC_ISR_TSOVF   RTC_ISR_TSOVF_Msk
     
    #define RTC_ISR_TSF_Pos   (11U)
     
    #define RTC_ISR_TSF_Msk   (0x1UL << RTC_ISR_TSF_Pos)
     
    #define RTC_ISR_TSF   RTC_ISR_TSF_Msk
     
    #define RTC_ISR_WUTF_Pos   (10U)
     
    #define RTC_ISR_WUTF_Msk   (0x1UL << RTC_ISR_WUTF_Pos)
     
    #define RTC_ISR_WUTF   RTC_ISR_WUTF_Msk
     
    #define RTC_ISR_ALRBF_Pos   (9U)
     
    #define RTC_ISR_ALRBF_Msk   (0x1UL << RTC_ISR_ALRBF_Pos)
     
    #define RTC_ISR_ALRBF   RTC_ISR_ALRBF_Msk
     
    #define RTC_ISR_ALRAF_Pos   (8U)
     
    #define RTC_ISR_ALRAF_Msk   (0x1UL << RTC_ISR_ALRAF_Pos)
     
    #define RTC_ISR_ALRAF   RTC_ISR_ALRAF_Msk
     
    #define RTC_ISR_INIT_Pos   (7U)
     
    #define RTC_ISR_INIT_Msk   (0x1UL << RTC_ISR_INIT_Pos)
     
    #define RTC_ISR_INIT   RTC_ISR_INIT_Msk
     
    #define RTC_ISR_INITF_Pos   (6U)
     
    #define RTC_ISR_INITF_Msk   (0x1UL << RTC_ISR_INITF_Pos)
     
    #define RTC_ISR_INITF   RTC_ISR_INITF_Msk
     
    #define RTC_ISR_RSF_Pos   (5U)
     
    #define RTC_ISR_RSF_Msk   (0x1UL << RTC_ISR_RSF_Pos)
     
    #define RTC_ISR_RSF   RTC_ISR_RSF_Msk
     
    #define RTC_ISR_INITS_Pos   (4U)
     
    #define RTC_ISR_INITS_Msk   (0x1UL << RTC_ISR_INITS_Pos)
     
    #define RTC_ISR_INITS   RTC_ISR_INITS_Msk
     
    #define RTC_ISR_SHPF_Pos   (3U)
     
    #define RTC_ISR_SHPF_Msk   (0x1UL << RTC_ISR_SHPF_Pos)
     
    #define RTC_ISR_SHPF   RTC_ISR_SHPF_Msk
     
    #define RTC_ISR_WUTWF_Pos   (2U)
     
    #define RTC_ISR_WUTWF_Msk   (0x1UL << RTC_ISR_WUTWF_Pos)
     
    #define RTC_ISR_WUTWF   RTC_ISR_WUTWF_Msk
     
    #define RTC_ISR_ALRBWF_Pos   (1U)
     
    #define RTC_ISR_ALRBWF_Msk   (0x1UL << RTC_ISR_ALRBWF_Pos)
     
    #define RTC_ISR_ALRBWF   RTC_ISR_ALRBWF_Msk
     
    #define RTC_ISR_ALRAWF_Pos   (0U)
     
    #define RTC_ISR_ALRAWF_Msk   (0x1UL << RTC_ISR_ALRAWF_Pos)
     
    #define RTC_ISR_ALRAWF   RTC_ISR_ALRAWF_Msk
     
    #define RTC_PRER_PREDIV_A_Pos   (16U)
     
    #define RTC_PRER_PREDIV_A_Msk   (0x7FUL << RTC_PRER_PREDIV_A_Pos)
     
    #define RTC_PRER_PREDIV_A   RTC_PRER_PREDIV_A_Msk
     
    #define RTC_PRER_PREDIV_S_Pos   (0U)
     
    #define RTC_PRER_PREDIV_S_Msk   (0x7FFFUL << RTC_PRER_PREDIV_S_Pos)
     
    #define RTC_PRER_PREDIV_S   RTC_PRER_PREDIV_S_Msk
     
    #define RTC_WUTR_WUT_Pos   (0U)
     
    #define RTC_WUTR_WUT_Msk   (0xFFFFUL << RTC_WUTR_WUT_Pos)
     
    #define RTC_WUTR_WUT   RTC_WUTR_WUT_Msk
     
    #define RTC_CALIBR_DCS_Pos   (7U)
     
    #define RTC_CALIBR_DCS_Msk   (0x1UL << RTC_CALIBR_DCS_Pos)
     
    #define RTC_CALIBR_DCS   RTC_CALIBR_DCS_Msk
     
    #define RTC_CALIBR_DC_Pos   (0U)
     
    #define RTC_CALIBR_DC_Msk   (0x1FUL << RTC_CALIBR_DC_Pos)
     
    #define RTC_CALIBR_DC   RTC_CALIBR_DC_Msk
     
    #define RTC_ALRMAR_MSK4_Pos   (31U)
     
    #define RTC_ALRMAR_MSK4_Msk   (0x1UL << RTC_ALRMAR_MSK4_Pos)
     
    #define RTC_ALRMAR_MSK4   RTC_ALRMAR_MSK4_Msk
     
    #define RTC_ALRMAR_WDSEL_Pos   (30U)
     
    #define RTC_ALRMAR_WDSEL_Msk   (0x1UL << RTC_ALRMAR_WDSEL_Pos)
     
    #define RTC_ALRMAR_WDSEL   RTC_ALRMAR_WDSEL_Msk
     
    #define RTC_ALRMAR_DT_Pos   (28U)
     
    #define RTC_ALRMAR_DT_Msk   (0x3UL << RTC_ALRMAR_DT_Pos)
     
    #define RTC_ALRMAR_DT   RTC_ALRMAR_DT_Msk
     
    #define RTC_ALRMAR_DT_0   (0x1UL << RTC_ALRMAR_DT_Pos)
     
    #define RTC_ALRMAR_DT_1   (0x2UL << RTC_ALRMAR_DT_Pos)
     
    #define RTC_ALRMAR_DU_Pos   (24U)
     
    #define RTC_ALRMAR_DU_Msk   (0xFUL << RTC_ALRMAR_DU_Pos)
     
    #define RTC_ALRMAR_DU   RTC_ALRMAR_DU_Msk
     
    #define RTC_ALRMAR_DU_0   (0x1UL << RTC_ALRMAR_DU_Pos)
     
    #define RTC_ALRMAR_DU_1   (0x2UL << RTC_ALRMAR_DU_Pos)
     
    #define RTC_ALRMAR_DU_2   (0x4UL << RTC_ALRMAR_DU_Pos)
     
    #define RTC_ALRMAR_DU_3   (0x8UL << RTC_ALRMAR_DU_Pos)
     
    #define RTC_ALRMAR_MSK3_Pos   (23U)
     
    #define RTC_ALRMAR_MSK3_Msk   (0x1UL << RTC_ALRMAR_MSK3_Pos)
     
    #define RTC_ALRMAR_MSK3   RTC_ALRMAR_MSK3_Msk
     
    #define RTC_ALRMAR_PM_Pos   (22U)
     
    #define RTC_ALRMAR_PM_Msk   (0x1UL << RTC_ALRMAR_PM_Pos)
     
    #define RTC_ALRMAR_PM   RTC_ALRMAR_PM_Msk
     
    #define RTC_ALRMAR_HT_Pos   (20U)
     
    #define RTC_ALRMAR_HT_Msk   (0x3UL << RTC_ALRMAR_HT_Pos)
     
    #define RTC_ALRMAR_HT   RTC_ALRMAR_HT_Msk
     
    #define RTC_ALRMAR_HT_0   (0x1UL << RTC_ALRMAR_HT_Pos)
     
    #define RTC_ALRMAR_HT_1   (0x2UL << RTC_ALRMAR_HT_Pos)
     
    #define RTC_ALRMAR_HU_Pos   (16U)
     
    #define RTC_ALRMAR_HU_Msk   (0xFUL << RTC_ALRMAR_HU_Pos)
     
    #define RTC_ALRMAR_HU   RTC_ALRMAR_HU_Msk
     
    #define RTC_ALRMAR_HU_0   (0x1UL << RTC_ALRMAR_HU_Pos)
     
    #define RTC_ALRMAR_HU_1   (0x2UL << RTC_ALRMAR_HU_Pos)
     
    #define RTC_ALRMAR_HU_2   (0x4UL << RTC_ALRMAR_HU_Pos)
     
    #define RTC_ALRMAR_HU_3   (0x8UL << RTC_ALRMAR_HU_Pos)
     
    #define RTC_ALRMAR_MSK2_Pos   (15U)
     
    #define RTC_ALRMAR_MSK2_Msk   (0x1UL << RTC_ALRMAR_MSK2_Pos)
     
    #define RTC_ALRMAR_MSK2   RTC_ALRMAR_MSK2_Msk
     
    #define RTC_ALRMAR_MNT_Pos   (12U)
     
    #define RTC_ALRMAR_MNT_Msk   (0x7UL << RTC_ALRMAR_MNT_Pos)
     
    #define RTC_ALRMAR_MNT   RTC_ALRMAR_MNT_Msk
     
    #define RTC_ALRMAR_MNT_0   (0x1UL << RTC_ALRMAR_MNT_Pos)
     
    #define RTC_ALRMAR_MNT_1   (0x2UL << RTC_ALRMAR_MNT_Pos)
     
    #define RTC_ALRMAR_MNT_2   (0x4UL << RTC_ALRMAR_MNT_Pos)
     
    #define RTC_ALRMAR_MNU_Pos   (8U)
     
    #define RTC_ALRMAR_MNU_Msk   (0xFUL << RTC_ALRMAR_MNU_Pos)
     
    #define RTC_ALRMAR_MNU   RTC_ALRMAR_MNU_Msk
     
    #define RTC_ALRMAR_MNU_0   (0x1UL << RTC_ALRMAR_MNU_Pos)
     
    #define RTC_ALRMAR_MNU_1   (0x2UL << RTC_ALRMAR_MNU_Pos)
     
    #define RTC_ALRMAR_MNU_2   (0x4UL << RTC_ALRMAR_MNU_Pos)
     
    #define RTC_ALRMAR_MNU_3   (0x8UL << RTC_ALRMAR_MNU_Pos)
     
    #define RTC_ALRMAR_MSK1_Pos   (7U)
     
    #define RTC_ALRMAR_MSK1_Msk   (0x1UL << RTC_ALRMAR_MSK1_Pos)
     
    #define RTC_ALRMAR_MSK1   RTC_ALRMAR_MSK1_Msk
     
    #define RTC_ALRMAR_ST_Pos   (4U)
     
    #define RTC_ALRMAR_ST_Msk   (0x7UL << RTC_ALRMAR_ST_Pos)
     
    #define RTC_ALRMAR_ST   RTC_ALRMAR_ST_Msk
     
    #define RTC_ALRMAR_ST_0   (0x1UL << RTC_ALRMAR_ST_Pos)
     
    #define RTC_ALRMAR_ST_1   (0x2UL << RTC_ALRMAR_ST_Pos)
     
    #define RTC_ALRMAR_ST_2   (0x4UL << RTC_ALRMAR_ST_Pos)
     
    #define RTC_ALRMAR_SU_Pos   (0U)
     
    #define RTC_ALRMAR_SU_Msk   (0xFUL << RTC_ALRMAR_SU_Pos)
     
    #define RTC_ALRMAR_SU   RTC_ALRMAR_SU_Msk
     
    #define RTC_ALRMAR_SU_0   (0x1UL << RTC_ALRMAR_SU_Pos)
     
    #define RTC_ALRMAR_SU_1   (0x2UL << RTC_ALRMAR_SU_Pos)
     
    #define RTC_ALRMAR_SU_2   (0x4UL << RTC_ALRMAR_SU_Pos)
     
    #define RTC_ALRMAR_SU_3   (0x8UL << RTC_ALRMAR_SU_Pos)
     
    #define RTC_ALRMBR_MSK4_Pos   (31U)
     
    #define RTC_ALRMBR_MSK4_Msk   (0x1UL << RTC_ALRMBR_MSK4_Pos)
     
    #define RTC_ALRMBR_MSK4   RTC_ALRMBR_MSK4_Msk
     
    #define RTC_ALRMBR_WDSEL_Pos   (30U)
     
    #define RTC_ALRMBR_WDSEL_Msk   (0x1UL << RTC_ALRMBR_WDSEL_Pos)
     
    #define RTC_ALRMBR_WDSEL   RTC_ALRMBR_WDSEL_Msk
     
    #define RTC_ALRMBR_DT_Pos   (28U)
     
    #define RTC_ALRMBR_DT_Msk   (0x3UL << RTC_ALRMBR_DT_Pos)
     
    #define RTC_ALRMBR_DT   RTC_ALRMBR_DT_Msk
     
    #define RTC_ALRMBR_DT_0   (0x1UL << RTC_ALRMBR_DT_Pos)
     
    #define RTC_ALRMBR_DT_1   (0x2UL << RTC_ALRMBR_DT_Pos)
     
    #define RTC_ALRMBR_DU_Pos   (24U)
     
    #define RTC_ALRMBR_DU_Msk   (0xFUL << RTC_ALRMBR_DU_Pos)
     
    #define RTC_ALRMBR_DU   RTC_ALRMBR_DU_Msk
     
    #define RTC_ALRMBR_DU_0   (0x1UL << RTC_ALRMBR_DU_Pos)
     
    #define RTC_ALRMBR_DU_1   (0x2UL << RTC_ALRMBR_DU_Pos)
     
    #define RTC_ALRMBR_DU_2   (0x4UL << RTC_ALRMBR_DU_Pos)
     
    #define RTC_ALRMBR_DU_3   (0x8UL << RTC_ALRMBR_DU_Pos)
     
    #define RTC_ALRMBR_MSK3_Pos   (23U)
     
    #define RTC_ALRMBR_MSK3_Msk   (0x1UL << RTC_ALRMBR_MSK3_Pos)
     
    #define RTC_ALRMBR_MSK3   RTC_ALRMBR_MSK3_Msk
     
    #define RTC_ALRMBR_PM_Pos   (22U)
     
    #define RTC_ALRMBR_PM_Msk   (0x1UL << RTC_ALRMBR_PM_Pos)
     
    #define RTC_ALRMBR_PM   RTC_ALRMBR_PM_Msk
     
    #define RTC_ALRMBR_HT_Pos   (20U)
     
    #define RTC_ALRMBR_HT_Msk   (0x3UL << RTC_ALRMBR_HT_Pos)
     
    #define RTC_ALRMBR_HT   RTC_ALRMBR_HT_Msk
     
    #define RTC_ALRMBR_HT_0   (0x1UL << RTC_ALRMBR_HT_Pos)
     
    #define RTC_ALRMBR_HT_1   (0x2UL << RTC_ALRMBR_HT_Pos)
     
    #define RTC_ALRMBR_HU_Pos   (16U)
     
    #define RTC_ALRMBR_HU_Msk   (0xFUL << RTC_ALRMBR_HU_Pos)
     
    #define RTC_ALRMBR_HU   RTC_ALRMBR_HU_Msk
     
    #define RTC_ALRMBR_HU_0   (0x1UL << RTC_ALRMBR_HU_Pos)
     
    #define RTC_ALRMBR_HU_1   (0x2UL << RTC_ALRMBR_HU_Pos)
     
    #define RTC_ALRMBR_HU_2   (0x4UL << RTC_ALRMBR_HU_Pos)
     
    #define RTC_ALRMBR_HU_3   (0x8UL << RTC_ALRMBR_HU_Pos)
     
    #define RTC_ALRMBR_MSK2_Pos   (15U)
     
    #define RTC_ALRMBR_MSK2_Msk   (0x1UL << RTC_ALRMBR_MSK2_Pos)
     
    #define RTC_ALRMBR_MSK2   RTC_ALRMBR_MSK2_Msk
     
    #define RTC_ALRMBR_MNT_Pos   (12U)
     
    #define RTC_ALRMBR_MNT_Msk   (0x7UL << RTC_ALRMBR_MNT_Pos)
     
    #define RTC_ALRMBR_MNT   RTC_ALRMBR_MNT_Msk
     
    #define RTC_ALRMBR_MNT_0   (0x1UL << RTC_ALRMBR_MNT_Pos)
     
    #define RTC_ALRMBR_MNT_1   (0x2UL << RTC_ALRMBR_MNT_Pos)
     
    #define RTC_ALRMBR_MNT_2   (0x4UL << RTC_ALRMBR_MNT_Pos)
     
    #define RTC_ALRMBR_MNU_Pos   (8U)
     
    #define RTC_ALRMBR_MNU_Msk   (0xFUL << RTC_ALRMBR_MNU_Pos)
     
    #define RTC_ALRMBR_MNU   RTC_ALRMBR_MNU_Msk
     
    #define RTC_ALRMBR_MNU_0   (0x1UL << RTC_ALRMBR_MNU_Pos)
     
    #define RTC_ALRMBR_MNU_1   (0x2UL << RTC_ALRMBR_MNU_Pos)
     
    #define RTC_ALRMBR_MNU_2   (0x4UL << RTC_ALRMBR_MNU_Pos)
     
    #define RTC_ALRMBR_MNU_3   (0x8UL << RTC_ALRMBR_MNU_Pos)
     
    #define RTC_ALRMBR_MSK1_Pos   (7U)
     
    #define RTC_ALRMBR_MSK1_Msk   (0x1UL << RTC_ALRMBR_MSK1_Pos)
     
    #define RTC_ALRMBR_MSK1   RTC_ALRMBR_MSK1_Msk
     
    #define RTC_ALRMBR_ST_Pos   (4U)
     
    #define RTC_ALRMBR_ST_Msk   (0x7UL << RTC_ALRMBR_ST_Pos)
     
    #define RTC_ALRMBR_ST   RTC_ALRMBR_ST_Msk
     
    #define RTC_ALRMBR_ST_0   (0x1UL << RTC_ALRMBR_ST_Pos)
     
    #define RTC_ALRMBR_ST_1   (0x2UL << RTC_ALRMBR_ST_Pos)
     
    #define RTC_ALRMBR_ST_2   (0x4UL << RTC_ALRMBR_ST_Pos)
     
    #define RTC_ALRMBR_SU_Pos   (0U)
     
    #define RTC_ALRMBR_SU_Msk   (0xFUL << RTC_ALRMBR_SU_Pos)
     
    #define RTC_ALRMBR_SU   RTC_ALRMBR_SU_Msk
     
    #define RTC_ALRMBR_SU_0   (0x1UL << RTC_ALRMBR_SU_Pos)
     
    #define RTC_ALRMBR_SU_1   (0x2UL << RTC_ALRMBR_SU_Pos)
     
    #define RTC_ALRMBR_SU_2   (0x4UL << RTC_ALRMBR_SU_Pos)
     
    #define RTC_ALRMBR_SU_3   (0x8UL << RTC_ALRMBR_SU_Pos)
     
    #define RTC_WPR_KEY_Pos   (0U)
     
    #define RTC_WPR_KEY_Msk   (0xFFUL << RTC_WPR_KEY_Pos)
     
    #define RTC_WPR_KEY   RTC_WPR_KEY_Msk
     
    #define RTC_SSR_SS_Pos   (0U)
     
    #define RTC_SSR_SS_Msk   (0xFFFFUL << RTC_SSR_SS_Pos)
     
    #define RTC_SSR_SS   RTC_SSR_SS_Msk
     
    #define RTC_SHIFTR_SUBFS_Pos   (0U)
     
    #define RTC_SHIFTR_SUBFS_Msk   (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos)
     
    #define RTC_SHIFTR_SUBFS   RTC_SHIFTR_SUBFS_Msk
     
    #define RTC_SHIFTR_ADD1S_Pos   (31U)
     
    #define RTC_SHIFTR_ADD1S_Msk   (0x1UL << RTC_SHIFTR_ADD1S_Pos)
     
    #define RTC_SHIFTR_ADD1S   RTC_SHIFTR_ADD1S_Msk
     
    #define RTC_TSTR_PM_Pos   (22U)
     
    #define RTC_TSTR_PM_Msk   (0x1UL << RTC_TSTR_PM_Pos)
     
    #define RTC_TSTR_PM   RTC_TSTR_PM_Msk
     
    #define RTC_TSTR_HT_Pos   (20U)
     
    #define RTC_TSTR_HT_Msk   (0x3UL << RTC_TSTR_HT_Pos)
     
    #define RTC_TSTR_HT   RTC_TSTR_HT_Msk
     
    #define RTC_TSTR_HT_0   (0x1UL << RTC_TSTR_HT_Pos)
     
    #define RTC_TSTR_HT_1   (0x2UL << RTC_TSTR_HT_Pos)
     
    #define RTC_TSTR_HU_Pos   (16U)
     
    #define RTC_TSTR_HU_Msk   (0xFUL << RTC_TSTR_HU_Pos)
     
    #define RTC_TSTR_HU   RTC_TSTR_HU_Msk
     
    #define RTC_TSTR_HU_0   (0x1UL << RTC_TSTR_HU_Pos)
     
    #define RTC_TSTR_HU_1   (0x2UL << RTC_TSTR_HU_Pos)
     
    #define RTC_TSTR_HU_2   (0x4UL << RTC_TSTR_HU_Pos)
     
    #define RTC_TSTR_HU_3   (0x8UL << RTC_TSTR_HU_Pos)
     
    #define RTC_TSTR_MNT_Pos   (12U)
     
    #define RTC_TSTR_MNT_Msk   (0x7UL << RTC_TSTR_MNT_Pos)
     
    #define RTC_TSTR_MNT   RTC_TSTR_MNT_Msk
     
    #define RTC_TSTR_MNT_0   (0x1UL << RTC_TSTR_MNT_Pos)
     
    #define RTC_TSTR_MNT_1   (0x2UL << RTC_TSTR_MNT_Pos)
     
    #define RTC_TSTR_MNT_2   (0x4UL << RTC_TSTR_MNT_Pos)
     
    #define RTC_TSTR_MNU_Pos   (8U)
     
    #define RTC_TSTR_MNU_Msk   (0xFUL << RTC_TSTR_MNU_Pos)
     
    #define RTC_TSTR_MNU   RTC_TSTR_MNU_Msk
     
    #define RTC_TSTR_MNU_0   (0x1UL << RTC_TSTR_MNU_Pos)
     
    #define RTC_TSTR_MNU_1   (0x2UL << RTC_TSTR_MNU_Pos)
     
    #define RTC_TSTR_MNU_2   (0x4UL << RTC_TSTR_MNU_Pos)
     
    #define RTC_TSTR_MNU_3   (0x8UL << RTC_TSTR_MNU_Pos)
     
    #define RTC_TSTR_ST_Pos   (4U)
     
    #define RTC_TSTR_ST_Msk   (0x7UL << RTC_TSTR_ST_Pos)
     
    #define RTC_TSTR_ST   RTC_TSTR_ST_Msk
     
    #define RTC_TSTR_ST_0   (0x1UL << RTC_TSTR_ST_Pos)
     
    #define RTC_TSTR_ST_1   (0x2UL << RTC_TSTR_ST_Pos)
     
    #define RTC_TSTR_ST_2   (0x4UL << RTC_TSTR_ST_Pos)
     
    #define RTC_TSTR_SU_Pos   (0U)
     
    #define RTC_TSTR_SU_Msk   (0xFUL << RTC_TSTR_SU_Pos)
     
    #define RTC_TSTR_SU   RTC_TSTR_SU_Msk
     
    #define RTC_TSTR_SU_0   (0x1UL << RTC_TSTR_SU_Pos)
     
    #define RTC_TSTR_SU_1   (0x2UL << RTC_TSTR_SU_Pos)
     
    #define RTC_TSTR_SU_2   (0x4UL << RTC_TSTR_SU_Pos)
     
    #define RTC_TSTR_SU_3   (0x8UL << RTC_TSTR_SU_Pos)
     
    #define RTC_TSDR_WDU_Pos   (13U)
     
    #define RTC_TSDR_WDU_Msk   (0x7UL << RTC_TSDR_WDU_Pos)
     
    #define RTC_TSDR_WDU   RTC_TSDR_WDU_Msk
     
    #define RTC_TSDR_WDU_0   (0x1UL << RTC_TSDR_WDU_Pos)
     
    #define RTC_TSDR_WDU_1   (0x2UL << RTC_TSDR_WDU_Pos)
     
    #define RTC_TSDR_WDU_2   (0x4UL << RTC_TSDR_WDU_Pos)
     
    #define RTC_TSDR_MT_Pos   (12U)
     
    #define RTC_TSDR_MT_Msk   (0x1UL << RTC_TSDR_MT_Pos)
     
    #define RTC_TSDR_MT   RTC_TSDR_MT_Msk
     
    #define RTC_TSDR_MU_Pos   (8U)
     
    #define RTC_TSDR_MU_Msk   (0xFUL << RTC_TSDR_MU_Pos)
     
    #define RTC_TSDR_MU   RTC_TSDR_MU_Msk
     
    #define RTC_TSDR_MU_0   (0x1UL << RTC_TSDR_MU_Pos)
     
    #define RTC_TSDR_MU_1   (0x2UL << RTC_TSDR_MU_Pos)
     
    #define RTC_TSDR_MU_2   (0x4UL << RTC_TSDR_MU_Pos)
     
    #define RTC_TSDR_MU_3   (0x8UL << RTC_TSDR_MU_Pos)
     
    #define RTC_TSDR_DT_Pos   (4U)
     
    #define RTC_TSDR_DT_Msk   (0x3UL << RTC_TSDR_DT_Pos)
     
    #define RTC_TSDR_DT   RTC_TSDR_DT_Msk
     
    #define RTC_TSDR_DT_0   (0x1UL << RTC_TSDR_DT_Pos)
     
    #define RTC_TSDR_DT_1   (0x2UL << RTC_TSDR_DT_Pos)
     
    #define RTC_TSDR_DU_Pos   (0U)
     
    #define RTC_TSDR_DU_Msk   (0xFUL << RTC_TSDR_DU_Pos)
     
    #define RTC_TSDR_DU   RTC_TSDR_DU_Msk
     
    #define RTC_TSDR_DU_0   (0x1UL << RTC_TSDR_DU_Pos)
     
    #define RTC_TSDR_DU_1   (0x2UL << RTC_TSDR_DU_Pos)
     
    #define RTC_TSDR_DU_2   (0x4UL << RTC_TSDR_DU_Pos)
     
    #define RTC_TSDR_DU_3   (0x8UL << RTC_TSDR_DU_Pos)
     
    #define RTC_TSSSR_SS_Pos   (0U)
     
    #define RTC_TSSSR_SS_Msk   (0xFFFFUL << RTC_TSSSR_SS_Pos)
     
    #define RTC_TSSSR_SS   RTC_TSSSR_SS_Msk
     
    #define RTC_CALR_CALP_Pos   (15U)
     
    #define RTC_CALR_CALP_Msk   (0x1UL << RTC_CALR_CALP_Pos)
     
    #define RTC_CALR_CALP   RTC_CALR_CALP_Msk
     
    #define RTC_CALR_CALW8_Pos   (14U)
     
    #define RTC_CALR_CALW8_Msk   (0x1UL << RTC_CALR_CALW8_Pos)
     
    #define RTC_CALR_CALW8   RTC_CALR_CALW8_Msk
     
    #define RTC_CALR_CALW16_Pos   (13U)
     
    #define RTC_CALR_CALW16_Msk   (0x1UL << RTC_CALR_CALW16_Pos)
     
    #define RTC_CALR_CALW16   RTC_CALR_CALW16_Msk
     
    #define RTC_CALR_CALM_Pos   (0U)
     
    #define RTC_CALR_CALM_Msk   (0x1FFUL << RTC_CALR_CALM_Pos)
     
    #define RTC_CALR_CALM   RTC_CALR_CALM_Msk
     
    #define RTC_CALR_CALM_0   (0x001UL << RTC_CALR_CALM_Pos)
     
    #define RTC_CALR_CALM_1   (0x002UL << RTC_CALR_CALM_Pos)
     
    #define RTC_CALR_CALM_2   (0x004UL << RTC_CALR_CALM_Pos)
     
    #define RTC_CALR_CALM_3   (0x008UL << RTC_CALR_CALM_Pos)
     
    #define RTC_CALR_CALM_4   (0x010UL << RTC_CALR_CALM_Pos)
     
    #define RTC_CALR_CALM_5   (0x020UL << RTC_CALR_CALM_Pos)
     
    #define RTC_CALR_CALM_6   (0x040UL << RTC_CALR_CALM_Pos)
     
    #define RTC_CALR_CALM_7   (0x080UL << RTC_CALR_CALM_Pos)
     
    #define RTC_CALR_CALM_8   (0x100UL << RTC_CALR_CALM_Pos)
     
    #define RTC_TAFCR_ALARMOUTTYPE_Pos   (18U)
     
    #define RTC_TAFCR_ALARMOUTTYPE_Msk   (0x1UL << RTC_TAFCR_ALARMOUTTYPE_Pos)
     
    #define RTC_TAFCR_ALARMOUTTYPE   RTC_TAFCR_ALARMOUTTYPE_Msk
     
    #define RTC_TAFCR_TSINSEL_Pos   (17U)
     
    #define RTC_TAFCR_TSINSEL_Msk   (0x1UL << RTC_TAFCR_TSINSEL_Pos)
     
    #define RTC_TAFCR_TSINSEL   RTC_TAFCR_TSINSEL_Msk
     
    #define RTC_TAFCR_TAMP1INSEL_Pos   (16U)
     
    #define RTC_TAFCR_TAMP1INSEL_Msk   (0x1UL << RTC_TAFCR_TAMP1INSEL_Pos)
     
    #define RTC_TAFCR_TAMP1INSEL   RTC_TAFCR_TAMP1INSEL_Msk
     
    #define RTC_TAFCR_TAMPPUDIS_Pos   (15U)
     
    #define RTC_TAFCR_TAMPPUDIS_Msk   (0x1UL << RTC_TAFCR_TAMPPUDIS_Pos)
     
    #define RTC_TAFCR_TAMPPUDIS   RTC_TAFCR_TAMPPUDIS_Msk
     
    #define RTC_TAFCR_TAMPPRCH_Pos   (13U)
     
    #define RTC_TAFCR_TAMPPRCH_Msk   (0x3UL << RTC_TAFCR_TAMPPRCH_Pos)
     
    #define RTC_TAFCR_TAMPPRCH   RTC_TAFCR_TAMPPRCH_Msk
     
    #define RTC_TAFCR_TAMPPRCH_0   (0x1UL << RTC_TAFCR_TAMPPRCH_Pos)
     
    #define RTC_TAFCR_TAMPPRCH_1   (0x2UL << RTC_TAFCR_TAMPPRCH_Pos)
     
    #define RTC_TAFCR_TAMPFLT_Pos   (11U)
     
    #define RTC_TAFCR_TAMPFLT_Msk   (0x3UL << RTC_TAFCR_TAMPFLT_Pos)
     
    #define RTC_TAFCR_TAMPFLT   RTC_TAFCR_TAMPFLT_Msk
     
    #define RTC_TAFCR_TAMPFLT_0   (0x1UL << RTC_TAFCR_TAMPFLT_Pos)
     
    #define RTC_TAFCR_TAMPFLT_1   (0x2UL << RTC_TAFCR_TAMPFLT_Pos)
     
    #define RTC_TAFCR_TAMPFREQ_Pos   (8U)
     
    #define RTC_TAFCR_TAMPFREQ_Msk   (0x7UL << RTC_TAFCR_TAMPFREQ_Pos)
     
    #define RTC_TAFCR_TAMPFREQ   RTC_TAFCR_TAMPFREQ_Msk
     
    #define RTC_TAFCR_TAMPFREQ_0   (0x1UL << RTC_TAFCR_TAMPFREQ_Pos)
     
    #define RTC_TAFCR_TAMPFREQ_1   (0x2UL << RTC_TAFCR_TAMPFREQ_Pos)
     
    #define RTC_TAFCR_TAMPFREQ_2   (0x4UL << RTC_TAFCR_TAMPFREQ_Pos)
     
    #define RTC_TAFCR_TAMPTS_Pos   (7U)
     
    #define RTC_TAFCR_TAMPTS_Msk   (0x1UL << RTC_TAFCR_TAMPTS_Pos)
     
    #define RTC_TAFCR_TAMPTS   RTC_TAFCR_TAMPTS_Msk
     
    #define RTC_TAFCR_TAMP2TRG_Pos   (4U)
     
    #define RTC_TAFCR_TAMP2TRG_Msk   (0x1UL << RTC_TAFCR_TAMP2TRG_Pos)
     
    #define RTC_TAFCR_TAMP2TRG   RTC_TAFCR_TAMP2TRG_Msk
     
    #define RTC_TAFCR_TAMP2E_Pos   (3U)
     
    #define RTC_TAFCR_TAMP2E_Msk   (0x1UL << RTC_TAFCR_TAMP2E_Pos)
     
    #define RTC_TAFCR_TAMP2E   RTC_TAFCR_TAMP2E_Msk
     
    #define RTC_TAFCR_TAMPIE_Pos   (2U)
     
    #define RTC_TAFCR_TAMPIE_Msk   (0x1UL << RTC_TAFCR_TAMPIE_Pos)
     
    #define RTC_TAFCR_TAMPIE   RTC_TAFCR_TAMPIE_Msk
     
    #define RTC_TAFCR_TAMP1TRG_Pos   (1U)
     
    #define RTC_TAFCR_TAMP1TRG_Msk   (0x1UL << RTC_TAFCR_TAMP1TRG_Pos)
     
    #define RTC_TAFCR_TAMP1TRG   RTC_TAFCR_TAMP1TRG_Msk
     
    #define RTC_TAFCR_TAMP1E_Pos   (0U)
     
    #define RTC_TAFCR_TAMP1E_Msk   (0x1UL << RTC_TAFCR_TAMP1E_Pos)
     
    #define RTC_TAFCR_TAMP1E   RTC_TAFCR_TAMP1E_Msk
     
    #define RTC_TAFCR_TAMPINSEL   RTC_TAFCR_TAMP1INSEL
     
    #define RTC_ALRMASSR_MASKSS_Pos   (24U)
     
    #define RTC_ALRMASSR_MASKSS_Msk   (0xFUL << RTC_ALRMASSR_MASKSS_Pos)
     
    #define RTC_ALRMASSR_MASKSS   RTC_ALRMASSR_MASKSS_Msk
     
    #define RTC_ALRMASSR_MASKSS_0   (0x1UL << RTC_ALRMASSR_MASKSS_Pos)
     
    #define RTC_ALRMASSR_MASKSS_1   (0x2UL << RTC_ALRMASSR_MASKSS_Pos)
     
    #define RTC_ALRMASSR_MASKSS_2   (0x4UL << RTC_ALRMASSR_MASKSS_Pos)
     
    #define RTC_ALRMASSR_MASKSS_3   (0x8UL << RTC_ALRMASSR_MASKSS_Pos)
     
    #define RTC_ALRMASSR_SS_Pos   (0U)
     
    #define RTC_ALRMASSR_SS_Msk   (0x7FFFUL << RTC_ALRMASSR_SS_Pos)
     
    #define RTC_ALRMASSR_SS   RTC_ALRMASSR_SS_Msk
     
    #define RTC_ALRMBSSR_MASKSS_Pos   (24U)
     
    #define RTC_ALRMBSSR_MASKSS_Msk   (0xFUL << RTC_ALRMBSSR_MASKSS_Pos)
     
    #define RTC_ALRMBSSR_MASKSS   RTC_ALRMBSSR_MASKSS_Msk
     
    #define RTC_ALRMBSSR_MASKSS_0   (0x1UL << RTC_ALRMBSSR_MASKSS_Pos)
     
    #define RTC_ALRMBSSR_MASKSS_1   (0x2UL << RTC_ALRMBSSR_MASKSS_Pos)
     
    #define RTC_ALRMBSSR_MASKSS_2   (0x4UL << RTC_ALRMBSSR_MASKSS_Pos)
     
    #define RTC_ALRMBSSR_MASKSS_3   (0x8UL << RTC_ALRMBSSR_MASKSS_Pos)
     
    #define RTC_ALRMBSSR_SS_Pos   (0U)
     
    #define RTC_ALRMBSSR_SS_Msk   (0x7FFFUL << RTC_ALRMBSSR_SS_Pos)
     
    #define RTC_ALRMBSSR_SS   RTC_ALRMBSSR_SS_Msk
     
    #define RTC_BKP0R_Pos   (0U)
     
    #define RTC_BKP0R_Msk   (0xFFFFFFFFUL << RTC_BKP0R_Pos)
     
    #define RTC_BKP0R   RTC_BKP0R_Msk
     
    #define RTC_BKP1R_Pos   (0U)
     
    #define RTC_BKP1R_Msk   (0xFFFFFFFFUL << RTC_BKP1R_Pos)
     
    #define RTC_BKP1R   RTC_BKP1R_Msk
     
    #define RTC_BKP2R_Pos   (0U)
     
    #define RTC_BKP2R_Msk   (0xFFFFFFFFUL << RTC_BKP2R_Pos)
     
    #define RTC_BKP2R   RTC_BKP2R_Msk
     
    #define RTC_BKP3R_Pos   (0U)
     
    #define RTC_BKP3R_Msk   (0xFFFFFFFFUL << RTC_BKP3R_Pos)
     
    #define RTC_BKP3R   RTC_BKP3R_Msk
     
    #define RTC_BKP4R_Pos   (0U)
     
    #define RTC_BKP4R_Msk   (0xFFFFFFFFUL << RTC_BKP4R_Pos)
     
    #define RTC_BKP4R   RTC_BKP4R_Msk
     
    #define RTC_BKP5R_Pos   (0U)
     
    #define RTC_BKP5R_Msk   (0xFFFFFFFFUL << RTC_BKP5R_Pos)
     
    #define RTC_BKP5R   RTC_BKP5R_Msk
     
    #define RTC_BKP6R_Pos   (0U)
     
    #define RTC_BKP6R_Msk   (0xFFFFFFFFUL << RTC_BKP6R_Pos)
     
    #define RTC_BKP6R   RTC_BKP6R_Msk
     
    #define RTC_BKP7R_Pos   (0U)
     
    #define RTC_BKP7R_Msk   (0xFFFFFFFFUL << RTC_BKP7R_Pos)
     
    #define RTC_BKP7R   RTC_BKP7R_Msk
     
    #define RTC_BKP8R_Pos   (0U)
     
    #define RTC_BKP8R_Msk   (0xFFFFFFFFUL << RTC_BKP8R_Pos)
     
    #define RTC_BKP8R   RTC_BKP8R_Msk
     
    #define RTC_BKP9R_Pos   (0U)
     
    #define RTC_BKP9R_Msk   (0xFFFFFFFFUL << RTC_BKP9R_Pos)
     
    #define RTC_BKP9R   RTC_BKP9R_Msk
     
    #define RTC_BKP10R_Pos   (0U)
     
    #define RTC_BKP10R_Msk   (0xFFFFFFFFUL << RTC_BKP10R_Pos)
     
    #define RTC_BKP10R   RTC_BKP10R_Msk
     
    #define RTC_BKP11R_Pos   (0U)
     
    #define RTC_BKP11R_Msk   (0xFFFFFFFFUL << RTC_BKP11R_Pos)
     
    #define RTC_BKP11R   RTC_BKP11R_Msk
     
    #define RTC_BKP12R_Pos   (0U)
     
    #define RTC_BKP12R_Msk   (0xFFFFFFFFUL << RTC_BKP12R_Pos)
     
    #define RTC_BKP12R   RTC_BKP12R_Msk
     
    #define RTC_BKP13R_Pos   (0U)
     
    #define RTC_BKP13R_Msk   (0xFFFFFFFFUL << RTC_BKP13R_Pos)
     
    #define RTC_BKP13R   RTC_BKP13R_Msk
     
    #define RTC_BKP14R_Pos   (0U)
     
    #define RTC_BKP14R_Msk   (0xFFFFFFFFUL << RTC_BKP14R_Pos)
     
    #define RTC_BKP14R   RTC_BKP14R_Msk
     
    #define RTC_BKP15R_Pos   (0U)
     
    #define RTC_BKP15R_Msk   (0xFFFFFFFFUL << RTC_BKP15R_Pos)
     
    #define RTC_BKP15R   RTC_BKP15R_Msk
     
    #define RTC_BKP16R_Pos   (0U)
     
    #define RTC_BKP16R_Msk   (0xFFFFFFFFUL << RTC_BKP16R_Pos)
     
    #define RTC_BKP16R   RTC_BKP16R_Msk
     
    #define RTC_BKP17R_Pos   (0U)
     
    #define RTC_BKP17R_Msk   (0xFFFFFFFFUL << RTC_BKP17R_Pos)
     
    #define RTC_BKP17R   RTC_BKP17R_Msk
     
    #define RTC_BKP18R_Pos   (0U)
     
    #define RTC_BKP18R_Msk   (0xFFFFFFFFUL << RTC_BKP18R_Pos)
     
    #define RTC_BKP18R   RTC_BKP18R_Msk
     
    #define RTC_BKP19R_Pos   (0U)
     
    #define RTC_BKP19R_Msk   (0xFFFFFFFFUL << RTC_BKP19R_Pos)
     
    #define RTC_BKP19R   RTC_BKP19R_Msk
     
    #define RTC_BKP_NUMBER   0x000000014U
     
    #define SDIO_POWER_PWRCTRL_Pos   (0U)
     
    #define SDIO_POWER_PWRCTRL_Msk   (0x3UL << SDIO_POWER_PWRCTRL_Pos)
     
    #define SDIO_POWER_PWRCTRL   SDIO_POWER_PWRCTRL_Msk
     
    #define SDIO_POWER_PWRCTRL_0   (0x1UL << SDIO_POWER_PWRCTRL_Pos)
     
    #define SDIO_POWER_PWRCTRL_1   (0x2UL << SDIO_POWER_PWRCTRL_Pos)
     
    #define SDIO_CLKCR_CLKDIV_Pos   (0U)
     
    #define SDIO_CLKCR_CLKDIV_Msk   (0xFFUL << SDIO_CLKCR_CLKDIV_Pos)
     
    #define SDIO_CLKCR_CLKDIV   SDIO_CLKCR_CLKDIV_Msk
     
    #define SDIO_CLKCR_CLKEN_Pos   (8U)
     
    #define SDIO_CLKCR_CLKEN_Msk   (0x1UL << SDIO_CLKCR_CLKEN_Pos)
     
    #define SDIO_CLKCR_CLKEN   SDIO_CLKCR_CLKEN_Msk
     
    #define SDIO_CLKCR_PWRSAV_Pos   (9U)
     
    #define SDIO_CLKCR_PWRSAV_Msk   (0x1UL << SDIO_CLKCR_PWRSAV_Pos)
     
    #define SDIO_CLKCR_PWRSAV   SDIO_CLKCR_PWRSAV_Msk
     
    #define SDIO_CLKCR_BYPASS_Pos   (10U)
     
    #define SDIO_CLKCR_BYPASS_Msk   (0x1UL << SDIO_CLKCR_BYPASS_Pos)
     
    #define SDIO_CLKCR_BYPASS   SDIO_CLKCR_BYPASS_Msk
     
    #define SDIO_CLKCR_WIDBUS_Pos   (11U)
     
    #define SDIO_CLKCR_WIDBUS_Msk   (0x3UL << SDIO_CLKCR_WIDBUS_Pos)
     
    #define SDIO_CLKCR_WIDBUS   SDIO_CLKCR_WIDBUS_Msk
     
    #define SDIO_CLKCR_WIDBUS_0   (0x1UL << SDIO_CLKCR_WIDBUS_Pos)
     
    #define SDIO_CLKCR_WIDBUS_1   (0x2UL << SDIO_CLKCR_WIDBUS_Pos)
     
    #define SDIO_CLKCR_NEGEDGE_Pos   (13U)
     
    #define SDIO_CLKCR_NEGEDGE_Msk   (0x1UL << SDIO_CLKCR_NEGEDGE_Pos)
     
    #define SDIO_CLKCR_NEGEDGE   SDIO_CLKCR_NEGEDGE_Msk
     
    #define SDIO_CLKCR_HWFC_EN_Pos   (14U)
     
    #define SDIO_CLKCR_HWFC_EN_Msk   (0x1UL << SDIO_CLKCR_HWFC_EN_Pos)
     
    #define SDIO_CLKCR_HWFC_EN   SDIO_CLKCR_HWFC_EN_Msk
     
    #define SDIO_ARG_CMDARG_Pos   (0U)
     
    #define SDIO_ARG_CMDARG_Msk   (0xFFFFFFFFUL << SDIO_ARG_CMDARG_Pos)
     
    #define SDIO_ARG_CMDARG   SDIO_ARG_CMDARG_Msk
     
    #define SDIO_CMD_CMDINDEX_Pos   (0U)
     
    #define SDIO_CMD_CMDINDEX_Msk   (0x3FUL << SDIO_CMD_CMDINDEX_Pos)
     
    #define SDIO_CMD_CMDINDEX   SDIO_CMD_CMDINDEX_Msk
     
    #define SDIO_CMD_WAITRESP_Pos   (6U)
     
    #define SDIO_CMD_WAITRESP_Msk   (0x3UL << SDIO_CMD_WAITRESP_Pos)
     
    #define SDIO_CMD_WAITRESP   SDIO_CMD_WAITRESP_Msk
     
    #define SDIO_CMD_WAITRESP_0   (0x1UL << SDIO_CMD_WAITRESP_Pos)
     
    #define SDIO_CMD_WAITRESP_1   (0x2UL << SDIO_CMD_WAITRESP_Pos)
     
    #define SDIO_CMD_WAITINT_Pos   (8U)
     
    #define SDIO_CMD_WAITINT_Msk   (0x1UL << SDIO_CMD_WAITINT_Pos)
     
    #define SDIO_CMD_WAITINT   SDIO_CMD_WAITINT_Msk
     
    #define SDIO_CMD_WAITPEND_Pos   (9U)
     
    #define SDIO_CMD_WAITPEND_Msk   (0x1UL << SDIO_CMD_WAITPEND_Pos)
     
    #define SDIO_CMD_WAITPEND   SDIO_CMD_WAITPEND_Msk
     
    #define SDIO_CMD_CPSMEN_Pos   (10U)
     
    #define SDIO_CMD_CPSMEN_Msk   (0x1UL << SDIO_CMD_CPSMEN_Pos)
     
    #define SDIO_CMD_CPSMEN   SDIO_CMD_CPSMEN_Msk
     
    #define SDIO_CMD_SDIOSUSPEND_Pos   (11U)
     
    #define SDIO_CMD_SDIOSUSPEND_Msk   (0x1UL << SDIO_CMD_SDIOSUSPEND_Pos)
     
    #define SDIO_CMD_SDIOSUSPEND   SDIO_CMD_SDIOSUSPEND_Msk
     
    #define SDIO_CMD_ENCMDCOMPL_Pos   (12U)
     
    #define SDIO_CMD_ENCMDCOMPL_Msk   (0x1UL << SDIO_CMD_ENCMDCOMPL_Pos)
     
    #define SDIO_CMD_ENCMDCOMPL   SDIO_CMD_ENCMDCOMPL_Msk
     
    #define SDIO_CMD_NIEN_Pos   (13U)
     
    #define SDIO_CMD_NIEN_Msk   (0x1UL << SDIO_CMD_NIEN_Pos)
     
    #define SDIO_CMD_NIEN   SDIO_CMD_NIEN_Msk
     
    #define SDIO_CMD_CEATACMD_Pos   (14U)
     
    #define SDIO_CMD_CEATACMD_Msk   (0x1UL << SDIO_CMD_CEATACMD_Pos)
     
    #define SDIO_CMD_CEATACMD   SDIO_CMD_CEATACMD_Msk
     
    #define SDIO_RESPCMD_RESPCMD_Pos   (0U)
     
    #define SDIO_RESPCMD_RESPCMD_Msk   (0x3FUL << SDIO_RESPCMD_RESPCMD_Pos)
     
    #define SDIO_RESPCMD_RESPCMD   SDIO_RESPCMD_RESPCMD_Msk
     
    #define SDIO_RESP0_CARDSTATUS0_Pos   (0U)
     
    #define SDIO_RESP0_CARDSTATUS0_Msk   (0xFFFFFFFFUL << SDIO_RESP0_CARDSTATUS0_Pos)
     
    #define SDIO_RESP0_CARDSTATUS0   SDIO_RESP0_CARDSTATUS0_Msk
     
    #define SDIO_RESP1_CARDSTATUS1_Pos   (0U)
     
    #define SDIO_RESP1_CARDSTATUS1_Msk   (0xFFFFFFFFUL << SDIO_RESP1_CARDSTATUS1_Pos)
     
    #define SDIO_RESP1_CARDSTATUS1   SDIO_RESP1_CARDSTATUS1_Msk
     
    #define SDIO_RESP2_CARDSTATUS2_Pos   (0U)
     
    #define SDIO_RESP2_CARDSTATUS2_Msk   (0xFFFFFFFFUL << SDIO_RESP2_CARDSTATUS2_Pos)
     
    #define SDIO_RESP2_CARDSTATUS2   SDIO_RESP2_CARDSTATUS2_Msk
     
    #define SDIO_RESP3_CARDSTATUS3_Pos   (0U)
     
    #define SDIO_RESP3_CARDSTATUS3_Msk   (0xFFFFFFFFUL << SDIO_RESP3_CARDSTATUS3_Pos)
     
    #define SDIO_RESP3_CARDSTATUS3   SDIO_RESP3_CARDSTATUS3_Msk
     
    #define SDIO_RESP4_CARDSTATUS4_Pos   (0U)
     
    #define SDIO_RESP4_CARDSTATUS4_Msk   (0xFFFFFFFFUL << SDIO_RESP4_CARDSTATUS4_Pos)
     
    #define SDIO_RESP4_CARDSTATUS4   SDIO_RESP4_CARDSTATUS4_Msk
     
    #define SDIO_DTIMER_DATATIME_Pos   (0U)
     
    #define SDIO_DTIMER_DATATIME_Msk   (0xFFFFFFFFUL << SDIO_DTIMER_DATATIME_Pos)
     
    #define SDIO_DTIMER_DATATIME   SDIO_DTIMER_DATATIME_Msk
     
    #define SDIO_DLEN_DATALENGTH_Pos   (0U)
     
    #define SDIO_DLEN_DATALENGTH_Msk   (0x1FFFFFFUL << SDIO_DLEN_DATALENGTH_Pos)
     
    #define SDIO_DLEN_DATALENGTH   SDIO_DLEN_DATALENGTH_Msk
     
    #define SDIO_DCTRL_DTEN_Pos   (0U)
     
    #define SDIO_DCTRL_DTEN_Msk   (0x1UL << SDIO_DCTRL_DTEN_Pos)
     
    #define SDIO_DCTRL_DTEN   SDIO_DCTRL_DTEN_Msk
     
    #define SDIO_DCTRL_DTDIR_Pos   (1U)
     
    #define SDIO_DCTRL_DTDIR_Msk   (0x1UL << SDIO_DCTRL_DTDIR_Pos)
     
    #define SDIO_DCTRL_DTDIR   SDIO_DCTRL_DTDIR_Msk
     
    #define SDIO_DCTRL_DTMODE_Pos   (2U)
     
    #define SDIO_DCTRL_DTMODE_Msk   (0x1UL << SDIO_DCTRL_DTMODE_Pos)
     
    #define SDIO_DCTRL_DTMODE   SDIO_DCTRL_DTMODE_Msk
     
    #define SDIO_DCTRL_DMAEN_Pos   (3U)
     
    #define SDIO_DCTRL_DMAEN_Msk   (0x1UL << SDIO_DCTRL_DMAEN_Pos)
     
    #define SDIO_DCTRL_DMAEN   SDIO_DCTRL_DMAEN_Msk
     
    #define SDIO_DCTRL_DBLOCKSIZE_Pos   (4U)
     
    #define SDIO_DCTRL_DBLOCKSIZE_Msk   (0xFUL << SDIO_DCTRL_DBLOCKSIZE_Pos)
     
    #define SDIO_DCTRL_DBLOCKSIZE   SDIO_DCTRL_DBLOCKSIZE_Msk
     
    #define SDIO_DCTRL_DBLOCKSIZE_0   (0x1UL << SDIO_DCTRL_DBLOCKSIZE_Pos)
     
    #define SDIO_DCTRL_DBLOCKSIZE_1   (0x2UL << SDIO_DCTRL_DBLOCKSIZE_Pos)
     
    #define SDIO_DCTRL_DBLOCKSIZE_2   (0x4UL << SDIO_DCTRL_DBLOCKSIZE_Pos)
     
    #define SDIO_DCTRL_DBLOCKSIZE_3   (0x8UL << SDIO_DCTRL_DBLOCKSIZE_Pos)
     
    #define SDIO_DCTRL_RWSTART_Pos   (8U)
     
    #define SDIO_DCTRL_RWSTART_Msk   (0x1UL << SDIO_DCTRL_RWSTART_Pos)
     
    #define SDIO_DCTRL_RWSTART   SDIO_DCTRL_RWSTART_Msk
     
    #define SDIO_DCTRL_RWSTOP_Pos   (9U)
     
    #define SDIO_DCTRL_RWSTOP_Msk   (0x1UL << SDIO_DCTRL_RWSTOP_Pos)
     
    #define SDIO_DCTRL_RWSTOP   SDIO_DCTRL_RWSTOP_Msk
     
    #define SDIO_DCTRL_RWMOD_Pos   (10U)
     
    #define SDIO_DCTRL_RWMOD_Msk   (0x1UL << SDIO_DCTRL_RWMOD_Pos)
     
    #define SDIO_DCTRL_RWMOD   SDIO_DCTRL_RWMOD_Msk
     
    #define SDIO_DCTRL_SDIOEN_Pos   (11U)
     
    #define SDIO_DCTRL_SDIOEN_Msk   (0x1UL << SDIO_DCTRL_SDIOEN_Pos)
     
    #define SDIO_DCTRL_SDIOEN   SDIO_DCTRL_SDIOEN_Msk
     
    #define SDIO_DCOUNT_DATACOUNT_Pos   (0U)
     
    #define SDIO_DCOUNT_DATACOUNT_Msk   (0x1FFFFFFUL << SDIO_DCOUNT_DATACOUNT_Pos)
     
    #define SDIO_DCOUNT_DATACOUNT   SDIO_DCOUNT_DATACOUNT_Msk
     
    #define SDIO_STA_CCRCFAIL_Pos   (0U)
     
    #define SDIO_STA_CCRCFAIL_Msk   (0x1UL << SDIO_STA_CCRCFAIL_Pos)
     
    #define SDIO_STA_CCRCFAIL   SDIO_STA_CCRCFAIL_Msk
     
    #define SDIO_STA_DCRCFAIL_Pos   (1U)
     
    #define SDIO_STA_DCRCFAIL_Msk   (0x1UL << SDIO_STA_DCRCFAIL_Pos)
     
    #define SDIO_STA_DCRCFAIL   SDIO_STA_DCRCFAIL_Msk
     
    #define SDIO_STA_CTIMEOUT_Pos   (2U)
     
    #define SDIO_STA_CTIMEOUT_Msk   (0x1UL << SDIO_STA_CTIMEOUT_Pos)
     
    #define SDIO_STA_CTIMEOUT   SDIO_STA_CTIMEOUT_Msk
     
    #define SDIO_STA_DTIMEOUT_Pos   (3U)
     
    #define SDIO_STA_DTIMEOUT_Msk   (0x1UL << SDIO_STA_DTIMEOUT_Pos)
     
    #define SDIO_STA_DTIMEOUT   SDIO_STA_DTIMEOUT_Msk
     
    #define SDIO_STA_TXUNDERR_Pos   (4U)
     
    #define SDIO_STA_TXUNDERR_Msk   (0x1UL << SDIO_STA_TXUNDERR_Pos)
     
    #define SDIO_STA_TXUNDERR   SDIO_STA_TXUNDERR_Msk
     
    #define SDIO_STA_RXOVERR_Pos   (5U)
     
    #define SDIO_STA_RXOVERR_Msk   (0x1UL << SDIO_STA_RXOVERR_Pos)
     
    #define SDIO_STA_RXOVERR   SDIO_STA_RXOVERR_Msk
     
    #define SDIO_STA_CMDREND_Pos   (6U)
     
    #define SDIO_STA_CMDREND_Msk   (0x1UL << SDIO_STA_CMDREND_Pos)
     
    #define SDIO_STA_CMDREND   SDIO_STA_CMDREND_Msk
     
    #define SDIO_STA_CMDSENT_Pos   (7U)
     
    #define SDIO_STA_CMDSENT_Msk   (0x1UL << SDIO_STA_CMDSENT_Pos)
     
    #define SDIO_STA_CMDSENT   SDIO_STA_CMDSENT_Msk
     
    #define SDIO_STA_DATAEND_Pos   (8U)
     
    #define SDIO_STA_DATAEND_Msk   (0x1UL << SDIO_STA_DATAEND_Pos)
     
    #define SDIO_STA_DATAEND   SDIO_STA_DATAEND_Msk
     
    #define SDIO_STA_STBITERR_Pos   (9U)
     
    #define SDIO_STA_STBITERR_Msk   (0x1UL << SDIO_STA_STBITERR_Pos)
     
    #define SDIO_STA_STBITERR   SDIO_STA_STBITERR_Msk
     
    #define SDIO_STA_DBCKEND_Pos   (10U)
     
    #define SDIO_STA_DBCKEND_Msk   (0x1UL << SDIO_STA_DBCKEND_Pos)
     
    #define SDIO_STA_DBCKEND   SDIO_STA_DBCKEND_Msk
     
    #define SDIO_STA_CMDACT_Pos   (11U)
     
    #define SDIO_STA_CMDACT_Msk   (0x1UL << SDIO_STA_CMDACT_Pos)
     
    #define SDIO_STA_CMDACT   SDIO_STA_CMDACT_Msk
     
    #define SDIO_STA_TXACT_Pos   (12U)
     
    #define SDIO_STA_TXACT_Msk   (0x1UL << SDIO_STA_TXACT_Pos)
     
    #define SDIO_STA_TXACT   SDIO_STA_TXACT_Msk
     
    #define SDIO_STA_RXACT_Pos   (13U)
     
    #define SDIO_STA_RXACT_Msk   (0x1UL << SDIO_STA_RXACT_Pos)
     
    #define SDIO_STA_RXACT   SDIO_STA_RXACT_Msk
     
    #define SDIO_STA_TXFIFOHE_Pos   (14U)
     
    #define SDIO_STA_TXFIFOHE_Msk   (0x1UL << SDIO_STA_TXFIFOHE_Pos)
     
    #define SDIO_STA_TXFIFOHE   SDIO_STA_TXFIFOHE_Msk
     
    #define SDIO_STA_RXFIFOHF_Pos   (15U)
     
    #define SDIO_STA_RXFIFOHF_Msk   (0x1UL << SDIO_STA_RXFIFOHF_Pos)
     
    #define SDIO_STA_RXFIFOHF   SDIO_STA_RXFIFOHF_Msk
     
    #define SDIO_STA_TXFIFOF_Pos   (16U)
     
    #define SDIO_STA_TXFIFOF_Msk   (0x1UL << SDIO_STA_TXFIFOF_Pos)
     
    #define SDIO_STA_TXFIFOF   SDIO_STA_TXFIFOF_Msk
     
    #define SDIO_STA_RXFIFOF_Pos   (17U)
     
    #define SDIO_STA_RXFIFOF_Msk   (0x1UL << SDIO_STA_RXFIFOF_Pos)
     
    #define SDIO_STA_RXFIFOF   SDIO_STA_RXFIFOF_Msk
     
    #define SDIO_STA_TXFIFOE_Pos   (18U)
     
    #define SDIO_STA_TXFIFOE_Msk   (0x1UL << SDIO_STA_TXFIFOE_Pos)
     
    #define SDIO_STA_TXFIFOE   SDIO_STA_TXFIFOE_Msk
     
    #define SDIO_STA_RXFIFOE_Pos   (19U)
     
    #define SDIO_STA_RXFIFOE_Msk   (0x1UL << SDIO_STA_RXFIFOE_Pos)
     
    #define SDIO_STA_RXFIFOE   SDIO_STA_RXFIFOE_Msk
     
    #define SDIO_STA_TXDAVL_Pos   (20U)
     
    #define SDIO_STA_TXDAVL_Msk   (0x1UL << SDIO_STA_TXDAVL_Pos)
     
    #define SDIO_STA_TXDAVL   SDIO_STA_TXDAVL_Msk
     
    #define SDIO_STA_RXDAVL_Pos   (21U)
     
    #define SDIO_STA_RXDAVL_Msk   (0x1UL << SDIO_STA_RXDAVL_Pos)
     
    #define SDIO_STA_RXDAVL   SDIO_STA_RXDAVL_Msk
     
    #define SDIO_STA_SDIOIT_Pos   (22U)
     
    #define SDIO_STA_SDIOIT_Msk   (0x1UL << SDIO_STA_SDIOIT_Pos)
     
    #define SDIO_STA_SDIOIT   SDIO_STA_SDIOIT_Msk
     
    #define SDIO_STA_CEATAEND_Pos   (23U)
     
    #define SDIO_STA_CEATAEND_Msk   (0x1UL << SDIO_STA_CEATAEND_Pos)
     
    #define SDIO_STA_CEATAEND   SDIO_STA_CEATAEND_Msk
     
    #define SDIO_ICR_CCRCFAILC_Pos   (0U)
     
    #define SDIO_ICR_CCRCFAILC_Msk   (0x1UL << SDIO_ICR_CCRCFAILC_Pos)
     
    #define SDIO_ICR_CCRCFAILC   SDIO_ICR_CCRCFAILC_Msk
     
    #define SDIO_ICR_DCRCFAILC_Pos   (1U)
     
    #define SDIO_ICR_DCRCFAILC_Msk   (0x1UL << SDIO_ICR_DCRCFAILC_Pos)
     
    #define SDIO_ICR_DCRCFAILC   SDIO_ICR_DCRCFAILC_Msk
     
    #define SDIO_ICR_CTIMEOUTC_Pos   (2U)
     
    #define SDIO_ICR_CTIMEOUTC_Msk   (0x1UL << SDIO_ICR_CTIMEOUTC_Pos)
     
    #define SDIO_ICR_CTIMEOUTC   SDIO_ICR_CTIMEOUTC_Msk
     
    #define SDIO_ICR_DTIMEOUTC_Pos   (3U)
     
    #define SDIO_ICR_DTIMEOUTC_Msk   (0x1UL << SDIO_ICR_DTIMEOUTC_Pos)
     
    #define SDIO_ICR_DTIMEOUTC   SDIO_ICR_DTIMEOUTC_Msk
     
    #define SDIO_ICR_TXUNDERRC_Pos   (4U)
     
    #define SDIO_ICR_TXUNDERRC_Msk   (0x1UL << SDIO_ICR_TXUNDERRC_Pos)
     
    #define SDIO_ICR_TXUNDERRC   SDIO_ICR_TXUNDERRC_Msk
     
    #define SDIO_ICR_RXOVERRC_Pos   (5U)
     
    #define SDIO_ICR_RXOVERRC_Msk   (0x1UL << SDIO_ICR_RXOVERRC_Pos)
     
    #define SDIO_ICR_RXOVERRC   SDIO_ICR_RXOVERRC_Msk
     
    #define SDIO_ICR_CMDRENDC_Pos   (6U)
     
    #define SDIO_ICR_CMDRENDC_Msk   (0x1UL << SDIO_ICR_CMDRENDC_Pos)
     
    #define SDIO_ICR_CMDRENDC   SDIO_ICR_CMDRENDC_Msk
     
    #define SDIO_ICR_CMDSENTC_Pos   (7U)
     
    #define SDIO_ICR_CMDSENTC_Msk   (0x1UL << SDIO_ICR_CMDSENTC_Pos)
     
    #define SDIO_ICR_CMDSENTC   SDIO_ICR_CMDSENTC_Msk
     
    #define SDIO_ICR_DATAENDC_Pos   (8U)
     
    #define SDIO_ICR_DATAENDC_Msk   (0x1UL << SDIO_ICR_DATAENDC_Pos)
     
    #define SDIO_ICR_DATAENDC   SDIO_ICR_DATAENDC_Msk
     
    #define SDIO_ICR_STBITERRC_Pos   (9U)
     
    #define SDIO_ICR_STBITERRC_Msk   (0x1UL << SDIO_ICR_STBITERRC_Pos)
     
    #define SDIO_ICR_STBITERRC   SDIO_ICR_STBITERRC_Msk
     
    #define SDIO_ICR_DBCKENDC_Pos   (10U)
     
    #define SDIO_ICR_DBCKENDC_Msk   (0x1UL << SDIO_ICR_DBCKENDC_Pos)
     
    #define SDIO_ICR_DBCKENDC   SDIO_ICR_DBCKENDC_Msk
     
    #define SDIO_ICR_SDIOITC_Pos   (22U)
     
    #define SDIO_ICR_SDIOITC_Msk   (0x1UL << SDIO_ICR_SDIOITC_Pos)
     
    #define SDIO_ICR_SDIOITC   SDIO_ICR_SDIOITC_Msk
     
    #define SDIO_ICR_CEATAENDC_Pos   (23U)
     
    #define SDIO_ICR_CEATAENDC_Msk   (0x1UL << SDIO_ICR_CEATAENDC_Pos)
     
    #define SDIO_ICR_CEATAENDC   SDIO_ICR_CEATAENDC_Msk
     
    #define SDIO_MASK_CCRCFAILIE_Pos   (0U)
     
    #define SDIO_MASK_CCRCFAILIE_Msk   (0x1UL << SDIO_MASK_CCRCFAILIE_Pos)
     
    #define SDIO_MASK_CCRCFAILIE   SDIO_MASK_CCRCFAILIE_Msk
     
    #define SDIO_MASK_DCRCFAILIE_Pos   (1U)
     
    #define SDIO_MASK_DCRCFAILIE_Msk   (0x1UL << SDIO_MASK_DCRCFAILIE_Pos)
     
    #define SDIO_MASK_DCRCFAILIE   SDIO_MASK_DCRCFAILIE_Msk
     
    #define SDIO_MASK_CTIMEOUTIE_Pos   (2U)
     
    #define SDIO_MASK_CTIMEOUTIE_Msk   (0x1UL << SDIO_MASK_CTIMEOUTIE_Pos)
     
    #define SDIO_MASK_CTIMEOUTIE   SDIO_MASK_CTIMEOUTIE_Msk
     
    #define SDIO_MASK_DTIMEOUTIE_Pos   (3U)
     
    #define SDIO_MASK_DTIMEOUTIE_Msk   (0x1UL << SDIO_MASK_DTIMEOUTIE_Pos)
     
    #define SDIO_MASK_DTIMEOUTIE   SDIO_MASK_DTIMEOUTIE_Msk
     
    #define SDIO_MASK_TXUNDERRIE_Pos   (4U)
     
    #define SDIO_MASK_TXUNDERRIE_Msk   (0x1UL << SDIO_MASK_TXUNDERRIE_Pos)
     
    #define SDIO_MASK_TXUNDERRIE   SDIO_MASK_TXUNDERRIE_Msk
     
    #define SDIO_MASK_RXOVERRIE_Pos   (5U)
     
    #define SDIO_MASK_RXOVERRIE_Msk   (0x1UL << SDIO_MASK_RXOVERRIE_Pos)
     
    #define SDIO_MASK_RXOVERRIE   SDIO_MASK_RXOVERRIE_Msk
     
    #define SDIO_MASK_CMDRENDIE_Pos   (6U)
     
    #define SDIO_MASK_CMDRENDIE_Msk   (0x1UL << SDIO_MASK_CMDRENDIE_Pos)
     
    #define SDIO_MASK_CMDRENDIE   SDIO_MASK_CMDRENDIE_Msk
     
    #define SDIO_MASK_CMDSENTIE_Pos   (7U)
     
    #define SDIO_MASK_CMDSENTIE_Msk   (0x1UL << SDIO_MASK_CMDSENTIE_Pos)
     
    #define SDIO_MASK_CMDSENTIE   SDIO_MASK_CMDSENTIE_Msk
     
    #define SDIO_MASK_DATAENDIE_Pos   (8U)
     
    #define SDIO_MASK_DATAENDIE_Msk   (0x1UL << SDIO_MASK_DATAENDIE_Pos)
     
    #define SDIO_MASK_DATAENDIE   SDIO_MASK_DATAENDIE_Msk
     
    #define SDIO_MASK_STBITERRIE_Pos   (9U)
     
    #define SDIO_MASK_STBITERRIE_Msk   (0x1UL << SDIO_MASK_STBITERRIE_Pos)
     
    #define SDIO_MASK_STBITERRIE   SDIO_MASK_STBITERRIE_Msk
     
    #define SDIO_MASK_DBCKENDIE_Pos   (10U)
     
    #define SDIO_MASK_DBCKENDIE_Msk   (0x1UL << SDIO_MASK_DBCKENDIE_Pos)
     
    #define SDIO_MASK_DBCKENDIE   SDIO_MASK_DBCKENDIE_Msk
     
    #define SDIO_MASK_CMDACTIE_Pos   (11U)
     
    #define SDIO_MASK_CMDACTIE_Msk   (0x1UL << SDIO_MASK_CMDACTIE_Pos)
     
    #define SDIO_MASK_CMDACTIE   SDIO_MASK_CMDACTIE_Msk
     
    #define SDIO_MASK_TXACTIE_Pos   (12U)
     
    #define SDIO_MASK_TXACTIE_Msk   (0x1UL << SDIO_MASK_TXACTIE_Pos)
     
    #define SDIO_MASK_TXACTIE   SDIO_MASK_TXACTIE_Msk
     
    #define SDIO_MASK_RXACTIE_Pos   (13U)
     
    #define SDIO_MASK_RXACTIE_Msk   (0x1UL << SDIO_MASK_RXACTIE_Pos)
     
    #define SDIO_MASK_RXACTIE   SDIO_MASK_RXACTIE_Msk
     
    #define SDIO_MASK_TXFIFOHEIE_Pos   (14U)
     
    #define SDIO_MASK_TXFIFOHEIE_Msk   (0x1UL << SDIO_MASK_TXFIFOHEIE_Pos)
     
    #define SDIO_MASK_TXFIFOHEIE   SDIO_MASK_TXFIFOHEIE_Msk
     
    #define SDIO_MASK_RXFIFOHFIE_Pos   (15U)
     
    #define SDIO_MASK_RXFIFOHFIE_Msk   (0x1UL << SDIO_MASK_RXFIFOHFIE_Pos)
     
    #define SDIO_MASK_RXFIFOHFIE   SDIO_MASK_RXFIFOHFIE_Msk
     
    #define SDIO_MASK_TXFIFOFIE_Pos   (16U)
     
    #define SDIO_MASK_TXFIFOFIE_Msk   (0x1UL << SDIO_MASK_TXFIFOFIE_Pos)
     
    #define SDIO_MASK_TXFIFOFIE   SDIO_MASK_TXFIFOFIE_Msk
     
    #define SDIO_MASK_RXFIFOFIE_Pos   (17U)
     
    #define SDIO_MASK_RXFIFOFIE_Msk   (0x1UL << SDIO_MASK_RXFIFOFIE_Pos)
     
    #define SDIO_MASK_RXFIFOFIE   SDIO_MASK_RXFIFOFIE_Msk
     
    #define SDIO_MASK_TXFIFOEIE_Pos   (18U)
     
    #define SDIO_MASK_TXFIFOEIE_Msk   (0x1UL << SDIO_MASK_TXFIFOEIE_Pos)
     
    #define SDIO_MASK_TXFIFOEIE   SDIO_MASK_TXFIFOEIE_Msk
     
    #define SDIO_MASK_RXFIFOEIE_Pos   (19U)
     
    #define SDIO_MASK_RXFIFOEIE_Msk   (0x1UL << SDIO_MASK_RXFIFOEIE_Pos)
     
    #define SDIO_MASK_RXFIFOEIE   SDIO_MASK_RXFIFOEIE_Msk
     
    #define SDIO_MASK_TXDAVLIE_Pos   (20U)
     
    #define SDIO_MASK_TXDAVLIE_Msk   (0x1UL << SDIO_MASK_TXDAVLIE_Pos)
     
    #define SDIO_MASK_TXDAVLIE   SDIO_MASK_TXDAVLIE_Msk
     
    #define SDIO_MASK_RXDAVLIE_Pos   (21U)
     
    #define SDIO_MASK_RXDAVLIE_Msk   (0x1UL << SDIO_MASK_RXDAVLIE_Pos)
     
    #define SDIO_MASK_RXDAVLIE   SDIO_MASK_RXDAVLIE_Msk
     
    #define SDIO_MASK_SDIOITIE_Pos   (22U)
     
    #define SDIO_MASK_SDIOITIE_Msk   (0x1UL << SDIO_MASK_SDIOITIE_Pos)
     
    #define SDIO_MASK_SDIOITIE   SDIO_MASK_SDIOITIE_Msk
     
    #define SDIO_MASK_CEATAENDIE_Pos   (23U)
     
    #define SDIO_MASK_CEATAENDIE_Msk   (0x1UL << SDIO_MASK_CEATAENDIE_Pos)
     
    #define SDIO_MASK_CEATAENDIE   SDIO_MASK_CEATAENDIE_Msk
     
    #define SDIO_FIFOCNT_FIFOCOUNT_Pos   (0U)
     
    #define SDIO_FIFOCNT_FIFOCOUNT_Msk   (0xFFFFFFUL << SDIO_FIFOCNT_FIFOCOUNT_Pos)
     
    #define SDIO_FIFOCNT_FIFOCOUNT   SDIO_FIFOCNT_FIFOCOUNT_Msk
     
    #define SDIO_FIFO_FIFODATA_Pos   (0U)
     
    #define SDIO_FIFO_FIFODATA_Msk   (0xFFFFFFFFUL << SDIO_FIFO_FIFODATA_Pos)
     
    #define SDIO_FIFO_FIFODATA   SDIO_FIFO_FIFODATA_Msk
     
    #define SPI_I2S_FULLDUPLEX_SUPPORT
     
    #define SPI_CR1_CPHA_Pos   (0U)
     
    #define SPI_CR1_CPHA_Msk   (0x1UL << SPI_CR1_CPHA_Pos)
     
    #define SPI_CR1_CPHA   SPI_CR1_CPHA_Msk
     
    #define SPI_CR1_CPOL_Pos   (1U)
     
    #define SPI_CR1_CPOL_Msk   (0x1UL << SPI_CR1_CPOL_Pos)
     
    #define SPI_CR1_CPOL   SPI_CR1_CPOL_Msk
     
    #define SPI_CR1_MSTR_Pos   (2U)
     
    #define SPI_CR1_MSTR_Msk   (0x1UL << SPI_CR1_MSTR_Pos)
     
    #define SPI_CR1_MSTR   SPI_CR1_MSTR_Msk
     
    #define SPI_CR1_BR_Pos   (3U)
     
    #define SPI_CR1_BR_Msk   (0x7UL << SPI_CR1_BR_Pos)
     
    #define SPI_CR1_BR   SPI_CR1_BR_Msk
     
    #define SPI_CR1_BR_0   (0x1UL << SPI_CR1_BR_Pos)
     
    #define SPI_CR1_BR_1   (0x2UL << SPI_CR1_BR_Pos)
     
    #define SPI_CR1_BR_2   (0x4UL << SPI_CR1_BR_Pos)
     
    #define SPI_CR1_SPE_Pos   (6U)
     
    #define SPI_CR1_SPE_Msk   (0x1UL << SPI_CR1_SPE_Pos)
     
    #define SPI_CR1_SPE   SPI_CR1_SPE_Msk
     
    #define SPI_CR1_LSBFIRST_Pos   (7U)
     
    #define SPI_CR1_LSBFIRST_Msk   (0x1UL << SPI_CR1_LSBFIRST_Pos)
     
    #define SPI_CR1_LSBFIRST   SPI_CR1_LSBFIRST_Msk
     
    #define SPI_CR1_SSI_Pos   (8U)
     
    #define SPI_CR1_SSI_Msk   (0x1UL << SPI_CR1_SSI_Pos)
     
    #define SPI_CR1_SSI   SPI_CR1_SSI_Msk
     
    #define SPI_CR1_SSM_Pos   (9U)
     
    #define SPI_CR1_SSM_Msk   (0x1UL << SPI_CR1_SSM_Pos)
     
    #define SPI_CR1_SSM   SPI_CR1_SSM_Msk
     
    #define SPI_CR1_RXONLY_Pos   (10U)
     
    #define SPI_CR1_RXONLY_Msk   (0x1UL << SPI_CR1_RXONLY_Pos)
     
    #define SPI_CR1_RXONLY   SPI_CR1_RXONLY_Msk
     
    #define SPI_CR1_DFF_Pos   (11U)
     
    #define SPI_CR1_DFF_Msk   (0x1UL << SPI_CR1_DFF_Pos)
     
    #define SPI_CR1_DFF   SPI_CR1_DFF_Msk
     
    #define SPI_CR1_CRCNEXT_Pos   (12U)
     
    #define SPI_CR1_CRCNEXT_Msk   (0x1UL << SPI_CR1_CRCNEXT_Pos)
     
    #define SPI_CR1_CRCNEXT   SPI_CR1_CRCNEXT_Msk
     
    #define SPI_CR1_CRCEN_Pos   (13U)
     
    #define SPI_CR1_CRCEN_Msk   (0x1UL << SPI_CR1_CRCEN_Pos)
     
    #define SPI_CR1_CRCEN   SPI_CR1_CRCEN_Msk
     
    #define SPI_CR1_BIDIOE_Pos   (14U)
     
    #define SPI_CR1_BIDIOE_Msk   (0x1UL << SPI_CR1_BIDIOE_Pos)
     
    #define SPI_CR1_BIDIOE   SPI_CR1_BIDIOE_Msk
     
    #define SPI_CR1_BIDIMODE_Pos   (15U)
     
    #define SPI_CR1_BIDIMODE_Msk   (0x1UL << SPI_CR1_BIDIMODE_Pos)
     
    #define SPI_CR1_BIDIMODE   SPI_CR1_BIDIMODE_Msk
     
    #define SPI_CR2_RXDMAEN_Pos   (0U)
     
    #define SPI_CR2_RXDMAEN_Msk   (0x1UL << SPI_CR2_RXDMAEN_Pos)
     
    #define SPI_CR2_RXDMAEN   SPI_CR2_RXDMAEN_Msk
     
    #define SPI_CR2_TXDMAEN_Pos   (1U)
     
    #define SPI_CR2_TXDMAEN_Msk   (0x1UL << SPI_CR2_TXDMAEN_Pos)
     
    #define SPI_CR2_TXDMAEN   SPI_CR2_TXDMAEN_Msk
     
    #define SPI_CR2_SSOE_Pos   (2U)
     
    #define SPI_CR2_SSOE_Msk   (0x1UL << SPI_CR2_SSOE_Pos)
     
    #define SPI_CR2_SSOE   SPI_CR2_SSOE_Msk
     
    #define SPI_CR2_FRF_Pos   (4U)
     
    #define SPI_CR2_FRF_Msk   (0x1UL << SPI_CR2_FRF_Pos)
     
    #define SPI_CR2_FRF   SPI_CR2_FRF_Msk
     
    #define SPI_CR2_ERRIE_Pos   (5U)
     
    #define SPI_CR2_ERRIE_Msk   (0x1UL << SPI_CR2_ERRIE_Pos)
     
    #define SPI_CR2_ERRIE   SPI_CR2_ERRIE_Msk
     
    #define SPI_CR2_RXNEIE_Pos   (6U)
     
    #define SPI_CR2_RXNEIE_Msk   (0x1UL << SPI_CR2_RXNEIE_Pos)
     
    #define SPI_CR2_RXNEIE   SPI_CR2_RXNEIE_Msk
     
    #define SPI_CR2_TXEIE_Pos   (7U)
     
    #define SPI_CR2_TXEIE_Msk   (0x1UL << SPI_CR2_TXEIE_Pos)
     
    #define SPI_CR2_TXEIE   SPI_CR2_TXEIE_Msk
     
    #define SPI_SR_RXNE_Pos   (0U)
     
    #define SPI_SR_RXNE_Msk   (0x1UL << SPI_SR_RXNE_Pos)
     
    #define SPI_SR_RXNE   SPI_SR_RXNE_Msk
     
    #define SPI_SR_TXE_Pos   (1U)
     
    #define SPI_SR_TXE_Msk   (0x1UL << SPI_SR_TXE_Pos)
     
    #define SPI_SR_TXE   SPI_SR_TXE_Msk
     
    #define SPI_SR_CHSIDE_Pos   (2U)
     
    #define SPI_SR_CHSIDE_Msk   (0x1UL << SPI_SR_CHSIDE_Pos)
     
    #define SPI_SR_CHSIDE   SPI_SR_CHSIDE_Msk
     
    #define SPI_SR_UDR_Pos   (3U)
     
    #define SPI_SR_UDR_Msk   (0x1UL << SPI_SR_UDR_Pos)
     
    #define SPI_SR_UDR   SPI_SR_UDR_Msk
     
    #define SPI_SR_CRCERR_Pos   (4U)
     
    #define SPI_SR_CRCERR_Msk   (0x1UL << SPI_SR_CRCERR_Pos)
     
    #define SPI_SR_CRCERR   SPI_SR_CRCERR_Msk
     
    #define SPI_SR_MODF_Pos   (5U)
     
    #define SPI_SR_MODF_Msk   (0x1UL << SPI_SR_MODF_Pos)
     
    #define SPI_SR_MODF   SPI_SR_MODF_Msk
     
    #define SPI_SR_OVR_Pos   (6U)
     
    #define SPI_SR_OVR_Msk   (0x1UL << SPI_SR_OVR_Pos)
     
    #define SPI_SR_OVR   SPI_SR_OVR_Msk
     
    #define SPI_SR_BSY_Pos   (7U)
     
    #define SPI_SR_BSY_Msk   (0x1UL << SPI_SR_BSY_Pos)
     
    #define SPI_SR_BSY   SPI_SR_BSY_Msk
     
    #define SPI_SR_FRE_Pos   (8U)
     
    #define SPI_SR_FRE_Msk   (0x1UL << SPI_SR_FRE_Pos)
     
    #define SPI_SR_FRE   SPI_SR_FRE_Msk
     
    #define SPI_DR_DR_Pos   (0U)
     
    #define SPI_DR_DR_Msk   (0xFFFFUL << SPI_DR_DR_Pos)
     
    #define SPI_DR_DR   SPI_DR_DR_Msk
     
    #define SPI_CRCPR_CRCPOLY_Pos   (0U)
     
    #define SPI_CRCPR_CRCPOLY_Msk   (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos)
     
    #define SPI_CRCPR_CRCPOLY   SPI_CRCPR_CRCPOLY_Msk
     
    #define SPI_RXCRCR_RXCRC_Pos   (0U)
     
    #define SPI_RXCRCR_RXCRC_Msk   (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos)
     
    #define SPI_RXCRCR_RXCRC   SPI_RXCRCR_RXCRC_Msk
     
    #define SPI_TXCRCR_TXCRC_Pos   (0U)
     
    #define SPI_TXCRCR_TXCRC_Msk   (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos)
     
    #define SPI_TXCRCR_TXCRC   SPI_TXCRCR_TXCRC_Msk
     
    #define SPI_I2SCFGR_CHLEN_Pos   (0U)
     
    #define SPI_I2SCFGR_CHLEN_Msk   (0x1UL << SPI_I2SCFGR_CHLEN_Pos)
     
    #define SPI_I2SCFGR_CHLEN   SPI_I2SCFGR_CHLEN_Msk
     
    #define SPI_I2SCFGR_DATLEN_Pos   (1U)
     
    #define SPI_I2SCFGR_DATLEN_Msk   (0x3UL << SPI_I2SCFGR_DATLEN_Pos)
     
    #define SPI_I2SCFGR_DATLEN   SPI_I2SCFGR_DATLEN_Msk
     
    #define SPI_I2SCFGR_DATLEN_0   (0x1UL << SPI_I2SCFGR_DATLEN_Pos)
     
    #define SPI_I2SCFGR_DATLEN_1   (0x2UL << SPI_I2SCFGR_DATLEN_Pos)
     
    #define SPI_I2SCFGR_CKPOL_Pos   (3U)
     
    #define SPI_I2SCFGR_CKPOL_Msk   (0x1UL << SPI_I2SCFGR_CKPOL_Pos)
     
    #define SPI_I2SCFGR_CKPOL   SPI_I2SCFGR_CKPOL_Msk
     
    #define SPI_I2SCFGR_I2SSTD_Pos   (4U)
     
    #define SPI_I2SCFGR_I2SSTD_Msk   (0x3UL << SPI_I2SCFGR_I2SSTD_Pos)
     
    #define SPI_I2SCFGR_I2SSTD   SPI_I2SCFGR_I2SSTD_Msk
     
    #define SPI_I2SCFGR_I2SSTD_0   (0x1UL << SPI_I2SCFGR_I2SSTD_Pos)
     
    #define SPI_I2SCFGR_I2SSTD_1   (0x2UL << SPI_I2SCFGR_I2SSTD_Pos)
     
    #define SPI_I2SCFGR_PCMSYNC_Pos   (7U)
     
    #define SPI_I2SCFGR_PCMSYNC_Msk   (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos)
     
    #define SPI_I2SCFGR_PCMSYNC   SPI_I2SCFGR_PCMSYNC_Msk
     
    #define SPI_I2SCFGR_I2SCFG_Pos   (8U)
     
    #define SPI_I2SCFGR_I2SCFG_Msk   (0x3UL << SPI_I2SCFGR_I2SCFG_Pos)
     
    #define SPI_I2SCFGR_I2SCFG   SPI_I2SCFGR_I2SCFG_Msk
     
    #define SPI_I2SCFGR_I2SCFG_0   (0x1UL << SPI_I2SCFGR_I2SCFG_Pos)
     
    #define SPI_I2SCFGR_I2SCFG_1   (0x2UL << SPI_I2SCFGR_I2SCFG_Pos)
     
    #define SPI_I2SCFGR_I2SE_Pos   (10U)
     
    #define SPI_I2SCFGR_I2SE_Msk   (0x1UL << SPI_I2SCFGR_I2SE_Pos)
     
    #define SPI_I2SCFGR_I2SE   SPI_I2SCFGR_I2SE_Msk
     
    #define SPI_I2SCFGR_I2SMOD_Pos   (11U)
     
    #define SPI_I2SCFGR_I2SMOD_Msk   (0x1UL << SPI_I2SCFGR_I2SMOD_Pos)
     
    #define SPI_I2SCFGR_I2SMOD   SPI_I2SCFGR_I2SMOD_Msk
     
    #define SPI_I2SPR_I2SDIV_Pos   (0U)
     
    #define SPI_I2SPR_I2SDIV_Msk   (0xFFUL << SPI_I2SPR_I2SDIV_Pos)
     
    #define SPI_I2SPR_I2SDIV   SPI_I2SPR_I2SDIV_Msk
     
    #define SPI_I2SPR_ODD_Pos   (8U)
     
    #define SPI_I2SPR_ODD_Msk   (0x1UL << SPI_I2SPR_ODD_Pos)
     
    #define SPI_I2SPR_ODD   SPI_I2SPR_ODD_Msk
     
    #define SPI_I2SPR_MCKOE_Pos   (9U)
     
    #define SPI_I2SPR_MCKOE_Msk   (0x1UL << SPI_I2SPR_MCKOE_Pos)
     
    #define SPI_I2SPR_MCKOE   SPI_I2SPR_MCKOE_Msk
     
    #define SYSCFG_MEMRMP_MEM_MODE_Pos   (0U)
     
    #define SYSCFG_MEMRMP_MEM_MODE_Msk   (0x3UL << SYSCFG_MEMRMP_MEM_MODE_Pos)
     
    #define SYSCFG_MEMRMP_MEM_MODE   SYSCFG_MEMRMP_MEM_MODE_Msk
     
    #define SYSCFG_MEMRMP_MEM_MODE_0   (0x1UL << SYSCFG_MEMRMP_MEM_MODE_Pos)
     
    #define SYSCFG_MEMRMP_MEM_MODE_1   (0x2UL << SYSCFG_MEMRMP_MEM_MODE_Pos)
     
    #define SYSCFG_PMC_MII_RMII_SEL_Pos   (23U)
     
    #define SYSCFG_PMC_MII_RMII_SEL_Msk   (0x1UL << SYSCFG_PMC_MII_RMII_SEL_Pos)
     
    #define SYSCFG_PMC_MII_RMII_SEL   SYSCFG_PMC_MII_RMII_SEL_Msk
     
    #define SYSCFG_PMC_MII_RMII   SYSCFG_PMC_MII_RMII_SEL
     
    #define SYSCFG_EXTICR1_EXTI0_Pos   (0U)
     
    #define SYSCFG_EXTICR1_EXTI0_Msk   (0xFUL << SYSCFG_EXTICR1_EXTI0_Pos)
     
    #define SYSCFG_EXTICR1_EXTI0   SYSCFG_EXTICR1_EXTI0_Msk
     
    #define SYSCFG_EXTICR1_EXTI1_Pos   (4U)
     
    #define SYSCFG_EXTICR1_EXTI1_Msk   (0xFUL << SYSCFG_EXTICR1_EXTI1_Pos)
     
    #define SYSCFG_EXTICR1_EXTI1   SYSCFG_EXTICR1_EXTI1_Msk
     
    #define SYSCFG_EXTICR1_EXTI2_Pos   (8U)
     
    #define SYSCFG_EXTICR1_EXTI2_Msk   (0xFUL << SYSCFG_EXTICR1_EXTI2_Pos)
     
    #define SYSCFG_EXTICR1_EXTI2   SYSCFG_EXTICR1_EXTI2_Msk
     
    #define SYSCFG_EXTICR1_EXTI3_Pos   (12U)
     
    #define SYSCFG_EXTICR1_EXTI3_Msk   (0xFUL << SYSCFG_EXTICR1_EXTI3_Pos)
     
    #define SYSCFG_EXTICR1_EXTI3   SYSCFG_EXTICR1_EXTI3_Msk
     
    #define SYSCFG_EXTICR1_EXTI0_PA   0x0000U
     EXTI0 configuration
    -
     
    #define SYSCFG_EXTICR1_EXTI0_PB   0x0001U
     
    #define SYSCFG_EXTICR1_EXTI0_PC   0x0002U
     
    #define SYSCFG_EXTICR1_EXTI0_PD   0x0003U
     
    #define SYSCFG_EXTICR1_EXTI0_PE   0x0004U
     
    #define SYSCFG_EXTICR1_EXTI0_PF   0x0005U
     
    #define SYSCFG_EXTICR1_EXTI0_PG   0x0006U
     
    #define SYSCFG_EXTICR1_EXTI0_PH   0x0007U
     
    #define SYSCFG_EXTICR1_EXTI0_PI   0x0008U
     
    #define SYSCFG_EXTICR1_EXTI1_PA   0x0000U
     EXTI1 configuration
    -
     
    #define SYSCFG_EXTICR1_EXTI1_PB   0x0010U
     
    #define SYSCFG_EXTICR1_EXTI1_PC   0x0020U
     
    #define SYSCFG_EXTICR1_EXTI1_PD   0x0030U
     
    #define SYSCFG_EXTICR1_EXTI1_PE   0x0040U
     
    #define SYSCFG_EXTICR1_EXTI1_PF   0x0050U
     
    #define SYSCFG_EXTICR1_EXTI1_PG   0x0060U
     
    #define SYSCFG_EXTICR1_EXTI1_PH   0x0070U
     
    #define SYSCFG_EXTICR1_EXTI1_PI   0x0080U
     
    #define SYSCFG_EXTICR1_EXTI2_PA   0x0000U
     EXTI2 configuration
    -
     
    #define SYSCFG_EXTICR1_EXTI2_PB   0x0100U
     
    #define SYSCFG_EXTICR1_EXTI2_PC   0x0200U
     
    #define SYSCFG_EXTICR1_EXTI2_PD   0x0300U
     
    #define SYSCFG_EXTICR1_EXTI2_PE   0x0400U
     
    #define SYSCFG_EXTICR1_EXTI2_PF   0x0500U
     
    #define SYSCFG_EXTICR1_EXTI2_PG   0x0600U
     
    #define SYSCFG_EXTICR1_EXTI2_PH   0x0700U
     
    #define SYSCFG_EXTICR1_EXTI2_PI   0x0800U
     
    #define SYSCFG_EXTICR1_EXTI3_PA   0x0000U
     EXTI3 configuration
    -
     
    #define SYSCFG_EXTICR1_EXTI3_PB   0x1000U
     
    #define SYSCFG_EXTICR1_EXTI3_PC   0x2000U
     
    #define SYSCFG_EXTICR1_EXTI3_PD   0x3000U
     
    #define SYSCFG_EXTICR1_EXTI3_PE   0x4000U
     
    #define SYSCFG_EXTICR1_EXTI3_PF   0x5000U
     
    #define SYSCFG_EXTICR1_EXTI3_PG   0x6000U
     
    #define SYSCFG_EXTICR1_EXTI3_PH   0x7000U
     
    #define SYSCFG_EXTICR1_EXTI3_PI   0x8000U
     
    #define SYSCFG_EXTICR2_EXTI4_Pos   (0U)
     
    #define SYSCFG_EXTICR2_EXTI4_Msk   (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos)
     
    #define SYSCFG_EXTICR2_EXTI4   SYSCFG_EXTICR2_EXTI4_Msk
     
    #define SYSCFG_EXTICR2_EXTI5_Pos   (4U)
     
    #define SYSCFG_EXTICR2_EXTI5_Msk   (0xFUL << SYSCFG_EXTICR2_EXTI5_Pos)
     
    #define SYSCFG_EXTICR2_EXTI5   SYSCFG_EXTICR2_EXTI5_Msk
     
    #define SYSCFG_EXTICR2_EXTI6_Pos   (8U)
     
    #define SYSCFG_EXTICR2_EXTI6_Msk   (0xFUL << SYSCFG_EXTICR2_EXTI6_Pos)
     
    #define SYSCFG_EXTICR2_EXTI6   SYSCFG_EXTICR2_EXTI6_Msk
     
    #define SYSCFG_EXTICR2_EXTI7_Pos   (12U)
     
    #define SYSCFG_EXTICR2_EXTI7_Msk   (0xFUL << SYSCFG_EXTICR2_EXTI7_Pos)
     
    #define SYSCFG_EXTICR2_EXTI7   SYSCFG_EXTICR2_EXTI7_Msk
     
    #define SYSCFG_EXTICR2_EXTI4_PA   0x0000U
     EXTI4 configuration
    -
     
    #define SYSCFG_EXTICR2_EXTI4_PB   0x0001U
     
    #define SYSCFG_EXTICR2_EXTI4_PC   0x0002U
     
    #define SYSCFG_EXTICR2_EXTI4_PD   0x0003U
     
    #define SYSCFG_EXTICR2_EXTI4_PE   0x0004U
     
    #define SYSCFG_EXTICR2_EXTI4_PF   0x0005U
     
    #define SYSCFG_EXTICR2_EXTI4_PG   0x0006U
     
    #define SYSCFG_EXTICR2_EXTI4_PH   0x0007U
     
    #define SYSCFG_EXTICR2_EXTI4_PI   0x0008U
     
    #define SYSCFG_EXTICR2_EXTI5_PA   0x0000U
     EXTI5 configuration
    -
     
    #define SYSCFG_EXTICR2_EXTI5_PB   0x0010U
     
    #define SYSCFG_EXTICR2_EXTI5_PC   0x0020U
     
    #define SYSCFG_EXTICR2_EXTI5_PD   0x0030U
     
    #define SYSCFG_EXTICR2_EXTI5_PE   0x0040U
     
    #define SYSCFG_EXTICR2_EXTI5_PF   0x0050U
     
    #define SYSCFG_EXTICR2_EXTI5_PG   0x0060U
     
    #define SYSCFG_EXTICR2_EXTI5_PH   0x0070U
     
    #define SYSCFG_EXTICR2_EXTI5_PI   0x0080U
     
    #define SYSCFG_EXTICR2_EXTI6_PA   0x0000U
     EXTI6 configuration
    -
     
    #define SYSCFG_EXTICR2_EXTI6_PB   0x0100U
     
    #define SYSCFG_EXTICR2_EXTI6_PC   0x0200U
     
    #define SYSCFG_EXTICR2_EXTI6_PD   0x0300U
     
    #define SYSCFG_EXTICR2_EXTI6_PE   0x0400U
     
    #define SYSCFG_EXTICR2_EXTI6_PF   0x0500U
     
    #define SYSCFG_EXTICR2_EXTI6_PG   0x0600U
     
    #define SYSCFG_EXTICR2_EXTI6_PH   0x0700U
     
    #define SYSCFG_EXTICR2_EXTI6_PI   0x0800U
     
    #define SYSCFG_EXTICR2_EXTI7_PA   0x0000U
     EXTI7 configuration
    -
     
    #define SYSCFG_EXTICR2_EXTI7_PB   0x1000U
     
    #define SYSCFG_EXTICR2_EXTI7_PC   0x2000U
     
    #define SYSCFG_EXTICR2_EXTI7_PD   0x3000U
     
    #define SYSCFG_EXTICR2_EXTI7_PE   0x4000U
     
    #define SYSCFG_EXTICR2_EXTI7_PF   0x5000U
     
    #define SYSCFG_EXTICR2_EXTI7_PG   0x6000U
     
    #define SYSCFG_EXTICR2_EXTI7_PH   0x7000U
     
    #define SYSCFG_EXTICR2_EXTI7_PI   0x8000U
     
    #define SYSCFG_EXTICR3_EXTI8_Pos   (0U)
     
    #define SYSCFG_EXTICR3_EXTI8_Msk   (0xFUL << SYSCFG_EXTICR3_EXTI8_Pos)
     
    #define SYSCFG_EXTICR3_EXTI8   SYSCFG_EXTICR3_EXTI8_Msk
     
    #define SYSCFG_EXTICR3_EXTI9_Pos   (4U)
     
    #define SYSCFG_EXTICR3_EXTI9_Msk   (0xFUL << SYSCFG_EXTICR3_EXTI9_Pos)
     
    #define SYSCFG_EXTICR3_EXTI9   SYSCFG_EXTICR3_EXTI9_Msk
     
    #define SYSCFG_EXTICR3_EXTI10_Pos   (8U)
     
    #define SYSCFG_EXTICR3_EXTI10_Msk   (0xFUL << SYSCFG_EXTICR3_EXTI10_Pos)
     
    #define SYSCFG_EXTICR3_EXTI10   SYSCFG_EXTICR3_EXTI10_Msk
     
    #define SYSCFG_EXTICR3_EXTI11_Pos   (12U)
     
    #define SYSCFG_EXTICR3_EXTI11_Msk   (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos)
     
    #define SYSCFG_EXTICR3_EXTI11   SYSCFG_EXTICR3_EXTI11_Msk
     
    #define SYSCFG_EXTICR3_EXTI8_PA   0x0000U
     EXTI8 configuration
    -
     
    #define SYSCFG_EXTICR3_EXTI8_PB   0x0001U
     
    #define SYSCFG_EXTICR3_EXTI8_PC   0x0002U
     
    #define SYSCFG_EXTICR3_EXTI8_PD   0x0003U
     
    #define SYSCFG_EXTICR3_EXTI8_PE   0x0004U
     
    #define SYSCFG_EXTICR3_EXTI8_PF   0x0005U
     
    #define SYSCFG_EXTICR3_EXTI8_PG   0x0006U
     
    #define SYSCFG_EXTICR3_EXTI8_PH   0x0007U
     
    #define SYSCFG_EXTICR3_EXTI8_PI   0x0008U
     
    #define SYSCFG_EXTICR3_EXTI9_PA   0x0000U
     EXTI9 configuration
    -
     
    #define SYSCFG_EXTICR3_EXTI9_PB   0x0010U
     
    #define SYSCFG_EXTICR3_EXTI9_PC   0x0020U
     
    #define SYSCFG_EXTICR3_EXTI9_PD   0x0030U
     
    #define SYSCFG_EXTICR3_EXTI9_PE   0x0040U
     
    #define SYSCFG_EXTICR3_EXTI9_PF   0x0050U
     
    #define SYSCFG_EXTICR3_EXTI9_PG   0x0060U
     
    #define SYSCFG_EXTICR3_EXTI9_PH   0x0070U
     
    #define SYSCFG_EXTICR3_EXTI9_PI   0x0080U
     
    #define SYSCFG_EXTICR3_EXTI10_PA   0x0000U
     EXTI10 configuration
    -
     
    #define SYSCFG_EXTICR3_EXTI10_PB   0x0100U
     
    #define SYSCFG_EXTICR3_EXTI10_PC   0x0200U
     
    #define SYSCFG_EXTICR3_EXTI10_PD   0x0300U
     
    #define SYSCFG_EXTICR3_EXTI10_PE   0x0400U
     
    #define SYSCFG_EXTICR3_EXTI10_PF   0x0500U
     
    #define SYSCFG_EXTICR3_EXTI10_PG   0x0600U
     
    #define SYSCFG_EXTICR3_EXTI10_PH   0x0700U
     
    #define SYSCFG_EXTICR3_EXTI10_PI   0x0800U
     
    #define SYSCFG_EXTICR3_EXTI11_PA   0x0000U
     EXTI11 configuration
    -
     
    #define SYSCFG_EXTICR3_EXTI11_PB   0x1000U
     
    #define SYSCFG_EXTICR3_EXTI11_PC   0x2000U
     
    #define SYSCFG_EXTICR3_EXTI11_PD   0x3000U
     
    #define SYSCFG_EXTICR3_EXTI11_PE   0x4000U
     
    #define SYSCFG_EXTICR3_EXTI11_PF   0x5000U
     
    #define SYSCFG_EXTICR3_EXTI11_PG   0x6000U
     
    #define SYSCFG_EXTICR3_EXTI11_PH   0x7000U
     
    #define SYSCFG_EXTICR3_EXTI11_PI   0x8000U
     
    #define SYSCFG_EXTICR4_EXTI12_Pos   (0U)
     
    #define SYSCFG_EXTICR4_EXTI12_Msk   (0xFUL << SYSCFG_EXTICR4_EXTI12_Pos)
     
    #define SYSCFG_EXTICR4_EXTI12   SYSCFG_EXTICR4_EXTI12_Msk
     
    #define SYSCFG_EXTICR4_EXTI13_Pos   (4U)
     
    #define SYSCFG_EXTICR4_EXTI13_Msk   (0xFUL << SYSCFG_EXTICR4_EXTI13_Pos)
     
    #define SYSCFG_EXTICR4_EXTI13   SYSCFG_EXTICR4_EXTI13_Msk
     
    #define SYSCFG_EXTICR4_EXTI14_Pos   (8U)
     
    #define SYSCFG_EXTICR4_EXTI14_Msk   (0xFUL << SYSCFG_EXTICR4_EXTI14_Pos)
     
    #define SYSCFG_EXTICR4_EXTI14   SYSCFG_EXTICR4_EXTI14_Msk
     
    #define SYSCFG_EXTICR4_EXTI15_Pos   (12U)
     
    #define SYSCFG_EXTICR4_EXTI15_Msk   (0xFUL << SYSCFG_EXTICR4_EXTI15_Pos)
     
    #define SYSCFG_EXTICR4_EXTI15   SYSCFG_EXTICR4_EXTI15_Msk
     
    #define SYSCFG_EXTICR4_EXTI12_PA   0x0000U
     EXTI12 configuration
    -
     
    #define SYSCFG_EXTICR4_EXTI12_PB   0x0001U
     
    #define SYSCFG_EXTICR4_EXTI12_PC   0x0002U
     
    #define SYSCFG_EXTICR4_EXTI12_PD   0x0003U
     
    #define SYSCFG_EXTICR4_EXTI12_PE   0x0004U
     
    #define SYSCFG_EXTICR4_EXTI12_PF   0x0005U
     
    #define SYSCFG_EXTICR4_EXTI12_PG   0x0006U
     
    #define SYSCFG_EXTICR4_EXTI12_PH   0x0007U
     
    #define SYSCFG_EXTICR4_EXTI13_PA   0x0000U
     EXTI13 configuration
    -
     
    #define SYSCFG_EXTICR4_EXTI13_PB   0x0010U
     
    #define SYSCFG_EXTICR4_EXTI13_PC   0x0020U
     
    #define SYSCFG_EXTICR4_EXTI13_PD   0x0030U
     
    #define SYSCFG_EXTICR4_EXTI13_PE   0x0040U
     
    #define SYSCFG_EXTICR4_EXTI13_PF   0x0050U
     
    #define SYSCFG_EXTICR4_EXTI13_PG   0x0060U
     
    #define SYSCFG_EXTICR4_EXTI13_PH   0x0070U
     
    #define SYSCFG_EXTICR4_EXTI14_PA   0x0000U
     EXTI14 configuration
    -
     
    #define SYSCFG_EXTICR4_EXTI14_PB   0x0100U
     
    #define SYSCFG_EXTICR4_EXTI14_PC   0x0200U
     
    #define SYSCFG_EXTICR4_EXTI14_PD   0x0300U
     
    #define SYSCFG_EXTICR4_EXTI14_PE   0x0400U
     
    #define SYSCFG_EXTICR4_EXTI14_PF   0x0500U
     
    #define SYSCFG_EXTICR4_EXTI14_PG   0x0600U
     
    #define SYSCFG_EXTICR4_EXTI14_PH   0x0700U
     
    #define SYSCFG_EXTICR4_EXTI15_PA   0x0000U
     EXTI15 configuration
    -
     
    #define SYSCFG_EXTICR4_EXTI15_PB   0x1000U
     
    #define SYSCFG_EXTICR4_EXTI15_PC   0x2000U
     
    #define SYSCFG_EXTICR4_EXTI15_PD   0x3000U
     
    #define SYSCFG_EXTICR4_EXTI15_PE   0x4000U
     
    #define SYSCFG_EXTICR4_EXTI15_PF   0x5000U
     
    #define SYSCFG_EXTICR4_EXTI15_PG   0x6000U
     
    #define SYSCFG_EXTICR4_EXTI15_PH   0x7000U
     
    #define SYSCFG_CMPCR_CMP_PD_Pos   (0U)
     
    #define SYSCFG_CMPCR_CMP_PD_Msk   (0x1UL << SYSCFG_CMPCR_CMP_PD_Pos)
     
    #define SYSCFG_CMPCR_CMP_PD   SYSCFG_CMPCR_CMP_PD_Msk
     
    #define SYSCFG_CMPCR_READY_Pos   (8U)
     
    #define SYSCFG_CMPCR_READY_Msk   (0x1UL << SYSCFG_CMPCR_READY_Pos)
     
    #define SYSCFG_CMPCR_READY   SYSCFG_CMPCR_READY_Msk
     
    #define TIM_CR1_CEN_Pos   (0U)
     
    #define TIM_CR1_CEN_Msk   (0x1UL << TIM_CR1_CEN_Pos)
     
    #define TIM_CR1_CEN   TIM_CR1_CEN_Msk
     
    #define TIM_CR1_UDIS_Pos   (1U)
     
    #define TIM_CR1_UDIS_Msk   (0x1UL << TIM_CR1_UDIS_Pos)
     
    #define TIM_CR1_UDIS   TIM_CR1_UDIS_Msk
     
    #define TIM_CR1_URS_Pos   (2U)
     
    #define TIM_CR1_URS_Msk   (0x1UL << TIM_CR1_URS_Pos)
     
    #define TIM_CR1_URS   TIM_CR1_URS_Msk
     
    #define TIM_CR1_OPM_Pos   (3U)
     
    #define TIM_CR1_OPM_Msk   (0x1UL << TIM_CR1_OPM_Pos)
     
    #define TIM_CR1_OPM   TIM_CR1_OPM_Msk
     
    #define TIM_CR1_DIR_Pos   (4U)
     
    #define TIM_CR1_DIR_Msk   (0x1UL << TIM_CR1_DIR_Pos)
     
    #define TIM_CR1_DIR   TIM_CR1_DIR_Msk
     
    #define TIM_CR1_CMS_Pos   (5U)
     
    #define TIM_CR1_CMS_Msk   (0x3UL << TIM_CR1_CMS_Pos)
     
    #define TIM_CR1_CMS   TIM_CR1_CMS_Msk
     
    #define TIM_CR1_CMS_0   (0x1UL << TIM_CR1_CMS_Pos)
     
    #define TIM_CR1_CMS_1   (0x2UL << TIM_CR1_CMS_Pos)
     
    #define TIM_CR1_ARPE_Pos   (7U)
     
    #define TIM_CR1_ARPE_Msk   (0x1UL << TIM_CR1_ARPE_Pos)
     
    #define TIM_CR1_ARPE   TIM_CR1_ARPE_Msk
     
    #define TIM_CR1_CKD_Pos   (8U)
     
    #define TIM_CR1_CKD_Msk   (0x3UL << TIM_CR1_CKD_Pos)
     
    #define TIM_CR1_CKD   TIM_CR1_CKD_Msk
     
    #define TIM_CR1_CKD_0   (0x1UL << TIM_CR1_CKD_Pos)
     
    #define TIM_CR1_CKD_1   (0x2UL << TIM_CR1_CKD_Pos)
     
    #define TIM_CR2_CCPC_Pos   (0U)
     
    #define TIM_CR2_CCPC_Msk   (0x1UL << TIM_CR2_CCPC_Pos)
     
    #define TIM_CR2_CCPC   TIM_CR2_CCPC_Msk
     
    #define TIM_CR2_CCUS_Pos   (2U)
     
    #define TIM_CR2_CCUS_Msk   (0x1UL << TIM_CR2_CCUS_Pos)
     
    #define TIM_CR2_CCUS   TIM_CR2_CCUS_Msk
     
    #define TIM_CR2_CCDS_Pos   (3U)
     
    #define TIM_CR2_CCDS_Msk   (0x1UL << TIM_CR2_CCDS_Pos)
     
    #define TIM_CR2_CCDS   TIM_CR2_CCDS_Msk
     
    #define TIM_CR2_MMS_Pos   (4U)
     
    #define TIM_CR2_MMS_Msk   (0x7UL << TIM_CR2_MMS_Pos)
     
    #define TIM_CR2_MMS   TIM_CR2_MMS_Msk
     
    #define TIM_CR2_MMS_0   (0x1UL << TIM_CR2_MMS_Pos)
     
    #define TIM_CR2_MMS_1   (0x2UL << TIM_CR2_MMS_Pos)
     
    #define TIM_CR2_MMS_2   (0x4UL << TIM_CR2_MMS_Pos)
     
    #define TIM_CR2_TI1S_Pos   (7U)
     
    #define TIM_CR2_TI1S_Msk   (0x1UL << TIM_CR2_TI1S_Pos)
     
    #define TIM_CR2_TI1S   TIM_CR2_TI1S_Msk
     
    #define TIM_CR2_OIS1_Pos   (8U)
     
    #define TIM_CR2_OIS1_Msk   (0x1UL << TIM_CR2_OIS1_Pos)
     
    #define TIM_CR2_OIS1   TIM_CR2_OIS1_Msk
     
    #define TIM_CR2_OIS1N_Pos   (9U)
     
    #define TIM_CR2_OIS1N_Msk   (0x1UL << TIM_CR2_OIS1N_Pos)
     
    #define TIM_CR2_OIS1N   TIM_CR2_OIS1N_Msk
     
    #define TIM_CR2_OIS2_Pos   (10U)
     
    #define TIM_CR2_OIS2_Msk   (0x1UL << TIM_CR2_OIS2_Pos)
     
    #define TIM_CR2_OIS2   TIM_CR2_OIS2_Msk
     
    #define TIM_CR2_OIS2N_Pos   (11U)
     
    #define TIM_CR2_OIS2N_Msk   (0x1UL << TIM_CR2_OIS2N_Pos)
     
    #define TIM_CR2_OIS2N   TIM_CR2_OIS2N_Msk
     
    #define TIM_CR2_OIS3_Pos   (12U)
     
    #define TIM_CR2_OIS3_Msk   (0x1UL << TIM_CR2_OIS3_Pos)
     
    #define TIM_CR2_OIS3   TIM_CR2_OIS3_Msk
     
    #define TIM_CR2_OIS3N_Pos   (13U)
     
    #define TIM_CR2_OIS3N_Msk   (0x1UL << TIM_CR2_OIS3N_Pos)
     
    #define TIM_CR2_OIS3N   TIM_CR2_OIS3N_Msk
     
    #define TIM_CR2_OIS4_Pos   (14U)
     
    #define TIM_CR2_OIS4_Msk   (0x1UL << TIM_CR2_OIS4_Pos)
     
    #define TIM_CR2_OIS4   TIM_CR2_OIS4_Msk
     
    #define TIM_SMCR_SMS_Pos   (0U)
     
    #define TIM_SMCR_SMS_Msk   (0x7UL << TIM_SMCR_SMS_Pos)
     
    #define TIM_SMCR_SMS   TIM_SMCR_SMS_Msk
     
    #define TIM_SMCR_SMS_0   (0x1UL << TIM_SMCR_SMS_Pos)
     
    #define TIM_SMCR_SMS_1   (0x2UL << TIM_SMCR_SMS_Pos)
     
    #define TIM_SMCR_SMS_2   (0x4UL << TIM_SMCR_SMS_Pos)
     
    #define TIM_SMCR_TS_Pos   (4U)
     
    #define TIM_SMCR_TS_Msk   (0x7UL << TIM_SMCR_TS_Pos)
     
    #define TIM_SMCR_TS   TIM_SMCR_TS_Msk
     
    #define TIM_SMCR_TS_0   (0x1UL << TIM_SMCR_TS_Pos)
     
    #define TIM_SMCR_TS_1   (0x2UL << TIM_SMCR_TS_Pos)
     
    #define TIM_SMCR_TS_2   (0x4UL << TIM_SMCR_TS_Pos)
     
    #define TIM_SMCR_MSM_Pos   (7U)
     
    #define TIM_SMCR_MSM_Msk   (0x1UL << TIM_SMCR_MSM_Pos)
     
    #define TIM_SMCR_MSM   TIM_SMCR_MSM_Msk
     
    #define TIM_SMCR_ETF_Pos   (8U)
     
    #define TIM_SMCR_ETF_Msk   (0xFUL << TIM_SMCR_ETF_Pos)
     
    #define TIM_SMCR_ETF   TIM_SMCR_ETF_Msk
     
    #define TIM_SMCR_ETF_0   (0x1UL << TIM_SMCR_ETF_Pos)
     
    #define TIM_SMCR_ETF_1   (0x2UL << TIM_SMCR_ETF_Pos)
     
    #define TIM_SMCR_ETF_2   (0x4UL << TIM_SMCR_ETF_Pos)
     
    #define TIM_SMCR_ETF_3   (0x8UL << TIM_SMCR_ETF_Pos)
     
    #define TIM_SMCR_ETPS_Pos   (12U)
     
    #define TIM_SMCR_ETPS_Msk   (0x3UL << TIM_SMCR_ETPS_Pos)
     
    #define TIM_SMCR_ETPS   TIM_SMCR_ETPS_Msk
     
    #define TIM_SMCR_ETPS_0   (0x1UL << TIM_SMCR_ETPS_Pos)
     
    #define TIM_SMCR_ETPS_1   (0x2UL << TIM_SMCR_ETPS_Pos)
     
    #define TIM_SMCR_ECE_Pos   (14U)
     
    #define TIM_SMCR_ECE_Msk   (0x1UL << TIM_SMCR_ECE_Pos)
     
    #define TIM_SMCR_ECE   TIM_SMCR_ECE_Msk
     
    #define TIM_SMCR_ETP_Pos   (15U)
     
    #define TIM_SMCR_ETP_Msk   (0x1UL << TIM_SMCR_ETP_Pos)
     
    #define TIM_SMCR_ETP   TIM_SMCR_ETP_Msk
     
    #define TIM_DIER_UIE_Pos   (0U)
     
    #define TIM_DIER_UIE_Msk   (0x1UL << TIM_DIER_UIE_Pos)
     
    #define TIM_DIER_UIE   TIM_DIER_UIE_Msk
     
    #define TIM_DIER_CC1IE_Pos   (1U)
     
    #define TIM_DIER_CC1IE_Msk   (0x1UL << TIM_DIER_CC1IE_Pos)
     
    #define TIM_DIER_CC1IE   TIM_DIER_CC1IE_Msk
     
    #define TIM_DIER_CC2IE_Pos   (2U)
     
    #define TIM_DIER_CC2IE_Msk   (0x1UL << TIM_DIER_CC2IE_Pos)
     
    #define TIM_DIER_CC2IE   TIM_DIER_CC2IE_Msk
     
    #define TIM_DIER_CC3IE_Pos   (3U)
     
    #define TIM_DIER_CC3IE_Msk   (0x1UL << TIM_DIER_CC3IE_Pos)
     
    #define TIM_DIER_CC3IE   TIM_DIER_CC3IE_Msk
     
    #define TIM_DIER_CC4IE_Pos   (4U)
     
    #define TIM_DIER_CC4IE_Msk   (0x1UL << TIM_DIER_CC4IE_Pos)
     
    #define TIM_DIER_CC4IE   TIM_DIER_CC4IE_Msk
     
    #define TIM_DIER_COMIE_Pos   (5U)
     
    #define TIM_DIER_COMIE_Msk   (0x1UL << TIM_DIER_COMIE_Pos)
     
    #define TIM_DIER_COMIE   TIM_DIER_COMIE_Msk
     
    #define TIM_DIER_TIE_Pos   (6U)
     
    #define TIM_DIER_TIE_Msk   (0x1UL << TIM_DIER_TIE_Pos)
     
    #define TIM_DIER_TIE   TIM_DIER_TIE_Msk
     
    #define TIM_DIER_BIE_Pos   (7U)
     
    #define TIM_DIER_BIE_Msk   (0x1UL << TIM_DIER_BIE_Pos)
     
    #define TIM_DIER_BIE   TIM_DIER_BIE_Msk
     
    #define TIM_DIER_UDE_Pos   (8U)
     
    #define TIM_DIER_UDE_Msk   (0x1UL << TIM_DIER_UDE_Pos)
     
    #define TIM_DIER_UDE   TIM_DIER_UDE_Msk
     
    #define TIM_DIER_CC1DE_Pos   (9U)
     
    #define TIM_DIER_CC1DE_Msk   (0x1UL << TIM_DIER_CC1DE_Pos)
     
    #define TIM_DIER_CC1DE   TIM_DIER_CC1DE_Msk
     
    #define TIM_DIER_CC2DE_Pos   (10U)
     
    #define TIM_DIER_CC2DE_Msk   (0x1UL << TIM_DIER_CC2DE_Pos)
     
    #define TIM_DIER_CC2DE   TIM_DIER_CC2DE_Msk
     
    #define TIM_DIER_CC3DE_Pos   (11U)
     
    #define TIM_DIER_CC3DE_Msk   (0x1UL << TIM_DIER_CC3DE_Pos)
     
    #define TIM_DIER_CC3DE   TIM_DIER_CC3DE_Msk
     
    #define TIM_DIER_CC4DE_Pos   (12U)
     
    #define TIM_DIER_CC4DE_Msk   (0x1UL << TIM_DIER_CC4DE_Pos)
     
    #define TIM_DIER_CC4DE   TIM_DIER_CC4DE_Msk
     
    #define TIM_DIER_COMDE_Pos   (13U)
     
    #define TIM_DIER_COMDE_Msk   (0x1UL << TIM_DIER_COMDE_Pos)
     
    #define TIM_DIER_COMDE   TIM_DIER_COMDE_Msk
     
    #define TIM_DIER_TDE_Pos   (14U)
     
    #define TIM_DIER_TDE_Msk   (0x1UL << TIM_DIER_TDE_Pos)
     
    #define TIM_DIER_TDE   TIM_DIER_TDE_Msk
     
    #define TIM_SR_UIF_Pos   (0U)
     
    #define TIM_SR_UIF_Msk   (0x1UL << TIM_SR_UIF_Pos)
     
    #define TIM_SR_UIF   TIM_SR_UIF_Msk
     
    #define TIM_SR_CC1IF_Pos   (1U)
     
    #define TIM_SR_CC1IF_Msk   (0x1UL << TIM_SR_CC1IF_Pos)
     
    #define TIM_SR_CC1IF   TIM_SR_CC1IF_Msk
     
    #define TIM_SR_CC2IF_Pos   (2U)
     
    #define TIM_SR_CC2IF_Msk   (0x1UL << TIM_SR_CC2IF_Pos)
     
    #define TIM_SR_CC2IF   TIM_SR_CC2IF_Msk
     
    #define TIM_SR_CC3IF_Pos   (3U)
     
    #define TIM_SR_CC3IF_Msk   (0x1UL << TIM_SR_CC3IF_Pos)
     
    #define TIM_SR_CC3IF   TIM_SR_CC3IF_Msk
     
    #define TIM_SR_CC4IF_Pos   (4U)
     
    #define TIM_SR_CC4IF_Msk   (0x1UL << TIM_SR_CC4IF_Pos)
     
    #define TIM_SR_CC4IF   TIM_SR_CC4IF_Msk
     
    #define TIM_SR_COMIF_Pos   (5U)
     
    #define TIM_SR_COMIF_Msk   (0x1UL << TIM_SR_COMIF_Pos)
     
    #define TIM_SR_COMIF   TIM_SR_COMIF_Msk
     
    #define TIM_SR_TIF_Pos   (6U)
     
    #define TIM_SR_TIF_Msk   (0x1UL << TIM_SR_TIF_Pos)
     
    #define TIM_SR_TIF   TIM_SR_TIF_Msk
     
    #define TIM_SR_BIF_Pos   (7U)
     
    #define TIM_SR_BIF_Msk   (0x1UL << TIM_SR_BIF_Pos)
     
    #define TIM_SR_BIF   TIM_SR_BIF_Msk
     
    #define TIM_SR_CC1OF_Pos   (9U)
     
    #define TIM_SR_CC1OF_Msk   (0x1UL << TIM_SR_CC1OF_Pos)
     
    #define TIM_SR_CC1OF   TIM_SR_CC1OF_Msk
     
    #define TIM_SR_CC2OF_Pos   (10U)
     
    #define TIM_SR_CC2OF_Msk   (0x1UL << TIM_SR_CC2OF_Pos)
     
    #define TIM_SR_CC2OF   TIM_SR_CC2OF_Msk
     
    #define TIM_SR_CC3OF_Pos   (11U)
     
    #define TIM_SR_CC3OF_Msk   (0x1UL << TIM_SR_CC3OF_Pos)
     
    #define TIM_SR_CC3OF   TIM_SR_CC3OF_Msk
     
    #define TIM_SR_CC4OF_Pos   (12U)
     
    #define TIM_SR_CC4OF_Msk   (0x1UL << TIM_SR_CC4OF_Pos)
     
    #define TIM_SR_CC4OF   TIM_SR_CC4OF_Msk
     
    #define TIM_EGR_UG_Pos   (0U)
     
    #define TIM_EGR_UG_Msk   (0x1UL << TIM_EGR_UG_Pos)
     
    #define TIM_EGR_UG   TIM_EGR_UG_Msk
     
    #define TIM_EGR_CC1G_Pos   (1U)
     
    #define TIM_EGR_CC1G_Msk   (0x1UL << TIM_EGR_CC1G_Pos)
     
    #define TIM_EGR_CC1G   TIM_EGR_CC1G_Msk
     
    #define TIM_EGR_CC2G_Pos   (2U)
     
    #define TIM_EGR_CC2G_Msk   (0x1UL << TIM_EGR_CC2G_Pos)
     
    #define TIM_EGR_CC2G   TIM_EGR_CC2G_Msk
     
    #define TIM_EGR_CC3G_Pos   (3U)
     
    #define TIM_EGR_CC3G_Msk   (0x1UL << TIM_EGR_CC3G_Pos)
     
    #define TIM_EGR_CC3G   TIM_EGR_CC3G_Msk
     
    #define TIM_EGR_CC4G_Pos   (4U)
     
    #define TIM_EGR_CC4G_Msk   (0x1UL << TIM_EGR_CC4G_Pos)
     
    #define TIM_EGR_CC4G   TIM_EGR_CC4G_Msk
     
    #define TIM_EGR_COMG_Pos   (5U)
     
    #define TIM_EGR_COMG_Msk   (0x1UL << TIM_EGR_COMG_Pos)
     
    #define TIM_EGR_COMG   TIM_EGR_COMG_Msk
     
    #define TIM_EGR_TG_Pos   (6U)
     
    #define TIM_EGR_TG_Msk   (0x1UL << TIM_EGR_TG_Pos)
     
    #define TIM_EGR_TG   TIM_EGR_TG_Msk
     
    #define TIM_EGR_BG_Pos   (7U)
     
    #define TIM_EGR_BG_Msk   (0x1UL << TIM_EGR_BG_Pos)
     
    #define TIM_EGR_BG   TIM_EGR_BG_Msk
     
    #define TIM_CCMR1_CC1S_Pos   (0U)
     
    #define TIM_CCMR1_CC1S_Msk   (0x3UL << TIM_CCMR1_CC1S_Pos)
     
    #define TIM_CCMR1_CC1S   TIM_CCMR1_CC1S_Msk
     
    #define TIM_CCMR1_CC1S_0   (0x1UL << TIM_CCMR1_CC1S_Pos)
     
    #define TIM_CCMR1_CC1S_1   (0x2UL << TIM_CCMR1_CC1S_Pos)
     
    #define TIM_CCMR1_OC1FE_Pos   (2U)
     
    #define TIM_CCMR1_OC1FE_Msk   (0x1UL << TIM_CCMR1_OC1FE_Pos)
     
    #define TIM_CCMR1_OC1FE   TIM_CCMR1_OC1FE_Msk
     
    #define TIM_CCMR1_OC1PE_Pos   (3U)
     
    #define TIM_CCMR1_OC1PE_Msk   (0x1UL << TIM_CCMR1_OC1PE_Pos)
     
    #define TIM_CCMR1_OC1PE   TIM_CCMR1_OC1PE_Msk
     
    #define TIM_CCMR1_OC1M_Pos   (4U)
     
    #define TIM_CCMR1_OC1M_Msk   (0x7UL << TIM_CCMR1_OC1M_Pos)
     
    #define TIM_CCMR1_OC1M   TIM_CCMR1_OC1M_Msk
     
    #define TIM_CCMR1_OC1M_0   (0x1UL << TIM_CCMR1_OC1M_Pos)
     
    #define TIM_CCMR1_OC1M_1   (0x2UL << TIM_CCMR1_OC1M_Pos)
     
    #define TIM_CCMR1_OC1M_2   (0x4UL << TIM_CCMR1_OC1M_Pos)
     
    #define TIM_CCMR1_OC1CE_Pos   (7U)
     
    #define TIM_CCMR1_OC1CE_Msk   (0x1UL << TIM_CCMR1_OC1CE_Pos)
     
    #define TIM_CCMR1_OC1CE   TIM_CCMR1_OC1CE_Msk
     
    #define TIM_CCMR1_CC2S_Pos   (8U)
     
    #define TIM_CCMR1_CC2S_Msk   (0x3UL << TIM_CCMR1_CC2S_Pos)
     
    #define TIM_CCMR1_CC2S   TIM_CCMR1_CC2S_Msk
     
    #define TIM_CCMR1_CC2S_0   (0x1UL << TIM_CCMR1_CC2S_Pos)
     
    #define TIM_CCMR1_CC2S_1   (0x2UL << TIM_CCMR1_CC2S_Pos)
     
    #define TIM_CCMR1_OC2FE_Pos   (10U)
     
    #define TIM_CCMR1_OC2FE_Msk   (0x1UL << TIM_CCMR1_OC2FE_Pos)
     
    #define TIM_CCMR1_OC2FE   TIM_CCMR1_OC2FE_Msk
     
    #define TIM_CCMR1_OC2PE_Pos   (11U)
     
    #define TIM_CCMR1_OC2PE_Msk   (0x1UL << TIM_CCMR1_OC2PE_Pos)
     
    #define TIM_CCMR1_OC2PE   TIM_CCMR1_OC2PE_Msk
     
    #define TIM_CCMR1_OC2M_Pos   (12U)
     
    #define TIM_CCMR1_OC2M_Msk   (0x7UL << TIM_CCMR1_OC2M_Pos)
     
    #define TIM_CCMR1_OC2M   TIM_CCMR1_OC2M_Msk
     
    #define TIM_CCMR1_OC2M_0   (0x1UL << TIM_CCMR1_OC2M_Pos)
     
    #define TIM_CCMR1_OC2M_1   (0x2UL << TIM_CCMR1_OC2M_Pos)
     
    #define TIM_CCMR1_OC2M_2   (0x4UL << TIM_CCMR1_OC2M_Pos)
     
    #define TIM_CCMR1_OC2CE_Pos   (15U)
     
    #define TIM_CCMR1_OC2CE_Msk   (0x1UL << TIM_CCMR1_OC2CE_Pos)
     
    #define TIM_CCMR1_OC2CE   TIM_CCMR1_OC2CE_Msk
     
    #define TIM_CCMR1_IC1PSC_Pos   (2U)
     
    #define TIM_CCMR1_IC1PSC_Msk   (0x3UL << TIM_CCMR1_IC1PSC_Pos)
     
    #define TIM_CCMR1_IC1PSC   TIM_CCMR1_IC1PSC_Msk
     
    #define TIM_CCMR1_IC1PSC_0   (0x1UL << TIM_CCMR1_IC1PSC_Pos)
     
    #define TIM_CCMR1_IC1PSC_1   (0x2UL << TIM_CCMR1_IC1PSC_Pos)
     
    #define TIM_CCMR1_IC1F_Pos   (4U)
     
    #define TIM_CCMR1_IC1F_Msk   (0xFUL << TIM_CCMR1_IC1F_Pos)
     
    #define TIM_CCMR1_IC1F   TIM_CCMR1_IC1F_Msk
     
    #define TIM_CCMR1_IC1F_0   (0x1UL << TIM_CCMR1_IC1F_Pos)
     
    #define TIM_CCMR1_IC1F_1   (0x2UL << TIM_CCMR1_IC1F_Pos)
     
    #define TIM_CCMR1_IC1F_2   (0x4UL << TIM_CCMR1_IC1F_Pos)
     
    #define TIM_CCMR1_IC1F_3   (0x8UL << TIM_CCMR1_IC1F_Pos)
     
    #define TIM_CCMR1_IC2PSC_Pos   (10U)
     
    #define TIM_CCMR1_IC2PSC_Msk   (0x3UL << TIM_CCMR1_IC2PSC_Pos)
     
    #define TIM_CCMR1_IC2PSC   TIM_CCMR1_IC2PSC_Msk
     
    #define TIM_CCMR1_IC2PSC_0   (0x1UL << TIM_CCMR1_IC2PSC_Pos)
     
    #define TIM_CCMR1_IC2PSC_1   (0x2UL << TIM_CCMR1_IC2PSC_Pos)
     
    #define TIM_CCMR1_IC2F_Pos   (12U)
     
    #define TIM_CCMR1_IC2F_Msk   (0xFUL << TIM_CCMR1_IC2F_Pos)
     
    #define TIM_CCMR1_IC2F   TIM_CCMR1_IC2F_Msk
     
    #define TIM_CCMR1_IC2F_0   (0x1UL << TIM_CCMR1_IC2F_Pos)
     
    #define TIM_CCMR1_IC2F_1   (0x2UL << TIM_CCMR1_IC2F_Pos)
     
    #define TIM_CCMR1_IC2F_2   (0x4UL << TIM_CCMR1_IC2F_Pos)
     
    #define TIM_CCMR1_IC2F_3   (0x8UL << TIM_CCMR1_IC2F_Pos)
     
    #define TIM_CCMR2_CC3S_Pos   (0U)
     
    #define TIM_CCMR2_CC3S_Msk   (0x3UL << TIM_CCMR2_CC3S_Pos)
     
    #define TIM_CCMR2_CC3S   TIM_CCMR2_CC3S_Msk
     
    #define TIM_CCMR2_CC3S_0   (0x1UL << TIM_CCMR2_CC3S_Pos)
     
    #define TIM_CCMR2_CC3S_1   (0x2UL << TIM_CCMR2_CC3S_Pos)
     
    #define TIM_CCMR2_OC3FE_Pos   (2U)
     
    #define TIM_CCMR2_OC3FE_Msk   (0x1UL << TIM_CCMR2_OC3FE_Pos)
     
    #define TIM_CCMR2_OC3FE   TIM_CCMR2_OC3FE_Msk
     
    #define TIM_CCMR2_OC3PE_Pos   (3U)
     
    #define TIM_CCMR2_OC3PE_Msk   (0x1UL << TIM_CCMR2_OC3PE_Pos)
     
    #define TIM_CCMR2_OC3PE   TIM_CCMR2_OC3PE_Msk
     
    #define TIM_CCMR2_OC3M_Pos   (4U)
     
    #define TIM_CCMR2_OC3M_Msk   (0x7UL << TIM_CCMR2_OC3M_Pos)
     
    #define TIM_CCMR2_OC3M   TIM_CCMR2_OC3M_Msk
     
    #define TIM_CCMR2_OC3M_0   (0x1UL << TIM_CCMR2_OC3M_Pos)
     
    #define TIM_CCMR2_OC3M_1   (0x2UL << TIM_CCMR2_OC3M_Pos)
     
    #define TIM_CCMR2_OC3M_2   (0x4UL << TIM_CCMR2_OC3M_Pos)
     
    #define TIM_CCMR2_OC3CE_Pos   (7U)
     
    #define TIM_CCMR2_OC3CE_Msk   (0x1UL << TIM_CCMR2_OC3CE_Pos)
     
    #define TIM_CCMR2_OC3CE   TIM_CCMR2_OC3CE_Msk
     
    #define TIM_CCMR2_CC4S_Pos   (8U)
     
    #define TIM_CCMR2_CC4S_Msk   (0x3UL << TIM_CCMR2_CC4S_Pos)
     
    #define TIM_CCMR2_CC4S   TIM_CCMR2_CC4S_Msk
     
    #define TIM_CCMR2_CC4S_0   (0x1UL << TIM_CCMR2_CC4S_Pos)
     
    #define TIM_CCMR2_CC4S_1   (0x2UL << TIM_CCMR2_CC4S_Pos)
     
    #define TIM_CCMR2_OC4FE_Pos   (10U)
     
    #define TIM_CCMR2_OC4FE_Msk   (0x1UL << TIM_CCMR2_OC4FE_Pos)
     
    #define TIM_CCMR2_OC4FE   TIM_CCMR2_OC4FE_Msk
     
    #define TIM_CCMR2_OC4PE_Pos   (11U)
     
    #define TIM_CCMR2_OC4PE_Msk   (0x1UL << TIM_CCMR2_OC4PE_Pos)
     
    #define TIM_CCMR2_OC4PE   TIM_CCMR2_OC4PE_Msk
     
    #define TIM_CCMR2_OC4M_Pos   (12U)
     
    #define TIM_CCMR2_OC4M_Msk   (0x7UL << TIM_CCMR2_OC4M_Pos)
     
    #define TIM_CCMR2_OC4M   TIM_CCMR2_OC4M_Msk
     
    #define TIM_CCMR2_OC4M_0   (0x1UL << TIM_CCMR2_OC4M_Pos)
     
    #define TIM_CCMR2_OC4M_1   (0x2UL << TIM_CCMR2_OC4M_Pos)
     
    #define TIM_CCMR2_OC4M_2   (0x4UL << TIM_CCMR2_OC4M_Pos)
     
    #define TIM_CCMR2_OC4CE_Pos   (15U)
     
    #define TIM_CCMR2_OC4CE_Msk   (0x1UL << TIM_CCMR2_OC4CE_Pos)
     
    #define TIM_CCMR2_OC4CE   TIM_CCMR2_OC4CE_Msk
     
    #define TIM_CCMR2_IC3PSC_Pos   (2U)
     
    #define TIM_CCMR2_IC3PSC_Msk   (0x3UL << TIM_CCMR2_IC3PSC_Pos)
     
    #define TIM_CCMR2_IC3PSC   TIM_CCMR2_IC3PSC_Msk
     
    #define TIM_CCMR2_IC3PSC_0   (0x1UL << TIM_CCMR2_IC3PSC_Pos)
     
    #define TIM_CCMR2_IC3PSC_1   (0x2UL << TIM_CCMR2_IC3PSC_Pos)
     
    #define TIM_CCMR2_IC3F_Pos   (4U)
     
    #define TIM_CCMR2_IC3F_Msk   (0xFUL << TIM_CCMR2_IC3F_Pos)
     
    #define TIM_CCMR2_IC3F   TIM_CCMR2_IC3F_Msk
     
    #define TIM_CCMR2_IC3F_0   (0x1UL << TIM_CCMR2_IC3F_Pos)
     
    #define TIM_CCMR2_IC3F_1   (0x2UL << TIM_CCMR2_IC3F_Pos)
     
    #define TIM_CCMR2_IC3F_2   (0x4UL << TIM_CCMR2_IC3F_Pos)
     
    #define TIM_CCMR2_IC3F_3   (0x8UL << TIM_CCMR2_IC3F_Pos)
     
    #define TIM_CCMR2_IC4PSC_Pos   (10U)
     
    #define TIM_CCMR2_IC4PSC_Msk   (0x3UL << TIM_CCMR2_IC4PSC_Pos)
     
    #define TIM_CCMR2_IC4PSC   TIM_CCMR2_IC4PSC_Msk
     
    #define TIM_CCMR2_IC4PSC_0   (0x1UL << TIM_CCMR2_IC4PSC_Pos)
     
    #define TIM_CCMR2_IC4PSC_1   (0x2UL << TIM_CCMR2_IC4PSC_Pos)
     
    #define TIM_CCMR2_IC4F_Pos   (12U)
     
    #define TIM_CCMR2_IC4F_Msk   (0xFUL << TIM_CCMR2_IC4F_Pos)
     
    #define TIM_CCMR2_IC4F   TIM_CCMR2_IC4F_Msk
     
    #define TIM_CCMR2_IC4F_0   (0x1UL << TIM_CCMR2_IC4F_Pos)
     
    #define TIM_CCMR2_IC4F_1   (0x2UL << TIM_CCMR2_IC4F_Pos)
     
    #define TIM_CCMR2_IC4F_2   (0x4UL << TIM_CCMR2_IC4F_Pos)
     
    #define TIM_CCMR2_IC4F_3   (0x8UL << TIM_CCMR2_IC4F_Pos)
     
    #define TIM_CCER_CC1E_Pos   (0U)
     
    #define TIM_CCER_CC1E_Msk   (0x1UL << TIM_CCER_CC1E_Pos)
     
    #define TIM_CCER_CC1E   TIM_CCER_CC1E_Msk
     
    #define TIM_CCER_CC1P_Pos   (1U)
     
    #define TIM_CCER_CC1P_Msk   (0x1UL << TIM_CCER_CC1P_Pos)
     
    #define TIM_CCER_CC1P   TIM_CCER_CC1P_Msk
     
    #define TIM_CCER_CC1NE_Pos   (2U)
     
    #define TIM_CCER_CC1NE_Msk   (0x1UL << TIM_CCER_CC1NE_Pos)
     
    #define TIM_CCER_CC1NE   TIM_CCER_CC1NE_Msk
     
    #define TIM_CCER_CC1NP_Pos   (3U)
     
    #define TIM_CCER_CC1NP_Msk   (0x1UL << TIM_CCER_CC1NP_Pos)
     
    #define TIM_CCER_CC1NP   TIM_CCER_CC1NP_Msk
     
    #define TIM_CCER_CC2E_Pos   (4U)
     
    #define TIM_CCER_CC2E_Msk   (0x1UL << TIM_CCER_CC2E_Pos)
     
    #define TIM_CCER_CC2E   TIM_CCER_CC2E_Msk
     
    #define TIM_CCER_CC2P_Pos   (5U)
     
    #define TIM_CCER_CC2P_Msk   (0x1UL << TIM_CCER_CC2P_Pos)
     
    #define TIM_CCER_CC2P   TIM_CCER_CC2P_Msk
     
    #define TIM_CCER_CC2NE_Pos   (6U)
     
    #define TIM_CCER_CC2NE_Msk   (0x1UL << TIM_CCER_CC2NE_Pos)
     
    #define TIM_CCER_CC2NE   TIM_CCER_CC2NE_Msk
     
    #define TIM_CCER_CC2NP_Pos   (7U)
     
    #define TIM_CCER_CC2NP_Msk   (0x1UL << TIM_CCER_CC2NP_Pos)
     
    #define TIM_CCER_CC2NP   TIM_CCER_CC2NP_Msk
     
    #define TIM_CCER_CC3E_Pos   (8U)
     
    #define TIM_CCER_CC3E_Msk   (0x1UL << TIM_CCER_CC3E_Pos)
     
    #define TIM_CCER_CC3E   TIM_CCER_CC3E_Msk
     
    #define TIM_CCER_CC3P_Pos   (9U)
     
    #define TIM_CCER_CC3P_Msk   (0x1UL << TIM_CCER_CC3P_Pos)
     
    #define TIM_CCER_CC3P   TIM_CCER_CC3P_Msk
     
    #define TIM_CCER_CC3NE_Pos   (10U)
     
    #define TIM_CCER_CC3NE_Msk   (0x1UL << TIM_CCER_CC3NE_Pos)
     
    #define TIM_CCER_CC3NE   TIM_CCER_CC3NE_Msk
     
    #define TIM_CCER_CC3NP_Pos   (11U)
     
    #define TIM_CCER_CC3NP_Msk   (0x1UL << TIM_CCER_CC3NP_Pos)
     
    #define TIM_CCER_CC3NP   TIM_CCER_CC3NP_Msk
     
    #define TIM_CCER_CC4E_Pos   (12U)
     
    #define TIM_CCER_CC4E_Msk   (0x1UL << TIM_CCER_CC4E_Pos)
     
    #define TIM_CCER_CC4E   TIM_CCER_CC4E_Msk
     
    #define TIM_CCER_CC4P_Pos   (13U)
     
    #define TIM_CCER_CC4P_Msk   (0x1UL << TIM_CCER_CC4P_Pos)
     
    #define TIM_CCER_CC4P   TIM_CCER_CC4P_Msk
     
    #define TIM_CCER_CC4NP_Pos   (15U)
     
    #define TIM_CCER_CC4NP_Msk   (0x1UL << TIM_CCER_CC4NP_Pos)
     
    #define TIM_CCER_CC4NP   TIM_CCER_CC4NP_Msk
     
    #define TIM_CNT_CNT_Pos   (0U)
     
    #define TIM_CNT_CNT_Msk   (0xFFFFFFFFUL << TIM_CNT_CNT_Pos)
     
    #define TIM_CNT_CNT   TIM_CNT_CNT_Msk
     
    #define TIM_PSC_PSC_Pos   (0U)
     
    #define TIM_PSC_PSC_Msk   (0xFFFFUL << TIM_PSC_PSC_Pos)
     
    #define TIM_PSC_PSC   TIM_PSC_PSC_Msk
     
    #define TIM_ARR_ARR_Pos   (0U)
     
    #define TIM_ARR_ARR_Msk   (0xFFFFFFFFUL << TIM_ARR_ARR_Pos)
     
    #define TIM_ARR_ARR   TIM_ARR_ARR_Msk
     
    #define TIM_RCR_REP_Pos   (0U)
     
    #define TIM_RCR_REP_Msk   (0xFFUL << TIM_RCR_REP_Pos)
     
    #define TIM_RCR_REP   TIM_RCR_REP_Msk
     
    #define TIM_CCR1_CCR1_Pos   (0U)
     
    #define TIM_CCR1_CCR1_Msk   (0xFFFFUL << TIM_CCR1_CCR1_Pos)
     
    #define TIM_CCR1_CCR1   TIM_CCR1_CCR1_Msk
     
    #define TIM_CCR2_CCR2_Pos   (0U)
     
    #define TIM_CCR2_CCR2_Msk   (0xFFFFUL << TIM_CCR2_CCR2_Pos)
     
    #define TIM_CCR2_CCR2   TIM_CCR2_CCR2_Msk
     
    #define TIM_CCR3_CCR3_Pos   (0U)
     
    #define TIM_CCR3_CCR3_Msk   (0xFFFFUL << TIM_CCR3_CCR3_Pos)
     
    #define TIM_CCR3_CCR3   TIM_CCR3_CCR3_Msk
     
    #define TIM_CCR4_CCR4_Pos   (0U)
     
    #define TIM_CCR4_CCR4_Msk   (0xFFFFUL << TIM_CCR4_CCR4_Pos)
     
    #define TIM_CCR4_CCR4   TIM_CCR4_CCR4_Msk
     
    #define TIM_BDTR_DTG_Pos   (0U)
     
    #define TIM_BDTR_DTG_Msk   (0xFFUL << TIM_BDTR_DTG_Pos)
     
    #define TIM_BDTR_DTG   TIM_BDTR_DTG_Msk
     
    #define TIM_BDTR_DTG_0   (0x01UL << TIM_BDTR_DTG_Pos)
     
    #define TIM_BDTR_DTG_1   (0x02UL << TIM_BDTR_DTG_Pos)
     
    #define TIM_BDTR_DTG_2   (0x04UL << TIM_BDTR_DTG_Pos)
     
    #define TIM_BDTR_DTG_3   (0x08UL << TIM_BDTR_DTG_Pos)
     
    #define TIM_BDTR_DTG_4   (0x10UL << TIM_BDTR_DTG_Pos)
     
    #define TIM_BDTR_DTG_5   (0x20UL << TIM_BDTR_DTG_Pos)
     
    #define TIM_BDTR_DTG_6   (0x40UL << TIM_BDTR_DTG_Pos)
     
    #define TIM_BDTR_DTG_7   (0x80UL << TIM_BDTR_DTG_Pos)
     
    #define TIM_BDTR_LOCK_Pos   (8U)
     
    #define TIM_BDTR_LOCK_Msk   (0x3UL << TIM_BDTR_LOCK_Pos)
     
    #define TIM_BDTR_LOCK   TIM_BDTR_LOCK_Msk
     
    #define TIM_BDTR_LOCK_0   (0x1UL << TIM_BDTR_LOCK_Pos)
     
    #define TIM_BDTR_LOCK_1   (0x2UL << TIM_BDTR_LOCK_Pos)
     
    #define TIM_BDTR_OSSI_Pos   (10U)
     
    #define TIM_BDTR_OSSI_Msk   (0x1UL << TIM_BDTR_OSSI_Pos)
     
    #define TIM_BDTR_OSSI   TIM_BDTR_OSSI_Msk
     
    #define TIM_BDTR_OSSR_Pos   (11U)
     
    #define TIM_BDTR_OSSR_Msk   (0x1UL << TIM_BDTR_OSSR_Pos)
     
    #define TIM_BDTR_OSSR   TIM_BDTR_OSSR_Msk
     
    #define TIM_BDTR_BKE_Pos   (12U)
     
    #define TIM_BDTR_BKE_Msk   (0x1UL << TIM_BDTR_BKE_Pos)
     
    #define TIM_BDTR_BKE   TIM_BDTR_BKE_Msk
     
    #define TIM_BDTR_BKP_Pos   (13U)
     
    #define TIM_BDTR_BKP_Msk   (0x1UL << TIM_BDTR_BKP_Pos)
     
    #define TIM_BDTR_BKP   TIM_BDTR_BKP_Msk
     
    #define TIM_BDTR_AOE_Pos   (14U)
     
    #define TIM_BDTR_AOE_Msk   (0x1UL << TIM_BDTR_AOE_Pos)
     
    #define TIM_BDTR_AOE   TIM_BDTR_AOE_Msk
     
    #define TIM_BDTR_MOE_Pos   (15U)
     
    #define TIM_BDTR_MOE_Msk   (0x1UL << TIM_BDTR_MOE_Pos)
     
    #define TIM_BDTR_MOE   TIM_BDTR_MOE_Msk
     
    #define TIM_DCR_DBA_Pos   (0U)
     
    #define TIM_DCR_DBA_Msk   (0x1FUL << TIM_DCR_DBA_Pos)
     
    #define TIM_DCR_DBA   TIM_DCR_DBA_Msk
     
    #define TIM_DCR_DBA_0   (0x01UL << TIM_DCR_DBA_Pos)
     
    #define TIM_DCR_DBA_1   (0x02UL << TIM_DCR_DBA_Pos)
     
    #define TIM_DCR_DBA_2   (0x04UL << TIM_DCR_DBA_Pos)
     
    #define TIM_DCR_DBA_3   (0x08UL << TIM_DCR_DBA_Pos)
     
    #define TIM_DCR_DBA_4   (0x10UL << TIM_DCR_DBA_Pos)
     
    #define TIM_DCR_DBL_Pos   (8U)
     
    #define TIM_DCR_DBL_Msk   (0x1FUL << TIM_DCR_DBL_Pos)
     
    #define TIM_DCR_DBL   TIM_DCR_DBL_Msk
     
    #define TIM_DCR_DBL_0   (0x01UL << TIM_DCR_DBL_Pos)
     
    #define TIM_DCR_DBL_1   (0x02UL << TIM_DCR_DBL_Pos)
     
    #define TIM_DCR_DBL_2   (0x04UL << TIM_DCR_DBL_Pos)
     
    #define TIM_DCR_DBL_3   (0x08UL << TIM_DCR_DBL_Pos)
     
    #define TIM_DCR_DBL_4   (0x10UL << TIM_DCR_DBL_Pos)
     
    #define TIM_DMAR_DMAB_Pos   (0U)
     
    #define TIM_DMAR_DMAB_Msk   (0xFFFFUL << TIM_DMAR_DMAB_Pos)
     
    #define TIM_DMAR_DMAB   TIM_DMAR_DMAB_Msk
     
    #define TIM_OR_TI1_RMP_Pos   (0U)
     
    #define TIM_OR_TI1_RMP_Msk   (0x3UL << TIM_OR_TI1_RMP_Pos)
     
    #define TIM_OR_TI1_RMP   TIM_OR_TI1_RMP_Msk
     
    #define TIM_OR_TI1_RMP_0   (0x1UL << TIM_OR_TI1_RMP_Pos)
     
    #define TIM_OR_TI1_RMP_1   (0x2UL << TIM_OR_TI1_RMP_Pos)
     
    #define TIM_OR_TI4_RMP_Pos   (6U)
     
    #define TIM_OR_TI4_RMP_Msk   (0x3UL << TIM_OR_TI4_RMP_Pos)
     
    #define TIM_OR_TI4_RMP   TIM_OR_TI4_RMP_Msk
     
    #define TIM_OR_TI4_RMP_0   (0x1UL << TIM_OR_TI4_RMP_Pos)
     
    #define TIM_OR_TI4_RMP_1   (0x2UL << TIM_OR_TI4_RMP_Pos)
     
    #define TIM_OR_ITR1_RMP_Pos   (10U)
     
    #define TIM_OR_ITR1_RMP_Msk   (0x3UL << TIM_OR_ITR1_RMP_Pos)
     
    #define TIM_OR_ITR1_RMP   TIM_OR_ITR1_RMP_Msk
     
    #define TIM_OR_ITR1_RMP_0   (0x1UL << TIM_OR_ITR1_RMP_Pos)
     
    #define TIM_OR_ITR1_RMP_1   (0x2UL << TIM_OR_ITR1_RMP_Pos)
     
    #define USART_SR_PE_Pos   (0U)
     
    #define USART_SR_PE_Msk   (0x1UL << USART_SR_PE_Pos)
     
    #define USART_SR_PE   USART_SR_PE_Msk
     
    #define USART_SR_FE_Pos   (1U)
     
    #define USART_SR_FE_Msk   (0x1UL << USART_SR_FE_Pos)
     
    #define USART_SR_FE   USART_SR_FE_Msk
     
    #define USART_SR_NE_Pos   (2U)
     
    #define USART_SR_NE_Msk   (0x1UL << USART_SR_NE_Pos)
     
    #define USART_SR_NE   USART_SR_NE_Msk
     
    #define USART_SR_ORE_Pos   (3U)
     
    #define USART_SR_ORE_Msk   (0x1UL << USART_SR_ORE_Pos)
     
    #define USART_SR_ORE   USART_SR_ORE_Msk
     
    #define USART_SR_IDLE_Pos   (4U)
     
    #define USART_SR_IDLE_Msk   (0x1UL << USART_SR_IDLE_Pos)
     
    #define USART_SR_IDLE   USART_SR_IDLE_Msk
     
    #define USART_SR_RXNE_Pos   (5U)
     
    #define USART_SR_RXNE_Msk   (0x1UL << USART_SR_RXNE_Pos)
     
    #define USART_SR_RXNE   USART_SR_RXNE_Msk
     
    #define USART_SR_TC_Pos   (6U)
     
    #define USART_SR_TC_Msk   (0x1UL << USART_SR_TC_Pos)
     
    #define USART_SR_TC   USART_SR_TC_Msk
     
    #define USART_SR_TXE_Pos   (7U)
     
    #define USART_SR_TXE_Msk   (0x1UL << USART_SR_TXE_Pos)
     
    #define USART_SR_TXE   USART_SR_TXE_Msk
     
    #define USART_SR_LBD_Pos   (8U)
     
    #define USART_SR_LBD_Msk   (0x1UL << USART_SR_LBD_Pos)
     
    #define USART_SR_LBD   USART_SR_LBD_Msk
     
    #define USART_SR_CTS_Pos   (9U)
     
    #define USART_SR_CTS_Msk   (0x1UL << USART_SR_CTS_Pos)
     
    #define USART_SR_CTS   USART_SR_CTS_Msk
     
    #define USART_DR_DR_Pos   (0U)
     
    #define USART_DR_DR_Msk   (0x1FFUL << USART_DR_DR_Pos)
     
    #define USART_DR_DR   USART_DR_DR_Msk
     
    #define USART_BRR_DIV_Fraction_Pos   (0U)
     
    #define USART_BRR_DIV_Fraction_Msk   (0xFUL << USART_BRR_DIV_Fraction_Pos)
     
    #define USART_BRR_DIV_Fraction   USART_BRR_DIV_Fraction_Msk
     
    #define USART_BRR_DIV_Mantissa_Pos   (4U)
     
    #define USART_BRR_DIV_Mantissa_Msk   (0xFFFUL << USART_BRR_DIV_Mantissa_Pos)
     
    #define USART_BRR_DIV_Mantissa   USART_BRR_DIV_Mantissa_Msk
     
    #define USART_CR1_SBK_Pos   (0U)
     
    #define USART_CR1_SBK_Msk   (0x1UL << USART_CR1_SBK_Pos)
     
    #define USART_CR1_SBK   USART_CR1_SBK_Msk
     
    #define USART_CR1_RWU_Pos   (1U)
     
    #define USART_CR1_RWU_Msk   (0x1UL << USART_CR1_RWU_Pos)
     
    #define USART_CR1_RWU   USART_CR1_RWU_Msk
     
    #define USART_CR1_RE_Pos   (2U)
     
    #define USART_CR1_RE_Msk   (0x1UL << USART_CR1_RE_Pos)
     
    #define USART_CR1_RE   USART_CR1_RE_Msk
     
    #define USART_CR1_TE_Pos   (3U)
     
    #define USART_CR1_TE_Msk   (0x1UL << USART_CR1_TE_Pos)
     
    #define USART_CR1_TE   USART_CR1_TE_Msk
     
    #define USART_CR1_IDLEIE_Pos   (4U)
     
    #define USART_CR1_IDLEIE_Msk   (0x1UL << USART_CR1_IDLEIE_Pos)
     
    #define USART_CR1_IDLEIE   USART_CR1_IDLEIE_Msk
     
    #define USART_CR1_RXNEIE_Pos   (5U)
     
    #define USART_CR1_RXNEIE_Msk   (0x1UL << USART_CR1_RXNEIE_Pos)
     
    #define USART_CR1_RXNEIE   USART_CR1_RXNEIE_Msk
     
    #define USART_CR1_TCIE_Pos   (6U)
     
    #define USART_CR1_TCIE_Msk   (0x1UL << USART_CR1_TCIE_Pos)
     
    #define USART_CR1_TCIE   USART_CR1_TCIE_Msk
     
    #define USART_CR1_TXEIE_Pos   (7U)
     
    #define USART_CR1_TXEIE_Msk   (0x1UL << USART_CR1_TXEIE_Pos)
     
    #define USART_CR1_TXEIE   USART_CR1_TXEIE_Msk
     
    #define USART_CR1_PEIE_Pos   (8U)
     
    #define USART_CR1_PEIE_Msk   (0x1UL << USART_CR1_PEIE_Pos)
     
    #define USART_CR1_PEIE   USART_CR1_PEIE_Msk
     
    #define USART_CR1_PS_Pos   (9U)
     
    #define USART_CR1_PS_Msk   (0x1UL << USART_CR1_PS_Pos)
     
    #define USART_CR1_PS   USART_CR1_PS_Msk
     
    #define USART_CR1_PCE_Pos   (10U)
     
    #define USART_CR1_PCE_Msk   (0x1UL << USART_CR1_PCE_Pos)
     
    #define USART_CR1_PCE   USART_CR1_PCE_Msk
     
    #define USART_CR1_WAKE_Pos   (11U)
     
    #define USART_CR1_WAKE_Msk   (0x1UL << USART_CR1_WAKE_Pos)
     
    #define USART_CR1_WAKE   USART_CR1_WAKE_Msk
     
    #define USART_CR1_M_Pos   (12U)
     
    #define USART_CR1_M_Msk   (0x1UL << USART_CR1_M_Pos)
     
    #define USART_CR1_M   USART_CR1_M_Msk
     
    #define USART_CR1_UE_Pos   (13U)
     
    #define USART_CR1_UE_Msk   (0x1UL << USART_CR1_UE_Pos)
     
    #define USART_CR1_UE   USART_CR1_UE_Msk
     
    #define USART_CR1_OVER8_Pos   (15U)
     
    #define USART_CR1_OVER8_Msk   (0x1UL << USART_CR1_OVER8_Pos)
     
    #define USART_CR1_OVER8   USART_CR1_OVER8_Msk
     
    #define USART_CR2_ADD_Pos   (0U)
     
    #define USART_CR2_ADD_Msk   (0xFUL << USART_CR2_ADD_Pos)
     
    #define USART_CR2_ADD   USART_CR2_ADD_Msk
     
    #define USART_CR2_LBDL_Pos   (5U)
     
    #define USART_CR2_LBDL_Msk   (0x1UL << USART_CR2_LBDL_Pos)
     
    #define USART_CR2_LBDL   USART_CR2_LBDL_Msk
     
    #define USART_CR2_LBDIE_Pos   (6U)
     
    #define USART_CR2_LBDIE_Msk   (0x1UL << USART_CR2_LBDIE_Pos)
     
    #define USART_CR2_LBDIE   USART_CR2_LBDIE_Msk
     
    #define USART_CR2_LBCL_Pos   (8U)
     
    #define USART_CR2_LBCL_Msk   (0x1UL << USART_CR2_LBCL_Pos)
     
    #define USART_CR2_LBCL   USART_CR2_LBCL_Msk
     
    #define USART_CR2_CPHA_Pos   (9U)
     
    #define USART_CR2_CPHA_Msk   (0x1UL << USART_CR2_CPHA_Pos)
     
    #define USART_CR2_CPHA   USART_CR2_CPHA_Msk
     
    #define USART_CR2_CPOL_Pos   (10U)
     
    #define USART_CR2_CPOL_Msk   (0x1UL << USART_CR2_CPOL_Pos)
     
    #define USART_CR2_CPOL   USART_CR2_CPOL_Msk
     
    #define USART_CR2_CLKEN_Pos   (11U)
     
    #define USART_CR2_CLKEN_Msk   (0x1UL << USART_CR2_CLKEN_Pos)
     
    #define USART_CR2_CLKEN   USART_CR2_CLKEN_Msk
     
    #define USART_CR2_STOP_Pos   (12U)
     
    #define USART_CR2_STOP_Msk   (0x3UL << USART_CR2_STOP_Pos)
     
    #define USART_CR2_STOP   USART_CR2_STOP_Msk
     
    #define USART_CR2_STOP_0   (0x1UL << USART_CR2_STOP_Pos)
     
    #define USART_CR2_STOP_1   (0x2UL << USART_CR2_STOP_Pos)
     
    #define USART_CR2_LINEN_Pos   (14U)
     
    #define USART_CR2_LINEN_Msk   (0x1UL << USART_CR2_LINEN_Pos)
     
    #define USART_CR2_LINEN   USART_CR2_LINEN_Msk
     
    #define USART_CR3_EIE_Pos   (0U)
     
    #define USART_CR3_EIE_Msk   (0x1UL << USART_CR3_EIE_Pos)
     
    #define USART_CR3_EIE   USART_CR3_EIE_Msk
     
    #define USART_CR3_IREN_Pos   (1U)
     
    #define USART_CR3_IREN_Msk   (0x1UL << USART_CR3_IREN_Pos)
     
    #define USART_CR3_IREN   USART_CR3_IREN_Msk
     
    #define USART_CR3_IRLP_Pos   (2U)
     
    #define USART_CR3_IRLP_Msk   (0x1UL << USART_CR3_IRLP_Pos)
     
    #define USART_CR3_IRLP   USART_CR3_IRLP_Msk
     
    #define USART_CR3_HDSEL_Pos   (3U)
     
    #define USART_CR3_HDSEL_Msk   (0x1UL << USART_CR3_HDSEL_Pos)
     
    #define USART_CR3_HDSEL   USART_CR3_HDSEL_Msk
     
    #define USART_CR3_NACK_Pos   (4U)
     
    #define USART_CR3_NACK_Msk   (0x1UL << USART_CR3_NACK_Pos)
     
    #define USART_CR3_NACK   USART_CR3_NACK_Msk
     
    #define USART_CR3_SCEN_Pos   (5U)
     
    #define USART_CR3_SCEN_Msk   (0x1UL << USART_CR3_SCEN_Pos)
     
    #define USART_CR3_SCEN   USART_CR3_SCEN_Msk
     
    #define USART_CR3_DMAR_Pos   (6U)
     
    #define USART_CR3_DMAR_Msk   (0x1UL << USART_CR3_DMAR_Pos)
     
    #define USART_CR3_DMAR   USART_CR3_DMAR_Msk
     
    #define USART_CR3_DMAT_Pos   (7U)
     
    #define USART_CR3_DMAT_Msk   (0x1UL << USART_CR3_DMAT_Pos)
     
    #define USART_CR3_DMAT   USART_CR3_DMAT_Msk
     
    #define USART_CR3_RTSE_Pos   (8U)
     
    #define USART_CR3_RTSE_Msk   (0x1UL << USART_CR3_RTSE_Pos)
     
    #define USART_CR3_RTSE   USART_CR3_RTSE_Msk
     
    #define USART_CR3_CTSE_Pos   (9U)
     
    #define USART_CR3_CTSE_Msk   (0x1UL << USART_CR3_CTSE_Pos)
     
    #define USART_CR3_CTSE   USART_CR3_CTSE_Msk
     
    #define USART_CR3_CTSIE_Pos   (10U)
     
    #define USART_CR3_CTSIE_Msk   (0x1UL << USART_CR3_CTSIE_Pos)
     
    #define USART_CR3_CTSIE   USART_CR3_CTSIE_Msk
     
    #define USART_CR3_ONEBIT_Pos   (11U)
     
    #define USART_CR3_ONEBIT_Msk   (0x1UL << USART_CR3_ONEBIT_Pos)
     
    #define USART_CR3_ONEBIT   USART_CR3_ONEBIT_Msk
     
    #define USART_GTPR_PSC_Pos   (0U)
     
    #define USART_GTPR_PSC_Msk   (0xFFUL << USART_GTPR_PSC_Pos)
     
    #define USART_GTPR_PSC   USART_GTPR_PSC_Msk
     
    #define USART_GTPR_PSC_0   (0x01UL << USART_GTPR_PSC_Pos)
     
    #define USART_GTPR_PSC_1   (0x02UL << USART_GTPR_PSC_Pos)
     
    #define USART_GTPR_PSC_2   (0x04UL << USART_GTPR_PSC_Pos)
     
    #define USART_GTPR_PSC_3   (0x08UL << USART_GTPR_PSC_Pos)
     
    #define USART_GTPR_PSC_4   (0x10UL << USART_GTPR_PSC_Pos)
     
    #define USART_GTPR_PSC_5   (0x20UL << USART_GTPR_PSC_Pos)
     
    #define USART_GTPR_PSC_6   (0x40UL << USART_GTPR_PSC_Pos)
     
    #define USART_GTPR_PSC_7   (0x80UL << USART_GTPR_PSC_Pos)
     
    #define USART_GTPR_GT_Pos   (8U)
     
    #define USART_GTPR_GT_Msk   (0xFFUL << USART_GTPR_GT_Pos)
     
    #define USART_GTPR_GT   USART_GTPR_GT_Msk
     
    #define WWDG_CR_T_Pos   (0U)
     
    #define WWDG_CR_T_Msk   (0x7FUL << WWDG_CR_T_Pos)
     
    #define WWDG_CR_T   WWDG_CR_T_Msk
     
    #define WWDG_CR_T_0   (0x01UL << WWDG_CR_T_Pos)
     
    #define WWDG_CR_T_1   (0x02UL << WWDG_CR_T_Pos)
     
    #define WWDG_CR_T_2   (0x04UL << WWDG_CR_T_Pos)
     
    #define WWDG_CR_T_3   (0x08UL << WWDG_CR_T_Pos)
     
    #define WWDG_CR_T_4   (0x10UL << WWDG_CR_T_Pos)
     
    #define WWDG_CR_T_5   (0x20UL << WWDG_CR_T_Pos)
     
    #define WWDG_CR_T_6   (0x40UL << WWDG_CR_T_Pos)
     
    #define WWDG_CR_T0   WWDG_CR_T_0
     
    #define WWDG_CR_T1   WWDG_CR_T_1
     
    #define WWDG_CR_T2   WWDG_CR_T_2
     
    #define WWDG_CR_T3   WWDG_CR_T_3
     
    #define WWDG_CR_T4   WWDG_CR_T_4
     
    #define WWDG_CR_T5   WWDG_CR_T_5
     
    #define WWDG_CR_T6   WWDG_CR_T_6
     
    #define WWDG_CR_WDGA_Pos   (7U)
     
    #define WWDG_CR_WDGA_Msk   (0x1UL << WWDG_CR_WDGA_Pos)
     
    #define WWDG_CR_WDGA   WWDG_CR_WDGA_Msk
     
    #define WWDG_CFR_W_Pos   (0U)
     
    #define WWDG_CFR_W_Msk   (0x7FUL << WWDG_CFR_W_Pos)
     
    #define WWDG_CFR_W   WWDG_CFR_W_Msk
     
    #define WWDG_CFR_W_0   (0x01UL << WWDG_CFR_W_Pos)
     
    #define WWDG_CFR_W_1   (0x02UL << WWDG_CFR_W_Pos)
     
    #define WWDG_CFR_W_2   (0x04UL << WWDG_CFR_W_Pos)
     
    #define WWDG_CFR_W_3   (0x08UL << WWDG_CFR_W_Pos)
     
    #define WWDG_CFR_W_4   (0x10UL << WWDG_CFR_W_Pos)
     
    #define WWDG_CFR_W_5   (0x20UL << WWDG_CFR_W_Pos)
     
    #define WWDG_CFR_W_6   (0x40UL << WWDG_CFR_W_Pos)
     
    #define WWDG_CFR_W0   WWDG_CFR_W_0
     
    #define WWDG_CFR_W1   WWDG_CFR_W_1
     
    #define WWDG_CFR_W2   WWDG_CFR_W_2
     
    #define WWDG_CFR_W3   WWDG_CFR_W_3
     
    #define WWDG_CFR_W4   WWDG_CFR_W_4
     
    #define WWDG_CFR_W5   WWDG_CFR_W_5
     
    #define WWDG_CFR_W6   WWDG_CFR_W_6
     
    #define WWDG_CFR_WDGTB_Pos   (7U)
     
    #define WWDG_CFR_WDGTB_Msk   (0x3UL << WWDG_CFR_WDGTB_Pos)
     
    #define WWDG_CFR_WDGTB   WWDG_CFR_WDGTB_Msk
     
    #define WWDG_CFR_WDGTB_0   (0x1UL << WWDG_CFR_WDGTB_Pos)
     
    #define WWDG_CFR_WDGTB_1   (0x2UL << WWDG_CFR_WDGTB_Pos)
     
    #define WWDG_CFR_WDGTB0   WWDG_CFR_WDGTB_0
     
    #define WWDG_CFR_WDGTB1   WWDG_CFR_WDGTB_1
     
    #define WWDG_CFR_EWI_Pos   (9U)
     
    #define WWDG_CFR_EWI_Msk   (0x1UL << WWDG_CFR_EWI_Pos)
     
    #define WWDG_CFR_EWI   WWDG_CFR_EWI_Msk
     
    #define WWDG_SR_EWIF_Pos   (0U)
     
    #define WWDG_SR_EWIF_Msk   (0x1UL << WWDG_SR_EWIF_Pos)
     
    #define WWDG_SR_EWIF   WWDG_SR_EWIF_Msk
     
    #define DBGMCU_IDCODE_DEV_ID_Pos   (0U)
     
    #define DBGMCU_IDCODE_DEV_ID_Msk   (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos)
     
    #define DBGMCU_IDCODE_DEV_ID   DBGMCU_IDCODE_DEV_ID_Msk
     
    #define DBGMCU_IDCODE_REV_ID_Pos   (16U)
     
    #define DBGMCU_IDCODE_REV_ID_Msk   (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos)
     
    #define DBGMCU_IDCODE_REV_ID   DBGMCU_IDCODE_REV_ID_Msk
     
    #define DBGMCU_CR_DBG_SLEEP_Pos   (0U)
     
    #define DBGMCU_CR_DBG_SLEEP_Msk   (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos)
     
    #define DBGMCU_CR_DBG_SLEEP   DBGMCU_CR_DBG_SLEEP_Msk
     
    #define DBGMCU_CR_DBG_STOP_Pos   (1U)
     
    #define DBGMCU_CR_DBG_STOP_Msk   (0x1UL << DBGMCU_CR_DBG_STOP_Pos)
     
    #define DBGMCU_CR_DBG_STOP   DBGMCU_CR_DBG_STOP_Msk
     
    #define DBGMCU_CR_DBG_STANDBY_Pos   (2U)
     
    #define DBGMCU_CR_DBG_STANDBY_Msk   (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos)
     
    #define DBGMCU_CR_DBG_STANDBY   DBGMCU_CR_DBG_STANDBY_Msk
     
    #define DBGMCU_CR_TRACE_IOEN_Pos   (5U)
     
    #define DBGMCU_CR_TRACE_IOEN_Msk   (0x1UL << DBGMCU_CR_TRACE_IOEN_Pos)
     
    #define DBGMCU_CR_TRACE_IOEN   DBGMCU_CR_TRACE_IOEN_Msk
     
    #define DBGMCU_CR_TRACE_MODE_Pos   (6U)
     
    #define DBGMCU_CR_TRACE_MODE_Msk   (0x3UL << DBGMCU_CR_TRACE_MODE_Pos)
     
    #define DBGMCU_CR_TRACE_MODE   DBGMCU_CR_TRACE_MODE_Msk
     
    #define DBGMCU_CR_TRACE_MODE_0   (0x1UL << DBGMCU_CR_TRACE_MODE_Pos)
     
    #define DBGMCU_CR_TRACE_MODE_1   (0x2UL << DBGMCU_CR_TRACE_MODE_Pos)
     
    #define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos   (0U)
     
    #define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk   (0x1UL << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos)
     
    #define DBGMCU_APB1_FZ_DBG_TIM2_STOP   DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk
     
    #define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos   (1U)
     
    #define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk   (0x1UL << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos)
     
    #define DBGMCU_APB1_FZ_DBG_TIM3_STOP   DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk
     
    #define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos   (2U)
     
    #define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk   (0x1UL << DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos)
     
    #define DBGMCU_APB1_FZ_DBG_TIM4_STOP   DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk
     
    #define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos   (3U)
     
    #define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk   (0x1UL << DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos)
     
    #define DBGMCU_APB1_FZ_DBG_TIM5_STOP   DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk
     
    #define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos   (4U)
     
    #define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk   (0x1UL << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos)
     
    #define DBGMCU_APB1_FZ_DBG_TIM6_STOP   DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk
     
    #define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos   (5U)
     
    #define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk   (0x1UL << DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos)
     
    #define DBGMCU_APB1_FZ_DBG_TIM7_STOP   DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk
     
    #define DBGMCU_APB1_FZ_DBG_TIM12_STOP_Pos   (6U)
     
    #define DBGMCU_APB1_FZ_DBG_TIM12_STOP_Msk   (0x1UL << DBGMCU_APB1_FZ_DBG_TIM12_STOP_Pos)
     
    #define DBGMCU_APB1_FZ_DBG_TIM12_STOP   DBGMCU_APB1_FZ_DBG_TIM12_STOP_Msk
     
    #define DBGMCU_APB1_FZ_DBG_TIM13_STOP_Pos   (7U)
     
    #define DBGMCU_APB1_FZ_DBG_TIM13_STOP_Msk   (0x1UL << DBGMCU_APB1_FZ_DBG_TIM13_STOP_Pos)
     
    #define DBGMCU_APB1_FZ_DBG_TIM13_STOP   DBGMCU_APB1_FZ_DBG_TIM13_STOP_Msk
     
    #define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos   (8U)
     
    #define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk   (0x1UL << DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos)
     
    #define DBGMCU_APB1_FZ_DBG_TIM14_STOP   DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk
     
    #define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos   (10U)
     
    #define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk   (0x1UL << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos)
     
    #define DBGMCU_APB1_FZ_DBG_RTC_STOP   DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk
     
    #define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos   (11U)
     
    #define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk   (0x1UL << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos)
     
    #define DBGMCU_APB1_FZ_DBG_WWDG_STOP   DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk
     
    #define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos   (12U)
     
    #define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk   (0x1UL << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos)
     
    #define DBGMCU_APB1_FZ_DBG_IWDG_STOP   DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk
     
    #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos   (21U)
     
    #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk   (0x1UL << DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos)
     
    #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT   DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk
     
    #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos   (22U)
     
    #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk   (0x1UL << DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos)
     
    #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT   DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk
     
    #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos   (23U)
     
    #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk   (0x1UL << DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos)
     
    #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT   DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk
     
    #define DBGMCU_APB1_FZ_DBG_CAN1_STOP_Pos   (25U)
     
    #define DBGMCU_APB1_FZ_DBG_CAN1_STOP_Msk   (0x1UL << DBGMCU_APB1_FZ_DBG_CAN1_STOP_Pos)
     
    #define DBGMCU_APB1_FZ_DBG_CAN1_STOP   DBGMCU_APB1_FZ_DBG_CAN1_STOP_Msk
     
    #define DBGMCU_APB1_FZ_DBG_CAN2_STOP_Pos   (26U)
     
    #define DBGMCU_APB1_FZ_DBG_CAN2_STOP_Msk   (0x1UL << DBGMCU_APB1_FZ_DBG_CAN2_STOP_Pos)
     
    #define DBGMCU_APB1_FZ_DBG_CAN2_STOP   DBGMCU_APB1_FZ_DBG_CAN2_STOP_Msk
     
    #define DBGMCU_APB1_FZ_DBG_IWDEG_STOP   DBGMCU_APB1_FZ_DBG_IWDG_STOP
     
    #define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos   (0U)
     
    #define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk   (0x1UL << DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos)
     
    #define DBGMCU_APB2_FZ_DBG_TIM1_STOP   DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk
     
    #define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos   (1U)
     
    #define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk   (0x1UL << DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos)
     
    #define DBGMCU_APB2_FZ_DBG_TIM8_STOP   DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk
     
    #define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos   (16U)
     
    #define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk   (0x1UL << DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos)
     
    #define DBGMCU_APB2_FZ_DBG_TIM9_STOP   DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk
     
    #define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos   (17U)
     
    #define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk   (0x1UL << DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos)
     
    #define DBGMCU_APB2_FZ_DBG_TIM10_STOP   DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk
     
    #define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos   (18U)
     
    #define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk   (0x1UL << DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos)
     
    #define DBGMCU_APB2_FZ_DBG_TIM11_STOP   DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk
     
    #define ETH_MACCR_WD_Pos   (23U)
     
    #define ETH_MACCR_WD_Msk   (0x1UL << ETH_MACCR_WD_Pos)
     
    #define ETH_MACCR_WD   ETH_MACCR_WD_Msk /* Watchdog disable */
     
    #define ETH_MACCR_JD_Pos   (22U)
     
    #define ETH_MACCR_JD_Msk   (0x1UL << ETH_MACCR_JD_Pos)
     
    #define ETH_MACCR_JD   ETH_MACCR_JD_Msk /* Jabber disable */
     
    #define ETH_MACCR_IFG_Pos   (17U)
     
    #define ETH_MACCR_IFG_Msk   (0x7UL << ETH_MACCR_IFG_Pos)
     
    #define ETH_MACCR_IFG   ETH_MACCR_IFG_Msk /* Inter-frame gap */
     
    #define ETH_MACCR_IFG_96Bit   0x00000000U /* Minimum IFG between frames during transmission is 96Bit */
     
    #define ETH_MACCR_IFG_88Bit   0x00020000U /* Minimum IFG between frames during transmission is 88Bit */
     
    #define ETH_MACCR_IFG_80Bit   0x00040000U /* Minimum IFG between frames during transmission is 80Bit */
     
    #define ETH_MACCR_IFG_72Bit   0x00060000U /* Minimum IFG between frames during transmission is 72Bit */
     
    #define ETH_MACCR_IFG_64Bit   0x00080000U /* Minimum IFG between frames during transmission is 64Bit */
     
    #define ETH_MACCR_IFG_56Bit   0x000A0000U /* Minimum IFG between frames during transmission is 56Bit */
     
    #define ETH_MACCR_IFG_48Bit   0x000C0000U /* Minimum IFG between frames during transmission is 48Bit */
     
    #define ETH_MACCR_IFG_40Bit   0x000E0000U /* Minimum IFG between frames during transmission is 40Bit */
     
    #define ETH_MACCR_CSD_Pos   (16U)
     
    #define ETH_MACCR_CSD_Msk   (0x1UL << ETH_MACCR_CSD_Pos)
     
    #define ETH_MACCR_CSD   ETH_MACCR_CSD_Msk /* Carrier sense disable (during transmission) */
     
    #define ETH_MACCR_FES_Pos   (14U)
     
    #define ETH_MACCR_FES_Msk   (0x1UL << ETH_MACCR_FES_Pos)
     
    #define ETH_MACCR_FES   ETH_MACCR_FES_Msk /* Fast ethernet speed */
     
    #define ETH_MACCR_ROD_Pos   (13U)
     
    #define ETH_MACCR_ROD_Msk   (0x1UL << ETH_MACCR_ROD_Pos)
     
    #define ETH_MACCR_ROD   ETH_MACCR_ROD_Msk /* Receive own disable */
     
    #define ETH_MACCR_LM_Pos   (12U)
     
    #define ETH_MACCR_LM_Msk   (0x1UL << ETH_MACCR_LM_Pos)
     
    #define ETH_MACCR_LM   ETH_MACCR_LM_Msk /* loopback mode */
     
    #define ETH_MACCR_DM_Pos   (11U)
     
    #define ETH_MACCR_DM_Msk   (0x1UL << ETH_MACCR_DM_Pos)
     
    #define ETH_MACCR_DM   ETH_MACCR_DM_Msk /* Duplex mode */
     
    #define ETH_MACCR_IPCO_Pos   (10U)
     
    #define ETH_MACCR_IPCO_Msk   (0x1UL << ETH_MACCR_IPCO_Pos)
     
    #define ETH_MACCR_IPCO   ETH_MACCR_IPCO_Msk /* IP Checksum offload */
     
    #define ETH_MACCR_RD_Pos   (9U)
     
    #define ETH_MACCR_RD_Msk   (0x1UL << ETH_MACCR_RD_Pos)
     
    #define ETH_MACCR_RD   ETH_MACCR_RD_Msk /* Retry disable */
     
    #define ETH_MACCR_APCS_Pos   (7U)
     
    #define ETH_MACCR_APCS_Msk   (0x1UL << ETH_MACCR_APCS_Pos)
     
    #define ETH_MACCR_APCS   ETH_MACCR_APCS_Msk /* Automatic Pad/CRC stripping */
     
    #define ETH_MACCR_BL_Pos   (5U)
     
    #define ETH_MACCR_BL_Msk   (0x3UL << ETH_MACCR_BL_Pos)
     
    #define ETH_MACCR_BL
     
    #define ETH_MACCR_BL_10   0x00000000U /* k = min (n, 10) */
     
    #define ETH_MACCR_BL_8   0x00000020U /* k = min (n, 8) */
     
    #define ETH_MACCR_BL_4   0x00000040U /* k = min (n, 4) */
     
    #define ETH_MACCR_BL_1   0x00000060U /* k = min (n, 1) */
     
    #define ETH_MACCR_DC_Pos   (4U)
     
    #define ETH_MACCR_DC_Msk   (0x1UL << ETH_MACCR_DC_Pos)
     
    #define ETH_MACCR_DC   ETH_MACCR_DC_Msk /* Defferal check */
     
    #define ETH_MACCR_TE_Pos   (3U)
     
    #define ETH_MACCR_TE_Msk   (0x1UL << ETH_MACCR_TE_Pos)
     
    #define ETH_MACCR_TE   ETH_MACCR_TE_Msk /* Transmitter enable */
     
    #define ETH_MACCR_RE_Pos   (2U)
     
    #define ETH_MACCR_RE_Msk   (0x1UL << ETH_MACCR_RE_Pos)
     
    #define ETH_MACCR_RE   ETH_MACCR_RE_Msk /* Receiver enable */
     
    #define ETH_MACFFR_RA_Pos   (31U)
     
    #define ETH_MACFFR_RA_Msk   (0x1UL << ETH_MACFFR_RA_Pos)
     
    #define ETH_MACFFR_RA   ETH_MACFFR_RA_Msk /* Receive all */
     
    #define ETH_MACFFR_HPF_Pos   (10U)
     
    #define ETH_MACFFR_HPF_Msk   (0x1UL << ETH_MACFFR_HPF_Pos)
     
    #define ETH_MACFFR_HPF   ETH_MACFFR_HPF_Msk /* Hash or perfect filter */
     
    #define ETH_MACFFR_SAF_Pos   (9U)
     
    #define ETH_MACFFR_SAF_Msk   (0x1UL << ETH_MACFFR_SAF_Pos)
     
    #define ETH_MACFFR_SAF   ETH_MACFFR_SAF_Msk /* Source address filter enable */
     
    #define ETH_MACFFR_SAIF_Pos   (8U)
     
    #define ETH_MACFFR_SAIF_Msk   (0x1UL << ETH_MACFFR_SAIF_Pos)
     
    #define ETH_MACFFR_SAIF   ETH_MACFFR_SAIF_Msk /* SA inverse filtering */
     
    #define ETH_MACFFR_PCF_Pos   (6U)
     
    #define ETH_MACFFR_PCF_Msk   (0x3UL << ETH_MACFFR_PCF_Pos)
     
    #define ETH_MACFFR_PCF   ETH_MACFFR_PCF_Msk /* Pass control frames: 3 cases */
     
    #define ETH_MACFFR_PCF_BlockAll_Pos   (6U)
     
    #define ETH_MACFFR_PCF_BlockAll_Msk   (0x1UL << ETH_MACFFR_PCF_BlockAll_Pos)
     
    #define ETH_MACFFR_PCF_BlockAll   ETH_MACFFR_PCF_BlockAll_Msk /* MAC filters all control frames from reaching the application */
     
    #define ETH_MACFFR_PCF_ForwardAll_Pos   (7U)
     
    #define ETH_MACFFR_PCF_ForwardAll_Msk   (0x1UL << ETH_MACFFR_PCF_ForwardAll_Pos)
     
    #define ETH_MACFFR_PCF_ForwardAll   ETH_MACFFR_PCF_ForwardAll_Msk /* MAC forwards all control frames to application even if they fail the Address Filter */
     
    #define ETH_MACFFR_PCF_ForwardPassedAddrFilter_Pos   (6U)
     
    #define ETH_MACFFR_PCF_ForwardPassedAddrFilter_Msk   (0x3UL << ETH_MACFFR_PCF_ForwardPassedAddrFilter_Pos)
     
    #define ETH_MACFFR_PCF_ForwardPassedAddrFilter   ETH_MACFFR_PCF_ForwardPassedAddrFilter_Msk /* MAC forwards control frames that pass the Address Filter. */
     
    #define ETH_MACFFR_BFD_Pos   (5U)
     
    #define ETH_MACFFR_BFD_Msk   (0x1UL << ETH_MACFFR_BFD_Pos)
     
    #define ETH_MACFFR_BFD   ETH_MACFFR_BFD_Msk /* Broadcast frame disable */
     
    #define ETH_MACFFR_PAM_Pos   (4U)
     
    #define ETH_MACFFR_PAM_Msk   (0x1UL << ETH_MACFFR_PAM_Pos)
     
    #define ETH_MACFFR_PAM   ETH_MACFFR_PAM_Msk /* Pass all mutlicast */
     
    #define ETH_MACFFR_DAIF_Pos   (3U)
     
    #define ETH_MACFFR_DAIF_Msk   (0x1UL << ETH_MACFFR_DAIF_Pos)
     
    #define ETH_MACFFR_DAIF   ETH_MACFFR_DAIF_Msk /* DA Inverse filtering */
     
    #define ETH_MACFFR_HM_Pos   (2U)
     
    #define ETH_MACFFR_HM_Msk   (0x1UL << ETH_MACFFR_HM_Pos)
     
    #define ETH_MACFFR_HM   ETH_MACFFR_HM_Msk /* Hash multicast */
     
    #define ETH_MACFFR_HU_Pos   (1U)
     
    #define ETH_MACFFR_HU_Msk   (0x1UL << ETH_MACFFR_HU_Pos)
     
    #define ETH_MACFFR_HU   ETH_MACFFR_HU_Msk /* Hash unicast */
     
    #define ETH_MACFFR_PM_Pos   (0U)
     
    #define ETH_MACFFR_PM_Msk   (0x1UL << ETH_MACFFR_PM_Pos)
     
    #define ETH_MACFFR_PM   ETH_MACFFR_PM_Msk /* Promiscuous mode */
     
    #define ETH_MACHTHR_HTH_Pos   (0U)
     
    #define ETH_MACHTHR_HTH_Msk   (0xFFFFFFFFUL << ETH_MACHTHR_HTH_Pos)
     
    #define ETH_MACHTHR_HTH   ETH_MACHTHR_HTH_Msk /* Hash table high */
     
    #define ETH_MACHTLR_HTL_Pos   (0U)
     
    #define ETH_MACHTLR_HTL_Msk   (0xFFFFFFFFUL << ETH_MACHTLR_HTL_Pos)
     
    #define ETH_MACHTLR_HTL   ETH_MACHTLR_HTL_Msk /* Hash table low */
     
    #define ETH_MACMIIAR_PA_Pos   (11U)
     
    #define ETH_MACMIIAR_PA_Msk   (0x1FUL << ETH_MACMIIAR_PA_Pos)
     
    #define ETH_MACMIIAR_PA   ETH_MACMIIAR_PA_Msk /* Physical layer address */
     
    #define ETH_MACMIIAR_MR_Pos   (6U)
     
    #define ETH_MACMIIAR_MR_Msk   (0x1FUL << ETH_MACMIIAR_MR_Pos)
     
    #define ETH_MACMIIAR_MR   ETH_MACMIIAR_MR_Msk /* MII register in the selected PHY */
     
    #define ETH_MACMIIAR_CR_Pos   (2U)
     
    #define ETH_MACMIIAR_CR_Msk   (0x7UL << ETH_MACMIIAR_CR_Pos)
     
    #define ETH_MACMIIAR_CR   ETH_MACMIIAR_CR_Msk /* CR clock range: 6 cases */
     
    #define ETH_MACMIIAR_CR_Div42   0x00000000U /* HCLK:60-100 MHz; MDC clock= HCLK/42 */
     
    #define ETH_MACMIIAR_CR_Div62_Pos   (2U)
     
    #define ETH_MACMIIAR_CR_Div62_Msk   (0x1UL << ETH_MACMIIAR_CR_Div62_Pos)
     
    #define ETH_MACMIIAR_CR_Div62   ETH_MACMIIAR_CR_Div62_Msk /* HCLK:100-150 MHz; MDC clock= HCLK/62 */
     
    #define ETH_MACMIIAR_CR_Div16_Pos   (3U)
     
    #define ETH_MACMIIAR_CR_Div16_Msk   (0x1UL << ETH_MACMIIAR_CR_Div16_Pos)
     
    #define ETH_MACMIIAR_CR_Div16   ETH_MACMIIAR_CR_Div16_Msk /* HCLK:20-35 MHz; MDC clock= HCLK/16 */
     
    #define ETH_MACMIIAR_CR_Div26_Pos   (2U)
     
    #define ETH_MACMIIAR_CR_Div26_Msk   (0x3UL << ETH_MACMIIAR_CR_Div26_Pos)
     
    #define ETH_MACMIIAR_CR_Div26   ETH_MACMIIAR_CR_Div26_Msk /* HCLK:35-60 MHz; MDC clock= HCLK/26 */
     
    #define ETH_MACMIIAR_CR_Div102_Pos   (4U)
     
    #define ETH_MACMIIAR_CR_Div102_Msk   (0x1UL << ETH_MACMIIAR_CR_Div102_Pos)
     
    #define ETH_MACMIIAR_CR_Div102   ETH_MACMIIAR_CR_Div102_Msk /* HCLK:150-168 MHz; MDC clock= HCLK/102 */
     
    #define ETH_MACMIIAR_MW_Pos   (1U)
     
    #define ETH_MACMIIAR_MW_Msk   (0x1UL << ETH_MACMIIAR_MW_Pos)
     
    #define ETH_MACMIIAR_MW   ETH_MACMIIAR_MW_Msk /* MII write */
     
    #define ETH_MACMIIAR_MB_Pos   (0U)
     
    #define ETH_MACMIIAR_MB_Msk   (0x1UL << ETH_MACMIIAR_MB_Pos)
     
    #define ETH_MACMIIAR_MB   ETH_MACMIIAR_MB_Msk /* MII busy */
     
    #define ETH_MACMIIDR_MD_Pos   (0U)
     
    #define ETH_MACMIIDR_MD_Msk   (0xFFFFUL << ETH_MACMIIDR_MD_Pos)
     
    #define ETH_MACMIIDR_MD   ETH_MACMIIDR_MD_Msk /* MII data: read/write data from/to PHY */
     
    #define ETH_MACFCR_PT_Pos   (16U)
     
    #define ETH_MACFCR_PT_Msk   (0xFFFFUL << ETH_MACFCR_PT_Pos)
     
    #define ETH_MACFCR_PT   ETH_MACFCR_PT_Msk /* Pause time */
     
    #define ETH_MACFCR_ZQPD_Pos   (7U)
     
    #define ETH_MACFCR_ZQPD_Msk   (0x1UL << ETH_MACFCR_ZQPD_Pos)
     
    #define ETH_MACFCR_ZQPD   ETH_MACFCR_ZQPD_Msk /* Zero-quanta pause disable */
     
    #define ETH_MACFCR_PLT_Pos   (4U)
     
    #define ETH_MACFCR_PLT_Msk   (0x3UL << ETH_MACFCR_PLT_Pos)
     
    #define ETH_MACFCR_PLT   ETH_MACFCR_PLT_Msk /* Pause low threshold: 4 cases */
     
    #define ETH_MACFCR_PLT_Minus4   0x00000000U /* Pause time minus 4 slot times */
     
    #define ETH_MACFCR_PLT_Minus28_Pos   (4U)
     
    #define ETH_MACFCR_PLT_Minus28_Msk   (0x1UL << ETH_MACFCR_PLT_Minus28_Pos)
     
    #define ETH_MACFCR_PLT_Minus28   ETH_MACFCR_PLT_Minus28_Msk /* Pause time minus 28 slot times */
     
    #define ETH_MACFCR_PLT_Minus144_Pos   (5U)
     
    #define ETH_MACFCR_PLT_Minus144_Msk   (0x1UL << ETH_MACFCR_PLT_Minus144_Pos)
     
    #define ETH_MACFCR_PLT_Minus144   ETH_MACFCR_PLT_Minus144_Msk /* Pause time minus 144 slot times */
     
    #define ETH_MACFCR_PLT_Minus256_Pos   (4U)
     
    #define ETH_MACFCR_PLT_Minus256_Msk   (0x3UL << ETH_MACFCR_PLT_Minus256_Pos)
     
    #define ETH_MACFCR_PLT_Minus256   ETH_MACFCR_PLT_Minus256_Msk /* Pause time minus 256 slot times */
     
    #define ETH_MACFCR_UPFD_Pos   (3U)
     
    #define ETH_MACFCR_UPFD_Msk   (0x1UL << ETH_MACFCR_UPFD_Pos)
     
    #define ETH_MACFCR_UPFD   ETH_MACFCR_UPFD_Msk /* Unicast pause frame detect */
     
    #define ETH_MACFCR_RFCE_Pos   (2U)
     
    #define ETH_MACFCR_RFCE_Msk   (0x1UL << ETH_MACFCR_RFCE_Pos)
     
    #define ETH_MACFCR_RFCE   ETH_MACFCR_RFCE_Msk /* Receive flow control enable */
     
    #define ETH_MACFCR_TFCE_Pos   (1U)
     
    #define ETH_MACFCR_TFCE_Msk   (0x1UL << ETH_MACFCR_TFCE_Pos)
     
    #define ETH_MACFCR_TFCE   ETH_MACFCR_TFCE_Msk /* Transmit flow control enable */
     
    #define ETH_MACFCR_FCBBPA_Pos   (0U)
     
    #define ETH_MACFCR_FCBBPA_Msk   (0x1UL << ETH_MACFCR_FCBBPA_Pos)
     
    #define ETH_MACFCR_FCBBPA   ETH_MACFCR_FCBBPA_Msk /* Flow control busy/backpressure activate */
     
    #define ETH_MACVLANTR_VLANTC_Pos   (16U)
     
    #define ETH_MACVLANTR_VLANTC_Msk   (0x1UL << ETH_MACVLANTR_VLANTC_Pos)
     
    #define ETH_MACVLANTR_VLANTC   ETH_MACVLANTR_VLANTC_Msk /* 12-bit VLAN tag comparison */
     
    #define ETH_MACVLANTR_VLANTI_Pos   (0U)
     
    #define ETH_MACVLANTR_VLANTI_Msk   (0xFFFFUL << ETH_MACVLANTR_VLANTI_Pos)
     
    #define ETH_MACVLANTR_VLANTI   ETH_MACVLANTR_VLANTI_Msk /* VLAN tag identifier (for receive frames) */
     
    #define ETH_MACRWUFFR_D_Pos   (0U)
     
    #define ETH_MACRWUFFR_D_Msk   (0xFFFFFFFFUL << ETH_MACRWUFFR_D_Pos)
     
    #define ETH_MACRWUFFR_D   ETH_MACRWUFFR_D_Msk /* Wake-up frame filter register data */
     
    #define ETH_MACPMTCSR_WFFRPR_Pos   (31U)
     
    #define ETH_MACPMTCSR_WFFRPR_Msk   (0x1UL << ETH_MACPMTCSR_WFFRPR_Pos)
     
    #define ETH_MACPMTCSR_WFFRPR   ETH_MACPMTCSR_WFFRPR_Msk /* Wake-Up Frame Filter Register Pointer Reset */
     
    #define ETH_MACPMTCSR_GU_Pos   (9U)
     
    #define ETH_MACPMTCSR_GU_Msk   (0x1UL << ETH_MACPMTCSR_GU_Pos)
     
    #define ETH_MACPMTCSR_GU   ETH_MACPMTCSR_GU_Msk /* Global Unicast */
     
    #define ETH_MACPMTCSR_WFR_Pos   (6U)
     
    #define ETH_MACPMTCSR_WFR_Msk   (0x1UL << ETH_MACPMTCSR_WFR_Pos)
     
    #define ETH_MACPMTCSR_WFR   ETH_MACPMTCSR_WFR_Msk /* Wake-Up Frame Received */
     
    #define ETH_MACPMTCSR_MPR_Pos   (5U)
     
    #define ETH_MACPMTCSR_MPR_Msk   (0x1UL << ETH_MACPMTCSR_MPR_Pos)
     
    #define ETH_MACPMTCSR_MPR   ETH_MACPMTCSR_MPR_Msk /* Magic Packet Received */
     
    #define ETH_MACPMTCSR_WFE_Pos   (2U)
     
    #define ETH_MACPMTCSR_WFE_Msk   (0x1UL << ETH_MACPMTCSR_WFE_Pos)
     
    #define ETH_MACPMTCSR_WFE   ETH_MACPMTCSR_WFE_Msk /* Wake-Up Frame Enable */
     
    #define ETH_MACPMTCSR_MPE_Pos   (1U)
     
    #define ETH_MACPMTCSR_MPE_Msk   (0x1UL << ETH_MACPMTCSR_MPE_Pos)
     
    #define ETH_MACPMTCSR_MPE   ETH_MACPMTCSR_MPE_Msk /* Magic Packet Enable */
     
    #define ETH_MACPMTCSR_PD_Pos   (0U)
     
    #define ETH_MACPMTCSR_PD_Msk   (0x1UL << ETH_MACPMTCSR_PD_Pos)
     
    #define ETH_MACPMTCSR_PD   ETH_MACPMTCSR_PD_Msk /* Power Down */
     
    #define ETH_MACDBGR_TFF_Pos   (25U)
     
    #define ETH_MACDBGR_TFF_Msk   (0x1UL << ETH_MACDBGR_TFF_Pos)
     
    #define ETH_MACDBGR_TFF   ETH_MACDBGR_TFF_Msk /* Tx FIFO full */
     
    #define ETH_MACDBGR_TFNE_Pos   (24U)
     
    #define ETH_MACDBGR_TFNE_Msk   (0x1UL << ETH_MACDBGR_TFNE_Pos)
     
    #define ETH_MACDBGR_TFNE   ETH_MACDBGR_TFNE_Msk /* Tx FIFO not empty */
     
    #define ETH_MACDBGR_TFWA_Pos   (22U)
     
    #define ETH_MACDBGR_TFWA_Msk   (0x1UL << ETH_MACDBGR_TFWA_Pos)
     
    #define ETH_MACDBGR_TFWA   ETH_MACDBGR_TFWA_Msk /* Tx FIFO write active */
     
    #define ETH_MACDBGR_TFRS_Pos   (20U)
     
    #define ETH_MACDBGR_TFRS_Msk   (0x3UL << ETH_MACDBGR_TFRS_Pos)
     
    #define ETH_MACDBGR_TFRS   ETH_MACDBGR_TFRS_Msk /* Tx FIFO read status mask */
     
    #define ETH_MACDBGR_TFRS_WRITING_Pos   (20U)
     
    #define ETH_MACDBGR_TFRS_WRITING_Msk   (0x3UL << ETH_MACDBGR_TFRS_WRITING_Pos)
     
    #define ETH_MACDBGR_TFRS_WRITING   ETH_MACDBGR_TFRS_WRITING_Msk /* Writing the received TxStatus or flushing the TxFIFO */
     
    #define ETH_MACDBGR_TFRS_WAITING_Pos   (21U)
     
    #define ETH_MACDBGR_TFRS_WAITING_Msk   (0x1UL << ETH_MACDBGR_TFRS_WAITING_Pos)
     
    #define ETH_MACDBGR_TFRS_WAITING   ETH_MACDBGR_TFRS_WAITING_Msk /* Waiting for TxStatus from MAC transmitter */
     
    #define ETH_MACDBGR_TFRS_READ_Pos   (20U)
     
    #define ETH_MACDBGR_TFRS_READ_Msk   (0x1UL << ETH_MACDBGR_TFRS_READ_Pos)
     
    #define ETH_MACDBGR_TFRS_READ   ETH_MACDBGR_TFRS_READ_Msk /* Read state (transferring data to the MAC transmitter) */
     
    #define ETH_MACDBGR_TFRS_IDLE   0x00000000U /* Idle state */
     
    #define ETH_MACDBGR_MTP_Pos   (19U)
     
    #define ETH_MACDBGR_MTP_Msk   (0x1UL << ETH_MACDBGR_MTP_Pos)
     
    #define ETH_MACDBGR_MTP   ETH_MACDBGR_MTP_Msk /* MAC transmitter in pause */
     
    #define ETH_MACDBGR_MTFCS_Pos   (17U)
     
    #define ETH_MACDBGR_MTFCS_Msk   (0x3UL << ETH_MACDBGR_MTFCS_Pos)
     
    #define ETH_MACDBGR_MTFCS   ETH_MACDBGR_MTFCS_Msk /* MAC transmit frame controller status mask */
     
    #define ETH_MACDBGR_MTFCS_TRANSFERRING_Pos   (17U)
     
    #define ETH_MACDBGR_MTFCS_TRANSFERRING_Msk   (0x3UL << ETH_MACDBGR_MTFCS_TRANSFERRING_Pos)
     
    #define ETH_MACDBGR_MTFCS_TRANSFERRING   ETH_MACDBGR_MTFCS_TRANSFERRING_Msk /* Transferring input frame for transmission */
     
    #define ETH_MACDBGR_MTFCS_GENERATINGPCF_Pos   (18U)
     
    #define ETH_MACDBGR_MTFCS_GENERATINGPCF_Msk   (0x1UL << ETH_MACDBGR_MTFCS_GENERATINGPCF_Pos)
     
    #define ETH_MACDBGR_MTFCS_GENERATINGPCF   ETH_MACDBGR_MTFCS_GENERATINGPCF_Msk /* Generating and transmitting a Pause control frame (in full duplex mode) */
     
    #define ETH_MACDBGR_MTFCS_WAITING_Pos   (17U)
     
    #define ETH_MACDBGR_MTFCS_WAITING_Msk   (0x1UL << ETH_MACDBGR_MTFCS_WAITING_Pos)
     
    #define ETH_MACDBGR_MTFCS_WAITING   ETH_MACDBGR_MTFCS_WAITING_Msk /* Waiting for Status of previous frame or IFG/backoff period to be over */
     
    #define ETH_MACDBGR_MTFCS_IDLE   0x00000000U /* Idle */
     
    #define ETH_MACDBGR_MMTEA_Pos   (16U)
     
    #define ETH_MACDBGR_MMTEA_Msk   (0x1UL << ETH_MACDBGR_MMTEA_Pos)
     
    #define ETH_MACDBGR_MMTEA   ETH_MACDBGR_MMTEA_Msk /* MAC MII transmit engine active */
     
    #define ETH_MACDBGR_RFFL_Pos   (8U)
     
    #define ETH_MACDBGR_RFFL_Msk   (0x3UL << ETH_MACDBGR_RFFL_Pos)
     
    #define ETH_MACDBGR_RFFL   ETH_MACDBGR_RFFL_Msk /* Rx FIFO fill level mask */
     
    #define ETH_MACDBGR_RFFL_FULL_Pos   (8U)
     
    #define ETH_MACDBGR_RFFL_FULL_Msk   (0x3UL << ETH_MACDBGR_RFFL_FULL_Pos)
     
    #define ETH_MACDBGR_RFFL_FULL   ETH_MACDBGR_RFFL_FULL_Msk /* RxFIFO full */
     
    #define ETH_MACDBGR_RFFL_ABOVEFCT_Pos   (9U)
     
    #define ETH_MACDBGR_RFFL_ABOVEFCT_Msk   (0x1UL << ETH_MACDBGR_RFFL_ABOVEFCT_Pos)
     
    #define ETH_MACDBGR_RFFL_ABOVEFCT   ETH_MACDBGR_RFFL_ABOVEFCT_Msk /* RxFIFO fill-level above flow-control activate threshold */
     
    #define ETH_MACDBGR_RFFL_BELOWFCT_Pos   (8U)
     
    #define ETH_MACDBGR_RFFL_BELOWFCT_Msk   (0x1UL << ETH_MACDBGR_RFFL_BELOWFCT_Pos)
     
    #define ETH_MACDBGR_RFFL_BELOWFCT   ETH_MACDBGR_RFFL_BELOWFCT_Msk /* RxFIFO fill-level below flow-control de-activate threshold */
     
    #define ETH_MACDBGR_RFFL_EMPTY   0x00000000U /* RxFIFO empty */
     
    #define ETH_MACDBGR_RFRCS_Pos   (5U)
     
    #define ETH_MACDBGR_RFRCS_Msk   (0x3UL << ETH_MACDBGR_RFRCS_Pos)
     
    #define ETH_MACDBGR_RFRCS   ETH_MACDBGR_RFRCS_Msk /* Rx FIFO read controller status mask */
     
    #define ETH_MACDBGR_RFRCS_FLUSHING_Pos   (5U)
     
    #define ETH_MACDBGR_RFRCS_FLUSHING_Msk   (0x3UL << ETH_MACDBGR_RFRCS_FLUSHING_Pos)
     
    #define ETH_MACDBGR_RFRCS_FLUSHING   ETH_MACDBGR_RFRCS_FLUSHING_Msk /* Flushing the frame data and status */
     
    #define ETH_MACDBGR_RFRCS_STATUSREADING_Pos   (6U)
     
    #define ETH_MACDBGR_RFRCS_STATUSREADING_Msk   (0x1UL << ETH_MACDBGR_RFRCS_STATUSREADING_Pos)
     
    #define ETH_MACDBGR_RFRCS_STATUSREADING   ETH_MACDBGR_RFRCS_STATUSREADING_Msk /* Reading frame status (or time-stamp) */
     
    #define ETH_MACDBGR_RFRCS_DATAREADING_Pos   (5U)
     
    #define ETH_MACDBGR_RFRCS_DATAREADING_Msk   (0x1UL << ETH_MACDBGR_RFRCS_DATAREADING_Pos)
     
    #define ETH_MACDBGR_RFRCS_DATAREADING   ETH_MACDBGR_RFRCS_DATAREADING_Msk /* Reading frame data */
     
    #define ETH_MACDBGR_RFRCS_IDLE   0x00000000U /* IDLE state */
     
    #define ETH_MACDBGR_RFWRA_Pos   (4U)
     
    #define ETH_MACDBGR_RFWRA_Msk   (0x1UL << ETH_MACDBGR_RFWRA_Pos)
     
    #define ETH_MACDBGR_RFWRA   ETH_MACDBGR_RFWRA_Msk /* Rx FIFO write controller active */
     
    #define ETH_MACDBGR_MSFRWCS_Pos   (1U)
     
    #define ETH_MACDBGR_MSFRWCS_Msk   (0x3UL << ETH_MACDBGR_MSFRWCS_Pos)
     
    #define ETH_MACDBGR_MSFRWCS   ETH_MACDBGR_MSFRWCS_Msk /* MAC small FIFO read / write controllers status mask */
     
    #define ETH_MACDBGR_MSFRWCS_1   (0x2UL << ETH_MACDBGR_MSFRWCS_Pos)
     
    #define ETH_MACDBGR_MSFRWCS_0   (0x1UL << ETH_MACDBGR_MSFRWCS_Pos)
     
    #define ETH_MACDBGR_MMRPEA_Pos   (0U)
     
    #define ETH_MACDBGR_MMRPEA_Msk   (0x1UL << ETH_MACDBGR_MMRPEA_Pos)
     
    #define ETH_MACDBGR_MMRPEA   ETH_MACDBGR_MMRPEA_Msk /* MAC MII receive protocol engine active */
     
    #define ETH_MACSR_TSTS_Pos   (9U)
     
    #define ETH_MACSR_TSTS_Msk   (0x1UL << ETH_MACSR_TSTS_Pos)
     
    #define ETH_MACSR_TSTS   ETH_MACSR_TSTS_Msk /* Time stamp trigger status */
     
    #define ETH_MACSR_MMCTS_Pos   (6U)
     
    #define ETH_MACSR_MMCTS_Msk   (0x1UL << ETH_MACSR_MMCTS_Pos)
     
    #define ETH_MACSR_MMCTS   ETH_MACSR_MMCTS_Msk /* MMC transmit status */
     
    #define ETH_MACSR_MMMCRS_Pos   (5U)
     
    #define ETH_MACSR_MMMCRS_Msk   (0x1UL << ETH_MACSR_MMMCRS_Pos)
     
    #define ETH_MACSR_MMMCRS   ETH_MACSR_MMMCRS_Msk /* MMC receive status */
     
    #define ETH_MACSR_MMCS_Pos   (4U)
     
    #define ETH_MACSR_MMCS_Msk   (0x1UL << ETH_MACSR_MMCS_Pos)
     
    #define ETH_MACSR_MMCS   ETH_MACSR_MMCS_Msk /* MMC status */
     
    #define ETH_MACSR_PMTS_Pos   (3U)
     
    #define ETH_MACSR_PMTS_Msk   (0x1UL << ETH_MACSR_PMTS_Pos)
     
    #define ETH_MACSR_PMTS   ETH_MACSR_PMTS_Msk /* PMT status */
     
    #define ETH_MACIMR_TSTIM_Pos   (9U)
     
    #define ETH_MACIMR_TSTIM_Msk   (0x1UL << ETH_MACIMR_TSTIM_Pos)
     
    #define ETH_MACIMR_TSTIM   ETH_MACIMR_TSTIM_Msk /* Time stamp trigger interrupt mask */
     
    #define ETH_MACIMR_PMTIM_Pos   (3U)
     
    #define ETH_MACIMR_PMTIM_Msk   (0x1UL << ETH_MACIMR_PMTIM_Pos)
     
    #define ETH_MACIMR_PMTIM   ETH_MACIMR_PMTIM_Msk /* PMT interrupt mask */
     
    #define ETH_MACA0HR_MACA0H_Pos   (0U)
     
    #define ETH_MACA0HR_MACA0H_Msk   (0xFFFFUL << ETH_MACA0HR_MACA0H_Pos)
     
    #define ETH_MACA0HR_MACA0H   ETH_MACA0HR_MACA0H_Msk /* MAC address0 high */
     
    #define ETH_MACA0LR_MACA0L_Pos   (0U)
     
    #define ETH_MACA0LR_MACA0L_Msk   (0xFFFFFFFFUL << ETH_MACA0LR_MACA0L_Pos)
     
    #define ETH_MACA0LR_MACA0L   ETH_MACA0LR_MACA0L_Msk /* MAC address0 low */
     
    #define ETH_MACA1HR_AE_Pos   (31U)
     
    #define ETH_MACA1HR_AE_Msk   (0x1UL << ETH_MACA1HR_AE_Pos)
     
    #define ETH_MACA1HR_AE   ETH_MACA1HR_AE_Msk /* Address enable */
     
    #define ETH_MACA1HR_SA_Pos   (30U)
     
    #define ETH_MACA1HR_SA_Msk   (0x1UL << ETH_MACA1HR_SA_Pos)
     
    #define ETH_MACA1HR_SA   ETH_MACA1HR_SA_Msk /* Source address */
     
    #define ETH_MACA1HR_MBC_Pos   (24U)
     
    #define ETH_MACA1HR_MBC_Msk   (0x3FUL << ETH_MACA1HR_MBC_Pos)
     
    #define ETH_MACA1HR_MBC   ETH_MACA1HR_MBC_Msk /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
     
    #define ETH_MACA1HR_MBC_HBits15_8   0x20000000U /* Mask MAC Address high reg bits [15:8] */
     
    #define ETH_MACA1HR_MBC_HBits7_0   0x10000000U /* Mask MAC Address high reg bits [7:0] */
     
    #define ETH_MACA1HR_MBC_LBits31_24   0x08000000U /* Mask MAC Address low reg bits [31:24] */
     
    #define ETH_MACA1HR_MBC_LBits23_16   0x04000000U /* Mask MAC Address low reg bits [23:16] */
     
    #define ETH_MACA1HR_MBC_LBits15_8   0x02000000U /* Mask MAC Address low reg bits [15:8] */
     
    #define ETH_MACA1HR_MBC_LBits7_0   0x01000000U /* Mask MAC Address low reg bits [7:0] */
     
    #define ETH_MACA1HR_MACA1H_Pos   (0U)
     
    #define ETH_MACA1HR_MACA1H_Msk   (0xFFFFUL << ETH_MACA1HR_MACA1H_Pos)
     
    #define ETH_MACA1HR_MACA1H   ETH_MACA1HR_MACA1H_Msk /* MAC address1 high */
     
    #define ETH_MACA1LR_MACA1L_Pos   (0U)
     
    #define ETH_MACA1LR_MACA1L_Msk   (0xFFFFFFFFUL << ETH_MACA1LR_MACA1L_Pos)
     
    #define ETH_MACA1LR_MACA1L   ETH_MACA1LR_MACA1L_Msk /* MAC address1 low */
     
    #define ETH_MACA2HR_AE_Pos   (31U)
     
    #define ETH_MACA2HR_AE_Msk   (0x1UL << ETH_MACA2HR_AE_Pos)
     
    #define ETH_MACA2HR_AE   ETH_MACA2HR_AE_Msk /* Address enable */
     
    #define ETH_MACA2HR_SA_Pos   (30U)
     
    #define ETH_MACA2HR_SA_Msk   (0x1UL << ETH_MACA2HR_SA_Pos)
     
    #define ETH_MACA2HR_SA   ETH_MACA2HR_SA_Msk /* Source address */
     
    #define ETH_MACA2HR_MBC_Pos   (24U)
     
    #define ETH_MACA2HR_MBC_Msk   (0x3FUL << ETH_MACA2HR_MBC_Pos)
     
    #define ETH_MACA2HR_MBC   ETH_MACA2HR_MBC_Msk /* Mask byte control */
     
    #define ETH_MACA2HR_MBC_HBits15_8   0x20000000U /* Mask MAC Address high reg bits [15:8] */
     
    #define ETH_MACA2HR_MBC_HBits7_0   0x10000000U /* Mask MAC Address high reg bits [7:0] */
     
    #define ETH_MACA2HR_MBC_LBits31_24   0x08000000U /* Mask MAC Address low reg bits [31:24] */
     
    #define ETH_MACA2HR_MBC_LBits23_16   0x04000000U /* Mask MAC Address low reg bits [23:16] */
     
    #define ETH_MACA2HR_MBC_LBits15_8   0x02000000U /* Mask MAC Address low reg bits [15:8] */
     
    #define ETH_MACA2HR_MBC_LBits7_0   0x01000000U /* Mask MAC Address low reg bits [70] */
     
    #define ETH_MACA2HR_MACA2H_Pos   (0U)
     
    #define ETH_MACA2HR_MACA2H_Msk   (0xFFFFUL << ETH_MACA2HR_MACA2H_Pos)
     
    #define ETH_MACA2HR_MACA2H   ETH_MACA2HR_MACA2H_Msk /* MAC address1 high */
     
    #define ETH_MACA2LR_MACA2L_Pos   (0U)
     
    #define ETH_MACA2LR_MACA2L_Msk   (0xFFFFFFFFUL << ETH_MACA2LR_MACA2L_Pos)
     
    #define ETH_MACA2LR_MACA2L   ETH_MACA2LR_MACA2L_Msk /* MAC address2 low */
     
    #define ETH_MACA3HR_AE_Pos   (31U)
     
    #define ETH_MACA3HR_AE_Msk   (0x1UL << ETH_MACA3HR_AE_Pos)
     
    #define ETH_MACA3HR_AE   ETH_MACA3HR_AE_Msk /* Address enable */
     
    #define ETH_MACA3HR_SA_Pos   (30U)
     
    #define ETH_MACA3HR_SA_Msk   (0x1UL << ETH_MACA3HR_SA_Pos)
     
    #define ETH_MACA3HR_SA   ETH_MACA3HR_SA_Msk /* Source address */
     
    #define ETH_MACA3HR_MBC_Pos   (24U)
     
    #define ETH_MACA3HR_MBC_Msk   (0x3FUL << ETH_MACA3HR_MBC_Pos)
     
    #define ETH_MACA3HR_MBC   ETH_MACA3HR_MBC_Msk /* Mask byte control */
     
    #define ETH_MACA3HR_MBC_HBits15_8   0x20000000U /* Mask MAC Address high reg bits [15:8] */
     
    #define ETH_MACA3HR_MBC_HBits7_0   0x10000000U /* Mask MAC Address high reg bits [7:0] */
     
    #define ETH_MACA3HR_MBC_LBits31_24   0x08000000U /* Mask MAC Address low reg bits [31:24] */
     
    #define ETH_MACA3HR_MBC_LBits23_16   0x04000000U /* Mask MAC Address low reg bits [23:16] */
     
    #define ETH_MACA3HR_MBC_LBits15_8   0x02000000U /* Mask MAC Address low reg bits [15:8] */
     
    #define ETH_MACA3HR_MBC_LBits7_0   0x01000000U /* Mask MAC Address low reg bits [70] */
     
    #define ETH_MACA3HR_MACA3H_Pos   (0U)
     
    #define ETH_MACA3HR_MACA3H_Msk   (0xFFFFUL << ETH_MACA3HR_MACA3H_Pos)
     
    #define ETH_MACA3HR_MACA3H   ETH_MACA3HR_MACA3H_Msk /* MAC address3 high */
     
    #define ETH_MACA3LR_MACA3L_Pos   (0U)
     
    #define ETH_MACA3LR_MACA3L_Msk   (0xFFFFFFFFUL << ETH_MACA3LR_MACA3L_Pos)
     
    #define ETH_MACA3LR_MACA3L   ETH_MACA3LR_MACA3L_Msk /* MAC address3 low */
     
    #define ETH_MMCCR_MCFHP_Pos   (5U)
     
    #define ETH_MMCCR_MCFHP_Msk   (0x1UL << ETH_MMCCR_MCFHP_Pos)
     
    #define ETH_MMCCR_MCFHP   ETH_MMCCR_MCFHP_Msk /* MMC counter Full-Half preset */
     
    #define ETH_MMCCR_MCP_Pos   (4U)
     
    #define ETH_MMCCR_MCP_Msk   (0x1UL << ETH_MMCCR_MCP_Pos)
     
    #define ETH_MMCCR_MCP   ETH_MMCCR_MCP_Msk /* MMC counter preset */
     
    #define ETH_MMCCR_MCF_Pos   (3U)
     
    #define ETH_MMCCR_MCF_Msk   (0x1UL << ETH_MMCCR_MCF_Pos)
     
    #define ETH_MMCCR_MCF   ETH_MMCCR_MCF_Msk /* MMC Counter Freeze */
     
    #define ETH_MMCCR_ROR_Pos   (2U)
     
    #define ETH_MMCCR_ROR_Msk   (0x1UL << ETH_MMCCR_ROR_Pos)
     
    #define ETH_MMCCR_ROR   ETH_MMCCR_ROR_Msk /* Reset on Read */
     
    #define ETH_MMCCR_CSR_Pos   (1U)
     
    #define ETH_MMCCR_CSR_Msk   (0x1UL << ETH_MMCCR_CSR_Pos)
     
    #define ETH_MMCCR_CSR   ETH_MMCCR_CSR_Msk /* Counter Stop Rollover */
     
    #define ETH_MMCCR_CR_Pos   (0U)
     
    #define ETH_MMCCR_CR_Msk   (0x1UL << ETH_MMCCR_CR_Pos)
     
    #define ETH_MMCCR_CR   ETH_MMCCR_CR_Msk /* Counters Reset */
     
    #define ETH_MMCRIR_RGUFS_Pos   (17U)
     
    #define ETH_MMCRIR_RGUFS_Msk   (0x1UL << ETH_MMCRIR_RGUFS_Pos)
     
    #define ETH_MMCRIR_RGUFS   ETH_MMCRIR_RGUFS_Msk /* Set when Rx good unicast frames counter reaches half the maximum value */
     
    #define ETH_MMCRIR_RFAES_Pos   (6U)
     
    #define ETH_MMCRIR_RFAES_Msk   (0x1UL << ETH_MMCRIR_RFAES_Pos)
     
    #define ETH_MMCRIR_RFAES   ETH_MMCRIR_RFAES_Msk /* Set when Rx alignment error counter reaches half the maximum value */
     
    #define ETH_MMCRIR_RFCES_Pos   (5U)
     
    #define ETH_MMCRIR_RFCES_Msk   (0x1UL << ETH_MMCRIR_RFCES_Pos)
     
    #define ETH_MMCRIR_RFCES   ETH_MMCRIR_RFCES_Msk /* Set when Rx crc error counter reaches half the maximum value */
     
    #define ETH_MMCTIR_TGFS_Pos   (21U)
     
    #define ETH_MMCTIR_TGFS_Msk   (0x1UL << ETH_MMCTIR_TGFS_Pos)
     
    #define ETH_MMCTIR_TGFS   ETH_MMCTIR_TGFS_Msk /* Set when Tx good frame count counter reaches half the maximum value */
     
    #define ETH_MMCTIR_TGFMSCS_Pos   (15U)
     
    #define ETH_MMCTIR_TGFMSCS_Msk   (0x1UL << ETH_MMCTIR_TGFMSCS_Pos)
     
    #define ETH_MMCTIR_TGFMSCS   ETH_MMCTIR_TGFMSCS_Msk /* Set when Tx good multi col counter reaches half the maximum value */
     
    #define ETH_MMCTIR_TGFSCS_Pos   (14U)
     
    #define ETH_MMCTIR_TGFSCS_Msk   (0x1UL << ETH_MMCTIR_TGFSCS_Pos)
     
    #define ETH_MMCTIR_TGFSCS   ETH_MMCTIR_TGFSCS_Msk /* Set when Tx good single col counter reaches half the maximum value */
     
    #define ETH_MMCRIMR_RGUFM_Pos   (17U)
     
    #define ETH_MMCRIMR_RGUFM_Msk   (0x1UL << ETH_MMCRIMR_RGUFM_Pos)
     
    #define ETH_MMCRIMR_RGUFM   ETH_MMCRIMR_RGUFM_Msk /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */
     
    #define ETH_MMCRIMR_RFAEM_Pos   (6U)
     
    #define ETH_MMCRIMR_RFAEM_Msk   (0x1UL << ETH_MMCRIMR_RFAEM_Pos)
     
    #define ETH_MMCRIMR_RFAEM   ETH_MMCRIMR_RFAEM_Msk /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */
     
    #define ETH_MMCRIMR_RFCEM_Pos   (5U)
     
    #define ETH_MMCRIMR_RFCEM_Msk   (0x1UL << ETH_MMCRIMR_RFCEM_Pos)
     
    #define ETH_MMCRIMR_RFCEM   ETH_MMCRIMR_RFCEM_Msk /* Mask the interrupt when Rx crc error counter reaches half the maximum value */
     
    #define ETH_MMCTIMR_TGFM_Pos   (21U)
     
    #define ETH_MMCTIMR_TGFM_Msk   (0x1UL << ETH_MMCTIMR_TGFM_Pos)
     
    #define ETH_MMCTIMR_TGFM   ETH_MMCTIMR_TGFM_Msk /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */
     
    #define ETH_MMCTIMR_TGFMSCM_Pos   (15U)
     
    #define ETH_MMCTIMR_TGFMSCM_Msk   (0x1UL << ETH_MMCTIMR_TGFMSCM_Pos)
     
    #define ETH_MMCTIMR_TGFMSCM   ETH_MMCTIMR_TGFMSCM_Msk /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */
     
    #define ETH_MMCTIMR_TGFSCM_Pos   (14U)
     
    #define ETH_MMCTIMR_TGFSCM_Msk   (0x1UL << ETH_MMCTIMR_TGFSCM_Pos)
     
    #define ETH_MMCTIMR_TGFSCM   ETH_MMCTIMR_TGFSCM_Msk /* Mask the interrupt when Tx good single col counter reaches half the maximum value */
     
    #define ETH_MMCTGFSCCR_TGFSCC_Pos   (0U)
     
    #define ETH_MMCTGFSCCR_TGFSCC_Msk   (0xFFFFFFFFUL << ETH_MMCTGFSCCR_TGFSCC_Pos)
     
    #define ETH_MMCTGFSCCR_TGFSCC   ETH_MMCTGFSCCR_TGFSCC_Msk /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */
     
    #define ETH_MMCTGFMSCCR_TGFMSCC_Pos   (0U)
     
    #define ETH_MMCTGFMSCCR_TGFMSCC_Msk   (0xFFFFFFFFUL << ETH_MMCTGFMSCCR_TGFMSCC_Pos)
     
    #define ETH_MMCTGFMSCCR_TGFMSCC   ETH_MMCTGFMSCCR_TGFMSCC_Msk /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */
     
    #define ETH_MMCTGFCR_TGFC_Pos   (0U)
     
    #define ETH_MMCTGFCR_TGFC_Msk   (0xFFFFFFFFUL << ETH_MMCTGFCR_TGFC_Pos)
     
    #define ETH_MMCTGFCR_TGFC   ETH_MMCTGFCR_TGFC_Msk /* Number of good frames transmitted. */
     
    #define ETH_MMCRFCECR_RFCEC_Pos   (0U)
     
    #define ETH_MMCRFCECR_RFCEC_Msk   (0xFFFFFFFFUL << ETH_MMCRFCECR_RFCEC_Pos)
     
    #define ETH_MMCRFCECR_RFCEC   ETH_MMCRFCECR_RFCEC_Msk /* Number of frames received with CRC error. */
     
    #define ETH_MMCRFAECR_RFAEC_Pos   (0U)
     
    #define ETH_MMCRFAECR_RFAEC_Msk   (0xFFFFFFFFUL << ETH_MMCRFAECR_RFAEC_Pos)
     
    #define ETH_MMCRFAECR_RFAEC   ETH_MMCRFAECR_RFAEC_Msk /* Number of frames received with alignment (dribble) error */
     
    #define ETH_MMCRGUFCR_RGUFC_Pos   (0U)
     
    #define ETH_MMCRGUFCR_RGUFC_Msk   (0xFFFFFFFFUL << ETH_MMCRGUFCR_RGUFC_Pos)
     
    #define ETH_MMCRGUFCR_RGUFC   ETH_MMCRGUFCR_RGUFC_Msk /* Number of good unicast frames received. */
     
    #define ETH_PTPTSCR_TSPFFMAE_Pos   (18U)
     
    #define ETH_PTPTSCR_TSPFFMAE_Msk   (0x1UL << ETH_PTPTSCR_TSPFFMAE_Pos)
     
    #define ETH_PTPTSCR_TSPFFMAE   ETH_PTPTSCR_TSPFFMAE_Msk /* Time stamp PTP frame filtering MAC address enable */
     
    #define ETH_PTPTSCR_TSCNT_Pos   (16U)
     
    #define ETH_PTPTSCR_TSCNT_Msk   (0x3UL << ETH_PTPTSCR_TSCNT_Pos)
     
    #define ETH_PTPTSCR_TSCNT   ETH_PTPTSCR_TSCNT_Msk /* Time stamp clock node type */
     
    #define ETH_PTPTSCR_TSSMRME_Pos   (15U)
     
    #define ETH_PTPTSCR_TSSMRME_Msk   (0x1UL << ETH_PTPTSCR_TSSMRME_Pos)
     
    #define ETH_PTPTSCR_TSSMRME   ETH_PTPTSCR_TSSMRME_Msk /* Time stamp snapshot for message relevant to master enable */
     
    #define ETH_PTPTSCR_TSSEME_Pos   (14U)
     
    #define ETH_PTPTSCR_TSSEME_Msk   (0x1UL << ETH_PTPTSCR_TSSEME_Pos)
     
    #define ETH_PTPTSCR_TSSEME   ETH_PTPTSCR_TSSEME_Msk /* Time stamp snapshot for event message enable */
     
    #define ETH_PTPTSCR_TSSIPV4FE_Pos   (13U)
     
    #define ETH_PTPTSCR_TSSIPV4FE_Msk   (0x1UL << ETH_PTPTSCR_TSSIPV4FE_Pos)
     
    #define ETH_PTPTSCR_TSSIPV4FE   ETH_PTPTSCR_TSSIPV4FE_Msk /* Time stamp snapshot for IPv4 frames enable */
     
    #define ETH_PTPTSCR_TSSIPV6FE_Pos   (12U)
     
    #define ETH_PTPTSCR_TSSIPV6FE_Msk   (0x1UL << ETH_PTPTSCR_TSSIPV6FE_Pos)
     
    #define ETH_PTPTSCR_TSSIPV6FE   ETH_PTPTSCR_TSSIPV6FE_Msk /* Time stamp snapshot for IPv6 frames enable */
     
    #define ETH_PTPTSCR_TSSPTPOEFE_Pos   (11U)
     
    #define ETH_PTPTSCR_TSSPTPOEFE_Msk   (0x1UL << ETH_PTPTSCR_TSSPTPOEFE_Pos)
     
    #define ETH_PTPTSCR_TSSPTPOEFE   ETH_PTPTSCR_TSSPTPOEFE_Msk /* Time stamp snapshot for PTP over ethernet frames enable */
     
    #define ETH_PTPTSCR_TSPTPPSV2E_Pos   (10U)
     
    #define ETH_PTPTSCR_TSPTPPSV2E_Msk   (0x1UL << ETH_PTPTSCR_TSPTPPSV2E_Pos)
     
    #define ETH_PTPTSCR_TSPTPPSV2E   ETH_PTPTSCR_TSPTPPSV2E_Msk /* Time stamp PTP packet snooping for version2 format enable */
     
    #define ETH_PTPTSCR_TSSSR_Pos   (9U)
     
    #define ETH_PTPTSCR_TSSSR_Msk   (0x1UL << ETH_PTPTSCR_TSSSR_Pos)
     
    #define ETH_PTPTSCR_TSSSR   ETH_PTPTSCR_TSSSR_Msk /* Time stamp Sub-seconds rollover */
     
    #define ETH_PTPTSCR_TSSARFE_Pos   (8U)
     
    #define ETH_PTPTSCR_TSSARFE_Msk   (0x1UL << ETH_PTPTSCR_TSSARFE_Pos)
     
    #define ETH_PTPTSCR_TSSARFE   ETH_PTPTSCR_TSSARFE_Msk /* Time stamp snapshot for all received frames enable */
     
    #define ETH_PTPTSCR_TSARU_Pos   (5U)
     
    #define ETH_PTPTSCR_TSARU_Msk   (0x1UL << ETH_PTPTSCR_TSARU_Pos)
     
    #define ETH_PTPTSCR_TSARU   ETH_PTPTSCR_TSARU_Msk /* Addend register update */
     
    #define ETH_PTPTSCR_TSITE_Pos   (4U)
     
    #define ETH_PTPTSCR_TSITE_Msk   (0x1UL << ETH_PTPTSCR_TSITE_Pos)
     
    #define ETH_PTPTSCR_TSITE   ETH_PTPTSCR_TSITE_Msk /* Time stamp interrupt trigger enable */
     
    #define ETH_PTPTSCR_TSSTU_Pos   (3U)
     
    #define ETH_PTPTSCR_TSSTU_Msk   (0x1UL << ETH_PTPTSCR_TSSTU_Pos)
     
    #define ETH_PTPTSCR_TSSTU   ETH_PTPTSCR_TSSTU_Msk /* Time stamp update */
     
    #define ETH_PTPTSCR_TSSTI_Pos   (2U)
     
    #define ETH_PTPTSCR_TSSTI_Msk   (0x1UL << ETH_PTPTSCR_TSSTI_Pos)
     
    #define ETH_PTPTSCR_TSSTI   ETH_PTPTSCR_TSSTI_Msk /* Time stamp initialize */
     
    #define ETH_PTPTSCR_TSFCU_Pos   (1U)
     
    #define ETH_PTPTSCR_TSFCU_Msk   (0x1UL << ETH_PTPTSCR_TSFCU_Pos)
     
    #define ETH_PTPTSCR_TSFCU   ETH_PTPTSCR_TSFCU_Msk /* Time stamp fine or coarse update */
     
    #define ETH_PTPTSCR_TSE_Pos   (0U)
     
    #define ETH_PTPTSCR_TSE_Msk   (0x1UL << ETH_PTPTSCR_TSE_Pos)
     
    #define ETH_PTPTSCR_TSE   ETH_PTPTSCR_TSE_Msk /* Time stamp enable */
     
    #define ETH_PTPSSIR_STSSI_Pos   (0U)
     
    #define ETH_PTPSSIR_STSSI_Msk   (0xFFUL << ETH_PTPSSIR_STSSI_Pos)
     
    #define ETH_PTPSSIR_STSSI   ETH_PTPSSIR_STSSI_Msk /* System time Sub-second increment value */
     
    #define ETH_PTPTSHR_STS_Pos   (0U)
     
    #define ETH_PTPTSHR_STS_Msk   (0xFFFFFFFFUL << ETH_PTPTSHR_STS_Pos)
     
    #define ETH_PTPTSHR_STS   ETH_PTPTSHR_STS_Msk /* System Time second */
     
    #define ETH_PTPTSLR_STPNS_Pos   (31U)
     
    #define ETH_PTPTSLR_STPNS_Msk   (0x1UL << ETH_PTPTSLR_STPNS_Pos)
     
    #define ETH_PTPTSLR_STPNS   ETH_PTPTSLR_STPNS_Msk /* System Time Positive or negative time */
     
    #define ETH_PTPTSLR_STSS_Pos   (0U)
     
    #define ETH_PTPTSLR_STSS_Msk   (0x7FFFFFFFUL << ETH_PTPTSLR_STSS_Pos)
     
    #define ETH_PTPTSLR_STSS   ETH_PTPTSLR_STSS_Msk /* System Time sub-seconds */
     
    #define ETH_PTPTSHUR_TSUS_Pos   (0U)
     
    #define ETH_PTPTSHUR_TSUS_Msk   (0xFFFFFFFFUL << ETH_PTPTSHUR_TSUS_Pos)
     
    #define ETH_PTPTSHUR_TSUS   ETH_PTPTSHUR_TSUS_Msk /* Time stamp update seconds */
     
    #define ETH_PTPTSLUR_TSUPNS_Pos   (31U)
     
    #define ETH_PTPTSLUR_TSUPNS_Msk   (0x1UL << ETH_PTPTSLUR_TSUPNS_Pos)
     
    #define ETH_PTPTSLUR_TSUPNS   ETH_PTPTSLUR_TSUPNS_Msk /* Time stamp update Positive or negative time */
     
    #define ETH_PTPTSLUR_TSUSS_Pos   (0U)
     
    #define ETH_PTPTSLUR_TSUSS_Msk   (0x7FFFFFFFUL << ETH_PTPTSLUR_TSUSS_Pos)
     
    #define ETH_PTPTSLUR_TSUSS   ETH_PTPTSLUR_TSUSS_Msk /* Time stamp update sub-seconds */
     
    #define ETH_PTPTSAR_TSA_Pos   (0U)
     
    #define ETH_PTPTSAR_TSA_Msk   (0xFFFFFFFFUL << ETH_PTPTSAR_TSA_Pos)
     
    #define ETH_PTPTSAR_TSA   ETH_PTPTSAR_TSA_Msk /* Time stamp addend */
     
    #define ETH_PTPTTHR_TTSH_Pos   (0U)
     
    #define ETH_PTPTTHR_TTSH_Msk   (0xFFFFFFFFUL << ETH_PTPTTHR_TTSH_Pos)
     
    #define ETH_PTPTTHR_TTSH   ETH_PTPTTHR_TTSH_Msk /* Target time stamp high */
     
    #define ETH_PTPTTLR_TTSL_Pos   (0U)
     
    #define ETH_PTPTTLR_TTSL_Msk   (0xFFFFFFFFUL << ETH_PTPTTLR_TTSL_Pos)
     
    #define ETH_PTPTTLR_TTSL   ETH_PTPTTLR_TTSL_Msk /* Target time stamp low */
     
    #define ETH_PTPTSSR_TSTTR_Pos   (5U)
     
    #define ETH_PTPTSSR_TSTTR_Msk   (0x1UL << ETH_PTPTSSR_TSTTR_Pos)
     
    #define ETH_PTPTSSR_TSTTR   ETH_PTPTSSR_TSTTR_Msk /* Time stamp target time reached */
     
    #define ETH_PTPTSSR_TSSO_Pos   (4U)
     
    #define ETH_PTPTSSR_TSSO_Msk   (0x1UL << ETH_PTPTSSR_TSSO_Pos)
     
    #define ETH_PTPTSSR_TSSO   ETH_PTPTSSR_TSSO_Msk /* Time stamp seconds overflow */
     
    #define ETH_DMABMR_MB_Pos   (26U)
     
    #define ETH_DMABMR_MB_Msk   (0x1UL << ETH_DMABMR_MB_Pos)
     
    #define ETH_DMABMR_MB   ETH_DMABMR_MB_Msk /* Mixed Burst */
     
    #define ETH_DMABMR_AAB_Pos   (25U)
     
    #define ETH_DMABMR_AAB_Msk   (0x1UL << ETH_DMABMR_AAB_Pos)
     
    #define ETH_DMABMR_AAB   ETH_DMABMR_AAB_Msk /* Address-Aligned beats */
     
    #define ETH_DMABMR_FPM_Pos   (24U)
     
    #define ETH_DMABMR_FPM_Msk   (0x1UL << ETH_DMABMR_FPM_Pos)
     
    #define ETH_DMABMR_FPM   ETH_DMABMR_FPM_Msk /* 4xPBL mode */
     
    #define ETH_DMABMR_USP_Pos   (23U)
     
    #define ETH_DMABMR_USP_Msk   (0x1UL << ETH_DMABMR_USP_Pos)
     
    #define ETH_DMABMR_USP   ETH_DMABMR_USP_Msk /* Use separate PBL */
     
    #define ETH_DMABMR_RDP_Pos   (17U)
     
    #define ETH_DMABMR_RDP_Msk   (0x3FUL << ETH_DMABMR_RDP_Pos)
     
    #define ETH_DMABMR_RDP   ETH_DMABMR_RDP_Msk /* RxDMA PBL */
     
    #define ETH_DMABMR_RDP_1Beat   0x00020000U /* maximum number of beats to be transferred in one RxDMA transaction is 1 */
     
    #define ETH_DMABMR_RDP_2Beat   0x00040000U /* maximum number of beats to be transferred in one RxDMA transaction is 2 */
     
    #define ETH_DMABMR_RDP_4Beat   0x00080000U /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
     
    #define ETH_DMABMR_RDP_8Beat   0x00100000U /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
     
    #define ETH_DMABMR_RDP_16Beat   0x00200000U /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
     
    #define ETH_DMABMR_RDP_32Beat   0x00400000U /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
     
    #define ETH_DMABMR_RDP_4xPBL_4Beat   0x01020000U /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
     
    #define ETH_DMABMR_RDP_4xPBL_8Beat   0x01040000U /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
     
    #define ETH_DMABMR_RDP_4xPBL_16Beat   0x01080000U /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
     
    #define ETH_DMABMR_RDP_4xPBL_32Beat   0x01100000U /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
     
    #define ETH_DMABMR_RDP_4xPBL_64Beat   0x01200000U /* maximum number of beats to be transferred in one RxDMA transaction is 64 */
     
    #define ETH_DMABMR_RDP_4xPBL_128Beat   0x01400000U /* maximum number of beats to be transferred in one RxDMA transaction is 128 */
     
    #define ETH_DMABMR_FB_Pos   (16U)
     
    #define ETH_DMABMR_FB_Msk   (0x1UL << ETH_DMABMR_FB_Pos)
     
    #define ETH_DMABMR_FB   ETH_DMABMR_FB_Msk /* Fixed Burst */
     
    #define ETH_DMABMR_RTPR_Pos   (14U)
     
    #define ETH_DMABMR_RTPR_Msk   (0x3UL << ETH_DMABMR_RTPR_Pos)
     
    #define ETH_DMABMR_RTPR   ETH_DMABMR_RTPR_Msk /* Rx Tx priority ratio */
     
    #define ETH_DMABMR_RTPR_1_1   0x00000000U /* Rx Tx priority ratio */
     
    #define ETH_DMABMR_RTPR_2_1   0x00004000U /* Rx Tx priority ratio */
     
    #define ETH_DMABMR_RTPR_3_1   0x00008000U /* Rx Tx priority ratio */
     
    #define ETH_DMABMR_RTPR_4_1   0x0000C000U /* Rx Tx priority ratio */
     
    #define ETH_DMABMR_PBL_Pos   (8U)
     
    #define ETH_DMABMR_PBL_Msk   (0x3FUL << ETH_DMABMR_PBL_Pos)
     
    #define ETH_DMABMR_PBL   ETH_DMABMR_PBL_Msk /* Programmable burst length */
     
    #define ETH_DMABMR_PBL_1Beat   0x00000100U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
     
    #define ETH_DMABMR_PBL_2Beat   0x00000200U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
     
    #define ETH_DMABMR_PBL_4Beat   0x00000400U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
     
    #define ETH_DMABMR_PBL_8Beat   0x00000800U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
     
    #define ETH_DMABMR_PBL_16Beat   0x00001000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
     
    #define ETH_DMABMR_PBL_32Beat   0x00002000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
     
    #define ETH_DMABMR_PBL_4xPBL_4Beat   0x01000100U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
     
    #define ETH_DMABMR_PBL_4xPBL_8Beat   0x01000200U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
     
    #define ETH_DMABMR_PBL_4xPBL_16Beat   0x01000400U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
     
    #define ETH_DMABMR_PBL_4xPBL_32Beat   0x01000800U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
     
    #define ETH_DMABMR_PBL_4xPBL_64Beat   0x01001000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
     
    #define ETH_DMABMR_PBL_4xPBL_128Beat   0x01002000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
     
    #define ETH_DMABMR_EDE_Pos   (7U)
     
    #define ETH_DMABMR_EDE_Msk   (0x1UL << ETH_DMABMR_EDE_Pos)
     
    #define ETH_DMABMR_EDE   ETH_DMABMR_EDE_Msk /* Enhanced Descriptor Enable */
     
    #define ETH_DMABMR_DSL_Pos   (2U)
     
    #define ETH_DMABMR_DSL_Msk   (0x1FUL << ETH_DMABMR_DSL_Pos)
     
    #define ETH_DMABMR_DSL   ETH_DMABMR_DSL_Msk /* Descriptor Skip Length */
     
    #define ETH_DMABMR_DA_Pos   (1U)
     
    #define ETH_DMABMR_DA_Msk   (0x1UL << ETH_DMABMR_DA_Pos)
     
    #define ETH_DMABMR_DA   ETH_DMABMR_DA_Msk /* DMA arbitration scheme */
     
    #define ETH_DMABMR_SR_Pos   (0U)
     
    #define ETH_DMABMR_SR_Msk   (0x1UL << ETH_DMABMR_SR_Pos)
     
    #define ETH_DMABMR_SR   ETH_DMABMR_SR_Msk /* Software reset */
     
    #define ETH_DMATPDR_TPD_Pos   (0U)
     
    #define ETH_DMATPDR_TPD_Msk   (0xFFFFFFFFUL << ETH_DMATPDR_TPD_Pos)
     
    #define ETH_DMATPDR_TPD   ETH_DMATPDR_TPD_Msk /* Transmit poll demand */
     
    #define ETH_DMARPDR_RPD_Pos   (0U)
     
    #define ETH_DMARPDR_RPD_Msk   (0xFFFFFFFFUL << ETH_DMARPDR_RPD_Pos)
     
    #define ETH_DMARPDR_RPD   ETH_DMARPDR_RPD_Msk /* Receive poll demand */
     
    #define ETH_DMARDLAR_SRL_Pos   (0U)
     
    #define ETH_DMARDLAR_SRL_Msk   (0xFFFFFFFFUL << ETH_DMARDLAR_SRL_Pos)
     
    #define ETH_DMARDLAR_SRL   ETH_DMARDLAR_SRL_Msk /* Start of receive list */
     
    #define ETH_DMATDLAR_STL_Pos   (0U)
     
    #define ETH_DMATDLAR_STL_Msk   (0xFFFFFFFFUL << ETH_DMATDLAR_STL_Pos)
     
    #define ETH_DMATDLAR_STL   ETH_DMATDLAR_STL_Msk /* Start of transmit list */
     
    #define ETH_DMASR_TSTS_Pos   (29U)
     
    #define ETH_DMASR_TSTS_Msk   (0x1UL << ETH_DMASR_TSTS_Pos)
     
    #define ETH_DMASR_TSTS   ETH_DMASR_TSTS_Msk /* Time-stamp trigger status */
     
    #define ETH_DMASR_PMTS_Pos   (28U)
     
    #define ETH_DMASR_PMTS_Msk   (0x1UL << ETH_DMASR_PMTS_Pos)
     
    #define ETH_DMASR_PMTS   ETH_DMASR_PMTS_Msk /* PMT status */
     
    #define ETH_DMASR_MMCS_Pos   (27U)
     
    #define ETH_DMASR_MMCS_Msk   (0x1UL << ETH_DMASR_MMCS_Pos)
     
    #define ETH_DMASR_MMCS   ETH_DMASR_MMCS_Msk /* MMC status */
     
    #define ETH_DMASR_EBS_Pos   (23U)
     
    #define ETH_DMASR_EBS_Msk   (0x7UL << ETH_DMASR_EBS_Pos)
     
    #define ETH_DMASR_EBS   ETH_DMASR_EBS_Msk /* Error bits status */
     
    #define ETH_DMASR_EBS_DescAccess_Pos   (25U)
     
    #define ETH_DMASR_EBS_DescAccess_Msk   (0x1UL << ETH_DMASR_EBS_DescAccess_Pos)
     
    #define ETH_DMASR_EBS_DescAccess   ETH_DMASR_EBS_DescAccess_Msk /* Error bits 0-data buffer, 1-desc. access */
     
    #define ETH_DMASR_EBS_ReadTransf_Pos   (24U)
     
    #define ETH_DMASR_EBS_ReadTransf_Msk   (0x1UL << ETH_DMASR_EBS_ReadTransf_Pos)
     
    #define ETH_DMASR_EBS_ReadTransf   ETH_DMASR_EBS_ReadTransf_Msk /* Error bits 0-write trnsf, 1-read transfr */
     
    #define ETH_DMASR_EBS_DataTransfTx_Pos   (23U)
     
    #define ETH_DMASR_EBS_DataTransfTx_Msk   (0x1UL << ETH_DMASR_EBS_DataTransfTx_Pos)
     
    #define ETH_DMASR_EBS_DataTransfTx   ETH_DMASR_EBS_DataTransfTx_Msk /* Error bits 0-Rx DMA, 1-Tx DMA */
     
    #define ETH_DMASR_TPS_Pos   (20U)
     
    #define ETH_DMASR_TPS_Msk   (0x7UL << ETH_DMASR_TPS_Pos)
     
    #define ETH_DMASR_TPS   ETH_DMASR_TPS_Msk /* Transmit process state */
     
    #define ETH_DMASR_TPS_Stopped   0x00000000U /* Stopped - Reset or Stop Tx Command issued */
     
    #define ETH_DMASR_TPS_Fetching_Pos   (20U)
     
    #define ETH_DMASR_TPS_Fetching_Msk   (0x1UL << ETH_DMASR_TPS_Fetching_Pos)
     
    #define ETH_DMASR_TPS_Fetching   ETH_DMASR_TPS_Fetching_Msk /* Running - fetching the Tx descriptor */
     
    #define ETH_DMASR_TPS_Waiting_Pos   (21U)
     
    #define ETH_DMASR_TPS_Waiting_Msk   (0x1UL << ETH_DMASR_TPS_Waiting_Pos)
     
    #define ETH_DMASR_TPS_Waiting   ETH_DMASR_TPS_Waiting_Msk /* Running - waiting for status */
     
    #define ETH_DMASR_TPS_Reading_Pos   (20U)
     
    #define ETH_DMASR_TPS_Reading_Msk   (0x3UL << ETH_DMASR_TPS_Reading_Pos)
     
    #define ETH_DMASR_TPS_Reading   ETH_DMASR_TPS_Reading_Msk /* Running - reading the data from host memory */
     
    #define ETH_DMASR_TPS_Suspended_Pos   (21U)
     
    #define ETH_DMASR_TPS_Suspended_Msk   (0x3UL << ETH_DMASR_TPS_Suspended_Pos)
     
    #define ETH_DMASR_TPS_Suspended   ETH_DMASR_TPS_Suspended_Msk /* Suspended - Tx Descriptor unavailable */
     
    #define ETH_DMASR_TPS_Closing_Pos   (20U)
     
    #define ETH_DMASR_TPS_Closing_Msk   (0x7UL << ETH_DMASR_TPS_Closing_Pos)
     
    #define ETH_DMASR_TPS_Closing   ETH_DMASR_TPS_Closing_Msk /* Running - closing Rx descriptor */
     
    #define ETH_DMASR_RPS_Pos   (17U)
     
    #define ETH_DMASR_RPS_Msk   (0x7UL << ETH_DMASR_RPS_Pos)
     
    #define ETH_DMASR_RPS   ETH_DMASR_RPS_Msk /* Receive process state */
     
    #define ETH_DMASR_RPS_Stopped   0x00000000U /* Stopped - Reset or Stop Rx Command issued */
     
    #define ETH_DMASR_RPS_Fetching_Pos   (17U)
     
    #define ETH_DMASR_RPS_Fetching_Msk   (0x1UL << ETH_DMASR_RPS_Fetching_Pos)
     
    #define ETH_DMASR_RPS_Fetching   ETH_DMASR_RPS_Fetching_Msk /* Running - fetching the Rx descriptor */
     
    #define ETH_DMASR_RPS_Waiting_Pos   (17U)
     
    #define ETH_DMASR_RPS_Waiting_Msk   (0x3UL << ETH_DMASR_RPS_Waiting_Pos)
     
    #define ETH_DMASR_RPS_Waiting   ETH_DMASR_RPS_Waiting_Msk /* Running - waiting for packet */
     
    #define ETH_DMASR_RPS_Suspended_Pos   (19U)
     
    #define ETH_DMASR_RPS_Suspended_Msk   (0x1UL << ETH_DMASR_RPS_Suspended_Pos)
     
    #define ETH_DMASR_RPS_Suspended   ETH_DMASR_RPS_Suspended_Msk /* Suspended - Rx Descriptor unavailable */
     
    #define ETH_DMASR_RPS_Closing_Pos   (17U)
     
    #define ETH_DMASR_RPS_Closing_Msk   (0x5UL << ETH_DMASR_RPS_Closing_Pos)
     
    #define ETH_DMASR_RPS_Closing   ETH_DMASR_RPS_Closing_Msk /* Running - closing descriptor */
     
    #define ETH_DMASR_RPS_Queuing_Pos   (17U)
     
    #define ETH_DMASR_RPS_Queuing_Msk   (0x7UL << ETH_DMASR_RPS_Queuing_Pos)
     
    #define ETH_DMASR_RPS_Queuing   ETH_DMASR_RPS_Queuing_Msk /* Running - queuing the receive frame into host memory */
     
    #define ETH_DMASR_NIS_Pos   (16U)
     
    #define ETH_DMASR_NIS_Msk   (0x1UL << ETH_DMASR_NIS_Pos)
     
    #define ETH_DMASR_NIS   ETH_DMASR_NIS_Msk /* Normal interrupt summary */
     
    #define ETH_DMASR_AIS_Pos   (15U)
     
    #define ETH_DMASR_AIS_Msk   (0x1UL << ETH_DMASR_AIS_Pos)
     
    #define ETH_DMASR_AIS   ETH_DMASR_AIS_Msk /* Abnormal interrupt summary */
     
    #define ETH_DMASR_ERS_Pos   (14U)
     
    #define ETH_DMASR_ERS_Msk   (0x1UL << ETH_DMASR_ERS_Pos)
     
    #define ETH_DMASR_ERS   ETH_DMASR_ERS_Msk /* Early receive status */
     
    #define ETH_DMASR_FBES_Pos   (13U)
     
    #define ETH_DMASR_FBES_Msk   (0x1UL << ETH_DMASR_FBES_Pos)
     
    #define ETH_DMASR_FBES   ETH_DMASR_FBES_Msk /* Fatal bus error status */
     
    #define ETH_DMASR_ETS_Pos   (10U)
     
    #define ETH_DMASR_ETS_Msk   (0x1UL << ETH_DMASR_ETS_Pos)
     
    #define ETH_DMASR_ETS   ETH_DMASR_ETS_Msk /* Early transmit status */
     
    #define ETH_DMASR_RWTS_Pos   (9U)
     
    #define ETH_DMASR_RWTS_Msk   (0x1UL << ETH_DMASR_RWTS_Pos)
     
    #define ETH_DMASR_RWTS   ETH_DMASR_RWTS_Msk /* Receive watchdog timeout status */
     
    #define ETH_DMASR_RPSS_Pos   (8U)
     
    #define ETH_DMASR_RPSS_Msk   (0x1UL << ETH_DMASR_RPSS_Pos)
     
    #define ETH_DMASR_RPSS   ETH_DMASR_RPSS_Msk /* Receive process stopped status */
     
    #define ETH_DMASR_RBUS_Pos   (7U)
     
    #define ETH_DMASR_RBUS_Msk   (0x1UL << ETH_DMASR_RBUS_Pos)
     
    #define ETH_DMASR_RBUS   ETH_DMASR_RBUS_Msk /* Receive buffer unavailable status */
     
    #define ETH_DMASR_RS_Pos   (6U)
     
    #define ETH_DMASR_RS_Msk   (0x1UL << ETH_DMASR_RS_Pos)
     
    #define ETH_DMASR_RS   ETH_DMASR_RS_Msk /* Receive status */
     
    #define ETH_DMASR_TUS_Pos   (5U)
     
    #define ETH_DMASR_TUS_Msk   (0x1UL << ETH_DMASR_TUS_Pos)
     
    #define ETH_DMASR_TUS   ETH_DMASR_TUS_Msk /* Transmit underflow status */
     
    #define ETH_DMASR_ROS_Pos   (4U)
     
    #define ETH_DMASR_ROS_Msk   (0x1UL << ETH_DMASR_ROS_Pos)
     
    #define ETH_DMASR_ROS   ETH_DMASR_ROS_Msk /* Receive overflow status */
     
    #define ETH_DMASR_TJTS_Pos   (3U)
     
    #define ETH_DMASR_TJTS_Msk   (0x1UL << ETH_DMASR_TJTS_Pos)
     
    #define ETH_DMASR_TJTS   ETH_DMASR_TJTS_Msk /* Transmit jabber timeout status */
     
    #define ETH_DMASR_TBUS_Pos   (2U)
     
    #define ETH_DMASR_TBUS_Msk   (0x1UL << ETH_DMASR_TBUS_Pos)
     
    #define ETH_DMASR_TBUS   ETH_DMASR_TBUS_Msk /* Transmit buffer unavailable status */
     
    #define ETH_DMASR_TPSS_Pos   (1U)
     
    #define ETH_DMASR_TPSS_Msk   (0x1UL << ETH_DMASR_TPSS_Pos)
     
    #define ETH_DMASR_TPSS   ETH_DMASR_TPSS_Msk /* Transmit process stopped status */
     
    #define ETH_DMASR_TS_Pos   (0U)
     
    #define ETH_DMASR_TS_Msk   (0x1UL << ETH_DMASR_TS_Pos)
     
    #define ETH_DMASR_TS   ETH_DMASR_TS_Msk /* Transmit status */
     
    #define ETH_DMAOMR_DTCEFD_Pos   (26U)
     
    #define ETH_DMAOMR_DTCEFD_Msk   (0x1UL << ETH_DMAOMR_DTCEFD_Pos)
     
    #define ETH_DMAOMR_DTCEFD   ETH_DMAOMR_DTCEFD_Msk /* Disable Dropping of TCP/IP checksum error frames */
     
    #define ETH_DMAOMR_RSF_Pos   (25U)
     
    #define ETH_DMAOMR_RSF_Msk   (0x1UL << ETH_DMAOMR_RSF_Pos)
     
    #define ETH_DMAOMR_RSF   ETH_DMAOMR_RSF_Msk /* Receive store and forward */
     
    #define ETH_DMAOMR_DFRF_Pos   (24U)
     
    #define ETH_DMAOMR_DFRF_Msk   (0x1UL << ETH_DMAOMR_DFRF_Pos)
     
    #define ETH_DMAOMR_DFRF   ETH_DMAOMR_DFRF_Msk /* Disable flushing of received frames */
     
    #define ETH_DMAOMR_TSF_Pos   (21U)
     
    #define ETH_DMAOMR_TSF_Msk   (0x1UL << ETH_DMAOMR_TSF_Pos)
     
    #define ETH_DMAOMR_TSF   ETH_DMAOMR_TSF_Msk /* Transmit store and forward */
     
    #define ETH_DMAOMR_FTF_Pos   (20U)
     
    #define ETH_DMAOMR_FTF_Msk   (0x1UL << ETH_DMAOMR_FTF_Pos)
     
    #define ETH_DMAOMR_FTF   ETH_DMAOMR_FTF_Msk /* Flush transmit FIFO */
     
    #define ETH_DMAOMR_TTC_Pos   (14U)
     
    #define ETH_DMAOMR_TTC_Msk   (0x7UL << ETH_DMAOMR_TTC_Pos)
     
    #define ETH_DMAOMR_TTC   ETH_DMAOMR_TTC_Msk /* Transmit threshold control */
     
    #define ETH_DMAOMR_TTC_64Bytes   0x00000000U /* threshold level of the MTL Transmit FIFO is 64 Bytes */
     
    #define ETH_DMAOMR_TTC_128Bytes   0x00004000U /* threshold level of the MTL Transmit FIFO is 128 Bytes */
     
    #define ETH_DMAOMR_TTC_192Bytes   0x00008000U /* threshold level of the MTL Transmit FIFO is 192 Bytes */
     
    #define ETH_DMAOMR_TTC_256Bytes   0x0000C000U /* threshold level of the MTL Transmit FIFO is 256 Bytes */
     
    #define ETH_DMAOMR_TTC_40Bytes   0x00010000U /* threshold level of the MTL Transmit FIFO is 40 Bytes */
     
    #define ETH_DMAOMR_TTC_32Bytes   0x00014000U /* threshold level of the MTL Transmit FIFO is 32 Bytes */
     
    #define ETH_DMAOMR_TTC_24Bytes   0x00018000U /* threshold level of the MTL Transmit FIFO is 24 Bytes */
     
    #define ETH_DMAOMR_TTC_16Bytes   0x0001C000U /* threshold level of the MTL Transmit FIFO is 16 Bytes */
     
    #define ETH_DMAOMR_ST_Pos   (13U)
     
    #define ETH_DMAOMR_ST_Msk   (0x1UL << ETH_DMAOMR_ST_Pos)
     
    #define ETH_DMAOMR_ST   ETH_DMAOMR_ST_Msk /* Start/stop transmission command */
     
    #define ETH_DMAOMR_FEF_Pos   (7U)
     
    #define ETH_DMAOMR_FEF_Msk   (0x1UL << ETH_DMAOMR_FEF_Pos)
     
    #define ETH_DMAOMR_FEF   ETH_DMAOMR_FEF_Msk /* Forward error frames */
     
    #define ETH_DMAOMR_FUGF_Pos   (6U)
     
    #define ETH_DMAOMR_FUGF_Msk   (0x1UL << ETH_DMAOMR_FUGF_Pos)
     
    #define ETH_DMAOMR_FUGF   ETH_DMAOMR_FUGF_Msk /* Forward undersized good frames */
     
    #define ETH_DMAOMR_RTC_Pos   (3U)
     
    #define ETH_DMAOMR_RTC_Msk   (0x3UL << ETH_DMAOMR_RTC_Pos)
     
    #define ETH_DMAOMR_RTC   ETH_DMAOMR_RTC_Msk /* receive threshold control */
     
    #define ETH_DMAOMR_RTC_64Bytes   0x00000000U /* threshold level of the MTL Receive FIFO is 64 Bytes */
     
    #define ETH_DMAOMR_RTC_32Bytes   0x00000008U /* threshold level of the MTL Receive FIFO is 32 Bytes */
     
    #define ETH_DMAOMR_RTC_96Bytes   0x00000010U /* threshold level of the MTL Receive FIFO is 96 Bytes */
     
    #define ETH_DMAOMR_RTC_128Bytes   0x00000018U /* threshold level of the MTL Receive FIFO is 128 Bytes */
     
    #define ETH_DMAOMR_OSF_Pos   (2U)
     
    #define ETH_DMAOMR_OSF_Msk   (0x1UL << ETH_DMAOMR_OSF_Pos)
     
    #define ETH_DMAOMR_OSF   ETH_DMAOMR_OSF_Msk /* operate on second frame */
     
    #define ETH_DMAOMR_SR_Pos   (1U)
     
    #define ETH_DMAOMR_SR_Msk   (0x1UL << ETH_DMAOMR_SR_Pos)
     
    #define ETH_DMAOMR_SR   ETH_DMAOMR_SR_Msk /* Start/stop receive */
     
    #define ETH_DMAIER_NISE_Pos   (16U)
     
    #define ETH_DMAIER_NISE_Msk   (0x1UL << ETH_DMAIER_NISE_Pos)
     
    #define ETH_DMAIER_NISE   ETH_DMAIER_NISE_Msk /* Normal interrupt summary enable */
     
    #define ETH_DMAIER_AISE_Pos   (15U)
     
    #define ETH_DMAIER_AISE_Msk   (0x1UL << ETH_DMAIER_AISE_Pos)
     
    #define ETH_DMAIER_AISE   ETH_DMAIER_AISE_Msk /* Abnormal interrupt summary enable */
     
    #define ETH_DMAIER_ERIE_Pos   (14U)
     
    #define ETH_DMAIER_ERIE_Msk   (0x1UL << ETH_DMAIER_ERIE_Pos)
     
    #define ETH_DMAIER_ERIE   ETH_DMAIER_ERIE_Msk /* Early receive interrupt enable */
     
    #define ETH_DMAIER_FBEIE_Pos   (13U)
     
    #define ETH_DMAIER_FBEIE_Msk   (0x1UL << ETH_DMAIER_FBEIE_Pos)
     
    #define ETH_DMAIER_FBEIE   ETH_DMAIER_FBEIE_Msk /* Fatal bus error interrupt enable */
     
    #define ETH_DMAIER_ETIE_Pos   (10U)
     
    #define ETH_DMAIER_ETIE_Msk   (0x1UL << ETH_DMAIER_ETIE_Pos)
     
    #define ETH_DMAIER_ETIE   ETH_DMAIER_ETIE_Msk /* Early transmit interrupt enable */
     
    #define ETH_DMAIER_RWTIE_Pos   (9U)
     
    #define ETH_DMAIER_RWTIE_Msk   (0x1UL << ETH_DMAIER_RWTIE_Pos)
     
    #define ETH_DMAIER_RWTIE   ETH_DMAIER_RWTIE_Msk /* Receive watchdog timeout interrupt enable */
     
    #define ETH_DMAIER_RPSIE_Pos   (8U)
     
    #define ETH_DMAIER_RPSIE_Msk   (0x1UL << ETH_DMAIER_RPSIE_Pos)
     
    #define ETH_DMAIER_RPSIE   ETH_DMAIER_RPSIE_Msk /* Receive process stopped interrupt enable */
     
    #define ETH_DMAIER_RBUIE_Pos   (7U)
     
    #define ETH_DMAIER_RBUIE_Msk   (0x1UL << ETH_DMAIER_RBUIE_Pos)
     
    #define ETH_DMAIER_RBUIE   ETH_DMAIER_RBUIE_Msk /* Receive buffer unavailable interrupt enable */
     
    #define ETH_DMAIER_RIE_Pos   (6U)
     
    #define ETH_DMAIER_RIE_Msk   (0x1UL << ETH_DMAIER_RIE_Pos)
     
    #define ETH_DMAIER_RIE   ETH_DMAIER_RIE_Msk /* Receive interrupt enable */
     
    #define ETH_DMAIER_TUIE_Pos   (5U)
     
    #define ETH_DMAIER_TUIE_Msk   (0x1UL << ETH_DMAIER_TUIE_Pos)
     
    #define ETH_DMAIER_TUIE   ETH_DMAIER_TUIE_Msk /* Transmit Underflow interrupt enable */
     
    #define ETH_DMAIER_ROIE_Pos   (4U)
     
    #define ETH_DMAIER_ROIE_Msk   (0x1UL << ETH_DMAIER_ROIE_Pos)
     
    #define ETH_DMAIER_ROIE   ETH_DMAIER_ROIE_Msk /* Receive Overflow interrupt enable */
     
    #define ETH_DMAIER_TJTIE_Pos   (3U)
     
    #define ETH_DMAIER_TJTIE_Msk   (0x1UL << ETH_DMAIER_TJTIE_Pos)
     
    #define ETH_DMAIER_TJTIE   ETH_DMAIER_TJTIE_Msk /* Transmit jabber timeout interrupt enable */
     
    #define ETH_DMAIER_TBUIE_Pos   (2U)
     
    #define ETH_DMAIER_TBUIE_Msk   (0x1UL << ETH_DMAIER_TBUIE_Pos)
     
    #define ETH_DMAIER_TBUIE   ETH_DMAIER_TBUIE_Msk /* Transmit buffer unavailable interrupt enable */
     
    #define ETH_DMAIER_TPSIE_Pos   (1U)
     
    #define ETH_DMAIER_TPSIE_Msk   (0x1UL << ETH_DMAIER_TPSIE_Pos)
     
    #define ETH_DMAIER_TPSIE   ETH_DMAIER_TPSIE_Msk /* Transmit process stopped interrupt enable */
     
    #define ETH_DMAIER_TIE_Pos   (0U)
     
    #define ETH_DMAIER_TIE_Msk   (0x1UL << ETH_DMAIER_TIE_Pos)
     
    #define ETH_DMAIER_TIE   ETH_DMAIER_TIE_Msk /* Transmit interrupt enable */
     
    #define ETH_DMAMFBOCR_OFOC_Pos   (28U)
     
    #define ETH_DMAMFBOCR_OFOC_Msk   (0x1UL << ETH_DMAMFBOCR_OFOC_Pos)
     
    #define ETH_DMAMFBOCR_OFOC   ETH_DMAMFBOCR_OFOC_Msk /* Overflow bit for FIFO overflow counter */
     
    #define ETH_DMAMFBOCR_MFA_Pos   (17U)
     
    #define ETH_DMAMFBOCR_MFA_Msk   (0x7FFUL << ETH_DMAMFBOCR_MFA_Pos)
     
    #define ETH_DMAMFBOCR_MFA   ETH_DMAMFBOCR_MFA_Msk /* Number of frames missed by the application */
     
    #define ETH_DMAMFBOCR_OMFC_Pos   (16U)
     
    #define ETH_DMAMFBOCR_OMFC_Msk   (0x1UL << ETH_DMAMFBOCR_OMFC_Pos)
     
    #define ETH_DMAMFBOCR_OMFC   ETH_DMAMFBOCR_OMFC_Msk /* Overflow bit for missed frame counter */
     
    #define ETH_DMAMFBOCR_MFC_Pos   (0U)
     
    #define ETH_DMAMFBOCR_MFC_Msk   (0xFFFFUL << ETH_DMAMFBOCR_MFC_Pos)
     
    #define ETH_DMAMFBOCR_MFC   ETH_DMAMFBOCR_MFC_Msk /* Number of frames missed by the controller */
     
    #define ETH_DMACHTDR_HTDAP_Pos   (0U)
     
    #define ETH_DMACHTDR_HTDAP_Msk   (0xFFFFFFFFUL << ETH_DMACHTDR_HTDAP_Pos)
     
    #define ETH_DMACHTDR_HTDAP   ETH_DMACHTDR_HTDAP_Msk /* Host transmit descriptor address pointer */
     
    #define ETH_DMACHRDR_HRDAP_Pos   (0U)
     
    #define ETH_DMACHRDR_HRDAP_Msk   (0xFFFFFFFFUL << ETH_DMACHRDR_HRDAP_Pos)
     
    #define ETH_DMACHRDR_HRDAP   ETH_DMACHRDR_HRDAP_Msk /* Host receive descriptor address pointer */
     
    #define ETH_DMACHTBAR_HTBAP_Pos   (0U)
     
    #define ETH_DMACHTBAR_HTBAP_Msk   (0xFFFFFFFFUL << ETH_DMACHTBAR_HTBAP_Pos)
     
    #define ETH_DMACHTBAR_HTBAP   ETH_DMACHTBAR_HTBAP_Msk /* Host transmit buffer address pointer */
     
    #define ETH_DMACHRBAR_HRBAP_Pos   (0U)
     
    #define ETH_DMACHRBAR_HRBAP_Msk   (0xFFFFFFFFUL << ETH_DMACHRBAR_HRBAP_Pos)
     
    #define ETH_DMACHRBAR_HRBAP   ETH_DMACHRBAR_HRBAP_Msk /* Host receive buffer address pointer */
     
    #define USB_OTG_GOTGCTL_SRQSCS_Pos   (0U)
     
    #define USB_OTG_GOTGCTL_SRQSCS_Msk   (0x1UL << USB_OTG_GOTGCTL_SRQSCS_Pos)
     
    #define USB_OTG_GOTGCTL_SRQSCS   USB_OTG_GOTGCTL_SRQSCS_Msk
     
    #define USB_OTG_GOTGCTL_SRQ_Pos   (1U)
     
    #define USB_OTG_GOTGCTL_SRQ_Msk   (0x1UL << USB_OTG_GOTGCTL_SRQ_Pos)
     
    #define USB_OTG_GOTGCTL_SRQ   USB_OTG_GOTGCTL_SRQ_Msk
     
    #define USB_OTG_GOTGCTL_HNGSCS_Pos   (8U)
     
    #define USB_OTG_GOTGCTL_HNGSCS_Msk   (0x1UL << USB_OTG_GOTGCTL_HNGSCS_Pos)
     
    #define USB_OTG_GOTGCTL_HNGSCS   USB_OTG_GOTGCTL_HNGSCS_Msk
     
    #define USB_OTG_GOTGCTL_HNPRQ_Pos   (9U)
     
    #define USB_OTG_GOTGCTL_HNPRQ_Msk   (0x1UL << USB_OTG_GOTGCTL_HNPRQ_Pos)
     
    #define USB_OTG_GOTGCTL_HNPRQ   USB_OTG_GOTGCTL_HNPRQ_Msk
     
    #define USB_OTG_GOTGCTL_HSHNPEN_Pos   (10U)
     
    #define USB_OTG_GOTGCTL_HSHNPEN_Msk   (0x1UL << USB_OTG_GOTGCTL_HSHNPEN_Pos)
     
    #define USB_OTG_GOTGCTL_HSHNPEN   USB_OTG_GOTGCTL_HSHNPEN_Msk
     
    #define USB_OTG_GOTGCTL_DHNPEN_Pos   (11U)
     
    #define USB_OTG_GOTGCTL_DHNPEN_Msk   (0x1UL << USB_OTG_GOTGCTL_DHNPEN_Pos)
     
    #define USB_OTG_GOTGCTL_DHNPEN   USB_OTG_GOTGCTL_DHNPEN_Msk
     
    #define USB_OTG_GOTGCTL_CIDSTS_Pos   (16U)
     
    #define USB_OTG_GOTGCTL_CIDSTS_Msk   (0x1UL << USB_OTG_GOTGCTL_CIDSTS_Pos)
     
    #define USB_OTG_GOTGCTL_CIDSTS   USB_OTG_GOTGCTL_CIDSTS_Msk
     
    #define USB_OTG_GOTGCTL_DBCT_Pos   (17U)
     
    #define USB_OTG_GOTGCTL_DBCT_Msk   (0x1UL << USB_OTG_GOTGCTL_DBCT_Pos)
     
    #define USB_OTG_GOTGCTL_DBCT   USB_OTG_GOTGCTL_DBCT_Msk
     
    #define USB_OTG_GOTGCTL_ASVLD_Pos   (18U)
     
    #define USB_OTG_GOTGCTL_ASVLD_Msk   (0x1UL << USB_OTG_GOTGCTL_ASVLD_Pos)
     
    #define USB_OTG_GOTGCTL_ASVLD   USB_OTG_GOTGCTL_ASVLD_Msk
     
    #define USB_OTG_GOTGCTL_BSVLD_Pos   (19U)
     
    #define USB_OTG_GOTGCTL_BSVLD_Msk   (0x1UL << USB_OTG_GOTGCTL_BSVLD_Pos)
     
    #define USB_OTG_GOTGCTL_BSVLD   USB_OTG_GOTGCTL_BSVLD_Msk
     
    #define USB_OTG_HCFG_FSLSPCS_Pos   (0U)
     
    #define USB_OTG_HCFG_FSLSPCS_Msk   (0x3UL << USB_OTG_HCFG_FSLSPCS_Pos)
     
    #define USB_OTG_HCFG_FSLSPCS   USB_OTG_HCFG_FSLSPCS_Msk
     
    #define USB_OTG_HCFG_FSLSPCS_0   (0x1UL << USB_OTG_HCFG_FSLSPCS_Pos)
     
    #define USB_OTG_HCFG_FSLSPCS_1   (0x2UL << USB_OTG_HCFG_FSLSPCS_Pos)
     
    #define USB_OTG_HCFG_FSLSS_Pos   (2U)
     
    #define USB_OTG_HCFG_FSLSS_Msk   (0x1UL << USB_OTG_HCFG_FSLSS_Pos)
     
    #define USB_OTG_HCFG_FSLSS   USB_OTG_HCFG_FSLSS_Msk
     
    #define USB_OTG_DCFG_DSPD_Pos   (0U)
     
    #define USB_OTG_DCFG_DSPD_Msk   (0x3UL << USB_OTG_DCFG_DSPD_Pos)
     
    #define USB_OTG_DCFG_DSPD   USB_OTG_DCFG_DSPD_Msk
     
    #define USB_OTG_DCFG_DSPD_0   (0x1UL << USB_OTG_DCFG_DSPD_Pos)
     
    #define USB_OTG_DCFG_DSPD_1   (0x2UL << USB_OTG_DCFG_DSPD_Pos)
     
    #define USB_OTG_DCFG_NZLSOHSK_Pos   (2U)
     
    #define USB_OTG_DCFG_NZLSOHSK_Msk   (0x1UL << USB_OTG_DCFG_NZLSOHSK_Pos)
     
    #define USB_OTG_DCFG_NZLSOHSK   USB_OTG_DCFG_NZLSOHSK_Msk
     
    #define USB_OTG_DCFG_DAD_Pos   (4U)
     
    #define USB_OTG_DCFG_DAD_Msk   (0x7FUL << USB_OTG_DCFG_DAD_Pos)
     
    #define USB_OTG_DCFG_DAD   USB_OTG_DCFG_DAD_Msk
     
    #define USB_OTG_DCFG_DAD_0   (0x01UL << USB_OTG_DCFG_DAD_Pos)
     
    #define USB_OTG_DCFG_DAD_1   (0x02UL << USB_OTG_DCFG_DAD_Pos)
     
    #define USB_OTG_DCFG_DAD_2   (0x04UL << USB_OTG_DCFG_DAD_Pos)
     
    #define USB_OTG_DCFG_DAD_3   (0x08UL << USB_OTG_DCFG_DAD_Pos)
     
    #define USB_OTG_DCFG_DAD_4   (0x10UL << USB_OTG_DCFG_DAD_Pos)
     
    #define USB_OTG_DCFG_DAD_5   (0x20UL << USB_OTG_DCFG_DAD_Pos)
     
    #define USB_OTG_DCFG_DAD_6   (0x40UL << USB_OTG_DCFG_DAD_Pos)
     
    #define USB_OTG_DCFG_PFIVL_Pos   (11U)
     
    #define USB_OTG_DCFG_PFIVL_Msk   (0x3UL << USB_OTG_DCFG_PFIVL_Pos)
     
    #define USB_OTG_DCFG_PFIVL   USB_OTG_DCFG_PFIVL_Msk
     
    #define USB_OTG_DCFG_PFIVL_0   (0x1UL << USB_OTG_DCFG_PFIVL_Pos)
     
    #define USB_OTG_DCFG_PFIVL_1   (0x2UL << USB_OTG_DCFG_PFIVL_Pos)
     
    #define USB_OTG_DCFG_XCVRDLY_Pos   (14U)
     
    #define USB_OTG_DCFG_XCVRDLY_Msk   (0x1UL << USB_OTG_DCFG_XCVRDLY_Pos)
     
    #define USB_OTG_DCFG_XCVRDLY   USB_OTG_DCFG_XCVRDLY_Msk
     
    #define USB_OTG_DCFG_ERRATIM_Pos   (15U)
     
    #define USB_OTG_DCFG_ERRATIM_Msk   (0x1UL << USB_OTG_DCFG_ERRATIM_Pos)
     
    #define USB_OTG_DCFG_ERRATIM   USB_OTG_DCFG_ERRATIM_Msk
     
    #define USB_OTG_DCFG_PERSCHIVL_Pos   (24U)
     
    #define USB_OTG_DCFG_PERSCHIVL_Msk   (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos)
     
    #define USB_OTG_DCFG_PERSCHIVL   USB_OTG_DCFG_PERSCHIVL_Msk
     
    #define USB_OTG_DCFG_PERSCHIVL_0   (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos)
     
    #define USB_OTG_DCFG_PERSCHIVL_1   (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos)
     
    #define USB_OTG_PCGCR_STPPCLK_Pos   (0U)
     
    #define USB_OTG_PCGCR_STPPCLK_Msk   (0x1UL << USB_OTG_PCGCR_STPPCLK_Pos)
     
    #define USB_OTG_PCGCR_STPPCLK   USB_OTG_PCGCR_STPPCLK_Msk
     
    #define USB_OTG_PCGCR_GATEHCLK_Pos   (1U)
     
    #define USB_OTG_PCGCR_GATEHCLK_Msk   (0x1UL << USB_OTG_PCGCR_GATEHCLK_Pos)
     
    #define USB_OTG_PCGCR_GATEHCLK   USB_OTG_PCGCR_GATEHCLK_Msk
     
    #define USB_OTG_PCGCR_PHYSUSP_Pos   (4U)
     
    #define USB_OTG_PCGCR_PHYSUSP_Msk   (0x1UL << USB_OTG_PCGCR_PHYSUSP_Pos)
     
    #define USB_OTG_PCGCR_PHYSUSP   USB_OTG_PCGCR_PHYSUSP_Msk
     
    #define USB_OTG_GOTGINT_SEDET_Pos   (2U)
     
    #define USB_OTG_GOTGINT_SEDET_Msk   (0x1UL << USB_OTG_GOTGINT_SEDET_Pos)
     
    #define USB_OTG_GOTGINT_SEDET   USB_OTG_GOTGINT_SEDET_Msk
     
    #define USB_OTG_GOTGINT_SRSSCHG_Pos   (8U)
     
    #define USB_OTG_GOTGINT_SRSSCHG_Msk   (0x1UL << USB_OTG_GOTGINT_SRSSCHG_Pos)
     
    #define USB_OTG_GOTGINT_SRSSCHG   USB_OTG_GOTGINT_SRSSCHG_Msk
     
    #define USB_OTG_GOTGINT_HNSSCHG_Pos   (9U)
     
    #define USB_OTG_GOTGINT_HNSSCHG_Msk   (0x1UL << USB_OTG_GOTGINT_HNSSCHG_Pos)
     
    #define USB_OTG_GOTGINT_HNSSCHG   USB_OTG_GOTGINT_HNSSCHG_Msk
     
    #define USB_OTG_GOTGINT_HNGDET_Pos   (17U)
     
    #define USB_OTG_GOTGINT_HNGDET_Msk   (0x1UL << USB_OTG_GOTGINT_HNGDET_Pos)
     
    #define USB_OTG_GOTGINT_HNGDET   USB_OTG_GOTGINT_HNGDET_Msk
     
    #define USB_OTG_GOTGINT_ADTOCHG_Pos   (18U)
     
    #define USB_OTG_GOTGINT_ADTOCHG_Msk   (0x1UL << USB_OTG_GOTGINT_ADTOCHG_Pos)
     
    #define USB_OTG_GOTGINT_ADTOCHG   USB_OTG_GOTGINT_ADTOCHG_Msk
     
    #define USB_OTG_GOTGINT_DBCDNE_Pos   (19U)
     
    #define USB_OTG_GOTGINT_DBCDNE_Msk   (0x1UL << USB_OTG_GOTGINT_DBCDNE_Pos)
     
    #define USB_OTG_GOTGINT_DBCDNE   USB_OTG_GOTGINT_DBCDNE_Msk
     
    #define USB_OTG_DCTL_RWUSIG_Pos   (0U)
     
    #define USB_OTG_DCTL_RWUSIG_Msk   (0x1UL << USB_OTG_DCTL_RWUSIG_Pos)
     
    #define USB_OTG_DCTL_RWUSIG   USB_OTG_DCTL_RWUSIG_Msk
     
    #define USB_OTG_DCTL_SDIS_Pos   (1U)
     
    #define USB_OTG_DCTL_SDIS_Msk   (0x1UL << USB_OTG_DCTL_SDIS_Pos)
     
    #define USB_OTG_DCTL_SDIS   USB_OTG_DCTL_SDIS_Msk
     
    #define USB_OTG_DCTL_GINSTS_Pos   (2U)
     
    #define USB_OTG_DCTL_GINSTS_Msk   (0x1UL << USB_OTG_DCTL_GINSTS_Pos)
     
    #define USB_OTG_DCTL_GINSTS   USB_OTG_DCTL_GINSTS_Msk
     
    #define USB_OTG_DCTL_GONSTS_Pos   (3U)
     
    #define USB_OTG_DCTL_GONSTS_Msk   (0x1UL << USB_OTG_DCTL_GONSTS_Pos)
     
    #define USB_OTG_DCTL_GONSTS   USB_OTG_DCTL_GONSTS_Msk
     
    #define USB_OTG_DCTL_TCTL_Pos   (4U)
     
    #define USB_OTG_DCTL_TCTL_Msk   (0x7UL << USB_OTG_DCTL_TCTL_Pos)
     
    #define USB_OTG_DCTL_TCTL   USB_OTG_DCTL_TCTL_Msk
     
    #define USB_OTG_DCTL_TCTL_0   (0x1UL << USB_OTG_DCTL_TCTL_Pos)
     
    #define USB_OTG_DCTL_TCTL_1   (0x2UL << USB_OTG_DCTL_TCTL_Pos)
     
    #define USB_OTG_DCTL_TCTL_2   (0x4UL << USB_OTG_DCTL_TCTL_Pos)
     
    #define USB_OTG_DCTL_SGINAK_Pos   (7U)
     
    #define USB_OTG_DCTL_SGINAK_Msk   (0x1UL << USB_OTG_DCTL_SGINAK_Pos)
     
    #define USB_OTG_DCTL_SGINAK   USB_OTG_DCTL_SGINAK_Msk
     
    #define USB_OTG_DCTL_CGINAK_Pos   (8U)
     
    #define USB_OTG_DCTL_CGINAK_Msk   (0x1UL << USB_OTG_DCTL_CGINAK_Pos)
     
    #define USB_OTG_DCTL_CGINAK   USB_OTG_DCTL_CGINAK_Msk
     
    #define USB_OTG_DCTL_SGONAK_Pos   (9U)
     
    #define USB_OTG_DCTL_SGONAK_Msk   (0x1UL << USB_OTG_DCTL_SGONAK_Pos)
     
    #define USB_OTG_DCTL_SGONAK   USB_OTG_DCTL_SGONAK_Msk
     
    #define USB_OTG_DCTL_CGONAK_Pos   (10U)
     
    #define USB_OTG_DCTL_CGONAK_Msk   (0x1UL << USB_OTG_DCTL_CGONAK_Pos)
     
    #define USB_OTG_DCTL_CGONAK   USB_OTG_DCTL_CGONAK_Msk
     
    #define USB_OTG_DCTL_POPRGDNE_Pos   (11U)
     
    #define USB_OTG_DCTL_POPRGDNE_Msk   (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos)
     
    #define USB_OTG_DCTL_POPRGDNE   USB_OTG_DCTL_POPRGDNE_Msk
     
    #define USB_OTG_HFIR_FRIVL_Pos   (0U)
     
    #define USB_OTG_HFIR_FRIVL_Msk   (0xFFFFUL << USB_OTG_HFIR_FRIVL_Pos)
     
    #define USB_OTG_HFIR_FRIVL   USB_OTG_HFIR_FRIVL_Msk
     
    #define USB_OTG_HFNUM_FRNUM_Pos   (0U)
     
    #define USB_OTG_HFNUM_FRNUM_Msk   (0xFFFFUL << USB_OTG_HFNUM_FRNUM_Pos)
     
    #define USB_OTG_HFNUM_FRNUM   USB_OTG_HFNUM_FRNUM_Msk
     
    #define USB_OTG_HFNUM_FTREM_Pos   (16U)
     
    #define USB_OTG_HFNUM_FTREM_Msk   (0xFFFFUL << USB_OTG_HFNUM_FTREM_Pos)
     
    #define USB_OTG_HFNUM_FTREM   USB_OTG_HFNUM_FTREM_Msk
     
    #define USB_OTG_DSTS_SUSPSTS_Pos   (0U)
     
    #define USB_OTG_DSTS_SUSPSTS_Msk   (0x1UL << USB_OTG_DSTS_SUSPSTS_Pos)
     
    #define USB_OTG_DSTS_SUSPSTS   USB_OTG_DSTS_SUSPSTS_Msk
     
    #define USB_OTG_DSTS_ENUMSPD_Pos   (1U)
     
    #define USB_OTG_DSTS_ENUMSPD_Msk   (0x3UL << USB_OTG_DSTS_ENUMSPD_Pos)
     
    #define USB_OTG_DSTS_ENUMSPD   USB_OTG_DSTS_ENUMSPD_Msk
     
    #define USB_OTG_DSTS_ENUMSPD_0   (0x1UL << USB_OTG_DSTS_ENUMSPD_Pos)
     
    #define USB_OTG_DSTS_ENUMSPD_1   (0x2UL << USB_OTG_DSTS_ENUMSPD_Pos)
     
    #define USB_OTG_DSTS_EERR_Pos   (3U)
     
    #define USB_OTG_DSTS_EERR_Msk   (0x1UL << USB_OTG_DSTS_EERR_Pos)
     
    #define USB_OTG_DSTS_EERR   USB_OTG_DSTS_EERR_Msk
     
    #define USB_OTG_DSTS_FNSOF_Pos   (8U)
     
    #define USB_OTG_DSTS_FNSOF_Msk   (0x3FFFUL << USB_OTG_DSTS_FNSOF_Pos)
     
    #define USB_OTG_DSTS_FNSOF   USB_OTG_DSTS_FNSOF_Msk
     
    #define USB_OTG_GAHBCFG_GINT_Pos   (0U)
     
    #define USB_OTG_GAHBCFG_GINT_Msk   (0x1UL << USB_OTG_GAHBCFG_GINT_Pos)
     
    #define USB_OTG_GAHBCFG_GINT   USB_OTG_GAHBCFG_GINT_Msk
     
    #define USB_OTG_GAHBCFG_HBSTLEN_Pos   (1U)
     
    #define USB_OTG_GAHBCFG_HBSTLEN_Msk   (0xFUL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
     
    #define USB_OTG_GAHBCFG_HBSTLEN   USB_OTG_GAHBCFG_HBSTLEN_Msk
     
    #define USB_OTG_GAHBCFG_HBSTLEN_0   (0x0UL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
     
    #define USB_OTG_GAHBCFG_HBSTLEN_1   (0x1UL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
     
    #define USB_OTG_GAHBCFG_HBSTLEN_2   (0x3UL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
     
    #define USB_OTG_GAHBCFG_HBSTLEN_3   (0x5UL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
     
    #define USB_OTG_GAHBCFG_HBSTLEN_4   (0x7UL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
     
    #define USB_OTG_GAHBCFG_DMAEN_Pos   (5U)
     
    #define USB_OTG_GAHBCFG_DMAEN_Msk   (0x1UL << USB_OTG_GAHBCFG_DMAEN_Pos)
     
    #define USB_OTG_GAHBCFG_DMAEN   USB_OTG_GAHBCFG_DMAEN_Msk
     
    #define USB_OTG_GAHBCFG_TXFELVL_Pos   (7U)
     
    #define USB_OTG_GAHBCFG_TXFELVL_Msk   (0x1UL << USB_OTG_GAHBCFG_TXFELVL_Pos)
     
    #define USB_OTG_GAHBCFG_TXFELVL   USB_OTG_GAHBCFG_TXFELVL_Msk
     
    #define USB_OTG_GAHBCFG_PTXFELVL_Pos   (8U)
     
    #define USB_OTG_GAHBCFG_PTXFELVL_Msk   (0x1UL << USB_OTG_GAHBCFG_PTXFELVL_Pos)
     
    #define USB_OTG_GAHBCFG_PTXFELVL   USB_OTG_GAHBCFG_PTXFELVL_Msk
     
    #define USB_OTG_GUSBCFG_TOCAL_Pos   (0U)
     
    #define USB_OTG_GUSBCFG_TOCAL_Msk   (0x7UL << USB_OTG_GUSBCFG_TOCAL_Pos)
     
    #define USB_OTG_GUSBCFG_TOCAL   USB_OTG_GUSBCFG_TOCAL_Msk
     
    #define USB_OTG_GUSBCFG_TOCAL_0   (0x1UL << USB_OTG_GUSBCFG_TOCAL_Pos)
     
    #define USB_OTG_GUSBCFG_TOCAL_1   (0x2UL << USB_OTG_GUSBCFG_TOCAL_Pos)
     
    #define USB_OTG_GUSBCFG_TOCAL_2   (0x4UL << USB_OTG_GUSBCFG_TOCAL_Pos)
     
    #define USB_OTG_GUSBCFG_PHYSEL_Pos   (6U)
     
    #define USB_OTG_GUSBCFG_PHYSEL_Msk   (0x1UL << USB_OTG_GUSBCFG_PHYSEL_Pos)
     
    #define USB_OTG_GUSBCFG_PHYSEL   USB_OTG_GUSBCFG_PHYSEL_Msk
     
    #define USB_OTG_GUSBCFG_SRPCAP_Pos   (8U)
     
    #define USB_OTG_GUSBCFG_SRPCAP_Msk   (0x1UL << USB_OTG_GUSBCFG_SRPCAP_Pos)
     
    #define USB_OTG_GUSBCFG_SRPCAP   USB_OTG_GUSBCFG_SRPCAP_Msk
     
    #define USB_OTG_GUSBCFG_HNPCAP_Pos   (9U)
     
    #define USB_OTG_GUSBCFG_HNPCAP_Msk   (0x1UL << USB_OTG_GUSBCFG_HNPCAP_Pos)
     
    #define USB_OTG_GUSBCFG_HNPCAP   USB_OTG_GUSBCFG_HNPCAP_Msk
     
    #define USB_OTG_GUSBCFG_TRDT_Pos   (10U)
     
    #define USB_OTG_GUSBCFG_TRDT_Msk   (0xFUL << USB_OTG_GUSBCFG_TRDT_Pos)
     
    #define USB_OTG_GUSBCFG_TRDT   USB_OTG_GUSBCFG_TRDT_Msk
     
    #define USB_OTG_GUSBCFG_TRDT_0   (0x1UL << USB_OTG_GUSBCFG_TRDT_Pos)
     
    #define USB_OTG_GUSBCFG_TRDT_1   (0x2UL << USB_OTG_GUSBCFG_TRDT_Pos)
     
    #define USB_OTG_GUSBCFG_TRDT_2   (0x4UL << USB_OTG_GUSBCFG_TRDT_Pos)
     
    #define USB_OTG_GUSBCFG_TRDT_3   (0x8UL << USB_OTG_GUSBCFG_TRDT_Pos)
     
    #define USB_OTG_GUSBCFG_PHYLPCS_Pos   (15U)
     
    #define USB_OTG_GUSBCFG_PHYLPCS_Msk   (0x1UL << USB_OTG_GUSBCFG_PHYLPCS_Pos)
     
    #define USB_OTG_GUSBCFG_PHYLPCS   USB_OTG_GUSBCFG_PHYLPCS_Msk
     
    #define USB_OTG_GUSBCFG_ULPIFSLS_Pos   (17U)
     
    #define USB_OTG_GUSBCFG_ULPIFSLS_Msk   (0x1UL << USB_OTG_GUSBCFG_ULPIFSLS_Pos)
     
    #define USB_OTG_GUSBCFG_ULPIFSLS   USB_OTG_GUSBCFG_ULPIFSLS_Msk
     
    #define USB_OTG_GUSBCFG_ULPIAR_Pos   (18U)
     
    #define USB_OTG_GUSBCFG_ULPIAR_Msk   (0x1UL << USB_OTG_GUSBCFG_ULPIAR_Pos)
     
    #define USB_OTG_GUSBCFG_ULPIAR   USB_OTG_GUSBCFG_ULPIAR_Msk
     
    #define USB_OTG_GUSBCFG_ULPICSM_Pos   (19U)
     
    #define USB_OTG_GUSBCFG_ULPICSM_Msk   (0x1UL << USB_OTG_GUSBCFG_ULPICSM_Pos)
     
    #define USB_OTG_GUSBCFG_ULPICSM   USB_OTG_GUSBCFG_ULPICSM_Msk
     
    #define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos   (20U)
     
    #define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk   (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos)
     
    #define USB_OTG_GUSBCFG_ULPIEVBUSD   USB_OTG_GUSBCFG_ULPIEVBUSD_Msk
     
    #define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos   (21U)
     
    #define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk   (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos)
     
    #define USB_OTG_GUSBCFG_ULPIEVBUSI   USB_OTG_GUSBCFG_ULPIEVBUSI_Msk
     
    #define USB_OTG_GUSBCFG_TSDPS_Pos   (22U)
     
    #define USB_OTG_GUSBCFG_TSDPS_Msk   (0x1UL << USB_OTG_GUSBCFG_TSDPS_Pos)
     
    #define USB_OTG_GUSBCFG_TSDPS   USB_OTG_GUSBCFG_TSDPS_Msk
     
    #define USB_OTG_GUSBCFG_PCCI_Pos   (23U)
     
    #define USB_OTG_GUSBCFG_PCCI_Msk   (0x1UL << USB_OTG_GUSBCFG_PCCI_Pos)
     
    #define USB_OTG_GUSBCFG_PCCI   USB_OTG_GUSBCFG_PCCI_Msk
     
    #define USB_OTG_GUSBCFG_PTCI_Pos   (24U)
     
    #define USB_OTG_GUSBCFG_PTCI_Msk   (0x1UL << USB_OTG_GUSBCFG_PTCI_Pos)
     
    #define USB_OTG_GUSBCFG_PTCI   USB_OTG_GUSBCFG_PTCI_Msk
     
    #define USB_OTG_GUSBCFG_ULPIIPD_Pos   (25U)
     
    #define USB_OTG_GUSBCFG_ULPIIPD_Msk   (0x1UL << USB_OTG_GUSBCFG_ULPIIPD_Pos)
     
    #define USB_OTG_GUSBCFG_ULPIIPD   USB_OTG_GUSBCFG_ULPIIPD_Msk
     
    #define USB_OTG_GUSBCFG_FHMOD_Pos   (29U)
     
    #define USB_OTG_GUSBCFG_FHMOD_Msk   (0x1UL << USB_OTG_GUSBCFG_FHMOD_Pos)
     
    #define USB_OTG_GUSBCFG_FHMOD   USB_OTG_GUSBCFG_FHMOD_Msk
     
    #define USB_OTG_GUSBCFG_FDMOD_Pos   (30U)
     
    #define USB_OTG_GUSBCFG_FDMOD_Msk   (0x1UL << USB_OTG_GUSBCFG_FDMOD_Pos)
     
    #define USB_OTG_GUSBCFG_FDMOD   USB_OTG_GUSBCFG_FDMOD_Msk
     
    #define USB_OTG_GUSBCFG_CTXPKT_Pos   (31U)
     
    #define USB_OTG_GUSBCFG_CTXPKT_Msk   (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos)
     
    #define USB_OTG_GUSBCFG_CTXPKT   USB_OTG_GUSBCFG_CTXPKT_Msk
     
    #define USB_OTG_GRSTCTL_CSRST_Pos   (0U)
     
    #define USB_OTG_GRSTCTL_CSRST_Msk   (0x1UL << USB_OTG_GRSTCTL_CSRST_Pos)
     
    #define USB_OTG_GRSTCTL_CSRST   USB_OTG_GRSTCTL_CSRST_Msk
     
    #define USB_OTG_GRSTCTL_HSRST_Pos   (1U)
     
    #define USB_OTG_GRSTCTL_HSRST_Msk   (0x1UL << USB_OTG_GRSTCTL_HSRST_Pos)
     
    #define USB_OTG_GRSTCTL_HSRST   USB_OTG_GRSTCTL_HSRST_Msk
     
    #define USB_OTG_GRSTCTL_FCRST_Pos   (2U)
     
    #define USB_OTG_GRSTCTL_FCRST_Msk   (0x1UL << USB_OTG_GRSTCTL_FCRST_Pos)
     
    #define USB_OTG_GRSTCTL_FCRST   USB_OTG_GRSTCTL_FCRST_Msk
     
    #define USB_OTG_GRSTCTL_RXFFLSH_Pos   (4U)
     
    #define USB_OTG_GRSTCTL_RXFFLSH_Msk   (0x1UL << USB_OTG_GRSTCTL_RXFFLSH_Pos)
     
    #define USB_OTG_GRSTCTL_RXFFLSH   USB_OTG_GRSTCTL_RXFFLSH_Msk
     
    #define USB_OTG_GRSTCTL_TXFFLSH_Pos   (5U)
     
    #define USB_OTG_GRSTCTL_TXFFLSH_Msk   (0x1UL << USB_OTG_GRSTCTL_TXFFLSH_Pos)
     
    #define USB_OTG_GRSTCTL_TXFFLSH   USB_OTG_GRSTCTL_TXFFLSH_Msk
     
    #define USB_OTG_GRSTCTL_TXFNUM_Pos   (6U)
     
    #define USB_OTG_GRSTCTL_TXFNUM_Msk   (0x1FUL << USB_OTG_GRSTCTL_TXFNUM_Pos)
     
    #define USB_OTG_GRSTCTL_TXFNUM   USB_OTG_GRSTCTL_TXFNUM_Msk
     
    #define USB_OTG_GRSTCTL_TXFNUM_0   (0x01UL << USB_OTG_GRSTCTL_TXFNUM_Pos)
     
    #define USB_OTG_GRSTCTL_TXFNUM_1   (0x02UL << USB_OTG_GRSTCTL_TXFNUM_Pos)
     
    #define USB_OTG_GRSTCTL_TXFNUM_2   (0x04UL << USB_OTG_GRSTCTL_TXFNUM_Pos)
     
    #define USB_OTG_GRSTCTL_TXFNUM_3   (0x08UL << USB_OTG_GRSTCTL_TXFNUM_Pos)
     
    #define USB_OTG_GRSTCTL_TXFNUM_4   (0x10UL << USB_OTG_GRSTCTL_TXFNUM_Pos)
     
    #define USB_OTG_GRSTCTL_DMAREQ_Pos   (30U)
     
    #define USB_OTG_GRSTCTL_DMAREQ_Msk   (0x1UL << USB_OTG_GRSTCTL_DMAREQ_Pos)
     
    #define USB_OTG_GRSTCTL_DMAREQ   USB_OTG_GRSTCTL_DMAREQ_Msk
     
    #define USB_OTG_GRSTCTL_AHBIDL_Pos   (31U)
     
    #define USB_OTG_GRSTCTL_AHBIDL_Msk   (0x1UL << USB_OTG_GRSTCTL_AHBIDL_Pos)
     
    #define USB_OTG_GRSTCTL_AHBIDL   USB_OTG_GRSTCTL_AHBIDL_Msk
     
    #define USB_OTG_DIEPMSK_XFRCM_Pos   (0U)
     
    #define USB_OTG_DIEPMSK_XFRCM_Msk   (0x1UL << USB_OTG_DIEPMSK_XFRCM_Pos)
     
    #define USB_OTG_DIEPMSK_XFRCM   USB_OTG_DIEPMSK_XFRCM_Msk
     
    #define USB_OTG_DIEPMSK_EPDM_Pos   (1U)
     
    #define USB_OTG_DIEPMSK_EPDM_Msk   (0x1UL << USB_OTG_DIEPMSK_EPDM_Pos)
     
    #define USB_OTG_DIEPMSK_EPDM   USB_OTG_DIEPMSK_EPDM_Msk
     
    #define USB_OTG_DIEPMSK_TOM_Pos   (3U)
     
    #define USB_OTG_DIEPMSK_TOM_Msk   (0x1UL << USB_OTG_DIEPMSK_TOM_Pos)
     
    #define USB_OTG_DIEPMSK_TOM   USB_OTG_DIEPMSK_TOM_Msk
     
    #define USB_OTG_DIEPMSK_ITTXFEMSK_Pos   (4U)
     
    #define USB_OTG_DIEPMSK_ITTXFEMSK_Msk   (0x1UL << USB_OTG_DIEPMSK_ITTXFEMSK_Pos)
     
    #define USB_OTG_DIEPMSK_ITTXFEMSK   USB_OTG_DIEPMSK_ITTXFEMSK_Msk
     
    #define USB_OTG_DIEPMSK_INEPNMM_Pos   (5U)
     
    #define USB_OTG_DIEPMSK_INEPNMM_Msk   (0x1UL << USB_OTG_DIEPMSK_INEPNMM_Pos)
     
    #define USB_OTG_DIEPMSK_INEPNMM   USB_OTG_DIEPMSK_INEPNMM_Msk
     
    #define USB_OTG_DIEPMSK_INEPNEM_Pos   (6U)
     
    #define USB_OTG_DIEPMSK_INEPNEM_Msk   (0x1UL << USB_OTG_DIEPMSK_INEPNEM_Pos)
     
    #define USB_OTG_DIEPMSK_INEPNEM   USB_OTG_DIEPMSK_INEPNEM_Msk
     
    #define USB_OTG_DIEPMSK_TXFURM_Pos   (8U)
     
    #define USB_OTG_DIEPMSK_TXFURM_Msk   (0x1UL << USB_OTG_DIEPMSK_TXFURM_Pos)
     
    #define USB_OTG_DIEPMSK_TXFURM   USB_OTG_DIEPMSK_TXFURM_Msk
     
    #define USB_OTG_DIEPMSK_BIM_Pos   (9U)
     
    #define USB_OTG_DIEPMSK_BIM_Msk   (0x1UL << USB_OTG_DIEPMSK_BIM_Pos)
     
    #define USB_OTG_DIEPMSK_BIM   USB_OTG_DIEPMSK_BIM_Msk
     
    #define USB_OTG_HPTXSTS_PTXFSAVL_Pos   (0U)
     
    #define USB_OTG_HPTXSTS_PTXFSAVL_Msk   (0xFFFFUL << USB_OTG_HPTXSTS_PTXFSAVL_Pos)
     
    #define USB_OTG_HPTXSTS_PTXFSAVL   USB_OTG_HPTXSTS_PTXFSAVL_Msk
     
    #define USB_OTG_HPTXSTS_PTXQSAV_Pos   (16U)
     
    #define USB_OTG_HPTXSTS_PTXQSAV_Msk   (0xFFUL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
     
    #define USB_OTG_HPTXSTS_PTXQSAV   USB_OTG_HPTXSTS_PTXQSAV_Msk
     
    #define USB_OTG_HPTXSTS_PTXQSAV_0   (0x01UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
     
    #define USB_OTG_HPTXSTS_PTXQSAV_1   (0x02UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
     
    #define USB_OTG_HPTXSTS_PTXQSAV_2   (0x04UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
     
    #define USB_OTG_HPTXSTS_PTXQSAV_3   (0x08UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
     
    #define USB_OTG_HPTXSTS_PTXQSAV_4   (0x10UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
     
    #define USB_OTG_HPTXSTS_PTXQSAV_5   (0x20UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
     
    #define USB_OTG_HPTXSTS_PTXQSAV_6   (0x40UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
     
    #define USB_OTG_HPTXSTS_PTXQSAV_7   (0x80UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
     
    #define USB_OTG_HPTXSTS_PTXQTOP_Pos   (24U)
     
    #define USB_OTG_HPTXSTS_PTXQTOP_Msk   (0xFFUL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
     
    #define USB_OTG_HPTXSTS_PTXQTOP   USB_OTG_HPTXSTS_PTXQTOP_Msk
     
    #define USB_OTG_HPTXSTS_PTXQTOP_0   (0x01UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
     
    #define USB_OTG_HPTXSTS_PTXQTOP_1   (0x02UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
     
    #define USB_OTG_HPTXSTS_PTXQTOP_2   (0x04UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
     
    #define USB_OTG_HPTXSTS_PTXQTOP_3   (0x08UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
     
    #define USB_OTG_HPTXSTS_PTXQTOP_4   (0x10UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
     
    #define USB_OTG_HPTXSTS_PTXQTOP_5   (0x20UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
     
    #define USB_OTG_HPTXSTS_PTXQTOP_6   (0x40UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
     
    #define USB_OTG_HPTXSTS_PTXQTOP_7   (0x80UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
     
    #define USB_OTG_HAINT_HAINT_Pos   (0U)
     
    #define USB_OTG_HAINT_HAINT_Msk   (0xFFFFUL << USB_OTG_HAINT_HAINT_Pos)
     
    #define USB_OTG_HAINT_HAINT   USB_OTG_HAINT_HAINT_Msk
     
    #define USB_OTG_DOEPMSK_XFRCM_Pos   (0U)
     
    #define USB_OTG_DOEPMSK_XFRCM_Msk   (0x1UL << USB_OTG_DOEPMSK_XFRCM_Pos)
     
    #define USB_OTG_DOEPMSK_XFRCM   USB_OTG_DOEPMSK_XFRCM_Msk
     
    #define USB_OTG_DOEPMSK_EPDM_Pos   (1U)
     
    #define USB_OTG_DOEPMSK_EPDM_Msk   (0x1UL << USB_OTG_DOEPMSK_EPDM_Pos)
     
    #define USB_OTG_DOEPMSK_EPDM   USB_OTG_DOEPMSK_EPDM_Msk
     
    #define USB_OTG_DOEPMSK_AHBERRM_Pos   (2U)
     
    #define USB_OTG_DOEPMSK_AHBERRM_Msk   (0x1UL << USB_OTG_DOEPMSK_AHBERRM_Pos)
     
    #define USB_OTG_DOEPMSK_AHBERRM   USB_OTG_DOEPMSK_AHBERRM_Msk
     
    #define USB_OTG_DOEPMSK_STUPM_Pos   (3U)
     
    #define USB_OTG_DOEPMSK_STUPM_Msk   (0x1UL << USB_OTG_DOEPMSK_STUPM_Pos)
     
    #define USB_OTG_DOEPMSK_STUPM   USB_OTG_DOEPMSK_STUPM_Msk
     
    #define USB_OTG_DOEPMSK_OTEPDM_Pos   (4U)
     
    #define USB_OTG_DOEPMSK_OTEPDM_Msk   (0x1UL << USB_OTG_DOEPMSK_OTEPDM_Pos)
     
    #define USB_OTG_DOEPMSK_OTEPDM   USB_OTG_DOEPMSK_OTEPDM_Msk
     
    #define USB_OTG_DOEPMSK_OTEPSPRM_Pos   (5U)
     
    #define USB_OTG_DOEPMSK_OTEPSPRM_Msk   (0x1UL << USB_OTG_DOEPMSK_OTEPSPRM_Pos)
     
    #define USB_OTG_DOEPMSK_OTEPSPRM   USB_OTG_DOEPMSK_OTEPSPRM_Msk
     
    #define USB_OTG_DOEPMSK_B2BSTUP_Pos   (6U)
     
    #define USB_OTG_DOEPMSK_B2BSTUP_Msk   (0x1UL << USB_OTG_DOEPMSK_B2BSTUP_Pos)
     
    #define USB_OTG_DOEPMSK_B2BSTUP   USB_OTG_DOEPMSK_B2BSTUP_Msk
     
    #define USB_OTG_DOEPMSK_OPEM_Pos   (8U)
     
    #define USB_OTG_DOEPMSK_OPEM_Msk   (0x1UL << USB_OTG_DOEPMSK_OPEM_Pos)
     
    #define USB_OTG_DOEPMSK_OPEM   USB_OTG_DOEPMSK_OPEM_Msk
     
    #define USB_OTG_DOEPMSK_BOIM_Pos   (9U)
     
    #define USB_OTG_DOEPMSK_BOIM_Msk   (0x1UL << USB_OTG_DOEPMSK_BOIM_Pos)
     
    #define USB_OTG_DOEPMSK_BOIM   USB_OTG_DOEPMSK_BOIM_Msk
     
    #define USB_OTG_DOEPMSK_BERRM_Pos   (12U)
     
    #define USB_OTG_DOEPMSK_BERRM_Msk   (0x1UL << USB_OTG_DOEPMSK_BERRM_Pos)
     
    #define USB_OTG_DOEPMSK_BERRM   USB_OTG_DOEPMSK_BERRM_Msk
     
    #define USB_OTG_DOEPMSK_NAKM_Pos   (13U)
     
    #define USB_OTG_DOEPMSK_NAKM_Msk   (0x1UL << USB_OTG_DOEPMSK_NAKM_Pos)
     
    #define USB_OTG_DOEPMSK_NAKM   USB_OTG_DOEPMSK_NAKM_Msk
     
    #define USB_OTG_DOEPMSK_NYETM_Pos   (14U)
     
    #define USB_OTG_DOEPMSK_NYETM_Msk   (0x1UL << USB_OTG_DOEPMSK_NYETM_Pos)
     
    #define USB_OTG_DOEPMSK_NYETM   USB_OTG_DOEPMSK_NYETM_Msk
     
    #define USB_OTG_GINTSTS_CMOD_Pos   (0U)
     
    #define USB_OTG_GINTSTS_CMOD_Msk   (0x1UL << USB_OTG_GINTSTS_CMOD_Pos)
     
    #define USB_OTG_GINTSTS_CMOD   USB_OTG_GINTSTS_CMOD_Msk
     
    #define USB_OTG_GINTSTS_MMIS_Pos   (1U)
     
    #define USB_OTG_GINTSTS_MMIS_Msk   (0x1UL << USB_OTG_GINTSTS_MMIS_Pos)
     
    #define USB_OTG_GINTSTS_MMIS   USB_OTG_GINTSTS_MMIS_Msk
     
    #define USB_OTG_GINTSTS_OTGINT_Pos   (2U)
     
    #define USB_OTG_GINTSTS_OTGINT_Msk   (0x1UL << USB_OTG_GINTSTS_OTGINT_Pos)
     
    #define USB_OTG_GINTSTS_OTGINT   USB_OTG_GINTSTS_OTGINT_Msk
     
    #define USB_OTG_GINTSTS_SOF_Pos   (3U)
     
    #define USB_OTG_GINTSTS_SOF_Msk   (0x1UL << USB_OTG_GINTSTS_SOF_Pos)
     
    #define USB_OTG_GINTSTS_SOF   USB_OTG_GINTSTS_SOF_Msk
     
    #define USB_OTG_GINTSTS_RXFLVL_Pos   (4U)
     
    #define USB_OTG_GINTSTS_RXFLVL_Msk   (0x1UL << USB_OTG_GINTSTS_RXFLVL_Pos)
     
    #define USB_OTG_GINTSTS_RXFLVL   USB_OTG_GINTSTS_RXFLVL_Msk
     
    #define USB_OTG_GINTSTS_NPTXFE_Pos   (5U)
     
    #define USB_OTG_GINTSTS_NPTXFE_Msk   (0x1UL << USB_OTG_GINTSTS_NPTXFE_Pos)
     
    #define USB_OTG_GINTSTS_NPTXFE   USB_OTG_GINTSTS_NPTXFE_Msk
     
    #define USB_OTG_GINTSTS_GINAKEFF_Pos   (6U)
     
    #define USB_OTG_GINTSTS_GINAKEFF_Msk   (0x1UL << USB_OTG_GINTSTS_GINAKEFF_Pos)
     
    #define USB_OTG_GINTSTS_GINAKEFF   USB_OTG_GINTSTS_GINAKEFF_Msk
     
    #define USB_OTG_GINTSTS_BOUTNAKEFF_Pos   (7U)
     
    #define USB_OTG_GINTSTS_BOUTNAKEFF_Msk   (0x1UL << USB_OTG_GINTSTS_BOUTNAKEFF_Pos)
     
    #define USB_OTG_GINTSTS_BOUTNAKEFF   USB_OTG_GINTSTS_BOUTNAKEFF_Msk
     
    #define USB_OTG_GINTSTS_ESUSP_Pos   (10U)
     
    #define USB_OTG_GINTSTS_ESUSP_Msk   (0x1UL << USB_OTG_GINTSTS_ESUSP_Pos)
     
    #define USB_OTG_GINTSTS_ESUSP   USB_OTG_GINTSTS_ESUSP_Msk
     
    #define USB_OTG_GINTSTS_USBSUSP_Pos   (11U)
     
    #define USB_OTG_GINTSTS_USBSUSP_Msk   (0x1UL << USB_OTG_GINTSTS_USBSUSP_Pos)
     
    #define USB_OTG_GINTSTS_USBSUSP   USB_OTG_GINTSTS_USBSUSP_Msk
     
    #define USB_OTG_GINTSTS_USBRST_Pos   (12U)
     
    #define USB_OTG_GINTSTS_USBRST_Msk   (0x1UL << USB_OTG_GINTSTS_USBRST_Pos)
     
    #define USB_OTG_GINTSTS_USBRST   USB_OTG_GINTSTS_USBRST_Msk
     
    #define USB_OTG_GINTSTS_ENUMDNE_Pos   (13U)
     
    #define USB_OTG_GINTSTS_ENUMDNE_Msk   (0x1UL << USB_OTG_GINTSTS_ENUMDNE_Pos)
     
    #define USB_OTG_GINTSTS_ENUMDNE   USB_OTG_GINTSTS_ENUMDNE_Msk
     
    #define USB_OTG_GINTSTS_ISOODRP_Pos   (14U)
     
    #define USB_OTG_GINTSTS_ISOODRP_Msk   (0x1UL << USB_OTG_GINTSTS_ISOODRP_Pos)
     
    #define USB_OTG_GINTSTS_ISOODRP   USB_OTG_GINTSTS_ISOODRP_Msk
     
    #define USB_OTG_GINTSTS_EOPF_Pos   (15U)
     
    #define USB_OTG_GINTSTS_EOPF_Msk   (0x1UL << USB_OTG_GINTSTS_EOPF_Pos)
     
    #define USB_OTG_GINTSTS_EOPF   USB_OTG_GINTSTS_EOPF_Msk
     
    #define USB_OTG_GINTSTS_IEPINT_Pos   (18U)
     
    #define USB_OTG_GINTSTS_IEPINT_Msk   (0x1UL << USB_OTG_GINTSTS_IEPINT_Pos)
     
    #define USB_OTG_GINTSTS_IEPINT   USB_OTG_GINTSTS_IEPINT_Msk
     
    #define USB_OTG_GINTSTS_OEPINT_Pos   (19U)
     
    #define USB_OTG_GINTSTS_OEPINT_Msk   (0x1UL << USB_OTG_GINTSTS_OEPINT_Pos)
     
    #define USB_OTG_GINTSTS_OEPINT   USB_OTG_GINTSTS_OEPINT_Msk
     
    #define USB_OTG_GINTSTS_IISOIXFR_Pos   (20U)
     
    #define USB_OTG_GINTSTS_IISOIXFR_Msk   (0x1UL << USB_OTG_GINTSTS_IISOIXFR_Pos)
     
    #define USB_OTG_GINTSTS_IISOIXFR   USB_OTG_GINTSTS_IISOIXFR_Msk
     
    #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos   (21U)
     
    #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk   (0x1UL << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos)
     
    #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT   USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk
     
    #define USB_OTG_GINTSTS_DATAFSUSP_Pos   (22U)
     
    #define USB_OTG_GINTSTS_DATAFSUSP_Msk   (0x1UL << USB_OTG_GINTSTS_DATAFSUSP_Pos)
     
    #define USB_OTG_GINTSTS_DATAFSUSP   USB_OTG_GINTSTS_DATAFSUSP_Msk
     
    #define USB_OTG_GINTSTS_HPRTINT_Pos   (24U)
     
    #define USB_OTG_GINTSTS_HPRTINT_Msk   (0x1UL << USB_OTG_GINTSTS_HPRTINT_Pos)
     
    #define USB_OTG_GINTSTS_HPRTINT   USB_OTG_GINTSTS_HPRTINT_Msk
     
    #define USB_OTG_GINTSTS_HCINT_Pos   (25U)
     
    #define USB_OTG_GINTSTS_HCINT_Msk   (0x1UL << USB_OTG_GINTSTS_HCINT_Pos)
     
    #define USB_OTG_GINTSTS_HCINT   USB_OTG_GINTSTS_HCINT_Msk
     
    #define USB_OTG_GINTSTS_PTXFE_Pos   (26U)
     
    #define USB_OTG_GINTSTS_PTXFE_Msk   (0x1UL << USB_OTG_GINTSTS_PTXFE_Pos)
     
    #define USB_OTG_GINTSTS_PTXFE   USB_OTG_GINTSTS_PTXFE_Msk
     
    #define USB_OTG_GINTSTS_CIDSCHG_Pos   (28U)
     
    #define USB_OTG_GINTSTS_CIDSCHG_Msk   (0x1UL << USB_OTG_GINTSTS_CIDSCHG_Pos)
     
    #define USB_OTG_GINTSTS_CIDSCHG   USB_OTG_GINTSTS_CIDSCHG_Msk
     
    #define USB_OTG_GINTSTS_DISCINT_Pos   (29U)
     
    #define USB_OTG_GINTSTS_DISCINT_Msk   (0x1UL << USB_OTG_GINTSTS_DISCINT_Pos)
     
    #define USB_OTG_GINTSTS_DISCINT   USB_OTG_GINTSTS_DISCINT_Msk
     
    #define USB_OTG_GINTSTS_SRQINT_Pos   (30U)
     
    #define USB_OTG_GINTSTS_SRQINT_Msk   (0x1UL << USB_OTG_GINTSTS_SRQINT_Pos)
     
    #define USB_OTG_GINTSTS_SRQINT   USB_OTG_GINTSTS_SRQINT_Msk
     
    #define USB_OTG_GINTSTS_WKUINT_Pos   (31U)
     
    #define USB_OTG_GINTSTS_WKUINT_Msk   (0x1UL << USB_OTG_GINTSTS_WKUINT_Pos)
     
    #define USB_OTG_GINTSTS_WKUINT   USB_OTG_GINTSTS_WKUINT_Msk
     
    #define USB_OTG_GINTMSK_MMISM_Pos   (1U)
     
    #define USB_OTG_GINTMSK_MMISM_Msk   (0x1UL << USB_OTG_GINTMSK_MMISM_Pos)
     
    #define USB_OTG_GINTMSK_MMISM   USB_OTG_GINTMSK_MMISM_Msk
     
    #define USB_OTG_GINTMSK_OTGINT_Pos   (2U)
     
    #define USB_OTG_GINTMSK_OTGINT_Msk   (0x1UL << USB_OTG_GINTMSK_OTGINT_Pos)
     
    #define USB_OTG_GINTMSK_OTGINT   USB_OTG_GINTMSK_OTGINT_Msk
     
    #define USB_OTG_GINTMSK_SOFM_Pos   (3U)
     
    #define USB_OTG_GINTMSK_SOFM_Msk   (0x1UL << USB_OTG_GINTMSK_SOFM_Pos)
     
    #define USB_OTG_GINTMSK_SOFM   USB_OTG_GINTMSK_SOFM_Msk
     
    #define USB_OTG_GINTMSK_RXFLVLM_Pos   (4U)
     
    #define USB_OTG_GINTMSK_RXFLVLM_Msk   (0x1UL << USB_OTG_GINTMSK_RXFLVLM_Pos)
     
    #define USB_OTG_GINTMSK_RXFLVLM   USB_OTG_GINTMSK_RXFLVLM_Msk
     
    #define USB_OTG_GINTMSK_NPTXFEM_Pos   (5U)
     
    #define USB_OTG_GINTMSK_NPTXFEM_Msk   (0x1UL << USB_OTG_GINTMSK_NPTXFEM_Pos)
     
    #define USB_OTG_GINTMSK_NPTXFEM   USB_OTG_GINTMSK_NPTXFEM_Msk
     
    #define USB_OTG_GINTMSK_GINAKEFFM_Pos   (6U)
     
    #define USB_OTG_GINTMSK_GINAKEFFM_Msk   (0x1UL << USB_OTG_GINTMSK_GINAKEFFM_Pos)
     
    #define USB_OTG_GINTMSK_GINAKEFFM   USB_OTG_GINTMSK_GINAKEFFM_Msk
     
    #define USB_OTG_GINTMSK_GONAKEFFM_Pos   (7U)
     
    #define USB_OTG_GINTMSK_GONAKEFFM_Msk   (0x1UL << USB_OTG_GINTMSK_GONAKEFFM_Pos)
     
    #define USB_OTG_GINTMSK_GONAKEFFM   USB_OTG_GINTMSK_GONAKEFFM_Msk
     
    #define USB_OTG_GINTMSK_ESUSPM_Pos   (10U)
     
    #define USB_OTG_GINTMSK_ESUSPM_Msk   (0x1UL << USB_OTG_GINTMSK_ESUSPM_Pos)
     
    #define USB_OTG_GINTMSK_ESUSPM   USB_OTG_GINTMSK_ESUSPM_Msk
     
    #define USB_OTG_GINTMSK_USBSUSPM_Pos   (11U)
     
    #define USB_OTG_GINTMSK_USBSUSPM_Msk   (0x1UL << USB_OTG_GINTMSK_USBSUSPM_Pos)
     
    #define USB_OTG_GINTMSK_USBSUSPM   USB_OTG_GINTMSK_USBSUSPM_Msk
     
    #define USB_OTG_GINTMSK_USBRST_Pos   (12U)
     
    #define USB_OTG_GINTMSK_USBRST_Msk   (0x1UL << USB_OTG_GINTMSK_USBRST_Pos)
     
    #define USB_OTG_GINTMSK_USBRST   USB_OTG_GINTMSK_USBRST_Msk
     
    #define USB_OTG_GINTMSK_ENUMDNEM_Pos   (13U)
     
    #define USB_OTG_GINTMSK_ENUMDNEM_Msk   (0x1UL << USB_OTG_GINTMSK_ENUMDNEM_Pos)
     
    #define USB_OTG_GINTMSK_ENUMDNEM   USB_OTG_GINTMSK_ENUMDNEM_Msk
     
    #define USB_OTG_GINTMSK_ISOODRPM_Pos   (14U)
     
    #define USB_OTG_GINTMSK_ISOODRPM_Msk   (0x1UL << USB_OTG_GINTMSK_ISOODRPM_Pos)
     
    #define USB_OTG_GINTMSK_ISOODRPM   USB_OTG_GINTMSK_ISOODRPM_Msk
     
    #define USB_OTG_GINTMSK_EOPFM_Pos   (15U)
     
    #define USB_OTG_GINTMSK_EOPFM_Msk   (0x1UL << USB_OTG_GINTMSK_EOPFM_Pos)
     
    #define USB_OTG_GINTMSK_EOPFM   USB_OTG_GINTMSK_EOPFM_Msk
     
    #define USB_OTG_GINTMSK_EPMISM_Pos   (17U)
     
    #define USB_OTG_GINTMSK_EPMISM_Msk   (0x1UL << USB_OTG_GINTMSK_EPMISM_Pos)
     
    #define USB_OTG_GINTMSK_EPMISM   USB_OTG_GINTMSK_EPMISM_Msk
     
    #define USB_OTG_GINTMSK_IEPINT_Pos   (18U)
     
    #define USB_OTG_GINTMSK_IEPINT_Msk   (0x1UL << USB_OTG_GINTMSK_IEPINT_Pos)
     
    #define USB_OTG_GINTMSK_IEPINT   USB_OTG_GINTMSK_IEPINT_Msk
     
    #define USB_OTG_GINTMSK_OEPINT_Pos   (19U)
     
    #define USB_OTG_GINTMSK_OEPINT_Msk   (0x1UL << USB_OTG_GINTMSK_OEPINT_Pos)
     
    #define USB_OTG_GINTMSK_OEPINT   USB_OTG_GINTMSK_OEPINT_Msk
     
    #define USB_OTG_GINTMSK_IISOIXFRM_Pos   (20U)
     
    #define USB_OTG_GINTMSK_IISOIXFRM_Msk   (0x1UL << USB_OTG_GINTMSK_IISOIXFRM_Pos)
     
    #define USB_OTG_GINTMSK_IISOIXFRM   USB_OTG_GINTMSK_IISOIXFRM_Msk
     
    #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos   (21U)
     
    #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk   (0x1UL << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos)
     
    #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM   USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk
     
    #define USB_OTG_GINTMSK_FSUSPM_Pos   (22U)
     
    #define USB_OTG_GINTMSK_FSUSPM_Msk   (0x1UL << USB_OTG_GINTMSK_FSUSPM_Pos)
     
    #define USB_OTG_GINTMSK_FSUSPM   USB_OTG_GINTMSK_FSUSPM_Msk
     
    #define USB_OTG_GINTMSK_PRTIM_Pos   (24U)
     
    #define USB_OTG_GINTMSK_PRTIM_Msk   (0x1UL << USB_OTG_GINTMSK_PRTIM_Pos)
     
    #define USB_OTG_GINTMSK_PRTIM   USB_OTG_GINTMSK_PRTIM_Msk
     
    #define USB_OTG_GINTMSK_HCIM_Pos   (25U)
     
    #define USB_OTG_GINTMSK_HCIM_Msk   (0x1UL << USB_OTG_GINTMSK_HCIM_Pos)
     
    #define USB_OTG_GINTMSK_HCIM   USB_OTG_GINTMSK_HCIM_Msk
     
    #define USB_OTG_GINTMSK_PTXFEM_Pos   (26U)
     
    #define USB_OTG_GINTMSK_PTXFEM_Msk   (0x1UL << USB_OTG_GINTMSK_PTXFEM_Pos)
     
    #define USB_OTG_GINTMSK_PTXFEM   USB_OTG_GINTMSK_PTXFEM_Msk
     
    #define USB_OTG_GINTMSK_CIDSCHGM_Pos   (28U)
     
    #define USB_OTG_GINTMSK_CIDSCHGM_Msk   (0x1UL << USB_OTG_GINTMSK_CIDSCHGM_Pos)
     
    #define USB_OTG_GINTMSK_CIDSCHGM   USB_OTG_GINTMSK_CIDSCHGM_Msk
     
    #define USB_OTG_GINTMSK_DISCINT_Pos   (29U)
     
    #define USB_OTG_GINTMSK_DISCINT_Msk   (0x1UL << USB_OTG_GINTMSK_DISCINT_Pos)
     
    #define USB_OTG_GINTMSK_DISCINT   USB_OTG_GINTMSK_DISCINT_Msk
     
    #define USB_OTG_GINTMSK_SRQIM_Pos   (30U)
     
    #define USB_OTG_GINTMSK_SRQIM_Msk   (0x1UL << USB_OTG_GINTMSK_SRQIM_Pos)
     
    #define USB_OTG_GINTMSK_SRQIM   USB_OTG_GINTMSK_SRQIM_Msk
     
    #define USB_OTG_GINTMSK_WUIM_Pos   (31U)
     
    #define USB_OTG_GINTMSK_WUIM_Msk   (0x1UL << USB_OTG_GINTMSK_WUIM_Pos)
     
    #define USB_OTG_GINTMSK_WUIM   USB_OTG_GINTMSK_WUIM_Msk
     
    #define USB_OTG_DAINT_IEPINT_Pos   (0U)
     
    #define USB_OTG_DAINT_IEPINT_Msk   (0xFFFFUL << USB_OTG_DAINT_IEPINT_Pos)
     
    #define USB_OTG_DAINT_IEPINT   USB_OTG_DAINT_IEPINT_Msk
     
    #define USB_OTG_DAINT_OEPINT_Pos   (16U)
     
    #define USB_OTG_DAINT_OEPINT_Msk   (0xFFFFUL << USB_OTG_DAINT_OEPINT_Pos)
     
    #define USB_OTG_DAINT_OEPINT   USB_OTG_DAINT_OEPINT_Msk
     
    #define USB_OTG_HAINTMSK_HAINTM_Pos   (0U)
     
    #define USB_OTG_HAINTMSK_HAINTM_Msk   (0xFFFFUL << USB_OTG_HAINTMSK_HAINTM_Pos)
     
    #define USB_OTG_HAINTMSK_HAINTM   USB_OTG_HAINTMSK_HAINTM_Msk
     
    #define USB_OTG_GRXSTSP_EPNUM_Pos   (0U)
     
    #define USB_OTG_GRXSTSP_EPNUM_Msk   (0xFUL << USB_OTG_GRXSTSP_EPNUM_Pos)
     
    #define USB_OTG_GRXSTSP_EPNUM   USB_OTG_GRXSTSP_EPNUM_Msk
     
    #define USB_OTG_GRXSTSP_BCNT_Pos   (4U)
     
    #define USB_OTG_GRXSTSP_BCNT_Msk   (0x7FFUL << USB_OTG_GRXSTSP_BCNT_Pos)
     
    #define USB_OTG_GRXSTSP_BCNT   USB_OTG_GRXSTSP_BCNT_Msk
     
    #define USB_OTG_GRXSTSP_DPID_Pos   (15U)
     
    #define USB_OTG_GRXSTSP_DPID_Msk   (0x3UL << USB_OTG_GRXSTSP_DPID_Pos)
     
    #define USB_OTG_GRXSTSP_DPID   USB_OTG_GRXSTSP_DPID_Msk
     
    #define USB_OTG_GRXSTSP_PKTSTS_Pos   (17U)
     
    #define USB_OTG_GRXSTSP_PKTSTS_Msk   (0xFUL << USB_OTG_GRXSTSP_PKTSTS_Pos)
     
    #define USB_OTG_GRXSTSP_PKTSTS   USB_OTG_GRXSTSP_PKTSTS_Msk
     
    #define USB_OTG_DAINTMSK_IEPM_Pos   (0U)
     
    #define USB_OTG_DAINTMSK_IEPM_Msk   (0xFFFFUL << USB_OTG_DAINTMSK_IEPM_Pos)
     
    #define USB_OTG_DAINTMSK_IEPM   USB_OTG_DAINTMSK_IEPM_Msk
     
    #define USB_OTG_DAINTMSK_OEPM_Pos   (16U)
     
    #define USB_OTG_DAINTMSK_OEPM_Msk   (0xFFFFUL << USB_OTG_DAINTMSK_OEPM_Pos)
     
    #define USB_OTG_DAINTMSK_OEPM   USB_OTG_DAINTMSK_OEPM_Msk
     
    #define USB_OTG_GRXFSIZ_RXFD_Pos   (0U)
     
    #define USB_OTG_GRXFSIZ_RXFD_Msk   (0xFFFFUL << USB_OTG_GRXFSIZ_RXFD_Pos)
     
    #define USB_OTG_GRXFSIZ_RXFD   USB_OTG_GRXFSIZ_RXFD_Msk
     
    #define USB_OTG_DVBUSDIS_VBUSDT_Pos   (0U)
     
    #define USB_OTG_DVBUSDIS_VBUSDT_Msk   (0xFFFFUL << USB_OTG_DVBUSDIS_VBUSDT_Pos)
     
    #define USB_OTG_DVBUSDIS_VBUSDT   USB_OTG_DVBUSDIS_VBUSDT_Msk
     
    #define USB_OTG_NPTXFSA_Pos   (0U)
     
    #define USB_OTG_NPTXFSA_Msk   (0xFFFFUL << USB_OTG_NPTXFSA_Pos)
     
    #define USB_OTG_NPTXFSA   USB_OTG_NPTXFSA_Msk
     
    #define USB_OTG_NPTXFD_Pos   (16U)
     
    #define USB_OTG_NPTXFD_Msk   (0xFFFFUL << USB_OTG_NPTXFD_Pos)
     
    #define USB_OTG_NPTXFD   USB_OTG_NPTXFD_Msk
     
    #define USB_OTG_TX0FSA_Pos   (0U)
     
    #define USB_OTG_TX0FSA_Msk   (0xFFFFUL << USB_OTG_TX0FSA_Pos)
     
    #define USB_OTG_TX0FSA   USB_OTG_TX0FSA_Msk
     
    #define USB_OTG_TX0FD_Pos   (16U)
     
    #define USB_OTG_TX0FD_Msk   (0xFFFFUL << USB_OTG_TX0FD_Pos)
     
    #define USB_OTG_TX0FD   USB_OTG_TX0FD_Msk
     
    #define USB_OTG_DVBUSPULSE_DVBUSP_Pos   (0U)
     
    #define USB_OTG_DVBUSPULSE_DVBUSP_Msk   (0xFFFUL << USB_OTG_DVBUSPULSE_DVBUSP_Pos)
     
    #define USB_OTG_DVBUSPULSE_DVBUSP   USB_OTG_DVBUSPULSE_DVBUSP_Msk
     
    #define USB_OTG_GNPTXSTS_NPTXFSAV_Pos   (0U)
     
    #define USB_OTG_GNPTXSTS_NPTXFSAV_Msk   (0xFFFFUL << USB_OTG_GNPTXSTS_NPTXFSAV_Pos)
     
    #define USB_OTG_GNPTXSTS_NPTXFSAV   USB_OTG_GNPTXSTS_NPTXFSAV_Msk
     
    #define USB_OTG_GNPTXSTS_NPTQXSAV_Pos   (16U)
     
    #define USB_OTG_GNPTXSTS_NPTQXSAV_Msk   (0xFFUL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
     
    #define USB_OTG_GNPTXSTS_NPTQXSAV   USB_OTG_GNPTXSTS_NPTQXSAV_Msk
     
    #define USB_OTG_GNPTXSTS_NPTQXSAV_0   (0x01UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
     
    #define USB_OTG_GNPTXSTS_NPTQXSAV_1   (0x02UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
     
    #define USB_OTG_GNPTXSTS_NPTQXSAV_2   (0x04UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
     
    #define USB_OTG_GNPTXSTS_NPTQXSAV_3   (0x08UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
     
    #define USB_OTG_GNPTXSTS_NPTQXSAV_4   (0x10UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
     
    #define USB_OTG_GNPTXSTS_NPTQXSAV_5   (0x20UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
     
    #define USB_OTG_GNPTXSTS_NPTQXSAV_6   (0x40UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
     
    #define USB_OTG_GNPTXSTS_NPTQXSAV_7   (0x80UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
     
    #define USB_OTG_GNPTXSTS_NPTXQTOP_Pos   (24U)
     
    #define USB_OTG_GNPTXSTS_NPTXQTOP_Msk   (0x7FUL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
     
    #define USB_OTG_GNPTXSTS_NPTXQTOP   USB_OTG_GNPTXSTS_NPTXQTOP_Msk
     
    #define USB_OTG_GNPTXSTS_NPTXQTOP_0   (0x01UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
     
    #define USB_OTG_GNPTXSTS_NPTXQTOP_1   (0x02UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
     
    #define USB_OTG_GNPTXSTS_NPTXQTOP_2   (0x04UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
     
    #define USB_OTG_GNPTXSTS_NPTXQTOP_3   (0x08UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
     
    #define USB_OTG_GNPTXSTS_NPTXQTOP_4   (0x10UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
     
    #define USB_OTG_GNPTXSTS_NPTXQTOP_5   (0x20UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
     
    #define USB_OTG_GNPTXSTS_NPTXQTOP_6   (0x40UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
     
    #define USB_OTG_DTHRCTL_NONISOTHREN_Pos   (0U)
     
    #define USB_OTG_DTHRCTL_NONISOTHREN_Msk   (0x1UL << USB_OTG_DTHRCTL_NONISOTHREN_Pos)
     
    #define USB_OTG_DTHRCTL_NONISOTHREN   USB_OTG_DTHRCTL_NONISOTHREN_Msk
     
    #define USB_OTG_DTHRCTL_ISOTHREN_Pos   (1U)
     
    #define USB_OTG_DTHRCTL_ISOTHREN_Msk   (0x1UL << USB_OTG_DTHRCTL_ISOTHREN_Pos)
     
    #define USB_OTG_DTHRCTL_ISOTHREN   USB_OTG_DTHRCTL_ISOTHREN_Msk
     
    #define USB_OTG_DTHRCTL_TXTHRLEN_Pos   (2U)
     
    #define USB_OTG_DTHRCTL_TXTHRLEN_Msk   (0x1FFUL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
     
    #define USB_OTG_DTHRCTL_TXTHRLEN   USB_OTG_DTHRCTL_TXTHRLEN_Msk
     
    #define USB_OTG_DTHRCTL_TXTHRLEN_0   (0x001UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
     
    #define USB_OTG_DTHRCTL_TXTHRLEN_1   (0x002UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
     
    #define USB_OTG_DTHRCTL_TXTHRLEN_2   (0x004UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
     
    #define USB_OTG_DTHRCTL_TXTHRLEN_3   (0x008UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
     
    #define USB_OTG_DTHRCTL_TXTHRLEN_4   (0x010UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
     
    #define USB_OTG_DTHRCTL_TXTHRLEN_5   (0x020UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
     
    #define USB_OTG_DTHRCTL_TXTHRLEN_6   (0x040UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
     
    #define USB_OTG_DTHRCTL_TXTHRLEN_7   (0x080UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
     
    #define USB_OTG_DTHRCTL_TXTHRLEN_8   (0x100UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
     
    #define USB_OTG_DTHRCTL_RXTHREN_Pos   (16U)
     
    #define USB_OTG_DTHRCTL_RXTHREN_Msk   (0x1UL << USB_OTG_DTHRCTL_RXTHREN_Pos)
     
    #define USB_OTG_DTHRCTL_RXTHREN   USB_OTG_DTHRCTL_RXTHREN_Msk
     
    #define USB_OTG_DTHRCTL_RXTHRLEN_Pos   (17U)
     
    #define USB_OTG_DTHRCTL_RXTHRLEN_Msk   (0x1FFUL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
     
    #define USB_OTG_DTHRCTL_RXTHRLEN   USB_OTG_DTHRCTL_RXTHRLEN_Msk
     
    #define USB_OTG_DTHRCTL_RXTHRLEN_0   (0x001UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
     
    #define USB_OTG_DTHRCTL_RXTHRLEN_1   (0x002UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
     
    #define USB_OTG_DTHRCTL_RXTHRLEN_2   (0x004UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
     
    #define USB_OTG_DTHRCTL_RXTHRLEN_3   (0x008UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
     
    #define USB_OTG_DTHRCTL_RXTHRLEN_4   (0x010UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
     
    #define USB_OTG_DTHRCTL_RXTHRLEN_5   (0x020UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
     
    #define USB_OTG_DTHRCTL_RXTHRLEN_6   (0x040UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
     
    #define USB_OTG_DTHRCTL_RXTHRLEN_7   (0x080UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
     
    #define USB_OTG_DTHRCTL_RXTHRLEN_8   (0x100UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
     
    #define USB_OTG_DTHRCTL_ARPEN_Pos   (27U)
     
    #define USB_OTG_DTHRCTL_ARPEN_Msk   (0x1UL << USB_OTG_DTHRCTL_ARPEN_Pos)
     
    #define USB_OTG_DTHRCTL_ARPEN   USB_OTG_DTHRCTL_ARPEN_Msk
     
    #define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos   (0U)
     
    #define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk   (0xFFFFUL << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos)
     
    #define USB_OTG_DIEPEMPMSK_INEPTXFEM   USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk
     
    #define USB_OTG_DEACHINT_IEP1INT_Pos   (1U)
     
    #define USB_OTG_DEACHINT_IEP1INT_Msk   (0x1UL << USB_OTG_DEACHINT_IEP1INT_Pos)
     
    #define USB_OTG_DEACHINT_IEP1INT   USB_OTG_DEACHINT_IEP1INT_Msk
     
    #define USB_OTG_DEACHINT_OEP1INT_Pos   (17U)
     
    #define USB_OTG_DEACHINT_OEP1INT_Msk   (0x1UL << USB_OTG_DEACHINT_OEP1INT_Pos)
     
    #define USB_OTG_DEACHINT_OEP1INT   USB_OTG_DEACHINT_OEP1INT_Msk
     
    #define USB_OTG_GCCFG_PWRDWN_Pos   (16U)
     
    #define USB_OTG_GCCFG_PWRDWN_Msk   (0x1UL << USB_OTG_GCCFG_PWRDWN_Pos)
     
    #define USB_OTG_GCCFG_PWRDWN   USB_OTG_GCCFG_PWRDWN_Msk
     
    #define USB_OTG_GCCFG_I2CPADEN_Pos   (17U)
     
    #define USB_OTG_GCCFG_I2CPADEN_Msk   (0x1UL << USB_OTG_GCCFG_I2CPADEN_Pos)
     
    #define USB_OTG_GCCFG_I2CPADEN   USB_OTG_GCCFG_I2CPADEN_Msk
     
    #define USB_OTG_GCCFG_VBUSASEN_Pos   (18U)
     
    #define USB_OTG_GCCFG_VBUSASEN_Msk   (0x1UL << USB_OTG_GCCFG_VBUSASEN_Pos)
     
    #define USB_OTG_GCCFG_VBUSASEN   USB_OTG_GCCFG_VBUSASEN_Msk
     
    #define USB_OTG_GCCFG_VBUSBSEN_Pos   (19U)
     
    #define USB_OTG_GCCFG_VBUSBSEN_Msk   (0x1UL << USB_OTG_GCCFG_VBUSBSEN_Pos)
     
    #define USB_OTG_GCCFG_VBUSBSEN   USB_OTG_GCCFG_VBUSBSEN_Msk
     
    #define USB_OTG_GCCFG_SOFOUTEN_Pos   (20U)
     
    #define USB_OTG_GCCFG_SOFOUTEN_Msk   (0x1UL << USB_OTG_GCCFG_SOFOUTEN_Pos)
     
    #define USB_OTG_GCCFG_SOFOUTEN   USB_OTG_GCCFG_SOFOUTEN_Msk
     
    #define USB_OTG_GCCFG_NOVBUSSENS_Pos   (21U)
     
    #define USB_OTG_GCCFG_NOVBUSSENS_Msk   (0x1UL << USB_OTG_GCCFG_NOVBUSSENS_Pos)
     
    #define USB_OTG_GCCFG_NOVBUSSENS   USB_OTG_GCCFG_NOVBUSSENS_Msk
     
    #define USB_OTG_DEACHINTMSK_IEP1INTM_Pos   (1U)
     
    #define USB_OTG_DEACHINTMSK_IEP1INTM_Msk   (0x1UL << USB_OTG_DEACHINTMSK_IEP1INTM_Pos)
     
    #define USB_OTG_DEACHINTMSK_IEP1INTM   USB_OTG_DEACHINTMSK_IEP1INTM_Msk
     
    #define USB_OTG_DEACHINTMSK_OEP1INTM_Pos   (17U)
     
    #define USB_OTG_DEACHINTMSK_OEP1INTM_Msk   (0x1UL << USB_OTG_DEACHINTMSK_OEP1INTM_Pos)
     
    #define USB_OTG_DEACHINTMSK_OEP1INTM   USB_OTG_DEACHINTMSK_OEP1INTM_Msk
     
    #define USB_OTG_CID_PRODUCT_ID_Pos   (0U)
     
    #define USB_OTG_CID_PRODUCT_ID_Msk   (0xFFFFFFFFUL << USB_OTG_CID_PRODUCT_ID_Pos)
     
    #define USB_OTG_CID_PRODUCT_ID   USB_OTG_CID_PRODUCT_ID_Msk
     
    #define USB_OTG_DIEPEACHMSK1_XFRCM_Pos   (0U)
     
    #define USB_OTG_DIEPEACHMSK1_XFRCM_Msk   (0x1UL << USB_OTG_DIEPEACHMSK1_XFRCM_Pos)
     
    #define USB_OTG_DIEPEACHMSK1_XFRCM   USB_OTG_DIEPEACHMSK1_XFRCM_Msk
     
    #define USB_OTG_DIEPEACHMSK1_EPDM_Pos   (1U)
     
    #define USB_OTG_DIEPEACHMSK1_EPDM_Msk   (0x1UL << USB_OTG_DIEPEACHMSK1_EPDM_Pos)
     
    #define USB_OTG_DIEPEACHMSK1_EPDM   USB_OTG_DIEPEACHMSK1_EPDM_Msk
     
    #define USB_OTG_DIEPEACHMSK1_TOM_Pos   (3U)
     
    #define USB_OTG_DIEPEACHMSK1_TOM_Msk   (0x1UL << USB_OTG_DIEPEACHMSK1_TOM_Pos)
     
    #define USB_OTG_DIEPEACHMSK1_TOM   USB_OTG_DIEPEACHMSK1_TOM_Msk
     
    #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos   (4U)
     
    #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk   (0x1UL << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos)
     
    #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK   USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk
     
    #define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos   (5U)
     
    #define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk   (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos)
     
    #define USB_OTG_DIEPEACHMSK1_INEPNMM   USB_OTG_DIEPEACHMSK1_INEPNMM_Msk
     
    #define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos   (6U)
     
    #define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk   (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos)
     
    #define USB_OTG_DIEPEACHMSK1_INEPNEM   USB_OTG_DIEPEACHMSK1_INEPNEM_Msk
     
    #define USB_OTG_DIEPEACHMSK1_TXFURM_Pos   (8U)
     
    #define USB_OTG_DIEPEACHMSK1_TXFURM_Msk   (0x1UL << USB_OTG_DIEPEACHMSK1_TXFURM_Pos)
     
    #define USB_OTG_DIEPEACHMSK1_TXFURM   USB_OTG_DIEPEACHMSK1_TXFURM_Msk
     
    #define USB_OTG_DIEPEACHMSK1_BIM_Pos   (9U)
     
    #define USB_OTG_DIEPEACHMSK1_BIM_Msk   (0x1UL << USB_OTG_DIEPEACHMSK1_BIM_Pos)
     
    #define USB_OTG_DIEPEACHMSK1_BIM   USB_OTG_DIEPEACHMSK1_BIM_Msk
     
    #define USB_OTG_DIEPEACHMSK1_NAKM_Pos   (13U)
     
    #define USB_OTG_DIEPEACHMSK1_NAKM_Msk   (0x1UL << USB_OTG_DIEPEACHMSK1_NAKM_Pos)
     
    #define USB_OTG_DIEPEACHMSK1_NAKM   USB_OTG_DIEPEACHMSK1_NAKM_Msk
     
    #define USB_OTG_HPRT_PCSTS_Pos   (0U)
     
    #define USB_OTG_HPRT_PCSTS_Msk   (0x1UL << USB_OTG_HPRT_PCSTS_Pos)
     
    #define USB_OTG_HPRT_PCSTS   USB_OTG_HPRT_PCSTS_Msk
     
    #define USB_OTG_HPRT_PCDET_Pos   (1U)
     
    #define USB_OTG_HPRT_PCDET_Msk   (0x1UL << USB_OTG_HPRT_PCDET_Pos)
     
    #define USB_OTG_HPRT_PCDET   USB_OTG_HPRT_PCDET_Msk
     
    #define USB_OTG_HPRT_PENA_Pos   (2U)
     
    #define USB_OTG_HPRT_PENA_Msk   (0x1UL << USB_OTG_HPRT_PENA_Pos)
     
    #define USB_OTG_HPRT_PENA   USB_OTG_HPRT_PENA_Msk
     
    #define USB_OTG_HPRT_PENCHNG_Pos   (3U)
     
    #define USB_OTG_HPRT_PENCHNG_Msk   (0x1UL << USB_OTG_HPRT_PENCHNG_Pos)
     
    #define USB_OTG_HPRT_PENCHNG   USB_OTG_HPRT_PENCHNG_Msk
     
    #define USB_OTG_HPRT_POCA_Pos   (4U)
     
    #define USB_OTG_HPRT_POCA_Msk   (0x1UL << USB_OTG_HPRT_POCA_Pos)
     
    #define USB_OTG_HPRT_POCA   USB_OTG_HPRT_POCA_Msk
     
    #define USB_OTG_HPRT_POCCHNG_Pos   (5U)
     
    #define USB_OTG_HPRT_POCCHNG_Msk   (0x1UL << USB_OTG_HPRT_POCCHNG_Pos)
     
    #define USB_OTG_HPRT_POCCHNG   USB_OTG_HPRT_POCCHNG_Msk
     
    #define USB_OTG_HPRT_PRES_Pos   (6U)
     
    #define USB_OTG_HPRT_PRES_Msk   (0x1UL << USB_OTG_HPRT_PRES_Pos)
     
    #define USB_OTG_HPRT_PRES   USB_OTG_HPRT_PRES_Msk
     
    #define USB_OTG_HPRT_PSUSP_Pos   (7U)
     
    #define USB_OTG_HPRT_PSUSP_Msk   (0x1UL << USB_OTG_HPRT_PSUSP_Pos)
     
    #define USB_OTG_HPRT_PSUSP   USB_OTG_HPRT_PSUSP_Msk
     
    #define USB_OTG_HPRT_PRST_Pos   (8U)
     
    #define USB_OTG_HPRT_PRST_Msk   (0x1UL << USB_OTG_HPRT_PRST_Pos)
     
    #define USB_OTG_HPRT_PRST   USB_OTG_HPRT_PRST_Msk
     
    #define USB_OTG_HPRT_PLSTS_Pos   (10U)
     
    #define USB_OTG_HPRT_PLSTS_Msk   (0x3UL << USB_OTG_HPRT_PLSTS_Pos)
     
    #define USB_OTG_HPRT_PLSTS   USB_OTG_HPRT_PLSTS_Msk
     
    #define USB_OTG_HPRT_PLSTS_0   (0x1UL << USB_OTG_HPRT_PLSTS_Pos)
     
    #define USB_OTG_HPRT_PLSTS_1   (0x2UL << USB_OTG_HPRT_PLSTS_Pos)
     
    #define USB_OTG_HPRT_PPWR_Pos   (12U)
     
    #define USB_OTG_HPRT_PPWR_Msk   (0x1UL << USB_OTG_HPRT_PPWR_Pos)
     
    #define USB_OTG_HPRT_PPWR   USB_OTG_HPRT_PPWR_Msk
     
    #define USB_OTG_HPRT_PTCTL_Pos   (13U)
     
    #define USB_OTG_HPRT_PTCTL_Msk   (0xFUL << USB_OTG_HPRT_PTCTL_Pos)
     
    #define USB_OTG_HPRT_PTCTL   USB_OTG_HPRT_PTCTL_Msk
     
    #define USB_OTG_HPRT_PTCTL_0   (0x1UL << USB_OTG_HPRT_PTCTL_Pos)
     
    #define USB_OTG_HPRT_PTCTL_1   (0x2UL << USB_OTG_HPRT_PTCTL_Pos)
     
    #define USB_OTG_HPRT_PTCTL_2   (0x4UL << USB_OTG_HPRT_PTCTL_Pos)
     
    #define USB_OTG_HPRT_PTCTL_3   (0x8UL << USB_OTG_HPRT_PTCTL_Pos)
     
    #define USB_OTG_HPRT_PSPD_Pos   (17U)
     
    #define USB_OTG_HPRT_PSPD_Msk   (0x3UL << USB_OTG_HPRT_PSPD_Pos)
     
    #define USB_OTG_HPRT_PSPD   USB_OTG_HPRT_PSPD_Msk
     
    #define USB_OTG_HPRT_PSPD_0   (0x1UL << USB_OTG_HPRT_PSPD_Pos)
     
    #define USB_OTG_HPRT_PSPD_1   (0x2UL << USB_OTG_HPRT_PSPD_Pos)
     
    #define USB_OTG_DOEPEACHMSK1_XFRCM_Pos   (0U)
     
    #define USB_OTG_DOEPEACHMSK1_XFRCM_Msk   (0x1UL << USB_OTG_DOEPEACHMSK1_XFRCM_Pos)
     
    #define USB_OTG_DOEPEACHMSK1_XFRCM   USB_OTG_DOEPEACHMSK1_XFRCM_Msk
     
    #define USB_OTG_DOEPEACHMSK1_EPDM_Pos   (1U)
     
    #define USB_OTG_DOEPEACHMSK1_EPDM_Msk   (0x1UL << USB_OTG_DOEPEACHMSK1_EPDM_Pos)
     
    #define USB_OTG_DOEPEACHMSK1_EPDM   USB_OTG_DOEPEACHMSK1_EPDM_Msk
     
    #define USB_OTG_DOEPEACHMSK1_TOM_Pos   (3U)
     
    #define USB_OTG_DOEPEACHMSK1_TOM_Msk   (0x1UL << USB_OTG_DOEPEACHMSK1_TOM_Pos)
     
    #define USB_OTG_DOEPEACHMSK1_TOM   USB_OTG_DOEPEACHMSK1_TOM_Msk
     
    #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos   (4U)
     
    #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk   (0x1UL << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos)
     
    #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK   USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk
     
    #define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos   (5U)
     
    #define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk   (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos)
     
    #define USB_OTG_DOEPEACHMSK1_INEPNMM   USB_OTG_DOEPEACHMSK1_INEPNMM_Msk
     
    #define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos   (6U)
     
    #define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk   (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos)
     
    #define USB_OTG_DOEPEACHMSK1_INEPNEM   USB_OTG_DOEPEACHMSK1_INEPNEM_Msk
     
    #define USB_OTG_DOEPEACHMSK1_TXFURM_Pos   (8U)
     
    #define USB_OTG_DOEPEACHMSK1_TXFURM_Msk   (0x1UL << USB_OTG_DOEPEACHMSK1_TXFURM_Pos)
     
    #define USB_OTG_DOEPEACHMSK1_TXFURM   USB_OTG_DOEPEACHMSK1_TXFURM_Msk
     
    #define USB_OTG_DOEPEACHMSK1_BIM_Pos   (9U)
     
    #define USB_OTG_DOEPEACHMSK1_BIM_Msk   (0x1UL << USB_OTG_DOEPEACHMSK1_BIM_Pos)
     
    #define USB_OTG_DOEPEACHMSK1_BIM   USB_OTG_DOEPEACHMSK1_BIM_Msk
     
    #define USB_OTG_DOEPEACHMSK1_BERRM_Pos   (12U)
     
    #define USB_OTG_DOEPEACHMSK1_BERRM_Msk   (0x1UL << USB_OTG_DOEPEACHMSK1_BERRM_Pos)
     
    #define USB_OTG_DOEPEACHMSK1_BERRM   USB_OTG_DOEPEACHMSK1_BERRM_Msk
     
    #define USB_OTG_DOEPEACHMSK1_NAKM_Pos   (13U)
     
    #define USB_OTG_DOEPEACHMSK1_NAKM_Msk   (0x1UL << USB_OTG_DOEPEACHMSK1_NAKM_Pos)
     
    #define USB_OTG_DOEPEACHMSK1_NAKM   USB_OTG_DOEPEACHMSK1_NAKM_Msk
     
    #define USB_OTG_DOEPEACHMSK1_NYETM_Pos   (14U)
     
    #define USB_OTG_DOEPEACHMSK1_NYETM_Msk   (0x1UL << USB_OTG_DOEPEACHMSK1_NYETM_Pos)
     
    #define USB_OTG_DOEPEACHMSK1_NYETM   USB_OTG_DOEPEACHMSK1_NYETM_Msk
     
    #define USB_OTG_HPTXFSIZ_PTXSA_Pos   (0U)
     
    #define USB_OTG_HPTXFSIZ_PTXSA_Msk   (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXSA_Pos)
     
    #define USB_OTG_HPTXFSIZ_PTXSA   USB_OTG_HPTXFSIZ_PTXSA_Msk
     
    #define USB_OTG_HPTXFSIZ_PTXFD_Pos   (16U)
     
    #define USB_OTG_HPTXFSIZ_PTXFD_Msk   (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXFD_Pos)
     
    #define USB_OTG_HPTXFSIZ_PTXFD   USB_OTG_HPTXFSIZ_PTXFD_Msk
     
    #define USB_OTG_DIEPCTL_MPSIZ_Pos   (0U)
     
    #define USB_OTG_DIEPCTL_MPSIZ_Msk   (0x7FFUL << USB_OTG_DIEPCTL_MPSIZ_Pos)
     
    #define USB_OTG_DIEPCTL_MPSIZ   USB_OTG_DIEPCTL_MPSIZ_Msk
     
    #define USB_OTG_DIEPCTL_USBAEP_Pos   (15U)
     
    #define USB_OTG_DIEPCTL_USBAEP_Msk   (0x1UL << USB_OTG_DIEPCTL_USBAEP_Pos)
     
    #define USB_OTG_DIEPCTL_USBAEP   USB_OTG_DIEPCTL_USBAEP_Msk
     
    #define USB_OTG_DIEPCTL_EONUM_DPID_Pos   (16U)
     
    #define USB_OTG_DIEPCTL_EONUM_DPID_Msk   (0x1UL << USB_OTG_DIEPCTL_EONUM_DPID_Pos)
     
    #define USB_OTG_DIEPCTL_EONUM_DPID   USB_OTG_DIEPCTL_EONUM_DPID_Msk
     
    #define USB_OTG_DIEPCTL_NAKSTS_Pos   (17U)
     
    #define USB_OTG_DIEPCTL_NAKSTS_Msk   (0x1UL << USB_OTG_DIEPCTL_NAKSTS_Pos)
     
    #define USB_OTG_DIEPCTL_NAKSTS   USB_OTG_DIEPCTL_NAKSTS_Msk
     
    #define USB_OTG_DIEPCTL_EPTYP_Pos   (18U)
     
    #define USB_OTG_DIEPCTL_EPTYP_Msk   (0x3UL << USB_OTG_DIEPCTL_EPTYP_Pos)
     
    #define USB_OTG_DIEPCTL_EPTYP   USB_OTG_DIEPCTL_EPTYP_Msk
     
    #define USB_OTG_DIEPCTL_EPTYP_0   (0x1UL << USB_OTG_DIEPCTL_EPTYP_Pos)
     
    #define USB_OTG_DIEPCTL_EPTYP_1   (0x2UL << USB_OTG_DIEPCTL_EPTYP_Pos)
     
    #define USB_OTG_DIEPCTL_STALL_Pos   (21U)
     
    #define USB_OTG_DIEPCTL_STALL_Msk   (0x1UL << USB_OTG_DIEPCTL_STALL_Pos)
     
    #define USB_OTG_DIEPCTL_STALL   USB_OTG_DIEPCTL_STALL_Msk
     
    #define USB_OTG_DIEPCTL_TXFNUM_Pos   (22U)
     
    #define USB_OTG_DIEPCTL_TXFNUM_Msk   (0xFUL << USB_OTG_DIEPCTL_TXFNUM_Pos)
     
    #define USB_OTG_DIEPCTL_TXFNUM   USB_OTG_DIEPCTL_TXFNUM_Msk
     
    #define USB_OTG_DIEPCTL_TXFNUM_0   (0x1UL << USB_OTG_DIEPCTL_TXFNUM_Pos)
     
    #define USB_OTG_DIEPCTL_TXFNUM_1   (0x2UL << USB_OTG_DIEPCTL_TXFNUM_Pos)
     
    #define USB_OTG_DIEPCTL_TXFNUM_2   (0x4UL << USB_OTG_DIEPCTL_TXFNUM_Pos)
     
    #define USB_OTG_DIEPCTL_TXFNUM_3   (0x8UL << USB_OTG_DIEPCTL_TXFNUM_Pos)
     
    #define USB_OTG_DIEPCTL_CNAK_Pos   (26U)
     
    #define USB_OTG_DIEPCTL_CNAK_Msk   (0x1UL << USB_OTG_DIEPCTL_CNAK_Pos)
     
    #define USB_OTG_DIEPCTL_CNAK   USB_OTG_DIEPCTL_CNAK_Msk
     
    #define USB_OTG_DIEPCTL_SNAK_Pos   (27U)
     
    #define USB_OTG_DIEPCTL_SNAK_Msk   (0x1UL << USB_OTG_DIEPCTL_SNAK_Pos)
     
    #define USB_OTG_DIEPCTL_SNAK   USB_OTG_DIEPCTL_SNAK_Msk
     
    #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos   (28U)
     
    #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk   (0x1UL << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos)
     
    #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM   USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk
     
    #define USB_OTG_DIEPCTL_SODDFRM_Pos   (29U)
     
    #define USB_OTG_DIEPCTL_SODDFRM_Msk   (0x1UL << USB_OTG_DIEPCTL_SODDFRM_Pos)
     
    #define USB_OTG_DIEPCTL_SODDFRM   USB_OTG_DIEPCTL_SODDFRM_Msk
     
    #define USB_OTG_DIEPCTL_EPDIS_Pos   (30U)
     
    #define USB_OTG_DIEPCTL_EPDIS_Msk   (0x1UL << USB_OTG_DIEPCTL_EPDIS_Pos)
     
    #define USB_OTG_DIEPCTL_EPDIS   USB_OTG_DIEPCTL_EPDIS_Msk
     
    #define USB_OTG_DIEPCTL_EPENA_Pos   (31U)
     
    #define USB_OTG_DIEPCTL_EPENA_Msk   (0x1UL << USB_OTG_DIEPCTL_EPENA_Pos)
     
    #define USB_OTG_DIEPCTL_EPENA   USB_OTG_DIEPCTL_EPENA_Msk
     
    #define USB_OTG_HCCHAR_MPSIZ_Pos   (0U)
     
    #define USB_OTG_HCCHAR_MPSIZ_Msk   (0x7FFUL << USB_OTG_HCCHAR_MPSIZ_Pos)
     
    #define USB_OTG_HCCHAR_MPSIZ   USB_OTG_HCCHAR_MPSIZ_Msk
     
    #define USB_OTG_HCCHAR_EPNUM_Pos   (11U)
     
    #define USB_OTG_HCCHAR_EPNUM_Msk   (0xFUL << USB_OTG_HCCHAR_EPNUM_Pos)
     
    #define USB_OTG_HCCHAR_EPNUM   USB_OTG_HCCHAR_EPNUM_Msk
     
    #define USB_OTG_HCCHAR_EPNUM_0   (0x1UL << USB_OTG_HCCHAR_EPNUM_Pos)
     
    #define USB_OTG_HCCHAR_EPNUM_1   (0x2UL << USB_OTG_HCCHAR_EPNUM_Pos)
     
    #define USB_OTG_HCCHAR_EPNUM_2   (0x4UL << USB_OTG_HCCHAR_EPNUM_Pos)
     
    #define USB_OTG_HCCHAR_EPNUM_3   (0x8UL << USB_OTG_HCCHAR_EPNUM_Pos)
     
    #define USB_OTG_HCCHAR_EPDIR_Pos   (15U)
     
    #define USB_OTG_HCCHAR_EPDIR_Msk   (0x1UL << USB_OTG_HCCHAR_EPDIR_Pos)
     
    #define USB_OTG_HCCHAR_EPDIR   USB_OTG_HCCHAR_EPDIR_Msk
     
    #define USB_OTG_HCCHAR_LSDEV_Pos   (17U)
     
    #define USB_OTG_HCCHAR_LSDEV_Msk   (0x1UL << USB_OTG_HCCHAR_LSDEV_Pos)
     
    #define USB_OTG_HCCHAR_LSDEV   USB_OTG_HCCHAR_LSDEV_Msk
     
    #define USB_OTG_HCCHAR_EPTYP_Pos   (18U)
     
    #define USB_OTG_HCCHAR_EPTYP_Msk   (0x3UL << USB_OTG_HCCHAR_EPTYP_Pos)
     
    #define USB_OTG_HCCHAR_EPTYP   USB_OTG_HCCHAR_EPTYP_Msk
     
    #define USB_OTG_HCCHAR_EPTYP_0   (0x1UL << USB_OTG_HCCHAR_EPTYP_Pos)
     
    #define USB_OTG_HCCHAR_EPTYP_1   (0x2UL << USB_OTG_HCCHAR_EPTYP_Pos)
     
    #define USB_OTG_HCCHAR_MC_Pos   (20U)
     
    #define USB_OTG_HCCHAR_MC_Msk   (0x3UL << USB_OTG_HCCHAR_MC_Pos)
     
    #define USB_OTG_HCCHAR_MC   USB_OTG_HCCHAR_MC_Msk
     
    #define USB_OTG_HCCHAR_MC_0   (0x1UL << USB_OTG_HCCHAR_MC_Pos)
     
    #define USB_OTG_HCCHAR_MC_1   (0x2UL << USB_OTG_HCCHAR_MC_Pos)
     
    #define USB_OTG_HCCHAR_DAD_Pos   (22U)
     
    #define USB_OTG_HCCHAR_DAD_Msk   (0x7FUL << USB_OTG_HCCHAR_DAD_Pos)
     
    #define USB_OTG_HCCHAR_DAD   USB_OTG_HCCHAR_DAD_Msk
     
    #define USB_OTG_HCCHAR_DAD_0   (0x01UL << USB_OTG_HCCHAR_DAD_Pos)
     
    #define USB_OTG_HCCHAR_DAD_1   (0x02UL << USB_OTG_HCCHAR_DAD_Pos)
     
    #define USB_OTG_HCCHAR_DAD_2   (0x04UL << USB_OTG_HCCHAR_DAD_Pos)
     
    #define USB_OTG_HCCHAR_DAD_3   (0x08UL << USB_OTG_HCCHAR_DAD_Pos)
     
    #define USB_OTG_HCCHAR_DAD_4   (0x10UL << USB_OTG_HCCHAR_DAD_Pos)
     
    #define USB_OTG_HCCHAR_DAD_5   (0x20UL << USB_OTG_HCCHAR_DAD_Pos)
     
    #define USB_OTG_HCCHAR_DAD_6   (0x40UL << USB_OTG_HCCHAR_DAD_Pos)
     
    #define USB_OTG_HCCHAR_ODDFRM_Pos   (29U)
     
    #define USB_OTG_HCCHAR_ODDFRM_Msk   (0x1UL << USB_OTG_HCCHAR_ODDFRM_Pos)
     
    #define USB_OTG_HCCHAR_ODDFRM   USB_OTG_HCCHAR_ODDFRM_Msk
     
    #define USB_OTG_HCCHAR_CHDIS_Pos   (30U)
     
    #define USB_OTG_HCCHAR_CHDIS_Msk   (0x1UL << USB_OTG_HCCHAR_CHDIS_Pos)
     
    #define USB_OTG_HCCHAR_CHDIS   USB_OTG_HCCHAR_CHDIS_Msk
     
    #define USB_OTG_HCCHAR_CHENA_Pos   (31U)
     
    #define USB_OTG_HCCHAR_CHENA_Msk   (0x1UL << USB_OTG_HCCHAR_CHENA_Pos)
     
    #define USB_OTG_HCCHAR_CHENA   USB_OTG_HCCHAR_CHENA_Msk
     
    #define USB_OTG_HCSPLT_PRTADDR_Pos   (0U)
     
    #define USB_OTG_HCSPLT_PRTADDR_Msk   (0x7FUL << USB_OTG_HCSPLT_PRTADDR_Pos)
     
    #define USB_OTG_HCSPLT_PRTADDR   USB_OTG_HCSPLT_PRTADDR_Msk
     
    #define USB_OTG_HCSPLT_PRTADDR_0   (0x01UL << USB_OTG_HCSPLT_PRTADDR_Pos)
     
    #define USB_OTG_HCSPLT_PRTADDR_1   (0x02UL << USB_OTG_HCSPLT_PRTADDR_Pos)
     
    #define USB_OTG_HCSPLT_PRTADDR_2   (0x04UL << USB_OTG_HCSPLT_PRTADDR_Pos)
     
    #define USB_OTG_HCSPLT_PRTADDR_3   (0x08UL << USB_OTG_HCSPLT_PRTADDR_Pos)
     
    #define USB_OTG_HCSPLT_PRTADDR_4   (0x10UL << USB_OTG_HCSPLT_PRTADDR_Pos)
     
    #define USB_OTG_HCSPLT_PRTADDR_5   (0x20UL << USB_OTG_HCSPLT_PRTADDR_Pos)
     
    #define USB_OTG_HCSPLT_PRTADDR_6   (0x40UL << USB_OTG_HCSPLT_PRTADDR_Pos)
     
    #define USB_OTG_HCSPLT_HUBADDR_Pos   (7U)
     
    #define USB_OTG_HCSPLT_HUBADDR_Msk   (0x7FUL << USB_OTG_HCSPLT_HUBADDR_Pos)
     
    #define USB_OTG_HCSPLT_HUBADDR   USB_OTG_HCSPLT_HUBADDR_Msk
     
    #define USB_OTG_HCSPLT_HUBADDR_0   (0x01UL << USB_OTG_HCSPLT_HUBADDR_Pos)
     
    #define USB_OTG_HCSPLT_HUBADDR_1   (0x02UL << USB_OTG_HCSPLT_HUBADDR_Pos)
     
    #define USB_OTG_HCSPLT_HUBADDR_2   (0x04UL << USB_OTG_HCSPLT_HUBADDR_Pos)
     
    #define USB_OTG_HCSPLT_HUBADDR_3   (0x08UL << USB_OTG_HCSPLT_HUBADDR_Pos)
     
    #define USB_OTG_HCSPLT_HUBADDR_4   (0x10UL << USB_OTG_HCSPLT_HUBADDR_Pos)
     
    #define USB_OTG_HCSPLT_HUBADDR_5   (0x20UL << USB_OTG_HCSPLT_HUBADDR_Pos)
     
    #define USB_OTG_HCSPLT_HUBADDR_6   (0x40UL << USB_OTG_HCSPLT_HUBADDR_Pos)
     
    #define USB_OTG_HCSPLT_XACTPOS_Pos   (14U)
     
    #define USB_OTG_HCSPLT_XACTPOS_Msk   (0x3UL << USB_OTG_HCSPLT_XACTPOS_Pos)
     
    #define USB_OTG_HCSPLT_XACTPOS   USB_OTG_HCSPLT_XACTPOS_Msk
     
    #define USB_OTG_HCSPLT_XACTPOS_0   (0x1UL << USB_OTG_HCSPLT_XACTPOS_Pos)
     
    #define USB_OTG_HCSPLT_XACTPOS_1   (0x2UL << USB_OTG_HCSPLT_XACTPOS_Pos)
     
    #define USB_OTG_HCSPLT_COMPLSPLT_Pos   (16U)
     
    #define USB_OTG_HCSPLT_COMPLSPLT_Msk   (0x1UL << USB_OTG_HCSPLT_COMPLSPLT_Pos)
     
    #define USB_OTG_HCSPLT_COMPLSPLT   USB_OTG_HCSPLT_COMPLSPLT_Msk
     
    #define USB_OTG_HCSPLT_SPLITEN_Pos   (31U)
     
    #define USB_OTG_HCSPLT_SPLITEN_Msk   (0x1UL << USB_OTG_HCSPLT_SPLITEN_Pos)
     
    #define USB_OTG_HCSPLT_SPLITEN   USB_OTG_HCSPLT_SPLITEN_Msk
     
    #define USB_OTG_HCINT_XFRC_Pos   (0U)
     
    #define USB_OTG_HCINT_XFRC_Msk   (0x1UL << USB_OTG_HCINT_XFRC_Pos)
     
    #define USB_OTG_HCINT_XFRC   USB_OTG_HCINT_XFRC_Msk
     
    #define USB_OTG_HCINT_CHH_Pos   (1U)
     
    #define USB_OTG_HCINT_CHH_Msk   (0x1UL << USB_OTG_HCINT_CHH_Pos)
     
    #define USB_OTG_HCINT_CHH   USB_OTG_HCINT_CHH_Msk
     
    #define USB_OTG_HCINT_AHBERR_Pos   (2U)
     
    #define USB_OTG_HCINT_AHBERR_Msk   (0x1UL << USB_OTG_HCINT_AHBERR_Pos)
     
    #define USB_OTG_HCINT_AHBERR   USB_OTG_HCINT_AHBERR_Msk
     
    #define USB_OTG_HCINT_STALL_Pos   (3U)
     
    #define USB_OTG_HCINT_STALL_Msk   (0x1UL << USB_OTG_HCINT_STALL_Pos)
     
    #define USB_OTG_HCINT_STALL   USB_OTG_HCINT_STALL_Msk
     
    #define USB_OTG_HCINT_NAK_Pos   (4U)
     
    #define USB_OTG_HCINT_NAK_Msk   (0x1UL << USB_OTG_HCINT_NAK_Pos)
     
    #define USB_OTG_HCINT_NAK   USB_OTG_HCINT_NAK_Msk
     
    #define USB_OTG_HCINT_ACK_Pos   (5U)
     
    #define USB_OTG_HCINT_ACK_Msk   (0x1UL << USB_OTG_HCINT_ACK_Pos)
     
    #define USB_OTG_HCINT_ACK   USB_OTG_HCINT_ACK_Msk
     
    #define USB_OTG_HCINT_NYET_Pos   (6U)
     
    #define USB_OTG_HCINT_NYET_Msk   (0x1UL << USB_OTG_HCINT_NYET_Pos)
     
    #define USB_OTG_HCINT_NYET   USB_OTG_HCINT_NYET_Msk
     
    #define USB_OTG_HCINT_TXERR_Pos   (7U)
     
    #define USB_OTG_HCINT_TXERR_Msk   (0x1UL << USB_OTG_HCINT_TXERR_Pos)
     
    #define USB_OTG_HCINT_TXERR   USB_OTG_HCINT_TXERR_Msk
     
    #define USB_OTG_HCINT_BBERR_Pos   (8U)
     
    #define USB_OTG_HCINT_BBERR_Msk   (0x1UL << USB_OTG_HCINT_BBERR_Pos)
     
    #define USB_OTG_HCINT_BBERR   USB_OTG_HCINT_BBERR_Msk
     
    #define USB_OTG_HCINT_FRMOR_Pos   (9U)
     
    #define USB_OTG_HCINT_FRMOR_Msk   (0x1UL << USB_OTG_HCINT_FRMOR_Pos)
     
    #define USB_OTG_HCINT_FRMOR   USB_OTG_HCINT_FRMOR_Msk
     
    #define USB_OTG_HCINT_DTERR_Pos   (10U)
     
    #define USB_OTG_HCINT_DTERR_Msk   (0x1UL << USB_OTG_HCINT_DTERR_Pos)
     
    #define USB_OTG_HCINT_DTERR   USB_OTG_HCINT_DTERR_Msk
     
    #define USB_OTG_DIEPINT_XFRC_Pos   (0U)
     
    #define USB_OTG_DIEPINT_XFRC_Msk   (0x1UL << USB_OTG_DIEPINT_XFRC_Pos)
     
    #define USB_OTG_DIEPINT_XFRC   USB_OTG_DIEPINT_XFRC_Msk
     
    #define USB_OTG_DIEPINT_EPDISD_Pos   (1U)
     
    #define USB_OTG_DIEPINT_EPDISD_Msk   (0x1UL << USB_OTG_DIEPINT_EPDISD_Pos)
     
    #define USB_OTG_DIEPINT_EPDISD   USB_OTG_DIEPINT_EPDISD_Msk
     
    #define USB_OTG_DIEPINT_AHBERR_Pos   (2U)
     
    #define USB_OTG_DIEPINT_AHBERR_Msk   (0x1UL << USB_OTG_DIEPINT_AHBERR_Pos)
     
    #define USB_OTG_DIEPINT_AHBERR   USB_OTG_DIEPINT_AHBERR_Msk
     
    #define USB_OTG_DIEPINT_TOC_Pos   (3U)
     
    #define USB_OTG_DIEPINT_TOC_Msk   (0x1UL << USB_OTG_DIEPINT_TOC_Pos)
     
    #define USB_OTG_DIEPINT_TOC   USB_OTG_DIEPINT_TOC_Msk
     
    #define USB_OTG_DIEPINT_ITTXFE_Pos   (4U)
     
    #define USB_OTG_DIEPINT_ITTXFE_Msk   (0x1UL << USB_OTG_DIEPINT_ITTXFE_Pos)
     
    #define USB_OTG_DIEPINT_ITTXFE   USB_OTG_DIEPINT_ITTXFE_Msk
     
    #define USB_OTG_DIEPINT_INEPNM_Pos   (5U)
     
    #define USB_OTG_DIEPINT_INEPNM_Msk   (0x1UL << USB_OTG_DIEPINT_INEPNM_Pos)
     
    #define USB_OTG_DIEPINT_INEPNM   USB_OTG_DIEPINT_INEPNM_Msk
     
    #define USB_OTG_DIEPINT_INEPNE_Pos   (6U)
     
    #define USB_OTG_DIEPINT_INEPNE_Msk   (0x1UL << USB_OTG_DIEPINT_INEPNE_Pos)
     
    #define USB_OTG_DIEPINT_INEPNE   USB_OTG_DIEPINT_INEPNE_Msk
     
    #define USB_OTG_DIEPINT_TXFE_Pos   (7U)
     
    #define USB_OTG_DIEPINT_TXFE_Msk   (0x1UL << USB_OTG_DIEPINT_TXFE_Pos)
     
    #define USB_OTG_DIEPINT_TXFE   USB_OTG_DIEPINT_TXFE_Msk
     
    #define USB_OTG_DIEPINT_TXFIFOUDRN_Pos   (8U)
     
    #define USB_OTG_DIEPINT_TXFIFOUDRN_Msk   (0x1UL << USB_OTG_DIEPINT_TXFIFOUDRN_Pos)
     
    #define USB_OTG_DIEPINT_TXFIFOUDRN   USB_OTG_DIEPINT_TXFIFOUDRN_Msk
     
    #define USB_OTG_DIEPINT_BNA_Pos   (9U)
     
    #define USB_OTG_DIEPINT_BNA_Msk   (0x1UL << USB_OTG_DIEPINT_BNA_Pos)
     
    #define USB_OTG_DIEPINT_BNA   USB_OTG_DIEPINT_BNA_Msk
     
    #define USB_OTG_DIEPINT_PKTDRPSTS_Pos   (11U)
     
    #define USB_OTG_DIEPINT_PKTDRPSTS_Msk   (0x1UL << USB_OTG_DIEPINT_PKTDRPSTS_Pos)
     
    #define USB_OTG_DIEPINT_PKTDRPSTS   USB_OTG_DIEPINT_PKTDRPSTS_Msk
     
    #define USB_OTG_DIEPINT_BERR_Pos   (12U)
     
    #define USB_OTG_DIEPINT_BERR_Msk   (0x1UL << USB_OTG_DIEPINT_BERR_Pos)
     
    #define USB_OTG_DIEPINT_BERR   USB_OTG_DIEPINT_BERR_Msk
     
    #define USB_OTG_DIEPINT_NAK_Pos   (13U)
     
    #define USB_OTG_DIEPINT_NAK_Msk   (0x1UL << USB_OTG_DIEPINT_NAK_Pos)
     
    #define USB_OTG_DIEPINT_NAK   USB_OTG_DIEPINT_NAK_Msk
     
    #define USB_OTG_HCINTMSK_XFRCM_Pos   (0U)
     
    #define USB_OTG_HCINTMSK_XFRCM_Msk   (0x1UL << USB_OTG_HCINTMSK_XFRCM_Pos)
     
    #define USB_OTG_HCINTMSK_XFRCM   USB_OTG_HCINTMSK_XFRCM_Msk
     
    #define USB_OTG_HCINTMSK_CHHM_Pos   (1U)
     
    #define USB_OTG_HCINTMSK_CHHM_Msk   (0x1UL << USB_OTG_HCINTMSK_CHHM_Pos)
     
    #define USB_OTG_HCINTMSK_CHHM   USB_OTG_HCINTMSK_CHHM_Msk
     
    #define USB_OTG_HCINTMSK_AHBERR_Pos   (2U)
     
    #define USB_OTG_HCINTMSK_AHBERR_Msk   (0x1UL << USB_OTG_HCINTMSK_AHBERR_Pos)
     
    #define USB_OTG_HCINTMSK_AHBERR   USB_OTG_HCINTMSK_AHBERR_Msk
     
    #define USB_OTG_HCINTMSK_STALLM_Pos   (3U)
     
    #define USB_OTG_HCINTMSK_STALLM_Msk   (0x1UL << USB_OTG_HCINTMSK_STALLM_Pos)
     
    #define USB_OTG_HCINTMSK_STALLM   USB_OTG_HCINTMSK_STALLM_Msk
     
    #define USB_OTG_HCINTMSK_NAKM_Pos   (4U)
     
    #define USB_OTG_HCINTMSK_NAKM_Msk   (0x1UL << USB_OTG_HCINTMSK_NAKM_Pos)
     
    #define USB_OTG_HCINTMSK_NAKM   USB_OTG_HCINTMSK_NAKM_Msk
     
    #define USB_OTG_HCINTMSK_ACKM_Pos   (5U)
     
    #define USB_OTG_HCINTMSK_ACKM_Msk   (0x1UL << USB_OTG_HCINTMSK_ACKM_Pos)
     
    #define USB_OTG_HCINTMSK_ACKM   USB_OTG_HCINTMSK_ACKM_Msk
     
    #define USB_OTG_HCINTMSK_NYET_Pos   (6U)
     
    #define USB_OTG_HCINTMSK_NYET_Msk   (0x1UL << USB_OTG_HCINTMSK_NYET_Pos)
     
    #define USB_OTG_HCINTMSK_NYET   USB_OTG_HCINTMSK_NYET_Msk
     
    #define USB_OTG_HCINTMSK_TXERRM_Pos   (7U)
     
    #define USB_OTG_HCINTMSK_TXERRM_Msk   (0x1UL << USB_OTG_HCINTMSK_TXERRM_Pos)
     
    #define USB_OTG_HCINTMSK_TXERRM   USB_OTG_HCINTMSK_TXERRM_Msk
     
    #define USB_OTG_HCINTMSK_BBERRM_Pos   (8U)
     
    #define USB_OTG_HCINTMSK_BBERRM_Msk   (0x1UL << USB_OTG_HCINTMSK_BBERRM_Pos)
     
    #define USB_OTG_HCINTMSK_BBERRM   USB_OTG_HCINTMSK_BBERRM_Msk
     
    #define USB_OTG_HCINTMSK_FRMORM_Pos   (9U)
     
    #define USB_OTG_HCINTMSK_FRMORM_Msk   (0x1UL << USB_OTG_HCINTMSK_FRMORM_Pos)
     
    #define USB_OTG_HCINTMSK_FRMORM   USB_OTG_HCINTMSK_FRMORM_Msk
     
    #define USB_OTG_HCINTMSK_DTERRM_Pos   (10U)
     
    #define USB_OTG_HCINTMSK_DTERRM_Msk   (0x1UL << USB_OTG_HCINTMSK_DTERRM_Pos)
     
    #define USB_OTG_HCINTMSK_DTERRM   USB_OTG_HCINTMSK_DTERRM_Msk
     
    #define USB_OTG_DIEPTSIZ_XFRSIZ_Pos   (0U)
     
    #define USB_OTG_DIEPTSIZ_XFRSIZ_Msk   (0x7FFFFUL << USB_OTG_DIEPTSIZ_XFRSIZ_Pos)
     
    #define USB_OTG_DIEPTSIZ_XFRSIZ   USB_OTG_DIEPTSIZ_XFRSIZ_Msk
     
    #define USB_OTG_DIEPTSIZ_PKTCNT_Pos   (19U)
     
    #define USB_OTG_DIEPTSIZ_PKTCNT_Msk   (0x3FFUL << USB_OTG_DIEPTSIZ_PKTCNT_Pos)
     
    #define USB_OTG_DIEPTSIZ_PKTCNT   USB_OTG_DIEPTSIZ_PKTCNT_Msk
     
    #define USB_OTG_DIEPTSIZ_MULCNT_Pos   (29U)
     
    #define USB_OTG_DIEPTSIZ_MULCNT_Msk   (0x3UL << USB_OTG_DIEPTSIZ_MULCNT_Pos)
     
    #define USB_OTG_DIEPTSIZ_MULCNT   USB_OTG_DIEPTSIZ_MULCNT_Msk
     
    #define USB_OTG_HCTSIZ_XFRSIZ_Pos   (0U)
     
    #define USB_OTG_HCTSIZ_XFRSIZ_Msk   (0x7FFFFUL << USB_OTG_HCTSIZ_XFRSIZ_Pos)
     
    #define USB_OTG_HCTSIZ_XFRSIZ   USB_OTG_HCTSIZ_XFRSIZ_Msk
     
    #define USB_OTG_HCTSIZ_PKTCNT_Pos   (19U)
     
    #define USB_OTG_HCTSIZ_PKTCNT_Msk   (0x3FFUL << USB_OTG_HCTSIZ_PKTCNT_Pos)
     
    #define USB_OTG_HCTSIZ_PKTCNT   USB_OTG_HCTSIZ_PKTCNT_Msk
     
    #define USB_OTG_HCTSIZ_DOPING_Pos   (31U)
     
    #define USB_OTG_HCTSIZ_DOPING_Msk   (0x1UL << USB_OTG_HCTSIZ_DOPING_Pos)
     
    #define USB_OTG_HCTSIZ_DOPING   USB_OTG_HCTSIZ_DOPING_Msk
     
    #define USB_OTG_HCTSIZ_DPID_Pos   (29U)
     
    #define USB_OTG_HCTSIZ_DPID_Msk   (0x3UL << USB_OTG_HCTSIZ_DPID_Pos)
     
    #define USB_OTG_HCTSIZ_DPID   USB_OTG_HCTSIZ_DPID_Msk
     
    #define USB_OTG_HCTSIZ_DPID_0   (0x1UL << USB_OTG_HCTSIZ_DPID_Pos)
     
    #define USB_OTG_HCTSIZ_DPID_1   (0x2UL << USB_OTG_HCTSIZ_DPID_Pos)
     
    #define USB_OTG_DIEPDMA_DMAADDR_Pos   (0U)
     
    #define USB_OTG_DIEPDMA_DMAADDR_Msk   (0xFFFFFFFFUL << USB_OTG_DIEPDMA_DMAADDR_Pos)
     
    #define USB_OTG_DIEPDMA_DMAADDR   USB_OTG_DIEPDMA_DMAADDR_Msk
     
    #define USB_OTG_HCDMA_DMAADDR_Pos   (0U)
     
    #define USB_OTG_HCDMA_DMAADDR_Msk   (0xFFFFFFFFUL << USB_OTG_HCDMA_DMAADDR_Pos)
     
    #define USB_OTG_HCDMA_DMAADDR   USB_OTG_HCDMA_DMAADDR_Msk
     
    #define USB_OTG_DTXFSTS_INEPTFSAV_Pos   (0U)
     
    #define USB_OTG_DTXFSTS_INEPTFSAV_Msk   (0xFFFFUL << USB_OTG_DTXFSTS_INEPTFSAV_Pos)
     
    #define USB_OTG_DTXFSTS_INEPTFSAV   USB_OTG_DTXFSTS_INEPTFSAV_Msk
     
    #define USB_OTG_DIEPTXF_INEPTXSA_Pos   (0U)
     
    #define USB_OTG_DIEPTXF_INEPTXSA_Msk   (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXSA_Pos)
     
    #define USB_OTG_DIEPTXF_INEPTXSA   USB_OTG_DIEPTXF_INEPTXSA_Msk
     
    #define USB_OTG_DIEPTXF_INEPTXFD_Pos   (16U)
     
    #define USB_OTG_DIEPTXF_INEPTXFD_Msk   (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXFD_Pos)
     
    #define USB_OTG_DIEPTXF_INEPTXFD   USB_OTG_DIEPTXF_INEPTXFD_Msk
     
    #define USB_OTG_DOEPCTL_MPSIZ_Pos   (0U)
     
    #define USB_OTG_DOEPCTL_MPSIZ_Msk   (0x7FFUL << USB_OTG_DOEPCTL_MPSIZ_Pos)
     
    #define USB_OTG_DOEPCTL_MPSIZ   USB_OTG_DOEPCTL_MPSIZ_Msk /*!< Maximum packet size */
     
    #define USB_OTG_DOEPCTL_USBAEP_Pos   (15U)
     
    #define USB_OTG_DOEPCTL_USBAEP_Msk   (0x1UL << USB_OTG_DOEPCTL_USBAEP_Pos)
     
    #define USB_OTG_DOEPCTL_USBAEP   USB_OTG_DOEPCTL_USBAEP_Msk
     
    #define USB_OTG_DOEPCTL_NAKSTS_Pos   (17U)
     
    #define USB_OTG_DOEPCTL_NAKSTS_Msk   (0x1UL << USB_OTG_DOEPCTL_NAKSTS_Pos)
     
    #define USB_OTG_DOEPCTL_NAKSTS   USB_OTG_DOEPCTL_NAKSTS_Msk
     
    #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos   (28U)
     
    #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk   (0x1UL << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos)
     
    #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM   USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk
     
    #define USB_OTG_DOEPCTL_SODDFRM_Pos   (29U)
     
    #define USB_OTG_DOEPCTL_SODDFRM_Msk   (0x1UL << USB_OTG_DOEPCTL_SODDFRM_Pos)
     
    #define USB_OTG_DOEPCTL_SODDFRM   USB_OTG_DOEPCTL_SODDFRM_Msk
     
    #define USB_OTG_DOEPCTL_EPTYP_Pos   (18U)
     
    #define USB_OTG_DOEPCTL_EPTYP_Msk   (0x3UL << USB_OTG_DOEPCTL_EPTYP_Pos)
     
    #define USB_OTG_DOEPCTL_EPTYP   USB_OTG_DOEPCTL_EPTYP_Msk
     
    #define USB_OTG_DOEPCTL_EPTYP_0   (0x1UL << USB_OTG_DOEPCTL_EPTYP_Pos)
     
    #define USB_OTG_DOEPCTL_EPTYP_1   (0x2UL << USB_OTG_DOEPCTL_EPTYP_Pos)
     
    #define USB_OTG_DOEPCTL_SNPM_Pos   (20U)
     
    #define USB_OTG_DOEPCTL_SNPM_Msk   (0x1UL << USB_OTG_DOEPCTL_SNPM_Pos)
     
    #define USB_OTG_DOEPCTL_SNPM   USB_OTG_DOEPCTL_SNPM_Msk
     
    #define USB_OTG_DOEPCTL_STALL_Pos   (21U)
     
    #define USB_OTG_DOEPCTL_STALL_Msk   (0x1UL << USB_OTG_DOEPCTL_STALL_Pos)
     
    #define USB_OTG_DOEPCTL_STALL   USB_OTG_DOEPCTL_STALL_Msk
     
    #define USB_OTG_DOEPCTL_CNAK_Pos   (26U)
     
    #define USB_OTG_DOEPCTL_CNAK_Msk   (0x1UL << USB_OTG_DOEPCTL_CNAK_Pos)
     
    #define USB_OTG_DOEPCTL_CNAK   USB_OTG_DOEPCTL_CNAK_Msk
     
    #define USB_OTG_DOEPCTL_SNAK_Pos   (27U)
     
    #define USB_OTG_DOEPCTL_SNAK_Msk   (0x1UL << USB_OTG_DOEPCTL_SNAK_Pos)
     
    #define USB_OTG_DOEPCTL_SNAK   USB_OTG_DOEPCTL_SNAK_Msk
     
    #define USB_OTG_DOEPCTL_EPDIS_Pos   (30U)
     
    #define USB_OTG_DOEPCTL_EPDIS_Msk   (0x1UL << USB_OTG_DOEPCTL_EPDIS_Pos)
     
    #define USB_OTG_DOEPCTL_EPDIS   USB_OTG_DOEPCTL_EPDIS_Msk
     
    #define USB_OTG_DOEPCTL_EPENA_Pos   (31U)
     
    #define USB_OTG_DOEPCTL_EPENA_Msk   (0x1UL << USB_OTG_DOEPCTL_EPENA_Pos)
     
    #define USB_OTG_DOEPCTL_EPENA   USB_OTG_DOEPCTL_EPENA_Msk
     
    #define USB_OTG_DOEPINT_XFRC_Pos   (0U)
     
    #define USB_OTG_DOEPINT_XFRC_Msk   (0x1UL << USB_OTG_DOEPINT_XFRC_Pos)
     
    #define USB_OTG_DOEPINT_XFRC   USB_OTG_DOEPINT_XFRC_Msk
     
    #define USB_OTG_DOEPINT_EPDISD_Pos   (1U)
     
    #define USB_OTG_DOEPINT_EPDISD_Msk   (0x1UL << USB_OTG_DOEPINT_EPDISD_Pos)
     
    #define USB_OTG_DOEPINT_EPDISD   USB_OTG_DOEPINT_EPDISD_Msk
     
    #define USB_OTG_DOEPINT_AHBERR_Pos   (2U)
     
    #define USB_OTG_DOEPINT_AHBERR_Msk   (0x1UL << USB_OTG_DOEPINT_AHBERR_Pos)
     
    #define USB_OTG_DOEPINT_AHBERR   USB_OTG_DOEPINT_AHBERR_Msk
     
    #define USB_OTG_DOEPINT_STUP_Pos   (3U)
     
    #define USB_OTG_DOEPINT_STUP_Msk   (0x1UL << USB_OTG_DOEPINT_STUP_Pos)
     
    #define USB_OTG_DOEPINT_STUP   USB_OTG_DOEPINT_STUP_Msk
     
    #define USB_OTG_DOEPINT_OTEPDIS_Pos   (4U)
     
    #define USB_OTG_DOEPINT_OTEPDIS_Msk   (0x1UL << USB_OTG_DOEPINT_OTEPDIS_Pos)
     
    #define USB_OTG_DOEPINT_OTEPDIS   USB_OTG_DOEPINT_OTEPDIS_Msk
     
    #define USB_OTG_DOEPINT_OTEPSPR_Pos   (5U)
     
    #define USB_OTG_DOEPINT_OTEPSPR_Msk   (0x1UL << USB_OTG_DOEPINT_OTEPSPR_Pos)
     
    #define USB_OTG_DOEPINT_OTEPSPR   USB_OTG_DOEPINT_OTEPSPR_Msk
     
    #define USB_OTG_DOEPINT_B2BSTUP_Pos   (6U)
     
    #define USB_OTG_DOEPINT_B2BSTUP_Msk   (0x1UL << USB_OTG_DOEPINT_B2BSTUP_Pos)
     
    #define USB_OTG_DOEPINT_B2BSTUP   USB_OTG_DOEPINT_B2BSTUP_Msk
     
    #define USB_OTG_DOEPINT_OUTPKTERR_Pos   (8U)
     
    #define USB_OTG_DOEPINT_OUTPKTERR_Msk   (0x1UL << USB_OTG_DOEPINT_OUTPKTERR_Pos)
     
    #define USB_OTG_DOEPINT_OUTPKTERR   USB_OTG_DOEPINT_OUTPKTERR_Msk
     
    #define USB_OTG_DOEPINT_NAK_Pos   (13U)
     
    #define USB_OTG_DOEPINT_NAK_Msk   (0x1UL << USB_OTG_DOEPINT_NAK_Pos)
     
    #define USB_OTG_DOEPINT_NAK   USB_OTG_DOEPINT_NAK_Msk
     
    #define USB_OTG_DOEPINT_NYET_Pos   (14U)
     
    #define USB_OTG_DOEPINT_NYET_Msk   (0x1UL << USB_OTG_DOEPINT_NYET_Pos)
     
    #define USB_OTG_DOEPINT_NYET   USB_OTG_DOEPINT_NYET_Msk
     
    #define USB_OTG_DOEPINT_STPKTRX_Pos   (15U)
     
    #define USB_OTG_DOEPINT_STPKTRX_Msk   (0x1UL << USB_OTG_DOEPINT_STPKTRX_Pos)
     
    #define USB_OTG_DOEPINT_STPKTRX   USB_OTG_DOEPINT_STPKTRX_Msk
     
    #define USB_OTG_DOEPTSIZ_XFRSIZ_Pos   (0U)
     
    #define USB_OTG_DOEPTSIZ_XFRSIZ_Msk   (0x7FFFFUL << USB_OTG_DOEPTSIZ_XFRSIZ_Pos)
     
    #define USB_OTG_DOEPTSIZ_XFRSIZ   USB_OTG_DOEPTSIZ_XFRSIZ_Msk
     
    #define USB_OTG_DOEPTSIZ_PKTCNT_Pos   (19U)
     
    #define USB_OTG_DOEPTSIZ_PKTCNT_Msk   (0x3FFUL << USB_OTG_DOEPTSIZ_PKTCNT_Pos)
     
    #define USB_OTG_DOEPTSIZ_PKTCNT   USB_OTG_DOEPTSIZ_PKTCNT_Msk
     
    #define USB_OTG_DOEPTSIZ_STUPCNT_Pos   (29U)
     
    #define USB_OTG_DOEPTSIZ_STUPCNT_Msk   (0x3UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos)
     
    #define USB_OTG_DOEPTSIZ_STUPCNT   USB_OTG_DOEPTSIZ_STUPCNT_Msk
     
    #define USB_OTG_DOEPTSIZ_STUPCNT_0   (0x1UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos)
     
    #define USB_OTG_DOEPTSIZ_STUPCNT_1   (0x2UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos)
     
    #define USB_OTG_PCGCCTL_STOPCLK_Pos   (0U)
     
    #define USB_OTG_PCGCCTL_STOPCLK_Msk   (0x1UL << USB_OTG_PCGCCTL_STOPCLK_Pos)
     
    #define USB_OTG_PCGCCTL_STOPCLK   USB_OTG_PCGCCTL_STOPCLK_Msk
     
    #define USB_OTG_PCGCCTL_GATECLK_Pos   (1U)
     
    #define USB_OTG_PCGCCTL_GATECLK_Msk   (0x1UL << USB_OTG_PCGCCTL_GATECLK_Pos)
     
    #define USB_OTG_PCGCCTL_GATECLK   USB_OTG_PCGCCTL_GATECLK_Msk
     
    #define USB_OTG_PCGCCTL_PHYSUSP_Pos   (4U)
     
    #define USB_OTG_PCGCCTL_PHYSUSP_Msk   (0x1UL << USB_OTG_PCGCCTL_PHYSUSP_Pos)
     
    #define USB_OTG_PCGCCTL_PHYSUSP   USB_OTG_PCGCCTL_PHYSUSP_Msk
     
    #define USB_OTG_CHNUM_Pos   (0U)
     
    #define USB_OTG_CHNUM_Msk   (0xFUL << USB_OTG_CHNUM_Pos)
     
    #define USB_OTG_CHNUM   USB_OTG_CHNUM_Msk
     
    #define USB_OTG_CHNUM_0   (0x1UL << USB_OTG_CHNUM_Pos)
     
    #define USB_OTG_CHNUM_1   (0x2UL << USB_OTG_CHNUM_Pos)
     
    #define USB_OTG_CHNUM_2   (0x4UL << USB_OTG_CHNUM_Pos)
     
    #define USB_OTG_CHNUM_3   (0x8UL << USB_OTG_CHNUM_Pos)
     
    #define USB_OTG_BCNT_Pos   (4U)
     
    #define USB_OTG_BCNT_Msk   (0x7FFUL << USB_OTG_BCNT_Pos)
     
    #define USB_OTG_BCNT   USB_OTG_BCNT_Msk
     
    #define USB_OTG_DPID_Pos   (15U)
     
    #define USB_OTG_DPID_Msk   (0x3UL << USB_OTG_DPID_Pos)
     
    #define USB_OTG_DPID   USB_OTG_DPID_Msk
     
    #define USB_OTG_DPID_0   (0x1UL << USB_OTG_DPID_Pos)
     
    #define USB_OTG_DPID_1   (0x2UL << USB_OTG_DPID_Pos)
     
    #define USB_OTG_PKTSTS_Pos   (17U)
     
    #define USB_OTG_PKTSTS_Msk   (0xFUL << USB_OTG_PKTSTS_Pos)
     
    #define USB_OTG_PKTSTS   USB_OTG_PKTSTS_Msk
     
    #define USB_OTG_PKTSTS_0   (0x1UL << USB_OTG_PKTSTS_Pos)
     
    #define USB_OTG_PKTSTS_1   (0x2UL << USB_OTG_PKTSTS_Pos)
     
    #define USB_OTG_PKTSTS_2   (0x4UL << USB_OTG_PKTSTS_Pos)
     
    #define USB_OTG_PKTSTS_3   (0x8UL << USB_OTG_PKTSTS_Pos)
     
    #define USB_OTG_EPNUM_Pos   (0U)
     
    #define USB_OTG_EPNUM_Msk   (0xFUL << USB_OTG_EPNUM_Pos)
     
    #define USB_OTG_EPNUM   USB_OTG_EPNUM_Msk
     
    #define USB_OTG_EPNUM_0   (0x1UL << USB_OTG_EPNUM_Pos)
     
    #define USB_OTG_EPNUM_1   (0x2UL << USB_OTG_EPNUM_Pos)
     
    #define USB_OTG_EPNUM_2   (0x4UL << USB_OTG_EPNUM_Pos)
     
    #define USB_OTG_EPNUM_3   (0x8UL << USB_OTG_EPNUM_Pos)
     
    #define USB_OTG_FRMNUM_Pos   (21U)
     
    #define USB_OTG_FRMNUM_Msk   (0xFUL << USB_OTG_FRMNUM_Pos)
     
    #define USB_OTG_FRMNUM   USB_OTG_FRMNUM_Msk
     
    #define USB_OTG_FRMNUM_0   (0x1UL << USB_OTG_FRMNUM_Pos)
     
    #define USB_OTG_FRMNUM_1   (0x2UL << USB_OTG_FRMNUM_Pos)
     
    #define USB_OTG_FRMNUM_2   (0x4UL << USB_OTG_FRMNUM_Pos)
     
    #define USB_OTG_FRMNUM_3   (0x8UL << USB_OTG_FRMNUM_Pos)
     
    -

    Detailed Description

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    Macro Definition Documentation

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    ◆ ADC_MULTIMODE_SUPPORT

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    #define ADC_MULTIMODE_SUPPORT
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    ADC Multimode feature available on specific devices

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    ◆ ADC_SR_AWD_Pos

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    #define ADC_SR_AWD_Pos   (0U)
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    ◆ ADC_SR_AWD_Msk

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    #define ADC_SR_AWD_Msk   (0x1UL << ADC_SR_AWD_Pos)
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    0x00000001

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    ◆ ADC_SR_AWD

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    #define ADC_SR_AWD   ADC_SR_AWD_Msk
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    Analog watchdog flag

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    ◆ ADC_SR_EOC_Pos

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    #define ADC_SR_EOC_Pos   (1U)
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    ◆ ADC_SR_EOC_Msk

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    #define ADC_SR_EOC_Msk   (0x1UL << ADC_SR_EOC_Pos)
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    0x00000002

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    ◆ ADC_SR_EOC

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    #define ADC_SR_EOC   ADC_SR_EOC_Msk
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    End of conversion

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    ◆ ADC_SR_JEOC_Pos

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    #define ADC_SR_JEOC_Pos   (2U)
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    ◆ ADC_SR_JEOC_Msk

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    #define ADC_SR_JEOC_Msk   (0x1UL << ADC_SR_JEOC_Pos)
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    0x00000004

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    ◆ ADC_SR_JEOC

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    #define ADC_SR_JEOC   ADC_SR_JEOC_Msk
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    Injected channel end of conversion

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    ◆ ADC_SR_JSTRT_Pos

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    #define ADC_SR_JSTRT_Pos   (3U)
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    ◆ ADC_SR_JSTRT_Msk

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    #define ADC_SR_JSTRT_Msk   (0x1UL << ADC_SR_JSTRT_Pos)
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    0x00000008

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    ◆ ADC_SR_JSTRT

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    #define ADC_SR_JSTRT   ADC_SR_JSTRT_Msk
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    Injected channel Start flag

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    ◆ ADC_SR_STRT_Pos

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    #define ADC_SR_STRT_Pos   (4U)
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    ◆ ADC_SR_STRT_Msk

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    #define ADC_SR_STRT_Msk   (0x1UL << ADC_SR_STRT_Pos)
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    0x00000010

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    ◆ ADC_SR_STRT

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    #define ADC_SR_STRT   ADC_SR_STRT_Msk
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    Regular channel Start flag

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    ◆ ADC_SR_OVR_Pos

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    #define ADC_SR_OVR_Pos   (5U)
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    ◆ ADC_SR_OVR_Msk

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    #define ADC_SR_OVR_Msk   (0x1UL << ADC_SR_OVR_Pos)
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    0x00000020

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    ◆ ADC_SR_OVR

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    #define ADC_SR_OVR   ADC_SR_OVR_Msk
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    Overrun flag

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    ◆ ADC_CR1_AWDCH_Pos

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    #define ADC_CR1_AWDCH_Pos   (0U)
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    ◆ ADC_CR1_AWDCH_Msk

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    #define ADC_CR1_AWDCH_Msk   (0x1FUL << ADC_CR1_AWDCH_Pos)
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    0x0000001F

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    ◆ ADC_CR1_AWDCH

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    #define ADC_CR1_AWDCH   ADC_CR1_AWDCH_Msk
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    AWDCH[4:0] bits (Analog watchdog channel select bits)

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    ◆ ADC_CR1_AWDCH_0

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    #define ADC_CR1_AWDCH_0   (0x01UL << ADC_CR1_AWDCH_Pos)
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    0x00000001

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    ◆ ADC_CR1_AWDCH_1

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    #define ADC_CR1_AWDCH_1   (0x02UL << ADC_CR1_AWDCH_Pos)
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    0x00000002

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    ◆ ADC_CR1_AWDCH_2

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    #define ADC_CR1_AWDCH_2   (0x04UL << ADC_CR1_AWDCH_Pos)
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    0x00000004

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    ◆ ADC_CR1_AWDCH_3

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    #define ADC_CR1_AWDCH_3   (0x08UL << ADC_CR1_AWDCH_Pos)
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    0x00000008

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    ◆ ADC_CR1_AWDCH_4

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    #define ADC_CR1_AWDCH_4   (0x10UL << ADC_CR1_AWDCH_Pos)
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    0x00000010

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    ◆ ADC_CR1_EOCIE_Pos

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    #define ADC_CR1_EOCIE_Pos   (5U)
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    ◆ ADC_CR1_EOCIE_Msk

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    #define ADC_CR1_EOCIE_Msk   (0x1UL << ADC_CR1_EOCIE_Pos)
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    0x00000020

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    ◆ ADC_CR1_EOCIE

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    #define ADC_CR1_EOCIE   ADC_CR1_EOCIE_Msk
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    Interrupt enable for EOC

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    ◆ ADC_CR1_AWDIE_Pos

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    #define ADC_CR1_AWDIE_Pos   (6U)
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    ◆ ADC_CR1_AWDIE_Msk

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    #define ADC_CR1_AWDIE_Msk   (0x1UL << ADC_CR1_AWDIE_Pos)
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    0x00000040

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    ◆ ADC_CR1_AWDIE

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    #define ADC_CR1_AWDIE   ADC_CR1_AWDIE_Msk
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    AAnalog Watchdog interrupt enable

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    ◆ ADC_CR1_JEOCIE_Pos

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    #define ADC_CR1_JEOCIE_Pos   (7U)
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    ◆ ADC_CR1_JEOCIE_Msk

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    #define ADC_CR1_JEOCIE_Msk   (0x1UL << ADC_CR1_JEOCIE_Pos)
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    0x00000080

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    ◆ ADC_CR1_JEOCIE

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    #define ADC_CR1_JEOCIE   ADC_CR1_JEOCIE_Msk
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    Interrupt enable for injected channels

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    ◆ ADC_CR1_SCAN_Pos

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    #define ADC_CR1_SCAN_Pos   (8U)
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    ◆ ADC_CR1_SCAN_Msk

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    #define ADC_CR1_SCAN_Msk   (0x1UL << ADC_CR1_SCAN_Pos)
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    0x00000100

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    ◆ ADC_CR1_SCAN

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    #define ADC_CR1_SCAN   ADC_CR1_SCAN_Msk
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    Scan mode

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    ◆ ADC_CR1_AWDSGL_Pos

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    #define ADC_CR1_AWDSGL_Pos   (9U)
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    ◆ ADC_CR1_AWDSGL_Msk

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    #define ADC_CR1_AWDSGL_Msk   (0x1UL << ADC_CR1_AWDSGL_Pos)
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    0x00000200

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    ◆ ADC_CR1_AWDSGL

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    #define ADC_CR1_AWDSGL   ADC_CR1_AWDSGL_Msk
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    Enable the watchdog on a single channel in scan mode

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    ◆ ADC_CR1_JAUTO_Pos

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    #define ADC_CR1_JAUTO_Pos   (10U)
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    ◆ ADC_CR1_JAUTO_Msk

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    #define ADC_CR1_JAUTO_Msk   (0x1UL << ADC_CR1_JAUTO_Pos)
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    0x00000400

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    ◆ ADC_CR1_JAUTO

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    #define ADC_CR1_JAUTO   ADC_CR1_JAUTO_Msk
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    Automatic injected group conversion

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    ◆ ADC_CR1_DISCEN_Pos

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    #define ADC_CR1_DISCEN_Pos   (11U)
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    ◆ ADC_CR1_DISCEN_Msk

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    #define ADC_CR1_DISCEN_Msk   (0x1UL << ADC_CR1_DISCEN_Pos)
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    0x00000800

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    ◆ ADC_CR1_DISCEN

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    #define ADC_CR1_DISCEN   ADC_CR1_DISCEN_Msk
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    Discontinuous mode on regular channels

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    ◆ ADC_CR1_JDISCEN_Pos

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    #define ADC_CR1_JDISCEN_Pos   (12U)
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    ◆ ADC_CR1_JDISCEN_Msk

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    #define ADC_CR1_JDISCEN_Msk   (0x1UL << ADC_CR1_JDISCEN_Pos)
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    0x00001000

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    ◆ ADC_CR1_JDISCEN

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    #define ADC_CR1_JDISCEN   ADC_CR1_JDISCEN_Msk
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    Discontinuous mode on injected channels

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    ◆ ADC_CR1_DISCNUM_Pos

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    #define ADC_CR1_DISCNUM_Pos   (13U)
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    ◆ ADC_CR1_DISCNUM_Msk

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    #define ADC_CR1_DISCNUM_Msk   (0x7UL << ADC_CR1_DISCNUM_Pos)
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    0x0000E000

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    ◆ ADC_CR1_DISCNUM

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    #define ADC_CR1_DISCNUM   ADC_CR1_DISCNUM_Msk
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    DISCNUM[2:0] bits (Discontinuous mode channel count)

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    ◆ ADC_CR1_DISCNUM_0

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    #define ADC_CR1_DISCNUM_0   (0x1UL << ADC_CR1_DISCNUM_Pos)
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    0x00002000

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    ◆ ADC_CR1_DISCNUM_1

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    #define ADC_CR1_DISCNUM_1   (0x2UL << ADC_CR1_DISCNUM_Pos)
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    0x00004000

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    ◆ ADC_CR1_DISCNUM_2

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    #define ADC_CR1_DISCNUM_2   (0x4UL << ADC_CR1_DISCNUM_Pos)
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    0x00008000

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    ◆ ADC_CR1_JAWDEN_Pos

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    #define ADC_CR1_JAWDEN_Pos   (22U)
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    ◆ ADC_CR1_JAWDEN_Msk

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    #define ADC_CR1_JAWDEN_Msk   (0x1UL << ADC_CR1_JAWDEN_Pos)
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    0x00400000

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    ◆ ADC_CR1_JAWDEN

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    #define ADC_CR1_JAWDEN   ADC_CR1_JAWDEN_Msk
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    Analog watchdog enable on injected channels

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    ◆ ADC_CR1_AWDEN_Pos

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    #define ADC_CR1_AWDEN_Pos   (23U)
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    ◆ ADC_CR1_AWDEN_Msk

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    #define ADC_CR1_AWDEN_Msk   (0x1UL << ADC_CR1_AWDEN_Pos)
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    0x00800000

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    ◆ ADC_CR1_AWDEN

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    #define ADC_CR1_AWDEN   ADC_CR1_AWDEN_Msk
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    Analog watchdog enable on regular channels

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    ◆ ADC_CR1_RES_Pos

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    #define ADC_CR1_RES_Pos   (24U)
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    ◆ ADC_CR1_RES_Msk

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    #define ADC_CR1_RES_Msk   (0x3UL << ADC_CR1_RES_Pos)
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    0x03000000

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    ◆ ADC_CR1_RES

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    #define ADC_CR1_RES   ADC_CR1_RES_Msk
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    RES[2:0] bits (Resolution)

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    ◆ ADC_CR1_RES_0

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    #define ADC_CR1_RES_0   (0x1UL << ADC_CR1_RES_Pos)
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    0x01000000

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    ◆ ADC_CR1_RES_1

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    #define ADC_CR1_RES_1   (0x2UL << ADC_CR1_RES_Pos)
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    0x02000000

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    ◆ ADC_CR1_OVRIE_Pos

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    #define ADC_CR1_OVRIE_Pos   (26U)
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    ◆ ADC_CR1_OVRIE_Msk

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    #define ADC_CR1_OVRIE_Msk   (0x1UL << ADC_CR1_OVRIE_Pos)
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    0x04000000

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    ◆ ADC_CR1_OVRIE

    - -
    -
    - - - - -
    #define ADC_CR1_OVRIE   ADC_CR1_OVRIE_Msk
    -
    -

    overrun interrupt enable

    - -
    -
    - -

    ◆ ADC_CR2_ADON_Pos

    - -
    -
    - - - - -
    #define ADC_CR2_ADON_Pos   (0U)
    -
    - -
    -
    - -

    ◆ ADC_CR2_ADON_Msk

    - -
    -
    - - - - -
    #define ADC_CR2_ADON_Msk   (0x1UL << ADC_CR2_ADON_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ ADC_CR2_ADON

    - -
    -
    - - - - -
    #define ADC_CR2_ADON   ADC_CR2_ADON_Msk
    -
    -

    A/D Converter ON / OFF

    - -
    -
    - -

    ◆ ADC_CR2_CONT_Pos

    - -
    -
    - - - - -
    #define ADC_CR2_CONT_Pos   (1U)
    -
    - -
    -
    - -

    ◆ ADC_CR2_CONT_Msk

    - -
    -
    - - - - -
    #define ADC_CR2_CONT_Msk   (0x1UL << ADC_CR2_CONT_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ ADC_CR2_CONT

    - -
    -
    - - - - -
    #define ADC_CR2_CONT   ADC_CR2_CONT_Msk
    -
    -

    Continuous Conversion

    - -
    -
    - -

    ◆ ADC_CR2_DMA_Pos

    - -
    -
    - - - - -
    #define ADC_CR2_DMA_Pos   (8U)
    -
    - -
    -
    - -

    ◆ ADC_CR2_DMA_Msk

    - -
    -
    - - - - -
    #define ADC_CR2_DMA_Msk   (0x1UL << ADC_CR2_DMA_Pos)
    -
    -

    0x00000100

    - -
    -
    - -

    ◆ ADC_CR2_DMA

    - -
    -
    - - - - -
    #define ADC_CR2_DMA   ADC_CR2_DMA_Msk
    -
    -

    Direct Memory access mode

    - -
    -
    - -

    ◆ ADC_CR2_DDS_Pos

    - -
    -
    - - - - -
    #define ADC_CR2_DDS_Pos   (9U)
    -
    - -
    -
    - -

    ◆ ADC_CR2_DDS_Msk

    - -
    -
    - - - - -
    #define ADC_CR2_DDS_Msk   (0x1UL << ADC_CR2_DDS_Pos)
    -
    -

    0x00000200

    - -
    -
    - -

    ◆ ADC_CR2_DDS

    - -
    -
    - - - - -
    #define ADC_CR2_DDS   ADC_CR2_DDS_Msk
    -
    -

    DMA disable selection (Single ADC)

    - -
    -
    - -

    ◆ ADC_CR2_EOCS_Pos

    - -
    -
    - - - - -
    #define ADC_CR2_EOCS_Pos   (10U)
    -
    - -
    -
    - -

    ◆ ADC_CR2_EOCS_Msk

    - -
    -
    - - - - -
    #define ADC_CR2_EOCS_Msk   (0x1UL << ADC_CR2_EOCS_Pos)
    -
    -

    0x00000400

    - -
    -
    - -

    ◆ ADC_CR2_EOCS

    - -
    -
    - - - - -
    #define ADC_CR2_EOCS   ADC_CR2_EOCS_Msk
    -
    -

    End of conversion selection

    - -
    -
    - -

    ◆ ADC_CR2_ALIGN_Pos

    - -
    -
    - - - - -
    #define ADC_CR2_ALIGN_Pos   (11U)
    -
    - -
    -
    - -

    ◆ ADC_CR2_ALIGN_Msk

    - -
    -
    - - - - -
    #define ADC_CR2_ALIGN_Msk   (0x1UL << ADC_CR2_ALIGN_Pos)
    -
    -

    0x00000800

    - -
    -
    - -

    ◆ ADC_CR2_ALIGN

    - -
    -
    - - - - -
    #define ADC_CR2_ALIGN   ADC_CR2_ALIGN_Msk
    -
    -

    Data Alignment

    - -
    -
    - -

    ◆ ADC_CR2_JEXTSEL_Pos

    - -
    -
    - - - - -
    #define ADC_CR2_JEXTSEL_Pos   (16U)
    -
    - -
    -
    - -

    ◆ ADC_CR2_JEXTSEL_Msk

    - -
    -
    - - - - -
    #define ADC_CR2_JEXTSEL_Msk   (0xFUL << ADC_CR2_JEXTSEL_Pos)
    -
    -

    0x000F0000

    - -
    -
    - -

    ◆ ADC_CR2_JEXTSEL

    - -
    -
    - - - - -
    #define ADC_CR2_JEXTSEL   ADC_CR2_JEXTSEL_Msk
    -
    -

    JEXTSEL[3:0] bits (External event select for injected group)

    - -
    -
    - -

    ◆ ADC_CR2_JEXTSEL_0

    - -
    -
    - - - - -
    #define ADC_CR2_JEXTSEL_0   (0x1UL << ADC_CR2_JEXTSEL_Pos)
    -
    -

    0x00010000

    - -
    -
    - -

    ◆ ADC_CR2_JEXTSEL_1

    - -
    -
    - - - - -
    #define ADC_CR2_JEXTSEL_1   (0x2UL << ADC_CR2_JEXTSEL_Pos)
    -
    -

    0x00020000

    - -
    -
    - -

    ◆ ADC_CR2_JEXTSEL_2

    - -
    -
    - - - - -
    #define ADC_CR2_JEXTSEL_2   (0x4UL << ADC_CR2_JEXTSEL_Pos)
    -
    -

    0x00040000

    - -
    -
    - -

    ◆ ADC_CR2_JEXTSEL_3

    - -
    -
    - - - - -
    #define ADC_CR2_JEXTSEL_3   (0x8UL << ADC_CR2_JEXTSEL_Pos)
    -
    -

    0x00080000

    - -
    -
    - -

    ◆ ADC_CR2_JEXTEN_Pos

    - -
    -
    - - - - -
    #define ADC_CR2_JEXTEN_Pos   (20U)
    -
    - -
    -
    - -

    ◆ ADC_CR2_JEXTEN_Msk

    - -
    -
    - - - - -
    #define ADC_CR2_JEXTEN_Msk   (0x3UL << ADC_CR2_JEXTEN_Pos)
    -
    -

    0x00300000

    - -
    -
    - -

    ◆ ADC_CR2_JEXTEN

    - -
    -
    - - - - -
    #define ADC_CR2_JEXTEN   ADC_CR2_JEXTEN_Msk
    -
    -

    JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp)

    - -
    -
    - -

    ◆ ADC_CR2_JEXTEN_0

    - -
    -
    - - - - -
    #define ADC_CR2_JEXTEN_0   (0x1UL << ADC_CR2_JEXTEN_Pos)
    -
    -

    0x00100000

    - -
    -
    - -

    ◆ ADC_CR2_JEXTEN_1

    - -
    -
    - - - - -
    #define ADC_CR2_JEXTEN_1   (0x2UL << ADC_CR2_JEXTEN_Pos)
    -
    -

    0x00200000

    - -
    -
    - -

    ◆ ADC_CR2_JSWSTART_Pos

    - -
    -
    - - - - -
    #define ADC_CR2_JSWSTART_Pos   (22U)
    -
    - -
    -
    - -

    ◆ ADC_CR2_JSWSTART_Msk

    - -
    -
    - - - - -
    #define ADC_CR2_JSWSTART_Msk   (0x1UL << ADC_CR2_JSWSTART_Pos)
    -
    -

    0x00400000

    - -
    -
    - -

    ◆ ADC_CR2_JSWSTART

    - -
    -
    - - - - -
    #define ADC_CR2_JSWSTART   ADC_CR2_JSWSTART_Msk
    -
    -

    Start Conversion of injected channels

    - -
    -
    - -

    ◆ ADC_CR2_EXTSEL_Pos

    - -
    -
    - - - - -
    #define ADC_CR2_EXTSEL_Pos   (24U)
    -
    - -
    -
    - -

    ◆ ADC_CR2_EXTSEL_Msk

    - -
    -
    - - - - -
    #define ADC_CR2_EXTSEL_Msk   (0xFUL << ADC_CR2_EXTSEL_Pos)
    -
    -

    0x0F000000

    - -
    -
    - -

    ◆ ADC_CR2_EXTSEL

    - -
    -
    - - - - -
    #define ADC_CR2_EXTSEL   ADC_CR2_EXTSEL_Msk
    -
    -

    EXTSEL[3:0] bits (External Event Select for regular group)

    - -
    -
    - -

    ◆ ADC_CR2_EXTSEL_0

    - -
    -
    - - - - -
    #define ADC_CR2_EXTSEL_0   (0x1UL << ADC_CR2_EXTSEL_Pos)
    -
    -

    0x01000000

    - -
    -
    - -

    ◆ ADC_CR2_EXTSEL_1

    - -
    -
    - - - - -
    #define ADC_CR2_EXTSEL_1   (0x2UL << ADC_CR2_EXTSEL_Pos)
    -
    -

    0x02000000

    - -
    -
    - -

    ◆ ADC_CR2_EXTSEL_2

    - -
    -
    - - - - -
    #define ADC_CR2_EXTSEL_2   (0x4UL << ADC_CR2_EXTSEL_Pos)
    -
    -

    0x04000000

    - -
    -
    - -

    ◆ ADC_CR2_EXTSEL_3

    - -
    -
    - - - - -
    #define ADC_CR2_EXTSEL_3   (0x8UL << ADC_CR2_EXTSEL_Pos)
    -
    -

    0x08000000

    - -
    -
    - -

    ◆ ADC_CR2_EXTEN_Pos

    - -
    -
    - - - - -
    #define ADC_CR2_EXTEN_Pos   (28U)
    -
    - -
    -
    - -

    ◆ ADC_CR2_EXTEN_Msk

    - -
    -
    - - - - -
    #define ADC_CR2_EXTEN_Msk   (0x3UL << ADC_CR2_EXTEN_Pos)
    -
    -

    0x30000000

    - -
    -
    - -

    ◆ ADC_CR2_EXTEN

    - -
    -
    - - - - -
    #define ADC_CR2_EXTEN   ADC_CR2_EXTEN_Msk
    -
    -

    EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp)

    - -
    -
    - -

    ◆ ADC_CR2_EXTEN_0

    - -
    -
    - - - - -
    #define ADC_CR2_EXTEN_0   (0x1UL << ADC_CR2_EXTEN_Pos)
    -
    -

    0x10000000

    - -
    -
    - -

    ◆ ADC_CR2_EXTEN_1

    - -
    -
    - - - - -
    #define ADC_CR2_EXTEN_1   (0x2UL << ADC_CR2_EXTEN_Pos)
    -
    -

    0x20000000

    - -
    -
    - -

    ◆ ADC_CR2_SWSTART_Pos

    - -
    -
    - - - - -
    #define ADC_CR2_SWSTART_Pos   (30U)
    -
    - -
    -
    - -

    ◆ ADC_CR2_SWSTART_Msk

    - -
    -
    - - - - -
    #define ADC_CR2_SWSTART_Msk   (0x1UL << ADC_CR2_SWSTART_Pos)
    -
    -

    0x40000000

    - -
    -
    - -

    ◆ ADC_CR2_SWSTART

    - -
    -
    - - - - -
    #define ADC_CR2_SWSTART   ADC_CR2_SWSTART_Msk
    -
    -

    Start Conversion of regular channels

    - -
    -
    - -

    ◆ ADC_SMPR1_SMP10_Pos

    - -
    -
    - - - - -
    #define ADC_SMPR1_SMP10_Pos   (0U)
    -
    - -
    -
    - -

    ◆ ADC_SMPR1_SMP10_Msk

    - -
    -
    - - - - -
    #define ADC_SMPR1_SMP10_Msk   (0x7UL << ADC_SMPR1_SMP10_Pos)
    -
    -

    0x00000007

    - -
    -
    - -

    ◆ ADC_SMPR1_SMP10

    - -
    -
    - - - - -
    #define ADC_SMPR1_SMP10   ADC_SMPR1_SMP10_Msk
    -
    -

    SMP10[2:0] bits (Channel 10 Sample time selection)

    - -
    -
    - -

    ◆ ADC_SMPR1_SMP10_0

    - -
    -
    - - - - -
    #define ADC_SMPR1_SMP10_0   (0x1UL << ADC_SMPR1_SMP10_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ ADC_SMPR1_SMP10_1

    - -
    -
    - - - - -
    #define ADC_SMPR1_SMP10_1   (0x2UL << ADC_SMPR1_SMP10_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ ADC_SMPR1_SMP10_2

    - -
    -
    - - - - -
    #define ADC_SMPR1_SMP10_2   (0x4UL << ADC_SMPR1_SMP10_Pos)
    -
    -

    0x00000004

    - -
    -
    - -

    ◆ ADC_SMPR1_SMP11_Pos

    - -
    -
    - - - - -
    #define ADC_SMPR1_SMP11_Pos   (3U)
    -
    - -
    -
    - -

    ◆ ADC_SMPR1_SMP11_Msk

    - -
    -
    - - - - -
    #define ADC_SMPR1_SMP11_Msk   (0x7UL << ADC_SMPR1_SMP11_Pos)
    -
    -

    0x00000038

    - -
    -
    - -

    ◆ ADC_SMPR1_SMP11

    - -
    -
    - - - - -
    #define ADC_SMPR1_SMP11   ADC_SMPR1_SMP11_Msk
    -
    -

    SMP11[2:0] bits (Channel 11 Sample time selection)

    - -
    -
    - -

    ◆ ADC_SMPR1_SMP11_0

    - -
    -
    - - - - -
    #define ADC_SMPR1_SMP11_0   (0x1UL << ADC_SMPR1_SMP11_Pos)
    -
    -

    0x00000008

    - -
    -
    - -

    ◆ ADC_SMPR1_SMP11_1

    - -
    -
    - - - - -
    #define ADC_SMPR1_SMP11_1   (0x2UL << ADC_SMPR1_SMP11_Pos)
    -
    -

    0x00000010

    - -
    -
    - -

    ◆ ADC_SMPR1_SMP11_2

    - -
    -
    - - - - -
    #define ADC_SMPR1_SMP11_2   (0x4UL << ADC_SMPR1_SMP11_Pos)
    -
    -

    0x00000020

    - -
    -
    - -

    ◆ ADC_SMPR1_SMP12_Pos

    - -
    -
    - - - - -
    #define ADC_SMPR1_SMP12_Pos   (6U)
    -
    - -
    -
    - -

    ◆ ADC_SMPR1_SMP12_Msk

    - -
    -
    - - - - -
    #define ADC_SMPR1_SMP12_Msk   (0x7UL << ADC_SMPR1_SMP12_Pos)
    -
    -

    0x000001C0

    - -
    -
    - -

    ◆ ADC_SMPR1_SMP12

    - -
    -
    - - - - -
    #define ADC_SMPR1_SMP12   ADC_SMPR1_SMP12_Msk
    -
    -

    SMP12[2:0] bits (Channel 12 Sample time selection)

    - -
    -
    - -

    ◆ ADC_SMPR1_SMP12_0

    - -
    -
    - - - - -
    #define ADC_SMPR1_SMP12_0   (0x1UL << ADC_SMPR1_SMP12_Pos)
    -
    -

    0x00000040

    - -
    -
    - -

    ◆ ADC_SMPR1_SMP12_1

    - -
    -
    - - - - -
    #define ADC_SMPR1_SMP12_1   (0x2UL << ADC_SMPR1_SMP12_Pos)
    -
    -

    0x00000080

    - -
    -
    - -

    ◆ ADC_SMPR1_SMP12_2

    - -
    -
    - - - - -
    #define ADC_SMPR1_SMP12_2   (0x4UL << ADC_SMPR1_SMP12_Pos)
    -
    -

    0x00000100

    - -
    -
    - -

    ◆ ADC_SMPR1_SMP13_Pos

    - -
    -
    - - - - -
    #define ADC_SMPR1_SMP13_Pos   (9U)
    -
    - -
    -
    - -

    ◆ ADC_SMPR1_SMP13_Msk

    - -
    -
    - - - - -
    #define ADC_SMPR1_SMP13_Msk   (0x7UL << ADC_SMPR1_SMP13_Pos)
    -
    -

    0x00000E00

    - -
    -
    - -

    ◆ ADC_SMPR1_SMP13

    - -
    -
    - - - - -
    #define ADC_SMPR1_SMP13   ADC_SMPR1_SMP13_Msk
    -
    -

    SMP13[2:0] bits (Channel 13 Sample time selection)

    - -
    -
    - -

    ◆ ADC_SMPR1_SMP13_0

    - -
    -
    - - - - -
    #define ADC_SMPR1_SMP13_0   (0x1UL << ADC_SMPR1_SMP13_Pos)
    -
    -

    0x00000200

    - -
    -
    - -

    ◆ ADC_SMPR1_SMP13_1

    - -
    -
    - - - - -
    #define ADC_SMPR1_SMP13_1   (0x2UL << ADC_SMPR1_SMP13_Pos)
    -
    -

    0x00000400

    - -
    -
    - -

    ◆ ADC_SMPR1_SMP13_2

    - -
    -
    - - - - -
    #define ADC_SMPR1_SMP13_2   (0x4UL << ADC_SMPR1_SMP13_Pos)
    -
    -

    0x00000800

    - -
    -
    - -

    ◆ ADC_SMPR1_SMP14_Pos

    - -
    -
    - - - - -
    #define ADC_SMPR1_SMP14_Pos   (12U)
    -
    - -
    -
    - -

    ◆ ADC_SMPR1_SMP14_Msk

    - -
    -
    - - - - -
    #define ADC_SMPR1_SMP14_Msk   (0x7UL << ADC_SMPR1_SMP14_Pos)
    -
    -

    0x00007000

    - -
    -
    - -

    ◆ ADC_SMPR1_SMP14

    - -
    -
    - - - - -
    #define ADC_SMPR1_SMP14   ADC_SMPR1_SMP14_Msk
    -
    -

    SMP14[2:0] bits (Channel 14 Sample time selection)

    - -
    -
    - -

    ◆ ADC_SMPR1_SMP14_0

    - -
    -
    - - - - -
    #define ADC_SMPR1_SMP14_0   (0x1UL << ADC_SMPR1_SMP14_Pos)
    -
    -

    0x00001000

    - -
    -
    - -

    ◆ ADC_SMPR1_SMP14_1

    - -
    -
    - - - - -
    #define ADC_SMPR1_SMP14_1   (0x2UL << ADC_SMPR1_SMP14_Pos)
    -
    -

    0x00002000

    - -
    -
    - -

    ◆ ADC_SMPR1_SMP14_2

    - -
    -
    - - - - -
    #define ADC_SMPR1_SMP14_2   (0x4UL << ADC_SMPR1_SMP14_Pos)
    -
    -

    0x00004000

    - -
    -
    - -

    ◆ ADC_SMPR1_SMP15_Pos

    - -
    -
    - - - - -
    #define ADC_SMPR1_SMP15_Pos   (15U)
    -
    - -
    -
    - -

    ◆ ADC_SMPR1_SMP15_Msk

    - -
    -
    - - - - -
    #define ADC_SMPR1_SMP15_Msk   (0x7UL << ADC_SMPR1_SMP15_Pos)
    -
    -

    0x00038000

    - -
    -
    - -

    ◆ ADC_SMPR1_SMP15

    - -
    -
    - - - - -
    #define ADC_SMPR1_SMP15   ADC_SMPR1_SMP15_Msk
    -
    -

    SMP15[2:0] bits (Channel 15 Sample time selection)

    - -
    -
    - -

    ◆ ADC_SMPR1_SMP15_0

    - -
    -
    - - - - -
    #define ADC_SMPR1_SMP15_0   (0x1UL << ADC_SMPR1_SMP15_Pos)
    -
    -

    0x00008000

    - -
    -
    - -

    ◆ ADC_SMPR1_SMP15_1

    - -
    -
    - - - - -
    #define ADC_SMPR1_SMP15_1   (0x2UL << ADC_SMPR1_SMP15_Pos)
    -
    -

    0x00010000

    - -
    -
    - -

    ◆ ADC_SMPR1_SMP15_2

    - -
    -
    - - - - -
    #define ADC_SMPR1_SMP15_2   (0x4UL << ADC_SMPR1_SMP15_Pos)
    -
    -

    0x00020000

    - -
    -
    - -

    ◆ ADC_SMPR1_SMP16_Pos

    - -
    -
    - - - - -
    #define ADC_SMPR1_SMP16_Pos   (18U)
    -
    - -
    -
    - -

    ◆ ADC_SMPR1_SMP16_Msk

    - -
    -
    - - - - -
    #define ADC_SMPR1_SMP16_Msk   (0x7UL << ADC_SMPR1_SMP16_Pos)
    -
    -

    0x001C0000

    - -
    -
    - -

    ◆ ADC_SMPR1_SMP16

    - -
    -
    - - - - -
    #define ADC_SMPR1_SMP16   ADC_SMPR1_SMP16_Msk
    -
    -

    SMP16[2:0] bits (Channel 16 Sample time selection)

    - -
    -
    - -

    ◆ ADC_SMPR1_SMP16_0

    - -
    -
    - - - - -
    #define ADC_SMPR1_SMP16_0   (0x1UL << ADC_SMPR1_SMP16_Pos)
    -
    -

    0x00040000

    - -
    -
    - -

    ◆ ADC_SMPR1_SMP16_1

    - -
    -
    - - - - -
    #define ADC_SMPR1_SMP16_1   (0x2UL << ADC_SMPR1_SMP16_Pos)
    -
    -

    0x00080000

    - -
    -
    - -

    ◆ ADC_SMPR1_SMP16_2

    - -
    -
    - - - - -
    #define ADC_SMPR1_SMP16_2   (0x4UL << ADC_SMPR1_SMP16_Pos)
    -
    -

    0x00100000

    - -
    -
    - -

    ◆ ADC_SMPR1_SMP17_Pos

    - -
    -
    - - - - -
    #define ADC_SMPR1_SMP17_Pos   (21U)
    -
    - -
    -
    - -

    ◆ ADC_SMPR1_SMP17_Msk

    - -
    -
    - - - - -
    #define ADC_SMPR1_SMP17_Msk   (0x7UL << ADC_SMPR1_SMP17_Pos)
    -
    -

    0x00E00000

    - -
    -
    - -

    ◆ ADC_SMPR1_SMP17

    - -
    -
    - - - - -
    #define ADC_SMPR1_SMP17   ADC_SMPR1_SMP17_Msk
    -
    -

    SMP17[2:0] bits (Channel 17 Sample time selection)

    - -
    -
    - -

    ◆ ADC_SMPR1_SMP17_0

    - -
    -
    - - - - -
    #define ADC_SMPR1_SMP17_0   (0x1UL << ADC_SMPR1_SMP17_Pos)
    -
    -

    0x00200000

    - -
    -
    - -

    ◆ ADC_SMPR1_SMP17_1

    - -
    -
    - - - - -
    #define ADC_SMPR1_SMP17_1   (0x2UL << ADC_SMPR1_SMP17_Pos)
    -
    -

    0x00400000

    - -
    -
    - -

    ◆ ADC_SMPR1_SMP17_2

    - -
    -
    - - - - -
    #define ADC_SMPR1_SMP17_2   (0x4UL << ADC_SMPR1_SMP17_Pos)
    -
    -

    0x00800000

    - -
    -
    - -

    ◆ ADC_SMPR1_SMP18_Pos

    - -
    -
    - - - - -
    #define ADC_SMPR1_SMP18_Pos   (24U)
    -
    - -
    -
    - -

    ◆ ADC_SMPR1_SMP18_Msk

    - -
    -
    - - - - -
    #define ADC_SMPR1_SMP18_Msk   (0x7UL << ADC_SMPR1_SMP18_Pos)
    -
    -

    0x07000000

    - -
    -
    - -

    ◆ ADC_SMPR1_SMP18

    - -
    -
    - - - - -
    #define ADC_SMPR1_SMP18   ADC_SMPR1_SMP18_Msk
    -
    -

    SMP18[2:0] bits (Channel 18 Sample time selection)

    - -
    -
    - -

    ◆ ADC_SMPR1_SMP18_0

    - -
    -
    - - - - -
    #define ADC_SMPR1_SMP18_0   (0x1UL << ADC_SMPR1_SMP18_Pos)
    -
    -

    0x01000000

    - -
    -
    - -

    ◆ ADC_SMPR1_SMP18_1

    - -
    -
    - - - - -
    #define ADC_SMPR1_SMP18_1   (0x2UL << ADC_SMPR1_SMP18_Pos)
    -
    -

    0x02000000

    - -
    -
    - -

    ◆ ADC_SMPR1_SMP18_2

    - -
    -
    - - - - -
    #define ADC_SMPR1_SMP18_2   (0x4UL << ADC_SMPR1_SMP18_Pos)
    -
    -

    0x04000000

    - -
    -
    - -

    ◆ ADC_SMPR2_SMP0_Pos

    - -
    -
    - - - - -
    #define ADC_SMPR2_SMP0_Pos   (0U)
    -
    - -
    -
    - -

    ◆ ADC_SMPR2_SMP0_Msk

    - -
    -
    - - - - -
    #define ADC_SMPR2_SMP0_Msk   (0x7UL << ADC_SMPR2_SMP0_Pos)
    -
    -

    0x00000007

    - -
    -
    - -

    ◆ ADC_SMPR2_SMP0

    - -
    -
    - - - - -
    #define ADC_SMPR2_SMP0   ADC_SMPR2_SMP0_Msk
    -
    -

    SMP0[2:0] bits (Channel 0 Sample time selection)

    - -
    -
    - -

    ◆ ADC_SMPR2_SMP0_0

    - -
    -
    - - - - -
    #define ADC_SMPR2_SMP0_0   (0x1UL << ADC_SMPR2_SMP0_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ ADC_SMPR2_SMP0_1

    - -
    -
    - - - - -
    #define ADC_SMPR2_SMP0_1   (0x2UL << ADC_SMPR2_SMP0_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ ADC_SMPR2_SMP0_2

    - -
    -
    - - - - -
    #define ADC_SMPR2_SMP0_2   (0x4UL << ADC_SMPR2_SMP0_Pos)
    -
    -

    0x00000004

    - -
    -
    - -

    ◆ ADC_SMPR2_SMP1_Pos

    - -
    -
    - - - - -
    #define ADC_SMPR2_SMP1_Pos   (3U)
    -
    - -
    -
    - -

    ◆ ADC_SMPR2_SMP1_Msk

    - -
    -
    - - - - -
    #define ADC_SMPR2_SMP1_Msk   (0x7UL << ADC_SMPR2_SMP1_Pos)
    -
    -

    0x00000038

    - -
    -
    - -

    ◆ ADC_SMPR2_SMP1

    - -
    -
    - - - - -
    #define ADC_SMPR2_SMP1   ADC_SMPR2_SMP1_Msk
    -
    -

    SMP1[2:0] bits (Channel 1 Sample time selection)

    - -
    -
    - -

    ◆ ADC_SMPR2_SMP1_0

    - -
    -
    - - - - -
    #define ADC_SMPR2_SMP1_0   (0x1UL << ADC_SMPR2_SMP1_Pos)
    -
    -

    0x00000008

    - -
    -
    - -

    ◆ ADC_SMPR2_SMP1_1

    - -
    -
    - - - - -
    #define ADC_SMPR2_SMP1_1   (0x2UL << ADC_SMPR2_SMP1_Pos)
    -
    -

    0x00000010

    - -
    -
    - -

    ◆ ADC_SMPR2_SMP1_2

    - -
    -
    - - - - -
    #define ADC_SMPR2_SMP1_2   (0x4UL << ADC_SMPR2_SMP1_Pos)
    -
    -

    0x00000020

    - -
    -
    - -

    ◆ ADC_SMPR2_SMP2_Pos

    - -
    -
    - - - - -
    #define ADC_SMPR2_SMP2_Pos   (6U)
    -
    - -
    -
    - -

    ◆ ADC_SMPR2_SMP2_Msk

    - -
    -
    - - - - -
    #define ADC_SMPR2_SMP2_Msk   (0x7UL << ADC_SMPR2_SMP2_Pos)
    -
    -

    0x000001C0

    - -
    -
    - -

    ◆ ADC_SMPR2_SMP2

    - -
    -
    - - - - -
    #define ADC_SMPR2_SMP2   ADC_SMPR2_SMP2_Msk
    -
    -

    SMP2[2:0] bits (Channel 2 Sample time selection)

    - -
    -
    - -

    ◆ ADC_SMPR2_SMP2_0

    - -
    -
    - - - - -
    #define ADC_SMPR2_SMP2_0   (0x1UL << ADC_SMPR2_SMP2_Pos)
    -
    -

    0x00000040

    - -
    -
    - -

    ◆ ADC_SMPR2_SMP2_1

    - -
    -
    - - - - -
    #define ADC_SMPR2_SMP2_1   (0x2UL << ADC_SMPR2_SMP2_Pos)
    -
    -

    0x00000080

    - -
    -
    - -

    ◆ ADC_SMPR2_SMP2_2

    - -
    -
    - - - - -
    #define ADC_SMPR2_SMP2_2   (0x4UL << ADC_SMPR2_SMP2_Pos)
    -
    -

    0x00000100

    - -
    -
    - -

    ◆ ADC_SMPR2_SMP3_Pos

    - -
    -
    - - - - -
    #define ADC_SMPR2_SMP3_Pos   (9U)
    -
    - -
    -
    - -

    ◆ ADC_SMPR2_SMP3_Msk

    - -
    -
    - - - - -
    #define ADC_SMPR2_SMP3_Msk   (0x7UL << ADC_SMPR2_SMP3_Pos)
    -
    -

    0x00000E00

    - -
    -
    - -

    ◆ ADC_SMPR2_SMP3

    - -
    -
    - - - - -
    #define ADC_SMPR2_SMP3   ADC_SMPR2_SMP3_Msk
    -
    -

    SMP3[2:0] bits (Channel 3 Sample time selection)

    - -
    -
    - -

    ◆ ADC_SMPR2_SMP3_0

    - -
    -
    - - - - -
    #define ADC_SMPR2_SMP3_0   (0x1UL << ADC_SMPR2_SMP3_Pos)
    -
    -

    0x00000200

    - -
    -
    - -

    ◆ ADC_SMPR2_SMP3_1

    - -
    -
    - - - - -
    #define ADC_SMPR2_SMP3_1   (0x2UL << ADC_SMPR2_SMP3_Pos)
    -
    -

    0x00000400

    - -
    -
    - -

    ◆ ADC_SMPR2_SMP3_2

    - -
    -
    - - - - -
    #define ADC_SMPR2_SMP3_2   (0x4UL << ADC_SMPR2_SMP3_Pos)
    -
    -

    0x00000800

    - -
    -
    - -

    ◆ ADC_SMPR2_SMP4_Pos

    - -
    -
    - - - - -
    #define ADC_SMPR2_SMP4_Pos   (12U)
    -
    - -
    -
    - -

    ◆ ADC_SMPR2_SMP4_Msk

    - -
    -
    - - - - -
    #define ADC_SMPR2_SMP4_Msk   (0x7UL << ADC_SMPR2_SMP4_Pos)
    -
    -

    0x00007000

    - -
    -
    - -

    ◆ ADC_SMPR2_SMP4

    - -
    -
    - - - - -
    #define ADC_SMPR2_SMP4   ADC_SMPR2_SMP4_Msk
    -
    -

    SMP4[2:0] bits (Channel 4 Sample time selection)

    - -
    -
    - -

    ◆ ADC_SMPR2_SMP4_0

    - -
    -
    - - - - -
    #define ADC_SMPR2_SMP4_0   (0x1UL << ADC_SMPR2_SMP4_Pos)
    -
    -

    0x00001000

    - -
    -
    - -

    ◆ ADC_SMPR2_SMP4_1

    - -
    -
    - - - - -
    #define ADC_SMPR2_SMP4_1   (0x2UL << ADC_SMPR2_SMP4_Pos)
    -
    -

    0x00002000

    - -
    -
    - -

    ◆ ADC_SMPR2_SMP4_2

    - -
    -
    - - - - -
    #define ADC_SMPR2_SMP4_2   (0x4UL << ADC_SMPR2_SMP4_Pos)
    -
    -

    0x00004000

    - -
    -
    - -

    ◆ ADC_SMPR2_SMP5_Pos

    - -
    -
    - - - - -
    #define ADC_SMPR2_SMP5_Pos   (15U)
    -
    - -
    -
    - -

    ◆ ADC_SMPR2_SMP5_Msk

    - -
    -
    - - - - -
    #define ADC_SMPR2_SMP5_Msk   (0x7UL << ADC_SMPR2_SMP5_Pos)
    -
    -

    0x00038000

    - -
    -
    - -

    ◆ ADC_SMPR2_SMP5

    - -
    -
    - - - - -
    #define ADC_SMPR2_SMP5   ADC_SMPR2_SMP5_Msk
    -
    -

    SMP5[2:0] bits (Channel 5 Sample time selection)

    - -
    -
    - -

    ◆ ADC_SMPR2_SMP5_0

    - -
    -
    - - - - -
    #define ADC_SMPR2_SMP5_0   (0x1UL << ADC_SMPR2_SMP5_Pos)
    -
    -

    0x00008000

    - -
    -
    - -

    ◆ ADC_SMPR2_SMP5_1

    - -
    -
    - - - - -
    #define ADC_SMPR2_SMP5_1   (0x2UL << ADC_SMPR2_SMP5_Pos)
    -
    -

    0x00010000

    - -
    -
    - -

    ◆ ADC_SMPR2_SMP5_2

    - -
    -
    - - - - -
    #define ADC_SMPR2_SMP5_2   (0x4UL << ADC_SMPR2_SMP5_Pos)
    -
    -

    0x00020000

    - -
    -
    - -

    ◆ ADC_SMPR2_SMP6_Pos

    - -
    -
    - - - - -
    #define ADC_SMPR2_SMP6_Pos   (18U)
    -
    - -
    -
    - -

    ◆ ADC_SMPR2_SMP6_Msk

    - -
    -
    - - - - -
    #define ADC_SMPR2_SMP6_Msk   (0x7UL << ADC_SMPR2_SMP6_Pos)
    -
    -

    0x001C0000

    - -
    -
    - -

    ◆ ADC_SMPR2_SMP6

    - -
    -
    - - - - -
    #define ADC_SMPR2_SMP6   ADC_SMPR2_SMP6_Msk
    -
    -

    SMP6[2:0] bits (Channel 6 Sample time selection)

    - -
    -
    - -

    ◆ ADC_SMPR2_SMP6_0

    - -
    -
    - - - - -
    #define ADC_SMPR2_SMP6_0   (0x1UL << ADC_SMPR2_SMP6_Pos)
    -
    -

    0x00040000

    - -
    -
    - -

    ◆ ADC_SMPR2_SMP6_1

    - -
    -
    - - - - -
    #define ADC_SMPR2_SMP6_1   (0x2UL << ADC_SMPR2_SMP6_Pos)
    -
    -

    0x00080000

    - -
    -
    - -

    ◆ ADC_SMPR2_SMP6_2

    - -
    -
    - - - - -
    #define ADC_SMPR2_SMP6_2   (0x4UL << ADC_SMPR2_SMP6_Pos)
    -
    -

    0x00100000

    - -
    -
    - -

    ◆ ADC_SMPR2_SMP7_Pos

    - -
    -
    - - - - -
    #define ADC_SMPR2_SMP7_Pos   (21U)
    -
    - -
    -
    - -

    ◆ ADC_SMPR2_SMP7_Msk

    - -
    -
    - - - - -
    #define ADC_SMPR2_SMP7_Msk   (0x7UL << ADC_SMPR2_SMP7_Pos)
    -
    -

    0x00E00000

    - -
    -
    - -

    ◆ ADC_SMPR2_SMP7

    - -
    -
    - - - - -
    #define ADC_SMPR2_SMP7   ADC_SMPR2_SMP7_Msk
    -
    -

    SMP7[2:0] bits (Channel 7 Sample time selection)

    - -
    -
    - -

    ◆ ADC_SMPR2_SMP7_0

    - -
    -
    - - - - -
    #define ADC_SMPR2_SMP7_0   (0x1UL << ADC_SMPR2_SMP7_Pos)
    -
    -

    0x00200000

    - -
    -
    - -

    ◆ ADC_SMPR2_SMP7_1

    - -
    -
    - - - - -
    #define ADC_SMPR2_SMP7_1   (0x2UL << ADC_SMPR2_SMP7_Pos)
    -
    -

    0x00400000

    - -
    -
    - -

    ◆ ADC_SMPR2_SMP7_2

    - -
    -
    - - - - -
    #define ADC_SMPR2_SMP7_2   (0x4UL << ADC_SMPR2_SMP7_Pos)
    -
    -

    0x00800000

    - -
    -
    - -

    ◆ ADC_SMPR2_SMP8_Pos

    - -
    -
    - - - - -
    #define ADC_SMPR2_SMP8_Pos   (24U)
    -
    - -
    -
    - -

    ◆ ADC_SMPR2_SMP8_Msk

    - -
    -
    - - - - -
    #define ADC_SMPR2_SMP8_Msk   (0x7UL << ADC_SMPR2_SMP8_Pos)
    -
    -

    0x07000000

    - -
    -
    - -

    ◆ ADC_SMPR2_SMP8

    - -
    -
    - - - - -
    #define ADC_SMPR2_SMP8   ADC_SMPR2_SMP8_Msk
    -
    -

    SMP8[2:0] bits (Channel 8 Sample time selection)

    - -
    -
    - -

    ◆ ADC_SMPR2_SMP8_0

    - -
    -
    - - - - -
    #define ADC_SMPR2_SMP8_0   (0x1UL << ADC_SMPR2_SMP8_Pos)
    -
    -

    0x01000000

    - -
    -
    - -

    ◆ ADC_SMPR2_SMP8_1

    - -
    -
    - - - - -
    #define ADC_SMPR2_SMP8_1   (0x2UL << ADC_SMPR2_SMP8_Pos)
    -
    -

    0x02000000

    - -
    -
    - -

    ◆ ADC_SMPR2_SMP8_2

    - -
    -
    - - - - -
    #define ADC_SMPR2_SMP8_2   (0x4UL << ADC_SMPR2_SMP8_Pos)
    -
    -

    0x04000000

    - -
    -
    - -

    ◆ ADC_SMPR2_SMP9_Pos

    - -
    -
    - - - - -
    #define ADC_SMPR2_SMP9_Pos   (27U)
    -
    - -
    -
    - -

    ◆ ADC_SMPR2_SMP9_Msk

    - -
    -
    - - - - -
    #define ADC_SMPR2_SMP9_Msk   (0x7UL << ADC_SMPR2_SMP9_Pos)
    -
    -

    0x38000000

    - -
    -
    - -

    ◆ ADC_SMPR2_SMP9

    - -
    -
    - - - - -
    #define ADC_SMPR2_SMP9   ADC_SMPR2_SMP9_Msk
    -
    -

    SMP9[2:0] bits (Channel 9 Sample time selection)

    - -
    -
    - -

    ◆ ADC_SMPR2_SMP9_0

    - -
    -
    - - - - -
    #define ADC_SMPR2_SMP9_0   (0x1UL << ADC_SMPR2_SMP9_Pos)
    -
    -

    0x08000000

    - -
    -
    - -

    ◆ ADC_SMPR2_SMP9_1

    - -
    -
    - - - - -
    #define ADC_SMPR2_SMP9_1   (0x2UL << ADC_SMPR2_SMP9_Pos)
    -
    -

    0x10000000

    - -
    -
    - -

    ◆ ADC_SMPR2_SMP9_2

    - -
    -
    - - - - -
    #define ADC_SMPR2_SMP9_2   (0x4UL << ADC_SMPR2_SMP9_Pos)
    -
    -

    0x20000000

    - -
    -
    - -

    ◆ ADC_JOFR1_JOFFSET1_Pos

    - -
    -
    - - - - -
    #define ADC_JOFR1_JOFFSET1_Pos   (0U)
    -
    - -
    -
    - -

    ◆ ADC_JOFR1_JOFFSET1_Msk

    - -
    -
    - - - - -
    #define ADC_JOFR1_JOFFSET1_Msk   (0xFFFUL << ADC_JOFR1_JOFFSET1_Pos)
    -
    -

    0x00000FFF

    - -
    -
    - -

    ◆ ADC_JOFR1_JOFFSET1

    - -
    -
    - - - - -
    #define ADC_JOFR1_JOFFSET1   ADC_JOFR1_JOFFSET1_Msk
    -
    -

    Data offset for injected channel 1

    - -
    -
    - -

    ◆ ADC_JOFR2_JOFFSET2_Pos

    - -
    -
    - - - - -
    #define ADC_JOFR2_JOFFSET2_Pos   (0U)
    -
    - -
    -
    - -

    ◆ ADC_JOFR2_JOFFSET2_Msk

    - -
    -
    - - - - -
    #define ADC_JOFR2_JOFFSET2_Msk   (0xFFFUL << ADC_JOFR2_JOFFSET2_Pos)
    -
    -

    0x00000FFF

    - -
    -
    - -

    ◆ ADC_JOFR2_JOFFSET2

    - -
    -
    - - - - -
    #define ADC_JOFR2_JOFFSET2   ADC_JOFR2_JOFFSET2_Msk
    -
    -

    Data offset for injected channel 2

    - -
    -
    - -

    ◆ ADC_JOFR3_JOFFSET3_Pos

    - -
    -
    - - - - -
    #define ADC_JOFR3_JOFFSET3_Pos   (0U)
    -
    - -
    -
    - -

    ◆ ADC_JOFR3_JOFFSET3_Msk

    - -
    -
    - - - - -
    #define ADC_JOFR3_JOFFSET3_Msk   (0xFFFUL << ADC_JOFR3_JOFFSET3_Pos)
    -
    -

    0x00000FFF

    - -
    -
    - -

    ◆ ADC_JOFR3_JOFFSET3

    - -
    -
    - - - - -
    #define ADC_JOFR3_JOFFSET3   ADC_JOFR3_JOFFSET3_Msk
    -
    -

    Data offset for injected channel 3

    - -
    -
    - -

    ◆ ADC_JOFR4_JOFFSET4_Pos

    - -
    -
    - - - - -
    #define ADC_JOFR4_JOFFSET4_Pos   (0U)
    -
    - -
    -
    - -

    ◆ ADC_JOFR4_JOFFSET4_Msk

    - -
    -
    - - - - -
    #define ADC_JOFR4_JOFFSET4_Msk   (0xFFFUL << ADC_JOFR4_JOFFSET4_Pos)
    -
    -

    0x00000FFF

    - -
    -
    - -

    ◆ ADC_JOFR4_JOFFSET4

    - -
    -
    - - - - -
    #define ADC_JOFR4_JOFFSET4   ADC_JOFR4_JOFFSET4_Msk
    -
    -

    Data offset for injected channel 4

    - -
    -
    - -

    ◆ ADC_HTR_HT_Pos

    - -
    -
    - - - - -
    #define ADC_HTR_HT_Pos   (0U)
    -
    - -
    -
    - -

    ◆ ADC_HTR_HT_Msk

    - -
    -
    - - - - -
    #define ADC_HTR_HT_Msk   (0xFFFUL << ADC_HTR_HT_Pos)
    -
    -

    0x00000FFF

    - -
    -
    - -

    ◆ ADC_HTR_HT

    - -
    -
    - - - - -
    #define ADC_HTR_HT   ADC_HTR_HT_Msk
    -
    -

    Analog watchdog high threshold

    - -
    -
    - -

    ◆ ADC_LTR_LT_Pos

    - -
    -
    - - - - -
    #define ADC_LTR_LT_Pos   (0U)
    -
    - -
    -
    - -

    ◆ ADC_LTR_LT_Msk

    - -
    -
    - - - - -
    #define ADC_LTR_LT_Msk   (0xFFFUL << ADC_LTR_LT_Pos)
    -
    -

    0x00000FFF

    - -
    -
    - -

    ◆ ADC_LTR_LT

    - -
    -
    - - - - -
    #define ADC_LTR_LT   ADC_LTR_LT_Msk
    -
    -

    Analog watchdog low threshold

    - -
    -
    - -

    ◆ ADC_SQR1_SQ13_Pos

    - -
    -
    - - - - -
    #define ADC_SQR1_SQ13_Pos   (0U)
    -
    - -
    -
    - -

    ◆ ADC_SQR1_SQ13_Msk

    - -
    -
    - - - - -
    #define ADC_SQR1_SQ13_Msk   (0x1FUL << ADC_SQR1_SQ13_Pos)
    -
    -

    0x0000001F

    - -
    -
    - -

    ◆ ADC_SQR1_SQ13

    - -
    -
    - - - - -
    #define ADC_SQR1_SQ13   ADC_SQR1_SQ13_Msk
    -
    -

    SQ13[4:0] bits (13th conversion in regular sequence)

    - -
    -
    - -

    ◆ ADC_SQR1_SQ13_0

    - -
    -
    - - - - -
    #define ADC_SQR1_SQ13_0   (0x01UL << ADC_SQR1_SQ13_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ ADC_SQR1_SQ13_1

    - -
    -
    - - - - -
    #define ADC_SQR1_SQ13_1   (0x02UL << ADC_SQR1_SQ13_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ ADC_SQR1_SQ13_2

    - -
    -
    - - - - -
    #define ADC_SQR1_SQ13_2   (0x04UL << ADC_SQR1_SQ13_Pos)
    -
    -

    0x00000004

    - -
    -
    - -

    ◆ ADC_SQR1_SQ13_3

    - -
    -
    - - - - -
    #define ADC_SQR1_SQ13_3   (0x08UL << ADC_SQR1_SQ13_Pos)
    -
    -

    0x00000008

    - -
    -
    - -

    ◆ ADC_SQR1_SQ13_4

    - -
    -
    - - - - -
    #define ADC_SQR1_SQ13_4   (0x10UL << ADC_SQR1_SQ13_Pos)
    -
    -

    0x00000010

    - -
    -
    - -

    ◆ ADC_SQR1_SQ14_Pos

    - -
    -
    - - - - -
    #define ADC_SQR1_SQ14_Pos   (5U)
    -
    - -
    -
    - -

    ◆ ADC_SQR1_SQ14_Msk

    - -
    -
    - - - - -
    #define ADC_SQR1_SQ14_Msk   (0x1FUL << ADC_SQR1_SQ14_Pos)
    -
    -

    0x000003E0

    - -
    -
    - -

    ◆ ADC_SQR1_SQ14

    - -
    -
    - - - - -
    #define ADC_SQR1_SQ14   ADC_SQR1_SQ14_Msk
    -
    -

    SQ14[4:0] bits (14th conversion in regular sequence)

    - -
    -
    - -

    ◆ ADC_SQR1_SQ14_0

    - -
    -
    - - - - -
    #define ADC_SQR1_SQ14_0   (0x01UL << ADC_SQR1_SQ14_Pos)
    -
    -

    0x00000020

    - -
    -
    - -

    ◆ ADC_SQR1_SQ14_1

    - -
    -
    - - - - -
    #define ADC_SQR1_SQ14_1   (0x02UL << ADC_SQR1_SQ14_Pos)
    -
    -

    0x00000040

    - -
    -
    - -

    ◆ ADC_SQR1_SQ14_2

    - -
    -
    - - - - -
    #define ADC_SQR1_SQ14_2   (0x04UL << ADC_SQR1_SQ14_Pos)
    -
    -

    0x00000080

    - -
    -
    - -

    ◆ ADC_SQR1_SQ14_3

    - -
    -
    - - - - -
    #define ADC_SQR1_SQ14_3   (0x08UL << ADC_SQR1_SQ14_Pos)
    -
    -

    0x00000100

    - -
    -
    - -

    ◆ ADC_SQR1_SQ14_4

    - -
    -
    - - - - -
    #define ADC_SQR1_SQ14_4   (0x10UL << ADC_SQR1_SQ14_Pos)
    -
    -

    0x00000200

    - -
    -
    - -

    ◆ ADC_SQR1_SQ15_Pos

    - -
    -
    - - - - -
    #define ADC_SQR1_SQ15_Pos   (10U)
    -
    - -
    -
    - -

    ◆ ADC_SQR1_SQ15_Msk

    - -
    -
    - - - - -
    #define ADC_SQR1_SQ15_Msk   (0x1FUL << ADC_SQR1_SQ15_Pos)
    -
    -

    0x00007C00

    - -
    -
    - -

    ◆ ADC_SQR1_SQ15

    - -
    -
    - - - - -
    #define ADC_SQR1_SQ15   ADC_SQR1_SQ15_Msk
    -
    -

    SQ15[4:0] bits (15th conversion in regular sequence)

    - -
    -
    - -

    ◆ ADC_SQR1_SQ15_0

    - -
    -
    - - - - -
    #define ADC_SQR1_SQ15_0   (0x01UL << ADC_SQR1_SQ15_Pos)
    -
    -

    0x00000400

    - -
    -
    - -

    ◆ ADC_SQR1_SQ15_1

    - -
    -
    - - - - -
    #define ADC_SQR1_SQ15_1   (0x02UL << ADC_SQR1_SQ15_Pos)
    -
    -

    0x00000800

    - -
    -
    - -

    ◆ ADC_SQR1_SQ15_2

    - -
    -
    - - - - -
    #define ADC_SQR1_SQ15_2   (0x04UL << ADC_SQR1_SQ15_Pos)
    -
    -

    0x00001000

    - -
    -
    - -

    ◆ ADC_SQR1_SQ15_3

    - -
    -
    - - - - -
    #define ADC_SQR1_SQ15_3   (0x08UL << ADC_SQR1_SQ15_Pos)
    -
    -

    0x00002000

    - -
    -
    - -

    ◆ ADC_SQR1_SQ15_4

    - -
    -
    - - - - -
    #define ADC_SQR1_SQ15_4   (0x10UL << ADC_SQR1_SQ15_Pos)
    -
    -

    0x00004000

    - -
    -
    - -

    ◆ ADC_SQR1_SQ16_Pos

    - -
    -
    - - - - -
    #define ADC_SQR1_SQ16_Pos   (15U)
    -
    - -
    -
    - -

    ◆ ADC_SQR1_SQ16_Msk

    - -
    -
    - - - - -
    #define ADC_SQR1_SQ16_Msk   (0x1FUL << ADC_SQR1_SQ16_Pos)
    -
    -

    0x000F8000

    - -
    -
    - -

    ◆ ADC_SQR1_SQ16

    - -
    -
    - - - - -
    #define ADC_SQR1_SQ16   ADC_SQR1_SQ16_Msk
    -
    -

    SQ16[4:0] bits (16th conversion in regular sequence)

    - -
    -
    - -

    ◆ ADC_SQR1_SQ16_0

    - -
    -
    - - - - -
    #define ADC_SQR1_SQ16_0   (0x01UL << ADC_SQR1_SQ16_Pos)
    -
    -

    0x00008000

    - -
    -
    - -

    ◆ ADC_SQR1_SQ16_1

    - -
    -
    - - - - -
    #define ADC_SQR1_SQ16_1   (0x02UL << ADC_SQR1_SQ16_Pos)
    -
    -

    0x00010000

    - -
    -
    - -

    ◆ ADC_SQR1_SQ16_2

    - -
    -
    - - - - -
    #define ADC_SQR1_SQ16_2   (0x04UL << ADC_SQR1_SQ16_Pos)
    -
    -

    0x00020000

    - -
    -
    - -

    ◆ ADC_SQR1_SQ16_3

    - -
    -
    - - - - -
    #define ADC_SQR1_SQ16_3   (0x08UL << ADC_SQR1_SQ16_Pos)
    -
    -

    0x00040000

    - -
    -
    - -

    ◆ ADC_SQR1_SQ16_4

    - -
    -
    - - - - -
    #define ADC_SQR1_SQ16_4   (0x10UL << ADC_SQR1_SQ16_Pos)
    -
    -

    0x00080000

    - -
    -
    - -

    ◆ ADC_SQR1_L_Pos

    - -
    -
    - - - - -
    #define ADC_SQR1_L_Pos   (20U)
    -
    - -
    -
    - -

    ◆ ADC_SQR1_L_Msk

    - -
    -
    - - - - -
    #define ADC_SQR1_L_Msk   (0xFUL << ADC_SQR1_L_Pos)
    -
    -

    0x00F00000

    - -
    -
    - -

    ◆ ADC_SQR1_L

    - -
    -
    - - - - -
    #define ADC_SQR1_L   ADC_SQR1_L_Msk
    -
    -

    L[3:0] bits (Regular channel sequence length)

    - -
    -
    - -

    ◆ ADC_SQR1_L_0

    - -
    -
    - - - - -
    #define ADC_SQR1_L_0   (0x1UL << ADC_SQR1_L_Pos)
    -
    -

    0x00100000

    - -
    -
    - -

    ◆ ADC_SQR1_L_1

    - -
    -
    - - - - -
    #define ADC_SQR1_L_1   (0x2UL << ADC_SQR1_L_Pos)
    -
    -

    0x00200000

    - -
    -
    - -

    ◆ ADC_SQR1_L_2

    - -
    -
    - - - - -
    #define ADC_SQR1_L_2   (0x4UL << ADC_SQR1_L_Pos)
    -
    -

    0x00400000

    - -
    -
    - -

    ◆ ADC_SQR1_L_3

    - -
    -
    - - - - -
    #define ADC_SQR1_L_3   (0x8UL << ADC_SQR1_L_Pos)
    -
    -

    0x00800000

    - -
    -
    - -

    ◆ ADC_SQR2_SQ7_Pos

    - -
    -
    - - - - -
    #define ADC_SQR2_SQ7_Pos   (0U)
    -
    - -
    -
    - -

    ◆ ADC_SQR2_SQ7_Msk

    - -
    -
    - - - - -
    #define ADC_SQR2_SQ7_Msk   (0x1FUL << ADC_SQR2_SQ7_Pos)
    -
    -

    0x0000001F

    - -
    -
    - -

    ◆ ADC_SQR2_SQ7

    - -
    -
    - - - - -
    #define ADC_SQR2_SQ7   ADC_SQR2_SQ7_Msk
    -
    -

    SQ7[4:0] bits (7th conversion in regular sequence)

    - -
    -
    - -

    ◆ ADC_SQR2_SQ7_0

    - -
    -
    - - - - -
    #define ADC_SQR2_SQ7_0   (0x01UL << ADC_SQR2_SQ7_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ ADC_SQR2_SQ7_1

    - -
    -
    - - - - -
    #define ADC_SQR2_SQ7_1   (0x02UL << ADC_SQR2_SQ7_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ ADC_SQR2_SQ7_2

    - -
    -
    - - - - -
    #define ADC_SQR2_SQ7_2   (0x04UL << ADC_SQR2_SQ7_Pos)
    -
    -

    0x00000004

    - -
    -
    - -

    ◆ ADC_SQR2_SQ7_3

    - -
    -
    - - - - -
    #define ADC_SQR2_SQ7_3   (0x08UL << ADC_SQR2_SQ7_Pos)
    -
    -

    0x00000008

    - -
    -
    - -

    ◆ ADC_SQR2_SQ7_4

    - -
    -
    - - - - -
    #define ADC_SQR2_SQ7_4   (0x10UL << ADC_SQR2_SQ7_Pos)
    -
    -

    0x00000010

    - -
    -
    - -

    ◆ ADC_SQR2_SQ8_Pos

    - -
    -
    - - - - -
    #define ADC_SQR2_SQ8_Pos   (5U)
    -
    - -
    -
    - -

    ◆ ADC_SQR2_SQ8_Msk

    - -
    -
    - - - - -
    #define ADC_SQR2_SQ8_Msk   (0x1FUL << ADC_SQR2_SQ8_Pos)
    -
    -

    0x000003E0

    - -
    -
    - -

    ◆ ADC_SQR2_SQ8

    - -
    -
    - - - - -
    #define ADC_SQR2_SQ8   ADC_SQR2_SQ8_Msk
    -
    -

    SQ8[4:0] bits (8th conversion in regular sequence)

    - -
    -
    - -

    ◆ ADC_SQR2_SQ8_0

    - -
    -
    - - - - -
    #define ADC_SQR2_SQ8_0   (0x01UL << ADC_SQR2_SQ8_Pos)
    -
    -

    0x00000020

    - -
    -
    - -

    ◆ ADC_SQR2_SQ8_1

    - -
    -
    - - - - -
    #define ADC_SQR2_SQ8_1   (0x02UL << ADC_SQR2_SQ8_Pos)
    -
    -

    0x00000040

    - -
    -
    - -

    ◆ ADC_SQR2_SQ8_2

    - -
    -
    - - - - -
    #define ADC_SQR2_SQ8_2   (0x04UL << ADC_SQR2_SQ8_Pos)
    -
    -

    0x00000080

    - -
    -
    - -

    ◆ ADC_SQR2_SQ8_3

    - -
    -
    - - - - -
    #define ADC_SQR2_SQ8_3   (0x08UL << ADC_SQR2_SQ8_Pos)
    -
    -

    0x00000100

    - -
    -
    - -

    ◆ ADC_SQR2_SQ8_4

    - -
    -
    - - - - -
    #define ADC_SQR2_SQ8_4   (0x10UL << ADC_SQR2_SQ8_Pos)
    -
    -

    0x00000200

    - -
    -
    - -

    ◆ ADC_SQR2_SQ9_Pos

    - -
    -
    - - - - -
    #define ADC_SQR2_SQ9_Pos   (10U)
    -
    - -
    -
    - -

    ◆ ADC_SQR2_SQ9_Msk

    - -
    -
    - - - - -
    #define ADC_SQR2_SQ9_Msk   (0x1FUL << ADC_SQR2_SQ9_Pos)
    -
    -

    0x00007C00

    - -
    -
    - -

    ◆ ADC_SQR2_SQ9

    - -
    -
    - - - - -
    #define ADC_SQR2_SQ9   ADC_SQR2_SQ9_Msk
    -
    -

    SQ9[4:0] bits (9th conversion in regular sequence)

    - -
    -
    - -

    ◆ ADC_SQR2_SQ9_0

    - -
    -
    - - - - -
    #define ADC_SQR2_SQ9_0   (0x01UL << ADC_SQR2_SQ9_Pos)
    -
    -

    0x00000400

    - -
    -
    - -

    ◆ ADC_SQR2_SQ9_1

    - -
    -
    - - - - -
    #define ADC_SQR2_SQ9_1   (0x02UL << ADC_SQR2_SQ9_Pos)
    -
    -

    0x00000800

    - -
    -
    - -

    ◆ ADC_SQR2_SQ9_2

    - -
    -
    - - - - -
    #define ADC_SQR2_SQ9_2   (0x04UL << ADC_SQR2_SQ9_Pos)
    -
    -

    0x00001000

    - -
    -
    - -

    ◆ ADC_SQR2_SQ9_3

    - -
    -
    - - - - -
    #define ADC_SQR2_SQ9_3   (0x08UL << ADC_SQR2_SQ9_Pos)
    -
    -

    0x00002000

    - -
    -
    - -

    ◆ ADC_SQR2_SQ9_4

    - -
    -
    - - - - -
    #define ADC_SQR2_SQ9_4   (0x10UL << ADC_SQR2_SQ9_Pos)
    -
    -

    0x00004000

    - -
    -
    - -

    ◆ ADC_SQR2_SQ10_Pos

    - -
    -
    - - - - -
    #define ADC_SQR2_SQ10_Pos   (15U)
    -
    - -
    -
    - -

    ◆ ADC_SQR2_SQ10_Msk

    - -
    -
    - - - - -
    #define ADC_SQR2_SQ10_Msk   (0x1FUL << ADC_SQR2_SQ10_Pos)
    -
    -

    0x000F8000

    - -
    -
    - -

    ◆ ADC_SQR2_SQ10

    - -
    -
    - - - - -
    #define ADC_SQR2_SQ10   ADC_SQR2_SQ10_Msk
    -
    -

    SQ10[4:0] bits (10th conversion in regular sequence)

    - -
    -
    - -

    ◆ ADC_SQR2_SQ10_0

    - -
    -
    - - - - -
    #define ADC_SQR2_SQ10_0   (0x01UL << ADC_SQR2_SQ10_Pos)
    -
    -

    0x00008000

    - -
    -
    - -

    ◆ ADC_SQR2_SQ10_1

    - -
    -
    - - - - -
    #define ADC_SQR2_SQ10_1   (0x02UL << ADC_SQR2_SQ10_Pos)
    -
    -

    0x00010000

    - -
    -
    - -

    ◆ ADC_SQR2_SQ10_2

    - -
    -
    - - - - -
    #define ADC_SQR2_SQ10_2   (0x04UL << ADC_SQR2_SQ10_Pos)
    -
    -

    0x00020000

    - -
    -
    - -

    ◆ ADC_SQR2_SQ10_3

    - -
    -
    - - - - -
    #define ADC_SQR2_SQ10_3   (0x08UL << ADC_SQR2_SQ10_Pos)
    -
    -

    0x00040000

    - -
    -
    - -

    ◆ ADC_SQR2_SQ10_4

    - -
    -
    - - - - -
    #define ADC_SQR2_SQ10_4   (0x10UL << ADC_SQR2_SQ10_Pos)
    -
    -

    0x00080000

    - -
    -
    - -

    ◆ ADC_SQR2_SQ11_Pos

    - -
    -
    - - - - -
    #define ADC_SQR2_SQ11_Pos   (20U)
    -
    - -
    -
    - -

    ◆ ADC_SQR2_SQ11_Msk

    - -
    -
    - - - - -
    #define ADC_SQR2_SQ11_Msk   (0x1FUL << ADC_SQR2_SQ11_Pos)
    -
    -

    0x01F00000

    - -
    -
    - -

    ◆ ADC_SQR2_SQ11

    - -
    -
    - - - - -
    #define ADC_SQR2_SQ11   ADC_SQR2_SQ11_Msk
    -
    -

    SQ11[4:0] bits (11th conversion in regular sequence)

    - -
    -
    - -

    ◆ ADC_SQR2_SQ11_0

    - -
    -
    - - - - -
    #define ADC_SQR2_SQ11_0   (0x01UL << ADC_SQR2_SQ11_Pos)
    -
    -

    0x00100000

    - -
    -
    - -

    ◆ ADC_SQR2_SQ11_1

    - -
    -
    - - - - -
    #define ADC_SQR2_SQ11_1   (0x02UL << ADC_SQR2_SQ11_Pos)
    -
    -

    0x00200000

    - -
    -
    - -

    ◆ ADC_SQR2_SQ11_2

    - -
    -
    - - - - -
    #define ADC_SQR2_SQ11_2   (0x04UL << ADC_SQR2_SQ11_Pos)
    -
    -

    0x00400000

    - -
    -
    - -

    ◆ ADC_SQR2_SQ11_3

    - -
    -
    - - - - -
    #define ADC_SQR2_SQ11_3   (0x08UL << ADC_SQR2_SQ11_Pos)
    -
    -

    0x00800000

    - -
    -
    - -

    ◆ ADC_SQR2_SQ11_4

    - -
    -
    - - - - -
    #define ADC_SQR2_SQ11_4   (0x10UL << ADC_SQR2_SQ11_Pos)
    -
    -

    0x01000000

    - -
    -
    - -

    ◆ ADC_SQR2_SQ12_Pos

    - -
    -
    - - - - -
    #define ADC_SQR2_SQ12_Pos   (25U)
    -
    - -
    -
    - -

    ◆ ADC_SQR2_SQ12_Msk

    - -
    -
    - - - - -
    #define ADC_SQR2_SQ12_Msk   (0x1FUL << ADC_SQR2_SQ12_Pos)
    -
    -

    0x3E000000

    - -
    -
    - -

    ◆ ADC_SQR2_SQ12

    - -
    -
    - - - - -
    #define ADC_SQR2_SQ12   ADC_SQR2_SQ12_Msk
    -
    -

    SQ12[4:0] bits (12th conversion in regular sequence)

    - -
    -
    - -

    ◆ ADC_SQR2_SQ12_0

    - -
    -
    - - - - -
    #define ADC_SQR2_SQ12_0   (0x01UL << ADC_SQR2_SQ12_Pos)
    -
    -

    0x02000000

    - -
    -
    - -

    ◆ ADC_SQR2_SQ12_1

    - -
    -
    - - - - -
    #define ADC_SQR2_SQ12_1   (0x02UL << ADC_SQR2_SQ12_Pos)
    -
    -

    0x04000000

    - -
    -
    - -

    ◆ ADC_SQR2_SQ12_2

    - -
    -
    - - - - -
    #define ADC_SQR2_SQ12_2   (0x04UL << ADC_SQR2_SQ12_Pos)
    -
    -

    0x08000000

    - -
    -
    - -

    ◆ ADC_SQR2_SQ12_3

    - -
    -
    - - - - -
    #define ADC_SQR2_SQ12_3   (0x08UL << ADC_SQR2_SQ12_Pos)
    -
    -

    0x10000000

    - -
    -
    - -

    ◆ ADC_SQR2_SQ12_4

    - -
    -
    - - - - -
    #define ADC_SQR2_SQ12_4   (0x10UL << ADC_SQR2_SQ12_Pos)
    -
    -

    0x20000000

    - -
    -
    - -

    ◆ ADC_SQR3_SQ1_Pos

    - -
    -
    - - - - -
    #define ADC_SQR3_SQ1_Pos   (0U)
    -
    - -
    -
    - -

    ◆ ADC_SQR3_SQ1_Msk

    - -
    -
    - - - - -
    #define ADC_SQR3_SQ1_Msk   (0x1FUL << ADC_SQR3_SQ1_Pos)
    -
    -

    0x0000001F

    - -
    -
    - -

    ◆ ADC_SQR3_SQ1

    - -
    -
    - - - - -
    #define ADC_SQR3_SQ1   ADC_SQR3_SQ1_Msk
    -
    -

    SQ1[4:0] bits (1st conversion in regular sequence)

    - -
    -
    - -

    ◆ ADC_SQR3_SQ1_0

    - -
    -
    - - - - -
    #define ADC_SQR3_SQ1_0   (0x01UL << ADC_SQR3_SQ1_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ ADC_SQR3_SQ1_1

    - -
    -
    - - - - -
    #define ADC_SQR3_SQ1_1   (0x02UL << ADC_SQR3_SQ1_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ ADC_SQR3_SQ1_2

    - -
    -
    - - - - -
    #define ADC_SQR3_SQ1_2   (0x04UL << ADC_SQR3_SQ1_Pos)
    -
    -

    0x00000004

    - -
    -
    - -

    ◆ ADC_SQR3_SQ1_3

    - -
    -
    - - - - -
    #define ADC_SQR3_SQ1_3   (0x08UL << ADC_SQR3_SQ1_Pos)
    -
    -

    0x00000008

    - -
    -
    - -

    ◆ ADC_SQR3_SQ1_4

    - -
    -
    - - - - -
    #define ADC_SQR3_SQ1_4   (0x10UL << ADC_SQR3_SQ1_Pos)
    -
    -

    0x00000010

    - -
    -
    - -

    ◆ ADC_SQR3_SQ2_Pos

    - -
    -
    - - - - -
    #define ADC_SQR3_SQ2_Pos   (5U)
    -
    - -
    -
    - -

    ◆ ADC_SQR3_SQ2_Msk

    - -
    -
    - - - - -
    #define ADC_SQR3_SQ2_Msk   (0x1FUL << ADC_SQR3_SQ2_Pos)
    -
    -

    0x000003E0

    - -
    -
    - -

    ◆ ADC_SQR3_SQ2

    - -
    -
    - - - - -
    #define ADC_SQR3_SQ2   ADC_SQR3_SQ2_Msk
    -
    -

    SQ2[4:0] bits (2nd conversion in regular sequence)

    - -
    -
    - -

    ◆ ADC_SQR3_SQ2_0

    - -
    -
    - - - - -
    #define ADC_SQR3_SQ2_0   (0x01UL << ADC_SQR3_SQ2_Pos)
    -
    -

    0x00000020

    - -
    -
    - -

    ◆ ADC_SQR3_SQ2_1

    - -
    -
    - - - - -
    #define ADC_SQR3_SQ2_1   (0x02UL << ADC_SQR3_SQ2_Pos)
    -
    -

    0x00000040

    - -
    -
    - -

    ◆ ADC_SQR3_SQ2_2

    - -
    -
    - - - - -
    #define ADC_SQR3_SQ2_2   (0x04UL << ADC_SQR3_SQ2_Pos)
    -
    -

    0x00000080

    - -
    -
    - -

    ◆ ADC_SQR3_SQ2_3

    - -
    -
    - - - - -
    #define ADC_SQR3_SQ2_3   (0x08UL << ADC_SQR3_SQ2_Pos)
    -
    -

    0x00000100

    - -
    -
    - -

    ◆ ADC_SQR3_SQ2_4

    - -
    -
    - - - - -
    #define ADC_SQR3_SQ2_4   (0x10UL << ADC_SQR3_SQ2_Pos)
    -
    -

    0x00000200

    - -
    -
    - -

    ◆ ADC_SQR3_SQ3_Pos

    - -
    -
    - - - - -
    #define ADC_SQR3_SQ3_Pos   (10U)
    -
    - -
    -
    - -

    ◆ ADC_SQR3_SQ3_Msk

    - -
    -
    - - - - -
    #define ADC_SQR3_SQ3_Msk   (0x1FUL << ADC_SQR3_SQ3_Pos)
    -
    -

    0x00007C00

    - -
    -
    - -

    ◆ ADC_SQR3_SQ3

    - -
    -
    - - - - -
    #define ADC_SQR3_SQ3   ADC_SQR3_SQ3_Msk
    -
    -

    SQ3[4:0] bits (3rd conversion in regular sequence)

    - -
    -
    - -

    ◆ ADC_SQR3_SQ3_0

    - -
    -
    - - - - -
    #define ADC_SQR3_SQ3_0   (0x01UL << ADC_SQR3_SQ3_Pos)
    -
    -

    0x00000400

    - -
    -
    - -

    ◆ ADC_SQR3_SQ3_1

    - -
    -
    - - - - -
    #define ADC_SQR3_SQ3_1   (0x02UL << ADC_SQR3_SQ3_Pos)
    -
    -

    0x00000800

    - -
    -
    - -

    ◆ ADC_SQR3_SQ3_2

    - -
    -
    - - - - -
    #define ADC_SQR3_SQ3_2   (0x04UL << ADC_SQR3_SQ3_Pos)
    -
    -

    0x00001000

    - -
    -
    - -

    ◆ ADC_SQR3_SQ3_3

    - -
    -
    - - - - -
    #define ADC_SQR3_SQ3_3   (0x08UL << ADC_SQR3_SQ3_Pos)
    -
    -

    0x00002000

    - -
    -
    - -

    ◆ ADC_SQR3_SQ3_4

    - -
    -
    - - - - -
    #define ADC_SQR3_SQ3_4   (0x10UL << ADC_SQR3_SQ3_Pos)
    -
    -

    0x00004000

    - -
    -
    - -

    ◆ ADC_SQR3_SQ4_Pos

    - -
    -
    - - - - -
    #define ADC_SQR3_SQ4_Pos   (15U)
    -
    - -
    -
    - -

    ◆ ADC_SQR3_SQ4_Msk

    - -
    -
    - - - - -
    #define ADC_SQR3_SQ4_Msk   (0x1FUL << ADC_SQR3_SQ4_Pos)
    -
    -

    0x000F8000

    - -
    -
    - -

    ◆ ADC_SQR3_SQ4

    - -
    -
    - - - - -
    #define ADC_SQR3_SQ4   ADC_SQR3_SQ4_Msk
    -
    -

    SQ4[4:0] bits (4th conversion in regular sequence)

    - -
    -
    - -

    ◆ ADC_SQR3_SQ4_0

    - -
    -
    - - - - -
    #define ADC_SQR3_SQ4_0   (0x01UL << ADC_SQR3_SQ4_Pos)
    -
    -

    0x00008000

    - -
    -
    - -

    ◆ ADC_SQR3_SQ4_1

    - -
    -
    - - - - -
    #define ADC_SQR3_SQ4_1   (0x02UL << ADC_SQR3_SQ4_Pos)
    -
    -

    0x00010000

    - -
    -
    - -

    ◆ ADC_SQR3_SQ4_2

    - -
    -
    - - - - -
    #define ADC_SQR3_SQ4_2   (0x04UL << ADC_SQR3_SQ4_Pos)
    -
    -

    0x00020000

    - -
    -
    - -

    ◆ ADC_SQR3_SQ4_3

    - -
    -
    - - - - -
    #define ADC_SQR3_SQ4_3   (0x08UL << ADC_SQR3_SQ4_Pos)
    -
    -

    0x00040000

    - -
    -
    - -

    ◆ ADC_SQR3_SQ4_4

    - -
    -
    - - - - -
    #define ADC_SQR3_SQ4_4   (0x10UL << ADC_SQR3_SQ4_Pos)
    -
    -

    0x00080000

    - -
    -
    - -

    ◆ ADC_SQR3_SQ5_Pos

    - -
    -
    - - - - -
    #define ADC_SQR3_SQ5_Pos   (20U)
    -
    - -
    -
    - -

    ◆ ADC_SQR3_SQ5_Msk

    - -
    -
    - - - - -
    #define ADC_SQR3_SQ5_Msk   (0x1FUL << ADC_SQR3_SQ5_Pos)
    -
    -

    0x01F00000

    - -
    -
    - -

    ◆ ADC_SQR3_SQ5

    - -
    -
    - - - - -
    #define ADC_SQR3_SQ5   ADC_SQR3_SQ5_Msk
    -
    -

    SQ5[4:0] bits (5th conversion in regular sequence)

    - -
    -
    - -

    ◆ ADC_SQR3_SQ5_0

    - -
    -
    - - - - -
    #define ADC_SQR3_SQ5_0   (0x01UL << ADC_SQR3_SQ5_Pos)
    -
    -

    0x00100000

    - -
    -
    - -

    ◆ ADC_SQR3_SQ5_1

    - -
    -
    - - - - -
    #define ADC_SQR3_SQ5_1   (0x02UL << ADC_SQR3_SQ5_Pos)
    -
    -

    0x00200000

    - -
    -
    - -

    ◆ ADC_SQR3_SQ5_2

    - -
    -
    - - - - -
    #define ADC_SQR3_SQ5_2   (0x04UL << ADC_SQR3_SQ5_Pos)
    -
    -

    0x00400000

    - -
    -
    - -

    ◆ ADC_SQR3_SQ5_3

    - -
    -
    - - - - -
    #define ADC_SQR3_SQ5_3   (0x08UL << ADC_SQR3_SQ5_Pos)
    -
    -

    0x00800000

    - -
    -
    - -

    ◆ ADC_SQR3_SQ5_4

    - -
    -
    - - - - -
    #define ADC_SQR3_SQ5_4   (0x10UL << ADC_SQR3_SQ5_Pos)
    -
    -

    0x01000000

    - -
    -
    - -

    ◆ ADC_SQR3_SQ6_Pos

    - -
    -
    - - - - -
    #define ADC_SQR3_SQ6_Pos   (25U)
    -
    - -
    -
    - -

    ◆ ADC_SQR3_SQ6_Msk

    - -
    -
    - - - - -
    #define ADC_SQR3_SQ6_Msk   (0x1FUL << ADC_SQR3_SQ6_Pos)
    -
    -

    0x3E000000

    - -
    -
    - -

    ◆ ADC_SQR3_SQ6

    - -
    -
    - - - - -
    #define ADC_SQR3_SQ6   ADC_SQR3_SQ6_Msk
    -
    -

    SQ6[4:0] bits (6th conversion in regular sequence)

    - -
    -
    - -

    ◆ ADC_SQR3_SQ6_0

    - -
    -
    - - - - -
    #define ADC_SQR3_SQ6_0   (0x01UL << ADC_SQR3_SQ6_Pos)
    -
    -

    0x02000000

    - -
    -
    - -

    ◆ ADC_SQR3_SQ6_1

    - -
    -
    - - - - -
    #define ADC_SQR3_SQ6_1   (0x02UL << ADC_SQR3_SQ6_Pos)
    -
    -

    0x04000000

    - -
    -
    - -

    ◆ ADC_SQR3_SQ6_2

    - -
    -
    - - - - -
    #define ADC_SQR3_SQ6_2   (0x04UL << ADC_SQR3_SQ6_Pos)
    -
    -

    0x08000000

    - -
    -
    - -

    ◆ ADC_SQR3_SQ6_3

    - -
    -
    - - - - -
    #define ADC_SQR3_SQ6_3   (0x08UL << ADC_SQR3_SQ6_Pos)
    -
    -

    0x10000000

    - -
    -
    - -

    ◆ ADC_SQR3_SQ6_4

    - -
    -
    - - - - -
    #define ADC_SQR3_SQ6_4   (0x10UL << ADC_SQR3_SQ6_Pos)
    -
    -

    0x20000000

    - -
    -
    - -

    ◆ ADC_JSQR_JSQ1_Pos

    - -
    -
    - - - - -
    #define ADC_JSQR_JSQ1_Pos   (0U)
    -
    - -
    -
    - -

    ◆ ADC_JSQR_JSQ1_Msk

    - -
    -
    - - - - -
    #define ADC_JSQR_JSQ1_Msk   (0x1FUL << ADC_JSQR_JSQ1_Pos)
    -
    -

    0x0000001F

    - -
    -
    - -

    ◆ ADC_JSQR_JSQ1

    - -
    -
    - - - - -
    #define ADC_JSQR_JSQ1   ADC_JSQR_JSQ1_Msk
    -
    -

    JSQ1[4:0] bits (1st conversion in injected sequence)

    - -
    -
    - -

    ◆ ADC_JSQR_JSQ1_0

    - -
    -
    - - - - -
    #define ADC_JSQR_JSQ1_0   (0x01UL << ADC_JSQR_JSQ1_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ ADC_JSQR_JSQ1_1

    - -
    -
    - - - - -
    #define ADC_JSQR_JSQ1_1   (0x02UL << ADC_JSQR_JSQ1_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ ADC_JSQR_JSQ1_2

    - -
    -
    - - - - -
    #define ADC_JSQR_JSQ1_2   (0x04UL << ADC_JSQR_JSQ1_Pos)
    -
    -

    0x00000004

    - -
    -
    - -

    ◆ ADC_JSQR_JSQ1_3

    - -
    -
    - - - - -
    #define ADC_JSQR_JSQ1_3   (0x08UL << ADC_JSQR_JSQ1_Pos)
    -
    -

    0x00000008

    - -
    -
    - -

    ◆ ADC_JSQR_JSQ1_4

    - -
    -
    - - - - -
    #define ADC_JSQR_JSQ1_4   (0x10UL << ADC_JSQR_JSQ1_Pos)
    -
    -

    0x00000010

    - -
    -
    - -

    ◆ ADC_JSQR_JSQ2_Pos

    - -
    -
    - - - - -
    #define ADC_JSQR_JSQ2_Pos   (5U)
    -
    - -
    -
    - -

    ◆ ADC_JSQR_JSQ2_Msk

    - -
    -
    - - - - -
    #define ADC_JSQR_JSQ2_Msk   (0x1FUL << ADC_JSQR_JSQ2_Pos)
    -
    -

    0x000003E0

    - -
    -
    - -

    ◆ ADC_JSQR_JSQ2

    - -
    -
    - - - - -
    #define ADC_JSQR_JSQ2   ADC_JSQR_JSQ2_Msk
    -
    -

    JSQ2[4:0] bits (2nd conversion in injected sequence)

    - -
    -
    - -

    ◆ ADC_JSQR_JSQ2_0

    - -
    -
    - - - - -
    #define ADC_JSQR_JSQ2_0   (0x01UL << ADC_JSQR_JSQ2_Pos)
    -
    -

    0x00000020

    - -
    -
    - -

    ◆ ADC_JSQR_JSQ2_1

    - -
    -
    - - - - -
    #define ADC_JSQR_JSQ2_1   (0x02UL << ADC_JSQR_JSQ2_Pos)
    -
    -

    0x00000040

    - -
    -
    - -

    ◆ ADC_JSQR_JSQ2_2

    - -
    -
    - - - - -
    #define ADC_JSQR_JSQ2_2   (0x04UL << ADC_JSQR_JSQ2_Pos)
    -
    -

    0x00000080

    - -
    -
    - -

    ◆ ADC_JSQR_JSQ2_3

    - -
    -
    - - - - -
    #define ADC_JSQR_JSQ2_3   (0x08UL << ADC_JSQR_JSQ2_Pos)
    -
    -

    0x00000100

    - -
    -
    - -

    ◆ ADC_JSQR_JSQ2_4

    - -
    -
    - - - - -
    #define ADC_JSQR_JSQ2_4   (0x10UL << ADC_JSQR_JSQ2_Pos)
    -
    -

    0x00000200

    - -
    -
    - -

    ◆ ADC_JSQR_JSQ3_Pos

    - -
    -
    - - - - -
    #define ADC_JSQR_JSQ3_Pos   (10U)
    -
    - -
    -
    - -

    ◆ ADC_JSQR_JSQ3_Msk

    - -
    -
    - - - - -
    #define ADC_JSQR_JSQ3_Msk   (0x1FUL << ADC_JSQR_JSQ3_Pos)
    -
    -

    0x00007C00

    - -
    -
    - -

    ◆ ADC_JSQR_JSQ3

    - -
    -
    - - - - -
    #define ADC_JSQR_JSQ3   ADC_JSQR_JSQ3_Msk
    -
    -

    JSQ3[4:0] bits (3rd conversion in injected sequence)

    - -
    -
    - -

    ◆ ADC_JSQR_JSQ3_0

    - -
    -
    - - - - -
    #define ADC_JSQR_JSQ3_0   (0x01UL << ADC_JSQR_JSQ3_Pos)
    -
    -

    0x00000400

    - -
    -
    - -

    ◆ ADC_JSQR_JSQ3_1

    - -
    -
    - - - - -
    #define ADC_JSQR_JSQ3_1   (0x02UL << ADC_JSQR_JSQ3_Pos)
    -
    -

    0x00000800

    - -
    -
    - -

    ◆ ADC_JSQR_JSQ3_2

    - -
    -
    - - - - -
    #define ADC_JSQR_JSQ3_2   (0x04UL << ADC_JSQR_JSQ3_Pos)
    -
    -

    0x00001000

    - -
    -
    - -

    ◆ ADC_JSQR_JSQ3_3

    - -
    -
    - - - - -
    #define ADC_JSQR_JSQ3_3   (0x08UL << ADC_JSQR_JSQ3_Pos)
    -
    -

    0x00002000

    - -
    -
    - -

    ◆ ADC_JSQR_JSQ3_4

    - -
    -
    - - - - -
    #define ADC_JSQR_JSQ3_4   (0x10UL << ADC_JSQR_JSQ3_Pos)
    -
    -

    0x00004000

    - -
    -
    - -

    ◆ ADC_JSQR_JSQ4_Pos

    - -
    -
    - - - - -
    #define ADC_JSQR_JSQ4_Pos   (15U)
    -
    - -
    -
    - -

    ◆ ADC_JSQR_JSQ4_Msk

    - -
    -
    - - - - -
    #define ADC_JSQR_JSQ4_Msk   (0x1FUL << ADC_JSQR_JSQ4_Pos)
    -
    -

    0x000F8000

    - -
    -
    - -

    ◆ ADC_JSQR_JSQ4

    - -
    -
    - - - - -
    #define ADC_JSQR_JSQ4   ADC_JSQR_JSQ4_Msk
    -
    -

    JSQ4[4:0] bits (4th conversion in injected sequence)

    - -
    -
    - -

    ◆ ADC_JSQR_JSQ4_0

    - -
    -
    - - - - -
    #define ADC_JSQR_JSQ4_0   (0x01UL << ADC_JSQR_JSQ4_Pos)
    -
    -

    0x00008000

    - -
    -
    - -

    ◆ ADC_JSQR_JSQ4_1

    - -
    -
    - - - - -
    #define ADC_JSQR_JSQ4_1   (0x02UL << ADC_JSQR_JSQ4_Pos)
    -
    -

    0x00010000

    - -
    -
    - -

    ◆ ADC_JSQR_JSQ4_2

    - -
    -
    - - - - -
    #define ADC_JSQR_JSQ4_2   (0x04UL << ADC_JSQR_JSQ4_Pos)
    -
    -

    0x00020000

    - -
    -
    - -

    ◆ ADC_JSQR_JSQ4_3

    - -
    -
    - - - - -
    #define ADC_JSQR_JSQ4_3   (0x08UL << ADC_JSQR_JSQ4_Pos)
    -
    -

    0x00040000

    - -
    -
    - -

    ◆ ADC_JSQR_JSQ4_4

    - -
    -
    - - - - -
    #define ADC_JSQR_JSQ4_4   (0x10UL << ADC_JSQR_JSQ4_Pos)
    -
    -

    0x00080000

    - -
    -
    - -

    ◆ ADC_JSQR_JL_Pos

    - -
    -
    - - - - -
    #define ADC_JSQR_JL_Pos   (20U)
    -
    - -
    -
    - -

    ◆ ADC_JSQR_JL_Msk

    - -
    -
    - - - - -
    #define ADC_JSQR_JL_Msk   (0x3UL << ADC_JSQR_JL_Pos)
    -
    -

    0x00300000

    - -
    -
    - -

    ◆ ADC_JSQR_JL

    - -
    -
    - - - - -
    #define ADC_JSQR_JL   ADC_JSQR_JL_Msk
    -
    -

    JL[1:0] bits (Injected Sequence length)

    - -
    -
    - -

    ◆ ADC_JSQR_JL_0

    - -
    -
    - - - - -
    #define ADC_JSQR_JL_0   (0x1UL << ADC_JSQR_JL_Pos)
    -
    -

    0x00100000

    - -
    -
    - -

    ◆ ADC_JSQR_JL_1

    - -
    -
    - - - - -
    #define ADC_JSQR_JL_1   (0x2UL << ADC_JSQR_JL_Pos)
    -
    -

    0x00200000

    - -
    -
    - -

    ◆ ADC_JDR1_JDATA_Pos

    - -
    -
    - - - - -
    #define ADC_JDR1_JDATA_Pos   (0U)
    -
    - -
    -
    - -

    ◆ ADC_JDR1_JDATA_Msk

    - -
    -
    - - - - -
    #define ADC_JDR1_JDATA_Msk   (0xFFFFUL << ADC_JDR1_JDATA_Pos)
    -
    -

    0x0000FFFF

    - -
    -
    - -

    ◆ ADC_JDR1_JDATA

    - -
    -
    - - - - -
    #define ADC_JDR1_JDATA   ADC_JDR1_JDATA_Msk
    -
    -

    Injected data

    - -
    -
    - -

    ◆ ADC_JDR2_JDATA_Pos

    - -
    -
    - - - - -
    #define ADC_JDR2_JDATA_Pos   (0U)
    -
    - -
    -
    - -

    ◆ ADC_JDR2_JDATA_Msk

    - -
    -
    - - - - -
    #define ADC_JDR2_JDATA_Msk   (0xFFFFUL << ADC_JDR2_JDATA_Pos)
    -
    -

    0x0000FFFF

    - -
    -
    - -

    ◆ ADC_JDR2_JDATA

    - -
    -
    - - - - -
    #define ADC_JDR2_JDATA   ADC_JDR2_JDATA_Msk
    -
    -

    Injected data

    - -
    -
    - -

    ◆ ADC_JDR3_JDATA_Pos

    - -
    -
    - - - - -
    #define ADC_JDR3_JDATA_Pos   (0U)
    -
    - -
    -
    - -

    ◆ ADC_JDR3_JDATA_Msk

    - -
    -
    - - - - -
    #define ADC_JDR3_JDATA_Msk   (0xFFFFUL << ADC_JDR3_JDATA_Pos)
    -
    -

    0x0000FFFF

    - -
    -
    - -

    ◆ ADC_JDR3_JDATA

    - -
    -
    - - - - -
    #define ADC_JDR3_JDATA   ADC_JDR3_JDATA_Msk
    -
    -

    Injected data

    - -
    -
    - -

    ◆ ADC_JDR4_JDATA_Pos

    - -
    -
    - - - - -
    #define ADC_JDR4_JDATA_Pos   (0U)
    -
    - -
    -
    - -

    ◆ ADC_JDR4_JDATA_Msk

    - -
    -
    - - - - -
    #define ADC_JDR4_JDATA_Msk   (0xFFFFUL << ADC_JDR4_JDATA_Pos)
    -
    -

    0x0000FFFF

    - -
    -
    - -

    ◆ ADC_JDR4_JDATA

    - -
    -
    - - - - -
    #define ADC_JDR4_JDATA   ADC_JDR4_JDATA_Msk
    -
    -

    Injected data

    - -
    -
    - -

    ◆ ADC_DR_DATA_Pos

    - -
    -
    - - - - -
    #define ADC_DR_DATA_Pos   (0U)
    -
    - -
    -
    - -

    ◆ ADC_DR_DATA_Msk

    - -
    -
    - - - - -
    #define ADC_DR_DATA_Msk   (0xFFFFUL << ADC_DR_DATA_Pos)
    -
    -

    0x0000FFFF

    - -
    -
    - -

    ◆ ADC_DR_DATA

    - -
    -
    - - - - -
    #define ADC_DR_DATA   ADC_DR_DATA_Msk
    -
    -

    Regular data

    - -
    -
    - -

    ◆ ADC_DR_ADC2DATA_Pos

    - -
    -
    - - - - -
    #define ADC_DR_ADC2DATA_Pos   (16U)
    -
    - -
    -
    - -

    ◆ ADC_DR_ADC2DATA_Msk

    - -
    -
    - - - - -
    #define ADC_DR_ADC2DATA_Msk   (0xFFFFUL << ADC_DR_ADC2DATA_Pos)
    -
    -

    0xFFFF0000

    - -
    -
    - -

    ◆ ADC_DR_ADC2DATA

    - -
    -
    - - - - -
    #define ADC_DR_ADC2DATA   ADC_DR_ADC2DATA_Msk
    -
    -

    ADC2 data

    - -
    -
    - -

    ◆ ADC_CSR_AWD1_Pos

    - -
    -
    - - - - -
    #define ADC_CSR_AWD1_Pos   (0U)
    -
    - -
    -
    - -

    ◆ ADC_CSR_AWD1_Msk

    - -
    -
    - - - - -
    #define ADC_CSR_AWD1_Msk   (0x1UL << ADC_CSR_AWD1_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ ADC_CSR_AWD1

    - -
    -
    - - - - -
    #define ADC_CSR_AWD1   ADC_CSR_AWD1_Msk
    -
    -

    ADC1 Analog watchdog flag

    - -
    -
    - -

    ◆ ADC_CSR_EOC1_Pos

    - -
    -
    - - - - -
    #define ADC_CSR_EOC1_Pos   (1U)
    -
    - -
    -
    - -

    ◆ ADC_CSR_EOC1_Msk

    - -
    -
    - - - - -
    #define ADC_CSR_EOC1_Msk   (0x1UL << ADC_CSR_EOC1_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ ADC_CSR_EOC1

    - -
    -
    - - - - -
    #define ADC_CSR_EOC1   ADC_CSR_EOC1_Msk
    -
    -

    ADC1 End of conversion

    - -
    -
    - -

    ◆ ADC_CSR_JEOC1_Pos

    - -
    -
    - - - - -
    #define ADC_CSR_JEOC1_Pos   (2U)
    -
    - -
    -
    - -

    ◆ ADC_CSR_JEOC1_Msk

    - -
    -
    - - - - -
    #define ADC_CSR_JEOC1_Msk   (0x1UL << ADC_CSR_JEOC1_Pos)
    -
    -

    0x00000004

    - -
    -
    - -

    ◆ ADC_CSR_JEOC1

    - -
    -
    - - - - -
    #define ADC_CSR_JEOC1   ADC_CSR_JEOC1_Msk
    -
    -

    ADC1 Injected channel end of conversion

    - -
    -
    - -

    ◆ ADC_CSR_JSTRT1_Pos

    - -
    -
    - - - - -
    #define ADC_CSR_JSTRT1_Pos   (3U)
    -
    - -
    -
    - -

    ◆ ADC_CSR_JSTRT1_Msk

    - -
    -
    - - - - -
    #define ADC_CSR_JSTRT1_Msk   (0x1UL << ADC_CSR_JSTRT1_Pos)
    -
    -

    0x00000008

    - -
    -
    - -

    ◆ ADC_CSR_JSTRT1

    - -
    -
    - - - - -
    #define ADC_CSR_JSTRT1   ADC_CSR_JSTRT1_Msk
    -
    -

    ADC1 Injected channel Start flag

    - -
    -
    - -

    ◆ ADC_CSR_STRT1_Pos

    - -
    -
    - - - - -
    #define ADC_CSR_STRT1_Pos   (4U)
    -
    - -
    -
    - -

    ◆ ADC_CSR_STRT1_Msk

    - -
    -
    - - - - -
    #define ADC_CSR_STRT1_Msk   (0x1UL << ADC_CSR_STRT1_Pos)
    -
    -

    0x00000010

    - -
    -
    - -

    ◆ ADC_CSR_STRT1

    - -
    -
    - - - - -
    #define ADC_CSR_STRT1   ADC_CSR_STRT1_Msk
    -
    -

    ADC1 Regular channel Start flag

    - -
    -
    - -

    ◆ ADC_CSR_OVR1_Pos

    - -
    -
    - - - - -
    #define ADC_CSR_OVR1_Pos   (5U)
    -
    - -
    -
    - -

    ◆ ADC_CSR_OVR1_Msk

    - -
    -
    - - - - -
    #define ADC_CSR_OVR1_Msk   (0x1UL << ADC_CSR_OVR1_Pos)
    -
    -

    0x00000020

    - -
    -
    - -

    ◆ ADC_CSR_OVR1

    - -
    -
    - - - - -
    #define ADC_CSR_OVR1   ADC_CSR_OVR1_Msk
    -
    -

    ADC1 DMA overrun flag

    - -
    -
    - -

    ◆ ADC_CSR_AWD2_Pos

    - -
    -
    - - - - -
    #define ADC_CSR_AWD2_Pos   (8U)
    -
    - -
    -
    - -

    ◆ ADC_CSR_AWD2_Msk

    - -
    -
    - - - - -
    #define ADC_CSR_AWD2_Msk   (0x1UL << ADC_CSR_AWD2_Pos)
    -
    -

    0x00000100

    - -
    -
    - -

    ◆ ADC_CSR_AWD2

    - -
    -
    - - - - -
    #define ADC_CSR_AWD2   ADC_CSR_AWD2_Msk
    -
    -

    ADC2 Analog watchdog flag

    - -
    -
    - -

    ◆ ADC_CSR_EOC2_Pos

    - -
    -
    - - - - -
    #define ADC_CSR_EOC2_Pos   (9U)
    -
    - -
    -
    - -

    ◆ ADC_CSR_EOC2_Msk

    - -
    -
    - - - - -
    #define ADC_CSR_EOC2_Msk   (0x1UL << ADC_CSR_EOC2_Pos)
    -
    -

    0x00000200

    - -
    -
    - -

    ◆ ADC_CSR_EOC2

    - -
    -
    - - - - -
    #define ADC_CSR_EOC2   ADC_CSR_EOC2_Msk
    -
    -

    ADC2 End of conversion

    - -
    -
    - -

    ◆ ADC_CSR_JEOC2_Pos

    - -
    -
    - - - - -
    #define ADC_CSR_JEOC2_Pos   (10U)
    -
    - -
    -
    - -

    ◆ ADC_CSR_JEOC2_Msk

    - -
    -
    - - - - -
    #define ADC_CSR_JEOC2_Msk   (0x1UL << ADC_CSR_JEOC2_Pos)
    -
    -

    0x00000400

    - -
    -
    - -

    ◆ ADC_CSR_JEOC2

    - -
    -
    - - - - -
    #define ADC_CSR_JEOC2   ADC_CSR_JEOC2_Msk
    -
    -

    ADC2 Injected channel end of conversion

    - -
    -
    - -

    ◆ ADC_CSR_JSTRT2_Pos

    - -
    -
    - - - - -
    #define ADC_CSR_JSTRT2_Pos   (11U)
    -
    - -
    -
    - -

    ◆ ADC_CSR_JSTRT2_Msk

    - -
    -
    - - - - -
    #define ADC_CSR_JSTRT2_Msk   (0x1UL << ADC_CSR_JSTRT2_Pos)
    -
    -

    0x00000800

    - -
    -
    - -

    ◆ ADC_CSR_JSTRT2

    - -
    -
    - - - - -
    #define ADC_CSR_JSTRT2   ADC_CSR_JSTRT2_Msk
    -
    -

    ADC2 Injected channel Start flag

    - -
    -
    - -

    ◆ ADC_CSR_STRT2_Pos

    - -
    -
    - - - - -
    #define ADC_CSR_STRT2_Pos   (12U)
    -
    - -
    -
    - -

    ◆ ADC_CSR_STRT2_Msk

    - -
    -
    - - - - -
    #define ADC_CSR_STRT2_Msk   (0x1UL << ADC_CSR_STRT2_Pos)
    -
    -

    0x00001000

    - -
    -
    - -

    ◆ ADC_CSR_STRT2

    - -
    -
    - - - - -
    #define ADC_CSR_STRT2   ADC_CSR_STRT2_Msk
    -
    -

    ADC2 Regular channel Start flag

    - -
    -
    - -

    ◆ ADC_CSR_OVR2_Pos

    - -
    -
    - - - - -
    #define ADC_CSR_OVR2_Pos   (13U)
    -
    - -
    -
    - -

    ◆ ADC_CSR_OVR2_Msk

    - -
    -
    - - - - -
    #define ADC_CSR_OVR2_Msk   (0x1UL << ADC_CSR_OVR2_Pos)
    -
    -

    0x00002000

    - -
    -
    - -

    ◆ ADC_CSR_OVR2

    - -
    -
    - - - - -
    #define ADC_CSR_OVR2   ADC_CSR_OVR2_Msk
    -
    -

    ADC2 DMA overrun flag

    - -
    -
    - -

    ◆ ADC_CSR_AWD3_Pos

    - -
    -
    - - - - -
    #define ADC_CSR_AWD3_Pos   (16U)
    -
    - -
    -
    - -

    ◆ ADC_CSR_AWD3_Msk

    - -
    -
    - - - - -
    #define ADC_CSR_AWD3_Msk   (0x1UL << ADC_CSR_AWD3_Pos)
    -
    -

    0x00010000

    - -
    -
    - -

    ◆ ADC_CSR_AWD3

    - -
    -
    - - - - -
    #define ADC_CSR_AWD3   ADC_CSR_AWD3_Msk
    -
    -

    ADC3 Analog watchdog flag

    - -
    -
    - -

    ◆ ADC_CSR_EOC3_Pos

    - -
    -
    - - - - -
    #define ADC_CSR_EOC3_Pos   (17U)
    -
    - -
    -
    - -

    ◆ ADC_CSR_EOC3_Msk

    - -
    -
    - - - - -
    #define ADC_CSR_EOC3_Msk   (0x1UL << ADC_CSR_EOC3_Pos)
    -
    -

    0x00020000

    - -
    -
    - -

    ◆ ADC_CSR_EOC3

    - -
    -
    - - - - -
    #define ADC_CSR_EOC3   ADC_CSR_EOC3_Msk
    -
    -

    ADC3 End of conversion

    - -
    -
    - -

    ◆ ADC_CSR_JEOC3_Pos

    - -
    -
    - - - - -
    #define ADC_CSR_JEOC3_Pos   (18U)
    -
    - -
    -
    - -

    ◆ ADC_CSR_JEOC3_Msk

    - -
    -
    - - - - -
    #define ADC_CSR_JEOC3_Msk   (0x1UL << ADC_CSR_JEOC3_Pos)
    -
    -

    0x00040000

    - -
    -
    - -

    ◆ ADC_CSR_JEOC3

    - -
    -
    - - - - -
    #define ADC_CSR_JEOC3   ADC_CSR_JEOC3_Msk
    -
    -

    ADC3 Injected channel end of conversion

    - -
    -
    - -

    ◆ ADC_CSR_JSTRT3_Pos

    - -
    -
    - - - - -
    #define ADC_CSR_JSTRT3_Pos   (19U)
    -
    - -
    -
    - -

    ◆ ADC_CSR_JSTRT3_Msk

    - -
    -
    - - - - -
    #define ADC_CSR_JSTRT3_Msk   (0x1UL << ADC_CSR_JSTRT3_Pos)
    -
    -

    0x00080000

    - -
    -
    - -

    ◆ ADC_CSR_JSTRT3

    - -
    -
    - - - - -
    #define ADC_CSR_JSTRT3   ADC_CSR_JSTRT3_Msk
    -
    -

    ADC3 Injected channel Start flag

    - -
    -
    - -

    ◆ ADC_CSR_STRT3_Pos

    - -
    -
    - - - - -
    #define ADC_CSR_STRT3_Pos   (20U)
    -
    - -
    -
    - -

    ◆ ADC_CSR_STRT3_Msk

    - -
    -
    - - - - -
    #define ADC_CSR_STRT3_Msk   (0x1UL << ADC_CSR_STRT3_Pos)
    -
    -

    0x00100000

    - -
    -
    - -

    ◆ ADC_CSR_STRT3

    - -
    -
    - - - - -
    #define ADC_CSR_STRT3   ADC_CSR_STRT3_Msk
    -
    -

    ADC3 Regular channel Start flag

    - -
    -
    - -

    ◆ ADC_CSR_OVR3_Pos

    - -
    -
    - - - - -
    #define ADC_CSR_OVR3_Pos   (21U)
    -
    - -
    -
    - -

    ◆ ADC_CSR_OVR3_Msk

    - -
    -
    - - - - -
    #define ADC_CSR_OVR3_Msk   (0x1UL << ADC_CSR_OVR3_Pos)
    -
    -

    0x00200000

    - -
    -
    - -

    ◆ ADC_CSR_OVR3

    - -
    -
    - - - - -
    #define ADC_CSR_OVR3   ADC_CSR_OVR3_Msk
    -
    -

    ADC3 DMA overrun flag

    - -
    -
    - -

    ◆ ADC_CSR_DOVR1

    - -
    -
    - - - - -
    #define ADC_CSR_DOVR1   ADC_CSR_OVR1
    -
    - -
    -
    - -

    ◆ ADC_CSR_DOVR2

    - -
    -
    - - - - -
    #define ADC_CSR_DOVR2   ADC_CSR_OVR2
    -
    - -
    -
    - -

    ◆ ADC_CSR_DOVR3

    - -
    -
    - - - - -
    #define ADC_CSR_DOVR3   ADC_CSR_OVR3
    -
    - -
    -
    - -

    ◆ ADC_CCR_MULTI_Pos

    - -
    -
    - - - - -
    #define ADC_CCR_MULTI_Pos   (0U)
    -
    - -
    -
    - -

    ◆ ADC_CCR_MULTI_Msk

    - -
    -
    - - - - -
    #define ADC_CCR_MULTI_Msk   (0x1FUL << ADC_CCR_MULTI_Pos)
    -
    -

    0x0000001F

    - -
    -
    - -

    ◆ ADC_CCR_MULTI

    - -
    -
    - - - - -
    #define ADC_CCR_MULTI   ADC_CCR_MULTI_Msk
    -
    -

    MULTI[4:0] bits (Multi-ADC mode selection)

    - -
    -
    - -

    ◆ ADC_CCR_MULTI_0

    - -
    -
    - - - - -
    #define ADC_CCR_MULTI_0   (0x01UL << ADC_CCR_MULTI_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ ADC_CCR_MULTI_1

    - -
    -
    - - - - -
    #define ADC_CCR_MULTI_1   (0x02UL << ADC_CCR_MULTI_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ ADC_CCR_MULTI_2

    - -
    -
    - - - - -
    #define ADC_CCR_MULTI_2   (0x04UL << ADC_CCR_MULTI_Pos)
    -
    -

    0x00000004

    - -
    -
    - -

    ◆ ADC_CCR_MULTI_3

    - -
    -
    - - - - -
    #define ADC_CCR_MULTI_3   (0x08UL << ADC_CCR_MULTI_Pos)
    -
    -

    0x00000008

    - -
    -
    - -

    ◆ ADC_CCR_MULTI_4

    - -
    -
    - - - - -
    #define ADC_CCR_MULTI_4   (0x10UL << ADC_CCR_MULTI_Pos)
    -
    -

    0x00000010

    - -
    -
    - -

    ◆ ADC_CCR_DELAY_Pos

    - -
    -
    - - - - -
    #define ADC_CCR_DELAY_Pos   (8U)
    -
    - -
    -
    - -

    ◆ ADC_CCR_DELAY_Msk

    - -
    -
    - - - - -
    #define ADC_CCR_DELAY_Msk   (0xFUL << ADC_CCR_DELAY_Pos)
    -
    -

    0x00000F00

    - -
    -
    - -

    ◆ ADC_CCR_DELAY

    - -
    -
    - - - - -
    #define ADC_CCR_DELAY   ADC_CCR_DELAY_Msk
    -
    -

    DELAY[3:0] bits (Delay between 2 sampling phases)

    - -
    -
    - -

    ◆ ADC_CCR_DELAY_0

    - -
    -
    - - - - -
    #define ADC_CCR_DELAY_0   (0x1UL << ADC_CCR_DELAY_Pos)
    -
    -

    0x00000100

    - -
    -
    - -

    ◆ ADC_CCR_DELAY_1

    - -
    -
    - - - - -
    #define ADC_CCR_DELAY_1   (0x2UL << ADC_CCR_DELAY_Pos)
    -
    -

    0x00000200

    - -
    -
    - -

    ◆ ADC_CCR_DELAY_2

    - -
    -
    - - - - -
    #define ADC_CCR_DELAY_2   (0x4UL << ADC_CCR_DELAY_Pos)
    -
    -

    0x00000400

    - -
    -
    - -

    ◆ ADC_CCR_DELAY_3

    - -
    -
    - - - - -
    #define ADC_CCR_DELAY_3   (0x8UL << ADC_CCR_DELAY_Pos)
    -
    -

    0x00000800

    - -
    -
    - -

    ◆ ADC_CCR_DDS_Pos

    - -
    -
    - - - - -
    #define ADC_CCR_DDS_Pos   (13U)
    -
    - -
    -
    - -

    ◆ ADC_CCR_DDS_Msk

    - -
    -
    - - - - -
    #define ADC_CCR_DDS_Msk   (0x1UL << ADC_CCR_DDS_Pos)
    -
    -

    0x00002000

    - -
    -
    - -

    ◆ ADC_CCR_DDS

    - -
    -
    - - - - -
    #define ADC_CCR_DDS   ADC_CCR_DDS_Msk
    -
    -

    DMA disable selection (Multi-ADC mode)

    - -
    -
    - -

    ◆ ADC_CCR_DMA_Pos

    - -
    -
    - - - - -
    #define ADC_CCR_DMA_Pos   (14U)
    -
    - -
    -
    - -

    ◆ ADC_CCR_DMA_Msk

    - -
    -
    - - - - -
    #define ADC_CCR_DMA_Msk   (0x3UL << ADC_CCR_DMA_Pos)
    -
    -

    0x0000C000

    - -
    -
    - -

    ◆ ADC_CCR_DMA

    - -
    -
    - - - - -
    #define ADC_CCR_DMA   ADC_CCR_DMA_Msk
    -
    -

    DMA[1:0] bits (Direct Memory Access mode for multimode)

    - -
    -
    - -

    ◆ ADC_CCR_DMA_0

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    -
    - - - - -
    #define ADC_CCR_DMA_0   (0x1UL << ADC_CCR_DMA_Pos)
    -
    -

    0x00004000

    - -
    -
    - -

    ◆ ADC_CCR_DMA_1

    - -
    -
    - - - - -
    #define ADC_CCR_DMA_1   (0x2UL << ADC_CCR_DMA_Pos)
    -
    -

    0x00008000

    - -
    -
    - -

    ◆ ADC_CCR_ADCPRE_Pos

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    -
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    #define ADC_CCR_ADCPRE_Pos   (16U)
    -
    - -
    -
    - -

    ◆ ADC_CCR_ADCPRE_Msk

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    -
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    #define ADC_CCR_ADCPRE_Msk   (0x3UL << ADC_CCR_ADCPRE_Pos)
    -
    -

    0x00030000

    - -
    -
    - -

    ◆ ADC_CCR_ADCPRE

    - -
    -
    - - - - -
    #define ADC_CCR_ADCPRE   ADC_CCR_ADCPRE_Msk
    -
    -

    ADCPRE[1:0] bits (ADC prescaler)

    - -
    -
    - -

    ◆ ADC_CCR_ADCPRE_0

    - -
    -
    - - - - -
    #define ADC_CCR_ADCPRE_0   (0x1UL << ADC_CCR_ADCPRE_Pos)
    -
    -

    0x00010000

    - -
    -
    - -

    ◆ ADC_CCR_ADCPRE_1

    - -
    -
    - - - - -
    #define ADC_CCR_ADCPRE_1   (0x2UL << ADC_CCR_ADCPRE_Pos)
    -
    -

    0x00020000

    - -
    -
    - -

    ◆ ADC_CCR_VBATE_Pos

    - -
    -
    - - - - -
    #define ADC_CCR_VBATE_Pos   (22U)
    -
    - -
    -
    - -

    ◆ ADC_CCR_VBATE_Msk

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    -
    - - - - -
    #define ADC_CCR_VBATE_Msk   (0x1UL << ADC_CCR_VBATE_Pos)
    -
    -

    0x00400000

    - -
    -
    - -

    ◆ ADC_CCR_VBATE

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    -
    - - - - -
    #define ADC_CCR_VBATE   ADC_CCR_VBATE_Msk
    -
    -

    VBAT Enable

    - -
    -
    - -

    ◆ ADC_CCR_TSVREFE_Pos

    - -
    -
    - - - - -
    #define ADC_CCR_TSVREFE_Pos   (23U)
    -
    - -
    -
    - -

    ◆ ADC_CCR_TSVREFE_Msk

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    -
    - - - - -
    #define ADC_CCR_TSVREFE_Msk   (0x1UL << ADC_CCR_TSVREFE_Pos)
    -
    -

    0x00800000

    - -
    -
    - -

    ◆ ADC_CCR_TSVREFE

    - -
    -
    - - - - -
    #define ADC_CCR_TSVREFE   ADC_CCR_TSVREFE_Msk
    -
    -

    Temperature Sensor and VREFINT Enable

    - -
    -
    - -

    ◆ ADC_CDR_DATA1_Pos

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    -
    - - - - -
    #define ADC_CDR_DATA1_Pos   (0U)
    -
    - -
    -
    - -

    ◆ ADC_CDR_DATA1_Msk

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    -
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    #define ADC_CDR_DATA1_Msk   (0xFFFFUL << ADC_CDR_DATA1_Pos)
    -
    -

    0x0000FFFF

    - -
    -
    - -

    ◆ ADC_CDR_DATA1

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    -
    - - - - -
    #define ADC_CDR_DATA1   ADC_CDR_DATA1_Msk
    -
    -

    1st data of a pair of regular conversions

    - -
    -
    - -

    ◆ ADC_CDR_DATA2_Pos

    - -
    -
    - - - - -
    #define ADC_CDR_DATA2_Pos   (16U)
    -
    - -
    -
    - -

    ◆ ADC_CDR_DATA2_Msk

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    -
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    #define ADC_CDR_DATA2_Msk   (0xFFFFUL << ADC_CDR_DATA2_Pos)
    -
    -

    0xFFFF0000

    - -
    -
    - -

    ◆ ADC_CDR_DATA2

    - -
    -
    - - - - -
    #define ADC_CDR_DATA2   ADC_CDR_DATA2_Msk
    -
    -

    2nd data of a pair of regular conversions

    - -
    -
    - -

    ◆ ADC_CDR_RDATA_MST

    - -
    -
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    #define ADC_CDR_RDATA_MST   ADC_CDR_DATA1
    -
    - -
    -
    - -

    ◆ ADC_CDR_RDATA_SLV

    - -
    -
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    #define ADC_CDR_RDATA_SLV   ADC_CDR_DATA2
    -
    - -
    -
    - -

    ◆ CAN_MCR_INRQ_Pos

    - -
    -
    - - - - -
    #define CAN_MCR_INRQ_Pos   (0U)
    -
    -

    <CAN control and status registers

    - -
    -
    - -

    ◆ CAN_MCR_INRQ_Msk

    - -
    -
    - - - - -
    #define CAN_MCR_INRQ_Msk   (0x1UL << CAN_MCR_INRQ_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ CAN_MCR_INRQ

    - -
    -
    - - - - -
    #define CAN_MCR_INRQ   CAN_MCR_INRQ_Msk
    -
    -

    Initialization Request

    - -
    -
    - -

    ◆ CAN_MCR_SLEEP_Pos

    - -
    -
    - - - - -
    #define CAN_MCR_SLEEP_Pos   (1U)
    -
    - -
    -
    - -

    ◆ CAN_MCR_SLEEP_Msk

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    -
    - - - - -
    #define CAN_MCR_SLEEP_Msk   (0x1UL << CAN_MCR_SLEEP_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ CAN_MCR_SLEEP

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    -
    - - - - -
    #define CAN_MCR_SLEEP   CAN_MCR_SLEEP_Msk
    -
    -

    Sleep Mode Request

    - -
    -
    - -

    ◆ CAN_MCR_TXFP_Pos

    - -
    -
    - - - - -
    #define CAN_MCR_TXFP_Pos   (2U)
    -
    - -
    -
    - -

    ◆ CAN_MCR_TXFP_Msk

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    -
    - - - - -
    #define CAN_MCR_TXFP_Msk   (0x1UL << CAN_MCR_TXFP_Pos)
    -
    -

    0x00000004

    - -
    -
    - -

    ◆ CAN_MCR_TXFP

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    -
    - - - - -
    #define CAN_MCR_TXFP   CAN_MCR_TXFP_Msk
    -
    -

    Transmit FIFO Priority

    - -
    -
    - -

    ◆ CAN_MCR_RFLM_Pos

    - -
    -
    - - - - -
    #define CAN_MCR_RFLM_Pos   (3U)
    -
    - -
    -
    - -

    ◆ CAN_MCR_RFLM_Msk

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    -
    - - - - -
    #define CAN_MCR_RFLM_Msk   (0x1UL << CAN_MCR_RFLM_Pos)
    -
    -

    0x00000008

    - -
    -
    - -

    ◆ CAN_MCR_RFLM

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    -
    - - - - -
    #define CAN_MCR_RFLM   CAN_MCR_RFLM_Msk
    -
    -

    Receive FIFO Locked Mode

    - -
    -
    - -

    ◆ CAN_MCR_NART_Pos

    - -
    -
    - - - - -
    #define CAN_MCR_NART_Pos   (4U)
    -
    - -
    -
    - -

    ◆ CAN_MCR_NART_Msk

    - -
    -
    - - - - -
    #define CAN_MCR_NART_Msk   (0x1UL << CAN_MCR_NART_Pos)
    -
    -

    0x00000010

    - -
    -
    - -

    ◆ CAN_MCR_NART

    - -
    -
    - - - - -
    #define CAN_MCR_NART   CAN_MCR_NART_Msk
    -
    -

    No Automatic Retransmission

    - -
    -
    - -

    ◆ CAN_MCR_AWUM_Pos

    - -
    -
    - - - - -
    #define CAN_MCR_AWUM_Pos   (5U)
    -
    - -
    -
    - -

    ◆ CAN_MCR_AWUM_Msk

    - -
    -
    - - - - -
    #define CAN_MCR_AWUM_Msk   (0x1UL << CAN_MCR_AWUM_Pos)
    -
    -

    0x00000020

    - -
    -
    - -

    ◆ CAN_MCR_AWUM

    - -
    -
    - - - - -
    #define CAN_MCR_AWUM   CAN_MCR_AWUM_Msk
    -
    -

    Automatic Wakeup Mode

    - -
    -
    - -

    ◆ CAN_MCR_ABOM_Pos

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    -
    - - - - -
    #define CAN_MCR_ABOM_Pos   (6U)
    -
    - -
    -
    - -

    ◆ CAN_MCR_ABOM_Msk

    - -
    -
    - - - - -
    #define CAN_MCR_ABOM_Msk   (0x1UL << CAN_MCR_ABOM_Pos)
    -
    -

    0x00000040

    - -
    -
    - -

    ◆ CAN_MCR_ABOM

    - -
    -
    - - - - -
    #define CAN_MCR_ABOM   CAN_MCR_ABOM_Msk
    -
    -

    Automatic Bus-Off Management

    - -
    -
    - -

    ◆ CAN_MCR_TTCM_Pos

    - -
    -
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    #define CAN_MCR_TTCM_Pos   (7U)
    -
    - -
    -
    - -

    ◆ CAN_MCR_TTCM_Msk

    - -
    -
    - - - - -
    #define CAN_MCR_TTCM_Msk   (0x1UL << CAN_MCR_TTCM_Pos)
    -
    -

    0x00000080

    - -
    -
    - -

    ◆ CAN_MCR_TTCM

    - -
    -
    - - - - -
    #define CAN_MCR_TTCM   CAN_MCR_TTCM_Msk
    -
    -

    Time Triggered Communication Mode

    - -
    -
    - -

    ◆ CAN_MCR_RESET_Pos

    - -
    -
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    #define CAN_MCR_RESET_Pos   (15U)
    -
    - -
    -
    - -

    ◆ CAN_MCR_RESET_Msk

    - -
    -
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    #define CAN_MCR_RESET_Msk   (0x1UL << CAN_MCR_RESET_Pos)
    -
    -

    0x00008000

    - -
    -
    - -

    ◆ CAN_MCR_RESET

    - -
    -
    - - - - -
    #define CAN_MCR_RESET   CAN_MCR_RESET_Msk
    -
    -

    bxCAN software master reset

    - -
    -
    - -

    ◆ CAN_MCR_DBF_Pos

    - -
    -
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    #define CAN_MCR_DBF_Pos   (16U)
    -
    - -
    -
    - -

    ◆ CAN_MCR_DBF_Msk

    - -
    -
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    #define CAN_MCR_DBF_Msk   (0x1UL << CAN_MCR_DBF_Pos)
    -
    -

    0x00010000

    - -
    -
    - -

    ◆ CAN_MCR_DBF

    - -
    -
    - - - - -
    #define CAN_MCR_DBF   CAN_MCR_DBF_Msk
    -
    -

    bxCAN Debug freeze

    - -
    -
    - -

    ◆ CAN_MSR_INAK_Pos

    - -
    -
    - - - - -
    #define CAN_MSR_INAK_Pos   (0U)
    -
    - -
    -
    - -

    ◆ CAN_MSR_INAK_Msk

    - -
    -
    - - - - -
    #define CAN_MSR_INAK_Msk   (0x1UL << CAN_MSR_INAK_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ CAN_MSR_INAK

    - -
    -
    - - - - -
    #define CAN_MSR_INAK   CAN_MSR_INAK_Msk
    -
    -

    Initialization Acknowledge

    - -
    -
    - -

    ◆ CAN_MSR_SLAK_Pos

    - -
    -
    - - - - -
    #define CAN_MSR_SLAK_Pos   (1U)
    -
    - -
    -
    - -

    ◆ CAN_MSR_SLAK_Msk

    - -
    -
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    #define CAN_MSR_SLAK_Msk   (0x1UL << CAN_MSR_SLAK_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ CAN_MSR_SLAK

    - -
    -
    - - - - -
    #define CAN_MSR_SLAK   CAN_MSR_SLAK_Msk
    -
    -

    Sleep Acknowledge

    - -
    -
    - -

    ◆ CAN_MSR_ERRI_Pos

    - -
    -
    - - - - -
    #define CAN_MSR_ERRI_Pos   (2U)
    -
    - -
    -
    - -

    ◆ CAN_MSR_ERRI_Msk

    - -
    -
    - - - - -
    #define CAN_MSR_ERRI_Msk   (0x1UL << CAN_MSR_ERRI_Pos)
    -
    -

    0x00000004

    - -
    -
    - -

    ◆ CAN_MSR_ERRI

    - -
    -
    - - - - -
    #define CAN_MSR_ERRI   CAN_MSR_ERRI_Msk
    -
    -

    Error Interrupt

    - -
    -
    - -

    ◆ CAN_MSR_WKUI_Pos

    - -
    -
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    #define CAN_MSR_WKUI_Pos   (3U)
    -
    - -
    -
    - -

    ◆ CAN_MSR_WKUI_Msk

    - -
    -
    - - - - -
    #define CAN_MSR_WKUI_Msk   (0x1UL << CAN_MSR_WKUI_Pos)
    -
    -

    0x00000008

    - -
    -
    - -

    ◆ CAN_MSR_WKUI

    - -
    -
    - - - - -
    #define CAN_MSR_WKUI   CAN_MSR_WKUI_Msk
    -
    -

    Wakeup Interrupt

    - -
    -
    - -

    ◆ CAN_MSR_SLAKI_Pos

    - -
    -
    - - - - -
    #define CAN_MSR_SLAKI_Pos   (4U)
    -
    - -
    -
    - -

    ◆ CAN_MSR_SLAKI_Msk

    - -
    -
    - - - - -
    #define CAN_MSR_SLAKI_Msk   (0x1UL << CAN_MSR_SLAKI_Pos)
    -
    -

    0x00000010

    - -
    -
    - -

    ◆ CAN_MSR_SLAKI

    - -
    -
    - - - - -
    #define CAN_MSR_SLAKI   CAN_MSR_SLAKI_Msk
    -
    -

    Sleep Acknowledge Interrupt

    - -
    -
    - -

    ◆ CAN_MSR_TXM_Pos

    - -
    -
    - - - - -
    #define CAN_MSR_TXM_Pos   (8U)
    -
    - -
    -
    - -

    ◆ CAN_MSR_TXM_Msk

    - -
    -
    - - - - -
    #define CAN_MSR_TXM_Msk   (0x1UL << CAN_MSR_TXM_Pos)
    -
    -

    0x00000100

    - -
    -
    - -

    ◆ CAN_MSR_TXM

    - -
    -
    - - - - -
    #define CAN_MSR_TXM   CAN_MSR_TXM_Msk
    -
    -

    Transmit Mode

    - -
    -
    - -

    ◆ CAN_MSR_RXM_Pos

    - -
    -
    - - - - -
    #define CAN_MSR_RXM_Pos   (9U)
    -
    - -
    -
    - -

    ◆ CAN_MSR_RXM_Msk

    - -
    -
    - - - - -
    #define CAN_MSR_RXM_Msk   (0x1UL << CAN_MSR_RXM_Pos)
    -
    -

    0x00000200

    - -
    -
    - -

    ◆ CAN_MSR_RXM

    - -
    -
    - - - - -
    #define CAN_MSR_RXM   CAN_MSR_RXM_Msk
    -
    -

    Receive Mode

    - -
    -
    - -

    ◆ CAN_MSR_SAMP_Pos

    - -
    -
    - - - - -
    #define CAN_MSR_SAMP_Pos   (10U)
    -
    - -
    -
    - -

    ◆ CAN_MSR_SAMP_Msk

    - -
    -
    - - - - -
    #define CAN_MSR_SAMP_Msk   (0x1UL << CAN_MSR_SAMP_Pos)
    -
    -

    0x00000400

    - -
    -
    - -

    ◆ CAN_MSR_SAMP

    - -
    -
    - - - - -
    #define CAN_MSR_SAMP   CAN_MSR_SAMP_Msk
    -
    -

    Last Sample Point

    - -
    -
    - -

    ◆ CAN_MSR_RX_Pos

    - -
    -
    - - - - -
    #define CAN_MSR_RX_Pos   (11U)
    -
    - -
    -
    - -

    ◆ CAN_MSR_RX_Msk

    - -
    -
    - - - - -
    #define CAN_MSR_RX_Msk   (0x1UL << CAN_MSR_RX_Pos)
    -
    -

    0x00000800

    - -
    -
    - -

    ◆ CAN_MSR_RX

    - -
    -
    - - - - -
    #define CAN_MSR_RX   CAN_MSR_RX_Msk
    -
    -

    CAN Rx Signal

    - -
    -
    - -

    ◆ CAN_TSR_RQCP0_Pos

    - -
    -
    - - - - -
    #define CAN_TSR_RQCP0_Pos   (0U)
    -
    - -
    -
    - -

    ◆ CAN_TSR_RQCP0_Msk

    - -
    -
    - - - - -
    #define CAN_TSR_RQCP0_Msk   (0x1UL << CAN_TSR_RQCP0_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ CAN_TSR_RQCP0

    - -
    -
    - - - - -
    #define CAN_TSR_RQCP0   CAN_TSR_RQCP0_Msk
    -
    -

    Request Completed Mailbox0

    - -
    -
    - -

    ◆ CAN_TSR_TXOK0_Pos

    - -
    -
    - - - - -
    #define CAN_TSR_TXOK0_Pos   (1U)
    -
    - -
    -
    - -

    ◆ CAN_TSR_TXOK0_Msk

    - -
    -
    - - - - -
    #define CAN_TSR_TXOK0_Msk   (0x1UL << CAN_TSR_TXOK0_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ CAN_TSR_TXOK0

    - -
    -
    - - - - -
    #define CAN_TSR_TXOK0   CAN_TSR_TXOK0_Msk
    -
    -

    Transmission OK of Mailbox0

    - -
    -
    - -

    ◆ CAN_TSR_ALST0_Pos

    - -
    -
    - - - - -
    #define CAN_TSR_ALST0_Pos   (2U)
    -
    - -
    -
    - -

    ◆ CAN_TSR_ALST0_Msk

    - -
    -
    - - - - -
    #define CAN_TSR_ALST0_Msk   (0x1UL << CAN_TSR_ALST0_Pos)
    -
    -

    0x00000004

    - -
    -
    - -

    ◆ CAN_TSR_ALST0

    - -
    -
    - - - - -
    #define CAN_TSR_ALST0   CAN_TSR_ALST0_Msk
    -
    -

    Arbitration Lost for Mailbox0

    - -
    -
    - -

    ◆ CAN_TSR_TERR0_Pos

    - -
    -
    - - - - -
    #define CAN_TSR_TERR0_Pos   (3U)
    -
    - -
    -
    - -

    ◆ CAN_TSR_TERR0_Msk

    - -
    -
    - - - - -
    #define CAN_TSR_TERR0_Msk   (0x1UL << CAN_TSR_TERR0_Pos)
    -
    -

    0x00000008

    - -
    -
    - -

    ◆ CAN_TSR_TERR0

    - -
    -
    - - - - -
    #define CAN_TSR_TERR0   CAN_TSR_TERR0_Msk
    -
    -

    Transmission Error of Mailbox0

    - -
    -
    - -

    ◆ CAN_TSR_ABRQ0_Pos

    - -
    -
    - - - - -
    #define CAN_TSR_ABRQ0_Pos   (7U)
    -
    - -
    -
    - -

    ◆ CAN_TSR_ABRQ0_Msk

    - -
    -
    - - - - -
    #define CAN_TSR_ABRQ0_Msk   (0x1UL << CAN_TSR_ABRQ0_Pos)
    -
    -

    0x00000080

    - -
    -
    - -

    ◆ CAN_TSR_ABRQ0

    - -
    -
    - - - - -
    #define CAN_TSR_ABRQ0   CAN_TSR_ABRQ0_Msk
    -
    -

    Abort Request for Mailbox0

    - -
    -
    - -

    ◆ CAN_TSR_RQCP1_Pos

    - -
    -
    - - - - -
    #define CAN_TSR_RQCP1_Pos   (8U)
    -
    - -
    -
    - -

    ◆ CAN_TSR_RQCP1_Msk

    - -
    -
    - - - - -
    #define CAN_TSR_RQCP1_Msk   (0x1UL << CAN_TSR_RQCP1_Pos)
    -
    -

    0x00000100

    - -
    -
    - -

    ◆ CAN_TSR_RQCP1

    - -
    -
    - - - - -
    #define CAN_TSR_RQCP1   CAN_TSR_RQCP1_Msk
    -
    -

    Request Completed Mailbox1

    - -
    -
    - -

    ◆ CAN_TSR_TXOK1_Pos

    - -
    -
    - - - - -
    #define CAN_TSR_TXOK1_Pos   (9U)
    -
    - -
    -
    - -

    ◆ CAN_TSR_TXOK1_Msk

    - -
    -
    - - - - -
    #define CAN_TSR_TXOK1_Msk   (0x1UL << CAN_TSR_TXOK1_Pos)
    -
    -

    0x00000200

    - -
    -
    - -

    ◆ CAN_TSR_TXOK1

    - -
    -
    - - - - -
    #define CAN_TSR_TXOK1   CAN_TSR_TXOK1_Msk
    -
    -

    Transmission OK of Mailbox1

    - -
    -
    - -

    ◆ CAN_TSR_ALST1_Pos

    - -
    -
    - - - - -
    #define CAN_TSR_ALST1_Pos   (10U)
    -
    - -
    -
    - -

    ◆ CAN_TSR_ALST1_Msk

    - -
    -
    - - - - -
    #define CAN_TSR_ALST1_Msk   (0x1UL << CAN_TSR_ALST1_Pos)
    -
    -

    0x00000400

    - -
    -
    - -

    ◆ CAN_TSR_ALST1

    - -
    -
    - - - - -
    #define CAN_TSR_ALST1   CAN_TSR_ALST1_Msk
    -
    -

    Arbitration Lost for Mailbox1

    - -
    -
    - -

    ◆ CAN_TSR_TERR1_Pos

    - -
    -
    - - - - -
    #define CAN_TSR_TERR1_Pos   (11U)
    -
    - -
    -
    - -

    ◆ CAN_TSR_TERR1_Msk

    - -
    -
    - - - - -
    #define CAN_TSR_TERR1_Msk   (0x1UL << CAN_TSR_TERR1_Pos)
    -
    -

    0x00000800

    - -
    -
    - -

    ◆ CAN_TSR_TERR1

    - -
    -
    - - - - -
    #define CAN_TSR_TERR1   CAN_TSR_TERR1_Msk
    -
    -

    Transmission Error of Mailbox1

    - -
    -
    - -

    ◆ CAN_TSR_ABRQ1_Pos

    - -
    -
    - - - - -
    #define CAN_TSR_ABRQ1_Pos   (15U)
    -
    - -
    -
    - -

    ◆ CAN_TSR_ABRQ1_Msk

    - -
    -
    - - - - -
    #define CAN_TSR_ABRQ1_Msk   (0x1UL << CAN_TSR_ABRQ1_Pos)
    -
    -

    0x00008000

    - -
    -
    - -

    ◆ CAN_TSR_ABRQ1

    - -
    -
    - - - - -
    #define CAN_TSR_ABRQ1   CAN_TSR_ABRQ1_Msk
    -
    -

    Abort Request for Mailbox 1

    - -
    -
    - -

    ◆ CAN_TSR_RQCP2_Pos

    - -
    -
    - - - - -
    #define CAN_TSR_RQCP2_Pos   (16U)
    -
    - -
    -
    - -

    ◆ CAN_TSR_RQCP2_Msk

    - -
    -
    - - - - -
    #define CAN_TSR_RQCP2_Msk   (0x1UL << CAN_TSR_RQCP2_Pos)
    -
    -

    0x00010000

    - -
    -
    - -

    ◆ CAN_TSR_RQCP2

    - -
    -
    - - - - -
    #define CAN_TSR_RQCP2   CAN_TSR_RQCP2_Msk
    -
    -

    Request Completed Mailbox2

    - -
    -
    - -

    ◆ CAN_TSR_TXOK2_Pos

    - -
    -
    - - - - -
    #define CAN_TSR_TXOK2_Pos   (17U)
    -
    - -
    -
    - -

    ◆ CAN_TSR_TXOK2_Msk

    - -
    -
    - - - - -
    #define CAN_TSR_TXOK2_Msk   (0x1UL << CAN_TSR_TXOK2_Pos)
    -
    -

    0x00020000

    - -
    -
    - -

    ◆ CAN_TSR_TXOK2

    - -
    -
    - - - - -
    #define CAN_TSR_TXOK2   CAN_TSR_TXOK2_Msk
    -
    -

    Transmission OK of Mailbox 2

    - -
    -
    - -

    ◆ CAN_TSR_ALST2_Pos

    - -
    -
    - - - - -
    #define CAN_TSR_ALST2_Pos   (18U)
    -
    - -
    -
    - -

    ◆ CAN_TSR_ALST2_Msk

    - -
    -
    - - - - -
    #define CAN_TSR_ALST2_Msk   (0x1UL << CAN_TSR_ALST2_Pos)
    -
    -

    0x00040000

    - -
    -
    - -

    ◆ CAN_TSR_ALST2

    - -
    -
    - - - - -
    #define CAN_TSR_ALST2   CAN_TSR_ALST2_Msk
    -
    -

    Arbitration Lost for mailbox 2

    - -
    -
    - -

    ◆ CAN_TSR_TERR2_Pos

    - -
    -
    - - - - -
    #define CAN_TSR_TERR2_Pos   (19U)
    -
    - -
    -
    - -

    ◆ CAN_TSR_TERR2_Msk

    - -
    -
    - - - - -
    #define CAN_TSR_TERR2_Msk   (0x1UL << CAN_TSR_TERR2_Pos)
    -
    -

    0x00080000

    - -
    -
    - -

    ◆ CAN_TSR_TERR2

    - -
    -
    - - - - -
    #define CAN_TSR_TERR2   CAN_TSR_TERR2_Msk
    -
    -

    Transmission Error of Mailbox 2

    - -
    -
    - -

    ◆ CAN_TSR_ABRQ2_Pos

    - -
    -
    - - - - -
    #define CAN_TSR_ABRQ2_Pos   (23U)
    -
    - -
    -
    - -

    ◆ CAN_TSR_ABRQ2_Msk

    - -
    -
    - - - - -
    #define CAN_TSR_ABRQ2_Msk   (0x1UL << CAN_TSR_ABRQ2_Pos)
    -
    -

    0x00800000

    - -
    -
    - -

    ◆ CAN_TSR_ABRQ2

    - -
    -
    - - - - -
    #define CAN_TSR_ABRQ2   CAN_TSR_ABRQ2_Msk
    -
    -

    Abort Request for Mailbox 2

    - -
    -
    - -

    ◆ CAN_TSR_CODE_Pos

    - -
    -
    - - - - -
    #define CAN_TSR_CODE_Pos   (24U)
    -
    - -
    -
    - -

    ◆ CAN_TSR_CODE_Msk

    - -
    -
    - - - - -
    #define CAN_TSR_CODE_Msk   (0x3UL << CAN_TSR_CODE_Pos)
    -
    -

    0x03000000

    - -
    -
    - -

    ◆ CAN_TSR_CODE

    - -
    -
    - - - - -
    #define CAN_TSR_CODE   CAN_TSR_CODE_Msk
    -
    -

    Mailbox Code

    - -
    -
    - -

    ◆ CAN_TSR_TME_Pos

    - -
    -
    - - - - -
    #define CAN_TSR_TME_Pos   (26U)
    -
    - -
    -
    - -

    ◆ CAN_TSR_TME_Msk

    - -
    -
    - - - - -
    #define CAN_TSR_TME_Msk   (0x7UL << CAN_TSR_TME_Pos)
    -
    -

    0x1C000000

    - -
    -
    - -

    ◆ CAN_TSR_TME

    - -
    -
    - - - - -
    #define CAN_TSR_TME   CAN_TSR_TME_Msk
    -
    -

    TME[2:0] bits

    - -
    -
    - -

    ◆ CAN_TSR_TME0_Pos

    - -
    -
    - - - - -
    #define CAN_TSR_TME0_Pos   (26U)
    -
    - -
    -
    - -

    ◆ CAN_TSR_TME0_Msk

    - -
    -
    - - - - -
    #define CAN_TSR_TME0_Msk   (0x1UL << CAN_TSR_TME0_Pos)
    -
    -

    0x04000000

    - -
    -
    - -

    ◆ CAN_TSR_TME0

    - -
    -
    - - - - -
    #define CAN_TSR_TME0   CAN_TSR_TME0_Msk
    -
    -

    Transmit Mailbox 0 Empty

    - -
    -
    - -

    ◆ CAN_TSR_TME1_Pos

    - -
    -
    - - - - -
    #define CAN_TSR_TME1_Pos   (27U)
    -
    - -
    -
    - -

    ◆ CAN_TSR_TME1_Msk

    - -
    -
    - - - - -
    #define CAN_TSR_TME1_Msk   (0x1UL << CAN_TSR_TME1_Pos)
    -
    -

    0x08000000

    - -
    -
    - -

    ◆ CAN_TSR_TME1

    - -
    -
    - - - - -
    #define CAN_TSR_TME1   CAN_TSR_TME1_Msk
    -
    -

    Transmit Mailbox 1 Empty

    - -
    -
    - -

    ◆ CAN_TSR_TME2_Pos

    - -
    -
    - - - - -
    #define CAN_TSR_TME2_Pos   (28U)
    -
    - -
    -
    - -

    ◆ CAN_TSR_TME2_Msk

    - -
    -
    - - - - -
    #define CAN_TSR_TME2_Msk   (0x1UL << CAN_TSR_TME2_Pos)
    -
    -

    0x10000000

    - -
    -
    - -

    ◆ CAN_TSR_TME2

    - -
    -
    - - - - -
    #define CAN_TSR_TME2   CAN_TSR_TME2_Msk
    -
    -

    Transmit Mailbox 2 Empty

    - -
    -
    - -

    ◆ CAN_TSR_LOW_Pos

    - -
    -
    - - - - -
    #define CAN_TSR_LOW_Pos   (29U)
    -
    - -
    -
    - -

    ◆ CAN_TSR_LOW_Msk

    - -
    -
    - - - - -
    #define CAN_TSR_LOW_Msk   (0x7UL << CAN_TSR_LOW_Pos)
    -
    -

    0xE0000000

    - -
    -
    - -

    ◆ CAN_TSR_LOW

    - -
    -
    - - - - -
    #define CAN_TSR_LOW   CAN_TSR_LOW_Msk
    -
    -

    LOW[2:0] bits

    - -
    -
    - -

    ◆ CAN_TSR_LOW0_Pos

    - -
    -
    - - - - -
    #define CAN_TSR_LOW0_Pos   (29U)
    -
    - -
    -
    - -

    ◆ CAN_TSR_LOW0_Msk

    - -
    -
    - - - - -
    #define CAN_TSR_LOW0_Msk   (0x1UL << CAN_TSR_LOW0_Pos)
    -
    -

    0x20000000

    - -
    -
    - -

    ◆ CAN_TSR_LOW0

    - -
    -
    - - - - -
    #define CAN_TSR_LOW0   CAN_TSR_LOW0_Msk
    -
    -

    Lowest Priority Flag for Mailbox 0

    - -
    -
    - -

    ◆ CAN_TSR_LOW1_Pos

    - -
    -
    - - - - -
    #define CAN_TSR_LOW1_Pos   (30U)
    -
    - -
    -
    - -

    ◆ CAN_TSR_LOW1_Msk

    - -
    -
    - - - - -
    #define CAN_TSR_LOW1_Msk   (0x1UL << CAN_TSR_LOW1_Pos)
    -
    -

    0x40000000

    - -
    -
    - -

    ◆ CAN_TSR_LOW1

    - -
    -
    - - - - -
    #define CAN_TSR_LOW1   CAN_TSR_LOW1_Msk
    -
    -

    Lowest Priority Flag for Mailbox 1

    - -
    -
    - -

    ◆ CAN_TSR_LOW2_Pos

    - -
    -
    - - - - -
    #define CAN_TSR_LOW2_Pos   (31U)
    -
    - -
    -
    - -

    ◆ CAN_TSR_LOW2_Msk

    - -
    -
    - - - - -
    #define CAN_TSR_LOW2_Msk   (0x1UL << CAN_TSR_LOW2_Pos)
    -
    -

    0x80000000

    - -
    -
    - -

    ◆ CAN_TSR_LOW2

    - -
    -
    - - - - -
    #define CAN_TSR_LOW2   CAN_TSR_LOW2_Msk
    -
    -

    Lowest Priority Flag for Mailbox 2

    - -
    -
    - -

    ◆ CAN_RF0R_FMP0_Pos

    - -
    -
    - - - - -
    #define CAN_RF0R_FMP0_Pos   (0U)
    -
    - -
    -
    - -

    ◆ CAN_RF0R_FMP0_Msk

    - -
    -
    - - - - -
    #define CAN_RF0R_FMP0_Msk   (0x3UL << CAN_RF0R_FMP0_Pos)
    -
    -

    0x00000003

    - -
    -
    - -

    ◆ CAN_RF0R_FMP0

    - -
    -
    - - - - -
    #define CAN_RF0R_FMP0   CAN_RF0R_FMP0_Msk
    -
    -

    FIFO 0 Message Pending

    - -
    -
    - -

    ◆ CAN_RF0R_FULL0_Pos

    - -
    -
    - - - - -
    #define CAN_RF0R_FULL0_Pos   (3U)
    -
    - -
    -
    - -

    ◆ CAN_RF0R_FULL0_Msk

    - -
    -
    - - - - -
    #define CAN_RF0R_FULL0_Msk   (0x1UL << CAN_RF0R_FULL0_Pos)
    -
    -

    0x00000008

    - -
    -
    - -

    ◆ CAN_RF0R_FULL0

    - -
    -
    - - - - -
    #define CAN_RF0R_FULL0   CAN_RF0R_FULL0_Msk
    -
    -

    FIFO 0 Full

    - -
    -
    - -

    ◆ CAN_RF0R_FOVR0_Pos

    - -
    -
    - - - - -
    #define CAN_RF0R_FOVR0_Pos   (4U)
    -
    - -
    -
    - -

    ◆ CAN_RF0R_FOVR0_Msk

    - -
    -
    - - - - -
    #define CAN_RF0R_FOVR0_Msk   (0x1UL << CAN_RF0R_FOVR0_Pos)
    -
    -

    0x00000010

    - -
    -
    - -

    ◆ CAN_RF0R_FOVR0

    - -
    -
    - - - - -
    #define CAN_RF0R_FOVR0   CAN_RF0R_FOVR0_Msk
    -
    -

    FIFO 0 Overrun

    - -
    -
    - -

    ◆ CAN_RF0R_RFOM0_Pos

    - -
    -
    - - - - -
    #define CAN_RF0R_RFOM0_Pos   (5U)
    -
    - -
    -
    - -

    ◆ CAN_RF0R_RFOM0_Msk

    - -
    -
    - - - - -
    #define CAN_RF0R_RFOM0_Msk   (0x1UL << CAN_RF0R_RFOM0_Pos)
    -
    -

    0x00000020

    - -
    -
    - -

    ◆ CAN_RF0R_RFOM0

    - -
    -
    - - - - -
    #define CAN_RF0R_RFOM0   CAN_RF0R_RFOM0_Msk
    -
    -

    Release FIFO 0 Output Mailbox

    - -
    -
    - -

    ◆ CAN_RF1R_FMP1_Pos

    - -
    -
    - - - - -
    #define CAN_RF1R_FMP1_Pos   (0U)
    -
    - -
    -
    - -

    ◆ CAN_RF1R_FMP1_Msk

    - -
    -
    - - - - -
    #define CAN_RF1R_FMP1_Msk   (0x3UL << CAN_RF1R_FMP1_Pos)
    -
    -

    0x00000003

    - -
    -
    - -

    ◆ CAN_RF1R_FMP1

    - -
    -
    - - - - -
    #define CAN_RF1R_FMP1   CAN_RF1R_FMP1_Msk
    -
    -

    FIFO 1 Message Pending

    - -
    -
    - -

    ◆ CAN_RF1R_FULL1_Pos

    - -
    -
    - - - - -
    #define CAN_RF1R_FULL1_Pos   (3U)
    -
    - -
    -
    - -

    ◆ CAN_RF1R_FULL1_Msk

    - -
    -
    - - - - -
    #define CAN_RF1R_FULL1_Msk   (0x1UL << CAN_RF1R_FULL1_Pos)
    -
    -

    0x00000008

    - -
    -
    - -

    ◆ CAN_RF1R_FULL1

    - -
    -
    - - - - -
    #define CAN_RF1R_FULL1   CAN_RF1R_FULL1_Msk
    -
    -

    FIFO 1 Full

    - -
    -
    - -

    ◆ CAN_RF1R_FOVR1_Pos

    - -
    -
    - - - - -
    #define CAN_RF1R_FOVR1_Pos   (4U)
    -
    - -
    -
    - -

    ◆ CAN_RF1R_FOVR1_Msk

    - -
    -
    - - - - -
    #define CAN_RF1R_FOVR1_Msk   (0x1UL << CAN_RF1R_FOVR1_Pos)
    -
    -

    0x00000010

    - -
    -
    - -

    ◆ CAN_RF1R_FOVR1

    - -
    -
    - - - - -
    #define CAN_RF1R_FOVR1   CAN_RF1R_FOVR1_Msk
    -
    -

    FIFO 1 Overrun

    - -
    -
    - -

    ◆ CAN_RF1R_RFOM1_Pos

    - -
    -
    - - - - -
    #define CAN_RF1R_RFOM1_Pos   (5U)
    -
    - -
    -
    - -

    ◆ CAN_RF1R_RFOM1_Msk

    - -
    -
    - - - - -
    #define CAN_RF1R_RFOM1_Msk   (0x1UL << CAN_RF1R_RFOM1_Pos)
    -
    -

    0x00000020

    - -
    -
    - -

    ◆ CAN_RF1R_RFOM1

    - -
    -
    - - - - -
    #define CAN_RF1R_RFOM1   CAN_RF1R_RFOM1_Msk
    -
    -

    Release FIFO 1 Output Mailbox

    - -
    -
    - -

    ◆ CAN_IER_TMEIE_Pos

    - -
    -
    - - - - -
    #define CAN_IER_TMEIE_Pos   (0U)
    -
    - -
    -
    - -

    ◆ CAN_IER_TMEIE_Msk

    - -
    -
    - - - - -
    #define CAN_IER_TMEIE_Msk   (0x1UL << CAN_IER_TMEIE_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ CAN_IER_TMEIE

    - -
    -
    - - - - -
    #define CAN_IER_TMEIE   CAN_IER_TMEIE_Msk
    -
    -

    Transmit Mailbox Empty Interrupt Enable

    - -
    -
    - -

    ◆ CAN_IER_FMPIE0_Pos

    - -
    -
    - - - - -
    #define CAN_IER_FMPIE0_Pos   (1U)
    -
    - -
    -
    - -

    ◆ CAN_IER_FMPIE0_Msk

    - -
    -
    - - - - -
    #define CAN_IER_FMPIE0_Msk   (0x1UL << CAN_IER_FMPIE0_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ CAN_IER_FMPIE0

    - -
    -
    - - - - -
    #define CAN_IER_FMPIE0   CAN_IER_FMPIE0_Msk
    -
    -

    FIFO Message Pending Interrupt Enable

    - -
    -
    - -

    ◆ CAN_IER_FFIE0_Pos

    - -
    -
    - - - - -
    #define CAN_IER_FFIE0_Pos   (2U)
    -
    - -
    -
    - -

    ◆ CAN_IER_FFIE0_Msk

    - -
    -
    - - - - -
    #define CAN_IER_FFIE0_Msk   (0x1UL << CAN_IER_FFIE0_Pos)
    -
    -

    0x00000004

    - -
    -
    - -

    ◆ CAN_IER_FFIE0

    - -
    -
    - - - - -
    #define CAN_IER_FFIE0   CAN_IER_FFIE0_Msk
    -
    -

    FIFO Full Interrupt Enable

    - -
    -
    - -

    ◆ CAN_IER_FOVIE0_Pos

    - -
    -
    - - - - -
    #define CAN_IER_FOVIE0_Pos   (3U)
    -
    - -
    -
    - -

    ◆ CAN_IER_FOVIE0_Msk

    - -
    -
    - - - - -
    #define CAN_IER_FOVIE0_Msk   (0x1UL << CAN_IER_FOVIE0_Pos)
    -
    -

    0x00000008

    - -
    -
    - -

    ◆ CAN_IER_FOVIE0

    - -
    -
    - - - - -
    #define CAN_IER_FOVIE0   CAN_IER_FOVIE0_Msk
    -
    -

    FIFO Overrun Interrupt Enable

    - -
    -
    - -

    ◆ CAN_IER_FMPIE1_Pos

    - -
    -
    - - - - -
    #define CAN_IER_FMPIE1_Pos   (4U)
    -
    - -
    -
    - -

    ◆ CAN_IER_FMPIE1_Msk

    - -
    -
    - - - - -
    #define CAN_IER_FMPIE1_Msk   (0x1UL << CAN_IER_FMPIE1_Pos)
    -
    -

    0x00000010

    - -
    -
    - -

    ◆ CAN_IER_FMPIE1

    - -
    -
    - - - - -
    #define CAN_IER_FMPIE1   CAN_IER_FMPIE1_Msk
    -
    -

    FIFO Message Pending Interrupt Enable

    - -
    -
    - -

    ◆ CAN_IER_FFIE1_Pos

    - -
    -
    - - - - -
    #define CAN_IER_FFIE1_Pos   (5U)
    -
    - -
    -
    - -

    ◆ CAN_IER_FFIE1_Msk

    - -
    -
    - - - - -
    #define CAN_IER_FFIE1_Msk   (0x1UL << CAN_IER_FFIE1_Pos)
    -
    -

    0x00000020

    - -
    -
    - -

    ◆ CAN_IER_FFIE1

    - -
    -
    - - - - -
    #define CAN_IER_FFIE1   CAN_IER_FFIE1_Msk
    -
    -

    FIFO Full Interrupt Enable

    - -
    -
    - -

    ◆ CAN_IER_FOVIE1_Pos

    - -
    -
    - - - - -
    #define CAN_IER_FOVIE1_Pos   (6U)
    -
    - -
    -
    - -

    ◆ CAN_IER_FOVIE1_Msk

    - -
    -
    - - - - -
    #define CAN_IER_FOVIE1_Msk   (0x1UL << CAN_IER_FOVIE1_Pos)
    -
    -

    0x00000040

    - -
    -
    - -

    ◆ CAN_IER_FOVIE1

    - -
    -
    - - - - -
    #define CAN_IER_FOVIE1   CAN_IER_FOVIE1_Msk
    -
    -

    FIFO Overrun Interrupt Enable

    - -
    -
    - -

    ◆ CAN_IER_EWGIE_Pos [1/2]

    - -
    -
    - - - - -
    #define CAN_IER_EWGIE_Pos   (8U)
    -
    - -
    -
    - -

    ◆ CAN_IER_EWGIE_Pos [2/2]

    - -
    -
    - - - - -
    #define CAN_IER_EWGIE_Pos   (8U)
    -
    - -
    -
    - -

    ◆ CAN_IER_EWGIE_Msk

    - -
    -
    - - - - -
    #define CAN_IER_EWGIE_Msk   (0x1UL << CAN_IER_EWGIE_Pos)
    -
    -

    0x00000100

    - -
    -
    - -

    ◆ CAN_IER_EWGIE

    - -
    -
    - - - - -
    #define CAN_IER_EWGIE   CAN_IER_EWGIE_Msk
    -
    -

    Error Warning Interrupt Enable

    - -
    -
    - -

    ◆ CAN_IER_EPVIE_Pos

    - -
    -
    - - - - -
    #define CAN_IER_EPVIE_Pos   (9U)
    -
    - -
    -
    - -

    ◆ CAN_IER_EPVIE_Msk

    - -
    -
    - - - - -
    #define CAN_IER_EPVIE_Msk   (0x1UL << CAN_IER_EPVIE_Pos)
    -
    -

    0x00000200

    - -
    -
    - -

    ◆ CAN_IER_EPVIE

    - -
    -
    - - - - -
    #define CAN_IER_EPVIE   CAN_IER_EPVIE_Msk
    -
    -

    Error Passive Interrupt Enable

    - -
    -
    - -

    ◆ CAN_IER_BOFIE_Pos

    - -
    -
    - - - - -
    #define CAN_IER_BOFIE_Pos   (10U)
    -
    - -
    -
    - -

    ◆ CAN_IER_BOFIE_Msk

    - -
    -
    - - - - -
    #define CAN_IER_BOFIE_Msk   (0x1UL << CAN_IER_BOFIE_Pos)
    -
    -

    0x00000400

    - -
    -
    - -

    ◆ CAN_IER_BOFIE

    - -
    -
    - - - - -
    #define CAN_IER_BOFIE   CAN_IER_BOFIE_Msk
    -
    -

    Bus-Off Interrupt Enable

    - -
    -
    - -

    ◆ CAN_IER_LECIE_Pos

    - -
    -
    - - - - -
    #define CAN_IER_LECIE_Pos   (11U)
    -
    - -
    -
    - -

    ◆ CAN_IER_LECIE_Msk

    - -
    -
    - - - - -
    #define CAN_IER_LECIE_Msk   (0x1UL << CAN_IER_LECIE_Pos)
    -
    -

    0x00000800

    - -
    -
    - -

    ◆ CAN_IER_LECIE

    - -
    -
    - - - - -
    #define CAN_IER_LECIE   CAN_IER_LECIE_Msk
    -
    -

    Last Error Code Interrupt Enable

    - -
    -
    - -

    ◆ CAN_IER_ERRIE_Pos

    - -
    -
    - - - - -
    #define CAN_IER_ERRIE_Pos   (15U)
    -
    - -
    -
    - -

    ◆ CAN_IER_ERRIE_Msk

    - -
    -
    - - - - -
    #define CAN_IER_ERRIE_Msk   (0x1UL << CAN_IER_ERRIE_Pos)
    -
    -

    0x00008000

    - -
    -
    - -

    ◆ CAN_IER_ERRIE

    - -
    -
    - - - - -
    #define CAN_IER_ERRIE   CAN_IER_ERRIE_Msk
    -
    -

    Error Interrupt Enable

    - -
    -
    - -

    ◆ CAN_IER_WKUIE_Pos

    - -
    -
    - - - - -
    #define CAN_IER_WKUIE_Pos   (16U)
    -
    - -
    -
    - -

    ◆ CAN_IER_WKUIE_Msk

    - -
    -
    - - - - -
    #define CAN_IER_WKUIE_Msk   (0x1UL << CAN_IER_WKUIE_Pos)
    -
    -

    0x00010000

    - -
    -
    - -

    ◆ CAN_IER_WKUIE

    - -
    -
    - - - - -
    #define CAN_IER_WKUIE   CAN_IER_WKUIE_Msk
    -
    -

    Wakeup Interrupt Enable

    - -
    -
    - -

    ◆ CAN_IER_SLKIE_Pos

    - -
    -
    - - - - -
    #define CAN_IER_SLKIE_Pos   (17U)
    -
    - -
    -
    - -

    ◆ CAN_IER_SLKIE_Msk

    - -
    -
    - - - - -
    #define CAN_IER_SLKIE_Msk   (0x1UL << CAN_IER_SLKIE_Pos)
    -
    -

    0x00020000

    - -
    -
    - -

    ◆ CAN_IER_SLKIE

    - -
    -
    - - - - -
    #define CAN_IER_SLKIE   CAN_IER_SLKIE_Msk
    -
    -

    Sleep Interrupt Enable

    - -
    -
    - -

    ◆ CAN_ESR_EWGF_Pos

    - -
    -
    - - - - -
    #define CAN_ESR_EWGF_Pos   (0U)
    -
    - -
    -
    - -

    ◆ CAN_ESR_EWGF_Msk

    - -
    -
    - - - - -
    #define CAN_ESR_EWGF_Msk   (0x1UL << CAN_ESR_EWGF_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ CAN_ESR_EWGF

    - -
    -
    - - - - -
    #define CAN_ESR_EWGF   CAN_ESR_EWGF_Msk
    -
    -

    Error Warning Flag

    - -
    -
    - -

    ◆ CAN_ESR_EPVF_Pos

    - -
    -
    - - - - -
    #define CAN_ESR_EPVF_Pos   (1U)
    -
    - -
    -
    - -

    ◆ CAN_ESR_EPVF_Msk

    - -
    -
    - - - - -
    #define CAN_ESR_EPVF_Msk   (0x1UL << CAN_ESR_EPVF_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ CAN_ESR_EPVF

    - -
    -
    - - - - -
    #define CAN_ESR_EPVF   CAN_ESR_EPVF_Msk
    -
    -

    Error Passive Flag

    - -
    -
    - -

    ◆ CAN_ESR_BOFF_Pos

    - -
    -
    - - - - -
    #define CAN_ESR_BOFF_Pos   (2U)
    -
    - -
    -
    - -

    ◆ CAN_ESR_BOFF_Msk

    - -
    -
    - - - - -
    #define CAN_ESR_BOFF_Msk   (0x1UL << CAN_ESR_BOFF_Pos)
    -
    -

    0x00000004

    - -
    -
    - -

    ◆ CAN_ESR_BOFF

    - -
    -
    - - - - -
    #define CAN_ESR_BOFF   CAN_ESR_BOFF_Msk
    -
    -

    Bus-Off Flag

    - -
    -
    - -

    ◆ CAN_ESR_LEC_Pos

    - -
    -
    - - - - -
    #define CAN_ESR_LEC_Pos   (4U)
    -
    - -
    -
    - -

    ◆ CAN_ESR_LEC_Msk

    - -
    -
    - - - - -
    #define CAN_ESR_LEC_Msk   (0x7UL << CAN_ESR_LEC_Pos)
    -
    -

    0x00000070

    - -
    -
    - -

    ◆ CAN_ESR_LEC

    - -
    -
    - - - - -
    #define CAN_ESR_LEC   CAN_ESR_LEC_Msk
    -
    -

    LEC[2:0] bits (Last Error Code)

    - -
    -
    - -

    ◆ CAN_ESR_LEC_0

    - -
    -
    - - - - -
    #define CAN_ESR_LEC_0   (0x1UL << CAN_ESR_LEC_Pos)
    -
    -

    0x00000010

    - -
    -
    - -

    ◆ CAN_ESR_LEC_1

    - -
    -
    - - - - -
    #define CAN_ESR_LEC_1   (0x2UL << CAN_ESR_LEC_Pos)
    -
    -

    0x00000020

    - -
    -
    - -

    ◆ CAN_ESR_LEC_2

    - -
    -
    - - - - -
    #define CAN_ESR_LEC_2   (0x4UL << CAN_ESR_LEC_Pos)
    -
    -

    0x00000040

    - -
    -
    - -

    ◆ CAN_ESR_TEC_Pos

    - -
    -
    - - - - -
    #define CAN_ESR_TEC_Pos   (16U)
    -
    - -
    -
    - -

    ◆ CAN_ESR_TEC_Msk

    - -
    -
    - - - - -
    #define CAN_ESR_TEC_Msk   (0xFFUL << CAN_ESR_TEC_Pos)
    -
    -

    0x00FF0000

    - -
    -
    - -

    ◆ CAN_ESR_TEC

    - -
    -
    - - - - -
    #define CAN_ESR_TEC   CAN_ESR_TEC_Msk
    -
    -

    Least significant byte of the 9-bit Transmit Error Counter

    - -
    -
    - -

    ◆ CAN_ESR_REC_Pos

    - -
    -
    - - - - -
    #define CAN_ESR_REC_Pos   (24U)
    -
    - -
    -
    - -

    ◆ CAN_ESR_REC_Msk

    - -
    -
    - - - - -
    #define CAN_ESR_REC_Msk   (0xFFUL << CAN_ESR_REC_Pos)
    -
    -

    0xFF000000

    - -
    -
    - -

    ◆ CAN_ESR_REC

    - -
    -
    - - - - -
    #define CAN_ESR_REC   CAN_ESR_REC_Msk
    -
    -

    Receive Error Counter

    - -
    -
    - -

    ◆ CAN_BTR_BRP_Pos

    - -
    -
    - - - - -
    #define CAN_BTR_BRP_Pos   (0U)
    -
    - -
    -
    - -

    ◆ CAN_BTR_BRP_Msk

    - -
    -
    - - - - -
    #define CAN_BTR_BRP_Msk   (0x3FFUL << CAN_BTR_BRP_Pos)
    -
    -

    0x000003FF

    - -
    -
    - -

    ◆ CAN_BTR_BRP

    - -
    -
    - - - - -
    #define CAN_BTR_BRP   CAN_BTR_BRP_Msk
    -
    -

    Baud Rate Prescaler

    - -
    -
    - -

    ◆ CAN_BTR_TS1_Pos

    - -
    -
    - - - - -
    #define CAN_BTR_TS1_Pos   (16U)
    -
    - -
    -
    - -

    ◆ CAN_BTR_TS1_Msk

    - -
    -
    - - - - -
    #define CAN_BTR_TS1_Msk   (0xFUL << CAN_BTR_TS1_Pos)
    -
    -

    0x000F0000

    - -
    -
    - -

    ◆ CAN_BTR_TS1

    - -
    -
    - - - - -
    #define CAN_BTR_TS1   CAN_BTR_TS1_Msk
    -
    -

    Time Segment 1

    - -
    -
    - -

    ◆ CAN_BTR_TS1_0

    - -
    -
    - - - - -
    #define CAN_BTR_TS1_0   (0x1UL << CAN_BTR_TS1_Pos)
    -
    -

    0x00010000

    - -
    -
    - -

    ◆ CAN_BTR_TS1_1

    - -
    -
    - - - - -
    #define CAN_BTR_TS1_1   (0x2UL << CAN_BTR_TS1_Pos)
    -
    -

    0x00020000

    - -
    -
    - -

    ◆ CAN_BTR_TS1_2

    - -
    -
    - - - - -
    #define CAN_BTR_TS1_2   (0x4UL << CAN_BTR_TS1_Pos)
    -
    -

    0x00040000

    - -
    -
    - -

    ◆ CAN_BTR_TS1_3

    - -
    -
    - - - - -
    #define CAN_BTR_TS1_3   (0x8UL << CAN_BTR_TS1_Pos)
    -
    -

    0x00080000

    - -
    -
    - -

    ◆ CAN_BTR_TS2_Pos

    - -
    -
    - - - - -
    #define CAN_BTR_TS2_Pos   (20U)
    -
    - -
    -
    - -

    ◆ CAN_BTR_TS2_Msk

    - -
    -
    - - - - -
    #define CAN_BTR_TS2_Msk   (0x7UL << CAN_BTR_TS2_Pos)
    -
    -

    0x00700000

    - -
    -
    - -

    ◆ CAN_BTR_TS2

    - -
    -
    - - - - -
    #define CAN_BTR_TS2   CAN_BTR_TS2_Msk
    -
    -

    Time Segment 2

    - -
    -
    - -

    ◆ CAN_BTR_TS2_0

    - -
    -
    - - - - -
    #define CAN_BTR_TS2_0   (0x1UL << CAN_BTR_TS2_Pos)
    -
    -

    0x00100000

    - -
    -
    - -

    ◆ CAN_BTR_TS2_1

    - -
    -
    - - - - -
    #define CAN_BTR_TS2_1   (0x2UL << CAN_BTR_TS2_Pos)
    -
    -

    0x00200000

    - -
    -
    - -

    ◆ CAN_BTR_TS2_2

    - -
    -
    - - - - -
    #define CAN_BTR_TS2_2   (0x4UL << CAN_BTR_TS2_Pos)
    -
    -

    0x00400000

    - -
    -
    - -

    ◆ CAN_BTR_SJW_Pos

    - -
    -
    - - - - -
    #define CAN_BTR_SJW_Pos   (24U)
    -
    - -
    -
    - -

    ◆ CAN_BTR_SJW_Msk

    - -
    -
    - - - - -
    #define CAN_BTR_SJW_Msk   (0x3UL << CAN_BTR_SJW_Pos)
    -
    -

    0x03000000

    - -
    -
    - -

    ◆ CAN_BTR_SJW

    - -
    -
    - - - - -
    #define CAN_BTR_SJW   CAN_BTR_SJW_Msk
    -
    -

    Resynchronization Jump Width

    - -
    -
    - -

    ◆ CAN_BTR_SJW_0

    - -
    -
    - - - - -
    #define CAN_BTR_SJW_0   (0x1UL << CAN_BTR_SJW_Pos)
    -
    -

    0x01000000

    - -
    -
    - -

    ◆ CAN_BTR_SJW_1

    - -
    -
    - - - - -
    #define CAN_BTR_SJW_1   (0x2UL << CAN_BTR_SJW_Pos)
    -
    -

    0x02000000

    - -
    -
    - -

    ◆ CAN_BTR_LBKM_Pos

    - -
    -
    - - - - -
    #define CAN_BTR_LBKM_Pos   (30U)
    -
    - -
    -
    - -

    ◆ CAN_BTR_LBKM_Msk

    - -
    -
    - - - - -
    #define CAN_BTR_LBKM_Msk   (0x1UL << CAN_BTR_LBKM_Pos)
    -
    -

    0x40000000

    - -
    -
    - -

    ◆ CAN_BTR_LBKM

    - -
    -
    - - - - -
    #define CAN_BTR_LBKM   CAN_BTR_LBKM_Msk
    -
    -

    Loop Back Mode (Debug)

    - -
    -
    - -

    ◆ CAN_BTR_SILM_Pos

    - -
    -
    - - - - -
    #define CAN_BTR_SILM_Pos   (31U)
    -
    - -
    -
    - -

    ◆ CAN_BTR_SILM_Msk

    - -
    -
    - - - - -
    #define CAN_BTR_SILM_Msk   (0x1UL << CAN_BTR_SILM_Pos)
    -
    -

    0x80000000

    - -
    -
    - -

    ◆ CAN_BTR_SILM

    - -
    -
    - - - - -
    #define CAN_BTR_SILM   CAN_BTR_SILM_Msk
    -
    -

    Silent Mode Mailbox registers

    - -
    -
    - -

    ◆ CAN_TI0R_TXRQ_Pos

    - -
    -
    - - - - -
    #define CAN_TI0R_TXRQ_Pos   (0U)
    -
    - -
    -
    - -

    ◆ CAN_TI0R_TXRQ_Msk

    - -
    -
    - - - - -
    #define CAN_TI0R_TXRQ_Msk   (0x1UL << CAN_TI0R_TXRQ_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ CAN_TI0R_TXRQ

    - -
    -
    - - - - -
    #define CAN_TI0R_TXRQ   CAN_TI0R_TXRQ_Msk
    -
    -

    Transmit Mailbox Request

    - -
    -
    - -

    ◆ CAN_TI0R_RTR_Pos

    - -
    -
    - - - - -
    #define CAN_TI0R_RTR_Pos   (1U)
    -
    - -
    -
    - -

    ◆ CAN_TI0R_RTR_Msk

    - -
    -
    - - - - -
    #define CAN_TI0R_RTR_Msk   (0x1UL << CAN_TI0R_RTR_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ CAN_TI0R_RTR

    - -
    -
    - - - - -
    #define CAN_TI0R_RTR   CAN_TI0R_RTR_Msk
    -
    -

    Remote Transmission Request

    - -
    -
    - -

    ◆ CAN_TI0R_IDE_Pos

    - -
    -
    - - - - -
    #define CAN_TI0R_IDE_Pos   (2U)
    -
    - -
    -
    - -

    ◆ CAN_TI0R_IDE_Msk

    - -
    -
    - - - - -
    #define CAN_TI0R_IDE_Msk   (0x1UL << CAN_TI0R_IDE_Pos)
    -
    -

    0x00000004

    - -
    -
    - -

    ◆ CAN_TI0R_IDE

    - -
    -
    - - - - -
    #define CAN_TI0R_IDE   CAN_TI0R_IDE_Msk
    -
    -

    Identifier Extension

    - -
    -
    - -

    ◆ CAN_TI0R_EXID_Pos

    - -
    -
    - - - - -
    #define CAN_TI0R_EXID_Pos   (3U)
    -
    - -
    -
    - -

    ◆ CAN_TI0R_EXID_Msk

    - -
    -
    - - - - -
    #define CAN_TI0R_EXID_Msk   (0x3FFFFUL << CAN_TI0R_EXID_Pos)
    -
    -

    0x001FFFF8

    - -
    -
    - -

    ◆ CAN_TI0R_EXID

    - -
    -
    - - - - -
    #define CAN_TI0R_EXID   CAN_TI0R_EXID_Msk
    -
    -

    Extended Identifier

    - -
    -
    - -

    ◆ CAN_TI0R_STID_Pos

    - -
    -
    - - - - -
    #define CAN_TI0R_STID_Pos   (21U)
    -
    - -
    -
    - -

    ◆ CAN_TI0R_STID_Msk

    - -
    -
    - - - - -
    #define CAN_TI0R_STID_Msk   (0x7FFUL << CAN_TI0R_STID_Pos)
    -
    -

    0xFFE00000

    - -
    -
    - -

    ◆ CAN_TI0R_STID

    - -
    -
    - - - - -
    #define CAN_TI0R_STID   CAN_TI0R_STID_Msk
    -
    -

    Standard Identifier or Extended Identifier

    - -
    -
    - -

    ◆ CAN_TDT0R_DLC_Pos

    - -
    -
    - - - - -
    #define CAN_TDT0R_DLC_Pos   (0U)
    -
    - -
    -
    - -

    ◆ CAN_TDT0R_DLC_Msk

    - -
    -
    - - - - -
    #define CAN_TDT0R_DLC_Msk   (0xFUL << CAN_TDT0R_DLC_Pos)
    -
    -

    0x0000000F

    - -
    -
    - -

    ◆ CAN_TDT0R_DLC

    - -
    -
    - - - - -
    #define CAN_TDT0R_DLC   CAN_TDT0R_DLC_Msk
    -
    -

    Data Length Code

    - -
    -
    - -

    ◆ CAN_TDT0R_TGT_Pos

    - -
    -
    - - - - -
    #define CAN_TDT0R_TGT_Pos   (8U)
    -
    - -
    -
    - -

    ◆ CAN_TDT0R_TGT_Msk

    - -
    -
    - - - - -
    #define CAN_TDT0R_TGT_Msk   (0x1UL << CAN_TDT0R_TGT_Pos)
    -
    -

    0x00000100

    - -
    -
    - -

    ◆ CAN_TDT0R_TGT

    - -
    -
    - - - - -
    #define CAN_TDT0R_TGT   CAN_TDT0R_TGT_Msk
    -
    -

    Transmit Global Time

    - -
    -
    - -

    ◆ CAN_TDT0R_TIME_Pos

    - -
    -
    - - - - -
    #define CAN_TDT0R_TIME_Pos   (16U)
    -
    - -
    -
    - -

    ◆ CAN_TDT0R_TIME_Msk

    - -
    -
    - - - - -
    #define CAN_TDT0R_TIME_Msk   (0xFFFFUL << CAN_TDT0R_TIME_Pos)
    -
    -

    0xFFFF0000

    - -
    -
    - -

    ◆ CAN_TDT0R_TIME

    - -
    -
    - - - - -
    #define CAN_TDT0R_TIME   CAN_TDT0R_TIME_Msk
    -
    -

    Message Time Stamp

    - -
    -
    - -

    ◆ CAN_TDL0R_DATA0_Pos

    - -
    -
    - - - - -
    #define CAN_TDL0R_DATA0_Pos   (0U)
    -
    - -
    -
    - -

    ◆ CAN_TDL0R_DATA0_Msk

    - -
    -
    - - - - -
    #define CAN_TDL0R_DATA0_Msk   (0xFFUL << CAN_TDL0R_DATA0_Pos)
    -
    -

    0x000000FF

    - -
    -
    - -

    ◆ CAN_TDL0R_DATA0

    - -
    -
    - - - - -
    #define CAN_TDL0R_DATA0   CAN_TDL0R_DATA0_Msk
    -
    -

    Data byte 0

    - -
    -
    - -

    ◆ CAN_TDL0R_DATA1_Pos

    - -
    -
    - - - - -
    #define CAN_TDL0R_DATA1_Pos   (8U)
    -
    - -
    -
    - -

    ◆ CAN_TDL0R_DATA1_Msk

    - -
    -
    - - - - -
    #define CAN_TDL0R_DATA1_Msk   (0xFFUL << CAN_TDL0R_DATA1_Pos)
    -
    -

    0x0000FF00

    - -
    -
    - -

    ◆ CAN_TDL0R_DATA1

    - -
    -
    - - - - -
    #define CAN_TDL0R_DATA1   CAN_TDL0R_DATA1_Msk
    -
    -

    Data byte 1

    - -
    -
    - -

    ◆ CAN_TDL0R_DATA2_Pos

    - -
    -
    - - - - -
    #define CAN_TDL0R_DATA2_Pos   (16U)
    -
    - -
    -
    - -

    ◆ CAN_TDL0R_DATA2_Msk

    - -
    -
    - - - - -
    #define CAN_TDL0R_DATA2_Msk   (0xFFUL << CAN_TDL0R_DATA2_Pos)
    -
    -

    0x00FF0000

    - -
    -
    - -

    ◆ CAN_TDL0R_DATA2

    - -
    -
    - - - - -
    #define CAN_TDL0R_DATA2   CAN_TDL0R_DATA2_Msk
    -
    -

    Data byte 2

    - -
    -
    - -

    ◆ CAN_TDL0R_DATA3_Pos

    - -
    -
    - - - - -
    #define CAN_TDL0R_DATA3_Pos   (24U)
    -
    - -
    -
    - -

    ◆ CAN_TDL0R_DATA3_Msk

    - -
    -
    - - - - -
    #define CAN_TDL0R_DATA3_Msk   (0xFFUL << CAN_TDL0R_DATA3_Pos)
    -
    -

    0xFF000000

    - -
    -
    - -

    ◆ CAN_TDL0R_DATA3

    - -
    -
    - - - - -
    #define CAN_TDL0R_DATA3   CAN_TDL0R_DATA3_Msk
    -
    -

    Data byte 3

    - -
    -
    - -

    ◆ CAN_TDH0R_DATA4_Pos

    - -
    -
    - - - - -
    #define CAN_TDH0R_DATA4_Pos   (0U)
    -
    - -
    -
    - -

    ◆ CAN_TDH0R_DATA4_Msk

    - -
    -
    - - - - -
    #define CAN_TDH0R_DATA4_Msk   (0xFFUL << CAN_TDH0R_DATA4_Pos)
    -
    -

    0x000000FF

    - -
    -
    - -

    ◆ CAN_TDH0R_DATA4

    - -
    -
    - - - - -
    #define CAN_TDH0R_DATA4   CAN_TDH0R_DATA4_Msk
    -
    -

    Data byte 4

    - -
    -
    - -

    ◆ CAN_TDH0R_DATA5_Pos

    - -
    -
    - - - - -
    #define CAN_TDH0R_DATA5_Pos   (8U)
    -
    - -
    -
    - -

    ◆ CAN_TDH0R_DATA5_Msk

    - -
    -
    - - - - -
    #define CAN_TDH0R_DATA5_Msk   (0xFFUL << CAN_TDH0R_DATA5_Pos)
    -
    -

    0x0000FF00

    - -
    -
    - -

    ◆ CAN_TDH0R_DATA5

    - -
    -
    - - - - -
    #define CAN_TDH0R_DATA5   CAN_TDH0R_DATA5_Msk
    -
    -

    Data byte 5

    - -
    -
    - -

    ◆ CAN_TDH0R_DATA6_Pos

    - -
    -
    - - - - -
    #define CAN_TDH0R_DATA6_Pos   (16U)
    -
    - -
    -
    - -

    ◆ CAN_TDH0R_DATA6_Msk

    - -
    -
    - - - - -
    #define CAN_TDH0R_DATA6_Msk   (0xFFUL << CAN_TDH0R_DATA6_Pos)
    -
    -

    0x00FF0000

    - -
    -
    - -

    ◆ CAN_TDH0R_DATA6

    - -
    -
    - - - - -
    #define CAN_TDH0R_DATA6   CAN_TDH0R_DATA6_Msk
    -
    -

    Data byte 6

    - -
    -
    - -

    ◆ CAN_TDH0R_DATA7_Pos

    - -
    -
    - - - - -
    #define CAN_TDH0R_DATA7_Pos   (24U)
    -
    - -
    -
    - -

    ◆ CAN_TDH0R_DATA7_Msk

    - -
    -
    - - - - -
    #define CAN_TDH0R_DATA7_Msk   (0xFFUL << CAN_TDH0R_DATA7_Pos)
    -
    -

    0xFF000000

    - -
    -
    - -

    ◆ CAN_TDH0R_DATA7

    - -
    -
    - - - - -
    #define CAN_TDH0R_DATA7   CAN_TDH0R_DATA7_Msk
    -
    -

    Data byte 7

    - -
    -
    - -

    ◆ CAN_TI1R_TXRQ_Pos

    - -
    -
    - - - - -
    #define CAN_TI1R_TXRQ_Pos   (0U)
    -
    - -
    -
    - -

    ◆ CAN_TI1R_TXRQ_Msk

    - -
    -
    - - - - -
    #define CAN_TI1R_TXRQ_Msk   (0x1UL << CAN_TI1R_TXRQ_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ CAN_TI1R_TXRQ

    - -
    -
    - - - - -
    #define CAN_TI1R_TXRQ   CAN_TI1R_TXRQ_Msk
    -
    -

    Transmit Mailbox Request

    - -
    -
    - -

    ◆ CAN_TI1R_RTR_Pos

    - -
    -
    - - - - -
    #define CAN_TI1R_RTR_Pos   (1U)
    -
    - -
    -
    - -

    ◆ CAN_TI1R_RTR_Msk

    - -
    -
    - - - - -
    #define CAN_TI1R_RTR_Msk   (0x1UL << CAN_TI1R_RTR_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ CAN_TI1R_RTR

    - -
    -
    - - - - -
    #define CAN_TI1R_RTR   CAN_TI1R_RTR_Msk
    -
    -

    Remote Transmission Request

    - -
    -
    - -

    ◆ CAN_TI1R_IDE_Pos

    - -
    -
    - - - - -
    #define CAN_TI1R_IDE_Pos   (2U)
    -
    - -
    -
    - -

    ◆ CAN_TI1R_IDE_Msk

    - -
    -
    - - - - -
    #define CAN_TI1R_IDE_Msk   (0x1UL << CAN_TI1R_IDE_Pos)
    -
    -

    0x00000004

    - -
    -
    - -

    ◆ CAN_TI1R_IDE

    - -
    -
    - - - - -
    #define CAN_TI1R_IDE   CAN_TI1R_IDE_Msk
    -
    -

    Identifier Extension

    - -
    -
    - -

    ◆ CAN_TI1R_EXID_Pos

    - -
    -
    - - - - -
    #define CAN_TI1R_EXID_Pos   (3U)
    -
    - -
    -
    - -

    ◆ CAN_TI1R_EXID_Msk

    - -
    -
    - - - - -
    #define CAN_TI1R_EXID_Msk   (0x3FFFFUL << CAN_TI1R_EXID_Pos)
    -
    -

    0x001FFFF8

    - -
    -
    - -

    ◆ CAN_TI1R_EXID

    - -
    -
    - - - - -
    #define CAN_TI1R_EXID   CAN_TI1R_EXID_Msk
    -
    -

    Extended Identifier

    - -
    -
    - -

    ◆ CAN_TI1R_STID_Pos

    - -
    -
    - - - - -
    #define CAN_TI1R_STID_Pos   (21U)
    -
    - -
    -
    - -

    ◆ CAN_TI1R_STID_Msk

    - -
    -
    - - - - -
    #define CAN_TI1R_STID_Msk   (0x7FFUL << CAN_TI1R_STID_Pos)
    -
    -

    0xFFE00000

    - -
    -
    - -

    ◆ CAN_TI1R_STID

    - -
    -
    - - - - -
    #define CAN_TI1R_STID   CAN_TI1R_STID_Msk
    -
    -

    Standard Identifier or Extended Identifier

    - -
    -
    - -

    ◆ CAN_TDT1R_DLC_Pos

    - -
    -
    - - - - -
    #define CAN_TDT1R_DLC_Pos   (0U)
    -
    - -
    -
    - -

    ◆ CAN_TDT1R_DLC_Msk

    - -
    -
    - - - - -
    #define CAN_TDT1R_DLC_Msk   (0xFUL << CAN_TDT1R_DLC_Pos)
    -
    -

    0x0000000F

    - -
    -
    - -

    ◆ CAN_TDT1R_DLC

    - -
    -
    - - - - -
    #define CAN_TDT1R_DLC   CAN_TDT1R_DLC_Msk
    -
    -

    Data Length Code

    - -
    -
    - -

    ◆ CAN_TDT1R_TGT_Pos

    - -
    -
    - - - - -
    #define CAN_TDT1R_TGT_Pos   (8U)
    -
    - -
    -
    - -

    ◆ CAN_TDT1R_TGT_Msk

    - -
    -
    - - - - -
    #define CAN_TDT1R_TGT_Msk   (0x1UL << CAN_TDT1R_TGT_Pos)
    -
    -

    0x00000100

    - -
    -
    - -

    ◆ CAN_TDT1R_TGT

    - -
    -
    - - - - -
    #define CAN_TDT1R_TGT   CAN_TDT1R_TGT_Msk
    -
    -

    Transmit Global Time

    - -
    -
    - -

    ◆ CAN_TDT1R_TIME_Pos

    - -
    -
    - - - - -
    #define CAN_TDT1R_TIME_Pos   (16U)
    -
    - -
    -
    - -

    ◆ CAN_TDT1R_TIME_Msk

    - -
    -
    - - - - -
    #define CAN_TDT1R_TIME_Msk   (0xFFFFUL << CAN_TDT1R_TIME_Pos)
    -
    -

    0xFFFF0000

    - -
    -
    - -

    ◆ CAN_TDT1R_TIME

    - -
    -
    - - - - -
    #define CAN_TDT1R_TIME   CAN_TDT1R_TIME_Msk
    -
    -

    Message Time Stamp

    - -
    -
    - -

    ◆ CAN_TDL1R_DATA0_Pos

    - -
    -
    - - - - -
    #define CAN_TDL1R_DATA0_Pos   (0U)
    -
    - -
    -
    - -

    ◆ CAN_TDL1R_DATA0_Msk

    - -
    -
    - - - - -
    #define CAN_TDL1R_DATA0_Msk   (0xFFUL << CAN_TDL1R_DATA0_Pos)
    -
    -

    0x000000FF

    - -
    -
    - -

    ◆ CAN_TDL1R_DATA0

    - -
    -
    - - - - -
    #define CAN_TDL1R_DATA0   CAN_TDL1R_DATA0_Msk
    -
    -

    Data byte 0

    - -
    -
    - -

    ◆ CAN_TDL1R_DATA1_Pos

    - -
    -
    - - - - -
    #define CAN_TDL1R_DATA1_Pos   (8U)
    -
    - -
    -
    - -

    ◆ CAN_TDL1R_DATA1_Msk

    - -
    -
    - - - - -
    #define CAN_TDL1R_DATA1_Msk   (0xFFUL << CAN_TDL1R_DATA1_Pos)
    -
    -

    0x0000FF00

    - -
    -
    - -

    ◆ CAN_TDL1R_DATA1

    - -
    -
    - - - - -
    #define CAN_TDL1R_DATA1   CAN_TDL1R_DATA1_Msk
    -
    -

    Data byte 1

    - -
    -
    - -

    ◆ CAN_TDL1R_DATA2_Pos

    - -
    -
    - - - - -
    #define CAN_TDL1R_DATA2_Pos   (16U)
    -
    - -
    -
    - -

    ◆ CAN_TDL1R_DATA2_Msk

    - -
    -
    - - - - -
    #define CAN_TDL1R_DATA2_Msk   (0xFFUL << CAN_TDL1R_DATA2_Pos)
    -
    -

    0x00FF0000

    - -
    -
    - -

    ◆ CAN_TDL1R_DATA2

    - -
    -
    - - - - -
    #define CAN_TDL1R_DATA2   CAN_TDL1R_DATA2_Msk
    -
    -

    Data byte 2

    - -
    -
    - -

    ◆ CAN_TDL1R_DATA3_Pos

    - -
    -
    - - - - -
    #define CAN_TDL1R_DATA3_Pos   (24U)
    -
    - -
    -
    - -

    ◆ CAN_TDL1R_DATA3_Msk

    - -
    -
    - - - - -
    #define CAN_TDL1R_DATA3_Msk   (0xFFUL << CAN_TDL1R_DATA3_Pos)
    -
    -

    0xFF000000

    - -
    -
    - -

    ◆ CAN_TDL1R_DATA3

    - -
    -
    - - - - -
    #define CAN_TDL1R_DATA3   CAN_TDL1R_DATA3_Msk
    -
    -

    Data byte 3

    - -
    -
    - -

    ◆ CAN_TDH1R_DATA4_Pos

    - -
    -
    - - - - -
    #define CAN_TDH1R_DATA4_Pos   (0U)
    -
    - -
    -
    - -

    ◆ CAN_TDH1R_DATA4_Msk

    - -
    -
    - - - - -
    #define CAN_TDH1R_DATA4_Msk   (0xFFUL << CAN_TDH1R_DATA4_Pos)
    -
    -

    0x000000FF

    - -
    -
    - -

    ◆ CAN_TDH1R_DATA4

    - -
    -
    - - - - -
    #define CAN_TDH1R_DATA4   CAN_TDH1R_DATA4_Msk
    -
    -

    Data byte 4

    - -
    -
    - -

    ◆ CAN_TDH1R_DATA5_Pos

    - -
    -
    - - - - -
    #define CAN_TDH1R_DATA5_Pos   (8U)
    -
    - -
    -
    - -

    ◆ CAN_TDH1R_DATA5_Msk

    - -
    -
    - - - - -
    #define CAN_TDH1R_DATA5_Msk   (0xFFUL << CAN_TDH1R_DATA5_Pos)
    -
    -

    0x0000FF00

    - -
    -
    - -

    ◆ CAN_TDH1R_DATA5

    - -
    -
    - - - - -
    #define CAN_TDH1R_DATA5   CAN_TDH1R_DATA5_Msk
    -
    -

    Data byte 5

    - -
    -
    - -

    ◆ CAN_TDH1R_DATA6_Pos

    - -
    -
    - - - - -
    #define CAN_TDH1R_DATA6_Pos   (16U)
    -
    - -
    -
    - -

    ◆ CAN_TDH1R_DATA6_Msk

    - -
    -
    - - - - -
    #define CAN_TDH1R_DATA6_Msk   (0xFFUL << CAN_TDH1R_DATA6_Pos)
    -
    -

    0x00FF0000

    - -
    -
    - -

    ◆ CAN_TDH1R_DATA6

    - -
    -
    - - - - -
    #define CAN_TDH1R_DATA6   CAN_TDH1R_DATA6_Msk
    -
    -

    Data byte 6

    - -
    -
    - -

    ◆ CAN_TDH1R_DATA7_Pos

    - -
    -
    - - - - -
    #define CAN_TDH1R_DATA7_Pos   (24U)
    -
    - -
    -
    - -

    ◆ CAN_TDH1R_DATA7_Msk

    - -
    -
    - - - - -
    #define CAN_TDH1R_DATA7_Msk   (0xFFUL << CAN_TDH1R_DATA7_Pos)
    -
    -

    0xFF000000

    - -
    -
    - -

    ◆ CAN_TDH1R_DATA7

    - -
    -
    - - - - -
    #define CAN_TDH1R_DATA7   CAN_TDH1R_DATA7_Msk
    -
    -

    Data byte 7

    - -
    -
    - -

    ◆ CAN_TI2R_TXRQ_Pos

    - -
    -
    - - - - -
    #define CAN_TI2R_TXRQ_Pos   (0U)
    -
    - -
    -
    - -

    ◆ CAN_TI2R_TXRQ_Msk

    - -
    -
    - - - - -
    #define CAN_TI2R_TXRQ_Msk   (0x1UL << CAN_TI2R_TXRQ_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ CAN_TI2R_TXRQ

    - -
    -
    - - - - -
    #define CAN_TI2R_TXRQ   CAN_TI2R_TXRQ_Msk
    -
    -

    Transmit Mailbox Request

    - -
    -
    - -

    ◆ CAN_TI2R_RTR_Pos

    - -
    -
    - - - - -
    #define CAN_TI2R_RTR_Pos   (1U)
    -
    - -
    -
    - -

    ◆ CAN_TI2R_RTR_Msk

    - -
    -
    - - - - -
    #define CAN_TI2R_RTR_Msk   (0x1UL << CAN_TI2R_RTR_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ CAN_TI2R_RTR

    - -
    -
    - - - - -
    #define CAN_TI2R_RTR   CAN_TI2R_RTR_Msk
    -
    -

    Remote Transmission Request

    - -
    -
    - -

    ◆ CAN_TI2R_IDE_Pos

    - -
    -
    - - - - -
    #define CAN_TI2R_IDE_Pos   (2U)
    -
    - -
    -
    - -

    ◆ CAN_TI2R_IDE_Msk

    - -
    -
    - - - - -
    #define CAN_TI2R_IDE_Msk   (0x1UL << CAN_TI2R_IDE_Pos)
    -
    -

    0x00000004

    - -
    -
    - -

    ◆ CAN_TI2R_IDE

    - -
    -
    - - - - -
    #define CAN_TI2R_IDE   CAN_TI2R_IDE_Msk
    -
    -

    Identifier Extension

    - -
    -
    - -

    ◆ CAN_TI2R_EXID_Pos

    - -
    -
    - - - - -
    #define CAN_TI2R_EXID_Pos   (3U)
    -
    - -
    -
    - -

    ◆ CAN_TI2R_EXID_Msk

    - -
    -
    - - - - -
    #define CAN_TI2R_EXID_Msk   (0x3FFFFUL << CAN_TI2R_EXID_Pos)
    -
    -

    0x001FFFF8

    - -
    -
    - -

    ◆ CAN_TI2R_EXID

    - -
    -
    - - - - -
    #define CAN_TI2R_EXID   CAN_TI2R_EXID_Msk
    -
    -

    Extended identifier

    - -
    -
    - -

    ◆ CAN_TI2R_STID_Pos

    - -
    -
    - - - - -
    #define CAN_TI2R_STID_Pos   (21U)
    -
    - -
    -
    - -

    ◆ CAN_TI2R_STID_Msk

    - -
    -
    - - - - -
    #define CAN_TI2R_STID_Msk   (0x7FFUL << CAN_TI2R_STID_Pos)
    -
    -

    0xFFE00000

    - -
    -
    - -

    ◆ CAN_TI2R_STID

    - -
    -
    - - - - -
    #define CAN_TI2R_STID   CAN_TI2R_STID_Msk
    -
    -

    Standard Identifier or Extended Identifier

    - -
    -
    - -

    ◆ CAN_TDT2R_DLC_Pos

    - -
    -
    - - - - -
    #define CAN_TDT2R_DLC_Pos   (0U)
    -
    - -
    -
    - -

    ◆ CAN_TDT2R_DLC_Msk

    - -
    -
    - - - - -
    #define CAN_TDT2R_DLC_Msk   (0xFUL << CAN_TDT2R_DLC_Pos)
    -
    -

    0x0000000F

    - -
    -
    - -

    ◆ CAN_TDT2R_DLC

    - -
    -
    - - - - -
    #define CAN_TDT2R_DLC   CAN_TDT2R_DLC_Msk
    -
    -

    Data Length Code

    - -
    -
    - -

    ◆ CAN_TDT2R_TGT_Pos

    - -
    -
    - - - - -
    #define CAN_TDT2R_TGT_Pos   (8U)
    -
    - -
    -
    - -

    ◆ CAN_TDT2R_TGT_Msk

    - -
    -
    - - - - -
    #define CAN_TDT2R_TGT_Msk   (0x1UL << CAN_TDT2R_TGT_Pos)
    -
    -

    0x00000100

    - -
    -
    - -

    ◆ CAN_TDT2R_TGT

    - -
    -
    - - - - -
    #define CAN_TDT2R_TGT   CAN_TDT2R_TGT_Msk
    -
    -

    Transmit Global Time

    - -
    -
    - -

    ◆ CAN_TDT2R_TIME_Pos

    - -
    -
    - - - - -
    #define CAN_TDT2R_TIME_Pos   (16U)
    -
    - -
    -
    - -

    ◆ CAN_TDT2R_TIME_Msk

    - -
    -
    - - - - -
    #define CAN_TDT2R_TIME_Msk   (0xFFFFUL << CAN_TDT2R_TIME_Pos)
    -
    -

    0xFFFF0000

    - -
    -
    - -

    ◆ CAN_TDT2R_TIME

    - -
    -
    - - - - -
    #define CAN_TDT2R_TIME   CAN_TDT2R_TIME_Msk
    -
    -

    Message Time Stamp

    - -
    -
    - -

    ◆ CAN_TDL2R_DATA0_Pos

    - -
    -
    - - - - -
    #define CAN_TDL2R_DATA0_Pos   (0U)
    -
    - -
    -
    - -

    ◆ CAN_TDL2R_DATA0_Msk

    - -
    -
    - - - - -
    #define CAN_TDL2R_DATA0_Msk   (0xFFUL << CAN_TDL2R_DATA0_Pos)
    -
    -

    0x000000FF

    - -
    -
    - -

    ◆ CAN_TDL2R_DATA0

    - -
    -
    - - - - -
    #define CAN_TDL2R_DATA0   CAN_TDL2R_DATA0_Msk
    -
    -

    Data byte 0

    - -
    -
    - -

    ◆ CAN_TDL2R_DATA1_Pos

    - -
    -
    - - - - -
    #define CAN_TDL2R_DATA1_Pos   (8U)
    -
    - -
    -
    - -

    ◆ CAN_TDL2R_DATA1_Msk

    - -
    -
    - - - - -
    #define CAN_TDL2R_DATA1_Msk   (0xFFUL << CAN_TDL2R_DATA1_Pos)
    -
    -

    0x0000FF00

    - -
    -
    - -

    ◆ CAN_TDL2R_DATA1

    - -
    -
    - - - - -
    #define CAN_TDL2R_DATA1   CAN_TDL2R_DATA1_Msk
    -
    -

    Data byte 1

    - -
    -
    - -

    ◆ CAN_TDL2R_DATA2_Pos

    - -
    -
    - - - - -
    #define CAN_TDL2R_DATA2_Pos   (16U)
    -
    - -
    -
    - -

    ◆ CAN_TDL2R_DATA2_Msk

    - -
    -
    - - - - -
    #define CAN_TDL2R_DATA2_Msk   (0xFFUL << CAN_TDL2R_DATA2_Pos)
    -
    -

    0x00FF0000

    - -
    -
    - -

    ◆ CAN_TDL2R_DATA2

    - -
    -
    - - - - -
    #define CAN_TDL2R_DATA2   CAN_TDL2R_DATA2_Msk
    -
    -

    Data byte 2

    - -
    -
    - -

    ◆ CAN_TDL2R_DATA3_Pos

    - -
    -
    - - - - -
    #define CAN_TDL2R_DATA3_Pos   (24U)
    -
    - -
    -
    - -

    ◆ CAN_TDL2R_DATA3_Msk

    - -
    -
    - - - - -
    #define CAN_TDL2R_DATA3_Msk   (0xFFUL << CAN_TDL2R_DATA3_Pos)
    -
    -

    0xFF000000

    - -
    -
    - -

    ◆ CAN_TDL2R_DATA3

    - -
    -
    - - - - -
    #define CAN_TDL2R_DATA3   CAN_TDL2R_DATA3_Msk
    -
    -

    Data byte 3

    - -
    -
    - -

    ◆ CAN_TDH2R_DATA4_Pos

    - -
    -
    - - - - -
    #define CAN_TDH2R_DATA4_Pos   (0U)
    -
    - -
    -
    - -

    ◆ CAN_TDH2R_DATA4_Msk

    - -
    -
    - - - - -
    #define CAN_TDH2R_DATA4_Msk   (0xFFUL << CAN_TDH2R_DATA4_Pos)
    -
    -

    0x000000FF

    - -
    -
    - -

    ◆ CAN_TDH2R_DATA4

    - -
    -
    - - - - -
    #define CAN_TDH2R_DATA4   CAN_TDH2R_DATA4_Msk
    -
    -

    Data byte 4

    - -
    -
    - -

    ◆ CAN_TDH2R_DATA5_Pos

    - -
    -
    - - - - -
    #define CAN_TDH2R_DATA5_Pos   (8U)
    -
    - -
    -
    - -

    ◆ CAN_TDH2R_DATA5_Msk

    - -
    -
    - - - - -
    #define CAN_TDH2R_DATA5_Msk   (0xFFUL << CAN_TDH2R_DATA5_Pos)
    -
    -

    0x0000FF00

    - -
    -
    - -

    ◆ CAN_TDH2R_DATA5

    - -
    -
    - - - - -
    #define CAN_TDH2R_DATA5   CAN_TDH2R_DATA5_Msk
    -
    -

    Data byte 5

    - -
    -
    - -

    ◆ CAN_TDH2R_DATA6_Pos

    - -
    -
    - - - - -
    #define CAN_TDH2R_DATA6_Pos   (16U)
    -
    - -
    -
    - -

    ◆ CAN_TDH2R_DATA6_Msk

    - -
    -
    - - - - -
    #define CAN_TDH2R_DATA6_Msk   (0xFFUL << CAN_TDH2R_DATA6_Pos)
    -
    -

    0x00FF0000

    - -
    -
    - -

    ◆ CAN_TDH2R_DATA6

    - -
    -
    - - - - -
    #define CAN_TDH2R_DATA6   CAN_TDH2R_DATA6_Msk
    -
    -

    Data byte 6

    - -
    -
    - -

    ◆ CAN_TDH2R_DATA7_Pos

    - -
    -
    - - - - -
    #define CAN_TDH2R_DATA7_Pos   (24U)
    -
    - -
    -
    - -

    ◆ CAN_TDH2R_DATA7_Msk

    - -
    -
    - - - - -
    #define CAN_TDH2R_DATA7_Msk   (0xFFUL << CAN_TDH2R_DATA7_Pos)
    -
    -

    0xFF000000

    - -
    -
    - -

    ◆ CAN_TDH2R_DATA7

    - -
    -
    - - - - -
    #define CAN_TDH2R_DATA7   CAN_TDH2R_DATA7_Msk
    -
    -

    Data byte 7

    - -
    -
    - -

    ◆ CAN_RI0R_RTR_Pos

    - -
    -
    - - - - -
    #define CAN_RI0R_RTR_Pos   (1U)
    -
    - -
    -
    - -

    ◆ CAN_RI0R_RTR_Msk

    - -
    -
    - - - - -
    #define CAN_RI0R_RTR_Msk   (0x1UL << CAN_RI0R_RTR_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ CAN_RI0R_RTR

    - -
    -
    - - - - -
    #define CAN_RI0R_RTR   CAN_RI0R_RTR_Msk
    -
    -

    Remote Transmission Request

    - -
    -
    - -

    ◆ CAN_RI0R_IDE_Pos

    - -
    -
    - - - - -
    #define CAN_RI0R_IDE_Pos   (2U)
    -
    - -
    -
    - -

    ◆ CAN_RI0R_IDE_Msk

    - -
    -
    - - - - -
    #define CAN_RI0R_IDE_Msk   (0x1UL << CAN_RI0R_IDE_Pos)
    -
    -

    0x00000004

    - -
    -
    - -

    ◆ CAN_RI0R_IDE

    - -
    -
    - - - - -
    #define CAN_RI0R_IDE   CAN_RI0R_IDE_Msk
    -
    -

    Identifier Extension

    - -
    -
    - -

    ◆ CAN_RI0R_EXID_Pos

    - -
    -
    - - - - -
    #define CAN_RI0R_EXID_Pos   (3U)
    -
    - -
    -
    - -

    ◆ CAN_RI0R_EXID_Msk

    - -
    -
    - - - - -
    #define CAN_RI0R_EXID_Msk   (0x3FFFFUL << CAN_RI0R_EXID_Pos)
    -
    -

    0x001FFFF8

    - -
    -
    - -

    ◆ CAN_RI0R_EXID

    - -
    -
    - - - - -
    #define CAN_RI0R_EXID   CAN_RI0R_EXID_Msk
    -
    -

    Extended Identifier

    - -
    -
    - -

    ◆ CAN_RI0R_STID_Pos

    - -
    -
    - - - - -
    #define CAN_RI0R_STID_Pos   (21U)
    -
    - -
    -
    - -

    ◆ CAN_RI0R_STID_Msk

    - -
    -
    - - - - -
    #define CAN_RI0R_STID_Msk   (0x7FFUL << CAN_RI0R_STID_Pos)
    -
    -

    0xFFE00000

    - -
    -
    - -

    ◆ CAN_RI0R_STID

    - -
    -
    - - - - -
    #define CAN_RI0R_STID   CAN_RI0R_STID_Msk
    -
    -

    Standard Identifier or Extended Identifier

    - -
    -
    - -

    ◆ CAN_RDT0R_DLC_Pos

    - -
    -
    - - - - -
    #define CAN_RDT0R_DLC_Pos   (0U)
    -
    - -
    -
    - -

    ◆ CAN_RDT0R_DLC_Msk

    - -
    -
    - - - - -
    #define CAN_RDT0R_DLC_Msk   (0xFUL << CAN_RDT0R_DLC_Pos)
    -
    -

    0x0000000F

    - -
    -
    - -

    ◆ CAN_RDT0R_DLC

    - -
    -
    - - - - -
    #define CAN_RDT0R_DLC   CAN_RDT0R_DLC_Msk
    -
    -

    Data Length Code

    - -
    -
    - -

    ◆ CAN_RDT0R_FMI_Pos

    - -
    -
    - - - - -
    #define CAN_RDT0R_FMI_Pos   (8U)
    -
    - -
    -
    - -

    ◆ CAN_RDT0R_FMI_Msk

    - -
    -
    - - - - -
    #define CAN_RDT0R_FMI_Msk   (0xFFUL << CAN_RDT0R_FMI_Pos)
    -
    -

    0x0000FF00

    - -
    -
    - -

    ◆ CAN_RDT0R_FMI

    - -
    -
    - - - - -
    #define CAN_RDT0R_FMI   CAN_RDT0R_FMI_Msk
    -
    -

    Filter Match Index

    - -
    -
    - -

    ◆ CAN_RDT0R_TIME_Pos

    - -
    -
    - - - - -
    #define CAN_RDT0R_TIME_Pos   (16U)
    -
    - -
    -
    - -

    ◆ CAN_RDT0R_TIME_Msk

    - -
    -
    - - - - -
    #define CAN_RDT0R_TIME_Msk   (0xFFFFUL << CAN_RDT0R_TIME_Pos)
    -
    -

    0xFFFF0000

    - -
    -
    - -

    ◆ CAN_RDT0R_TIME

    - -
    -
    - - - - -
    #define CAN_RDT0R_TIME   CAN_RDT0R_TIME_Msk
    -
    -

    Message Time Stamp

    - -
    -
    - -

    ◆ CAN_RDL0R_DATA0_Pos

    - -
    -
    - - - - -
    #define CAN_RDL0R_DATA0_Pos   (0U)
    -
    - -
    -
    - -

    ◆ CAN_RDL0R_DATA0_Msk

    - -
    -
    - - - - -
    #define CAN_RDL0R_DATA0_Msk   (0xFFUL << CAN_RDL0R_DATA0_Pos)
    -
    -

    0x000000FF

    - -
    -
    - -

    ◆ CAN_RDL0R_DATA0

    - -
    -
    - - - - -
    #define CAN_RDL0R_DATA0   CAN_RDL0R_DATA0_Msk
    -
    -

    Data byte 0

    - -
    -
    - -

    ◆ CAN_RDL0R_DATA1_Pos

    - -
    -
    - - - - -
    #define CAN_RDL0R_DATA1_Pos   (8U)
    -
    - -
    -
    - -

    ◆ CAN_RDL0R_DATA1_Msk

    - -
    -
    - - - - -
    #define CAN_RDL0R_DATA1_Msk   (0xFFUL << CAN_RDL0R_DATA1_Pos)
    -
    -

    0x0000FF00

    - -
    -
    - -

    ◆ CAN_RDL0R_DATA1

    - -
    -
    - - - - -
    #define CAN_RDL0R_DATA1   CAN_RDL0R_DATA1_Msk
    -
    -

    Data byte 1

    - -
    -
    - -

    ◆ CAN_RDL0R_DATA2_Pos

    - -
    -
    - - - - -
    #define CAN_RDL0R_DATA2_Pos   (16U)
    -
    - -
    -
    - -

    ◆ CAN_RDL0R_DATA2_Msk

    - -
    -
    - - - - -
    #define CAN_RDL0R_DATA2_Msk   (0xFFUL << CAN_RDL0R_DATA2_Pos)
    -
    -

    0x00FF0000

    - -
    -
    - -

    ◆ CAN_RDL0R_DATA2

    - -
    -
    - - - - -
    #define CAN_RDL0R_DATA2   CAN_RDL0R_DATA2_Msk
    -
    -

    Data byte 2

    - -
    -
    - -

    ◆ CAN_RDL0R_DATA3_Pos

    - -
    -
    - - - - -
    #define CAN_RDL0R_DATA3_Pos   (24U)
    -
    - -
    -
    - -

    ◆ CAN_RDL0R_DATA3_Msk

    - -
    -
    - - - - -
    #define CAN_RDL0R_DATA3_Msk   (0xFFUL << CAN_RDL0R_DATA3_Pos)
    -
    -

    0xFF000000

    - -
    -
    - -

    ◆ CAN_RDL0R_DATA3

    - -
    -
    - - - - -
    #define CAN_RDL0R_DATA3   CAN_RDL0R_DATA3_Msk
    -
    -

    Data byte 3

    - -
    -
    - -

    ◆ CAN_RDH0R_DATA4_Pos

    - -
    -
    - - - - -
    #define CAN_RDH0R_DATA4_Pos   (0U)
    -
    - -
    -
    - -

    ◆ CAN_RDH0R_DATA4_Msk

    - -
    -
    - - - - -
    #define CAN_RDH0R_DATA4_Msk   (0xFFUL << CAN_RDH0R_DATA4_Pos)
    -
    -

    0x000000FF

    - -
    -
    - -

    ◆ CAN_RDH0R_DATA4

    - -
    -
    - - - - -
    #define CAN_RDH0R_DATA4   CAN_RDH0R_DATA4_Msk
    -
    -

    Data byte 4

    - -
    -
    - -

    ◆ CAN_RDH0R_DATA5_Pos

    - -
    -
    - - - - -
    #define CAN_RDH0R_DATA5_Pos   (8U)
    -
    - -
    -
    - -

    ◆ CAN_RDH0R_DATA5_Msk

    - -
    -
    - - - - -
    #define CAN_RDH0R_DATA5_Msk   (0xFFUL << CAN_RDH0R_DATA5_Pos)
    -
    -

    0x0000FF00

    - -
    -
    - -

    ◆ CAN_RDH0R_DATA5

    - -
    -
    - - - - -
    #define CAN_RDH0R_DATA5   CAN_RDH0R_DATA5_Msk
    -
    -

    Data byte 5

    - -
    -
    - -

    ◆ CAN_RDH0R_DATA6_Pos

    - -
    -
    - - - - -
    #define CAN_RDH0R_DATA6_Pos   (16U)
    -
    - -
    -
    - -

    ◆ CAN_RDH0R_DATA6_Msk

    - -
    -
    - - - - -
    #define CAN_RDH0R_DATA6_Msk   (0xFFUL << CAN_RDH0R_DATA6_Pos)
    -
    -

    0x00FF0000

    - -
    -
    - -

    ◆ CAN_RDH0R_DATA6

    - -
    -
    - - - - -
    #define CAN_RDH0R_DATA6   CAN_RDH0R_DATA6_Msk
    -
    -

    Data byte 6

    - -
    -
    - -

    ◆ CAN_RDH0R_DATA7_Pos

    - -
    -
    - - - - -
    #define CAN_RDH0R_DATA7_Pos   (24U)
    -
    - -
    -
    - -

    ◆ CAN_RDH0R_DATA7_Msk

    - -
    -
    - - - - -
    #define CAN_RDH0R_DATA7_Msk   (0xFFUL << CAN_RDH0R_DATA7_Pos)
    -
    -

    0xFF000000

    - -
    -
    - -

    ◆ CAN_RDH0R_DATA7

    - -
    -
    - - - - -
    #define CAN_RDH0R_DATA7   CAN_RDH0R_DATA7_Msk
    -
    -

    Data byte 7

    - -
    -
    - -

    ◆ CAN_RI1R_RTR_Pos

    - -
    -
    - - - - -
    #define CAN_RI1R_RTR_Pos   (1U)
    -
    - -
    -
    - -

    ◆ CAN_RI1R_RTR_Msk

    - -
    -
    - - - - -
    #define CAN_RI1R_RTR_Msk   (0x1UL << CAN_RI1R_RTR_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ CAN_RI1R_RTR

    - -
    -
    - - - - -
    #define CAN_RI1R_RTR   CAN_RI1R_RTR_Msk
    -
    -

    Remote Transmission Request

    - -
    -
    - -

    ◆ CAN_RI1R_IDE_Pos

    - -
    -
    - - - - -
    #define CAN_RI1R_IDE_Pos   (2U)
    -
    - -
    -
    - -

    ◆ CAN_RI1R_IDE_Msk

    - -
    -
    - - - - -
    #define CAN_RI1R_IDE_Msk   (0x1UL << CAN_RI1R_IDE_Pos)
    -
    -

    0x00000004

    - -
    -
    - -

    ◆ CAN_RI1R_IDE

    - -
    -
    - - - - -
    #define CAN_RI1R_IDE   CAN_RI1R_IDE_Msk
    -
    -

    Identifier Extension

    - -
    -
    - -

    ◆ CAN_RI1R_EXID_Pos

    - -
    -
    - - - - -
    #define CAN_RI1R_EXID_Pos   (3U)
    -
    - -
    -
    - -

    ◆ CAN_RI1R_EXID_Msk

    - -
    -
    - - - - -
    #define CAN_RI1R_EXID_Msk   (0x3FFFFUL << CAN_RI1R_EXID_Pos)
    -
    -

    0x001FFFF8

    - -
    -
    - -

    ◆ CAN_RI1R_EXID

    - -
    -
    - - - - -
    #define CAN_RI1R_EXID   CAN_RI1R_EXID_Msk
    -
    -

    Extended identifier

    - -
    -
    - -

    ◆ CAN_RI1R_STID_Pos

    - -
    -
    - - - - -
    #define CAN_RI1R_STID_Pos   (21U)
    -
    - -
    -
    - -

    ◆ CAN_RI1R_STID_Msk

    - -
    -
    - - - - -
    #define CAN_RI1R_STID_Msk   (0x7FFUL << CAN_RI1R_STID_Pos)
    -
    -

    0xFFE00000

    - -
    -
    - -

    ◆ CAN_RI1R_STID

    - -
    -
    - - - - -
    #define CAN_RI1R_STID   CAN_RI1R_STID_Msk
    -
    -

    Standard Identifier or Extended Identifier

    - -
    -
    - -

    ◆ CAN_RDT1R_DLC_Pos

    - -
    -
    - - - - -
    #define CAN_RDT1R_DLC_Pos   (0U)
    -
    - -
    -
    - -

    ◆ CAN_RDT1R_DLC_Msk

    - -
    -
    - - - - -
    #define CAN_RDT1R_DLC_Msk   (0xFUL << CAN_RDT1R_DLC_Pos)
    -
    -

    0x0000000F

    - -
    -
    - -

    ◆ CAN_RDT1R_DLC

    - -
    -
    - - - - -
    #define CAN_RDT1R_DLC   CAN_RDT1R_DLC_Msk
    -
    -

    Data Length Code

    - -
    -
    - -

    ◆ CAN_RDT1R_FMI_Pos

    - -
    -
    - - - - -
    #define CAN_RDT1R_FMI_Pos   (8U)
    -
    - -
    -
    - -

    ◆ CAN_RDT1R_FMI_Msk

    - -
    -
    - - - - -
    #define CAN_RDT1R_FMI_Msk   (0xFFUL << CAN_RDT1R_FMI_Pos)
    -
    -

    0x0000FF00

    - -
    -
    - -

    ◆ CAN_RDT1R_FMI

    - -
    -
    - - - - -
    #define CAN_RDT1R_FMI   CAN_RDT1R_FMI_Msk
    -
    -

    Filter Match Index

    - -
    -
    - -

    ◆ CAN_RDT1R_TIME_Pos

    - -
    -
    - - - - -
    #define CAN_RDT1R_TIME_Pos   (16U)
    -
    - -
    -
    - -

    ◆ CAN_RDT1R_TIME_Msk

    - -
    -
    - - - - -
    #define CAN_RDT1R_TIME_Msk   (0xFFFFUL << CAN_RDT1R_TIME_Pos)
    -
    -

    0xFFFF0000

    - -
    -
    - -

    ◆ CAN_RDT1R_TIME

    - -
    -
    - - - - -
    #define CAN_RDT1R_TIME   CAN_RDT1R_TIME_Msk
    -
    -

    Message Time Stamp

    - -
    -
    - -

    ◆ CAN_RDL1R_DATA0_Pos

    - -
    -
    - - - - -
    #define CAN_RDL1R_DATA0_Pos   (0U)
    -
    - -
    -
    - -

    ◆ CAN_RDL1R_DATA0_Msk

    - -
    -
    - - - - -
    #define CAN_RDL1R_DATA0_Msk   (0xFFUL << CAN_RDL1R_DATA0_Pos)
    -
    -

    0x000000FF

    - -
    -
    - -

    ◆ CAN_RDL1R_DATA0

    - -
    -
    - - - - -
    #define CAN_RDL1R_DATA0   CAN_RDL1R_DATA0_Msk
    -
    -

    Data byte 0

    - -
    -
    - -

    ◆ CAN_RDL1R_DATA1_Pos

    - -
    -
    - - - - -
    #define CAN_RDL1R_DATA1_Pos   (8U)
    -
    - -
    -
    - -

    ◆ CAN_RDL1R_DATA1_Msk

    - -
    -
    - - - - -
    #define CAN_RDL1R_DATA1_Msk   (0xFFUL << CAN_RDL1R_DATA1_Pos)
    -
    -

    0x0000FF00

    - -
    -
    - -

    ◆ CAN_RDL1R_DATA1

    - -
    -
    - - - - -
    #define CAN_RDL1R_DATA1   CAN_RDL1R_DATA1_Msk
    -
    -

    Data byte 1

    - -
    -
    - -

    ◆ CAN_RDL1R_DATA2_Pos

    - -
    -
    - - - - -
    #define CAN_RDL1R_DATA2_Pos   (16U)
    -
    - -
    -
    - -

    ◆ CAN_RDL1R_DATA2_Msk

    - -
    -
    - - - - -
    #define CAN_RDL1R_DATA2_Msk   (0xFFUL << CAN_RDL1R_DATA2_Pos)
    -
    -

    0x00FF0000

    - -
    -
    - -

    ◆ CAN_RDL1R_DATA2

    - -
    -
    - - - - -
    #define CAN_RDL1R_DATA2   CAN_RDL1R_DATA2_Msk
    -
    -

    Data byte 2

    - -
    -
    - -

    ◆ CAN_RDL1R_DATA3_Pos

    - -
    -
    - - - - -
    #define CAN_RDL1R_DATA3_Pos   (24U)
    -
    - -
    -
    - -

    ◆ CAN_RDL1R_DATA3_Msk

    - -
    -
    - - - - -
    #define CAN_RDL1R_DATA3_Msk   (0xFFUL << CAN_RDL1R_DATA3_Pos)
    -
    -

    0xFF000000

    - -
    -
    - -

    ◆ CAN_RDL1R_DATA3

    - -
    -
    - - - - -
    #define CAN_RDL1R_DATA3   CAN_RDL1R_DATA3_Msk
    -
    -

    Data byte 3

    - -
    -
    - -

    ◆ CAN_RDH1R_DATA4_Pos

    - -
    -
    - - - - -
    #define CAN_RDH1R_DATA4_Pos   (0U)
    -
    - -
    -
    - -

    ◆ CAN_RDH1R_DATA4_Msk

    - -
    -
    - - - - -
    #define CAN_RDH1R_DATA4_Msk   (0xFFUL << CAN_RDH1R_DATA4_Pos)
    -
    -

    0x000000FF

    - -
    -
    - -

    ◆ CAN_RDH1R_DATA4

    - -
    -
    - - - - -
    #define CAN_RDH1R_DATA4   CAN_RDH1R_DATA4_Msk
    -
    -

    Data byte 4

    - -
    -
    - -

    ◆ CAN_RDH1R_DATA5_Pos

    - -
    -
    - - - - -
    #define CAN_RDH1R_DATA5_Pos   (8U)
    -
    - -
    -
    - -

    ◆ CAN_RDH1R_DATA5_Msk

    - -
    -
    - - - - -
    #define CAN_RDH1R_DATA5_Msk   (0xFFUL << CAN_RDH1R_DATA5_Pos)
    -
    -

    0x0000FF00

    - -
    -
    - -

    ◆ CAN_RDH1R_DATA5

    - -
    -
    - - - - -
    #define CAN_RDH1R_DATA5   CAN_RDH1R_DATA5_Msk
    -
    -

    Data byte 5

    - -
    -
    - -

    ◆ CAN_RDH1R_DATA6_Pos

    - -
    -
    - - - - -
    #define CAN_RDH1R_DATA6_Pos   (16U)
    -
    - -
    -
    - -

    ◆ CAN_RDH1R_DATA6_Msk

    - -
    -
    - - - - -
    #define CAN_RDH1R_DATA6_Msk   (0xFFUL << CAN_RDH1R_DATA6_Pos)
    -
    -

    0x00FF0000

    - -
    -
    - -

    ◆ CAN_RDH1R_DATA6

    - -
    -
    - - - - -
    #define CAN_RDH1R_DATA6   CAN_RDH1R_DATA6_Msk
    -
    -

    Data byte 6

    - -
    -
    - -

    ◆ CAN_RDH1R_DATA7_Pos

    - -
    -
    - - - - -
    #define CAN_RDH1R_DATA7_Pos   (24U)
    -
    - -
    -
    - -

    ◆ CAN_RDH1R_DATA7_Msk

    - -
    -
    - - - - -
    #define CAN_RDH1R_DATA7_Msk   (0xFFUL << CAN_RDH1R_DATA7_Pos)
    -
    -

    0xFF000000

    - -
    -
    - -

    ◆ CAN_RDH1R_DATA7

    - -
    -
    - - - - -
    #define CAN_RDH1R_DATA7   CAN_RDH1R_DATA7_Msk
    -
    -

    Data byte 7 CAN filter registers

    - -
    -
    - -

    ◆ CAN_FMR_FINIT_Pos

    - -
    -
    - - - - -
    #define CAN_FMR_FINIT_Pos   (0U)
    -
    - -
    -
    - -

    ◆ CAN_FMR_FINIT_Msk

    - -
    -
    - - - - -
    #define CAN_FMR_FINIT_Msk   (0x1UL << CAN_FMR_FINIT_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ CAN_FMR_FINIT

    - -
    -
    - - - - -
    #define CAN_FMR_FINIT   CAN_FMR_FINIT_Msk
    -
    -

    Filter Init Mode

    - -
    -
    - -

    ◆ CAN_FMR_CAN2SB_Pos

    - -
    -
    - - - - -
    #define CAN_FMR_CAN2SB_Pos   (8U)
    -
    - -
    -
    - -

    ◆ CAN_FMR_CAN2SB_Msk

    - -
    -
    - - - - -
    #define CAN_FMR_CAN2SB_Msk   (0x3FUL << CAN_FMR_CAN2SB_Pos)
    -
    -

    0x00003F00

    - -
    -
    - -

    ◆ CAN_FMR_CAN2SB

    - -
    -
    - - - - -
    #define CAN_FMR_CAN2SB   CAN_FMR_CAN2SB_Msk
    -
    -

    CAN2 start bank

    - -
    -
    - -

    ◆ CAN_FM1R_FBM_Pos

    - -
    -
    - - - - -
    #define CAN_FM1R_FBM_Pos   (0U)
    -
    - -
    -
    - -

    ◆ CAN_FM1R_FBM_Msk

    - -
    -
    - - - - -
    #define CAN_FM1R_FBM_Msk   (0xFFFFFFFUL << CAN_FM1R_FBM_Pos)
    -
    -

    0x0FFFFFFF

    - -
    -
    - -

    ◆ CAN_FM1R_FBM

    - -
    -
    - - - - -
    #define CAN_FM1R_FBM   CAN_FM1R_FBM_Msk
    -
    -

    Filter Mode

    - -
    -
    - -

    ◆ CAN_FM1R_FBM0_Pos

    - -
    -
    - - - - -
    #define CAN_FM1R_FBM0_Pos   (0U)
    -
    - -
    -
    - -

    ◆ CAN_FM1R_FBM0_Msk

    - -
    -
    - - - - -
    #define CAN_FM1R_FBM0_Msk   (0x1UL << CAN_FM1R_FBM0_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ CAN_FM1R_FBM0

    - -
    -
    - - - - -
    #define CAN_FM1R_FBM0   CAN_FM1R_FBM0_Msk
    -
    -

    Filter Init Mode bit 0

    - -
    -
    - -

    ◆ CAN_FM1R_FBM1_Pos

    - -
    -
    - - - - -
    #define CAN_FM1R_FBM1_Pos   (1U)
    -
    - -
    -
    - -

    ◆ CAN_FM1R_FBM1_Msk

    - -
    -
    - - - - -
    #define CAN_FM1R_FBM1_Msk   (0x1UL << CAN_FM1R_FBM1_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ CAN_FM1R_FBM1

    - -
    -
    - - - - -
    #define CAN_FM1R_FBM1   CAN_FM1R_FBM1_Msk
    -
    -

    Filter Init Mode bit 1

    - -
    -
    - -

    ◆ CAN_FM1R_FBM2_Pos

    - -
    -
    - - - - -
    #define CAN_FM1R_FBM2_Pos   (2U)
    -
    - -
    -
    - -

    ◆ CAN_FM1R_FBM2_Msk

    - -
    -
    - - - - -
    #define CAN_FM1R_FBM2_Msk   (0x1UL << CAN_FM1R_FBM2_Pos)
    -
    -

    0x00000004

    - -
    -
    - -

    ◆ CAN_FM1R_FBM2

    - -
    -
    - - - - -
    #define CAN_FM1R_FBM2   CAN_FM1R_FBM2_Msk
    -
    -

    Filter Init Mode bit 2

    - -
    -
    - -

    ◆ CAN_FM1R_FBM3_Pos

    - -
    -
    - - - - -
    #define CAN_FM1R_FBM3_Pos   (3U)
    -
    - -
    -
    - -

    ◆ CAN_FM1R_FBM3_Msk

    - -
    -
    - - - - -
    #define CAN_FM1R_FBM3_Msk   (0x1UL << CAN_FM1R_FBM3_Pos)
    -
    -

    0x00000008

    - -
    -
    - -

    ◆ CAN_FM1R_FBM3

    - -
    -
    - - - - -
    #define CAN_FM1R_FBM3   CAN_FM1R_FBM3_Msk
    -
    -

    Filter Init Mode bit 3

    - -
    -
    - -

    ◆ CAN_FM1R_FBM4_Pos

    - -
    -
    - - - - -
    #define CAN_FM1R_FBM4_Pos   (4U)
    -
    - -
    -
    - -

    ◆ CAN_FM1R_FBM4_Msk

    - -
    -
    - - - - -
    #define CAN_FM1R_FBM4_Msk   (0x1UL << CAN_FM1R_FBM4_Pos)
    -
    -

    0x00000010

    - -
    -
    - -

    ◆ CAN_FM1R_FBM4

    - -
    -
    - - - - -
    #define CAN_FM1R_FBM4   CAN_FM1R_FBM4_Msk
    -
    -

    Filter Init Mode bit 4

    - -
    -
    - -

    ◆ CAN_FM1R_FBM5_Pos

    - -
    -
    - - - - -
    #define CAN_FM1R_FBM5_Pos   (5U)
    -
    - -
    -
    - -

    ◆ CAN_FM1R_FBM5_Msk

    - -
    -
    - - - - -
    #define CAN_FM1R_FBM5_Msk   (0x1UL << CAN_FM1R_FBM5_Pos)
    -
    -

    0x00000020

    - -
    -
    - -

    ◆ CAN_FM1R_FBM5

    - -
    -
    - - - - -
    #define CAN_FM1R_FBM5   CAN_FM1R_FBM5_Msk
    -
    -

    Filter Init Mode bit 5

    - -
    -
    - -

    ◆ CAN_FM1R_FBM6_Pos

    - -
    -
    - - - - -
    #define CAN_FM1R_FBM6_Pos   (6U)
    -
    - -
    -
    - -

    ◆ CAN_FM1R_FBM6_Msk

    - -
    -
    - - - - -
    #define CAN_FM1R_FBM6_Msk   (0x1UL << CAN_FM1R_FBM6_Pos)
    -
    -

    0x00000040

    - -
    -
    - -

    ◆ CAN_FM1R_FBM6

    - -
    -
    - - - - -
    #define CAN_FM1R_FBM6   CAN_FM1R_FBM6_Msk
    -
    -

    Filter Init Mode bit 6

    - -
    -
    - -

    ◆ CAN_FM1R_FBM7_Pos

    - -
    -
    - - - - -
    #define CAN_FM1R_FBM7_Pos   (7U)
    -
    - -
    -
    - -

    ◆ CAN_FM1R_FBM7_Msk

    - -
    -
    - - - - -
    #define CAN_FM1R_FBM7_Msk   (0x1UL << CAN_FM1R_FBM7_Pos)
    -
    -

    0x00000080

    - -
    -
    - -

    ◆ CAN_FM1R_FBM7

    - -
    -
    - - - - -
    #define CAN_FM1R_FBM7   CAN_FM1R_FBM7_Msk
    -
    -

    Filter Init Mode bit 7

    - -
    -
    - -

    ◆ CAN_FM1R_FBM8_Pos

    - -
    -
    - - - - -
    #define CAN_FM1R_FBM8_Pos   (8U)
    -
    - -
    -
    - -

    ◆ CAN_FM1R_FBM8_Msk

    - -
    -
    - - - - -
    #define CAN_FM1R_FBM8_Msk   (0x1UL << CAN_FM1R_FBM8_Pos)
    -
    -

    0x00000100

    - -
    -
    - -

    ◆ CAN_FM1R_FBM8

    - -
    -
    - - - - -
    #define CAN_FM1R_FBM8   CAN_FM1R_FBM8_Msk
    -
    -

    Filter Init Mode bit 8

    - -
    -
    - -

    ◆ CAN_FM1R_FBM9_Pos

    - -
    -
    - - - - -
    #define CAN_FM1R_FBM9_Pos   (9U)
    -
    - -
    -
    - -

    ◆ CAN_FM1R_FBM9_Msk

    - -
    -
    - - - - -
    #define CAN_FM1R_FBM9_Msk   (0x1UL << CAN_FM1R_FBM9_Pos)
    -
    -

    0x00000200

    - -
    -
    - -

    ◆ CAN_FM1R_FBM9

    - -
    -
    - - - - -
    #define CAN_FM1R_FBM9   CAN_FM1R_FBM9_Msk
    -
    -

    Filter Init Mode bit 9

    - -
    -
    - -

    ◆ CAN_FM1R_FBM10_Pos

    - -
    -
    - - - - -
    #define CAN_FM1R_FBM10_Pos   (10U)
    -
    - -
    -
    - -

    ◆ CAN_FM1R_FBM10_Msk

    - -
    -
    - - - - -
    #define CAN_FM1R_FBM10_Msk   (0x1UL << CAN_FM1R_FBM10_Pos)
    -
    -

    0x00000400

    - -
    -
    - -

    ◆ CAN_FM1R_FBM10

    - -
    -
    - - - - -
    #define CAN_FM1R_FBM10   CAN_FM1R_FBM10_Msk
    -
    -

    Filter Init Mode bit 10

    - -
    -
    - -

    ◆ CAN_FM1R_FBM11_Pos

    - -
    -
    - - - - -
    #define CAN_FM1R_FBM11_Pos   (11U)
    -
    - -
    -
    - -

    ◆ CAN_FM1R_FBM11_Msk

    - -
    -
    - - - - -
    #define CAN_FM1R_FBM11_Msk   (0x1UL << CAN_FM1R_FBM11_Pos)
    -
    -

    0x00000800

    - -
    -
    - -

    ◆ CAN_FM1R_FBM11

    - -
    -
    - - - - -
    #define CAN_FM1R_FBM11   CAN_FM1R_FBM11_Msk
    -
    -

    Filter Init Mode bit 11

    - -
    -
    - -

    ◆ CAN_FM1R_FBM12_Pos

    - -
    -
    - - - - -
    #define CAN_FM1R_FBM12_Pos   (12U)
    -
    - -
    -
    - -

    ◆ CAN_FM1R_FBM12_Msk

    - -
    -
    - - - - -
    #define CAN_FM1R_FBM12_Msk   (0x1UL << CAN_FM1R_FBM12_Pos)
    -
    -

    0x00001000

    - -
    -
    - -

    ◆ CAN_FM1R_FBM12

    - -
    -
    - - - - -
    #define CAN_FM1R_FBM12   CAN_FM1R_FBM12_Msk
    -
    -

    Filter Init Mode bit 12

    - -
    -
    - -

    ◆ CAN_FM1R_FBM13_Pos

    - -
    -
    - - - - -
    #define CAN_FM1R_FBM13_Pos   (13U)
    -
    - -
    -
    - -

    ◆ CAN_FM1R_FBM13_Msk

    - -
    -
    - - - - -
    #define CAN_FM1R_FBM13_Msk   (0x1UL << CAN_FM1R_FBM13_Pos)
    -
    -

    0x00002000

    - -
    -
    - -

    ◆ CAN_FM1R_FBM13

    - -
    -
    - - - - -
    #define CAN_FM1R_FBM13   CAN_FM1R_FBM13_Msk
    -
    -

    Filter Init Mode bit 13

    - -
    -
    - -

    ◆ CAN_FM1R_FBM14_Pos

    - -
    -
    - - - - -
    #define CAN_FM1R_FBM14_Pos   (14U)
    -
    - -
    -
    - -

    ◆ CAN_FM1R_FBM14_Msk

    - -
    -
    - - - - -
    #define CAN_FM1R_FBM14_Msk   (0x1UL << CAN_FM1R_FBM14_Pos)
    -
    -

    0x00004000

    - -
    -
    - -

    ◆ CAN_FM1R_FBM14

    - -
    -
    - - - - -
    #define CAN_FM1R_FBM14   CAN_FM1R_FBM14_Msk
    -
    -

    Filter Init Mode bit 14

    - -
    -
    - -

    ◆ CAN_FM1R_FBM15_Pos

    - -
    -
    - - - - -
    #define CAN_FM1R_FBM15_Pos   (15U)
    -
    - -
    -
    - -

    ◆ CAN_FM1R_FBM15_Msk

    - -
    -
    - - - - -
    #define CAN_FM1R_FBM15_Msk   (0x1UL << CAN_FM1R_FBM15_Pos)
    -
    -

    0x00008000

    - -
    -
    - -

    ◆ CAN_FM1R_FBM15

    - -
    -
    - - - - -
    #define CAN_FM1R_FBM15   CAN_FM1R_FBM15_Msk
    -
    -

    Filter Init Mode bit 15

    - -
    -
    - -

    ◆ CAN_FM1R_FBM16_Pos

    - -
    -
    - - - - -
    #define CAN_FM1R_FBM16_Pos   (16U)
    -
    - -
    -
    - -

    ◆ CAN_FM1R_FBM16_Msk

    - -
    -
    - - - - -
    #define CAN_FM1R_FBM16_Msk   (0x1UL << CAN_FM1R_FBM16_Pos)
    -
    -

    0x00010000

    - -
    -
    - -

    ◆ CAN_FM1R_FBM16

    - -
    -
    - - - - -
    #define CAN_FM1R_FBM16   CAN_FM1R_FBM16_Msk
    -
    -

    Filter Init Mode bit 16

    - -
    -
    - -

    ◆ CAN_FM1R_FBM17_Pos

    - -
    -
    - - - - -
    #define CAN_FM1R_FBM17_Pos   (17U)
    -
    - -
    -
    - -

    ◆ CAN_FM1R_FBM17_Msk

    - -
    -
    - - - - -
    #define CAN_FM1R_FBM17_Msk   (0x1UL << CAN_FM1R_FBM17_Pos)
    -
    -

    0x00020000

    - -
    -
    - -

    ◆ CAN_FM1R_FBM17

    - -
    -
    - - - - -
    #define CAN_FM1R_FBM17   CAN_FM1R_FBM17_Msk
    -
    -

    Filter Init Mode bit 17

    - -
    -
    - -

    ◆ CAN_FM1R_FBM18_Pos

    - -
    -
    - - - - -
    #define CAN_FM1R_FBM18_Pos   (18U)
    -
    - -
    -
    - -

    ◆ CAN_FM1R_FBM18_Msk

    - -
    -
    - - - - -
    #define CAN_FM1R_FBM18_Msk   (0x1UL << CAN_FM1R_FBM18_Pos)
    -
    -

    0x00040000

    - -
    -
    - -

    ◆ CAN_FM1R_FBM18

    - -
    -
    - - - - -
    #define CAN_FM1R_FBM18   CAN_FM1R_FBM18_Msk
    -
    -

    Filter Init Mode bit 18

    - -
    -
    - -

    ◆ CAN_FM1R_FBM19_Pos

    - -
    -
    - - - - -
    #define CAN_FM1R_FBM19_Pos   (19U)
    -
    - -
    -
    - -

    ◆ CAN_FM1R_FBM19_Msk

    - -
    -
    - - - - -
    #define CAN_FM1R_FBM19_Msk   (0x1UL << CAN_FM1R_FBM19_Pos)
    -
    -

    0x00080000

    - -
    -
    - -

    ◆ CAN_FM1R_FBM19

    - -
    -
    - - - - -
    #define CAN_FM1R_FBM19   CAN_FM1R_FBM19_Msk
    -
    -

    Filter Init Mode bit 19

    - -
    -
    - -

    ◆ CAN_FM1R_FBM20_Pos

    - -
    -
    - - - - -
    #define CAN_FM1R_FBM20_Pos   (20U)
    -
    - -
    -
    - -

    ◆ CAN_FM1R_FBM20_Msk

    - -
    -
    - - - - -
    #define CAN_FM1R_FBM20_Msk   (0x1UL << CAN_FM1R_FBM20_Pos)
    -
    -

    0x00100000

    - -
    -
    - -

    ◆ CAN_FM1R_FBM20

    - -
    -
    - - - - -
    #define CAN_FM1R_FBM20   CAN_FM1R_FBM20_Msk
    -
    -

    Filter Init Mode bit 20

    - -
    -
    - -

    ◆ CAN_FM1R_FBM21_Pos

    - -
    -
    - - - - -
    #define CAN_FM1R_FBM21_Pos   (21U)
    -
    - -
    -
    - -

    ◆ CAN_FM1R_FBM21_Msk

    - -
    -
    - - - - -
    #define CAN_FM1R_FBM21_Msk   (0x1UL << CAN_FM1R_FBM21_Pos)
    -
    -

    0x00200000

    - -
    -
    - -

    ◆ CAN_FM1R_FBM21

    - -
    -
    - - - - -
    #define CAN_FM1R_FBM21   CAN_FM1R_FBM21_Msk
    -
    -

    Filter Init Mode bit 21

    - -
    -
    - -

    ◆ CAN_FM1R_FBM22_Pos

    - -
    -
    - - - - -
    #define CAN_FM1R_FBM22_Pos   (22U)
    -
    - -
    -
    - -

    ◆ CAN_FM1R_FBM22_Msk

    - -
    -
    - - - - -
    #define CAN_FM1R_FBM22_Msk   (0x1UL << CAN_FM1R_FBM22_Pos)
    -
    -

    0x00400000

    - -
    -
    - -

    ◆ CAN_FM1R_FBM22

    - -
    -
    - - - - -
    #define CAN_FM1R_FBM22   CAN_FM1R_FBM22_Msk
    -
    -

    Filter Init Mode bit 22

    - -
    -
    - -

    ◆ CAN_FM1R_FBM23_Pos

    - -
    -
    - - - - -
    #define CAN_FM1R_FBM23_Pos   (23U)
    -
    - -
    -
    - -

    ◆ CAN_FM1R_FBM23_Msk

    - -
    -
    - - - - -
    #define CAN_FM1R_FBM23_Msk   (0x1UL << CAN_FM1R_FBM23_Pos)
    -
    -

    0x00800000

    - -
    -
    - -

    ◆ CAN_FM1R_FBM23

    - -
    -
    - - - - -
    #define CAN_FM1R_FBM23   CAN_FM1R_FBM23_Msk
    -
    -

    Filter Init Mode bit 23

    - -
    -
    - -

    ◆ CAN_FM1R_FBM24_Pos

    - -
    -
    - - - - -
    #define CAN_FM1R_FBM24_Pos   (24U)
    -
    - -
    -
    - -

    ◆ CAN_FM1R_FBM24_Msk

    - -
    -
    - - - - -
    #define CAN_FM1R_FBM24_Msk   (0x1UL << CAN_FM1R_FBM24_Pos)
    -
    -

    0x01000000

    - -
    -
    - -

    ◆ CAN_FM1R_FBM24

    - -
    -
    - - - - -
    #define CAN_FM1R_FBM24   CAN_FM1R_FBM24_Msk
    -
    -

    Filter Init Mode bit 24

    - -
    -
    - -

    ◆ CAN_FM1R_FBM25_Pos

    - -
    -
    - - - - -
    #define CAN_FM1R_FBM25_Pos   (25U)
    -
    - -
    -
    - -

    ◆ CAN_FM1R_FBM25_Msk

    - -
    -
    - - - - -
    #define CAN_FM1R_FBM25_Msk   (0x1UL << CAN_FM1R_FBM25_Pos)
    -
    -

    0x02000000

    - -
    -
    - -

    ◆ CAN_FM1R_FBM25

    - -
    -
    - - - - -
    #define CAN_FM1R_FBM25   CAN_FM1R_FBM25_Msk
    -
    -

    Filter Init Mode bit 25

    - -
    -
    - -

    ◆ CAN_FM1R_FBM26_Pos

    - -
    -
    - - - - -
    #define CAN_FM1R_FBM26_Pos   (26U)
    -
    - -
    -
    - -

    ◆ CAN_FM1R_FBM26_Msk

    - -
    -
    - - - - -
    #define CAN_FM1R_FBM26_Msk   (0x1UL << CAN_FM1R_FBM26_Pos)
    -
    -

    0x04000000

    - -
    -
    - -

    ◆ CAN_FM1R_FBM26

    - -
    -
    - - - - -
    #define CAN_FM1R_FBM26   CAN_FM1R_FBM26_Msk
    -
    -

    Filter Init Mode bit 26

    - -
    -
    - -

    ◆ CAN_FM1R_FBM27_Pos

    - -
    -
    - - - - -
    #define CAN_FM1R_FBM27_Pos   (27U)
    -
    - -
    -
    - -

    ◆ CAN_FM1R_FBM27_Msk

    - -
    -
    - - - - -
    #define CAN_FM1R_FBM27_Msk   (0x1UL << CAN_FM1R_FBM27_Pos)
    -
    -

    0x08000000

    - -
    -
    - -

    ◆ CAN_FM1R_FBM27

    - -
    -
    - - - - -
    #define CAN_FM1R_FBM27   CAN_FM1R_FBM27_Msk
    -
    -

    Filter Init Mode bit 27

    - -
    -
    - -

    ◆ CAN_FS1R_FSC_Pos

    - -
    -
    - - - - -
    #define CAN_FS1R_FSC_Pos   (0U)
    -
    - -
    -
    - -

    ◆ CAN_FS1R_FSC_Msk

    - -
    -
    - - - - -
    #define CAN_FS1R_FSC_Msk   (0xFFFFFFFUL << CAN_FS1R_FSC_Pos)
    -
    -

    0x0FFFFFFF

    - -
    -
    - -

    ◆ CAN_FS1R_FSC

    - -
    -
    - - - - -
    #define CAN_FS1R_FSC   CAN_FS1R_FSC_Msk
    -
    -

    Filter Scale Configuration

    - -
    -
    - -

    ◆ CAN_FS1R_FSC0_Pos

    - -
    -
    - - - - -
    #define CAN_FS1R_FSC0_Pos   (0U)
    -
    - -
    -
    - -

    ◆ CAN_FS1R_FSC0_Msk

    - -
    -
    - - - - -
    #define CAN_FS1R_FSC0_Msk   (0x1UL << CAN_FS1R_FSC0_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ CAN_FS1R_FSC0

    - -
    -
    - - - - -
    #define CAN_FS1R_FSC0   CAN_FS1R_FSC0_Msk
    -
    -

    Filter Scale Configuration bit 0

    - -
    -
    - -

    ◆ CAN_FS1R_FSC1_Pos

    - -
    -
    - - - - -
    #define CAN_FS1R_FSC1_Pos   (1U)
    -
    - -
    -
    - -

    ◆ CAN_FS1R_FSC1_Msk

    - -
    -
    - - - - -
    #define CAN_FS1R_FSC1_Msk   (0x1UL << CAN_FS1R_FSC1_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ CAN_FS1R_FSC1

    - -
    -
    - - - - -
    #define CAN_FS1R_FSC1   CAN_FS1R_FSC1_Msk
    -
    -

    Filter Scale Configuration bit 1

    - -
    -
    - -

    ◆ CAN_FS1R_FSC2_Pos

    - -
    -
    - - - - -
    #define CAN_FS1R_FSC2_Pos   (2U)
    -
    - -
    -
    - -

    ◆ CAN_FS1R_FSC2_Msk

    - -
    -
    - - - - -
    #define CAN_FS1R_FSC2_Msk   (0x1UL << CAN_FS1R_FSC2_Pos)
    -
    -

    0x00000004

    - -
    -
    - -

    ◆ CAN_FS1R_FSC2

    - -
    -
    - - - - -
    #define CAN_FS1R_FSC2   CAN_FS1R_FSC2_Msk
    -
    -

    Filter Scale Configuration bit 2

    - -
    -
    - -

    ◆ CAN_FS1R_FSC3_Pos

    - -
    -
    - - - - -
    #define CAN_FS1R_FSC3_Pos   (3U)
    -
    - -
    -
    - -

    ◆ CAN_FS1R_FSC3_Msk

    - -
    -
    - - - - -
    #define CAN_FS1R_FSC3_Msk   (0x1UL << CAN_FS1R_FSC3_Pos)
    -
    -

    0x00000008

    - -
    -
    - -

    ◆ CAN_FS1R_FSC3

    - -
    -
    - - - - -
    #define CAN_FS1R_FSC3   CAN_FS1R_FSC3_Msk
    -
    -

    Filter Scale Configuration bit 3

    - -
    -
    - -

    ◆ CAN_FS1R_FSC4_Pos

    - -
    -
    - - - - -
    #define CAN_FS1R_FSC4_Pos   (4U)
    -
    - -
    -
    - -

    ◆ CAN_FS1R_FSC4_Msk

    - -
    -
    - - - - -
    #define CAN_FS1R_FSC4_Msk   (0x1UL << CAN_FS1R_FSC4_Pos)
    -
    -

    0x00000010

    - -
    -
    - -

    ◆ CAN_FS1R_FSC4

    - -
    -
    - - - - -
    #define CAN_FS1R_FSC4   CAN_FS1R_FSC4_Msk
    -
    -

    Filter Scale Configuration bit 4

    - -
    -
    - -

    ◆ CAN_FS1R_FSC5_Pos

    - -
    -
    - - - - -
    #define CAN_FS1R_FSC5_Pos   (5U)
    -
    - -
    -
    - -

    ◆ CAN_FS1R_FSC5_Msk

    - -
    -
    - - - - -
    #define CAN_FS1R_FSC5_Msk   (0x1UL << CAN_FS1R_FSC5_Pos)
    -
    -

    0x00000020

    - -
    -
    - -

    ◆ CAN_FS1R_FSC5

    - -
    -
    - - - - -
    #define CAN_FS1R_FSC5   CAN_FS1R_FSC5_Msk
    -
    -

    Filter Scale Configuration bit 5

    - -
    -
    - -

    ◆ CAN_FS1R_FSC6_Pos

    - -
    -
    - - - - -
    #define CAN_FS1R_FSC6_Pos   (6U)
    -
    - -
    -
    - -

    ◆ CAN_FS1R_FSC6_Msk

    - -
    -
    - - - - -
    #define CAN_FS1R_FSC6_Msk   (0x1UL << CAN_FS1R_FSC6_Pos)
    -
    -

    0x00000040

    - -
    -
    - -

    ◆ CAN_FS1R_FSC6

    - -
    -
    - - - - -
    #define CAN_FS1R_FSC6   CAN_FS1R_FSC6_Msk
    -
    -

    Filter Scale Configuration bit 6

    - -
    -
    - -

    ◆ CAN_FS1R_FSC7_Pos

    - -
    -
    - - - - -
    #define CAN_FS1R_FSC7_Pos   (7U)
    -
    - -
    -
    - -

    ◆ CAN_FS1R_FSC7_Msk

    - -
    -
    - - - - -
    #define CAN_FS1R_FSC7_Msk   (0x1UL << CAN_FS1R_FSC7_Pos)
    -
    -

    0x00000080

    - -
    -
    - -

    ◆ CAN_FS1R_FSC7

    - -
    -
    - - - - -
    #define CAN_FS1R_FSC7   CAN_FS1R_FSC7_Msk
    -
    -

    Filter Scale Configuration bit 7

    - -
    -
    - -

    ◆ CAN_FS1R_FSC8_Pos

    - -
    -
    - - - - -
    #define CAN_FS1R_FSC8_Pos   (8U)
    -
    - -
    -
    - -

    ◆ CAN_FS1R_FSC8_Msk

    - -
    -
    - - - - -
    #define CAN_FS1R_FSC8_Msk   (0x1UL << CAN_FS1R_FSC8_Pos)
    -
    -

    0x00000100

    - -
    -
    - -

    ◆ CAN_FS1R_FSC8

    - -
    -
    - - - - -
    #define CAN_FS1R_FSC8   CAN_FS1R_FSC8_Msk
    -
    -

    Filter Scale Configuration bit 8

    - -
    -
    - -

    ◆ CAN_FS1R_FSC9_Pos

    - -
    -
    - - - - -
    #define CAN_FS1R_FSC9_Pos   (9U)
    -
    - -
    -
    - -

    ◆ CAN_FS1R_FSC9_Msk

    - -
    -
    - - - - -
    #define CAN_FS1R_FSC9_Msk   (0x1UL << CAN_FS1R_FSC9_Pos)
    -
    -

    0x00000200

    - -
    -
    - -

    ◆ CAN_FS1R_FSC9

    - -
    -
    - - - - -
    #define CAN_FS1R_FSC9   CAN_FS1R_FSC9_Msk
    -
    -

    Filter Scale Configuration bit 9

    - -
    -
    - -

    ◆ CAN_FS1R_FSC10_Pos

    - -
    -
    - - - - -
    #define CAN_FS1R_FSC10_Pos   (10U)
    -
    - -
    -
    - -

    ◆ CAN_FS1R_FSC10_Msk

    - -
    -
    - - - - -
    #define CAN_FS1R_FSC10_Msk   (0x1UL << CAN_FS1R_FSC10_Pos)
    -
    -

    0x00000400

    - -
    -
    - -

    ◆ CAN_FS1R_FSC10

    - -
    -
    - - - - -
    #define CAN_FS1R_FSC10   CAN_FS1R_FSC10_Msk
    -
    -

    Filter Scale Configuration bit 10

    - -
    -
    - -

    ◆ CAN_FS1R_FSC11_Pos

    - -
    -
    - - - - -
    #define CAN_FS1R_FSC11_Pos   (11U)
    -
    - -
    -
    - -

    ◆ CAN_FS1R_FSC11_Msk

    - -
    -
    - - - - -
    #define CAN_FS1R_FSC11_Msk   (0x1UL << CAN_FS1R_FSC11_Pos)
    -
    -

    0x00000800

    - -
    -
    - -

    ◆ CAN_FS1R_FSC11

    - -
    -
    - - - - -
    #define CAN_FS1R_FSC11   CAN_FS1R_FSC11_Msk
    -
    -

    Filter Scale Configuration bit 11

    - -
    -
    - -

    ◆ CAN_FS1R_FSC12_Pos

    - -
    -
    - - - - -
    #define CAN_FS1R_FSC12_Pos   (12U)
    -
    - -
    -
    - -

    ◆ CAN_FS1R_FSC12_Msk

    - -
    -
    - - - - -
    #define CAN_FS1R_FSC12_Msk   (0x1UL << CAN_FS1R_FSC12_Pos)
    -
    -

    0x00001000

    - -
    -
    - -

    ◆ CAN_FS1R_FSC12

    - -
    -
    - - - - -
    #define CAN_FS1R_FSC12   CAN_FS1R_FSC12_Msk
    -
    -

    Filter Scale Configuration bit 12

    - -
    -
    - -

    ◆ CAN_FS1R_FSC13_Pos

    - -
    -
    - - - - -
    #define CAN_FS1R_FSC13_Pos   (13U)
    -
    - -
    -
    - -

    ◆ CAN_FS1R_FSC13_Msk

    - -
    -
    - - - - -
    #define CAN_FS1R_FSC13_Msk   (0x1UL << CAN_FS1R_FSC13_Pos)
    -
    -

    0x00002000

    - -
    -
    - -

    ◆ CAN_FS1R_FSC13

    - -
    -
    - - - - -
    #define CAN_FS1R_FSC13   CAN_FS1R_FSC13_Msk
    -
    -

    Filter Scale Configuration bit 13

    - -
    -
    - -

    ◆ CAN_FS1R_FSC14_Pos

    - -
    -
    - - - - -
    #define CAN_FS1R_FSC14_Pos   (14U)
    -
    - -
    -
    - -

    ◆ CAN_FS1R_FSC14_Msk

    - -
    -
    - - - - -
    #define CAN_FS1R_FSC14_Msk   (0x1UL << CAN_FS1R_FSC14_Pos)
    -
    -

    0x00004000

    - -
    -
    - -

    ◆ CAN_FS1R_FSC14

    - -
    -
    - - - - -
    #define CAN_FS1R_FSC14   CAN_FS1R_FSC14_Msk
    -
    -

    Filter Scale Configuration bit 14

    - -
    -
    - -

    ◆ CAN_FS1R_FSC15_Pos

    - -
    -
    - - - - -
    #define CAN_FS1R_FSC15_Pos   (15U)
    -
    - -
    -
    - -

    ◆ CAN_FS1R_FSC15_Msk

    - -
    -
    - - - - -
    #define CAN_FS1R_FSC15_Msk   (0x1UL << CAN_FS1R_FSC15_Pos)
    -
    -

    0x00008000

    - -
    -
    - -

    ◆ CAN_FS1R_FSC15

    - -
    -
    - - - - -
    #define CAN_FS1R_FSC15   CAN_FS1R_FSC15_Msk
    -
    -

    Filter Scale Configuration bit 15

    - -
    -
    - -

    ◆ CAN_FS1R_FSC16_Pos

    - -
    -
    - - - - -
    #define CAN_FS1R_FSC16_Pos   (16U)
    -
    - -
    -
    - -

    ◆ CAN_FS1R_FSC16_Msk

    - -
    -
    - - - - -
    #define CAN_FS1R_FSC16_Msk   (0x1UL << CAN_FS1R_FSC16_Pos)
    -
    -

    0x00010000

    - -
    -
    - -

    ◆ CAN_FS1R_FSC16

    - -
    -
    - - - - -
    #define CAN_FS1R_FSC16   CAN_FS1R_FSC16_Msk
    -
    -

    Filter Scale Configuration bit 16

    - -
    -
    - -

    ◆ CAN_FS1R_FSC17_Pos

    - -
    -
    - - - - -
    #define CAN_FS1R_FSC17_Pos   (17U)
    -
    - -
    -
    - -

    ◆ CAN_FS1R_FSC17_Msk

    - -
    -
    - - - - -
    #define CAN_FS1R_FSC17_Msk   (0x1UL << CAN_FS1R_FSC17_Pos)
    -
    -

    0x00020000

    - -
    -
    - -

    ◆ CAN_FS1R_FSC17

    - -
    -
    - - - - -
    #define CAN_FS1R_FSC17   CAN_FS1R_FSC17_Msk
    -
    -

    Filter Scale Configuration bit 17

    - -
    -
    - -

    ◆ CAN_FS1R_FSC18_Pos

    - -
    -
    - - - - -
    #define CAN_FS1R_FSC18_Pos   (18U)
    -
    - -
    -
    - -

    ◆ CAN_FS1R_FSC18_Msk

    - -
    -
    - - - - -
    #define CAN_FS1R_FSC18_Msk   (0x1UL << CAN_FS1R_FSC18_Pos)
    -
    -

    0x00040000

    - -
    -
    - -

    ◆ CAN_FS1R_FSC18

    - -
    -
    - - - - -
    #define CAN_FS1R_FSC18   CAN_FS1R_FSC18_Msk
    -
    -

    Filter Scale Configuration bit 18

    - -
    -
    - -

    ◆ CAN_FS1R_FSC19_Pos

    - -
    -
    - - - - -
    #define CAN_FS1R_FSC19_Pos   (19U)
    -
    - -
    -
    - -

    ◆ CAN_FS1R_FSC19_Msk

    - -
    -
    - - - - -
    #define CAN_FS1R_FSC19_Msk   (0x1UL << CAN_FS1R_FSC19_Pos)
    -
    -

    0x00080000

    - -
    -
    - -

    ◆ CAN_FS1R_FSC19

    - -
    -
    - - - - -
    #define CAN_FS1R_FSC19   CAN_FS1R_FSC19_Msk
    -
    -

    Filter Scale Configuration bit 19

    - -
    -
    - -

    ◆ CAN_FS1R_FSC20_Pos

    - -
    -
    - - - - -
    #define CAN_FS1R_FSC20_Pos   (20U)
    -
    - -
    -
    - -

    ◆ CAN_FS1R_FSC20_Msk

    - -
    -
    - - - - -
    #define CAN_FS1R_FSC20_Msk   (0x1UL << CAN_FS1R_FSC20_Pos)
    -
    -

    0x00100000

    - -
    -
    - -

    ◆ CAN_FS1R_FSC20

    - -
    -
    - - - - -
    #define CAN_FS1R_FSC20   CAN_FS1R_FSC20_Msk
    -
    -

    Filter Scale Configuration bit 20

    - -
    -
    - -

    ◆ CAN_FS1R_FSC21_Pos

    - -
    -
    - - - - -
    #define CAN_FS1R_FSC21_Pos   (21U)
    -
    - -
    -
    - -

    ◆ CAN_FS1R_FSC21_Msk

    - -
    -
    - - - - -
    #define CAN_FS1R_FSC21_Msk   (0x1UL << CAN_FS1R_FSC21_Pos)
    -
    -

    0x00200000

    - -
    -
    - -

    ◆ CAN_FS1R_FSC21

    - -
    -
    - - - - -
    #define CAN_FS1R_FSC21   CAN_FS1R_FSC21_Msk
    -
    -

    Filter Scale Configuration bit 21

    - -
    -
    - -

    ◆ CAN_FS1R_FSC22_Pos

    - -
    -
    - - - - -
    #define CAN_FS1R_FSC22_Pos   (22U)
    -
    - -
    -
    - -

    ◆ CAN_FS1R_FSC22_Msk

    - -
    -
    - - - - -
    #define CAN_FS1R_FSC22_Msk   (0x1UL << CAN_FS1R_FSC22_Pos)
    -
    -

    0x00400000

    - -
    -
    - -

    ◆ CAN_FS1R_FSC22

    - -
    -
    - - - - -
    #define CAN_FS1R_FSC22   CAN_FS1R_FSC22_Msk
    -
    -

    Filter Scale Configuration bit 22

    - -
    -
    - -

    ◆ CAN_FS1R_FSC23_Pos

    - -
    -
    - - - - -
    #define CAN_FS1R_FSC23_Pos   (23U)
    -
    - -
    -
    - -

    ◆ CAN_FS1R_FSC23_Msk

    - -
    -
    - - - - -
    #define CAN_FS1R_FSC23_Msk   (0x1UL << CAN_FS1R_FSC23_Pos)
    -
    -

    0x00800000

    - -
    -
    - -

    ◆ CAN_FS1R_FSC23

    - -
    -
    - - - - -
    #define CAN_FS1R_FSC23   CAN_FS1R_FSC23_Msk
    -
    -

    Filter Scale Configuration bit 23

    - -
    -
    - -

    ◆ CAN_FS1R_FSC24_Pos

    - -
    -
    - - - - -
    #define CAN_FS1R_FSC24_Pos   (24U)
    -
    - -
    -
    - -

    ◆ CAN_FS1R_FSC24_Msk

    - -
    -
    - - - - -
    #define CAN_FS1R_FSC24_Msk   (0x1UL << CAN_FS1R_FSC24_Pos)
    -
    -

    0x01000000

    - -
    -
    - -

    ◆ CAN_FS1R_FSC24

    - -
    -
    - - - - -
    #define CAN_FS1R_FSC24   CAN_FS1R_FSC24_Msk
    -
    -

    Filter Scale Configuration bit 24

    - -
    -
    - -

    ◆ CAN_FS1R_FSC25_Pos

    - -
    -
    - - - - -
    #define CAN_FS1R_FSC25_Pos   (25U)
    -
    - -
    -
    - -

    ◆ CAN_FS1R_FSC25_Msk

    - -
    -
    - - - - -
    #define CAN_FS1R_FSC25_Msk   (0x1UL << CAN_FS1R_FSC25_Pos)
    -
    -

    0x02000000

    - -
    -
    - -

    ◆ CAN_FS1R_FSC25

    - -
    -
    - - - - -
    #define CAN_FS1R_FSC25   CAN_FS1R_FSC25_Msk
    -
    -

    Filter Scale Configuration bit 25

    - -
    -
    - -

    ◆ CAN_FS1R_FSC26_Pos

    - -
    -
    - - - - -
    #define CAN_FS1R_FSC26_Pos   (26U)
    -
    - -
    -
    - -

    ◆ CAN_FS1R_FSC26_Msk

    - -
    -
    - - - - -
    #define CAN_FS1R_FSC26_Msk   (0x1UL << CAN_FS1R_FSC26_Pos)
    -
    -

    0x04000000

    - -
    -
    - -

    ◆ CAN_FS1R_FSC26

    - -
    -
    - - - - -
    #define CAN_FS1R_FSC26   CAN_FS1R_FSC26_Msk
    -
    -

    Filter Scale Configuration bit 26

    - -
    -
    - -

    ◆ CAN_FS1R_FSC27_Pos

    - -
    -
    - - - - -
    #define CAN_FS1R_FSC27_Pos   (27U)
    -
    - -
    -
    - -

    ◆ CAN_FS1R_FSC27_Msk

    - -
    -
    - - - - -
    #define CAN_FS1R_FSC27_Msk   (0x1UL << CAN_FS1R_FSC27_Pos)
    -
    -

    0x08000000

    - -
    -
    - -

    ◆ CAN_FS1R_FSC27

    - -
    -
    - - - - -
    #define CAN_FS1R_FSC27   CAN_FS1R_FSC27_Msk
    -
    -

    Filter Scale Configuration bit 27

    - -
    -
    - -

    ◆ CAN_FFA1R_FFA_Pos

    - -
    -
    - - - - -
    #define CAN_FFA1R_FFA_Pos   (0U)
    -
    - -
    -
    - -

    ◆ CAN_FFA1R_FFA_Msk

    - -
    -
    - - - - -
    #define CAN_FFA1R_FFA_Msk   (0xFFFFFFFUL << CAN_FFA1R_FFA_Pos)
    -
    -

    0x0FFFFFFF

    - -
    -
    - -

    ◆ CAN_FFA1R_FFA

    - -
    -
    - - - - -
    #define CAN_FFA1R_FFA   CAN_FFA1R_FFA_Msk
    -
    -

    Filter FIFO Assignment

    - -
    -
    - -

    ◆ CAN_FFA1R_FFA0_Pos

    - -
    -
    - - - - -
    #define CAN_FFA1R_FFA0_Pos   (0U)
    -
    - -
    -
    - -

    ◆ CAN_FFA1R_FFA0_Msk

    - -
    -
    - - - - -
    #define CAN_FFA1R_FFA0_Msk   (0x1UL << CAN_FFA1R_FFA0_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ CAN_FFA1R_FFA0

    - -
    -
    - - - - -
    #define CAN_FFA1R_FFA0   CAN_FFA1R_FFA0_Msk
    -
    -

    Filter FIFO Assignment bit 0

    - -
    -
    - -

    ◆ CAN_FFA1R_FFA1_Pos

    - -
    -
    - - - - -
    #define CAN_FFA1R_FFA1_Pos   (1U)
    -
    - -
    -
    - -

    ◆ CAN_FFA1R_FFA1_Msk

    - -
    -
    - - - - -
    #define CAN_FFA1R_FFA1_Msk   (0x1UL << CAN_FFA1R_FFA1_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ CAN_FFA1R_FFA1

    - -
    -
    - - - - -
    #define CAN_FFA1R_FFA1   CAN_FFA1R_FFA1_Msk
    -
    -

    Filter FIFO Assignment bit 1

    - -
    -
    - -

    ◆ CAN_FFA1R_FFA2_Pos

    - -
    -
    - - - - -
    #define CAN_FFA1R_FFA2_Pos   (2U)
    -
    - -
    -
    - -

    ◆ CAN_FFA1R_FFA2_Msk

    - -
    -
    - - - - -
    #define CAN_FFA1R_FFA2_Msk   (0x1UL << CAN_FFA1R_FFA2_Pos)
    -
    -

    0x00000004

    - -
    -
    - -

    ◆ CAN_FFA1R_FFA2

    - -
    -
    - - - - -
    #define CAN_FFA1R_FFA2   CAN_FFA1R_FFA2_Msk
    -
    -

    Filter FIFO Assignment bit 2

    - -
    -
    - -

    ◆ CAN_FFA1R_FFA3_Pos

    - -
    -
    - - - - -
    #define CAN_FFA1R_FFA3_Pos   (3U)
    -
    - -
    -
    - -

    ◆ CAN_FFA1R_FFA3_Msk

    - -
    -
    - - - - -
    #define CAN_FFA1R_FFA3_Msk   (0x1UL << CAN_FFA1R_FFA3_Pos)
    -
    -

    0x00000008

    - -
    -
    - -

    ◆ CAN_FFA1R_FFA3

    - -
    -
    - - - - -
    #define CAN_FFA1R_FFA3   CAN_FFA1R_FFA3_Msk
    -
    -

    Filter FIFO Assignment bit 3

    - -
    -
    - -

    ◆ CAN_FFA1R_FFA4_Pos

    - -
    -
    - - - - -
    #define CAN_FFA1R_FFA4_Pos   (4U)
    -
    - -
    -
    - -

    ◆ CAN_FFA1R_FFA4_Msk

    - -
    -
    - - - - -
    #define CAN_FFA1R_FFA4_Msk   (0x1UL << CAN_FFA1R_FFA4_Pos)
    -
    -

    0x00000010

    - -
    -
    - -

    ◆ CAN_FFA1R_FFA4

    - -
    -
    - - - - -
    #define CAN_FFA1R_FFA4   CAN_FFA1R_FFA4_Msk
    -
    -

    Filter FIFO Assignment bit 4

    - -
    -
    - -

    ◆ CAN_FFA1R_FFA5_Pos

    - -
    -
    - - - - -
    #define CAN_FFA1R_FFA5_Pos   (5U)
    -
    - -
    -
    - -

    ◆ CAN_FFA1R_FFA5_Msk

    - -
    -
    - - - - -
    #define CAN_FFA1R_FFA5_Msk   (0x1UL << CAN_FFA1R_FFA5_Pos)
    -
    -

    0x00000020

    - -
    -
    - -

    ◆ CAN_FFA1R_FFA5

    - -
    -
    - - - - -
    #define CAN_FFA1R_FFA5   CAN_FFA1R_FFA5_Msk
    -
    -

    Filter FIFO Assignment bit 5

    - -
    -
    - -

    ◆ CAN_FFA1R_FFA6_Pos

    - -
    -
    - - - - -
    #define CAN_FFA1R_FFA6_Pos   (6U)
    -
    - -
    -
    - -

    ◆ CAN_FFA1R_FFA6_Msk

    - -
    -
    - - - - -
    #define CAN_FFA1R_FFA6_Msk   (0x1UL << CAN_FFA1R_FFA6_Pos)
    -
    -

    0x00000040

    - -
    -
    - -

    ◆ CAN_FFA1R_FFA6

    - -
    -
    - - - - -
    #define CAN_FFA1R_FFA6   CAN_FFA1R_FFA6_Msk
    -
    -

    Filter FIFO Assignment bit 6

    - -
    -
    - -

    ◆ CAN_FFA1R_FFA7_Pos

    - -
    -
    - - - - -
    #define CAN_FFA1R_FFA7_Pos   (7U)
    -
    - -
    -
    - -

    ◆ CAN_FFA1R_FFA7_Msk

    - -
    -
    - - - - -
    #define CAN_FFA1R_FFA7_Msk   (0x1UL << CAN_FFA1R_FFA7_Pos)
    -
    -

    0x00000080

    - -
    -
    - -

    ◆ CAN_FFA1R_FFA7

    - -
    -
    - - - - -
    #define CAN_FFA1R_FFA7   CAN_FFA1R_FFA7_Msk
    -
    -

    Filter FIFO Assignment bit 7

    - -
    -
    - -

    ◆ CAN_FFA1R_FFA8_Pos

    - -
    -
    - - - - -
    #define CAN_FFA1R_FFA8_Pos   (8U)
    -
    - -
    -
    - -

    ◆ CAN_FFA1R_FFA8_Msk

    - -
    -
    - - - - -
    #define CAN_FFA1R_FFA8_Msk   (0x1UL << CAN_FFA1R_FFA8_Pos)
    -
    -

    0x00000100

    - -
    -
    - -

    ◆ CAN_FFA1R_FFA8

    - -
    -
    - - - - -
    #define CAN_FFA1R_FFA8   CAN_FFA1R_FFA8_Msk
    -
    -

    Filter FIFO Assignment bit 8

    - -
    -
    - -

    ◆ CAN_FFA1R_FFA9_Pos

    - -
    -
    - - - - -
    #define CAN_FFA1R_FFA9_Pos   (9U)
    -
    - -
    -
    - -

    ◆ CAN_FFA1R_FFA9_Msk

    - -
    -
    - - - - -
    #define CAN_FFA1R_FFA9_Msk   (0x1UL << CAN_FFA1R_FFA9_Pos)
    -
    -

    0x00000200

    - -
    -
    - -

    ◆ CAN_FFA1R_FFA9

    - -
    -
    - - - - -
    #define CAN_FFA1R_FFA9   CAN_FFA1R_FFA9_Msk
    -
    -

    Filter FIFO Assignment bit 9

    - -
    -
    - -

    ◆ CAN_FFA1R_FFA10_Pos

    - -
    -
    - - - - -
    #define CAN_FFA1R_FFA10_Pos   (10U)
    -
    - -
    -
    - -

    ◆ CAN_FFA1R_FFA10_Msk

    - -
    -
    - - - - -
    #define CAN_FFA1R_FFA10_Msk   (0x1UL << CAN_FFA1R_FFA10_Pos)
    -
    -

    0x00000400

    - -
    -
    - -

    ◆ CAN_FFA1R_FFA10

    - -
    -
    - - - - -
    #define CAN_FFA1R_FFA10   CAN_FFA1R_FFA10_Msk
    -
    -

    Filter FIFO Assignment bit 10

    - -
    -
    - -

    ◆ CAN_FFA1R_FFA11_Pos

    - -
    -
    - - - - -
    #define CAN_FFA1R_FFA11_Pos   (11U)
    -
    - -
    -
    - -

    ◆ CAN_FFA1R_FFA11_Msk

    - -
    -
    - - - - -
    #define CAN_FFA1R_FFA11_Msk   (0x1UL << CAN_FFA1R_FFA11_Pos)
    -
    -

    0x00000800

    - -
    -
    - -

    ◆ CAN_FFA1R_FFA11

    - -
    -
    - - - - -
    #define CAN_FFA1R_FFA11   CAN_FFA1R_FFA11_Msk
    -
    -

    Filter FIFO Assignment bit 11

    - -
    -
    - -

    ◆ CAN_FFA1R_FFA12_Pos

    - -
    -
    - - - - -
    #define CAN_FFA1R_FFA12_Pos   (12U)
    -
    - -
    -
    - -

    ◆ CAN_FFA1R_FFA12_Msk

    - -
    -
    - - - - -
    #define CAN_FFA1R_FFA12_Msk   (0x1UL << CAN_FFA1R_FFA12_Pos)
    -
    -

    0x00001000

    - -
    -
    - -

    ◆ CAN_FFA1R_FFA12

    - -
    -
    - - - - -
    #define CAN_FFA1R_FFA12   CAN_FFA1R_FFA12_Msk
    -
    -

    Filter FIFO Assignment bit 12

    - -
    -
    - -

    ◆ CAN_FFA1R_FFA13_Pos

    - -
    -
    - - - - -
    #define CAN_FFA1R_FFA13_Pos   (13U)
    -
    - -
    -
    - -

    ◆ CAN_FFA1R_FFA13_Msk

    - -
    -
    - - - - -
    #define CAN_FFA1R_FFA13_Msk   (0x1UL << CAN_FFA1R_FFA13_Pos)
    -
    -

    0x00002000

    - -
    -
    - -

    ◆ CAN_FFA1R_FFA13

    - -
    -
    - - - - -
    #define CAN_FFA1R_FFA13   CAN_FFA1R_FFA13_Msk
    -
    -

    Filter FIFO Assignment bit 13

    - -
    -
    - -

    ◆ CAN_FFA1R_FFA14_Pos

    - -
    -
    - - - - -
    #define CAN_FFA1R_FFA14_Pos   (14U)
    -
    - -
    -
    - -

    ◆ CAN_FFA1R_FFA14_Msk

    - -
    -
    - - - - -
    #define CAN_FFA1R_FFA14_Msk   (0x1UL << CAN_FFA1R_FFA14_Pos)
    -
    -

    0x00004000

    - -
    -
    - -

    ◆ CAN_FFA1R_FFA14

    - -
    -
    - - - - -
    #define CAN_FFA1R_FFA14   CAN_FFA1R_FFA14_Msk
    -
    -

    Filter FIFO Assignment bit 14

    - -
    -
    - -

    ◆ CAN_FFA1R_FFA15_Pos

    - -
    -
    - - - - -
    #define CAN_FFA1R_FFA15_Pos   (15U)
    -
    - -
    -
    - -

    ◆ CAN_FFA1R_FFA15_Msk

    - -
    -
    - - - - -
    #define CAN_FFA1R_FFA15_Msk   (0x1UL << CAN_FFA1R_FFA15_Pos)
    -
    -

    0x00008000

    - -
    -
    - -

    ◆ CAN_FFA1R_FFA15

    - -
    -
    - - - - -
    #define CAN_FFA1R_FFA15   CAN_FFA1R_FFA15_Msk
    -
    -

    Filter FIFO Assignment bit 15

    - -
    -
    - -

    ◆ CAN_FFA1R_FFA16_Pos

    - -
    -
    - - - - -
    #define CAN_FFA1R_FFA16_Pos   (16U)
    -
    - -
    -
    - -

    ◆ CAN_FFA1R_FFA16_Msk

    - -
    -
    - - - - -
    #define CAN_FFA1R_FFA16_Msk   (0x1UL << CAN_FFA1R_FFA16_Pos)
    -
    -

    0x00010000

    - -
    -
    - -

    ◆ CAN_FFA1R_FFA16

    - -
    -
    - - - - -
    #define CAN_FFA1R_FFA16   CAN_FFA1R_FFA16_Msk
    -
    -

    Filter FIFO Assignment bit 16

    - -
    -
    - -

    ◆ CAN_FFA1R_FFA17_Pos

    - -
    -
    - - - - -
    #define CAN_FFA1R_FFA17_Pos   (17U)
    -
    - -
    -
    - -

    ◆ CAN_FFA1R_FFA17_Msk

    - -
    -
    - - - - -
    #define CAN_FFA1R_FFA17_Msk   (0x1UL << CAN_FFA1R_FFA17_Pos)
    -
    -

    0x00020000

    - -
    -
    - -

    ◆ CAN_FFA1R_FFA17

    - -
    -
    - - - - -
    #define CAN_FFA1R_FFA17   CAN_FFA1R_FFA17_Msk
    -
    -

    Filter FIFO Assignment bit 17

    - -
    -
    - -

    ◆ CAN_FFA1R_FFA18_Pos

    - -
    -
    - - - - -
    #define CAN_FFA1R_FFA18_Pos   (18U)
    -
    - -
    -
    - -

    ◆ CAN_FFA1R_FFA18_Msk

    - -
    -
    - - - - -
    #define CAN_FFA1R_FFA18_Msk   (0x1UL << CAN_FFA1R_FFA18_Pos)
    -
    -

    0x00040000

    - -
    -
    - -

    ◆ CAN_FFA1R_FFA18

    - -
    -
    - - - - -
    #define CAN_FFA1R_FFA18   CAN_FFA1R_FFA18_Msk
    -
    -

    Filter FIFO Assignment bit 18

    - -
    -
    - -

    ◆ CAN_FFA1R_FFA19_Pos

    - -
    -
    - - - - -
    #define CAN_FFA1R_FFA19_Pos   (19U)
    -
    - -
    -
    - -

    ◆ CAN_FFA1R_FFA19_Msk

    - -
    -
    - - - - -
    #define CAN_FFA1R_FFA19_Msk   (0x1UL << CAN_FFA1R_FFA19_Pos)
    -
    -

    0x00080000

    - -
    -
    - -

    ◆ CAN_FFA1R_FFA19

    - -
    -
    - - - - -
    #define CAN_FFA1R_FFA19   CAN_FFA1R_FFA19_Msk
    -
    -

    Filter FIFO Assignment bit 19

    - -
    -
    - -

    ◆ CAN_FFA1R_FFA20_Pos

    - -
    -
    - - - - -
    #define CAN_FFA1R_FFA20_Pos   (20U)
    -
    - -
    -
    - -

    ◆ CAN_FFA1R_FFA20_Msk

    - -
    -
    - - - - -
    #define CAN_FFA1R_FFA20_Msk   (0x1UL << CAN_FFA1R_FFA20_Pos)
    -
    -

    0x00100000

    - -
    -
    - -

    ◆ CAN_FFA1R_FFA20

    - -
    -
    - - - - -
    #define CAN_FFA1R_FFA20   CAN_FFA1R_FFA20_Msk
    -
    -

    Filter FIFO Assignment bit 20

    - -
    -
    - -

    ◆ CAN_FFA1R_FFA21_Pos

    - -
    -
    - - - - -
    #define CAN_FFA1R_FFA21_Pos   (21U)
    -
    - -
    -
    - -

    ◆ CAN_FFA1R_FFA21_Msk

    - -
    -
    - - - - -
    #define CAN_FFA1R_FFA21_Msk   (0x1UL << CAN_FFA1R_FFA21_Pos)
    -
    -

    0x00200000

    - -
    -
    - -

    ◆ CAN_FFA1R_FFA21

    - -
    -
    - - - - -
    #define CAN_FFA1R_FFA21   CAN_FFA1R_FFA21_Msk
    -
    -

    Filter FIFO Assignment bit 21

    - -
    -
    - -

    ◆ CAN_FFA1R_FFA22_Pos

    - -
    -
    - - - - -
    #define CAN_FFA1R_FFA22_Pos   (22U)
    -
    - -
    -
    - -

    ◆ CAN_FFA1R_FFA22_Msk

    - -
    -
    - - - - -
    #define CAN_FFA1R_FFA22_Msk   (0x1UL << CAN_FFA1R_FFA22_Pos)
    -
    -

    0x00400000

    - -
    -
    - -

    ◆ CAN_FFA1R_FFA22

    - -
    -
    - - - - -
    #define CAN_FFA1R_FFA22   CAN_FFA1R_FFA22_Msk
    -
    -

    Filter FIFO Assignment bit 22

    - -
    -
    - -

    ◆ CAN_FFA1R_FFA23_Pos

    - -
    -
    - - - - -
    #define CAN_FFA1R_FFA23_Pos   (23U)
    -
    - -
    -
    - -

    ◆ CAN_FFA1R_FFA23_Msk

    - -
    -
    - - - - -
    #define CAN_FFA1R_FFA23_Msk   (0x1UL << CAN_FFA1R_FFA23_Pos)
    -
    -

    0x00800000

    - -
    -
    - -

    ◆ CAN_FFA1R_FFA23

    - -
    -
    - - - - -
    #define CAN_FFA1R_FFA23   CAN_FFA1R_FFA23_Msk
    -
    -

    Filter FIFO Assignment bit 23

    - -
    -
    - -

    ◆ CAN_FFA1R_FFA24_Pos

    - -
    -
    - - - - -
    #define CAN_FFA1R_FFA24_Pos   (24U)
    -
    - -
    -
    - -

    ◆ CAN_FFA1R_FFA24_Msk

    - -
    -
    - - - - -
    #define CAN_FFA1R_FFA24_Msk   (0x1UL << CAN_FFA1R_FFA24_Pos)
    -
    -

    0x01000000

    - -
    -
    - -

    ◆ CAN_FFA1R_FFA24

    - -
    -
    - - - - -
    #define CAN_FFA1R_FFA24   CAN_FFA1R_FFA24_Msk
    -
    -

    Filter FIFO Assignment bit 24

    - -
    -
    - -

    ◆ CAN_FFA1R_FFA25_Pos

    - -
    -
    - - - - -
    #define CAN_FFA1R_FFA25_Pos   (25U)
    -
    - -
    -
    - -

    ◆ CAN_FFA1R_FFA25_Msk

    - -
    -
    - - - - -
    #define CAN_FFA1R_FFA25_Msk   (0x1UL << CAN_FFA1R_FFA25_Pos)
    -
    -

    0x02000000

    - -
    -
    - -

    ◆ CAN_FFA1R_FFA25

    - -
    -
    - - - - -
    #define CAN_FFA1R_FFA25   CAN_FFA1R_FFA25_Msk
    -
    -

    Filter FIFO Assignment bit 25

    - -
    -
    - -

    ◆ CAN_FFA1R_FFA26_Pos

    - -
    -
    - - - - -
    #define CAN_FFA1R_FFA26_Pos   (26U)
    -
    - -
    -
    - -

    ◆ CAN_FFA1R_FFA26_Msk

    - -
    -
    - - - - -
    #define CAN_FFA1R_FFA26_Msk   (0x1UL << CAN_FFA1R_FFA26_Pos)
    -
    -

    0x04000000

    - -
    -
    - -

    ◆ CAN_FFA1R_FFA26

    - -
    -
    - - - - -
    #define CAN_FFA1R_FFA26   CAN_FFA1R_FFA26_Msk
    -
    -

    Filter FIFO Assignment bit 26

    - -
    -
    - -

    ◆ CAN_FFA1R_FFA27_Pos

    - -
    -
    - - - - -
    #define CAN_FFA1R_FFA27_Pos   (27U)
    -
    - -
    -
    - -

    ◆ CAN_FFA1R_FFA27_Msk

    - -
    -
    - - - - -
    #define CAN_FFA1R_FFA27_Msk   (0x1UL << CAN_FFA1R_FFA27_Pos)
    -
    -

    0x08000000

    - -
    -
    - -

    ◆ CAN_FFA1R_FFA27

    - -
    -
    - - - - -
    #define CAN_FFA1R_FFA27   CAN_FFA1R_FFA27_Msk
    -
    -

    Filter FIFO Assignment bit 27

    - -
    -
    - -

    ◆ CAN_FA1R_FACT_Pos

    - -
    -
    - - - - -
    #define CAN_FA1R_FACT_Pos   (0U)
    -
    - -
    -
    - -

    ◆ CAN_FA1R_FACT_Msk

    - -
    -
    - - - - -
    #define CAN_FA1R_FACT_Msk   (0xFFFFFFFUL << CAN_FA1R_FACT_Pos)
    -
    -

    0x0FFFFFFF

    - -
    -
    - -

    ◆ CAN_FA1R_FACT

    - -
    -
    - - - - -
    #define CAN_FA1R_FACT   CAN_FA1R_FACT_Msk
    -
    -

    Filter Active

    - -
    -
    - -

    ◆ CAN_FA1R_FACT0_Pos

    - -
    -
    - - - - -
    #define CAN_FA1R_FACT0_Pos   (0U)
    -
    - -
    -
    - -

    ◆ CAN_FA1R_FACT0_Msk

    - -
    -
    - - - - -
    #define CAN_FA1R_FACT0_Msk   (0x1UL << CAN_FA1R_FACT0_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ CAN_FA1R_FACT0

    - -
    -
    - - - - -
    #define CAN_FA1R_FACT0   CAN_FA1R_FACT0_Msk
    -
    -

    Filter Active bit 0

    - -
    -
    - -

    ◆ CAN_FA1R_FACT1_Pos

    - -
    -
    - - - - -
    #define CAN_FA1R_FACT1_Pos   (1U)
    -
    - -
    -
    - -

    ◆ CAN_FA1R_FACT1_Msk

    - -
    -
    - - - - -
    #define CAN_FA1R_FACT1_Msk   (0x1UL << CAN_FA1R_FACT1_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ CAN_FA1R_FACT1

    - -
    -
    - - - - -
    #define CAN_FA1R_FACT1   CAN_FA1R_FACT1_Msk
    -
    -

    Filter Active bit 1

    - -
    -
    - -

    ◆ CAN_FA1R_FACT2_Pos

    - -
    -
    - - - - -
    #define CAN_FA1R_FACT2_Pos   (2U)
    -
    - -
    -
    - -

    ◆ CAN_FA1R_FACT2_Msk

    - -
    -
    - - - - -
    #define CAN_FA1R_FACT2_Msk   (0x1UL << CAN_FA1R_FACT2_Pos)
    -
    -

    0x00000004

    - -
    -
    - -

    ◆ CAN_FA1R_FACT2

    - -
    -
    - - - - -
    #define CAN_FA1R_FACT2   CAN_FA1R_FACT2_Msk
    -
    -

    Filter Active bit 2

    - -
    -
    - -

    ◆ CAN_FA1R_FACT3_Pos

    - -
    -
    - - - - -
    #define CAN_FA1R_FACT3_Pos   (3U)
    -
    - -
    -
    - -

    ◆ CAN_FA1R_FACT3_Msk

    - -
    -
    - - - - -
    #define CAN_FA1R_FACT3_Msk   (0x1UL << CAN_FA1R_FACT3_Pos)
    -
    -

    0x00000008

    - -
    -
    - -

    ◆ CAN_FA1R_FACT3

    - -
    -
    - - - - -
    #define CAN_FA1R_FACT3   CAN_FA1R_FACT3_Msk
    -
    -

    Filter Active bit 3

    - -
    -
    - -

    ◆ CAN_FA1R_FACT4_Pos

    - -
    -
    - - - - -
    #define CAN_FA1R_FACT4_Pos   (4U)
    -
    - -
    -
    - -

    ◆ CAN_FA1R_FACT4_Msk

    - -
    -
    - - - - -
    #define CAN_FA1R_FACT4_Msk   (0x1UL << CAN_FA1R_FACT4_Pos)
    -
    -

    0x00000010

    - -
    -
    - -

    ◆ CAN_FA1R_FACT4

    - -
    -
    - - - - -
    #define CAN_FA1R_FACT4   CAN_FA1R_FACT4_Msk
    -
    -

    Filter Active bit 4

    - -
    -
    - -

    ◆ CAN_FA1R_FACT5_Pos

    - -
    -
    - - - - -
    #define CAN_FA1R_FACT5_Pos   (5U)
    -
    - -
    -
    - -

    ◆ CAN_FA1R_FACT5_Msk

    - -
    -
    - - - - -
    #define CAN_FA1R_FACT5_Msk   (0x1UL << CAN_FA1R_FACT5_Pos)
    -
    -

    0x00000020

    - -
    -
    - -

    ◆ CAN_FA1R_FACT5

    - -
    -
    - - - - -
    #define CAN_FA1R_FACT5   CAN_FA1R_FACT5_Msk
    -
    -

    Filter Active bit 5

    - -
    -
    - -

    ◆ CAN_FA1R_FACT6_Pos

    - -
    -
    - - - - -
    #define CAN_FA1R_FACT6_Pos   (6U)
    -
    - -
    -
    - -

    ◆ CAN_FA1R_FACT6_Msk

    - -
    -
    - - - - -
    #define CAN_FA1R_FACT6_Msk   (0x1UL << CAN_FA1R_FACT6_Pos)
    -
    -

    0x00000040

    - -
    -
    - -

    ◆ CAN_FA1R_FACT6

    - -
    -
    - - - - -
    #define CAN_FA1R_FACT6   CAN_FA1R_FACT6_Msk
    -
    -

    Filter Active bit 6

    - -
    -
    - -

    ◆ CAN_FA1R_FACT7_Pos

    - -
    -
    - - - - -
    #define CAN_FA1R_FACT7_Pos   (7U)
    -
    - -
    -
    - -

    ◆ CAN_FA1R_FACT7_Msk

    - -
    -
    - - - - -
    #define CAN_FA1R_FACT7_Msk   (0x1UL << CAN_FA1R_FACT7_Pos)
    -
    -

    0x00000080

    - -
    -
    - -

    ◆ CAN_FA1R_FACT7

    - -
    -
    - - - - -
    #define CAN_FA1R_FACT7   CAN_FA1R_FACT7_Msk
    -
    -

    Filter Active bit 7

    - -
    -
    - -

    ◆ CAN_FA1R_FACT8_Pos

    - -
    -
    - - - - -
    #define CAN_FA1R_FACT8_Pos   (8U)
    -
    - -
    -
    - -

    ◆ CAN_FA1R_FACT8_Msk

    - -
    -
    - - - - -
    #define CAN_FA1R_FACT8_Msk   (0x1UL << CAN_FA1R_FACT8_Pos)
    -
    -

    0x00000100

    - -
    -
    - -

    ◆ CAN_FA1R_FACT8

    - -
    -
    - - - - -
    #define CAN_FA1R_FACT8   CAN_FA1R_FACT8_Msk
    -
    -

    Filter Active bit 8

    - -
    -
    - -

    ◆ CAN_FA1R_FACT9_Pos

    - -
    -
    - - - - -
    #define CAN_FA1R_FACT9_Pos   (9U)
    -
    - -
    -
    - -

    ◆ CAN_FA1R_FACT9_Msk

    - -
    -
    - - - - -
    #define CAN_FA1R_FACT9_Msk   (0x1UL << CAN_FA1R_FACT9_Pos)
    -
    -

    0x00000200

    - -
    -
    - -

    ◆ CAN_FA1R_FACT9

    - -
    -
    - - - - -
    #define CAN_FA1R_FACT9   CAN_FA1R_FACT9_Msk
    -
    -

    Filter Active bit 9

    - -
    -
    - -

    ◆ CAN_FA1R_FACT10_Pos

    - -
    -
    - - - - -
    #define CAN_FA1R_FACT10_Pos   (10U)
    -
    - -
    -
    - -

    ◆ CAN_FA1R_FACT10_Msk

    - -
    -
    - - - - -
    #define CAN_FA1R_FACT10_Msk   (0x1UL << CAN_FA1R_FACT10_Pos)
    -
    -

    0x00000400

    - -
    -
    - -

    ◆ CAN_FA1R_FACT10

    - -
    -
    - - - - -
    #define CAN_FA1R_FACT10   CAN_FA1R_FACT10_Msk
    -
    -

    Filter Active bit 10

    - -
    -
    - -

    ◆ CAN_FA1R_FACT11_Pos

    - -
    -
    - - - - -
    #define CAN_FA1R_FACT11_Pos   (11U)
    -
    - -
    -
    - -

    ◆ CAN_FA1R_FACT11_Msk

    - -
    -
    - - - - -
    #define CAN_FA1R_FACT11_Msk   (0x1UL << CAN_FA1R_FACT11_Pos)
    -
    -

    0x00000800

    - -
    -
    - -

    ◆ CAN_FA1R_FACT11

    - -
    -
    - - - - -
    #define CAN_FA1R_FACT11   CAN_FA1R_FACT11_Msk
    -
    -

    Filter Active bit 11

    - -
    -
    - -

    ◆ CAN_FA1R_FACT12_Pos

    - -
    -
    - - - - -
    #define CAN_FA1R_FACT12_Pos   (12U)
    -
    - -
    -
    - -

    ◆ CAN_FA1R_FACT12_Msk

    - -
    -
    - - - - -
    #define CAN_FA1R_FACT12_Msk   (0x1UL << CAN_FA1R_FACT12_Pos)
    -
    -

    0x00001000

    - -
    -
    - -

    ◆ CAN_FA1R_FACT12

    - -
    -
    - - - - -
    #define CAN_FA1R_FACT12   CAN_FA1R_FACT12_Msk
    -
    -

    Filter Active bit 12

    - -
    -
    - -

    ◆ CAN_FA1R_FACT13_Pos

    - -
    -
    - - - - -
    #define CAN_FA1R_FACT13_Pos   (13U)
    -
    - -
    -
    - -

    ◆ CAN_FA1R_FACT13_Msk

    - -
    -
    - - - - -
    #define CAN_FA1R_FACT13_Msk   (0x1UL << CAN_FA1R_FACT13_Pos)
    -
    -

    0x00002000

    - -
    -
    - -

    ◆ CAN_FA1R_FACT13

    - -
    -
    - - - - -
    #define CAN_FA1R_FACT13   CAN_FA1R_FACT13_Msk
    -
    -

    Filter Active bit 13

    - -
    -
    - -

    ◆ CAN_FA1R_FACT14_Pos

    - -
    -
    - - - - -
    #define CAN_FA1R_FACT14_Pos   (14U)
    -
    - -
    -
    - -

    ◆ CAN_FA1R_FACT14_Msk

    - -
    -
    - - - - -
    #define CAN_FA1R_FACT14_Msk   (0x1UL << CAN_FA1R_FACT14_Pos)
    -
    -

    0x00004000

    - -
    -
    - -

    ◆ CAN_FA1R_FACT14

    - -
    -
    - - - - -
    #define CAN_FA1R_FACT14   CAN_FA1R_FACT14_Msk
    -
    -

    Filter Active bit 14

    - -
    -
    - -

    ◆ CAN_FA1R_FACT15_Pos

    - -
    -
    - - - - -
    #define CAN_FA1R_FACT15_Pos   (15U)
    -
    - -
    -
    - -

    ◆ CAN_FA1R_FACT15_Msk

    - -
    -
    - - - - -
    #define CAN_FA1R_FACT15_Msk   (0x1UL << CAN_FA1R_FACT15_Pos)
    -
    -

    0x00008000

    - -
    -
    - -

    ◆ CAN_FA1R_FACT15

    - -
    -
    - - - - -
    #define CAN_FA1R_FACT15   CAN_FA1R_FACT15_Msk
    -
    -

    Filter Active bit 15

    - -
    -
    - -

    ◆ CAN_FA1R_FACT16_Pos

    - -
    -
    - - - - -
    #define CAN_FA1R_FACT16_Pos   (16U)
    -
    - -
    -
    - -

    ◆ CAN_FA1R_FACT16_Msk

    - -
    -
    - - - - -
    #define CAN_FA1R_FACT16_Msk   (0x1UL << CAN_FA1R_FACT16_Pos)
    -
    -

    0x00010000

    - -
    -
    - -

    ◆ CAN_FA1R_FACT16

    - -
    -
    - - - - -
    #define CAN_FA1R_FACT16   CAN_FA1R_FACT16_Msk
    -
    -

    Filter Active bit 16

    - -
    -
    - -

    ◆ CAN_FA1R_FACT17_Pos

    - -
    -
    - - - - -
    #define CAN_FA1R_FACT17_Pos   (17U)
    -
    - -
    -
    - -

    ◆ CAN_FA1R_FACT17_Msk

    - -
    -
    - - - - -
    #define CAN_FA1R_FACT17_Msk   (0x1UL << CAN_FA1R_FACT17_Pos)
    -
    -

    0x00020000

    - -
    -
    - -

    ◆ CAN_FA1R_FACT17

    - -
    -
    - - - - -
    #define CAN_FA1R_FACT17   CAN_FA1R_FACT17_Msk
    -
    -

    Filter Active bit 17

    - -
    -
    - -

    ◆ CAN_FA1R_FACT18_Pos

    - -
    -
    - - - - -
    #define CAN_FA1R_FACT18_Pos   (18U)
    -
    - -
    -
    - -

    ◆ CAN_FA1R_FACT18_Msk

    - -
    -
    - - - - -
    #define CAN_FA1R_FACT18_Msk   (0x1UL << CAN_FA1R_FACT18_Pos)
    -
    -

    0x00040000

    - -
    -
    - -

    ◆ CAN_FA1R_FACT18

    - -
    -
    - - - - -
    #define CAN_FA1R_FACT18   CAN_FA1R_FACT18_Msk
    -
    -

    Filter Active bit 18

    - -
    -
    - -

    ◆ CAN_FA1R_FACT19_Pos

    - -
    -
    - - - - -
    #define CAN_FA1R_FACT19_Pos   (19U)
    -
    - -
    -
    - -

    ◆ CAN_FA1R_FACT19_Msk

    - -
    -
    - - - - -
    #define CAN_FA1R_FACT19_Msk   (0x1UL << CAN_FA1R_FACT19_Pos)
    -
    -

    0x00080000

    - -
    -
    - -

    ◆ CAN_FA1R_FACT19

    - -
    -
    - - - - -
    #define CAN_FA1R_FACT19   CAN_FA1R_FACT19_Msk
    -
    -

    Filter Active bit 19

    - -
    -
    - -

    ◆ CAN_FA1R_FACT20_Pos

    - -
    -
    - - - - -
    #define CAN_FA1R_FACT20_Pos   (20U)
    -
    - -
    -
    - -

    ◆ CAN_FA1R_FACT20_Msk

    - -
    -
    - - - - -
    #define CAN_FA1R_FACT20_Msk   (0x1UL << CAN_FA1R_FACT20_Pos)
    -
    -

    0x00100000

    - -
    -
    - -

    ◆ CAN_FA1R_FACT20

    - -
    -
    - - - - -
    #define CAN_FA1R_FACT20   CAN_FA1R_FACT20_Msk
    -
    -

    Filter Active bit 20

    - -
    -
    - -

    ◆ CAN_FA1R_FACT21_Pos

    - -
    -
    - - - - -
    #define CAN_FA1R_FACT21_Pos   (21U)
    -
    - -
    -
    - -

    ◆ CAN_FA1R_FACT21_Msk

    - -
    -
    - - - - -
    #define CAN_FA1R_FACT21_Msk   (0x1UL << CAN_FA1R_FACT21_Pos)
    -
    -

    0x00200000

    - -
    -
    - -

    ◆ CAN_FA1R_FACT21

    - -
    -
    - - - - -
    #define CAN_FA1R_FACT21   CAN_FA1R_FACT21_Msk
    -
    -

    Filter Active bit 21

    - -
    -
    - -

    ◆ CAN_FA1R_FACT22_Pos

    - -
    -
    - - - - -
    #define CAN_FA1R_FACT22_Pos   (22U)
    -
    - -
    -
    - -

    ◆ CAN_FA1R_FACT22_Msk

    - -
    -
    - - - - -
    #define CAN_FA1R_FACT22_Msk   (0x1UL << CAN_FA1R_FACT22_Pos)
    -
    -

    0x00400000

    - -
    -
    - -

    ◆ CAN_FA1R_FACT22

    - -
    -
    - - - - -
    #define CAN_FA1R_FACT22   CAN_FA1R_FACT22_Msk
    -
    -

    Filter Active bit 22

    - -
    -
    - -

    ◆ CAN_FA1R_FACT23_Pos

    - -
    -
    - - - - -
    #define CAN_FA1R_FACT23_Pos   (23U)
    -
    - -
    -
    - -

    ◆ CAN_FA1R_FACT23_Msk

    - -
    -
    - - - - -
    #define CAN_FA1R_FACT23_Msk   (0x1UL << CAN_FA1R_FACT23_Pos)
    -
    -

    0x00800000

    - -
    -
    - -

    ◆ CAN_FA1R_FACT23

    - -
    -
    - - - - -
    #define CAN_FA1R_FACT23   CAN_FA1R_FACT23_Msk
    -
    -

    Filter Active bit 23

    - -
    -
    - -

    ◆ CAN_FA1R_FACT24_Pos

    - -
    -
    - - - - -
    #define CAN_FA1R_FACT24_Pos   (24U)
    -
    - -
    -
    - -

    ◆ CAN_FA1R_FACT24_Msk

    - -
    -
    - - - - -
    #define CAN_FA1R_FACT24_Msk   (0x1UL << CAN_FA1R_FACT24_Pos)
    -
    -

    0x01000000

    - -
    -
    - -

    ◆ CAN_FA1R_FACT24

    - -
    -
    - - - - -
    #define CAN_FA1R_FACT24   CAN_FA1R_FACT24_Msk
    -
    -

    Filter Active bit 24

    - -
    -
    - -

    ◆ CAN_FA1R_FACT25_Pos

    - -
    -
    - - - - -
    #define CAN_FA1R_FACT25_Pos   (25U)
    -
    - -
    -
    - -

    ◆ CAN_FA1R_FACT25_Msk

    - -
    -
    - - - - -
    #define CAN_FA1R_FACT25_Msk   (0x1UL << CAN_FA1R_FACT25_Pos)
    -
    -

    0x02000000

    - -
    -
    - -

    ◆ CAN_FA1R_FACT25

    - -
    -
    - - - - -
    #define CAN_FA1R_FACT25   CAN_FA1R_FACT25_Msk
    -
    -

    Filter Active bit 25

    - -
    -
    - -

    ◆ CAN_FA1R_FACT26_Pos

    - -
    -
    - - - - -
    #define CAN_FA1R_FACT26_Pos   (26U)
    -
    - -
    -
    - -

    ◆ CAN_FA1R_FACT26_Msk

    - -
    -
    - - - - -
    #define CAN_FA1R_FACT26_Msk   (0x1UL << CAN_FA1R_FACT26_Pos)
    -
    -

    0x04000000

    - -
    -
    - -

    ◆ CAN_FA1R_FACT26

    - -
    -
    - - - - -
    #define CAN_FA1R_FACT26   CAN_FA1R_FACT26_Msk
    -
    -

    Filter Active bit 26

    - -
    -
    - -

    ◆ CAN_FA1R_FACT27_Pos

    - -
    -
    - - - - -
    #define CAN_FA1R_FACT27_Pos   (27U)
    -
    - -
    -
    - -

    ◆ CAN_FA1R_FACT27_Msk

    - -
    -
    - - - - -
    #define CAN_FA1R_FACT27_Msk   (0x1UL << CAN_FA1R_FACT27_Pos)
    -
    -

    0x08000000

    - -
    -
    - -

    ◆ CAN_FA1R_FACT27

    - -
    -
    - - - - -
    #define CAN_FA1R_FACT27   CAN_FA1R_FACT27_Msk
    -
    -

    Filter Active bit 27

    - -
    -
    - -

    ◆ CAN_F0R1_FB0_Pos

    - -
    -
    - - - - -
    #define CAN_F0R1_FB0_Pos   (0U)
    -
    - -
    -
    - -

    ◆ CAN_F0R1_FB0_Msk

    - -
    -
    - - - - -
    #define CAN_F0R1_FB0_Msk   (0x1UL << CAN_F0R1_FB0_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ CAN_F0R1_FB0

    - -
    -
    - - - - -
    #define CAN_F0R1_FB0   CAN_F0R1_FB0_Msk
    -
    -

    Filter bit 0

    - -
    -
    - -

    ◆ CAN_F0R1_FB1_Pos

    - -
    -
    - - - - -
    #define CAN_F0R1_FB1_Pos   (1U)
    -
    - -
    -
    - -

    ◆ CAN_F0R1_FB1_Msk

    - -
    -
    - - - - -
    #define CAN_F0R1_FB1_Msk   (0x1UL << CAN_F0R1_FB1_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ CAN_F0R1_FB1

    - -
    -
    - - - - -
    #define CAN_F0R1_FB1   CAN_F0R1_FB1_Msk
    -
    -

    Filter bit 1

    - -
    -
    - -

    ◆ CAN_F0R1_FB2_Pos

    - -
    -
    - - - - -
    #define CAN_F0R1_FB2_Pos   (2U)
    -
    - -
    -
    - -

    ◆ CAN_F0R1_FB2_Msk

    - -
    -
    - - - - -
    #define CAN_F0R1_FB2_Msk   (0x1UL << CAN_F0R1_FB2_Pos)
    -
    -

    0x00000004

    - -
    -
    - -

    ◆ CAN_F0R1_FB2

    - -
    -
    - - - - -
    #define CAN_F0R1_FB2   CAN_F0R1_FB2_Msk
    -
    -

    Filter bit 2

    - -
    -
    - -

    ◆ CAN_F0R1_FB3_Pos

    - -
    -
    - - - - -
    #define CAN_F0R1_FB3_Pos   (3U)
    -
    - -
    -
    - -

    ◆ CAN_F0R1_FB3_Msk

    - -
    -
    - - - - -
    #define CAN_F0R1_FB3_Msk   (0x1UL << CAN_F0R1_FB3_Pos)
    -
    -

    0x00000008

    - -
    -
    - -

    ◆ CAN_F0R1_FB3

    - -
    -
    - - - - -
    #define CAN_F0R1_FB3   CAN_F0R1_FB3_Msk
    -
    -

    Filter bit 3

    - -
    -
    - -

    ◆ CAN_F0R1_FB4_Pos

    - -
    -
    - - - - -
    #define CAN_F0R1_FB4_Pos   (4U)
    -
    - -
    -
    - -

    ◆ CAN_F0R1_FB4_Msk

    - -
    -
    - - - - -
    #define CAN_F0R1_FB4_Msk   (0x1UL << CAN_F0R1_FB4_Pos)
    -
    -

    0x00000010

    - -
    -
    - -

    ◆ CAN_F0R1_FB4

    - -
    -
    - - - - -
    #define CAN_F0R1_FB4   CAN_F0R1_FB4_Msk
    -
    -

    Filter bit 4

    - -
    -
    - -

    ◆ CAN_F0R1_FB5_Pos

    - -
    -
    - - - - -
    #define CAN_F0R1_FB5_Pos   (5U)
    -
    - -
    -
    - -

    ◆ CAN_F0R1_FB5_Msk

    - -
    -
    - - - - -
    #define CAN_F0R1_FB5_Msk   (0x1UL << CAN_F0R1_FB5_Pos)
    -
    -

    0x00000020

    - -
    -
    - -

    ◆ CAN_F0R1_FB5

    - -
    -
    - - - - -
    #define CAN_F0R1_FB5   CAN_F0R1_FB5_Msk
    -
    -

    Filter bit 5

    - -
    -
    - -

    ◆ CAN_F0R1_FB6_Pos

    - -
    -
    - - - - -
    #define CAN_F0R1_FB6_Pos   (6U)
    -
    - -
    -
    - -

    ◆ CAN_F0R1_FB6_Msk

    - -
    -
    - - - - -
    #define CAN_F0R1_FB6_Msk   (0x1UL << CAN_F0R1_FB6_Pos)
    -
    -

    0x00000040

    - -
    -
    - -

    ◆ CAN_F0R1_FB6

    - -
    -
    - - - - -
    #define CAN_F0R1_FB6   CAN_F0R1_FB6_Msk
    -
    -

    Filter bit 6

    - -
    -
    - -

    ◆ CAN_F0R1_FB7_Pos

    - -
    -
    - - - - -
    #define CAN_F0R1_FB7_Pos   (7U)
    -
    - -
    -
    - -

    ◆ CAN_F0R1_FB7_Msk

    - -
    -
    - - - - -
    #define CAN_F0R1_FB7_Msk   (0x1UL << CAN_F0R1_FB7_Pos)
    -
    -

    0x00000080

    - -
    -
    - -

    ◆ CAN_F0R1_FB7

    - -
    -
    - - - - -
    #define CAN_F0R1_FB7   CAN_F0R1_FB7_Msk
    -
    -

    Filter bit 7

    - -
    -
    - -

    ◆ CAN_F0R1_FB8_Pos

    - -
    -
    - - - - -
    #define CAN_F0R1_FB8_Pos   (8U)
    -
    - -
    -
    - -

    ◆ CAN_F0R1_FB8_Msk

    - -
    -
    - - - - -
    #define CAN_F0R1_FB8_Msk   (0x1UL << CAN_F0R1_FB8_Pos)
    -
    -

    0x00000100

    - -
    -
    - -

    ◆ CAN_F0R1_FB8

    - -
    -
    - - - - -
    #define CAN_F0R1_FB8   CAN_F0R1_FB8_Msk
    -
    -

    Filter bit 8

    - -
    -
    - -

    ◆ CAN_F0R1_FB9_Pos

    - -
    -
    - - - - -
    #define CAN_F0R1_FB9_Pos   (9U)
    -
    - -
    -
    - -

    ◆ CAN_F0R1_FB9_Msk

    - -
    -
    - - - - -
    #define CAN_F0R1_FB9_Msk   (0x1UL << CAN_F0R1_FB9_Pos)
    -
    -

    0x00000200

    - -
    -
    - -

    ◆ CAN_F0R1_FB9

    - -
    -
    - - - - -
    #define CAN_F0R1_FB9   CAN_F0R1_FB9_Msk
    -
    -

    Filter bit 9

    - -
    -
    - -

    ◆ CAN_F0R1_FB10_Pos

    - -
    -
    - - - - -
    #define CAN_F0R1_FB10_Pos   (10U)
    -
    - -
    -
    - -

    ◆ CAN_F0R1_FB10_Msk

    - -
    -
    - - - - -
    #define CAN_F0R1_FB10_Msk   (0x1UL << CAN_F0R1_FB10_Pos)
    -
    -

    0x00000400

    - -
    -
    - -

    ◆ CAN_F0R1_FB10

    - -
    -
    - - - - -
    #define CAN_F0R1_FB10   CAN_F0R1_FB10_Msk
    -
    -

    Filter bit 10

    - -
    -
    - -

    ◆ CAN_F0R1_FB11_Pos

    - -
    -
    - - - - -
    #define CAN_F0R1_FB11_Pos   (11U)
    -
    - -
    -
    - -

    ◆ CAN_F0R1_FB11_Msk

    - -
    -
    - - - - -
    #define CAN_F0R1_FB11_Msk   (0x1UL << CAN_F0R1_FB11_Pos)
    -
    -

    0x00000800

    - -
    -
    - -

    ◆ CAN_F0R1_FB11

    - -
    -
    - - - - -
    #define CAN_F0R1_FB11   CAN_F0R1_FB11_Msk
    -
    -

    Filter bit 11

    - -
    -
    - -

    ◆ CAN_F0R1_FB12_Pos

    - -
    -
    - - - - -
    #define CAN_F0R1_FB12_Pos   (12U)
    -
    - -
    -
    - -

    ◆ CAN_F0R1_FB12_Msk

    - -
    -
    - - - - -
    #define CAN_F0R1_FB12_Msk   (0x1UL << CAN_F0R1_FB12_Pos)
    -
    -

    0x00001000

    - -
    -
    - -

    ◆ CAN_F0R1_FB12

    - -
    -
    - - - - -
    #define CAN_F0R1_FB12   CAN_F0R1_FB12_Msk
    -
    -

    Filter bit 12

    - -
    -
    - -

    ◆ CAN_F0R1_FB13_Pos

    - -
    -
    - - - - -
    #define CAN_F0R1_FB13_Pos   (13U)
    -
    - -
    -
    - -

    ◆ CAN_F0R1_FB13_Msk

    - -
    -
    - - - - -
    #define CAN_F0R1_FB13_Msk   (0x1UL << CAN_F0R1_FB13_Pos)
    -
    -

    0x00002000

    - -
    -
    - -

    ◆ CAN_F0R1_FB13

    - -
    -
    - - - - -
    #define CAN_F0R1_FB13   CAN_F0R1_FB13_Msk
    -
    -

    Filter bit 13

    - -
    -
    - -

    ◆ CAN_F0R1_FB14_Pos

    - -
    -
    - - - - -
    #define CAN_F0R1_FB14_Pos   (14U)
    -
    - -
    -
    - -

    ◆ CAN_F0R1_FB14_Msk

    - -
    -
    - - - - -
    #define CAN_F0R1_FB14_Msk   (0x1UL << CAN_F0R1_FB14_Pos)
    -
    -

    0x00004000

    - -
    -
    - -

    ◆ CAN_F0R1_FB14

    - -
    -
    - - - - -
    #define CAN_F0R1_FB14   CAN_F0R1_FB14_Msk
    -
    -

    Filter bit 14

    - -
    -
    - -

    ◆ CAN_F0R1_FB15_Pos

    - -
    -
    - - - - -
    #define CAN_F0R1_FB15_Pos   (15U)
    -
    - -
    -
    - -

    ◆ CAN_F0R1_FB15_Msk

    - -
    -
    - - - - -
    #define CAN_F0R1_FB15_Msk   (0x1UL << CAN_F0R1_FB15_Pos)
    -
    -

    0x00008000

    - -
    -
    - -

    ◆ CAN_F0R1_FB15

    - -
    -
    - - - - -
    #define CAN_F0R1_FB15   CAN_F0R1_FB15_Msk
    -
    -

    Filter bit 15

    - -
    -
    - -

    ◆ CAN_F0R1_FB16_Pos

    - -
    -
    - - - - -
    #define CAN_F0R1_FB16_Pos   (16U)
    -
    - -
    -
    - -

    ◆ CAN_F0R1_FB16_Msk

    - -
    -
    - - - - -
    #define CAN_F0R1_FB16_Msk   (0x1UL << CAN_F0R1_FB16_Pos)
    -
    -

    0x00010000

    - -
    -
    - -

    ◆ CAN_F0R1_FB16

    - -
    -
    - - - - -
    #define CAN_F0R1_FB16   CAN_F0R1_FB16_Msk
    -
    -

    Filter bit 16

    - -
    -
    - -

    ◆ CAN_F0R1_FB17_Pos

    - -
    -
    - - - - -
    #define CAN_F0R1_FB17_Pos   (17U)
    -
    - -
    -
    - -

    ◆ CAN_F0R1_FB17_Msk

    - -
    -
    - - - - -
    #define CAN_F0R1_FB17_Msk   (0x1UL << CAN_F0R1_FB17_Pos)
    -
    -

    0x00020000

    - -
    -
    - -

    ◆ CAN_F0R1_FB17

    - -
    -
    - - - - -
    #define CAN_F0R1_FB17   CAN_F0R1_FB17_Msk
    -
    -

    Filter bit 17

    - -
    -
    - -

    ◆ CAN_F0R1_FB18_Pos

    - -
    -
    - - - - -
    #define CAN_F0R1_FB18_Pos   (18U)
    -
    - -
    -
    - -

    ◆ CAN_F0R1_FB18_Msk

    - -
    -
    - - - - -
    #define CAN_F0R1_FB18_Msk   (0x1UL << CAN_F0R1_FB18_Pos)
    -
    -

    0x00040000

    - -
    -
    - -

    ◆ CAN_F0R1_FB18

    - -
    -
    - - - - -
    #define CAN_F0R1_FB18   CAN_F0R1_FB18_Msk
    -
    -

    Filter bit 18

    - -
    -
    - -

    ◆ CAN_F0R1_FB19_Pos

    - -
    -
    - - - - -
    #define CAN_F0R1_FB19_Pos   (19U)
    -
    - -
    -
    - -

    ◆ CAN_F0R1_FB19_Msk

    - -
    -
    - - - - -
    #define CAN_F0R1_FB19_Msk   (0x1UL << CAN_F0R1_FB19_Pos)
    -
    -

    0x00080000

    - -
    -
    - -

    ◆ CAN_F0R1_FB19

    - -
    -
    - - - - -
    #define CAN_F0R1_FB19   CAN_F0R1_FB19_Msk
    -
    -

    Filter bit 19

    - -
    -
    - -

    ◆ CAN_F0R1_FB20_Pos

    - -
    -
    - - - - -
    #define CAN_F0R1_FB20_Pos   (20U)
    -
    - -
    -
    - -

    ◆ CAN_F0R1_FB20_Msk

    - -
    -
    - - - - -
    #define CAN_F0R1_FB20_Msk   (0x1UL << CAN_F0R1_FB20_Pos)
    -
    -

    0x00100000

    - -
    -
    - -

    ◆ CAN_F0R1_FB20

    - -
    -
    - - - - -
    #define CAN_F0R1_FB20   CAN_F0R1_FB20_Msk
    -
    -

    Filter bit 20

    - -
    -
    - -

    ◆ CAN_F0R1_FB21_Pos

    - -
    -
    - - - - -
    #define CAN_F0R1_FB21_Pos   (21U)
    -
    - -
    -
    - -

    ◆ CAN_F0R1_FB21_Msk

    - -
    -
    - - - - -
    #define CAN_F0R1_FB21_Msk   (0x1UL << CAN_F0R1_FB21_Pos)
    -
    -

    0x00200000

    - -
    -
    - -

    ◆ CAN_F0R1_FB21

    - -
    -
    - - - - -
    #define CAN_F0R1_FB21   CAN_F0R1_FB21_Msk
    -
    -

    Filter bit 21

    - -
    -
    - -

    ◆ CAN_F0R1_FB22_Pos

    - -
    -
    - - - - -
    #define CAN_F0R1_FB22_Pos   (22U)
    -
    - -
    -
    - -

    ◆ CAN_F0R1_FB22_Msk

    - -
    -
    - - - - -
    #define CAN_F0R1_FB22_Msk   (0x1UL << CAN_F0R1_FB22_Pos)
    -
    -

    0x00400000

    - -
    -
    - -

    ◆ CAN_F0R1_FB22

    - -
    -
    - - - - -
    #define CAN_F0R1_FB22   CAN_F0R1_FB22_Msk
    -
    -

    Filter bit 22

    - -
    -
    - -

    ◆ CAN_F0R1_FB23_Pos

    - -
    -
    - - - - -
    #define CAN_F0R1_FB23_Pos   (23U)
    -
    - -
    -
    - -

    ◆ CAN_F0R1_FB23_Msk

    - -
    -
    - - - - -
    #define CAN_F0R1_FB23_Msk   (0x1UL << CAN_F0R1_FB23_Pos)
    -
    -

    0x00800000

    - -
    -
    - -

    ◆ CAN_F0R1_FB23

    - -
    -
    - - - - -
    #define CAN_F0R1_FB23   CAN_F0R1_FB23_Msk
    -
    -

    Filter bit 23

    - -
    -
    - -

    ◆ CAN_F0R1_FB24_Pos

    - -
    -
    - - - - -
    #define CAN_F0R1_FB24_Pos   (24U)
    -
    - -
    -
    - -

    ◆ CAN_F0R1_FB24_Msk

    - -
    -
    - - - - -
    #define CAN_F0R1_FB24_Msk   (0x1UL << CAN_F0R1_FB24_Pos)
    -
    -

    0x01000000

    - -
    -
    - -

    ◆ CAN_F0R1_FB24

    - -
    -
    - - - - -
    #define CAN_F0R1_FB24   CAN_F0R1_FB24_Msk
    -
    -

    Filter bit 24

    - -
    -
    - -

    ◆ CAN_F0R1_FB25_Pos

    - -
    -
    - - - - -
    #define CAN_F0R1_FB25_Pos   (25U)
    -
    - -
    -
    - -

    ◆ CAN_F0R1_FB25_Msk

    - -
    -
    - - - - -
    #define CAN_F0R1_FB25_Msk   (0x1UL << CAN_F0R1_FB25_Pos)
    -
    -

    0x02000000

    - -
    -
    - -

    ◆ CAN_F0R1_FB25

    - -
    -
    - - - - -
    #define CAN_F0R1_FB25   CAN_F0R1_FB25_Msk
    -
    -

    Filter bit 25

    - -
    -
    - -

    ◆ CAN_F0R1_FB26_Pos

    - -
    -
    - - - - -
    #define CAN_F0R1_FB26_Pos   (26U)
    -
    - -
    -
    - -

    ◆ CAN_F0R1_FB26_Msk

    - -
    -
    - - - - -
    #define CAN_F0R1_FB26_Msk   (0x1UL << CAN_F0R1_FB26_Pos)
    -
    -

    0x04000000

    - -
    -
    - -

    ◆ CAN_F0R1_FB26

    - -
    -
    - - - - -
    #define CAN_F0R1_FB26   CAN_F0R1_FB26_Msk
    -
    -

    Filter bit 26

    - -
    -
    - -

    ◆ CAN_F0R1_FB27_Pos

    - -
    -
    - - - - -
    #define CAN_F0R1_FB27_Pos   (27U)
    -
    - -
    -
    - -

    ◆ CAN_F0R1_FB27_Msk

    - -
    -
    - - - - -
    #define CAN_F0R1_FB27_Msk   (0x1UL << CAN_F0R1_FB27_Pos)
    -
    -

    0x08000000

    - -
    -
    - -

    ◆ CAN_F0R1_FB27

    - -
    -
    - - - - -
    #define CAN_F0R1_FB27   CAN_F0R1_FB27_Msk
    -
    -

    Filter bit 27

    - -
    -
    - -

    ◆ CAN_F0R1_FB28_Pos

    - -
    -
    - - - - -
    #define CAN_F0R1_FB28_Pos   (28U)
    -
    - -
    -
    - -

    ◆ CAN_F0R1_FB28_Msk

    - -
    -
    - - - - -
    #define CAN_F0R1_FB28_Msk   (0x1UL << CAN_F0R1_FB28_Pos)
    -
    -

    0x10000000

    - -
    -
    - -

    ◆ CAN_F0R1_FB28

    - -
    -
    - - - - -
    #define CAN_F0R1_FB28   CAN_F0R1_FB28_Msk
    -
    -

    Filter bit 28

    - -
    -
    - -

    ◆ CAN_F0R1_FB29_Pos

    - -
    -
    - - - - -
    #define CAN_F0R1_FB29_Pos   (29U)
    -
    - -
    -
    - -

    ◆ CAN_F0R1_FB29_Msk

    - -
    -
    - - - - -
    #define CAN_F0R1_FB29_Msk   (0x1UL << CAN_F0R1_FB29_Pos)
    -
    -

    0x20000000

    - -
    -
    - -

    ◆ CAN_F0R1_FB29

    - -
    -
    - - - - -
    #define CAN_F0R1_FB29   CAN_F0R1_FB29_Msk
    -
    -

    Filter bit 29

    - -
    -
    - -

    ◆ CAN_F0R1_FB30_Pos

    - -
    -
    - - - - -
    #define CAN_F0R1_FB30_Pos   (30U)
    -
    - -
    -
    - -

    ◆ CAN_F0R1_FB30_Msk

    - -
    -
    - - - - -
    #define CAN_F0R1_FB30_Msk   (0x1UL << CAN_F0R1_FB30_Pos)
    -
    -

    0x40000000

    - -
    -
    - -

    ◆ CAN_F0R1_FB30

    - -
    -
    - - - - -
    #define CAN_F0R1_FB30   CAN_F0R1_FB30_Msk
    -
    -

    Filter bit 30

    - -
    -
    - -

    ◆ CAN_F0R1_FB31_Pos

    - -
    -
    - - - - -
    #define CAN_F0R1_FB31_Pos   (31U)
    -
    - -
    -
    - -

    ◆ CAN_F0R1_FB31_Msk

    - -
    -
    - - - - -
    #define CAN_F0R1_FB31_Msk   (0x1UL << CAN_F0R1_FB31_Pos)
    -
    -

    0x80000000

    - -
    -
    - -

    ◆ CAN_F0R1_FB31

    - -
    -
    - - - - -
    #define CAN_F0R1_FB31   CAN_F0R1_FB31_Msk
    -
    -

    Filter bit 31

    - -
    -
    - -

    ◆ CAN_F1R1_FB0_Pos

    - -
    -
    - - - - -
    #define CAN_F1R1_FB0_Pos   (0U)
    -
    - -
    -
    - -

    ◆ CAN_F1R1_FB0_Msk

    - -
    -
    - - - - -
    #define CAN_F1R1_FB0_Msk   (0x1UL << CAN_F1R1_FB0_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ CAN_F1R1_FB0

    - -
    -
    - - - - -
    #define CAN_F1R1_FB0   CAN_F1R1_FB0_Msk
    -
    -

    Filter bit 0

    - -
    -
    - -

    ◆ CAN_F1R1_FB1_Pos

    - -
    -
    - - - - -
    #define CAN_F1R1_FB1_Pos   (1U)
    -
    - -
    -
    - -

    ◆ CAN_F1R1_FB1_Msk

    - -
    -
    - - - - -
    #define CAN_F1R1_FB1_Msk   (0x1UL << CAN_F1R1_FB1_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ CAN_F1R1_FB1

    - -
    -
    - - - - -
    #define CAN_F1R1_FB1   CAN_F1R1_FB1_Msk
    -
    -

    Filter bit 1

    - -
    -
    - -

    ◆ CAN_F1R1_FB2_Pos

    - -
    -
    - - - - -
    #define CAN_F1R1_FB2_Pos   (2U)
    -
    - -
    -
    - -

    ◆ CAN_F1R1_FB2_Msk

    - -
    -
    - - - - -
    #define CAN_F1R1_FB2_Msk   (0x1UL << CAN_F1R1_FB2_Pos)
    -
    -

    0x00000004

    - -
    -
    - -

    ◆ CAN_F1R1_FB2

    - -
    -
    - - - - -
    #define CAN_F1R1_FB2   CAN_F1R1_FB2_Msk
    -
    -

    Filter bit 2

    - -
    -
    - -

    ◆ CAN_F1R1_FB3_Pos

    - -
    -
    - - - - -
    #define CAN_F1R1_FB3_Pos   (3U)
    -
    - -
    -
    - -

    ◆ CAN_F1R1_FB3_Msk

    - -
    -
    - - - - -
    #define CAN_F1R1_FB3_Msk   (0x1UL << CAN_F1R1_FB3_Pos)
    -
    -

    0x00000008

    - -
    -
    - -

    ◆ CAN_F1R1_FB3

    - -
    -
    - - - - -
    #define CAN_F1R1_FB3   CAN_F1R1_FB3_Msk
    -
    -

    Filter bit 3

    - -
    -
    - -

    ◆ CAN_F1R1_FB4_Pos

    - -
    -
    - - - - -
    #define CAN_F1R1_FB4_Pos   (4U)
    -
    - -
    -
    - -

    ◆ CAN_F1R1_FB4_Msk

    - -
    -
    - - - - -
    #define CAN_F1R1_FB4_Msk   (0x1UL << CAN_F1R1_FB4_Pos)
    -
    -

    0x00000010

    - -
    -
    - -

    ◆ CAN_F1R1_FB4

    - -
    -
    - - - - -
    #define CAN_F1R1_FB4   CAN_F1R1_FB4_Msk
    -
    -

    Filter bit 4

    - -
    -
    - -

    ◆ CAN_F1R1_FB5_Pos

    - -
    -
    - - - - -
    #define CAN_F1R1_FB5_Pos   (5U)
    -
    - -
    -
    - -

    ◆ CAN_F1R1_FB5_Msk

    - -
    -
    - - - - -
    #define CAN_F1R1_FB5_Msk   (0x1UL << CAN_F1R1_FB5_Pos)
    -
    -

    0x00000020

    - -
    -
    - -

    ◆ CAN_F1R1_FB5

    - -
    -
    - - - - -
    #define CAN_F1R1_FB5   CAN_F1R1_FB5_Msk
    -
    -

    Filter bit 5

    - -
    -
    - -

    ◆ CAN_F1R1_FB6_Pos

    - -
    -
    - - - - -
    #define CAN_F1R1_FB6_Pos   (6U)
    -
    - -
    -
    - -

    ◆ CAN_F1R1_FB6_Msk

    - -
    -
    - - - - -
    #define CAN_F1R1_FB6_Msk   (0x1UL << CAN_F1R1_FB6_Pos)
    -
    -

    0x00000040

    - -
    -
    - -

    ◆ CAN_F1R1_FB6

    - -
    -
    - - - - -
    #define CAN_F1R1_FB6   CAN_F1R1_FB6_Msk
    -
    -

    Filter bit 6

    - -
    -
    - -

    ◆ CAN_F1R1_FB7_Pos

    - -
    -
    - - - - -
    #define CAN_F1R1_FB7_Pos   (7U)
    -
    - -
    -
    - -

    ◆ CAN_F1R1_FB7_Msk

    - -
    -
    - - - - -
    #define CAN_F1R1_FB7_Msk   (0x1UL << CAN_F1R1_FB7_Pos)
    -
    -

    0x00000080

    - -
    -
    - -

    ◆ CAN_F1R1_FB7

    - -
    -
    - - - - -
    #define CAN_F1R1_FB7   CAN_F1R1_FB7_Msk
    -
    -

    Filter bit 7

    - -
    -
    - -

    ◆ CAN_F1R1_FB8_Pos

    - -
    -
    - - - - -
    #define CAN_F1R1_FB8_Pos   (8U)
    -
    - -
    -
    - -

    ◆ CAN_F1R1_FB8_Msk

    - -
    -
    - - - - -
    #define CAN_F1R1_FB8_Msk   (0x1UL << CAN_F1R1_FB8_Pos)
    -
    -

    0x00000100

    - -
    -
    - -

    ◆ CAN_F1R1_FB8

    - -
    -
    - - - - -
    #define CAN_F1R1_FB8   CAN_F1R1_FB8_Msk
    -
    -

    Filter bit 8

    - -
    -
    - -

    ◆ CAN_F1R1_FB9_Pos

    - -
    -
    - - - - -
    #define CAN_F1R1_FB9_Pos   (9U)
    -
    - -
    -
    - -

    ◆ CAN_F1R1_FB9_Msk

    - -
    -
    - - - - -
    #define CAN_F1R1_FB9_Msk   (0x1UL << CAN_F1R1_FB9_Pos)
    -
    -

    0x00000200

    - -
    -
    - -

    ◆ CAN_F1R1_FB9

    - -
    -
    - - - - -
    #define CAN_F1R1_FB9   CAN_F1R1_FB9_Msk
    -
    -

    Filter bit 9

    - -
    -
    - -

    ◆ CAN_F1R1_FB10_Pos

    - -
    -
    - - - - -
    #define CAN_F1R1_FB10_Pos   (10U)
    -
    - -
    -
    - -

    ◆ CAN_F1R1_FB10_Msk

    - -
    -
    - - - - -
    #define CAN_F1R1_FB10_Msk   (0x1UL << CAN_F1R1_FB10_Pos)
    -
    -

    0x00000400

    - -
    -
    - -

    ◆ CAN_F1R1_FB10

    - -
    -
    - - - - -
    #define CAN_F1R1_FB10   CAN_F1R1_FB10_Msk
    -
    -

    Filter bit 10

    - -
    -
    - -

    ◆ CAN_F1R1_FB11_Pos

    - -
    -
    - - - - -
    #define CAN_F1R1_FB11_Pos   (11U)
    -
    - -
    -
    - -

    ◆ CAN_F1R1_FB11_Msk

    - -
    -
    - - - - -
    #define CAN_F1R1_FB11_Msk   (0x1UL << CAN_F1R1_FB11_Pos)
    -
    -

    0x00000800

    - -
    -
    - -

    ◆ CAN_F1R1_FB11

    - -
    -
    - - - - -
    #define CAN_F1R1_FB11   CAN_F1R1_FB11_Msk
    -
    -

    Filter bit 11

    - -
    -
    - -

    ◆ CAN_F1R1_FB12_Pos

    - -
    -
    - - - - -
    #define CAN_F1R1_FB12_Pos   (12U)
    -
    - -
    -
    - -

    ◆ CAN_F1R1_FB12_Msk

    - -
    -
    - - - - -
    #define CAN_F1R1_FB12_Msk   (0x1UL << CAN_F1R1_FB12_Pos)
    -
    -

    0x00001000

    - -
    -
    - -

    ◆ CAN_F1R1_FB12

    - -
    -
    - - - - -
    #define CAN_F1R1_FB12   CAN_F1R1_FB12_Msk
    -
    -

    Filter bit 12

    - -
    -
    - -

    ◆ CAN_F1R1_FB13_Pos

    - -
    -
    - - - - -
    #define CAN_F1R1_FB13_Pos   (13U)
    -
    - -
    -
    - -

    ◆ CAN_F1R1_FB13_Msk

    - -
    -
    - - - - -
    #define CAN_F1R1_FB13_Msk   (0x1UL << CAN_F1R1_FB13_Pos)
    -
    -

    0x00002000

    - -
    -
    - -

    ◆ CAN_F1R1_FB13

    - -
    -
    - - - - -
    #define CAN_F1R1_FB13   CAN_F1R1_FB13_Msk
    -
    -

    Filter bit 13

    - -
    -
    - -

    ◆ CAN_F1R1_FB14_Pos

    - -
    -
    - - - - -
    #define CAN_F1R1_FB14_Pos   (14U)
    -
    - -
    -
    - -

    ◆ CAN_F1R1_FB14_Msk

    - -
    -
    - - - - -
    #define CAN_F1R1_FB14_Msk   (0x1UL << CAN_F1R1_FB14_Pos)
    -
    -

    0x00004000

    - -
    -
    - -

    ◆ CAN_F1R1_FB14

    - -
    -
    - - - - -
    #define CAN_F1R1_FB14   CAN_F1R1_FB14_Msk
    -
    -

    Filter bit 14

    - -
    -
    - -

    ◆ CAN_F1R1_FB15_Pos

    - -
    -
    - - - - -
    #define CAN_F1R1_FB15_Pos   (15U)
    -
    - -
    -
    - -

    ◆ CAN_F1R1_FB15_Msk

    - -
    -
    - - - - -
    #define CAN_F1R1_FB15_Msk   (0x1UL << CAN_F1R1_FB15_Pos)
    -
    -

    0x00008000

    - -
    -
    - -

    ◆ CAN_F1R1_FB15

    - -
    -
    - - - - -
    #define CAN_F1R1_FB15   CAN_F1R1_FB15_Msk
    -
    -

    Filter bit 15

    - -
    -
    - -

    ◆ CAN_F1R1_FB16_Pos

    - -
    -
    - - - - -
    #define CAN_F1R1_FB16_Pos   (16U)
    -
    - -
    -
    - -

    ◆ CAN_F1R1_FB16_Msk

    - -
    -
    - - - - -
    #define CAN_F1R1_FB16_Msk   (0x1UL << CAN_F1R1_FB16_Pos)
    -
    -

    0x00010000

    - -
    -
    - -

    ◆ CAN_F1R1_FB16

    - -
    -
    - - - - -
    #define CAN_F1R1_FB16   CAN_F1R1_FB16_Msk
    -
    -

    Filter bit 16

    - -
    -
    - -

    ◆ CAN_F1R1_FB17_Pos

    - -
    -
    - - - - -
    #define CAN_F1R1_FB17_Pos   (17U)
    -
    - -
    -
    - -

    ◆ CAN_F1R1_FB17_Msk

    - -
    -
    - - - - -
    #define CAN_F1R1_FB17_Msk   (0x1UL << CAN_F1R1_FB17_Pos)
    -
    -

    0x00020000

    - -
    -
    - -

    ◆ CAN_F1R1_FB17

    - -
    -
    - - - - -
    #define CAN_F1R1_FB17   CAN_F1R1_FB17_Msk
    -
    -

    Filter bit 17

    - -
    -
    - -

    ◆ CAN_F1R1_FB18_Pos

    - -
    -
    - - - - -
    #define CAN_F1R1_FB18_Pos   (18U)
    -
    - -
    -
    - -

    ◆ CAN_F1R1_FB18_Msk

    - -
    -
    - - - - -
    #define CAN_F1R1_FB18_Msk   (0x1UL << CAN_F1R1_FB18_Pos)
    -
    -

    0x00040000

    - -
    -
    - -

    ◆ CAN_F1R1_FB18

    - -
    -
    - - - - -
    #define CAN_F1R1_FB18   CAN_F1R1_FB18_Msk
    -
    -

    Filter bit 18

    - -
    -
    - -

    ◆ CAN_F1R1_FB19_Pos

    - -
    -
    - - - - -
    #define CAN_F1R1_FB19_Pos   (19U)
    -
    - -
    -
    - -

    ◆ CAN_F1R1_FB19_Msk

    - -
    -
    - - - - -
    #define CAN_F1R1_FB19_Msk   (0x1UL << CAN_F1R1_FB19_Pos)
    -
    -

    0x00080000

    - -
    -
    - -

    ◆ CAN_F1R1_FB19

    - -
    -
    - - - - -
    #define CAN_F1R1_FB19   CAN_F1R1_FB19_Msk
    -
    -

    Filter bit 19

    - -
    -
    - -

    ◆ CAN_F1R1_FB20_Pos

    - -
    -
    - - - - -
    #define CAN_F1R1_FB20_Pos   (20U)
    -
    - -
    -
    - -

    ◆ CAN_F1R1_FB20_Msk

    - -
    -
    - - - - -
    #define CAN_F1R1_FB20_Msk   (0x1UL << CAN_F1R1_FB20_Pos)
    -
    -

    0x00100000

    - -
    -
    - -

    ◆ CAN_F1R1_FB20

    - -
    -
    - - - - -
    #define CAN_F1R1_FB20   CAN_F1R1_FB20_Msk
    -
    -

    Filter bit 20

    - -
    -
    - -

    ◆ CAN_F1R1_FB21_Pos

    - -
    -
    - - - - -
    #define CAN_F1R1_FB21_Pos   (21U)
    -
    - -
    -
    - -

    ◆ CAN_F1R1_FB21_Msk

    - -
    -
    - - - - -
    #define CAN_F1R1_FB21_Msk   (0x1UL << CAN_F1R1_FB21_Pos)
    -
    -

    0x00200000

    - -
    -
    - -

    ◆ CAN_F1R1_FB21

    - -
    -
    - - - - -
    #define CAN_F1R1_FB21   CAN_F1R1_FB21_Msk
    -
    -

    Filter bit 21

    - -
    -
    - -

    ◆ CAN_F1R1_FB22_Pos

    - -
    -
    - - - - -
    #define CAN_F1R1_FB22_Pos   (22U)
    -
    - -
    -
    - -

    ◆ CAN_F1R1_FB22_Msk

    - -
    -
    - - - - -
    #define CAN_F1R1_FB22_Msk   (0x1UL << CAN_F1R1_FB22_Pos)
    -
    -

    0x00400000

    - -
    -
    - -

    ◆ CAN_F1R1_FB22

    - -
    -
    - - - - -
    #define CAN_F1R1_FB22   CAN_F1R1_FB22_Msk
    -
    -

    Filter bit 22

    - -
    -
    - -

    ◆ CAN_F1R1_FB23_Pos

    - -
    -
    - - - - -
    #define CAN_F1R1_FB23_Pos   (23U)
    -
    - -
    -
    - -

    ◆ CAN_F1R1_FB23_Msk

    - -
    -
    - - - - -
    #define CAN_F1R1_FB23_Msk   (0x1UL << CAN_F1R1_FB23_Pos)
    -
    -

    0x00800000

    - -
    -
    - -

    ◆ CAN_F1R1_FB23

    - -
    -
    - - - - -
    #define CAN_F1R1_FB23   CAN_F1R1_FB23_Msk
    -
    -

    Filter bit 23

    - -
    -
    - -

    ◆ CAN_F1R1_FB24_Pos

    - -
    -
    - - - - -
    #define CAN_F1R1_FB24_Pos   (24U)
    -
    - -
    -
    - -

    ◆ CAN_F1R1_FB24_Msk

    - -
    -
    - - - - -
    #define CAN_F1R1_FB24_Msk   (0x1UL << CAN_F1R1_FB24_Pos)
    -
    -

    0x01000000

    - -
    -
    - -

    ◆ CAN_F1R1_FB24

    - -
    -
    - - - - -
    #define CAN_F1R1_FB24   CAN_F1R1_FB24_Msk
    -
    -

    Filter bit 24

    - -
    -
    - -

    ◆ CAN_F1R1_FB25_Pos

    - -
    -
    - - - - -
    #define CAN_F1R1_FB25_Pos   (25U)
    -
    - -
    -
    - -

    ◆ CAN_F1R1_FB25_Msk

    - -
    -
    - - - - -
    #define CAN_F1R1_FB25_Msk   (0x1UL << CAN_F1R1_FB25_Pos)
    -
    -

    0x02000000

    - -
    -
    - -

    ◆ CAN_F1R1_FB25

    - -
    -
    - - - - -
    #define CAN_F1R1_FB25   CAN_F1R1_FB25_Msk
    -
    -

    Filter bit 25

    - -
    -
    - -

    ◆ CAN_F1R1_FB26_Pos

    - -
    -
    - - - - -
    #define CAN_F1R1_FB26_Pos   (26U)
    -
    - -
    -
    - -

    ◆ CAN_F1R1_FB26_Msk

    - -
    -
    - - - - -
    #define CAN_F1R1_FB26_Msk   (0x1UL << CAN_F1R1_FB26_Pos)
    -
    -

    0x04000000

    - -
    -
    - -

    ◆ CAN_F1R1_FB26

    - -
    -
    - - - - -
    #define CAN_F1R1_FB26   CAN_F1R1_FB26_Msk
    -
    -

    Filter bit 26

    - -
    -
    - -

    ◆ CAN_F1R1_FB27_Pos

    - -
    -
    - - - - -
    #define CAN_F1R1_FB27_Pos   (27U)
    -
    - -
    -
    - -

    ◆ CAN_F1R1_FB27_Msk

    - -
    -
    - - - - -
    #define CAN_F1R1_FB27_Msk   (0x1UL << CAN_F1R1_FB27_Pos)
    -
    -

    0x08000000

    - -
    -
    - -

    ◆ CAN_F1R1_FB27

    - -
    -
    - - - - -
    #define CAN_F1R1_FB27   CAN_F1R1_FB27_Msk
    -
    -

    Filter bit 27

    - -
    -
    - -

    ◆ CAN_F1R1_FB28_Pos

    - -
    -
    - - - - -
    #define CAN_F1R1_FB28_Pos   (28U)
    -
    - -
    -
    - -

    ◆ CAN_F1R1_FB28_Msk

    - -
    -
    - - - - -
    #define CAN_F1R1_FB28_Msk   (0x1UL << CAN_F1R1_FB28_Pos)
    -
    -

    0x10000000

    - -
    -
    - -

    ◆ CAN_F1R1_FB28

    - -
    -
    - - - - -
    #define CAN_F1R1_FB28   CAN_F1R1_FB28_Msk
    -
    -

    Filter bit 28

    - -
    -
    - -

    ◆ CAN_F1R1_FB29_Pos

    - -
    -
    - - - - -
    #define CAN_F1R1_FB29_Pos   (29U)
    -
    - -
    -
    - -

    ◆ CAN_F1R1_FB29_Msk

    - -
    -
    - - - - -
    #define CAN_F1R1_FB29_Msk   (0x1UL << CAN_F1R1_FB29_Pos)
    -
    -

    0x20000000

    - -
    -
    - -

    ◆ CAN_F1R1_FB29

    - -
    -
    - - - - -
    #define CAN_F1R1_FB29   CAN_F1R1_FB29_Msk
    -
    -

    Filter bit 29

    - -
    -
    - -

    ◆ CAN_F1R1_FB30_Pos

    - -
    -
    - - - - -
    #define CAN_F1R1_FB30_Pos   (30U)
    -
    - -
    -
    - -

    ◆ CAN_F1R1_FB30_Msk

    - -
    -
    - - - - -
    #define CAN_F1R1_FB30_Msk   (0x1UL << CAN_F1R1_FB30_Pos)
    -
    -

    0x40000000

    - -
    -
    - -

    ◆ CAN_F1R1_FB30

    - -
    -
    - - - - -
    #define CAN_F1R1_FB30   CAN_F1R1_FB30_Msk
    -
    -

    Filter bit 30

    - -
    -
    - -

    ◆ CAN_F1R1_FB31_Pos

    - -
    -
    - - - - -
    #define CAN_F1R1_FB31_Pos   (31U)
    -
    - -
    -
    - -

    ◆ CAN_F1R1_FB31_Msk

    - -
    -
    - - - - -
    #define CAN_F1R1_FB31_Msk   (0x1UL << CAN_F1R1_FB31_Pos)
    -
    -

    0x80000000

    - -
    -
    - -

    ◆ CAN_F1R1_FB31

    - -
    -
    - - - - -
    #define CAN_F1R1_FB31   CAN_F1R1_FB31_Msk
    -
    -

    Filter bit 31

    - -
    -
    - -

    ◆ CAN_F2R1_FB0_Pos

    - -
    -
    - - - - -
    #define CAN_F2R1_FB0_Pos   (0U)
    -
    - -
    -
    - -

    ◆ CAN_F2R1_FB0_Msk

    - -
    -
    - - - - -
    #define CAN_F2R1_FB0_Msk   (0x1UL << CAN_F2R1_FB0_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ CAN_F2R1_FB0

    - -
    -
    - - - - -
    #define CAN_F2R1_FB0   CAN_F2R1_FB0_Msk
    -
    -

    Filter bit 0

    - -
    -
    - -

    ◆ CAN_F2R1_FB1_Pos

    - -
    -
    - - - - -
    #define CAN_F2R1_FB1_Pos   (1U)
    -
    - -
    -
    - -

    ◆ CAN_F2R1_FB1_Msk

    - -
    -
    - - - - -
    #define CAN_F2R1_FB1_Msk   (0x1UL << CAN_F2R1_FB1_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ CAN_F2R1_FB1

    - -
    -
    - - - - -
    #define CAN_F2R1_FB1   CAN_F2R1_FB1_Msk
    -
    -

    Filter bit 1

    - -
    -
    - -

    ◆ CAN_F2R1_FB2_Pos

    - -
    -
    - - - - -
    #define CAN_F2R1_FB2_Pos   (2U)
    -
    - -
    -
    - -

    ◆ CAN_F2R1_FB2_Msk

    - -
    -
    - - - - -
    #define CAN_F2R1_FB2_Msk   (0x1UL << CAN_F2R1_FB2_Pos)
    -
    -

    0x00000004

    - -
    -
    - -

    ◆ CAN_F2R1_FB2

    - -
    -
    - - - - -
    #define CAN_F2R1_FB2   CAN_F2R1_FB2_Msk
    -
    -

    Filter bit 2

    - -
    -
    - -

    ◆ CAN_F2R1_FB3_Pos

    - -
    -
    - - - - -
    #define CAN_F2R1_FB3_Pos   (3U)
    -
    - -
    -
    - -

    ◆ CAN_F2R1_FB3_Msk

    - -
    -
    - - - - -
    #define CAN_F2R1_FB3_Msk   (0x1UL << CAN_F2R1_FB3_Pos)
    -
    -

    0x00000008

    - -
    -
    - -

    ◆ CAN_F2R1_FB3

    - -
    -
    - - - - -
    #define CAN_F2R1_FB3   CAN_F2R1_FB3_Msk
    -
    -

    Filter bit 3

    - -
    -
    - -

    ◆ CAN_F2R1_FB4_Pos

    - -
    -
    - - - - -
    #define CAN_F2R1_FB4_Pos   (4U)
    -
    - -
    -
    - -

    ◆ CAN_F2R1_FB4_Msk

    - -
    -
    - - - - -
    #define CAN_F2R1_FB4_Msk   (0x1UL << CAN_F2R1_FB4_Pos)
    -
    -

    0x00000010

    - -
    -
    - -

    ◆ CAN_F2R1_FB4

    - -
    -
    - - - - -
    #define CAN_F2R1_FB4   CAN_F2R1_FB4_Msk
    -
    -

    Filter bit 4

    - -
    -
    - -

    ◆ CAN_F2R1_FB5_Pos

    - -
    -
    - - - - -
    #define CAN_F2R1_FB5_Pos   (5U)
    -
    - -
    -
    - -

    ◆ CAN_F2R1_FB5_Msk

    - -
    -
    - - - - -
    #define CAN_F2R1_FB5_Msk   (0x1UL << CAN_F2R1_FB5_Pos)
    -
    -

    0x00000020

    - -
    -
    - -

    ◆ CAN_F2R1_FB5

    - -
    -
    - - - - -
    #define CAN_F2R1_FB5   CAN_F2R1_FB5_Msk
    -
    -

    Filter bit 5

    - -
    -
    - -

    ◆ CAN_F2R1_FB6_Pos

    - -
    -
    - - - - -
    #define CAN_F2R1_FB6_Pos   (6U)
    -
    - -
    -
    - -

    ◆ CAN_F2R1_FB6_Msk

    - -
    -
    - - - - -
    #define CAN_F2R1_FB6_Msk   (0x1UL << CAN_F2R1_FB6_Pos)
    -
    -

    0x00000040

    - -
    -
    - -

    ◆ CAN_F2R1_FB6

    - -
    -
    - - - - -
    #define CAN_F2R1_FB6   CAN_F2R1_FB6_Msk
    -
    -

    Filter bit 6

    - -
    -
    - -

    ◆ CAN_F2R1_FB7_Pos

    - -
    -
    - - - - -
    #define CAN_F2R1_FB7_Pos   (7U)
    -
    - -
    -
    - -

    ◆ CAN_F2R1_FB7_Msk

    - -
    -
    - - - - -
    #define CAN_F2R1_FB7_Msk   (0x1UL << CAN_F2R1_FB7_Pos)
    -
    -

    0x00000080

    - -
    -
    - -

    ◆ CAN_F2R1_FB7

    - -
    -
    - - - - -
    #define CAN_F2R1_FB7   CAN_F2R1_FB7_Msk
    -
    -

    Filter bit 7

    - -
    -
    - -

    ◆ CAN_F2R1_FB8_Pos

    - -
    -
    - - - - -
    #define CAN_F2R1_FB8_Pos   (8U)
    -
    - -
    -
    - -

    ◆ CAN_F2R1_FB8_Msk

    - -
    -
    - - - - -
    #define CAN_F2R1_FB8_Msk   (0x1UL << CAN_F2R1_FB8_Pos)
    -
    -

    0x00000100

    - -
    -
    - -

    ◆ CAN_F2R1_FB8

    - -
    -
    - - - - -
    #define CAN_F2R1_FB8   CAN_F2R1_FB8_Msk
    -
    -

    Filter bit 8

    - -
    -
    - -

    ◆ CAN_F2R1_FB9_Pos

    - -
    -
    - - - - -
    #define CAN_F2R1_FB9_Pos   (9U)
    -
    - -
    -
    - -

    ◆ CAN_F2R1_FB9_Msk

    - -
    -
    - - - - -
    #define CAN_F2R1_FB9_Msk   (0x1UL << CAN_F2R1_FB9_Pos)
    -
    -

    0x00000200

    - -
    -
    - -

    ◆ CAN_F2R1_FB9

    - -
    -
    - - - - -
    #define CAN_F2R1_FB9   CAN_F2R1_FB9_Msk
    -
    -

    Filter bit 9

    - -
    -
    - -

    ◆ CAN_F2R1_FB10_Pos

    - -
    -
    - - - - -
    #define CAN_F2R1_FB10_Pos   (10U)
    -
    - -
    -
    - -

    ◆ CAN_F2R1_FB10_Msk

    - -
    -
    - - - - -
    #define CAN_F2R1_FB10_Msk   (0x1UL << CAN_F2R1_FB10_Pos)
    -
    -

    0x00000400

    - -
    -
    - -

    ◆ CAN_F2R1_FB10

    - -
    -
    - - - - -
    #define CAN_F2R1_FB10   CAN_F2R1_FB10_Msk
    -
    -

    Filter bit 10

    - -
    -
    - -

    ◆ CAN_F2R1_FB11_Pos

    - -
    -
    - - - - -
    #define CAN_F2R1_FB11_Pos   (11U)
    -
    - -
    -
    - -

    ◆ CAN_F2R1_FB11_Msk

    - -
    -
    - - - - -
    #define CAN_F2R1_FB11_Msk   (0x1UL << CAN_F2R1_FB11_Pos)
    -
    -

    0x00000800

    - -
    -
    - -

    ◆ CAN_F2R1_FB11

    - -
    -
    - - - - -
    #define CAN_F2R1_FB11   CAN_F2R1_FB11_Msk
    -
    -

    Filter bit 11

    - -
    -
    - -

    ◆ CAN_F2R1_FB12_Pos

    - -
    -
    - - - - -
    #define CAN_F2R1_FB12_Pos   (12U)
    -
    - -
    -
    - -

    ◆ CAN_F2R1_FB12_Msk

    - -
    -
    - - - - -
    #define CAN_F2R1_FB12_Msk   (0x1UL << CAN_F2R1_FB12_Pos)
    -
    -

    0x00001000

    - -
    -
    - -

    ◆ CAN_F2R1_FB12

    - -
    -
    - - - - -
    #define CAN_F2R1_FB12   CAN_F2R1_FB12_Msk
    -
    -

    Filter bit 12

    - -
    -
    - -

    ◆ CAN_F2R1_FB13_Pos

    - -
    -
    - - - - -
    #define CAN_F2R1_FB13_Pos   (13U)
    -
    - -
    -
    - -

    ◆ CAN_F2R1_FB13_Msk

    - -
    -
    - - - - -
    #define CAN_F2R1_FB13_Msk   (0x1UL << CAN_F2R1_FB13_Pos)
    -
    -

    0x00002000

    - -
    -
    - -

    ◆ CAN_F2R1_FB13

    - -
    -
    - - - - -
    #define CAN_F2R1_FB13   CAN_F2R1_FB13_Msk
    -
    -

    Filter bit 13

    - -
    -
    - -

    ◆ CAN_F2R1_FB14_Pos

    - -
    -
    - - - - -
    #define CAN_F2R1_FB14_Pos   (14U)
    -
    - -
    -
    - -

    ◆ CAN_F2R1_FB14_Msk

    - -
    -
    - - - - -
    #define CAN_F2R1_FB14_Msk   (0x1UL << CAN_F2R1_FB14_Pos)
    -
    -

    0x00004000

    - -
    -
    - -

    ◆ CAN_F2R1_FB14

    - -
    -
    - - - - -
    #define CAN_F2R1_FB14   CAN_F2R1_FB14_Msk
    -
    -

    Filter bit 14

    - -
    -
    - -

    ◆ CAN_F2R1_FB15_Pos

    - -
    -
    - - - - -
    #define CAN_F2R1_FB15_Pos   (15U)
    -
    - -
    -
    - -

    ◆ CAN_F2R1_FB15_Msk

    - -
    -
    - - - - -
    #define CAN_F2R1_FB15_Msk   (0x1UL << CAN_F2R1_FB15_Pos)
    -
    -

    0x00008000

    - -
    -
    - -

    ◆ CAN_F2R1_FB15

    - -
    -
    - - - - -
    #define CAN_F2R1_FB15   CAN_F2R1_FB15_Msk
    -
    -

    Filter bit 15

    - -
    -
    - -

    ◆ CAN_F2R1_FB16_Pos

    - -
    -
    - - - - -
    #define CAN_F2R1_FB16_Pos   (16U)
    -
    - -
    -
    - -

    ◆ CAN_F2R1_FB16_Msk

    - -
    -
    - - - - -
    #define CAN_F2R1_FB16_Msk   (0x1UL << CAN_F2R1_FB16_Pos)
    -
    -

    0x00010000

    - -
    -
    - -

    ◆ CAN_F2R1_FB16

    - -
    -
    - - - - -
    #define CAN_F2R1_FB16   CAN_F2R1_FB16_Msk
    -
    -

    Filter bit 16

    - -
    -
    - -

    ◆ CAN_F2R1_FB17_Pos

    - -
    -
    - - - - -
    #define CAN_F2R1_FB17_Pos   (17U)
    -
    - -
    -
    - -

    ◆ CAN_F2R1_FB17_Msk

    - -
    -
    - - - - -
    #define CAN_F2R1_FB17_Msk   (0x1UL << CAN_F2R1_FB17_Pos)
    -
    -

    0x00020000

    - -
    -
    - -

    ◆ CAN_F2R1_FB17

    - -
    -
    - - - - -
    #define CAN_F2R1_FB17   CAN_F2R1_FB17_Msk
    -
    -

    Filter bit 17

    - -
    -
    - -

    ◆ CAN_F2R1_FB18_Pos

    - -
    -
    - - - - -
    #define CAN_F2R1_FB18_Pos   (18U)
    -
    - -
    -
    - -

    ◆ CAN_F2R1_FB18_Msk

    - -
    -
    - - - - -
    #define CAN_F2R1_FB18_Msk   (0x1UL << CAN_F2R1_FB18_Pos)
    -
    -

    0x00040000

    - -
    -
    - -

    ◆ CAN_F2R1_FB18

    - -
    -
    - - - - -
    #define CAN_F2R1_FB18   CAN_F2R1_FB18_Msk
    -
    -

    Filter bit 18

    - -
    -
    - -

    ◆ CAN_F2R1_FB19_Pos

    - -
    -
    - - - - -
    #define CAN_F2R1_FB19_Pos   (19U)
    -
    - -
    -
    - -

    ◆ CAN_F2R1_FB19_Msk

    - -
    -
    - - - - -
    #define CAN_F2R1_FB19_Msk   (0x1UL << CAN_F2R1_FB19_Pos)
    -
    -

    0x00080000

    - -
    -
    - -

    ◆ CAN_F2R1_FB19

    - -
    -
    - - - - -
    #define CAN_F2R1_FB19   CAN_F2R1_FB19_Msk
    -
    -

    Filter bit 19

    - -
    -
    - -

    ◆ CAN_F2R1_FB20_Pos

    - -
    -
    - - - - -
    #define CAN_F2R1_FB20_Pos   (20U)
    -
    - -
    -
    - -

    ◆ CAN_F2R1_FB20_Msk

    - -
    -
    - - - - -
    #define CAN_F2R1_FB20_Msk   (0x1UL << CAN_F2R1_FB20_Pos)
    -
    -

    0x00100000

    - -
    -
    - -

    ◆ CAN_F2R1_FB20

    - -
    -
    - - - - -
    #define CAN_F2R1_FB20   CAN_F2R1_FB20_Msk
    -
    -

    Filter bit 20

    - -
    -
    - -

    ◆ CAN_F2R1_FB21_Pos

    - -
    -
    - - - - -
    #define CAN_F2R1_FB21_Pos   (21U)
    -
    - -
    -
    - -

    ◆ CAN_F2R1_FB21_Msk

    - -
    -
    - - - - -
    #define CAN_F2R1_FB21_Msk   (0x1UL << CAN_F2R1_FB21_Pos)
    -
    -

    0x00200000

    - -
    -
    - -

    ◆ CAN_F2R1_FB21

    - -
    -
    - - - - -
    #define CAN_F2R1_FB21   CAN_F2R1_FB21_Msk
    -
    -

    Filter bit 21

    - -
    -
    - -

    ◆ CAN_F2R1_FB22_Pos

    - -
    -
    - - - - -
    #define CAN_F2R1_FB22_Pos   (22U)
    -
    - -
    -
    - -

    ◆ CAN_F2R1_FB22_Msk

    - -
    -
    - - - - -
    #define CAN_F2R1_FB22_Msk   (0x1UL << CAN_F2R1_FB22_Pos)
    -
    -

    0x00400000

    - -
    -
    - -

    ◆ CAN_F2R1_FB22

    - -
    -
    - - - - -
    #define CAN_F2R1_FB22   CAN_F2R1_FB22_Msk
    -
    -

    Filter bit 22

    - -
    -
    - -

    ◆ CAN_F2R1_FB23_Pos

    - -
    -
    - - - - -
    #define CAN_F2R1_FB23_Pos   (23U)
    -
    - -
    -
    - -

    ◆ CAN_F2R1_FB23_Msk

    - -
    -
    - - - - -
    #define CAN_F2R1_FB23_Msk   (0x1UL << CAN_F2R1_FB23_Pos)
    -
    -

    0x00800000

    - -
    -
    - -

    ◆ CAN_F2R1_FB23

    - -
    -
    - - - - -
    #define CAN_F2R1_FB23   CAN_F2R1_FB23_Msk
    -
    -

    Filter bit 23

    - -
    -
    - -

    ◆ CAN_F2R1_FB24_Pos

    - -
    -
    - - - - -
    #define CAN_F2R1_FB24_Pos   (24U)
    -
    - -
    -
    - -

    ◆ CAN_F2R1_FB24_Msk

    - -
    -
    - - - - -
    #define CAN_F2R1_FB24_Msk   (0x1UL << CAN_F2R1_FB24_Pos)
    -
    -

    0x01000000

    - -
    -
    - -

    ◆ CAN_F2R1_FB24

    - -
    -
    - - - - -
    #define CAN_F2R1_FB24   CAN_F2R1_FB24_Msk
    -
    -

    Filter bit 24

    - -
    -
    - -

    ◆ CAN_F2R1_FB25_Pos

    - -
    -
    - - - - -
    #define CAN_F2R1_FB25_Pos   (25U)
    -
    - -
    -
    - -

    ◆ CAN_F2R1_FB25_Msk

    - -
    -
    - - - - -
    #define CAN_F2R1_FB25_Msk   (0x1UL << CAN_F2R1_FB25_Pos)
    -
    -

    0x02000000

    - -
    -
    - -

    ◆ CAN_F2R1_FB25

    - -
    -
    - - - - -
    #define CAN_F2R1_FB25   CAN_F2R1_FB25_Msk
    -
    -

    Filter bit 25

    - -
    -
    - -

    ◆ CAN_F2R1_FB26_Pos

    - -
    -
    - - - - -
    #define CAN_F2R1_FB26_Pos   (26U)
    -
    - -
    -
    - -

    ◆ CAN_F2R1_FB26_Msk

    - -
    -
    - - - - -
    #define CAN_F2R1_FB26_Msk   (0x1UL << CAN_F2R1_FB26_Pos)
    -
    -

    0x04000000

    - -
    -
    - -

    ◆ CAN_F2R1_FB26

    - -
    -
    - - - - -
    #define CAN_F2R1_FB26   CAN_F2R1_FB26_Msk
    -
    -

    Filter bit 26

    - -
    -
    - -

    ◆ CAN_F2R1_FB27_Pos

    - -
    -
    - - - - -
    #define CAN_F2R1_FB27_Pos   (27U)
    -
    - -
    -
    - -

    ◆ CAN_F2R1_FB27_Msk

    - -
    -
    - - - - -
    #define CAN_F2R1_FB27_Msk   (0x1UL << CAN_F2R1_FB27_Pos)
    -
    -

    0x08000000

    - -
    -
    - -

    ◆ CAN_F2R1_FB27

    - -
    -
    - - - - -
    #define CAN_F2R1_FB27   CAN_F2R1_FB27_Msk
    -
    -

    Filter bit 27

    - -
    -
    - -

    ◆ CAN_F2R1_FB28_Pos

    - -
    -
    - - - - -
    #define CAN_F2R1_FB28_Pos   (28U)
    -
    - -
    -
    - -

    ◆ CAN_F2R1_FB28_Msk

    - -
    -
    - - - - -
    #define CAN_F2R1_FB28_Msk   (0x1UL << CAN_F2R1_FB28_Pos)
    -
    -

    0x10000000

    - -
    -
    - -

    ◆ CAN_F2R1_FB28

    - -
    -
    - - - - -
    #define CAN_F2R1_FB28   CAN_F2R1_FB28_Msk
    -
    -

    Filter bit 28

    - -
    -
    - -

    ◆ CAN_F2R1_FB29_Pos

    - -
    -
    - - - - -
    #define CAN_F2R1_FB29_Pos   (29U)
    -
    - -
    -
    - -

    ◆ CAN_F2R1_FB29_Msk

    - -
    -
    - - - - -
    #define CAN_F2R1_FB29_Msk   (0x1UL << CAN_F2R1_FB29_Pos)
    -
    -

    0x20000000

    - -
    -
    - -

    ◆ CAN_F2R1_FB29

    - -
    -
    - - - - -
    #define CAN_F2R1_FB29   CAN_F2R1_FB29_Msk
    -
    -

    Filter bit 29

    - -
    -
    - -

    ◆ CAN_F2R1_FB30_Pos

    - -
    -
    - - - - -
    #define CAN_F2R1_FB30_Pos   (30U)
    -
    - -
    -
    - -

    ◆ CAN_F2R1_FB30_Msk

    - -
    -
    - - - - -
    #define CAN_F2R1_FB30_Msk   (0x1UL << CAN_F2R1_FB30_Pos)
    -
    -

    0x40000000

    - -
    -
    - -

    ◆ CAN_F2R1_FB30

    - -
    -
    - - - - -
    #define CAN_F2R1_FB30   CAN_F2R1_FB30_Msk
    -
    -

    Filter bit 30

    - -
    -
    - -

    ◆ CAN_F2R1_FB31_Pos

    - -
    -
    - - - - -
    #define CAN_F2R1_FB31_Pos   (31U)
    -
    - -
    -
    - -

    ◆ CAN_F2R1_FB31_Msk

    - -
    -
    - - - - -
    #define CAN_F2R1_FB31_Msk   (0x1UL << CAN_F2R1_FB31_Pos)
    -
    -

    0x80000000

    - -
    -
    - -

    ◆ CAN_F2R1_FB31

    - -
    -
    - - - - -
    #define CAN_F2R1_FB31   CAN_F2R1_FB31_Msk
    -
    -

    Filter bit 31

    - -
    -
    - -

    ◆ CAN_F3R1_FB0_Pos

    - -
    -
    - - - - -
    #define CAN_F3R1_FB0_Pos   (0U)
    -
    - -
    -
    - -

    ◆ CAN_F3R1_FB0_Msk

    - -
    -
    - - - - -
    #define CAN_F3R1_FB0_Msk   (0x1UL << CAN_F3R1_FB0_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ CAN_F3R1_FB0

    - -
    -
    - - - - -
    #define CAN_F3R1_FB0   CAN_F3R1_FB0_Msk
    -
    -

    Filter bit 0

    - -
    -
    - -

    ◆ CAN_F3R1_FB1_Pos

    - -
    -
    - - - - -
    #define CAN_F3R1_FB1_Pos   (1U)
    -
    - -
    -
    - -

    ◆ CAN_F3R1_FB1_Msk

    - -
    -
    - - - - -
    #define CAN_F3R1_FB1_Msk   (0x1UL << CAN_F3R1_FB1_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ CAN_F3R1_FB1

    - -
    -
    - - - - -
    #define CAN_F3R1_FB1   CAN_F3R1_FB1_Msk
    -
    -

    Filter bit 1

    - -
    -
    - -

    ◆ CAN_F3R1_FB2_Pos

    - -
    -
    - - - - -
    #define CAN_F3R1_FB2_Pos   (2U)
    -
    - -
    -
    - -

    ◆ CAN_F3R1_FB2_Msk

    - -
    -
    - - - - -
    #define CAN_F3R1_FB2_Msk   (0x1UL << CAN_F3R1_FB2_Pos)
    -
    -

    0x00000004

    - -
    -
    - -

    ◆ CAN_F3R1_FB2

    - -
    -
    - - - - -
    #define CAN_F3R1_FB2   CAN_F3R1_FB2_Msk
    -
    -

    Filter bit 2

    - -
    -
    - -

    ◆ CAN_F3R1_FB3_Pos

    - -
    -
    - - - - -
    #define CAN_F3R1_FB3_Pos   (3U)
    -
    - -
    -
    - -

    ◆ CAN_F3R1_FB3_Msk

    - -
    -
    - - - - -
    #define CAN_F3R1_FB3_Msk   (0x1UL << CAN_F3R1_FB3_Pos)
    -
    -

    0x00000008

    - -
    -
    - -

    ◆ CAN_F3R1_FB3

    - -
    -
    - - - - -
    #define CAN_F3R1_FB3   CAN_F3R1_FB3_Msk
    -
    -

    Filter bit 3

    - -
    -
    - -

    ◆ CAN_F3R1_FB4_Pos

    - -
    -
    - - - - -
    #define CAN_F3R1_FB4_Pos   (4U)
    -
    - -
    -
    - -

    ◆ CAN_F3R1_FB4_Msk

    - -
    -
    - - - - -
    #define CAN_F3R1_FB4_Msk   (0x1UL << CAN_F3R1_FB4_Pos)
    -
    -

    0x00000010

    - -
    -
    - -

    ◆ CAN_F3R1_FB4

    - -
    -
    - - - - -
    #define CAN_F3R1_FB4   CAN_F3R1_FB4_Msk
    -
    -

    Filter bit 4

    - -
    -
    - -

    ◆ CAN_F3R1_FB5_Pos

    - -
    -
    - - - - -
    #define CAN_F3R1_FB5_Pos   (5U)
    -
    - -
    -
    - -

    ◆ CAN_F3R1_FB5_Msk

    - -
    -
    - - - - -
    #define CAN_F3R1_FB5_Msk   (0x1UL << CAN_F3R1_FB5_Pos)
    -
    -

    0x00000020

    - -
    -
    - -

    ◆ CAN_F3R1_FB5

    - -
    -
    - - - - -
    #define CAN_F3R1_FB5   CAN_F3R1_FB5_Msk
    -
    -

    Filter bit 5

    - -
    -
    - -

    ◆ CAN_F3R1_FB6_Pos

    - -
    -
    - - - - -
    #define CAN_F3R1_FB6_Pos   (6U)
    -
    - -
    -
    - -

    ◆ CAN_F3R1_FB6_Msk

    - -
    -
    - - - - -
    #define CAN_F3R1_FB6_Msk   (0x1UL << CAN_F3R1_FB6_Pos)
    -
    -

    0x00000040

    - -
    -
    - -

    ◆ CAN_F3R1_FB6

    - -
    -
    - - - - -
    #define CAN_F3R1_FB6   CAN_F3R1_FB6_Msk
    -
    -

    Filter bit 6

    - -
    -
    - -

    ◆ CAN_F3R1_FB7_Pos

    - -
    -
    - - - - -
    #define CAN_F3R1_FB7_Pos   (7U)
    -
    - -
    -
    - -

    ◆ CAN_F3R1_FB7_Msk

    - -
    -
    - - - - -
    #define CAN_F3R1_FB7_Msk   (0x1UL << CAN_F3R1_FB7_Pos)
    -
    -

    0x00000080

    - -
    -
    - -

    ◆ CAN_F3R1_FB7

    - -
    -
    - - - - -
    #define CAN_F3R1_FB7   CAN_F3R1_FB7_Msk
    -
    -

    Filter bit 7

    - -
    -
    - -

    ◆ CAN_F3R1_FB8_Pos

    - -
    -
    - - - - -
    #define CAN_F3R1_FB8_Pos   (8U)
    -
    - -
    -
    - -

    ◆ CAN_F3R1_FB8_Msk

    - -
    -
    - - - - -
    #define CAN_F3R1_FB8_Msk   (0x1UL << CAN_F3R1_FB8_Pos)
    -
    -

    0x00000100

    - -
    -
    - -

    ◆ CAN_F3R1_FB8

    - -
    -
    - - - - -
    #define CAN_F3R1_FB8   CAN_F3R1_FB8_Msk
    -
    -

    Filter bit 8

    - -
    -
    - -

    ◆ CAN_F3R1_FB9_Pos

    - -
    -
    - - - - -
    #define CAN_F3R1_FB9_Pos   (9U)
    -
    - -
    -
    - -

    ◆ CAN_F3R1_FB9_Msk

    - -
    -
    - - - - -
    #define CAN_F3R1_FB9_Msk   (0x1UL << CAN_F3R1_FB9_Pos)
    -
    -

    0x00000200

    - -
    -
    - -

    ◆ CAN_F3R1_FB9

    - -
    -
    - - - - -
    #define CAN_F3R1_FB9   CAN_F3R1_FB9_Msk
    -
    -

    Filter bit 9

    - -
    -
    - -

    ◆ CAN_F3R1_FB10_Pos

    - -
    -
    - - - - -
    #define CAN_F3R1_FB10_Pos   (10U)
    -
    - -
    -
    - -

    ◆ CAN_F3R1_FB10_Msk

    - -
    -
    - - - - -
    #define CAN_F3R1_FB10_Msk   (0x1UL << CAN_F3R1_FB10_Pos)
    -
    -

    0x00000400

    - -
    -
    - -

    ◆ CAN_F3R1_FB10

    - -
    -
    - - - - -
    #define CAN_F3R1_FB10   CAN_F3R1_FB10_Msk
    -
    -

    Filter bit 10

    - -
    -
    - -

    ◆ CAN_F3R1_FB11_Pos

    - -
    -
    - - - - -
    #define CAN_F3R1_FB11_Pos   (11U)
    -
    - -
    -
    - -

    ◆ CAN_F3R1_FB11_Msk

    - -
    -
    - - - - -
    #define CAN_F3R1_FB11_Msk   (0x1UL << CAN_F3R1_FB11_Pos)
    -
    -

    0x00000800

    - -
    -
    - -

    ◆ CAN_F3R1_FB11

    - -
    -
    - - - - -
    #define CAN_F3R1_FB11   CAN_F3R1_FB11_Msk
    -
    -

    Filter bit 11

    - -
    -
    - -

    ◆ CAN_F3R1_FB12_Pos

    - -
    -
    - - - - -
    #define CAN_F3R1_FB12_Pos   (12U)
    -
    - -
    -
    - -

    ◆ CAN_F3R1_FB12_Msk

    - -
    -
    - - - - -
    #define CAN_F3R1_FB12_Msk   (0x1UL << CAN_F3R1_FB12_Pos)
    -
    -

    0x00001000

    - -
    -
    - -

    ◆ CAN_F3R1_FB12

    - -
    -
    - - - - -
    #define CAN_F3R1_FB12   CAN_F3R1_FB12_Msk
    -
    -

    Filter bit 12

    - -
    -
    - -

    ◆ CAN_F3R1_FB13_Pos

    - -
    -
    - - - - -
    #define CAN_F3R1_FB13_Pos   (13U)
    -
    - -
    -
    - -

    ◆ CAN_F3R1_FB13_Msk

    - -
    -
    - - - - -
    #define CAN_F3R1_FB13_Msk   (0x1UL << CAN_F3R1_FB13_Pos)
    -
    -

    0x00002000

    - -
    -
    - -

    ◆ CAN_F3R1_FB13

    - -
    -
    - - - - -
    #define CAN_F3R1_FB13   CAN_F3R1_FB13_Msk
    -
    -

    Filter bit 13

    - -
    -
    - -

    ◆ CAN_F3R1_FB14_Pos

    - -
    -
    - - - - -
    #define CAN_F3R1_FB14_Pos   (14U)
    -
    - -
    -
    - -

    ◆ CAN_F3R1_FB14_Msk

    - -
    -
    - - - - -
    #define CAN_F3R1_FB14_Msk   (0x1UL << CAN_F3R1_FB14_Pos)
    -
    -

    0x00004000

    - -
    -
    - -

    ◆ CAN_F3R1_FB14

    - -
    -
    - - - - -
    #define CAN_F3R1_FB14   CAN_F3R1_FB14_Msk
    -
    -

    Filter bit 14

    - -
    -
    - -

    ◆ CAN_F3R1_FB15_Pos

    - -
    -
    - - - - -
    #define CAN_F3R1_FB15_Pos   (15U)
    -
    - -
    -
    - -

    ◆ CAN_F3R1_FB15_Msk

    - -
    -
    - - - - -
    #define CAN_F3R1_FB15_Msk   (0x1UL << CAN_F3R1_FB15_Pos)
    -
    -

    0x00008000

    - -
    -
    - -

    ◆ CAN_F3R1_FB15

    - -
    -
    - - - - -
    #define CAN_F3R1_FB15   CAN_F3R1_FB15_Msk
    -
    -

    Filter bit 15

    - -
    -
    - -

    ◆ CAN_F3R1_FB16_Pos

    - -
    -
    - - - - -
    #define CAN_F3R1_FB16_Pos   (16U)
    -
    - -
    -
    - -

    ◆ CAN_F3R1_FB16_Msk

    - -
    -
    - - - - -
    #define CAN_F3R1_FB16_Msk   (0x1UL << CAN_F3R1_FB16_Pos)
    -
    -

    0x00010000

    - -
    -
    - -

    ◆ CAN_F3R1_FB16

    - -
    -
    - - - - -
    #define CAN_F3R1_FB16   CAN_F3R1_FB16_Msk
    -
    -

    Filter bit 16

    - -
    -
    - -

    ◆ CAN_F3R1_FB17_Pos

    - -
    -
    - - - - -
    #define CAN_F3R1_FB17_Pos   (17U)
    -
    - -
    -
    - -

    ◆ CAN_F3R1_FB17_Msk

    - -
    -
    - - - - -
    #define CAN_F3R1_FB17_Msk   (0x1UL << CAN_F3R1_FB17_Pos)
    -
    -

    0x00020000

    - -
    -
    - -

    ◆ CAN_F3R1_FB17

    - -
    -
    - - - - -
    #define CAN_F3R1_FB17   CAN_F3R1_FB17_Msk
    -
    -

    Filter bit 17

    - -
    -
    - -

    ◆ CAN_F3R1_FB18_Pos

    - -
    -
    - - - - -
    #define CAN_F3R1_FB18_Pos   (18U)
    -
    - -
    -
    - -

    ◆ CAN_F3R1_FB18_Msk

    - -
    -
    - - - - -
    #define CAN_F3R1_FB18_Msk   (0x1UL << CAN_F3R1_FB18_Pos)
    -
    -

    0x00040000

    - -
    -
    - -

    ◆ CAN_F3R1_FB18

    - -
    -
    - - - - -
    #define CAN_F3R1_FB18   CAN_F3R1_FB18_Msk
    -
    -

    Filter bit 18

    - -
    -
    - -

    ◆ CAN_F3R1_FB19_Pos

    - -
    -
    - - - - -
    #define CAN_F3R1_FB19_Pos   (19U)
    -
    - -
    -
    - -

    ◆ CAN_F3R1_FB19_Msk

    - -
    -
    - - - - -
    #define CAN_F3R1_FB19_Msk   (0x1UL << CAN_F3R1_FB19_Pos)
    -
    -

    0x00080000

    - -
    -
    - -

    ◆ CAN_F3R1_FB19

    - -
    -
    - - - - -
    #define CAN_F3R1_FB19   CAN_F3R1_FB19_Msk
    -
    -

    Filter bit 19

    - -
    -
    - -

    ◆ CAN_F3R1_FB20_Pos

    - -
    -
    - - - - -
    #define CAN_F3R1_FB20_Pos   (20U)
    -
    - -
    -
    - -

    ◆ CAN_F3R1_FB20_Msk

    - -
    -
    - - - - -
    #define CAN_F3R1_FB20_Msk   (0x1UL << CAN_F3R1_FB20_Pos)
    -
    -

    0x00100000

    - -
    -
    - -

    ◆ CAN_F3R1_FB20

    - -
    -
    - - - - -
    #define CAN_F3R1_FB20   CAN_F3R1_FB20_Msk
    -
    -

    Filter bit 20

    - -
    -
    - -

    ◆ CAN_F3R1_FB21_Pos

    - -
    -
    - - - - -
    #define CAN_F3R1_FB21_Pos   (21U)
    -
    - -
    -
    - -

    ◆ CAN_F3R1_FB21_Msk

    - -
    -
    - - - - -
    #define CAN_F3R1_FB21_Msk   (0x1UL << CAN_F3R1_FB21_Pos)
    -
    -

    0x00200000

    - -
    -
    - -

    ◆ CAN_F3R1_FB21

    - -
    -
    - - - - -
    #define CAN_F3R1_FB21   CAN_F3R1_FB21_Msk
    -
    -

    Filter bit 21

    - -
    -
    - -

    ◆ CAN_F3R1_FB22_Pos

    - -
    -
    - - - - -
    #define CAN_F3R1_FB22_Pos   (22U)
    -
    - -
    -
    - -

    ◆ CAN_F3R1_FB22_Msk

    - -
    -
    - - - - -
    #define CAN_F3R1_FB22_Msk   (0x1UL << CAN_F3R1_FB22_Pos)
    -
    -

    0x00400000

    - -
    -
    - -

    ◆ CAN_F3R1_FB22

    - -
    -
    - - - - -
    #define CAN_F3R1_FB22   CAN_F3R1_FB22_Msk
    -
    -

    Filter bit 22

    - -
    -
    - -

    ◆ CAN_F3R1_FB23_Pos

    - -
    -
    - - - - -
    #define CAN_F3R1_FB23_Pos   (23U)
    -
    - -
    -
    - -

    ◆ CAN_F3R1_FB23_Msk

    - -
    -
    - - - - -
    #define CAN_F3R1_FB23_Msk   (0x1UL << CAN_F3R1_FB23_Pos)
    -
    -

    0x00800000

    - -
    -
    - -

    ◆ CAN_F3R1_FB23

    - -
    -
    - - - - -
    #define CAN_F3R1_FB23   CAN_F3R1_FB23_Msk
    -
    -

    Filter bit 23

    - -
    -
    - -

    ◆ CAN_F3R1_FB24_Pos

    - -
    -
    - - - - -
    #define CAN_F3R1_FB24_Pos   (24U)
    -
    - -
    -
    - -

    ◆ CAN_F3R1_FB24_Msk

    - -
    -
    - - - - -
    #define CAN_F3R1_FB24_Msk   (0x1UL << CAN_F3R1_FB24_Pos)
    -
    -

    0x01000000

    - -
    -
    - -

    ◆ CAN_F3R1_FB24

    - -
    -
    - - - - -
    #define CAN_F3R1_FB24   CAN_F3R1_FB24_Msk
    -
    -

    Filter bit 24

    - -
    -
    - -

    ◆ CAN_F3R1_FB25_Pos

    - -
    -
    - - - - -
    #define CAN_F3R1_FB25_Pos   (25U)
    -
    - -
    -
    - -

    ◆ CAN_F3R1_FB25_Msk

    - -
    -
    - - - - -
    #define CAN_F3R1_FB25_Msk   (0x1UL << CAN_F3R1_FB25_Pos)
    -
    -

    0x02000000

    - -
    -
    - -

    ◆ CAN_F3R1_FB25

    - -
    -
    - - - - -
    #define CAN_F3R1_FB25   CAN_F3R1_FB25_Msk
    -
    -

    Filter bit 25

    - -
    -
    - -

    ◆ CAN_F3R1_FB26_Pos

    - -
    -
    - - - - -
    #define CAN_F3R1_FB26_Pos   (26U)
    -
    - -
    -
    - -

    ◆ CAN_F3R1_FB26_Msk

    - -
    -
    - - - - -
    #define CAN_F3R1_FB26_Msk   (0x1UL << CAN_F3R1_FB26_Pos)
    -
    -

    0x04000000

    - -
    -
    - -

    ◆ CAN_F3R1_FB26

    - -
    -
    - - - - -
    #define CAN_F3R1_FB26   CAN_F3R1_FB26_Msk
    -
    -

    Filter bit 26

    - -
    -
    - -

    ◆ CAN_F3R1_FB27_Pos

    - -
    -
    - - - - -
    #define CAN_F3R1_FB27_Pos   (27U)
    -
    - -
    -
    - -

    ◆ CAN_F3R1_FB27_Msk

    - -
    -
    - - - - -
    #define CAN_F3R1_FB27_Msk   (0x1UL << CAN_F3R1_FB27_Pos)
    -
    -

    0x08000000

    - -
    -
    - -

    ◆ CAN_F3R1_FB27

    - -
    -
    - - - - -
    #define CAN_F3R1_FB27   CAN_F3R1_FB27_Msk
    -
    -

    Filter bit 27

    - -
    -
    - -

    ◆ CAN_F3R1_FB28_Pos

    - -
    -
    - - - - -
    #define CAN_F3R1_FB28_Pos   (28U)
    -
    - -
    -
    - -

    ◆ CAN_F3R1_FB28_Msk

    - -
    -
    - - - - -
    #define CAN_F3R1_FB28_Msk   (0x1UL << CAN_F3R1_FB28_Pos)
    -
    -

    0x10000000

    - -
    -
    - -

    ◆ CAN_F3R1_FB28

    - -
    -
    - - - - -
    #define CAN_F3R1_FB28   CAN_F3R1_FB28_Msk
    -
    -

    Filter bit 28

    - -
    -
    - -

    ◆ CAN_F3R1_FB29_Pos

    - -
    -
    - - - - -
    #define CAN_F3R1_FB29_Pos   (29U)
    -
    - -
    -
    - -

    ◆ CAN_F3R1_FB29_Msk

    - -
    -
    - - - - -
    #define CAN_F3R1_FB29_Msk   (0x1UL << CAN_F3R1_FB29_Pos)
    -
    -

    0x20000000

    - -
    -
    - -

    ◆ CAN_F3R1_FB29

    - -
    -
    - - - - -
    #define CAN_F3R1_FB29   CAN_F3R1_FB29_Msk
    -
    -

    Filter bit 29

    - -
    -
    - -

    ◆ CAN_F3R1_FB30_Pos

    - -
    -
    - - - - -
    #define CAN_F3R1_FB30_Pos   (30U)
    -
    - -
    -
    - -

    ◆ CAN_F3R1_FB30_Msk

    - -
    -
    - - - - -
    #define CAN_F3R1_FB30_Msk   (0x1UL << CAN_F3R1_FB30_Pos)
    -
    -

    0x40000000

    - -
    -
    - -

    ◆ CAN_F3R1_FB30

    - -
    -
    - - - - -
    #define CAN_F3R1_FB30   CAN_F3R1_FB30_Msk
    -
    -

    Filter bit 30

    - -
    -
    - -

    ◆ CAN_F3R1_FB31_Pos

    - -
    -
    - - - - -
    #define CAN_F3R1_FB31_Pos   (31U)
    -
    - -
    -
    - -

    ◆ CAN_F3R1_FB31_Msk

    - -
    -
    - - - - -
    #define CAN_F3R1_FB31_Msk   (0x1UL << CAN_F3R1_FB31_Pos)
    -
    -

    0x80000000

    - -
    -
    - -

    ◆ CAN_F3R1_FB31

    - -
    -
    - - - - -
    #define CAN_F3R1_FB31   CAN_F3R1_FB31_Msk
    -
    -

    Filter bit 31

    - -
    -
    - -

    ◆ CAN_F4R1_FB0_Pos

    - -
    -
    - - - - -
    #define CAN_F4R1_FB0_Pos   (0U)
    -
    - -
    -
    - -

    ◆ CAN_F4R1_FB0_Msk

    - -
    -
    - - - - -
    #define CAN_F4R1_FB0_Msk   (0x1UL << CAN_F4R1_FB0_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ CAN_F4R1_FB0

    - -
    -
    - - - - -
    #define CAN_F4R1_FB0   CAN_F4R1_FB0_Msk
    -
    -

    Filter bit 0

    - -
    -
    - -

    ◆ CAN_F4R1_FB1_Pos

    - -
    -
    - - - - -
    #define CAN_F4R1_FB1_Pos   (1U)
    -
    - -
    -
    - -

    ◆ CAN_F4R1_FB1_Msk

    - -
    -
    - - - - -
    #define CAN_F4R1_FB1_Msk   (0x1UL << CAN_F4R1_FB1_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ CAN_F4R1_FB1

    - -
    -
    - - - - -
    #define CAN_F4R1_FB1   CAN_F4R1_FB1_Msk
    -
    -

    Filter bit 1

    - -
    -
    - -

    ◆ CAN_F4R1_FB2_Pos

    - -
    -
    - - - - -
    #define CAN_F4R1_FB2_Pos   (2U)
    -
    - -
    -
    - -

    ◆ CAN_F4R1_FB2_Msk

    - -
    -
    - - - - -
    #define CAN_F4R1_FB2_Msk   (0x1UL << CAN_F4R1_FB2_Pos)
    -
    -

    0x00000004

    - -
    -
    - -

    ◆ CAN_F4R1_FB2

    - -
    -
    - - - - -
    #define CAN_F4R1_FB2   CAN_F4R1_FB2_Msk
    -
    -

    Filter bit 2

    - -
    -
    - -

    ◆ CAN_F4R1_FB3_Pos

    - -
    -
    - - - - -
    #define CAN_F4R1_FB3_Pos   (3U)
    -
    - -
    -
    - -

    ◆ CAN_F4R1_FB3_Msk

    - -
    -
    - - - - -
    #define CAN_F4R1_FB3_Msk   (0x1UL << CAN_F4R1_FB3_Pos)
    -
    -

    0x00000008

    - -
    -
    - -

    ◆ CAN_F4R1_FB3

    - -
    -
    - - - - -
    #define CAN_F4R1_FB3   CAN_F4R1_FB3_Msk
    -
    -

    Filter bit 3

    - -
    -
    - -

    ◆ CAN_F4R1_FB4_Pos

    - -
    -
    - - - - -
    #define CAN_F4R1_FB4_Pos   (4U)
    -
    - -
    -
    - -

    ◆ CAN_F4R1_FB4_Msk

    - -
    -
    - - - - -
    #define CAN_F4R1_FB4_Msk   (0x1UL << CAN_F4R1_FB4_Pos)
    -
    -

    0x00000010

    - -
    -
    - -

    ◆ CAN_F4R1_FB4

    - -
    -
    - - - - -
    #define CAN_F4R1_FB4   CAN_F4R1_FB4_Msk
    -
    -

    Filter bit 4

    - -
    -
    - -

    ◆ CAN_F4R1_FB5_Pos

    - -
    -
    - - - - -
    #define CAN_F4R1_FB5_Pos   (5U)
    -
    - -
    -
    - -

    ◆ CAN_F4R1_FB5_Msk

    - -
    -
    - - - - -
    #define CAN_F4R1_FB5_Msk   (0x1UL << CAN_F4R1_FB5_Pos)
    -
    -

    0x00000020

    - -
    -
    - -

    ◆ CAN_F4R1_FB5

    - -
    -
    - - - - -
    #define CAN_F4R1_FB5   CAN_F4R1_FB5_Msk
    -
    -

    Filter bit 5

    - -
    -
    - -

    ◆ CAN_F4R1_FB6_Pos

    - -
    -
    - - - - -
    #define CAN_F4R1_FB6_Pos   (6U)
    -
    - -
    -
    - -

    ◆ CAN_F4R1_FB6_Msk

    - -
    -
    - - - - -
    #define CAN_F4R1_FB6_Msk   (0x1UL << CAN_F4R1_FB6_Pos)
    -
    -

    0x00000040

    - -
    -
    - -

    ◆ CAN_F4R1_FB6

    - -
    -
    - - - - -
    #define CAN_F4R1_FB6   CAN_F4R1_FB6_Msk
    -
    -

    Filter bit 6

    - -
    -
    - -

    ◆ CAN_F4R1_FB7_Pos

    - -
    -
    - - - - -
    #define CAN_F4R1_FB7_Pos   (7U)
    -
    - -
    -
    - -

    ◆ CAN_F4R1_FB7_Msk

    - -
    -
    - - - - -
    #define CAN_F4R1_FB7_Msk   (0x1UL << CAN_F4R1_FB7_Pos)
    -
    -

    0x00000080

    - -
    -
    - -

    ◆ CAN_F4R1_FB7

    - -
    -
    - - - - -
    #define CAN_F4R1_FB7   CAN_F4R1_FB7_Msk
    -
    -

    Filter bit 7

    - -
    -
    - -

    ◆ CAN_F4R1_FB8_Pos

    - -
    -
    - - - - -
    #define CAN_F4R1_FB8_Pos   (8U)
    -
    - -
    -
    - -

    ◆ CAN_F4R1_FB8_Msk

    - -
    -
    - - - - -
    #define CAN_F4R1_FB8_Msk   (0x1UL << CAN_F4R1_FB8_Pos)
    -
    -

    0x00000100

    - -
    -
    - -

    ◆ CAN_F4R1_FB8

    - -
    -
    - - - - -
    #define CAN_F4R1_FB8   CAN_F4R1_FB8_Msk
    -
    -

    Filter bit 8

    - -
    -
    - -

    ◆ CAN_F4R1_FB9_Pos

    - -
    -
    - - - - -
    #define CAN_F4R1_FB9_Pos   (9U)
    -
    - -
    -
    - -

    ◆ CAN_F4R1_FB9_Msk

    - -
    -
    - - - - -
    #define CAN_F4R1_FB9_Msk   (0x1UL << CAN_F4R1_FB9_Pos)
    -
    -

    0x00000200

    - -
    -
    - -

    ◆ CAN_F4R1_FB9

    - -
    -
    - - - - -
    #define CAN_F4R1_FB9   CAN_F4R1_FB9_Msk
    -
    -

    Filter bit 9

    - -
    -
    - -

    ◆ CAN_F4R1_FB10_Pos

    - -
    -
    - - - - -
    #define CAN_F4R1_FB10_Pos   (10U)
    -
    - -
    -
    - -

    ◆ CAN_F4R1_FB10_Msk

    - -
    -
    - - - - -
    #define CAN_F4R1_FB10_Msk   (0x1UL << CAN_F4R1_FB10_Pos)
    -
    -

    0x00000400

    - -
    -
    - -

    ◆ CAN_F4R1_FB10

    - -
    -
    - - - - -
    #define CAN_F4R1_FB10   CAN_F4R1_FB10_Msk
    -
    -

    Filter bit 10

    - -
    -
    - -

    ◆ CAN_F4R1_FB11_Pos

    - -
    -
    - - - - -
    #define CAN_F4R1_FB11_Pos   (11U)
    -
    - -
    -
    - -

    ◆ CAN_F4R1_FB11_Msk

    - -
    -
    - - - - -
    #define CAN_F4R1_FB11_Msk   (0x1UL << CAN_F4R1_FB11_Pos)
    -
    -

    0x00000800

    - -
    -
    - -

    ◆ CAN_F4R1_FB11

    - -
    -
    - - - - -
    #define CAN_F4R1_FB11   CAN_F4R1_FB11_Msk
    -
    -

    Filter bit 11

    - -
    -
    - -

    ◆ CAN_F4R1_FB12_Pos

    - -
    -
    - - - - -
    #define CAN_F4R1_FB12_Pos   (12U)
    -
    - -
    -
    - -

    ◆ CAN_F4R1_FB12_Msk

    - -
    -
    - - - - -
    #define CAN_F4R1_FB12_Msk   (0x1UL << CAN_F4R1_FB12_Pos)
    -
    -

    0x00001000

    - -
    -
    - -

    ◆ CAN_F4R1_FB12

    - -
    -
    - - - - -
    #define CAN_F4R1_FB12   CAN_F4R1_FB12_Msk
    -
    -

    Filter bit 12

    - -
    -
    - -

    ◆ CAN_F4R1_FB13_Pos

    - -
    -
    - - - - -
    #define CAN_F4R1_FB13_Pos   (13U)
    -
    - -
    -
    - -

    ◆ CAN_F4R1_FB13_Msk

    - -
    -
    - - - - -
    #define CAN_F4R1_FB13_Msk   (0x1UL << CAN_F4R1_FB13_Pos)
    -
    -

    0x00002000

    - -
    -
    - -

    ◆ CAN_F4R1_FB13

    - -
    -
    - - - - -
    #define CAN_F4R1_FB13   CAN_F4R1_FB13_Msk
    -
    -

    Filter bit 13

    - -
    -
    - -

    ◆ CAN_F4R1_FB14_Pos

    - -
    -
    - - - - -
    #define CAN_F4R1_FB14_Pos   (14U)
    -
    - -
    -
    - -

    ◆ CAN_F4R1_FB14_Msk

    - -
    -
    - - - - -
    #define CAN_F4R1_FB14_Msk   (0x1UL << CAN_F4R1_FB14_Pos)
    -
    -

    0x00004000

    - -
    -
    - -

    ◆ CAN_F4R1_FB14

    - -
    -
    - - - - -
    #define CAN_F4R1_FB14   CAN_F4R1_FB14_Msk
    -
    -

    Filter bit 14

    - -
    -
    - -

    ◆ CAN_F4R1_FB15_Pos

    - -
    -
    - - - - -
    #define CAN_F4R1_FB15_Pos   (15U)
    -
    - -
    -
    - -

    ◆ CAN_F4R1_FB15_Msk

    - -
    -
    - - - - -
    #define CAN_F4R1_FB15_Msk   (0x1UL << CAN_F4R1_FB15_Pos)
    -
    -

    0x00008000

    - -
    -
    - -

    ◆ CAN_F4R1_FB15

    - -
    -
    - - - - -
    #define CAN_F4R1_FB15   CAN_F4R1_FB15_Msk
    -
    -

    Filter bit 15

    - -
    -
    - -

    ◆ CAN_F4R1_FB16_Pos

    - -
    -
    - - - - -
    #define CAN_F4R1_FB16_Pos   (16U)
    -
    - -
    -
    - -

    ◆ CAN_F4R1_FB16_Msk

    - -
    -
    - - - - -
    #define CAN_F4R1_FB16_Msk   (0x1UL << CAN_F4R1_FB16_Pos)
    -
    -

    0x00010000

    - -
    -
    - -

    ◆ CAN_F4R1_FB16

    - -
    -
    - - - - -
    #define CAN_F4R1_FB16   CAN_F4R1_FB16_Msk
    -
    -

    Filter bit 16

    - -
    -
    - -

    ◆ CAN_F4R1_FB17_Pos

    - -
    -
    - - - - -
    #define CAN_F4R1_FB17_Pos   (17U)
    -
    - -
    -
    - -

    ◆ CAN_F4R1_FB17_Msk

    - -
    -
    - - - - -
    #define CAN_F4R1_FB17_Msk   (0x1UL << CAN_F4R1_FB17_Pos)
    -
    -

    0x00020000

    - -
    -
    - -

    ◆ CAN_F4R1_FB17

    - -
    -
    - - - - -
    #define CAN_F4R1_FB17   CAN_F4R1_FB17_Msk
    -
    -

    Filter bit 17

    - -
    -
    - -

    ◆ CAN_F4R1_FB18_Pos

    - -
    -
    - - - - -
    #define CAN_F4R1_FB18_Pos   (18U)
    -
    - -
    -
    - -

    ◆ CAN_F4R1_FB18_Msk

    - -
    -
    - - - - -
    #define CAN_F4R1_FB18_Msk   (0x1UL << CAN_F4R1_FB18_Pos)
    -
    -

    0x00040000

    - -
    -
    - -

    ◆ CAN_F4R1_FB18

    - -
    -
    - - - - -
    #define CAN_F4R1_FB18   CAN_F4R1_FB18_Msk
    -
    -

    Filter bit 18

    - -
    -
    - -

    ◆ CAN_F4R1_FB19_Pos

    - -
    -
    - - - - -
    #define CAN_F4R1_FB19_Pos   (19U)
    -
    - -
    -
    - -

    ◆ CAN_F4R1_FB19_Msk

    - -
    -
    - - - - -
    #define CAN_F4R1_FB19_Msk   (0x1UL << CAN_F4R1_FB19_Pos)
    -
    -

    0x00080000

    - -
    -
    - -

    ◆ CAN_F4R1_FB19

    - -
    -
    - - - - -
    #define CAN_F4R1_FB19   CAN_F4R1_FB19_Msk
    -
    -

    Filter bit 19

    - -
    -
    - -

    ◆ CAN_F4R1_FB20_Pos

    - -
    -
    - - - - -
    #define CAN_F4R1_FB20_Pos   (20U)
    -
    - -
    -
    - -

    ◆ CAN_F4R1_FB20_Msk

    - -
    -
    - - - - -
    #define CAN_F4R1_FB20_Msk   (0x1UL << CAN_F4R1_FB20_Pos)
    -
    -

    0x00100000

    - -
    -
    - -

    ◆ CAN_F4R1_FB20

    - -
    -
    - - - - -
    #define CAN_F4R1_FB20   CAN_F4R1_FB20_Msk
    -
    -

    Filter bit 20

    - -
    -
    - -

    ◆ CAN_F4R1_FB21_Pos

    - -
    -
    - - - - -
    #define CAN_F4R1_FB21_Pos   (21U)
    -
    - -
    -
    - -

    ◆ CAN_F4R1_FB21_Msk

    - -
    -
    - - - - -
    #define CAN_F4R1_FB21_Msk   (0x1UL << CAN_F4R1_FB21_Pos)
    -
    -

    0x00200000

    - -
    -
    - -

    ◆ CAN_F4R1_FB21

    - -
    -
    - - - - -
    #define CAN_F4R1_FB21   CAN_F4R1_FB21_Msk
    -
    -

    Filter bit 21

    - -
    -
    - -

    ◆ CAN_F4R1_FB22_Pos

    - -
    -
    - - - - -
    #define CAN_F4R1_FB22_Pos   (22U)
    -
    - -
    -
    - -

    ◆ CAN_F4R1_FB22_Msk

    - -
    -
    - - - - -
    #define CAN_F4R1_FB22_Msk   (0x1UL << CAN_F4R1_FB22_Pos)
    -
    -

    0x00400000

    - -
    -
    - -

    ◆ CAN_F4R1_FB22

    - -
    -
    - - - - -
    #define CAN_F4R1_FB22   CAN_F4R1_FB22_Msk
    -
    -

    Filter bit 22

    - -
    -
    - -

    ◆ CAN_F4R1_FB23_Pos

    - -
    -
    - - - - -
    #define CAN_F4R1_FB23_Pos   (23U)
    -
    - -
    -
    - -

    ◆ CAN_F4R1_FB23_Msk

    - -
    -
    - - - - -
    #define CAN_F4R1_FB23_Msk   (0x1UL << CAN_F4R1_FB23_Pos)
    -
    -

    0x00800000

    - -
    -
    - -

    ◆ CAN_F4R1_FB23

    - -
    -
    - - - - -
    #define CAN_F4R1_FB23   CAN_F4R1_FB23_Msk
    -
    -

    Filter bit 23

    - -
    -
    - -

    ◆ CAN_F4R1_FB24_Pos

    - -
    -
    - - - - -
    #define CAN_F4R1_FB24_Pos   (24U)
    -
    - -
    -
    - -

    ◆ CAN_F4R1_FB24_Msk

    - -
    -
    - - - - -
    #define CAN_F4R1_FB24_Msk   (0x1UL << CAN_F4R1_FB24_Pos)
    -
    -

    0x01000000

    - -
    -
    - -

    ◆ CAN_F4R1_FB24

    - -
    -
    - - - - -
    #define CAN_F4R1_FB24   CAN_F4R1_FB24_Msk
    -
    -

    Filter bit 24

    - -
    -
    - -

    ◆ CAN_F4R1_FB25_Pos

    - -
    -
    - - - - -
    #define CAN_F4R1_FB25_Pos   (25U)
    -
    - -
    -
    - -

    ◆ CAN_F4R1_FB25_Msk

    - -
    -
    - - - - -
    #define CAN_F4R1_FB25_Msk   (0x1UL << CAN_F4R1_FB25_Pos)
    -
    -

    0x02000000

    - -
    -
    - -

    ◆ CAN_F4R1_FB25

    - -
    -
    - - - - -
    #define CAN_F4R1_FB25   CAN_F4R1_FB25_Msk
    -
    -

    Filter bit 25

    - -
    -
    - -

    ◆ CAN_F4R1_FB26_Pos

    - -
    -
    - - - - -
    #define CAN_F4R1_FB26_Pos   (26U)
    -
    - -
    -
    - -

    ◆ CAN_F4R1_FB26_Msk

    - -
    -
    - - - - -
    #define CAN_F4R1_FB26_Msk   (0x1UL << CAN_F4R1_FB26_Pos)
    -
    -

    0x04000000

    - -
    -
    - -

    ◆ CAN_F4R1_FB26

    - -
    -
    - - - - -
    #define CAN_F4R1_FB26   CAN_F4R1_FB26_Msk
    -
    -

    Filter bit 26

    - -
    -
    - -

    ◆ CAN_F4R1_FB27_Pos

    - -
    -
    - - - - -
    #define CAN_F4R1_FB27_Pos   (27U)
    -
    - -
    -
    - -

    ◆ CAN_F4R1_FB27_Msk

    - -
    -
    - - - - -
    #define CAN_F4R1_FB27_Msk   (0x1UL << CAN_F4R1_FB27_Pos)
    -
    -

    0x08000000

    - -
    -
    - -

    ◆ CAN_F4R1_FB27

    - -
    -
    - - - - -
    #define CAN_F4R1_FB27   CAN_F4R1_FB27_Msk
    -
    -

    Filter bit 27

    - -
    -
    - -

    ◆ CAN_F4R1_FB28_Pos

    - -
    -
    - - - - -
    #define CAN_F4R1_FB28_Pos   (28U)
    -
    - -
    -
    - -

    ◆ CAN_F4R1_FB28_Msk

    - -
    -
    - - - - -
    #define CAN_F4R1_FB28_Msk   (0x1UL << CAN_F4R1_FB28_Pos)
    -
    -

    0x10000000

    - -
    -
    - -

    ◆ CAN_F4R1_FB28

    - -
    -
    - - - - -
    #define CAN_F4R1_FB28   CAN_F4R1_FB28_Msk
    -
    -

    Filter bit 28

    - -
    -
    - -

    ◆ CAN_F4R1_FB29_Pos

    - -
    -
    - - - - -
    #define CAN_F4R1_FB29_Pos   (29U)
    -
    - -
    -
    - -

    ◆ CAN_F4R1_FB29_Msk

    - -
    -
    - - - - -
    #define CAN_F4R1_FB29_Msk   (0x1UL << CAN_F4R1_FB29_Pos)
    -
    -

    0x20000000

    - -
    -
    - -

    ◆ CAN_F4R1_FB29

    - -
    -
    - - - - -
    #define CAN_F4R1_FB29   CAN_F4R1_FB29_Msk
    -
    -

    Filter bit 29

    - -
    -
    - -

    ◆ CAN_F4R1_FB30_Pos

    - -
    -
    - - - - -
    #define CAN_F4R1_FB30_Pos   (30U)
    -
    - -
    -
    - -

    ◆ CAN_F4R1_FB30_Msk

    - -
    -
    - - - - -
    #define CAN_F4R1_FB30_Msk   (0x1UL << CAN_F4R1_FB30_Pos)
    -
    -

    0x40000000

    - -
    -
    - -

    ◆ CAN_F4R1_FB30

    - -
    -
    - - - - -
    #define CAN_F4R1_FB30   CAN_F4R1_FB30_Msk
    -
    -

    Filter bit 30

    - -
    -
    - -

    ◆ CAN_F4R1_FB31_Pos

    - -
    -
    - - - - -
    #define CAN_F4R1_FB31_Pos   (31U)
    -
    - -
    -
    - -

    ◆ CAN_F4R1_FB31_Msk

    - -
    -
    - - - - -
    #define CAN_F4R1_FB31_Msk   (0x1UL << CAN_F4R1_FB31_Pos)
    -
    -

    0x80000000

    - -
    -
    - -

    ◆ CAN_F4R1_FB31

    - -
    -
    - - - - -
    #define CAN_F4R1_FB31   CAN_F4R1_FB31_Msk
    -
    -

    Filter bit 31

    - -
    -
    - -

    ◆ CAN_F5R1_FB0_Pos

    - -
    -
    - - - - -
    #define CAN_F5R1_FB0_Pos   (0U)
    -
    - -
    -
    - -

    ◆ CAN_F5R1_FB0_Msk

    - -
    -
    - - - - -
    #define CAN_F5R1_FB0_Msk   (0x1UL << CAN_F5R1_FB0_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ CAN_F5R1_FB0

    - -
    -
    - - - - -
    #define CAN_F5R1_FB0   CAN_F5R1_FB0_Msk
    -
    -

    Filter bit 0

    - -
    -
    - -

    ◆ CAN_F5R1_FB1_Pos

    - -
    -
    - - - - -
    #define CAN_F5R1_FB1_Pos   (1U)
    -
    - -
    -
    - -

    ◆ CAN_F5R1_FB1_Msk

    - -
    -
    - - - - -
    #define CAN_F5R1_FB1_Msk   (0x1UL << CAN_F5R1_FB1_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ CAN_F5R1_FB1

    - -
    -
    - - - - -
    #define CAN_F5R1_FB1   CAN_F5R1_FB1_Msk
    -
    -

    Filter bit 1

    - -
    -
    - -

    ◆ CAN_F5R1_FB2_Pos

    - -
    -
    - - - - -
    #define CAN_F5R1_FB2_Pos   (2U)
    -
    - -
    -
    - -

    ◆ CAN_F5R1_FB2_Msk

    - -
    -
    - - - - -
    #define CAN_F5R1_FB2_Msk   (0x1UL << CAN_F5R1_FB2_Pos)
    -
    -

    0x00000004

    - -
    -
    - -

    ◆ CAN_F5R1_FB2

    - -
    -
    - - - - -
    #define CAN_F5R1_FB2   CAN_F5R1_FB2_Msk
    -
    -

    Filter bit 2

    - -
    -
    - -

    ◆ CAN_F5R1_FB3_Pos

    - -
    -
    - - - - -
    #define CAN_F5R1_FB3_Pos   (3U)
    -
    - -
    -
    - -

    ◆ CAN_F5R1_FB3_Msk

    - -
    -
    - - - - -
    #define CAN_F5R1_FB3_Msk   (0x1UL << CAN_F5R1_FB3_Pos)
    -
    -

    0x00000008

    - -
    -
    - -

    ◆ CAN_F5R1_FB3

    - -
    -
    - - - - -
    #define CAN_F5R1_FB3   CAN_F5R1_FB3_Msk
    -
    -

    Filter bit 3

    - -
    -
    - -

    ◆ CAN_F5R1_FB4_Pos

    - -
    -
    - - - - -
    #define CAN_F5R1_FB4_Pos   (4U)
    -
    - -
    -
    - -

    ◆ CAN_F5R1_FB4_Msk

    - -
    -
    - - - - -
    #define CAN_F5R1_FB4_Msk   (0x1UL << CAN_F5R1_FB4_Pos)
    -
    -

    0x00000010

    - -
    -
    - -

    ◆ CAN_F5R1_FB4

    - -
    -
    - - - - -
    #define CAN_F5R1_FB4   CAN_F5R1_FB4_Msk
    -
    -

    Filter bit 4

    - -
    -
    - -

    ◆ CAN_F5R1_FB5_Pos

    - -
    -
    - - - - -
    #define CAN_F5R1_FB5_Pos   (5U)
    -
    - -
    -
    - -

    ◆ CAN_F5R1_FB5_Msk

    - -
    -
    - - - - -
    #define CAN_F5R1_FB5_Msk   (0x1UL << CAN_F5R1_FB5_Pos)
    -
    -

    0x00000020

    - -
    -
    - -

    ◆ CAN_F5R1_FB5

    - -
    -
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    #define CAN_F5R1_FB5   CAN_F5R1_FB5_Msk
    -
    -

    Filter bit 5

    - -
    -
    - -

    ◆ CAN_F5R1_FB6_Pos

    - -
    -
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    #define CAN_F5R1_FB6_Pos   (6U)
    -
    - -
    -
    - -

    ◆ CAN_F5R1_FB6_Msk

    - -
    -
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    #define CAN_F5R1_FB6_Msk   (0x1UL << CAN_F5R1_FB6_Pos)
    -
    -

    0x00000040

    - -
    -
    - -

    ◆ CAN_F5R1_FB6

    - -
    -
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    #define CAN_F5R1_FB6   CAN_F5R1_FB6_Msk
    -
    -

    Filter bit 6

    - -
    -
    - -

    ◆ CAN_F5R1_FB7_Pos

    - -
    -
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    #define CAN_F5R1_FB7_Pos   (7U)
    -
    - -
    -
    - -

    ◆ CAN_F5R1_FB7_Msk

    - -
    -
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    #define CAN_F5R1_FB7_Msk   (0x1UL << CAN_F5R1_FB7_Pos)
    -
    -

    0x00000080

    - -
    -
    - -

    ◆ CAN_F5R1_FB7

    - -
    -
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    #define CAN_F5R1_FB7   CAN_F5R1_FB7_Msk
    -
    -

    Filter bit 7

    - -
    -
    - -

    ◆ CAN_F5R1_FB8_Pos

    - -
    -
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    #define CAN_F5R1_FB8_Pos   (8U)
    -
    - -
    -
    - -

    ◆ CAN_F5R1_FB8_Msk

    - -
    -
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    #define CAN_F5R1_FB8_Msk   (0x1UL << CAN_F5R1_FB8_Pos)
    -
    -

    0x00000100

    - -
    -
    - -

    ◆ CAN_F5R1_FB8

    - -
    -
    - - - - -
    #define CAN_F5R1_FB8   CAN_F5R1_FB8_Msk
    -
    -

    Filter bit 8

    - -
    -
    - -

    ◆ CAN_F5R1_FB9_Pos

    - -
    -
    - - - - -
    #define CAN_F5R1_FB9_Pos   (9U)
    -
    - -
    -
    - -

    ◆ CAN_F5R1_FB9_Msk

    - -
    -
    - - - - -
    #define CAN_F5R1_FB9_Msk   (0x1UL << CAN_F5R1_FB9_Pos)
    -
    -

    0x00000200

    - -
    -
    - -

    ◆ CAN_F5R1_FB9

    - -
    -
    - - - - -
    #define CAN_F5R1_FB9   CAN_F5R1_FB9_Msk
    -
    -

    Filter bit 9

    - -
    -
    - -

    ◆ CAN_F5R1_FB10_Pos

    - -
    -
    - - - - -
    #define CAN_F5R1_FB10_Pos   (10U)
    -
    - -
    -
    - -

    ◆ CAN_F5R1_FB10_Msk

    - -
    -
    - - - - -
    #define CAN_F5R1_FB10_Msk   (0x1UL << CAN_F5R1_FB10_Pos)
    -
    -

    0x00000400

    - -
    -
    - -

    ◆ CAN_F5R1_FB10

    - -
    -
    - - - - -
    #define CAN_F5R1_FB10   CAN_F5R1_FB10_Msk
    -
    -

    Filter bit 10

    - -
    -
    - -

    ◆ CAN_F5R1_FB11_Pos

    - -
    -
    - - - - -
    #define CAN_F5R1_FB11_Pos   (11U)
    -
    - -
    -
    - -

    ◆ CAN_F5R1_FB11_Msk

    - -
    -
    - - - - -
    #define CAN_F5R1_FB11_Msk   (0x1UL << CAN_F5R1_FB11_Pos)
    -
    -

    0x00000800

    - -
    -
    - -

    ◆ CAN_F5R1_FB11

    - -
    -
    - - - - -
    #define CAN_F5R1_FB11   CAN_F5R1_FB11_Msk
    -
    -

    Filter bit 11

    - -
    -
    - -

    ◆ CAN_F5R1_FB12_Pos

    - -
    -
    - - - - -
    #define CAN_F5R1_FB12_Pos   (12U)
    -
    - -
    -
    - -

    ◆ CAN_F5R1_FB12_Msk

    - -
    -
    - - - - -
    #define CAN_F5R1_FB12_Msk   (0x1UL << CAN_F5R1_FB12_Pos)
    -
    -

    0x00001000

    - -
    -
    - -

    ◆ CAN_F5R1_FB12

    - -
    -
    - - - - -
    #define CAN_F5R1_FB12   CAN_F5R1_FB12_Msk
    -
    -

    Filter bit 12

    - -
    -
    - -

    ◆ CAN_F5R1_FB13_Pos

    - -
    -
    - - - - -
    #define CAN_F5R1_FB13_Pos   (13U)
    -
    - -
    -
    - -

    ◆ CAN_F5R1_FB13_Msk

    - -
    -
    - - - - -
    #define CAN_F5R1_FB13_Msk   (0x1UL << CAN_F5R1_FB13_Pos)
    -
    -

    0x00002000

    - -
    -
    - -

    ◆ CAN_F5R1_FB13

    - -
    -
    - - - - -
    #define CAN_F5R1_FB13   CAN_F5R1_FB13_Msk
    -
    -

    Filter bit 13

    - -
    -
    - -

    ◆ CAN_F5R1_FB14_Pos

    - -
    -
    - - - - -
    #define CAN_F5R1_FB14_Pos   (14U)
    -
    - -
    -
    - -

    ◆ CAN_F5R1_FB14_Msk

    - -
    -
    - - - - -
    #define CAN_F5R1_FB14_Msk   (0x1UL << CAN_F5R1_FB14_Pos)
    -
    -

    0x00004000

    - -
    -
    - -

    ◆ CAN_F5R1_FB14

    - -
    -
    - - - - -
    #define CAN_F5R1_FB14   CAN_F5R1_FB14_Msk
    -
    -

    Filter bit 14

    - -
    -
    - -

    ◆ CAN_F5R1_FB15_Pos

    - -
    -
    - - - - -
    #define CAN_F5R1_FB15_Pos   (15U)
    -
    - -
    -
    - -

    ◆ CAN_F5R1_FB15_Msk

    - -
    -
    - - - - -
    #define CAN_F5R1_FB15_Msk   (0x1UL << CAN_F5R1_FB15_Pos)
    -
    -

    0x00008000

    - -
    -
    - -

    ◆ CAN_F5R1_FB15

    - -
    -
    - - - - -
    #define CAN_F5R1_FB15   CAN_F5R1_FB15_Msk
    -
    -

    Filter bit 15

    - -
    -
    - -

    ◆ CAN_F5R1_FB16_Pos

    - -
    -
    - - - - -
    #define CAN_F5R1_FB16_Pos   (16U)
    -
    - -
    -
    - -

    ◆ CAN_F5R1_FB16_Msk

    - -
    -
    - - - - -
    #define CAN_F5R1_FB16_Msk   (0x1UL << CAN_F5R1_FB16_Pos)
    -
    -

    0x00010000

    - -
    -
    - -

    ◆ CAN_F5R1_FB16

    - -
    -
    - - - - -
    #define CAN_F5R1_FB16   CAN_F5R1_FB16_Msk
    -
    -

    Filter bit 16

    - -
    -
    - -

    ◆ CAN_F5R1_FB17_Pos

    - -
    -
    - - - - -
    #define CAN_F5R1_FB17_Pos   (17U)
    -
    - -
    -
    - -

    ◆ CAN_F5R1_FB17_Msk

    - -
    -
    - - - - -
    #define CAN_F5R1_FB17_Msk   (0x1UL << CAN_F5R1_FB17_Pos)
    -
    -

    0x00020000

    - -
    -
    - -

    ◆ CAN_F5R1_FB17

    - -
    -
    - - - - -
    #define CAN_F5R1_FB17   CAN_F5R1_FB17_Msk
    -
    -

    Filter bit 17

    - -
    -
    - -

    ◆ CAN_F5R1_FB18_Pos

    - -
    -
    - - - - -
    #define CAN_F5R1_FB18_Pos   (18U)
    -
    - -
    -
    - -

    ◆ CAN_F5R1_FB18_Msk

    - -
    -
    - - - - -
    #define CAN_F5R1_FB18_Msk   (0x1UL << CAN_F5R1_FB18_Pos)
    -
    -

    0x00040000

    - -
    -
    - -

    ◆ CAN_F5R1_FB18

    - -
    -
    - - - - -
    #define CAN_F5R1_FB18   CAN_F5R1_FB18_Msk
    -
    -

    Filter bit 18

    - -
    -
    - -

    ◆ CAN_F5R1_FB19_Pos

    - -
    -
    - - - - -
    #define CAN_F5R1_FB19_Pos   (19U)
    -
    - -
    -
    - -

    ◆ CAN_F5R1_FB19_Msk

    - -
    -
    - - - - -
    #define CAN_F5R1_FB19_Msk   (0x1UL << CAN_F5R1_FB19_Pos)
    -
    -

    0x00080000

    - -
    -
    - -

    ◆ CAN_F5R1_FB19

    - -
    -
    - - - - -
    #define CAN_F5R1_FB19   CAN_F5R1_FB19_Msk
    -
    -

    Filter bit 19

    - -
    -
    - -

    ◆ CAN_F5R1_FB20_Pos

    - -
    -
    - - - - -
    #define CAN_F5R1_FB20_Pos   (20U)
    -
    - -
    -
    - -

    ◆ CAN_F5R1_FB20_Msk

    - -
    -
    - - - - -
    #define CAN_F5R1_FB20_Msk   (0x1UL << CAN_F5R1_FB20_Pos)
    -
    -

    0x00100000

    - -
    -
    - -

    ◆ CAN_F5R1_FB20

    - -
    -
    - - - - -
    #define CAN_F5R1_FB20   CAN_F5R1_FB20_Msk
    -
    -

    Filter bit 20

    - -
    -
    - -

    ◆ CAN_F5R1_FB21_Pos

    - -
    -
    - - - - -
    #define CAN_F5R1_FB21_Pos   (21U)
    -
    - -
    -
    - -

    ◆ CAN_F5R1_FB21_Msk

    - -
    -
    - - - - -
    #define CAN_F5R1_FB21_Msk   (0x1UL << CAN_F5R1_FB21_Pos)
    -
    -

    0x00200000

    - -
    -
    - -

    ◆ CAN_F5R1_FB21

    - -
    -
    - - - - -
    #define CAN_F5R1_FB21   CAN_F5R1_FB21_Msk
    -
    -

    Filter bit 21

    - -
    -
    - -

    ◆ CAN_F5R1_FB22_Pos

    - -
    -
    - - - - -
    #define CAN_F5R1_FB22_Pos   (22U)
    -
    - -
    -
    - -

    ◆ CAN_F5R1_FB22_Msk

    - -
    -
    - - - - -
    #define CAN_F5R1_FB22_Msk   (0x1UL << CAN_F5R1_FB22_Pos)
    -
    -

    0x00400000

    - -
    -
    - -

    ◆ CAN_F5R1_FB22

    - -
    -
    - - - - -
    #define CAN_F5R1_FB22   CAN_F5R1_FB22_Msk
    -
    -

    Filter bit 22

    - -
    -
    - -

    ◆ CAN_F5R1_FB23_Pos

    - -
    -
    - - - - -
    #define CAN_F5R1_FB23_Pos   (23U)
    -
    - -
    -
    - -

    ◆ CAN_F5R1_FB23_Msk

    - -
    -
    - - - - -
    #define CAN_F5R1_FB23_Msk   (0x1UL << CAN_F5R1_FB23_Pos)
    -
    -

    0x00800000

    - -
    -
    - -

    ◆ CAN_F5R1_FB23

    - -
    -
    - - - - -
    #define CAN_F5R1_FB23   CAN_F5R1_FB23_Msk
    -
    -

    Filter bit 23

    - -
    -
    - -

    ◆ CAN_F5R1_FB24_Pos

    - -
    -
    - - - - -
    #define CAN_F5R1_FB24_Pos   (24U)
    -
    - -
    -
    - -

    ◆ CAN_F5R1_FB24_Msk

    - -
    -
    - - - - -
    #define CAN_F5R1_FB24_Msk   (0x1UL << CAN_F5R1_FB24_Pos)
    -
    -

    0x01000000

    - -
    -
    - -

    ◆ CAN_F5R1_FB24

    - -
    -
    - - - - -
    #define CAN_F5R1_FB24   CAN_F5R1_FB24_Msk
    -
    -

    Filter bit 24

    - -
    -
    - -

    ◆ CAN_F5R1_FB25_Pos

    - -
    -
    - - - - -
    #define CAN_F5R1_FB25_Pos   (25U)
    -
    - -
    -
    - -

    ◆ CAN_F5R1_FB25_Msk

    - -
    -
    - - - - -
    #define CAN_F5R1_FB25_Msk   (0x1UL << CAN_F5R1_FB25_Pos)
    -
    -

    0x02000000

    - -
    -
    - -

    ◆ CAN_F5R1_FB25

    - -
    -
    - - - - -
    #define CAN_F5R1_FB25   CAN_F5R1_FB25_Msk
    -
    -

    Filter bit 25

    - -
    -
    - -

    ◆ CAN_F5R1_FB26_Pos

    - -
    -
    - - - - -
    #define CAN_F5R1_FB26_Pos   (26U)
    -
    - -
    -
    - -

    ◆ CAN_F5R1_FB26_Msk

    - -
    -
    - - - - -
    #define CAN_F5R1_FB26_Msk   (0x1UL << CAN_F5R1_FB26_Pos)
    -
    -

    0x04000000

    - -
    -
    - -

    ◆ CAN_F5R1_FB26

    - -
    -
    - - - - -
    #define CAN_F5R1_FB26   CAN_F5R1_FB26_Msk
    -
    -

    Filter bit 26

    - -
    -
    - -

    ◆ CAN_F5R1_FB27_Pos

    - -
    -
    - - - - -
    #define CAN_F5R1_FB27_Pos   (27U)
    -
    - -
    -
    - -

    ◆ CAN_F5R1_FB27_Msk

    - -
    -
    - - - - -
    #define CAN_F5R1_FB27_Msk   (0x1UL << CAN_F5R1_FB27_Pos)
    -
    -

    0x08000000

    - -
    -
    - -

    ◆ CAN_F5R1_FB27

    - -
    -
    - - - - -
    #define CAN_F5R1_FB27   CAN_F5R1_FB27_Msk
    -
    -

    Filter bit 27

    - -
    -
    - -

    ◆ CAN_F5R1_FB28_Pos

    - -
    -
    - - - - -
    #define CAN_F5R1_FB28_Pos   (28U)
    -
    - -
    -
    - -

    ◆ CAN_F5R1_FB28_Msk

    - -
    -
    - - - - -
    #define CAN_F5R1_FB28_Msk   (0x1UL << CAN_F5R1_FB28_Pos)
    -
    -

    0x10000000

    - -
    -
    - -

    ◆ CAN_F5R1_FB28

    - -
    -
    - - - - -
    #define CAN_F5R1_FB28   CAN_F5R1_FB28_Msk
    -
    -

    Filter bit 28

    - -
    -
    - -

    ◆ CAN_F5R1_FB29_Pos

    - -
    -
    - - - - -
    #define CAN_F5R1_FB29_Pos   (29U)
    -
    - -
    -
    - -

    ◆ CAN_F5R1_FB29_Msk

    - -
    -
    - - - - -
    #define CAN_F5R1_FB29_Msk   (0x1UL << CAN_F5R1_FB29_Pos)
    -
    -

    0x20000000

    - -
    -
    - -

    ◆ CAN_F5R1_FB29

    - -
    -
    - - - - -
    #define CAN_F5R1_FB29   CAN_F5R1_FB29_Msk
    -
    -

    Filter bit 29

    - -
    -
    - -

    ◆ CAN_F5R1_FB30_Pos

    - -
    -
    - - - - -
    #define CAN_F5R1_FB30_Pos   (30U)
    -
    - -
    -
    - -

    ◆ CAN_F5R1_FB30_Msk

    - -
    -
    - - - - -
    #define CAN_F5R1_FB30_Msk   (0x1UL << CAN_F5R1_FB30_Pos)
    -
    -

    0x40000000

    - -
    -
    - -

    ◆ CAN_F5R1_FB30

    - -
    -
    - - - - -
    #define CAN_F5R1_FB30   CAN_F5R1_FB30_Msk
    -
    -

    Filter bit 30

    - -
    -
    - -

    ◆ CAN_F5R1_FB31_Pos

    - -
    -
    - - - - -
    #define CAN_F5R1_FB31_Pos   (31U)
    -
    - -
    -
    - -

    ◆ CAN_F5R1_FB31_Msk

    - -
    -
    - - - - -
    #define CAN_F5R1_FB31_Msk   (0x1UL << CAN_F5R1_FB31_Pos)
    -
    -

    0x80000000

    - -
    -
    - -

    ◆ CAN_F5R1_FB31

    - -
    -
    - - - - -
    #define CAN_F5R1_FB31   CAN_F5R1_FB31_Msk
    -
    -

    Filter bit 31

    - -
    -
    - -

    ◆ CAN_F6R1_FB0_Pos

    - -
    -
    - - - - -
    #define CAN_F6R1_FB0_Pos   (0U)
    -
    - -
    -
    - -

    ◆ CAN_F6R1_FB0_Msk

    - -
    -
    - - - - -
    #define CAN_F6R1_FB0_Msk   (0x1UL << CAN_F6R1_FB0_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ CAN_F6R1_FB0

    - -
    -
    - - - - -
    #define CAN_F6R1_FB0   CAN_F6R1_FB0_Msk
    -
    -

    Filter bit 0

    - -
    -
    - -

    ◆ CAN_F6R1_FB1_Pos

    - -
    -
    - - - - -
    #define CAN_F6R1_FB1_Pos   (1U)
    -
    - -
    -
    - -

    ◆ CAN_F6R1_FB1_Msk

    - -
    -
    - - - - -
    #define CAN_F6R1_FB1_Msk   (0x1UL << CAN_F6R1_FB1_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ CAN_F6R1_FB1

    - -
    -
    - - - - -
    #define CAN_F6R1_FB1   CAN_F6R1_FB1_Msk
    -
    -

    Filter bit 1

    - -
    -
    - -

    ◆ CAN_F6R1_FB2_Pos

    - -
    -
    - - - - -
    #define CAN_F6R1_FB2_Pos   (2U)
    -
    - -
    -
    - -

    ◆ CAN_F6R1_FB2_Msk

    - -
    -
    - - - - -
    #define CAN_F6R1_FB2_Msk   (0x1UL << CAN_F6R1_FB2_Pos)
    -
    -

    0x00000004

    - -
    -
    - -

    ◆ CAN_F6R1_FB2

    - -
    -
    - - - - -
    #define CAN_F6R1_FB2   CAN_F6R1_FB2_Msk
    -
    -

    Filter bit 2

    - -
    -
    - -

    ◆ CAN_F6R1_FB3_Pos

    - -
    -
    - - - - -
    #define CAN_F6R1_FB3_Pos   (3U)
    -
    - -
    -
    - -

    ◆ CAN_F6R1_FB3_Msk

    - -
    -
    - - - - -
    #define CAN_F6R1_FB3_Msk   (0x1UL << CAN_F6R1_FB3_Pos)
    -
    -

    0x00000008

    - -
    -
    - -

    ◆ CAN_F6R1_FB3

    - -
    -
    - - - - -
    #define CAN_F6R1_FB3   CAN_F6R1_FB3_Msk
    -
    -

    Filter bit 3

    - -
    -
    - -

    ◆ CAN_F6R1_FB4_Pos

    - -
    -
    - - - - -
    #define CAN_F6R1_FB4_Pos   (4U)
    -
    - -
    -
    - -

    ◆ CAN_F6R1_FB4_Msk

    - -
    -
    - - - - -
    #define CAN_F6R1_FB4_Msk   (0x1UL << CAN_F6R1_FB4_Pos)
    -
    -

    0x00000010

    - -
    -
    - -

    ◆ CAN_F6R1_FB4

    - -
    -
    - - - - -
    #define CAN_F6R1_FB4   CAN_F6R1_FB4_Msk
    -
    -

    Filter bit 4

    - -
    -
    - -

    ◆ CAN_F6R1_FB5_Pos

    - -
    -
    - - - - -
    #define CAN_F6R1_FB5_Pos   (5U)
    -
    - -
    -
    - -

    ◆ CAN_F6R1_FB5_Msk

    - -
    -
    - - - - -
    #define CAN_F6R1_FB5_Msk   (0x1UL << CAN_F6R1_FB5_Pos)
    -
    -

    0x00000020

    - -
    -
    - -

    ◆ CAN_F6R1_FB5

    - -
    -
    - - - - -
    #define CAN_F6R1_FB5   CAN_F6R1_FB5_Msk
    -
    -

    Filter bit 5

    - -
    -
    - -

    ◆ CAN_F6R1_FB6_Pos

    - -
    -
    - - - - -
    #define CAN_F6R1_FB6_Pos   (6U)
    -
    - -
    -
    - -

    ◆ CAN_F6R1_FB6_Msk

    - -
    -
    - - - - -
    #define CAN_F6R1_FB6_Msk   (0x1UL << CAN_F6R1_FB6_Pos)
    -
    -

    0x00000040

    - -
    -
    - -

    ◆ CAN_F6R1_FB6

    - -
    -
    - - - - -
    #define CAN_F6R1_FB6   CAN_F6R1_FB6_Msk
    -
    -

    Filter bit 6

    - -
    -
    - -

    ◆ CAN_F6R1_FB7_Pos

    - -
    -
    - - - - -
    #define CAN_F6R1_FB7_Pos   (7U)
    -
    - -
    -
    - -

    ◆ CAN_F6R1_FB7_Msk

    - -
    -
    - - - - -
    #define CAN_F6R1_FB7_Msk   (0x1UL << CAN_F6R1_FB7_Pos)
    -
    -

    0x00000080

    - -
    -
    - -

    ◆ CAN_F6R1_FB7

    - -
    -
    - - - - -
    #define CAN_F6R1_FB7   CAN_F6R1_FB7_Msk
    -
    -

    Filter bit 7

    - -
    -
    - -

    ◆ CAN_F6R1_FB8_Pos

    - -
    -
    - - - - -
    #define CAN_F6R1_FB8_Pos   (8U)
    -
    - -
    -
    - -

    ◆ CAN_F6R1_FB8_Msk

    - -
    -
    - - - - -
    #define CAN_F6R1_FB8_Msk   (0x1UL << CAN_F6R1_FB8_Pos)
    -
    -

    0x00000100

    - -
    -
    - -

    ◆ CAN_F6R1_FB8

    - -
    -
    - - - - -
    #define CAN_F6R1_FB8   CAN_F6R1_FB8_Msk
    -
    -

    Filter bit 8

    - -
    -
    - -

    ◆ CAN_F6R1_FB9_Pos

    - -
    -
    - - - - -
    #define CAN_F6R1_FB9_Pos   (9U)
    -
    - -
    -
    - -

    ◆ CAN_F6R1_FB9_Msk

    - -
    -
    - - - - -
    #define CAN_F6R1_FB9_Msk   (0x1UL << CAN_F6R1_FB9_Pos)
    -
    -

    0x00000200

    - -
    -
    - -

    ◆ CAN_F6R1_FB9

    - -
    -
    - - - - -
    #define CAN_F6R1_FB9   CAN_F6R1_FB9_Msk
    -
    -

    Filter bit 9

    - -
    -
    - -

    ◆ CAN_F6R1_FB10_Pos

    - -
    -
    - - - - -
    #define CAN_F6R1_FB10_Pos   (10U)
    -
    - -
    -
    - -

    ◆ CAN_F6R1_FB10_Msk

    - -
    -
    - - - - -
    #define CAN_F6R1_FB10_Msk   (0x1UL << CAN_F6R1_FB10_Pos)
    -
    -

    0x00000400

    - -
    -
    - -

    ◆ CAN_F6R1_FB10

    - -
    -
    - - - - -
    #define CAN_F6R1_FB10   CAN_F6R1_FB10_Msk
    -
    -

    Filter bit 10

    - -
    -
    - -

    ◆ CAN_F6R1_FB11_Pos

    - -
    -
    - - - - -
    #define CAN_F6R1_FB11_Pos   (11U)
    -
    - -
    -
    - -

    ◆ CAN_F6R1_FB11_Msk

    - -
    -
    - - - - -
    #define CAN_F6R1_FB11_Msk   (0x1UL << CAN_F6R1_FB11_Pos)
    -
    -

    0x00000800

    - -
    -
    - -

    ◆ CAN_F6R1_FB11

    - -
    -
    - - - - -
    #define CAN_F6R1_FB11   CAN_F6R1_FB11_Msk
    -
    -

    Filter bit 11

    - -
    -
    - -

    ◆ CAN_F6R1_FB12_Pos

    - -
    -
    - - - - -
    #define CAN_F6R1_FB12_Pos   (12U)
    -
    - -
    -
    - -

    ◆ CAN_F6R1_FB12_Msk

    - -
    -
    - - - - -
    #define CAN_F6R1_FB12_Msk   (0x1UL << CAN_F6R1_FB12_Pos)
    -
    -

    0x00001000

    - -
    -
    - -

    ◆ CAN_F6R1_FB12

    - -
    -
    - - - - -
    #define CAN_F6R1_FB12   CAN_F6R1_FB12_Msk
    -
    -

    Filter bit 12

    - -
    -
    - -

    ◆ CAN_F6R1_FB13_Pos

    - -
    -
    - - - - -
    #define CAN_F6R1_FB13_Pos   (13U)
    -
    - -
    -
    - -

    ◆ CAN_F6R1_FB13_Msk

    - -
    -
    - - - - -
    #define CAN_F6R1_FB13_Msk   (0x1UL << CAN_F6R1_FB13_Pos)
    -
    -

    0x00002000

    - -
    -
    - -

    ◆ CAN_F6R1_FB13

    - -
    -
    - - - - -
    #define CAN_F6R1_FB13   CAN_F6R1_FB13_Msk
    -
    -

    Filter bit 13

    - -
    -
    - -

    ◆ CAN_F6R1_FB14_Pos

    - -
    -
    - - - - -
    #define CAN_F6R1_FB14_Pos   (14U)
    -
    - -
    -
    - -

    ◆ CAN_F6R1_FB14_Msk

    - -
    -
    - - - - -
    #define CAN_F6R1_FB14_Msk   (0x1UL << CAN_F6R1_FB14_Pos)
    -
    -

    0x00004000

    - -
    -
    - -

    ◆ CAN_F6R1_FB14

    - -
    -
    - - - - -
    #define CAN_F6R1_FB14   CAN_F6R1_FB14_Msk
    -
    -

    Filter bit 14

    - -
    -
    - -

    ◆ CAN_F6R1_FB15_Pos

    - -
    -
    - - - - -
    #define CAN_F6R1_FB15_Pos   (15U)
    -
    - -
    -
    - -

    ◆ CAN_F6R1_FB15_Msk

    - -
    -
    - - - - -
    #define CAN_F6R1_FB15_Msk   (0x1UL << CAN_F6R1_FB15_Pos)
    -
    -

    0x00008000

    - -
    -
    - -

    ◆ CAN_F6R1_FB15

    - -
    -
    - - - - -
    #define CAN_F6R1_FB15   CAN_F6R1_FB15_Msk
    -
    -

    Filter bit 15

    - -
    -
    - -

    ◆ CAN_F6R1_FB16_Pos

    - -
    -
    - - - - -
    #define CAN_F6R1_FB16_Pos   (16U)
    -
    - -
    -
    - -

    ◆ CAN_F6R1_FB16_Msk

    - -
    -
    - - - - -
    #define CAN_F6R1_FB16_Msk   (0x1UL << CAN_F6R1_FB16_Pos)
    -
    -

    0x00010000

    - -
    -
    - -

    ◆ CAN_F6R1_FB16

    - -
    -
    - - - - -
    #define CAN_F6R1_FB16   CAN_F6R1_FB16_Msk
    -
    -

    Filter bit 16

    - -
    -
    - -

    ◆ CAN_F6R1_FB17_Pos

    - -
    -
    - - - - -
    #define CAN_F6R1_FB17_Pos   (17U)
    -
    - -
    -
    - -

    ◆ CAN_F6R1_FB17_Msk

    - -
    -
    - - - - -
    #define CAN_F6R1_FB17_Msk   (0x1UL << CAN_F6R1_FB17_Pos)
    -
    -

    0x00020000

    - -
    -
    - -

    ◆ CAN_F6R1_FB17

    - -
    -
    - - - - -
    #define CAN_F6R1_FB17   CAN_F6R1_FB17_Msk
    -
    -

    Filter bit 17

    - -
    -
    - -

    ◆ CAN_F6R1_FB18_Pos

    - -
    -
    - - - - -
    #define CAN_F6R1_FB18_Pos   (18U)
    -
    - -
    -
    - -

    ◆ CAN_F6R1_FB18_Msk

    - -
    -
    - - - - -
    #define CAN_F6R1_FB18_Msk   (0x1UL << CAN_F6R1_FB18_Pos)
    -
    -

    0x00040000

    - -
    -
    - -

    ◆ CAN_F6R1_FB18

    - -
    -
    - - - - -
    #define CAN_F6R1_FB18   CAN_F6R1_FB18_Msk
    -
    -

    Filter bit 18

    - -
    -
    - -

    ◆ CAN_F6R1_FB19_Pos

    - -
    -
    - - - - -
    #define CAN_F6R1_FB19_Pos   (19U)
    -
    - -
    -
    - -

    ◆ CAN_F6R1_FB19_Msk

    - -
    -
    - - - - -
    #define CAN_F6R1_FB19_Msk   (0x1UL << CAN_F6R1_FB19_Pos)
    -
    -

    0x00080000

    - -
    -
    - -

    ◆ CAN_F6R1_FB19

    - -
    -
    - - - - -
    #define CAN_F6R1_FB19   CAN_F6R1_FB19_Msk
    -
    -

    Filter bit 19

    - -
    -
    - -

    ◆ CAN_F6R1_FB20_Pos

    - -
    -
    - - - - -
    #define CAN_F6R1_FB20_Pos   (20U)
    -
    - -
    -
    - -

    ◆ CAN_F6R1_FB20_Msk

    - -
    -
    - - - - -
    #define CAN_F6R1_FB20_Msk   (0x1UL << CAN_F6R1_FB20_Pos)
    -
    -

    0x00100000

    - -
    -
    - -

    ◆ CAN_F6R1_FB20

    - -
    -
    - - - - -
    #define CAN_F6R1_FB20   CAN_F6R1_FB20_Msk
    -
    -

    Filter bit 20

    - -
    -
    - -

    ◆ CAN_F6R1_FB21_Pos

    - -
    -
    - - - - -
    #define CAN_F6R1_FB21_Pos   (21U)
    -
    - -
    -
    - -

    ◆ CAN_F6R1_FB21_Msk

    - -
    -
    - - - - -
    #define CAN_F6R1_FB21_Msk   (0x1UL << CAN_F6R1_FB21_Pos)
    -
    -

    0x00200000

    - -
    -
    - -

    ◆ CAN_F6R1_FB21

    - -
    -
    - - - - -
    #define CAN_F6R1_FB21   CAN_F6R1_FB21_Msk
    -
    -

    Filter bit 21

    - -
    -
    - -

    ◆ CAN_F6R1_FB22_Pos

    - -
    -
    - - - - -
    #define CAN_F6R1_FB22_Pos   (22U)
    -
    - -
    -
    - -

    ◆ CAN_F6R1_FB22_Msk

    - -
    -
    - - - - -
    #define CAN_F6R1_FB22_Msk   (0x1UL << CAN_F6R1_FB22_Pos)
    -
    -

    0x00400000

    - -
    -
    - -

    ◆ CAN_F6R1_FB22

    - -
    -
    - - - - -
    #define CAN_F6R1_FB22   CAN_F6R1_FB22_Msk
    -
    -

    Filter bit 22

    - -
    -
    - -

    ◆ CAN_F6R1_FB23_Pos

    - -
    -
    - - - - -
    #define CAN_F6R1_FB23_Pos   (23U)
    -
    - -
    -
    - -

    ◆ CAN_F6R1_FB23_Msk

    - -
    -
    - - - - -
    #define CAN_F6R1_FB23_Msk   (0x1UL << CAN_F6R1_FB23_Pos)
    -
    -

    0x00800000

    - -
    -
    - -

    ◆ CAN_F6R1_FB23

    - -
    -
    - - - - -
    #define CAN_F6R1_FB23   CAN_F6R1_FB23_Msk
    -
    -

    Filter bit 23

    - -
    -
    - -

    ◆ CAN_F6R1_FB24_Pos

    - -
    -
    - - - - -
    #define CAN_F6R1_FB24_Pos   (24U)
    -
    - -
    -
    - -

    ◆ CAN_F6R1_FB24_Msk

    - -
    -
    - - - - -
    #define CAN_F6R1_FB24_Msk   (0x1UL << CAN_F6R1_FB24_Pos)
    -
    -

    0x01000000

    - -
    -
    - -

    ◆ CAN_F6R1_FB24

    - -
    -
    - - - - -
    #define CAN_F6R1_FB24   CAN_F6R1_FB24_Msk
    -
    -

    Filter bit 24

    - -
    -
    - -

    ◆ CAN_F6R1_FB25_Pos

    - -
    -
    - - - - -
    #define CAN_F6R1_FB25_Pos   (25U)
    -
    - -
    -
    - -

    ◆ CAN_F6R1_FB25_Msk

    - -
    -
    - - - - -
    #define CAN_F6R1_FB25_Msk   (0x1UL << CAN_F6R1_FB25_Pos)
    -
    -

    0x02000000

    - -
    -
    - -

    ◆ CAN_F6R1_FB25

    - -
    -
    - - - - -
    #define CAN_F6R1_FB25   CAN_F6R1_FB25_Msk
    -
    -

    Filter bit 25

    - -
    -
    - -

    ◆ CAN_F6R1_FB26_Pos

    - -
    -
    - - - - -
    #define CAN_F6R1_FB26_Pos   (26U)
    -
    - -
    -
    - -

    ◆ CAN_F6R1_FB26_Msk

    - -
    -
    - - - - -
    #define CAN_F6R1_FB26_Msk   (0x1UL << CAN_F6R1_FB26_Pos)
    -
    -

    0x04000000

    - -
    -
    - -

    ◆ CAN_F6R1_FB26

    - -
    -
    - - - - -
    #define CAN_F6R1_FB26   CAN_F6R1_FB26_Msk
    -
    -

    Filter bit 26

    - -
    -
    - -

    ◆ CAN_F6R1_FB27_Pos

    - -
    -
    - - - - -
    #define CAN_F6R1_FB27_Pos   (27U)
    -
    - -
    -
    - -

    ◆ CAN_F6R1_FB27_Msk

    - -
    -
    - - - - -
    #define CAN_F6R1_FB27_Msk   (0x1UL << CAN_F6R1_FB27_Pos)
    -
    -

    0x08000000

    - -
    -
    - -

    ◆ CAN_F6R1_FB27

    - -
    -
    - - - - -
    #define CAN_F6R1_FB27   CAN_F6R1_FB27_Msk
    -
    -

    Filter bit 27

    - -
    -
    - -

    ◆ CAN_F6R1_FB28_Pos

    - -
    -
    - - - - -
    #define CAN_F6R1_FB28_Pos   (28U)
    -
    - -
    -
    - -

    ◆ CAN_F6R1_FB28_Msk

    - -
    -
    - - - - -
    #define CAN_F6R1_FB28_Msk   (0x1UL << CAN_F6R1_FB28_Pos)
    -
    -

    0x10000000

    - -
    -
    - -

    ◆ CAN_F6R1_FB28

    - -
    -
    - - - - -
    #define CAN_F6R1_FB28   CAN_F6R1_FB28_Msk
    -
    -

    Filter bit 28

    - -
    -
    - -

    ◆ CAN_F6R1_FB29_Pos

    - -
    -
    - - - - -
    #define CAN_F6R1_FB29_Pos   (29U)
    -
    - -
    -
    - -

    ◆ CAN_F6R1_FB29_Msk

    - -
    -
    - - - - -
    #define CAN_F6R1_FB29_Msk   (0x1UL << CAN_F6R1_FB29_Pos)
    -
    -

    0x20000000

    - -
    -
    - -

    ◆ CAN_F6R1_FB29

    - -
    -
    - - - - -
    #define CAN_F6R1_FB29   CAN_F6R1_FB29_Msk
    -
    -

    Filter bit 29

    - -
    -
    - -

    ◆ CAN_F6R1_FB30_Pos

    - -
    -
    - - - - -
    #define CAN_F6R1_FB30_Pos   (30U)
    -
    - -
    -
    - -

    ◆ CAN_F6R1_FB30_Msk

    - -
    -
    - - - - -
    #define CAN_F6R1_FB30_Msk   (0x1UL << CAN_F6R1_FB30_Pos)
    -
    -

    0x40000000

    - -
    -
    - -

    ◆ CAN_F6R1_FB30

    - -
    -
    - - - - -
    #define CAN_F6R1_FB30   CAN_F6R1_FB30_Msk
    -
    -

    Filter bit 30

    - -
    -
    - -

    ◆ CAN_F6R1_FB31_Pos

    - -
    -
    - - - - -
    #define CAN_F6R1_FB31_Pos   (31U)
    -
    - -
    -
    - -

    ◆ CAN_F6R1_FB31_Msk

    - -
    -
    - - - - -
    #define CAN_F6R1_FB31_Msk   (0x1UL << CAN_F6R1_FB31_Pos)
    -
    -

    0x80000000

    - -
    -
    - -

    ◆ CAN_F6R1_FB31

    - -
    -
    - - - - -
    #define CAN_F6R1_FB31   CAN_F6R1_FB31_Msk
    -
    -

    Filter bit 31

    - -
    -
    - -

    ◆ CAN_F7R1_FB0_Pos

    - -
    -
    - - - - -
    #define CAN_F7R1_FB0_Pos   (0U)
    -
    - -
    -
    - -

    ◆ CAN_F7R1_FB0_Msk

    - -
    -
    - - - - -
    #define CAN_F7R1_FB0_Msk   (0x1UL << CAN_F7R1_FB0_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ CAN_F7R1_FB0

    - -
    -
    - - - - -
    #define CAN_F7R1_FB0   CAN_F7R1_FB0_Msk
    -
    -

    Filter bit 0

    - -
    -
    - -

    ◆ CAN_F7R1_FB1_Pos

    - -
    -
    - - - - -
    #define CAN_F7R1_FB1_Pos   (1U)
    -
    - -
    -
    - -

    ◆ CAN_F7R1_FB1_Msk

    - -
    -
    - - - - -
    #define CAN_F7R1_FB1_Msk   (0x1UL << CAN_F7R1_FB1_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ CAN_F7R1_FB1

    - -
    -
    - - - - -
    #define CAN_F7R1_FB1   CAN_F7R1_FB1_Msk
    -
    -

    Filter bit 1

    - -
    -
    - -

    ◆ CAN_F7R1_FB2_Pos

    - -
    -
    - - - - -
    #define CAN_F7R1_FB2_Pos   (2U)
    -
    - -
    -
    - -

    ◆ CAN_F7R1_FB2_Msk

    - -
    -
    - - - - -
    #define CAN_F7R1_FB2_Msk   (0x1UL << CAN_F7R1_FB2_Pos)
    -
    -

    0x00000004

    - -
    -
    - -

    ◆ CAN_F7R1_FB2

    - -
    -
    - - - - -
    #define CAN_F7R1_FB2   CAN_F7R1_FB2_Msk
    -
    -

    Filter bit 2

    - -
    -
    - -

    ◆ CAN_F7R1_FB3_Pos

    - -
    -
    - - - - -
    #define CAN_F7R1_FB3_Pos   (3U)
    -
    - -
    -
    - -

    ◆ CAN_F7R1_FB3_Msk

    - -
    -
    - - - - -
    #define CAN_F7R1_FB3_Msk   (0x1UL << CAN_F7R1_FB3_Pos)
    -
    -

    0x00000008

    - -
    -
    - -

    ◆ CAN_F7R1_FB3

    - -
    -
    - - - - -
    #define CAN_F7R1_FB3   CAN_F7R1_FB3_Msk
    -
    -

    Filter bit 3

    - -
    -
    - -

    ◆ CAN_F7R1_FB4_Pos

    - -
    -
    - - - - -
    #define CAN_F7R1_FB4_Pos   (4U)
    -
    - -
    -
    - -

    ◆ CAN_F7R1_FB4_Msk

    - -
    -
    - - - - -
    #define CAN_F7R1_FB4_Msk   (0x1UL << CAN_F7R1_FB4_Pos)
    -
    -

    0x00000010

    - -
    -
    - -

    ◆ CAN_F7R1_FB4

    - -
    -
    - - - - -
    #define CAN_F7R1_FB4   CAN_F7R1_FB4_Msk
    -
    -

    Filter bit 4

    - -
    -
    - -

    ◆ CAN_F7R1_FB5_Pos

    - -
    -
    - - - - -
    #define CAN_F7R1_FB5_Pos   (5U)
    -
    - -
    -
    - -

    ◆ CAN_F7R1_FB5_Msk

    - -
    -
    - - - - -
    #define CAN_F7R1_FB5_Msk   (0x1UL << CAN_F7R1_FB5_Pos)
    -
    -

    0x00000020

    - -
    -
    - -

    ◆ CAN_F7R1_FB5

    - -
    -
    - - - - -
    #define CAN_F7R1_FB5   CAN_F7R1_FB5_Msk
    -
    -

    Filter bit 5

    - -
    -
    - -

    ◆ CAN_F7R1_FB6_Pos

    - -
    -
    - - - - -
    #define CAN_F7R1_FB6_Pos   (6U)
    -
    - -
    -
    - -

    ◆ CAN_F7R1_FB6_Msk

    - -
    -
    - - - - -
    #define CAN_F7R1_FB6_Msk   (0x1UL << CAN_F7R1_FB6_Pos)
    -
    -

    0x00000040

    - -
    -
    - -

    ◆ CAN_F7R1_FB6

    - -
    -
    - - - - -
    #define CAN_F7R1_FB6   CAN_F7R1_FB6_Msk
    -
    -

    Filter bit 6

    - -
    -
    - -

    ◆ CAN_F7R1_FB7_Pos

    - -
    -
    - - - - -
    #define CAN_F7R1_FB7_Pos   (7U)
    -
    - -
    -
    - -

    ◆ CAN_F7R1_FB7_Msk

    - -
    -
    - - - - -
    #define CAN_F7R1_FB7_Msk   (0x1UL << CAN_F7R1_FB7_Pos)
    -
    -

    0x00000080

    - -
    -
    - -

    ◆ CAN_F7R1_FB7

    - -
    -
    - - - - -
    #define CAN_F7R1_FB7   CAN_F7R1_FB7_Msk
    -
    -

    Filter bit 7

    - -
    -
    - -

    ◆ CAN_F7R1_FB8_Pos

    - -
    -
    - - - - -
    #define CAN_F7R1_FB8_Pos   (8U)
    -
    - -
    -
    - -

    ◆ CAN_F7R1_FB8_Msk

    - -
    -
    - - - - -
    #define CAN_F7R1_FB8_Msk   (0x1UL << CAN_F7R1_FB8_Pos)
    -
    -

    0x00000100

    - -
    -
    - -

    ◆ CAN_F7R1_FB8

    - -
    -
    - - - - -
    #define CAN_F7R1_FB8   CAN_F7R1_FB8_Msk
    -
    -

    Filter bit 8

    - -
    -
    - -

    ◆ CAN_F7R1_FB9_Pos

    - -
    -
    - - - - -
    #define CAN_F7R1_FB9_Pos   (9U)
    -
    - -
    -
    - -

    ◆ CAN_F7R1_FB9_Msk

    - -
    -
    - - - - -
    #define CAN_F7R1_FB9_Msk   (0x1UL << CAN_F7R1_FB9_Pos)
    -
    -

    0x00000200

    - -
    -
    - -

    ◆ CAN_F7R1_FB9

    - -
    -
    - - - - -
    #define CAN_F7R1_FB9   CAN_F7R1_FB9_Msk
    -
    -

    Filter bit 9

    - -
    -
    - -

    ◆ CAN_F7R1_FB10_Pos

    - -
    -
    - - - - -
    #define CAN_F7R1_FB10_Pos   (10U)
    -
    - -
    -
    - -

    ◆ CAN_F7R1_FB10_Msk

    - -
    -
    - - - - -
    #define CAN_F7R1_FB10_Msk   (0x1UL << CAN_F7R1_FB10_Pos)
    -
    -

    0x00000400

    - -
    -
    - -

    ◆ CAN_F7R1_FB10

    - -
    -
    - - - - -
    #define CAN_F7R1_FB10   CAN_F7R1_FB10_Msk
    -
    -

    Filter bit 10

    - -
    -
    - -

    ◆ CAN_F7R1_FB11_Pos

    - -
    -
    - - - - -
    #define CAN_F7R1_FB11_Pos   (11U)
    -
    - -
    -
    - -

    ◆ CAN_F7R1_FB11_Msk

    - -
    -
    - - - - -
    #define CAN_F7R1_FB11_Msk   (0x1UL << CAN_F7R1_FB11_Pos)
    -
    -

    0x00000800

    - -
    -
    - -

    ◆ CAN_F7R1_FB11

    - -
    -
    - - - - -
    #define CAN_F7R1_FB11   CAN_F7R1_FB11_Msk
    -
    -

    Filter bit 11

    - -
    -
    - -

    ◆ CAN_F7R1_FB12_Pos

    - -
    -
    - - - - -
    #define CAN_F7R1_FB12_Pos   (12U)
    -
    - -
    -
    - -

    ◆ CAN_F7R1_FB12_Msk

    - -
    -
    - - - - -
    #define CAN_F7R1_FB12_Msk   (0x1UL << CAN_F7R1_FB12_Pos)
    -
    -

    0x00001000

    - -
    -
    - -

    ◆ CAN_F7R1_FB12

    - -
    -
    - - - - -
    #define CAN_F7R1_FB12   CAN_F7R1_FB12_Msk
    -
    -

    Filter bit 12

    - -
    -
    - -

    ◆ CAN_F7R1_FB13_Pos

    - -
    -
    - - - - -
    #define CAN_F7R1_FB13_Pos   (13U)
    -
    - -
    -
    - -

    ◆ CAN_F7R1_FB13_Msk

    - -
    -
    - - - - -
    #define CAN_F7R1_FB13_Msk   (0x1UL << CAN_F7R1_FB13_Pos)
    -
    -

    0x00002000

    - -
    -
    - -

    ◆ CAN_F7R1_FB13

    - -
    -
    - - - - -
    #define CAN_F7R1_FB13   CAN_F7R1_FB13_Msk
    -
    -

    Filter bit 13

    - -
    -
    - -

    ◆ CAN_F7R1_FB14_Pos

    - -
    -
    - - - - -
    #define CAN_F7R1_FB14_Pos   (14U)
    -
    - -
    -
    - -

    ◆ CAN_F7R1_FB14_Msk

    - -
    -
    - - - - -
    #define CAN_F7R1_FB14_Msk   (0x1UL << CAN_F7R1_FB14_Pos)
    -
    -

    0x00004000

    - -
    -
    - -

    ◆ CAN_F7R1_FB14

    - -
    -
    - - - - -
    #define CAN_F7R1_FB14   CAN_F7R1_FB14_Msk
    -
    -

    Filter bit 14

    - -
    -
    - -

    ◆ CAN_F7R1_FB15_Pos

    - -
    -
    - - - - -
    #define CAN_F7R1_FB15_Pos   (15U)
    -
    - -
    -
    - -

    ◆ CAN_F7R1_FB15_Msk

    - -
    -
    - - - - -
    #define CAN_F7R1_FB15_Msk   (0x1UL << CAN_F7R1_FB15_Pos)
    -
    -

    0x00008000

    - -
    -
    - -

    ◆ CAN_F7R1_FB15

    - -
    -
    - - - - -
    #define CAN_F7R1_FB15   CAN_F7R1_FB15_Msk
    -
    -

    Filter bit 15

    - -
    -
    - -

    ◆ CAN_F7R1_FB16_Pos

    - -
    -
    - - - - -
    #define CAN_F7R1_FB16_Pos   (16U)
    -
    - -
    -
    - -

    ◆ CAN_F7R1_FB16_Msk

    - -
    -
    - - - - -
    #define CAN_F7R1_FB16_Msk   (0x1UL << CAN_F7R1_FB16_Pos)
    -
    -

    0x00010000

    - -
    -
    - -

    ◆ CAN_F7R1_FB16

    - -
    -
    - - - - -
    #define CAN_F7R1_FB16   CAN_F7R1_FB16_Msk
    -
    -

    Filter bit 16

    - -
    -
    - -

    ◆ CAN_F7R1_FB17_Pos

    - -
    -
    - - - - -
    #define CAN_F7R1_FB17_Pos   (17U)
    -
    - -
    -
    - -

    ◆ CAN_F7R1_FB17_Msk

    - -
    -
    - - - - -
    #define CAN_F7R1_FB17_Msk   (0x1UL << CAN_F7R1_FB17_Pos)
    -
    -

    0x00020000

    - -
    -
    - -

    ◆ CAN_F7R1_FB17

    - -
    -
    - - - - -
    #define CAN_F7R1_FB17   CAN_F7R1_FB17_Msk
    -
    -

    Filter bit 17

    - -
    -
    - -

    ◆ CAN_F7R1_FB18_Pos

    - -
    -
    - - - - -
    #define CAN_F7R1_FB18_Pos   (18U)
    -
    - -
    -
    - -

    ◆ CAN_F7R1_FB18_Msk

    - -
    -
    - - - - -
    #define CAN_F7R1_FB18_Msk   (0x1UL << CAN_F7R1_FB18_Pos)
    -
    -

    0x00040000

    - -
    -
    - -

    ◆ CAN_F7R1_FB18

    - -
    -
    - - - - -
    #define CAN_F7R1_FB18   CAN_F7R1_FB18_Msk
    -
    -

    Filter bit 18

    - -
    -
    - -

    ◆ CAN_F7R1_FB19_Pos

    - -
    -
    - - - - -
    #define CAN_F7R1_FB19_Pos   (19U)
    -
    - -
    -
    - -

    ◆ CAN_F7R1_FB19_Msk

    - -
    -
    - - - - -
    #define CAN_F7R1_FB19_Msk   (0x1UL << CAN_F7R1_FB19_Pos)
    -
    -

    0x00080000

    - -
    -
    - -

    ◆ CAN_F7R1_FB19

    - -
    -
    - - - - -
    #define CAN_F7R1_FB19   CAN_F7R1_FB19_Msk
    -
    -

    Filter bit 19

    - -
    -
    - -

    ◆ CAN_F7R1_FB20_Pos

    - -
    -
    - - - - -
    #define CAN_F7R1_FB20_Pos   (20U)
    -
    - -
    -
    - -

    ◆ CAN_F7R1_FB20_Msk

    - -
    -
    - - - - -
    #define CAN_F7R1_FB20_Msk   (0x1UL << CAN_F7R1_FB20_Pos)
    -
    -

    0x00100000

    - -
    -
    - -

    ◆ CAN_F7R1_FB20

    - -
    -
    - - - - -
    #define CAN_F7R1_FB20   CAN_F7R1_FB20_Msk
    -
    -

    Filter bit 20

    - -
    -
    - -

    ◆ CAN_F7R1_FB21_Pos

    - -
    -
    - - - - -
    #define CAN_F7R1_FB21_Pos   (21U)
    -
    - -
    -
    - -

    ◆ CAN_F7R1_FB21_Msk

    - -
    -
    - - - - -
    #define CAN_F7R1_FB21_Msk   (0x1UL << CAN_F7R1_FB21_Pos)
    -
    -

    0x00200000

    - -
    -
    - -

    ◆ CAN_F7R1_FB21

    - -
    -
    - - - - -
    #define CAN_F7R1_FB21   CAN_F7R1_FB21_Msk
    -
    -

    Filter bit 21

    - -
    -
    - -

    ◆ CAN_F7R1_FB22_Pos

    - -
    -
    - - - - -
    #define CAN_F7R1_FB22_Pos   (22U)
    -
    - -
    -
    - -

    ◆ CAN_F7R1_FB22_Msk

    - -
    -
    - - - - -
    #define CAN_F7R1_FB22_Msk   (0x1UL << CAN_F7R1_FB22_Pos)
    -
    -

    0x00400000

    - -
    -
    - -

    ◆ CAN_F7R1_FB22

    - -
    -
    - - - - -
    #define CAN_F7R1_FB22   CAN_F7R1_FB22_Msk
    -
    -

    Filter bit 22

    - -
    -
    - -

    ◆ CAN_F7R1_FB23_Pos

    - -
    -
    - - - - -
    #define CAN_F7R1_FB23_Pos   (23U)
    -
    - -
    -
    - -

    ◆ CAN_F7R1_FB23_Msk

    - -
    -
    - - - - -
    #define CAN_F7R1_FB23_Msk   (0x1UL << CAN_F7R1_FB23_Pos)
    -
    -

    0x00800000

    - -
    -
    - -

    ◆ CAN_F7R1_FB23

    - -
    -
    - - - - -
    #define CAN_F7R1_FB23   CAN_F7R1_FB23_Msk
    -
    -

    Filter bit 23

    - -
    -
    - -

    ◆ CAN_F7R1_FB24_Pos

    - -
    -
    - - - - -
    #define CAN_F7R1_FB24_Pos   (24U)
    -
    - -
    -
    - -

    ◆ CAN_F7R1_FB24_Msk

    - -
    -
    - - - - -
    #define CAN_F7R1_FB24_Msk   (0x1UL << CAN_F7R1_FB24_Pos)
    -
    -

    0x01000000

    - -
    -
    - -

    ◆ CAN_F7R1_FB24

    - -
    -
    - - - - -
    #define CAN_F7R1_FB24   CAN_F7R1_FB24_Msk
    -
    -

    Filter bit 24

    - -
    -
    - -

    ◆ CAN_F7R1_FB25_Pos

    - -
    -
    - - - - -
    #define CAN_F7R1_FB25_Pos   (25U)
    -
    - -
    -
    - -

    ◆ CAN_F7R1_FB25_Msk

    - -
    -
    - - - - -
    #define CAN_F7R1_FB25_Msk   (0x1UL << CAN_F7R1_FB25_Pos)
    -
    -

    0x02000000

    - -
    -
    - -

    ◆ CAN_F7R1_FB25

    - -
    -
    - - - - -
    #define CAN_F7R1_FB25   CAN_F7R1_FB25_Msk
    -
    -

    Filter bit 25

    - -
    -
    - -

    ◆ CAN_F7R1_FB26_Pos

    - -
    -
    - - - - -
    #define CAN_F7R1_FB26_Pos   (26U)
    -
    - -
    -
    - -

    ◆ CAN_F7R1_FB26_Msk

    - -
    -
    - - - - -
    #define CAN_F7R1_FB26_Msk   (0x1UL << CAN_F7R1_FB26_Pos)
    -
    -

    0x04000000

    - -
    -
    - -

    ◆ CAN_F7R1_FB26

    - -
    -
    - - - - -
    #define CAN_F7R1_FB26   CAN_F7R1_FB26_Msk
    -
    -

    Filter bit 26

    - -
    -
    - -

    ◆ CAN_F7R1_FB27_Pos

    - -
    -
    - - - - -
    #define CAN_F7R1_FB27_Pos   (27U)
    -
    - -
    -
    - -

    ◆ CAN_F7R1_FB27_Msk

    - -
    -
    - - - - -
    #define CAN_F7R1_FB27_Msk   (0x1UL << CAN_F7R1_FB27_Pos)
    -
    -

    0x08000000

    - -
    -
    - -

    ◆ CAN_F7R1_FB27

    - -
    -
    - - - - -
    #define CAN_F7R1_FB27   CAN_F7R1_FB27_Msk
    -
    -

    Filter bit 27

    - -
    -
    - -

    ◆ CAN_F7R1_FB28_Pos

    - -
    -
    - - - - -
    #define CAN_F7R1_FB28_Pos   (28U)
    -
    - -
    -
    - -

    ◆ CAN_F7R1_FB28_Msk

    - -
    -
    - - - - -
    #define CAN_F7R1_FB28_Msk   (0x1UL << CAN_F7R1_FB28_Pos)
    -
    -

    0x10000000

    - -
    -
    - -

    ◆ CAN_F7R1_FB28

    - -
    -
    - - - - -
    #define CAN_F7R1_FB28   CAN_F7R1_FB28_Msk
    -
    -

    Filter bit 28

    - -
    -
    - -

    ◆ CAN_F7R1_FB29_Pos

    - -
    -
    - - - - -
    #define CAN_F7R1_FB29_Pos   (29U)
    -
    - -
    -
    - -

    ◆ CAN_F7R1_FB29_Msk

    - -
    -
    - - - - -
    #define CAN_F7R1_FB29_Msk   (0x1UL << CAN_F7R1_FB29_Pos)
    -
    -

    0x20000000

    - -
    -
    - -

    ◆ CAN_F7R1_FB29

    - -
    -
    - - - - -
    #define CAN_F7R1_FB29   CAN_F7R1_FB29_Msk
    -
    -

    Filter bit 29

    - -
    -
    - -

    ◆ CAN_F7R1_FB30_Pos

    - -
    -
    - - - - -
    #define CAN_F7R1_FB30_Pos   (30U)
    -
    - -
    -
    - -

    ◆ CAN_F7R1_FB30_Msk

    - -
    -
    - - - - -
    #define CAN_F7R1_FB30_Msk   (0x1UL << CAN_F7R1_FB30_Pos)
    -
    -

    0x40000000

    - -
    -
    - -

    ◆ CAN_F7R1_FB30

    - -
    -
    - - - - -
    #define CAN_F7R1_FB30   CAN_F7R1_FB30_Msk
    -
    -

    Filter bit 30

    - -
    -
    - -

    ◆ CAN_F7R1_FB31_Pos

    - -
    -
    - - - - -
    #define CAN_F7R1_FB31_Pos   (31U)
    -
    - -
    -
    - -

    ◆ CAN_F7R1_FB31_Msk

    - -
    -
    - - - - -
    #define CAN_F7R1_FB31_Msk   (0x1UL << CAN_F7R1_FB31_Pos)
    -
    -

    0x80000000

    - -
    -
    - -

    ◆ CAN_F7R1_FB31

    - -
    -
    - - - - -
    #define CAN_F7R1_FB31   CAN_F7R1_FB31_Msk
    -
    -

    Filter bit 31

    - -
    -
    - -

    ◆ CAN_F8R1_FB0_Pos

    - -
    -
    - - - - -
    #define CAN_F8R1_FB0_Pos   (0U)
    -
    - -
    -
    - -

    ◆ CAN_F8R1_FB0_Msk

    - -
    -
    - - - - -
    #define CAN_F8R1_FB0_Msk   (0x1UL << CAN_F8R1_FB0_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ CAN_F8R1_FB0

    - -
    -
    - - - - -
    #define CAN_F8R1_FB0   CAN_F8R1_FB0_Msk
    -
    -

    Filter bit 0

    - -
    -
    - -

    ◆ CAN_F8R1_FB1_Pos

    - -
    -
    - - - - -
    #define CAN_F8R1_FB1_Pos   (1U)
    -
    - -
    -
    - -

    ◆ CAN_F8R1_FB1_Msk

    - -
    -
    - - - - -
    #define CAN_F8R1_FB1_Msk   (0x1UL << CAN_F8R1_FB1_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ CAN_F8R1_FB1

    - -
    -
    - - - - -
    #define CAN_F8R1_FB1   CAN_F8R1_FB1_Msk
    -
    -

    Filter bit 1

    - -
    -
    - -

    ◆ CAN_F8R1_FB2_Pos

    - -
    -
    - - - - -
    #define CAN_F8R1_FB2_Pos   (2U)
    -
    - -
    -
    - -

    ◆ CAN_F8R1_FB2_Msk

    - -
    -
    - - - - -
    #define CAN_F8R1_FB2_Msk   (0x1UL << CAN_F8R1_FB2_Pos)
    -
    -

    0x00000004

    - -
    -
    - -

    ◆ CAN_F8R1_FB2

    - -
    -
    - - - - -
    #define CAN_F8R1_FB2   CAN_F8R1_FB2_Msk
    -
    -

    Filter bit 2

    - -
    -
    - -

    ◆ CAN_F8R1_FB3_Pos

    - -
    -
    - - - - -
    #define CAN_F8R1_FB3_Pos   (3U)
    -
    - -
    -
    - -

    ◆ CAN_F8R1_FB3_Msk

    - -
    -
    - - - - -
    #define CAN_F8R1_FB3_Msk   (0x1UL << CAN_F8R1_FB3_Pos)
    -
    -

    0x00000008

    - -
    -
    - -

    ◆ CAN_F8R1_FB3

    - -
    -
    - - - - -
    #define CAN_F8R1_FB3   CAN_F8R1_FB3_Msk
    -
    -

    Filter bit 3

    - -
    -
    - -

    ◆ CAN_F8R1_FB4_Pos

    - -
    -
    - - - - -
    #define CAN_F8R1_FB4_Pos   (4U)
    -
    - -
    -
    - -

    ◆ CAN_F8R1_FB4_Msk

    - -
    -
    - - - - -
    #define CAN_F8R1_FB4_Msk   (0x1UL << CAN_F8R1_FB4_Pos)
    -
    -

    0x00000010

    - -
    -
    - -

    ◆ CAN_F8R1_FB4

    - -
    -
    - - - - -
    #define CAN_F8R1_FB4   CAN_F8R1_FB4_Msk
    -
    -

    Filter bit 4

    - -
    -
    - -

    ◆ CAN_F8R1_FB5_Pos

    - -
    -
    - - - - -
    #define CAN_F8R1_FB5_Pos   (5U)
    -
    - -
    -
    - -

    ◆ CAN_F8R1_FB5_Msk

    - -
    -
    - - - - -
    #define CAN_F8R1_FB5_Msk   (0x1UL << CAN_F8R1_FB5_Pos)
    -
    -

    0x00000020

    - -
    -
    - -

    ◆ CAN_F8R1_FB5

    - -
    -
    - - - - -
    #define CAN_F8R1_FB5   CAN_F8R1_FB5_Msk
    -
    -

    Filter bit 5

    - -
    -
    - -

    ◆ CAN_F8R1_FB6_Pos

    - -
    -
    - - - - -
    #define CAN_F8R1_FB6_Pos   (6U)
    -
    - -
    -
    - -

    ◆ CAN_F8R1_FB6_Msk

    - -
    -
    - - - - -
    #define CAN_F8R1_FB6_Msk   (0x1UL << CAN_F8R1_FB6_Pos)
    -
    -

    0x00000040

    - -
    -
    - -

    ◆ CAN_F8R1_FB6

    - -
    -
    - - - - -
    #define CAN_F8R1_FB6   CAN_F8R1_FB6_Msk
    -
    -

    Filter bit 6

    - -
    -
    - -

    ◆ CAN_F8R1_FB7_Pos

    - -
    -
    - - - - -
    #define CAN_F8R1_FB7_Pos   (7U)
    -
    - -
    -
    - -

    ◆ CAN_F8R1_FB7_Msk

    - -
    -
    - - - - -
    #define CAN_F8R1_FB7_Msk   (0x1UL << CAN_F8R1_FB7_Pos)
    -
    -

    0x00000080

    - -
    -
    - -

    ◆ CAN_F8R1_FB7

    - -
    -
    - - - - -
    #define CAN_F8R1_FB7   CAN_F8R1_FB7_Msk
    -
    -

    Filter bit 7

    - -
    -
    - -

    ◆ CAN_F8R1_FB8_Pos

    - -
    -
    - - - - -
    #define CAN_F8R1_FB8_Pos   (8U)
    -
    - -
    -
    - -

    ◆ CAN_F8R1_FB8_Msk

    - -
    -
    - - - - -
    #define CAN_F8R1_FB8_Msk   (0x1UL << CAN_F8R1_FB8_Pos)
    -
    -

    0x00000100

    - -
    -
    - -

    ◆ CAN_F8R1_FB8

    - -
    -
    - - - - -
    #define CAN_F8R1_FB8   CAN_F8R1_FB8_Msk
    -
    -

    Filter bit 8

    - -
    -
    - -

    ◆ CAN_F8R1_FB9_Pos

    - -
    -
    - - - - -
    #define CAN_F8R1_FB9_Pos   (9U)
    -
    - -
    -
    - -

    ◆ CAN_F8R1_FB9_Msk

    - -
    -
    - - - - -
    #define CAN_F8R1_FB9_Msk   (0x1UL << CAN_F8R1_FB9_Pos)
    -
    -

    0x00000200

    - -
    -
    - -

    ◆ CAN_F8R1_FB9

    - -
    -
    - - - - -
    #define CAN_F8R1_FB9   CAN_F8R1_FB9_Msk
    -
    -

    Filter bit 9

    - -
    -
    - -

    ◆ CAN_F8R1_FB10_Pos

    - -
    -
    - - - - -
    #define CAN_F8R1_FB10_Pos   (10U)
    -
    - -
    -
    - -

    ◆ CAN_F8R1_FB10_Msk

    - -
    -
    - - - - -
    #define CAN_F8R1_FB10_Msk   (0x1UL << CAN_F8R1_FB10_Pos)
    -
    -

    0x00000400

    - -
    -
    - -

    ◆ CAN_F8R1_FB10

    - -
    -
    - - - - -
    #define CAN_F8R1_FB10   CAN_F8R1_FB10_Msk
    -
    -

    Filter bit 10

    - -
    -
    - -

    ◆ CAN_F8R1_FB11_Pos

    - -
    -
    - - - - -
    #define CAN_F8R1_FB11_Pos   (11U)
    -
    - -
    -
    - -

    ◆ CAN_F8R1_FB11_Msk

    - -
    -
    - - - - -
    #define CAN_F8R1_FB11_Msk   (0x1UL << CAN_F8R1_FB11_Pos)
    -
    -

    0x00000800

    - -
    -
    - -

    ◆ CAN_F8R1_FB11

    - -
    -
    - - - - -
    #define CAN_F8R1_FB11   CAN_F8R1_FB11_Msk
    -
    -

    Filter bit 11

    - -
    -
    - -

    ◆ CAN_F8R1_FB12_Pos

    - -
    -
    - - - - -
    #define CAN_F8R1_FB12_Pos   (12U)
    -
    - -
    -
    - -

    ◆ CAN_F8R1_FB12_Msk

    - -
    -
    - - - - -
    #define CAN_F8R1_FB12_Msk   (0x1UL << CAN_F8R1_FB12_Pos)
    -
    -

    0x00001000

    - -
    -
    - -

    ◆ CAN_F8R1_FB12

    - -
    -
    - - - - -
    #define CAN_F8R1_FB12   CAN_F8R1_FB12_Msk
    -
    -

    Filter bit 12

    - -
    -
    - -

    ◆ CAN_F8R1_FB13_Pos

    - -
    -
    - - - - -
    #define CAN_F8R1_FB13_Pos   (13U)
    -
    - -
    -
    - -

    ◆ CAN_F8R1_FB13_Msk

    - -
    -
    - - - - -
    #define CAN_F8R1_FB13_Msk   (0x1UL << CAN_F8R1_FB13_Pos)
    -
    -

    0x00002000

    - -
    -
    - -

    ◆ CAN_F8R1_FB13

    - -
    -
    - - - - -
    #define CAN_F8R1_FB13   CAN_F8R1_FB13_Msk
    -
    -

    Filter bit 13

    - -
    -
    - -

    ◆ CAN_F8R1_FB14_Pos

    - -
    -
    - - - - -
    #define CAN_F8R1_FB14_Pos   (14U)
    -
    - -
    -
    - -

    ◆ CAN_F8R1_FB14_Msk

    - -
    -
    - - - - -
    #define CAN_F8R1_FB14_Msk   (0x1UL << CAN_F8R1_FB14_Pos)
    -
    -

    0x00004000

    - -
    -
    - -

    ◆ CAN_F8R1_FB14

    - -
    -
    - - - - -
    #define CAN_F8R1_FB14   CAN_F8R1_FB14_Msk
    -
    -

    Filter bit 14

    - -
    -
    - -

    ◆ CAN_F8R1_FB15_Pos

    - -
    -
    - - - - -
    #define CAN_F8R1_FB15_Pos   (15U)
    -
    - -
    -
    - -

    ◆ CAN_F8R1_FB15_Msk

    - -
    -
    - - - - -
    #define CAN_F8R1_FB15_Msk   (0x1UL << CAN_F8R1_FB15_Pos)
    -
    -

    0x00008000

    - -
    -
    - -

    ◆ CAN_F8R1_FB15

    - -
    -
    - - - - -
    #define CAN_F8R1_FB15   CAN_F8R1_FB15_Msk
    -
    -

    Filter bit 15

    - -
    -
    - -

    ◆ CAN_F8R1_FB16_Pos

    - -
    -
    - - - - -
    #define CAN_F8R1_FB16_Pos   (16U)
    -
    - -
    -
    - -

    ◆ CAN_F8R1_FB16_Msk

    - -
    -
    - - - - -
    #define CAN_F8R1_FB16_Msk   (0x1UL << CAN_F8R1_FB16_Pos)
    -
    -

    0x00010000

    - -
    -
    - -

    ◆ CAN_F8R1_FB16

    - -
    -
    - - - - -
    #define CAN_F8R1_FB16   CAN_F8R1_FB16_Msk
    -
    -

    Filter bit 16

    - -
    -
    - -

    ◆ CAN_F8R1_FB17_Pos

    - -
    -
    - - - - -
    #define CAN_F8R1_FB17_Pos   (17U)
    -
    - -
    -
    - -

    ◆ CAN_F8R1_FB17_Msk

    - -
    -
    - - - - -
    #define CAN_F8R1_FB17_Msk   (0x1UL << CAN_F8R1_FB17_Pos)
    -
    -

    0x00020000

    - -
    -
    - -

    ◆ CAN_F8R1_FB17

    - -
    -
    - - - - -
    #define CAN_F8R1_FB17   CAN_F8R1_FB17_Msk
    -
    -

    Filter bit 17

    - -
    -
    - -

    ◆ CAN_F8R1_FB18_Pos

    - -
    -
    - - - - -
    #define CAN_F8R1_FB18_Pos   (18U)
    -
    - -
    -
    - -

    ◆ CAN_F8R1_FB18_Msk

    - -
    -
    - - - - -
    #define CAN_F8R1_FB18_Msk   (0x1UL << CAN_F8R1_FB18_Pos)
    -
    -

    0x00040000

    - -
    -
    - -

    ◆ CAN_F8R1_FB18

    - -
    -
    - - - - -
    #define CAN_F8R1_FB18   CAN_F8R1_FB18_Msk
    -
    -

    Filter bit 18

    - -
    -
    - -

    ◆ CAN_F8R1_FB19_Pos

    - -
    -
    - - - - -
    #define CAN_F8R1_FB19_Pos   (19U)
    -
    - -
    -
    - -

    ◆ CAN_F8R1_FB19_Msk

    - -
    -
    - - - - -
    #define CAN_F8R1_FB19_Msk   (0x1UL << CAN_F8R1_FB19_Pos)
    -
    -

    0x00080000

    - -
    -
    - -

    ◆ CAN_F8R1_FB19

    - -
    -
    - - - - -
    #define CAN_F8R1_FB19   CAN_F8R1_FB19_Msk
    -
    -

    Filter bit 19

    - -
    -
    - -

    ◆ CAN_F8R1_FB20_Pos

    - -
    -
    - - - - -
    #define CAN_F8R1_FB20_Pos   (20U)
    -
    - -
    -
    - -

    ◆ CAN_F8R1_FB20_Msk

    - -
    -
    - - - - -
    #define CAN_F8R1_FB20_Msk   (0x1UL << CAN_F8R1_FB20_Pos)
    -
    -

    0x00100000

    - -
    -
    - -

    ◆ CAN_F8R1_FB20

    - -
    -
    - - - - -
    #define CAN_F8R1_FB20   CAN_F8R1_FB20_Msk
    -
    -

    Filter bit 20

    - -
    -
    - -

    ◆ CAN_F8R1_FB21_Pos

    - -
    -
    - - - - -
    #define CAN_F8R1_FB21_Pos   (21U)
    -
    - -
    -
    - -

    ◆ CAN_F8R1_FB21_Msk

    - -
    -
    - - - - -
    #define CAN_F8R1_FB21_Msk   (0x1UL << CAN_F8R1_FB21_Pos)
    -
    -

    0x00200000

    - -
    -
    - -

    ◆ CAN_F8R1_FB21

    - -
    -
    - - - - -
    #define CAN_F8R1_FB21   CAN_F8R1_FB21_Msk
    -
    -

    Filter bit 21

    - -
    -
    - -

    ◆ CAN_F8R1_FB22_Pos

    - -
    -
    - - - - -
    #define CAN_F8R1_FB22_Pos   (22U)
    -
    - -
    -
    - -

    ◆ CAN_F8R1_FB22_Msk

    - -
    -
    - - - - -
    #define CAN_F8R1_FB22_Msk   (0x1UL << CAN_F8R1_FB22_Pos)
    -
    -

    0x00400000

    - -
    -
    - -

    ◆ CAN_F8R1_FB22

    - -
    -
    - - - - -
    #define CAN_F8R1_FB22   CAN_F8R1_FB22_Msk
    -
    -

    Filter bit 22

    - -
    -
    - -

    ◆ CAN_F8R1_FB23_Pos

    - -
    -
    - - - - -
    #define CAN_F8R1_FB23_Pos   (23U)
    -
    - -
    -
    - -

    ◆ CAN_F8R1_FB23_Msk

    - -
    -
    - - - - -
    #define CAN_F8R1_FB23_Msk   (0x1UL << CAN_F8R1_FB23_Pos)
    -
    -

    0x00800000

    - -
    -
    - -

    ◆ CAN_F8R1_FB23

    - -
    -
    - - - - -
    #define CAN_F8R1_FB23   CAN_F8R1_FB23_Msk
    -
    -

    Filter bit 23

    - -
    -
    - -

    ◆ CAN_F8R1_FB24_Pos

    - -
    -
    - - - - -
    #define CAN_F8R1_FB24_Pos   (24U)
    -
    - -
    -
    - -

    ◆ CAN_F8R1_FB24_Msk

    - -
    -
    - - - - -
    #define CAN_F8R1_FB24_Msk   (0x1UL << CAN_F8R1_FB24_Pos)
    -
    -

    0x01000000

    - -
    -
    - -

    ◆ CAN_F8R1_FB24

    - -
    -
    - - - - -
    #define CAN_F8R1_FB24   CAN_F8R1_FB24_Msk
    -
    -

    Filter bit 24

    - -
    -
    - -

    ◆ CAN_F8R1_FB25_Pos

    - -
    -
    - - - - -
    #define CAN_F8R1_FB25_Pos   (25U)
    -
    - -
    -
    - -

    ◆ CAN_F8R1_FB25_Msk

    - -
    -
    - - - - -
    #define CAN_F8R1_FB25_Msk   (0x1UL << CAN_F8R1_FB25_Pos)
    -
    -

    0x02000000

    - -
    -
    - -

    ◆ CAN_F8R1_FB25

    - -
    -
    - - - - -
    #define CAN_F8R1_FB25   CAN_F8R1_FB25_Msk
    -
    -

    Filter bit 25

    - -
    -
    - -

    ◆ CAN_F8R1_FB26_Pos

    - -
    -
    - - - - -
    #define CAN_F8R1_FB26_Pos   (26U)
    -
    - -
    -
    - -

    ◆ CAN_F8R1_FB26_Msk

    - -
    -
    - - - - -
    #define CAN_F8R1_FB26_Msk   (0x1UL << CAN_F8R1_FB26_Pos)
    -
    -

    0x04000000

    - -
    -
    - -

    ◆ CAN_F8R1_FB26

    - -
    -
    - - - - -
    #define CAN_F8R1_FB26   CAN_F8R1_FB26_Msk
    -
    -

    Filter bit 26

    - -
    -
    - -

    ◆ CAN_F8R1_FB27_Pos

    - -
    -
    - - - - -
    #define CAN_F8R1_FB27_Pos   (27U)
    -
    - -
    -
    - -

    ◆ CAN_F8R1_FB27_Msk

    - -
    -
    - - - - -
    #define CAN_F8R1_FB27_Msk   (0x1UL << CAN_F8R1_FB27_Pos)
    -
    -

    0x08000000

    - -
    -
    - -

    ◆ CAN_F8R1_FB27

    - -
    -
    - - - - -
    #define CAN_F8R1_FB27   CAN_F8R1_FB27_Msk
    -
    -

    Filter bit 27

    - -
    -
    - -

    ◆ CAN_F8R1_FB28_Pos

    - -
    -
    - - - - -
    #define CAN_F8R1_FB28_Pos   (28U)
    -
    - -
    -
    - -

    ◆ CAN_F8R1_FB28_Msk

    - -
    -
    - - - - -
    #define CAN_F8R1_FB28_Msk   (0x1UL << CAN_F8R1_FB28_Pos)
    -
    -

    0x10000000

    - -
    -
    - -

    ◆ CAN_F8R1_FB28

    - -
    -
    - - - - -
    #define CAN_F8R1_FB28   CAN_F8R1_FB28_Msk
    -
    -

    Filter bit 28

    - -
    -
    - -

    ◆ CAN_F8R1_FB29_Pos

    - -
    -
    - - - - -
    #define CAN_F8R1_FB29_Pos   (29U)
    -
    - -
    -
    - -

    ◆ CAN_F8R1_FB29_Msk

    - -
    -
    - - - - -
    #define CAN_F8R1_FB29_Msk   (0x1UL << CAN_F8R1_FB29_Pos)
    -
    -

    0x20000000

    - -
    -
    - -

    ◆ CAN_F8R1_FB29

    - -
    -
    - - - - -
    #define CAN_F8R1_FB29   CAN_F8R1_FB29_Msk
    -
    -

    Filter bit 29

    - -
    -
    - -

    ◆ CAN_F8R1_FB30_Pos

    - -
    -
    - - - - -
    #define CAN_F8R1_FB30_Pos   (30U)
    -
    - -
    -
    - -

    ◆ CAN_F8R1_FB30_Msk

    - -
    -
    - - - - -
    #define CAN_F8R1_FB30_Msk   (0x1UL << CAN_F8R1_FB30_Pos)
    -
    -

    0x40000000

    - -
    -
    - -

    ◆ CAN_F8R1_FB30

    - -
    -
    - - - - -
    #define CAN_F8R1_FB30   CAN_F8R1_FB30_Msk
    -
    -

    Filter bit 30

    - -
    -
    - -

    ◆ CAN_F8R1_FB31_Pos

    - -
    -
    - - - - -
    #define CAN_F8R1_FB31_Pos   (31U)
    -
    - -
    -
    - -

    ◆ CAN_F8R1_FB31_Msk

    - -
    -
    - - - - -
    #define CAN_F8R1_FB31_Msk   (0x1UL << CAN_F8R1_FB31_Pos)
    -
    -

    0x80000000

    - -
    -
    - -

    ◆ CAN_F8R1_FB31

    - -
    -
    - - - - -
    #define CAN_F8R1_FB31   CAN_F8R1_FB31_Msk
    -
    -

    Filter bit 31

    - -
    -
    - -

    ◆ CAN_F9R1_FB0_Pos

    - -
    -
    - - - - -
    #define CAN_F9R1_FB0_Pos   (0U)
    -
    - -
    -
    - -

    ◆ CAN_F9R1_FB0_Msk

    - -
    -
    - - - - -
    #define CAN_F9R1_FB0_Msk   (0x1UL << CAN_F9R1_FB0_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ CAN_F9R1_FB0

    - -
    -
    - - - - -
    #define CAN_F9R1_FB0   CAN_F9R1_FB0_Msk
    -
    -

    Filter bit 0

    - -
    -
    - -

    ◆ CAN_F9R1_FB1_Pos

    - -
    -
    - - - - -
    #define CAN_F9R1_FB1_Pos   (1U)
    -
    - -
    -
    - -

    ◆ CAN_F9R1_FB1_Msk

    - -
    -
    - - - - -
    #define CAN_F9R1_FB1_Msk   (0x1UL << CAN_F9R1_FB1_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ CAN_F9R1_FB1

    - -
    -
    - - - - -
    #define CAN_F9R1_FB1   CAN_F9R1_FB1_Msk
    -
    -

    Filter bit 1

    - -
    -
    - -

    ◆ CAN_F9R1_FB2_Pos

    - -
    -
    - - - - -
    #define CAN_F9R1_FB2_Pos   (2U)
    -
    - -
    -
    - -

    ◆ CAN_F9R1_FB2_Msk

    - -
    -
    - - - - -
    #define CAN_F9R1_FB2_Msk   (0x1UL << CAN_F9R1_FB2_Pos)
    -
    -

    0x00000004

    - -
    -
    - -

    ◆ CAN_F9R1_FB2

    - -
    -
    - - - - -
    #define CAN_F9R1_FB2   CAN_F9R1_FB2_Msk
    -
    -

    Filter bit 2

    - -
    -
    - -

    ◆ CAN_F9R1_FB3_Pos

    - -
    -
    - - - - -
    #define CAN_F9R1_FB3_Pos   (3U)
    -
    - -
    -
    - -

    ◆ CAN_F9R1_FB3_Msk

    - -
    -
    - - - - -
    #define CAN_F9R1_FB3_Msk   (0x1UL << CAN_F9R1_FB3_Pos)
    -
    -

    0x00000008

    - -
    -
    - -

    ◆ CAN_F9R1_FB3

    - -
    -
    - - - - -
    #define CAN_F9R1_FB3   CAN_F9R1_FB3_Msk
    -
    -

    Filter bit 3

    - -
    -
    - -

    ◆ CAN_F9R1_FB4_Pos

    - -
    -
    - - - - -
    #define CAN_F9R1_FB4_Pos   (4U)
    -
    - -
    -
    - -

    ◆ CAN_F9R1_FB4_Msk

    - -
    -
    - - - - -
    #define CAN_F9R1_FB4_Msk   (0x1UL << CAN_F9R1_FB4_Pos)
    -
    -

    0x00000010

    - -
    -
    - -

    ◆ CAN_F9R1_FB4

    - -
    -
    - - - - -
    #define CAN_F9R1_FB4   CAN_F9R1_FB4_Msk
    -
    -

    Filter bit 4

    - -
    -
    - -

    ◆ CAN_F9R1_FB5_Pos

    - -
    -
    - - - - -
    #define CAN_F9R1_FB5_Pos   (5U)
    -
    - -
    -
    - -

    ◆ CAN_F9R1_FB5_Msk

    - -
    -
    - - - - -
    #define CAN_F9R1_FB5_Msk   (0x1UL << CAN_F9R1_FB5_Pos)
    -
    -

    0x00000020

    - -
    -
    - -

    ◆ CAN_F9R1_FB5

    - -
    -
    - - - - -
    #define CAN_F9R1_FB5   CAN_F9R1_FB5_Msk
    -
    -

    Filter bit 5

    - -
    -
    - -

    ◆ CAN_F9R1_FB6_Pos

    - -
    -
    - - - - -
    #define CAN_F9R1_FB6_Pos   (6U)
    -
    - -
    -
    - -

    ◆ CAN_F9R1_FB6_Msk

    - -
    -
    - - - - -
    #define CAN_F9R1_FB6_Msk   (0x1UL << CAN_F9R1_FB6_Pos)
    -
    -

    0x00000040

    - -
    -
    - -

    ◆ CAN_F9R1_FB6

    - -
    -
    - - - - -
    #define CAN_F9R1_FB6   CAN_F9R1_FB6_Msk
    -
    -

    Filter bit 6

    - -
    -
    - -

    ◆ CAN_F9R1_FB7_Pos

    - -
    -
    - - - - -
    #define CAN_F9R1_FB7_Pos   (7U)
    -
    - -
    -
    - -

    ◆ CAN_F9R1_FB7_Msk

    - -
    -
    - - - - -
    #define CAN_F9R1_FB7_Msk   (0x1UL << CAN_F9R1_FB7_Pos)
    -
    -

    0x00000080

    - -
    -
    - -

    ◆ CAN_F9R1_FB7

    - -
    -
    - - - - -
    #define CAN_F9R1_FB7   CAN_F9R1_FB7_Msk
    -
    -

    Filter bit 7

    - -
    -
    - -

    ◆ CAN_F9R1_FB8_Pos

    - -
    -
    - - - - -
    #define CAN_F9R1_FB8_Pos   (8U)
    -
    - -
    -
    - -

    ◆ CAN_F9R1_FB8_Msk

    - -
    -
    - - - - -
    #define CAN_F9R1_FB8_Msk   (0x1UL << CAN_F9R1_FB8_Pos)
    -
    -

    0x00000100

    - -
    -
    - -

    ◆ CAN_F9R1_FB8

    - -
    -
    - - - - -
    #define CAN_F9R1_FB8   CAN_F9R1_FB8_Msk
    -
    -

    Filter bit 8

    - -
    -
    - -

    ◆ CAN_F9R1_FB9_Pos

    - -
    -
    - - - - -
    #define CAN_F9R1_FB9_Pos   (9U)
    -
    - -
    -
    - -

    ◆ CAN_F9R1_FB9_Msk

    - -
    -
    - - - - -
    #define CAN_F9R1_FB9_Msk   (0x1UL << CAN_F9R1_FB9_Pos)
    -
    -

    0x00000200

    - -
    -
    - -

    ◆ CAN_F9R1_FB9

    - -
    -
    - - - - -
    #define CAN_F9R1_FB9   CAN_F9R1_FB9_Msk
    -
    -

    Filter bit 9

    - -
    -
    - -

    ◆ CAN_F9R1_FB10_Pos

    - -
    -
    - - - - -
    #define CAN_F9R1_FB10_Pos   (10U)
    -
    - -
    -
    - -

    ◆ CAN_F9R1_FB10_Msk

    - -
    -
    - - - - -
    #define CAN_F9R1_FB10_Msk   (0x1UL << CAN_F9R1_FB10_Pos)
    -
    -

    0x00000400

    - -
    -
    - -

    ◆ CAN_F9R1_FB10

    - -
    -
    - - - - -
    #define CAN_F9R1_FB10   CAN_F9R1_FB10_Msk
    -
    -

    Filter bit 10

    - -
    -
    - -

    ◆ CAN_F9R1_FB11_Pos

    - -
    -
    - - - - -
    #define CAN_F9R1_FB11_Pos   (11U)
    -
    - -
    -
    - -

    ◆ CAN_F9R1_FB11_Msk

    - -
    -
    - - - - -
    #define CAN_F9R1_FB11_Msk   (0x1UL << CAN_F9R1_FB11_Pos)
    -
    -

    0x00000800

    - -
    -
    - -

    ◆ CAN_F9R1_FB11

    - -
    -
    - - - - -
    #define CAN_F9R1_FB11   CAN_F9R1_FB11_Msk
    -
    -

    Filter bit 11

    - -
    -
    - -

    ◆ CAN_F9R1_FB12_Pos

    - -
    -
    - - - - -
    #define CAN_F9R1_FB12_Pos   (12U)
    -
    - -
    -
    - -

    ◆ CAN_F9R1_FB12_Msk

    - -
    -
    - - - - -
    #define CAN_F9R1_FB12_Msk   (0x1UL << CAN_F9R1_FB12_Pos)
    -
    -

    0x00001000

    - -
    -
    - -

    ◆ CAN_F9R1_FB12

    - -
    -
    - - - - -
    #define CAN_F9R1_FB12   CAN_F9R1_FB12_Msk
    -
    -

    Filter bit 12

    - -
    -
    - -

    ◆ CAN_F9R1_FB13_Pos

    - -
    -
    - - - - -
    #define CAN_F9R1_FB13_Pos   (13U)
    -
    - -
    -
    - -

    ◆ CAN_F9R1_FB13_Msk

    - -
    -
    - - - - -
    #define CAN_F9R1_FB13_Msk   (0x1UL << CAN_F9R1_FB13_Pos)
    -
    -

    0x00002000

    - -
    -
    - -

    ◆ CAN_F9R1_FB13

    - -
    -
    - - - - -
    #define CAN_F9R1_FB13   CAN_F9R1_FB13_Msk
    -
    -

    Filter bit 13

    - -
    -
    - -

    ◆ CAN_F9R1_FB14_Pos

    - -
    -
    - - - - -
    #define CAN_F9R1_FB14_Pos   (14U)
    -
    - -
    -
    - -

    ◆ CAN_F9R1_FB14_Msk

    - -
    -
    - - - - -
    #define CAN_F9R1_FB14_Msk   (0x1UL << CAN_F9R1_FB14_Pos)
    -
    -

    0x00004000

    - -
    -
    - -

    ◆ CAN_F9R1_FB14

    - -
    -
    - - - - -
    #define CAN_F9R1_FB14   CAN_F9R1_FB14_Msk
    -
    -

    Filter bit 14

    - -
    -
    - -

    ◆ CAN_F9R1_FB15_Pos

    - -
    -
    - - - - -
    #define CAN_F9R1_FB15_Pos   (15U)
    -
    - -
    -
    - -

    ◆ CAN_F9R1_FB15_Msk

    - -
    -
    - - - - -
    #define CAN_F9R1_FB15_Msk   (0x1UL << CAN_F9R1_FB15_Pos)
    -
    -

    0x00008000

    - -
    -
    - -

    ◆ CAN_F9R1_FB15

    - -
    -
    - - - - -
    #define CAN_F9R1_FB15   CAN_F9R1_FB15_Msk
    -
    -

    Filter bit 15

    - -
    -
    - -

    ◆ CAN_F9R1_FB16_Pos

    - -
    -
    - - - - -
    #define CAN_F9R1_FB16_Pos   (16U)
    -
    - -
    -
    - -

    ◆ CAN_F9R1_FB16_Msk

    - -
    -
    - - - - -
    #define CAN_F9R1_FB16_Msk   (0x1UL << CAN_F9R1_FB16_Pos)
    -
    -

    0x00010000

    - -
    -
    - -

    ◆ CAN_F9R1_FB16

    - -
    -
    - - - - -
    #define CAN_F9R1_FB16   CAN_F9R1_FB16_Msk
    -
    -

    Filter bit 16

    - -
    -
    - -

    ◆ CAN_F9R1_FB17_Pos

    - -
    -
    - - - - -
    #define CAN_F9R1_FB17_Pos   (17U)
    -
    - -
    -
    - -

    ◆ CAN_F9R1_FB17_Msk

    - -
    -
    - - - - -
    #define CAN_F9R1_FB17_Msk   (0x1UL << CAN_F9R1_FB17_Pos)
    -
    -

    0x00020000

    - -
    -
    - -

    ◆ CAN_F9R1_FB17

    - -
    -
    - - - - -
    #define CAN_F9R1_FB17   CAN_F9R1_FB17_Msk
    -
    -

    Filter bit 17

    - -
    -
    - -

    ◆ CAN_F9R1_FB18_Pos

    - -
    -
    - - - - -
    #define CAN_F9R1_FB18_Pos   (18U)
    -
    - -
    -
    - -

    ◆ CAN_F9R1_FB18_Msk

    - -
    -
    - - - - -
    #define CAN_F9R1_FB18_Msk   (0x1UL << CAN_F9R1_FB18_Pos)
    -
    -

    0x00040000

    - -
    -
    - -

    ◆ CAN_F9R1_FB18

    - -
    -
    - - - - -
    #define CAN_F9R1_FB18   CAN_F9R1_FB18_Msk
    -
    -

    Filter bit 18

    - -
    -
    - -

    ◆ CAN_F9R1_FB19_Pos

    - -
    -
    - - - - -
    #define CAN_F9R1_FB19_Pos   (19U)
    -
    - -
    -
    - -

    ◆ CAN_F9R1_FB19_Msk

    - -
    -
    - - - - -
    #define CAN_F9R1_FB19_Msk   (0x1UL << CAN_F9R1_FB19_Pos)
    -
    -

    0x00080000

    - -
    -
    - -

    ◆ CAN_F9R1_FB19

    - -
    -
    - - - - -
    #define CAN_F9R1_FB19   CAN_F9R1_FB19_Msk
    -
    -

    Filter bit 19

    - -
    -
    - -

    ◆ CAN_F9R1_FB20_Pos

    - -
    -
    - - - - -
    #define CAN_F9R1_FB20_Pos   (20U)
    -
    - -
    -
    - -

    ◆ CAN_F9R1_FB20_Msk

    - -
    -
    - - - - -
    #define CAN_F9R1_FB20_Msk   (0x1UL << CAN_F9R1_FB20_Pos)
    -
    -

    0x00100000

    - -
    -
    - -

    ◆ CAN_F9R1_FB20

    - -
    -
    - - - - -
    #define CAN_F9R1_FB20   CAN_F9R1_FB20_Msk
    -
    -

    Filter bit 20

    - -
    -
    - -

    ◆ CAN_F9R1_FB21_Pos

    - -
    -
    - - - - -
    #define CAN_F9R1_FB21_Pos   (21U)
    -
    - -
    -
    - -

    ◆ CAN_F9R1_FB21_Msk

    - -
    -
    - - - - -
    #define CAN_F9R1_FB21_Msk   (0x1UL << CAN_F9R1_FB21_Pos)
    -
    -

    0x00200000

    - -
    -
    - -

    ◆ CAN_F9R1_FB21

    - -
    -
    - - - - -
    #define CAN_F9R1_FB21   CAN_F9R1_FB21_Msk
    -
    -

    Filter bit 21

    - -
    -
    - -

    ◆ CAN_F9R1_FB22_Pos

    - -
    -
    - - - - -
    #define CAN_F9R1_FB22_Pos   (22U)
    -
    - -
    -
    - -

    ◆ CAN_F9R1_FB22_Msk

    - -
    -
    - - - - -
    #define CAN_F9R1_FB22_Msk   (0x1UL << CAN_F9R1_FB22_Pos)
    -
    -

    0x00400000

    - -
    -
    - -

    ◆ CAN_F9R1_FB22

    - -
    -
    - - - - -
    #define CAN_F9R1_FB22   CAN_F9R1_FB22_Msk
    -
    -

    Filter bit 22

    - -
    -
    - -

    ◆ CAN_F9R1_FB23_Pos

    - -
    -
    - - - - -
    #define CAN_F9R1_FB23_Pos   (23U)
    -
    - -
    -
    - -

    ◆ CAN_F9R1_FB23_Msk

    - -
    -
    - - - - -
    #define CAN_F9R1_FB23_Msk   (0x1UL << CAN_F9R1_FB23_Pos)
    -
    -

    0x00800000

    - -
    -
    - -

    ◆ CAN_F9R1_FB23

    - -
    -
    - - - - -
    #define CAN_F9R1_FB23   CAN_F9R1_FB23_Msk
    -
    -

    Filter bit 23

    - -
    -
    - -

    ◆ CAN_F9R1_FB24_Pos

    - -
    -
    - - - - -
    #define CAN_F9R1_FB24_Pos   (24U)
    -
    - -
    -
    - -

    ◆ CAN_F9R1_FB24_Msk

    - -
    -
    - - - - -
    #define CAN_F9R1_FB24_Msk   (0x1UL << CAN_F9R1_FB24_Pos)
    -
    -

    0x01000000

    - -
    -
    - -

    ◆ CAN_F9R1_FB24

    - -
    -
    - - - - -
    #define CAN_F9R1_FB24   CAN_F9R1_FB24_Msk
    -
    -

    Filter bit 24

    - -
    -
    - -

    ◆ CAN_F9R1_FB25_Pos

    - -
    -
    - - - - -
    #define CAN_F9R1_FB25_Pos   (25U)
    -
    - -
    -
    - -

    ◆ CAN_F9R1_FB25_Msk

    - -
    -
    - - - - -
    #define CAN_F9R1_FB25_Msk   (0x1UL << CAN_F9R1_FB25_Pos)
    -
    -

    0x02000000

    - -
    -
    - -

    ◆ CAN_F9R1_FB25

    - -
    -
    - - - - -
    #define CAN_F9R1_FB25   CAN_F9R1_FB25_Msk
    -
    -

    Filter bit 25

    - -
    -
    - -

    ◆ CAN_F9R1_FB26_Pos

    - -
    -
    - - - - -
    #define CAN_F9R1_FB26_Pos   (26U)
    -
    - -
    -
    - -

    ◆ CAN_F9R1_FB26_Msk

    - -
    -
    - - - - -
    #define CAN_F9R1_FB26_Msk   (0x1UL << CAN_F9R1_FB26_Pos)
    -
    -

    0x04000000

    - -
    -
    - -

    ◆ CAN_F9R1_FB26

    - -
    -
    - - - - -
    #define CAN_F9R1_FB26   CAN_F9R1_FB26_Msk
    -
    -

    Filter bit 26

    - -
    -
    - -

    ◆ CAN_F9R1_FB27_Pos

    - -
    -
    - - - - -
    #define CAN_F9R1_FB27_Pos   (27U)
    -
    - -
    -
    - -

    ◆ CAN_F9R1_FB27_Msk

    - -
    -
    - - - - -
    #define CAN_F9R1_FB27_Msk   (0x1UL << CAN_F9R1_FB27_Pos)
    -
    -

    0x08000000

    - -
    -
    - -

    ◆ CAN_F9R1_FB27

    - -
    -
    - - - - -
    #define CAN_F9R1_FB27   CAN_F9R1_FB27_Msk
    -
    -

    Filter bit 27

    - -
    -
    - -

    ◆ CAN_F9R1_FB28_Pos

    - -
    -
    - - - - -
    #define CAN_F9R1_FB28_Pos   (28U)
    -
    - -
    -
    - -

    ◆ CAN_F9R1_FB28_Msk

    - -
    -
    - - - - -
    #define CAN_F9R1_FB28_Msk   (0x1UL << CAN_F9R1_FB28_Pos)
    -
    -

    0x10000000

    - -
    -
    - -

    ◆ CAN_F9R1_FB28

    - -
    -
    - - - - -
    #define CAN_F9R1_FB28   CAN_F9R1_FB28_Msk
    -
    -

    Filter bit 28

    - -
    -
    - -

    ◆ CAN_F9R1_FB29_Pos

    - -
    -
    - - - - -
    #define CAN_F9R1_FB29_Pos   (29U)
    -
    - -
    -
    - -

    ◆ CAN_F9R1_FB29_Msk

    - -
    -
    - - - - -
    #define CAN_F9R1_FB29_Msk   (0x1UL << CAN_F9R1_FB29_Pos)
    -
    -

    0x20000000

    - -
    -
    - -

    ◆ CAN_F9R1_FB29

    - -
    -
    - - - - -
    #define CAN_F9R1_FB29   CAN_F9R1_FB29_Msk
    -
    -

    Filter bit 29

    - -
    -
    - -

    ◆ CAN_F9R1_FB30_Pos

    - -
    -
    - - - - -
    #define CAN_F9R1_FB30_Pos   (30U)
    -
    - -
    -
    - -

    ◆ CAN_F9R1_FB30_Msk

    - -
    -
    - - - - -
    #define CAN_F9R1_FB30_Msk   (0x1UL << CAN_F9R1_FB30_Pos)
    -
    -

    0x40000000

    - -
    -
    - -

    ◆ CAN_F9R1_FB30

    - -
    -
    - - - - -
    #define CAN_F9R1_FB30   CAN_F9R1_FB30_Msk
    -
    -

    Filter bit 30

    - -
    -
    - -

    ◆ CAN_F9R1_FB31_Pos

    - -
    -
    - - - - -
    #define CAN_F9R1_FB31_Pos   (31U)
    -
    - -
    -
    - -

    ◆ CAN_F9R1_FB31_Msk

    - -
    -
    - - - - -
    #define CAN_F9R1_FB31_Msk   (0x1UL << CAN_F9R1_FB31_Pos)
    -
    -

    0x80000000

    - -
    -
    - -

    ◆ CAN_F9R1_FB31

    - -
    -
    - - - - -
    #define CAN_F9R1_FB31   CAN_F9R1_FB31_Msk
    -
    -

    Filter bit 31

    - -
    -
    - -

    ◆ CAN_F10R1_FB0_Pos

    - -
    -
    - - - - -
    #define CAN_F10R1_FB0_Pos   (0U)
    -
    - -
    -
    - -

    ◆ CAN_F10R1_FB0_Msk

    - -
    -
    - - - - -
    #define CAN_F10R1_FB0_Msk   (0x1UL << CAN_F10R1_FB0_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ CAN_F10R1_FB0

    - -
    -
    - - - - -
    #define CAN_F10R1_FB0   CAN_F10R1_FB0_Msk
    -
    -

    Filter bit 0

    - -
    -
    - -

    ◆ CAN_F10R1_FB1_Pos

    - -
    -
    - - - - -
    #define CAN_F10R1_FB1_Pos   (1U)
    -
    - -
    -
    - -

    ◆ CAN_F10R1_FB1_Msk

    - -
    -
    - - - - -
    #define CAN_F10R1_FB1_Msk   (0x1UL << CAN_F10R1_FB1_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ CAN_F10R1_FB1

    - -
    -
    - - - - -
    #define CAN_F10R1_FB1   CAN_F10R1_FB1_Msk
    -
    -

    Filter bit 1

    - -
    -
    - -

    ◆ CAN_F10R1_FB2_Pos

    - -
    -
    - - - - -
    #define CAN_F10R1_FB2_Pos   (2U)
    -
    - -
    -
    - -

    ◆ CAN_F10R1_FB2_Msk

    - -
    -
    - - - - -
    #define CAN_F10R1_FB2_Msk   (0x1UL << CAN_F10R1_FB2_Pos)
    -
    -

    0x00000004

    - -
    -
    - -

    ◆ CAN_F10R1_FB2

    - -
    -
    - - - - -
    #define CAN_F10R1_FB2   CAN_F10R1_FB2_Msk
    -
    -

    Filter bit 2

    - -
    -
    - -

    ◆ CAN_F10R1_FB3_Pos

    - -
    -
    - - - - -
    #define CAN_F10R1_FB3_Pos   (3U)
    -
    - -
    -
    - -

    ◆ CAN_F10R1_FB3_Msk

    - -
    -
    - - - - -
    #define CAN_F10R1_FB3_Msk   (0x1UL << CAN_F10R1_FB3_Pos)
    -
    -

    0x00000008

    - -
    -
    - -

    ◆ CAN_F10R1_FB3

    - -
    -
    - - - - -
    #define CAN_F10R1_FB3   CAN_F10R1_FB3_Msk
    -
    -

    Filter bit 3

    - -
    -
    - -

    ◆ CAN_F10R1_FB4_Pos

    - -
    -
    - - - - -
    #define CAN_F10R1_FB4_Pos   (4U)
    -
    - -
    -
    - -

    ◆ CAN_F10R1_FB4_Msk

    - -
    -
    - - - - -
    #define CAN_F10R1_FB4_Msk   (0x1UL << CAN_F10R1_FB4_Pos)
    -
    -

    0x00000010

    - -
    -
    - -

    ◆ CAN_F10R1_FB4

    - -
    -
    - - - - -
    #define CAN_F10R1_FB4   CAN_F10R1_FB4_Msk
    -
    -

    Filter bit 4

    - -
    -
    - -

    ◆ CAN_F10R1_FB5_Pos

    - -
    -
    - - - - -
    #define CAN_F10R1_FB5_Pos   (5U)
    -
    - -
    -
    - -

    ◆ CAN_F10R1_FB5_Msk

    - -
    -
    - - - - -
    #define CAN_F10R1_FB5_Msk   (0x1UL << CAN_F10R1_FB5_Pos)
    -
    -

    0x00000020

    - -
    -
    - -

    ◆ CAN_F10R1_FB5

    - -
    -
    - - - - -
    #define CAN_F10R1_FB5   CAN_F10R1_FB5_Msk
    -
    -

    Filter bit 5

    - -
    -
    - -

    ◆ CAN_F10R1_FB6_Pos

    - -
    -
    - - - - -
    #define CAN_F10R1_FB6_Pos   (6U)
    -
    - -
    -
    - -

    ◆ CAN_F10R1_FB6_Msk

    - -
    -
    - - - - -
    #define CAN_F10R1_FB6_Msk   (0x1UL << CAN_F10R1_FB6_Pos)
    -
    -

    0x00000040

    - -
    -
    - -

    ◆ CAN_F10R1_FB6

    - -
    -
    - - - - -
    #define CAN_F10R1_FB6   CAN_F10R1_FB6_Msk
    -
    -

    Filter bit 6

    - -
    -
    - -

    ◆ CAN_F10R1_FB7_Pos

    - -
    -
    - - - - -
    #define CAN_F10R1_FB7_Pos   (7U)
    -
    - -
    -
    - -

    ◆ CAN_F10R1_FB7_Msk

    - -
    -
    - - - - -
    #define CAN_F10R1_FB7_Msk   (0x1UL << CAN_F10R1_FB7_Pos)
    -
    -

    0x00000080

    - -
    -
    - -

    ◆ CAN_F10R1_FB7

    - -
    -
    - - - - -
    #define CAN_F10R1_FB7   CAN_F10R1_FB7_Msk
    -
    -

    Filter bit 7

    - -
    -
    - -

    ◆ CAN_F10R1_FB8_Pos

    - -
    -
    - - - - -
    #define CAN_F10R1_FB8_Pos   (8U)
    -
    - -
    -
    - -

    ◆ CAN_F10R1_FB8_Msk

    - -
    -
    - - - - -
    #define CAN_F10R1_FB8_Msk   (0x1UL << CAN_F10R1_FB8_Pos)
    -
    -

    0x00000100

    - -
    -
    - -

    ◆ CAN_F10R1_FB8

    - -
    -
    - - - - -
    #define CAN_F10R1_FB8   CAN_F10R1_FB8_Msk
    -
    -

    Filter bit 8

    - -
    -
    - -

    ◆ CAN_F10R1_FB9_Pos

    - -
    -
    - - - - -
    #define CAN_F10R1_FB9_Pos   (9U)
    -
    - -
    -
    - -

    ◆ CAN_F10R1_FB9_Msk

    - -
    -
    - - - - -
    #define CAN_F10R1_FB9_Msk   (0x1UL << CAN_F10R1_FB9_Pos)
    -
    -

    0x00000200

    - -
    -
    - -

    ◆ CAN_F10R1_FB9

    - -
    -
    - - - - -
    #define CAN_F10R1_FB9   CAN_F10R1_FB9_Msk
    -
    -

    Filter bit 9

    - -
    -
    - -

    ◆ CAN_F10R1_FB10_Pos

    - -
    -
    - - - - -
    #define CAN_F10R1_FB10_Pos   (10U)
    -
    - -
    -
    - -

    ◆ CAN_F10R1_FB10_Msk

    - -
    -
    - - - - -
    #define CAN_F10R1_FB10_Msk   (0x1UL << CAN_F10R1_FB10_Pos)
    -
    -

    0x00000400

    - -
    -
    - -

    ◆ CAN_F10R1_FB10

    - -
    -
    - - - - -
    #define CAN_F10R1_FB10   CAN_F10R1_FB10_Msk
    -
    -

    Filter bit 10

    - -
    -
    - -

    ◆ CAN_F10R1_FB11_Pos

    - -
    -
    - - - - -
    #define CAN_F10R1_FB11_Pos   (11U)
    -
    - -
    -
    - -

    ◆ CAN_F10R1_FB11_Msk

    - -
    -
    - - - - -
    #define CAN_F10R1_FB11_Msk   (0x1UL << CAN_F10R1_FB11_Pos)
    -
    -

    0x00000800

    - -
    -
    - -

    ◆ CAN_F10R1_FB11

    - -
    -
    - - - - -
    #define CAN_F10R1_FB11   CAN_F10R1_FB11_Msk
    -
    -

    Filter bit 11

    - -
    -
    - -

    ◆ CAN_F10R1_FB12_Pos

    - -
    -
    - - - - -
    #define CAN_F10R1_FB12_Pos   (12U)
    -
    - -
    -
    - -

    ◆ CAN_F10R1_FB12_Msk

    - -
    -
    - - - - -
    #define CAN_F10R1_FB12_Msk   (0x1UL << CAN_F10R1_FB12_Pos)
    -
    -

    0x00001000

    - -
    -
    - -

    ◆ CAN_F10R1_FB12

    - -
    -
    - - - - -
    #define CAN_F10R1_FB12   CAN_F10R1_FB12_Msk
    -
    -

    Filter bit 12

    - -
    -
    - -

    ◆ CAN_F10R1_FB13_Pos

    - -
    -
    - - - - -
    #define CAN_F10R1_FB13_Pos   (13U)
    -
    - -
    -
    - -

    ◆ CAN_F10R1_FB13_Msk

    - -
    -
    - - - - -
    #define CAN_F10R1_FB13_Msk   (0x1UL << CAN_F10R1_FB13_Pos)
    -
    -

    0x00002000

    - -
    -
    - -

    ◆ CAN_F10R1_FB13

    - -
    -
    - - - - -
    #define CAN_F10R1_FB13   CAN_F10R1_FB13_Msk
    -
    -

    Filter bit 13

    - -
    -
    - -

    ◆ CAN_F10R1_FB14_Pos

    - -
    -
    - - - - -
    #define CAN_F10R1_FB14_Pos   (14U)
    -
    - -
    -
    - -

    ◆ CAN_F10R1_FB14_Msk

    - -
    -
    - - - - -
    #define CAN_F10R1_FB14_Msk   (0x1UL << CAN_F10R1_FB14_Pos)
    -
    -

    0x00004000

    - -
    -
    - -

    ◆ CAN_F10R1_FB14

    - -
    -
    - - - - -
    #define CAN_F10R1_FB14   CAN_F10R1_FB14_Msk
    -
    -

    Filter bit 14

    - -
    -
    - -

    ◆ CAN_F10R1_FB15_Pos

    - -
    -
    - - - - -
    #define CAN_F10R1_FB15_Pos   (15U)
    -
    - -
    -
    - -

    ◆ CAN_F10R1_FB15_Msk

    - -
    -
    - - - - -
    #define CAN_F10R1_FB15_Msk   (0x1UL << CAN_F10R1_FB15_Pos)
    -
    -

    0x00008000

    - -
    -
    - -

    ◆ CAN_F10R1_FB15

    - -
    -
    - - - - -
    #define CAN_F10R1_FB15   CAN_F10R1_FB15_Msk
    -
    -

    Filter bit 15

    - -
    -
    - -

    ◆ CAN_F10R1_FB16_Pos

    - -
    -
    - - - - -
    #define CAN_F10R1_FB16_Pos   (16U)
    -
    - -
    -
    - -

    ◆ CAN_F10R1_FB16_Msk

    - -
    -
    - - - - -
    #define CAN_F10R1_FB16_Msk   (0x1UL << CAN_F10R1_FB16_Pos)
    -
    -

    0x00010000

    - -
    -
    - -

    ◆ CAN_F10R1_FB16

    - -
    -
    - - - - -
    #define CAN_F10R1_FB16   CAN_F10R1_FB16_Msk
    -
    -

    Filter bit 16

    - -
    -
    - -

    ◆ CAN_F10R1_FB17_Pos

    - -
    -
    - - - - -
    #define CAN_F10R1_FB17_Pos   (17U)
    -
    - -
    -
    - -

    ◆ CAN_F10R1_FB17_Msk

    - -
    -
    - - - - -
    #define CAN_F10R1_FB17_Msk   (0x1UL << CAN_F10R1_FB17_Pos)
    -
    -

    0x00020000

    - -
    -
    - -

    ◆ CAN_F10R1_FB17

    - -
    -
    - - - - -
    #define CAN_F10R1_FB17   CAN_F10R1_FB17_Msk
    -
    -

    Filter bit 17

    - -
    -
    - -

    ◆ CAN_F10R1_FB18_Pos

    - -
    -
    - - - - -
    #define CAN_F10R1_FB18_Pos   (18U)
    -
    - -
    -
    - -

    ◆ CAN_F10R1_FB18_Msk

    - -
    -
    - - - - -
    #define CAN_F10R1_FB18_Msk   (0x1UL << CAN_F10R1_FB18_Pos)
    -
    -

    0x00040000

    - -
    -
    - -

    ◆ CAN_F10R1_FB18

    - -
    -
    - - - - -
    #define CAN_F10R1_FB18   CAN_F10R1_FB18_Msk
    -
    -

    Filter bit 18

    - -
    -
    - -

    ◆ CAN_F10R1_FB19_Pos

    - -
    -
    - - - - -
    #define CAN_F10R1_FB19_Pos   (19U)
    -
    - -
    -
    - -

    ◆ CAN_F10R1_FB19_Msk

    - -
    -
    - - - - -
    #define CAN_F10R1_FB19_Msk   (0x1UL << CAN_F10R1_FB19_Pos)
    -
    -

    0x00080000

    - -
    -
    - -

    ◆ CAN_F10R1_FB19

    - -
    -
    - - - - -
    #define CAN_F10R1_FB19   CAN_F10R1_FB19_Msk
    -
    -

    Filter bit 19

    - -
    -
    - -

    ◆ CAN_F10R1_FB20_Pos

    - -
    -
    - - - - -
    #define CAN_F10R1_FB20_Pos   (20U)
    -
    - -
    -
    - -

    ◆ CAN_F10R1_FB20_Msk

    - -
    -
    - - - - -
    #define CAN_F10R1_FB20_Msk   (0x1UL << CAN_F10R1_FB20_Pos)
    -
    -

    0x00100000

    - -
    -
    - -

    ◆ CAN_F10R1_FB20

    - -
    -
    - - - - -
    #define CAN_F10R1_FB20   CAN_F10R1_FB20_Msk
    -
    -

    Filter bit 20

    - -
    -
    - -

    ◆ CAN_F10R1_FB21_Pos

    - -
    -
    - - - - -
    #define CAN_F10R1_FB21_Pos   (21U)
    -
    - -
    -
    - -

    ◆ CAN_F10R1_FB21_Msk

    - -
    -
    - - - - -
    #define CAN_F10R1_FB21_Msk   (0x1UL << CAN_F10R1_FB21_Pos)
    -
    -

    0x00200000

    - -
    -
    - -

    ◆ CAN_F10R1_FB21

    - -
    -
    - - - - -
    #define CAN_F10R1_FB21   CAN_F10R1_FB21_Msk
    -
    -

    Filter bit 21

    - -
    -
    - -

    ◆ CAN_F10R1_FB22_Pos

    - -
    -
    - - - - -
    #define CAN_F10R1_FB22_Pos   (22U)
    -
    - -
    -
    - -

    ◆ CAN_F10R1_FB22_Msk

    - -
    -
    - - - - -
    #define CAN_F10R1_FB22_Msk   (0x1UL << CAN_F10R1_FB22_Pos)
    -
    -

    0x00400000

    - -
    -
    - -

    ◆ CAN_F10R1_FB22

    - -
    -
    - - - - -
    #define CAN_F10R1_FB22   CAN_F10R1_FB22_Msk
    -
    -

    Filter bit 22

    - -
    -
    - -

    ◆ CAN_F10R1_FB23_Pos

    - -
    -
    - - - - -
    #define CAN_F10R1_FB23_Pos   (23U)
    -
    - -
    -
    - -

    ◆ CAN_F10R1_FB23_Msk

    - -
    -
    - - - - -
    #define CAN_F10R1_FB23_Msk   (0x1UL << CAN_F10R1_FB23_Pos)
    -
    -

    0x00800000

    - -
    -
    - -

    ◆ CAN_F10R1_FB23

    - -
    -
    - - - - -
    #define CAN_F10R1_FB23   CAN_F10R1_FB23_Msk
    -
    -

    Filter bit 23

    - -
    -
    - -

    ◆ CAN_F10R1_FB24_Pos

    - -
    -
    - - - - -
    #define CAN_F10R1_FB24_Pos   (24U)
    -
    - -
    -
    - -

    ◆ CAN_F10R1_FB24_Msk

    - -
    -
    - - - - -
    #define CAN_F10R1_FB24_Msk   (0x1UL << CAN_F10R1_FB24_Pos)
    -
    -

    0x01000000

    - -
    -
    - -

    ◆ CAN_F10R1_FB24

    - -
    -
    - - - - -
    #define CAN_F10R1_FB24   CAN_F10R1_FB24_Msk
    -
    -

    Filter bit 24

    - -
    -
    - -

    ◆ CAN_F10R1_FB25_Pos

    - -
    -
    - - - - -
    #define CAN_F10R1_FB25_Pos   (25U)
    -
    - -
    -
    - -

    ◆ CAN_F10R1_FB25_Msk

    - -
    -
    - - - - -
    #define CAN_F10R1_FB25_Msk   (0x1UL << CAN_F10R1_FB25_Pos)
    -
    -

    0x02000000

    - -
    -
    - -

    ◆ CAN_F10R1_FB25

    - -
    -
    - - - - -
    #define CAN_F10R1_FB25   CAN_F10R1_FB25_Msk
    -
    -

    Filter bit 25

    - -
    -
    - -

    ◆ CAN_F10R1_FB26_Pos

    - -
    -
    - - - - -
    #define CAN_F10R1_FB26_Pos   (26U)
    -
    - -
    -
    - -

    ◆ CAN_F10R1_FB26_Msk

    - -
    -
    - - - - -
    #define CAN_F10R1_FB26_Msk   (0x1UL << CAN_F10R1_FB26_Pos)
    -
    -

    0x04000000

    - -
    -
    - -

    ◆ CAN_F10R1_FB26

    - -
    -
    - - - - -
    #define CAN_F10R1_FB26   CAN_F10R1_FB26_Msk
    -
    -

    Filter bit 26

    - -
    -
    - -

    ◆ CAN_F10R1_FB27_Pos

    - -
    -
    - - - - -
    #define CAN_F10R1_FB27_Pos   (27U)
    -
    - -
    -
    - -

    ◆ CAN_F10R1_FB27_Msk

    - -
    -
    - - - - -
    #define CAN_F10R1_FB27_Msk   (0x1UL << CAN_F10R1_FB27_Pos)
    -
    -

    0x08000000

    - -
    -
    - -

    ◆ CAN_F10R1_FB27

    - -
    -
    - - - - -
    #define CAN_F10R1_FB27   CAN_F10R1_FB27_Msk
    -
    -

    Filter bit 27

    - -
    -
    - -

    ◆ CAN_F10R1_FB28_Pos

    - -
    -
    - - - - -
    #define CAN_F10R1_FB28_Pos   (28U)
    -
    - -
    -
    - -

    ◆ CAN_F10R1_FB28_Msk

    - -
    -
    - - - - -
    #define CAN_F10R1_FB28_Msk   (0x1UL << CAN_F10R1_FB28_Pos)
    -
    -

    0x10000000

    - -
    -
    - -

    ◆ CAN_F10R1_FB28

    - -
    -
    - - - - -
    #define CAN_F10R1_FB28   CAN_F10R1_FB28_Msk
    -
    -

    Filter bit 28

    - -
    -
    - -

    ◆ CAN_F10R1_FB29_Pos

    - -
    -
    - - - - -
    #define CAN_F10R1_FB29_Pos   (29U)
    -
    - -
    -
    - -

    ◆ CAN_F10R1_FB29_Msk

    - -
    -
    - - - - -
    #define CAN_F10R1_FB29_Msk   (0x1UL << CAN_F10R1_FB29_Pos)
    -
    -

    0x20000000

    - -
    -
    - -

    ◆ CAN_F10R1_FB29

    - -
    -
    - - - - -
    #define CAN_F10R1_FB29   CAN_F10R1_FB29_Msk
    -
    -

    Filter bit 29

    - -
    -
    - -

    ◆ CAN_F10R1_FB30_Pos

    - -
    -
    - - - - -
    #define CAN_F10R1_FB30_Pos   (30U)
    -
    - -
    -
    - -

    ◆ CAN_F10R1_FB30_Msk

    - -
    -
    - - - - -
    #define CAN_F10R1_FB30_Msk   (0x1UL << CAN_F10R1_FB30_Pos)
    -
    -

    0x40000000

    - -
    -
    - -

    ◆ CAN_F10R1_FB30

    - -
    -
    - - - - -
    #define CAN_F10R1_FB30   CAN_F10R1_FB30_Msk
    -
    -

    Filter bit 30

    - -
    -
    - -

    ◆ CAN_F10R1_FB31_Pos

    - -
    -
    - - - - -
    #define CAN_F10R1_FB31_Pos   (31U)
    -
    - -
    -
    - -

    ◆ CAN_F10R1_FB31_Msk

    - -
    -
    - - - - -
    #define CAN_F10R1_FB31_Msk   (0x1UL << CAN_F10R1_FB31_Pos)
    -
    -

    0x80000000

    - -
    -
    - -

    ◆ CAN_F10R1_FB31

    - -
    -
    - - - - -
    #define CAN_F10R1_FB31   CAN_F10R1_FB31_Msk
    -
    -

    Filter bit 31

    - -
    -
    - -

    ◆ CAN_F11R1_FB0_Pos

    - -
    -
    - - - - -
    #define CAN_F11R1_FB0_Pos   (0U)
    -
    - -
    -
    - -

    ◆ CAN_F11R1_FB0_Msk

    - -
    -
    - - - - -
    #define CAN_F11R1_FB0_Msk   (0x1UL << CAN_F11R1_FB0_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ CAN_F11R1_FB0

    - -
    -
    - - - - -
    #define CAN_F11R1_FB0   CAN_F11R1_FB0_Msk
    -
    -

    Filter bit 0

    - -
    -
    - -

    ◆ CAN_F11R1_FB1_Pos

    - -
    -
    - - - - -
    #define CAN_F11R1_FB1_Pos   (1U)
    -
    - -
    -
    - -

    ◆ CAN_F11R1_FB1_Msk

    - -
    -
    - - - - -
    #define CAN_F11R1_FB1_Msk   (0x1UL << CAN_F11R1_FB1_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ CAN_F11R1_FB1

    - -
    -
    - - - - -
    #define CAN_F11R1_FB1   CAN_F11R1_FB1_Msk
    -
    -

    Filter bit 1

    - -
    -
    - -

    ◆ CAN_F11R1_FB2_Pos

    - -
    -
    - - - - -
    #define CAN_F11R1_FB2_Pos   (2U)
    -
    - -
    -
    - -

    ◆ CAN_F11R1_FB2_Msk

    - -
    -
    - - - - -
    #define CAN_F11R1_FB2_Msk   (0x1UL << CAN_F11R1_FB2_Pos)
    -
    -

    0x00000004

    - -
    -
    - -

    ◆ CAN_F11R1_FB2

    - -
    -
    - - - - -
    #define CAN_F11R1_FB2   CAN_F11R1_FB2_Msk
    -
    -

    Filter bit 2

    - -
    -
    - -

    ◆ CAN_F11R1_FB3_Pos

    - -
    -
    - - - - -
    #define CAN_F11R1_FB3_Pos   (3U)
    -
    - -
    -
    - -

    ◆ CAN_F11R1_FB3_Msk

    - -
    -
    - - - - -
    #define CAN_F11R1_FB3_Msk   (0x1UL << CAN_F11R1_FB3_Pos)
    -
    -

    0x00000008

    - -
    -
    - -

    ◆ CAN_F11R1_FB3

    - -
    -
    - - - - -
    #define CAN_F11R1_FB3   CAN_F11R1_FB3_Msk
    -
    -

    Filter bit 3

    - -
    -
    - -

    ◆ CAN_F11R1_FB4_Pos

    - -
    -
    - - - - -
    #define CAN_F11R1_FB4_Pos   (4U)
    -
    - -
    -
    - -

    ◆ CAN_F11R1_FB4_Msk

    - -
    -
    - - - - -
    #define CAN_F11R1_FB4_Msk   (0x1UL << CAN_F11R1_FB4_Pos)
    -
    -

    0x00000010

    - -
    -
    - -

    ◆ CAN_F11R1_FB4

    - -
    -
    - - - - -
    #define CAN_F11R1_FB4   CAN_F11R1_FB4_Msk
    -
    -

    Filter bit 4

    - -
    -
    - -

    ◆ CAN_F11R1_FB5_Pos

    - -
    -
    - - - - -
    #define CAN_F11R1_FB5_Pos   (5U)
    -
    - -
    -
    - -

    ◆ CAN_F11R1_FB5_Msk

    - -
    -
    - - - - -
    #define CAN_F11R1_FB5_Msk   (0x1UL << CAN_F11R1_FB5_Pos)
    -
    -

    0x00000020

    - -
    -
    - -

    ◆ CAN_F11R1_FB5

    - -
    -
    - - - - -
    #define CAN_F11R1_FB5   CAN_F11R1_FB5_Msk
    -
    -

    Filter bit 5

    - -
    -
    - -

    ◆ CAN_F11R1_FB6_Pos

    - -
    -
    - - - - -
    #define CAN_F11R1_FB6_Pos   (6U)
    -
    - -
    -
    - -

    ◆ CAN_F11R1_FB6_Msk

    - -
    -
    - - - - -
    #define CAN_F11R1_FB6_Msk   (0x1UL << CAN_F11R1_FB6_Pos)
    -
    -

    0x00000040

    - -
    -
    - -

    ◆ CAN_F11R1_FB6

    - -
    -
    - - - - -
    #define CAN_F11R1_FB6   CAN_F11R1_FB6_Msk
    -
    -

    Filter bit 6

    - -
    -
    - -

    ◆ CAN_F11R1_FB7_Pos

    - -
    -
    - - - - -
    #define CAN_F11R1_FB7_Pos   (7U)
    -
    - -
    -
    - -

    ◆ CAN_F11R1_FB7_Msk

    - -
    -
    - - - - -
    #define CAN_F11R1_FB7_Msk   (0x1UL << CAN_F11R1_FB7_Pos)
    -
    -

    0x00000080

    - -
    -
    - -

    ◆ CAN_F11R1_FB7

    - -
    -
    - - - - -
    #define CAN_F11R1_FB7   CAN_F11R1_FB7_Msk
    -
    -

    Filter bit 7

    - -
    -
    - -

    ◆ CAN_F11R1_FB8_Pos

    - -
    -
    - - - - -
    #define CAN_F11R1_FB8_Pos   (8U)
    -
    - -
    -
    - -

    ◆ CAN_F11R1_FB8_Msk

    - -
    -
    - - - - -
    #define CAN_F11R1_FB8_Msk   (0x1UL << CAN_F11R1_FB8_Pos)
    -
    -

    0x00000100

    - -
    -
    - -

    ◆ CAN_F11R1_FB8

    - -
    -
    - - - - -
    #define CAN_F11R1_FB8   CAN_F11R1_FB8_Msk
    -
    -

    Filter bit 8

    - -
    -
    - -

    ◆ CAN_F11R1_FB9_Pos

    - -
    -
    - - - - -
    #define CAN_F11R1_FB9_Pos   (9U)
    -
    - -
    -
    - -

    ◆ CAN_F11R1_FB9_Msk

    - -
    -
    - - - - -
    #define CAN_F11R1_FB9_Msk   (0x1UL << CAN_F11R1_FB9_Pos)
    -
    -

    0x00000200

    - -
    -
    - -

    ◆ CAN_F11R1_FB9

    - -
    -
    - - - - -
    #define CAN_F11R1_FB9   CAN_F11R1_FB9_Msk
    -
    -

    Filter bit 9

    - -
    -
    - -

    ◆ CAN_F11R1_FB10_Pos

    - -
    -
    - - - - -
    #define CAN_F11R1_FB10_Pos   (10U)
    -
    - -
    -
    - -

    ◆ CAN_F11R1_FB10_Msk

    - -
    -
    - - - - -
    #define CAN_F11R1_FB10_Msk   (0x1UL << CAN_F11R1_FB10_Pos)
    -
    -

    0x00000400

    - -
    -
    - -

    ◆ CAN_F11R1_FB10

    - -
    -
    - - - - -
    #define CAN_F11R1_FB10   CAN_F11R1_FB10_Msk
    -
    -

    Filter bit 10

    - -
    -
    - -

    ◆ CAN_F11R1_FB11_Pos

    - -
    -
    - - - - -
    #define CAN_F11R1_FB11_Pos   (11U)
    -
    - -
    -
    - -

    ◆ CAN_F11R1_FB11_Msk

    - -
    -
    - - - - -
    #define CAN_F11R1_FB11_Msk   (0x1UL << CAN_F11R1_FB11_Pos)
    -
    -

    0x00000800

    - -
    -
    - -

    ◆ CAN_F11R1_FB11

    - -
    -
    - - - - -
    #define CAN_F11R1_FB11   CAN_F11R1_FB11_Msk
    -
    -

    Filter bit 11

    - -
    -
    - -

    ◆ CAN_F11R1_FB12_Pos

    - -
    -
    - - - - -
    #define CAN_F11R1_FB12_Pos   (12U)
    -
    - -
    -
    - -

    ◆ CAN_F11R1_FB12_Msk

    - -
    -
    - - - - -
    #define CAN_F11R1_FB12_Msk   (0x1UL << CAN_F11R1_FB12_Pos)
    -
    -

    0x00001000

    - -
    -
    - -

    ◆ CAN_F11R1_FB12

    - -
    -
    - - - - -
    #define CAN_F11R1_FB12   CAN_F11R1_FB12_Msk
    -
    -

    Filter bit 12

    - -
    -
    - -

    ◆ CAN_F11R1_FB13_Pos

    - -
    -
    - - - - -
    #define CAN_F11R1_FB13_Pos   (13U)
    -
    - -
    -
    - -

    ◆ CAN_F11R1_FB13_Msk

    - -
    -
    - - - - -
    #define CAN_F11R1_FB13_Msk   (0x1UL << CAN_F11R1_FB13_Pos)
    -
    -

    0x00002000

    - -
    -
    - -

    ◆ CAN_F11R1_FB13

    - -
    -
    - - - - -
    #define CAN_F11R1_FB13   CAN_F11R1_FB13_Msk
    -
    -

    Filter bit 13

    - -
    -
    - -

    ◆ CAN_F11R1_FB14_Pos

    - -
    -
    - - - - -
    #define CAN_F11R1_FB14_Pos   (14U)
    -
    - -
    -
    - -

    ◆ CAN_F11R1_FB14_Msk

    - -
    -
    - - - - -
    #define CAN_F11R1_FB14_Msk   (0x1UL << CAN_F11R1_FB14_Pos)
    -
    -

    0x00004000

    - -
    -
    - -

    ◆ CAN_F11R1_FB14

    - -
    -
    - - - - -
    #define CAN_F11R1_FB14   CAN_F11R1_FB14_Msk
    -
    -

    Filter bit 14

    - -
    -
    - -

    ◆ CAN_F11R1_FB15_Pos

    - -
    -
    - - - - -
    #define CAN_F11R1_FB15_Pos   (15U)
    -
    - -
    -
    - -

    ◆ CAN_F11R1_FB15_Msk

    - -
    -
    - - - - -
    #define CAN_F11R1_FB15_Msk   (0x1UL << CAN_F11R1_FB15_Pos)
    -
    -

    0x00008000

    - -
    -
    - -

    ◆ CAN_F11R1_FB15

    - -
    -
    - - - - -
    #define CAN_F11R1_FB15   CAN_F11R1_FB15_Msk
    -
    -

    Filter bit 15

    - -
    -
    - -

    ◆ CAN_F11R1_FB16_Pos

    - -
    -
    - - - - -
    #define CAN_F11R1_FB16_Pos   (16U)
    -
    - -
    -
    - -

    ◆ CAN_F11R1_FB16_Msk

    - -
    -
    - - - - -
    #define CAN_F11R1_FB16_Msk   (0x1UL << CAN_F11R1_FB16_Pos)
    -
    -

    0x00010000

    - -
    -
    - -

    ◆ CAN_F11R1_FB16

    - -
    -
    - - - - -
    #define CAN_F11R1_FB16   CAN_F11R1_FB16_Msk
    -
    -

    Filter bit 16

    - -
    -
    - -

    ◆ CAN_F11R1_FB17_Pos

    - -
    -
    - - - - -
    #define CAN_F11R1_FB17_Pos   (17U)
    -
    - -
    -
    - -

    ◆ CAN_F11R1_FB17_Msk

    - -
    -
    - - - - -
    #define CAN_F11R1_FB17_Msk   (0x1UL << CAN_F11R1_FB17_Pos)
    -
    -

    0x00020000

    - -
    -
    - -

    ◆ CAN_F11R1_FB17

    - -
    -
    - - - - -
    #define CAN_F11R1_FB17   CAN_F11R1_FB17_Msk
    -
    -

    Filter bit 17

    - -
    -
    - -

    ◆ CAN_F11R1_FB18_Pos

    - -
    -
    - - - - -
    #define CAN_F11R1_FB18_Pos   (18U)
    -
    - -
    -
    - -

    ◆ CAN_F11R1_FB18_Msk

    - -
    -
    - - - - -
    #define CAN_F11R1_FB18_Msk   (0x1UL << CAN_F11R1_FB18_Pos)
    -
    -

    0x00040000

    - -
    -
    - -

    ◆ CAN_F11R1_FB18

    - -
    -
    - - - - -
    #define CAN_F11R1_FB18   CAN_F11R1_FB18_Msk
    -
    -

    Filter bit 18

    - -
    -
    - -

    ◆ CAN_F11R1_FB19_Pos

    - -
    -
    - - - - -
    #define CAN_F11R1_FB19_Pos   (19U)
    -
    - -
    -
    - -

    ◆ CAN_F11R1_FB19_Msk

    - -
    -
    - - - - -
    #define CAN_F11R1_FB19_Msk   (0x1UL << CAN_F11R1_FB19_Pos)
    -
    -

    0x00080000

    - -
    -
    - -

    ◆ CAN_F11R1_FB19

    - -
    -
    - - - - -
    #define CAN_F11R1_FB19   CAN_F11R1_FB19_Msk
    -
    -

    Filter bit 19

    - -
    -
    - -

    ◆ CAN_F11R1_FB20_Pos

    - -
    -
    - - - - -
    #define CAN_F11R1_FB20_Pos   (20U)
    -
    - -
    -
    - -

    ◆ CAN_F11R1_FB20_Msk

    - -
    -
    - - - - -
    #define CAN_F11R1_FB20_Msk   (0x1UL << CAN_F11R1_FB20_Pos)
    -
    -

    0x00100000

    - -
    -
    - -

    ◆ CAN_F11R1_FB20

    - -
    -
    - - - - -
    #define CAN_F11R1_FB20   CAN_F11R1_FB20_Msk
    -
    -

    Filter bit 20

    - -
    -
    - -

    ◆ CAN_F11R1_FB21_Pos

    - -
    -
    - - - - -
    #define CAN_F11R1_FB21_Pos   (21U)
    -
    - -
    -
    - -

    ◆ CAN_F11R1_FB21_Msk

    - -
    -
    - - - - -
    #define CAN_F11R1_FB21_Msk   (0x1UL << CAN_F11R1_FB21_Pos)
    -
    -

    0x00200000

    - -
    -
    - -

    ◆ CAN_F11R1_FB21

    - -
    -
    - - - - -
    #define CAN_F11R1_FB21   CAN_F11R1_FB21_Msk
    -
    -

    Filter bit 21

    - -
    -
    - -

    ◆ CAN_F11R1_FB22_Pos

    - -
    -
    - - - - -
    #define CAN_F11R1_FB22_Pos   (22U)
    -
    - -
    -
    - -

    ◆ CAN_F11R1_FB22_Msk

    - -
    -
    - - - - -
    #define CAN_F11R1_FB22_Msk   (0x1UL << CAN_F11R1_FB22_Pos)
    -
    -

    0x00400000

    - -
    -
    - -

    ◆ CAN_F11R1_FB22

    - -
    -
    - - - - -
    #define CAN_F11R1_FB22   CAN_F11R1_FB22_Msk
    -
    -

    Filter bit 22

    - -
    -
    - -

    ◆ CAN_F11R1_FB23_Pos

    - -
    -
    - - - - -
    #define CAN_F11R1_FB23_Pos   (23U)
    -
    - -
    -
    - -

    ◆ CAN_F11R1_FB23_Msk

    - -
    -
    - - - - -
    #define CAN_F11R1_FB23_Msk   (0x1UL << CAN_F11R1_FB23_Pos)
    -
    -

    0x00800000

    - -
    -
    - -

    ◆ CAN_F11R1_FB23

    - -
    -
    - - - - -
    #define CAN_F11R1_FB23   CAN_F11R1_FB23_Msk
    -
    -

    Filter bit 23

    - -
    -
    - -

    ◆ CAN_F11R1_FB24_Pos

    - -
    -
    - - - - -
    #define CAN_F11R1_FB24_Pos   (24U)
    -
    - -
    -
    - -

    ◆ CAN_F11R1_FB24_Msk

    - -
    -
    - - - - -
    #define CAN_F11R1_FB24_Msk   (0x1UL << CAN_F11R1_FB24_Pos)
    -
    -

    0x01000000

    - -
    -
    - -

    ◆ CAN_F11R1_FB24

    - -
    -
    - - - - -
    #define CAN_F11R1_FB24   CAN_F11R1_FB24_Msk
    -
    -

    Filter bit 24

    - -
    -
    - -

    ◆ CAN_F11R1_FB25_Pos

    - -
    -
    - - - - -
    #define CAN_F11R1_FB25_Pos   (25U)
    -
    - -
    -
    - -

    ◆ CAN_F11R1_FB25_Msk

    - -
    -
    - - - - -
    #define CAN_F11R1_FB25_Msk   (0x1UL << CAN_F11R1_FB25_Pos)
    -
    -

    0x02000000

    - -
    -
    - -

    ◆ CAN_F11R1_FB25

    - -
    -
    - - - - -
    #define CAN_F11R1_FB25   CAN_F11R1_FB25_Msk
    -
    -

    Filter bit 25

    - -
    -
    - -

    ◆ CAN_F11R1_FB26_Pos

    - -
    -
    - - - - -
    #define CAN_F11R1_FB26_Pos   (26U)
    -
    - -
    -
    - -

    ◆ CAN_F11R1_FB26_Msk

    - -
    -
    - - - - -
    #define CAN_F11R1_FB26_Msk   (0x1UL << CAN_F11R1_FB26_Pos)
    -
    -

    0x04000000

    - -
    -
    - -

    ◆ CAN_F11R1_FB26

    - -
    -
    - - - - -
    #define CAN_F11R1_FB26   CAN_F11R1_FB26_Msk
    -
    -

    Filter bit 26

    - -
    -
    - -

    ◆ CAN_F11R1_FB27_Pos

    - -
    -
    - - - - -
    #define CAN_F11R1_FB27_Pos   (27U)
    -
    - -
    -
    - -

    ◆ CAN_F11R1_FB27_Msk

    - -
    -
    - - - - -
    #define CAN_F11R1_FB27_Msk   (0x1UL << CAN_F11R1_FB27_Pos)
    -
    -

    0x08000000

    - -
    -
    - -

    ◆ CAN_F11R1_FB27

    - -
    -
    - - - - -
    #define CAN_F11R1_FB27   CAN_F11R1_FB27_Msk
    -
    -

    Filter bit 27

    - -
    -
    - -

    ◆ CAN_F11R1_FB28_Pos

    - -
    -
    - - - - -
    #define CAN_F11R1_FB28_Pos   (28U)
    -
    - -
    -
    - -

    ◆ CAN_F11R1_FB28_Msk

    - -
    -
    - - - - -
    #define CAN_F11R1_FB28_Msk   (0x1UL << CAN_F11R1_FB28_Pos)
    -
    -

    0x10000000

    - -
    -
    - -

    ◆ CAN_F11R1_FB28

    - -
    -
    - - - - -
    #define CAN_F11R1_FB28   CAN_F11R1_FB28_Msk
    -
    -

    Filter bit 28

    - -
    -
    - -

    ◆ CAN_F11R1_FB29_Pos

    - -
    -
    - - - - -
    #define CAN_F11R1_FB29_Pos   (29U)
    -
    - -
    -
    - -

    ◆ CAN_F11R1_FB29_Msk

    - -
    -
    - - - - -
    #define CAN_F11R1_FB29_Msk   (0x1UL << CAN_F11R1_FB29_Pos)
    -
    -

    0x20000000

    - -
    -
    - -

    ◆ CAN_F11R1_FB29

    - -
    -
    - - - - -
    #define CAN_F11R1_FB29   CAN_F11R1_FB29_Msk
    -
    -

    Filter bit 29

    - -
    -
    - -

    ◆ CAN_F11R1_FB30_Pos

    - -
    -
    - - - - -
    #define CAN_F11R1_FB30_Pos   (30U)
    -
    - -
    -
    - -

    ◆ CAN_F11R1_FB30_Msk

    - -
    -
    - - - - -
    #define CAN_F11R1_FB30_Msk   (0x1UL << CAN_F11R1_FB30_Pos)
    -
    -

    0x40000000

    - -
    -
    - -

    ◆ CAN_F11R1_FB30

    - -
    -
    - - - - -
    #define CAN_F11R1_FB30   CAN_F11R1_FB30_Msk
    -
    -

    Filter bit 30

    - -
    -
    - -

    ◆ CAN_F11R1_FB31_Pos

    - -
    -
    - - - - -
    #define CAN_F11R1_FB31_Pos   (31U)
    -
    - -
    -
    - -

    ◆ CAN_F11R1_FB31_Msk

    - -
    -
    - - - - -
    #define CAN_F11R1_FB31_Msk   (0x1UL << CAN_F11R1_FB31_Pos)
    -
    -

    0x80000000

    - -
    -
    - -

    ◆ CAN_F11R1_FB31

    - -
    -
    - - - - -
    #define CAN_F11R1_FB31   CAN_F11R1_FB31_Msk
    -
    -

    Filter bit 31

    - -
    -
    - -

    ◆ CAN_F12R1_FB0_Pos

    - -
    -
    - - - - -
    #define CAN_F12R1_FB0_Pos   (0U)
    -
    - -
    -
    - -

    ◆ CAN_F12R1_FB0_Msk

    - -
    -
    - - - - -
    #define CAN_F12R1_FB0_Msk   (0x1UL << CAN_F12R1_FB0_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ CAN_F12R1_FB0

    - -
    -
    - - - - -
    #define CAN_F12R1_FB0   CAN_F12R1_FB0_Msk
    -
    -

    Filter bit 0

    - -
    -
    - -

    ◆ CAN_F12R1_FB1_Pos

    - -
    -
    - - - - -
    #define CAN_F12R1_FB1_Pos   (1U)
    -
    - -
    -
    - -

    ◆ CAN_F12R1_FB1_Msk

    - -
    -
    - - - - -
    #define CAN_F12R1_FB1_Msk   (0x1UL << CAN_F12R1_FB1_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ CAN_F12R1_FB1

    - -
    -
    - - - - -
    #define CAN_F12R1_FB1   CAN_F12R1_FB1_Msk
    -
    -

    Filter bit 1

    - -
    -
    - -

    ◆ CAN_F12R1_FB2_Pos

    - -
    -
    - - - - -
    #define CAN_F12R1_FB2_Pos   (2U)
    -
    - -
    -
    - -

    ◆ CAN_F12R1_FB2_Msk

    - -
    -
    - - - - -
    #define CAN_F12R1_FB2_Msk   (0x1UL << CAN_F12R1_FB2_Pos)
    -
    -

    0x00000004

    - -
    -
    - -

    ◆ CAN_F12R1_FB2

    - -
    -
    - - - - -
    #define CAN_F12R1_FB2   CAN_F12R1_FB2_Msk
    -
    -

    Filter bit 2

    - -
    -
    - -

    ◆ CAN_F12R1_FB3_Pos

    - -
    -
    - - - - -
    #define CAN_F12R1_FB3_Pos   (3U)
    -
    - -
    -
    - -

    ◆ CAN_F12R1_FB3_Msk

    - -
    -
    - - - - -
    #define CAN_F12R1_FB3_Msk   (0x1UL << CAN_F12R1_FB3_Pos)
    -
    -

    0x00000008

    - -
    -
    - -

    ◆ CAN_F12R1_FB3

    - -
    -
    - - - - -
    #define CAN_F12R1_FB3   CAN_F12R1_FB3_Msk
    -
    -

    Filter bit 3

    - -
    -
    - -

    ◆ CAN_F12R1_FB4_Pos

    - -
    -
    - - - - -
    #define CAN_F12R1_FB4_Pos   (4U)
    -
    - -
    -
    - -

    ◆ CAN_F12R1_FB4_Msk

    - -
    -
    - - - - -
    #define CAN_F12R1_FB4_Msk   (0x1UL << CAN_F12R1_FB4_Pos)
    -
    -

    0x00000010

    - -
    -
    - -

    ◆ CAN_F12R1_FB4

    - -
    -
    - - - - -
    #define CAN_F12R1_FB4   CAN_F12R1_FB4_Msk
    -
    -

    Filter bit 4

    - -
    -
    - -

    ◆ CAN_F12R1_FB5_Pos

    - -
    -
    - - - - -
    #define CAN_F12R1_FB5_Pos   (5U)
    -
    - -
    -
    - -

    ◆ CAN_F12R1_FB5_Msk

    - -
    -
    - - - - -
    #define CAN_F12R1_FB5_Msk   (0x1UL << CAN_F12R1_FB5_Pos)
    -
    -

    0x00000020

    - -
    -
    - -

    ◆ CAN_F12R1_FB5

    - -
    -
    - - - - -
    #define CAN_F12R1_FB5   CAN_F12R1_FB5_Msk
    -
    -

    Filter bit 5

    - -
    -
    - -

    ◆ CAN_F12R1_FB6_Pos

    - -
    -
    - - - - -
    #define CAN_F12R1_FB6_Pos   (6U)
    -
    - -
    -
    - -

    ◆ CAN_F12R1_FB6_Msk

    - -
    -
    - - - - -
    #define CAN_F12R1_FB6_Msk   (0x1UL << CAN_F12R1_FB6_Pos)
    -
    -

    0x00000040

    - -
    -
    - -

    ◆ CAN_F12R1_FB6

    - -
    -
    - - - - -
    #define CAN_F12R1_FB6   CAN_F12R1_FB6_Msk
    -
    -

    Filter bit 6

    - -
    -
    - -

    ◆ CAN_F12R1_FB7_Pos

    - -
    -
    - - - - -
    #define CAN_F12R1_FB7_Pos   (7U)
    -
    - -
    -
    - -

    ◆ CAN_F12R1_FB7_Msk

    - -
    -
    - - - - -
    #define CAN_F12R1_FB7_Msk   (0x1UL << CAN_F12R1_FB7_Pos)
    -
    -

    0x00000080

    - -
    -
    - -

    ◆ CAN_F12R1_FB7

    - -
    -
    - - - - -
    #define CAN_F12R1_FB7   CAN_F12R1_FB7_Msk
    -
    -

    Filter bit 7

    - -
    -
    - -

    ◆ CAN_F12R1_FB8_Pos

    - -
    -
    - - - - -
    #define CAN_F12R1_FB8_Pos   (8U)
    -
    - -
    -
    - -

    ◆ CAN_F12R1_FB8_Msk

    - -
    -
    - - - - -
    #define CAN_F12R1_FB8_Msk   (0x1UL << CAN_F12R1_FB8_Pos)
    -
    -

    0x00000100

    - -
    -
    - -

    ◆ CAN_F12R1_FB8

    - -
    -
    - - - - -
    #define CAN_F12R1_FB8   CAN_F12R1_FB8_Msk
    -
    -

    Filter bit 8

    - -
    -
    - -

    ◆ CAN_F12R1_FB9_Pos

    - -
    -
    - - - - -
    #define CAN_F12R1_FB9_Pos   (9U)
    -
    - -
    -
    - -

    ◆ CAN_F12R1_FB9_Msk

    - -
    -
    - - - - -
    #define CAN_F12R1_FB9_Msk   (0x1UL << CAN_F12R1_FB9_Pos)
    -
    -

    0x00000200

    - -
    -
    - -

    ◆ CAN_F12R1_FB9

    - -
    -
    - - - - -
    #define CAN_F12R1_FB9   CAN_F12R1_FB9_Msk
    -
    -

    Filter bit 9

    - -
    -
    - -

    ◆ CAN_F12R1_FB10_Pos

    - -
    -
    - - - - -
    #define CAN_F12R1_FB10_Pos   (10U)
    -
    - -
    -
    - -

    ◆ CAN_F12R1_FB10_Msk

    - -
    -
    - - - - -
    #define CAN_F12R1_FB10_Msk   (0x1UL << CAN_F12R1_FB10_Pos)
    -
    -

    0x00000400

    - -
    -
    - -

    ◆ CAN_F12R1_FB10

    - -
    -
    - - - - -
    #define CAN_F12R1_FB10   CAN_F12R1_FB10_Msk
    -
    -

    Filter bit 10

    - -
    -
    - -

    ◆ CAN_F12R1_FB11_Pos

    - -
    -
    - - - - -
    #define CAN_F12R1_FB11_Pos   (11U)
    -
    - -
    -
    - -

    ◆ CAN_F12R1_FB11_Msk

    - -
    -
    - - - - -
    #define CAN_F12R1_FB11_Msk   (0x1UL << CAN_F12R1_FB11_Pos)
    -
    -

    0x00000800

    - -
    -
    - -

    ◆ CAN_F12R1_FB11

    - -
    -
    - - - - -
    #define CAN_F12R1_FB11   CAN_F12R1_FB11_Msk
    -
    -

    Filter bit 11

    - -
    -
    - -

    ◆ CAN_F12R1_FB12_Pos

    - -
    -
    - - - - -
    #define CAN_F12R1_FB12_Pos   (12U)
    -
    - -
    -
    - -

    ◆ CAN_F12R1_FB12_Msk

    - -
    -
    - - - - -
    #define CAN_F12R1_FB12_Msk   (0x1UL << CAN_F12R1_FB12_Pos)
    -
    -

    0x00001000

    - -
    -
    - -

    ◆ CAN_F12R1_FB12

    - -
    -
    - - - - -
    #define CAN_F12R1_FB12   CAN_F12R1_FB12_Msk
    -
    -

    Filter bit 12

    - -
    -
    - -

    ◆ CAN_F12R1_FB13_Pos

    - -
    -
    - - - - -
    #define CAN_F12R1_FB13_Pos   (13U)
    -
    - -
    -
    - -

    ◆ CAN_F12R1_FB13_Msk

    - -
    -
    - - - - -
    #define CAN_F12R1_FB13_Msk   (0x1UL << CAN_F12R1_FB13_Pos)
    -
    -

    0x00002000

    - -
    -
    - -

    ◆ CAN_F12R1_FB13

    - -
    -
    - - - - -
    #define CAN_F12R1_FB13   CAN_F12R1_FB13_Msk
    -
    -

    Filter bit 13

    - -
    -
    - -

    ◆ CAN_F12R1_FB14_Pos

    - -
    -
    - - - - -
    #define CAN_F12R1_FB14_Pos   (14U)
    -
    - -
    -
    - -

    ◆ CAN_F12R1_FB14_Msk

    - -
    -
    - - - - -
    #define CAN_F12R1_FB14_Msk   (0x1UL << CAN_F12R1_FB14_Pos)
    -
    -

    0x00004000

    - -
    -
    - -

    ◆ CAN_F12R1_FB14

    - -
    -
    - - - - -
    #define CAN_F12R1_FB14   CAN_F12R1_FB14_Msk
    -
    -

    Filter bit 14

    - -
    -
    - -

    ◆ CAN_F12R1_FB15_Pos

    - -
    -
    - - - - -
    #define CAN_F12R1_FB15_Pos   (15U)
    -
    - -
    -
    - -

    ◆ CAN_F12R1_FB15_Msk

    - -
    -
    - - - - -
    #define CAN_F12R1_FB15_Msk   (0x1UL << CAN_F12R1_FB15_Pos)
    -
    -

    0x00008000

    - -
    -
    - -

    ◆ CAN_F12R1_FB15

    - -
    -
    - - - - -
    #define CAN_F12R1_FB15   CAN_F12R1_FB15_Msk
    -
    -

    Filter bit 15

    - -
    -
    - -

    ◆ CAN_F12R1_FB16_Pos

    - -
    -
    - - - - -
    #define CAN_F12R1_FB16_Pos   (16U)
    -
    - -
    -
    - -

    ◆ CAN_F12R1_FB16_Msk

    - -
    -
    - - - - -
    #define CAN_F12R1_FB16_Msk   (0x1UL << CAN_F12R1_FB16_Pos)
    -
    -

    0x00010000

    - -
    -
    - -

    ◆ CAN_F12R1_FB16

    - -
    -
    - - - - -
    #define CAN_F12R1_FB16   CAN_F12R1_FB16_Msk
    -
    -

    Filter bit 16

    - -
    -
    - -

    ◆ CAN_F12R1_FB17_Pos

    - -
    -
    - - - - -
    #define CAN_F12R1_FB17_Pos   (17U)
    -
    - -
    -
    - -

    ◆ CAN_F12R1_FB17_Msk

    - -
    -
    - - - - -
    #define CAN_F12R1_FB17_Msk   (0x1UL << CAN_F12R1_FB17_Pos)
    -
    -

    0x00020000

    - -
    -
    - -

    ◆ CAN_F12R1_FB17

    - -
    -
    - - - - -
    #define CAN_F12R1_FB17   CAN_F12R1_FB17_Msk
    -
    -

    Filter bit 17

    - -
    -
    - -

    ◆ CAN_F12R1_FB18_Pos

    - -
    -
    - - - - -
    #define CAN_F12R1_FB18_Pos   (18U)
    -
    - -
    -
    - -

    ◆ CAN_F12R1_FB18_Msk

    - -
    -
    - - - - -
    #define CAN_F12R1_FB18_Msk   (0x1UL << CAN_F12R1_FB18_Pos)
    -
    -

    0x00040000

    - -
    -
    - -

    ◆ CAN_F12R1_FB18

    - -
    -
    - - - - -
    #define CAN_F12R1_FB18   CAN_F12R1_FB18_Msk
    -
    -

    Filter bit 18

    - -
    -
    - -

    ◆ CAN_F12R1_FB19_Pos

    - -
    -
    - - - - -
    #define CAN_F12R1_FB19_Pos   (19U)
    -
    - -
    -
    - -

    ◆ CAN_F12R1_FB19_Msk

    - -
    -
    - - - - -
    #define CAN_F12R1_FB19_Msk   (0x1UL << CAN_F12R1_FB19_Pos)
    -
    -

    0x00080000

    - -
    -
    - -

    ◆ CAN_F12R1_FB19

    - -
    -
    - - - - -
    #define CAN_F12R1_FB19   CAN_F12R1_FB19_Msk
    -
    -

    Filter bit 19

    - -
    -
    - -

    ◆ CAN_F12R1_FB20_Pos

    - -
    -
    - - - - -
    #define CAN_F12R1_FB20_Pos   (20U)
    -
    - -
    -
    - -

    ◆ CAN_F12R1_FB20_Msk

    - -
    -
    - - - - -
    #define CAN_F12R1_FB20_Msk   (0x1UL << CAN_F12R1_FB20_Pos)
    -
    -

    0x00100000

    - -
    -
    - -

    ◆ CAN_F12R1_FB20

    - -
    -
    - - - - -
    #define CAN_F12R1_FB20   CAN_F12R1_FB20_Msk
    -
    -

    Filter bit 20

    - -
    -
    - -

    ◆ CAN_F12R1_FB21_Pos

    - -
    -
    - - - - -
    #define CAN_F12R1_FB21_Pos   (21U)
    -
    - -
    -
    - -

    ◆ CAN_F12R1_FB21_Msk

    - -
    -
    - - - - -
    #define CAN_F12R1_FB21_Msk   (0x1UL << CAN_F12R1_FB21_Pos)
    -
    -

    0x00200000

    - -
    -
    - -

    ◆ CAN_F12R1_FB21

    - -
    -
    - - - - -
    #define CAN_F12R1_FB21   CAN_F12R1_FB21_Msk
    -
    -

    Filter bit 21

    - -
    -
    - -

    ◆ CAN_F12R1_FB22_Pos

    - -
    -
    - - - - -
    #define CAN_F12R1_FB22_Pos   (22U)
    -
    - -
    -
    - -

    ◆ CAN_F12R1_FB22_Msk

    - -
    -
    - - - - -
    #define CAN_F12R1_FB22_Msk   (0x1UL << CAN_F12R1_FB22_Pos)
    -
    -

    0x00400000

    - -
    -
    - -

    ◆ CAN_F12R1_FB22

    - -
    -
    - - - - -
    #define CAN_F12R1_FB22   CAN_F12R1_FB22_Msk
    -
    -

    Filter bit 22

    - -
    -
    - -

    ◆ CAN_F12R1_FB23_Pos

    - -
    -
    - - - - -
    #define CAN_F12R1_FB23_Pos   (23U)
    -
    - -
    -
    - -

    ◆ CAN_F12R1_FB23_Msk

    - -
    -
    - - - - -
    #define CAN_F12R1_FB23_Msk   (0x1UL << CAN_F12R1_FB23_Pos)
    -
    -

    0x00800000

    - -
    -
    - -

    ◆ CAN_F12R1_FB23

    - -
    -
    - - - - -
    #define CAN_F12R1_FB23   CAN_F12R1_FB23_Msk
    -
    -

    Filter bit 23

    - -
    -
    - -

    ◆ CAN_F12R1_FB24_Pos

    - -
    -
    - - - - -
    #define CAN_F12R1_FB24_Pos   (24U)
    -
    - -
    -
    - -

    ◆ CAN_F12R1_FB24_Msk

    - -
    -
    - - - - -
    #define CAN_F12R1_FB24_Msk   (0x1UL << CAN_F12R1_FB24_Pos)
    -
    -

    0x01000000

    - -
    -
    - -

    ◆ CAN_F12R1_FB24

    - -
    -
    - - - - -
    #define CAN_F12R1_FB24   CAN_F12R1_FB24_Msk
    -
    -

    Filter bit 24

    - -
    -
    - -

    ◆ CAN_F12R1_FB25_Pos

    - -
    -
    - - - - -
    #define CAN_F12R1_FB25_Pos   (25U)
    -
    - -
    -
    - -

    ◆ CAN_F12R1_FB25_Msk

    - -
    -
    - - - - -
    #define CAN_F12R1_FB25_Msk   (0x1UL << CAN_F12R1_FB25_Pos)
    -
    -

    0x02000000

    - -
    -
    - -

    ◆ CAN_F12R1_FB25

    - -
    -
    - - - - -
    #define CAN_F12R1_FB25   CAN_F12R1_FB25_Msk
    -
    -

    Filter bit 25

    - -
    -
    - -

    ◆ CAN_F12R1_FB26_Pos

    - -
    -
    - - - - -
    #define CAN_F12R1_FB26_Pos   (26U)
    -
    - -
    -
    - -

    ◆ CAN_F12R1_FB26_Msk

    - -
    -
    - - - - -
    #define CAN_F12R1_FB26_Msk   (0x1UL << CAN_F12R1_FB26_Pos)
    -
    -

    0x04000000

    - -
    -
    - -

    ◆ CAN_F12R1_FB26

    - -
    -
    - - - - -
    #define CAN_F12R1_FB26   CAN_F12R1_FB26_Msk
    -
    -

    Filter bit 26

    - -
    -
    - -

    ◆ CAN_F12R1_FB27_Pos

    - -
    -
    - - - - -
    #define CAN_F12R1_FB27_Pos   (27U)
    -
    - -
    -
    - -

    ◆ CAN_F12R1_FB27_Msk

    - -
    -
    - - - - -
    #define CAN_F12R1_FB27_Msk   (0x1UL << CAN_F12R1_FB27_Pos)
    -
    -

    0x08000000

    - -
    -
    - -

    ◆ CAN_F12R1_FB27

    - -
    -
    - - - - -
    #define CAN_F12R1_FB27   CAN_F12R1_FB27_Msk
    -
    -

    Filter bit 27

    - -
    -
    - -

    ◆ CAN_F12R1_FB28_Pos

    - -
    -
    - - - - -
    #define CAN_F12R1_FB28_Pos   (28U)
    -
    - -
    -
    - -

    ◆ CAN_F12R1_FB28_Msk

    - -
    -
    - - - - -
    #define CAN_F12R1_FB28_Msk   (0x1UL << CAN_F12R1_FB28_Pos)
    -
    -

    0x10000000

    - -
    -
    - -

    ◆ CAN_F12R1_FB28

    - -
    -
    - - - - -
    #define CAN_F12R1_FB28   CAN_F12R1_FB28_Msk
    -
    -

    Filter bit 28

    - -
    -
    - -

    ◆ CAN_F12R1_FB29_Pos

    - -
    -
    - - - - -
    #define CAN_F12R1_FB29_Pos   (29U)
    -
    - -
    -
    - -

    ◆ CAN_F12R1_FB29_Msk

    - -
    -
    - - - - -
    #define CAN_F12R1_FB29_Msk   (0x1UL << CAN_F12R1_FB29_Pos)
    -
    -

    0x20000000

    - -
    -
    - -

    ◆ CAN_F12R1_FB29

    - -
    -
    - - - - -
    #define CAN_F12R1_FB29   CAN_F12R1_FB29_Msk
    -
    -

    Filter bit 29

    - -
    -
    - -

    ◆ CAN_F12R1_FB30_Pos

    - -
    -
    - - - - -
    #define CAN_F12R1_FB30_Pos   (30U)
    -
    - -
    -
    - -

    ◆ CAN_F12R1_FB30_Msk

    - -
    -
    - - - - -
    #define CAN_F12R1_FB30_Msk   (0x1UL << CAN_F12R1_FB30_Pos)
    -
    -

    0x40000000

    - -
    -
    - -

    ◆ CAN_F12R1_FB30

    - -
    -
    - - - - -
    #define CAN_F12R1_FB30   CAN_F12R1_FB30_Msk
    -
    -

    Filter bit 30

    - -
    -
    - -

    ◆ CAN_F12R1_FB31_Pos

    - -
    -
    - - - - -
    #define CAN_F12R1_FB31_Pos   (31U)
    -
    - -
    -
    - -

    ◆ CAN_F12R1_FB31_Msk

    - -
    -
    - - - - -
    #define CAN_F12R1_FB31_Msk   (0x1UL << CAN_F12R1_FB31_Pos)
    -
    -

    0x80000000

    - -
    -
    - -

    ◆ CAN_F12R1_FB31

    - -
    -
    - - - - -
    #define CAN_F12R1_FB31   CAN_F12R1_FB31_Msk
    -
    -

    Filter bit 31

    - -
    -
    - -

    ◆ CAN_F13R1_FB0_Pos

    - -
    -
    - - - - -
    #define CAN_F13R1_FB0_Pos   (0U)
    -
    - -
    -
    - -

    ◆ CAN_F13R1_FB0_Msk

    - -
    -
    - - - - -
    #define CAN_F13R1_FB0_Msk   (0x1UL << CAN_F13R1_FB0_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ CAN_F13R1_FB0

    - -
    -
    - - - - -
    #define CAN_F13R1_FB0   CAN_F13R1_FB0_Msk
    -
    -

    Filter bit 0

    - -
    -
    - -

    ◆ CAN_F13R1_FB1_Pos

    - -
    -
    - - - - -
    #define CAN_F13R1_FB1_Pos   (1U)
    -
    - -
    -
    - -

    ◆ CAN_F13R1_FB1_Msk

    - -
    -
    - - - - -
    #define CAN_F13R1_FB1_Msk   (0x1UL << CAN_F13R1_FB1_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ CAN_F13R1_FB1

    - -
    -
    - - - - -
    #define CAN_F13R1_FB1   CAN_F13R1_FB1_Msk
    -
    -

    Filter bit 1

    - -
    -
    - -

    ◆ CAN_F13R1_FB2_Pos

    - -
    -
    - - - - -
    #define CAN_F13R1_FB2_Pos   (2U)
    -
    - -
    -
    - -

    ◆ CAN_F13R1_FB2_Msk

    - -
    -
    - - - - -
    #define CAN_F13R1_FB2_Msk   (0x1UL << CAN_F13R1_FB2_Pos)
    -
    -

    0x00000004

    - -
    -
    - -

    ◆ CAN_F13R1_FB2

    - -
    -
    - - - - -
    #define CAN_F13R1_FB2   CAN_F13R1_FB2_Msk
    -
    -

    Filter bit 2

    - -
    -
    - -

    ◆ CAN_F13R1_FB3_Pos

    - -
    -
    - - - - -
    #define CAN_F13R1_FB3_Pos   (3U)
    -
    - -
    -
    - -

    ◆ CAN_F13R1_FB3_Msk

    - -
    -
    - - - - -
    #define CAN_F13R1_FB3_Msk   (0x1UL << CAN_F13R1_FB3_Pos)
    -
    -

    0x00000008

    - -
    -
    - -

    ◆ CAN_F13R1_FB3

    - -
    -
    - - - - -
    #define CAN_F13R1_FB3   CAN_F13R1_FB3_Msk
    -
    -

    Filter bit 3

    - -
    -
    - -

    ◆ CAN_F13R1_FB4_Pos

    - -
    -
    - - - - -
    #define CAN_F13R1_FB4_Pos   (4U)
    -
    - -
    -
    - -

    ◆ CAN_F13R1_FB4_Msk

    - -
    -
    - - - - -
    #define CAN_F13R1_FB4_Msk   (0x1UL << CAN_F13R1_FB4_Pos)
    -
    -

    0x00000010

    - -
    -
    - -

    ◆ CAN_F13R1_FB4

    - -
    -
    - - - - -
    #define CAN_F13R1_FB4   CAN_F13R1_FB4_Msk
    -
    -

    Filter bit 4

    - -
    -
    - -

    ◆ CAN_F13R1_FB5_Pos

    - -
    -
    - - - - -
    #define CAN_F13R1_FB5_Pos   (5U)
    -
    - -
    -
    - -

    ◆ CAN_F13R1_FB5_Msk

    - -
    -
    - - - - -
    #define CAN_F13R1_FB5_Msk   (0x1UL << CAN_F13R1_FB5_Pos)
    -
    -

    0x00000020

    - -
    -
    - -

    ◆ CAN_F13R1_FB5

    - -
    -
    - - - - -
    #define CAN_F13R1_FB5   CAN_F13R1_FB5_Msk
    -
    -

    Filter bit 5

    - -
    -
    - -

    ◆ CAN_F13R1_FB6_Pos

    - -
    -
    - - - - -
    #define CAN_F13R1_FB6_Pos   (6U)
    -
    - -
    -
    - -

    ◆ CAN_F13R1_FB6_Msk

    - -
    -
    - - - - -
    #define CAN_F13R1_FB6_Msk   (0x1UL << CAN_F13R1_FB6_Pos)
    -
    -

    0x00000040

    - -
    -
    - -

    ◆ CAN_F13R1_FB6

    - -
    -
    - - - - -
    #define CAN_F13R1_FB6   CAN_F13R1_FB6_Msk
    -
    -

    Filter bit 6

    - -
    -
    - -

    ◆ CAN_F13R1_FB7_Pos

    - -
    -
    - - - - -
    #define CAN_F13R1_FB7_Pos   (7U)
    -
    - -
    -
    - -

    ◆ CAN_F13R1_FB7_Msk

    - -
    -
    - - - - -
    #define CAN_F13R1_FB7_Msk   (0x1UL << CAN_F13R1_FB7_Pos)
    -
    -

    0x00000080

    - -
    -
    - -

    ◆ CAN_F13R1_FB7

    - -
    -
    - - - - -
    #define CAN_F13R1_FB7   CAN_F13R1_FB7_Msk
    -
    -

    Filter bit 7

    - -
    -
    - -

    ◆ CAN_F13R1_FB8_Pos

    - -
    -
    - - - - -
    #define CAN_F13R1_FB8_Pos   (8U)
    -
    - -
    -
    - -

    ◆ CAN_F13R1_FB8_Msk

    - -
    -
    - - - - -
    #define CAN_F13R1_FB8_Msk   (0x1UL << CAN_F13R1_FB8_Pos)
    -
    -

    0x00000100

    - -
    -
    - -

    ◆ CAN_F13R1_FB8

    - -
    -
    - - - - -
    #define CAN_F13R1_FB8   CAN_F13R1_FB8_Msk
    -
    -

    Filter bit 8

    - -
    -
    - -

    ◆ CAN_F13R1_FB9_Pos

    - -
    -
    - - - - -
    #define CAN_F13R1_FB9_Pos   (9U)
    -
    - -
    -
    - -

    ◆ CAN_F13R1_FB9_Msk

    - -
    -
    - - - - -
    #define CAN_F13R1_FB9_Msk   (0x1UL << CAN_F13R1_FB9_Pos)
    -
    -

    0x00000200

    - -
    -
    - -

    ◆ CAN_F13R1_FB9

    - -
    -
    - - - - -
    #define CAN_F13R1_FB9   CAN_F13R1_FB9_Msk
    -
    -

    Filter bit 9

    - -
    -
    - -

    ◆ CAN_F13R1_FB10_Pos

    - -
    -
    - - - - -
    #define CAN_F13R1_FB10_Pos   (10U)
    -
    - -
    -
    - -

    ◆ CAN_F13R1_FB10_Msk

    - -
    -
    - - - - -
    #define CAN_F13R1_FB10_Msk   (0x1UL << CAN_F13R1_FB10_Pos)
    -
    -

    0x00000400

    - -
    -
    - -

    ◆ CAN_F13R1_FB10

    - -
    -
    - - - - -
    #define CAN_F13R1_FB10   CAN_F13R1_FB10_Msk
    -
    -

    Filter bit 10

    - -
    -
    - -

    ◆ CAN_F13R1_FB11_Pos

    - -
    -
    - - - - -
    #define CAN_F13R1_FB11_Pos   (11U)
    -
    - -
    -
    - -

    ◆ CAN_F13R1_FB11_Msk

    - -
    -
    - - - - -
    #define CAN_F13R1_FB11_Msk   (0x1UL << CAN_F13R1_FB11_Pos)
    -
    -

    0x00000800

    - -
    -
    - -

    ◆ CAN_F13R1_FB11

    - -
    -
    - - - - -
    #define CAN_F13R1_FB11   CAN_F13R1_FB11_Msk
    -
    -

    Filter bit 11

    - -
    -
    - -

    ◆ CAN_F13R1_FB12_Pos

    - -
    -
    - - - - -
    #define CAN_F13R1_FB12_Pos   (12U)
    -
    - -
    -
    - -

    ◆ CAN_F13R1_FB12_Msk

    - -
    -
    - - - - -
    #define CAN_F13R1_FB12_Msk   (0x1UL << CAN_F13R1_FB12_Pos)
    -
    -

    0x00001000

    - -
    -
    - -

    ◆ CAN_F13R1_FB12

    - -
    -
    - - - - -
    #define CAN_F13R1_FB12   CAN_F13R1_FB12_Msk
    -
    -

    Filter bit 12

    - -
    -
    - -

    ◆ CAN_F13R1_FB13_Pos

    - -
    -
    - - - - -
    #define CAN_F13R1_FB13_Pos   (13U)
    -
    - -
    -
    - -

    ◆ CAN_F13R1_FB13_Msk

    - -
    -
    - - - - -
    #define CAN_F13R1_FB13_Msk   (0x1UL << CAN_F13R1_FB13_Pos)
    -
    -

    0x00002000

    - -
    -
    - -

    ◆ CAN_F13R1_FB13

    - -
    -
    - - - - -
    #define CAN_F13R1_FB13   CAN_F13R1_FB13_Msk
    -
    -

    Filter bit 13

    - -
    -
    - -

    ◆ CAN_F13R1_FB14_Pos

    - -
    -
    - - - - -
    #define CAN_F13R1_FB14_Pos   (14U)
    -
    - -
    -
    - -

    ◆ CAN_F13R1_FB14_Msk

    - -
    -
    - - - - -
    #define CAN_F13R1_FB14_Msk   (0x1UL << CAN_F13R1_FB14_Pos)
    -
    -

    0x00004000

    - -
    -
    - -

    ◆ CAN_F13R1_FB14

    - -
    -
    - - - - -
    #define CAN_F13R1_FB14   CAN_F13R1_FB14_Msk
    -
    -

    Filter bit 14

    - -
    -
    - -

    ◆ CAN_F13R1_FB15_Pos

    - -
    -
    - - - - -
    #define CAN_F13R1_FB15_Pos   (15U)
    -
    - -
    -
    - -

    ◆ CAN_F13R1_FB15_Msk

    - -
    -
    - - - - -
    #define CAN_F13R1_FB15_Msk   (0x1UL << CAN_F13R1_FB15_Pos)
    -
    -

    0x00008000

    - -
    -
    - -

    ◆ CAN_F13R1_FB15

    - -
    -
    - - - - -
    #define CAN_F13R1_FB15   CAN_F13R1_FB15_Msk
    -
    -

    Filter bit 15

    - -
    -
    - -

    ◆ CAN_F13R1_FB16_Pos

    - -
    -
    - - - - -
    #define CAN_F13R1_FB16_Pos   (16U)
    -
    - -
    -
    - -

    ◆ CAN_F13R1_FB16_Msk

    - -
    -
    - - - - -
    #define CAN_F13R1_FB16_Msk   (0x1UL << CAN_F13R1_FB16_Pos)
    -
    -

    0x00010000

    - -
    -
    - -

    ◆ CAN_F13R1_FB16

    - -
    -
    - - - - -
    #define CAN_F13R1_FB16   CAN_F13R1_FB16_Msk
    -
    -

    Filter bit 16

    - -
    -
    - -

    ◆ CAN_F13R1_FB17_Pos

    - -
    -
    - - - - -
    #define CAN_F13R1_FB17_Pos   (17U)
    -
    - -
    -
    - -

    ◆ CAN_F13R1_FB17_Msk

    - -
    -
    - - - - -
    #define CAN_F13R1_FB17_Msk   (0x1UL << CAN_F13R1_FB17_Pos)
    -
    -

    0x00020000

    - -
    -
    - -

    ◆ CAN_F13R1_FB17

    - -
    -
    - - - - -
    #define CAN_F13R1_FB17   CAN_F13R1_FB17_Msk
    -
    -

    Filter bit 17

    - -
    -
    - -

    ◆ CAN_F13R1_FB18_Pos

    - -
    -
    - - - - -
    #define CAN_F13R1_FB18_Pos   (18U)
    -
    - -
    -
    - -

    ◆ CAN_F13R1_FB18_Msk

    - -
    -
    - - - - -
    #define CAN_F13R1_FB18_Msk   (0x1UL << CAN_F13R1_FB18_Pos)
    -
    -

    0x00040000

    - -
    -
    - -

    ◆ CAN_F13R1_FB18

    - -
    -
    - - - - -
    #define CAN_F13R1_FB18   CAN_F13R1_FB18_Msk
    -
    -

    Filter bit 18

    - -
    -
    - -

    ◆ CAN_F13R1_FB19_Pos

    - -
    -
    - - - - -
    #define CAN_F13R1_FB19_Pos   (19U)
    -
    - -
    -
    - -

    ◆ CAN_F13R1_FB19_Msk

    - -
    -
    - - - - -
    #define CAN_F13R1_FB19_Msk   (0x1UL << CAN_F13R1_FB19_Pos)
    -
    -

    0x00080000

    - -
    -
    - -

    ◆ CAN_F13R1_FB19

    - -
    -
    - - - - -
    #define CAN_F13R1_FB19   CAN_F13R1_FB19_Msk
    -
    -

    Filter bit 19

    - -
    -
    - -

    ◆ CAN_F13R1_FB20_Pos

    - -
    -
    - - - - -
    #define CAN_F13R1_FB20_Pos   (20U)
    -
    - -
    -
    - -

    ◆ CAN_F13R1_FB20_Msk

    - -
    -
    - - - - -
    #define CAN_F13R1_FB20_Msk   (0x1UL << CAN_F13R1_FB20_Pos)
    -
    -

    0x00100000

    - -
    -
    - -

    ◆ CAN_F13R1_FB20

    - -
    -
    - - - - -
    #define CAN_F13R1_FB20   CAN_F13R1_FB20_Msk
    -
    -

    Filter bit 20

    - -
    -
    - -

    ◆ CAN_F13R1_FB21_Pos

    - -
    -
    - - - - -
    #define CAN_F13R1_FB21_Pos   (21U)
    -
    - -
    -
    - -

    ◆ CAN_F13R1_FB21_Msk

    - -
    -
    - - - - -
    #define CAN_F13R1_FB21_Msk   (0x1UL << CAN_F13R1_FB21_Pos)
    -
    -

    0x00200000

    - -
    -
    - -

    ◆ CAN_F13R1_FB21

    - -
    -
    - - - - -
    #define CAN_F13R1_FB21   CAN_F13R1_FB21_Msk
    -
    -

    Filter bit 21

    - -
    -
    - -

    ◆ CAN_F13R1_FB22_Pos

    - -
    -
    - - - - -
    #define CAN_F13R1_FB22_Pos   (22U)
    -
    - -
    -
    - -

    ◆ CAN_F13R1_FB22_Msk

    - -
    -
    - - - - -
    #define CAN_F13R1_FB22_Msk   (0x1UL << CAN_F13R1_FB22_Pos)
    -
    -

    0x00400000

    - -
    -
    - -

    ◆ CAN_F13R1_FB22

    - -
    -
    - - - - -
    #define CAN_F13R1_FB22   CAN_F13R1_FB22_Msk
    -
    -

    Filter bit 22

    - -
    -
    - -

    ◆ CAN_F13R1_FB23_Pos

    - -
    -
    - - - - -
    #define CAN_F13R1_FB23_Pos   (23U)
    -
    - -
    -
    - -

    ◆ CAN_F13R1_FB23_Msk

    - -
    -
    - - - - -
    #define CAN_F13R1_FB23_Msk   (0x1UL << CAN_F13R1_FB23_Pos)
    -
    -

    0x00800000

    - -
    -
    - -

    ◆ CAN_F13R1_FB23

    - -
    -
    - - - - -
    #define CAN_F13R1_FB23   CAN_F13R1_FB23_Msk
    -
    -

    Filter bit 23

    - -
    -
    - -

    ◆ CAN_F13R1_FB24_Pos

    - -
    -
    - - - - -
    #define CAN_F13R1_FB24_Pos   (24U)
    -
    - -
    -
    - -

    ◆ CAN_F13R1_FB24_Msk

    - -
    -
    - - - - -
    #define CAN_F13R1_FB24_Msk   (0x1UL << CAN_F13R1_FB24_Pos)
    -
    -

    0x01000000

    - -
    -
    - -

    ◆ CAN_F13R1_FB24

    - -
    -
    - - - - -
    #define CAN_F13R1_FB24   CAN_F13R1_FB24_Msk
    -
    -

    Filter bit 24

    - -
    -
    - -

    ◆ CAN_F13R1_FB25_Pos

    - -
    -
    - - - - -
    #define CAN_F13R1_FB25_Pos   (25U)
    -
    - -
    -
    - -

    ◆ CAN_F13R1_FB25_Msk

    - -
    -
    - - - - -
    #define CAN_F13R1_FB25_Msk   (0x1UL << CAN_F13R1_FB25_Pos)
    -
    -

    0x02000000

    - -
    -
    - -

    ◆ CAN_F13R1_FB25

    - -
    -
    - - - - -
    #define CAN_F13R1_FB25   CAN_F13R1_FB25_Msk
    -
    -

    Filter bit 25

    - -
    -
    - -

    ◆ CAN_F13R1_FB26_Pos

    - -
    -
    - - - - -
    #define CAN_F13R1_FB26_Pos   (26U)
    -
    - -
    -
    - -

    ◆ CAN_F13R1_FB26_Msk

    - -
    -
    - - - - -
    #define CAN_F13R1_FB26_Msk   (0x1UL << CAN_F13R1_FB26_Pos)
    -
    -

    0x04000000

    - -
    -
    - -

    ◆ CAN_F13R1_FB26

    - -
    -
    - - - - -
    #define CAN_F13R1_FB26   CAN_F13R1_FB26_Msk
    -
    -

    Filter bit 26

    - -
    -
    - -

    ◆ CAN_F13R1_FB27_Pos

    - -
    -
    - - - - -
    #define CAN_F13R1_FB27_Pos   (27U)
    -
    - -
    -
    - -

    ◆ CAN_F13R1_FB27_Msk

    - -
    -
    - - - - -
    #define CAN_F13R1_FB27_Msk   (0x1UL << CAN_F13R1_FB27_Pos)
    -
    -

    0x08000000

    - -
    -
    - -

    ◆ CAN_F13R1_FB27

    - -
    -
    - - - - -
    #define CAN_F13R1_FB27   CAN_F13R1_FB27_Msk
    -
    -

    Filter bit 27

    - -
    -
    - -

    ◆ CAN_F13R1_FB28_Pos

    - -
    -
    - - - - -
    #define CAN_F13R1_FB28_Pos   (28U)
    -
    - -
    -
    - -

    ◆ CAN_F13R1_FB28_Msk

    - -
    -
    - - - - -
    #define CAN_F13R1_FB28_Msk   (0x1UL << CAN_F13R1_FB28_Pos)
    -
    -

    0x10000000

    - -
    -
    - -

    ◆ CAN_F13R1_FB28

    - -
    -
    - - - - -
    #define CAN_F13R1_FB28   CAN_F13R1_FB28_Msk
    -
    -

    Filter bit 28

    - -
    -
    - -

    ◆ CAN_F13R1_FB29_Pos

    - -
    -
    - - - - -
    #define CAN_F13R1_FB29_Pos   (29U)
    -
    - -
    -
    - -

    ◆ CAN_F13R1_FB29_Msk

    - -
    -
    - - - - -
    #define CAN_F13R1_FB29_Msk   (0x1UL << CAN_F13R1_FB29_Pos)
    -
    -

    0x20000000

    - -
    -
    - -

    ◆ CAN_F13R1_FB29

    - -
    -
    - - - - -
    #define CAN_F13R1_FB29   CAN_F13R1_FB29_Msk
    -
    -

    Filter bit 29

    - -
    -
    - -

    ◆ CAN_F13R1_FB30_Pos

    - -
    -
    - - - - -
    #define CAN_F13R1_FB30_Pos   (30U)
    -
    - -
    -
    - -

    ◆ CAN_F13R1_FB30_Msk

    - -
    -
    - - - - -
    #define CAN_F13R1_FB30_Msk   (0x1UL << CAN_F13R1_FB30_Pos)
    -
    -

    0x40000000

    - -
    -
    - -

    ◆ CAN_F13R1_FB30

    - -
    -
    - - - - -
    #define CAN_F13R1_FB30   CAN_F13R1_FB30_Msk
    -
    -

    Filter bit 30

    - -
    -
    - -

    ◆ CAN_F13R1_FB31_Pos

    - -
    -
    - - - - -
    #define CAN_F13R1_FB31_Pos   (31U)
    -
    - -
    -
    - -

    ◆ CAN_F13R1_FB31_Msk

    - -
    -
    - - - - -
    #define CAN_F13R1_FB31_Msk   (0x1UL << CAN_F13R1_FB31_Pos)
    -
    -

    0x80000000

    - -
    -
    - -

    ◆ CAN_F13R1_FB31

    - -
    -
    - - - - -
    #define CAN_F13R1_FB31   CAN_F13R1_FB31_Msk
    -
    -

    Filter bit 31

    - -
    -
    - -

    ◆ CAN_F0R2_FB0_Pos

    - -
    -
    - - - - -
    #define CAN_F0R2_FB0_Pos   (0U)
    -
    - -
    -
    - -

    ◆ CAN_F0R2_FB0_Msk

    - -
    -
    - - - - -
    #define CAN_F0R2_FB0_Msk   (0x1UL << CAN_F0R2_FB0_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ CAN_F0R2_FB0

    - -
    -
    - - - - -
    #define CAN_F0R2_FB0   CAN_F0R2_FB0_Msk
    -
    -

    Filter bit 0

    - -
    -
    - -

    ◆ CAN_F0R2_FB1_Pos

    - -
    -
    - - - - -
    #define CAN_F0R2_FB1_Pos   (1U)
    -
    - -
    -
    - -

    ◆ CAN_F0R2_FB1_Msk

    - -
    -
    - - - - -
    #define CAN_F0R2_FB1_Msk   (0x1UL << CAN_F0R2_FB1_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ CAN_F0R2_FB1

    - -
    -
    - - - - -
    #define CAN_F0R2_FB1   CAN_F0R2_FB1_Msk
    -
    -

    Filter bit 1

    - -
    -
    - -

    ◆ CAN_F0R2_FB2_Pos

    - -
    -
    - - - - -
    #define CAN_F0R2_FB2_Pos   (2U)
    -
    - -
    -
    - -

    ◆ CAN_F0R2_FB2_Msk

    - -
    -
    - - - - -
    #define CAN_F0R2_FB2_Msk   (0x1UL << CAN_F0R2_FB2_Pos)
    -
    -

    0x00000004

    - -
    -
    - -

    ◆ CAN_F0R2_FB2

    - -
    -
    - - - - -
    #define CAN_F0R2_FB2   CAN_F0R2_FB2_Msk
    -
    -

    Filter bit 2

    - -
    -
    - -

    ◆ CAN_F0R2_FB3_Pos

    - -
    -
    - - - - -
    #define CAN_F0R2_FB3_Pos   (3U)
    -
    - -
    -
    - -

    ◆ CAN_F0R2_FB3_Msk

    - -
    -
    - - - - -
    #define CAN_F0R2_FB3_Msk   (0x1UL << CAN_F0R2_FB3_Pos)
    -
    -

    0x00000008

    - -
    -
    - -

    ◆ CAN_F0R2_FB3

    - -
    -
    - - - - -
    #define CAN_F0R2_FB3   CAN_F0R2_FB3_Msk
    -
    -

    Filter bit 3

    - -
    -
    - -

    ◆ CAN_F0R2_FB4_Pos

    - -
    -
    - - - - -
    #define CAN_F0R2_FB4_Pos   (4U)
    -
    - -
    -
    - -

    ◆ CAN_F0R2_FB4_Msk

    - -
    -
    - - - - -
    #define CAN_F0R2_FB4_Msk   (0x1UL << CAN_F0R2_FB4_Pos)
    -
    -

    0x00000010

    - -
    -
    - -

    ◆ CAN_F0R2_FB4

    - -
    -
    - - - - -
    #define CAN_F0R2_FB4   CAN_F0R2_FB4_Msk
    -
    -

    Filter bit 4

    - -
    -
    - -

    ◆ CAN_F0R2_FB5_Pos

    - -
    -
    - - - - -
    #define CAN_F0R2_FB5_Pos   (5U)
    -
    - -
    -
    - -

    ◆ CAN_F0R2_FB5_Msk

    - -
    -
    - - - - -
    #define CAN_F0R2_FB5_Msk   (0x1UL << CAN_F0R2_FB5_Pos)
    -
    -

    0x00000020

    - -
    -
    - -

    ◆ CAN_F0R2_FB5

    - -
    -
    - - - - -
    #define CAN_F0R2_FB5   CAN_F0R2_FB5_Msk
    -
    -

    Filter bit 5

    - -
    -
    - -

    ◆ CAN_F0R2_FB6_Pos

    - -
    -
    - - - - -
    #define CAN_F0R2_FB6_Pos   (6U)
    -
    - -
    -
    - -

    ◆ CAN_F0R2_FB6_Msk

    - -
    -
    - - - - -
    #define CAN_F0R2_FB6_Msk   (0x1UL << CAN_F0R2_FB6_Pos)
    -
    -

    0x00000040

    - -
    -
    - -

    ◆ CAN_F0R2_FB6

    - -
    -
    - - - - -
    #define CAN_F0R2_FB6   CAN_F0R2_FB6_Msk
    -
    -

    Filter bit 6

    - -
    -
    - -

    ◆ CAN_F0R2_FB7_Pos

    - -
    -
    - - - - -
    #define CAN_F0R2_FB7_Pos   (7U)
    -
    - -
    -
    - -

    ◆ CAN_F0R2_FB7_Msk

    - -
    -
    - - - - -
    #define CAN_F0R2_FB7_Msk   (0x1UL << CAN_F0R2_FB7_Pos)
    -
    -

    0x00000080

    - -
    -
    - -

    ◆ CAN_F0R2_FB7

    - -
    -
    - - - - -
    #define CAN_F0R2_FB7   CAN_F0R2_FB7_Msk
    -
    -

    Filter bit 7

    - -
    -
    - -

    ◆ CAN_F0R2_FB8_Pos

    - -
    -
    - - - - -
    #define CAN_F0R2_FB8_Pos   (8U)
    -
    - -
    -
    - -

    ◆ CAN_F0R2_FB8_Msk

    - -
    -
    - - - - -
    #define CAN_F0R2_FB8_Msk   (0x1UL << CAN_F0R2_FB8_Pos)
    -
    -

    0x00000100

    - -
    -
    - -

    ◆ CAN_F0R2_FB8

    - -
    -
    - - - - -
    #define CAN_F0R2_FB8   CAN_F0R2_FB8_Msk
    -
    -

    Filter bit 8

    - -
    -
    - -

    ◆ CAN_F0R2_FB9_Pos

    - -
    -
    - - - - -
    #define CAN_F0R2_FB9_Pos   (9U)
    -
    - -
    -
    - -

    ◆ CAN_F0R2_FB9_Msk

    - -
    -
    - - - - -
    #define CAN_F0R2_FB9_Msk   (0x1UL << CAN_F0R2_FB9_Pos)
    -
    -

    0x00000200

    - -
    -
    - -

    ◆ CAN_F0R2_FB9

    - -
    -
    - - - - -
    #define CAN_F0R2_FB9   CAN_F0R2_FB9_Msk
    -
    -

    Filter bit 9

    - -
    -
    - -

    ◆ CAN_F0R2_FB10_Pos

    - -
    -
    - - - - -
    #define CAN_F0R2_FB10_Pos   (10U)
    -
    - -
    -
    - -

    ◆ CAN_F0R2_FB10_Msk

    - -
    -
    - - - - -
    #define CAN_F0R2_FB10_Msk   (0x1UL << CAN_F0R2_FB10_Pos)
    -
    -

    0x00000400

    - -
    -
    - -

    ◆ CAN_F0R2_FB10

    - -
    -
    - - - - -
    #define CAN_F0R2_FB10   CAN_F0R2_FB10_Msk
    -
    -

    Filter bit 10

    - -
    -
    - -

    ◆ CAN_F0R2_FB11_Pos

    - -
    -
    - - - - -
    #define CAN_F0R2_FB11_Pos   (11U)
    -
    - -
    -
    - -

    ◆ CAN_F0R2_FB11_Msk

    - -
    -
    - - - - -
    #define CAN_F0R2_FB11_Msk   (0x1UL << CAN_F0R2_FB11_Pos)
    -
    -

    0x00000800

    - -
    -
    - -

    ◆ CAN_F0R2_FB11

    - -
    -
    - - - - -
    #define CAN_F0R2_FB11   CAN_F0R2_FB11_Msk
    -
    -

    Filter bit 11

    - -
    -
    - -

    ◆ CAN_F0R2_FB12_Pos

    - -
    -
    - - - - -
    #define CAN_F0R2_FB12_Pos   (12U)
    -
    - -
    -
    - -

    ◆ CAN_F0R2_FB12_Msk

    - -
    -
    - - - - -
    #define CAN_F0R2_FB12_Msk   (0x1UL << CAN_F0R2_FB12_Pos)
    -
    -

    0x00001000

    - -
    -
    - -

    ◆ CAN_F0R2_FB12

    - -
    -
    - - - - -
    #define CAN_F0R2_FB12   CAN_F0R2_FB12_Msk
    -
    -

    Filter bit 12

    - -
    -
    - -

    ◆ CAN_F0R2_FB13_Pos

    - -
    -
    - - - - -
    #define CAN_F0R2_FB13_Pos   (13U)
    -
    - -
    -
    - -

    ◆ CAN_F0R2_FB13_Msk

    - -
    -
    - - - - -
    #define CAN_F0R2_FB13_Msk   (0x1UL << CAN_F0R2_FB13_Pos)
    -
    -

    0x00002000

    - -
    -
    - -

    ◆ CAN_F0R2_FB13

    - -
    -
    - - - - -
    #define CAN_F0R2_FB13   CAN_F0R2_FB13_Msk
    -
    -

    Filter bit 13

    - -
    -
    - -

    ◆ CAN_F0R2_FB14_Pos

    - -
    -
    - - - - -
    #define CAN_F0R2_FB14_Pos   (14U)
    -
    - -
    -
    - -

    ◆ CAN_F0R2_FB14_Msk

    - -
    -
    - - - - -
    #define CAN_F0R2_FB14_Msk   (0x1UL << CAN_F0R2_FB14_Pos)
    -
    -

    0x00004000

    - -
    -
    - -

    ◆ CAN_F0R2_FB14

    - -
    -
    - - - - -
    #define CAN_F0R2_FB14   CAN_F0R2_FB14_Msk
    -
    -

    Filter bit 14

    - -
    -
    - -

    ◆ CAN_F0R2_FB15_Pos

    - -
    -
    - - - - -
    #define CAN_F0R2_FB15_Pos   (15U)
    -
    - -
    -
    - -

    ◆ CAN_F0R2_FB15_Msk

    - -
    -
    - - - - -
    #define CAN_F0R2_FB15_Msk   (0x1UL << CAN_F0R2_FB15_Pos)
    -
    -

    0x00008000

    - -
    -
    - -

    ◆ CAN_F0R2_FB15

    - -
    -
    - - - - -
    #define CAN_F0R2_FB15   CAN_F0R2_FB15_Msk
    -
    -

    Filter bit 15

    - -
    -
    - -

    ◆ CAN_F0R2_FB16_Pos

    - -
    -
    - - - - -
    #define CAN_F0R2_FB16_Pos   (16U)
    -
    - -
    -
    - -

    ◆ CAN_F0R2_FB16_Msk

    - -
    -
    - - - - -
    #define CAN_F0R2_FB16_Msk   (0x1UL << CAN_F0R2_FB16_Pos)
    -
    -

    0x00010000

    - -
    -
    - -

    ◆ CAN_F0R2_FB16

    - -
    -
    - - - - -
    #define CAN_F0R2_FB16   CAN_F0R2_FB16_Msk
    -
    -

    Filter bit 16

    - -
    -
    - -

    ◆ CAN_F0R2_FB17_Pos

    - -
    -
    - - - - -
    #define CAN_F0R2_FB17_Pos   (17U)
    -
    - -
    -
    - -

    ◆ CAN_F0R2_FB17_Msk

    - -
    -
    - - - - -
    #define CAN_F0R2_FB17_Msk   (0x1UL << CAN_F0R2_FB17_Pos)
    -
    -

    0x00020000

    - -
    -
    - -

    ◆ CAN_F0R2_FB17

    - -
    -
    - - - - -
    #define CAN_F0R2_FB17   CAN_F0R2_FB17_Msk
    -
    -

    Filter bit 17

    - -
    -
    - -

    ◆ CAN_F0R2_FB18_Pos

    - -
    -
    - - - - -
    #define CAN_F0R2_FB18_Pos   (18U)
    -
    - -
    -
    - -

    ◆ CAN_F0R2_FB18_Msk

    - -
    -
    - - - - -
    #define CAN_F0R2_FB18_Msk   (0x1UL << CAN_F0R2_FB18_Pos)
    -
    -

    0x00040000

    - -
    -
    - -

    ◆ CAN_F0R2_FB18

    - -
    -
    - - - - -
    #define CAN_F0R2_FB18   CAN_F0R2_FB18_Msk
    -
    -

    Filter bit 18

    - -
    -
    - -

    ◆ CAN_F0R2_FB19_Pos

    - -
    -
    - - - - -
    #define CAN_F0R2_FB19_Pos   (19U)
    -
    - -
    -
    - -

    ◆ CAN_F0R2_FB19_Msk

    - -
    -
    - - - - -
    #define CAN_F0R2_FB19_Msk   (0x1UL << CAN_F0R2_FB19_Pos)
    -
    -

    0x00080000

    - -
    -
    - -

    ◆ CAN_F0R2_FB19

    - -
    -
    - - - - -
    #define CAN_F0R2_FB19   CAN_F0R2_FB19_Msk
    -
    -

    Filter bit 19

    - -
    -
    - -

    ◆ CAN_F0R2_FB20_Pos

    - -
    -
    - - - - -
    #define CAN_F0R2_FB20_Pos   (20U)
    -
    - -
    -
    - -

    ◆ CAN_F0R2_FB20_Msk

    - -
    -
    - - - - -
    #define CAN_F0R2_FB20_Msk   (0x1UL << CAN_F0R2_FB20_Pos)
    -
    -

    0x00100000

    - -
    -
    - -

    ◆ CAN_F0R2_FB20

    - -
    -
    - - - - -
    #define CAN_F0R2_FB20   CAN_F0R2_FB20_Msk
    -
    -

    Filter bit 20

    - -
    -
    - -

    ◆ CAN_F0R2_FB21_Pos

    - -
    -
    - - - - -
    #define CAN_F0R2_FB21_Pos   (21U)
    -
    - -
    -
    - -

    ◆ CAN_F0R2_FB21_Msk

    - -
    -
    - - - - -
    #define CAN_F0R2_FB21_Msk   (0x1UL << CAN_F0R2_FB21_Pos)
    -
    -

    0x00200000

    - -
    -
    - -

    ◆ CAN_F0R2_FB21

    - -
    -
    - - - - -
    #define CAN_F0R2_FB21   CAN_F0R2_FB21_Msk
    -
    -

    Filter bit 21

    - -
    -
    - -

    ◆ CAN_F0R2_FB22_Pos

    - -
    -
    - - - - -
    #define CAN_F0R2_FB22_Pos   (22U)
    -
    - -
    -
    - -

    ◆ CAN_F0R2_FB22_Msk

    - -
    -
    - - - - -
    #define CAN_F0R2_FB22_Msk   (0x1UL << CAN_F0R2_FB22_Pos)
    -
    -

    0x00400000

    - -
    -
    - -

    ◆ CAN_F0R2_FB22

    - -
    -
    - - - - -
    #define CAN_F0R2_FB22   CAN_F0R2_FB22_Msk
    -
    -

    Filter bit 22

    - -
    -
    - -

    ◆ CAN_F0R2_FB23_Pos

    - -
    -
    - - - - -
    #define CAN_F0R2_FB23_Pos   (23U)
    -
    - -
    -
    - -

    ◆ CAN_F0R2_FB23_Msk

    - -
    -
    - - - - -
    #define CAN_F0R2_FB23_Msk   (0x1UL << CAN_F0R2_FB23_Pos)
    -
    -

    0x00800000

    - -
    -
    - -

    ◆ CAN_F0R2_FB23

    - -
    -
    - - - - -
    #define CAN_F0R2_FB23   CAN_F0R2_FB23_Msk
    -
    -

    Filter bit 23

    - -
    -
    - -

    ◆ CAN_F0R2_FB24_Pos

    - -
    -
    - - - - -
    #define CAN_F0R2_FB24_Pos   (24U)
    -
    - -
    -
    - -

    ◆ CAN_F0R2_FB24_Msk

    - -
    -
    - - - - -
    #define CAN_F0R2_FB24_Msk   (0x1UL << CAN_F0R2_FB24_Pos)
    -
    -

    0x01000000

    - -
    -
    - -

    ◆ CAN_F0R2_FB24

    - -
    -
    - - - - -
    #define CAN_F0R2_FB24   CAN_F0R2_FB24_Msk
    -
    -

    Filter bit 24

    - -
    -
    - -

    ◆ CAN_F0R2_FB25_Pos

    - -
    -
    - - - - -
    #define CAN_F0R2_FB25_Pos   (25U)
    -
    - -
    -
    - -

    ◆ CAN_F0R2_FB25_Msk

    - -
    -
    - - - - -
    #define CAN_F0R2_FB25_Msk   (0x1UL << CAN_F0R2_FB25_Pos)
    -
    -

    0x02000000

    - -
    -
    - -

    ◆ CAN_F0R2_FB25

    - -
    -
    - - - - -
    #define CAN_F0R2_FB25   CAN_F0R2_FB25_Msk
    -
    -

    Filter bit 25

    - -
    -
    - -

    ◆ CAN_F0R2_FB26_Pos

    - -
    -
    - - - - -
    #define CAN_F0R2_FB26_Pos   (26U)
    -
    - -
    -
    - -

    ◆ CAN_F0R2_FB26_Msk

    - -
    -
    - - - - -
    #define CAN_F0R2_FB26_Msk   (0x1UL << CAN_F0R2_FB26_Pos)
    -
    -

    0x04000000

    - -
    -
    - -

    ◆ CAN_F0R2_FB26

    - -
    -
    - - - - -
    #define CAN_F0R2_FB26   CAN_F0R2_FB26_Msk
    -
    -

    Filter bit 26

    - -
    -
    - -

    ◆ CAN_F0R2_FB27_Pos

    - -
    -
    - - - - -
    #define CAN_F0R2_FB27_Pos   (27U)
    -
    - -
    -
    - -

    ◆ CAN_F0R2_FB27_Msk

    - -
    -
    - - - - -
    #define CAN_F0R2_FB27_Msk   (0x1UL << CAN_F0R2_FB27_Pos)
    -
    -

    0x08000000

    - -
    -
    - -

    ◆ CAN_F0R2_FB27

    - -
    -
    - - - - -
    #define CAN_F0R2_FB27   CAN_F0R2_FB27_Msk
    -
    -

    Filter bit 27

    - -
    -
    - -

    ◆ CAN_F0R2_FB28_Pos

    - -
    -
    - - - - -
    #define CAN_F0R2_FB28_Pos   (28U)
    -
    - -
    -
    - -

    ◆ CAN_F0R2_FB28_Msk

    - -
    -
    - - - - -
    #define CAN_F0R2_FB28_Msk   (0x1UL << CAN_F0R2_FB28_Pos)
    -
    -

    0x10000000

    - -
    -
    - -

    ◆ CAN_F0R2_FB28

    - -
    -
    - - - - -
    #define CAN_F0R2_FB28   CAN_F0R2_FB28_Msk
    -
    -

    Filter bit 28

    - -
    -
    - -

    ◆ CAN_F0R2_FB29_Pos

    - -
    -
    - - - - -
    #define CAN_F0R2_FB29_Pos   (29U)
    -
    - -
    -
    - -

    ◆ CAN_F0R2_FB29_Msk

    - -
    -
    - - - - -
    #define CAN_F0R2_FB29_Msk   (0x1UL << CAN_F0R2_FB29_Pos)
    -
    -

    0x20000000

    - -
    -
    - -

    ◆ CAN_F0R2_FB29

    - -
    -
    - - - - -
    #define CAN_F0R2_FB29   CAN_F0R2_FB29_Msk
    -
    -

    Filter bit 29

    - -
    -
    - -

    ◆ CAN_F0R2_FB30_Pos

    - -
    -
    - - - - -
    #define CAN_F0R2_FB30_Pos   (30U)
    -
    - -
    -
    - -

    ◆ CAN_F0R2_FB30_Msk

    - -
    -
    - - - - -
    #define CAN_F0R2_FB30_Msk   (0x1UL << CAN_F0R2_FB30_Pos)
    -
    -

    0x40000000

    - -
    -
    - -

    ◆ CAN_F0R2_FB30

    - -
    -
    - - - - -
    #define CAN_F0R2_FB30   CAN_F0R2_FB30_Msk
    -
    -

    Filter bit 30

    - -
    -
    - -

    ◆ CAN_F0R2_FB31_Pos

    - -
    -
    - - - - -
    #define CAN_F0R2_FB31_Pos   (31U)
    -
    - -
    -
    - -

    ◆ CAN_F0R2_FB31_Msk

    - -
    -
    - - - - -
    #define CAN_F0R2_FB31_Msk   (0x1UL << CAN_F0R2_FB31_Pos)
    -
    -

    0x80000000

    - -
    -
    - -

    ◆ CAN_F0R2_FB31

    - -
    -
    - - - - -
    #define CAN_F0R2_FB31   CAN_F0R2_FB31_Msk
    -
    -

    Filter bit 31

    - -
    -
    - -

    ◆ CAN_F1R2_FB0_Pos

    - -
    -
    - - - - -
    #define CAN_F1R2_FB0_Pos   (0U)
    -
    - -
    -
    - -

    ◆ CAN_F1R2_FB0_Msk

    - -
    -
    - - - - -
    #define CAN_F1R2_FB0_Msk   (0x1UL << CAN_F1R2_FB0_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ CAN_F1R2_FB0

    - -
    -
    - - - - -
    #define CAN_F1R2_FB0   CAN_F1R2_FB0_Msk
    -
    -

    Filter bit 0

    - -
    -
    - -

    ◆ CAN_F1R2_FB1_Pos

    - -
    -
    - - - - -
    #define CAN_F1R2_FB1_Pos   (1U)
    -
    - -
    -
    - -

    ◆ CAN_F1R2_FB1_Msk

    - -
    -
    - - - - -
    #define CAN_F1R2_FB1_Msk   (0x1UL << CAN_F1R2_FB1_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ CAN_F1R2_FB1

    - -
    -
    - - - - -
    #define CAN_F1R2_FB1   CAN_F1R2_FB1_Msk
    -
    -

    Filter bit 1

    - -
    -
    - -

    ◆ CAN_F1R2_FB2_Pos

    - -
    -
    - - - - -
    #define CAN_F1R2_FB2_Pos   (2U)
    -
    - -
    -
    - -

    ◆ CAN_F1R2_FB2_Msk

    - -
    -
    - - - - -
    #define CAN_F1R2_FB2_Msk   (0x1UL << CAN_F1R2_FB2_Pos)
    -
    -

    0x00000004

    - -
    -
    - -

    ◆ CAN_F1R2_FB2

    - -
    -
    - - - - -
    #define CAN_F1R2_FB2   CAN_F1R2_FB2_Msk
    -
    -

    Filter bit 2

    - -
    -
    - -

    ◆ CAN_F1R2_FB3_Pos

    - -
    -
    - - - - -
    #define CAN_F1R2_FB3_Pos   (3U)
    -
    - -
    -
    - -

    ◆ CAN_F1R2_FB3_Msk

    - -
    -
    - - - - -
    #define CAN_F1R2_FB3_Msk   (0x1UL << CAN_F1R2_FB3_Pos)
    -
    -

    0x00000008

    - -
    -
    - -

    ◆ CAN_F1R2_FB3

    - -
    -
    - - - - -
    #define CAN_F1R2_FB3   CAN_F1R2_FB3_Msk
    -
    -

    Filter bit 3

    - -
    -
    - -

    ◆ CAN_F1R2_FB4_Pos

    - -
    -
    - - - - -
    #define CAN_F1R2_FB4_Pos   (4U)
    -
    - -
    -
    - -

    ◆ CAN_F1R2_FB4_Msk

    - -
    -
    - - - - -
    #define CAN_F1R2_FB4_Msk   (0x1UL << CAN_F1R2_FB4_Pos)
    -
    -

    0x00000010

    - -
    -
    - -

    ◆ CAN_F1R2_FB4

    - -
    -
    - - - - -
    #define CAN_F1R2_FB4   CAN_F1R2_FB4_Msk
    -
    -

    Filter bit 4

    - -
    -
    - -

    ◆ CAN_F1R2_FB5_Pos

    - -
    -
    - - - - -
    #define CAN_F1R2_FB5_Pos   (5U)
    -
    - -
    -
    - -

    ◆ CAN_F1R2_FB5_Msk

    - -
    -
    - - - - -
    #define CAN_F1R2_FB5_Msk   (0x1UL << CAN_F1R2_FB5_Pos)
    -
    -

    0x00000020

    - -
    -
    - -

    ◆ CAN_F1R2_FB5

    - -
    -
    - - - - -
    #define CAN_F1R2_FB5   CAN_F1R2_FB5_Msk
    -
    -

    Filter bit 5

    - -
    -
    - -

    ◆ CAN_F1R2_FB6_Pos

    - -
    -
    - - - - -
    #define CAN_F1R2_FB6_Pos   (6U)
    -
    - -
    -
    - -

    ◆ CAN_F1R2_FB6_Msk

    - -
    -
    - - - - -
    #define CAN_F1R2_FB6_Msk   (0x1UL << CAN_F1R2_FB6_Pos)
    -
    -

    0x00000040

    - -
    -
    - -

    ◆ CAN_F1R2_FB6

    - -
    -
    - - - - -
    #define CAN_F1R2_FB6   CAN_F1R2_FB6_Msk
    -
    -

    Filter bit 6

    - -
    -
    - -

    ◆ CAN_F1R2_FB7_Pos

    - -
    -
    - - - - -
    #define CAN_F1R2_FB7_Pos   (7U)
    -
    - -
    -
    - -

    ◆ CAN_F1R2_FB7_Msk

    - -
    -
    - - - - -
    #define CAN_F1R2_FB7_Msk   (0x1UL << CAN_F1R2_FB7_Pos)
    -
    -

    0x00000080

    - -
    -
    - -

    ◆ CAN_F1R2_FB7

    - -
    -
    - - - - -
    #define CAN_F1R2_FB7   CAN_F1R2_FB7_Msk
    -
    -

    Filter bit 7

    - -
    -
    - -

    ◆ CAN_F1R2_FB8_Pos

    - -
    -
    - - - - -
    #define CAN_F1R2_FB8_Pos   (8U)
    -
    - -
    -
    - -

    ◆ CAN_F1R2_FB8_Msk

    - -
    -
    - - - - -
    #define CAN_F1R2_FB8_Msk   (0x1UL << CAN_F1R2_FB8_Pos)
    -
    -

    0x00000100

    - -
    -
    - -

    ◆ CAN_F1R2_FB8

    - -
    -
    - - - - -
    #define CAN_F1R2_FB8   CAN_F1R2_FB8_Msk
    -
    -

    Filter bit 8

    - -
    -
    - -

    ◆ CAN_F1R2_FB9_Pos

    - -
    -
    - - - - -
    #define CAN_F1R2_FB9_Pos   (9U)
    -
    - -
    -
    - -

    ◆ CAN_F1R2_FB9_Msk

    - -
    -
    - - - - -
    #define CAN_F1R2_FB9_Msk   (0x1UL << CAN_F1R2_FB9_Pos)
    -
    -

    0x00000200

    - -
    -
    - -

    ◆ CAN_F1R2_FB9

    - -
    -
    - - - - -
    #define CAN_F1R2_FB9   CAN_F1R2_FB9_Msk
    -
    -

    Filter bit 9

    - -
    -
    - -

    ◆ CAN_F1R2_FB10_Pos

    - -
    -
    - - - - -
    #define CAN_F1R2_FB10_Pos   (10U)
    -
    - -
    -
    - -

    ◆ CAN_F1R2_FB10_Msk

    - -
    -
    - - - - -
    #define CAN_F1R2_FB10_Msk   (0x1UL << CAN_F1R2_FB10_Pos)
    -
    -

    0x00000400

    - -
    -
    - -

    ◆ CAN_F1R2_FB10

    - -
    -
    - - - - -
    #define CAN_F1R2_FB10   CAN_F1R2_FB10_Msk
    -
    -

    Filter bit 10

    - -
    -
    - -

    ◆ CAN_F1R2_FB11_Pos

    - -
    -
    - - - - -
    #define CAN_F1R2_FB11_Pos   (11U)
    -
    - -
    -
    - -

    ◆ CAN_F1R2_FB11_Msk

    - -
    -
    - - - - -
    #define CAN_F1R2_FB11_Msk   (0x1UL << CAN_F1R2_FB11_Pos)
    -
    -

    0x00000800

    - -
    -
    - -

    ◆ CAN_F1R2_FB11

    - -
    -
    - - - - -
    #define CAN_F1R2_FB11   CAN_F1R2_FB11_Msk
    -
    -

    Filter bit 11

    - -
    -
    - -

    ◆ CAN_F1R2_FB12_Pos

    - -
    -
    - - - - -
    #define CAN_F1R2_FB12_Pos   (12U)
    -
    - -
    -
    - -

    ◆ CAN_F1R2_FB12_Msk

    - -
    -
    - - - - -
    #define CAN_F1R2_FB12_Msk   (0x1UL << CAN_F1R2_FB12_Pos)
    -
    -

    0x00001000

    - -
    -
    - -

    ◆ CAN_F1R2_FB12

    - -
    -
    - - - - -
    #define CAN_F1R2_FB12   CAN_F1R2_FB12_Msk
    -
    -

    Filter bit 12

    - -
    -
    - -

    ◆ CAN_F1R2_FB13_Pos

    - -
    -
    - - - - -
    #define CAN_F1R2_FB13_Pos   (13U)
    -
    - -
    -
    - -

    ◆ CAN_F1R2_FB13_Msk

    - -
    -
    - - - - -
    #define CAN_F1R2_FB13_Msk   (0x1UL << CAN_F1R2_FB13_Pos)
    -
    -

    0x00002000

    - -
    -
    - -

    ◆ CAN_F1R2_FB13

    - -
    -
    - - - - -
    #define CAN_F1R2_FB13   CAN_F1R2_FB13_Msk
    -
    -

    Filter bit 13

    - -
    -
    - -

    ◆ CAN_F1R2_FB14_Pos

    - -
    -
    - - - - -
    #define CAN_F1R2_FB14_Pos   (14U)
    -
    - -
    -
    - -

    ◆ CAN_F1R2_FB14_Msk

    - -
    -
    - - - - -
    #define CAN_F1R2_FB14_Msk   (0x1UL << CAN_F1R2_FB14_Pos)
    -
    -

    0x00004000

    - -
    -
    - -

    ◆ CAN_F1R2_FB14

    - -
    -
    - - - - -
    #define CAN_F1R2_FB14   CAN_F1R2_FB14_Msk
    -
    -

    Filter bit 14

    - -
    -
    - -

    ◆ CAN_F1R2_FB15_Pos

    - -
    -
    - - - - -
    #define CAN_F1R2_FB15_Pos   (15U)
    -
    - -
    -
    - -

    ◆ CAN_F1R2_FB15_Msk

    - -
    -
    - - - - -
    #define CAN_F1R2_FB15_Msk   (0x1UL << CAN_F1R2_FB15_Pos)
    -
    -

    0x00008000

    - -
    -
    - -

    ◆ CAN_F1R2_FB15

    - -
    -
    - - - - -
    #define CAN_F1R2_FB15   CAN_F1R2_FB15_Msk
    -
    -

    Filter bit 15

    - -
    -
    - -

    ◆ CAN_F1R2_FB16_Pos

    - -
    -
    - - - - -
    #define CAN_F1R2_FB16_Pos   (16U)
    -
    - -
    -
    - -

    ◆ CAN_F1R2_FB16_Msk

    - -
    -
    - - - - -
    #define CAN_F1R2_FB16_Msk   (0x1UL << CAN_F1R2_FB16_Pos)
    -
    -

    0x00010000

    - -
    -
    - -

    ◆ CAN_F1R2_FB16

    - -
    -
    - - - - -
    #define CAN_F1R2_FB16   CAN_F1R2_FB16_Msk
    -
    -

    Filter bit 16

    - -
    -
    - -

    ◆ CAN_F1R2_FB17_Pos

    - -
    -
    - - - - -
    #define CAN_F1R2_FB17_Pos   (17U)
    -
    - -
    -
    - -

    ◆ CAN_F1R2_FB17_Msk

    - -
    -
    - - - - -
    #define CAN_F1R2_FB17_Msk   (0x1UL << CAN_F1R2_FB17_Pos)
    -
    -

    0x00020000

    - -
    -
    - -

    ◆ CAN_F1R2_FB17

    - -
    -
    - - - - -
    #define CAN_F1R2_FB17   CAN_F1R2_FB17_Msk
    -
    -

    Filter bit 17

    - -
    -
    - -

    ◆ CAN_F1R2_FB18_Pos

    - -
    -
    - - - - -
    #define CAN_F1R2_FB18_Pos   (18U)
    -
    - -
    -
    - -

    ◆ CAN_F1R2_FB18_Msk

    - -
    -
    - - - - -
    #define CAN_F1R2_FB18_Msk   (0x1UL << CAN_F1R2_FB18_Pos)
    -
    -

    0x00040000

    - -
    -
    - -

    ◆ CAN_F1R2_FB18

    - -
    -
    - - - - -
    #define CAN_F1R2_FB18   CAN_F1R2_FB18_Msk
    -
    -

    Filter bit 18

    - -
    -
    - -

    ◆ CAN_F1R2_FB19_Pos

    - -
    -
    - - - - -
    #define CAN_F1R2_FB19_Pos   (19U)
    -
    - -
    -
    - -

    ◆ CAN_F1R2_FB19_Msk

    - -
    -
    - - - - -
    #define CAN_F1R2_FB19_Msk   (0x1UL << CAN_F1R2_FB19_Pos)
    -
    -

    0x00080000

    - -
    -
    - -

    ◆ CAN_F1R2_FB19

    - -
    -
    - - - - -
    #define CAN_F1R2_FB19   CAN_F1R2_FB19_Msk
    -
    -

    Filter bit 19

    - -
    -
    - -

    ◆ CAN_F1R2_FB20_Pos

    - -
    -
    - - - - -
    #define CAN_F1R2_FB20_Pos   (20U)
    -
    - -
    -
    - -

    ◆ CAN_F1R2_FB20_Msk

    - -
    -
    - - - - -
    #define CAN_F1R2_FB20_Msk   (0x1UL << CAN_F1R2_FB20_Pos)
    -
    -

    0x00100000

    - -
    -
    - -

    ◆ CAN_F1R2_FB20

    - -
    -
    - - - - -
    #define CAN_F1R2_FB20   CAN_F1R2_FB20_Msk
    -
    -

    Filter bit 20

    - -
    -
    - -

    ◆ CAN_F1R2_FB21_Pos

    - -
    -
    - - - - -
    #define CAN_F1R2_FB21_Pos   (21U)
    -
    - -
    -
    - -

    ◆ CAN_F1R2_FB21_Msk

    - -
    -
    - - - - -
    #define CAN_F1R2_FB21_Msk   (0x1UL << CAN_F1R2_FB21_Pos)
    -
    -

    0x00200000

    - -
    -
    - -

    ◆ CAN_F1R2_FB21

    - -
    -
    - - - - -
    #define CAN_F1R2_FB21   CAN_F1R2_FB21_Msk
    -
    -

    Filter bit 21

    - -
    -
    - -

    ◆ CAN_F1R2_FB22_Pos

    - -
    -
    - - - - -
    #define CAN_F1R2_FB22_Pos   (22U)
    -
    - -
    -
    - -

    ◆ CAN_F1R2_FB22_Msk

    - -
    -
    - - - - -
    #define CAN_F1R2_FB22_Msk   (0x1UL << CAN_F1R2_FB22_Pos)
    -
    -

    0x00400000

    - -
    -
    - -

    ◆ CAN_F1R2_FB22

    - -
    -
    - - - - -
    #define CAN_F1R2_FB22   CAN_F1R2_FB22_Msk
    -
    -

    Filter bit 22

    - -
    -
    - -

    ◆ CAN_F1R2_FB23_Pos

    - -
    -
    - - - - -
    #define CAN_F1R2_FB23_Pos   (23U)
    -
    - -
    -
    - -

    ◆ CAN_F1R2_FB23_Msk

    - -
    -
    - - - - -
    #define CAN_F1R2_FB23_Msk   (0x1UL << CAN_F1R2_FB23_Pos)
    -
    -

    0x00800000

    - -
    -
    - -

    ◆ CAN_F1R2_FB23

    - -
    -
    - - - - -
    #define CAN_F1R2_FB23   CAN_F1R2_FB23_Msk
    -
    -

    Filter bit 23

    - -
    -
    - -

    ◆ CAN_F1R2_FB24_Pos

    - -
    -
    - - - - -
    #define CAN_F1R2_FB24_Pos   (24U)
    -
    - -
    -
    - -

    ◆ CAN_F1R2_FB24_Msk

    - -
    -
    - - - - -
    #define CAN_F1R2_FB24_Msk   (0x1UL << CAN_F1R2_FB24_Pos)
    -
    -

    0x01000000

    - -
    -
    - -

    ◆ CAN_F1R2_FB24

    - -
    -
    - - - - -
    #define CAN_F1R2_FB24   CAN_F1R2_FB24_Msk
    -
    -

    Filter bit 24

    - -
    -
    - -

    ◆ CAN_F1R2_FB25_Pos

    - -
    -
    - - - - -
    #define CAN_F1R2_FB25_Pos   (25U)
    -
    - -
    -
    - -

    ◆ CAN_F1R2_FB25_Msk

    - -
    -
    - - - - -
    #define CAN_F1R2_FB25_Msk   (0x1UL << CAN_F1R2_FB25_Pos)
    -
    -

    0x02000000

    - -
    -
    - -

    ◆ CAN_F1R2_FB25

    - -
    -
    - - - - -
    #define CAN_F1R2_FB25   CAN_F1R2_FB25_Msk
    -
    -

    Filter bit 25

    - -
    -
    - -

    ◆ CAN_F1R2_FB26_Pos

    - -
    -
    - - - - -
    #define CAN_F1R2_FB26_Pos   (26U)
    -
    - -
    -
    - -

    ◆ CAN_F1R2_FB26_Msk

    - -
    -
    - - - - -
    #define CAN_F1R2_FB26_Msk   (0x1UL << CAN_F1R2_FB26_Pos)
    -
    -

    0x04000000

    - -
    -
    - -

    ◆ CAN_F1R2_FB26

    - -
    -
    - - - - -
    #define CAN_F1R2_FB26   CAN_F1R2_FB26_Msk
    -
    -

    Filter bit 26

    - -
    -
    - -

    ◆ CAN_F1R2_FB27_Pos

    - -
    -
    - - - - -
    #define CAN_F1R2_FB27_Pos   (27U)
    -
    - -
    -
    - -

    ◆ CAN_F1R2_FB27_Msk

    - -
    -
    - - - - -
    #define CAN_F1R2_FB27_Msk   (0x1UL << CAN_F1R2_FB27_Pos)
    -
    -

    0x08000000

    - -
    -
    - -

    ◆ CAN_F1R2_FB27

    - -
    -
    - - - - -
    #define CAN_F1R2_FB27   CAN_F1R2_FB27_Msk
    -
    -

    Filter bit 27

    - -
    -
    - -

    ◆ CAN_F1R2_FB28_Pos

    - -
    -
    - - - - -
    #define CAN_F1R2_FB28_Pos   (28U)
    -
    - -
    -
    - -

    ◆ CAN_F1R2_FB28_Msk

    - -
    -
    - - - - -
    #define CAN_F1R2_FB28_Msk   (0x1UL << CAN_F1R2_FB28_Pos)
    -
    -

    0x10000000

    - -
    -
    - -

    ◆ CAN_F1R2_FB28

    - -
    -
    - - - - -
    #define CAN_F1R2_FB28   CAN_F1R2_FB28_Msk
    -
    -

    Filter bit 28

    - -
    -
    - -

    ◆ CAN_F1R2_FB29_Pos

    - -
    -
    - - - - -
    #define CAN_F1R2_FB29_Pos   (29U)
    -
    - -
    -
    - -

    ◆ CAN_F1R2_FB29_Msk

    - -
    -
    - - - - -
    #define CAN_F1R2_FB29_Msk   (0x1UL << CAN_F1R2_FB29_Pos)
    -
    -

    0x20000000

    - -
    -
    - -

    ◆ CAN_F1R2_FB29

    - -
    -
    - - - - -
    #define CAN_F1R2_FB29   CAN_F1R2_FB29_Msk
    -
    -

    Filter bit 29

    - -
    -
    - -

    ◆ CAN_F1R2_FB30_Pos

    - -
    -
    - - - - -
    #define CAN_F1R2_FB30_Pos   (30U)
    -
    - -
    -
    - -

    ◆ CAN_F1R2_FB30_Msk

    - -
    -
    - - - - -
    #define CAN_F1R2_FB30_Msk   (0x1UL << CAN_F1R2_FB30_Pos)
    -
    -

    0x40000000

    - -
    -
    - -

    ◆ CAN_F1R2_FB30

    - -
    -
    - - - - -
    #define CAN_F1R2_FB30   CAN_F1R2_FB30_Msk
    -
    -

    Filter bit 30

    - -
    -
    - -

    ◆ CAN_F1R2_FB31_Pos

    - -
    -
    - - - - -
    #define CAN_F1R2_FB31_Pos   (31U)
    -
    - -
    -
    - -

    ◆ CAN_F1R2_FB31_Msk

    - -
    -
    - - - - -
    #define CAN_F1R2_FB31_Msk   (0x1UL << CAN_F1R2_FB31_Pos)
    -
    -

    0x80000000

    - -
    -
    - -

    ◆ CAN_F1R2_FB31

    - -
    -
    - - - - -
    #define CAN_F1R2_FB31   CAN_F1R2_FB31_Msk
    -
    -

    Filter bit 31

    - -
    -
    - -

    ◆ CAN_F2R2_FB0_Pos

    - -
    -
    - - - - -
    #define CAN_F2R2_FB0_Pos   (0U)
    -
    - -
    -
    - -

    ◆ CAN_F2R2_FB0_Msk

    - -
    -
    - - - - -
    #define CAN_F2R2_FB0_Msk   (0x1UL << CAN_F2R2_FB0_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ CAN_F2R2_FB0

    - -
    -
    - - - - -
    #define CAN_F2R2_FB0   CAN_F2R2_FB0_Msk
    -
    -

    Filter bit 0

    - -
    -
    - -

    ◆ CAN_F2R2_FB1_Pos

    - -
    -
    - - - - -
    #define CAN_F2R2_FB1_Pos   (1U)
    -
    - -
    -
    - -

    ◆ CAN_F2R2_FB1_Msk

    - -
    -
    - - - - -
    #define CAN_F2R2_FB1_Msk   (0x1UL << CAN_F2R2_FB1_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ CAN_F2R2_FB1

    - -
    -
    - - - - -
    #define CAN_F2R2_FB1   CAN_F2R2_FB1_Msk
    -
    -

    Filter bit 1

    - -
    -
    - -

    ◆ CAN_F2R2_FB2_Pos

    - -
    -
    - - - - -
    #define CAN_F2R2_FB2_Pos   (2U)
    -
    - -
    -
    - -

    ◆ CAN_F2R2_FB2_Msk

    - -
    -
    - - - - -
    #define CAN_F2R2_FB2_Msk   (0x1UL << CAN_F2R2_FB2_Pos)
    -
    -

    0x00000004

    - -
    -
    - -

    ◆ CAN_F2R2_FB2

    - -
    -
    - - - - -
    #define CAN_F2R2_FB2   CAN_F2R2_FB2_Msk
    -
    -

    Filter bit 2

    - -
    -
    - -

    ◆ CAN_F2R2_FB3_Pos

    - -
    -
    - - - - -
    #define CAN_F2R2_FB3_Pos   (3U)
    -
    - -
    -
    - -

    ◆ CAN_F2R2_FB3_Msk

    - -
    -
    - - - - -
    #define CAN_F2R2_FB3_Msk   (0x1UL << CAN_F2R2_FB3_Pos)
    -
    -

    0x00000008

    - -
    -
    - -

    ◆ CAN_F2R2_FB3

    - -
    -
    - - - - -
    #define CAN_F2R2_FB3   CAN_F2R2_FB3_Msk
    -
    -

    Filter bit 3

    - -
    -
    - -

    ◆ CAN_F2R2_FB4_Pos

    - -
    -
    - - - - -
    #define CAN_F2R2_FB4_Pos   (4U)
    -
    - -
    -
    - -

    ◆ CAN_F2R2_FB4_Msk

    - -
    -
    - - - - -
    #define CAN_F2R2_FB4_Msk   (0x1UL << CAN_F2R2_FB4_Pos)
    -
    -

    0x00000010

    - -
    -
    - -

    ◆ CAN_F2R2_FB4

    - -
    -
    - - - - -
    #define CAN_F2R2_FB4   CAN_F2R2_FB4_Msk
    -
    -

    Filter bit 4

    - -
    -
    - -

    ◆ CAN_F2R2_FB5_Pos

    - -
    -
    - - - - -
    #define CAN_F2R2_FB5_Pos   (5U)
    -
    - -
    -
    - -

    ◆ CAN_F2R2_FB5_Msk

    - -
    -
    - - - - -
    #define CAN_F2R2_FB5_Msk   (0x1UL << CAN_F2R2_FB5_Pos)
    -
    -

    0x00000020

    - -
    -
    - -

    ◆ CAN_F2R2_FB5

    - -
    -
    - - - - -
    #define CAN_F2R2_FB5   CAN_F2R2_FB5_Msk
    -
    -

    Filter bit 5

    - -
    -
    - -

    ◆ CAN_F2R2_FB6_Pos

    - -
    -
    - - - - -
    #define CAN_F2R2_FB6_Pos   (6U)
    -
    - -
    -
    - -

    ◆ CAN_F2R2_FB6_Msk

    - -
    -
    - - - - -
    #define CAN_F2R2_FB6_Msk   (0x1UL << CAN_F2R2_FB6_Pos)
    -
    -

    0x00000040

    - -
    -
    - -

    ◆ CAN_F2R2_FB6

    - -
    -
    - - - - -
    #define CAN_F2R2_FB6   CAN_F2R2_FB6_Msk
    -
    -

    Filter bit 6

    - -
    -
    - -

    ◆ CAN_F2R2_FB7_Pos

    - -
    -
    - - - - -
    #define CAN_F2R2_FB7_Pos   (7U)
    -
    - -
    -
    - -

    ◆ CAN_F2R2_FB7_Msk

    - -
    -
    - - - - -
    #define CAN_F2R2_FB7_Msk   (0x1UL << CAN_F2R2_FB7_Pos)
    -
    -

    0x00000080

    - -
    -
    - -

    ◆ CAN_F2R2_FB7

    - -
    -
    - - - - -
    #define CAN_F2R2_FB7   CAN_F2R2_FB7_Msk
    -
    -

    Filter bit 7

    - -
    -
    - -

    ◆ CAN_F2R2_FB8_Pos

    - -
    -
    - - - - -
    #define CAN_F2R2_FB8_Pos   (8U)
    -
    - -
    -
    - -

    ◆ CAN_F2R2_FB8_Msk

    - -
    -
    - - - - -
    #define CAN_F2R2_FB8_Msk   (0x1UL << CAN_F2R2_FB8_Pos)
    -
    -

    0x00000100

    - -
    -
    - -

    ◆ CAN_F2R2_FB8

    - -
    -
    - - - - -
    #define CAN_F2R2_FB8   CAN_F2R2_FB8_Msk
    -
    -

    Filter bit 8

    - -
    -
    - -

    ◆ CAN_F2R2_FB9_Pos

    - -
    -
    - - - - -
    #define CAN_F2R2_FB9_Pos   (9U)
    -
    - -
    -
    - -

    ◆ CAN_F2R2_FB9_Msk

    - -
    -
    - - - - -
    #define CAN_F2R2_FB9_Msk   (0x1UL << CAN_F2R2_FB9_Pos)
    -
    -

    0x00000200

    - -
    -
    - -

    ◆ CAN_F2R2_FB9

    - -
    -
    - - - - -
    #define CAN_F2R2_FB9   CAN_F2R2_FB9_Msk
    -
    -

    Filter bit 9

    - -
    -
    - -

    ◆ CAN_F2R2_FB10_Pos

    - -
    -
    - - - - -
    #define CAN_F2R2_FB10_Pos   (10U)
    -
    - -
    -
    - -

    ◆ CAN_F2R2_FB10_Msk

    - -
    -
    - - - - -
    #define CAN_F2R2_FB10_Msk   (0x1UL << CAN_F2R2_FB10_Pos)
    -
    -

    0x00000400

    - -
    -
    - -

    ◆ CAN_F2R2_FB10

    - -
    -
    - - - - -
    #define CAN_F2R2_FB10   CAN_F2R2_FB10_Msk
    -
    -

    Filter bit 10

    - -
    -
    - -

    ◆ CAN_F2R2_FB11_Pos

    - -
    -
    - - - - -
    #define CAN_F2R2_FB11_Pos   (11U)
    -
    - -
    -
    - -

    ◆ CAN_F2R2_FB11_Msk

    - -
    -
    - - - - -
    #define CAN_F2R2_FB11_Msk   (0x1UL << CAN_F2R2_FB11_Pos)
    -
    -

    0x00000800

    - -
    -
    - -

    ◆ CAN_F2R2_FB11

    - -
    -
    - - - - -
    #define CAN_F2R2_FB11   CAN_F2R2_FB11_Msk
    -
    -

    Filter bit 11

    - -
    -
    - -

    ◆ CAN_F2R2_FB12_Pos

    - -
    -
    - - - - -
    #define CAN_F2R2_FB12_Pos   (12U)
    -
    - -
    -
    - -

    ◆ CAN_F2R2_FB12_Msk

    - -
    -
    - - - - -
    #define CAN_F2R2_FB12_Msk   (0x1UL << CAN_F2R2_FB12_Pos)
    -
    -

    0x00001000

    - -
    -
    - -

    ◆ CAN_F2R2_FB12

    - -
    -
    - - - - -
    #define CAN_F2R2_FB12   CAN_F2R2_FB12_Msk
    -
    -

    Filter bit 12

    - -
    -
    - -

    ◆ CAN_F2R2_FB13_Pos

    - -
    -
    - - - - -
    #define CAN_F2R2_FB13_Pos   (13U)
    -
    - -
    -
    - -

    ◆ CAN_F2R2_FB13_Msk

    - -
    -
    - - - - -
    #define CAN_F2R2_FB13_Msk   (0x1UL << CAN_F2R2_FB13_Pos)
    -
    -

    0x00002000

    - -
    -
    - -

    ◆ CAN_F2R2_FB13

    - -
    -
    - - - - -
    #define CAN_F2R2_FB13   CAN_F2R2_FB13_Msk
    -
    -

    Filter bit 13

    - -
    -
    - -

    ◆ CAN_F2R2_FB14_Pos

    - -
    -
    - - - - -
    #define CAN_F2R2_FB14_Pos   (14U)
    -
    - -
    -
    - -

    ◆ CAN_F2R2_FB14_Msk

    - -
    -
    - - - - -
    #define CAN_F2R2_FB14_Msk   (0x1UL << CAN_F2R2_FB14_Pos)
    -
    -

    0x00004000

    - -
    -
    - -

    ◆ CAN_F2R2_FB14

    - -
    -
    - - - - -
    #define CAN_F2R2_FB14   CAN_F2R2_FB14_Msk
    -
    -

    Filter bit 14

    - -
    -
    - -

    ◆ CAN_F2R2_FB15_Pos

    - -
    -
    - - - - -
    #define CAN_F2R2_FB15_Pos   (15U)
    -
    - -
    -
    - -

    ◆ CAN_F2R2_FB15_Msk

    - -
    -
    - - - - -
    #define CAN_F2R2_FB15_Msk   (0x1UL << CAN_F2R2_FB15_Pos)
    -
    -

    0x00008000

    - -
    -
    - -

    ◆ CAN_F2R2_FB15

    - -
    -
    - - - - -
    #define CAN_F2R2_FB15   CAN_F2R2_FB15_Msk
    -
    -

    Filter bit 15

    - -
    -
    - -

    ◆ CAN_F2R2_FB16_Pos

    - -
    -
    - - - - -
    #define CAN_F2R2_FB16_Pos   (16U)
    -
    - -
    -
    - -

    ◆ CAN_F2R2_FB16_Msk

    - -
    -
    - - - - -
    #define CAN_F2R2_FB16_Msk   (0x1UL << CAN_F2R2_FB16_Pos)
    -
    -

    0x00010000

    - -
    -
    - -

    ◆ CAN_F2R2_FB16

    - -
    -
    - - - - -
    #define CAN_F2R2_FB16   CAN_F2R2_FB16_Msk
    -
    -

    Filter bit 16

    - -
    -
    - -

    ◆ CAN_F2R2_FB17_Pos

    - -
    -
    - - - - -
    #define CAN_F2R2_FB17_Pos   (17U)
    -
    - -
    -
    - -

    ◆ CAN_F2R2_FB17_Msk

    - -
    -
    - - - - -
    #define CAN_F2R2_FB17_Msk   (0x1UL << CAN_F2R2_FB17_Pos)
    -
    -

    0x00020000

    - -
    -
    - -

    ◆ CAN_F2R2_FB17

    - -
    -
    - - - - -
    #define CAN_F2R2_FB17   CAN_F2R2_FB17_Msk
    -
    -

    Filter bit 17

    - -
    -
    - -

    ◆ CAN_F2R2_FB18_Pos

    - -
    -
    - - - - -
    #define CAN_F2R2_FB18_Pos   (18U)
    -
    - -
    -
    - -

    ◆ CAN_F2R2_FB18_Msk

    - -
    -
    - - - - -
    #define CAN_F2R2_FB18_Msk   (0x1UL << CAN_F2R2_FB18_Pos)
    -
    -

    0x00040000

    - -
    -
    - -

    ◆ CAN_F2R2_FB18

    - -
    -
    - - - - -
    #define CAN_F2R2_FB18   CAN_F2R2_FB18_Msk
    -
    -

    Filter bit 18

    - -
    -
    - -

    ◆ CAN_F2R2_FB19_Pos

    - -
    -
    - - - - -
    #define CAN_F2R2_FB19_Pos   (19U)
    -
    - -
    -
    - -

    ◆ CAN_F2R2_FB19_Msk

    - -
    -
    - - - - -
    #define CAN_F2R2_FB19_Msk   (0x1UL << CAN_F2R2_FB19_Pos)
    -
    -

    0x00080000

    - -
    -
    - -

    ◆ CAN_F2R2_FB19

    - -
    -
    - - - - -
    #define CAN_F2R2_FB19   CAN_F2R2_FB19_Msk
    -
    -

    Filter bit 19

    - -
    -
    - -

    ◆ CAN_F2R2_FB20_Pos

    - -
    -
    - - - - -
    #define CAN_F2R2_FB20_Pos   (20U)
    -
    - -
    -
    - -

    ◆ CAN_F2R2_FB20_Msk

    - -
    -
    - - - - -
    #define CAN_F2R2_FB20_Msk   (0x1UL << CAN_F2R2_FB20_Pos)
    -
    -

    0x00100000

    - -
    -
    - -

    ◆ CAN_F2R2_FB20

    - -
    -
    - - - - -
    #define CAN_F2R2_FB20   CAN_F2R2_FB20_Msk
    -
    -

    Filter bit 20

    - -
    -
    - -

    ◆ CAN_F2R2_FB21_Pos

    - -
    -
    - - - - -
    #define CAN_F2R2_FB21_Pos   (21U)
    -
    - -
    -
    - -

    ◆ CAN_F2R2_FB21_Msk

    - -
    -
    - - - - -
    #define CAN_F2R2_FB21_Msk   (0x1UL << CAN_F2R2_FB21_Pos)
    -
    -

    0x00200000

    - -
    -
    - -

    ◆ CAN_F2R2_FB21

    - -
    -
    - - - - -
    #define CAN_F2R2_FB21   CAN_F2R2_FB21_Msk
    -
    -

    Filter bit 21

    - -
    -
    - -

    ◆ CAN_F2R2_FB22_Pos

    - -
    -
    - - - - -
    #define CAN_F2R2_FB22_Pos   (22U)
    -
    - -
    -
    - -

    ◆ CAN_F2R2_FB22_Msk

    - -
    -
    - - - - -
    #define CAN_F2R2_FB22_Msk   (0x1UL << CAN_F2R2_FB22_Pos)
    -
    -

    0x00400000

    - -
    -
    - -

    ◆ CAN_F2R2_FB22

    - -
    -
    - - - - -
    #define CAN_F2R2_FB22   CAN_F2R2_FB22_Msk
    -
    -

    Filter bit 22

    - -
    -
    - -

    ◆ CAN_F2R2_FB23_Pos

    - -
    -
    - - - - -
    #define CAN_F2R2_FB23_Pos   (23U)
    -
    - -
    -
    - -

    ◆ CAN_F2R2_FB23_Msk

    - -
    -
    - - - - -
    #define CAN_F2R2_FB23_Msk   (0x1UL << CAN_F2R2_FB23_Pos)
    -
    -

    0x00800000

    - -
    -
    - -

    ◆ CAN_F2R2_FB23

    - -
    -
    - - - - -
    #define CAN_F2R2_FB23   CAN_F2R2_FB23_Msk
    -
    -

    Filter bit 23

    - -
    -
    - -

    ◆ CAN_F2R2_FB24_Pos

    - -
    -
    - - - - -
    #define CAN_F2R2_FB24_Pos   (24U)
    -
    - -
    -
    - -

    ◆ CAN_F2R2_FB24_Msk

    - -
    -
    - - - - -
    #define CAN_F2R2_FB24_Msk   (0x1UL << CAN_F2R2_FB24_Pos)
    -
    -

    0x01000000

    - -
    -
    - -

    ◆ CAN_F2R2_FB24

    - -
    -
    - - - - -
    #define CAN_F2R2_FB24   CAN_F2R2_FB24_Msk
    -
    -

    Filter bit 24

    - -
    -
    - -

    ◆ CAN_F2R2_FB25_Pos

    - -
    -
    - - - - -
    #define CAN_F2R2_FB25_Pos   (25U)
    -
    - -
    -
    - -

    ◆ CAN_F2R2_FB25_Msk

    - -
    -
    - - - - -
    #define CAN_F2R2_FB25_Msk   (0x1UL << CAN_F2R2_FB25_Pos)
    -
    -

    0x02000000

    - -
    -
    - -

    ◆ CAN_F2R2_FB25

    - -
    -
    - - - - -
    #define CAN_F2R2_FB25   CAN_F2R2_FB25_Msk
    -
    -

    Filter bit 25

    - -
    -
    - -

    ◆ CAN_F2R2_FB26_Pos

    - -
    -
    - - - - -
    #define CAN_F2R2_FB26_Pos   (26U)
    -
    - -
    -
    - -

    ◆ CAN_F2R2_FB26_Msk

    - -
    -
    - - - - -
    #define CAN_F2R2_FB26_Msk   (0x1UL << CAN_F2R2_FB26_Pos)
    -
    -

    0x04000000

    - -
    -
    - -

    ◆ CAN_F2R2_FB26

    - -
    -
    - - - - -
    #define CAN_F2R2_FB26   CAN_F2R2_FB26_Msk
    -
    -

    Filter bit 26

    - -
    -
    - -

    ◆ CAN_F2R2_FB27_Pos

    - -
    -
    - - - - -
    #define CAN_F2R2_FB27_Pos   (27U)
    -
    - -
    -
    - -

    ◆ CAN_F2R2_FB27_Msk

    - -
    -
    - - - - -
    #define CAN_F2R2_FB27_Msk   (0x1UL << CAN_F2R2_FB27_Pos)
    -
    -

    0x08000000

    - -
    -
    - -

    ◆ CAN_F2R2_FB27

    - -
    -
    - - - - -
    #define CAN_F2R2_FB27   CAN_F2R2_FB27_Msk
    -
    -

    Filter bit 27

    - -
    -
    - -

    ◆ CAN_F2R2_FB28_Pos

    - -
    -
    - - - - -
    #define CAN_F2R2_FB28_Pos   (28U)
    -
    - -
    -
    - -

    ◆ CAN_F2R2_FB28_Msk

    - -
    -
    - - - - -
    #define CAN_F2R2_FB28_Msk   (0x1UL << CAN_F2R2_FB28_Pos)
    -
    -

    0x10000000

    - -
    -
    - -

    ◆ CAN_F2R2_FB28

    - -
    -
    - - - - -
    #define CAN_F2R2_FB28   CAN_F2R2_FB28_Msk
    -
    -

    Filter bit 28

    - -
    -
    - -

    ◆ CAN_F2R2_FB29_Pos

    - -
    -
    - - - - -
    #define CAN_F2R2_FB29_Pos   (29U)
    -
    - -
    -
    - -

    ◆ CAN_F2R2_FB29_Msk

    - -
    -
    - - - - -
    #define CAN_F2R2_FB29_Msk   (0x1UL << CAN_F2R2_FB29_Pos)
    -
    -

    0x20000000

    - -
    -
    - -

    ◆ CAN_F2R2_FB29

    - -
    -
    - - - - -
    #define CAN_F2R2_FB29   CAN_F2R2_FB29_Msk
    -
    -

    Filter bit 29

    - -
    -
    - -

    ◆ CAN_F2R2_FB30_Pos

    - -
    -
    - - - - -
    #define CAN_F2R2_FB30_Pos   (30U)
    -
    - -
    -
    - -

    ◆ CAN_F2R2_FB30_Msk

    - -
    -
    - - - - -
    #define CAN_F2R2_FB30_Msk   (0x1UL << CAN_F2R2_FB30_Pos)
    -
    -

    0x40000000

    - -
    -
    - -

    ◆ CAN_F2R2_FB30

    - -
    -
    - - - - -
    #define CAN_F2R2_FB30   CAN_F2R2_FB30_Msk
    -
    -

    Filter bit 30

    - -
    -
    - -

    ◆ CAN_F2R2_FB31_Pos

    - -
    -
    - - - - -
    #define CAN_F2R2_FB31_Pos   (31U)
    -
    - -
    -
    - -

    ◆ CAN_F2R2_FB31_Msk

    - -
    -
    - - - - -
    #define CAN_F2R2_FB31_Msk   (0x1UL << CAN_F2R2_FB31_Pos)
    -
    -

    0x80000000

    - -
    -
    - -

    ◆ CAN_F2R2_FB31

    - -
    -
    - - - - -
    #define CAN_F2R2_FB31   CAN_F2R2_FB31_Msk
    -
    -

    Filter bit 31

    - -
    -
    - -

    ◆ CAN_F3R2_FB0_Pos

    - -
    -
    - - - - -
    #define CAN_F3R2_FB0_Pos   (0U)
    -
    - -
    -
    - -

    ◆ CAN_F3R2_FB0_Msk

    - -
    -
    - - - - -
    #define CAN_F3R2_FB0_Msk   (0x1UL << CAN_F3R2_FB0_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ CAN_F3R2_FB0

    - -
    -
    - - - - -
    #define CAN_F3R2_FB0   CAN_F3R2_FB0_Msk
    -
    -

    Filter bit 0

    - -
    -
    - -

    ◆ CAN_F3R2_FB1_Pos

    - -
    -
    - - - - -
    #define CAN_F3R2_FB1_Pos   (1U)
    -
    - -
    -
    - -

    ◆ CAN_F3R2_FB1_Msk

    - -
    -
    - - - - -
    #define CAN_F3R2_FB1_Msk   (0x1UL << CAN_F3R2_FB1_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ CAN_F3R2_FB1

    - -
    -
    - - - - -
    #define CAN_F3R2_FB1   CAN_F3R2_FB1_Msk
    -
    -

    Filter bit 1

    - -
    -
    - -

    ◆ CAN_F3R2_FB2_Pos

    - -
    -
    - - - - -
    #define CAN_F3R2_FB2_Pos   (2U)
    -
    - -
    -
    - -

    ◆ CAN_F3R2_FB2_Msk

    - -
    -
    - - - - -
    #define CAN_F3R2_FB2_Msk   (0x1UL << CAN_F3R2_FB2_Pos)
    -
    -

    0x00000004

    - -
    -
    - -

    ◆ CAN_F3R2_FB2

    - -
    -
    - - - - -
    #define CAN_F3R2_FB2   CAN_F3R2_FB2_Msk
    -
    -

    Filter bit 2

    - -
    -
    - -

    ◆ CAN_F3R2_FB3_Pos

    - -
    -
    - - - - -
    #define CAN_F3R2_FB3_Pos   (3U)
    -
    - -
    -
    - -

    ◆ CAN_F3R2_FB3_Msk

    - -
    -
    - - - - -
    #define CAN_F3R2_FB3_Msk   (0x1UL << CAN_F3R2_FB3_Pos)
    -
    -

    0x00000008

    - -
    -
    - -

    ◆ CAN_F3R2_FB3

    - -
    -
    - - - - -
    #define CAN_F3R2_FB3   CAN_F3R2_FB3_Msk
    -
    -

    Filter bit 3

    - -
    -
    - -

    ◆ CAN_F3R2_FB4_Pos

    - -
    -
    - - - - -
    #define CAN_F3R2_FB4_Pos   (4U)
    -
    - -
    -
    - -

    ◆ CAN_F3R2_FB4_Msk

    - -
    -
    - - - - -
    #define CAN_F3R2_FB4_Msk   (0x1UL << CAN_F3R2_FB4_Pos)
    -
    -

    0x00000010

    - -
    -
    - -

    ◆ CAN_F3R2_FB4

    - -
    -
    - - - - -
    #define CAN_F3R2_FB4   CAN_F3R2_FB4_Msk
    -
    -

    Filter bit 4

    - -
    -
    - -

    ◆ CAN_F3R2_FB5_Pos

    - -
    -
    - - - - -
    #define CAN_F3R2_FB5_Pos   (5U)
    -
    - -
    -
    - -

    ◆ CAN_F3R2_FB5_Msk

    - -
    -
    - - - - -
    #define CAN_F3R2_FB5_Msk   (0x1UL << CAN_F3R2_FB5_Pos)
    -
    -

    0x00000020

    - -
    -
    - -

    ◆ CAN_F3R2_FB5

    - -
    -
    - - - - -
    #define CAN_F3R2_FB5   CAN_F3R2_FB5_Msk
    -
    -

    Filter bit 5

    - -
    -
    - -

    ◆ CAN_F3R2_FB6_Pos

    - -
    -
    - - - - -
    #define CAN_F3R2_FB6_Pos   (6U)
    -
    - -
    -
    - -

    ◆ CAN_F3R2_FB6_Msk

    - -
    -
    - - - - -
    #define CAN_F3R2_FB6_Msk   (0x1UL << CAN_F3R2_FB6_Pos)
    -
    -

    0x00000040

    - -
    -
    - -

    ◆ CAN_F3R2_FB6

    - -
    -
    - - - - -
    #define CAN_F3R2_FB6   CAN_F3R2_FB6_Msk
    -
    -

    Filter bit 6

    - -
    -
    - -

    ◆ CAN_F3R2_FB7_Pos

    - -
    -
    - - - - -
    #define CAN_F3R2_FB7_Pos   (7U)
    -
    - -
    -
    - -

    ◆ CAN_F3R2_FB7_Msk

    - -
    -
    - - - - -
    #define CAN_F3R2_FB7_Msk   (0x1UL << CAN_F3R2_FB7_Pos)
    -
    -

    0x00000080

    - -
    -
    - -

    ◆ CAN_F3R2_FB7

    - -
    -
    - - - - -
    #define CAN_F3R2_FB7   CAN_F3R2_FB7_Msk
    -
    -

    Filter bit 7

    - -
    -
    - -

    ◆ CAN_F3R2_FB8_Pos

    - -
    -
    - - - - -
    #define CAN_F3R2_FB8_Pos   (8U)
    -
    - -
    -
    - -

    ◆ CAN_F3R2_FB8_Msk

    - -
    -
    - - - - -
    #define CAN_F3R2_FB8_Msk   (0x1UL << CAN_F3R2_FB8_Pos)
    -
    -

    0x00000100

    - -
    -
    - -

    ◆ CAN_F3R2_FB8

    - -
    -
    - - - - -
    #define CAN_F3R2_FB8   CAN_F3R2_FB8_Msk
    -
    -

    Filter bit 8

    - -
    -
    - -

    ◆ CAN_F3R2_FB9_Pos

    - -
    -
    - - - - -
    #define CAN_F3R2_FB9_Pos   (9U)
    -
    - -
    -
    - -

    ◆ CAN_F3R2_FB9_Msk

    - -
    -
    - - - - -
    #define CAN_F3R2_FB9_Msk   (0x1UL << CAN_F3R2_FB9_Pos)
    -
    -

    0x00000200

    - -
    -
    - -

    ◆ CAN_F3R2_FB9

    - -
    -
    - - - - -
    #define CAN_F3R2_FB9   CAN_F3R2_FB9_Msk
    -
    -

    Filter bit 9

    - -
    -
    - -

    ◆ CAN_F3R2_FB10_Pos

    - -
    -
    - - - - -
    #define CAN_F3R2_FB10_Pos   (10U)
    -
    - -
    -
    - -

    ◆ CAN_F3R2_FB10_Msk

    - -
    -
    - - - - -
    #define CAN_F3R2_FB10_Msk   (0x1UL << CAN_F3R2_FB10_Pos)
    -
    -

    0x00000400

    - -
    -
    - -

    ◆ CAN_F3R2_FB10

    - -
    -
    - - - - -
    #define CAN_F3R2_FB10   CAN_F3R2_FB10_Msk
    -
    -

    Filter bit 10

    - -
    -
    - -

    ◆ CAN_F3R2_FB11_Pos

    - -
    -
    - - - - -
    #define CAN_F3R2_FB11_Pos   (11U)
    -
    - -
    -
    - -

    ◆ CAN_F3R2_FB11_Msk

    - -
    -
    - - - - -
    #define CAN_F3R2_FB11_Msk   (0x1UL << CAN_F3R2_FB11_Pos)
    -
    -

    0x00000800

    - -
    -
    - -

    ◆ CAN_F3R2_FB11

    - -
    -
    - - - - -
    #define CAN_F3R2_FB11   CAN_F3R2_FB11_Msk
    -
    -

    Filter bit 11

    - -
    -
    - -

    ◆ CAN_F3R2_FB12_Pos

    - -
    -
    - - - - -
    #define CAN_F3R2_FB12_Pos   (12U)
    -
    - -
    -
    - -

    ◆ CAN_F3R2_FB12_Msk

    - -
    -
    - - - - -
    #define CAN_F3R2_FB12_Msk   (0x1UL << CAN_F3R2_FB12_Pos)
    -
    -

    0x00001000

    - -
    -
    - -

    ◆ CAN_F3R2_FB12

    - -
    -
    - - - - -
    #define CAN_F3R2_FB12   CAN_F3R2_FB12_Msk
    -
    -

    Filter bit 12

    - -
    -
    - -

    ◆ CAN_F3R2_FB13_Pos

    - -
    -
    - - - - -
    #define CAN_F3R2_FB13_Pos   (13U)
    -
    - -
    -
    - -

    ◆ CAN_F3R2_FB13_Msk

    - -
    -
    - - - - -
    #define CAN_F3R2_FB13_Msk   (0x1UL << CAN_F3R2_FB13_Pos)
    -
    -

    0x00002000

    - -
    -
    - -

    ◆ CAN_F3R2_FB13

    - -
    -
    - - - - -
    #define CAN_F3R2_FB13   CAN_F3R2_FB13_Msk
    -
    -

    Filter bit 13

    - -
    -
    - -

    ◆ CAN_F3R2_FB14_Pos

    - -
    -
    - - - - -
    #define CAN_F3R2_FB14_Pos   (14U)
    -
    - -
    -
    - -

    ◆ CAN_F3R2_FB14_Msk

    - -
    -
    - - - - -
    #define CAN_F3R2_FB14_Msk   (0x1UL << CAN_F3R2_FB14_Pos)
    -
    -

    0x00004000

    - -
    -
    - -

    ◆ CAN_F3R2_FB14

    - -
    -
    - - - - -
    #define CAN_F3R2_FB14   CAN_F3R2_FB14_Msk
    -
    -

    Filter bit 14

    - -
    -
    - -

    ◆ CAN_F3R2_FB15_Pos

    - -
    -
    - - - - -
    #define CAN_F3R2_FB15_Pos   (15U)
    -
    - -
    -
    - -

    ◆ CAN_F3R2_FB15_Msk

    - -
    -
    - - - - -
    #define CAN_F3R2_FB15_Msk   (0x1UL << CAN_F3R2_FB15_Pos)
    -
    -

    0x00008000

    - -
    -
    - -

    ◆ CAN_F3R2_FB15

    - -
    -
    - - - - -
    #define CAN_F3R2_FB15   CAN_F3R2_FB15_Msk
    -
    -

    Filter bit 15

    - -
    -
    - -

    ◆ CAN_F3R2_FB16_Pos

    - -
    -
    - - - - -
    #define CAN_F3R2_FB16_Pos   (16U)
    -
    - -
    -
    - -

    ◆ CAN_F3R2_FB16_Msk

    - -
    -
    - - - - -
    #define CAN_F3R2_FB16_Msk   (0x1UL << CAN_F3R2_FB16_Pos)
    -
    -

    0x00010000

    - -
    -
    - -

    ◆ CAN_F3R2_FB16

    - -
    -
    - - - - -
    #define CAN_F3R2_FB16   CAN_F3R2_FB16_Msk
    -
    -

    Filter bit 16

    - -
    -
    - -

    ◆ CAN_F3R2_FB17_Pos

    - -
    -
    - - - - -
    #define CAN_F3R2_FB17_Pos   (17U)
    -
    - -
    -
    - -

    ◆ CAN_F3R2_FB17_Msk

    - -
    -
    - - - - -
    #define CAN_F3R2_FB17_Msk   (0x1UL << CAN_F3R2_FB17_Pos)
    -
    -

    0x00020000

    - -
    -
    - -

    ◆ CAN_F3R2_FB17

    - -
    -
    - - - - -
    #define CAN_F3R2_FB17   CAN_F3R2_FB17_Msk
    -
    -

    Filter bit 17

    - -
    -
    - -

    ◆ CAN_F3R2_FB18_Pos

    - -
    -
    - - - - -
    #define CAN_F3R2_FB18_Pos   (18U)
    -
    - -
    -
    - -

    ◆ CAN_F3R2_FB18_Msk

    - -
    -
    - - - - -
    #define CAN_F3R2_FB18_Msk   (0x1UL << CAN_F3R2_FB18_Pos)
    -
    -

    0x00040000

    - -
    -
    - -

    ◆ CAN_F3R2_FB18

    - -
    -
    - - - - -
    #define CAN_F3R2_FB18   CAN_F3R2_FB18_Msk
    -
    -

    Filter bit 18

    - -
    -
    - -

    ◆ CAN_F3R2_FB19_Pos

    - -
    -
    - - - - -
    #define CAN_F3R2_FB19_Pos   (19U)
    -
    - -
    -
    - -

    ◆ CAN_F3R2_FB19_Msk

    - -
    -
    - - - - -
    #define CAN_F3R2_FB19_Msk   (0x1UL << CAN_F3R2_FB19_Pos)
    -
    -

    0x00080000

    - -
    -
    - -

    ◆ CAN_F3R2_FB19

    - -
    -
    - - - - -
    #define CAN_F3R2_FB19   CAN_F3R2_FB19_Msk
    -
    -

    Filter bit 19

    - -
    -
    - -

    ◆ CAN_F3R2_FB20_Pos

    - -
    -
    - - - - -
    #define CAN_F3R2_FB20_Pos   (20U)
    -
    - -
    -
    - -

    ◆ CAN_F3R2_FB20_Msk

    - -
    -
    - - - - -
    #define CAN_F3R2_FB20_Msk   (0x1UL << CAN_F3R2_FB20_Pos)
    -
    -

    0x00100000

    - -
    -
    - -

    ◆ CAN_F3R2_FB20

    - -
    -
    - - - - -
    #define CAN_F3R2_FB20   CAN_F3R2_FB20_Msk
    -
    -

    Filter bit 20

    - -
    -
    - -

    ◆ CAN_F3R2_FB21_Pos

    - -
    -
    - - - - -
    #define CAN_F3R2_FB21_Pos   (21U)
    -
    - -
    -
    - -

    ◆ CAN_F3R2_FB21_Msk

    - -
    -
    - - - - -
    #define CAN_F3R2_FB21_Msk   (0x1UL << CAN_F3R2_FB21_Pos)
    -
    -

    0x00200000

    - -
    -
    - -

    ◆ CAN_F3R2_FB21

    - -
    -
    - - - - -
    #define CAN_F3R2_FB21   CAN_F3R2_FB21_Msk
    -
    -

    Filter bit 21

    - -
    -
    - -

    ◆ CAN_F3R2_FB22_Pos

    - -
    -
    - - - - -
    #define CAN_F3R2_FB22_Pos   (22U)
    -
    - -
    -
    - -

    ◆ CAN_F3R2_FB22_Msk

    - -
    -
    - - - - -
    #define CAN_F3R2_FB22_Msk   (0x1UL << CAN_F3R2_FB22_Pos)
    -
    -

    0x00400000

    - -
    -
    - -

    ◆ CAN_F3R2_FB22

    - -
    -
    - - - - -
    #define CAN_F3R2_FB22   CAN_F3R2_FB22_Msk
    -
    -

    Filter bit 22

    - -
    -
    - -

    ◆ CAN_F3R2_FB23_Pos

    - -
    -
    - - - - -
    #define CAN_F3R2_FB23_Pos   (23U)
    -
    - -
    -
    - -

    ◆ CAN_F3R2_FB23_Msk

    - -
    -
    - - - - -
    #define CAN_F3R2_FB23_Msk   (0x1UL << CAN_F3R2_FB23_Pos)
    -
    -

    0x00800000

    - -
    -
    - -

    ◆ CAN_F3R2_FB23

    - -
    -
    - - - - -
    #define CAN_F3R2_FB23   CAN_F3R2_FB23_Msk
    -
    -

    Filter bit 23

    - -
    -
    - -

    ◆ CAN_F3R2_FB24_Pos

    - -
    -
    - - - - -
    #define CAN_F3R2_FB24_Pos   (24U)
    -
    - -
    -
    - -

    ◆ CAN_F3R2_FB24_Msk

    - -
    -
    - - - - -
    #define CAN_F3R2_FB24_Msk   (0x1UL << CAN_F3R2_FB24_Pos)
    -
    -

    0x01000000

    - -
    -
    - -

    ◆ CAN_F3R2_FB24

    - -
    -
    - - - - -
    #define CAN_F3R2_FB24   CAN_F3R2_FB24_Msk
    -
    -

    Filter bit 24

    - -
    -
    - -

    ◆ CAN_F3R2_FB25_Pos

    - -
    -
    - - - - -
    #define CAN_F3R2_FB25_Pos   (25U)
    -
    - -
    -
    - -

    ◆ CAN_F3R2_FB25_Msk

    - -
    -
    - - - - -
    #define CAN_F3R2_FB25_Msk   (0x1UL << CAN_F3R2_FB25_Pos)
    -
    -

    0x02000000

    - -
    -
    - -

    ◆ CAN_F3R2_FB25

    - -
    -
    - - - - -
    #define CAN_F3R2_FB25   CAN_F3R2_FB25_Msk
    -
    -

    Filter bit 25

    - -
    -
    - -

    ◆ CAN_F3R2_FB26_Pos

    - -
    -
    - - - - -
    #define CAN_F3R2_FB26_Pos   (26U)
    -
    - -
    -
    - -

    ◆ CAN_F3R2_FB26_Msk

    - -
    -
    - - - - -
    #define CAN_F3R2_FB26_Msk   (0x1UL << CAN_F3R2_FB26_Pos)
    -
    -

    0x04000000

    - -
    -
    - -

    ◆ CAN_F3R2_FB26

    - -
    -
    - - - - -
    #define CAN_F3R2_FB26   CAN_F3R2_FB26_Msk
    -
    -

    Filter bit 26

    - -
    -
    - -

    ◆ CAN_F3R2_FB27_Pos

    - -
    -
    - - - - -
    #define CAN_F3R2_FB27_Pos   (27U)
    -
    - -
    -
    - -

    ◆ CAN_F3R2_FB27_Msk

    - -
    -
    - - - - -
    #define CAN_F3R2_FB27_Msk   (0x1UL << CAN_F3R2_FB27_Pos)
    -
    -

    0x08000000

    - -
    -
    - -

    ◆ CAN_F3R2_FB27

    - -
    -
    - - - - -
    #define CAN_F3R2_FB27   CAN_F3R2_FB27_Msk
    -
    -

    Filter bit 27

    - -
    -
    - -

    ◆ CAN_F3R2_FB28_Pos

    - -
    -
    - - - - -
    #define CAN_F3R2_FB28_Pos   (28U)
    -
    - -
    -
    - -

    ◆ CAN_F3R2_FB28_Msk

    - -
    -
    - - - - -
    #define CAN_F3R2_FB28_Msk   (0x1UL << CAN_F3R2_FB28_Pos)
    -
    -

    0x10000000

    - -
    -
    - -

    ◆ CAN_F3R2_FB28

    - -
    -
    - - - - -
    #define CAN_F3R2_FB28   CAN_F3R2_FB28_Msk
    -
    -

    Filter bit 28

    - -
    -
    - -

    ◆ CAN_F3R2_FB29_Pos

    - -
    -
    - - - - -
    #define CAN_F3R2_FB29_Pos   (29U)
    -
    - -
    -
    - -

    ◆ CAN_F3R2_FB29_Msk

    - -
    -
    - - - - -
    #define CAN_F3R2_FB29_Msk   (0x1UL << CAN_F3R2_FB29_Pos)
    -
    -

    0x20000000

    - -
    -
    - -

    ◆ CAN_F3R2_FB29

    - -
    -
    - - - - -
    #define CAN_F3R2_FB29   CAN_F3R2_FB29_Msk
    -
    -

    Filter bit 29

    - -
    -
    - -

    ◆ CAN_F3R2_FB30_Pos

    - -
    -
    - - - - -
    #define CAN_F3R2_FB30_Pos   (30U)
    -
    - -
    -
    - -

    ◆ CAN_F3R2_FB30_Msk

    - -
    -
    - - - - -
    #define CAN_F3R2_FB30_Msk   (0x1UL << CAN_F3R2_FB30_Pos)
    -
    -

    0x40000000

    - -
    -
    - -

    ◆ CAN_F3R2_FB30

    - -
    -
    - - - - -
    #define CAN_F3R2_FB30   CAN_F3R2_FB30_Msk
    -
    -

    Filter bit 30

    - -
    -
    - -

    ◆ CAN_F3R2_FB31_Pos

    - -
    -
    - - - - -
    #define CAN_F3R2_FB31_Pos   (31U)
    -
    - -
    -
    - -

    ◆ CAN_F3R2_FB31_Msk

    - -
    -
    - - - - -
    #define CAN_F3R2_FB31_Msk   (0x1UL << CAN_F3R2_FB31_Pos)
    -
    -

    0x80000000

    - -
    -
    - -

    ◆ CAN_F3R2_FB31

    - -
    -
    - - - - -
    #define CAN_F3R2_FB31   CAN_F3R2_FB31_Msk
    -
    -

    Filter bit 31

    - -
    -
    - -

    ◆ CAN_F4R2_FB0_Pos

    - -
    -
    - - - - -
    #define CAN_F4R2_FB0_Pos   (0U)
    -
    - -
    -
    - -

    ◆ CAN_F4R2_FB0_Msk

    - -
    -
    - - - - -
    #define CAN_F4R2_FB0_Msk   (0x1UL << CAN_F4R2_FB0_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ CAN_F4R2_FB0

    - -
    -
    - - - - -
    #define CAN_F4R2_FB0   CAN_F4R2_FB0_Msk
    -
    -

    Filter bit 0

    - -
    -
    - -

    ◆ CAN_F4R2_FB1_Pos

    - -
    -
    - - - - -
    #define CAN_F4R2_FB1_Pos   (1U)
    -
    - -
    -
    - -

    ◆ CAN_F4R2_FB1_Msk

    - -
    -
    - - - - -
    #define CAN_F4R2_FB1_Msk   (0x1UL << CAN_F4R2_FB1_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ CAN_F4R2_FB1

    - -
    -
    - - - - -
    #define CAN_F4R2_FB1   CAN_F4R2_FB1_Msk
    -
    -

    Filter bit 1

    - -
    -
    - -

    ◆ CAN_F4R2_FB2_Pos

    - -
    -
    - - - - -
    #define CAN_F4R2_FB2_Pos   (2U)
    -
    - -
    -
    - -

    ◆ CAN_F4R2_FB2_Msk

    - -
    -
    - - - - -
    #define CAN_F4R2_FB2_Msk   (0x1UL << CAN_F4R2_FB2_Pos)
    -
    -

    0x00000004

    - -
    -
    - -

    ◆ CAN_F4R2_FB2

    - -
    -
    - - - - -
    #define CAN_F4R2_FB2   CAN_F4R2_FB2_Msk
    -
    -

    Filter bit 2

    - -
    -
    - -

    ◆ CAN_F4R2_FB3_Pos

    - -
    -
    - - - - -
    #define CAN_F4R2_FB3_Pos   (3U)
    -
    - -
    -
    - -

    ◆ CAN_F4R2_FB3_Msk

    - -
    -
    - - - - -
    #define CAN_F4R2_FB3_Msk   (0x1UL << CAN_F4R2_FB3_Pos)
    -
    -

    0x00000008

    - -
    -
    - -

    ◆ CAN_F4R2_FB3

    - -
    -
    - - - - -
    #define CAN_F4R2_FB3   CAN_F4R2_FB3_Msk
    -
    -

    Filter bit 3

    - -
    -
    - -

    ◆ CAN_F4R2_FB4_Pos

    - -
    -
    - - - - -
    #define CAN_F4R2_FB4_Pos   (4U)
    -
    - -
    -
    - -

    ◆ CAN_F4R2_FB4_Msk

    - -
    -
    - - - - -
    #define CAN_F4R2_FB4_Msk   (0x1UL << CAN_F4R2_FB4_Pos)
    -
    -

    0x00000010

    - -
    -
    - -

    ◆ CAN_F4R2_FB4

    - -
    -
    - - - - -
    #define CAN_F4R2_FB4   CAN_F4R2_FB4_Msk
    -
    -

    Filter bit 4

    - -
    -
    - -

    ◆ CAN_F4R2_FB5_Pos

    - -
    -
    - - - - -
    #define CAN_F4R2_FB5_Pos   (5U)
    -
    - -
    -
    - -

    ◆ CAN_F4R2_FB5_Msk

    - -
    -
    - - - - -
    #define CAN_F4R2_FB5_Msk   (0x1UL << CAN_F4R2_FB5_Pos)
    -
    -

    0x00000020

    - -
    -
    - -

    ◆ CAN_F4R2_FB5

    - -
    -
    - - - - -
    #define CAN_F4R2_FB5   CAN_F4R2_FB5_Msk
    -
    -

    Filter bit 5

    - -
    -
    - -

    ◆ CAN_F4R2_FB6_Pos

    - -
    -
    - - - - -
    #define CAN_F4R2_FB6_Pos   (6U)
    -
    - -
    -
    - -

    ◆ CAN_F4R2_FB6_Msk

    - -
    -
    - - - - -
    #define CAN_F4R2_FB6_Msk   (0x1UL << CAN_F4R2_FB6_Pos)
    -
    -

    0x00000040

    - -
    -
    - -

    ◆ CAN_F4R2_FB6

    - -
    -
    - - - - -
    #define CAN_F4R2_FB6   CAN_F4R2_FB6_Msk
    -
    -

    Filter bit 6

    - -
    -
    - -

    ◆ CAN_F4R2_FB7_Pos

    - -
    -
    - - - - -
    #define CAN_F4R2_FB7_Pos   (7U)
    -
    - -
    -
    - -

    ◆ CAN_F4R2_FB7_Msk

    - -
    -
    - - - - -
    #define CAN_F4R2_FB7_Msk   (0x1UL << CAN_F4R2_FB7_Pos)
    -
    -

    0x00000080

    - -
    -
    - -

    ◆ CAN_F4R2_FB7

    - -
    -
    - - - - -
    #define CAN_F4R2_FB7   CAN_F4R2_FB7_Msk
    -
    -

    Filter bit 7

    - -
    -
    - -

    ◆ CAN_F4R2_FB8_Pos

    - -
    -
    - - - - -
    #define CAN_F4R2_FB8_Pos   (8U)
    -
    - -
    -
    - -

    ◆ CAN_F4R2_FB8_Msk

    - -
    -
    - - - - -
    #define CAN_F4R2_FB8_Msk   (0x1UL << CAN_F4R2_FB8_Pos)
    -
    -

    0x00000100

    - -
    -
    - -

    ◆ CAN_F4R2_FB8

    - -
    -
    - - - - -
    #define CAN_F4R2_FB8   CAN_F4R2_FB8_Msk
    -
    -

    Filter bit 8

    - -
    -
    - -

    ◆ CAN_F4R2_FB9_Pos

    - -
    -
    - - - - -
    #define CAN_F4R2_FB9_Pos   (9U)
    -
    - -
    -
    - -

    ◆ CAN_F4R2_FB9_Msk

    - -
    -
    - - - - -
    #define CAN_F4R2_FB9_Msk   (0x1UL << CAN_F4R2_FB9_Pos)
    -
    -

    0x00000200

    - -
    -
    - -

    ◆ CAN_F4R2_FB9

    - -
    -
    - - - - -
    #define CAN_F4R2_FB9   CAN_F4R2_FB9_Msk
    -
    -

    Filter bit 9

    - -
    -
    - -

    ◆ CAN_F4R2_FB10_Pos

    - -
    -
    - - - - -
    #define CAN_F4R2_FB10_Pos   (10U)
    -
    - -
    -
    - -

    ◆ CAN_F4R2_FB10_Msk

    - -
    -
    - - - - -
    #define CAN_F4R2_FB10_Msk   (0x1UL << CAN_F4R2_FB10_Pos)
    -
    -

    0x00000400

    - -
    -
    - -

    ◆ CAN_F4R2_FB10

    - -
    -
    - - - - -
    #define CAN_F4R2_FB10   CAN_F4R2_FB10_Msk
    -
    -

    Filter bit 10

    - -
    -
    - -

    ◆ CAN_F4R2_FB11_Pos

    - -
    -
    - - - - -
    #define CAN_F4R2_FB11_Pos   (11U)
    -
    - -
    -
    - -

    ◆ CAN_F4R2_FB11_Msk

    - -
    -
    - - - - -
    #define CAN_F4R2_FB11_Msk   (0x1UL << CAN_F4R2_FB11_Pos)
    -
    -

    0x00000800

    - -
    -
    - -

    ◆ CAN_F4R2_FB11

    - -
    -
    - - - - -
    #define CAN_F4R2_FB11   CAN_F4R2_FB11_Msk
    -
    -

    Filter bit 11

    - -
    -
    - -

    ◆ CAN_F4R2_FB12_Pos

    - -
    -
    - - - - -
    #define CAN_F4R2_FB12_Pos   (12U)
    -
    - -
    -
    - -

    ◆ CAN_F4R2_FB12_Msk

    - -
    -
    - - - - -
    #define CAN_F4R2_FB12_Msk   (0x1UL << CAN_F4R2_FB12_Pos)
    -
    -

    0x00001000

    - -
    -
    - -

    ◆ CAN_F4R2_FB12

    - -
    -
    - - - - -
    #define CAN_F4R2_FB12   CAN_F4R2_FB12_Msk
    -
    -

    Filter bit 12

    - -
    -
    - -

    ◆ CAN_F4R2_FB13_Pos

    - -
    -
    - - - - -
    #define CAN_F4R2_FB13_Pos   (13U)
    -
    - -
    -
    - -

    ◆ CAN_F4R2_FB13_Msk

    - -
    -
    - - - - -
    #define CAN_F4R2_FB13_Msk   (0x1UL << CAN_F4R2_FB13_Pos)
    -
    -

    0x00002000

    - -
    -
    - -

    ◆ CAN_F4R2_FB13

    - -
    -
    - - - - -
    #define CAN_F4R2_FB13   CAN_F4R2_FB13_Msk
    -
    -

    Filter bit 13

    - -
    -
    - -

    ◆ CAN_F4R2_FB14_Pos

    - -
    -
    - - - - -
    #define CAN_F4R2_FB14_Pos   (14U)
    -
    - -
    -
    - -

    ◆ CAN_F4R2_FB14_Msk

    - -
    -
    - - - - -
    #define CAN_F4R2_FB14_Msk   (0x1UL << CAN_F4R2_FB14_Pos)
    -
    -

    0x00004000

    - -
    -
    - -

    ◆ CAN_F4R2_FB14

    - -
    -
    - - - - -
    #define CAN_F4R2_FB14   CAN_F4R2_FB14_Msk
    -
    -

    Filter bit 14

    - -
    -
    - -

    ◆ CAN_F4R2_FB15_Pos

    - -
    -
    - - - - -
    #define CAN_F4R2_FB15_Pos   (15U)
    -
    - -
    -
    - -

    ◆ CAN_F4R2_FB15_Msk

    - -
    -
    - - - - -
    #define CAN_F4R2_FB15_Msk   (0x1UL << CAN_F4R2_FB15_Pos)
    -
    -

    0x00008000

    - -
    -
    - -

    ◆ CAN_F4R2_FB15

    - -
    -
    - - - - -
    #define CAN_F4R2_FB15   CAN_F4R2_FB15_Msk
    -
    -

    Filter bit 15

    - -
    -
    - -

    ◆ CAN_F4R2_FB16_Pos

    - -
    -
    - - - - -
    #define CAN_F4R2_FB16_Pos   (16U)
    -
    - -
    -
    - -

    ◆ CAN_F4R2_FB16_Msk

    - -
    -
    - - - - -
    #define CAN_F4R2_FB16_Msk   (0x1UL << CAN_F4R2_FB16_Pos)
    -
    -

    0x00010000

    - -
    -
    - -

    ◆ CAN_F4R2_FB16

    - -
    -
    - - - - -
    #define CAN_F4R2_FB16   CAN_F4R2_FB16_Msk
    -
    -

    Filter bit 16

    - -
    -
    - -

    ◆ CAN_F4R2_FB17_Pos

    - -
    -
    - - - - -
    #define CAN_F4R2_FB17_Pos   (17U)
    -
    - -
    -
    - -

    ◆ CAN_F4R2_FB17_Msk

    - -
    -
    - - - - -
    #define CAN_F4R2_FB17_Msk   (0x1UL << CAN_F4R2_FB17_Pos)
    -
    -

    0x00020000

    - -
    -
    - -

    ◆ CAN_F4R2_FB17

    - -
    -
    - - - - -
    #define CAN_F4R2_FB17   CAN_F4R2_FB17_Msk
    -
    -

    Filter bit 17

    - -
    -
    - -

    ◆ CAN_F4R2_FB18_Pos

    - -
    -
    - - - - -
    #define CAN_F4R2_FB18_Pos   (18U)
    -
    - -
    -
    - -

    ◆ CAN_F4R2_FB18_Msk

    - -
    -
    - - - - -
    #define CAN_F4R2_FB18_Msk   (0x1UL << CAN_F4R2_FB18_Pos)
    -
    -

    0x00040000

    - -
    -
    - -

    ◆ CAN_F4R2_FB18

    - -
    -
    - - - - -
    #define CAN_F4R2_FB18   CAN_F4R2_FB18_Msk
    -
    -

    Filter bit 18

    - -
    -
    - -

    ◆ CAN_F4R2_FB19_Pos

    - -
    -
    - - - - -
    #define CAN_F4R2_FB19_Pos   (19U)
    -
    - -
    -
    - -

    ◆ CAN_F4R2_FB19_Msk

    - -
    -
    - - - - -
    #define CAN_F4R2_FB19_Msk   (0x1UL << CAN_F4R2_FB19_Pos)
    -
    -

    0x00080000

    - -
    -
    - -

    ◆ CAN_F4R2_FB19

    - -
    -
    - - - - -
    #define CAN_F4R2_FB19   CAN_F4R2_FB19_Msk
    -
    -

    Filter bit 19

    - -
    -
    - -

    ◆ CAN_F4R2_FB20_Pos

    - -
    -
    - - - - -
    #define CAN_F4R2_FB20_Pos   (20U)
    -
    - -
    -
    - -

    ◆ CAN_F4R2_FB20_Msk

    - -
    -
    - - - - -
    #define CAN_F4R2_FB20_Msk   (0x1UL << CAN_F4R2_FB20_Pos)
    -
    -

    0x00100000

    - -
    -
    - -

    ◆ CAN_F4R2_FB20

    - -
    -
    - - - - -
    #define CAN_F4R2_FB20   CAN_F4R2_FB20_Msk
    -
    -

    Filter bit 20

    - -
    -
    - -

    ◆ CAN_F4R2_FB21_Pos

    - -
    -
    - - - - -
    #define CAN_F4R2_FB21_Pos   (21U)
    -
    - -
    -
    - -

    ◆ CAN_F4R2_FB21_Msk

    - -
    -
    - - - - -
    #define CAN_F4R2_FB21_Msk   (0x1UL << CAN_F4R2_FB21_Pos)
    -
    -

    0x00200000

    - -
    -
    - -

    ◆ CAN_F4R2_FB21

    - -
    -
    - - - - -
    #define CAN_F4R2_FB21   CAN_F4R2_FB21_Msk
    -
    -

    Filter bit 21

    - -
    -
    - -

    ◆ CAN_F4R2_FB22_Pos

    - -
    -
    - - - - -
    #define CAN_F4R2_FB22_Pos   (22U)
    -
    - -
    -
    - -

    ◆ CAN_F4R2_FB22_Msk

    - -
    -
    - - - - -
    #define CAN_F4R2_FB22_Msk   (0x1UL << CAN_F4R2_FB22_Pos)
    -
    -

    0x00400000

    - -
    -
    - -

    ◆ CAN_F4R2_FB22

    - -
    -
    - - - - -
    #define CAN_F4R2_FB22   CAN_F4R2_FB22_Msk
    -
    -

    Filter bit 22

    - -
    -
    - -

    ◆ CAN_F4R2_FB23_Pos

    - -
    -
    - - - - -
    #define CAN_F4R2_FB23_Pos   (23U)
    -
    - -
    -
    - -

    ◆ CAN_F4R2_FB23_Msk

    - -
    -
    - - - - -
    #define CAN_F4R2_FB23_Msk   (0x1UL << CAN_F4R2_FB23_Pos)
    -
    -

    0x00800000

    - -
    -
    - -

    ◆ CAN_F4R2_FB23

    - -
    -
    - - - - -
    #define CAN_F4R2_FB23   CAN_F4R2_FB23_Msk
    -
    -

    Filter bit 23

    - -
    -
    - -

    ◆ CAN_F4R2_FB24_Pos

    - -
    -
    - - - - -
    #define CAN_F4R2_FB24_Pos   (24U)
    -
    - -
    -
    - -

    ◆ CAN_F4R2_FB24_Msk

    - -
    -
    - - - - -
    #define CAN_F4R2_FB24_Msk   (0x1UL << CAN_F4R2_FB24_Pos)
    -
    -

    0x01000000

    - -
    -
    - -

    ◆ CAN_F4R2_FB24

    - -
    -
    - - - - -
    #define CAN_F4R2_FB24   CAN_F4R2_FB24_Msk
    -
    -

    Filter bit 24

    - -
    -
    - -

    ◆ CAN_F4R2_FB25_Pos

    - -
    -
    - - - - -
    #define CAN_F4R2_FB25_Pos   (25U)
    -
    - -
    -
    - -

    ◆ CAN_F4R2_FB25_Msk

    - -
    -
    - - - - -
    #define CAN_F4R2_FB25_Msk   (0x1UL << CAN_F4R2_FB25_Pos)
    -
    -

    0x02000000

    - -
    -
    - -

    ◆ CAN_F4R2_FB25

    - -
    -
    - - - - -
    #define CAN_F4R2_FB25   CAN_F4R2_FB25_Msk
    -
    -

    Filter bit 25

    - -
    -
    - -

    ◆ CAN_F4R2_FB26_Pos

    - -
    -
    - - - - -
    #define CAN_F4R2_FB26_Pos   (26U)
    -
    - -
    -
    - -

    ◆ CAN_F4R2_FB26_Msk

    - -
    -
    - - - - -
    #define CAN_F4R2_FB26_Msk   (0x1UL << CAN_F4R2_FB26_Pos)
    -
    -

    0x04000000

    - -
    -
    - -

    ◆ CAN_F4R2_FB26

    - -
    -
    - - - - -
    #define CAN_F4R2_FB26   CAN_F4R2_FB26_Msk
    -
    -

    Filter bit 26

    - -
    -
    - -

    ◆ CAN_F4R2_FB27_Pos

    - -
    -
    - - - - -
    #define CAN_F4R2_FB27_Pos   (27U)
    -
    - -
    -
    - -

    ◆ CAN_F4R2_FB27_Msk

    - -
    -
    - - - - -
    #define CAN_F4R2_FB27_Msk   (0x1UL << CAN_F4R2_FB27_Pos)
    -
    -

    0x08000000

    - -
    -
    - -

    ◆ CAN_F4R2_FB27

    - -
    -
    - - - - -
    #define CAN_F4R2_FB27   CAN_F4R2_FB27_Msk
    -
    -

    Filter bit 27

    - -
    -
    - -

    ◆ CAN_F4R2_FB28_Pos

    - -
    -
    - - - - -
    #define CAN_F4R2_FB28_Pos   (28U)
    -
    - -
    -
    - -

    ◆ CAN_F4R2_FB28_Msk

    - -
    -
    - - - - -
    #define CAN_F4R2_FB28_Msk   (0x1UL << CAN_F4R2_FB28_Pos)
    -
    -

    0x10000000

    - -
    -
    - -

    ◆ CAN_F4R2_FB28

    - -
    -
    - - - - -
    #define CAN_F4R2_FB28   CAN_F4R2_FB28_Msk
    -
    -

    Filter bit 28

    - -
    -
    - -

    ◆ CAN_F4R2_FB29_Pos

    - -
    -
    - - - - -
    #define CAN_F4R2_FB29_Pos   (29U)
    -
    - -
    -
    - -

    ◆ CAN_F4R2_FB29_Msk

    - -
    -
    - - - - -
    #define CAN_F4R2_FB29_Msk   (0x1UL << CAN_F4R2_FB29_Pos)
    -
    -

    0x20000000

    - -
    -
    - -

    ◆ CAN_F4R2_FB29

    - -
    -
    - - - - -
    #define CAN_F4R2_FB29   CAN_F4R2_FB29_Msk
    -
    -

    Filter bit 29

    - -
    -
    - -

    ◆ CAN_F4R2_FB30_Pos

    - -
    -
    - - - - -
    #define CAN_F4R2_FB30_Pos   (30U)
    -
    - -
    -
    - -

    ◆ CAN_F4R2_FB30_Msk

    - -
    -
    - - - - -
    #define CAN_F4R2_FB30_Msk   (0x1UL << CAN_F4R2_FB30_Pos)
    -
    -

    0x40000000

    - -
    -
    - -

    ◆ CAN_F4R2_FB30

    - -
    -
    - - - - -
    #define CAN_F4R2_FB30   CAN_F4R2_FB30_Msk
    -
    -

    Filter bit 30

    - -
    -
    - -

    ◆ CAN_F4R2_FB31_Pos

    - -
    -
    - - - - -
    #define CAN_F4R2_FB31_Pos   (31U)
    -
    - -
    -
    - -

    ◆ CAN_F4R2_FB31_Msk

    - -
    -
    - - - - -
    #define CAN_F4R2_FB31_Msk   (0x1UL << CAN_F4R2_FB31_Pos)
    -
    -

    0x80000000

    - -
    -
    - -

    ◆ CAN_F4R2_FB31

    - -
    -
    - - - - -
    #define CAN_F4R2_FB31   CAN_F4R2_FB31_Msk
    -
    -

    Filter bit 31

    - -
    -
    - -

    ◆ CAN_F5R2_FB0_Pos

    - -
    -
    - - - - -
    #define CAN_F5R2_FB0_Pos   (0U)
    -
    - -
    -
    - -

    ◆ CAN_F5R2_FB0_Msk

    - -
    -
    - - - - -
    #define CAN_F5R2_FB0_Msk   (0x1UL << CAN_F5R2_FB0_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ CAN_F5R2_FB0

    - -
    -
    - - - - -
    #define CAN_F5R2_FB0   CAN_F5R2_FB0_Msk
    -
    -

    Filter bit 0

    - -
    -
    - -

    ◆ CAN_F5R2_FB1_Pos

    - -
    -
    - - - - -
    #define CAN_F5R2_FB1_Pos   (1U)
    -
    - -
    -
    - -

    ◆ CAN_F5R2_FB1_Msk

    - -
    -
    - - - - -
    #define CAN_F5R2_FB1_Msk   (0x1UL << CAN_F5R2_FB1_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ CAN_F5R2_FB1

    - -
    -
    - - - - -
    #define CAN_F5R2_FB1   CAN_F5R2_FB1_Msk
    -
    -

    Filter bit 1

    - -
    -
    - -

    ◆ CAN_F5R2_FB2_Pos

    - -
    -
    - - - - -
    #define CAN_F5R2_FB2_Pos   (2U)
    -
    - -
    -
    - -

    ◆ CAN_F5R2_FB2_Msk

    - -
    -
    - - - - -
    #define CAN_F5R2_FB2_Msk   (0x1UL << CAN_F5R2_FB2_Pos)
    -
    -

    0x00000004

    - -
    -
    - -

    ◆ CAN_F5R2_FB2

    - -
    -
    - - - - -
    #define CAN_F5R2_FB2   CAN_F5R2_FB2_Msk
    -
    -

    Filter bit 2

    - -
    -
    - -

    ◆ CAN_F5R2_FB3_Pos

    - -
    -
    - - - - -
    #define CAN_F5R2_FB3_Pos   (3U)
    -
    - -
    -
    - -

    ◆ CAN_F5R2_FB3_Msk

    - -
    -
    - - - - -
    #define CAN_F5R2_FB3_Msk   (0x1UL << CAN_F5R2_FB3_Pos)
    -
    -

    0x00000008

    - -
    -
    - -

    ◆ CAN_F5R2_FB3

    - -
    -
    - - - - -
    #define CAN_F5R2_FB3   CAN_F5R2_FB3_Msk
    -
    -

    Filter bit 3

    - -
    -
    - -

    ◆ CAN_F5R2_FB4_Pos

    - -
    -
    - - - - -
    #define CAN_F5R2_FB4_Pos   (4U)
    -
    - -
    -
    - -

    ◆ CAN_F5R2_FB4_Msk

    - -
    -
    - - - - -
    #define CAN_F5R2_FB4_Msk   (0x1UL << CAN_F5R2_FB4_Pos)
    -
    -

    0x00000010

    - -
    -
    - -

    ◆ CAN_F5R2_FB4

    - -
    -
    - - - - -
    #define CAN_F5R2_FB4   CAN_F5R2_FB4_Msk
    -
    -

    Filter bit 4

    - -
    -
    - -

    ◆ CAN_F5R2_FB5_Pos

    - -
    -
    - - - - -
    #define CAN_F5R2_FB5_Pos   (5U)
    -
    - -
    -
    - -

    ◆ CAN_F5R2_FB5_Msk

    - -
    -
    - - - - -
    #define CAN_F5R2_FB5_Msk   (0x1UL << CAN_F5R2_FB5_Pos)
    -
    -

    0x00000020

    - -
    -
    - -

    ◆ CAN_F5R2_FB5

    - -
    -
    - - - - -
    #define CAN_F5R2_FB5   CAN_F5R2_FB5_Msk
    -
    -

    Filter bit 5

    - -
    -
    - -

    ◆ CAN_F5R2_FB6_Pos

    - -
    -
    - - - - -
    #define CAN_F5R2_FB6_Pos   (6U)
    -
    - -
    -
    - -

    ◆ CAN_F5R2_FB6_Msk

    - -
    -
    - - - - -
    #define CAN_F5R2_FB6_Msk   (0x1UL << CAN_F5R2_FB6_Pos)
    -
    -

    0x00000040

    - -
    -
    - -

    ◆ CAN_F5R2_FB6

    - -
    -
    - - - - -
    #define CAN_F5R2_FB6   CAN_F5R2_FB6_Msk
    -
    -

    Filter bit 6

    - -
    -
    - -

    ◆ CAN_F5R2_FB7_Pos

    - -
    -
    - - - - -
    #define CAN_F5R2_FB7_Pos   (7U)
    -
    - -
    -
    - -

    ◆ CAN_F5R2_FB7_Msk

    - -
    -
    - - - - -
    #define CAN_F5R2_FB7_Msk   (0x1UL << CAN_F5R2_FB7_Pos)
    -
    -

    0x00000080

    - -
    -
    - -

    ◆ CAN_F5R2_FB7

    - -
    -
    - - - - -
    #define CAN_F5R2_FB7   CAN_F5R2_FB7_Msk
    -
    -

    Filter bit 7

    - -
    -
    - -

    ◆ CAN_F5R2_FB8_Pos

    - -
    -
    - - - - -
    #define CAN_F5R2_FB8_Pos   (8U)
    -
    - -
    -
    - -

    ◆ CAN_F5R2_FB8_Msk

    - -
    -
    - - - - -
    #define CAN_F5R2_FB8_Msk   (0x1UL << CAN_F5R2_FB8_Pos)
    -
    -

    0x00000100

    - -
    -
    - -

    ◆ CAN_F5R2_FB8

    - -
    -
    - - - - -
    #define CAN_F5R2_FB8   CAN_F5R2_FB8_Msk
    -
    -

    Filter bit 8

    - -
    -
    - -

    ◆ CAN_F5R2_FB9_Pos

    - -
    -
    - - - - -
    #define CAN_F5R2_FB9_Pos   (9U)
    -
    - -
    -
    - -

    ◆ CAN_F5R2_FB9_Msk

    - -
    -
    - - - - -
    #define CAN_F5R2_FB9_Msk   (0x1UL << CAN_F5R2_FB9_Pos)
    -
    -

    0x00000200

    - -
    -
    - -

    ◆ CAN_F5R2_FB9

    - -
    -
    - - - - -
    #define CAN_F5R2_FB9   CAN_F5R2_FB9_Msk
    -
    -

    Filter bit 9

    - -
    -
    - -

    ◆ CAN_F5R2_FB10_Pos

    - -
    -
    - - - - -
    #define CAN_F5R2_FB10_Pos   (10U)
    -
    - -
    -
    - -

    ◆ CAN_F5R2_FB10_Msk

    - -
    -
    - - - - -
    #define CAN_F5R2_FB10_Msk   (0x1UL << CAN_F5R2_FB10_Pos)
    -
    -

    0x00000400

    - -
    -
    - -

    ◆ CAN_F5R2_FB10

    - -
    -
    - - - - -
    #define CAN_F5R2_FB10   CAN_F5R2_FB10_Msk
    -
    -

    Filter bit 10

    - -
    -
    - -

    ◆ CAN_F5R2_FB11_Pos

    - -
    -
    - - - - -
    #define CAN_F5R2_FB11_Pos   (11U)
    -
    - -
    -
    - -

    ◆ CAN_F5R2_FB11_Msk

    - -
    -
    - - - - -
    #define CAN_F5R2_FB11_Msk   (0x1UL << CAN_F5R2_FB11_Pos)
    -
    -

    0x00000800

    - -
    -
    - -

    ◆ CAN_F5R2_FB11

    - -
    -
    - - - - -
    #define CAN_F5R2_FB11   CAN_F5R2_FB11_Msk
    -
    -

    Filter bit 11

    - -
    -
    - -

    ◆ CAN_F5R2_FB12_Pos

    - -
    -
    - - - - -
    #define CAN_F5R2_FB12_Pos   (12U)
    -
    - -
    -
    - -

    ◆ CAN_F5R2_FB12_Msk

    - -
    -
    - - - - -
    #define CAN_F5R2_FB12_Msk   (0x1UL << CAN_F5R2_FB12_Pos)
    -
    -

    0x00001000

    - -
    -
    - -

    ◆ CAN_F5R2_FB12

    - -
    -
    - - - - -
    #define CAN_F5R2_FB12   CAN_F5R2_FB12_Msk
    -
    -

    Filter bit 12

    - -
    -
    - -

    ◆ CAN_F5R2_FB13_Pos

    - -
    -
    - - - - -
    #define CAN_F5R2_FB13_Pos   (13U)
    -
    - -
    -
    - -

    ◆ CAN_F5R2_FB13_Msk

    - -
    -
    - - - - -
    #define CAN_F5R2_FB13_Msk   (0x1UL << CAN_F5R2_FB13_Pos)
    -
    -

    0x00002000

    - -
    -
    - -

    ◆ CAN_F5R2_FB13

    - -
    -
    - - - - -
    #define CAN_F5R2_FB13   CAN_F5R2_FB13_Msk
    -
    -

    Filter bit 13

    - -
    -
    - -

    ◆ CAN_F5R2_FB14_Pos

    - -
    -
    - - - - -
    #define CAN_F5R2_FB14_Pos   (14U)
    -
    - -
    -
    - -

    ◆ CAN_F5R2_FB14_Msk

    - -
    -
    - - - - -
    #define CAN_F5R2_FB14_Msk   (0x1UL << CAN_F5R2_FB14_Pos)
    -
    -

    0x00004000

    - -
    -
    - -

    ◆ CAN_F5R2_FB14

    - -
    -
    - - - - -
    #define CAN_F5R2_FB14   CAN_F5R2_FB14_Msk
    -
    -

    Filter bit 14

    - -
    -
    - -

    ◆ CAN_F5R2_FB15_Pos

    - -
    -
    - - - - -
    #define CAN_F5R2_FB15_Pos   (15U)
    -
    - -
    -
    - -

    ◆ CAN_F5R2_FB15_Msk

    - -
    -
    - - - - -
    #define CAN_F5R2_FB15_Msk   (0x1UL << CAN_F5R2_FB15_Pos)
    -
    -

    0x00008000

    - -
    -
    - -

    ◆ CAN_F5R2_FB15

    - -
    -
    - - - - -
    #define CAN_F5R2_FB15   CAN_F5R2_FB15_Msk
    -
    -

    Filter bit 15

    - -
    -
    - -

    ◆ CAN_F5R2_FB16_Pos

    - -
    -
    - - - - -
    #define CAN_F5R2_FB16_Pos   (16U)
    -
    - -
    -
    - -

    ◆ CAN_F5R2_FB16_Msk

    - -
    -
    - - - - -
    #define CAN_F5R2_FB16_Msk   (0x1UL << CAN_F5R2_FB16_Pos)
    -
    -

    0x00010000

    - -
    -
    - -

    ◆ CAN_F5R2_FB16

    - -
    -
    - - - - -
    #define CAN_F5R2_FB16   CAN_F5R2_FB16_Msk
    -
    -

    Filter bit 16

    - -
    -
    - -

    ◆ CAN_F5R2_FB17_Pos

    - -
    -
    - - - - -
    #define CAN_F5R2_FB17_Pos   (17U)
    -
    - -
    -
    - -

    ◆ CAN_F5R2_FB17_Msk

    - -
    -
    - - - - -
    #define CAN_F5R2_FB17_Msk   (0x1UL << CAN_F5R2_FB17_Pos)
    -
    -

    0x00020000

    - -
    -
    - -

    ◆ CAN_F5R2_FB17

    - -
    -
    - - - - -
    #define CAN_F5R2_FB17   CAN_F5R2_FB17_Msk
    -
    -

    Filter bit 17

    - -
    -
    - -

    ◆ CAN_F5R2_FB18_Pos

    - -
    -
    - - - - -
    #define CAN_F5R2_FB18_Pos   (18U)
    -
    - -
    -
    - -

    ◆ CAN_F5R2_FB18_Msk

    - -
    -
    - - - - -
    #define CAN_F5R2_FB18_Msk   (0x1UL << CAN_F5R2_FB18_Pos)
    -
    -

    0x00040000

    - -
    -
    - -

    ◆ CAN_F5R2_FB18

    - -
    -
    - - - - -
    #define CAN_F5R2_FB18   CAN_F5R2_FB18_Msk
    -
    -

    Filter bit 18

    - -
    -
    - -

    ◆ CAN_F5R2_FB19_Pos

    - -
    -
    - - - - -
    #define CAN_F5R2_FB19_Pos   (19U)
    -
    - -
    -
    - -

    ◆ CAN_F5R2_FB19_Msk

    - -
    -
    - - - - -
    #define CAN_F5R2_FB19_Msk   (0x1UL << CAN_F5R2_FB19_Pos)
    -
    -

    0x00080000

    - -
    -
    - -

    ◆ CAN_F5R2_FB19

    - -
    -
    - - - - -
    #define CAN_F5R2_FB19   CAN_F5R2_FB19_Msk
    -
    -

    Filter bit 19

    - -
    -
    - -

    ◆ CAN_F5R2_FB20_Pos

    - -
    -
    - - - - -
    #define CAN_F5R2_FB20_Pos   (20U)
    -
    - -
    -
    - -

    ◆ CAN_F5R2_FB20_Msk

    - -
    -
    - - - - -
    #define CAN_F5R2_FB20_Msk   (0x1UL << CAN_F5R2_FB20_Pos)
    -
    -

    0x00100000

    - -
    -
    - -

    ◆ CAN_F5R2_FB20

    - -
    -
    - - - - -
    #define CAN_F5R2_FB20   CAN_F5R2_FB20_Msk
    -
    -

    Filter bit 20

    - -
    -
    - -

    ◆ CAN_F5R2_FB21_Pos

    - -
    -
    - - - - -
    #define CAN_F5R2_FB21_Pos   (21U)
    -
    - -
    -
    - -

    ◆ CAN_F5R2_FB21_Msk

    - -
    -
    - - - - -
    #define CAN_F5R2_FB21_Msk   (0x1UL << CAN_F5R2_FB21_Pos)
    -
    -

    0x00200000

    - -
    -
    - -

    ◆ CAN_F5R2_FB21

    - -
    -
    - - - - -
    #define CAN_F5R2_FB21   CAN_F5R2_FB21_Msk
    -
    -

    Filter bit 21

    - -
    -
    - -

    ◆ CAN_F5R2_FB22_Pos

    - -
    -
    - - - - -
    #define CAN_F5R2_FB22_Pos   (22U)
    -
    - -
    -
    - -

    ◆ CAN_F5R2_FB22_Msk

    - -
    -
    - - - - -
    #define CAN_F5R2_FB22_Msk   (0x1UL << CAN_F5R2_FB22_Pos)
    -
    -

    0x00400000

    - -
    -
    - -

    ◆ CAN_F5R2_FB22

    - -
    -
    - - - - -
    #define CAN_F5R2_FB22   CAN_F5R2_FB22_Msk
    -
    -

    Filter bit 22

    - -
    -
    - -

    ◆ CAN_F5R2_FB23_Pos

    - -
    -
    - - - - -
    #define CAN_F5R2_FB23_Pos   (23U)
    -
    - -
    -
    - -

    ◆ CAN_F5R2_FB23_Msk

    - -
    -
    - - - - -
    #define CAN_F5R2_FB23_Msk   (0x1UL << CAN_F5R2_FB23_Pos)
    -
    -

    0x00800000

    - -
    -
    - -

    ◆ CAN_F5R2_FB23

    - -
    -
    - - - - -
    #define CAN_F5R2_FB23   CAN_F5R2_FB23_Msk
    -
    -

    Filter bit 23

    - -
    -
    - -

    ◆ CAN_F5R2_FB24_Pos

    - -
    -
    - - - - -
    #define CAN_F5R2_FB24_Pos   (24U)
    -
    - -
    -
    - -

    ◆ CAN_F5R2_FB24_Msk

    - -
    -
    - - - - -
    #define CAN_F5R2_FB24_Msk   (0x1UL << CAN_F5R2_FB24_Pos)
    -
    -

    0x01000000

    - -
    -
    - -

    ◆ CAN_F5R2_FB24

    - -
    -
    - - - - -
    #define CAN_F5R2_FB24   CAN_F5R2_FB24_Msk
    -
    -

    Filter bit 24

    - -
    -
    - -

    ◆ CAN_F5R2_FB25_Pos

    - -
    -
    - - - - -
    #define CAN_F5R2_FB25_Pos   (25U)
    -
    - -
    -
    - -

    ◆ CAN_F5R2_FB25_Msk

    - -
    -
    - - - - -
    #define CAN_F5R2_FB25_Msk   (0x1UL << CAN_F5R2_FB25_Pos)
    -
    -

    0x02000000

    - -
    -
    - -

    ◆ CAN_F5R2_FB25

    - -
    -
    - - - - -
    #define CAN_F5R2_FB25   CAN_F5R2_FB25_Msk
    -
    -

    Filter bit 25

    - -
    -
    - -

    ◆ CAN_F5R2_FB26_Pos

    - -
    -
    - - - - -
    #define CAN_F5R2_FB26_Pos   (26U)
    -
    - -
    -
    - -

    ◆ CAN_F5R2_FB26_Msk

    - -
    -
    - - - - -
    #define CAN_F5R2_FB26_Msk   (0x1UL << CAN_F5R2_FB26_Pos)
    -
    -

    0x04000000

    - -
    -
    - -

    ◆ CAN_F5R2_FB26

    - -
    -
    - - - - -
    #define CAN_F5R2_FB26   CAN_F5R2_FB26_Msk
    -
    -

    Filter bit 26

    - -
    -
    - -

    ◆ CAN_F5R2_FB27_Pos

    - -
    -
    - - - - -
    #define CAN_F5R2_FB27_Pos   (27U)
    -
    - -
    -
    - -

    ◆ CAN_F5R2_FB27_Msk

    - -
    -
    - - - - -
    #define CAN_F5R2_FB27_Msk   (0x1UL << CAN_F5R2_FB27_Pos)
    -
    -

    0x08000000

    - -
    -
    - -

    ◆ CAN_F5R2_FB27

    - -
    -
    - - - - -
    #define CAN_F5R2_FB27   CAN_F5R2_FB27_Msk
    -
    -

    Filter bit 27

    - -
    -
    - -

    ◆ CAN_F5R2_FB28_Pos

    - -
    -
    - - - - -
    #define CAN_F5R2_FB28_Pos   (28U)
    -
    - -
    -
    - -

    ◆ CAN_F5R2_FB28_Msk

    - -
    -
    - - - - -
    #define CAN_F5R2_FB28_Msk   (0x1UL << CAN_F5R2_FB28_Pos)
    -
    -

    0x10000000

    - -
    -
    - -

    ◆ CAN_F5R2_FB28

    - -
    -
    - - - - -
    #define CAN_F5R2_FB28   CAN_F5R2_FB28_Msk
    -
    -

    Filter bit 28

    - -
    -
    - -

    ◆ CAN_F5R2_FB29_Pos

    - -
    -
    - - - - -
    #define CAN_F5R2_FB29_Pos   (29U)
    -
    - -
    -
    - -

    ◆ CAN_F5R2_FB29_Msk

    - -
    -
    - - - - -
    #define CAN_F5R2_FB29_Msk   (0x1UL << CAN_F5R2_FB29_Pos)
    -
    -

    0x20000000

    - -
    -
    - -

    ◆ CAN_F5R2_FB29

    - -
    -
    - - - - -
    #define CAN_F5R2_FB29   CAN_F5R2_FB29_Msk
    -
    -

    Filter bit 29

    - -
    -
    - -

    ◆ CAN_F5R2_FB30_Pos

    - -
    -
    - - - - -
    #define CAN_F5R2_FB30_Pos   (30U)
    -
    - -
    -
    - -

    ◆ CAN_F5R2_FB30_Msk

    - -
    -
    - - - - -
    #define CAN_F5R2_FB30_Msk   (0x1UL << CAN_F5R2_FB30_Pos)
    -
    -

    0x40000000

    - -
    -
    - -

    ◆ CAN_F5R2_FB30

    - -
    -
    - - - - -
    #define CAN_F5R2_FB30   CAN_F5R2_FB30_Msk
    -
    -

    Filter bit 30

    - -
    -
    - -

    ◆ CAN_F5R2_FB31_Pos

    - -
    -
    - - - - -
    #define CAN_F5R2_FB31_Pos   (31U)
    -
    - -
    -
    - -

    ◆ CAN_F5R2_FB31_Msk

    - -
    -
    - - - - -
    #define CAN_F5R2_FB31_Msk   (0x1UL << CAN_F5R2_FB31_Pos)
    -
    -

    0x80000000

    - -
    -
    - -

    ◆ CAN_F5R2_FB31

    - -
    -
    - - - - -
    #define CAN_F5R2_FB31   CAN_F5R2_FB31_Msk
    -
    -

    Filter bit 31

    - -
    -
    - -

    ◆ CAN_F6R2_FB0_Pos

    - -
    -
    - - - - -
    #define CAN_F6R2_FB0_Pos   (0U)
    -
    - -
    -
    - -

    ◆ CAN_F6R2_FB0_Msk

    - -
    -
    - - - - -
    #define CAN_F6R2_FB0_Msk   (0x1UL << CAN_F6R2_FB0_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ CAN_F6R2_FB0

    - -
    -
    - - - - -
    #define CAN_F6R2_FB0   CAN_F6R2_FB0_Msk
    -
    -

    Filter bit 0

    - -
    -
    - -

    ◆ CAN_F6R2_FB1_Pos

    - -
    -
    - - - - -
    #define CAN_F6R2_FB1_Pos   (1U)
    -
    - -
    -
    - -

    ◆ CAN_F6R2_FB1_Msk

    - -
    -
    - - - - -
    #define CAN_F6R2_FB1_Msk   (0x1UL << CAN_F6R2_FB1_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ CAN_F6R2_FB1

    - -
    -
    - - - - -
    #define CAN_F6R2_FB1   CAN_F6R2_FB1_Msk
    -
    -

    Filter bit 1

    - -
    -
    - -

    ◆ CAN_F6R2_FB2_Pos

    - -
    -
    - - - - -
    #define CAN_F6R2_FB2_Pos   (2U)
    -
    - -
    -
    - -

    ◆ CAN_F6R2_FB2_Msk

    - -
    -
    - - - - -
    #define CAN_F6R2_FB2_Msk   (0x1UL << CAN_F6R2_FB2_Pos)
    -
    -

    0x00000004

    - -
    -
    - -

    ◆ CAN_F6R2_FB2

    - -
    -
    - - - - -
    #define CAN_F6R2_FB2   CAN_F6R2_FB2_Msk
    -
    -

    Filter bit 2

    - -
    -
    - -

    ◆ CAN_F6R2_FB3_Pos

    - -
    -
    - - - - -
    #define CAN_F6R2_FB3_Pos   (3U)
    -
    - -
    -
    - -

    ◆ CAN_F6R2_FB3_Msk

    - -
    -
    - - - - -
    #define CAN_F6R2_FB3_Msk   (0x1UL << CAN_F6R2_FB3_Pos)
    -
    -

    0x00000008

    - -
    -
    - -

    ◆ CAN_F6R2_FB3

    - -
    -
    - - - - -
    #define CAN_F6R2_FB3   CAN_F6R2_FB3_Msk
    -
    -

    Filter bit 3

    - -
    -
    - -

    ◆ CAN_F6R2_FB4_Pos

    - -
    -
    - - - - -
    #define CAN_F6R2_FB4_Pos   (4U)
    -
    - -
    -
    - -

    ◆ CAN_F6R2_FB4_Msk

    - -
    -
    - - - - -
    #define CAN_F6R2_FB4_Msk   (0x1UL << CAN_F6R2_FB4_Pos)
    -
    -

    0x00000010

    - -
    -
    - -

    ◆ CAN_F6R2_FB4

    - -
    -
    - - - - -
    #define CAN_F6R2_FB4   CAN_F6R2_FB4_Msk
    -
    -

    Filter bit 4

    - -
    -
    - -

    ◆ CAN_F6R2_FB5_Pos

    - -
    -
    - - - - -
    #define CAN_F6R2_FB5_Pos   (5U)
    -
    - -
    -
    - -

    ◆ CAN_F6R2_FB5_Msk

    - -
    -
    - - - - -
    #define CAN_F6R2_FB5_Msk   (0x1UL << CAN_F6R2_FB5_Pos)
    -
    -

    0x00000020

    - -
    -
    - -

    ◆ CAN_F6R2_FB5

    - -
    -
    - - - - -
    #define CAN_F6R2_FB5   CAN_F6R2_FB5_Msk
    -
    -

    Filter bit 5

    - -
    -
    - -

    ◆ CAN_F6R2_FB6_Pos

    - -
    -
    - - - - -
    #define CAN_F6R2_FB6_Pos   (6U)
    -
    - -
    -
    - -

    ◆ CAN_F6R2_FB6_Msk

    - -
    -
    - - - - -
    #define CAN_F6R2_FB6_Msk   (0x1UL << CAN_F6R2_FB6_Pos)
    -
    -

    0x00000040

    - -
    -
    - -

    ◆ CAN_F6R2_FB6

    - -
    -
    - - - - -
    #define CAN_F6R2_FB6   CAN_F6R2_FB6_Msk
    -
    -

    Filter bit 6

    - -
    -
    - -

    ◆ CAN_F6R2_FB7_Pos

    - -
    -
    - - - - -
    #define CAN_F6R2_FB7_Pos   (7U)
    -
    - -
    -
    - -

    ◆ CAN_F6R2_FB7_Msk

    - -
    -
    - - - - -
    #define CAN_F6R2_FB7_Msk   (0x1UL << CAN_F6R2_FB7_Pos)
    -
    -

    0x00000080

    - -
    -
    - -

    ◆ CAN_F6R2_FB7

    - -
    -
    - - - - -
    #define CAN_F6R2_FB7   CAN_F6R2_FB7_Msk
    -
    -

    Filter bit 7

    - -
    -
    - -

    ◆ CAN_F6R2_FB8_Pos

    - -
    -
    - - - - -
    #define CAN_F6R2_FB8_Pos   (8U)
    -
    - -
    -
    - -

    ◆ CAN_F6R2_FB8_Msk

    - -
    -
    - - - - -
    #define CAN_F6R2_FB8_Msk   (0x1UL << CAN_F6R2_FB8_Pos)
    -
    -

    0x00000100

    - -
    -
    - -

    ◆ CAN_F6R2_FB8

    - -
    -
    - - - - -
    #define CAN_F6R2_FB8   CAN_F6R2_FB8_Msk
    -
    -

    Filter bit 8

    - -
    -
    - -

    ◆ CAN_F6R2_FB9_Pos

    - -
    -
    - - - - -
    #define CAN_F6R2_FB9_Pos   (9U)
    -
    - -
    -
    - -

    ◆ CAN_F6R2_FB9_Msk

    - -
    -
    - - - - -
    #define CAN_F6R2_FB9_Msk   (0x1UL << CAN_F6R2_FB9_Pos)
    -
    -

    0x00000200

    - -
    -
    - -

    ◆ CAN_F6R2_FB9

    - -
    -
    - - - - -
    #define CAN_F6R2_FB9   CAN_F6R2_FB9_Msk
    -
    -

    Filter bit 9

    - -
    -
    - -

    ◆ CAN_F6R2_FB10_Pos

    - -
    -
    - - - - -
    #define CAN_F6R2_FB10_Pos   (10U)
    -
    - -
    -
    - -

    ◆ CAN_F6R2_FB10_Msk

    - -
    -
    - - - - -
    #define CAN_F6R2_FB10_Msk   (0x1UL << CAN_F6R2_FB10_Pos)
    -
    -

    0x00000400

    - -
    -
    - -

    ◆ CAN_F6R2_FB10

    - -
    -
    - - - - -
    #define CAN_F6R2_FB10   CAN_F6R2_FB10_Msk
    -
    -

    Filter bit 10

    - -
    -
    - -

    ◆ CAN_F6R2_FB11_Pos

    - -
    -
    - - - - -
    #define CAN_F6R2_FB11_Pos   (11U)
    -
    - -
    -
    - -

    ◆ CAN_F6R2_FB11_Msk

    - -
    -
    - - - - -
    #define CAN_F6R2_FB11_Msk   (0x1UL << CAN_F6R2_FB11_Pos)
    -
    -

    0x00000800

    - -
    -
    - -

    ◆ CAN_F6R2_FB11

    - -
    -
    - - - - -
    #define CAN_F6R2_FB11   CAN_F6R2_FB11_Msk
    -
    -

    Filter bit 11

    - -
    -
    - -

    ◆ CAN_F6R2_FB12_Pos

    - -
    -
    - - - - -
    #define CAN_F6R2_FB12_Pos   (12U)
    -
    - -
    -
    - -

    ◆ CAN_F6R2_FB12_Msk

    - -
    -
    - - - - -
    #define CAN_F6R2_FB12_Msk   (0x1UL << CAN_F6R2_FB12_Pos)
    -
    -

    0x00001000

    - -
    -
    - -

    ◆ CAN_F6R2_FB12

    - -
    -
    - - - - -
    #define CAN_F6R2_FB12   CAN_F6R2_FB12_Msk
    -
    -

    Filter bit 12

    - -
    -
    - -

    ◆ CAN_F6R2_FB13_Pos

    - -
    -
    - - - - -
    #define CAN_F6R2_FB13_Pos   (13U)
    -
    - -
    -
    - -

    ◆ CAN_F6R2_FB13_Msk

    - -
    -
    - - - - -
    #define CAN_F6R2_FB13_Msk   (0x1UL << CAN_F6R2_FB13_Pos)
    -
    -

    0x00002000

    - -
    -
    - -

    ◆ CAN_F6R2_FB13

    - -
    -
    - - - - -
    #define CAN_F6R2_FB13   CAN_F6R2_FB13_Msk
    -
    -

    Filter bit 13

    - -
    -
    - -

    ◆ CAN_F6R2_FB14_Pos

    - -
    -
    - - - - -
    #define CAN_F6R2_FB14_Pos   (14U)
    -
    - -
    -
    - -

    ◆ CAN_F6R2_FB14_Msk

    - -
    -
    - - - - -
    #define CAN_F6R2_FB14_Msk   (0x1UL << CAN_F6R2_FB14_Pos)
    -
    -

    0x00004000

    - -
    -
    - -

    ◆ CAN_F6R2_FB14

    - -
    -
    - - - - -
    #define CAN_F6R2_FB14   CAN_F6R2_FB14_Msk
    -
    -

    Filter bit 14

    - -
    -
    - -

    ◆ CAN_F6R2_FB15_Pos

    - -
    -
    - - - - -
    #define CAN_F6R2_FB15_Pos   (15U)
    -
    - -
    -
    - -

    ◆ CAN_F6R2_FB15_Msk

    - -
    -
    - - - - -
    #define CAN_F6R2_FB15_Msk   (0x1UL << CAN_F6R2_FB15_Pos)
    -
    -

    0x00008000

    - -
    -
    - -

    ◆ CAN_F6R2_FB15

    - -
    -
    - - - - -
    #define CAN_F6R2_FB15   CAN_F6R2_FB15_Msk
    -
    -

    Filter bit 15

    - -
    -
    - -

    ◆ CAN_F6R2_FB16_Pos

    - -
    -
    - - - - -
    #define CAN_F6R2_FB16_Pos   (16U)
    -
    - -
    -
    - -

    ◆ CAN_F6R2_FB16_Msk

    - -
    -
    - - - - -
    #define CAN_F6R2_FB16_Msk   (0x1UL << CAN_F6R2_FB16_Pos)
    -
    -

    0x00010000

    - -
    -
    - -

    ◆ CAN_F6R2_FB16

    - -
    -
    - - - - -
    #define CAN_F6R2_FB16   CAN_F6R2_FB16_Msk
    -
    -

    Filter bit 16

    - -
    -
    - -

    ◆ CAN_F6R2_FB17_Pos

    - -
    -
    - - - - -
    #define CAN_F6R2_FB17_Pos   (17U)
    -
    - -
    -
    - -

    ◆ CAN_F6R2_FB17_Msk

    - -
    -
    - - - - -
    #define CAN_F6R2_FB17_Msk   (0x1UL << CAN_F6R2_FB17_Pos)
    -
    -

    0x00020000

    - -
    -
    - -

    ◆ CAN_F6R2_FB17

    - -
    -
    - - - - -
    #define CAN_F6R2_FB17   CAN_F6R2_FB17_Msk
    -
    -

    Filter bit 17

    - -
    -
    - -

    ◆ CAN_F6R2_FB18_Pos

    - -
    -
    - - - - -
    #define CAN_F6R2_FB18_Pos   (18U)
    -
    - -
    -
    - -

    ◆ CAN_F6R2_FB18_Msk

    - -
    -
    - - - - -
    #define CAN_F6R2_FB18_Msk   (0x1UL << CAN_F6R2_FB18_Pos)
    -
    -

    0x00040000

    - -
    -
    - -

    ◆ CAN_F6R2_FB18

    - -
    -
    - - - - -
    #define CAN_F6R2_FB18   CAN_F6R2_FB18_Msk
    -
    -

    Filter bit 18

    - -
    -
    - -

    ◆ CAN_F6R2_FB19_Pos

    - -
    -
    - - - - -
    #define CAN_F6R2_FB19_Pos   (19U)
    -
    - -
    -
    - -

    ◆ CAN_F6R2_FB19_Msk

    - -
    -
    - - - - -
    #define CAN_F6R2_FB19_Msk   (0x1UL << CAN_F6R2_FB19_Pos)
    -
    -

    0x00080000

    - -
    -
    - -

    ◆ CAN_F6R2_FB19

    - -
    -
    - - - - -
    #define CAN_F6R2_FB19   CAN_F6R2_FB19_Msk
    -
    -

    Filter bit 19

    - -
    -
    - -

    ◆ CAN_F6R2_FB20_Pos

    - -
    -
    - - - - -
    #define CAN_F6R2_FB20_Pos   (20U)
    -
    - -
    -
    - -

    ◆ CAN_F6R2_FB20_Msk

    - -
    -
    - - - - -
    #define CAN_F6R2_FB20_Msk   (0x1UL << CAN_F6R2_FB20_Pos)
    -
    -

    0x00100000

    - -
    -
    - -

    ◆ CAN_F6R2_FB20

    - -
    -
    - - - - -
    #define CAN_F6R2_FB20   CAN_F6R2_FB20_Msk
    -
    -

    Filter bit 20

    - -
    -
    - -

    ◆ CAN_F6R2_FB21_Pos

    - -
    -
    - - - - -
    #define CAN_F6R2_FB21_Pos   (21U)
    -
    - -
    -
    - -

    ◆ CAN_F6R2_FB21_Msk

    - -
    -
    - - - - -
    #define CAN_F6R2_FB21_Msk   (0x1UL << CAN_F6R2_FB21_Pos)
    -
    -

    0x00200000

    - -
    -
    - -

    ◆ CAN_F6R2_FB21

    - -
    -
    - - - - -
    #define CAN_F6R2_FB21   CAN_F6R2_FB21_Msk
    -
    -

    Filter bit 21

    - -
    -
    - -

    ◆ CAN_F6R2_FB22_Pos

    - -
    -
    - - - - -
    #define CAN_F6R2_FB22_Pos   (22U)
    -
    - -
    -
    - -

    ◆ CAN_F6R2_FB22_Msk

    - -
    -
    - - - - -
    #define CAN_F6R2_FB22_Msk   (0x1UL << CAN_F6R2_FB22_Pos)
    -
    -

    0x00400000

    - -
    -
    - -

    ◆ CAN_F6R2_FB22

    - -
    -
    - - - - -
    #define CAN_F6R2_FB22   CAN_F6R2_FB22_Msk
    -
    -

    Filter bit 22

    - -
    -
    - -

    ◆ CAN_F6R2_FB23_Pos

    - -
    -
    - - - - -
    #define CAN_F6R2_FB23_Pos   (23U)
    -
    - -
    -
    - -

    ◆ CAN_F6R2_FB23_Msk

    - -
    -
    - - - - -
    #define CAN_F6R2_FB23_Msk   (0x1UL << CAN_F6R2_FB23_Pos)
    -
    -

    0x00800000

    - -
    -
    - -

    ◆ CAN_F6R2_FB23

    - -
    -
    - - - - -
    #define CAN_F6R2_FB23   CAN_F6R2_FB23_Msk
    -
    -

    Filter bit 23

    - -
    -
    - -

    ◆ CAN_F6R2_FB24_Pos

    - -
    -
    - - - - -
    #define CAN_F6R2_FB24_Pos   (24U)
    -
    - -
    -
    - -

    ◆ CAN_F6R2_FB24_Msk

    - -
    -
    - - - - -
    #define CAN_F6R2_FB24_Msk   (0x1UL << CAN_F6R2_FB24_Pos)
    -
    -

    0x01000000

    - -
    -
    - -

    ◆ CAN_F6R2_FB24

    - -
    -
    - - - - -
    #define CAN_F6R2_FB24   CAN_F6R2_FB24_Msk
    -
    -

    Filter bit 24

    - -
    -
    - -

    ◆ CAN_F6R2_FB25_Pos

    - -
    -
    - - - - -
    #define CAN_F6R2_FB25_Pos   (25U)
    -
    - -
    -
    - -

    ◆ CAN_F6R2_FB25_Msk

    - -
    -
    - - - - -
    #define CAN_F6R2_FB25_Msk   (0x1UL << CAN_F6R2_FB25_Pos)
    -
    -

    0x02000000

    - -
    -
    - -

    ◆ CAN_F6R2_FB25

    - -
    -
    - - - - -
    #define CAN_F6R2_FB25   CAN_F6R2_FB25_Msk
    -
    -

    Filter bit 25

    - -
    -
    - -

    ◆ CAN_F6R2_FB26_Pos

    - -
    -
    - - - - -
    #define CAN_F6R2_FB26_Pos   (26U)
    -
    - -
    -
    - -

    ◆ CAN_F6R2_FB26_Msk

    - -
    -
    - - - - -
    #define CAN_F6R2_FB26_Msk   (0x1UL << CAN_F6R2_FB26_Pos)
    -
    -

    0x04000000

    - -
    -
    - -

    ◆ CAN_F6R2_FB26

    - -
    -
    - - - - -
    #define CAN_F6R2_FB26   CAN_F6R2_FB26_Msk
    -
    -

    Filter bit 26

    - -
    -
    - -

    ◆ CAN_F6R2_FB27_Pos

    - -
    -
    - - - - -
    #define CAN_F6R2_FB27_Pos   (27U)
    -
    - -
    -
    - -

    ◆ CAN_F6R2_FB27_Msk

    - -
    -
    - - - - -
    #define CAN_F6R2_FB27_Msk   (0x1UL << CAN_F6R2_FB27_Pos)
    -
    -

    0x08000000

    - -
    -
    - -

    ◆ CAN_F6R2_FB27

    - -
    -
    - - - - -
    #define CAN_F6R2_FB27   CAN_F6R2_FB27_Msk
    -
    -

    Filter bit 27

    - -
    -
    - -

    ◆ CAN_F6R2_FB28_Pos

    - -
    -
    - - - - -
    #define CAN_F6R2_FB28_Pos   (28U)
    -
    - -
    -
    - -

    ◆ CAN_F6R2_FB28_Msk

    - -
    -
    - - - - -
    #define CAN_F6R2_FB28_Msk   (0x1UL << CAN_F6R2_FB28_Pos)
    -
    -

    0x10000000

    - -
    -
    - -

    ◆ CAN_F6R2_FB28

    - -
    -
    - - - - -
    #define CAN_F6R2_FB28   CAN_F6R2_FB28_Msk
    -
    -

    Filter bit 28

    - -
    -
    - -

    ◆ CAN_F6R2_FB29_Pos

    - -
    -
    - - - - -
    #define CAN_F6R2_FB29_Pos   (29U)
    -
    - -
    -
    - -

    ◆ CAN_F6R2_FB29_Msk

    - -
    -
    - - - - -
    #define CAN_F6R2_FB29_Msk   (0x1UL << CAN_F6R2_FB29_Pos)
    -
    -

    0x20000000

    - -
    -
    - -

    ◆ CAN_F6R2_FB29

    - -
    -
    - - - - -
    #define CAN_F6R2_FB29   CAN_F6R2_FB29_Msk
    -
    -

    Filter bit 29

    - -
    -
    - -

    ◆ CAN_F6R2_FB30_Pos

    - -
    -
    - - - - -
    #define CAN_F6R2_FB30_Pos   (30U)
    -
    - -
    -
    - -

    ◆ CAN_F6R2_FB30_Msk

    - -
    -
    - - - - -
    #define CAN_F6R2_FB30_Msk   (0x1UL << CAN_F6R2_FB30_Pos)
    -
    -

    0x40000000

    - -
    -
    - -

    ◆ CAN_F6R2_FB30

    - -
    -
    - - - - -
    #define CAN_F6R2_FB30   CAN_F6R2_FB30_Msk
    -
    -

    Filter bit 30

    - -
    -
    - -

    ◆ CAN_F6R2_FB31_Pos

    - -
    -
    - - - - -
    #define CAN_F6R2_FB31_Pos   (31U)
    -
    - -
    -
    - -

    ◆ CAN_F6R2_FB31_Msk

    - -
    -
    - - - - -
    #define CAN_F6R2_FB31_Msk   (0x1UL << CAN_F6R2_FB31_Pos)
    -
    -

    0x80000000

    - -
    -
    - -

    ◆ CAN_F6R2_FB31

    - -
    -
    - - - - -
    #define CAN_F6R2_FB31   CAN_F6R2_FB31_Msk
    -
    -

    Filter bit 31

    - -
    -
    - -

    ◆ CAN_F7R2_FB0_Pos

    - -
    -
    - - - - -
    #define CAN_F7R2_FB0_Pos   (0U)
    -
    - -
    -
    - -

    ◆ CAN_F7R2_FB0_Msk

    - -
    -
    - - - - -
    #define CAN_F7R2_FB0_Msk   (0x1UL << CAN_F7R2_FB0_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ CAN_F7R2_FB0

    - -
    -
    - - - - -
    #define CAN_F7R2_FB0   CAN_F7R2_FB0_Msk
    -
    -

    Filter bit 0

    - -
    -
    - -

    ◆ CAN_F7R2_FB1_Pos

    - -
    -
    - - - - -
    #define CAN_F7R2_FB1_Pos   (1U)
    -
    - -
    -
    - -

    ◆ CAN_F7R2_FB1_Msk

    - -
    -
    - - - - -
    #define CAN_F7R2_FB1_Msk   (0x1UL << CAN_F7R2_FB1_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ CAN_F7R2_FB1

    - -
    -
    - - - - -
    #define CAN_F7R2_FB1   CAN_F7R2_FB1_Msk
    -
    -

    Filter bit 1

    - -
    -
    - -

    ◆ CAN_F7R2_FB2_Pos

    - -
    -
    - - - - -
    #define CAN_F7R2_FB2_Pos   (2U)
    -
    - -
    -
    - -

    ◆ CAN_F7R2_FB2_Msk

    - -
    -
    - - - - -
    #define CAN_F7R2_FB2_Msk   (0x1UL << CAN_F7R2_FB2_Pos)
    -
    -

    0x00000004

    - -
    -
    - -

    ◆ CAN_F7R2_FB2

    - -
    -
    - - - - -
    #define CAN_F7R2_FB2   CAN_F7R2_FB2_Msk
    -
    -

    Filter bit 2

    - -
    -
    - -

    ◆ CAN_F7R2_FB3_Pos

    - -
    -
    - - - - -
    #define CAN_F7R2_FB3_Pos   (3U)
    -
    - -
    -
    - -

    ◆ CAN_F7R2_FB3_Msk

    - -
    -
    - - - - -
    #define CAN_F7R2_FB3_Msk   (0x1UL << CAN_F7R2_FB3_Pos)
    -
    -

    0x00000008

    - -
    -
    - -

    ◆ CAN_F7R2_FB3

    - -
    -
    - - - - -
    #define CAN_F7R2_FB3   CAN_F7R2_FB3_Msk
    -
    -

    Filter bit 3

    - -
    -
    - -

    ◆ CAN_F7R2_FB4_Pos

    - -
    -
    - - - - -
    #define CAN_F7R2_FB4_Pos   (4U)
    -
    - -
    -
    - -

    ◆ CAN_F7R2_FB4_Msk

    - -
    -
    - - - - -
    #define CAN_F7R2_FB4_Msk   (0x1UL << CAN_F7R2_FB4_Pos)
    -
    -

    0x00000010

    - -
    -
    - -

    ◆ CAN_F7R2_FB4

    - -
    -
    - - - - -
    #define CAN_F7R2_FB4   CAN_F7R2_FB4_Msk
    -
    -

    Filter bit 4

    - -
    -
    - -

    ◆ CAN_F7R2_FB5_Pos

    - -
    -
    - - - - -
    #define CAN_F7R2_FB5_Pos   (5U)
    -
    - -
    -
    - -

    ◆ CAN_F7R2_FB5_Msk

    - -
    -
    - - - - -
    #define CAN_F7R2_FB5_Msk   (0x1UL << CAN_F7R2_FB5_Pos)
    -
    -

    0x00000020

    - -
    -
    - -

    ◆ CAN_F7R2_FB5

    - -
    -
    - - - - -
    #define CAN_F7R2_FB5   CAN_F7R2_FB5_Msk
    -
    -

    Filter bit 5

    - -
    -
    - -

    ◆ CAN_F7R2_FB6_Pos

    - -
    -
    - - - - -
    #define CAN_F7R2_FB6_Pos   (6U)
    -
    - -
    -
    - -

    ◆ CAN_F7R2_FB6_Msk

    - -
    -
    - - - - -
    #define CAN_F7R2_FB6_Msk   (0x1UL << CAN_F7R2_FB6_Pos)
    -
    -

    0x00000040

    - -
    -
    - -

    ◆ CAN_F7R2_FB6

    - -
    -
    - - - - -
    #define CAN_F7R2_FB6   CAN_F7R2_FB6_Msk
    -
    -

    Filter bit 6

    - -
    -
    - -

    ◆ CAN_F7R2_FB7_Pos

    - -
    -
    - - - - -
    #define CAN_F7R2_FB7_Pos   (7U)
    -
    - -
    -
    - -

    ◆ CAN_F7R2_FB7_Msk

    - -
    -
    - - - - -
    #define CAN_F7R2_FB7_Msk   (0x1UL << CAN_F7R2_FB7_Pos)
    -
    -

    0x00000080

    - -
    -
    - -

    ◆ CAN_F7R2_FB7

    - -
    -
    - - - - -
    #define CAN_F7R2_FB7   CAN_F7R2_FB7_Msk
    -
    -

    Filter bit 7

    - -
    -
    - -

    ◆ CAN_F7R2_FB8_Pos

    - -
    -
    - - - - -
    #define CAN_F7R2_FB8_Pos   (8U)
    -
    - -
    -
    - -

    ◆ CAN_F7R2_FB8_Msk

    - -
    -
    - - - - -
    #define CAN_F7R2_FB8_Msk   (0x1UL << CAN_F7R2_FB8_Pos)
    -
    -

    0x00000100

    - -
    -
    - -

    ◆ CAN_F7R2_FB8

    - -
    -
    - - - - -
    #define CAN_F7R2_FB8   CAN_F7R2_FB8_Msk
    -
    -

    Filter bit 8

    - -
    -
    - -

    ◆ CAN_F7R2_FB9_Pos

    - -
    -
    - - - - -
    #define CAN_F7R2_FB9_Pos   (9U)
    -
    - -
    -
    - -

    ◆ CAN_F7R2_FB9_Msk

    - -
    -
    - - - - -
    #define CAN_F7R2_FB9_Msk   (0x1UL << CAN_F7R2_FB9_Pos)
    -
    -

    0x00000200

    - -
    -
    - -

    ◆ CAN_F7R2_FB9

    - -
    -
    - - - - -
    #define CAN_F7R2_FB9   CAN_F7R2_FB9_Msk
    -
    -

    Filter bit 9

    - -
    -
    - -

    ◆ CAN_F7R2_FB10_Pos

    - -
    -
    - - - - -
    #define CAN_F7R2_FB10_Pos   (10U)
    -
    - -
    -
    - -

    ◆ CAN_F7R2_FB10_Msk

    - -
    -
    - - - - -
    #define CAN_F7R2_FB10_Msk   (0x1UL << CAN_F7R2_FB10_Pos)
    -
    -

    0x00000400

    - -
    -
    - -

    ◆ CAN_F7R2_FB10

    - -
    -
    - - - - -
    #define CAN_F7R2_FB10   CAN_F7R2_FB10_Msk
    -
    -

    Filter bit 10

    - -
    -
    - -

    ◆ CAN_F7R2_FB11_Pos

    - -
    -
    - - - - -
    #define CAN_F7R2_FB11_Pos   (11U)
    -
    - -
    -
    - -

    ◆ CAN_F7R2_FB11_Msk

    - -
    -
    - - - - -
    #define CAN_F7R2_FB11_Msk   (0x1UL << CAN_F7R2_FB11_Pos)
    -
    -

    0x00000800

    - -
    -
    - -

    ◆ CAN_F7R2_FB11

    - -
    -
    - - - - -
    #define CAN_F7R2_FB11   CAN_F7R2_FB11_Msk
    -
    -

    Filter bit 11

    - -
    -
    - -

    ◆ CAN_F7R2_FB12_Pos

    - -
    -
    - - - - -
    #define CAN_F7R2_FB12_Pos   (12U)
    -
    - -
    -
    - -

    ◆ CAN_F7R2_FB12_Msk

    - -
    -
    - - - - -
    #define CAN_F7R2_FB12_Msk   (0x1UL << CAN_F7R2_FB12_Pos)
    -
    -

    0x00001000

    - -
    -
    - -

    ◆ CAN_F7R2_FB12

    - -
    -
    - - - - -
    #define CAN_F7R2_FB12   CAN_F7R2_FB12_Msk
    -
    -

    Filter bit 12

    - -
    -
    - -

    ◆ CAN_F7R2_FB13_Pos

    - -
    -
    - - - - -
    #define CAN_F7R2_FB13_Pos   (13U)
    -
    - -
    -
    - -

    ◆ CAN_F7R2_FB13_Msk

    - -
    -
    - - - - -
    #define CAN_F7R2_FB13_Msk   (0x1UL << CAN_F7R2_FB13_Pos)
    -
    -

    0x00002000

    - -
    -
    - -

    ◆ CAN_F7R2_FB13

    - -
    -
    - - - - -
    #define CAN_F7R2_FB13   CAN_F7R2_FB13_Msk
    -
    -

    Filter bit 13

    - -
    -
    - -

    ◆ CAN_F7R2_FB14_Pos

    - -
    -
    - - - - -
    #define CAN_F7R2_FB14_Pos   (14U)
    -
    - -
    -
    - -

    ◆ CAN_F7R2_FB14_Msk

    - -
    -
    - - - - -
    #define CAN_F7R2_FB14_Msk   (0x1UL << CAN_F7R2_FB14_Pos)
    -
    -

    0x00004000

    - -
    -
    - -

    ◆ CAN_F7R2_FB14

    - -
    -
    - - - - -
    #define CAN_F7R2_FB14   CAN_F7R2_FB14_Msk
    -
    -

    Filter bit 14

    - -
    -
    - -

    ◆ CAN_F7R2_FB15_Pos

    - -
    -
    - - - - -
    #define CAN_F7R2_FB15_Pos   (15U)
    -
    - -
    -
    - -

    ◆ CAN_F7R2_FB15_Msk

    - -
    -
    - - - - -
    #define CAN_F7R2_FB15_Msk   (0x1UL << CAN_F7R2_FB15_Pos)
    -
    -

    0x00008000

    - -
    -
    - -

    ◆ CAN_F7R2_FB15

    - -
    -
    - - - - -
    #define CAN_F7R2_FB15   CAN_F7R2_FB15_Msk
    -
    -

    Filter bit 15

    - -
    -
    - -

    ◆ CAN_F7R2_FB16_Pos

    - -
    -
    - - - - -
    #define CAN_F7R2_FB16_Pos   (16U)
    -
    - -
    -
    - -

    ◆ CAN_F7R2_FB16_Msk

    - -
    -
    - - - - -
    #define CAN_F7R2_FB16_Msk   (0x1UL << CAN_F7R2_FB16_Pos)
    -
    -

    0x00010000

    - -
    -
    - -

    ◆ CAN_F7R2_FB16

    - -
    -
    - - - - -
    #define CAN_F7R2_FB16   CAN_F7R2_FB16_Msk
    -
    -

    Filter bit 16

    - -
    -
    - -

    ◆ CAN_F7R2_FB17_Pos

    - -
    -
    - - - - -
    #define CAN_F7R2_FB17_Pos   (17U)
    -
    - -
    -
    - -

    ◆ CAN_F7R2_FB17_Msk

    - -
    -
    - - - - -
    #define CAN_F7R2_FB17_Msk   (0x1UL << CAN_F7R2_FB17_Pos)
    -
    -

    0x00020000

    - -
    -
    - -

    ◆ CAN_F7R2_FB17

    - -
    -
    - - - - -
    #define CAN_F7R2_FB17   CAN_F7R2_FB17_Msk
    -
    -

    Filter bit 17

    - -
    -
    - -

    ◆ CAN_F7R2_FB18_Pos

    - -
    -
    - - - - -
    #define CAN_F7R2_FB18_Pos   (18U)
    -
    - -
    -
    - -

    ◆ CAN_F7R2_FB18_Msk

    - -
    -
    - - - - -
    #define CAN_F7R2_FB18_Msk   (0x1UL << CAN_F7R2_FB18_Pos)
    -
    -

    0x00040000

    - -
    -
    - -

    ◆ CAN_F7R2_FB18

    - -
    -
    - - - - -
    #define CAN_F7R2_FB18   CAN_F7R2_FB18_Msk
    -
    -

    Filter bit 18

    - -
    -
    - -

    ◆ CAN_F7R2_FB19_Pos

    - -
    -
    - - - - -
    #define CAN_F7R2_FB19_Pos   (19U)
    -
    - -
    -
    - -

    ◆ CAN_F7R2_FB19_Msk

    - -
    -
    - - - - -
    #define CAN_F7R2_FB19_Msk   (0x1UL << CAN_F7R2_FB19_Pos)
    -
    -

    0x00080000

    - -
    -
    - -

    ◆ CAN_F7R2_FB19

    - -
    -
    - - - - -
    #define CAN_F7R2_FB19   CAN_F7R2_FB19_Msk
    -
    -

    Filter bit 19

    - -
    -
    - -

    ◆ CAN_F7R2_FB20_Pos

    - -
    -
    - - - - -
    #define CAN_F7R2_FB20_Pos   (20U)
    -
    - -
    -
    - -

    ◆ CAN_F7R2_FB20_Msk

    - -
    -
    - - - - -
    #define CAN_F7R2_FB20_Msk   (0x1UL << CAN_F7R2_FB20_Pos)
    -
    -

    0x00100000

    - -
    -
    - -

    ◆ CAN_F7R2_FB20

    - -
    -
    - - - - -
    #define CAN_F7R2_FB20   CAN_F7R2_FB20_Msk
    -
    -

    Filter bit 20

    - -
    -
    - -

    ◆ CAN_F7R2_FB21_Pos

    - -
    -
    - - - - -
    #define CAN_F7R2_FB21_Pos   (21U)
    -
    - -
    -
    - -

    ◆ CAN_F7R2_FB21_Msk

    - -
    -
    - - - - -
    #define CAN_F7R2_FB21_Msk   (0x1UL << CAN_F7R2_FB21_Pos)
    -
    -

    0x00200000

    - -
    -
    - -

    ◆ CAN_F7R2_FB21

    - -
    -
    - - - - -
    #define CAN_F7R2_FB21   CAN_F7R2_FB21_Msk
    -
    -

    Filter bit 21

    - -
    -
    - -

    ◆ CAN_F7R2_FB22_Pos

    - -
    -
    - - - - -
    #define CAN_F7R2_FB22_Pos   (22U)
    -
    - -
    -
    - -

    ◆ CAN_F7R2_FB22_Msk

    - -
    -
    - - - - -
    #define CAN_F7R2_FB22_Msk   (0x1UL << CAN_F7R2_FB22_Pos)
    -
    -

    0x00400000

    - -
    -
    - -

    ◆ CAN_F7R2_FB22

    - -
    -
    - - - - -
    #define CAN_F7R2_FB22   CAN_F7R2_FB22_Msk
    -
    -

    Filter bit 22

    - -
    -
    - -

    ◆ CAN_F7R2_FB23_Pos

    - -
    -
    - - - - -
    #define CAN_F7R2_FB23_Pos   (23U)
    -
    - -
    -
    - -

    ◆ CAN_F7R2_FB23_Msk

    - -
    -
    - - - - -
    #define CAN_F7R2_FB23_Msk   (0x1UL << CAN_F7R2_FB23_Pos)
    -
    -

    0x00800000

    - -
    -
    - -

    ◆ CAN_F7R2_FB23

    - -
    -
    - - - - -
    #define CAN_F7R2_FB23   CAN_F7R2_FB23_Msk
    -
    -

    Filter bit 23

    - -
    -
    - -

    ◆ CAN_F7R2_FB24_Pos

    - -
    -
    - - - - -
    #define CAN_F7R2_FB24_Pos   (24U)
    -
    - -
    -
    - -

    ◆ CAN_F7R2_FB24_Msk

    - -
    -
    - - - - -
    #define CAN_F7R2_FB24_Msk   (0x1UL << CAN_F7R2_FB24_Pos)
    -
    -

    0x01000000

    - -
    -
    - -

    ◆ CAN_F7R2_FB24

    - -
    -
    - - - - -
    #define CAN_F7R2_FB24   CAN_F7R2_FB24_Msk
    -
    -

    Filter bit 24

    - -
    -
    - -

    ◆ CAN_F7R2_FB25_Pos

    - -
    -
    - - - - -
    #define CAN_F7R2_FB25_Pos   (25U)
    -
    - -
    -
    - -

    ◆ CAN_F7R2_FB25_Msk

    - -
    -
    - - - - -
    #define CAN_F7R2_FB25_Msk   (0x1UL << CAN_F7R2_FB25_Pos)
    -
    -

    0x02000000

    - -
    -
    - -

    ◆ CAN_F7R2_FB25

    - -
    -
    - - - - -
    #define CAN_F7R2_FB25   CAN_F7R2_FB25_Msk
    -
    -

    Filter bit 25

    - -
    -
    - -

    ◆ CAN_F7R2_FB26_Pos

    - -
    -
    - - - - -
    #define CAN_F7R2_FB26_Pos   (26U)
    -
    - -
    -
    - -

    ◆ CAN_F7R2_FB26_Msk

    - -
    -
    - - - - -
    #define CAN_F7R2_FB26_Msk   (0x1UL << CAN_F7R2_FB26_Pos)
    -
    -

    0x04000000

    - -
    -
    - -

    ◆ CAN_F7R2_FB26

    - -
    -
    - - - - -
    #define CAN_F7R2_FB26   CAN_F7R2_FB26_Msk
    -
    -

    Filter bit 26

    - -
    -
    - -

    ◆ CAN_F7R2_FB27_Pos

    - -
    -
    - - - - -
    #define CAN_F7R2_FB27_Pos   (27U)
    -
    - -
    -
    - -

    ◆ CAN_F7R2_FB27_Msk

    - -
    -
    - - - - -
    #define CAN_F7R2_FB27_Msk   (0x1UL << CAN_F7R2_FB27_Pos)
    -
    -

    0x08000000

    - -
    -
    - -

    ◆ CAN_F7R2_FB27

    - -
    -
    - - - - -
    #define CAN_F7R2_FB27   CAN_F7R2_FB27_Msk
    -
    -

    Filter bit 27

    - -
    -
    - -

    ◆ CAN_F7R2_FB28_Pos

    - -
    -
    - - - - -
    #define CAN_F7R2_FB28_Pos   (28U)
    -
    - -
    -
    - -

    ◆ CAN_F7R2_FB28_Msk

    - -
    -
    - - - - -
    #define CAN_F7R2_FB28_Msk   (0x1UL << CAN_F7R2_FB28_Pos)
    -
    -

    0x10000000

    - -
    -
    - -

    ◆ CAN_F7R2_FB28

    - -
    -
    - - - - -
    #define CAN_F7R2_FB28   CAN_F7R2_FB28_Msk
    -
    -

    Filter bit 28

    - -
    -
    - -

    ◆ CAN_F7R2_FB29_Pos

    - -
    -
    - - - - -
    #define CAN_F7R2_FB29_Pos   (29U)
    -
    - -
    -
    - -

    ◆ CAN_F7R2_FB29_Msk

    - -
    -
    - - - - -
    #define CAN_F7R2_FB29_Msk   (0x1UL << CAN_F7R2_FB29_Pos)
    -
    -

    0x20000000

    - -
    -
    - -

    ◆ CAN_F7R2_FB29

    - -
    -
    - - - - -
    #define CAN_F7R2_FB29   CAN_F7R2_FB29_Msk
    -
    -

    Filter bit 29

    - -
    -
    - -

    ◆ CAN_F7R2_FB30_Pos

    - -
    -
    - - - - -
    #define CAN_F7R2_FB30_Pos   (30U)
    -
    - -
    -
    - -

    ◆ CAN_F7R2_FB30_Msk

    - -
    -
    - - - - -
    #define CAN_F7R2_FB30_Msk   (0x1UL << CAN_F7R2_FB30_Pos)
    -
    -

    0x40000000

    - -
    -
    - -

    ◆ CAN_F7R2_FB30

    - -
    -
    - - - - -
    #define CAN_F7R2_FB30   CAN_F7R2_FB30_Msk
    -
    -

    Filter bit 30

    - -
    -
    - -

    ◆ CAN_F7R2_FB31_Pos

    - -
    -
    - - - - -
    #define CAN_F7R2_FB31_Pos   (31U)
    -
    - -
    -
    - -

    ◆ CAN_F7R2_FB31_Msk

    - -
    -
    - - - - -
    #define CAN_F7R2_FB31_Msk   (0x1UL << CAN_F7R2_FB31_Pos)
    -
    -

    0x80000000

    - -
    -
    - -

    ◆ CAN_F7R2_FB31

    - -
    -
    - - - - -
    #define CAN_F7R2_FB31   CAN_F7R2_FB31_Msk
    -
    -

    Filter bit 31

    - -
    -
    - -

    ◆ CAN_F8R2_FB0_Pos

    - -
    -
    - - - - -
    #define CAN_F8R2_FB0_Pos   (0U)
    -
    - -
    -
    - -

    ◆ CAN_F8R2_FB0_Msk

    - -
    -
    - - - - -
    #define CAN_F8R2_FB0_Msk   (0x1UL << CAN_F8R2_FB0_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ CAN_F8R2_FB0

    - -
    -
    - - - - -
    #define CAN_F8R2_FB0   CAN_F8R2_FB0_Msk
    -
    -

    Filter bit 0

    - -
    -
    - -

    ◆ CAN_F8R2_FB1_Pos

    - -
    -
    - - - - -
    #define CAN_F8R2_FB1_Pos   (1U)
    -
    - -
    -
    - -

    ◆ CAN_F8R2_FB1_Msk

    - -
    -
    - - - - -
    #define CAN_F8R2_FB1_Msk   (0x1UL << CAN_F8R2_FB1_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ CAN_F8R2_FB1

    - -
    -
    - - - - -
    #define CAN_F8R2_FB1   CAN_F8R2_FB1_Msk
    -
    -

    Filter bit 1

    - -
    -
    - -

    ◆ CAN_F8R2_FB2_Pos

    - -
    -
    - - - - -
    #define CAN_F8R2_FB2_Pos   (2U)
    -
    - -
    -
    - -

    ◆ CAN_F8R2_FB2_Msk

    - -
    -
    - - - - -
    #define CAN_F8R2_FB2_Msk   (0x1UL << CAN_F8R2_FB2_Pos)
    -
    -

    0x00000004

    - -
    -
    - -

    ◆ CAN_F8R2_FB2

    - -
    -
    - - - - -
    #define CAN_F8R2_FB2   CAN_F8R2_FB2_Msk
    -
    -

    Filter bit 2

    - -
    -
    - -

    ◆ CAN_F8R2_FB3_Pos

    - -
    -
    - - - - -
    #define CAN_F8R2_FB3_Pos   (3U)
    -
    - -
    -
    - -

    ◆ CAN_F8R2_FB3_Msk

    - -
    -
    - - - - -
    #define CAN_F8R2_FB3_Msk   (0x1UL << CAN_F8R2_FB3_Pos)
    -
    -

    0x00000008

    - -
    -
    - -

    ◆ CAN_F8R2_FB3

    - -
    -
    - - - - -
    #define CAN_F8R2_FB3   CAN_F8R2_FB3_Msk
    -
    -

    Filter bit 3

    - -
    -
    - -

    ◆ CAN_F8R2_FB4_Pos

    - -
    -
    - - - - -
    #define CAN_F8R2_FB4_Pos   (4U)
    -
    - -
    -
    - -

    ◆ CAN_F8R2_FB4_Msk

    - -
    -
    - - - - -
    #define CAN_F8R2_FB4_Msk   (0x1UL << CAN_F8R2_FB4_Pos)
    -
    -

    0x00000010

    - -
    -
    - -

    ◆ CAN_F8R2_FB4

    - -
    -
    - - - - -
    #define CAN_F8R2_FB4   CAN_F8R2_FB4_Msk
    -
    -

    Filter bit 4

    - -
    -
    - -

    ◆ CAN_F8R2_FB5_Pos

    - -
    -
    - - - - -
    #define CAN_F8R2_FB5_Pos   (5U)
    -
    - -
    -
    - -

    ◆ CAN_F8R2_FB5_Msk

    - -
    -
    - - - - -
    #define CAN_F8R2_FB5_Msk   (0x1UL << CAN_F8R2_FB5_Pos)
    -
    -

    0x00000020

    - -
    -
    - -

    ◆ CAN_F8R2_FB5

    - -
    -
    - - - - -
    #define CAN_F8R2_FB5   CAN_F8R2_FB5_Msk
    -
    -

    Filter bit 5

    - -
    -
    - -

    ◆ CAN_F8R2_FB6_Pos

    - -
    -
    - - - - -
    #define CAN_F8R2_FB6_Pos   (6U)
    -
    - -
    -
    - -

    ◆ CAN_F8R2_FB6_Msk

    - -
    -
    - - - - -
    #define CAN_F8R2_FB6_Msk   (0x1UL << CAN_F8R2_FB6_Pos)
    -
    -

    0x00000040

    - -
    -
    - -

    ◆ CAN_F8R2_FB6

    - -
    -
    - - - - -
    #define CAN_F8R2_FB6   CAN_F8R2_FB6_Msk
    -
    -

    Filter bit 6

    - -
    -
    - -

    ◆ CAN_F8R2_FB7_Pos

    - -
    -
    - - - - -
    #define CAN_F8R2_FB7_Pos   (7U)
    -
    - -
    -
    - -

    ◆ CAN_F8R2_FB7_Msk

    - -
    -
    - - - - -
    #define CAN_F8R2_FB7_Msk   (0x1UL << CAN_F8R2_FB7_Pos)
    -
    -

    0x00000080

    - -
    -
    - -

    ◆ CAN_F8R2_FB7

    - -
    -
    - - - - -
    #define CAN_F8R2_FB7   CAN_F8R2_FB7_Msk
    -
    -

    Filter bit 7

    - -
    -
    - -

    ◆ CAN_F8R2_FB8_Pos

    - -
    -
    - - - - -
    #define CAN_F8R2_FB8_Pos   (8U)
    -
    - -
    -
    - -

    ◆ CAN_F8R2_FB8_Msk

    - -
    -
    - - - - -
    #define CAN_F8R2_FB8_Msk   (0x1UL << CAN_F8R2_FB8_Pos)
    -
    -

    0x00000100

    - -
    -
    - -

    ◆ CAN_F8R2_FB8

    - -
    -
    - - - - -
    #define CAN_F8R2_FB8   CAN_F8R2_FB8_Msk
    -
    -

    Filter bit 8

    - -
    -
    - -

    ◆ CAN_F8R2_FB9_Pos

    - -
    -
    - - - - -
    #define CAN_F8R2_FB9_Pos   (9U)
    -
    - -
    -
    - -

    ◆ CAN_F8R2_FB9_Msk

    - -
    -
    - - - - -
    #define CAN_F8R2_FB9_Msk   (0x1UL << CAN_F8R2_FB9_Pos)
    -
    -

    0x00000200

    - -
    -
    - -

    ◆ CAN_F8R2_FB9

    - -
    -
    - - - - -
    #define CAN_F8R2_FB9   CAN_F8R2_FB9_Msk
    -
    -

    Filter bit 9

    - -
    -
    - -

    ◆ CAN_F8R2_FB10_Pos

    - -
    -
    - - - - -
    #define CAN_F8R2_FB10_Pos   (10U)
    -
    - -
    -
    - -

    ◆ CAN_F8R2_FB10_Msk

    - -
    -
    - - - - -
    #define CAN_F8R2_FB10_Msk   (0x1UL << CAN_F8R2_FB10_Pos)
    -
    -

    0x00000400

    - -
    -
    - -

    ◆ CAN_F8R2_FB10

    - -
    -
    - - - - -
    #define CAN_F8R2_FB10   CAN_F8R2_FB10_Msk
    -
    -

    Filter bit 10

    - -
    -
    - -

    ◆ CAN_F8R2_FB11_Pos

    - -
    -
    - - - - -
    #define CAN_F8R2_FB11_Pos   (11U)
    -
    - -
    -
    - -

    ◆ CAN_F8R2_FB11_Msk

    - -
    -
    - - - - -
    #define CAN_F8R2_FB11_Msk   (0x1UL << CAN_F8R2_FB11_Pos)
    -
    -

    0x00000800

    - -
    -
    - -

    ◆ CAN_F8R2_FB11

    - -
    -
    - - - - -
    #define CAN_F8R2_FB11   CAN_F8R2_FB11_Msk
    -
    -

    Filter bit 11

    - -
    -
    - -

    ◆ CAN_F8R2_FB12_Pos

    - -
    -
    - - - - -
    #define CAN_F8R2_FB12_Pos   (12U)
    -
    - -
    -
    - -

    ◆ CAN_F8R2_FB12_Msk

    - -
    -
    - - - - -
    #define CAN_F8R2_FB12_Msk   (0x1UL << CAN_F8R2_FB12_Pos)
    -
    -

    0x00001000

    - -
    -
    - -

    ◆ CAN_F8R2_FB12

    - -
    -
    - - - - -
    #define CAN_F8R2_FB12   CAN_F8R2_FB12_Msk
    -
    -

    Filter bit 12

    - -
    -
    - -

    ◆ CAN_F8R2_FB13_Pos

    - -
    -
    - - - - -
    #define CAN_F8R2_FB13_Pos   (13U)
    -
    - -
    -
    - -

    ◆ CAN_F8R2_FB13_Msk

    - -
    -
    - - - - -
    #define CAN_F8R2_FB13_Msk   (0x1UL << CAN_F8R2_FB13_Pos)
    -
    -

    0x00002000

    - -
    -
    - -

    ◆ CAN_F8R2_FB13

    - -
    -
    - - - - -
    #define CAN_F8R2_FB13   CAN_F8R2_FB13_Msk
    -
    -

    Filter bit 13

    - -
    -
    - -

    ◆ CAN_F8R2_FB14_Pos

    - -
    -
    - - - - -
    #define CAN_F8R2_FB14_Pos   (14U)
    -
    - -
    -
    - -

    ◆ CAN_F8R2_FB14_Msk

    - -
    -
    - - - - -
    #define CAN_F8R2_FB14_Msk   (0x1UL << CAN_F8R2_FB14_Pos)
    -
    -

    0x00004000

    - -
    -
    - -

    ◆ CAN_F8R2_FB14

    - -
    -
    - - - - -
    #define CAN_F8R2_FB14   CAN_F8R2_FB14_Msk
    -
    -

    Filter bit 14

    - -
    -
    - -

    ◆ CAN_F8R2_FB15_Pos

    - -
    -
    - - - - -
    #define CAN_F8R2_FB15_Pos   (15U)
    -
    - -
    -
    - -

    ◆ CAN_F8R2_FB15_Msk

    - -
    -
    - - - - -
    #define CAN_F8R2_FB15_Msk   (0x1UL << CAN_F8R2_FB15_Pos)
    -
    -

    0x00008000

    - -
    -
    - -

    ◆ CAN_F8R2_FB15

    - -
    -
    - - - - -
    #define CAN_F8R2_FB15   CAN_F8R2_FB15_Msk
    -
    -

    Filter bit 15

    - -
    -
    - -

    ◆ CAN_F8R2_FB16_Pos

    - -
    -
    - - - - -
    #define CAN_F8R2_FB16_Pos   (16U)
    -
    - -
    -
    - -

    ◆ CAN_F8R2_FB16_Msk

    - -
    -
    - - - - -
    #define CAN_F8R2_FB16_Msk   (0x1UL << CAN_F8R2_FB16_Pos)
    -
    -

    0x00010000

    - -
    -
    - -

    ◆ CAN_F8R2_FB16

    - -
    -
    - - - - -
    #define CAN_F8R2_FB16   CAN_F8R2_FB16_Msk
    -
    -

    Filter bit 16

    - -
    -
    - -

    ◆ CAN_F8R2_FB17_Pos

    - -
    -
    - - - - -
    #define CAN_F8R2_FB17_Pos   (17U)
    -
    - -
    -
    - -

    ◆ CAN_F8R2_FB17_Msk

    - -
    -
    - - - - -
    #define CAN_F8R2_FB17_Msk   (0x1UL << CAN_F8R2_FB17_Pos)
    -
    -

    0x00020000

    - -
    -
    - -

    ◆ CAN_F8R2_FB17

    - -
    -
    - - - - -
    #define CAN_F8R2_FB17   CAN_F8R2_FB17_Msk
    -
    -

    Filter bit 17

    - -
    -
    - -

    ◆ CAN_F8R2_FB18_Pos

    - -
    -
    - - - - -
    #define CAN_F8R2_FB18_Pos   (18U)
    -
    - -
    -
    - -

    ◆ CAN_F8R2_FB18_Msk

    - -
    -
    - - - - -
    #define CAN_F8R2_FB18_Msk   (0x1UL << CAN_F8R2_FB18_Pos)
    -
    -

    0x00040000

    - -
    -
    - -

    ◆ CAN_F8R2_FB18

    - -
    -
    - - - - -
    #define CAN_F8R2_FB18   CAN_F8R2_FB18_Msk
    -
    -

    Filter bit 18

    - -
    -
    - -

    ◆ CAN_F8R2_FB19_Pos

    - -
    -
    - - - - -
    #define CAN_F8R2_FB19_Pos   (19U)
    -
    - -
    -
    - -

    ◆ CAN_F8R2_FB19_Msk

    - -
    -
    - - - - -
    #define CAN_F8R2_FB19_Msk   (0x1UL << CAN_F8R2_FB19_Pos)
    -
    -

    0x00080000

    - -
    -
    - -

    ◆ CAN_F8R2_FB19

    - -
    -
    - - - - -
    #define CAN_F8R2_FB19   CAN_F8R2_FB19_Msk
    -
    -

    Filter bit 19

    - -
    -
    - -

    ◆ CAN_F8R2_FB20_Pos

    - -
    -
    - - - - -
    #define CAN_F8R2_FB20_Pos   (20U)
    -
    - -
    -
    - -

    ◆ CAN_F8R2_FB20_Msk

    - -
    -
    - - - - -
    #define CAN_F8R2_FB20_Msk   (0x1UL << CAN_F8R2_FB20_Pos)
    -
    -

    0x00100000

    - -
    -
    - -

    ◆ CAN_F8R2_FB20

    - -
    -
    - - - - -
    #define CAN_F8R2_FB20   CAN_F8R2_FB20_Msk
    -
    -

    Filter bit 20

    - -
    -
    - -

    ◆ CAN_F8R2_FB21_Pos

    - -
    -
    - - - - -
    #define CAN_F8R2_FB21_Pos   (21U)
    -
    - -
    -
    - -

    ◆ CAN_F8R2_FB21_Msk

    - -
    -
    - - - - -
    #define CAN_F8R2_FB21_Msk   (0x1UL << CAN_F8R2_FB21_Pos)
    -
    -

    0x00200000

    - -
    -
    - -

    ◆ CAN_F8R2_FB21

    - -
    -
    - - - - -
    #define CAN_F8R2_FB21   CAN_F8R2_FB21_Msk
    -
    -

    Filter bit 21

    - -
    -
    - -

    ◆ CAN_F8R2_FB22_Pos

    - -
    -
    - - - - -
    #define CAN_F8R2_FB22_Pos   (22U)
    -
    - -
    -
    - -

    ◆ CAN_F8R2_FB22_Msk

    - -
    -
    - - - - -
    #define CAN_F8R2_FB22_Msk   (0x1UL << CAN_F8R2_FB22_Pos)
    -
    -

    0x00400000

    - -
    -
    - -

    ◆ CAN_F8R2_FB22

    - -
    -
    - - - - -
    #define CAN_F8R2_FB22   CAN_F8R2_FB22_Msk
    -
    -

    Filter bit 22

    - -
    -
    - -

    ◆ CAN_F8R2_FB23_Pos

    - -
    -
    - - - - -
    #define CAN_F8R2_FB23_Pos   (23U)
    -
    - -
    -
    - -

    ◆ CAN_F8R2_FB23_Msk

    - -
    -
    - - - - -
    #define CAN_F8R2_FB23_Msk   (0x1UL << CAN_F8R2_FB23_Pos)
    -
    -

    0x00800000

    - -
    -
    - -

    ◆ CAN_F8R2_FB23

    - -
    -
    - - - - -
    #define CAN_F8R2_FB23   CAN_F8R2_FB23_Msk
    -
    -

    Filter bit 23

    - -
    -
    - -

    ◆ CAN_F8R2_FB24_Pos

    - -
    -
    - - - - -
    #define CAN_F8R2_FB24_Pos   (24U)
    -
    - -
    -
    - -

    ◆ CAN_F8R2_FB24_Msk

    - -
    -
    - - - - -
    #define CAN_F8R2_FB24_Msk   (0x1UL << CAN_F8R2_FB24_Pos)
    -
    -

    0x01000000

    - -
    -
    - -

    ◆ CAN_F8R2_FB24

    - -
    -
    - - - - -
    #define CAN_F8R2_FB24   CAN_F8R2_FB24_Msk
    -
    -

    Filter bit 24

    - -
    -
    - -

    ◆ CAN_F8R2_FB25_Pos

    - -
    -
    - - - - -
    #define CAN_F8R2_FB25_Pos   (25U)
    -
    - -
    -
    - -

    ◆ CAN_F8R2_FB25_Msk

    - -
    -
    - - - - -
    #define CAN_F8R2_FB25_Msk   (0x1UL << CAN_F8R2_FB25_Pos)
    -
    -

    0x02000000

    - -
    -
    - -

    ◆ CAN_F8R2_FB25

    - -
    -
    - - - - -
    #define CAN_F8R2_FB25   CAN_F8R2_FB25_Msk
    -
    -

    Filter bit 25

    - -
    -
    - -

    ◆ CAN_F8R2_FB26_Pos

    - -
    -
    - - - - -
    #define CAN_F8R2_FB26_Pos   (26U)
    -
    - -
    -
    - -

    ◆ CAN_F8R2_FB26_Msk

    - -
    -
    - - - - -
    #define CAN_F8R2_FB26_Msk   (0x1UL << CAN_F8R2_FB26_Pos)
    -
    -

    0x04000000

    - -
    -
    - -

    ◆ CAN_F8R2_FB26

    - -
    -
    - - - - -
    #define CAN_F8R2_FB26   CAN_F8R2_FB26_Msk
    -
    -

    Filter bit 26

    - -
    -
    - -

    ◆ CAN_F8R2_FB27_Pos

    - -
    -
    - - - - -
    #define CAN_F8R2_FB27_Pos   (27U)
    -
    - -
    -
    - -

    ◆ CAN_F8R2_FB27_Msk

    - -
    -
    - - - - -
    #define CAN_F8R2_FB27_Msk   (0x1UL << CAN_F8R2_FB27_Pos)
    -
    -

    0x08000000

    - -
    -
    - -

    ◆ CAN_F8R2_FB27

    - -
    -
    - - - - -
    #define CAN_F8R2_FB27   CAN_F8R2_FB27_Msk
    -
    -

    Filter bit 27

    - -
    -
    - -

    ◆ CAN_F8R2_FB28_Pos

    - -
    -
    - - - - -
    #define CAN_F8R2_FB28_Pos   (28U)
    -
    - -
    -
    - -

    ◆ CAN_F8R2_FB28_Msk

    - -
    -
    - - - - -
    #define CAN_F8R2_FB28_Msk   (0x1UL << CAN_F8R2_FB28_Pos)
    -
    -

    0x10000000

    - -
    -
    - -

    ◆ CAN_F8R2_FB28

    - -
    -
    - - - - -
    #define CAN_F8R2_FB28   CAN_F8R2_FB28_Msk
    -
    -

    Filter bit 28

    - -
    -
    - -

    ◆ CAN_F8R2_FB29_Pos

    - -
    -
    - - - - -
    #define CAN_F8R2_FB29_Pos   (29U)
    -
    - -
    -
    - -

    ◆ CAN_F8R2_FB29_Msk

    - -
    -
    - - - - -
    #define CAN_F8R2_FB29_Msk   (0x1UL << CAN_F8R2_FB29_Pos)
    -
    -

    0x20000000

    - -
    -
    - -

    ◆ CAN_F8R2_FB29

    - -
    -
    - - - - -
    #define CAN_F8R2_FB29   CAN_F8R2_FB29_Msk
    -
    -

    Filter bit 29

    - -
    -
    - -

    ◆ CAN_F8R2_FB30_Pos

    - -
    -
    - - - - -
    #define CAN_F8R2_FB30_Pos   (30U)
    -
    - -
    -
    - -

    ◆ CAN_F8R2_FB30_Msk

    - -
    -
    - - - - -
    #define CAN_F8R2_FB30_Msk   (0x1UL << CAN_F8R2_FB30_Pos)
    -
    -

    0x40000000

    - -
    -
    - -

    ◆ CAN_F8R2_FB30

    - -
    -
    - - - - -
    #define CAN_F8R2_FB30   CAN_F8R2_FB30_Msk
    -
    -

    Filter bit 30

    - -
    -
    - -

    ◆ CAN_F8R2_FB31_Pos

    - -
    -
    - - - - -
    #define CAN_F8R2_FB31_Pos   (31U)
    -
    - -
    -
    - -

    ◆ CAN_F8R2_FB31_Msk

    - -
    -
    - - - - -
    #define CAN_F8R2_FB31_Msk   (0x1UL << CAN_F8R2_FB31_Pos)
    -
    -

    0x80000000

    - -
    -
    - -

    ◆ CAN_F8R2_FB31

    - -
    -
    - - - - -
    #define CAN_F8R2_FB31   CAN_F8R2_FB31_Msk
    -
    -

    Filter bit 31

    - -
    -
    - -

    ◆ CAN_F9R2_FB0_Pos

    - -
    -
    - - - - -
    #define CAN_F9R2_FB0_Pos   (0U)
    -
    - -
    -
    - -

    ◆ CAN_F9R2_FB0_Msk

    - -
    -
    - - - - -
    #define CAN_F9R2_FB0_Msk   (0x1UL << CAN_F9R2_FB0_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ CAN_F9R2_FB0

    - -
    -
    - - - - -
    #define CAN_F9R2_FB0   CAN_F9R2_FB0_Msk
    -
    -

    Filter bit 0

    - -
    -
    - -

    ◆ CAN_F9R2_FB1_Pos

    - -
    -
    - - - - -
    #define CAN_F9R2_FB1_Pos   (1U)
    -
    - -
    -
    - -

    ◆ CAN_F9R2_FB1_Msk

    - -
    -
    - - - - -
    #define CAN_F9R2_FB1_Msk   (0x1UL << CAN_F9R2_FB1_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ CAN_F9R2_FB1

    - -
    -
    - - - - -
    #define CAN_F9R2_FB1   CAN_F9R2_FB1_Msk
    -
    -

    Filter bit 1

    - -
    -
    - -

    ◆ CAN_F9R2_FB2_Pos

    - -
    -
    - - - - -
    #define CAN_F9R2_FB2_Pos   (2U)
    -
    - -
    -
    - -

    ◆ CAN_F9R2_FB2_Msk

    - -
    -
    - - - - -
    #define CAN_F9R2_FB2_Msk   (0x1UL << CAN_F9R2_FB2_Pos)
    -
    -

    0x00000004

    - -
    -
    - -

    ◆ CAN_F9R2_FB2

    - -
    -
    - - - - -
    #define CAN_F9R2_FB2   CAN_F9R2_FB2_Msk
    -
    -

    Filter bit 2

    - -
    -
    - -

    ◆ CAN_F9R2_FB3_Pos

    - -
    -
    - - - - -
    #define CAN_F9R2_FB3_Pos   (3U)
    -
    - -
    -
    - -

    ◆ CAN_F9R2_FB3_Msk

    - -
    -
    - - - - -
    #define CAN_F9R2_FB3_Msk   (0x1UL << CAN_F9R2_FB3_Pos)
    -
    -

    0x00000008

    - -
    -
    - -

    ◆ CAN_F9R2_FB3

    - -
    -
    - - - - -
    #define CAN_F9R2_FB3   CAN_F9R2_FB3_Msk
    -
    -

    Filter bit 3

    - -
    -
    - -

    ◆ CAN_F9R2_FB4_Pos

    - -
    -
    - - - - -
    #define CAN_F9R2_FB4_Pos   (4U)
    -
    - -
    -
    - -

    ◆ CAN_F9R2_FB4_Msk

    - -
    -
    - - - - -
    #define CAN_F9R2_FB4_Msk   (0x1UL << CAN_F9R2_FB4_Pos)
    -
    -

    0x00000010

    - -
    -
    - -

    ◆ CAN_F9R2_FB4

    - -
    -
    - - - - -
    #define CAN_F9R2_FB4   CAN_F9R2_FB4_Msk
    -
    -

    Filter bit 4

    - -
    -
    - -

    ◆ CAN_F9R2_FB5_Pos

    - -
    -
    - - - - -
    #define CAN_F9R2_FB5_Pos   (5U)
    -
    - -
    -
    - -

    ◆ CAN_F9R2_FB5_Msk

    - -
    -
    - - - - -
    #define CAN_F9R2_FB5_Msk   (0x1UL << CAN_F9R2_FB5_Pos)
    -
    -

    0x00000020

    - -
    -
    - -

    ◆ CAN_F9R2_FB5

    - -
    -
    - - - - -
    #define CAN_F9R2_FB5   CAN_F9R2_FB5_Msk
    -
    -

    Filter bit 5

    - -
    -
    - -

    ◆ CAN_F9R2_FB6_Pos

    - -
    -
    - - - - -
    #define CAN_F9R2_FB6_Pos   (6U)
    -
    - -
    -
    - -

    ◆ CAN_F9R2_FB6_Msk

    - -
    -
    - - - - -
    #define CAN_F9R2_FB6_Msk   (0x1UL << CAN_F9R2_FB6_Pos)
    -
    -

    0x00000040

    - -
    -
    - -

    ◆ CAN_F9R2_FB6

    - -
    -
    - - - - -
    #define CAN_F9R2_FB6   CAN_F9R2_FB6_Msk
    -
    -

    Filter bit 6

    - -
    -
    - -

    ◆ CAN_F9R2_FB7_Pos

    - -
    -
    - - - - -
    #define CAN_F9R2_FB7_Pos   (7U)
    -
    - -
    -
    - -

    ◆ CAN_F9R2_FB7_Msk

    - -
    -
    - - - - -
    #define CAN_F9R2_FB7_Msk   (0x1UL << CAN_F9R2_FB7_Pos)
    -
    -

    0x00000080

    - -
    -
    - -

    ◆ CAN_F9R2_FB7

    - -
    -
    - - - - -
    #define CAN_F9R2_FB7   CAN_F9R2_FB7_Msk
    -
    -

    Filter bit 7

    - -
    -
    - -

    ◆ CAN_F9R2_FB8_Pos

    - -
    -
    - - - - -
    #define CAN_F9R2_FB8_Pos   (8U)
    -
    - -
    -
    - -

    ◆ CAN_F9R2_FB8_Msk

    - -
    -
    - - - - -
    #define CAN_F9R2_FB8_Msk   (0x1UL << CAN_F9R2_FB8_Pos)
    -
    -

    0x00000100

    - -
    -
    - -

    ◆ CAN_F9R2_FB8

    - -
    -
    - - - - -
    #define CAN_F9R2_FB8   CAN_F9R2_FB8_Msk
    -
    -

    Filter bit 8

    - -
    -
    - -

    ◆ CAN_F9R2_FB9_Pos

    - -
    -
    - - - - -
    #define CAN_F9R2_FB9_Pos   (9U)
    -
    - -
    -
    - -

    ◆ CAN_F9R2_FB9_Msk

    - -
    -
    - - - - -
    #define CAN_F9R2_FB9_Msk   (0x1UL << CAN_F9R2_FB9_Pos)
    -
    -

    0x00000200

    - -
    -
    - -

    ◆ CAN_F9R2_FB9

    - -
    -
    - - - - -
    #define CAN_F9R2_FB9   CAN_F9R2_FB9_Msk
    -
    -

    Filter bit 9

    - -
    -
    - -

    ◆ CAN_F9R2_FB10_Pos

    - -
    -
    - - - - -
    #define CAN_F9R2_FB10_Pos   (10U)
    -
    - -
    -
    - -

    ◆ CAN_F9R2_FB10_Msk

    - -
    -
    - - - - -
    #define CAN_F9R2_FB10_Msk   (0x1UL << CAN_F9R2_FB10_Pos)
    -
    -

    0x00000400

    - -
    -
    - -

    ◆ CAN_F9R2_FB10

    - -
    -
    - - - - -
    #define CAN_F9R2_FB10   CAN_F9R2_FB10_Msk
    -
    -

    Filter bit 10

    - -
    -
    - -

    ◆ CAN_F9R2_FB11_Pos

    - -
    -
    - - - - -
    #define CAN_F9R2_FB11_Pos   (11U)
    -
    - -
    -
    - -

    ◆ CAN_F9R2_FB11_Msk

    - -
    -
    - - - - -
    #define CAN_F9R2_FB11_Msk   (0x1UL << CAN_F9R2_FB11_Pos)
    -
    -

    0x00000800

    - -
    -
    - -

    ◆ CAN_F9R2_FB11

    - -
    -
    - - - - -
    #define CAN_F9R2_FB11   CAN_F9R2_FB11_Msk
    -
    -

    Filter bit 11

    - -
    -
    - -

    ◆ CAN_F9R2_FB12_Pos

    - -
    -
    - - - - -
    #define CAN_F9R2_FB12_Pos   (12U)
    -
    - -
    -
    - -

    ◆ CAN_F9R2_FB12_Msk

    - -
    -
    - - - - -
    #define CAN_F9R2_FB12_Msk   (0x1UL << CAN_F9R2_FB12_Pos)
    -
    -

    0x00001000

    - -
    -
    - -

    ◆ CAN_F9R2_FB12

    - -
    -
    - - - - -
    #define CAN_F9R2_FB12   CAN_F9R2_FB12_Msk
    -
    -

    Filter bit 12

    - -
    -
    - -

    ◆ CAN_F9R2_FB13_Pos

    - -
    -
    - - - - -
    #define CAN_F9R2_FB13_Pos   (13U)
    -
    - -
    -
    - -

    ◆ CAN_F9R2_FB13_Msk

    - -
    -
    - - - - -
    #define CAN_F9R2_FB13_Msk   (0x1UL << CAN_F9R2_FB13_Pos)
    -
    -

    0x00002000

    - -
    -
    - -

    ◆ CAN_F9R2_FB13

    - -
    -
    - - - - -
    #define CAN_F9R2_FB13   CAN_F9R2_FB13_Msk
    -
    -

    Filter bit 13

    - -
    -
    - -

    ◆ CAN_F9R2_FB14_Pos

    - -
    -
    - - - - -
    #define CAN_F9R2_FB14_Pos   (14U)
    -
    - -
    -
    - -

    ◆ CAN_F9R2_FB14_Msk

    - -
    -
    - - - - -
    #define CAN_F9R2_FB14_Msk   (0x1UL << CAN_F9R2_FB14_Pos)
    -
    -

    0x00004000

    - -
    -
    - -

    ◆ CAN_F9R2_FB14

    - -
    -
    - - - - -
    #define CAN_F9R2_FB14   CAN_F9R2_FB14_Msk
    -
    -

    Filter bit 14

    - -
    -
    - -

    ◆ CAN_F9R2_FB15_Pos

    - -
    -
    - - - - -
    #define CAN_F9R2_FB15_Pos   (15U)
    -
    - -
    -
    - -

    ◆ CAN_F9R2_FB15_Msk

    - -
    -
    - - - - -
    #define CAN_F9R2_FB15_Msk   (0x1UL << CAN_F9R2_FB15_Pos)
    -
    -

    0x00008000

    - -
    -
    - -

    ◆ CAN_F9R2_FB15

    - -
    -
    - - - - -
    #define CAN_F9R2_FB15   CAN_F9R2_FB15_Msk
    -
    -

    Filter bit 15

    - -
    -
    - -

    ◆ CAN_F9R2_FB16_Pos

    - -
    -
    - - - - -
    #define CAN_F9R2_FB16_Pos   (16U)
    -
    - -
    -
    - -

    ◆ CAN_F9R2_FB16_Msk

    - -
    -
    - - - - -
    #define CAN_F9R2_FB16_Msk   (0x1UL << CAN_F9R2_FB16_Pos)
    -
    -

    0x00010000

    - -
    -
    - -

    ◆ CAN_F9R2_FB16

    - -
    -
    - - - - -
    #define CAN_F9R2_FB16   CAN_F9R2_FB16_Msk
    -
    -

    Filter bit 16

    - -
    -
    - -

    ◆ CAN_F9R2_FB17_Pos

    - -
    -
    - - - - -
    #define CAN_F9R2_FB17_Pos   (17U)
    -
    - -
    -
    - -

    ◆ CAN_F9R2_FB17_Msk

    - -
    -
    - - - - -
    #define CAN_F9R2_FB17_Msk   (0x1UL << CAN_F9R2_FB17_Pos)
    -
    -

    0x00020000

    - -
    -
    - -

    ◆ CAN_F9R2_FB17

    - -
    -
    - - - - -
    #define CAN_F9R2_FB17   CAN_F9R2_FB17_Msk
    -
    -

    Filter bit 17

    - -
    -
    - -

    ◆ CAN_F9R2_FB18_Pos

    - -
    -
    - - - - -
    #define CAN_F9R2_FB18_Pos   (18U)
    -
    - -
    -
    - -

    ◆ CAN_F9R2_FB18_Msk

    - -
    -
    - - - - -
    #define CAN_F9R2_FB18_Msk   (0x1UL << CAN_F9R2_FB18_Pos)
    -
    -

    0x00040000

    - -
    -
    - -

    ◆ CAN_F9R2_FB18

    - -
    -
    - - - - -
    #define CAN_F9R2_FB18   CAN_F9R2_FB18_Msk
    -
    -

    Filter bit 18

    - -
    -
    - -

    ◆ CAN_F9R2_FB19_Pos

    - -
    -
    - - - - -
    #define CAN_F9R2_FB19_Pos   (19U)
    -
    - -
    -
    - -

    ◆ CAN_F9R2_FB19_Msk

    - -
    -
    - - - - -
    #define CAN_F9R2_FB19_Msk   (0x1UL << CAN_F9R2_FB19_Pos)
    -
    -

    0x00080000

    - -
    -
    - -

    ◆ CAN_F9R2_FB19

    - -
    -
    - - - - -
    #define CAN_F9R2_FB19   CAN_F9R2_FB19_Msk
    -
    -

    Filter bit 19

    - -
    -
    - -

    ◆ CAN_F9R2_FB20_Pos

    - -
    -
    - - - - -
    #define CAN_F9R2_FB20_Pos   (20U)
    -
    - -
    -
    - -

    ◆ CAN_F9R2_FB20_Msk

    - -
    -
    - - - - -
    #define CAN_F9R2_FB20_Msk   (0x1UL << CAN_F9R2_FB20_Pos)
    -
    -

    0x00100000

    - -
    -
    - -

    ◆ CAN_F9R2_FB20

    - -
    -
    - - - - -
    #define CAN_F9R2_FB20   CAN_F9R2_FB20_Msk
    -
    -

    Filter bit 20

    - -
    -
    - -

    ◆ CAN_F9R2_FB21_Pos

    - -
    -
    - - - - -
    #define CAN_F9R2_FB21_Pos   (21U)
    -
    - -
    -
    - -

    ◆ CAN_F9R2_FB21_Msk

    - -
    -
    - - - - -
    #define CAN_F9R2_FB21_Msk   (0x1UL << CAN_F9R2_FB21_Pos)
    -
    -

    0x00200000

    - -
    -
    - -

    ◆ CAN_F9R2_FB21

    - -
    -
    - - - - -
    #define CAN_F9R2_FB21   CAN_F9R2_FB21_Msk
    -
    -

    Filter bit 21

    - -
    -
    - -

    ◆ CAN_F9R2_FB22_Pos

    - -
    -
    - - - - -
    #define CAN_F9R2_FB22_Pos   (22U)
    -
    - -
    -
    - -

    ◆ CAN_F9R2_FB22_Msk

    - -
    -
    - - - - -
    #define CAN_F9R2_FB22_Msk   (0x1UL << CAN_F9R2_FB22_Pos)
    -
    -

    0x00400000

    - -
    -
    - -

    ◆ CAN_F9R2_FB22

    - -
    -
    - - - - -
    #define CAN_F9R2_FB22   CAN_F9R2_FB22_Msk
    -
    -

    Filter bit 22

    - -
    -
    - -

    ◆ CAN_F9R2_FB23_Pos

    - -
    -
    - - - - -
    #define CAN_F9R2_FB23_Pos   (23U)
    -
    - -
    -
    - -

    ◆ CAN_F9R2_FB23_Msk

    - -
    -
    - - - - -
    #define CAN_F9R2_FB23_Msk   (0x1UL << CAN_F9R2_FB23_Pos)
    -
    -

    0x00800000

    - -
    -
    - -

    ◆ CAN_F9R2_FB23

    - -
    -
    - - - - -
    #define CAN_F9R2_FB23   CAN_F9R2_FB23_Msk
    -
    -

    Filter bit 23

    - -
    -
    - -

    ◆ CAN_F9R2_FB24_Pos

    - -
    -
    - - - - -
    #define CAN_F9R2_FB24_Pos   (24U)
    -
    - -
    -
    - -

    ◆ CAN_F9R2_FB24_Msk

    - -
    -
    - - - - -
    #define CAN_F9R2_FB24_Msk   (0x1UL << CAN_F9R2_FB24_Pos)
    -
    -

    0x01000000

    - -
    -
    - -

    ◆ CAN_F9R2_FB24

    - -
    -
    - - - - -
    #define CAN_F9R2_FB24   CAN_F9R2_FB24_Msk
    -
    -

    Filter bit 24

    - -
    -
    - -

    ◆ CAN_F9R2_FB25_Pos

    - -
    -
    - - - - -
    #define CAN_F9R2_FB25_Pos   (25U)
    -
    - -
    -
    - -

    ◆ CAN_F9R2_FB25_Msk

    - -
    -
    - - - - -
    #define CAN_F9R2_FB25_Msk   (0x1UL << CAN_F9R2_FB25_Pos)
    -
    -

    0x02000000

    - -
    -
    - -

    ◆ CAN_F9R2_FB25

    - -
    -
    - - - - -
    #define CAN_F9R2_FB25   CAN_F9R2_FB25_Msk
    -
    -

    Filter bit 25

    - -
    -
    - -

    ◆ CAN_F9R2_FB26_Pos

    - -
    -
    - - - - -
    #define CAN_F9R2_FB26_Pos   (26U)
    -
    - -
    -
    - -

    ◆ CAN_F9R2_FB26_Msk

    - -
    -
    - - - - -
    #define CAN_F9R2_FB26_Msk   (0x1UL << CAN_F9R2_FB26_Pos)
    -
    -

    0x04000000

    - -
    -
    - -

    ◆ CAN_F9R2_FB26

    - -
    -
    - - - - -
    #define CAN_F9R2_FB26   CAN_F9R2_FB26_Msk
    -
    -

    Filter bit 26

    - -
    -
    - -

    ◆ CAN_F9R2_FB27_Pos

    - -
    -
    - - - - -
    #define CAN_F9R2_FB27_Pos   (27U)
    -
    - -
    -
    - -

    ◆ CAN_F9R2_FB27_Msk

    - -
    -
    - - - - -
    #define CAN_F9R2_FB27_Msk   (0x1UL << CAN_F9R2_FB27_Pos)
    -
    -

    0x08000000

    - -
    -
    - -

    ◆ CAN_F9R2_FB27

    - -
    -
    - - - - -
    #define CAN_F9R2_FB27   CAN_F9R2_FB27_Msk
    -
    -

    Filter bit 27

    - -
    -
    - -

    ◆ CAN_F9R2_FB28_Pos

    - -
    -
    - - - - -
    #define CAN_F9R2_FB28_Pos   (28U)
    -
    - -
    -
    - -

    ◆ CAN_F9R2_FB28_Msk

    - -
    -
    - - - - -
    #define CAN_F9R2_FB28_Msk   (0x1UL << CAN_F9R2_FB28_Pos)
    -
    -

    0x10000000

    - -
    -
    - -

    ◆ CAN_F9R2_FB28

    - -
    -
    - - - - -
    #define CAN_F9R2_FB28   CAN_F9R2_FB28_Msk
    -
    -

    Filter bit 28

    - -
    -
    - -

    ◆ CAN_F9R2_FB29_Pos

    - -
    -
    - - - - -
    #define CAN_F9R2_FB29_Pos   (29U)
    -
    - -
    -
    - -

    ◆ CAN_F9R2_FB29_Msk

    - -
    -
    - - - - -
    #define CAN_F9R2_FB29_Msk   (0x1UL << CAN_F9R2_FB29_Pos)
    -
    -

    0x20000000

    - -
    -
    - -

    ◆ CAN_F9R2_FB29

    - -
    -
    - - - - -
    #define CAN_F9R2_FB29   CAN_F9R2_FB29_Msk
    -
    -

    Filter bit 29

    - -
    -
    - -

    ◆ CAN_F9R2_FB30_Pos

    - -
    -
    - - - - -
    #define CAN_F9R2_FB30_Pos   (30U)
    -
    - -
    -
    - -

    ◆ CAN_F9R2_FB30_Msk

    - -
    -
    - - - - -
    #define CAN_F9R2_FB30_Msk   (0x1UL << CAN_F9R2_FB30_Pos)
    -
    -

    0x40000000

    - -
    -
    - -

    ◆ CAN_F9R2_FB30

    - -
    -
    - - - - -
    #define CAN_F9R2_FB30   CAN_F9R2_FB30_Msk
    -
    -

    Filter bit 30

    - -
    -
    - -

    ◆ CAN_F9R2_FB31_Pos

    - -
    -
    - - - - -
    #define CAN_F9R2_FB31_Pos   (31U)
    -
    - -
    -
    - -

    ◆ CAN_F9R2_FB31_Msk

    - -
    -
    - - - - -
    #define CAN_F9R2_FB31_Msk   (0x1UL << CAN_F9R2_FB31_Pos)
    -
    -

    0x80000000

    - -
    -
    - -

    ◆ CAN_F9R2_FB31

    - -
    -
    - - - - -
    #define CAN_F9R2_FB31   CAN_F9R2_FB31_Msk
    -
    -

    Filter bit 31

    - -
    -
    - -

    ◆ CAN_F10R2_FB0_Pos

    - -
    -
    - - - - -
    #define CAN_F10R2_FB0_Pos   (0U)
    -
    - -
    -
    - -

    ◆ CAN_F10R2_FB0_Msk

    - -
    -
    - - - - -
    #define CAN_F10R2_FB0_Msk   (0x1UL << CAN_F10R2_FB0_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ CAN_F10R2_FB0

    - -
    -
    - - - - -
    #define CAN_F10R2_FB0   CAN_F10R2_FB0_Msk
    -
    -

    Filter bit 0

    - -
    -
    - -

    ◆ CAN_F10R2_FB1_Pos

    - -
    -
    - - - - -
    #define CAN_F10R2_FB1_Pos   (1U)
    -
    - -
    -
    - -

    ◆ CAN_F10R2_FB1_Msk

    - -
    -
    - - - - -
    #define CAN_F10R2_FB1_Msk   (0x1UL << CAN_F10R2_FB1_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ CAN_F10R2_FB1

    - -
    -
    - - - - -
    #define CAN_F10R2_FB1   CAN_F10R2_FB1_Msk
    -
    -

    Filter bit 1

    - -
    -
    - -

    ◆ CAN_F10R2_FB2_Pos

    - -
    -
    - - - - -
    #define CAN_F10R2_FB2_Pos   (2U)
    -
    - -
    -
    - -

    ◆ CAN_F10R2_FB2_Msk

    - -
    -
    - - - - -
    #define CAN_F10R2_FB2_Msk   (0x1UL << CAN_F10R2_FB2_Pos)
    -
    -

    0x00000004

    - -
    -
    - -

    ◆ CAN_F10R2_FB2

    - -
    -
    - - - - -
    #define CAN_F10R2_FB2   CAN_F10R2_FB2_Msk
    -
    -

    Filter bit 2

    - -
    -
    - -

    ◆ CAN_F10R2_FB3_Pos

    - -
    -
    - - - - -
    #define CAN_F10R2_FB3_Pos   (3U)
    -
    - -
    -
    - -

    ◆ CAN_F10R2_FB3_Msk

    - -
    -
    - - - - -
    #define CAN_F10R2_FB3_Msk   (0x1UL << CAN_F10R2_FB3_Pos)
    -
    -

    0x00000008

    - -
    -
    - -

    ◆ CAN_F10R2_FB3

    - -
    -
    - - - - -
    #define CAN_F10R2_FB3   CAN_F10R2_FB3_Msk
    -
    -

    Filter bit 3

    - -
    -
    - -

    ◆ CAN_F10R2_FB4_Pos

    - -
    -
    - - - - -
    #define CAN_F10R2_FB4_Pos   (4U)
    -
    - -
    -
    - -

    ◆ CAN_F10R2_FB4_Msk

    - -
    -
    - - - - -
    #define CAN_F10R2_FB4_Msk   (0x1UL << CAN_F10R2_FB4_Pos)
    -
    -

    0x00000010

    - -
    -
    - -

    ◆ CAN_F10R2_FB4

    - -
    -
    - - - - -
    #define CAN_F10R2_FB4   CAN_F10R2_FB4_Msk
    -
    -

    Filter bit 4

    - -
    -
    - -

    ◆ CAN_F10R2_FB5_Pos

    - -
    -
    - - - - -
    #define CAN_F10R2_FB5_Pos   (5U)
    -
    - -
    -
    - -

    ◆ CAN_F10R2_FB5_Msk

    - -
    -
    - - - - -
    #define CAN_F10R2_FB5_Msk   (0x1UL << CAN_F10R2_FB5_Pos)
    -
    -

    0x00000020

    - -
    -
    - -

    ◆ CAN_F10R2_FB5

    - -
    -
    - - - - -
    #define CAN_F10R2_FB5   CAN_F10R2_FB5_Msk
    -
    -

    Filter bit 5

    - -
    -
    - -

    ◆ CAN_F10R2_FB6_Pos

    - -
    -
    - - - - -
    #define CAN_F10R2_FB6_Pos   (6U)
    -
    - -
    -
    - -

    ◆ CAN_F10R2_FB6_Msk

    - -
    -
    - - - - -
    #define CAN_F10R2_FB6_Msk   (0x1UL << CAN_F10R2_FB6_Pos)
    -
    -

    0x00000040

    - -
    -
    - -

    ◆ CAN_F10R2_FB6

    - -
    -
    - - - - -
    #define CAN_F10R2_FB6   CAN_F10R2_FB6_Msk
    -
    -

    Filter bit 6

    - -
    -
    - -

    ◆ CAN_F10R2_FB7_Pos

    - -
    -
    - - - - -
    #define CAN_F10R2_FB7_Pos   (7U)
    -
    - -
    -
    - -

    ◆ CAN_F10R2_FB7_Msk

    - -
    -
    - - - - -
    #define CAN_F10R2_FB7_Msk   (0x1UL << CAN_F10R2_FB7_Pos)
    -
    -

    0x00000080

    - -
    -
    - -

    ◆ CAN_F10R2_FB7

    - -
    -
    - - - - -
    #define CAN_F10R2_FB7   CAN_F10R2_FB7_Msk
    -
    -

    Filter bit 7

    - -
    -
    - -

    ◆ CAN_F10R2_FB8_Pos

    - -
    -
    - - - - -
    #define CAN_F10R2_FB8_Pos   (8U)
    -
    - -
    -
    - -

    ◆ CAN_F10R2_FB8_Msk

    - -
    -
    - - - - -
    #define CAN_F10R2_FB8_Msk   (0x1UL << CAN_F10R2_FB8_Pos)
    -
    -

    0x00000100

    - -
    -
    - -

    ◆ CAN_F10R2_FB8

    - -
    -
    - - - - -
    #define CAN_F10R2_FB8   CAN_F10R2_FB8_Msk
    -
    -

    Filter bit 8

    - -
    -
    - -

    ◆ CAN_F10R2_FB9_Pos

    - -
    -
    - - - - -
    #define CAN_F10R2_FB9_Pos   (9U)
    -
    - -
    -
    - -

    ◆ CAN_F10R2_FB9_Msk

    - -
    -
    - - - - -
    #define CAN_F10R2_FB9_Msk   (0x1UL << CAN_F10R2_FB9_Pos)
    -
    -

    0x00000200

    - -
    -
    - -

    ◆ CAN_F10R2_FB9

    - -
    -
    - - - - -
    #define CAN_F10R2_FB9   CAN_F10R2_FB9_Msk
    -
    -

    Filter bit 9

    - -
    -
    - -

    ◆ CAN_F10R2_FB10_Pos

    - -
    -
    - - - - -
    #define CAN_F10R2_FB10_Pos   (10U)
    -
    - -
    -
    - -

    ◆ CAN_F10R2_FB10_Msk

    - -
    -
    - - - - -
    #define CAN_F10R2_FB10_Msk   (0x1UL << CAN_F10R2_FB10_Pos)
    -
    -

    0x00000400

    - -
    -
    - -

    ◆ CAN_F10R2_FB10

    - -
    -
    - - - - -
    #define CAN_F10R2_FB10   CAN_F10R2_FB10_Msk
    -
    -

    Filter bit 10

    - -
    -
    - -

    ◆ CAN_F10R2_FB11_Pos

    - -
    -
    - - - - -
    #define CAN_F10R2_FB11_Pos   (11U)
    -
    - -
    -
    - -

    ◆ CAN_F10R2_FB11_Msk

    - -
    -
    - - - - -
    #define CAN_F10R2_FB11_Msk   (0x1UL << CAN_F10R2_FB11_Pos)
    -
    -

    0x00000800

    - -
    -
    - -

    ◆ CAN_F10R2_FB11

    - -
    -
    - - - - -
    #define CAN_F10R2_FB11   CAN_F10R2_FB11_Msk
    -
    -

    Filter bit 11

    - -
    -
    - -

    ◆ CAN_F10R2_FB12_Pos

    - -
    -
    - - - - -
    #define CAN_F10R2_FB12_Pos   (12U)
    -
    - -
    -
    - -

    ◆ CAN_F10R2_FB12_Msk

    - -
    -
    - - - - -
    #define CAN_F10R2_FB12_Msk   (0x1UL << CAN_F10R2_FB12_Pos)
    -
    -

    0x00001000

    - -
    -
    - -

    ◆ CAN_F10R2_FB12

    - -
    -
    - - - - -
    #define CAN_F10R2_FB12   CAN_F10R2_FB12_Msk
    -
    -

    Filter bit 12

    - -
    -
    - -

    ◆ CAN_F10R2_FB13_Pos

    - -
    -
    - - - - -
    #define CAN_F10R2_FB13_Pos   (13U)
    -
    - -
    -
    - -

    ◆ CAN_F10R2_FB13_Msk

    - -
    -
    - - - - -
    #define CAN_F10R2_FB13_Msk   (0x1UL << CAN_F10R2_FB13_Pos)
    -
    -

    0x00002000

    - -
    -
    - -

    ◆ CAN_F10R2_FB13

    - -
    -
    - - - - -
    #define CAN_F10R2_FB13   CAN_F10R2_FB13_Msk
    -
    -

    Filter bit 13

    - -
    -
    - -

    ◆ CAN_F10R2_FB14_Pos

    - -
    -
    - - - - -
    #define CAN_F10R2_FB14_Pos   (14U)
    -
    - -
    -
    - -

    ◆ CAN_F10R2_FB14_Msk

    - -
    -
    - - - - -
    #define CAN_F10R2_FB14_Msk   (0x1UL << CAN_F10R2_FB14_Pos)
    -
    -

    0x00004000

    - -
    -
    - -

    ◆ CAN_F10R2_FB14

    - -
    -
    - - - - -
    #define CAN_F10R2_FB14   CAN_F10R2_FB14_Msk
    -
    -

    Filter bit 14

    - -
    -
    - -

    ◆ CAN_F10R2_FB15_Pos

    - -
    -
    - - - - -
    #define CAN_F10R2_FB15_Pos   (15U)
    -
    - -
    -
    - -

    ◆ CAN_F10R2_FB15_Msk

    - -
    -
    - - - - -
    #define CAN_F10R2_FB15_Msk   (0x1UL << CAN_F10R2_FB15_Pos)
    -
    -

    0x00008000

    - -
    -
    - -

    ◆ CAN_F10R2_FB15

    - -
    -
    - - - - -
    #define CAN_F10R2_FB15   CAN_F10R2_FB15_Msk
    -
    -

    Filter bit 15

    - -
    -
    - -

    ◆ CAN_F10R2_FB16_Pos

    - -
    -
    - - - - -
    #define CAN_F10R2_FB16_Pos   (16U)
    -
    - -
    -
    - -

    ◆ CAN_F10R2_FB16_Msk

    - -
    -
    - - - - -
    #define CAN_F10R2_FB16_Msk   (0x1UL << CAN_F10R2_FB16_Pos)
    -
    -

    0x00010000

    - -
    -
    - -

    ◆ CAN_F10R2_FB16

    - -
    -
    - - - - -
    #define CAN_F10R2_FB16   CAN_F10R2_FB16_Msk
    -
    -

    Filter bit 16

    - -
    -
    - -

    ◆ CAN_F10R2_FB17_Pos

    - -
    -
    - - - - -
    #define CAN_F10R2_FB17_Pos   (17U)
    -
    - -
    -
    - -

    ◆ CAN_F10R2_FB17_Msk

    - -
    -
    - - - - -
    #define CAN_F10R2_FB17_Msk   (0x1UL << CAN_F10R2_FB17_Pos)
    -
    -

    0x00020000

    - -
    -
    - -

    ◆ CAN_F10R2_FB17

    - -
    -
    - - - - -
    #define CAN_F10R2_FB17   CAN_F10R2_FB17_Msk
    -
    -

    Filter bit 17

    - -
    -
    - -

    ◆ CAN_F10R2_FB18_Pos

    - -
    -
    - - - - -
    #define CAN_F10R2_FB18_Pos   (18U)
    -
    - -
    -
    - -

    ◆ CAN_F10R2_FB18_Msk

    - -
    -
    - - - - -
    #define CAN_F10R2_FB18_Msk   (0x1UL << CAN_F10R2_FB18_Pos)
    -
    -

    0x00040000

    - -
    -
    - -

    ◆ CAN_F10R2_FB18

    - -
    -
    - - - - -
    #define CAN_F10R2_FB18   CAN_F10R2_FB18_Msk
    -
    -

    Filter bit 18

    - -
    -
    - -

    ◆ CAN_F10R2_FB19_Pos

    - -
    -
    - - - - -
    #define CAN_F10R2_FB19_Pos   (19U)
    -
    - -
    -
    - -

    ◆ CAN_F10R2_FB19_Msk

    - -
    -
    - - - - -
    #define CAN_F10R2_FB19_Msk   (0x1UL << CAN_F10R2_FB19_Pos)
    -
    -

    0x00080000

    - -
    -
    - -

    ◆ CAN_F10R2_FB19

    - -
    -
    - - - - -
    #define CAN_F10R2_FB19   CAN_F10R2_FB19_Msk
    -
    -

    Filter bit 19

    - -
    -
    - -

    ◆ CAN_F10R2_FB20_Pos

    - -
    -
    - - - - -
    #define CAN_F10R2_FB20_Pos   (20U)
    -
    - -
    -
    - -

    ◆ CAN_F10R2_FB20_Msk

    - -
    -
    - - - - -
    #define CAN_F10R2_FB20_Msk   (0x1UL << CAN_F10R2_FB20_Pos)
    -
    -

    0x00100000

    - -
    -
    - -

    ◆ CAN_F10R2_FB20

    - -
    -
    - - - - -
    #define CAN_F10R2_FB20   CAN_F10R2_FB20_Msk
    -
    -

    Filter bit 20

    - -
    -
    - -

    ◆ CAN_F10R2_FB21_Pos

    - -
    -
    - - - - -
    #define CAN_F10R2_FB21_Pos   (21U)
    -
    - -
    -
    - -

    ◆ CAN_F10R2_FB21_Msk

    - -
    -
    - - - - -
    #define CAN_F10R2_FB21_Msk   (0x1UL << CAN_F10R2_FB21_Pos)
    -
    -

    0x00200000

    - -
    -
    - -

    ◆ CAN_F10R2_FB21

    - -
    -
    - - - - -
    #define CAN_F10R2_FB21   CAN_F10R2_FB21_Msk
    -
    -

    Filter bit 21

    - -
    -
    - -

    ◆ CAN_F10R2_FB22_Pos

    - -
    -
    - - - - -
    #define CAN_F10R2_FB22_Pos   (22U)
    -
    - -
    -
    - -

    ◆ CAN_F10R2_FB22_Msk

    - -
    -
    - - - - -
    #define CAN_F10R2_FB22_Msk   (0x1UL << CAN_F10R2_FB22_Pos)
    -
    -

    0x00400000

    - -
    -
    - -

    ◆ CAN_F10R2_FB22

    - -
    -
    - - - - -
    #define CAN_F10R2_FB22   CAN_F10R2_FB22_Msk
    -
    -

    Filter bit 22

    - -
    -
    - -

    ◆ CAN_F10R2_FB23_Pos

    - -
    -
    - - - - -
    #define CAN_F10R2_FB23_Pos   (23U)
    -
    - -
    -
    - -

    ◆ CAN_F10R2_FB23_Msk

    - -
    -
    - - - - -
    #define CAN_F10R2_FB23_Msk   (0x1UL << CAN_F10R2_FB23_Pos)
    -
    -

    0x00800000

    - -
    -
    - -

    ◆ CAN_F10R2_FB23

    - -
    -
    - - - - -
    #define CAN_F10R2_FB23   CAN_F10R2_FB23_Msk
    -
    -

    Filter bit 23

    - -
    -
    - -

    ◆ CAN_F10R2_FB24_Pos

    - -
    -
    - - - - -
    #define CAN_F10R2_FB24_Pos   (24U)
    -
    - -
    -
    - -

    ◆ CAN_F10R2_FB24_Msk

    - -
    -
    - - - - -
    #define CAN_F10R2_FB24_Msk   (0x1UL << CAN_F10R2_FB24_Pos)
    -
    -

    0x01000000

    - -
    -
    - -

    ◆ CAN_F10R2_FB24

    - -
    -
    - - - - -
    #define CAN_F10R2_FB24   CAN_F10R2_FB24_Msk
    -
    -

    Filter bit 24

    - -
    -
    - -

    ◆ CAN_F10R2_FB25_Pos

    - -
    -
    - - - - -
    #define CAN_F10R2_FB25_Pos   (25U)
    -
    - -
    -
    - -

    ◆ CAN_F10R2_FB25_Msk

    - -
    -
    - - - - -
    #define CAN_F10R2_FB25_Msk   (0x1UL << CAN_F10R2_FB25_Pos)
    -
    -

    0x02000000

    - -
    -
    - -

    ◆ CAN_F10R2_FB25

    - -
    -
    - - - - -
    #define CAN_F10R2_FB25   CAN_F10R2_FB25_Msk
    -
    -

    Filter bit 25

    - -
    -
    - -

    ◆ CAN_F10R2_FB26_Pos

    - -
    -
    - - - - -
    #define CAN_F10R2_FB26_Pos   (26U)
    -
    - -
    -
    - -

    ◆ CAN_F10R2_FB26_Msk

    - -
    -
    - - - - -
    #define CAN_F10R2_FB26_Msk   (0x1UL << CAN_F10R2_FB26_Pos)
    -
    -

    0x04000000

    - -
    -
    - -

    ◆ CAN_F10R2_FB26

    - -
    -
    - - - - -
    #define CAN_F10R2_FB26   CAN_F10R2_FB26_Msk
    -
    -

    Filter bit 26

    - -
    -
    - -

    ◆ CAN_F10R2_FB27_Pos

    - -
    -
    - - - - -
    #define CAN_F10R2_FB27_Pos   (27U)
    -
    - -
    -
    - -

    ◆ CAN_F10R2_FB27_Msk

    - -
    -
    - - - - -
    #define CAN_F10R2_FB27_Msk   (0x1UL << CAN_F10R2_FB27_Pos)
    -
    -

    0x08000000

    - -
    -
    - -

    ◆ CAN_F10R2_FB27

    - -
    -
    - - - - -
    #define CAN_F10R2_FB27   CAN_F10R2_FB27_Msk
    -
    -

    Filter bit 27

    - -
    -
    - -

    ◆ CAN_F10R2_FB28_Pos

    - -
    -
    - - - - -
    #define CAN_F10R2_FB28_Pos   (28U)
    -
    - -
    -
    - -

    ◆ CAN_F10R2_FB28_Msk

    - -
    -
    - - - - -
    #define CAN_F10R2_FB28_Msk   (0x1UL << CAN_F10R2_FB28_Pos)
    -
    -

    0x10000000

    - -
    -
    - -

    ◆ CAN_F10R2_FB28

    - -
    -
    - - - - -
    #define CAN_F10R2_FB28   CAN_F10R2_FB28_Msk
    -
    -

    Filter bit 28

    - -
    -
    - -

    ◆ CAN_F10R2_FB29_Pos

    - -
    -
    - - - - -
    #define CAN_F10R2_FB29_Pos   (29U)
    -
    - -
    -
    - -

    ◆ CAN_F10R2_FB29_Msk

    - -
    -
    - - - - -
    #define CAN_F10R2_FB29_Msk   (0x1UL << CAN_F10R2_FB29_Pos)
    -
    -

    0x20000000

    - -
    -
    - -

    ◆ CAN_F10R2_FB29

    - -
    -
    - - - - -
    #define CAN_F10R2_FB29   CAN_F10R2_FB29_Msk
    -
    -

    Filter bit 29

    - -
    -
    - -

    ◆ CAN_F10R2_FB30_Pos

    - -
    -
    - - - - -
    #define CAN_F10R2_FB30_Pos   (30U)
    -
    - -
    -
    - -

    ◆ CAN_F10R2_FB30_Msk

    - -
    -
    - - - - -
    #define CAN_F10R2_FB30_Msk   (0x1UL << CAN_F10R2_FB30_Pos)
    -
    -

    0x40000000

    - -
    -
    - -

    ◆ CAN_F10R2_FB30

    - -
    -
    - - - - -
    #define CAN_F10R2_FB30   CAN_F10R2_FB30_Msk
    -
    -

    Filter bit 30

    - -
    -
    - -

    ◆ CAN_F10R2_FB31_Pos

    - -
    -
    - - - - -
    #define CAN_F10R2_FB31_Pos   (31U)
    -
    - -
    -
    - -

    ◆ CAN_F10R2_FB31_Msk

    - -
    -
    - - - - -
    #define CAN_F10R2_FB31_Msk   (0x1UL << CAN_F10R2_FB31_Pos)
    -
    -

    0x80000000

    - -
    -
    - -

    ◆ CAN_F10R2_FB31

    - -
    -
    - - - - -
    #define CAN_F10R2_FB31   CAN_F10R2_FB31_Msk
    -
    -

    Filter bit 31

    - -
    -
    - -

    ◆ CAN_F11R2_FB0_Pos

    - -
    -
    - - - - -
    #define CAN_F11R2_FB0_Pos   (0U)
    -
    - -
    -
    - -

    ◆ CAN_F11R2_FB0_Msk

    - -
    -
    - - - - -
    #define CAN_F11R2_FB0_Msk   (0x1UL << CAN_F11R2_FB0_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ CAN_F11R2_FB0

    - -
    -
    - - - - -
    #define CAN_F11R2_FB0   CAN_F11R2_FB0_Msk
    -
    -

    Filter bit 0

    - -
    -
    - -

    ◆ CAN_F11R2_FB1_Pos

    - -
    -
    - - - - -
    #define CAN_F11R2_FB1_Pos   (1U)
    -
    - -
    -
    - -

    ◆ CAN_F11R2_FB1_Msk

    - -
    -
    - - - - -
    #define CAN_F11R2_FB1_Msk   (0x1UL << CAN_F11R2_FB1_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ CAN_F11R2_FB1

    - -
    -
    - - - - -
    #define CAN_F11R2_FB1   CAN_F11R2_FB1_Msk
    -
    -

    Filter bit 1

    - -
    -
    - -

    ◆ CAN_F11R2_FB2_Pos

    - -
    -
    - - - - -
    #define CAN_F11R2_FB2_Pos   (2U)
    -
    - -
    -
    - -

    ◆ CAN_F11R2_FB2_Msk

    - -
    -
    - - - - -
    #define CAN_F11R2_FB2_Msk   (0x1UL << CAN_F11R2_FB2_Pos)
    -
    -

    0x00000004

    - -
    -
    - -

    ◆ CAN_F11R2_FB2

    - -
    -
    - - - - -
    #define CAN_F11R2_FB2   CAN_F11R2_FB2_Msk
    -
    -

    Filter bit 2

    - -
    -
    - -

    ◆ CAN_F11R2_FB3_Pos

    - -
    -
    - - - - -
    #define CAN_F11R2_FB3_Pos   (3U)
    -
    - -
    -
    - -

    ◆ CAN_F11R2_FB3_Msk

    - -
    -
    - - - - -
    #define CAN_F11R2_FB3_Msk   (0x1UL << CAN_F11R2_FB3_Pos)
    -
    -

    0x00000008

    - -
    -
    - -

    ◆ CAN_F11R2_FB3

    - -
    -
    - - - - -
    #define CAN_F11R2_FB3   CAN_F11R2_FB3_Msk
    -
    -

    Filter bit 3

    - -
    -
    - -

    ◆ CAN_F11R2_FB4_Pos

    - -
    -
    - - - - -
    #define CAN_F11R2_FB4_Pos   (4U)
    -
    - -
    -
    - -

    ◆ CAN_F11R2_FB4_Msk

    - -
    -
    - - - - -
    #define CAN_F11R2_FB4_Msk   (0x1UL << CAN_F11R2_FB4_Pos)
    -
    -

    0x00000010

    - -
    -
    - -

    ◆ CAN_F11R2_FB4

    - -
    -
    - - - - -
    #define CAN_F11R2_FB4   CAN_F11R2_FB4_Msk
    -
    -

    Filter bit 4

    - -
    -
    - -

    ◆ CAN_F11R2_FB5_Pos

    - -
    -
    - - - - -
    #define CAN_F11R2_FB5_Pos   (5U)
    -
    - -
    -
    - -

    ◆ CAN_F11R2_FB5_Msk

    - -
    -
    - - - - -
    #define CAN_F11R2_FB5_Msk   (0x1UL << CAN_F11R2_FB5_Pos)
    -
    -

    0x00000020

    - -
    -
    - -

    ◆ CAN_F11R2_FB5

    - -
    -
    - - - - -
    #define CAN_F11R2_FB5   CAN_F11R2_FB5_Msk
    -
    -

    Filter bit 5

    - -
    -
    - -

    ◆ CAN_F11R2_FB6_Pos

    - -
    -
    - - - - -
    #define CAN_F11R2_FB6_Pos   (6U)
    -
    - -
    -
    - -

    ◆ CAN_F11R2_FB6_Msk

    - -
    -
    - - - - -
    #define CAN_F11R2_FB6_Msk   (0x1UL << CAN_F11R2_FB6_Pos)
    -
    -

    0x00000040

    - -
    -
    - -

    ◆ CAN_F11R2_FB6

    - -
    -
    - - - - -
    #define CAN_F11R2_FB6   CAN_F11R2_FB6_Msk
    -
    -

    Filter bit 6

    - -
    -
    - -

    ◆ CAN_F11R2_FB7_Pos

    - -
    -
    - - - - -
    #define CAN_F11R2_FB7_Pos   (7U)
    -
    - -
    -
    - -

    ◆ CAN_F11R2_FB7_Msk

    - -
    -
    - - - - -
    #define CAN_F11R2_FB7_Msk   (0x1UL << CAN_F11R2_FB7_Pos)
    -
    -

    0x00000080

    - -
    -
    - -

    ◆ CAN_F11R2_FB7

    - -
    -
    - - - - -
    #define CAN_F11R2_FB7   CAN_F11R2_FB7_Msk
    -
    -

    Filter bit 7

    - -
    -
    - -

    ◆ CAN_F11R2_FB8_Pos

    - -
    -
    - - - - -
    #define CAN_F11R2_FB8_Pos   (8U)
    -
    - -
    -
    - -

    ◆ CAN_F11R2_FB8_Msk

    - -
    -
    - - - - -
    #define CAN_F11R2_FB8_Msk   (0x1UL << CAN_F11R2_FB8_Pos)
    -
    -

    0x00000100

    - -
    -
    - -

    ◆ CAN_F11R2_FB8

    - -
    -
    - - - - -
    #define CAN_F11R2_FB8   CAN_F11R2_FB8_Msk
    -
    -

    Filter bit 8

    - -
    -
    - -

    ◆ CAN_F11R2_FB9_Pos

    - -
    -
    - - - - -
    #define CAN_F11R2_FB9_Pos   (9U)
    -
    - -
    -
    - -

    ◆ CAN_F11R2_FB9_Msk

    - -
    -
    - - - - -
    #define CAN_F11R2_FB9_Msk   (0x1UL << CAN_F11R2_FB9_Pos)
    -
    -

    0x00000200

    - -
    -
    - -

    ◆ CAN_F11R2_FB9

    - -
    -
    - - - - -
    #define CAN_F11R2_FB9   CAN_F11R2_FB9_Msk
    -
    -

    Filter bit 9

    - -
    -
    - -

    ◆ CAN_F11R2_FB10_Pos

    - -
    -
    - - - - -
    #define CAN_F11R2_FB10_Pos   (10U)
    -
    - -
    -
    - -

    ◆ CAN_F11R2_FB10_Msk

    - -
    -
    - - - - -
    #define CAN_F11R2_FB10_Msk   (0x1UL << CAN_F11R2_FB10_Pos)
    -
    -

    0x00000400

    - -
    -
    - -

    ◆ CAN_F11R2_FB10

    - -
    -
    - - - - -
    #define CAN_F11R2_FB10   CAN_F11R2_FB10_Msk
    -
    -

    Filter bit 10

    - -
    -
    - -

    ◆ CAN_F11R2_FB11_Pos

    - -
    -
    - - - - -
    #define CAN_F11R2_FB11_Pos   (11U)
    -
    - -
    -
    - -

    ◆ CAN_F11R2_FB11_Msk

    - -
    -
    - - - - -
    #define CAN_F11R2_FB11_Msk   (0x1UL << CAN_F11R2_FB11_Pos)
    -
    -

    0x00000800

    - -
    -
    - -

    ◆ CAN_F11R2_FB11

    - -
    -
    - - - - -
    #define CAN_F11R2_FB11   CAN_F11R2_FB11_Msk
    -
    -

    Filter bit 11

    - -
    -
    - -

    ◆ CAN_F11R2_FB12_Pos

    - -
    -
    - - - - -
    #define CAN_F11R2_FB12_Pos   (12U)
    -
    - -
    -
    - -

    ◆ CAN_F11R2_FB12_Msk

    - -
    -
    - - - - -
    #define CAN_F11R2_FB12_Msk   (0x1UL << CAN_F11R2_FB12_Pos)
    -
    -

    0x00001000

    - -
    -
    - -

    ◆ CAN_F11R2_FB12

    - -
    -
    - - - - -
    #define CAN_F11R2_FB12   CAN_F11R2_FB12_Msk
    -
    -

    Filter bit 12

    - -
    -
    - -

    ◆ CAN_F11R2_FB13_Pos

    - -
    -
    - - - - -
    #define CAN_F11R2_FB13_Pos   (13U)
    -
    - -
    -
    - -

    ◆ CAN_F11R2_FB13_Msk

    - -
    -
    - - - - -
    #define CAN_F11R2_FB13_Msk   (0x1UL << CAN_F11R2_FB13_Pos)
    -
    -

    0x00002000

    - -
    -
    - -

    ◆ CAN_F11R2_FB13

    - -
    -
    - - - - -
    #define CAN_F11R2_FB13   CAN_F11R2_FB13_Msk
    -
    -

    Filter bit 13

    - -
    -
    - -

    ◆ CAN_F11R2_FB14_Pos

    - -
    -
    - - - - -
    #define CAN_F11R2_FB14_Pos   (14U)
    -
    - -
    -
    - -

    ◆ CAN_F11R2_FB14_Msk

    - -
    -
    - - - - -
    #define CAN_F11R2_FB14_Msk   (0x1UL << CAN_F11R2_FB14_Pos)
    -
    -

    0x00004000

    - -
    -
    - -

    ◆ CAN_F11R2_FB14

    - -
    -
    - - - - -
    #define CAN_F11R2_FB14   CAN_F11R2_FB14_Msk
    -
    -

    Filter bit 14

    - -
    -
    - -

    ◆ CAN_F11R2_FB15_Pos

    - -
    -
    - - - - -
    #define CAN_F11R2_FB15_Pos   (15U)
    -
    - -
    -
    - -

    ◆ CAN_F11R2_FB15_Msk

    - -
    -
    - - - - -
    #define CAN_F11R2_FB15_Msk   (0x1UL << CAN_F11R2_FB15_Pos)
    -
    -

    0x00008000

    - -
    -
    - -

    ◆ CAN_F11R2_FB15

    - -
    -
    - - - - -
    #define CAN_F11R2_FB15   CAN_F11R2_FB15_Msk
    -
    -

    Filter bit 15

    - -
    -
    - -

    ◆ CAN_F11R2_FB16_Pos

    - -
    -
    - - - - -
    #define CAN_F11R2_FB16_Pos   (16U)
    -
    - -
    -
    - -

    ◆ CAN_F11R2_FB16_Msk

    - -
    -
    - - - - -
    #define CAN_F11R2_FB16_Msk   (0x1UL << CAN_F11R2_FB16_Pos)
    -
    -

    0x00010000

    - -
    -
    - -

    ◆ CAN_F11R2_FB16

    - -
    -
    - - - - -
    #define CAN_F11R2_FB16   CAN_F11R2_FB16_Msk
    -
    -

    Filter bit 16

    - -
    -
    - -

    ◆ CAN_F11R2_FB17_Pos

    - -
    -
    - - - - -
    #define CAN_F11R2_FB17_Pos   (17U)
    -
    - -
    -
    - -

    ◆ CAN_F11R2_FB17_Msk

    - -
    -
    - - - - -
    #define CAN_F11R2_FB17_Msk   (0x1UL << CAN_F11R2_FB17_Pos)
    -
    -

    0x00020000

    - -
    -
    - -

    ◆ CAN_F11R2_FB17

    - -
    -
    - - - - -
    #define CAN_F11R2_FB17   CAN_F11R2_FB17_Msk
    -
    -

    Filter bit 17

    - -
    -
    - -

    ◆ CAN_F11R2_FB18_Pos

    - -
    -
    - - - - -
    #define CAN_F11R2_FB18_Pos   (18U)
    -
    - -
    -
    - -

    ◆ CAN_F11R2_FB18_Msk

    - -
    -
    - - - - -
    #define CAN_F11R2_FB18_Msk   (0x1UL << CAN_F11R2_FB18_Pos)
    -
    -

    0x00040000

    - -
    -
    - -

    ◆ CAN_F11R2_FB18

    - -
    -
    - - - - -
    #define CAN_F11R2_FB18   CAN_F11R2_FB18_Msk
    -
    -

    Filter bit 18

    - -
    -
    - -

    ◆ CAN_F11R2_FB19_Pos

    - -
    -
    - - - - -
    #define CAN_F11R2_FB19_Pos   (19U)
    -
    - -
    -
    - -

    ◆ CAN_F11R2_FB19_Msk

    - -
    -
    - - - - -
    #define CAN_F11R2_FB19_Msk   (0x1UL << CAN_F11R2_FB19_Pos)
    -
    -

    0x00080000

    - -
    -
    - -

    ◆ CAN_F11R2_FB19

    - -
    -
    - - - - -
    #define CAN_F11R2_FB19   CAN_F11R2_FB19_Msk
    -
    -

    Filter bit 19

    - -
    -
    - -

    ◆ CAN_F11R2_FB20_Pos

    - -
    -
    - - - - -
    #define CAN_F11R2_FB20_Pos   (20U)
    -
    - -
    -
    - -

    ◆ CAN_F11R2_FB20_Msk

    - -
    -
    - - - - -
    #define CAN_F11R2_FB20_Msk   (0x1UL << CAN_F11R2_FB20_Pos)
    -
    -

    0x00100000

    - -
    -
    - -

    ◆ CAN_F11R2_FB20

    - -
    -
    - - - - -
    #define CAN_F11R2_FB20   CAN_F11R2_FB20_Msk
    -
    -

    Filter bit 20

    - -
    -
    - -

    ◆ CAN_F11R2_FB21_Pos

    - -
    -
    - - - - -
    #define CAN_F11R2_FB21_Pos   (21U)
    -
    - -
    -
    - -

    ◆ CAN_F11R2_FB21_Msk

    - -
    -
    - - - - -
    #define CAN_F11R2_FB21_Msk   (0x1UL << CAN_F11R2_FB21_Pos)
    -
    -

    0x00200000

    - -
    -
    - -

    ◆ CAN_F11R2_FB21

    - -
    -
    - - - - -
    #define CAN_F11R2_FB21   CAN_F11R2_FB21_Msk
    -
    -

    Filter bit 21

    - -
    -
    - -

    ◆ CAN_F11R2_FB22_Pos

    - -
    -
    - - - - -
    #define CAN_F11R2_FB22_Pos   (22U)
    -
    - -
    -
    - -

    ◆ CAN_F11R2_FB22_Msk

    - -
    -
    - - - - -
    #define CAN_F11R2_FB22_Msk   (0x1UL << CAN_F11R2_FB22_Pos)
    -
    -

    0x00400000

    - -
    -
    - -

    ◆ CAN_F11R2_FB22

    - -
    -
    - - - - -
    #define CAN_F11R2_FB22   CAN_F11R2_FB22_Msk
    -
    -

    Filter bit 22

    - -
    -
    - -

    ◆ CAN_F11R2_FB23_Pos

    - -
    -
    - - - - -
    #define CAN_F11R2_FB23_Pos   (23U)
    -
    - -
    -
    - -

    ◆ CAN_F11R2_FB23_Msk

    - -
    -
    - - - - -
    #define CAN_F11R2_FB23_Msk   (0x1UL << CAN_F11R2_FB23_Pos)
    -
    -

    0x00800000

    - -
    -
    - -

    ◆ CAN_F11R2_FB23

    - -
    -
    - - - - -
    #define CAN_F11R2_FB23   CAN_F11R2_FB23_Msk
    -
    -

    Filter bit 23

    - -
    -
    - -

    ◆ CAN_F11R2_FB24_Pos

    - -
    -
    - - - - -
    #define CAN_F11R2_FB24_Pos   (24U)
    -
    - -
    -
    - -

    ◆ CAN_F11R2_FB24_Msk

    - -
    -
    - - - - -
    #define CAN_F11R2_FB24_Msk   (0x1UL << CAN_F11R2_FB24_Pos)
    -
    -

    0x01000000

    - -
    -
    - -

    ◆ CAN_F11R2_FB24

    - -
    -
    - - - - -
    #define CAN_F11R2_FB24   CAN_F11R2_FB24_Msk
    -
    -

    Filter bit 24

    - -
    -
    - -

    ◆ CAN_F11R2_FB25_Pos

    - -
    -
    - - - - -
    #define CAN_F11R2_FB25_Pos   (25U)
    -
    - -
    -
    - -

    ◆ CAN_F11R2_FB25_Msk

    - -
    -
    - - - - -
    #define CAN_F11R2_FB25_Msk   (0x1UL << CAN_F11R2_FB25_Pos)
    -
    -

    0x02000000

    - -
    -
    - -

    ◆ CAN_F11R2_FB25

    - -
    -
    - - - - -
    #define CAN_F11R2_FB25   CAN_F11R2_FB25_Msk
    -
    -

    Filter bit 25

    - -
    -
    - -

    ◆ CAN_F11R2_FB26_Pos

    - -
    -
    - - - - -
    #define CAN_F11R2_FB26_Pos   (26U)
    -
    - -
    -
    - -

    ◆ CAN_F11R2_FB26_Msk

    - -
    -
    - - - - -
    #define CAN_F11R2_FB26_Msk   (0x1UL << CAN_F11R2_FB26_Pos)
    -
    -

    0x04000000

    - -
    -
    - -

    ◆ CAN_F11R2_FB26

    - -
    -
    - - - - -
    #define CAN_F11R2_FB26   CAN_F11R2_FB26_Msk
    -
    -

    Filter bit 26

    - -
    -
    - -

    ◆ CAN_F11R2_FB27_Pos

    - -
    -
    - - - - -
    #define CAN_F11R2_FB27_Pos   (27U)
    -
    - -
    -
    - -

    ◆ CAN_F11R2_FB27_Msk

    - -
    -
    - - - - -
    #define CAN_F11R2_FB27_Msk   (0x1UL << CAN_F11R2_FB27_Pos)
    -
    -

    0x08000000

    - -
    -
    - -

    ◆ CAN_F11R2_FB27

    - -
    -
    - - - - -
    #define CAN_F11R2_FB27   CAN_F11R2_FB27_Msk
    -
    -

    Filter bit 27

    - -
    -
    - -

    ◆ CAN_F11R2_FB28_Pos

    - -
    -
    - - - - -
    #define CAN_F11R2_FB28_Pos   (28U)
    -
    - -
    -
    - -

    ◆ CAN_F11R2_FB28_Msk

    - -
    -
    - - - - -
    #define CAN_F11R2_FB28_Msk   (0x1UL << CAN_F11R2_FB28_Pos)
    -
    -

    0x10000000

    - -
    -
    - -

    ◆ CAN_F11R2_FB28

    - -
    -
    - - - - -
    #define CAN_F11R2_FB28   CAN_F11R2_FB28_Msk
    -
    -

    Filter bit 28

    - -
    -
    - -

    ◆ CAN_F11R2_FB29_Pos

    - -
    -
    - - - - -
    #define CAN_F11R2_FB29_Pos   (29U)
    -
    - -
    -
    - -

    ◆ CAN_F11R2_FB29_Msk

    - -
    -
    - - - - -
    #define CAN_F11R2_FB29_Msk   (0x1UL << CAN_F11R2_FB29_Pos)
    -
    -

    0x20000000

    - -
    -
    - -

    ◆ CAN_F11R2_FB29

    - -
    -
    - - - - -
    #define CAN_F11R2_FB29   CAN_F11R2_FB29_Msk
    -
    -

    Filter bit 29

    - -
    -
    - -

    ◆ CAN_F11R2_FB30_Pos

    - -
    -
    - - - - -
    #define CAN_F11R2_FB30_Pos   (30U)
    -
    - -
    -
    - -

    ◆ CAN_F11R2_FB30_Msk

    - -
    -
    - - - - -
    #define CAN_F11R2_FB30_Msk   (0x1UL << CAN_F11R2_FB30_Pos)
    -
    -

    0x40000000

    - -
    -
    - -

    ◆ CAN_F11R2_FB30

    - -
    -
    - - - - -
    #define CAN_F11R2_FB30   CAN_F11R2_FB30_Msk
    -
    -

    Filter bit 30

    - -
    -
    - -

    ◆ CAN_F11R2_FB31_Pos

    - -
    -
    - - - - -
    #define CAN_F11R2_FB31_Pos   (31U)
    -
    - -
    -
    - -

    ◆ CAN_F11R2_FB31_Msk

    - -
    -
    - - - - -
    #define CAN_F11R2_FB31_Msk   (0x1UL << CAN_F11R2_FB31_Pos)
    -
    -

    0x80000000

    - -
    -
    - -

    ◆ CAN_F11R2_FB31

    - -
    -
    - - - - -
    #define CAN_F11R2_FB31   CAN_F11R2_FB31_Msk
    -
    -

    Filter bit 31

    - -
    -
    - -

    ◆ CAN_F12R2_FB0_Pos

    - -
    -
    - - - - -
    #define CAN_F12R2_FB0_Pos   (0U)
    -
    - -
    -
    - -

    ◆ CAN_F12R2_FB0_Msk

    - -
    -
    - - - - -
    #define CAN_F12R2_FB0_Msk   (0x1UL << CAN_F12R2_FB0_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ CAN_F12R2_FB0

    - -
    -
    - - - - -
    #define CAN_F12R2_FB0   CAN_F12R2_FB0_Msk
    -
    -

    Filter bit 0

    - -
    -
    - -

    ◆ CAN_F12R2_FB1_Pos

    - -
    -
    - - - - -
    #define CAN_F12R2_FB1_Pos   (1U)
    -
    - -
    -
    - -

    ◆ CAN_F12R2_FB1_Msk

    - -
    -
    - - - - -
    #define CAN_F12R2_FB1_Msk   (0x1UL << CAN_F12R2_FB1_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ CAN_F12R2_FB1

    - -
    -
    - - - - -
    #define CAN_F12R2_FB1   CAN_F12R2_FB1_Msk
    -
    -

    Filter bit 1

    - -
    -
    - -

    ◆ CAN_F12R2_FB2_Pos

    - -
    -
    - - - - -
    #define CAN_F12R2_FB2_Pos   (2U)
    -
    - -
    -
    - -

    ◆ CAN_F12R2_FB2_Msk

    - -
    -
    - - - - -
    #define CAN_F12R2_FB2_Msk   (0x1UL << CAN_F12R2_FB2_Pos)
    -
    -

    0x00000004

    - -
    -
    - -

    ◆ CAN_F12R2_FB2

    - -
    -
    - - - - -
    #define CAN_F12R2_FB2   CAN_F12R2_FB2_Msk
    -
    -

    Filter bit 2

    - -
    -
    - -

    ◆ CAN_F12R2_FB3_Pos

    - -
    -
    - - - - -
    #define CAN_F12R2_FB3_Pos   (3U)
    -
    - -
    -
    - -

    ◆ CAN_F12R2_FB3_Msk

    - -
    -
    - - - - -
    #define CAN_F12R2_FB3_Msk   (0x1UL << CAN_F12R2_FB3_Pos)
    -
    -

    0x00000008

    - -
    -
    - -

    ◆ CAN_F12R2_FB3

    - -
    -
    - - - - -
    #define CAN_F12R2_FB3   CAN_F12R2_FB3_Msk
    -
    -

    Filter bit 3

    - -
    -
    - -

    ◆ CAN_F12R2_FB4_Pos

    - -
    -
    - - - - -
    #define CAN_F12R2_FB4_Pos   (4U)
    -
    - -
    -
    - -

    ◆ CAN_F12R2_FB4_Msk

    - -
    -
    - - - - -
    #define CAN_F12R2_FB4_Msk   (0x1UL << CAN_F12R2_FB4_Pos)
    -
    -

    0x00000010

    - -
    -
    - -

    ◆ CAN_F12R2_FB4

    - -
    -
    - - - - -
    #define CAN_F12R2_FB4   CAN_F12R2_FB4_Msk
    -
    -

    Filter bit 4

    - -
    -
    - -

    ◆ CAN_F12R2_FB5_Pos

    - -
    -
    - - - - -
    #define CAN_F12R2_FB5_Pos   (5U)
    -
    - -
    -
    - -

    ◆ CAN_F12R2_FB5_Msk

    - -
    -
    - - - - -
    #define CAN_F12R2_FB5_Msk   (0x1UL << CAN_F12R2_FB5_Pos)
    -
    -

    0x00000020

    - -
    -
    - -

    ◆ CAN_F12R2_FB5

    - -
    -
    - - - - -
    #define CAN_F12R2_FB5   CAN_F12R2_FB5_Msk
    -
    -

    Filter bit 5

    - -
    -
    - -

    ◆ CAN_F12R2_FB6_Pos

    - -
    -
    - - - - -
    #define CAN_F12R2_FB6_Pos   (6U)
    -
    - -
    -
    - -

    ◆ CAN_F12R2_FB6_Msk

    - -
    -
    - - - - -
    #define CAN_F12R2_FB6_Msk   (0x1UL << CAN_F12R2_FB6_Pos)
    -
    -

    0x00000040

    - -
    -
    - -

    ◆ CAN_F12R2_FB6

    - -
    -
    - - - - -
    #define CAN_F12R2_FB6   CAN_F12R2_FB6_Msk
    -
    -

    Filter bit 6

    - -
    -
    - -

    ◆ CAN_F12R2_FB7_Pos

    - -
    -
    - - - - -
    #define CAN_F12R2_FB7_Pos   (7U)
    -
    - -
    -
    - -

    ◆ CAN_F12R2_FB7_Msk

    - -
    -
    - - - - -
    #define CAN_F12R2_FB7_Msk   (0x1UL << CAN_F12R2_FB7_Pos)
    -
    -

    0x00000080

    - -
    -
    - -

    ◆ CAN_F12R2_FB7

    - -
    -
    - - - - -
    #define CAN_F12R2_FB7   CAN_F12R2_FB7_Msk
    -
    -

    Filter bit 7

    - -
    -
    - -

    ◆ CAN_F12R2_FB8_Pos

    - -
    -
    - - - - -
    #define CAN_F12R2_FB8_Pos   (8U)
    -
    - -
    -
    - -

    ◆ CAN_F12R2_FB8_Msk

    - -
    -
    - - - - -
    #define CAN_F12R2_FB8_Msk   (0x1UL << CAN_F12R2_FB8_Pos)
    -
    -

    0x00000100

    - -
    -
    - -

    ◆ CAN_F12R2_FB8

    - -
    -
    - - - - -
    #define CAN_F12R2_FB8   CAN_F12R2_FB8_Msk
    -
    -

    Filter bit 8

    - -
    -
    - -

    ◆ CAN_F12R2_FB9_Pos

    - -
    -
    - - - - -
    #define CAN_F12R2_FB9_Pos   (9U)
    -
    - -
    -
    - -

    ◆ CAN_F12R2_FB9_Msk

    - -
    -
    - - - - -
    #define CAN_F12R2_FB9_Msk   (0x1UL << CAN_F12R2_FB9_Pos)
    -
    -

    0x00000200

    - -
    -
    - -

    ◆ CAN_F12R2_FB9

    - -
    -
    - - - - -
    #define CAN_F12R2_FB9   CAN_F12R2_FB9_Msk
    -
    -

    Filter bit 9

    - -
    -
    - -

    ◆ CAN_F12R2_FB10_Pos

    - -
    -
    - - - - -
    #define CAN_F12R2_FB10_Pos   (10U)
    -
    - -
    -
    - -

    ◆ CAN_F12R2_FB10_Msk

    - -
    -
    - - - - -
    #define CAN_F12R2_FB10_Msk   (0x1UL << CAN_F12R2_FB10_Pos)
    -
    -

    0x00000400

    - -
    -
    - -

    ◆ CAN_F12R2_FB10

    - -
    -
    - - - - -
    #define CAN_F12R2_FB10   CAN_F12R2_FB10_Msk
    -
    -

    Filter bit 10

    - -
    -
    - -

    ◆ CAN_F12R2_FB11_Pos

    - -
    -
    - - - - -
    #define CAN_F12R2_FB11_Pos   (11U)
    -
    - -
    -
    - -

    ◆ CAN_F12R2_FB11_Msk

    - -
    -
    - - - - -
    #define CAN_F12R2_FB11_Msk   (0x1UL << CAN_F12R2_FB11_Pos)
    -
    -

    0x00000800

    - -
    -
    - -

    ◆ CAN_F12R2_FB11

    - -
    -
    - - - - -
    #define CAN_F12R2_FB11   CAN_F12R2_FB11_Msk
    -
    -

    Filter bit 11

    - -
    -
    - -

    ◆ CAN_F12R2_FB12_Pos

    - -
    -
    - - - - -
    #define CAN_F12R2_FB12_Pos   (12U)
    -
    - -
    -
    - -

    ◆ CAN_F12R2_FB12_Msk

    - -
    -
    - - - - -
    #define CAN_F12R2_FB12_Msk   (0x1UL << CAN_F12R2_FB12_Pos)
    -
    -

    0x00001000

    - -
    -
    - -

    ◆ CAN_F12R2_FB12

    - -
    -
    - - - - -
    #define CAN_F12R2_FB12   CAN_F12R2_FB12_Msk
    -
    -

    Filter bit 12

    - -
    -
    - -

    ◆ CAN_F12R2_FB13_Pos

    - -
    -
    - - - - -
    #define CAN_F12R2_FB13_Pos   (13U)
    -
    - -
    -
    - -

    ◆ CAN_F12R2_FB13_Msk

    - -
    -
    - - - - -
    #define CAN_F12R2_FB13_Msk   (0x1UL << CAN_F12R2_FB13_Pos)
    -
    -

    0x00002000

    - -
    -
    - -

    ◆ CAN_F12R2_FB13

    - -
    -
    - - - - -
    #define CAN_F12R2_FB13   CAN_F12R2_FB13_Msk
    -
    -

    Filter bit 13

    - -
    -
    - -

    ◆ CAN_F12R2_FB14_Pos

    - -
    -
    - - - - -
    #define CAN_F12R2_FB14_Pos   (14U)
    -
    - -
    -
    - -

    ◆ CAN_F12R2_FB14_Msk

    - -
    -
    - - - - -
    #define CAN_F12R2_FB14_Msk   (0x1UL << CAN_F12R2_FB14_Pos)
    -
    -

    0x00004000

    - -
    -
    - -

    ◆ CAN_F12R2_FB14

    - -
    -
    - - - - -
    #define CAN_F12R2_FB14   CAN_F12R2_FB14_Msk
    -
    -

    Filter bit 14

    - -
    -
    - -

    ◆ CAN_F12R2_FB15_Pos

    - -
    -
    - - - - -
    #define CAN_F12R2_FB15_Pos   (15U)
    -
    - -
    -
    - -

    ◆ CAN_F12R2_FB15_Msk

    - -
    -
    - - - - -
    #define CAN_F12R2_FB15_Msk   (0x1UL << CAN_F12R2_FB15_Pos)
    -
    -

    0x00008000

    - -
    -
    - -

    ◆ CAN_F12R2_FB15

    - -
    -
    - - - - -
    #define CAN_F12R2_FB15   CAN_F12R2_FB15_Msk
    -
    -

    Filter bit 15

    - -
    -
    - -

    ◆ CAN_F12R2_FB16_Pos

    - -
    -
    - - - - -
    #define CAN_F12R2_FB16_Pos   (16U)
    -
    - -
    -
    - -

    ◆ CAN_F12R2_FB16_Msk

    - -
    -
    - - - - -
    #define CAN_F12R2_FB16_Msk   (0x1UL << CAN_F12R2_FB16_Pos)
    -
    -

    0x00010000

    - -
    -
    - -

    ◆ CAN_F12R2_FB16

    - -
    -
    - - - - -
    #define CAN_F12R2_FB16   CAN_F12R2_FB16_Msk
    -
    -

    Filter bit 16

    - -
    -
    - -

    ◆ CAN_F12R2_FB17_Pos

    - -
    -
    - - - - -
    #define CAN_F12R2_FB17_Pos   (17U)
    -
    - -
    -
    - -

    ◆ CAN_F12R2_FB17_Msk

    - -
    -
    - - - - -
    #define CAN_F12R2_FB17_Msk   (0x1UL << CAN_F12R2_FB17_Pos)
    -
    -

    0x00020000

    - -
    -
    - -

    ◆ CAN_F12R2_FB17

    - -
    -
    - - - - -
    #define CAN_F12R2_FB17   CAN_F12R2_FB17_Msk
    -
    -

    Filter bit 17

    - -
    -
    - -

    ◆ CAN_F12R2_FB18_Pos

    - -
    -
    - - - - -
    #define CAN_F12R2_FB18_Pos   (18U)
    -
    - -
    -
    - -

    ◆ CAN_F12R2_FB18_Msk

    - -
    -
    - - - - -
    #define CAN_F12R2_FB18_Msk   (0x1UL << CAN_F12R2_FB18_Pos)
    -
    -

    0x00040000

    - -
    -
    - -

    ◆ CAN_F12R2_FB18

    - -
    -
    - - - - -
    #define CAN_F12R2_FB18   CAN_F12R2_FB18_Msk
    -
    -

    Filter bit 18

    - -
    -
    - -

    ◆ CAN_F12R2_FB19_Pos

    - -
    -
    - - - - -
    #define CAN_F12R2_FB19_Pos   (19U)
    -
    - -
    -
    - -

    ◆ CAN_F12R2_FB19_Msk

    - -
    -
    - - - - -
    #define CAN_F12R2_FB19_Msk   (0x1UL << CAN_F12R2_FB19_Pos)
    -
    -

    0x00080000

    - -
    -
    - -

    ◆ CAN_F12R2_FB19

    - -
    -
    - - - - -
    #define CAN_F12R2_FB19   CAN_F12R2_FB19_Msk
    -
    -

    Filter bit 19

    - -
    -
    - -

    ◆ CAN_F12R2_FB20_Pos

    - -
    -
    - - - - -
    #define CAN_F12R2_FB20_Pos   (20U)
    -
    - -
    -
    - -

    ◆ CAN_F12R2_FB20_Msk

    - -
    -
    - - - - -
    #define CAN_F12R2_FB20_Msk   (0x1UL << CAN_F12R2_FB20_Pos)
    -
    -

    0x00100000

    - -
    -
    - -

    ◆ CAN_F12R2_FB20

    - -
    -
    - - - - -
    #define CAN_F12R2_FB20   CAN_F12R2_FB20_Msk
    -
    -

    Filter bit 20

    - -
    -
    - -

    ◆ CAN_F12R2_FB21_Pos

    - -
    -
    - - - - -
    #define CAN_F12R2_FB21_Pos   (21U)
    -
    - -
    -
    - -

    ◆ CAN_F12R2_FB21_Msk

    - -
    -
    - - - - -
    #define CAN_F12R2_FB21_Msk   (0x1UL << CAN_F12R2_FB21_Pos)
    -
    -

    0x00200000

    - -
    -
    - -

    ◆ CAN_F12R2_FB21

    - -
    -
    - - - - -
    #define CAN_F12R2_FB21   CAN_F12R2_FB21_Msk
    -
    -

    Filter bit 21

    - -
    -
    - -

    ◆ CAN_F12R2_FB22_Pos

    - -
    -
    - - - - -
    #define CAN_F12R2_FB22_Pos   (22U)
    -
    - -
    -
    - -

    ◆ CAN_F12R2_FB22_Msk

    - -
    -
    - - - - -
    #define CAN_F12R2_FB22_Msk   (0x1UL << CAN_F12R2_FB22_Pos)
    -
    -

    0x00400000

    - -
    -
    - -

    ◆ CAN_F12R2_FB22

    - -
    -
    - - - - -
    #define CAN_F12R2_FB22   CAN_F12R2_FB22_Msk
    -
    -

    Filter bit 22

    - -
    -
    - -

    ◆ CAN_F12R2_FB23_Pos

    - -
    -
    - - - - -
    #define CAN_F12R2_FB23_Pos   (23U)
    -
    - -
    -
    - -

    ◆ CAN_F12R2_FB23_Msk

    - -
    -
    - - - - -
    #define CAN_F12R2_FB23_Msk   (0x1UL << CAN_F12R2_FB23_Pos)
    -
    -

    0x00800000

    - -
    -
    - -

    ◆ CAN_F12R2_FB23

    - -
    -
    - - - - -
    #define CAN_F12R2_FB23   CAN_F12R2_FB23_Msk
    -
    -

    Filter bit 23

    - -
    -
    - -

    ◆ CAN_F12R2_FB24_Pos

    - -
    -
    - - - - -
    #define CAN_F12R2_FB24_Pos   (24U)
    -
    - -
    -
    - -

    ◆ CAN_F12R2_FB24_Msk

    - -
    -
    - - - - -
    #define CAN_F12R2_FB24_Msk   (0x1UL << CAN_F12R2_FB24_Pos)
    -
    -

    0x01000000

    - -
    -
    - -

    ◆ CAN_F12R2_FB24

    - -
    -
    - - - - -
    #define CAN_F12R2_FB24   CAN_F12R2_FB24_Msk
    -
    -

    Filter bit 24

    - -
    -
    - -

    ◆ CAN_F12R2_FB25_Pos

    - -
    -
    - - - - -
    #define CAN_F12R2_FB25_Pos   (25U)
    -
    - -
    -
    - -

    ◆ CAN_F12R2_FB25_Msk

    - -
    -
    - - - - -
    #define CAN_F12R2_FB25_Msk   (0x1UL << CAN_F12R2_FB25_Pos)
    -
    -

    0x02000000

    - -
    -
    - -

    ◆ CAN_F12R2_FB25

    - -
    -
    - - - - -
    #define CAN_F12R2_FB25   CAN_F12R2_FB25_Msk
    -
    -

    Filter bit 25

    - -
    -
    - -

    ◆ CAN_F12R2_FB26_Pos

    - -
    -
    - - - - -
    #define CAN_F12R2_FB26_Pos   (26U)
    -
    - -
    -
    - -

    ◆ CAN_F12R2_FB26_Msk

    - -
    -
    - - - - -
    #define CAN_F12R2_FB26_Msk   (0x1UL << CAN_F12R2_FB26_Pos)
    -
    -

    0x04000000

    - -
    -
    - -

    ◆ CAN_F12R2_FB26

    - -
    -
    - - - - -
    #define CAN_F12R2_FB26   CAN_F12R2_FB26_Msk
    -
    -

    Filter bit 26

    - -
    -
    - -

    ◆ CAN_F12R2_FB27_Pos

    - -
    -
    - - - - -
    #define CAN_F12R2_FB27_Pos   (27U)
    -
    - -
    -
    - -

    ◆ CAN_F12R2_FB27_Msk

    - -
    -
    - - - - -
    #define CAN_F12R2_FB27_Msk   (0x1UL << CAN_F12R2_FB27_Pos)
    -
    -

    0x08000000

    - -
    -
    - -

    ◆ CAN_F12R2_FB27

    - -
    -
    - - - - -
    #define CAN_F12R2_FB27   CAN_F12R2_FB27_Msk
    -
    -

    Filter bit 27

    - -
    -
    - -

    ◆ CAN_F12R2_FB28_Pos

    - -
    -
    - - - - -
    #define CAN_F12R2_FB28_Pos   (28U)
    -
    - -
    -
    - -

    ◆ CAN_F12R2_FB28_Msk

    - -
    -
    - - - - -
    #define CAN_F12R2_FB28_Msk   (0x1UL << CAN_F12R2_FB28_Pos)
    -
    -

    0x10000000

    - -
    -
    - -

    ◆ CAN_F12R2_FB28

    - -
    -
    - - - - -
    #define CAN_F12R2_FB28   CAN_F12R2_FB28_Msk
    -
    -

    Filter bit 28

    - -
    -
    - -

    ◆ CAN_F12R2_FB29_Pos

    - -
    -
    - - - - -
    #define CAN_F12R2_FB29_Pos   (29U)
    -
    - -
    -
    - -

    ◆ CAN_F12R2_FB29_Msk

    - -
    -
    - - - - -
    #define CAN_F12R2_FB29_Msk   (0x1UL << CAN_F12R2_FB29_Pos)
    -
    -

    0x20000000

    - -
    -
    - -

    ◆ CAN_F12R2_FB29

    - -
    -
    - - - - -
    #define CAN_F12R2_FB29   CAN_F12R2_FB29_Msk
    -
    -

    Filter bit 29

    - -
    -
    - -

    ◆ CAN_F12R2_FB30_Pos

    - -
    -
    - - - - -
    #define CAN_F12R2_FB30_Pos   (30U)
    -
    - -
    -
    - -

    ◆ CAN_F12R2_FB30_Msk

    - -
    -
    - - - - -
    #define CAN_F12R2_FB30_Msk   (0x1UL << CAN_F12R2_FB30_Pos)
    -
    -

    0x40000000

    - -
    -
    - -

    ◆ CAN_F12R2_FB30

    - -
    -
    - - - - -
    #define CAN_F12R2_FB30   CAN_F12R2_FB30_Msk
    -
    -

    Filter bit 30

    - -
    -
    - -

    ◆ CAN_F12R2_FB31_Pos

    - -
    -
    - - - - -
    #define CAN_F12R2_FB31_Pos   (31U)
    -
    - -
    -
    - -

    ◆ CAN_F12R2_FB31_Msk

    - -
    -
    - - - - -
    #define CAN_F12R2_FB31_Msk   (0x1UL << CAN_F12R2_FB31_Pos)
    -
    -

    0x80000000

    - -
    -
    - -

    ◆ CAN_F12R2_FB31

    - -
    -
    - - - - -
    #define CAN_F12R2_FB31   CAN_F12R2_FB31_Msk
    -
    -

    Filter bit 31

    - -
    -
    - -

    ◆ CAN_F13R2_FB0_Pos

    - -
    -
    - - - - -
    #define CAN_F13R2_FB0_Pos   (0U)
    -
    - -
    -
    - -

    ◆ CAN_F13R2_FB0_Msk

    - -
    -
    - - - - -
    #define CAN_F13R2_FB0_Msk   (0x1UL << CAN_F13R2_FB0_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ CAN_F13R2_FB0

    - -
    -
    - - - - -
    #define CAN_F13R2_FB0   CAN_F13R2_FB0_Msk
    -
    -

    Filter bit 0

    - -
    -
    - -

    ◆ CAN_F13R2_FB1_Pos

    - -
    -
    - - - - -
    #define CAN_F13R2_FB1_Pos   (1U)
    -
    - -
    -
    - -

    ◆ CAN_F13R2_FB1_Msk

    - -
    -
    - - - - -
    #define CAN_F13R2_FB1_Msk   (0x1UL << CAN_F13R2_FB1_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ CAN_F13R2_FB1

    - -
    -
    - - - - -
    #define CAN_F13R2_FB1   CAN_F13R2_FB1_Msk
    -
    -

    Filter bit 1

    - -
    -
    - -

    ◆ CAN_F13R2_FB2_Pos

    - -
    -
    - - - - -
    #define CAN_F13R2_FB2_Pos   (2U)
    -
    - -
    -
    - -

    ◆ CAN_F13R2_FB2_Msk

    - -
    -
    - - - - -
    #define CAN_F13R2_FB2_Msk   (0x1UL << CAN_F13R2_FB2_Pos)
    -
    -

    0x00000004

    - -
    -
    - -

    ◆ CAN_F13R2_FB2

    - -
    -
    - - - - -
    #define CAN_F13R2_FB2   CAN_F13R2_FB2_Msk
    -
    -

    Filter bit 2

    - -
    -
    - -

    ◆ CAN_F13R2_FB3_Pos

    - -
    -
    - - - - -
    #define CAN_F13R2_FB3_Pos   (3U)
    -
    - -
    -
    - -

    ◆ CAN_F13R2_FB3_Msk

    - -
    -
    - - - - -
    #define CAN_F13R2_FB3_Msk   (0x1UL << CAN_F13R2_FB3_Pos)
    -
    -

    0x00000008

    - -
    -
    - -

    ◆ CAN_F13R2_FB3

    - -
    -
    - - - - -
    #define CAN_F13R2_FB3   CAN_F13R2_FB3_Msk
    -
    -

    Filter bit 3

    - -
    -
    - -

    ◆ CAN_F13R2_FB4_Pos

    - -
    -
    - - - - -
    #define CAN_F13R2_FB4_Pos   (4U)
    -
    - -
    -
    - -

    ◆ CAN_F13R2_FB4_Msk

    - -
    -
    - - - - -
    #define CAN_F13R2_FB4_Msk   (0x1UL << CAN_F13R2_FB4_Pos)
    -
    -

    0x00000010

    - -
    -
    - -

    ◆ CAN_F13R2_FB4

    - -
    -
    - - - - -
    #define CAN_F13R2_FB4   CAN_F13R2_FB4_Msk
    -
    -

    Filter bit 4

    - -
    -
    - -

    ◆ CAN_F13R2_FB5_Pos

    - -
    -
    - - - - -
    #define CAN_F13R2_FB5_Pos   (5U)
    -
    - -
    -
    - -

    ◆ CAN_F13R2_FB5_Msk

    - -
    -
    - - - - -
    #define CAN_F13R2_FB5_Msk   (0x1UL << CAN_F13R2_FB5_Pos)
    -
    -

    0x00000020

    - -
    -
    - -

    ◆ CAN_F13R2_FB5

    - -
    -
    - - - - -
    #define CAN_F13R2_FB5   CAN_F13R2_FB5_Msk
    -
    -

    Filter bit 5

    - -
    -
    - -

    ◆ CAN_F13R2_FB6_Pos

    - -
    -
    - - - - -
    #define CAN_F13R2_FB6_Pos   (6U)
    -
    - -
    -
    - -

    ◆ CAN_F13R2_FB6_Msk

    - -
    -
    - - - - -
    #define CAN_F13R2_FB6_Msk   (0x1UL << CAN_F13R2_FB6_Pos)
    -
    -

    0x00000040

    - -
    -
    - -

    ◆ CAN_F13R2_FB6

    - -
    -
    - - - - -
    #define CAN_F13R2_FB6   CAN_F13R2_FB6_Msk
    -
    -

    Filter bit 6

    - -
    -
    - -

    ◆ CAN_F13R2_FB7_Pos

    - -
    -
    - - - - -
    #define CAN_F13R2_FB7_Pos   (7U)
    -
    - -
    -
    - -

    ◆ CAN_F13R2_FB7_Msk

    - -
    -
    - - - - -
    #define CAN_F13R2_FB7_Msk   (0x1UL << CAN_F13R2_FB7_Pos)
    -
    -

    0x00000080

    - -
    -
    - -

    ◆ CAN_F13R2_FB7

    - -
    -
    - - - - -
    #define CAN_F13R2_FB7   CAN_F13R2_FB7_Msk
    -
    -

    Filter bit 7

    - -
    -
    - -

    ◆ CAN_F13R2_FB8_Pos

    - -
    -
    - - - - -
    #define CAN_F13R2_FB8_Pos   (8U)
    -
    - -
    -
    - -

    ◆ CAN_F13R2_FB8_Msk

    - -
    -
    - - - - -
    #define CAN_F13R2_FB8_Msk   (0x1UL << CAN_F13R2_FB8_Pos)
    -
    -

    0x00000100

    - -
    -
    - -

    ◆ CAN_F13R2_FB8

    - -
    -
    - - - - -
    #define CAN_F13R2_FB8   CAN_F13R2_FB8_Msk
    -
    -

    Filter bit 8

    - -
    -
    - -

    ◆ CAN_F13R2_FB9_Pos

    - -
    -
    - - - - -
    #define CAN_F13R2_FB9_Pos   (9U)
    -
    - -
    -
    - -

    ◆ CAN_F13R2_FB9_Msk

    - -
    -
    - - - - -
    #define CAN_F13R2_FB9_Msk   (0x1UL << CAN_F13R2_FB9_Pos)
    -
    -

    0x00000200

    - -
    -
    - -

    ◆ CAN_F13R2_FB9

    - -
    -
    - - - - -
    #define CAN_F13R2_FB9   CAN_F13R2_FB9_Msk
    -
    -

    Filter bit 9

    - -
    -
    - -

    ◆ CAN_F13R2_FB10_Pos

    - -
    -
    - - - - -
    #define CAN_F13R2_FB10_Pos   (10U)
    -
    - -
    -
    - -

    ◆ CAN_F13R2_FB10_Msk

    - -
    -
    - - - - -
    #define CAN_F13R2_FB10_Msk   (0x1UL << CAN_F13R2_FB10_Pos)
    -
    -

    0x00000400

    - -
    -
    - -

    ◆ CAN_F13R2_FB10

    - -
    -
    - - - - -
    #define CAN_F13R2_FB10   CAN_F13R2_FB10_Msk
    -
    -

    Filter bit 10

    - -
    -
    - -

    ◆ CAN_F13R2_FB11_Pos

    - -
    -
    - - - - -
    #define CAN_F13R2_FB11_Pos   (11U)
    -
    - -
    -
    - -

    ◆ CAN_F13R2_FB11_Msk

    - -
    -
    - - - - -
    #define CAN_F13R2_FB11_Msk   (0x1UL << CAN_F13R2_FB11_Pos)
    -
    -

    0x00000800

    - -
    -
    - -

    ◆ CAN_F13R2_FB11

    - -
    -
    - - - - -
    #define CAN_F13R2_FB11   CAN_F13R2_FB11_Msk
    -
    -

    Filter bit 11

    - -
    -
    - -

    ◆ CAN_F13R2_FB12_Pos

    - -
    -
    - - - - -
    #define CAN_F13R2_FB12_Pos   (12U)
    -
    - -
    -
    - -

    ◆ CAN_F13R2_FB12_Msk

    - -
    -
    - - - - -
    #define CAN_F13R2_FB12_Msk   (0x1UL << CAN_F13R2_FB12_Pos)
    -
    -

    0x00001000

    - -
    -
    - -

    ◆ CAN_F13R2_FB12

    - -
    -
    - - - - -
    #define CAN_F13R2_FB12   CAN_F13R2_FB12_Msk
    -
    -

    Filter bit 12

    - -
    -
    - -

    ◆ CAN_F13R2_FB13_Pos

    - -
    -
    - - - - -
    #define CAN_F13R2_FB13_Pos   (13U)
    -
    - -
    -
    - -

    ◆ CAN_F13R2_FB13_Msk

    - -
    -
    - - - - -
    #define CAN_F13R2_FB13_Msk   (0x1UL << CAN_F13R2_FB13_Pos)
    -
    -

    0x00002000

    - -
    -
    - -

    ◆ CAN_F13R2_FB13

    - -
    -
    - - - - -
    #define CAN_F13R2_FB13   CAN_F13R2_FB13_Msk
    -
    -

    Filter bit 13

    - -
    -
    - -

    ◆ CAN_F13R2_FB14_Pos

    - -
    -
    - - - - -
    #define CAN_F13R2_FB14_Pos   (14U)
    -
    - -
    -
    - -

    ◆ CAN_F13R2_FB14_Msk

    - -
    -
    - - - - -
    #define CAN_F13R2_FB14_Msk   (0x1UL << CAN_F13R2_FB14_Pos)
    -
    -

    0x00004000

    - -
    -
    - -

    ◆ CAN_F13R2_FB14

    - -
    -
    - - - - -
    #define CAN_F13R2_FB14   CAN_F13R2_FB14_Msk
    -
    -

    Filter bit 14

    - -
    -
    - -

    ◆ CAN_F13R2_FB15_Pos

    - -
    -
    - - - - -
    #define CAN_F13R2_FB15_Pos   (15U)
    -
    - -
    -
    - -

    ◆ CAN_F13R2_FB15_Msk

    - -
    -
    - - - - -
    #define CAN_F13R2_FB15_Msk   (0x1UL << CAN_F13R2_FB15_Pos)
    -
    -

    0x00008000

    - -
    -
    - -

    ◆ CAN_F13R2_FB15

    - -
    -
    - - - - -
    #define CAN_F13R2_FB15   CAN_F13R2_FB15_Msk
    -
    -

    Filter bit 15

    - -
    -
    - -

    ◆ CAN_F13R2_FB16_Pos

    - -
    -
    - - - - -
    #define CAN_F13R2_FB16_Pos   (16U)
    -
    - -
    -
    - -

    ◆ CAN_F13R2_FB16_Msk

    - -
    -
    - - - - -
    #define CAN_F13R2_FB16_Msk   (0x1UL << CAN_F13R2_FB16_Pos)
    -
    -

    0x00010000

    - -
    -
    - -

    ◆ CAN_F13R2_FB16

    - -
    -
    - - - - -
    #define CAN_F13R2_FB16   CAN_F13R2_FB16_Msk
    -
    -

    Filter bit 16

    - -
    -
    - -

    ◆ CAN_F13R2_FB17_Pos

    - -
    -
    - - - - -
    #define CAN_F13R2_FB17_Pos   (17U)
    -
    - -
    -
    - -

    ◆ CAN_F13R2_FB17_Msk

    - -
    -
    - - - - -
    #define CAN_F13R2_FB17_Msk   (0x1UL << CAN_F13R2_FB17_Pos)
    -
    -

    0x00020000

    - -
    -
    - -

    ◆ CAN_F13R2_FB17

    - -
    -
    - - - - -
    #define CAN_F13R2_FB17   CAN_F13R2_FB17_Msk
    -
    -

    Filter bit 17

    - -
    -
    - -

    ◆ CAN_F13R2_FB18_Pos

    - -
    -
    - - - - -
    #define CAN_F13R2_FB18_Pos   (18U)
    -
    - -
    -
    - -

    ◆ CAN_F13R2_FB18_Msk

    - -
    -
    - - - - -
    #define CAN_F13R2_FB18_Msk   (0x1UL << CAN_F13R2_FB18_Pos)
    -
    -

    0x00040000

    - -
    -
    - -

    ◆ CAN_F13R2_FB18

    - -
    -
    - - - - -
    #define CAN_F13R2_FB18   CAN_F13R2_FB18_Msk
    -
    -

    Filter bit 18

    - -
    -
    - -

    ◆ CAN_F13R2_FB19_Pos

    - -
    -
    - - - - -
    #define CAN_F13R2_FB19_Pos   (19U)
    -
    - -
    -
    - -

    ◆ CAN_F13R2_FB19_Msk

    - -
    -
    - - - - -
    #define CAN_F13R2_FB19_Msk   (0x1UL << CAN_F13R2_FB19_Pos)
    -
    -

    0x00080000

    - -
    -
    - -

    ◆ CAN_F13R2_FB19

    - -
    -
    - - - - -
    #define CAN_F13R2_FB19   CAN_F13R2_FB19_Msk
    -
    -

    Filter bit 19

    - -
    -
    - -

    ◆ CAN_F13R2_FB20_Pos

    - -
    -
    - - - - -
    #define CAN_F13R2_FB20_Pos   (20U)
    -
    - -
    -
    - -

    ◆ CAN_F13R2_FB20_Msk

    - -
    -
    - - - - -
    #define CAN_F13R2_FB20_Msk   (0x1UL << CAN_F13R2_FB20_Pos)
    -
    -

    0x00100000

    - -
    -
    - -

    ◆ CAN_F13R2_FB20

    - -
    -
    - - - - -
    #define CAN_F13R2_FB20   CAN_F13R2_FB20_Msk
    -
    -

    Filter bit 20

    - -
    -
    - -

    ◆ CAN_F13R2_FB21_Pos

    - -
    -
    - - - - -
    #define CAN_F13R2_FB21_Pos   (21U)
    -
    - -
    -
    - -

    ◆ CAN_F13R2_FB21_Msk

    - -
    -
    - - - - -
    #define CAN_F13R2_FB21_Msk   (0x1UL << CAN_F13R2_FB21_Pos)
    -
    -

    0x00200000

    - -
    -
    - -

    ◆ CAN_F13R2_FB21

    - -
    -
    - - - - -
    #define CAN_F13R2_FB21   CAN_F13R2_FB21_Msk
    -
    -

    Filter bit 21

    - -
    -
    - -

    ◆ CAN_F13R2_FB22_Pos

    - -
    -
    - - - - -
    #define CAN_F13R2_FB22_Pos   (22U)
    -
    - -
    -
    - -

    ◆ CAN_F13R2_FB22_Msk

    - -
    -
    - - - - -
    #define CAN_F13R2_FB22_Msk   (0x1UL << CAN_F13R2_FB22_Pos)
    -
    -

    0x00400000

    - -
    -
    - -

    ◆ CAN_F13R2_FB22

    - -
    -
    - - - - -
    #define CAN_F13R2_FB22   CAN_F13R2_FB22_Msk
    -
    -

    Filter bit 22

    - -
    -
    - -

    ◆ CAN_F13R2_FB23_Pos

    - -
    -
    - - - - -
    #define CAN_F13R2_FB23_Pos   (23U)
    -
    - -
    -
    - -

    ◆ CAN_F13R2_FB23_Msk

    - -
    -
    - - - - -
    #define CAN_F13R2_FB23_Msk   (0x1UL << CAN_F13R2_FB23_Pos)
    -
    -

    0x00800000

    - -
    -
    - -

    ◆ CAN_F13R2_FB23

    - -
    -
    - - - - -
    #define CAN_F13R2_FB23   CAN_F13R2_FB23_Msk
    -
    -

    Filter bit 23

    - -
    -
    - -

    ◆ CAN_F13R2_FB24_Pos

    - -
    -
    - - - - -
    #define CAN_F13R2_FB24_Pos   (24U)
    -
    - -
    -
    - -

    ◆ CAN_F13R2_FB24_Msk

    - -
    -
    - - - - -
    #define CAN_F13R2_FB24_Msk   (0x1UL << CAN_F13R2_FB24_Pos)
    -
    -

    0x01000000

    - -
    -
    - -

    ◆ CAN_F13R2_FB24

    - -
    -
    - - - - -
    #define CAN_F13R2_FB24   CAN_F13R2_FB24_Msk
    -
    -

    Filter bit 24

    - -
    -
    - -

    ◆ CAN_F13R2_FB25_Pos

    - -
    -
    - - - - -
    #define CAN_F13R2_FB25_Pos   (25U)
    -
    - -
    -
    - -

    ◆ CAN_F13R2_FB25_Msk

    - -
    -
    - - - - -
    #define CAN_F13R2_FB25_Msk   (0x1UL << CAN_F13R2_FB25_Pos)
    -
    -

    0x02000000

    - -
    -
    - -

    ◆ CAN_F13R2_FB25

    - -
    -
    - - - - -
    #define CAN_F13R2_FB25   CAN_F13R2_FB25_Msk
    -
    -

    Filter bit 25

    - -
    -
    - -

    ◆ CAN_F13R2_FB26_Pos

    - -
    -
    - - - - -
    #define CAN_F13R2_FB26_Pos   (26U)
    -
    - -
    -
    - -

    ◆ CAN_F13R2_FB26_Msk

    - -
    -
    - - - - -
    #define CAN_F13R2_FB26_Msk   (0x1UL << CAN_F13R2_FB26_Pos)
    -
    -

    0x04000000

    - -
    -
    - -

    ◆ CAN_F13R2_FB26

    - -
    -
    - - - - -
    #define CAN_F13R2_FB26   CAN_F13R2_FB26_Msk
    -
    -

    Filter bit 26

    - -
    -
    - -

    ◆ CAN_F13R2_FB27_Pos

    - -
    -
    - - - - -
    #define CAN_F13R2_FB27_Pos   (27U)
    -
    - -
    -
    - -

    ◆ CAN_F13R2_FB27_Msk

    - -
    -
    - - - - -
    #define CAN_F13R2_FB27_Msk   (0x1UL << CAN_F13R2_FB27_Pos)
    -
    -

    0x08000000

    - -
    -
    - -

    ◆ CAN_F13R2_FB27

    - -
    -
    - - - - -
    #define CAN_F13R2_FB27   CAN_F13R2_FB27_Msk
    -
    -

    Filter bit 27

    - -
    -
    - -

    ◆ CAN_F13R2_FB28_Pos

    - -
    -
    - - - - -
    #define CAN_F13R2_FB28_Pos   (28U)
    -
    - -
    -
    - -

    ◆ CAN_F13R2_FB28_Msk

    - -
    -
    - - - - -
    #define CAN_F13R2_FB28_Msk   (0x1UL << CAN_F13R2_FB28_Pos)
    -
    -

    0x10000000

    - -
    -
    - -

    ◆ CAN_F13R2_FB28

    - -
    -
    - - - - -
    #define CAN_F13R2_FB28   CAN_F13R2_FB28_Msk
    -
    -

    Filter bit 28

    - -
    -
    - -

    ◆ CAN_F13R2_FB29_Pos

    - -
    -
    - - - - -
    #define CAN_F13R2_FB29_Pos   (29U)
    -
    - -
    -
    - -

    ◆ CAN_F13R2_FB29_Msk

    - -
    -
    - - - - -
    #define CAN_F13R2_FB29_Msk   (0x1UL << CAN_F13R2_FB29_Pos)
    -
    -

    0x20000000

    - -
    -
    - -

    ◆ CAN_F13R2_FB29

    - -
    -
    - - - - -
    #define CAN_F13R2_FB29   CAN_F13R2_FB29_Msk
    -
    -

    Filter bit 29

    - -
    -
    - -

    ◆ CAN_F13R2_FB30_Pos

    - -
    -
    - - - - -
    #define CAN_F13R2_FB30_Pos   (30U)
    -
    - -
    -
    - -

    ◆ CAN_F13R2_FB30_Msk

    - -
    -
    - - - - -
    #define CAN_F13R2_FB30_Msk   (0x1UL << CAN_F13R2_FB30_Pos)
    -
    -

    0x40000000

    - -
    -
    - -

    ◆ CAN_F13R2_FB30

    - -
    -
    - - - - -
    #define CAN_F13R2_FB30   CAN_F13R2_FB30_Msk
    -
    -

    Filter bit 30

    - -
    -
    - -

    ◆ CAN_F13R2_FB31_Pos

    - -
    -
    - - - - -
    #define CAN_F13R2_FB31_Pos   (31U)
    -
    - -
    -
    - -

    ◆ CAN_F13R2_FB31_Msk

    - -
    -
    - - - - -
    #define CAN_F13R2_FB31_Msk   (0x1UL << CAN_F13R2_FB31_Pos)
    -
    -

    0x80000000

    - -
    -
    - -

    ◆ CAN_F13R2_FB31

    - -
    -
    - - - - -
    #define CAN_F13R2_FB31   CAN_F13R2_FB31_Msk
    -
    -

    Filter bit 31

    - -
    -
    - -

    ◆ CRC_DR_DR_Pos

    - -
    -
    - - - - -
    #define CRC_DR_DR_Pos   (0U)
    -
    - -
    -
    - -

    ◆ CRC_DR_DR_Msk

    - -
    -
    - - - - -
    #define CRC_DR_DR_Msk   (0xFFFFFFFFUL << CRC_DR_DR_Pos)
    -
    -

    0xFFFFFFFF

    - -
    -
    - -

    ◆ CRC_DR_DR

    - -
    -
    - - - - -
    #define CRC_DR_DR   CRC_DR_DR_Msk
    -
    -

    Data register bits

    - -
    -
    - -

    ◆ CRC_IDR_IDR_Pos

    - -
    -
    - - - - -
    #define CRC_IDR_IDR_Pos   (0U)
    -
    - -
    -
    - -

    ◆ CRC_IDR_IDR_Msk

    - -
    -
    - - - - -
    #define CRC_IDR_IDR_Msk   (0xFFUL << CRC_IDR_IDR_Pos)
    -
    -

    0x000000FF

    - -
    -
    - -

    ◆ CRC_IDR_IDR

    - -
    -
    - - - - -
    #define CRC_IDR_IDR   CRC_IDR_IDR_Msk
    -
    -

    General-purpose 8-bit data register bits

    - -
    -
    - -

    ◆ CRC_CR_RESET_Pos

    - -
    -
    - - - - -
    #define CRC_CR_RESET_Pos   (0U)
    -
    - -
    -
    - -

    ◆ CRC_CR_RESET_Msk

    - -
    -
    - - - - -
    #define CRC_CR_RESET_Msk   (0x1UL << CRC_CR_RESET_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ CRC_CR_RESET

    - -
    -
    - - - - -
    #define CRC_CR_RESET   CRC_CR_RESET_Msk
    -
    -

    RESET bit

    - -
    -
    - -

    ◆ DAC_CHANNEL2_SUPPORT

    - -
    -
    - - - - -
    #define DAC_CHANNEL2_SUPPORT
    -
    -

    DAC feature available only on specific devices: availability of DAC channel 2

    - -
    -
    - -

    ◆ DAC_CR_EN1_Pos

    - -
    -
    - - - - -
    #define DAC_CR_EN1_Pos   (0U)
    -
    - -
    -
    - -

    ◆ DAC_CR_EN1_Msk

    - -
    -
    - - - - -
    #define DAC_CR_EN1_Msk   (0x1UL << DAC_CR_EN1_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ DAC_CR_EN1

    - -
    -
    - - - - -
    #define DAC_CR_EN1   DAC_CR_EN1_Msk
    -
    -

    DAC channel1 enable

    - -
    -
    - -

    ◆ DAC_CR_BOFF1_Pos

    - -
    -
    - - - - -
    #define DAC_CR_BOFF1_Pos   (1U)
    -
    - -
    -
    - -

    ◆ DAC_CR_BOFF1_Msk

    - -
    -
    - - - - -
    #define DAC_CR_BOFF1_Msk   (0x1UL << DAC_CR_BOFF1_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ DAC_CR_BOFF1

    - -
    -
    - - - - -
    #define DAC_CR_BOFF1   DAC_CR_BOFF1_Msk
    -
    -

    DAC channel1 output buffer disable

    - -
    -
    - -

    ◆ DAC_CR_TEN1_Pos

    - -
    -
    - - - - -
    #define DAC_CR_TEN1_Pos   (2U)
    -
    - -
    -
    - -

    ◆ DAC_CR_TEN1_Msk

    - -
    -
    - - - - -
    #define DAC_CR_TEN1_Msk   (0x1UL << DAC_CR_TEN1_Pos)
    -
    -

    0x00000004

    - -
    -
    - -

    ◆ DAC_CR_TEN1

    - -
    -
    - - - - -
    #define DAC_CR_TEN1   DAC_CR_TEN1_Msk
    -
    -

    DAC channel1 Trigger enable

    - -
    -
    - -

    ◆ DAC_CR_TSEL1_Pos

    - -
    -
    - - - - -
    #define DAC_CR_TSEL1_Pos   (3U)
    -
    - -
    -
    - -

    ◆ DAC_CR_TSEL1_Msk

    - -
    -
    - - - - -
    #define DAC_CR_TSEL1_Msk   (0x7UL << DAC_CR_TSEL1_Pos)
    -
    -

    0x00000038

    - -
    -
    - -

    ◆ DAC_CR_TSEL1

    - -
    -
    - - - - -
    #define DAC_CR_TSEL1   DAC_CR_TSEL1_Msk
    -
    -

    TSEL1[2:0] (DAC channel1 Trigger selection)

    - -
    -
    - -

    ◆ DAC_CR_TSEL1_0

    - -
    -
    - - - - -
    #define DAC_CR_TSEL1_0   (0x1UL << DAC_CR_TSEL1_Pos)
    -
    -

    0x00000008

    - -
    -
    - -

    ◆ DAC_CR_TSEL1_1

    - -
    -
    - - - - -
    #define DAC_CR_TSEL1_1   (0x2UL << DAC_CR_TSEL1_Pos)
    -
    -

    0x00000010

    - -
    -
    - -

    ◆ DAC_CR_TSEL1_2

    - -
    -
    - - - - -
    #define DAC_CR_TSEL1_2   (0x4UL << DAC_CR_TSEL1_Pos)
    -
    -

    0x00000020

    - -
    -
    - -

    ◆ DAC_CR_WAVE1_Pos

    - -
    -
    - - - - -
    #define DAC_CR_WAVE1_Pos   (6U)
    -
    - -
    -
    - -

    ◆ DAC_CR_WAVE1_Msk

    - -
    -
    - - - - -
    #define DAC_CR_WAVE1_Msk   (0x3UL << DAC_CR_WAVE1_Pos)
    -
    -

    0x000000C0

    - -
    -
    - -

    ◆ DAC_CR_WAVE1

    - -
    -
    - - - - -
    #define DAC_CR_WAVE1   DAC_CR_WAVE1_Msk
    -
    -

    WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable)

    - -
    -
    - -

    ◆ DAC_CR_WAVE1_0

    - -
    -
    - - - - -
    #define DAC_CR_WAVE1_0   (0x1UL << DAC_CR_WAVE1_Pos)
    -
    -

    0x00000040

    - -
    -
    - -

    ◆ DAC_CR_WAVE1_1

    - -
    -
    - - - - -
    #define DAC_CR_WAVE1_1   (0x2UL << DAC_CR_WAVE1_Pos)
    -
    -

    0x00000080

    - -
    -
    - -

    ◆ DAC_CR_MAMP1_Pos

    - -
    -
    - - - - -
    #define DAC_CR_MAMP1_Pos   (8U)
    -
    - -
    -
    - -

    ◆ DAC_CR_MAMP1_Msk

    - -
    -
    - - - - -
    #define DAC_CR_MAMP1_Msk   (0xFUL << DAC_CR_MAMP1_Pos)
    -
    -

    0x00000F00

    - -
    -
    - -

    ◆ DAC_CR_MAMP1

    - -
    -
    - - - - -
    #define DAC_CR_MAMP1   DAC_CR_MAMP1_Msk
    -
    -

    MAMP1[3:0] (DAC channel1 Mask/Amplitude selector)

    - -
    -
    - -

    ◆ DAC_CR_MAMP1_0

    - -
    -
    - - - - -
    #define DAC_CR_MAMP1_0   (0x1UL << DAC_CR_MAMP1_Pos)
    -
    -

    0x00000100

    - -
    -
    - -

    ◆ DAC_CR_MAMP1_1

    - -
    -
    - - - - -
    #define DAC_CR_MAMP1_1   (0x2UL << DAC_CR_MAMP1_Pos)
    -
    -

    0x00000200

    - -
    -
    - -

    ◆ DAC_CR_MAMP1_2

    - -
    -
    - - - - -
    #define DAC_CR_MAMP1_2   (0x4UL << DAC_CR_MAMP1_Pos)
    -
    -

    0x00000400

    - -
    -
    - -

    ◆ DAC_CR_MAMP1_3

    - -
    -
    - - - - -
    #define DAC_CR_MAMP1_3   (0x8UL << DAC_CR_MAMP1_Pos)
    -
    -

    0x00000800

    - -
    -
    - -

    ◆ DAC_CR_DMAEN1_Pos

    - -
    -
    - - - - -
    #define DAC_CR_DMAEN1_Pos   (12U)
    -
    - -
    -
    - -

    ◆ DAC_CR_DMAEN1_Msk

    - -
    -
    - - - - -
    #define DAC_CR_DMAEN1_Msk   (0x1UL << DAC_CR_DMAEN1_Pos)
    -
    -

    0x00001000

    - -
    -
    - -

    ◆ DAC_CR_DMAEN1

    - -
    -
    - - - - -
    #define DAC_CR_DMAEN1   DAC_CR_DMAEN1_Msk
    -
    -

    DAC channel1 DMA enable

    - -
    -
    - -

    ◆ DAC_CR_DMAUDRIE1_Pos

    - -
    -
    - - - - -
    #define DAC_CR_DMAUDRIE1_Pos   (13U)
    -
    - -
    -
    - -

    ◆ DAC_CR_DMAUDRIE1_Msk

    - -
    -
    - - - - -
    #define DAC_CR_DMAUDRIE1_Msk   (0x1UL << DAC_CR_DMAUDRIE1_Pos)
    -
    -

    0x00002000

    - -
    -
    - -

    ◆ DAC_CR_DMAUDRIE1

    - -
    -
    - - - - -
    #define DAC_CR_DMAUDRIE1   DAC_CR_DMAUDRIE1_Msk
    -
    -

    DAC channel1 DMA underrun interrupt enable

    - -
    -
    - -

    ◆ DAC_CR_EN2_Pos

    - -
    -
    - - - - -
    #define DAC_CR_EN2_Pos   (16U)
    -
    - -
    -
    - -

    ◆ DAC_CR_EN2_Msk

    - -
    -
    - - - - -
    #define DAC_CR_EN2_Msk   (0x1UL << DAC_CR_EN2_Pos)
    -
    -

    0x00010000

    - -
    -
    - -

    ◆ DAC_CR_EN2

    - -
    -
    - - - - -
    #define DAC_CR_EN2   DAC_CR_EN2_Msk
    -
    -

    DAC channel2 enable

    - -
    -
    - -

    ◆ DAC_CR_BOFF2_Pos

    - -
    -
    - - - - -
    #define DAC_CR_BOFF2_Pos   (17U)
    -
    - -
    -
    - -

    ◆ DAC_CR_BOFF2_Msk

    - -
    -
    - - - - -
    #define DAC_CR_BOFF2_Msk   (0x1UL << DAC_CR_BOFF2_Pos)
    -
    -

    0x00020000

    - -
    -
    - -

    ◆ DAC_CR_BOFF2

    - -
    -
    - - - - -
    #define DAC_CR_BOFF2   DAC_CR_BOFF2_Msk
    -
    -

    DAC channel2 output buffer disable

    - -
    -
    - -

    ◆ DAC_CR_TEN2_Pos

    - -
    -
    - - - - -
    #define DAC_CR_TEN2_Pos   (18U)
    -
    - -
    -
    - -

    ◆ DAC_CR_TEN2_Msk

    - -
    -
    - - - - -
    #define DAC_CR_TEN2_Msk   (0x1UL << DAC_CR_TEN2_Pos)
    -
    -

    0x00040000

    - -
    -
    - -

    ◆ DAC_CR_TEN2

    - -
    -
    - - - - -
    #define DAC_CR_TEN2   DAC_CR_TEN2_Msk
    -
    -

    DAC channel2 Trigger enable

    - -
    -
    - -

    ◆ DAC_CR_TSEL2_Pos

    - -
    -
    - - - - -
    #define DAC_CR_TSEL2_Pos   (19U)
    -
    - -
    -
    - -

    ◆ DAC_CR_TSEL2_Msk

    - -
    -
    - - - - -
    #define DAC_CR_TSEL2_Msk   (0x7UL << DAC_CR_TSEL2_Pos)
    -
    -

    0x00380000

    - -
    -
    - -

    ◆ DAC_CR_TSEL2

    - -
    -
    - - - - -
    #define DAC_CR_TSEL2   DAC_CR_TSEL2_Msk
    -
    -

    TSEL2[2:0] (DAC channel2 Trigger selection)

    - -
    -
    - -

    ◆ DAC_CR_TSEL2_0

    - -
    -
    - - - - -
    #define DAC_CR_TSEL2_0   (0x1UL << DAC_CR_TSEL2_Pos)
    -
    -

    0x00080000

    - -
    -
    - -

    ◆ DAC_CR_TSEL2_1

    - -
    -
    - - - - -
    #define DAC_CR_TSEL2_1   (0x2UL << DAC_CR_TSEL2_Pos)
    -
    -

    0x00100000

    - -
    -
    - -

    ◆ DAC_CR_TSEL2_2

    - -
    -
    - - - - -
    #define DAC_CR_TSEL2_2   (0x4UL << DAC_CR_TSEL2_Pos)
    -
    -

    0x00200000

    - -
    -
    - -

    ◆ DAC_CR_WAVE2_Pos

    - -
    -
    - - - - -
    #define DAC_CR_WAVE2_Pos   (22U)
    -
    - -
    -
    - -

    ◆ DAC_CR_WAVE2_Msk

    - -
    -
    - - - - -
    #define DAC_CR_WAVE2_Msk   (0x3UL << DAC_CR_WAVE2_Pos)
    -
    -

    0x00C00000

    - -
    -
    - -

    ◆ DAC_CR_WAVE2

    - -
    -
    - - - - -
    #define DAC_CR_WAVE2   DAC_CR_WAVE2_Msk
    -
    -

    WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable)

    - -
    -
    - -

    ◆ DAC_CR_WAVE2_0

    - -
    -
    - - - - -
    #define DAC_CR_WAVE2_0   (0x1UL << DAC_CR_WAVE2_Pos)
    -
    -

    0x00400000

    - -
    -
    - -

    ◆ DAC_CR_WAVE2_1

    - -
    -
    - - - - -
    #define DAC_CR_WAVE2_1   (0x2UL << DAC_CR_WAVE2_Pos)
    -
    -

    0x00800000

    - -
    -
    - -

    ◆ DAC_CR_MAMP2_Pos

    - -
    -
    - - - - -
    #define DAC_CR_MAMP2_Pos   (24U)
    -
    - -
    -
    - -

    ◆ DAC_CR_MAMP2_Msk

    - -
    -
    - - - - -
    #define DAC_CR_MAMP2_Msk   (0xFUL << DAC_CR_MAMP2_Pos)
    -
    -

    0x0F000000

    - -
    -
    - -

    ◆ DAC_CR_MAMP2

    - -
    -
    - - - - -
    #define DAC_CR_MAMP2   DAC_CR_MAMP2_Msk
    -
    -

    MAMP2[3:0] (DAC channel2 Mask/Amplitude selector)

    - -
    -
    - -

    ◆ DAC_CR_MAMP2_0

    - -
    -
    - - - - -
    #define DAC_CR_MAMP2_0   (0x1UL << DAC_CR_MAMP2_Pos)
    -
    -

    0x01000000

    - -
    -
    - -

    ◆ DAC_CR_MAMP2_1

    - -
    -
    - - - - -
    #define DAC_CR_MAMP2_1   (0x2UL << DAC_CR_MAMP2_Pos)
    -
    -

    0x02000000

    - -
    -
    - -

    ◆ DAC_CR_MAMP2_2

    - -
    -
    - - - - -
    #define DAC_CR_MAMP2_2   (0x4UL << DAC_CR_MAMP2_Pos)
    -
    -

    0x04000000

    - -
    -
    - -

    ◆ DAC_CR_MAMP2_3

    - -
    -
    - - - - -
    #define DAC_CR_MAMP2_3   (0x8UL << DAC_CR_MAMP2_Pos)
    -
    -

    0x08000000

    - -
    -
    - -

    ◆ DAC_CR_DMAEN2_Pos

    - -
    -
    - - - - -
    #define DAC_CR_DMAEN2_Pos   (28U)
    -
    - -
    -
    - -

    ◆ DAC_CR_DMAEN2_Msk

    - -
    -
    - - - - -
    #define DAC_CR_DMAEN2_Msk   (0x1UL << DAC_CR_DMAEN2_Pos)
    -
    -

    0x10000000

    - -
    -
    - -

    ◆ DAC_CR_DMAEN2

    - -
    -
    - - - - -
    #define DAC_CR_DMAEN2   DAC_CR_DMAEN2_Msk
    -
    -

    DAC channel2 DMA enabled

    - -
    -
    - -

    ◆ DAC_CR_DMAUDRIE2_Pos

    - -
    -
    - - - - -
    #define DAC_CR_DMAUDRIE2_Pos   (29U)
    -
    - -
    -
    - -

    ◆ DAC_CR_DMAUDRIE2_Msk

    - -
    -
    - - - - -
    #define DAC_CR_DMAUDRIE2_Msk   (0x1UL << DAC_CR_DMAUDRIE2_Pos)
    -
    -

    0x20000000

    - -
    -
    - -

    ◆ DAC_CR_DMAUDRIE2

    - -
    -
    - - - - -
    #define DAC_CR_DMAUDRIE2   DAC_CR_DMAUDRIE2_Msk
    -
    -

    DAC channel2 DMA underrun interrupt enable

    - -
    -
    - -

    ◆ DAC_SWTRIGR_SWTRIG1_Pos

    - -
    -
    - - - - -
    #define DAC_SWTRIGR_SWTRIG1_Pos   (0U)
    -
    - -
    -
    - -

    ◆ DAC_SWTRIGR_SWTRIG1_Msk

    - -
    -
    - - - - -
    #define DAC_SWTRIGR_SWTRIG1_Msk   (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ DAC_SWTRIGR_SWTRIG1

    - -
    -
    - - - - -
    #define DAC_SWTRIGR_SWTRIG1   DAC_SWTRIGR_SWTRIG1_Msk
    -
    -

    DAC channel1 software trigger

    - -
    -
    - -

    ◆ DAC_SWTRIGR_SWTRIG2_Pos

    - -
    -
    - - - - -
    #define DAC_SWTRIGR_SWTRIG2_Pos   (1U)
    -
    - -
    -
    - -

    ◆ DAC_SWTRIGR_SWTRIG2_Msk

    - -
    -
    - - - - -
    #define DAC_SWTRIGR_SWTRIG2_Msk   (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ DAC_SWTRIGR_SWTRIG2

    - -
    -
    - - - - -
    #define DAC_SWTRIGR_SWTRIG2   DAC_SWTRIGR_SWTRIG2_Msk
    -
    -

    DAC channel2 software trigger

    - -
    -
    - -

    ◆ DAC_DHR12R1_DACC1DHR_Pos

    - -
    -
    - - - - -
    #define DAC_DHR12R1_DACC1DHR_Pos   (0U)
    -
    - -
    -
    - -

    ◆ DAC_DHR12R1_DACC1DHR_Msk

    - -
    -
    - - - - -
    #define DAC_DHR12R1_DACC1DHR_Msk   (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos)
    -
    -

    0x00000FFF

    - -
    -
    - -

    ◆ DAC_DHR12R1_DACC1DHR

    - -
    -
    - - - - -
    #define DAC_DHR12R1_DACC1DHR   DAC_DHR12R1_DACC1DHR_Msk
    -
    -

    DAC channel1 12-bit Right aligned data

    - -
    -
    - -

    ◆ DAC_DHR12L1_DACC1DHR_Pos

    - -
    -
    - - - - -
    #define DAC_DHR12L1_DACC1DHR_Pos   (4U)
    -
    - -
    -
    - -

    ◆ DAC_DHR12L1_DACC1DHR_Msk

    - -
    -
    - - - - -
    #define DAC_DHR12L1_DACC1DHR_Msk   (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos)
    -
    -

    0x0000FFF0

    - -
    -
    - -

    ◆ DAC_DHR12L1_DACC1DHR

    - -
    -
    - - - - -
    #define DAC_DHR12L1_DACC1DHR   DAC_DHR12L1_DACC1DHR_Msk
    -
    -

    DAC channel1 12-bit Left aligned data

    - -
    -
    - -

    ◆ DAC_DHR8R1_DACC1DHR_Pos

    - -
    -
    - - - - -
    #define DAC_DHR8R1_DACC1DHR_Pos   (0U)
    -
    - -
    -
    - -

    ◆ DAC_DHR8R1_DACC1DHR_Msk

    - -
    -
    - - - - -
    #define DAC_DHR8R1_DACC1DHR_Msk   (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos)
    -
    -

    0x000000FF

    - -
    -
    - -

    ◆ DAC_DHR8R1_DACC1DHR

    - -
    -
    - - - - -
    #define DAC_DHR8R1_DACC1DHR   DAC_DHR8R1_DACC1DHR_Msk
    -
    -

    DAC channel1 8-bit Right aligned data

    - -
    -
    - -

    ◆ DAC_DHR12R2_DACC2DHR_Pos

    - -
    -
    - - - - -
    #define DAC_DHR12R2_DACC2DHR_Pos   (0U)
    -
    - -
    -
    - -

    ◆ DAC_DHR12R2_DACC2DHR_Msk

    - -
    -
    - - - - -
    #define DAC_DHR12R2_DACC2DHR_Msk   (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos)
    -
    -

    0x00000FFF

    - -
    -
    - -

    ◆ DAC_DHR12R2_DACC2DHR

    - -
    -
    - - - - -
    #define DAC_DHR12R2_DACC2DHR   DAC_DHR12R2_DACC2DHR_Msk
    -
    -

    DAC channel2 12-bit Right aligned data

    - -
    -
    - -

    ◆ DAC_DHR12L2_DACC2DHR_Pos

    - -
    -
    - - - - -
    #define DAC_DHR12L2_DACC2DHR_Pos   (4U)
    -
    - -
    -
    - -

    ◆ DAC_DHR12L2_DACC2DHR_Msk

    - -
    -
    - - - - -
    #define DAC_DHR12L2_DACC2DHR_Msk   (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos)
    -
    -

    0x0000FFF0

    - -
    -
    - -

    ◆ DAC_DHR12L2_DACC2DHR

    - -
    -
    - - - - -
    #define DAC_DHR12L2_DACC2DHR   DAC_DHR12L2_DACC2DHR_Msk
    -
    -

    DAC channel2 12-bit Left aligned data

    - -
    -
    - -

    ◆ DAC_DHR8R2_DACC2DHR_Pos

    - -
    -
    - - - - -
    #define DAC_DHR8R2_DACC2DHR_Pos   (0U)
    -
    - -
    -
    - -

    ◆ DAC_DHR8R2_DACC2DHR_Msk

    - -
    -
    - - - - -
    #define DAC_DHR8R2_DACC2DHR_Msk   (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos)
    -
    -

    0x000000FF

    - -
    -
    - -

    ◆ DAC_DHR8R2_DACC2DHR

    - -
    -
    - - - - -
    #define DAC_DHR8R2_DACC2DHR   DAC_DHR8R2_DACC2DHR_Msk
    -
    -

    DAC channel2 8-bit Right aligned data

    - -
    -
    - -

    ◆ DAC_DHR12RD_DACC1DHR_Pos

    - -
    -
    - - - - -
    #define DAC_DHR12RD_DACC1DHR_Pos   (0U)
    -
    - -
    -
    - -

    ◆ DAC_DHR12RD_DACC1DHR_Msk

    - -
    -
    - - - - -
    #define DAC_DHR12RD_DACC1DHR_Msk   (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos)
    -
    -

    0x00000FFF

    - -
    -
    - -

    ◆ DAC_DHR12RD_DACC1DHR

    - -
    -
    - - - - -
    #define DAC_DHR12RD_DACC1DHR   DAC_DHR12RD_DACC1DHR_Msk
    -
    -

    DAC channel1 12-bit Right aligned data

    - -
    -
    - -

    ◆ DAC_DHR12RD_DACC2DHR_Pos

    - -
    -
    - - - - -
    #define DAC_DHR12RD_DACC2DHR_Pos   (16U)
    -
    - -
    -
    - -

    ◆ DAC_DHR12RD_DACC2DHR_Msk

    - -
    -
    - - - - -
    #define DAC_DHR12RD_DACC2DHR_Msk   (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos)
    -
    -

    0x0FFF0000

    - -
    -
    - -

    ◆ DAC_DHR12RD_DACC2DHR

    - -
    -
    - - - - -
    #define DAC_DHR12RD_DACC2DHR   DAC_DHR12RD_DACC2DHR_Msk
    -
    -

    DAC channel2 12-bit Right aligned data

    - -
    -
    - -

    ◆ DAC_DHR12LD_DACC1DHR_Pos

    - -
    -
    - - - - -
    #define DAC_DHR12LD_DACC1DHR_Pos   (4U)
    -
    - -
    -
    - -

    ◆ DAC_DHR12LD_DACC1DHR_Msk

    - -
    -
    - - - - -
    #define DAC_DHR12LD_DACC1DHR_Msk   (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos)
    -
    -

    0x0000FFF0

    - -
    -
    - -

    ◆ DAC_DHR12LD_DACC1DHR

    - -
    -
    - - - - -
    #define DAC_DHR12LD_DACC1DHR   DAC_DHR12LD_DACC1DHR_Msk
    -
    -

    DAC channel1 12-bit Left aligned data

    - -
    -
    - -

    ◆ DAC_DHR12LD_DACC2DHR_Pos

    - -
    -
    - - - - -
    #define DAC_DHR12LD_DACC2DHR_Pos   (20U)
    -
    - -
    -
    - -

    ◆ DAC_DHR12LD_DACC2DHR_Msk

    - -
    -
    - - - - -
    #define DAC_DHR12LD_DACC2DHR_Msk   (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos)
    -
    -

    0xFFF00000

    - -
    -
    - -

    ◆ DAC_DHR12LD_DACC2DHR

    - -
    -
    - - - - -
    #define DAC_DHR12LD_DACC2DHR   DAC_DHR12LD_DACC2DHR_Msk
    -
    -

    DAC channel2 12-bit Left aligned data

    - -
    -
    - -

    ◆ DAC_DHR8RD_DACC1DHR_Pos

    - -
    -
    - - - - -
    #define DAC_DHR8RD_DACC1DHR_Pos   (0U)
    -
    - -
    -
    - -

    ◆ DAC_DHR8RD_DACC1DHR_Msk

    - -
    -
    - - - - -
    #define DAC_DHR8RD_DACC1DHR_Msk   (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos)
    -
    -

    0x000000FF

    - -
    -
    - -

    ◆ DAC_DHR8RD_DACC1DHR

    - -
    -
    - - - - -
    #define DAC_DHR8RD_DACC1DHR   DAC_DHR8RD_DACC1DHR_Msk
    -
    -

    DAC channel1 8-bit Right aligned data

    - -
    -
    - -

    ◆ DAC_DHR8RD_DACC2DHR_Pos

    - -
    -
    - - - - -
    #define DAC_DHR8RD_DACC2DHR_Pos   (8U)
    -
    - -
    -
    - -

    ◆ DAC_DHR8RD_DACC2DHR_Msk

    - -
    -
    - - - - -
    #define DAC_DHR8RD_DACC2DHR_Msk   (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos)
    -
    -

    0x0000FF00

    - -
    -
    - -

    ◆ DAC_DHR8RD_DACC2DHR

    - -
    -
    - - - - -
    #define DAC_DHR8RD_DACC2DHR   DAC_DHR8RD_DACC2DHR_Msk
    -
    -

    DAC channel2 8-bit Right aligned data

    - -
    -
    - -

    ◆ DAC_DOR1_DACC1DOR_Pos

    - -
    -
    - - - - -
    #define DAC_DOR1_DACC1DOR_Pos   (0U)
    -
    - -
    -
    - -

    ◆ DAC_DOR1_DACC1DOR_Msk

    - -
    -
    - - - - -
    #define DAC_DOR1_DACC1DOR_Msk   (0xFFFUL << DAC_DOR1_DACC1DOR_Pos)
    -
    -

    0x00000FFF

    - -
    -
    - -

    ◆ DAC_DOR1_DACC1DOR

    - -
    -
    - - - - -
    #define DAC_DOR1_DACC1DOR   DAC_DOR1_DACC1DOR_Msk
    -
    -

    DAC channel1 data output

    - -
    -
    - -

    ◆ DAC_DOR2_DACC2DOR_Pos

    - -
    -
    - - - - -
    #define DAC_DOR2_DACC2DOR_Pos   (0U)
    -
    - -
    -
    - -

    ◆ DAC_DOR2_DACC2DOR_Msk

    - -
    -
    - - - - -
    #define DAC_DOR2_DACC2DOR_Msk   (0xFFFUL << DAC_DOR2_DACC2DOR_Pos)
    -
    -

    0x00000FFF

    - -
    -
    - -

    ◆ DAC_DOR2_DACC2DOR

    - -
    -
    - - - - -
    #define DAC_DOR2_DACC2DOR   DAC_DOR2_DACC2DOR_Msk
    -
    -

    DAC channel2 data output

    - -
    -
    - -

    ◆ DAC_SR_DMAUDR1_Pos

    - -
    -
    - - - - -
    #define DAC_SR_DMAUDR1_Pos   (13U)
    -
    - -
    -
    - -

    ◆ DAC_SR_DMAUDR1_Msk

    - -
    -
    - - - - -
    #define DAC_SR_DMAUDR1_Msk   (0x1UL << DAC_SR_DMAUDR1_Pos)
    -
    -

    0x00002000

    - -
    -
    - -

    ◆ DAC_SR_DMAUDR1

    - -
    -
    - - - - -
    #define DAC_SR_DMAUDR1   DAC_SR_DMAUDR1_Msk
    -
    -

    DAC channel1 DMA underrun flag

    - -
    -
    - -

    ◆ DAC_SR_DMAUDR2_Pos

    - -
    -
    - - - - -
    #define DAC_SR_DMAUDR2_Pos   (29U)
    -
    - -
    -
    - -

    ◆ DAC_SR_DMAUDR2_Msk

    - -
    -
    - - - - -
    #define DAC_SR_DMAUDR2_Msk   (0x1UL << DAC_SR_DMAUDR2_Pos)
    -
    -

    0x20000000

    - -
    -
    - -

    ◆ DAC_SR_DMAUDR2

    - -
    -
    - - - - -
    #define DAC_SR_DMAUDR2   DAC_SR_DMAUDR2_Msk
    -
    -

    DAC channel2 DMA underrun flag

    - -
    -
    - -

    ◆ DCMI_CR_CAPTURE_Pos

    - -
    -
    - - - - -
    #define DCMI_CR_CAPTURE_Pos   (0U)
    -
    - -
    -
    - -

    ◆ DCMI_CR_CAPTURE_Msk

    - -
    -
    - - - - -
    #define DCMI_CR_CAPTURE_Msk   (0x1UL << DCMI_CR_CAPTURE_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ DCMI_CR_CAPTURE

    - -
    -
    - - - - -
    #define DCMI_CR_CAPTURE   DCMI_CR_CAPTURE_Msk
    -
    - -
    -
    - -

    ◆ DCMI_CR_CM_Pos

    - -
    -
    - - - - -
    #define DCMI_CR_CM_Pos   (1U)
    -
    - -
    -
    - -

    ◆ DCMI_CR_CM_Msk

    - -
    -
    - - - - -
    #define DCMI_CR_CM_Msk   (0x1UL << DCMI_CR_CM_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ DCMI_CR_CM

    - -
    -
    - - - - -
    #define DCMI_CR_CM   DCMI_CR_CM_Msk
    -
    - -
    -
    - -

    ◆ DCMI_CR_CROP_Pos

    - -
    -
    - - - - -
    #define DCMI_CR_CROP_Pos   (2U)
    -
    - -
    -
    - -

    ◆ DCMI_CR_CROP_Msk

    - -
    -
    - - - - -
    #define DCMI_CR_CROP_Msk   (0x1UL << DCMI_CR_CROP_Pos)
    -
    -

    0x00000004

    - -
    -
    - -

    ◆ DCMI_CR_CROP

    - -
    -
    - - - - -
    #define DCMI_CR_CROP   DCMI_CR_CROP_Msk
    -
    - -
    -
    - -

    ◆ DCMI_CR_JPEG_Pos

    - -
    -
    - - - - -
    #define DCMI_CR_JPEG_Pos   (3U)
    -
    - -
    -
    - -

    ◆ DCMI_CR_JPEG_Msk

    - -
    -
    - - - - -
    #define DCMI_CR_JPEG_Msk   (0x1UL << DCMI_CR_JPEG_Pos)
    -
    -

    0x00000008

    - -
    -
    - -

    ◆ DCMI_CR_JPEG

    - -
    -
    - - - - -
    #define DCMI_CR_JPEG   DCMI_CR_JPEG_Msk
    -
    - -
    -
    - -

    ◆ DCMI_CR_ESS_Pos

    - -
    -
    - - - - -
    #define DCMI_CR_ESS_Pos   (4U)
    -
    - -
    -
    - -

    ◆ DCMI_CR_ESS_Msk

    - -
    -
    - - - - -
    #define DCMI_CR_ESS_Msk   (0x1UL << DCMI_CR_ESS_Pos)
    -
    -

    0x00000010

    - -
    -
    - -

    ◆ DCMI_CR_ESS

    - -
    -
    - - - - -
    #define DCMI_CR_ESS   DCMI_CR_ESS_Msk
    -
    - -
    -
    - -

    ◆ DCMI_CR_PCKPOL_Pos

    - -
    -
    - - - - -
    #define DCMI_CR_PCKPOL_Pos   (5U)
    -
    - -
    -
    - -

    ◆ DCMI_CR_PCKPOL_Msk

    - -
    -
    - - - - -
    #define DCMI_CR_PCKPOL_Msk   (0x1UL << DCMI_CR_PCKPOL_Pos)
    -
    -

    0x00000020

    - -
    -
    - -

    ◆ DCMI_CR_PCKPOL

    - -
    -
    - - - - -
    #define DCMI_CR_PCKPOL   DCMI_CR_PCKPOL_Msk
    -
    - -
    -
    - -

    ◆ DCMI_CR_HSPOL_Pos

    - -
    -
    - - - - -
    #define DCMI_CR_HSPOL_Pos   (6U)
    -
    - -
    -
    - -

    ◆ DCMI_CR_HSPOL_Msk

    - -
    -
    - - - - -
    #define DCMI_CR_HSPOL_Msk   (0x1UL << DCMI_CR_HSPOL_Pos)
    -
    -

    0x00000040

    - -
    -
    - -

    ◆ DCMI_CR_HSPOL

    - -
    -
    - - - - -
    #define DCMI_CR_HSPOL   DCMI_CR_HSPOL_Msk
    -
    - -
    -
    - -

    ◆ DCMI_CR_VSPOL_Pos

    - -
    -
    - - - - -
    #define DCMI_CR_VSPOL_Pos   (7U)
    -
    - -
    -
    - -

    ◆ DCMI_CR_VSPOL_Msk

    - -
    -
    - - - - -
    #define DCMI_CR_VSPOL_Msk   (0x1UL << DCMI_CR_VSPOL_Pos)
    -
    -

    0x00000080

    - -
    -
    - -

    ◆ DCMI_CR_VSPOL

    - -
    -
    - - - - -
    #define DCMI_CR_VSPOL   DCMI_CR_VSPOL_Msk
    -
    - -
    -
    - -

    ◆ DCMI_CR_FCRC_0

    - -
    -
    - - - - -
    #define DCMI_CR_FCRC_0   0x00000100U
    -
    - -
    -
    - -

    ◆ DCMI_CR_FCRC_1

    - -
    -
    - - - - -
    #define DCMI_CR_FCRC_1   0x00000200U
    -
    - -
    -
    - -

    ◆ DCMI_CR_EDM_0

    - -
    -
    - - - - -
    #define DCMI_CR_EDM_0   0x00000400U
    -
    - -
    -
    - -

    ◆ DCMI_CR_EDM_1

    - -
    -
    - - - - -
    #define DCMI_CR_EDM_1   0x00000800U
    -
    - -
    -
    - -

    ◆ DCMI_CR_CRE_Pos

    - -
    -
    - - - - -
    #define DCMI_CR_CRE_Pos   (12U)
    -
    - -
    -
    - -

    ◆ DCMI_CR_CRE_Msk

    - -
    -
    - - - - -
    #define DCMI_CR_CRE_Msk   (0x1UL << DCMI_CR_CRE_Pos)
    -
    -

    0x00001000

    - -
    -
    - -

    ◆ DCMI_CR_CRE

    - -
    -
    - - - - -
    #define DCMI_CR_CRE   DCMI_CR_CRE_Msk
    -
    - -
    -
    - -

    ◆ DCMI_CR_ENABLE_Pos

    - -
    -
    - - - - -
    #define DCMI_CR_ENABLE_Pos   (14U)
    -
    - -
    -
    - -

    ◆ DCMI_CR_ENABLE_Msk

    - -
    -
    - - - - -
    #define DCMI_CR_ENABLE_Msk   (0x1UL << DCMI_CR_ENABLE_Pos)
    -
    -

    0x00004000

    - -
    -
    - -

    ◆ DCMI_CR_ENABLE

    - -
    -
    - - - - -
    #define DCMI_CR_ENABLE   DCMI_CR_ENABLE_Msk
    -
    - -
    -
    - -

    ◆ DCMI_SR_HSYNC_Pos

    - -
    -
    - - - - -
    #define DCMI_SR_HSYNC_Pos   (0U)
    -
    - -
    -
    - -

    ◆ DCMI_SR_HSYNC_Msk

    - -
    -
    - - - - -
    #define DCMI_SR_HSYNC_Msk   (0x1UL << DCMI_SR_HSYNC_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ DCMI_SR_HSYNC

    - -
    -
    - - - - -
    #define DCMI_SR_HSYNC   DCMI_SR_HSYNC_Msk
    -
    - -
    -
    - -

    ◆ DCMI_SR_VSYNC_Pos

    - -
    -
    - - - - -
    #define DCMI_SR_VSYNC_Pos   (1U)
    -
    - -
    -
    - -

    ◆ DCMI_SR_VSYNC_Msk

    - -
    -
    - - - - -
    #define DCMI_SR_VSYNC_Msk   (0x1UL << DCMI_SR_VSYNC_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ DCMI_SR_VSYNC

    - -
    -
    - - - - -
    #define DCMI_SR_VSYNC   DCMI_SR_VSYNC_Msk
    -
    - -
    -
    - -

    ◆ DCMI_SR_FNE_Pos

    - -
    -
    - - - - -
    #define DCMI_SR_FNE_Pos   (2U)
    -
    - -
    -
    - -

    ◆ DCMI_SR_FNE_Msk

    - -
    -
    - - - - -
    #define DCMI_SR_FNE_Msk   (0x1UL << DCMI_SR_FNE_Pos)
    -
    -

    0x00000004

    - -
    -
    - -

    ◆ DCMI_SR_FNE

    - -
    -
    - - - - -
    #define DCMI_SR_FNE   DCMI_SR_FNE_Msk
    -
    - -
    -
    - -

    ◆ DCMI_RIS_FRAME_RIS_Pos

    - -
    -
    - - - - -
    #define DCMI_RIS_FRAME_RIS_Pos   (0U)
    -
    - -
    -
    - -

    ◆ DCMI_RIS_FRAME_RIS_Msk

    - -
    -
    - - - - -
    #define DCMI_RIS_FRAME_RIS_Msk   (0x1UL << DCMI_RIS_FRAME_RIS_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ DCMI_RIS_FRAME_RIS

    - -
    -
    - - - - -
    #define DCMI_RIS_FRAME_RIS   DCMI_RIS_FRAME_RIS_Msk
    -
    - -
    -
    - -

    ◆ DCMI_RIS_OVR_RIS_Pos

    - -
    -
    - - - - -
    #define DCMI_RIS_OVR_RIS_Pos   (1U)
    -
    - -
    -
    - -

    ◆ DCMI_RIS_OVR_RIS_Msk

    - -
    -
    - - - - -
    #define DCMI_RIS_OVR_RIS_Msk   (0x1UL << DCMI_RIS_OVR_RIS_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ DCMI_RIS_OVR_RIS

    - -
    -
    - - - - -
    #define DCMI_RIS_OVR_RIS   DCMI_RIS_OVR_RIS_Msk
    -
    - -
    -
    - -

    ◆ DCMI_RIS_ERR_RIS_Pos

    - -
    -
    - - - - -
    #define DCMI_RIS_ERR_RIS_Pos   (2U)
    -
    - -
    -
    - -

    ◆ DCMI_RIS_ERR_RIS_Msk

    - -
    -
    - - - - -
    #define DCMI_RIS_ERR_RIS_Msk   (0x1UL << DCMI_RIS_ERR_RIS_Pos)
    -
    -

    0x00000004

    - -
    -
    - -

    ◆ DCMI_RIS_ERR_RIS

    - -
    -
    - - - - -
    #define DCMI_RIS_ERR_RIS   DCMI_RIS_ERR_RIS_Msk
    -
    - -
    -
    - -

    ◆ DCMI_RIS_VSYNC_RIS_Pos

    - -
    -
    - - - - -
    #define DCMI_RIS_VSYNC_RIS_Pos   (3U)
    -
    - -
    -
    - -

    ◆ DCMI_RIS_VSYNC_RIS_Msk

    - -
    -
    - - - - -
    #define DCMI_RIS_VSYNC_RIS_Msk   (0x1UL << DCMI_RIS_VSYNC_RIS_Pos)
    -
    -

    0x00000008

    - -
    -
    - -

    ◆ DCMI_RIS_VSYNC_RIS

    - -
    -
    - - - - -
    #define DCMI_RIS_VSYNC_RIS   DCMI_RIS_VSYNC_RIS_Msk
    -
    - -
    -
    - -

    ◆ DCMI_RIS_LINE_RIS_Pos

    - -
    -
    - - - - -
    #define DCMI_RIS_LINE_RIS_Pos   (4U)
    -
    - -
    -
    - -

    ◆ DCMI_RIS_LINE_RIS_Msk

    - -
    -
    - - - - -
    #define DCMI_RIS_LINE_RIS_Msk   (0x1UL << DCMI_RIS_LINE_RIS_Pos)
    -
    -

    0x00000010

    - -
    -
    - -

    ◆ DCMI_RIS_LINE_RIS

    - -
    -
    - - - - -
    #define DCMI_RIS_LINE_RIS   DCMI_RIS_LINE_RIS_Msk
    -
    - -
    -
    - -

    ◆ DCMI_RISR_FRAME_RIS

    - -
    -
    - - - - -
    #define DCMI_RISR_FRAME_RIS   DCMI_RIS_FRAME_RIS
    -
    - -
    -
    - -

    ◆ DCMI_RISR_OVR_RIS

    - -
    -
    - - - - -
    #define DCMI_RISR_OVR_RIS   DCMI_RIS_OVR_RIS
    -
    - -
    -
    - -

    ◆ DCMI_RISR_ERR_RIS

    - -
    -
    - - - - -
    #define DCMI_RISR_ERR_RIS   DCMI_RIS_ERR_RIS
    -
    - -
    -
    - -

    ◆ DCMI_RISR_VSYNC_RIS

    - -
    -
    - - - - -
    #define DCMI_RISR_VSYNC_RIS   DCMI_RIS_VSYNC_RIS
    -
    - -
    -
    - -

    ◆ DCMI_RISR_LINE_RIS

    - -
    -
    - - - - -
    #define DCMI_RISR_LINE_RIS   DCMI_RIS_LINE_RIS
    -
    - -
    -
    - -

    ◆ DCMI_RISR_OVF_RIS

    - -
    -
    - - - - -
    #define DCMI_RISR_OVF_RIS   DCMI_RIS_OVR_RIS
    -
    - -
    -
    - -

    ◆ DCMI_IER_FRAME_IE_Pos

    - -
    -
    - - - - -
    #define DCMI_IER_FRAME_IE_Pos   (0U)
    -
    - -
    -
    - -

    ◆ DCMI_IER_FRAME_IE_Msk

    - -
    -
    - - - - -
    #define DCMI_IER_FRAME_IE_Msk   (0x1UL << DCMI_IER_FRAME_IE_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ DCMI_IER_FRAME_IE

    - -
    -
    - - - - -
    #define DCMI_IER_FRAME_IE   DCMI_IER_FRAME_IE_Msk
    -
    - -
    -
    - -

    ◆ DCMI_IER_OVR_IE_Pos

    - -
    -
    - - - - -
    #define DCMI_IER_OVR_IE_Pos   (1U)
    -
    - -
    -
    - -

    ◆ DCMI_IER_OVR_IE_Msk

    - -
    -
    - - - - -
    #define DCMI_IER_OVR_IE_Msk   (0x1UL << DCMI_IER_OVR_IE_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ DCMI_IER_OVR_IE

    - -
    -
    - - - - -
    #define DCMI_IER_OVR_IE   DCMI_IER_OVR_IE_Msk
    -
    - -
    -
    - -

    ◆ DCMI_IER_ERR_IE_Pos

    - -
    -
    - - - - -
    #define DCMI_IER_ERR_IE_Pos   (2U)
    -
    - -
    -
    - -

    ◆ DCMI_IER_ERR_IE_Msk

    - -
    -
    - - - - -
    #define DCMI_IER_ERR_IE_Msk   (0x1UL << DCMI_IER_ERR_IE_Pos)
    -
    -

    0x00000004

    - -
    -
    - -

    ◆ DCMI_IER_ERR_IE

    - -
    -
    - - - - -
    #define DCMI_IER_ERR_IE   DCMI_IER_ERR_IE_Msk
    -
    - -
    -
    - -

    ◆ DCMI_IER_VSYNC_IE_Pos

    - -
    -
    - - - - -
    #define DCMI_IER_VSYNC_IE_Pos   (3U)
    -
    - -
    -
    - -

    ◆ DCMI_IER_VSYNC_IE_Msk

    - -
    -
    - - - - -
    #define DCMI_IER_VSYNC_IE_Msk   (0x1UL << DCMI_IER_VSYNC_IE_Pos)
    -
    -

    0x00000008

    - -
    -
    - -

    ◆ DCMI_IER_VSYNC_IE

    - -
    -
    - - - - -
    #define DCMI_IER_VSYNC_IE   DCMI_IER_VSYNC_IE_Msk
    -
    - -
    -
    - -

    ◆ DCMI_IER_LINE_IE_Pos

    - -
    -
    - - - - -
    #define DCMI_IER_LINE_IE_Pos   (4U)
    -
    - -
    -
    - -

    ◆ DCMI_IER_LINE_IE_Msk

    - -
    -
    - - - - -
    #define DCMI_IER_LINE_IE_Msk   (0x1UL << DCMI_IER_LINE_IE_Pos)
    -
    -

    0x00000010

    - -
    -
    - -

    ◆ DCMI_IER_LINE_IE

    - -
    -
    - - - - -
    #define DCMI_IER_LINE_IE   DCMI_IER_LINE_IE_Msk
    -
    - -
    -
    - -

    ◆ DCMI_IER_OVF_IE

    - -
    -
    - - - - -
    #define DCMI_IER_OVF_IE   DCMI_IER_OVR_IE
    -
    - -
    -
    - -

    ◆ DCMI_MIS_FRAME_MIS_Pos

    - -
    -
    - - - - -
    #define DCMI_MIS_FRAME_MIS_Pos   (0U)
    -
    - -
    -
    - -

    ◆ DCMI_MIS_FRAME_MIS_Msk

    - -
    -
    - - - - -
    #define DCMI_MIS_FRAME_MIS_Msk   (0x1UL << DCMI_MIS_FRAME_MIS_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ DCMI_MIS_FRAME_MIS

    - -
    -
    - - - - -
    #define DCMI_MIS_FRAME_MIS   DCMI_MIS_FRAME_MIS_Msk
    -
    - -
    -
    - -

    ◆ DCMI_MIS_OVR_MIS_Pos

    - -
    -
    - - - - -
    #define DCMI_MIS_OVR_MIS_Pos   (1U)
    -
    - -
    -
    - -

    ◆ DCMI_MIS_OVR_MIS_Msk

    - -
    -
    - - - - -
    #define DCMI_MIS_OVR_MIS_Msk   (0x1UL << DCMI_MIS_OVR_MIS_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ DCMI_MIS_OVR_MIS

    - -
    -
    - - - - -
    #define DCMI_MIS_OVR_MIS   DCMI_MIS_OVR_MIS_Msk
    -
    - -
    -
    - -

    ◆ DCMI_MIS_ERR_MIS_Pos

    - -
    -
    - - - - -
    #define DCMI_MIS_ERR_MIS_Pos   (2U)
    -
    - -
    -
    - -

    ◆ DCMI_MIS_ERR_MIS_Msk

    - -
    -
    - - - - -
    #define DCMI_MIS_ERR_MIS_Msk   (0x1UL << DCMI_MIS_ERR_MIS_Pos)
    -
    -

    0x00000004

    - -
    -
    - -

    ◆ DCMI_MIS_ERR_MIS

    - -
    -
    - - - - -
    #define DCMI_MIS_ERR_MIS   DCMI_MIS_ERR_MIS_Msk
    -
    - -
    -
    - -

    ◆ DCMI_MIS_VSYNC_MIS_Pos

    - -
    -
    - - - - -
    #define DCMI_MIS_VSYNC_MIS_Pos   (3U)
    -
    - -
    -
    - -

    ◆ DCMI_MIS_VSYNC_MIS_Msk

    - -
    -
    - - - - -
    #define DCMI_MIS_VSYNC_MIS_Msk   (0x1UL << DCMI_MIS_VSYNC_MIS_Pos)
    -
    -

    0x00000008

    - -
    -
    - -

    ◆ DCMI_MIS_VSYNC_MIS

    - -
    -
    - - - - -
    #define DCMI_MIS_VSYNC_MIS   DCMI_MIS_VSYNC_MIS_Msk
    -
    - -
    -
    - -

    ◆ DCMI_MIS_LINE_MIS_Pos

    - -
    -
    - - - - -
    #define DCMI_MIS_LINE_MIS_Pos   (4U)
    -
    - -
    -
    - -

    ◆ DCMI_MIS_LINE_MIS_Msk

    - -
    -
    - - - - -
    #define DCMI_MIS_LINE_MIS_Msk   (0x1UL << DCMI_MIS_LINE_MIS_Pos)
    -
    -

    0x00000010

    - -
    -
    - -

    ◆ DCMI_MIS_LINE_MIS

    - -
    -
    - - - - -
    #define DCMI_MIS_LINE_MIS   DCMI_MIS_LINE_MIS_Msk
    -
    - -
    -
    - -

    ◆ DCMI_MISR_FRAME_MIS

    - -
    -
    - - - - -
    #define DCMI_MISR_FRAME_MIS   DCMI_MIS_FRAME_MIS
    -
    - -
    -
    - -

    ◆ DCMI_MISR_OVF_MIS

    - -
    -
    - - - - -
    #define DCMI_MISR_OVF_MIS   DCMI_MIS_OVR_MIS
    -
    - -
    -
    - -

    ◆ DCMI_MISR_ERR_MIS

    - -
    -
    - - - - -
    #define DCMI_MISR_ERR_MIS   DCMI_MIS_ERR_MIS
    -
    - -
    -
    - -

    ◆ DCMI_MISR_VSYNC_MIS

    - -
    -
    - - - - -
    #define DCMI_MISR_VSYNC_MIS   DCMI_MIS_VSYNC_MIS
    -
    - -
    -
    - -

    ◆ DCMI_MISR_LINE_MIS

    - -
    -
    - - - - -
    #define DCMI_MISR_LINE_MIS   DCMI_MIS_LINE_MIS
    -
    - -
    -
    - -

    ◆ DCMI_ICR_FRAME_ISC_Pos

    - -
    -
    - - - - -
    #define DCMI_ICR_FRAME_ISC_Pos   (0U)
    -
    - -
    -
    - -

    ◆ DCMI_ICR_FRAME_ISC_Msk

    - -
    -
    - - - - -
    #define DCMI_ICR_FRAME_ISC_Msk   (0x1UL << DCMI_ICR_FRAME_ISC_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ DCMI_ICR_FRAME_ISC

    - -
    -
    - - - - -
    #define DCMI_ICR_FRAME_ISC   DCMI_ICR_FRAME_ISC_Msk
    -
    - -
    -
    - -

    ◆ DCMI_ICR_OVR_ISC_Pos

    - -
    -
    - - - - -
    #define DCMI_ICR_OVR_ISC_Pos   (1U)
    -
    - -
    -
    - -

    ◆ DCMI_ICR_OVR_ISC_Msk

    - -
    -
    - - - - -
    #define DCMI_ICR_OVR_ISC_Msk   (0x1UL << DCMI_ICR_OVR_ISC_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ DCMI_ICR_OVR_ISC

    - -
    -
    - - - - -
    #define DCMI_ICR_OVR_ISC   DCMI_ICR_OVR_ISC_Msk
    -
    - -
    -
    - -

    ◆ DCMI_ICR_ERR_ISC_Pos

    - -
    -
    - - - - -
    #define DCMI_ICR_ERR_ISC_Pos   (2U)
    -
    - -
    -
    - -

    ◆ DCMI_ICR_ERR_ISC_Msk

    - -
    -
    - - - - -
    #define DCMI_ICR_ERR_ISC_Msk   (0x1UL << DCMI_ICR_ERR_ISC_Pos)
    -
    -

    0x00000004

    - -
    -
    - -

    ◆ DCMI_ICR_ERR_ISC

    - -
    -
    - - - - -
    #define DCMI_ICR_ERR_ISC   DCMI_ICR_ERR_ISC_Msk
    -
    - -
    -
    - -

    ◆ DCMI_ICR_VSYNC_ISC_Pos

    - -
    -
    - - - - -
    #define DCMI_ICR_VSYNC_ISC_Pos   (3U)
    -
    - -
    -
    - -

    ◆ DCMI_ICR_VSYNC_ISC_Msk

    - -
    -
    - - - - -
    #define DCMI_ICR_VSYNC_ISC_Msk   (0x1UL << DCMI_ICR_VSYNC_ISC_Pos)
    -
    -

    0x00000008

    - -
    -
    - -

    ◆ DCMI_ICR_VSYNC_ISC

    - -
    -
    - - - - -
    #define DCMI_ICR_VSYNC_ISC   DCMI_ICR_VSYNC_ISC_Msk
    -
    - -
    -
    - -

    ◆ DCMI_ICR_LINE_ISC_Pos

    - -
    -
    - - - - -
    #define DCMI_ICR_LINE_ISC_Pos   (4U)
    -
    - -
    -
    - -

    ◆ DCMI_ICR_LINE_ISC_Msk

    - -
    -
    - - - - -
    #define DCMI_ICR_LINE_ISC_Msk   (0x1UL << DCMI_ICR_LINE_ISC_Pos)
    -
    -

    0x00000010

    - -
    -
    - -

    ◆ DCMI_ICR_LINE_ISC

    - -
    -
    - - - - -
    #define DCMI_ICR_LINE_ISC   DCMI_ICR_LINE_ISC_Msk
    -
    - -
    -
    - -

    ◆ DCMI_ICR_OVF_ISC

    - -
    -
    - - - - -
    #define DCMI_ICR_OVF_ISC   DCMI_ICR_OVR_ISC
    -
    - -
    -
    - -

    ◆ DCMI_ESCR_FSC_Pos

    - -
    -
    - - - - -
    #define DCMI_ESCR_FSC_Pos   (0U)
    -
    - -
    -
    - -

    ◆ DCMI_ESCR_FSC_Msk

    - -
    -
    - - - - -
    #define DCMI_ESCR_FSC_Msk   (0xFFUL << DCMI_ESCR_FSC_Pos)
    -
    -

    0x000000FF

    - -
    -
    - -

    ◆ DCMI_ESCR_FSC

    - -
    -
    - - - - -
    #define DCMI_ESCR_FSC   DCMI_ESCR_FSC_Msk
    -
    - -
    -
    - -

    ◆ DCMI_ESCR_LSC_Pos

    - -
    -
    - - - - -
    #define DCMI_ESCR_LSC_Pos   (8U)
    -
    - -
    -
    - -

    ◆ DCMI_ESCR_LSC_Msk

    - -
    -
    - - - - -
    #define DCMI_ESCR_LSC_Msk   (0xFFUL << DCMI_ESCR_LSC_Pos)
    -
    -

    0x0000FF00

    - -
    -
    - -

    ◆ DCMI_ESCR_LSC

    - -
    -
    - - - - -
    #define DCMI_ESCR_LSC   DCMI_ESCR_LSC_Msk
    -
    - -
    -
    - -

    ◆ DCMI_ESCR_LEC_Pos

    - -
    -
    - - - - -
    #define DCMI_ESCR_LEC_Pos   (16U)
    -
    - -
    -
    - -

    ◆ DCMI_ESCR_LEC_Msk

    - -
    -
    - - - - -
    #define DCMI_ESCR_LEC_Msk   (0xFFUL << DCMI_ESCR_LEC_Pos)
    -
    -

    0x00FF0000

    - -
    -
    - -

    ◆ DCMI_ESCR_LEC

    - -
    -
    - - - - -
    #define DCMI_ESCR_LEC   DCMI_ESCR_LEC_Msk
    -
    - -
    -
    - -

    ◆ DCMI_ESCR_FEC_Pos

    - -
    -
    - - - - -
    #define DCMI_ESCR_FEC_Pos   (24U)
    -
    - -
    -
    - -

    ◆ DCMI_ESCR_FEC_Msk

    - -
    -
    - - - - -
    #define DCMI_ESCR_FEC_Msk   (0xFFUL << DCMI_ESCR_FEC_Pos)
    -
    -

    0xFF000000

    - -
    -
    - -

    ◆ DCMI_ESCR_FEC

    - -
    -
    - - - - -
    #define DCMI_ESCR_FEC   DCMI_ESCR_FEC_Msk
    -
    - -
    -
    - -

    ◆ DCMI_ESUR_FSU_Pos

    - -
    -
    - - - - -
    #define DCMI_ESUR_FSU_Pos   (0U)
    -
    - -
    -
    - -

    ◆ DCMI_ESUR_FSU_Msk

    - -
    -
    - - - - -
    #define DCMI_ESUR_FSU_Msk   (0xFFUL << DCMI_ESUR_FSU_Pos)
    -
    -

    0x000000FF

    - -
    -
    - -

    ◆ DCMI_ESUR_FSU

    - -
    -
    - - - - -
    #define DCMI_ESUR_FSU   DCMI_ESUR_FSU_Msk
    -
    - -
    -
    - -

    ◆ DCMI_ESUR_LSU_Pos

    - -
    -
    - - - - -
    #define DCMI_ESUR_LSU_Pos   (8U)
    -
    - -
    -
    - -

    ◆ DCMI_ESUR_LSU_Msk

    - -
    -
    - - - - -
    #define DCMI_ESUR_LSU_Msk   (0xFFUL << DCMI_ESUR_LSU_Pos)
    -
    -

    0x0000FF00

    - -
    -
    - -

    ◆ DCMI_ESUR_LSU

    - -
    -
    - - - - -
    #define DCMI_ESUR_LSU   DCMI_ESUR_LSU_Msk
    -
    - -
    -
    - -

    ◆ DCMI_ESUR_LEU_Pos

    - -
    -
    - - - - -
    #define DCMI_ESUR_LEU_Pos   (16U)
    -
    - -
    -
    - -

    ◆ DCMI_ESUR_LEU_Msk

    - -
    -
    - - - - -
    #define DCMI_ESUR_LEU_Msk   (0xFFUL << DCMI_ESUR_LEU_Pos)
    -
    -

    0x00FF0000

    - -
    -
    - -

    ◆ DCMI_ESUR_LEU

    - -
    -
    - - - - -
    #define DCMI_ESUR_LEU   DCMI_ESUR_LEU_Msk
    -
    - -
    -
    - -

    ◆ DCMI_ESUR_FEU_Pos

    - -
    -
    - - - - -
    #define DCMI_ESUR_FEU_Pos   (24U)
    -
    - -
    -
    - -

    ◆ DCMI_ESUR_FEU_Msk

    - -
    -
    - - - - -
    #define DCMI_ESUR_FEU_Msk   (0xFFUL << DCMI_ESUR_FEU_Pos)
    -
    -

    0xFF000000

    - -
    -
    - -

    ◆ DCMI_ESUR_FEU

    - -
    -
    - - - - -
    #define DCMI_ESUR_FEU   DCMI_ESUR_FEU_Msk
    -
    - -
    -
    - -

    ◆ DCMI_CWSTRT_HOFFCNT_Pos

    - -
    -
    - - - - -
    #define DCMI_CWSTRT_HOFFCNT_Pos   (0U)
    -
    - -
    -
    - -

    ◆ DCMI_CWSTRT_HOFFCNT_Msk

    - -
    -
    - - - - -
    #define DCMI_CWSTRT_HOFFCNT_Msk   (0x3FFFUL << DCMI_CWSTRT_HOFFCNT_Pos)
    -
    -

    0x00003FFF

    - -
    -
    - -

    ◆ DCMI_CWSTRT_HOFFCNT

    - -
    -
    - - - - -
    #define DCMI_CWSTRT_HOFFCNT   DCMI_CWSTRT_HOFFCNT_Msk
    -
    - -
    -
    - -

    ◆ DCMI_CWSTRT_VST_Pos

    - -
    -
    - - - - -
    #define DCMI_CWSTRT_VST_Pos   (16U)
    -
    - -
    -
    - -

    ◆ DCMI_CWSTRT_VST_Msk

    - -
    -
    - - - - -
    #define DCMI_CWSTRT_VST_Msk   (0x1FFFUL << DCMI_CWSTRT_VST_Pos)
    -
    -

    0x1FFF0000

    - -
    -
    - -

    ◆ DCMI_CWSTRT_VST

    - -
    -
    - - - - -
    #define DCMI_CWSTRT_VST   DCMI_CWSTRT_VST_Msk
    -
    - -
    -
    - -

    ◆ DCMI_CWSIZE_CAPCNT_Pos

    - -
    -
    - - - - -
    #define DCMI_CWSIZE_CAPCNT_Pos   (0U)
    -
    - -
    -
    - -

    ◆ DCMI_CWSIZE_CAPCNT_Msk

    - -
    -
    - - - - -
    #define DCMI_CWSIZE_CAPCNT_Msk   (0x3FFFUL << DCMI_CWSIZE_CAPCNT_Pos)
    -
    -

    0x00003FFF

    - -
    -
    - -

    ◆ DCMI_CWSIZE_CAPCNT

    - -
    -
    - - - - -
    #define DCMI_CWSIZE_CAPCNT   DCMI_CWSIZE_CAPCNT_Msk
    -
    - -
    -
    - -

    ◆ DCMI_CWSIZE_VLINE_Pos

    - -
    -
    - - - - -
    #define DCMI_CWSIZE_VLINE_Pos   (16U)
    -
    - -
    -
    - -

    ◆ DCMI_CWSIZE_VLINE_Msk

    - -
    -
    - - - - -
    #define DCMI_CWSIZE_VLINE_Msk   (0x3FFFUL << DCMI_CWSIZE_VLINE_Pos)
    -
    -

    0x3FFF0000

    - -
    -
    - -

    ◆ DCMI_CWSIZE_VLINE

    - -
    -
    - - - - -
    #define DCMI_CWSIZE_VLINE   DCMI_CWSIZE_VLINE_Msk
    -
    - -
    -
    - -

    ◆ DCMI_DR_BYTE0_Pos

    - -
    -
    - - - - -
    #define DCMI_DR_BYTE0_Pos   (0U)
    -
    - -
    -
    - -

    ◆ DCMI_DR_BYTE0_Msk

    - -
    -
    - - - - -
    #define DCMI_DR_BYTE0_Msk   (0xFFUL << DCMI_DR_BYTE0_Pos)
    -
    -

    0x000000FF

    - -
    -
    - -

    ◆ DCMI_DR_BYTE0

    - -
    -
    - - - - -
    #define DCMI_DR_BYTE0   DCMI_DR_BYTE0_Msk
    -
    - -
    -
    - -

    ◆ DCMI_DR_BYTE1_Pos

    - -
    -
    - - - - -
    #define DCMI_DR_BYTE1_Pos   (8U)
    -
    - -
    -
    - -

    ◆ DCMI_DR_BYTE1_Msk

    - -
    -
    - - - - -
    #define DCMI_DR_BYTE1_Msk   (0xFFUL << DCMI_DR_BYTE1_Pos)
    -
    -

    0x0000FF00

    - -
    -
    - -

    ◆ DCMI_DR_BYTE1

    - -
    -
    - - - - -
    #define DCMI_DR_BYTE1   DCMI_DR_BYTE1_Msk
    -
    - -
    -
    - -

    ◆ DCMI_DR_BYTE2_Pos

    - -
    -
    - - - - -
    #define DCMI_DR_BYTE2_Pos   (16U)
    -
    - -
    -
    - -

    ◆ DCMI_DR_BYTE2_Msk

    - -
    -
    - - - - -
    #define DCMI_DR_BYTE2_Msk   (0xFFUL << DCMI_DR_BYTE2_Pos)
    -
    -

    0x00FF0000

    - -
    -
    - -

    ◆ DCMI_DR_BYTE2

    - -
    -
    - - - - -
    #define DCMI_DR_BYTE2   DCMI_DR_BYTE2_Msk
    -
    - -
    -
    - -

    ◆ DCMI_DR_BYTE3_Pos

    - -
    -
    - - - - -
    #define DCMI_DR_BYTE3_Pos   (24U)
    -
    - -
    -
    - -

    ◆ DCMI_DR_BYTE3_Msk

    - -
    -
    - - - - -
    #define DCMI_DR_BYTE3_Msk   (0xFFUL << DCMI_DR_BYTE3_Pos)
    -
    -

    0xFF000000

    - -
    -
    - -

    ◆ DCMI_DR_BYTE3

    - -
    -
    - - - - -
    #define DCMI_DR_BYTE3   DCMI_DR_BYTE3_Msk
    -
    - -
    -
    - -

    ◆ DMA_SxCR_CHSEL_Pos

    - -
    -
    - - - - -
    #define DMA_SxCR_CHSEL_Pos   (25U)
    -
    - -
    -
    - -

    ◆ DMA_SxCR_CHSEL_Msk

    - -
    -
    - - - - -
    #define DMA_SxCR_CHSEL_Msk   (0x7UL << DMA_SxCR_CHSEL_Pos)
    -
    -

    0x0E000000

    - -
    -
    - -

    ◆ DMA_SxCR_CHSEL

    - -
    -
    - - - - -
    #define DMA_SxCR_CHSEL   DMA_SxCR_CHSEL_Msk
    -
    - -
    -
    - -

    ◆ DMA_SxCR_CHSEL_0

    - -
    -
    - - - - -
    #define DMA_SxCR_CHSEL_0   0x02000000U
    -
    - -
    -
    - -

    ◆ DMA_SxCR_CHSEL_1

    - -
    -
    - - - - -
    #define DMA_SxCR_CHSEL_1   0x04000000U
    -
    - -
    -
    - -

    ◆ DMA_SxCR_CHSEL_2

    - -
    -
    - - - - -
    #define DMA_SxCR_CHSEL_2   0x08000000U
    -
    - -
    -
    - -

    ◆ DMA_SxCR_MBURST_Pos

    - -
    -
    - - - - -
    #define DMA_SxCR_MBURST_Pos   (23U)
    -
    - -
    -
    - -

    ◆ DMA_SxCR_MBURST_Msk

    - -
    -
    - - - - -
    #define DMA_SxCR_MBURST_Msk   (0x3UL << DMA_SxCR_MBURST_Pos)
    -
    -

    0x01800000

    - -
    -
    - -

    ◆ DMA_SxCR_MBURST

    - -
    -
    - - - - -
    #define DMA_SxCR_MBURST   DMA_SxCR_MBURST_Msk
    -
    - -
    -
    - -

    ◆ DMA_SxCR_MBURST_0

    - -
    -
    - - - - -
    #define DMA_SxCR_MBURST_0   (0x1UL << DMA_SxCR_MBURST_Pos)
    -
    -

    0x00800000

    - -
    -
    - -

    ◆ DMA_SxCR_MBURST_1

    - -
    -
    - - - - -
    #define DMA_SxCR_MBURST_1   (0x2UL << DMA_SxCR_MBURST_Pos)
    -
    -

    0x01000000

    - -
    -
    - -

    ◆ DMA_SxCR_PBURST_Pos

    - -
    -
    - - - - -
    #define DMA_SxCR_PBURST_Pos   (21U)
    -
    - -
    -
    - -

    ◆ DMA_SxCR_PBURST_Msk

    - -
    -
    - - - - -
    #define DMA_SxCR_PBURST_Msk   (0x3UL << DMA_SxCR_PBURST_Pos)
    -
    -

    0x00600000

    - -
    -
    - -

    ◆ DMA_SxCR_PBURST

    - -
    -
    - - - - -
    #define DMA_SxCR_PBURST   DMA_SxCR_PBURST_Msk
    -
    - -
    -
    - -

    ◆ DMA_SxCR_PBURST_0

    - -
    -
    - - - - -
    #define DMA_SxCR_PBURST_0   (0x1UL << DMA_SxCR_PBURST_Pos)
    -
    -

    0x00200000

    - -
    -
    - -

    ◆ DMA_SxCR_PBURST_1

    - -
    -
    - - - - -
    #define DMA_SxCR_PBURST_1   (0x2UL << DMA_SxCR_PBURST_Pos)
    -
    -

    0x00400000

    - -
    -
    - -

    ◆ DMA_SxCR_CT_Pos

    - -
    -
    - - - - -
    #define DMA_SxCR_CT_Pos   (19U)
    -
    - -
    -
    - -

    ◆ DMA_SxCR_CT_Msk

    - -
    -
    - - - - -
    #define DMA_SxCR_CT_Msk   (0x1UL << DMA_SxCR_CT_Pos)
    -
    -

    0x00080000

    - -
    -
    - -

    ◆ DMA_SxCR_CT

    - -
    -
    - - - - -
    #define DMA_SxCR_CT   DMA_SxCR_CT_Msk
    -
    - -
    -
    - -

    ◆ DMA_SxCR_DBM_Pos

    - -
    -
    - - - - -
    #define DMA_SxCR_DBM_Pos   (18U)
    -
    - -
    -
    - -

    ◆ DMA_SxCR_DBM_Msk

    - -
    -
    - - - - -
    #define DMA_SxCR_DBM_Msk   (0x1UL << DMA_SxCR_DBM_Pos)
    -
    -

    0x00040000

    - -
    -
    - -

    ◆ DMA_SxCR_DBM

    - -
    -
    - - - - -
    #define DMA_SxCR_DBM   DMA_SxCR_DBM_Msk
    -
    - -
    -
    - -

    ◆ DMA_SxCR_PL_Pos

    - -
    -
    - - - - -
    #define DMA_SxCR_PL_Pos   (16U)
    -
    - -
    -
    - -

    ◆ DMA_SxCR_PL_Msk

    - -
    -
    - - - - -
    #define DMA_SxCR_PL_Msk   (0x3UL << DMA_SxCR_PL_Pos)
    -
    -

    0x00030000

    - -
    -
    - -

    ◆ DMA_SxCR_PL

    - -
    -
    - - - - -
    #define DMA_SxCR_PL   DMA_SxCR_PL_Msk
    -
    - -
    -
    - -

    ◆ DMA_SxCR_PL_0

    - -
    -
    - - - - -
    #define DMA_SxCR_PL_0   (0x1UL << DMA_SxCR_PL_Pos)
    -
    -

    0x00010000

    - -
    -
    - -

    ◆ DMA_SxCR_PL_1

    - -
    -
    - - - - -
    #define DMA_SxCR_PL_1   (0x2UL << DMA_SxCR_PL_Pos)
    -
    -

    0x00020000

    - -
    -
    - -

    ◆ DMA_SxCR_PINCOS_Pos

    - -
    -
    - - - - -
    #define DMA_SxCR_PINCOS_Pos   (15U)
    -
    - -
    -
    - -

    ◆ DMA_SxCR_PINCOS_Msk

    - -
    -
    - - - - -
    #define DMA_SxCR_PINCOS_Msk   (0x1UL << DMA_SxCR_PINCOS_Pos)
    -
    -

    0x00008000

    - -
    -
    - -

    ◆ DMA_SxCR_PINCOS

    - -
    -
    - - - - -
    #define DMA_SxCR_PINCOS   DMA_SxCR_PINCOS_Msk
    -
    - -
    -
    - -

    ◆ DMA_SxCR_MSIZE_Pos

    - -
    -
    - - - - -
    #define DMA_SxCR_MSIZE_Pos   (13U)
    -
    - -
    -
    - -

    ◆ DMA_SxCR_MSIZE_Msk

    - -
    -
    - - - - -
    #define DMA_SxCR_MSIZE_Msk   (0x3UL << DMA_SxCR_MSIZE_Pos)
    -
    -

    0x00006000

    - -
    -
    - -

    ◆ DMA_SxCR_MSIZE

    - -
    -
    - - - - -
    #define DMA_SxCR_MSIZE   DMA_SxCR_MSIZE_Msk
    -
    - -
    -
    - -

    ◆ DMA_SxCR_MSIZE_0

    - -
    -
    - - - - -
    #define DMA_SxCR_MSIZE_0   (0x1UL << DMA_SxCR_MSIZE_Pos)
    -
    -

    0x00002000

    - -
    -
    - -

    ◆ DMA_SxCR_MSIZE_1

    - -
    -
    - - - - -
    #define DMA_SxCR_MSIZE_1   (0x2UL << DMA_SxCR_MSIZE_Pos)
    -
    -

    0x00004000

    - -
    -
    - -

    ◆ DMA_SxCR_PSIZE_Pos

    - -
    -
    - - - - -
    #define DMA_SxCR_PSIZE_Pos   (11U)
    -
    - -
    -
    - -

    ◆ DMA_SxCR_PSIZE_Msk

    - -
    -
    - - - - -
    #define DMA_SxCR_PSIZE_Msk   (0x3UL << DMA_SxCR_PSIZE_Pos)
    -
    -

    0x00001800

    - -
    -
    - -

    ◆ DMA_SxCR_PSIZE

    - -
    -
    - - - - -
    #define DMA_SxCR_PSIZE   DMA_SxCR_PSIZE_Msk
    -
    - -
    -
    - -

    ◆ DMA_SxCR_PSIZE_0

    - -
    -
    - - - - -
    #define DMA_SxCR_PSIZE_0   (0x1UL << DMA_SxCR_PSIZE_Pos)
    -
    -

    0x00000800

    - -
    -
    - -

    ◆ DMA_SxCR_PSIZE_1

    - -
    -
    - - - - -
    #define DMA_SxCR_PSIZE_1   (0x2UL << DMA_SxCR_PSIZE_Pos)
    -
    -

    0x00001000

    - -
    -
    - -

    ◆ DMA_SxCR_MINC_Pos

    - -
    -
    - - - - -
    #define DMA_SxCR_MINC_Pos   (10U)
    -
    - -
    -
    - -

    ◆ DMA_SxCR_MINC_Msk

    - -
    -
    - - - - -
    #define DMA_SxCR_MINC_Msk   (0x1UL << DMA_SxCR_MINC_Pos)
    -
    -

    0x00000400

    - -
    -
    - -

    ◆ DMA_SxCR_MINC

    - -
    -
    - - - - -
    #define DMA_SxCR_MINC   DMA_SxCR_MINC_Msk
    -
    - -
    -
    - -

    ◆ DMA_SxCR_PINC_Pos

    - -
    -
    - - - - -
    #define DMA_SxCR_PINC_Pos   (9U)
    -
    - -
    -
    - -

    ◆ DMA_SxCR_PINC_Msk

    - -
    -
    - - - - -
    #define DMA_SxCR_PINC_Msk   (0x1UL << DMA_SxCR_PINC_Pos)
    -
    -

    0x00000200

    - -
    -
    - -

    ◆ DMA_SxCR_PINC

    - -
    -
    - - - - -
    #define DMA_SxCR_PINC   DMA_SxCR_PINC_Msk
    -
    - -
    -
    - -

    ◆ DMA_SxCR_CIRC_Pos

    - -
    -
    - - - - -
    #define DMA_SxCR_CIRC_Pos   (8U)
    -
    - -
    -
    - -

    ◆ DMA_SxCR_CIRC_Msk

    - -
    -
    - - - - -
    #define DMA_SxCR_CIRC_Msk   (0x1UL << DMA_SxCR_CIRC_Pos)
    -
    -

    0x00000100

    - -
    -
    - -

    ◆ DMA_SxCR_CIRC

    - -
    -
    - - - - -
    #define DMA_SxCR_CIRC   DMA_SxCR_CIRC_Msk
    -
    - -
    -
    - -

    ◆ DMA_SxCR_DIR_Pos

    - -
    -
    - - - - -
    #define DMA_SxCR_DIR_Pos   (6U)
    -
    - -
    -
    - -

    ◆ DMA_SxCR_DIR_Msk

    - -
    -
    - - - - -
    #define DMA_SxCR_DIR_Msk   (0x3UL << DMA_SxCR_DIR_Pos)
    -
    -

    0x000000C0

    - -
    -
    - -

    ◆ DMA_SxCR_DIR

    - -
    -
    - - - - -
    #define DMA_SxCR_DIR   DMA_SxCR_DIR_Msk
    -
    - -
    -
    - -

    ◆ DMA_SxCR_DIR_0

    - -
    -
    - - - - -
    #define DMA_SxCR_DIR_0   (0x1UL << DMA_SxCR_DIR_Pos)
    -
    -

    0x00000040

    - -
    -
    - -

    ◆ DMA_SxCR_DIR_1

    - -
    -
    - - - - -
    #define DMA_SxCR_DIR_1   (0x2UL << DMA_SxCR_DIR_Pos)
    -
    -

    0x00000080

    - -
    -
    - -

    ◆ DMA_SxCR_PFCTRL_Pos

    - -
    -
    - - - - -
    #define DMA_SxCR_PFCTRL_Pos   (5U)
    -
    - -
    -
    - -

    ◆ DMA_SxCR_PFCTRL_Msk

    - -
    -
    - - - - -
    #define DMA_SxCR_PFCTRL_Msk   (0x1UL << DMA_SxCR_PFCTRL_Pos)
    -
    -

    0x00000020

    - -
    -
    - -

    ◆ DMA_SxCR_PFCTRL

    - -
    -
    - - - - -
    #define DMA_SxCR_PFCTRL   DMA_SxCR_PFCTRL_Msk
    -
    - -
    -
    - -

    ◆ DMA_SxCR_TCIE_Pos

    - -
    -
    - - - - -
    #define DMA_SxCR_TCIE_Pos   (4U)
    -
    - -
    -
    - -

    ◆ DMA_SxCR_TCIE_Msk

    - -
    -
    - - - - -
    #define DMA_SxCR_TCIE_Msk   (0x1UL << DMA_SxCR_TCIE_Pos)
    -
    -

    0x00000010

    - -
    -
    - -

    ◆ DMA_SxCR_TCIE

    - -
    -
    - - - - -
    #define DMA_SxCR_TCIE   DMA_SxCR_TCIE_Msk
    -
    - -
    -
    - -

    ◆ DMA_SxCR_HTIE_Pos

    - -
    -
    - - - - -
    #define DMA_SxCR_HTIE_Pos   (3U)
    -
    - -
    -
    - -

    ◆ DMA_SxCR_HTIE_Msk

    - -
    -
    - - - - -
    #define DMA_SxCR_HTIE_Msk   (0x1UL << DMA_SxCR_HTIE_Pos)
    -
    -

    0x00000008

    - -
    -
    - -

    ◆ DMA_SxCR_HTIE

    - -
    -
    - - - - -
    #define DMA_SxCR_HTIE   DMA_SxCR_HTIE_Msk
    -
    - -
    -
    - -

    ◆ DMA_SxCR_TEIE_Pos

    - -
    -
    - - - - -
    #define DMA_SxCR_TEIE_Pos   (2U)
    -
    - -
    -
    - -

    ◆ DMA_SxCR_TEIE_Msk

    - -
    -
    - - - - -
    #define DMA_SxCR_TEIE_Msk   (0x1UL << DMA_SxCR_TEIE_Pos)
    -
    -

    0x00000004

    - -
    -
    - -

    ◆ DMA_SxCR_TEIE

    - -
    -
    - - - - -
    #define DMA_SxCR_TEIE   DMA_SxCR_TEIE_Msk
    -
    - -
    -
    - -

    ◆ DMA_SxCR_DMEIE_Pos

    - -
    -
    - - - - -
    #define DMA_SxCR_DMEIE_Pos   (1U)
    -
    - -
    -
    - -

    ◆ DMA_SxCR_DMEIE_Msk

    - -
    -
    - - - - -
    #define DMA_SxCR_DMEIE_Msk   (0x1UL << DMA_SxCR_DMEIE_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ DMA_SxCR_DMEIE

    - -
    -
    - - - - -
    #define DMA_SxCR_DMEIE   DMA_SxCR_DMEIE_Msk
    -
    - -
    -
    - -

    ◆ DMA_SxCR_EN_Pos

    - -
    -
    - - - - -
    #define DMA_SxCR_EN_Pos   (0U)
    -
    - -
    -
    - -

    ◆ DMA_SxCR_EN_Msk

    - -
    -
    - - - - -
    #define DMA_SxCR_EN_Msk   (0x1UL << DMA_SxCR_EN_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ DMA_SxCR_EN

    - -
    -
    - - - - -
    #define DMA_SxCR_EN   DMA_SxCR_EN_Msk
    -
    - -
    -
    - -

    ◆ DMA_SxCR_ACK_Pos

    - -
    -
    - - - - -
    #define DMA_SxCR_ACK_Pos   (20U)
    -
    - -
    -
    - -

    ◆ DMA_SxCR_ACK_Msk

    - -
    -
    - - - - -
    #define DMA_SxCR_ACK_Msk   (0x1UL << DMA_SxCR_ACK_Pos)
    -
    -

    0x00100000

    - -
    -
    - -

    ◆ DMA_SxCR_ACK

    - -
    -
    - - - - -
    #define DMA_SxCR_ACK   DMA_SxCR_ACK_Msk
    -
    - -
    -
    - -

    ◆ DMA_SxNDT_Pos

    - -
    -
    - - - - -
    #define DMA_SxNDT_Pos   (0U)
    -
    - -
    -
    - -

    ◆ DMA_SxNDT_Msk

    - -
    -
    - - - - -
    #define DMA_SxNDT_Msk   (0xFFFFUL << DMA_SxNDT_Pos)
    -
    -

    0x0000FFFF

    - -
    -
    - -

    ◆ DMA_SxNDT

    - -
    -
    - - - - -
    #define DMA_SxNDT   DMA_SxNDT_Msk
    -
    - -
    -
    - -

    ◆ DMA_SxNDT_0

    - -
    -
    - - - - -
    #define DMA_SxNDT_0   (0x0001UL << DMA_SxNDT_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ DMA_SxNDT_1

    - -
    -
    - - - - -
    #define DMA_SxNDT_1   (0x0002UL << DMA_SxNDT_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ DMA_SxNDT_2

    - -
    -
    - - - - -
    #define DMA_SxNDT_2   (0x0004UL << DMA_SxNDT_Pos)
    -
    -

    0x00000004

    - -
    -
    - -

    ◆ DMA_SxNDT_3

    - -
    -
    - - - - -
    #define DMA_SxNDT_3   (0x0008UL << DMA_SxNDT_Pos)
    -
    -

    0x00000008

    - -
    -
    - -

    ◆ DMA_SxNDT_4

    - -
    -
    - - - - -
    #define DMA_SxNDT_4   (0x0010UL << DMA_SxNDT_Pos)
    -
    -

    0x00000010

    - -
    -
    - -

    ◆ DMA_SxNDT_5

    - -
    -
    - - - - -
    #define DMA_SxNDT_5   (0x0020UL << DMA_SxNDT_Pos)
    -
    -

    0x00000020

    - -
    -
    - -

    ◆ DMA_SxNDT_6

    - -
    -
    - - - - -
    #define DMA_SxNDT_6   (0x0040UL << DMA_SxNDT_Pos)
    -
    -

    0x00000040

    - -
    -
    - -

    ◆ DMA_SxNDT_7

    - -
    -
    - - - - -
    #define DMA_SxNDT_7   (0x0080UL << DMA_SxNDT_Pos)
    -
    -

    0x00000080

    - -
    -
    - -

    ◆ DMA_SxNDT_8

    - -
    -
    - - - - -
    #define DMA_SxNDT_8   (0x0100UL << DMA_SxNDT_Pos)
    -
    -

    0x00000100

    - -
    -
    - -

    ◆ DMA_SxNDT_9

    - -
    -
    - - - - -
    #define DMA_SxNDT_9   (0x0200UL << DMA_SxNDT_Pos)
    -
    -

    0x00000200

    - -
    -
    - -

    ◆ DMA_SxNDT_10

    - -
    -
    - - - - -
    #define DMA_SxNDT_10   (0x0400UL << DMA_SxNDT_Pos)
    -
    -

    0x00000400

    - -
    -
    - -

    ◆ DMA_SxNDT_11

    - -
    -
    - - - - -
    #define DMA_SxNDT_11   (0x0800UL << DMA_SxNDT_Pos)
    -
    -

    0x00000800

    - -
    -
    - -

    ◆ DMA_SxNDT_12

    - -
    -
    - - - - -
    #define DMA_SxNDT_12   (0x1000UL << DMA_SxNDT_Pos)
    -
    -

    0x00001000

    - -
    -
    - -

    ◆ DMA_SxNDT_13

    - -
    -
    - - - - -
    #define DMA_SxNDT_13   (0x2000UL << DMA_SxNDT_Pos)
    -
    -

    0x00002000

    - -
    -
    - -

    ◆ DMA_SxNDT_14

    - -
    -
    - - - - -
    #define DMA_SxNDT_14   (0x4000UL << DMA_SxNDT_Pos)
    -
    -

    0x00004000

    - -
    -
    - -

    ◆ DMA_SxNDT_15

    - -
    -
    - - - - -
    #define DMA_SxNDT_15   (0x8000UL << DMA_SxNDT_Pos)
    -
    -

    0x00008000

    - -
    -
    - -

    ◆ DMA_SxFCR_FEIE_Pos

    - -
    -
    - - - - -
    #define DMA_SxFCR_FEIE_Pos   (7U)
    -
    - -
    -
    - -

    ◆ DMA_SxFCR_FEIE_Msk

    - -
    -
    - - - - -
    #define DMA_SxFCR_FEIE_Msk   (0x1UL << DMA_SxFCR_FEIE_Pos)
    -
    -

    0x00000080

    - -
    -
    - -

    ◆ DMA_SxFCR_FEIE

    - -
    -
    - - - - -
    #define DMA_SxFCR_FEIE   DMA_SxFCR_FEIE_Msk
    -
    - -
    -
    - -

    ◆ DMA_SxFCR_FS_Pos

    - -
    -
    - - - - -
    #define DMA_SxFCR_FS_Pos   (3U)
    -
    - -
    -
    - -

    ◆ DMA_SxFCR_FS_Msk

    - -
    -
    - - - - -
    #define DMA_SxFCR_FS_Msk   (0x7UL << DMA_SxFCR_FS_Pos)
    -
    -

    0x00000038

    - -
    -
    - -

    ◆ DMA_SxFCR_FS

    - -
    -
    - - - - -
    #define DMA_SxFCR_FS   DMA_SxFCR_FS_Msk
    -
    - -
    -
    - -

    ◆ DMA_SxFCR_FS_0

    - -
    -
    - - - - -
    #define DMA_SxFCR_FS_0   (0x1UL << DMA_SxFCR_FS_Pos)
    -
    -

    0x00000008

    - -
    -
    - -

    ◆ DMA_SxFCR_FS_1

    - -
    -
    - - - - -
    #define DMA_SxFCR_FS_1   (0x2UL << DMA_SxFCR_FS_Pos)
    -
    -

    0x00000010

    - -
    -
    - -

    ◆ DMA_SxFCR_FS_2

    - -
    -
    - - - - -
    #define DMA_SxFCR_FS_2   (0x4UL << DMA_SxFCR_FS_Pos)
    -
    -

    0x00000020

    - -
    -
    - -

    ◆ DMA_SxFCR_DMDIS_Pos

    - -
    -
    - - - - -
    #define DMA_SxFCR_DMDIS_Pos   (2U)
    -
    - -
    -
    - -

    ◆ DMA_SxFCR_DMDIS_Msk

    - -
    -
    - - - - -
    #define DMA_SxFCR_DMDIS_Msk   (0x1UL << DMA_SxFCR_DMDIS_Pos)
    -
    -

    0x00000004

    - -
    -
    - -

    ◆ DMA_SxFCR_DMDIS

    - -
    -
    - - - - -
    #define DMA_SxFCR_DMDIS   DMA_SxFCR_DMDIS_Msk
    -
    - -
    -
    - -

    ◆ DMA_SxFCR_FTH_Pos

    - -
    -
    - - - - -
    #define DMA_SxFCR_FTH_Pos   (0U)
    -
    - -
    -
    - -

    ◆ DMA_SxFCR_FTH_Msk

    - -
    -
    - - - - -
    #define DMA_SxFCR_FTH_Msk   (0x3UL << DMA_SxFCR_FTH_Pos)
    -
    -

    0x00000003

    - -
    -
    - -

    ◆ DMA_SxFCR_FTH

    - -
    -
    - - - - -
    #define DMA_SxFCR_FTH   DMA_SxFCR_FTH_Msk
    -
    - -
    -
    - -

    ◆ DMA_SxFCR_FTH_0

    - -
    -
    - - - - -
    #define DMA_SxFCR_FTH_0   (0x1UL << DMA_SxFCR_FTH_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ DMA_SxFCR_FTH_1

    - -
    -
    - - - - -
    #define DMA_SxFCR_FTH_1   (0x2UL << DMA_SxFCR_FTH_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ DMA_LISR_TCIF3_Pos

    - -
    -
    - - - - -
    #define DMA_LISR_TCIF3_Pos   (27U)
    -
    - -
    -
    - -

    ◆ DMA_LISR_TCIF3_Msk

    - -
    -
    - - - - -
    #define DMA_LISR_TCIF3_Msk   (0x1UL << DMA_LISR_TCIF3_Pos)
    -
    -

    0x08000000

    - -
    -
    - -

    ◆ DMA_LISR_TCIF3

    - -
    -
    - - - - -
    #define DMA_LISR_TCIF3   DMA_LISR_TCIF3_Msk
    -
    - -
    -
    - -

    ◆ DMA_LISR_HTIF3_Pos

    - -
    -
    - - - - -
    #define DMA_LISR_HTIF3_Pos   (26U)
    -
    - -
    -
    - -

    ◆ DMA_LISR_HTIF3_Msk

    - -
    -
    - - - - -
    #define DMA_LISR_HTIF3_Msk   (0x1UL << DMA_LISR_HTIF3_Pos)
    -
    -

    0x04000000

    - -
    -
    - -

    ◆ DMA_LISR_HTIF3

    - -
    -
    - - - - -
    #define DMA_LISR_HTIF3   DMA_LISR_HTIF3_Msk
    -
    - -
    -
    - -

    ◆ DMA_LISR_TEIF3_Pos

    - -
    -
    - - - - -
    #define DMA_LISR_TEIF3_Pos   (25U)
    -
    - -
    -
    - -

    ◆ DMA_LISR_TEIF3_Msk

    - -
    -
    - - - - -
    #define DMA_LISR_TEIF3_Msk   (0x1UL << DMA_LISR_TEIF3_Pos)
    -
    -

    0x02000000

    - -
    -
    - -

    ◆ DMA_LISR_TEIF3

    - -
    -
    - - - - -
    #define DMA_LISR_TEIF3   DMA_LISR_TEIF3_Msk
    -
    - -
    -
    - -

    ◆ DMA_LISR_DMEIF3_Pos

    - -
    -
    - - - - -
    #define DMA_LISR_DMEIF3_Pos   (24U)
    -
    - -
    -
    - -

    ◆ DMA_LISR_DMEIF3_Msk

    - -
    -
    - - - - -
    #define DMA_LISR_DMEIF3_Msk   (0x1UL << DMA_LISR_DMEIF3_Pos)
    -
    -

    0x01000000

    - -
    -
    - -

    ◆ DMA_LISR_DMEIF3

    - -
    -
    - - - - -
    #define DMA_LISR_DMEIF3   DMA_LISR_DMEIF3_Msk
    -
    - -
    -
    - -

    ◆ DMA_LISR_FEIF3_Pos

    - -
    -
    - - - - -
    #define DMA_LISR_FEIF3_Pos   (22U)
    -
    - -
    -
    - -

    ◆ DMA_LISR_FEIF3_Msk

    - -
    -
    - - - - -
    #define DMA_LISR_FEIF3_Msk   (0x1UL << DMA_LISR_FEIF3_Pos)
    -
    -

    0x00400000

    - -
    -
    - -

    ◆ DMA_LISR_FEIF3

    - -
    -
    - - - - -
    #define DMA_LISR_FEIF3   DMA_LISR_FEIF3_Msk
    -
    - -
    -
    - -

    ◆ DMA_LISR_TCIF2_Pos

    - -
    -
    - - - - -
    #define DMA_LISR_TCIF2_Pos   (21U)
    -
    - -
    -
    - -

    ◆ DMA_LISR_TCIF2_Msk

    - -
    -
    - - - - -
    #define DMA_LISR_TCIF2_Msk   (0x1UL << DMA_LISR_TCIF2_Pos)
    -
    -

    0x00200000

    - -
    -
    - -

    ◆ DMA_LISR_TCIF2

    - -
    -
    - - - - -
    #define DMA_LISR_TCIF2   DMA_LISR_TCIF2_Msk
    -
    - -
    -
    - -

    ◆ DMA_LISR_HTIF2_Pos

    - -
    -
    - - - - -
    #define DMA_LISR_HTIF2_Pos   (20U)
    -
    - -
    -
    - -

    ◆ DMA_LISR_HTIF2_Msk

    - -
    -
    - - - - -
    #define DMA_LISR_HTIF2_Msk   (0x1UL << DMA_LISR_HTIF2_Pos)
    -
    -

    0x00100000

    - -
    -
    - -

    ◆ DMA_LISR_HTIF2

    - -
    -
    - - - - -
    #define DMA_LISR_HTIF2   DMA_LISR_HTIF2_Msk
    -
    - -
    -
    - -

    ◆ DMA_LISR_TEIF2_Pos

    - -
    -
    - - - - -
    #define DMA_LISR_TEIF2_Pos   (19U)
    -
    - -
    -
    - -

    ◆ DMA_LISR_TEIF2_Msk

    - -
    -
    - - - - -
    #define DMA_LISR_TEIF2_Msk   (0x1UL << DMA_LISR_TEIF2_Pos)
    -
    -

    0x00080000

    - -
    -
    - -

    ◆ DMA_LISR_TEIF2

    - -
    -
    - - - - -
    #define DMA_LISR_TEIF2   DMA_LISR_TEIF2_Msk
    -
    - -
    -
    - -

    ◆ DMA_LISR_DMEIF2_Pos

    - -
    -
    - - - - -
    #define DMA_LISR_DMEIF2_Pos   (18U)
    -
    - -
    -
    - -

    ◆ DMA_LISR_DMEIF2_Msk

    - -
    -
    - - - - -
    #define DMA_LISR_DMEIF2_Msk   (0x1UL << DMA_LISR_DMEIF2_Pos)
    -
    -

    0x00040000

    - -
    -
    - -

    ◆ DMA_LISR_DMEIF2

    - -
    -
    - - - - -
    #define DMA_LISR_DMEIF2   DMA_LISR_DMEIF2_Msk
    -
    - -
    -
    - -

    ◆ DMA_LISR_FEIF2_Pos

    - -
    -
    - - - - -
    #define DMA_LISR_FEIF2_Pos   (16U)
    -
    - -
    -
    - -

    ◆ DMA_LISR_FEIF2_Msk

    - -
    -
    - - - - -
    #define DMA_LISR_FEIF2_Msk   (0x1UL << DMA_LISR_FEIF2_Pos)
    -
    -

    0x00010000

    - -
    -
    - -

    ◆ DMA_LISR_FEIF2

    - -
    -
    - - - - -
    #define DMA_LISR_FEIF2   DMA_LISR_FEIF2_Msk
    -
    - -
    -
    - -

    ◆ DMA_LISR_TCIF1_Pos

    - -
    -
    - - - - -
    #define DMA_LISR_TCIF1_Pos   (11U)
    -
    - -
    -
    - -

    ◆ DMA_LISR_TCIF1_Msk

    - -
    -
    - - - - -
    #define DMA_LISR_TCIF1_Msk   (0x1UL << DMA_LISR_TCIF1_Pos)
    -
    -

    0x00000800

    - -
    -
    - -

    ◆ DMA_LISR_TCIF1

    - -
    -
    - - - - -
    #define DMA_LISR_TCIF1   DMA_LISR_TCIF1_Msk
    -
    - -
    -
    - -

    ◆ DMA_LISR_HTIF1_Pos

    - -
    -
    - - - - -
    #define DMA_LISR_HTIF1_Pos   (10U)
    -
    - -
    -
    - -

    ◆ DMA_LISR_HTIF1_Msk

    - -
    -
    - - - - -
    #define DMA_LISR_HTIF1_Msk   (0x1UL << DMA_LISR_HTIF1_Pos)
    -
    -

    0x00000400

    - -
    -
    - -

    ◆ DMA_LISR_HTIF1

    - -
    -
    - - - - -
    #define DMA_LISR_HTIF1   DMA_LISR_HTIF1_Msk
    -
    - -
    -
    - -

    ◆ DMA_LISR_TEIF1_Pos

    - -
    -
    - - - - -
    #define DMA_LISR_TEIF1_Pos   (9U)
    -
    - -
    -
    - -

    ◆ DMA_LISR_TEIF1_Msk

    - -
    -
    - - - - -
    #define DMA_LISR_TEIF1_Msk   (0x1UL << DMA_LISR_TEIF1_Pos)
    -
    -

    0x00000200

    - -
    -
    - -

    ◆ DMA_LISR_TEIF1

    - -
    -
    - - - - -
    #define DMA_LISR_TEIF1   DMA_LISR_TEIF1_Msk
    -
    - -
    -
    - -

    ◆ DMA_LISR_DMEIF1_Pos

    - -
    -
    - - - - -
    #define DMA_LISR_DMEIF1_Pos   (8U)
    -
    - -
    -
    - -

    ◆ DMA_LISR_DMEIF1_Msk

    - -
    -
    - - - - -
    #define DMA_LISR_DMEIF1_Msk   (0x1UL << DMA_LISR_DMEIF1_Pos)
    -
    -

    0x00000100

    - -
    -
    - -

    ◆ DMA_LISR_DMEIF1

    - -
    -
    - - - - -
    #define DMA_LISR_DMEIF1   DMA_LISR_DMEIF1_Msk
    -
    - -
    -
    - -

    ◆ DMA_LISR_FEIF1_Pos

    - -
    -
    - - - - -
    #define DMA_LISR_FEIF1_Pos   (6U)
    -
    - -
    -
    - -

    ◆ DMA_LISR_FEIF1_Msk

    - -
    -
    - - - - -
    #define DMA_LISR_FEIF1_Msk   (0x1UL << DMA_LISR_FEIF1_Pos)
    -
    -

    0x00000040

    - -
    -
    - -

    ◆ DMA_LISR_FEIF1

    - -
    -
    - - - - -
    #define DMA_LISR_FEIF1   DMA_LISR_FEIF1_Msk
    -
    - -
    -
    - -

    ◆ DMA_LISR_TCIF0_Pos

    - -
    -
    - - - - -
    #define DMA_LISR_TCIF0_Pos   (5U)
    -
    - -
    -
    - -

    ◆ DMA_LISR_TCIF0_Msk

    - -
    -
    - - - - -
    #define DMA_LISR_TCIF0_Msk   (0x1UL << DMA_LISR_TCIF0_Pos)
    -
    -

    0x00000020

    - -
    -
    - -

    ◆ DMA_LISR_TCIF0

    - -
    -
    - - - - -
    #define DMA_LISR_TCIF0   DMA_LISR_TCIF0_Msk
    -
    - -
    -
    - -

    ◆ DMA_LISR_HTIF0_Pos

    - -
    -
    - - - - -
    #define DMA_LISR_HTIF0_Pos   (4U)
    -
    - -
    -
    - -

    ◆ DMA_LISR_HTIF0_Msk

    - -
    -
    - - - - -
    #define DMA_LISR_HTIF0_Msk   (0x1UL << DMA_LISR_HTIF0_Pos)
    -
    -

    0x00000010

    - -
    -
    - -

    ◆ DMA_LISR_HTIF0

    - -
    -
    - - - - -
    #define DMA_LISR_HTIF0   DMA_LISR_HTIF0_Msk
    -
    - -
    -
    - -

    ◆ DMA_LISR_TEIF0_Pos

    - -
    -
    - - - - -
    #define DMA_LISR_TEIF0_Pos   (3U)
    -
    - -
    -
    - -

    ◆ DMA_LISR_TEIF0_Msk

    - -
    -
    - - - - -
    #define DMA_LISR_TEIF0_Msk   (0x1UL << DMA_LISR_TEIF0_Pos)
    -
    -

    0x00000008

    - -
    -
    - -

    ◆ DMA_LISR_TEIF0

    - -
    -
    - - - - -
    #define DMA_LISR_TEIF0   DMA_LISR_TEIF0_Msk
    -
    - -
    -
    - -

    ◆ DMA_LISR_DMEIF0_Pos

    - -
    -
    - - - - -
    #define DMA_LISR_DMEIF0_Pos   (2U)
    -
    - -
    -
    - -

    ◆ DMA_LISR_DMEIF0_Msk

    - -
    -
    - - - - -
    #define DMA_LISR_DMEIF0_Msk   (0x1UL << DMA_LISR_DMEIF0_Pos)
    -
    -

    0x00000004

    - -
    -
    - -

    ◆ DMA_LISR_DMEIF0

    - -
    -
    - - - - -
    #define DMA_LISR_DMEIF0   DMA_LISR_DMEIF0_Msk
    -
    - -
    -
    - -

    ◆ DMA_LISR_FEIF0_Pos

    - -
    -
    - - - - -
    #define DMA_LISR_FEIF0_Pos   (0U)
    -
    - -
    -
    - -

    ◆ DMA_LISR_FEIF0_Msk

    - -
    -
    - - - - -
    #define DMA_LISR_FEIF0_Msk   (0x1UL << DMA_LISR_FEIF0_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ DMA_LISR_FEIF0

    - -
    -
    - - - - -
    #define DMA_LISR_FEIF0   DMA_LISR_FEIF0_Msk
    -
    - -
    -
    - -

    ◆ DMA_HISR_TCIF7_Pos

    - -
    -
    - - - - -
    #define DMA_HISR_TCIF7_Pos   (27U)
    -
    - -
    -
    - -

    ◆ DMA_HISR_TCIF7_Msk

    - -
    -
    - - - - -
    #define DMA_HISR_TCIF7_Msk   (0x1UL << DMA_HISR_TCIF7_Pos)
    -
    -

    0x08000000

    - -
    -
    - -

    ◆ DMA_HISR_TCIF7

    - -
    -
    - - - - -
    #define DMA_HISR_TCIF7   DMA_HISR_TCIF7_Msk
    -
    - -
    -
    - -

    ◆ DMA_HISR_HTIF7_Pos

    - -
    -
    - - - - -
    #define DMA_HISR_HTIF7_Pos   (26U)
    -
    - -
    -
    - -

    ◆ DMA_HISR_HTIF7_Msk

    - -
    -
    - - - - -
    #define DMA_HISR_HTIF7_Msk   (0x1UL << DMA_HISR_HTIF7_Pos)
    -
    -

    0x04000000

    - -
    -
    - -

    ◆ DMA_HISR_HTIF7

    - -
    -
    - - - - -
    #define DMA_HISR_HTIF7   DMA_HISR_HTIF7_Msk
    -
    - -
    -
    - -

    ◆ DMA_HISR_TEIF7_Pos

    - -
    -
    - - - - -
    #define DMA_HISR_TEIF7_Pos   (25U)
    -
    - -
    -
    - -

    ◆ DMA_HISR_TEIF7_Msk

    - -
    -
    - - - - -
    #define DMA_HISR_TEIF7_Msk   (0x1UL << DMA_HISR_TEIF7_Pos)
    -
    -

    0x02000000

    - -
    -
    - -

    ◆ DMA_HISR_TEIF7

    - -
    -
    - - - - -
    #define DMA_HISR_TEIF7   DMA_HISR_TEIF7_Msk
    -
    - -
    -
    - -

    ◆ DMA_HISR_DMEIF7_Pos

    - -
    -
    - - - - -
    #define DMA_HISR_DMEIF7_Pos   (24U)
    -
    - -
    -
    - -

    ◆ DMA_HISR_DMEIF7_Msk

    - -
    -
    - - - - -
    #define DMA_HISR_DMEIF7_Msk   (0x1UL << DMA_HISR_DMEIF7_Pos)
    -
    -

    0x01000000

    - -
    -
    - -

    ◆ DMA_HISR_DMEIF7

    - -
    -
    - - - - -
    #define DMA_HISR_DMEIF7   DMA_HISR_DMEIF7_Msk
    -
    - -
    -
    - -

    ◆ DMA_HISR_FEIF7_Pos

    - -
    -
    - - - - -
    #define DMA_HISR_FEIF7_Pos   (22U)
    -
    - -
    -
    - -

    ◆ DMA_HISR_FEIF7_Msk

    - -
    -
    - - - - -
    #define DMA_HISR_FEIF7_Msk   (0x1UL << DMA_HISR_FEIF7_Pos)
    -
    -

    0x00400000

    - -
    -
    - -

    ◆ DMA_HISR_FEIF7

    - -
    -
    - - - - -
    #define DMA_HISR_FEIF7   DMA_HISR_FEIF7_Msk
    -
    - -
    -
    - -

    ◆ DMA_HISR_TCIF6_Pos

    - -
    -
    - - - - -
    #define DMA_HISR_TCIF6_Pos   (21U)
    -
    - -
    -
    - -

    ◆ DMA_HISR_TCIF6_Msk

    - -
    -
    - - - - -
    #define DMA_HISR_TCIF6_Msk   (0x1UL << DMA_HISR_TCIF6_Pos)
    -
    -

    0x00200000

    - -
    -
    - -

    ◆ DMA_HISR_TCIF6

    - -
    -
    - - - - -
    #define DMA_HISR_TCIF6   DMA_HISR_TCIF6_Msk
    -
    - -
    -
    - -

    ◆ DMA_HISR_HTIF6_Pos

    - -
    -
    - - - - -
    #define DMA_HISR_HTIF6_Pos   (20U)
    -
    - -
    -
    - -

    ◆ DMA_HISR_HTIF6_Msk

    - -
    -
    - - - - -
    #define DMA_HISR_HTIF6_Msk   (0x1UL << DMA_HISR_HTIF6_Pos)
    -
    -

    0x00100000

    - -
    -
    - -

    ◆ DMA_HISR_HTIF6

    - -
    -
    - - - - -
    #define DMA_HISR_HTIF6   DMA_HISR_HTIF6_Msk
    -
    - -
    -
    - -

    ◆ DMA_HISR_TEIF6_Pos

    - -
    -
    - - - - -
    #define DMA_HISR_TEIF6_Pos   (19U)
    -
    - -
    -
    - -

    ◆ DMA_HISR_TEIF6_Msk

    - -
    -
    - - - - -
    #define DMA_HISR_TEIF6_Msk   (0x1UL << DMA_HISR_TEIF6_Pos)
    -
    -

    0x00080000

    - -
    -
    - -

    ◆ DMA_HISR_TEIF6

    - -
    -
    - - - - -
    #define DMA_HISR_TEIF6   DMA_HISR_TEIF6_Msk
    -
    - -
    -
    - -

    ◆ DMA_HISR_DMEIF6_Pos

    - -
    -
    - - - - -
    #define DMA_HISR_DMEIF6_Pos   (18U)
    -
    - -
    -
    - -

    ◆ DMA_HISR_DMEIF6_Msk

    - -
    -
    - - - - -
    #define DMA_HISR_DMEIF6_Msk   (0x1UL << DMA_HISR_DMEIF6_Pos)
    -
    -

    0x00040000

    - -
    -
    - -

    ◆ DMA_HISR_DMEIF6

    - -
    -
    - - - - -
    #define DMA_HISR_DMEIF6   DMA_HISR_DMEIF6_Msk
    -
    - -
    -
    - -

    ◆ DMA_HISR_FEIF6_Pos

    - -
    -
    - - - - -
    #define DMA_HISR_FEIF6_Pos   (16U)
    -
    - -
    -
    - -

    ◆ DMA_HISR_FEIF6_Msk

    - -
    -
    - - - - -
    #define DMA_HISR_FEIF6_Msk   (0x1UL << DMA_HISR_FEIF6_Pos)
    -
    -

    0x00010000

    - -
    -
    - -

    ◆ DMA_HISR_FEIF6

    - -
    -
    - - - - -
    #define DMA_HISR_FEIF6   DMA_HISR_FEIF6_Msk
    -
    - -
    -
    - -

    ◆ DMA_HISR_TCIF5_Pos

    - -
    -
    - - - - -
    #define DMA_HISR_TCIF5_Pos   (11U)
    -
    - -
    -
    - -

    ◆ DMA_HISR_TCIF5_Msk

    - -
    -
    - - - - -
    #define DMA_HISR_TCIF5_Msk   (0x1UL << DMA_HISR_TCIF5_Pos)
    -
    -

    0x00000800

    - -
    -
    - -

    ◆ DMA_HISR_TCIF5

    - -
    -
    - - - - -
    #define DMA_HISR_TCIF5   DMA_HISR_TCIF5_Msk
    -
    - -
    -
    - -

    ◆ DMA_HISR_HTIF5_Pos

    - -
    -
    - - - - -
    #define DMA_HISR_HTIF5_Pos   (10U)
    -
    - -
    -
    - -

    ◆ DMA_HISR_HTIF5_Msk

    - -
    -
    - - - - -
    #define DMA_HISR_HTIF5_Msk   (0x1UL << DMA_HISR_HTIF5_Pos)
    -
    -

    0x00000400

    - -
    -
    - -

    ◆ DMA_HISR_HTIF5

    - -
    -
    - - - - -
    #define DMA_HISR_HTIF5   DMA_HISR_HTIF5_Msk
    -
    - -
    -
    - -

    ◆ DMA_HISR_TEIF5_Pos

    - -
    -
    - - - - -
    #define DMA_HISR_TEIF5_Pos   (9U)
    -
    - -
    -
    - -

    ◆ DMA_HISR_TEIF5_Msk

    - -
    -
    - - - - -
    #define DMA_HISR_TEIF5_Msk   (0x1UL << DMA_HISR_TEIF5_Pos)
    -
    -

    0x00000200

    - -
    -
    - -

    ◆ DMA_HISR_TEIF5

    - -
    -
    - - - - -
    #define DMA_HISR_TEIF5   DMA_HISR_TEIF5_Msk
    -
    - -
    -
    - -

    ◆ DMA_HISR_DMEIF5_Pos

    - -
    -
    - - - - -
    #define DMA_HISR_DMEIF5_Pos   (8U)
    -
    - -
    -
    - -

    ◆ DMA_HISR_DMEIF5_Msk

    - -
    -
    - - - - -
    #define DMA_HISR_DMEIF5_Msk   (0x1UL << DMA_HISR_DMEIF5_Pos)
    -
    -

    0x00000100

    - -
    -
    - -

    ◆ DMA_HISR_DMEIF5

    - -
    -
    - - - - -
    #define DMA_HISR_DMEIF5   DMA_HISR_DMEIF5_Msk
    -
    - -
    -
    - -

    ◆ DMA_HISR_FEIF5_Pos

    - -
    -
    - - - - -
    #define DMA_HISR_FEIF5_Pos   (6U)
    -
    - -
    -
    - -

    ◆ DMA_HISR_FEIF5_Msk

    - -
    -
    - - - - -
    #define DMA_HISR_FEIF5_Msk   (0x1UL << DMA_HISR_FEIF5_Pos)
    -
    -

    0x00000040

    - -
    -
    - -

    ◆ DMA_HISR_FEIF5

    - -
    -
    - - - - -
    #define DMA_HISR_FEIF5   DMA_HISR_FEIF5_Msk
    -
    - -
    -
    - -

    ◆ DMA_HISR_TCIF4_Pos

    - -
    -
    - - - - -
    #define DMA_HISR_TCIF4_Pos   (5U)
    -
    - -
    -
    - -

    ◆ DMA_HISR_TCIF4_Msk

    - -
    -
    - - - - -
    #define DMA_HISR_TCIF4_Msk   (0x1UL << DMA_HISR_TCIF4_Pos)
    -
    -

    0x00000020

    - -
    -
    - -

    ◆ DMA_HISR_TCIF4

    - -
    -
    - - - - -
    #define DMA_HISR_TCIF4   DMA_HISR_TCIF4_Msk
    -
    - -
    -
    - -

    ◆ DMA_HISR_HTIF4_Pos

    - -
    -
    - - - - -
    #define DMA_HISR_HTIF4_Pos   (4U)
    -
    - -
    -
    - -

    ◆ DMA_HISR_HTIF4_Msk

    - -
    -
    - - - - -
    #define DMA_HISR_HTIF4_Msk   (0x1UL << DMA_HISR_HTIF4_Pos)
    -
    -

    0x00000010

    - -
    -
    - -

    ◆ DMA_HISR_HTIF4

    - -
    -
    - - - - -
    #define DMA_HISR_HTIF4   DMA_HISR_HTIF4_Msk
    -
    - -
    -
    - -

    ◆ DMA_HISR_TEIF4_Pos

    - -
    -
    - - - - -
    #define DMA_HISR_TEIF4_Pos   (3U)
    -
    - -
    -
    - -

    ◆ DMA_HISR_TEIF4_Msk

    - -
    -
    - - - - -
    #define DMA_HISR_TEIF4_Msk   (0x1UL << DMA_HISR_TEIF4_Pos)
    -
    -

    0x00000008

    - -
    -
    - -

    ◆ DMA_HISR_TEIF4

    - -
    -
    - - - - -
    #define DMA_HISR_TEIF4   DMA_HISR_TEIF4_Msk
    -
    - -
    -
    - -

    ◆ DMA_HISR_DMEIF4_Pos

    - -
    -
    - - - - -
    #define DMA_HISR_DMEIF4_Pos   (2U)
    -
    - -
    -
    - -

    ◆ DMA_HISR_DMEIF4_Msk

    - -
    -
    - - - - -
    #define DMA_HISR_DMEIF4_Msk   (0x1UL << DMA_HISR_DMEIF4_Pos)
    -
    -

    0x00000004

    - -
    -
    - -

    ◆ DMA_HISR_DMEIF4

    - -
    -
    - - - - -
    #define DMA_HISR_DMEIF4   DMA_HISR_DMEIF4_Msk
    -
    - -
    -
    - -

    ◆ DMA_HISR_FEIF4_Pos

    - -
    -
    - - - - -
    #define DMA_HISR_FEIF4_Pos   (0U)
    -
    - -
    -
    - -

    ◆ DMA_HISR_FEIF4_Msk

    - -
    -
    - - - - -
    #define DMA_HISR_FEIF4_Msk   (0x1UL << DMA_HISR_FEIF4_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ DMA_HISR_FEIF4

    - -
    -
    - - - - -
    #define DMA_HISR_FEIF4   DMA_HISR_FEIF4_Msk
    -
    - -
    -
    - -

    ◆ DMA_LIFCR_CTCIF3_Pos

    - -
    -
    - - - - -
    #define DMA_LIFCR_CTCIF3_Pos   (27U)
    -
    - -
    -
    - -

    ◆ DMA_LIFCR_CTCIF3_Msk

    - -
    -
    - - - - -
    #define DMA_LIFCR_CTCIF3_Msk   (0x1UL << DMA_LIFCR_CTCIF3_Pos)
    -
    -

    0x08000000

    - -
    -
    - -

    ◆ DMA_LIFCR_CTCIF3

    - -
    -
    - - - - -
    #define DMA_LIFCR_CTCIF3   DMA_LIFCR_CTCIF3_Msk
    -
    - -
    -
    - -

    ◆ DMA_LIFCR_CHTIF3_Pos

    - -
    -
    - - - - -
    #define DMA_LIFCR_CHTIF3_Pos   (26U)
    -
    - -
    -
    - -

    ◆ DMA_LIFCR_CHTIF3_Msk

    - -
    -
    - - - - -
    #define DMA_LIFCR_CHTIF3_Msk   (0x1UL << DMA_LIFCR_CHTIF3_Pos)
    -
    -

    0x04000000

    - -
    -
    - -

    ◆ DMA_LIFCR_CHTIF3

    - -
    -
    - - - - -
    #define DMA_LIFCR_CHTIF3   DMA_LIFCR_CHTIF3_Msk
    -
    - -
    -
    - -

    ◆ DMA_LIFCR_CTEIF3_Pos

    - -
    -
    - - - - -
    #define DMA_LIFCR_CTEIF3_Pos   (25U)
    -
    - -
    -
    - -

    ◆ DMA_LIFCR_CTEIF3_Msk

    - -
    -
    - - - - -
    #define DMA_LIFCR_CTEIF3_Msk   (0x1UL << DMA_LIFCR_CTEIF3_Pos)
    -
    -

    0x02000000

    - -
    -
    - -

    ◆ DMA_LIFCR_CTEIF3

    - -
    -
    - - - - -
    #define DMA_LIFCR_CTEIF3   DMA_LIFCR_CTEIF3_Msk
    -
    - -
    -
    - -

    ◆ DMA_LIFCR_CDMEIF3_Pos

    - -
    -
    - - - - -
    #define DMA_LIFCR_CDMEIF3_Pos   (24U)
    -
    - -
    -
    - -

    ◆ DMA_LIFCR_CDMEIF3_Msk

    - -
    -
    - - - - -
    #define DMA_LIFCR_CDMEIF3_Msk   (0x1UL << DMA_LIFCR_CDMEIF3_Pos)
    -
    -

    0x01000000

    - -
    -
    - -

    ◆ DMA_LIFCR_CDMEIF3

    - -
    -
    - - - - -
    #define DMA_LIFCR_CDMEIF3   DMA_LIFCR_CDMEIF3_Msk
    -
    - -
    -
    - -

    ◆ DMA_LIFCR_CFEIF3_Pos

    - -
    -
    - - - - -
    #define DMA_LIFCR_CFEIF3_Pos   (22U)
    -
    - -
    -
    - -

    ◆ DMA_LIFCR_CFEIF3_Msk

    - -
    -
    - - - - -
    #define DMA_LIFCR_CFEIF3_Msk   (0x1UL << DMA_LIFCR_CFEIF3_Pos)
    -
    -

    0x00400000

    - -
    -
    - -

    ◆ DMA_LIFCR_CFEIF3

    - -
    -
    - - - - -
    #define DMA_LIFCR_CFEIF3   DMA_LIFCR_CFEIF3_Msk
    -
    - -
    -
    - -

    ◆ DMA_LIFCR_CTCIF2_Pos

    - -
    -
    - - - - -
    #define DMA_LIFCR_CTCIF2_Pos   (21U)
    -
    - -
    -
    - -

    ◆ DMA_LIFCR_CTCIF2_Msk

    - -
    -
    - - - - -
    #define DMA_LIFCR_CTCIF2_Msk   (0x1UL << DMA_LIFCR_CTCIF2_Pos)
    -
    -

    0x00200000

    - -
    -
    - -

    ◆ DMA_LIFCR_CTCIF2

    - -
    -
    - - - - -
    #define DMA_LIFCR_CTCIF2   DMA_LIFCR_CTCIF2_Msk
    -
    - -
    -
    - -

    ◆ DMA_LIFCR_CHTIF2_Pos

    - -
    -
    - - - - -
    #define DMA_LIFCR_CHTIF2_Pos   (20U)
    -
    - -
    -
    - -

    ◆ DMA_LIFCR_CHTIF2_Msk

    - -
    -
    - - - - -
    #define DMA_LIFCR_CHTIF2_Msk   (0x1UL << DMA_LIFCR_CHTIF2_Pos)
    -
    -

    0x00100000

    - -
    -
    - -

    ◆ DMA_LIFCR_CHTIF2

    - -
    -
    - - - - -
    #define DMA_LIFCR_CHTIF2   DMA_LIFCR_CHTIF2_Msk
    -
    - -
    -
    - -

    ◆ DMA_LIFCR_CTEIF2_Pos

    - -
    -
    - - - - -
    #define DMA_LIFCR_CTEIF2_Pos   (19U)
    -
    - -
    -
    - -

    ◆ DMA_LIFCR_CTEIF2_Msk

    - -
    -
    - - - - -
    #define DMA_LIFCR_CTEIF2_Msk   (0x1UL << DMA_LIFCR_CTEIF2_Pos)
    -
    -

    0x00080000

    - -
    -
    - -

    ◆ DMA_LIFCR_CTEIF2

    - -
    -
    - - - - -
    #define DMA_LIFCR_CTEIF2   DMA_LIFCR_CTEIF2_Msk
    -
    - -
    -
    - -

    ◆ DMA_LIFCR_CDMEIF2_Pos

    - -
    -
    - - - - -
    #define DMA_LIFCR_CDMEIF2_Pos   (18U)
    -
    - -
    -
    - -

    ◆ DMA_LIFCR_CDMEIF2_Msk

    - -
    -
    - - - - -
    #define DMA_LIFCR_CDMEIF2_Msk   (0x1UL << DMA_LIFCR_CDMEIF2_Pos)
    -
    -

    0x00040000

    - -
    -
    - -

    ◆ DMA_LIFCR_CDMEIF2

    - -
    -
    - - - - -
    #define DMA_LIFCR_CDMEIF2   DMA_LIFCR_CDMEIF2_Msk
    -
    - -
    -
    - -

    ◆ DMA_LIFCR_CFEIF2_Pos

    - -
    -
    - - - - -
    #define DMA_LIFCR_CFEIF2_Pos   (16U)
    -
    - -
    -
    - -

    ◆ DMA_LIFCR_CFEIF2_Msk

    - -
    -
    - - - - -
    #define DMA_LIFCR_CFEIF2_Msk   (0x1UL << DMA_LIFCR_CFEIF2_Pos)
    -
    -

    0x00010000

    - -
    -
    - -

    ◆ DMA_LIFCR_CFEIF2

    - -
    -
    - - - - -
    #define DMA_LIFCR_CFEIF2   DMA_LIFCR_CFEIF2_Msk
    -
    - -
    -
    - -

    ◆ DMA_LIFCR_CTCIF1_Pos

    - -
    -
    - - - - -
    #define DMA_LIFCR_CTCIF1_Pos   (11U)
    -
    - -
    -
    - -

    ◆ DMA_LIFCR_CTCIF1_Msk

    - -
    -
    - - - - -
    #define DMA_LIFCR_CTCIF1_Msk   (0x1UL << DMA_LIFCR_CTCIF1_Pos)
    -
    -

    0x00000800

    - -
    -
    - -

    ◆ DMA_LIFCR_CTCIF1

    - -
    -
    - - - - -
    #define DMA_LIFCR_CTCIF1   DMA_LIFCR_CTCIF1_Msk
    -
    - -
    -
    - -

    ◆ DMA_LIFCR_CHTIF1_Pos

    - -
    -
    - - - - -
    #define DMA_LIFCR_CHTIF1_Pos   (10U)
    -
    - -
    -
    - -

    ◆ DMA_LIFCR_CHTIF1_Msk

    - -
    -
    - - - - -
    #define DMA_LIFCR_CHTIF1_Msk   (0x1UL << DMA_LIFCR_CHTIF1_Pos)
    -
    -

    0x00000400

    - -
    -
    - -

    ◆ DMA_LIFCR_CHTIF1

    - -
    -
    - - - - -
    #define DMA_LIFCR_CHTIF1   DMA_LIFCR_CHTIF1_Msk
    -
    - -
    -
    - -

    ◆ DMA_LIFCR_CTEIF1_Pos

    - -
    -
    - - - - -
    #define DMA_LIFCR_CTEIF1_Pos   (9U)
    -
    - -
    -
    - -

    ◆ DMA_LIFCR_CTEIF1_Msk

    - -
    -
    - - - - -
    #define DMA_LIFCR_CTEIF1_Msk   (0x1UL << DMA_LIFCR_CTEIF1_Pos)
    -
    -

    0x00000200

    - -
    -
    - -

    ◆ DMA_LIFCR_CTEIF1

    - -
    -
    - - - - -
    #define DMA_LIFCR_CTEIF1   DMA_LIFCR_CTEIF1_Msk
    -
    - -
    -
    - -

    ◆ DMA_LIFCR_CDMEIF1_Pos

    - -
    -
    - - - - -
    #define DMA_LIFCR_CDMEIF1_Pos   (8U)
    -
    - -
    -
    - -

    ◆ DMA_LIFCR_CDMEIF1_Msk

    - -
    -
    - - - - -
    #define DMA_LIFCR_CDMEIF1_Msk   (0x1UL << DMA_LIFCR_CDMEIF1_Pos)
    -
    -

    0x00000100

    - -
    -
    - -

    ◆ DMA_LIFCR_CDMEIF1

    - -
    -
    - - - - -
    #define DMA_LIFCR_CDMEIF1   DMA_LIFCR_CDMEIF1_Msk
    -
    - -
    -
    - -

    ◆ DMA_LIFCR_CFEIF1_Pos

    - -
    -
    - - - - -
    #define DMA_LIFCR_CFEIF1_Pos   (6U)
    -
    - -
    -
    - -

    ◆ DMA_LIFCR_CFEIF1_Msk

    - -
    -
    - - - - -
    #define DMA_LIFCR_CFEIF1_Msk   (0x1UL << DMA_LIFCR_CFEIF1_Pos)
    -
    -

    0x00000040

    - -
    -
    - -

    ◆ DMA_LIFCR_CFEIF1

    - -
    -
    - - - - -
    #define DMA_LIFCR_CFEIF1   DMA_LIFCR_CFEIF1_Msk
    -
    - -
    -
    - -

    ◆ DMA_LIFCR_CTCIF0_Pos

    - -
    -
    - - - - -
    #define DMA_LIFCR_CTCIF0_Pos   (5U)
    -
    - -
    -
    - -

    ◆ DMA_LIFCR_CTCIF0_Msk

    - -
    -
    - - - - -
    #define DMA_LIFCR_CTCIF0_Msk   (0x1UL << DMA_LIFCR_CTCIF0_Pos)
    -
    -

    0x00000020

    - -
    -
    - -

    ◆ DMA_LIFCR_CTCIF0

    - -
    -
    - - - - -
    #define DMA_LIFCR_CTCIF0   DMA_LIFCR_CTCIF0_Msk
    -
    - -
    -
    - -

    ◆ DMA_LIFCR_CHTIF0_Pos

    - -
    -
    - - - - -
    #define DMA_LIFCR_CHTIF0_Pos   (4U)
    -
    - -
    -
    - -

    ◆ DMA_LIFCR_CHTIF0_Msk

    - -
    -
    - - - - -
    #define DMA_LIFCR_CHTIF0_Msk   (0x1UL << DMA_LIFCR_CHTIF0_Pos)
    -
    -

    0x00000010

    - -
    -
    - -

    ◆ DMA_LIFCR_CHTIF0

    - -
    -
    - - - - -
    #define DMA_LIFCR_CHTIF0   DMA_LIFCR_CHTIF0_Msk
    -
    - -
    -
    - -

    ◆ DMA_LIFCR_CTEIF0_Pos

    - -
    -
    - - - - -
    #define DMA_LIFCR_CTEIF0_Pos   (3U)
    -
    - -
    -
    - -

    ◆ DMA_LIFCR_CTEIF0_Msk

    - -
    -
    - - - - -
    #define DMA_LIFCR_CTEIF0_Msk   (0x1UL << DMA_LIFCR_CTEIF0_Pos)
    -
    -

    0x00000008

    - -
    -
    - -

    ◆ DMA_LIFCR_CTEIF0

    - -
    -
    - - - - -
    #define DMA_LIFCR_CTEIF0   DMA_LIFCR_CTEIF0_Msk
    -
    - -
    -
    - -

    ◆ DMA_LIFCR_CDMEIF0_Pos

    - -
    -
    - - - - -
    #define DMA_LIFCR_CDMEIF0_Pos   (2U)
    -
    - -
    -
    - -

    ◆ DMA_LIFCR_CDMEIF0_Msk

    - -
    -
    - - - - -
    #define DMA_LIFCR_CDMEIF0_Msk   (0x1UL << DMA_LIFCR_CDMEIF0_Pos)
    -
    -

    0x00000004

    - -
    -
    - -

    ◆ DMA_LIFCR_CDMEIF0

    - -
    -
    - - - - -
    #define DMA_LIFCR_CDMEIF0   DMA_LIFCR_CDMEIF0_Msk
    -
    - -
    -
    - -

    ◆ DMA_LIFCR_CFEIF0_Pos

    - -
    -
    - - - - -
    #define DMA_LIFCR_CFEIF0_Pos   (0U)
    -
    - -
    -
    - -

    ◆ DMA_LIFCR_CFEIF0_Msk

    - -
    -
    - - - - -
    #define DMA_LIFCR_CFEIF0_Msk   (0x1UL << DMA_LIFCR_CFEIF0_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ DMA_LIFCR_CFEIF0

    - -
    -
    - - - - -
    #define DMA_LIFCR_CFEIF0   DMA_LIFCR_CFEIF0_Msk
    -
    - -
    -
    - -

    ◆ DMA_HIFCR_CTCIF7_Pos

    - -
    -
    - - - - -
    #define DMA_HIFCR_CTCIF7_Pos   (27U)
    -
    - -
    -
    - -

    ◆ DMA_HIFCR_CTCIF7_Msk

    - -
    -
    - - - - -
    #define DMA_HIFCR_CTCIF7_Msk   (0x1UL << DMA_HIFCR_CTCIF7_Pos)
    -
    -

    0x08000000

    - -
    -
    - -

    ◆ DMA_HIFCR_CTCIF7

    - -
    -
    - - - - -
    #define DMA_HIFCR_CTCIF7   DMA_HIFCR_CTCIF7_Msk
    -
    - -
    -
    - -

    ◆ DMA_HIFCR_CHTIF7_Pos

    - -
    -
    - - - - -
    #define DMA_HIFCR_CHTIF7_Pos   (26U)
    -
    - -
    -
    - -

    ◆ DMA_HIFCR_CHTIF7_Msk

    - -
    -
    - - - - -
    #define DMA_HIFCR_CHTIF7_Msk   (0x1UL << DMA_HIFCR_CHTIF7_Pos)
    -
    -

    0x04000000

    - -
    -
    - -

    ◆ DMA_HIFCR_CHTIF7

    - -
    -
    - - - - -
    #define DMA_HIFCR_CHTIF7   DMA_HIFCR_CHTIF7_Msk
    -
    - -
    -
    - -

    ◆ DMA_HIFCR_CTEIF7_Pos

    - -
    -
    - - - - -
    #define DMA_HIFCR_CTEIF7_Pos   (25U)
    -
    - -
    -
    - -

    ◆ DMA_HIFCR_CTEIF7_Msk

    - -
    -
    - - - - -
    #define DMA_HIFCR_CTEIF7_Msk   (0x1UL << DMA_HIFCR_CTEIF7_Pos)
    -
    -

    0x02000000

    - -
    -
    - -

    ◆ DMA_HIFCR_CTEIF7

    - -
    -
    - - - - -
    #define DMA_HIFCR_CTEIF7   DMA_HIFCR_CTEIF7_Msk
    -
    - -
    -
    - -

    ◆ DMA_HIFCR_CDMEIF7_Pos

    - -
    -
    - - - - -
    #define DMA_HIFCR_CDMEIF7_Pos   (24U)
    -
    - -
    -
    - -

    ◆ DMA_HIFCR_CDMEIF7_Msk

    - -
    -
    - - - - -
    #define DMA_HIFCR_CDMEIF7_Msk   (0x1UL << DMA_HIFCR_CDMEIF7_Pos)
    -
    -

    0x01000000

    - -
    -
    - -

    ◆ DMA_HIFCR_CDMEIF7

    - -
    -
    - - - - -
    #define DMA_HIFCR_CDMEIF7   DMA_HIFCR_CDMEIF7_Msk
    -
    - -
    -
    - -

    ◆ DMA_HIFCR_CFEIF7_Pos

    - -
    -
    - - - - -
    #define DMA_HIFCR_CFEIF7_Pos   (22U)
    -
    - -
    -
    - -

    ◆ DMA_HIFCR_CFEIF7_Msk

    - -
    -
    - - - - -
    #define DMA_HIFCR_CFEIF7_Msk   (0x1UL << DMA_HIFCR_CFEIF7_Pos)
    -
    -

    0x00400000

    - -
    -
    - -

    ◆ DMA_HIFCR_CFEIF7

    - -
    -
    - - - - -
    #define DMA_HIFCR_CFEIF7   DMA_HIFCR_CFEIF7_Msk
    -
    - -
    -
    - -

    ◆ DMA_HIFCR_CTCIF6_Pos

    - -
    -
    - - - - -
    #define DMA_HIFCR_CTCIF6_Pos   (21U)
    -
    - -
    -
    - -

    ◆ DMA_HIFCR_CTCIF6_Msk

    - -
    -
    - - - - -
    #define DMA_HIFCR_CTCIF6_Msk   (0x1UL << DMA_HIFCR_CTCIF6_Pos)
    -
    -

    0x00200000

    - -
    -
    - -

    ◆ DMA_HIFCR_CTCIF6

    - -
    -
    - - - - -
    #define DMA_HIFCR_CTCIF6   DMA_HIFCR_CTCIF6_Msk
    -
    - -
    -
    - -

    ◆ DMA_HIFCR_CHTIF6_Pos

    - -
    -
    - - - - -
    #define DMA_HIFCR_CHTIF6_Pos   (20U)
    -
    - -
    -
    - -

    ◆ DMA_HIFCR_CHTIF6_Msk

    - -
    -
    - - - - -
    #define DMA_HIFCR_CHTIF6_Msk   (0x1UL << DMA_HIFCR_CHTIF6_Pos)
    -
    -

    0x00100000

    - -
    -
    - -

    ◆ DMA_HIFCR_CHTIF6

    - -
    -
    - - - - -
    #define DMA_HIFCR_CHTIF6   DMA_HIFCR_CHTIF6_Msk
    -
    - -
    -
    - -

    ◆ DMA_HIFCR_CTEIF6_Pos

    - -
    -
    - - - - -
    #define DMA_HIFCR_CTEIF6_Pos   (19U)
    -
    - -
    -
    - -

    ◆ DMA_HIFCR_CTEIF6_Msk

    - -
    -
    - - - - -
    #define DMA_HIFCR_CTEIF6_Msk   (0x1UL << DMA_HIFCR_CTEIF6_Pos)
    -
    -

    0x00080000

    - -
    -
    - -

    ◆ DMA_HIFCR_CTEIF6

    - -
    -
    - - - - -
    #define DMA_HIFCR_CTEIF6   DMA_HIFCR_CTEIF6_Msk
    -
    - -
    -
    - -

    ◆ DMA_HIFCR_CDMEIF6_Pos

    - -
    -
    - - - - -
    #define DMA_HIFCR_CDMEIF6_Pos   (18U)
    -
    - -
    -
    - -

    ◆ DMA_HIFCR_CDMEIF6_Msk

    - -
    -
    - - - - -
    #define DMA_HIFCR_CDMEIF6_Msk   (0x1UL << DMA_HIFCR_CDMEIF6_Pos)
    -
    -

    0x00040000

    - -
    -
    - -

    ◆ DMA_HIFCR_CDMEIF6

    - -
    -
    - - - - -
    #define DMA_HIFCR_CDMEIF6   DMA_HIFCR_CDMEIF6_Msk
    -
    - -
    -
    - -

    ◆ DMA_HIFCR_CFEIF6_Pos

    - -
    -
    - - - - -
    #define DMA_HIFCR_CFEIF6_Pos   (16U)
    -
    - -
    -
    - -

    ◆ DMA_HIFCR_CFEIF6_Msk

    - -
    -
    - - - - -
    #define DMA_HIFCR_CFEIF6_Msk   (0x1UL << DMA_HIFCR_CFEIF6_Pos)
    -
    -

    0x00010000

    - -
    -
    - -

    ◆ DMA_HIFCR_CFEIF6

    - -
    -
    - - - - -
    #define DMA_HIFCR_CFEIF6   DMA_HIFCR_CFEIF6_Msk
    -
    - -
    -
    - -

    ◆ DMA_HIFCR_CTCIF5_Pos

    - -
    -
    - - - - -
    #define DMA_HIFCR_CTCIF5_Pos   (11U)
    -
    - -
    -
    - -

    ◆ DMA_HIFCR_CTCIF5_Msk

    - -
    -
    - - - - -
    #define DMA_HIFCR_CTCIF5_Msk   (0x1UL << DMA_HIFCR_CTCIF5_Pos)
    -
    -

    0x00000800

    - -
    -
    - -

    ◆ DMA_HIFCR_CTCIF5

    - -
    -
    - - - - -
    #define DMA_HIFCR_CTCIF5   DMA_HIFCR_CTCIF5_Msk
    -
    - -
    -
    - -

    ◆ DMA_HIFCR_CHTIF5_Pos

    - -
    -
    - - - - -
    #define DMA_HIFCR_CHTIF5_Pos   (10U)
    -
    - -
    -
    - -

    ◆ DMA_HIFCR_CHTIF5_Msk

    - -
    -
    - - - - -
    #define DMA_HIFCR_CHTIF5_Msk   (0x1UL << DMA_HIFCR_CHTIF5_Pos)
    -
    -

    0x00000400

    - -
    -
    - -

    ◆ DMA_HIFCR_CHTIF5

    - -
    -
    - - - - -
    #define DMA_HIFCR_CHTIF5   DMA_HIFCR_CHTIF5_Msk
    -
    - -
    -
    - -

    ◆ DMA_HIFCR_CTEIF5_Pos

    - -
    -
    - - - - -
    #define DMA_HIFCR_CTEIF5_Pos   (9U)
    -
    - -
    -
    - -

    ◆ DMA_HIFCR_CTEIF5_Msk

    - -
    -
    - - - - -
    #define DMA_HIFCR_CTEIF5_Msk   (0x1UL << DMA_HIFCR_CTEIF5_Pos)
    -
    -

    0x00000200

    - -
    -
    - -

    ◆ DMA_HIFCR_CTEIF5

    - -
    -
    - - - - -
    #define DMA_HIFCR_CTEIF5   DMA_HIFCR_CTEIF5_Msk
    -
    - -
    -
    - -

    ◆ DMA_HIFCR_CDMEIF5_Pos

    - -
    -
    - - - - -
    #define DMA_HIFCR_CDMEIF5_Pos   (8U)
    -
    - -
    -
    - -

    ◆ DMA_HIFCR_CDMEIF5_Msk

    - -
    -
    - - - - -
    #define DMA_HIFCR_CDMEIF5_Msk   (0x1UL << DMA_HIFCR_CDMEIF5_Pos)
    -
    -

    0x00000100

    - -
    -
    - -

    ◆ DMA_HIFCR_CDMEIF5

    - -
    -
    - - - - -
    #define DMA_HIFCR_CDMEIF5   DMA_HIFCR_CDMEIF5_Msk
    -
    - -
    -
    - -

    ◆ DMA_HIFCR_CFEIF5_Pos

    - -
    -
    - - - - -
    #define DMA_HIFCR_CFEIF5_Pos   (6U)
    -
    - -
    -
    - -

    ◆ DMA_HIFCR_CFEIF5_Msk

    - -
    -
    - - - - -
    #define DMA_HIFCR_CFEIF5_Msk   (0x1UL << DMA_HIFCR_CFEIF5_Pos)
    -
    -

    0x00000040

    - -
    -
    - -

    ◆ DMA_HIFCR_CFEIF5

    - -
    -
    - - - - -
    #define DMA_HIFCR_CFEIF5   DMA_HIFCR_CFEIF5_Msk
    -
    - -
    -
    - -

    ◆ DMA_HIFCR_CTCIF4_Pos

    - -
    -
    - - - - -
    #define DMA_HIFCR_CTCIF4_Pos   (5U)
    -
    - -
    -
    - -

    ◆ DMA_HIFCR_CTCIF4_Msk

    - -
    -
    - - - - -
    #define DMA_HIFCR_CTCIF4_Msk   (0x1UL << DMA_HIFCR_CTCIF4_Pos)
    -
    -

    0x00000020

    - -
    -
    - -

    ◆ DMA_HIFCR_CTCIF4

    - -
    -
    - - - - -
    #define DMA_HIFCR_CTCIF4   DMA_HIFCR_CTCIF4_Msk
    -
    - -
    -
    - -

    ◆ DMA_HIFCR_CHTIF4_Pos

    - -
    -
    - - - - -
    #define DMA_HIFCR_CHTIF4_Pos   (4U)
    -
    - -
    -
    - -

    ◆ DMA_HIFCR_CHTIF4_Msk

    - -
    -
    - - - - -
    #define DMA_HIFCR_CHTIF4_Msk   (0x1UL << DMA_HIFCR_CHTIF4_Pos)
    -
    -

    0x00000010

    - -
    -
    - -

    ◆ DMA_HIFCR_CHTIF4

    - -
    -
    - - - - -
    #define DMA_HIFCR_CHTIF4   DMA_HIFCR_CHTIF4_Msk
    -
    - -
    -
    - -

    ◆ DMA_HIFCR_CTEIF4_Pos

    - -
    -
    - - - - -
    #define DMA_HIFCR_CTEIF4_Pos   (3U)
    -
    - -
    -
    - -

    ◆ DMA_HIFCR_CTEIF4_Msk

    - -
    -
    - - - - -
    #define DMA_HIFCR_CTEIF4_Msk   (0x1UL << DMA_HIFCR_CTEIF4_Pos)
    -
    -

    0x00000008

    - -
    -
    - -

    ◆ DMA_HIFCR_CTEIF4

    - -
    -
    - - - - -
    #define DMA_HIFCR_CTEIF4   DMA_HIFCR_CTEIF4_Msk
    -
    - -
    -
    - -

    ◆ DMA_HIFCR_CDMEIF4_Pos

    - -
    -
    - - - - -
    #define DMA_HIFCR_CDMEIF4_Pos   (2U)
    -
    - -
    -
    - -

    ◆ DMA_HIFCR_CDMEIF4_Msk

    - -
    -
    - - - - -
    #define DMA_HIFCR_CDMEIF4_Msk   (0x1UL << DMA_HIFCR_CDMEIF4_Pos)
    -
    -

    0x00000004

    - -
    -
    - -

    ◆ DMA_HIFCR_CDMEIF4

    - -
    -
    - - - - -
    #define DMA_HIFCR_CDMEIF4   DMA_HIFCR_CDMEIF4_Msk
    -
    - -
    -
    - -

    ◆ DMA_HIFCR_CFEIF4_Pos

    - -
    -
    - - - - -
    #define DMA_HIFCR_CFEIF4_Pos   (0U)
    -
    - -
    -
    - -

    ◆ DMA_HIFCR_CFEIF4_Msk

    - -
    -
    - - - - -
    #define DMA_HIFCR_CFEIF4_Msk   (0x1UL << DMA_HIFCR_CFEIF4_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ DMA_HIFCR_CFEIF4

    - -
    -
    - - - - -
    #define DMA_HIFCR_CFEIF4   DMA_HIFCR_CFEIF4_Msk
    -
    - -
    -
    - -

    ◆ DMA_SxPAR_PA_Pos

    - -
    -
    - - - - -
    #define DMA_SxPAR_PA_Pos   (0U)
    -
    - -
    -
    - -

    ◆ DMA_SxPAR_PA_Msk

    - -
    -
    - - - - -
    #define DMA_SxPAR_PA_Msk   (0xFFFFFFFFUL << DMA_SxPAR_PA_Pos)
    -
    -

    0xFFFFFFFF

    - -
    -
    - -

    ◆ DMA_SxPAR_PA

    - -
    -
    - - - - -
    #define DMA_SxPAR_PA   DMA_SxPAR_PA_Msk
    -
    -

    Peripheral Address

    - -
    -
    - -

    ◆ DMA_SxM0AR_M0A_Pos

    - -
    -
    - - - - -
    #define DMA_SxM0AR_M0A_Pos   (0U)
    -
    - -
    -
    - -

    ◆ DMA_SxM0AR_M0A_Msk

    - -
    -
    - - - - -
    #define DMA_SxM0AR_M0A_Msk   (0xFFFFFFFFUL << DMA_SxM0AR_M0A_Pos)
    -
    -

    0xFFFFFFFF

    - -
    -
    - -

    ◆ DMA_SxM0AR_M0A

    - -
    -
    - - - - -
    #define DMA_SxM0AR_M0A   DMA_SxM0AR_M0A_Msk
    -
    -

    Memory Address

    - -
    -
    - -

    ◆ DMA_SxM1AR_M1A_Pos

    - -
    -
    - - - - -
    #define DMA_SxM1AR_M1A_Pos   (0U)
    -
    - -
    -
    - -

    ◆ DMA_SxM1AR_M1A_Msk

    - -
    -
    - - - - -
    #define DMA_SxM1AR_M1A_Msk   (0xFFFFFFFFUL << DMA_SxM1AR_M1A_Pos)
    -
    -

    0xFFFFFFFF

    - -
    -
    - -

    ◆ DMA_SxM1AR_M1A

    - -
    -
    - - - - -
    #define DMA_SxM1AR_M1A   DMA_SxM1AR_M1A_Msk
    -
    -

    Memory Address

    - -
    -
    - -

    ◆ EXTI_IMR_MR0_Pos

    - -
    -
    - - - - -
    #define EXTI_IMR_MR0_Pos   (0U)
    -
    - -
    -
    - -

    ◆ EXTI_IMR_MR0_Msk

    - -
    -
    - - - - -
    #define EXTI_IMR_MR0_Msk   (0x1UL << EXTI_IMR_MR0_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ EXTI_IMR_MR0

    - -
    -
    - - - - -
    #define EXTI_IMR_MR0   EXTI_IMR_MR0_Msk
    -
    -

    Interrupt Mask on line 0

    - -
    -
    - -

    ◆ EXTI_IMR_MR1_Pos

    - -
    -
    - - - - -
    #define EXTI_IMR_MR1_Pos   (1U)
    -
    - -
    -
    - -

    ◆ EXTI_IMR_MR1_Msk

    - -
    -
    - - - - -
    #define EXTI_IMR_MR1_Msk   (0x1UL << EXTI_IMR_MR1_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ EXTI_IMR_MR1

    - -
    -
    - - - - -
    #define EXTI_IMR_MR1   EXTI_IMR_MR1_Msk
    -
    -

    Interrupt Mask on line 1

    - -
    -
    - -

    ◆ EXTI_IMR_MR2_Pos

    - -
    -
    - - - - -
    #define EXTI_IMR_MR2_Pos   (2U)
    -
    - -
    -
    - -

    ◆ EXTI_IMR_MR2_Msk

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    #define EXTI_IMR_MR2_Msk   (0x1UL << EXTI_IMR_MR2_Pos)
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    0x00000004

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    ◆ EXTI_IMR_MR2

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    #define EXTI_IMR_MR2   EXTI_IMR_MR2_Msk
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    Interrupt Mask on line 2

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    ◆ EXTI_IMR_MR3_Pos

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    #define EXTI_IMR_MR3_Pos   (3U)
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    ◆ EXTI_IMR_MR3_Msk

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    #define EXTI_IMR_MR3_Msk   (0x1UL << EXTI_IMR_MR3_Pos)
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    0x00000008

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    ◆ EXTI_IMR_MR3

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    #define EXTI_IMR_MR3   EXTI_IMR_MR3_Msk
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    Interrupt Mask on line 3

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    ◆ EXTI_IMR_MR4_Pos

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    #define EXTI_IMR_MR4_Pos   (4U)
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    ◆ EXTI_IMR_MR4_Msk

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    #define EXTI_IMR_MR4_Msk   (0x1UL << EXTI_IMR_MR4_Pos)
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    0x00000010

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    ◆ EXTI_IMR_MR4

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    #define EXTI_IMR_MR4   EXTI_IMR_MR4_Msk
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    Interrupt Mask on line 4

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    ◆ EXTI_IMR_MR5_Pos

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    #define EXTI_IMR_MR5_Pos   (5U)
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    ◆ EXTI_IMR_MR5_Msk

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    #define EXTI_IMR_MR5_Msk   (0x1UL << EXTI_IMR_MR5_Pos)
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    0x00000020

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    ◆ EXTI_IMR_MR5

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    #define EXTI_IMR_MR5   EXTI_IMR_MR5_Msk
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    Interrupt Mask on line 5

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    ◆ EXTI_IMR_MR6_Pos

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    #define EXTI_IMR_MR6_Pos   (6U)
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    ◆ EXTI_IMR_MR6_Msk

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    #define EXTI_IMR_MR6_Msk   (0x1UL << EXTI_IMR_MR6_Pos)
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    0x00000040

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    ◆ EXTI_IMR_MR6

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    #define EXTI_IMR_MR6   EXTI_IMR_MR6_Msk
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    Interrupt Mask on line 6

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    ◆ EXTI_IMR_MR7_Pos

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    #define EXTI_IMR_MR7_Pos   (7U)
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    ◆ EXTI_IMR_MR7_Msk

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    #define EXTI_IMR_MR7_Msk   (0x1UL << EXTI_IMR_MR7_Pos)
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    0x00000080

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    ◆ EXTI_IMR_MR7

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    #define EXTI_IMR_MR7   EXTI_IMR_MR7_Msk
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    Interrupt Mask on line 7

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    ◆ EXTI_IMR_MR8_Pos

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    #define EXTI_IMR_MR8_Pos   (8U)
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    ◆ EXTI_IMR_MR8_Msk

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    #define EXTI_IMR_MR8_Msk   (0x1UL << EXTI_IMR_MR8_Pos)
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    0x00000100

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    ◆ EXTI_IMR_MR8

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    #define EXTI_IMR_MR8   EXTI_IMR_MR8_Msk
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    Interrupt Mask on line 8

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    ◆ EXTI_IMR_MR9_Pos

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    #define EXTI_IMR_MR9_Pos   (9U)
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    ◆ EXTI_IMR_MR9_Msk

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    #define EXTI_IMR_MR9_Msk   (0x1UL << EXTI_IMR_MR9_Pos)
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    0x00000200

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    ◆ EXTI_IMR_MR9

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    #define EXTI_IMR_MR9   EXTI_IMR_MR9_Msk
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    Interrupt Mask on line 9

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    ◆ EXTI_IMR_MR10_Pos

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    #define EXTI_IMR_MR10_Pos   (10U)
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    ◆ EXTI_IMR_MR10_Msk

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    #define EXTI_IMR_MR10_Msk   (0x1UL << EXTI_IMR_MR10_Pos)
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    0x00000400

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    ◆ EXTI_IMR_MR10

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    #define EXTI_IMR_MR10   EXTI_IMR_MR10_Msk
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    Interrupt Mask on line 10

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    ◆ EXTI_IMR_MR11_Pos

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    #define EXTI_IMR_MR11_Pos   (11U)
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    ◆ EXTI_IMR_MR11_Msk

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    #define EXTI_IMR_MR11_Msk   (0x1UL << EXTI_IMR_MR11_Pos)
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    0x00000800

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    ◆ EXTI_IMR_MR11

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    #define EXTI_IMR_MR11   EXTI_IMR_MR11_Msk
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    Interrupt Mask on line 11

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    ◆ EXTI_IMR_MR12_Pos

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    #define EXTI_IMR_MR12_Pos   (12U)
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    ◆ EXTI_IMR_MR12_Msk

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    #define EXTI_IMR_MR12_Msk   (0x1UL << EXTI_IMR_MR12_Pos)
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    0x00001000

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    ◆ EXTI_IMR_MR12

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    #define EXTI_IMR_MR12   EXTI_IMR_MR12_Msk
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    Interrupt Mask on line 12

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    ◆ EXTI_IMR_MR13_Pos

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    #define EXTI_IMR_MR13_Pos   (13U)
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    ◆ EXTI_IMR_MR13_Msk

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    #define EXTI_IMR_MR13_Msk   (0x1UL << EXTI_IMR_MR13_Pos)
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    0x00002000

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    ◆ EXTI_IMR_MR13

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    #define EXTI_IMR_MR13   EXTI_IMR_MR13_Msk
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    Interrupt Mask on line 13

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    ◆ EXTI_IMR_MR14_Pos

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    #define EXTI_IMR_MR14_Pos   (14U)
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    ◆ EXTI_IMR_MR14_Msk

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    #define EXTI_IMR_MR14_Msk   (0x1UL << EXTI_IMR_MR14_Pos)
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    0x00004000

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    ◆ EXTI_IMR_MR14

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    #define EXTI_IMR_MR14   EXTI_IMR_MR14_Msk
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    Interrupt Mask on line 14

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    ◆ EXTI_IMR_MR15_Pos

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    #define EXTI_IMR_MR15_Pos   (15U)
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    ◆ EXTI_IMR_MR15_Msk

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    #define EXTI_IMR_MR15_Msk   (0x1UL << EXTI_IMR_MR15_Pos)
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    0x00008000

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    ◆ EXTI_IMR_MR15

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    #define EXTI_IMR_MR15   EXTI_IMR_MR15_Msk
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    Interrupt Mask on line 15

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    ◆ EXTI_IMR_MR16_Pos

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    #define EXTI_IMR_MR16_Pos   (16U)
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    ◆ EXTI_IMR_MR16_Msk

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    #define EXTI_IMR_MR16_Msk   (0x1UL << EXTI_IMR_MR16_Pos)
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    0x00010000

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    ◆ EXTI_IMR_MR16

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    #define EXTI_IMR_MR16   EXTI_IMR_MR16_Msk
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    Interrupt Mask on line 16

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    ◆ EXTI_IMR_MR17_Pos

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    #define EXTI_IMR_MR17_Pos   (17U)
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    ◆ EXTI_IMR_MR17_Msk

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    #define EXTI_IMR_MR17_Msk   (0x1UL << EXTI_IMR_MR17_Pos)
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    0x00020000

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    ◆ EXTI_IMR_MR17

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    #define EXTI_IMR_MR17   EXTI_IMR_MR17_Msk
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    Interrupt Mask on line 17

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    ◆ EXTI_IMR_MR18_Pos

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    #define EXTI_IMR_MR18_Pos   (18U)
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    ◆ EXTI_IMR_MR18_Msk

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    #define EXTI_IMR_MR18_Msk   (0x1UL << EXTI_IMR_MR18_Pos)
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    0x00040000

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    ◆ EXTI_IMR_MR18

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    #define EXTI_IMR_MR18   EXTI_IMR_MR18_Msk
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    Interrupt Mask on line 18

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    ◆ EXTI_IMR_MR19_Pos

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    #define EXTI_IMR_MR19_Pos   (19U)
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    ◆ EXTI_IMR_MR19_Msk

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    #define EXTI_IMR_MR19_Msk   (0x1UL << EXTI_IMR_MR19_Pos)
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    0x00080000

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    ◆ EXTI_IMR_MR19

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    #define EXTI_IMR_MR19   EXTI_IMR_MR19_Msk
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    Interrupt Mask on line 19

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    ◆ EXTI_IMR_MR20_Pos

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    #define EXTI_IMR_MR20_Pos   (20U)
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    ◆ EXTI_IMR_MR20_Msk

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    #define EXTI_IMR_MR20_Msk   (0x1UL << EXTI_IMR_MR20_Pos)
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    0x00100000

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    ◆ EXTI_IMR_MR20

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    #define EXTI_IMR_MR20   EXTI_IMR_MR20_Msk
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    Interrupt Mask on line 20

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    ◆ EXTI_IMR_MR21_Pos

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    #define EXTI_IMR_MR21_Pos   (21U)
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    ◆ EXTI_IMR_MR21_Msk

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    #define EXTI_IMR_MR21_Msk   (0x1UL << EXTI_IMR_MR21_Pos)
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    0x00200000

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    ◆ EXTI_IMR_MR21

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    #define EXTI_IMR_MR21   EXTI_IMR_MR21_Msk
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    Interrupt Mask on line 21

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    ◆ EXTI_IMR_MR22_Pos

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    #define EXTI_IMR_MR22_Pos   (22U)
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    ◆ EXTI_IMR_MR22_Msk

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    #define EXTI_IMR_MR22_Msk   (0x1UL << EXTI_IMR_MR22_Pos)
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    0x00400000

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    ◆ EXTI_IMR_MR22

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    #define EXTI_IMR_MR22   EXTI_IMR_MR22_Msk
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    Interrupt Mask on line 22

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    ◆ EXTI_IMR_IM0

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    #define EXTI_IMR_IM0   EXTI_IMR_MR0
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    ◆ EXTI_IMR_IM1

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    #define EXTI_IMR_IM1   EXTI_IMR_MR1
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    ◆ EXTI_IMR_IM2

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    #define EXTI_IMR_IM2   EXTI_IMR_MR2
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    ◆ EXTI_IMR_IM3

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    #define EXTI_IMR_IM3   EXTI_IMR_MR3
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    ◆ EXTI_IMR_IM4

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    #define EXTI_IMR_IM4   EXTI_IMR_MR4
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    ◆ EXTI_IMR_IM5

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    #define EXTI_IMR_IM5   EXTI_IMR_MR5
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    ◆ EXTI_IMR_IM6

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    #define EXTI_IMR_IM6   EXTI_IMR_MR6
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    ◆ EXTI_IMR_IM7

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    #define EXTI_IMR_IM7   EXTI_IMR_MR7
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    ◆ EXTI_IMR_IM8

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    #define EXTI_IMR_IM8   EXTI_IMR_MR8
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    ◆ EXTI_IMR_IM9

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    #define EXTI_IMR_IM9   EXTI_IMR_MR9
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    ◆ EXTI_IMR_IM10

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    #define EXTI_IMR_IM10   EXTI_IMR_MR10
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    ◆ EXTI_IMR_IM11

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    #define EXTI_IMR_IM11   EXTI_IMR_MR11
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    ◆ EXTI_IMR_IM12

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    #define EXTI_IMR_IM12   EXTI_IMR_MR12
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    ◆ EXTI_IMR_IM13

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    #define EXTI_IMR_IM13   EXTI_IMR_MR13
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    ◆ EXTI_IMR_IM14

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    #define EXTI_IMR_IM14   EXTI_IMR_MR14
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    ◆ EXTI_IMR_IM15

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    #define EXTI_IMR_IM15   EXTI_IMR_MR15
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    ◆ EXTI_IMR_IM16

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    #define EXTI_IMR_IM16   EXTI_IMR_MR16
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    ◆ EXTI_IMR_IM17

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    #define EXTI_IMR_IM17   EXTI_IMR_MR17
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    ◆ EXTI_IMR_IM18

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    #define EXTI_IMR_IM18   EXTI_IMR_MR18
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    ◆ EXTI_IMR_IM19

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    #define EXTI_IMR_IM19   EXTI_IMR_MR19
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    ◆ EXTI_IMR_IM20

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    #define EXTI_IMR_IM20   EXTI_IMR_MR20
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    ◆ EXTI_IMR_IM21

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    #define EXTI_IMR_IM21   EXTI_IMR_MR21
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    ◆ EXTI_IMR_IM22

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    #define EXTI_IMR_IM22   EXTI_IMR_MR22
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    ◆ EXTI_IMR_IM_Pos

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    #define EXTI_IMR_IM_Pos   (0U)
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    ◆ EXTI_IMR_IM_Msk

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    #define EXTI_IMR_IM_Msk   (0x7FFFFFUL << EXTI_IMR_IM_Pos)
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    0x007FFFFF

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    ◆ EXTI_IMR_IM

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    #define EXTI_IMR_IM   EXTI_IMR_IM_Msk
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    Interrupt Mask All

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    ◆ EXTI_EMR_MR0_Pos

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    #define EXTI_EMR_MR0_Pos   (0U)
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    ◆ EXTI_EMR_MR0_Msk

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    #define EXTI_EMR_MR0_Msk   (0x1UL << EXTI_EMR_MR0_Pos)
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    0x00000001

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    ◆ EXTI_EMR_MR0

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    #define EXTI_EMR_MR0   EXTI_EMR_MR0_Msk
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    Event Mask on line 0

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    ◆ EXTI_EMR_MR1_Pos

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    #define EXTI_EMR_MR1_Pos   (1U)
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    ◆ EXTI_EMR_MR1_Msk

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    #define EXTI_EMR_MR1_Msk   (0x1UL << EXTI_EMR_MR1_Pos)
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    0x00000002

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    ◆ EXTI_EMR_MR1

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    #define EXTI_EMR_MR1   EXTI_EMR_MR1_Msk
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    Event Mask on line 1

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    ◆ EXTI_EMR_MR2_Pos

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    #define EXTI_EMR_MR2_Pos   (2U)
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    ◆ EXTI_EMR_MR2_Msk

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    #define EXTI_EMR_MR2_Msk   (0x1UL << EXTI_EMR_MR2_Pos)
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    0x00000004

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    ◆ EXTI_EMR_MR2

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    #define EXTI_EMR_MR2   EXTI_EMR_MR2_Msk
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    Event Mask on line 2

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    ◆ EXTI_EMR_MR3_Pos

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    #define EXTI_EMR_MR3_Pos   (3U)
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    ◆ EXTI_EMR_MR3_Msk

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    #define EXTI_EMR_MR3_Msk   (0x1UL << EXTI_EMR_MR3_Pos)
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    0x00000008

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    ◆ EXTI_EMR_MR3

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    #define EXTI_EMR_MR3   EXTI_EMR_MR3_Msk
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    Event Mask on line 3

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    ◆ EXTI_EMR_MR4_Pos

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    #define EXTI_EMR_MR4_Pos   (4U)
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    ◆ EXTI_EMR_MR4_Msk

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    #define EXTI_EMR_MR4_Msk   (0x1UL << EXTI_EMR_MR4_Pos)
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    0x00000010

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    ◆ EXTI_EMR_MR4

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    #define EXTI_EMR_MR4   EXTI_EMR_MR4_Msk
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    Event Mask on line 4

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    ◆ EXTI_EMR_MR5_Pos

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    #define EXTI_EMR_MR5_Pos   (5U)
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    ◆ EXTI_EMR_MR5_Msk

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    #define EXTI_EMR_MR5_Msk   (0x1UL << EXTI_EMR_MR5_Pos)
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    0x00000020

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    ◆ EXTI_EMR_MR5

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    #define EXTI_EMR_MR5   EXTI_EMR_MR5_Msk
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    Event Mask on line 5

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    ◆ EXTI_EMR_MR6_Pos

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    #define EXTI_EMR_MR6_Pos   (6U)
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    ◆ EXTI_EMR_MR6_Msk

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    #define EXTI_EMR_MR6_Msk   (0x1UL << EXTI_EMR_MR6_Pos)
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    0x00000040

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    ◆ EXTI_EMR_MR6

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    #define EXTI_EMR_MR6   EXTI_EMR_MR6_Msk
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    Event Mask on line 6

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    ◆ EXTI_EMR_MR7_Pos

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    #define EXTI_EMR_MR7_Pos   (7U)
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    ◆ EXTI_EMR_MR7_Msk

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    #define EXTI_EMR_MR7_Msk   (0x1UL << EXTI_EMR_MR7_Pos)
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    0x00000080

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    ◆ EXTI_EMR_MR7

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    #define EXTI_EMR_MR7   EXTI_EMR_MR7_Msk
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    Event Mask on line 7

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    ◆ EXTI_EMR_MR8_Pos

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    #define EXTI_EMR_MR8_Pos   (8U)
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    ◆ EXTI_EMR_MR8_Msk

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    #define EXTI_EMR_MR8_Msk   (0x1UL << EXTI_EMR_MR8_Pos)
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    0x00000100

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    ◆ EXTI_EMR_MR8

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    #define EXTI_EMR_MR8   EXTI_EMR_MR8_Msk
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    Event Mask on line 8

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    ◆ EXTI_EMR_MR9_Pos

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    #define EXTI_EMR_MR9_Pos   (9U)
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    ◆ EXTI_EMR_MR9_Msk

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    #define EXTI_EMR_MR9_Msk   (0x1UL << EXTI_EMR_MR9_Pos)
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    0x00000200

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    ◆ EXTI_EMR_MR9

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    #define EXTI_EMR_MR9   EXTI_EMR_MR9_Msk
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    Event Mask on line 9

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    ◆ EXTI_EMR_MR10_Pos

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    #define EXTI_EMR_MR10_Pos   (10U)
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    ◆ EXTI_EMR_MR10_Msk

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    #define EXTI_EMR_MR10_Msk   (0x1UL << EXTI_EMR_MR10_Pos)
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    0x00000400

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    ◆ EXTI_EMR_MR10

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    #define EXTI_EMR_MR10   EXTI_EMR_MR10_Msk
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    Event Mask on line 10

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    ◆ EXTI_EMR_MR11_Pos

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    #define EXTI_EMR_MR11_Pos   (11U)
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    ◆ EXTI_EMR_MR11_Msk

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    #define EXTI_EMR_MR11_Msk   (0x1UL << EXTI_EMR_MR11_Pos)
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    0x00000800

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    ◆ EXTI_EMR_MR11

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    #define EXTI_EMR_MR11   EXTI_EMR_MR11_Msk
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    Event Mask on line 11

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    ◆ EXTI_EMR_MR12_Pos

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    #define EXTI_EMR_MR12_Pos   (12U)
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    ◆ EXTI_EMR_MR12_Msk

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    #define EXTI_EMR_MR12_Msk   (0x1UL << EXTI_EMR_MR12_Pos)
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    0x00001000

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    ◆ EXTI_EMR_MR12

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    #define EXTI_EMR_MR12   EXTI_EMR_MR12_Msk
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    Event Mask on line 12

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    ◆ EXTI_EMR_MR13_Pos

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    #define EXTI_EMR_MR13_Pos   (13U)
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    ◆ EXTI_EMR_MR13_Msk

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    #define EXTI_EMR_MR13_Msk   (0x1UL << EXTI_EMR_MR13_Pos)
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    0x00002000

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    ◆ EXTI_EMR_MR13

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    #define EXTI_EMR_MR13   EXTI_EMR_MR13_Msk
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    Event Mask on line 13

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    ◆ EXTI_EMR_MR14_Pos

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    #define EXTI_EMR_MR14_Pos   (14U)
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    ◆ EXTI_EMR_MR14_Msk

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    #define EXTI_EMR_MR14_Msk   (0x1UL << EXTI_EMR_MR14_Pos)
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    0x00004000

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    ◆ EXTI_EMR_MR14

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    #define EXTI_EMR_MR14   EXTI_EMR_MR14_Msk
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    Event Mask on line 14

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    ◆ EXTI_EMR_MR15_Pos

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    #define EXTI_EMR_MR15_Pos   (15U)
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    ◆ EXTI_EMR_MR15_Msk

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    #define EXTI_EMR_MR15_Msk   (0x1UL << EXTI_EMR_MR15_Pos)
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    0x00008000

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    ◆ EXTI_EMR_MR15

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    #define EXTI_EMR_MR15   EXTI_EMR_MR15_Msk
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    Event Mask on line 15

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    ◆ EXTI_EMR_MR16_Pos

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    #define EXTI_EMR_MR16_Pos   (16U)
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    ◆ EXTI_EMR_MR16_Msk

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    #define EXTI_EMR_MR16_Msk   (0x1UL << EXTI_EMR_MR16_Pos)
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    0x00010000

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    ◆ EXTI_EMR_MR16

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    #define EXTI_EMR_MR16   EXTI_EMR_MR16_Msk
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    Event Mask on line 16

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    ◆ EXTI_EMR_MR17_Pos

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    #define EXTI_EMR_MR17_Pos   (17U)
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    ◆ EXTI_EMR_MR17_Msk

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    #define EXTI_EMR_MR17_Msk   (0x1UL << EXTI_EMR_MR17_Pos)
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    0x00020000

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    ◆ EXTI_EMR_MR17

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    #define EXTI_EMR_MR17   EXTI_EMR_MR17_Msk
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    Event Mask on line 17

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    ◆ EXTI_EMR_MR18_Pos

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    #define EXTI_EMR_MR18_Pos   (18U)
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    ◆ EXTI_EMR_MR18_Msk

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    #define EXTI_EMR_MR18_Msk   (0x1UL << EXTI_EMR_MR18_Pos)
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    0x00040000

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    ◆ EXTI_EMR_MR18

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    #define EXTI_EMR_MR18   EXTI_EMR_MR18_Msk
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    Event Mask on line 18

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    ◆ EXTI_EMR_MR19_Pos

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    #define EXTI_EMR_MR19_Pos   (19U)
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    ◆ EXTI_EMR_MR19_Msk

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    #define EXTI_EMR_MR19_Msk   (0x1UL << EXTI_EMR_MR19_Pos)
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    0x00080000

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    ◆ EXTI_EMR_MR19

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    #define EXTI_EMR_MR19   EXTI_EMR_MR19_Msk
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    Event Mask on line 19

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    ◆ EXTI_EMR_MR20_Pos

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    #define EXTI_EMR_MR20_Pos   (20U)
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    ◆ EXTI_EMR_MR20_Msk

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    #define EXTI_EMR_MR20_Msk   (0x1UL << EXTI_EMR_MR20_Pos)
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    0x00100000

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    ◆ EXTI_EMR_MR20

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    #define EXTI_EMR_MR20   EXTI_EMR_MR20_Msk
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    Event Mask on line 20

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    ◆ EXTI_EMR_MR21_Pos

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    #define EXTI_EMR_MR21_Pos   (21U)
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    ◆ EXTI_EMR_MR21_Msk

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    #define EXTI_EMR_MR21_Msk   (0x1UL << EXTI_EMR_MR21_Pos)
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    0x00200000

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    ◆ EXTI_EMR_MR21

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    #define EXTI_EMR_MR21   EXTI_EMR_MR21_Msk
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    Event Mask on line 21

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    ◆ EXTI_EMR_MR22_Pos

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    #define EXTI_EMR_MR22_Pos   (22U)
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    ◆ EXTI_EMR_MR22_Msk

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    #define EXTI_EMR_MR22_Msk   (0x1UL << EXTI_EMR_MR22_Pos)
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    0x00400000

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    ◆ EXTI_EMR_MR22

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    #define EXTI_EMR_MR22   EXTI_EMR_MR22_Msk
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    Event Mask on line 22

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    ◆ EXTI_EMR_EM0

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    #define EXTI_EMR_EM0   EXTI_EMR_MR0
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    ◆ EXTI_EMR_EM1

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    #define EXTI_EMR_EM1   EXTI_EMR_MR1
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    ◆ EXTI_EMR_EM2

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    #define EXTI_EMR_EM2   EXTI_EMR_MR2
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    ◆ EXTI_EMR_EM3

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    #define EXTI_EMR_EM3   EXTI_EMR_MR3
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    ◆ EXTI_EMR_EM4

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    #define EXTI_EMR_EM4   EXTI_EMR_MR4
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    ◆ EXTI_EMR_EM5

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    #define EXTI_EMR_EM5   EXTI_EMR_MR5
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    ◆ EXTI_EMR_EM6

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    #define EXTI_EMR_EM6   EXTI_EMR_MR6
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    ◆ EXTI_EMR_EM7

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    #define EXTI_EMR_EM7   EXTI_EMR_MR7
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    ◆ EXTI_EMR_EM8

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    #define EXTI_EMR_EM8   EXTI_EMR_MR8
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    ◆ EXTI_EMR_EM9

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    #define EXTI_EMR_EM9   EXTI_EMR_MR9
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    ◆ EXTI_EMR_EM10

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    #define EXTI_EMR_EM10   EXTI_EMR_MR10
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    ◆ EXTI_EMR_EM11

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    #define EXTI_EMR_EM11   EXTI_EMR_MR11
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    ◆ EXTI_EMR_EM12

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    #define EXTI_EMR_EM12   EXTI_EMR_MR12
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    ◆ EXTI_EMR_EM13

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    #define EXTI_EMR_EM13   EXTI_EMR_MR13
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    ◆ EXTI_EMR_EM14

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    #define EXTI_EMR_EM14   EXTI_EMR_MR14
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    ◆ EXTI_EMR_EM15

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    #define EXTI_EMR_EM15   EXTI_EMR_MR15
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    ◆ EXTI_EMR_EM16

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    #define EXTI_EMR_EM16   EXTI_EMR_MR16
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    ◆ EXTI_EMR_EM17

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    #define EXTI_EMR_EM17   EXTI_EMR_MR17
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    ◆ EXTI_EMR_EM18

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    #define EXTI_EMR_EM18   EXTI_EMR_MR18
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    ◆ EXTI_EMR_EM19

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    #define EXTI_EMR_EM19   EXTI_EMR_MR19
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    ◆ EXTI_EMR_EM20

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    #define EXTI_EMR_EM20   EXTI_EMR_MR20
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    ◆ EXTI_EMR_EM21

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    #define EXTI_EMR_EM21   EXTI_EMR_MR21
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    ◆ EXTI_EMR_EM22

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    #define EXTI_EMR_EM22   EXTI_EMR_MR22
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    ◆ EXTI_RTSR_TR0_Pos

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    #define EXTI_RTSR_TR0_Pos   (0U)
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    ◆ EXTI_RTSR_TR0_Msk

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    #define EXTI_RTSR_TR0_Msk   (0x1UL << EXTI_RTSR_TR0_Pos)
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    0x00000001

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    ◆ EXTI_RTSR_TR0

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    #define EXTI_RTSR_TR0   EXTI_RTSR_TR0_Msk
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    Rising trigger event configuration bit of line 0

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    ◆ EXTI_RTSR_TR1_Pos

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    #define EXTI_RTSR_TR1_Pos   (1U)
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    ◆ EXTI_RTSR_TR1_Msk

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    #define EXTI_RTSR_TR1_Msk   (0x1UL << EXTI_RTSR_TR1_Pos)
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    0x00000002

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    ◆ EXTI_RTSR_TR1

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    #define EXTI_RTSR_TR1   EXTI_RTSR_TR1_Msk
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    Rising trigger event configuration bit of line 1

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    ◆ EXTI_RTSR_TR2_Pos

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    #define EXTI_RTSR_TR2_Pos   (2U)
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    ◆ EXTI_RTSR_TR2_Msk

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    #define EXTI_RTSR_TR2_Msk   (0x1UL << EXTI_RTSR_TR2_Pos)
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    0x00000004

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    ◆ EXTI_RTSR_TR2

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    #define EXTI_RTSR_TR2   EXTI_RTSR_TR2_Msk
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    Rising trigger event configuration bit of line 2

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    ◆ EXTI_RTSR_TR3_Pos

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    #define EXTI_RTSR_TR3_Pos   (3U)
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    ◆ EXTI_RTSR_TR3_Msk

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    #define EXTI_RTSR_TR3_Msk   (0x1UL << EXTI_RTSR_TR3_Pos)
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    0x00000008

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    ◆ EXTI_RTSR_TR3

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    #define EXTI_RTSR_TR3   EXTI_RTSR_TR3_Msk
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    Rising trigger event configuration bit of line 3

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    ◆ EXTI_RTSR_TR4_Pos

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    #define EXTI_RTSR_TR4_Pos   (4U)
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    ◆ EXTI_RTSR_TR4_Msk

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    #define EXTI_RTSR_TR4_Msk   (0x1UL << EXTI_RTSR_TR4_Pos)
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    0x00000010

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    ◆ EXTI_RTSR_TR4

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    #define EXTI_RTSR_TR4   EXTI_RTSR_TR4_Msk
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    Rising trigger event configuration bit of line 4

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    ◆ EXTI_RTSR_TR5_Pos

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    #define EXTI_RTSR_TR5_Pos   (5U)
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    ◆ EXTI_RTSR_TR5_Msk

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    #define EXTI_RTSR_TR5_Msk   (0x1UL << EXTI_RTSR_TR5_Pos)
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    0x00000020

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    ◆ EXTI_RTSR_TR5

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    #define EXTI_RTSR_TR5   EXTI_RTSR_TR5_Msk
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    Rising trigger event configuration bit of line 5

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    ◆ EXTI_RTSR_TR6_Pos

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    #define EXTI_RTSR_TR6_Pos   (6U)
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    - -
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    - -

    ◆ EXTI_RTSR_TR6_Msk

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    #define EXTI_RTSR_TR6_Msk   (0x1UL << EXTI_RTSR_TR6_Pos)
    -
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    0x00000040

    - -
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    ◆ EXTI_RTSR_TR6

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    #define EXTI_RTSR_TR6   EXTI_RTSR_TR6_Msk
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    Rising trigger event configuration bit of line 6

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    ◆ EXTI_RTSR_TR7_Pos

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    #define EXTI_RTSR_TR7_Pos   (7U)
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    - -
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    - -

    ◆ EXTI_RTSR_TR7_Msk

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    #define EXTI_RTSR_TR7_Msk   (0x1UL << EXTI_RTSR_TR7_Pos)
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    0x00000080

    - -
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    ◆ EXTI_RTSR_TR7

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    #define EXTI_RTSR_TR7   EXTI_RTSR_TR7_Msk
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    Rising trigger event configuration bit of line 7

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    ◆ EXTI_RTSR_TR8_Pos

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    #define EXTI_RTSR_TR8_Pos   (8U)
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    - -
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    ◆ EXTI_RTSR_TR8_Msk

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    #define EXTI_RTSR_TR8_Msk   (0x1UL << EXTI_RTSR_TR8_Pos)
    -
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    0x00000100

    - -
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    ◆ EXTI_RTSR_TR8

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    #define EXTI_RTSR_TR8   EXTI_RTSR_TR8_Msk
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    Rising trigger event configuration bit of line 8

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    ◆ EXTI_RTSR_TR9_Pos

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    #define EXTI_RTSR_TR9_Pos   (9U)
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    ◆ EXTI_RTSR_TR9_Msk

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    #define EXTI_RTSR_TR9_Msk   (0x1UL << EXTI_RTSR_TR9_Pos)
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    0x00000200

    - -
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    ◆ EXTI_RTSR_TR9

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    #define EXTI_RTSR_TR9   EXTI_RTSR_TR9_Msk
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    Rising trigger event configuration bit of line 9

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    ◆ EXTI_RTSR_TR10_Pos

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    #define EXTI_RTSR_TR10_Pos   (10U)
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    ◆ EXTI_RTSR_TR10_Msk

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    #define EXTI_RTSR_TR10_Msk   (0x1UL << EXTI_RTSR_TR10_Pos)
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    0x00000400

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    ◆ EXTI_RTSR_TR10

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    #define EXTI_RTSR_TR10   EXTI_RTSR_TR10_Msk
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    Rising trigger event configuration bit of line 10

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    ◆ EXTI_RTSR_TR11_Pos

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    #define EXTI_RTSR_TR11_Pos   (11U)
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    ◆ EXTI_RTSR_TR11_Msk

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    #define EXTI_RTSR_TR11_Msk   (0x1UL << EXTI_RTSR_TR11_Pos)
    -
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    0x00000800

    - -
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    ◆ EXTI_RTSR_TR11

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    #define EXTI_RTSR_TR11   EXTI_RTSR_TR11_Msk
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    Rising trigger event configuration bit of line 11

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    ◆ EXTI_RTSR_TR12_Pos

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    #define EXTI_RTSR_TR12_Pos   (12U)
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    - -
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    - -

    ◆ EXTI_RTSR_TR12_Msk

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    - - - - -
    #define EXTI_RTSR_TR12_Msk   (0x1UL << EXTI_RTSR_TR12_Pos)
    -
    -

    0x00001000

    - -
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    ◆ EXTI_RTSR_TR12

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    #define EXTI_RTSR_TR12   EXTI_RTSR_TR12_Msk
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    Rising trigger event configuration bit of line 12

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    ◆ EXTI_RTSR_TR13_Pos

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    -
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    #define EXTI_RTSR_TR13_Pos   (13U)
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    - -
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    - -

    ◆ EXTI_RTSR_TR13_Msk

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    - - - - -
    #define EXTI_RTSR_TR13_Msk   (0x1UL << EXTI_RTSR_TR13_Pos)
    -
    -

    0x00002000

    - -
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    ◆ EXTI_RTSR_TR13

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    #define EXTI_RTSR_TR13   EXTI_RTSR_TR13_Msk
    -
    -

    Rising trigger event configuration bit of line 13

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    ◆ EXTI_RTSR_TR14_Pos

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    #define EXTI_RTSR_TR14_Pos   (14U)
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    - -
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    - -

    ◆ EXTI_RTSR_TR14_Msk

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    - - - - -
    #define EXTI_RTSR_TR14_Msk   (0x1UL << EXTI_RTSR_TR14_Pos)
    -
    -

    0x00004000

    - -
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    - -

    ◆ EXTI_RTSR_TR14

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    #define EXTI_RTSR_TR14   EXTI_RTSR_TR14_Msk
    -
    -

    Rising trigger event configuration bit of line 14

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    ◆ EXTI_RTSR_TR15_Pos

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    -
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    #define EXTI_RTSR_TR15_Pos   (15U)
    -
    - -
    -
    - -

    ◆ EXTI_RTSR_TR15_Msk

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    - - - - -
    #define EXTI_RTSR_TR15_Msk   (0x1UL << EXTI_RTSR_TR15_Pos)
    -
    -

    0x00008000

    - -
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    - -

    ◆ EXTI_RTSR_TR15

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    #define EXTI_RTSR_TR15   EXTI_RTSR_TR15_Msk
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    -

    Rising trigger event configuration bit of line 15

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    ◆ EXTI_RTSR_TR16_Pos

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    #define EXTI_RTSR_TR16_Pos   (16U)
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    - -
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    - -

    ◆ EXTI_RTSR_TR16_Msk

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    - - - - -
    #define EXTI_RTSR_TR16_Msk   (0x1UL << EXTI_RTSR_TR16_Pos)
    -
    -

    0x00010000

    - -
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    - -

    ◆ EXTI_RTSR_TR16

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    #define EXTI_RTSR_TR16   EXTI_RTSR_TR16_Msk
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    -

    Rising trigger event configuration bit of line 16

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    ◆ EXTI_RTSR_TR17_Pos

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    -
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    #define EXTI_RTSR_TR17_Pos   (17U)
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    - -
    -
    - -

    ◆ EXTI_RTSR_TR17_Msk

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    - - - - -
    #define EXTI_RTSR_TR17_Msk   (0x1UL << EXTI_RTSR_TR17_Pos)
    -
    -

    0x00020000

    - -
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    - -

    ◆ EXTI_RTSR_TR17

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    #define EXTI_RTSR_TR17   EXTI_RTSR_TR17_Msk
    -
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    Rising trigger event configuration bit of line 17

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    ◆ EXTI_RTSR_TR18_Pos

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    #define EXTI_RTSR_TR18_Pos   (18U)
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    - -
    -
    - -

    ◆ EXTI_RTSR_TR18_Msk

    - -
    -
    - - - - -
    #define EXTI_RTSR_TR18_Msk   (0x1UL << EXTI_RTSR_TR18_Pos)
    -
    -

    0x00040000

    - -
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    - -

    ◆ EXTI_RTSR_TR18

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    #define EXTI_RTSR_TR18   EXTI_RTSR_TR18_Msk
    -
    -

    Rising trigger event configuration bit of line 18

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    ◆ EXTI_RTSR_TR19_Pos

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    -
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    #define EXTI_RTSR_TR19_Pos   (19U)
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    - -
    -
    - -

    ◆ EXTI_RTSR_TR19_Msk

    - -
    -
    - - - - -
    #define EXTI_RTSR_TR19_Msk   (0x1UL << EXTI_RTSR_TR19_Pos)
    -
    -

    0x00080000

    - -
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    - -

    ◆ EXTI_RTSR_TR19

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    #define EXTI_RTSR_TR19   EXTI_RTSR_TR19_Msk
    -
    -

    Rising trigger event configuration bit of line 19

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    ◆ EXTI_RTSR_TR20_Pos

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    #define EXTI_RTSR_TR20_Pos   (20U)
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    - -
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    - -

    ◆ EXTI_RTSR_TR20_Msk

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    - - - - -
    #define EXTI_RTSR_TR20_Msk   (0x1UL << EXTI_RTSR_TR20_Pos)
    -
    -

    0x00100000

    - -
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    - -

    ◆ EXTI_RTSR_TR20

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    #define EXTI_RTSR_TR20   EXTI_RTSR_TR20_Msk
    -
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    Rising trigger event configuration bit of line 20

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    ◆ EXTI_RTSR_TR21_Pos

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    #define EXTI_RTSR_TR21_Pos   (21U)
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    - -
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    - -

    ◆ EXTI_RTSR_TR21_Msk

    - -
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    #define EXTI_RTSR_TR21_Msk   (0x1UL << EXTI_RTSR_TR21_Pos)
    -
    -

    0x00200000

    - -
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    ◆ EXTI_RTSR_TR21

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    #define EXTI_RTSR_TR21   EXTI_RTSR_TR21_Msk
    -
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    Rising trigger event configuration bit of line 21

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    ◆ EXTI_RTSR_TR22_Pos

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    #define EXTI_RTSR_TR22_Pos   (22U)
    -
    - -
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    - -

    ◆ EXTI_RTSR_TR22_Msk

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    #define EXTI_RTSR_TR22_Msk   (0x1UL << EXTI_RTSR_TR22_Pos)
    -
    -

    0x00400000

    - -
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    ◆ EXTI_RTSR_TR22

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    #define EXTI_RTSR_TR22   EXTI_RTSR_TR22_Msk
    -
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    Rising trigger event configuration bit of line 22

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    ◆ EXTI_FTSR_TR0_Pos

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    #define EXTI_FTSR_TR0_Pos   (0U)
    -
    - -
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    - -

    ◆ EXTI_FTSR_TR0_Msk

    - -
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    - - - - -
    #define EXTI_FTSR_TR0_Msk   (0x1UL << EXTI_FTSR_TR0_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ EXTI_FTSR_TR0

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    #define EXTI_FTSR_TR0   EXTI_FTSR_TR0_Msk
    -
    -

    Falling trigger event configuration bit of line 0

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    ◆ EXTI_FTSR_TR1_Pos

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    #define EXTI_FTSR_TR1_Pos   (1U)
    -
    - -
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    - -

    ◆ EXTI_FTSR_TR1_Msk

    - -
    -
    - - - - -
    #define EXTI_FTSR_TR1_Msk   (0x1UL << EXTI_FTSR_TR1_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ EXTI_FTSR_TR1

    - -
    -
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    #define EXTI_FTSR_TR1   EXTI_FTSR_TR1_Msk
    -
    -

    Falling trigger event configuration bit of line 1

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    ◆ EXTI_FTSR_TR2_Pos

    - -
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    #define EXTI_FTSR_TR2_Pos   (2U)
    -
    - -
    -
    - -

    ◆ EXTI_FTSR_TR2_Msk

    - -
    -
    - - - - -
    #define EXTI_FTSR_TR2_Msk   (0x1UL << EXTI_FTSR_TR2_Pos)
    -
    -

    0x00000004

    - -
    -
    - -

    ◆ EXTI_FTSR_TR2

    - -
    -
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    #define EXTI_FTSR_TR2   EXTI_FTSR_TR2_Msk
    -
    -

    Falling trigger event configuration bit of line 2

    - -
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    ◆ EXTI_FTSR_TR3_Pos

    - -
    -
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    #define EXTI_FTSR_TR3_Pos   (3U)
    -
    - -
    -
    - -

    ◆ EXTI_FTSR_TR3_Msk

    - -
    -
    - - - - -
    #define EXTI_FTSR_TR3_Msk   (0x1UL << EXTI_FTSR_TR3_Pos)
    -
    -

    0x00000008

    - -
    -
    - -

    ◆ EXTI_FTSR_TR3

    - -
    -
    - - - - -
    #define EXTI_FTSR_TR3   EXTI_FTSR_TR3_Msk
    -
    -

    Falling trigger event configuration bit of line 3

    - -
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    ◆ EXTI_FTSR_TR4_Pos

    - -
    -
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    #define EXTI_FTSR_TR4_Pos   (4U)
    -
    - -
    -
    - -

    ◆ EXTI_FTSR_TR4_Msk

    - -
    -
    - - - - -
    #define EXTI_FTSR_TR4_Msk   (0x1UL << EXTI_FTSR_TR4_Pos)
    -
    -

    0x00000010

    - -
    -
    - -

    ◆ EXTI_FTSR_TR4

    - -
    -
    - - - - -
    #define EXTI_FTSR_TR4   EXTI_FTSR_TR4_Msk
    -
    -

    Falling trigger event configuration bit of line 4

    - -
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    ◆ EXTI_FTSR_TR5_Pos

    - -
    -
    - - - - -
    #define EXTI_FTSR_TR5_Pos   (5U)
    -
    - -
    -
    - -

    ◆ EXTI_FTSR_TR5_Msk

    - -
    -
    - - - - -
    #define EXTI_FTSR_TR5_Msk   (0x1UL << EXTI_FTSR_TR5_Pos)
    -
    -

    0x00000020

    - -
    -
    - -

    ◆ EXTI_FTSR_TR5

    - -
    -
    - - - - -
    #define EXTI_FTSR_TR5   EXTI_FTSR_TR5_Msk
    -
    -

    Falling trigger event configuration bit of line 5

    - -
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    ◆ EXTI_FTSR_TR6_Pos

    - -
    -
    - - - - -
    #define EXTI_FTSR_TR6_Pos   (6U)
    -
    - -
    -
    - -

    ◆ EXTI_FTSR_TR6_Msk

    - -
    -
    - - - - -
    #define EXTI_FTSR_TR6_Msk   (0x1UL << EXTI_FTSR_TR6_Pos)
    -
    -

    0x00000040

    - -
    -
    - -

    ◆ EXTI_FTSR_TR6

    - -
    -
    - - - - -
    #define EXTI_FTSR_TR6   EXTI_FTSR_TR6_Msk
    -
    -

    Falling trigger event configuration bit of line 6

    - -
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    ◆ EXTI_FTSR_TR7_Pos

    - -
    -
    - - - - -
    #define EXTI_FTSR_TR7_Pos   (7U)
    -
    - -
    -
    - -

    ◆ EXTI_FTSR_TR7_Msk

    - -
    -
    - - - - -
    #define EXTI_FTSR_TR7_Msk   (0x1UL << EXTI_FTSR_TR7_Pos)
    -
    -

    0x00000080

    - -
    -
    - -

    ◆ EXTI_FTSR_TR7

    - -
    -
    - - - - -
    #define EXTI_FTSR_TR7   EXTI_FTSR_TR7_Msk
    -
    -

    Falling trigger event configuration bit of line 7

    - -
    -
    - -

    ◆ EXTI_FTSR_TR8_Pos

    - -
    -
    - - - - -
    #define EXTI_FTSR_TR8_Pos   (8U)
    -
    - -
    -
    - -

    ◆ EXTI_FTSR_TR8_Msk

    - -
    -
    - - - - -
    #define EXTI_FTSR_TR8_Msk   (0x1UL << EXTI_FTSR_TR8_Pos)
    -
    -

    0x00000100

    - -
    -
    - -

    ◆ EXTI_FTSR_TR8

    - -
    -
    - - - - -
    #define EXTI_FTSR_TR8   EXTI_FTSR_TR8_Msk
    -
    -

    Falling trigger event configuration bit of line 8

    - -
    -
    - -

    ◆ EXTI_FTSR_TR9_Pos

    - -
    -
    - - - - -
    #define EXTI_FTSR_TR9_Pos   (9U)
    -
    - -
    -
    - -

    ◆ EXTI_FTSR_TR9_Msk

    - -
    -
    - - - - -
    #define EXTI_FTSR_TR9_Msk   (0x1UL << EXTI_FTSR_TR9_Pos)
    -
    -

    0x00000200

    - -
    -
    - -

    ◆ EXTI_FTSR_TR9

    - -
    -
    - - - - -
    #define EXTI_FTSR_TR9   EXTI_FTSR_TR9_Msk
    -
    -

    Falling trigger event configuration bit of line 9

    - -
    -
    - -

    ◆ EXTI_FTSR_TR10_Pos

    - -
    -
    - - - - -
    #define EXTI_FTSR_TR10_Pos   (10U)
    -
    - -
    -
    - -

    ◆ EXTI_FTSR_TR10_Msk

    - -
    -
    - - - - -
    #define EXTI_FTSR_TR10_Msk   (0x1UL << EXTI_FTSR_TR10_Pos)
    -
    -

    0x00000400

    - -
    -
    - -

    ◆ EXTI_FTSR_TR10

    - -
    -
    - - - - -
    #define EXTI_FTSR_TR10   EXTI_FTSR_TR10_Msk
    -
    -

    Falling trigger event configuration bit of line 10

    - -
    -
    - -

    ◆ EXTI_FTSR_TR11_Pos

    - -
    -
    - - - - -
    #define EXTI_FTSR_TR11_Pos   (11U)
    -
    - -
    -
    - -

    ◆ EXTI_FTSR_TR11_Msk

    - -
    -
    - - - - -
    #define EXTI_FTSR_TR11_Msk   (0x1UL << EXTI_FTSR_TR11_Pos)
    -
    -

    0x00000800

    - -
    -
    - -

    ◆ EXTI_FTSR_TR11

    - -
    -
    - - - - -
    #define EXTI_FTSR_TR11   EXTI_FTSR_TR11_Msk
    -
    -

    Falling trigger event configuration bit of line 11

    - -
    -
    - -

    ◆ EXTI_FTSR_TR12_Pos

    - -
    -
    - - - - -
    #define EXTI_FTSR_TR12_Pos   (12U)
    -
    - -
    -
    - -

    ◆ EXTI_FTSR_TR12_Msk

    - -
    -
    - - - - -
    #define EXTI_FTSR_TR12_Msk   (0x1UL << EXTI_FTSR_TR12_Pos)
    -
    -

    0x00001000

    - -
    -
    - -

    ◆ EXTI_FTSR_TR12

    - -
    -
    - - - - -
    #define EXTI_FTSR_TR12   EXTI_FTSR_TR12_Msk
    -
    -

    Falling trigger event configuration bit of line 12

    - -
    -
    - -

    ◆ EXTI_FTSR_TR13_Pos

    - -
    -
    - - - - -
    #define EXTI_FTSR_TR13_Pos   (13U)
    -
    - -
    -
    - -

    ◆ EXTI_FTSR_TR13_Msk

    - -
    -
    - - - - -
    #define EXTI_FTSR_TR13_Msk   (0x1UL << EXTI_FTSR_TR13_Pos)
    -
    -

    0x00002000

    - -
    -
    - -

    ◆ EXTI_FTSR_TR13

    - -
    -
    - - - - -
    #define EXTI_FTSR_TR13   EXTI_FTSR_TR13_Msk
    -
    -

    Falling trigger event configuration bit of line 13

    - -
    -
    - -

    ◆ EXTI_FTSR_TR14_Pos

    - -
    -
    - - - - -
    #define EXTI_FTSR_TR14_Pos   (14U)
    -
    - -
    -
    - -

    ◆ EXTI_FTSR_TR14_Msk

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    -
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    #define EXTI_FTSR_TR14_Msk   (0x1UL << EXTI_FTSR_TR14_Pos)
    -
    -

    0x00004000

    - -
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    ◆ EXTI_FTSR_TR14

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    #define EXTI_FTSR_TR14   EXTI_FTSR_TR14_Msk
    -
    -

    Falling trigger event configuration bit of line 14

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    ◆ EXTI_FTSR_TR15_Pos

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    #define EXTI_FTSR_TR15_Pos   (15U)
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    - -
    -
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    ◆ EXTI_FTSR_TR15_Msk

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    #define EXTI_FTSR_TR15_Msk   (0x1UL << EXTI_FTSR_TR15_Pos)
    -
    -

    0x00008000

    - -
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    ◆ EXTI_FTSR_TR15

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    #define EXTI_FTSR_TR15   EXTI_FTSR_TR15_Msk
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    -

    Falling trigger event configuration bit of line 15

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    ◆ EXTI_FTSR_TR16_Pos

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    #define EXTI_FTSR_TR16_Pos   (16U)
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    - -
    -
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    ◆ EXTI_FTSR_TR16_Msk

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    #define EXTI_FTSR_TR16_Msk   (0x1UL << EXTI_FTSR_TR16_Pos)
    -
    -

    0x00010000

    - -
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    ◆ EXTI_FTSR_TR16

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    #define EXTI_FTSR_TR16   EXTI_FTSR_TR16_Msk
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    -

    Falling trigger event configuration bit of line 16

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    ◆ EXTI_FTSR_TR17_Pos

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    #define EXTI_FTSR_TR17_Pos   (17U)
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    - -
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    ◆ EXTI_FTSR_TR17_Msk

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    #define EXTI_FTSR_TR17_Msk   (0x1UL << EXTI_FTSR_TR17_Pos)
    -
    -

    0x00020000

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    ◆ EXTI_FTSR_TR17

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    #define EXTI_FTSR_TR17   EXTI_FTSR_TR17_Msk
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    Falling trigger event configuration bit of line 17

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    ◆ EXTI_FTSR_TR18_Pos

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    #define EXTI_FTSR_TR18_Pos   (18U)
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    - -
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    ◆ EXTI_FTSR_TR18_Msk

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    #define EXTI_FTSR_TR18_Msk   (0x1UL << EXTI_FTSR_TR18_Pos)
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    0x00040000

    - -
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    ◆ EXTI_FTSR_TR18

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    #define EXTI_FTSR_TR18   EXTI_FTSR_TR18_Msk
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    -

    Falling trigger event configuration bit of line 18

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    ◆ EXTI_FTSR_TR19_Pos

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    #define EXTI_FTSR_TR19_Pos   (19U)
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    - -
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    ◆ EXTI_FTSR_TR19_Msk

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    #define EXTI_FTSR_TR19_Msk   (0x1UL << EXTI_FTSR_TR19_Pos)
    -
    -

    0x00080000

    - -
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    ◆ EXTI_FTSR_TR19

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    #define EXTI_FTSR_TR19   EXTI_FTSR_TR19_Msk
    -
    -

    Falling trigger event configuration bit of line 19

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    ◆ EXTI_FTSR_TR20_Pos

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    #define EXTI_FTSR_TR20_Pos   (20U)
    -
    - -
    -
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    ◆ EXTI_FTSR_TR20_Msk

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    #define EXTI_FTSR_TR20_Msk   (0x1UL << EXTI_FTSR_TR20_Pos)
    -
    -

    0x00100000

    - -
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    - -

    ◆ EXTI_FTSR_TR20

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    #define EXTI_FTSR_TR20   EXTI_FTSR_TR20_Msk
    -
    -

    Falling trigger event configuration bit of line 20

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    ◆ EXTI_FTSR_TR21_Pos

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    #define EXTI_FTSR_TR21_Pos   (21U)
    -
    - -
    -
    - -

    ◆ EXTI_FTSR_TR21_Msk

    - -
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    #define EXTI_FTSR_TR21_Msk   (0x1UL << EXTI_FTSR_TR21_Pos)
    -
    -

    0x00200000

    - -
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    ◆ EXTI_FTSR_TR21

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    #define EXTI_FTSR_TR21   EXTI_FTSR_TR21_Msk
    -
    -

    Falling trigger event configuration bit of line 21

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    ◆ EXTI_FTSR_TR22_Pos

    - -
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    #define EXTI_FTSR_TR22_Pos   (22U)
    -
    - -
    -
    - -

    ◆ EXTI_FTSR_TR22_Msk

    - -
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    - - - - -
    #define EXTI_FTSR_TR22_Msk   (0x1UL << EXTI_FTSR_TR22_Pos)
    -
    -

    0x00400000

    - -
    -
    - -

    ◆ EXTI_FTSR_TR22

    - -
    -
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    #define EXTI_FTSR_TR22   EXTI_FTSR_TR22_Msk
    -
    -

    Falling trigger event configuration bit of line 22

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    - -

    ◆ EXTI_SWIER_SWIER0_Pos

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    #define EXTI_SWIER_SWIER0_Pos   (0U)
    -
    - -
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    - -

    ◆ EXTI_SWIER_SWIER0_Msk

    - -
    -
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    #define EXTI_SWIER_SWIER0_Msk   (0x1UL << EXTI_SWIER_SWIER0_Pos)
    -
    -

    0x00000001

    - -
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    - -

    ◆ EXTI_SWIER_SWIER0

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    #define EXTI_SWIER_SWIER0   EXTI_SWIER_SWIER0_Msk
    -
    -

    Software Interrupt on line 0

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    ◆ EXTI_SWIER_SWIER1_Pos

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    #define EXTI_SWIER_SWIER1_Pos   (1U)
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    - -
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    - -

    ◆ EXTI_SWIER_SWIER1_Msk

    - -
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    #define EXTI_SWIER_SWIER1_Msk   (0x1UL << EXTI_SWIER_SWIER1_Pos)
    -
    -

    0x00000002

    - -
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    - -

    ◆ EXTI_SWIER_SWIER1

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    #define EXTI_SWIER_SWIER1   EXTI_SWIER_SWIER1_Msk
    -
    -

    Software Interrupt on line 1

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    ◆ EXTI_SWIER_SWIER2_Pos

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    #define EXTI_SWIER_SWIER2_Pos   (2U)
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    - -
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    ◆ EXTI_SWIER_SWIER2_Msk

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    #define EXTI_SWIER_SWIER2_Msk   (0x1UL << EXTI_SWIER_SWIER2_Pos)
    -
    -

    0x00000004

    - -
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    - -

    ◆ EXTI_SWIER_SWIER2

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    #define EXTI_SWIER_SWIER2   EXTI_SWIER_SWIER2_Msk
    -
    -

    Software Interrupt on line 2

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    ◆ EXTI_SWIER_SWIER3_Pos

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    #define EXTI_SWIER_SWIER3_Pos   (3U)
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    - -
    -
    - -

    ◆ EXTI_SWIER_SWIER3_Msk

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    #define EXTI_SWIER_SWIER3_Msk   (0x1UL << EXTI_SWIER_SWIER3_Pos)
    -
    -

    0x00000008

    - -
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    - -

    ◆ EXTI_SWIER_SWIER3

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    #define EXTI_SWIER_SWIER3   EXTI_SWIER_SWIER3_Msk
    -
    -

    Software Interrupt on line 3

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    ◆ EXTI_SWIER_SWIER4_Pos

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    #define EXTI_SWIER_SWIER4_Pos   (4U)
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    - -
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    - -

    ◆ EXTI_SWIER_SWIER4_Msk

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    #define EXTI_SWIER_SWIER4_Msk   (0x1UL << EXTI_SWIER_SWIER4_Pos)
    -
    -

    0x00000010

    - -
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    - -

    ◆ EXTI_SWIER_SWIER4

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    #define EXTI_SWIER_SWIER4   EXTI_SWIER_SWIER4_Msk
    -
    -

    Software Interrupt on line 4

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    ◆ EXTI_SWIER_SWIER5_Pos

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    #define EXTI_SWIER_SWIER5_Pos   (5U)
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    - -
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    - -

    ◆ EXTI_SWIER_SWIER5_Msk

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    #define EXTI_SWIER_SWIER5_Msk   (0x1UL << EXTI_SWIER_SWIER5_Pos)
    -
    -

    0x00000020

    - -
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    - -

    ◆ EXTI_SWIER_SWIER5

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    #define EXTI_SWIER_SWIER5   EXTI_SWIER_SWIER5_Msk
    -
    -

    Software Interrupt on line 5

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    ◆ EXTI_SWIER_SWIER6_Pos

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    #define EXTI_SWIER_SWIER6_Pos   (6U)
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    - -
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    ◆ EXTI_SWIER_SWIER6_Msk

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    #define EXTI_SWIER_SWIER6_Msk   (0x1UL << EXTI_SWIER_SWIER6_Pos)
    -
    -

    0x00000040

    - -
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    - -

    ◆ EXTI_SWIER_SWIER6

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    #define EXTI_SWIER_SWIER6   EXTI_SWIER_SWIER6_Msk
    -
    -

    Software Interrupt on line 6

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    ◆ EXTI_SWIER_SWIER7_Pos

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    #define EXTI_SWIER_SWIER7_Pos   (7U)
    -
    - -
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    ◆ EXTI_SWIER_SWIER7_Msk

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    #define EXTI_SWIER_SWIER7_Msk   (0x1UL << EXTI_SWIER_SWIER7_Pos)
    -
    -

    0x00000080

    - -
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    - -

    ◆ EXTI_SWIER_SWIER7

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    #define EXTI_SWIER_SWIER7   EXTI_SWIER_SWIER7_Msk
    -
    -

    Software Interrupt on line 7

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    ◆ EXTI_SWIER_SWIER8_Pos

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    #define EXTI_SWIER_SWIER8_Pos   (8U)
    -
    - -
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    ◆ EXTI_SWIER_SWIER8_Msk

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    #define EXTI_SWIER_SWIER8_Msk   (0x1UL << EXTI_SWIER_SWIER8_Pos)
    -
    -

    0x00000100

    - -
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    - -

    ◆ EXTI_SWIER_SWIER8

    - -
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    #define EXTI_SWIER_SWIER8   EXTI_SWIER_SWIER8_Msk
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    -

    Software Interrupt on line 8

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    ◆ EXTI_SWIER_SWIER9_Pos

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    #define EXTI_SWIER_SWIER9_Pos   (9U)
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    - -
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    ◆ EXTI_SWIER_SWIER9_Msk

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    #define EXTI_SWIER_SWIER9_Msk   (0x1UL << EXTI_SWIER_SWIER9_Pos)
    -
    -

    0x00000200

    - -
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    - -

    ◆ EXTI_SWIER_SWIER9

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    #define EXTI_SWIER_SWIER9   EXTI_SWIER_SWIER9_Msk
    -
    -

    Software Interrupt on line 9

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    ◆ EXTI_SWIER_SWIER10_Pos

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    #define EXTI_SWIER_SWIER10_Pos   (10U)
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    - -
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    ◆ EXTI_SWIER_SWIER10_Msk

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    #define EXTI_SWIER_SWIER10_Msk   (0x1UL << EXTI_SWIER_SWIER10_Pos)
    -
    -

    0x00000400

    - -
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    ◆ EXTI_SWIER_SWIER10

    - -
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    #define EXTI_SWIER_SWIER10   EXTI_SWIER_SWIER10_Msk
    -
    -

    Software Interrupt on line 10

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    ◆ EXTI_SWIER_SWIER11_Pos

    - -
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    #define EXTI_SWIER_SWIER11_Pos   (11U)
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    - -
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    ◆ EXTI_SWIER_SWIER11_Msk

    - -
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    #define EXTI_SWIER_SWIER11_Msk   (0x1UL << EXTI_SWIER_SWIER11_Pos)
    -
    -

    0x00000800

    - -
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    - -

    ◆ EXTI_SWIER_SWIER11

    - -
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    #define EXTI_SWIER_SWIER11   EXTI_SWIER_SWIER11_Msk
    -
    -

    Software Interrupt on line 11

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    ◆ EXTI_SWIER_SWIER12_Pos

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    #define EXTI_SWIER_SWIER12_Pos   (12U)
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    - -
    -
    - -

    ◆ EXTI_SWIER_SWIER12_Msk

    - -
    -
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    #define EXTI_SWIER_SWIER12_Msk   (0x1UL << EXTI_SWIER_SWIER12_Pos)
    -
    -

    0x00001000

    - -
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    - -

    ◆ EXTI_SWIER_SWIER12

    - -
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    #define EXTI_SWIER_SWIER12   EXTI_SWIER_SWIER12_Msk
    -
    -

    Software Interrupt on line 12

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    ◆ EXTI_SWIER_SWIER13_Pos

    - -
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    #define EXTI_SWIER_SWIER13_Pos   (13U)
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    - -
    -
    - -

    ◆ EXTI_SWIER_SWIER13_Msk

    - -
    -
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    #define EXTI_SWIER_SWIER13_Msk   (0x1UL << EXTI_SWIER_SWIER13_Pos)
    -
    -

    0x00002000

    - -
    -
    - -

    ◆ EXTI_SWIER_SWIER13

    - -
    -
    - - - - -
    #define EXTI_SWIER_SWIER13   EXTI_SWIER_SWIER13_Msk
    -
    -

    Software Interrupt on line 13

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    - -

    ◆ EXTI_SWIER_SWIER14_Pos

    - -
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    - - - - -
    #define EXTI_SWIER_SWIER14_Pos   (14U)
    -
    - -
    -
    - -

    ◆ EXTI_SWIER_SWIER14_Msk

    - -
    -
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    #define EXTI_SWIER_SWIER14_Msk   (0x1UL << EXTI_SWIER_SWIER14_Pos)
    -
    -

    0x00004000

    - -
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    - -

    ◆ EXTI_SWIER_SWIER14

    - -
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    #define EXTI_SWIER_SWIER14   EXTI_SWIER_SWIER14_Msk
    -
    -

    Software Interrupt on line 14

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    - -

    ◆ EXTI_SWIER_SWIER15_Pos

    - -
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    - - - - -
    #define EXTI_SWIER_SWIER15_Pos   (15U)
    -
    - -
    -
    - -

    ◆ EXTI_SWIER_SWIER15_Msk

    - -
    -
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    #define EXTI_SWIER_SWIER15_Msk   (0x1UL << EXTI_SWIER_SWIER15_Pos)
    -
    -

    0x00008000

    - -
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    - -

    ◆ EXTI_SWIER_SWIER15

    - -
    -
    - - - - -
    #define EXTI_SWIER_SWIER15   EXTI_SWIER_SWIER15_Msk
    -
    -

    Software Interrupt on line 15

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    - -

    ◆ EXTI_SWIER_SWIER16_Pos

    - -
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    #define EXTI_SWIER_SWIER16_Pos   (16U)
    -
    - -
    -
    - -

    ◆ EXTI_SWIER_SWIER16_Msk

    - -
    -
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    #define EXTI_SWIER_SWIER16_Msk   (0x1UL << EXTI_SWIER_SWIER16_Pos)
    -
    -

    0x00010000

    - -
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    - -

    ◆ EXTI_SWIER_SWIER16

    - -
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    #define EXTI_SWIER_SWIER16   EXTI_SWIER_SWIER16_Msk
    -
    -

    Software Interrupt on line 16

    - -
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    - -

    ◆ EXTI_SWIER_SWIER17_Pos

    - -
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    - - - - -
    #define EXTI_SWIER_SWIER17_Pos   (17U)
    -
    - -
    -
    - -

    ◆ EXTI_SWIER_SWIER17_Msk

    - -
    -
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    #define EXTI_SWIER_SWIER17_Msk   (0x1UL << EXTI_SWIER_SWIER17_Pos)
    -
    -

    0x00020000

    - -
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    - -

    ◆ EXTI_SWIER_SWIER17

    - -
    -
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    #define EXTI_SWIER_SWIER17   EXTI_SWIER_SWIER17_Msk
    -
    -

    Software Interrupt on line 17

    - -
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    - -

    ◆ EXTI_SWIER_SWIER18_Pos

    - -
    -
    - - - - -
    #define EXTI_SWIER_SWIER18_Pos   (18U)
    -
    - -
    -
    - -

    ◆ EXTI_SWIER_SWIER18_Msk

    - -
    -
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    #define EXTI_SWIER_SWIER18_Msk   (0x1UL << EXTI_SWIER_SWIER18_Pos)
    -
    -

    0x00040000

    - -
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    - -

    ◆ EXTI_SWIER_SWIER18

    - -
    -
    - - - - -
    #define EXTI_SWIER_SWIER18   EXTI_SWIER_SWIER18_Msk
    -
    -

    Software Interrupt on line 18

    - -
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    - -

    ◆ EXTI_SWIER_SWIER19_Pos

    - -
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    - - - - -
    #define EXTI_SWIER_SWIER19_Pos   (19U)
    -
    - -
    -
    - -

    ◆ EXTI_SWIER_SWIER19_Msk

    - -
    -
    - - - - -
    #define EXTI_SWIER_SWIER19_Msk   (0x1UL << EXTI_SWIER_SWIER19_Pos)
    -
    -

    0x00080000

    - -
    -
    - -

    ◆ EXTI_SWIER_SWIER19

    - -
    -
    - - - - -
    #define EXTI_SWIER_SWIER19   EXTI_SWIER_SWIER19_Msk
    -
    -

    Software Interrupt on line 19

    - -
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    - -

    ◆ EXTI_SWIER_SWIER20_Pos

    - -
    -
    - - - - -
    #define EXTI_SWIER_SWIER20_Pos   (20U)
    -
    - -
    -
    - -

    ◆ EXTI_SWIER_SWIER20_Msk

    - -
    -
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    #define EXTI_SWIER_SWIER20_Msk   (0x1UL << EXTI_SWIER_SWIER20_Pos)
    -
    -

    0x00100000

    - -
    -
    - -

    ◆ EXTI_SWIER_SWIER20

    - -
    -
    - - - - -
    #define EXTI_SWIER_SWIER20   EXTI_SWIER_SWIER20_Msk
    -
    -

    Software Interrupt on line 20

    - -
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    - -

    ◆ EXTI_SWIER_SWIER21_Pos

    - -
    -
    - - - - -
    #define EXTI_SWIER_SWIER21_Pos   (21U)
    -
    - -
    -
    - -

    ◆ EXTI_SWIER_SWIER21_Msk

    - -
    -
    - - - - -
    #define EXTI_SWIER_SWIER21_Msk   (0x1UL << EXTI_SWIER_SWIER21_Pos)
    -
    -

    0x00200000

    - -
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    - -

    ◆ EXTI_SWIER_SWIER21

    - -
    -
    - - - - -
    #define EXTI_SWIER_SWIER21   EXTI_SWIER_SWIER21_Msk
    -
    -

    Software Interrupt on line 21

    - -
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    - -

    ◆ EXTI_SWIER_SWIER22_Pos

    - -
    -
    - - - - -
    #define EXTI_SWIER_SWIER22_Pos   (22U)
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    ◆ EXTI_SWIER_SWIER22_Msk

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    #define EXTI_SWIER_SWIER22_Msk   (0x1UL << EXTI_SWIER_SWIER22_Pos)
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    0x00400000

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    ◆ EXTI_SWIER_SWIER22

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    #define EXTI_SWIER_SWIER22   EXTI_SWIER_SWIER22_Msk
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    Software Interrupt on line 22

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    ◆ EXTI_PR_PR0_Pos

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    #define EXTI_PR_PR0_Pos   (0U)
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    ◆ EXTI_PR_PR0_Msk

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    #define EXTI_PR_PR0_Msk   (0x1UL << EXTI_PR_PR0_Pos)
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    0x00000001

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    ◆ EXTI_PR_PR0

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    #define EXTI_PR_PR0   EXTI_PR_PR0_Msk
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    Pending bit for line 0

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    ◆ EXTI_PR_PR1_Pos

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    #define EXTI_PR_PR1_Pos   (1U)
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    ◆ EXTI_PR_PR1_Msk

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    #define EXTI_PR_PR1_Msk   (0x1UL << EXTI_PR_PR1_Pos)
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    0x00000002

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    ◆ EXTI_PR_PR1

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    #define EXTI_PR_PR1   EXTI_PR_PR1_Msk
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    Pending bit for line 1

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    ◆ EXTI_PR_PR2_Pos

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    #define EXTI_PR_PR2_Pos   (2U)
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    ◆ EXTI_PR_PR2_Msk

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    #define EXTI_PR_PR2_Msk   (0x1UL << EXTI_PR_PR2_Pos)
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    0x00000004

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    ◆ EXTI_PR_PR2

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    #define EXTI_PR_PR2   EXTI_PR_PR2_Msk
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    Pending bit for line 2

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    ◆ EXTI_PR_PR3_Pos

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    #define EXTI_PR_PR3_Pos   (3U)
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    ◆ EXTI_PR_PR3_Msk

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    #define EXTI_PR_PR3_Msk   (0x1UL << EXTI_PR_PR3_Pos)
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    0x00000008

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    ◆ EXTI_PR_PR3

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    #define EXTI_PR_PR3   EXTI_PR_PR3_Msk
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    Pending bit for line 3

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    ◆ EXTI_PR_PR4_Pos

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    #define EXTI_PR_PR4_Pos   (4U)
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    ◆ EXTI_PR_PR4_Msk

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    #define EXTI_PR_PR4_Msk   (0x1UL << EXTI_PR_PR4_Pos)
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    0x00000010

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    ◆ EXTI_PR_PR4

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    #define EXTI_PR_PR4   EXTI_PR_PR4_Msk
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    Pending bit for line 4

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    ◆ EXTI_PR_PR5_Pos

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    #define EXTI_PR_PR5_Pos   (5U)
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    ◆ EXTI_PR_PR5_Msk

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    #define EXTI_PR_PR5_Msk   (0x1UL << EXTI_PR_PR5_Pos)
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    0x00000020

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    ◆ EXTI_PR_PR5

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    #define EXTI_PR_PR5   EXTI_PR_PR5_Msk
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    Pending bit for line 5

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    ◆ EXTI_PR_PR6_Pos

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    #define EXTI_PR_PR6_Pos   (6U)
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    ◆ EXTI_PR_PR6_Msk

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    #define EXTI_PR_PR6_Msk   (0x1UL << EXTI_PR_PR6_Pos)
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    0x00000040

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    ◆ EXTI_PR_PR6

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    #define EXTI_PR_PR6   EXTI_PR_PR6_Msk
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    Pending bit for line 6

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    ◆ EXTI_PR_PR7_Pos

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    #define EXTI_PR_PR7_Pos   (7U)
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    ◆ EXTI_PR_PR7_Msk

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    #define EXTI_PR_PR7_Msk   (0x1UL << EXTI_PR_PR7_Pos)
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    0x00000080

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    ◆ EXTI_PR_PR7

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    #define EXTI_PR_PR7   EXTI_PR_PR7_Msk
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    Pending bit for line 7

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    ◆ EXTI_PR_PR8_Pos

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    #define EXTI_PR_PR8_Pos   (8U)
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    ◆ EXTI_PR_PR8_Msk

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    #define EXTI_PR_PR8_Msk   (0x1UL << EXTI_PR_PR8_Pos)
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    0x00000100

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    ◆ EXTI_PR_PR8

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    #define EXTI_PR_PR8   EXTI_PR_PR8_Msk
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    Pending bit for line 8

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    ◆ EXTI_PR_PR9_Pos

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    #define EXTI_PR_PR9_Pos   (9U)
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    ◆ EXTI_PR_PR9_Msk

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    #define EXTI_PR_PR9_Msk   (0x1UL << EXTI_PR_PR9_Pos)
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    0x00000200

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    ◆ EXTI_PR_PR9

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    #define EXTI_PR_PR9   EXTI_PR_PR9_Msk
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    Pending bit for line 9

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    ◆ EXTI_PR_PR10_Pos

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    #define EXTI_PR_PR10_Pos   (10U)
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    ◆ EXTI_PR_PR10_Msk

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    #define EXTI_PR_PR10_Msk   (0x1UL << EXTI_PR_PR10_Pos)
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    0x00000400

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    ◆ EXTI_PR_PR10

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    #define EXTI_PR_PR10   EXTI_PR_PR10_Msk
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    Pending bit for line 10

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    ◆ EXTI_PR_PR11_Pos

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    #define EXTI_PR_PR11_Pos   (11U)
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    ◆ EXTI_PR_PR11_Msk

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    #define EXTI_PR_PR11_Msk   (0x1UL << EXTI_PR_PR11_Pos)
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    0x00000800

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    ◆ EXTI_PR_PR11

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    #define EXTI_PR_PR11   EXTI_PR_PR11_Msk
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    Pending bit for line 11

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    ◆ EXTI_PR_PR12_Pos

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    #define EXTI_PR_PR12_Pos   (12U)
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    ◆ EXTI_PR_PR12_Msk

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    #define EXTI_PR_PR12_Msk   (0x1UL << EXTI_PR_PR12_Pos)
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    0x00001000

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    ◆ EXTI_PR_PR12

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    #define EXTI_PR_PR12   EXTI_PR_PR12_Msk
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    Pending bit for line 12

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    ◆ EXTI_PR_PR13_Pos

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    #define EXTI_PR_PR13_Pos   (13U)
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    ◆ EXTI_PR_PR13_Msk

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    #define EXTI_PR_PR13_Msk   (0x1UL << EXTI_PR_PR13_Pos)
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    0x00002000

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    ◆ EXTI_PR_PR13

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    #define EXTI_PR_PR13   EXTI_PR_PR13_Msk
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    Pending bit for line 13

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    ◆ EXTI_PR_PR14_Pos

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    #define EXTI_PR_PR14_Pos   (14U)
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    ◆ EXTI_PR_PR14_Msk

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    #define EXTI_PR_PR14_Msk   (0x1UL << EXTI_PR_PR14_Pos)
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    0x00004000

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    ◆ EXTI_PR_PR14

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    #define EXTI_PR_PR14   EXTI_PR_PR14_Msk
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    Pending bit for line 14

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    ◆ EXTI_PR_PR15_Pos

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    #define EXTI_PR_PR15_Pos   (15U)
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    ◆ EXTI_PR_PR15_Msk

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    #define EXTI_PR_PR15_Msk   (0x1UL << EXTI_PR_PR15_Pos)
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    0x00008000

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    ◆ EXTI_PR_PR15

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    #define EXTI_PR_PR15   EXTI_PR_PR15_Msk
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    Pending bit for line 15

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    ◆ EXTI_PR_PR16_Pos

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    #define EXTI_PR_PR16_Pos   (16U)
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    ◆ EXTI_PR_PR16_Msk

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    #define EXTI_PR_PR16_Msk   (0x1UL << EXTI_PR_PR16_Pos)
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    0x00010000

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    ◆ EXTI_PR_PR16

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    #define EXTI_PR_PR16   EXTI_PR_PR16_Msk
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    Pending bit for line 16

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    ◆ EXTI_PR_PR17_Pos

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    #define EXTI_PR_PR17_Pos   (17U)
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    ◆ EXTI_PR_PR17_Msk

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    #define EXTI_PR_PR17_Msk   (0x1UL << EXTI_PR_PR17_Pos)
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    0x00020000

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    ◆ EXTI_PR_PR17

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    #define EXTI_PR_PR17   EXTI_PR_PR17_Msk
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    Pending bit for line 17

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    ◆ EXTI_PR_PR18_Pos

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    #define EXTI_PR_PR18_Pos   (18U)
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    ◆ EXTI_PR_PR18_Msk

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    #define EXTI_PR_PR18_Msk   (0x1UL << EXTI_PR_PR18_Pos)
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    0x00040000

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    ◆ EXTI_PR_PR18

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    #define EXTI_PR_PR18   EXTI_PR_PR18_Msk
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    Pending bit for line 18

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    ◆ EXTI_PR_PR19_Pos

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    #define EXTI_PR_PR19_Pos   (19U)
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    ◆ EXTI_PR_PR19_Msk

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    #define EXTI_PR_PR19_Msk   (0x1UL << EXTI_PR_PR19_Pos)
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    0x00080000

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    ◆ EXTI_PR_PR19

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    #define EXTI_PR_PR19   EXTI_PR_PR19_Msk
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    Pending bit for line 19

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    ◆ EXTI_PR_PR20_Pos

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    #define EXTI_PR_PR20_Pos   (20U)
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    ◆ EXTI_PR_PR20_Msk

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    #define EXTI_PR_PR20_Msk   (0x1UL << EXTI_PR_PR20_Pos)
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    0x00100000

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    ◆ EXTI_PR_PR20

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    #define EXTI_PR_PR20   EXTI_PR_PR20_Msk
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    Pending bit for line 20

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    ◆ EXTI_PR_PR21_Pos

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    #define EXTI_PR_PR21_Pos   (21U)
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    ◆ EXTI_PR_PR21_Msk

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    #define EXTI_PR_PR21_Msk   (0x1UL << EXTI_PR_PR21_Pos)
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    0x00200000

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    ◆ EXTI_PR_PR21

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    #define EXTI_PR_PR21   EXTI_PR_PR21_Msk
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    Pending bit for line 21

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    ◆ EXTI_PR_PR22_Pos

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    #define EXTI_PR_PR22_Pos   (22U)
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    ◆ EXTI_PR_PR22_Msk

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    #define EXTI_PR_PR22_Msk   (0x1UL << EXTI_PR_PR22_Pos)
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    0x00400000

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    ◆ EXTI_PR_PR22

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    #define EXTI_PR_PR22   EXTI_PR_PR22_Msk
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    Pending bit for line 22

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    ◆ FLASH_ACR_LATENCY_Pos

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    #define FLASH_ACR_LATENCY_Pos   (0U)
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    ◆ FLASH_ACR_LATENCY_Msk

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    #define FLASH_ACR_LATENCY_Msk   (0x7UL << FLASH_ACR_LATENCY_Pos)
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    0x00000007

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    ◆ FLASH_ACR_LATENCY

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    #define FLASH_ACR_LATENCY   FLASH_ACR_LATENCY_Msk
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    ◆ FLASH_ACR_LATENCY_0WS

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    #define FLASH_ACR_LATENCY_0WS   0x00000000U
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    ◆ FLASH_ACR_LATENCY_1WS

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    #define FLASH_ACR_LATENCY_1WS   0x00000001U
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    ◆ FLASH_ACR_LATENCY_2WS

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    #define FLASH_ACR_LATENCY_2WS   0x00000002U
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    ◆ FLASH_ACR_LATENCY_3WS

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    #define FLASH_ACR_LATENCY_3WS   0x00000003U
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    ◆ FLASH_ACR_LATENCY_4WS

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    #define FLASH_ACR_LATENCY_4WS   0x00000004U
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    ◆ FLASH_ACR_LATENCY_5WS

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    #define FLASH_ACR_LATENCY_5WS   0x00000005U
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    ◆ FLASH_ACR_LATENCY_6WS

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    #define FLASH_ACR_LATENCY_6WS   0x00000006U
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    ◆ FLASH_ACR_LATENCY_7WS

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    #define FLASH_ACR_LATENCY_7WS   0x00000007U
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    ◆ FLASH_ACR_PRFTEN_Pos

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    #define FLASH_ACR_PRFTEN_Pos   (8U)
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    ◆ FLASH_ACR_PRFTEN_Msk

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    #define FLASH_ACR_PRFTEN_Msk   (0x1UL << FLASH_ACR_PRFTEN_Pos)
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    0x00000100

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    ◆ FLASH_ACR_PRFTEN

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    #define FLASH_ACR_PRFTEN   FLASH_ACR_PRFTEN_Msk
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    ◆ FLASH_ACR_ICEN_Pos

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    #define FLASH_ACR_ICEN_Pos   (9U)
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    ◆ FLASH_ACR_ICEN_Msk

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    #define FLASH_ACR_ICEN_Msk   (0x1UL << FLASH_ACR_ICEN_Pos)
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    0x00000200

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    ◆ FLASH_ACR_ICEN

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    #define FLASH_ACR_ICEN   FLASH_ACR_ICEN_Msk
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    ◆ FLASH_ACR_DCEN_Pos

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    #define FLASH_ACR_DCEN_Pos   (10U)
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    ◆ FLASH_ACR_DCEN_Msk

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    #define FLASH_ACR_DCEN_Msk   (0x1UL << FLASH_ACR_DCEN_Pos)
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    0x00000400

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    ◆ FLASH_ACR_DCEN

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    #define FLASH_ACR_DCEN   FLASH_ACR_DCEN_Msk
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    ◆ FLASH_ACR_ICRST_Pos

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    #define FLASH_ACR_ICRST_Pos   (11U)
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    ◆ FLASH_ACR_ICRST_Msk

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    #define FLASH_ACR_ICRST_Msk   (0x1UL << FLASH_ACR_ICRST_Pos)
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    0x00000800

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    ◆ FLASH_ACR_ICRST

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    #define FLASH_ACR_ICRST   FLASH_ACR_ICRST_Msk
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    ◆ FLASH_ACR_DCRST_Pos

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    #define FLASH_ACR_DCRST_Pos   (12U)
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    ◆ FLASH_ACR_DCRST_Msk

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    #define FLASH_ACR_DCRST_Msk   (0x1UL << FLASH_ACR_DCRST_Pos)
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    0x00001000

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    ◆ FLASH_ACR_DCRST

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    #define FLASH_ACR_DCRST   FLASH_ACR_DCRST_Msk
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    ◆ FLASH_ACR_BYTE0_ADDRESS_Pos

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    #define FLASH_ACR_BYTE0_ADDRESS_Pos   (10U)
    -
    - -
    -
    - -

    ◆ FLASH_ACR_BYTE0_ADDRESS_Msk

    - -
    -
    - - - - -
    #define FLASH_ACR_BYTE0_ADDRESS_Msk   (0x10008FUL << FLASH_ACR_BYTE0_ADDRESS_Pos)
    -
    -

    0x40023C00

    - -
    -
    - -

    ◆ FLASH_ACR_BYTE0_ADDRESS

    - -
    -
    - - - - -
    #define FLASH_ACR_BYTE0_ADDRESS   FLASH_ACR_BYTE0_ADDRESS_Msk
    -
    - -
    -
    - -

    ◆ FLASH_ACR_BYTE2_ADDRESS_Pos

    - -
    -
    - - - - -
    #define FLASH_ACR_BYTE2_ADDRESS_Pos   (0U)
    -
    - -
    -
    - -

    ◆ FLASH_ACR_BYTE2_ADDRESS_Msk

    - -
    -
    - - - - -
    #define FLASH_ACR_BYTE2_ADDRESS_Msk   (0x40023C03UL << FLASH_ACR_BYTE2_ADDRESS_Pos)
    -
    -

    0x40023C03

    - -
    -
    - -

    ◆ FLASH_ACR_BYTE2_ADDRESS

    - -
    -
    - - - - -
    #define FLASH_ACR_BYTE2_ADDRESS   FLASH_ACR_BYTE2_ADDRESS_Msk
    -
    - -
    -
    - -

    ◆ FLASH_SR_EOP_Pos

    - -
    -
    - - - - -
    #define FLASH_SR_EOP_Pos   (0U)
    -
    - -
    -
    - -

    ◆ FLASH_SR_EOP_Msk

    - -
    -
    - - - - -
    #define FLASH_SR_EOP_Msk   (0x1UL << FLASH_SR_EOP_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ FLASH_SR_EOP

    - -
    -
    - - - - -
    #define FLASH_SR_EOP   FLASH_SR_EOP_Msk
    -
    - -
    -
    - -

    ◆ FLASH_SR_SOP_Pos

    - -
    -
    - - - - -
    #define FLASH_SR_SOP_Pos   (1U)
    -
    - -
    -
    - -

    ◆ FLASH_SR_SOP_Msk

    - -
    -
    - - - - -
    #define FLASH_SR_SOP_Msk   (0x1UL << FLASH_SR_SOP_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ FLASH_SR_SOP

    - -
    -
    - - - - -
    #define FLASH_SR_SOP   FLASH_SR_SOP_Msk
    -
    - -
    -
    - -

    ◆ FLASH_SR_WRPERR_Pos

    - -
    -
    - - - - -
    #define FLASH_SR_WRPERR_Pos   (4U)
    -
    - -
    -
    - -

    ◆ FLASH_SR_WRPERR_Msk

    - -
    -
    - - - - -
    #define FLASH_SR_WRPERR_Msk   (0x1UL << FLASH_SR_WRPERR_Pos)
    -
    -

    0x00000010

    - -
    -
    - -

    ◆ FLASH_SR_WRPERR

    - -
    -
    - - - - -
    #define FLASH_SR_WRPERR   FLASH_SR_WRPERR_Msk
    -
    - -
    -
    - -

    ◆ FLASH_SR_PGAERR_Pos

    - -
    -
    - - - - -
    #define FLASH_SR_PGAERR_Pos   (5U)
    -
    - -
    -
    - -

    ◆ FLASH_SR_PGAERR_Msk

    - -
    -
    - - - - -
    #define FLASH_SR_PGAERR_Msk   (0x1UL << FLASH_SR_PGAERR_Pos)
    -
    -

    0x00000020

    - -
    -
    - -

    ◆ FLASH_SR_PGAERR

    - -
    -
    - - - - -
    #define FLASH_SR_PGAERR   FLASH_SR_PGAERR_Msk
    -
    - -
    -
    - -

    ◆ FLASH_SR_PGPERR_Pos

    - -
    -
    - - - - -
    #define FLASH_SR_PGPERR_Pos   (6U)
    -
    - -
    -
    - -

    ◆ FLASH_SR_PGPERR_Msk

    - -
    -
    - - - - -
    #define FLASH_SR_PGPERR_Msk   (0x1UL << FLASH_SR_PGPERR_Pos)
    -
    -

    0x00000040

    - -
    -
    - -

    ◆ FLASH_SR_PGPERR

    - -
    -
    - - - - -
    #define FLASH_SR_PGPERR   FLASH_SR_PGPERR_Msk
    -
    - -
    -
    - -

    ◆ FLASH_SR_PGSERR_Pos

    - -
    -
    - - - - -
    #define FLASH_SR_PGSERR_Pos   (7U)
    -
    - -
    -
    - -

    ◆ FLASH_SR_PGSERR_Msk

    - -
    -
    - - - - -
    #define FLASH_SR_PGSERR_Msk   (0x1UL << FLASH_SR_PGSERR_Pos)
    -
    -

    0x00000080

    - -
    -
    - -

    ◆ FLASH_SR_PGSERR

    - -
    -
    - - - - -
    #define FLASH_SR_PGSERR   FLASH_SR_PGSERR_Msk
    -
    - -
    -
    - -

    ◆ FLASH_SR_BSY_Pos

    - -
    -
    - - - - -
    #define FLASH_SR_BSY_Pos   (16U)
    -
    - -
    -
    - -

    ◆ FLASH_SR_BSY_Msk

    - -
    -
    - - - - -
    #define FLASH_SR_BSY_Msk   (0x1UL << FLASH_SR_BSY_Pos)
    -
    -

    0x00010000

    - -
    -
    - -

    ◆ FLASH_SR_BSY

    - -
    -
    - - - - -
    #define FLASH_SR_BSY   FLASH_SR_BSY_Msk
    -
    - -
    -
    - -

    ◆ FLASH_CR_PG_Pos

    - -
    -
    - - - - -
    #define FLASH_CR_PG_Pos   (0U)
    -
    - -
    -
    - -

    ◆ FLASH_CR_PG_Msk

    - -
    -
    - - - - -
    #define FLASH_CR_PG_Msk   (0x1UL << FLASH_CR_PG_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ FLASH_CR_PG

    - -
    -
    - - - - -
    #define FLASH_CR_PG   FLASH_CR_PG_Msk
    -
    - -
    -
    - -

    ◆ FLASH_CR_SER_Pos

    - -
    -
    - - - - -
    #define FLASH_CR_SER_Pos   (1U)
    -
    - -
    -
    - -

    ◆ FLASH_CR_SER_Msk

    - -
    -
    - - - - -
    #define FLASH_CR_SER_Msk   (0x1UL << FLASH_CR_SER_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ FLASH_CR_SER

    - -
    -
    - - - - -
    #define FLASH_CR_SER   FLASH_CR_SER_Msk
    -
    - -
    -
    - -

    ◆ FLASH_CR_MER_Pos

    - -
    -
    - - - - -
    #define FLASH_CR_MER_Pos   (2U)
    -
    - -
    -
    - -

    ◆ FLASH_CR_MER_Msk

    - -
    -
    - - - - -
    #define FLASH_CR_MER_Msk   (0x1UL << FLASH_CR_MER_Pos)
    -
    -

    0x00000004

    - -
    -
    - -

    ◆ FLASH_CR_MER

    - -
    -
    - - - - -
    #define FLASH_CR_MER   FLASH_CR_MER_Msk
    -
    - -
    -
    - -

    ◆ FLASH_CR_SNB_Pos

    - -
    -
    - - - - -
    #define FLASH_CR_SNB_Pos   (3U)
    -
    - -
    -
    - -

    ◆ FLASH_CR_SNB_Msk

    - -
    -
    - - - - -
    #define FLASH_CR_SNB_Msk   (0x1FUL << FLASH_CR_SNB_Pos)
    -
    -

    0x000000F8

    - -
    -
    - -

    ◆ FLASH_CR_SNB

    - -
    -
    - - - - -
    #define FLASH_CR_SNB   FLASH_CR_SNB_Msk
    -
    - -
    -
    - -

    ◆ FLASH_CR_SNB_0

    - -
    -
    - - - - -
    #define FLASH_CR_SNB_0   (0x01UL << FLASH_CR_SNB_Pos)
    -
    -

    0x00000008

    - -
    -
    - -

    ◆ FLASH_CR_SNB_1

    - -
    -
    - - - - -
    #define FLASH_CR_SNB_1   (0x02UL << FLASH_CR_SNB_Pos)
    -
    -

    0x00000010

    - -
    -
    - -

    ◆ FLASH_CR_SNB_2

    - -
    -
    - - - - -
    #define FLASH_CR_SNB_2   (0x04UL << FLASH_CR_SNB_Pos)
    -
    -

    0x00000020

    - -
    -
    - -

    ◆ FLASH_CR_SNB_3

    - -
    -
    - - - - -
    #define FLASH_CR_SNB_3   (0x08UL << FLASH_CR_SNB_Pos)
    -
    -

    0x00000040

    - -
    -
    - -

    ◆ FLASH_CR_SNB_4

    - -
    -
    - - - - -
    #define FLASH_CR_SNB_4   (0x10UL << FLASH_CR_SNB_Pos)
    -
    -

    0x00000080

    - -
    -
    - -

    ◆ FLASH_CR_PSIZE_Pos

    - -
    -
    - - - - -
    #define FLASH_CR_PSIZE_Pos   (8U)
    -
    - -
    -
    - -

    ◆ FLASH_CR_PSIZE_Msk

    - -
    -
    - - - - -
    #define FLASH_CR_PSIZE_Msk   (0x3UL << FLASH_CR_PSIZE_Pos)
    -
    -

    0x00000300

    - -
    -
    - -

    ◆ FLASH_CR_PSIZE

    - -
    -
    - - - - -
    #define FLASH_CR_PSIZE   FLASH_CR_PSIZE_Msk
    -
    - -
    -
    - -

    ◆ FLASH_CR_PSIZE_0

    - -
    -
    - - - - -
    #define FLASH_CR_PSIZE_0   (0x1UL << FLASH_CR_PSIZE_Pos)
    -
    -

    0x00000100

    - -
    -
    - -

    ◆ FLASH_CR_PSIZE_1

    - -
    -
    - - - - -
    #define FLASH_CR_PSIZE_1   (0x2UL << FLASH_CR_PSIZE_Pos)
    -
    -

    0x00000200

    - -
    -
    - -

    ◆ FLASH_CR_STRT_Pos

    - -
    -
    - - - - -
    #define FLASH_CR_STRT_Pos   (16U)
    -
    - -
    -
    - -

    ◆ FLASH_CR_STRT_Msk

    - -
    -
    - - - - -
    #define FLASH_CR_STRT_Msk   (0x1UL << FLASH_CR_STRT_Pos)
    -
    -

    0x00010000

    - -
    -
    - -

    ◆ FLASH_CR_STRT

    - -
    -
    - - - - -
    #define FLASH_CR_STRT   FLASH_CR_STRT_Msk
    -
    - -
    -
    - -

    ◆ FLASH_CR_EOPIE_Pos

    - -
    -
    - - - - -
    #define FLASH_CR_EOPIE_Pos   (24U)
    -
    - -
    -
    - -

    ◆ FLASH_CR_EOPIE_Msk

    - -
    -
    - - - - -
    #define FLASH_CR_EOPIE_Msk   (0x1UL << FLASH_CR_EOPIE_Pos)
    -
    -

    0x01000000

    - -
    -
    - -

    ◆ FLASH_CR_EOPIE

    - -
    -
    - - - - -
    #define FLASH_CR_EOPIE   FLASH_CR_EOPIE_Msk
    -
    - -
    -
    - -

    ◆ FLASH_CR_ERRIE_Pos

    - -
    -
    - - - - -
    #define FLASH_CR_ERRIE_Pos   (25U)
    -
    - -
    -
    - -

    ◆ FLASH_CR_ERRIE_Msk

    - -
    -
    - - - - -
    #define FLASH_CR_ERRIE_Msk   (0x1UL << FLASH_CR_ERRIE_Pos)
    -
    - -
    -
    - -

    ◆ FLASH_CR_ERRIE

    - -
    -
    - - - - -
    #define FLASH_CR_ERRIE   FLASH_CR_ERRIE_Msk
    -
    - -
    -
    - -

    ◆ FLASH_CR_LOCK_Pos

    - -
    -
    - - - - -
    #define FLASH_CR_LOCK_Pos   (31U)
    -
    - -
    -
    - -

    ◆ FLASH_CR_LOCK_Msk

    - -
    -
    - - - - -
    #define FLASH_CR_LOCK_Msk   (0x1UL << FLASH_CR_LOCK_Pos)
    -
    -

    0x80000000

    - -
    -
    - -

    ◆ FLASH_CR_LOCK

    - -
    -
    - - - - -
    #define FLASH_CR_LOCK   FLASH_CR_LOCK_Msk
    -
    - -
    -
    - -

    ◆ FLASH_OPTCR_OPTLOCK_Pos

    - -
    -
    - - - - -
    #define FLASH_OPTCR_OPTLOCK_Pos   (0U)
    -
    - -
    -
    - -

    ◆ FLASH_OPTCR_OPTLOCK_Msk

    - -
    -
    - - - - -
    #define FLASH_OPTCR_OPTLOCK_Msk   (0x1UL << FLASH_OPTCR_OPTLOCK_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ FLASH_OPTCR_OPTLOCK

    - -
    -
    - - - - -
    #define FLASH_OPTCR_OPTLOCK   FLASH_OPTCR_OPTLOCK_Msk
    -
    - -
    -
    - -

    ◆ FLASH_OPTCR_OPTSTRT_Pos

    - -
    -
    - - - - -
    #define FLASH_OPTCR_OPTSTRT_Pos   (1U)
    -
    - -
    -
    - -

    ◆ FLASH_OPTCR_OPTSTRT_Msk

    - -
    -
    - - - - -
    #define FLASH_OPTCR_OPTSTRT_Msk   (0x1UL << FLASH_OPTCR_OPTSTRT_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ FLASH_OPTCR_OPTSTRT

    - -
    -
    - - - - -
    #define FLASH_OPTCR_OPTSTRT   FLASH_OPTCR_OPTSTRT_Msk
    -
    - -
    -
    - -

    ◆ FLASH_OPTCR_BOR_LEV_0

    - -
    -
    - - - - -
    #define FLASH_OPTCR_BOR_LEV_0   0x00000004U
    -
    - -
    -
    - -

    ◆ FLASH_OPTCR_BOR_LEV_1

    - -
    -
    - - - - -
    #define FLASH_OPTCR_BOR_LEV_1   0x00000008U
    -
    - -
    -
    - -

    ◆ FLASH_OPTCR_BOR_LEV_Pos

    - -
    -
    - - - - -
    #define FLASH_OPTCR_BOR_LEV_Pos   (2U)
    -
    - -
    -
    - -

    ◆ FLASH_OPTCR_BOR_LEV_Msk

    - -
    -
    - - - - -
    #define FLASH_OPTCR_BOR_LEV_Msk   (0x3UL << FLASH_OPTCR_BOR_LEV_Pos)
    -
    -

    0x0000000C

    - -
    -
    - -

    ◆ FLASH_OPTCR_BOR_LEV

    - -
    -
    - - - - -
    #define FLASH_OPTCR_BOR_LEV   FLASH_OPTCR_BOR_LEV_Msk
    -
    - -
    -
    - -

    ◆ FLASH_OPTCR_WDG_SW_Pos

    - -
    -
    - - - - -
    #define FLASH_OPTCR_WDG_SW_Pos   (5U)
    -
    - -
    -
    - -

    ◆ FLASH_OPTCR_WDG_SW_Msk

    - -
    -
    - - - - -
    #define FLASH_OPTCR_WDG_SW_Msk   (0x1UL << FLASH_OPTCR_WDG_SW_Pos)
    -
    -

    0x00000020

    - -
    -
    - -

    ◆ FLASH_OPTCR_WDG_SW

    - -
    -
    - - - - -
    #define FLASH_OPTCR_WDG_SW   FLASH_OPTCR_WDG_SW_Msk
    -
    - -
    -
    - -

    ◆ FLASH_OPTCR_nRST_STOP_Pos

    - -
    -
    - - - - -
    #define FLASH_OPTCR_nRST_STOP_Pos   (6U)
    -
    - -
    -
    - -

    ◆ FLASH_OPTCR_nRST_STOP_Msk

    - -
    -
    - - - - -
    #define FLASH_OPTCR_nRST_STOP_Msk   (0x1UL << FLASH_OPTCR_nRST_STOP_Pos)
    -
    -

    0x00000040

    - -
    -
    - -

    ◆ FLASH_OPTCR_nRST_STOP

    - -
    -
    - - - - -
    #define FLASH_OPTCR_nRST_STOP   FLASH_OPTCR_nRST_STOP_Msk
    -
    - -
    -
    - -

    ◆ FLASH_OPTCR_nRST_STDBY_Pos

    - -
    -
    - - - - -
    #define FLASH_OPTCR_nRST_STDBY_Pos   (7U)
    -
    - -
    -
    - -

    ◆ FLASH_OPTCR_nRST_STDBY_Msk

    - -
    -
    - - - - -
    #define FLASH_OPTCR_nRST_STDBY_Msk   (0x1UL << FLASH_OPTCR_nRST_STDBY_Pos)
    -
    -

    0x00000080

    - -
    -
    - -

    ◆ FLASH_OPTCR_nRST_STDBY

    - -
    -
    - - - - -
    #define FLASH_OPTCR_nRST_STDBY   FLASH_OPTCR_nRST_STDBY_Msk
    -
    - -
    -
    - -

    ◆ FLASH_OPTCR_RDP_Pos

    - -
    -
    - - - - -
    #define FLASH_OPTCR_RDP_Pos   (8U)
    -
    - -
    -
    - -

    ◆ FLASH_OPTCR_RDP_Msk

    - -
    -
    - - - - -
    #define FLASH_OPTCR_RDP_Msk   (0xFFUL << FLASH_OPTCR_RDP_Pos)
    -
    -

    0x0000FF00

    - -
    -
    - -

    ◆ FLASH_OPTCR_RDP

    - -
    -
    - - - - -
    #define FLASH_OPTCR_RDP   FLASH_OPTCR_RDP_Msk
    -
    - -
    -
    - -

    ◆ FLASH_OPTCR_RDP_0

    - -
    -
    - - - - -
    #define FLASH_OPTCR_RDP_0   (0x01UL << FLASH_OPTCR_RDP_Pos)
    -
    -

    0x00000100

    - -
    -
    - -

    ◆ FLASH_OPTCR_RDP_1

    - -
    -
    - - - - -
    #define FLASH_OPTCR_RDP_1   (0x02UL << FLASH_OPTCR_RDP_Pos)
    -
    -

    0x00000200

    - -
    -
    - -

    ◆ FLASH_OPTCR_RDP_2

    - -
    -
    - - - - -
    #define FLASH_OPTCR_RDP_2   (0x04UL << FLASH_OPTCR_RDP_Pos)
    -
    -

    0x00000400

    - -
    -
    - -

    ◆ FLASH_OPTCR_RDP_3

    - -
    -
    - - - - -
    #define FLASH_OPTCR_RDP_3   (0x08UL << FLASH_OPTCR_RDP_Pos)
    -
    -

    0x00000800

    - -
    -
    - -

    ◆ FLASH_OPTCR_RDP_4

    - -
    -
    - - - - -
    #define FLASH_OPTCR_RDP_4   (0x10UL << FLASH_OPTCR_RDP_Pos)
    -
    -

    0x00001000

    - -
    -
    - -

    ◆ FLASH_OPTCR_RDP_5

    - -
    -
    - - - - -
    #define FLASH_OPTCR_RDP_5   (0x20UL << FLASH_OPTCR_RDP_Pos)
    -
    -

    0x00002000

    - -
    -
    - -

    ◆ FLASH_OPTCR_RDP_6

    - -
    -
    - - - - -
    #define FLASH_OPTCR_RDP_6   (0x40UL << FLASH_OPTCR_RDP_Pos)
    -
    -

    0x00004000

    - -
    -
    - -

    ◆ FLASH_OPTCR_RDP_7

    - -
    -
    - - - - -
    #define FLASH_OPTCR_RDP_7   (0x80UL << FLASH_OPTCR_RDP_Pos)
    -
    -

    0x00008000

    - -
    -
    - -

    ◆ FLASH_OPTCR_nWRP_Pos

    - -
    -
    - - - - -
    #define FLASH_OPTCR_nWRP_Pos   (16U)
    -
    - -
    -
    - -

    ◆ FLASH_OPTCR_nWRP_Msk

    - -
    -
    - - - - -
    #define FLASH_OPTCR_nWRP_Msk   (0xFFFUL << FLASH_OPTCR_nWRP_Pos)
    -
    -

    0x0FFF0000

    - -
    -
    - -

    ◆ FLASH_OPTCR_nWRP

    - -
    -
    - - - - -
    #define FLASH_OPTCR_nWRP   FLASH_OPTCR_nWRP_Msk
    -
    - -
    -
    - -

    ◆ FLASH_OPTCR_nWRP_0

    - -
    -
    - - - - -
    #define FLASH_OPTCR_nWRP_0   0x00010000U
    -
    - -
    -
    - -

    ◆ FLASH_OPTCR_nWRP_1

    - -
    -
    - - - - -
    #define FLASH_OPTCR_nWRP_1   0x00020000U
    -
    - -
    -
    - -

    ◆ FLASH_OPTCR_nWRP_2

    - -
    -
    - - - - -
    #define FLASH_OPTCR_nWRP_2   0x00040000U
    -
    - -
    -
    - -

    ◆ FLASH_OPTCR_nWRP_3

    - -
    -
    - - - - -
    #define FLASH_OPTCR_nWRP_3   0x00080000U
    -
    - -
    -
    - -

    ◆ FLASH_OPTCR_nWRP_4

    - -
    -
    - - - - -
    #define FLASH_OPTCR_nWRP_4   0x00100000U
    -
    - -
    -
    - -

    ◆ FLASH_OPTCR_nWRP_5

    - -
    -
    - - - - -
    #define FLASH_OPTCR_nWRP_5   0x00200000U
    -
    - -
    -
    - -

    ◆ FLASH_OPTCR_nWRP_6

    - -
    -
    - - - - -
    #define FLASH_OPTCR_nWRP_6   0x00400000U
    -
    - -
    -
    - -

    ◆ FLASH_OPTCR_nWRP_7

    - -
    -
    - - - - -
    #define FLASH_OPTCR_nWRP_7   0x00800000U
    -
    - -
    -
    - -

    ◆ FLASH_OPTCR_nWRP_8

    - -
    -
    - - - - -
    #define FLASH_OPTCR_nWRP_8   0x01000000U
    -
    - -
    -
    - -

    ◆ FLASH_OPTCR_nWRP_9

    - -
    -
    - - - - -
    #define FLASH_OPTCR_nWRP_9   0x02000000U
    -
    - -
    -
    - -

    ◆ FLASH_OPTCR_nWRP_10

    - -
    -
    - - - - -
    #define FLASH_OPTCR_nWRP_10   0x04000000U
    -
    - -
    -
    - -

    ◆ FLASH_OPTCR_nWRP_11

    - -
    -
    - - - - -
    #define FLASH_OPTCR_nWRP_11   0x08000000U
    -
    - -
    -
    - -

    ◆ FLASH_OPTCR1_nWRP_Pos

    - -
    -
    - - - - -
    #define FLASH_OPTCR1_nWRP_Pos   (16U)
    -
    - -
    -
    - -

    ◆ FLASH_OPTCR1_nWRP_Msk

    - -
    -
    - - - - -
    #define FLASH_OPTCR1_nWRP_Msk   (0xFFFUL << FLASH_OPTCR1_nWRP_Pos)
    -
    -

    0x0FFF0000

    - -
    -
    - -

    ◆ FLASH_OPTCR1_nWRP

    - -
    -
    - - - - -
    #define FLASH_OPTCR1_nWRP   FLASH_OPTCR1_nWRP_Msk
    -
    - -
    -
    - -

    ◆ FLASH_OPTCR1_nWRP_0

    - -
    -
    - - - - -
    #define FLASH_OPTCR1_nWRP_0   (0x001UL << FLASH_OPTCR1_nWRP_Pos)
    -
    -

    0x00010000

    - -
    -
    - -

    ◆ FLASH_OPTCR1_nWRP_1

    - -
    -
    - - - - -
    #define FLASH_OPTCR1_nWRP_1   (0x002UL << FLASH_OPTCR1_nWRP_Pos)
    -
    -

    0x00020000

    - -
    -
    - -

    ◆ FLASH_OPTCR1_nWRP_2

    - -
    -
    - - - - -
    #define FLASH_OPTCR1_nWRP_2   (0x004UL << FLASH_OPTCR1_nWRP_Pos)
    -
    -

    0x00040000

    - -
    -
    - -

    ◆ FLASH_OPTCR1_nWRP_3

    - -
    -
    - - - - -
    #define FLASH_OPTCR1_nWRP_3   (0x008UL << FLASH_OPTCR1_nWRP_Pos)
    -
    -

    0x00080000

    - -
    -
    - -

    ◆ FLASH_OPTCR1_nWRP_4

    - -
    -
    - - - - -
    #define FLASH_OPTCR1_nWRP_4   (0x010UL << FLASH_OPTCR1_nWRP_Pos)
    -
    -

    0x00100000

    - -
    -
    - -

    ◆ FLASH_OPTCR1_nWRP_5

    - -
    -
    - - - - -
    #define FLASH_OPTCR1_nWRP_5   (0x020UL << FLASH_OPTCR1_nWRP_Pos)
    -
    -

    0x00200000

    - -
    -
    - -

    ◆ FLASH_OPTCR1_nWRP_6

    - -
    -
    - - - - -
    #define FLASH_OPTCR1_nWRP_6   (0x040UL << FLASH_OPTCR1_nWRP_Pos)
    -
    -

    0x00400000

    - -
    -
    - -

    ◆ FLASH_OPTCR1_nWRP_7

    - -
    -
    - - - - -
    #define FLASH_OPTCR1_nWRP_7   (0x080UL << FLASH_OPTCR1_nWRP_Pos)
    -
    -

    0x00800000

    - -
    -
    - -

    ◆ FLASH_OPTCR1_nWRP_8

    - -
    -
    - - - - -
    #define FLASH_OPTCR1_nWRP_8   (0x100UL << FLASH_OPTCR1_nWRP_Pos)
    -
    -

    0x01000000

    - -
    -
    - -

    ◆ FLASH_OPTCR1_nWRP_9

    - -
    -
    - - - - -
    #define FLASH_OPTCR1_nWRP_9   (0x200UL << FLASH_OPTCR1_nWRP_Pos)
    -
    -

    0x02000000

    - -
    -
    - -

    ◆ FLASH_OPTCR1_nWRP_10

    - -
    -
    - - - - -
    #define FLASH_OPTCR1_nWRP_10   (0x400UL << FLASH_OPTCR1_nWRP_Pos)
    -
    -

    0x04000000

    - -
    -
    - -

    ◆ FLASH_OPTCR1_nWRP_11

    - -
    -
    - - - - -
    #define FLASH_OPTCR1_nWRP_11   (0x800UL << FLASH_OPTCR1_nWRP_Pos)
    -
    -

    0x08000000

    - -
    -
    - -

    ◆ FSMC_BCR1_MBKEN_Pos

    - -
    -
    - - - - -
    #define FSMC_BCR1_MBKEN_Pos   (0U)
    -
    - -
    -
    - -

    ◆ FSMC_BCR1_MBKEN_Msk

    - -
    -
    - - - - -
    #define FSMC_BCR1_MBKEN_Msk   (0x1UL << FSMC_BCR1_MBKEN_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ FSMC_BCR1_MBKEN

    - -
    -
    - - - - -
    #define FSMC_BCR1_MBKEN   FSMC_BCR1_MBKEN_Msk
    -
    -

    Memory bank enable bit
    -

    - -
    -
    - -

    ◆ FSMC_BCR1_MUXEN_Pos

    - -
    -
    - - - - -
    #define FSMC_BCR1_MUXEN_Pos   (1U)
    -
    - -
    -
    - -

    ◆ FSMC_BCR1_MUXEN_Msk

    - -
    -
    - - - - -
    #define FSMC_BCR1_MUXEN_Msk   (0x1UL << FSMC_BCR1_MUXEN_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ FSMC_BCR1_MUXEN

    - -
    -
    - - - - -
    #define FSMC_BCR1_MUXEN   FSMC_BCR1_MUXEN_Msk
    -
    -

    Address/data multiplexing enable bit
    -

    - -
    -
    - -

    ◆ FSMC_BCR1_MTYP_Pos

    - -
    -
    - - - - -
    #define FSMC_BCR1_MTYP_Pos   (2U)
    -
    - -
    -
    - -

    ◆ FSMC_BCR1_MTYP_Msk

    - -
    -
    - - - - -
    #define FSMC_BCR1_MTYP_Msk   (0x3UL << FSMC_BCR1_MTYP_Pos)
    -
    -

    0x0000000C

    - -
    -
    - -

    ◆ FSMC_BCR1_MTYP

    - -
    -
    - - - - -
    #define FSMC_BCR1_MTYP   FSMC_BCR1_MTYP_Msk
    -
    -

    MTYP[1:0] bits (Memory type)
    -

    - -
    -
    - -

    ◆ FSMC_BCR1_MTYP_0

    - -
    -
    - - - - -
    #define FSMC_BCR1_MTYP_0   (0x1UL << FSMC_BCR1_MTYP_Pos)
    -
    -

    0x00000004

    - -
    -
    - -

    ◆ FSMC_BCR1_MTYP_1

    - -
    -
    - - - - -
    #define FSMC_BCR1_MTYP_1   (0x2UL << FSMC_BCR1_MTYP_Pos)
    -
    -

    0x00000008

    - -
    -
    - -

    ◆ FSMC_BCR1_MWID_Pos

    - -
    -
    - - - - -
    #define FSMC_BCR1_MWID_Pos   (4U)
    -
    - -
    -
    - -

    ◆ FSMC_BCR1_MWID_Msk

    - -
    -
    - - - - -
    #define FSMC_BCR1_MWID_Msk   (0x3UL << FSMC_BCR1_MWID_Pos)
    -
    -

    0x00000030

    - -
    -
    - -

    ◆ FSMC_BCR1_MWID

    - -
    -
    - - - - -
    #define FSMC_BCR1_MWID   FSMC_BCR1_MWID_Msk
    -
    -

    MWID[1:0] bits (Memory data bus width)

    - -
    -
    - -

    ◆ FSMC_BCR1_MWID_0

    - -
    -
    - - - - -
    #define FSMC_BCR1_MWID_0   (0x1UL << FSMC_BCR1_MWID_Pos)
    -
    -

    0x00000010

    - -
    -
    - -

    ◆ FSMC_BCR1_MWID_1

    - -
    -
    - - - - -
    #define FSMC_BCR1_MWID_1   (0x2UL << FSMC_BCR1_MWID_Pos)
    -
    -

    0x00000020

    - -
    -
    - -

    ◆ FSMC_BCR1_FACCEN_Pos

    - -
    -
    - - - - -
    #define FSMC_BCR1_FACCEN_Pos   (6U)
    -
    - -
    -
    - -

    ◆ FSMC_BCR1_FACCEN_Msk

    - -
    -
    - - - - -
    #define FSMC_BCR1_FACCEN_Msk   (0x1UL << FSMC_BCR1_FACCEN_Pos)
    -
    -

    0x00000040

    - -
    -
    - -

    ◆ FSMC_BCR1_FACCEN

    - -
    -
    - - - - -
    #define FSMC_BCR1_FACCEN   FSMC_BCR1_FACCEN_Msk
    -
    -

    Flash access enable
    -

    - -
    -
    - -

    ◆ FSMC_BCR1_BURSTEN_Pos

    - -
    -
    - - - - -
    #define FSMC_BCR1_BURSTEN_Pos   (8U)
    -
    - -
    -
    - -

    ◆ FSMC_BCR1_BURSTEN_Msk

    - -
    -
    - - - - -
    #define FSMC_BCR1_BURSTEN_Msk   (0x1UL << FSMC_BCR1_BURSTEN_Pos)
    -
    -

    0x00000100

    - -
    -
    - -

    ◆ FSMC_BCR1_BURSTEN

    - -
    -
    - - - - -
    #define FSMC_BCR1_BURSTEN   FSMC_BCR1_BURSTEN_Msk
    -
    -

    Burst enable bit
    -

    - -
    -
    - -

    ◆ FSMC_BCR1_WAITPOL_Pos

    - -
    -
    - - - - -
    #define FSMC_BCR1_WAITPOL_Pos   (9U)
    -
    - -
    -
    - -

    ◆ FSMC_BCR1_WAITPOL_Msk

    - -
    -
    - - - - -
    #define FSMC_BCR1_WAITPOL_Msk   (0x1UL << FSMC_BCR1_WAITPOL_Pos)
    -
    -

    0x00000200

    - -
    -
    - -

    ◆ FSMC_BCR1_WAITPOL

    - -
    -
    - - - - -
    #define FSMC_BCR1_WAITPOL   FSMC_BCR1_WAITPOL_Msk
    -
    -

    Wait signal polarity bit
    -

    - -
    -
    - -

    ◆ FSMC_BCR1_WRAPMOD_Pos

    - -
    -
    - - - - -
    #define FSMC_BCR1_WRAPMOD_Pos   (10U)
    -
    - -
    -
    - -

    ◆ FSMC_BCR1_WRAPMOD_Msk

    - -
    -
    - - - - -
    #define FSMC_BCR1_WRAPMOD_Msk   (0x1UL << FSMC_BCR1_WRAPMOD_Pos)
    -
    -

    0x00000400

    - -
    -
    - -

    ◆ FSMC_BCR1_WRAPMOD

    - -
    -
    - - - - -
    #define FSMC_BCR1_WRAPMOD   FSMC_BCR1_WRAPMOD_Msk
    -
    -

    Wrapped burst mode support
    -

    - -
    -
    - -

    ◆ FSMC_BCR1_WAITCFG_Pos

    - -
    -
    - - - - -
    #define FSMC_BCR1_WAITCFG_Pos   (11U)
    -
    - -
    -
    - -

    ◆ FSMC_BCR1_WAITCFG_Msk

    - -
    -
    - - - - -
    #define FSMC_BCR1_WAITCFG_Msk   (0x1UL << FSMC_BCR1_WAITCFG_Pos)
    -
    -

    0x00000800

    - -
    -
    - -

    ◆ FSMC_BCR1_WAITCFG

    - -
    -
    - - - - -
    #define FSMC_BCR1_WAITCFG   FSMC_BCR1_WAITCFG_Msk
    -
    -

    Wait timing configuration
    -

    - -
    -
    - -

    ◆ FSMC_BCR1_WREN_Pos

    - -
    -
    - - - - -
    #define FSMC_BCR1_WREN_Pos   (12U)
    -
    - -
    -
    - -

    ◆ FSMC_BCR1_WREN_Msk

    - -
    -
    - - - - -
    #define FSMC_BCR1_WREN_Msk   (0x1UL << FSMC_BCR1_WREN_Pos)
    -
    -

    0x00001000

    - -
    -
    - -

    ◆ FSMC_BCR1_WREN

    - -
    -
    - - - - -
    #define FSMC_BCR1_WREN   FSMC_BCR1_WREN_Msk
    -
    -

    Write enable bit
    -

    - -
    -
    - -

    ◆ FSMC_BCR1_WAITEN_Pos

    - -
    -
    - - - - -
    #define FSMC_BCR1_WAITEN_Pos   (13U)
    -
    - -
    -
    - -

    ◆ FSMC_BCR1_WAITEN_Msk

    - -
    -
    - - - - -
    #define FSMC_BCR1_WAITEN_Msk   (0x1UL << FSMC_BCR1_WAITEN_Pos)
    -
    -

    0x00002000

    - -
    -
    - -

    ◆ FSMC_BCR1_WAITEN

    - -
    -
    - - - - -
    #define FSMC_BCR1_WAITEN   FSMC_BCR1_WAITEN_Msk
    -
    -

    Wait enable bit
    -

    - -
    -
    - -

    ◆ FSMC_BCR1_EXTMOD_Pos

    - -
    -
    - - - - -
    #define FSMC_BCR1_EXTMOD_Pos   (14U)
    -
    - -
    -
    - -

    ◆ FSMC_BCR1_EXTMOD_Msk

    - -
    -
    - - - - -
    #define FSMC_BCR1_EXTMOD_Msk   (0x1UL << FSMC_BCR1_EXTMOD_Pos)
    -
    -

    0x00004000

    - -
    -
    - -

    ◆ FSMC_BCR1_EXTMOD

    - -
    -
    - - - - -
    #define FSMC_BCR1_EXTMOD   FSMC_BCR1_EXTMOD_Msk
    -
    -

    Extended mode enable
    -

    - -
    -
    - -

    ◆ FSMC_BCR1_ASYNCWAIT_Pos

    - -
    -
    - - - - -
    #define FSMC_BCR1_ASYNCWAIT_Pos   (15U)
    -
    - -
    -
    - -

    ◆ FSMC_BCR1_ASYNCWAIT_Msk

    - -
    -
    - - - - -
    #define FSMC_BCR1_ASYNCWAIT_Msk   (0x1UL << FSMC_BCR1_ASYNCWAIT_Pos)
    -
    -

    0x00008000

    - -
    -
    - -

    ◆ FSMC_BCR1_ASYNCWAIT

    - -
    -
    - - - - -
    #define FSMC_BCR1_ASYNCWAIT   FSMC_BCR1_ASYNCWAIT_Msk
    -
    -

    Asynchronous wait
    -

    - -
    -
    - -

    ◆ FSMC_BCR1_CPSIZE_Pos

    - -
    -
    - - - - -
    #define FSMC_BCR1_CPSIZE_Pos   (16U)
    -
    - -
    -
    - -

    ◆ FSMC_BCR1_CPSIZE_Msk

    - -
    -
    - - - - -
    #define FSMC_BCR1_CPSIZE_Msk   (0x7UL << FSMC_BCR1_CPSIZE_Pos)
    -
    -

    0x00070000

    - -
    -
    - -

    ◆ FSMC_BCR1_CPSIZE

    - -
    -
    - - - - -
    #define FSMC_BCR1_CPSIZE   FSMC_BCR1_CPSIZE_Msk
    -
    -

    CRAM page size

    - -
    -
    - -

    ◆ FSMC_BCR1_CPSIZE_0

    - -
    -
    - - - - -
    #define FSMC_BCR1_CPSIZE_0   (0x1UL << FSMC_BCR1_CPSIZE_Pos)
    -
    -

    0x00010000

    - -
    -
    - -

    ◆ FSMC_BCR1_CPSIZE_1

    - -
    -
    - - - - -
    #define FSMC_BCR1_CPSIZE_1   (0x2UL << FSMC_BCR1_CPSIZE_Pos)
    -
    -

    0x00020000

    - -
    -
    - -

    ◆ FSMC_BCR1_CPSIZE_2

    - -
    -
    - - - - -
    #define FSMC_BCR1_CPSIZE_2   (0x4UL << FSMC_BCR1_CPSIZE_Pos)
    -
    -

    0x00040000

    - -
    -
    - -

    ◆ FSMC_BCR1_CBURSTRW_Pos

    - -
    -
    - - - - -
    #define FSMC_BCR1_CBURSTRW_Pos   (19U)
    -
    - -
    -
    - -

    ◆ FSMC_BCR1_CBURSTRW_Msk

    - -
    -
    - - - - -
    #define FSMC_BCR1_CBURSTRW_Msk   (0x1UL << FSMC_BCR1_CBURSTRW_Pos)
    -
    -

    0x00080000

    - -
    -
    - -

    ◆ FSMC_BCR1_CBURSTRW

    - -
    -
    - - - - -
    #define FSMC_BCR1_CBURSTRW   FSMC_BCR1_CBURSTRW_Msk
    -
    -

    Write burst enable
    -

    - -
    -
    - -

    ◆ FSMC_BCR2_MBKEN_Pos

    - -
    -
    - - - - -
    #define FSMC_BCR2_MBKEN_Pos   (0U)
    -
    - -
    -
    - -

    ◆ FSMC_BCR2_MBKEN_Msk

    - -
    -
    - - - - -
    #define FSMC_BCR2_MBKEN_Msk   (0x1UL << FSMC_BCR2_MBKEN_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ FSMC_BCR2_MBKEN

    - -
    -
    - - - - -
    #define FSMC_BCR2_MBKEN   FSMC_BCR2_MBKEN_Msk
    -
    -

    Memory bank enable bit
    -

    - -
    -
    - -

    ◆ FSMC_BCR2_MUXEN_Pos

    - -
    -
    - - - - -
    #define FSMC_BCR2_MUXEN_Pos   (1U)
    -
    - -
    -
    - -

    ◆ FSMC_BCR2_MUXEN_Msk

    - -
    -
    - - - - -
    #define FSMC_BCR2_MUXEN_Msk   (0x1UL << FSMC_BCR2_MUXEN_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ FSMC_BCR2_MUXEN

    - -
    -
    - - - - -
    #define FSMC_BCR2_MUXEN   FSMC_BCR2_MUXEN_Msk
    -
    -

    Address/data multiplexing enable bit
    -

    - -
    -
    - -

    ◆ FSMC_BCR2_MTYP_Pos

    - -
    -
    - - - - -
    #define FSMC_BCR2_MTYP_Pos   (2U)
    -
    - -
    -
    - -

    ◆ FSMC_BCR2_MTYP_Msk

    - -
    -
    - - - - -
    #define FSMC_BCR2_MTYP_Msk   (0x3UL << FSMC_BCR2_MTYP_Pos)
    -
    -

    0x0000000C

    - -
    -
    - -

    ◆ FSMC_BCR2_MTYP

    - -
    -
    - - - - -
    #define FSMC_BCR2_MTYP   FSMC_BCR2_MTYP_Msk
    -
    -

    MTYP[1:0] bits (Memory type)
    -

    - -
    -
    - -

    ◆ FSMC_BCR2_MTYP_0

    - -
    -
    - - - - -
    #define FSMC_BCR2_MTYP_0   (0x1UL << FSMC_BCR2_MTYP_Pos)
    -
    -

    0x00000004

    - -
    -
    - -

    ◆ FSMC_BCR2_MTYP_1

    - -
    -
    - - - - -
    #define FSMC_BCR2_MTYP_1   (0x2UL << FSMC_BCR2_MTYP_Pos)
    -
    -

    0x00000008

    - -
    -
    - -

    ◆ FSMC_BCR2_MWID_Pos

    - -
    -
    - - - - -
    #define FSMC_BCR2_MWID_Pos   (4U)
    -
    - -
    -
    - -

    ◆ FSMC_BCR2_MWID_Msk

    - -
    -
    - - - - -
    #define FSMC_BCR2_MWID_Msk   (0x3UL << FSMC_BCR2_MWID_Pos)
    -
    -

    0x00000030

    - -
    -
    - -

    ◆ FSMC_BCR2_MWID

    - -
    -
    - - - - -
    #define FSMC_BCR2_MWID   FSMC_BCR2_MWID_Msk
    -
    -

    MWID[1:0] bits (Memory data bus width)

    - -
    -
    - -

    ◆ FSMC_BCR2_MWID_0

    - -
    -
    - - - - -
    #define FSMC_BCR2_MWID_0   (0x1UL << FSMC_BCR2_MWID_Pos)
    -
    -

    0x00000010

    - -
    -
    - -

    ◆ FSMC_BCR2_MWID_1

    - -
    -
    - - - - -
    #define FSMC_BCR2_MWID_1   (0x2UL << FSMC_BCR2_MWID_Pos)
    -
    -

    0x00000020

    - -
    -
    - -

    ◆ FSMC_BCR2_FACCEN_Pos

    - -
    -
    - - - - -
    #define FSMC_BCR2_FACCEN_Pos   (6U)
    -
    - -
    -
    - -

    ◆ FSMC_BCR2_FACCEN_Msk

    - -
    -
    - - - - -
    #define FSMC_BCR2_FACCEN_Msk   (0x1UL << FSMC_BCR2_FACCEN_Pos)
    -
    -

    0x00000040

    - -
    -
    - -

    ◆ FSMC_BCR2_FACCEN

    - -
    -
    - - - - -
    #define FSMC_BCR2_FACCEN   FSMC_BCR2_FACCEN_Msk
    -
    -

    Flash access enable
    -

    - -
    -
    - -

    ◆ FSMC_BCR2_BURSTEN_Pos

    - -
    -
    - - - - -
    #define FSMC_BCR2_BURSTEN_Pos   (8U)
    -
    - -
    -
    - -

    ◆ FSMC_BCR2_BURSTEN_Msk

    - -
    -
    - - - - -
    #define FSMC_BCR2_BURSTEN_Msk   (0x1UL << FSMC_BCR2_BURSTEN_Pos)
    -
    -

    0x00000100

    - -
    -
    - -

    ◆ FSMC_BCR2_BURSTEN

    - -
    -
    - - - - -
    #define FSMC_BCR2_BURSTEN   FSMC_BCR2_BURSTEN_Msk
    -
    -

    Burst enable bit
    -

    - -
    -
    - -

    ◆ FSMC_BCR2_WAITPOL_Pos

    - -
    -
    - - - - -
    #define FSMC_BCR2_WAITPOL_Pos   (9U)
    -
    - -
    -
    - -

    ◆ FSMC_BCR2_WAITPOL_Msk

    - -
    -
    - - - - -
    #define FSMC_BCR2_WAITPOL_Msk   (0x1UL << FSMC_BCR2_WAITPOL_Pos)
    -
    -

    0x00000200

    - -
    -
    - -

    ◆ FSMC_BCR2_WAITPOL

    - -
    -
    - - - - -
    #define FSMC_BCR2_WAITPOL   FSMC_BCR2_WAITPOL_Msk
    -
    -

    Wait signal polarity bit
    -

    - -
    -
    - -

    ◆ FSMC_BCR2_WRAPMOD_Pos

    - -
    -
    - - - - -
    #define FSMC_BCR2_WRAPMOD_Pos   (10U)
    -
    - -
    -
    - -

    ◆ FSMC_BCR2_WRAPMOD_Msk

    - -
    -
    - - - - -
    #define FSMC_BCR2_WRAPMOD_Msk   (0x1UL << FSMC_BCR2_WRAPMOD_Pos)
    -
    -

    0x00000400

    - -
    -
    - -

    ◆ FSMC_BCR2_WRAPMOD

    - -
    -
    - - - - -
    #define FSMC_BCR2_WRAPMOD   FSMC_BCR2_WRAPMOD_Msk
    -
    -

    Wrapped burst mode support
    -

    - -
    -
    - -

    ◆ FSMC_BCR2_WAITCFG_Pos

    - -
    -
    - - - - -
    #define FSMC_BCR2_WAITCFG_Pos   (11U)
    -
    - -
    -
    - -

    ◆ FSMC_BCR2_WAITCFG_Msk

    - -
    -
    - - - - -
    #define FSMC_BCR2_WAITCFG_Msk   (0x1UL << FSMC_BCR2_WAITCFG_Pos)
    -
    -

    0x00000800

    - -
    -
    - -

    ◆ FSMC_BCR2_WAITCFG

    - -
    -
    - - - - -
    #define FSMC_BCR2_WAITCFG   FSMC_BCR2_WAITCFG_Msk
    -
    -

    Wait timing configuration
    -

    - -
    -
    - -

    ◆ FSMC_BCR2_WREN_Pos

    - -
    -
    - - - - -
    #define FSMC_BCR2_WREN_Pos   (12U)
    -
    - -
    -
    - -

    ◆ FSMC_BCR2_WREN_Msk

    - -
    -
    - - - - -
    #define FSMC_BCR2_WREN_Msk   (0x1UL << FSMC_BCR2_WREN_Pos)
    -
    -

    0x00001000

    - -
    -
    - -

    ◆ FSMC_BCR2_WREN

    - -
    -
    - - - - -
    #define FSMC_BCR2_WREN   FSMC_BCR2_WREN_Msk
    -
    -

    Write enable bit
    -

    - -
    -
    - -

    ◆ FSMC_BCR2_WAITEN_Pos

    - -
    -
    - - - - -
    #define FSMC_BCR2_WAITEN_Pos   (13U)
    -
    - -
    -
    - -

    ◆ FSMC_BCR2_WAITEN_Msk

    - -
    -
    - - - - -
    #define FSMC_BCR2_WAITEN_Msk   (0x1UL << FSMC_BCR2_WAITEN_Pos)
    -
    -

    0x00002000

    - -
    -
    - -

    ◆ FSMC_BCR2_WAITEN

    - -
    -
    - - - - -
    #define FSMC_BCR2_WAITEN   FSMC_BCR2_WAITEN_Msk
    -
    -

    Wait enable bit
    -

    - -
    -
    - -

    ◆ FSMC_BCR2_EXTMOD_Pos

    - -
    -
    - - - - -
    #define FSMC_BCR2_EXTMOD_Pos   (14U)
    -
    - -
    -
    - -

    ◆ FSMC_BCR2_EXTMOD_Msk

    - -
    -
    - - - - -
    #define FSMC_BCR2_EXTMOD_Msk   (0x1UL << FSMC_BCR2_EXTMOD_Pos)
    -
    -

    0x00004000

    - -
    -
    - -

    ◆ FSMC_BCR2_EXTMOD

    - -
    -
    - - - - -
    #define FSMC_BCR2_EXTMOD   FSMC_BCR2_EXTMOD_Msk
    -
    -

    Extended mode enable
    -

    - -
    -
    - -

    ◆ FSMC_BCR2_ASYNCWAIT_Pos

    - -
    -
    - - - - -
    #define FSMC_BCR2_ASYNCWAIT_Pos   (15U)
    -
    - -
    -
    - -

    ◆ FSMC_BCR2_ASYNCWAIT_Msk

    - -
    -
    - - - - -
    #define FSMC_BCR2_ASYNCWAIT_Msk   (0x1UL << FSMC_BCR2_ASYNCWAIT_Pos)
    -
    -

    0x00008000

    - -
    -
    - -

    ◆ FSMC_BCR2_ASYNCWAIT

    - -
    -
    - - - - -
    #define FSMC_BCR2_ASYNCWAIT   FSMC_BCR2_ASYNCWAIT_Msk
    -
    -

    Asynchronous wait
    -

    - -
    -
    - -

    ◆ FSMC_BCR2_CPSIZE_Pos

    - -
    -
    - - - - -
    #define FSMC_BCR2_CPSIZE_Pos   (16U)
    -
    - -
    -
    - -

    ◆ FSMC_BCR2_CPSIZE_Msk

    - -
    -
    - - - - -
    #define FSMC_BCR2_CPSIZE_Msk   (0x7UL << FSMC_BCR2_CPSIZE_Pos)
    -
    -

    0x00070000

    - -
    -
    - -

    ◆ FSMC_BCR2_CPSIZE

    - -
    -
    - - - - -
    #define FSMC_BCR2_CPSIZE   FSMC_BCR2_CPSIZE_Msk
    -
    -

    CRAM page size

    - -
    -
    - -

    ◆ FSMC_BCR2_CPSIZE_0

    - -
    -
    - - - - -
    #define FSMC_BCR2_CPSIZE_0   (0x1UL << FSMC_BCR2_CPSIZE_Pos)
    -
    -

    0x00010000

    - -
    -
    - -

    ◆ FSMC_BCR2_CPSIZE_1

    - -
    -
    - - - - -
    #define FSMC_BCR2_CPSIZE_1   (0x2UL << FSMC_BCR2_CPSIZE_Pos)
    -
    -

    0x00020000

    - -
    -
    - -

    ◆ FSMC_BCR2_CPSIZE_2

    - -
    -
    - - - - -
    #define FSMC_BCR2_CPSIZE_2   (0x4UL << FSMC_BCR2_CPSIZE_Pos)
    -
    -

    0x00040000

    - -
    -
    - -

    ◆ FSMC_BCR2_CBURSTRW_Pos

    - -
    -
    - - - - -
    #define FSMC_BCR2_CBURSTRW_Pos   (19U)
    -
    - -
    -
    - -

    ◆ FSMC_BCR2_CBURSTRW_Msk

    - -
    -
    - - - - -
    #define FSMC_BCR2_CBURSTRW_Msk   (0x1UL << FSMC_BCR2_CBURSTRW_Pos)
    -
    -

    0x00080000

    - -
    -
    - -

    ◆ FSMC_BCR2_CBURSTRW

    - -
    -
    - - - - -
    #define FSMC_BCR2_CBURSTRW   FSMC_BCR2_CBURSTRW_Msk
    -
    -

    Write burst enable
    -

    - -
    -
    - -

    ◆ FSMC_BCR3_MBKEN_Pos

    - -
    -
    - - - - -
    #define FSMC_BCR3_MBKEN_Pos   (0U)
    -
    - -
    -
    - -

    ◆ FSMC_BCR3_MBKEN_Msk

    - -
    -
    - - - - -
    #define FSMC_BCR3_MBKEN_Msk   (0x1UL << FSMC_BCR3_MBKEN_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ FSMC_BCR3_MBKEN

    - -
    -
    - - - - -
    #define FSMC_BCR3_MBKEN   FSMC_BCR3_MBKEN_Msk
    -
    -

    Memory bank enable bit
    -

    - -
    -
    - -

    ◆ FSMC_BCR3_MUXEN_Pos

    - -
    -
    - - - - -
    #define FSMC_BCR3_MUXEN_Pos   (1U)
    -
    - -
    -
    - -

    ◆ FSMC_BCR3_MUXEN_Msk

    - -
    -
    - - - - -
    #define FSMC_BCR3_MUXEN_Msk   (0x1UL << FSMC_BCR3_MUXEN_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ FSMC_BCR3_MUXEN

    - -
    -
    - - - - -
    #define FSMC_BCR3_MUXEN   FSMC_BCR3_MUXEN_Msk
    -
    -

    Address/data multiplexing enable bit
    -

    - -
    -
    - -

    ◆ FSMC_BCR3_MTYP_Pos

    - -
    -
    - - - - -
    #define FSMC_BCR3_MTYP_Pos   (2U)
    -
    - -
    -
    - -

    ◆ FSMC_BCR3_MTYP_Msk

    - -
    -
    - - - - -
    #define FSMC_BCR3_MTYP_Msk   (0x3UL << FSMC_BCR3_MTYP_Pos)
    -
    -

    0x0000000C

    - -
    -
    - -

    ◆ FSMC_BCR3_MTYP

    - -
    -
    - - - - -
    #define FSMC_BCR3_MTYP   FSMC_BCR3_MTYP_Msk
    -
    -

    MTYP[1:0] bits (Memory type)
    -

    - -
    -
    - -

    ◆ FSMC_BCR3_MTYP_0

    - -
    -
    - - - - -
    #define FSMC_BCR3_MTYP_0   (0x1UL << FSMC_BCR3_MTYP_Pos)
    -
    -

    0x00000004

    - -
    -
    - -

    ◆ FSMC_BCR3_MTYP_1

    - -
    -
    - - - - -
    #define FSMC_BCR3_MTYP_1   (0x2UL << FSMC_BCR3_MTYP_Pos)
    -
    -

    0x00000008

    - -
    -
    - -

    ◆ FSMC_BCR3_MWID_Pos

    - -
    -
    - - - - -
    #define FSMC_BCR3_MWID_Pos   (4U)
    -
    - -
    -
    - -

    ◆ FSMC_BCR3_MWID_Msk

    - -
    -
    - - - - -
    #define FSMC_BCR3_MWID_Msk   (0x3UL << FSMC_BCR3_MWID_Pos)
    -
    -

    0x00000030

    - -
    -
    - -

    ◆ FSMC_BCR3_MWID

    - -
    -
    - - - - -
    #define FSMC_BCR3_MWID   FSMC_BCR3_MWID_Msk
    -
    -

    MWID[1:0] bits (Memory data bus width)

    - -
    -
    - -

    ◆ FSMC_BCR3_MWID_0

    - -
    -
    - - - - -
    #define FSMC_BCR3_MWID_0   (0x1UL << FSMC_BCR3_MWID_Pos)
    -
    -

    0x00000010

    - -
    -
    - -

    ◆ FSMC_BCR3_MWID_1

    - -
    -
    - - - - -
    #define FSMC_BCR3_MWID_1   (0x2UL << FSMC_BCR3_MWID_Pos)
    -
    -

    0x00000020

    - -
    -
    - -

    ◆ FSMC_BCR3_FACCEN_Pos

    - -
    -
    - - - - -
    #define FSMC_BCR3_FACCEN_Pos   (6U)
    -
    - -
    -
    - -

    ◆ FSMC_BCR3_FACCEN_Msk

    - -
    -
    - - - - -
    #define FSMC_BCR3_FACCEN_Msk   (0x1UL << FSMC_BCR3_FACCEN_Pos)
    -
    -

    0x00000040

    - -
    -
    - -

    ◆ FSMC_BCR3_FACCEN

    - -
    -
    - - - - -
    #define FSMC_BCR3_FACCEN   FSMC_BCR3_FACCEN_Msk
    -
    -

    Flash access enable
    -

    - -
    -
    - -

    ◆ FSMC_BCR3_BURSTEN_Pos

    - -
    -
    - - - - -
    #define FSMC_BCR3_BURSTEN_Pos   (8U)
    -
    - -
    -
    - -

    ◆ FSMC_BCR3_BURSTEN_Msk

    - -
    -
    - - - - -
    #define FSMC_BCR3_BURSTEN_Msk   (0x1UL << FSMC_BCR3_BURSTEN_Pos)
    -
    -

    0x00000100

    - -
    -
    - -

    ◆ FSMC_BCR3_BURSTEN

    - -
    -
    - - - - -
    #define FSMC_BCR3_BURSTEN   FSMC_BCR3_BURSTEN_Msk
    -
    -

    Burst enable bit
    -

    - -
    -
    - -

    ◆ FSMC_BCR3_WAITPOL_Pos

    - -
    -
    - - - - -
    #define FSMC_BCR3_WAITPOL_Pos   (9U)
    -
    - -
    -
    - -

    ◆ FSMC_BCR3_WAITPOL_Msk

    - -
    -
    - - - - -
    #define FSMC_BCR3_WAITPOL_Msk   (0x1UL << FSMC_BCR3_WAITPOL_Pos)
    -
    -

    0x00000200

    - -
    -
    - -

    ◆ FSMC_BCR3_WAITPOL

    - -
    -
    - - - - -
    #define FSMC_BCR3_WAITPOL   FSMC_BCR3_WAITPOL_Msk
    -
    -

    Wait signal polarity bit
    -

    - -
    -
    - -

    ◆ FSMC_BCR3_WRAPMOD_Pos

    - -
    -
    - - - - -
    #define FSMC_BCR3_WRAPMOD_Pos   (10U)
    -
    - -
    -
    - -

    ◆ FSMC_BCR3_WRAPMOD_Msk

    - -
    -
    - - - - -
    #define FSMC_BCR3_WRAPMOD_Msk   (0x1UL << FSMC_BCR3_WRAPMOD_Pos)
    -
    -

    0x00000400

    - -
    -
    - -

    ◆ FSMC_BCR3_WRAPMOD

    - -
    -
    - - - - -
    #define FSMC_BCR3_WRAPMOD   FSMC_BCR3_WRAPMOD_Msk
    -
    -

    Wrapped burst mode support
    -

    - -
    -
    - -

    ◆ FSMC_BCR3_WAITCFG_Pos

    - -
    -
    - - - - -
    #define FSMC_BCR3_WAITCFG_Pos   (11U)
    -
    - -
    -
    - -

    ◆ FSMC_BCR3_WAITCFG_Msk

    - -
    -
    - - - - -
    #define FSMC_BCR3_WAITCFG_Msk   (0x1UL << FSMC_BCR3_WAITCFG_Pos)
    -
    -

    0x00000800

    - -
    -
    - -

    ◆ FSMC_BCR3_WAITCFG

    - -
    -
    - - - - -
    #define FSMC_BCR3_WAITCFG   FSMC_BCR3_WAITCFG_Msk
    -
    -

    Wait timing configuration
    -

    - -
    -
    - -

    ◆ FSMC_BCR3_WREN_Pos

    - -
    -
    - - - - -
    #define FSMC_BCR3_WREN_Pos   (12U)
    -
    - -
    -
    - -

    ◆ FSMC_BCR3_WREN_Msk

    - -
    -
    - - - - -
    #define FSMC_BCR3_WREN_Msk   (0x1UL << FSMC_BCR3_WREN_Pos)
    -
    -

    0x00001000

    - -
    -
    - -

    ◆ FSMC_BCR3_WREN

    - -
    -
    - - - - -
    #define FSMC_BCR3_WREN   FSMC_BCR3_WREN_Msk
    -
    -

    Write enable bit
    -

    - -
    -
    - -

    ◆ FSMC_BCR3_WAITEN_Pos

    - -
    -
    - - - - -
    #define FSMC_BCR3_WAITEN_Pos   (13U)
    -
    - -
    -
    - -

    ◆ FSMC_BCR3_WAITEN_Msk

    - -
    -
    - - - - -
    #define FSMC_BCR3_WAITEN_Msk   (0x1UL << FSMC_BCR3_WAITEN_Pos)
    -
    -

    0x00002000

    - -
    -
    - -

    ◆ FSMC_BCR3_WAITEN

    - -
    -
    - - - - -
    #define FSMC_BCR3_WAITEN   FSMC_BCR3_WAITEN_Msk
    -
    -

    Wait enable bit
    -

    - -
    -
    - -

    ◆ FSMC_BCR3_EXTMOD_Pos

    - -
    -
    - - - - -
    #define FSMC_BCR3_EXTMOD_Pos   (14U)
    -
    - -
    -
    - -

    ◆ FSMC_BCR3_EXTMOD_Msk

    - -
    -
    - - - - -
    #define FSMC_BCR3_EXTMOD_Msk   (0x1UL << FSMC_BCR3_EXTMOD_Pos)
    -
    -

    0x00004000

    - -
    -
    - -

    ◆ FSMC_BCR3_EXTMOD

    - -
    -
    - - - - -
    #define FSMC_BCR3_EXTMOD   FSMC_BCR3_EXTMOD_Msk
    -
    -

    Extended mode enable
    -

    - -
    -
    - -

    ◆ FSMC_BCR3_ASYNCWAIT_Pos

    - -
    -
    - - - - -
    #define FSMC_BCR3_ASYNCWAIT_Pos   (15U)
    -
    - -
    -
    - -

    ◆ FSMC_BCR3_ASYNCWAIT_Msk

    - -
    -
    - - - - -
    #define FSMC_BCR3_ASYNCWAIT_Msk   (0x1UL << FSMC_BCR3_ASYNCWAIT_Pos)
    -
    -

    0x00008000

    - -
    -
    - -

    ◆ FSMC_BCR3_ASYNCWAIT

    - -
    -
    - - - - -
    #define FSMC_BCR3_ASYNCWAIT   FSMC_BCR3_ASYNCWAIT_Msk
    -
    -

    Asynchronous wait
    -

    - -
    -
    - -

    ◆ FSMC_BCR3_CPSIZE_Pos

    - -
    -
    - - - - -
    #define FSMC_BCR3_CPSIZE_Pos   (16U)
    -
    - -
    -
    - -

    ◆ FSMC_BCR3_CPSIZE_Msk

    - -
    -
    - - - - -
    #define FSMC_BCR3_CPSIZE_Msk   (0x7UL << FSMC_BCR3_CPSIZE_Pos)
    -
    -

    0x00070000

    - -
    -
    - -

    ◆ FSMC_BCR3_CPSIZE

    - -
    -
    - - - - -
    #define FSMC_BCR3_CPSIZE   FSMC_BCR3_CPSIZE_Msk
    -
    -

    CRAM page size

    - -
    -
    - -

    ◆ FSMC_BCR3_CPSIZE_0

    - -
    -
    - - - - -
    #define FSMC_BCR3_CPSIZE_0   (0x1UL << FSMC_BCR3_CPSIZE_Pos)
    -
    -

    0x00010000

    - -
    -
    - -

    ◆ FSMC_BCR3_CPSIZE_1

    - -
    -
    - - - - -
    #define FSMC_BCR3_CPSIZE_1   (0x2UL << FSMC_BCR3_CPSIZE_Pos)
    -
    -

    0x00020000

    - -
    -
    - -

    ◆ FSMC_BCR3_CPSIZE_2

    - -
    -
    - - - - -
    #define FSMC_BCR3_CPSIZE_2   (0x4UL << FSMC_BCR3_CPSIZE_Pos)
    -
    -

    0x00040000

    - -
    -
    - -

    ◆ FSMC_BCR3_CBURSTRW_Pos

    - -
    -
    - - - - -
    #define FSMC_BCR3_CBURSTRW_Pos   (19U)
    -
    - -
    -
    - -

    ◆ FSMC_BCR3_CBURSTRW_Msk

    - -
    -
    - - - - -
    #define FSMC_BCR3_CBURSTRW_Msk   (0x1UL << FSMC_BCR3_CBURSTRW_Pos)
    -
    -

    0x00080000

    - -
    -
    - -

    ◆ FSMC_BCR3_CBURSTRW

    - -
    -
    - - - - -
    #define FSMC_BCR3_CBURSTRW   FSMC_BCR3_CBURSTRW_Msk
    -
    -

    Write burst enable
    -

    - -
    -
    - -

    ◆ FSMC_BCR4_MBKEN_Pos

    - -
    -
    - - - - -
    #define FSMC_BCR4_MBKEN_Pos   (0U)
    -
    - -
    -
    - -

    ◆ FSMC_BCR4_MBKEN_Msk

    - -
    -
    - - - - -
    #define FSMC_BCR4_MBKEN_Msk   (0x1UL << FSMC_BCR4_MBKEN_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ FSMC_BCR4_MBKEN

    - -
    -
    - - - - -
    #define FSMC_BCR4_MBKEN   FSMC_BCR4_MBKEN_Msk
    -
    -

    Memory bank enable bit

    - -
    -
    - -

    ◆ FSMC_BCR4_MUXEN_Pos

    - -
    -
    - - - - -
    #define FSMC_BCR4_MUXEN_Pos   (1U)
    -
    - -
    -
    - -

    ◆ FSMC_BCR4_MUXEN_Msk

    - -
    -
    - - - - -
    #define FSMC_BCR4_MUXEN_Msk   (0x1UL << FSMC_BCR4_MUXEN_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ FSMC_BCR4_MUXEN

    - -
    -
    - - - - -
    #define FSMC_BCR4_MUXEN   FSMC_BCR4_MUXEN_Msk
    -
    -

    Address/data multiplexing enable bit
    -

    - -
    -
    - -

    ◆ FSMC_BCR4_MTYP_Pos

    - -
    -
    - - - - -
    #define FSMC_BCR4_MTYP_Pos   (2U)
    -
    - -
    -
    - -

    ◆ FSMC_BCR4_MTYP_Msk

    - -
    -
    - - - - -
    #define FSMC_BCR4_MTYP_Msk   (0x3UL << FSMC_BCR4_MTYP_Pos)
    -
    -

    0x0000000C

    - -
    -
    - -

    ◆ FSMC_BCR4_MTYP

    - -
    -
    - - - - -
    #define FSMC_BCR4_MTYP   FSMC_BCR4_MTYP_Msk
    -
    -

    MTYP[1:0] bits (Memory type)
    -

    - -
    -
    - -

    ◆ FSMC_BCR4_MTYP_0

    - -
    -
    - - - - -
    #define FSMC_BCR4_MTYP_0   (0x1UL << FSMC_BCR4_MTYP_Pos)
    -
    -

    0x00000004

    - -
    -
    - -

    ◆ FSMC_BCR4_MTYP_1

    - -
    -
    - - - - -
    #define FSMC_BCR4_MTYP_1   (0x2UL << FSMC_BCR4_MTYP_Pos)
    -
    -

    0x00000008

    - -
    -
    - -

    ◆ FSMC_BCR4_MWID_Pos

    - -
    -
    - - - - -
    #define FSMC_BCR4_MWID_Pos   (4U)
    -
    - -
    -
    - -

    ◆ FSMC_BCR4_MWID_Msk

    - -
    -
    - - - - -
    #define FSMC_BCR4_MWID_Msk   (0x3UL << FSMC_BCR4_MWID_Pos)
    -
    -

    0x00000030

    - -
    -
    - -

    ◆ FSMC_BCR4_MWID

    - -
    -
    - - - - -
    #define FSMC_BCR4_MWID   FSMC_BCR4_MWID_Msk
    -
    -

    MWID[1:0] bits (Memory data bus width)

    - -
    -
    - -

    ◆ FSMC_BCR4_MWID_0

    - -
    -
    - - - - -
    #define FSMC_BCR4_MWID_0   (0x1UL << FSMC_BCR4_MWID_Pos)
    -
    -

    0x00000010

    - -
    -
    - -

    ◆ FSMC_BCR4_MWID_1

    - -
    -
    - - - - -
    #define FSMC_BCR4_MWID_1   (0x2UL << FSMC_BCR4_MWID_Pos)
    -
    -

    0x00000020

    - -
    -
    - -

    ◆ FSMC_BCR4_FACCEN_Pos

    - -
    -
    - - - - -
    #define FSMC_BCR4_FACCEN_Pos   (6U)
    -
    - -
    -
    - -

    ◆ FSMC_BCR4_FACCEN_Msk

    - -
    -
    - - - - -
    #define FSMC_BCR4_FACCEN_Msk   (0x1UL << FSMC_BCR4_FACCEN_Pos)
    -
    -

    0x00000040

    - -
    -
    - -

    ◆ FSMC_BCR4_FACCEN

    - -
    -
    - - - - -
    #define FSMC_BCR4_FACCEN   FSMC_BCR4_FACCEN_Msk
    -
    -

    Flash access enable
    -

    - -
    -
    - -

    ◆ FSMC_BCR4_BURSTEN_Pos

    - -
    -
    - - - - -
    #define FSMC_BCR4_BURSTEN_Pos   (8U)
    -
    - -
    -
    - -

    ◆ FSMC_BCR4_BURSTEN_Msk

    - -
    -
    - - - - -
    #define FSMC_BCR4_BURSTEN_Msk   (0x1UL << FSMC_BCR4_BURSTEN_Pos)
    -
    -

    0x00000100

    - -
    -
    - -

    ◆ FSMC_BCR4_BURSTEN

    - -
    -
    - - - - -
    #define FSMC_BCR4_BURSTEN   FSMC_BCR4_BURSTEN_Msk
    -
    -

    Burst enable bit
    -

    - -
    -
    - -

    ◆ FSMC_BCR4_WAITPOL_Pos

    - -
    -
    - - - - -
    #define FSMC_BCR4_WAITPOL_Pos   (9U)
    -
    - -
    -
    - -

    ◆ FSMC_BCR4_WAITPOL_Msk

    - -
    -
    - - - - -
    #define FSMC_BCR4_WAITPOL_Msk   (0x1UL << FSMC_BCR4_WAITPOL_Pos)
    -
    -

    0x00000200

    - -
    -
    - -

    ◆ FSMC_BCR4_WAITPOL

    - -
    -
    - - - - -
    #define FSMC_BCR4_WAITPOL   FSMC_BCR4_WAITPOL_Msk
    -
    -

    Wait signal polarity bit
    -

    - -
    -
    - -

    ◆ FSMC_BCR4_WRAPMOD_Pos

    - -
    -
    - - - - -
    #define FSMC_BCR4_WRAPMOD_Pos   (10U)
    -
    - -
    -
    - -

    ◆ FSMC_BCR4_WRAPMOD_Msk

    - -
    -
    - - - - -
    #define FSMC_BCR4_WRAPMOD_Msk   (0x1UL << FSMC_BCR4_WRAPMOD_Pos)
    -
    -

    0x00000400

    - -
    -
    - -

    ◆ FSMC_BCR4_WRAPMOD

    - -
    -
    - - - - -
    #define FSMC_BCR4_WRAPMOD   FSMC_BCR4_WRAPMOD_Msk
    -
    -

    Wrapped burst mode support
    -

    - -
    -
    - -

    ◆ FSMC_BCR4_WAITCFG_Pos

    - -
    -
    - - - - -
    #define FSMC_BCR4_WAITCFG_Pos   (11U)
    -
    - -
    -
    - -

    ◆ FSMC_BCR4_WAITCFG_Msk

    - -
    -
    - - - - -
    #define FSMC_BCR4_WAITCFG_Msk   (0x1UL << FSMC_BCR4_WAITCFG_Pos)
    -
    -

    0x00000800

    - -
    -
    - -

    ◆ FSMC_BCR4_WAITCFG

    - -
    -
    - - - - -
    #define FSMC_BCR4_WAITCFG   FSMC_BCR4_WAITCFG_Msk
    -
    -

    Wait timing configuration
    -

    - -
    -
    - -

    ◆ FSMC_BCR4_WREN_Pos

    - -
    -
    - - - - -
    #define FSMC_BCR4_WREN_Pos   (12U)
    -
    - -
    -
    - -

    ◆ FSMC_BCR4_WREN_Msk

    - -
    -
    - - - - -
    #define FSMC_BCR4_WREN_Msk   (0x1UL << FSMC_BCR4_WREN_Pos)
    -
    -

    0x00001000

    - -
    -
    - -

    ◆ FSMC_BCR4_WREN

    - -
    -
    - - - - -
    #define FSMC_BCR4_WREN   FSMC_BCR4_WREN_Msk
    -
    -

    Write enable bit
    -

    - -
    -
    - -

    ◆ FSMC_BCR4_WAITEN_Pos

    - -
    -
    - - - - -
    #define FSMC_BCR4_WAITEN_Pos   (13U)
    -
    - -
    -
    - -

    ◆ FSMC_BCR4_WAITEN_Msk

    - -
    -
    - - - - -
    #define FSMC_BCR4_WAITEN_Msk   (0x1UL << FSMC_BCR4_WAITEN_Pos)
    -
    -

    0x00002000

    - -
    -
    - -

    ◆ FSMC_BCR4_WAITEN

    - -
    -
    - - - - -
    #define FSMC_BCR4_WAITEN   FSMC_BCR4_WAITEN_Msk
    -
    -

    Wait enable bit
    -

    - -
    -
    - -

    ◆ FSMC_BCR4_EXTMOD_Pos

    - -
    -
    - - - - -
    #define FSMC_BCR4_EXTMOD_Pos   (14U)
    -
    - -
    -
    - -

    ◆ FSMC_BCR4_EXTMOD_Msk

    - -
    -
    - - - - -
    #define FSMC_BCR4_EXTMOD_Msk   (0x1UL << FSMC_BCR4_EXTMOD_Pos)
    -
    -

    0x00004000

    - -
    -
    - -

    ◆ FSMC_BCR4_EXTMOD

    - -
    -
    - - - - -
    #define FSMC_BCR4_EXTMOD   FSMC_BCR4_EXTMOD_Msk
    -
    -

    Extended mode enable
    -

    - -
    -
    - -

    ◆ FSMC_BCR4_ASYNCWAIT_Pos

    - -
    -
    - - - - -
    #define FSMC_BCR4_ASYNCWAIT_Pos   (15U)
    -
    - -
    -
    - -

    ◆ FSMC_BCR4_ASYNCWAIT_Msk

    - -
    -
    - - - - -
    #define FSMC_BCR4_ASYNCWAIT_Msk   (0x1UL << FSMC_BCR4_ASYNCWAIT_Pos)
    -
    -

    0x00008000

    - -
    -
    - -

    ◆ FSMC_BCR4_ASYNCWAIT

    - -
    -
    - - - - -
    #define FSMC_BCR4_ASYNCWAIT   FSMC_BCR4_ASYNCWAIT_Msk
    -
    -

    Asynchronous wait
    -

    - -
    -
    - -

    ◆ FSMC_BCR4_CPSIZE_Pos

    - -
    -
    - - - - -
    #define FSMC_BCR4_CPSIZE_Pos   (16U)
    -
    - -
    -
    - -

    ◆ FSMC_BCR4_CPSIZE_Msk

    - -
    -
    - - - - -
    #define FSMC_BCR4_CPSIZE_Msk   (0x7UL << FSMC_BCR4_CPSIZE_Pos)
    -
    -

    0x00070000

    - -
    -
    - -

    ◆ FSMC_BCR4_CPSIZE

    - -
    -
    - - - - -
    #define FSMC_BCR4_CPSIZE   FSMC_BCR4_CPSIZE_Msk
    -
    -

    CRAM page size

    - -
    -
    - -

    ◆ FSMC_BCR4_CPSIZE_0

    - -
    -
    - - - - -
    #define FSMC_BCR4_CPSIZE_0   (0x1UL << FSMC_BCR4_CPSIZE_Pos)
    -
    -

    0x00010000

    - -
    -
    - -

    ◆ FSMC_BCR4_CPSIZE_1

    - -
    -
    - - - - -
    #define FSMC_BCR4_CPSIZE_1   (0x2UL << FSMC_BCR4_CPSIZE_Pos)
    -
    -

    0x00020000

    - -
    -
    - -

    ◆ FSMC_BCR4_CPSIZE_2

    - -
    -
    - - - - -
    #define FSMC_BCR4_CPSIZE_2   (0x4UL << FSMC_BCR4_CPSIZE_Pos)
    -
    -

    0x00040000

    - -
    -
    - -

    ◆ FSMC_BCR4_CBURSTRW_Pos

    - -
    -
    - - - - -
    #define FSMC_BCR4_CBURSTRW_Pos   (19U)
    -
    - -
    -
    - -

    ◆ FSMC_BCR4_CBURSTRW_Msk

    - -
    -
    - - - - -
    #define FSMC_BCR4_CBURSTRW_Msk   (0x1UL << FSMC_BCR4_CBURSTRW_Pos)
    -
    -

    0x00080000

    - -
    -
    - -

    ◆ FSMC_BCR4_CBURSTRW

    - -
    -
    - - - - -
    #define FSMC_BCR4_CBURSTRW   FSMC_BCR4_CBURSTRW_Msk
    -
    -

    Write burst enable
    -

    - -
    -
    - -

    ◆ FSMC_BTR1_ADDSET_Pos

    - -
    -
    - - - - -
    #define FSMC_BTR1_ADDSET_Pos   (0U)
    -
    - -
    -
    - -

    ◆ FSMC_BTR1_ADDSET_Msk

    - -
    -
    - - - - -
    #define FSMC_BTR1_ADDSET_Msk   (0xFUL << FSMC_BTR1_ADDSET_Pos)
    -
    -

    0x0000000F

    - -
    -
    - -

    ◆ FSMC_BTR1_ADDSET

    - -
    -
    - - - - -
    #define FSMC_BTR1_ADDSET   FSMC_BTR1_ADDSET_Msk
    -
    -

    ADDSET[3:0] bits (Address setup phase duration)

    - -
    -
    - -

    ◆ FSMC_BTR1_ADDSET_0

    - -
    -
    - - - - -
    #define FSMC_BTR1_ADDSET_0   (0x1UL << FSMC_BTR1_ADDSET_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ FSMC_BTR1_ADDSET_1

    - -
    -
    - - - - -
    #define FSMC_BTR1_ADDSET_1   (0x2UL << FSMC_BTR1_ADDSET_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ FSMC_BTR1_ADDSET_2

    - -
    -
    - - - - -
    #define FSMC_BTR1_ADDSET_2   (0x4UL << FSMC_BTR1_ADDSET_Pos)
    -
    -

    0x00000004

    - -
    -
    - -

    ◆ FSMC_BTR1_ADDSET_3

    - -
    -
    - - - - -
    #define FSMC_BTR1_ADDSET_3   (0x8UL << FSMC_BTR1_ADDSET_Pos)
    -
    -

    0x00000008

    - -
    -
    - -

    ◆ FSMC_BTR1_ADDHLD_Pos

    - -
    -
    - - - - -
    #define FSMC_BTR1_ADDHLD_Pos   (4U)
    -
    - -
    -
    - -

    ◆ FSMC_BTR1_ADDHLD_Msk

    - -
    -
    - - - - -
    #define FSMC_BTR1_ADDHLD_Msk   (0xFUL << FSMC_BTR1_ADDHLD_Pos)
    -
    -

    0x000000F0

    - -
    -
    - -

    ◆ FSMC_BTR1_ADDHLD

    - -
    -
    - - - - -
    #define FSMC_BTR1_ADDHLD   FSMC_BTR1_ADDHLD_Msk
    -
    -

    ADDHLD[3:0] bits (Address-hold phase duration)

    - -
    -
    - -

    ◆ FSMC_BTR1_ADDHLD_0

    - -
    -
    - - - - -
    #define FSMC_BTR1_ADDHLD_0   (0x1UL << FSMC_BTR1_ADDHLD_Pos)
    -
    -

    0x00000010

    - -
    -
    - -

    ◆ FSMC_BTR1_ADDHLD_1

    - -
    -
    - - - - -
    #define FSMC_BTR1_ADDHLD_1   (0x2UL << FSMC_BTR1_ADDHLD_Pos)
    -
    -

    0x00000020

    - -
    -
    - -

    ◆ FSMC_BTR1_ADDHLD_2

    - -
    -
    - - - - -
    #define FSMC_BTR1_ADDHLD_2   (0x4UL << FSMC_BTR1_ADDHLD_Pos)
    -
    -

    0x00000040

    - -
    -
    - -

    ◆ FSMC_BTR1_ADDHLD_3

    - -
    -
    - - - - -
    #define FSMC_BTR1_ADDHLD_3   (0x8UL << FSMC_BTR1_ADDHLD_Pos)
    -
    -

    0x00000080

    - -
    -
    - -

    ◆ FSMC_BTR1_DATAST_Pos

    - -
    -
    - - - - -
    #define FSMC_BTR1_DATAST_Pos   (8U)
    -
    - -
    -
    - -

    ◆ FSMC_BTR1_DATAST_Msk

    - -
    -
    - - - - -
    #define FSMC_BTR1_DATAST_Msk   (0xFFUL << FSMC_BTR1_DATAST_Pos)
    -
    -

    0x0000FF00

    - -
    -
    - -

    ◆ FSMC_BTR1_DATAST

    - -
    -
    - - - - -
    #define FSMC_BTR1_DATAST   FSMC_BTR1_DATAST_Msk
    -
    -

    DATAST [7:0] bits (Data-phase duration)

    - -
    -
    - -

    ◆ FSMC_BTR1_DATAST_0

    - -
    -
    - - - - -
    #define FSMC_BTR1_DATAST_0   (0x01UL << FSMC_BTR1_DATAST_Pos)
    -
    -

    0x00000100

    - -
    -
    - -

    ◆ FSMC_BTR1_DATAST_1

    - -
    -
    - - - - -
    #define FSMC_BTR1_DATAST_1   (0x02UL << FSMC_BTR1_DATAST_Pos)
    -
    -

    0x00000200

    - -
    -
    - -

    ◆ FSMC_BTR1_DATAST_2

    - -
    -
    - - - - -
    #define FSMC_BTR1_DATAST_2   (0x04UL << FSMC_BTR1_DATAST_Pos)
    -
    -

    0x00000400

    - -
    -
    - -

    ◆ FSMC_BTR1_DATAST_3

    - -
    -
    - - - - -
    #define FSMC_BTR1_DATAST_3   (0x08UL << FSMC_BTR1_DATAST_Pos)
    -
    -

    0x00000800

    - -
    -
    - -

    ◆ FSMC_BTR1_DATAST_4

    - -
    -
    - - - - -
    #define FSMC_BTR1_DATAST_4   (0x10UL << FSMC_BTR1_DATAST_Pos)
    -
    -

    0x00001000

    - -
    -
    - -

    ◆ FSMC_BTR1_DATAST_5

    - -
    -
    - - - - -
    #define FSMC_BTR1_DATAST_5   (0x20UL << FSMC_BTR1_DATAST_Pos)
    -
    -

    0x00002000

    - -
    -
    - -

    ◆ FSMC_BTR1_DATAST_6

    - -
    -
    - - - - -
    #define FSMC_BTR1_DATAST_6   (0x40UL << FSMC_BTR1_DATAST_Pos)
    -
    -

    0x00004000

    - -
    -
    - -

    ◆ FSMC_BTR1_DATAST_7

    - -
    -
    - - - - -
    #define FSMC_BTR1_DATAST_7   (0x80UL << FSMC_BTR1_DATAST_Pos)
    -
    -

    0x00008000

    - -
    -
    - -

    ◆ FSMC_BTR1_BUSTURN_Pos

    - -
    -
    - - - - -
    #define FSMC_BTR1_BUSTURN_Pos   (16U)
    -
    - -
    -
    - -

    ◆ FSMC_BTR1_BUSTURN_Msk

    - -
    -
    - - - - -
    #define FSMC_BTR1_BUSTURN_Msk   (0xFUL << FSMC_BTR1_BUSTURN_Pos)
    -
    -

    0x000F0000

    - -
    -
    - -

    ◆ FSMC_BTR1_BUSTURN

    - -
    -
    - - - - -
    #define FSMC_BTR1_BUSTURN   FSMC_BTR1_BUSTURN_Msk
    -
    -

    BUSTURN[3:0] bits (Bus turnaround phase duration)

    - -
    -
    - -

    ◆ FSMC_BTR1_BUSTURN_0

    - -
    -
    - - - - -
    #define FSMC_BTR1_BUSTURN_0   (0x1UL << FSMC_BTR1_BUSTURN_Pos)
    -
    -

    0x00010000

    - -
    -
    - -

    ◆ FSMC_BTR1_BUSTURN_1

    - -
    -
    - - - - -
    #define FSMC_BTR1_BUSTURN_1   (0x2UL << FSMC_BTR1_BUSTURN_Pos)
    -
    -

    0x00020000

    - -
    -
    - -

    ◆ FSMC_BTR1_BUSTURN_2

    - -
    -
    - - - - -
    #define FSMC_BTR1_BUSTURN_2   (0x4UL << FSMC_BTR1_BUSTURN_Pos)
    -
    -

    0x00040000

    - -
    -
    - -

    ◆ FSMC_BTR1_BUSTURN_3

    - -
    -
    - - - - -
    #define FSMC_BTR1_BUSTURN_3   (0x8UL << FSMC_BTR1_BUSTURN_Pos)
    -
    -

    0x00080000

    - -
    -
    - -

    ◆ FSMC_BTR1_CLKDIV_Pos

    - -
    -
    - - - - -
    #define FSMC_BTR1_CLKDIV_Pos   (20U)
    -
    - -
    -
    - -

    ◆ FSMC_BTR1_CLKDIV_Msk

    - -
    -
    - - - - -
    #define FSMC_BTR1_CLKDIV_Msk   (0xFUL << FSMC_BTR1_CLKDIV_Pos)
    -
    -

    0x00F00000

    - -
    -
    - -

    ◆ FSMC_BTR1_CLKDIV

    - -
    -
    - - - - -
    #define FSMC_BTR1_CLKDIV   FSMC_BTR1_CLKDIV_Msk
    -
    -

    CLKDIV[3:0] bits (Clock divide ratio)

    - -
    -
    - -

    ◆ FSMC_BTR1_CLKDIV_0

    - -
    -
    - - - - -
    #define FSMC_BTR1_CLKDIV_0   (0x1UL << FSMC_BTR1_CLKDIV_Pos)
    -
    -

    0x00100000

    - -
    -
    - -

    ◆ FSMC_BTR1_CLKDIV_1

    - -
    -
    - - - - -
    #define FSMC_BTR1_CLKDIV_1   (0x2UL << FSMC_BTR1_CLKDIV_Pos)
    -
    -

    0x00200000

    - -
    -
    - -

    ◆ FSMC_BTR1_CLKDIV_2

    - -
    -
    - - - - -
    #define FSMC_BTR1_CLKDIV_2   (0x4UL << FSMC_BTR1_CLKDIV_Pos)
    -
    -

    0x00400000

    - -
    -
    - -

    ◆ FSMC_BTR1_CLKDIV_3

    - -
    -
    - - - - -
    #define FSMC_BTR1_CLKDIV_3   (0x8UL << FSMC_BTR1_CLKDIV_Pos)
    -
    -

    0x00800000

    - -
    -
    - -

    ◆ FSMC_BTR1_DATLAT_Pos

    - -
    -
    - - - - -
    #define FSMC_BTR1_DATLAT_Pos   (24U)
    -
    - -
    -
    - -

    ◆ FSMC_BTR1_DATLAT_Msk

    - -
    -
    - - - - -
    #define FSMC_BTR1_DATLAT_Msk   (0xFUL << FSMC_BTR1_DATLAT_Pos)
    -
    -

    0x0F000000

    - -
    -
    - -

    ◆ FSMC_BTR1_DATLAT

    - -
    -
    - - - - -
    #define FSMC_BTR1_DATLAT   FSMC_BTR1_DATLAT_Msk
    -
    -

    DATLA[3:0] bits (Data latency)

    - -
    -
    - -

    ◆ FSMC_BTR1_DATLAT_0

    - -
    -
    - - - - -
    #define FSMC_BTR1_DATLAT_0   (0x1UL << FSMC_BTR1_DATLAT_Pos)
    -
    -

    0x01000000

    - -
    -
    - -

    ◆ FSMC_BTR1_DATLAT_1

    - -
    -
    - - - - -
    #define FSMC_BTR1_DATLAT_1   (0x2UL << FSMC_BTR1_DATLAT_Pos)
    -
    -

    0x02000000

    - -
    -
    - -

    ◆ FSMC_BTR1_DATLAT_2

    - -
    -
    - - - - -
    #define FSMC_BTR1_DATLAT_2   (0x4UL << FSMC_BTR1_DATLAT_Pos)
    -
    -

    0x04000000

    - -
    -
    - -

    ◆ FSMC_BTR1_DATLAT_3

    - -
    -
    - - - - -
    #define FSMC_BTR1_DATLAT_3   (0x8UL << FSMC_BTR1_DATLAT_Pos)
    -
    -

    0x08000000

    - -
    -
    - -

    ◆ FSMC_BTR1_ACCMOD_Pos

    - -
    -
    - - - - -
    #define FSMC_BTR1_ACCMOD_Pos   (28U)
    -
    - -
    -
    - -

    ◆ FSMC_BTR1_ACCMOD_Msk

    - -
    -
    - - - - -
    #define FSMC_BTR1_ACCMOD_Msk   (0x3UL << FSMC_BTR1_ACCMOD_Pos)
    -
    -

    0x30000000

    - -
    -
    - -

    ◆ FSMC_BTR1_ACCMOD

    - -
    -
    - - - - -
    #define FSMC_BTR1_ACCMOD   FSMC_BTR1_ACCMOD_Msk
    -
    -

    ACCMOD[1:0] bits (Access mode)

    - -
    -
    - -

    ◆ FSMC_BTR1_ACCMOD_0

    - -
    -
    - - - - -
    #define FSMC_BTR1_ACCMOD_0   (0x1UL << FSMC_BTR1_ACCMOD_Pos)
    -
    -

    0x10000000

    - -
    -
    - -

    ◆ FSMC_BTR1_ACCMOD_1

    - -
    -
    - - - - -
    #define FSMC_BTR1_ACCMOD_1   (0x2UL << FSMC_BTR1_ACCMOD_Pos)
    -
    -

    0x20000000

    - -
    -
    - -

    ◆ FSMC_BTR2_ADDSET_Pos

    - -
    -
    - - - - -
    #define FSMC_BTR2_ADDSET_Pos   (0U)
    -
    - -
    -
    - -

    ◆ FSMC_BTR2_ADDSET_Msk

    - -
    -
    - - - - -
    #define FSMC_BTR2_ADDSET_Msk   (0xFUL << FSMC_BTR2_ADDSET_Pos)
    -
    -

    0x0000000F

    - -
    -
    - -

    ◆ FSMC_BTR2_ADDSET

    - -
    -
    - - - - -
    #define FSMC_BTR2_ADDSET   FSMC_BTR2_ADDSET_Msk
    -
    -

    ADDSET[3:0] bits (Address setup phase duration)

    - -
    -
    - -

    ◆ FSMC_BTR2_ADDSET_0

    - -
    -
    - - - - -
    #define FSMC_BTR2_ADDSET_0   (0x1UL << FSMC_BTR2_ADDSET_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ FSMC_BTR2_ADDSET_1

    - -
    -
    - - - - -
    #define FSMC_BTR2_ADDSET_1   (0x2UL << FSMC_BTR2_ADDSET_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ FSMC_BTR2_ADDSET_2

    - -
    -
    - - - - -
    #define FSMC_BTR2_ADDSET_2   (0x4UL << FSMC_BTR2_ADDSET_Pos)
    -
    -

    0x00000004

    - -
    -
    - -

    ◆ FSMC_BTR2_ADDSET_3

    - -
    -
    - - - - -
    #define FSMC_BTR2_ADDSET_3   (0x8UL << FSMC_BTR2_ADDSET_Pos)
    -
    -

    0x00000008

    - -
    -
    - -

    ◆ FSMC_BTR2_ADDHLD_Pos

    - -
    -
    - - - - -
    #define FSMC_BTR2_ADDHLD_Pos   (4U)
    -
    - -
    -
    - -

    ◆ FSMC_BTR2_ADDHLD_Msk

    - -
    -
    - - - - -
    #define FSMC_BTR2_ADDHLD_Msk   (0xFUL << FSMC_BTR2_ADDHLD_Pos)
    -
    -

    0x000000F0

    - -
    -
    - -

    ◆ FSMC_BTR2_ADDHLD

    - -
    -
    - - - - -
    #define FSMC_BTR2_ADDHLD   FSMC_BTR2_ADDHLD_Msk
    -
    -

    ADDHLD[3:0] bits (Address-hold phase duration)

    - -
    -
    - -

    ◆ FSMC_BTR2_ADDHLD_0

    - -
    -
    - - - - -
    #define FSMC_BTR2_ADDHLD_0   (0x1UL << FSMC_BTR2_ADDHLD_Pos)
    -
    -

    0x00000010

    - -
    -
    - -

    ◆ FSMC_BTR2_ADDHLD_1

    - -
    -
    - - - - -
    #define FSMC_BTR2_ADDHLD_1   (0x2UL << FSMC_BTR2_ADDHLD_Pos)
    -
    -

    0x00000020

    - -
    -
    - -

    ◆ FSMC_BTR2_ADDHLD_2

    - -
    -
    - - - - -
    #define FSMC_BTR2_ADDHLD_2   (0x4UL << FSMC_BTR2_ADDHLD_Pos)
    -
    -

    0x00000040

    - -
    -
    - -

    ◆ FSMC_BTR2_ADDHLD_3

    - -
    -
    - - - - -
    #define FSMC_BTR2_ADDHLD_3   (0x8UL << FSMC_BTR2_ADDHLD_Pos)
    -
    -

    0x00000080

    - -
    -
    - -

    ◆ FSMC_BTR2_DATAST_Pos

    - -
    -
    - - - - -
    #define FSMC_BTR2_DATAST_Pos   (8U)
    -
    - -
    -
    - -

    ◆ FSMC_BTR2_DATAST_Msk

    - -
    -
    - - - - -
    #define FSMC_BTR2_DATAST_Msk   (0xFFUL << FSMC_BTR2_DATAST_Pos)
    -
    -

    0x0000FF00

    - -
    -
    - -

    ◆ FSMC_BTR2_DATAST

    - -
    -
    - - - - -
    #define FSMC_BTR2_DATAST   FSMC_BTR2_DATAST_Msk
    -
    -

    DATAST [7:0] bits (Data-phase duration)

    - -
    -
    - -

    ◆ FSMC_BTR2_DATAST_0

    - -
    -
    - - - - -
    #define FSMC_BTR2_DATAST_0   (0x01UL << FSMC_BTR2_DATAST_Pos)
    -
    -

    0x00000100

    - -
    -
    - -

    ◆ FSMC_BTR2_DATAST_1

    - -
    -
    - - - - -
    #define FSMC_BTR2_DATAST_1   (0x02UL << FSMC_BTR2_DATAST_Pos)
    -
    -

    0x00000200

    - -
    -
    - -

    ◆ FSMC_BTR2_DATAST_2

    - -
    -
    - - - - -
    #define FSMC_BTR2_DATAST_2   (0x04UL << FSMC_BTR2_DATAST_Pos)
    -
    -

    0x00000400

    - -
    -
    - -

    ◆ FSMC_BTR2_DATAST_3

    - -
    -
    - - - - -
    #define FSMC_BTR2_DATAST_3   (0x08UL << FSMC_BTR2_DATAST_Pos)
    -
    -

    0x00000800

    - -
    -
    - -

    ◆ FSMC_BTR2_DATAST_4

    - -
    -
    - - - - -
    #define FSMC_BTR2_DATAST_4   (0x10UL << FSMC_BTR2_DATAST_Pos)
    -
    -

    0x00001000

    - -
    -
    - -

    ◆ FSMC_BTR2_DATAST_5

    - -
    -
    - - - - -
    #define FSMC_BTR2_DATAST_5   (0x20UL << FSMC_BTR2_DATAST_Pos)
    -
    -

    0x00002000

    - -
    -
    - -

    ◆ FSMC_BTR2_DATAST_6

    - -
    -
    - - - - -
    #define FSMC_BTR2_DATAST_6   (0x40UL << FSMC_BTR2_DATAST_Pos)
    -
    -

    0x00004000

    - -
    -
    - -

    ◆ FSMC_BTR2_DATAST_7

    - -
    -
    - - - - -
    #define FSMC_BTR2_DATAST_7   (0x80UL << FSMC_BTR2_DATAST_Pos)
    -
    -

    0x00008000

    - -
    -
    - -

    ◆ FSMC_BTR2_BUSTURN_Pos

    - -
    -
    - - - - -
    #define FSMC_BTR2_BUSTURN_Pos   (16U)
    -
    - -
    -
    - -

    ◆ FSMC_BTR2_BUSTURN_Msk

    - -
    -
    - - - - -
    #define FSMC_BTR2_BUSTURN_Msk   (0xFUL << FSMC_BTR2_BUSTURN_Pos)
    -
    -

    0x000F0000

    - -
    -
    - -

    ◆ FSMC_BTR2_BUSTURN

    - -
    -
    - - - - -
    #define FSMC_BTR2_BUSTURN   FSMC_BTR2_BUSTURN_Msk
    -
    -

    BUSTURN[3:0] bits (Bus turnaround phase duration)

    - -
    -
    - -

    ◆ FSMC_BTR2_BUSTURN_0

    - -
    -
    - - - - -
    #define FSMC_BTR2_BUSTURN_0   (0x1UL << FSMC_BTR2_BUSTURN_Pos)
    -
    -

    0x00010000

    - -
    -
    - -

    ◆ FSMC_BTR2_BUSTURN_1

    - -
    -
    - - - - -
    #define FSMC_BTR2_BUSTURN_1   (0x2UL << FSMC_BTR2_BUSTURN_Pos)
    -
    -

    0x00020000

    - -
    -
    - -

    ◆ FSMC_BTR2_BUSTURN_2

    - -
    -
    - - - - -
    #define FSMC_BTR2_BUSTURN_2   (0x4UL << FSMC_BTR2_BUSTURN_Pos)
    -
    -

    0x00040000

    - -
    -
    - -

    ◆ FSMC_BTR2_BUSTURN_3

    - -
    -
    - - - - -
    #define FSMC_BTR2_BUSTURN_3   (0x8UL << FSMC_BTR2_BUSTURN_Pos)
    -
    -

    0x00080000

    - -
    -
    - -

    ◆ FSMC_BTR2_CLKDIV_Pos

    - -
    -
    - - - - -
    #define FSMC_BTR2_CLKDIV_Pos   (20U)
    -
    - -
    -
    - -

    ◆ FSMC_BTR2_CLKDIV_Msk

    - -
    -
    - - - - -
    #define FSMC_BTR2_CLKDIV_Msk   (0xFUL << FSMC_BTR2_CLKDIV_Pos)
    -
    -

    0x00F00000

    - -
    -
    - -

    ◆ FSMC_BTR2_CLKDIV

    - -
    -
    - - - - -
    #define FSMC_BTR2_CLKDIV   FSMC_BTR2_CLKDIV_Msk
    -
    -

    CLKDIV[3:0] bits (Clock divide ratio)

    - -
    -
    - -

    ◆ FSMC_BTR2_CLKDIV_0

    - -
    -
    - - - - -
    #define FSMC_BTR2_CLKDIV_0   (0x1UL << FSMC_BTR2_CLKDIV_Pos)
    -
    -

    0x00100000

    - -
    -
    - -

    ◆ FSMC_BTR2_CLKDIV_1

    - -
    -
    - - - - -
    #define FSMC_BTR2_CLKDIV_1   (0x2UL << FSMC_BTR2_CLKDIV_Pos)
    -
    -

    0x00200000

    - -
    -
    - -

    ◆ FSMC_BTR2_CLKDIV_2

    - -
    -
    - - - - -
    #define FSMC_BTR2_CLKDIV_2   (0x4UL << FSMC_BTR2_CLKDIV_Pos)
    -
    -

    0x00400000

    - -
    -
    - -

    ◆ FSMC_BTR2_CLKDIV_3

    - -
    -
    - - - - -
    #define FSMC_BTR2_CLKDIV_3   (0x8UL << FSMC_BTR2_CLKDIV_Pos)
    -
    -

    0x00800000

    - -
    -
    - -

    ◆ FSMC_BTR2_DATLAT_Pos

    - -
    -
    - - - - -
    #define FSMC_BTR2_DATLAT_Pos   (24U)
    -
    - -
    -
    - -

    ◆ FSMC_BTR2_DATLAT_Msk

    - -
    -
    - - - - -
    #define FSMC_BTR2_DATLAT_Msk   (0xFUL << FSMC_BTR2_DATLAT_Pos)
    -
    -

    0x0F000000

    - -
    -
    - -

    ◆ FSMC_BTR2_DATLAT

    - -
    -
    - - - - -
    #define FSMC_BTR2_DATLAT   FSMC_BTR2_DATLAT_Msk
    -
    -

    DATLA[3:0] bits (Data latency)

    - -
    -
    - -

    ◆ FSMC_BTR2_DATLAT_0

    - -
    -
    - - - - -
    #define FSMC_BTR2_DATLAT_0   (0x1UL << FSMC_BTR2_DATLAT_Pos)
    -
    -

    0x01000000

    - -
    -
    - -

    ◆ FSMC_BTR2_DATLAT_1

    - -
    -
    - - - - -
    #define FSMC_BTR2_DATLAT_1   (0x2UL << FSMC_BTR2_DATLAT_Pos)
    -
    -

    0x02000000

    - -
    -
    - -

    ◆ FSMC_BTR2_DATLAT_2

    - -
    -
    - - - - -
    #define FSMC_BTR2_DATLAT_2   (0x4UL << FSMC_BTR2_DATLAT_Pos)
    -
    -

    0x04000000

    - -
    -
    - -

    ◆ FSMC_BTR2_DATLAT_3

    - -
    -
    - - - - -
    #define FSMC_BTR2_DATLAT_3   (0x8UL << FSMC_BTR2_DATLAT_Pos)
    -
    -

    0x08000000

    - -
    -
    - -

    ◆ FSMC_BTR2_ACCMOD_Pos

    - -
    -
    - - - - -
    #define FSMC_BTR2_ACCMOD_Pos   (28U)
    -
    - -
    -
    - -

    ◆ FSMC_BTR2_ACCMOD_Msk

    - -
    -
    - - - - -
    #define FSMC_BTR2_ACCMOD_Msk   (0x3UL << FSMC_BTR2_ACCMOD_Pos)
    -
    -

    0x30000000

    - -
    -
    - -

    ◆ FSMC_BTR2_ACCMOD

    - -
    -
    - - - - -
    #define FSMC_BTR2_ACCMOD   FSMC_BTR2_ACCMOD_Msk
    -
    -

    ACCMOD[1:0] bits (Access mode)

    - -
    -
    - -

    ◆ FSMC_BTR2_ACCMOD_0

    - -
    -
    - - - - -
    #define FSMC_BTR2_ACCMOD_0   (0x1UL << FSMC_BTR2_ACCMOD_Pos)
    -
    -

    0x10000000

    - -
    -
    - -

    ◆ FSMC_BTR2_ACCMOD_1

    - -
    -
    - - - - -
    #define FSMC_BTR2_ACCMOD_1   (0x2UL << FSMC_BTR2_ACCMOD_Pos)
    -
    -

    0x20000000

    - -
    -
    - -

    ◆ FSMC_BTR3_ADDSET_Pos

    - -
    -
    - - - - -
    #define FSMC_BTR3_ADDSET_Pos   (0U)
    -
    - -
    -
    - -

    ◆ FSMC_BTR3_ADDSET_Msk

    - -
    -
    - - - - -
    #define FSMC_BTR3_ADDSET_Msk   (0xFUL << FSMC_BTR3_ADDSET_Pos)
    -
    -

    0x0000000F

    - -
    -
    - -

    ◆ FSMC_BTR3_ADDSET

    - -
    -
    - - - - -
    #define FSMC_BTR3_ADDSET   FSMC_BTR3_ADDSET_Msk
    -
    -

    ADDSET[3:0] bits (Address setup phase duration)

    - -
    -
    - -

    ◆ FSMC_BTR3_ADDSET_0

    - -
    -
    - - - - -
    #define FSMC_BTR3_ADDSET_0   (0x1UL << FSMC_BTR3_ADDSET_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ FSMC_BTR3_ADDSET_1

    - -
    -
    - - - - -
    #define FSMC_BTR3_ADDSET_1   (0x2UL << FSMC_BTR3_ADDSET_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ FSMC_BTR3_ADDSET_2

    - -
    -
    - - - - -
    #define FSMC_BTR3_ADDSET_2   (0x4UL << FSMC_BTR3_ADDSET_Pos)
    -
    -

    0x00000004

    - -
    -
    - -

    ◆ FSMC_BTR3_ADDSET_3

    - -
    -
    - - - - -
    #define FSMC_BTR3_ADDSET_3   (0x8UL << FSMC_BTR3_ADDSET_Pos)
    -
    -

    0x00000008

    - -
    -
    - -

    ◆ FSMC_BTR3_ADDHLD_Pos

    - -
    -
    - - - - -
    #define FSMC_BTR3_ADDHLD_Pos   (4U)
    -
    - -
    -
    - -

    ◆ FSMC_BTR3_ADDHLD_Msk

    - -
    -
    - - - - -
    #define FSMC_BTR3_ADDHLD_Msk   (0xFUL << FSMC_BTR3_ADDHLD_Pos)
    -
    -

    0x000000F0

    - -
    -
    - -

    ◆ FSMC_BTR3_ADDHLD

    - -
    -
    - - - - -
    #define FSMC_BTR3_ADDHLD   FSMC_BTR3_ADDHLD_Msk
    -
    -

    ADDHLD[3:0] bits (Address-hold phase duration)

    - -
    -
    - -

    ◆ FSMC_BTR3_ADDHLD_0

    - -
    -
    - - - - -
    #define FSMC_BTR3_ADDHLD_0   (0x1UL << FSMC_BTR3_ADDHLD_Pos)
    -
    -

    0x00000010

    - -
    -
    - -

    ◆ FSMC_BTR3_ADDHLD_1

    - -
    -
    - - - - -
    #define FSMC_BTR3_ADDHLD_1   (0x2UL << FSMC_BTR3_ADDHLD_Pos)
    -
    -

    0x00000020

    - -
    -
    - -

    ◆ FSMC_BTR3_ADDHLD_2

    - -
    -
    - - - - -
    #define FSMC_BTR3_ADDHLD_2   (0x4UL << FSMC_BTR3_ADDHLD_Pos)
    -
    -

    0x00000040

    - -
    -
    - -

    ◆ FSMC_BTR3_ADDHLD_3

    - -
    -
    - - - - -
    #define FSMC_BTR3_ADDHLD_3   (0x8UL << FSMC_BTR3_ADDHLD_Pos)
    -
    -

    0x00000080

    - -
    -
    - -

    ◆ FSMC_BTR3_DATAST_Pos

    - -
    -
    - - - - -
    #define FSMC_BTR3_DATAST_Pos   (8U)
    -
    - -
    -
    - -

    ◆ FSMC_BTR3_DATAST_Msk

    - -
    -
    - - - - -
    #define FSMC_BTR3_DATAST_Msk   (0xFFUL << FSMC_BTR3_DATAST_Pos)
    -
    -

    0x0000FF00

    - -
    -
    - -

    ◆ FSMC_BTR3_DATAST

    - -
    -
    - - - - -
    #define FSMC_BTR3_DATAST   FSMC_BTR3_DATAST_Msk
    -
    -

    DATAST [7:0] bits (Data-phase duration)

    - -
    -
    - -

    ◆ FSMC_BTR3_DATAST_0

    - -
    -
    - - - - -
    #define FSMC_BTR3_DATAST_0   (0x01UL << FSMC_BTR3_DATAST_Pos)
    -
    -

    0x00000100

    - -
    -
    - -

    ◆ FSMC_BTR3_DATAST_1

    - -
    -
    - - - - -
    #define FSMC_BTR3_DATAST_1   (0x02UL << FSMC_BTR3_DATAST_Pos)
    -
    -

    0x00000200

    - -
    -
    - -

    ◆ FSMC_BTR3_DATAST_2

    - -
    -
    - - - - -
    #define FSMC_BTR3_DATAST_2   (0x04UL << FSMC_BTR3_DATAST_Pos)
    -
    -

    0x00000400

    - -
    -
    - -

    ◆ FSMC_BTR3_DATAST_3

    - -
    -
    - - - - -
    #define FSMC_BTR3_DATAST_3   (0x08UL << FSMC_BTR3_DATAST_Pos)
    -
    -

    0x00000800

    - -
    -
    - -

    ◆ FSMC_BTR3_DATAST_4

    - -
    -
    - - - - -
    #define FSMC_BTR3_DATAST_4   (0x10UL << FSMC_BTR3_DATAST_Pos)
    -
    -

    0x00001000

    - -
    -
    - -

    ◆ FSMC_BTR3_DATAST_5

    - -
    -
    - - - - -
    #define FSMC_BTR3_DATAST_5   (0x20UL << FSMC_BTR3_DATAST_Pos)
    -
    -

    0x00002000

    - -
    -
    - -

    ◆ FSMC_BTR3_DATAST_6

    - -
    -
    - - - - -
    #define FSMC_BTR3_DATAST_6   (0x40UL << FSMC_BTR3_DATAST_Pos)
    -
    -

    0x00004000

    - -
    -
    - -

    ◆ FSMC_BTR3_DATAST_7

    - -
    -
    - - - - -
    #define FSMC_BTR3_DATAST_7   (0x80UL << FSMC_BTR3_DATAST_Pos)
    -
    -

    0x00008000

    - -
    -
    - -

    ◆ FSMC_BTR3_BUSTURN_Pos

    - -
    -
    - - - - -
    #define FSMC_BTR3_BUSTURN_Pos   (16U)
    -
    - -
    -
    - -

    ◆ FSMC_BTR3_BUSTURN_Msk

    - -
    -
    - - - - -
    #define FSMC_BTR3_BUSTURN_Msk   (0xFUL << FSMC_BTR3_BUSTURN_Pos)
    -
    -

    0x000F0000

    - -
    -
    - -

    ◆ FSMC_BTR3_BUSTURN

    - -
    -
    - - - - -
    #define FSMC_BTR3_BUSTURN   FSMC_BTR3_BUSTURN_Msk
    -
    -

    BUSTURN[3:0] bits (Bus turnaround phase duration)

    - -
    -
    - -

    ◆ FSMC_BTR3_BUSTURN_0

    - -
    -
    - - - - -
    #define FSMC_BTR3_BUSTURN_0   (0x1UL << FSMC_BTR3_BUSTURN_Pos)
    -
    -

    0x00010000

    - -
    -
    - -

    ◆ FSMC_BTR3_BUSTURN_1

    - -
    -
    - - - - -
    #define FSMC_BTR3_BUSTURN_1   (0x2UL << FSMC_BTR3_BUSTURN_Pos)
    -
    -

    0x00020000

    - -
    -
    - -

    ◆ FSMC_BTR3_BUSTURN_2

    - -
    -
    - - - - -
    #define FSMC_BTR3_BUSTURN_2   (0x4UL << FSMC_BTR3_BUSTURN_Pos)
    -
    -

    0x00040000

    - -
    -
    - -

    ◆ FSMC_BTR3_BUSTURN_3

    - -
    -
    - - - - -
    #define FSMC_BTR3_BUSTURN_3   (0x8UL << FSMC_BTR3_BUSTURN_Pos)
    -
    -

    0x00080000

    - -
    -
    - -

    ◆ FSMC_BTR3_CLKDIV_Pos

    - -
    -
    - - - - -
    #define FSMC_BTR3_CLKDIV_Pos   (20U)
    -
    - -
    -
    - -

    ◆ FSMC_BTR3_CLKDIV_Msk

    - -
    -
    - - - - -
    #define FSMC_BTR3_CLKDIV_Msk   (0xFUL << FSMC_BTR3_CLKDIV_Pos)
    -
    -

    0x00F00000

    - -
    -
    - -

    ◆ FSMC_BTR3_CLKDIV

    - -
    -
    - - - - -
    #define FSMC_BTR3_CLKDIV   FSMC_BTR3_CLKDIV_Msk
    -
    -

    CLKDIV[3:0] bits (Clock divide ratio)

    - -
    -
    - -

    ◆ FSMC_BTR3_CLKDIV_0

    - -
    -
    - - - - -
    #define FSMC_BTR3_CLKDIV_0   (0x1UL << FSMC_BTR3_CLKDIV_Pos)
    -
    -

    0x00100000

    - -
    -
    - -

    ◆ FSMC_BTR3_CLKDIV_1

    - -
    -
    - - - - -
    #define FSMC_BTR3_CLKDIV_1   (0x2UL << FSMC_BTR3_CLKDIV_Pos)
    -
    -

    0x00200000

    - -
    -
    - -

    ◆ FSMC_BTR3_CLKDIV_2

    - -
    -
    - - - - -
    #define FSMC_BTR3_CLKDIV_2   (0x4UL << FSMC_BTR3_CLKDIV_Pos)
    -
    -

    0x00400000

    - -
    -
    - -

    ◆ FSMC_BTR3_CLKDIV_3

    - -
    -
    - - - - -
    #define FSMC_BTR3_CLKDIV_3   (0x8UL << FSMC_BTR3_CLKDIV_Pos)
    -
    -

    0x00800000

    - -
    -
    - -

    ◆ FSMC_BTR3_DATLAT_Pos

    - -
    -
    - - - - -
    #define FSMC_BTR3_DATLAT_Pos   (24U)
    -
    - -
    -
    - -

    ◆ FSMC_BTR3_DATLAT_Msk

    - -
    -
    - - - - -
    #define FSMC_BTR3_DATLAT_Msk   (0xFUL << FSMC_BTR3_DATLAT_Pos)
    -
    -

    0x0F000000

    - -
    -
    - -

    ◆ FSMC_BTR3_DATLAT

    - -
    -
    - - - - -
    #define FSMC_BTR3_DATLAT   FSMC_BTR3_DATLAT_Msk
    -
    -

    DATLA[3:0] bits (Data latency)

    - -
    -
    - -

    ◆ FSMC_BTR3_DATLAT_0

    - -
    -
    - - - - -
    #define FSMC_BTR3_DATLAT_0   (0x1UL << FSMC_BTR3_DATLAT_Pos)
    -
    -

    0x01000000

    - -
    -
    - -

    ◆ FSMC_BTR3_DATLAT_1

    - -
    -
    - - - - -
    #define FSMC_BTR3_DATLAT_1   (0x2UL << FSMC_BTR3_DATLAT_Pos)
    -
    -

    0x02000000

    - -
    -
    - -

    ◆ FSMC_BTR3_DATLAT_2

    - -
    -
    - - - - -
    #define FSMC_BTR3_DATLAT_2   (0x4UL << FSMC_BTR3_DATLAT_Pos)
    -
    -

    0x04000000

    - -
    -
    - -

    ◆ FSMC_BTR3_DATLAT_3

    - -
    -
    - - - - -
    #define FSMC_BTR3_DATLAT_3   (0x8UL << FSMC_BTR3_DATLAT_Pos)
    -
    -

    0x08000000

    - -
    -
    - -

    ◆ FSMC_BTR3_ACCMOD_Pos

    - -
    -
    - - - - -
    #define FSMC_BTR3_ACCMOD_Pos   (28U)
    -
    - -
    -
    - -

    ◆ FSMC_BTR3_ACCMOD_Msk

    - -
    -
    - - - - -
    #define FSMC_BTR3_ACCMOD_Msk   (0x3UL << FSMC_BTR3_ACCMOD_Pos)
    -
    -

    0x30000000

    - -
    -
    - -

    ◆ FSMC_BTR3_ACCMOD

    - -
    -
    - - - - -
    #define FSMC_BTR3_ACCMOD   FSMC_BTR3_ACCMOD_Msk
    -
    -

    ACCMOD[1:0] bits (Access mode)

    - -
    -
    - -

    ◆ FSMC_BTR3_ACCMOD_0

    - -
    -
    - - - - -
    #define FSMC_BTR3_ACCMOD_0   (0x1UL << FSMC_BTR3_ACCMOD_Pos)
    -
    -

    0x10000000

    - -
    -
    - -

    ◆ FSMC_BTR3_ACCMOD_1

    - -
    -
    - - - - -
    #define FSMC_BTR3_ACCMOD_1   (0x2UL << FSMC_BTR3_ACCMOD_Pos)
    -
    -

    0x20000000

    - -
    -
    - -

    ◆ FSMC_BTR4_ADDSET_Pos

    - -
    -
    - - - - -
    #define FSMC_BTR4_ADDSET_Pos   (0U)
    -
    - -
    -
    - -

    ◆ FSMC_BTR4_ADDSET_Msk

    - -
    -
    - - - - -
    #define FSMC_BTR4_ADDSET_Msk   (0xFUL << FSMC_BTR4_ADDSET_Pos)
    -
    -

    0x0000000F

    - -
    -
    - -

    ◆ FSMC_BTR4_ADDSET

    - -
    -
    - - - - -
    #define FSMC_BTR4_ADDSET   FSMC_BTR4_ADDSET_Msk
    -
    -

    ADDSET[3:0] bits (Address setup phase duration)

    - -
    -
    - -

    ◆ FSMC_BTR4_ADDSET_0

    - -
    -
    - - - - -
    #define FSMC_BTR4_ADDSET_0   (0x1UL << FSMC_BTR4_ADDSET_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ FSMC_BTR4_ADDSET_1

    - -
    -
    - - - - -
    #define FSMC_BTR4_ADDSET_1   (0x2UL << FSMC_BTR4_ADDSET_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ FSMC_BTR4_ADDSET_2

    - -
    -
    - - - - -
    #define FSMC_BTR4_ADDSET_2   (0x4UL << FSMC_BTR4_ADDSET_Pos)
    -
    -

    0x00000004

    - -
    -
    - -

    ◆ FSMC_BTR4_ADDSET_3

    - -
    -
    - - - - -
    #define FSMC_BTR4_ADDSET_3   (0x8UL << FSMC_BTR4_ADDSET_Pos)
    -
    -

    0x00000008

    - -
    -
    - -

    ◆ FSMC_BTR4_ADDHLD_Pos

    - -
    -
    - - - - -
    #define FSMC_BTR4_ADDHLD_Pos   (4U)
    -
    - -
    -
    - -

    ◆ FSMC_BTR4_ADDHLD_Msk

    - -
    -
    - - - - -
    #define FSMC_BTR4_ADDHLD_Msk   (0xFUL << FSMC_BTR4_ADDHLD_Pos)
    -
    -

    0x000000F0

    - -
    -
    - -

    ◆ FSMC_BTR4_ADDHLD

    - -
    -
    - - - - -
    #define FSMC_BTR4_ADDHLD   FSMC_BTR4_ADDHLD_Msk
    -
    -

    ADDHLD[3:0] bits (Address-hold phase duration)

    - -
    -
    - -

    ◆ FSMC_BTR4_ADDHLD_0

    - -
    -
    - - - - -
    #define FSMC_BTR4_ADDHLD_0   (0x1UL << FSMC_BTR4_ADDHLD_Pos)
    -
    -

    0x00000010

    - -
    -
    - -

    ◆ FSMC_BTR4_ADDHLD_1

    - -
    -
    - - - - -
    #define FSMC_BTR4_ADDHLD_1   (0x2UL << FSMC_BTR4_ADDHLD_Pos)
    -
    -

    0x00000020

    - -
    -
    - -

    ◆ FSMC_BTR4_ADDHLD_2

    - -
    -
    - - - - -
    #define FSMC_BTR4_ADDHLD_2   (0x4UL << FSMC_BTR4_ADDHLD_Pos)
    -
    -

    0x00000040

    - -
    -
    - -

    ◆ FSMC_BTR4_ADDHLD_3

    - -
    -
    - - - - -
    #define FSMC_BTR4_ADDHLD_3   (0x8UL << FSMC_BTR4_ADDHLD_Pos)
    -
    -

    0x00000080

    - -
    -
    - -

    ◆ FSMC_BTR4_DATAST_Pos

    - -
    -
    - - - - -
    #define FSMC_BTR4_DATAST_Pos   (8U)
    -
    - -
    -
    - -

    ◆ FSMC_BTR4_DATAST_Msk

    - -
    -
    - - - - -
    #define FSMC_BTR4_DATAST_Msk   (0xFFUL << FSMC_BTR4_DATAST_Pos)
    -
    -

    0x0000FF00

    - -
    -
    - -

    ◆ FSMC_BTR4_DATAST

    - -
    -
    - - - - -
    #define FSMC_BTR4_DATAST   FSMC_BTR4_DATAST_Msk
    -
    -

    DATAST [7:0] bits (Data-phase duration)

    - -
    -
    - -

    ◆ FSMC_BTR4_DATAST_0

    - -
    -
    - - - - -
    #define FSMC_BTR4_DATAST_0   (0x01UL << FSMC_BTR4_DATAST_Pos)
    -
    -

    0x00000100

    - -
    -
    - -

    ◆ FSMC_BTR4_DATAST_1

    - -
    -
    - - - - -
    #define FSMC_BTR4_DATAST_1   (0x02UL << FSMC_BTR4_DATAST_Pos)
    -
    -

    0x00000200

    - -
    -
    - -

    ◆ FSMC_BTR4_DATAST_2

    - -
    -
    - - - - -
    #define FSMC_BTR4_DATAST_2   (0x04UL << FSMC_BTR4_DATAST_Pos)
    -
    -

    0x00000400

    - -
    -
    - -

    ◆ FSMC_BTR4_DATAST_3

    - -
    -
    - - - - -
    #define FSMC_BTR4_DATAST_3   (0x08UL << FSMC_BTR4_DATAST_Pos)
    -
    -

    0x00000800

    - -
    -
    - -

    ◆ FSMC_BTR4_DATAST_4

    - -
    -
    - - - - -
    #define FSMC_BTR4_DATAST_4   (0x10UL << FSMC_BTR4_DATAST_Pos)
    -
    -

    0x00001000

    - -
    -
    - -

    ◆ FSMC_BTR4_DATAST_5

    - -
    -
    - - - - -
    #define FSMC_BTR4_DATAST_5   (0x20UL << FSMC_BTR4_DATAST_Pos)
    -
    -

    0x00002000

    - -
    -
    - -

    ◆ FSMC_BTR4_DATAST_6

    - -
    -
    - - - - -
    #define FSMC_BTR4_DATAST_6   (0x40UL << FSMC_BTR4_DATAST_Pos)
    -
    -

    0x00004000

    - -
    -
    - -

    ◆ FSMC_BTR4_DATAST_7

    - -
    -
    - - - - -
    #define FSMC_BTR4_DATAST_7   (0x80UL << FSMC_BTR4_DATAST_Pos)
    -
    -

    0x00008000

    - -
    -
    - -

    ◆ FSMC_BTR4_BUSTURN_Pos

    - -
    -
    - - - - -
    #define FSMC_BTR4_BUSTURN_Pos   (16U)
    -
    - -
    -
    - -

    ◆ FSMC_BTR4_BUSTURN_Msk

    - -
    -
    - - - - -
    #define FSMC_BTR4_BUSTURN_Msk   (0xFUL << FSMC_BTR4_BUSTURN_Pos)
    -
    -

    0x000F0000

    - -
    -
    - -

    ◆ FSMC_BTR4_BUSTURN

    - -
    -
    - - - - -
    #define FSMC_BTR4_BUSTURN   FSMC_BTR4_BUSTURN_Msk
    -
    -

    BUSTURN[3:0] bits (Bus turnaround phase duration)

    - -
    -
    - -

    ◆ FSMC_BTR4_BUSTURN_0

    - -
    -
    - - - - -
    #define FSMC_BTR4_BUSTURN_0   (0x1UL << FSMC_BTR4_BUSTURN_Pos)
    -
    -

    0x00010000

    - -
    -
    - -

    ◆ FSMC_BTR4_BUSTURN_1

    - -
    -
    - - - - -
    #define FSMC_BTR4_BUSTURN_1   (0x2UL << FSMC_BTR4_BUSTURN_Pos)
    -
    -

    0x00020000

    - -
    -
    - -

    ◆ FSMC_BTR4_BUSTURN_2

    - -
    -
    - - - - -
    #define FSMC_BTR4_BUSTURN_2   (0x4UL << FSMC_BTR4_BUSTURN_Pos)
    -
    -

    0x00040000

    - -
    -
    - -

    ◆ FSMC_BTR4_BUSTURN_3

    - -
    -
    - - - - -
    #define FSMC_BTR4_BUSTURN_3   (0x8UL << FSMC_BTR4_BUSTURN_Pos)
    -
    -

    0x00080000

    - -
    -
    - -

    ◆ FSMC_BTR4_CLKDIV_Pos

    - -
    -
    - - - - -
    #define FSMC_BTR4_CLKDIV_Pos   (20U)
    -
    - -
    -
    - -

    ◆ FSMC_BTR4_CLKDIV_Msk

    - -
    -
    - - - - -
    #define FSMC_BTR4_CLKDIV_Msk   (0xFUL << FSMC_BTR4_CLKDIV_Pos)
    -
    -

    0x00F00000

    - -
    -
    - -

    ◆ FSMC_BTR4_CLKDIV

    - -
    -
    - - - - -
    #define FSMC_BTR4_CLKDIV   FSMC_BTR4_CLKDIV_Msk
    -
    -

    CLKDIV[3:0] bits (Clock divide ratio)

    - -
    -
    - -

    ◆ FSMC_BTR4_CLKDIV_0

    - -
    -
    - - - - -
    #define FSMC_BTR4_CLKDIV_0   (0x1UL << FSMC_BTR4_CLKDIV_Pos)
    -
    -

    0x00100000

    - -
    -
    - -

    ◆ FSMC_BTR4_CLKDIV_1

    - -
    -
    - - - - -
    #define FSMC_BTR4_CLKDIV_1   (0x2UL << FSMC_BTR4_CLKDIV_Pos)
    -
    -

    0x00200000

    - -
    -
    - -

    ◆ FSMC_BTR4_CLKDIV_2

    - -
    -
    - - - - -
    #define FSMC_BTR4_CLKDIV_2   (0x4UL << FSMC_BTR4_CLKDIV_Pos)
    -
    -

    0x00400000

    - -
    -
    - -

    ◆ FSMC_BTR4_CLKDIV_3

    - -
    -
    - - - - -
    #define FSMC_BTR4_CLKDIV_3   (0x8UL << FSMC_BTR4_CLKDIV_Pos)
    -
    -

    0x00800000

    - -
    -
    - -

    ◆ FSMC_BTR4_DATLAT_Pos

    - -
    -
    - - - - -
    #define FSMC_BTR4_DATLAT_Pos   (24U)
    -
    - -
    -
    - -

    ◆ FSMC_BTR4_DATLAT_Msk

    - -
    -
    - - - - -
    #define FSMC_BTR4_DATLAT_Msk   (0xFUL << FSMC_BTR4_DATLAT_Pos)
    -
    -

    0x0F000000

    - -
    -
    - -

    ◆ FSMC_BTR4_DATLAT

    - -
    -
    - - - - -
    #define FSMC_BTR4_DATLAT   FSMC_BTR4_DATLAT_Msk
    -
    -

    DATLA[3:0] bits (Data latency)

    - -
    -
    - -

    ◆ FSMC_BTR4_DATLAT_0

    - -
    -
    - - - - -
    #define FSMC_BTR4_DATLAT_0   (0x1UL << FSMC_BTR4_DATLAT_Pos)
    -
    -

    0x01000000

    - -
    -
    - -

    ◆ FSMC_BTR4_DATLAT_1

    - -
    -
    - - - - -
    #define FSMC_BTR4_DATLAT_1   (0x2UL << FSMC_BTR4_DATLAT_Pos)
    -
    -

    0x02000000

    - -
    -
    - -

    ◆ FSMC_BTR4_DATLAT_2

    - -
    -
    - - - - -
    #define FSMC_BTR4_DATLAT_2   (0x4UL << FSMC_BTR4_DATLAT_Pos)
    -
    -

    0x04000000

    - -
    -
    - -

    ◆ FSMC_BTR4_DATLAT_3

    - -
    -
    - - - - -
    #define FSMC_BTR4_DATLAT_3   (0x8UL << FSMC_BTR4_DATLAT_Pos)
    -
    -

    0x08000000

    - -
    -
    - -

    ◆ FSMC_BTR4_ACCMOD_Pos

    - -
    -
    - - - - -
    #define FSMC_BTR4_ACCMOD_Pos   (28U)
    -
    - -
    -
    - -

    ◆ FSMC_BTR4_ACCMOD_Msk

    - -
    -
    - - - - -
    #define FSMC_BTR4_ACCMOD_Msk   (0x3UL << FSMC_BTR4_ACCMOD_Pos)
    -
    -

    0x30000000

    - -
    -
    - -

    ◆ FSMC_BTR4_ACCMOD

    - -
    -
    - - - - -
    #define FSMC_BTR4_ACCMOD   FSMC_BTR4_ACCMOD_Msk
    -
    -

    ACCMOD[1:0] bits (Access mode)

    - -
    -
    - -

    ◆ FSMC_BTR4_ACCMOD_0

    - -
    -
    - - - - -
    #define FSMC_BTR4_ACCMOD_0   (0x1UL << FSMC_BTR4_ACCMOD_Pos)
    -
    -

    0x10000000

    - -
    -
    - -

    ◆ FSMC_BTR4_ACCMOD_1

    - -
    -
    - - - - -
    #define FSMC_BTR4_ACCMOD_1   (0x2UL << FSMC_BTR4_ACCMOD_Pos)
    -
    -

    0x20000000

    - -
    -
    - -

    ◆ FSMC_BWTR1_ADDSET_Pos

    - -
    -
    - - - - -
    #define FSMC_BWTR1_ADDSET_Pos   (0U)
    -
    - -
    -
    - -

    ◆ FSMC_BWTR1_ADDSET_Msk

    - -
    -
    - - - - -
    #define FSMC_BWTR1_ADDSET_Msk   (0xFUL << FSMC_BWTR1_ADDSET_Pos)
    -
    -

    0x0000000F

    - -
    -
    - -

    ◆ FSMC_BWTR1_ADDSET

    - -
    -
    - - - - -
    #define FSMC_BWTR1_ADDSET   FSMC_BWTR1_ADDSET_Msk
    -
    -

    ADDSET[3:0] bits (Address setup phase duration)

    - -
    -
    - -

    ◆ FSMC_BWTR1_ADDSET_0

    - -
    -
    - - - - -
    #define FSMC_BWTR1_ADDSET_0   (0x1UL << FSMC_BWTR1_ADDSET_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ FSMC_BWTR1_ADDSET_1

    - -
    -
    - - - - -
    #define FSMC_BWTR1_ADDSET_1   (0x2UL << FSMC_BWTR1_ADDSET_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ FSMC_BWTR1_ADDSET_2

    - -
    -
    - - - - -
    #define FSMC_BWTR1_ADDSET_2   (0x4UL << FSMC_BWTR1_ADDSET_Pos)
    -
    -

    0x00000004

    - -
    -
    - -

    ◆ FSMC_BWTR1_ADDSET_3

    - -
    -
    - - - - -
    #define FSMC_BWTR1_ADDSET_3   (0x8UL << FSMC_BWTR1_ADDSET_Pos)
    -
    -

    0x00000008

    - -
    -
    - -

    ◆ FSMC_BWTR1_ADDHLD_Pos

    - -
    -
    - - - - -
    #define FSMC_BWTR1_ADDHLD_Pos   (4U)
    -
    - -
    -
    - -

    ◆ FSMC_BWTR1_ADDHLD_Msk

    - -
    -
    - - - - -
    #define FSMC_BWTR1_ADDHLD_Msk   (0xFUL << FSMC_BWTR1_ADDHLD_Pos)
    -
    -

    0x000000F0

    - -
    -
    - -

    ◆ FSMC_BWTR1_ADDHLD

    - -
    -
    - - - - -
    #define FSMC_BWTR1_ADDHLD   FSMC_BWTR1_ADDHLD_Msk
    -
    -

    ADDHLD[3:0] bits (Address-hold phase duration)

    - -
    -
    - -

    ◆ FSMC_BWTR1_ADDHLD_0

    - -
    -
    - - - - -
    #define FSMC_BWTR1_ADDHLD_0   (0x1UL << FSMC_BWTR1_ADDHLD_Pos)
    -
    -

    0x00000010

    - -
    -
    - -

    ◆ FSMC_BWTR1_ADDHLD_1

    - -
    -
    - - - - -
    #define FSMC_BWTR1_ADDHLD_1   (0x2UL << FSMC_BWTR1_ADDHLD_Pos)
    -
    -

    0x00000020

    - -
    -
    - -

    ◆ FSMC_BWTR1_ADDHLD_2

    - -
    -
    - - - - -
    #define FSMC_BWTR1_ADDHLD_2   (0x4UL << FSMC_BWTR1_ADDHLD_Pos)
    -
    -

    0x00000040

    - -
    -
    - -

    ◆ FSMC_BWTR1_ADDHLD_3

    - -
    -
    - - - - -
    #define FSMC_BWTR1_ADDHLD_3   (0x8UL << FSMC_BWTR1_ADDHLD_Pos)
    -
    -

    0x00000080

    - -
    -
    - -

    ◆ FSMC_BWTR1_DATAST_Pos

    - -
    -
    - - - - -
    #define FSMC_BWTR1_DATAST_Pos   (8U)
    -
    - -
    -
    - -

    ◆ FSMC_BWTR1_DATAST_Msk

    - -
    -
    - - - - -
    #define FSMC_BWTR1_DATAST_Msk   (0xFFUL << FSMC_BWTR1_DATAST_Pos)
    -
    -

    0x0000FF00

    - -
    -
    - -

    ◆ FSMC_BWTR1_DATAST

    - -
    -
    - - - - -
    #define FSMC_BWTR1_DATAST   FSMC_BWTR1_DATAST_Msk
    -
    -

    DATAST [7:0] bits (Data-phase duration)

    - -
    -
    - -

    ◆ FSMC_BWTR1_DATAST_0

    - -
    -
    - - - - -
    #define FSMC_BWTR1_DATAST_0   (0x01UL << FSMC_BWTR1_DATAST_Pos)
    -
    -

    0x00000100

    - -
    -
    - -

    ◆ FSMC_BWTR1_DATAST_1

    - -
    -
    - - - - -
    #define FSMC_BWTR1_DATAST_1   (0x02UL << FSMC_BWTR1_DATAST_Pos)
    -
    -

    0x00000200

    - -
    -
    - -

    ◆ FSMC_BWTR1_DATAST_2

    - -
    -
    - - - - -
    #define FSMC_BWTR1_DATAST_2   (0x04UL << FSMC_BWTR1_DATAST_Pos)
    -
    -

    0x00000400

    - -
    -
    - -

    ◆ FSMC_BWTR1_DATAST_3

    - -
    -
    - - - - -
    #define FSMC_BWTR1_DATAST_3   (0x08UL << FSMC_BWTR1_DATAST_Pos)
    -
    -

    0x00000800

    - -
    -
    - -

    ◆ FSMC_BWTR1_DATAST_4

    - -
    -
    - - - - -
    #define FSMC_BWTR1_DATAST_4   (0x10UL << FSMC_BWTR1_DATAST_Pos)
    -
    -

    0x00001000

    - -
    -
    - -

    ◆ FSMC_BWTR1_DATAST_5

    - -
    -
    - - - - -
    #define FSMC_BWTR1_DATAST_5   (0x20UL << FSMC_BWTR1_DATAST_Pos)
    -
    -

    0x00002000

    - -
    -
    - -

    ◆ FSMC_BWTR1_DATAST_6

    - -
    -
    - - - - -
    #define FSMC_BWTR1_DATAST_6   (0x40UL << FSMC_BWTR1_DATAST_Pos)
    -
    -

    0x00004000

    - -
    -
    - -

    ◆ FSMC_BWTR1_DATAST_7

    - -
    -
    - - - - -
    #define FSMC_BWTR1_DATAST_7   (0x80UL << FSMC_BWTR1_DATAST_Pos)
    -
    -

    0x00008000

    - -
    -
    - -

    ◆ FSMC_BWTR1_BUSTURN_Pos

    - -
    -
    - - - - -
    #define FSMC_BWTR1_BUSTURN_Pos   (16U)
    -
    - -
    -
    - -

    ◆ FSMC_BWTR1_BUSTURN_Msk

    - -
    -
    - - - - -
    #define FSMC_BWTR1_BUSTURN_Msk   (0xFUL << FSMC_BWTR1_BUSTURN_Pos)
    -
    -

    0x000F0000

    - -
    -
    - -

    ◆ FSMC_BWTR1_BUSTURN

    - -
    -
    - - - - -
    #define FSMC_BWTR1_BUSTURN   FSMC_BWTR1_BUSTURN_Msk
    -
    -

    BUSTURN[3:0] bits (Bus turnaround duration)

    - -
    -
    - -

    ◆ FSMC_BWTR1_BUSTURN_0

    - -
    -
    - - - - -
    #define FSMC_BWTR1_BUSTURN_0   (0x1UL << FSMC_BWTR1_BUSTURN_Pos)
    -
    -

    0x00010000

    - -
    -
    - -

    ◆ FSMC_BWTR1_BUSTURN_1

    - -
    -
    - - - - -
    #define FSMC_BWTR1_BUSTURN_1   (0x2UL << FSMC_BWTR1_BUSTURN_Pos)
    -
    -

    0x00020000

    - -
    -
    - -

    ◆ FSMC_BWTR1_BUSTURN_2

    - -
    -
    - - - - -
    #define FSMC_BWTR1_BUSTURN_2   (0x4UL << FSMC_BWTR1_BUSTURN_Pos)
    -
    -

    0x00040000

    - -
    -
    - -

    ◆ FSMC_BWTR1_BUSTURN_3

    - -
    -
    - - - - -
    #define FSMC_BWTR1_BUSTURN_3   (0x8UL << FSMC_BWTR1_BUSTURN_Pos)
    -
    -

    0x00080000

    - -
    -
    - -

    ◆ FSMC_BWTR1_ACCMOD_Pos

    - -
    -
    - - - - -
    #define FSMC_BWTR1_ACCMOD_Pos   (28U)
    -
    - -
    -
    - -

    ◆ FSMC_BWTR1_ACCMOD_Msk

    - -
    -
    - - - - -
    #define FSMC_BWTR1_ACCMOD_Msk   (0x3UL << FSMC_BWTR1_ACCMOD_Pos)
    -
    -

    0x30000000

    - -
    -
    - -

    ◆ FSMC_BWTR1_ACCMOD

    - -
    -
    - - - - -
    #define FSMC_BWTR1_ACCMOD   FSMC_BWTR1_ACCMOD_Msk
    -
    -

    ACCMOD[1:0] bits (Access mode)

    - -
    -
    - -

    ◆ FSMC_BWTR1_ACCMOD_0

    - -
    -
    - - - - -
    #define FSMC_BWTR1_ACCMOD_0   (0x1UL << FSMC_BWTR1_ACCMOD_Pos)
    -
    -

    0x10000000

    - -
    -
    - -

    ◆ FSMC_BWTR1_ACCMOD_1

    - -
    -
    - - - - -
    #define FSMC_BWTR1_ACCMOD_1   (0x2UL << FSMC_BWTR1_ACCMOD_Pos)
    -
    -

    0x20000000

    - -
    -
    - -

    ◆ FSMC_BWTR2_ADDSET_Pos

    - -
    -
    - - - - -
    #define FSMC_BWTR2_ADDSET_Pos   (0U)
    -
    - -
    -
    - -

    ◆ FSMC_BWTR2_ADDSET_Msk

    - -
    -
    - - - - -
    #define FSMC_BWTR2_ADDSET_Msk   (0xFUL << FSMC_BWTR2_ADDSET_Pos)
    -
    -

    0x0000000F

    - -
    -
    - -

    ◆ FSMC_BWTR2_ADDSET

    - -
    -
    - - - - -
    #define FSMC_BWTR2_ADDSET   FSMC_BWTR2_ADDSET_Msk
    -
    -

    ADDSET[3:0] bits (Address setup phase duration)

    - -
    -
    - -

    ◆ FSMC_BWTR2_ADDSET_0

    - -
    -
    - - - - -
    #define FSMC_BWTR2_ADDSET_0   (0x1UL << FSMC_BWTR2_ADDSET_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ FSMC_BWTR2_ADDSET_1

    - -
    -
    - - - - -
    #define FSMC_BWTR2_ADDSET_1   (0x2UL << FSMC_BWTR2_ADDSET_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ FSMC_BWTR2_ADDSET_2

    - -
    -
    - - - - -
    #define FSMC_BWTR2_ADDSET_2   (0x4UL << FSMC_BWTR2_ADDSET_Pos)
    -
    -

    0x00000004

    - -
    -
    - -

    ◆ FSMC_BWTR2_ADDSET_3

    - -
    -
    - - - - -
    #define FSMC_BWTR2_ADDSET_3   (0x8UL << FSMC_BWTR2_ADDSET_Pos)
    -
    -

    0x00000008

    - -
    -
    - -

    ◆ FSMC_BWTR2_ADDHLD_Pos

    - -
    -
    - - - - -
    #define FSMC_BWTR2_ADDHLD_Pos   (4U)
    -
    - -
    -
    - -

    ◆ FSMC_BWTR2_ADDHLD_Msk

    - -
    -
    - - - - -
    #define FSMC_BWTR2_ADDHLD_Msk   (0xFUL << FSMC_BWTR2_ADDHLD_Pos)
    -
    -

    0x000000F0

    - -
    -
    - -

    ◆ FSMC_BWTR2_ADDHLD

    - -
    -
    - - - - -
    #define FSMC_BWTR2_ADDHLD   FSMC_BWTR2_ADDHLD_Msk
    -
    -

    ADDHLD[3:0] bits (Address-hold phase duration)

    - -
    -
    - -

    ◆ FSMC_BWTR2_ADDHLD_0

    - -
    -
    - - - - -
    #define FSMC_BWTR2_ADDHLD_0   (0x1UL << FSMC_BWTR2_ADDHLD_Pos)
    -
    -

    0x00000010

    - -
    -
    - -

    ◆ FSMC_BWTR2_ADDHLD_1

    - -
    -
    - - - - -
    #define FSMC_BWTR2_ADDHLD_1   (0x2UL << FSMC_BWTR2_ADDHLD_Pos)
    -
    -

    0x00000020

    - -
    -
    - -

    ◆ FSMC_BWTR2_ADDHLD_2

    - -
    -
    - - - - -
    #define FSMC_BWTR2_ADDHLD_2   (0x4UL << FSMC_BWTR2_ADDHLD_Pos)
    -
    -

    0x00000040

    - -
    -
    - -

    ◆ FSMC_BWTR2_ADDHLD_3

    - -
    -
    - - - - -
    #define FSMC_BWTR2_ADDHLD_3   (0x8UL << FSMC_BWTR2_ADDHLD_Pos)
    -
    -

    0x00000080

    - -
    -
    - -

    ◆ FSMC_BWTR2_DATAST_Pos

    - -
    -
    - - - - -
    #define FSMC_BWTR2_DATAST_Pos   (8U)
    -
    - -
    -
    - -

    ◆ FSMC_BWTR2_DATAST_Msk

    - -
    -
    - - - - -
    #define FSMC_BWTR2_DATAST_Msk   (0xFFUL << FSMC_BWTR2_DATAST_Pos)
    -
    -

    0x0000FF00

    - -
    -
    - -

    ◆ FSMC_BWTR2_DATAST

    - -
    -
    - - - - -
    #define FSMC_BWTR2_DATAST   FSMC_BWTR2_DATAST_Msk
    -
    -

    DATAST [7:0] bits (Data-phase duration)

    - -
    -
    - -

    ◆ FSMC_BWTR2_DATAST_0

    - -
    -
    - - - - -
    #define FSMC_BWTR2_DATAST_0   (0x01UL << FSMC_BWTR2_DATAST_Pos)
    -
    -

    0x00000100

    - -
    -
    - -

    ◆ FSMC_BWTR2_DATAST_1

    - -
    -
    - - - - -
    #define FSMC_BWTR2_DATAST_1   (0x02UL << FSMC_BWTR2_DATAST_Pos)
    -
    -

    0x00000200

    - -
    -
    - -

    ◆ FSMC_BWTR2_DATAST_2

    - -
    -
    - - - - -
    #define FSMC_BWTR2_DATAST_2   (0x04UL << FSMC_BWTR2_DATAST_Pos)
    -
    -

    0x00000400

    - -
    -
    - -

    ◆ FSMC_BWTR2_DATAST_3

    - -
    -
    - - - - -
    #define FSMC_BWTR2_DATAST_3   (0x08UL << FSMC_BWTR2_DATAST_Pos)
    -
    -

    0x00000800

    - -
    -
    - -

    ◆ FSMC_BWTR2_DATAST_4

    - -
    -
    - - - - -
    #define FSMC_BWTR2_DATAST_4   (0x10UL << FSMC_BWTR2_DATAST_Pos)
    -
    -

    0x00001000

    - -
    -
    - -

    ◆ FSMC_BWTR2_DATAST_5

    - -
    -
    - - - - -
    #define FSMC_BWTR2_DATAST_5   (0x20UL << FSMC_BWTR2_DATAST_Pos)
    -
    -

    0x00002000

    - -
    -
    - -

    ◆ FSMC_BWTR2_DATAST_6

    - -
    -
    - - - - -
    #define FSMC_BWTR2_DATAST_6   (0x40UL << FSMC_BWTR2_DATAST_Pos)
    -
    -

    0x00004000

    - -
    -
    - -

    ◆ FSMC_BWTR2_DATAST_7

    - -
    -
    - - - - -
    #define FSMC_BWTR2_DATAST_7   (0x80UL << FSMC_BWTR2_DATAST_Pos)
    -
    -

    0x00008000

    - -
    -
    - -

    ◆ FSMC_BWTR2_BUSTURN_Pos

    - -
    -
    - - - - -
    #define FSMC_BWTR2_BUSTURN_Pos   (16U)
    -
    - -
    -
    - -

    ◆ FSMC_BWTR2_BUSTURN_Msk

    - -
    -
    - - - - -
    #define FSMC_BWTR2_BUSTURN_Msk   (0xFUL << FSMC_BWTR2_BUSTURN_Pos)
    -
    -

    0x000F0000

    - -
    -
    - -

    ◆ FSMC_BWTR2_BUSTURN

    - -
    -
    - - - - -
    #define FSMC_BWTR2_BUSTURN   FSMC_BWTR2_BUSTURN_Msk
    -
    -

    BUSTURN[3:0] bits (Bus turnaround duration)

    - -
    -
    - -

    ◆ FSMC_BWTR2_BUSTURN_0

    - -
    -
    - - - - -
    #define FSMC_BWTR2_BUSTURN_0   (0x1UL << FSMC_BWTR2_BUSTURN_Pos)
    -
    -

    0x00010000

    - -
    -
    - -

    ◆ FSMC_BWTR2_BUSTURN_1

    - -
    -
    - - - - -
    #define FSMC_BWTR2_BUSTURN_1   (0x2UL << FSMC_BWTR2_BUSTURN_Pos)
    -
    -

    0x00020000

    - -
    -
    - -

    ◆ FSMC_BWTR2_BUSTURN_2

    - -
    -
    - - - - -
    #define FSMC_BWTR2_BUSTURN_2   (0x4UL << FSMC_BWTR2_BUSTURN_Pos)
    -
    -

    0x00040000

    - -
    -
    - -

    ◆ FSMC_BWTR2_BUSTURN_3

    - -
    -
    - - - - -
    #define FSMC_BWTR2_BUSTURN_3   (0x8UL << FSMC_BWTR2_BUSTURN_Pos)
    -
    -

    0x00080000

    - -
    -
    - -

    ◆ FSMC_BWTR2_ACCMOD_Pos

    - -
    -
    - - - - -
    #define FSMC_BWTR2_ACCMOD_Pos   (28U)
    -
    - -
    -
    - -

    ◆ FSMC_BWTR2_ACCMOD_Msk

    - -
    -
    - - - - -
    #define FSMC_BWTR2_ACCMOD_Msk   (0x3UL << FSMC_BWTR2_ACCMOD_Pos)
    -
    -

    0x30000000

    - -
    -
    - -

    ◆ FSMC_BWTR2_ACCMOD

    - -
    -
    - - - - -
    #define FSMC_BWTR2_ACCMOD   FSMC_BWTR2_ACCMOD_Msk
    -
    -

    ACCMOD[1:0] bits (Access mode)

    - -
    -
    - -

    ◆ FSMC_BWTR2_ACCMOD_0

    - -
    -
    - - - - -
    #define FSMC_BWTR2_ACCMOD_0   (0x1UL << FSMC_BWTR2_ACCMOD_Pos)
    -
    -

    0x10000000

    - -
    -
    - -

    ◆ FSMC_BWTR2_ACCMOD_1

    - -
    -
    - - - - -
    #define FSMC_BWTR2_ACCMOD_1   (0x2UL << FSMC_BWTR2_ACCMOD_Pos)
    -
    -

    0x20000000

    - -
    -
    - -

    ◆ FSMC_BWTR3_ADDSET_Pos

    - -
    -
    - - - - -
    #define FSMC_BWTR3_ADDSET_Pos   (0U)
    -
    - -
    -
    - -

    ◆ FSMC_BWTR3_ADDSET_Msk

    - -
    -
    - - - - -
    #define FSMC_BWTR3_ADDSET_Msk   (0xFUL << FSMC_BWTR3_ADDSET_Pos)
    -
    -

    0x0000000F

    - -
    -
    - -

    ◆ FSMC_BWTR3_ADDSET

    - -
    -
    - - - - -
    #define FSMC_BWTR3_ADDSET   FSMC_BWTR3_ADDSET_Msk
    -
    -

    ADDSET[3:0] bits (Address setup phase duration)

    - -
    -
    - -

    ◆ FSMC_BWTR3_ADDSET_0

    - -
    -
    - - - - -
    #define FSMC_BWTR3_ADDSET_0   (0x1UL << FSMC_BWTR3_ADDSET_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ FSMC_BWTR3_ADDSET_1

    - -
    -
    - - - - -
    #define FSMC_BWTR3_ADDSET_1   (0x2UL << FSMC_BWTR3_ADDSET_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ FSMC_BWTR3_ADDSET_2

    - -
    -
    - - - - -
    #define FSMC_BWTR3_ADDSET_2   (0x4UL << FSMC_BWTR3_ADDSET_Pos)
    -
    -

    0x00000004

    - -
    -
    - -

    ◆ FSMC_BWTR3_ADDSET_3

    - -
    -
    - - - - -
    #define FSMC_BWTR3_ADDSET_3   (0x8UL << FSMC_BWTR3_ADDSET_Pos)
    -
    -

    0x00000008

    - -
    -
    - -

    ◆ FSMC_BWTR3_ADDHLD_Pos

    - -
    -
    - - - - -
    #define FSMC_BWTR3_ADDHLD_Pos   (4U)
    -
    - -
    -
    - -

    ◆ FSMC_BWTR3_ADDHLD_Msk

    - -
    -
    - - - - -
    #define FSMC_BWTR3_ADDHLD_Msk   (0xFUL << FSMC_BWTR3_ADDHLD_Pos)
    -
    -

    0x000000F0

    - -
    -
    - -

    ◆ FSMC_BWTR3_ADDHLD

    - -
    -
    - - - - -
    #define FSMC_BWTR3_ADDHLD   FSMC_BWTR3_ADDHLD_Msk
    -
    -

    ADDHLD[3:0] bits (Address-hold phase duration)

    - -
    -
    - -

    ◆ FSMC_BWTR3_ADDHLD_0

    - -
    -
    - - - - -
    #define FSMC_BWTR3_ADDHLD_0   (0x1UL << FSMC_BWTR3_ADDHLD_Pos)
    -
    -

    0x00000010

    - -
    -
    - -

    ◆ FSMC_BWTR3_ADDHLD_1

    - -
    -
    - - - - -
    #define FSMC_BWTR3_ADDHLD_1   (0x2UL << FSMC_BWTR3_ADDHLD_Pos)
    -
    -

    0x00000020

    - -
    -
    - -

    ◆ FSMC_BWTR3_ADDHLD_2

    - -
    -
    - - - - -
    #define FSMC_BWTR3_ADDHLD_2   (0x4UL << FSMC_BWTR3_ADDHLD_Pos)
    -
    -

    0x00000040

    - -
    -
    - -

    ◆ FSMC_BWTR3_ADDHLD_3

    - -
    -
    - - - - -
    #define FSMC_BWTR3_ADDHLD_3   (0x8UL << FSMC_BWTR3_ADDHLD_Pos)
    -
    -

    0x00000080

    - -
    -
    - -

    ◆ FSMC_BWTR3_DATAST_Pos

    - -
    -
    - - - - -
    #define FSMC_BWTR3_DATAST_Pos   (8U)
    -
    - -
    -
    - -

    ◆ FSMC_BWTR3_DATAST_Msk

    - -
    -
    - - - - -
    #define FSMC_BWTR3_DATAST_Msk   (0xFFUL << FSMC_BWTR3_DATAST_Pos)
    -
    -

    0x0000FF00

    - -
    -
    - -

    ◆ FSMC_BWTR3_DATAST

    - -
    -
    - - - - -
    #define FSMC_BWTR3_DATAST   FSMC_BWTR3_DATAST_Msk
    -
    -

    DATAST [7:0] bits (Data-phase duration)

    - -
    -
    - -

    ◆ FSMC_BWTR3_DATAST_0

    - -
    -
    - - - - -
    #define FSMC_BWTR3_DATAST_0   (0x01UL << FSMC_BWTR3_DATAST_Pos)
    -
    -

    0x00000100

    - -
    -
    - -

    ◆ FSMC_BWTR3_DATAST_1

    - -
    -
    - - - - -
    #define FSMC_BWTR3_DATAST_1   (0x02UL << FSMC_BWTR3_DATAST_Pos)
    -
    -

    0x00000200

    - -
    -
    - -

    ◆ FSMC_BWTR3_DATAST_2

    - -
    -
    - - - - -
    #define FSMC_BWTR3_DATAST_2   (0x04UL << FSMC_BWTR3_DATAST_Pos)
    -
    -

    0x00000400

    - -
    -
    - -

    ◆ FSMC_BWTR3_DATAST_3

    - -
    -
    - - - - -
    #define FSMC_BWTR3_DATAST_3   (0x08UL << FSMC_BWTR3_DATAST_Pos)
    -
    -

    0x00000800

    - -
    -
    - -

    ◆ FSMC_BWTR3_DATAST_4

    - -
    -
    - - - - -
    #define FSMC_BWTR3_DATAST_4   (0x10UL << FSMC_BWTR3_DATAST_Pos)
    -
    -

    0x00001000

    - -
    -
    - -

    ◆ FSMC_BWTR3_DATAST_5

    - -
    -
    - - - - -
    #define FSMC_BWTR3_DATAST_5   (0x20UL << FSMC_BWTR3_DATAST_Pos)
    -
    -

    0x00002000

    - -
    -
    - -

    ◆ FSMC_BWTR3_DATAST_6

    - -
    -
    - - - - -
    #define FSMC_BWTR3_DATAST_6   (0x40UL << FSMC_BWTR3_DATAST_Pos)
    -
    -

    0x00004000

    - -
    -
    - -

    ◆ FSMC_BWTR3_DATAST_7

    - -
    -
    - - - - -
    #define FSMC_BWTR3_DATAST_7   (0x80UL << FSMC_BWTR3_DATAST_Pos)
    -
    -

    0x00008000

    - -
    -
    - -

    ◆ FSMC_BWTR3_BUSTURN_Pos

    - -
    -
    - - - - -
    #define FSMC_BWTR3_BUSTURN_Pos   (16U)
    -
    - -
    -
    - -

    ◆ FSMC_BWTR3_BUSTURN_Msk

    - -
    -
    - - - - -
    #define FSMC_BWTR3_BUSTURN_Msk   (0xFUL << FSMC_BWTR3_BUSTURN_Pos)
    -
    -

    0x000F0000

    - -
    -
    - -

    ◆ FSMC_BWTR3_BUSTURN

    - -
    -
    - - - - -
    #define FSMC_BWTR3_BUSTURN   FSMC_BWTR3_BUSTURN_Msk
    -
    -

    BUSTURN[3:0] bits (Bus turnaround duration)

    - -
    -
    - -

    ◆ FSMC_BWTR3_BUSTURN_0

    - -
    -
    - - - - -
    #define FSMC_BWTR3_BUSTURN_0   (0x1UL << FSMC_BWTR3_BUSTURN_Pos)
    -
    -

    0x00010000

    - -
    -
    - -

    ◆ FSMC_BWTR3_BUSTURN_1

    - -
    -
    - - - - -
    #define FSMC_BWTR3_BUSTURN_1   (0x2UL << FSMC_BWTR3_BUSTURN_Pos)
    -
    -

    0x00020000

    - -
    -
    - -

    ◆ FSMC_BWTR3_BUSTURN_2

    - -
    -
    - - - - -
    #define FSMC_BWTR3_BUSTURN_2   (0x4UL << FSMC_BWTR3_BUSTURN_Pos)
    -
    -

    0x00040000

    - -
    -
    - -

    ◆ FSMC_BWTR3_BUSTURN_3

    - -
    -
    - - - - -
    #define FSMC_BWTR3_BUSTURN_3   (0x8UL << FSMC_BWTR3_BUSTURN_Pos)
    -
    -

    0x00080000

    - -
    -
    - -

    ◆ FSMC_BWTR3_ACCMOD_Pos

    - -
    -
    - - - - -
    #define FSMC_BWTR3_ACCMOD_Pos   (28U)
    -
    - -
    -
    - -

    ◆ FSMC_BWTR3_ACCMOD_Msk

    - -
    -
    - - - - -
    #define FSMC_BWTR3_ACCMOD_Msk   (0x3UL << FSMC_BWTR3_ACCMOD_Pos)
    -
    -

    0x30000000

    - -
    -
    - -

    ◆ FSMC_BWTR3_ACCMOD

    - -
    -
    - - - - -
    #define FSMC_BWTR3_ACCMOD   FSMC_BWTR3_ACCMOD_Msk
    -
    -

    ACCMOD[1:0] bits (Access mode)

    - -
    -
    - -

    ◆ FSMC_BWTR3_ACCMOD_0

    - -
    -
    - - - - -
    #define FSMC_BWTR3_ACCMOD_0   (0x1UL << FSMC_BWTR3_ACCMOD_Pos)
    -
    -

    0x10000000

    - -
    -
    - -

    ◆ FSMC_BWTR3_ACCMOD_1

    - -
    -
    - - - - -
    #define FSMC_BWTR3_ACCMOD_1   (0x2UL << FSMC_BWTR3_ACCMOD_Pos)
    -
    -

    0x20000000

    - -
    -
    - -

    ◆ FSMC_BWTR4_ADDSET_Pos

    - -
    -
    - - - - -
    #define FSMC_BWTR4_ADDSET_Pos   (0U)
    -
    - -
    -
    - -

    ◆ FSMC_BWTR4_ADDSET_Msk

    - -
    -
    - - - - -
    #define FSMC_BWTR4_ADDSET_Msk   (0xFUL << FSMC_BWTR4_ADDSET_Pos)
    -
    -

    0x0000000F

    - -
    -
    - -

    ◆ FSMC_BWTR4_ADDSET

    - -
    -
    - - - - -
    #define FSMC_BWTR4_ADDSET   FSMC_BWTR4_ADDSET_Msk
    -
    -

    ADDSET[3:0] bits (Address setup phase duration)

    - -
    -
    - -

    ◆ FSMC_BWTR4_ADDSET_0

    - -
    -
    - - - - -
    #define FSMC_BWTR4_ADDSET_0   (0x1UL << FSMC_BWTR4_ADDSET_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ FSMC_BWTR4_ADDSET_1

    - -
    -
    - - - - -
    #define FSMC_BWTR4_ADDSET_1   (0x2UL << FSMC_BWTR4_ADDSET_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ FSMC_BWTR4_ADDSET_2

    - -
    -
    - - - - -
    #define FSMC_BWTR4_ADDSET_2   (0x4UL << FSMC_BWTR4_ADDSET_Pos)
    -
    -

    0x00000004

    - -
    -
    - -

    ◆ FSMC_BWTR4_ADDSET_3

    - -
    -
    - - - - -
    #define FSMC_BWTR4_ADDSET_3   (0x8UL << FSMC_BWTR4_ADDSET_Pos)
    -
    -

    0x00000008

    - -
    -
    - -

    ◆ FSMC_BWTR4_ADDHLD_Pos

    - -
    -
    - - - - -
    #define FSMC_BWTR4_ADDHLD_Pos   (4U)
    -
    - -
    -
    - -

    ◆ FSMC_BWTR4_ADDHLD_Msk

    - -
    -
    - - - - -
    #define FSMC_BWTR4_ADDHLD_Msk   (0xFUL << FSMC_BWTR4_ADDHLD_Pos)
    -
    -

    0x000000F0

    - -
    -
    - -

    ◆ FSMC_BWTR4_ADDHLD

    - -
    -
    - - - - -
    #define FSMC_BWTR4_ADDHLD   FSMC_BWTR4_ADDHLD_Msk
    -
    -

    ADDHLD[3:0] bits (Address-hold phase duration)

    - -
    -
    - -

    ◆ FSMC_BWTR4_ADDHLD_0

    - -
    -
    - - - - -
    #define FSMC_BWTR4_ADDHLD_0   (0x1UL << FSMC_BWTR4_ADDHLD_Pos)
    -
    -

    0x00000010

    - -
    -
    - -

    ◆ FSMC_BWTR4_ADDHLD_1

    - -
    -
    - - - - -
    #define FSMC_BWTR4_ADDHLD_1   (0x2UL << FSMC_BWTR4_ADDHLD_Pos)
    -
    -

    0x00000020

    - -
    -
    - -

    ◆ FSMC_BWTR4_ADDHLD_2

    - -
    -
    - - - - -
    #define FSMC_BWTR4_ADDHLD_2   (0x4UL << FSMC_BWTR4_ADDHLD_Pos)
    -
    -

    0x00000040

    - -
    -
    - -

    ◆ FSMC_BWTR4_ADDHLD_3

    - -
    -
    - - - - -
    #define FSMC_BWTR4_ADDHLD_3   (0x8UL << FSMC_BWTR4_ADDHLD_Pos)
    -
    -

    0x00000080

    - -
    -
    - -

    ◆ FSMC_BWTR4_DATAST_Pos

    - -
    -
    - - - - -
    #define FSMC_BWTR4_DATAST_Pos   (8U)
    -
    - -
    -
    - -

    ◆ FSMC_BWTR4_DATAST_Msk

    - -
    -
    - - - - -
    #define FSMC_BWTR4_DATAST_Msk   (0xFFUL << FSMC_BWTR4_DATAST_Pos)
    -
    -

    0x0000FF00

    - -
    -
    - -

    ◆ FSMC_BWTR4_DATAST

    - -
    -
    - - - - -
    #define FSMC_BWTR4_DATAST   FSMC_BWTR4_DATAST_Msk
    -
    -

    DATAST [3:0] bits (Data-phase duration)

    - -
    -
    - -

    ◆ FSMC_BWTR4_DATAST_0

    - -
    -
    - - - - -
    #define FSMC_BWTR4_DATAST_0   0x00000100U
    -
    -

    Bit 0

    - -
    -
    - -

    ◆ FSMC_BWTR4_DATAST_1

    - -
    -
    - - - - -
    #define FSMC_BWTR4_DATAST_1   0x00000200U
    -
    -

    Bit 1

    - -
    -
    - -

    ◆ FSMC_BWTR4_DATAST_2

    - -
    -
    - - - - -
    #define FSMC_BWTR4_DATAST_2   0x00000400U
    -
    -

    Bit 2

    - -
    -
    - -

    ◆ FSMC_BWTR4_DATAST_3

    - -
    -
    - - - - -
    #define FSMC_BWTR4_DATAST_3   0x00000800U
    -
    -

    Bit 3

    - -
    -
    - -

    ◆ FSMC_BWTR4_DATAST_4

    - -
    -
    - - - - -
    #define FSMC_BWTR4_DATAST_4   0x00001000U
    -
    -

    Bit 4

    - -
    -
    - -

    ◆ FSMC_BWTR4_DATAST_5

    - -
    -
    - - - - -
    #define FSMC_BWTR4_DATAST_5   0x00002000U
    -
    -

    Bit 5

    - -
    -
    - -

    ◆ FSMC_BWTR4_DATAST_6

    - -
    -
    - - - - -
    #define FSMC_BWTR4_DATAST_6   0x00004000U
    -
    -

    Bit 6

    - -
    -
    - -

    ◆ FSMC_BWTR4_DATAST_7

    - -
    -
    - - - - -
    #define FSMC_BWTR4_DATAST_7   0x00008000U
    -
    -

    Bit 7

    - -
    -
    - -

    ◆ FSMC_BWTR4_BUSTURN_Pos

    - -
    -
    - - - - -
    #define FSMC_BWTR4_BUSTURN_Pos   (16U)
    -
    - -
    -
    - -

    ◆ FSMC_BWTR4_BUSTURN_Msk

    - -
    -
    - - - - -
    #define FSMC_BWTR4_BUSTURN_Msk   (0xFUL << FSMC_BWTR4_BUSTURN_Pos)
    -
    -

    0x000F0000

    - -
    -
    - -

    ◆ FSMC_BWTR4_BUSTURN

    - -
    -
    - - - - -
    #define FSMC_BWTR4_BUSTURN   FSMC_BWTR4_BUSTURN_Msk
    -
    -

    BUSTURN[3:0] bits (Bus turnaround duration)

    - -
    -
    - -

    ◆ FSMC_BWTR4_BUSTURN_0

    - -
    -
    - - - - -
    #define FSMC_BWTR4_BUSTURN_0   (0x1UL << FSMC_BWTR4_BUSTURN_Pos)
    -
    -

    0x00010000

    - -
    -
    - -

    ◆ FSMC_BWTR4_BUSTURN_1

    - -
    -
    - - - - -
    #define FSMC_BWTR4_BUSTURN_1   (0x2UL << FSMC_BWTR4_BUSTURN_Pos)
    -
    -

    0x00020000

    - -
    -
    - -

    ◆ FSMC_BWTR4_BUSTURN_2

    - -
    -
    - - - - -
    #define FSMC_BWTR4_BUSTURN_2   (0x4UL << FSMC_BWTR4_BUSTURN_Pos)
    -
    -

    0x00040000

    - -
    -
    - -

    ◆ FSMC_BWTR4_BUSTURN_3

    - -
    -
    - - - - -
    #define FSMC_BWTR4_BUSTURN_3   (0x8UL << FSMC_BWTR4_BUSTURN_Pos)
    -
    -

    0x00080000

    - -
    -
    - -

    ◆ FSMC_BWTR4_ACCMOD_Pos

    - -
    -
    - - - - -
    #define FSMC_BWTR4_ACCMOD_Pos   (28U)
    -
    - -
    -
    - -

    ◆ FSMC_BWTR4_ACCMOD_Msk

    - -
    -
    - - - - -
    #define FSMC_BWTR4_ACCMOD_Msk   (0x3UL << FSMC_BWTR4_ACCMOD_Pos)
    -
    -

    0x30000000

    - -
    -
    - -

    ◆ FSMC_BWTR4_ACCMOD

    - -
    -
    - - - - -
    #define FSMC_BWTR4_ACCMOD   FSMC_BWTR4_ACCMOD_Msk
    -
    -

    ACCMOD[1:0] bits (Access mode)

    - -
    -
    - -

    ◆ FSMC_BWTR4_ACCMOD_0

    - -
    -
    - - - - -
    #define FSMC_BWTR4_ACCMOD_0   (0x1UL << FSMC_BWTR4_ACCMOD_Pos)
    -
    -

    0x10000000

    - -
    -
    - -

    ◆ FSMC_BWTR4_ACCMOD_1

    - -
    -
    - - - - -
    #define FSMC_BWTR4_ACCMOD_1   (0x2UL << FSMC_BWTR4_ACCMOD_Pos)
    -
    -

    0x20000000

    - -
    -
    - -

    ◆ FSMC_PCR2_PWAITEN_Pos

    - -
    -
    - - - - -
    #define FSMC_PCR2_PWAITEN_Pos   (1U)
    -
    - -
    -
    - -

    ◆ FSMC_PCR2_PWAITEN_Msk

    - -
    -
    - - - - -
    #define FSMC_PCR2_PWAITEN_Msk   (0x1UL << FSMC_PCR2_PWAITEN_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ FSMC_PCR2_PWAITEN

    - -
    -
    - - - - -
    #define FSMC_PCR2_PWAITEN   FSMC_PCR2_PWAITEN_Msk
    -
    -

    Wait feature enable bit

    - -
    -
    - -

    ◆ FSMC_PCR2_PBKEN_Pos

    - -
    -
    - - - - -
    #define FSMC_PCR2_PBKEN_Pos   (2U)
    -
    - -
    -
    - -

    ◆ FSMC_PCR2_PBKEN_Msk

    - -
    -
    - - - - -
    #define FSMC_PCR2_PBKEN_Msk   (0x1UL << FSMC_PCR2_PBKEN_Pos)
    -
    -

    0x00000004

    - -
    -
    - -

    ◆ FSMC_PCR2_PBKEN

    - -
    -
    - - - - -
    #define FSMC_PCR2_PBKEN   FSMC_PCR2_PBKEN_Msk
    -
    -

    PC Card/NAND Flash memory bank enable bit

    - -
    -
    - -

    ◆ FSMC_PCR2_PTYP_Pos

    - -
    -
    - - - - -
    #define FSMC_PCR2_PTYP_Pos   (3U)
    -
    - -
    -
    - -

    ◆ FSMC_PCR2_PTYP_Msk

    - -
    -
    - - - - -
    #define FSMC_PCR2_PTYP_Msk   (0x1UL << FSMC_PCR2_PTYP_Pos)
    -
    -

    0x00000008

    - -
    -
    - -

    ◆ FSMC_PCR2_PTYP

    - -
    -
    - - - - -
    #define FSMC_PCR2_PTYP   FSMC_PCR2_PTYP_Msk
    -
    -

    Memory type

    - -
    -
    - -

    ◆ FSMC_PCR2_PWID_Pos

    - -
    -
    - - - - -
    #define FSMC_PCR2_PWID_Pos   (4U)
    -
    - -
    -
    - -

    ◆ FSMC_PCR2_PWID_Msk

    - -
    -
    - - - - -
    #define FSMC_PCR2_PWID_Msk   (0x3UL << FSMC_PCR2_PWID_Pos)
    -
    -

    0x00000030

    - -
    -
    - -

    ◆ FSMC_PCR2_PWID

    - -
    -
    - - - - -
    #define FSMC_PCR2_PWID   FSMC_PCR2_PWID_Msk
    -
    -

    PWID[1:0] bits (NAND Flash databus width)

    - -
    -
    - -

    ◆ FSMC_PCR2_PWID_0

    - -
    -
    - - - - -
    #define FSMC_PCR2_PWID_0   (0x1UL << FSMC_PCR2_PWID_Pos)
    -
    -

    0x00000010

    - -
    -
    - -

    ◆ FSMC_PCR2_PWID_1

    - -
    -
    - - - - -
    #define FSMC_PCR2_PWID_1   (0x2UL << FSMC_PCR2_PWID_Pos)
    -
    -

    0x00000020

    - -
    -
    - -

    ◆ FSMC_PCR2_ECCEN_Pos

    - -
    -
    - - - - -
    #define FSMC_PCR2_ECCEN_Pos   (6U)
    -
    - -
    -
    - -

    ◆ FSMC_PCR2_ECCEN_Msk

    - -
    -
    - - - - -
    #define FSMC_PCR2_ECCEN_Msk   (0x1UL << FSMC_PCR2_ECCEN_Pos)
    -
    -

    0x00000040

    - -
    -
    - -

    ◆ FSMC_PCR2_ECCEN

    - -
    -
    - - - - -
    #define FSMC_PCR2_ECCEN   FSMC_PCR2_ECCEN_Msk
    -
    -

    ECC computation logic enable bit

    - -
    -
    - -

    ◆ FSMC_PCR2_TCLR_Pos

    - -
    -
    - - - - -
    #define FSMC_PCR2_TCLR_Pos   (9U)
    -
    - -
    -
    - -

    ◆ FSMC_PCR2_TCLR_Msk

    - -
    -
    - - - - -
    #define FSMC_PCR2_TCLR_Msk   (0xFUL << FSMC_PCR2_TCLR_Pos)
    -
    -

    0x00001E00

    - -
    -
    - -

    ◆ FSMC_PCR2_TCLR

    - -
    -
    - - - - -
    #define FSMC_PCR2_TCLR   FSMC_PCR2_TCLR_Msk
    -
    -

    TCLR[3:0] bits (CLE to RE delay)

    - -
    -
    - -

    ◆ FSMC_PCR2_TCLR_0

    - -
    -
    - - - - -
    #define FSMC_PCR2_TCLR_0   (0x1UL << FSMC_PCR2_TCLR_Pos)
    -
    -

    0x00000200

    - -
    -
    - -

    ◆ FSMC_PCR2_TCLR_1

    - -
    -
    - - - - -
    #define FSMC_PCR2_TCLR_1   (0x2UL << FSMC_PCR2_TCLR_Pos)
    -
    -

    0x00000400

    - -
    -
    - -

    ◆ FSMC_PCR2_TCLR_2

    - -
    -
    - - - - -
    #define FSMC_PCR2_TCLR_2   (0x4UL << FSMC_PCR2_TCLR_Pos)
    -
    -

    0x00000800

    - -
    -
    - -

    ◆ FSMC_PCR2_TCLR_3

    - -
    -
    - - - - -
    #define FSMC_PCR2_TCLR_3   (0x8UL << FSMC_PCR2_TCLR_Pos)
    -
    -

    0x00001000

    - -
    -
    - -

    ◆ FSMC_PCR2_TAR_Pos

    - -
    -
    - - - - -
    #define FSMC_PCR2_TAR_Pos   (13U)
    -
    - -
    -
    - -

    ◆ FSMC_PCR2_TAR_Msk

    - -
    -
    - - - - -
    #define FSMC_PCR2_TAR_Msk   (0xFUL << FSMC_PCR2_TAR_Pos)
    -
    -

    0x0001E000

    - -
    -
    - -

    ◆ FSMC_PCR2_TAR

    - -
    -
    - - - - -
    #define FSMC_PCR2_TAR   FSMC_PCR2_TAR_Msk
    -
    -

    TAR[3:0] bits (ALE to RE delay)

    - -
    -
    - -

    ◆ FSMC_PCR2_TAR_0

    - -
    -
    - - - - -
    #define FSMC_PCR2_TAR_0   (0x1UL << FSMC_PCR2_TAR_Pos)
    -
    -

    0x00002000

    - -
    -
    - -

    ◆ FSMC_PCR2_TAR_1

    - -
    -
    - - - - -
    #define FSMC_PCR2_TAR_1   (0x2UL << FSMC_PCR2_TAR_Pos)
    -
    -

    0x00004000

    - -
    -
    - -

    ◆ FSMC_PCR2_TAR_2

    - -
    -
    - - - - -
    #define FSMC_PCR2_TAR_2   (0x4UL << FSMC_PCR2_TAR_Pos)
    -
    -

    0x00008000

    - -
    -
    - -

    ◆ FSMC_PCR2_TAR_3

    - -
    -
    - - - - -
    #define FSMC_PCR2_TAR_3   (0x8UL << FSMC_PCR2_TAR_Pos)
    -
    -

    0x00010000

    - -
    -
    - -

    ◆ FSMC_PCR2_ECCPS_Pos

    - -
    -
    - - - - -
    #define FSMC_PCR2_ECCPS_Pos   (17U)
    -
    - -
    -
    - -

    ◆ FSMC_PCR2_ECCPS_Msk

    - -
    -
    - - - - -
    #define FSMC_PCR2_ECCPS_Msk   (0x7UL << FSMC_PCR2_ECCPS_Pos)
    -
    -

    0x000E0000

    - -
    -
    - -

    ◆ FSMC_PCR2_ECCPS

    - -
    -
    - - - - -
    #define FSMC_PCR2_ECCPS   FSMC_PCR2_ECCPS_Msk
    -
    -

    ECCPS[1:0] bits (ECC page size)

    - -
    -
    - -

    ◆ FSMC_PCR2_ECCPS_0

    - -
    -
    - - - - -
    #define FSMC_PCR2_ECCPS_0   (0x1UL << FSMC_PCR2_ECCPS_Pos)
    -
    -

    0x00020000

    - -
    -
    - -

    ◆ FSMC_PCR2_ECCPS_1

    - -
    -
    - - - - -
    #define FSMC_PCR2_ECCPS_1   (0x2UL << FSMC_PCR2_ECCPS_Pos)
    -
    -

    0x00040000

    - -
    -
    - -

    ◆ FSMC_PCR2_ECCPS_2

    - -
    -
    - - - - -
    #define FSMC_PCR2_ECCPS_2   (0x4UL << FSMC_PCR2_ECCPS_Pos)
    -
    -

    0x00080000

    - -
    -
    - -

    ◆ FSMC_PCR3_PWAITEN_Pos

    - -
    -
    - - - - -
    #define FSMC_PCR3_PWAITEN_Pos   (1U)
    -
    - -
    -
    - -

    ◆ FSMC_PCR3_PWAITEN_Msk

    - -
    -
    - - - - -
    #define FSMC_PCR3_PWAITEN_Msk   (0x1UL << FSMC_PCR3_PWAITEN_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ FSMC_PCR3_PWAITEN

    - -
    -
    - - - - -
    #define FSMC_PCR3_PWAITEN   FSMC_PCR3_PWAITEN_Msk
    -
    -

    Wait feature enable bit

    - -
    -
    - -

    ◆ FSMC_PCR3_PBKEN_Pos

    - -
    -
    - - - - -
    #define FSMC_PCR3_PBKEN_Pos   (2U)
    -
    - -
    -
    - -

    ◆ FSMC_PCR3_PBKEN_Msk

    - -
    -
    - - - - -
    #define FSMC_PCR3_PBKEN_Msk   (0x1UL << FSMC_PCR3_PBKEN_Pos)
    -
    -

    0x00000004

    - -
    -
    - -

    ◆ FSMC_PCR3_PBKEN

    - -
    -
    - - - - -
    #define FSMC_PCR3_PBKEN   FSMC_PCR3_PBKEN_Msk
    -
    -

    PC Card/NAND Flash memory bank enable bit

    - -
    -
    - -

    ◆ FSMC_PCR3_PTYP_Pos

    - -
    -
    - - - - -
    #define FSMC_PCR3_PTYP_Pos   (3U)
    -
    - -
    -
    - -

    ◆ FSMC_PCR3_PTYP_Msk

    - -
    -
    - - - - -
    #define FSMC_PCR3_PTYP_Msk   (0x1UL << FSMC_PCR3_PTYP_Pos)
    -
    -

    0x00000008

    - -
    -
    - -

    ◆ FSMC_PCR3_PTYP

    - -
    -
    - - - - -
    #define FSMC_PCR3_PTYP   FSMC_PCR3_PTYP_Msk
    -
    -

    Memory type

    - -
    -
    - -

    ◆ FSMC_PCR3_PWID_Pos

    - -
    -
    - - - - -
    #define FSMC_PCR3_PWID_Pos   (4U)
    -
    - -
    -
    - -

    ◆ FSMC_PCR3_PWID_Msk

    - -
    -
    - - - - -
    #define FSMC_PCR3_PWID_Msk   (0x3UL << FSMC_PCR3_PWID_Pos)
    -
    -

    0x00000030

    - -
    -
    - -

    ◆ FSMC_PCR3_PWID

    - -
    -
    - - - - -
    #define FSMC_PCR3_PWID   FSMC_PCR3_PWID_Msk
    -
    -

    PWID[1:0] bits (NAND Flash databus width)

    - -
    -
    - -

    ◆ FSMC_PCR3_PWID_0

    - -
    -
    - - - - -
    #define FSMC_PCR3_PWID_0   (0x1UL << FSMC_PCR3_PWID_Pos)
    -
    -

    0x00000010

    - -
    -
    - -

    ◆ FSMC_PCR3_PWID_1

    - -
    -
    - - - - -
    #define FSMC_PCR3_PWID_1   (0x2UL << FSMC_PCR3_PWID_Pos)
    -
    -

    0x00000020

    - -
    -
    - -

    ◆ FSMC_PCR3_ECCEN_Pos

    - -
    -
    - - - - -
    #define FSMC_PCR3_ECCEN_Pos   (6U)
    -
    - -
    -
    - -

    ◆ FSMC_PCR3_ECCEN_Msk

    - -
    -
    - - - - -
    #define FSMC_PCR3_ECCEN_Msk   (0x1UL << FSMC_PCR3_ECCEN_Pos)
    -
    -

    0x00000040

    - -
    -
    - -

    ◆ FSMC_PCR3_ECCEN

    - -
    -
    - - - - -
    #define FSMC_PCR3_ECCEN   FSMC_PCR3_ECCEN_Msk
    -
    -

    ECC computation logic enable bit

    - -
    -
    - -

    ◆ FSMC_PCR3_TCLR_Pos

    - -
    -
    - - - - -
    #define FSMC_PCR3_TCLR_Pos   (9U)
    -
    - -
    -
    - -

    ◆ FSMC_PCR3_TCLR_Msk

    - -
    -
    - - - - -
    #define FSMC_PCR3_TCLR_Msk   (0xFUL << FSMC_PCR3_TCLR_Pos)
    -
    -

    0x00001E00

    - -
    -
    - -

    ◆ FSMC_PCR3_TCLR

    - -
    -
    - - - - -
    #define FSMC_PCR3_TCLR   FSMC_PCR3_TCLR_Msk
    -
    -

    TCLR[3:0] bits (CLE to RE delay)

    - -
    -
    - -

    ◆ FSMC_PCR3_TCLR_0

    - -
    -
    - - - - -
    #define FSMC_PCR3_TCLR_0   (0x1UL << FSMC_PCR3_TCLR_Pos)
    -
    -

    0x00000200

    - -
    -
    - -

    ◆ FSMC_PCR3_TCLR_1

    - -
    -
    - - - - -
    #define FSMC_PCR3_TCLR_1   (0x2UL << FSMC_PCR3_TCLR_Pos)
    -
    -

    0x00000400

    - -
    -
    - -

    ◆ FSMC_PCR3_TCLR_2

    - -
    -
    - - - - -
    #define FSMC_PCR3_TCLR_2   (0x4UL << FSMC_PCR3_TCLR_Pos)
    -
    -

    0x00000800

    - -
    -
    - -

    ◆ FSMC_PCR3_TCLR_3

    - -
    -
    - - - - -
    #define FSMC_PCR3_TCLR_3   (0x8UL << FSMC_PCR3_TCLR_Pos)
    -
    -

    0x00001000

    - -
    -
    - -

    ◆ FSMC_PCR3_TAR_Pos

    - -
    -
    - - - - -
    #define FSMC_PCR3_TAR_Pos   (13U)
    -
    - -
    -
    - -

    ◆ FSMC_PCR3_TAR_Msk

    - -
    -
    - - - - -
    #define FSMC_PCR3_TAR_Msk   (0xFUL << FSMC_PCR3_TAR_Pos)
    -
    -

    0x0001E000

    - -
    -
    - -

    ◆ FSMC_PCR3_TAR

    - -
    -
    - - - - -
    #define FSMC_PCR3_TAR   FSMC_PCR3_TAR_Msk
    -
    -

    TAR[3:0] bits (ALE to RE delay)

    - -
    -
    - -

    ◆ FSMC_PCR3_TAR_0

    - -
    -
    - - - - -
    #define FSMC_PCR3_TAR_0   (0x1UL << FSMC_PCR3_TAR_Pos)
    -
    -

    0x00002000

    - -
    -
    - -

    ◆ FSMC_PCR3_TAR_1

    - -
    -
    - - - - -
    #define FSMC_PCR3_TAR_1   (0x2UL << FSMC_PCR3_TAR_Pos)
    -
    -

    0x00004000

    - -
    -
    - -

    ◆ FSMC_PCR3_TAR_2

    - -
    -
    - - - - -
    #define FSMC_PCR3_TAR_2   (0x4UL << FSMC_PCR3_TAR_Pos)
    -
    -

    0x00008000

    - -
    -
    - -

    ◆ FSMC_PCR3_TAR_3

    - -
    -
    - - - - -
    #define FSMC_PCR3_TAR_3   (0x8UL << FSMC_PCR3_TAR_Pos)
    -
    -

    0x00010000

    - -
    -
    - -

    ◆ FSMC_PCR3_ECCPS_Pos

    - -
    -
    - - - - -
    #define FSMC_PCR3_ECCPS_Pos   (17U)
    -
    - -
    -
    - -

    ◆ FSMC_PCR3_ECCPS_Msk

    - -
    -
    - - - - -
    #define FSMC_PCR3_ECCPS_Msk   (0x7UL << FSMC_PCR3_ECCPS_Pos)
    -
    -

    0x000E0000

    - -
    -
    - -

    ◆ FSMC_PCR3_ECCPS

    - -
    -
    - - - - -
    #define FSMC_PCR3_ECCPS   FSMC_PCR3_ECCPS_Msk
    -
    -

    ECCPS[2:0] bits (ECC page size)

    - -
    -
    - -

    ◆ FSMC_PCR3_ECCPS_0

    - -
    -
    - - - - -
    #define FSMC_PCR3_ECCPS_0   (0x1UL << FSMC_PCR3_ECCPS_Pos)
    -
    -

    0x00020000

    - -
    -
    - -

    ◆ FSMC_PCR3_ECCPS_1

    - -
    -
    - - - - -
    #define FSMC_PCR3_ECCPS_1   (0x2UL << FSMC_PCR3_ECCPS_Pos)
    -
    -

    0x00040000

    - -
    -
    - -

    ◆ FSMC_PCR3_ECCPS_2

    - -
    -
    - - - - -
    #define FSMC_PCR3_ECCPS_2   (0x4UL << FSMC_PCR3_ECCPS_Pos)
    -
    -

    0x00080000

    - -
    -
    - -

    ◆ FSMC_PCR4_PWAITEN_Pos

    - -
    -
    - - - - -
    #define FSMC_PCR4_PWAITEN_Pos   (1U)
    -
    - -
    -
    - -

    ◆ FSMC_PCR4_PWAITEN_Msk

    - -
    -
    - - - - -
    #define FSMC_PCR4_PWAITEN_Msk   (0x1UL << FSMC_PCR4_PWAITEN_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ FSMC_PCR4_PWAITEN

    - -
    -
    - - - - -
    #define FSMC_PCR4_PWAITEN   FSMC_PCR4_PWAITEN_Msk
    -
    -

    Wait feature enable bit

    - -
    -
    - -

    ◆ FSMC_PCR4_PBKEN_Pos

    - -
    -
    - - - - -
    #define FSMC_PCR4_PBKEN_Pos   (2U)
    -
    - -
    -
    - -

    ◆ FSMC_PCR4_PBKEN_Msk

    - -
    -
    - - - - -
    #define FSMC_PCR4_PBKEN_Msk   (0x1UL << FSMC_PCR4_PBKEN_Pos)
    -
    -

    0x00000004

    - -
    -
    - -

    ◆ FSMC_PCR4_PBKEN

    - -
    -
    - - - - -
    #define FSMC_PCR4_PBKEN   FSMC_PCR4_PBKEN_Msk
    -
    -

    PC Card/NAND Flash memory bank enable bit

    - -
    -
    - -

    ◆ FSMC_PCR4_PTYP_Pos

    - -
    -
    - - - - -
    #define FSMC_PCR4_PTYP_Pos   (3U)
    -
    - -
    -
    - -

    ◆ FSMC_PCR4_PTYP_Msk

    - -
    -
    - - - - -
    #define FSMC_PCR4_PTYP_Msk   (0x1UL << FSMC_PCR4_PTYP_Pos)
    -
    -

    0x00000008

    - -
    -
    - -

    ◆ FSMC_PCR4_PTYP

    - -
    -
    - - - - -
    #define FSMC_PCR4_PTYP   FSMC_PCR4_PTYP_Msk
    -
    -

    Memory type

    - -
    -
    - -

    ◆ FSMC_PCR4_PWID_Pos

    - -
    -
    - - - - -
    #define FSMC_PCR4_PWID_Pos   (4U)
    -
    - -
    -
    - -

    ◆ FSMC_PCR4_PWID_Msk

    - -
    -
    - - - - -
    #define FSMC_PCR4_PWID_Msk   (0x3UL << FSMC_PCR4_PWID_Pos)
    -
    -

    0x00000030

    - -
    -
    - -

    ◆ FSMC_PCR4_PWID

    - -
    -
    - - - - -
    #define FSMC_PCR4_PWID   FSMC_PCR4_PWID_Msk
    -
    -

    PWID[1:0] bits (NAND Flash databus width)

    - -
    -
    - -

    ◆ FSMC_PCR4_PWID_0

    - -
    -
    - - - - -
    #define FSMC_PCR4_PWID_0   (0x1UL << FSMC_PCR4_PWID_Pos)
    -
    -

    0x00000010

    - -
    -
    - -

    ◆ FSMC_PCR4_PWID_1

    - -
    -
    - - - - -
    #define FSMC_PCR4_PWID_1   (0x2UL << FSMC_PCR4_PWID_Pos)
    -
    -

    0x00000020

    - -
    -
    - -

    ◆ FSMC_PCR4_ECCEN_Pos

    - -
    -
    - - - - -
    #define FSMC_PCR4_ECCEN_Pos   (6U)
    -
    - -
    -
    - -

    ◆ FSMC_PCR4_ECCEN_Msk

    - -
    -
    - - - - -
    #define FSMC_PCR4_ECCEN_Msk   (0x1UL << FSMC_PCR4_ECCEN_Pos)
    -
    -

    0x00000040

    - -
    -
    - -

    ◆ FSMC_PCR4_ECCEN

    - -
    -
    - - - - -
    #define FSMC_PCR4_ECCEN   FSMC_PCR4_ECCEN_Msk
    -
    -

    ECC computation logic enable bit

    - -
    -
    - -

    ◆ FSMC_PCR4_TCLR_Pos

    - -
    -
    - - - - -
    #define FSMC_PCR4_TCLR_Pos   (9U)
    -
    - -
    -
    - -

    ◆ FSMC_PCR4_TCLR_Msk

    - -
    -
    - - - - -
    #define FSMC_PCR4_TCLR_Msk   (0xFUL << FSMC_PCR4_TCLR_Pos)
    -
    -

    0x00001E00

    - -
    -
    - -

    ◆ FSMC_PCR4_TCLR

    - -
    -
    - - - - -
    #define FSMC_PCR4_TCLR   FSMC_PCR4_TCLR_Msk
    -
    -

    TCLR[3:0] bits (CLE to RE delay)

    - -
    -
    - -

    ◆ FSMC_PCR4_TCLR_0

    - -
    -
    - - - - -
    #define FSMC_PCR4_TCLR_0   (0x1UL << FSMC_PCR4_TCLR_Pos)
    -
    -

    0x00000200

    - -
    -
    - -

    ◆ FSMC_PCR4_TCLR_1

    - -
    -
    - - - - -
    #define FSMC_PCR4_TCLR_1   (0x2UL << FSMC_PCR4_TCLR_Pos)
    -
    -

    0x00000400

    - -
    -
    - -

    ◆ FSMC_PCR4_TCLR_2

    - -
    -
    - - - - -
    #define FSMC_PCR4_TCLR_2   (0x4UL << FSMC_PCR4_TCLR_Pos)
    -
    -

    0x00000800

    - -
    -
    - -

    ◆ FSMC_PCR4_TCLR_3

    - -
    -
    - - - - -
    #define FSMC_PCR4_TCLR_3   (0x8UL << FSMC_PCR4_TCLR_Pos)
    -
    -

    0x00001000

    - -
    -
    - -

    ◆ FSMC_PCR4_TAR_Pos

    - -
    -
    - - - - -
    #define FSMC_PCR4_TAR_Pos   (13U)
    -
    - -
    -
    - -

    ◆ FSMC_PCR4_TAR_Msk

    - -
    -
    - - - - -
    #define FSMC_PCR4_TAR_Msk   (0xFUL << FSMC_PCR4_TAR_Pos)
    -
    -

    0x0001E000

    - -
    -
    - -

    ◆ FSMC_PCR4_TAR

    - -
    -
    - - - - -
    #define FSMC_PCR4_TAR   FSMC_PCR4_TAR_Msk
    -
    -

    TAR[3:0] bits (ALE to RE delay)

    - -
    -
    - -

    ◆ FSMC_PCR4_TAR_0

    - -
    -
    - - - - -
    #define FSMC_PCR4_TAR_0   (0x1UL << FSMC_PCR4_TAR_Pos)
    -
    -

    0x00002000

    - -
    -
    - -

    ◆ FSMC_PCR4_TAR_1

    - -
    -
    - - - - -
    #define FSMC_PCR4_TAR_1   (0x2UL << FSMC_PCR4_TAR_Pos)
    -
    -

    0x00004000

    - -
    -
    - -

    ◆ FSMC_PCR4_TAR_2

    - -
    -
    - - - - -
    #define FSMC_PCR4_TAR_2   (0x4UL << FSMC_PCR4_TAR_Pos)
    -
    -

    0x00008000

    - -
    -
    - -

    ◆ FSMC_PCR4_TAR_3

    - -
    -
    - - - - -
    #define FSMC_PCR4_TAR_3   (0x8UL << FSMC_PCR4_TAR_Pos)
    -
    -

    0x00010000

    - -
    -
    - -

    ◆ FSMC_PCR4_ECCPS_Pos

    - -
    -
    - - - - -
    #define FSMC_PCR4_ECCPS_Pos   (17U)
    -
    - -
    -
    - -

    ◆ FSMC_PCR4_ECCPS_Msk

    - -
    -
    - - - - -
    #define FSMC_PCR4_ECCPS_Msk   (0x7UL << FSMC_PCR4_ECCPS_Pos)
    -
    -

    0x000E0000

    - -
    -
    - -

    ◆ FSMC_PCR4_ECCPS

    - -
    -
    - - - - -
    #define FSMC_PCR4_ECCPS   FSMC_PCR4_ECCPS_Msk
    -
    -

    ECCPS[2:0] bits (ECC page size)

    - -
    -
    - -

    ◆ FSMC_PCR4_ECCPS_0

    - -
    -
    - - - - -
    #define FSMC_PCR4_ECCPS_0   (0x1UL << FSMC_PCR4_ECCPS_Pos)
    -
    -

    0x00020000

    - -
    -
    - -

    ◆ FSMC_PCR4_ECCPS_1

    - -
    -
    - - - - -
    #define FSMC_PCR4_ECCPS_1   (0x2UL << FSMC_PCR4_ECCPS_Pos)
    -
    -

    0x00040000

    - -
    -
    - -

    ◆ FSMC_PCR4_ECCPS_2

    - -
    -
    - - - - -
    #define FSMC_PCR4_ECCPS_2   (0x4UL << FSMC_PCR4_ECCPS_Pos)
    -
    -

    0x00080000

    - -
    -
    - -

    ◆ FSMC_SR2_IRS_Pos

    - -
    -
    - - - - -
    #define FSMC_SR2_IRS_Pos   (0U)
    -
    - -
    -
    - -

    ◆ FSMC_SR2_IRS_Msk

    - -
    -
    - - - - -
    #define FSMC_SR2_IRS_Msk   (0x1UL << FSMC_SR2_IRS_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ FSMC_SR2_IRS

    - -
    -
    - - - - -
    #define FSMC_SR2_IRS   FSMC_SR2_IRS_Msk
    -
    -

    Interrupt Rising Edge status
    -

    - -
    -
    - -

    ◆ FSMC_SR2_ILS_Pos

    - -
    -
    - - - - -
    #define FSMC_SR2_ILS_Pos   (1U)
    -
    - -
    -
    - -

    ◆ FSMC_SR2_ILS_Msk

    - -
    -
    - - - - -
    #define FSMC_SR2_ILS_Msk   (0x1UL << FSMC_SR2_ILS_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ FSMC_SR2_ILS

    - -
    -
    - - - - -
    #define FSMC_SR2_ILS   FSMC_SR2_ILS_Msk
    -
    -

    Interrupt Level status
    -

    - -
    -
    - -

    ◆ FSMC_SR2_IFS_Pos

    - -
    -
    - - - - -
    #define FSMC_SR2_IFS_Pos   (2U)
    -
    - -
    -
    - -

    ◆ FSMC_SR2_IFS_Msk

    - -
    -
    - - - - -
    #define FSMC_SR2_IFS_Msk   (0x1UL << FSMC_SR2_IFS_Pos)
    -
    -

    0x00000004

    - -
    -
    - -

    ◆ FSMC_SR2_IFS

    - -
    -
    - - - - -
    #define FSMC_SR2_IFS   FSMC_SR2_IFS_Msk
    -
    -

    Interrupt Falling Edge status
    -

    - -
    -
    - -

    ◆ FSMC_SR2_IREN_Pos

    - -
    -
    - - - - -
    #define FSMC_SR2_IREN_Pos   (3U)
    -
    - -
    -
    - -

    ◆ FSMC_SR2_IREN_Msk

    - -
    -
    - - - - -
    #define FSMC_SR2_IREN_Msk   (0x1UL << FSMC_SR2_IREN_Pos)
    -
    -

    0x00000008

    - -
    -
    - -

    ◆ FSMC_SR2_IREN

    - -
    -
    - - - - -
    #define FSMC_SR2_IREN   FSMC_SR2_IREN_Msk
    -
    -

    Interrupt Rising Edge detection Enable bit
    -

    - -
    -
    - -

    ◆ FSMC_SR2_ILEN_Pos

    - -
    -
    - - - - -
    #define FSMC_SR2_ILEN_Pos   (4U)
    -
    - -
    -
    - -

    ◆ FSMC_SR2_ILEN_Msk

    - -
    -
    - - - - -
    #define FSMC_SR2_ILEN_Msk   (0x1UL << FSMC_SR2_ILEN_Pos)
    -
    -

    0x00000010

    - -
    -
    - -

    ◆ FSMC_SR2_ILEN

    - -
    -
    - - - - -
    #define FSMC_SR2_ILEN   FSMC_SR2_ILEN_Msk
    -
    -

    Interrupt Level detection Enable bit
    -

    - -
    -
    - -

    ◆ FSMC_SR2_IFEN_Pos

    - -
    -
    - - - - -
    #define FSMC_SR2_IFEN_Pos   (5U)
    -
    - -
    -
    - -

    ◆ FSMC_SR2_IFEN_Msk

    - -
    -
    - - - - -
    #define FSMC_SR2_IFEN_Msk   (0x1UL << FSMC_SR2_IFEN_Pos)
    -
    -

    0x00000020

    - -
    -
    - -

    ◆ FSMC_SR2_IFEN

    - -
    -
    - - - - -
    #define FSMC_SR2_IFEN   FSMC_SR2_IFEN_Msk
    -
    -

    Interrupt Falling Edge detection Enable bit

    - -
    -
    - -

    ◆ FSMC_SR2_FEMPT_Pos

    - -
    -
    - - - - -
    #define FSMC_SR2_FEMPT_Pos   (6U)
    -
    - -
    -
    - -

    ◆ FSMC_SR2_FEMPT_Msk

    - -
    -
    - - - - -
    #define FSMC_SR2_FEMPT_Msk   (0x1UL << FSMC_SR2_FEMPT_Pos)
    -
    -

    0x00000040

    - -
    -
    - -

    ◆ FSMC_SR2_FEMPT

    - -
    -
    - - - - -
    #define FSMC_SR2_FEMPT   FSMC_SR2_FEMPT_Msk
    -
    -

    FIFO empty

    - -
    -
    - -

    ◆ FSMC_SR3_IRS_Pos

    - -
    -
    - - - - -
    #define FSMC_SR3_IRS_Pos   (0U)
    -
    - -
    -
    - -

    ◆ FSMC_SR3_IRS_Msk

    - -
    -
    - - - - -
    #define FSMC_SR3_IRS_Msk   (0x1UL << FSMC_SR3_IRS_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ FSMC_SR3_IRS

    - -
    -
    - - - - -
    #define FSMC_SR3_IRS   FSMC_SR3_IRS_Msk
    -
    -

    Interrupt Rising Edge status
    -

    - -
    -
    - -

    ◆ FSMC_SR3_ILS_Pos

    - -
    -
    - - - - -
    #define FSMC_SR3_ILS_Pos   (1U)
    -
    - -
    -
    - -

    ◆ FSMC_SR3_ILS_Msk

    - -
    -
    - - - - -
    #define FSMC_SR3_ILS_Msk   (0x1UL << FSMC_SR3_ILS_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ FSMC_SR3_ILS

    - -
    -
    - - - - -
    #define FSMC_SR3_ILS   FSMC_SR3_ILS_Msk
    -
    -

    Interrupt Level status
    -

    - -
    -
    - -

    ◆ FSMC_SR3_IFS_Pos

    - -
    -
    - - - - -
    #define FSMC_SR3_IFS_Pos   (2U)
    -
    - -
    -
    - -

    ◆ FSMC_SR3_IFS_Msk

    - -
    -
    - - - - -
    #define FSMC_SR3_IFS_Msk   (0x1UL << FSMC_SR3_IFS_Pos)
    -
    -

    0x00000004

    - -
    -
    - -

    ◆ FSMC_SR3_IFS

    - -
    -
    - - - - -
    #define FSMC_SR3_IFS   FSMC_SR3_IFS_Msk
    -
    -

    Interrupt Falling Edge status
    -

    - -
    -
    - -

    ◆ FSMC_SR3_IREN_Pos

    - -
    -
    - - - - -
    #define FSMC_SR3_IREN_Pos   (3U)
    -
    - -
    -
    - -

    ◆ FSMC_SR3_IREN_Msk

    - -
    -
    - - - - -
    #define FSMC_SR3_IREN_Msk   (0x1UL << FSMC_SR3_IREN_Pos)
    -
    -

    0x00000008

    - -
    -
    - -

    ◆ FSMC_SR3_IREN

    - -
    -
    - - - - -
    #define FSMC_SR3_IREN   FSMC_SR3_IREN_Msk
    -
    -

    Interrupt Rising Edge detection Enable bit
    -

    - -
    -
    - -

    ◆ FSMC_SR3_ILEN_Pos

    - -
    -
    - - - - -
    #define FSMC_SR3_ILEN_Pos   (4U)
    -
    - -
    -
    - -

    ◆ FSMC_SR3_ILEN_Msk

    - -
    -
    - - - - -
    #define FSMC_SR3_ILEN_Msk   (0x1UL << FSMC_SR3_ILEN_Pos)
    -
    -

    0x00000010

    - -
    -
    - -

    ◆ FSMC_SR3_ILEN

    - -
    -
    - - - - -
    #define FSMC_SR3_ILEN   FSMC_SR3_ILEN_Msk
    -
    -

    Interrupt Level detection Enable bit
    -

    - -
    -
    - -

    ◆ FSMC_SR3_IFEN_Pos

    - -
    -
    - - - - -
    #define FSMC_SR3_IFEN_Pos   (5U)
    -
    - -
    -
    - -

    ◆ FSMC_SR3_IFEN_Msk

    - -
    -
    - - - - -
    #define FSMC_SR3_IFEN_Msk   (0x1UL << FSMC_SR3_IFEN_Pos)
    -
    -

    0x00000020

    - -
    -
    - -

    ◆ FSMC_SR3_IFEN

    - -
    -
    - - - - -
    #define FSMC_SR3_IFEN   FSMC_SR3_IFEN_Msk
    -
    -

    Interrupt Falling Edge detection Enable bit

    - -
    -
    - -

    ◆ FSMC_SR3_FEMPT_Pos

    - -
    -
    - - - - -
    #define FSMC_SR3_FEMPT_Pos   (6U)
    -
    - -
    -
    - -

    ◆ FSMC_SR3_FEMPT_Msk

    - -
    -
    - - - - -
    #define FSMC_SR3_FEMPT_Msk   (0x1UL << FSMC_SR3_FEMPT_Pos)
    -
    -

    0x00000040

    - -
    -
    - -

    ◆ FSMC_SR3_FEMPT

    - -
    -
    - - - - -
    #define FSMC_SR3_FEMPT   FSMC_SR3_FEMPT_Msk
    -
    -

    FIFO empty

    - -
    -
    - -

    ◆ FSMC_SR4_IRS_Pos

    - -
    -
    - - - - -
    #define FSMC_SR4_IRS_Pos   (0U)
    -
    - -
    -
    - -

    ◆ FSMC_SR4_IRS_Msk

    - -
    -
    - - - - -
    #define FSMC_SR4_IRS_Msk   (0x1UL << FSMC_SR4_IRS_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ FSMC_SR4_IRS

    - -
    -
    - - - - -
    #define FSMC_SR4_IRS   FSMC_SR4_IRS_Msk
    -
    -

    Interrupt Rising Edge status
    -

    - -
    -
    - -

    ◆ FSMC_SR4_ILS_Pos

    - -
    -
    - - - - -
    #define FSMC_SR4_ILS_Pos   (1U)
    -
    - -
    -
    - -

    ◆ FSMC_SR4_ILS_Msk

    - -
    -
    - - - - -
    #define FSMC_SR4_ILS_Msk   (0x1UL << FSMC_SR4_ILS_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ FSMC_SR4_ILS

    - -
    -
    - - - - -
    #define FSMC_SR4_ILS   FSMC_SR4_ILS_Msk
    -
    -

    Interrupt Level status
    -

    - -
    -
    - -

    ◆ FSMC_SR4_IFS_Pos

    - -
    -
    - - - - -
    #define FSMC_SR4_IFS_Pos   (2U)
    -
    - -
    -
    - -

    ◆ FSMC_SR4_IFS_Msk

    - -
    -
    - - - - -
    #define FSMC_SR4_IFS_Msk   (0x1UL << FSMC_SR4_IFS_Pos)
    -
    -

    0x00000004

    - -
    -
    - -

    ◆ FSMC_SR4_IFS

    - -
    -
    - - - - -
    #define FSMC_SR4_IFS   FSMC_SR4_IFS_Msk
    -
    -

    Interrupt Falling Edge status
    -

    - -
    -
    - -

    ◆ FSMC_SR4_IREN_Pos

    - -
    -
    - - - - -
    #define FSMC_SR4_IREN_Pos   (3U)
    -
    - -
    -
    - -

    ◆ FSMC_SR4_IREN_Msk

    - -
    -
    - - - - -
    #define FSMC_SR4_IREN_Msk   (0x1UL << FSMC_SR4_IREN_Pos)
    -
    -

    0x00000008

    - -
    -
    - -

    ◆ FSMC_SR4_IREN

    - -
    -
    - - - - -
    #define FSMC_SR4_IREN   FSMC_SR4_IREN_Msk
    -
    -

    Interrupt Rising Edge detection Enable bit
    -

    - -
    -
    - -

    ◆ FSMC_SR4_ILEN_Pos

    - -
    -
    - - - - -
    #define FSMC_SR4_ILEN_Pos   (4U)
    -
    - -
    -
    - -

    ◆ FSMC_SR4_ILEN_Msk

    - -
    -
    - - - - -
    #define FSMC_SR4_ILEN_Msk   (0x1UL << FSMC_SR4_ILEN_Pos)
    -
    -

    0x00000010

    - -
    -
    - -

    ◆ FSMC_SR4_ILEN

    - -
    -
    - - - - -
    #define FSMC_SR4_ILEN   FSMC_SR4_ILEN_Msk
    -
    -

    Interrupt Level detection Enable bit
    -

    - -
    -
    - -

    ◆ FSMC_SR4_IFEN_Pos

    - -
    -
    - - - - -
    #define FSMC_SR4_IFEN_Pos   (5U)
    -
    - -
    -
    - -

    ◆ FSMC_SR4_IFEN_Msk

    - -
    -
    - - - - -
    #define FSMC_SR4_IFEN_Msk   (0x1UL << FSMC_SR4_IFEN_Pos)
    -
    -

    0x00000020

    - -
    -
    - -

    ◆ FSMC_SR4_IFEN

    - -
    -
    - - - - -
    #define FSMC_SR4_IFEN   FSMC_SR4_IFEN_Msk
    -
    -

    Interrupt Falling Edge detection Enable bit
    -

    - -
    -
    - -

    ◆ FSMC_SR4_FEMPT_Pos

    - -
    -
    - - - - -
    #define FSMC_SR4_FEMPT_Pos   (6U)
    -
    - -
    -
    - -

    ◆ FSMC_SR4_FEMPT_Msk

    - -
    -
    - - - - -
    #define FSMC_SR4_FEMPT_Msk   (0x1UL << FSMC_SR4_FEMPT_Pos)
    -
    -

    0x00000040

    - -
    -
    - -

    ◆ FSMC_SR4_FEMPT

    - -
    -
    - - - - -
    #define FSMC_SR4_FEMPT   FSMC_SR4_FEMPT_Msk
    -
    -

    FIFO empty

    - -
    -
    - -

    ◆ FSMC_PMEM2_MEMSET2_Pos

    - -
    -
    - - - - -
    #define FSMC_PMEM2_MEMSET2_Pos   (0U)
    -
    - -
    -
    - -

    ◆ FSMC_PMEM2_MEMSET2_Msk

    - -
    -
    - - - - -
    #define FSMC_PMEM2_MEMSET2_Msk   (0xFFUL << FSMC_PMEM2_MEMSET2_Pos)
    -
    -

    0x000000FF

    - -
    -
    - -

    ◆ FSMC_PMEM2_MEMSET2

    - -
    -
    - - - - -
    #define FSMC_PMEM2_MEMSET2   FSMC_PMEM2_MEMSET2_Msk
    -
    -

    MEMSET2[7:0] bits (Common memory 2 setup time)

    - -
    -
    - -

    ◆ FSMC_PMEM2_MEMSET2_0

    - -
    -
    - - - - -
    #define FSMC_PMEM2_MEMSET2_0   (0x01UL << FSMC_PMEM2_MEMSET2_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ FSMC_PMEM2_MEMSET2_1

    - -
    -
    - - - - -
    #define FSMC_PMEM2_MEMSET2_1   (0x02UL << FSMC_PMEM2_MEMSET2_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ FSMC_PMEM2_MEMSET2_2

    - -
    -
    - - - - -
    #define FSMC_PMEM2_MEMSET2_2   (0x04UL << FSMC_PMEM2_MEMSET2_Pos)
    -
    -

    0x00000004

    - -
    -
    - -

    ◆ FSMC_PMEM2_MEMSET2_3

    - -
    -
    - - - - -
    #define FSMC_PMEM2_MEMSET2_3   (0x08UL << FSMC_PMEM2_MEMSET2_Pos)
    -
    -

    0x00000008

    - -
    -
    - -

    ◆ FSMC_PMEM2_MEMSET2_4

    - -
    -
    - - - - -
    #define FSMC_PMEM2_MEMSET2_4   (0x10UL << FSMC_PMEM2_MEMSET2_Pos)
    -
    -

    0x00000010

    - -
    -
    - -

    ◆ FSMC_PMEM2_MEMSET2_5

    - -
    -
    - - - - -
    #define FSMC_PMEM2_MEMSET2_5   (0x20UL << FSMC_PMEM2_MEMSET2_Pos)
    -
    -

    0x00000020

    - -
    -
    - -

    ◆ FSMC_PMEM2_MEMSET2_6

    - -
    -
    - - - - -
    #define FSMC_PMEM2_MEMSET2_6   (0x40UL << FSMC_PMEM2_MEMSET2_Pos)
    -
    -

    0x00000040

    - -
    -
    - -

    ◆ FSMC_PMEM2_MEMSET2_7

    - -
    -
    - - - - -
    #define FSMC_PMEM2_MEMSET2_7   (0x80UL << FSMC_PMEM2_MEMSET2_Pos)
    -
    -

    0x00000080

    - -
    -
    - -

    ◆ FSMC_PMEM2_MEMWAIT2_Pos

    - -
    -
    - - - - -
    #define FSMC_PMEM2_MEMWAIT2_Pos   (8U)
    -
    - -
    -
    - -

    ◆ FSMC_PMEM2_MEMWAIT2_Msk

    - -
    -
    - - - - -
    #define FSMC_PMEM2_MEMWAIT2_Msk   (0xFFUL << FSMC_PMEM2_MEMWAIT2_Pos)
    -
    -

    0x0000FF00

    - -
    -
    - -

    ◆ FSMC_PMEM2_MEMWAIT2

    - -
    -
    - - - - -
    #define FSMC_PMEM2_MEMWAIT2   FSMC_PMEM2_MEMWAIT2_Msk
    -
    -

    MEMWAIT2[7:0] bits (Common memory 2 wait time)

    - -
    -
    - -

    ◆ FSMC_PMEM2_MEMWAIT2_0

    - -
    -
    - - - - -
    #define FSMC_PMEM2_MEMWAIT2_0   (0x01UL << FSMC_PMEM2_MEMWAIT2_Pos)
    -
    -

    0x00000100

    - -
    -
    - -

    ◆ FSMC_PMEM2_MEMWAIT2_1

    - -
    -
    - - - - -
    #define FSMC_PMEM2_MEMWAIT2_1   (0x02UL << FSMC_PMEM2_MEMWAIT2_Pos)
    -
    -

    0x00000200

    - -
    -
    - -

    ◆ FSMC_PMEM2_MEMWAIT2_2

    - -
    -
    - - - - -
    #define FSMC_PMEM2_MEMWAIT2_2   (0x04UL << FSMC_PMEM2_MEMWAIT2_Pos)
    -
    -

    0x00000400

    - -
    -
    - -

    ◆ FSMC_PMEM2_MEMWAIT2_3

    - -
    -
    - - - - -
    #define FSMC_PMEM2_MEMWAIT2_3   (0x08UL << FSMC_PMEM2_MEMWAIT2_Pos)
    -
    -

    0x00000800

    - -
    -
    - -

    ◆ FSMC_PMEM2_MEMWAIT2_4

    - -
    -
    - - - - -
    #define FSMC_PMEM2_MEMWAIT2_4   (0x10UL << FSMC_PMEM2_MEMWAIT2_Pos)
    -
    -

    0x00001000

    - -
    -
    - -

    ◆ FSMC_PMEM2_MEMWAIT2_5

    - -
    -
    - - - - -
    #define FSMC_PMEM2_MEMWAIT2_5   (0x20UL << FSMC_PMEM2_MEMWAIT2_Pos)
    -
    -

    0x00002000

    - -
    -
    - -

    ◆ FSMC_PMEM2_MEMWAIT2_6

    - -
    -
    - - - - -
    #define FSMC_PMEM2_MEMWAIT2_6   (0x40UL << FSMC_PMEM2_MEMWAIT2_Pos)
    -
    -

    0x00004000

    - -
    -
    - -

    ◆ FSMC_PMEM2_MEMWAIT2_7

    - -
    -
    - - - - -
    #define FSMC_PMEM2_MEMWAIT2_7   (0x80UL << FSMC_PMEM2_MEMWAIT2_Pos)
    -
    -

    0x00008000

    - -
    -
    - -

    ◆ FSMC_PMEM2_MEMHOLD2_Pos

    - -
    -
    - - - - -
    #define FSMC_PMEM2_MEMHOLD2_Pos   (16U)
    -
    - -
    -
    - -

    ◆ FSMC_PMEM2_MEMHOLD2_Msk

    - -
    -
    - - - - -
    #define FSMC_PMEM2_MEMHOLD2_Msk   (0xFFUL << FSMC_PMEM2_MEMHOLD2_Pos)
    -
    -

    0x00FF0000

    - -
    -
    - -

    ◆ FSMC_PMEM2_MEMHOLD2

    - -
    -
    - - - - -
    #define FSMC_PMEM2_MEMHOLD2   FSMC_PMEM2_MEMHOLD2_Msk
    -
    -

    MEMHOLD2[7:0] bits (Common memory 2 hold time)

    - -
    -
    - -

    ◆ FSMC_PMEM2_MEMHOLD2_0

    - -
    -
    - - - - -
    #define FSMC_PMEM2_MEMHOLD2_0   (0x01UL << FSMC_PMEM2_MEMHOLD2_Pos)
    -
    -

    0x00010000

    - -
    -
    - -

    ◆ FSMC_PMEM2_MEMHOLD2_1

    - -
    -
    - - - - -
    #define FSMC_PMEM2_MEMHOLD2_1   (0x02UL << FSMC_PMEM2_MEMHOLD2_Pos)
    -
    -

    0x00020000

    - -
    -
    - -

    ◆ FSMC_PMEM2_MEMHOLD2_2

    - -
    -
    - - - - -
    #define FSMC_PMEM2_MEMHOLD2_2   (0x04UL << FSMC_PMEM2_MEMHOLD2_Pos)
    -
    -

    0x00040000

    - -
    -
    - -

    ◆ FSMC_PMEM2_MEMHOLD2_3

    - -
    -
    - - - - -
    #define FSMC_PMEM2_MEMHOLD2_3   (0x08UL << FSMC_PMEM2_MEMHOLD2_Pos)
    -
    -

    0x00080000

    - -
    -
    - -

    ◆ FSMC_PMEM2_MEMHOLD2_4

    - -
    -
    - - - - -
    #define FSMC_PMEM2_MEMHOLD2_4   (0x10UL << FSMC_PMEM2_MEMHOLD2_Pos)
    -
    -

    0x00100000

    - -
    -
    - -

    ◆ FSMC_PMEM2_MEMHOLD2_5

    - -
    -
    - - - - -
    #define FSMC_PMEM2_MEMHOLD2_5   (0x20UL << FSMC_PMEM2_MEMHOLD2_Pos)
    -
    -

    0x00200000

    - -
    -
    - -

    ◆ FSMC_PMEM2_MEMHOLD2_6

    - -
    -
    - - - - -
    #define FSMC_PMEM2_MEMHOLD2_6   (0x40UL << FSMC_PMEM2_MEMHOLD2_Pos)
    -
    -

    0x00400000

    - -
    -
    - -

    ◆ FSMC_PMEM2_MEMHOLD2_7

    - -
    -
    - - - - -
    #define FSMC_PMEM2_MEMHOLD2_7   (0x80UL << FSMC_PMEM2_MEMHOLD2_Pos)
    -
    -

    0x00800000

    - -
    -
    - -

    ◆ FSMC_PMEM2_MEMHIZ2_Pos

    - -
    -
    - - - - -
    #define FSMC_PMEM2_MEMHIZ2_Pos   (24U)
    -
    - -
    -
    - -

    ◆ FSMC_PMEM2_MEMHIZ2_Msk

    - -
    -
    - - - - -
    #define FSMC_PMEM2_MEMHIZ2_Msk   (0xFFUL << FSMC_PMEM2_MEMHIZ2_Pos)
    -
    -

    0xFF000000

    - -
    -
    - -

    ◆ FSMC_PMEM2_MEMHIZ2

    - -
    -
    - - - - -
    #define FSMC_PMEM2_MEMHIZ2   FSMC_PMEM2_MEMHIZ2_Msk
    -
    -

    MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time)

    - -
    -
    - -

    ◆ FSMC_PMEM2_MEMHIZ2_0

    - -
    -
    - - - - -
    #define FSMC_PMEM2_MEMHIZ2_0   (0x01UL << FSMC_PMEM2_MEMHIZ2_Pos)
    -
    -

    0x01000000

    - -
    -
    - -

    ◆ FSMC_PMEM2_MEMHIZ2_1

    - -
    -
    - - - - -
    #define FSMC_PMEM2_MEMHIZ2_1   (0x02UL << FSMC_PMEM2_MEMHIZ2_Pos)
    -
    -

    0x02000000

    - -
    -
    - -

    ◆ FSMC_PMEM2_MEMHIZ2_2

    - -
    -
    - - - - -
    #define FSMC_PMEM2_MEMHIZ2_2   (0x04UL << FSMC_PMEM2_MEMHIZ2_Pos)
    -
    -

    0x04000000

    - -
    -
    - -

    ◆ FSMC_PMEM2_MEMHIZ2_3

    - -
    -
    - - - - -
    #define FSMC_PMEM2_MEMHIZ2_3   (0x08UL << FSMC_PMEM2_MEMHIZ2_Pos)
    -
    -

    0x08000000

    - -
    -
    - -

    ◆ FSMC_PMEM2_MEMHIZ2_4

    - -
    -
    - - - - -
    #define FSMC_PMEM2_MEMHIZ2_4   (0x10UL << FSMC_PMEM2_MEMHIZ2_Pos)
    -
    -

    0x10000000

    - -
    -
    - -

    ◆ FSMC_PMEM2_MEMHIZ2_5

    - -
    -
    - - - - -
    #define FSMC_PMEM2_MEMHIZ2_5   (0x20UL << FSMC_PMEM2_MEMHIZ2_Pos)
    -
    -

    0x20000000

    - -
    -
    - -

    ◆ FSMC_PMEM2_MEMHIZ2_6

    - -
    -
    - - - - -
    #define FSMC_PMEM2_MEMHIZ2_6   (0x40UL << FSMC_PMEM2_MEMHIZ2_Pos)
    -
    -

    0x40000000

    - -
    -
    - -

    ◆ FSMC_PMEM2_MEMHIZ2_7

    - -
    -
    - - - - -
    #define FSMC_PMEM2_MEMHIZ2_7   (0x80UL << FSMC_PMEM2_MEMHIZ2_Pos)
    -
    -

    0x80000000

    - -
    -
    - -

    ◆ FSMC_PMEM3_MEMSET3_Pos

    - -
    -
    - - - - -
    #define FSMC_PMEM3_MEMSET3_Pos   (0U)
    -
    - -
    -
    - -

    ◆ FSMC_PMEM3_MEMSET3_Msk

    - -
    -
    - - - - -
    #define FSMC_PMEM3_MEMSET3_Msk   (0xFFUL << FSMC_PMEM3_MEMSET3_Pos)
    -
    -

    0x000000FF

    - -
    -
    - -

    ◆ FSMC_PMEM3_MEMSET3

    - -
    -
    - - - - -
    #define FSMC_PMEM3_MEMSET3   FSMC_PMEM3_MEMSET3_Msk
    -
    -

    MEMSET3[7:0] bits (Common memory 3 setup time)

    - -
    -
    - -

    ◆ FSMC_PMEM3_MEMSET3_0

    - -
    -
    - - - - -
    #define FSMC_PMEM3_MEMSET3_0   (0x01UL << FSMC_PMEM3_MEMSET3_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ FSMC_PMEM3_MEMSET3_1

    - -
    -
    - - - - -
    #define FSMC_PMEM3_MEMSET3_1   (0x02UL << FSMC_PMEM3_MEMSET3_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ FSMC_PMEM3_MEMSET3_2

    - -
    -
    - - - - -
    #define FSMC_PMEM3_MEMSET3_2   (0x04UL << FSMC_PMEM3_MEMSET3_Pos)
    -
    -

    0x00000004

    - -
    -
    - -

    ◆ FSMC_PMEM3_MEMSET3_3

    - -
    -
    - - - - -
    #define FSMC_PMEM3_MEMSET3_3   (0x08UL << FSMC_PMEM3_MEMSET3_Pos)
    -
    -

    0x00000008

    - -
    -
    - -

    ◆ FSMC_PMEM3_MEMSET3_4

    - -
    -
    - - - - -
    #define FSMC_PMEM3_MEMSET3_4   (0x10UL << FSMC_PMEM3_MEMSET3_Pos)
    -
    -

    0x00000010

    - -
    -
    - -

    ◆ FSMC_PMEM3_MEMSET3_5

    - -
    -
    - - - - -
    #define FSMC_PMEM3_MEMSET3_5   (0x20UL << FSMC_PMEM3_MEMSET3_Pos)
    -
    -

    0x00000020

    - -
    -
    - -

    ◆ FSMC_PMEM3_MEMSET3_6

    - -
    -
    - - - - -
    #define FSMC_PMEM3_MEMSET3_6   (0x40UL << FSMC_PMEM3_MEMSET3_Pos)
    -
    -

    0x00000040

    - -
    -
    - -

    ◆ FSMC_PMEM3_MEMSET3_7

    - -
    -
    - - - - -
    #define FSMC_PMEM3_MEMSET3_7   (0x80UL << FSMC_PMEM3_MEMSET3_Pos)
    -
    -

    0x00000080

    - -
    -
    - -

    ◆ FSMC_PMEM3_MEMWAIT3_Pos

    - -
    -
    - - - - -
    #define FSMC_PMEM3_MEMWAIT3_Pos   (8U)
    -
    - -
    -
    - -

    ◆ FSMC_PMEM3_MEMWAIT3_Msk

    - -
    -
    - - - - -
    #define FSMC_PMEM3_MEMWAIT3_Msk   (0xFFUL << FSMC_PMEM3_MEMWAIT3_Pos)
    -
    -

    0x0000FF00

    - -
    -
    - -

    ◆ FSMC_PMEM3_MEMWAIT3

    - -
    -
    - - - - -
    #define FSMC_PMEM3_MEMWAIT3   FSMC_PMEM3_MEMWAIT3_Msk
    -
    -

    MEMWAIT3[7:0] bits (Common memory 3 wait time)

    - -
    -
    - -

    ◆ FSMC_PMEM3_MEMWAIT3_0

    - -
    -
    - - - - -
    #define FSMC_PMEM3_MEMWAIT3_0   (0x01UL << FSMC_PMEM3_MEMWAIT3_Pos)
    -
    -

    0x00000100

    - -
    -
    - -

    ◆ FSMC_PMEM3_MEMWAIT3_1

    - -
    -
    - - - - -
    #define FSMC_PMEM3_MEMWAIT3_1   (0x02UL << FSMC_PMEM3_MEMWAIT3_Pos)
    -
    -

    0x00000200

    - -
    -
    - -

    ◆ FSMC_PMEM3_MEMWAIT3_2

    - -
    -
    - - - - -
    #define FSMC_PMEM3_MEMWAIT3_2   (0x04UL << FSMC_PMEM3_MEMWAIT3_Pos)
    -
    -

    0x00000400

    - -
    -
    - -

    ◆ FSMC_PMEM3_MEMWAIT3_3

    - -
    -
    - - - - -
    #define FSMC_PMEM3_MEMWAIT3_3   (0x08UL << FSMC_PMEM3_MEMWAIT3_Pos)
    -
    -

    0x00000800

    - -
    -
    - -

    ◆ FSMC_PMEM3_MEMWAIT3_4

    - -
    -
    - - - - -
    #define FSMC_PMEM3_MEMWAIT3_4   (0x10UL << FSMC_PMEM3_MEMWAIT3_Pos)
    -
    -

    0x00001000

    - -
    -
    - -

    ◆ FSMC_PMEM3_MEMWAIT3_5

    - -
    -
    - - - - -
    #define FSMC_PMEM3_MEMWAIT3_5   (0x20UL << FSMC_PMEM3_MEMWAIT3_Pos)
    -
    -

    0x00002000

    - -
    -
    - -

    ◆ FSMC_PMEM3_MEMWAIT3_6

    - -
    -
    - - - - -
    #define FSMC_PMEM3_MEMWAIT3_6   (0x40UL << FSMC_PMEM3_MEMWAIT3_Pos)
    -
    -

    0x00004000

    - -
    -
    - -

    ◆ FSMC_PMEM3_MEMWAIT3_7

    - -
    -
    - - - - -
    #define FSMC_PMEM3_MEMWAIT3_7   (0x80UL << FSMC_PMEM3_MEMWAIT3_Pos)
    -
    -

    0x00008000

    - -
    -
    - -

    ◆ FSMC_PMEM3_MEMHOLD3_Pos

    - -
    -
    - - - - -
    #define FSMC_PMEM3_MEMHOLD3_Pos   (16U)
    -
    - -
    -
    - -

    ◆ FSMC_PMEM3_MEMHOLD3_Msk

    - -
    -
    - - - - -
    #define FSMC_PMEM3_MEMHOLD3_Msk   (0xFFUL << FSMC_PMEM3_MEMHOLD3_Pos)
    -
    -

    0x00FF0000

    - -
    -
    - -

    ◆ FSMC_PMEM3_MEMHOLD3

    - -
    -
    - - - - -
    #define FSMC_PMEM3_MEMHOLD3   FSMC_PMEM3_MEMHOLD3_Msk
    -
    -

    MEMHOLD3[7:0] bits (Common memory 3 hold time)

    - -
    -
    - -

    ◆ FSMC_PMEM3_MEMHOLD3_0

    - -
    -
    - - - - -
    #define FSMC_PMEM3_MEMHOLD3_0   (0x01UL << FSMC_PMEM3_MEMHOLD3_Pos)
    -
    -

    0x00010000

    - -
    -
    - -

    ◆ FSMC_PMEM3_MEMHOLD3_1

    - -
    -
    - - - - -
    #define FSMC_PMEM3_MEMHOLD3_1   (0x02UL << FSMC_PMEM3_MEMHOLD3_Pos)
    -
    -

    0x00020000

    - -
    -
    - -

    ◆ FSMC_PMEM3_MEMHOLD3_2

    - -
    -
    - - - - -
    #define FSMC_PMEM3_MEMHOLD3_2   (0x04UL << FSMC_PMEM3_MEMHOLD3_Pos)
    -
    -

    0x00040000

    - -
    -
    - -

    ◆ FSMC_PMEM3_MEMHOLD3_3

    - -
    -
    - - - - -
    #define FSMC_PMEM3_MEMHOLD3_3   (0x08UL << FSMC_PMEM3_MEMHOLD3_Pos)
    -
    -

    0x00080000

    - -
    -
    - -

    ◆ FSMC_PMEM3_MEMHOLD3_4

    - -
    -
    - - - - -
    #define FSMC_PMEM3_MEMHOLD3_4   (0x10UL << FSMC_PMEM3_MEMHOLD3_Pos)
    -
    -

    0x00100000

    - -
    -
    - -

    ◆ FSMC_PMEM3_MEMHOLD3_5

    - -
    -
    - - - - -
    #define FSMC_PMEM3_MEMHOLD3_5   (0x20UL << FSMC_PMEM3_MEMHOLD3_Pos)
    -
    -

    0x00200000

    - -
    -
    - -

    ◆ FSMC_PMEM3_MEMHOLD3_6

    - -
    -
    - - - - -
    #define FSMC_PMEM3_MEMHOLD3_6   (0x40UL << FSMC_PMEM3_MEMHOLD3_Pos)
    -
    -

    0x00400000

    - -
    -
    - -

    ◆ FSMC_PMEM3_MEMHOLD3_7

    - -
    -
    - - - - -
    #define FSMC_PMEM3_MEMHOLD3_7   (0x80UL << FSMC_PMEM3_MEMHOLD3_Pos)
    -
    -

    0x00800000

    - -
    -
    - -

    ◆ FSMC_PMEM3_MEMHIZ3_Pos

    - -
    -
    - - - - -
    #define FSMC_PMEM3_MEMHIZ3_Pos   (24U)
    -
    - -
    -
    - -

    ◆ FSMC_PMEM3_MEMHIZ3_Msk

    - -
    -
    - - - - -
    #define FSMC_PMEM3_MEMHIZ3_Msk   (0xFFUL << FSMC_PMEM3_MEMHIZ3_Pos)
    -
    -

    0xFF000000

    - -
    -
    - -

    ◆ FSMC_PMEM3_MEMHIZ3

    - -
    -
    - - - - -
    #define FSMC_PMEM3_MEMHIZ3   FSMC_PMEM3_MEMHIZ3_Msk
    -
    -

    MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time)

    - -
    -
    - -

    ◆ FSMC_PMEM3_MEMHIZ3_0

    - -
    -
    - - - - -
    #define FSMC_PMEM3_MEMHIZ3_0   (0x01UL << FSMC_PMEM3_MEMHIZ3_Pos)
    -
    -

    0x01000000

    - -
    -
    - -

    ◆ FSMC_PMEM3_MEMHIZ3_1

    - -
    -
    - - - - -
    #define FSMC_PMEM3_MEMHIZ3_1   (0x02UL << FSMC_PMEM3_MEMHIZ3_Pos)
    -
    -

    0x02000000

    - -
    -
    - -

    ◆ FSMC_PMEM3_MEMHIZ3_2

    - -
    -
    - - - - -
    #define FSMC_PMEM3_MEMHIZ3_2   (0x04UL << FSMC_PMEM3_MEMHIZ3_Pos)
    -
    -

    0x04000000

    - -
    -
    - -

    ◆ FSMC_PMEM3_MEMHIZ3_3

    - -
    -
    - - - - -
    #define FSMC_PMEM3_MEMHIZ3_3   (0x08UL << FSMC_PMEM3_MEMHIZ3_Pos)
    -
    -

    0x08000000

    - -
    -
    - -

    ◆ FSMC_PMEM3_MEMHIZ3_4

    - -
    -
    - - - - -
    #define FSMC_PMEM3_MEMHIZ3_4   (0x10UL << FSMC_PMEM3_MEMHIZ3_Pos)
    -
    -

    0x10000000

    - -
    -
    - -

    ◆ FSMC_PMEM3_MEMHIZ3_5

    - -
    -
    - - - - -
    #define FSMC_PMEM3_MEMHIZ3_5   (0x20UL << FSMC_PMEM3_MEMHIZ3_Pos)
    -
    -

    0x20000000

    - -
    -
    - -

    ◆ FSMC_PMEM3_MEMHIZ3_6

    - -
    -
    - - - - -
    #define FSMC_PMEM3_MEMHIZ3_6   (0x40UL << FSMC_PMEM3_MEMHIZ3_Pos)
    -
    -

    0x40000000

    - -
    -
    - -

    ◆ FSMC_PMEM3_MEMHIZ3_7

    - -
    -
    - - - - -
    #define FSMC_PMEM3_MEMHIZ3_7   (0x80UL << FSMC_PMEM3_MEMHIZ3_Pos)
    -
    -

    0x80000000

    - -
    -
    - -

    ◆ FSMC_PMEM4_MEMSET4_Pos

    - -
    -
    - - - - -
    #define FSMC_PMEM4_MEMSET4_Pos   (0U)
    -
    - -
    -
    - -

    ◆ FSMC_PMEM4_MEMSET4_Msk

    - -
    -
    - - - - -
    #define FSMC_PMEM4_MEMSET4_Msk   (0xFFUL << FSMC_PMEM4_MEMSET4_Pos)
    -
    -

    0x000000FF

    - -
    -
    - -

    ◆ FSMC_PMEM4_MEMSET4

    - -
    -
    - - - - -
    #define FSMC_PMEM4_MEMSET4   FSMC_PMEM4_MEMSET4_Msk
    -
    -

    MEMSET4[7:0] bits (Common memory 4 setup time)

    - -
    -
    - -

    ◆ FSMC_PMEM4_MEMSET4_0

    - -
    -
    - - - - -
    #define FSMC_PMEM4_MEMSET4_0   (0x01UL << FSMC_PMEM4_MEMSET4_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ FSMC_PMEM4_MEMSET4_1

    - -
    -
    - - - - -
    #define FSMC_PMEM4_MEMSET4_1   (0x02UL << FSMC_PMEM4_MEMSET4_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ FSMC_PMEM4_MEMSET4_2

    - -
    -
    - - - - -
    #define FSMC_PMEM4_MEMSET4_2   (0x04UL << FSMC_PMEM4_MEMSET4_Pos)
    -
    -

    0x00000004

    - -
    -
    - -

    ◆ FSMC_PMEM4_MEMSET4_3

    - -
    -
    - - - - -
    #define FSMC_PMEM4_MEMSET4_3   (0x08UL << FSMC_PMEM4_MEMSET4_Pos)
    -
    -

    0x00000008

    - -
    -
    - -

    ◆ FSMC_PMEM4_MEMSET4_4

    - -
    -
    - - - - -
    #define FSMC_PMEM4_MEMSET4_4   (0x10UL << FSMC_PMEM4_MEMSET4_Pos)
    -
    -

    0x00000010

    - -
    -
    - -

    ◆ FSMC_PMEM4_MEMSET4_5

    - -
    -
    - - - - -
    #define FSMC_PMEM4_MEMSET4_5   (0x20UL << FSMC_PMEM4_MEMSET4_Pos)
    -
    -

    0x00000020

    - -
    -
    - -

    ◆ FSMC_PMEM4_MEMSET4_6

    - -
    -
    - - - - -
    #define FSMC_PMEM4_MEMSET4_6   (0x40UL << FSMC_PMEM4_MEMSET4_Pos)
    -
    -

    0x00000040

    - -
    -
    - -

    ◆ FSMC_PMEM4_MEMSET4_7

    - -
    -
    - - - - -
    #define FSMC_PMEM4_MEMSET4_7   (0x80UL << FSMC_PMEM4_MEMSET4_Pos)
    -
    -

    0x00000080

    - -
    -
    - -

    ◆ FSMC_PMEM4_MEMWAIT4_Pos

    - -
    -
    - - - - -
    #define FSMC_PMEM4_MEMWAIT4_Pos   (8U)
    -
    - -
    -
    - -

    ◆ FSMC_PMEM4_MEMWAIT4_Msk

    - -
    -
    - - - - -
    #define FSMC_PMEM4_MEMWAIT4_Msk   (0xFFUL << FSMC_PMEM4_MEMWAIT4_Pos)
    -
    -

    0x0000FF00

    - -
    -
    - -

    ◆ FSMC_PMEM4_MEMWAIT4

    - -
    -
    - - - - -
    #define FSMC_PMEM4_MEMWAIT4   FSMC_PMEM4_MEMWAIT4_Msk
    -
    -

    MEMWAIT4[7:0] bits (Common memory 4 wait time)

    - -
    -
    - -

    ◆ FSMC_PMEM4_MEMWAIT4_0

    - -
    -
    - - - - -
    #define FSMC_PMEM4_MEMWAIT4_0   (0x01UL << FSMC_PMEM4_MEMWAIT4_Pos)
    -
    -

    0x00000100

    - -
    -
    - -

    ◆ FSMC_PMEM4_MEMWAIT4_1

    - -
    -
    - - - - -
    #define FSMC_PMEM4_MEMWAIT4_1   (0x02UL << FSMC_PMEM4_MEMWAIT4_Pos)
    -
    -

    0x00000200

    - -
    -
    - -

    ◆ FSMC_PMEM4_MEMWAIT4_2

    - -
    -
    - - - - -
    #define FSMC_PMEM4_MEMWAIT4_2   (0x04UL << FSMC_PMEM4_MEMWAIT4_Pos)
    -
    -

    0x00000400

    - -
    -
    - -

    ◆ FSMC_PMEM4_MEMWAIT4_3

    - -
    -
    - - - - -
    #define FSMC_PMEM4_MEMWAIT4_3   (0x08UL << FSMC_PMEM4_MEMWAIT4_Pos)
    -
    -

    0x00000800

    - -
    -
    - -

    ◆ FSMC_PMEM4_MEMWAIT4_4

    - -
    -
    - - - - -
    #define FSMC_PMEM4_MEMWAIT4_4   (0x10UL << FSMC_PMEM4_MEMWAIT4_Pos)
    -
    -

    0x00001000

    - -
    -
    - -

    ◆ FSMC_PMEM4_MEMWAIT4_5

    - -
    -
    - - - - -
    #define FSMC_PMEM4_MEMWAIT4_5   (0x20UL << FSMC_PMEM4_MEMWAIT4_Pos)
    -
    -

    0x00002000

    - -
    -
    - -

    ◆ FSMC_PMEM4_MEMWAIT4_6

    - -
    -
    - - - - -
    #define FSMC_PMEM4_MEMWAIT4_6   (0x40UL << FSMC_PMEM4_MEMWAIT4_Pos)
    -
    -

    0x00004000

    - -
    -
    - -

    ◆ FSMC_PMEM4_MEMWAIT4_7

    - -
    -
    - - - - -
    #define FSMC_PMEM4_MEMWAIT4_7   (0x80UL << FSMC_PMEM4_MEMWAIT4_Pos)
    -
    -

    0x00008000

    - -
    -
    - -

    ◆ FSMC_PMEM4_MEMHOLD4_Pos

    - -
    -
    - - - - -
    #define FSMC_PMEM4_MEMHOLD4_Pos   (16U)
    -
    - -
    -
    - -

    ◆ FSMC_PMEM4_MEMHOLD4_Msk

    - -
    -
    - - - - -
    #define FSMC_PMEM4_MEMHOLD4_Msk   (0xFFUL << FSMC_PMEM4_MEMHOLD4_Pos)
    -
    -

    0x00FF0000

    - -
    -
    - -

    ◆ FSMC_PMEM4_MEMHOLD4

    - -
    -
    - - - - -
    #define FSMC_PMEM4_MEMHOLD4   FSMC_PMEM4_MEMHOLD4_Msk
    -
    -

    MEMHOLD4[7:0] bits (Common memory 4 hold time)

    - -
    -
    - -

    ◆ FSMC_PMEM4_MEMHOLD4_0

    - -
    -
    - - - - -
    #define FSMC_PMEM4_MEMHOLD4_0   (0x01UL << FSMC_PMEM4_MEMHOLD4_Pos)
    -
    -

    0x00010000

    - -
    -
    - -

    ◆ FSMC_PMEM4_MEMHOLD4_1

    - -
    -
    - - - - -
    #define FSMC_PMEM4_MEMHOLD4_1   (0x02UL << FSMC_PMEM4_MEMHOLD4_Pos)
    -
    -

    0x00020000

    - -
    -
    - -

    ◆ FSMC_PMEM4_MEMHOLD4_2

    - -
    -
    - - - - -
    #define FSMC_PMEM4_MEMHOLD4_2   (0x04UL << FSMC_PMEM4_MEMHOLD4_Pos)
    -
    -

    0x00040000

    - -
    -
    - -

    ◆ FSMC_PMEM4_MEMHOLD4_3

    - -
    -
    - - - - -
    #define FSMC_PMEM4_MEMHOLD4_3   (0x08UL << FSMC_PMEM4_MEMHOLD4_Pos)
    -
    -

    0x00080000

    - -
    -
    - -

    ◆ FSMC_PMEM4_MEMHOLD4_4

    - -
    -
    - - - - -
    #define FSMC_PMEM4_MEMHOLD4_4   (0x10UL << FSMC_PMEM4_MEMHOLD4_Pos)
    -
    -

    0x00100000

    - -
    -
    - -

    ◆ FSMC_PMEM4_MEMHOLD4_5

    - -
    -
    - - - - -
    #define FSMC_PMEM4_MEMHOLD4_5   (0x20UL << FSMC_PMEM4_MEMHOLD4_Pos)
    -
    -

    0x00200000

    - -
    -
    - -

    ◆ FSMC_PMEM4_MEMHOLD4_6

    - -
    -
    - - - - -
    #define FSMC_PMEM4_MEMHOLD4_6   (0x40UL << FSMC_PMEM4_MEMHOLD4_Pos)
    -
    -

    0x00400000

    - -
    -
    - -

    ◆ FSMC_PMEM4_MEMHOLD4_7

    - -
    -
    - - - - -
    #define FSMC_PMEM4_MEMHOLD4_7   (0x80UL << FSMC_PMEM4_MEMHOLD4_Pos)
    -
    -

    0x00800000

    - -
    -
    - -

    ◆ FSMC_PMEM4_MEMHIZ4_Pos

    - -
    -
    - - - - -
    #define FSMC_PMEM4_MEMHIZ4_Pos   (24U)
    -
    - -
    -
    - -

    ◆ FSMC_PMEM4_MEMHIZ4_Msk

    - -
    -
    - - - - -
    #define FSMC_PMEM4_MEMHIZ4_Msk   (0xFFUL << FSMC_PMEM4_MEMHIZ4_Pos)
    -
    -

    0xFF000000

    - -
    -
    - -

    ◆ FSMC_PMEM4_MEMHIZ4

    - -
    -
    - - - - -
    #define FSMC_PMEM4_MEMHIZ4   FSMC_PMEM4_MEMHIZ4_Msk
    -
    -

    MEMHIZ4[7:0] bits (Common memory 4 databus HiZ time)

    - -
    -
    - -

    ◆ FSMC_PMEM4_MEMHIZ4_0

    - -
    -
    - - - - -
    #define FSMC_PMEM4_MEMHIZ4_0   (0x01UL << FSMC_PMEM4_MEMHIZ4_Pos)
    -
    -

    0x01000000

    - -
    -
    - -

    ◆ FSMC_PMEM4_MEMHIZ4_1

    - -
    -
    - - - - -
    #define FSMC_PMEM4_MEMHIZ4_1   (0x02UL << FSMC_PMEM4_MEMHIZ4_Pos)
    -
    -

    0x02000000

    - -
    -
    - -

    ◆ FSMC_PMEM4_MEMHIZ4_2

    - -
    -
    - - - - -
    #define FSMC_PMEM4_MEMHIZ4_2   (0x04UL << FSMC_PMEM4_MEMHIZ4_Pos)
    -
    -

    0x04000000

    - -
    -
    - -

    ◆ FSMC_PMEM4_MEMHIZ4_3

    - -
    -
    - - - - -
    #define FSMC_PMEM4_MEMHIZ4_3   (0x08UL << FSMC_PMEM4_MEMHIZ4_Pos)
    -
    -

    0x08000000

    - -
    -
    - -

    ◆ FSMC_PMEM4_MEMHIZ4_4

    - -
    -
    - - - - -
    #define FSMC_PMEM4_MEMHIZ4_4   (0x10UL << FSMC_PMEM4_MEMHIZ4_Pos)
    -
    -

    0x10000000

    - -
    -
    - -

    ◆ FSMC_PMEM4_MEMHIZ4_5

    - -
    -
    - - - - -
    #define FSMC_PMEM4_MEMHIZ4_5   (0x20UL << FSMC_PMEM4_MEMHIZ4_Pos)
    -
    -

    0x20000000

    - -
    -
    - -

    ◆ FSMC_PMEM4_MEMHIZ4_6

    - -
    -
    - - - - -
    #define FSMC_PMEM4_MEMHIZ4_6   (0x40UL << FSMC_PMEM4_MEMHIZ4_Pos)
    -
    -

    0x40000000

    - -
    -
    - -

    ◆ FSMC_PMEM4_MEMHIZ4_7

    - -
    -
    - - - - -
    #define FSMC_PMEM4_MEMHIZ4_7   (0x80UL << FSMC_PMEM4_MEMHIZ4_Pos)
    -
    -

    0x80000000

    - -
    -
    - -

    ◆ FSMC_PATT2_ATTSET2_Pos

    - -
    -
    - - - - -
    #define FSMC_PATT2_ATTSET2_Pos   (0U)
    -
    - -
    -
    - -

    ◆ FSMC_PATT2_ATTSET2_Msk

    - -
    -
    - - - - -
    #define FSMC_PATT2_ATTSET2_Msk   (0xFFUL << FSMC_PATT2_ATTSET2_Pos)
    -
    -

    0x000000FF

    - -
    -
    - -

    ◆ FSMC_PATT2_ATTSET2

    - -
    -
    - - - - -
    #define FSMC_PATT2_ATTSET2   FSMC_PATT2_ATTSET2_Msk
    -
    -

    ATTSET2[7:0] bits (Attribute memory 2 setup time)

    - -
    -
    - -

    ◆ FSMC_PATT2_ATTSET2_0

    - -
    -
    - - - - -
    #define FSMC_PATT2_ATTSET2_0   (0x01UL << FSMC_PATT2_ATTSET2_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ FSMC_PATT2_ATTSET2_1

    - -
    -
    - - - - -
    #define FSMC_PATT2_ATTSET2_1   (0x02UL << FSMC_PATT2_ATTSET2_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ FSMC_PATT2_ATTSET2_2

    - -
    -
    - - - - -
    #define FSMC_PATT2_ATTSET2_2   (0x04UL << FSMC_PATT2_ATTSET2_Pos)
    -
    -

    0x00000004

    - -
    -
    - -

    ◆ FSMC_PATT2_ATTSET2_3

    - -
    -
    - - - - -
    #define FSMC_PATT2_ATTSET2_3   (0x08UL << FSMC_PATT2_ATTSET2_Pos)
    -
    -

    0x00000008

    - -
    -
    - -

    ◆ FSMC_PATT2_ATTSET2_4

    - -
    -
    - - - - -
    #define FSMC_PATT2_ATTSET2_4   (0x10UL << FSMC_PATT2_ATTSET2_Pos)
    -
    -

    0x00000010

    - -
    -
    - -

    ◆ FSMC_PATT2_ATTSET2_5

    - -
    -
    - - - - -
    #define FSMC_PATT2_ATTSET2_5   (0x20UL << FSMC_PATT2_ATTSET2_Pos)
    -
    -

    0x00000020

    - -
    -
    - -

    ◆ FSMC_PATT2_ATTSET2_6

    - -
    -
    - - - - -
    #define FSMC_PATT2_ATTSET2_6   (0x40UL << FSMC_PATT2_ATTSET2_Pos)
    -
    -

    0x00000040

    - -
    -
    - -

    ◆ FSMC_PATT2_ATTSET2_7

    - -
    -
    - - - - -
    #define FSMC_PATT2_ATTSET2_7   (0x80UL << FSMC_PATT2_ATTSET2_Pos)
    -
    -

    0x00000080

    - -
    -
    - -

    ◆ FSMC_PATT2_ATTWAIT2_Pos

    - -
    -
    - - - - -
    #define FSMC_PATT2_ATTWAIT2_Pos   (8U)
    -
    - -
    -
    - -

    ◆ FSMC_PATT2_ATTWAIT2_Msk

    - -
    -
    - - - - -
    #define FSMC_PATT2_ATTWAIT2_Msk   (0xFFUL << FSMC_PATT2_ATTWAIT2_Pos)
    -
    -

    0x0000FF00

    - -
    -
    - -

    ◆ FSMC_PATT2_ATTWAIT2

    - -
    -
    - - - - -
    #define FSMC_PATT2_ATTWAIT2   FSMC_PATT2_ATTWAIT2_Msk
    -
    -

    ATTWAIT2[7:0] bits (Attribute memory 2 wait time)

    - -
    -
    - -

    ◆ FSMC_PATT2_ATTWAIT2_0

    - -
    -
    - - - - -
    #define FSMC_PATT2_ATTWAIT2_0   (0x01UL << FSMC_PATT2_ATTWAIT2_Pos)
    -
    -

    0x00000100

    - -
    -
    - -

    ◆ FSMC_PATT2_ATTWAIT2_1

    - -
    -
    - - - - -
    #define FSMC_PATT2_ATTWAIT2_1   (0x02UL << FSMC_PATT2_ATTWAIT2_Pos)
    -
    -

    0x00000200

    - -
    -
    - -

    ◆ FSMC_PATT2_ATTWAIT2_2

    - -
    -
    - - - - -
    #define FSMC_PATT2_ATTWAIT2_2   (0x04UL << FSMC_PATT2_ATTWAIT2_Pos)
    -
    -

    0x00000400

    - -
    -
    - -

    ◆ FSMC_PATT2_ATTWAIT2_3

    - -
    -
    - - - - -
    #define FSMC_PATT2_ATTWAIT2_3   (0x08UL << FSMC_PATT2_ATTWAIT2_Pos)
    -
    -

    0x00000800

    - -
    -
    - -

    ◆ FSMC_PATT2_ATTWAIT2_4

    - -
    -
    - - - - -
    #define FSMC_PATT2_ATTWAIT2_4   (0x10UL << FSMC_PATT2_ATTWAIT2_Pos)
    -
    -

    0x00001000

    - -
    -
    - -

    ◆ FSMC_PATT2_ATTWAIT2_5

    - -
    -
    - - - - -
    #define FSMC_PATT2_ATTWAIT2_5   (0x20UL << FSMC_PATT2_ATTWAIT2_Pos)
    -
    -

    0x00002000

    - -
    -
    - -

    ◆ FSMC_PATT2_ATTWAIT2_6

    - -
    -
    - - - - -
    #define FSMC_PATT2_ATTWAIT2_6   (0x40UL << FSMC_PATT2_ATTWAIT2_Pos)
    -
    -

    0x00004000

    - -
    -
    - -

    ◆ FSMC_PATT2_ATTWAIT2_7

    - -
    -
    - - - - -
    #define FSMC_PATT2_ATTWAIT2_7   (0x80UL << FSMC_PATT2_ATTWAIT2_Pos)
    -
    -

    0x00008000

    - -
    -
    - -

    ◆ FSMC_PATT2_ATTHOLD2_Pos

    - -
    -
    - - - - -
    #define FSMC_PATT2_ATTHOLD2_Pos   (16U)
    -
    - -
    -
    - -

    ◆ FSMC_PATT2_ATTHOLD2_Msk

    - -
    -
    - - - - -
    #define FSMC_PATT2_ATTHOLD2_Msk   (0xFFUL << FSMC_PATT2_ATTHOLD2_Pos)
    -
    -

    0x00FF0000

    - -
    -
    - -

    ◆ FSMC_PATT2_ATTHOLD2

    - -
    -
    - - - - -
    #define FSMC_PATT2_ATTHOLD2   FSMC_PATT2_ATTHOLD2_Msk
    -
    -

    ATTHOLD2[7:0] bits (Attribute memory 2 hold time)

    - -
    -
    - -

    ◆ FSMC_PATT2_ATTHOLD2_0

    - -
    -
    - - - - -
    #define FSMC_PATT2_ATTHOLD2_0   (0x01UL << FSMC_PATT2_ATTHOLD2_Pos)
    -
    -

    0x00010000

    - -
    -
    - -

    ◆ FSMC_PATT2_ATTHOLD2_1

    - -
    -
    - - - - -
    #define FSMC_PATT2_ATTHOLD2_1   (0x02UL << FSMC_PATT2_ATTHOLD2_Pos)
    -
    -

    0x00020000

    - -
    -
    - -

    ◆ FSMC_PATT2_ATTHOLD2_2

    - -
    -
    - - - - -
    #define FSMC_PATT2_ATTHOLD2_2   (0x04UL << FSMC_PATT2_ATTHOLD2_Pos)
    -
    -

    0x00040000

    - -
    -
    - -

    ◆ FSMC_PATT2_ATTHOLD2_3

    - -
    -
    - - - - -
    #define FSMC_PATT2_ATTHOLD2_3   (0x08UL << FSMC_PATT2_ATTHOLD2_Pos)
    -
    -

    0x00080000

    - -
    -
    - -

    ◆ FSMC_PATT2_ATTHOLD2_4

    - -
    -
    - - - - -
    #define FSMC_PATT2_ATTHOLD2_4   (0x10UL << FSMC_PATT2_ATTHOLD2_Pos)
    -
    -

    0x00100000

    - -
    -
    - -

    ◆ FSMC_PATT2_ATTHOLD2_5

    - -
    -
    - - - - -
    #define FSMC_PATT2_ATTHOLD2_5   (0x20UL << FSMC_PATT2_ATTHOLD2_Pos)
    -
    -

    0x00200000

    - -
    -
    - -

    ◆ FSMC_PATT2_ATTHOLD2_6

    - -
    -
    - - - - -
    #define FSMC_PATT2_ATTHOLD2_6   (0x40UL << FSMC_PATT2_ATTHOLD2_Pos)
    -
    -

    0x00400000

    - -
    -
    - -

    ◆ FSMC_PATT2_ATTHOLD2_7

    - -
    -
    - - - - -
    #define FSMC_PATT2_ATTHOLD2_7   (0x80UL << FSMC_PATT2_ATTHOLD2_Pos)
    -
    -

    0x00800000

    - -
    -
    - -

    ◆ FSMC_PATT2_ATTHIZ2_Pos

    - -
    -
    - - - - -
    #define FSMC_PATT2_ATTHIZ2_Pos   (24U)
    -
    - -
    -
    - -

    ◆ FSMC_PATT2_ATTHIZ2_Msk

    - -
    -
    - - - - -
    #define FSMC_PATT2_ATTHIZ2_Msk   (0xFFUL << FSMC_PATT2_ATTHIZ2_Pos)
    -
    -

    0xFF000000

    - -
    -
    - -

    ◆ FSMC_PATT2_ATTHIZ2

    - -
    -
    - - - - -
    #define FSMC_PATT2_ATTHIZ2   FSMC_PATT2_ATTHIZ2_Msk
    -
    -

    ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time)

    - -
    -
    - -

    ◆ FSMC_PATT2_ATTHIZ2_0

    - -
    -
    - - - - -
    #define FSMC_PATT2_ATTHIZ2_0   (0x01UL << FSMC_PATT2_ATTHIZ2_Pos)
    -
    -

    0x01000000

    - -
    -
    - -

    ◆ FSMC_PATT2_ATTHIZ2_1

    - -
    -
    - - - - -
    #define FSMC_PATT2_ATTHIZ2_1   (0x02UL << FSMC_PATT2_ATTHIZ2_Pos)
    -
    -

    0x02000000

    - -
    -
    - -

    ◆ FSMC_PATT2_ATTHIZ2_2

    - -
    -
    - - - - -
    #define FSMC_PATT2_ATTHIZ2_2   (0x04UL << FSMC_PATT2_ATTHIZ2_Pos)
    -
    -

    0x04000000

    - -
    -
    - -

    ◆ FSMC_PATT2_ATTHIZ2_3

    - -
    -
    - - - - -
    #define FSMC_PATT2_ATTHIZ2_3   (0x08UL << FSMC_PATT2_ATTHIZ2_Pos)
    -
    -

    0x08000000

    - -
    -
    - -

    ◆ FSMC_PATT2_ATTHIZ2_4

    - -
    -
    - - - - -
    #define FSMC_PATT2_ATTHIZ2_4   (0x10UL << FSMC_PATT2_ATTHIZ2_Pos)
    -
    -

    0x10000000

    - -
    -
    - -

    ◆ FSMC_PATT2_ATTHIZ2_5

    - -
    -
    - - - - -
    #define FSMC_PATT2_ATTHIZ2_5   (0x20UL << FSMC_PATT2_ATTHIZ2_Pos)
    -
    -

    0x20000000

    - -
    -
    - -

    ◆ FSMC_PATT2_ATTHIZ2_6

    - -
    -
    - - - - -
    #define FSMC_PATT2_ATTHIZ2_6   (0x40UL << FSMC_PATT2_ATTHIZ2_Pos)
    -
    -

    0x40000000

    - -
    -
    - -

    ◆ FSMC_PATT2_ATTHIZ2_7

    - -
    -
    - - - - -
    #define FSMC_PATT2_ATTHIZ2_7   (0x80UL << FSMC_PATT2_ATTHIZ2_Pos)
    -
    -

    0x80000000

    - -
    -
    - -

    ◆ FSMC_PATT3_ATTSET3_Pos

    - -
    -
    - - - - -
    #define FSMC_PATT3_ATTSET3_Pos   (0U)
    -
    - -
    -
    - -

    ◆ FSMC_PATT3_ATTSET3_Msk

    - -
    -
    - - - - -
    #define FSMC_PATT3_ATTSET3_Msk   (0xFFUL << FSMC_PATT3_ATTSET3_Pos)
    -
    -

    0x000000FF

    - -
    -
    - -

    ◆ FSMC_PATT3_ATTSET3

    - -
    -
    - - - - -
    #define FSMC_PATT3_ATTSET3   FSMC_PATT3_ATTSET3_Msk
    -
    -

    ATTSET3[7:0] bits (Attribute memory 3 setup time)

    - -
    -
    - -

    ◆ FSMC_PATT3_ATTSET3_0

    - -
    -
    - - - - -
    #define FSMC_PATT3_ATTSET3_0   (0x01UL << FSMC_PATT3_ATTSET3_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ FSMC_PATT3_ATTSET3_1

    - -
    -
    - - - - -
    #define FSMC_PATT3_ATTSET3_1   (0x02UL << FSMC_PATT3_ATTSET3_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ FSMC_PATT3_ATTSET3_2

    - -
    -
    - - - - -
    #define FSMC_PATT3_ATTSET3_2   (0x04UL << FSMC_PATT3_ATTSET3_Pos)
    -
    -

    0x00000004

    - -
    -
    - -

    ◆ FSMC_PATT3_ATTSET3_3

    - -
    -
    - - - - -
    #define FSMC_PATT3_ATTSET3_3   (0x08UL << FSMC_PATT3_ATTSET3_Pos)
    -
    -

    0x00000008

    - -
    -
    - -

    ◆ FSMC_PATT3_ATTSET3_4

    - -
    -
    - - - - -
    #define FSMC_PATT3_ATTSET3_4   (0x10UL << FSMC_PATT3_ATTSET3_Pos)
    -
    -

    0x00000010

    - -
    -
    - -

    ◆ FSMC_PATT3_ATTSET3_5

    - -
    -
    - - - - -
    #define FSMC_PATT3_ATTSET3_5   (0x20UL << FSMC_PATT3_ATTSET3_Pos)
    -
    -

    0x00000020

    - -
    -
    - -

    ◆ FSMC_PATT3_ATTSET3_6

    - -
    -
    - - - - -
    #define FSMC_PATT3_ATTSET3_6   (0x40UL << FSMC_PATT3_ATTSET3_Pos)
    -
    -

    0x00000040

    - -
    -
    - -

    ◆ FSMC_PATT3_ATTSET3_7

    - -
    -
    - - - - -
    #define FSMC_PATT3_ATTSET3_7   (0x80UL << FSMC_PATT3_ATTSET3_Pos)
    -
    -

    0x00000080

    - -
    -
    - -

    ◆ FSMC_PATT3_ATTWAIT3_Pos

    - -
    -
    - - - - -
    #define FSMC_PATT3_ATTWAIT3_Pos   (8U)
    -
    - -
    -
    - -

    ◆ FSMC_PATT3_ATTWAIT3_Msk

    - -
    -
    - - - - -
    #define FSMC_PATT3_ATTWAIT3_Msk   (0xFFUL << FSMC_PATT3_ATTWAIT3_Pos)
    -
    -

    0x0000FF00

    - -
    -
    - -

    ◆ FSMC_PATT3_ATTWAIT3

    - -
    -
    - - - - -
    #define FSMC_PATT3_ATTWAIT3   FSMC_PATT3_ATTWAIT3_Msk
    -
    -

    ATTWAIT3[7:0] bits (Attribute memory 3 wait time)

    - -
    -
    - -

    ◆ FSMC_PATT3_ATTWAIT3_0

    - -
    -
    - - - - -
    #define FSMC_PATT3_ATTWAIT3_0   (0x01UL << FSMC_PATT3_ATTWAIT3_Pos)
    -
    -

    0x00000100

    - -
    -
    - -

    ◆ FSMC_PATT3_ATTWAIT3_1

    - -
    -
    - - - - -
    #define FSMC_PATT3_ATTWAIT3_1   (0x02UL << FSMC_PATT3_ATTWAIT3_Pos)
    -
    -

    0x00000200

    - -
    -
    - -

    ◆ FSMC_PATT3_ATTWAIT3_2

    - -
    -
    - - - - -
    #define FSMC_PATT3_ATTWAIT3_2   (0x04UL << FSMC_PATT3_ATTWAIT3_Pos)
    -
    -

    0x00000400

    - -
    -
    - -

    ◆ FSMC_PATT3_ATTWAIT3_3

    - -
    -
    - - - - -
    #define FSMC_PATT3_ATTWAIT3_3   (0x08UL << FSMC_PATT3_ATTWAIT3_Pos)
    -
    -

    0x00000800

    - -
    -
    - -

    ◆ FSMC_PATT3_ATTWAIT3_4

    - -
    -
    - - - - -
    #define FSMC_PATT3_ATTWAIT3_4   (0x10UL << FSMC_PATT3_ATTWAIT3_Pos)
    -
    -

    0x00001000

    - -
    -
    - -

    ◆ FSMC_PATT3_ATTWAIT3_5

    - -
    -
    - - - - -
    #define FSMC_PATT3_ATTWAIT3_5   (0x20UL << FSMC_PATT3_ATTWAIT3_Pos)
    -
    -

    0x00002000

    - -
    -
    - -

    ◆ FSMC_PATT3_ATTWAIT3_6

    - -
    -
    - - - - -
    #define FSMC_PATT3_ATTWAIT3_6   (0x40UL << FSMC_PATT3_ATTWAIT3_Pos)
    -
    -

    0x00004000

    - -
    -
    - -

    ◆ FSMC_PATT3_ATTWAIT3_7

    - -
    -
    - - - - -
    #define FSMC_PATT3_ATTWAIT3_7   (0x80UL << FSMC_PATT3_ATTWAIT3_Pos)
    -
    -

    0x00008000

    - -
    -
    - -

    ◆ FSMC_PATT3_ATTHOLD3_Pos

    - -
    -
    - - - - -
    #define FSMC_PATT3_ATTHOLD3_Pos   (16U)
    -
    - -
    -
    - -

    ◆ FSMC_PATT3_ATTHOLD3_Msk

    - -
    -
    - - - - -
    #define FSMC_PATT3_ATTHOLD3_Msk   (0xFFUL << FSMC_PATT3_ATTHOLD3_Pos)
    -
    -

    0x00FF0000

    - -
    -
    - -

    ◆ FSMC_PATT3_ATTHOLD3

    - -
    -
    - - - - -
    #define FSMC_PATT3_ATTHOLD3   FSMC_PATT3_ATTHOLD3_Msk
    -
    -

    ATTHOLD3[7:0] bits (Attribute memory 3 hold time)

    - -
    -
    - -

    ◆ FSMC_PATT3_ATTHOLD3_0

    - -
    -
    - - - - -
    #define FSMC_PATT3_ATTHOLD3_0   (0x01UL << FSMC_PATT3_ATTHOLD3_Pos)
    -
    -

    0x00010000

    - -
    -
    - -

    ◆ FSMC_PATT3_ATTHOLD3_1

    - -
    -
    - - - - -
    #define FSMC_PATT3_ATTHOLD3_1   (0x02UL << FSMC_PATT3_ATTHOLD3_Pos)
    -
    -

    0x00020000

    - -
    -
    - -

    ◆ FSMC_PATT3_ATTHOLD3_2

    - -
    -
    - - - - -
    #define FSMC_PATT3_ATTHOLD3_2   (0x04UL << FSMC_PATT3_ATTHOLD3_Pos)
    -
    -

    0x00040000

    - -
    -
    - -

    ◆ FSMC_PATT3_ATTHOLD3_3

    - -
    -
    - - - - -
    #define FSMC_PATT3_ATTHOLD3_3   (0x08UL << FSMC_PATT3_ATTHOLD3_Pos)
    -
    -

    0x00080000

    - -
    -
    - -

    ◆ FSMC_PATT3_ATTHOLD3_4

    - -
    -
    - - - - -
    #define FSMC_PATT3_ATTHOLD3_4   (0x10UL << FSMC_PATT3_ATTHOLD3_Pos)
    -
    -

    0x00100000

    - -
    -
    - -

    ◆ FSMC_PATT3_ATTHOLD3_5

    - -
    -
    - - - - -
    #define FSMC_PATT3_ATTHOLD3_5   (0x20UL << FSMC_PATT3_ATTHOLD3_Pos)
    -
    -

    0x00200000

    - -
    -
    - -

    ◆ FSMC_PATT3_ATTHOLD3_6

    - -
    -
    - - - - -
    #define FSMC_PATT3_ATTHOLD3_6   (0x40UL << FSMC_PATT3_ATTHOLD3_Pos)
    -
    -

    0x00400000

    - -
    -
    - -

    ◆ FSMC_PATT3_ATTHOLD3_7

    - -
    -
    - - - - -
    #define FSMC_PATT3_ATTHOLD3_7   (0x80UL << FSMC_PATT3_ATTHOLD3_Pos)
    -
    -

    0x00800000

    - -
    -
    - -

    ◆ FSMC_PATT3_ATTHIZ3_Pos

    - -
    -
    - - - - -
    #define FSMC_PATT3_ATTHIZ3_Pos   (24U)
    -
    - -
    -
    - -

    ◆ FSMC_PATT3_ATTHIZ3_Msk

    - -
    -
    - - - - -
    #define FSMC_PATT3_ATTHIZ3_Msk   (0xFFUL << FSMC_PATT3_ATTHIZ3_Pos)
    -
    -

    0xFF000000

    - -
    -
    - -

    ◆ FSMC_PATT3_ATTHIZ3

    - -
    -
    - - - - -
    #define FSMC_PATT3_ATTHIZ3   FSMC_PATT3_ATTHIZ3_Msk
    -
    -

    ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time)

    - -
    -
    - -

    ◆ FSMC_PATT3_ATTHIZ3_0

    - -
    -
    - - - - -
    #define FSMC_PATT3_ATTHIZ3_0   (0x01UL << FSMC_PATT3_ATTHIZ3_Pos)
    -
    -

    0x01000000

    - -
    -
    - -

    ◆ FSMC_PATT3_ATTHIZ3_1

    - -
    -
    - - - - -
    #define FSMC_PATT3_ATTHIZ3_1   (0x02UL << FSMC_PATT3_ATTHIZ3_Pos)
    -
    -

    0x02000000

    - -
    -
    - -

    ◆ FSMC_PATT3_ATTHIZ3_2

    - -
    -
    - - - - -
    #define FSMC_PATT3_ATTHIZ3_2   (0x04UL << FSMC_PATT3_ATTHIZ3_Pos)
    -
    -

    0x04000000

    - -
    -
    - -

    ◆ FSMC_PATT3_ATTHIZ3_3

    - -
    -
    - - - - -
    #define FSMC_PATT3_ATTHIZ3_3   (0x08UL << FSMC_PATT3_ATTHIZ3_Pos)
    -
    -

    0x08000000

    - -
    -
    - -

    ◆ FSMC_PATT3_ATTHIZ3_4

    - -
    -
    - - - - -
    #define FSMC_PATT3_ATTHIZ3_4   (0x10UL << FSMC_PATT3_ATTHIZ3_Pos)
    -
    -

    0x10000000

    - -
    -
    - -

    ◆ FSMC_PATT3_ATTHIZ3_5

    - -
    -
    - - - - -
    #define FSMC_PATT3_ATTHIZ3_5   (0x20UL << FSMC_PATT3_ATTHIZ3_Pos)
    -
    -

    0x20000000

    - -
    -
    - -

    ◆ FSMC_PATT3_ATTHIZ3_6

    - -
    -
    - - - - -
    #define FSMC_PATT3_ATTHIZ3_6   (0x40UL << FSMC_PATT3_ATTHIZ3_Pos)
    -
    -

    0x40000000

    - -
    -
    - -

    ◆ FSMC_PATT3_ATTHIZ3_7

    - -
    -
    - - - - -
    #define FSMC_PATT3_ATTHIZ3_7   (0x80UL << FSMC_PATT3_ATTHIZ3_Pos)
    -
    -

    0x80000000

    - -
    -
    - -

    ◆ FSMC_PATT4_ATTSET4_Pos

    - -
    -
    - - - - -
    #define FSMC_PATT4_ATTSET4_Pos   (0U)
    -
    - -
    -
    - -

    ◆ FSMC_PATT4_ATTSET4_Msk

    - -
    -
    - - - - -
    #define FSMC_PATT4_ATTSET4_Msk   (0xFFUL << FSMC_PATT4_ATTSET4_Pos)
    -
    -

    0x000000FF

    - -
    -
    - -

    ◆ FSMC_PATT4_ATTSET4

    - -
    -
    - - - - -
    #define FSMC_PATT4_ATTSET4   FSMC_PATT4_ATTSET4_Msk
    -
    -

    ATTSET4[7:0] bits (Attribute memory 4 setup time)

    - -
    -
    - -

    ◆ FSMC_PATT4_ATTSET4_0

    - -
    -
    - - - - -
    #define FSMC_PATT4_ATTSET4_0   (0x01UL << FSMC_PATT4_ATTSET4_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ FSMC_PATT4_ATTSET4_1

    - -
    -
    - - - - -
    #define FSMC_PATT4_ATTSET4_1   (0x02UL << FSMC_PATT4_ATTSET4_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ FSMC_PATT4_ATTSET4_2

    - -
    -
    - - - - -
    #define FSMC_PATT4_ATTSET4_2   (0x04UL << FSMC_PATT4_ATTSET4_Pos)
    -
    -

    0x00000004

    - -
    -
    - -

    ◆ FSMC_PATT4_ATTSET4_3

    - -
    -
    - - - - -
    #define FSMC_PATT4_ATTSET4_3   (0x08UL << FSMC_PATT4_ATTSET4_Pos)
    -
    -

    0x00000008

    - -
    -
    - -

    ◆ FSMC_PATT4_ATTSET4_4

    - -
    -
    - - - - -
    #define FSMC_PATT4_ATTSET4_4   (0x10UL << FSMC_PATT4_ATTSET4_Pos)
    -
    -

    0x00000010

    - -
    -
    - -

    ◆ FSMC_PATT4_ATTSET4_5

    - -
    -
    - - - - -
    #define FSMC_PATT4_ATTSET4_5   (0x20UL << FSMC_PATT4_ATTSET4_Pos)
    -
    -

    0x00000020

    - -
    -
    - -

    ◆ FSMC_PATT4_ATTSET4_6

    - -
    -
    - - - - -
    #define FSMC_PATT4_ATTSET4_6   (0x40UL << FSMC_PATT4_ATTSET4_Pos)
    -
    -

    0x00000040

    - -
    -
    - -

    ◆ FSMC_PATT4_ATTSET4_7

    - -
    -
    - - - - -
    #define FSMC_PATT4_ATTSET4_7   (0x80UL << FSMC_PATT4_ATTSET4_Pos)
    -
    -

    0x00000080

    - -
    -
    - -

    ◆ FSMC_PATT4_ATTWAIT4_Pos

    - -
    -
    - - - - -
    #define FSMC_PATT4_ATTWAIT4_Pos   (8U)
    -
    - -
    -
    - -

    ◆ FSMC_PATT4_ATTWAIT4_Msk

    - -
    -
    - - - - -
    #define FSMC_PATT4_ATTWAIT4_Msk   (0xFFUL << FSMC_PATT4_ATTWAIT4_Pos)
    -
    -

    0x0000FF00

    - -
    -
    - -

    ◆ FSMC_PATT4_ATTWAIT4

    - -
    -
    - - - - -
    #define FSMC_PATT4_ATTWAIT4   FSMC_PATT4_ATTWAIT4_Msk
    -
    -

    ATTWAIT4[7:0] bits (Attribute memory 4 wait time)

    - -
    -
    - -

    ◆ FSMC_PATT4_ATTWAIT4_0

    - -
    -
    - - - - -
    #define FSMC_PATT4_ATTWAIT4_0   (0x01UL << FSMC_PATT4_ATTWAIT4_Pos)
    -
    -

    0x00000100

    - -
    -
    - -

    ◆ FSMC_PATT4_ATTWAIT4_1

    - -
    -
    - - - - -
    #define FSMC_PATT4_ATTWAIT4_1   (0x02UL << FSMC_PATT4_ATTWAIT4_Pos)
    -
    -

    0x00000200

    - -
    -
    - -

    ◆ FSMC_PATT4_ATTWAIT4_2

    - -
    -
    - - - - -
    #define FSMC_PATT4_ATTWAIT4_2   (0x04UL << FSMC_PATT4_ATTWAIT4_Pos)
    -
    -

    0x00000400

    - -
    -
    - -

    ◆ FSMC_PATT4_ATTWAIT4_3

    - -
    -
    - - - - -
    #define FSMC_PATT4_ATTWAIT4_3   (0x08UL << FSMC_PATT4_ATTWAIT4_Pos)
    -
    -

    0x00000800

    - -
    -
    - -

    ◆ FSMC_PATT4_ATTWAIT4_4

    - -
    -
    - - - - -
    #define FSMC_PATT4_ATTWAIT4_4   (0x10UL << FSMC_PATT4_ATTWAIT4_Pos)
    -
    -

    0x00001000

    - -
    -
    - -

    ◆ FSMC_PATT4_ATTWAIT4_5

    - -
    -
    - - - - -
    #define FSMC_PATT4_ATTWAIT4_5   (0x20UL << FSMC_PATT4_ATTWAIT4_Pos)
    -
    -

    0x00002000

    - -
    -
    - -

    ◆ FSMC_PATT4_ATTWAIT4_6

    - -
    -
    - - - - -
    #define FSMC_PATT4_ATTWAIT4_6   (0x40UL << FSMC_PATT4_ATTWAIT4_Pos)
    -
    -

    0x00004000

    - -
    -
    - -

    ◆ FSMC_PATT4_ATTWAIT4_7

    - -
    -
    - - - - -
    #define FSMC_PATT4_ATTWAIT4_7   (0x80UL << FSMC_PATT4_ATTWAIT4_Pos)
    -
    -

    0x00008000

    - -
    -
    - -

    ◆ FSMC_PATT4_ATTHOLD4_Pos

    - -
    -
    - - - - -
    #define FSMC_PATT4_ATTHOLD4_Pos   (16U)
    -
    - -
    -
    - -

    ◆ FSMC_PATT4_ATTHOLD4_Msk

    - -
    -
    - - - - -
    #define FSMC_PATT4_ATTHOLD4_Msk   (0xFFUL << FSMC_PATT4_ATTHOLD4_Pos)
    -
    -

    0x00FF0000

    - -
    -
    - -

    ◆ FSMC_PATT4_ATTHOLD4

    - -
    -
    - - - - -
    #define FSMC_PATT4_ATTHOLD4   FSMC_PATT4_ATTHOLD4_Msk
    -
    -

    ATTHOLD4[7:0] bits (Attribute memory 4 hold time)

    - -
    -
    - -

    ◆ FSMC_PATT4_ATTHOLD4_0

    - -
    -
    - - - - -
    #define FSMC_PATT4_ATTHOLD4_0   (0x01UL << FSMC_PATT4_ATTHOLD4_Pos)
    -
    -

    0x00010000

    - -
    -
    - -

    ◆ FSMC_PATT4_ATTHOLD4_1

    - -
    -
    - - - - -
    #define FSMC_PATT4_ATTHOLD4_1   (0x02UL << FSMC_PATT4_ATTHOLD4_Pos)
    -
    -

    0x00020000

    - -
    -
    - -

    ◆ FSMC_PATT4_ATTHOLD4_2

    - -
    -
    - - - - -
    #define FSMC_PATT4_ATTHOLD4_2   (0x04UL << FSMC_PATT4_ATTHOLD4_Pos)
    -
    -

    0x00040000

    - -
    -
    - -

    ◆ FSMC_PATT4_ATTHOLD4_3

    - -
    -
    - - - - -
    #define FSMC_PATT4_ATTHOLD4_3   (0x08UL << FSMC_PATT4_ATTHOLD4_Pos)
    -
    -

    0x00080000

    - -
    -
    - -

    ◆ FSMC_PATT4_ATTHOLD4_4

    - -
    -
    - - - - -
    #define FSMC_PATT4_ATTHOLD4_4   (0x10UL << FSMC_PATT4_ATTHOLD4_Pos)
    -
    -

    0x00100000

    - -
    -
    - -

    ◆ FSMC_PATT4_ATTHOLD4_5

    - -
    -
    - - - - -
    #define FSMC_PATT4_ATTHOLD4_5   (0x20UL << FSMC_PATT4_ATTHOLD4_Pos)
    -
    -

    0x00200000

    - -
    -
    - -

    ◆ FSMC_PATT4_ATTHOLD4_6

    - -
    -
    - - - - -
    #define FSMC_PATT4_ATTHOLD4_6   (0x40UL << FSMC_PATT4_ATTHOLD4_Pos)
    -
    -

    0x00400000

    - -
    -
    - -

    ◆ FSMC_PATT4_ATTHOLD4_7

    - -
    -
    - - - - -
    #define FSMC_PATT4_ATTHOLD4_7   (0x80UL << FSMC_PATT4_ATTHOLD4_Pos)
    -
    -

    0x00800000

    - -
    -
    - -

    ◆ FSMC_PATT4_ATTHIZ4_Pos

    - -
    -
    - - - - -
    #define FSMC_PATT4_ATTHIZ4_Pos   (24U)
    -
    - -
    -
    - -

    ◆ FSMC_PATT4_ATTHIZ4_Msk

    - -
    -
    - - - - -
    #define FSMC_PATT4_ATTHIZ4_Msk   (0xFFUL << FSMC_PATT4_ATTHIZ4_Pos)
    -
    -

    0xFF000000

    - -
    -
    - -

    ◆ FSMC_PATT4_ATTHIZ4

    - -
    -
    - - - - -
    #define FSMC_PATT4_ATTHIZ4   FSMC_PATT4_ATTHIZ4_Msk
    -
    -

    ATTHIZ4[7:0] bits (Attribute memory 4 databus HiZ time)

    - -
    -
    - -

    ◆ FSMC_PATT4_ATTHIZ4_0

    - -
    -
    - - - - -
    #define FSMC_PATT4_ATTHIZ4_0   (0x01UL << FSMC_PATT4_ATTHIZ4_Pos)
    -
    -

    0x01000000

    - -
    -
    - -

    ◆ FSMC_PATT4_ATTHIZ4_1

    - -
    -
    - - - - -
    #define FSMC_PATT4_ATTHIZ4_1   (0x02UL << FSMC_PATT4_ATTHIZ4_Pos)
    -
    -

    0x02000000

    - -
    -
    - -

    ◆ FSMC_PATT4_ATTHIZ4_2

    - -
    -
    - - - - -
    #define FSMC_PATT4_ATTHIZ4_2   (0x04UL << FSMC_PATT4_ATTHIZ4_Pos)
    -
    -

    0x04000000

    - -
    -
    - -

    ◆ FSMC_PATT4_ATTHIZ4_3

    - -
    -
    - - - - -
    #define FSMC_PATT4_ATTHIZ4_3   (0x08UL << FSMC_PATT4_ATTHIZ4_Pos)
    -
    -

    0x08000000

    - -
    -
    - -

    ◆ FSMC_PATT4_ATTHIZ4_4

    - -
    -
    - - - - -
    #define FSMC_PATT4_ATTHIZ4_4   (0x10UL << FSMC_PATT4_ATTHIZ4_Pos)
    -
    -

    0x10000000

    - -
    -
    - -

    ◆ FSMC_PATT4_ATTHIZ4_5

    - -
    -
    - - - - -
    #define FSMC_PATT4_ATTHIZ4_5   (0x20UL << FSMC_PATT4_ATTHIZ4_Pos)
    -
    -

    0x20000000

    - -
    -
    - -

    ◆ FSMC_PATT4_ATTHIZ4_6

    - -
    -
    - - - - -
    #define FSMC_PATT4_ATTHIZ4_6   (0x40UL << FSMC_PATT4_ATTHIZ4_Pos)
    -
    -

    0x40000000

    - -
    -
    - -

    ◆ FSMC_PATT4_ATTHIZ4_7

    - -
    -
    - - - - -
    #define FSMC_PATT4_ATTHIZ4_7   (0x80UL << FSMC_PATT4_ATTHIZ4_Pos)
    -
    -

    0x80000000

    - -
    -
    - -

    ◆ FSMC_PIO4_IOSET4_Pos

    - -
    -
    - - - - -
    #define FSMC_PIO4_IOSET4_Pos   (0U)
    -
    - -
    -
    - -

    ◆ FSMC_PIO4_IOSET4_Msk

    - -
    -
    - - - - -
    #define FSMC_PIO4_IOSET4_Msk   (0xFFUL << FSMC_PIO4_IOSET4_Pos)
    -
    -

    0x000000FF

    - -
    -
    - -

    ◆ FSMC_PIO4_IOSET4

    - -
    -
    - - - - -
    #define FSMC_PIO4_IOSET4   FSMC_PIO4_IOSET4_Msk
    -
    -

    IOSET4[7:0] bits (I/O 4 setup time)

    - -
    -
    - -

    ◆ FSMC_PIO4_IOSET4_0

    - -
    -
    - - - - -
    #define FSMC_PIO4_IOSET4_0   (0x01UL << FSMC_PIO4_IOSET4_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ FSMC_PIO4_IOSET4_1

    - -
    -
    - - - - -
    #define FSMC_PIO4_IOSET4_1   (0x02UL << FSMC_PIO4_IOSET4_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ FSMC_PIO4_IOSET4_2

    - -
    -
    - - - - -
    #define FSMC_PIO4_IOSET4_2   (0x04UL << FSMC_PIO4_IOSET4_Pos)
    -
    -

    0x00000004

    - -
    -
    - -

    ◆ FSMC_PIO4_IOSET4_3

    - -
    -
    - - - - -
    #define FSMC_PIO4_IOSET4_3   (0x08UL << FSMC_PIO4_IOSET4_Pos)
    -
    -

    0x00000008

    - -
    -
    - -

    ◆ FSMC_PIO4_IOSET4_4

    - -
    -
    - - - - -
    #define FSMC_PIO4_IOSET4_4   (0x10UL << FSMC_PIO4_IOSET4_Pos)
    -
    -

    0x00000010

    - -
    -
    - -

    ◆ FSMC_PIO4_IOSET4_5

    - -
    -
    - - - - -
    #define FSMC_PIO4_IOSET4_5   (0x20UL << FSMC_PIO4_IOSET4_Pos)
    -
    -

    0x00000020

    - -
    -
    - -

    ◆ FSMC_PIO4_IOSET4_6

    - -
    -
    - - - - -
    #define FSMC_PIO4_IOSET4_6   (0x40UL << FSMC_PIO4_IOSET4_Pos)
    -
    -

    0x00000040

    - -
    -
    - -

    ◆ FSMC_PIO4_IOSET4_7

    - -
    -
    - - - - -
    #define FSMC_PIO4_IOSET4_7   (0x80UL << FSMC_PIO4_IOSET4_Pos)
    -
    -

    0x00000080

    - -
    -
    - -

    ◆ FSMC_PIO4_IOWAIT4_Pos

    - -
    -
    - - - - -
    #define FSMC_PIO4_IOWAIT4_Pos   (8U)
    -
    - -
    -
    - -

    ◆ FSMC_PIO4_IOWAIT4_Msk

    - -
    -
    - - - - -
    #define FSMC_PIO4_IOWAIT4_Msk   (0xFFUL << FSMC_PIO4_IOWAIT4_Pos)
    -
    -

    0x0000FF00

    - -
    -
    - -

    ◆ FSMC_PIO4_IOWAIT4

    - -
    -
    - - - - -
    #define FSMC_PIO4_IOWAIT4   FSMC_PIO4_IOWAIT4_Msk
    -
    -

    IOWAIT4[7:0] bits (I/O 4 wait time)

    - -
    -
    - -

    ◆ FSMC_PIO4_IOWAIT4_0

    - -
    -
    - - - - -
    #define FSMC_PIO4_IOWAIT4_0   (0x01UL << FSMC_PIO4_IOWAIT4_Pos)
    -
    -

    0x00000100

    - -
    -
    - -

    ◆ FSMC_PIO4_IOWAIT4_1

    - -
    -
    - - - - -
    #define FSMC_PIO4_IOWAIT4_1   (0x02UL << FSMC_PIO4_IOWAIT4_Pos)
    -
    -

    0x00000200

    - -
    -
    - -

    ◆ FSMC_PIO4_IOWAIT4_2

    - -
    -
    - - - - -
    #define FSMC_PIO4_IOWAIT4_2   (0x04UL << FSMC_PIO4_IOWAIT4_Pos)
    -
    -

    0x00000400

    - -
    -
    - -

    ◆ FSMC_PIO4_IOWAIT4_3

    - -
    -
    - - - - -
    #define FSMC_PIO4_IOWAIT4_3   (0x08UL << FSMC_PIO4_IOWAIT4_Pos)
    -
    -

    0x00000800

    - -
    -
    - -

    ◆ FSMC_PIO4_IOWAIT4_4

    - -
    -
    - - - - -
    #define FSMC_PIO4_IOWAIT4_4   (0x10UL << FSMC_PIO4_IOWAIT4_Pos)
    -
    -

    0x00001000

    - -
    -
    - -

    ◆ FSMC_PIO4_IOWAIT4_5

    - -
    -
    - - - - -
    #define FSMC_PIO4_IOWAIT4_5   (0x20UL << FSMC_PIO4_IOWAIT4_Pos)
    -
    -

    0x00002000

    - -
    -
    - -

    ◆ FSMC_PIO4_IOWAIT4_6

    - -
    -
    - - - - -
    #define FSMC_PIO4_IOWAIT4_6   (0x40UL << FSMC_PIO4_IOWAIT4_Pos)
    -
    -

    0x00004000

    - -
    -
    - -

    ◆ FSMC_PIO4_IOWAIT4_7

    - -
    -
    - - - - -
    #define FSMC_PIO4_IOWAIT4_7   (0x80UL << FSMC_PIO4_IOWAIT4_Pos)
    -
    -

    0x00008000

    - -
    -
    - -

    ◆ FSMC_PIO4_IOHOLD4_Pos

    - -
    -
    - - - - -
    #define FSMC_PIO4_IOHOLD4_Pos   (16U)
    -
    - -
    -
    - -

    ◆ FSMC_PIO4_IOHOLD4_Msk

    - -
    -
    - - - - -
    #define FSMC_PIO4_IOHOLD4_Msk   (0xFFUL << FSMC_PIO4_IOHOLD4_Pos)
    -
    -

    0x00FF0000

    - -
    -
    - -

    ◆ FSMC_PIO4_IOHOLD4

    - -
    -
    - - - - -
    #define FSMC_PIO4_IOHOLD4   FSMC_PIO4_IOHOLD4_Msk
    -
    -

    IOHOLD4[7:0] bits (I/O 4 hold time)

    - -
    -
    - -

    ◆ FSMC_PIO4_IOHOLD4_0

    - -
    -
    - - - - -
    #define FSMC_PIO4_IOHOLD4_0   (0x01UL << FSMC_PIO4_IOHOLD4_Pos)
    -
    -

    0x00010000

    - -
    -
    - -

    ◆ FSMC_PIO4_IOHOLD4_1

    - -
    -
    - - - - -
    #define FSMC_PIO4_IOHOLD4_1   (0x02UL << FSMC_PIO4_IOHOLD4_Pos)
    -
    -

    0x00020000

    - -
    -
    - -

    ◆ FSMC_PIO4_IOHOLD4_2

    - -
    -
    - - - - -
    #define FSMC_PIO4_IOHOLD4_2   (0x04UL << FSMC_PIO4_IOHOLD4_Pos)
    -
    -

    0x00040000

    - -
    -
    - -

    ◆ FSMC_PIO4_IOHOLD4_3

    - -
    -
    - - - - -
    #define FSMC_PIO4_IOHOLD4_3   (0x08UL << FSMC_PIO4_IOHOLD4_Pos)
    -
    -

    0x00080000

    - -
    -
    - -

    ◆ FSMC_PIO4_IOHOLD4_4

    - -
    -
    - - - - -
    #define FSMC_PIO4_IOHOLD4_4   (0x10UL << FSMC_PIO4_IOHOLD4_Pos)
    -
    -

    0x00100000

    - -
    -
    - -

    ◆ FSMC_PIO4_IOHOLD4_5

    - -
    -
    - - - - -
    #define FSMC_PIO4_IOHOLD4_5   (0x20UL << FSMC_PIO4_IOHOLD4_Pos)
    -
    -

    0x00200000

    - -
    -
    - -

    ◆ FSMC_PIO4_IOHOLD4_6

    - -
    -
    - - - - -
    #define FSMC_PIO4_IOHOLD4_6   (0x40UL << FSMC_PIO4_IOHOLD4_Pos)
    -
    -

    0x00400000

    - -
    -
    - -

    ◆ FSMC_PIO4_IOHOLD4_7

    - -
    -
    - - - - -
    #define FSMC_PIO4_IOHOLD4_7   (0x80UL << FSMC_PIO4_IOHOLD4_Pos)
    -
    -

    0x00800000

    - -
    -
    - -

    ◆ FSMC_PIO4_IOHIZ4_Pos

    - -
    -
    - - - - -
    #define FSMC_PIO4_IOHIZ4_Pos   (24U)
    -
    - -
    -
    - -

    ◆ FSMC_PIO4_IOHIZ4_Msk

    - -
    -
    - - - - -
    #define FSMC_PIO4_IOHIZ4_Msk   (0xFFUL << FSMC_PIO4_IOHIZ4_Pos)
    -
    -

    0xFF000000

    - -
    -
    - -

    ◆ FSMC_PIO4_IOHIZ4

    - -
    -
    - - - - -
    #define FSMC_PIO4_IOHIZ4   FSMC_PIO4_IOHIZ4_Msk
    -
    -

    IOHIZ4[7:0] bits (I/O 4 databus HiZ time)

    - -
    -
    - -

    ◆ FSMC_PIO4_IOHIZ4_0

    - -
    -
    - - - - -
    #define FSMC_PIO4_IOHIZ4_0   (0x01UL << FSMC_PIO4_IOHIZ4_Pos)
    -
    -

    0x01000000

    - -
    -
    - -

    ◆ FSMC_PIO4_IOHIZ4_1

    - -
    -
    - - - - -
    #define FSMC_PIO4_IOHIZ4_1   (0x02UL << FSMC_PIO4_IOHIZ4_Pos)
    -
    -

    0x02000000

    - -
    -
    - -

    ◆ FSMC_PIO4_IOHIZ4_2

    - -
    -
    - - - - -
    #define FSMC_PIO4_IOHIZ4_2   (0x04UL << FSMC_PIO4_IOHIZ4_Pos)
    -
    -

    0x04000000

    - -
    -
    - -

    ◆ FSMC_PIO4_IOHIZ4_3

    - -
    -
    - - - - -
    #define FSMC_PIO4_IOHIZ4_3   (0x08UL << FSMC_PIO4_IOHIZ4_Pos)
    -
    -

    0x08000000

    - -
    -
    - -

    ◆ FSMC_PIO4_IOHIZ4_4

    - -
    -
    - - - - -
    #define FSMC_PIO4_IOHIZ4_4   (0x10UL << FSMC_PIO4_IOHIZ4_Pos)
    -
    -

    0x10000000

    - -
    -
    - -

    ◆ FSMC_PIO4_IOHIZ4_5

    - -
    -
    - - - - -
    #define FSMC_PIO4_IOHIZ4_5   (0x20UL << FSMC_PIO4_IOHIZ4_Pos)
    -
    -

    0x20000000

    - -
    -
    - -

    ◆ FSMC_PIO4_IOHIZ4_6

    - -
    -
    - - - - -
    #define FSMC_PIO4_IOHIZ4_6   (0x40UL << FSMC_PIO4_IOHIZ4_Pos)
    -
    -

    0x40000000

    - -
    -
    - -

    ◆ FSMC_PIO4_IOHIZ4_7

    - -
    -
    - - - - -
    #define FSMC_PIO4_IOHIZ4_7   (0x80UL << FSMC_PIO4_IOHIZ4_Pos)
    -
    -

    0x80000000

    - -
    -
    - -

    ◆ FSMC_ECCR2_ECC2_Pos

    - -
    -
    - - - - -
    #define FSMC_ECCR2_ECC2_Pos   (0U)
    -
    - -
    -
    - -

    ◆ FSMC_ECCR2_ECC2_Msk

    - -
    -
    - - - - -
    #define FSMC_ECCR2_ECC2_Msk   (0xFFFFFFFFUL << FSMC_ECCR2_ECC2_Pos)
    -
    -

    0xFFFFFFFF

    - -
    -
    - -

    ◆ FSMC_ECCR2_ECC2

    - -
    -
    - - - - -
    #define FSMC_ECCR2_ECC2   FSMC_ECCR2_ECC2_Msk
    -
    -

    ECC result

    - -
    -
    - -

    ◆ FSMC_ECCR3_ECC3_Pos

    - -
    -
    - - - - -
    #define FSMC_ECCR3_ECC3_Pos   (0U)
    -
    - -
    -
    - -

    ◆ FSMC_ECCR3_ECC3_Msk

    - -
    -
    - - - - -
    #define FSMC_ECCR3_ECC3_Msk   (0xFFFFFFFFUL << FSMC_ECCR3_ECC3_Pos)
    -
    -

    0xFFFFFFFF

    - -
    -
    - -

    ◆ FSMC_ECCR3_ECC3

    - -
    -
    - - - - -
    #define FSMC_ECCR3_ECC3   FSMC_ECCR3_ECC3_Msk
    -
    -

    ECC result

    - -
    -
    - -

    ◆ GPIO_MODER_MODER0_Pos

    - -
    -
    - - - - -
    #define GPIO_MODER_MODER0_Pos   (0U)
    -
    - -
    -
    - -

    ◆ GPIO_MODER_MODER0_Msk

    - -
    -
    - - - - -
    #define GPIO_MODER_MODER0_Msk   (0x3UL << GPIO_MODER_MODER0_Pos)
    -
    -

    0x00000003

    - -
    -
    - -

    ◆ GPIO_MODER_MODER0

    - -
    -
    - - - - -
    #define GPIO_MODER_MODER0   GPIO_MODER_MODER0_Msk
    -
    - -
    -
    - -

    ◆ GPIO_MODER_MODER0_0

    - -
    -
    - - - - -
    #define GPIO_MODER_MODER0_0   (0x1UL << GPIO_MODER_MODER0_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ GPIO_MODER_MODER0_1

    - -
    -
    - - - - -
    #define GPIO_MODER_MODER0_1   (0x2UL << GPIO_MODER_MODER0_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ GPIO_MODER_MODER1_Pos

    - -
    -
    - - - - -
    #define GPIO_MODER_MODER1_Pos   (2U)
    -
    - -
    -
    - -

    ◆ GPIO_MODER_MODER1_Msk

    - -
    -
    - - - - -
    #define GPIO_MODER_MODER1_Msk   (0x3UL << GPIO_MODER_MODER1_Pos)
    -
    -

    0x0000000C

    - -
    -
    - -

    ◆ GPIO_MODER_MODER1

    - -
    -
    - - - - -
    #define GPIO_MODER_MODER1   GPIO_MODER_MODER1_Msk
    -
    - -
    -
    - -

    ◆ GPIO_MODER_MODER1_0

    - -
    -
    - - - - -
    #define GPIO_MODER_MODER1_0   (0x1UL << GPIO_MODER_MODER1_Pos)
    -
    -

    0x00000004

    - -
    -
    - -

    ◆ GPIO_MODER_MODER1_1

    - -
    -
    - - - - -
    #define GPIO_MODER_MODER1_1   (0x2UL << GPIO_MODER_MODER1_Pos)
    -
    -

    0x00000008

    - -
    -
    - -

    ◆ GPIO_MODER_MODER2_Pos

    - -
    -
    - - - - -
    #define GPIO_MODER_MODER2_Pos   (4U)
    -
    - -
    -
    - -

    ◆ GPIO_MODER_MODER2_Msk

    - -
    -
    - - - - -
    #define GPIO_MODER_MODER2_Msk   (0x3UL << GPIO_MODER_MODER2_Pos)
    -
    -

    0x00000030

    - -
    -
    - -

    ◆ GPIO_MODER_MODER2

    - -
    -
    - - - - -
    #define GPIO_MODER_MODER2   GPIO_MODER_MODER2_Msk
    -
    - -
    -
    - -

    ◆ GPIO_MODER_MODER2_0

    - -
    -
    - - - - -
    #define GPIO_MODER_MODER2_0   (0x1UL << GPIO_MODER_MODER2_Pos)
    -
    -

    0x00000010

    - -
    -
    - -

    ◆ GPIO_MODER_MODER2_1

    - -
    -
    - - - - -
    #define GPIO_MODER_MODER2_1   (0x2UL << GPIO_MODER_MODER2_Pos)
    -
    -

    0x00000020

    - -
    -
    - -

    ◆ GPIO_MODER_MODER3_Pos

    - -
    -
    - - - - -
    #define GPIO_MODER_MODER3_Pos   (6U)
    -
    - -
    -
    - -

    ◆ GPIO_MODER_MODER3_Msk

    - -
    -
    - - - - -
    #define GPIO_MODER_MODER3_Msk   (0x3UL << GPIO_MODER_MODER3_Pos)
    -
    -

    0x000000C0

    - -
    -
    - -

    ◆ GPIO_MODER_MODER3

    - -
    -
    - - - - -
    #define GPIO_MODER_MODER3   GPIO_MODER_MODER3_Msk
    -
    - -
    -
    - -

    ◆ GPIO_MODER_MODER3_0

    - -
    -
    - - - - -
    #define GPIO_MODER_MODER3_0   (0x1UL << GPIO_MODER_MODER3_Pos)
    -
    -

    0x00000040

    - -
    -
    - -

    ◆ GPIO_MODER_MODER3_1

    - -
    -
    - - - - -
    #define GPIO_MODER_MODER3_1   (0x2UL << GPIO_MODER_MODER3_Pos)
    -
    -

    0x00000080

    - -
    -
    - -

    ◆ GPIO_MODER_MODER4_Pos

    - -
    -
    - - - - -
    #define GPIO_MODER_MODER4_Pos   (8U)
    -
    - -
    -
    - -

    ◆ GPIO_MODER_MODER4_Msk

    - -
    -
    - - - - -
    #define GPIO_MODER_MODER4_Msk   (0x3UL << GPIO_MODER_MODER4_Pos)
    -
    -

    0x00000300

    - -
    -
    - -

    ◆ GPIO_MODER_MODER4

    - -
    -
    - - - - -
    #define GPIO_MODER_MODER4   GPIO_MODER_MODER4_Msk
    -
    - -
    -
    - -

    ◆ GPIO_MODER_MODER4_0

    - -
    -
    - - - - -
    #define GPIO_MODER_MODER4_0   (0x1UL << GPIO_MODER_MODER4_Pos)
    -
    -

    0x00000100

    - -
    -
    - -

    ◆ GPIO_MODER_MODER4_1

    - -
    -
    - - - - -
    #define GPIO_MODER_MODER4_1   (0x2UL << GPIO_MODER_MODER4_Pos)
    -
    -

    0x00000200

    - -
    -
    - -

    ◆ GPIO_MODER_MODER5_Pos

    - -
    -
    - - - - -
    #define GPIO_MODER_MODER5_Pos   (10U)
    -
    - -
    -
    - -

    ◆ GPIO_MODER_MODER5_Msk

    - -
    -
    - - - - -
    #define GPIO_MODER_MODER5_Msk   (0x3UL << GPIO_MODER_MODER5_Pos)
    -
    -

    0x00000C00

    - -
    -
    - -

    ◆ GPIO_MODER_MODER5

    - -
    -
    - - - - -
    #define GPIO_MODER_MODER5   GPIO_MODER_MODER5_Msk
    -
    - -
    -
    - -

    ◆ GPIO_MODER_MODER5_0

    - -
    -
    - - - - -
    #define GPIO_MODER_MODER5_0   (0x1UL << GPIO_MODER_MODER5_Pos)
    -
    -

    0x00000400

    - -
    -
    - -

    ◆ GPIO_MODER_MODER5_1

    - -
    -
    - - - - -
    #define GPIO_MODER_MODER5_1   (0x2UL << GPIO_MODER_MODER5_Pos)
    -
    -

    0x00000800

    - -
    -
    - -

    ◆ GPIO_MODER_MODER6_Pos

    - -
    -
    - - - - -
    #define GPIO_MODER_MODER6_Pos   (12U)
    -
    - -
    -
    - -

    ◆ GPIO_MODER_MODER6_Msk

    - -
    -
    - - - - -
    #define GPIO_MODER_MODER6_Msk   (0x3UL << GPIO_MODER_MODER6_Pos)
    -
    -

    0x00003000

    - -
    -
    - -

    ◆ GPIO_MODER_MODER6

    - -
    -
    - - - - -
    #define GPIO_MODER_MODER6   GPIO_MODER_MODER6_Msk
    -
    - -
    -
    - -

    ◆ GPIO_MODER_MODER6_0

    - -
    -
    - - - - -
    #define GPIO_MODER_MODER6_0   (0x1UL << GPIO_MODER_MODER6_Pos)
    -
    -

    0x00001000

    - -
    -
    - -

    ◆ GPIO_MODER_MODER6_1

    - -
    -
    - - - - -
    #define GPIO_MODER_MODER6_1   (0x2UL << GPIO_MODER_MODER6_Pos)
    -
    -

    0x00002000

    - -
    -
    - -

    ◆ GPIO_MODER_MODER7_Pos

    - -
    -
    - - - - -
    #define GPIO_MODER_MODER7_Pos   (14U)
    -
    - -
    -
    - -

    ◆ GPIO_MODER_MODER7_Msk

    - -
    -
    - - - - -
    #define GPIO_MODER_MODER7_Msk   (0x3UL << GPIO_MODER_MODER7_Pos)
    -
    -

    0x0000C000

    - -
    -
    - -

    ◆ GPIO_MODER_MODER7

    - -
    -
    - - - - -
    #define GPIO_MODER_MODER7   GPIO_MODER_MODER7_Msk
    -
    - -
    -
    - -

    ◆ GPIO_MODER_MODER7_0

    - -
    -
    - - - - -
    #define GPIO_MODER_MODER7_0   (0x1UL << GPIO_MODER_MODER7_Pos)
    -
    -

    0x00004000

    - -
    -
    - -

    ◆ GPIO_MODER_MODER7_1

    - -
    -
    - - - - -
    #define GPIO_MODER_MODER7_1   (0x2UL << GPIO_MODER_MODER7_Pos)
    -
    -

    0x00008000

    - -
    -
    - -

    ◆ GPIO_MODER_MODER8_Pos

    - -
    -
    - - - - -
    #define GPIO_MODER_MODER8_Pos   (16U)
    -
    - -
    -
    - -

    ◆ GPIO_MODER_MODER8_Msk

    - -
    -
    - - - - -
    #define GPIO_MODER_MODER8_Msk   (0x3UL << GPIO_MODER_MODER8_Pos)
    -
    -

    0x00030000

    - -
    -
    - -

    ◆ GPIO_MODER_MODER8

    - -
    -
    - - - - -
    #define GPIO_MODER_MODER8   GPIO_MODER_MODER8_Msk
    -
    - -
    -
    - -

    ◆ GPIO_MODER_MODER8_0

    - -
    -
    - - - - -
    #define GPIO_MODER_MODER8_0   (0x1UL << GPIO_MODER_MODER8_Pos)
    -
    -

    0x00010000

    - -
    -
    - -

    ◆ GPIO_MODER_MODER8_1

    - -
    -
    - - - - -
    #define GPIO_MODER_MODER8_1   (0x2UL << GPIO_MODER_MODER8_Pos)
    -
    -

    0x00020000

    - -
    -
    - -

    ◆ GPIO_MODER_MODER9_Pos

    - -
    -
    - - - - -
    #define GPIO_MODER_MODER9_Pos   (18U)
    -
    - -
    -
    - -

    ◆ GPIO_MODER_MODER9_Msk

    - -
    -
    - - - - -
    #define GPIO_MODER_MODER9_Msk   (0x3UL << GPIO_MODER_MODER9_Pos)
    -
    -

    0x000C0000

    - -
    -
    - -

    ◆ GPIO_MODER_MODER9

    - -
    -
    - - - - -
    #define GPIO_MODER_MODER9   GPIO_MODER_MODER9_Msk
    -
    - -
    -
    - -

    ◆ GPIO_MODER_MODER9_0

    - -
    -
    - - - - -
    #define GPIO_MODER_MODER9_0   (0x1UL << GPIO_MODER_MODER9_Pos)
    -
    -

    0x00040000

    - -
    -
    - -

    ◆ GPIO_MODER_MODER9_1

    - -
    -
    - - - - -
    #define GPIO_MODER_MODER9_1   (0x2UL << GPIO_MODER_MODER9_Pos)
    -
    -

    0x00080000

    - -
    -
    - -

    ◆ GPIO_MODER_MODER10_Pos

    - -
    -
    - - - - -
    #define GPIO_MODER_MODER10_Pos   (20U)
    -
    - -
    -
    - -

    ◆ GPIO_MODER_MODER10_Msk

    - -
    -
    - - - - -
    #define GPIO_MODER_MODER10_Msk   (0x3UL << GPIO_MODER_MODER10_Pos)
    -
    -

    0x00300000

    - -
    -
    - -

    ◆ GPIO_MODER_MODER10

    - -
    -
    - - - - -
    #define GPIO_MODER_MODER10   GPIO_MODER_MODER10_Msk
    -
    - -
    -
    - -

    ◆ GPIO_MODER_MODER10_0

    - -
    -
    - - - - -
    #define GPIO_MODER_MODER10_0   (0x1UL << GPIO_MODER_MODER10_Pos)
    -
    -

    0x00100000

    - -
    -
    - -

    ◆ GPIO_MODER_MODER10_1

    - -
    -
    - - - - -
    #define GPIO_MODER_MODER10_1   (0x2UL << GPIO_MODER_MODER10_Pos)
    -
    -

    0x00200000

    - -
    -
    - -

    ◆ GPIO_MODER_MODER11_Pos

    - -
    -
    - - - - -
    #define GPIO_MODER_MODER11_Pos   (22U)
    -
    - -
    -
    - -

    ◆ GPIO_MODER_MODER11_Msk

    - -
    -
    - - - - -
    #define GPIO_MODER_MODER11_Msk   (0x3UL << GPIO_MODER_MODER11_Pos)
    -
    -

    0x00C00000

    - -
    -
    - -

    ◆ GPIO_MODER_MODER11

    - -
    -
    - - - - -
    #define GPIO_MODER_MODER11   GPIO_MODER_MODER11_Msk
    -
    - -
    -
    - -

    ◆ GPIO_MODER_MODER11_0

    - -
    -
    - - - - -
    #define GPIO_MODER_MODER11_0   (0x1UL << GPIO_MODER_MODER11_Pos)
    -
    -

    0x00400000

    - -
    -
    - -

    ◆ GPIO_MODER_MODER11_1

    - -
    -
    - - - - -
    #define GPIO_MODER_MODER11_1   (0x2UL << GPIO_MODER_MODER11_Pos)
    -
    -

    0x00800000

    - -
    -
    - -

    ◆ GPIO_MODER_MODER12_Pos

    - -
    -
    - - - - -
    #define GPIO_MODER_MODER12_Pos   (24U)
    -
    - -
    -
    - -

    ◆ GPIO_MODER_MODER12_Msk

    - -
    -
    - - - - -
    #define GPIO_MODER_MODER12_Msk   (0x3UL << GPIO_MODER_MODER12_Pos)
    -
    -

    0x03000000

    - -
    -
    - -

    ◆ GPIO_MODER_MODER12

    - -
    -
    - - - - -
    #define GPIO_MODER_MODER12   GPIO_MODER_MODER12_Msk
    -
    - -
    -
    - -

    ◆ GPIO_MODER_MODER12_0

    - -
    -
    - - - - -
    #define GPIO_MODER_MODER12_0   (0x1UL << GPIO_MODER_MODER12_Pos)
    -
    -

    0x01000000

    - -
    -
    - -

    ◆ GPIO_MODER_MODER12_1

    - -
    -
    - - - - -
    #define GPIO_MODER_MODER12_1   (0x2UL << GPIO_MODER_MODER12_Pos)
    -
    -

    0x02000000

    - -
    -
    - -

    ◆ GPIO_MODER_MODER13_Pos

    - -
    -
    - - - - -
    #define GPIO_MODER_MODER13_Pos   (26U)
    -
    - -
    -
    - -

    ◆ GPIO_MODER_MODER13_Msk

    - -
    -
    - - - - -
    #define GPIO_MODER_MODER13_Msk   (0x3UL << GPIO_MODER_MODER13_Pos)
    -
    -

    0x0C000000

    - -
    -
    - -

    ◆ GPIO_MODER_MODER13

    - -
    -
    - - - - -
    #define GPIO_MODER_MODER13   GPIO_MODER_MODER13_Msk
    -
    - -
    -
    - -

    ◆ GPIO_MODER_MODER13_0

    - -
    -
    - - - - -
    #define GPIO_MODER_MODER13_0   (0x1UL << GPIO_MODER_MODER13_Pos)
    -
    -

    0x04000000

    - -
    -
    - -

    ◆ GPIO_MODER_MODER13_1

    - -
    -
    - - - - -
    #define GPIO_MODER_MODER13_1   (0x2UL << GPIO_MODER_MODER13_Pos)
    -
    -

    0x08000000

    - -
    -
    - -

    ◆ GPIO_MODER_MODER14_Pos

    - -
    -
    - - - - -
    #define GPIO_MODER_MODER14_Pos   (28U)
    -
    - -
    -
    - -

    ◆ GPIO_MODER_MODER14_Msk

    - -
    -
    - - - - -
    #define GPIO_MODER_MODER14_Msk   (0x3UL << GPIO_MODER_MODER14_Pos)
    -
    -

    0x30000000

    - -
    -
    - -

    ◆ GPIO_MODER_MODER14

    - -
    -
    - - - - -
    #define GPIO_MODER_MODER14   GPIO_MODER_MODER14_Msk
    -
    - -
    -
    - -

    ◆ GPIO_MODER_MODER14_0

    - -
    -
    - - - - -
    #define GPIO_MODER_MODER14_0   (0x1UL << GPIO_MODER_MODER14_Pos)
    -
    -

    0x10000000

    - -
    -
    - -

    ◆ GPIO_MODER_MODER14_1

    - -
    -
    - - - - -
    #define GPIO_MODER_MODER14_1   (0x2UL << GPIO_MODER_MODER14_Pos)
    -
    -

    0x20000000

    - -
    -
    - -

    ◆ GPIO_MODER_MODER15_Pos

    - -
    -
    - - - - -
    #define GPIO_MODER_MODER15_Pos   (30U)
    -
    - -
    -
    - -

    ◆ GPIO_MODER_MODER15_Msk

    - -
    -
    - - - - -
    #define GPIO_MODER_MODER15_Msk   (0x3UL << GPIO_MODER_MODER15_Pos)
    -
    -

    0xC0000000

    - -
    -
    - -

    ◆ GPIO_MODER_MODER15

    - -
    -
    - - - - -
    #define GPIO_MODER_MODER15   GPIO_MODER_MODER15_Msk
    -
    - -
    -
    - -

    ◆ GPIO_MODER_MODER15_0

    - -
    -
    - - - - -
    #define GPIO_MODER_MODER15_0   (0x1UL << GPIO_MODER_MODER15_Pos)
    -
    -

    0x40000000

    - -
    -
    - -

    ◆ GPIO_MODER_MODER15_1

    - -
    -
    - - - - -
    #define GPIO_MODER_MODER15_1   (0x2UL << GPIO_MODER_MODER15_Pos)
    -
    -

    0x80000000

    - -
    -
    - -

    ◆ GPIO_MODER_MODE0_Pos

    - -
    -
    - - - - -
    #define GPIO_MODER_MODE0_Pos   GPIO_MODER_MODER0_Pos
    -
    - -
    -
    - -

    ◆ GPIO_MODER_MODE0_Msk

    - -
    -
    - - - - -
    #define GPIO_MODER_MODE0_Msk   GPIO_MODER_MODER0_Msk
    -
    - -
    -
    - -

    ◆ GPIO_MODER_MODE0

    - -
    -
    - - - - -
    #define GPIO_MODER_MODE0   GPIO_MODER_MODER0
    -
    - -
    -
    - -

    ◆ GPIO_MODER_MODE0_0

    - -
    -
    - - - - -
    #define GPIO_MODER_MODE0_0   GPIO_MODER_MODER0_0
    -
    - -
    -
    - -

    ◆ GPIO_MODER_MODE0_1

    - -
    -
    - - - - -
    #define GPIO_MODER_MODE0_1   GPIO_MODER_MODER0_1
    -
    - -
    -
    - -

    ◆ GPIO_MODER_MODE1_Pos

    - -
    -
    - - - - -
    #define GPIO_MODER_MODE1_Pos   GPIO_MODER_MODER1_Pos
    -
    - -
    -
    - -

    ◆ GPIO_MODER_MODE1_Msk

    - -
    -
    - - - - -
    #define GPIO_MODER_MODE1_Msk   GPIO_MODER_MODER1_Msk
    -
    - -
    -
    - -

    ◆ GPIO_MODER_MODE1

    - -
    -
    - - - - -
    #define GPIO_MODER_MODE1   GPIO_MODER_MODER1
    -
    - -
    -
    - -

    ◆ GPIO_MODER_MODE1_0

    - -
    -
    - - - - -
    #define GPIO_MODER_MODE1_0   GPIO_MODER_MODER1_0
    -
    - -
    -
    - -

    ◆ GPIO_MODER_MODE1_1

    - -
    -
    - - - - -
    #define GPIO_MODER_MODE1_1   GPIO_MODER_MODER1_1
    -
    - -
    -
    - -

    ◆ GPIO_MODER_MODE2_Pos

    - -
    -
    - - - - -
    #define GPIO_MODER_MODE2_Pos   GPIO_MODER_MODER2_Pos
    -
    - -
    -
    - -

    ◆ GPIO_MODER_MODE2_Msk

    - -
    -
    - - - - -
    #define GPIO_MODER_MODE2_Msk   GPIO_MODER_MODER2_Msk
    -
    - -
    -
    - -

    ◆ GPIO_MODER_MODE2

    - -
    -
    - - - - -
    #define GPIO_MODER_MODE2   GPIO_MODER_MODER2
    -
    - -
    -
    - -

    ◆ GPIO_MODER_MODE2_0

    - -
    -
    - - - - -
    #define GPIO_MODER_MODE2_0   GPIO_MODER_MODER2_0
    -
    - -
    -
    - -

    ◆ GPIO_MODER_MODE2_1

    - -
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    #define GPIO_MODER_MODE2_1   GPIO_MODER_MODER2_1
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    ◆ GPIO_MODER_MODE3_Pos

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    #define GPIO_MODER_MODE3_Pos   GPIO_MODER_MODER3_Pos
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    ◆ GPIO_MODER_MODE3_Msk

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    #define GPIO_MODER_MODE3_Msk   GPIO_MODER_MODER3_Msk
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    ◆ GPIO_MODER_MODE3

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    #define GPIO_MODER_MODE3   GPIO_MODER_MODER3
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    ◆ GPIO_MODER_MODE3_0

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    #define GPIO_MODER_MODE3_0   GPIO_MODER_MODER3_0
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    ◆ GPIO_MODER_MODE3_1

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    #define GPIO_MODER_MODE3_1   GPIO_MODER_MODER3_1
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    ◆ GPIO_MODER_MODE4_Pos

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    #define GPIO_MODER_MODE4_Pos   GPIO_MODER_MODER4_Pos
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    ◆ GPIO_MODER_MODE4_Msk

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    #define GPIO_MODER_MODE4_Msk   GPIO_MODER_MODER4_Msk
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    ◆ GPIO_MODER_MODE4

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    #define GPIO_MODER_MODE4   GPIO_MODER_MODER4
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    ◆ GPIO_MODER_MODE4_0

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    #define GPIO_MODER_MODE4_0   GPIO_MODER_MODER4_0
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    ◆ GPIO_MODER_MODE4_1

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    #define GPIO_MODER_MODE4_1   GPIO_MODER_MODER4_1
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    ◆ GPIO_MODER_MODE5_Pos

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    #define GPIO_MODER_MODE5_Pos   GPIO_MODER_MODER5_Pos
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    ◆ GPIO_MODER_MODE5_Msk

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    #define GPIO_MODER_MODE5_Msk   GPIO_MODER_MODER5_Msk
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    ◆ GPIO_MODER_MODE5

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    #define GPIO_MODER_MODE5   GPIO_MODER_MODER5
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    ◆ GPIO_MODER_MODE5_0

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    #define GPIO_MODER_MODE5_0   GPIO_MODER_MODER5_0
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    ◆ GPIO_MODER_MODE5_1

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    #define GPIO_MODER_MODE5_1   GPIO_MODER_MODER5_1
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    ◆ GPIO_MODER_MODE6_Pos

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    #define GPIO_MODER_MODE6_Pos   GPIO_MODER_MODER6_Pos
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    ◆ GPIO_MODER_MODE6_Msk

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    #define GPIO_MODER_MODE6_Msk   GPIO_MODER_MODER6_Msk
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    ◆ GPIO_MODER_MODE6

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    #define GPIO_MODER_MODE6   GPIO_MODER_MODER6
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    ◆ GPIO_MODER_MODE6_0

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    #define GPIO_MODER_MODE6_0   GPIO_MODER_MODER6_0
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    ◆ GPIO_MODER_MODE6_1

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    #define GPIO_MODER_MODE6_1   GPIO_MODER_MODER6_1
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    ◆ GPIO_MODER_MODE7_Pos

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    #define GPIO_MODER_MODE7_Pos   GPIO_MODER_MODER7_Pos
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    ◆ GPIO_MODER_MODE7_Msk

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    #define GPIO_MODER_MODE7_Msk   GPIO_MODER_MODER7_Msk
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    ◆ GPIO_MODER_MODE7

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    #define GPIO_MODER_MODE7   GPIO_MODER_MODER7
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    ◆ GPIO_MODER_MODE7_0

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    #define GPIO_MODER_MODE7_0   GPIO_MODER_MODER7_0
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    ◆ GPIO_MODER_MODE7_1

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    #define GPIO_MODER_MODE7_1   GPIO_MODER_MODER7_1
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    ◆ GPIO_MODER_MODE8_Pos

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    #define GPIO_MODER_MODE8_Pos   GPIO_MODER_MODER8_Pos
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    ◆ GPIO_MODER_MODE8_Msk

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    #define GPIO_MODER_MODE8_Msk   GPIO_MODER_MODER8_Msk
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    ◆ GPIO_MODER_MODE8

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    #define GPIO_MODER_MODE8   GPIO_MODER_MODER8
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    ◆ GPIO_MODER_MODE8_0

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    #define GPIO_MODER_MODE8_0   GPIO_MODER_MODER8_0
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    ◆ GPIO_MODER_MODE8_1

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    #define GPIO_MODER_MODE8_1   GPIO_MODER_MODER8_1
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    ◆ GPIO_MODER_MODE9_Pos

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    #define GPIO_MODER_MODE9_Pos   GPIO_MODER_MODER9_Pos
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    ◆ GPIO_MODER_MODE9_Msk

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    #define GPIO_MODER_MODE9_Msk   GPIO_MODER_MODER9_Msk
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    ◆ GPIO_MODER_MODE9

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    #define GPIO_MODER_MODE9   GPIO_MODER_MODER9
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    ◆ GPIO_MODER_MODE9_0

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    #define GPIO_MODER_MODE9_0   GPIO_MODER_MODER9_0
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    ◆ GPIO_MODER_MODE9_1

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    #define GPIO_MODER_MODE9_1   GPIO_MODER_MODER9_1
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    ◆ GPIO_MODER_MODE10_Pos

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    #define GPIO_MODER_MODE10_Pos   GPIO_MODER_MODER10_Pos
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    ◆ GPIO_MODER_MODE10_Msk

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    #define GPIO_MODER_MODE10_Msk   GPIO_MODER_MODER10_Msk
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    ◆ GPIO_MODER_MODE10

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    #define GPIO_MODER_MODE10   GPIO_MODER_MODER10
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    ◆ GPIO_MODER_MODE10_0

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    #define GPIO_MODER_MODE10_0   GPIO_MODER_MODER10_0
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    ◆ GPIO_MODER_MODE10_1

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    #define GPIO_MODER_MODE10_1   GPIO_MODER_MODER10_1
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    ◆ GPIO_MODER_MODE11_Pos

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    #define GPIO_MODER_MODE11_Pos   GPIO_MODER_MODER11_Pos
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    ◆ GPIO_MODER_MODE11_Msk

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    #define GPIO_MODER_MODE11_Msk   GPIO_MODER_MODER11_Msk
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    - -
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    - -

    ◆ GPIO_MODER_MODE11

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    #define GPIO_MODER_MODE11   GPIO_MODER_MODER11
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    ◆ GPIO_MODER_MODE11_0

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    #define GPIO_MODER_MODE11_0   GPIO_MODER_MODER11_0
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    ◆ GPIO_MODER_MODE11_1

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    #define GPIO_MODER_MODE11_1   GPIO_MODER_MODER11_1
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    ◆ GPIO_MODER_MODE12_Pos

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    #define GPIO_MODER_MODE12_Pos   GPIO_MODER_MODER12_Pos
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    ◆ GPIO_MODER_MODE12_Msk

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    #define GPIO_MODER_MODE12_Msk   GPIO_MODER_MODER12_Msk
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    - -
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    ◆ GPIO_MODER_MODE12

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    #define GPIO_MODER_MODE12   GPIO_MODER_MODER12
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    ◆ GPIO_MODER_MODE12_0

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    #define GPIO_MODER_MODE12_0   GPIO_MODER_MODER12_0
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    ◆ GPIO_MODER_MODE12_1

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    #define GPIO_MODER_MODE12_1   GPIO_MODER_MODER12_1
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    ◆ GPIO_MODER_MODE13_Pos

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    #define GPIO_MODER_MODE13_Pos   GPIO_MODER_MODER13_Pos
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    ◆ GPIO_MODER_MODE13_Msk

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    #define GPIO_MODER_MODE13_Msk   GPIO_MODER_MODER13_Msk
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    ◆ GPIO_MODER_MODE13

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    #define GPIO_MODER_MODE13   GPIO_MODER_MODER13
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    ◆ GPIO_MODER_MODE13_0

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    #define GPIO_MODER_MODE13_0   GPIO_MODER_MODER13_0
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    ◆ GPIO_MODER_MODE13_1

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    #define GPIO_MODER_MODE13_1   GPIO_MODER_MODER13_1
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    ◆ GPIO_MODER_MODE14_Pos

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    #define GPIO_MODER_MODE14_Pos   GPIO_MODER_MODER14_Pos
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    ◆ GPIO_MODER_MODE14_Msk

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    #define GPIO_MODER_MODE14_Msk   GPIO_MODER_MODER14_Msk
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    ◆ GPIO_MODER_MODE14

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    #define GPIO_MODER_MODE14   GPIO_MODER_MODER14
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    ◆ GPIO_MODER_MODE14_0

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    #define GPIO_MODER_MODE14_0   GPIO_MODER_MODER14_0
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    ◆ GPIO_MODER_MODE14_1

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    #define GPIO_MODER_MODE14_1   GPIO_MODER_MODER14_1
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    ◆ GPIO_MODER_MODE15_Pos

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    #define GPIO_MODER_MODE15_Pos   GPIO_MODER_MODER15_Pos
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    ◆ GPIO_MODER_MODE15_Msk

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    #define GPIO_MODER_MODE15_Msk   GPIO_MODER_MODER15_Msk
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    ◆ GPIO_MODER_MODE15

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    #define GPIO_MODER_MODE15   GPIO_MODER_MODER15
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    ◆ GPIO_MODER_MODE15_0

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    #define GPIO_MODER_MODE15_0   GPIO_MODER_MODER15_0
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    ◆ GPIO_MODER_MODE15_1

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    #define GPIO_MODER_MODE15_1   GPIO_MODER_MODER15_1
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    ◆ GPIO_OTYPER_OT0_Pos

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    #define GPIO_OTYPER_OT0_Pos   (0U)
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    ◆ GPIO_OTYPER_OT0_Msk

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    #define GPIO_OTYPER_OT0_Msk   (0x1UL << GPIO_OTYPER_OT0_Pos)
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    -

    0x00000001

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    ◆ GPIO_OTYPER_OT0

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    #define GPIO_OTYPER_OT0   GPIO_OTYPER_OT0_Msk
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    ◆ GPIO_OTYPER_OT1_Pos

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    #define GPIO_OTYPER_OT1_Pos   (1U)
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    ◆ GPIO_OTYPER_OT1_Msk

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    #define GPIO_OTYPER_OT1_Msk   (0x1UL << GPIO_OTYPER_OT1_Pos)
    -
    -

    0x00000002

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    ◆ GPIO_OTYPER_OT1

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    #define GPIO_OTYPER_OT1   GPIO_OTYPER_OT1_Msk
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    ◆ GPIO_OTYPER_OT2_Pos

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    #define GPIO_OTYPER_OT2_Pos   (2U)
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    ◆ GPIO_OTYPER_OT2_Msk

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    #define GPIO_OTYPER_OT2_Msk   (0x1UL << GPIO_OTYPER_OT2_Pos)
    -
    -

    0x00000004

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    -
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    ◆ GPIO_OTYPER_OT2

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    #define GPIO_OTYPER_OT2   GPIO_OTYPER_OT2_Msk
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    ◆ GPIO_OTYPER_OT3_Pos

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    #define GPIO_OTYPER_OT3_Pos   (3U)
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    ◆ GPIO_OTYPER_OT3_Msk

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    #define GPIO_OTYPER_OT3_Msk   (0x1UL << GPIO_OTYPER_OT3_Pos)
    -
    -

    0x00000008

    - -
    -
    - -

    ◆ GPIO_OTYPER_OT3

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    #define GPIO_OTYPER_OT3   GPIO_OTYPER_OT3_Msk
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    ◆ GPIO_OTYPER_OT4_Pos

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    #define GPIO_OTYPER_OT4_Pos   (4U)
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    ◆ GPIO_OTYPER_OT4_Msk

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    #define GPIO_OTYPER_OT4_Msk   (0x1UL << GPIO_OTYPER_OT4_Pos)
    -
    -

    0x00000010

    - -
    -
    - -

    ◆ GPIO_OTYPER_OT4

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    #define GPIO_OTYPER_OT4   GPIO_OTYPER_OT4_Msk
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    ◆ GPIO_OTYPER_OT5_Pos

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    #define GPIO_OTYPER_OT5_Pos   (5U)
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    ◆ GPIO_OTYPER_OT5_Msk

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    #define GPIO_OTYPER_OT5_Msk   (0x1UL << GPIO_OTYPER_OT5_Pos)
    -
    -

    0x00000020

    - -
    -
    - -

    ◆ GPIO_OTYPER_OT5

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    #define GPIO_OTYPER_OT5   GPIO_OTYPER_OT5_Msk
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    ◆ GPIO_OTYPER_OT6_Pos

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    #define GPIO_OTYPER_OT6_Pos   (6U)
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    - -
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    ◆ GPIO_OTYPER_OT6_Msk

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    #define GPIO_OTYPER_OT6_Msk   (0x1UL << GPIO_OTYPER_OT6_Pos)
    -
    -

    0x00000040

    - -
    -
    - -

    ◆ GPIO_OTYPER_OT6

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    #define GPIO_OTYPER_OT6   GPIO_OTYPER_OT6_Msk
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    ◆ GPIO_OTYPER_OT7_Pos

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    #define GPIO_OTYPER_OT7_Pos   (7U)
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    ◆ GPIO_OTYPER_OT7_Msk

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    #define GPIO_OTYPER_OT7_Msk   (0x1UL << GPIO_OTYPER_OT7_Pos)
    -
    -

    0x00000080

    - -
    -
    - -

    ◆ GPIO_OTYPER_OT7

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    #define GPIO_OTYPER_OT7   GPIO_OTYPER_OT7_Msk
    -
    - -
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    ◆ GPIO_OTYPER_OT8_Pos

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    #define GPIO_OTYPER_OT8_Pos   (8U)
    -
    - -
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    ◆ GPIO_OTYPER_OT8_Msk

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    #define GPIO_OTYPER_OT8_Msk   (0x1UL << GPIO_OTYPER_OT8_Pos)
    -
    -

    0x00000100

    - -
    -
    - -

    ◆ GPIO_OTYPER_OT8

    - -
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    #define GPIO_OTYPER_OT8   GPIO_OTYPER_OT8_Msk
    -
    - -
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    ◆ GPIO_OTYPER_OT9_Pos

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    #define GPIO_OTYPER_OT9_Pos   (9U)
    -
    - -
    -
    - -

    ◆ GPIO_OTYPER_OT9_Msk

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    #define GPIO_OTYPER_OT9_Msk   (0x1UL << GPIO_OTYPER_OT9_Pos)
    -
    -

    0x00000200

    - -
    -
    - -

    ◆ GPIO_OTYPER_OT9

    - -
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    #define GPIO_OTYPER_OT9   GPIO_OTYPER_OT9_Msk
    -
    - -
    -
    - -

    ◆ GPIO_OTYPER_OT10_Pos

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    -
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    #define GPIO_OTYPER_OT10_Pos   (10U)
    -
    - -
    -
    - -

    ◆ GPIO_OTYPER_OT10_Msk

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    #define GPIO_OTYPER_OT10_Msk   (0x1UL << GPIO_OTYPER_OT10_Pos)
    -
    -

    0x00000400

    - -
    -
    - -

    ◆ GPIO_OTYPER_OT10

    - -
    -
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    #define GPIO_OTYPER_OT10   GPIO_OTYPER_OT10_Msk
    -
    - -
    -
    - -

    ◆ GPIO_OTYPER_OT11_Pos

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    -
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    #define GPIO_OTYPER_OT11_Pos   (11U)
    -
    - -
    -
    - -

    ◆ GPIO_OTYPER_OT11_Msk

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    #define GPIO_OTYPER_OT11_Msk   (0x1UL << GPIO_OTYPER_OT11_Pos)
    -
    -

    0x00000800

    - -
    -
    - -

    ◆ GPIO_OTYPER_OT11

    - -
    -
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    #define GPIO_OTYPER_OT11   GPIO_OTYPER_OT11_Msk
    -
    - -
    -
    - -

    ◆ GPIO_OTYPER_OT12_Pos

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    -
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    #define GPIO_OTYPER_OT12_Pos   (12U)
    -
    - -
    -
    - -

    ◆ GPIO_OTYPER_OT12_Msk

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    #define GPIO_OTYPER_OT12_Msk   (0x1UL << GPIO_OTYPER_OT12_Pos)
    -
    -

    0x00001000

    - -
    -
    - -

    ◆ GPIO_OTYPER_OT12

    - -
    -
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    #define GPIO_OTYPER_OT12   GPIO_OTYPER_OT12_Msk
    -
    - -
    -
    - -

    ◆ GPIO_OTYPER_OT13_Pos

    - -
    -
    - - - - -
    #define GPIO_OTYPER_OT13_Pos   (13U)
    -
    - -
    -
    - -

    ◆ GPIO_OTYPER_OT13_Msk

    - -
    -
    - - - - -
    #define GPIO_OTYPER_OT13_Msk   (0x1UL << GPIO_OTYPER_OT13_Pos)
    -
    -

    0x00002000

    - -
    -
    - -

    ◆ GPIO_OTYPER_OT13

    - -
    -
    - - - - -
    #define GPIO_OTYPER_OT13   GPIO_OTYPER_OT13_Msk
    -
    - -
    -
    - -

    ◆ GPIO_OTYPER_OT14_Pos

    - -
    -
    - - - - -
    #define GPIO_OTYPER_OT14_Pos   (14U)
    -
    - -
    -
    - -

    ◆ GPIO_OTYPER_OT14_Msk

    - -
    -
    - - - - -
    #define GPIO_OTYPER_OT14_Msk   (0x1UL << GPIO_OTYPER_OT14_Pos)
    -
    -

    0x00004000

    - -
    -
    - -

    ◆ GPIO_OTYPER_OT14

    - -
    -
    - - - - -
    #define GPIO_OTYPER_OT14   GPIO_OTYPER_OT14_Msk
    -
    - -
    -
    - -

    ◆ GPIO_OTYPER_OT15_Pos

    - -
    -
    - - - - -
    #define GPIO_OTYPER_OT15_Pos   (15U)
    -
    - -
    -
    - -

    ◆ GPIO_OTYPER_OT15_Msk

    - -
    -
    - - - - -
    #define GPIO_OTYPER_OT15_Msk   (0x1UL << GPIO_OTYPER_OT15_Pos)
    -
    -

    0x00008000

    - -
    -
    - -

    ◆ GPIO_OTYPER_OT15

    - -
    -
    - - - - -
    #define GPIO_OTYPER_OT15   GPIO_OTYPER_OT15_Msk
    -
    - -
    -
    - -

    ◆ GPIO_OTYPER_OT_0

    - -
    -
    - - - - -
    #define GPIO_OTYPER_OT_0   GPIO_OTYPER_OT0
    -
    - -
    -
    - -

    ◆ GPIO_OTYPER_OT_1

    - -
    -
    - - - - -
    #define GPIO_OTYPER_OT_1   GPIO_OTYPER_OT1
    -
    - -
    -
    - -

    ◆ GPIO_OTYPER_OT_2

    - -
    -
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    #define GPIO_OTYPER_OT_2   GPIO_OTYPER_OT2
    -
    - -
    -
    - -

    ◆ GPIO_OTYPER_OT_3

    - -
    -
    - - - - -
    #define GPIO_OTYPER_OT_3   GPIO_OTYPER_OT3
    -
    - -
    -
    - -

    ◆ GPIO_OTYPER_OT_4

    - -
    -
    - - - - -
    #define GPIO_OTYPER_OT_4   GPIO_OTYPER_OT4
    -
    - -
    -
    - -

    ◆ GPIO_OTYPER_OT_5

    - -
    -
    - - - - -
    #define GPIO_OTYPER_OT_5   GPIO_OTYPER_OT5
    -
    - -
    -
    - -

    ◆ GPIO_OTYPER_OT_6

    - -
    -
    - - - - -
    #define GPIO_OTYPER_OT_6   GPIO_OTYPER_OT6
    -
    - -
    -
    - -

    ◆ GPIO_OTYPER_OT_7

    - -
    -
    - - - - -
    #define GPIO_OTYPER_OT_7   GPIO_OTYPER_OT7
    -
    - -
    -
    - -

    ◆ GPIO_OTYPER_OT_8

    - -
    -
    - - - - -
    #define GPIO_OTYPER_OT_8   GPIO_OTYPER_OT8
    -
    - -
    -
    - -

    ◆ GPIO_OTYPER_OT_9

    - -
    -
    - - - - -
    #define GPIO_OTYPER_OT_9   GPIO_OTYPER_OT9
    -
    - -
    -
    - -

    ◆ GPIO_OTYPER_OT_10

    - -
    -
    - - - - -
    #define GPIO_OTYPER_OT_10   GPIO_OTYPER_OT10
    -
    - -
    -
    - -

    ◆ GPIO_OTYPER_OT_11

    - -
    -
    - - - - -
    #define GPIO_OTYPER_OT_11   GPIO_OTYPER_OT11
    -
    - -
    -
    - -

    ◆ GPIO_OTYPER_OT_12

    - -
    -
    - - - - -
    #define GPIO_OTYPER_OT_12   GPIO_OTYPER_OT12
    -
    - -
    -
    - -

    ◆ GPIO_OTYPER_OT_13

    - -
    -
    - - - - -
    #define GPIO_OTYPER_OT_13   GPIO_OTYPER_OT13
    -
    - -
    -
    - -

    ◆ GPIO_OTYPER_OT_14

    - -
    -
    - - - - -
    #define GPIO_OTYPER_OT_14   GPIO_OTYPER_OT14
    -
    - -
    -
    - -

    ◆ GPIO_OTYPER_OT_15

    - -
    -
    - - - - -
    #define GPIO_OTYPER_OT_15   GPIO_OTYPER_OT15
    -
    - -
    -
    - -

    ◆ GPIO_OSPEEDR_OSPEED0_Pos

    - -
    -
    - - - - -
    #define GPIO_OSPEEDR_OSPEED0_Pos   (0U)
    -
    - -
    -
    - -

    ◆ GPIO_OSPEEDR_OSPEED0_Msk

    - -
    -
    - - - - -
    #define GPIO_OSPEEDR_OSPEED0_Msk   (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos)
    -
    -

    0x00000003

    - -
    -
    - -

    ◆ GPIO_OSPEEDR_OSPEED0

    - -
    -
    - - - - -
    #define GPIO_OSPEEDR_OSPEED0   GPIO_OSPEEDR_OSPEED0_Msk
    -
    - -
    -
    - -

    ◆ GPIO_OSPEEDR_OSPEED0_0

    - -
    -
    - - - - -
    #define GPIO_OSPEEDR_OSPEED0_0   (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ GPIO_OSPEEDR_OSPEED0_1

    - -
    -
    - - - - -
    #define GPIO_OSPEEDR_OSPEED0_1   (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ GPIO_OSPEEDR_OSPEED1_Pos

    - -
    -
    - - - - -
    #define GPIO_OSPEEDR_OSPEED1_Pos   (2U)
    -
    - -
    -
    - -

    ◆ GPIO_OSPEEDR_OSPEED1_Msk

    - -
    -
    - - - - -
    #define GPIO_OSPEEDR_OSPEED1_Msk   (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos)
    -
    -

    0x0000000C

    - -
    -
    - -

    ◆ GPIO_OSPEEDR_OSPEED1

    - -
    -
    - - - - -
    #define GPIO_OSPEEDR_OSPEED1   GPIO_OSPEEDR_OSPEED1_Msk
    -
    - -
    -
    - -

    ◆ GPIO_OSPEEDR_OSPEED1_0

    - -
    -
    - - - - -
    #define GPIO_OSPEEDR_OSPEED1_0   (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos)
    -
    -

    0x00000004

    - -
    -
    - -

    ◆ GPIO_OSPEEDR_OSPEED1_1

    - -
    -
    - - - - -
    #define GPIO_OSPEEDR_OSPEED1_1   (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos)
    -
    -

    0x00000008

    - -
    -
    - -

    ◆ GPIO_OSPEEDR_OSPEED2_Pos

    - -
    -
    - - - - -
    #define GPIO_OSPEEDR_OSPEED2_Pos   (4U)
    -
    - -
    -
    - -

    ◆ GPIO_OSPEEDR_OSPEED2_Msk

    - -
    -
    - - - - -
    #define GPIO_OSPEEDR_OSPEED2_Msk   (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos)
    -
    -

    0x00000030

    - -
    -
    - -

    ◆ GPIO_OSPEEDR_OSPEED2

    - -
    -
    - - - - -
    #define GPIO_OSPEEDR_OSPEED2   GPIO_OSPEEDR_OSPEED2_Msk
    -
    - -
    -
    - -

    ◆ GPIO_OSPEEDR_OSPEED2_0

    - -
    -
    - - - - -
    #define GPIO_OSPEEDR_OSPEED2_0   (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos)
    -
    -

    0x00000010

    - -
    -
    - -

    ◆ GPIO_OSPEEDR_OSPEED2_1

    - -
    -
    - - - - -
    #define GPIO_OSPEEDR_OSPEED2_1   (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos)
    -
    -

    0x00000020

    - -
    -
    - -

    ◆ GPIO_OSPEEDR_OSPEED3_Pos

    - -
    -
    - - - - -
    #define GPIO_OSPEEDR_OSPEED3_Pos   (6U)
    -
    - -
    -
    - -

    ◆ GPIO_OSPEEDR_OSPEED3_Msk

    - -
    -
    - - - - -
    #define GPIO_OSPEEDR_OSPEED3_Msk   (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos)
    -
    -

    0x000000C0

    - -
    -
    - -

    ◆ GPIO_OSPEEDR_OSPEED3

    - -
    -
    - - - - -
    #define GPIO_OSPEEDR_OSPEED3   GPIO_OSPEEDR_OSPEED3_Msk
    -
    - -
    -
    - -

    ◆ GPIO_OSPEEDR_OSPEED3_0

    - -
    -
    - - - - -
    #define GPIO_OSPEEDR_OSPEED3_0   (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos)
    -
    -

    0x00000040

    - -
    -
    - -

    ◆ GPIO_OSPEEDR_OSPEED3_1

    - -
    -
    - - - - -
    #define GPIO_OSPEEDR_OSPEED3_1   (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos)
    -
    -

    0x00000080

    - -
    -
    - -

    ◆ GPIO_OSPEEDR_OSPEED4_Pos

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    -
    - - - - -
    #define GPIO_OSPEEDR_OSPEED4_Pos   (8U)
    -
    - -
    -
    - -

    ◆ GPIO_OSPEEDR_OSPEED4_Msk

    - -
    -
    - - - - -
    #define GPIO_OSPEEDR_OSPEED4_Msk   (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos)
    -
    -

    0x00000300

    - -
    -
    - -

    ◆ GPIO_OSPEEDR_OSPEED4

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    -
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    #define GPIO_OSPEEDR_OSPEED4   GPIO_OSPEEDR_OSPEED4_Msk
    -
    - -
    -
    - -

    ◆ GPIO_OSPEEDR_OSPEED4_0

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    -
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    #define GPIO_OSPEEDR_OSPEED4_0   (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos)
    -
    -

    0x00000100

    - -
    -
    - -

    ◆ GPIO_OSPEEDR_OSPEED4_1

    - -
    -
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    #define GPIO_OSPEEDR_OSPEED4_1   (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos)
    -
    -

    0x00000200

    - -
    -
    - -

    ◆ GPIO_OSPEEDR_OSPEED5_Pos

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    -
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    #define GPIO_OSPEEDR_OSPEED5_Pos   (10U)
    -
    - -
    -
    - -

    ◆ GPIO_OSPEEDR_OSPEED5_Msk

    - -
    -
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    #define GPIO_OSPEEDR_OSPEED5_Msk   (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos)
    -
    -

    0x00000C00

    - -
    -
    - -

    ◆ GPIO_OSPEEDR_OSPEED5

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    -
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    #define GPIO_OSPEEDR_OSPEED5   GPIO_OSPEEDR_OSPEED5_Msk
    -
    - -
    -
    - -

    ◆ GPIO_OSPEEDR_OSPEED5_0

    - -
    -
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    #define GPIO_OSPEEDR_OSPEED5_0   (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos)
    -
    -

    0x00000400

    - -
    -
    - -

    ◆ GPIO_OSPEEDR_OSPEED5_1

    - -
    -
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    #define GPIO_OSPEEDR_OSPEED5_1   (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos)
    -
    -

    0x00000800

    - -
    -
    - -

    ◆ GPIO_OSPEEDR_OSPEED6_Pos

    - -
    -
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    #define GPIO_OSPEEDR_OSPEED6_Pos   (12U)
    -
    - -
    -
    - -

    ◆ GPIO_OSPEEDR_OSPEED6_Msk

    - -
    -
    - - - - -
    #define GPIO_OSPEEDR_OSPEED6_Msk   (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos)
    -
    -

    0x00003000

    - -
    -
    - -

    ◆ GPIO_OSPEEDR_OSPEED6

    - -
    -
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    #define GPIO_OSPEEDR_OSPEED6   GPIO_OSPEEDR_OSPEED6_Msk
    -
    - -
    -
    - -

    ◆ GPIO_OSPEEDR_OSPEED6_0

    - -
    -
    - - - - -
    #define GPIO_OSPEEDR_OSPEED6_0   (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos)
    -
    -

    0x00001000

    - -
    -
    - -

    ◆ GPIO_OSPEEDR_OSPEED6_1

    - -
    -
    - - - - -
    #define GPIO_OSPEEDR_OSPEED6_1   (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos)
    -
    -

    0x00002000

    - -
    -
    - -

    ◆ GPIO_OSPEEDR_OSPEED7_Pos

    - -
    -
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    #define GPIO_OSPEEDR_OSPEED7_Pos   (14U)
    -
    - -
    -
    - -

    ◆ GPIO_OSPEEDR_OSPEED7_Msk

    - -
    -
    - - - - -
    #define GPIO_OSPEEDR_OSPEED7_Msk   (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos)
    -
    -

    0x0000C000

    - -
    -
    - -

    ◆ GPIO_OSPEEDR_OSPEED7

    - -
    -
    - - - - -
    #define GPIO_OSPEEDR_OSPEED7   GPIO_OSPEEDR_OSPEED7_Msk
    -
    - -
    -
    - -

    ◆ GPIO_OSPEEDR_OSPEED7_0

    - -
    -
    - - - - -
    #define GPIO_OSPEEDR_OSPEED7_0   (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos)
    -
    -

    0x00004000

    - -
    -
    - -

    ◆ GPIO_OSPEEDR_OSPEED7_1

    - -
    -
    - - - - -
    #define GPIO_OSPEEDR_OSPEED7_1   (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos)
    -
    -

    0x00008000

    - -
    -
    - -

    ◆ GPIO_OSPEEDR_OSPEED8_Pos

    - -
    -
    - - - - -
    #define GPIO_OSPEEDR_OSPEED8_Pos   (16U)
    -
    - -
    -
    - -

    ◆ GPIO_OSPEEDR_OSPEED8_Msk

    - -
    -
    - - - - -
    #define GPIO_OSPEEDR_OSPEED8_Msk   (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos)
    -
    -

    0x00030000

    - -
    -
    - -

    ◆ GPIO_OSPEEDR_OSPEED8

    - -
    -
    - - - - -
    #define GPIO_OSPEEDR_OSPEED8   GPIO_OSPEEDR_OSPEED8_Msk
    -
    - -
    -
    - -

    ◆ GPIO_OSPEEDR_OSPEED8_0

    - -
    -
    - - - - -
    #define GPIO_OSPEEDR_OSPEED8_0   (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos)
    -
    -

    0x00010000

    - -
    -
    - -

    ◆ GPIO_OSPEEDR_OSPEED8_1

    - -
    -
    - - - - -
    #define GPIO_OSPEEDR_OSPEED8_1   (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos)
    -
    -

    0x00020000

    - -
    -
    - -

    ◆ GPIO_OSPEEDR_OSPEED9_Pos

    - -
    -
    - - - - -
    #define GPIO_OSPEEDR_OSPEED9_Pos   (18U)
    -
    - -
    -
    - -

    ◆ GPIO_OSPEEDR_OSPEED9_Msk

    - -
    -
    - - - - -
    #define GPIO_OSPEEDR_OSPEED9_Msk   (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos)
    -
    -

    0x000C0000

    - -
    -
    - -

    ◆ GPIO_OSPEEDR_OSPEED9

    - -
    -
    - - - - -
    #define GPIO_OSPEEDR_OSPEED9   GPIO_OSPEEDR_OSPEED9_Msk
    -
    - -
    -
    - -

    ◆ GPIO_OSPEEDR_OSPEED9_0

    - -
    -
    - - - - -
    #define GPIO_OSPEEDR_OSPEED9_0   (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos)
    -
    -

    0x00040000

    - -
    -
    - -

    ◆ GPIO_OSPEEDR_OSPEED9_1

    - -
    -
    - - - - -
    #define GPIO_OSPEEDR_OSPEED9_1   (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos)
    -
    -

    0x00080000

    - -
    -
    - -

    ◆ GPIO_OSPEEDR_OSPEED10_Pos

    - -
    -
    - - - - -
    #define GPIO_OSPEEDR_OSPEED10_Pos   (20U)
    -
    - -
    -
    - -

    ◆ GPIO_OSPEEDR_OSPEED10_Msk

    - -
    -
    - - - - -
    #define GPIO_OSPEEDR_OSPEED10_Msk   (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos)
    -
    -

    0x00300000

    - -
    -
    - -

    ◆ GPIO_OSPEEDR_OSPEED10

    - -
    -
    - - - - -
    #define GPIO_OSPEEDR_OSPEED10   GPIO_OSPEEDR_OSPEED10_Msk
    -
    - -
    -
    - -

    ◆ GPIO_OSPEEDR_OSPEED10_0

    - -
    -
    - - - - -
    #define GPIO_OSPEEDR_OSPEED10_0   (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos)
    -
    -

    0x00100000

    - -
    -
    - -

    ◆ GPIO_OSPEEDR_OSPEED10_1

    - -
    -
    - - - - -
    #define GPIO_OSPEEDR_OSPEED10_1   (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos)
    -
    -

    0x00200000

    - -
    -
    - -

    ◆ GPIO_OSPEEDR_OSPEED11_Pos

    - -
    -
    - - - - -
    #define GPIO_OSPEEDR_OSPEED11_Pos   (22U)
    -
    - -
    -
    - -

    ◆ GPIO_OSPEEDR_OSPEED11_Msk

    - -
    -
    - - - - -
    #define GPIO_OSPEEDR_OSPEED11_Msk   (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos)
    -
    -

    0x00C00000

    - -
    -
    - -

    ◆ GPIO_OSPEEDR_OSPEED11

    - -
    -
    - - - - -
    #define GPIO_OSPEEDR_OSPEED11   GPIO_OSPEEDR_OSPEED11_Msk
    -
    - -
    -
    - -

    ◆ GPIO_OSPEEDR_OSPEED11_0

    - -
    -
    - - - - -
    #define GPIO_OSPEEDR_OSPEED11_0   (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos)
    -
    -

    0x00400000

    - -
    -
    - -

    ◆ GPIO_OSPEEDR_OSPEED11_1

    - -
    -
    - - - - -
    #define GPIO_OSPEEDR_OSPEED11_1   (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos)
    -
    -

    0x00800000

    - -
    -
    - -

    ◆ GPIO_OSPEEDR_OSPEED12_Pos

    - -
    -
    - - - - -
    #define GPIO_OSPEEDR_OSPEED12_Pos   (24U)
    -
    - -
    -
    - -

    ◆ GPIO_OSPEEDR_OSPEED12_Msk

    - -
    -
    - - - - -
    #define GPIO_OSPEEDR_OSPEED12_Msk   (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos)
    -
    -

    0x03000000

    - -
    -
    - -

    ◆ GPIO_OSPEEDR_OSPEED12

    - -
    -
    - - - - -
    #define GPIO_OSPEEDR_OSPEED12   GPIO_OSPEEDR_OSPEED12_Msk
    -
    - -
    -
    - -

    ◆ GPIO_OSPEEDR_OSPEED12_0

    - -
    -
    - - - - -
    #define GPIO_OSPEEDR_OSPEED12_0   (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos)
    -
    -

    0x01000000

    - -
    -
    - -

    ◆ GPIO_OSPEEDR_OSPEED12_1

    - -
    -
    - - - - -
    #define GPIO_OSPEEDR_OSPEED12_1   (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos)
    -
    -

    0x02000000

    - -
    -
    - -

    ◆ GPIO_OSPEEDR_OSPEED13_Pos

    - -
    -
    - - - - -
    #define GPIO_OSPEEDR_OSPEED13_Pos   (26U)
    -
    - -
    -
    - -

    ◆ GPIO_OSPEEDR_OSPEED13_Msk

    - -
    -
    - - - - -
    #define GPIO_OSPEEDR_OSPEED13_Msk   (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos)
    -
    -

    0x0C000000

    - -
    -
    - -

    ◆ GPIO_OSPEEDR_OSPEED13

    - -
    -
    - - - - -
    #define GPIO_OSPEEDR_OSPEED13   GPIO_OSPEEDR_OSPEED13_Msk
    -
    - -
    -
    - -

    ◆ GPIO_OSPEEDR_OSPEED13_0

    - -
    -
    - - - - -
    #define GPIO_OSPEEDR_OSPEED13_0   (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos)
    -
    -

    0x04000000

    - -
    -
    - -

    ◆ GPIO_OSPEEDR_OSPEED13_1

    - -
    -
    - - - - -
    #define GPIO_OSPEEDR_OSPEED13_1   (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos)
    -
    -

    0x08000000

    - -
    -
    - -

    ◆ GPIO_OSPEEDR_OSPEED14_Pos

    - -
    -
    - - - - -
    #define GPIO_OSPEEDR_OSPEED14_Pos   (28U)
    -
    - -
    -
    - -

    ◆ GPIO_OSPEEDR_OSPEED14_Msk

    - -
    -
    - - - - -
    #define GPIO_OSPEEDR_OSPEED14_Msk   (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos)
    -
    -

    0x30000000

    - -
    -
    - -

    ◆ GPIO_OSPEEDR_OSPEED14

    - -
    -
    - - - - -
    #define GPIO_OSPEEDR_OSPEED14   GPIO_OSPEEDR_OSPEED14_Msk
    -
    - -
    -
    - -

    ◆ GPIO_OSPEEDR_OSPEED14_0

    - -
    -
    - - - - -
    #define GPIO_OSPEEDR_OSPEED14_0   (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos)
    -
    -

    0x10000000

    - -
    -
    - -

    ◆ GPIO_OSPEEDR_OSPEED14_1

    - -
    -
    - - - - -
    #define GPIO_OSPEEDR_OSPEED14_1   (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos)
    -
    -

    0x20000000

    - -
    -
    - -

    ◆ GPIO_OSPEEDR_OSPEED15_Pos

    - -
    -
    - - - - -
    #define GPIO_OSPEEDR_OSPEED15_Pos   (30U)
    -
    - -
    -
    - -

    ◆ GPIO_OSPEEDR_OSPEED15_Msk

    - -
    -
    - - - - -
    #define GPIO_OSPEEDR_OSPEED15_Msk   (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos)
    -
    -

    0xC0000000

    - -
    -
    - -

    ◆ GPIO_OSPEEDR_OSPEED15

    - -
    -
    - - - - -
    #define GPIO_OSPEEDR_OSPEED15   GPIO_OSPEEDR_OSPEED15_Msk
    -
    - -
    -
    - -

    ◆ GPIO_OSPEEDR_OSPEED15_0

    - -
    -
    - - - - -
    #define GPIO_OSPEEDR_OSPEED15_0   (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos)
    -
    -

    0x40000000

    - -
    -
    - -

    ◆ GPIO_OSPEEDR_OSPEED15_1

    - -
    -
    - - - - -
    #define GPIO_OSPEEDR_OSPEED15_1   (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos)
    -
    -

    0x80000000

    - -
    -
    - -

    ◆ GPIO_OSPEEDER_OSPEEDR0

    - -
    -
    - - - - -
    #define GPIO_OSPEEDER_OSPEEDR0   GPIO_OSPEEDR_OSPEED0
    -
    - -
    -
    - -

    ◆ GPIO_OSPEEDER_OSPEEDR0_0

    - -
    -
    - - - - -
    #define GPIO_OSPEEDER_OSPEEDR0_0   GPIO_OSPEEDR_OSPEED0_0
    -
    - -
    -
    - -

    ◆ GPIO_OSPEEDER_OSPEEDR0_1

    - -
    -
    - - - - -
    #define GPIO_OSPEEDER_OSPEEDR0_1   GPIO_OSPEEDR_OSPEED0_1
    -
    - -
    -
    - -

    ◆ GPIO_OSPEEDER_OSPEEDR1

    - -
    -
    - - - - -
    #define GPIO_OSPEEDER_OSPEEDR1   GPIO_OSPEEDR_OSPEED1
    -
    - -
    -
    - -

    ◆ GPIO_OSPEEDER_OSPEEDR1_0

    - -
    -
    - - - - -
    #define GPIO_OSPEEDER_OSPEEDR1_0   GPIO_OSPEEDR_OSPEED1_0
    -
    - -
    -
    - -

    ◆ GPIO_OSPEEDER_OSPEEDR1_1

    - -
    -
    - - - - -
    #define GPIO_OSPEEDER_OSPEEDR1_1   GPIO_OSPEEDR_OSPEED1_1
    -
    - -
    -
    - -

    ◆ GPIO_OSPEEDER_OSPEEDR2

    - -
    -
    - - - - -
    #define GPIO_OSPEEDER_OSPEEDR2   GPIO_OSPEEDR_OSPEED2
    -
    - -
    -
    - -

    ◆ GPIO_OSPEEDER_OSPEEDR2_0

    - -
    -
    - - - - -
    #define GPIO_OSPEEDER_OSPEEDR2_0   GPIO_OSPEEDR_OSPEED2_0
    -
    - -
    -
    - -

    ◆ GPIO_OSPEEDER_OSPEEDR2_1

    - -
    -
    - - - - -
    #define GPIO_OSPEEDER_OSPEEDR2_1   GPIO_OSPEEDR_OSPEED2_1
    -
    - -
    -
    - -

    ◆ GPIO_OSPEEDER_OSPEEDR3

    - -
    -
    - - - - -
    #define GPIO_OSPEEDER_OSPEEDR3   GPIO_OSPEEDR_OSPEED3
    -
    - -
    -
    - -

    ◆ GPIO_OSPEEDER_OSPEEDR3_0

    - -
    -
    - - - - -
    #define GPIO_OSPEEDER_OSPEEDR3_0   GPIO_OSPEEDR_OSPEED3_0
    -
    - -
    -
    - -

    ◆ GPIO_OSPEEDER_OSPEEDR3_1

    - -
    -
    - - - - -
    #define GPIO_OSPEEDER_OSPEEDR3_1   GPIO_OSPEEDR_OSPEED3_1
    -
    - -
    -
    - -

    ◆ GPIO_OSPEEDER_OSPEEDR4

    - -
    -
    - - - - -
    #define GPIO_OSPEEDER_OSPEEDR4   GPIO_OSPEEDR_OSPEED4
    -
    - -
    -
    - -

    ◆ GPIO_OSPEEDER_OSPEEDR4_0

    - -
    -
    - - - - -
    #define GPIO_OSPEEDER_OSPEEDR4_0   GPIO_OSPEEDR_OSPEED4_0
    -
    - -
    -
    - -

    ◆ GPIO_OSPEEDER_OSPEEDR4_1

    - -
    -
    - - - - -
    #define GPIO_OSPEEDER_OSPEEDR4_1   GPIO_OSPEEDR_OSPEED4_1
    -
    - -
    -
    - -

    ◆ GPIO_OSPEEDER_OSPEEDR5

    - -
    -
    - - - - -
    #define GPIO_OSPEEDER_OSPEEDR5   GPIO_OSPEEDR_OSPEED5
    -
    - -
    -
    - -

    ◆ GPIO_OSPEEDER_OSPEEDR5_0

    - -
    -
    - - - - -
    #define GPIO_OSPEEDER_OSPEEDR5_0   GPIO_OSPEEDR_OSPEED5_0
    -
    - -
    -
    - -

    ◆ GPIO_OSPEEDER_OSPEEDR5_1

    - -
    -
    - - - - -
    #define GPIO_OSPEEDER_OSPEEDR5_1   GPIO_OSPEEDR_OSPEED5_1
    -
    - -
    -
    - -

    ◆ GPIO_OSPEEDER_OSPEEDR6

    - -
    -
    - - - - -
    #define GPIO_OSPEEDER_OSPEEDR6   GPIO_OSPEEDR_OSPEED6
    -
    - -
    -
    - -

    ◆ GPIO_OSPEEDER_OSPEEDR6_0

    - -
    -
    - - - - -
    #define GPIO_OSPEEDER_OSPEEDR6_0   GPIO_OSPEEDR_OSPEED6_0
    -
    - -
    -
    - -

    ◆ GPIO_OSPEEDER_OSPEEDR6_1

    - -
    -
    - - - - -
    #define GPIO_OSPEEDER_OSPEEDR6_1   GPIO_OSPEEDR_OSPEED6_1
    -
    - -
    -
    - -

    ◆ GPIO_OSPEEDER_OSPEEDR7

    - -
    -
    - - - - -
    #define GPIO_OSPEEDER_OSPEEDR7   GPIO_OSPEEDR_OSPEED7
    -
    - -
    -
    - -

    ◆ GPIO_OSPEEDER_OSPEEDR7_0

    - -
    -
    - - - - -
    #define GPIO_OSPEEDER_OSPEEDR7_0   GPIO_OSPEEDR_OSPEED7_0
    -
    - -
    -
    - -

    ◆ GPIO_OSPEEDER_OSPEEDR7_1

    - -
    -
    - - - - -
    #define GPIO_OSPEEDER_OSPEEDR7_1   GPIO_OSPEEDR_OSPEED7_1
    -
    - -
    -
    - -

    ◆ GPIO_OSPEEDER_OSPEEDR8

    - -
    -
    - - - - -
    #define GPIO_OSPEEDER_OSPEEDR8   GPIO_OSPEEDR_OSPEED8
    -
    - -
    -
    - -

    ◆ GPIO_OSPEEDER_OSPEEDR8_0

    - -
    -
    - - - - -
    #define GPIO_OSPEEDER_OSPEEDR8_0   GPIO_OSPEEDR_OSPEED8_0
    -
    - -
    -
    - -

    ◆ GPIO_OSPEEDER_OSPEEDR8_1

    - -
    -
    - - - - -
    #define GPIO_OSPEEDER_OSPEEDR8_1   GPIO_OSPEEDR_OSPEED8_1
    -
    - -
    -
    - -

    ◆ GPIO_OSPEEDER_OSPEEDR9

    - -
    -
    - - - - -
    #define GPIO_OSPEEDER_OSPEEDR9   GPIO_OSPEEDR_OSPEED9
    -
    - -
    -
    - -

    ◆ GPIO_OSPEEDER_OSPEEDR9_0

    - -
    -
    - - - - -
    #define GPIO_OSPEEDER_OSPEEDR9_0   GPIO_OSPEEDR_OSPEED9_0
    -
    - -
    -
    - -

    ◆ GPIO_OSPEEDER_OSPEEDR9_1

    - -
    -
    - - - - -
    #define GPIO_OSPEEDER_OSPEEDR9_1   GPIO_OSPEEDR_OSPEED9_1
    -
    - -
    -
    - -

    ◆ GPIO_OSPEEDER_OSPEEDR10

    - -
    -
    - - - - -
    #define GPIO_OSPEEDER_OSPEEDR10   GPIO_OSPEEDR_OSPEED10
    -
    - -
    -
    - -

    ◆ GPIO_OSPEEDER_OSPEEDR10_0

    - -
    -
    - - - - -
    #define GPIO_OSPEEDER_OSPEEDR10_0   GPIO_OSPEEDR_OSPEED10_0
    -
    - -
    -
    - -

    ◆ GPIO_OSPEEDER_OSPEEDR10_1

    - -
    -
    - - - - -
    #define GPIO_OSPEEDER_OSPEEDR10_1   GPIO_OSPEEDR_OSPEED10_1
    -
    - -
    -
    - -

    ◆ GPIO_OSPEEDER_OSPEEDR11

    - -
    -
    - - - - -
    #define GPIO_OSPEEDER_OSPEEDR11   GPIO_OSPEEDR_OSPEED11
    -
    - -
    -
    - -

    ◆ GPIO_OSPEEDER_OSPEEDR11_0

    - -
    -
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    #define GPIO_OSPEEDER_OSPEEDR11_0   GPIO_OSPEEDR_OSPEED11_0
    -
    - -
    -
    - -

    ◆ GPIO_OSPEEDER_OSPEEDR11_1

    - -
    -
    - - - - -
    #define GPIO_OSPEEDER_OSPEEDR11_1   GPIO_OSPEEDR_OSPEED11_1
    -
    - -
    -
    - -

    ◆ GPIO_OSPEEDER_OSPEEDR12

    - -
    -
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    #define GPIO_OSPEEDER_OSPEEDR12   GPIO_OSPEEDR_OSPEED12
    -
    - -
    -
    - -

    ◆ GPIO_OSPEEDER_OSPEEDR12_0

    - -
    -
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    #define GPIO_OSPEEDER_OSPEEDR12_0   GPIO_OSPEEDR_OSPEED12_0
    -
    - -
    -
    - -

    ◆ GPIO_OSPEEDER_OSPEEDR12_1

    - -
    -
    - - - - -
    #define GPIO_OSPEEDER_OSPEEDR12_1   GPIO_OSPEEDR_OSPEED12_1
    -
    - -
    -
    - -

    ◆ GPIO_OSPEEDER_OSPEEDR13

    - -
    -
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    #define GPIO_OSPEEDER_OSPEEDR13   GPIO_OSPEEDR_OSPEED13
    -
    - -
    -
    - -

    ◆ GPIO_OSPEEDER_OSPEEDR13_0

    - -
    -
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    #define GPIO_OSPEEDER_OSPEEDR13_0   GPIO_OSPEEDR_OSPEED13_0
    -
    - -
    -
    - -

    ◆ GPIO_OSPEEDER_OSPEEDR13_1

    - -
    -
    - - - - -
    #define GPIO_OSPEEDER_OSPEEDR13_1   GPIO_OSPEEDR_OSPEED13_1
    -
    - -
    -
    - -

    ◆ GPIO_OSPEEDER_OSPEEDR14

    - -
    -
    - - - - -
    #define GPIO_OSPEEDER_OSPEEDR14   GPIO_OSPEEDR_OSPEED14
    -
    - -
    -
    - -

    ◆ GPIO_OSPEEDER_OSPEEDR14_0

    - -
    -
    - - - - -
    #define GPIO_OSPEEDER_OSPEEDR14_0   GPIO_OSPEEDR_OSPEED14_0
    -
    - -
    -
    - -

    ◆ GPIO_OSPEEDER_OSPEEDR14_1

    - -
    -
    - - - - -
    #define GPIO_OSPEEDER_OSPEEDR14_1   GPIO_OSPEEDR_OSPEED14_1
    -
    - -
    -
    - -

    ◆ GPIO_OSPEEDER_OSPEEDR15

    - -
    -
    - - - - -
    #define GPIO_OSPEEDER_OSPEEDR15   GPIO_OSPEEDR_OSPEED15
    -
    - -
    -
    - -

    ◆ GPIO_OSPEEDER_OSPEEDR15_0

    - -
    -
    - - - - -
    #define GPIO_OSPEEDER_OSPEEDR15_0   GPIO_OSPEEDR_OSPEED15_0
    -
    - -
    -
    - -

    ◆ GPIO_OSPEEDER_OSPEEDR15_1

    - -
    -
    - - - - -
    #define GPIO_OSPEEDER_OSPEEDR15_1   GPIO_OSPEEDR_OSPEED15_1
    -
    - -
    -
    - -

    ◆ GPIO_PUPDR_PUPD0_Pos

    - -
    -
    - - - - -
    #define GPIO_PUPDR_PUPD0_Pos   (0U)
    -
    - -
    -
    - -

    ◆ GPIO_PUPDR_PUPD0_Msk

    - -
    -
    - - - - -
    #define GPIO_PUPDR_PUPD0_Msk   (0x3UL << GPIO_PUPDR_PUPD0_Pos)
    -
    -

    0x00000003

    - -
    -
    - -

    ◆ GPIO_PUPDR_PUPD0

    - -
    -
    - - - - -
    #define GPIO_PUPDR_PUPD0   GPIO_PUPDR_PUPD0_Msk
    -
    - -
    -
    - -

    ◆ GPIO_PUPDR_PUPD0_0

    - -
    -
    - - - - -
    #define GPIO_PUPDR_PUPD0_0   (0x1UL << GPIO_PUPDR_PUPD0_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ GPIO_PUPDR_PUPD0_1

    - -
    -
    - - - - -
    #define GPIO_PUPDR_PUPD0_1   (0x2UL << GPIO_PUPDR_PUPD0_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ GPIO_PUPDR_PUPD1_Pos

    - -
    -
    - - - - -
    #define GPIO_PUPDR_PUPD1_Pos   (2U)
    -
    - -
    -
    - -

    ◆ GPIO_PUPDR_PUPD1_Msk

    - -
    -
    - - - - -
    #define GPIO_PUPDR_PUPD1_Msk   (0x3UL << GPIO_PUPDR_PUPD1_Pos)
    -
    -

    0x0000000C

    - -
    -
    - -

    ◆ GPIO_PUPDR_PUPD1

    - -
    -
    - - - - -
    #define GPIO_PUPDR_PUPD1   GPIO_PUPDR_PUPD1_Msk
    -
    - -
    -
    - -

    ◆ GPIO_PUPDR_PUPD1_0

    - -
    -
    - - - - -
    #define GPIO_PUPDR_PUPD1_0   (0x1UL << GPIO_PUPDR_PUPD1_Pos)
    -
    -

    0x00000004

    - -
    -
    - -

    ◆ GPIO_PUPDR_PUPD1_1

    - -
    -
    - - - - -
    #define GPIO_PUPDR_PUPD1_1   (0x2UL << GPIO_PUPDR_PUPD1_Pos)
    -
    -

    0x00000008

    - -
    -
    - -

    ◆ GPIO_PUPDR_PUPD2_Pos

    - -
    -
    - - - - -
    #define GPIO_PUPDR_PUPD2_Pos   (4U)
    -
    - -
    -
    - -

    ◆ GPIO_PUPDR_PUPD2_Msk

    - -
    -
    - - - - -
    #define GPIO_PUPDR_PUPD2_Msk   (0x3UL << GPIO_PUPDR_PUPD2_Pos)
    -
    -

    0x00000030

    - -
    -
    - -

    ◆ GPIO_PUPDR_PUPD2

    - -
    -
    - - - - -
    #define GPIO_PUPDR_PUPD2   GPIO_PUPDR_PUPD2_Msk
    -
    - -
    -
    - -

    ◆ GPIO_PUPDR_PUPD2_0

    - -
    -
    - - - - -
    #define GPIO_PUPDR_PUPD2_0   (0x1UL << GPIO_PUPDR_PUPD2_Pos)
    -
    -

    0x00000010

    - -
    -
    - -

    ◆ GPIO_PUPDR_PUPD2_1

    - -
    -
    - - - - -
    #define GPIO_PUPDR_PUPD2_1   (0x2UL << GPIO_PUPDR_PUPD2_Pos)
    -
    -

    0x00000020

    - -
    -
    - -

    ◆ GPIO_PUPDR_PUPD3_Pos

    - -
    -
    - - - - -
    #define GPIO_PUPDR_PUPD3_Pos   (6U)
    -
    - -
    -
    - -

    ◆ GPIO_PUPDR_PUPD3_Msk

    - -
    -
    - - - - -
    #define GPIO_PUPDR_PUPD3_Msk   (0x3UL << GPIO_PUPDR_PUPD3_Pos)
    -
    -

    0x000000C0

    - -
    -
    - -

    ◆ GPIO_PUPDR_PUPD3

    - -
    -
    - - - - -
    #define GPIO_PUPDR_PUPD3   GPIO_PUPDR_PUPD3_Msk
    -
    - -
    -
    - -

    ◆ GPIO_PUPDR_PUPD3_0

    - -
    -
    - - - - -
    #define GPIO_PUPDR_PUPD3_0   (0x1UL << GPIO_PUPDR_PUPD3_Pos)
    -
    -

    0x00000040

    - -
    -
    - -

    ◆ GPIO_PUPDR_PUPD3_1

    - -
    -
    - - - - -
    #define GPIO_PUPDR_PUPD3_1   (0x2UL << GPIO_PUPDR_PUPD3_Pos)
    -
    -

    0x00000080

    - -
    -
    - -

    ◆ GPIO_PUPDR_PUPD4_Pos

    - -
    -
    - - - - -
    #define GPIO_PUPDR_PUPD4_Pos   (8U)
    -
    - -
    -
    - -

    ◆ GPIO_PUPDR_PUPD4_Msk

    - -
    -
    - - - - -
    #define GPIO_PUPDR_PUPD4_Msk   (0x3UL << GPIO_PUPDR_PUPD4_Pos)
    -
    -

    0x00000300

    - -
    -
    - -

    ◆ GPIO_PUPDR_PUPD4

    - -
    -
    - - - - -
    #define GPIO_PUPDR_PUPD4   GPIO_PUPDR_PUPD4_Msk
    -
    - -
    -
    - -

    ◆ GPIO_PUPDR_PUPD4_0

    - -
    -
    - - - - -
    #define GPIO_PUPDR_PUPD4_0   (0x1UL << GPIO_PUPDR_PUPD4_Pos)
    -
    -

    0x00000100

    - -
    -
    - -

    ◆ GPIO_PUPDR_PUPD4_1

    - -
    -
    - - - - -
    #define GPIO_PUPDR_PUPD4_1   (0x2UL << GPIO_PUPDR_PUPD4_Pos)
    -
    -

    0x00000200

    - -
    -
    - -

    ◆ GPIO_PUPDR_PUPD5_Pos

    - -
    -
    - - - - -
    #define GPIO_PUPDR_PUPD5_Pos   (10U)
    -
    - -
    -
    - -

    ◆ GPIO_PUPDR_PUPD5_Msk

    - -
    -
    - - - - -
    #define GPIO_PUPDR_PUPD5_Msk   (0x3UL << GPIO_PUPDR_PUPD5_Pos)
    -
    -

    0x00000C00

    - -
    -
    - -

    ◆ GPIO_PUPDR_PUPD5

    - -
    -
    - - - - -
    #define GPIO_PUPDR_PUPD5   GPIO_PUPDR_PUPD5_Msk
    -
    - -
    -
    - -

    ◆ GPIO_PUPDR_PUPD5_0

    - -
    -
    - - - - -
    #define GPIO_PUPDR_PUPD5_0   (0x1UL << GPIO_PUPDR_PUPD5_Pos)
    -
    -

    0x00000400

    - -
    -
    - -

    ◆ GPIO_PUPDR_PUPD5_1

    - -
    -
    - - - - -
    #define GPIO_PUPDR_PUPD5_1   (0x2UL << GPIO_PUPDR_PUPD5_Pos)
    -
    -

    0x00000800

    - -
    -
    - -

    ◆ GPIO_PUPDR_PUPD6_Pos

    - -
    -
    - - - - -
    #define GPIO_PUPDR_PUPD6_Pos   (12U)
    -
    - -
    -
    - -

    ◆ GPIO_PUPDR_PUPD6_Msk

    - -
    -
    - - - - -
    #define GPIO_PUPDR_PUPD6_Msk   (0x3UL << GPIO_PUPDR_PUPD6_Pos)
    -
    -

    0x00003000

    - -
    -
    - -

    ◆ GPIO_PUPDR_PUPD6

    - -
    -
    - - - - -
    #define GPIO_PUPDR_PUPD6   GPIO_PUPDR_PUPD6_Msk
    -
    - -
    -
    - -

    ◆ GPIO_PUPDR_PUPD6_0

    - -
    -
    - - - - -
    #define GPIO_PUPDR_PUPD6_0   (0x1UL << GPIO_PUPDR_PUPD6_Pos)
    -
    -

    0x00001000

    - -
    -
    - -

    ◆ GPIO_PUPDR_PUPD6_1

    - -
    -
    - - - - -
    #define GPIO_PUPDR_PUPD6_1   (0x2UL << GPIO_PUPDR_PUPD6_Pos)
    -
    -

    0x00002000

    - -
    -
    - -

    ◆ GPIO_PUPDR_PUPD7_Pos

    - -
    -
    - - - - -
    #define GPIO_PUPDR_PUPD7_Pos   (14U)
    -
    - -
    -
    - -

    ◆ GPIO_PUPDR_PUPD7_Msk

    - -
    -
    - - - - -
    #define GPIO_PUPDR_PUPD7_Msk   (0x3UL << GPIO_PUPDR_PUPD7_Pos)
    -
    -

    0x0000C000

    - -
    -
    - -

    ◆ GPIO_PUPDR_PUPD7

    - -
    -
    - - - - -
    #define GPIO_PUPDR_PUPD7   GPIO_PUPDR_PUPD7_Msk
    -
    - -
    -
    - -

    ◆ GPIO_PUPDR_PUPD7_0

    - -
    -
    - - - - -
    #define GPIO_PUPDR_PUPD7_0   (0x1UL << GPIO_PUPDR_PUPD7_Pos)
    -
    -

    0x00004000

    - -
    -
    - -

    ◆ GPIO_PUPDR_PUPD7_1

    - -
    -
    - - - - -
    #define GPIO_PUPDR_PUPD7_1   (0x2UL << GPIO_PUPDR_PUPD7_Pos)
    -
    -

    0x00008000

    - -
    -
    - -

    ◆ GPIO_PUPDR_PUPD8_Pos

    - -
    -
    - - - - -
    #define GPIO_PUPDR_PUPD8_Pos   (16U)
    -
    - -
    -
    - -

    ◆ GPIO_PUPDR_PUPD8_Msk

    - -
    -
    - - - - -
    #define GPIO_PUPDR_PUPD8_Msk   (0x3UL << GPIO_PUPDR_PUPD8_Pos)
    -
    -

    0x00030000

    - -
    -
    - -

    ◆ GPIO_PUPDR_PUPD8

    - -
    -
    - - - - -
    #define GPIO_PUPDR_PUPD8   GPIO_PUPDR_PUPD8_Msk
    -
    - -
    -
    - -

    ◆ GPIO_PUPDR_PUPD8_0

    - -
    -
    - - - - -
    #define GPIO_PUPDR_PUPD8_0   (0x1UL << GPIO_PUPDR_PUPD8_Pos)
    -
    -

    0x00010000

    - -
    -
    - -

    ◆ GPIO_PUPDR_PUPD8_1

    - -
    -
    - - - - -
    #define GPIO_PUPDR_PUPD8_1   (0x2UL << GPIO_PUPDR_PUPD8_Pos)
    -
    -

    0x00020000

    - -
    -
    - -

    ◆ GPIO_PUPDR_PUPD9_Pos

    - -
    -
    - - - - -
    #define GPIO_PUPDR_PUPD9_Pos   (18U)
    -
    - -
    -
    - -

    ◆ GPIO_PUPDR_PUPD9_Msk

    - -
    -
    - - - - -
    #define GPIO_PUPDR_PUPD9_Msk   (0x3UL << GPIO_PUPDR_PUPD9_Pos)
    -
    -

    0x000C0000

    - -
    -
    - -

    ◆ GPIO_PUPDR_PUPD9

    - -
    -
    - - - - -
    #define GPIO_PUPDR_PUPD9   GPIO_PUPDR_PUPD9_Msk
    -
    - -
    -
    - -

    ◆ GPIO_PUPDR_PUPD9_0

    - -
    -
    - - - - -
    #define GPIO_PUPDR_PUPD9_0   (0x1UL << GPIO_PUPDR_PUPD9_Pos)
    -
    -

    0x00040000

    - -
    -
    - -

    ◆ GPIO_PUPDR_PUPD9_1

    - -
    -
    - - - - -
    #define GPIO_PUPDR_PUPD9_1   (0x2UL << GPIO_PUPDR_PUPD9_Pos)
    -
    -

    0x00080000

    - -
    -
    - -

    ◆ GPIO_PUPDR_PUPD10_Pos

    - -
    -
    - - - - -
    #define GPIO_PUPDR_PUPD10_Pos   (20U)
    -
    - -
    -
    - -

    ◆ GPIO_PUPDR_PUPD10_Msk

    - -
    -
    - - - - -
    #define GPIO_PUPDR_PUPD10_Msk   (0x3UL << GPIO_PUPDR_PUPD10_Pos)
    -
    -

    0x00300000

    - -
    -
    - -

    ◆ GPIO_PUPDR_PUPD10

    - -
    -
    - - - - -
    #define GPIO_PUPDR_PUPD10   GPIO_PUPDR_PUPD10_Msk
    -
    - -
    -
    - -

    ◆ GPIO_PUPDR_PUPD10_0

    - -
    -
    - - - - -
    #define GPIO_PUPDR_PUPD10_0   (0x1UL << GPIO_PUPDR_PUPD10_Pos)
    -
    -

    0x00100000

    - -
    -
    - -

    ◆ GPIO_PUPDR_PUPD10_1

    - -
    -
    - - - - -
    #define GPIO_PUPDR_PUPD10_1   (0x2UL << GPIO_PUPDR_PUPD10_Pos)
    -
    -

    0x00200000

    - -
    -
    - -

    ◆ GPIO_PUPDR_PUPD11_Pos

    - -
    -
    - - - - -
    #define GPIO_PUPDR_PUPD11_Pos   (22U)
    -
    - -
    -
    - -

    ◆ GPIO_PUPDR_PUPD11_Msk

    - -
    -
    - - - - -
    #define GPIO_PUPDR_PUPD11_Msk   (0x3UL << GPIO_PUPDR_PUPD11_Pos)
    -
    -

    0x00C00000

    - -
    -
    - -

    ◆ GPIO_PUPDR_PUPD11

    - -
    -
    - - - - -
    #define GPIO_PUPDR_PUPD11   GPIO_PUPDR_PUPD11_Msk
    -
    - -
    -
    - -

    ◆ GPIO_PUPDR_PUPD11_0

    - -
    -
    - - - - -
    #define GPIO_PUPDR_PUPD11_0   (0x1UL << GPIO_PUPDR_PUPD11_Pos)
    -
    -

    0x00400000

    - -
    -
    - -

    ◆ GPIO_PUPDR_PUPD11_1

    - -
    -
    - - - - -
    #define GPIO_PUPDR_PUPD11_1   (0x2UL << GPIO_PUPDR_PUPD11_Pos)
    -
    -

    0x00800000

    - -
    -
    - -

    ◆ GPIO_PUPDR_PUPD12_Pos

    - -
    -
    - - - - -
    #define GPIO_PUPDR_PUPD12_Pos   (24U)
    -
    - -
    -
    - -

    ◆ GPIO_PUPDR_PUPD12_Msk

    - -
    -
    - - - - -
    #define GPIO_PUPDR_PUPD12_Msk   (0x3UL << GPIO_PUPDR_PUPD12_Pos)
    -
    -

    0x03000000

    - -
    -
    - -

    ◆ GPIO_PUPDR_PUPD12

    - -
    -
    - - - - -
    #define GPIO_PUPDR_PUPD12   GPIO_PUPDR_PUPD12_Msk
    -
    - -
    -
    - -

    ◆ GPIO_PUPDR_PUPD12_0

    - -
    -
    - - - - -
    #define GPIO_PUPDR_PUPD12_0   (0x1UL << GPIO_PUPDR_PUPD12_Pos)
    -
    -

    0x01000000

    - -
    -
    - -

    ◆ GPIO_PUPDR_PUPD12_1

    - -
    -
    - - - - -
    #define GPIO_PUPDR_PUPD12_1   (0x2UL << GPIO_PUPDR_PUPD12_Pos)
    -
    -

    0x02000000

    - -
    -
    - -

    ◆ GPIO_PUPDR_PUPD13_Pos

    - -
    -
    - - - - -
    #define GPIO_PUPDR_PUPD13_Pos   (26U)
    -
    - -
    -
    - -

    ◆ GPIO_PUPDR_PUPD13_Msk

    - -
    -
    - - - - -
    #define GPIO_PUPDR_PUPD13_Msk   (0x3UL << GPIO_PUPDR_PUPD13_Pos)
    -
    -

    0x0C000000

    - -
    -
    - -

    ◆ GPIO_PUPDR_PUPD13

    - -
    -
    - - - - -
    #define GPIO_PUPDR_PUPD13   GPIO_PUPDR_PUPD13_Msk
    -
    - -
    -
    - -

    ◆ GPIO_PUPDR_PUPD13_0

    - -
    -
    - - - - -
    #define GPIO_PUPDR_PUPD13_0   (0x1UL << GPIO_PUPDR_PUPD13_Pos)
    -
    -

    0x04000000

    - -
    -
    - -

    ◆ GPIO_PUPDR_PUPD13_1

    - -
    -
    - - - - -
    #define GPIO_PUPDR_PUPD13_1   (0x2UL << GPIO_PUPDR_PUPD13_Pos)
    -
    -

    0x08000000

    - -
    -
    - -

    ◆ GPIO_PUPDR_PUPD14_Pos

    - -
    -
    - - - - -
    #define GPIO_PUPDR_PUPD14_Pos   (28U)
    -
    - -
    -
    - -

    ◆ GPIO_PUPDR_PUPD14_Msk

    - -
    -
    - - - - -
    #define GPIO_PUPDR_PUPD14_Msk   (0x3UL << GPIO_PUPDR_PUPD14_Pos)
    -
    -

    0x30000000

    - -
    -
    - -

    ◆ GPIO_PUPDR_PUPD14

    - -
    -
    - - - - -
    #define GPIO_PUPDR_PUPD14   GPIO_PUPDR_PUPD14_Msk
    -
    - -
    -
    - -

    ◆ GPIO_PUPDR_PUPD14_0

    - -
    -
    - - - - -
    #define GPIO_PUPDR_PUPD14_0   (0x1UL << GPIO_PUPDR_PUPD14_Pos)
    -
    -

    0x10000000

    - -
    -
    - -

    ◆ GPIO_PUPDR_PUPD14_1

    - -
    -
    - - - - -
    #define GPIO_PUPDR_PUPD14_1   (0x2UL << GPIO_PUPDR_PUPD14_Pos)
    -
    -

    0x20000000

    - -
    -
    - -

    ◆ GPIO_PUPDR_PUPD15_Pos

    - -
    -
    - - - - -
    #define GPIO_PUPDR_PUPD15_Pos   (30U)
    -
    - -
    -
    - -

    ◆ GPIO_PUPDR_PUPD15_Msk

    - -
    -
    - - - - -
    #define GPIO_PUPDR_PUPD15_Msk   (0x3UL << GPIO_PUPDR_PUPD15_Pos)
    -
    -

    0xC0000000

    - -
    -
    - -

    ◆ GPIO_PUPDR_PUPD15

    - -
    -
    - - - - -
    #define GPIO_PUPDR_PUPD15   GPIO_PUPDR_PUPD15_Msk
    -
    - -
    -
    - -

    ◆ GPIO_PUPDR_PUPD15_0

    - -
    -
    - - - - -
    #define GPIO_PUPDR_PUPD15_0   (0x1UL << GPIO_PUPDR_PUPD15_Pos)
    -
    -

    0x40000000

    - -
    -
    - -

    ◆ GPIO_PUPDR_PUPD15_1

    - -
    -
    - - - - -
    #define GPIO_PUPDR_PUPD15_1   (0x2UL << GPIO_PUPDR_PUPD15_Pos)
    -
    -

    0x80000000

    - -
    -
    - -

    ◆ GPIO_PUPDR_PUPDR0

    - -
    -
    - - - - -
    #define GPIO_PUPDR_PUPDR0   GPIO_PUPDR_PUPD0
    -
    - -
    -
    - -

    ◆ GPIO_PUPDR_PUPDR0_0

    - -
    -
    - - - - -
    #define GPIO_PUPDR_PUPDR0_0   GPIO_PUPDR_PUPD0_0
    -
    - -
    -
    - -

    ◆ GPIO_PUPDR_PUPDR0_1

    - -
    -
    - - - - -
    #define GPIO_PUPDR_PUPDR0_1   GPIO_PUPDR_PUPD0_1
    -
    - -
    -
    - -

    ◆ GPIO_PUPDR_PUPDR1

    - -
    -
    - - - - -
    #define GPIO_PUPDR_PUPDR1   GPIO_PUPDR_PUPD1
    -
    - -
    -
    - -

    ◆ GPIO_PUPDR_PUPDR1_0

    - -
    -
    - - - - -
    #define GPIO_PUPDR_PUPDR1_0   GPIO_PUPDR_PUPD1_0
    -
    - -
    -
    - -

    ◆ GPIO_PUPDR_PUPDR1_1

    - -
    -
    - - - - -
    #define GPIO_PUPDR_PUPDR1_1   GPIO_PUPDR_PUPD1_1
    -
    - -
    -
    - -

    ◆ GPIO_PUPDR_PUPDR2

    - -
    -
    - - - - -
    #define GPIO_PUPDR_PUPDR2   GPIO_PUPDR_PUPD2
    -
    - -
    -
    - -

    ◆ GPIO_PUPDR_PUPDR2_0

    - -
    -
    - - - - -
    #define GPIO_PUPDR_PUPDR2_0   GPIO_PUPDR_PUPD2_0
    -
    - -
    -
    - -

    ◆ GPIO_PUPDR_PUPDR2_1

    - -
    -
    - - - - -
    #define GPIO_PUPDR_PUPDR2_1   GPIO_PUPDR_PUPD2_1
    -
    - -
    -
    - -

    ◆ GPIO_PUPDR_PUPDR3

    - -
    -
    - - - - -
    #define GPIO_PUPDR_PUPDR3   GPIO_PUPDR_PUPD3
    -
    - -
    -
    - -

    ◆ GPIO_PUPDR_PUPDR3_0

    - -
    -
    - - - - -
    #define GPIO_PUPDR_PUPDR3_0   GPIO_PUPDR_PUPD3_0
    -
    - -
    -
    - -

    ◆ GPIO_PUPDR_PUPDR3_1

    - -
    -
    - - - - -
    #define GPIO_PUPDR_PUPDR3_1   GPIO_PUPDR_PUPD3_1
    -
    - -
    -
    - -

    ◆ GPIO_PUPDR_PUPDR4

    - -
    -
    - - - - -
    #define GPIO_PUPDR_PUPDR4   GPIO_PUPDR_PUPD4
    -
    - -
    -
    - -

    ◆ GPIO_PUPDR_PUPDR4_0

    - -
    -
    - - - - -
    #define GPIO_PUPDR_PUPDR4_0   GPIO_PUPDR_PUPD4_0
    -
    - -
    -
    - -

    ◆ GPIO_PUPDR_PUPDR4_1

    - -
    -
    - - - - -
    #define GPIO_PUPDR_PUPDR4_1   GPIO_PUPDR_PUPD4_1
    -
    - -
    -
    - -

    ◆ GPIO_PUPDR_PUPDR5

    - -
    -
    - - - - -
    #define GPIO_PUPDR_PUPDR5   GPIO_PUPDR_PUPD5
    -
    - -
    -
    - -

    ◆ GPIO_PUPDR_PUPDR5_0

    - -
    -
    - - - - -
    #define GPIO_PUPDR_PUPDR5_0   GPIO_PUPDR_PUPD5_0
    -
    - -
    -
    - -

    ◆ GPIO_PUPDR_PUPDR5_1

    - -
    -
    - - - - -
    #define GPIO_PUPDR_PUPDR5_1   GPIO_PUPDR_PUPD5_1
    -
    - -
    -
    - -

    ◆ GPIO_PUPDR_PUPDR6

    - -
    -
    - - - - -
    #define GPIO_PUPDR_PUPDR6   GPIO_PUPDR_PUPD6
    -
    - -
    -
    - -

    ◆ GPIO_PUPDR_PUPDR6_0

    - -
    -
    - - - - -
    #define GPIO_PUPDR_PUPDR6_0   GPIO_PUPDR_PUPD6_0
    -
    - -
    -
    - -

    ◆ GPIO_PUPDR_PUPDR6_1

    - -
    -
    - - - - -
    #define GPIO_PUPDR_PUPDR6_1   GPIO_PUPDR_PUPD6_1
    -
    - -
    -
    - -

    ◆ GPIO_PUPDR_PUPDR7

    - -
    -
    - - - - -
    #define GPIO_PUPDR_PUPDR7   GPIO_PUPDR_PUPD7
    -
    - -
    -
    - -

    ◆ GPIO_PUPDR_PUPDR7_0

    - -
    -
    - - - - -
    #define GPIO_PUPDR_PUPDR7_0   GPIO_PUPDR_PUPD7_0
    -
    - -
    -
    - -

    ◆ GPIO_PUPDR_PUPDR7_1

    - -
    -
    - - - - -
    #define GPIO_PUPDR_PUPDR7_1   GPIO_PUPDR_PUPD7_1
    -
    - -
    -
    - -

    ◆ GPIO_PUPDR_PUPDR8

    - -
    -
    - - - - -
    #define GPIO_PUPDR_PUPDR8   GPIO_PUPDR_PUPD8
    -
    - -
    -
    - -

    ◆ GPIO_PUPDR_PUPDR8_0

    - -
    -
    - - - - -
    #define GPIO_PUPDR_PUPDR8_0   GPIO_PUPDR_PUPD8_0
    -
    - -
    -
    - -

    ◆ GPIO_PUPDR_PUPDR8_1

    - -
    -
    - - - - -
    #define GPIO_PUPDR_PUPDR8_1   GPIO_PUPDR_PUPD8_1
    -
    - -
    -
    - -

    ◆ GPIO_PUPDR_PUPDR9

    - -
    -
    - - - - -
    #define GPIO_PUPDR_PUPDR9   GPIO_PUPDR_PUPD9
    -
    - -
    -
    - -

    ◆ GPIO_PUPDR_PUPDR9_0

    - -
    -
    - - - - -
    #define GPIO_PUPDR_PUPDR9_0   GPIO_PUPDR_PUPD9_0
    -
    - -
    -
    - -

    ◆ GPIO_PUPDR_PUPDR9_1

    - -
    -
    - - - - -
    #define GPIO_PUPDR_PUPDR9_1   GPIO_PUPDR_PUPD9_1
    -
    - -
    -
    - -

    ◆ GPIO_PUPDR_PUPDR10

    - -
    -
    - - - - -
    #define GPIO_PUPDR_PUPDR10   GPIO_PUPDR_PUPD10
    -
    - -
    -
    - -

    ◆ GPIO_PUPDR_PUPDR10_0

    - -
    -
    - - - - -
    #define GPIO_PUPDR_PUPDR10_0   GPIO_PUPDR_PUPD10_0
    -
    - -
    -
    - -

    ◆ GPIO_PUPDR_PUPDR10_1

    - -
    -
    - - - - -
    #define GPIO_PUPDR_PUPDR10_1   GPIO_PUPDR_PUPD10_1
    -
    - -
    -
    - -

    ◆ GPIO_PUPDR_PUPDR11

    - -
    -
    - - - - -
    #define GPIO_PUPDR_PUPDR11   GPIO_PUPDR_PUPD11
    -
    - -
    -
    - -

    ◆ GPIO_PUPDR_PUPDR11_0

    - -
    -
    - - - - -
    #define GPIO_PUPDR_PUPDR11_0   GPIO_PUPDR_PUPD11_0
    -
    - -
    -
    - -

    ◆ GPIO_PUPDR_PUPDR11_1

    - -
    -
    - - - - -
    #define GPIO_PUPDR_PUPDR11_1   GPIO_PUPDR_PUPD11_1
    -
    - -
    -
    - -

    ◆ GPIO_PUPDR_PUPDR12

    - -
    -
    - - - - -
    #define GPIO_PUPDR_PUPDR12   GPIO_PUPDR_PUPD12
    -
    - -
    -
    - -

    ◆ GPIO_PUPDR_PUPDR12_0

    - -
    -
    - - - - -
    #define GPIO_PUPDR_PUPDR12_0   GPIO_PUPDR_PUPD12_0
    -
    - -
    -
    - -

    ◆ GPIO_PUPDR_PUPDR12_1

    - -
    -
    - - - - -
    #define GPIO_PUPDR_PUPDR12_1   GPIO_PUPDR_PUPD12_1
    -
    - -
    -
    - -

    ◆ GPIO_PUPDR_PUPDR13

    - -
    -
    - - - - -
    #define GPIO_PUPDR_PUPDR13   GPIO_PUPDR_PUPD13
    -
    - -
    -
    - -

    ◆ GPIO_PUPDR_PUPDR13_0

    - -
    -
    - - - - -
    #define GPIO_PUPDR_PUPDR13_0   GPIO_PUPDR_PUPD13_0
    -
    - -
    -
    - -

    ◆ GPIO_PUPDR_PUPDR13_1

    - -
    -
    - - - - -
    #define GPIO_PUPDR_PUPDR13_1   GPIO_PUPDR_PUPD13_1
    -
    - -
    -
    - -

    ◆ GPIO_PUPDR_PUPDR14

    - -
    -
    - - - - -
    #define GPIO_PUPDR_PUPDR14   GPIO_PUPDR_PUPD14
    -
    - -
    -
    - -

    ◆ GPIO_PUPDR_PUPDR14_0

    - -
    -
    - - - - -
    #define GPIO_PUPDR_PUPDR14_0   GPIO_PUPDR_PUPD14_0
    -
    - -
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    ◆ GPIO_PUPDR_PUPDR14_1

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    #define GPIO_PUPDR_PUPDR14_1   GPIO_PUPDR_PUPD14_1
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    ◆ GPIO_PUPDR_PUPDR15

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    #define GPIO_PUPDR_PUPDR15   GPIO_PUPDR_PUPD15
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    ◆ GPIO_PUPDR_PUPDR15_0

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    #define GPIO_PUPDR_PUPDR15_0   GPIO_PUPDR_PUPD15_0
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    ◆ GPIO_PUPDR_PUPDR15_1

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    #define GPIO_PUPDR_PUPDR15_1   GPIO_PUPDR_PUPD15_1
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    ◆ GPIO_IDR_ID0_Pos

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    #define GPIO_IDR_ID0_Pos   (0U)
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    ◆ GPIO_IDR_ID0_Msk

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    #define GPIO_IDR_ID0_Msk   (0x1UL << GPIO_IDR_ID0_Pos)
    -
    -

    0x00000001

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    ◆ GPIO_IDR_ID0

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    #define GPIO_IDR_ID0   GPIO_IDR_ID0_Msk
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    ◆ GPIO_IDR_ID1_Pos

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    #define GPIO_IDR_ID1_Pos   (1U)
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    ◆ GPIO_IDR_ID1_Msk

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    #define GPIO_IDR_ID1_Msk   (0x1UL << GPIO_IDR_ID1_Pos)
    -
    -

    0x00000002

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    ◆ GPIO_IDR_ID1

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    #define GPIO_IDR_ID1   GPIO_IDR_ID1_Msk
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    ◆ GPIO_IDR_ID2_Pos

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    #define GPIO_IDR_ID2_Pos   (2U)
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    ◆ GPIO_IDR_ID2_Msk

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    #define GPIO_IDR_ID2_Msk   (0x1UL << GPIO_IDR_ID2_Pos)
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    0x00000004

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    ◆ GPIO_IDR_ID2

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    #define GPIO_IDR_ID2   GPIO_IDR_ID2_Msk
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    ◆ GPIO_IDR_ID3_Pos

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    #define GPIO_IDR_ID3_Pos   (3U)
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    ◆ GPIO_IDR_ID3_Msk

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    #define GPIO_IDR_ID3_Msk   (0x1UL << GPIO_IDR_ID3_Pos)
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    0x00000008

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    ◆ GPIO_IDR_ID3

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    #define GPIO_IDR_ID3   GPIO_IDR_ID3_Msk
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    ◆ GPIO_IDR_ID4_Pos

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    #define GPIO_IDR_ID4_Pos   (4U)
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    ◆ GPIO_IDR_ID4_Msk

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    #define GPIO_IDR_ID4_Msk   (0x1UL << GPIO_IDR_ID4_Pos)
    -
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    0x00000010

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    ◆ GPIO_IDR_ID4

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    #define GPIO_IDR_ID4   GPIO_IDR_ID4_Msk
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    ◆ GPIO_IDR_ID5_Pos

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    #define GPIO_IDR_ID5_Pos   (5U)
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    ◆ GPIO_IDR_ID5_Msk

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    #define GPIO_IDR_ID5_Msk   (0x1UL << GPIO_IDR_ID5_Pos)
    -
    -

    0x00000020

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    ◆ GPIO_IDR_ID5

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    #define GPIO_IDR_ID5   GPIO_IDR_ID5_Msk
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    ◆ GPIO_IDR_ID6_Pos

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    #define GPIO_IDR_ID6_Pos   (6U)
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    ◆ GPIO_IDR_ID6_Msk

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    #define GPIO_IDR_ID6_Msk   (0x1UL << GPIO_IDR_ID6_Pos)
    -
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    0x00000040

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    ◆ GPIO_IDR_ID6

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    #define GPIO_IDR_ID6   GPIO_IDR_ID6_Msk
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    ◆ GPIO_IDR_ID7_Pos

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    #define GPIO_IDR_ID7_Pos   (7U)
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    ◆ GPIO_IDR_ID7_Msk

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    #define GPIO_IDR_ID7_Msk   (0x1UL << GPIO_IDR_ID7_Pos)
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    -

    0x00000080

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    ◆ GPIO_IDR_ID7

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    #define GPIO_IDR_ID7   GPIO_IDR_ID7_Msk
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    ◆ GPIO_IDR_ID8_Pos

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    #define GPIO_IDR_ID8_Pos   (8U)
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    ◆ GPIO_IDR_ID8_Msk

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    #define GPIO_IDR_ID8_Msk   (0x1UL << GPIO_IDR_ID8_Pos)
    -
    -

    0x00000100

    - -
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    ◆ GPIO_IDR_ID8

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    #define GPIO_IDR_ID8   GPIO_IDR_ID8_Msk
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    ◆ GPIO_IDR_ID9_Pos

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    #define GPIO_IDR_ID9_Pos   (9U)
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    ◆ GPIO_IDR_ID9_Msk

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    #define GPIO_IDR_ID9_Msk   (0x1UL << GPIO_IDR_ID9_Pos)
    -
    -

    0x00000200

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    ◆ GPIO_IDR_ID9

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    #define GPIO_IDR_ID9   GPIO_IDR_ID9_Msk
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    ◆ GPIO_IDR_ID10_Pos

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    #define GPIO_IDR_ID10_Pos   (10U)
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    ◆ GPIO_IDR_ID10_Msk

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    #define GPIO_IDR_ID10_Msk   (0x1UL << GPIO_IDR_ID10_Pos)
    -
    -

    0x00000400

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    - -

    ◆ GPIO_IDR_ID10

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    #define GPIO_IDR_ID10   GPIO_IDR_ID10_Msk
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    ◆ GPIO_IDR_ID11_Pos

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    #define GPIO_IDR_ID11_Pos   (11U)
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    ◆ GPIO_IDR_ID11_Msk

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    #define GPIO_IDR_ID11_Msk   (0x1UL << GPIO_IDR_ID11_Pos)
    -
    -

    0x00000800

    - -
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    - -

    ◆ GPIO_IDR_ID11

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    #define GPIO_IDR_ID11   GPIO_IDR_ID11_Msk
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    ◆ GPIO_IDR_ID12_Pos

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    #define GPIO_IDR_ID12_Pos   (12U)
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    ◆ GPIO_IDR_ID12_Msk

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    #define GPIO_IDR_ID12_Msk   (0x1UL << GPIO_IDR_ID12_Pos)
    -
    -

    0x00001000

    - -
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    - -

    ◆ GPIO_IDR_ID12

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    #define GPIO_IDR_ID12   GPIO_IDR_ID12_Msk
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    ◆ GPIO_IDR_ID13_Pos

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    #define GPIO_IDR_ID13_Pos   (13U)
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    ◆ GPIO_IDR_ID13_Msk

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    #define GPIO_IDR_ID13_Msk   (0x1UL << GPIO_IDR_ID13_Pos)
    -
    -

    0x00002000

    - -
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    ◆ GPIO_IDR_ID13

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    #define GPIO_IDR_ID13   GPIO_IDR_ID13_Msk
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    ◆ GPIO_IDR_ID14_Pos

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    #define GPIO_IDR_ID14_Pos   (14U)
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    ◆ GPIO_IDR_ID14_Msk

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    #define GPIO_IDR_ID14_Msk   (0x1UL << GPIO_IDR_ID14_Pos)
    -
    -

    0x00004000

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    ◆ GPIO_IDR_ID14

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    #define GPIO_IDR_ID14   GPIO_IDR_ID14_Msk
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    ◆ GPIO_IDR_ID15_Pos

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    #define GPIO_IDR_ID15_Pos   (15U)
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    ◆ GPIO_IDR_ID15_Msk

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    #define GPIO_IDR_ID15_Msk   (0x1UL << GPIO_IDR_ID15_Pos)
    -
    -

    0x00008000

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    ◆ GPIO_IDR_ID15

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    #define GPIO_IDR_ID15   GPIO_IDR_ID15_Msk
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    ◆ GPIO_IDR_IDR_0

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    #define GPIO_IDR_IDR_0   GPIO_IDR_ID0
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    ◆ GPIO_IDR_IDR_1

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    #define GPIO_IDR_IDR_1   GPIO_IDR_ID1
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    ◆ GPIO_IDR_IDR_2

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    #define GPIO_IDR_IDR_2   GPIO_IDR_ID2
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    ◆ GPIO_IDR_IDR_3

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    #define GPIO_IDR_IDR_3   GPIO_IDR_ID3
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    ◆ GPIO_IDR_IDR_4

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    #define GPIO_IDR_IDR_4   GPIO_IDR_ID4
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    ◆ GPIO_IDR_IDR_5

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    #define GPIO_IDR_IDR_5   GPIO_IDR_ID5
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    ◆ GPIO_IDR_IDR_6

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    #define GPIO_IDR_IDR_6   GPIO_IDR_ID6
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    ◆ GPIO_IDR_IDR_7

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    #define GPIO_IDR_IDR_7   GPIO_IDR_ID7
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    ◆ GPIO_IDR_IDR_8

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    #define GPIO_IDR_IDR_8   GPIO_IDR_ID8
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    ◆ GPIO_IDR_IDR_9

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    #define GPIO_IDR_IDR_9   GPIO_IDR_ID9
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    ◆ GPIO_IDR_IDR_10

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    #define GPIO_IDR_IDR_10   GPIO_IDR_ID10
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    ◆ GPIO_IDR_IDR_11

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    #define GPIO_IDR_IDR_11   GPIO_IDR_ID11
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    ◆ GPIO_IDR_IDR_12

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    #define GPIO_IDR_IDR_12   GPIO_IDR_ID12
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    ◆ GPIO_IDR_IDR_13

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    #define GPIO_IDR_IDR_13   GPIO_IDR_ID13
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    ◆ GPIO_IDR_IDR_14

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    #define GPIO_IDR_IDR_14   GPIO_IDR_ID14
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    ◆ GPIO_IDR_IDR_15

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    #define GPIO_IDR_IDR_15   GPIO_IDR_ID15
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    ◆ GPIO_ODR_OD0_Pos

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    #define GPIO_ODR_OD0_Pos   (0U)
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    ◆ GPIO_ODR_OD0_Msk

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    #define GPIO_ODR_OD0_Msk   (0x1UL << GPIO_ODR_OD0_Pos)
    -
    -

    0x00000001

    - -
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    ◆ GPIO_ODR_OD0

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    #define GPIO_ODR_OD0   GPIO_ODR_OD0_Msk
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    ◆ GPIO_ODR_OD1_Pos

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    #define GPIO_ODR_OD1_Pos   (1U)
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    ◆ GPIO_ODR_OD1_Msk

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    #define GPIO_ODR_OD1_Msk   (0x1UL << GPIO_ODR_OD1_Pos)
    -
    -

    0x00000002

    - -
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    ◆ GPIO_ODR_OD1

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    #define GPIO_ODR_OD1   GPIO_ODR_OD1_Msk
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    ◆ GPIO_ODR_OD2_Pos

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    #define GPIO_ODR_OD2_Pos   (2U)
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    ◆ GPIO_ODR_OD2_Msk

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    #define GPIO_ODR_OD2_Msk   (0x1UL << GPIO_ODR_OD2_Pos)
    -
    -

    0x00000004

    - -
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    ◆ GPIO_ODR_OD2

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    #define GPIO_ODR_OD2   GPIO_ODR_OD2_Msk
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    ◆ GPIO_ODR_OD3_Pos

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    #define GPIO_ODR_OD3_Pos   (3U)
    -
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    ◆ GPIO_ODR_OD3_Msk

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    #define GPIO_ODR_OD3_Msk   (0x1UL << GPIO_ODR_OD3_Pos)
    -
    -

    0x00000008

    - -
    -
    - -

    ◆ GPIO_ODR_OD3

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    #define GPIO_ODR_OD3   GPIO_ODR_OD3_Msk
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    ◆ GPIO_ODR_OD4_Pos

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    #define GPIO_ODR_OD4_Pos   (4U)
    -
    - -
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    ◆ GPIO_ODR_OD4_Msk

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    #define GPIO_ODR_OD4_Msk   (0x1UL << GPIO_ODR_OD4_Pos)
    -
    -

    0x00000010

    - -
    -
    - -

    ◆ GPIO_ODR_OD4

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    #define GPIO_ODR_OD4   GPIO_ODR_OD4_Msk
    -
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    ◆ GPIO_ODR_OD5_Pos

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    #define GPIO_ODR_OD5_Pos   (5U)
    -
    - -
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    - -

    ◆ GPIO_ODR_OD5_Msk

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    #define GPIO_ODR_OD5_Msk   (0x1UL << GPIO_ODR_OD5_Pos)
    -
    -

    0x00000020

    - -
    -
    - -

    ◆ GPIO_ODR_OD5

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    #define GPIO_ODR_OD5   GPIO_ODR_OD5_Msk
    -
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    ◆ GPIO_ODR_OD6_Pos

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    #define GPIO_ODR_OD6_Pos   (6U)
    -
    - -
    -
    - -

    ◆ GPIO_ODR_OD6_Msk

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    #define GPIO_ODR_OD6_Msk   (0x1UL << GPIO_ODR_OD6_Pos)
    -
    -

    0x00000040

    - -
    -
    - -

    ◆ GPIO_ODR_OD6

    - -
    -
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    #define GPIO_ODR_OD6   GPIO_ODR_OD6_Msk
    -
    - -
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    ◆ GPIO_ODR_OD7_Pos

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    #define GPIO_ODR_OD7_Pos   (7U)
    -
    - -
    -
    - -

    ◆ GPIO_ODR_OD7_Msk

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    #define GPIO_ODR_OD7_Msk   (0x1UL << GPIO_ODR_OD7_Pos)
    -
    -

    0x00000080

    - -
    -
    - -

    ◆ GPIO_ODR_OD7

    - -
    -
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    #define GPIO_ODR_OD7   GPIO_ODR_OD7_Msk
    -
    - -
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    - -

    ◆ GPIO_ODR_OD8_Pos

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    #define GPIO_ODR_OD8_Pos   (8U)
    -
    - -
    -
    - -

    ◆ GPIO_ODR_OD8_Msk

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    #define GPIO_ODR_OD8_Msk   (0x1UL << GPIO_ODR_OD8_Pos)
    -
    -

    0x00000100

    - -
    -
    - -

    ◆ GPIO_ODR_OD8

    - -
    -
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    #define GPIO_ODR_OD8   GPIO_ODR_OD8_Msk
    -
    - -
    -
    - -

    ◆ GPIO_ODR_OD9_Pos

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    #define GPIO_ODR_OD9_Pos   (9U)
    -
    - -
    -
    - -

    ◆ GPIO_ODR_OD9_Msk

    - -
    -
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    #define GPIO_ODR_OD9_Msk   (0x1UL << GPIO_ODR_OD9_Pos)
    -
    -

    0x00000200

    - -
    -
    - -

    ◆ GPIO_ODR_OD9

    - -
    -
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    #define GPIO_ODR_OD9   GPIO_ODR_OD9_Msk
    -
    - -
    -
    - -

    ◆ GPIO_ODR_OD10_Pos

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    #define GPIO_ODR_OD10_Pos   (10U)
    -
    - -
    -
    - -

    ◆ GPIO_ODR_OD10_Msk

    - -
    -
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    #define GPIO_ODR_OD10_Msk   (0x1UL << GPIO_ODR_OD10_Pos)
    -
    -

    0x00000400

    - -
    -
    - -

    ◆ GPIO_ODR_OD10

    - -
    -
    - - - - -
    #define GPIO_ODR_OD10   GPIO_ODR_OD10_Msk
    -
    - -
    -
    - -

    ◆ GPIO_ODR_OD11_Pos

    - -
    -
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    #define GPIO_ODR_OD11_Pos   (11U)
    -
    - -
    -
    - -

    ◆ GPIO_ODR_OD11_Msk

    - -
    -
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    #define GPIO_ODR_OD11_Msk   (0x1UL << GPIO_ODR_OD11_Pos)
    -
    -

    0x00000800

    - -
    -
    - -

    ◆ GPIO_ODR_OD11

    - -
    -
    - - - - -
    #define GPIO_ODR_OD11   GPIO_ODR_OD11_Msk
    -
    - -
    -
    - -

    ◆ GPIO_ODR_OD12_Pos

    - -
    -
    - - - - -
    #define GPIO_ODR_OD12_Pos   (12U)
    -
    - -
    -
    - -

    ◆ GPIO_ODR_OD12_Msk

    - -
    -
    - - - - -
    #define GPIO_ODR_OD12_Msk   (0x1UL << GPIO_ODR_OD12_Pos)
    -
    -

    0x00001000

    - -
    -
    - -

    ◆ GPIO_ODR_OD12

    - -
    -
    - - - - -
    #define GPIO_ODR_OD12   GPIO_ODR_OD12_Msk
    -
    - -
    -
    - -

    ◆ GPIO_ODR_OD13_Pos

    - -
    -
    - - - - -
    #define GPIO_ODR_OD13_Pos   (13U)
    -
    - -
    -
    - -

    ◆ GPIO_ODR_OD13_Msk

    - -
    -
    - - - - -
    #define GPIO_ODR_OD13_Msk   (0x1UL << GPIO_ODR_OD13_Pos)
    -
    -

    0x00002000

    - -
    -
    - -

    ◆ GPIO_ODR_OD13

    - -
    -
    - - - - -
    #define GPIO_ODR_OD13   GPIO_ODR_OD13_Msk
    -
    - -
    -
    - -

    ◆ GPIO_ODR_OD14_Pos

    - -
    -
    - - - - -
    #define GPIO_ODR_OD14_Pos   (14U)
    -
    - -
    -
    - -

    ◆ GPIO_ODR_OD14_Msk

    - -
    -
    - - - - -
    #define GPIO_ODR_OD14_Msk   (0x1UL << GPIO_ODR_OD14_Pos)
    -
    -

    0x00004000

    - -
    -
    - -

    ◆ GPIO_ODR_OD14

    - -
    -
    - - - - -
    #define GPIO_ODR_OD14   GPIO_ODR_OD14_Msk
    -
    - -
    -
    - -

    ◆ GPIO_ODR_OD15_Pos

    - -
    -
    - - - - -
    #define GPIO_ODR_OD15_Pos   (15U)
    -
    - -
    -
    - -

    ◆ GPIO_ODR_OD15_Msk

    - -
    -
    - - - - -
    #define GPIO_ODR_OD15_Msk   (0x1UL << GPIO_ODR_OD15_Pos)
    -
    -

    0x00008000

    - -
    -
    - -

    ◆ GPIO_ODR_OD15

    - -
    -
    - - - - -
    #define GPIO_ODR_OD15   GPIO_ODR_OD15_Msk
    -
    - -
    -
    - -

    ◆ GPIO_ODR_ODR_0

    - -
    -
    - - - - -
    #define GPIO_ODR_ODR_0   GPIO_ODR_OD0
    -
    - -
    -
    - -

    ◆ GPIO_ODR_ODR_1

    - -
    -
    - - - - -
    #define GPIO_ODR_ODR_1   GPIO_ODR_OD1
    -
    - -
    -
    - -

    ◆ GPIO_ODR_ODR_2

    - -
    -
    - - - - -
    #define GPIO_ODR_ODR_2   GPIO_ODR_OD2
    -
    - -
    -
    - -

    ◆ GPIO_ODR_ODR_3

    - -
    -
    - - - - -
    #define GPIO_ODR_ODR_3   GPIO_ODR_OD3
    -
    - -
    -
    - -

    ◆ GPIO_ODR_ODR_4

    - -
    -
    - - - - -
    #define GPIO_ODR_ODR_4   GPIO_ODR_OD4
    -
    - -
    -
    - -

    ◆ GPIO_ODR_ODR_5

    - -
    -
    - - - - -
    #define GPIO_ODR_ODR_5   GPIO_ODR_OD5
    -
    - -
    -
    - -

    ◆ GPIO_ODR_ODR_6

    - -
    -
    - - - - -
    #define GPIO_ODR_ODR_6   GPIO_ODR_OD6
    -
    - -
    -
    - -

    ◆ GPIO_ODR_ODR_7

    - -
    -
    - - - - -
    #define GPIO_ODR_ODR_7   GPIO_ODR_OD7
    -
    - -
    -
    - -

    ◆ GPIO_ODR_ODR_8

    - -
    -
    - - - - -
    #define GPIO_ODR_ODR_8   GPIO_ODR_OD8
    -
    - -
    -
    - -

    ◆ GPIO_ODR_ODR_9

    - -
    -
    - - - - -
    #define GPIO_ODR_ODR_9   GPIO_ODR_OD9
    -
    - -
    -
    - -

    ◆ GPIO_ODR_ODR_10

    - -
    -
    - - - - -
    #define GPIO_ODR_ODR_10   GPIO_ODR_OD10
    -
    - -
    -
    - -

    ◆ GPIO_ODR_ODR_11

    - -
    -
    - - - - -
    #define GPIO_ODR_ODR_11   GPIO_ODR_OD11
    -
    - -
    -
    - -

    ◆ GPIO_ODR_ODR_12

    - -
    -
    - - - - -
    #define GPIO_ODR_ODR_12   GPIO_ODR_OD12
    -
    - -
    -
    - -

    ◆ GPIO_ODR_ODR_13

    - -
    -
    - - - - -
    #define GPIO_ODR_ODR_13   GPIO_ODR_OD13
    -
    - -
    -
    - -

    ◆ GPIO_ODR_ODR_14

    - -
    -
    - - - - -
    #define GPIO_ODR_ODR_14   GPIO_ODR_OD14
    -
    - -
    -
    - -

    ◆ GPIO_ODR_ODR_15

    - -
    -
    - - - - -
    #define GPIO_ODR_ODR_15   GPIO_ODR_OD15
    -
    - -
    -
    - -

    ◆ GPIO_BSRR_BS0_Pos

    - -
    -
    - - - - -
    #define GPIO_BSRR_BS0_Pos   (0U)
    -
    - -
    -
    - -

    ◆ GPIO_BSRR_BS0_Msk

    - -
    -
    - - - - -
    #define GPIO_BSRR_BS0_Msk   (0x1UL << GPIO_BSRR_BS0_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ GPIO_BSRR_BS0

    - -
    -
    - - - - -
    #define GPIO_BSRR_BS0   GPIO_BSRR_BS0_Msk
    -
    - -
    -
    - -

    ◆ GPIO_BSRR_BS1_Pos

    - -
    -
    - - - - -
    #define GPIO_BSRR_BS1_Pos   (1U)
    -
    - -
    -
    - -

    ◆ GPIO_BSRR_BS1_Msk

    - -
    -
    - - - - -
    #define GPIO_BSRR_BS1_Msk   (0x1UL << GPIO_BSRR_BS1_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ GPIO_BSRR_BS1

    - -
    -
    - - - - -
    #define GPIO_BSRR_BS1   GPIO_BSRR_BS1_Msk
    -
    - -
    -
    - -

    ◆ GPIO_BSRR_BS2_Pos

    - -
    -
    - - - - -
    #define GPIO_BSRR_BS2_Pos   (2U)
    -
    - -
    -
    - -

    ◆ GPIO_BSRR_BS2_Msk

    - -
    -
    - - - - -
    #define GPIO_BSRR_BS2_Msk   (0x1UL << GPIO_BSRR_BS2_Pos)
    -
    -

    0x00000004

    - -
    -
    - -

    ◆ GPIO_BSRR_BS2

    - -
    -
    - - - - -
    #define GPIO_BSRR_BS2   GPIO_BSRR_BS2_Msk
    -
    - -
    -
    - -

    ◆ GPIO_BSRR_BS3_Pos

    - -
    -
    - - - - -
    #define GPIO_BSRR_BS3_Pos   (3U)
    -
    - -
    -
    - -

    ◆ GPIO_BSRR_BS3_Msk

    - -
    -
    - - - - -
    #define GPIO_BSRR_BS3_Msk   (0x1UL << GPIO_BSRR_BS3_Pos)
    -
    -

    0x00000008

    - -
    -
    - -

    ◆ GPIO_BSRR_BS3

    - -
    -
    - - - - -
    #define GPIO_BSRR_BS3   GPIO_BSRR_BS3_Msk
    -
    - -
    -
    - -

    ◆ GPIO_BSRR_BS4_Pos

    - -
    -
    - - - - -
    #define GPIO_BSRR_BS4_Pos   (4U)
    -
    - -
    -
    - -

    ◆ GPIO_BSRR_BS4_Msk

    - -
    -
    - - - - -
    #define GPIO_BSRR_BS4_Msk   (0x1UL << GPIO_BSRR_BS4_Pos)
    -
    -

    0x00000010

    - -
    -
    - -

    ◆ GPIO_BSRR_BS4

    - -
    -
    - - - - -
    #define GPIO_BSRR_BS4   GPIO_BSRR_BS4_Msk
    -
    - -
    -
    - -

    ◆ GPIO_BSRR_BS5_Pos

    - -
    -
    - - - - -
    #define GPIO_BSRR_BS5_Pos   (5U)
    -
    - -
    -
    - -

    ◆ GPIO_BSRR_BS5_Msk

    - -
    -
    - - - - -
    #define GPIO_BSRR_BS5_Msk   (0x1UL << GPIO_BSRR_BS5_Pos)
    -
    -

    0x00000020

    - -
    -
    - -

    ◆ GPIO_BSRR_BS5

    - -
    -
    - - - - -
    #define GPIO_BSRR_BS5   GPIO_BSRR_BS5_Msk
    -
    - -
    -
    - -

    ◆ GPIO_BSRR_BS6_Pos

    - -
    -
    - - - - -
    #define GPIO_BSRR_BS6_Pos   (6U)
    -
    - -
    -
    - -

    ◆ GPIO_BSRR_BS6_Msk

    - -
    -
    - - - - -
    #define GPIO_BSRR_BS6_Msk   (0x1UL << GPIO_BSRR_BS6_Pos)
    -
    -

    0x00000040

    - -
    -
    - -

    ◆ GPIO_BSRR_BS6

    - -
    -
    - - - - -
    #define GPIO_BSRR_BS6   GPIO_BSRR_BS6_Msk
    -
    - -
    -
    - -

    ◆ GPIO_BSRR_BS7_Pos

    - -
    -
    - - - - -
    #define GPIO_BSRR_BS7_Pos   (7U)
    -
    - -
    -
    - -

    ◆ GPIO_BSRR_BS7_Msk

    - -
    -
    - - - - -
    #define GPIO_BSRR_BS7_Msk   (0x1UL << GPIO_BSRR_BS7_Pos)
    -
    -

    0x00000080

    - -
    -
    - -

    ◆ GPIO_BSRR_BS7

    - -
    -
    - - - - -
    #define GPIO_BSRR_BS7   GPIO_BSRR_BS7_Msk
    -
    - -
    -
    - -

    ◆ GPIO_BSRR_BS8_Pos

    - -
    -
    - - - - -
    #define GPIO_BSRR_BS8_Pos   (8U)
    -
    - -
    -
    - -

    ◆ GPIO_BSRR_BS8_Msk

    - -
    -
    - - - - -
    #define GPIO_BSRR_BS8_Msk   (0x1UL << GPIO_BSRR_BS8_Pos)
    -
    -

    0x00000100

    - -
    -
    - -

    ◆ GPIO_BSRR_BS8

    - -
    -
    - - - - -
    #define GPIO_BSRR_BS8   GPIO_BSRR_BS8_Msk
    -
    - -
    -
    - -

    ◆ GPIO_BSRR_BS9_Pos

    - -
    -
    - - - - -
    #define GPIO_BSRR_BS9_Pos   (9U)
    -
    - -
    -
    - -

    ◆ GPIO_BSRR_BS9_Msk

    - -
    -
    - - - - -
    #define GPIO_BSRR_BS9_Msk   (0x1UL << GPIO_BSRR_BS9_Pos)
    -
    -

    0x00000200

    - -
    -
    - -

    ◆ GPIO_BSRR_BS9

    - -
    -
    - - - - -
    #define GPIO_BSRR_BS9   GPIO_BSRR_BS9_Msk
    -
    - -
    -
    - -

    ◆ GPIO_BSRR_BS10_Pos

    - -
    -
    - - - - -
    #define GPIO_BSRR_BS10_Pos   (10U)
    -
    - -
    -
    - -

    ◆ GPIO_BSRR_BS10_Msk

    - -
    -
    - - - - -
    #define GPIO_BSRR_BS10_Msk   (0x1UL << GPIO_BSRR_BS10_Pos)
    -
    -

    0x00000400

    - -
    -
    - -

    ◆ GPIO_BSRR_BS10

    - -
    -
    - - - - -
    #define GPIO_BSRR_BS10   GPIO_BSRR_BS10_Msk
    -
    - -
    -
    - -

    ◆ GPIO_BSRR_BS11_Pos

    - -
    -
    - - - - -
    #define GPIO_BSRR_BS11_Pos   (11U)
    -
    - -
    -
    - -

    ◆ GPIO_BSRR_BS11_Msk

    - -
    -
    - - - - -
    #define GPIO_BSRR_BS11_Msk   (0x1UL << GPIO_BSRR_BS11_Pos)
    -
    -

    0x00000800

    - -
    -
    - -

    ◆ GPIO_BSRR_BS11

    - -
    -
    - - - - -
    #define GPIO_BSRR_BS11   GPIO_BSRR_BS11_Msk
    -
    - -
    -
    - -

    ◆ GPIO_BSRR_BS12_Pos

    - -
    -
    - - - - -
    #define GPIO_BSRR_BS12_Pos   (12U)
    -
    - -
    -
    - -

    ◆ GPIO_BSRR_BS12_Msk

    - -
    -
    - - - - -
    #define GPIO_BSRR_BS12_Msk   (0x1UL << GPIO_BSRR_BS12_Pos)
    -
    -

    0x00001000

    - -
    -
    - -

    ◆ GPIO_BSRR_BS12

    - -
    -
    - - - - -
    #define GPIO_BSRR_BS12   GPIO_BSRR_BS12_Msk
    -
    - -
    -
    - -

    ◆ GPIO_BSRR_BS13_Pos

    - -
    -
    - - - - -
    #define GPIO_BSRR_BS13_Pos   (13U)
    -
    - -
    -
    - -

    ◆ GPIO_BSRR_BS13_Msk

    - -
    -
    - - - - -
    #define GPIO_BSRR_BS13_Msk   (0x1UL << GPIO_BSRR_BS13_Pos)
    -
    -

    0x00002000

    - -
    -
    - -

    ◆ GPIO_BSRR_BS13

    - -
    -
    - - - - -
    #define GPIO_BSRR_BS13   GPIO_BSRR_BS13_Msk
    -
    - -
    -
    - -

    ◆ GPIO_BSRR_BS14_Pos

    - -
    -
    - - - - -
    #define GPIO_BSRR_BS14_Pos   (14U)
    -
    - -
    -
    - -

    ◆ GPIO_BSRR_BS14_Msk

    - -
    -
    - - - - -
    #define GPIO_BSRR_BS14_Msk   (0x1UL << GPIO_BSRR_BS14_Pos)
    -
    -

    0x00004000

    - -
    -
    - -

    ◆ GPIO_BSRR_BS14

    - -
    -
    - - - - -
    #define GPIO_BSRR_BS14   GPIO_BSRR_BS14_Msk
    -
    - -
    -
    - -

    ◆ GPIO_BSRR_BS15_Pos

    - -
    -
    - - - - -
    #define GPIO_BSRR_BS15_Pos   (15U)
    -
    - -
    -
    - -

    ◆ GPIO_BSRR_BS15_Msk

    - -
    -
    - - - - -
    #define GPIO_BSRR_BS15_Msk   (0x1UL << GPIO_BSRR_BS15_Pos)
    -
    -

    0x00008000

    - -
    -
    - -

    ◆ GPIO_BSRR_BS15

    - -
    -
    - - - - -
    #define GPIO_BSRR_BS15   GPIO_BSRR_BS15_Msk
    -
    - -
    -
    - -

    ◆ GPIO_BSRR_BR0_Pos

    - -
    -
    - - - - -
    #define GPIO_BSRR_BR0_Pos   (16U)
    -
    - -
    -
    - -

    ◆ GPIO_BSRR_BR0_Msk

    - -
    -
    - - - - -
    #define GPIO_BSRR_BR0_Msk   (0x1UL << GPIO_BSRR_BR0_Pos)
    -
    -

    0x00010000

    - -
    -
    - -

    ◆ GPIO_BSRR_BR0

    - -
    -
    - - - - -
    #define GPIO_BSRR_BR0   GPIO_BSRR_BR0_Msk
    -
    - -
    -
    - -

    ◆ GPIO_BSRR_BR1_Pos

    - -
    -
    - - - - -
    #define GPIO_BSRR_BR1_Pos   (17U)
    -
    - -
    -
    - -

    ◆ GPIO_BSRR_BR1_Msk

    - -
    -
    - - - - -
    #define GPIO_BSRR_BR1_Msk   (0x1UL << GPIO_BSRR_BR1_Pos)
    -
    -

    0x00020000

    - -
    -
    - -

    ◆ GPIO_BSRR_BR1

    - -
    -
    - - - - -
    #define GPIO_BSRR_BR1   GPIO_BSRR_BR1_Msk
    -
    - -
    -
    - -

    ◆ GPIO_BSRR_BR2_Pos

    - -
    -
    - - - - -
    #define GPIO_BSRR_BR2_Pos   (18U)
    -
    - -
    -
    - -

    ◆ GPIO_BSRR_BR2_Msk

    - -
    -
    - - - - -
    #define GPIO_BSRR_BR2_Msk   (0x1UL << GPIO_BSRR_BR2_Pos)
    -
    -

    0x00040000

    - -
    -
    - -

    ◆ GPIO_BSRR_BR2

    - -
    -
    - - - - -
    #define GPIO_BSRR_BR2   GPIO_BSRR_BR2_Msk
    -
    - -
    -
    - -

    ◆ GPIO_BSRR_BR3_Pos

    - -
    -
    - - - - -
    #define GPIO_BSRR_BR3_Pos   (19U)
    -
    - -
    -
    - -

    ◆ GPIO_BSRR_BR3_Msk

    - -
    -
    - - - - -
    #define GPIO_BSRR_BR3_Msk   (0x1UL << GPIO_BSRR_BR3_Pos)
    -
    -

    0x00080000

    - -
    -
    - -

    ◆ GPIO_BSRR_BR3

    - -
    -
    - - - - -
    #define GPIO_BSRR_BR3   GPIO_BSRR_BR3_Msk
    -
    - -
    -
    - -

    ◆ GPIO_BSRR_BR4_Pos

    - -
    -
    - - - - -
    #define GPIO_BSRR_BR4_Pos   (20U)
    -
    - -
    -
    - -

    ◆ GPIO_BSRR_BR4_Msk

    - -
    -
    - - - - -
    #define GPIO_BSRR_BR4_Msk   (0x1UL << GPIO_BSRR_BR4_Pos)
    -
    -

    0x00100000

    - -
    -
    - -

    ◆ GPIO_BSRR_BR4

    - -
    -
    - - - - -
    #define GPIO_BSRR_BR4   GPIO_BSRR_BR4_Msk
    -
    - -
    -
    - -

    ◆ GPIO_BSRR_BR5_Pos

    - -
    -
    - - - - -
    #define GPIO_BSRR_BR5_Pos   (21U)
    -
    - -
    -
    - -

    ◆ GPIO_BSRR_BR5_Msk

    - -
    -
    - - - - -
    #define GPIO_BSRR_BR5_Msk   (0x1UL << GPIO_BSRR_BR5_Pos)
    -
    -

    0x00200000

    - -
    -
    - -

    ◆ GPIO_BSRR_BR5

    - -
    -
    - - - - -
    #define GPIO_BSRR_BR5   GPIO_BSRR_BR5_Msk
    -
    - -
    -
    - -

    ◆ GPIO_BSRR_BR6_Pos

    - -
    -
    - - - - -
    #define GPIO_BSRR_BR6_Pos   (22U)
    -
    - -
    -
    - -

    ◆ GPIO_BSRR_BR6_Msk

    - -
    -
    - - - - -
    #define GPIO_BSRR_BR6_Msk   (0x1UL << GPIO_BSRR_BR6_Pos)
    -
    -

    0x00400000

    - -
    -
    - -

    ◆ GPIO_BSRR_BR6

    - -
    -
    - - - - -
    #define GPIO_BSRR_BR6   GPIO_BSRR_BR6_Msk
    -
    - -
    -
    - -

    ◆ GPIO_BSRR_BR7_Pos

    - -
    -
    - - - - -
    #define GPIO_BSRR_BR7_Pos   (23U)
    -
    - -
    -
    - -

    ◆ GPIO_BSRR_BR7_Msk

    - -
    -
    - - - - -
    #define GPIO_BSRR_BR7_Msk   (0x1UL << GPIO_BSRR_BR7_Pos)
    -
    -

    0x00800000

    - -
    -
    - -

    ◆ GPIO_BSRR_BR7

    - -
    -
    - - - - -
    #define GPIO_BSRR_BR7   GPIO_BSRR_BR7_Msk
    -
    - -
    -
    - -

    ◆ GPIO_BSRR_BR8_Pos

    - -
    -
    - - - - -
    #define GPIO_BSRR_BR8_Pos   (24U)
    -
    - -
    -
    - -

    ◆ GPIO_BSRR_BR8_Msk

    - -
    -
    - - - - -
    #define GPIO_BSRR_BR8_Msk   (0x1UL << GPIO_BSRR_BR8_Pos)
    -
    -

    0x01000000

    - -
    -
    - -

    ◆ GPIO_BSRR_BR8

    - -
    -
    - - - - -
    #define GPIO_BSRR_BR8   GPIO_BSRR_BR8_Msk
    -
    - -
    -
    - -

    ◆ GPIO_BSRR_BR9_Pos

    - -
    -
    - - - - -
    #define GPIO_BSRR_BR9_Pos   (25U)
    -
    - -
    -
    - -

    ◆ GPIO_BSRR_BR9_Msk

    - -
    -
    - - - - -
    #define GPIO_BSRR_BR9_Msk   (0x1UL << GPIO_BSRR_BR9_Pos)
    -
    -

    0x02000000

    - -
    -
    - -

    ◆ GPIO_BSRR_BR9

    - -
    -
    - - - - -
    #define GPIO_BSRR_BR9   GPIO_BSRR_BR9_Msk
    -
    - -
    -
    - -

    ◆ GPIO_BSRR_BR10_Pos

    - -
    -
    - - - - -
    #define GPIO_BSRR_BR10_Pos   (26U)
    -
    - -
    -
    - -

    ◆ GPIO_BSRR_BR10_Msk

    - -
    -
    - - - - -
    #define GPIO_BSRR_BR10_Msk   (0x1UL << GPIO_BSRR_BR10_Pos)
    -
    -

    0x04000000

    - -
    -
    - -

    ◆ GPIO_BSRR_BR10

    - -
    -
    - - - - -
    #define GPIO_BSRR_BR10   GPIO_BSRR_BR10_Msk
    -
    - -
    -
    - -

    ◆ GPIO_BSRR_BR11_Pos

    - -
    -
    - - - - -
    #define GPIO_BSRR_BR11_Pos   (27U)
    -
    - -
    -
    - -

    ◆ GPIO_BSRR_BR11_Msk

    - -
    -
    - - - - -
    #define GPIO_BSRR_BR11_Msk   (0x1UL << GPIO_BSRR_BR11_Pos)
    -
    -

    0x08000000

    - -
    -
    - -

    ◆ GPIO_BSRR_BR11

    - -
    -
    - - - - -
    #define GPIO_BSRR_BR11   GPIO_BSRR_BR11_Msk
    -
    - -
    -
    - -

    ◆ GPIO_BSRR_BR12_Pos

    - -
    -
    - - - - -
    #define GPIO_BSRR_BR12_Pos   (28U)
    -
    - -
    -
    - -

    ◆ GPIO_BSRR_BR12_Msk

    - -
    -
    - - - - -
    #define GPIO_BSRR_BR12_Msk   (0x1UL << GPIO_BSRR_BR12_Pos)
    -
    -

    0x10000000

    - -
    -
    - -

    ◆ GPIO_BSRR_BR12

    - -
    -
    - - - - -
    #define GPIO_BSRR_BR12   GPIO_BSRR_BR12_Msk
    -
    - -
    -
    - -

    ◆ GPIO_BSRR_BR13_Pos

    - -
    -
    - - - - -
    #define GPIO_BSRR_BR13_Pos   (29U)
    -
    - -
    -
    - -

    ◆ GPIO_BSRR_BR13_Msk

    - -
    -
    - - - - -
    #define GPIO_BSRR_BR13_Msk   (0x1UL << GPIO_BSRR_BR13_Pos)
    -
    -

    0x20000000

    - -
    -
    - -

    ◆ GPIO_BSRR_BR13

    - -
    -
    - - - - -
    #define GPIO_BSRR_BR13   GPIO_BSRR_BR13_Msk
    -
    - -
    -
    - -

    ◆ GPIO_BSRR_BR14_Pos

    - -
    -
    - - - - -
    #define GPIO_BSRR_BR14_Pos   (30U)
    -
    - -
    -
    - -

    ◆ GPIO_BSRR_BR14_Msk

    - -
    -
    - - - - -
    #define GPIO_BSRR_BR14_Msk   (0x1UL << GPIO_BSRR_BR14_Pos)
    -
    -

    0x40000000

    - -
    -
    - -

    ◆ GPIO_BSRR_BR14

    - -
    -
    - - - - -
    #define GPIO_BSRR_BR14   GPIO_BSRR_BR14_Msk
    -
    - -
    -
    - -

    ◆ GPIO_BSRR_BR15_Pos

    - -
    -
    - - - - -
    #define GPIO_BSRR_BR15_Pos   (31U)
    -
    - -
    -
    - -

    ◆ GPIO_BSRR_BR15_Msk

    - -
    -
    - - - - -
    #define GPIO_BSRR_BR15_Msk   (0x1UL << GPIO_BSRR_BR15_Pos)
    -
    -

    0x80000000

    - -
    -
    - -

    ◆ GPIO_BSRR_BR15

    - -
    -
    - - - - -
    #define GPIO_BSRR_BR15   GPIO_BSRR_BR15_Msk
    -
    - -
    -
    - -

    ◆ GPIO_BSRR_BS_0

    - -
    -
    - - - - -
    #define GPIO_BSRR_BS_0   GPIO_BSRR_BS0
    -
    - -
    -
    - -

    ◆ GPIO_BSRR_BS_1

    - -
    -
    - - - - -
    #define GPIO_BSRR_BS_1   GPIO_BSRR_BS1
    -
    - -
    -
    - -

    ◆ GPIO_BSRR_BS_2

    - -
    -
    - - - - -
    #define GPIO_BSRR_BS_2   GPIO_BSRR_BS2
    -
    - -
    -
    - -

    ◆ GPIO_BSRR_BS_3

    - -
    -
    - - - - -
    #define GPIO_BSRR_BS_3   GPIO_BSRR_BS3
    -
    - -
    -
    - -

    ◆ GPIO_BSRR_BS_4

    - -
    -
    - - - - -
    #define GPIO_BSRR_BS_4   GPIO_BSRR_BS4
    -
    - -
    -
    - -

    ◆ GPIO_BSRR_BS_5

    - -
    -
    - - - - -
    #define GPIO_BSRR_BS_5   GPIO_BSRR_BS5
    -
    - -
    -
    - -

    ◆ GPIO_BSRR_BS_6

    - -
    -
    - - - - -
    #define GPIO_BSRR_BS_6   GPIO_BSRR_BS6
    -
    - -
    -
    - -

    ◆ GPIO_BSRR_BS_7

    - -
    -
    - - - - -
    #define GPIO_BSRR_BS_7   GPIO_BSRR_BS7
    -
    - -
    -
    - -

    ◆ GPIO_BSRR_BS_8

    - -
    -
    - - - - -
    #define GPIO_BSRR_BS_8   GPIO_BSRR_BS8
    -
    - -
    -
    - -

    ◆ GPIO_BSRR_BS_9

    - -
    -
    - - - - -
    #define GPIO_BSRR_BS_9   GPIO_BSRR_BS9
    -
    - -
    -
    - -

    ◆ GPIO_BSRR_BS_10

    - -
    -
    - - - - -
    #define GPIO_BSRR_BS_10   GPIO_BSRR_BS10
    -
    - -
    -
    - -

    ◆ GPIO_BSRR_BS_11

    - -
    -
    - - - - -
    #define GPIO_BSRR_BS_11   GPIO_BSRR_BS11
    -
    - -
    -
    - -

    ◆ GPIO_BSRR_BS_12

    - -
    -
    - - - - -
    #define GPIO_BSRR_BS_12   GPIO_BSRR_BS12
    -
    - -
    -
    - -

    ◆ GPIO_BSRR_BS_13

    - -
    -
    - - - - -
    #define GPIO_BSRR_BS_13   GPIO_BSRR_BS13
    -
    - -
    -
    - -

    ◆ GPIO_BSRR_BS_14

    - -
    -
    - - - - -
    #define GPIO_BSRR_BS_14   GPIO_BSRR_BS14
    -
    - -
    -
    - -

    ◆ GPIO_BSRR_BS_15

    - -
    -
    - - - - -
    #define GPIO_BSRR_BS_15   GPIO_BSRR_BS15
    -
    - -
    -
    - -

    ◆ GPIO_BSRR_BR_0

    - -
    -
    - - - - -
    #define GPIO_BSRR_BR_0   GPIO_BSRR_BR0
    -
    - -
    -
    - -

    ◆ GPIO_BSRR_BR_1

    - -
    -
    - - - - -
    #define GPIO_BSRR_BR_1   GPIO_BSRR_BR1
    -
    - -
    -
    - -

    ◆ GPIO_BSRR_BR_2

    - -
    -
    - - - - -
    #define GPIO_BSRR_BR_2   GPIO_BSRR_BR2
    -
    - -
    -
    - -

    ◆ GPIO_BSRR_BR_3

    - -
    -
    - - - - -
    #define GPIO_BSRR_BR_3   GPIO_BSRR_BR3
    -
    - -
    -
    - -

    ◆ GPIO_BSRR_BR_4

    - -
    -
    - - - - -
    #define GPIO_BSRR_BR_4   GPIO_BSRR_BR4
    -
    - -
    -
    - -

    ◆ GPIO_BSRR_BR_5

    - -
    -
    - - - - -
    #define GPIO_BSRR_BR_5   GPIO_BSRR_BR5
    -
    - -
    -
    - -

    ◆ GPIO_BSRR_BR_6

    - -
    -
    - - - - -
    #define GPIO_BSRR_BR_6   GPIO_BSRR_BR6
    -
    - -
    -
    - -

    ◆ GPIO_BSRR_BR_7

    - -
    -
    - - - - -
    #define GPIO_BSRR_BR_7   GPIO_BSRR_BR7
    -
    - -
    -
    - -

    ◆ GPIO_BSRR_BR_8

    - -
    -
    - - - - -
    #define GPIO_BSRR_BR_8   GPIO_BSRR_BR8
    -
    - -
    -
    - -

    ◆ GPIO_BSRR_BR_9

    - -
    -
    - - - - -
    #define GPIO_BSRR_BR_9   GPIO_BSRR_BR9
    -
    - -
    -
    - -

    ◆ GPIO_BSRR_BR_10

    - -
    -
    - - - - -
    #define GPIO_BSRR_BR_10   GPIO_BSRR_BR10
    -
    - -
    -
    - -

    ◆ GPIO_BSRR_BR_11

    - -
    -
    - - - - -
    #define GPIO_BSRR_BR_11   GPIO_BSRR_BR11
    -
    - -
    -
    - -

    ◆ GPIO_BSRR_BR_12

    - -
    -
    - - - - -
    #define GPIO_BSRR_BR_12   GPIO_BSRR_BR12
    -
    - -
    -
    - -

    ◆ GPIO_BSRR_BR_13

    - -
    -
    - - - - -
    #define GPIO_BSRR_BR_13   GPIO_BSRR_BR13
    -
    - -
    -
    - -

    ◆ GPIO_BSRR_BR_14

    - -
    -
    - - - - -
    #define GPIO_BSRR_BR_14   GPIO_BSRR_BR14
    -
    - -
    -
    - -

    ◆ GPIO_BSRR_BR_15

    - -
    -
    - - - - -
    #define GPIO_BSRR_BR_15   GPIO_BSRR_BR15
    -
    - -
    -
    - -

    ◆ GPIO_BRR_BR0

    - -
    -
    - - - - -
    #define GPIO_BRR_BR0   GPIO_BSRR_BR0
    -
    - -
    -
    - -

    ◆ GPIO_BRR_BR0_Pos

    - -
    -
    - - - - -
    #define GPIO_BRR_BR0_Pos   GPIO_BSRR_BR0_Pos
    -
    - -
    -
    - -

    ◆ GPIO_BRR_BR0_Msk

    - -
    -
    - - - - -
    #define GPIO_BRR_BR0_Msk   GPIO_BSRR_BR0_Msk
    -
    - -
    -
    - -

    ◆ GPIO_BRR_BR1

    - -
    -
    - - - - -
    #define GPIO_BRR_BR1   GPIO_BSRR_BR1
    -
    - -
    -
    - -

    ◆ GPIO_BRR_BR1_Pos

    - -
    -
    - - - - -
    #define GPIO_BRR_BR1_Pos   GPIO_BSRR_BR1_Pos
    -
    - -
    -
    - -

    ◆ GPIO_BRR_BR1_Msk

    - -
    -
    - - - - -
    #define GPIO_BRR_BR1_Msk   GPIO_BSRR_BR1_Msk
    -
    - -
    -
    - -

    ◆ GPIO_BRR_BR2

    - -
    -
    - - - - -
    #define GPIO_BRR_BR2   GPIO_BSRR_BR2
    -
    - -
    -
    - -

    ◆ GPIO_BRR_BR2_Pos

    - -
    -
    - - - - -
    #define GPIO_BRR_BR2_Pos   GPIO_BSRR_BR2_Pos
    -
    - -
    -
    - -

    ◆ GPIO_BRR_BR2_Msk

    - -
    -
    - - - - -
    #define GPIO_BRR_BR2_Msk   GPIO_BSRR_BR2_Msk
    -
    - -
    -
    - -

    ◆ GPIO_BRR_BR3

    - -
    -
    - - - - -
    #define GPIO_BRR_BR3   GPIO_BSRR_BR3
    -
    - -
    -
    - -

    ◆ GPIO_BRR_BR3_Pos

    - -
    -
    - - - - -
    #define GPIO_BRR_BR3_Pos   GPIO_BSRR_BR3_Pos
    -
    - -
    -
    - -

    ◆ GPIO_BRR_BR3_Msk

    - -
    -
    - - - - -
    #define GPIO_BRR_BR3_Msk   GPIO_BSRR_BR3_Msk
    -
    - -
    -
    - -

    ◆ GPIO_BRR_BR4

    - -
    -
    - - - - -
    #define GPIO_BRR_BR4   GPIO_BSRR_BR4
    -
    - -
    -
    - -

    ◆ GPIO_BRR_BR4_Pos

    - -
    -
    - - - - -
    #define GPIO_BRR_BR4_Pos   GPIO_BSRR_BR4_Pos
    -
    - -
    -
    - -

    ◆ GPIO_BRR_BR4_Msk

    - -
    -
    - - - - -
    #define GPIO_BRR_BR4_Msk   GPIO_BSRR_BR4_Msk
    -
    - -
    -
    - -

    ◆ GPIO_BRR_BR5

    - -
    -
    - - - - -
    #define GPIO_BRR_BR5   GPIO_BSRR_BR5
    -
    - -
    -
    - -

    ◆ GPIO_BRR_BR5_Pos

    - -
    -
    - - - - -
    #define GPIO_BRR_BR5_Pos   GPIO_BSRR_BR5_Pos
    -
    - -
    -
    - -

    ◆ GPIO_BRR_BR5_Msk

    - -
    -
    - - - - -
    #define GPIO_BRR_BR5_Msk   GPIO_BSRR_BR5_Msk
    -
    - -
    -
    - -

    ◆ GPIO_BRR_BR6

    - -
    -
    - - - - -
    #define GPIO_BRR_BR6   GPIO_BSRR_BR6
    -
    - -
    -
    - -

    ◆ GPIO_BRR_BR6_Pos

    - -
    -
    - - - - -
    #define GPIO_BRR_BR6_Pos   GPIO_BSRR_BR6_Pos
    -
    - -
    -
    - -

    ◆ GPIO_BRR_BR6_Msk

    - -
    -
    - - - - -
    #define GPIO_BRR_BR6_Msk   GPIO_BSRR_BR6_Msk
    -
    - -
    -
    - -

    ◆ GPIO_BRR_BR7

    - -
    -
    - - - - -
    #define GPIO_BRR_BR7   GPIO_BSRR_BR7
    -
    - -
    -
    - -

    ◆ GPIO_BRR_BR7_Pos

    - -
    -
    - - - - -
    #define GPIO_BRR_BR7_Pos   GPIO_BSRR_BR7_Pos
    -
    - -
    -
    - -

    ◆ GPIO_BRR_BR7_Msk

    - -
    -
    - - - - -
    #define GPIO_BRR_BR7_Msk   GPIO_BSRR_BR7_Msk
    -
    - -
    -
    - -

    ◆ GPIO_BRR_BR8

    - -
    -
    - - - - -
    #define GPIO_BRR_BR8   GPIO_BSRR_BR8
    -
    - -
    -
    - -

    ◆ GPIO_BRR_BR8_Pos

    - -
    -
    - - - - -
    #define GPIO_BRR_BR8_Pos   GPIO_BSRR_BR8_Pos
    -
    - -
    -
    - -

    ◆ GPIO_BRR_BR8_Msk

    - -
    -
    - - - - -
    #define GPIO_BRR_BR8_Msk   GPIO_BSRR_BR8_Msk
    -
    - -
    -
    - -

    ◆ GPIO_BRR_BR9

    - -
    -
    - - - - -
    #define GPIO_BRR_BR9   GPIO_BSRR_BR9
    -
    - -
    -
    - -

    ◆ GPIO_BRR_BR9_Pos

    - -
    -
    - - - - -
    #define GPIO_BRR_BR9_Pos   GPIO_BSRR_BR9_Pos
    -
    - -
    -
    - -

    ◆ GPIO_BRR_BR9_Msk

    - -
    -
    - - - - -
    #define GPIO_BRR_BR9_Msk   GPIO_BSRR_BR9_Msk
    -
    - -
    -
    - -

    ◆ GPIO_BRR_BR10

    - -
    -
    - - - - -
    #define GPIO_BRR_BR10   GPIO_BSRR_BR10
    -
    - -
    -
    - -

    ◆ GPIO_BRR_BR10_Pos

    - -
    -
    - - - - -
    #define GPIO_BRR_BR10_Pos   GPIO_BSRR_BR10_Pos
    -
    - -
    -
    - -

    ◆ GPIO_BRR_BR10_Msk

    - -
    -
    - - - - -
    #define GPIO_BRR_BR10_Msk   GPIO_BSRR_BR10_Msk
    -
    - -
    -
    - -

    ◆ GPIO_BRR_BR11

    - -
    -
    - - - - -
    #define GPIO_BRR_BR11   GPIO_BSRR_BR11
    -
    - -
    -
    - -

    ◆ GPIO_BRR_BR11_Pos

    - -
    -
    - - - - -
    #define GPIO_BRR_BR11_Pos   GPIO_BSRR_BR11_Pos
    -
    - -
    -
    - -

    ◆ GPIO_BRR_BR11_Msk

    - -
    -
    - - - - -
    #define GPIO_BRR_BR11_Msk   GPIO_BSRR_BR11_Msk
    -
    - -
    -
    - -

    ◆ GPIO_BRR_BR12

    - -
    -
    - - - - -
    #define GPIO_BRR_BR12   GPIO_BSRR_BR12
    -
    - -
    -
    - -

    ◆ GPIO_BRR_BR12_Pos

    - -
    -
    - - - - -
    #define GPIO_BRR_BR12_Pos   GPIO_BSRR_BR12_Pos
    -
    - -
    -
    - -

    ◆ GPIO_BRR_BR12_Msk

    - -
    -
    - - - - -
    #define GPIO_BRR_BR12_Msk   GPIO_BSRR_BR12_Msk
    -
    - -
    -
    - -

    ◆ GPIO_BRR_BR13

    - -
    -
    - - - - -
    #define GPIO_BRR_BR13   GPIO_BSRR_BR13
    -
    - -
    -
    - -

    ◆ GPIO_BRR_BR13_Pos

    - -
    -
    - - - - -
    #define GPIO_BRR_BR13_Pos   GPIO_BSRR_BR13_Pos
    -
    - -
    -
    - -

    ◆ GPIO_BRR_BR13_Msk

    - -
    -
    - - - - -
    #define GPIO_BRR_BR13_Msk   GPIO_BSRR_BR13_Msk
    -
    - -
    -
    - -

    ◆ GPIO_BRR_BR14

    - -
    -
    - - - - -
    #define GPIO_BRR_BR14   GPIO_BSRR_BR14
    -
    - -
    -
    - -

    ◆ GPIO_BRR_BR14_Pos

    - -
    -
    - - - - -
    #define GPIO_BRR_BR14_Pos   GPIO_BSRR_BR14_Pos
    -
    - -
    -
    - -

    ◆ GPIO_BRR_BR14_Msk

    - -
    -
    - - - - -
    #define GPIO_BRR_BR14_Msk   GPIO_BSRR_BR14_Msk
    -
    - -
    -
    - -

    ◆ GPIO_BRR_BR15

    - -
    -
    - - - - -
    #define GPIO_BRR_BR15   GPIO_BSRR_BR15
    -
    - -
    -
    - -

    ◆ GPIO_BRR_BR15_Pos

    - -
    -
    - - - - -
    #define GPIO_BRR_BR15_Pos   GPIO_BSRR_BR15_Pos
    -
    - -
    -
    - -

    ◆ GPIO_BRR_BR15_Msk

    - -
    -
    - - - - -
    #define GPIO_BRR_BR15_Msk   GPIO_BSRR_BR15_Msk
    -
    - -
    -
    - -

    ◆ GPIO_LCKR_LCK0_Pos

    - -
    -
    - - - - -
    #define GPIO_LCKR_LCK0_Pos   (0U)
    -
    - -
    -
    - -

    ◆ GPIO_LCKR_LCK0_Msk

    - -
    -
    - - - - -
    #define GPIO_LCKR_LCK0_Msk   (0x1UL << GPIO_LCKR_LCK0_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ GPIO_LCKR_LCK0

    - -
    -
    - - - - -
    #define GPIO_LCKR_LCK0   GPIO_LCKR_LCK0_Msk
    -
    - -
    -
    - -

    ◆ GPIO_LCKR_LCK1_Pos

    - -
    -
    - - - - -
    #define GPIO_LCKR_LCK1_Pos   (1U)
    -
    - -
    -
    - -

    ◆ GPIO_LCKR_LCK1_Msk

    - -
    -
    - - - - -
    #define GPIO_LCKR_LCK1_Msk   (0x1UL << GPIO_LCKR_LCK1_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ GPIO_LCKR_LCK1

    - -
    -
    - - - - -
    #define GPIO_LCKR_LCK1   GPIO_LCKR_LCK1_Msk
    -
    - -
    -
    - -

    ◆ GPIO_LCKR_LCK2_Pos

    - -
    -
    - - - - -
    #define GPIO_LCKR_LCK2_Pos   (2U)
    -
    - -
    -
    - -

    ◆ GPIO_LCKR_LCK2_Msk

    - -
    -
    - - - - -
    #define GPIO_LCKR_LCK2_Msk   (0x1UL << GPIO_LCKR_LCK2_Pos)
    -
    -

    0x00000004

    - -
    -
    - -

    ◆ GPIO_LCKR_LCK2

    - -
    -
    - - - - -
    #define GPIO_LCKR_LCK2   GPIO_LCKR_LCK2_Msk
    -
    - -
    -
    - -

    ◆ GPIO_LCKR_LCK3_Pos

    - -
    -
    - - - - -
    #define GPIO_LCKR_LCK3_Pos   (3U)
    -
    - -
    -
    - -

    ◆ GPIO_LCKR_LCK3_Msk

    - -
    -
    - - - - -
    #define GPIO_LCKR_LCK3_Msk   (0x1UL << GPIO_LCKR_LCK3_Pos)
    -
    -

    0x00000008

    - -
    -
    - -

    ◆ GPIO_LCKR_LCK3

    - -
    -
    - - - - -
    #define GPIO_LCKR_LCK3   GPIO_LCKR_LCK3_Msk
    -
    - -
    -
    - -

    ◆ GPIO_LCKR_LCK4_Pos

    - -
    -
    - - - - -
    #define GPIO_LCKR_LCK4_Pos   (4U)
    -
    - -
    -
    - -

    ◆ GPIO_LCKR_LCK4_Msk

    - -
    -
    - - - - -
    #define GPIO_LCKR_LCK4_Msk   (0x1UL << GPIO_LCKR_LCK4_Pos)
    -
    -

    0x00000010

    - -
    -
    - -

    ◆ GPIO_LCKR_LCK4

    - -
    -
    - - - - -
    #define GPIO_LCKR_LCK4   GPIO_LCKR_LCK4_Msk
    -
    - -
    -
    - -

    ◆ GPIO_LCKR_LCK5_Pos

    - -
    -
    - - - - -
    #define GPIO_LCKR_LCK5_Pos   (5U)
    -
    - -
    -
    - -

    ◆ GPIO_LCKR_LCK5_Msk

    - -
    -
    - - - - -
    #define GPIO_LCKR_LCK5_Msk   (0x1UL << GPIO_LCKR_LCK5_Pos)
    -
    -

    0x00000020

    - -
    -
    - -

    ◆ GPIO_LCKR_LCK5

    - -
    -
    - - - - -
    #define GPIO_LCKR_LCK5   GPIO_LCKR_LCK5_Msk
    -
    - -
    -
    - -

    ◆ GPIO_LCKR_LCK6_Pos

    - -
    -
    - - - - -
    #define GPIO_LCKR_LCK6_Pos   (6U)
    -
    - -
    -
    - -

    ◆ GPIO_LCKR_LCK6_Msk

    - -
    -
    - - - - -
    #define GPIO_LCKR_LCK6_Msk   (0x1UL << GPIO_LCKR_LCK6_Pos)
    -
    -

    0x00000040

    - -
    -
    - -

    ◆ GPIO_LCKR_LCK6

    - -
    -
    - - - - -
    #define GPIO_LCKR_LCK6   GPIO_LCKR_LCK6_Msk
    -
    - -
    -
    - -

    ◆ GPIO_LCKR_LCK7_Pos

    - -
    -
    - - - - -
    #define GPIO_LCKR_LCK7_Pos   (7U)
    -
    - -
    -
    - -

    ◆ GPIO_LCKR_LCK7_Msk

    - -
    -
    - - - - -
    #define GPIO_LCKR_LCK7_Msk   (0x1UL << GPIO_LCKR_LCK7_Pos)
    -
    -

    0x00000080

    - -
    -
    - -

    ◆ GPIO_LCKR_LCK7

    - -
    -
    - - - - -
    #define GPIO_LCKR_LCK7   GPIO_LCKR_LCK7_Msk
    -
    - -
    -
    - -

    ◆ GPIO_LCKR_LCK8_Pos

    - -
    -
    - - - - -
    #define GPIO_LCKR_LCK8_Pos   (8U)
    -
    - -
    -
    - -

    ◆ GPIO_LCKR_LCK8_Msk

    - -
    -
    - - - - -
    #define GPIO_LCKR_LCK8_Msk   (0x1UL << GPIO_LCKR_LCK8_Pos)
    -
    -

    0x00000100

    - -
    -
    - -

    ◆ GPIO_LCKR_LCK8

    - -
    -
    - - - - -
    #define GPIO_LCKR_LCK8   GPIO_LCKR_LCK8_Msk
    -
    - -
    -
    - -

    ◆ GPIO_LCKR_LCK9_Pos

    - -
    -
    - - - - -
    #define GPIO_LCKR_LCK9_Pos   (9U)
    -
    - -
    -
    - -

    ◆ GPIO_LCKR_LCK9_Msk

    - -
    -
    - - - - -
    #define GPIO_LCKR_LCK9_Msk   (0x1UL << GPIO_LCKR_LCK9_Pos)
    -
    -

    0x00000200

    - -
    -
    - -

    ◆ GPIO_LCKR_LCK9

    - -
    -
    - - - - -
    #define GPIO_LCKR_LCK9   GPIO_LCKR_LCK9_Msk
    -
    - -
    -
    - -

    ◆ GPIO_LCKR_LCK10_Pos

    - -
    -
    - - - - -
    #define GPIO_LCKR_LCK10_Pos   (10U)
    -
    - -
    -
    - -

    ◆ GPIO_LCKR_LCK10_Msk

    - -
    -
    - - - - -
    #define GPIO_LCKR_LCK10_Msk   (0x1UL << GPIO_LCKR_LCK10_Pos)
    -
    -

    0x00000400

    - -
    -
    - -

    ◆ GPIO_LCKR_LCK10

    - -
    -
    - - - - -
    #define GPIO_LCKR_LCK10   GPIO_LCKR_LCK10_Msk
    -
    - -
    -
    - -

    ◆ GPIO_LCKR_LCK11_Pos

    - -
    -
    - - - - -
    #define GPIO_LCKR_LCK11_Pos   (11U)
    -
    - -
    -
    - -

    ◆ GPIO_LCKR_LCK11_Msk

    - -
    -
    - - - - -
    #define GPIO_LCKR_LCK11_Msk   (0x1UL << GPIO_LCKR_LCK11_Pos)
    -
    -

    0x00000800

    - -
    -
    - -

    ◆ GPIO_LCKR_LCK11

    - -
    -
    - - - - -
    #define GPIO_LCKR_LCK11   GPIO_LCKR_LCK11_Msk
    -
    - -
    -
    - -

    ◆ GPIO_LCKR_LCK12_Pos

    - -
    -
    - - - - -
    #define GPIO_LCKR_LCK12_Pos   (12U)
    -
    - -
    -
    - -

    ◆ GPIO_LCKR_LCK12_Msk

    - -
    -
    - - - - -
    #define GPIO_LCKR_LCK12_Msk   (0x1UL << GPIO_LCKR_LCK12_Pos)
    -
    -

    0x00001000

    - -
    -
    - -

    ◆ GPIO_LCKR_LCK12

    - -
    -
    - - - - -
    #define GPIO_LCKR_LCK12   GPIO_LCKR_LCK12_Msk
    -
    - -
    -
    - -

    ◆ GPIO_LCKR_LCK13_Pos

    - -
    -
    - - - - -
    #define GPIO_LCKR_LCK13_Pos   (13U)
    -
    - -
    -
    - -

    ◆ GPIO_LCKR_LCK13_Msk

    - -
    -
    - - - - -
    #define GPIO_LCKR_LCK13_Msk   (0x1UL << GPIO_LCKR_LCK13_Pos)
    -
    -

    0x00002000

    - -
    -
    - -

    ◆ GPIO_LCKR_LCK13

    - -
    -
    - - - - -
    #define GPIO_LCKR_LCK13   GPIO_LCKR_LCK13_Msk
    -
    - -
    -
    - -

    ◆ GPIO_LCKR_LCK14_Pos

    - -
    -
    - - - - -
    #define GPIO_LCKR_LCK14_Pos   (14U)
    -
    - -
    -
    - -

    ◆ GPIO_LCKR_LCK14_Msk

    - -
    -
    - - - - -
    #define GPIO_LCKR_LCK14_Msk   (0x1UL << GPIO_LCKR_LCK14_Pos)
    -
    -

    0x00004000

    - -
    -
    - -

    ◆ GPIO_LCKR_LCK14

    - -
    -
    - - - - -
    #define GPIO_LCKR_LCK14   GPIO_LCKR_LCK14_Msk
    -
    - -
    -
    - -

    ◆ GPIO_LCKR_LCK15_Pos

    - -
    -
    - - - - -
    #define GPIO_LCKR_LCK15_Pos   (15U)
    -
    - -
    -
    - -

    ◆ GPIO_LCKR_LCK15_Msk

    - -
    -
    - - - - -
    #define GPIO_LCKR_LCK15_Msk   (0x1UL << GPIO_LCKR_LCK15_Pos)
    -
    -

    0x00008000

    - -
    -
    - -

    ◆ GPIO_LCKR_LCK15

    - -
    -
    - - - - -
    #define GPIO_LCKR_LCK15   GPIO_LCKR_LCK15_Msk
    -
    - -
    -
    - -

    ◆ GPIO_LCKR_LCKK_Pos

    - -
    -
    - - - - -
    #define GPIO_LCKR_LCKK_Pos   (16U)
    -
    - -
    -
    - -

    ◆ GPIO_LCKR_LCKK_Msk

    - -
    -
    - - - - -
    #define GPIO_LCKR_LCKK_Msk   (0x1UL << GPIO_LCKR_LCKK_Pos)
    -
    -

    0x00010000

    - -
    -
    - -

    ◆ GPIO_LCKR_LCKK

    - -
    -
    - - - - -
    #define GPIO_LCKR_LCKK   GPIO_LCKR_LCKK_Msk
    -
    - -
    -
    - -

    ◆ GPIO_AFRL_AFSEL0_Pos

    - -
    -
    - - - - -
    #define GPIO_AFRL_AFSEL0_Pos   (0U)
    -
    - -
    -
    - -

    ◆ GPIO_AFRL_AFSEL0_Msk

    - -
    -
    - - - - -
    #define GPIO_AFRL_AFSEL0_Msk   (0xFUL << GPIO_AFRL_AFSEL0_Pos)
    -
    -

    0x0000000F

    - -
    -
    - -

    ◆ GPIO_AFRL_AFSEL0

    - -
    -
    - - - - -
    #define GPIO_AFRL_AFSEL0   GPIO_AFRL_AFSEL0_Msk
    -
    - -
    -
    - -

    ◆ GPIO_AFRL_AFSEL0_0

    - -
    -
    - - - - -
    #define GPIO_AFRL_AFSEL0_0   (0x1UL << GPIO_AFRL_AFSEL0_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ GPIO_AFRL_AFSEL0_1

    - -
    -
    - - - - -
    #define GPIO_AFRL_AFSEL0_1   (0x2UL << GPIO_AFRL_AFSEL0_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ GPIO_AFRL_AFSEL0_2

    - -
    -
    - - - - -
    #define GPIO_AFRL_AFSEL0_2   (0x4UL << GPIO_AFRL_AFSEL0_Pos)
    -
    -

    0x00000004

    - -
    -
    - -

    ◆ GPIO_AFRL_AFSEL0_3

    - -
    -
    - - - - -
    #define GPIO_AFRL_AFSEL0_3   (0x8UL << GPIO_AFRL_AFSEL0_Pos)
    -
    -

    0x00000008

    - -
    -
    - -

    ◆ GPIO_AFRL_AFSEL1_Pos

    - -
    -
    - - - - -
    #define GPIO_AFRL_AFSEL1_Pos   (4U)
    -
    - -
    -
    - -

    ◆ GPIO_AFRL_AFSEL1_Msk

    - -
    -
    - - - - -
    #define GPIO_AFRL_AFSEL1_Msk   (0xFUL << GPIO_AFRL_AFSEL1_Pos)
    -
    -

    0x000000F0

    - -
    -
    - -

    ◆ GPIO_AFRL_AFSEL1

    - -
    -
    - - - - -
    #define GPIO_AFRL_AFSEL1   GPIO_AFRL_AFSEL1_Msk
    -
    - -
    -
    - -

    ◆ GPIO_AFRL_AFSEL1_0

    - -
    -
    - - - - -
    #define GPIO_AFRL_AFSEL1_0   (0x1UL << GPIO_AFRL_AFSEL1_Pos)
    -
    -

    0x00000010

    - -
    -
    - -

    ◆ GPIO_AFRL_AFSEL1_1

    - -
    -
    - - - - -
    #define GPIO_AFRL_AFSEL1_1   (0x2UL << GPIO_AFRL_AFSEL1_Pos)
    -
    -

    0x00000020

    - -
    -
    - -

    ◆ GPIO_AFRL_AFSEL1_2

    - -
    -
    - - - - -
    #define GPIO_AFRL_AFSEL1_2   (0x4UL << GPIO_AFRL_AFSEL1_Pos)
    -
    -

    0x00000040

    - -
    -
    - -

    ◆ GPIO_AFRL_AFSEL1_3

    - -
    -
    - - - - -
    #define GPIO_AFRL_AFSEL1_3   (0x8UL << GPIO_AFRL_AFSEL1_Pos)
    -
    -

    0x00000080

    - -
    -
    - -

    ◆ GPIO_AFRL_AFSEL2_Pos

    - -
    -
    - - - - -
    #define GPIO_AFRL_AFSEL2_Pos   (8U)
    -
    - -
    -
    - -

    ◆ GPIO_AFRL_AFSEL2_Msk

    - -
    -
    - - - - -
    #define GPIO_AFRL_AFSEL2_Msk   (0xFUL << GPIO_AFRL_AFSEL2_Pos)
    -
    -

    0x00000F00

    - -
    -
    - -

    ◆ GPIO_AFRL_AFSEL2

    - -
    -
    - - - - -
    #define GPIO_AFRL_AFSEL2   GPIO_AFRL_AFSEL2_Msk
    -
    - -
    -
    - -

    ◆ GPIO_AFRL_AFSEL2_0

    - -
    -
    - - - - -
    #define GPIO_AFRL_AFSEL2_0   (0x1UL << GPIO_AFRL_AFSEL2_Pos)
    -
    -

    0x00000100

    - -
    -
    - -

    ◆ GPIO_AFRL_AFSEL2_1

    - -
    -
    - - - - -
    #define GPIO_AFRL_AFSEL2_1   (0x2UL << GPIO_AFRL_AFSEL2_Pos)
    -
    -

    0x00000200

    - -
    -
    - -

    ◆ GPIO_AFRL_AFSEL2_2

    - -
    -
    - - - - -
    #define GPIO_AFRL_AFSEL2_2   (0x4UL << GPIO_AFRL_AFSEL2_Pos)
    -
    -

    0x00000400

    - -
    -
    - -

    ◆ GPIO_AFRL_AFSEL2_3

    - -
    -
    - - - - -
    #define GPIO_AFRL_AFSEL2_3   (0x8UL << GPIO_AFRL_AFSEL2_Pos)
    -
    -

    0x00000800

    - -
    -
    - -

    ◆ GPIO_AFRL_AFSEL3_Pos

    - -
    -
    - - - - -
    #define GPIO_AFRL_AFSEL3_Pos   (12U)
    -
    - -
    -
    - -

    ◆ GPIO_AFRL_AFSEL3_Msk

    - -
    -
    - - - - -
    #define GPIO_AFRL_AFSEL3_Msk   (0xFUL << GPIO_AFRL_AFSEL3_Pos)
    -
    -

    0x0000F000

    - -
    -
    - -

    ◆ GPIO_AFRL_AFSEL3

    - -
    -
    - - - - -
    #define GPIO_AFRL_AFSEL3   GPIO_AFRL_AFSEL3_Msk
    -
    - -
    -
    - -

    ◆ GPIO_AFRL_AFSEL3_0

    - -
    -
    - - - - -
    #define GPIO_AFRL_AFSEL3_0   (0x1UL << GPIO_AFRL_AFSEL3_Pos)
    -
    -

    0x00001000

    - -
    -
    - -

    ◆ GPIO_AFRL_AFSEL3_1

    - -
    -
    - - - - -
    #define GPIO_AFRL_AFSEL3_1   (0x2UL << GPIO_AFRL_AFSEL3_Pos)
    -
    -

    0x00002000

    - -
    -
    - -

    ◆ GPIO_AFRL_AFSEL3_2

    - -
    -
    - - - - -
    #define GPIO_AFRL_AFSEL3_2   (0x4UL << GPIO_AFRL_AFSEL3_Pos)
    -
    -

    0x00004000

    - -
    -
    - -

    ◆ GPIO_AFRL_AFSEL3_3

    - -
    -
    - - - - -
    #define GPIO_AFRL_AFSEL3_3   (0x8UL << GPIO_AFRL_AFSEL3_Pos)
    -
    -

    0x00008000

    - -
    -
    - -

    ◆ GPIO_AFRL_AFSEL4_Pos

    - -
    -
    - - - - -
    #define GPIO_AFRL_AFSEL4_Pos   (16U)
    -
    - -
    -
    - -

    ◆ GPIO_AFRL_AFSEL4_Msk

    - -
    -
    - - - - -
    #define GPIO_AFRL_AFSEL4_Msk   (0xFUL << GPIO_AFRL_AFSEL4_Pos)
    -
    -

    0x000F0000

    - -
    -
    - -

    ◆ GPIO_AFRL_AFSEL4

    - -
    -
    - - - - -
    #define GPIO_AFRL_AFSEL4   GPIO_AFRL_AFSEL4_Msk
    -
    - -
    -
    - -

    ◆ GPIO_AFRL_AFSEL4_0

    - -
    -
    - - - - -
    #define GPIO_AFRL_AFSEL4_0   (0x1UL << GPIO_AFRL_AFSEL4_Pos)
    -
    -

    0x00010000

    - -
    -
    - -

    ◆ GPIO_AFRL_AFSEL4_1

    - -
    -
    - - - - -
    #define GPIO_AFRL_AFSEL4_1   (0x2UL << GPIO_AFRL_AFSEL4_Pos)
    -
    -

    0x00020000

    - -
    -
    - -

    ◆ GPIO_AFRL_AFSEL4_2

    - -
    -
    - - - - -
    #define GPIO_AFRL_AFSEL4_2   (0x4UL << GPIO_AFRL_AFSEL4_Pos)
    -
    -

    0x00040000

    - -
    -
    - -

    ◆ GPIO_AFRL_AFSEL4_3

    - -
    -
    - - - - -
    #define GPIO_AFRL_AFSEL4_3   (0x8UL << GPIO_AFRL_AFSEL4_Pos)
    -
    -

    0x00080000

    - -
    -
    - -

    ◆ GPIO_AFRL_AFSEL5_Pos

    - -
    -
    - - - - -
    #define GPIO_AFRL_AFSEL5_Pos   (20U)
    -
    - -
    -
    - -

    ◆ GPIO_AFRL_AFSEL5_Msk

    - -
    -
    - - - - -
    #define GPIO_AFRL_AFSEL5_Msk   (0xFUL << GPIO_AFRL_AFSEL5_Pos)
    -
    -

    0x00F00000

    - -
    -
    - -

    ◆ GPIO_AFRL_AFSEL5

    - -
    -
    - - - - -
    #define GPIO_AFRL_AFSEL5   GPIO_AFRL_AFSEL5_Msk
    -
    - -
    -
    - -

    ◆ GPIO_AFRL_AFSEL5_0

    - -
    -
    - - - - -
    #define GPIO_AFRL_AFSEL5_0   (0x1UL << GPIO_AFRL_AFSEL5_Pos)
    -
    -

    0x00100000

    - -
    -
    - -

    ◆ GPIO_AFRL_AFSEL5_1

    - -
    -
    - - - - -
    #define GPIO_AFRL_AFSEL5_1   (0x2UL << GPIO_AFRL_AFSEL5_Pos)
    -
    -

    0x00200000

    - -
    -
    - -

    ◆ GPIO_AFRL_AFSEL5_2

    - -
    -
    - - - - -
    #define GPIO_AFRL_AFSEL5_2   (0x4UL << GPIO_AFRL_AFSEL5_Pos)
    -
    -

    0x00400000

    - -
    -
    - -

    ◆ GPIO_AFRL_AFSEL5_3

    - -
    -
    - - - - -
    #define GPIO_AFRL_AFSEL5_3   (0x8UL << GPIO_AFRL_AFSEL5_Pos)
    -
    -

    0x00800000

    - -
    -
    - -

    ◆ GPIO_AFRL_AFSEL6_Pos

    - -
    -
    - - - - -
    #define GPIO_AFRL_AFSEL6_Pos   (24U)
    -
    - -
    -
    - -

    ◆ GPIO_AFRL_AFSEL6_Msk

    - -
    -
    - - - - -
    #define GPIO_AFRL_AFSEL6_Msk   (0xFUL << GPIO_AFRL_AFSEL6_Pos)
    -
    -

    0x0F000000

    - -
    -
    - -

    ◆ GPIO_AFRL_AFSEL6

    - -
    -
    - - - - -
    #define GPIO_AFRL_AFSEL6   GPIO_AFRL_AFSEL6_Msk
    -
    - -
    -
    - -

    ◆ GPIO_AFRL_AFSEL6_0

    - -
    -
    - - - - -
    #define GPIO_AFRL_AFSEL6_0   (0x1UL << GPIO_AFRL_AFSEL6_Pos)
    -
    -

    0x01000000

    - -
    -
    - -

    ◆ GPIO_AFRL_AFSEL6_1

    - -
    -
    - - - - -
    #define GPIO_AFRL_AFSEL6_1   (0x2UL << GPIO_AFRL_AFSEL6_Pos)
    -
    -

    0x02000000

    - -
    -
    - -

    ◆ GPIO_AFRL_AFSEL6_2

    - -
    -
    - - - - -
    #define GPIO_AFRL_AFSEL6_2   (0x4UL << GPIO_AFRL_AFSEL6_Pos)
    -
    -

    0x04000000

    - -
    -
    - -

    ◆ GPIO_AFRL_AFSEL6_3

    - -
    -
    - - - - -
    #define GPIO_AFRL_AFSEL6_3   (0x8UL << GPIO_AFRL_AFSEL6_Pos)
    -
    -

    0x08000000

    - -
    -
    - -

    ◆ GPIO_AFRL_AFSEL7_Pos

    - -
    -
    - - - - -
    #define GPIO_AFRL_AFSEL7_Pos   (28U)
    -
    - -
    -
    - -

    ◆ GPIO_AFRL_AFSEL7_Msk

    - -
    -
    - - - - -
    #define GPIO_AFRL_AFSEL7_Msk   (0xFUL << GPIO_AFRL_AFSEL7_Pos)
    -
    -

    0xF0000000

    - -
    -
    - -

    ◆ GPIO_AFRL_AFSEL7

    - -
    -
    - - - - -
    #define GPIO_AFRL_AFSEL7   GPIO_AFRL_AFSEL7_Msk
    -
    - -
    -
    - -

    ◆ GPIO_AFRL_AFSEL7_0

    - -
    -
    - - - - -
    #define GPIO_AFRL_AFSEL7_0   (0x1UL << GPIO_AFRL_AFSEL7_Pos)
    -
    -

    0x10000000

    - -
    -
    - -

    ◆ GPIO_AFRL_AFSEL7_1

    - -
    -
    - - - - -
    #define GPIO_AFRL_AFSEL7_1   (0x2UL << GPIO_AFRL_AFSEL7_Pos)
    -
    -

    0x20000000

    - -
    -
    - -

    ◆ GPIO_AFRL_AFSEL7_2

    - -
    -
    - - - - -
    #define GPIO_AFRL_AFSEL7_2   (0x4UL << GPIO_AFRL_AFSEL7_Pos)
    -
    -

    0x40000000

    - -
    -
    - -

    ◆ GPIO_AFRL_AFSEL7_3

    - -
    -
    - - - - -
    #define GPIO_AFRL_AFSEL7_3   (0x8UL << GPIO_AFRL_AFSEL7_Pos)
    -
    -

    0x80000000

    - -
    -
    - -

    ◆ GPIO_AFRL_AFRL0

    - -
    -
    - - - - -
    #define GPIO_AFRL_AFRL0   GPIO_AFRL_AFSEL0
    -
    - -
    -
    - -

    ◆ GPIO_AFRL_AFRL0_0

    - -
    -
    - - - - -
    #define GPIO_AFRL_AFRL0_0   GPIO_AFRL_AFSEL0_0
    -
    - -
    -
    - -

    ◆ GPIO_AFRL_AFRL0_1

    - -
    -
    - - - - -
    #define GPIO_AFRL_AFRL0_1   GPIO_AFRL_AFSEL0_1
    -
    - -
    -
    - -

    ◆ GPIO_AFRL_AFRL0_2

    - -
    -
    - - - - -
    #define GPIO_AFRL_AFRL0_2   GPIO_AFRL_AFSEL0_2
    -
    - -
    -
    - -

    ◆ GPIO_AFRL_AFRL0_3

    - -
    -
    - - - - -
    #define GPIO_AFRL_AFRL0_3   GPIO_AFRL_AFSEL0_3
    -
    - -
    -
    - -

    ◆ GPIO_AFRL_AFRL1

    - -
    -
    - - - - -
    #define GPIO_AFRL_AFRL1   GPIO_AFRL_AFSEL1
    -
    - -
    -
    - -

    ◆ GPIO_AFRL_AFRL1_0

    - -
    -
    - - - - -
    #define GPIO_AFRL_AFRL1_0   GPIO_AFRL_AFSEL1_0
    -
    - -
    -
    - -

    ◆ GPIO_AFRL_AFRL1_1

    - -
    -
    - - - - -
    #define GPIO_AFRL_AFRL1_1   GPIO_AFRL_AFSEL1_1
    -
    - -
    -
    - -

    ◆ GPIO_AFRL_AFRL1_2

    - -
    -
    - - - - -
    #define GPIO_AFRL_AFRL1_2   GPIO_AFRL_AFSEL1_2
    -
    - -
    -
    - -

    ◆ GPIO_AFRL_AFRL1_3

    - -
    -
    - - - - -
    #define GPIO_AFRL_AFRL1_3   GPIO_AFRL_AFSEL1_3
    -
    - -
    -
    - -

    ◆ GPIO_AFRL_AFRL2

    - -
    -
    - - - - -
    #define GPIO_AFRL_AFRL2   GPIO_AFRL_AFSEL2
    -
    - -
    -
    - -

    ◆ GPIO_AFRL_AFRL2_0

    - -
    -
    - - - - -
    #define GPIO_AFRL_AFRL2_0   GPIO_AFRL_AFSEL2_0
    -
    - -
    -
    - -

    ◆ GPIO_AFRL_AFRL2_1

    - -
    -
    - - - - -
    #define GPIO_AFRL_AFRL2_1   GPIO_AFRL_AFSEL2_1
    -
    - -
    -
    - -

    ◆ GPIO_AFRL_AFRL2_2

    - -
    -
    - - - - -
    #define GPIO_AFRL_AFRL2_2   GPIO_AFRL_AFSEL2_2
    -
    - -
    -
    - -

    ◆ GPIO_AFRL_AFRL2_3

    - -
    -
    - - - - -
    #define GPIO_AFRL_AFRL2_3   GPIO_AFRL_AFSEL2_3
    -
    - -
    -
    - -

    ◆ GPIO_AFRL_AFRL3

    - -
    -
    - - - - -
    #define GPIO_AFRL_AFRL3   GPIO_AFRL_AFSEL3
    -
    - -
    -
    - -

    ◆ GPIO_AFRL_AFRL3_0

    - -
    -
    - - - - -
    #define GPIO_AFRL_AFRL3_0   GPIO_AFRL_AFSEL3_0
    -
    - -
    -
    - -

    ◆ GPIO_AFRL_AFRL3_1

    - -
    -
    - - - - -
    #define GPIO_AFRL_AFRL3_1   GPIO_AFRL_AFSEL3_1
    -
    - -
    -
    - -

    ◆ GPIO_AFRL_AFRL3_2

    - -
    -
    - - - - -
    #define GPIO_AFRL_AFRL3_2   GPIO_AFRL_AFSEL3_2
    -
    - -
    -
    - -

    ◆ GPIO_AFRL_AFRL3_3

    - -
    -
    - - - - -
    #define GPIO_AFRL_AFRL3_3   GPIO_AFRL_AFSEL3_3
    -
    - -
    -
    - -

    ◆ GPIO_AFRL_AFRL4

    - -
    -
    - - - - -
    #define GPIO_AFRL_AFRL4   GPIO_AFRL_AFSEL4
    -
    - -
    -
    - -

    ◆ GPIO_AFRL_AFRL4_0

    - -
    -
    - - - - -
    #define GPIO_AFRL_AFRL4_0   GPIO_AFRL_AFSEL4_0
    -
    - -
    -
    - -

    ◆ GPIO_AFRL_AFRL4_1

    - -
    -
    - - - - -
    #define GPIO_AFRL_AFRL4_1   GPIO_AFRL_AFSEL4_1
    -
    - -
    -
    - -

    ◆ GPIO_AFRL_AFRL4_2

    - -
    -
    - - - - -
    #define GPIO_AFRL_AFRL4_2   GPIO_AFRL_AFSEL4_2
    -
    - -
    -
    - -

    ◆ GPIO_AFRL_AFRL4_3

    - -
    -
    - - - - -
    #define GPIO_AFRL_AFRL4_3   GPIO_AFRL_AFSEL4_3
    -
    - -
    -
    - -

    ◆ GPIO_AFRL_AFRL5

    - -
    -
    - - - - -
    #define GPIO_AFRL_AFRL5   GPIO_AFRL_AFSEL5
    -
    - -
    -
    - -

    ◆ GPIO_AFRL_AFRL5_0

    - -
    -
    - - - - -
    #define GPIO_AFRL_AFRL5_0   GPIO_AFRL_AFSEL5_0
    -
    - -
    -
    - -

    ◆ GPIO_AFRL_AFRL5_1

    - -
    -
    - - - - -
    #define GPIO_AFRL_AFRL5_1   GPIO_AFRL_AFSEL5_1
    -
    - -
    -
    - -

    ◆ GPIO_AFRL_AFRL5_2

    - -
    -
    - - - - -
    #define GPIO_AFRL_AFRL5_2   GPIO_AFRL_AFSEL5_2
    -
    - -
    -
    - -

    ◆ GPIO_AFRL_AFRL5_3

    - -
    -
    - - - - -
    #define GPIO_AFRL_AFRL5_3   GPIO_AFRL_AFSEL5_3
    -
    - -
    -
    - -

    ◆ GPIO_AFRL_AFRL6

    - -
    -
    - - - - -
    #define GPIO_AFRL_AFRL6   GPIO_AFRL_AFSEL6
    -
    - -
    -
    - -

    ◆ GPIO_AFRL_AFRL6_0

    - -
    -
    - - - - -
    #define GPIO_AFRL_AFRL6_0   GPIO_AFRL_AFSEL6_0
    -
    - -
    -
    - -

    ◆ GPIO_AFRL_AFRL6_1

    - -
    -
    - - - - -
    #define GPIO_AFRL_AFRL6_1   GPIO_AFRL_AFSEL6_1
    -
    - -
    -
    - -

    ◆ GPIO_AFRL_AFRL6_2

    - -
    -
    - - - - -
    #define GPIO_AFRL_AFRL6_2   GPIO_AFRL_AFSEL6_2
    -
    - -
    -
    - -

    ◆ GPIO_AFRL_AFRL6_3

    - -
    -
    - - - - -
    #define GPIO_AFRL_AFRL6_3   GPIO_AFRL_AFSEL6_3
    -
    - -
    -
    - -

    ◆ GPIO_AFRL_AFRL7

    - -
    -
    - - - - -
    #define GPIO_AFRL_AFRL7   GPIO_AFRL_AFSEL7
    -
    - -
    -
    - -

    ◆ GPIO_AFRL_AFRL7_0

    - -
    -
    - - - - -
    #define GPIO_AFRL_AFRL7_0   GPIO_AFRL_AFSEL7_0
    -
    - -
    -
    - -

    ◆ GPIO_AFRL_AFRL7_1

    - -
    -
    - - - - -
    #define GPIO_AFRL_AFRL7_1   GPIO_AFRL_AFSEL7_1
    -
    - -
    -
    - -

    ◆ GPIO_AFRL_AFRL7_2

    - -
    -
    - - - - -
    #define GPIO_AFRL_AFRL7_2   GPIO_AFRL_AFSEL7_2
    -
    - -
    -
    - -

    ◆ GPIO_AFRL_AFRL7_3

    - -
    -
    - - - - -
    #define GPIO_AFRL_AFRL7_3   GPIO_AFRL_AFSEL7_3
    -
    - -
    -
    - -

    ◆ GPIO_AFRH_AFSEL8_Pos

    - -
    -
    - - - - -
    #define GPIO_AFRH_AFSEL8_Pos   (0U)
    -
    - -
    -
    - -

    ◆ GPIO_AFRH_AFSEL8_Msk

    - -
    -
    - - - - -
    #define GPIO_AFRH_AFSEL8_Msk   (0xFUL << GPIO_AFRH_AFSEL8_Pos)
    -
    -

    0x0000000F

    - -
    -
    - -

    ◆ GPIO_AFRH_AFSEL8

    - -
    -
    - - - - -
    #define GPIO_AFRH_AFSEL8   GPIO_AFRH_AFSEL8_Msk
    -
    - -
    -
    - -

    ◆ GPIO_AFRH_AFSEL8_0

    - -
    -
    - - - - -
    #define GPIO_AFRH_AFSEL8_0   (0x1UL << GPIO_AFRH_AFSEL8_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ GPIO_AFRH_AFSEL8_1

    - -
    -
    - - - - -
    #define GPIO_AFRH_AFSEL8_1   (0x2UL << GPIO_AFRH_AFSEL8_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ GPIO_AFRH_AFSEL8_2

    - -
    -
    - - - - -
    #define GPIO_AFRH_AFSEL8_2   (0x4UL << GPIO_AFRH_AFSEL8_Pos)
    -
    -

    0x00000004

    - -
    -
    - -

    ◆ GPIO_AFRH_AFSEL8_3

    - -
    -
    - - - - -
    #define GPIO_AFRH_AFSEL8_3   (0x8UL << GPIO_AFRH_AFSEL8_Pos)
    -
    -

    0x00000008

    - -
    -
    - -

    ◆ GPIO_AFRH_AFSEL9_Pos

    - -
    -
    - - - - -
    #define GPIO_AFRH_AFSEL9_Pos   (4U)
    -
    - -
    -
    - -

    ◆ GPIO_AFRH_AFSEL9_Msk

    - -
    -
    - - - - -
    #define GPIO_AFRH_AFSEL9_Msk   (0xFUL << GPIO_AFRH_AFSEL9_Pos)
    -
    -

    0x000000F0

    - -
    -
    - -

    ◆ GPIO_AFRH_AFSEL9

    - -
    -
    - - - - -
    #define GPIO_AFRH_AFSEL9   GPIO_AFRH_AFSEL9_Msk
    -
    - -
    -
    - -

    ◆ GPIO_AFRH_AFSEL9_0

    - -
    -
    - - - - -
    #define GPIO_AFRH_AFSEL9_0   (0x1UL << GPIO_AFRH_AFSEL9_Pos)
    -
    -

    0x00000010

    - -
    -
    - -

    ◆ GPIO_AFRH_AFSEL9_1

    - -
    -
    - - - - -
    #define GPIO_AFRH_AFSEL9_1   (0x2UL << GPIO_AFRH_AFSEL9_Pos)
    -
    -

    0x00000020

    - -
    -
    - -

    ◆ GPIO_AFRH_AFSEL9_2

    - -
    -
    - - - - -
    #define GPIO_AFRH_AFSEL9_2   (0x4UL << GPIO_AFRH_AFSEL9_Pos)
    -
    -

    0x00000040

    - -
    -
    - -

    ◆ GPIO_AFRH_AFSEL9_3

    - -
    -
    - - - - -
    #define GPIO_AFRH_AFSEL9_3   (0x8UL << GPIO_AFRH_AFSEL9_Pos)
    -
    -

    0x00000080

    - -
    -
    - -

    ◆ GPIO_AFRH_AFSEL10_Pos

    - -
    -
    - - - - -
    #define GPIO_AFRH_AFSEL10_Pos   (8U)
    -
    - -
    -
    - -

    ◆ GPIO_AFRH_AFSEL10_Msk

    - -
    -
    - - - - -
    #define GPIO_AFRH_AFSEL10_Msk   (0xFUL << GPIO_AFRH_AFSEL10_Pos)
    -
    -

    0x00000F00

    - -
    -
    - -

    ◆ GPIO_AFRH_AFSEL10

    - -
    -
    - - - - -
    #define GPIO_AFRH_AFSEL10   GPIO_AFRH_AFSEL10_Msk
    -
    - -
    -
    - -

    ◆ GPIO_AFRH_AFSEL10_0

    - -
    -
    - - - - -
    #define GPIO_AFRH_AFSEL10_0   (0x1UL << GPIO_AFRH_AFSEL10_Pos)
    -
    -

    0x00000100

    - -
    -
    - -

    ◆ GPIO_AFRH_AFSEL10_1

    - -
    -
    - - - - -
    #define GPIO_AFRH_AFSEL10_1   (0x2UL << GPIO_AFRH_AFSEL10_Pos)
    -
    -

    0x00000200

    - -
    -
    - -

    ◆ GPIO_AFRH_AFSEL10_2

    - -
    -
    - - - - -
    #define GPIO_AFRH_AFSEL10_2   (0x4UL << GPIO_AFRH_AFSEL10_Pos)
    -
    -

    0x00000400

    - -
    -
    - -

    ◆ GPIO_AFRH_AFSEL10_3

    - -
    -
    - - - - -
    #define GPIO_AFRH_AFSEL10_3   (0x8UL << GPIO_AFRH_AFSEL10_Pos)
    -
    -

    0x00000800

    - -
    -
    - -

    ◆ GPIO_AFRH_AFSEL11_Pos

    - -
    -
    - - - - -
    #define GPIO_AFRH_AFSEL11_Pos   (12U)
    -
    - -
    -
    - -

    ◆ GPIO_AFRH_AFSEL11_Msk

    - -
    -
    - - - - -
    #define GPIO_AFRH_AFSEL11_Msk   (0xFUL << GPIO_AFRH_AFSEL11_Pos)
    -
    -

    0x0000F000

    - -
    -
    - -

    ◆ GPIO_AFRH_AFSEL11

    - -
    -
    - - - - -
    #define GPIO_AFRH_AFSEL11   GPIO_AFRH_AFSEL11_Msk
    -
    - -
    -
    - -

    ◆ GPIO_AFRH_AFSEL11_0

    - -
    -
    - - - - -
    #define GPIO_AFRH_AFSEL11_0   (0x1UL << GPIO_AFRH_AFSEL11_Pos)
    -
    -

    0x00001000

    - -
    -
    - -

    ◆ GPIO_AFRH_AFSEL11_1

    - -
    -
    - - - - -
    #define GPIO_AFRH_AFSEL11_1   (0x2UL << GPIO_AFRH_AFSEL11_Pos)
    -
    -

    0x00002000

    - -
    -
    - -

    ◆ GPIO_AFRH_AFSEL11_2

    - -
    -
    - - - - -
    #define GPIO_AFRH_AFSEL11_2   (0x4UL << GPIO_AFRH_AFSEL11_Pos)
    -
    -

    0x00004000

    - -
    -
    - -

    ◆ GPIO_AFRH_AFSEL11_3

    - -
    -
    - - - - -
    #define GPIO_AFRH_AFSEL11_3   (0x8UL << GPIO_AFRH_AFSEL11_Pos)
    -
    -

    0x00008000

    - -
    -
    - -

    ◆ GPIO_AFRH_AFSEL12_Pos

    - -
    -
    - - - - -
    #define GPIO_AFRH_AFSEL12_Pos   (16U)
    -
    - -
    -
    - -

    ◆ GPIO_AFRH_AFSEL12_Msk

    - -
    -
    - - - - -
    #define GPIO_AFRH_AFSEL12_Msk   (0xFUL << GPIO_AFRH_AFSEL12_Pos)
    -
    -

    0x000F0000

    - -
    -
    - -

    ◆ GPIO_AFRH_AFSEL12

    - -
    -
    - - - - -
    #define GPIO_AFRH_AFSEL12   GPIO_AFRH_AFSEL12_Msk
    -
    - -
    -
    - -

    ◆ GPIO_AFRH_AFSEL12_0

    - -
    -
    - - - - -
    #define GPIO_AFRH_AFSEL12_0   (0x1UL << GPIO_AFRH_AFSEL12_Pos)
    -
    -

    0x00010000

    - -
    -
    - -

    ◆ GPIO_AFRH_AFSEL12_1

    - -
    -
    - - - - -
    #define GPIO_AFRH_AFSEL12_1   (0x2UL << GPIO_AFRH_AFSEL12_Pos)
    -
    -

    0x00020000

    - -
    -
    - -

    ◆ GPIO_AFRH_AFSEL12_2

    - -
    -
    - - - - -
    #define GPIO_AFRH_AFSEL12_2   (0x4UL << GPIO_AFRH_AFSEL12_Pos)
    -
    -

    0x00040000

    - -
    -
    - -

    ◆ GPIO_AFRH_AFSEL12_3

    - -
    -
    - - - - -
    #define GPIO_AFRH_AFSEL12_3   (0x8UL << GPIO_AFRH_AFSEL12_Pos)
    -
    -

    0x00080000

    - -
    -
    - -

    ◆ GPIO_AFRH_AFSEL13_Pos

    - -
    -
    - - - - -
    #define GPIO_AFRH_AFSEL13_Pos   (20U)
    -
    - -
    -
    - -

    ◆ GPIO_AFRH_AFSEL13_Msk

    - -
    -
    - - - - -
    #define GPIO_AFRH_AFSEL13_Msk   (0xFUL << GPIO_AFRH_AFSEL13_Pos)
    -
    -

    0x00F00000

    - -
    -
    - -

    ◆ GPIO_AFRH_AFSEL13

    - -
    -
    - - - - -
    #define GPIO_AFRH_AFSEL13   GPIO_AFRH_AFSEL13_Msk
    -
    - -
    -
    - -

    ◆ GPIO_AFRH_AFSEL13_0

    - -
    -
    - - - - -
    #define GPIO_AFRH_AFSEL13_0   (0x1UL << GPIO_AFRH_AFSEL13_Pos)
    -
    -

    0x00100000

    - -
    -
    - -

    ◆ GPIO_AFRH_AFSEL13_1

    - -
    -
    - - - - -
    #define GPIO_AFRH_AFSEL13_1   (0x2UL << GPIO_AFRH_AFSEL13_Pos)
    -
    -

    0x00200000

    - -
    -
    - -

    ◆ GPIO_AFRH_AFSEL13_2

    - -
    -
    - - - - -
    #define GPIO_AFRH_AFSEL13_2   (0x4UL << GPIO_AFRH_AFSEL13_Pos)
    -
    -

    0x00400000

    - -
    -
    - -

    ◆ GPIO_AFRH_AFSEL13_3

    - -
    -
    - - - - -
    #define GPIO_AFRH_AFSEL13_3   (0x8UL << GPIO_AFRH_AFSEL13_Pos)
    -
    -

    0x00800000

    - -
    -
    - -

    ◆ GPIO_AFRH_AFSEL14_Pos

    - -
    -
    - - - - -
    #define GPIO_AFRH_AFSEL14_Pos   (24U)
    -
    - -
    -
    - -

    ◆ GPIO_AFRH_AFSEL14_Msk

    - -
    -
    - - - - -
    #define GPIO_AFRH_AFSEL14_Msk   (0xFUL << GPIO_AFRH_AFSEL14_Pos)
    -
    -

    0x0F000000

    - -
    -
    - -

    ◆ GPIO_AFRH_AFSEL14

    - -
    -
    - - - - -
    #define GPIO_AFRH_AFSEL14   GPIO_AFRH_AFSEL14_Msk
    -
    - -
    -
    - -

    ◆ GPIO_AFRH_AFSEL14_0

    - -
    -
    - - - - -
    #define GPIO_AFRH_AFSEL14_0   (0x1UL << GPIO_AFRH_AFSEL14_Pos)
    -
    -

    0x01000000

    - -
    -
    - -

    ◆ GPIO_AFRH_AFSEL14_1

    - -
    -
    - - - - -
    #define GPIO_AFRH_AFSEL14_1   (0x2UL << GPIO_AFRH_AFSEL14_Pos)
    -
    -

    0x02000000

    - -
    -
    - -

    ◆ GPIO_AFRH_AFSEL14_2

    - -
    -
    - - - - -
    #define GPIO_AFRH_AFSEL14_2   (0x4UL << GPIO_AFRH_AFSEL14_Pos)
    -
    -

    0x04000000

    - -
    -
    - -

    ◆ GPIO_AFRH_AFSEL14_3

    - -
    -
    - - - - -
    #define GPIO_AFRH_AFSEL14_3   (0x8UL << GPIO_AFRH_AFSEL14_Pos)
    -
    -

    0x08000000

    - -
    -
    - -

    ◆ GPIO_AFRH_AFSEL15_Pos

    - -
    -
    - - - - -
    #define GPIO_AFRH_AFSEL15_Pos   (28U)
    -
    - -
    -
    - -

    ◆ GPIO_AFRH_AFSEL15_Msk

    - -
    -
    - - - - -
    #define GPIO_AFRH_AFSEL15_Msk   (0xFUL << GPIO_AFRH_AFSEL15_Pos)
    -
    -

    0xF0000000

    - -
    -
    - -

    ◆ GPIO_AFRH_AFSEL15

    - -
    -
    - - - - -
    #define GPIO_AFRH_AFSEL15   GPIO_AFRH_AFSEL15_Msk
    -
    - -
    -
    - -

    ◆ GPIO_AFRH_AFSEL15_0

    - -
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    #define GPIO_AFRH_AFSEL15_0   (0x1UL << GPIO_AFRH_AFSEL15_Pos)
    -
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    0x10000000

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    ◆ GPIO_AFRH_AFSEL15_1

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    #define GPIO_AFRH_AFSEL15_1   (0x2UL << GPIO_AFRH_AFSEL15_Pos)
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    0x20000000

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    ◆ GPIO_AFRH_AFSEL15_2

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    #define GPIO_AFRH_AFSEL15_2   (0x4UL << GPIO_AFRH_AFSEL15_Pos)
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    0x40000000

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    ◆ GPIO_AFRH_AFSEL15_3

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    #define GPIO_AFRH_AFSEL15_3   (0x8UL << GPIO_AFRH_AFSEL15_Pos)
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    0x80000000

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    ◆ GPIO_AFRH_AFRH0

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    #define GPIO_AFRH_AFRH0   GPIO_AFRH_AFSEL8
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    ◆ GPIO_AFRH_AFRH0_0

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    #define GPIO_AFRH_AFRH0_0   GPIO_AFRH_AFSEL8_0
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    ◆ GPIO_AFRH_AFRH0_1

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    #define GPIO_AFRH_AFRH0_1   GPIO_AFRH_AFSEL8_1
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    ◆ GPIO_AFRH_AFRH0_2

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    #define GPIO_AFRH_AFRH0_2   GPIO_AFRH_AFSEL8_2
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    ◆ GPIO_AFRH_AFRH0_3

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    #define GPIO_AFRH_AFRH0_3   GPIO_AFRH_AFSEL8_3
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    ◆ GPIO_AFRH_AFRH1

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    #define GPIO_AFRH_AFRH1   GPIO_AFRH_AFSEL9
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    ◆ GPIO_AFRH_AFRH1_0

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    #define GPIO_AFRH_AFRH1_0   GPIO_AFRH_AFSEL9_0
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    ◆ GPIO_AFRH_AFRH1_1

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    #define GPIO_AFRH_AFRH1_1   GPIO_AFRH_AFSEL9_1
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    ◆ GPIO_AFRH_AFRH1_2

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    #define GPIO_AFRH_AFRH1_2   GPIO_AFRH_AFSEL9_2
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    ◆ GPIO_AFRH_AFRH1_3

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    #define GPIO_AFRH_AFRH1_3   GPIO_AFRH_AFSEL9_3
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    ◆ GPIO_AFRH_AFRH2

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    #define GPIO_AFRH_AFRH2   GPIO_AFRH_AFSEL10
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    ◆ GPIO_AFRH_AFRH2_0

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    #define GPIO_AFRH_AFRH2_0   GPIO_AFRH_AFSEL10_0
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    ◆ GPIO_AFRH_AFRH2_1

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    #define GPIO_AFRH_AFRH2_1   GPIO_AFRH_AFSEL10_1
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    ◆ GPIO_AFRH_AFRH2_2

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    #define GPIO_AFRH_AFRH2_2   GPIO_AFRH_AFSEL10_2
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    ◆ GPIO_AFRH_AFRH2_3

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    #define GPIO_AFRH_AFRH2_3   GPIO_AFRH_AFSEL10_3
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    ◆ GPIO_AFRH_AFRH3

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    #define GPIO_AFRH_AFRH3   GPIO_AFRH_AFSEL11
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    ◆ GPIO_AFRH_AFRH3_0

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    #define GPIO_AFRH_AFRH3_0   GPIO_AFRH_AFSEL11_0
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    ◆ GPIO_AFRH_AFRH3_1

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    #define GPIO_AFRH_AFRH3_1   GPIO_AFRH_AFSEL11_1
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    ◆ GPIO_AFRH_AFRH3_2

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    #define GPIO_AFRH_AFRH3_2   GPIO_AFRH_AFSEL11_2
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    ◆ GPIO_AFRH_AFRH3_3

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    #define GPIO_AFRH_AFRH3_3   GPIO_AFRH_AFSEL11_3
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    ◆ GPIO_AFRH_AFRH4

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    #define GPIO_AFRH_AFRH4   GPIO_AFRH_AFSEL12
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    ◆ GPIO_AFRH_AFRH4_0

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    #define GPIO_AFRH_AFRH4_0   GPIO_AFRH_AFSEL12_0
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    ◆ GPIO_AFRH_AFRH4_1

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    #define GPIO_AFRH_AFRH4_1   GPIO_AFRH_AFSEL12_1
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    ◆ GPIO_AFRH_AFRH4_2

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    #define GPIO_AFRH_AFRH4_2   GPIO_AFRH_AFSEL12_2
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    ◆ GPIO_AFRH_AFRH4_3

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    #define GPIO_AFRH_AFRH4_3   GPIO_AFRH_AFSEL12_3
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    ◆ GPIO_AFRH_AFRH5

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    #define GPIO_AFRH_AFRH5   GPIO_AFRH_AFSEL13
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    ◆ GPIO_AFRH_AFRH5_0

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    #define GPIO_AFRH_AFRH5_0   GPIO_AFRH_AFSEL13_0
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    ◆ GPIO_AFRH_AFRH5_1

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    #define GPIO_AFRH_AFRH5_1   GPIO_AFRH_AFSEL13_1
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    ◆ GPIO_AFRH_AFRH5_2

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    #define GPIO_AFRH_AFRH5_2   GPIO_AFRH_AFSEL13_2
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    ◆ GPIO_AFRH_AFRH5_3

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    #define GPIO_AFRH_AFRH5_3   GPIO_AFRH_AFSEL13_3
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    ◆ GPIO_AFRH_AFRH6

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    #define GPIO_AFRH_AFRH6   GPIO_AFRH_AFSEL14
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    ◆ GPIO_AFRH_AFRH6_0

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    #define GPIO_AFRH_AFRH6_0   GPIO_AFRH_AFSEL14_0
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    ◆ GPIO_AFRH_AFRH6_1

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    #define GPIO_AFRH_AFRH6_1   GPIO_AFRH_AFSEL14_1
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    ◆ GPIO_AFRH_AFRH6_2

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    #define GPIO_AFRH_AFRH6_2   GPIO_AFRH_AFSEL14_2
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    ◆ GPIO_AFRH_AFRH6_3

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    #define GPIO_AFRH_AFRH6_3   GPIO_AFRH_AFSEL14_3
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    ◆ GPIO_AFRH_AFRH7

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    #define GPIO_AFRH_AFRH7   GPIO_AFRH_AFSEL15
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    ◆ GPIO_AFRH_AFRH7_0

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    #define GPIO_AFRH_AFRH7_0   GPIO_AFRH_AFSEL15_0
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    ◆ GPIO_AFRH_AFRH7_1

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    #define GPIO_AFRH_AFRH7_1   GPIO_AFRH_AFSEL15_1
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    ◆ GPIO_AFRH_AFRH7_2

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    #define GPIO_AFRH_AFRH7_2   GPIO_AFRH_AFSEL15_2
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    ◆ GPIO_AFRH_AFRH7_3

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    #define GPIO_AFRH_AFRH7_3   GPIO_AFRH_AFSEL15_3
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    ◆ I2C_CR1_PE_Pos

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    #define I2C_CR1_PE_Pos   (0U)
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    ◆ I2C_CR1_PE_Msk

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    #define I2C_CR1_PE_Msk   (0x1UL << I2C_CR1_PE_Pos)
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    0x00000001

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    ◆ I2C_CR1_PE

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    #define I2C_CR1_PE   I2C_CR1_PE_Msk
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    Peripheral Enable
    -

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    ◆ I2C_CR1_SMBUS_Pos

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    #define I2C_CR1_SMBUS_Pos   (1U)
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    ◆ I2C_CR1_SMBUS_Msk

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    #define I2C_CR1_SMBUS_Msk   (0x1UL << I2C_CR1_SMBUS_Pos)
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    0x00000002

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    ◆ I2C_CR1_SMBUS

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    #define I2C_CR1_SMBUS   I2C_CR1_SMBUS_Msk
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    SMBus Mode
    -

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    ◆ I2C_CR1_SMBTYPE_Pos

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    #define I2C_CR1_SMBTYPE_Pos   (3U)
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    ◆ I2C_CR1_SMBTYPE_Msk

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    #define I2C_CR1_SMBTYPE_Msk   (0x1UL << I2C_CR1_SMBTYPE_Pos)
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    0x00000008

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    ◆ I2C_CR1_SMBTYPE

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    #define I2C_CR1_SMBTYPE   I2C_CR1_SMBTYPE_Msk
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    SMBus Type
    -

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    ◆ I2C_CR1_ENARP_Pos

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    #define I2C_CR1_ENARP_Pos   (4U)
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    ◆ I2C_CR1_ENARP_Msk

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    #define I2C_CR1_ENARP_Msk   (0x1UL << I2C_CR1_ENARP_Pos)
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    0x00000010

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    ◆ I2C_CR1_ENARP

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    #define I2C_CR1_ENARP   I2C_CR1_ENARP_Msk
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    ARP Enable
    -

    - -
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    ◆ I2C_CR1_ENPEC_Pos

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    #define I2C_CR1_ENPEC_Pos   (5U)
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    ◆ I2C_CR1_ENPEC_Msk

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    #define I2C_CR1_ENPEC_Msk   (0x1UL << I2C_CR1_ENPEC_Pos)
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    0x00000020

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    ◆ I2C_CR1_ENPEC

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    #define I2C_CR1_ENPEC   I2C_CR1_ENPEC_Msk
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    PEC Enable
    -

    - -
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    ◆ I2C_CR1_ENGC_Pos

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    #define I2C_CR1_ENGC_Pos   (6U)
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    ◆ I2C_CR1_ENGC_Msk

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    #define I2C_CR1_ENGC_Msk   (0x1UL << I2C_CR1_ENGC_Pos)
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    0x00000040

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    ◆ I2C_CR1_ENGC

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    #define I2C_CR1_ENGC   I2C_CR1_ENGC_Msk
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    General Call Enable
    -

    - -
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    ◆ I2C_CR1_NOSTRETCH_Pos

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    #define I2C_CR1_NOSTRETCH_Pos   (7U)
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    ◆ I2C_CR1_NOSTRETCH_Msk

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    #define I2C_CR1_NOSTRETCH_Msk   (0x1UL << I2C_CR1_NOSTRETCH_Pos)
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    0x00000080

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    ◆ I2C_CR1_NOSTRETCH

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    #define I2C_CR1_NOSTRETCH   I2C_CR1_NOSTRETCH_Msk
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    Clock Stretching Disable (Slave mode)
    -

    - -
    -
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    ◆ I2C_CR1_START_Pos

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    #define I2C_CR1_START_Pos   (8U)
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    ◆ I2C_CR1_START_Msk

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    #define I2C_CR1_START_Msk   (0x1UL << I2C_CR1_START_Pos)
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    0x00000100

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    ◆ I2C_CR1_START

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    #define I2C_CR1_START   I2C_CR1_START_Msk
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    Start Generation
    -

    - -
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    ◆ I2C_CR1_STOP_Pos

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    #define I2C_CR1_STOP_Pos   (9U)
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    ◆ I2C_CR1_STOP_Msk

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    #define I2C_CR1_STOP_Msk   (0x1UL << I2C_CR1_STOP_Pos)
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    0x00000200

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    ◆ I2C_CR1_STOP

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    #define I2C_CR1_STOP   I2C_CR1_STOP_Msk
    -
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    Stop Generation
    -

    - -
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    ◆ I2C_CR1_ACK_Pos

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    #define I2C_CR1_ACK_Pos   (10U)
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    ◆ I2C_CR1_ACK_Msk

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    #define I2C_CR1_ACK_Msk   (0x1UL << I2C_CR1_ACK_Pos)
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    0x00000400

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    ◆ I2C_CR1_ACK

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    #define I2C_CR1_ACK   I2C_CR1_ACK_Msk
    -
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    Acknowledge Enable
    -

    - -
    -
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    ◆ I2C_CR1_POS_Pos

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    #define I2C_CR1_POS_Pos   (11U)
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    ◆ I2C_CR1_POS_Msk

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    #define I2C_CR1_POS_Msk   (0x1UL << I2C_CR1_POS_Pos)
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    -

    0x00000800

    - -
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    ◆ I2C_CR1_POS

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    #define I2C_CR1_POS   I2C_CR1_POS_Msk
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    Acknowledge/PEC Position (for data reception)

    - -
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    ◆ I2C_CR1_PEC_Pos

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    #define I2C_CR1_PEC_Pos   (12U)
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    ◆ I2C_CR1_PEC_Msk

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    #define I2C_CR1_PEC_Msk   (0x1UL << I2C_CR1_PEC_Pos)
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    0x00001000

    - -
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    ◆ I2C_CR1_PEC

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    #define I2C_CR1_PEC   I2C_CR1_PEC_Msk
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    Packet Error Checking
    -

    - -
    -
    - -

    ◆ I2C_CR1_ALERT_Pos

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    #define I2C_CR1_ALERT_Pos   (13U)
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    ◆ I2C_CR1_ALERT_Msk

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    #define I2C_CR1_ALERT_Msk   (0x1UL << I2C_CR1_ALERT_Pos)
    -
    -

    0x00002000

    - -
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    ◆ I2C_CR1_ALERT

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    #define I2C_CR1_ALERT   I2C_CR1_ALERT_Msk
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    -

    SMBus Alert
    -

    - -
    -
    - -

    ◆ I2C_CR1_SWRST_Pos

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    #define I2C_CR1_SWRST_Pos   (15U)
    -
    - -
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    ◆ I2C_CR1_SWRST_Msk

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    #define I2C_CR1_SWRST_Msk   (0x1UL << I2C_CR1_SWRST_Pos)
    -
    -

    0x00008000

    - -
    -
    - -

    ◆ I2C_CR1_SWRST

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    #define I2C_CR1_SWRST   I2C_CR1_SWRST_Msk
    -
    -

    Software Reset
    -

    - -
    -
    - -

    ◆ I2C_CR2_FREQ_Pos

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    #define I2C_CR2_FREQ_Pos   (0U)
    -
    - -
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    ◆ I2C_CR2_FREQ_Msk

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    #define I2C_CR2_FREQ_Msk   (0x3FUL << I2C_CR2_FREQ_Pos)
    -
    -

    0x0000003F

    - -
    -
    - -

    ◆ I2C_CR2_FREQ

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    #define I2C_CR2_FREQ   I2C_CR2_FREQ_Msk
    -
    -

    FREQ[5:0] bits (Peripheral Clock Frequency)
    -

    - -
    -
    - -

    ◆ I2C_CR2_FREQ_0

    - -
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    #define I2C_CR2_FREQ_0   (0x01UL << I2C_CR2_FREQ_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ I2C_CR2_FREQ_1

    - -
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    #define I2C_CR2_FREQ_1   (0x02UL << I2C_CR2_FREQ_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ I2C_CR2_FREQ_2

    - -
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    #define I2C_CR2_FREQ_2   (0x04UL << I2C_CR2_FREQ_Pos)
    -
    -

    0x00000004

    - -
    -
    - -

    ◆ I2C_CR2_FREQ_3

    - -
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    #define I2C_CR2_FREQ_3   (0x08UL << I2C_CR2_FREQ_Pos)
    -
    -

    0x00000008

    - -
    -
    - -

    ◆ I2C_CR2_FREQ_4

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    #define I2C_CR2_FREQ_4   (0x10UL << I2C_CR2_FREQ_Pos)
    -
    -

    0x00000010

    - -
    -
    - -

    ◆ I2C_CR2_FREQ_5

    - -
    -
    - - - - -
    #define I2C_CR2_FREQ_5   (0x20UL << I2C_CR2_FREQ_Pos)
    -
    -

    0x00000020

    - -
    -
    - -

    ◆ I2C_CR2_ITERREN_Pos

    - -
    -
    - - - - -
    #define I2C_CR2_ITERREN_Pos   (8U)
    -
    - -
    -
    - -

    ◆ I2C_CR2_ITERREN_Msk

    - -
    -
    - - - - -
    #define I2C_CR2_ITERREN_Msk   (0x1UL << I2C_CR2_ITERREN_Pos)
    -
    -

    0x00000100

    - -
    -
    - -

    ◆ I2C_CR2_ITERREN

    - -
    -
    - - - - -
    #define I2C_CR2_ITERREN   I2C_CR2_ITERREN_Msk
    -
    -

    Error Interrupt Enable
    -

    - -
    -
    - -

    ◆ I2C_CR2_ITEVTEN_Pos

    - -
    -
    - - - - -
    #define I2C_CR2_ITEVTEN_Pos   (9U)
    -
    - -
    -
    - -

    ◆ I2C_CR2_ITEVTEN_Msk

    - -
    -
    - - - - -
    #define I2C_CR2_ITEVTEN_Msk   (0x1UL << I2C_CR2_ITEVTEN_Pos)
    -
    -

    0x00000200

    - -
    -
    - -

    ◆ I2C_CR2_ITEVTEN

    - -
    -
    - - - - -
    #define I2C_CR2_ITEVTEN   I2C_CR2_ITEVTEN_Msk
    -
    -

    Event Interrupt Enable
    -

    - -
    -
    - -

    ◆ I2C_CR2_ITBUFEN_Pos

    - -
    -
    - - - - -
    #define I2C_CR2_ITBUFEN_Pos   (10U)
    -
    - -
    -
    - -

    ◆ I2C_CR2_ITBUFEN_Msk

    - -
    -
    - - - - -
    #define I2C_CR2_ITBUFEN_Msk   (0x1UL << I2C_CR2_ITBUFEN_Pos)
    -
    -

    0x00000400

    - -
    -
    - -

    ◆ I2C_CR2_ITBUFEN

    - -
    -
    - - - - -
    #define I2C_CR2_ITBUFEN   I2C_CR2_ITBUFEN_Msk
    -
    -

    Buffer Interrupt Enable

    - -
    -
    - -

    ◆ I2C_CR2_DMAEN_Pos

    - -
    -
    - - - - -
    #define I2C_CR2_DMAEN_Pos   (11U)
    -
    - -
    -
    - -

    ◆ I2C_CR2_DMAEN_Msk

    - -
    -
    - - - - -
    #define I2C_CR2_DMAEN_Msk   (0x1UL << I2C_CR2_DMAEN_Pos)
    -
    -

    0x00000800

    - -
    -
    - -

    ◆ I2C_CR2_DMAEN

    - -
    -
    - - - - -
    #define I2C_CR2_DMAEN   I2C_CR2_DMAEN_Msk
    -
    -

    DMA Requests Enable
    -

    - -
    -
    - -

    ◆ I2C_CR2_LAST_Pos

    - -
    -
    - - - - -
    #define I2C_CR2_LAST_Pos   (12U)
    -
    - -
    -
    - -

    ◆ I2C_CR2_LAST_Msk

    - -
    -
    - - - - -
    #define I2C_CR2_LAST_Msk   (0x1UL << I2C_CR2_LAST_Pos)
    -
    -

    0x00001000

    - -
    -
    - -

    ◆ I2C_CR2_LAST

    - -
    -
    - - - - -
    #define I2C_CR2_LAST   I2C_CR2_LAST_Msk
    -
    -

    DMA Last Transfer
    -

    - -
    -
    - -

    ◆ I2C_OAR1_ADD1_7

    - -
    -
    - - - - -
    #define I2C_OAR1_ADD1_7   0x000000FEU
    -
    -

    Interface Address

    - -
    -
    - -

    ◆ I2C_OAR1_ADD8_9

    - -
    -
    - - - - -
    #define I2C_OAR1_ADD8_9   0x00000300U
    -
    -

    Interface Address

    - -
    -
    - -

    ◆ I2C_OAR1_ADD0_Pos

    - -
    -
    - - - - -
    #define I2C_OAR1_ADD0_Pos   (0U)
    -
    - -
    -
    - -

    ◆ I2C_OAR1_ADD0_Msk

    - -
    -
    - - - - -
    #define I2C_OAR1_ADD0_Msk   (0x1UL << I2C_OAR1_ADD0_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ I2C_OAR1_ADD0

    - -
    -
    - - - - -
    #define I2C_OAR1_ADD0   I2C_OAR1_ADD0_Msk
    -
    -

    Bit 0

    - -
    -
    - -

    ◆ I2C_OAR1_ADD1_Pos

    - -
    -
    - - - - -
    #define I2C_OAR1_ADD1_Pos   (1U)
    -
    - -
    -
    - -

    ◆ I2C_OAR1_ADD1_Msk

    - -
    -
    - - - - -
    #define I2C_OAR1_ADD1_Msk   (0x1UL << I2C_OAR1_ADD1_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ I2C_OAR1_ADD1

    - -
    -
    - - - - -
    #define I2C_OAR1_ADD1   I2C_OAR1_ADD1_Msk
    -
    -

    Bit 1

    - -
    -
    - -

    ◆ I2C_OAR1_ADD2_Pos

    - -
    -
    - - - - -
    #define I2C_OAR1_ADD2_Pos   (2U)
    -
    - -
    -
    - -

    ◆ I2C_OAR1_ADD2_Msk

    - -
    -
    - - - - -
    #define I2C_OAR1_ADD2_Msk   (0x1UL << I2C_OAR1_ADD2_Pos)
    -
    -

    0x00000004

    - -
    -
    - -

    ◆ I2C_OAR1_ADD2

    - -
    -
    - - - - -
    #define I2C_OAR1_ADD2   I2C_OAR1_ADD2_Msk
    -
    -

    Bit 2

    - -
    -
    - -

    ◆ I2C_OAR1_ADD3_Pos

    - -
    -
    - - - - -
    #define I2C_OAR1_ADD3_Pos   (3U)
    -
    - -
    -
    - -

    ◆ I2C_OAR1_ADD3_Msk

    - -
    -
    - - - - -
    #define I2C_OAR1_ADD3_Msk   (0x1UL << I2C_OAR1_ADD3_Pos)
    -
    -

    0x00000008

    - -
    -
    - -

    ◆ I2C_OAR1_ADD3

    - -
    -
    - - - - -
    #define I2C_OAR1_ADD3   I2C_OAR1_ADD3_Msk
    -
    -

    Bit 3

    - -
    -
    - -

    ◆ I2C_OAR1_ADD4_Pos

    - -
    -
    - - - - -
    #define I2C_OAR1_ADD4_Pos   (4U)
    -
    - -
    -
    - -

    ◆ I2C_OAR1_ADD4_Msk

    - -
    -
    - - - - -
    #define I2C_OAR1_ADD4_Msk   (0x1UL << I2C_OAR1_ADD4_Pos)
    -
    -

    0x00000010

    - -
    -
    - -

    ◆ I2C_OAR1_ADD4

    - -
    -
    - - - - -
    #define I2C_OAR1_ADD4   I2C_OAR1_ADD4_Msk
    -
    -

    Bit 4

    - -
    -
    - -

    ◆ I2C_OAR1_ADD5_Pos

    - -
    -
    - - - - -
    #define I2C_OAR1_ADD5_Pos   (5U)
    -
    - -
    -
    - -

    ◆ I2C_OAR1_ADD5_Msk

    - -
    -
    - - - - -
    #define I2C_OAR1_ADD5_Msk   (0x1UL << I2C_OAR1_ADD5_Pos)
    -
    -

    0x00000020

    - -
    -
    - -

    ◆ I2C_OAR1_ADD5

    - -
    -
    - - - - -
    #define I2C_OAR1_ADD5   I2C_OAR1_ADD5_Msk
    -
    -

    Bit 5

    - -
    -
    - -

    ◆ I2C_OAR1_ADD6_Pos

    - -
    -
    - - - - -
    #define I2C_OAR1_ADD6_Pos   (6U)
    -
    - -
    -
    - -

    ◆ I2C_OAR1_ADD6_Msk

    - -
    -
    - - - - -
    #define I2C_OAR1_ADD6_Msk   (0x1UL << I2C_OAR1_ADD6_Pos)
    -
    -

    0x00000040

    - -
    -
    - -

    ◆ I2C_OAR1_ADD6

    - -
    -
    - - - - -
    #define I2C_OAR1_ADD6   I2C_OAR1_ADD6_Msk
    -
    -

    Bit 6

    - -
    -
    - -

    ◆ I2C_OAR1_ADD7_Pos

    - -
    -
    - - - - -
    #define I2C_OAR1_ADD7_Pos   (7U)
    -
    - -
    -
    - -

    ◆ I2C_OAR1_ADD7_Msk

    - -
    -
    - - - - -
    #define I2C_OAR1_ADD7_Msk   (0x1UL << I2C_OAR1_ADD7_Pos)
    -
    -

    0x00000080

    - -
    -
    - -

    ◆ I2C_OAR1_ADD7

    - -
    -
    - - - - -
    #define I2C_OAR1_ADD7   I2C_OAR1_ADD7_Msk
    -
    -

    Bit 7

    - -
    -
    - -

    ◆ I2C_OAR1_ADD8_Pos

    - -
    -
    - - - - -
    #define I2C_OAR1_ADD8_Pos   (8U)
    -
    - -
    -
    - -

    ◆ I2C_OAR1_ADD8_Msk

    - -
    -
    - - - - -
    #define I2C_OAR1_ADD8_Msk   (0x1UL << I2C_OAR1_ADD8_Pos)
    -
    -

    0x00000100

    - -
    -
    - -

    ◆ I2C_OAR1_ADD8

    - -
    -
    - - - - -
    #define I2C_OAR1_ADD8   I2C_OAR1_ADD8_Msk
    -
    -

    Bit 8

    - -
    -
    - -

    ◆ I2C_OAR1_ADD9_Pos

    - -
    -
    - - - - -
    #define I2C_OAR1_ADD9_Pos   (9U)
    -
    - -
    -
    - -

    ◆ I2C_OAR1_ADD9_Msk

    - -
    -
    - - - - -
    #define I2C_OAR1_ADD9_Msk   (0x1UL << I2C_OAR1_ADD9_Pos)
    -
    -

    0x00000200

    - -
    -
    - -

    ◆ I2C_OAR1_ADD9

    - -
    -
    - - - - -
    #define I2C_OAR1_ADD9   I2C_OAR1_ADD9_Msk
    -
    -

    Bit 9

    - -
    -
    - -

    ◆ I2C_OAR1_ADDMODE_Pos

    - -
    -
    - - - - -
    #define I2C_OAR1_ADDMODE_Pos   (15U)
    -
    - -
    -
    - -

    ◆ I2C_OAR1_ADDMODE_Msk

    - -
    -
    - - - - -
    #define I2C_OAR1_ADDMODE_Msk   (0x1UL << I2C_OAR1_ADDMODE_Pos)
    -
    -

    0x00008000

    - -
    -
    - -

    ◆ I2C_OAR1_ADDMODE

    - -
    -
    - - - - -
    #define I2C_OAR1_ADDMODE   I2C_OAR1_ADDMODE_Msk
    -
    -

    Addressing Mode (Slave mode)

    - -
    -
    - -

    ◆ I2C_OAR2_ENDUAL_Pos

    - -
    -
    - - - - -
    #define I2C_OAR2_ENDUAL_Pos   (0U)
    -
    - -
    -
    - -

    ◆ I2C_OAR2_ENDUAL_Msk

    - -
    -
    - - - - -
    #define I2C_OAR2_ENDUAL_Msk   (0x1UL << I2C_OAR2_ENDUAL_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ I2C_OAR2_ENDUAL

    - -
    -
    - - - - -
    #define I2C_OAR2_ENDUAL   I2C_OAR2_ENDUAL_Msk
    -
    -

    Dual addressing mode enable

    - -
    -
    - -

    ◆ I2C_OAR2_ADD2_Pos

    - -
    -
    - - - - -
    #define I2C_OAR2_ADD2_Pos   (1U)
    -
    - -
    -
    - -

    ◆ I2C_OAR2_ADD2_Msk

    - -
    -
    - - - - -
    #define I2C_OAR2_ADD2_Msk   (0x7FUL << I2C_OAR2_ADD2_Pos)
    -
    -

    0x000000FE

    - -
    -
    - -

    ◆ I2C_OAR2_ADD2

    - -
    -
    - - - - -
    #define I2C_OAR2_ADD2   I2C_OAR2_ADD2_Msk
    -
    -

    Interface address
    -

    - -
    -
    - -

    ◆ I2C_DR_DR_Pos

    - -
    -
    - - - - -
    #define I2C_DR_DR_Pos   (0U)
    -
    - -
    -
    - -

    ◆ I2C_DR_DR_Msk

    - -
    -
    - - - - -
    #define I2C_DR_DR_Msk   (0xFFUL << I2C_DR_DR_Pos)
    -
    -

    0x000000FF

    - -
    -
    - -

    ◆ I2C_DR_DR

    - -
    -
    - - - - -
    #define I2C_DR_DR   I2C_DR_DR_Msk
    -
    -

    8-bit Data Register
    -

    - -
    -
    - -

    ◆ I2C_SR1_SB_Pos

    - -
    -
    - - - - -
    #define I2C_SR1_SB_Pos   (0U)
    -
    - -
    -
    - -

    ◆ I2C_SR1_SB_Msk

    - -
    -
    - - - - -
    #define I2C_SR1_SB_Msk   (0x1UL << I2C_SR1_SB_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ I2C_SR1_SB

    - -
    -
    - - - - -
    #define I2C_SR1_SB   I2C_SR1_SB_Msk
    -
    -

    Start Bit (Master mode)
    -

    - -
    -
    - -

    ◆ I2C_SR1_ADDR_Pos

    - -
    -
    - - - - -
    #define I2C_SR1_ADDR_Pos   (1U)
    -
    - -
    -
    - -

    ◆ I2C_SR1_ADDR_Msk

    - -
    -
    - - - - -
    #define I2C_SR1_ADDR_Msk   (0x1UL << I2C_SR1_ADDR_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ I2C_SR1_ADDR

    - -
    -
    - - - - -
    #define I2C_SR1_ADDR   I2C_SR1_ADDR_Msk
    -
    -

    Address sent (master mode)/matched (slave mode)

    - -
    -
    - -

    ◆ I2C_SR1_BTF_Pos

    - -
    -
    - - - - -
    #define I2C_SR1_BTF_Pos   (2U)
    -
    - -
    -
    - -

    ◆ I2C_SR1_BTF_Msk

    - -
    -
    - - - - -
    #define I2C_SR1_BTF_Msk   (0x1UL << I2C_SR1_BTF_Pos)
    -
    -

    0x00000004

    - -
    -
    - -

    ◆ I2C_SR1_BTF

    - -
    -
    - - - - -
    #define I2C_SR1_BTF   I2C_SR1_BTF_Msk
    -
    -

    Byte Transfer Finished
    -

    - -
    -
    - -

    ◆ I2C_SR1_ADD10_Pos

    - -
    -
    - - - - -
    #define I2C_SR1_ADD10_Pos   (3U)
    -
    - -
    -
    - -

    ◆ I2C_SR1_ADD10_Msk

    - -
    -
    - - - - -
    #define I2C_SR1_ADD10_Msk   (0x1UL << I2C_SR1_ADD10_Pos)
    -
    -

    0x00000008

    - -
    -
    - -

    ◆ I2C_SR1_ADD10

    - -
    -
    - - - - -
    #define I2C_SR1_ADD10   I2C_SR1_ADD10_Msk
    -
    -

    10-bit header sent (Master mode)
    -

    - -
    -
    - -

    ◆ I2C_SR1_STOPF_Pos

    - -
    -
    - - - - -
    #define I2C_SR1_STOPF_Pos   (4U)
    -
    - -
    -
    - -

    ◆ I2C_SR1_STOPF_Msk

    - -
    -
    - - - - -
    #define I2C_SR1_STOPF_Msk   (0x1UL << I2C_SR1_STOPF_Pos)
    -
    -

    0x00000010

    - -
    -
    - -

    ◆ I2C_SR1_STOPF

    - -
    -
    - - - - -
    #define I2C_SR1_STOPF   I2C_SR1_STOPF_Msk
    -
    -

    Stop detection (Slave mode)
    -

    - -
    -
    - -

    ◆ I2C_SR1_RXNE_Pos

    - -
    -
    - - - - -
    #define I2C_SR1_RXNE_Pos   (6U)
    -
    - -
    -
    - -

    ◆ I2C_SR1_RXNE_Msk

    - -
    -
    - - - - -
    #define I2C_SR1_RXNE_Msk   (0x1UL << I2C_SR1_RXNE_Pos)
    -
    -

    0x00000040

    - -
    -
    - -

    ◆ I2C_SR1_RXNE

    - -
    -
    - - - - -
    #define I2C_SR1_RXNE   I2C_SR1_RXNE_Msk
    -
    -

    Data Register not Empty (receivers)
    -

    - -
    -
    - -

    ◆ I2C_SR1_TXE_Pos

    - -
    -
    - - - - -
    #define I2C_SR1_TXE_Pos   (7U)
    -
    - -
    -
    - -

    ◆ I2C_SR1_TXE_Msk

    - -
    -
    - - - - -
    #define I2C_SR1_TXE_Msk   (0x1UL << I2C_SR1_TXE_Pos)
    -
    -

    0x00000080

    - -
    -
    - -

    ◆ I2C_SR1_TXE

    - -
    -
    - - - - -
    #define I2C_SR1_TXE   I2C_SR1_TXE_Msk
    -
    -

    Data Register Empty (transmitters)
    -

    - -
    -
    - -

    ◆ I2C_SR1_BERR_Pos

    - -
    -
    - - - - -
    #define I2C_SR1_BERR_Pos   (8U)
    -
    - -
    -
    - -

    ◆ I2C_SR1_BERR_Msk

    - -
    -
    - - - - -
    #define I2C_SR1_BERR_Msk   (0x1UL << I2C_SR1_BERR_Pos)
    -
    -

    0x00000100

    - -
    -
    - -

    ◆ I2C_SR1_BERR

    - -
    -
    - - - - -
    #define I2C_SR1_BERR   I2C_SR1_BERR_Msk
    -
    -

    Bus Error
    -

    - -
    -
    - -

    ◆ I2C_SR1_ARLO_Pos

    - -
    -
    - - - - -
    #define I2C_SR1_ARLO_Pos   (9U)
    -
    - -
    -
    - -

    ◆ I2C_SR1_ARLO_Msk

    - -
    -
    - - - - -
    #define I2C_SR1_ARLO_Msk   (0x1UL << I2C_SR1_ARLO_Pos)
    -
    -

    0x00000200

    - -
    -
    - -

    ◆ I2C_SR1_ARLO

    - -
    -
    - - - - -
    #define I2C_SR1_ARLO   I2C_SR1_ARLO_Msk
    -
    -

    Arbitration Lost (master mode)
    -

    - -
    -
    - -

    ◆ I2C_SR1_AF_Pos

    - -
    -
    - - - - -
    #define I2C_SR1_AF_Pos   (10U)
    -
    - -
    -
    - -

    ◆ I2C_SR1_AF_Msk

    - -
    -
    - - - - -
    #define I2C_SR1_AF_Msk   (0x1UL << I2C_SR1_AF_Pos)
    -
    -

    0x00000400

    - -
    -
    - -

    ◆ I2C_SR1_AF

    - -
    -
    - - - - -
    #define I2C_SR1_AF   I2C_SR1_AF_Msk
    -
    -

    Acknowledge Failure
    -

    - -
    -
    - -

    ◆ I2C_SR1_OVR_Pos

    - -
    -
    - - - - -
    #define I2C_SR1_OVR_Pos   (11U)
    -
    - -
    -
    - -

    ◆ I2C_SR1_OVR_Msk

    - -
    -
    - - - - -
    #define I2C_SR1_OVR_Msk   (0x1UL << I2C_SR1_OVR_Pos)
    -
    -

    0x00000800

    - -
    -
    - -

    ◆ I2C_SR1_OVR

    - -
    -
    - - - - -
    #define I2C_SR1_OVR   I2C_SR1_OVR_Msk
    -
    -

    Overrun/Underrun
    -

    - -
    -
    - -

    ◆ I2C_SR1_PECERR_Pos

    - -
    -
    - - - - -
    #define I2C_SR1_PECERR_Pos   (12U)
    -
    - -
    -
    - -

    ◆ I2C_SR1_PECERR_Msk

    - -
    -
    - - - - -
    #define I2C_SR1_PECERR_Msk   (0x1UL << I2C_SR1_PECERR_Pos)
    -
    -

    0x00001000

    - -
    -
    - -

    ◆ I2C_SR1_PECERR

    - -
    -
    - - - - -
    #define I2C_SR1_PECERR   I2C_SR1_PECERR_Msk
    -
    -

    PEC Error in reception
    -

    - -
    -
    - -

    ◆ I2C_SR1_TIMEOUT_Pos

    - -
    -
    - - - - -
    #define I2C_SR1_TIMEOUT_Pos   (14U)
    -
    - -
    -
    - -

    ◆ I2C_SR1_TIMEOUT_Msk

    - -
    -
    - - - - -
    #define I2C_SR1_TIMEOUT_Msk   (0x1UL << I2C_SR1_TIMEOUT_Pos)
    -
    -

    0x00004000

    - -
    -
    - -

    ◆ I2C_SR1_TIMEOUT

    - -
    -
    - - - - -
    #define I2C_SR1_TIMEOUT   I2C_SR1_TIMEOUT_Msk
    -
    -

    Timeout or Tlow Error
    -

    - -
    -
    - -

    ◆ I2C_SR1_SMBALERT_Pos

    - -
    -
    - - - - -
    #define I2C_SR1_SMBALERT_Pos   (15U)
    -
    - -
    -
    - -

    ◆ I2C_SR1_SMBALERT_Msk

    - -
    -
    - - - - -
    #define I2C_SR1_SMBALERT_Msk   (0x1UL << I2C_SR1_SMBALERT_Pos)
    -
    -

    0x00008000

    - -
    -
    - -

    ◆ I2C_SR1_SMBALERT

    - -
    -
    - - - - -
    #define I2C_SR1_SMBALERT   I2C_SR1_SMBALERT_Msk
    -
    -

    SMBus Alert
    -

    - -
    -
    - -

    ◆ I2C_SR2_MSL_Pos

    - -
    -
    - - - - -
    #define I2C_SR2_MSL_Pos   (0U)
    -
    - -
    -
    - -

    ◆ I2C_SR2_MSL_Msk

    - -
    -
    - - - - -
    #define I2C_SR2_MSL_Msk   (0x1UL << I2C_SR2_MSL_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ I2C_SR2_MSL

    - -
    -
    - - - - -
    #define I2C_SR2_MSL   I2C_SR2_MSL_Msk
    -
    -

    Master/Slave
    -

    - -
    -
    - -

    ◆ I2C_SR2_BUSY_Pos

    - -
    -
    - - - - -
    #define I2C_SR2_BUSY_Pos   (1U)
    -
    - -
    -
    - -

    ◆ I2C_SR2_BUSY_Msk

    - -
    -
    - - - - -
    #define I2C_SR2_BUSY_Msk   (0x1UL << I2C_SR2_BUSY_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ I2C_SR2_BUSY

    - -
    -
    - - - - -
    #define I2C_SR2_BUSY   I2C_SR2_BUSY_Msk
    -
    -

    Bus Busy
    -

    - -
    -
    - -

    ◆ I2C_SR2_TRA_Pos

    - -
    -
    - - - - -
    #define I2C_SR2_TRA_Pos   (2U)
    -
    - -
    -
    - -

    ◆ I2C_SR2_TRA_Msk

    - -
    -
    - - - - -
    #define I2C_SR2_TRA_Msk   (0x1UL << I2C_SR2_TRA_Pos)
    -
    -

    0x00000004

    - -
    -
    - -

    ◆ I2C_SR2_TRA

    - -
    -
    - - - - -
    #define I2C_SR2_TRA   I2C_SR2_TRA_Msk
    -
    -

    Transmitter/Receiver
    -

    - -
    -
    - -

    ◆ I2C_SR2_GENCALL_Pos

    - -
    -
    - - - - -
    #define I2C_SR2_GENCALL_Pos   (4U)
    -
    - -
    -
    - -

    ◆ I2C_SR2_GENCALL_Msk

    - -
    -
    - - - - -
    #define I2C_SR2_GENCALL_Msk   (0x1UL << I2C_SR2_GENCALL_Pos)
    -
    -

    0x00000010

    - -
    -
    - -

    ◆ I2C_SR2_GENCALL

    - -
    -
    - - - - -
    #define I2C_SR2_GENCALL   I2C_SR2_GENCALL_Msk
    -
    -

    General Call Address (Slave mode)
    -

    - -
    -
    - -

    ◆ I2C_SR2_SMBDEFAULT_Pos

    - -
    -
    - - - - -
    #define I2C_SR2_SMBDEFAULT_Pos   (5U)
    -
    - -
    -
    - -

    ◆ I2C_SR2_SMBDEFAULT_Msk

    - -
    -
    - - - - -
    #define I2C_SR2_SMBDEFAULT_Msk   (0x1UL << I2C_SR2_SMBDEFAULT_Pos)
    -
    -

    0x00000020

    - -
    -
    - -

    ◆ I2C_SR2_SMBDEFAULT

    - -
    -
    - - - - -
    #define I2C_SR2_SMBDEFAULT   I2C_SR2_SMBDEFAULT_Msk
    -
    -

    SMBus Device Default Address (Slave mode)
    -

    - -
    -
    - -

    ◆ I2C_SR2_SMBHOST_Pos

    - -
    -
    - - - - -
    #define I2C_SR2_SMBHOST_Pos   (6U)
    -
    - -
    -
    - -

    ◆ I2C_SR2_SMBHOST_Msk

    - -
    -
    - - - - -
    #define I2C_SR2_SMBHOST_Msk   (0x1UL << I2C_SR2_SMBHOST_Pos)
    -
    -

    0x00000040

    - -
    -
    - -

    ◆ I2C_SR2_SMBHOST

    - -
    -
    - - - - -
    #define I2C_SR2_SMBHOST   I2C_SR2_SMBHOST_Msk
    -
    -

    SMBus Host Header (Slave mode)
    -

    - -
    -
    - -

    ◆ I2C_SR2_DUALF_Pos

    - -
    -
    - - - - -
    #define I2C_SR2_DUALF_Pos   (7U)
    -
    - -
    -
    - -

    ◆ I2C_SR2_DUALF_Msk

    - -
    -
    - - - - -
    #define I2C_SR2_DUALF_Msk   (0x1UL << I2C_SR2_DUALF_Pos)
    -
    -

    0x00000080

    - -
    -
    - -

    ◆ I2C_SR2_DUALF

    - -
    -
    - - - - -
    #define I2C_SR2_DUALF   I2C_SR2_DUALF_Msk
    -
    -

    Dual Flag (Slave mode)
    -

    - -
    -
    - -

    ◆ I2C_SR2_PEC_Pos

    - -
    -
    - - - - -
    #define I2C_SR2_PEC_Pos   (8U)
    -
    - -
    -
    - -

    ◆ I2C_SR2_PEC_Msk

    - -
    -
    - - - - -
    #define I2C_SR2_PEC_Msk   (0xFFUL << I2C_SR2_PEC_Pos)
    -
    -

    0x0000FF00

    - -
    -
    - -

    ◆ I2C_SR2_PEC

    - -
    -
    - - - - -
    #define I2C_SR2_PEC   I2C_SR2_PEC_Msk
    -
    -

    Packet Error Checking Register
    -

    - -
    -
    - -

    ◆ I2C_CCR_CCR_Pos

    - -
    -
    - - - - -
    #define I2C_CCR_CCR_Pos   (0U)
    -
    - -
    -
    - -

    ◆ I2C_CCR_CCR_Msk

    - -
    -
    - - - - -
    #define I2C_CCR_CCR_Msk   (0xFFFUL << I2C_CCR_CCR_Pos)
    -
    -

    0x00000FFF

    - -
    -
    - -

    ◆ I2C_CCR_CCR

    - -
    -
    - - - - -
    #define I2C_CCR_CCR   I2C_CCR_CCR_Msk
    -
    -

    Clock Control Register in Fast/Standard mode (Master mode)

    - -
    -
    - -

    ◆ I2C_CCR_DUTY_Pos

    - -
    -
    - - - - -
    #define I2C_CCR_DUTY_Pos   (14U)
    -
    - -
    -
    - -

    ◆ I2C_CCR_DUTY_Msk

    - -
    -
    - - - - -
    #define I2C_CCR_DUTY_Msk   (0x1UL << I2C_CCR_DUTY_Pos)
    -
    -

    0x00004000

    - -
    -
    - -

    ◆ I2C_CCR_DUTY

    - -
    -
    - - - - -
    #define I2C_CCR_DUTY   I2C_CCR_DUTY_Msk
    -
    -

    Fast Mode Duty Cycle
    -

    - -
    -
    - -

    ◆ I2C_CCR_FS_Pos

    - -
    -
    - - - - -
    #define I2C_CCR_FS_Pos   (15U)
    -
    - -
    -
    - -

    ◆ I2C_CCR_FS_Msk

    - -
    -
    - - - - -
    #define I2C_CCR_FS_Msk   (0x1UL << I2C_CCR_FS_Pos)
    -
    -

    0x00008000

    - -
    -
    - -

    ◆ I2C_CCR_FS

    - -
    -
    - - - - -
    #define I2C_CCR_FS   I2C_CCR_FS_Msk
    -
    -

    I2C Master Mode Selection
    -

    - -
    -
    - -

    ◆ I2C_TRISE_TRISE_Pos

    - -
    -
    - - - - -
    #define I2C_TRISE_TRISE_Pos   (0U)
    -
    - -
    -
    - -

    ◆ I2C_TRISE_TRISE_Msk

    - -
    -
    - - - - -
    #define I2C_TRISE_TRISE_Msk   (0x3FUL << I2C_TRISE_TRISE_Pos)
    -
    -

    0x0000003F

    - -
    -
    - -

    ◆ I2C_TRISE_TRISE

    - -
    -
    - - - - -
    #define I2C_TRISE_TRISE   I2C_TRISE_TRISE_Msk
    -
    -

    Maximum Rise Time in Fast/Standard mode (Master mode)

    - -
    -
    - -

    ◆ IWDG_KR_KEY_Pos

    - -
    -
    - - - - -
    #define IWDG_KR_KEY_Pos   (0U)
    -
    - -
    -
    - -

    ◆ IWDG_KR_KEY_Msk

    - -
    -
    - - - - -
    #define IWDG_KR_KEY_Msk   (0xFFFFUL << IWDG_KR_KEY_Pos)
    -
    -

    0x0000FFFF

    - -
    -
    - -

    ◆ IWDG_KR_KEY

    - -
    -
    - - - - -
    #define IWDG_KR_KEY   IWDG_KR_KEY_Msk
    -
    -

    Key value (write only, read 0000h)
    -

    - -
    -
    - -

    ◆ IWDG_PR_PR_Pos

    - -
    -
    - - - - -
    #define IWDG_PR_PR_Pos   (0U)
    -
    - -
    -
    - -

    ◆ IWDG_PR_PR_Msk

    - -
    -
    - - - - -
    #define IWDG_PR_PR_Msk   (0x7UL << IWDG_PR_PR_Pos)
    -
    -

    0x00000007

    - -
    -
    - -

    ◆ IWDG_PR_PR

    - -
    -
    - - - - -
    #define IWDG_PR_PR   IWDG_PR_PR_Msk
    -
    -

    PR[2:0] (Prescaler divider)
    -

    - -
    -
    - -

    ◆ IWDG_PR_PR_0

    - -
    -
    - - - - -
    #define IWDG_PR_PR_0   (0x1UL << IWDG_PR_PR_Pos)
    -
    -

    0x01

    - -
    -
    - -

    ◆ IWDG_PR_PR_1

    - -
    -
    - - - - -
    #define IWDG_PR_PR_1   (0x2UL << IWDG_PR_PR_Pos)
    -
    -

    0x02

    - -
    -
    - -

    ◆ IWDG_PR_PR_2

    - -
    -
    - - - - -
    #define IWDG_PR_PR_2   (0x4UL << IWDG_PR_PR_Pos)
    -
    -

    0x04

    - -
    -
    - -

    ◆ IWDG_RLR_RL_Pos

    - -
    -
    - - - - -
    #define IWDG_RLR_RL_Pos   (0U)
    -
    - -
    -
    - -

    ◆ IWDG_RLR_RL_Msk

    - -
    -
    - - - - -
    #define IWDG_RLR_RL_Msk   (0xFFFUL << IWDG_RLR_RL_Pos)
    -
    -

    0x00000FFF

    - -
    -
    - -

    ◆ IWDG_RLR_RL

    - -
    -
    - - - - -
    #define IWDG_RLR_RL   IWDG_RLR_RL_Msk
    -
    -

    Watchdog counter reload value
    -

    - -
    -
    - -

    ◆ IWDG_SR_PVU_Pos

    - -
    -
    - - - - -
    #define IWDG_SR_PVU_Pos   (0U)
    -
    - -
    -
    - -

    ◆ IWDG_SR_PVU_Msk

    - -
    -
    - - - - -
    #define IWDG_SR_PVU_Msk   (0x1UL << IWDG_SR_PVU_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ IWDG_SR_PVU

    - -
    -
    - - - - -
    #define IWDG_SR_PVU   IWDG_SR_PVU_Msk
    -
    -

    Watchdog prescaler value update
    -

    - -
    -
    - -

    ◆ IWDG_SR_RVU_Pos

    - -
    -
    - - - - -
    #define IWDG_SR_RVU_Pos   (1U)
    -
    - -
    -
    - -

    ◆ IWDG_SR_RVU_Msk

    - -
    -
    - - - - -
    #define IWDG_SR_RVU_Msk   (0x1UL << IWDG_SR_RVU_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ IWDG_SR_RVU

    - -
    -
    - - - - -
    #define IWDG_SR_RVU   IWDG_SR_RVU_Msk
    -
    -

    Watchdog counter reload value update

    - -
    -
    - -

    ◆ PWR_CR_LPDS_Pos

    - -
    -
    - - - - -
    #define PWR_CR_LPDS_Pos   (0U)
    -
    - -
    -
    - -

    ◆ PWR_CR_LPDS_Msk

    - -
    -
    - - - - -
    #define PWR_CR_LPDS_Msk   (0x1UL << PWR_CR_LPDS_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ PWR_CR_LPDS

    - -
    -
    - - - - -
    #define PWR_CR_LPDS   PWR_CR_LPDS_Msk
    -
    -

    Low-Power Deepsleep
    -

    - -
    -
    - -

    ◆ PWR_CR_PDDS_Pos

    - -
    -
    - - - - -
    #define PWR_CR_PDDS_Pos   (1U)
    -
    - -
    -
    - -

    ◆ PWR_CR_PDDS_Msk

    - -
    -
    - - - - -
    #define PWR_CR_PDDS_Msk   (0x1UL << PWR_CR_PDDS_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ PWR_CR_PDDS

    - -
    -
    - - - - -
    #define PWR_CR_PDDS   PWR_CR_PDDS_Msk
    -
    -

    Power Down Deepsleep
    -

    - -
    -
    - -

    ◆ PWR_CR_CWUF_Pos

    - -
    -
    - - - - -
    #define PWR_CR_CWUF_Pos   (2U)
    -
    - -
    -
    - -

    ◆ PWR_CR_CWUF_Msk

    - -
    -
    - - - - -
    #define PWR_CR_CWUF_Msk   (0x1UL << PWR_CR_CWUF_Pos)
    -
    -

    0x00000004

    - -
    -
    - -

    ◆ PWR_CR_CWUF

    - -
    -
    - - - - -
    #define PWR_CR_CWUF   PWR_CR_CWUF_Msk
    -
    -

    Clear Wakeup Flag
    -

    - -
    -
    - -

    ◆ PWR_CR_CSBF_Pos

    - -
    -
    - - - - -
    #define PWR_CR_CSBF_Pos   (3U)
    -
    - -
    -
    - -

    ◆ PWR_CR_CSBF_Msk

    - -
    -
    - - - - -
    #define PWR_CR_CSBF_Msk   (0x1UL << PWR_CR_CSBF_Pos)
    -
    -

    0x00000008

    - -
    -
    - -

    ◆ PWR_CR_CSBF

    - -
    -
    - - - - -
    #define PWR_CR_CSBF   PWR_CR_CSBF_Msk
    -
    -

    Clear Standby Flag
    -

    - -
    -
    - -

    ◆ PWR_CR_PVDE_Pos

    - -
    -
    - - - - -
    #define PWR_CR_PVDE_Pos   (4U)
    -
    - -
    -
    - -

    ◆ PWR_CR_PVDE_Msk

    - -
    -
    - - - - -
    #define PWR_CR_PVDE_Msk   (0x1UL << PWR_CR_PVDE_Pos)
    -
    -

    0x00000010

    - -
    -
    - -

    ◆ PWR_CR_PVDE

    - -
    -
    - - - - -
    #define PWR_CR_PVDE   PWR_CR_PVDE_Msk
    -
    -

    Power Voltage Detector Enable
    -

    - -
    -
    - -

    ◆ PWR_CR_PLS_Pos

    - -
    -
    - - - - -
    #define PWR_CR_PLS_Pos   (5U)
    -
    - -
    -
    - -

    ◆ PWR_CR_PLS_Msk

    - -
    -
    - - - - -
    #define PWR_CR_PLS_Msk   (0x7UL << PWR_CR_PLS_Pos)
    -
    -

    0x000000E0

    - -
    -
    - -

    ◆ PWR_CR_PLS

    - -
    -
    - - - - -
    #define PWR_CR_PLS   PWR_CR_PLS_Msk
    -
    -

    PLS[2:0] bits (PVD Level Selection)

    - -
    -
    - -

    ◆ PWR_CR_PLS_0

    - -
    -
    - - - - -
    #define PWR_CR_PLS_0   (0x1UL << PWR_CR_PLS_Pos)
    -
    -

    0x00000020

    - -
    -
    - -

    ◆ PWR_CR_PLS_1

    - -
    -
    - - - - -
    #define PWR_CR_PLS_1   (0x2UL << PWR_CR_PLS_Pos)
    -
    -

    0x00000040

    - -
    -
    - -

    ◆ PWR_CR_PLS_2

    - -
    -
    - - - - -
    #define PWR_CR_PLS_2   (0x4UL << PWR_CR_PLS_Pos)
    -
    -

    0x00000080 PVD level configuration

    - -
    -
    - -

    ◆ PWR_CR_PLS_LEV0

    - -
    -
    - - - - -
    #define PWR_CR_PLS_LEV0   0x00000000U
    -
    -

    PVD level 0

    - -
    -
    - -

    ◆ PWR_CR_PLS_LEV1

    - -
    -
    - - - - -
    #define PWR_CR_PLS_LEV1   0x00000020U
    -
    -

    PVD level 1

    - -
    -
    - -

    ◆ PWR_CR_PLS_LEV2

    - -
    -
    - - - - -
    #define PWR_CR_PLS_LEV2   0x00000040U
    -
    -

    PVD level 2

    - -
    -
    - -

    ◆ PWR_CR_PLS_LEV3

    - -
    -
    - - - - -
    #define PWR_CR_PLS_LEV3   0x00000060U
    -
    -

    PVD level 3

    - -
    -
    - -

    ◆ PWR_CR_PLS_LEV4

    - -
    -
    - - - - -
    #define PWR_CR_PLS_LEV4   0x00000080U
    -
    -

    PVD level 4

    - -
    -
    - -

    ◆ PWR_CR_PLS_LEV5

    - -
    -
    - - - - -
    #define PWR_CR_PLS_LEV5   0x000000A0U
    -
    -

    PVD level 5

    - -
    -
    - -

    ◆ PWR_CR_PLS_LEV6

    - -
    -
    - - - - -
    #define PWR_CR_PLS_LEV6   0x000000C0U
    -
    -

    PVD level 6

    - -
    -
    - -

    ◆ PWR_CR_PLS_LEV7

    - -
    -
    - - - - -
    #define PWR_CR_PLS_LEV7   0x000000E0U
    -
    -

    PVD level 7

    - -
    -
    - -

    ◆ PWR_CR_DBP_Pos

    - -
    -
    - - - - -
    #define PWR_CR_DBP_Pos   (8U)
    -
    - -
    -
    - -

    ◆ PWR_CR_DBP_Msk

    - -
    -
    - - - - -
    #define PWR_CR_DBP_Msk   (0x1UL << PWR_CR_DBP_Pos)
    -
    -

    0x00000100

    - -
    -
    - -

    ◆ PWR_CR_DBP

    - -
    -
    - - - - -
    #define PWR_CR_DBP   PWR_CR_DBP_Msk
    -
    -

    Disable Backup Domain write protection
    -

    - -
    -
    - -

    ◆ PWR_CR_FPDS_Pos

    - -
    -
    - - - - -
    #define PWR_CR_FPDS_Pos   (9U)
    -
    - -
    -
    - -

    ◆ PWR_CR_FPDS_Msk

    - -
    -
    - - - - -
    #define PWR_CR_FPDS_Msk   (0x1UL << PWR_CR_FPDS_Pos)
    -
    -

    0x00000200

    - -
    -
    - -

    ◆ PWR_CR_FPDS

    - -
    -
    - - - - -
    #define PWR_CR_FPDS   PWR_CR_FPDS_Msk
    -
    -

    Flash power down in Stop mode
    -

    - -
    -
    - -

    ◆ PWR_CR_VOS_Pos

    - -
    -
    - - - - -
    #define PWR_CR_VOS_Pos   (14U)
    -
    - -
    -
    - -

    ◆ PWR_CR_VOS_Msk

    - -
    -
    - - - - -
    #define PWR_CR_VOS_Msk   (0x1UL << PWR_CR_VOS_Pos)
    -
    -

    0x00004000

    - -
    -
    - -

    ◆ PWR_CR_VOS

    - -
    -
    - - - - -
    #define PWR_CR_VOS   PWR_CR_VOS_Msk
    -
    -

    VOS bit (Regulator voltage scaling output selection)

    - -
    -
    - -

    ◆ PWR_CR_PMODE

    - -
    -
    - - - - -
    #define PWR_CR_PMODE   PWR_CR_VOS
    -
    - -
    -
    - -

    ◆ PWR_CSR_WUF_Pos

    - -
    -
    - - - - -
    #define PWR_CSR_WUF_Pos   (0U)
    -
    - -
    -
    - -

    ◆ PWR_CSR_WUF_Msk

    - -
    -
    - - - - -
    #define PWR_CSR_WUF_Msk   (0x1UL << PWR_CSR_WUF_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ PWR_CSR_WUF

    - -
    -
    - - - - -
    #define PWR_CSR_WUF   PWR_CSR_WUF_Msk
    -
    -

    Wakeup Flag
    -

    - -
    -
    - -

    ◆ PWR_CSR_SBF_Pos

    - -
    -
    - - - - -
    #define PWR_CSR_SBF_Pos   (1U)
    -
    - -
    -
    - -

    ◆ PWR_CSR_SBF_Msk

    - -
    -
    - - - - -
    #define PWR_CSR_SBF_Msk   (0x1UL << PWR_CSR_SBF_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ PWR_CSR_SBF

    - -
    -
    - - - - -
    #define PWR_CSR_SBF   PWR_CSR_SBF_Msk
    -
    -

    Standby Flag
    -

    - -
    -
    - -

    ◆ PWR_CSR_PVDO_Pos

    - -
    -
    - - - - -
    #define PWR_CSR_PVDO_Pos   (2U)
    -
    - -
    -
    - -

    ◆ PWR_CSR_PVDO_Msk

    - -
    -
    - - - - -
    #define PWR_CSR_PVDO_Msk   (0x1UL << PWR_CSR_PVDO_Pos)
    -
    -

    0x00000004

    - -
    -
    - -

    ◆ PWR_CSR_PVDO

    - -
    -
    - - - - -
    #define PWR_CSR_PVDO   PWR_CSR_PVDO_Msk
    -
    -

    PVD Output
    -

    - -
    -
    - -

    ◆ PWR_CSR_BRR_Pos

    - -
    -
    - - - - -
    #define PWR_CSR_BRR_Pos   (3U)
    -
    - -
    -
    - -

    ◆ PWR_CSR_BRR_Msk

    - -
    -
    - - - - -
    #define PWR_CSR_BRR_Msk   (0x1UL << PWR_CSR_BRR_Pos)
    -
    -

    0x00000008

    - -
    -
    - -

    ◆ PWR_CSR_BRR

    - -
    -
    - - - - -
    #define PWR_CSR_BRR   PWR_CSR_BRR_Msk
    -
    -

    Backup regulator ready
    -

    - -
    -
    - -

    ◆ PWR_CSR_EWUP_Pos

    - -
    -
    - - - - -
    #define PWR_CSR_EWUP_Pos   (8U)
    -
    - -
    -
    - -

    ◆ PWR_CSR_EWUP_Msk

    - -
    -
    - - - - -
    #define PWR_CSR_EWUP_Msk   (0x1UL << PWR_CSR_EWUP_Pos)
    -
    -

    0x00000100

    - -
    -
    - -

    ◆ PWR_CSR_EWUP

    - -
    -
    - - - - -
    #define PWR_CSR_EWUP   PWR_CSR_EWUP_Msk
    -
    -

    Enable WKUP pin
    -

    - -
    -
    - -

    ◆ PWR_CSR_BRE_Pos

    - -
    -
    - - - - -
    #define PWR_CSR_BRE_Pos   (9U)
    -
    - -
    -
    - -

    ◆ PWR_CSR_BRE_Msk

    - -
    -
    - - - - -
    #define PWR_CSR_BRE_Msk   (0x1UL << PWR_CSR_BRE_Pos)
    -
    -

    0x00000200

    - -
    -
    - -

    ◆ PWR_CSR_BRE

    - -
    -
    - - - - -
    #define PWR_CSR_BRE   PWR_CSR_BRE_Msk
    -
    -

    Backup regulator enable
    -

    - -
    -
    - -

    ◆ PWR_CSR_VOSRDY_Pos

    - -
    -
    - - - - -
    #define PWR_CSR_VOSRDY_Pos   (14U)
    -
    - -
    -
    - -

    ◆ PWR_CSR_VOSRDY_Msk

    - -
    -
    - - - - -
    #define PWR_CSR_VOSRDY_Msk   (0x1UL << PWR_CSR_VOSRDY_Pos)
    -
    -

    0x00004000

    - -
    -
    - -

    ◆ PWR_CSR_VOSRDY

    - -
    -
    - - - - -
    #define PWR_CSR_VOSRDY   PWR_CSR_VOSRDY_Msk
    -
    -

    Regulator voltage scaling output selection ready

    - -
    -
    - -

    ◆ PWR_CSR_REGRDY

    - -
    -
    - - - - -
    #define PWR_CSR_REGRDY   PWR_CSR_VOSRDY
    -
    - -
    -
    - -

    ◆ RCC_CR_HSION_Pos

    - -
    -
    - - - - -
    #define RCC_CR_HSION_Pos   (0U)
    -
    - -
    -
    - -

    ◆ RCC_CR_HSION_Msk

    - -
    -
    - - - - -
    #define RCC_CR_HSION_Msk   (0x1UL << RCC_CR_HSION_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ RCC_CR_HSION

    - -
    -
    - - - - -
    #define RCC_CR_HSION   RCC_CR_HSION_Msk
    -
    - -
    -
    - -

    ◆ RCC_CR_HSIRDY_Pos

    - -
    -
    - - - - -
    #define RCC_CR_HSIRDY_Pos   (1U)
    -
    - -
    -
    - -

    ◆ RCC_CR_HSIRDY_Msk

    - -
    -
    - - - - -
    #define RCC_CR_HSIRDY_Msk   (0x1UL << RCC_CR_HSIRDY_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ RCC_CR_HSIRDY

    - -
    -
    - - - - -
    #define RCC_CR_HSIRDY   RCC_CR_HSIRDY_Msk
    -
    - -
    -
    - -

    ◆ RCC_CR_HSITRIM_Pos

    - -
    -
    - - - - -
    #define RCC_CR_HSITRIM_Pos   (3U)
    -
    - -
    -
    - -

    ◆ RCC_CR_HSITRIM_Msk

    - -
    -
    - - - - -
    #define RCC_CR_HSITRIM_Msk   (0x1FUL << RCC_CR_HSITRIM_Pos)
    -
    -

    0x000000F8

    - -
    -
    - -

    ◆ RCC_CR_HSITRIM

    - -
    -
    - - - - -
    #define RCC_CR_HSITRIM   RCC_CR_HSITRIM_Msk
    -
    - -
    -
    - -

    ◆ RCC_CR_HSITRIM_0

    - -
    -
    - - - - -
    #define RCC_CR_HSITRIM_0   (0x01UL << RCC_CR_HSITRIM_Pos)
    -
    -

    0x00000008

    - -
    -
    - -

    ◆ RCC_CR_HSITRIM_1

    - -
    -
    - - - - -
    #define RCC_CR_HSITRIM_1   (0x02UL << RCC_CR_HSITRIM_Pos)
    -
    -

    0x00000010

    - -
    -
    - -

    ◆ RCC_CR_HSITRIM_2

    - -
    -
    - - - - -
    #define RCC_CR_HSITRIM_2   (0x04UL << RCC_CR_HSITRIM_Pos)
    -
    -

    0x00000020

    - -
    -
    - -

    ◆ RCC_CR_HSITRIM_3

    - -
    -
    - - - - -
    #define RCC_CR_HSITRIM_3   (0x08UL << RCC_CR_HSITRIM_Pos)
    -
    -

    0x00000040

    - -
    -
    - -

    ◆ RCC_CR_HSITRIM_4

    - -
    -
    - - - - -
    #define RCC_CR_HSITRIM_4   (0x10UL << RCC_CR_HSITRIM_Pos)
    -
    -

    0x00000080

    - -
    -
    - -

    ◆ RCC_CR_HSICAL_Pos

    - -
    -
    - - - - -
    #define RCC_CR_HSICAL_Pos   (8U)
    -
    - -
    -
    - -

    ◆ RCC_CR_HSICAL_Msk

    - -
    -
    - - - - -
    #define RCC_CR_HSICAL_Msk   (0xFFUL << RCC_CR_HSICAL_Pos)
    -
    -

    0x0000FF00

    - -
    -
    - -

    ◆ RCC_CR_HSICAL

    - -
    -
    - - - - -
    #define RCC_CR_HSICAL   RCC_CR_HSICAL_Msk
    -
    - -
    -
    - -

    ◆ RCC_CR_HSICAL_0

    - -
    -
    - - - - -
    #define RCC_CR_HSICAL_0   (0x01UL << RCC_CR_HSICAL_Pos)
    -
    -

    0x00000100

    - -
    -
    - -

    ◆ RCC_CR_HSICAL_1

    - -
    -
    - - - - -
    #define RCC_CR_HSICAL_1   (0x02UL << RCC_CR_HSICAL_Pos)
    -
    -

    0x00000200

    - -
    -
    - -

    ◆ RCC_CR_HSICAL_2

    - -
    -
    - - - - -
    #define RCC_CR_HSICAL_2   (0x04UL << RCC_CR_HSICAL_Pos)
    -
    -

    0x00000400

    - -
    -
    - -

    ◆ RCC_CR_HSICAL_3

    - -
    -
    - - - - -
    #define RCC_CR_HSICAL_3   (0x08UL << RCC_CR_HSICAL_Pos)
    -
    -

    0x00000800

    - -
    -
    - -

    ◆ RCC_CR_HSICAL_4

    - -
    -
    - - - - -
    #define RCC_CR_HSICAL_4   (0x10UL << RCC_CR_HSICAL_Pos)
    -
    -

    0x00001000

    - -
    -
    - -

    ◆ RCC_CR_HSICAL_5

    - -
    -
    - - - - -
    #define RCC_CR_HSICAL_5   (0x20UL << RCC_CR_HSICAL_Pos)
    -
    -

    0x00002000

    - -
    -
    - -

    ◆ RCC_CR_HSICAL_6

    - -
    -
    - - - - -
    #define RCC_CR_HSICAL_6   (0x40UL << RCC_CR_HSICAL_Pos)
    -
    -

    0x00004000

    - -
    -
    - -

    ◆ RCC_CR_HSICAL_7

    - -
    -
    - - - - -
    #define RCC_CR_HSICAL_7   (0x80UL << RCC_CR_HSICAL_Pos)
    -
    -

    0x00008000

    - -
    -
    - -

    ◆ RCC_CR_HSEON_Pos

    - -
    -
    - - - - -
    #define RCC_CR_HSEON_Pos   (16U)
    -
    - -
    -
    - -

    ◆ RCC_CR_HSEON_Msk

    - -
    -
    - - - - -
    #define RCC_CR_HSEON_Msk   (0x1UL << RCC_CR_HSEON_Pos)
    -
    -

    0x00010000

    - -
    -
    - -

    ◆ RCC_CR_HSEON

    - -
    -
    - - - - -
    #define RCC_CR_HSEON   RCC_CR_HSEON_Msk
    -
    - -
    -
    - -

    ◆ RCC_CR_HSERDY_Pos

    - -
    -
    - - - - -
    #define RCC_CR_HSERDY_Pos   (17U)
    -
    - -
    -
    - -

    ◆ RCC_CR_HSERDY_Msk

    - -
    -
    - - - - -
    #define RCC_CR_HSERDY_Msk   (0x1UL << RCC_CR_HSERDY_Pos)
    -
    -

    0x00020000

    - -
    -
    - -

    ◆ RCC_CR_HSERDY

    - -
    -
    - - - - -
    #define RCC_CR_HSERDY   RCC_CR_HSERDY_Msk
    -
    - -
    -
    - -

    ◆ RCC_CR_HSEBYP_Pos

    - -
    -
    - - - - -
    #define RCC_CR_HSEBYP_Pos   (18U)
    -
    - -
    -
    - -

    ◆ RCC_CR_HSEBYP_Msk

    - -
    -
    - - - - -
    #define RCC_CR_HSEBYP_Msk   (0x1UL << RCC_CR_HSEBYP_Pos)
    -
    -

    0x00040000

    - -
    -
    - -

    ◆ RCC_CR_HSEBYP

    - -
    -
    - - - - -
    #define RCC_CR_HSEBYP   RCC_CR_HSEBYP_Msk
    -
    - -
    -
    - -

    ◆ RCC_CR_CSSON_Pos

    - -
    -
    - - - - -
    #define RCC_CR_CSSON_Pos   (19U)
    -
    - -
    -
    - -

    ◆ RCC_CR_CSSON_Msk

    - -
    -
    - - - - -
    #define RCC_CR_CSSON_Msk   (0x1UL << RCC_CR_CSSON_Pos)
    -
    -

    0x00080000

    - -
    -
    - -

    ◆ RCC_CR_CSSON

    - -
    -
    - - - - -
    #define RCC_CR_CSSON   RCC_CR_CSSON_Msk
    -
    - -
    -
    - -

    ◆ RCC_CR_PLLON_Pos

    - -
    -
    - - - - -
    #define RCC_CR_PLLON_Pos   (24U)
    -
    - -
    -
    - -

    ◆ RCC_CR_PLLON_Msk

    - -
    -
    - - - - -
    #define RCC_CR_PLLON_Msk   (0x1UL << RCC_CR_PLLON_Pos)
    -
    -

    0x01000000

    - -
    -
    - -

    ◆ RCC_CR_PLLON

    - -
    -
    - - - - -
    #define RCC_CR_PLLON   RCC_CR_PLLON_Msk
    -
    - -
    -
    - -

    ◆ RCC_CR_PLLRDY_Pos

    - -
    -
    - - - - -
    #define RCC_CR_PLLRDY_Pos   (25U)
    -
    - -
    -
    - -

    ◆ RCC_CR_PLLRDY_Msk

    - -
    -
    - - - - -
    #define RCC_CR_PLLRDY_Msk   (0x1UL << RCC_CR_PLLRDY_Pos)
    -
    -

    0x02000000

    - -
    -
    - -

    ◆ RCC_CR_PLLRDY

    - -
    -
    - - - - -
    #define RCC_CR_PLLRDY   RCC_CR_PLLRDY_Msk
    -
    - -
    -
    - -

    ◆ RCC_PLLI2S_SUPPORT

    - -
    -
    - - - - -
    #define RCC_PLLI2S_SUPPORT
    -
    -

    Support PLLI2S oscillator

    - -
    -
    - -

    ◆ RCC_CR_PLLI2SON_Pos

    - -
    -
    - - - - -
    #define RCC_CR_PLLI2SON_Pos   (26U)
    -
    - -
    -
    - -

    ◆ RCC_CR_PLLI2SON_Msk

    - -
    -
    - - - - -
    #define RCC_CR_PLLI2SON_Msk   (0x1UL << RCC_CR_PLLI2SON_Pos)
    -
    -

    0x04000000

    - -
    -
    - -

    ◆ RCC_CR_PLLI2SON

    - -
    -
    - - - - -
    #define RCC_CR_PLLI2SON   RCC_CR_PLLI2SON_Msk
    -
    - -
    -
    - -

    ◆ RCC_CR_PLLI2SRDY_Pos

    - -
    -
    - - - - -
    #define RCC_CR_PLLI2SRDY_Pos   (27U)
    -
    - -
    -
    - -

    ◆ RCC_CR_PLLI2SRDY_Msk

    - -
    -
    - - - - -
    #define RCC_CR_PLLI2SRDY_Msk   (0x1UL << RCC_CR_PLLI2SRDY_Pos)
    -
    -

    0x08000000

    - -
    -
    - -

    ◆ RCC_CR_PLLI2SRDY

    - -
    -
    - - - - -
    #define RCC_CR_PLLI2SRDY   RCC_CR_PLLI2SRDY_Msk
    -
    - -
    -
    - -

    ◆ RCC_PLLCFGR_PLLM_Pos

    - -
    -
    - - - - -
    #define RCC_PLLCFGR_PLLM_Pos   (0U)
    -
    - -
    -
    - -

    ◆ RCC_PLLCFGR_PLLM_Msk

    - -
    -
    - - - - -
    #define RCC_PLLCFGR_PLLM_Msk   (0x3FUL << RCC_PLLCFGR_PLLM_Pos)
    -
    -

    0x0000003F

    - -
    -
    - -

    ◆ RCC_PLLCFGR_PLLM

    - -
    -
    - - - - -
    #define RCC_PLLCFGR_PLLM   RCC_PLLCFGR_PLLM_Msk
    -
    - -
    -
    - -

    ◆ RCC_PLLCFGR_PLLM_0

    - -
    -
    - - - - -
    #define RCC_PLLCFGR_PLLM_0   (0x01UL << RCC_PLLCFGR_PLLM_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ RCC_PLLCFGR_PLLM_1

    - -
    -
    - - - - -
    #define RCC_PLLCFGR_PLLM_1   (0x02UL << RCC_PLLCFGR_PLLM_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ RCC_PLLCFGR_PLLM_2

    - -
    -
    - - - - -
    #define RCC_PLLCFGR_PLLM_2   (0x04UL << RCC_PLLCFGR_PLLM_Pos)
    -
    -

    0x00000004

    - -
    -
    - -

    ◆ RCC_PLLCFGR_PLLM_3

    - -
    -
    - - - - -
    #define RCC_PLLCFGR_PLLM_3   (0x08UL << RCC_PLLCFGR_PLLM_Pos)
    -
    -

    0x00000008

    - -
    -
    - -

    ◆ RCC_PLLCFGR_PLLM_4

    - -
    -
    - - - - -
    #define RCC_PLLCFGR_PLLM_4   (0x10UL << RCC_PLLCFGR_PLLM_Pos)
    -
    -

    0x00000010

    - -
    -
    - -

    ◆ RCC_PLLCFGR_PLLM_5

    - -
    -
    - - - - -
    #define RCC_PLLCFGR_PLLM_5   (0x20UL << RCC_PLLCFGR_PLLM_Pos)
    -
    -

    0x00000020

    - -
    -
    - -

    ◆ RCC_PLLCFGR_PLLN_Pos

    - -
    -
    - - - - -
    #define RCC_PLLCFGR_PLLN_Pos   (6U)
    -
    - -
    -
    - -

    ◆ RCC_PLLCFGR_PLLN_Msk

    - -
    -
    - - - - -
    #define RCC_PLLCFGR_PLLN_Msk   (0x1FFUL << RCC_PLLCFGR_PLLN_Pos)
    -
    -

    0x00007FC0

    - -
    -
    - -

    ◆ RCC_PLLCFGR_PLLN

    - -
    -
    - - - - -
    #define RCC_PLLCFGR_PLLN   RCC_PLLCFGR_PLLN_Msk
    -
    - -
    -
    - -

    ◆ RCC_PLLCFGR_PLLN_0

    - -
    -
    - - - - -
    #define RCC_PLLCFGR_PLLN_0   (0x001UL << RCC_PLLCFGR_PLLN_Pos)
    -
    -

    0x00000040

    - -
    -
    - -

    ◆ RCC_PLLCFGR_PLLN_1

    - -
    -
    - - - - -
    #define RCC_PLLCFGR_PLLN_1   (0x002UL << RCC_PLLCFGR_PLLN_Pos)
    -
    -

    0x00000080

    - -
    -
    - -

    ◆ RCC_PLLCFGR_PLLN_2

    - -
    -
    - - - - -
    #define RCC_PLLCFGR_PLLN_2   (0x004UL << RCC_PLLCFGR_PLLN_Pos)
    -
    -

    0x00000100

    - -
    -
    - -

    ◆ RCC_PLLCFGR_PLLN_3

    - -
    -
    - - - - -
    #define RCC_PLLCFGR_PLLN_3   (0x008UL << RCC_PLLCFGR_PLLN_Pos)
    -
    -

    0x00000200

    - -
    -
    - -

    ◆ RCC_PLLCFGR_PLLN_4

    - -
    -
    - - - - -
    #define RCC_PLLCFGR_PLLN_4   (0x010UL << RCC_PLLCFGR_PLLN_Pos)
    -
    -

    0x00000400

    - -
    -
    - -

    ◆ RCC_PLLCFGR_PLLN_5

    - -
    -
    - - - - -
    #define RCC_PLLCFGR_PLLN_5   (0x020UL << RCC_PLLCFGR_PLLN_Pos)
    -
    -

    0x00000800

    - -
    -
    - -

    ◆ RCC_PLLCFGR_PLLN_6

    - -
    -
    - - - - -
    #define RCC_PLLCFGR_PLLN_6   (0x040UL << RCC_PLLCFGR_PLLN_Pos)
    -
    -

    0x00001000

    - -
    -
    - -

    ◆ RCC_PLLCFGR_PLLN_7

    - -
    -
    - - - - -
    #define RCC_PLLCFGR_PLLN_7   (0x080UL << RCC_PLLCFGR_PLLN_Pos)
    -
    -

    0x00002000

    - -
    -
    - -

    ◆ RCC_PLLCFGR_PLLN_8

    - -
    -
    - - - - -
    #define RCC_PLLCFGR_PLLN_8   (0x100UL << RCC_PLLCFGR_PLLN_Pos)
    -
    -

    0x00004000

    - -
    -
    - -

    ◆ RCC_PLLCFGR_PLLP_Pos

    - -
    -
    - - - - -
    #define RCC_PLLCFGR_PLLP_Pos   (16U)
    -
    - -
    -
    - -

    ◆ RCC_PLLCFGR_PLLP_Msk

    - -
    -
    - - - - -
    #define RCC_PLLCFGR_PLLP_Msk   (0x3UL << RCC_PLLCFGR_PLLP_Pos)
    -
    -

    0x00030000

    - -
    -
    - -

    ◆ RCC_PLLCFGR_PLLP

    - -
    -
    - - - - -
    #define RCC_PLLCFGR_PLLP   RCC_PLLCFGR_PLLP_Msk
    -
    - -
    -
    - -

    ◆ RCC_PLLCFGR_PLLP_0

    - -
    -
    - - - - -
    #define RCC_PLLCFGR_PLLP_0   (0x1UL << RCC_PLLCFGR_PLLP_Pos)
    -
    -

    0x00010000

    - -
    -
    - -

    ◆ RCC_PLLCFGR_PLLP_1

    - -
    -
    - - - - -
    #define RCC_PLLCFGR_PLLP_1   (0x2UL << RCC_PLLCFGR_PLLP_Pos)
    -
    -

    0x00020000

    - -
    -
    - -

    ◆ RCC_PLLCFGR_PLLSRC_Pos

    - -
    -
    - - - - -
    #define RCC_PLLCFGR_PLLSRC_Pos   (22U)
    -
    - -
    -
    - -

    ◆ RCC_PLLCFGR_PLLSRC_Msk

    - -
    -
    - - - - -
    #define RCC_PLLCFGR_PLLSRC_Msk   (0x1UL << RCC_PLLCFGR_PLLSRC_Pos)
    -
    -

    0x00400000

    - -
    -
    - -

    ◆ RCC_PLLCFGR_PLLSRC

    - -
    -
    - - - - -
    #define RCC_PLLCFGR_PLLSRC   RCC_PLLCFGR_PLLSRC_Msk
    -
    - -
    -
    - -

    ◆ RCC_PLLCFGR_PLLSRC_HSE_Pos

    - -
    -
    - - - - -
    #define RCC_PLLCFGR_PLLSRC_HSE_Pos   (22U)
    -
    - -
    -
    - -

    ◆ RCC_PLLCFGR_PLLSRC_HSE_Msk

    - -
    -
    - - - - -
    #define RCC_PLLCFGR_PLLSRC_HSE_Msk   (0x1UL << RCC_PLLCFGR_PLLSRC_HSE_Pos)
    -
    -

    0x00400000

    - -
    -
    - -

    ◆ RCC_PLLCFGR_PLLSRC_HSE

    - -
    -
    - - - - -
    #define RCC_PLLCFGR_PLLSRC_HSE   RCC_PLLCFGR_PLLSRC_HSE_Msk
    -
    - -
    -
    - -

    ◆ RCC_PLLCFGR_PLLSRC_HSI

    - -
    -
    - - - - -
    #define RCC_PLLCFGR_PLLSRC_HSI   0x00000000U
    -
    - -
    -
    - -

    ◆ RCC_PLLCFGR_PLLQ_Pos

    - -
    -
    - - - - -
    #define RCC_PLLCFGR_PLLQ_Pos   (24U)
    -
    - -
    -
    - -

    ◆ RCC_PLLCFGR_PLLQ_Msk

    - -
    -
    - - - - -
    #define RCC_PLLCFGR_PLLQ_Msk   (0xFUL << RCC_PLLCFGR_PLLQ_Pos)
    -
    -

    0x0F000000

    - -
    -
    - -

    ◆ RCC_PLLCFGR_PLLQ

    - -
    -
    - - - - -
    #define RCC_PLLCFGR_PLLQ   RCC_PLLCFGR_PLLQ_Msk
    -
    - -
    -
    - -

    ◆ RCC_PLLCFGR_PLLQ_0

    - -
    -
    - - - - -
    #define RCC_PLLCFGR_PLLQ_0   (0x1UL << RCC_PLLCFGR_PLLQ_Pos)
    -
    -

    0x01000000

    - -
    -
    - -

    ◆ RCC_PLLCFGR_PLLQ_1

    - -
    -
    - - - - -
    #define RCC_PLLCFGR_PLLQ_1   (0x2UL << RCC_PLLCFGR_PLLQ_Pos)
    -
    -

    0x02000000

    - -
    -
    - -

    ◆ RCC_PLLCFGR_PLLQ_2

    - -
    -
    - - - - -
    #define RCC_PLLCFGR_PLLQ_2   (0x4UL << RCC_PLLCFGR_PLLQ_Pos)
    -
    -

    0x04000000

    - -
    -
    - -

    ◆ RCC_PLLCFGR_PLLQ_3

    - -
    -
    - - - - -
    #define RCC_PLLCFGR_PLLQ_3   (0x8UL << RCC_PLLCFGR_PLLQ_Pos)
    -
    -

    0x08000000

    - -
    -
    - -

    ◆ RCC_CFGR_SW_Pos

    - -
    -
    - - - - -
    #define RCC_CFGR_SW_Pos   (0U)
    -
    -

    < SW configuration

    - -
    -
    - -

    ◆ RCC_CFGR_SW_Msk

    - -
    -
    - - - - -
    #define RCC_CFGR_SW_Msk   (0x3UL << RCC_CFGR_SW_Pos)
    -
    -

    0x00000003

    - -
    -
    - -

    ◆ RCC_CFGR_SW

    - -
    -
    - - - - -
    #define RCC_CFGR_SW   RCC_CFGR_SW_Msk
    -
    -

    SW[1:0] bits (System clock Switch)

    - -
    -
    - -

    ◆ RCC_CFGR_SW_0

    - -
    -
    - - - - -
    #define RCC_CFGR_SW_0   (0x1UL << RCC_CFGR_SW_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ RCC_CFGR_SW_1

    - -
    -
    - - - - -
    #define RCC_CFGR_SW_1   (0x2UL << RCC_CFGR_SW_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ RCC_CFGR_SW_HSI

    - -
    -
    - - - - -
    #define RCC_CFGR_SW_HSI   0x00000000U
    -
    -

    HSI selected as system clock

    - -
    -
    - -

    ◆ RCC_CFGR_SW_HSE

    - -
    -
    - - - - -
    #define RCC_CFGR_SW_HSE   0x00000001U
    -
    -

    HSE selected as system clock

    - -
    -
    - -

    ◆ RCC_CFGR_SW_PLL

    - -
    -
    - - - - -
    #define RCC_CFGR_SW_PLL   0x00000002U
    -
    -

    PLL selected as system clock SWS configuration

    - -
    -
    - -

    ◆ RCC_CFGR_SWS_Pos

    - -
    -
    - - - - -
    #define RCC_CFGR_SWS_Pos   (2U)
    -
    - -
    -
    - -

    ◆ RCC_CFGR_SWS_Msk

    - -
    -
    - - - - -
    #define RCC_CFGR_SWS_Msk   (0x3UL << RCC_CFGR_SWS_Pos)
    -
    -

    0x0000000C

    - -
    -
    - -

    ◆ RCC_CFGR_SWS

    - -
    -
    - - - - -
    #define RCC_CFGR_SWS   RCC_CFGR_SWS_Msk
    -
    -

    SWS[1:0] bits (System Clock Switch Status)

    - -
    -
    - -

    ◆ RCC_CFGR_SWS_0

    - -
    -
    - - - - -
    #define RCC_CFGR_SWS_0   (0x1UL << RCC_CFGR_SWS_Pos)
    -
    -

    0x00000004

    - -
    -
    - -

    ◆ RCC_CFGR_SWS_1

    - -
    -
    - - - - -
    #define RCC_CFGR_SWS_1   (0x2UL << RCC_CFGR_SWS_Pos)
    -
    -

    0x00000008

    - -
    -
    - -

    ◆ RCC_CFGR_SWS_HSI

    - -
    -
    - - - - -
    #define RCC_CFGR_SWS_HSI   0x00000000U
    -
    -

    HSI oscillator used as system clock
    -

    - -
    -
    - -

    ◆ RCC_CFGR_SWS_HSE

    - -
    -
    - - - - -
    #define RCC_CFGR_SWS_HSE   0x00000004U
    -
    -

    HSE oscillator used as system clock
    -

    - -
    -
    - -

    ◆ RCC_CFGR_SWS_PLL

    - -
    -
    - - - - -
    #define RCC_CFGR_SWS_PLL   0x00000008U
    -
    -

    PLL used as system clock
    - HPRE configuration

    - -
    -
    - -

    ◆ RCC_CFGR_HPRE_Pos

    - -
    -
    - - - - -
    #define RCC_CFGR_HPRE_Pos   (4U)
    -
    - -
    -
    - -

    ◆ RCC_CFGR_HPRE_Msk

    - -
    -
    - - - - -
    #define RCC_CFGR_HPRE_Msk   (0xFUL << RCC_CFGR_HPRE_Pos)
    -
    -

    0x000000F0

    - -
    -
    - -

    ◆ RCC_CFGR_HPRE

    - -
    -
    - - - - -
    #define RCC_CFGR_HPRE   RCC_CFGR_HPRE_Msk
    -
    -

    HPRE[3:0] bits (AHB prescaler)

    - -
    -
    - -

    ◆ RCC_CFGR_HPRE_0

    - -
    -
    - - - - -
    #define RCC_CFGR_HPRE_0   (0x1UL << RCC_CFGR_HPRE_Pos)
    -
    -

    0x00000010

    - -
    -
    - -

    ◆ RCC_CFGR_HPRE_1

    - -
    -
    - - - - -
    #define RCC_CFGR_HPRE_1   (0x2UL << RCC_CFGR_HPRE_Pos)
    -
    -

    0x00000020

    - -
    -
    - -

    ◆ RCC_CFGR_HPRE_2

    - -
    -
    - - - - -
    #define RCC_CFGR_HPRE_2   (0x4UL << RCC_CFGR_HPRE_Pos)
    -
    -

    0x00000040

    - -
    -
    - -

    ◆ RCC_CFGR_HPRE_3

    - -
    -
    - - - - -
    #define RCC_CFGR_HPRE_3   (0x8UL << RCC_CFGR_HPRE_Pos)
    -
    -

    0x00000080

    - -
    -
    - -

    ◆ RCC_CFGR_HPRE_DIV1

    - -
    -
    - - - - -
    #define RCC_CFGR_HPRE_DIV1   0x00000000U
    -
    -

    SYSCLK not divided
    -

    - -
    -
    - -

    ◆ RCC_CFGR_HPRE_DIV2

    - -
    -
    - - - - -
    #define RCC_CFGR_HPRE_DIV2   0x00000080U
    -
    -

    SYSCLK divided by 2
    -

    - -
    -
    - -

    ◆ RCC_CFGR_HPRE_DIV4

    - -
    -
    - - - - -
    #define RCC_CFGR_HPRE_DIV4   0x00000090U
    -
    -

    SYSCLK divided by 4
    -

    - -
    -
    - -

    ◆ RCC_CFGR_HPRE_DIV8

    - -
    -
    - - - - -
    #define RCC_CFGR_HPRE_DIV8   0x000000A0U
    -
    -

    SYSCLK divided by 8
    -

    - -
    -
    - -

    ◆ RCC_CFGR_HPRE_DIV16

    - -
    -
    - - - - -
    #define RCC_CFGR_HPRE_DIV16   0x000000B0U
    -
    -

    SYSCLK divided by 16
    -

    - -
    -
    - -

    ◆ RCC_CFGR_HPRE_DIV64

    - -
    -
    - - - - -
    #define RCC_CFGR_HPRE_DIV64   0x000000C0U
    -
    -

    SYSCLK divided by 64
    -

    - -
    -
    - -

    ◆ RCC_CFGR_HPRE_DIV128

    - -
    -
    - - - - -
    #define RCC_CFGR_HPRE_DIV128   0x000000D0U
    -
    -

    SYSCLK divided by 128

    - -
    -
    - -

    ◆ RCC_CFGR_HPRE_DIV256

    - -
    -
    - - - - -
    #define RCC_CFGR_HPRE_DIV256   0x000000E0U
    -
    -

    SYSCLK divided by 256

    - -
    -
    - -

    ◆ RCC_CFGR_HPRE_DIV512

    - -
    -
    - - - - -
    #define RCC_CFGR_HPRE_DIV512   0x000000F0U
    -
    -

    SYSCLK divided by 512 PPRE1 configuration

    - -
    -
    - -

    ◆ RCC_CFGR_PPRE1_Pos

    - -
    -
    - - - - -
    #define RCC_CFGR_PPRE1_Pos   (10U)
    -
    - -
    -
    - -

    ◆ RCC_CFGR_PPRE1_Msk

    - -
    -
    - - - - -
    #define RCC_CFGR_PPRE1_Msk   (0x7UL << RCC_CFGR_PPRE1_Pos)
    -
    -

    0x00001C00

    - -
    -
    - -

    ◆ RCC_CFGR_PPRE1

    - -
    -
    - - - - -
    #define RCC_CFGR_PPRE1   RCC_CFGR_PPRE1_Msk
    -
    -

    PRE1[2:0] bits (APB1 prescaler)

    - -
    -
    - -

    ◆ RCC_CFGR_PPRE1_0

    - -
    -
    - - - - -
    #define RCC_CFGR_PPRE1_0   (0x1UL << RCC_CFGR_PPRE1_Pos)
    -
    -

    0x00000400

    - -
    -
    - -

    ◆ RCC_CFGR_PPRE1_1

    - -
    -
    - - - - -
    #define RCC_CFGR_PPRE1_1   (0x2UL << RCC_CFGR_PPRE1_Pos)
    -
    -

    0x00000800

    - -
    -
    - -

    ◆ RCC_CFGR_PPRE1_2

    - -
    -
    - - - - -
    #define RCC_CFGR_PPRE1_2   (0x4UL << RCC_CFGR_PPRE1_Pos)
    -
    -

    0x00001000

    - -
    -
    - -

    ◆ RCC_CFGR_PPRE1_DIV1

    - -
    -
    - - - - -
    #define RCC_CFGR_PPRE1_DIV1   0x00000000U
    -
    -

    HCLK not divided
    -

    - -
    -
    - -

    ◆ RCC_CFGR_PPRE1_DIV2

    - -
    -
    - - - - -
    #define RCC_CFGR_PPRE1_DIV2   0x00001000U
    -
    -

    HCLK divided by 2
    -

    - -
    -
    - -

    ◆ RCC_CFGR_PPRE1_DIV4

    - -
    -
    - - - - -
    #define RCC_CFGR_PPRE1_DIV4   0x00001400U
    -
    -

    HCLK divided by 4
    -

    - -
    -
    - -

    ◆ RCC_CFGR_PPRE1_DIV8

    - -
    -
    - - - - -
    #define RCC_CFGR_PPRE1_DIV8   0x00001800U
    -
    -

    HCLK divided by 8
    -

    - -
    -
    - -

    ◆ RCC_CFGR_PPRE1_DIV16

    - -
    -
    - - - - -
    #define RCC_CFGR_PPRE1_DIV16   0x00001C00U
    -
    -

    HCLK divided by 16 PPRE2 configuration

    - -
    -
    - -

    ◆ RCC_CFGR_PPRE2_Pos

    - -
    -
    - - - - -
    #define RCC_CFGR_PPRE2_Pos   (13U)
    -
    - -
    -
    - -

    ◆ RCC_CFGR_PPRE2_Msk

    - -
    -
    - - - - -
    #define RCC_CFGR_PPRE2_Msk   (0x7UL << RCC_CFGR_PPRE2_Pos)
    -
    -

    0x0000E000

    - -
    -
    - -

    ◆ RCC_CFGR_PPRE2

    - -
    -
    - - - - -
    #define RCC_CFGR_PPRE2   RCC_CFGR_PPRE2_Msk
    -
    -

    PRE2[2:0] bits (APB2 prescaler)

    - -
    -
    - -

    ◆ RCC_CFGR_PPRE2_0

    - -
    -
    - - - - -
    #define RCC_CFGR_PPRE2_0   (0x1UL << RCC_CFGR_PPRE2_Pos)
    -
    -

    0x00002000

    - -
    -
    - -

    ◆ RCC_CFGR_PPRE2_1

    - -
    -
    - - - - -
    #define RCC_CFGR_PPRE2_1   (0x2UL << RCC_CFGR_PPRE2_Pos)
    -
    -

    0x00004000

    - -
    -
    - -

    ◆ RCC_CFGR_PPRE2_2

    - -
    -
    - - - - -
    #define RCC_CFGR_PPRE2_2   (0x4UL << RCC_CFGR_PPRE2_Pos)
    -
    -

    0x00008000

    - -
    -
    - -

    ◆ RCC_CFGR_PPRE2_DIV1

    - -
    -
    - - - - -
    #define RCC_CFGR_PPRE2_DIV1   0x00000000U
    -
    -

    HCLK not divided
    -

    - -
    -
    - -

    ◆ RCC_CFGR_PPRE2_DIV2

    - -
    -
    - - - - -
    #define RCC_CFGR_PPRE2_DIV2   0x00008000U
    -
    -

    HCLK divided by 2
    -

    - -
    -
    - -

    ◆ RCC_CFGR_PPRE2_DIV4

    - -
    -
    - - - - -
    #define RCC_CFGR_PPRE2_DIV4   0x0000A000U
    -
    -

    HCLK divided by 4
    -

    - -
    -
    - -

    ◆ RCC_CFGR_PPRE2_DIV8

    - -
    -
    - - - - -
    #define RCC_CFGR_PPRE2_DIV8   0x0000C000U
    -
    -

    HCLK divided by 8
    -

    - -
    -
    - -

    ◆ RCC_CFGR_PPRE2_DIV16

    - -
    -
    - - - - -
    #define RCC_CFGR_PPRE2_DIV16   0x0000E000U
    -
    -

    HCLK divided by 16 RTCPRE configuration

    - -
    -
    - -

    ◆ RCC_CFGR_RTCPRE_Pos

    - -
    -
    - - - - -
    #define RCC_CFGR_RTCPRE_Pos   (16U)
    -
    - -
    -
    - -

    ◆ RCC_CFGR_RTCPRE_Msk

    - -
    -
    - - - - -
    #define RCC_CFGR_RTCPRE_Msk   (0x1FUL << RCC_CFGR_RTCPRE_Pos)
    -
    -

    0x001F0000

    - -
    -
    - -

    ◆ RCC_CFGR_RTCPRE

    - -
    -
    - - - - -
    #define RCC_CFGR_RTCPRE   RCC_CFGR_RTCPRE_Msk
    -
    - -
    -
    - -

    ◆ RCC_CFGR_RTCPRE_0

    - -
    -
    - - - - -
    #define RCC_CFGR_RTCPRE_0   (0x01UL << RCC_CFGR_RTCPRE_Pos)
    -
    -

    0x00010000

    - -
    -
    - -

    ◆ RCC_CFGR_RTCPRE_1

    - -
    -
    - - - - -
    #define RCC_CFGR_RTCPRE_1   (0x02UL << RCC_CFGR_RTCPRE_Pos)
    -
    -

    0x00020000

    - -
    -
    - -

    ◆ RCC_CFGR_RTCPRE_2

    - -
    -
    - - - - -
    #define RCC_CFGR_RTCPRE_2   (0x04UL << RCC_CFGR_RTCPRE_Pos)
    -
    -

    0x00040000

    - -
    -
    - -

    ◆ RCC_CFGR_RTCPRE_3

    - -
    -
    - - - - -
    #define RCC_CFGR_RTCPRE_3   (0x08UL << RCC_CFGR_RTCPRE_Pos)
    -
    -

    0x00080000

    - -
    -
    - -

    ◆ RCC_CFGR_RTCPRE_4

    - -
    -
    - - - - -
    #define RCC_CFGR_RTCPRE_4   (0x10UL << RCC_CFGR_RTCPRE_Pos)
    -
    -

    0x00100000 MCO1 configuration

    - -
    -
    - -

    ◆ RCC_CFGR_MCO1_Pos

    - -
    -
    - - - - -
    #define RCC_CFGR_MCO1_Pos   (21U)
    -
    - -
    -
    - -

    ◆ RCC_CFGR_MCO1_Msk

    - -
    -
    - - - - -
    #define RCC_CFGR_MCO1_Msk   (0x3UL << RCC_CFGR_MCO1_Pos)
    -
    -

    0x00600000

    - -
    -
    - -

    ◆ RCC_CFGR_MCO1

    - -
    -
    - - - - -
    #define RCC_CFGR_MCO1   RCC_CFGR_MCO1_Msk
    -
    - -
    -
    - -

    ◆ RCC_CFGR_MCO1_0

    - -
    -
    - - - - -
    #define RCC_CFGR_MCO1_0   (0x1UL << RCC_CFGR_MCO1_Pos)
    -
    -

    0x00200000

    - -
    -
    - -

    ◆ RCC_CFGR_MCO1_1

    - -
    -
    - - - - -
    #define RCC_CFGR_MCO1_1   (0x2UL << RCC_CFGR_MCO1_Pos)
    -
    -

    0x00400000

    - -
    -
    - -

    ◆ RCC_CFGR_I2SSRC_Pos

    - -
    -
    - - - - -
    #define RCC_CFGR_I2SSRC_Pos   (23U)
    -
    - -
    -
    - -

    ◆ RCC_CFGR_I2SSRC_Msk

    - -
    -
    - - - - -
    #define RCC_CFGR_I2SSRC_Msk   (0x1UL << RCC_CFGR_I2SSRC_Pos)
    -
    -

    0x00800000

    - -
    -
    - -

    ◆ RCC_CFGR_I2SSRC

    - -
    -
    - - - - -
    #define RCC_CFGR_I2SSRC   RCC_CFGR_I2SSRC_Msk
    -
    - -
    -
    - -

    ◆ RCC_CFGR_MCO1PRE_Pos

    - -
    -
    - - - - -
    #define RCC_CFGR_MCO1PRE_Pos   (24U)
    -
    - -
    -
    - -

    ◆ RCC_CFGR_MCO1PRE_Msk

    - -
    -
    - - - - -
    #define RCC_CFGR_MCO1PRE_Msk   (0x7UL << RCC_CFGR_MCO1PRE_Pos)
    -
    -

    0x07000000

    - -
    -
    - -

    ◆ RCC_CFGR_MCO1PRE

    - -
    -
    - - - - -
    #define RCC_CFGR_MCO1PRE   RCC_CFGR_MCO1PRE_Msk
    -
    - -
    -
    - -

    ◆ RCC_CFGR_MCO1PRE_0

    - -
    -
    - - - - -
    #define RCC_CFGR_MCO1PRE_0   (0x1UL << RCC_CFGR_MCO1PRE_Pos)
    -
    -

    0x01000000

    - -
    -
    - -

    ◆ RCC_CFGR_MCO1PRE_1

    - -
    -
    - - - - -
    #define RCC_CFGR_MCO1PRE_1   (0x2UL << RCC_CFGR_MCO1PRE_Pos)
    -
    -

    0x02000000

    - -
    -
    - -

    ◆ RCC_CFGR_MCO1PRE_2

    - -
    -
    - - - - -
    #define RCC_CFGR_MCO1PRE_2   (0x4UL << RCC_CFGR_MCO1PRE_Pos)
    -
    -

    0x04000000

    - -
    -
    - -

    ◆ RCC_CFGR_MCO2PRE_Pos

    - -
    -
    - - - - -
    #define RCC_CFGR_MCO2PRE_Pos   (27U)
    -
    - -
    -
    - -

    ◆ RCC_CFGR_MCO2PRE_Msk

    - -
    -
    - - - - -
    #define RCC_CFGR_MCO2PRE_Msk   (0x7UL << RCC_CFGR_MCO2PRE_Pos)
    -
    -

    0x38000000

    - -
    -
    - -

    ◆ RCC_CFGR_MCO2PRE

    - -
    -
    - - - - -
    #define RCC_CFGR_MCO2PRE   RCC_CFGR_MCO2PRE_Msk
    -
    - -
    -
    - -

    ◆ RCC_CFGR_MCO2PRE_0

    - -
    -
    - - - - -
    #define RCC_CFGR_MCO2PRE_0   (0x1UL << RCC_CFGR_MCO2PRE_Pos)
    -
    -

    0x08000000

    - -
    -
    - -

    ◆ RCC_CFGR_MCO2PRE_1

    - -
    -
    - - - - -
    #define RCC_CFGR_MCO2PRE_1   (0x2UL << RCC_CFGR_MCO2PRE_Pos)
    -
    -

    0x10000000

    - -
    -
    - -

    ◆ RCC_CFGR_MCO2PRE_2

    - -
    -
    - - - - -
    #define RCC_CFGR_MCO2PRE_2   (0x4UL << RCC_CFGR_MCO2PRE_Pos)
    -
    -

    0x20000000

    - -
    -
    - -

    ◆ RCC_CFGR_MCO2_Pos

    - -
    -
    - - - - -
    #define RCC_CFGR_MCO2_Pos   (30U)
    -
    - -
    -
    - -

    ◆ RCC_CFGR_MCO2_Msk

    - -
    -
    - - - - -
    #define RCC_CFGR_MCO2_Msk   (0x3UL << RCC_CFGR_MCO2_Pos)
    -
    -

    0xC0000000

    - -
    -
    - -

    ◆ RCC_CFGR_MCO2

    - -
    -
    - - - - -
    #define RCC_CFGR_MCO2   RCC_CFGR_MCO2_Msk
    -
    - -
    -
    - -

    ◆ RCC_CFGR_MCO2_0

    - -
    -
    - - - - -
    #define RCC_CFGR_MCO2_0   (0x1UL << RCC_CFGR_MCO2_Pos)
    -
    -

    0x40000000

    - -
    -
    - -

    ◆ RCC_CFGR_MCO2_1

    - -
    -
    - - - - -
    #define RCC_CFGR_MCO2_1   (0x2UL << RCC_CFGR_MCO2_Pos)
    -
    -

    0x80000000

    - -
    -
    - -

    ◆ RCC_CIR_LSIRDYF_Pos

    - -
    -
    - - - - -
    #define RCC_CIR_LSIRDYF_Pos   (0U)
    -
    - -
    -
    - -

    ◆ RCC_CIR_LSIRDYF_Msk

    - -
    -
    - - - - -
    #define RCC_CIR_LSIRDYF_Msk   (0x1UL << RCC_CIR_LSIRDYF_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ RCC_CIR_LSIRDYF

    - -
    -
    - - - - -
    #define RCC_CIR_LSIRDYF   RCC_CIR_LSIRDYF_Msk
    -
    - -
    -
    - -

    ◆ RCC_CIR_LSERDYF_Pos

    - -
    -
    - - - - -
    #define RCC_CIR_LSERDYF_Pos   (1U)
    -
    - -
    -
    - -

    ◆ RCC_CIR_LSERDYF_Msk

    - -
    -
    - - - - -
    #define RCC_CIR_LSERDYF_Msk   (0x1UL << RCC_CIR_LSERDYF_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ RCC_CIR_LSERDYF

    - -
    -
    - - - - -
    #define RCC_CIR_LSERDYF   RCC_CIR_LSERDYF_Msk
    -
    - -
    -
    - -

    ◆ RCC_CIR_HSIRDYF_Pos

    - -
    -
    - - - - -
    #define RCC_CIR_HSIRDYF_Pos   (2U)
    -
    - -
    -
    - -

    ◆ RCC_CIR_HSIRDYF_Msk

    - -
    -
    - - - - -
    #define RCC_CIR_HSIRDYF_Msk   (0x1UL << RCC_CIR_HSIRDYF_Pos)
    -
    -

    0x00000004

    - -
    -
    - -

    ◆ RCC_CIR_HSIRDYF

    - -
    -
    - - - - -
    #define RCC_CIR_HSIRDYF   RCC_CIR_HSIRDYF_Msk
    -
    - -
    -
    - -

    ◆ RCC_CIR_HSERDYF_Pos

    - -
    -
    - - - - -
    #define RCC_CIR_HSERDYF_Pos   (3U)
    -
    - -
    -
    - -

    ◆ RCC_CIR_HSERDYF_Msk

    - -
    -
    - - - - -
    #define RCC_CIR_HSERDYF_Msk   (0x1UL << RCC_CIR_HSERDYF_Pos)
    -
    -

    0x00000008

    - -
    -
    - -

    ◆ RCC_CIR_HSERDYF

    - -
    -
    - - - - -
    #define RCC_CIR_HSERDYF   RCC_CIR_HSERDYF_Msk
    -
    - -
    -
    - -

    ◆ RCC_CIR_PLLRDYF_Pos

    - -
    -
    - - - - -
    #define RCC_CIR_PLLRDYF_Pos   (4U)
    -
    - -
    -
    - -

    ◆ RCC_CIR_PLLRDYF_Msk

    - -
    -
    - - - - -
    #define RCC_CIR_PLLRDYF_Msk   (0x1UL << RCC_CIR_PLLRDYF_Pos)
    -
    -

    0x00000010

    - -
    -
    - -

    ◆ RCC_CIR_PLLRDYF

    - -
    -
    - - - - -
    #define RCC_CIR_PLLRDYF   RCC_CIR_PLLRDYF_Msk
    -
    - -
    -
    - -

    ◆ RCC_CIR_PLLI2SRDYF_Pos

    - -
    -
    - - - - -
    #define RCC_CIR_PLLI2SRDYF_Pos   (5U)
    -
    - -
    -
    - -

    ◆ RCC_CIR_PLLI2SRDYF_Msk

    - -
    -
    - - - - -
    #define RCC_CIR_PLLI2SRDYF_Msk   (0x1UL << RCC_CIR_PLLI2SRDYF_Pos)
    -
    -

    0x00000020

    - -
    -
    - -

    ◆ RCC_CIR_PLLI2SRDYF

    - -
    -
    - - - - -
    #define RCC_CIR_PLLI2SRDYF   RCC_CIR_PLLI2SRDYF_Msk
    -
    - -
    -
    - -

    ◆ RCC_CIR_CSSF_Pos

    - -
    -
    - - - - -
    #define RCC_CIR_CSSF_Pos   (7U)
    -
    - -
    -
    - -

    ◆ RCC_CIR_CSSF_Msk

    - -
    -
    - - - - -
    #define RCC_CIR_CSSF_Msk   (0x1UL << RCC_CIR_CSSF_Pos)
    -
    -

    0x00000080

    - -
    -
    - -

    ◆ RCC_CIR_CSSF

    - -
    -
    - - - - -
    #define RCC_CIR_CSSF   RCC_CIR_CSSF_Msk
    -
    - -
    -
    - -

    ◆ RCC_CIR_LSIRDYIE_Pos

    - -
    -
    - - - - -
    #define RCC_CIR_LSIRDYIE_Pos   (8U)
    -
    - -
    -
    - -

    ◆ RCC_CIR_LSIRDYIE_Msk

    - -
    -
    - - - - -
    #define RCC_CIR_LSIRDYIE_Msk   (0x1UL << RCC_CIR_LSIRDYIE_Pos)
    -
    -

    0x00000100

    - -
    -
    - -

    ◆ RCC_CIR_LSIRDYIE

    - -
    -
    - - - - -
    #define RCC_CIR_LSIRDYIE   RCC_CIR_LSIRDYIE_Msk
    -
    - -
    -
    - -

    ◆ RCC_CIR_LSERDYIE_Pos

    - -
    -
    - - - - -
    #define RCC_CIR_LSERDYIE_Pos   (9U)
    -
    - -
    -
    - -

    ◆ RCC_CIR_LSERDYIE_Msk

    - -
    -
    - - - - -
    #define RCC_CIR_LSERDYIE_Msk   (0x1UL << RCC_CIR_LSERDYIE_Pos)
    -
    -

    0x00000200

    - -
    -
    - -

    ◆ RCC_CIR_LSERDYIE

    - -
    -
    - - - - -
    #define RCC_CIR_LSERDYIE   RCC_CIR_LSERDYIE_Msk
    -
    - -
    -
    - -

    ◆ RCC_CIR_HSIRDYIE_Pos

    - -
    -
    - - - - -
    #define RCC_CIR_HSIRDYIE_Pos   (10U)
    -
    - -
    -
    - -

    ◆ RCC_CIR_HSIRDYIE_Msk

    - -
    -
    - - - - -
    #define RCC_CIR_HSIRDYIE_Msk   (0x1UL << RCC_CIR_HSIRDYIE_Pos)
    -
    -

    0x00000400

    - -
    -
    - -

    ◆ RCC_CIR_HSIRDYIE

    - -
    -
    - - - - -
    #define RCC_CIR_HSIRDYIE   RCC_CIR_HSIRDYIE_Msk
    -
    - -
    -
    - -

    ◆ RCC_CIR_HSERDYIE_Pos

    - -
    -
    - - - - -
    #define RCC_CIR_HSERDYIE_Pos   (11U)
    -
    - -
    -
    - -

    ◆ RCC_CIR_HSERDYIE_Msk

    - -
    -
    - - - - -
    #define RCC_CIR_HSERDYIE_Msk   (0x1UL << RCC_CIR_HSERDYIE_Pos)
    -
    -

    0x00000800

    - -
    -
    - -

    ◆ RCC_CIR_HSERDYIE

    - -
    -
    - - - - -
    #define RCC_CIR_HSERDYIE   RCC_CIR_HSERDYIE_Msk
    -
    - -
    -
    - -

    ◆ RCC_CIR_PLLRDYIE_Pos

    - -
    -
    - - - - -
    #define RCC_CIR_PLLRDYIE_Pos   (12U)
    -
    - -
    -
    - -

    ◆ RCC_CIR_PLLRDYIE_Msk

    - -
    -
    - - - - -
    #define RCC_CIR_PLLRDYIE_Msk   (0x1UL << RCC_CIR_PLLRDYIE_Pos)
    -
    -

    0x00001000

    - -
    -
    - -

    ◆ RCC_CIR_PLLRDYIE

    - -
    -
    - - - - -
    #define RCC_CIR_PLLRDYIE   RCC_CIR_PLLRDYIE_Msk
    -
    - -
    -
    - -

    ◆ RCC_CIR_PLLI2SRDYIE_Pos

    - -
    -
    - - - - -
    #define RCC_CIR_PLLI2SRDYIE_Pos   (13U)
    -
    - -
    -
    - -

    ◆ RCC_CIR_PLLI2SRDYIE_Msk

    - -
    -
    - - - - -
    #define RCC_CIR_PLLI2SRDYIE_Msk   (0x1UL << RCC_CIR_PLLI2SRDYIE_Pos)
    -
    -

    0x00002000

    - -
    -
    - -

    ◆ RCC_CIR_PLLI2SRDYIE

    - -
    -
    - - - - -
    #define RCC_CIR_PLLI2SRDYIE   RCC_CIR_PLLI2SRDYIE_Msk
    -
    - -
    -
    - -

    ◆ RCC_CIR_LSIRDYC_Pos

    - -
    -
    - - - - -
    #define RCC_CIR_LSIRDYC_Pos   (16U)
    -
    - -
    -
    - -

    ◆ RCC_CIR_LSIRDYC_Msk

    - -
    -
    - - - - -
    #define RCC_CIR_LSIRDYC_Msk   (0x1UL << RCC_CIR_LSIRDYC_Pos)
    -
    -

    0x00010000

    - -
    -
    - -

    ◆ RCC_CIR_LSIRDYC

    - -
    -
    - - - - -
    #define RCC_CIR_LSIRDYC   RCC_CIR_LSIRDYC_Msk
    -
    - -
    -
    - -

    ◆ RCC_CIR_LSERDYC_Pos

    - -
    -
    - - - - -
    #define RCC_CIR_LSERDYC_Pos   (17U)
    -
    - -
    -
    - -

    ◆ RCC_CIR_LSERDYC_Msk

    - -
    -
    - - - - -
    #define RCC_CIR_LSERDYC_Msk   (0x1UL << RCC_CIR_LSERDYC_Pos)
    -
    -

    0x00020000

    - -
    -
    - -

    ◆ RCC_CIR_LSERDYC

    - -
    -
    - - - - -
    #define RCC_CIR_LSERDYC   RCC_CIR_LSERDYC_Msk
    -
    - -
    -
    - -

    ◆ RCC_CIR_HSIRDYC_Pos

    - -
    -
    - - - - -
    #define RCC_CIR_HSIRDYC_Pos   (18U)
    -
    - -
    -
    - -

    ◆ RCC_CIR_HSIRDYC_Msk

    - -
    -
    - - - - -
    #define RCC_CIR_HSIRDYC_Msk   (0x1UL << RCC_CIR_HSIRDYC_Pos)
    -
    -

    0x00040000

    - -
    -
    - -

    ◆ RCC_CIR_HSIRDYC

    - -
    -
    - - - - -
    #define RCC_CIR_HSIRDYC   RCC_CIR_HSIRDYC_Msk
    -
    - -
    -
    - -

    ◆ RCC_CIR_HSERDYC_Pos

    - -
    -
    - - - - -
    #define RCC_CIR_HSERDYC_Pos   (19U)
    -
    - -
    -
    - -

    ◆ RCC_CIR_HSERDYC_Msk

    - -
    -
    - - - - -
    #define RCC_CIR_HSERDYC_Msk   (0x1UL << RCC_CIR_HSERDYC_Pos)
    -
    -

    0x00080000

    - -
    -
    - -

    ◆ RCC_CIR_HSERDYC

    - -
    -
    - - - - -
    #define RCC_CIR_HSERDYC   RCC_CIR_HSERDYC_Msk
    -
    - -
    -
    - -

    ◆ RCC_CIR_PLLRDYC_Pos

    - -
    -
    - - - - -
    #define RCC_CIR_PLLRDYC_Pos   (20U)
    -
    - -
    -
    - -

    ◆ RCC_CIR_PLLRDYC_Msk

    - -
    -
    - - - - -
    #define RCC_CIR_PLLRDYC_Msk   (0x1UL << RCC_CIR_PLLRDYC_Pos)
    -
    -

    0x00100000

    - -
    -
    - -

    ◆ RCC_CIR_PLLRDYC

    - -
    -
    - - - - -
    #define RCC_CIR_PLLRDYC   RCC_CIR_PLLRDYC_Msk
    -
    - -
    -
    - -

    ◆ RCC_CIR_PLLI2SRDYC_Pos

    - -
    -
    - - - - -
    #define RCC_CIR_PLLI2SRDYC_Pos   (21U)
    -
    - -
    -
    - -

    ◆ RCC_CIR_PLLI2SRDYC_Msk

    - -
    -
    - - - - -
    #define RCC_CIR_PLLI2SRDYC_Msk   (0x1UL << RCC_CIR_PLLI2SRDYC_Pos)
    -
    -

    0x00200000

    - -
    -
    - -

    ◆ RCC_CIR_PLLI2SRDYC

    - -
    -
    - - - - -
    #define RCC_CIR_PLLI2SRDYC   RCC_CIR_PLLI2SRDYC_Msk
    -
    - -
    -
    - -

    ◆ RCC_CIR_CSSC_Pos

    - -
    -
    - - - - -
    #define RCC_CIR_CSSC_Pos   (23U)
    -
    - -
    -
    - -

    ◆ RCC_CIR_CSSC_Msk

    - -
    -
    - - - - -
    #define RCC_CIR_CSSC_Msk   (0x1UL << RCC_CIR_CSSC_Pos)
    -
    -

    0x00800000

    - -
    -
    - -

    ◆ RCC_CIR_CSSC

    - -
    -
    - - - - -
    #define RCC_CIR_CSSC   RCC_CIR_CSSC_Msk
    -
    - -
    -
    - -

    ◆ RCC_AHB1RSTR_GPIOARST_Pos

    - -
    -
    - - - - -
    #define RCC_AHB1RSTR_GPIOARST_Pos   (0U)
    -
    - -
    -
    - -

    ◆ RCC_AHB1RSTR_GPIOARST_Msk

    - -
    -
    - - - - -
    #define RCC_AHB1RSTR_GPIOARST_Msk   (0x1UL << RCC_AHB1RSTR_GPIOARST_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ RCC_AHB1RSTR_GPIOARST

    - -
    -
    - - - - -
    #define RCC_AHB1RSTR_GPIOARST   RCC_AHB1RSTR_GPIOARST_Msk
    -
    - -
    -
    - -

    ◆ RCC_AHB1RSTR_GPIOBRST_Pos

    - -
    -
    - - - - -
    #define RCC_AHB1RSTR_GPIOBRST_Pos   (1U)
    -
    - -
    -
    - -

    ◆ RCC_AHB1RSTR_GPIOBRST_Msk

    - -
    -
    - - - - -
    #define RCC_AHB1RSTR_GPIOBRST_Msk   (0x1UL << RCC_AHB1RSTR_GPIOBRST_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ RCC_AHB1RSTR_GPIOBRST

    - -
    -
    - - - - -
    #define RCC_AHB1RSTR_GPIOBRST   RCC_AHB1RSTR_GPIOBRST_Msk
    -
    - -
    -
    - -

    ◆ RCC_AHB1RSTR_GPIOCRST_Pos

    - -
    -
    - - - - -
    #define RCC_AHB1RSTR_GPIOCRST_Pos   (2U)
    -
    - -
    -
    - -

    ◆ RCC_AHB1RSTR_GPIOCRST_Msk

    - -
    -
    - - - - -
    #define RCC_AHB1RSTR_GPIOCRST_Msk   (0x1UL << RCC_AHB1RSTR_GPIOCRST_Pos)
    -
    -

    0x00000004

    - -
    -
    - -

    ◆ RCC_AHB1RSTR_GPIOCRST

    - -
    -
    - - - - -
    #define RCC_AHB1RSTR_GPIOCRST   RCC_AHB1RSTR_GPIOCRST_Msk
    -
    - -
    -
    - -

    ◆ RCC_AHB1RSTR_GPIODRST_Pos

    - -
    -
    - - - - -
    #define RCC_AHB1RSTR_GPIODRST_Pos   (3U)
    -
    - -
    -
    - -

    ◆ RCC_AHB1RSTR_GPIODRST_Msk

    - -
    -
    - - - - -
    #define RCC_AHB1RSTR_GPIODRST_Msk   (0x1UL << RCC_AHB1RSTR_GPIODRST_Pos)
    -
    -

    0x00000008

    - -
    -
    - -

    ◆ RCC_AHB1RSTR_GPIODRST

    - -
    -
    - - - - -
    #define RCC_AHB1RSTR_GPIODRST   RCC_AHB1RSTR_GPIODRST_Msk
    -
    - -
    -
    - -

    ◆ RCC_AHB1RSTR_GPIOERST_Pos

    - -
    -
    - - - - -
    #define RCC_AHB1RSTR_GPIOERST_Pos   (4U)
    -
    - -
    -
    - -

    ◆ RCC_AHB1RSTR_GPIOERST_Msk

    - -
    -
    - - - - -
    #define RCC_AHB1RSTR_GPIOERST_Msk   (0x1UL << RCC_AHB1RSTR_GPIOERST_Pos)
    -
    -

    0x00000010

    - -
    -
    - -

    ◆ RCC_AHB1RSTR_GPIOERST

    - -
    -
    - - - - -
    #define RCC_AHB1RSTR_GPIOERST   RCC_AHB1RSTR_GPIOERST_Msk
    -
    - -
    -
    - -

    ◆ RCC_AHB1RSTR_GPIOFRST_Pos

    - -
    -
    - - - - -
    #define RCC_AHB1RSTR_GPIOFRST_Pos   (5U)
    -
    - -
    -
    - -

    ◆ RCC_AHB1RSTR_GPIOFRST_Msk

    - -
    -
    - - - - -
    #define RCC_AHB1RSTR_GPIOFRST_Msk   (0x1UL << RCC_AHB1RSTR_GPIOFRST_Pos)
    -
    -

    0x00000020

    - -
    -
    - -

    ◆ RCC_AHB1RSTR_GPIOFRST

    - -
    -
    - - - - -
    #define RCC_AHB1RSTR_GPIOFRST   RCC_AHB1RSTR_GPIOFRST_Msk
    -
    - -
    -
    - -

    ◆ RCC_AHB1RSTR_GPIOGRST_Pos

    - -
    -
    - - - - -
    #define RCC_AHB1RSTR_GPIOGRST_Pos   (6U)
    -
    - -
    -
    - -

    ◆ RCC_AHB1RSTR_GPIOGRST_Msk

    - -
    -
    - - - - -
    #define RCC_AHB1RSTR_GPIOGRST_Msk   (0x1UL << RCC_AHB1RSTR_GPIOGRST_Pos)
    -
    -

    0x00000040

    - -
    -
    - -

    ◆ RCC_AHB1RSTR_GPIOGRST

    - -
    -
    - - - - -
    #define RCC_AHB1RSTR_GPIOGRST   RCC_AHB1RSTR_GPIOGRST_Msk
    -
    - -
    -
    - -

    ◆ RCC_AHB1RSTR_GPIOHRST_Pos

    - -
    -
    - - - - -
    #define RCC_AHB1RSTR_GPIOHRST_Pos   (7U)
    -
    - -
    -
    - -

    ◆ RCC_AHB1RSTR_GPIOHRST_Msk

    - -
    -
    - - - - -
    #define RCC_AHB1RSTR_GPIOHRST_Msk   (0x1UL << RCC_AHB1RSTR_GPIOHRST_Pos)
    -
    -

    0x00000080

    - -
    -
    - -

    ◆ RCC_AHB1RSTR_GPIOHRST

    - -
    -
    - - - - -
    #define RCC_AHB1RSTR_GPIOHRST   RCC_AHB1RSTR_GPIOHRST_Msk
    -
    - -
    -
    - -

    ◆ RCC_AHB1RSTR_GPIOIRST_Pos

    - -
    -
    - - - - -
    #define RCC_AHB1RSTR_GPIOIRST_Pos   (8U)
    -
    - -
    -
    - -

    ◆ RCC_AHB1RSTR_GPIOIRST_Msk

    - -
    -
    - - - - -
    #define RCC_AHB1RSTR_GPIOIRST_Msk   (0x1UL << RCC_AHB1RSTR_GPIOIRST_Pos)
    -
    -

    0x00000100

    - -
    -
    - -

    ◆ RCC_AHB1RSTR_GPIOIRST

    - -
    -
    - - - - -
    #define RCC_AHB1RSTR_GPIOIRST   RCC_AHB1RSTR_GPIOIRST_Msk
    -
    - -
    -
    - -

    ◆ RCC_AHB1RSTR_CRCRST_Pos

    - -
    -
    - - - - -
    #define RCC_AHB1RSTR_CRCRST_Pos   (12U)
    -
    - -
    -
    - -

    ◆ RCC_AHB1RSTR_CRCRST_Msk

    - -
    -
    - - - - -
    #define RCC_AHB1RSTR_CRCRST_Msk   (0x1UL << RCC_AHB1RSTR_CRCRST_Pos)
    -
    -

    0x00001000

    - -
    -
    - -

    ◆ RCC_AHB1RSTR_CRCRST

    - -
    -
    - - - - -
    #define RCC_AHB1RSTR_CRCRST   RCC_AHB1RSTR_CRCRST_Msk
    -
    - -
    -
    - -

    ◆ RCC_AHB1RSTR_DMA1RST_Pos

    - -
    -
    - - - - -
    #define RCC_AHB1RSTR_DMA1RST_Pos   (21U)
    -
    - -
    -
    - -

    ◆ RCC_AHB1RSTR_DMA1RST_Msk

    - -
    -
    - - - - -
    #define RCC_AHB1RSTR_DMA1RST_Msk   (0x1UL << RCC_AHB1RSTR_DMA1RST_Pos)
    -
    -

    0x00200000

    - -
    -
    - -

    ◆ RCC_AHB1RSTR_DMA1RST

    - -
    -
    - - - - -
    #define RCC_AHB1RSTR_DMA1RST   RCC_AHB1RSTR_DMA1RST_Msk
    -
    - -
    -
    - -

    ◆ RCC_AHB1RSTR_DMA2RST_Pos

    - -
    -
    - - - - -
    #define RCC_AHB1RSTR_DMA2RST_Pos   (22U)
    -
    - -
    -
    - -

    ◆ RCC_AHB1RSTR_DMA2RST_Msk

    - -
    -
    - - - - -
    #define RCC_AHB1RSTR_DMA2RST_Msk   (0x1UL << RCC_AHB1RSTR_DMA2RST_Pos)
    -
    -

    0x00400000

    - -
    -
    - -

    ◆ RCC_AHB1RSTR_DMA2RST

    - -
    -
    - - - - -
    #define RCC_AHB1RSTR_DMA2RST   RCC_AHB1RSTR_DMA2RST_Msk
    -
    - -
    -
    - -

    ◆ RCC_AHB1RSTR_ETHMACRST_Pos

    - -
    -
    - - - - -
    #define RCC_AHB1RSTR_ETHMACRST_Pos   (25U)
    -
    - -
    -
    - -

    ◆ RCC_AHB1RSTR_ETHMACRST_Msk

    - -
    -
    - - - - -
    #define RCC_AHB1RSTR_ETHMACRST_Msk   (0x1UL << RCC_AHB1RSTR_ETHMACRST_Pos)
    -
    -

    0x02000000

    - -
    -
    - -

    ◆ RCC_AHB1RSTR_ETHMACRST

    - -
    -
    - - - - -
    #define RCC_AHB1RSTR_ETHMACRST   RCC_AHB1RSTR_ETHMACRST_Msk
    -
    - -
    -
    - -

    ◆ RCC_AHB1RSTR_OTGHRST_Pos

    - -
    -
    - - - - -
    #define RCC_AHB1RSTR_OTGHRST_Pos   (29U)
    -
    - -
    -
    - -

    ◆ RCC_AHB1RSTR_OTGHRST_Msk

    - -
    -
    - - - - -
    #define RCC_AHB1RSTR_OTGHRST_Msk   (0x1UL << RCC_AHB1RSTR_OTGHRST_Pos)
    -
    -

    0x20000000

    - -
    -
    - -

    ◆ RCC_AHB1RSTR_OTGHRST

    - -
    -
    - - - - -
    #define RCC_AHB1RSTR_OTGHRST   RCC_AHB1RSTR_OTGHRST_Msk
    -
    - -
    -
    - -

    ◆ RCC_AHB2RSTR_DCMIRST_Pos

    - -
    -
    - - - - -
    #define RCC_AHB2RSTR_DCMIRST_Pos   (0U)
    -
    - -
    -
    - -

    ◆ RCC_AHB2RSTR_DCMIRST_Msk

    - -
    -
    - - - - -
    #define RCC_AHB2RSTR_DCMIRST_Msk   (0x1UL << RCC_AHB2RSTR_DCMIRST_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ RCC_AHB2RSTR_DCMIRST

    - -
    -
    - - - - -
    #define RCC_AHB2RSTR_DCMIRST   RCC_AHB2RSTR_DCMIRST_Msk
    -
    - -
    -
    - -

    ◆ RCC_AHB2RSTR_RNGRST_Pos

    - -
    -
    - - - - -
    #define RCC_AHB2RSTR_RNGRST_Pos   (6U)
    -
    - -
    -
    - -

    ◆ RCC_AHB2RSTR_RNGRST_Msk

    - -
    -
    - - - - -
    #define RCC_AHB2RSTR_RNGRST_Msk   (0x1UL << RCC_AHB2RSTR_RNGRST_Pos)
    -
    -

    0x00000040

    - -
    -
    - -

    ◆ RCC_AHB2RSTR_RNGRST

    - -
    -
    - - - - -
    #define RCC_AHB2RSTR_RNGRST   RCC_AHB2RSTR_RNGRST_Msk
    -
    - -
    -
    - -

    ◆ RCC_AHB2RSTR_OTGFSRST_Pos

    - -
    -
    - - - - -
    #define RCC_AHB2RSTR_OTGFSRST_Pos   (7U)
    -
    - -
    -
    - -

    ◆ RCC_AHB2RSTR_OTGFSRST_Msk

    - -
    -
    - - - - -
    #define RCC_AHB2RSTR_OTGFSRST_Msk   (0x1UL << RCC_AHB2RSTR_OTGFSRST_Pos)
    -
    -

    0x00000080

    - -
    -
    - -

    ◆ RCC_AHB2RSTR_OTGFSRST

    - -
    -
    - - - - -
    #define RCC_AHB2RSTR_OTGFSRST   RCC_AHB2RSTR_OTGFSRST_Msk
    -
    - -
    -
    - -

    ◆ RCC_AHB3RSTR_FSMCRST_Pos

    - -
    -
    - - - - -
    #define RCC_AHB3RSTR_FSMCRST_Pos   (0U)
    -
    - -
    -
    - -

    ◆ RCC_AHB3RSTR_FSMCRST_Msk

    - -
    -
    - - - - -
    #define RCC_AHB3RSTR_FSMCRST_Msk   (0x1UL << RCC_AHB3RSTR_FSMCRST_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ RCC_AHB3RSTR_FSMCRST

    - -
    -
    - - - - -
    #define RCC_AHB3RSTR_FSMCRST   RCC_AHB3RSTR_FSMCRST_Msk
    -
    - -
    -
    - -

    ◆ RCC_APB1RSTR_TIM2RST_Pos

    - -
    -
    - - - - -
    #define RCC_APB1RSTR_TIM2RST_Pos   (0U)
    -
    - -
    -
    - -

    ◆ RCC_APB1RSTR_TIM2RST_Msk

    - -
    -
    - - - - -
    #define RCC_APB1RSTR_TIM2RST_Msk   (0x1UL << RCC_APB1RSTR_TIM2RST_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ RCC_APB1RSTR_TIM2RST

    - -
    -
    - - - - -
    #define RCC_APB1RSTR_TIM2RST   RCC_APB1RSTR_TIM2RST_Msk
    -
    - -
    -
    - -

    ◆ RCC_APB1RSTR_TIM3RST_Pos

    - -
    -
    - - - - -
    #define RCC_APB1RSTR_TIM3RST_Pos   (1U)
    -
    - -
    -
    - -

    ◆ RCC_APB1RSTR_TIM3RST_Msk

    - -
    -
    - - - - -
    #define RCC_APB1RSTR_TIM3RST_Msk   (0x1UL << RCC_APB1RSTR_TIM3RST_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ RCC_APB1RSTR_TIM3RST

    - -
    -
    - - - - -
    #define RCC_APB1RSTR_TIM3RST   RCC_APB1RSTR_TIM3RST_Msk
    -
    - -
    -
    - -

    ◆ RCC_APB1RSTR_TIM4RST_Pos

    - -
    -
    - - - - -
    #define RCC_APB1RSTR_TIM4RST_Pos   (2U)
    -
    - -
    -
    - -

    ◆ RCC_APB1RSTR_TIM4RST_Msk

    - -
    -
    - - - - -
    #define RCC_APB1RSTR_TIM4RST_Msk   (0x1UL << RCC_APB1RSTR_TIM4RST_Pos)
    -
    -

    0x00000004

    - -
    -
    - -

    ◆ RCC_APB1RSTR_TIM4RST

    - -
    -
    - - - - -
    #define RCC_APB1RSTR_TIM4RST   RCC_APB1RSTR_TIM4RST_Msk
    -
    - -
    -
    - -

    ◆ RCC_APB1RSTR_TIM5RST_Pos

    - -
    -
    - - - - -
    #define RCC_APB1RSTR_TIM5RST_Pos   (3U)
    -
    - -
    -
    - -

    ◆ RCC_APB1RSTR_TIM5RST_Msk

    - -
    -
    - - - - -
    #define RCC_APB1RSTR_TIM5RST_Msk   (0x1UL << RCC_APB1RSTR_TIM5RST_Pos)
    -
    -

    0x00000008

    - -
    -
    - -

    ◆ RCC_APB1RSTR_TIM5RST

    - -
    -
    - - - - -
    #define RCC_APB1RSTR_TIM5RST   RCC_APB1RSTR_TIM5RST_Msk
    -
    - -
    -
    - -

    ◆ RCC_APB1RSTR_TIM6RST_Pos

    - -
    -
    - - - - -
    #define RCC_APB1RSTR_TIM6RST_Pos   (4U)
    -
    - -
    -
    - -

    ◆ RCC_APB1RSTR_TIM6RST_Msk

    - -
    -
    - - - - -
    #define RCC_APB1RSTR_TIM6RST_Msk   (0x1UL << RCC_APB1RSTR_TIM6RST_Pos)
    -
    -

    0x00000010

    - -
    -
    - -

    ◆ RCC_APB1RSTR_TIM6RST

    - -
    -
    - - - - -
    #define RCC_APB1RSTR_TIM6RST   RCC_APB1RSTR_TIM6RST_Msk
    -
    - -
    -
    - -

    ◆ RCC_APB1RSTR_TIM7RST_Pos

    - -
    -
    - - - - -
    #define RCC_APB1RSTR_TIM7RST_Pos   (5U)
    -
    - -
    -
    - -

    ◆ RCC_APB1RSTR_TIM7RST_Msk

    - -
    -
    - - - - -
    #define RCC_APB1RSTR_TIM7RST_Msk   (0x1UL << RCC_APB1RSTR_TIM7RST_Pos)
    -
    -

    0x00000020

    - -
    -
    - -

    ◆ RCC_APB1RSTR_TIM7RST

    - -
    -
    - - - - -
    #define RCC_APB1RSTR_TIM7RST   RCC_APB1RSTR_TIM7RST_Msk
    -
    - -
    -
    - -

    ◆ RCC_APB1RSTR_TIM12RST_Pos

    - -
    -
    - - - - -
    #define RCC_APB1RSTR_TIM12RST_Pos   (6U)
    -
    - -
    -
    - -

    ◆ RCC_APB1RSTR_TIM12RST_Msk

    - -
    -
    - - - - -
    #define RCC_APB1RSTR_TIM12RST_Msk   (0x1UL << RCC_APB1RSTR_TIM12RST_Pos)
    -
    -

    0x00000040

    - -
    -
    - -

    ◆ RCC_APB1RSTR_TIM12RST

    - -
    -
    - - - - -
    #define RCC_APB1RSTR_TIM12RST   RCC_APB1RSTR_TIM12RST_Msk
    -
    - -
    -
    - -

    ◆ RCC_APB1RSTR_TIM13RST_Pos

    - -
    -
    - - - - -
    #define RCC_APB1RSTR_TIM13RST_Pos   (7U)
    -
    - -
    -
    - -

    ◆ RCC_APB1RSTR_TIM13RST_Msk

    - -
    -
    - - - - -
    #define RCC_APB1RSTR_TIM13RST_Msk   (0x1UL << RCC_APB1RSTR_TIM13RST_Pos)
    -
    -

    0x00000080

    - -
    -
    - -

    ◆ RCC_APB1RSTR_TIM13RST

    - -
    -
    - - - - -
    #define RCC_APB1RSTR_TIM13RST   RCC_APB1RSTR_TIM13RST_Msk
    -
    - -
    -
    - -

    ◆ RCC_APB1RSTR_TIM14RST_Pos

    - -
    -
    - - - - -
    #define RCC_APB1RSTR_TIM14RST_Pos   (8U)
    -
    - -
    -
    - -

    ◆ RCC_APB1RSTR_TIM14RST_Msk

    - -
    -
    - - - - -
    #define RCC_APB1RSTR_TIM14RST_Msk   (0x1UL << RCC_APB1RSTR_TIM14RST_Pos)
    -
    -

    0x00000100

    - -
    -
    - -

    ◆ RCC_APB1RSTR_TIM14RST

    - -
    -
    - - - - -
    #define RCC_APB1RSTR_TIM14RST   RCC_APB1RSTR_TIM14RST_Msk
    -
    - -
    -
    - -

    ◆ RCC_APB1RSTR_WWDGRST_Pos

    - -
    -
    - - - - -
    #define RCC_APB1RSTR_WWDGRST_Pos   (11U)
    -
    - -
    -
    - -

    ◆ RCC_APB1RSTR_WWDGRST_Msk

    - -
    -
    - - - - -
    #define RCC_APB1RSTR_WWDGRST_Msk   (0x1UL << RCC_APB1RSTR_WWDGRST_Pos)
    -
    -

    0x00000800

    - -
    -
    - -

    ◆ RCC_APB1RSTR_WWDGRST

    - -
    -
    - - - - -
    #define RCC_APB1RSTR_WWDGRST   RCC_APB1RSTR_WWDGRST_Msk
    -
    - -
    -
    - -

    ◆ RCC_APB1RSTR_SPI2RST_Pos

    - -
    -
    - - - - -
    #define RCC_APB1RSTR_SPI2RST_Pos   (14U)
    -
    - -
    -
    - -

    ◆ RCC_APB1RSTR_SPI2RST_Msk

    - -
    -
    - - - - -
    #define RCC_APB1RSTR_SPI2RST_Msk   (0x1UL << RCC_APB1RSTR_SPI2RST_Pos)
    -
    -

    0x00004000

    - -
    -
    - -

    ◆ RCC_APB1RSTR_SPI2RST

    - -
    -
    - - - - -
    #define RCC_APB1RSTR_SPI2RST   RCC_APB1RSTR_SPI2RST_Msk
    -
    - -
    -
    - -

    ◆ RCC_APB1RSTR_SPI3RST_Pos

    - -
    -
    - - - - -
    #define RCC_APB1RSTR_SPI3RST_Pos   (15U)
    -
    - -
    -
    - -

    ◆ RCC_APB1RSTR_SPI3RST_Msk

    - -
    -
    - - - - -
    #define RCC_APB1RSTR_SPI3RST_Msk   (0x1UL << RCC_APB1RSTR_SPI3RST_Pos)
    -
    -

    0x00008000

    - -
    -
    - -

    ◆ RCC_APB1RSTR_SPI3RST

    - -
    -
    - - - - -
    #define RCC_APB1RSTR_SPI3RST   RCC_APB1RSTR_SPI3RST_Msk
    -
    - -
    -
    - -

    ◆ RCC_APB1RSTR_USART2RST_Pos

    - -
    -
    - - - - -
    #define RCC_APB1RSTR_USART2RST_Pos   (17U)
    -
    - -
    -
    - -

    ◆ RCC_APB1RSTR_USART2RST_Msk

    - -
    -
    - - - - -
    #define RCC_APB1RSTR_USART2RST_Msk   (0x1UL << RCC_APB1RSTR_USART2RST_Pos)
    -
    -

    0x00020000

    - -
    -
    - -

    ◆ RCC_APB1RSTR_USART2RST

    - -
    -
    - - - - -
    #define RCC_APB1RSTR_USART2RST   RCC_APB1RSTR_USART2RST_Msk
    -
    - -
    -
    - -

    ◆ RCC_APB1RSTR_USART3RST_Pos

    - -
    -
    - - - - -
    #define RCC_APB1RSTR_USART3RST_Pos   (18U)
    -
    - -
    -
    - -

    ◆ RCC_APB1RSTR_USART3RST_Msk

    - -
    -
    - - - - -
    #define RCC_APB1RSTR_USART3RST_Msk   (0x1UL << RCC_APB1RSTR_USART3RST_Pos)
    -
    -

    0x00040000

    - -
    -
    - -

    ◆ RCC_APB1RSTR_USART3RST

    - -
    -
    - - - - -
    #define RCC_APB1RSTR_USART3RST   RCC_APB1RSTR_USART3RST_Msk
    -
    - -
    -
    - -

    ◆ RCC_APB1RSTR_UART4RST_Pos

    - -
    -
    - - - - -
    #define RCC_APB1RSTR_UART4RST_Pos   (19U)
    -
    - -
    -
    - -

    ◆ RCC_APB1RSTR_UART4RST_Msk

    - -
    -
    - - - - -
    #define RCC_APB1RSTR_UART4RST_Msk   (0x1UL << RCC_APB1RSTR_UART4RST_Pos)
    -
    -

    0x00080000

    - -
    -
    - -

    ◆ RCC_APB1RSTR_UART4RST

    - -
    -
    - - - - -
    #define RCC_APB1RSTR_UART4RST   RCC_APB1RSTR_UART4RST_Msk
    -
    - -
    -
    - -

    ◆ RCC_APB1RSTR_UART5RST_Pos

    - -
    -
    - - - - -
    #define RCC_APB1RSTR_UART5RST_Pos   (20U)
    -
    - -
    -
    - -

    ◆ RCC_APB1RSTR_UART5RST_Msk

    - -
    -
    - - - - -
    #define RCC_APB1RSTR_UART5RST_Msk   (0x1UL << RCC_APB1RSTR_UART5RST_Pos)
    -
    -

    0x00100000

    - -
    -
    - -

    ◆ RCC_APB1RSTR_UART5RST

    - -
    -
    - - - - -
    #define RCC_APB1RSTR_UART5RST   RCC_APB1RSTR_UART5RST_Msk
    -
    - -
    -
    - -

    ◆ RCC_APB1RSTR_I2C1RST_Pos

    - -
    -
    - - - - -
    #define RCC_APB1RSTR_I2C1RST_Pos   (21U)
    -
    - -
    -
    - -

    ◆ RCC_APB1RSTR_I2C1RST_Msk

    - -
    -
    - - - - -
    #define RCC_APB1RSTR_I2C1RST_Msk   (0x1UL << RCC_APB1RSTR_I2C1RST_Pos)
    -
    -

    0x00200000

    - -
    -
    - -

    ◆ RCC_APB1RSTR_I2C1RST

    - -
    -
    - - - - -
    #define RCC_APB1RSTR_I2C1RST   RCC_APB1RSTR_I2C1RST_Msk
    -
    - -
    -
    - -

    ◆ RCC_APB1RSTR_I2C2RST_Pos

    - -
    -
    - - - - -
    #define RCC_APB1RSTR_I2C2RST_Pos   (22U)
    -
    - -
    -
    - -

    ◆ RCC_APB1RSTR_I2C2RST_Msk

    - -
    -
    - - - - -
    #define RCC_APB1RSTR_I2C2RST_Msk   (0x1UL << RCC_APB1RSTR_I2C2RST_Pos)
    -
    -

    0x00400000

    - -
    -
    - -

    ◆ RCC_APB1RSTR_I2C2RST

    - -
    -
    - - - - -
    #define RCC_APB1RSTR_I2C2RST   RCC_APB1RSTR_I2C2RST_Msk
    -
    - -
    -
    - -

    ◆ RCC_APB1RSTR_I2C3RST_Pos

    - -
    -
    - - - - -
    #define RCC_APB1RSTR_I2C3RST_Pos   (23U)
    -
    - -
    -
    - -

    ◆ RCC_APB1RSTR_I2C3RST_Msk

    - -
    -
    - - - - -
    #define RCC_APB1RSTR_I2C3RST_Msk   (0x1UL << RCC_APB1RSTR_I2C3RST_Pos)
    -
    -

    0x00800000

    - -
    -
    - -

    ◆ RCC_APB1RSTR_I2C3RST

    - -
    -
    - - - - -
    #define RCC_APB1RSTR_I2C3RST   RCC_APB1RSTR_I2C3RST_Msk
    -
    - -
    -
    - -

    ◆ RCC_APB1RSTR_CAN1RST_Pos

    - -
    -
    - - - - -
    #define RCC_APB1RSTR_CAN1RST_Pos   (25U)
    -
    - -
    -
    - -

    ◆ RCC_APB1RSTR_CAN1RST_Msk

    - -
    -
    - - - - -
    #define RCC_APB1RSTR_CAN1RST_Msk   (0x1UL << RCC_APB1RSTR_CAN1RST_Pos)
    -
    -

    0x02000000

    - -
    -
    - -

    ◆ RCC_APB1RSTR_CAN1RST

    - -
    -
    - - - - -
    #define RCC_APB1RSTR_CAN1RST   RCC_APB1RSTR_CAN1RST_Msk
    -
    - -
    -
    - -

    ◆ RCC_APB1RSTR_CAN2RST_Pos

    - -
    -
    - - - - -
    #define RCC_APB1RSTR_CAN2RST_Pos   (26U)
    -
    - -
    -
    - -

    ◆ RCC_APB1RSTR_CAN2RST_Msk

    - -
    -
    - - - - -
    #define RCC_APB1RSTR_CAN2RST_Msk   (0x1UL << RCC_APB1RSTR_CAN2RST_Pos)
    -
    -

    0x04000000

    - -
    -
    - -

    ◆ RCC_APB1RSTR_CAN2RST

    - -
    -
    - - - - -
    #define RCC_APB1RSTR_CAN2RST   RCC_APB1RSTR_CAN2RST_Msk
    -
    - -
    -
    - -

    ◆ RCC_APB1RSTR_PWRRST_Pos

    - -
    -
    - - - - -
    #define RCC_APB1RSTR_PWRRST_Pos   (28U)
    -
    - -
    -
    - -

    ◆ RCC_APB1RSTR_PWRRST_Msk

    - -
    -
    - - - - -
    #define RCC_APB1RSTR_PWRRST_Msk   (0x1UL << RCC_APB1RSTR_PWRRST_Pos)
    -
    -

    0x10000000

    - -
    -
    - -

    ◆ RCC_APB1RSTR_PWRRST

    - -
    -
    - - - - -
    #define RCC_APB1RSTR_PWRRST   RCC_APB1RSTR_PWRRST_Msk
    -
    - -
    -
    - -

    ◆ RCC_APB1RSTR_DACRST_Pos

    - -
    -
    - - - - -
    #define RCC_APB1RSTR_DACRST_Pos   (29U)
    -
    - -
    -
    - -

    ◆ RCC_APB1RSTR_DACRST_Msk

    - -
    -
    - - - - -
    #define RCC_APB1RSTR_DACRST_Msk   (0x1UL << RCC_APB1RSTR_DACRST_Pos)
    -
    -

    0x20000000

    - -
    -
    - -

    ◆ RCC_APB1RSTR_DACRST

    - -
    -
    - - - - -
    #define RCC_APB1RSTR_DACRST   RCC_APB1RSTR_DACRST_Msk
    -
    - -
    -
    - -

    ◆ RCC_APB2RSTR_TIM1RST_Pos

    - -
    -
    - - - - -
    #define RCC_APB2RSTR_TIM1RST_Pos   (0U)
    -
    - -
    -
    - -

    ◆ RCC_APB2RSTR_TIM1RST_Msk

    - -
    -
    - - - - -
    #define RCC_APB2RSTR_TIM1RST_Msk   (0x1UL << RCC_APB2RSTR_TIM1RST_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ RCC_APB2RSTR_TIM1RST

    - -
    -
    - - - - -
    #define RCC_APB2RSTR_TIM1RST   RCC_APB2RSTR_TIM1RST_Msk
    -
    - -
    -
    - -

    ◆ RCC_APB2RSTR_TIM8RST_Pos

    - -
    -
    - - - - -
    #define RCC_APB2RSTR_TIM8RST_Pos   (1U)
    -
    - -
    -
    - -

    ◆ RCC_APB2RSTR_TIM8RST_Msk

    - -
    -
    - - - - -
    #define RCC_APB2RSTR_TIM8RST_Msk   (0x1UL << RCC_APB2RSTR_TIM8RST_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ RCC_APB2RSTR_TIM8RST

    - -
    -
    - - - - -
    #define RCC_APB2RSTR_TIM8RST   RCC_APB2RSTR_TIM8RST_Msk
    -
    - -
    -
    - -

    ◆ RCC_APB2RSTR_USART1RST_Pos

    - -
    -
    - - - - -
    #define RCC_APB2RSTR_USART1RST_Pos   (4U)
    -
    - -
    -
    - -

    ◆ RCC_APB2RSTR_USART1RST_Msk

    - -
    -
    - - - - -
    #define RCC_APB2RSTR_USART1RST_Msk   (0x1UL << RCC_APB2RSTR_USART1RST_Pos)
    -
    -

    0x00000010

    - -
    -
    - -

    ◆ RCC_APB2RSTR_USART1RST

    - -
    -
    - - - - -
    #define RCC_APB2RSTR_USART1RST   RCC_APB2RSTR_USART1RST_Msk
    -
    - -
    -
    - -

    ◆ RCC_APB2RSTR_USART6RST_Pos

    - -
    -
    - - - - -
    #define RCC_APB2RSTR_USART6RST_Pos   (5U)
    -
    - -
    -
    - -

    ◆ RCC_APB2RSTR_USART6RST_Msk

    - -
    -
    - - - - -
    #define RCC_APB2RSTR_USART6RST_Msk   (0x1UL << RCC_APB2RSTR_USART6RST_Pos)
    -
    -

    0x00000020

    - -
    -
    - -

    ◆ RCC_APB2RSTR_USART6RST

    - -
    -
    - - - - -
    #define RCC_APB2RSTR_USART6RST   RCC_APB2RSTR_USART6RST_Msk
    -
    - -
    -
    - -

    ◆ RCC_APB2RSTR_ADCRST_Pos

    - -
    -
    - - - - -
    #define RCC_APB2RSTR_ADCRST_Pos   (8U)
    -
    - -
    -
    - -

    ◆ RCC_APB2RSTR_ADCRST_Msk

    - -
    -
    - - - - -
    #define RCC_APB2RSTR_ADCRST_Msk   (0x1UL << RCC_APB2RSTR_ADCRST_Pos)
    -
    -

    0x00000100

    - -
    -
    - -

    ◆ RCC_APB2RSTR_ADCRST

    - -
    -
    - - - - -
    #define RCC_APB2RSTR_ADCRST   RCC_APB2RSTR_ADCRST_Msk
    -
    - -
    -
    - -

    ◆ RCC_APB2RSTR_SDIORST_Pos

    - -
    -
    - - - - -
    #define RCC_APB2RSTR_SDIORST_Pos   (11U)
    -
    - -
    -
    - -

    ◆ RCC_APB2RSTR_SDIORST_Msk

    - -
    -
    - - - - -
    #define RCC_APB2RSTR_SDIORST_Msk   (0x1UL << RCC_APB2RSTR_SDIORST_Pos)
    -
    -

    0x00000800

    - -
    -
    - -

    ◆ RCC_APB2RSTR_SDIORST

    - -
    -
    - - - - -
    #define RCC_APB2RSTR_SDIORST   RCC_APB2RSTR_SDIORST_Msk
    -
    - -
    -
    - -

    ◆ RCC_APB2RSTR_SPI1RST_Pos

    - -
    -
    - - - - -
    #define RCC_APB2RSTR_SPI1RST_Pos   (12U)
    -
    - -
    -
    - -

    ◆ RCC_APB2RSTR_SPI1RST_Msk

    - -
    -
    - - - - -
    #define RCC_APB2RSTR_SPI1RST_Msk   (0x1UL << RCC_APB2RSTR_SPI1RST_Pos)
    -
    -

    0x00001000

    - -
    -
    - -

    ◆ RCC_APB2RSTR_SPI1RST

    - -
    -
    - - - - -
    #define RCC_APB2RSTR_SPI1RST   RCC_APB2RSTR_SPI1RST_Msk
    -
    - -
    -
    - -

    ◆ RCC_APB2RSTR_SYSCFGRST_Pos

    - -
    -
    - - - - -
    #define RCC_APB2RSTR_SYSCFGRST_Pos   (14U)
    -
    - -
    -
    - -

    ◆ RCC_APB2RSTR_SYSCFGRST_Msk

    - -
    -
    - - - - -
    #define RCC_APB2RSTR_SYSCFGRST_Msk   (0x1UL << RCC_APB2RSTR_SYSCFGRST_Pos)
    -
    -

    0x00004000

    - -
    -
    - -

    ◆ RCC_APB2RSTR_SYSCFGRST

    - -
    -
    - - - - -
    #define RCC_APB2RSTR_SYSCFGRST   RCC_APB2RSTR_SYSCFGRST_Msk
    -
    - -
    -
    - -

    ◆ RCC_APB2RSTR_TIM9RST_Pos

    - -
    -
    - - - - -
    #define RCC_APB2RSTR_TIM9RST_Pos   (16U)
    -
    - -
    -
    - -

    ◆ RCC_APB2RSTR_TIM9RST_Msk

    - -
    -
    - - - - -
    #define RCC_APB2RSTR_TIM9RST_Msk   (0x1UL << RCC_APB2RSTR_TIM9RST_Pos)
    -
    -

    0x00010000

    - -
    -
    - -

    ◆ RCC_APB2RSTR_TIM9RST

    - -
    -
    - - - - -
    #define RCC_APB2RSTR_TIM9RST   RCC_APB2RSTR_TIM9RST_Msk
    -
    - -
    -
    - -

    ◆ RCC_APB2RSTR_TIM10RST_Pos

    - -
    -
    - - - - -
    #define RCC_APB2RSTR_TIM10RST_Pos   (17U)
    -
    - -
    -
    - -

    ◆ RCC_APB2RSTR_TIM10RST_Msk

    - -
    -
    - - - - -
    #define RCC_APB2RSTR_TIM10RST_Msk   (0x1UL << RCC_APB2RSTR_TIM10RST_Pos)
    -
    -

    0x00020000

    - -
    -
    - -

    ◆ RCC_APB2RSTR_TIM10RST

    - -
    -
    - - - - -
    #define RCC_APB2RSTR_TIM10RST   RCC_APB2RSTR_TIM10RST_Msk
    -
    - -
    -
    - -

    ◆ RCC_APB2RSTR_TIM11RST_Pos

    - -
    -
    - - - - -
    #define RCC_APB2RSTR_TIM11RST_Pos   (18U)
    -
    - -
    -
    - -

    ◆ RCC_APB2RSTR_TIM11RST_Msk

    - -
    -
    - - - - -
    #define RCC_APB2RSTR_TIM11RST_Msk   (0x1UL << RCC_APB2RSTR_TIM11RST_Pos)
    -
    -

    0x00040000

    - -
    -
    - -

    ◆ RCC_APB2RSTR_TIM11RST

    - -
    -
    - - - - -
    #define RCC_APB2RSTR_TIM11RST   RCC_APB2RSTR_TIM11RST_Msk
    -
    - -
    -
    - -

    ◆ RCC_APB2RSTR_SPI1

    - -
    -
    - - - - -
    #define RCC_APB2RSTR_SPI1   RCC_APB2RSTR_SPI1RST
    -
    - -
    -
    - -

    ◆ RCC_AHB1ENR_GPIOAEN_Pos

    - -
    -
    - - - - -
    #define RCC_AHB1ENR_GPIOAEN_Pos   (0U)
    -
    - -
    -
    - -

    ◆ RCC_AHB1ENR_GPIOAEN_Msk

    - -
    -
    - - - - -
    #define RCC_AHB1ENR_GPIOAEN_Msk   (0x1UL << RCC_AHB1ENR_GPIOAEN_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ RCC_AHB1ENR_GPIOAEN

    - -
    -
    - - - - -
    #define RCC_AHB1ENR_GPIOAEN   RCC_AHB1ENR_GPIOAEN_Msk
    -
    - -
    -
    - -

    ◆ RCC_AHB1ENR_GPIOBEN_Pos

    - -
    -
    - - - - -
    #define RCC_AHB1ENR_GPIOBEN_Pos   (1U)
    -
    - -
    -
    - -

    ◆ RCC_AHB1ENR_GPIOBEN_Msk

    - -
    -
    - - - - -
    #define RCC_AHB1ENR_GPIOBEN_Msk   (0x1UL << RCC_AHB1ENR_GPIOBEN_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ RCC_AHB1ENR_GPIOBEN

    - -
    -
    - - - - -
    #define RCC_AHB1ENR_GPIOBEN   RCC_AHB1ENR_GPIOBEN_Msk
    -
    - -
    -
    - -

    ◆ RCC_AHB1ENR_GPIOCEN_Pos

    - -
    -
    - - - - -
    #define RCC_AHB1ENR_GPIOCEN_Pos   (2U)
    -
    - -
    -
    - -

    ◆ RCC_AHB1ENR_GPIOCEN_Msk

    - -
    -
    - - - - -
    #define RCC_AHB1ENR_GPIOCEN_Msk   (0x1UL << RCC_AHB1ENR_GPIOCEN_Pos)
    -
    -

    0x00000004

    - -
    -
    - -

    ◆ RCC_AHB1ENR_GPIOCEN

    - -
    -
    - - - - -
    #define RCC_AHB1ENR_GPIOCEN   RCC_AHB1ENR_GPIOCEN_Msk
    -
    - -
    -
    - -

    ◆ RCC_AHB1ENR_GPIODEN_Pos

    - -
    -
    - - - - -
    #define RCC_AHB1ENR_GPIODEN_Pos   (3U)
    -
    - -
    -
    - -

    ◆ RCC_AHB1ENR_GPIODEN_Msk

    - -
    -
    - - - - -
    #define RCC_AHB1ENR_GPIODEN_Msk   (0x1UL << RCC_AHB1ENR_GPIODEN_Pos)
    -
    -

    0x00000008

    - -
    -
    - -

    ◆ RCC_AHB1ENR_GPIODEN

    - -
    -
    - - - - -
    #define RCC_AHB1ENR_GPIODEN   RCC_AHB1ENR_GPIODEN_Msk
    -
    - -
    -
    - -

    ◆ RCC_AHB1ENR_GPIOEEN_Pos

    - -
    -
    - - - - -
    #define RCC_AHB1ENR_GPIOEEN_Pos   (4U)
    -
    - -
    -
    - -

    ◆ RCC_AHB1ENR_GPIOEEN_Msk

    - -
    -
    - - - - -
    #define RCC_AHB1ENR_GPIOEEN_Msk   (0x1UL << RCC_AHB1ENR_GPIOEEN_Pos)
    -
    -

    0x00000010

    - -
    -
    - -

    ◆ RCC_AHB1ENR_GPIOEEN

    - -
    -
    - - - - -
    #define RCC_AHB1ENR_GPIOEEN   RCC_AHB1ENR_GPIOEEN_Msk
    -
    - -
    -
    - -

    ◆ RCC_AHB1ENR_GPIOFEN_Pos

    - -
    -
    - - - - -
    #define RCC_AHB1ENR_GPIOFEN_Pos   (5U)
    -
    - -
    -
    - -

    ◆ RCC_AHB1ENR_GPIOFEN_Msk

    - -
    -
    - - - - -
    #define RCC_AHB1ENR_GPIOFEN_Msk   (0x1UL << RCC_AHB1ENR_GPIOFEN_Pos)
    -
    -

    0x00000020

    - -
    -
    - -

    ◆ RCC_AHB1ENR_GPIOFEN

    - -
    -
    - - - - -
    #define RCC_AHB1ENR_GPIOFEN   RCC_AHB1ENR_GPIOFEN_Msk
    -
    - -
    -
    - -

    ◆ RCC_AHB1ENR_GPIOGEN_Pos

    - -
    -
    - - - - -
    #define RCC_AHB1ENR_GPIOGEN_Pos   (6U)
    -
    - -
    -
    - -

    ◆ RCC_AHB1ENR_GPIOGEN_Msk

    - -
    -
    - - - - -
    #define RCC_AHB1ENR_GPIOGEN_Msk   (0x1UL << RCC_AHB1ENR_GPIOGEN_Pos)
    -
    -

    0x00000040

    - -
    -
    - -

    ◆ RCC_AHB1ENR_GPIOGEN

    - -
    -
    - - - - -
    #define RCC_AHB1ENR_GPIOGEN   RCC_AHB1ENR_GPIOGEN_Msk
    -
    - -
    -
    - -

    ◆ RCC_AHB1ENR_GPIOHEN_Pos

    - -
    -
    - - - - -
    #define RCC_AHB1ENR_GPIOHEN_Pos   (7U)
    -
    - -
    -
    - -

    ◆ RCC_AHB1ENR_GPIOHEN_Msk

    - -
    -
    - - - - -
    #define RCC_AHB1ENR_GPIOHEN_Msk   (0x1UL << RCC_AHB1ENR_GPIOHEN_Pos)
    -
    -

    0x00000080

    - -
    -
    - -

    ◆ RCC_AHB1ENR_GPIOHEN

    - -
    -
    - - - - -
    #define RCC_AHB1ENR_GPIOHEN   RCC_AHB1ENR_GPIOHEN_Msk
    -
    - -
    -
    - -

    ◆ RCC_AHB1ENR_GPIOIEN_Pos

    - -
    -
    - - - - -
    #define RCC_AHB1ENR_GPIOIEN_Pos   (8U)
    -
    - -
    -
    - -

    ◆ RCC_AHB1ENR_GPIOIEN_Msk

    - -
    -
    - - - - -
    #define RCC_AHB1ENR_GPIOIEN_Msk   (0x1UL << RCC_AHB1ENR_GPIOIEN_Pos)
    -
    -

    0x00000100

    - -
    -
    - -

    ◆ RCC_AHB1ENR_GPIOIEN

    - -
    -
    - - - - -
    #define RCC_AHB1ENR_GPIOIEN   RCC_AHB1ENR_GPIOIEN_Msk
    -
    - -
    -
    - -

    ◆ RCC_AHB1ENR_CRCEN_Pos

    - -
    -
    - - - - -
    #define RCC_AHB1ENR_CRCEN_Pos   (12U)
    -
    - -
    -
    - -

    ◆ RCC_AHB1ENR_CRCEN_Msk

    - -
    -
    - - - - -
    #define RCC_AHB1ENR_CRCEN_Msk   (0x1UL << RCC_AHB1ENR_CRCEN_Pos)
    -
    -

    0x00001000

    - -
    -
    - -

    ◆ RCC_AHB1ENR_CRCEN

    - -
    -
    - - - - -
    #define RCC_AHB1ENR_CRCEN   RCC_AHB1ENR_CRCEN_Msk
    -
    - -
    -
    - -

    ◆ RCC_AHB1ENR_BKPSRAMEN_Pos

    - -
    -
    - - - - -
    #define RCC_AHB1ENR_BKPSRAMEN_Pos   (18U)
    -
    - -
    -
    - -

    ◆ RCC_AHB1ENR_BKPSRAMEN_Msk

    - -
    -
    - - - - -
    #define RCC_AHB1ENR_BKPSRAMEN_Msk   (0x1UL << RCC_AHB1ENR_BKPSRAMEN_Pos)
    -
    -

    0x00040000

    - -
    -
    - -

    ◆ RCC_AHB1ENR_BKPSRAMEN

    - -
    -
    - - - - -
    #define RCC_AHB1ENR_BKPSRAMEN   RCC_AHB1ENR_BKPSRAMEN_Msk
    -
    - -
    -
    - -

    ◆ RCC_AHB1ENR_CCMDATARAMEN_Pos

    - -
    -
    - - - - -
    #define RCC_AHB1ENR_CCMDATARAMEN_Pos   (20U)
    -
    - -
    -
    - -

    ◆ RCC_AHB1ENR_CCMDATARAMEN_Msk

    - -
    -
    - - - - -
    #define RCC_AHB1ENR_CCMDATARAMEN_Msk   (0x1UL << RCC_AHB1ENR_CCMDATARAMEN_Pos)
    -
    -

    0x00100000

    - -
    -
    - -

    ◆ RCC_AHB1ENR_CCMDATARAMEN

    - -
    -
    - - - - -
    #define RCC_AHB1ENR_CCMDATARAMEN   RCC_AHB1ENR_CCMDATARAMEN_Msk
    -
    - -
    -
    - -

    ◆ RCC_AHB1ENR_DMA1EN_Pos

    - -
    -
    - - - - -
    #define RCC_AHB1ENR_DMA1EN_Pos   (21U)
    -
    - -
    -
    - -

    ◆ RCC_AHB1ENR_DMA1EN_Msk

    - -
    -
    - - - - -
    #define RCC_AHB1ENR_DMA1EN_Msk   (0x1UL << RCC_AHB1ENR_DMA1EN_Pos)
    -
    -

    0x00200000

    - -
    -
    - -

    ◆ RCC_AHB1ENR_DMA1EN

    - -
    -
    - - - - -
    #define RCC_AHB1ENR_DMA1EN   RCC_AHB1ENR_DMA1EN_Msk
    -
    - -
    -
    - -

    ◆ RCC_AHB1ENR_DMA2EN_Pos

    - -
    -
    - - - - -
    #define RCC_AHB1ENR_DMA2EN_Pos   (22U)
    -
    - -
    -
    - -

    ◆ RCC_AHB1ENR_DMA2EN_Msk

    - -
    -
    - - - - -
    #define RCC_AHB1ENR_DMA2EN_Msk   (0x1UL << RCC_AHB1ENR_DMA2EN_Pos)
    -
    -

    0x00400000

    - -
    -
    - -

    ◆ RCC_AHB1ENR_DMA2EN

    - -
    -
    - - - - -
    #define RCC_AHB1ENR_DMA2EN   RCC_AHB1ENR_DMA2EN_Msk
    -
    - -
    -
    - -

    ◆ RCC_AHB1ENR_ETHMACEN_Pos

    - -
    -
    - - - - -
    #define RCC_AHB1ENR_ETHMACEN_Pos   (25U)
    -
    - -
    -
    - -

    ◆ RCC_AHB1ENR_ETHMACEN_Msk

    - -
    -
    - - - - -
    #define RCC_AHB1ENR_ETHMACEN_Msk   (0x1UL << RCC_AHB1ENR_ETHMACEN_Pos)
    -
    -

    0x02000000

    - -
    -
    - -

    ◆ RCC_AHB1ENR_ETHMACEN

    - -
    -
    - - - - -
    #define RCC_AHB1ENR_ETHMACEN   RCC_AHB1ENR_ETHMACEN_Msk
    -
    - -
    -
    - -

    ◆ RCC_AHB1ENR_ETHMACTXEN_Pos

    - -
    -
    - - - - -
    #define RCC_AHB1ENR_ETHMACTXEN_Pos   (26U)
    -
    - -
    -
    - -

    ◆ RCC_AHB1ENR_ETHMACTXEN_Msk

    - -
    -
    - - - - -
    #define RCC_AHB1ENR_ETHMACTXEN_Msk   (0x1UL << RCC_AHB1ENR_ETHMACTXEN_Pos)
    -
    -

    0x04000000

    - -
    -
    - -

    ◆ RCC_AHB1ENR_ETHMACTXEN

    - -
    -
    - - - - -
    #define RCC_AHB1ENR_ETHMACTXEN   RCC_AHB1ENR_ETHMACTXEN_Msk
    -
    - -
    -
    - -

    ◆ RCC_AHB1ENR_ETHMACRXEN_Pos

    - -
    -
    - - - - -
    #define RCC_AHB1ENR_ETHMACRXEN_Pos   (27U)
    -
    - -
    -
    - -

    ◆ RCC_AHB1ENR_ETHMACRXEN_Msk

    - -
    -
    - - - - -
    #define RCC_AHB1ENR_ETHMACRXEN_Msk   (0x1UL << RCC_AHB1ENR_ETHMACRXEN_Pos)
    -
    -

    0x08000000

    - -
    -
    - -

    ◆ RCC_AHB1ENR_ETHMACRXEN

    - -
    -
    - - - - -
    #define RCC_AHB1ENR_ETHMACRXEN   RCC_AHB1ENR_ETHMACRXEN_Msk
    -
    - -
    -
    - -

    ◆ RCC_AHB1ENR_ETHMACPTPEN_Pos

    - -
    -
    - - - - -
    #define RCC_AHB1ENR_ETHMACPTPEN_Pos   (28U)
    -
    - -
    -
    - -

    ◆ RCC_AHB1ENR_ETHMACPTPEN_Msk

    - -
    -
    - - - - -
    #define RCC_AHB1ENR_ETHMACPTPEN_Msk   (0x1UL << RCC_AHB1ENR_ETHMACPTPEN_Pos)
    -
    -

    0x10000000

    - -
    -
    - -

    ◆ RCC_AHB1ENR_ETHMACPTPEN

    - -
    -
    - - - - -
    #define RCC_AHB1ENR_ETHMACPTPEN   RCC_AHB1ENR_ETHMACPTPEN_Msk
    -
    - -
    -
    - -

    ◆ RCC_AHB1ENR_OTGHSEN_Pos

    - -
    -
    - - - - -
    #define RCC_AHB1ENR_OTGHSEN_Pos   (29U)
    -
    - -
    -
    - -

    ◆ RCC_AHB1ENR_OTGHSEN_Msk

    - -
    -
    - - - - -
    #define RCC_AHB1ENR_OTGHSEN_Msk   (0x1UL << RCC_AHB1ENR_OTGHSEN_Pos)
    -
    -

    0x20000000

    - -
    -
    - -

    ◆ RCC_AHB1ENR_OTGHSEN

    - -
    -
    - - - - -
    #define RCC_AHB1ENR_OTGHSEN   RCC_AHB1ENR_OTGHSEN_Msk
    -
    - -
    -
    - -

    ◆ RCC_AHB1ENR_OTGHSULPIEN_Pos

    - -
    -
    - - - - -
    #define RCC_AHB1ENR_OTGHSULPIEN_Pos   (30U)
    -
    - -
    -
    - -

    ◆ RCC_AHB1ENR_OTGHSULPIEN_Msk

    - -
    -
    - - - - -
    #define RCC_AHB1ENR_OTGHSULPIEN_Msk   (0x1UL << RCC_AHB1ENR_OTGHSULPIEN_Pos)
    -
    -

    0x40000000

    - -
    -
    - -

    ◆ RCC_AHB1ENR_OTGHSULPIEN

    - -
    -
    - - - - -
    #define RCC_AHB1ENR_OTGHSULPIEN   RCC_AHB1ENR_OTGHSULPIEN_Msk
    -
    - -
    -
    - -

    ◆ RCC_AHB2_SUPPORT

    - -
    -
    - - - - -
    #define RCC_AHB2_SUPPORT
    -
    -

    AHB2 Bus is supported

    - -
    -
    - -

    ◆ RCC_AHB2ENR_DCMIEN_Pos

    - -
    -
    - - - - -
    #define RCC_AHB2ENR_DCMIEN_Pos   (0U)
    -
    - -
    -
    - -

    ◆ RCC_AHB2ENR_DCMIEN_Msk

    - -
    -
    - - - - -
    #define RCC_AHB2ENR_DCMIEN_Msk   (0x1UL << RCC_AHB2ENR_DCMIEN_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ RCC_AHB2ENR_DCMIEN

    - -
    -
    - - - - -
    #define RCC_AHB2ENR_DCMIEN   RCC_AHB2ENR_DCMIEN_Msk
    -
    - -
    -
    - -

    ◆ RCC_AHB2ENR_RNGEN_Pos

    - -
    -
    - - - - -
    #define RCC_AHB2ENR_RNGEN_Pos   (6U)
    -
    - -
    -
    - -

    ◆ RCC_AHB2ENR_RNGEN_Msk

    - -
    -
    - - - - -
    #define RCC_AHB2ENR_RNGEN_Msk   (0x1UL << RCC_AHB2ENR_RNGEN_Pos)
    -
    -

    0x00000040

    - -
    -
    - -

    ◆ RCC_AHB2ENR_RNGEN

    - -
    -
    - - - - -
    #define RCC_AHB2ENR_RNGEN   RCC_AHB2ENR_RNGEN_Msk
    -
    - -
    -
    - -

    ◆ RCC_AHB2ENR_OTGFSEN_Pos

    - -
    -
    - - - - -
    #define RCC_AHB2ENR_OTGFSEN_Pos   (7U)
    -
    - -
    -
    - -

    ◆ RCC_AHB2ENR_OTGFSEN_Msk

    - -
    -
    - - - - -
    #define RCC_AHB2ENR_OTGFSEN_Msk   (0x1UL << RCC_AHB2ENR_OTGFSEN_Pos)
    -
    -

    0x00000080

    - -
    -
    - -

    ◆ RCC_AHB2ENR_OTGFSEN

    - -
    -
    - - - - -
    #define RCC_AHB2ENR_OTGFSEN   RCC_AHB2ENR_OTGFSEN_Msk
    -
    - -
    -
    - -

    ◆ RCC_AHB3_SUPPORT

    - -
    -
    - - - - -
    #define RCC_AHB3_SUPPORT
    -
    -

    AHB3 Bus is supported

    - -
    -
    - -

    ◆ RCC_AHB3ENR_FSMCEN_Pos

    - -
    -
    - - - - -
    #define RCC_AHB3ENR_FSMCEN_Pos   (0U)
    -
    - -
    -
    - -

    ◆ RCC_AHB3ENR_FSMCEN_Msk

    - -
    -
    - - - - -
    #define RCC_AHB3ENR_FSMCEN_Msk   (0x1UL << RCC_AHB3ENR_FSMCEN_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ RCC_AHB3ENR_FSMCEN

    - -
    -
    - - - - -
    #define RCC_AHB3ENR_FSMCEN   RCC_AHB3ENR_FSMCEN_Msk
    -
    - -
    -
    - -

    ◆ RCC_APB1ENR_TIM2EN_Pos

    - -
    -
    - - - - -
    #define RCC_APB1ENR_TIM2EN_Pos   (0U)
    -
    - -
    -
    - -

    ◆ RCC_APB1ENR_TIM2EN_Msk

    - -
    -
    - - - - -
    #define RCC_APB1ENR_TIM2EN_Msk   (0x1UL << RCC_APB1ENR_TIM2EN_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ RCC_APB1ENR_TIM2EN

    - -
    -
    - - - - -
    #define RCC_APB1ENR_TIM2EN   RCC_APB1ENR_TIM2EN_Msk
    -
    - -
    -
    - -

    ◆ RCC_APB1ENR_TIM3EN_Pos

    - -
    -
    - - - - -
    #define RCC_APB1ENR_TIM3EN_Pos   (1U)
    -
    - -
    -
    - -

    ◆ RCC_APB1ENR_TIM3EN_Msk

    - -
    -
    - - - - -
    #define RCC_APB1ENR_TIM3EN_Msk   (0x1UL << RCC_APB1ENR_TIM3EN_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ RCC_APB1ENR_TIM3EN

    - -
    -
    - - - - -
    #define RCC_APB1ENR_TIM3EN   RCC_APB1ENR_TIM3EN_Msk
    -
    - -
    -
    - -

    ◆ RCC_APB1ENR_TIM4EN_Pos

    - -
    -
    - - - - -
    #define RCC_APB1ENR_TIM4EN_Pos   (2U)
    -
    - -
    -
    - -

    ◆ RCC_APB1ENR_TIM4EN_Msk

    - -
    -
    - - - - -
    #define RCC_APB1ENR_TIM4EN_Msk   (0x1UL << RCC_APB1ENR_TIM4EN_Pos)
    -
    -

    0x00000004

    - -
    -
    - -

    ◆ RCC_APB1ENR_TIM4EN

    - -
    -
    - - - - -
    #define RCC_APB1ENR_TIM4EN   RCC_APB1ENR_TIM4EN_Msk
    -
    - -
    -
    - -

    ◆ RCC_APB1ENR_TIM5EN_Pos

    - -
    -
    - - - - -
    #define RCC_APB1ENR_TIM5EN_Pos   (3U)
    -
    - -
    -
    - -

    ◆ RCC_APB1ENR_TIM5EN_Msk

    - -
    -
    - - - - -
    #define RCC_APB1ENR_TIM5EN_Msk   (0x1UL << RCC_APB1ENR_TIM5EN_Pos)
    -
    -

    0x00000008

    - -
    -
    - -

    ◆ RCC_APB1ENR_TIM5EN

    - -
    -
    - - - - -
    #define RCC_APB1ENR_TIM5EN   RCC_APB1ENR_TIM5EN_Msk
    -
    - -
    -
    - -

    ◆ RCC_APB1ENR_TIM6EN_Pos

    - -
    -
    - - - - -
    #define RCC_APB1ENR_TIM6EN_Pos   (4U)
    -
    - -
    -
    - -

    ◆ RCC_APB1ENR_TIM6EN_Msk

    - -
    -
    - - - - -
    #define RCC_APB1ENR_TIM6EN_Msk   (0x1UL << RCC_APB1ENR_TIM6EN_Pos)
    -
    -

    0x00000010

    - -
    -
    - -

    ◆ RCC_APB1ENR_TIM6EN

    - -
    -
    - - - - -
    #define RCC_APB1ENR_TIM6EN   RCC_APB1ENR_TIM6EN_Msk
    -
    - -
    -
    - -

    ◆ RCC_APB1ENR_TIM7EN_Pos

    - -
    -
    - - - - -
    #define RCC_APB1ENR_TIM7EN_Pos   (5U)
    -
    - -
    -
    - -

    ◆ RCC_APB1ENR_TIM7EN_Msk

    - -
    -
    - - - - -
    #define RCC_APB1ENR_TIM7EN_Msk   (0x1UL << RCC_APB1ENR_TIM7EN_Pos)
    -
    -

    0x00000020

    - -
    -
    - -

    ◆ RCC_APB1ENR_TIM7EN

    - -
    -
    - - - - -
    #define RCC_APB1ENR_TIM7EN   RCC_APB1ENR_TIM7EN_Msk
    -
    - -
    -
    - -

    ◆ RCC_APB1ENR_TIM12EN_Pos

    - -
    -
    - - - - -
    #define RCC_APB1ENR_TIM12EN_Pos   (6U)
    -
    - -
    -
    - -

    ◆ RCC_APB1ENR_TIM12EN_Msk

    - -
    -
    - - - - -
    #define RCC_APB1ENR_TIM12EN_Msk   (0x1UL << RCC_APB1ENR_TIM12EN_Pos)
    -
    -

    0x00000040

    - -
    -
    - -

    ◆ RCC_APB1ENR_TIM12EN

    - -
    -
    - - - - -
    #define RCC_APB1ENR_TIM12EN   RCC_APB1ENR_TIM12EN_Msk
    -
    - -
    -
    - -

    ◆ RCC_APB1ENR_TIM13EN_Pos

    - -
    -
    - - - - -
    #define RCC_APB1ENR_TIM13EN_Pos   (7U)
    -
    - -
    -
    - -

    ◆ RCC_APB1ENR_TIM13EN_Msk

    - -
    -
    - - - - -
    #define RCC_APB1ENR_TIM13EN_Msk   (0x1UL << RCC_APB1ENR_TIM13EN_Pos)
    -
    -

    0x00000080

    - -
    -
    - -

    ◆ RCC_APB1ENR_TIM13EN

    - -
    -
    - - - - -
    #define RCC_APB1ENR_TIM13EN   RCC_APB1ENR_TIM13EN_Msk
    -
    - -
    -
    - -

    ◆ RCC_APB1ENR_TIM14EN_Pos

    - -
    -
    - - - - -
    #define RCC_APB1ENR_TIM14EN_Pos   (8U)
    -
    - -
    -
    - -

    ◆ RCC_APB1ENR_TIM14EN_Msk

    - -
    -
    - - - - -
    #define RCC_APB1ENR_TIM14EN_Msk   (0x1UL << RCC_APB1ENR_TIM14EN_Pos)
    -
    -

    0x00000100

    - -
    -
    - -

    ◆ RCC_APB1ENR_TIM14EN

    - -
    -
    - - - - -
    #define RCC_APB1ENR_TIM14EN   RCC_APB1ENR_TIM14EN_Msk
    -
    - -
    -
    - -

    ◆ RCC_APB1ENR_WWDGEN_Pos

    - -
    -
    - - - - -
    #define RCC_APB1ENR_WWDGEN_Pos   (11U)
    -
    - -
    -
    - -

    ◆ RCC_APB1ENR_WWDGEN_Msk

    - -
    -
    - - - - -
    #define RCC_APB1ENR_WWDGEN_Msk   (0x1UL << RCC_APB1ENR_WWDGEN_Pos)
    -
    -

    0x00000800

    - -
    -
    - -

    ◆ RCC_APB1ENR_WWDGEN

    - -
    -
    - - - - -
    #define RCC_APB1ENR_WWDGEN   RCC_APB1ENR_WWDGEN_Msk
    -
    - -
    -
    - -

    ◆ RCC_APB1ENR_SPI2EN_Pos

    - -
    -
    - - - - -
    #define RCC_APB1ENR_SPI2EN_Pos   (14U)
    -
    - -
    -
    - -

    ◆ RCC_APB1ENR_SPI2EN_Msk

    - -
    -
    - - - - -
    #define RCC_APB1ENR_SPI2EN_Msk   (0x1UL << RCC_APB1ENR_SPI2EN_Pos)
    -
    -

    0x00004000

    - -
    -
    - -

    ◆ RCC_APB1ENR_SPI2EN

    - -
    -
    - - - - -
    #define RCC_APB1ENR_SPI2EN   RCC_APB1ENR_SPI2EN_Msk
    -
    - -
    -
    - -

    ◆ RCC_APB1ENR_SPI3EN_Pos

    - -
    -
    - - - - -
    #define RCC_APB1ENR_SPI3EN_Pos   (15U)
    -
    - -
    -
    - -

    ◆ RCC_APB1ENR_SPI3EN_Msk

    - -
    -
    - - - - -
    #define RCC_APB1ENR_SPI3EN_Msk   (0x1UL << RCC_APB1ENR_SPI3EN_Pos)
    -
    -

    0x00008000

    - -
    -
    - -

    ◆ RCC_APB1ENR_SPI3EN

    - -
    -
    - - - - -
    #define RCC_APB1ENR_SPI3EN   RCC_APB1ENR_SPI3EN_Msk
    -
    - -
    -
    - -

    ◆ RCC_APB1ENR_USART2EN_Pos

    - -
    -
    - - - - -
    #define RCC_APB1ENR_USART2EN_Pos   (17U)
    -
    - -
    -
    - -

    ◆ RCC_APB1ENR_USART2EN_Msk

    - -
    -
    - - - - -
    #define RCC_APB1ENR_USART2EN_Msk   (0x1UL << RCC_APB1ENR_USART2EN_Pos)
    -
    -

    0x00020000

    - -
    -
    - -

    ◆ RCC_APB1ENR_USART2EN

    - -
    -
    - - - - -
    #define RCC_APB1ENR_USART2EN   RCC_APB1ENR_USART2EN_Msk
    -
    - -
    -
    - -

    ◆ RCC_APB1ENR_USART3EN_Pos

    - -
    -
    - - - - -
    #define RCC_APB1ENR_USART3EN_Pos   (18U)
    -
    - -
    -
    - -

    ◆ RCC_APB1ENR_USART3EN_Msk

    - -
    -
    - - - - -
    #define RCC_APB1ENR_USART3EN_Msk   (0x1UL << RCC_APB1ENR_USART3EN_Pos)
    -
    -

    0x00040000

    - -
    -
    - -

    ◆ RCC_APB1ENR_USART3EN

    - -
    -
    - - - - -
    #define RCC_APB1ENR_USART3EN   RCC_APB1ENR_USART3EN_Msk
    -
    - -
    -
    - -

    ◆ RCC_APB1ENR_UART4EN_Pos

    - -
    -
    - - - - -
    #define RCC_APB1ENR_UART4EN_Pos   (19U)
    -
    - -
    -
    - -

    ◆ RCC_APB1ENR_UART4EN_Msk

    - -
    -
    - - - - -
    #define RCC_APB1ENR_UART4EN_Msk   (0x1UL << RCC_APB1ENR_UART4EN_Pos)
    -
    -

    0x00080000

    - -
    -
    - -

    ◆ RCC_APB1ENR_UART4EN

    - -
    -
    - - - - -
    #define RCC_APB1ENR_UART4EN   RCC_APB1ENR_UART4EN_Msk
    -
    - -
    -
    - -

    ◆ RCC_APB1ENR_UART5EN_Pos

    - -
    -
    - - - - -
    #define RCC_APB1ENR_UART5EN_Pos   (20U)
    -
    - -
    -
    - -

    ◆ RCC_APB1ENR_UART5EN_Msk

    - -
    -
    - - - - -
    #define RCC_APB1ENR_UART5EN_Msk   (0x1UL << RCC_APB1ENR_UART5EN_Pos)
    -
    -

    0x00100000

    - -
    -
    - -

    ◆ RCC_APB1ENR_UART5EN

    - -
    -
    - - - - -
    #define RCC_APB1ENR_UART5EN   RCC_APB1ENR_UART5EN_Msk
    -
    - -
    -
    - -

    ◆ RCC_APB1ENR_I2C1EN_Pos

    - -
    -
    - - - - -
    #define RCC_APB1ENR_I2C1EN_Pos   (21U)
    -
    - -
    -
    - -

    ◆ RCC_APB1ENR_I2C1EN_Msk

    - -
    -
    - - - - -
    #define RCC_APB1ENR_I2C1EN_Msk   (0x1UL << RCC_APB1ENR_I2C1EN_Pos)
    -
    -

    0x00200000

    - -
    -
    - -

    ◆ RCC_APB1ENR_I2C1EN

    - -
    -
    - - - - -
    #define RCC_APB1ENR_I2C1EN   RCC_APB1ENR_I2C1EN_Msk
    -
    - -
    -
    - -

    ◆ RCC_APB1ENR_I2C2EN_Pos

    - -
    -
    - - - - -
    #define RCC_APB1ENR_I2C2EN_Pos   (22U)
    -
    - -
    -
    - -

    ◆ RCC_APB1ENR_I2C2EN_Msk

    - -
    -
    - - - - -
    #define RCC_APB1ENR_I2C2EN_Msk   (0x1UL << RCC_APB1ENR_I2C2EN_Pos)
    -
    -

    0x00400000

    - -
    -
    - -

    ◆ RCC_APB1ENR_I2C2EN

    - -
    -
    - - - - -
    #define RCC_APB1ENR_I2C2EN   RCC_APB1ENR_I2C2EN_Msk
    -
    - -
    -
    - -

    ◆ RCC_APB1ENR_I2C3EN_Pos

    - -
    -
    - - - - -
    #define RCC_APB1ENR_I2C3EN_Pos   (23U)
    -
    - -
    -
    - -

    ◆ RCC_APB1ENR_I2C3EN_Msk

    - -
    -
    - - - - -
    #define RCC_APB1ENR_I2C3EN_Msk   (0x1UL << RCC_APB1ENR_I2C3EN_Pos)
    -
    -

    0x00800000

    - -
    -
    - -

    ◆ RCC_APB1ENR_I2C3EN

    - -
    -
    - - - - -
    #define RCC_APB1ENR_I2C3EN   RCC_APB1ENR_I2C3EN_Msk
    -
    - -
    -
    - -

    ◆ RCC_APB1ENR_CAN1EN_Pos

    - -
    -
    - - - - -
    #define RCC_APB1ENR_CAN1EN_Pos   (25U)
    -
    - -
    -
    - -

    ◆ RCC_APB1ENR_CAN1EN_Msk

    - -
    -
    - - - - -
    #define RCC_APB1ENR_CAN1EN_Msk   (0x1UL << RCC_APB1ENR_CAN1EN_Pos)
    -
    -

    0x02000000

    - -
    -
    - -

    ◆ RCC_APB1ENR_CAN1EN

    - -
    -
    - - - - -
    #define RCC_APB1ENR_CAN1EN   RCC_APB1ENR_CAN1EN_Msk
    -
    - -
    -
    - -

    ◆ RCC_APB1ENR_CAN2EN_Pos

    - -
    -
    - - - - -
    #define RCC_APB1ENR_CAN2EN_Pos   (26U)
    -
    - -
    -
    - -

    ◆ RCC_APB1ENR_CAN2EN_Msk

    - -
    -
    - - - - -
    #define RCC_APB1ENR_CAN2EN_Msk   (0x1UL << RCC_APB1ENR_CAN2EN_Pos)
    -
    -

    0x04000000

    - -
    -
    - -

    ◆ RCC_APB1ENR_CAN2EN

    - -
    -
    - - - - -
    #define RCC_APB1ENR_CAN2EN   RCC_APB1ENR_CAN2EN_Msk
    -
    - -
    -
    - -

    ◆ RCC_APB1ENR_PWREN_Pos

    - -
    -
    - - - - -
    #define RCC_APB1ENR_PWREN_Pos   (28U)
    -
    - -
    -
    - -

    ◆ RCC_APB1ENR_PWREN_Msk

    - -
    -
    - - - - -
    #define RCC_APB1ENR_PWREN_Msk   (0x1UL << RCC_APB1ENR_PWREN_Pos)
    -
    -

    0x10000000

    - -
    -
    - -

    ◆ RCC_APB1ENR_PWREN

    - -
    -
    - - - - -
    #define RCC_APB1ENR_PWREN   RCC_APB1ENR_PWREN_Msk
    -
    - -
    -
    - -

    ◆ RCC_APB1ENR_DACEN_Pos

    - -
    -
    - - - - -
    #define RCC_APB1ENR_DACEN_Pos   (29U)
    -
    - -
    -
    - -

    ◆ RCC_APB1ENR_DACEN_Msk

    - -
    -
    - - - - -
    #define RCC_APB1ENR_DACEN_Msk   (0x1UL << RCC_APB1ENR_DACEN_Pos)
    -
    -

    0x20000000

    - -
    -
    - -

    ◆ RCC_APB1ENR_DACEN

    - -
    -
    - - - - -
    #define RCC_APB1ENR_DACEN   RCC_APB1ENR_DACEN_Msk
    -
    - -
    -
    - -

    ◆ RCC_APB2ENR_TIM1EN_Pos

    - -
    -
    - - - - -
    #define RCC_APB2ENR_TIM1EN_Pos   (0U)
    -
    - -
    -
    - -

    ◆ RCC_APB2ENR_TIM1EN_Msk

    - -
    -
    - - - - -
    #define RCC_APB2ENR_TIM1EN_Msk   (0x1UL << RCC_APB2ENR_TIM1EN_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ RCC_APB2ENR_TIM1EN

    - -
    -
    - - - - -
    #define RCC_APB2ENR_TIM1EN   RCC_APB2ENR_TIM1EN_Msk
    -
    - -
    -
    - -

    ◆ RCC_APB2ENR_TIM8EN_Pos

    - -
    -
    - - - - -
    #define RCC_APB2ENR_TIM8EN_Pos   (1U)
    -
    - -
    -
    - -

    ◆ RCC_APB2ENR_TIM8EN_Msk

    - -
    -
    - - - - -
    #define RCC_APB2ENR_TIM8EN_Msk   (0x1UL << RCC_APB2ENR_TIM8EN_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ RCC_APB2ENR_TIM8EN

    - -
    -
    - - - - -
    #define RCC_APB2ENR_TIM8EN   RCC_APB2ENR_TIM8EN_Msk
    -
    - -
    -
    - -

    ◆ RCC_APB2ENR_USART1EN_Pos

    - -
    -
    - - - - -
    #define RCC_APB2ENR_USART1EN_Pos   (4U)
    -
    - -
    -
    - -

    ◆ RCC_APB2ENR_USART1EN_Msk

    - -
    -
    - - - - -
    #define RCC_APB2ENR_USART1EN_Msk   (0x1UL << RCC_APB2ENR_USART1EN_Pos)
    -
    -

    0x00000010

    - -
    -
    - -

    ◆ RCC_APB2ENR_USART1EN

    - -
    -
    - - - - -
    #define RCC_APB2ENR_USART1EN   RCC_APB2ENR_USART1EN_Msk
    -
    - -
    -
    - -

    ◆ RCC_APB2ENR_USART6EN_Pos

    - -
    -
    - - - - -
    #define RCC_APB2ENR_USART6EN_Pos   (5U)
    -
    - -
    -
    - -

    ◆ RCC_APB2ENR_USART6EN_Msk

    - -
    -
    - - - - -
    #define RCC_APB2ENR_USART6EN_Msk   (0x1UL << RCC_APB2ENR_USART6EN_Pos)
    -
    -

    0x00000020

    - -
    -
    - -

    ◆ RCC_APB2ENR_USART6EN

    - -
    -
    - - - - -
    #define RCC_APB2ENR_USART6EN   RCC_APB2ENR_USART6EN_Msk
    -
    - -
    -
    - -

    ◆ RCC_APB2ENR_ADC1EN_Pos

    - -
    -
    - - - - -
    #define RCC_APB2ENR_ADC1EN_Pos   (8U)
    -
    - -
    -
    - -

    ◆ RCC_APB2ENR_ADC1EN_Msk

    - -
    -
    - - - - -
    #define RCC_APB2ENR_ADC1EN_Msk   (0x1UL << RCC_APB2ENR_ADC1EN_Pos)
    -
    -

    0x00000100

    - -
    -
    - -

    ◆ RCC_APB2ENR_ADC1EN

    - -
    -
    - - - - -
    #define RCC_APB2ENR_ADC1EN   RCC_APB2ENR_ADC1EN_Msk
    -
    - -
    -
    - -

    ◆ RCC_APB2ENR_ADC2EN_Pos

    - -
    -
    - - - - -
    #define RCC_APB2ENR_ADC2EN_Pos   (9U)
    -
    - -
    -
    - -

    ◆ RCC_APB2ENR_ADC2EN_Msk

    - -
    -
    - - - - -
    #define RCC_APB2ENR_ADC2EN_Msk   (0x1UL << RCC_APB2ENR_ADC2EN_Pos)
    -
    -

    0x00000200

    - -
    -
    - -

    ◆ RCC_APB2ENR_ADC2EN

    - -
    -
    - - - - -
    #define RCC_APB2ENR_ADC2EN   RCC_APB2ENR_ADC2EN_Msk
    -
    - -
    -
    - -

    ◆ RCC_APB2ENR_ADC3EN_Pos

    - -
    -
    - - - - -
    #define RCC_APB2ENR_ADC3EN_Pos   (10U)
    -
    - -
    -
    - -

    ◆ RCC_APB2ENR_ADC3EN_Msk

    - -
    -
    - - - - -
    #define RCC_APB2ENR_ADC3EN_Msk   (0x1UL << RCC_APB2ENR_ADC3EN_Pos)
    -
    -

    0x00000400

    - -
    -
    - -

    ◆ RCC_APB2ENR_ADC3EN

    - -
    -
    - - - - -
    #define RCC_APB2ENR_ADC3EN   RCC_APB2ENR_ADC3EN_Msk
    -
    - -
    -
    - -

    ◆ RCC_APB2ENR_SDIOEN_Pos

    - -
    -
    - - - - -
    #define RCC_APB2ENR_SDIOEN_Pos   (11U)
    -
    - -
    -
    - -

    ◆ RCC_APB2ENR_SDIOEN_Msk

    - -
    -
    - - - - -
    #define RCC_APB2ENR_SDIOEN_Msk   (0x1UL << RCC_APB2ENR_SDIOEN_Pos)
    -
    -

    0x00000800

    - -
    -
    - -

    ◆ RCC_APB2ENR_SDIOEN

    - -
    -
    - - - - -
    #define RCC_APB2ENR_SDIOEN   RCC_APB2ENR_SDIOEN_Msk
    -
    - -
    -
    - -

    ◆ RCC_APB2ENR_SPI1EN_Pos

    - -
    -
    - - - - -
    #define RCC_APB2ENR_SPI1EN_Pos   (12U)
    -
    - -
    -
    - -

    ◆ RCC_APB2ENR_SPI1EN_Msk

    - -
    -
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    #define RCC_APB2ENR_SPI1EN_Msk   (0x1UL << RCC_APB2ENR_SPI1EN_Pos)
    -
    -

    0x00001000

    - -
    -
    - -

    ◆ RCC_APB2ENR_SPI1EN

    - -
    -
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    #define RCC_APB2ENR_SPI1EN   RCC_APB2ENR_SPI1EN_Msk
    -
    - -
    -
    - -

    ◆ RCC_APB2ENR_SYSCFGEN_Pos

    - -
    -
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    #define RCC_APB2ENR_SYSCFGEN_Pos   (14U)
    -
    - -
    -
    - -

    ◆ RCC_APB2ENR_SYSCFGEN_Msk

    - -
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    #define RCC_APB2ENR_SYSCFGEN_Msk   (0x1UL << RCC_APB2ENR_SYSCFGEN_Pos)
    -
    -

    0x00004000

    - -
    -
    - -

    ◆ RCC_APB2ENR_SYSCFGEN

    - -
    -
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    #define RCC_APB2ENR_SYSCFGEN   RCC_APB2ENR_SYSCFGEN_Msk
    -
    - -
    -
    - -

    ◆ RCC_APB2ENR_TIM9EN_Pos

    - -
    -
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    #define RCC_APB2ENR_TIM9EN_Pos   (16U)
    -
    - -
    -
    - -

    ◆ RCC_APB2ENR_TIM9EN_Msk

    - -
    -
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    #define RCC_APB2ENR_TIM9EN_Msk   (0x1UL << RCC_APB2ENR_TIM9EN_Pos)
    -
    -

    0x00010000

    - -
    -
    - -

    ◆ RCC_APB2ENR_TIM9EN

    - -
    -
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    #define RCC_APB2ENR_TIM9EN   RCC_APB2ENR_TIM9EN_Msk
    -
    - -
    -
    - -

    ◆ RCC_APB2ENR_TIM10EN_Pos

    - -
    -
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    #define RCC_APB2ENR_TIM10EN_Pos   (17U)
    -
    - -
    -
    - -

    ◆ RCC_APB2ENR_TIM10EN_Msk

    - -
    -
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    #define RCC_APB2ENR_TIM10EN_Msk   (0x1UL << RCC_APB2ENR_TIM10EN_Pos)
    -
    -

    0x00020000

    - -
    -
    - -

    ◆ RCC_APB2ENR_TIM10EN

    - -
    -
    - - - - -
    #define RCC_APB2ENR_TIM10EN   RCC_APB2ENR_TIM10EN_Msk
    -
    - -
    -
    - -

    ◆ RCC_APB2ENR_TIM11EN_Pos

    - -
    -
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    #define RCC_APB2ENR_TIM11EN_Pos   (18U)
    -
    - -
    -
    - -

    ◆ RCC_APB2ENR_TIM11EN_Msk

    - -
    -
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    #define RCC_APB2ENR_TIM11EN_Msk   (0x1UL << RCC_APB2ENR_TIM11EN_Pos)
    -
    -

    0x00040000

    - -
    -
    - -

    ◆ RCC_APB2ENR_TIM11EN

    - -
    -
    - - - - -
    #define RCC_APB2ENR_TIM11EN   RCC_APB2ENR_TIM11EN_Msk
    -
    - -
    -
    - -

    ◆ RCC_AHB1LPENR_GPIOALPEN_Pos

    - -
    -
    - - - - -
    #define RCC_AHB1LPENR_GPIOALPEN_Pos   (0U)
    -
    - -
    -
    - -

    ◆ RCC_AHB1LPENR_GPIOALPEN_Msk

    - -
    -
    - - - - -
    #define RCC_AHB1LPENR_GPIOALPEN_Msk   (0x1UL << RCC_AHB1LPENR_GPIOALPEN_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ RCC_AHB1LPENR_GPIOALPEN

    - -
    -
    - - - - -
    #define RCC_AHB1LPENR_GPIOALPEN   RCC_AHB1LPENR_GPIOALPEN_Msk
    -
    - -
    -
    - -

    ◆ RCC_AHB1LPENR_GPIOBLPEN_Pos

    - -
    -
    - - - - -
    #define RCC_AHB1LPENR_GPIOBLPEN_Pos   (1U)
    -
    - -
    -
    - -

    ◆ RCC_AHB1LPENR_GPIOBLPEN_Msk

    - -
    -
    - - - - -
    #define RCC_AHB1LPENR_GPIOBLPEN_Msk   (0x1UL << RCC_AHB1LPENR_GPIOBLPEN_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ RCC_AHB1LPENR_GPIOBLPEN

    - -
    -
    - - - - -
    #define RCC_AHB1LPENR_GPIOBLPEN   RCC_AHB1LPENR_GPIOBLPEN_Msk
    -
    - -
    -
    - -

    ◆ RCC_AHB1LPENR_GPIOCLPEN_Pos

    - -
    -
    - - - - -
    #define RCC_AHB1LPENR_GPIOCLPEN_Pos   (2U)
    -
    - -
    -
    - -

    ◆ RCC_AHB1LPENR_GPIOCLPEN_Msk

    - -
    -
    - - - - -
    #define RCC_AHB1LPENR_GPIOCLPEN_Msk   (0x1UL << RCC_AHB1LPENR_GPIOCLPEN_Pos)
    -
    -

    0x00000004

    - -
    -
    - -

    ◆ RCC_AHB1LPENR_GPIOCLPEN

    - -
    -
    - - - - -
    #define RCC_AHB1LPENR_GPIOCLPEN   RCC_AHB1LPENR_GPIOCLPEN_Msk
    -
    - -
    -
    - -

    ◆ RCC_AHB1LPENR_GPIODLPEN_Pos

    - -
    -
    - - - - -
    #define RCC_AHB1LPENR_GPIODLPEN_Pos   (3U)
    -
    - -
    -
    - -

    ◆ RCC_AHB1LPENR_GPIODLPEN_Msk

    - -
    -
    - - - - -
    #define RCC_AHB1LPENR_GPIODLPEN_Msk   (0x1UL << RCC_AHB1LPENR_GPIODLPEN_Pos)
    -
    -

    0x00000008

    - -
    -
    - -

    ◆ RCC_AHB1LPENR_GPIODLPEN

    - -
    -
    - - - - -
    #define RCC_AHB1LPENR_GPIODLPEN   RCC_AHB1LPENR_GPIODLPEN_Msk
    -
    - -
    -
    - -

    ◆ RCC_AHB1LPENR_GPIOELPEN_Pos

    - -
    -
    - - - - -
    #define RCC_AHB1LPENR_GPIOELPEN_Pos   (4U)
    -
    - -
    -
    - -

    ◆ RCC_AHB1LPENR_GPIOELPEN_Msk

    - -
    -
    - - - - -
    #define RCC_AHB1LPENR_GPIOELPEN_Msk   (0x1UL << RCC_AHB1LPENR_GPIOELPEN_Pos)
    -
    -

    0x00000010

    - -
    -
    - -

    ◆ RCC_AHB1LPENR_GPIOELPEN

    - -
    -
    - - - - -
    #define RCC_AHB1LPENR_GPIOELPEN   RCC_AHB1LPENR_GPIOELPEN_Msk
    -
    - -
    -
    - -

    ◆ RCC_AHB1LPENR_GPIOFLPEN_Pos

    - -
    -
    - - - - -
    #define RCC_AHB1LPENR_GPIOFLPEN_Pos   (5U)
    -
    - -
    -
    - -

    ◆ RCC_AHB1LPENR_GPIOFLPEN_Msk

    - -
    -
    - - - - -
    #define RCC_AHB1LPENR_GPIOFLPEN_Msk   (0x1UL << RCC_AHB1LPENR_GPIOFLPEN_Pos)
    -
    -

    0x00000020

    - -
    -
    - -

    ◆ RCC_AHB1LPENR_GPIOFLPEN

    - -
    -
    - - - - -
    #define RCC_AHB1LPENR_GPIOFLPEN   RCC_AHB1LPENR_GPIOFLPEN_Msk
    -
    - -
    -
    - -

    ◆ RCC_AHB1LPENR_GPIOGLPEN_Pos

    - -
    -
    - - - - -
    #define RCC_AHB1LPENR_GPIOGLPEN_Pos   (6U)
    -
    - -
    -
    - -

    ◆ RCC_AHB1LPENR_GPIOGLPEN_Msk

    - -
    -
    - - - - -
    #define RCC_AHB1LPENR_GPIOGLPEN_Msk   (0x1UL << RCC_AHB1LPENR_GPIOGLPEN_Pos)
    -
    -

    0x00000040

    - -
    -
    - -

    ◆ RCC_AHB1LPENR_GPIOGLPEN

    - -
    -
    - - - - -
    #define RCC_AHB1LPENR_GPIOGLPEN   RCC_AHB1LPENR_GPIOGLPEN_Msk
    -
    - -
    -
    - -

    ◆ RCC_AHB1LPENR_GPIOHLPEN_Pos

    - -
    -
    - - - - -
    #define RCC_AHB1LPENR_GPIOHLPEN_Pos   (7U)
    -
    - -
    -
    - -

    ◆ RCC_AHB1LPENR_GPIOHLPEN_Msk

    - -
    -
    - - - - -
    #define RCC_AHB1LPENR_GPIOHLPEN_Msk   (0x1UL << RCC_AHB1LPENR_GPIOHLPEN_Pos)
    -
    -

    0x00000080

    - -
    -
    - -

    ◆ RCC_AHB1LPENR_GPIOHLPEN

    - -
    -
    - - - - -
    #define RCC_AHB1LPENR_GPIOHLPEN   RCC_AHB1LPENR_GPIOHLPEN_Msk
    -
    - -
    -
    - -

    ◆ RCC_AHB1LPENR_GPIOILPEN_Pos

    - -
    -
    - - - - -
    #define RCC_AHB1LPENR_GPIOILPEN_Pos   (8U)
    -
    - -
    -
    - -

    ◆ RCC_AHB1LPENR_GPIOILPEN_Msk

    - -
    -
    - - - - -
    #define RCC_AHB1LPENR_GPIOILPEN_Msk   (0x1UL << RCC_AHB1LPENR_GPIOILPEN_Pos)
    -
    -

    0x00000100

    - -
    -
    - -

    ◆ RCC_AHB1LPENR_GPIOILPEN

    - -
    -
    - - - - -
    #define RCC_AHB1LPENR_GPIOILPEN   RCC_AHB1LPENR_GPIOILPEN_Msk
    -
    - -
    -
    - -

    ◆ RCC_AHB1LPENR_CRCLPEN_Pos

    - -
    -
    - - - - -
    #define RCC_AHB1LPENR_CRCLPEN_Pos   (12U)
    -
    - -
    -
    - -

    ◆ RCC_AHB1LPENR_CRCLPEN_Msk

    - -
    -
    - - - - -
    #define RCC_AHB1LPENR_CRCLPEN_Msk   (0x1UL << RCC_AHB1LPENR_CRCLPEN_Pos)
    -
    -

    0x00001000

    - -
    -
    - -

    ◆ RCC_AHB1LPENR_CRCLPEN

    - -
    -
    - - - - -
    #define RCC_AHB1LPENR_CRCLPEN   RCC_AHB1LPENR_CRCLPEN_Msk
    -
    - -
    -
    - -

    ◆ RCC_AHB1LPENR_FLITFLPEN_Pos

    - -
    -
    - - - - -
    #define RCC_AHB1LPENR_FLITFLPEN_Pos   (15U)
    -
    - -
    -
    - -

    ◆ RCC_AHB1LPENR_FLITFLPEN_Msk

    - -
    -
    - - - - -
    #define RCC_AHB1LPENR_FLITFLPEN_Msk   (0x1UL << RCC_AHB1LPENR_FLITFLPEN_Pos)
    -
    -

    0x00008000

    - -
    -
    - -

    ◆ RCC_AHB1LPENR_FLITFLPEN

    - -
    -
    - - - - -
    #define RCC_AHB1LPENR_FLITFLPEN   RCC_AHB1LPENR_FLITFLPEN_Msk
    -
    - -
    -
    - -

    ◆ RCC_AHB1LPENR_SRAM1LPEN_Pos

    - -
    -
    - - - - -
    #define RCC_AHB1LPENR_SRAM1LPEN_Pos   (16U)
    -
    - -
    -
    - -

    ◆ RCC_AHB1LPENR_SRAM1LPEN_Msk

    - -
    -
    - - - - -
    #define RCC_AHB1LPENR_SRAM1LPEN_Msk   (0x1UL << RCC_AHB1LPENR_SRAM1LPEN_Pos)
    -
    -

    0x00010000

    - -
    -
    - -

    ◆ RCC_AHB1LPENR_SRAM1LPEN

    - -
    -
    - - - - -
    #define RCC_AHB1LPENR_SRAM1LPEN   RCC_AHB1LPENR_SRAM1LPEN_Msk
    -
    - -
    -
    - -

    ◆ RCC_AHB1LPENR_SRAM2LPEN_Pos

    - -
    -
    - - - - -
    #define RCC_AHB1LPENR_SRAM2LPEN_Pos   (17U)
    -
    - -
    -
    - -

    ◆ RCC_AHB1LPENR_SRAM2LPEN_Msk

    - -
    -
    - - - - -
    #define RCC_AHB1LPENR_SRAM2LPEN_Msk   (0x1UL << RCC_AHB1LPENR_SRAM2LPEN_Pos)
    -
    -

    0x00020000

    - -
    -
    - -

    ◆ RCC_AHB1LPENR_SRAM2LPEN

    - -
    -
    - - - - -
    #define RCC_AHB1LPENR_SRAM2LPEN   RCC_AHB1LPENR_SRAM2LPEN_Msk
    -
    - -
    -
    - -

    ◆ RCC_AHB1LPENR_BKPSRAMLPEN_Pos

    - -
    -
    - - - - -
    #define RCC_AHB1LPENR_BKPSRAMLPEN_Pos   (18U)
    -
    - -
    -
    - -

    ◆ RCC_AHB1LPENR_BKPSRAMLPEN_Msk

    - -
    -
    - - - - -
    #define RCC_AHB1LPENR_BKPSRAMLPEN_Msk   (0x1UL << RCC_AHB1LPENR_BKPSRAMLPEN_Pos)
    -
    -

    0x00040000

    - -
    -
    - -

    ◆ RCC_AHB1LPENR_BKPSRAMLPEN

    - -
    -
    - - - - -
    #define RCC_AHB1LPENR_BKPSRAMLPEN   RCC_AHB1LPENR_BKPSRAMLPEN_Msk
    -
    - -
    -
    - -

    ◆ RCC_AHB1LPENR_DMA1LPEN_Pos

    - -
    -
    - - - - -
    #define RCC_AHB1LPENR_DMA1LPEN_Pos   (21U)
    -
    - -
    -
    - -

    ◆ RCC_AHB1LPENR_DMA1LPEN_Msk

    - -
    -
    - - - - -
    #define RCC_AHB1LPENR_DMA1LPEN_Msk   (0x1UL << RCC_AHB1LPENR_DMA1LPEN_Pos)
    -
    -

    0x00200000

    - -
    -
    - -

    ◆ RCC_AHB1LPENR_DMA1LPEN

    - -
    -
    - - - - -
    #define RCC_AHB1LPENR_DMA1LPEN   RCC_AHB1LPENR_DMA1LPEN_Msk
    -
    - -
    -
    - -

    ◆ RCC_AHB1LPENR_DMA2LPEN_Pos

    - -
    -
    - - - - -
    #define RCC_AHB1LPENR_DMA2LPEN_Pos   (22U)
    -
    - -
    -
    - -

    ◆ RCC_AHB1LPENR_DMA2LPEN_Msk

    - -
    -
    - - - - -
    #define RCC_AHB1LPENR_DMA2LPEN_Msk   (0x1UL << RCC_AHB1LPENR_DMA2LPEN_Pos)
    -
    -

    0x00400000

    - -
    -
    - -

    ◆ RCC_AHB1LPENR_DMA2LPEN

    - -
    -
    - - - - -
    #define RCC_AHB1LPENR_DMA2LPEN   RCC_AHB1LPENR_DMA2LPEN_Msk
    -
    - -
    -
    - -

    ◆ RCC_AHB1LPENR_ETHMACLPEN_Pos

    - -
    -
    - - - - -
    #define RCC_AHB1LPENR_ETHMACLPEN_Pos   (25U)
    -
    - -
    -
    - -

    ◆ RCC_AHB1LPENR_ETHMACLPEN_Msk

    - -
    -
    - - - - -
    #define RCC_AHB1LPENR_ETHMACLPEN_Msk   (0x1UL << RCC_AHB1LPENR_ETHMACLPEN_Pos)
    -
    -

    0x02000000

    - -
    -
    - -

    ◆ RCC_AHB1LPENR_ETHMACLPEN

    - -
    -
    - - - - -
    #define RCC_AHB1LPENR_ETHMACLPEN   RCC_AHB1LPENR_ETHMACLPEN_Msk
    -
    - -
    -
    - -

    ◆ RCC_AHB1LPENR_ETHMACTXLPEN_Pos

    - -
    -
    - - - - -
    #define RCC_AHB1LPENR_ETHMACTXLPEN_Pos   (26U)
    -
    - -
    -
    - -

    ◆ RCC_AHB1LPENR_ETHMACTXLPEN_Msk

    - -
    -
    - - - - -
    #define RCC_AHB1LPENR_ETHMACTXLPEN_Msk   (0x1UL << RCC_AHB1LPENR_ETHMACTXLPEN_Pos)
    -
    -

    0x04000000

    - -
    -
    - -

    ◆ RCC_AHB1LPENR_ETHMACTXLPEN

    - -
    -
    - - - - -
    #define RCC_AHB1LPENR_ETHMACTXLPEN   RCC_AHB1LPENR_ETHMACTXLPEN_Msk
    -
    - -
    -
    - -

    ◆ RCC_AHB1LPENR_ETHMACRXLPEN_Pos

    - -
    -
    - - - - -
    #define RCC_AHB1LPENR_ETHMACRXLPEN_Pos   (27U)
    -
    - -
    -
    - -

    ◆ RCC_AHB1LPENR_ETHMACRXLPEN_Msk

    - -
    -
    - - - - -
    #define RCC_AHB1LPENR_ETHMACRXLPEN_Msk   (0x1UL << RCC_AHB1LPENR_ETHMACRXLPEN_Pos)
    -
    -

    0x08000000

    - -
    -
    - -

    ◆ RCC_AHB1LPENR_ETHMACRXLPEN

    - -
    -
    - - - - -
    #define RCC_AHB1LPENR_ETHMACRXLPEN   RCC_AHB1LPENR_ETHMACRXLPEN_Msk
    -
    - -
    -
    - -

    ◆ RCC_AHB1LPENR_ETHMACPTPLPEN_Pos

    - -
    -
    - - - - -
    #define RCC_AHB1LPENR_ETHMACPTPLPEN_Pos   (28U)
    -
    - -
    -
    - -

    ◆ RCC_AHB1LPENR_ETHMACPTPLPEN_Msk

    - -
    -
    - - - - -
    #define RCC_AHB1LPENR_ETHMACPTPLPEN_Msk   (0x1UL << RCC_AHB1LPENR_ETHMACPTPLPEN_Pos)
    -
    -

    0x10000000

    - -
    -
    - -

    ◆ RCC_AHB1LPENR_ETHMACPTPLPEN

    - -
    -
    - - - - -
    #define RCC_AHB1LPENR_ETHMACPTPLPEN   RCC_AHB1LPENR_ETHMACPTPLPEN_Msk
    -
    - -
    -
    - -

    ◆ RCC_AHB1LPENR_OTGHSLPEN_Pos

    - -
    -
    - - - - -
    #define RCC_AHB1LPENR_OTGHSLPEN_Pos   (29U)
    -
    - -
    -
    - -

    ◆ RCC_AHB1LPENR_OTGHSLPEN_Msk

    - -
    -
    - - - - -
    #define RCC_AHB1LPENR_OTGHSLPEN_Msk   (0x1UL << RCC_AHB1LPENR_OTGHSLPEN_Pos)
    -
    -

    0x20000000

    - -
    -
    - -

    ◆ RCC_AHB1LPENR_OTGHSLPEN

    - -
    -
    - - - - -
    #define RCC_AHB1LPENR_OTGHSLPEN   RCC_AHB1LPENR_OTGHSLPEN_Msk
    -
    - -
    -
    - -

    ◆ RCC_AHB1LPENR_OTGHSULPILPEN_Pos

    - -
    -
    - - - - -
    #define RCC_AHB1LPENR_OTGHSULPILPEN_Pos   (30U)
    -
    - -
    -
    - -

    ◆ RCC_AHB1LPENR_OTGHSULPILPEN_Msk

    - -
    -
    - - - - -
    #define RCC_AHB1LPENR_OTGHSULPILPEN_Msk   (0x1UL << RCC_AHB1LPENR_OTGHSULPILPEN_Pos)
    -
    -

    0x40000000

    - -
    -
    - -

    ◆ RCC_AHB1LPENR_OTGHSULPILPEN

    - -
    -
    - - - - -
    #define RCC_AHB1LPENR_OTGHSULPILPEN   RCC_AHB1LPENR_OTGHSULPILPEN_Msk
    -
    - -
    -
    - -

    ◆ RCC_AHB2LPENR_DCMILPEN_Pos

    - -
    -
    - - - - -
    #define RCC_AHB2LPENR_DCMILPEN_Pos   (0U)
    -
    - -
    -
    - -

    ◆ RCC_AHB2LPENR_DCMILPEN_Msk

    - -
    -
    - - - - -
    #define RCC_AHB2LPENR_DCMILPEN_Msk   (0x1UL << RCC_AHB2LPENR_DCMILPEN_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ RCC_AHB2LPENR_DCMILPEN

    - -
    -
    - - - - -
    #define RCC_AHB2LPENR_DCMILPEN   RCC_AHB2LPENR_DCMILPEN_Msk
    -
    - -
    -
    - -

    ◆ RCC_AHB2LPENR_RNGLPEN_Pos

    - -
    -
    - - - - -
    #define RCC_AHB2LPENR_RNGLPEN_Pos   (6U)
    -
    - -
    -
    - -

    ◆ RCC_AHB2LPENR_RNGLPEN_Msk

    - -
    -
    - - - - -
    #define RCC_AHB2LPENR_RNGLPEN_Msk   (0x1UL << RCC_AHB2LPENR_RNGLPEN_Pos)
    -
    -

    0x00000040

    - -
    -
    - -

    ◆ RCC_AHB2LPENR_RNGLPEN

    - -
    -
    - - - - -
    #define RCC_AHB2LPENR_RNGLPEN   RCC_AHB2LPENR_RNGLPEN_Msk
    -
    - -
    -
    - -

    ◆ RCC_AHB2LPENR_OTGFSLPEN_Pos

    - -
    -
    - - - - -
    #define RCC_AHB2LPENR_OTGFSLPEN_Pos   (7U)
    -
    - -
    -
    - -

    ◆ RCC_AHB2LPENR_OTGFSLPEN_Msk

    - -
    -
    - - - - -
    #define RCC_AHB2LPENR_OTGFSLPEN_Msk   (0x1UL << RCC_AHB2LPENR_OTGFSLPEN_Pos)
    -
    -

    0x00000080

    - -
    -
    - -

    ◆ RCC_AHB2LPENR_OTGFSLPEN

    - -
    -
    - - - - -
    #define RCC_AHB2LPENR_OTGFSLPEN   RCC_AHB2LPENR_OTGFSLPEN_Msk
    -
    - -
    -
    - -

    ◆ RCC_AHB3LPENR_FSMCLPEN_Pos

    - -
    -
    - - - - -
    #define RCC_AHB3LPENR_FSMCLPEN_Pos   (0U)
    -
    - -
    -
    - -

    ◆ RCC_AHB3LPENR_FSMCLPEN_Msk

    - -
    -
    - - - - -
    #define RCC_AHB3LPENR_FSMCLPEN_Msk   (0x1UL << RCC_AHB3LPENR_FSMCLPEN_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ RCC_AHB3LPENR_FSMCLPEN

    - -
    -
    - - - - -
    #define RCC_AHB3LPENR_FSMCLPEN   RCC_AHB3LPENR_FSMCLPEN_Msk
    -
    - -
    -
    - -

    ◆ RCC_APB1LPENR_TIM2LPEN_Pos

    - -
    -
    - - - - -
    #define RCC_APB1LPENR_TIM2LPEN_Pos   (0U)
    -
    - -
    -
    - -

    ◆ RCC_APB1LPENR_TIM2LPEN_Msk

    - -
    -
    - - - - -
    #define RCC_APB1LPENR_TIM2LPEN_Msk   (0x1UL << RCC_APB1LPENR_TIM2LPEN_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ RCC_APB1LPENR_TIM2LPEN

    - -
    -
    - - - - -
    #define RCC_APB1LPENR_TIM2LPEN   RCC_APB1LPENR_TIM2LPEN_Msk
    -
    - -
    -
    - -

    ◆ RCC_APB1LPENR_TIM3LPEN_Pos

    - -
    -
    - - - - -
    #define RCC_APB1LPENR_TIM3LPEN_Pos   (1U)
    -
    - -
    -
    - -

    ◆ RCC_APB1LPENR_TIM3LPEN_Msk

    - -
    -
    - - - - -
    #define RCC_APB1LPENR_TIM3LPEN_Msk   (0x1UL << RCC_APB1LPENR_TIM3LPEN_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ RCC_APB1LPENR_TIM3LPEN

    - -
    -
    - - - - -
    #define RCC_APB1LPENR_TIM3LPEN   RCC_APB1LPENR_TIM3LPEN_Msk
    -
    - -
    -
    - -

    ◆ RCC_APB1LPENR_TIM4LPEN_Pos

    - -
    -
    - - - - -
    #define RCC_APB1LPENR_TIM4LPEN_Pos   (2U)
    -
    - -
    -
    - -

    ◆ RCC_APB1LPENR_TIM4LPEN_Msk

    - -
    -
    - - - - -
    #define RCC_APB1LPENR_TIM4LPEN_Msk   (0x1UL << RCC_APB1LPENR_TIM4LPEN_Pos)
    -
    -

    0x00000004

    - -
    -
    - -

    ◆ RCC_APB1LPENR_TIM4LPEN

    - -
    -
    - - - - -
    #define RCC_APB1LPENR_TIM4LPEN   RCC_APB1LPENR_TIM4LPEN_Msk
    -
    - -
    -
    - -

    ◆ RCC_APB1LPENR_TIM5LPEN_Pos

    - -
    -
    - - - - -
    #define RCC_APB1LPENR_TIM5LPEN_Pos   (3U)
    -
    - -
    -
    - -

    ◆ RCC_APB1LPENR_TIM5LPEN_Msk

    - -
    -
    - - - - -
    #define RCC_APB1LPENR_TIM5LPEN_Msk   (0x1UL << RCC_APB1LPENR_TIM5LPEN_Pos)
    -
    -

    0x00000008

    - -
    -
    - -

    ◆ RCC_APB1LPENR_TIM5LPEN

    - -
    -
    - - - - -
    #define RCC_APB1LPENR_TIM5LPEN   RCC_APB1LPENR_TIM5LPEN_Msk
    -
    - -
    -
    - -

    ◆ RCC_APB1LPENR_TIM6LPEN_Pos

    - -
    -
    - - - - -
    #define RCC_APB1LPENR_TIM6LPEN_Pos   (4U)
    -
    - -
    -
    - -

    ◆ RCC_APB1LPENR_TIM6LPEN_Msk

    - -
    -
    - - - - -
    #define RCC_APB1LPENR_TIM6LPEN_Msk   (0x1UL << RCC_APB1LPENR_TIM6LPEN_Pos)
    -
    -

    0x00000010

    - -
    -
    - -

    ◆ RCC_APB1LPENR_TIM6LPEN

    - -
    -
    - - - - -
    #define RCC_APB1LPENR_TIM6LPEN   RCC_APB1LPENR_TIM6LPEN_Msk
    -
    - -
    -
    - -

    ◆ RCC_APB1LPENR_TIM7LPEN_Pos

    - -
    -
    - - - - -
    #define RCC_APB1LPENR_TIM7LPEN_Pos   (5U)
    -
    - -
    -
    - -

    ◆ RCC_APB1LPENR_TIM7LPEN_Msk

    - -
    -
    - - - - -
    #define RCC_APB1LPENR_TIM7LPEN_Msk   (0x1UL << RCC_APB1LPENR_TIM7LPEN_Pos)
    -
    -

    0x00000020

    - -
    -
    - -

    ◆ RCC_APB1LPENR_TIM7LPEN

    - -
    -
    - - - - -
    #define RCC_APB1LPENR_TIM7LPEN   RCC_APB1LPENR_TIM7LPEN_Msk
    -
    - -
    -
    - -

    ◆ RCC_APB1LPENR_TIM12LPEN_Pos

    - -
    -
    - - - - -
    #define RCC_APB1LPENR_TIM12LPEN_Pos   (6U)
    -
    - -
    -
    - -

    ◆ RCC_APB1LPENR_TIM12LPEN_Msk

    - -
    -
    - - - - -
    #define RCC_APB1LPENR_TIM12LPEN_Msk   (0x1UL << RCC_APB1LPENR_TIM12LPEN_Pos)
    -
    -

    0x00000040

    - -
    -
    - -

    ◆ RCC_APB1LPENR_TIM12LPEN

    - -
    -
    - - - - -
    #define RCC_APB1LPENR_TIM12LPEN   RCC_APB1LPENR_TIM12LPEN_Msk
    -
    - -
    -
    - -

    ◆ RCC_APB1LPENR_TIM13LPEN_Pos

    - -
    -
    - - - - -
    #define RCC_APB1LPENR_TIM13LPEN_Pos   (7U)
    -
    - -
    -
    - -

    ◆ RCC_APB1LPENR_TIM13LPEN_Msk

    - -
    -
    - - - - -
    #define RCC_APB1LPENR_TIM13LPEN_Msk   (0x1UL << RCC_APB1LPENR_TIM13LPEN_Pos)
    -
    -

    0x00000080

    - -
    -
    - -

    ◆ RCC_APB1LPENR_TIM13LPEN

    - -
    -
    - - - - -
    #define RCC_APB1LPENR_TIM13LPEN   RCC_APB1LPENR_TIM13LPEN_Msk
    -
    - -
    -
    - -

    ◆ RCC_APB1LPENR_TIM14LPEN_Pos

    - -
    -
    - - - - -
    #define RCC_APB1LPENR_TIM14LPEN_Pos   (8U)
    -
    - -
    -
    - -

    ◆ RCC_APB1LPENR_TIM14LPEN_Msk

    - -
    -
    - - - - -
    #define RCC_APB1LPENR_TIM14LPEN_Msk   (0x1UL << RCC_APB1LPENR_TIM14LPEN_Pos)
    -
    -

    0x00000100

    - -
    -
    - -

    ◆ RCC_APB1LPENR_TIM14LPEN

    - -
    -
    - - - - -
    #define RCC_APB1LPENR_TIM14LPEN   RCC_APB1LPENR_TIM14LPEN_Msk
    -
    - -
    -
    - -

    ◆ RCC_APB1LPENR_WWDGLPEN_Pos

    - -
    -
    - - - - -
    #define RCC_APB1LPENR_WWDGLPEN_Pos   (11U)
    -
    - -
    -
    - -

    ◆ RCC_APB1LPENR_WWDGLPEN_Msk

    - -
    -
    - - - - -
    #define RCC_APB1LPENR_WWDGLPEN_Msk   (0x1UL << RCC_APB1LPENR_WWDGLPEN_Pos)
    -
    -

    0x00000800

    - -
    -
    - -

    ◆ RCC_APB1LPENR_WWDGLPEN

    - -
    -
    - - - - -
    #define RCC_APB1LPENR_WWDGLPEN   RCC_APB1LPENR_WWDGLPEN_Msk
    -
    - -
    -
    - -

    ◆ RCC_APB1LPENR_SPI2LPEN_Pos

    - -
    -
    - - - - -
    #define RCC_APB1LPENR_SPI2LPEN_Pos   (14U)
    -
    - -
    -
    - -

    ◆ RCC_APB1LPENR_SPI2LPEN_Msk

    - -
    -
    - - - - -
    #define RCC_APB1LPENR_SPI2LPEN_Msk   (0x1UL << RCC_APB1LPENR_SPI2LPEN_Pos)
    -
    -

    0x00004000

    - -
    -
    - -

    ◆ RCC_APB1LPENR_SPI2LPEN

    - -
    -
    - - - - -
    #define RCC_APB1LPENR_SPI2LPEN   RCC_APB1LPENR_SPI2LPEN_Msk
    -
    - -
    -
    - -

    ◆ RCC_APB1LPENR_SPI3LPEN_Pos

    - -
    -
    - - - - -
    #define RCC_APB1LPENR_SPI3LPEN_Pos   (15U)
    -
    - -
    -
    - -

    ◆ RCC_APB1LPENR_SPI3LPEN_Msk

    - -
    -
    - - - - -
    #define RCC_APB1LPENR_SPI3LPEN_Msk   (0x1UL << RCC_APB1LPENR_SPI3LPEN_Pos)
    -
    -

    0x00008000

    - -
    -
    - -

    ◆ RCC_APB1LPENR_SPI3LPEN

    - -
    -
    - - - - -
    #define RCC_APB1LPENR_SPI3LPEN   RCC_APB1LPENR_SPI3LPEN_Msk
    -
    - -
    -
    - -

    ◆ RCC_APB1LPENR_USART2LPEN_Pos

    - -
    -
    - - - - -
    #define RCC_APB1LPENR_USART2LPEN_Pos   (17U)
    -
    - -
    -
    - -

    ◆ RCC_APB1LPENR_USART2LPEN_Msk

    - -
    -
    - - - - -
    #define RCC_APB1LPENR_USART2LPEN_Msk   (0x1UL << RCC_APB1LPENR_USART2LPEN_Pos)
    -
    -

    0x00020000

    - -
    -
    - -

    ◆ RCC_APB1LPENR_USART2LPEN

    - -
    -
    - - - - -
    #define RCC_APB1LPENR_USART2LPEN   RCC_APB1LPENR_USART2LPEN_Msk
    -
    - -
    -
    - -

    ◆ RCC_APB1LPENR_USART3LPEN_Pos

    - -
    -
    - - - - -
    #define RCC_APB1LPENR_USART3LPEN_Pos   (18U)
    -
    - -
    -
    - -

    ◆ RCC_APB1LPENR_USART3LPEN_Msk

    - -
    -
    - - - - -
    #define RCC_APB1LPENR_USART3LPEN_Msk   (0x1UL << RCC_APB1LPENR_USART3LPEN_Pos)
    -
    -

    0x00040000

    - -
    -
    - -

    ◆ RCC_APB1LPENR_USART3LPEN

    - -
    -
    - - - - -
    #define RCC_APB1LPENR_USART3LPEN   RCC_APB1LPENR_USART3LPEN_Msk
    -
    - -
    -
    - -

    ◆ RCC_APB1LPENR_UART4LPEN_Pos

    - -
    -
    - - - - -
    #define RCC_APB1LPENR_UART4LPEN_Pos   (19U)
    -
    - -
    -
    - -

    ◆ RCC_APB1LPENR_UART4LPEN_Msk

    - -
    -
    - - - - -
    #define RCC_APB1LPENR_UART4LPEN_Msk   (0x1UL << RCC_APB1LPENR_UART4LPEN_Pos)
    -
    -

    0x00080000

    - -
    -
    - -

    ◆ RCC_APB1LPENR_UART4LPEN

    - -
    -
    - - - - -
    #define RCC_APB1LPENR_UART4LPEN   RCC_APB1LPENR_UART4LPEN_Msk
    -
    - -
    -
    - -

    ◆ RCC_APB1LPENR_UART5LPEN_Pos

    - -
    -
    - - - - -
    #define RCC_APB1LPENR_UART5LPEN_Pos   (20U)
    -
    - -
    -
    - -

    ◆ RCC_APB1LPENR_UART5LPEN_Msk

    - -
    -
    - - - - -
    #define RCC_APB1LPENR_UART5LPEN_Msk   (0x1UL << RCC_APB1LPENR_UART5LPEN_Pos)
    -
    -

    0x00100000

    - -
    -
    - -

    ◆ RCC_APB1LPENR_UART5LPEN

    - -
    -
    - - - - -
    #define RCC_APB1LPENR_UART5LPEN   RCC_APB1LPENR_UART5LPEN_Msk
    -
    - -
    -
    - -

    ◆ RCC_APB1LPENR_I2C1LPEN_Pos

    - -
    -
    - - - - -
    #define RCC_APB1LPENR_I2C1LPEN_Pos   (21U)
    -
    - -
    -
    - -

    ◆ RCC_APB1LPENR_I2C1LPEN_Msk

    - -
    -
    - - - - -
    #define RCC_APB1LPENR_I2C1LPEN_Msk   (0x1UL << RCC_APB1LPENR_I2C1LPEN_Pos)
    -
    -

    0x00200000

    - -
    -
    - -

    ◆ RCC_APB1LPENR_I2C1LPEN

    - -
    -
    - - - - -
    #define RCC_APB1LPENR_I2C1LPEN   RCC_APB1LPENR_I2C1LPEN_Msk
    -
    - -
    -
    - -

    ◆ RCC_APB1LPENR_I2C2LPEN_Pos

    - -
    -
    - - - - -
    #define RCC_APB1LPENR_I2C2LPEN_Pos   (22U)
    -
    - -
    -
    - -

    ◆ RCC_APB1LPENR_I2C2LPEN_Msk

    - -
    -
    - - - - -
    #define RCC_APB1LPENR_I2C2LPEN_Msk   (0x1UL << RCC_APB1LPENR_I2C2LPEN_Pos)
    -
    -

    0x00400000

    - -
    -
    - -

    ◆ RCC_APB1LPENR_I2C2LPEN

    - -
    -
    - - - - -
    #define RCC_APB1LPENR_I2C2LPEN   RCC_APB1LPENR_I2C2LPEN_Msk
    -
    - -
    -
    - -

    ◆ RCC_APB1LPENR_I2C3LPEN_Pos

    - -
    -
    - - - - -
    #define RCC_APB1LPENR_I2C3LPEN_Pos   (23U)
    -
    - -
    -
    - -

    ◆ RCC_APB1LPENR_I2C3LPEN_Msk

    - -
    -
    - - - - -
    #define RCC_APB1LPENR_I2C3LPEN_Msk   (0x1UL << RCC_APB1LPENR_I2C3LPEN_Pos)
    -
    -

    0x00800000

    - -
    -
    - -

    ◆ RCC_APB1LPENR_I2C3LPEN

    - -
    -
    - - - - -
    #define RCC_APB1LPENR_I2C3LPEN   RCC_APB1LPENR_I2C3LPEN_Msk
    -
    - -
    -
    - -

    ◆ RCC_APB1LPENR_CAN1LPEN_Pos

    - -
    -
    - - - - -
    #define RCC_APB1LPENR_CAN1LPEN_Pos   (25U)
    -
    - -
    -
    - -

    ◆ RCC_APB1LPENR_CAN1LPEN_Msk

    - -
    -
    - - - - -
    #define RCC_APB1LPENR_CAN1LPEN_Msk   (0x1UL << RCC_APB1LPENR_CAN1LPEN_Pos)
    -
    -

    0x02000000

    - -
    -
    - -

    ◆ RCC_APB1LPENR_CAN1LPEN

    - -
    -
    - - - - -
    #define RCC_APB1LPENR_CAN1LPEN   RCC_APB1LPENR_CAN1LPEN_Msk
    -
    - -
    -
    - -

    ◆ RCC_APB1LPENR_CAN2LPEN_Pos

    - -
    -
    - - - - -
    #define RCC_APB1LPENR_CAN2LPEN_Pos   (26U)
    -
    - -
    -
    - -

    ◆ RCC_APB1LPENR_CAN2LPEN_Msk

    - -
    -
    - - - - -
    #define RCC_APB1LPENR_CAN2LPEN_Msk   (0x1UL << RCC_APB1LPENR_CAN2LPEN_Pos)
    -
    -

    0x04000000

    - -
    -
    - -

    ◆ RCC_APB1LPENR_CAN2LPEN

    - -
    -
    - - - - -
    #define RCC_APB1LPENR_CAN2LPEN   RCC_APB1LPENR_CAN2LPEN_Msk
    -
    - -
    -
    - -

    ◆ RCC_APB1LPENR_PWRLPEN_Pos

    - -
    -
    - - - - -
    #define RCC_APB1LPENR_PWRLPEN_Pos   (28U)
    -
    - -
    -
    - -

    ◆ RCC_APB1LPENR_PWRLPEN_Msk

    - -
    -
    - - - - -
    #define RCC_APB1LPENR_PWRLPEN_Msk   (0x1UL << RCC_APB1LPENR_PWRLPEN_Pos)
    -
    -

    0x10000000

    - -
    -
    - -

    ◆ RCC_APB1LPENR_PWRLPEN

    - -
    -
    - - - - -
    #define RCC_APB1LPENR_PWRLPEN   RCC_APB1LPENR_PWRLPEN_Msk
    -
    - -
    -
    - -

    ◆ RCC_APB1LPENR_DACLPEN_Pos

    - -
    -
    - - - - -
    #define RCC_APB1LPENR_DACLPEN_Pos   (29U)
    -
    - -
    -
    - -

    ◆ RCC_APB1LPENR_DACLPEN_Msk

    - -
    -
    - - - - -
    #define RCC_APB1LPENR_DACLPEN_Msk   (0x1UL << RCC_APB1LPENR_DACLPEN_Pos)
    -
    -

    0x20000000

    - -
    -
    - -

    ◆ RCC_APB1LPENR_DACLPEN

    - -
    -
    - - - - -
    #define RCC_APB1LPENR_DACLPEN   RCC_APB1LPENR_DACLPEN_Msk
    -
    - -
    -
    - -

    ◆ RCC_APB2LPENR_TIM1LPEN_Pos

    - -
    -
    - - - - -
    #define RCC_APB2LPENR_TIM1LPEN_Pos   (0U)
    -
    - -
    -
    - -

    ◆ RCC_APB2LPENR_TIM1LPEN_Msk

    - -
    -
    - - - - -
    #define RCC_APB2LPENR_TIM1LPEN_Msk   (0x1UL << RCC_APB2LPENR_TIM1LPEN_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ RCC_APB2LPENR_TIM1LPEN

    - -
    -
    - - - - -
    #define RCC_APB2LPENR_TIM1LPEN   RCC_APB2LPENR_TIM1LPEN_Msk
    -
    - -
    -
    - -

    ◆ RCC_APB2LPENR_TIM8LPEN_Pos

    - -
    -
    - - - - -
    #define RCC_APB2LPENR_TIM8LPEN_Pos   (1U)
    -
    - -
    -
    - -

    ◆ RCC_APB2LPENR_TIM8LPEN_Msk

    - -
    -
    - - - - -
    #define RCC_APB2LPENR_TIM8LPEN_Msk   (0x1UL << RCC_APB2LPENR_TIM8LPEN_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ RCC_APB2LPENR_TIM8LPEN

    - -
    -
    - - - - -
    #define RCC_APB2LPENR_TIM8LPEN   RCC_APB2LPENR_TIM8LPEN_Msk
    -
    - -
    -
    - -

    ◆ RCC_APB2LPENR_USART1LPEN_Pos

    - -
    -
    - - - - -
    #define RCC_APB2LPENR_USART1LPEN_Pos   (4U)
    -
    - -
    -
    - -

    ◆ RCC_APB2LPENR_USART1LPEN_Msk

    - -
    -
    - - - - -
    #define RCC_APB2LPENR_USART1LPEN_Msk   (0x1UL << RCC_APB2LPENR_USART1LPEN_Pos)
    -
    -

    0x00000010

    - -
    -
    - -

    ◆ RCC_APB2LPENR_USART1LPEN

    - -
    -
    - - - - -
    #define RCC_APB2LPENR_USART1LPEN   RCC_APB2LPENR_USART1LPEN_Msk
    -
    - -
    -
    - -

    ◆ RCC_APB2LPENR_USART6LPEN_Pos

    - -
    -
    - - - - -
    #define RCC_APB2LPENR_USART6LPEN_Pos   (5U)
    -
    - -
    -
    - -

    ◆ RCC_APB2LPENR_USART6LPEN_Msk

    - -
    -
    - - - - -
    #define RCC_APB2LPENR_USART6LPEN_Msk   (0x1UL << RCC_APB2LPENR_USART6LPEN_Pos)
    -
    -

    0x00000020

    - -
    -
    - -

    ◆ RCC_APB2LPENR_USART6LPEN

    - -
    -
    - - - - -
    #define RCC_APB2LPENR_USART6LPEN   RCC_APB2LPENR_USART6LPEN_Msk
    -
    - -
    -
    - -

    ◆ RCC_APB2LPENR_ADC1LPEN_Pos

    - -
    -
    - - - - -
    #define RCC_APB2LPENR_ADC1LPEN_Pos   (8U)
    -
    - -
    -
    - -

    ◆ RCC_APB2LPENR_ADC1LPEN_Msk

    - -
    -
    - - - - -
    #define RCC_APB2LPENR_ADC1LPEN_Msk   (0x1UL << RCC_APB2LPENR_ADC1LPEN_Pos)
    -
    -

    0x00000100

    - -
    -
    - -

    ◆ RCC_APB2LPENR_ADC1LPEN

    - -
    -
    - - - - -
    #define RCC_APB2LPENR_ADC1LPEN   RCC_APB2LPENR_ADC1LPEN_Msk
    -
    - -
    -
    - -

    ◆ RCC_APB2LPENR_ADC2LPEN_Pos

    - -
    -
    - - - - -
    #define RCC_APB2LPENR_ADC2LPEN_Pos   (9U)
    -
    - -
    -
    - -

    ◆ RCC_APB2LPENR_ADC2LPEN_Msk

    - -
    -
    - - - - -
    #define RCC_APB2LPENR_ADC2LPEN_Msk   (0x1UL << RCC_APB2LPENR_ADC2LPEN_Pos)
    -
    -

    0x00000200

    - -
    -
    - -

    ◆ RCC_APB2LPENR_ADC2LPEN

    - -
    -
    - - - - -
    #define RCC_APB2LPENR_ADC2LPEN   RCC_APB2LPENR_ADC2LPEN_Msk
    -
    - -
    -
    - -

    ◆ RCC_APB2LPENR_ADC3LPEN_Pos

    - -
    -
    - - - - -
    #define RCC_APB2LPENR_ADC3LPEN_Pos   (10U)
    -
    - -
    -
    - -

    ◆ RCC_APB2LPENR_ADC3LPEN_Msk

    - -
    -
    - - - - -
    #define RCC_APB2LPENR_ADC3LPEN_Msk   (0x1UL << RCC_APB2LPENR_ADC3LPEN_Pos)
    -
    -

    0x00000400

    - -
    -
    - -

    ◆ RCC_APB2LPENR_ADC3LPEN

    - -
    -
    - - - - -
    #define RCC_APB2LPENR_ADC3LPEN   RCC_APB2LPENR_ADC3LPEN_Msk
    -
    - -
    -
    - -

    ◆ RCC_APB2LPENR_SDIOLPEN_Pos

    - -
    -
    - - - - -
    #define RCC_APB2LPENR_SDIOLPEN_Pos   (11U)
    -
    - -
    -
    - -

    ◆ RCC_APB2LPENR_SDIOLPEN_Msk

    - -
    -
    - - - - -
    #define RCC_APB2LPENR_SDIOLPEN_Msk   (0x1UL << RCC_APB2LPENR_SDIOLPEN_Pos)
    -
    -

    0x00000800

    - -
    -
    - -

    ◆ RCC_APB2LPENR_SDIOLPEN

    - -
    -
    - - - - -
    #define RCC_APB2LPENR_SDIOLPEN   RCC_APB2LPENR_SDIOLPEN_Msk
    -
    - -
    -
    - -

    ◆ RCC_APB2LPENR_SPI1LPEN_Pos

    - -
    -
    - - - - -
    #define RCC_APB2LPENR_SPI1LPEN_Pos   (12U)
    -
    - -
    -
    - -

    ◆ RCC_APB2LPENR_SPI1LPEN_Msk

    - -
    -
    - - - - -
    #define RCC_APB2LPENR_SPI1LPEN_Msk   (0x1UL << RCC_APB2LPENR_SPI1LPEN_Pos)
    -
    -

    0x00001000

    - -
    -
    - -

    ◆ RCC_APB2LPENR_SPI1LPEN

    - -
    -
    - - - - -
    #define RCC_APB2LPENR_SPI1LPEN   RCC_APB2LPENR_SPI1LPEN_Msk
    -
    - -
    -
    - -

    ◆ RCC_APB2LPENR_SYSCFGLPEN_Pos

    - -
    -
    - - - - -
    #define RCC_APB2LPENR_SYSCFGLPEN_Pos   (14U)
    -
    - -
    -
    - -

    ◆ RCC_APB2LPENR_SYSCFGLPEN_Msk

    - -
    -
    - - - - -
    #define RCC_APB2LPENR_SYSCFGLPEN_Msk   (0x1UL << RCC_APB2LPENR_SYSCFGLPEN_Pos)
    -
    -

    0x00004000

    - -
    -
    - -

    ◆ RCC_APB2LPENR_SYSCFGLPEN

    - -
    -
    - - - - -
    #define RCC_APB2LPENR_SYSCFGLPEN   RCC_APB2LPENR_SYSCFGLPEN_Msk
    -
    - -
    -
    - -

    ◆ RCC_APB2LPENR_TIM9LPEN_Pos

    - -
    -
    - - - - -
    #define RCC_APB2LPENR_TIM9LPEN_Pos   (16U)
    -
    - -
    -
    - -

    ◆ RCC_APB2LPENR_TIM9LPEN_Msk

    - -
    -
    - - - - -
    #define RCC_APB2LPENR_TIM9LPEN_Msk   (0x1UL << RCC_APB2LPENR_TIM9LPEN_Pos)
    -
    -

    0x00010000

    - -
    -
    - -

    ◆ RCC_APB2LPENR_TIM9LPEN

    - -
    -
    - - - - -
    #define RCC_APB2LPENR_TIM9LPEN   RCC_APB2LPENR_TIM9LPEN_Msk
    -
    - -
    -
    - -

    ◆ RCC_APB2LPENR_TIM10LPEN_Pos

    - -
    -
    - - - - -
    #define RCC_APB2LPENR_TIM10LPEN_Pos   (17U)
    -
    - -
    -
    - -

    ◆ RCC_APB2LPENR_TIM10LPEN_Msk

    - -
    -
    - - - - -
    #define RCC_APB2LPENR_TIM10LPEN_Msk   (0x1UL << RCC_APB2LPENR_TIM10LPEN_Pos)
    -
    -

    0x00020000

    - -
    -
    - -

    ◆ RCC_APB2LPENR_TIM10LPEN

    - -
    -
    - - - - -
    #define RCC_APB2LPENR_TIM10LPEN   RCC_APB2LPENR_TIM10LPEN_Msk
    -
    - -
    -
    - -

    ◆ RCC_APB2LPENR_TIM11LPEN_Pos

    - -
    -
    - - - - -
    #define RCC_APB2LPENR_TIM11LPEN_Pos   (18U)
    -
    - -
    -
    - -

    ◆ RCC_APB2LPENR_TIM11LPEN_Msk

    - -
    -
    - - - - -
    #define RCC_APB2LPENR_TIM11LPEN_Msk   (0x1UL << RCC_APB2LPENR_TIM11LPEN_Pos)
    -
    -

    0x00040000

    - -
    -
    - -

    ◆ RCC_APB2LPENR_TIM11LPEN

    - -
    -
    - - - - -
    #define RCC_APB2LPENR_TIM11LPEN   RCC_APB2LPENR_TIM11LPEN_Msk
    -
    - -
    -
    - -

    ◆ RCC_BDCR_LSEON_Pos

    - -
    -
    - - - - -
    #define RCC_BDCR_LSEON_Pos   (0U)
    -
    - -
    -
    - -

    ◆ RCC_BDCR_LSEON_Msk

    - -
    -
    - - - - -
    #define RCC_BDCR_LSEON_Msk   (0x1UL << RCC_BDCR_LSEON_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ RCC_BDCR_LSEON

    - -
    -
    - - - - -
    #define RCC_BDCR_LSEON   RCC_BDCR_LSEON_Msk
    -
    - -
    -
    - -

    ◆ RCC_BDCR_LSERDY_Pos

    - -
    -
    - - - - -
    #define RCC_BDCR_LSERDY_Pos   (1U)
    -
    - -
    -
    - -

    ◆ RCC_BDCR_LSERDY_Msk

    - -
    -
    - - - - -
    #define RCC_BDCR_LSERDY_Msk   (0x1UL << RCC_BDCR_LSERDY_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ RCC_BDCR_LSERDY

    - -
    -
    - - - - -
    #define RCC_BDCR_LSERDY   RCC_BDCR_LSERDY_Msk
    -
    - -
    -
    - -

    ◆ RCC_BDCR_LSEBYP_Pos

    - -
    -
    - - - - -
    #define RCC_BDCR_LSEBYP_Pos   (2U)
    -
    - -
    -
    - -

    ◆ RCC_BDCR_LSEBYP_Msk

    - -
    -
    - - - - -
    #define RCC_BDCR_LSEBYP_Msk   (0x1UL << RCC_BDCR_LSEBYP_Pos)
    -
    -

    0x00000004

    - -
    -
    - -

    ◆ RCC_BDCR_LSEBYP

    - -
    -
    - - - - -
    #define RCC_BDCR_LSEBYP   RCC_BDCR_LSEBYP_Msk
    -
    - -
    -
    - -

    ◆ RCC_BDCR_RTCSEL_Pos

    - -
    -
    - - - - -
    #define RCC_BDCR_RTCSEL_Pos   (8U)
    -
    - -
    -
    - -

    ◆ RCC_BDCR_RTCSEL_Msk

    - -
    -
    - - - - -
    #define RCC_BDCR_RTCSEL_Msk   (0x3UL << RCC_BDCR_RTCSEL_Pos)
    -
    -

    0x00000300

    - -
    -
    - -

    ◆ RCC_BDCR_RTCSEL

    - -
    -
    - - - - -
    #define RCC_BDCR_RTCSEL   RCC_BDCR_RTCSEL_Msk
    -
    - -
    -
    - -

    ◆ RCC_BDCR_RTCSEL_0

    - -
    -
    - - - - -
    #define RCC_BDCR_RTCSEL_0   (0x1UL << RCC_BDCR_RTCSEL_Pos)
    -
    -

    0x00000100

    - -
    -
    - -

    ◆ RCC_BDCR_RTCSEL_1

    - -
    -
    - - - - -
    #define RCC_BDCR_RTCSEL_1   (0x2UL << RCC_BDCR_RTCSEL_Pos)
    -
    -

    0x00000200

    - -
    -
    - -

    ◆ RCC_BDCR_RTCEN_Pos

    - -
    -
    - - - - -
    #define RCC_BDCR_RTCEN_Pos   (15U)
    -
    - -
    -
    - -

    ◆ RCC_BDCR_RTCEN_Msk

    - -
    -
    - - - - -
    #define RCC_BDCR_RTCEN_Msk   (0x1UL << RCC_BDCR_RTCEN_Pos)
    -
    -

    0x00008000

    - -
    -
    - -

    ◆ RCC_BDCR_RTCEN

    - -
    -
    - - - - -
    #define RCC_BDCR_RTCEN   RCC_BDCR_RTCEN_Msk
    -
    - -
    -
    - -

    ◆ RCC_BDCR_BDRST_Pos

    - -
    -
    - - - - -
    #define RCC_BDCR_BDRST_Pos   (16U)
    -
    - -
    -
    - -

    ◆ RCC_BDCR_BDRST_Msk

    - -
    -
    - - - - -
    #define RCC_BDCR_BDRST_Msk   (0x1UL << RCC_BDCR_BDRST_Pos)
    -
    -

    0x00010000

    - -
    -
    - -

    ◆ RCC_BDCR_BDRST

    - -
    -
    - - - - -
    #define RCC_BDCR_BDRST   RCC_BDCR_BDRST_Msk
    -
    - -
    -
    - -

    ◆ RCC_CSR_LSION_Pos

    - -
    -
    - - - - -
    #define RCC_CSR_LSION_Pos   (0U)
    -
    - -
    -
    - -

    ◆ RCC_CSR_LSION_Msk

    - -
    -
    - - - - -
    #define RCC_CSR_LSION_Msk   (0x1UL << RCC_CSR_LSION_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ RCC_CSR_LSION

    - -
    -
    - - - - -
    #define RCC_CSR_LSION   RCC_CSR_LSION_Msk
    -
    - -
    -
    - -

    ◆ RCC_CSR_LSIRDY_Pos

    - -
    -
    - - - - -
    #define RCC_CSR_LSIRDY_Pos   (1U)
    -
    - -
    -
    - -

    ◆ RCC_CSR_LSIRDY_Msk

    - -
    -
    - - - - -
    #define RCC_CSR_LSIRDY_Msk   (0x1UL << RCC_CSR_LSIRDY_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ RCC_CSR_LSIRDY

    - -
    -
    - - - - -
    #define RCC_CSR_LSIRDY   RCC_CSR_LSIRDY_Msk
    -
    - -
    -
    - -

    ◆ RCC_CSR_RMVF_Pos

    - -
    -
    - - - - -
    #define RCC_CSR_RMVF_Pos   (24U)
    -
    - -
    -
    - -

    ◆ RCC_CSR_RMVF_Msk

    - -
    -
    - - - - -
    #define RCC_CSR_RMVF_Msk   (0x1UL << RCC_CSR_RMVF_Pos)
    -
    -

    0x01000000

    - -
    -
    - -

    ◆ RCC_CSR_RMVF

    - -
    -
    - - - - -
    #define RCC_CSR_RMVF   RCC_CSR_RMVF_Msk
    -
    - -
    -
    - -

    ◆ RCC_CSR_BORRSTF_Pos

    - -
    -
    - - - - -
    #define RCC_CSR_BORRSTF_Pos   (25U)
    -
    - -
    -
    - -

    ◆ RCC_CSR_BORRSTF_Msk

    - -
    -
    - - - - -
    #define RCC_CSR_BORRSTF_Msk   (0x1UL << RCC_CSR_BORRSTF_Pos)
    -
    -

    0x02000000

    - -
    -
    - -

    ◆ RCC_CSR_BORRSTF

    - -
    -
    - - - - -
    #define RCC_CSR_BORRSTF   RCC_CSR_BORRSTF_Msk
    -
    - -
    -
    - -

    ◆ RCC_CSR_PINRSTF_Pos

    - -
    -
    - - - - -
    #define RCC_CSR_PINRSTF_Pos   (26U)
    -
    - -
    -
    - -

    ◆ RCC_CSR_PINRSTF_Msk

    - -
    -
    - - - - -
    #define RCC_CSR_PINRSTF_Msk   (0x1UL << RCC_CSR_PINRSTF_Pos)
    -
    -

    0x04000000

    - -
    -
    - -

    ◆ RCC_CSR_PINRSTF

    - -
    -
    - - - - -
    #define RCC_CSR_PINRSTF   RCC_CSR_PINRSTF_Msk
    -
    - -
    -
    - -

    ◆ RCC_CSR_PORRSTF_Pos

    - -
    -
    - - - - -
    #define RCC_CSR_PORRSTF_Pos   (27U)
    -
    - -
    -
    - -

    ◆ RCC_CSR_PORRSTF_Msk

    - -
    -
    - - - - -
    #define RCC_CSR_PORRSTF_Msk   (0x1UL << RCC_CSR_PORRSTF_Pos)
    -
    -

    0x08000000

    - -
    -
    - -

    ◆ RCC_CSR_PORRSTF

    - -
    -
    - - - - -
    #define RCC_CSR_PORRSTF   RCC_CSR_PORRSTF_Msk
    -
    - -
    -
    - -

    ◆ RCC_CSR_SFTRSTF_Pos

    - -
    -
    - - - - -
    #define RCC_CSR_SFTRSTF_Pos   (28U)
    -
    - -
    -
    - -

    ◆ RCC_CSR_SFTRSTF_Msk

    - -
    -
    - - - - -
    #define RCC_CSR_SFTRSTF_Msk   (0x1UL << RCC_CSR_SFTRSTF_Pos)
    -
    -

    0x10000000

    - -
    -
    - -

    ◆ RCC_CSR_SFTRSTF

    - -
    -
    - - - - -
    #define RCC_CSR_SFTRSTF   RCC_CSR_SFTRSTF_Msk
    -
    - -
    -
    - -

    ◆ RCC_CSR_IWDGRSTF_Pos

    - -
    -
    - - - - -
    #define RCC_CSR_IWDGRSTF_Pos   (29U)
    -
    - -
    -
    - -

    ◆ RCC_CSR_IWDGRSTF_Msk

    - -
    -
    - - - - -
    #define RCC_CSR_IWDGRSTF_Msk   (0x1UL << RCC_CSR_IWDGRSTF_Pos)
    -
    -

    0x20000000

    - -
    -
    - -

    ◆ RCC_CSR_IWDGRSTF

    - -
    -
    - - - - -
    #define RCC_CSR_IWDGRSTF   RCC_CSR_IWDGRSTF_Msk
    -
    - -
    -
    - -

    ◆ RCC_CSR_WWDGRSTF_Pos

    - -
    -
    - - - - -
    #define RCC_CSR_WWDGRSTF_Pos   (30U)
    -
    - -
    -
    - -

    ◆ RCC_CSR_WWDGRSTF_Msk

    - -
    -
    - - - - -
    #define RCC_CSR_WWDGRSTF_Msk   (0x1UL << RCC_CSR_WWDGRSTF_Pos)
    -
    -

    0x40000000

    - -
    -
    - -

    ◆ RCC_CSR_WWDGRSTF

    - -
    -
    - - - - -
    #define RCC_CSR_WWDGRSTF   RCC_CSR_WWDGRSTF_Msk
    -
    - -
    -
    - -

    ◆ RCC_CSR_LPWRRSTF_Pos

    - -
    -
    - - - - -
    #define RCC_CSR_LPWRRSTF_Pos   (31U)
    -
    - -
    -
    - -

    ◆ RCC_CSR_LPWRRSTF_Msk

    - -
    -
    - - - - -
    #define RCC_CSR_LPWRRSTF_Msk   (0x1UL << RCC_CSR_LPWRRSTF_Pos)
    -
    -

    0x80000000

    - -
    -
    - -

    ◆ RCC_CSR_LPWRRSTF

    - -
    -
    - - - - -
    #define RCC_CSR_LPWRRSTF   RCC_CSR_LPWRRSTF_Msk
    -
    - -
    -
    - -

    ◆ RCC_CSR_PADRSTF

    - -
    -
    - - - - -
    #define RCC_CSR_PADRSTF   RCC_CSR_PINRSTF
    -
    - -
    -
    - -

    ◆ RCC_CSR_WDGRSTF

    - -
    -
    - - - - -
    #define RCC_CSR_WDGRSTF   RCC_CSR_IWDGRSTF
    -
    - -
    -
    - -

    ◆ RCC_SSCGR_MODPER_Pos

    - -
    -
    - - - - -
    #define RCC_SSCGR_MODPER_Pos   (0U)
    -
    - -
    -
    - -

    ◆ RCC_SSCGR_MODPER_Msk

    - -
    -
    - - - - -
    #define RCC_SSCGR_MODPER_Msk   (0x1FFFUL << RCC_SSCGR_MODPER_Pos)
    -
    -

    0x00001FFF

    - -
    -
    - -

    ◆ RCC_SSCGR_MODPER

    - -
    -
    - - - - -
    #define RCC_SSCGR_MODPER   RCC_SSCGR_MODPER_Msk
    -
    - -
    -
    - -

    ◆ RCC_SSCGR_INCSTEP_Pos

    - -
    -
    - - - - -
    #define RCC_SSCGR_INCSTEP_Pos   (13U)
    -
    - -
    -
    - -

    ◆ RCC_SSCGR_INCSTEP_Msk

    - -
    -
    - - - - -
    #define RCC_SSCGR_INCSTEP_Msk   (0x7FFFUL << RCC_SSCGR_INCSTEP_Pos)
    -
    -

    0x0FFFE000

    - -
    -
    - -

    ◆ RCC_SSCGR_INCSTEP

    - -
    -
    - - - - -
    #define RCC_SSCGR_INCSTEP   RCC_SSCGR_INCSTEP_Msk
    -
    - -
    -
    - -

    ◆ RCC_SSCGR_SPREADSEL_Pos

    - -
    -
    - - - - -
    #define RCC_SSCGR_SPREADSEL_Pos   (30U)
    -
    - -
    -
    - -

    ◆ RCC_SSCGR_SPREADSEL_Msk

    - -
    -
    - - - - -
    #define RCC_SSCGR_SPREADSEL_Msk   (0x1UL << RCC_SSCGR_SPREADSEL_Pos)
    -
    -

    0x40000000

    - -
    -
    - -

    ◆ RCC_SSCGR_SPREADSEL

    - -
    -
    - - - - -
    #define RCC_SSCGR_SPREADSEL   RCC_SSCGR_SPREADSEL_Msk
    -
    - -
    -
    - -

    ◆ RCC_SSCGR_SSCGEN_Pos

    - -
    -
    - - - - -
    #define RCC_SSCGR_SSCGEN_Pos   (31U)
    -
    - -
    -
    - -

    ◆ RCC_SSCGR_SSCGEN_Msk

    - -
    -
    - - - - -
    #define RCC_SSCGR_SSCGEN_Msk   (0x1UL << RCC_SSCGR_SSCGEN_Pos)
    -
    -

    0x80000000

    - -
    -
    - -

    ◆ RCC_SSCGR_SSCGEN

    - -
    -
    - - - - -
    #define RCC_SSCGR_SSCGEN   RCC_SSCGR_SSCGEN_Msk
    -
    - -
    -
    - -

    ◆ RCC_PLLI2SCFGR_PLLI2SN_Pos

    - -
    -
    - - - - -
    #define RCC_PLLI2SCFGR_PLLI2SN_Pos   (6U)
    -
    - -
    -
    - -

    ◆ RCC_PLLI2SCFGR_PLLI2SN_Msk

    - -
    -
    - - - - -
    #define RCC_PLLI2SCFGR_PLLI2SN_Msk   (0x1FFUL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
    -
    -

    0x00007FC0

    - -
    -
    - -

    ◆ RCC_PLLI2SCFGR_PLLI2SN

    - -
    -
    - - - - -
    #define RCC_PLLI2SCFGR_PLLI2SN   RCC_PLLI2SCFGR_PLLI2SN_Msk
    -
    - -
    -
    - -

    ◆ RCC_PLLI2SCFGR_PLLI2SN_0

    - -
    -
    - - - - -
    #define RCC_PLLI2SCFGR_PLLI2SN_0   (0x001UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
    -
    -

    0x00000040

    - -
    -
    - -

    ◆ RCC_PLLI2SCFGR_PLLI2SN_1

    - -
    -
    - - - - -
    #define RCC_PLLI2SCFGR_PLLI2SN_1   (0x002UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
    -
    -

    0x00000080

    - -
    -
    - -

    ◆ RCC_PLLI2SCFGR_PLLI2SN_2

    - -
    -
    - - - - -
    #define RCC_PLLI2SCFGR_PLLI2SN_2   (0x004UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
    -
    -

    0x00000100

    - -
    -
    - -

    ◆ RCC_PLLI2SCFGR_PLLI2SN_3

    - -
    -
    - - - - -
    #define RCC_PLLI2SCFGR_PLLI2SN_3   (0x008UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
    -
    -

    0x00000200

    - -
    -
    - -

    ◆ RCC_PLLI2SCFGR_PLLI2SN_4

    - -
    -
    - - - - -
    #define RCC_PLLI2SCFGR_PLLI2SN_4   (0x010UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
    -
    -

    0x00000400

    - -
    -
    - -

    ◆ RCC_PLLI2SCFGR_PLLI2SN_5

    - -
    -
    - - - - -
    #define RCC_PLLI2SCFGR_PLLI2SN_5   (0x020UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
    -
    -

    0x00000800

    - -
    -
    - -

    ◆ RCC_PLLI2SCFGR_PLLI2SN_6

    - -
    -
    - - - - -
    #define RCC_PLLI2SCFGR_PLLI2SN_6   (0x040UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
    -
    -

    0x00001000

    - -
    -
    - -

    ◆ RCC_PLLI2SCFGR_PLLI2SN_7

    - -
    -
    - - - - -
    #define RCC_PLLI2SCFGR_PLLI2SN_7   (0x080UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
    -
    -

    0x00002000

    - -
    -
    - -

    ◆ RCC_PLLI2SCFGR_PLLI2SN_8

    - -
    -
    - - - - -
    #define RCC_PLLI2SCFGR_PLLI2SN_8   (0x100UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
    -
    -

    0x00004000

    - -
    -
    - -

    ◆ RCC_PLLI2SCFGR_PLLI2SR_Pos

    - -
    -
    - - - - -
    #define RCC_PLLI2SCFGR_PLLI2SR_Pos   (28U)
    -
    - -
    -
    - -

    ◆ RCC_PLLI2SCFGR_PLLI2SR_Msk

    - -
    -
    - - - - -
    #define RCC_PLLI2SCFGR_PLLI2SR_Msk   (0x7UL << RCC_PLLI2SCFGR_PLLI2SR_Pos)
    -
    -

    0x70000000

    - -
    -
    - -

    ◆ RCC_PLLI2SCFGR_PLLI2SR

    - -
    -
    - - - - -
    #define RCC_PLLI2SCFGR_PLLI2SR   RCC_PLLI2SCFGR_PLLI2SR_Msk
    -
    - -
    -
    - -

    ◆ RCC_PLLI2SCFGR_PLLI2SR_0

    - -
    -
    - - - - -
    #define RCC_PLLI2SCFGR_PLLI2SR_0   (0x1UL << RCC_PLLI2SCFGR_PLLI2SR_Pos)
    -
    -

    0x10000000

    - -
    -
    - -

    ◆ RCC_PLLI2SCFGR_PLLI2SR_1

    - -
    -
    - - - - -
    #define RCC_PLLI2SCFGR_PLLI2SR_1   (0x2UL << RCC_PLLI2SCFGR_PLLI2SR_Pos)
    -
    -

    0x20000000

    - -
    -
    - -

    ◆ RCC_PLLI2SCFGR_PLLI2SR_2

    - -
    -
    - - - - -
    #define RCC_PLLI2SCFGR_PLLI2SR_2   (0x4UL << RCC_PLLI2SCFGR_PLLI2SR_Pos)
    -
    -

    0x40000000

    - -
    -
    - -

    ◆ RNG_CR_RNGEN_Pos

    - -
    -
    - - - - -
    #define RNG_CR_RNGEN_Pos   (2U)
    -
    - -
    -
    - -

    ◆ RNG_CR_RNGEN_Msk

    - -
    -
    - - - - -
    #define RNG_CR_RNGEN_Msk   (0x1UL << RNG_CR_RNGEN_Pos)
    -
    -

    0x00000004

    - -
    -
    - -

    ◆ RNG_CR_RNGEN

    - -
    -
    - - - - -
    #define RNG_CR_RNGEN   RNG_CR_RNGEN_Msk
    -
    - -
    -
    - -

    ◆ RNG_CR_IE_Pos

    - -
    -
    - - - - -
    #define RNG_CR_IE_Pos   (3U)
    -
    - -
    -
    - -

    ◆ RNG_CR_IE_Msk

    - -
    -
    - - - - -
    #define RNG_CR_IE_Msk   (0x1UL << RNG_CR_IE_Pos)
    -
    -

    0x00000008

    - -
    -
    - -

    ◆ RNG_CR_IE

    - -
    -
    - - - - -
    #define RNG_CR_IE   RNG_CR_IE_Msk
    -
    - -
    -
    - -

    ◆ RNG_SR_DRDY_Pos

    - -
    -
    - - - - -
    #define RNG_SR_DRDY_Pos   (0U)
    -
    - -
    -
    - -

    ◆ RNG_SR_DRDY_Msk

    - -
    -
    - - - - -
    #define RNG_SR_DRDY_Msk   (0x1UL << RNG_SR_DRDY_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ RNG_SR_DRDY

    - -
    -
    - - - - -
    #define RNG_SR_DRDY   RNG_SR_DRDY_Msk
    -
    - -
    -
    - -

    ◆ RNG_SR_CECS_Pos

    - -
    -
    - - - - -
    #define RNG_SR_CECS_Pos   (1U)
    -
    - -
    -
    - -

    ◆ RNG_SR_CECS_Msk

    - -
    -
    - - - - -
    #define RNG_SR_CECS_Msk   (0x1UL << RNG_SR_CECS_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ RNG_SR_CECS

    - -
    -
    - - - - -
    #define RNG_SR_CECS   RNG_SR_CECS_Msk
    -
    - -
    -
    - -

    ◆ RNG_SR_SECS_Pos

    - -
    -
    - - - - -
    #define RNG_SR_SECS_Pos   (2U)
    -
    - -
    -
    - -

    ◆ RNG_SR_SECS_Msk

    - -
    -
    - - - - -
    #define RNG_SR_SECS_Msk   (0x1UL << RNG_SR_SECS_Pos)
    -
    -

    0x00000004

    - -
    -
    - -

    ◆ RNG_SR_SECS

    - -
    -
    - - - - -
    #define RNG_SR_SECS   RNG_SR_SECS_Msk
    -
    - -
    -
    - -

    ◆ RNG_SR_CEIS_Pos

    - -
    -
    - - - - -
    #define RNG_SR_CEIS_Pos   (5U)
    -
    - -
    -
    - -

    ◆ RNG_SR_CEIS_Msk

    - -
    -
    - - - - -
    #define RNG_SR_CEIS_Msk   (0x1UL << RNG_SR_CEIS_Pos)
    -
    -

    0x00000020

    - -
    -
    - -

    ◆ RNG_SR_CEIS

    - -
    -
    - - - - -
    #define RNG_SR_CEIS   RNG_SR_CEIS_Msk
    -
    - -
    -
    - -

    ◆ RNG_SR_SEIS_Pos

    - -
    -
    - - - - -
    #define RNG_SR_SEIS_Pos   (6U)
    -
    - -
    -
    - -

    ◆ RNG_SR_SEIS_Msk

    - -
    -
    - - - - -
    #define RNG_SR_SEIS_Msk   (0x1UL << RNG_SR_SEIS_Pos)
    -
    -

    0x00000040

    - -
    -
    - -

    ◆ RNG_SR_SEIS

    - -
    -
    - - - - -
    #define RNG_SR_SEIS   RNG_SR_SEIS_Msk
    -
    - -
    -
    - -

    ◆ RTC_TAMPER2_SUPPORT

    - -
    -
    - - - - -
    #define RTC_TAMPER2_SUPPORT
    -
    -

    TAMPER 2 feature support

    - -
    -
    - -

    ◆ RTC_AF2_SUPPORT

    - -
    -
    - - - - -
    #define RTC_AF2_SUPPORT
    -
    -

    RTC Alternate Function 2 mapping support

    - -
    -
    - -

    ◆ RTC_TR_PM_Pos

    - -
    -
    - - - - -
    #define RTC_TR_PM_Pos   (22U)
    -
    - -
    -
    - -

    ◆ RTC_TR_PM_Msk

    - -
    -
    - - - - -
    #define RTC_TR_PM_Msk   (0x1UL << RTC_TR_PM_Pos)
    -
    -

    0x00400000

    - -
    -
    - -

    ◆ RTC_TR_PM

    - -
    -
    - - - - -
    #define RTC_TR_PM   RTC_TR_PM_Msk
    -
    - -
    -
    - -

    ◆ RTC_TR_HT_Pos

    - -
    -
    - - - - -
    #define RTC_TR_HT_Pos   (20U)
    -
    - -
    -
    - -

    ◆ RTC_TR_HT_Msk

    - -
    -
    - - - - -
    #define RTC_TR_HT_Msk   (0x3UL << RTC_TR_HT_Pos)
    -
    -

    0x00300000

    - -
    -
    - -

    ◆ RTC_TR_HT

    - -
    -
    - - - - -
    #define RTC_TR_HT   RTC_TR_HT_Msk
    -
    - -
    -
    - -

    ◆ RTC_TR_HT_0

    - -
    -
    - - - - -
    #define RTC_TR_HT_0   (0x1UL << RTC_TR_HT_Pos)
    -
    -

    0x00100000

    - -
    -
    - -

    ◆ RTC_TR_HT_1

    - -
    -
    - - - - -
    #define RTC_TR_HT_1   (0x2UL << RTC_TR_HT_Pos)
    -
    -

    0x00200000

    - -
    -
    - -

    ◆ RTC_TR_HU_Pos

    - -
    -
    - - - - -
    #define RTC_TR_HU_Pos   (16U)
    -
    - -
    -
    - -

    ◆ RTC_TR_HU_Msk

    - -
    -
    - - - - -
    #define RTC_TR_HU_Msk   (0xFUL << RTC_TR_HU_Pos)
    -
    -

    0x000F0000

    - -
    -
    - -

    ◆ RTC_TR_HU

    - -
    -
    - - - - -
    #define RTC_TR_HU   RTC_TR_HU_Msk
    -
    - -
    -
    - -

    ◆ RTC_TR_HU_0

    - -
    -
    - - - - -
    #define RTC_TR_HU_0   (0x1UL << RTC_TR_HU_Pos)
    -
    -

    0x00010000

    - -
    -
    - -

    ◆ RTC_TR_HU_1

    - -
    -
    - - - - -
    #define RTC_TR_HU_1   (0x2UL << RTC_TR_HU_Pos)
    -
    -

    0x00020000

    - -
    -
    - -

    ◆ RTC_TR_HU_2

    - -
    -
    - - - - -
    #define RTC_TR_HU_2   (0x4UL << RTC_TR_HU_Pos)
    -
    -

    0x00040000

    - -
    -
    - -

    ◆ RTC_TR_HU_3

    - -
    -
    - - - - -
    #define RTC_TR_HU_3   (0x8UL << RTC_TR_HU_Pos)
    -
    -

    0x00080000

    - -
    -
    - -

    ◆ RTC_TR_MNT_Pos

    - -
    -
    - - - - -
    #define RTC_TR_MNT_Pos   (12U)
    -
    - -
    -
    - -

    ◆ RTC_TR_MNT_Msk

    - -
    -
    - - - - -
    #define RTC_TR_MNT_Msk   (0x7UL << RTC_TR_MNT_Pos)
    -
    -

    0x00007000

    - -
    -
    - -

    ◆ RTC_TR_MNT

    - -
    -
    - - - - -
    #define RTC_TR_MNT   RTC_TR_MNT_Msk
    -
    - -
    -
    - -

    ◆ RTC_TR_MNT_0

    - -
    -
    - - - - -
    #define RTC_TR_MNT_0   (0x1UL << RTC_TR_MNT_Pos)
    -
    -

    0x00001000

    - -
    -
    - -

    ◆ RTC_TR_MNT_1

    - -
    -
    - - - - -
    #define RTC_TR_MNT_1   (0x2UL << RTC_TR_MNT_Pos)
    -
    -

    0x00002000

    - -
    -
    - -

    ◆ RTC_TR_MNT_2

    - -
    -
    - - - - -
    #define RTC_TR_MNT_2   (0x4UL << RTC_TR_MNT_Pos)
    -
    -

    0x00004000

    - -
    -
    - -

    ◆ RTC_TR_MNU_Pos

    - -
    -
    - - - - -
    #define RTC_TR_MNU_Pos   (8U)
    -
    - -
    -
    - -

    ◆ RTC_TR_MNU_Msk

    - -
    -
    - - - - -
    #define RTC_TR_MNU_Msk   (0xFUL << RTC_TR_MNU_Pos)
    -
    -

    0x00000F00

    - -
    -
    - -

    ◆ RTC_TR_MNU

    - -
    -
    - - - - -
    #define RTC_TR_MNU   RTC_TR_MNU_Msk
    -
    - -
    -
    - -

    ◆ RTC_TR_MNU_0

    - -
    -
    - - - - -
    #define RTC_TR_MNU_0   (0x1UL << RTC_TR_MNU_Pos)
    -
    -

    0x00000100

    - -
    -
    - -

    ◆ RTC_TR_MNU_1

    - -
    -
    - - - - -
    #define RTC_TR_MNU_1   (0x2UL << RTC_TR_MNU_Pos)
    -
    -

    0x00000200

    - -
    -
    - -

    ◆ RTC_TR_MNU_2

    - -
    -
    - - - - -
    #define RTC_TR_MNU_2   (0x4UL << RTC_TR_MNU_Pos)
    -
    -

    0x00000400

    - -
    -
    - -

    ◆ RTC_TR_MNU_3

    - -
    -
    - - - - -
    #define RTC_TR_MNU_3   (0x8UL << RTC_TR_MNU_Pos)
    -
    -

    0x00000800

    - -
    -
    - -

    ◆ RTC_TR_ST_Pos

    - -
    -
    - - - - -
    #define RTC_TR_ST_Pos   (4U)
    -
    - -
    -
    - -

    ◆ RTC_TR_ST_Msk

    - -
    -
    - - - - -
    #define RTC_TR_ST_Msk   (0x7UL << RTC_TR_ST_Pos)
    -
    -

    0x00000070

    - -
    -
    - -

    ◆ RTC_TR_ST

    - -
    -
    - - - - -
    #define RTC_TR_ST   RTC_TR_ST_Msk
    -
    - -
    -
    - -

    ◆ RTC_TR_ST_0

    - -
    -
    - - - - -
    #define RTC_TR_ST_0   (0x1UL << RTC_TR_ST_Pos)
    -
    -

    0x00000010

    - -
    -
    - -

    ◆ RTC_TR_ST_1

    - -
    -
    - - - - -
    #define RTC_TR_ST_1   (0x2UL << RTC_TR_ST_Pos)
    -
    -

    0x00000020

    - -
    -
    - -

    ◆ RTC_TR_ST_2

    - -
    -
    - - - - -
    #define RTC_TR_ST_2   (0x4UL << RTC_TR_ST_Pos)
    -
    -

    0x00000040

    - -
    -
    - -

    ◆ RTC_TR_SU_Pos

    - -
    -
    - - - - -
    #define RTC_TR_SU_Pos   (0U)
    -
    - -
    -
    - -

    ◆ RTC_TR_SU_Msk

    - -
    -
    - - - - -
    #define RTC_TR_SU_Msk   (0xFUL << RTC_TR_SU_Pos)
    -
    -

    0x0000000F

    - -
    -
    - -

    ◆ RTC_TR_SU

    - -
    -
    - - - - -
    #define RTC_TR_SU   RTC_TR_SU_Msk
    -
    - -
    -
    - -

    ◆ RTC_TR_SU_0

    - -
    -
    - - - - -
    #define RTC_TR_SU_0   (0x1UL << RTC_TR_SU_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ RTC_TR_SU_1

    - -
    -
    - - - - -
    #define RTC_TR_SU_1   (0x2UL << RTC_TR_SU_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ RTC_TR_SU_2

    - -
    -
    - - - - -
    #define RTC_TR_SU_2   (0x4UL << RTC_TR_SU_Pos)
    -
    -

    0x00000004

    - -
    -
    - -

    ◆ RTC_TR_SU_3

    - -
    -
    - - - - -
    #define RTC_TR_SU_3   (0x8UL << RTC_TR_SU_Pos)
    -
    -

    0x00000008

    - -
    -
    - -

    ◆ RTC_DR_YT_Pos

    - -
    -
    - - - - -
    #define RTC_DR_YT_Pos   (20U)
    -
    - -
    -
    - -

    ◆ RTC_DR_YT_Msk

    - -
    -
    - - - - -
    #define RTC_DR_YT_Msk   (0xFUL << RTC_DR_YT_Pos)
    -
    -

    0x00F00000

    - -
    -
    - -

    ◆ RTC_DR_YT

    - -
    -
    - - - - -
    #define RTC_DR_YT   RTC_DR_YT_Msk
    -
    - -
    -
    - -

    ◆ RTC_DR_YT_0

    - -
    -
    - - - - -
    #define RTC_DR_YT_0   (0x1UL << RTC_DR_YT_Pos)
    -
    -

    0x00100000

    - -
    -
    - -

    ◆ RTC_DR_YT_1

    - -
    -
    - - - - -
    #define RTC_DR_YT_1   (0x2UL << RTC_DR_YT_Pos)
    -
    -

    0x00200000

    - -
    -
    - -

    ◆ RTC_DR_YT_2

    - -
    -
    - - - - -
    #define RTC_DR_YT_2   (0x4UL << RTC_DR_YT_Pos)
    -
    -

    0x00400000

    - -
    -
    - -

    ◆ RTC_DR_YT_3

    - -
    -
    - - - - -
    #define RTC_DR_YT_3   (0x8UL << RTC_DR_YT_Pos)
    -
    -

    0x00800000

    - -
    -
    - -

    ◆ RTC_DR_YU_Pos

    - -
    -
    - - - - -
    #define RTC_DR_YU_Pos   (16U)
    -
    - -
    -
    - -

    ◆ RTC_DR_YU_Msk

    - -
    -
    - - - - -
    #define RTC_DR_YU_Msk   (0xFUL << RTC_DR_YU_Pos)
    -
    -

    0x000F0000

    - -
    -
    - -

    ◆ RTC_DR_YU

    - -
    -
    - - - - -
    #define RTC_DR_YU   RTC_DR_YU_Msk
    -
    - -
    -
    - -

    ◆ RTC_DR_YU_0

    - -
    -
    - - - - -
    #define RTC_DR_YU_0   (0x1UL << RTC_DR_YU_Pos)
    -
    -

    0x00010000

    - -
    -
    - -

    ◆ RTC_DR_YU_1

    - -
    -
    - - - - -
    #define RTC_DR_YU_1   (0x2UL << RTC_DR_YU_Pos)
    -
    -

    0x00020000

    - -
    -
    - -

    ◆ RTC_DR_YU_2

    - -
    -
    - - - - -
    #define RTC_DR_YU_2   (0x4UL << RTC_DR_YU_Pos)
    -
    -

    0x00040000

    - -
    -
    - -

    ◆ RTC_DR_YU_3

    - -
    -
    - - - - -
    #define RTC_DR_YU_3   (0x8UL << RTC_DR_YU_Pos)
    -
    -

    0x00080000

    - -
    -
    - -

    ◆ RTC_DR_WDU_Pos

    - -
    -
    - - - - -
    #define RTC_DR_WDU_Pos   (13U)
    -
    - -
    -
    - -

    ◆ RTC_DR_WDU_Msk

    - -
    -
    - - - - -
    #define RTC_DR_WDU_Msk   (0x7UL << RTC_DR_WDU_Pos)
    -
    -

    0x0000E000

    - -
    -
    - -

    ◆ RTC_DR_WDU

    - -
    -
    - - - - -
    #define RTC_DR_WDU   RTC_DR_WDU_Msk
    -
    - -
    -
    - -

    ◆ RTC_DR_WDU_0

    - -
    -
    - - - - -
    #define RTC_DR_WDU_0   (0x1UL << RTC_DR_WDU_Pos)
    -
    -

    0x00002000

    - -
    -
    - -

    ◆ RTC_DR_WDU_1

    - -
    -
    - - - - -
    #define RTC_DR_WDU_1   (0x2UL << RTC_DR_WDU_Pos)
    -
    -

    0x00004000

    - -
    -
    - -

    ◆ RTC_DR_WDU_2

    - -
    -
    - - - - -
    #define RTC_DR_WDU_2   (0x4UL << RTC_DR_WDU_Pos)
    -
    -

    0x00008000

    - -
    -
    - -

    ◆ RTC_DR_MT_Pos

    - -
    -
    - - - - -
    #define RTC_DR_MT_Pos   (12U)
    -
    - -
    -
    - -

    ◆ RTC_DR_MT_Msk

    - -
    -
    - - - - -
    #define RTC_DR_MT_Msk   (0x1UL << RTC_DR_MT_Pos)
    -
    -

    0x00001000

    - -
    -
    - -

    ◆ RTC_DR_MT

    - -
    -
    - - - - -
    #define RTC_DR_MT   RTC_DR_MT_Msk
    -
    - -
    -
    - -

    ◆ RTC_DR_MU_Pos

    - -
    -
    - - - - -
    #define RTC_DR_MU_Pos   (8U)
    -
    - -
    -
    - -

    ◆ RTC_DR_MU_Msk

    - -
    -
    - - - - -
    #define RTC_DR_MU_Msk   (0xFUL << RTC_DR_MU_Pos)
    -
    -

    0x00000F00

    - -
    -
    - -

    ◆ RTC_DR_MU

    - -
    -
    - - - - -
    #define RTC_DR_MU   RTC_DR_MU_Msk
    -
    - -
    -
    - -

    ◆ RTC_DR_MU_0

    - -
    -
    - - - - -
    #define RTC_DR_MU_0   (0x1UL << RTC_DR_MU_Pos)
    -
    -

    0x00000100

    - -
    -
    - -

    ◆ RTC_DR_MU_1

    - -
    -
    - - - - -
    #define RTC_DR_MU_1   (0x2UL << RTC_DR_MU_Pos)
    -
    -

    0x00000200

    - -
    -
    - -

    ◆ RTC_DR_MU_2

    - -
    -
    - - - - -
    #define RTC_DR_MU_2   (0x4UL << RTC_DR_MU_Pos)
    -
    -

    0x00000400

    - -
    -
    - -

    ◆ RTC_DR_MU_3

    - -
    -
    - - - - -
    #define RTC_DR_MU_3   (0x8UL << RTC_DR_MU_Pos)
    -
    -

    0x00000800

    - -
    -
    - -

    ◆ RTC_DR_DT_Pos

    - -
    -
    - - - - -
    #define RTC_DR_DT_Pos   (4U)
    -
    - -
    -
    - -

    ◆ RTC_DR_DT_Msk

    - -
    -
    - - - - -
    #define RTC_DR_DT_Msk   (0x3UL << RTC_DR_DT_Pos)
    -
    -

    0x00000030

    - -
    -
    - -

    ◆ RTC_DR_DT

    - -
    -
    - - - - -
    #define RTC_DR_DT   RTC_DR_DT_Msk
    -
    - -
    -
    - -

    ◆ RTC_DR_DT_0

    - -
    -
    - - - - -
    #define RTC_DR_DT_0   (0x1UL << RTC_DR_DT_Pos)
    -
    -

    0x00000010

    - -
    -
    - -

    ◆ RTC_DR_DT_1

    - -
    -
    - - - - -
    #define RTC_DR_DT_1   (0x2UL << RTC_DR_DT_Pos)
    -
    -

    0x00000020

    - -
    -
    - -

    ◆ RTC_DR_DU_Pos

    - -
    -
    - - - - -
    #define RTC_DR_DU_Pos   (0U)
    -
    - -
    -
    - -

    ◆ RTC_DR_DU_Msk

    - -
    -
    - - - - -
    #define RTC_DR_DU_Msk   (0xFUL << RTC_DR_DU_Pos)
    -
    -

    0x0000000F

    - -
    -
    - -

    ◆ RTC_DR_DU

    - -
    -
    - - - - -
    #define RTC_DR_DU   RTC_DR_DU_Msk
    -
    - -
    -
    - -

    ◆ RTC_DR_DU_0

    - -
    -
    - - - - -
    #define RTC_DR_DU_0   (0x1UL << RTC_DR_DU_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ RTC_DR_DU_1

    - -
    -
    - - - - -
    #define RTC_DR_DU_1   (0x2UL << RTC_DR_DU_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ RTC_DR_DU_2

    - -
    -
    - - - - -
    #define RTC_DR_DU_2   (0x4UL << RTC_DR_DU_Pos)
    -
    -

    0x00000004

    - -
    -
    - -

    ◆ RTC_DR_DU_3

    - -
    -
    - - - - -
    #define RTC_DR_DU_3   (0x8UL << RTC_DR_DU_Pos)
    -
    -

    0x00000008

    - -
    -
    - -

    ◆ RTC_CR_COE_Pos

    - -
    -
    - - - - -
    #define RTC_CR_COE_Pos   (23U)
    -
    - -
    -
    - -

    ◆ RTC_CR_COE_Msk

    - -
    -
    - - - - -
    #define RTC_CR_COE_Msk   (0x1UL << RTC_CR_COE_Pos)
    -
    -

    0x00800000

    - -
    -
    - -

    ◆ RTC_CR_COE

    - -
    -
    - - - - -
    #define RTC_CR_COE   RTC_CR_COE_Msk
    -
    - -
    -
    - -

    ◆ RTC_CR_OSEL_Pos

    - -
    -
    - - - - -
    #define RTC_CR_OSEL_Pos   (21U)
    -
    - -
    -
    - -

    ◆ RTC_CR_OSEL_Msk

    - -
    -
    - - - - -
    #define RTC_CR_OSEL_Msk   (0x3UL << RTC_CR_OSEL_Pos)
    -
    -

    0x00600000

    - -
    -
    - -

    ◆ RTC_CR_OSEL

    - -
    -
    - - - - -
    #define RTC_CR_OSEL   RTC_CR_OSEL_Msk
    -
    - -
    -
    - -

    ◆ RTC_CR_OSEL_0

    - -
    -
    - - - - -
    #define RTC_CR_OSEL_0   (0x1UL << RTC_CR_OSEL_Pos)
    -
    -

    0x00200000

    - -
    -
    - -

    ◆ RTC_CR_OSEL_1

    - -
    -
    - - - - -
    #define RTC_CR_OSEL_1   (0x2UL << RTC_CR_OSEL_Pos)
    -
    -

    0x00400000

    - -
    -
    - -

    ◆ RTC_CR_POL_Pos

    - -
    -
    - - - - -
    #define RTC_CR_POL_Pos   (20U)
    -
    - -
    -
    - -

    ◆ RTC_CR_POL_Msk

    - -
    -
    - - - - -
    #define RTC_CR_POL_Msk   (0x1UL << RTC_CR_POL_Pos)
    -
    -

    0x00100000

    - -
    -
    - -

    ◆ RTC_CR_POL

    - -
    -
    - - - - -
    #define RTC_CR_POL   RTC_CR_POL_Msk
    -
    - -
    -
    - -

    ◆ RTC_CR_COSEL_Pos

    - -
    -
    - - - - -
    #define RTC_CR_COSEL_Pos   (19U)
    -
    - -
    -
    - -

    ◆ RTC_CR_COSEL_Msk

    - -
    -
    - - - - -
    #define RTC_CR_COSEL_Msk   (0x1UL << RTC_CR_COSEL_Pos)
    -
    -

    0x00080000

    - -
    -
    - -

    ◆ RTC_CR_COSEL

    - -
    -
    - - - - -
    #define RTC_CR_COSEL   RTC_CR_COSEL_Msk
    -
    - -
    -
    - -

    ◆ RTC_CR_BKP_Pos

    - -
    -
    - - - - -
    #define RTC_CR_BKP_Pos   (18U)
    -
    - -
    -
    - -

    ◆ RTC_CR_BKP_Msk

    - -
    -
    - - - - -
    #define RTC_CR_BKP_Msk   (0x1UL << RTC_CR_BKP_Pos)
    -
    -

    0x00040000

    - -
    -
    - -

    ◆ RTC_CR_BKP

    - -
    -
    - - - - -
    #define RTC_CR_BKP   RTC_CR_BKP_Msk
    -
    - -
    -
    - -

    ◆ RTC_CR_SUB1H_Pos

    - -
    -
    - - - - -
    #define RTC_CR_SUB1H_Pos   (17U)
    -
    - -
    -
    - -

    ◆ RTC_CR_SUB1H_Msk

    - -
    -
    - - - - -
    #define RTC_CR_SUB1H_Msk   (0x1UL << RTC_CR_SUB1H_Pos)
    -
    -

    0x00020000

    - -
    -
    - -

    ◆ RTC_CR_SUB1H

    - -
    -
    - - - - -
    #define RTC_CR_SUB1H   RTC_CR_SUB1H_Msk
    -
    - -
    -
    - -

    ◆ RTC_CR_ADD1H_Pos

    - -
    -
    - - - - -
    #define RTC_CR_ADD1H_Pos   (16U)
    -
    - -
    -
    - -

    ◆ RTC_CR_ADD1H_Msk

    - -
    -
    - - - - -
    #define RTC_CR_ADD1H_Msk   (0x1UL << RTC_CR_ADD1H_Pos)
    -
    -

    0x00010000

    - -
    -
    - -

    ◆ RTC_CR_ADD1H

    - -
    -
    - - - - -
    #define RTC_CR_ADD1H   RTC_CR_ADD1H_Msk
    -
    - -
    -
    - -

    ◆ RTC_CR_TSIE_Pos

    - -
    -
    - - - - -
    #define RTC_CR_TSIE_Pos   (15U)
    -
    - -
    -
    - -

    ◆ RTC_CR_TSIE_Msk

    - -
    -
    - - - - -
    #define RTC_CR_TSIE_Msk   (0x1UL << RTC_CR_TSIE_Pos)
    -
    -

    0x00008000

    - -
    -
    - -

    ◆ RTC_CR_TSIE

    - -
    -
    - - - - -
    #define RTC_CR_TSIE   RTC_CR_TSIE_Msk
    -
    - -
    -
    - -

    ◆ RTC_CR_WUTIE_Pos

    - -
    -
    - - - - -
    #define RTC_CR_WUTIE_Pos   (14U)
    -
    - -
    -
    - -

    ◆ RTC_CR_WUTIE_Msk

    - -
    -
    - - - - -
    #define RTC_CR_WUTIE_Msk   (0x1UL << RTC_CR_WUTIE_Pos)
    -
    -

    0x00004000

    - -
    -
    - -

    ◆ RTC_CR_WUTIE

    - -
    -
    - - - - -
    #define RTC_CR_WUTIE   RTC_CR_WUTIE_Msk
    -
    - -
    -
    - -

    ◆ RTC_CR_ALRBIE_Pos

    - -
    -
    - - - - -
    #define RTC_CR_ALRBIE_Pos   (13U)
    -
    - -
    -
    - -

    ◆ RTC_CR_ALRBIE_Msk

    - -
    -
    - - - - -
    #define RTC_CR_ALRBIE_Msk   (0x1UL << RTC_CR_ALRBIE_Pos)
    -
    -

    0x00002000

    - -
    -
    - -

    ◆ RTC_CR_ALRBIE

    - -
    -
    - - - - -
    #define RTC_CR_ALRBIE   RTC_CR_ALRBIE_Msk
    -
    - -
    -
    - -

    ◆ RTC_CR_ALRAIE_Pos

    - -
    -
    - - - - -
    #define RTC_CR_ALRAIE_Pos   (12U)
    -
    - -
    -
    - -

    ◆ RTC_CR_ALRAIE_Msk

    - -
    -
    - - - - -
    #define RTC_CR_ALRAIE_Msk   (0x1UL << RTC_CR_ALRAIE_Pos)
    -
    -

    0x00001000

    - -
    -
    - -

    ◆ RTC_CR_ALRAIE

    - -
    -
    - - - - -
    #define RTC_CR_ALRAIE   RTC_CR_ALRAIE_Msk
    -
    - -
    -
    - -

    ◆ RTC_CR_TSE_Pos

    - -
    -
    - - - - -
    #define RTC_CR_TSE_Pos   (11U)
    -
    - -
    -
    - -

    ◆ RTC_CR_TSE_Msk

    - -
    -
    - - - - -
    #define RTC_CR_TSE_Msk   (0x1UL << RTC_CR_TSE_Pos)
    -
    -

    0x00000800

    - -
    -
    - -

    ◆ RTC_CR_TSE

    - -
    -
    - - - - -
    #define RTC_CR_TSE   RTC_CR_TSE_Msk
    -
    - -
    -
    - -

    ◆ RTC_CR_WUTE_Pos

    - -
    -
    - - - - -
    #define RTC_CR_WUTE_Pos   (10U)
    -
    - -
    -
    - -

    ◆ RTC_CR_WUTE_Msk

    - -
    -
    - - - - -
    #define RTC_CR_WUTE_Msk   (0x1UL << RTC_CR_WUTE_Pos)
    -
    -

    0x00000400

    - -
    -
    - -

    ◆ RTC_CR_WUTE

    - -
    -
    - - - - -
    #define RTC_CR_WUTE   RTC_CR_WUTE_Msk
    -
    - -
    -
    - -

    ◆ RTC_CR_ALRBE_Pos

    - -
    -
    - - - - -
    #define RTC_CR_ALRBE_Pos   (9U)
    -
    - -
    -
    - -

    ◆ RTC_CR_ALRBE_Msk

    - -
    -
    - - - - -
    #define RTC_CR_ALRBE_Msk   (0x1UL << RTC_CR_ALRBE_Pos)
    -
    -

    0x00000200

    - -
    -
    - -

    ◆ RTC_CR_ALRBE

    - -
    -
    - - - - -
    #define RTC_CR_ALRBE   RTC_CR_ALRBE_Msk
    -
    - -
    -
    - -

    ◆ RTC_CR_ALRAE_Pos

    - -
    -
    - - - - -
    #define RTC_CR_ALRAE_Pos   (8U)
    -
    - -
    -
    - -

    ◆ RTC_CR_ALRAE_Msk

    - -
    -
    - - - - -
    #define RTC_CR_ALRAE_Msk   (0x1UL << RTC_CR_ALRAE_Pos)
    -
    -

    0x00000100

    - -
    -
    - -

    ◆ RTC_CR_ALRAE

    - -
    -
    - - - - -
    #define RTC_CR_ALRAE   RTC_CR_ALRAE_Msk
    -
    - -
    -
    - -

    ◆ RTC_CR_DCE_Pos

    - -
    -
    - - - - -
    #define RTC_CR_DCE_Pos   (7U)
    -
    - -
    -
    - -

    ◆ RTC_CR_DCE_Msk

    - -
    -
    - - - - -
    #define RTC_CR_DCE_Msk   (0x1UL << RTC_CR_DCE_Pos)
    -
    -

    0x00000080

    - -
    -
    - -

    ◆ RTC_CR_DCE

    - -
    -
    - - - - -
    #define RTC_CR_DCE   RTC_CR_DCE_Msk
    -
    - -
    -
    - -

    ◆ RTC_CR_FMT_Pos

    - -
    -
    - - - - -
    #define RTC_CR_FMT_Pos   (6U)
    -
    - -
    -
    - -

    ◆ RTC_CR_FMT_Msk

    - -
    -
    - - - - -
    #define RTC_CR_FMT_Msk   (0x1UL << RTC_CR_FMT_Pos)
    -
    -

    0x00000040

    - -
    -
    - -

    ◆ RTC_CR_FMT

    - -
    -
    - - - - -
    #define RTC_CR_FMT   RTC_CR_FMT_Msk
    -
    - -
    -
    - -

    ◆ RTC_CR_BYPSHAD_Pos

    - -
    -
    - - - - -
    #define RTC_CR_BYPSHAD_Pos   (5U)
    -
    - -
    -
    - -

    ◆ RTC_CR_BYPSHAD_Msk

    - -
    -
    - - - - -
    #define RTC_CR_BYPSHAD_Msk   (0x1UL << RTC_CR_BYPSHAD_Pos)
    -
    -

    0x00000020

    - -
    -
    - -

    ◆ RTC_CR_BYPSHAD

    - -
    -
    - - - - -
    #define RTC_CR_BYPSHAD   RTC_CR_BYPSHAD_Msk
    -
    - -
    -
    - -

    ◆ RTC_CR_REFCKON_Pos

    - -
    -
    - - - - -
    #define RTC_CR_REFCKON_Pos   (4U)
    -
    - -
    -
    - -

    ◆ RTC_CR_REFCKON_Msk

    - -
    -
    - - - - -
    #define RTC_CR_REFCKON_Msk   (0x1UL << RTC_CR_REFCKON_Pos)
    -
    -

    0x00000010

    - -
    -
    - -

    ◆ RTC_CR_REFCKON

    - -
    -
    - - - - -
    #define RTC_CR_REFCKON   RTC_CR_REFCKON_Msk
    -
    - -
    -
    - -

    ◆ RTC_CR_TSEDGE_Pos

    - -
    -
    - - - - -
    #define RTC_CR_TSEDGE_Pos   (3U)
    -
    - -
    -
    - -

    ◆ RTC_CR_TSEDGE_Msk

    - -
    -
    - - - - -
    #define RTC_CR_TSEDGE_Msk   (0x1UL << RTC_CR_TSEDGE_Pos)
    -
    -

    0x00000008

    - -
    -
    - -

    ◆ RTC_CR_TSEDGE

    - -
    -
    - - - - -
    #define RTC_CR_TSEDGE   RTC_CR_TSEDGE_Msk
    -
    - -
    -
    - -

    ◆ RTC_CR_WUCKSEL_Pos

    - -
    -
    - - - - -
    #define RTC_CR_WUCKSEL_Pos   (0U)
    -
    - -
    -
    - -

    ◆ RTC_CR_WUCKSEL_Msk

    - -
    -
    - - - - -
    #define RTC_CR_WUCKSEL_Msk   (0x7UL << RTC_CR_WUCKSEL_Pos)
    -
    -

    0x00000007

    - -
    -
    - -

    ◆ RTC_CR_WUCKSEL

    - -
    -
    - - - - -
    #define RTC_CR_WUCKSEL   RTC_CR_WUCKSEL_Msk
    -
    - -
    -
    - -

    ◆ RTC_CR_WUCKSEL_0

    - -
    -
    - - - - -
    #define RTC_CR_WUCKSEL_0   (0x1UL << RTC_CR_WUCKSEL_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ RTC_CR_WUCKSEL_1

    - -
    -
    - - - - -
    #define RTC_CR_WUCKSEL_1   (0x2UL << RTC_CR_WUCKSEL_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ RTC_CR_WUCKSEL_2

    - -
    -
    - - - - -
    #define RTC_CR_WUCKSEL_2   (0x4UL << RTC_CR_WUCKSEL_Pos)
    -
    -

    0x00000004

    - -
    -
    - -

    ◆ RTC_CR_BCK

    - -
    -
    - - - - -
    #define RTC_CR_BCK   RTC_CR_BKP
    -
    - -
    -
    - -

    ◆ RTC_ISR_RECALPF_Pos

    - -
    -
    - - - - -
    #define RTC_ISR_RECALPF_Pos   (16U)
    -
    - -
    -
    - -

    ◆ RTC_ISR_RECALPF_Msk

    - -
    -
    - - - - -
    #define RTC_ISR_RECALPF_Msk   (0x1UL << RTC_ISR_RECALPF_Pos)
    -
    -

    0x00010000

    - -
    -
    - -

    ◆ RTC_ISR_RECALPF

    - -
    -
    - - - - -
    #define RTC_ISR_RECALPF   RTC_ISR_RECALPF_Msk
    -
    - -
    -
    - -

    ◆ RTC_ISR_TAMP1F_Pos

    - -
    -
    - - - - -
    #define RTC_ISR_TAMP1F_Pos   (13U)
    -
    - -
    -
    - -

    ◆ RTC_ISR_TAMP1F_Msk

    - -
    -
    - - - - -
    #define RTC_ISR_TAMP1F_Msk   (0x1UL << RTC_ISR_TAMP1F_Pos)
    -
    -

    0x00002000

    - -
    -
    - -

    ◆ RTC_ISR_TAMP1F

    - -
    -
    - - - - -
    #define RTC_ISR_TAMP1F   RTC_ISR_TAMP1F_Msk
    -
    - -
    -
    - -

    ◆ RTC_ISR_TAMP2F_Pos

    - -
    -
    - - - - -
    #define RTC_ISR_TAMP2F_Pos   (14U)
    -
    - -
    -
    - -

    ◆ RTC_ISR_TAMP2F_Msk

    - -
    -
    - - - - -
    #define RTC_ISR_TAMP2F_Msk   (0x1UL << RTC_ISR_TAMP2F_Pos)
    -
    -

    0x00004000

    - -
    -
    - -

    ◆ RTC_ISR_TAMP2F

    - -
    -
    - - - - -
    #define RTC_ISR_TAMP2F   RTC_ISR_TAMP2F_Msk
    -
    - -
    -
    - -

    ◆ RTC_ISR_TSOVF_Pos

    - -
    -
    - - - - -
    #define RTC_ISR_TSOVF_Pos   (12U)
    -
    - -
    -
    - -

    ◆ RTC_ISR_TSOVF_Msk

    - -
    -
    - - - - -
    #define RTC_ISR_TSOVF_Msk   (0x1UL << RTC_ISR_TSOVF_Pos)
    -
    -

    0x00001000

    - -
    -
    - -

    ◆ RTC_ISR_TSOVF

    - -
    -
    - - - - -
    #define RTC_ISR_TSOVF   RTC_ISR_TSOVF_Msk
    -
    - -
    -
    - -

    ◆ RTC_ISR_TSF_Pos

    - -
    -
    - - - - -
    #define RTC_ISR_TSF_Pos   (11U)
    -
    - -
    -
    - -

    ◆ RTC_ISR_TSF_Msk

    - -
    -
    - - - - -
    #define RTC_ISR_TSF_Msk   (0x1UL << RTC_ISR_TSF_Pos)
    -
    -

    0x00000800

    - -
    -
    - -

    ◆ RTC_ISR_TSF

    - -
    -
    - - - - -
    #define RTC_ISR_TSF   RTC_ISR_TSF_Msk
    -
    - -
    -
    - -

    ◆ RTC_ISR_WUTF_Pos

    - -
    -
    - - - - -
    #define RTC_ISR_WUTF_Pos   (10U)
    -
    - -
    -
    - -

    ◆ RTC_ISR_WUTF_Msk

    - -
    -
    - - - - -
    #define RTC_ISR_WUTF_Msk   (0x1UL << RTC_ISR_WUTF_Pos)
    -
    -

    0x00000400

    - -
    -
    - -

    ◆ RTC_ISR_WUTF

    - -
    -
    - - - - -
    #define RTC_ISR_WUTF   RTC_ISR_WUTF_Msk
    -
    - -
    -
    - -

    ◆ RTC_ISR_ALRBF_Pos

    - -
    -
    - - - - -
    #define RTC_ISR_ALRBF_Pos   (9U)
    -
    - -
    -
    - -

    ◆ RTC_ISR_ALRBF_Msk

    - -
    -
    - - - - -
    #define RTC_ISR_ALRBF_Msk   (0x1UL << RTC_ISR_ALRBF_Pos)
    -
    -

    0x00000200

    - -
    -
    - -

    ◆ RTC_ISR_ALRBF

    - -
    -
    - - - - -
    #define RTC_ISR_ALRBF   RTC_ISR_ALRBF_Msk
    -
    - -
    -
    - -

    ◆ RTC_ISR_ALRAF_Pos

    - -
    -
    - - - - -
    #define RTC_ISR_ALRAF_Pos   (8U)
    -
    - -
    -
    - -

    ◆ RTC_ISR_ALRAF_Msk

    - -
    -
    - - - - -
    #define RTC_ISR_ALRAF_Msk   (0x1UL << RTC_ISR_ALRAF_Pos)
    -
    -

    0x00000100

    - -
    -
    - -

    ◆ RTC_ISR_ALRAF

    - -
    -
    - - - - -
    #define RTC_ISR_ALRAF   RTC_ISR_ALRAF_Msk
    -
    - -
    -
    - -

    ◆ RTC_ISR_INIT_Pos

    - -
    -
    - - - - -
    #define RTC_ISR_INIT_Pos   (7U)
    -
    - -
    -
    - -

    ◆ RTC_ISR_INIT_Msk

    - -
    -
    - - - - -
    #define RTC_ISR_INIT_Msk   (0x1UL << RTC_ISR_INIT_Pos)
    -
    -

    0x00000080

    - -
    -
    - -

    ◆ RTC_ISR_INIT

    - -
    -
    - - - - -
    #define RTC_ISR_INIT   RTC_ISR_INIT_Msk
    -
    - -
    -
    - -

    ◆ RTC_ISR_INITF_Pos

    - -
    -
    - - - - -
    #define RTC_ISR_INITF_Pos   (6U)
    -
    - -
    -
    - -

    ◆ RTC_ISR_INITF_Msk

    - -
    -
    - - - - -
    #define RTC_ISR_INITF_Msk   (0x1UL << RTC_ISR_INITF_Pos)
    -
    -

    0x00000040

    - -
    -
    - -

    ◆ RTC_ISR_INITF

    - -
    -
    - - - - -
    #define RTC_ISR_INITF   RTC_ISR_INITF_Msk
    -
    - -
    -
    - -

    ◆ RTC_ISR_RSF_Pos

    - -
    -
    - - - - -
    #define RTC_ISR_RSF_Pos   (5U)
    -
    - -
    -
    - -

    ◆ RTC_ISR_RSF_Msk

    - -
    -
    - - - - -
    #define RTC_ISR_RSF_Msk   (0x1UL << RTC_ISR_RSF_Pos)
    -
    -

    0x00000020

    - -
    -
    - -

    ◆ RTC_ISR_RSF

    - -
    -
    - - - - -
    #define RTC_ISR_RSF   RTC_ISR_RSF_Msk
    -
    - -
    -
    - -

    ◆ RTC_ISR_INITS_Pos

    - -
    -
    - - - - -
    #define RTC_ISR_INITS_Pos   (4U)
    -
    - -
    -
    - -

    ◆ RTC_ISR_INITS_Msk

    - -
    -
    - - - - -
    #define RTC_ISR_INITS_Msk   (0x1UL << RTC_ISR_INITS_Pos)
    -
    -

    0x00000010

    - -
    -
    - -

    ◆ RTC_ISR_INITS

    - -
    -
    - - - - -
    #define RTC_ISR_INITS   RTC_ISR_INITS_Msk
    -
    - -
    -
    - -

    ◆ RTC_ISR_SHPF_Pos

    - -
    -
    - - - - -
    #define RTC_ISR_SHPF_Pos   (3U)
    -
    - -
    -
    - -

    ◆ RTC_ISR_SHPF_Msk

    - -
    -
    - - - - -
    #define RTC_ISR_SHPF_Msk   (0x1UL << RTC_ISR_SHPF_Pos)
    -
    -

    0x00000008

    - -
    -
    - -

    ◆ RTC_ISR_SHPF

    - -
    -
    - - - - -
    #define RTC_ISR_SHPF   RTC_ISR_SHPF_Msk
    -
    - -
    -
    - -

    ◆ RTC_ISR_WUTWF_Pos

    - -
    -
    - - - - -
    #define RTC_ISR_WUTWF_Pos   (2U)
    -
    - -
    -
    - -

    ◆ RTC_ISR_WUTWF_Msk

    - -
    -
    - - - - -
    #define RTC_ISR_WUTWF_Msk   (0x1UL << RTC_ISR_WUTWF_Pos)
    -
    -

    0x00000004

    - -
    -
    - -

    ◆ RTC_ISR_WUTWF

    - -
    -
    - - - - -
    #define RTC_ISR_WUTWF   RTC_ISR_WUTWF_Msk
    -
    - -
    -
    - -

    ◆ RTC_ISR_ALRBWF_Pos

    - -
    -
    - - - - -
    #define RTC_ISR_ALRBWF_Pos   (1U)
    -
    - -
    -
    - -

    ◆ RTC_ISR_ALRBWF_Msk

    - -
    -
    - - - - -
    #define RTC_ISR_ALRBWF_Msk   (0x1UL << RTC_ISR_ALRBWF_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ RTC_ISR_ALRBWF

    - -
    -
    - - - - -
    #define RTC_ISR_ALRBWF   RTC_ISR_ALRBWF_Msk
    -
    - -
    -
    - -

    ◆ RTC_ISR_ALRAWF_Pos

    - -
    -
    - - - - -
    #define RTC_ISR_ALRAWF_Pos   (0U)
    -
    - -
    -
    - -

    ◆ RTC_ISR_ALRAWF_Msk

    - -
    -
    - - - - -
    #define RTC_ISR_ALRAWF_Msk   (0x1UL << RTC_ISR_ALRAWF_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ RTC_ISR_ALRAWF

    - -
    -
    - - - - -
    #define RTC_ISR_ALRAWF   RTC_ISR_ALRAWF_Msk
    -
    - -
    -
    - -

    ◆ RTC_PRER_PREDIV_A_Pos

    - -
    -
    - - - - -
    #define RTC_PRER_PREDIV_A_Pos   (16U)
    -
    - -
    -
    - -

    ◆ RTC_PRER_PREDIV_A_Msk

    - -
    -
    - - - - -
    #define RTC_PRER_PREDIV_A_Msk   (0x7FUL << RTC_PRER_PREDIV_A_Pos)
    -
    -

    0x007F0000

    - -
    -
    - -

    ◆ RTC_PRER_PREDIV_A

    - -
    -
    - - - - -
    #define RTC_PRER_PREDIV_A   RTC_PRER_PREDIV_A_Msk
    -
    - -
    -
    - -

    ◆ RTC_PRER_PREDIV_S_Pos

    - -
    -
    - - - - -
    #define RTC_PRER_PREDIV_S_Pos   (0U)
    -
    - -
    -
    - -

    ◆ RTC_PRER_PREDIV_S_Msk

    - -
    -
    - - - - -
    #define RTC_PRER_PREDIV_S_Msk   (0x7FFFUL << RTC_PRER_PREDIV_S_Pos)
    -
    -

    0x00007FFF

    - -
    -
    - -

    ◆ RTC_PRER_PREDIV_S

    - -
    -
    - - - - -
    #define RTC_PRER_PREDIV_S   RTC_PRER_PREDIV_S_Msk
    -
    - -
    -
    - -

    ◆ RTC_WUTR_WUT_Pos

    - -
    -
    - - - - -
    #define RTC_WUTR_WUT_Pos   (0U)
    -
    - -
    -
    - -

    ◆ RTC_WUTR_WUT_Msk

    - -
    -
    - - - - -
    #define RTC_WUTR_WUT_Msk   (0xFFFFUL << RTC_WUTR_WUT_Pos)
    -
    -

    0x0000FFFF

    - -
    -
    - -

    ◆ RTC_WUTR_WUT

    - -
    -
    - - - - -
    #define RTC_WUTR_WUT   RTC_WUTR_WUT_Msk
    -
    - -
    -
    - -

    ◆ RTC_CALIBR_DCS_Pos

    - -
    -
    - - - - -
    #define RTC_CALIBR_DCS_Pos   (7U)
    -
    - -
    -
    - -

    ◆ RTC_CALIBR_DCS_Msk

    - -
    -
    - - - - -
    #define RTC_CALIBR_DCS_Msk   (0x1UL << RTC_CALIBR_DCS_Pos)
    -
    -

    0x00000080

    - -
    -
    - -

    ◆ RTC_CALIBR_DCS

    - -
    -
    - - - - -
    #define RTC_CALIBR_DCS   RTC_CALIBR_DCS_Msk
    -
    - -
    -
    - -

    ◆ RTC_CALIBR_DC_Pos

    - -
    -
    - - - - -
    #define RTC_CALIBR_DC_Pos   (0U)
    -
    - -
    -
    - -

    ◆ RTC_CALIBR_DC_Msk

    - -
    -
    - - - - -
    #define RTC_CALIBR_DC_Msk   (0x1FUL << RTC_CALIBR_DC_Pos)
    -
    -

    0x0000001F

    - -
    -
    - -

    ◆ RTC_CALIBR_DC

    - -
    -
    - - - - -
    #define RTC_CALIBR_DC   RTC_CALIBR_DC_Msk
    -
    - -
    -
    - -

    ◆ RTC_ALRMAR_MSK4_Pos

    - -
    -
    - - - - -
    #define RTC_ALRMAR_MSK4_Pos   (31U)
    -
    - -
    -
    - -

    ◆ RTC_ALRMAR_MSK4_Msk

    - -
    -
    - - - - -
    #define RTC_ALRMAR_MSK4_Msk   (0x1UL << RTC_ALRMAR_MSK4_Pos)
    -
    -

    0x80000000

    - -
    -
    - -

    ◆ RTC_ALRMAR_MSK4

    - -
    -
    - - - - -
    #define RTC_ALRMAR_MSK4   RTC_ALRMAR_MSK4_Msk
    -
    - -
    -
    - -

    ◆ RTC_ALRMAR_WDSEL_Pos

    - -
    -
    - - - - -
    #define RTC_ALRMAR_WDSEL_Pos   (30U)
    -
    - -
    -
    - -

    ◆ RTC_ALRMAR_WDSEL_Msk

    - -
    -
    - - - - -
    #define RTC_ALRMAR_WDSEL_Msk   (0x1UL << RTC_ALRMAR_WDSEL_Pos)
    -
    -

    0x40000000

    - -
    -
    - -

    ◆ RTC_ALRMAR_WDSEL

    - -
    -
    - - - - -
    #define RTC_ALRMAR_WDSEL   RTC_ALRMAR_WDSEL_Msk
    -
    - -
    -
    - -

    ◆ RTC_ALRMAR_DT_Pos

    - -
    -
    - - - - -
    #define RTC_ALRMAR_DT_Pos   (28U)
    -
    - -
    -
    - -

    ◆ RTC_ALRMAR_DT_Msk

    - -
    -
    - - - - -
    #define RTC_ALRMAR_DT_Msk   (0x3UL << RTC_ALRMAR_DT_Pos)
    -
    -

    0x30000000

    - -
    -
    - -

    ◆ RTC_ALRMAR_DT

    - -
    -
    - - - - -
    #define RTC_ALRMAR_DT   RTC_ALRMAR_DT_Msk
    -
    - -
    -
    - -

    ◆ RTC_ALRMAR_DT_0

    - -
    -
    - - - - -
    #define RTC_ALRMAR_DT_0   (0x1UL << RTC_ALRMAR_DT_Pos)
    -
    -

    0x10000000

    - -
    -
    - -

    ◆ RTC_ALRMAR_DT_1

    - -
    -
    - - - - -
    #define RTC_ALRMAR_DT_1   (0x2UL << RTC_ALRMAR_DT_Pos)
    -
    -

    0x20000000

    - -
    -
    - -

    ◆ RTC_ALRMAR_DU_Pos

    - -
    -
    - - - - -
    #define RTC_ALRMAR_DU_Pos   (24U)
    -
    - -
    -
    - -

    ◆ RTC_ALRMAR_DU_Msk

    - -
    -
    - - - - -
    #define RTC_ALRMAR_DU_Msk   (0xFUL << RTC_ALRMAR_DU_Pos)
    -
    -

    0x0F000000

    - -
    -
    - -

    ◆ RTC_ALRMAR_DU

    - -
    -
    - - - - -
    #define RTC_ALRMAR_DU   RTC_ALRMAR_DU_Msk
    -
    - -
    -
    - -

    ◆ RTC_ALRMAR_DU_0

    - -
    -
    - - - - -
    #define RTC_ALRMAR_DU_0   (0x1UL << RTC_ALRMAR_DU_Pos)
    -
    -

    0x01000000

    - -
    -
    - -

    ◆ RTC_ALRMAR_DU_1

    - -
    -
    - - - - -
    #define RTC_ALRMAR_DU_1   (0x2UL << RTC_ALRMAR_DU_Pos)
    -
    -

    0x02000000

    - -
    -
    - -

    ◆ RTC_ALRMAR_DU_2

    - -
    -
    - - - - -
    #define RTC_ALRMAR_DU_2   (0x4UL << RTC_ALRMAR_DU_Pos)
    -
    -

    0x04000000

    - -
    -
    - -

    ◆ RTC_ALRMAR_DU_3

    - -
    -
    - - - - -
    #define RTC_ALRMAR_DU_3   (0x8UL << RTC_ALRMAR_DU_Pos)
    -
    -

    0x08000000

    - -
    -
    - -

    ◆ RTC_ALRMAR_MSK3_Pos

    - -
    -
    - - - - -
    #define RTC_ALRMAR_MSK3_Pos   (23U)
    -
    - -
    -
    - -

    ◆ RTC_ALRMAR_MSK3_Msk

    - -
    -
    - - - - -
    #define RTC_ALRMAR_MSK3_Msk   (0x1UL << RTC_ALRMAR_MSK3_Pos)
    -
    -

    0x00800000

    - -
    -
    - -

    ◆ RTC_ALRMAR_MSK3

    - -
    -
    - - - - -
    #define RTC_ALRMAR_MSK3   RTC_ALRMAR_MSK3_Msk
    -
    - -
    -
    - -

    ◆ RTC_ALRMAR_PM_Pos

    - -
    -
    - - - - -
    #define RTC_ALRMAR_PM_Pos   (22U)
    -
    - -
    -
    - -

    ◆ RTC_ALRMAR_PM_Msk

    - -
    -
    - - - - -
    #define RTC_ALRMAR_PM_Msk   (0x1UL << RTC_ALRMAR_PM_Pos)
    -
    -

    0x00400000

    - -
    -
    - -

    ◆ RTC_ALRMAR_PM

    - -
    -
    - - - - -
    #define RTC_ALRMAR_PM   RTC_ALRMAR_PM_Msk
    -
    - -
    -
    - -

    ◆ RTC_ALRMAR_HT_Pos

    - -
    -
    - - - - -
    #define RTC_ALRMAR_HT_Pos   (20U)
    -
    - -
    -
    - -

    ◆ RTC_ALRMAR_HT_Msk

    - -
    -
    - - - - -
    #define RTC_ALRMAR_HT_Msk   (0x3UL << RTC_ALRMAR_HT_Pos)
    -
    -

    0x00300000

    - -
    -
    - -

    ◆ RTC_ALRMAR_HT

    - -
    -
    - - - - -
    #define RTC_ALRMAR_HT   RTC_ALRMAR_HT_Msk
    -
    - -
    -
    - -

    ◆ RTC_ALRMAR_HT_0

    - -
    -
    - - - - -
    #define RTC_ALRMAR_HT_0   (0x1UL << RTC_ALRMAR_HT_Pos)
    -
    -

    0x00100000

    - -
    -
    - -

    ◆ RTC_ALRMAR_HT_1

    - -
    -
    - - - - -
    #define RTC_ALRMAR_HT_1   (0x2UL << RTC_ALRMAR_HT_Pos)
    -
    -

    0x00200000

    - -
    -
    - -

    ◆ RTC_ALRMAR_HU_Pos

    - -
    -
    - - - - -
    #define RTC_ALRMAR_HU_Pos   (16U)
    -
    - -
    -
    - -

    ◆ RTC_ALRMAR_HU_Msk

    - -
    -
    - - - - -
    #define RTC_ALRMAR_HU_Msk   (0xFUL << RTC_ALRMAR_HU_Pos)
    -
    -

    0x000F0000

    - -
    -
    - -

    ◆ RTC_ALRMAR_HU

    - -
    -
    - - - - -
    #define RTC_ALRMAR_HU   RTC_ALRMAR_HU_Msk
    -
    - -
    -
    - -

    ◆ RTC_ALRMAR_HU_0

    - -
    -
    - - - - -
    #define RTC_ALRMAR_HU_0   (0x1UL << RTC_ALRMAR_HU_Pos)
    -
    -

    0x00010000

    - -
    -
    - -

    ◆ RTC_ALRMAR_HU_1

    - -
    -
    - - - - -
    #define RTC_ALRMAR_HU_1   (0x2UL << RTC_ALRMAR_HU_Pos)
    -
    -

    0x00020000

    - -
    -
    - -

    ◆ RTC_ALRMAR_HU_2

    - -
    -
    - - - - -
    #define RTC_ALRMAR_HU_2   (0x4UL << RTC_ALRMAR_HU_Pos)
    -
    -

    0x00040000

    - -
    -
    - -

    ◆ RTC_ALRMAR_HU_3

    - -
    -
    - - - - -
    #define RTC_ALRMAR_HU_3   (0x8UL << RTC_ALRMAR_HU_Pos)
    -
    -

    0x00080000

    - -
    -
    - -

    ◆ RTC_ALRMAR_MSK2_Pos

    - -
    -
    - - - - -
    #define RTC_ALRMAR_MSK2_Pos   (15U)
    -
    - -
    -
    - -

    ◆ RTC_ALRMAR_MSK2_Msk

    - -
    -
    - - - - -
    #define RTC_ALRMAR_MSK2_Msk   (0x1UL << RTC_ALRMAR_MSK2_Pos)
    -
    -

    0x00008000

    - -
    -
    - -

    ◆ RTC_ALRMAR_MSK2

    - -
    -
    - - - - -
    #define RTC_ALRMAR_MSK2   RTC_ALRMAR_MSK2_Msk
    -
    - -
    -
    - -

    ◆ RTC_ALRMAR_MNT_Pos

    - -
    -
    - - - - -
    #define RTC_ALRMAR_MNT_Pos   (12U)
    -
    - -
    -
    - -

    ◆ RTC_ALRMAR_MNT_Msk

    - -
    -
    - - - - -
    #define RTC_ALRMAR_MNT_Msk   (0x7UL << RTC_ALRMAR_MNT_Pos)
    -
    -

    0x00007000

    - -
    -
    - -

    ◆ RTC_ALRMAR_MNT

    - -
    -
    - - - - -
    #define RTC_ALRMAR_MNT   RTC_ALRMAR_MNT_Msk
    -
    - -
    -
    - -

    ◆ RTC_ALRMAR_MNT_0

    - -
    -
    - - - - -
    #define RTC_ALRMAR_MNT_0   (0x1UL << RTC_ALRMAR_MNT_Pos)
    -
    -

    0x00001000

    - -
    -
    - -

    ◆ RTC_ALRMAR_MNT_1

    - -
    -
    - - - - -
    #define RTC_ALRMAR_MNT_1   (0x2UL << RTC_ALRMAR_MNT_Pos)
    -
    -

    0x00002000

    - -
    -
    - -

    ◆ RTC_ALRMAR_MNT_2

    - -
    -
    - - - - -
    #define RTC_ALRMAR_MNT_2   (0x4UL << RTC_ALRMAR_MNT_Pos)
    -
    -

    0x00004000

    - -
    -
    - -

    ◆ RTC_ALRMAR_MNU_Pos

    - -
    -
    - - - - -
    #define RTC_ALRMAR_MNU_Pos   (8U)
    -
    - -
    -
    - -

    ◆ RTC_ALRMAR_MNU_Msk

    - -
    -
    - - - - -
    #define RTC_ALRMAR_MNU_Msk   (0xFUL << RTC_ALRMAR_MNU_Pos)
    -
    -

    0x00000F00

    - -
    -
    - -

    ◆ RTC_ALRMAR_MNU

    - -
    -
    - - - - -
    #define RTC_ALRMAR_MNU   RTC_ALRMAR_MNU_Msk
    -
    - -
    -
    - -

    ◆ RTC_ALRMAR_MNU_0

    - -
    -
    - - - - -
    #define RTC_ALRMAR_MNU_0   (0x1UL << RTC_ALRMAR_MNU_Pos)
    -
    -

    0x00000100

    - -
    -
    - -

    ◆ RTC_ALRMAR_MNU_1

    - -
    -
    - - - - -
    #define RTC_ALRMAR_MNU_1   (0x2UL << RTC_ALRMAR_MNU_Pos)
    -
    -

    0x00000200

    - -
    -
    - -

    ◆ RTC_ALRMAR_MNU_2

    - -
    -
    - - - - -
    #define RTC_ALRMAR_MNU_2   (0x4UL << RTC_ALRMAR_MNU_Pos)
    -
    -

    0x00000400

    - -
    -
    - -

    ◆ RTC_ALRMAR_MNU_3

    - -
    -
    - - - - -
    #define RTC_ALRMAR_MNU_3   (0x8UL << RTC_ALRMAR_MNU_Pos)
    -
    -

    0x00000800

    - -
    -
    - -

    ◆ RTC_ALRMAR_MSK1_Pos

    - -
    -
    - - - - -
    #define RTC_ALRMAR_MSK1_Pos   (7U)
    -
    - -
    -
    - -

    ◆ RTC_ALRMAR_MSK1_Msk

    - -
    -
    - - - - -
    #define RTC_ALRMAR_MSK1_Msk   (0x1UL << RTC_ALRMAR_MSK1_Pos)
    -
    -

    0x00000080

    - -
    -
    - -

    ◆ RTC_ALRMAR_MSK1

    - -
    -
    - - - - -
    #define RTC_ALRMAR_MSK1   RTC_ALRMAR_MSK1_Msk
    -
    - -
    -
    - -

    ◆ RTC_ALRMAR_ST_Pos

    - -
    -
    - - - - -
    #define RTC_ALRMAR_ST_Pos   (4U)
    -
    - -
    -
    - -

    ◆ RTC_ALRMAR_ST_Msk

    - -
    -
    - - - - -
    #define RTC_ALRMAR_ST_Msk   (0x7UL << RTC_ALRMAR_ST_Pos)
    -
    -

    0x00000070

    - -
    -
    - -

    ◆ RTC_ALRMAR_ST

    - -
    -
    - - - - -
    #define RTC_ALRMAR_ST   RTC_ALRMAR_ST_Msk
    -
    - -
    -
    - -

    ◆ RTC_ALRMAR_ST_0

    - -
    -
    - - - - -
    #define RTC_ALRMAR_ST_0   (0x1UL << RTC_ALRMAR_ST_Pos)
    -
    -

    0x00000010

    - -
    -
    - -

    ◆ RTC_ALRMAR_ST_1

    - -
    -
    - - - - -
    #define RTC_ALRMAR_ST_1   (0x2UL << RTC_ALRMAR_ST_Pos)
    -
    -

    0x00000020

    - -
    -
    - -

    ◆ RTC_ALRMAR_ST_2

    - -
    -
    - - - - -
    #define RTC_ALRMAR_ST_2   (0x4UL << RTC_ALRMAR_ST_Pos)
    -
    -

    0x00000040

    - -
    -
    - -

    ◆ RTC_ALRMAR_SU_Pos

    - -
    -
    - - - - -
    #define RTC_ALRMAR_SU_Pos   (0U)
    -
    - -
    -
    - -

    ◆ RTC_ALRMAR_SU_Msk

    - -
    -
    - - - - -
    #define RTC_ALRMAR_SU_Msk   (0xFUL << RTC_ALRMAR_SU_Pos)
    -
    -

    0x0000000F

    - -
    -
    - -

    ◆ RTC_ALRMAR_SU

    - -
    -
    - - - - -
    #define RTC_ALRMAR_SU   RTC_ALRMAR_SU_Msk
    -
    - -
    -
    - -

    ◆ RTC_ALRMAR_SU_0

    - -
    -
    - - - - -
    #define RTC_ALRMAR_SU_0   (0x1UL << RTC_ALRMAR_SU_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ RTC_ALRMAR_SU_1

    - -
    -
    - - - - -
    #define RTC_ALRMAR_SU_1   (0x2UL << RTC_ALRMAR_SU_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ RTC_ALRMAR_SU_2

    - -
    -
    - - - - -
    #define RTC_ALRMAR_SU_2   (0x4UL << RTC_ALRMAR_SU_Pos)
    -
    -

    0x00000004

    - -
    -
    - -

    ◆ RTC_ALRMAR_SU_3

    - -
    -
    - - - - -
    #define RTC_ALRMAR_SU_3   (0x8UL << RTC_ALRMAR_SU_Pos)
    -
    -

    0x00000008

    - -
    -
    - -

    ◆ RTC_ALRMBR_MSK4_Pos

    - -
    -
    - - - - -
    #define RTC_ALRMBR_MSK4_Pos   (31U)
    -
    - -
    -
    - -

    ◆ RTC_ALRMBR_MSK4_Msk

    - -
    -
    - - - - -
    #define RTC_ALRMBR_MSK4_Msk   (0x1UL << RTC_ALRMBR_MSK4_Pos)
    -
    -

    0x80000000

    - -
    -
    - -

    ◆ RTC_ALRMBR_MSK4

    - -
    -
    - - - - -
    #define RTC_ALRMBR_MSK4   RTC_ALRMBR_MSK4_Msk
    -
    - -
    -
    - -

    ◆ RTC_ALRMBR_WDSEL_Pos

    - -
    -
    - - - - -
    #define RTC_ALRMBR_WDSEL_Pos   (30U)
    -
    - -
    -
    - -

    ◆ RTC_ALRMBR_WDSEL_Msk

    - -
    -
    - - - - -
    #define RTC_ALRMBR_WDSEL_Msk   (0x1UL << RTC_ALRMBR_WDSEL_Pos)
    -
    -

    0x40000000

    - -
    -
    - -

    ◆ RTC_ALRMBR_WDSEL

    - -
    -
    - - - - -
    #define RTC_ALRMBR_WDSEL   RTC_ALRMBR_WDSEL_Msk
    -
    - -
    -
    - -

    ◆ RTC_ALRMBR_DT_Pos

    - -
    -
    - - - - -
    #define RTC_ALRMBR_DT_Pos   (28U)
    -
    - -
    -
    - -

    ◆ RTC_ALRMBR_DT_Msk

    - -
    -
    - - - - -
    #define RTC_ALRMBR_DT_Msk   (0x3UL << RTC_ALRMBR_DT_Pos)
    -
    -

    0x30000000

    - -
    -
    - -

    ◆ RTC_ALRMBR_DT

    - -
    -
    - - - - -
    #define RTC_ALRMBR_DT   RTC_ALRMBR_DT_Msk
    -
    - -
    -
    - -

    ◆ RTC_ALRMBR_DT_0

    - -
    -
    - - - - -
    #define RTC_ALRMBR_DT_0   (0x1UL << RTC_ALRMBR_DT_Pos)
    -
    -

    0x10000000

    - -
    -
    - -

    ◆ RTC_ALRMBR_DT_1

    - -
    -
    - - - - -
    #define RTC_ALRMBR_DT_1   (0x2UL << RTC_ALRMBR_DT_Pos)
    -
    -

    0x20000000

    - -
    -
    - -

    ◆ RTC_ALRMBR_DU_Pos

    - -
    -
    - - - - -
    #define RTC_ALRMBR_DU_Pos   (24U)
    -
    - -
    -
    - -

    ◆ RTC_ALRMBR_DU_Msk

    - -
    -
    - - - - -
    #define RTC_ALRMBR_DU_Msk   (0xFUL << RTC_ALRMBR_DU_Pos)
    -
    -

    0x0F000000

    - -
    -
    - -

    ◆ RTC_ALRMBR_DU

    - -
    -
    - - - - -
    #define RTC_ALRMBR_DU   RTC_ALRMBR_DU_Msk
    -
    - -
    -
    - -

    ◆ RTC_ALRMBR_DU_0

    - -
    -
    - - - - -
    #define RTC_ALRMBR_DU_0   (0x1UL << RTC_ALRMBR_DU_Pos)
    -
    -

    0x01000000

    - -
    -
    - -

    ◆ RTC_ALRMBR_DU_1

    - -
    -
    - - - - -
    #define RTC_ALRMBR_DU_1   (0x2UL << RTC_ALRMBR_DU_Pos)
    -
    -

    0x02000000

    - -
    -
    - -

    ◆ RTC_ALRMBR_DU_2

    - -
    -
    - - - - -
    #define RTC_ALRMBR_DU_2   (0x4UL << RTC_ALRMBR_DU_Pos)
    -
    -

    0x04000000

    - -
    -
    - -

    ◆ RTC_ALRMBR_DU_3

    - -
    -
    - - - - -
    #define RTC_ALRMBR_DU_3   (0x8UL << RTC_ALRMBR_DU_Pos)
    -
    -

    0x08000000

    - -
    -
    - -

    ◆ RTC_ALRMBR_MSK3_Pos

    - -
    -
    - - - - -
    #define RTC_ALRMBR_MSK3_Pos   (23U)
    -
    - -
    -
    - -

    ◆ RTC_ALRMBR_MSK3_Msk

    - -
    -
    - - - - -
    #define RTC_ALRMBR_MSK3_Msk   (0x1UL << RTC_ALRMBR_MSK3_Pos)
    -
    -

    0x00800000

    - -
    -
    - -

    ◆ RTC_ALRMBR_MSK3

    - -
    -
    - - - - -
    #define RTC_ALRMBR_MSK3   RTC_ALRMBR_MSK3_Msk
    -
    - -
    -
    - -

    ◆ RTC_ALRMBR_PM_Pos

    - -
    -
    - - - - -
    #define RTC_ALRMBR_PM_Pos   (22U)
    -
    - -
    -
    - -

    ◆ RTC_ALRMBR_PM_Msk

    - -
    -
    - - - - -
    #define RTC_ALRMBR_PM_Msk   (0x1UL << RTC_ALRMBR_PM_Pos)
    -
    -

    0x00400000

    - -
    -
    - -

    ◆ RTC_ALRMBR_PM

    - -
    -
    - - - - -
    #define RTC_ALRMBR_PM   RTC_ALRMBR_PM_Msk
    -
    - -
    -
    - -

    ◆ RTC_ALRMBR_HT_Pos

    - -
    -
    - - - - -
    #define RTC_ALRMBR_HT_Pos   (20U)
    -
    - -
    -
    - -

    ◆ RTC_ALRMBR_HT_Msk

    - -
    -
    - - - - -
    #define RTC_ALRMBR_HT_Msk   (0x3UL << RTC_ALRMBR_HT_Pos)
    -
    -

    0x00300000

    - -
    -
    - -

    ◆ RTC_ALRMBR_HT

    - -
    -
    - - - - -
    #define RTC_ALRMBR_HT   RTC_ALRMBR_HT_Msk
    -
    - -
    -
    - -

    ◆ RTC_ALRMBR_HT_0

    - -
    -
    - - - - -
    #define RTC_ALRMBR_HT_0   (0x1UL << RTC_ALRMBR_HT_Pos)
    -
    -

    0x00100000

    - -
    -
    - -

    ◆ RTC_ALRMBR_HT_1

    - -
    -
    - - - - -
    #define RTC_ALRMBR_HT_1   (0x2UL << RTC_ALRMBR_HT_Pos)
    -
    -

    0x00200000

    - -
    -
    - -

    ◆ RTC_ALRMBR_HU_Pos

    - -
    -
    - - - - -
    #define RTC_ALRMBR_HU_Pos   (16U)
    -
    - -
    -
    - -

    ◆ RTC_ALRMBR_HU_Msk

    - -
    -
    - - - - -
    #define RTC_ALRMBR_HU_Msk   (0xFUL << RTC_ALRMBR_HU_Pos)
    -
    -

    0x000F0000

    - -
    -
    - -

    ◆ RTC_ALRMBR_HU

    - -
    -
    - - - - -
    #define RTC_ALRMBR_HU   RTC_ALRMBR_HU_Msk
    -
    - -
    -
    - -

    ◆ RTC_ALRMBR_HU_0

    - -
    -
    - - - - -
    #define RTC_ALRMBR_HU_0   (0x1UL << RTC_ALRMBR_HU_Pos)
    -
    -

    0x00010000

    - -
    -
    - -

    ◆ RTC_ALRMBR_HU_1

    - -
    -
    - - - - -
    #define RTC_ALRMBR_HU_1   (0x2UL << RTC_ALRMBR_HU_Pos)
    -
    -

    0x00020000

    - -
    -
    - -

    ◆ RTC_ALRMBR_HU_2

    - -
    -
    - - - - -
    #define RTC_ALRMBR_HU_2   (0x4UL << RTC_ALRMBR_HU_Pos)
    -
    -

    0x00040000

    - -
    -
    - -

    ◆ RTC_ALRMBR_HU_3

    - -
    -
    - - - - -
    #define RTC_ALRMBR_HU_3   (0x8UL << RTC_ALRMBR_HU_Pos)
    -
    -

    0x00080000

    - -
    -
    - -

    ◆ RTC_ALRMBR_MSK2_Pos

    - -
    -
    - - - - -
    #define RTC_ALRMBR_MSK2_Pos   (15U)
    -
    - -
    -
    - -

    ◆ RTC_ALRMBR_MSK2_Msk

    - -
    -
    - - - - -
    #define RTC_ALRMBR_MSK2_Msk   (0x1UL << RTC_ALRMBR_MSK2_Pos)
    -
    -

    0x00008000

    - -
    -
    - -

    ◆ RTC_ALRMBR_MSK2

    - -
    -
    - - - - -
    #define RTC_ALRMBR_MSK2   RTC_ALRMBR_MSK2_Msk
    -
    - -
    -
    - -

    ◆ RTC_ALRMBR_MNT_Pos

    - -
    -
    - - - - -
    #define RTC_ALRMBR_MNT_Pos   (12U)
    -
    - -
    -
    - -

    ◆ RTC_ALRMBR_MNT_Msk

    - -
    -
    - - - - -
    #define RTC_ALRMBR_MNT_Msk   (0x7UL << RTC_ALRMBR_MNT_Pos)
    -
    -

    0x00007000

    - -
    -
    - -

    ◆ RTC_ALRMBR_MNT

    - -
    -
    - - - - -
    #define RTC_ALRMBR_MNT   RTC_ALRMBR_MNT_Msk
    -
    - -
    -
    - -

    ◆ RTC_ALRMBR_MNT_0

    - -
    -
    - - - - -
    #define RTC_ALRMBR_MNT_0   (0x1UL << RTC_ALRMBR_MNT_Pos)
    -
    -

    0x00001000

    - -
    -
    - -

    ◆ RTC_ALRMBR_MNT_1

    - -
    -
    - - - - -
    #define RTC_ALRMBR_MNT_1   (0x2UL << RTC_ALRMBR_MNT_Pos)
    -
    -

    0x00002000

    - -
    -
    - -

    ◆ RTC_ALRMBR_MNT_2

    - -
    -
    - - - - -
    #define RTC_ALRMBR_MNT_2   (0x4UL << RTC_ALRMBR_MNT_Pos)
    -
    -

    0x00004000

    - -
    -
    - -

    ◆ RTC_ALRMBR_MNU_Pos

    - -
    -
    - - - - -
    #define RTC_ALRMBR_MNU_Pos   (8U)
    -
    - -
    -
    - -

    ◆ RTC_ALRMBR_MNU_Msk

    - -
    -
    - - - - -
    #define RTC_ALRMBR_MNU_Msk   (0xFUL << RTC_ALRMBR_MNU_Pos)
    -
    -

    0x00000F00

    - -
    -
    - -

    ◆ RTC_ALRMBR_MNU

    - -
    -
    - - - - -
    #define RTC_ALRMBR_MNU   RTC_ALRMBR_MNU_Msk
    -
    - -
    -
    - -

    ◆ RTC_ALRMBR_MNU_0

    - -
    -
    - - - - -
    #define RTC_ALRMBR_MNU_0   (0x1UL << RTC_ALRMBR_MNU_Pos)
    -
    -

    0x00000100

    - -
    -
    - -

    ◆ RTC_ALRMBR_MNU_1

    - -
    -
    - - - - -
    #define RTC_ALRMBR_MNU_1   (0x2UL << RTC_ALRMBR_MNU_Pos)
    -
    -

    0x00000200

    - -
    -
    - -

    ◆ RTC_ALRMBR_MNU_2

    - -
    -
    - - - - -
    #define RTC_ALRMBR_MNU_2   (0x4UL << RTC_ALRMBR_MNU_Pos)
    -
    -

    0x00000400

    - -
    -
    - -

    ◆ RTC_ALRMBR_MNU_3

    - -
    -
    - - - - -
    #define RTC_ALRMBR_MNU_3   (0x8UL << RTC_ALRMBR_MNU_Pos)
    -
    -

    0x00000800

    - -
    -
    - -

    ◆ RTC_ALRMBR_MSK1_Pos

    - -
    -
    - - - - -
    #define RTC_ALRMBR_MSK1_Pos   (7U)
    -
    - -
    -
    - -

    ◆ RTC_ALRMBR_MSK1_Msk

    - -
    -
    - - - - -
    #define RTC_ALRMBR_MSK1_Msk   (0x1UL << RTC_ALRMBR_MSK1_Pos)
    -
    -

    0x00000080

    - -
    -
    - -

    ◆ RTC_ALRMBR_MSK1

    - -
    -
    - - - - -
    #define RTC_ALRMBR_MSK1   RTC_ALRMBR_MSK1_Msk
    -
    - -
    -
    - -

    ◆ RTC_ALRMBR_ST_Pos

    - -
    -
    - - - - -
    #define RTC_ALRMBR_ST_Pos   (4U)
    -
    - -
    -
    - -

    ◆ RTC_ALRMBR_ST_Msk

    - -
    -
    - - - - -
    #define RTC_ALRMBR_ST_Msk   (0x7UL << RTC_ALRMBR_ST_Pos)
    -
    -

    0x00000070

    - -
    -
    - -

    ◆ RTC_ALRMBR_ST

    - -
    -
    - - - - -
    #define RTC_ALRMBR_ST   RTC_ALRMBR_ST_Msk
    -
    - -
    -
    - -

    ◆ RTC_ALRMBR_ST_0

    - -
    -
    - - - - -
    #define RTC_ALRMBR_ST_0   (0x1UL << RTC_ALRMBR_ST_Pos)
    -
    -

    0x00000010

    - -
    -
    - -

    ◆ RTC_ALRMBR_ST_1

    - -
    -
    - - - - -
    #define RTC_ALRMBR_ST_1   (0x2UL << RTC_ALRMBR_ST_Pos)
    -
    -

    0x00000020

    - -
    -
    - -

    ◆ RTC_ALRMBR_ST_2

    - -
    -
    - - - - -
    #define RTC_ALRMBR_ST_2   (0x4UL << RTC_ALRMBR_ST_Pos)
    -
    -

    0x00000040

    - -
    -
    - -

    ◆ RTC_ALRMBR_SU_Pos

    - -
    -
    - - - - -
    #define RTC_ALRMBR_SU_Pos   (0U)
    -
    - -
    -
    - -

    ◆ RTC_ALRMBR_SU_Msk

    - -
    -
    - - - - -
    #define RTC_ALRMBR_SU_Msk   (0xFUL << RTC_ALRMBR_SU_Pos)
    -
    -

    0x0000000F

    - -
    -
    - -

    ◆ RTC_ALRMBR_SU

    - -
    -
    - - - - -
    #define RTC_ALRMBR_SU   RTC_ALRMBR_SU_Msk
    -
    - -
    -
    - -

    ◆ RTC_ALRMBR_SU_0

    - -
    -
    - - - - -
    #define RTC_ALRMBR_SU_0   (0x1UL << RTC_ALRMBR_SU_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ RTC_ALRMBR_SU_1

    - -
    -
    - - - - -
    #define RTC_ALRMBR_SU_1   (0x2UL << RTC_ALRMBR_SU_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ RTC_ALRMBR_SU_2

    - -
    -
    - - - - -
    #define RTC_ALRMBR_SU_2   (0x4UL << RTC_ALRMBR_SU_Pos)
    -
    -

    0x00000004

    - -
    -
    - -

    ◆ RTC_ALRMBR_SU_3

    - -
    -
    - - - - -
    #define RTC_ALRMBR_SU_3   (0x8UL << RTC_ALRMBR_SU_Pos)
    -
    -

    0x00000008

    - -
    -
    - -

    ◆ RTC_WPR_KEY_Pos

    - -
    -
    - - - - -
    #define RTC_WPR_KEY_Pos   (0U)
    -
    - -
    -
    - -

    ◆ RTC_WPR_KEY_Msk

    - -
    -
    - - - - -
    #define RTC_WPR_KEY_Msk   (0xFFUL << RTC_WPR_KEY_Pos)
    -
    -

    0x000000FF

    - -
    -
    - -

    ◆ RTC_WPR_KEY

    - -
    -
    - - - - -
    #define RTC_WPR_KEY   RTC_WPR_KEY_Msk
    -
    - -
    -
    - -

    ◆ RTC_SSR_SS_Pos

    - -
    -
    - - - - -
    #define RTC_SSR_SS_Pos   (0U)
    -
    - -
    -
    - -

    ◆ RTC_SSR_SS_Msk

    - -
    -
    - - - - -
    #define RTC_SSR_SS_Msk   (0xFFFFUL << RTC_SSR_SS_Pos)
    -
    -

    0x0000FFFF

    - -
    -
    - -

    ◆ RTC_SSR_SS

    - -
    -
    - - - - -
    #define RTC_SSR_SS   RTC_SSR_SS_Msk
    -
    - -
    -
    - -

    ◆ RTC_SHIFTR_SUBFS_Pos

    - -
    -
    - - - - -
    #define RTC_SHIFTR_SUBFS_Pos   (0U)
    -
    - -
    -
    - -

    ◆ RTC_SHIFTR_SUBFS_Msk

    - -
    -
    - - - - -
    #define RTC_SHIFTR_SUBFS_Msk   (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos)
    -
    -

    0x00007FFF

    - -
    -
    - -

    ◆ RTC_SHIFTR_SUBFS

    - -
    -
    - - - - -
    #define RTC_SHIFTR_SUBFS   RTC_SHIFTR_SUBFS_Msk
    -
    - -
    -
    - -

    ◆ RTC_SHIFTR_ADD1S_Pos

    - -
    -
    - - - - -
    #define RTC_SHIFTR_ADD1S_Pos   (31U)
    -
    - -
    -
    - -

    ◆ RTC_SHIFTR_ADD1S_Msk

    - -
    -
    - - - - -
    #define RTC_SHIFTR_ADD1S_Msk   (0x1UL << RTC_SHIFTR_ADD1S_Pos)
    -
    -

    0x80000000

    - -
    -
    - -

    ◆ RTC_SHIFTR_ADD1S

    - -
    -
    - - - - -
    #define RTC_SHIFTR_ADD1S   RTC_SHIFTR_ADD1S_Msk
    -
    - -
    -
    - -

    ◆ RTC_TSTR_PM_Pos

    - -
    -
    - - - - -
    #define RTC_TSTR_PM_Pos   (22U)
    -
    - -
    -
    - -

    ◆ RTC_TSTR_PM_Msk

    - -
    -
    - - - - -
    #define RTC_TSTR_PM_Msk   (0x1UL << RTC_TSTR_PM_Pos)
    -
    -

    0x00400000

    - -
    -
    - -

    ◆ RTC_TSTR_PM

    - -
    -
    - - - - -
    #define RTC_TSTR_PM   RTC_TSTR_PM_Msk
    -
    - -
    -
    - -

    ◆ RTC_TSTR_HT_Pos

    - -
    -
    - - - - -
    #define RTC_TSTR_HT_Pos   (20U)
    -
    - -
    -
    - -

    ◆ RTC_TSTR_HT_Msk

    - -
    -
    - - - - -
    #define RTC_TSTR_HT_Msk   (0x3UL << RTC_TSTR_HT_Pos)
    -
    -

    0x00300000

    - -
    -
    - -

    ◆ RTC_TSTR_HT

    - -
    -
    - - - - -
    #define RTC_TSTR_HT   RTC_TSTR_HT_Msk
    -
    - -
    -
    - -

    ◆ RTC_TSTR_HT_0

    - -
    -
    - - - - -
    #define RTC_TSTR_HT_0   (0x1UL << RTC_TSTR_HT_Pos)
    -
    -

    0x00100000

    - -
    -
    - -

    ◆ RTC_TSTR_HT_1

    - -
    -
    - - - - -
    #define RTC_TSTR_HT_1   (0x2UL << RTC_TSTR_HT_Pos)
    -
    -

    0x00200000

    - -
    -
    - -

    ◆ RTC_TSTR_HU_Pos

    - -
    -
    - - - - -
    #define RTC_TSTR_HU_Pos   (16U)
    -
    - -
    -
    - -

    ◆ RTC_TSTR_HU_Msk

    - -
    -
    - - - - -
    #define RTC_TSTR_HU_Msk   (0xFUL << RTC_TSTR_HU_Pos)
    -
    -

    0x000F0000

    - -
    -
    - -

    ◆ RTC_TSTR_HU

    - -
    -
    - - - - -
    #define RTC_TSTR_HU   RTC_TSTR_HU_Msk
    -
    - -
    -
    - -

    ◆ RTC_TSTR_HU_0

    - -
    -
    - - - - -
    #define RTC_TSTR_HU_0   (0x1UL << RTC_TSTR_HU_Pos)
    -
    -

    0x00010000

    - -
    -
    - -

    ◆ RTC_TSTR_HU_1

    - -
    -
    - - - - -
    #define RTC_TSTR_HU_1   (0x2UL << RTC_TSTR_HU_Pos)
    -
    -

    0x00020000

    - -
    -
    - -

    ◆ RTC_TSTR_HU_2

    - -
    -
    - - - - -
    #define RTC_TSTR_HU_2   (0x4UL << RTC_TSTR_HU_Pos)
    -
    -

    0x00040000

    - -
    -
    - -

    ◆ RTC_TSTR_HU_3

    - -
    -
    - - - - -
    #define RTC_TSTR_HU_3   (0x8UL << RTC_TSTR_HU_Pos)
    -
    -

    0x00080000

    - -
    -
    - -

    ◆ RTC_TSTR_MNT_Pos

    - -
    -
    - - - - -
    #define RTC_TSTR_MNT_Pos   (12U)
    -
    - -
    -
    - -

    ◆ RTC_TSTR_MNT_Msk

    - -
    -
    - - - - -
    #define RTC_TSTR_MNT_Msk   (0x7UL << RTC_TSTR_MNT_Pos)
    -
    -

    0x00007000

    - -
    -
    - -

    ◆ RTC_TSTR_MNT

    - -
    -
    - - - - -
    #define RTC_TSTR_MNT   RTC_TSTR_MNT_Msk
    -
    - -
    -
    - -

    ◆ RTC_TSTR_MNT_0

    - -
    -
    - - - - -
    #define RTC_TSTR_MNT_0   (0x1UL << RTC_TSTR_MNT_Pos)
    -
    -

    0x00001000

    - -
    -
    - -

    ◆ RTC_TSTR_MNT_1

    - -
    -
    - - - - -
    #define RTC_TSTR_MNT_1   (0x2UL << RTC_TSTR_MNT_Pos)
    -
    -

    0x00002000

    - -
    -
    - -

    ◆ RTC_TSTR_MNT_2

    - -
    -
    - - - - -
    #define RTC_TSTR_MNT_2   (0x4UL << RTC_TSTR_MNT_Pos)
    -
    -

    0x00004000

    - -
    -
    - -

    ◆ RTC_TSTR_MNU_Pos

    - -
    -
    - - - - -
    #define RTC_TSTR_MNU_Pos   (8U)
    -
    - -
    -
    - -

    ◆ RTC_TSTR_MNU_Msk

    - -
    -
    - - - - -
    #define RTC_TSTR_MNU_Msk   (0xFUL << RTC_TSTR_MNU_Pos)
    -
    -

    0x00000F00

    - -
    -
    - -

    ◆ RTC_TSTR_MNU

    - -
    -
    - - - - -
    #define RTC_TSTR_MNU   RTC_TSTR_MNU_Msk
    -
    - -
    -
    - -

    ◆ RTC_TSTR_MNU_0

    - -
    -
    - - - - -
    #define RTC_TSTR_MNU_0   (0x1UL << RTC_TSTR_MNU_Pos)
    -
    -

    0x00000100

    - -
    -
    - -

    ◆ RTC_TSTR_MNU_1

    - -
    -
    - - - - -
    #define RTC_TSTR_MNU_1   (0x2UL << RTC_TSTR_MNU_Pos)
    -
    -

    0x00000200

    - -
    -
    - -

    ◆ RTC_TSTR_MNU_2

    - -
    -
    - - - - -
    #define RTC_TSTR_MNU_2   (0x4UL << RTC_TSTR_MNU_Pos)
    -
    -

    0x00000400

    - -
    -
    - -

    ◆ RTC_TSTR_MNU_3

    - -
    -
    - - - - -
    #define RTC_TSTR_MNU_3   (0x8UL << RTC_TSTR_MNU_Pos)
    -
    -

    0x00000800

    - -
    -
    - -

    ◆ RTC_TSTR_ST_Pos

    - -
    -
    - - - - -
    #define RTC_TSTR_ST_Pos   (4U)
    -
    - -
    -
    - -

    ◆ RTC_TSTR_ST_Msk

    - -
    -
    - - - - -
    #define RTC_TSTR_ST_Msk   (0x7UL << RTC_TSTR_ST_Pos)
    -
    -

    0x00000070

    - -
    -
    - -

    ◆ RTC_TSTR_ST

    - -
    -
    - - - - -
    #define RTC_TSTR_ST   RTC_TSTR_ST_Msk
    -
    - -
    -
    - -

    ◆ RTC_TSTR_ST_0

    - -
    -
    - - - - -
    #define RTC_TSTR_ST_0   (0x1UL << RTC_TSTR_ST_Pos)
    -
    -

    0x00000010

    - -
    -
    - -

    ◆ RTC_TSTR_ST_1

    - -
    -
    - - - - -
    #define RTC_TSTR_ST_1   (0x2UL << RTC_TSTR_ST_Pos)
    -
    -

    0x00000020

    - -
    -
    - -

    ◆ RTC_TSTR_ST_2

    - -
    -
    - - - - -
    #define RTC_TSTR_ST_2   (0x4UL << RTC_TSTR_ST_Pos)
    -
    -

    0x00000040

    - -
    -
    - -

    ◆ RTC_TSTR_SU_Pos

    - -
    -
    - - - - -
    #define RTC_TSTR_SU_Pos   (0U)
    -
    - -
    -
    - -

    ◆ RTC_TSTR_SU_Msk

    - -
    -
    - - - - -
    #define RTC_TSTR_SU_Msk   (0xFUL << RTC_TSTR_SU_Pos)
    -
    -

    0x0000000F

    - -
    -
    - -

    ◆ RTC_TSTR_SU

    - -
    -
    - - - - -
    #define RTC_TSTR_SU   RTC_TSTR_SU_Msk
    -
    - -
    -
    - -

    ◆ RTC_TSTR_SU_0

    - -
    -
    - - - - -
    #define RTC_TSTR_SU_0   (0x1UL << RTC_TSTR_SU_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ RTC_TSTR_SU_1

    - -
    -
    - - - - -
    #define RTC_TSTR_SU_1   (0x2UL << RTC_TSTR_SU_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ RTC_TSTR_SU_2

    - -
    -
    - - - - -
    #define RTC_TSTR_SU_2   (0x4UL << RTC_TSTR_SU_Pos)
    -
    -

    0x00000004

    - -
    -
    - -

    ◆ RTC_TSTR_SU_3

    - -
    -
    - - - - -
    #define RTC_TSTR_SU_3   (0x8UL << RTC_TSTR_SU_Pos)
    -
    -

    0x00000008

    - -
    -
    - -

    ◆ RTC_TSDR_WDU_Pos

    - -
    -
    - - - - -
    #define RTC_TSDR_WDU_Pos   (13U)
    -
    - -
    -
    - -

    ◆ RTC_TSDR_WDU_Msk

    - -
    -
    - - - - -
    #define RTC_TSDR_WDU_Msk   (0x7UL << RTC_TSDR_WDU_Pos)
    -
    -

    0x0000E000

    - -
    -
    - -

    ◆ RTC_TSDR_WDU

    - -
    -
    - - - - -
    #define RTC_TSDR_WDU   RTC_TSDR_WDU_Msk
    -
    - -
    -
    - -

    ◆ RTC_TSDR_WDU_0

    - -
    -
    - - - - -
    #define RTC_TSDR_WDU_0   (0x1UL << RTC_TSDR_WDU_Pos)
    -
    -

    0x00002000

    - -
    -
    - -

    ◆ RTC_TSDR_WDU_1

    - -
    -
    - - - - -
    #define RTC_TSDR_WDU_1   (0x2UL << RTC_TSDR_WDU_Pos)
    -
    -

    0x00004000

    - -
    -
    - -

    ◆ RTC_TSDR_WDU_2

    - -
    -
    - - - - -
    #define RTC_TSDR_WDU_2   (0x4UL << RTC_TSDR_WDU_Pos)
    -
    -

    0x00008000

    - -
    -
    - -

    ◆ RTC_TSDR_MT_Pos

    - -
    -
    - - - - -
    #define RTC_TSDR_MT_Pos   (12U)
    -
    - -
    -
    - -

    ◆ RTC_TSDR_MT_Msk

    - -
    -
    - - - - -
    #define RTC_TSDR_MT_Msk   (0x1UL << RTC_TSDR_MT_Pos)
    -
    -

    0x00001000

    - -
    -
    - -

    ◆ RTC_TSDR_MT

    - -
    -
    - - - - -
    #define RTC_TSDR_MT   RTC_TSDR_MT_Msk
    -
    - -
    -
    - -

    ◆ RTC_TSDR_MU_Pos

    - -
    -
    - - - - -
    #define RTC_TSDR_MU_Pos   (8U)
    -
    - -
    -
    - -

    ◆ RTC_TSDR_MU_Msk

    - -
    -
    - - - - -
    #define RTC_TSDR_MU_Msk   (0xFUL << RTC_TSDR_MU_Pos)
    -
    -

    0x00000F00

    - -
    -
    - -

    ◆ RTC_TSDR_MU

    - -
    -
    - - - - -
    #define RTC_TSDR_MU   RTC_TSDR_MU_Msk
    -
    - -
    -
    - -

    ◆ RTC_TSDR_MU_0

    - -
    -
    - - - - -
    #define RTC_TSDR_MU_0   (0x1UL << RTC_TSDR_MU_Pos)
    -
    -

    0x00000100

    - -
    -
    - -

    ◆ RTC_TSDR_MU_1

    - -
    -
    - - - - -
    #define RTC_TSDR_MU_1   (0x2UL << RTC_TSDR_MU_Pos)
    -
    -

    0x00000200

    - -
    -
    - -

    ◆ RTC_TSDR_MU_2

    - -
    -
    - - - - -
    #define RTC_TSDR_MU_2   (0x4UL << RTC_TSDR_MU_Pos)
    -
    -

    0x00000400

    - -
    -
    - -

    ◆ RTC_TSDR_MU_3

    - -
    -
    - - - - -
    #define RTC_TSDR_MU_3   (0x8UL << RTC_TSDR_MU_Pos)
    -
    -

    0x00000800

    - -
    -
    - -

    ◆ RTC_TSDR_DT_Pos

    - -
    -
    - - - - -
    #define RTC_TSDR_DT_Pos   (4U)
    -
    - -
    -
    - -

    ◆ RTC_TSDR_DT_Msk

    - -
    -
    - - - - -
    #define RTC_TSDR_DT_Msk   (0x3UL << RTC_TSDR_DT_Pos)
    -
    -

    0x00000030

    - -
    -
    - -

    ◆ RTC_TSDR_DT

    - -
    -
    - - - - -
    #define RTC_TSDR_DT   RTC_TSDR_DT_Msk
    -
    - -
    -
    - -

    ◆ RTC_TSDR_DT_0

    - -
    -
    - - - - -
    #define RTC_TSDR_DT_0   (0x1UL << RTC_TSDR_DT_Pos)
    -
    -

    0x00000010

    - -
    -
    - -

    ◆ RTC_TSDR_DT_1

    - -
    -
    - - - - -
    #define RTC_TSDR_DT_1   (0x2UL << RTC_TSDR_DT_Pos)
    -
    -

    0x00000020

    - -
    -
    - -

    ◆ RTC_TSDR_DU_Pos

    - -
    -
    - - - - -
    #define RTC_TSDR_DU_Pos   (0U)
    -
    - -
    -
    - -

    ◆ RTC_TSDR_DU_Msk

    - -
    -
    - - - - -
    #define RTC_TSDR_DU_Msk   (0xFUL << RTC_TSDR_DU_Pos)
    -
    -

    0x0000000F

    - -
    -
    - -

    ◆ RTC_TSDR_DU

    - -
    -
    - - - - -
    #define RTC_TSDR_DU   RTC_TSDR_DU_Msk
    -
    - -
    -
    - -

    ◆ RTC_TSDR_DU_0

    - -
    -
    - - - - -
    #define RTC_TSDR_DU_0   (0x1UL << RTC_TSDR_DU_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ RTC_TSDR_DU_1

    - -
    -
    - - - - -
    #define RTC_TSDR_DU_1   (0x2UL << RTC_TSDR_DU_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ RTC_TSDR_DU_2

    - -
    -
    - - - - -
    #define RTC_TSDR_DU_2   (0x4UL << RTC_TSDR_DU_Pos)
    -
    -

    0x00000004

    - -
    -
    - -

    ◆ RTC_TSDR_DU_3

    - -
    -
    - - - - -
    #define RTC_TSDR_DU_3   (0x8UL << RTC_TSDR_DU_Pos)
    -
    -

    0x00000008

    - -
    -
    - -

    ◆ RTC_TSSSR_SS_Pos

    - -
    -
    - - - - -
    #define RTC_TSSSR_SS_Pos   (0U)
    -
    - -
    -
    - -

    ◆ RTC_TSSSR_SS_Msk

    - -
    -
    - - - - -
    #define RTC_TSSSR_SS_Msk   (0xFFFFUL << RTC_TSSSR_SS_Pos)
    -
    -

    0x0000FFFF

    - -
    -
    - -

    ◆ RTC_TSSSR_SS

    - -
    -
    - - - - -
    #define RTC_TSSSR_SS   RTC_TSSSR_SS_Msk
    -
    - -
    -
    - -

    ◆ RTC_CALR_CALP_Pos

    - -
    -
    - - - - -
    #define RTC_CALR_CALP_Pos   (15U)
    -
    - -
    -
    - -

    ◆ RTC_CALR_CALP_Msk

    - -
    -
    - - - - -
    #define RTC_CALR_CALP_Msk   (0x1UL << RTC_CALR_CALP_Pos)
    -
    -

    0x00008000

    - -
    -
    - -

    ◆ RTC_CALR_CALP

    - -
    -
    - - - - -
    #define RTC_CALR_CALP   RTC_CALR_CALP_Msk
    -
    - -
    -
    - -

    ◆ RTC_CALR_CALW8_Pos

    - -
    -
    - - - - -
    #define RTC_CALR_CALW8_Pos   (14U)
    -
    - -
    -
    - -

    ◆ RTC_CALR_CALW8_Msk

    - -
    -
    - - - - -
    #define RTC_CALR_CALW8_Msk   (0x1UL << RTC_CALR_CALW8_Pos)
    -
    -

    0x00004000

    - -
    -
    - -

    ◆ RTC_CALR_CALW8

    - -
    -
    - - - - -
    #define RTC_CALR_CALW8   RTC_CALR_CALW8_Msk
    -
    - -
    -
    - -

    ◆ RTC_CALR_CALW16_Pos

    - -
    -
    - - - - -
    #define RTC_CALR_CALW16_Pos   (13U)
    -
    - -
    -
    - -

    ◆ RTC_CALR_CALW16_Msk

    - -
    -
    - - - - -
    #define RTC_CALR_CALW16_Msk   (0x1UL << RTC_CALR_CALW16_Pos)
    -
    -

    0x00002000

    - -
    -
    - -

    ◆ RTC_CALR_CALW16

    - -
    -
    - - - - -
    #define RTC_CALR_CALW16   RTC_CALR_CALW16_Msk
    -
    - -
    -
    - -

    ◆ RTC_CALR_CALM_Pos

    - -
    -
    - - - - -
    #define RTC_CALR_CALM_Pos   (0U)
    -
    - -
    -
    - -

    ◆ RTC_CALR_CALM_Msk

    - -
    -
    - - - - -
    #define RTC_CALR_CALM_Msk   (0x1FFUL << RTC_CALR_CALM_Pos)
    -
    -

    0x000001FF

    - -
    -
    - -

    ◆ RTC_CALR_CALM

    - -
    -
    - - - - -
    #define RTC_CALR_CALM   RTC_CALR_CALM_Msk
    -
    - -
    -
    - -

    ◆ RTC_CALR_CALM_0

    - -
    -
    - - - - -
    #define RTC_CALR_CALM_0   (0x001UL << RTC_CALR_CALM_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ RTC_CALR_CALM_1

    - -
    -
    - - - - -
    #define RTC_CALR_CALM_1   (0x002UL << RTC_CALR_CALM_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ RTC_CALR_CALM_2

    - -
    -
    - - - - -
    #define RTC_CALR_CALM_2   (0x004UL << RTC_CALR_CALM_Pos)
    -
    -

    0x00000004

    - -
    -
    - -

    ◆ RTC_CALR_CALM_3

    - -
    -
    - - - - -
    #define RTC_CALR_CALM_3   (0x008UL << RTC_CALR_CALM_Pos)
    -
    -

    0x00000008

    - -
    -
    - -

    ◆ RTC_CALR_CALM_4

    - -
    -
    - - - - -
    #define RTC_CALR_CALM_4   (0x010UL << RTC_CALR_CALM_Pos)
    -
    -

    0x00000010

    - -
    -
    - -

    ◆ RTC_CALR_CALM_5

    - -
    -
    - - - - -
    #define RTC_CALR_CALM_5   (0x020UL << RTC_CALR_CALM_Pos)
    -
    -

    0x00000020

    - -
    -
    - -

    ◆ RTC_CALR_CALM_6

    - -
    -
    - - - - -
    #define RTC_CALR_CALM_6   (0x040UL << RTC_CALR_CALM_Pos)
    -
    -

    0x00000040

    - -
    -
    - -

    ◆ RTC_CALR_CALM_7

    - -
    -
    - - - - -
    #define RTC_CALR_CALM_7   (0x080UL << RTC_CALR_CALM_Pos)
    -
    -

    0x00000080

    - -
    -
    - -

    ◆ RTC_CALR_CALM_8

    - -
    -
    - - - - -
    #define RTC_CALR_CALM_8   (0x100UL << RTC_CALR_CALM_Pos)
    -
    -

    0x00000100

    - -
    -
    - -

    ◆ RTC_TAFCR_ALARMOUTTYPE_Pos

    - -
    -
    - - - - -
    #define RTC_TAFCR_ALARMOUTTYPE_Pos   (18U)
    -
    - -
    -
    - -

    ◆ RTC_TAFCR_ALARMOUTTYPE_Msk

    - -
    -
    - - - - -
    #define RTC_TAFCR_ALARMOUTTYPE_Msk   (0x1UL << RTC_TAFCR_ALARMOUTTYPE_Pos)
    -
    -

    0x00040000

    - -
    -
    - -

    ◆ RTC_TAFCR_ALARMOUTTYPE

    - -
    -
    - - - - -
    #define RTC_TAFCR_ALARMOUTTYPE   RTC_TAFCR_ALARMOUTTYPE_Msk
    -
    - -
    -
    - -

    ◆ RTC_TAFCR_TSINSEL_Pos

    - -
    -
    - - - - -
    #define RTC_TAFCR_TSINSEL_Pos   (17U)
    -
    - -
    -
    - -

    ◆ RTC_TAFCR_TSINSEL_Msk

    - -
    -
    - - - - -
    #define RTC_TAFCR_TSINSEL_Msk   (0x1UL << RTC_TAFCR_TSINSEL_Pos)
    -
    -

    0x00020000

    - -
    -
    - -

    ◆ RTC_TAFCR_TSINSEL

    - -
    -
    - - - - -
    #define RTC_TAFCR_TSINSEL   RTC_TAFCR_TSINSEL_Msk
    -
    - -
    -
    - -

    ◆ RTC_TAFCR_TAMP1INSEL_Pos

    - -
    -
    - - - - -
    #define RTC_TAFCR_TAMP1INSEL_Pos   (16U)
    -
    - -
    -
    - -

    ◆ RTC_TAFCR_TAMP1INSEL_Msk

    - -
    -
    - - - - -
    #define RTC_TAFCR_TAMP1INSEL_Msk   (0x1UL << RTC_TAFCR_TAMP1INSEL_Pos)
    -
    -

    0x00010000

    - -
    -
    - -

    ◆ RTC_TAFCR_TAMP1INSEL

    - -
    -
    - - - - -
    #define RTC_TAFCR_TAMP1INSEL   RTC_TAFCR_TAMP1INSEL_Msk
    -
    - -
    -
    - -

    ◆ RTC_TAFCR_TAMPPUDIS_Pos

    - -
    -
    - - - - -
    #define RTC_TAFCR_TAMPPUDIS_Pos   (15U)
    -
    - -
    -
    - -

    ◆ RTC_TAFCR_TAMPPUDIS_Msk

    - -
    -
    - - - - -
    #define RTC_TAFCR_TAMPPUDIS_Msk   (0x1UL << RTC_TAFCR_TAMPPUDIS_Pos)
    -
    -

    0x00008000

    - -
    -
    - -

    ◆ RTC_TAFCR_TAMPPUDIS

    - -
    -
    - - - - -
    #define RTC_TAFCR_TAMPPUDIS   RTC_TAFCR_TAMPPUDIS_Msk
    -
    - -
    -
    - -

    ◆ RTC_TAFCR_TAMPPRCH_Pos

    - -
    -
    - - - - -
    #define RTC_TAFCR_TAMPPRCH_Pos   (13U)
    -
    - -
    -
    - -

    ◆ RTC_TAFCR_TAMPPRCH_Msk

    - -
    -
    - - - - -
    #define RTC_TAFCR_TAMPPRCH_Msk   (0x3UL << RTC_TAFCR_TAMPPRCH_Pos)
    -
    -

    0x00006000

    - -
    -
    - -

    ◆ RTC_TAFCR_TAMPPRCH

    - -
    -
    - - - - -
    #define RTC_TAFCR_TAMPPRCH   RTC_TAFCR_TAMPPRCH_Msk
    -
    - -
    -
    - -

    ◆ RTC_TAFCR_TAMPPRCH_0

    - -
    -
    - - - - -
    #define RTC_TAFCR_TAMPPRCH_0   (0x1UL << RTC_TAFCR_TAMPPRCH_Pos)
    -
    -

    0x00002000

    - -
    -
    - -

    ◆ RTC_TAFCR_TAMPPRCH_1

    - -
    -
    - - - - -
    #define RTC_TAFCR_TAMPPRCH_1   (0x2UL << RTC_TAFCR_TAMPPRCH_Pos)
    -
    -

    0x00004000

    - -
    -
    - -

    ◆ RTC_TAFCR_TAMPFLT_Pos

    - -
    -
    - - - - -
    #define RTC_TAFCR_TAMPFLT_Pos   (11U)
    -
    - -
    -
    - -

    ◆ RTC_TAFCR_TAMPFLT_Msk

    - -
    -
    - - - - -
    #define RTC_TAFCR_TAMPFLT_Msk   (0x3UL << RTC_TAFCR_TAMPFLT_Pos)
    -
    -

    0x00001800

    - -
    -
    - -

    ◆ RTC_TAFCR_TAMPFLT

    - -
    -
    - - - - -
    #define RTC_TAFCR_TAMPFLT   RTC_TAFCR_TAMPFLT_Msk
    -
    - -
    -
    - -

    ◆ RTC_TAFCR_TAMPFLT_0

    - -
    -
    - - - - -
    #define RTC_TAFCR_TAMPFLT_0   (0x1UL << RTC_TAFCR_TAMPFLT_Pos)
    -
    -

    0x00000800

    - -
    -
    - -

    ◆ RTC_TAFCR_TAMPFLT_1

    - -
    -
    - - - - -
    #define RTC_TAFCR_TAMPFLT_1   (0x2UL << RTC_TAFCR_TAMPFLT_Pos)
    -
    -

    0x00001000

    - -
    -
    - -

    ◆ RTC_TAFCR_TAMPFREQ_Pos

    - -
    -
    - - - - -
    #define RTC_TAFCR_TAMPFREQ_Pos   (8U)
    -
    - -
    -
    - -

    ◆ RTC_TAFCR_TAMPFREQ_Msk

    - -
    -
    - - - - -
    #define RTC_TAFCR_TAMPFREQ_Msk   (0x7UL << RTC_TAFCR_TAMPFREQ_Pos)
    -
    -

    0x00000700

    - -
    -
    - -

    ◆ RTC_TAFCR_TAMPFREQ

    - -
    -
    - - - - -
    #define RTC_TAFCR_TAMPFREQ   RTC_TAFCR_TAMPFREQ_Msk
    -
    - -
    -
    - -

    ◆ RTC_TAFCR_TAMPFREQ_0

    - -
    -
    - - - - -
    #define RTC_TAFCR_TAMPFREQ_0   (0x1UL << RTC_TAFCR_TAMPFREQ_Pos)
    -
    -

    0x00000100

    - -
    -
    - -

    ◆ RTC_TAFCR_TAMPFREQ_1

    - -
    -
    - - - - -
    #define RTC_TAFCR_TAMPFREQ_1   (0x2UL << RTC_TAFCR_TAMPFREQ_Pos)
    -
    -

    0x00000200

    - -
    -
    - -

    ◆ RTC_TAFCR_TAMPFREQ_2

    - -
    -
    - - - - -
    #define RTC_TAFCR_TAMPFREQ_2   (0x4UL << RTC_TAFCR_TAMPFREQ_Pos)
    -
    -

    0x00000400

    - -
    -
    - -

    ◆ RTC_TAFCR_TAMPTS_Pos

    - -
    -
    - - - - -
    #define RTC_TAFCR_TAMPTS_Pos   (7U)
    -
    - -
    -
    - -

    ◆ RTC_TAFCR_TAMPTS_Msk

    - -
    -
    - - - - -
    #define RTC_TAFCR_TAMPTS_Msk   (0x1UL << RTC_TAFCR_TAMPTS_Pos)
    -
    -

    0x00000080

    - -
    -
    - -

    ◆ RTC_TAFCR_TAMPTS

    - -
    -
    - - - - -
    #define RTC_TAFCR_TAMPTS   RTC_TAFCR_TAMPTS_Msk
    -
    - -
    -
    - -

    ◆ RTC_TAFCR_TAMP2TRG_Pos

    - -
    -
    - - - - -
    #define RTC_TAFCR_TAMP2TRG_Pos   (4U)
    -
    - -
    -
    - -

    ◆ RTC_TAFCR_TAMP2TRG_Msk

    - -
    -
    - - - - -
    #define RTC_TAFCR_TAMP2TRG_Msk   (0x1UL << RTC_TAFCR_TAMP2TRG_Pos)
    -
    -

    0x00000010

    - -
    -
    - -

    ◆ RTC_TAFCR_TAMP2TRG

    - -
    -
    - - - - -
    #define RTC_TAFCR_TAMP2TRG   RTC_TAFCR_TAMP2TRG_Msk
    -
    - -
    -
    - -

    ◆ RTC_TAFCR_TAMP2E_Pos

    - -
    -
    - - - - -
    #define RTC_TAFCR_TAMP2E_Pos   (3U)
    -
    - -
    -
    - -

    ◆ RTC_TAFCR_TAMP2E_Msk

    - -
    -
    - - - - -
    #define RTC_TAFCR_TAMP2E_Msk   (0x1UL << RTC_TAFCR_TAMP2E_Pos)
    -
    -

    0x00000008

    - -
    -
    - -

    ◆ RTC_TAFCR_TAMP2E

    - -
    -
    - - - - -
    #define RTC_TAFCR_TAMP2E   RTC_TAFCR_TAMP2E_Msk
    -
    - -
    -
    - -

    ◆ RTC_TAFCR_TAMPIE_Pos

    - -
    -
    - - - - -
    #define RTC_TAFCR_TAMPIE_Pos   (2U)
    -
    - -
    -
    - -

    ◆ RTC_TAFCR_TAMPIE_Msk

    - -
    -
    - - - - -
    #define RTC_TAFCR_TAMPIE_Msk   (0x1UL << RTC_TAFCR_TAMPIE_Pos)
    -
    -

    0x00000004

    - -
    -
    - -

    ◆ RTC_TAFCR_TAMPIE

    - -
    -
    - - - - -
    #define RTC_TAFCR_TAMPIE   RTC_TAFCR_TAMPIE_Msk
    -
    - -
    -
    - -

    ◆ RTC_TAFCR_TAMP1TRG_Pos

    - -
    -
    - - - - -
    #define RTC_TAFCR_TAMP1TRG_Pos   (1U)
    -
    - -
    -
    - -

    ◆ RTC_TAFCR_TAMP1TRG_Msk

    - -
    -
    - - - - -
    #define RTC_TAFCR_TAMP1TRG_Msk   (0x1UL << RTC_TAFCR_TAMP1TRG_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ RTC_TAFCR_TAMP1TRG

    - -
    -
    - - - - -
    #define RTC_TAFCR_TAMP1TRG   RTC_TAFCR_TAMP1TRG_Msk
    -
    - -
    -
    - -

    ◆ RTC_TAFCR_TAMP1E_Pos

    - -
    -
    - - - - -
    #define RTC_TAFCR_TAMP1E_Pos   (0U)
    -
    - -
    -
    - -

    ◆ RTC_TAFCR_TAMP1E_Msk

    - -
    -
    - - - - -
    #define RTC_TAFCR_TAMP1E_Msk   (0x1UL << RTC_TAFCR_TAMP1E_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ RTC_TAFCR_TAMP1E

    - -
    -
    - - - - -
    #define RTC_TAFCR_TAMP1E   RTC_TAFCR_TAMP1E_Msk
    -
    - -
    -
    - -

    ◆ RTC_TAFCR_TAMPINSEL

    - -
    -
    - - - - -
    #define RTC_TAFCR_TAMPINSEL   RTC_TAFCR_TAMP1INSEL
    -
    - -
    -
    - -

    ◆ RTC_ALRMASSR_MASKSS_Pos

    - -
    -
    - - - - -
    #define RTC_ALRMASSR_MASKSS_Pos   (24U)
    -
    - -
    -
    - -

    ◆ RTC_ALRMASSR_MASKSS_Msk

    - -
    -
    - - - - -
    #define RTC_ALRMASSR_MASKSS_Msk   (0xFUL << RTC_ALRMASSR_MASKSS_Pos)
    -
    -

    0x0F000000

    - -
    -
    - -

    ◆ RTC_ALRMASSR_MASKSS

    - -
    -
    - - - - -
    #define RTC_ALRMASSR_MASKSS   RTC_ALRMASSR_MASKSS_Msk
    -
    - -
    -
    - -

    ◆ RTC_ALRMASSR_MASKSS_0

    - -
    -
    - - - - -
    #define RTC_ALRMASSR_MASKSS_0   (0x1UL << RTC_ALRMASSR_MASKSS_Pos)
    -
    -

    0x01000000

    - -
    -
    - -

    ◆ RTC_ALRMASSR_MASKSS_1

    - -
    -
    - - - - -
    #define RTC_ALRMASSR_MASKSS_1   (0x2UL << RTC_ALRMASSR_MASKSS_Pos)
    -
    -

    0x02000000

    - -
    -
    - -

    ◆ RTC_ALRMASSR_MASKSS_2

    - -
    -
    - - - - -
    #define RTC_ALRMASSR_MASKSS_2   (0x4UL << RTC_ALRMASSR_MASKSS_Pos)
    -
    -

    0x04000000

    - -
    -
    - -

    ◆ RTC_ALRMASSR_MASKSS_3

    - -
    -
    - - - - -
    #define RTC_ALRMASSR_MASKSS_3   (0x8UL << RTC_ALRMASSR_MASKSS_Pos)
    -
    -

    0x08000000

    - -
    -
    - -

    ◆ RTC_ALRMASSR_SS_Pos

    - -
    -
    - - - - -
    #define RTC_ALRMASSR_SS_Pos   (0U)
    -
    - -
    -
    - -

    ◆ RTC_ALRMASSR_SS_Msk

    - -
    -
    - - - - -
    #define RTC_ALRMASSR_SS_Msk   (0x7FFFUL << RTC_ALRMASSR_SS_Pos)
    -
    -

    0x00007FFF

    - -
    -
    - -

    ◆ RTC_ALRMASSR_SS

    - -
    -
    - - - - -
    #define RTC_ALRMASSR_SS   RTC_ALRMASSR_SS_Msk
    -
    - -
    -
    - -

    ◆ RTC_ALRMBSSR_MASKSS_Pos

    - -
    -
    - - - - -
    #define RTC_ALRMBSSR_MASKSS_Pos   (24U)
    -
    - -
    -
    - -

    ◆ RTC_ALRMBSSR_MASKSS_Msk

    - -
    -
    - - - - -
    #define RTC_ALRMBSSR_MASKSS_Msk   (0xFUL << RTC_ALRMBSSR_MASKSS_Pos)
    -
    -

    0x0F000000

    - -
    -
    - -

    ◆ RTC_ALRMBSSR_MASKSS

    - -
    -
    - - - - -
    #define RTC_ALRMBSSR_MASKSS   RTC_ALRMBSSR_MASKSS_Msk
    -
    - -
    -
    - -

    ◆ RTC_ALRMBSSR_MASKSS_0

    - -
    -
    - - - - -
    #define RTC_ALRMBSSR_MASKSS_0   (0x1UL << RTC_ALRMBSSR_MASKSS_Pos)
    -
    -

    0x01000000

    - -
    -
    - -

    ◆ RTC_ALRMBSSR_MASKSS_1

    - -
    -
    - - - - -
    #define RTC_ALRMBSSR_MASKSS_1   (0x2UL << RTC_ALRMBSSR_MASKSS_Pos)
    -
    -

    0x02000000

    - -
    -
    - -

    ◆ RTC_ALRMBSSR_MASKSS_2

    - -
    -
    - - - - -
    #define RTC_ALRMBSSR_MASKSS_2   (0x4UL << RTC_ALRMBSSR_MASKSS_Pos)
    -
    -

    0x04000000

    - -
    -
    - -

    ◆ RTC_ALRMBSSR_MASKSS_3

    - -
    -
    - - - - -
    #define RTC_ALRMBSSR_MASKSS_3   (0x8UL << RTC_ALRMBSSR_MASKSS_Pos)
    -
    -

    0x08000000

    - -
    -
    - -

    ◆ RTC_ALRMBSSR_SS_Pos

    - -
    -
    - - - - -
    #define RTC_ALRMBSSR_SS_Pos   (0U)
    -
    - -
    -
    - -

    ◆ RTC_ALRMBSSR_SS_Msk

    - -
    -
    - - - - -
    #define RTC_ALRMBSSR_SS_Msk   (0x7FFFUL << RTC_ALRMBSSR_SS_Pos)
    -
    -

    0x00007FFF

    - -
    -
    - -

    ◆ RTC_ALRMBSSR_SS

    - -
    -
    - - - - -
    #define RTC_ALRMBSSR_SS   RTC_ALRMBSSR_SS_Msk
    -
    - -
    -
    - -

    ◆ RTC_BKP0R_Pos

    - -
    -
    - - - - -
    #define RTC_BKP0R_Pos   (0U)
    -
    - -
    -
    - -

    ◆ RTC_BKP0R_Msk

    - -
    -
    - - - - -
    #define RTC_BKP0R_Msk   (0xFFFFFFFFUL << RTC_BKP0R_Pos)
    -
    -

    0xFFFFFFFF

    - -
    -
    - -

    ◆ RTC_BKP0R

    - -
    -
    - - - - -
    #define RTC_BKP0R   RTC_BKP0R_Msk
    -
    - -
    -
    - -

    ◆ RTC_BKP1R_Pos

    - -
    -
    - - - - -
    #define RTC_BKP1R_Pos   (0U)
    -
    - -
    -
    - -

    ◆ RTC_BKP1R_Msk

    - -
    -
    - - - - -
    #define RTC_BKP1R_Msk   (0xFFFFFFFFUL << RTC_BKP1R_Pos)
    -
    -

    0xFFFFFFFF

    - -
    -
    - -

    ◆ RTC_BKP1R

    - -
    -
    - - - - -
    #define RTC_BKP1R   RTC_BKP1R_Msk
    -
    - -
    -
    - -

    ◆ RTC_BKP2R_Pos

    - -
    -
    - - - - -
    #define RTC_BKP2R_Pos   (0U)
    -
    - -
    -
    - -

    ◆ RTC_BKP2R_Msk

    - -
    -
    - - - - -
    #define RTC_BKP2R_Msk   (0xFFFFFFFFUL << RTC_BKP2R_Pos)
    -
    -

    0xFFFFFFFF

    - -
    -
    - -

    ◆ RTC_BKP2R

    - -
    -
    - - - - -
    #define RTC_BKP2R   RTC_BKP2R_Msk
    -
    - -
    -
    - -

    ◆ RTC_BKP3R_Pos

    - -
    -
    - - - - -
    #define RTC_BKP3R_Pos   (0U)
    -
    - -
    -
    - -

    ◆ RTC_BKP3R_Msk

    - -
    -
    - - - - -
    #define RTC_BKP3R_Msk   (0xFFFFFFFFUL << RTC_BKP3R_Pos)
    -
    -

    0xFFFFFFFF

    - -
    -
    - -

    ◆ RTC_BKP3R

    - -
    -
    - - - - -
    #define RTC_BKP3R   RTC_BKP3R_Msk
    -
    - -
    -
    - -

    ◆ RTC_BKP4R_Pos

    - -
    -
    - - - - -
    #define RTC_BKP4R_Pos   (0U)
    -
    - -
    -
    - -

    ◆ RTC_BKP4R_Msk

    - -
    -
    - - - - -
    #define RTC_BKP4R_Msk   (0xFFFFFFFFUL << RTC_BKP4R_Pos)
    -
    -

    0xFFFFFFFF

    - -
    -
    - -

    ◆ RTC_BKP4R

    - -
    -
    - - - - -
    #define RTC_BKP4R   RTC_BKP4R_Msk
    -
    - -
    -
    - -

    ◆ RTC_BKP5R_Pos

    - -
    -
    - - - - -
    #define RTC_BKP5R_Pos   (0U)
    -
    - -
    -
    - -

    ◆ RTC_BKP5R_Msk

    - -
    -
    - - - - -
    #define RTC_BKP5R_Msk   (0xFFFFFFFFUL << RTC_BKP5R_Pos)
    -
    -

    0xFFFFFFFF

    - -
    -
    - -

    ◆ RTC_BKP5R

    - -
    -
    - - - - -
    #define RTC_BKP5R   RTC_BKP5R_Msk
    -
    - -
    -
    - -

    ◆ RTC_BKP6R_Pos

    - -
    -
    - - - - -
    #define RTC_BKP6R_Pos   (0U)
    -
    - -
    -
    - -

    ◆ RTC_BKP6R_Msk

    - -
    -
    - - - - -
    #define RTC_BKP6R_Msk   (0xFFFFFFFFUL << RTC_BKP6R_Pos)
    -
    -

    0xFFFFFFFF

    - -
    -
    - -

    ◆ RTC_BKP6R

    - -
    -
    - - - - -
    #define RTC_BKP6R   RTC_BKP6R_Msk
    -
    - -
    -
    - -

    ◆ RTC_BKP7R_Pos

    - -
    -
    - - - - -
    #define RTC_BKP7R_Pos   (0U)
    -
    - -
    -
    - -

    ◆ RTC_BKP7R_Msk

    - -
    -
    - - - - -
    #define RTC_BKP7R_Msk   (0xFFFFFFFFUL << RTC_BKP7R_Pos)
    -
    -

    0xFFFFFFFF

    - -
    -
    - -

    ◆ RTC_BKP7R

    - -
    -
    - - - - -
    #define RTC_BKP7R   RTC_BKP7R_Msk
    -
    - -
    -
    - -

    ◆ RTC_BKP8R_Pos

    - -
    -
    - - - - -
    #define RTC_BKP8R_Pos   (0U)
    -
    - -
    -
    - -

    ◆ RTC_BKP8R_Msk

    - -
    -
    - - - - -
    #define RTC_BKP8R_Msk   (0xFFFFFFFFUL << RTC_BKP8R_Pos)
    -
    -

    0xFFFFFFFF

    - -
    -
    - -

    ◆ RTC_BKP8R

    - -
    -
    - - - - -
    #define RTC_BKP8R   RTC_BKP8R_Msk
    -
    - -
    -
    - -

    ◆ RTC_BKP9R_Pos

    - -
    -
    - - - - -
    #define RTC_BKP9R_Pos   (0U)
    -
    - -
    -
    - -

    ◆ RTC_BKP9R_Msk

    - -
    -
    - - - - -
    #define RTC_BKP9R_Msk   (0xFFFFFFFFUL << RTC_BKP9R_Pos)
    -
    -

    0xFFFFFFFF

    - -
    -
    - -

    ◆ RTC_BKP9R

    - -
    -
    - - - - -
    #define RTC_BKP9R   RTC_BKP9R_Msk
    -
    - -
    -
    - -

    ◆ RTC_BKP10R_Pos

    - -
    -
    - - - - -
    #define RTC_BKP10R_Pos   (0U)
    -
    - -
    -
    - -

    ◆ RTC_BKP10R_Msk

    - -
    -
    - - - - -
    #define RTC_BKP10R_Msk   (0xFFFFFFFFUL << RTC_BKP10R_Pos)
    -
    -

    0xFFFFFFFF

    - -
    -
    - -

    ◆ RTC_BKP10R

    - -
    -
    - - - - -
    #define RTC_BKP10R   RTC_BKP10R_Msk
    -
    - -
    -
    - -

    ◆ RTC_BKP11R_Pos

    - -
    -
    - - - - -
    #define RTC_BKP11R_Pos   (0U)
    -
    - -
    -
    - -

    ◆ RTC_BKP11R_Msk

    - -
    -
    - - - - -
    #define RTC_BKP11R_Msk   (0xFFFFFFFFUL << RTC_BKP11R_Pos)
    -
    -

    0xFFFFFFFF

    - -
    -
    - -

    ◆ RTC_BKP11R

    - -
    -
    - - - - -
    #define RTC_BKP11R   RTC_BKP11R_Msk
    -
    - -
    -
    - -

    ◆ RTC_BKP12R_Pos

    - -
    -
    - - - - -
    #define RTC_BKP12R_Pos   (0U)
    -
    - -
    -
    - -

    ◆ RTC_BKP12R_Msk

    - -
    -
    - - - - -
    #define RTC_BKP12R_Msk   (0xFFFFFFFFUL << RTC_BKP12R_Pos)
    -
    -

    0xFFFFFFFF

    - -
    -
    - -

    ◆ RTC_BKP12R

    - -
    -
    - - - - -
    #define RTC_BKP12R   RTC_BKP12R_Msk
    -
    - -
    -
    - -

    ◆ RTC_BKP13R_Pos

    - -
    -
    - - - - -
    #define RTC_BKP13R_Pos   (0U)
    -
    - -
    -
    - -

    ◆ RTC_BKP13R_Msk

    - -
    -
    - - - - -
    #define RTC_BKP13R_Msk   (0xFFFFFFFFUL << RTC_BKP13R_Pos)
    -
    -

    0xFFFFFFFF

    - -
    -
    - -

    ◆ RTC_BKP13R

    - -
    -
    - - - - -
    #define RTC_BKP13R   RTC_BKP13R_Msk
    -
    - -
    -
    - -

    ◆ RTC_BKP14R_Pos

    - -
    -
    - - - - -
    #define RTC_BKP14R_Pos   (0U)
    -
    - -
    -
    - -

    ◆ RTC_BKP14R_Msk

    - -
    -
    - - - - -
    #define RTC_BKP14R_Msk   (0xFFFFFFFFUL << RTC_BKP14R_Pos)
    -
    -

    0xFFFFFFFF

    - -
    -
    - -

    ◆ RTC_BKP14R

    - -
    -
    - - - - -
    #define RTC_BKP14R   RTC_BKP14R_Msk
    -
    - -
    -
    - -

    ◆ RTC_BKP15R_Pos

    - -
    -
    - - - - -
    #define RTC_BKP15R_Pos   (0U)
    -
    - -
    -
    - -

    ◆ RTC_BKP15R_Msk

    - -
    -
    - - - - -
    #define RTC_BKP15R_Msk   (0xFFFFFFFFUL << RTC_BKP15R_Pos)
    -
    -

    0xFFFFFFFF

    - -
    -
    - -

    ◆ RTC_BKP15R

    - -
    -
    - - - - -
    #define RTC_BKP15R   RTC_BKP15R_Msk
    -
    - -
    -
    - -

    ◆ RTC_BKP16R_Pos

    - -
    -
    - - - - -
    #define RTC_BKP16R_Pos   (0U)
    -
    - -
    -
    - -

    ◆ RTC_BKP16R_Msk

    - -
    -
    - - - - -
    #define RTC_BKP16R_Msk   (0xFFFFFFFFUL << RTC_BKP16R_Pos)
    -
    -

    0xFFFFFFFF

    - -
    -
    - -

    ◆ RTC_BKP16R

    - -
    -
    - - - - -
    #define RTC_BKP16R   RTC_BKP16R_Msk
    -
    - -
    -
    - -

    ◆ RTC_BKP17R_Pos

    - -
    -
    - - - - -
    #define RTC_BKP17R_Pos   (0U)
    -
    - -
    -
    - -

    ◆ RTC_BKP17R_Msk

    - -
    -
    - - - - -
    #define RTC_BKP17R_Msk   (0xFFFFFFFFUL << RTC_BKP17R_Pos)
    -
    -

    0xFFFFFFFF

    - -
    -
    - -

    ◆ RTC_BKP17R

    - -
    -
    - - - - -
    #define RTC_BKP17R   RTC_BKP17R_Msk
    -
    - -
    -
    - -

    ◆ RTC_BKP18R_Pos

    - -
    -
    - - - - -
    #define RTC_BKP18R_Pos   (0U)
    -
    - -
    -
    - -

    ◆ RTC_BKP18R_Msk

    - -
    -
    - - - - -
    #define RTC_BKP18R_Msk   (0xFFFFFFFFUL << RTC_BKP18R_Pos)
    -
    -

    0xFFFFFFFF

    - -
    -
    - -

    ◆ RTC_BKP18R

    - -
    -
    - - - - -
    #define RTC_BKP18R   RTC_BKP18R_Msk
    -
    - -
    -
    - -

    ◆ RTC_BKP19R_Pos

    - -
    -
    - - - - -
    #define RTC_BKP19R_Pos   (0U)
    -
    - -
    -
    - -

    ◆ RTC_BKP19R_Msk

    - -
    -
    - - - - -
    #define RTC_BKP19R_Msk   (0xFFFFFFFFUL << RTC_BKP19R_Pos)
    -
    -

    0xFFFFFFFF

    - -
    -
    - -

    ◆ RTC_BKP19R

    - -
    -
    - - - - -
    #define RTC_BKP19R   RTC_BKP19R_Msk
    -
    - -
    -
    - -

    ◆ RTC_BKP_NUMBER

    - -
    -
    - - - - -
    #define RTC_BKP_NUMBER   0x000000014U
    -
    - -
    -
    - -

    ◆ SDIO_POWER_PWRCTRL_Pos

    - -
    -
    - - - - -
    #define SDIO_POWER_PWRCTRL_Pos   (0U)
    -
    - -
    -
    - -

    ◆ SDIO_POWER_PWRCTRL_Msk

    - -
    -
    - - - - -
    #define SDIO_POWER_PWRCTRL_Msk   (0x3UL << SDIO_POWER_PWRCTRL_Pos)
    -
    -

    0x00000003

    - -
    -
    - -

    ◆ SDIO_POWER_PWRCTRL

    - -
    -
    - - - - -
    #define SDIO_POWER_PWRCTRL   SDIO_POWER_PWRCTRL_Msk
    -
    -

    PWRCTRL[1:0] bits (Power supply control bits)

    - -
    -
    - -

    ◆ SDIO_POWER_PWRCTRL_0

    - -
    -
    - - - - -
    #define SDIO_POWER_PWRCTRL_0   (0x1UL << SDIO_POWER_PWRCTRL_Pos)
    -
    -

    0x01

    - -
    -
    - -

    ◆ SDIO_POWER_PWRCTRL_1

    - -
    -
    - - - - -
    #define SDIO_POWER_PWRCTRL_1   (0x2UL << SDIO_POWER_PWRCTRL_Pos)
    -
    -

    0x02

    - -
    -
    - -

    ◆ SDIO_CLKCR_CLKDIV_Pos

    - -
    -
    - - - - -
    #define SDIO_CLKCR_CLKDIV_Pos   (0U)
    -
    - -
    -
    - -

    ◆ SDIO_CLKCR_CLKDIV_Msk

    - -
    -
    - - - - -
    #define SDIO_CLKCR_CLKDIV_Msk   (0xFFUL << SDIO_CLKCR_CLKDIV_Pos)
    -
    -

    0x000000FF

    - -
    -
    - -

    ◆ SDIO_CLKCR_CLKDIV

    - -
    -
    - - - - -
    #define SDIO_CLKCR_CLKDIV   SDIO_CLKCR_CLKDIV_Msk
    -
    -

    Clock divide factor
    -

    - -
    -
    - -

    ◆ SDIO_CLKCR_CLKEN_Pos

    - -
    -
    - - - - -
    #define SDIO_CLKCR_CLKEN_Pos   (8U)
    -
    - -
    -
    - -

    ◆ SDIO_CLKCR_CLKEN_Msk

    - -
    -
    - - - - -
    #define SDIO_CLKCR_CLKEN_Msk   (0x1UL << SDIO_CLKCR_CLKEN_Pos)
    -
    -

    0x00000100

    - -
    -
    - -

    ◆ SDIO_CLKCR_CLKEN

    - -
    -
    - - - - -
    #define SDIO_CLKCR_CLKEN   SDIO_CLKCR_CLKEN_Msk
    -
    -

    Clock enable bit
    -

    - -
    -
    - -

    ◆ SDIO_CLKCR_PWRSAV_Pos

    - -
    -
    - - - - -
    #define SDIO_CLKCR_PWRSAV_Pos   (9U)
    -
    - -
    -
    - -

    ◆ SDIO_CLKCR_PWRSAV_Msk

    - -
    -
    - - - - -
    #define SDIO_CLKCR_PWRSAV_Msk   (0x1UL << SDIO_CLKCR_PWRSAV_Pos)
    -
    -

    0x00000200

    - -
    -
    - -

    ◆ SDIO_CLKCR_PWRSAV

    - -
    -
    - - - - -
    #define SDIO_CLKCR_PWRSAV   SDIO_CLKCR_PWRSAV_Msk
    -
    -

    Power saving configuration bit
    -

    - -
    -
    - -

    ◆ SDIO_CLKCR_BYPASS_Pos

    - -
    -
    - - - - -
    #define SDIO_CLKCR_BYPASS_Pos   (10U)
    -
    - -
    -
    - -

    ◆ SDIO_CLKCR_BYPASS_Msk

    - -
    -
    - - - - -
    #define SDIO_CLKCR_BYPASS_Msk   (0x1UL << SDIO_CLKCR_BYPASS_Pos)
    -
    -

    0x00000400

    - -
    -
    - -

    ◆ SDIO_CLKCR_BYPASS

    - -
    -
    - - - - -
    #define SDIO_CLKCR_BYPASS   SDIO_CLKCR_BYPASS_Msk
    -
    -

    Clock divider bypass enable bit

    - -
    -
    - -

    ◆ SDIO_CLKCR_WIDBUS_Pos

    - -
    -
    - - - - -
    #define SDIO_CLKCR_WIDBUS_Pos   (11U)
    -
    - -
    -
    - -

    ◆ SDIO_CLKCR_WIDBUS_Msk

    - -
    -
    - - - - -
    #define SDIO_CLKCR_WIDBUS_Msk   (0x3UL << SDIO_CLKCR_WIDBUS_Pos)
    -
    -

    0x00001800

    - -
    -
    - -

    ◆ SDIO_CLKCR_WIDBUS

    - -
    -
    - - - - -
    #define SDIO_CLKCR_WIDBUS   SDIO_CLKCR_WIDBUS_Msk
    -
    -

    WIDBUS[1:0] bits (Wide bus mode enable bit)

    - -
    -
    - -

    ◆ SDIO_CLKCR_WIDBUS_0

    - -
    -
    - - - - -
    #define SDIO_CLKCR_WIDBUS_0   (0x1UL << SDIO_CLKCR_WIDBUS_Pos)
    -
    -

    0x0800

    - -
    -
    - -

    ◆ SDIO_CLKCR_WIDBUS_1

    - -
    -
    - - - - -
    #define SDIO_CLKCR_WIDBUS_1   (0x2UL << SDIO_CLKCR_WIDBUS_Pos)
    -
    -

    0x1000

    - -
    -
    - -

    ◆ SDIO_CLKCR_NEGEDGE_Pos

    - -
    -
    - - - - -
    #define SDIO_CLKCR_NEGEDGE_Pos   (13U)
    -
    - -
    -
    - -

    ◆ SDIO_CLKCR_NEGEDGE_Msk

    - -
    -
    - - - - -
    #define SDIO_CLKCR_NEGEDGE_Msk   (0x1UL << SDIO_CLKCR_NEGEDGE_Pos)
    -
    -

    0x00002000

    - -
    -
    - -

    ◆ SDIO_CLKCR_NEGEDGE

    - -
    -
    - - - - -
    #define SDIO_CLKCR_NEGEDGE   SDIO_CLKCR_NEGEDGE_Msk
    -
    -

    SDIO_CK dephasing selection bit

    - -
    -
    - -

    ◆ SDIO_CLKCR_HWFC_EN_Pos

    - -
    -
    - - - - -
    #define SDIO_CLKCR_HWFC_EN_Pos   (14U)
    -
    - -
    -
    - -

    ◆ SDIO_CLKCR_HWFC_EN_Msk

    - -
    -
    - - - - -
    #define SDIO_CLKCR_HWFC_EN_Msk   (0x1UL << SDIO_CLKCR_HWFC_EN_Pos)
    -
    -

    0x00004000

    - -
    -
    - -

    ◆ SDIO_CLKCR_HWFC_EN

    - -
    -
    - - - - -
    #define SDIO_CLKCR_HWFC_EN   SDIO_CLKCR_HWFC_EN_Msk
    -
    -

    HW Flow Control enable
    -

    - -
    -
    - -

    ◆ SDIO_ARG_CMDARG_Pos

    - -
    -
    - - - - -
    #define SDIO_ARG_CMDARG_Pos   (0U)
    -
    - -
    -
    - -

    ◆ SDIO_ARG_CMDARG_Msk

    - -
    -
    - - - - -
    #define SDIO_ARG_CMDARG_Msk   (0xFFFFFFFFUL << SDIO_ARG_CMDARG_Pos)
    -
    -

    0xFFFFFFFF

    - -
    -
    - -

    ◆ SDIO_ARG_CMDARG

    - -
    -
    - - - - -
    #define SDIO_ARG_CMDARG   SDIO_ARG_CMDARG_Msk
    -
    -

    Command argument

    - -
    -
    - -

    ◆ SDIO_CMD_CMDINDEX_Pos

    - -
    -
    - - - - -
    #define SDIO_CMD_CMDINDEX_Pos   (0U)
    -
    - -
    -
    - -

    ◆ SDIO_CMD_CMDINDEX_Msk

    - -
    -
    - - - - -
    #define SDIO_CMD_CMDINDEX_Msk   (0x3FUL << SDIO_CMD_CMDINDEX_Pos)
    -
    -

    0x0000003F

    - -
    -
    - -

    ◆ SDIO_CMD_CMDINDEX

    - -
    -
    - - - - -
    #define SDIO_CMD_CMDINDEX   SDIO_CMD_CMDINDEX_Msk
    -
    -

    Command Index
    -

    - -
    -
    - -

    ◆ SDIO_CMD_WAITRESP_Pos

    - -
    -
    - - - - -
    #define SDIO_CMD_WAITRESP_Pos   (6U)
    -
    - -
    -
    - -

    ◆ SDIO_CMD_WAITRESP_Msk

    - -
    -
    - - - - -
    #define SDIO_CMD_WAITRESP_Msk   (0x3UL << SDIO_CMD_WAITRESP_Pos)
    -
    -

    0x000000C0

    - -
    -
    - -

    ◆ SDIO_CMD_WAITRESP

    - -
    -
    - - - - -
    #define SDIO_CMD_WAITRESP   SDIO_CMD_WAITRESP_Msk
    -
    -

    WAITRESP[1:0] bits (Wait for response bits)

    - -
    -
    - -

    ◆ SDIO_CMD_WAITRESP_0

    - -
    -
    - - - - -
    #define SDIO_CMD_WAITRESP_0   (0x1UL << SDIO_CMD_WAITRESP_Pos)
    -
    -

    0x0040

    - -
    -
    - -

    ◆ SDIO_CMD_WAITRESP_1

    - -
    -
    - - - - -
    #define SDIO_CMD_WAITRESP_1   (0x2UL << SDIO_CMD_WAITRESP_Pos)
    -
    -

    0x0080

    - -
    -
    - -

    ◆ SDIO_CMD_WAITINT_Pos

    - -
    -
    - - - - -
    #define SDIO_CMD_WAITINT_Pos   (8U)
    -
    - -
    -
    - -

    ◆ SDIO_CMD_WAITINT_Msk

    - -
    -
    - - - - -
    #define SDIO_CMD_WAITINT_Msk   (0x1UL << SDIO_CMD_WAITINT_Pos)
    -
    -

    0x00000100

    - -
    -
    - -

    ◆ SDIO_CMD_WAITINT

    - -
    -
    - - - - -
    #define SDIO_CMD_WAITINT   SDIO_CMD_WAITINT_Msk
    -
    -

    CPSM Waits for Interrupt Request
    -

    - -
    -
    - -

    ◆ SDIO_CMD_WAITPEND_Pos

    - -
    -
    - - - - -
    #define SDIO_CMD_WAITPEND_Pos   (9U)
    -
    - -
    -
    - -

    ◆ SDIO_CMD_WAITPEND_Msk

    - -
    -
    - - - - -
    #define SDIO_CMD_WAITPEND_Msk   (0x1UL << SDIO_CMD_WAITPEND_Pos)
    -
    -

    0x00000200

    - -
    -
    - -

    ◆ SDIO_CMD_WAITPEND

    - -
    -
    - - - - -
    #define SDIO_CMD_WAITPEND   SDIO_CMD_WAITPEND_Msk
    -
    -

    CPSM Waits for ends of data transfer (CmdPend internal signal)

    - -
    -
    - -

    ◆ SDIO_CMD_CPSMEN_Pos

    - -
    -
    - - - - -
    #define SDIO_CMD_CPSMEN_Pos   (10U)
    -
    - -
    -
    - -

    ◆ SDIO_CMD_CPSMEN_Msk

    - -
    -
    - - - - -
    #define SDIO_CMD_CPSMEN_Msk   (0x1UL << SDIO_CMD_CPSMEN_Pos)
    -
    -

    0x00000400

    - -
    -
    - -

    ◆ SDIO_CMD_CPSMEN

    - -
    -
    - - - - -
    #define SDIO_CMD_CPSMEN   SDIO_CMD_CPSMEN_Msk
    -
    -

    Command path state machine (CPSM) Enable bit
    -

    - -
    -
    - -

    ◆ SDIO_CMD_SDIOSUSPEND_Pos

    - -
    -
    - - - - -
    #define SDIO_CMD_SDIOSUSPEND_Pos   (11U)
    -
    - -
    -
    - -

    ◆ SDIO_CMD_SDIOSUSPEND_Msk

    - -
    -
    - - - - -
    #define SDIO_CMD_SDIOSUSPEND_Msk   (0x1UL << SDIO_CMD_SDIOSUSPEND_Pos)
    -
    -

    0x00000800

    - -
    -
    - -

    ◆ SDIO_CMD_SDIOSUSPEND

    - -
    -
    - - - - -
    #define SDIO_CMD_SDIOSUSPEND   SDIO_CMD_SDIOSUSPEND_Msk
    -
    -

    SD I/O suspend command
    -

    - -
    -
    - -

    ◆ SDIO_CMD_ENCMDCOMPL_Pos

    - -
    -
    - - - - -
    #define SDIO_CMD_ENCMDCOMPL_Pos   (12U)
    -
    - -
    -
    - -

    ◆ SDIO_CMD_ENCMDCOMPL_Msk

    - -
    -
    - - - - -
    #define SDIO_CMD_ENCMDCOMPL_Msk   (0x1UL << SDIO_CMD_ENCMDCOMPL_Pos)
    -
    -

    0x00001000

    - -
    -
    - -

    ◆ SDIO_CMD_ENCMDCOMPL

    - -
    -
    - - - - -
    #define SDIO_CMD_ENCMDCOMPL   SDIO_CMD_ENCMDCOMPL_Msk
    -
    -

    Enable CMD completion
    -

    - -
    -
    - -

    ◆ SDIO_CMD_NIEN_Pos

    - -
    -
    - - - - -
    #define SDIO_CMD_NIEN_Pos   (13U)
    -
    - -
    -
    - -

    ◆ SDIO_CMD_NIEN_Msk

    - -
    -
    - - - - -
    #define SDIO_CMD_NIEN_Msk   (0x1UL << SDIO_CMD_NIEN_Pos)
    -
    -

    0x00002000

    - -
    -
    - -

    ◆ SDIO_CMD_NIEN

    - -
    -
    - - - - -
    #define SDIO_CMD_NIEN   SDIO_CMD_NIEN_Msk
    -
    -

    Not Interrupt Enable
    -

    - -
    -
    - -

    ◆ SDIO_CMD_CEATACMD_Pos

    - -
    -
    - - - - -
    #define SDIO_CMD_CEATACMD_Pos   (14U)
    -
    - -
    -
    - -

    ◆ SDIO_CMD_CEATACMD_Msk

    - -
    -
    - - - - -
    #define SDIO_CMD_CEATACMD_Msk   (0x1UL << SDIO_CMD_CEATACMD_Pos)
    -
    -

    0x00004000

    - -
    -
    - -

    ◆ SDIO_CMD_CEATACMD

    - -
    -
    - - - - -
    #define SDIO_CMD_CEATACMD   SDIO_CMD_CEATACMD_Msk
    -
    -

    CE-ATA command
    -

    - -
    -
    - -

    ◆ SDIO_RESPCMD_RESPCMD_Pos

    - -
    -
    - - - - -
    #define SDIO_RESPCMD_RESPCMD_Pos   (0U)
    -
    - -
    -
    - -

    ◆ SDIO_RESPCMD_RESPCMD_Msk

    - -
    -
    - - - - -
    #define SDIO_RESPCMD_RESPCMD_Msk   (0x3FUL << SDIO_RESPCMD_RESPCMD_Pos)
    -
    -

    0x0000003F

    - -
    -
    - -

    ◆ SDIO_RESPCMD_RESPCMD

    - -
    -
    - - - - -
    #define SDIO_RESPCMD_RESPCMD   SDIO_RESPCMD_RESPCMD_Msk
    -
    -

    Response command index

    - -
    -
    - -

    ◆ SDIO_RESP0_CARDSTATUS0_Pos

    - -
    -
    - - - - -
    #define SDIO_RESP0_CARDSTATUS0_Pos   (0U)
    -
    - -
    -
    - -

    ◆ SDIO_RESP0_CARDSTATUS0_Msk

    - -
    -
    - - - - -
    #define SDIO_RESP0_CARDSTATUS0_Msk   (0xFFFFFFFFUL << SDIO_RESP0_CARDSTATUS0_Pos)
    -
    -

    0xFFFFFFFF

    - -
    -
    - -

    ◆ SDIO_RESP0_CARDSTATUS0

    - -
    -
    - - - - -
    #define SDIO_RESP0_CARDSTATUS0   SDIO_RESP0_CARDSTATUS0_Msk
    -
    -

    Card Status

    - -
    -
    - -

    ◆ SDIO_RESP1_CARDSTATUS1_Pos

    - -
    -
    - - - - -
    #define SDIO_RESP1_CARDSTATUS1_Pos   (0U)
    -
    - -
    -
    - -

    ◆ SDIO_RESP1_CARDSTATUS1_Msk

    - -
    -
    - - - - -
    #define SDIO_RESP1_CARDSTATUS1_Msk   (0xFFFFFFFFUL << SDIO_RESP1_CARDSTATUS1_Pos)
    -
    -

    0xFFFFFFFF

    - -
    -
    - -

    ◆ SDIO_RESP1_CARDSTATUS1

    - -
    -
    - - - - -
    #define SDIO_RESP1_CARDSTATUS1   SDIO_RESP1_CARDSTATUS1_Msk
    -
    -

    Card Status

    - -
    -
    - -

    ◆ SDIO_RESP2_CARDSTATUS2_Pos

    - -
    -
    - - - - -
    #define SDIO_RESP2_CARDSTATUS2_Pos   (0U)
    -
    - -
    -
    - -

    ◆ SDIO_RESP2_CARDSTATUS2_Msk

    - -
    -
    - - - - -
    #define SDIO_RESP2_CARDSTATUS2_Msk   (0xFFFFFFFFUL << SDIO_RESP2_CARDSTATUS2_Pos)
    -
    -

    0xFFFFFFFF

    - -
    -
    - -

    ◆ SDIO_RESP2_CARDSTATUS2

    - -
    -
    - - - - -
    #define SDIO_RESP2_CARDSTATUS2   SDIO_RESP2_CARDSTATUS2_Msk
    -
    -

    Card Status

    - -
    -
    - -

    ◆ SDIO_RESP3_CARDSTATUS3_Pos

    - -
    -
    - - - - -
    #define SDIO_RESP3_CARDSTATUS3_Pos   (0U)
    -
    - -
    -
    - -

    ◆ SDIO_RESP3_CARDSTATUS3_Msk

    - -
    -
    - - - - -
    #define SDIO_RESP3_CARDSTATUS3_Msk   (0xFFFFFFFFUL << SDIO_RESP3_CARDSTATUS3_Pos)
    -
    -

    0xFFFFFFFF

    - -
    -
    - -

    ◆ SDIO_RESP3_CARDSTATUS3

    - -
    -
    - - - - -
    #define SDIO_RESP3_CARDSTATUS3   SDIO_RESP3_CARDSTATUS3_Msk
    -
    -

    Card Status

    - -
    -
    - -

    ◆ SDIO_RESP4_CARDSTATUS4_Pos

    - -
    -
    - - - - -
    #define SDIO_RESP4_CARDSTATUS4_Pos   (0U)
    -
    - -
    -
    - -

    ◆ SDIO_RESP4_CARDSTATUS4_Msk

    - -
    -
    - - - - -
    #define SDIO_RESP4_CARDSTATUS4_Msk   (0xFFFFFFFFUL << SDIO_RESP4_CARDSTATUS4_Pos)
    -
    -

    0xFFFFFFFF

    - -
    -
    - -

    ◆ SDIO_RESP4_CARDSTATUS4

    - -
    -
    - - - - -
    #define SDIO_RESP4_CARDSTATUS4   SDIO_RESP4_CARDSTATUS4_Msk
    -
    -

    Card Status

    - -
    -
    - -

    ◆ SDIO_DTIMER_DATATIME_Pos

    - -
    -
    - - - - -
    #define SDIO_DTIMER_DATATIME_Pos   (0U)
    -
    - -
    -
    - -

    ◆ SDIO_DTIMER_DATATIME_Msk

    - -
    -
    - - - - -
    #define SDIO_DTIMER_DATATIME_Msk   (0xFFFFFFFFUL << SDIO_DTIMER_DATATIME_Pos)
    -
    -

    0xFFFFFFFF

    - -
    -
    - -

    ◆ SDIO_DTIMER_DATATIME

    - -
    -
    - - - - -
    #define SDIO_DTIMER_DATATIME   SDIO_DTIMER_DATATIME_Msk
    -
    -

    Data timeout period.

    - -
    -
    - -

    ◆ SDIO_DLEN_DATALENGTH_Pos

    - -
    -
    - - - - -
    #define SDIO_DLEN_DATALENGTH_Pos   (0U)
    -
    - -
    -
    - -

    ◆ SDIO_DLEN_DATALENGTH_Msk

    - -
    -
    - - - - -
    #define SDIO_DLEN_DATALENGTH_Msk   (0x1FFFFFFUL << SDIO_DLEN_DATALENGTH_Pos)
    -
    -

    0x01FFFFFF

    - -
    -
    - -

    ◆ SDIO_DLEN_DATALENGTH

    - -
    -
    - - - - -
    #define SDIO_DLEN_DATALENGTH   SDIO_DLEN_DATALENGTH_Msk
    -
    -

    Data length value
    -

    - -
    -
    - -

    ◆ SDIO_DCTRL_DTEN_Pos

    - -
    -
    - - - - -
    #define SDIO_DCTRL_DTEN_Pos   (0U)
    -
    - -
    -
    - -

    ◆ SDIO_DCTRL_DTEN_Msk

    - -
    -
    - - - - -
    #define SDIO_DCTRL_DTEN_Msk   (0x1UL << SDIO_DCTRL_DTEN_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ SDIO_DCTRL_DTEN

    - -
    -
    - - - - -
    #define SDIO_DCTRL_DTEN   SDIO_DCTRL_DTEN_Msk
    -
    -

    Data transfer enabled bit
    -

    - -
    -
    - -

    ◆ SDIO_DCTRL_DTDIR_Pos

    - -
    -
    - - - - -
    #define SDIO_DCTRL_DTDIR_Pos   (1U)
    -
    - -
    -
    - -

    ◆ SDIO_DCTRL_DTDIR_Msk

    - -
    -
    - - - - -
    #define SDIO_DCTRL_DTDIR_Msk   (0x1UL << SDIO_DCTRL_DTDIR_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ SDIO_DCTRL_DTDIR

    - -
    -
    - - - - -
    #define SDIO_DCTRL_DTDIR   SDIO_DCTRL_DTDIR_Msk
    -
    -

    Data transfer direction selection

    - -
    -
    - -

    ◆ SDIO_DCTRL_DTMODE_Pos

    - -
    -
    - - - - -
    #define SDIO_DCTRL_DTMODE_Pos   (2U)
    -
    - -
    -
    - -

    ◆ SDIO_DCTRL_DTMODE_Msk

    - -
    -
    - - - - -
    #define SDIO_DCTRL_DTMODE_Msk   (0x1UL << SDIO_DCTRL_DTMODE_Pos)
    -
    -

    0x00000004

    - -
    -
    - -

    ◆ SDIO_DCTRL_DTMODE

    - -
    -
    - - - - -
    #define SDIO_DCTRL_DTMODE   SDIO_DCTRL_DTMODE_Msk
    -
    -

    Data transfer mode selection
    -

    - -
    -
    - -

    ◆ SDIO_DCTRL_DMAEN_Pos

    - -
    -
    - - - - -
    #define SDIO_DCTRL_DMAEN_Pos   (3U)
    -
    - -
    -
    - -

    ◆ SDIO_DCTRL_DMAEN_Msk

    - -
    -
    - - - - -
    #define SDIO_DCTRL_DMAEN_Msk   (0x1UL << SDIO_DCTRL_DMAEN_Pos)
    -
    -

    0x00000008

    - -
    -
    - -

    ◆ SDIO_DCTRL_DMAEN

    - -
    -
    - - - - -
    #define SDIO_DCTRL_DMAEN   SDIO_DCTRL_DMAEN_Msk
    -
    -

    DMA enabled bit
    -

    - -
    -
    - -

    ◆ SDIO_DCTRL_DBLOCKSIZE_Pos

    - -
    -
    - - - - -
    #define SDIO_DCTRL_DBLOCKSIZE_Pos   (4U)
    -
    - -
    -
    - -

    ◆ SDIO_DCTRL_DBLOCKSIZE_Msk

    - -
    -
    - - - - -
    #define SDIO_DCTRL_DBLOCKSIZE_Msk   (0xFUL << SDIO_DCTRL_DBLOCKSIZE_Pos)
    -
    -

    0x000000F0

    - -
    -
    - -

    ◆ SDIO_DCTRL_DBLOCKSIZE

    - -
    -
    - - - - -
    #define SDIO_DCTRL_DBLOCKSIZE   SDIO_DCTRL_DBLOCKSIZE_Msk
    -
    -

    DBLOCKSIZE[3:0] bits (Data block size)

    - -
    -
    - -

    ◆ SDIO_DCTRL_DBLOCKSIZE_0

    - -
    -
    - - - - -
    #define SDIO_DCTRL_DBLOCKSIZE_0   (0x1UL << SDIO_DCTRL_DBLOCKSIZE_Pos)
    -
    -

    0x0010

    - -
    -
    - -

    ◆ SDIO_DCTRL_DBLOCKSIZE_1

    - -
    -
    - - - - -
    #define SDIO_DCTRL_DBLOCKSIZE_1   (0x2UL << SDIO_DCTRL_DBLOCKSIZE_Pos)
    -
    -

    0x0020

    - -
    -
    - -

    ◆ SDIO_DCTRL_DBLOCKSIZE_2

    - -
    -
    - - - - -
    #define SDIO_DCTRL_DBLOCKSIZE_2   (0x4UL << SDIO_DCTRL_DBLOCKSIZE_Pos)
    -
    -

    0x0040

    - -
    -
    - -

    ◆ SDIO_DCTRL_DBLOCKSIZE_3

    - -
    -
    - - - - -
    #define SDIO_DCTRL_DBLOCKSIZE_3   (0x8UL << SDIO_DCTRL_DBLOCKSIZE_Pos)
    -
    -

    0x0080

    - -
    -
    - -

    ◆ SDIO_DCTRL_RWSTART_Pos

    - -
    -
    - - - - -
    #define SDIO_DCTRL_RWSTART_Pos   (8U)
    -
    - -
    -
    - -

    ◆ SDIO_DCTRL_RWSTART_Msk

    - -
    -
    - - - - -
    #define SDIO_DCTRL_RWSTART_Msk   (0x1UL << SDIO_DCTRL_RWSTART_Pos)
    -
    -

    0x00000100

    - -
    -
    - -

    ◆ SDIO_DCTRL_RWSTART

    - -
    -
    - - - - -
    #define SDIO_DCTRL_RWSTART   SDIO_DCTRL_RWSTART_Msk
    -
    -

    Read wait start
    -

    - -
    -
    - -

    ◆ SDIO_DCTRL_RWSTOP_Pos

    - -
    -
    - - - - -
    #define SDIO_DCTRL_RWSTOP_Pos   (9U)
    -
    - -
    -
    - -

    ◆ SDIO_DCTRL_RWSTOP_Msk

    - -
    -
    - - - - -
    #define SDIO_DCTRL_RWSTOP_Msk   (0x1UL << SDIO_DCTRL_RWSTOP_Pos)
    -
    -

    0x00000200

    - -
    -
    - -

    ◆ SDIO_DCTRL_RWSTOP

    - -
    -
    - - - - -
    #define SDIO_DCTRL_RWSTOP   SDIO_DCTRL_RWSTOP_Msk
    -
    -

    Read wait stop
    -

    - -
    -
    - -

    ◆ SDIO_DCTRL_RWMOD_Pos

    - -
    -
    - - - - -
    #define SDIO_DCTRL_RWMOD_Pos   (10U)
    -
    - -
    -
    - -

    ◆ SDIO_DCTRL_RWMOD_Msk

    - -
    -
    - - - - -
    #define SDIO_DCTRL_RWMOD_Msk   (0x1UL << SDIO_DCTRL_RWMOD_Pos)
    -
    -

    0x00000400

    - -
    -
    - -

    ◆ SDIO_DCTRL_RWMOD

    - -
    -
    - - - - -
    #define SDIO_DCTRL_RWMOD   SDIO_DCTRL_RWMOD_Msk
    -
    -

    Read wait mode
    -

    - -
    -
    - -

    ◆ SDIO_DCTRL_SDIOEN_Pos

    - -
    -
    - - - - -
    #define SDIO_DCTRL_SDIOEN_Pos   (11U)
    -
    - -
    -
    - -

    ◆ SDIO_DCTRL_SDIOEN_Msk

    - -
    -
    - - - - -
    #define SDIO_DCTRL_SDIOEN_Msk   (0x1UL << SDIO_DCTRL_SDIOEN_Pos)
    -
    -

    0x00000800

    - -
    -
    - -

    ◆ SDIO_DCTRL_SDIOEN

    - -
    -
    - - - - -
    #define SDIO_DCTRL_SDIOEN   SDIO_DCTRL_SDIOEN_Msk
    -
    -

    SD I/O enable functions

    - -
    -
    - -

    ◆ SDIO_DCOUNT_DATACOUNT_Pos

    - -
    -
    - - - - -
    #define SDIO_DCOUNT_DATACOUNT_Pos   (0U)
    -
    - -
    -
    - -

    ◆ SDIO_DCOUNT_DATACOUNT_Msk

    - -
    -
    - - - - -
    #define SDIO_DCOUNT_DATACOUNT_Msk   (0x1FFFFFFUL << SDIO_DCOUNT_DATACOUNT_Pos)
    -
    -

    0x01FFFFFF

    - -
    -
    - -

    ◆ SDIO_DCOUNT_DATACOUNT

    - -
    -
    - - - - -
    #define SDIO_DCOUNT_DATACOUNT   SDIO_DCOUNT_DATACOUNT_Msk
    -
    -

    Data count value

    - -
    -
    - -

    ◆ SDIO_STA_CCRCFAIL_Pos

    - -
    -
    - - - - -
    #define SDIO_STA_CCRCFAIL_Pos   (0U)
    -
    - -
    -
    - -

    ◆ SDIO_STA_CCRCFAIL_Msk

    - -
    -
    - - - - -
    #define SDIO_STA_CCRCFAIL_Msk   (0x1UL << SDIO_STA_CCRCFAIL_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ SDIO_STA_CCRCFAIL

    - -
    -
    - - - - -
    #define SDIO_STA_CCRCFAIL   SDIO_STA_CCRCFAIL_Msk
    -
    -

    Command response received (CRC check failed)
    -

    - -
    -
    - -

    ◆ SDIO_STA_DCRCFAIL_Pos

    - -
    -
    - - - - -
    #define SDIO_STA_DCRCFAIL_Pos   (1U)
    -
    - -
    -
    - -

    ◆ SDIO_STA_DCRCFAIL_Msk

    - -
    -
    - - - - -
    #define SDIO_STA_DCRCFAIL_Msk   (0x1UL << SDIO_STA_DCRCFAIL_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ SDIO_STA_DCRCFAIL

    - -
    -
    - - - - -
    #define SDIO_STA_DCRCFAIL   SDIO_STA_DCRCFAIL_Msk
    -
    -

    Data block sent/received (CRC check failed)
    -

    - -
    -
    - -

    ◆ SDIO_STA_CTIMEOUT_Pos

    - -
    -
    - - - - -
    #define SDIO_STA_CTIMEOUT_Pos   (2U)
    -
    - -
    -
    - -

    ◆ SDIO_STA_CTIMEOUT_Msk

    - -
    -
    - - - - -
    #define SDIO_STA_CTIMEOUT_Msk   (0x1UL << SDIO_STA_CTIMEOUT_Pos)
    -
    -

    0x00000004

    - -
    -
    - -

    ◆ SDIO_STA_CTIMEOUT

    - -
    -
    - - - - -
    #define SDIO_STA_CTIMEOUT   SDIO_STA_CTIMEOUT_Msk
    -
    -

    Command response timeout
    -

    - -
    -
    - -

    ◆ SDIO_STA_DTIMEOUT_Pos

    - -
    -
    - - - - -
    #define SDIO_STA_DTIMEOUT_Pos   (3U)
    -
    - -
    -
    - -

    ◆ SDIO_STA_DTIMEOUT_Msk

    - -
    -
    - - - - -
    #define SDIO_STA_DTIMEOUT_Msk   (0x1UL << SDIO_STA_DTIMEOUT_Pos)
    -
    -

    0x00000008

    - -
    -
    - -

    ◆ SDIO_STA_DTIMEOUT

    - -
    -
    - - - - -
    #define SDIO_STA_DTIMEOUT   SDIO_STA_DTIMEOUT_Msk
    -
    -

    Data timeout
    -

    - -
    -
    - -

    ◆ SDIO_STA_TXUNDERR_Pos

    - -
    -
    - - - - -
    #define SDIO_STA_TXUNDERR_Pos   (4U)
    -
    - -
    -
    - -

    ◆ SDIO_STA_TXUNDERR_Msk

    - -
    -
    - - - - -
    #define SDIO_STA_TXUNDERR_Msk   (0x1UL << SDIO_STA_TXUNDERR_Pos)
    -
    -

    0x00000010

    - -
    -
    - -

    ◆ SDIO_STA_TXUNDERR

    - -
    -
    - - - - -
    #define SDIO_STA_TXUNDERR   SDIO_STA_TXUNDERR_Msk
    -
    -

    Transmit FIFO underrun error
    -

    - -
    -
    - -

    ◆ SDIO_STA_RXOVERR_Pos

    - -
    -
    - - - - -
    #define SDIO_STA_RXOVERR_Pos   (5U)
    -
    - -
    -
    - -

    ◆ SDIO_STA_RXOVERR_Msk

    - -
    -
    - - - - -
    #define SDIO_STA_RXOVERR_Msk   (0x1UL << SDIO_STA_RXOVERR_Pos)
    -
    -

    0x00000020

    - -
    -
    - -

    ◆ SDIO_STA_RXOVERR

    - -
    -
    - - - - -
    #define SDIO_STA_RXOVERR   SDIO_STA_RXOVERR_Msk
    -
    -

    Received FIFO overrun error
    -

    - -
    -
    - -

    ◆ SDIO_STA_CMDREND_Pos

    - -
    -
    - - - - -
    #define SDIO_STA_CMDREND_Pos   (6U)
    -
    - -
    -
    - -

    ◆ SDIO_STA_CMDREND_Msk

    - -
    -
    - - - - -
    #define SDIO_STA_CMDREND_Msk   (0x1UL << SDIO_STA_CMDREND_Pos)
    -
    -

    0x00000040

    - -
    -
    - -

    ◆ SDIO_STA_CMDREND

    - -
    -
    - - - - -
    #define SDIO_STA_CMDREND   SDIO_STA_CMDREND_Msk
    -
    -

    Command response received (CRC check passed)
    -

    - -
    -
    - -

    ◆ SDIO_STA_CMDSENT_Pos

    - -
    -
    - - - - -
    #define SDIO_STA_CMDSENT_Pos   (7U)
    -
    - -
    -
    - -

    ◆ SDIO_STA_CMDSENT_Msk

    - -
    -
    - - - - -
    #define SDIO_STA_CMDSENT_Msk   (0x1UL << SDIO_STA_CMDSENT_Pos)
    -
    -

    0x00000080

    - -
    -
    - -

    ◆ SDIO_STA_CMDSENT

    - -
    -
    - - - - -
    #define SDIO_STA_CMDSENT   SDIO_STA_CMDSENT_Msk
    -
    -

    Command sent (no response required)
    -

    - -
    -
    - -

    ◆ SDIO_STA_DATAEND_Pos

    - -
    -
    - - - - -
    #define SDIO_STA_DATAEND_Pos   (8U)
    -
    - -
    -
    - -

    ◆ SDIO_STA_DATAEND_Msk

    - -
    -
    - - - - -
    #define SDIO_STA_DATAEND_Msk   (0x1UL << SDIO_STA_DATAEND_Pos)
    -
    -

    0x00000100

    - -
    -
    - -

    ◆ SDIO_STA_DATAEND

    - -
    -
    - - - - -
    #define SDIO_STA_DATAEND   SDIO_STA_DATAEND_Msk
    -
    -

    Data end (data counter, SDIDCOUNT, is zero)
    -

    - -
    -
    - -

    ◆ SDIO_STA_STBITERR_Pos

    - -
    -
    - - - - -
    #define SDIO_STA_STBITERR_Pos   (9U)
    -
    - -
    -
    - -

    ◆ SDIO_STA_STBITERR_Msk

    - -
    -
    - - - - -
    #define SDIO_STA_STBITERR_Msk   (0x1UL << SDIO_STA_STBITERR_Pos)
    -
    -

    0x00000200

    - -
    -
    - -

    ◆ SDIO_STA_STBITERR

    - -
    -
    - - - - -
    #define SDIO_STA_STBITERR   SDIO_STA_STBITERR_Msk
    -
    -

    Start bit not detected on all data signals in wide bus mode

    - -
    -
    - -

    ◆ SDIO_STA_DBCKEND_Pos

    - -
    -
    - - - - -
    #define SDIO_STA_DBCKEND_Pos   (10U)
    -
    - -
    -
    - -

    ◆ SDIO_STA_DBCKEND_Msk

    - -
    -
    - - - - -
    #define SDIO_STA_DBCKEND_Msk   (0x1UL << SDIO_STA_DBCKEND_Pos)
    -
    -

    0x00000400

    - -
    -
    - -

    ◆ SDIO_STA_DBCKEND

    - -
    -
    - - - - -
    #define SDIO_STA_DBCKEND   SDIO_STA_DBCKEND_Msk
    -
    -

    Data block sent/received (CRC check passed)
    -

    - -
    -
    - -

    ◆ SDIO_STA_CMDACT_Pos

    - -
    -
    - - - - -
    #define SDIO_STA_CMDACT_Pos   (11U)
    -
    - -
    -
    - -

    ◆ SDIO_STA_CMDACT_Msk

    - -
    -
    - - - - -
    #define SDIO_STA_CMDACT_Msk   (0x1UL << SDIO_STA_CMDACT_Pos)
    -
    -

    0x00000800

    - -
    -
    - -

    ◆ SDIO_STA_CMDACT

    - -
    -
    - - - - -
    #define SDIO_STA_CMDACT   SDIO_STA_CMDACT_Msk
    -
    -

    Command transfer in progress
    -

    - -
    -
    - -

    ◆ SDIO_STA_TXACT_Pos

    - -
    -
    - - - - -
    #define SDIO_STA_TXACT_Pos   (12U)
    -
    - -
    -
    - -

    ◆ SDIO_STA_TXACT_Msk

    - -
    -
    - - - - -
    #define SDIO_STA_TXACT_Msk   (0x1UL << SDIO_STA_TXACT_Pos)
    -
    -

    0x00001000

    - -
    -
    - -

    ◆ SDIO_STA_TXACT

    - -
    -
    - - - - -
    #define SDIO_STA_TXACT   SDIO_STA_TXACT_Msk
    -
    -

    Data transmit in progress
    -

    - -
    -
    - -

    ◆ SDIO_STA_RXACT_Pos

    - -
    -
    - - - - -
    #define SDIO_STA_RXACT_Pos   (13U)
    -
    - -
    -
    - -

    ◆ SDIO_STA_RXACT_Msk

    - -
    -
    - - - - -
    #define SDIO_STA_RXACT_Msk   (0x1UL << SDIO_STA_RXACT_Pos)
    -
    -

    0x00002000

    - -
    -
    - -

    ◆ SDIO_STA_RXACT

    - -
    -
    - - - - -
    #define SDIO_STA_RXACT   SDIO_STA_RXACT_Msk
    -
    -

    Data receive in progress
    -

    - -
    -
    - -

    ◆ SDIO_STA_TXFIFOHE_Pos

    - -
    -
    - - - - -
    #define SDIO_STA_TXFIFOHE_Pos   (14U)
    -
    - -
    -
    - -

    ◆ SDIO_STA_TXFIFOHE_Msk

    - -
    -
    - - - - -
    #define SDIO_STA_TXFIFOHE_Msk   (0x1UL << SDIO_STA_TXFIFOHE_Pos)
    -
    -

    0x00004000

    - -
    -
    - -

    ◆ SDIO_STA_TXFIFOHE

    - -
    -
    - - - - -
    #define SDIO_STA_TXFIFOHE   SDIO_STA_TXFIFOHE_Msk
    -
    -

    Transmit FIFO Half Empty: at least 8 words can be written into the FIFO

    - -
    -
    - -

    ◆ SDIO_STA_RXFIFOHF_Pos

    - -
    -
    - - - - -
    #define SDIO_STA_RXFIFOHF_Pos   (15U)
    -
    - -
    -
    - -

    ◆ SDIO_STA_RXFIFOHF_Msk

    - -
    -
    - - - - -
    #define SDIO_STA_RXFIFOHF_Msk   (0x1UL << SDIO_STA_RXFIFOHF_Pos)
    -
    -

    0x00008000

    - -
    -
    - -

    ◆ SDIO_STA_RXFIFOHF

    - -
    -
    - - - - -
    #define SDIO_STA_RXFIFOHF   SDIO_STA_RXFIFOHF_Msk
    -
    -

    Receive FIFO Half Full: there are at least 8 words in the FIFO

    - -
    -
    - -

    ◆ SDIO_STA_TXFIFOF_Pos

    - -
    -
    - - - - -
    #define SDIO_STA_TXFIFOF_Pos   (16U)
    -
    - -
    -
    - -

    ◆ SDIO_STA_TXFIFOF_Msk

    - -
    -
    - - - - -
    #define SDIO_STA_TXFIFOF_Msk   (0x1UL << SDIO_STA_TXFIFOF_Pos)
    -
    -

    0x00010000

    - -
    -
    - -

    ◆ SDIO_STA_TXFIFOF

    - -
    -
    - - - - -
    #define SDIO_STA_TXFIFOF   SDIO_STA_TXFIFOF_Msk
    -
    -

    Transmit FIFO full
    -

    - -
    -
    - -

    ◆ SDIO_STA_RXFIFOF_Pos

    - -
    -
    - - - - -
    #define SDIO_STA_RXFIFOF_Pos   (17U)
    -
    - -
    -
    - -

    ◆ SDIO_STA_RXFIFOF_Msk

    - -
    -
    - - - - -
    #define SDIO_STA_RXFIFOF_Msk   (0x1UL << SDIO_STA_RXFIFOF_Pos)
    -
    -

    0x00020000

    - -
    -
    - -

    ◆ SDIO_STA_RXFIFOF

    - -
    -
    - - - - -
    #define SDIO_STA_RXFIFOF   SDIO_STA_RXFIFOF_Msk
    -
    -

    Receive FIFO full
    -

    - -
    -
    - -

    ◆ SDIO_STA_TXFIFOE_Pos

    - -
    -
    - - - - -
    #define SDIO_STA_TXFIFOE_Pos   (18U)
    -
    - -
    -
    - -

    ◆ SDIO_STA_TXFIFOE_Msk

    - -
    -
    - - - - -
    #define SDIO_STA_TXFIFOE_Msk   (0x1UL << SDIO_STA_TXFIFOE_Pos)
    -
    -

    0x00040000

    - -
    -
    - -

    ◆ SDIO_STA_TXFIFOE

    - -
    -
    - - - - -
    #define SDIO_STA_TXFIFOE   SDIO_STA_TXFIFOE_Msk
    -
    -

    Transmit FIFO empty
    -

    - -
    -
    - -

    ◆ SDIO_STA_RXFIFOE_Pos

    - -
    -
    - - - - -
    #define SDIO_STA_RXFIFOE_Pos   (19U)
    -
    - -
    -
    - -

    ◆ SDIO_STA_RXFIFOE_Msk

    - -
    -
    - - - - -
    #define SDIO_STA_RXFIFOE_Msk   (0x1UL << SDIO_STA_RXFIFOE_Pos)
    -
    -

    0x00080000

    - -
    -
    - -

    ◆ SDIO_STA_RXFIFOE

    - -
    -
    - - - - -
    #define SDIO_STA_RXFIFOE   SDIO_STA_RXFIFOE_Msk
    -
    -

    Receive FIFO empty
    -

    - -
    -
    - -

    ◆ SDIO_STA_TXDAVL_Pos

    - -
    -
    - - - - -
    #define SDIO_STA_TXDAVL_Pos   (20U)
    -
    - -
    -
    - -

    ◆ SDIO_STA_TXDAVL_Msk

    - -
    -
    - - - - -
    #define SDIO_STA_TXDAVL_Msk   (0x1UL << SDIO_STA_TXDAVL_Pos)
    -
    -

    0x00100000

    - -
    -
    - -

    ◆ SDIO_STA_TXDAVL

    - -
    -
    - - - - -
    #define SDIO_STA_TXDAVL   SDIO_STA_TXDAVL_Msk
    -
    -

    Data available in transmit FIFO
    -

    - -
    -
    - -

    ◆ SDIO_STA_RXDAVL_Pos

    - -
    -
    - - - - -
    #define SDIO_STA_RXDAVL_Pos   (21U)
    -
    - -
    -
    - -

    ◆ SDIO_STA_RXDAVL_Msk

    - -
    -
    - - - - -
    #define SDIO_STA_RXDAVL_Msk   (0x1UL << SDIO_STA_RXDAVL_Pos)
    -
    -

    0x00200000

    - -
    -
    - -

    ◆ SDIO_STA_RXDAVL

    - -
    -
    - - - - -
    #define SDIO_STA_RXDAVL   SDIO_STA_RXDAVL_Msk
    -
    -

    Data available in receive FIFO
    -

    - -
    -
    - -

    ◆ SDIO_STA_SDIOIT_Pos

    - -
    -
    - - - - -
    #define SDIO_STA_SDIOIT_Pos   (22U)
    -
    - -
    -
    - -

    ◆ SDIO_STA_SDIOIT_Msk

    - -
    -
    - - - - -
    #define SDIO_STA_SDIOIT_Msk   (0x1UL << SDIO_STA_SDIOIT_Pos)
    -
    -

    0x00400000

    - -
    -
    - -

    ◆ SDIO_STA_SDIOIT

    - -
    -
    - - - - -
    #define SDIO_STA_SDIOIT   SDIO_STA_SDIOIT_Msk
    -
    -

    SDIO interrupt received
    -

    - -
    -
    - -

    ◆ SDIO_STA_CEATAEND_Pos

    - -
    -
    - - - - -
    #define SDIO_STA_CEATAEND_Pos   (23U)
    -
    - -
    -
    - -

    ◆ SDIO_STA_CEATAEND_Msk

    - -
    -
    - - - - -
    #define SDIO_STA_CEATAEND_Msk   (0x1UL << SDIO_STA_CEATAEND_Pos)
    -
    -

    0x00800000

    - -
    -
    - -

    ◆ SDIO_STA_CEATAEND

    - -
    -
    - - - - -
    #define SDIO_STA_CEATAEND   SDIO_STA_CEATAEND_Msk
    -
    -

    CE-ATA command completion signal received for CMD61

    - -
    -
    - -

    ◆ SDIO_ICR_CCRCFAILC_Pos

    - -
    -
    - - - - -
    #define SDIO_ICR_CCRCFAILC_Pos   (0U)
    -
    - -
    -
    - -

    ◆ SDIO_ICR_CCRCFAILC_Msk

    - -
    -
    - - - - -
    #define SDIO_ICR_CCRCFAILC_Msk   (0x1UL << SDIO_ICR_CCRCFAILC_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ SDIO_ICR_CCRCFAILC

    - -
    -
    - - - - -
    #define SDIO_ICR_CCRCFAILC   SDIO_ICR_CCRCFAILC_Msk
    -
    -

    CCRCFAIL flag clear bit

    - -
    -
    - -

    ◆ SDIO_ICR_DCRCFAILC_Pos

    - -
    -
    - - - - -
    #define SDIO_ICR_DCRCFAILC_Pos   (1U)
    -
    - -
    -
    - -

    ◆ SDIO_ICR_DCRCFAILC_Msk

    - -
    -
    - - - - -
    #define SDIO_ICR_DCRCFAILC_Msk   (0x1UL << SDIO_ICR_DCRCFAILC_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ SDIO_ICR_DCRCFAILC

    - -
    -
    - - - - -
    #define SDIO_ICR_DCRCFAILC   SDIO_ICR_DCRCFAILC_Msk
    -
    -

    DCRCFAIL flag clear bit

    - -
    -
    - -

    ◆ SDIO_ICR_CTIMEOUTC_Pos

    - -
    -
    - - - - -
    #define SDIO_ICR_CTIMEOUTC_Pos   (2U)
    -
    - -
    -
    - -

    ◆ SDIO_ICR_CTIMEOUTC_Msk

    - -
    -
    - - - - -
    #define SDIO_ICR_CTIMEOUTC_Msk   (0x1UL << SDIO_ICR_CTIMEOUTC_Pos)
    -
    -

    0x00000004

    - -
    -
    - -

    ◆ SDIO_ICR_CTIMEOUTC

    - -
    -
    - - - - -
    #define SDIO_ICR_CTIMEOUTC   SDIO_ICR_CTIMEOUTC_Msk
    -
    -

    CTIMEOUT flag clear bit

    - -
    -
    - -

    ◆ SDIO_ICR_DTIMEOUTC_Pos

    - -
    -
    - - - - -
    #define SDIO_ICR_DTIMEOUTC_Pos   (3U)
    -
    - -
    -
    - -

    ◆ SDIO_ICR_DTIMEOUTC_Msk

    - -
    -
    - - - - -
    #define SDIO_ICR_DTIMEOUTC_Msk   (0x1UL << SDIO_ICR_DTIMEOUTC_Pos)
    -
    -

    0x00000008

    - -
    -
    - -

    ◆ SDIO_ICR_DTIMEOUTC

    - -
    -
    - - - - -
    #define SDIO_ICR_DTIMEOUTC   SDIO_ICR_DTIMEOUTC_Msk
    -
    -

    DTIMEOUT flag clear bit

    - -
    -
    - -

    ◆ SDIO_ICR_TXUNDERRC_Pos

    - -
    -
    - - - - -
    #define SDIO_ICR_TXUNDERRC_Pos   (4U)
    -
    - -
    -
    - -

    ◆ SDIO_ICR_TXUNDERRC_Msk

    - -
    -
    - - - - -
    #define SDIO_ICR_TXUNDERRC_Msk   (0x1UL << SDIO_ICR_TXUNDERRC_Pos)
    -
    -

    0x00000010

    - -
    -
    - -

    ◆ SDIO_ICR_TXUNDERRC

    - -
    -
    - - - - -
    #define SDIO_ICR_TXUNDERRC   SDIO_ICR_TXUNDERRC_Msk
    -
    -

    TXUNDERR flag clear bit

    - -
    -
    - -

    ◆ SDIO_ICR_RXOVERRC_Pos

    - -
    -
    - - - - -
    #define SDIO_ICR_RXOVERRC_Pos   (5U)
    -
    - -
    -
    - -

    ◆ SDIO_ICR_RXOVERRC_Msk

    - -
    -
    - - - - -
    #define SDIO_ICR_RXOVERRC_Msk   (0x1UL << SDIO_ICR_RXOVERRC_Pos)
    -
    -

    0x00000020

    - -
    -
    - -

    ◆ SDIO_ICR_RXOVERRC

    - -
    -
    - - - - -
    #define SDIO_ICR_RXOVERRC   SDIO_ICR_RXOVERRC_Msk
    -
    -

    RXOVERR flag clear bit
    -

    - -
    -
    - -

    ◆ SDIO_ICR_CMDRENDC_Pos

    - -
    -
    - - - - -
    #define SDIO_ICR_CMDRENDC_Pos   (6U)
    -
    - -
    -
    - -

    ◆ SDIO_ICR_CMDRENDC_Msk

    - -
    -
    - - - - -
    #define SDIO_ICR_CMDRENDC_Msk   (0x1UL << SDIO_ICR_CMDRENDC_Pos)
    -
    -

    0x00000040

    - -
    -
    - -

    ◆ SDIO_ICR_CMDRENDC

    - -
    -
    - - - - -
    #define SDIO_ICR_CMDRENDC   SDIO_ICR_CMDRENDC_Msk
    -
    -

    CMDREND flag clear bit
    -

    - -
    -
    - -

    ◆ SDIO_ICR_CMDSENTC_Pos

    - -
    -
    - - - - -
    #define SDIO_ICR_CMDSENTC_Pos   (7U)
    -
    - -
    -
    - -

    ◆ SDIO_ICR_CMDSENTC_Msk

    - -
    -
    - - - - -
    #define SDIO_ICR_CMDSENTC_Msk   (0x1UL << SDIO_ICR_CMDSENTC_Pos)
    -
    -

    0x00000080

    - -
    -
    - -

    ◆ SDIO_ICR_CMDSENTC

    - -
    -
    - - - - -
    #define SDIO_ICR_CMDSENTC   SDIO_ICR_CMDSENTC_Msk
    -
    -

    CMDSENT flag clear bit
    -

    - -
    -
    - -

    ◆ SDIO_ICR_DATAENDC_Pos

    - -
    -
    - - - - -
    #define SDIO_ICR_DATAENDC_Pos   (8U)
    -
    - -
    -
    - -

    ◆ SDIO_ICR_DATAENDC_Msk

    - -
    -
    - - - - -
    #define SDIO_ICR_DATAENDC_Msk   (0x1UL << SDIO_ICR_DATAENDC_Pos)
    -
    -

    0x00000100

    - -
    -
    - -

    ◆ SDIO_ICR_DATAENDC

    - -
    -
    - - - - -
    #define SDIO_ICR_DATAENDC   SDIO_ICR_DATAENDC_Msk
    -
    -

    DATAEND flag clear bit
    -

    - -
    -
    - -

    ◆ SDIO_ICR_STBITERRC_Pos

    - -
    -
    - - - - -
    #define SDIO_ICR_STBITERRC_Pos   (9U)
    -
    - -
    -
    - -

    ◆ SDIO_ICR_STBITERRC_Msk

    - -
    -
    - - - - -
    #define SDIO_ICR_STBITERRC_Msk   (0x1UL << SDIO_ICR_STBITERRC_Pos)
    -
    -

    0x00000200

    - -
    -
    - -

    ◆ SDIO_ICR_STBITERRC

    - -
    -
    - - - - -
    #define SDIO_ICR_STBITERRC   SDIO_ICR_STBITERRC_Msk
    -
    -

    STBITERR flag clear bit

    - -
    -
    - -

    ◆ SDIO_ICR_DBCKENDC_Pos

    - -
    -
    - - - - -
    #define SDIO_ICR_DBCKENDC_Pos   (10U)
    -
    - -
    -
    - -

    ◆ SDIO_ICR_DBCKENDC_Msk

    - -
    -
    - - - - -
    #define SDIO_ICR_DBCKENDC_Msk   (0x1UL << SDIO_ICR_DBCKENDC_Pos)
    -
    -

    0x00000400

    - -
    -
    - -

    ◆ SDIO_ICR_DBCKENDC

    - -
    -
    - - - - -
    #define SDIO_ICR_DBCKENDC   SDIO_ICR_DBCKENDC_Msk
    -
    -

    DBCKEND flag clear bit
    -

    - -
    -
    - -

    ◆ SDIO_ICR_SDIOITC_Pos

    - -
    -
    - - - - -
    #define SDIO_ICR_SDIOITC_Pos   (22U)
    -
    - -
    -
    - -

    ◆ SDIO_ICR_SDIOITC_Msk

    - -
    -
    - - - - -
    #define SDIO_ICR_SDIOITC_Msk   (0x1UL << SDIO_ICR_SDIOITC_Pos)
    -
    -

    0x00400000

    - -
    -
    - -

    ◆ SDIO_ICR_SDIOITC

    - -
    -
    - - - - -
    #define SDIO_ICR_SDIOITC   SDIO_ICR_SDIOITC_Msk
    -
    -

    SDIOIT flag clear bit
    -

    - -
    -
    - -

    ◆ SDIO_ICR_CEATAENDC_Pos

    - -
    -
    - - - - -
    #define SDIO_ICR_CEATAENDC_Pos   (23U)
    -
    - -
    -
    - -

    ◆ SDIO_ICR_CEATAENDC_Msk

    - -
    -
    - - - - -
    #define SDIO_ICR_CEATAENDC_Msk   (0x1UL << SDIO_ICR_CEATAENDC_Pos)
    -
    -

    0x00800000

    - -
    -
    - -

    ◆ SDIO_ICR_CEATAENDC

    - -
    -
    - - - - -
    #define SDIO_ICR_CEATAENDC   SDIO_ICR_CEATAENDC_Msk
    -
    -

    CEATAEND flag clear bit

    - -
    -
    - -

    ◆ SDIO_MASK_CCRCFAILIE_Pos

    - -
    -
    - - - - -
    #define SDIO_MASK_CCRCFAILIE_Pos   (0U)
    -
    - -
    -
    - -

    ◆ SDIO_MASK_CCRCFAILIE_Msk

    - -
    -
    - - - - -
    #define SDIO_MASK_CCRCFAILIE_Msk   (0x1UL << SDIO_MASK_CCRCFAILIE_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ SDIO_MASK_CCRCFAILIE

    - -
    -
    - - - - -
    #define SDIO_MASK_CCRCFAILIE   SDIO_MASK_CCRCFAILIE_Msk
    -
    -

    Command CRC Fail Interrupt Enable
    -

    - -
    -
    - -

    ◆ SDIO_MASK_DCRCFAILIE_Pos

    - -
    -
    - - - - -
    #define SDIO_MASK_DCRCFAILIE_Pos   (1U)
    -
    - -
    -
    - -

    ◆ SDIO_MASK_DCRCFAILIE_Msk

    - -
    -
    - - - - -
    #define SDIO_MASK_DCRCFAILIE_Msk   (0x1UL << SDIO_MASK_DCRCFAILIE_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ SDIO_MASK_DCRCFAILIE

    - -
    -
    - - - - -
    #define SDIO_MASK_DCRCFAILIE   SDIO_MASK_DCRCFAILIE_Msk
    -
    -

    Data CRC Fail Interrupt Enable
    -

    - -
    -
    - -

    ◆ SDIO_MASK_CTIMEOUTIE_Pos

    - -
    -
    - - - - -
    #define SDIO_MASK_CTIMEOUTIE_Pos   (2U)
    -
    - -
    -
    - -

    ◆ SDIO_MASK_CTIMEOUTIE_Msk

    - -
    -
    - - - - -
    #define SDIO_MASK_CTIMEOUTIE_Msk   (0x1UL << SDIO_MASK_CTIMEOUTIE_Pos)
    -
    -

    0x00000004

    - -
    -
    - -

    ◆ SDIO_MASK_CTIMEOUTIE

    - -
    -
    - - - - -
    #define SDIO_MASK_CTIMEOUTIE   SDIO_MASK_CTIMEOUTIE_Msk
    -
    -

    Command TimeOut Interrupt Enable
    -

    - -
    -
    - -

    ◆ SDIO_MASK_DTIMEOUTIE_Pos

    - -
    -
    - - - - -
    #define SDIO_MASK_DTIMEOUTIE_Pos   (3U)
    -
    - -
    -
    - -

    ◆ SDIO_MASK_DTIMEOUTIE_Msk

    - -
    -
    - - - - -
    #define SDIO_MASK_DTIMEOUTIE_Msk   (0x1UL << SDIO_MASK_DTIMEOUTIE_Pos)
    -
    -

    0x00000008

    - -
    -
    - -

    ◆ SDIO_MASK_DTIMEOUTIE

    - -
    -
    - - - - -
    #define SDIO_MASK_DTIMEOUTIE   SDIO_MASK_DTIMEOUTIE_Msk
    -
    -

    Data TimeOut Interrupt Enable
    -

    - -
    -
    - -

    ◆ SDIO_MASK_TXUNDERRIE_Pos

    - -
    -
    - - - - -
    #define SDIO_MASK_TXUNDERRIE_Pos   (4U)
    -
    - -
    -
    - -

    ◆ SDIO_MASK_TXUNDERRIE_Msk

    - -
    -
    - - - - -
    #define SDIO_MASK_TXUNDERRIE_Msk   (0x1UL << SDIO_MASK_TXUNDERRIE_Pos)
    -
    -

    0x00000010

    - -
    -
    - -

    ◆ SDIO_MASK_TXUNDERRIE

    - -
    -
    - - - - -
    #define SDIO_MASK_TXUNDERRIE   SDIO_MASK_TXUNDERRIE_Msk
    -
    -

    Tx FIFO UnderRun Error Interrupt Enable
    -

    - -
    -
    - -

    ◆ SDIO_MASK_RXOVERRIE_Pos

    - -
    -
    - - - - -
    #define SDIO_MASK_RXOVERRIE_Pos   (5U)
    -
    - -
    -
    - -

    ◆ SDIO_MASK_RXOVERRIE_Msk

    - -
    -
    - - - - -
    #define SDIO_MASK_RXOVERRIE_Msk   (0x1UL << SDIO_MASK_RXOVERRIE_Pos)
    -
    -

    0x00000020

    - -
    -
    - -

    ◆ SDIO_MASK_RXOVERRIE

    - -
    -
    - - - - -
    #define SDIO_MASK_RXOVERRIE   SDIO_MASK_RXOVERRIE_Msk
    -
    -

    Rx FIFO OverRun Error Interrupt Enable
    -

    - -
    -
    - -

    ◆ SDIO_MASK_CMDRENDIE_Pos

    - -
    -
    - - - - -
    #define SDIO_MASK_CMDRENDIE_Pos   (6U)
    -
    - -
    -
    - -

    ◆ SDIO_MASK_CMDRENDIE_Msk

    - -
    -
    - - - - -
    #define SDIO_MASK_CMDRENDIE_Msk   (0x1UL << SDIO_MASK_CMDRENDIE_Pos)
    -
    -

    0x00000040

    - -
    -
    - -

    ◆ SDIO_MASK_CMDRENDIE

    - -
    -
    - - - - -
    #define SDIO_MASK_CMDRENDIE   SDIO_MASK_CMDRENDIE_Msk
    -
    -

    Command Response Received Interrupt Enable

    - -
    -
    - -

    ◆ SDIO_MASK_CMDSENTIE_Pos

    - -
    -
    - - - - -
    #define SDIO_MASK_CMDSENTIE_Pos   (7U)
    -
    - -
    -
    - -

    ◆ SDIO_MASK_CMDSENTIE_Msk

    - -
    -
    - - - - -
    #define SDIO_MASK_CMDSENTIE_Msk   (0x1UL << SDIO_MASK_CMDSENTIE_Pos)
    -
    -

    0x00000080

    - -
    -
    - -

    ◆ SDIO_MASK_CMDSENTIE

    - -
    -
    - - - - -
    #define SDIO_MASK_CMDSENTIE   SDIO_MASK_CMDSENTIE_Msk
    -
    -

    Command Sent Interrupt Enable
    -

    - -
    -
    - -

    ◆ SDIO_MASK_DATAENDIE_Pos

    - -
    -
    - - - - -
    #define SDIO_MASK_DATAENDIE_Pos   (8U)
    -
    - -
    -
    - -

    ◆ SDIO_MASK_DATAENDIE_Msk

    - -
    -
    - - - - -
    #define SDIO_MASK_DATAENDIE_Msk   (0x1UL << SDIO_MASK_DATAENDIE_Pos)
    -
    -

    0x00000100

    - -
    -
    - -

    ◆ SDIO_MASK_DATAENDIE

    - -
    -
    - - - - -
    #define SDIO_MASK_DATAENDIE   SDIO_MASK_DATAENDIE_Msk
    -
    -

    Data End Interrupt Enable
    -

    - -
    -
    - -

    ◆ SDIO_MASK_STBITERRIE_Pos

    - -
    -
    - - - - -
    #define SDIO_MASK_STBITERRIE_Pos   (9U)
    -
    - -
    -
    - -

    ◆ SDIO_MASK_STBITERRIE_Msk

    - -
    -
    - - - - -
    #define SDIO_MASK_STBITERRIE_Msk   (0x1UL << SDIO_MASK_STBITERRIE_Pos)
    -
    -

    0x00000200

    - -
    -
    - -

    ◆ SDIO_MASK_STBITERRIE

    - -
    -
    - - - - -
    #define SDIO_MASK_STBITERRIE   SDIO_MASK_STBITERRIE_Msk
    -
    -

    Start Bit Error Interrupt Enable
    -

    - -
    -
    - -

    ◆ SDIO_MASK_DBCKENDIE_Pos

    - -
    -
    - - - - -
    #define SDIO_MASK_DBCKENDIE_Pos   (10U)
    -
    - -
    -
    - -

    ◆ SDIO_MASK_DBCKENDIE_Msk

    - -
    -
    - - - - -
    #define SDIO_MASK_DBCKENDIE_Msk   (0x1UL << SDIO_MASK_DBCKENDIE_Pos)
    -
    -

    0x00000400

    - -
    -
    - -

    ◆ SDIO_MASK_DBCKENDIE

    - -
    -
    - - - - -
    #define SDIO_MASK_DBCKENDIE   SDIO_MASK_DBCKENDIE_Msk
    -
    -

    Data Block End Interrupt Enable
    -

    - -
    -
    - -

    ◆ SDIO_MASK_CMDACTIE_Pos

    - -
    -
    - - - - -
    #define SDIO_MASK_CMDACTIE_Pos   (11U)
    -
    - -
    -
    - -

    ◆ SDIO_MASK_CMDACTIE_Msk

    - -
    -
    - - - - -
    #define SDIO_MASK_CMDACTIE_Msk   (0x1UL << SDIO_MASK_CMDACTIE_Pos)
    -
    -

    0x00000800

    - -
    -
    - -

    ◆ SDIO_MASK_CMDACTIE

    - -
    -
    - - - - -
    #define SDIO_MASK_CMDACTIE   SDIO_MASK_CMDACTIE_Msk
    -
    -

    CCommand Acting Interrupt Enable
    -

    - -
    -
    - -

    ◆ SDIO_MASK_TXACTIE_Pos

    - -
    -
    - - - - -
    #define SDIO_MASK_TXACTIE_Pos   (12U)
    -
    - -
    -
    - -

    ◆ SDIO_MASK_TXACTIE_Msk

    - -
    -
    - - - - -
    #define SDIO_MASK_TXACTIE_Msk   (0x1UL << SDIO_MASK_TXACTIE_Pos)
    -
    -

    0x00001000

    - -
    -
    - -

    ◆ SDIO_MASK_TXACTIE

    - -
    -
    - - - - -
    #define SDIO_MASK_TXACTIE   SDIO_MASK_TXACTIE_Msk
    -
    -

    Data Transmit Acting Interrupt Enable
    -

    - -
    -
    - -

    ◆ SDIO_MASK_RXACTIE_Pos

    - -
    -
    - - - - -
    #define SDIO_MASK_RXACTIE_Pos   (13U)
    -
    - -
    -
    - -

    ◆ SDIO_MASK_RXACTIE_Msk

    - -
    -
    - - - - -
    #define SDIO_MASK_RXACTIE_Msk   (0x1UL << SDIO_MASK_RXACTIE_Pos)
    -
    -

    0x00002000

    - -
    -
    - -

    ◆ SDIO_MASK_RXACTIE

    - -
    -
    - - - - -
    #define SDIO_MASK_RXACTIE   SDIO_MASK_RXACTIE_Msk
    -
    -

    Data receive acting interrupt enabled
    -

    - -
    -
    - -

    ◆ SDIO_MASK_TXFIFOHEIE_Pos

    - -
    -
    - - - - -
    #define SDIO_MASK_TXFIFOHEIE_Pos   (14U)
    -
    - -
    -
    - -

    ◆ SDIO_MASK_TXFIFOHEIE_Msk

    - -
    -
    - - - - -
    #define SDIO_MASK_TXFIFOHEIE_Msk   (0x1UL << SDIO_MASK_TXFIFOHEIE_Pos)
    -
    -

    0x00004000

    - -
    -
    - -

    ◆ SDIO_MASK_TXFIFOHEIE

    - -
    -
    - - - - -
    #define SDIO_MASK_TXFIFOHEIE   SDIO_MASK_TXFIFOHEIE_Msk
    -
    -

    Tx FIFO Half Empty interrupt Enable
    -

    - -
    -
    - -

    ◆ SDIO_MASK_RXFIFOHFIE_Pos

    - -
    -
    - - - - -
    #define SDIO_MASK_RXFIFOHFIE_Pos   (15U)
    -
    - -
    -
    - -

    ◆ SDIO_MASK_RXFIFOHFIE_Msk

    - -
    -
    - - - - -
    #define SDIO_MASK_RXFIFOHFIE_Msk   (0x1UL << SDIO_MASK_RXFIFOHFIE_Pos)
    -
    -

    0x00008000

    - -
    -
    - -

    ◆ SDIO_MASK_RXFIFOHFIE

    - -
    -
    - - - - -
    #define SDIO_MASK_RXFIFOHFIE   SDIO_MASK_RXFIFOHFIE_Msk
    -
    -

    Rx FIFO Half Full interrupt Enable
    -

    - -
    -
    - -

    ◆ SDIO_MASK_TXFIFOFIE_Pos

    - -
    -
    - - - - -
    #define SDIO_MASK_TXFIFOFIE_Pos   (16U)
    -
    - -
    -
    - -

    ◆ SDIO_MASK_TXFIFOFIE_Msk

    - -
    -
    - - - - -
    #define SDIO_MASK_TXFIFOFIE_Msk   (0x1UL << SDIO_MASK_TXFIFOFIE_Pos)
    -
    -

    0x00010000

    - -
    -
    - -

    ◆ SDIO_MASK_TXFIFOFIE

    - -
    -
    - - - - -
    #define SDIO_MASK_TXFIFOFIE   SDIO_MASK_TXFIFOFIE_Msk
    -
    -

    Tx FIFO Full interrupt Enable
    -

    - -
    -
    - -

    ◆ SDIO_MASK_RXFIFOFIE_Pos

    - -
    -
    - - - - -
    #define SDIO_MASK_RXFIFOFIE_Pos   (17U)
    -
    - -
    -
    - -

    ◆ SDIO_MASK_RXFIFOFIE_Msk

    - -
    -
    - - - - -
    #define SDIO_MASK_RXFIFOFIE_Msk   (0x1UL << SDIO_MASK_RXFIFOFIE_Pos)
    -
    -

    0x00020000

    - -
    -
    - -

    ◆ SDIO_MASK_RXFIFOFIE

    - -
    -
    - - - - -
    #define SDIO_MASK_RXFIFOFIE   SDIO_MASK_RXFIFOFIE_Msk
    -
    -

    Rx FIFO Full interrupt Enable
    -

    - -
    -
    - -

    ◆ SDIO_MASK_TXFIFOEIE_Pos

    - -
    -
    - - - - -
    #define SDIO_MASK_TXFIFOEIE_Pos   (18U)
    -
    - -
    -
    - -

    ◆ SDIO_MASK_TXFIFOEIE_Msk

    - -
    -
    - - - - -
    #define SDIO_MASK_TXFIFOEIE_Msk   (0x1UL << SDIO_MASK_TXFIFOEIE_Pos)
    -
    -

    0x00040000

    - -
    -
    - -

    ◆ SDIO_MASK_TXFIFOEIE

    - -
    -
    - - - - -
    #define SDIO_MASK_TXFIFOEIE   SDIO_MASK_TXFIFOEIE_Msk
    -
    -

    Tx FIFO Empty interrupt Enable
    -

    - -
    -
    - -

    ◆ SDIO_MASK_RXFIFOEIE_Pos

    - -
    -
    - - - - -
    #define SDIO_MASK_RXFIFOEIE_Pos   (19U)
    -
    - -
    -
    - -

    ◆ SDIO_MASK_RXFIFOEIE_Msk

    - -
    -
    - - - - -
    #define SDIO_MASK_RXFIFOEIE_Msk   (0x1UL << SDIO_MASK_RXFIFOEIE_Pos)
    -
    -

    0x00080000

    - -
    -
    - -

    ◆ SDIO_MASK_RXFIFOEIE

    - -
    -
    - - - - -
    #define SDIO_MASK_RXFIFOEIE   SDIO_MASK_RXFIFOEIE_Msk
    -
    -

    Rx FIFO Empty interrupt Enable
    -

    - -
    -
    - -

    ◆ SDIO_MASK_TXDAVLIE_Pos

    - -
    -
    - - - - -
    #define SDIO_MASK_TXDAVLIE_Pos   (20U)
    -
    - -
    -
    - -

    ◆ SDIO_MASK_TXDAVLIE_Msk

    - -
    -
    - - - - -
    #define SDIO_MASK_TXDAVLIE_Msk   (0x1UL << SDIO_MASK_TXDAVLIE_Pos)
    -
    -

    0x00100000

    - -
    -
    - -

    ◆ SDIO_MASK_TXDAVLIE

    - -
    -
    - - - - -
    #define SDIO_MASK_TXDAVLIE   SDIO_MASK_TXDAVLIE_Msk
    -
    -

    Data available in Tx FIFO interrupt Enable

    - -
    -
    - -

    ◆ SDIO_MASK_RXDAVLIE_Pos

    - -
    -
    - - - - -
    #define SDIO_MASK_RXDAVLIE_Pos   (21U)
    -
    - -
    -
    - -

    ◆ SDIO_MASK_RXDAVLIE_Msk

    - -
    -
    - - - - -
    #define SDIO_MASK_RXDAVLIE_Msk   (0x1UL << SDIO_MASK_RXDAVLIE_Pos)
    -
    -

    0x00200000

    - -
    -
    - -

    ◆ SDIO_MASK_RXDAVLIE

    - -
    -
    - - - - -
    #define SDIO_MASK_RXDAVLIE   SDIO_MASK_RXDAVLIE_Msk
    -
    -

    Data available in Rx FIFO interrupt Enable

    - -
    -
    - -

    ◆ SDIO_MASK_SDIOITIE_Pos

    - -
    -
    - - - - -
    #define SDIO_MASK_SDIOITIE_Pos   (22U)
    -
    - -
    -
    - -

    ◆ SDIO_MASK_SDIOITIE_Msk

    - -
    -
    - - - - -
    #define SDIO_MASK_SDIOITIE_Msk   (0x1UL << SDIO_MASK_SDIOITIE_Pos)
    -
    -

    0x00400000

    - -
    -
    - -

    ◆ SDIO_MASK_SDIOITIE

    - -
    -
    - - - - -
    #define SDIO_MASK_SDIOITIE   SDIO_MASK_SDIOITIE_Msk
    -
    -

    SDIO Mode Interrupt Received interrupt Enable

    - -
    -
    - -

    ◆ SDIO_MASK_CEATAENDIE_Pos

    - -
    -
    - - - - -
    #define SDIO_MASK_CEATAENDIE_Pos   (23U)
    -
    - -
    -
    - -

    ◆ SDIO_MASK_CEATAENDIE_Msk

    - -
    -
    - - - - -
    #define SDIO_MASK_CEATAENDIE_Msk   (0x1UL << SDIO_MASK_CEATAENDIE_Pos)
    -
    -

    0x00800000

    - -
    -
    - -

    ◆ SDIO_MASK_CEATAENDIE

    - -
    -
    - - - - -
    #define SDIO_MASK_CEATAENDIE   SDIO_MASK_CEATAENDIE_Msk
    -
    -

    CE-ATA command completion signal received Interrupt Enable

    - -
    -
    - -

    ◆ SDIO_FIFOCNT_FIFOCOUNT_Pos

    - -
    -
    - - - - -
    #define SDIO_FIFOCNT_FIFOCOUNT_Pos   (0U)
    -
    - -
    -
    - -

    ◆ SDIO_FIFOCNT_FIFOCOUNT_Msk

    - -
    -
    - - - - -
    #define SDIO_FIFOCNT_FIFOCOUNT_Msk   (0xFFFFFFUL << SDIO_FIFOCNT_FIFOCOUNT_Pos)
    -
    -

    0x00FFFFFF

    - -
    -
    - -

    ◆ SDIO_FIFOCNT_FIFOCOUNT

    - -
    -
    - - - - -
    #define SDIO_FIFOCNT_FIFOCOUNT   SDIO_FIFOCNT_FIFOCOUNT_Msk
    -
    -

    Remaining number of words to be written to or read from the FIFO

    - -
    -
    - -

    ◆ SDIO_FIFO_FIFODATA_Pos

    - -
    -
    - - - - -
    #define SDIO_FIFO_FIFODATA_Pos   (0U)
    -
    - -
    -
    - -

    ◆ SDIO_FIFO_FIFODATA_Msk

    - -
    -
    - - - - -
    #define SDIO_FIFO_FIFODATA_Msk   (0xFFFFFFFFUL << SDIO_FIFO_FIFODATA_Pos)
    -
    -

    0xFFFFFFFF

    - -
    -
    - -

    ◆ SDIO_FIFO_FIFODATA

    - -
    -
    - - - - -
    #define SDIO_FIFO_FIFODATA   SDIO_FIFO_FIFODATA_Msk
    -
    -

    Receive and transmit FIFO data

    - -
    -
    - -

    ◆ SPI_I2S_FULLDUPLEX_SUPPORT

    - -
    -
    - - - - -
    #define SPI_I2S_FULLDUPLEX_SUPPORT
    -
    -

    I2S Full-Duplex support

    - -
    -
    - -

    ◆ SPI_CR1_CPHA_Pos

    - -
    -
    - - - - -
    #define SPI_CR1_CPHA_Pos   (0U)
    -
    - -
    -
    - -

    ◆ SPI_CR1_CPHA_Msk

    - -
    -
    - - - - -
    #define SPI_CR1_CPHA_Msk   (0x1UL << SPI_CR1_CPHA_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ SPI_CR1_CPHA

    - -
    -
    - - - - -
    #define SPI_CR1_CPHA   SPI_CR1_CPHA_Msk
    -
    -

    Clock Phase
    -

    - -
    -
    - -

    ◆ SPI_CR1_CPOL_Pos

    - -
    -
    - - - - -
    #define SPI_CR1_CPOL_Pos   (1U)
    -
    - -
    -
    - -

    ◆ SPI_CR1_CPOL_Msk

    - -
    -
    - - - - -
    #define SPI_CR1_CPOL_Msk   (0x1UL << SPI_CR1_CPOL_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ SPI_CR1_CPOL

    - -
    -
    - - - - -
    #define SPI_CR1_CPOL   SPI_CR1_CPOL_Msk
    -
    -

    Clock Polarity
    -

    - -
    -
    - -

    ◆ SPI_CR1_MSTR_Pos

    - -
    -
    - - - - -
    #define SPI_CR1_MSTR_Pos   (2U)
    -
    - -
    -
    - -

    ◆ SPI_CR1_MSTR_Msk

    - -
    -
    - - - - -
    #define SPI_CR1_MSTR_Msk   (0x1UL << SPI_CR1_MSTR_Pos)
    -
    -

    0x00000004

    - -
    -
    - -

    ◆ SPI_CR1_MSTR

    - -
    -
    - - - - -
    #define SPI_CR1_MSTR   SPI_CR1_MSTR_Msk
    -
    -

    Master Selection

    - -
    -
    - -

    ◆ SPI_CR1_BR_Pos

    - -
    -
    - - - - -
    #define SPI_CR1_BR_Pos   (3U)
    -
    - -
    -
    - -

    ◆ SPI_CR1_BR_Msk

    - -
    -
    - - - - -
    #define SPI_CR1_BR_Msk   (0x7UL << SPI_CR1_BR_Pos)
    -
    -

    0x00000038

    - -
    -
    - -

    ◆ SPI_CR1_BR

    - -
    -
    - - - - -
    #define SPI_CR1_BR   SPI_CR1_BR_Msk
    -
    -

    BR[2:0] bits (Baud Rate Control)

    - -
    -
    - -

    ◆ SPI_CR1_BR_0

    - -
    -
    - - - - -
    #define SPI_CR1_BR_0   (0x1UL << SPI_CR1_BR_Pos)
    -
    -

    0x00000008

    - -
    -
    - -

    ◆ SPI_CR1_BR_1

    - -
    -
    - - - - -
    #define SPI_CR1_BR_1   (0x2UL << SPI_CR1_BR_Pos)
    -
    -

    0x00000010

    - -
    -
    - -

    ◆ SPI_CR1_BR_2

    - -
    -
    - - - - -
    #define SPI_CR1_BR_2   (0x4UL << SPI_CR1_BR_Pos)
    -
    -

    0x00000020

    - -
    -
    - -

    ◆ SPI_CR1_SPE_Pos

    - -
    -
    - - - - -
    #define SPI_CR1_SPE_Pos   (6U)
    -
    - -
    -
    - -

    ◆ SPI_CR1_SPE_Msk

    - -
    -
    - - - - -
    #define SPI_CR1_SPE_Msk   (0x1UL << SPI_CR1_SPE_Pos)
    -
    -

    0x00000040

    - -
    -
    - -

    ◆ SPI_CR1_SPE

    - -
    -
    - - - - -
    #define SPI_CR1_SPE   SPI_CR1_SPE_Msk
    -
    -

    SPI Enable
    -

    - -
    -
    - -

    ◆ SPI_CR1_LSBFIRST_Pos

    - -
    -
    - - - - -
    #define SPI_CR1_LSBFIRST_Pos   (7U)
    -
    - -
    -
    - -

    ◆ SPI_CR1_LSBFIRST_Msk

    - -
    -
    - - - - -
    #define SPI_CR1_LSBFIRST_Msk   (0x1UL << SPI_CR1_LSBFIRST_Pos)
    -
    -

    0x00000080

    - -
    -
    - -

    ◆ SPI_CR1_LSBFIRST

    - -
    -
    - - - - -
    #define SPI_CR1_LSBFIRST   SPI_CR1_LSBFIRST_Msk
    -
    -

    Frame Format
    -

    - -
    -
    - -

    ◆ SPI_CR1_SSI_Pos

    - -
    -
    - - - - -
    #define SPI_CR1_SSI_Pos   (8U)
    -
    - -
    -
    - -

    ◆ SPI_CR1_SSI_Msk

    - -
    -
    - - - - -
    #define SPI_CR1_SSI_Msk   (0x1UL << SPI_CR1_SSI_Pos)
    -
    -

    0x00000100

    - -
    -
    - -

    ◆ SPI_CR1_SSI

    - -
    -
    - - - - -
    #define SPI_CR1_SSI   SPI_CR1_SSI_Msk
    -
    -

    Internal slave select
    -

    - -
    -
    - -

    ◆ SPI_CR1_SSM_Pos

    - -
    -
    - - - - -
    #define SPI_CR1_SSM_Pos   (9U)
    -
    - -
    -
    - -

    ◆ SPI_CR1_SSM_Msk

    - -
    -
    - - - - -
    #define SPI_CR1_SSM_Msk   (0x1UL << SPI_CR1_SSM_Pos)
    -
    -

    0x00000200

    - -
    -
    - -

    ◆ SPI_CR1_SSM

    - -
    -
    - - - - -
    #define SPI_CR1_SSM   SPI_CR1_SSM_Msk
    -
    -

    Software slave management
    -

    - -
    -
    - -

    ◆ SPI_CR1_RXONLY_Pos

    - -
    -
    - - - - -
    #define SPI_CR1_RXONLY_Pos   (10U)
    -
    - -
    -
    - -

    ◆ SPI_CR1_RXONLY_Msk

    - -
    -
    - - - - -
    #define SPI_CR1_RXONLY_Msk   (0x1UL << SPI_CR1_RXONLY_Pos)
    -
    -

    0x00000400

    - -
    -
    - -

    ◆ SPI_CR1_RXONLY

    - -
    -
    - - - - -
    #define SPI_CR1_RXONLY   SPI_CR1_RXONLY_Msk
    -
    -

    Receive only
    -

    - -
    -
    - -

    ◆ SPI_CR1_DFF_Pos

    - -
    -
    - - - - -
    #define SPI_CR1_DFF_Pos   (11U)
    -
    - -
    -
    - -

    ◆ SPI_CR1_DFF_Msk

    - -
    -
    - - - - -
    #define SPI_CR1_DFF_Msk   (0x1UL << SPI_CR1_DFF_Pos)
    -
    -

    0x00000800

    - -
    -
    - -

    ◆ SPI_CR1_DFF

    - -
    -
    - - - - -
    #define SPI_CR1_DFF   SPI_CR1_DFF_Msk
    -
    -

    Data Frame Format
    -

    - -
    -
    - -

    ◆ SPI_CR1_CRCNEXT_Pos

    - -
    -
    - - - - -
    #define SPI_CR1_CRCNEXT_Pos   (12U)
    -
    - -
    -
    - -

    ◆ SPI_CR1_CRCNEXT_Msk

    - -
    -
    - - - - -
    #define SPI_CR1_CRCNEXT_Msk   (0x1UL << SPI_CR1_CRCNEXT_Pos)
    -
    -

    0x00001000

    - -
    -
    - -

    ◆ SPI_CR1_CRCNEXT

    - -
    -
    - - - - -
    #define SPI_CR1_CRCNEXT   SPI_CR1_CRCNEXT_Msk
    -
    -

    Transmit CRC next
    -

    - -
    -
    - -

    ◆ SPI_CR1_CRCEN_Pos

    - -
    -
    - - - - -
    #define SPI_CR1_CRCEN_Pos   (13U)
    -
    - -
    -
    - -

    ◆ SPI_CR1_CRCEN_Msk

    - -
    -
    - - - - -
    #define SPI_CR1_CRCEN_Msk   (0x1UL << SPI_CR1_CRCEN_Pos)
    -
    -

    0x00002000

    - -
    -
    - -

    ◆ SPI_CR1_CRCEN

    - -
    -
    - - - - -
    #define SPI_CR1_CRCEN   SPI_CR1_CRCEN_Msk
    -
    -

    Hardware CRC calculation enable
    -

    - -
    -
    - -

    ◆ SPI_CR1_BIDIOE_Pos

    - -
    -
    - - - - -
    #define SPI_CR1_BIDIOE_Pos   (14U)
    -
    - -
    -
    - -

    ◆ SPI_CR1_BIDIOE_Msk

    - -
    -
    - - - - -
    #define SPI_CR1_BIDIOE_Msk   (0x1UL << SPI_CR1_BIDIOE_Pos)
    -
    -

    0x00004000

    - -
    -
    - -

    ◆ SPI_CR1_BIDIOE

    - -
    -
    - - - - -
    #define SPI_CR1_BIDIOE   SPI_CR1_BIDIOE_Msk
    -
    -

    Output enable in bidirectional mode

    - -
    -
    - -

    ◆ SPI_CR1_BIDIMODE_Pos

    - -
    -
    - - - - -
    #define SPI_CR1_BIDIMODE_Pos   (15U)
    -
    - -
    -
    - -

    ◆ SPI_CR1_BIDIMODE_Msk

    - -
    -
    - - - - -
    #define SPI_CR1_BIDIMODE_Msk   (0x1UL << SPI_CR1_BIDIMODE_Pos)
    -
    -

    0x00008000

    - -
    -
    - -

    ◆ SPI_CR1_BIDIMODE

    - -
    -
    - - - - -
    #define SPI_CR1_BIDIMODE   SPI_CR1_BIDIMODE_Msk
    -
    -

    Bidirectional data mode enable
    -

    - -
    -
    - -

    ◆ SPI_CR2_RXDMAEN_Pos

    - -
    -
    - - - - -
    #define SPI_CR2_RXDMAEN_Pos   (0U)
    -
    - -
    -
    - -

    ◆ SPI_CR2_RXDMAEN_Msk

    - -
    -
    - - - - -
    #define SPI_CR2_RXDMAEN_Msk   (0x1UL << SPI_CR2_RXDMAEN_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ SPI_CR2_RXDMAEN

    - -
    -
    - - - - -
    #define SPI_CR2_RXDMAEN   SPI_CR2_RXDMAEN_Msk
    -
    -

    Rx Buffer DMA Enable
    -

    - -
    -
    - -

    ◆ SPI_CR2_TXDMAEN_Pos

    - -
    -
    - - - - -
    #define SPI_CR2_TXDMAEN_Pos   (1U)
    -
    - -
    -
    - -

    ◆ SPI_CR2_TXDMAEN_Msk

    - -
    -
    - - - - -
    #define SPI_CR2_TXDMAEN_Msk   (0x1UL << SPI_CR2_TXDMAEN_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ SPI_CR2_TXDMAEN

    - -
    -
    - - - - -
    #define SPI_CR2_TXDMAEN   SPI_CR2_TXDMAEN_Msk
    -
    -

    Tx Buffer DMA Enable
    -

    - -
    -
    - -

    ◆ SPI_CR2_SSOE_Pos

    - -
    -
    - - - - -
    #define SPI_CR2_SSOE_Pos   (2U)
    -
    - -
    -
    - -

    ◆ SPI_CR2_SSOE_Msk

    - -
    -
    - - - - -
    #define SPI_CR2_SSOE_Msk   (0x1UL << SPI_CR2_SSOE_Pos)
    -
    -

    0x00000004

    - -
    -
    - -

    ◆ SPI_CR2_SSOE

    - -
    -
    - - - - -
    #define SPI_CR2_SSOE   SPI_CR2_SSOE_Msk
    -
    -

    SS Output Enable
    -

    - -
    -
    - -

    ◆ SPI_CR2_FRF_Pos

    - -
    -
    - - - - -
    #define SPI_CR2_FRF_Pos   (4U)
    -
    - -
    -
    - -

    ◆ SPI_CR2_FRF_Msk

    - -
    -
    - - - - -
    #define SPI_CR2_FRF_Msk   (0x1UL << SPI_CR2_FRF_Pos)
    -
    -

    0x00000010

    - -
    -
    - -

    ◆ SPI_CR2_FRF

    - -
    -
    - - - - -
    #define SPI_CR2_FRF   SPI_CR2_FRF_Msk
    -
    -

    Frame Format
    -

    - -
    -
    - -

    ◆ SPI_CR2_ERRIE_Pos

    - -
    -
    - - - - -
    #define SPI_CR2_ERRIE_Pos   (5U)
    -
    - -
    -
    - -

    ◆ SPI_CR2_ERRIE_Msk

    - -
    -
    - - - - -
    #define SPI_CR2_ERRIE_Msk   (0x1UL << SPI_CR2_ERRIE_Pos)
    -
    -

    0x00000020

    - -
    -
    - -

    ◆ SPI_CR2_ERRIE

    - -
    -
    - - - - -
    #define SPI_CR2_ERRIE   SPI_CR2_ERRIE_Msk
    -
    -

    Error Interrupt Enable
    -

    - -
    -
    - -

    ◆ SPI_CR2_RXNEIE_Pos

    - -
    -
    - - - - -
    #define SPI_CR2_RXNEIE_Pos   (6U)
    -
    - -
    -
    - -

    ◆ SPI_CR2_RXNEIE_Msk

    - -
    -
    - - - - -
    #define SPI_CR2_RXNEIE_Msk   (0x1UL << SPI_CR2_RXNEIE_Pos)
    -
    -

    0x00000040

    - -
    -
    - -

    ◆ SPI_CR2_RXNEIE

    - -
    -
    - - - - -
    #define SPI_CR2_RXNEIE   SPI_CR2_RXNEIE_Msk
    -
    -

    RX buffer Not Empty Interrupt Enable

    - -
    -
    - -

    ◆ SPI_CR2_TXEIE_Pos

    - -
    -
    - - - - -
    #define SPI_CR2_TXEIE_Pos   (7U)
    -
    - -
    -
    - -

    ◆ SPI_CR2_TXEIE_Msk

    - -
    -
    - - - - -
    #define SPI_CR2_TXEIE_Msk   (0x1UL << SPI_CR2_TXEIE_Pos)
    -
    -

    0x00000080

    - -
    -
    - -

    ◆ SPI_CR2_TXEIE

    - -
    -
    - - - - -
    #define SPI_CR2_TXEIE   SPI_CR2_TXEIE_Msk
    -
    -

    Tx buffer Empty Interrupt Enable
    -

    - -
    -
    - -

    ◆ SPI_SR_RXNE_Pos

    - -
    -
    - - - - -
    #define SPI_SR_RXNE_Pos   (0U)
    -
    - -
    -
    - -

    ◆ SPI_SR_RXNE_Msk

    - -
    -
    - - - - -
    #define SPI_SR_RXNE_Msk   (0x1UL << SPI_SR_RXNE_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ SPI_SR_RXNE

    - -
    -
    - - - - -
    #define SPI_SR_RXNE   SPI_SR_RXNE_Msk
    -
    -

    Receive buffer Not Empty

    - -
    -
    - -

    ◆ SPI_SR_TXE_Pos

    - -
    -
    - - - - -
    #define SPI_SR_TXE_Pos   (1U)
    -
    - -
    -
    - -

    ◆ SPI_SR_TXE_Msk

    - -
    -
    - - - - -
    #define SPI_SR_TXE_Msk   (0x1UL << SPI_SR_TXE_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ SPI_SR_TXE

    - -
    -
    - - - - -
    #define SPI_SR_TXE   SPI_SR_TXE_Msk
    -
    -

    Transmit buffer Empty
    -

    - -
    -
    - -

    ◆ SPI_SR_CHSIDE_Pos

    - -
    -
    - - - - -
    #define SPI_SR_CHSIDE_Pos   (2U)
    -
    - -
    -
    - -

    ◆ SPI_SR_CHSIDE_Msk

    - -
    -
    - - - - -
    #define SPI_SR_CHSIDE_Msk   (0x1UL << SPI_SR_CHSIDE_Pos)
    -
    -

    0x00000004

    - -
    -
    - -

    ◆ SPI_SR_CHSIDE

    - -
    -
    - - - - -
    #define SPI_SR_CHSIDE   SPI_SR_CHSIDE_Msk
    -
    -

    Channel side
    -

    - -
    -
    - -

    ◆ SPI_SR_UDR_Pos

    - -
    -
    - - - - -
    #define SPI_SR_UDR_Pos   (3U)
    -
    - -
    -
    - -

    ◆ SPI_SR_UDR_Msk

    - -
    -
    - - - - -
    #define SPI_SR_UDR_Msk   (0x1UL << SPI_SR_UDR_Pos)
    -
    -

    0x00000008

    - -
    -
    - -

    ◆ SPI_SR_UDR

    - -
    -
    - - - - -
    #define SPI_SR_UDR   SPI_SR_UDR_Msk
    -
    -

    Underrun flag
    -

    - -
    -
    - -

    ◆ SPI_SR_CRCERR_Pos

    - -
    -
    - - - - -
    #define SPI_SR_CRCERR_Pos   (4U)
    -
    - -
    -
    - -

    ◆ SPI_SR_CRCERR_Msk

    - -
    -
    - - - - -
    #define SPI_SR_CRCERR_Msk   (0x1UL << SPI_SR_CRCERR_Pos)
    -
    -

    0x00000010

    - -
    -
    - -

    ◆ SPI_SR_CRCERR

    - -
    -
    - - - - -
    #define SPI_SR_CRCERR   SPI_SR_CRCERR_Msk
    -
    -

    CRC Error flag
    -

    - -
    -
    - -

    ◆ SPI_SR_MODF_Pos

    - -
    -
    - - - - -
    #define SPI_SR_MODF_Pos   (5U)
    -
    - -
    -
    - -

    ◆ SPI_SR_MODF_Msk

    - -
    -
    - - - - -
    #define SPI_SR_MODF_Msk   (0x1UL << SPI_SR_MODF_Pos)
    -
    -

    0x00000020

    - -
    -
    - -

    ◆ SPI_SR_MODF

    - -
    -
    - - - - -
    #define SPI_SR_MODF   SPI_SR_MODF_Msk
    -
    -

    Mode fault
    -

    - -
    -
    - -

    ◆ SPI_SR_OVR_Pos

    - -
    -
    - - - - -
    #define SPI_SR_OVR_Pos   (6U)
    -
    - -
    -
    - -

    ◆ SPI_SR_OVR_Msk

    - -
    -
    - - - - -
    #define SPI_SR_OVR_Msk   (0x1UL << SPI_SR_OVR_Pos)
    -
    -

    0x00000040

    - -
    -
    - -

    ◆ SPI_SR_OVR

    - -
    -
    - - - - -
    #define SPI_SR_OVR   SPI_SR_OVR_Msk
    -
    -

    Overrun flag
    -

    - -
    -
    - -

    ◆ SPI_SR_BSY_Pos

    - -
    -
    - - - - -
    #define SPI_SR_BSY_Pos   (7U)
    -
    - -
    -
    - -

    ◆ SPI_SR_BSY_Msk

    - -
    -
    - - - - -
    #define SPI_SR_BSY_Msk   (0x1UL << SPI_SR_BSY_Pos)
    -
    -

    0x00000080

    - -
    -
    - -

    ◆ SPI_SR_BSY

    - -
    -
    - - - - -
    #define SPI_SR_BSY   SPI_SR_BSY_Msk
    -
    -

    Busy flag
    -

    - -
    -
    - -

    ◆ SPI_SR_FRE_Pos

    - -
    -
    - - - - -
    #define SPI_SR_FRE_Pos   (8U)
    -
    - -
    -
    - -

    ◆ SPI_SR_FRE_Msk

    - -
    -
    - - - - -
    #define SPI_SR_FRE_Msk   (0x1UL << SPI_SR_FRE_Pos)
    -
    -

    0x00000100

    - -
    -
    - -

    ◆ SPI_SR_FRE

    - -
    -
    - - - - -
    #define SPI_SR_FRE   SPI_SR_FRE_Msk
    -
    -

    Frame format error flag
    -

    - -
    -
    - -

    ◆ SPI_DR_DR_Pos

    - -
    -
    - - - - -
    #define SPI_DR_DR_Pos   (0U)
    -
    - -
    -
    - -

    ◆ SPI_DR_DR_Msk

    - -
    -
    - - - - -
    #define SPI_DR_DR_Msk   (0xFFFFUL << SPI_DR_DR_Pos)
    -
    -

    0x0000FFFF

    - -
    -
    - -

    ◆ SPI_DR_DR

    - -
    -
    - - - - -
    #define SPI_DR_DR   SPI_DR_DR_Msk
    -
    -

    Data Register
    -

    - -
    -
    - -

    ◆ SPI_CRCPR_CRCPOLY_Pos

    - -
    -
    - - - - -
    #define SPI_CRCPR_CRCPOLY_Pos   (0U)
    -
    - -
    -
    - -

    ◆ SPI_CRCPR_CRCPOLY_Msk

    - -
    -
    - - - - -
    #define SPI_CRCPR_CRCPOLY_Msk   (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos)
    -
    -

    0x0000FFFF

    - -
    -
    - -

    ◆ SPI_CRCPR_CRCPOLY

    - -
    -
    - - - - -
    #define SPI_CRCPR_CRCPOLY   SPI_CRCPR_CRCPOLY_Msk
    -
    -

    CRC polynomial register

    - -
    -
    - -

    ◆ SPI_RXCRCR_RXCRC_Pos

    - -
    -
    - - - - -
    #define SPI_RXCRCR_RXCRC_Pos   (0U)
    -
    - -
    -
    - -

    ◆ SPI_RXCRCR_RXCRC_Msk

    - -
    -
    - - - - -
    #define SPI_RXCRCR_RXCRC_Msk   (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos)
    -
    -

    0x0000FFFF

    - -
    -
    - -

    ◆ SPI_RXCRCR_RXCRC

    - -
    -
    - - - - -
    #define SPI_RXCRCR_RXCRC   SPI_RXCRCR_RXCRC_Msk
    -
    -

    Rx CRC Register
    -

    - -
    -
    - -

    ◆ SPI_TXCRCR_TXCRC_Pos

    - -
    -
    - - - - -
    #define SPI_TXCRCR_TXCRC_Pos   (0U)
    -
    - -
    -
    - -

    ◆ SPI_TXCRCR_TXCRC_Msk

    - -
    -
    - - - - -
    #define SPI_TXCRCR_TXCRC_Msk   (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos)
    -
    -

    0x0000FFFF

    - -
    -
    - -

    ◆ SPI_TXCRCR_TXCRC

    - -
    -
    - - - - -
    #define SPI_TXCRCR_TXCRC   SPI_TXCRCR_TXCRC_Msk
    -
    -

    Tx CRC Register
    -

    - -
    -
    - -

    ◆ SPI_I2SCFGR_CHLEN_Pos

    - -
    -
    - - - - -
    #define SPI_I2SCFGR_CHLEN_Pos   (0U)
    -
    - -
    -
    - -

    ◆ SPI_I2SCFGR_CHLEN_Msk

    - -
    -
    - - - - -
    #define SPI_I2SCFGR_CHLEN_Msk   (0x1UL << SPI_I2SCFGR_CHLEN_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ SPI_I2SCFGR_CHLEN

    - -
    -
    - - - - -
    #define SPI_I2SCFGR_CHLEN   SPI_I2SCFGR_CHLEN_Msk
    -
    -

    Channel length (number of bits per audio channel)

    - -
    -
    - -

    ◆ SPI_I2SCFGR_DATLEN_Pos

    - -
    -
    - - - - -
    #define SPI_I2SCFGR_DATLEN_Pos   (1U)
    -
    - -
    -
    - -

    ◆ SPI_I2SCFGR_DATLEN_Msk

    - -
    -
    - - - - -
    #define SPI_I2SCFGR_DATLEN_Msk   (0x3UL << SPI_I2SCFGR_DATLEN_Pos)
    -
    -

    0x00000006

    - -
    -
    - -

    ◆ SPI_I2SCFGR_DATLEN

    - -
    -
    - - - - -
    #define SPI_I2SCFGR_DATLEN   SPI_I2SCFGR_DATLEN_Msk
    -
    -

    DATLEN[1:0] bits (Data length to be transferred)
    -

    - -
    -
    - -

    ◆ SPI_I2SCFGR_DATLEN_0

    - -
    -
    - - - - -
    #define SPI_I2SCFGR_DATLEN_0   (0x1UL << SPI_I2SCFGR_DATLEN_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ SPI_I2SCFGR_DATLEN_1

    - -
    -
    - - - - -
    #define SPI_I2SCFGR_DATLEN_1   (0x2UL << SPI_I2SCFGR_DATLEN_Pos)
    -
    -

    0x00000004

    - -
    -
    - -

    ◆ SPI_I2SCFGR_CKPOL_Pos

    - -
    -
    - - - - -
    #define SPI_I2SCFGR_CKPOL_Pos   (3U)
    -
    - -
    -
    - -

    ◆ SPI_I2SCFGR_CKPOL_Msk

    - -
    -
    - - - - -
    #define SPI_I2SCFGR_CKPOL_Msk   (0x1UL << SPI_I2SCFGR_CKPOL_Pos)
    -
    -

    0x00000008

    - -
    -
    - -

    ◆ SPI_I2SCFGR_CKPOL

    - -
    -
    - - - - -
    #define SPI_I2SCFGR_CKPOL   SPI_I2SCFGR_CKPOL_Msk
    -
    -

    steady state clock polarity
    -

    - -
    -
    - -

    ◆ SPI_I2SCFGR_I2SSTD_Pos

    - -
    -
    - - - - -
    #define SPI_I2SCFGR_I2SSTD_Pos   (4U)
    -
    - -
    -
    - -

    ◆ SPI_I2SCFGR_I2SSTD_Msk

    - -
    -
    - - - - -
    #define SPI_I2SCFGR_I2SSTD_Msk   (0x3UL << SPI_I2SCFGR_I2SSTD_Pos)
    -
    -

    0x00000030

    - -
    -
    - -

    ◆ SPI_I2SCFGR_I2SSTD

    - -
    -
    - - - - -
    #define SPI_I2SCFGR_I2SSTD   SPI_I2SCFGR_I2SSTD_Msk
    -
    -

    I2SSTD[1:0] bits (I2S standard selection)

    - -
    -
    - -

    ◆ SPI_I2SCFGR_I2SSTD_0

    - -
    -
    - - - - -
    #define SPI_I2SCFGR_I2SSTD_0   (0x1UL << SPI_I2SCFGR_I2SSTD_Pos)
    -
    -

    0x00000010

    - -
    -
    - -

    ◆ SPI_I2SCFGR_I2SSTD_1

    - -
    -
    - - - - -
    #define SPI_I2SCFGR_I2SSTD_1   (0x2UL << SPI_I2SCFGR_I2SSTD_Pos)
    -
    -

    0x00000020

    - -
    -
    - -

    ◆ SPI_I2SCFGR_PCMSYNC_Pos

    - -
    -
    - - - - -
    #define SPI_I2SCFGR_PCMSYNC_Pos   (7U)
    -
    - -
    -
    - -

    ◆ SPI_I2SCFGR_PCMSYNC_Msk

    - -
    -
    - - - - -
    #define SPI_I2SCFGR_PCMSYNC_Msk   (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos)
    -
    -

    0x00000080

    - -
    -
    - -

    ◆ SPI_I2SCFGR_PCMSYNC

    - -
    -
    - - - - -
    #define SPI_I2SCFGR_PCMSYNC   SPI_I2SCFGR_PCMSYNC_Msk
    -
    -

    PCM frame synchronization
    -

    - -
    -
    - -

    ◆ SPI_I2SCFGR_I2SCFG_Pos

    - -
    -
    - - - - -
    #define SPI_I2SCFGR_I2SCFG_Pos   (8U)
    -
    - -
    -
    - -

    ◆ SPI_I2SCFGR_I2SCFG_Msk

    - -
    -
    - - - - -
    #define SPI_I2SCFGR_I2SCFG_Msk   (0x3UL << SPI_I2SCFGR_I2SCFG_Pos)
    -
    -

    0x00000300

    - -
    -
    - -

    ◆ SPI_I2SCFGR_I2SCFG

    - -
    -
    - - - - -
    #define SPI_I2SCFGR_I2SCFG   SPI_I2SCFGR_I2SCFG_Msk
    -
    -

    I2SCFG[1:0] bits (I2S configuration mode)

    - -
    -
    - -

    ◆ SPI_I2SCFGR_I2SCFG_0

    - -
    -
    - - - - -
    #define SPI_I2SCFGR_I2SCFG_0   (0x1UL << SPI_I2SCFGR_I2SCFG_Pos)
    -
    -

    0x00000100

    - -
    -
    - -

    ◆ SPI_I2SCFGR_I2SCFG_1

    - -
    -
    - - - - -
    #define SPI_I2SCFGR_I2SCFG_1   (0x2UL << SPI_I2SCFGR_I2SCFG_Pos)
    -
    -

    0x00000200

    - -
    -
    - -

    ◆ SPI_I2SCFGR_I2SE_Pos

    - -
    -
    - - - - -
    #define SPI_I2SCFGR_I2SE_Pos   (10U)
    -
    - -
    -
    - -

    ◆ SPI_I2SCFGR_I2SE_Msk

    - -
    -
    - - - - -
    #define SPI_I2SCFGR_I2SE_Msk   (0x1UL << SPI_I2SCFGR_I2SE_Pos)
    -
    -

    0x00000400

    - -
    -
    - -

    ◆ SPI_I2SCFGR_I2SE

    - -
    -
    - - - - -
    #define SPI_I2SCFGR_I2SE   SPI_I2SCFGR_I2SE_Msk
    -
    -

    I2S Enable
    -

    - -
    -
    - -

    ◆ SPI_I2SCFGR_I2SMOD_Pos

    - -
    -
    - - - - -
    #define SPI_I2SCFGR_I2SMOD_Pos   (11U)
    -
    - -
    -
    - -

    ◆ SPI_I2SCFGR_I2SMOD_Msk

    - -
    -
    - - - - -
    #define SPI_I2SCFGR_I2SMOD_Msk   (0x1UL << SPI_I2SCFGR_I2SMOD_Pos)
    -
    -

    0x00000800

    - -
    -
    - -

    ◆ SPI_I2SCFGR_I2SMOD

    - -
    -
    - - - - -
    #define SPI_I2SCFGR_I2SMOD   SPI_I2SCFGR_I2SMOD_Msk
    -
    -

    I2S mode selection

    - -
    -
    - -

    ◆ SPI_I2SPR_I2SDIV_Pos

    - -
    -
    - - - - -
    #define SPI_I2SPR_I2SDIV_Pos   (0U)
    -
    - -
    -
    - -

    ◆ SPI_I2SPR_I2SDIV_Msk

    - -
    -
    - - - - -
    #define SPI_I2SPR_I2SDIV_Msk   (0xFFUL << SPI_I2SPR_I2SDIV_Pos)
    -
    -

    0x000000FF

    - -
    -
    - -

    ◆ SPI_I2SPR_I2SDIV

    - -
    -
    - - - - -
    #define SPI_I2SPR_I2SDIV   SPI_I2SPR_I2SDIV_Msk
    -
    -

    I2S Linear prescaler
    -

    - -
    -
    - -

    ◆ SPI_I2SPR_ODD_Pos

    - -
    -
    - - - - -
    #define SPI_I2SPR_ODD_Pos   (8U)
    -
    - -
    -
    - -

    ◆ SPI_I2SPR_ODD_Msk

    - -
    -
    - - - - -
    #define SPI_I2SPR_ODD_Msk   (0x1UL << SPI_I2SPR_ODD_Pos)
    -
    -

    0x00000100

    - -
    -
    - -

    ◆ SPI_I2SPR_ODD

    - -
    -
    - - - - -
    #define SPI_I2SPR_ODD   SPI_I2SPR_ODD_Msk
    -
    -

    Odd factor for the prescaler

    - -
    -
    - -

    ◆ SPI_I2SPR_MCKOE_Pos

    - -
    -
    - - - - -
    #define SPI_I2SPR_MCKOE_Pos   (9U)
    -
    - -
    -
    - -

    ◆ SPI_I2SPR_MCKOE_Msk

    - -
    -
    - - - - -
    #define SPI_I2SPR_MCKOE_Msk   (0x1UL << SPI_I2SPR_MCKOE_Pos)
    -
    -

    0x00000200

    - -
    -
    - -

    ◆ SPI_I2SPR_MCKOE

    - -
    -
    - - - - -
    #define SPI_I2SPR_MCKOE   SPI_I2SPR_MCKOE_Msk
    -
    -

    Master Clock Output Enable
    -

    - -
    -
    - -

    ◆ SYSCFG_MEMRMP_MEM_MODE_Pos

    - -
    -
    - - - - -
    #define SYSCFG_MEMRMP_MEM_MODE_Pos   (0U)
    -
    - -
    -
    - -

    ◆ SYSCFG_MEMRMP_MEM_MODE_Msk

    - -
    -
    - - - - -
    #define SYSCFG_MEMRMP_MEM_MODE_Msk   (0x3UL << SYSCFG_MEMRMP_MEM_MODE_Pos)
    -
    -

    0x00000003

    - -
    -
    - -

    ◆ SYSCFG_MEMRMP_MEM_MODE

    - -
    -
    - - - - -
    #define SYSCFG_MEMRMP_MEM_MODE   SYSCFG_MEMRMP_MEM_MODE_Msk
    -
    -

    SYSCFG_Memory Remap Config

    - -
    -
    - -

    ◆ SYSCFG_MEMRMP_MEM_MODE_0

    - -
    -
    - - - - -
    #define SYSCFG_MEMRMP_MEM_MODE_0   (0x1UL << SYSCFG_MEMRMP_MEM_MODE_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ SYSCFG_MEMRMP_MEM_MODE_1

    - -
    -
    - - - - -
    #define SYSCFG_MEMRMP_MEM_MODE_1   (0x2UL << SYSCFG_MEMRMP_MEM_MODE_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ SYSCFG_PMC_MII_RMII_SEL_Pos

    - -
    -
    - - - - -
    #define SYSCFG_PMC_MII_RMII_SEL_Pos   (23U)
    -
    - -
    -
    - -

    ◆ SYSCFG_PMC_MII_RMII_SEL_Msk

    - -
    -
    - - - - -
    #define SYSCFG_PMC_MII_RMII_SEL_Msk   (0x1UL << SYSCFG_PMC_MII_RMII_SEL_Pos)
    -
    -

    0x00800000

    - -
    -
    - -

    ◆ SYSCFG_PMC_MII_RMII_SEL

    - -
    -
    - - - - -
    #define SYSCFG_PMC_MII_RMII_SEL   SYSCFG_PMC_MII_RMII_SEL_Msk
    -
    -

    Ethernet PHY interface selection

    - -
    -
    - -

    ◆ SYSCFG_PMC_MII_RMII

    - -
    -
    - - - - -
    #define SYSCFG_PMC_MII_RMII   SYSCFG_PMC_MII_RMII_SEL
    -
    - -
    -
    - -

    ◆ SYSCFG_EXTICR1_EXTI0_Pos

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR1_EXTI0_Pos   (0U)
    -
    - -
    -
    - -

    ◆ SYSCFG_EXTICR1_EXTI0_Msk

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR1_EXTI0_Msk   (0xFUL << SYSCFG_EXTICR1_EXTI0_Pos)
    -
    -

    0x0000000F

    - -
    -
    - -

    ◆ SYSCFG_EXTICR1_EXTI0

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR1_EXTI0   SYSCFG_EXTICR1_EXTI0_Msk
    -
    -

    EXTI 0 configuration

    - -
    -
    - -

    ◆ SYSCFG_EXTICR1_EXTI1_Pos

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR1_EXTI1_Pos   (4U)
    -
    - -
    -
    - -

    ◆ SYSCFG_EXTICR1_EXTI1_Msk

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR1_EXTI1_Msk   (0xFUL << SYSCFG_EXTICR1_EXTI1_Pos)
    -
    -

    0x000000F0

    - -
    -
    - -

    ◆ SYSCFG_EXTICR1_EXTI1

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR1_EXTI1   SYSCFG_EXTICR1_EXTI1_Msk
    -
    -

    EXTI 1 configuration

    - -
    -
    - -

    ◆ SYSCFG_EXTICR1_EXTI2_Pos

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR1_EXTI2_Pos   (8U)
    -
    - -
    -
    - -

    ◆ SYSCFG_EXTICR1_EXTI2_Msk

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR1_EXTI2_Msk   (0xFUL << SYSCFG_EXTICR1_EXTI2_Pos)
    -
    -

    0x00000F00

    - -
    -
    - -

    ◆ SYSCFG_EXTICR1_EXTI2

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR1_EXTI2   SYSCFG_EXTICR1_EXTI2_Msk
    -
    -

    EXTI 2 configuration

    - -
    -
    - -

    ◆ SYSCFG_EXTICR1_EXTI3_Pos

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR1_EXTI3_Pos   (12U)
    -
    - -
    -
    - -

    ◆ SYSCFG_EXTICR1_EXTI3_Msk

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR1_EXTI3_Msk   (0xFUL << SYSCFG_EXTICR1_EXTI3_Pos)
    -
    -

    0x0000F000

    - -
    -
    - -

    ◆ SYSCFG_EXTICR1_EXTI3

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR1_EXTI3   SYSCFG_EXTICR1_EXTI3_Msk
    -
    -

    EXTI 3 configuration

    - -
    -
    - -

    ◆ SYSCFG_EXTICR1_EXTI0_PA

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR1_EXTI0_PA   0x0000U
    -
    - -

    EXTI0 configuration
    -

    -

    PA[0] pin

    - -
    -
    - -

    ◆ SYSCFG_EXTICR1_EXTI0_PB

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR1_EXTI0_PB   0x0001U
    -
    -

    PB[0] pin

    - -
    -
    - -

    ◆ SYSCFG_EXTICR1_EXTI0_PC

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR1_EXTI0_PC   0x0002U
    -
    -

    PC[0] pin

    - -
    -
    - -

    ◆ SYSCFG_EXTICR1_EXTI0_PD

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR1_EXTI0_PD   0x0003U
    -
    -

    PD[0] pin

    - -
    -
    - -

    ◆ SYSCFG_EXTICR1_EXTI0_PE

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR1_EXTI0_PE   0x0004U
    -
    -

    PE[0] pin

    - -
    -
    - -

    ◆ SYSCFG_EXTICR1_EXTI0_PF

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR1_EXTI0_PF   0x0005U
    -
    -

    PF[0] pin

    - -
    -
    - -

    ◆ SYSCFG_EXTICR1_EXTI0_PG

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR1_EXTI0_PG   0x0006U
    -
    -

    PG[0] pin

    - -
    -
    - -

    ◆ SYSCFG_EXTICR1_EXTI0_PH

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR1_EXTI0_PH   0x0007U
    -
    -

    PH[0] pin

    - -
    -
    - -

    ◆ SYSCFG_EXTICR1_EXTI0_PI

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR1_EXTI0_PI   0x0008U
    -
    -

    PI[0] pin

    - -
    -
    - -

    ◆ SYSCFG_EXTICR1_EXTI1_PA

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR1_EXTI1_PA   0x0000U
    -
    - -

    EXTI1 configuration
    -

    -

    PA[1] pin

    - -
    -
    - -

    ◆ SYSCFG_EXTICR1_EXTI1_PB

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR1_EXTI1_PB   0x0010U
    -
    -

    PB[1] pin

    - -
    -
    - -

    ◆ SYSCFG_EXTICR1_EXTI1_PC

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR1_EXTI1_PC   0x0020U
    -
    -

    PC[1] pin

    - -
    -
    - -

    ◆ SYSCFG_EXTICR1_EXTI1_PD

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR1_EXTI1_PD   0x0030U
    -
    -

    PD[1] pin

    - -
    -
    - -

    ◆ SYSCFG_EXTICR1_EXTI1_PE

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR1_EXTI1_PE   0x0040U
    -
    -

    PE[1] pin

    - -
    -
    - -

    ◆ SYSCFG_EXTICR1_EXTI1_PF

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR1_EXTI1_PF   0x0050U
    -
    -

    PF[1] pin

    - -
    -
    - -

    ◆ SYSCFG_EXTICR1_EXTI1_PG

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR1_EXTI1_PG   0x0060U
    -
    -

    PG[1] pin

    - -
    -
    - -

    ◆ SYSCFG_EXTICR1_EXTI1_PH

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR1_EXTI1_PH   0x0070U
    -
    -

    PH[1] pin

    - -
    -
    - -

    ◆ SYSCFG_EXTICR1_EXTI1_PI

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR1_EXTI1_PI   0x0080U
    -
    -

    PI[1] pin

    - -
    -
    - -

    ◆ SYSCFG_EXTICR1_EXTI2_PA

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR1_EXTI2_PA   0x0000U
    -
    - -

    EXTI2 configuration
    -

    -

    PA[2] pin

    - -
    -
    - -

    ◆ SYSCFG_EXTICR1_EXTI2_PB

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR1_EXTI2_PB   0x0100U
    -
    -

    PB[2] pin

    - -
    -
    - -

    ◆ SYSCFG_EXTICR1_EXTI2_PC

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR1_EXTI2_PC   0x0200U
    -
    -

    PC[2] pin

    - -
    -
    - -

    ◆ SYSCFG_EXTICR1_EXTI2_PD

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR1_EXTI2_PD   0x0300U
    -
    -

    PD[2] pin

    - -
    -
    - -

    ◆ SYSCFG_EXTICR1_EXTI2_PE

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR1_EXTI2_PE   0x0400U
    -
    -

    PE[2] pin

    - -
    -
    - -

    ◆ SYSCFG_EXTICR1_EXTI2_PF

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR1_EXTI2_PF   0x0500U
    -
    -

    PF[2] pin

    - -
    -
    - -

    ◆ SYSCFG_EXTICR1_EXTI2_PG

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR1_EXTI2_PG   0x0600U
    -
    -

    PG[2] pin

    - -
    -
    - -

    ◆ SYSCFG_EXTICR1_EXTI2_PH

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR1_EXTI2_PH   0x0700U
    -
    -

    PH[2] pin

    - -
    -
    - -

    ◆ SYSCFG_EXTICR1_EXTI2_PI

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR1_EXTI2_PI   0x0800U
    -
    -

    PI[2] pin

    - -
    -
    - -

    ◆ SYSCFG_EXTICR1_EXTI3_PA

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR1_EXTI3_PA   0x0000U
    -
    - -

    EXTI3 configuration
    -

    -

    PA[3] pin

    - -
    -
    - -

    ◆ SYSCFG_EXTICR1_EXTI3_PB

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR1_EXTI3_PB   0x1000U
    -
    -

    PB[3] pin

    - -
    -
    - -

    ◆ SYSCFG_EXTICR1_EXTI3_PC

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR1_EXTI3_PC   0x2000U
    -
    -

    PC[3] pin

    - -
    -
    - -

    ◆ SYSCFG_EXTICR1_EXTI3_PD

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR1_EXTI3_PD   0x3000U
    -
    -

    PD[3] pin

    - -
    -
    - -

    ◆ SYSCFG_EXTICR1_EXTI3_PE

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR1_EXTI3_PE   0x4000U
    -
    -

    PE[3] pin

    - -
    -
    - -

    ◆ SYSCFG_EXTICR1_EXTI3_PF

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR1_EXTI3_PF   0x5000U
    -
    -

    PF[3] pin

    - -
    -
    - -

    ◆ SYSCFG_EXTICR1_EXTI3_PG

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR1_EXTI3_PG   0x6000U
    -
    -

    PG[3] pin

    - -
    -
    - -

    ◆ SYSCFG_EXTICR1_EXTI3_PH

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR1_EXTI3_PH   0x7000U
    -
    -

    PH[3] pin

    - -
    -
    - -

    ◆ SYSCFG_EXTICR1_EXTI3_PI

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR1_EXTI3_PI   0x8000U
    -
    -

    PI[3] pin

    - -
    -
    - -

    ◆ SYSCFG_EXTICR2_EXTI4_Pos

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR2_EXTI4_Pos   (0U)
    -
    - -
    -
    - -

    ◆ SYSCFG_EXTICR2_EXTI4_Msk

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR2_EXTI4_Msk   (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos)
    -
    -

    0x0000000F

    - -
    -
    - -

    ◆ SYSCFG_EXTICR2_EXTI4

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR2_EXTI4   SYSCFG_EXTICR2_EXTI4_Msk
    -
    -

    EXTI 4 configuration

    - -
    -
    - -

    ◆ SYSCFG_EXTICR2_EXTI5_Pos

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR2_EXTI5_Pos   (4U)
    -
    - -
    -
    - -

    ◆ SYSCFG_EXTICR2_EXTI5_Msk

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR2_EXTI5_Msk   (0xFUL << SYSCFG_EXTICR2_EXTI5_Pos)
    -
    -

    0x000000F0

    - -
    -
    - -

    ◆ SYSCFG_EXTICR2_EXTI5

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR2_EXTI5   SYSCFG_EXTICR2_EXTI5_Msk
    -
    -

    EXTI 5 configuration

    - -
    -
    - -

    ◆ SYSCFG_EXTICR2_EXTI6_Pos

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR2_EXTI6_Pos   (8U)
    -
    - -
    -
    - -

    ◆ SYSCFG_EXTICR2_EXTI6_Msk

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR2_EXTI6_Msk   (0xFUL << SYSCFG_EXTICR2_EXTI6_Pos)
    -
    -

    0x00000F00

    - -
    -
    - -

    ◆ SYSCFG_EXTICR2_EXTI6

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR2_EXTI6   SYSCFG_EXTICR2_EXTI6_Msk
    -
    -

    EXTI 6 configuration

    - -
    -
    - -

    ◆ SYSCFG_EXTICR2_EXTI7_Pos

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR2_EXTI7_Pos   (12U)
    -
    - -
    -
    - -

    ◆ SYSCFG_EXTICR2_EXTI7_Msk

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR2_EXTI7_Msk   (0xFUL << SYSCFG_EXTICR2_EXTI7_Pos)
    -
    -

    0x0000F000

    - -
    -
    - -

    ◆ SYSCFG_EXTICR2_EXTI7

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR2_EXTI7   SYSCFG_EXTICR2_EXTI7_Msk
    -
    -

    EXTI 7 configuration

    - -
    -
    - -

    ◆ SYSCFG_EXTICR2_EXTI4_PA

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR2_EXTI4_PA   0x0000U
    -
    - -

    EXTI4 configuration
    -

    -

    PA[4] pin

    - -
    -
    - -

    ◆ SYSCFG_EXTICR2_EXTI4_PB

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR2_EXTI4_PB   0x0001U
    -
    -

    PB[4] pin

    - -
    -
    - -

    ◆ SYSCFG_EXTICR2_EXTI4_PC

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR2_EXTI4_PC   0x0002U
    -
    -

    PC[4] pin

    - -
    -
    - -

    ◆ SYSCFG_EXTICR2_EXTI4_PD

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR2_EXTI4_PD   0x0003U
    -
    -

    PD[4] pin

    - -
    -
    - -

    ◆ SYSCFG_EXTICR2_EXTI4_PE

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR2_EXTI4_PE   0x0004U
    -
    -

    PE[4] pin

    - -
    -
    - -

    ◆ SYSCFG_EXTICR2_EXTI4_PF

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR2_EXTI4_PF   0x0005U
    -
    -

    PF[4] pin

    - -
    -
    - -

    ◆ SYSCFG_EXTICR2_EXTI4_PG

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR2_EXTI4_PG   0x0006U
    -
    -

    PG[4] pin

    - -
    -
    - -

    ◆ SYSCFG_EXTICR2_EXTI4_PH

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR2_EXTI4_PH   0x0007U
    -
    -

    PH[4] pin

    - -
    -
    - -

    ◆ SYSCFG_EXTICR2_EXTI4_PI

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR2_EXTI4_PI   0x0008U
    -
    -

    PI[4] pin

    - -
    -
    - -

    ◆ SYSCFG_EXTICR2_EXTI5_PA

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR2_EXTI5_PA   0x0000U
    -
    - -

    EXTI5 configuration
    -

    -

    PA[5] pin

    - -
    -
    - -

    ◆ SYSCFG_EXTICR2_EXTI5_PB

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR2_EXTI5_PB   0x0010U
    -
    -

    PB[5] pin

    - -
    -
    - -

    ◆ SYSCFG_EXTICR2_EXTI5_PC

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR2_EXTI5_PC   0x0020U
    -
    -

    PC[5] pin

    - -
    -
    - -

    ◆ SYSCFG_EXTICR2_EXTI5_PD

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR2_EXTI5_PD   0x0030U
    -
    -

    PD[5] pin

    - -
    -
    - -

    ◆ SYSCFG_EXTICR2_EXTI5_PE

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR2_EXTI5_PE   0x0040U
    -
    -

    PE[5] pin

    - -
    -
    - -

    ◆ SYSCFG_EXTICR2_EXTI5_PF

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR2_EXTI5_PF   0x0050U
    -
    -

    PF[5] pin

    - -
    -
    - -

    ◆ SYSCFG_EXTICR2_EXTI5_PG

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR2_EXTI5_PG   0x0060U
    -
    -

    PG[5] pin

    - -
    -
    - -

    ◆ SYSCFG_EXTICR2_EXTI5_PH

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR2_EXTI5_PH   0x0070U
    -
    -

    PH[5] pin

    - -
    -
    - -

    ◆ SYSCFG_EXTICR2_EXTI5_PI

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR2_EXTI5_PI   0x0080U
    -
    -

    PI[5] pin

    - -
    -
    - -

    ◆ SYSCFG_EXTICR2_EXTI6_PA

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR2_EXTI6_PA   0x0000U
    -
    - -

    EXTI6 configuration
    -

    -

    PA[6] pin

    - -
    -
    - -

    ◆ SYSCFG_EXTICR2_EXTI6_PB

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR2_EXTI6_PB   0x0100U
    -
    -

    PB[6] pin

    - -
    -
    - -

    ◆ SYSCFG_EXTICR2_EXTI6_PC

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR2_EXTI6_PC   0x0200U
    -
    -

    PC[6] pin

    - -
    -
    - -

    ◆ SYSCFG_EXTICR2_EXTI6_PD

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR2_EXTI6_PD   0x0300U
    -
    -

    PD[6] pin

    - -
    -
    - -

    ◆ SYSCFG_EXTICR2_EXTI6_PE

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR2_EXTI6_PE   0x0400U
    -
    -

    PE[6] pin

    - -
    -
    - -

    ◆ SYSCFG_EXTICR2_EXTI6_PF

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR2_EXTI6_PF   0x0500U
    -
    -

    PF[6] pin

    - -
    -
    - -

    ◆ SYSCFG_EXTICR2_EXTI6_PG

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR2_EXTI6_PG   0x0600U
    -
    -

    PG[6] pin

    - -
    -
    - -

    ◆ SYSCFG_EXTICR2_EXTI6_PH

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR2_EXTI6_PH   0x0700U
    -
    -

    PH[6] pin

    - -
    -
    - -

    ◆ SYSCFG_EXTICR2_EXTI6_PI

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR2_EXTI6_PI   0x0800U
    -
    -

    PI[6] pin

    - -
    -
    - -

    ◆ SYSCFG_EXTICR2_EXTI7_PA

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR2_EXTI7_PA   0x0000U
    -
    - -

    EXTI7 configuration
    -

    -

    PA[7] pin

    - -
    -
    - -

    ◆ SYSCFG_EXTICR2_EXTI7_PB

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR2_EXTI7_PB   0x1000U
    -
    -

    PB[7] pin

    - -
    -
    - -

    ◆ SYSCFG_EXTICR2_EXTI7_PC

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR2_EXTI7_PC   0x2000U
    -
    -

    PC[7] pin

    - -
    -
    - -

    ◆ SYSCFG_EXTICR2_EXTI7_PD

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR2_EXTI7_PD   0x3000U
    -
    -

    PD[7] pin

    - -
    -
    - -

    ◆ SYSCFG_EXTICR2_EXTI7_PE

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR2_EXTI7_PE   0x4000U
    -
    -

    PE[7] pin

    - -
    -
    - -

    ◆ SYSCFG_EXTICR2_EXTI7_PF

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR2_EXTI7_PF   0x5000U
    -
    -

    PF[7] pin

    - -
    -
    - -

    ◆ SYSCFG_EXTICR2_EXTI7_PG

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR2_EXTI7_PG   0x6000U
    -
    -

    PG[7] pin

    - -
    -
    - -

    ◆ SYSCFG_EXTICR2_EXTI7_PH

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR2_EXTI7_PH   0x7000U
    -
    -

    PH[7] pin

    - -
    -
    - -

    ◆ SYSCFG_EXTICR2_EXTI7_PI

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR2_EXTI7_PI   0x8000U
    -
    -

    PI[7] pin

    - -
    -
    - -

    ◆ SYSCFG_EXTICR3_EXTI8_Pos

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR3_EXTI8_Pos   (0U)
    -
    - -
    -
    - -

    ◆ SYSCFG_EXTICR3_EXTI8_Msk

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR3_EXTI8_Msk   (0xFUL << SYSCFG_EXTICR3_EXTI8_Pos)
    -
    -

    0x0000000F

    - -
    -
    - -

    ◆ SYSCFG_EXTICR3_EXTI8

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR3_EXTI8   SYSCFG_EXTICR3_EXTI8_Msk
    -
    -

    EXTI 8 configuration

    - -
    -
    - -

    ◆ SYSCFG_EXTICR3_EXTI9_Pos

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR3_EXTI9_Pos   (4U)
    -
    - -
    -
    - -

    ◆ SYSCFG_EXTICR3_EXTI9_Msk

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR3_EXTI9_Msk   (0xFUL << SYSCFG_EXTICR3_EXTI9_Pos)
    -
    -

    0x000000F0

    - -
    -
    - -

    ◆ SYSCFG_EXTICR3_EXTI9

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR3_EXTI9   SYSCFG_EXTICR3_EXTI9_Msk
    -
    -

    EXTI 9 configuration

    - -
    -
    - -

    ◆ SYSCFG_EXTICR3_EXTI10_Pos

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR3_EXTI10_Pos   (8U)
    -
    - -
    -
    - -

    ◆ SYSCFG_EXTICR3_EXTI10_Msk

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR3_EXTI10_Msk   (0xFUL << SYSCFG_EXTICR3_EXTI10_Pos)
    -
    -

    0x00000F00

    - -
    -
    - -

    ◆ SYSCFG_EXTICR3_EXTI10

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR3_EXTI10   SYSCFG_EXTICR3_EXTI10_Msk
    -
    -

    EXTI 10 configuration

    - -
    -
    - -

    ◆ SYSCFG_EXTICR3_EXTI11_Pos

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR3_EXTI11_Pos   (12U)
    -
    - -
    -
    - -

    ◆ SYSCFG_EXTICR3_EXTI11_Msk

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR3_EXTI11_Msk   (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos)
    -
    -

    0x0000F000

    - -
    -
    - -

    ◆ SYSCFG_EXTICR3_EXTI11

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR3_EXTI11   SYSCFG_EXTICR3_EXTI11_Msk
    -
    -

    EXTI 11 configuration

    - -
    -
    - -

    ◆ SYSCFG_EXTICR3_EXTI8_PA

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR3_EXTI8_PA   0x0000U
    -
    - -

    EXTI8 configuration
    -

    -

    PA[8] pin

    - -
    -
    - -

    ◆ SYSCFG_EXTICR3_EXTI8_PB

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR3_EXTI8_PB   0x0001U
    -
    -

    PB[8] pin

    - -
    -
    - -

    ◆ SYSCFG_EXTICR3_EXTI8_PC

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR3_EXTI8_PC   0x0002U
    -
    -

    PC[8] pin

    - -
    -
    - -

    ◆ SYSCFG_EXTICR3_EXTI8_PD

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR3_EXTI8_PD   0x0003U
    -
    -

    PD[8] pin

    - -
    -
    - -

    ◆ SYSCFG_EXTICR3_EXTI8_PE

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR3_EXTI8_PE   0x0004U
    -
    -

    PE[8] pin

    - -
    -
    - -

    ◆ SYSCFG_EXTICR3_EXTI8_PF

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR3_EXTI8_PF   0x0005U
    -
    -

    PF[8] pin

    - -
    -
    - -

    ◆ SYSCFG_EXTICR3_EXTI8_PG

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR3_EXTI8_PG   0x0006U
    -
    -

    PG[8] pin

    - -
    -
    - -

    ◆ SYSCFG_EXTICR3_EXTI8_PH

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR3_EXTI8_PH   0x0007U
    -
    -

    PH[8] pin

    - -
    -
    - -

    ◆ SYSCFG_EXTICR3_EXTI8_PI

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR3_EXTI8_PI   0x0008U
    -
    -

    PI[8] pin

    - -
    -
    - -

    ◆ SYSCFG_EXTICR3_EXTI9_PA

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR3_EXTI9_PA   0x0000U
    -
    - -

    EXTI9 configuration
    -

    -

    PA[9] pin

    - -
    -
    - -

    ◆ SYSCFG_EXTICR3_EXTI9_PB

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR3_EXTI9_PB   0x0010U
    -
    -

    PB[9] pin

    - -
    -
    - -

    ◆ SYSCFG_EXTICR3_EXTI9_PC

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR3_EXTI9_PC   0x0020U
    -
    -

    PC[9] pin

    - -
    -
    - -

    ◆ SYSCFG_EXTICR3_EXTI9_PD

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR3_EXTI9_PD   0x0030U
    -
    -

    PD[9] pin

    - -
    -
    - -

    ◆ SYSCFG_EXTICR3_EXTI9_PE

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR3_EXTI9_PE   0x0040U
    -
    -

    PE[9] pin

    - -
    -
    - -

    ◆ SYSCFG_EXTICR3_EXTI9_PF

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR3_EXTI9_PF   0x0050U
    -
    -

    PF[9] pin

    - -
    -
    - -

    ◆ SYSCFG_EXTICR3_EXTI9_PG

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR3_EXTI9_PG   0x0060U
    -
    -

    PG[9] pin

    - -
    -
    - -

    ◆ SYSCFG_EXTICR3_EXTI9_PH

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR3_EXTI9_PH   0x0070U
    -
    -

    PH[9] pin

    - -
    -
    - -

    ◆ SYSCFG_EXTICR3_EXTI9_PI

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR3_EXTI9_PI   0x0080U
    -
    -

    PI[9] pin

    - -
    -
    - -

    ◆ SYSCFG_EXTICR3_EXTI10_PA

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR3_EXTI10_PA   0x0000U
    -
    - -

    EXTI10 configuration
    -

    -

    PA[10] pin

    - -
    -
    - -

    ◆ SYSCFG_EXTICR3_EXTI10_PB

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR3_EXTI10_PB   0x0100U
    -
    -

    PB[10] pin

    - -
    -
    - -

    ◆ SYSCFG_EXTICR3_EXTI10_PC

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR3_EXTI10_PC   0x0200U
    -
    -

    PC[10] pin

    - -
    -
    - -

    ◆ SYSCFG_EXTICR3_EXTI10_PD

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR3_EXTI10_PD   0x0300U
    -
    -

    PD[10] pin

    - -
    -
    - -

    ◆ SYSCFG_EXTICR3_EXTI10_PE

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR3_EXTI10_PE   0x0400U
    -
    -

    PE[10] pin

    - -
    -
    - -

    ◆ SYSCFG_EXTICR3_EXTI10_PF

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR3_EXTI10_PF   0x0500U
    -
    -

    PF[10] pin

    - -
    -
    - -

    ◆ SYSCFG_EXTICR3_EXTI10_PG

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR3_EXTI10_PG   0x0600U
    -
    -

    PG[10] pin

    - -
    -
    - -

    ◆ SYSCFG_EXTICR3_EXTI10_PH

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR3_EXTI10_PH   0x0700U
    -
    -

    PH[10] pin

    - -
    -
    - -

    ◆ SYSCFG_EXTICR3_EXTI10_PI

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR3_EXTI10_PI   0x0800U
    -
    -

    PI[10] pin

    - -
    -
    - -

    ◆ SYSCFG_EXTICR3_EXTI11_PA

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR3_EXTI11_PA   0x0000U
    -
    - -

    EXTI11 configuration
    -

    -

    PA[11] pin

    - -
    -
    - -

    ◆ SYSCFG_EXTICR3_EXTI11_PB

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR3_EXTI11_PB   0x1000U
    -
    -

    PB[11] pin

    - -
    -
    - -

    ◆ SYSCFG_EXTICR3_EXTI11_PC

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR3_EXTI11_PC   0x2000U
    -
    -

    PC[11] pin

    - -
    -
    - -

    ◆ SYSCFG_EXTICR3_EXTI11_PD

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR3_EXTI11_PD   0x3000U
    -
    -

    PD[11] pin

    - -
    -
    - -

    ◆ SYSCFG_EXTICR3_EXTI11_PE

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR3_EXTI11_PE   0x4000U
    -
    -

    PE[11] pin

    - -
    -
    - -

    ◆ SYSCFG_EXTICR3_EXTI11_PF

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR3_EXTI11_PF   0x5000U
    -
    -

    PF[11] pin

    - -
    -
    - -

    ◆ SYSCFG_EXTICR3_EXTI11_PG

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR3_EXTI11_PG   0x6000U
    -
    -

    PG[11] pin

    - -
    -
    - -

    ◆ SYSCFG_EXTICR3_EXTI11_PH

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR3_EXTI11_PH   0x7000U
    -
    -

    PH[11] pin

    - -
    -
    - -

    ◆ SYSCFG_EXTICR3_EXTI11_PI

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR3_EXTI11_PI   0x8000U
    -
    -

    PI[11] pin

    - -
    -
    - -

    ◆ SYSCFG_EXTICR4_EXTI12_Pos

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR4_EXTI12_Pos   (0U)
    -
    - -
    -
    - -

    ◆ SYSCFG_EXTICR4_EXTI12_Msk

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR4_EXTI12_Msk   (0xFUL << SYSCFG_EXTICR4_EXTI12_Pos)
    -
    -

    0x0000000F

    - -
    -
    - -

    ◆ SYSCFG_EXTICR4_EXTI12

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR4_EXTI12   SYSCFG_EXTICR4_EXTI12_Msk
    -
    -

    EXTI 12 configuration

    - -
    -
    - -

    ◆ SYSCFG_EXTICR4_EXTI13_Pos

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR4_EXTI13_Pos   (4U)
    -
    - -
    -
    - -

    ◆ SYSCFG_EXTICR4_EXTI13_Msk

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR4_EXTI13_Msk   (0xFUL << SYSCFG_EXTICR4_EXTI13_Pos)
    -
    -

    0x000000F0

    - -
    -
    - -

    ◆ SYSCFG_EXTICR4_EXTI13

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR4_EXTI13   SYSCFG_EXTICR4_EXTI13_Msk
    -
    -

    EXTI 13 configuration

    - -
    -
    - -

    ◆ SYSCFG_EXTICR4_EXTI14_Pos

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR4_EXTI14_Pos   (8U)
    -
    - -
    -
    - -

    ◆ SYSCFG_EXTICR4_EXTI14_Msk

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR4_EXTI14_Msk   (0xFUL << SYSCFG_EXTICR4_EXTI14_Pos)
    -
    -

    0x00000F00

    - -
    -
    - -

    ◆ SYSCFG_EXTICR4_EXTI14

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR4_EXTI14   SYSCFG_EXTICR4_EXTI14_Msk
    -
    -

    EXTI 14 configuration

    - -
    -
    - -

    ◆ SYSCFG_EXTICR4_EXTI15_Pos

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR4_EXTI15_Pos   (12U)
    -
    - -
    -
    - -

    ◆ SYSCFG_EXTICR4_EXTI15_Msk

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR4_EXTI15_Msk   (0xFUL << SYSCFG_EXTICR4_EXTI15_Pos)
    -
    -

    0x0000F000

    - -
    -
    - -

    ◆ SYSCFG_EXTICR4_EXTI15

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR4_EXTI15   SYSCFG_EXTICR4_EXTI15_Msk
    -
    -

    EXTI 15 configuration

    - -
    -
    - -

    ◆ SYSCFG_EXTICR4_EXTI12_PA

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR4_EXTI12_PA   0x0000U
    -
    - -

    EXTI12 configuration
    -

    -

    PA[12] pin

    - -
    -
    - -

    ◆ SYSCFG_EXTICR4_EXTI12_PB

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR4_EXTI12_PB   0x0001U
    -
    -

    PB[12] pin

    - -
    -
    - -

    ◆ SYSCFG_EXTICR4_EXTI12_PC

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR4_EXTI12_PC   0x0002U
    -
    -

    PC[12] pin

    - -
    -
    - -

    ◆ SYSCFG_EXTICR4_EXTI12_PD

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR4_EXTI12_PD   0x0003U
    -
    -

    PD[12] pin

    - -
    -
    - -

    ◆ SYSCFG_EXTICR4_EXTI12_PE

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR4_EXTI12_PE   0x0004U
    -
    -

    PE[12] pin

    - -
    -
    - -

    ◆ SYSCFG_EXTICR4_EXTI12_PF

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR4_EXTI12_PF   0x0005U
    -
    -

    PF[12] pin

    - -
    -
    - -

    ◆ SYSCFG_EXTICR4_EXTI12_PG

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR4_EXTI12_PG   0x0006U
    -
    -

    PG[12] pin

    - -
    -
    - -

    ◆ SYSCFG_EXTICR4_EXTI12_PH

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR4_EXTI12_PH   0x0007U
    -
    -

    PH[12] pin

    - -
    -
    - -

    ◆ SYSCFG_EXTICR4_EXTI13_PA

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR4_EXTI13_PA   0x0000U
    -
    - -

    EXTI13 configuration
    -

    -

    PA[13] pin

    - -
    -
    - -

    ◆ SYSCFG_EXTICR4_EXTI13_PB

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR4_EXTI13_PB   0x0010U
    -
    -

    PB[13] pin

    - -
    -
    - -

    ◆ SYSCFG_EXTICR4_EXTI13_PC

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR4_EXTI13_PC   0x0020U
    -
    -

    PC[13] pin

    - -
    -
    - -

    ◆ SYSCFG_EXTICR4_EXTI13_PD

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR4_EXTI13_PD   0x0030U
    -
    -

    PD[13] pin

    - -
    -
    - -

    ◆ SYSCFG_EXTICR4_EXTI13_PE

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR4_EXTI13_PE   0x0040U
    -
    -

    PE[13] pin

    - -
    -
    - -

    ◆ SYSCFG_EXTICR4_EXTI13_PF

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR4_EXTI13_PF   0x0050U
    -
    -

    PF[13] pin

    - -
    -
    - -

    ◆ SYSCFG_EXTICR4_EXTI13_PG

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR4_EXTI13_PG   0x0060U
    -
    -

    PG[13] pin

    - -
    -
    - -

    ◆ SYSCFG_EXTICR4_EXTI13_PH

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR4_EXTI13_PH   0x0070U
    -
    -

    PH[13] pin

    - -
    -
    - -

    ◆ SYSCFG_EXTICR4_EXTI14_PA

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR4_EXTI14_PA   0x0000U
    -
    - -

    EXTI14 configuration
    -

    -

    PA[14] pin

    - -
    -
    - -

    ◆ SYSCFG_EXTICR4_EXTI14_PB

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR4_EXTI14_PB   0x0100U
    -
    -

    PB[14] pin

    - -
    -
    - -

    ◆ SYSCFG_EXTICR4_EXTI14_PC

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR4_EXTI14_PC   0x0200U
    -
    -

    PC[14] pin

    - -
    -
    - -

    ◆ SYSCFG_EXTICR4_EXTI14_PD

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR4_EXTI14_PD   0x0300U
    -
    -

    PD[14] pin

    - -
    -
    - -

    ◆ SYSCFG_EXTICR4_EXTI14_PE

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR4_EXTI14_PE   0x0400U
    -
    -

    PE[14] pin

    - -
    -
    - -

    ◆ SYSCFG_EXTICR4_EXTI14_PF

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR4_EXTI14_PF   0x0500U
    -
    -

    PF[14] pin

    - -
    -
    - -

    ◆ SYSCFG_EXTICR4_EXTI14_PG

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR4_EXTI14_PG   0x0600U
    -
    -

    PG[14] pin

    - -
    -
    - -

    ◆ SYSCFG_EXTICR4_EXTI14_PH

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR4_EXTI14_PH   0x0700U
    -
    -

    PH[14] pin

    - -
    -
    - -

    ◆ SYSCFG_EXTICR4_EXTI15_PA

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR4_EXTI15_PA   0x0000U
    -
    - -

    EXTI15 configuration
    -

    -

    PA[15] pin

    - -
    -
    - -

    ◆ SYSCFG_EXTICR4_EXTI15_PB

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR4_EXTI15_PB   0x1000U
    -
    -

    PB[15] pin

    - -
    -
    - -

    ◆ SYSCFG_EXTICR4_EXTI15_PC

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR4_EXTI15_PC   0x2000U
    -
    -

    PC[15] pin

    - -
    -
    - -

    ◆ SYSCFG_EXTICR4_EXTI15_PD

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR4_EXTI15_PD   0x3000U
    -
    -

    PD[15] pin

    - -
    -
    - -

    ◆ SYSCFG_EXTICR4_EXTI15_PE

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR4_EXTI15_PE   0x4000U
    -
    -

    PE[15] pin

    - -
    -
    - -

    ◆ SYSCFG_EXTICR4_EXTI15_PF

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR4_EXTI15_PF   0x5000U
    -
    -

    PF[15] pin

    - -
    -
    - -

    ◆ SYSCFG_EXTICR4_EXTI15_PG

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR4_EXTI15_PG   0x6000U
    -
    -

    PG[15] pin

    - -
    -
    - -

    ◆ SYSCFG_EXTICR4_EXTI15_PH

    - -
    -
    - - - - -
    #define SYSCFG_EXTICR4_EXTI15_PH   0x7000U
    -
    -

    PH[15] pin

    - -
    -
    - -

    ◆ SYSCFG_CMPCR_CMP_PD_Pos

    - -
    -
    - - - - -
    #define SYSCFG_CMPCR_CMP_PD_Pos   (0U)
    -
    - -
    -
    - -

    ◆ SYSCFG_CMPCR_CMP_PD_Msk

    - -
    -
    - - - - -
    #define SYSCFG_CMPCR_CMP_PD_Msk   (0x1UL << SYSCFG_CMPCR_CMP_PD_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ SYSCFG_CMPCR_CMP_PD

    - -
    -
    - - - - -
    #define SYSCFG_CMPCR_CMP_PD   SYSCFG_CMPCR_CMP_PD_Msk
    -
    -

    Compensation cell ready flag

    - -
    -
    - -

    ◆ SYSCFG_CMPCR_READY_Pos

    - -
    -
    - - - - -
    #define SYSCFG_CMPCR_READY_Pos   (8U)
    -
    - -
    -
    - -

    ◆ SYSCFG_CMPCR_READY_Msk

    - -
    -
    - - - - -
    #define SYSCFG_CMPCR_READY_Msk   (0x1UL << SYSCFG_CMPCR_READY_Pos)
    -
    -

    0x00000100

    - -
    -
    - -

    ◆ SYSCFG_CMPCR_READY

    - -
    -
    - - - - -
    #define SYSCFG_CMPCR_READY   SYSCFG_CMPCR_READY_Msk
    -
    -

    Compensation cell power-down

    - -
    -
    - -

    ◆ TIM_CR1_CEN_Pos

    - -
    -
    - - - - -
    #define TIM_CR1_CEN_Pos   (0U)
    -
    - -
    -
    - -

    ◆ TIM_CR1_CEN_Msk

    - -
    -
    - - - - -
    #define TIM_CR1_CEN_Msk   (0x1UL << TIM_CR1_CEN_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ TIM_CR1_CEN

    - -
    -
    - - - - -
    #define TIM_CR1_CEN   TIM_CR1_CEN_Msk
    -
    -

    Counter enable
    -

    - -
    -
    - -

    ◆ TIM_CR1_UDIS_Pos

    - -
    -
    - - - - -
    #define TIM_CR1_UDIS_Pos   (1U)
    -
    - -
    -
    - -

    ◆ TIM_CR1_UDIS_Msk

    - -
    -
    - - - - -
    #define TIM_CR1_UDIS_Msk   (0x1UL << TIM_CR1_UDIS_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ TIM_CR1_UDIS

    - -
    -
    - - - - -
    #define TIM_CR1_UDIS   TIM_CR1_UDIS_Msk
    -
    -

    Update disable
    -

    - -
    -
    - -

    ◆ TIM_CR1_URS_Pos

    - -
    -
    - - - - -
    #define TIM_CR1_URS_Pos   (2U)
    -
    - -
    -
    - -

    ◆ TIM_CR1_URS_Msk

    - -
    -
    - - - - -
    #define TIM_CR1_URS_Msk   (0x1UL << TIM_CR1_URS_Pos)
    -
    -

    0x00000004

    - -
    -
    - -

    ◆ TIM_CR1_URS

    - -
    -
    - - - - -
    #define TIM_CR1_URS   TIM_CR1_URS_Msk
    -
    -

    Update request source

    - -
    -
    - -

    ◆ TIM_CR1_OPM_Pos

    - -
    -
    - - - - -
    #define TIM_CR1_OPM_Pos   (3U)
    -
    - -
    -
    - -

    ◆ TIM_CR1_OPM_Msk

    - -
    -
    - - - - -
    #define TIM_CR1_OPM_Msk   (0x1UL << TIM_CR1_OPM_Pos)
    -
    -

    0x00000008

    - -
    -
    - -

    ◆ TIM_CR1_OPM

    - -
    -
    - - - - -
    #define TIM_CR1_OPM   TIM_CR1_OPM_Msk
    -
    -

    One pulse mode
    -

    - -
    -
    - -

    ◆ TIM_CR1_DIR_Pos

    - -
    -
    - - - - -
    #define TIM_CR1_DIR_Pos   (4U)
    -
    - -
    -
    - -

    ◆ TIM_CR1_DIR_Msk

    - -
    -
    - - - - -
    #define TIM_CR1_DIR_Msk   (0x1UL << TIM_CR1_DIR_Pos)
    -
    -

    0x00000010

    - -
    -
    - -

    ◆ TIM_CR1_DIR

    - -
    -
    - - - - -
    #define TIM_CR1_DIR   TIM_CR1_DIR_Msk
    -
    -

    Direction
    -

    - -
    -
    - -

    ◆ TIM_CR1_CMS_Pos

    - -
    -
    - - - - -
    #define TIM_CR1_CMS_Pos   (5U)
    -
    - -
    -
    - -

    ◆ TIM_CR1_CMS_Msk

    - -
    -
    - - - - -
    #define TIM_CR1_CMS_Msk   (0x3UL << TIM_CR1_CMS_Pos)
    -
    -

    0x00000060

    - -
    -
    - -

    ◆ TIM_CR1_CMS

    - -
    -
    - - - - -
    #define TIM_CR1_CMS   TIM_CR1_CMS_Msk
    -
    -

    CMS[1:0] bits (Center-aligned mode selection)

    - -
    -
    - -

    ◆ TIM_CR1_CMS_0

    - -
    -
    - - - - -
    #define TIM_CR1_CMS_0   (0x1UL << TIM_CR1_CMS_Pos)
    -
    -

    0x0020

    - -
    -
    - -

    ◆ TIM_CR1_CMS_1

    - -
    -
    - - - - -
    #define TIM_CR1_CMS_1   (0x2UL << TIM_CR1_CMS_Pos)
    -
    -

    0x0040

    - -
    -
    - -

    ◆ TIM_CR1_ARPE_Pos

    - -
    -
    - - - - -
    #define TIM_CR1_ARPE_Pos   (7U)
    -
    - -
    -
    - -

    ◆ TIM_CR1_ARPE_Msk

    - -
    -
    - - - - -
    #define TIM_CR1_ARPE_Msk   (0x1UL << TIM_CR1_ARPE_Pos)
    -
    -

    0x00000080

    - -
    -
    - -

    ◆ TIM_CR1_ARPE

    - -
    -
    - - - - -
    #define TIM_CR1_ARPE   TIM_CR1_ARPE_Msk
    -
    -

    Auto-reload preload enable
    -

    - -
    -
    - -

    ◆ TIM_CR1_CKD_Pos

    - -
    -
    - - - - -
    #define TIM_CR1_CKD_Pos   (8U)
    -
    - -
    -
    - -

    ◆ TIM_CR1_CKD_Msk

    - -
    -
    - - - - -
    #define TIM_CR1_CKD_Msk   (0x3UL << TIM_CR1_CKD_Pos)
    -
    -

    0x00000300

    - -
    -
    - -

    ◆ TIM_CR1_CKD

    - -
    -
    - - - - -
    #define TIM_CR1_CKD   TIM_CR1_CKD_Msk
    -
    -

    CKD[1:0] bits (clock division)

    - -
    -
    - -

    ◆ TIM_CR1_CKD_0

    - -
    -
    - - - - -
    #define TIM_CR1_CKD_0   (0x1UL << TIM_CR1_CKD_Pos)
    -
    -

    0x0100

    - -
    -
    - -

    ◆ TIM_CR1_CKD_1

    - -
    -
    - - - - -
    #define TIM_CR1_CKD_1   (0x2UL << TIM_CR1_CKD_Pos)
    -
    -

    0x0200

    - -
    -
    - -

    ◆ TIM_CR2_CCPC_Pos

    - -
    -
    - - - - -
    #define TIM_CR2_CCPC_Pos   (0U)
    -
    - -
    -
    - -

    ◆ TIM_CR2_CCPC_Msk

    - -
    -
    - - - - -
    #define TIM_CR2_CCPC_Msk   (0x1UL << TIM_CR2_CCPC_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ TIM_CR2_CCPC

    - -
    -
    - - - - -
    #define TIM_CR2_CCPC   TIM_CR2_CCPC_Msk
    -
    -

    Capture/Compare Preloaded Control
    -

    - -
    -
    - -

    ◆ TIM_CR2_CCUS_Pos

    - -
    -
    - - - - -
    #define TIM_CR2_CCUS_Pos   (2U)
    -
    - -
    -
    - -

    ◆ TIM_CR2_CCUS_Msk

    - -
    -
    - - - - -
    #define TIM_CR2_CCUS_Msk   (0x1UL << TIM_CR2_CCUS_Pos)
    -
    -

    0x00000004

    - -
    -
    - -

    ◆ TIM_CR2_CCUS

    - -
    -
    - - - - -
    #define TIM_CR2_CCUS   TIM_CR2_CCUS_Msk
    -
    -

    Capture/Compare Control Update Selection

    - -
    -
    - -

    ◆ TIM_CR2_CCDS_Pos

    - -
    -
    - - - - -
    #define TIM_CR2_CCDS_Pos   (3U)
    -
    - -
    -
    - -

    ◆ TIM_CR2_CCDS_Msk

    - -
    -
    - - - - -
    #define TIM_CR2_CCDS_Msk   (0x1UL << TIM_CR2_CCDS_Pos)
    -
    -

    0x00000008

    - -
    -
    - -

    ◆ TIM_CR2_CCDS

    - -
    -
    - - - - -
    #define TIM_CR2_CCDS   TIM_CR2_CCDS_Msk
    -
    -

    Capture/Compare DMA Selection
    -

    - -
    -
    - -

    ◆ TIM_CR2_MMS_Pos

    - -
    -
    - - - - -
    #define TIM_CR2_MMS_Pos   (4U)
    -
    - -
    -
    - -

    ◆ TIM_CR2_MMS_Msk

    - -
    -
    - - - - -
    #define TIM_CR2_MMS_Msk   (0x7UL << TIM_CR2_MMS_Pos)
    -
    -

    0x00000070

    - -
    -
    - -

    ◆ TIM_CR2_MMS

    - -
    -
    - - - - -
    #define TIM_CR2_MMS   TIM_CR2_MMS_Msk
    -
    -

    MMS[2:0] bits (Master Mode Selection)

    - -
    -
    - -

    ◆ TIM_CR2_MMS_0

    - -
    -
    - - - - -
    #define TIM_CR2_MMS_0   (0x1UL << TIM_CR2_MMS_Pos)
    -
    -

    0x0010

    - -
    -
    - -

    ◆ TIM_CR2_MMS_1

    - -
    -
    - - - - -
    #define TIM_CR2_MMS_1   (0x2UL << TIM_CR2_MMS_Pos)
    -
    -

    0x0020

    - -
    -
    - -

    ◆ TIM_CR2_MMS_2

    - -
    -
    - - - - -
    #define TIM_CR2_MMS_2   (0x4UL << TIM_CR2_MMS_Pos)
    -
    -

    0x0040

    - -
    -
    - -

    ◆ TIM_CR2_TI1S_Pos

    - -
    -
    - - - - -
    #define TIM_CR2_TI1S_Pos   (7U)
    -
    - -
    -
    - -

    ◆ TIM_CR2_TI1S_Msk

    - -
    -
    - - - - -
    #define TIM_CR2_TI1S_Msk   (0x1UL << TIM_CR2_TI1S_Pos)
    -
    -

    0x00000080

    - -
    -
    - -

    ◆ TIM_CR2_TI1S

    - -
    -
    - - - - -
    #define TIM_CR2_TI1S   TIM_CR2_TI1S_Msk
    -
    -

    TI1 Selection

    - -
    -
    - -

    ◆ TIM_CR2_OIS1_Pos

    - -
    -
    - - - - -
    #define TIM_CR2_OIS1_Pos   (8U)
    -
    - -
    -
    - -

    ◆ TIM_CR2_OIS1_Msk

    - -
    -
    - - - - -
    #define TIM_CR2_OIS1_Msk   (0x1UL << TIM_CR2_OIS1_Pos)
    -
    -

    0x00000100

    - -
    -
    - -

    ◆ TIM_CR2_OIS1

    - -
    -
    - - - - -
    #define TIM_CR2_OIS1   TIM_CR2_OIS1_Msk
    -
    -

    Output Idle state 1 (OC1 output)
    -

    - -
    -
    - -

    ◆ TIM_CR2_OIS1N_Pos

    - -
    -
    - - - - -
    #define TIM_CR2_OIS1N_Pos   (9U)
    -
    - -
    -
    - -

    ◆ TIM_CR2_OIS1N_Msk

    - -
    -
    - - - - -
    #define TIM_CR2_OIS1N_Msk   (0x1UL << TIM_CR2_OIS1N_Pos)
    -
    -

    0x00000200

    - -
    -
    - -

    ◆ TIM_CR2_OIS1N

    - -
    -
    - - - - -
    #define TIM_CR2_OIS1N   TIM_CR2_OIS1N_Msk
    -
    -

    Output Idle state 1 (OC1N output)

    - -
    -
    - -

    ◆ TIM_CR2_OIS2_Pos

    - -
    -
    - - - - -
    #define TIM_CR2_OIS2_Pos   (10U)
    -
    - -
    -
    - -

    ◆ TIM_CR2_OIS2_Msk

    - -
    -
    - - - - -
    #define TIM_CR2_OIS2_Msk   (0x1UL << TIM_CR2_OIS2_Pos)
    -
    -

    0x00000400

    - -
    -
    - -

    ◆ TIM_CR2_OIS2

    - -
    -
    - - - - -
    #define TIM_CR2_OIS2   TIM_CR2_OIS2_Msk
    -
    -

    Output Idle state 2 (OC2 output)
    -

    - -
    -
    - -

    ◆ TIM_CR2_OIS2N_Pos

    - -
    -
    - - - - -
    #define TIM_CR2_OIS2N_Pos   (11U)
    -
    - -
    -
    - -

    ◆ TIM_CR2_OIS2N_Msk

    - -
    -
    - - - - -
    #define TIM_CR2_OIS2N_Msk   (0x1UL << TIM_CR2_OIS2N_Pos)
    -
    -

    0x00000800

    - -
    -
    - -

    ◆ TIM_CR2_OIS2N

    - -
    -
    - - - - -
    #define TIM_CR2_OIS2N   TIM_CR2_OIS2N_Msk
    -
    -

    Output Idle state 2 (OC2N output)

    - -
    -
    - -

    ◆ TIM_CR2_OIS3_Pos

    - -
    -
    - - - - -
    #define TIM_CR2_OIS3_Pos   (12U)
    -
    - -
    -
    - -

    ◆ TIM_CR2_OIS3_Msk

    - -
    -
    - - - - -
    #define TIM_CR2_OIS3_Msk   (0x1UL << TIM_CR2_OIS3_Pos)
    -
    -

    0x00001000

    - -
    -
    - -

    ◆ TIM_CR2_OIS3

    - -
    -
    - - - - -
    #define TIM_CR2_OIS3   TIM_CR2_OIS3_Msk
    -
    -

    Output Idle state 3 (OC3 output)
    -

    - -
    -
    - -

    ◆ TIM_CR2_OIS3N_Pos

    - -
    -
    - - - - -
    #define TIM_CR2_OIS3N_Pos   (13U)
    -
    - -
    -
    - -

    ◆ TIM_CR2_OIS3N_Msk

    - -
    -
    - - - - -
    #define TIM_CR2_OIS3N_Msk   (0x1UL << TIM_CR2_OIS3N_Pos)
    -
    -

    0x00002000

    - -
    -
    - -

    ◆ TIM_CR2_OIS3N

    - -
    -
    - - - - -
    #define TIM_CR2_OIS3N   TIM_CR2_OIS3N_Msk
    -
    -

    Output Idle state 3 (OC3N output)

    - -
    -
    - -

    ◆ TIM_CR2_OIS4_Pos

    - -
    -
    - - - - -
    #define TIM_CR2_OIS4_Pos   (14U)
    -
    - -
    -
    - -

    ◆ TIM_CR2_OIS4_Msk

    - -
    -
    - - - - -
    #define TIM_CR2_OIS4_Msk   (0x1UL << TIM_CR2_OIS4_Pos)
    -
    -

    0x00004000

    - -
    -
    - -

    ◆ TIM_CR2_OIS4

    - -
    -
    - - - - -
    #define TIM_CR2_OIS4   TIM_CR2_OIS4_Msk
    -
    -

    Output Idle state 4 (OC4 output)
    -

    - -
    -
    - -

    ◆ TIM_SMCR_SMS_Pos

    - -
    -
    - - - - -
    #define TIM_SMCR_SMS_Pos   (0U)
    -
    - -
    -
    - -

    ◆ TIM_SMCR_SMS_Msk

    - -
    -
    - - - - -
    #define TIM_SMCR_SMS_Msk   (0x7UL << TIM_SMCR_SMS_Pos)
    -
    -

    0x00000007

    - -
    -
    - -

    ◆ TIM_SMCR_SMS

    - -
    -
    - - - - -
    #define TIM_SMCR_SMS   TIM_SMCR_SMS_Msk
    -
    -

    SMS[2:0] bits (Slave mode selection)
    -

    - -
    -
    - -

    ◆ TIM_SMCR_SMS_0

    - -
    -
    - - - - -
    #define TIM_SMCR_SMS_0   (0x1UL << TIM_SMCR_SMS_Pos)
    -
    -

    0x0001

    - -
    -
    - -

    ◆ TIM_SMCR_SMS_1

    - -
    -
    - - - - -
    #define TIM_SMCR_SMS_1   (0x2UL << TIM_SMCR_SMS_Pos)
    -
    -

    0x0002

    - -
    -
    - -

    ◆ TIM_SMCR_SMS_2

    - -
    -
    - - - - -
    #define TIM_SMCR_SMS_2   (0x4UL << TIM_SMCR_SMS_Pos)
    -
    -

    0x0004

    - -
    -
    - -

    ◆ TIM_SMCR_TS_Pos

    - -
    -
    - - - - -
    #define TIM_SMCR_TS_Pos   (4U)
    -
    - -
    -
    - -

    ◆ TIM_SMCR_TS_Msk

    - -
    -
    - - - - -
    #define TIM_SMCR_TS_Msk   (0x7UL << TIM_SMCR_TS_Pos)
    -
    -

    0x00000070

    - -
    -
    - -

    ◆ TIM_SMCR_TS

    - -
    -
    - - - - -
    #define TIM_SMCR_TS   TIM_SMCR_TS_Msk
    -
    -

    TS[2:0] bits (Trigger selection)
    -

    - -
    -
    - -

    ◆ TIM_SMCR_TS_0

    - -
    -
    - - - - -
    #define TIM_SMCR_TS_0   (0x1UL << TIM_SMCR_TS_Pos)
    -
    -

    0x0010

    - -
    -
    - -

    ◆ TIM_SMCR_TS_1

    - -
    -
    - - - - -
    #define TIM_SMCR_TS_1   (0x2UL << TIM_SMCR_TS_Pos)
    -
    -

    0x0020

    - -
    -
    - -

    ◆ TIM_SMCR_TS_2

    - -
    -
    - - - - -
    #define TIM_SMCR_TS_2   (0x4UL << TIM_SMCR_TS_Pos)
    -
    -

    0x0040

    - -
    -
    - -

    ◆ TIM_SMCR_MSM_Pos

    - -
    -
    - - - - -
    #define TIM_SMCR_MSM_Pos   (7U)
    -
    - -
    -
    - -

    ◆ TIM_SMCR_MSM_Msk

    - -
    -
    - - - - -
    #define TIM_SMCR_MSM_Msk   (0x1UL << TIM_SMCR_MSM_Pos)
    -
    -

    0x00000080

    - -
    -
    - -

    ◆ TIM_SMCR_MSM

    - -
    -
    - - - - -
    #define TIM_SMCR_MSM   TIM_SMCR_MSM_Msk
    -
    -

    Master/slave mode
    -

    - -
    -
    - -

    ◆ TIM_SMCR_ETF_Pos

    - -
    -
    - - - - -
    #define TIM_SMCR_ETF_Pos   (8U)
    -
    - -
    -
    - -

    ◆ TIM_SMCR_ETF_Msk

    - -
    -
    - - - - -
    #define TIM_SMCR_ETF_Msk   (0xFUL << TIM_SMCR_ETF_Pos)
    -
    -

    0x00000F00

    - -
    -
    - -

    ◆ TIM_SMCR_ETF

    - -
    -
    - - - - -
    #define TIM_SMCR_ETF   TIM_SMCR_ETF_Msk
    -
    -

    ETF[3:0] bits (External trigger filter)

    - -
    -
    - -

    ◆ TIM_SMCR_ETF_0

    - -
    -
    - - - - -
    #define TIM_SMCR_ETF_0   (0x1UL << TIM_SMCR_ETF_Pos)
    -
    -

    0x0100

    - -
    -
    - -

    ◆ TIM_SMCR_ETF_1

    - -
    -
    - - - - -
    #define TIM_SMCR_ETF_1   (0x2UL << TIM_SMCR_ETF_Pos)
    -
    -

    0x0200

    - -
    -
    - -

    ◆ TIM_SMCR_ETF_2

    - -
    -
    - - - - -
    #define TIM_SMCR_ETF_2   (0x4UL << TIM_SMCR_ETF_Pos)
    -
    -

    0x0400

    - -
    -
    - -

    ◆ TIM_SMCR_ETF_3

    - -
    -
    - - - - -
    #define TIM_SMCR_ETF_3   (0x8UL << TIM_SMCR_ETF_Pos)
    -
    -

    0x0800

    - -
    -
    - -

    ◆ TIM_SMCR_ETPS_Pos

    - -
    -
    - - - - -
    #define TIM_SMCR_ETPS_Pos   (12U)
    -
    - -
    -
    - -

    ◆ TIM_SMCR_ETPS_Msk

    - -
    -
    - - - - -
    #define TIM_SMCR_ETPS_Msk   (0x3UL << TIM_SMCR_ETPS_Pos)
    -
    -

    0x00003000

    - -
    -
    - -

    ◆ TIM_SMCR_ETPS

    - -
    -
    - - - - -
    #define TIM_SMCR_ETPS   TIM_SMCR_ETPS_Msk
    -
    -

    ETPS[1:0] bits (External trigger prescaler)

    - -
    -
    - -

    ◆ TIM_SMCR_ETPS_0

    - -
    -
    - - - - -
    #define TIM_SMCR_ETPS_0   (0x1UL << TIM_SMCR_ETPS_Pos)
    -
    -

    0x1000

    - -
    -
    - -

    ◆ TIM_SMCR_ETPS_1

    - -
    -
    - - - - -
    #define TIM_SMCR_ETPS_1   (0x2UL << TIM_SMCR_ETPS_Pos)
    -
    -

    0x2000

    - -
    -
    - -

    ◆ TIM_SMCR_ECE_Pos

    - -
    -
    - - - - -
    #define TIM_SMCR_ECE_Pos   (14U)
    -
    - -
    -
    - -

    ◆ TIM_SMCR_ECE_Msk

    - -
    -
    - - - - -
    #define TIM_SMCR_ECE_Msk   (0x1UL << TIM_SMCR_ECE_Pos)
    -
    -

    0x00004000

    - -
    -
    - -

    ◆ TIM_SMCR_ECE

    - -
    -
    - - - - -
    #define TIM_SMCR_ECE   TIM_SMCR_ECE_Msk
    -
    -

    External clock enable
    -

    - -
    -
    - -

    ◆ TIM_SMCR_ETP_Pos

    - -
    -
    - - - - -
    #define TIM_SMCR_ETP_Pos   (15U)
    -
    - -
    -
    - -

    ◆ TIM_SMCR_ETP_Msk

    - -
    -
    - - - - -
    #define TIM_SMCR_ETP_Msk   (0x1UL << TIM_SMCR_ETP_Pos)
    -
    -

    0x00008000

    - -
    -
    - -

    ◆ TIM_SMCR_ETP

    - -
    -
    - - - - -
    #define TIM_SMCR_ETP   TIM_SMCR_ETP_Msk
    -
    -

    External trigger polarity

    - -
    -
    - -

    ◆ TIM_DIER_UIE_Pos

    - -
    -
    - - - - -
    #define TIM_DIER_UIE_Pos   (0U)
    -
    - -
    -
    - -

    ◆ TIM_DIER_UIE_Msk

    - -
    -
    - - - - -
    #define TIM_DIER_UIE_Msk   (0x1UL << TIM_DIER_UIE_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ TIM_DIER_UIE

    - -
    -
    - - - - -
    #define TIM_DIER_UIE   TIM_DIER_UIE_Msk
    -
    -

    Update interrupt enable

    - -
    -
    - -

    ◆ TIM_DIER_CC1IE_Pos

    - -
    -
    - - - - -
    #define TIM_DIER_CC1IE_Pos   (1U)
    -
    - -
    -
    - -

    ◆ TIM_DIER_CC1IE_Msk

    - -
    -
    - - - - -
    #define TIM_DIER_CC1IE_Msk   (0x1UL << TIM_DIER_CC1IE_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ TIM_DIER_CC1IE

    - -
    -
    - - - - -
    #define TIM_DIER_CC1IE   TIM_DIER_CC1IE_Msk
    -
    -

    Capture/Compare 1 interrupt enable
    -

    - -
    -
    - -

    ◆ TIM_DIER_CC2IE_Pos

    - -
    -
    - - - - -
    #define TIM_DIER_CC2IE_Pos   (2U)
    -
    - -
    -
    - -

    ◆ TIM_DIER_CC2IE_Msk

    - -
    -
    - - - - -
    #define TIM_DIER_CC2IE_Msk   (0x1UL << TIM_DIER_CC2IE_Pos)
    -
    -

    0x00000004

    - -
    -
    - -

    ◆ TIM_DIER_CC2IE

    - -
    -
    - - - - -
    #define TIM_DIER_CC2IE   TIM_DIER_CC2IE_Msk
    -
    -

    Capture/Compare 2 interrupt enable
    -

    - -
    -
    - -

    ◆ TIM_DIER_CC3IE_Pos

    - -
    -
    - - - - -
    #define TIM_DIER_CC3IE_Pos   (3U)
    -
    - -
    -
    - -

    ◆ TIM_DIER_CC3IE_Msk

    - -
    -
    - - - - -
    #define TIM_DIER_CC3IE_Msk   (0x1UL << TIM_DIER_CC3IE_Pos)
    -
    -

    0x00000008

    - -
    -
    - -

    ◆ TIM_DIER_CC3IE

    - -
    -
    - - - - -
    #define TIM_DIER_CC3IE   TIM_DIER_CC3IE_Msk
    -
    -

    Capture/Compare 3 interrupt enable
    -

    - -
    -
    - -

    ◆ TIM_DIER_CC4IE_Pos

    - -
    -
    - - - - -
    #define TIM_DIER_CC4IE_Pos   (4U)
    -
    - -
    -
    - -

    ◆ TIM_DIER_CC4IE_Msk

    - -
    -
    - - - - -
    #define TIM_DIER_CC4IE_Msk   (0x1UL << TIM_DIER_CC4IE_Pos)
    -
    -

    0x00000010

    - -
    -
    - -

    ◆ TIM_DIER_CC4IE

    - -
    -
    - - - - -
    #define TIM_DIER_CC4IE   TIM_DIER_CC4IE_Msk
    -
    -

    Capture/Compare 4 interrupt enable
    -

    - -
    -
    - -

    ◆ TIM_DIER_COMIE_Pos

    - -
    -
    - - - - -
    #define TIM_DIER_COMIE_Pos   (5U)
    -
    - -
    -
    - -

    ◆ TIM_DIER_COMIE_Msk

    - -
    -
    - - - - -
    #define TIM_DIER_COMIE_Msk   (0x1UL << TIM_DIER_COMIE_Pos)
    -
    -

    0x00000020

    - -
    -
    - -

    ◆ TIM_DIER_COMIE

    - -
    -
    - - - - -
    #define TIM_DIER_COMIE   TIM_DIER_COMIE_Msk
    -
    -

    COM interrupt enable
    -

    - -
    -
    - -

    ◆ TIM_DIER_TIE_Pos

    - -
    -
    - - - - -
    #define TIM_DIER_TIE_Pos   (6U)
    -
    - -
    -
    - -

    ◆ TIM_DIER_TIE_Msk

    - -
    -
    - - - - -
    #define TIM_DIER_TIE_Msk   (0x1UL << TIM_DIER_TIE_Pos)
    -
    -

    0x00000040

    - -
    -
    - -

    ◆ TIM_DIER_TIE

    - -
    -
    - - - - -
    #define TIM_DIER_TIE   TIM_DIER_TIE_Msk
    -
    -

    Trigger interrupt enable
    -

    - -
    -
    - -

    ◆ TIM_DIER_BIE_Pos

    - -
    -
    - - - - -
    #define TIM_DIER_BIE_Pos   (7U)
    -
    - -
    -
    - -

    ◆ TIM_DIER_BIE_Msk

    - -
    -
    - - - - -
    #define TIM_DIER_BIE_Msk   (0x1UL << TIM_DIER_BIE_Pos)
    -
    -

    0x00000080

    - -
    -
    - -

    ◆ TIM_DIER_BIE

    - -
    -
    - - - - -
    #define TIM_DIER_BIE   TIM_DIER_BIE_Msk
    -
    -

    Break interrupt enable
    -

    - -
    -
    - -

    ◆ TIM_DIER_UDE_Pos

    - -
    -
    - - - - -
    #define TIM_DIER_UDE_Pos   (8U)
    -
    - -
    -
    - -

    ◆ TIM_DIER_UDE_Msk

    - -
    -
    - - - - -
    #define TIM_DIER_UDE_Msk   (0x1UL << TIM_DIER_UDE_Pos)
    -
    -

    0x00000100

    - -
    -
    - -

    ◆ TIM_DIER_UDE

    - -
    -
    - - - - -
    #define TIM_DIER_UDE   TIM_DIER_UDE_Msk
    -
    -

    Update DMA request enable
    -

    - -
    -
    - -

    ◆ TIM_DIER_CC1DE_Pos

    - -
    -
    - - - - -
    #define TIM_DIER_CC1DE_Pos   (9U)
    -
    - -
    -
    - -

    ◆ TIM_DIER_CC1DE_Msk

    - -
    -
    - - - - -
    #define TIM_DIER_CC1DE_Msk   (0x1UL << TIM_DIER_CC1DE_Pos)
    -
    -

    0x00000200

    - -
    -
    - -

    ◆ TIM_DIER_CC1DE

    - -
    -
    - - - - -
    #define TIM_DIER_CC1DE   TIM_DIER_CC1DE_Msk
    -
    -

    Capture/Compare 1 DMA request enable

    - -
    -
    - -

    ◆ TIM_DIER_CC2DE_Pos

    - -
    -
    - - - - -
    #define TIM_DIER_CC2DE_Pos   (10U)
    -
    - -
    -
    - -

    ◆ TIM_DIER_CC2DE_Msk

    - -
    -
    - - - - -
    #define TIM_DIER_CC2DE_Msk   (0x1UL << TIM_DIER_CC2DE_Pos)
    -
    -

    0x00000400

    - -
    -
    - -

    ◆ TIM_DIER_CC2DE

    - -
    -
    - - - - -
    #define TIM_DIER_CC2DE   TIM_DIER_CC2DE_Msk
    -
    -

    Capture/Compare 2 DMA request enable

    - -
    -
    - -

    ◆ TIM_DIER_CC3DE_Pos

    - -
    -
    - - - - -
    #define TIM_DIER_CC3DE_Pos   (11U)
    -
    - -
    -
    - -

    ◆ TIM_DIER_CC3DE_Msk

    - -
    -
    - - - - -
    #define TIM_DIER_CC3DE_Msk   (0x1UL << TIM_DIER_CC3DE_Pos)
    -
    -

    0x00000800

    - -
    -
    - -

    ◆ TIM_DIER_CC3DE

    - -
    -
    - - - - -
    #define TIM_DIER_CC3DE   TIM_DIER_CC3DE_Msk
    -
    -

    Capture/Compare 3 DMA request enable

    - -
    -
    - -

    ◆ TIM_DIER_CC4DE_Pos

    - -
    -
    - - - - -
    #define TIM_DIER_CC4DE_Pos   (12U)
    -
    - -
    -
    - -

    ◆ TIM_DIER_CC4DE_Msk

    - -
    -
    - - - - -
    #define TIM_DIER_CC4DE_Msk   (0x1UL << TIM_DIER_CC4DE_Pos)
    -
    -

    0x00001000

    - -
    -
    - -

    ◆ TIM_DIER_CC4DE

    - -
    -
    - - - - -
    #define TIM_DIER_CC4DE   TIM_DIER_CC4DE_Msk
    -
    -

    Capture/Compare 4 DMA request enable

    - -
    -
    - -

    ◆ TIM_DIER_COMDE_Pos

    - -
    -
    - - - - -
    #define TIM_DIER_COMDE_Pos   (13U)
    -
    - -
    -
    - -

    ◆ TIM_DIER_COMDE_Msk

    - -
    -
    - - - - -
    #define TIM_DIER_COMDE_Msk   (0x1UL << TIM_DIER_COMDE_Pos)
    -
    -

    0x00002000

    - -
    -
    - -

    ◆ TIM_DIER_COMDE

    - -
    -
    - - - - -
    #define TIM_DIER_COMDE   TIM_DIER_COMDE_Msk
    -
    -

    COM DMA request enable
    -

    - -
    -
    - -

    ◆ TIM_DIER_TDE_Pos

    - -
    -
    - - - - -
    #define TIM_DIER_TDE_Pos   (14U)
    -
    - -
    -
    - -

    ◆ TIM_DIER_TDE_Msk

    - -
    -
    - - - - -
    #define TIM_DIER_TDE_Msk   (0x1UL << TIM_DIER_TDE_Pos)
    -
    -

    0x00004000

    - -
    -
    - -

    ◆ TIM_DIER_TDE

    - -
    -
    - - - - -
    #define TIM_DIER_TDE   TIM_DIER_TDE_Msk
    -
    -

    Trigger DMA request enable
    -

    - -
    -
    - -

    ◆ TIM_SR_UIF_Pos

    - -
    -
    - - - - -
    #define TIM_SR_UIF_Pos   (0U)
    -
    - -
    -
    - -

    ◆ TIM_SR_UIF_Msk

    - -
    -
    - - - - -
    #define TIM_SR_UIF_Msk   (0x1UL << TIM_SR_UIF_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ TIM_SR_UIF

    - -
    -
    - - - - -
    #define TIM_SR_UIF   TIM_SR_UIF_Msk
    -
    -

    Update interrupt Flag
    -

    - -
    -
    - -

    ◆ TIM_SR_CC1IF_Pos

    - -
    -
    - - - - -
    #define TIM_SR_CC1IF_Pos   (1U)
    -
    - -
    -
    - -

    ◆ TIM_SR_CC1IF_Msk

    - -
    -
    - - - - -
    #define TIM_SR_CC1IF_Msk   (0x1UL << TIM_SR_CC1IF_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ TIM_SR_CC1IF

    - -
    -
    - - - - -
    #define TIM_SR_CC1IF   TIM_SR_CC1IF_Msk
    -
    -

    Capture/Compare 1 interrupt Flag
    -

    - -
    -
    - -

    ◆ TIM_SR_CC2IF_Pos

    - -
    -
    - - - - -
    #define TIM_SR_CC2IF_Pos   (2U)
    -
    - -
    -
    - -

    ◆ TIM_SR_CC2IF_Msk

    - -
    -
    - - - - -
    #define TIM_SR_CC2IF_Msk   (0x1UL << TIM_SR_CC2IF_Pos)
    -
    -

    0x00000004

    - -
    -
    - -

    ◆ TIM_SR_CC2IF

    - -
    -
    - - - - -
    #define TIM_SR_CC2IF   TIM_SR_CC2IF_Msk
    -
    -

    Capture/Compare 2 interrupt Flag
    -

    - -
    -
    - -

    ◆ TIM_SR_CC3IF_Pos

    - -
    -
    - - - - -
    #define TIM_SR_CC3IF_Pos   (3U)
    -
    - -
    -
    - -

    ◆ TIM_SR_CC3IF_Msk

    - -
    -
    - - - - -
    #define TIM_SR_CC3IF_Msk   (0x1UL << TIM_SR_CC3IF_Pos)
    -
    -

    0x00000008

    - -
    -
    - -

    ◆ TIM_SR_CC3IF

    - -
    -
    - - - - -
    #define TIM_SR_CC3IF   TIM_SR_CC3IF_Msk
    -
    -

    Capture/Compare 3 interrupt Flag
    -

    - -
    -
    - -

    ◆ TIM_SR_CC4IF_Pos

    - -
    -
    - - - - -
    #define TIM_SR_CC4IF_Pos   (4U)
    -
    - -
    -
    - -

    ◆ TIM_SR_CC4IF_Msk

    - -
    -
    - - - - -
    #define TIM_SR_CC4IF_Msk   (0x1UL << TIM_SR_CC4IF_Pos)
    -
    -

    0x00000010

    - -
    -
    - -

    ◆ TIM_SR_CC4IF

    - -
    -
    - - - - -
    #define TIM_SR_CC4IF   TIM_SR_CC4IF_Msk
    -
    -

    Capture/Compare 4 interrupt Flag
    -

    - -
    -
    - -

    ◆ TIM_SR_COMIF_Pos

    - -
    -
    - - - - -
    #define TIM_SR_COMIF_Pos   (5U)
    -
    - -
    -
    - -

    ◆ TIM_SR_COMIF_Msk

    - -
    -
    - - - - -
    #define TIM_SR_COMIF_Msk   (0x1UL << TIM_SR_COMIF_Pos)
    -
    -

    0x00000020

    - -
    -
    - -

    ◆ TIM_SR_COMIF

    - -
    -
    - - - - -
    #define TIM_SR_COMIF   TIM_SR_COMIF_Msk
    -
    -

    COM interrupt Flag
    -

    - -
    -
    - -

    ◆ TIM_SR_TIF_Pos

    - -
    -
    - - - - -
    #define TIM_SR_TIF_Pos   (6U)
    -
    - -
    -
    - -

    ◆ TIM_SR_TIF_Msk

    - -
    -
    - - - - -
    #define TIM_SR_TIF_Msk   (0x1UL << TIM_SR_TIF_Pos)
    -
    -

    0x00000040

    - -
    -
    - -

    ◆ TIM_SR_TIF

    - -
    -
    - - - - -
    #define TIM_SR_TIF   TIM_SR_TIF_Msk
    -
    -

    Trigger interrupt Flag
    -

    - -
    -
    - -

    ◆ TIM_SR_BIF_Pos

    - -
    -
    - - - - -
    #define TIM_SR_BIF_Pos   (7U)
    -
    - -
    -
    - -

    ◆ TIM_SR_BIF_Msk

    - -
    -
    - - - - -
    #define TIM_SR_BIF_Msk   (0x1UL << TIM_SR_BIF_Pos)
    -
    -

    0x00000080

    - -
    -
    - -

    ◆ TIM_SR_BIF

    - -
    -
    - - - - -
    #define TIM_SR_BIF   TIM_SR_BIF_Msk
    -
    -

    Break interrupt Flag
    -

    - -
    -
    - -

    ◆ TIM_SR_CC1OF_Pos

    - -
    -
    - - - - -
    #define TIM_SR_CC1OF_Pos   (9U)
    -
    - -
    -
    - -

    ◆ TIM_SR_CC1OF_Msk

    - -
    -
    - - - - -
    #define TIM_SR_CC1OF_Msk   (0x1UL << TIM_SR_CC1OF_Pos)
    -
    -

    0x00000200

    - -
    -
    - -

    ◆ TIM_SR_CC1OF

    - -
    -
    - - - - -
    #define TIM_SR_CC1OF   TIM_SR_CC1OF_Msk
    -
    -

    Capture/Compare 1 Overcapture Flag

    - -
    -
    - -

    ◆ TIM_SR_CC2OF_Pos

    - -
    -
    - - - - -
    #define TIM_SR_CC2OF_Pos   (10U)
    -
    - -
    -
    - -

    ◆ TIM_SR_CC2OF_Msk

    - -
    -
    - - - - -
    #define TIM_SR_CC2OF_Msk   (0x1UL << TIM_SR_CC2OF_Pos)
    -
    -

    0x00000400

    - -
    -
    - -

    ◆ TIM_SR_CC2OF

    - -
    -
    - - - - -
    #define TIM_SR_CC2OF   TIM_SR_CC2OF_Msk
    -
    -

    Capture/Compare 2 Overcapture Flag

    - -
    -
    - -

    ◆ TIM_SR_CC3OF_Pos

    - -
    -
    - - - - -
    #define TIM_SR_CC3OF_Pos   (11U)
    -
    - -
    -
    - -

    ◆ TIM_SR_CC3OF_Msk

    - -
    -
    - - - - -
    #define TIM_SR_CC3OF_Msk   (0x1UL << TIM_SR_CC3OF_Pos)
    -
    -

    0x00000800

    - -
    -
    - -

    ◆ TIM_SR_CC3OF

    - -
    -
    - - - - -
    #define TIM_SR_CC3OF   TIM_SR_CC3OF_Msk
    -
    -

    Capture/Compare 3 Overcapture Flag

    - -
    -
    - -

    ◆ TIM_SR_CC4OF_Pos

    - -
    -
    - - - - -
    #define TIM_SR_CC4OF_Pos   (12U)
    -
    - -
    -
    - -

    ◆ TIM_SR_CC4OF_Msk

    - -
    -
    - - - - -
    #define TIM_SR_CC4OF_Msk   (0x1UL << TIM_SR_CC4OF_Pos)
    -
    -

    0x00001000

    - -
    -
    - -

    ◆ TIM_SR_CC4OF

    - -
    -
    - - - - -
    #define TIM_SR_CC4OF   TIM_SR_CC4OF_Msk
    -
    -

    Capture/Compare 4 Overcapture Flag

    - -
    -
    - -

    ◆ TIM_EGR_UG_Pos

    - -
    -
    - - - - -
    #define TIM_EGR_UG_Pos   (0U)
    -
    - -
    -
    - -

    ◆ TIM_EGR_UG_Msk

    - -
    -
    - - - - -
    #define TIM_EGR_UG_Msk   (0x1UL << TIM_EGR_UG_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ TIM_EGR_UG

    - -
    -
    - - - - -
    #define TIM_EGR_UG   TIM_EGR_UG_Msk
    -
    -

    Update Generation
    -

    - -
    -
    - -

    ◆ TIM_EGR_CC1G_Pos

    - -
    -
    - - - - -
    #define TIM_EGR_CC1G_Pos   (1U)
    -
    - -
    -
    - -

    ◆ TIM_EGR_CC1G_Msk

    - -
    -
    - - - - -
    #define TIM_EGR_CC1G_Msk   (0x1UL << TIM_EGR_CC1G_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ TIM_EGR_CC1G

    - -
    -
    - - - - -
    #define TIM_EGR_CC1G   TIM_EGR_CC1G_Msk
    -
    -

    Capture/Compare 1 Generation
    -

    - -
    -
    - -

    ◆ TIM_EGR_CC2G_Pos

    - -
    -
    - - - - -
    #define TIM_EGR_CC2G_Pos   (2U)
    -
    - -
    -
    - -

    ◆ TIM_EGR_CC2G_Msk

    - -
    -
    - - - - -
    #define TIM_EGR_CC2G_Msk   (0x1UL << TIM_EGR_CC2G_Pos)
    -
    -

    0x00000004

    - -
    -
    - -

    ◆ TIM_EGR_CC2G

    - -
    -
    - - - - -
    #define TIM_EGR_CC2G   TIM_EGR_CC2G_Msk
    -
    -

    Capture/Compare 2 Generation
    -

    - -
    -
    - -

    ◆ TIM_EGR_CC3G_Pos

    - -
    -
    - - - - -
    #define TIM_EGR_CC3G_Pos   (3U)
    -
    - -
    -
    - -

    ◆ TIM_EGR_CC3G_Msk

    - -
    -
    - - - - -
    #define TIM_EGR_CC3G_Msk   (0x1UL << TIM_EGR_CC3G_Pos)
    -
    -

    0x00000008

    - -
    -
    - -

    ◆ TIM_EGR_CC3G

    - -
    -
    - - - - -
    #define TIM_EGR_CC3G   TIM_EGR_CC3G_Msk
    -
    -

    Capture/Compare 3 Generation
    -

    - -
    -
    - -

    ◆ TIM_EGR_CC4G_Pos

    - -
    -
    - - - - -
    #define TIM_EGR_CC4G_Pos   (4U)
    -
    - -
    -
    - -

    ◆ TIM_EGR_CC4G_Msk

    - -
    -
    - - - - -
    #define TIM_EGR_CC4G_Msk   (0x1UL << TIM_EGR_CC4G_Pos)
    -
    -

    0x00000010

    - -
    -
    - -

    ◆ TIM_EGR_CC4G

    - -
    -
    - - - - -
    #define TIM_EGR_CC4G   TIM_EGR_CC4G_Msk
    -
    -

    Capture/Compare 4 Generation
    -

    - -
    -
    - -

    ◆ TIM_EGR_COMG_Pos

    - -
    -
    - - - - -
    #define TIM_EGR_COMG_Pos   (5U)
    -
    - -
    -
    - -

    ◆ TIM_EGR_COMG_Msk

    - -
    -
    - - - - -
    #define TIM_EGR_COMG_Msk   (0x1UL << TIM_EGR_COMG_Pos)
    -
    -

    0x00000020

    - -
    -
    - -

    ◆ TIM_EGR_COMG

    - -
    -
    - - - - -
    #define TIM_EGR_COMG   TIM_EGR_COMG_Msk
    -
    -

    Capture/Compare Control Update Generation

    - -
    -
    - -

    ◆ TIM_EGR_TG_Pos

    - -
    -
    - - - - -
    #define TIM_EGR_TG_Pos   (6U)
    -
    - -
    -
    - -

    ◆ TIM_EGR_TG_Msk

    - -
    -
    - - - - -
    #define TIM_EGR_TG_Msk   (0x1UL << TIM_EGR_TG_Pos)
    -
    -

    0x00000040

    - -
    -
    - -

    ◆ TIM_EGR_TG

    - -
    -
    - - - - -
    #define TIM_EGR_TG   TIM_EGR_TG_Msk
    -
    -

    Trigger Generation
    -

    - -
    -
    - -

    ◆ TIM_EGR_BG_Pos

    - -
    -
    - - - - -
    #define TIM_EGR_BG_Pos   (7U)
    -
    - -
    -
    - -

    ◆ TIM_EGR_BG_Msk

    - -
    -
    - - - - -
    #define TIM_EGR_BG_Msk   (0x1UL << TIM_EGR_BG_Pos)
    -
    -

    0x00000080

    - -
    -
    - -

    ◆ TIM_EGR_BG

    - -
    -
    - - - - -
    #define TIM_EGR_BG   TIM_EGR_BG_Msk
    -
    -

    Break Generation
    -

    - -
    -
    - -

    ◆ TIM_CCMR1_CC1S_Pos

    - -
    -
    - - - - -
    #define TIM_CCMR1_CC1S_Pos   (0U)
    -
    - -
    -
    - -

    ◆ TIM_CCMR1_CC1S_Msk

    - -
    -
    - - - - -
    #define TIM_CCMR1_CC1S_Msk   (0x3UL << TIM_CCMR1_CC1S_Pos)
    -
    -

    0x00000003

    - -
    -
    - -

    ◆ TIM_CCMR1_CC1S

    - -
    -
    - - - - -
    #define TIM_CCMR1_CC1S   TIM_CCMR1_CC1S_Msk
    -
    -

    CC1S[1:0] bits (Capture/Compare 1 Selection)

    - -
    -
    - -

    ◆ TIM_CCMR1_CC1S_0

    - -
    -
    - - - - -
    #define TIM_CCMR1_CC1S_0   (0x1UL << TIM_CCMR1_CC1S_Pos)
    -
    -

    0x0001

    - -
    -
    - -

    ◆ TIM_CCMR1_CC1S_1

    - -
    -
    - - - - -
    #define TIM_CCMR1_CC1S_1   (0x2UL << TIM_CCMR1_CC1S_Pos)
    -
    -

    0x0002

    - -
    -
    - -

    ◆ TIM_CCMR1_OC1FE_Pos

    - -
    -
    - - - - -
    #define TIM_CCMR1_OC1FE_Pos   (2U)
    -
    - -
    -
    - -

    ◆ TIM_CCMR1_OC1FE_Msk

    - -
    -
    - - - - -
    #define TIM_CCMR1_OC1FE_Msk   (0x1UL << TIM_CCMR1_OC1FE_Pos)
    -
    -

    0x00000004

    - -
    -
    - -

    ◆ TIM_CCMR1_OC1FE

    - -
    -
    - - - - -
    #define TIM_CCMR1_OC1FE   TIM_CCMR1_OC1FE_Msk
    -
    -

    Output Compare 1 Fast enable
    -

    - -
    -
    - -

    ◆ TIM_CCMR1_OC1PE_Pos

    - -
    -
    - - - - -
    #define TIM_CCMR1_OC1PE_Pos   (3U)
    -
    - -
    -
    - -

    ◆ TIM_CCMR1_OC1PE_Msk

    - -
    -
    - - - - -
    #define TIM_CCMR1_OC1PE_Msk   (0x1UL << TIM_CCMR1_OC1PE_Pos)
    -
    -

    0x00000008

    - -
    -
    - -

    ◆ TIM_CCMR1_OC1PE

    - -
    -
    - - - - -
    #define TIM_CCMR1_OC1PE   TIM_CCMR1_OC1PE_Msk
    -
    -

    Output Compare 1 Preload enable
    -

    - -
    -
    - -

    ◆ TIM_CCMR1_OC1M_Pos

    - -
    -
    - - - - -
    #define TIM_CCMR1_OC1M_Pos   (4U)
    -
    - -
    -
    - -

    ◆ TIM_CCMR1_OC1M_Msk

    - -
    -
    - - - - -
    #define TIM_CCMR1_OC1M_Msk   (0x7UL << TIM_CCMR1_OC1M_Pos)
    -
    -

    0x00000070

    - -
    -
    - -

    ◆ TIM_CCMR1_OC1M

    - -
    -
    - - - - -
    #define TIM_CCMR1_OC1M   TIM_CCMR1_OC1M_Msk
    -
    -

    OC1M[2:0] bits (Output Compare 1 Mode)
    -

    - -
    -
    - -

    ◆ TIM_CCMR1_OC1M_0

    - -
    -
    - - - - -
    #define TIM_CCMR1_OC1M_0   (0x1UL << TIM_CCMR1_OC1M_Pos)
    -
    -

    0x0010

    - -
    -
    - -

    ◆ TIM_CCMR1_OC1M_1

    - -
    -
    - - - - -
    #define TIM_CCMR1_OC1M_1   (0x2UL << TIM_CCMR1_OC1M_Pos)
    -
    -

    0x0020

    - -
    -
    - -

    ◆ TIM_CCMR1_OC1M_2

    - -
    -
    - - - - -
    #define TIM_CCMR1_OC1M_2   (0x4UL << TIM_CCMR1_OC1M_Pos)
    -
    -

    0x0040

    - -
    -
    - -

    ◆ TIM_CCMR1_OC1CE_Pos

    - -
    -
    - - - - -
    #define TIM_CCMR1_OC1CE_Pos   (7U)
    -
    - -
    -
    - -

    ◆ TIM_CCMR1_OC1CE_Msk

    - -
    -
    - - - - -
    #define TIM_CCMR1_OC1CE_Msk   (0x1UL << TIM_CCMR1_OC1CE_Pos)
    -
    -

    0x00000080

    - -
    -
    - -

    ◆ TIM_CCMR1_OC1CE

    - -
    -
    - - - - -
    #define TIM_CCMR1_OC1CE   TIM_CCMR1_OC1CE_Msk
    -
    -

    Output Compare 1Clear Enable
    -

    - -
    -
    - -

    ◆ TIM_CCMR1_CC2S_Pos

    - -
    -
    - - - - -
    #define TIM_CCMR1_CC2S_Pos   (8U)
    -
    - -
    -
    - -

    ◆ TIM_CCMR1_CC2S_Msk

    - -
    -
    - - - - -
    #define TIM_CCMR1_CC2S_Msk   (0x3UL << TIM_CCMR1_CC2S_Pos)
    -
    -

    0x00000300

    - -
    -
    - -

    ◆ TIM_CCMR1_CC2S

    - -
    -
    - - - - -
    #define TIM_CCMR1_CC2S   TIM_CCMR1_CC2S_Msk
    -
    -

    CC2S[1:0] bits (Capture/Compare 2 Selection)

    - -
    -
    - -

    ◆ TIM_CCMR1_CC2S_0

    - -
    -
    - - - - -
    #define TIM_CCMR1_CC2S_0   (0x1UL << TIM_CCMR1_CC2S_Pos)
    -
    -

    0x0100

    - -
    -
    - -

    ◆ TIM_CCMR1_CC2S_1

    - -
    -
    - - - - -
    #define TIM_CCMR1_CC2S_1   (0x2UL << TIM_CCMR1_CC2S_Pos)
    -
    -

    0x0200

    - -
    -
    - -

    ◆ TIM_CCMR1_OC2FE_Pos

    - -
    -
    - - - - -
    #define TIM_CCMR1_OC2FE_Pos   (10U)
    -
    - -
    -
    - -

    ◆ TIM_CCMR1_OC2FE_Msk

    - -
    -
    - - - - -
    #define TIM_CCMR1_OC2FE_Msk   (0x1UL << TIM_CCMR1_OC2FE_Pos)
    -
    -

    0x00000400

    - -
    -
    - -

    ◆ TIM_CCMR1_OC2FE

    - -
    -
    - - - - -
    #define TIM_CCMR1_OC2FE   TIM_CCMR1_OC2FE_Msk
    -
    -

    Output Compare 2 Fast enable
    -

    - -
    -
    - -

    ◆ TIM_CCMR1_OC2PE_Pos

    - -
    -
    - - - - -
    #define TIM_CCMR1_OC2PE_Pos   (11U)
    -
    - -
    -
    - -

    ◆ TIM_CCMR1_OC2PE_Msk

    - -
    -
    - - - - -
    #define TIM_CCMR1_OC2PE_Msk   (0x1UL << TIM_CCMR1_OC2PE_Pos)
    -
    -

    0x00000800

    - -
    -
    - -

    ◆ TIM_CCMR1_OC2PE

    - -
    -
    - - - - -
    #define TIM_CCMR1_OC2PE   TIM_CCMR1_OC2PE_Msk
    -
    -

    Output Compare 2 Preload enable
    -

    - -
    -
    - -

    ◆ TIM_CCMR1_OC2M_Pos

    - -
    -
    - - - - -
    #define TIM_CCMR1_OC2M_Pos   (12U)
    -
    - -
    -
    - -

    ◆ TIM_CCMR1_OC2M_Msk

    - -
    -
    - - - - -
    #define TIM_CCMR1_OC2M_Msk   (0x7UL << TIM_CCMR1_OC2M_Pos)
    -
    -

    0x00007000

    - -
    -
    - -

    ◆ TIM_CCMR1_OC2M

    - -
    -
    - - - - -
    #define TIM_CCMR1_OC2M   TIM_CCMR1_OC2M_Msk
    -
    -

    OC2M[2:0] bits (Output Compare 2 Mode)
    -

    - -
    -
    - -

    ◆ TIM_CCMR1_OC2M_0

    - -
    -
    - - - - -
    #define TIM_CCMR1_OC2M_0   (0x1UL << TIM_CCMR1_OC2M_Pos)
    -
    -

    0x1000

    - -
    -
    - -

    ◆ TIM_CCMR1_OC2M_1

    - -
    -
    - - - - -
    #define TIM_CCMR1_OC2M_1   (0x2UL << TIM_CCMR1_OC2M_Pos)
    -
    -

    0x2000

    - -
    -
    - -

    ◆ TIM_CCMR1_OC2M_2

    - -
    -
    - - - - -
    #define TIM_CCMR1_OC2M_2   (0x4UL << TIM_CCMR1_OC2M_Pos)
    -
    -

    0x4000

    - -
    -
    - -

    ◆ TIM_CCMR1_OC2CE_Pos

    - -
    -
    - - - - -
    #define TIM_CCMR1_OC2CE_Pos   (15U)
    -
    - -
    -
    - -

    ◆ TIM_CCMR1_OC2CE_Msk

    - -
    -
    - - - - -
    #define TIM_CCMR1_OC2CE_Msk   (0x1UL << TIM_CCMR1_OC2CE_Pos)
    -
    -

    0x00008000

    - -
    -
    - -

    ◆ TIM_CCMR1_OC2CE

    - -
    -
    - - - - -
    #define TIM_CCMR1_OC2CE   TIM_CCMR1_OC2CE_Msk
    -
    -

    Output Compare 2 Clear Enable

    - -
    -
    - -

    ◆ TIM_CCMR1_IC1PSC_Pos

    - -
    -
    - - - - -
    #define TIM_CCMR1_IC1PSC_Pos   (2U)
    -
    - -
    -
    - -

    ◆ TIM_CCMR1_IC1PSC_Msk

    - -
    -
    - - - - -
    #define TIM_CCMR1_IC1PSC_Msk   (0x3UL << TIM_CCMR1_IC1PSC_Pos)
    -
    -

    0x0000000C

    - -
    -
    - -

    ◆ TIM_CCMR1_IC1PSC

    - -
    -
    - - - - -
    #define TIM_CCMR1_IC1PSC   TIM_CCMR1_IC1PSC_Msk
    -
    -

    IC1PSC[1:0] bits (Input Capture 1 Prescaler)

    - -
    -
    - -

    ◆ TIM_CCMR1_IC1PSC_0

    - -
    -
    - - - - -
    #define TIM_CCMR1_IC1PSC_0   (0x1UL << TIM_CCMR1_IC1PSC_Pos)
    -
    -

    0x0004

    - -
    -
    - -

    ◆ TIM_CCMR1_IC1PSC_1

    - -
    -
    - - - - -
    #define TIM_CCMR1_IC1PSC_1   (0x2UL << TIM_CCMR1_IC1PSC_Pos)
    -
    -

    0x0008

    - -
    -
    - -

    ◆ TIM_CCMR1_IC1F_Pos

    - -
    -
    - - - - -
    #define TIM_CCMR1_IC1F_Pos   (4U)
    -
    - -
    -
    - -

    ◆ TIM_CCMR1_IC1F_Msk

    - -
    -
    - - - - -
    #define TIM_CCMR1_IC1F_Msk   (0xFUL << TIM_CCMR1_IC1F_Pos)
    -
    -

    0x000000F0

    - -
    -
    - -

    ◆ TIM_CCMR1_IC1F

    - -
    -
    - - - - -
    #define TIM_CCMR1_IC1F   TIM_CCMR1_IC1F_Msk
    -
    -

    IC1F[3:0] bits (Input Capture 1 Filter)
    -

    - -
    -
    - -

    ◆ TIM_CCMR1_IC1F_0

    - -
    -
    - - - - -
    #define TIM_CCMR1_IC1F_0   (0x1UL << TIM_CCMR1_IC1F_Pos)
    -
    -

    0x0010

    - -
    -
    - -

    ◆ TIM_CCMR1_IC1F_1

    - -
    -
    - - - - -
    #define TIM_CCMR1_IC1F_1   (0x2UL << TIM_CCMR1_IC1F_Pos)
    -
    -

    0x0020

    - -
    -
    - -

    ◆ TIM_CCMR1_IC1F_2

    - -
    -
    - - - - -
    #define TIM_CCMR1_IC1F_2   (0x4UL << TIM_CCMR1_IC1F_Pos)
    -
    -

    0x0040

    - -
    -
    - -

    ◆ TIM_CCMR1_IC1F_3

    - -
    -
    - - - - -
    #define TIM_CCMR1_IC1F_3   (0x8UL << TIM_CCMR1_IC1F_Pos)
    -
    -

    0x0080

    - -
    -
    - -

    ◆ TIM_CCMR1_IC2PSC_Pos

    - -
    -
    - - - - -
    #define TIM_CCMR1_IC2PSC_Pos   (10U)
    -
    - -
    -
    - -

    ◆ TIM_CCMR1_IC2PSC_Msk

    - -
    -
    - - - - -
    #define TIM_CCMR1_IC2PSC_Msk   (0x3UL << TIM_CCMR1_IC2PSC_Pos)
    -
    -

    0x00000C00

    - -
    -
    - -

    ◆ TIM_CCMR1_IC2PSC

    - -
    -
    - - - - -
    #define TIM_CCMR1_IC2PSC   TIM_CCMR1_IC2PSC_Msk
    -
    -

    IC2PSC[1:0] bits (Input Capture 2 Prescaler)
    -

    - -
    -
    - -

    ◆ TIM_CCMR1_IC2PSC_0

    - -
    -
    - - - - -
    #define TIM_CCMR1_IC2PSC_0   (0x1UL << TIM_CCMR1_IC2PSC_Pos)
    -
    -

    0x0400

    - -
    -
    - -

    ◆ TIM_CCMR1_IC2PSC_1

    - -
    -
    - - - - -
    #define TIM_CCMR1_IC2PSC_1   (0x2UL << TIM_CCMR1_IC2PSC_Pos)
    -
    -

    0x0800

    - -
    -
    - -

    ◆ TIM_CCMR1_IC2F_Pos

    - -
    -
    - - - - -
    #define TIM_CCMR1_IC2F_Pos   (12U)
    -
    - -
    -
    - -

    ◆ TIM_CCMR1_IC2F_Msk

    - -
    -
    - - - - -
    #define TIM_CCMR1_IC2F_Msk   (0xFUL << TIM_CCMR1_IC2F_Pos)
    -
    -

    0x0000F000

    - -
    -
    - -

    ◆ TIM_CCMR1_IC2F

    - -
    -
    - - - - -
    #define TIM_CCMR1_IC2F   TIM_CCMR1_IC2F_Msk
    -
    -

    IC2F[3:0] bits (Input Capture 2 Filter)
    -

    - -
    -
    - -

    ◆ TIM_CCMR1_IC2F_0

    - -
    -
    - - - - -
    #define TIM_CCMR1_IC2F_0   (0x1UL << TIM_CCMR1_IC2F_Pos)
    -
    -

    0x1000

    - -
    -
    - -

    ◆ TIM_CCMR1_IC2F_1

    - -
    -
    - - - - -
    #define TIM_CCMR1_IC2F_1   (0x2UL << TIM_CCMR1_IC2F_Pos)
    -
    -

    0x2000

    - -
    -
    - -

    ◆ TIM_CCMR1_IC2F_2

    - -
    -
    - - - - -
    #define TIM_CCMR1_IC2F_2   (0x4UL << TIM_CCMR1_IC2F_Pos)
    -
    -

    0x4000

    - -
    -
    - -

    ◆ TIM_CCMR1_IC2F_3

    - -
    -
    - - - - -
    #define TIM_CCMR1_IC2F_3   (0x8UL << TIM_CCMR1_IC2F_Pos)
    -
    -

    0x8000

    - -
    -
    - -

    ◆ TIM_CCMR2_CC3S_Pos

    - -
    -
    - - - - -
    #define TIM_CCMR2_CC3S_Pos   (0U)
    -
    - -
    -
    - -

    ◆ TIM_CCMR2_CC3S_Msk

    - -
    -
    - - - - -
    #define TIM_CCMR2_CC3S_Msk   (0x3UL << TIM_CCMR2_CC3S_Pos)
    -
    -

    0x00000003

    - -
    -
    - -

    ◆ TIM_CCMR2_CC3S

    - -
    -
    - - - - -
    #define TIM_CCMR2_CC3S   TIM_CCMR2_CC3S_Msk
    -
    -

    CC3S[1:0] bits (Capture/Compare 3 Selection)
    -

    - -
    -
    - -

    ◆ TIM_CCMR2_CC3S_0

    - -
    -
    - - - - -
    #define TIM_CCMR2_CC3S_0   (0x1UL << TIM_CCMR2_CC3S_Pos)
    -
    -

    0x0001

    - -
    -
    - -

    ◆ TIM_CCMR2_CC3S_1

    - -
    -
    - - - - -
    #define TIM_CCMR2_CC3S_1   (0x2UL << TIM_CCMR2_CC3S_Pos)
    -
    -

    0x0002

    - -
    -
    - -

    ◆ TIM_CCMR2_OC3FE_Pos

    - -
    -
    - - - - -
    #define TIM_CCMR2_OC3FE_Pos   (2U)
    -
    - -
    -
    - -

    ◆ TIM_CCMR2_OC3FE_Msk

    - -
    -
    - - - - -
    #define TIM_CCMR2_OC3FE_Msk   (0x1UL << TIM_CCMR2_OC3FE_Pos)
    -
    -

    0x00000004

    - -
    -
    - -

    ◆ TIM_CCMR2_OC3FE

    - -
    -
    - - - - -
    #define TIM_CCMR2_OC3FE   TIM_CCMR2_OC3FE_Msk
    -
    -

    Output Compare 3 Fast enable
    -

    - -
    -
    - -

    ◆ TIM_CCMR2_OC3PE_Pos

    - -
    -
    - - - - -
    #define TIM_CCMR2_OC3PE_Pos   (3U)
    -
    - -
    -
    - -

    ◆ TIM_CCMR2_OC3PE_Msk

    - -
    -
    - - - - -
    #define TIM_CCMR2_OC3PE_Msk   (0x1UL << TIM_CCMR2_OC3PE_Pos)
    -
    -

    0x00000008

    - -
    -
    - -

    ◆ TIM_CCMR2_OC3PE

    - -
    -
    - - - - -
    #define TIM_CCMR2_OC3PE   TIM_CCMR2_OC3PE_Msk
    -
    -

    Output Compare 3 Preload enable
    -

    - -
    -
    - -

    ◆ TIM_CCMR2_OC3M_Pos

    - -
    -
    - - - - -
    #define TIM_CCMR2_OC3M_Pos   (4U)
    -
    - -
    -
    - -

    ◆ TIM_CCMR2_OC3M_Msk

    - -
    -
    - - - - -
    #define TIM_CCMR2_OC3M_Msk   (0x7UL << TIM_CCMR2_OC3M_Pos)
    -
    -

    0x00000070

    - -
    -
    - -

    ◆ TIM_CCMR2_OC3M

    - -
    -
    - - - - -
    #define TIM_CCMR2_OC3M   TIM_CCMR2_OC3M_Msk
    -
    -

    OC3M[2:0] bits (Output Compare 3 Mode)

    - -
    -
    - -

    ◆ TIM_CCMR2_OC3M_0

    - -
    -
    - - - - -
    #define TIM_CCMR2_OC3M_0   (0x1UL << TIM_CCMR2_OC3M_Pos)
    -
    -

    0x0010

    - -
    -
    - -

    ◆ TIM_CCMR2_OC3M_1

    - -
    -
    - - - - -
    #define TIM_CCMR2_OC3M_1   (0x2UL << TIM_CCMR2_OC3M_Pos)
    -
    -

    0x0020

    - -
    -
    - -

    ◆ TIM_CCMR2_OC3M_2

    - -
    -
    - - - - -
    #define TIM_CCMR2_OC3M_2   (0x4UL << TIM_CCMR2_OC3M_Pos)
    -
    -

    0x0040

    - -
    -
    - -

    ◆ TIM_CCMR2_OC3CE_Pos

    - -
    -
    - - - - -
    #define TIM_CCMR2_OC3CE_Pos   (7U)
    -
    - -
    -
    - -

    ◆ TIM_CCMR2_OC3CE_Msk

    - -
    -
    - - - - -
    #define TIM_CCMR2_OC3CE_Msk   (0x1UL << TIM_CCMR2_OC3CE_Pos)
    -
    -

    0x00000080

    - -
    -
    - -

    ◆ TIM_CCMR2_OC3CE

    - -
    -
    - - - - -
    #define TIM_CCMR2_OC3CE   TIM_CCMR2_OC3CE_Msk
    -
    -

    Output Compare 3 Clear Enable

    - -
    -
    - -

    ◆ TIM_CCMR2_CC4S_Pos

    - -
    -
    - - - - -
    #define TIM_CCMR2_CC4S_Pos   (8U)
    -
    - -
    -
    - -

    ◆ TIM_CCMR2_CC4S_Msk

    - -
    -
    - - - - -
    #define TIM_CCMR2_CC4S_Msk   (0x3UL << TIM_CCMR2_CC4S_Pos)
    -
    -

    0x00000300

    - -
    -
    - -

    ◆ TIM_CCMR2_CC4S

    - -
    -
    - - - - -
    #define TIM_CCMR2_CC4S   TIM_CCMR2_CC4S_Msk
    -
    -

    CC4S[1:0] bits (Capture/Compare 4 Selection)

    - -
    -
    - -

    ◆ TIM_CCMR2_CC4S_0

    - -
    -
    - - - - -
    #define TIM_CCMR2_CC4S_0   (0x1UL << TIM_CCMR2_CC4S_Pos)
    -
    -

    0x0100

    - -
    -
    - -

    ◆ TIM_CCMR2_CC4S_1

    - -
    -
    - - - - -
    #define TIM_CCMR2_CC4S_1   (0x2UL << TIM_CCMR2_CC4S_Pos)
    -
    -

    0x0200

    - -
    -
    - -

    ◆ TIM_CCMR2_OC4FE_Pos

    - -
    -
    - - - - -
    #define TIM_CCMR2_OC4FE_Pos   (10U)
    -
    - -
    -
    - -

    ◆ TIM_CCMR2_OC4FE_Msk

    - -
    -
    - - - - -
    #define TIM_CCMR2_OC4FE_Msk   (0x1UL << TIM_CCMR2_OC4FE_Pos)
    -
    -

    0x00000400

    - -
    -
    - -

    ◆ TIM_CCMR2_OC4FE

    - -
    -
    - - - - -
    #define TIM_CCMR2_OC4FE   TIM_CCMR2_OC4FE_Msk
    -
    -

    Output Compare 4 Fast enable
    -

    - -
    -
    - -

    ◆ TIM_CCMR2_OC4PE_Pos

    - -
    -
    - - - - -
    #define TIM_CCMR2_OC4PE_Pos   (11U)
    -
    - -
    -
    - -

    ◆ TIM_CCMR2_OC4PE_Msk

    - -
    -
    - - - - -
    #define TIM_CCMR2_OC4PE_Msk   (0x1UL << TIM_CCMR2_OC4PE_Pos)
    -
    -

    0x00000800

    - -
    -
    - -

    ◆ TIM_CCMR2_OC4PE

    - -
    -
    - - - - -
    #define TIM_CCMR2_OC4PE   TIM_CCMR2_OC4PE_Msk
    -
    -

    Output Compare 4 Preload enable

    - -
    -
    - -

    ◆ TIM_CCMR2_OC4M_Pos

    - -
    -
    - - - - -
    #define TIM_CCMR2_OC4M_Pos   (12U)
    -
    - -
    -
    - -

    ◆ TIM_CCMR2_OC4M_Msk

    - -
    -
    - - - - -
    #define TIM_CCMR2_OC4M_Msk   (0x7UL << TIM_CCMR2_OC4M_Pos)
    -
    -

    0x00007000

    - -
    -
    - -

    ◆ TIM_CCMR2_OC4M

    - -
    -
    - - - - -
    #define TIM_CCMR2_OC4M   TIM_CCMR2_OC4M_Msk
    -
    -

    OC4M[2:0] bits (Output Compare 4 Mode)

    - -
    -
    - -

    ◆ TIM_CCMR2_OC4M_0

    - -
    -
    - - - - -
    #define TIM_CCMR2_OC4M_0   (0x1UL << TIM_CCMR2_OC4M_Pos)
    -
    -

    0x1000

    - -
    -
    - -

    ◆ TIM_CCMR2_OC4M_1

    - -
    -
    - - - - -
    #define TIM_CCMR2_OC4M_1   (0x2UL << TIM_CCMR2_OC4M_Pos)
    -
    -

    0x2000

    - -
    -
    - -

    ◆ TIM_CCMR2_OC4M_2

    - -
    -
    - - - - -
    #define TIM_CCMR2_OC4M_2   (0x4UL << TIM_CCMR2_OC4M_Pos)
    -
    -

    0x4000

    - -
    -
    - -

    ◆ TIM_CCMR2_OC4CE_Pos

    - -
    -
    - - - - -
    #define TIM_CCMR2_OC4CE_Pos   (15U)
    -
    - -
    -
    - -

    ◆ TIM_CCMR2_OC4CE_Msk

    - -
    -
    - - - - -
    #define TIM_CCMR2_OC4CE_Msk   (0x1UL << TIM_CCMR2_OC4CE_Pos)
    -
    -

    0x00008000

    - -
    -
    - -

    ◆ TIM_CCMR2_OC4CE

    - -
    -
    - - - - -
    #define TIM_CCMR2_OC4CE   TIM_CCMR2_OC4CE_Msk
    -
    -

    Output Compare 4 Clear Enable

    - -
    -
    - -

    ◆ TIM_CCMR2_IC3PSC_Pos

    - -
    -
    - - - - -
    #define TIM_CCMR2_IC3PSC_Pos   (2U)
    -
    - -
    -
    - -

    ◆ TIM_CCMR2_IC3PSC_Msk

    - -
    -
    - - - - -
    #define TIM_CCMR2_IC3PSC_Msk   (0x3UL << TIM_CCMR2_IC3PSC_Pos)
    -
    -

    0x0000000C

    - -
    -
    - -

    ◆ TIM_CCMR2_IC3PSC

    - -
    -
    - - - - -
    #define TIM_CCMR2_IC3PSC   TIM_CCMR2_IC3PSC_Msk
    -
    -

    IC3PSC[1:0] bits (Input Capture 3 Prescaler)

    - -
    -
    - -

    ◆ TIM_CCMR2_IC3PSC_0

    - -
    -
    - - - - -
    #define TIM_CCMR2_IC3PSC_0   (0x1UL << TIM_CCMR2_IC3PSC_Pos)
    -
    -

    0x0004

    - -
    -
    - -

    ◆ TIM_CCMR2_IC3PSC_1

    - -
    -
    - - - - -
    #define TIM_CCMR2_IC3PSC_1   (0x2UL << TIM_CCMR2_IC3PSC_Pos)
    -
    -

    0x0008

    - -
    -
    - -

    ◆ TIM_CCMR2_IC3F_Pos

    - -
    -
    - - - - -
    #define TIM_CCMR2_IC3F_Pos   (4U)
    -
    - -
    -
    - -

    ◆ TIM_CCMR2_IC3F_Msk

    - -
    -
    - - - - -
    #define TIM_CCMR2_IC3F_Msk   (0xFUL << TIM_CCMR2_IC3F_Pos)
    -
    -

    0x000000F0

    - -
    -
    - -

    ◆ TIM_CCMR2_IC3F

    - -
    -
    - - - - -
    #define TIM_CCMR2_IC3F   TIM_CCMR2_IC3F_Msk
    -
    -

    IC3F[3:0] bits (Input Capture 3 Filter)

    - -
    -
    - -

    ◆ TIM_CCMR2_IC3F_0

    - -
    -
    - - - - -
    #define TIM_CCMR2_IC3F_0   (0x1UL << TIM_CCMR2_IC3F_Pos)
    -
    -

    0x0010

    - -
    -
    - -

    ◆ TIM_CCMR2_IC3F_1

    - -
    -
    - - - - -
    #define TIM_CCMR2_IC3F_1   (0x2UL << TIM_CCMR2_IC3F_Pos)
    -
    -

    0x0020

    - -
    -
    - -

    ◆ TIM_CCMR2_IC3F_2

    - -
    -
    - - - - -
    #define TIM_CCMR2_IC3F_2   (0x4UL << TIM_CCMR2_IC3F_Pos)
    -
    -

    0x0040

    - -
    -
    - -

    ◆ TIM_CCMR2_IC3F_3

    - -
    -
    - - - - -
    #define TIM_CCMR2_IC3F_3   (0x8UL << TIM_CCMR2_IC3F_Pos)
    -
    -

    0x0080

    - -
    -
    - -

    ◆ TIM_CCMR2_IC4PSC_Pos

    - -
    -
    - - - - -
    #define TIM_CCMR2_IC4PSC_Pos   (10U)
    -
    - -
    -
    - -

    ◆ TIM_CCMR2_IC4PSC_Msk

    - -
    -
    - - - - -
    #define TIM_CCMR2_IC4PSC_Msk   (0x3UL << TIM_CCMR2_IC4PSC_Pos)
    -
    -

    0x00000C00

    - -
    -
    - -

    ◆ TIM_CCMR2_IC4PSC

    - -
    -
    - - - - -
    #define TIM_CCMR2_IC4PSC   TIM_CCMR2_IC4PSC_Msk
    -
    -

    IC4PSC[1:0] bits (Input Capture 4 Prescaler)

    - -
    -
    - -

    ◆ TIM_CCMR2_IC4PSC_0

    - -
    -
    - - - - -
    #define TIM_CCMR2_IC4PSC_0   (0x1UL << TIM_CCMR2_IC4PSC_Pos)
    -
    -

    0x0400

    - -
    -
    - -

    ◆ TIM_CCMR2_IC4PSC_1

    - -
    -
    - - - - -
    #define TIM_CCMR2_IC4PSC_1   (0x2UL << TIM_CCMR2_IC4PSC_Pos)
    -
    -

    0x0800

    - -
    -
    - -

    ◆ TIM_CCMR2_IC4F_Pos

    - -
    -
    - - - - -
    #define TIM_CCMR2_IC4F_Pos   (12U)
    -
    - -
    -
    - -

    ◆ TIM_CCMR2_IC4F_Msk

    - -
    -
    - - - - -
    #define TIM_CCMR2_IC4F_Msk   (0xFUL << TIM_CCMR2_IC4F_Pos)
    -
    -

    0x0000F000

    - -
    -
    - -

    ◆ TIM_CCMR2_IC4F

    - -
    -
    - - - - -
    #define TIM_CCMR2_IC4F   TIM_CCMR2_IC4F_Msk
    -
    -

    IC4F[3:0] bits (Input Capture 4 Filter)

    - -
    -
    - -

    ◆ TIM_CCMR2_IC4F_0

    - -
    -
    - - - - -
    #define TIM_CCMR2_IC4F_0   (0x1UL << TIM_CCMR2_IC4F_Pos)
    -
    -

    0x1000

    - -
    -
    - -

    ◆ TIM_CCMR2_IC4F_1

    - -
    -
    - - - - -
    #define TIM_CCMR2_IC4F_1   (0x2UL << TIM_CCMR2_IC4F_Pos)
    -
    -

    0x2000

    - -
    -
    - -

    ◆ TIM_CCMR2_IC4F_2

    - -
    -
    - - - - -
    #define TIM_CCMR2_IC4F_2   (0x4UL << TIM_CCMR2_IC4F_Pos)
    -
    -

    0x4000

    - -
    -
    - -

    ◆ TIM_CCMR2_IC4F_3

    - -
    -
    - - - - -
    #define TIM_CCMR2_IC4F_3   (0x8UL << TIM_CCMR2_IC4F_Pos)
    -
    -

    0x8000

    - -
    -
    - -

    ◆ TIM_CCER_CC1E_Pos

    - -
    -
    - - - - -
    #define TIM_CCER_CC1E_Pos   (0U)
    -
    - -
    -
    - -

    ◆ TIM_CCER_CC1E_Msk

    - -
    -
    - - - - -
    #define TIM_CCER_CC1E_Msk   (0x1UL << TIM_CCER_CC1E_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ TIM_CCER_CC1E

    - -
    -
    - - - - -
    #define TIM_CCER_CC1E   TIM_CCER_CC1E_Msk
    -
    -

    Capture/Compare 1 output enable
    -

    - -
    -
    - -

    ◆ TIM_CCER_CC1P_Pos

    - -
    -
    - - - - -
    #define TIM_CCER_CC1P_Pos   (1U)
    -
    - -
    -
    - -

    ◆ TIM_CCER_CC1P_Msk

    - -
    -
    - - - - -
    #define TIM_CCER_CC1P_Msk   (0x1UL << TIM_CCER_CC1P_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ TIM_CCER_CC1P

    - -
    -
    - - - - -
    #define TIM_CCER_CC1P   TIM_CCER_CC1P_Msk
    -
    -

    Capture/Compare 1 output Polarity
    -

    - -
    -
    - -

    ◆ TIM_CCER_CC1NE_Pos

    - -
    -
    - - - - -
    #define TIM_CCER_CC1NE_Pos   (2U)
    -
    - -
    -
    - -

    ◆ TIM_CCER_CC1NE_Msk

    - -
    -
    - - - - -
    #define TIM_CCER_CC1NE_Msk   (0x1UL << TIM_CCER_CC1NE_Pos)
    -
    -

    0x00000004

    - -
    -
    - -

    ◆ TIM_CCER_CC1NE

    - -
    -
    - - - - -
    #define TIM_CCER_CC1NE   TIM_CCER_CC1NE_Msk
    -
    -

    Capture/Compare 1 Complementary output enable
    -

    - -
    -
    - -

    ◆ TIM_CCER_CC1NP_Pos

    - -
    -
    - - - - -
    #define TIM_CCER_CC1NP_Pos   (3U)
    -
    - -
    -
    - -

    ◆ TIM_CCER_CC1NP_Msk

    - -
    -
    - - - - -
    #define TIM_CCER_CC1NP_Msk   (0x1UL << TIM_CCER_CC1NP_Pos)
    -
    -

    0x00000008

    - -
    -
    - -

    ◆ TIM_CCER_CC1NP

    - -
    -
    - - - - -
    #define TIM_CCER_CC1NP   TIM_CCER_CC1NP_Msk
    -
    -

    Capture/Compare 1 Complementary output Polarity

    - -
    -
    - -

    ◆ TIM_CCER_CC2E_Pos

    - -
    -
    - - - - -
    #define TIM_CCER_CC2E_Pos   (4U)
    -
    - -
    -
    - -

    ◆ TIM_CCER_CC2E_Msk

    - -
    -
    - - - - -
    #define TIM_CCER_CC2E_Msk   (0x1UL << TIM_CCER_CC2E_Pos)
    -
    -

    0x00000010

    - -
    -
    - -

    ◆ TIM_CCER_CC2E

    - -
    -
    - - - - -
    #define TIM_CCER_CC2E   TIM_CCER_CC2E_Msk
    -
    -

    Capture/Compare 2 output enable
    -

    - -
    -
    - -

    ◆ TIM_CCER_CC2P_Pos

    - -
    -
    - - - - -
    #define TIM_CCER_CC2P_Pos   (5U)
    -
    - -
    -
    - -

    ◆ TIM_CCER_CC2P_Msk

    - -
    -
    - - - - -
    #define TIM_CCER_CC2P_Msk   (0x1UL << TIM_CCER_CC2P_Pos)
    -
    -

    0x00000020

    - -
    -
    - -

    ◆ TIM_CCER_CC2P

    - -
    -
    - - - - -
    #define TIM_CCER_CC2P   TIM_CCER_CC2P_Msk
    -
    -

    Capture/Compare 2 output Polarity
    -

    - -
    -
    - -

    ◆ TIM_CCER_CC2NE_Pos

    - -
    -
    - - - - -
    #define TIM_CCER_CC2NE_Pos   (6U)
    -
    - -
    -
    - -

    ◆ TIM_CCER_CC2NE_Msk

    - -
    -
    - - - - -
    #define TIM_CCER_CC2NE_Msk   (0x1UL << TIM_CCER_CC2NE_Pos)
    -
    -

    0x00000040

    - -
    -
    - -

    ◆ TIM_CCER_CC2NE

    - -
    -
    - - - - -
    #define TIM_CCER_CC2NE   TIM_CCER_CC2NE_Msk
    -
    -

    Capture/Compare 2 Complementary output enable
    -

    - -
    -
    - -

    ◆ TIM_CCER_CC2NP_Pos

    - -
    -
    - - - - -
    #define TIM_CCER_CC2NP_Pos   (7U)
    -
    - -
    -
    - -

    ◆ TIM_CCER_CC2NP_Msk

    - -
    -
    - - - - -
    #define TIM_CCER_CC2NP_Msk   (0x1UL << TIM_CCER_CC2NP_Pos)
    -
    -

    0x00000080

    - -
    -
    - -

    ◆ TIM_CCER_CC2NP

    - -
    -
    - - - - -
    #define TIM_CCER_CC2NP   TIM_CCER_CC2NP_Msk
    -
    -

    Capture/Compare 2 Complementary output Polarity

    - -
    -
    - -

    ◆ TIM_CCER_CC3E_Pos

    - -
    -
    - - - - -
    #define TIM_CCER_CC3E_Pos   (8U)
    -
    - -
    -
    - -

    ◆ TIM_CCER_CC3E_Msk

    - -
    -
    - - - - -
    #define TIM_CCER_CC3E_Msk   (0x1UL << TIM_CCER_CC3E_Pos)
    -
    -

    0x00000100

    - -
    -
    - -

    ◆ TIM_CCER_CC3E

    - -
    -
    - - - - -
    #define TIM_CCER_CC3E   TIM_CCER_CC3E_Msk
    -
    -

    Capture/Compare 3 output enable
    -

    - -
    -
    - -

    ◆ TIM_CCER_CC3P_Pos

    - -
    -
    - - - - -
    #define TIM_CCER_CC3P_Pos   (9U)
    -
    - -
    -
    - -

    ◆ TIM_CCER_CC3P_Msk

    - -
    -
    - - - - -
    #define TIM_CCER_CC3P_Msk   (0x1UL << TIM_CCER_CC3P_Pos)
    -
    -

    0x00000200

    - -
    -
    - -

    ◆ TIM_CCER_CC3P

    - -
    -
    - - - - -
    #define TIM_CCER_CC3P   TIM_CCER_CC3P_Msk
    -
    -

    Capture/Compare 3 output Polarity
    -

    - -
    -
    - -

    ◆ TIM_CCER_CC3NE_Pos

    - -
    -
    - - - - -
    #define TIM_CCER_CC3NE_Pos   (10U)
    -
    - -
    -
    - -

    ◆ TIM_CCER_CC3NE_Msk

    - -
    -
    - - - - -
    #define TIM_CCER_CC3NE_Msk   (0x1UL << TIM_CCER_CC3NE_Pos)
    -
    -

    0x00000400

    - -
    -
    - -

    ◆ TIM_CCER_CC3NE

    - -
    -
    - - - - -
    #define TIM_CCER_CC3NE   TIM_CCER_CC3NE_Msk
    -
    -

    Capture/Compare 3 Complementary output enable
    -

    - -
    -
    - -

    ◆ TIM_CCER_CC3NP_Pos

    - -
    -
    - - - - -
    #define TIM_CCER_CC3NP_Pos   (11U)
    -
    - -
    -
    - -

    ◆ TIM_CCER_CC3NP_Msk

    - -
    -
    - - - - -
    #define TIM_CCER_CC3NP_Msk   (0x1UL << TIM_CCER_CC3NP_Pos)
    -
    -

    0x00000800

    - -
    -
    - -

    ◆ TIM_CCER_CC3NP

    - -
    -
    - - - - -
    #define TIM_CCER_CC3NP   TIM_CCER_CC3NP_Msk
    -
    -

    Capture/Compare 3 Complementary output Polarity

    - -
    -
    - -

    ◆ TIM_CCER_CC4E_Pos

    - -
    -
    - - - - -
    #define TIM_CCER_CC4E_Pos   (12U)
    -
    - -
    -
    - -

    ◆ TIM_CCER_CC4E_Msk

    - -
    -
    - - - - -
    #define TIM_CCER_CC4E_Msk   (0x1UL << TIM_CCER_CC4E_Pos)
    -
    -

    0x00001000

    - -
    -
    - -

    ◆ TIM_CCER_CC4E

    - -
    -
    - - - - -
    #define TIM_CCER_CC4E   TIM_CCER_CC4E_Msk
    -
    -

    Capture/Compare 4 output enable
    -

    - -
    -
    - -

    ◆ TIM_CCER_CC4P_Pos

    - -
    -
    - - - - -
    #define TIM_CCER_CC4P_Pos   (13U)
    -
    - -
    -
    - -

    ◆ TIM_CCER_CC4P_Msk

    - -
    -
    - - - - -
    #define TIM_CCER_CC4P_Msk   (0x1UL << TIM_CCER_CC4P_Pos)
    -
    -

    0x00002000

    - -
    -
    - -

    ◆ TIM_CCER_CC4P

    - -
    -
    - - - - -
    #define TIM_CCER_CC4P   TIM_CCER_CC4P_Msk
    -
    -

    Capture/Compare 4 output Polarity
    -

    - -
    -
    - -

    ◆ TIM_CCER_CC4NP_Pos

    - -
    -
    - - - - -
    #define TIM_CCER_CC4NP_Pos   (15U)
    -
    - -
    -
    - -

    ◆ TIM_CCER_CC4NP_Msk

    - -
    -
    - - - - -
    #define TIM_CCER_CC4NP_Msk   (0x1UL << TIM_CCER_CC4NP_Pos)
    -
    -

    0x00008000

    - -
    -
    - -

    ◆ TIM_CCER_CC4NP

    - -
    -
    - - - - -
    #define TIM_CCER_CC4NP   TIM_CCER_CC4NP_Msk
    -
    -

    Capture/Compare 4 Complementary output Polarity

    - -
    -
    - -

    ◆ TIM_CNT_CNT_Pos

    - -
    -
    - - - - -
    #define TIM_CNT_CNT_Pos   (0U)
    -
    - -
    -
    - -

    ◆ TIM_CNT_CNT_Msk

    - -
    -
    - - - - -
    #define TIM_CNT_CNT_Msk   (0xFFFFFFFFUL << TIM_CNT_CNT_Pos)
    -
    -

    0xFFFFFFFF

    - -
    -
    - -

    ◆ TIM_CNT_CNT

    - -
    -
    - - - - -
    #define TIM_CNT_CNT   TIM_CNT_CNT_Msk
    -
    -

    Counter Value
    -

    - -
    -
    - -

    ◆ TIM_PSC_PSC_Pos

    - -
    -
    - - - - -
    #define TIM_PSC_PSC_Pos   (0U)
    -
    - -
    -
    - -

    ◆ TIM_PSC_PSC_Msk

    - -
    -
    - - - - -
    #define TIM_PSC_PSC_Msk   (0xFFFFUL << TIM_PSC_PSC_Pos)
    -
    -

    0x0000FFFF

    - -
    -
    - -

    ◆ TIM_PSC_PSC

    - -
    -
    - - - - -
    #define TIM_PSC_PSC   TIM_PSC_PSC_Msk
    -
    -

    Prescaler Value
    -

    - -
    -
    - -

    ◆ TIM_ARR_ARR_Pos

    - -
    -
    - - - - -
    #define TIM_ARR_ARR_Pos   (0U)
    -
    - -
    -
    - -

    ◆ TIM_ARR_ARR_Msk

    - -
    -
    - - - - -
    #define TIM_ARR_ARR_Msk   (0xFFFFFFFFUL << TIM_ARR_ARR_Pos)
    -
    -

    0xFFFFFFFF

    - -
    -
    - -

    ◆ TIM_ARR_ARR

    - -
    -
    - - - - -
    #define TIM_ARR_ARR   TIM_ARR_ARR_Msk
    -
    -

    actual auto-reload Value

    - -
    -
    - -

    ◆ TIM_RCR_REP_Pos

    - -
    -
    - - - - -
    #define TIM_RCR_REP_Pos   (0U)
    -
    - -
    -
    - -

    ◆ TIM_RCR_REP_Msk

    - -
    -
    - - - - -
    #define TIM_RCR_REP_Msk   (0xFFUL << TIM_RCR_REP_Pos)
    -
    -

    0x000000FF

    - -
    -
    - -

    ◆ TIM_RCR_REP

    - -
    -
    - - - - -
    #define TIM_RCR_REP   TIM_RCR_REP_Msk
    -
    -

    Repetition Counter Value

    - -
    -
    - -

    ◆ TIM_CCR1_CCR1_Pos

    - -
    -
    - - - - -
    #define TIM_CCR1_CCR1_Pos   (0U)
    -
    - -
    -
    - -

    ◆ TIM_CCR1_CCR1_Msk

    - -
    -
    - - - - -
    #define TIM_CCR1_CCR1_Msk   (0xFFFFUL << TIM_CCR1_CCR1_Pos)
    -
    -

    0x0000FFFF

    - -
    -
    - -

    ◆ TIM_CCR1_CCR1

    - -
    -
    - - - - -
    #define TIM_CCR1_CCR1   TIM_CCR1_CCR1_Msk
    -
    -

    Capture/Compare 1 Value
    -

    - -
    -
    - -

    ◆ TIM_CCR2_CCR2_Pos

    - -
    -
    - - - - -
    #define TIM_CCR2_CCR2_Pos   (0U)
    -
    - -
    -
    - -

    ◆ TIM_CCR2_CCR2_Msk

    - -
    -
    - - - - -
    #define TIM_CCR2_CCR2_Msk   (0xFFFFUL << TIM_CCR2_CCR2_Pos)
    -
    -

    0x0000FFFF

    - -
    -
    - -

    ◆ TIM_CCR2_CCR2

    - -
    -
    - - - - -
    #define TIM_CCR2_CCR2   TIM_CCR2_CCR2_Msk
    -
    -

    Capture/Compare 2 Value
    -

    - -
    -
    - -

    ◆ TIM_CCR3_CCR3_Pos

    - -
    -
    - - - - -
    #define TIM_CCR3_CCR3_Pos   (0U)
    -
    - -
    -
    - -

    ◆ TIM_CCR3_CCR3_Msk

    - -
    -
    - - - - -
    #define TIM_CCR3_CCR3_Msk   (0xFFFFUL << TIM_CCR3_CCR3_Pos)
    -
    -

    0x0000FFFF

    - -
    -
    - -

    ◆ TIM_CCR3_CCR3

    - -
    -
    - - - - -
    #define TIM_CCR3_CCR3   TIM_CCR3_CCR3_Msk
    -
    -

    Capture/Compare 3 Value
    -

    - -
    -
    - -

    ◆ TIM_CCR4_CCR4_Pos

    - -
    -
    - - - - -
    #define TIM_CCR4_CCR4_Pos   (0U)
    -
    - -
    -
    - -

    ◆ TIM_CCR4_CCR4_Msk

    - -
    -
    - - - - -
    #define TIM_CCR4_CCR4_Msk   (0xFFFFUL << TIM_CCR4_CCR4_Pos)
    -
    -

    0x0000FFFF

    - -
    -
    - -

    ◆ TIM_CCR4_CCR4

    - -
    -
    - - - - -
    #define TIM_CCR4_CCR4   TIM_CCR4_CCR4_Msk
    -
    -

    Capture/Compare 4 Value
    -

    - -
    -
    - -

    ◆ TIM_BDTR_DTG_Pos

    - -
    -
    - - - - -
    #define TIM_BDTR_DTG_Pos   (0U)
    -
    - -
    -
    - -

    ◆ TIM_BDTR_DTG_Msk

    - -
    -
    - - - - -
    #define TIM_BDTR_DTG_Msk   (0xFFUL << TIM_BDTR_DTG_Pos)
    -
    -

    0x000000FF

    - -
    -
    - -

    ◆ TIM_BDTR_DTG

    - -
    -
    - - - - -
    #define TIM_BDTR_DTG   TIM_BDTR_DTG_Msk
    -
    -

    DTG[0:7] bits (Dead-Time Generator set-up)

    - -
    -
    - -

    ◆ TIM_BDTR_DTG_0

    - -
    -
    - - - - -
    #define TIM_BDTR_DTG_0   (0x01UL << TIM_BDTR_DTG_Pos)
    -
    -

    0x0001

    - -
    -
    - -

    ◆ TIM_BDTR_DTG_1

    - -
    -
    - - - - -
    #define TIM_BDTR_DTG_1   (0x02UL << TIM_BDTR_DTG_Pos)
    -
    -

    0x0002

    - -
    -
    - -

    ◆ TIM_BDTR_DTG_2

    - -
    -
    - - - - -
    #define TIM_BDTR_DTG_2   (0x04UL << TIM_BDTR_DTG_Pos)
    -
    -

    0x0004

    - -
    -
    - -

    ◆ TIM_BDTR_DTG_3

    - -
    -
    - - - - -
    #define TIM_BDTR_DTG_3   (0x08UL << TIM_BDTR_DTG_Pos)
    -
    -

    0x0008

    - -
    -
    - -

    ◆ TIM_BDTR_DTG_4

    - -
    -
    - - - - -
    #define TIM_BDTR_DTG_4   (0x10UL << TIM_BDTR_DTG_Pos)
    -
    -

    0x0010

    - -
    -
    - -

    ◆ TIM_BDTR_DTG_5

    - -
    -
    - - - - -
    #define TIM_BDTR_DTG_5   (0x20UL << TIM_BDTR_DTG_Pos)
    -
    -

    0x0020

    - -
    -
    - -

    ◆ TIM_BDTR_DTG_6

    - -
    -
    - - - - -
    #define TIM_BDTR_DTG_6   (0x40UL << TIM_BDTR_DTG_Pos)
    -
    -

    0x0040

    - -
    -
    - -

    ◆ TIM_BDTR_DTG_7

    - -
    -
    - - - - -
    #define TIM_BDTR_DTG_7   (0x80UL << TIM_BDTR_DTG_Pos)
    -
    -

    0x0080

    - -
    -
    - -

    ◆ TIM_BDTR_LOCK_Pos

    - -
    -
    - - - - -
    #define TIM_BDTR_LOCK_Pos   (8U)
    -
    - -
    -
    - -

    ◆ TIM_BDTR_LOCK_Msk

    - -
    -
    - - - - -
    #define TIM_BDTR_LOCK_Msk   (0x3UL << TIM_BDTR_LOCK_Pos)
    -
    -

    0x00000300

    - -
    -
    - -

    ◆ TIM_BDTR_LOCK

    - -
    -
    - - - - -
    #define TIM_BDTR_LOCK   TIM_BDTR_LOCK_Msk
    -
    -

    LOCK[1:0] bits (Lock Configuration)

    - -
    -
    - -

    ◆ TIM_BDTR_LOCK_0

    - -
    -
    - - - - -
    #define TIM_BDTR_LOCK_0   (0x1UL << TIM_BDTR_LOCK_Pos)
    -
    -

    0x0100

    - -
    -
    - -

    ◆ TIM_BDTR_LOCK_1

    - -
    -
    - - - - -
    #define TIM_BDTR_LOCK_1   (0x2UL << TIM_BDTR_LOCK_Pos)
    -
    -

    0x0200

    - -
    -
    - -

    ◆ TIM_BDTR_OSSI_Pos

    - -
    -
    - - - - -
    #define TIM_BDTR_OSSI_Pos   (10U)
    -
    - -
    -
    - -

    ◆ TIM_BDTR_OSSI_Msk

    - -
    -
    - - - - -
    #define TIM_BDTR_OSSI_Msk   (0x1UL << TIM_BDTR_OSSI_Pos)
    -
    -

    0x00000400

    - -
    -
    - -

    ◆ TIM_BDTR_OSSI

    - -
    -
    - - - - -
    #define TIM_BDTR_OSSI   TIM_BDTR_OSSI_Msk
    -
    -

    Off-State Selection for Idle mode

    - -
    -
    - -

    ◆ TIM_BDTR_OSSR_Pos

    - -
    -
    - - - - -
    #define TIM_BDTR_OSSR_Pos   (11U)
    -
    - -
    -
    - -

    ◆ TIM_BDTR_OSSR_Msk

    - -
    -
    - - - - -
    #define TIM_BDTR_OSSR_Msk   (0x1UL << TIM_BDTR_OSSR_Pos)
    -
    -

    0x00000800

    - -
    -
    - -

    ◆ TIM_BDTR_OSSR

    - -
    -
    - - - - -
    #define TIM_BDTR_OSSR   TIM_BDTR_OSSR_Msk
    -
    -

    Off-State Selection for Run mode
    -

    - -
    -
    - -

    ◆ TIM_BDTR_BKE_Pos

    - -
    -
    - - - - -
    #define TIM_BDTR_BKE_Pos   (12U)
    -
    - -
    -
    - -

    ◆ TIM_BDTR_BKE_Msk

    - -
    -
    - - - - -
    #define TIM_BDTR_BKE_Msk   (0x1UL << TIM_BDTR_BKE_Pos)
    -
    -

    0x00001000

    - -
    -
    - -

    ◆ TIM_BDTR_BKE

    - -
    -
    - - - - -
    #define TIM_BDTR_BKE   TIM_BDTR_BKE_Msk
    -
    -

    Break enable
    -

    - -
    -
    - -

    ◆ TIM_BDTR_BKP_Pos

    - -
    -
    - - - - -
    #define TIM_BDTR_BKP_Pos   (13U)
    -
    - -
    -
    - -

    ◆ TIM_BDTR_BKP_Msk

    - -
    -
    - - - - -
    #define TIM_BDTR_BKP_Msk   (0x1UL << TIM_BDTR_BKP_Pos)
    -
    -

    0x00002000

    - -
    -
    - -

    ◆ TIM_BDTR_BKP

    - -
    -
    - - - - -
    #define TIM_BDTR_BKP   TIM_BDTR_BKP_Msk
    -
    -

    Break Polarity
    -

    - -
    -
    - -

    ◆ TIM_BDTR_AOE_Pos

    - -
    -
    - - - - -
    #define TIM_BDTR_AOE_Pos   (14U)
    -
    - -
    -
    - -

    ◆ TIM_BDTR_AOE_Msk

    - -
    -
    - - - - -
    #define TIM_BDTR_AOE_Msk   (0x1UL << TIM_BDTR_AOE_Pos)
    -
    -

    0x00004000

    - -
    -
    - -

    ◆ TIM_BDTR_AOE

    - -
    -
    - - - - -
    #define TIM_BDTR_AOE   TIM_BDTR_AOE_Msk
    -
    -

    Automatic Output enable
    -

    - -
    -
    - -

    ◆ TIM_BDTR_MOE_Pos

    - -
    -
    - - - - -
    #define TIM_BDTR_MOE_Pos   (15U)
    -
    - -
    -
    - -

    ◆ TIM_BDTR_MOE_Msk

    - -
    -
    - - - - -
    #define TIM_BDTR_MOE_Msk   (0x1UL << TIM_BDTR_MOE_Pos)
    -
    -

    0x00008000

    - -
    -
    - -

    ◆ TIM_BDTR_MOE

    - -
    -
    - - - - -
    #define TIM_BDTR_MOE   TIM_BDTR_MOE_Msk
    -
    -

    Main Output enable
    -

    - -
    -
    - -

    ◆ TIM_DCR_DBA_Pos

    - -
    -
    - - - - -
    #define TIM_DCR_DBA_Pos   (0U)
    -
    - -
    -
    - -

    ◆ TIM_DCR_DBA_Msk

    - -
    -
    - - - - -
    #define TIM_DCR_DBA_Msk   (0x1FUL << TIM_DCR_DBA_Pos)
    -
    -

    0x0000001F

    - -
    -
    - -

    ◆ TIM_DCR_DBA

    - -
    -
    - - - - -
    #define TIM_DCR_DBA   TIM_DCR_DBA_Msk
    -
    -

    DBA[4:0] bits (DMA Base Address)

    - -
    -
    - -

    ◆ TIM_DCR_DBA_0

    - -
    -
    - - - - -
    #define TIM_DCR_DBA_0   (0x01UL << TIM_DCR_DBA_Pos)
    -
    -

    0x0001

    - -
    -
    - -

    ◆ TIM_DCR_DBA_1

    - -
    -
    - - - - -
    #define TIM_DCR_DBA_1   (0x02UL << TIM_DCR_DBA_Pos)
    -
    -

    0x0002

    - -
    -
    - -

    ◆ TIM_DCR_DBA_2

    - -
    -
    - - - - -
    #define TIM_DCR_DBA_2   (0x04UL << TIM_DCR_DBA_Pos)
    -
    -

    0x0004

    - -
    -
    - -

    ◆ TIM_DCR_DBA_3

    - -
    -
    - - - - -
    #define TIM_DCR_DBA_3   (0x08UL << TIM_DCR_DBA_Pos)
    -
    -

    0x0008

    - -
    -
    - -

    ◆ TIM_DCR_DBA_4

    - -
    -
    - - - - -
    #define TIM_DCR_DBA_4   (0x10UL << TIM_DCR_DBA_Pos)
    -
    -

    0x0010

    - -
    -
    - -

    ◆ TIM_DCR_DBL_Pos

    - -
    -
    - - - - -
    #define TIM_DCR_DBL_Pos   (8U)
    -
    - -
    -
    - -

    ◆ TIM_DCR_DBL_Msk

    - -
    -
    - - - - -
    #define TIM_DCR_DBL_Msk   (0x1FUL << TIM_DCR_DBL_Pos)
    -
    -

    0x00001F00

    - -
    -
    - -

    ◆ TIM_DCR_DBL

    - -
    -
    - - - - -
    #define TIM_DCR_DBL   TIM_DCR_DBL_Msk
    -
    -

    DBL[4:0] bits (DMA Burst Length)

    - -
    -
    - -

    ◆ TIM_DCR_DBL_0

    - -
    -
    - - - - -
    #define TIM_DCR_DBL_0   (0x01UL << TIM_DCR_DBL_Pos)
    -
    -

    0x0100

    - -
    -
    - -

    ◆ TIM_DCR_DBL_1

    - -
    -
    - - - - -
    #define TIM_DCR_DBL_1   (0x02UL << TIM_DCR_DBL_Pos)
    -
    -

    0x0200

    - -
    -
    - -

    ◆ TIM_DCR_DBL_2

    - -
    -
    - - - - -
    #define TIM_DCR_DBL_2   (0x04UL << TIM_DCR_DBL_Pos)
    -
    -

    0x0400

    - -
    -
    - -

    ◆ TIM_DCR_DBL_3

    - -
    -
    - - - - -
    #define TIM_DCR_DBL_3   (0x08UL << TIM_DCR_DBL_Pos)
    -
    -

    0x0800

    - -
    -
    - -

    ◆ TIM_DCR_DBL_4

    - -
    -
    - - - - -
    #define TIM_DCR_DBL_4   (0x10UL << TIM_DCR_DBL_Pos)
    -
    -

    0x1000

    - -
    -
    - -

    ◆ TIM_DMAR_DMAB_Pos

    - -
    -
    - - - - -
    #define TIM_DMAR_DMAB_Pos   (0U)
    -
    - -
    -
    - -

    ◆ TIM_DMAR_DMAB_Msk

    - -
    -
    - - - - -
    #define TIM_DMAR_DMAB_Msk   (0xFFFFUL << TIM_DMAR_DMAB_Pos)
    -
    -

    0x0000FFFF

    - -
    -
    - -

    ◆ TIM_DMAR_DMAB

    - -
    -
    - - - - -
    #define TIM_DMAR_DMAB   TIM_DMAR_DMAB_Msk
    -
    -

    DMA register for burst accesses
    -

    - -
    -
    - -

    ◆ TIM_OR_TI1_RMP_Pos

    - -
    -
    - - - - -
    #define TIM_OR_TI1_RMP_Pos   (0U)
    -
    - -
    -
    - -

    ◆ TIM_OR_TI1_RMP_Msk

    - -
    -
    - - - - -
    #define TIM_OR_TI1_RMP_Msk   (0x3UL << TIM_OR_TI1_RMP_Pos)
    -
    -

    0x00000003

    - -
    -
    - -

    ◆ TIM_OR_TI1_RMP

    - -
    -
    - - - - -
    #define TIM_OR_TI1_RMP   TIM_OR_TI1_RMP_Msk
    -
    -

    TI1_RMP[1:0] bits (TIM11 Input Capture 1 remap)

    - -
    -
    - -

    ◆ TIM_OR_TI1_RMP_0

    - -
    -
    - - - - -
    #define TIM_OR_TI1_RMP_0   (0x1UL << TIM_OR_TI1_RMP_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ TIM_OR_TI1_RMP_1

    - -
    -
    - - - - -
    #define TIM_OR_TI1_RMP_1   (0x2UL << TIM_OR_TI1_RMP_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ TIM_OR_TI4_RMP_Pos

    - -
    -
    - - - - -
    #define TIM_OR_TI4_RMP_Pos   (6U)
    -
    - -
    -
    - -

    ◆ TIM_OR_TI4_RMP_Msk

    - -
    -
    - - - - -
    #define TIM_OR_TI4_RMP_Msk   (0x3UL << TIM_OR_TI4_RMP_Pos)
    -
    -

    0x000000C0

    - -
    -
    - -

    ◆ TIM_OR_TI4_RMP

    - -
    -
    - - - - -
    #define TIM_OR_TI4_RMP   TIM_OR_TI4_RMP_Msk
    -
    -

    TI4_RMP[1:0] bits (TIM5 Input 4 remap)
    -

    - -
    -
    - -

    ◆ TIM_OR_TI4_RMP_0

    - -
    -
    - - - - -
    #define TIM_OR_TI4_RMP_0   (0x1UL << TIM_OR_TI4_RMP_Pos)
    -
    -

    0x0040

    - -
    -
    - -

    ◆ TIM_OR_TI4_RMP_1

    - -
    -
    - - - - -
    #define TIM_OR_TI4_RMP_1   (0x2UL << TIM_OR_TI4_RMP_Pos)
    -
    -

    0x0080

    - -
    -
    - -

    ◆ TIM_OR_ITR1_RMP_Pos

    - -
    -
    - - - - -
    #define TIM_OR_ITR1_RMP_Pos   (10U)
    -
    - -
    -
    - -

    ◆ TIM_OR_ITR1_RMP_Msk

    - -
    -
    - - - - -
    #define TIM_OR_ITR1_RMP_Msk   (0x3UL << TIM_OR_ITR1_RMP_Pos)
    -
    -

    0x00000C00

    - -
    -
    - -

    ◆ TIM_OR_ITR1_RMP

    - -
    -
    - - - - -
    #define TIM_OR_ITR1_RMP   TIM_OR_ITR1_RMP_Msk
    -
    -

    ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap)

    - -
    -
    - -

    ◆ TIM_OR_ITR1_RMP_0

    - -
    -
    - - - - -
    #define TIM_OR_ITR1_RMP_0   (0x1UL << TIM_OR_ITR1_RMP_Pos)
    -
    -

    0x0400

    - -
    -
    - -

    ◆ TIM_OR_ITR1_RMP_1

    - -
    -
    - - - - -
    #define TIM_OR_ITR1_RMP_1   (0x2UL << TIM_OR_ITR1_RMP_Pos)
    -
    -

    0x0800

    - -
    -
    - -

    ◆ USART_SR_PE_Pos

    - -
    -
    - - - - -
    #define USART_SR_PE_Pos   (0U)
    -
    - -
    -
    - -

    ◆ USART_SR_PE_Msk

    - -
    -
    - - - - -
    #define USART_SR_PE_Msk   (0x1UL << USART_SR_PE_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ USART_SR_PE

    - -
    -
    - - - - -
    #define USART_SR_PE   USART_SR_PE_Msk
    -
    -

    Parity Error
    -

    - -
    -
    - -

    ◆ USART_SR_FE_Pos

    - -
    -
    - - - - -
    #define USART_SR_FE_Pos   (1U)
    -
    - -
    -
    - -

    ◆ USART_SR_FE_Msk

    - -
    -
    - - - - -
    #define USART_SR_FE_Msk   (0x1UL << USART_SR_FE_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ USART_SR_FE

    - -
    -
    - - - - -
    #define USART_SR_FE   USART_SR_FE_Msk
    -
    -

    Framing Error
    -

    - -
    -
    - -

    ◆ USART_SR_NE_Pos

    - -
    -
    - - - - -
    #define USART_SR_NE_Pos   (2U)
    -
    - -
    -
    - -

    ◆ USART_SR_NE_Msk

    - -
    -
    - - - - -
    #define USART_SR_NE_Msk   (0x1UL << USART_SR_NE_Pos)
    -
    -

    0x00000004

    - -
    -
    - -

    ◆ USART_SR_NE

    - -
    -
    - - - - -
    #define USART_SR_NE   USART_SR_NE_Msk
    -
    -

    Noise Error Flag
    -

    - -
    -
    - -

    ◆ USART_SR_ORE_Pos

    - -
    -
    - - - - -
    #define USART_SR_ORE_Pos   (3U)
    -
    - -
    -
    - -

    ◆ USART_SR_ORE_Msk

    - -
    -
    - - - - -
    #define USART_SR_ORE_Msk   (0x1UL << USART_SR_ORE_Pos)
    -
    -

    0x00000008

    - -
    -
    - -

    ◆ USART_SR_ORE

    - -
    -
    - - - - -
    #define USART_SR_ORE   USART_SR_ORE_Msk
    -
    -

    OverRun Error
    -

    - -
    -
    - -

    ◆ USART_SR_IDLE_Pos

    - -
    -
    - - - - -
    #define USART_SR_IDLE_Pos   (4U)
    -
    - -
    -
    - -

    ◆ USART_SR_IDLE_Msk

    - -
    -
    - - - - -
    #define USART_SR_IDLE_Msk   (0x1UL << USART_SR_IDLE_Pos)
    -
    -

    0x00000010

    - -
    -
    - -

    ◆ USART_SR_IDLE

    - -
    -
    - - - - -
    #define USART_SR_IDLE   USART_SR_IDLE_Msk
    -
    -

    IDLE line detected
    -

    - -
    -
    - -

    ◆ USART_SR_RXNE_Pos

    - -
    -
    - - - - -
    #define USART_SR_RXNE_Pos   (5U)
    -
    - -
    -
    - -

    ◆ USART_SR_RXNE_Msk

    - -
    -
    - - - - -
    #define USART_SR_RXNE_Msk   (0x1UL << USART_SR_RXNE_Pos)
    -
    -

    0x00000020

    - -
    -
    - -

    ◆ USART_SR_RXNE

    - -
    -
    - - - - -
    #define USART_SR_RXNE   USART_SR_RXNE_Msk
    -
    -

    Read Data Register Not Empty

    - -
    -
    - -

    ◆ USART_SR_TC_Pos

    - -
    -
    - - - - -
    #define USART_SR_TC_Pos   (6U)
    -
    - -
    -
    - -

    ◆ USART_SR_TC_Msk

    - -
    -
    - - - - -
    #define USART_SR_TC_Msk   (0x1UL << USART_SR_TC_Pos)
    -
    -

    0x00000040

    - -
    -
    - -

    ◆ USART_SR_TC

    - -
    -
    - - - - -
    #define USART_SR_TC   USART_SR_TC_Msk
    -
    -

    Transmission Complete
    -

    - -
    -
    - -

    ◆ USART_SR_TXE_Pos

    - -
    -
    - - - - -
    #define USART_SR_TXE_Pos   (7U)
    -
    - -
    -
    - -

    ◆ USART_SR_TXE_Msk

    - -
    -
    - - - - -
    #define USART_SR_TXE_Msk   (0x1UL << USART_SR_TXE_Pos)
    -
    -

    0x00000080

    - -
    -
    - -

    ◆ USART_SR_TXE

    - -
    -
    - - - - -
    #define USART_SR_TXE   USART_SR_TXE_Msk
    -
    -

    Transmit Data Register Empty

    - -
    -
    - -

    ◆ USART_SR_LBD_Pos

    - -
    -
    - - - - -
    #define USART_SR_LBD_Pos   (8U)
    -
    - -
    -
    - -

    ◆ USART_SR_LBD_Msk

    - -
    -
    - - - - -
    #define USART_SR_LBD_Msk   (0x1UL << USART_SR_LBD_Pos)
    -
    -

    0x00000100

    - -
    -
    - -

    ◆ USART_SR_LBD

    - -
    -
    - - - - -
    #define USART_SR_LBD   USART_SR_LBD_Msk
    -
    -

    LIN Break Detection Flag
    -

    - -
    -
    - -

    ◆ USART_SR_CTS_Pos

    - -
    -
    - - - - -
    #define USART_SR_CTS_Pos   (9U)
    -
    - -
    -
    - -

    ◆ USART_SR_CTS_Msk

    - -
    -
    - - - - -
    #define USART_SR_CTS_Msk   (0x1UL << USART_SR_CTS_Pos)
    -
    -

    0x00000200

    - -
    -
    - -

    ◆ USART_SR_CTS

    - -
    -
    - - - - -
    #define USART_SR_CTS   USART_SR_CTS_Msk
    -
    -

    CTS Flag
    -

    - -
    -
    - -

    ◆ USART_DR_DR_Pos

    - -
    -
    - - - - -
    #define USART_DR_DR_Pos   (0U)
    -
    - -
    -
    - -

    ◆ USART_DR_DR_Msk

    - -
    -
    - - - - -
    #define USART_DR_DR_Msk   (0x1FFUL << USART_DR_DR_Pos)
    -
    -

    0x000001FF

    - -
    -
    - -

    ◆ USART_DR_DR

    - -
    -
    - - - - -
    #define USART_DR_DR   USART_DR_DR_Msk
    -
    -

    Data value

    - -
    -
    - -

    ◆ USART_BRR_DIV_Fraction_Pos

    - -
    -
    - - - - -
    #define USART_BRR_DIV_Fraction_Pos   (0U)
    -
    - -
    -
    - -

    ◆ USART_BRR_DIV_Fraction_Msk

    - -
    -
    - - - - -
    #define USART_BRR_DIV_Fraction_Msk   (0xFUL << USART_BRR_DIV_Fraction_Pos)
    -
    -

    0x0000000F

    - -
    -
    - -

    ◆ USART_BRR_DIV_Fraction

    - -
    -
    - - - - -
    #define USART_BRR_DIV_Fraction   USART_BRR_DIV_Fraction_Msk
    -
    -

    Fraction of USARTDIV

    - -
    -
    - -

    ◆ USART_BRR_DIV_Mantissa_Pos

    - -
    -
    - - - - -
    #define USART_BRR_DIV_Mantissa_Pos   (4U)
    -
    - -
    -
    - -

    ◆ USART_BRR_DIV_Mantissa_Msk

    - -
    -
    - - - - -
    #define USART_BRR_DIV_Mantissa_Msk   (0xFFFUL << USART_BRR_DIV_Mantissa_Pos)
    -
    -

    0x0000FFF0

    - -
    -
    - -

    ◆ USART_BRR_DIV_Mantissa

    - -
    -
    - - - - -
    #define USART_BRR_DIV_Mantissa   USART_BRR_DIV_Mantissa_Msk
    -
    -

    Mantissa of USARTDIV

    - -
    -
    - -

    ◆ USART_CR1_SBK_Pos

    - -
    -
    - - - - -
    #define USART_CR1_SBK_Pos   (0U)
    -
    - -
    -
    - -

    ◆ USART_CR1_SBK_Msk

    - -
    -
    - - - - -
    #define USART_CR1_SBK_Msk   (0x1UL << USART_CR1_SBK_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ USART_CR1_SBK

    - -
    -
    - - - - -
    #define USART_CR1_SBK   USART_CR1_SBK_Msk
    -
    -

    Send Break
    -

    - -
    -
    - -

    ◆ USART_CR1_RWU_Pos

    - -
    -
    - - - - -
    #define USART_CR1_RWU_Pos   (1U)
    -
    - -
    -
    - -

    ◆ USART_CR1_RWU_Msk

    - -
    -
    - - - - -
    #define USART_CR1_RWU_Msk   (0x1UL << USART_CR1_RWU_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ USART_CR1_RWU

    - -
    -
    - - - - -
    #define USART_CR1_RWU   USART_CR1_RWU_Msk
    -
    -

    Receiver wakeup
    -

    - -
    -
    - -

    ◆ USART_CR1_RE_Pos

    - -
    -
    - - - - -
    #define USART_CR1_RE_Pos   (2U)
    -
    - -
    -
    - -

    ◆ USART_CR1_RE_Msk

    - -
    -
    - - - - -
    #define USART_CR1_RE_Msk   (0x1UL << USART_CR1_RE_Pos)
    -
    -

    0x00000004

    - -
    -
    - -

    ◆ USART_CR1_RE

    - -
    -
    - - - - -
    #define USART_CR1_RE   USART_CR1_RE_Msk
    -
    -

    Receiver Enable
    -

    - -
    -
    - -

    ◆ USART_CR1_TE_Pos

    - -
    -
    - - - - -
    #define USART_CR1_TE_Pos   (3U)
    -
    - -
    -
    - -

    ◆ USART_CR1_TE_Msk

    - -
    -
    - - - - -
    #define USART_CR1_TE_Msk   (0x1UL << USART_CR1_TE_Pos)
    -
    -

    0x00000008

    - -
    -
    - -

    ◆ USART_CR1_TE

    - -
    -
    - - - - -
    #define USART_CR1_TE   USART_CR1_TE_Msk
    -
    -

    Transmitter Enable
    -

    - -
    -
    - -

    ◆ USART_CR1_IDLEIE_Pos

    - -
    -
    - - - - -
    #define USART_CR1_IDLEIE_Pos   (4U)
    -
    - -
    -
    - -

    ◆ USART_CR1_IDLEIE_Msk

    - -
    -
    - - - - -
    #define USART_CR1_IDLEIE_Msk   (0x1UL << USART_CR1_IDLEIE_Pos)
    -
    -

    0x00000010

    - -
    -
    - -

    ◆ USART_CR1_IDLEIE

    - -
    -
    - - - - -
    #define USART_CR1_IDLEIE   USART_CR1_IDLEIE_Msk
    -
    -

    IDLE Interrupt Enable
    -

    - -
    -
    - -

    ◆ USART_CR1_RXNEIE_Pos

    - -
    -
    - - - - -
    #define USART_CR1_RXNEIE_Pos   (5U)
    -
    - -
    -
    - -

    ◆ USART_CR1_RXNEIE_Msk

    - -
    -
    - - - - -
    #define USART_CR1_RXNEIE_Msk   (0x1UL << USART_CR1_RXNEIE_Pos)
    -
    -

    0x00000020

    - -
    -
    - -

    ◆ USART_CR1_RXNEIE

    - -
    -
    - - - - -
    #define USART_CR1_RXNEIE   USART_CR1_RXNEIE_Msk
    -
    -

    RXNE Interrupt Enable
    -

    - -
    -
    - -

    ◆ USART_CR1_TCIE_Pos

    - -
    -
    - - - - -
    #define USART_CR1_TCIE_Pos   (6U)
    -
    - -
    -
    - -

    ◆ USART_CR1_TCIE_Msk

    - -
    -
    - - - - -
    #define USART_CR1_TCIE_Msk   (0x1UL << USART_CR1_TCIE_Pos)
    -
    -

    0x00000040

    - -
    -
    - -

    ◆ USART_CR1_TCIE

    - -
    -
    - - - - -
    #define USART_CR1_TCIE   USART_CR1_TCIE_Msk
    -
    -

    Transmission Complete Interrupt Enable

    - -
    -
    - -

    ◆ USART_CR1_TXEIE_Pos

    - -
    -
    - - - - -
    #define USART_CR1_TXEIE_Pos   (7U)
    -
    - -
    -
    - -

    ◆ USART_CR1_TXEIE_Msk

    - -
    -
    - - - - -
    #define USART_CR1_TXEIE_Msk   (0x1UL << USART_CR1_TXEIE_Pos)
    -
    -

    0x00000080

    - -
    -
    - -

    ◆ USART_CR1_TXEIE

    - -
    -
    - - - - -
    #define USART_CR1_TXEIE   USART_CR1_TXEIE_Msk
    -
    -

    TXE Interrupt Enable
    -

    - -
    -
    - -

    ◆ USART_CR1_PEIE_Pos

    - -
    -
    - - - - -
    #define USART_CR1_PEIE_Pos   (8U)
    -
    - -
    -
    - -

    ◆ USART_CR1_PEIE_Msk

    - -
    -
    - - - - -
    #define USART_CR1_PEIE_Msk   (0x1UL << USART_CR1_PEIE_Pos)
    -
    -

    0x00000100

    - -
    -
    - -

    ◆ USART_CR1_PEIE

    - -
    -
    - - - - -
    #define USART_CR1_PEIE   USART_CR1_PEIE_Msk
    -
    -

    PE Interrupt Enable
    -

    - -
    -
    - -

    ◆ USART_CR1_PS_Pos

    - -
    -
    - - - - -
    #define USART_CR1_PS_Pos   (9U)
    -
    - -
    -
    - -

    ◆ USART_CR1_PS_Msk

    - -
    -
    - - - - -
    #define USART_CR1_PS_Msk   (0x1UL << USART_CR1_PS_Pos)
    -
    -

    0x00000200

    - -
    -
    - -

    ◆ USART_CR1_PS

    - -
    -
    - - - - -
    #define USART_CR1_PS   USART_CR1_PS_Msk
    -
    -

    Parity Selection
    -

    - -
    -
    - -

    ◆ USART_CR1_PCE_Pos

    - -
    -
    - - - - -
    #define USART_CR1_PCE_Pos   (10U)
    -
    - -
    -
    - -

    ◆ USART_CR1_PCE_Msk

    - -
    -
    - - - - -
    #define USART_CR1_PCE_Msk   (0x1UL << USART_CR1_PCE_Pos)
    -
    -

    0x00000400

    - -
    -
    - -

    ◆ USART_CR1_PCE

    - -
    -
    - - - - -
    #define USART_CR1_PCE   USART_CR1_PCE_Msk
    -
    -

    Parity Control Enable
    -

    - -
    -
    - -

    ◆ USART_CR1_WAKE_Pos

    - -
    -
    - - - - -
    #define USART_CR1_WAKE_Pos   (11U)
    -
    - -
    -
    - -

    ◆ USART_CR1_WAKE_Msk

    - -
    -
    - - - - -
    #define USART_CR1_WAKE_Msk   (0x1UL << USART_CR1_WAKE_Pos)
    -
    -

    0x00000800

    - -
    -
    - -

    ◆ USART_CR1_WAKE

    - -
    -
    - - - - -
    #define USART_CR1_WAKE   USART_CR1_WAKE_Msk
    -
    -

    Wakeup method
    -

    - -
    -
    - -

    ◆ USART_CR1_M_Pos

    - -
    -
    - - - - -
    #define USART_CR1_M_Pos   (12U)
    -
    - -
    -
    - -

    ◆ USART_CR1_M_Msk

    - -
    -
    - - - - -
    #define USART_CR1_M_Msk   (0x1UL << USART_CR1_M_Pos)
    -
    -

    0x00001000

    - -
    -
    - -

    ◆ USART_CR1_M

    - -
    -
    - - - - -
    #define USART_CR1_M   USART_CR1_M_Msk
    -
    -

    Word length
    -

    - -
    -
    - -

    ◆ USART_CR1_UE_Pos

    - -
    -
    - - - - -
    #define USART_CR1_UE_Pos   (13U)
    -
    - -
    -
    - -

    ◆ USART_CR1_UE_Msk

    - -
    -
    - - - - -
    #define USART_CR1_UE_Msk   (0x1UL << USART_CR1_UE_Pos)
    -
    -

    0x00002000

    - -
    -
    - -

    ◆ USART_CR1_UE

    - -
    -
    - - - - -
    #define USART_CR1_UE   USART_CR1_UE_Msk
    -
    -

    USART Enable
    -

    - -
    -
    - -

    ◆ USART_CR1_OVER8_Pos

    - -
    -
    - - - - -
    #define USART_CR1_OVER8_Pos   (15U)
    -
    - -
    -
    - -

    ◆ USART_CR1_OVER8_Msk

    - -
    -
    - - - - -
    #define USART_CR1_OVER8_Msk   (0x1UL << USART_CR1_OVER8_Pos)
    -
    -

    0x00008000

    - -
    -
    - -

    ◆ USART_CR1_OVER8

    - -
    -
    - - - - -
    #define USART_CR1_OVER8   USART_CR1_OVER8_Msk
    -
    -

    USART Oversampling by 8 enable
    -

    - -
    -
    - -

    ◆ USART_CR2_ADD_Pos

    - -
    -
    - - - - -
    #define USART_CR2_ADD_Pos   (0U)
    -
    - -
    -
    - -

    ◆ USART_CR2_ADD_Msk

    - -
    -
    - - - - -
    #define USART_CR2_ADD_Msk   (0xFUL << USART_CR2_ADD_Pos)
    -
    -

    0x0000000F

    - -
    -
    - -

    ◆ USART_CR2_ADD

    - -
    -
    - - - - -
    #define USART_CR2_ADD   USART_CR2_ADD_Msk
    -
    -

    Address of the USART node
    -

    - -
    -
    - -

    ◆ USART_CR2_LBDL_Pos

    - -
    -
    - - - - -
    #define USART_CR2_LBDL_Pos   (5U)
    -
    - -
    -
    - -

    ◆ USART_CR2_LBDL_Msk

    - -
    -
    - - - - -
    #define USART_CR2_LBDL_Msk   (0x1UL << USART_CR2_LBDL_Pos)
    -
    -

    0x00000020

    - -
    -
    - -

    ◆ USART_CR2_LBDL

    - -
    -
    - - - - -
    #define USART_CR2_LBDL   USART_CR2_LBDL_Msk
    -
    -

    LIN Break Detection Length
    -

    - -
    -
    - -

    ◆ USART_CR2_LBDIE_Pos

    - -
    -
    - - - - -
    #define USART_CR2_LBDIE_Pos   (6U)
    -
    - -
    -
    - -

    ◆ USART_CR2_LBDIE_Msk

    - -
    -
    - - - - -
    #define USART_CR2_LBDIE_Msk   (0x1UL << USART_CR2_LBDIE_Pos)
    -
    -

    0x00000040

    - -
    -
    - -

    ◆ USART_CR2_LBDIE

    - -
    -
    - - - - -
    #define USART_CR2_LBDIE   USART_CR2_LBDIE_Msk
    -
    -

    LIN Break Detection Interrupt Enable

    - -
    -
    - -

    ◆ USART_CR2_LBCL_Pos

    - -
    -
    - - - - -
    #define USART_CR2_LBCL_Pos   (8U)
    -
    - -
    -
    - -

    ◆ USART_CR2_LBCL_Msk

    - -
    -
    - - - - -
    #define USART_CR2_LBCL_Msk   (0x1UL << USART_CR2_LBCL_Pos)
    -
    -

    0x00000100

    - -
    -
    - -

    ◆ USART_CR2_LBCL

    - -
    -
    - - - - -
    #define USART_CR2_LBCL   USART_CR2_LBCL_Msk
    -
    -

    Last Bit Clock pulse
    -

    - -
    -
    - -

    ◆ USART_CR2_CPHA_Pos

    - -
    -
    - - - - -
    #define USART_CR2_CPHA_Pos   (9U)
    -
    - -
    -
    - -

    ◆ USART_CR2_CPHA_Msk

    - -
    -
    - - - - -
    #define USART_CR2_CPHA_Msk   (0x1UL << USART_CR2_CPHA_Pos)
    -
    -

    0x00000200

    - -
    -
    - -

    ◆ USART_CR2_CPHA

    - -
    -
    - - - - -
    #define USART_CR2_CPHA   USART_CR2_CPHA_Msk
    -
    -

    Clock Phase
    -

    - -
    -
    - -

    ◆ USART_CR2_CPOL_Pos

    - -
    -
    - - - - -
    #define USART_CR2_CPOL_Pos   (10U)
    -
    - -
    -
    - -

    ◆ USART_CR2_CPOL_Msk

    - -
    -
    - - - - -
    #define USART_CR2_CPOL_Msk   (0x1UL << USART_CR2_CPOL_Pos)
    -
    -

    0x00000400

    - -
    -
    - -

    ◆ USART_CR2_CPOL

    - -
    -
    - - - - -
    #define USART_CR2_CPOL   USART_CR2_CPOL_Msk
    -
    -

    Clock Polarity
    -

    - -
    -
    - -

    ◆ USART_CR2_CLKEN_Pos

    - -
    -
    - - - - -
    #define USART_CR2_CLKEN_Pos   (11U)
    -
    - -
    -
    - -

    ◆ USART_CR2_CLKEN_Msk

    - -
    -
    - - - - -
    #define USART_CR2_CLKEN_Msk   (0x1UL << USART_CR2_CLKEN_Pos)
    -
    -

    0x00000800

    - -
    -
    - -

    ◆ USART_CR2_CLKEN

    - -
    -
    - - - - -
    #define USART_CR2_CLKEN   USART_CR2_CLKEN_Msk
    -
    -

    Clock Enable
    -

    - -
    -
    - -

    ◆ USART_CR2_STOP_Pos

    - -
    -
    - - - - -
    #define USART_CR2_STOP_Pos   (12U)
    -
    - -
    -
    - -

    ◆ USART_CR2_STOP_Msk

    - -
    -
    - - - - -
    #define USART_CR2_STOP_Msk   (0x3UL << USART_CR2_STOP_Pos)
    -
    -

    0x00003000

    - -
    -
    - -

    ◆ USART_CR2_STOP

    - -
    -
    - - - - -
    #define USART_CR2_STOP   USART_CR2_STOP_Msk
    -
    -

    STOP[1:0] bits (STOP bits)

    - -
    -
    - -

    ◆ USART_CR2_STOP_0

    - -
    -
    - - - - -
    #define USART_CR2_STOP_0   (0x1UL << USART_CR2_STOP_Pos)
    -
    -

    0x1000

    - -
    -
    - -

    ◆ USART_CR2_STOP_1

    - -
    -
    - - - - -
    #define USART_CR2_STOP_1   (0x2UL << USART_CR2_STOP_Pos)
    -
    -

    0x2000

    - -
    -
    - -

    ◆ USART_CR2_LINEN_Pos

    - -
    -
    - - - - -
    #define USART_CR2_LINEN_Pos   (14U)
    -
    - -
    -
    - -

    ◆ USART_CR2_LINEN_Msk

    - -
    -
    - - - - -
    #define USART_CR2_LINEN_Msk   (0x1UL << USART_CR2_LINEN_Pos)
    -
    -

    0x00004000

    - -
    -
    - -

    ◆ USART_CR2_LINEN

    - -
    -
    - - - - -
    #define USART_CR2_LINEN   USART_CR2_LINEN_Msk
    -
    -

    LIN mode enable

    - -
    -
    - -

    ◆ USART_CR3_EIE_Pos

    - -
    -
    - - - - -
    #define USART_CR3_EIE_Pos   (0U)
    -
    - -
    -
    - -

    ◆ USART_CR3_EIE_Msk

    - -
    -
    - - - - -
    #define USART_CR3_EIE_Msk   (0x1UL << USART_CR3_EIE_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ USART_CR3_EIE

    - -
    -
    - - - - -
    #define USART_CR3_EIE   USART_CR3_EIE_Msk
    -
    -

    Error Interrupt Enable
    -

    - -
    -
    - -

    ◆ USART_CR3_IREN_Pos

    - -
    -
    - - - - -
    #define USART_CR3_IREN_Pos   (1U)
    -
    - -
    -
    - -

    ◆ USART_CR3_IREN_Msk

    - -
    -
    - - - - -
    #define USART_CR3_IREN_Msk   (0x1UL << USART_CR3_IREN_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ USART_CR3_IREN

    - -
    -
    - - - - -
    #define USART_CR3_IREN   USART_CR3_IREN_Msk
    -
    -

    IrDA mode Enable
    -

    - -
    -
    - -

    ◆ USART_CR3_IRLP_Pos

    - -
    -
    - - - - -
    #define USART_CR3_IRLP_Pos   (2U)
    -
    - -
    -
    - -

    ◆ USART_CR3_IRLP_Msk

    - -
    -
    - - - - -
    #define USART_CR3_IRLP_Msk   (0x1UL << USART_CR3_IRLP_Pos)
    -
    -

    0x00000004

    - -
    -
    - -

    ◆ USART_CR3_IRLP

    - -
    -
    - - - - -
    #define USART_CR3_IRLP   USART_CR3_IRLP_Msk
    -
    -

    IrDA Low-Power
    -

    - -
    -
    - -

    ◆ USART_CR3_HDSEL_Pos

    - -
    -
    - - - - -
    #define USART_CR3_HDSEL_Pos   (3U)
    -
    - -
    -
    - -

    ◆ USART_CR3_HDSEL_Msk

    - -
    -
    - - - - -
    #define USART_CR3_HDSEL_Msk   (0x1UL << USART_CR3_HDSEL_Pos)
    -
    -

    0x00000008

    - -
    -
    - -

    ◆ USART_CR3_HDSEL

    - -
    -
    - - - - -
    #define USART_CR3_HDSEL   USART_CR3_HDSEL_Msk
    -
    -

    Half-Duplex Selection
    -

    - -
    -
    - -

    ◆ USART_CR3_NACK_Pos

    - -
    -
    - - - - -
    #define USART_CR3_NACK_Pos   (4U)
    -
    - -
    -
    - -

    ◆ USART_CR3_NACK_Msk

    - -
    -
    - - - - -
    #define USART_CR3_NACK_Msk   (0x1UL << USART_CR3_NACK_Pos)
    -
    -

    0x00000010

    - -
    -
    - -

    ◆ USART_CR3_NACK

    - -
    -
    - - - - -
    #define USART_CR3_NACK   USART_CR3_NACK_Msk
    -
    -

    Smartcard NACK enable
    -

    - -
    -
    - -

    ◆ USART_CR3_SCEN_Pos

    - -
    -
    - - - - -
    #define USART_CR3_SCEN_Pos   (5U)
    -
    - -
    -
    - -

    ◆ USART_CR3_SCEN_Msk

    - -
    -
    - - - - -
    #define USART_CR3_SCEN_Msk   (0x1UL << USART_CR3_SCEN_Pos)
    -
    -

    0x00000020

    - -
    -
    - -

    ◆ USART_CR3_SCEN

    - -
    -
    - - - - -
    #define USART_CR3_SCEN   USART_CR3_SCEN_Msk
    -
    -

    Smartcard mode enable
    -

    - -
    -
    - -

    ◆ USART_CR3_DMAR_Pos

    - -
    -
    - - - - -
    #define USART_CR3_DMAR_Pos   (6U)
    -
    - -
    -
    - -

    ◆ USART_CR3_DMAR_Msk

    - -
    -
    - - - - -
    #define USART_CR3_DMAR_Msk   (0x1UL << USART_CR3_DMAR_Pos)
    -
    -

    0x00000040

    - -
    -
    - -

    ◆ USART_CR3_DMAR

    - -
    -
    - - - - -
    #define USART_CR3_DMAR   USART_CR3_DMAR_Msk
    -
    -

    DMA Enable Receiver
    -

    - -
    -
    - -

    ◆ USART_CR3_DMAT_Pos

    - -
    -
    - - - - -
    #define USART_CR3_DMAT_Pos   (7U)
    -
    - -
    -
    - -

    ◆ USART_CR3_DMAT_Msk

    - -
    -
    - - - - -
    #define USART_CR3_DMAT_Msk   (0x1UL << USART_CR3_DMAT_Pos)
    -
    -

    0x00000080

    - -
    -
    - -

    ◆ USART_CR3_DMAT

    - -
    -
    - - - - -
    #define USART_CR3_DMAT   USART_CR3_DMAT_Msk
    -
    -

    DMA Enable Transmitter
    -

    - -
    -
    - -

    ◆ USART_CR3_RTSE_Pos

    - -
    -
    - - - - -
    #define USART_CR3_RTSE_Pos   (8U)
    -
    - -
    -
    - -

    ◆ USART_CR3_RTSE_Msk

    - -
    -
    - - - - -
    #define USART_CR3_RTSE_Msk   (0x1UL << USART_CR3_RTSE_Pos)
    -
    -

    0x00000100

    - -
    -
    - -

    ◆ USART_CR3_RTSE

    - -
    -
    - - - - -
    #define USART_CR3_RTSE   USART_CR3_RTSE_Msk
    -
    -

    RTS Enable
    -

    - -
    -
    - -

    ◆ USART_CR3_CTSE_Pos

    - -
    -
    - - - - -
    #define USART_CR3_CTSE_Pos   (9U)
    -
    - -
    -
    - -

    ◆ USART_CR3_CTSE_Msk

    - -
    -
    - - - - -
    #define USART_CR3_CTSE_Msk   (0x1UL << USART_CR3_CTSE_Pos)
    -
    -

    0x00000200

    - -
    -
    - -

    ◆ USART_CR3_CTSE

    - -
    -
    - - - - -
    #define USART_CR3_CTSE   USART_CR3_CTSE_Msk
    -
    -

    CTS Enable
    -

    - -
    -
    - -

    ◆ USART_CR3_CTSIE_Pos

    - -
    -
    - - - - -
    #define USART_CR3_CTSIE_Pos   (10U)
    -
    - -
    -
    - -

    ◆ USART_CR3_CTSIE_Msk

    - -
    -
    - - - - -
    #define USART_CR3_CTSIE_Msk   (0x1UL << USART_CR3_CTSIE_Pos)
    -
    -

    0x00000400

    - -
    -
    - -

    ◆ USART_CR3_CTSIE

    - -
    -
    - - - - -
    #define USART_CR3_CTSIE   USART_CR3_CTSIE_Msk
    -
    -

    CTS Interrupt Enable
    -

    - -
    -
    - -

    ◆ USART_CR3_ONEBIT_Pos

    - -
    -
    - - - - -
    #define USART_CR3_ONEBIT_Pos   (11U)
    -
    - -
    -
    - -

    ◆ USART_CR3_ONEBIT_Msk

    - -
    -
    - - - - -
    #define USART_CR3_ONEBIT_Msk   (0x1UL << USART_CR3_ONEBIT_Pos)
    -
    -

    0x00000800

    - -
    -
    - -

    ◆ USART_CR3_ONEBIT

    - -
    -
    - - - - -
    #define USART_CR3_ONEBIT   USART_CR3_ONEBIT_Msk
    -
    -

    USART One bit method enable

    - -
    -
    - -

    ◆ USART_GTPR_PSC_Pos

    - -
    -
    - - - - -
    #define USART_GTPR_PSC_Pos   (0U)
    -
    - -
    -
    - -

    ◆ USART_GTPR_PSC_Msk

    - -
    -
    - - - - -
    #define USART_GTPR_PSC_Msk   (0xFFUL << USART_GTPR_PSC_Pos)
    -
    -

    0x000000FF

    - -
    -
    - -

    ◆ USART_GTPR_PSC

    - -
    -
    - - - - -
    #define USART_GTPR_PSC   USART_GTPR_PSC_Msk
    -
    -

    PSC[7:0] bits (Prescaler value)

    - -
    -
    - -

    ◆ USART_GTPR_PSC_0

    - -
    -
    - - - - -
    #define USART_GTPR_PSC_0   (0x01UL << USART_GTPR_PSC_Pos)
    -
    -

    0x0001

    - -
    -
    - -

    ◆ USART_GTPR_PSC_1

    - -
    -
    - - - - -
    #define USART_GTPR_PSC_1   (0x02UL << USART_GTPR_PSC_Pos)
    -
    -

    0x0002

    - -
    -
    - -

    ◆ USART_GTPR_PSC_2

    - -
    -
    - - - - -
    #define USART_GTPR_PSC_2   (0x04UL << USART_GTPR_PSC_Pos)
    -
    -

    0x0004

    - -
    -
    - -

    ◆ USART_GTPR_PSC_3

    - -
    -
    - - - - -
    #define USART_GTPR_PSC_3   (0x08UL << USART_GTPR_PSC_Pos)
    -
    -

    0x0008

    - -
    -
    - -

    ◆ USART_GTPR_PSC_4

    - -
    -
    - - - - -
    #define USART_GTPR_PSC_4   (0x10UL << USART_GTPR_PSC_Pos)
    -
    -

    0x0010

    - -
    -
    - -

    ◆ USART_GTPR_PSC_5

    - -
    -
    - - - - -
    #define USART_GTPR_PSC_5   (0x20UL << USART_GTPR_PSC_Pos)
    -
    -

    0x0020

    - -
    -
    - -

    ◆ USART_GTPR_PSC_6

    - -
    -
    - - - - -
    #define USART_GTPR_PSC_6   (0x40UL << USART_GTPR_PSC_Pos)
    -
    -

    0x0040

    - -
    -
    - -

    ◆ USART_GTPR_PSC_7

    - -
    -
    - - - - -
    #define USART_GTPR_PSC_7   (0x80UL << USART_GTPR_PSC_Pos)
    -
    -

    0x0080

    - -
    -
    - -

    ◆ USART_GTPR_GT_Pos

    - -
    -
    - - - - -
    #define USART_GTPR_GT_Pos   (8U)
    -
    - -
    -
    - -

    ◆ USART_GTPR_GT_Msk

    - -
    -
    - - - - -
    #define USART_GTPR_GT_Msk   (0xFFUL << USART_GTPR_GT_Pos)
    -
    -

    0x0000FF00

    - -
    -
    - -

    ◆ USART_GTPR_GT

    - -
    -
    - - - - -
    #define USART_GTPR_GT   USART_GTPR_GT_Msk
    -
    -

    Guard time value

    - -
    -
    - -

    ◆ WWDG_CR_T_Pos

    - -
    -
    - - - - -
    #define WWDG_CR_T_Pos   (0U)
    -
    - -
    -
    - -

    ◆ WWDG_CR_T_Msk

    - -
    -
    - - - - -
    #define WWDG_CR_T_Msk   (0x7FUL << WWDG_CR_T_Pos)
    -
    -

    0x0000007F

    - -
    -
    - -

    ◆ WWDG_CR_T

    - -
    -
    - - - - -
    #define WWDG_CR_T   WWDG_CR_T_Msk
    -
    -

    T[6:0] bits (7-Bit counter (MSB to LSB))

    - -
    -
    - -

    ◆ WWDG_CR_T_0

    - -
    -
    - - - - -
    #define WWDG_CR_T_0   (0x01UL << WWDG_CR_T_Pos)
    -
    -

    0x01

    - -
    -
    - -

    ◆ WWDG_CR_T_1

    - -
    -
    - - - - -
    #define WWDG_CR_T_1   (0x02UL << WWDG_CR_T_Pos)
    -
    -

    0x02

    - -
    -
    - -

    ◆ WWDG_CR_T_2

    - -
    -
    - - - - -
    #define WWDG_CR_T_2   (0x04UL << WWDG_CR_T_Pos)
    -
    -

    0x04

    - -
    -
    - -

    ◆ WWDG_CR_T_3

    - -
    -
    - - - - -
    #define WWDG_CR_T_3   (0x08UL << WWDG_CR_T_Pos)
    -
    -

    0x08

    - -
    -
    - -

    ◆ WWDG_CR_T_4

    - -
    -
    - - - - -
    #define WWDG_CR_T_4   (0x10UL << WWDG_CR_T_Pos)
    -
    -

    0x10

    - -
    -
    - -

    ◆ WWDG_CR_T_5

    - -
    -
    - - - - -
    #define WWDG_CR_T_5   (0x20UL << WWDG_CR_T_Pos)
    -
    -

    0x20

    - -
    -
    - -

    ◆ WWDG_CR_T_6

    - -
    -
    - - - - -
    #define WWDG_CR_T_6   (0x40UL << WWDG_CR_T_Pos)
    -
    -

    0x40

    - -
    -
    - -

    ◆ WWDG_CR_T0

    - -
    -
    - - - - -
    #define WWDG_CR_T0   WWDG_CR_T_0
    -
    - -
    -
    - -

    ◆ WWDG_CR_T1

    - -
    -
    - - - - -
    #define WWDG_CR_T1   WWDG_CR_T_1
    -
    - -
    -
    - -

    ◆ WWDG_CR_T2

    - -
    -
    - - - - -
    #define WWDG_CR_T2   WWDG_CR_T_2
    -
    - -
    -
    - -

    ◆ WWDG_CR_T3

    - -
    -
    - - - - -
    #define WWDG_CR_T3   WWDG_CR_T_3
    -
    - -
    -
    - -

    ◆ WWDG_CR_T4

    - -
    -
    - - - - -
    #define WWDG_CR_T4   WWDG_CR_T_4
    -
    - -
    -
    - -

    ◆ WWDG_CR_T5

    - -
    -
    - - - - -
    #define WWDG_CR_T5   WWDG_CR_T_5
    -
    - -
    -
    - -

    ◆ WWDG_CR_T6

    - -
    -
    - - - - -
    #define WWDG_CR_T6   WWDG_CR_T_6
    -
    - -
    -
    - -

    ◆ WWDG_CR_WDGA_Pos

    - -
    -
    - - - - -
    #define WWDG_CR_WDGA_Pos   (7U)
    -
    - -
    -
    - -

    ◆ WWDG_CR_WDGA_Msk

    - -
    -
    - - - - -
    #define WWDG_CR_WDGA_Msk   (0x1UL << WWDG_CR_WDGA_Pos)
    -
    -

    0x00000080

    - -
    -
    - -

    ◆ WWDG_CR_WDGA

    - -
    -
    - - - - -
    #define WWDG_CR_WDGA   WWDG_CR_WDGA_Msk
    -
    -

    Activation bit

    - -
    -
    - -

    ◆ WWDG_CFR_W_Pos

    - -
    -
    - - - - -
    #define WWDG_CFR_W_Pos   (0U)
    -
    - -
    -
    - -

    ◆ WWDG_CFR_W_Msk

    - -
    -
    - - - - -
    #define WWDG_CFR_W_Msk   (0x7FUL << WWDG_CFR_W_Pos)
    -
    -

    0x0000007F

    - -
    -
    - -

    ◆ WWDG_CFR_W

    - -
    -
    - - - - -
    #define WWDG_CFR_W   WWDG_CFR_W_Msk
    -
    -

    W[6:0] bits (7-bit window value)

    - -
    -
    - -

    ◆ WWDG_CFR_W_0

    - -
    -
    - - - - -
    #define WWDG_CFR_W_0   (0x01UL << WWDG_CFR_W_Pos)
    -
    -

    0x0001

    - -
    -
    - -

    ◆ WWDG_CFR_W_1

    - -
    -
    - - - - -
    #define WWDG_CFR_W_1   (0x02UL << WWDG_CFR_W_Pos)
    -
    -

    0x0002

    - -
    -
    - -

    ◆ WWDG_CFR_W_2

    - -
    -
    - - - - -
    #define WWDG_CFR_W_2   (0x04UL << WWDG_CFR_W_Pos)
    -
    -

    0x0004

    - -
    -
    - -

    ◆ WWDG_CFR_W_3

    - -
    -
    - - - - -
    #define WWDG_CFR_W_3   (0x08UL << WWDG_CFR_W_Pos)
    -
    -

    0x0008

    - -
    -
    - -

    ◆ WWDG_CFR_W_4

    - -
    -
    - - - - -
    #define WWDG_CFR_W_4   (0x10UL << WWDG_CFR_W_Pos)
    -
    -

    0x0010

    - -
    -
    - -

    ◆ WWDG_CFR_W_5

    - -
    -
    - - - - -
    #define WWDG_CFR_W_5   (0x20UL << WWDG_CFR_W_Pos)
    -
    -

    0x0020

    - -
    -
    - -

    ◆ WWDG_CFR_W_6

    - -
    -
    - - - - -
    #define WWDG_CFR_W_6   (0x40UL << WWDG_CFR_W_Pos)
    -
    -

    0x0040

    - -
    -
    - -

    ◆ WWDG_CFR_W0

    - -
    -
    - - - - -
    #define WWDG_CFR_W0   WWDG_CFR_W_0
    -
    - -
    -
    - -

    ◆ WWDG_CFR_W1

    - -
    -
    - - - - -
    #define WWDG_CFR_W1   WWDG_CFR_W_1
    -
    - -
    -
    - -

    ◆ WWDG_CFR_W2

    - -
    -
    - - - - -
    #define WWDG_CFR_W2   WWDG_CFR_W_2
    -
    - -
    -
    - -

    ◆ WWDG_CFR_W3

    - -
    -
    - - - - -
    #define WWDG_CFR_W3   WWDG_CFR_W_3
    -
    - -
    -
    - -

    ◆ WWDG_CFR_W4

    - -
    -
    - - - - -
    #define WWDG_CFR_W4   WWDG_CFR_W_4
    -
    - -
    -
    - -

    ◆ WWDG_CFR_W5

    - -
    -
    - - - - -
    #define WWDG_CFR_W5   WWDG_CFR_W_5
    -
    - -
    -
    - -

    ◆ WWDG_CFR_W6

    - -
    -
    - - - - -
    #define WWDG_CFR_W6   WWDG_CFR_W_6
    -
    - -
    -
    - -

    ◆ WWDG_CFR_WDGTB_Pos

    - -
    -
    - - - - -
    #define WWDG_CFR_WDGTB_Pos   (7U)
    -
    - -
    -
    - -

    ◆ WWDG_CFR_WDGTB_Msk

    - -
    -
    - - - - -
    #define WWDG_CFR_WDGTB_Msk   (0x3UL << WWDG_CFR_WDGTB_Pos)
    -
    -

    0x00000180

    - -
    -
    - -

    ◆ WWDG_CFR_WDGTB

    - -
    -
    - - - - -
    #define WWDG_CFR_WDGTB   WWDG_CFR_WDGTB_Msk
    -
    -

    WDGTB[1:0] bits (Timer Base)

    - -
    -
    - -

    ◆ WWDG_CFR_WDGTB_0

    - -
    -
    - - - - -
    #define WWDG_CFR_WDGTB_0   (0x1UL << WWDG_CFR_WDGTB_Pos)
    -
    -

    0x0080

    - -
    -
    - -

    ◆ WWDG_CFR_WDGTB_1

    - -
    -
    - - - - -
    #define WWDG_CFR_WDGTB_1   (0x2UL << WWDG_CFR_WDGTB_Pos)
    -
    -

    0x0100

    - -
    -
    - -

    ◆ WWDG_CFR_WDGTB0

    - -
    -
    - - - - -
    #define WWDG_CFR_WDGTB0   WWDG_CFR_WDGTB_0
    -
    - -
    -
    - -

    ◆ WWDG_CFR_WDGTB1

    - -
    -
    - - - - -
    #define WWDG_CFR_WDGTB1   WWDG_CFR_WDGTB_1
    -
    - -
    -
    - -

    ◆ WWDG_CFR_EWI_Pos

    - -
    -
    - - - - -
    #define WWDG_CFR_EWI_Pos   (9U)
    -
    - -
    -
    - -

    ◆ WWDG_CFR_EWI_Msk

    - -
    -
    - - - - -
    #define WWDG_CFR_EWI_Msk   (0x1UL << WWDG_CFR_EWI_Pos)
    -
    -

    0x00000200

    - -
    -
    - -

    ◆ WWDG_CFR_EWI

    - -
    -
    - - - - -
    #define WWDG_CFR_EWI   WWDG_CFR_EWI_Msk
    -
    -

    Early Wakeup Interrupt

    - -
    -
    - -

    ◆ WWDG_SR_EWIF_Pos

    - -
    -
    - - - - -
    #define WWDG_SR_EWIF_Pos   (0U)
    -
    - -
    -
    - -

    ◆ WWDG_SR_EWIF_Msk

    - -
    -
    - - - - -
    #define WWDG_SR_EWIF_Msk   (0x1UL << WWDG_SR_EWIF_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ WWDG_SR_EWIF

    - -
    -
    - - - - -
    #define WWDG_SR_EWIF   WWDG_SR_EWIF_Msk
    -
    -

    Early Wakeup Interrupt Flag

    - -
    -
    - -

    ◆ DBGMCU_IDCODE_DEV_ID_Pos

    - -
    -
    - - - - -
    #define DBGMCU_IDCODE_DEV_ID_Pos   (0U)
    -
    - -
    -
    - -

    ◆ DBGMCU_IDCODE_DEV_ID_Msk

    - -
    -
    - - - - -
    #define DBGMCU_IDCODE_DEV_ID_Msk   (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos)
    -
    -

    0x00000FFF

    - -
    -
    - -

    ◆ DBGMCU_IDCODE_DEV_ID

    - -
    -
    - - - - -
    #define DBGMCU_IDCODE_DEV_ID   DBGMCU_IDCODE_DEV_ID_Msk
    -
    - -
    -
    - -

    ◆ DBGMCU_IDCODE_REV_ID_Pos

    - -
    -
    - - - - -
    #define DBGMCU_IDCODE_REV_ID_Pos   (16U)
    -
    - -
    -
    - -

    ◆ DBGMCU_IDCODE_REV_ID_Msk

    - -
    -
    - - - - -
    #define DBGMCU_IDCODE_REV_ID_Msk   (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos)
    -
    -

    0xFFFF0000

    - -
    -
    - -

    ◆ DBGMCU_IDCODE_REV_ID

    - -
    -
    - - - - -
    #define DBGMCU_IDCODE_REV_ID   DBGMCU_IDCODE_REV_ID_Msk
    -
    - -
    -
    - -

    ◆ DBGMCU_CR_DBG_SLEEP_Pos

    - -
    -
    - - - - -
    #define DBGMCU_CR_DBG_SLEEP_Pos   (0U)
    -
    - -
    -
    - -

    ◆ DBGMCU_CR_DBG_SLEEP_Msk

    - -
    -
    - - - - -
    #define DBGMCU_CR_DBG_SLEEP_Msk   (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ DBGMCU_CR_DBG_SLEEP

    - -
    -
    - - - - -
    #define DBGMCU_CR_DBG_SLEEP   DBGMCU_CR_DBG_SLEEP_Msk
    -
    - -
    -
    - -

    ◆ DBGMCU_CR_DBG_STOP_Pos

    - -
    -
    - - - - -
    #define DBGMCU_CR_DBG_STOP_Pos   (1U)
    -
    - -
    -
    - -

    ◆ DBGMCU_CR_DBG_STOP_Msk

    - -
    -
    - - - - -
    #define DBGMCU_CR_DBG_STOP_Msk   (0x1UL << DBGMCU_CR_DBG_STOP_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ DBGMCU_CR_DBG_STOP

    - -
    -
    - - - - -
    #define DBGMCU_CR_DBG_STOP   DBGMCU_CR_DBG_STOP_Msk
    -
    - -
    -
    - -

    ◆ DBGMCU_CR_DBG_STANDBY_Pos

    - -
    -
    - - - - -
    #define DBGMCU_CR_DBG_STANDBY_Pos   (2U)
    -
    - -
    -
    - -

    ◆ DBGMCU_CR_DBG_STANDBY_Msk

    - -
    -
    - - - - -
    #define DBGMCU_CR_DBG_STANDBY_Msk   (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos)
    -
    -

    0x00000004

    - -
    -
    - -

    ◆ DBGMCU_CR_DBG_STANDBY

    - -
    -
    - - - - -
    #define DBGMCU_CR_DBG_STANDBY   DBGMCU_CR_DBG_STANDBY_Msk
    -
    - -
    -
    - -

    ◆ DBGMCU_CR_TRACE_IOEN_Pos

    - -
    -
    - - - - -
    #define DBGMCU_CR_TRACE_IOEN_Pos   (5U)
    -
    - -
    -
    - -

    ◆ DBGMCU_CR_TRACE_IOEN_Msk

    - -
    -
    - - - - -
    #define DBGMCU_CR_TRACE_IOEN_Msk   (0x1UL << DBGMCU_CR_TRACE_IOEN_Pos)
    -
    -

    0x00000020

    - -
    -
    - -

    ◆ DBGMCU_CR_TRACE_IOEN

    - -
    -
    - - - - -
    #define DBGMCU_CR_TRACE_IOEN   DBGMCU_CR_TRACE_IOEN_Msk
    -
    - -
    -
    - -

    ◆ DBGMCU_CR_TRACE_MODE_Pos

    - -
    -
    - - - - -
    #define DBGMCU_CR_TRACE_MODE_Pos   (6U)
    -
    - -
    -
    - -

    ◆ DBGMCU_CR_TRACE_MODE_Msk

    - -
    -
    - - - - -
    #define DBGMCU_CR_TRACE_MODE_Msk   (0x3UL << DBGMCU_CR_TRACE_MODE_Pos)
    -
    -

    0x000000C0

    - -
    -
    - -

    ◆ DBGMCU_CR_TRACE_MODE

    - -
    -
    - - - - -
    #define DBGMCU_CR_TRACE_MODE   DBGMCU_CR_TRACE_MODE_Msk
    -
    - -
    -
    - -

    ◆ DBGMCU_CR_TRACE_MODE_0

    - -
    -
    - - - - -
    #define DBGMCU_CR_TRACE_MODE_0   (0x1UL << DBGMCU_CR_TRACE_MODE_Pos)
    -
    -

    0x00000040

    - -
    -
    - -

    ◆ DBGMCU_CR_TRACE_MODE_1

    - -
    -
    - - - - -
    #define DBGMCU_CR_TRACE_MODE_1   (0x2UL << DBGMCU_CR_TRACE_MODE_Pos)
    -
    -

    0x00000080

    - -
    -
    - -

    ◆ DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos

    - -
    -
    - - - - -
    #define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos   (0U)
    -
    - -
    -
    - -

    ◆ DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk

    - -
    -
    - - - - -
    #define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk   (0x1UL << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ DBGMCU_APB1_FZ_DBG_TIM2_STOP

    - -
    -
    - - - - -
    #define DBGMCU_APB1_FZ_DBG_TIM2_STOP   DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk
    -
    - -
    -
    - -

    ◆ DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos

    - -
    -
    - - - - -
    #define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos   (1U)
    -
    - -
    -
    - -

    ◆ DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk

    - -
    -
    - - - - -
    #define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk   (0x1UL << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ DBGMCU_APB1_FZ_DBG_TIM3_STOP

    - -
    -
    - - - - -
    #define DBGMCU_APB1_FZ_DBG_TIM3_STOP   DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk
    -
    - -
    -
    - -

    ◆ DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos

    - -
    -
    - - - - -
    #define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos   (2U)
    -
    - -
    -
    - -

    ◆ DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk

    - -
    -
    - - - - -
    #define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk   (0x1UL << DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos)
    -
    -

    0x00000004

    - -
    -
    - -

    ◆ DBGMCU_APB1_FZ_DBG_TIM4_STOP

    - -
    -
    - - - - -
    #define DBGMCU_APB1_FZ_DBG_TIM4_STOP   DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk
    -
    - -
    -
    - -

    ◆ DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos

    - -
    -
    - - - - -
    #define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos   (3U)
    -
    - -
    -
    - -

    ◆ DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk

    - -
    -
    - - - - -
    #define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk   (0x1UL << DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos)
    -
    -

    0x00000008

    - -
    -
    - -

    ◆ DBGMCU_APB1_FZ_DBG_TIM5_STOP

    - -
    -
    - - - - -
    #define DBGMCU_APB1_FZ_DBG_TIM5_STOP   DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk
    -
    - -
    -
    - -

    ◆ DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos

    - -
    -
    - - - - -
    #define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos   (4U)
    -
    - -
    -
    - -

    ◆ DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk

    - -
    -
    - - - - -
    #define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk   (0x1UL << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos)
    -
    -

    0x00000010

    - -
    -
    - -

    ◆ DBGMCU_APB1_FZ_DBG_TIM6_STOP

    - -
    -
    - - - - -
    #define DBGMCU_APB1_FZ_DBG_TIM6_STOP   DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk
    -
    - -
    -
    - -

    ◆ DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos

    - -
    -
    - - - - -
    #define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos   (5U)
    -
    - -
    -
    - -

    ◆ DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk

    - -
    -
    - - - - -
    #define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk   (0x1UL << DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos)
    -
    -

    0x00000020

    - -
    -
    - -

    ◆ DBGMCU_APB1_FZ_DBG_TIM7_STOP

    - -
    -
    - - - - -
    #define DBGMCU_APB1_FZ_DBG_TIM7_STOP   DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk
    -
    - -
    -
    - -

    ◆ DBGMCU_APB1_FZ_DBG_TIM12_STOP_Pos

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    #define DBGMCU_APB1_FZ_DBG_TIM12_STOP_Pos   (6U)
    -
    - -
    -
    - -

    ◆ DBGMCU_APB1_FZ_DBG_TIM12_STOP_Msk

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    #define DBGMCU_APB1_FZ_DBG_TIM12_STOP_Msk   (0x1UL << DBGMCU_APB1_FZ_DBG_TIM12_STOP_Pos)
    -
    -

    0x00000040

    - -
    -
    - -

    ◆ DBGMCU_APB1_FZ_DBG_TIM12_STOP

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    #define DBGMCU_APB1_FZ_DBG_TIM12_STOP   DBGMCU_APB1_FZ_DBG_TIM12_STOP_Msk
    -
    - -
    -
    - -

    ◆ DBGMCU_APB1_FZ_DBG_TIM13_STOP_Pos

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    #define DBGMCU_APB1_FZ_DBG_TIM13_STOP_Pos   (7U)
    -
    - -
    -
    - -

    ◆ DBGMCU_APB1_FZ_DBG_TIM13_STOP_Msk

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    #define DBGMCU_APB1_FZ_DBG_TIM13_STOP_Msk   (0x1UL << DBGMCU_APB1_FZ_DBG_TIM13_STOP_Pos)
    -
    -

    0x00000080

    - -
    -
    - -

    ◆ DBGMCU_APB1_FZ_DBG_TIM13_STOP

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    #define DBGMCU_APB1_FZ_DBG_TIM13_STOP   DBGMCU_APB1_FZ_DBG_TIM13_STOP_Msk
    -
    - -
    -
    - -

    ◆ DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos

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    #define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos   (8U)
    -
    - -
    -
    - -

    ◆ DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk

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    #define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk   (0x1UL << DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos)
    -
    -

    0x00000100

    - -
    -
    - -

    ◆ DBGMCU_APB1_FZ_DBG_TIM14_STOP

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    #define DBGMCU_APB1_FZ_DBG_TIM14_STOP   DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk
    -
    - -
    -
    - -

    ◆ DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos

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    #define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos   (10U)
    -
    - -
    -
    - -

    ◆ DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk

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    #define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk   (0x1UL << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos)
    -
    -

    0x00000400

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    -
    - -

    ◆ DBGMCU_APB1_FZ_DBG_RTC_STOP

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    #define DBGMCU_APB1_FZ_DBG_RTC_STOP   DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk
    -
    - -
    -
    - -

    ◆ DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos

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    #define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos   (11U)
    -
    - -
    -
    - -

    ◆ DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk

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    #define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk   (0x1UL << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos)
    -
    -

    0x00000800

    - -
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    - -

    ◆ DBGMCU_APB1_FZ_DBG_WWDG_STOP

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    #define DBGMCU_APB1_FZ_DBG_WWDG_STOP   DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk
    -
    - -
    -
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    ◆ DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos

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    #define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos   (12U)
    -
    - -
    -
    - -

    ◆ DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk

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    #define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk   (0x1UL << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos)
    -
    -

    0x00001000

    - -
    -
    - -

    ◆ DBGMCU_APB1_FZ_DBG_IWDG_STOP

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    #define DBGMCU_APB1_FZ_DBG_IWDG_STOP   DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk
    -
    - -
    -
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    ◆ DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos

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    #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos   (21U)
    -
    - -
    -
    - -

    ◆ DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk

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    #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk   (0x1UL << DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos)
    -
    -

    0x00200000

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    ◆ DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT

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    #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT   DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk
    -
    - -
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    ◆ DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos

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    #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos   (22U)
    -
    - -
    -
    - -

    ◆ DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk

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    #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk   (0x1UL << DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos)
    -
    -

    0x00400000

    - -
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    - -

    ◆ DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT

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    #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT   DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk
    -
    - -
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    ◆ DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos

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    #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos   (23U)
    -
    - -
    -
    - -

    ◆ DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk

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    #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk   (0x1UL << DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos)
    -
    -

    0x00800000

    - -
    -
    - -

    ◆ DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT

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    #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT   DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk
    -
    - -
    -
    - -

    ◆ DBGMCU_APB1_FZ_DBG_CAN1_STOP_Pos

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    #define DBGMCU_APB1_FZ_DBG_CAN1_STOP_Pos   (25U)
    -
    - -
    -
    - -

    ◆ DBGMCU_APB1_FZ_DBG_CAN1_STOP_Msk

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    #define DBGMCU_APB1_FZ_DBG_CAN1_STOP_Msk   (0x1UL << DBGMCU_APB1_FZ_DBG_CAN1_STOP_Pos)
    -
    -

    0x02000000

    - -
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    - -

    ◆ DBGMCU_APB1_FZ_DBG_CAN1_STOP

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    #define DBGMCU_APB1_FZ_DBG_CAN1_STOP   DBGMCU_APB1_FZ_DBG_CAN1_STOP_Msk
    -
    - -
    -
    - -

    ◆ DBGMCU_APB1_FZ_DBG_CAN2_STOP_Pos

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    #define DBGMCU_APB1_FZ_DBG_CAN2_STOP_Pos   (26U)
    -
    - -
    -
    - -

    ◆ DBGMCU_APB1_FZ_DBG_CAN2_STOP_Msk

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    #define DBGMCU_APB1_FZ_DBG_CAN2_STOP_Msk   (0x1UL << DBGMCU_APB1_FZ_DBG_CAN2_STOP_Pos)
    -
    -

    0x04000000

    - -
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    ◆ DBGMCU_APB1_FZ_DBG_CAN2_STOP

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    #define DBGMCU_APB1_FZ_DBG_CAN2_STOP   DBGMCU_APB1_FZ_DBG_CAN2_STOP_Msk
    -
    - -
    -
    - -

    ◆ DBGMCU_APB1_FZ_DBG_IWDEG_STOP

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    #define DBGMCU_APB1_FZ_DBG_IWDEG_STOP   DBGMCU_APB1_FZ_DBG_IWDG_STOP
    -
    - -
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    ◆ DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos

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    #define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos   (0U)
    -
    - -
    -
    - -

    ◆ DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk

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    #define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk   (0x1UL << DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos)
    -
    -

    0x00000001

    - -
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    ◆ DBGMCU_APB2_FZ_DBG_TIM1_STOP

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    #define DBGMCU_APB2_FZ_DBG_TIM1_STOP   DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk
    -
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    ◆ DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos

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    #define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos   (1U)
    -
    - -
    -
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    ◆ DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk

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    #define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk   (0x1UL << DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos)
    -
    -

    0x00000002

    - -
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    ◆ DBGMCU_APB2_FZ_DBG_TIM8_STOP

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    #define DBGMCU_APB2_FZ_DBG_TIM8_STOP   DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk
    -
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    ◆ DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos

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    #define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos   (16U)
    -
    - -
    -
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    ◆ DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk

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    #define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk   (0x1UL << DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos)
    -
    -

    0x00010000

    - -
    -
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    ◆ DBGMCU_APB2_FZ_DBG_TIM9_STOP

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    #define DBGMCU_APB2_FZ_DBG_TIM9_STOP   DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk
    -
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    -
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    ◆ DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos

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    #define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos   (17U)
    -
    - -
    -
    - -

    ◆ DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk

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    #define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk   (0x1UL << DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos)
    -
    -

    0x00020000

    - -
    -
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    ◆ DBGMCU_APB2_FZ_DBG_TIM10_STOP

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    #define DBGMCU_APB2_FZ_DBG_TIM10_STOP   DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk
    -
    - -
    -
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    ◆ DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos

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    #define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos   (18U)
    -
    - -
    -
    - -

    ◆ DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk

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    #define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk   (0x1UL << DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos)
    -
    -

    0x00040000

    - -
    -
    - -

    ◆ DBGMCU_APB2_FZ_DBG_TIM11_STOP

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    #define DBGMCU_APB2_FZ_DBG_TIM11_STOP   DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk
    -
    - -
    -
    - -

    ◆ ETH_MACCR_WD_Pos

    - -
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    #define ETH_MACCR_WD_Pos   (23U)
    -
    - -
    -
    - -

    ◆ ETH_MACCR_WD_Msk

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    #define ETH_MACCR_WD_Msk   (0x1UL << ETH_MACCR_WD_Pos)
    -
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    0x00800000

    - -
    -
    - -

    ◆ ETH_MACCR_WD

    - -
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    #define ETH_MACCR_WD   ETH_MACCR_WD_Msk /* Watchdog disable */
    -
    - -
    -
    - -

    ◆ ETH_MACCR_JD_Pos

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    #define ETH_MACCR_JD_Pos   (22U)
    -
    - -
    -
    - -

    ◆ ETH_MACCR_JD_Msk

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    #define ETH_MACCR_JD_Msk   (0x1UL << ETH_MACCR_JD_Pos)
    -
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    0x00400000

    - -
    -
    - -

    ◆ ETH_MACCR_JD

    - -
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    #define ETH_MACCR_JD   ETH_MACCR_JD_Msk /* Jabber disable */
    -
    - -
    -
    - -

    ◆ ETH_MACCR_IFG_Pos

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    #define ETH_MACCR_IFG_Pos   (17U)
    -
    - -
    -
    - -

    ◆ ETH_MACCR_IFG_Msk

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    #define ETH_MACCR_IFG_Msk   (0x7UL << ETH_MACCR_IFG_Pos)
    -
    -

    0x000E0000

    - -
    -
    - -

    ◆ ETH_MACCR_IFG

    - -
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    #define ETH_MACCR_IFG   ETH_MACCR_IFG_Msk /* Inter-frame gap */
    -
    - -
    -
    - -

    ◆ ETH_MACCR_IFG_96Bit

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    #define ETH_MACCR_IFG_96Bit   0x00000000U /* Minimum IFG between frames during transmission is 96Bit */
    -
    - -
    -
    - -

    ◆ ETH_MACCR_IFG_88Bit

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    #define ETH_MACCR_IFG_88Bit   0x00020000U /* Minimum IFG between frames during transmission is 88Bit */
    -
    - -
    -
    - -

    ◆ ETH_MACCR_IFG_80Bit

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    #define ETH_MACCR_IFG_80Bit   0x00040000U /* Minimum IFG between frames during transmission is 80Bit */
    -
    - -
    -
    - -

    ◆ ETH_MACCR_IFG_72Bit

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    #define ETH_MACCR_IFG_72Bit   0x00060000U /* Minimum IFG between frames during transmission is 72Bit */
    -
    - -
    -
    - -

    ◆ ETH_MACCR_IFG_64Bit

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    #define ETH_MACCR_IFG_64Bit   0x00080000U /* Minimum IFG between frames during transmission is 64Bit */
    -
    - -
    -
    - -

    ◆ ETH_MACCR_IFG_56Bit

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    #define ETH_MACCR_IFG_56Bit   0x000A0000U /* Minimum IFG between frames during transmission is 56Bit */
    -
    - -
    -
    - -

    ◆ ETH_MACCR_IFG_48Bit

    - -
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    #define ETH_MACCR_IFG_48Bit   0x000C0000U /* Minimum IFG between frames during transmission is 48Bit */
    -
    - -
    -
    - -

    ◆ ETH_MACCR_IFG_40Bit

    - -
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    #define ETH_MACCR_IFG_40Bit   0x000E0000U /* Minimum IFG between frames during transmission is 40Bit */
    -
    - -
    -
    - -

    ◆ ETH_MACCR_CSD_Pos

    - -
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    #define ETH_MACCR_CSD_Pos   (16U)
    -
    - -
    -
    - -

    ◆ ETH_MACCR_CSD_Msk

    - -
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    #define ETH_MACCR_CSD_Msk   (0x1UL << ETH_MACCR_CSD_Pos)
    -
    -

    0x00010000

    - -
    -
    - -

    ◆ ETH_MACCR_CSD

    - -
    -
    - - - - -
    #define ETH_MACCR_CSD   ETH_MACCR_CSD_Msk /* Carrier sense disable (during transmission) */
    -
    - -
    -
    - -

    ◆ ETH_MACCR_FES_Pos

    - -
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    #define ETH_MACCR_FES_Pos   (14U)
    -
    - -
    -
    - -

    ◆ ETH_MACCR_FES_Msk

    - -
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    #define ETH_MACCR_FES_Msk   (0x1UL << ETH_MACCR_FES_Pos)
    -
    -

    0x00004000

    - -
    -
    - -

    ◆ ETH_MACCR_FES

    - -
    -
    - - - - -
    #define ETH_MACCR_FES   ETH_MACCR_FES_Msk /* Fast ethernet speed */
    -
    - -
    -
    - -

    ◆ ETH_MACCR_ROD_Pos

    - -
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    #define ETH_MACCR_ROD_Pos   (13U)
    -
    - -
    -
    - -

    ◆ ETH_MACCR_ROD_Msk

    - -
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    #define ETH_MACCR_ROD_Msk   (0x1UL << ETH_MACCR_ROD_Pos)
    -
    -

    0x00002000

    - -
    -
    - -

    ◆ ETH_MACCR_ROD

    - -
    -
    - - - - -
    #define ETH_MACCR_ROD   ETH_MACCR_ROD_Msk /* Receive own disable */
    -
    - -
    -
    - -

    ◆ ETH_MACCR_LM_Pos

    - -
    -
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    #define ETH_MACCR_LM_Pos   (12U)
    -
    - -
    -
    - -

    ◆ ETH_MACCR_LM_Msk

    - -
    -
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    #define ETH_MACCR_LM_Msk   (0x1UL << ETH_MACCR_LM_Pos)
    -
    -

    0x00001000

    - -
    -
    - -

    ◆ ETH_MACCR_LM

    - -
    -
    - - - - -
    #define ETH_MACCR_LM   ETH_MACCR_LM_Msk /* loopback mode */
    -
    - -
    -
    - -

    ◆ ETH_MACCR_DM_Pos

    - -
    -
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    #define ETH_MACCR_DM_Pos   (11U)
    -
    - -
    -
    - -

    ◆ ETH_MACCR_DM_Msk

    - -
    -
    - - - - -
    #define ETH_MACCR_DM_Msk   (0x1UL << ETH_MACCR_DM_Pos)
    -
    -

    0x00000800

    - -
    -
    - -

    ◆ ETH_MACCR_DM

    - -
    -
    - - - - -
    #define ETH_MACCR_DM   ETH_MACCR_DM_Msk /* Duplex mode */
    -
    - -
    -
    - -

    ◆ ETH_MACCR_IPCO_Pos

    - -
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    #define ETH_MACCR_IPCO_Pos   (10U)
    -
    - -
    -
    - -

    ◆ ETH_MACCR_IPCO_Msk

    - -
    -
    - - - - -
    #define ETH_MACCR_IPCO_Msk   (0x1UL << ETH_MACCR_IPCO_Pos)
    -
    -

    0x00000400

    - -
    -
    - -

    ◆ ETH_MACCR_IPCO

    - -
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    #define ETH_MACCR_IPCO   ETH_MACCR_IPCO_Msk /* IP Checksum offload */
    -
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    ◆ ETH_MACCR_RD_Pos

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    #define ETH_MACCR_RD_Pos   (9U)
    -
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    ◆ ETH_MACCR_RD_Msk

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    #define ETH_MACCR_RD_Msk   (0x1UL << ETH_MACCR_RD_Pos)
    -
    -

    0x00000200

    - -
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    - -

    ◆ ETH_MACCR_RD

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    #define ETH_MACCR_RD   ETH_MACCR_RD_Msk /* Retry disable */
    -
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    ◆ ETH_MACCR_APCS_Pos

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    #define ETH_MACCR_APCS_Pos   (7U)
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    ◆ ETH_MACCR_APCS_Msk

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    #define ETH_MACCR_APCS_Msk   (0x1UL << ETH_MACCR_APCS_Pos)
    -
    -

    0x00000080

    - -
    -
    - -

    ◆ ETH_MACCR_APCS

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    #define ETH_MACCR_APCS   ETH_MACCR_APCS_Msk /* Automatic Pad/CRC stripping */
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    ◆ ETH_MACCR_BL_Pos

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    #define ETH_MACCR_BL_Pos   (5U)
    -
    - -
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    ◆ ETH_MACCR_BL_Msk

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    #define ETH_MACCR_BL_Msk   (0x3UL << ETH_MACCR_BL_Pos)
    -
    -

    0x00000060

    - -
    -
    - -

    ◆ ETH_MACCR_BL

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    #define ETH_MACCR_BL
    -
    -Value:
    ETH_MACCR_BL_Msk /* Back-off limit: random integer number (r) of slot time delays before rescheduling
    -
    a transmission attempt during retries after a collision: 0 =< r <2^k */
    -
    ETH_MACCR_BL_Msk
    #define ETH_MACCR_BL_Msk
    Definition stm32f407xx_matlab.h:12941
    -
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    ◆ ETH_MACCR_BL_10

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    #define ETH_MACCR_BL_10   0x00000000U /* k = min (n, 10) */
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    ◆ ETH_MACCR_BL_8

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    #define ETH_MACCR_BL_8   0x00000020U /* k = min (n, 8) */
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    ◆ ETH_MACCR_BL_4

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    #define ETH_MACCR_BL_4   0x00000040U /* k = min (n, 4) */
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    ◆ ETH_MACCR_BL_1

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    #define ETH_MACCR_BL_1   0x00000060U /* k = min (n, 1) */
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    - -
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    ◆ ETH_MACCR_DC_Pos

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    #define ETH_MACCR_DC_Pos   (4U)
    -
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    ◆ ETH_MACCR_DC_Msk

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    #define ETH_MACCR_DC_Msk   (0x1UL << ETH_MACCR_DC_Pos)
    -
    -

    0x00000010

    - -
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    - -

    ◆ ETH_MACCR_DC

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    #define ETH_MACCR_DC   ETH_MACCR_DC_Msk /* Defferal check */
    -
    - -
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    ◆ ETH_MACCR_TE_Pos

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    #define ETH_MACCR_TE_Pos   (3U)
    -
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    ◆ ETH_MACCR_TE_Msk

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    #define ETH_MACCR_TE_Msk   (0x1UL << ETH_MACCR_TE_Pos)
    -
    -

    0x00000008

    - -
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    - -

    ◆ ETH_MACCR_TE

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    #define ETH_MACCR_TE   ETH_MACCR_TE_Msk /* Transmitter enable */
    -
    - -
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    ◆ ETH_MACCR_RE_Pos

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    #define ETH_MACCR_RE_Pos   (2U)
    -
    - -
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    ◆ ETH_MACCR_RE_Msk

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    #define ETH_MACCR_RE_Msk   (0x1UL << ETH_MACCR_RE_Pos)
    -
    -

    0x00000004

    - -
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    - -

    ◆ ETH_MACCR_RE

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    #define ETH_MACCR_RE   ETH_MACCR_RE_Msk /* Receiver enable */
    -
    - -
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    ◆ ETH_MACFFR_RA_Pos

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    #define ETH_MACFFR_RA_Pos   (31U)
    -
    - -
    -
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    ◆ ETH_MACFFR_RA_Msk

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    #define ETH_MACFFR_RA_Msk   (0x1UL << ETH_MACFFR_RA_Pos)
    -
    -

    0x80000000

    - -
    -
    - -

    ◆ ETH_MACFFR_RA

    - -
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    #define ETH_MACFFR_RA   ETH_MACFFR_RA_Msk /* Receive all */
    -
    - -
    -
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    ◆ ETH_MACFFR_HPF_Pos

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    #define ETH_MACFFR_HPF_Pos   (10U)
    -
    - -
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    - -

    ◆ ETH_MACFFR_HPF_Msk

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    #define ETH_MACFFR_HPF_Msk   (0x1UL << ETH_MACFFR_HPF_Pos)
    -
    -

    0x00000400

    - -
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    ◆ ETH_MACFFR_HPF

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    #define ETH_MACFFR_HPF   ETH_MACFFR_HPF_Msk /* Hash or perfect filter */
    -
    - -
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    ◆ ETH_MACFFR_SAF_Pos

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    #define ETH_MACFFR_SAF_Pos   (9U)
    -
    - -
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    - -

    ◆ ETH_MACFFR_SAF_Msk

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    #define ETH_MACFFR_SAF_Msk   (0x1UL << ETH_MACFFR_SAF_Pos)
    -
    -

    0x00000200

    - -
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    - -

    ◆ ETH_MACFFR_SAF

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    #define ETH_MACFFR_SAF   ETH_MACFFR_SAF_Msk /* Source address filter enable */
    -
    - -
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    ◆ ETH_MACFFR_SAIF_Pos

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    #define ETH_MACFFR_SAIF_Pos   (8U)
    -
    - -
    -
    - -

    ◆ ETH_MACFFR_SAIF_Msk

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    #define ETH_MACFFR_SAIF_Msk   (0x1UL << ETH_MACFFR_SAIF_Pos)
    -
    -

    0x00000100

    - -
    -
    - -

    ◆ ETH_MACFFR_SAIF

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    #define ETH_MACFFR_SAIF   ETH_MACFFR_SAIF_Msk /* SA inverse filtering */
    -
    - -
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    ◆ ETH_MACFFR_PCF_Pos

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    #define ETH_MACFFR_PCF_Pos   (6U)
    -
    - -
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    - -

    ◆ ETH_MACFFR_PCF_Msk

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    #define ETH_MACFFR_PCF_Msk   (0x3UL << ETH_MACFFR_PCF_Pos)
    -
    -

    0x000000C0

    - -
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    - -

    ◆ ETH_MACFFR_PCF

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    #define ETH_MACFFR_PCF   ETH_MACFFR_PCF_Msk /* Pass control frames: 3 cases */
    -
    - -
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    - -

    ◆ ETH_MACFFR_PCF_BlockAll_Pos

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    #define ETH_MACFFR_PCF_BlockAll_Pos   (6U)
    -
    - -
    -
    - -

    ◆ ETH_MACFFR_PCF_BlockAll_Msk

    - -
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    #define ETH_MACFFR_PCF_BlockAll_Msk   (0x1UL << ETH_MACFFR_PCF_BlockAll_Pos)
    -
    -

    0x00000040

    - -
    -
    - -

    ◆ ETH_MACFFR_PCF_BlockAll

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    #define ETH_MACFFR_PCF_BlockAll   ETH_MACFFR_PCF_BlockAll_Msk /* MAC filters all control frames from reaching the application */
    -
    - -
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    - -

    ◆ ETH_MACFFR_PCF_ForwardAll_Pos

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    #define ETH_MACFFR_PCF_ForwardAll_Pos   (7U)
    -
    - -
    -
    - -

    ◆ ETH_MACFFR_PCF_ForwardAll_Msk

    - -
    -
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    #define ETH_MACFFR_PCF_ForwardAll_Msk   (0x1UL << ETH_MACFFR_PCF_ForwardAll_Pos)
    -
    -

    0x00000080

    - -
    -
    - -

    ◆ ETH_MACFFR_PCF_ForwardAll

    - -
    -
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    #define ETH_MACFFR_PCF_ForwardAll   ETH_MACFFR_PCF_ForwardAll_Msk /* MAC forwards all control frames to application even if they fail the Address Filter */
    -
    - -
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    - -

    ◆ ETH_MACFFR_PCF_ForwardPassedAddrFilter_Pos

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    #define ETH_MACFFR_PCF_ForwardPassedAddrFilter_Pos   (6U)
    -
    - -
    -
    - -

    ◆ ETH_MACFFR_PCF_ForwardPassedAddrFilter_Msk

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    #define ETH_MACFFR_PCF_ForwardPassedAddrFilter_Msk   (0x3UL << ETH_MACFFR_PCF_ForwardPassedAddrFilter_Pos)
    -
    -

    0x000000C0

    - -
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    - -

    ◆ ETH_MACFFR_PCF_ForwardPassedAddrFilter

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    #define ETH_MACFFR_PCF_ForwardPassedAddrFilter   ETH_MACFFR_PCF_ForwardPassedAddrFilter_Msk /* MAC forwards control frames that pass the Address Filter. */
    -
    - -
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    ◆ ETH_MACFFR_BFD_Pos

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    #define ETH_MACFFR_BFD_Pos   (5U)
    -
    - -
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    ◆ ETH_MACFFR_BFD_Msk

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    #define ETH_MACFFR_BFD_Msk   (0x1UL << ETH_MACFFR_BFD_Pos)
    -
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    0x00000020

    - -
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    ◆ ETH_MACFFR_BFD

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    #define ETH_MACFFR_BFD   ETH_MACFFR_BFD_Msk /* Broadcast frame disable */
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    ◆ ETH_MACFFR_PAM_Pos

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    #define ETH_MACFFR_PAM_Pos   (4U)
    -
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    ◆ ETH_MACFFR_PAM_Msk

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    #define ETH_MACFFR_PAM_Msk   (0x1UL << ETH_MACFFR_PAM_Pos)
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    0x00000010

    - -
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    ◆ ETH_MACFFR_PAM

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    #define ETH_MACFFR_PAM   ETH_MACFFR_PAM_Msk /* Pass all mutlicast */
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    ◆ ETH_MACFFR_DAIF_Pos

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    #define ETH_MACFFR_DAIF_Pos   (3U)
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    ◆ ETH_MACFFR_DAIF_Msk

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    #define ETH_MACFFR_DAIF_Msk   (0x1UL << ETH_MACFFR_DAIF_Pos)
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    0x00000008

    - -
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    ◆ ETH_MACFFR_DAIF

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    #define ETH_MACFFR_DAIF   ETH_MACFFR_DAIF_Msk /* DA Inverse filtering */
    -
    - -
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    ◆ ETH_MACFFR_HM_Pos

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    #define ETH_MACFFR_HM_Pos   (2U)
    -
    - -
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    ◆ ETH_MACFFR_HM_Msk

    - -
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    #define ETH_MACFFR_HM_Msk   (0x1UL << ETH_MACFFR_HM_Pos)
    -
    -

    0x00000004

    - -
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    ◆ ETH_MACFFR_HM

    - -
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    #define ETH_MACFFR_HM   ETH_MACFFR_HM_Msk /* Hash multicast */
    -
    - -
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    ◆ ETH_MACFFR_HU_Pos

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    #define ETH_MACFFR_HU_Pos   (1U)
    -
    - -
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    ◆ ETH_MACFFR_HU_Msk

    - -
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    #define ETH_MACFFR_HU_Msk   (0x1UL << ETH_MACFFR_HU_Pos)
    -
    -

    0x00000002

    - -
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    - -

    ◆ ETH_MACFFR_HU

    - -
    -
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    #define ETH_MACFFR_HU   ETH_MACFFR_HU_Msk /* Hash unicast */
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    - -
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    ◆ ETH_MACFFR_PM_Pos

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    #define ETH_MACFFR_PM_Pos   (0U)
    -
    - -
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    ◆ ETH_MACFFR_PM_Msk

    - -
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    #define ETH_MACFFR_PM_Msk   (0x1UL << ETH_MACFFR_PM_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ ETH_MACFFR_PM

    - -
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    #define ETH_MACFFR_PM   ETH_MACFFR_PM_Msk /* Promiscuous mode */
    -
    - -
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    ◆ ETH_MACHTHR_HTH_Pos

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    #define ETH_MACHTHR_HTH_Pos   (0U)
    -
    - -
    -
    - -

    ◆ ETH_MACHTHR_HTH_Msk

    - -
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    #define ETH_MACHTHR_HTH_Msk   (0xFFFFFFFFUL << ETH_MACHTHR_HTH_Pos)
    -
    -

    0xFFFFFFFF

    - -
    -
    - -

    ◆ ETH_MACHTHR_HTH

    - -
    -
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    #define ETH_MACHTHR_HTH   ETH_MACHTHR_HTH_Msk /* Hash table high */
    -
    - -
    -
    - -

    ◆ ETH_MACHTLR_HTL_Pos

    - -
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    #define ETH_MACHTLR_HTL_Pos   (0U)
    -
    - -
    -
    - -

    ◆ ETH_MACHTLR_HTL_Msk

    - -
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    #define ETH_MACHTLR_HTL_Msk   (0xFFFFFFFFUL << ETH_MACHTLR_HTL_Pos)
    -
    -

    0xFFFFFFFF

    - -
    -
    - -

    ◆ ETH_MACHTLR_HTL

    - -
    -
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    #define ETH_MACHTLR_HTL   ETH_MACHTLR_HTL_Msk /* Hash table low */
    -
    - -
    -
    - -

    ◆ ETH_MACMIIAR_PA_Pos

    - -
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    #define ETH_MACMIIAR_PA_Pos   (11U)
    -
    - -
    -
    - -

    ◆ ETH_MACMIIAR_PA_Msk

    - -
    -
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    #define ETH_MACMIIAR_PA_Msk   (0x1FUL << ETH_MACMIIAR_PA_Pos)
    -
    -

    0x0000F800

    - -
    -
    - -

    ◆ ETH_MACMIIAR_PA

    - -
    -
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    #define ETH_MACMIIAR_PA   ETH_MACMIIAR_PA_Msk /* Physical layer address */
    -
    - -
    -
    - -

    ◆ ETH_MACMIIAR_MR_Pos

    - -
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    #define ETH_MACMIIAR_MR_Pos   (6U)
    -
    - -
    -
    - -

    ◆ ETH_MACMIIAR_MR_Msk

    - -
    -
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    #define ETH_MACMIIAR_MR_Msk   (0x1FUL << ETH_MACMIIAR_MR_Pos)
    -
    -

    0x000007C0

    - -
    -
    - -

    ◆ ETH_MACMIIAR_MR

    - -
    -
    - - - - -
    #define ETH_MACMIIAR_MR   ETH_MACMIIAR_MR_Msk /* MII register in the selected PHY */
    -
    - -
    -
    - -

    ◆ ETH_MACMIIAR_CR_Pos

    - -
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    #define ETH_MACMIIAR_CR_Pos   (2U)
    -
    - -
    -
    - -

    ◆ ETH_MACMIIAR_CR_Msk

    - -
    -
    - - - - -
    #define ETH_MACMIIAR_CR_Msk   (0x7UL << ETH_MACMIIAR_CR_Pos)
    -
    -

    0x0000001C

    - -
    -
    - -

    ◆ ETH_MACMIIAR_CR

    - -
    -
    - - - - -
    #define ETH_MACMIIAR_CR   ETH_MACMIIAR_CR_Msk /* CR clock range: 6 cases */
    -
    - -
    -
    - -

    ◆ ETH_MACMIIAR_CR_Div42

    - -
    -
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    #define ETH_MACMIIAR_CR_Div42   0x00000000U /* HCLK:60-100 MHz; MDC clock= HCLK/42 */
    -
    - -
    -
    - -

    ◆ ETH_MACMIIAR_CR_Div62_Pos

    - -
    -
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    #define ETH_MACMIIAR_CR_Div62_Pos   (2U)
    -
    - -
    -
    - -

    ◆ ETH_MACMIIAR_CR_Div62_Msk

    - -
    -
    - - - - -
    #define ETH_MACMIIAR_CR_Div62_Msk   (0x1UL << ETH_MACMIIAR_CR_Div62_Pos)
    -
    -

    0x00000004

    - -
    -
    - -

    ◆ ETH_MACMIIAR_CR_Div62

    - -
    -
    - - - - -
    #define ETH_MACMIIAR_CR_Div62   ETH_MACMIIAR_CR_Div62_Msk /* HCLK:100-150 MHz; MDC clock= HCLK/62 */
    -
    - -
    -
    - -

    ◆ ETH_MACMIIAR_CR_Div16_Pos

    - -
    -
    - - - - -
    #define ETH_MACMIIAR_CR_Div16_Pos   (3U)
    -
    - -
    -
    - -

    ◆ ETH_MACMIIAR_CR_Div16_Msk

    - -
    -
    - - - - -
    #define ETH_MACMIIAR_CR_Div16_Msk   (0x1UL << ETH_MACMIIAR_CR_Div16_Pos)
    -
    -

    0x00000008

    - -
    -
    - -

    ◆ ETH_MACMIIAR_CR_Div16

    - -
    -
    - - - - -
    #define ETH_MACMIIAR_CR_Div16   ETH_MACMIIAR_CR_Div16_Msk /* HCLK:20-35 MHz; MDC clock= HCLK/16 */
    -
    - -
    -
    - -

    ◆ ETH_MACMIIAR_CR_Div26_Pos

    - -
    -
    - - - - -
    #define ETH_MACMIIAR_CR_Div26_Pos   (2U)
    -
    - -
    -
    - -

    ◆ ETH_MACMIIAR_CR_Div26_Msk

    - -
    -
    - - - - -
    #define ETH_MACMIIAR_CR_Div26_Msk   (0x3UL << ETH_MACMIIAR_CR_Div26_Pos)
    -
    -

    0x0000000C

    - -
    -
    - -

    ◆ ETH_MACMIIAR_CR_Div26

    - -
    -
    - - - - -
    #define ETH_MACMIIAR_CR_Div26   ETH_MACMIIAR_CR_Div26_Msk /* HCLK:35-60 MHz; MDC clock= HCLK/26 */
    -
    - -
    -
    - -

    ◆ ETH_MACMIIAR_CR_Div102_Pos

    - -
    -
    - - - - -
    #define ETH_MACMIIAR_CR_Div102_Pos   (4U)
    -
    - -
    -
    - -

    ◆ ETH_MACMIIAR_CR_Div102_Msk

    - -
    -
    - - - - -
    #define ETH_MACMIIAR_CR_Div102_Msk   (0x1UL << ETH_MACMIIAR_CR_Div102_Pos)
    -
    -

    0x00000010

    - -
    -
    - -

    ◆ ETH_MACMIIAR_CR_Div102

    - -
    -
    - - - - -
    #define ETH_MACMIIAR_CR_Div102   ETH_MACMIIAR_CR_Div102_Msk /* HCLK:150-168 MHz; MDC clock= HCLK/102 */
    -
    - -
    -
    - -

    ◆ ETH_MACMIIAR_MW_Pos

    - -
    -
    - - - - -
    #define ETH_MACMIIAR_MW_Pos   (1U)
    -
    - -
    -
    - -

    ◆ ETH_MACMIIAR_MW_Msk

    - -
    -
    - - - - -
    #define ETH_MACMIIAR_MW_Msk   (0x1UL << ETH_MACMIIAR_MW_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ ETH_MACMIIAR_MW

    - -
    -
    - - - - -
    #define ETH_MACMIIAR_MW   ETH_MACMIIAR_MW_Msk /* MII write */
    -
    - -
    -
    - -

    ◆ ETH_MACMIIAR_MB_Pos

    - -
    -
    - - - - -
    #define ETH_MACMIIAR_MB_Pos   (0U)
    -
    - -
    -
    - -

    ◆ ETH_MACMIIAR_MB_Msk

    - -
    -
    - - - - -
    #define ETH_MACMIIAR_MB_Msk   (0x1UL << ETH_MACMIIAR_MB_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ ETH_MACMIIAR_MB

    - -
    -
    - - - - -
    #define ETH_MACMIIAR_MB   ETH_MACMIIAR_MB_Msk /* MII busy */
    -
    - -
    -
    - -

    ◆ ETH_MACMIIDR_MD_Pos

    - -
    -
    - - - - -
    #define ETH_MACMIIDR_MD_Pos   (0U)
    -
    - -
    -
    - -

    ◆ ETH_MACMIIDR_MD_Msk

    - -
    -
    - - - - -
    #define ETH_MACMIIDR_MD_Msk   (0xFFFFUL << ETH_MACMIIDR_MD_Pos)
    -
    -

    0x0000FFFF

    - -
    -
    - -

    ◆ ETH_MACMIIDR_MD

    - -
    -
    - - - - -
    #define ETH_MACMIIDR_MD   ETH_MACMIIDR_MD_Msk /* MII data: read/write data from/to PHY */
    -
    - -
    -
    - -

    ◆ ETH_MACFCR_PT_Pos

    - -
    -
    - - - - -
    #define ETH_MACFCR_PT_Pos   (16U)
    -
    - -
    -
    - -

    ◆ ETH_MACFCR_PT_Msk

    - -
    -
    - - - - -
    #define ETH_MACFCR_PT_Msk   (0xFFFFUL << ETH_MACFCR_PT_Pos)
    -
    -

    0xFFFF0000

    - -
    -
    - -

    ◆ ETH_MACFCR_PT

    - -
    -
    - - - - -
    #define ETH_MACFCR_PT   ETH_MACFCR_PT_Msk /* Pause time */
    -
    - -
    -
    - -

    ◆ ETH_MACFCR_ZQPD_Pos

    - -
    -
    - - - - -
    #define ETH_MACFCR_ZQPD_Pos   (7U)
    -
    - -
    -
    - -

    ◆ ETH_MACFCR_ZQPD_Msk

    - -
    -
    - - - - -
    #define ETH_MACFCR_ZQPD_Msk   (0x1UL << ETH_MACFCR_ZQPD_Pos)
    -
    -

    0x00000080

    - -
    -
    - -

    ◆ ETH_MACFCR_ZQPD

    - -
    -
    - - - - -
    #define ETH_MACFCR_ZQPD   ETH_MACFCR_ZQPD_Msk /* Zero-quanta pause disable */
    -
    - -
    -
    - -

    ◆ ETH_MACFCR_PLT_Pos

    - -
    -
    - - - - -
    #define ETH_MACFCR_PLT_Pos   (4U)
    -
    - -
    -
    - -

    ◆ ETH_MACFCR_PLT_Msk

    - -
    -
    - - - - -
    #define ETH_MACFCR_PLT_Msk   (0x3UL << ETH_MACFCR_PLT_Pos)
    -
    -

    0x00000030

    - -
    -
    - -

    ◆ ETH_MACFCR_PLT

    - -
    -
    - - - - -
    #define ETH_MACFCR_PLT   ETH_MACFCR_PLT_Msk /* Pause low threshold: 4 cases */
    -
    - -
    -
    - -

    ◆ ETH_MACFCR_PLT_Minus4

    - -
    -
    - - - - -
    #define ETH_MACFCR_PLT_Minus4   0x00000000U /* Pause time minus 4 slot times */
    -
    - -
    -
    - -

    ◆ ETH_MACFCR_PLT_Minus28_Pos

    - -
    -
    - - - - -
    #define ETH_MACFCR_PLT_Minus28_Pos   (4U)
    -
    - -
    -
    - -

    ◆ ETH_MACFCR_PLT_Minus28_Msk

    - -
    -
    - - - - -
    #define ETH_MACFCR_PLT_Minus28_Msk   (0x1UL << ETH_MACFCR_PLT_Minus28_Pos)
    -
    -

    0x00000010

    - -
    -
    - -

    ◆ ETH_MACFCR_PLT_Minus28

    - -
    -
    - - - - -
    #define ETH_MACFCR_PLT_Minus28   ETH_MACFCR_PLT_Minus28_Msk /* Pause time minus 28 slot times */
    -
    - -
    -
    - -

    ◆ ETH_MACFCR_PLT_Minus144_Pos

    - -
    -
    - - - - -
    #define ETH_MACFCR_PLT_Minus144_Pos   (5U)
    -
    - -
    -
    - -

    ◆ ETH_MACFCR_PLT_Minus144_Msk

    - -
    -
    - - - - -
    #define ETH_MACFCR_PLT_Minus144_Msk   (0x1UL << ETH_MACFCR_PLT_Minus144_Pos)
    -
    -

    0x00000020

    - -
    -
    - -

    ◆ ETH_MACFCR_PLT_Minus144

    - -
    -
    - - - - -
    #define ETH_MACFCR_PLT_Minus144   ETH_MACFCR_PLT_Minus144_Msk /* Pause time minus 144 slot times */
    -
    - -
    -
    - -

    ◆ ETH_MACFCR_PLT_Minus256_Pos

    - -
    -
    - - - - -
    #define ETH_MACFCR_PLT_Minus256_Pos   (4U)
    -
    - -
    -
    - -

    ◆ ETH_MACFCR_PLT_Minus256_Msk

    - -
    -
    - - - - -
    #define ETH_MACFCR_PLT_Minus256_Msk   (0x3UL << ETH_MACFCR_PLT_Minus256_Pos)
    -
    -

    0x00000030

    - -
    -
    - -

    ◆ ETH_MACFCR_PLT_Minus256

    - -
    -
    - - - - -
    #define ETH_MACFCR_PLT_Minus256   ETH_MACFCR_PLT_Minus256_Msk /* Pause time minus 256 slot times */
    -
    - -
    -
    - -

    ◆ ETH_MACFCR_UPFD_Pos

    - -
    -
    - - - - -
    #define ETH_MACFCR_UPFD_Pos   (3U)
    -
    - -
    -
    - -

    ◆ ETH_MACFCR_UPFD_Msk

    - -
    -
    - - - - -
    #define ETH_MACFCR_UPFD_Msk   (0x1UL << ETH_MACFCR_UPFD_Pos)
    -
    -

    0x00000008

    - -
    -
    - -

    ◆ ETH_MACFCR_UPFD

    - -
    -
    - - - - -
    #define ETH_MACFCR_UPFD   ETH_MACFCR_UPFD_Msk /* Unicast pause frame detect */
    -
    - -
    -
    - -

    ◆ ETH_MACFCR_RFCE_Pos

    - -
    -
    - - - - -
    #define ETH_MACFCR_RFCE_Pos   (2U)
    -
    - -
    -
    - -

    ◆ ETH_MACFCR_RFCE_Msk

    - -
    -
    - - - - -
    #define ETH_MACFCR_RFCE_Msk   (0x1UL << ETH_MACFCR_RFCE_Pos)
    -
    -

    0x00000004

    - -
    -
    - -

    ◆ ETH_MACFCR_RFCE

    - -
    -
    - - - - -
    #define ETH_MACFCR_RFCE   ETH_MACFCR_RFCE_Msk /* Receive flow control enable */
    -
    - -
    -
    - -

    ◆ ETH_MACFCR_TFCE_Pos

    - -
    -
    - - - - -
    #define ETH_MACFCR_TFCE_Pos   (1U)
    -
    - -
    -
    - -

    ◆ ETH_MACFCR_TFCE_Msk

    - -
    -
    - - - - -
    #define ETH_MACFCR_TFCE_Msk   (0x1UL << ETH_MACFCR_TFCE_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ ETH_MACFCR_TFCE

    - -
    -
    - - - - -
    #define ETH_MACFCR_TFCE   ETH_MACFCR_TFCE_Msk /* Transmit flow control enable */
    -
    - -
    -
    - -

    ◆ ETH_MACFCR_FCBBPA_Pos

    - -
    -
    - - - - -
    #define ETH_MACFCR_FCBBPA_Pos   (0U)
    -
    - -
    -
    - -

    ◆ ETH_MACFCR_FCBBPA_Msk

    - -
    -
    - - - - -
    #define ETH_MACFCR_FCBBPA_Msk   (0x1UL << ETH_MACFCR_FCBBPA_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ ETH_MACFCR_FCBBPA

    - -
    -
    - - - - -
    #define ETH_MACFCR_FCBBPA   ETH_MACFCR_FCBBPA_Msk /* Flow control busy/backpressure activate */
    -
    - -
    -
    - -

    ◆ ETH_MACVLANTR_VLANTC_Pos

    - -
    -
    - - - - -
    #define ETH_MACVLANTR_VLANTC_Pos   (16U)
    -
    - -
    -
    - -

    ◆ ETH_MACVLANTR_VLANTC_Msk

    - -
    -
    - - - - -
    #define ETH_MACVLANTR_VLANTC_Msk   (0x1UL << ETH_MACVLANTR_VLANTC_Pos)
    -
    -

    0x00010000

    - -
    -
    - -

    ◆ ETH_MACVLANTR_VLANTC

    - -
    -
    - - - - -
    #define ETH_MACVLANTR_VLANTC   ETH_MACVLANTR_VLANTC_Msk /* 12-bit VLAN tag comparison */
    -
    - -
    -
    - -

    ◆ ETH_MACVLANTR_VLANTI_Pos

    - -
    -
    - - - - -
    #define ETH_MACVLANTR_VLANTI_Pos   (0U)
    -
    - -
    -
    - -

    ◆ ETH_MACVLANTR_VLANTI_Msk

    - -
    -
    - - - - -
    #define ETH_MACVLANTR_VLANTI_Msk   (0xFFFFUL << ETH_MACVLANTR_VLANTI_Pos)
    -
    -

    0x0000FFFF

    - -
    -
    - -

    ◆ ETH_MACVLANTR_VLANTI

    - -
    -
    - - - - -
    #define ETH_MACVLANTR_VLANTI   ETH_MACVLANTR_VLANTI_Msk /* VLAN tag identifier (for receive frames) */
    -
    - -
    -
    - -

    ◆ ETH_MACRWUFFR_D_Pos

    - -
    -
    - - - - -
    #define ETH_MACRWUFFR_D_Pos   (0U)
    -
    - -
    -
    - -

    ◆ ETH_MACRWUFFR_D_Msk

    - -
    -
    - - - - -
    #define ETH_MACRWUFFR_D_Msk   (0xFFFFFFFFUL << ETH_MACRWUFFR_D_Pos)
    -
    -

    0xFFFFFFFF

    - -
    -
    - -

    ◆ ETH_MACRWUFFR_D

    - -
    -
    - - - - -
    #define ETH_MACRWUFFR_D   ETH_MACRWUFFR_D_Msk /* Wake-up frame filter register data */
    -
    - -
    -
    - -

    ◆ ETH_MACPMTCSR_WFFRPR_Pos

    - -
    -
    - - - - -
    #define ETH_MACPMTCSR_WFFRPR_Pos   (31U)
    -
    - -
    -
    - -

    ◆ ETH_MACPMTCSR_WFFRPR_Msk

    - -
    -
    - - - - -
    #define ETH_MACPMTCSR_WFFRPR_Msk   (0x1UL << ETH_MACPMTCSR_WFFRPR_Pos)
    -
    -

    0x80000000

    - -
    -
    - -

    ◆ ETH_MACPMTCSR_WFFRPR

    - -
    -
    - - - - -
    #define ETH_MACPMTCSR_WFFRPR   ETH_MACPMTCSR_WFFRPR_Msk /* Wake-Up Frame Filter Register Pointer Reset */
    -
    - -
    -
    - -

    ◆ ETH_MACPMTCSR_GU_Pos

    - -
    -
    - - - - -
    #define ETH_MACPMTCSR_GU_Pos   (9U)
    -
    - -
    -
    - -

    ◆ ETH_MACPMTCSR_GU_Msk

    - -
    -
    - - - - -
    #define ETH_MACPMTCSR_GU_Msk   (0x1UL << ETH_MACPMTCSR_GU_Pos)
    -
    -

    0x00000200

    - -
    -
    - -

    ◆ ETH_MACPMTCSR_GU

    - -
    -
    - - - - -
    #define ETH_MACPMTCSR_GU   ETH_MACPMTCSR_GU_Msk /* Global Unicast */
    -
    - -
    -
    - -

    ◆ ETH_MACPMTCSR_WFR_Pos

    - -
    -
    - - - - -
    #define ETH_MACPMTCSR_WFR_Pos   (6U)
    -
    - -
    -
    - -

    ◆ ETH_MACPMTCSR_WFR_Msk

    - -
    -
    - - - - -
    #define ETH_MACPMTCSR_WFR_Msk   (0x1UL << ETH_MACPMTCSR_WFR_Pos)
    -
    -

    0x00000040

    - -
    -
    - -

    ◆ ETH_MACPMTCSR_WFR

    - -
    -
    - - - - -
    #define ETH_MACPMTCSR_WFR   ETH_MACPMTCSR_WFR_Msk /* Wake-Up Frame Received */
    -
    - -
    -
    - -

    ◆ ETH_MACPMTCSR_MPR_Pos

    - -
    -
    - - - - -
    #define ETH_MACPMTCSR_MPR_Pos   (5U)
    -
    - -
    -
    - -

    ◆ ETH_MACPMTCSR_MPR_Msk

    - -
    -
    - - - - -
    #define ETH_MACPMTCSR_MPR_Msk   (0x1UL << ETH_MACPMTCSR_MPR_Pos)
    -
    -

    0x00000020

    - -
    -
    - -

    ◆ ETH_MACPMTCSR_MPR

    - -
    -
    - - - - -
    #define ETH_MACPMTCSR_MPR   ETH_MACPMTCSR_MPR_Msk /* Magic Packet Received */
    -
    - -
    -
    - -

    ◆ ETH_MACPMTCSR_WFE_Pos

    - -
    -
    - - - - -
    #define ETH_MACPMTCSR_WFE_Pos   (2U)
    -
    - -
    -
    - -

    ◆ ETH_MACPMTCSR_WFE_Msk

    - -
    -
    - - - - -
    #define ETH_MACPMTCSR_WFE_Msk   (0x1UL << ETH_MACPMTCSR_WFE_Pos)
    -
    -

    0x00000004

    - -
    -
    - -

    ◆ ETH_MACPMTCSR_WFE

    - -
    -
    - - - - -
    #define ETH_MACPMTCSR_WFE   ETH_MACPMTCSR_WFE_Msk /* Wake-Up Frame Enable */
    -
    - -
    -
    - -

    ◆ ETH_MACPMTCSR_MPE_Pos

    - -
    -
    - - - - -
    #define ETH_MACPMTCSR_MPE_Pos   (1U)
    -
    - -
    -
    - -

    ◆ ETH_MACPMTCSR_MPE_Msk

    - -
    -
    - - - - -
    #define ETH_MACPMTCSR_MPE_Msk   (0x1UL << ETH_MACPMTCSR_MPE_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ ETH_MACPMTCSR_MPE

    - -
    -
    - - - - -
    #define ETH_MACPMTCSR_MPE   ETH_MACPMTCSR_MPE_Msk /* Magic Packet Enable */
    -
    - -
    -
    - -

    ◆ ETH_MACPMTCSR_PD_Pos

    - -
    -
    - - - - -
    #define ETH_MACPMTCSR_PD_Pos   (0U)
    -
    - -
    -
    - -

    ◆ ETH_MACPMTCSR_PD_Msk

    - -
    -
    - - - - -
    #define ETH_MACPMTCSR_PD_Msk   (0x1UL << ETH_MACPMTCSR_PD_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ ETH_MACPMTCSR_PD

    - -
    -
    - - - - -
    #define ETH_MACPMTCSR_PD   ETH_MACPMTCSR_PD_Msk /* Power Down */
    -
    - -
    -
    - -

    ◆ ETH_MACDBGR_TFF_Pos

    - -
    -
    - - - - -
    #define ETH_MACDBGR_TFF_Pos   (25U)
    -
    - -
    -
    - -

    ◆ ETH_MACDBGR_TFF_Msk

    - -
    -
    - - - - -
    #define ETH_MACDBGR_TFF_Msk   (0x1UL << ETH_MACDBGR_TFF_Pos)
    -
    -

    0x02000000

    - -
    -
    - -

    ◆ ETH_MACDBGR_TFF

    - -
    -
    - - - - -
    #define ETH_MACDBGR_TFF   ETH_MACDBGR_TFF_Msk /* Tx FIFO full */
    -
    - -
    -
    - -

    ◆ ETH_MACDBGR_TFNE_Pos

    - -
    -
    - - - - -
    #define ETH_MACDBGR_TFNE_Pos   (24U)
    -
    - -
    -
    - -

    ◆ ETH_MACDBGR_TFNE_Msk

    - -
    -
    - - - - -
    #define ETH_MACDBGR_TFNE_Msk   (0x1UL << ETH_MACDBGR_TFNE_Pos)
    -
    -

    0x01000000

    - -
    -
    - -

    ◆ ETH_MACDBGR_TFNE

    - -
    -
    - - - - -
    #define ETH_MACDBGR_TFNE   ETH_MACDBGR_TFNE_Msk /* Tx FIFO not empty */
    -
    - -
    -
    - -

    ◆ ETH_MACDBGR_TFWA_Pos

    - -
    -
    - - - - -
    #define ETH_MACDBGR_TFWA_Pos   (22U)
    -
    - -
    -
    - -

    ◆ ETH_MACDBGR_TFWA_Msk

    - -
    -
    - - - - -
    #define ETH_MACDBGR_TFWA_Msk   (0x1UL << ETH_MACDBGR_TFWA_Pos)
    -
    -

    0x00400000

    - -
    -
    - -

    ◆ ETH_MACDBGR_TFWA

    - -
    -
    - - - - -
    #define ETH_MACDBGR_TFWA   ETH_MACDBGR_TFWA_Msk /* Tx FIFO write active */
    -
    - -
    -
    - -

    ◆ ETH_MACDBGR_TFRS_Pos

    - -
    -
    - - - - -
    #define ETH_MACDBGR_TFRS_Pos   (20U)
    -
    - -
    -
    - -

    ◆ ETH_MACDBGR_TFRS_Msk

    - -
    -
    - - - - -
    #define ETH_MACDBGR_TFRS_Msk   (0x3UL << ETH_MACDBGR_TFRS_Pos)
    -
    -

    0x00300000

    - -
    -
    - -

    ◆ ETH_MACDBGR_TFRS

    - -
    -
    - - - - -
    #define ETH_MACDBGR_TFRS   ETH_MACDBGR_TFRS_Msk /* Tx FIFO read status mask */
    -
    - -
    -
    - -

    ◆ ETH_MACDBGR_TFRS_WRITING_Pos

    - -
    -
    - - - - -
    #define ETH_MACDBGR_TFRS_WRITING_Pos   (20U)
    -
    - -
    -
    - -

    ◆ ETH_MACDBGR_TFRS_WRITING_Msk

    - -
    -
    - - - - -
    #define ETH_MACDBGR_TFRS_WRITING_Msk   (0x3UL << ETH_MACDBGR_TFRS_WRITING_Pos)
    -
    -

    0x00300000

    - -
    -
    - -

    ◆ ETH_MACDBGR_TFRS_WRITING

    - -
    -
    - - - - -
    #define ETH_MACDBGR_TFRS_WRITING   ETH_MACDBGR_TFRS_WRITING_Msk /* Writing the received TxStatus or flushing the TxFIFO */
    -
    - -
    -
    - -

    ◆ ETH_MACDBGR_TFRS_WAITING_Pos

    - -
    -
    - - - - -
    #define ETH_MACDBGR_TFRS_WAITING_Pos   (21U)
    -
    - -
    -
    - -

    ◆ ETH_MACDBGR_TFRS_WAITING_Msk

    - -
    -
    - - - - -
    #define ETH_MACDBGR_TFRS_WAITING_Msk   (0x1UL << ETH_MACDBGR_TFRS_WAITING_Pos)
    -
    -

    0x00200000

    - -
    -
    - -

    ◆ ETH_MACDBGR_TFRS_WAITING

    - -
    -
    - - - - -
    #define ETH_MACDBGR_TFRS_WAITING   ETH_MACDBGR_TFRS_WAITING_Msk /* Waiting for TxStatus from MAC transmitter */
    -
    - -
    -
    - -

    ◆ ETH_MACDBGR_TFRS_READ_Pos

    - -
    -
    - - - - -
    #define ETH_MACDBGR_TFRS_READ_Pos   (20U)
    -
    - -
    -
    - -

    ◆ ETH_MACDBGR_TFRS_READ_Msk

    - -
    -
    - - - - -
    #define ETH_MACDBGR_TFRS_READ_Msk   (0x1UL << ETH_MACDBGR_TFRS_READ_Pos)
    -
    -

    0x00100000

    - -
    -
    - -

    ◆ ETH_MACDBGR_TFRS_READ

    - -
    -
    - - - - -
    #define ETH_MACDBGR_TFRS_READ   ETH_MACDBGR_TFRS_READ_Msk /* Read state (transferring data to the MAC transmitter) */
    -
    - -
    -
    - -

    ◆ ETH_MACDBGR_TFRS_IDLE

    - -
    -
    - - - - -
    #define ETH_MACDBGR_TFRS_IDLE   0x00000000U /* Idle state */
    -
    - -
    -
    - -

    ◆ ETH_MACDBGR_MTP_Pos

    - -
    -
    - - - - -
    #define ETH_MACDBGR_MTP_Pos   (19U)
    -
    - -
    -
    - -

    ◆ ETH_MACDBGR_MTP_Msk

    - -
    -
    - - - - -
    #define ETH_MACDBGR_MTP_Msk   (0x1UL << ETH_MACDBGR_MTP_Pos)
    -
    -

    0x00080000

    - -
    -
    - -

    ◆ ETH_MACDBGR_MTP

    - -
    -
    - - - - -
    #define ETH_MACDBGR_MTP   ETH_MACDBGR_MTP_Msk /* MAC transmitter in pause */
    -
    - -
    -
    - -

    ◆ ETH_MACDBGR_MTFCS_Pos

    - -
    -
    - - - - -
    #define ETH_MACDBGR_MTFCS_Pos   (17U)
    -
    - -
    -
    - -

    ◆ ETH_MACDBGR_MTFCS_Msk

    - -
    -
    - - - - -
    #define ETH_MACDBGR_MTFCS_Msk   (0x3UL << ETH_MACDBGR_MTFCS_Pos)
    -
    -

    0x00060000

    - -
    -
    - -

    ◆ ETH_MACDBGR_MTFCS

    - -
    -
    - - - - -
    #define ETH_MACDBGR_MTFCS   ETH_MACDBGR_MTFCS_Msk /* MAC transmit frame controller status mask */
    -
    - -
    -
    - -

    ◆ ETH_MACDBGR_MTFCS_TRANSFERRING_Pos

    - -
    -
    - - - - -
    #define ETH_MACDBGR_MTFCS_TRANSFERRING_Pos   (17U)
    -
    - -
    -
    - -

    ◆ ETH_MACDBGR_MTFCS_TRANSFERRING_Msk

    - -
    -
    - - - - -
    #define ETH_MACDBGR_MTFCS_TRANSFERRING_Msk   (0x3UL << ETH_MACDBGR_MTFCS_TRANSFERRING_Pos)
    -
    -

    0x00060000

    - -
    -
    - -

    ◆ ETH_MACDBGR_MTFCS_TRANSFERRING

    - -
    -
    - - - - -
    #define ETH_MACDBGR_MTFCS_TRANSFERRING   ETH_MACDBGR_MTFCS_TRANSFERRING_Msk /* Transferring input frame for transmission */
    -
    - -
    -
    - -

    ◆ ETH_MACDBGR_MTFCS_GENERATINGPCF_Pos

    - -
    -
    - - - - -
    #define ETH_MACDBGR_MTFCS_GENERATINGPCF_Pos   (18U)
    -
    - -
    -
    - -

    ◆ ETH_MACDBGR_MTFCS_GENERATINGPCF_Msk

    - -
    -
    - - - - -
    #define ETH_MACDBGR_MTFCS_GENERATINGPCF_Msk   (0x1UL << ETH_MACDBGR_MTFCS_GENERATINGPCF_Pos)
    -
    -

    0x00040000

    - -
    -
    - -

    ◆ ETH_MACDBGR_MTFCS_GENERATINGPCF

    - -
    -
    - - - - -
    #define ETH_MACDBGR_MTFCS_GENERATINGPCF   ETH_MACDBGR_MTFCS_GENERATINGPCF_Msk /* Generating and transmitting a Pause control frame (in full duplex mode) */
    -
    - -
    -
    - -

    ◆ ETH_MACDBGR_MTFCS_WAITING_Pos

    - -
    -
    - - - - -
    #define ETH_MACDBGR_MTFCS_WAITING_Pos   (17U)
    -
    - -
    -
    - -

    ◆ ETH_MACDBGR_MTFCS_WAITING_Msk

    - -
    -
    - - - - -
    #define ETH_MACDBGR_MTFCS_WAITING_Msk   (0x1UL << ETH_MACDBGR_MTFCS_WAITING_Pos)
    -
    -

    0x00020000

    - -
    -
    - -

    ◆ ETH_MACDBGR_MTFCS_WAITING

    - -
    -
    - - - - -
    #define ETH_MACDBGR_MTFCS_WAITING   ETH_MACDBGR_MTFCS_WAITING_Msk /* Waiting for Status of previous frame or IFG/backoff period to be over */
    -
    - -
    -
    - -

    ◆ ETH_MACDBGR_MTFCS_IDLE

    - -
    -
    - - - - -
    #define ETH_MACDBGR_MTFCS_IDLE   0x00000000U /* Idle */
    -
    - -
    -
    - -

    ◆ ETH_MACDBGR_MMTEA_Pos

    - -
    -
    - - - - -
    #define ETH_MACDBGR_MMTEA_Pos   (16U)
    -
    - -
    -
    - -

    ◆ ETH_MACDBGR_MMTEA_Msk

    - -
    -
    - - - - -
    #define ETH_MACDBGR_MMTEA_Msk   (0x1UL << ETH_MACDBGR_MMTEA_Pos)
    -
    -

    0x00010000

    - -
    -
    - -

    ◆ ETH_MACDBGR_MMTEA

    - -
    -
    - - - - -
    #define ETH_MACDBGR_MMTEA   ETH_MACDBGR_MMTEA_Msk /* MAC MII transmit engine active */
    -
    - -
    -
    - -

    ◆ ETH_MACDBGR_RFFL_Pos

    - -
    -
    - - - - -
    #define ETH_MACDBGR_RFFL_Pos   (8U)
    -
    - -
    -
    - -

    ◆ ETH_MACDBGR_RFFL_Msk

    - -
    -
    - - - - -
    #define ETH_MACDBGR_RFFL_Msk   (0x3UL << ETH_MACDBGR_RFFL_Pos)
    -
    -

    0x00000300

    - -
    -
    - -

    ◆ ETH_MACDBGR_RFFL

    - -
    -
    - - - - -
    #define ETH_MACDBGR_RFFL   ETH_MACDBGR_RFFL_Msk /* Rx FIFO fill level mask */
    -
    - -
    -
    - -

    ◆ ETH_MACDBGR_RFFL_FULL_Pos

    - -
    -
    - - - - -
    #define ETH_MACDBGR_RFFL_FULL_Pos   (8U)
    -
    - -
    -
    - -

    ◆ ETH_MACDBGR_RFFL_FULL_Msk

    - -
    -
    - - - - -
    #define ETH_MACDBGR_RFFL_FULL_Msk   (0x3UL << ETH_MACDBGR_RFFL_FULL_Pos)
    -
    -

    0x00000300

    - -
    -
    - -

    ◆ ETH_MACDBGR_RFFL_FULL

    - -
    -
    - - - - -
    #define ETH_MACDBGR_RFFL_FULL   ETH_MACDBGR_RFFL_FULL_Msk /* RxFIFO full */
    -
    - -
    -
    - -

    ◆ ETH_MACDBGR_RFFL_ABOVEFCT_Pos

    - -
    -
    - - - - -
    #define ETH_MACDBGR_RFFL_ABOVEFCT_Pos   (9U)
    -
    - -
    -
    - -

    ◆ ETH_MACDBGR_RFFL_ABOVEFCT_Msk

    - -
    -
    - - - - -
    #define ETH_MACDBGR_RFFL_ABOVEFCT_Msk   (0x1UL << ETH_MACDBGR_RFFL_ABOVEFCT_Pos)
    -
    -

    0x00000200

    - -
    -
    - -

    ◆ ETH_MACDBGR_RFFL_ABOVEFCT

    - -
    -
    - - - - -
    #define ETH_MACDBGR_RFFL_ABOVEFCT   ETH_MACDBGR_RFFL_ABOVEFCT_Msk /* RxFIFO fill-level above flow-control activate threshold */
    -
    - -
    -
    - -

    ◆ ETH_MACDBGR_RFFL_BELOWFCT_Pos

    - -
    -
    - - - - -
    #define ETH_MACDBGR_RFFL_BELOWFCT_Pos   (8U)
    -
    - -
    -
    - -

    ◆ ETH_MACDBGR_RFFL_BELOWFCT_Msk

    - -
    -
    - - - - -
    #define ETH_MACDBGR_RFFL_BELOWFCT_Msk   (0x1UL << ETH_MACDBGR_RFFL_BELOWFCT_Pos)
    -
    -

    0x00000100

    - -
    -
    - -

    ◆ ETH_MACDBGR_RFFL_BELOWFCT

    - -
    -
    - - - - -
    #define ETH_MACDBGR_RFFL_BELOWFCT   ETH_MACDBGR_RFFL_BELOWFCT_Msk /* RxFIFO fill-level below flow-control de-activate threshold */
    -
    - -
    -
    - -

    ◆ ETH_MACDBGR_RFFL_EMPTY

    - -
    -
    - - - - -
    #define ETH_MACDBGR_RFFL_EMPTY   0x00000000U /* RxFIFO empty */
    -
    - -
    -
    - -

    ◆ ETH_MACDBGR_RFRCS_Pos

    - -
    -
    - - - - -
    #define ETH_MACDBGR_RFRCS_Pos   (5U)
    -
    - -
    -
    - -

    ◆ ETH_MACDBGR_RFRCS_Msk

    - -
    -
    - - - - -
    #define ETH_MACDBGR_RFRCS_Msk   (0x3UL << ETH_MACDBGR_RFRCS_Pos)
    -
    -

    0x00000060

    - -
    -
    - -

    ◆ ETH_MACDBGR_RFRCS

    - -
    -
    - - - - -
    #define ETH_MACDBGR_RFRCS   ETH_MACDBGR_RFRCS_Msk /* Rx FIFO read controller status mask */
    -
    - -
    -
    - -

    ◆ ETH_MACDBGR_RFRCS_FLUSHING_Pos

    - -
    -
    - - - - -
    #define ETH_MACDBGR_RFRCS_FLUSHING_Pos   (5U)
    -
    - -
    -
    - -

    ◆ ETH_MACDBGR_RFRCS_FLUSHING_Msk

    - -
    -
    - - - - -
    #define ETH_MACDBGR_RFRCS_FLUSHING_Msk   (0x3UL << ETH_MACDBGR_RFRCS_FLUSHING_Pos)
    -
    -

    0x00000060

    - -
    -
    - -

    ◆ ETH_MACDBGR_RFRCS_FLUSHING

    - -
    -
    - - - - -
    #define ETH_MACDBGR_RFRCS_FLUSHING   ETH_MACDBGR_RFRCS_FLUSHING_Msk /* Flushing the frame data and status */
    -
    - -
    -
    - -

    ◆ ETH_MACDBGR_RFRCS_STATUSREADING_Pos

    - -
    -
    - - - - -
    #define ETH_MACDBGR_RFRCS_STATUSREADING_Pos   (6U)
    -
    - -
    -
    - -

    ◆ ETH_MACDBGR_RFRCS_STATUSREADING_Msk

    - -
    -
    - - - - -
    #define ETH_MACDBGR_RFRCS_STATUSREADING_Msk   (0x1UL << ETH_MACDBGR_RFRCS_STATUSREADING_Pos)
    -
    -

    0x00000040

    - -
    -
    - -

    ◆ ETH_MACDBGR_RFRCS_STATUSREADING

    - -
    -
    - - - - -
    #define ETH_MACDBGR_RFRCS_STATUSREADING   ETH_MACDBGR_RFRCS_STATUSREADING_Msk /* Reading frame status (or time-stamp) */
    -
    - -
    -
    - -

    ◆ ETH_MACDBGR_RFRCS_DATAREADING_Pos

    - -
    -
    - - - - -
    #define ETH_MACDBGR_RFRCS_DATAREADING_Pos   (5U)
    -
    - -
    -
    - -

    ◆ ETH_MACDBGR_RFRCS_DATAREADING_Msk

    - -
    -
    - - - - -
    #define ETH_MACDBGR_RFRCS_DATAREADING_Msk   (0x1UL << ETH_MACDBGR_RFRCS_DATAREADING_Pos)
    -
    -

    0x00000020

    - -
    -
    - -

    ◆ ETH_MACDBGR_RFRCS_DATAREADING

    - -
    -
    - - - - -
    #define ETH_MACDBGR_RFRCS_DATAREADING   ETH_MACDBGR_RFRCS_DATAREADING_Msk /* Reading frame data */
    -
    - -
    -
    - -

    ◆ ETH_MACDBGR_RFRCS_IDLE

    - -
    -
    - - - - -
    #define ETH_MACDBGR_RFRCS_IDLE   0x00000000U /* IDLE state */
    -
    - -
    -
    - -

    ◆ ETH_MACDBGR_RFWRA_Pos

    - -
    -
    - - - - -
    #define ETH_MACDBGR_RFWRA_Pos   (4U)
    -
    - -
    -
    - -

    ◆ ETH_MACDBGR_RFWRA_Msk

    - -
    -
    - - - - -
    #define ETH_MACDBGR_RFWRA_Msk   (0x1UL << ETH_MACDBGR_RFWRA_Pos)
    -
    -

    0x00000010

    - -
    -
    - -

    ◆ ETH_MACDBGR_RFWRA

    - -
    -
    - - - - -
    #define ETH_MACDBGR_RFWRA   ETH_MACDBGR_RFWRA_Msk /* Rx FIFO write controller active */
    -
    - -
    -
    - -

    ◆ ETH_MACDBGR_MSFRWCS_Pos

    - -
    -
    - - - - -
    #define ETH_MACDBGR_MSFRWCS_Pos   (1U)
    -
    - -
    -
    - -

    ◆ ETH_MACDBGR_MSFRWCS_Msk

    - -
    -
    - - - - -
    #define ETH_MACDBGR_MSFRWCS_Msk   (0x3UL << ETH_MACDBGR_MSFRWCS_Pos)
    -
    -

    0x00000006

    - -
    -
    - -

    ◆ ETH_MACDBGR_MSFRWCS

    - -
    -
    - - - - -
    #define ETH_MACDBGR_MSFRWCS   ETH_MACDBGR_MSFRWCS_Msk /* MAC small FIFO read / write controllers status mask */
    -
    - -
    -
    - -

    ◆ ETH_MACDBGR_MSFRWCS_1

    - -
    -
    - - - - -
    #define ETH_MACDBGR_MSFRWCS_1   (0x2UL << ETH_MACDBGR_MSFRWCS_Pos)
    -
    -

    0x00000004

    - -
    -
    - -

    ◆ ETH_MACDBGR_MSFRWCS_0

    - -
    -
    - - - - -
    #define ETH_MACDBGR_MSFRWCS_0   (0x1UL << ETH_MACDBGR_MSFRWCS_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ ETH_MACDBGR_MMRPEA_Pos

    - -
    -
    - - - - -
    #define ETH_MACDBGR_MMRPEA_Pos   (0U)
    -
    - -
    -
    - -

    ◆ ETH_MACDBGR_MMRPEA_Msk

    - -
    -
    - - - - -
    #define ETH_MACDBGR_MMRPEA_Msk   (0x1UL << ETH_MACDBGR_MMRPEA_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ ETH_MACDBGR_MMRPEA

    - -
    -
    - - - - -
    #define ETH_MACDBGR_MMRPEA   ETH_MACDBGR_MMRPEA_Msk /* MAC MII receive protocol engine active */
    -
    - -
    -
    - -

    ◆ ETH_MACSR_TSTS_Pos

    - -
    -
    - - - - -
    #define ETH_MACSR_TSTS_Pos   (9U)
    -
    - -
    -
    - -

    ◆ ETH_MACSR_TSTS_Msk

    - -
    -
    - - - - -
    #define ETH_MACSR_TSTS_Msk   (0x1UL << ETH_MACSR_TSTS_Pos)
    -
    -

    0x00000200

    - -
    -
    - -

    ◆ ETH_MACSR_TSTS

    - -
    -
    - - - - -
    #define ETH_MACSR_TSTS   ETH_MACSR_TSTS_Msk /* Time stamp trigger status */
    -
    - -
    -
    - -

    ◆ ETH_MACSR_MMCTS_Pos

    - -
    -
    - - - - -
    #define ETH_MACSR_MMCTS_Pos   (6U)
    -
    - -
    -
    - -

    ◆ ETH_MACSR_MMCTS_Msk

    - -
    -
    - - - - -
    #define ETH_MACSR_MMCTS_Msk   (0x1UL << ETH_MACSR_MMCTS_Pos)
    -
    -

    0x00000040

    - -
    -
    - -

    ◆ ETH_MACSR_MMCTS

    - -
    -
    - - - - -
    #define ETH_MACSR_MMCTS   ETH_MACSR_MMCTS_Msk /* MMC transmit status */
    -
    - -
    -
    - -

    ◆ ETH_MACSR_MMMCRS_Pos

    - -
    -
    - - - - -
    #define ETH_MACSR_MMMCRS_Pos   (5U)
    -
    - -
    -
    - -

    ◆ ETH_MACSR_MMMCRS_Msk

    - -
    -
    - - - - -
    #define ETH_MACSR_MMMCRS_Msk   (0x1UL << ETH_MACSR_MMMCRS_Pos)
    -
    -

    0x00000020

    - -
    -
    - -

    ◆ ETH_MACSR_MMMCRS

    - -
    -
    - - - - -
    #define ETH_MACSR_MMMCRS   ETH_MACSR_MMMCRS_Msk /* MMC receive status */
    -
    - -
    -
    - -

    ◆ ETH_MACSR_MMCS_Pos

    - -
    -
    - - - - -
    #define ETH_MACSR_MMCS_Pos   (4U)
    -
    - -
    -
    - -

    ◆ ETH_MACSR_MMCS_Msk

    - -
    -
    - - - - -
    #define ETH_MACSR_MMCS_Msk   (0x1UL << ETH_MACSR_MMCS_Pos)
    -
    -

    0x00000010

    - -
    -
    - -

    ◆ ETH_MACSR_MMCS

    - -
    -
    - - - - -
    #define ETH_MACSR_MMCS   ETH_MACSR_MMCS_Msk /* MMC status */
    -
    - -
    -
    - -

    ◆ ETH_MACSR_PMTS_Pos

    - -
    -
    - - - - -
    #define ETH_MACSR_PMTS_Pos   (3U)
    -
    - -
    -
    - -

    ◆ ETH_MACSR_PMTS_Msk

    - -
    -
    - - - - -
    #define ETH_MACSR_PMTS_Msk   (0x1UL << ETH_MACSR_PMTS_Pos)
    -
    -

    0x00000008

    - -
    -
    - -

    ◆ ETH_MACSR_PMTS

    - -
    -
    - - - - -
    #define ETH_MACSR_PMTS   ETH_MACSR_PMTS_Msk /* PMT status */
    -
    - -
    -
    - -

    ◆ ETH_MACIMR_TSTIM_Pos

    - -
    -
    - - - - -
    #define ETH_MACIMR_TSTIM_Pos   (9U)
    -
    - -
    -
    - -

    ◆ ETH_MACIMR_TSTIM_Msk

    - -
    -
    - - - - -
    #define ETH_MACIMR_TSTIM_Msk   (0x1UL << ETH_MACIMR_TSTIM_Pos)
    -
    -

    0x00000200

    - -
    -
    - -

    ◆ ETH_MACIMR_TSTIM

    - -
    -
    - - - - -
    #define ETH_MACIMR_TSTIM   ETH_MACIMR_TSTIM_Msk /* Time stamp trigger interrupt mask */
    -
    - -
    -
    - -

    ◆ ETH_MACIMR_PMTIM_Pos

    - -
    -
    - - - - -
    #define ETH_MACIMR_PMTIM_Pos   (3U)
    -
    - -
    -
    - -

    ◆ ETH_MACIMR_PMTIM_Msk

    - -
    -
    - - - - -
    #define ETH_MACIMR_PMTIM_Msk   (0x1UL << ETH_MACIMR_PMTIM_Pos)
    -
    -

    0x00000008

    - -
    -
    - -

    ◆ ETH_MACIMR_PMTIM

    - -
    -
    - - - - -
    #define ETH_MACIMR_PMTIM   ETH_MACIMR_PMTIM_Msk /* PMT interrupt mask */
    -
    - -
    -
    - -

    ◆ ETH_MACA0HR_MACA0H_Pos

    - -
    -
    - - - - -
    #define ETH_MACA0HR_MACA0H_Pos   (0U)
    -
    - -
    -
    - -

    ◆ ETH_MACA0HR_MACA0H_Msk

    - -
    -
    - - - - -
    #define ETH_MACA0HR_MACA0H_Msk   (0xFFFFUL << ETH_MACA0HR_MACA0H_Pos)
    -
    -

    0x0000FFFF

    - -
    -
    - -

    ◆ ETH_MACA0HR_MACA0H

    - -
    -
    - - - - -
    #define ETH_MACA0HR_MACA0H   ETH_MACA0HR_MACA0H_Msk /* MAC address0 high */
    -
    - -
    -
    - -

    ◆ ETH_MACA0LR_MACA0L_Pos

    - -
    -
    - - - - -
    #define ETH_MACA0LR_MACA0L_Pos   (0U)
    -
    - -
    -
    - -

    ◆ ETH_MACA0LR_MACA0L_Msk

    - -
    -
    - - - - -
    #define ETH_MACA0LR_MACA0L_Msk   (0xFFFFFFFFUL << ETH_MACA0LR_MACA0L_Pos)
    -
    -

    0xFFFFFFFF

    - -
    -
    - -

    ◆ ETH_MACA0LR_MACA0L

    - -
    -
    - - - - -
    #define ETH_MACA0LR_MACA0L   ETH_MACA0LR_MACA0L_Msk /* MAC address0 low */
    -
    - -
    -
    - -

    ◆ ETH_MACA1HR_AE_Pos

    - -
    -
    - - - - -
    #define ETH_MACA1HR_AE_Pos   (31U)
    -
    - -
    -
    - -

    ◆ ETH_MACA1HR_AE_Msk

    - -
    -
    - - - - -
    #define ETH_MACA1HR_AE_Msk   (0x1UL << ETH_MACA1HR_AE_Pos)
    -
    -

    0x80000000

    - -
    -
    - -

    ◆ ETH_MACA1HR_AE

    - -
    -
    - - - - -
    #define ETH_MACA1HR_AE   ETH_MACA1HR_AE_Msk /* Address enable */
    -
    - -
    -
    - -

    ◆ ETH_MACA1HR_SA_Pos

    - -
    -
    - - - - -
    #define ETH_MACA1HR_SA_Pos   (30U)
    -
    - -
    -
    - -

    ◆ ETH_MACA1HR_SA_Msk

    - -
    -
    - - - - -
    #define ETH_MACA1HR_SA_Msk   (0x1UL << ETH_MACA1HR_SA_Pos)
    -
    -

    0x40000000

    - -
    -
    - -

    ◆ ETH_MACA1HR_SA

    - -
    -
    - - - - -
    #define ETH_MACA1HR_SA   ETH_MACA1HR_SA_Msk /* Source address */
    -
    - -
    -
    - -

    ◆ ETH_MACA1HR_MBC_Pos

    - -
    -
    - - - - -
    #define ETH_MACA1HR_MBC_Pos   (24U)
    -
    - -
    -
    - -

    ◆ ETH_MACA1HR_MBC_Msk

    - -
    -
    - - - - -
    #define ETH_MACA1HR_MBC_Msk   (0x3FUL << ETH_MACA1HR_MBC_Pos)
    -
    -

    0x3F000000

    - -
    -
    - -

    ◆ ETH_MACA1HR_MBC

    - -
    -
    - - - - -
    #define ETH_MACA1HR_MBC   ETH_MACA1HR_MBC_Msk /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
    -
    - -
    -
    - -

    ◆ ETH_MACA1HR_MBC_HBits15_8

    - -
    -
    - - - - -
    #define ETH_MACA1HR_MBC_HBits15_8   0x20000000U /* Mask MAC Address high reg bits [15:8] */
    -
    - -
    -
    - -

    ◆ ETH_MACA1HR_MBC_HBits7_0

    - -
    -
    - - - - -
    #define ETH_MACA1HR_MBC_HBits7_0   0x10000000U /* Mask MAC Address high reg bits [7:0] */
    -
    - -
    -
    - -

    ◆ ETH_MACA1HR_MBC_LBits31_24

    - -
    -
    - - - - -
    #define ETH_MACA1HR_MBC_LBits31_24   0x08000000U /* Mask MAC Address low reg bits [31:24] */
    -
    - -
    -
    - -

    ◆ ETH_MACA1HR_MBC_LBits23_16

    - -
    -
    - - - - -
    #define ETH_MACA1HR_MBC_LBits23_16   0x04000000U /* Mask MAC Address low reg bits [23:16] */
    -
    - -
    -
    - -

    ◆ ETH_MACA1HR_MBC_LBits15_8

    - -
    -
    - - - - -
    #define ETH_MACA1HR_MBC_LBits15_8   0x02000000U /* Mask MAC Address low reg bits [15:8] */
    -
    - -
    -
    - -

    ◆ ETH_MACA1HR_MBC_LBits7_0

    - -
    -
    - - - - -
    #define ETH_MACA1HR_MBC_LBits7_0   0x01000000U /* Mask MAC Address low reg bits [7:0] */
    -
    - -
    -
    - -

    ◆ ETH_MACA1HR_MACA1H_Pos

    - -
    -
    - - - - -
    #define ETH_MACA1HR_MACA1H_Pos   (0U)
    -
    - -
    -
    - -

    ◆ ETH_MACA1HR_MACA1H_Msk

    - -
    -
    - - - - -
    #define ETH_MACA1HR_MACA1H_Msk   (0xFFFFUL << ETH_MACA1HR_MACA1H_Pos)
    -
    -

    0x0000FFFF

    - -
    -
    - -

    ◆ ETH_MACA1HR_MACA1H

    - -
    -
    - - - - -
    #define ETH_MACA1HR_MACA1H   ETH_MACA1HR_MACA1H_Msk /* MAC address1 high */
    -
    - -
    -
    - -

    ◆ ETH_MACA1LR_MACA1L_Pos

    - -
    -
    - - - - -
    #define ETH_MACA1LR_MACA1L_Pos   (0U)
    -
    - -
    -
    - -

    ◆ ETH_MACA1LR_MACA1L_Msk

    - -
    -
    - - - - -
    #define ETH_MACA1LR_MACA1L_Msk   (0xFFFFFFFFUL << ETH_MACA1LR_MACA1L_Pos)
    -
    -

    0xFFFFFFFF

    - -
    -
    - -

    ◆ ETH_MACA1LR_MACA1L

    - -
    -
    - - - - -
    #define ETH_MACA1LR_MACA1L   ETH_MACA1LR_MACA1L_Msk /* MAC address1 low */
    -
    - -
    -
    - -

    ◆ ETH_MACA2HR_AE_Pos

    - -
    -
    - - - - -
    #define ETH_MACA2HR_AE_Pos   (31U)
    -
    - -
    -
    - -

    ◆ ETH_MACA2HR_AE_Msk

    - -
    -
    - - - - -
    #define ETH_MACA2HR_AE_Msk   (0x1UL << ETH_MACA2HR_AE_Pos)
    -
    -

    0x80000000

    - -
    -
    - -

    ◆ ETH_MACA2HR_AE

    - -
    -
    - - - - -
    #define ETH_MACA2HR_AE   ETH_MACA2HR_AE_Msk /* Address enable */
    -
    - -
    -
    - -

    ◆ ETH_MACA2HR_SA_Pos

    - -
    -
    - - - - -
    #define ETH_MACA2HR_SA_Pos   (30U)
    -
    - -
    -
    - -

    ◆ ETH_MACA2HR_SA_Msk

    - -
    -
    - - - - -
    #define ETH_MACA2HR_SA_Msk   (0x1UL << ETH_MACA2HR_SA_Pos)
    -
    -

    0x40000000

    - -
    -
    - -

    ◆ ETH_MACA2HR_SA

    - -
    -
    - - - - -
    #define ETH_MACA2HR_SA   ETH_MACA2HR_SA_Msk /* Source address */
    -
    - -
    -
    - -

    ◆ ETH_MACA2HR_MBC_Pos

    - -
    -
    - - - - -
    #define ETH_MACA2HR_MBC_Pos   (24U)
    -
    - -
    -
    - -

    ◆ ETH_MACA2HR_MBC_Msk

    - -
    -
    - - - - -
    #define ETH_MACA2HR_MBC_Msk   (0x3FUL << ETH_MACA2HR_MBC_Pos)
    -
    -

    0x3F000000

    - -
    -
    - -

    ◆ ETH_MACA2HR_MBC

    - -
    -
    - - - - -
    #define ETH_MACA2HR_MBC   ETH_MACA2HR_MBC_Msk /* Mask byte control */
    -
    - -
    -
    - -

    ◆ ETH_MACA2HR_MBC_HBits15_8

    - -
    -
    - - - - -
    #define ETH_MACA2HR_MBC_HBits15_8   0x20000000U /* Mask MAC Address high reg bits [15:8] */
    -
    - -
    -
    - -

    ◆ ETH_MACA2HR_MBC_HBits7_0

    - -
    -
    - - - - -
    #define ETH_MACA2HR_MBC_HBits7_0   0x10000000U /* Mask MAC Address high reg bits [7:0] */
    -
    - -
    -
    - -

    ◆ ETH_MACA2HR_MBC_LBits31_24

    - -
    -
    - - - - -
    #define ETH_MACA2HR_MBC_LBits31_24   0x08000000U /* Mask MAC Address low reg bits [31:24] */
    -
    - -
    -
    - -

    ◆ ETH_MACA2HR_MBC_LBits23_16

    - -
    -
    - - - - -
    #define ETH_MACA2HR_MBC_LBits23_16   0x04000000U /* Mask MAC Address low reg bits [23:16] */
    -
    - -
    -
    - -

    ◆ ETH_MACA2HR_MBC_LBits15_8

    - -
    -
    - - - - -
    #define ETH_MACA2HR_MBC_LBits15_8   0x02000000U /* Mask MAC Address low reg bits [15:8] */
    -
    - -
    -
    - -

    ◆ ETH_MACA2HR_MBC_LBits7_0

    - -
    -
    - - - - -
    #define ETH_MACA2HR_MBC_LBits7_0   0x01000000U /* Mask MAC Address low reg bits [70] */
    -
    - -
    -
    - -

    ◆ ETH_MACA2HR_MACA2H_Pos

    - -
    -
    - - - - -
    #define ETH_MACA2HR_MACA2H_Pos   (0U)
    -
    - -
    -
    - -

    ◆ ETH_MACA2HR_MACA2H_Msk

    - -
    -
    - - - - -
    #define ETH_MACA2HR_MACA2H_Msk   (0xFFFFUL << ETH_MACA2HR_MACA2H_Pos)
    -
    -

    0x0000FFFF

    - -
    -
    - -

    ◆ ETH_MACA2HR_MACA2H

    - -
    -
    - - - - -
    #define ETH_MACA2HR_MACA2H   ETH_MACA2HR_MACA2H_Msk /* MAC address1 high */
    -
    - -
    -
    - -

    ◆ ETH_MACA2LR_MACA2L_Pos

    - -
    -
    - - - - -
    #define ETH_MACA2LR_MACA2L_Pos   (0U)
    -
    - -
    -
    - -

    ◆ ETH_MACA2LR_MACA2L_Msk

    - -
    -
    - - - - -
    #define ETH_MACA2LR_MACA2L_Msk   (0xFFFFFFFFUL << ETH_MACA2LR_MACA2L_Pos)
    -
    -

    0xFFFFFFFF

    - -
    -
    - -

    ◆ ETH_MACA2LR_MACA2L

    - -
    -
    - - - - -
    #define ETH_MACA2LR_MACA2L   ETH_MACA2LR_MACA2L_Msk /* MAC address2 low */
    -
    - -
    -
    - -

    ◆ ETH_MACA3HR_AE_Pos

    - -
    -
    - - - - -
    #define ETH_MACA3HR_AE_Pos   (31U)
    -
    - -
    -
    - -

    ◆ ETH_MACA3HR_AE_Msk

    - -
    -
    - - - - -
    #define ETH_MACA3HR_AE_Msk   (0x1UL << ETH_MACA3HR_AE_Pos)
    -
    -

    0x80000000

    - -
    -
    - -

    ◆ ETH_MACA3HR_AE

    - -
    -
    - - - - -
    #define ETH_MACA3HR_AE   ETH_MACA3HR_AE_Msk /* Address enable */
    -
    - -
    -
    - -

    ◆ ETH_MACA3HR_SA_Pos

    - -
    -
    - - - - -
    #define ETH_MACA3HR_SA_Pos   (30U)
    -
    - -
    -
    - -

    ◆ ETH_MACA3HR_SA_Msk

    - -
    -
    - - - - -
    #define ETH_MACA3HR_SA_Msk   (0x1UL << ETH_MACA3HR_SA_Pos)
    -
    -

    0x40000000

    - -
    -
    - -

    ◆ ETH_MACA3HR_SA

    - -
    -
    - - - - -
    #define ETH_MACA3HR_SA   ETH_MACA3HR_SA_Msk /* Source address */
    -
    - -
    -
    - -

    ◆ ETH_MACA3HR_MBC_Pos

    - -
    -
    - - - - -
    #define ETH_MACA3HR_MBC_Pos   (24U)
    -
    - -
    -
    - -

    ◆ ETH_MACA3HR_MBC_Msk

    - -
    -
    - - - - -
    #define ETH_MACA3HR_MBC_Msk   (0x3FUL << ETH_MACA3HR_MBC_Pos)
    -
    -

    0x3F000000

    - -
    -
    - -

    ◆ ETH_MACA3HR_MBC

    - -
    -
    - - - - -
    #define ETH_MACA3HR_MBC   ETH_MACA3HR_MBC_Msk /* Mask byte control */
    -
    - -
    -
    - -

    ◆ ETH_MACA3HR_MBC_HBits15_8

    - -
    -
    - - - - -
    #define ETH_MACA3HR_MBC_HBits15_8   0x20000000U /* Mask MAC Address high reg bits [15:8] */
    -
    - -
    -
    - -

    ◆ ETH_MACA3HR_MBC_HBits7_0

    - -
    -
    - - - - -
    #define ETH_MACA3HR_MBC_HBits7_0   0x10000000U /* Mask MAC Address high reg bits [7:0] */
    -
    - -
    -
    - -

    ◆ ETH_MACA3HR_MBC_LBits31_24

    - -
    -
    - - - - -
    #define ETH_MACA3HR_MBC_LBits31_24   0x08000000U /* Mask MAC Address low reg bits [31:24] */
    -
    - -
    -
    - -

    ◆ ETH_MACA3HR_MBC_LBits23_16

    - -
    -
    - - - - -
    #define ETH_MACA3HR_MBC_LBits23_16   0x04000000U /* Mask MAC Address low reg bits [23:16] */
    -
    - -
    -
    - -

    ◆ ETH_MACA3HR_MBC_LBits15_8

    - -
    -
    - - - - -
    #define ETH_MACA3HR_MBC_LBits15_8   0x02000000U /* Mask MAC Address low reg bits [15:8] */
    -
    - -
    -
    - -

    ◆ ETH_MACA3HR_MBC_LBits7_0

    - -
    -
    - - - - -
    #define ETH_MACA3HR_MBC_LBits7_0   0x01000000U /* Mask MAC Address low reg bits [70] */
    -
    - -
    -
    - -

    ◆ ETH_MACA3HR_MACA3H_Pos

    - -
    -
    - - - - -
    #define ETH_MACA3HR_MACA3H_Pos   (0U)
    -
    - -
    -
    - -

    ◆ ETH_MACA3HR_MACA3H_Msk

    - -
    -
    - - - - -
    #define ETH_MACA3HR_MACA3H_Msk   (0xFFFFUL << ETH_MACA3HR_MACA3H_Pos)
    -
    -

    0x0000FFFF

    - -
    -
    - -

    ◆ ETH_MACA3HR_MACA3H

    - -
    -
    - - - - -
    #define ETH_MACA3HR_MACA3H   ETH_MACA3HR_MACA3H_Msk /* MAC address3 high */
    -
    - -
    -
    - -

    ◆ ETH_MACA3LR_MACA3L_Pos

    - -
    -
    - - - - -
    #define ETH_MACA3LR_MACA3L_Pos   (0U)
    -
    - -
    -
    - -

    ◆ ETH_MACA3LR_MACA3L_Msk

    - -
    -
    - - - - -
    #define ETH_MACA3LR_MACA3L_Msk   (0xFFFFFFFFUL << ETH_MACA3LR_MACA3L_Pos)
    -
    -

    0xFFFFFFFF

    - -
    -
    - -

    ◆ ETH_MACA3LR_MACA3L

    - -
    -
    - - - - -
    #define ETH_MACA3LR_MACA3L   ETH_MACA3LR_MACA3L_Msk /* MAC address3 low */
    -
    - -
    -
    - -

    ◆ ETH_MMCCR_MCFHP_Pos

    - -
    -
    - - - - -
    #define ETH_MMCCR_MCFHP_Pos   (5U)
    -
    - -
    -
    - -

    ◆ ETH_MMCCR_MCFHP_Msk

    - -
    -
    - - - - -
    #define ETH_MMCCR_MCFHP_Msk   (0x1UL << ETH_MMCCR_MCFHP_Pos)
    -
    -

    0x00000020

    - -
    -
    - -

    ◆ ETH_MMCCR_MCFHP

    - -
    -
    - - - - -
    #define ETH_MMCCR_MCFHP   ETH_MMCCR_MCFHP_Msk /* MMC counter Full-Half preset */
    -
    - -
    -
    - -

    ◆ ETH_MMCCR_MCP_Pos

    - -
    -
    - - - - -
    #define ETH_MMCCR_MCP_Pos   (4U)
    -
    - -
    -
    - -

    ◆ ETH_MMCCR_MCP_Msk

    - -
    -
    - - - - -
    #define ETH_MMCCR_MCP_Msk   (0x1UL << ETH_MMCCR_MCP_Pos)
    -
    -

    0x00000010

    - -
    -
    - -

    ◆ ETH_MMCCR_MCP

    - -
    -
    - - - - -
    #define ETH_MMCCR_MCP   ETH_MMCCR_MCP_Msk /* MMC counter preset */
    -
    - -
    -
    - -

    ◆ ETH_MMCCR_MCF_Pos

    - -
    -
    - - - - -
    #define ETH_MMCCR_MCF_Pos   (3U)
    -
    - -
    -
    - -

    ◆ ETH_MMCCR_MCF_Msk

    - -
    -
    - - - - -
    #define ETH_MMCCR_MCF_Msk   (0x1UL << ETH_MMCCR_MCF_Pos)
    -
    -

    0x00000008

    - -
    -
    - -

    ◆ ETH_MMCCR_MCF

    - -
    -
    - - - - -
    #define ETH_MMCCR_MCF   ETH_MMCCR_MCF_Msk /* MMC Counter Freeze */
    -
    - -
    -
    - -

    ◆ ETH_MMCCR_ROR_Pos

    - -
    -
    - - - - -
    #define ETH_MMCCR_ROR_Pos   (2U)
    -
    - -
    -
    - -

    ◆ ETH_MMCCR_ROR_Msk

    - -
    -
    - - - - -
    #define ETH_MMCCR_ROR_Msk   (0x1UL << ETH_MMCCR_ROR_Pos)
    -
    -

    0x00000004

    - -
    -
    - -

    ◆ ETH_MMCCR_ROR

    - -
    -
    - - - - -
    #define ETH_MMCCR_ROR   ETH_MMCCR_ROR_Msk /* Reset on Read */
    -
    - -
    -
    - -

    ◆ ETH_MMCCR_CSR_Pos

    - -
    -
    - - - - -
    #define ETH_MMCCR_CSR_Pos   (1U)
    -
    - -
    -
    - -

    ◆ ETH_MMCCR_CSR_Msk

    - -
    -
    - - - - -
    #define ETH_MMCCR_CSR_Msk   (0x1UL << ETH_MMCCR_CSR_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ ETH_MMCCR_CSR

    - -
    -
    - - - - -
    #define ETH_MMCCR_CSR   ETH_MMCCR_CSR_Msk /* Counter Stop Rollover */
    -
    - -
    -
    - -

    ◆ ETH_MMCCR_CR_Pos

    - -
    -
    - - - - -
    #define ETH_MMCCR_CR_Pos   (0U)
    -
    - -
    -
    - -

    ◆ ETH_MMCCR_CR_Msk

    - -
    -
    - - - - -
    #define ETH_MMCCR_CR_Msk   (0x1UL << ETH_MMCCR_CR_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ ETH_MMCCR_CR

    - -
    -
    - - - - -
    #define ETH_MMCCR_CR   ETH_MMCCR_CR_Msk /* Counters Reset */
    -
    - -
    -
    - -

    ◆ ETH_MMCRIR_RGUFS_Pos

    - -
    -
    - - - - -
    #define ETH_MMCRIR_RGUFS_Pos   (17U)
    -
    - -
    -
    - -

    ◆ ETH_MMCRIR_RGUFS_Msk

    - -
    -
    - - - - -
    #define ETH_MMCRIR_RGUFS_Msk   (0x1UL << ETH_MMCRIR_RGUFS_Pos)
    -
    -

    0x00020000

    - -
    -
    - -

    ◆ ETH_MMCRIR_RGUFS

    - -
    -
    - - - - -
    #define ETH_MMCRIR_RGUFS   ETH_MMCRIR_RGUFS_Msk /* Set when Rx good unicast frames counter reaches half the maximum value */
    -
    - -
    -
    - -

    ◆ ETH_MMCRIR_RFAES_Pos

    - -
    -
    - - - - -
    #define ETH_MMCRIR_RFAES_Pos   (6U)
    -
    - -
    -
    - -

    ◆ ETH_MMCRIR_RFAES_Msk

    - -
    -
    - - - - -
    #define ETH_MMCRIR_RFAES_Msk   (0x1UL << ETH_MMCRIR_RFAES_Pos)
    -
    -

    0x00000040

    - -
    -
    - -

    ◆ ETH_MMCRIR_RFAES

    - -
    -
    - - - - -
    #define ETH_MMCRIR_RFAES   ETH_MMCRIR_RFAES_Msk /* Set when Rx alignment error counter reaches half the maximum value */
    -
    - -
    -
    - -

    ◆ ETH_MMCRIR_RFCES_Pos

    - -
    -
    - - - - -
    #define ETH_MMCRIR_RFCES_Pos   (5U)
    -
    - -
    -
    - -

    ◆ ETH_MMCRIR_RFCES_Msk

    - -
    -
    - - - - -
    #define ETH_MMCRIR_RFCES_Msk   (0x1UL << ETH_MMCRIR_RFCES_Pos)
    -
    -

    0x00000020

    - -
    -
    - -

    ◆ ETH_MMCRIR_RFCES

    - -
    -
    - - - - -
    #define ETH_MMCRIR_RFCES   ETH_MMCRIR_RFCES_Msk /* Set when Rx crc error counter reaches half the maximum value */
    -
    - -
    -
    - -

    ◆ ETH_MMCTIR_TGFS_Pos

    - -
    -
    - - - - -
    #define ETH_MMCTIR_TGFS_Pos   (21U)
    -
    - -
    -
    - -

    ◆ ETH_MMCTIR_TGFS_Msk

    - -
    -
    - - - - -
    #define ETH_MMCTIR_TGFS_Msk   (0x1UL << ETH_MMCTIR_TGFS_Pos)
    -
    -

    0x00200000

    - -
    -
    - -

    ◆ ETH_MMCTIR_TGFS

    - -
    -
    - - - - -
    #define ETH_MMCTIR_TGFS   ETH_MMCTIR_TGFS_Msk /* Set when Tx good frame count counter reaches half the maximum value */
    -
    - -
    -
    - -

    ◆ ETH_MMCTIR_TGFMSCS_Pos

    - -
    -
    - - - - -
    #define ETH_MMCTIR_TGFMSCS_Pos   (15U)
    -
    - -
    -
    - -

    ◆ ETH_MMCTIR_TGFMSCS_Msk

    - -
    -
    - - - - -
    #define ETH_MMCTIR_TGFMSCS_Msk   (0x1UL << ETH_MMCTIR_TGFMSCS_Pos)
    -
    -

    0x00008000

    - -
    -
    - -

    ◆ ETH_MMCTIR_TGFMSCS

    - -
    -
    - - - - -
    #define ETH_MMCTIR_TGFMSCS   ETH_MMCTIR_TGFMSCS_Msk /* Set when Tx good multi col counter reaches half the maximum value */
    -
    - -
    -
    - -

    ◆ ETH_MMCTIR_TGFSCS_Pos

    - -
    -
    - - - - -
    #define ETH_MMCTIR_TGFSCS_Pos   (14U)
    -
    - -
    -
    - -

    ◆ ETH_MMCTIR_TGFSCS_Msk

    - -
    -
    - - - - -
    #define ETH_MMCTIR_TGFSCS_Msk   (0x1UL << ETH_MMCTIR_TGFSCS_Pos)
    -
    -

    0x00004000

    - -
    -
    - -

    ◆ ETH_MMCTIR_TGFSCS

    - -
    -
    - - - - -
    #define ETH_MMCTIR_TGFSCS   ETH_MMCTIR_TGFSCS_Msk /* Set when Tx good single col counter reaches half the maximum value */
    -
    - -
    -
    - -

    ◆ ETH_MMCRIMR_RGUFM_Pos

    - -
    -
    - - - - -
    #define ETH_MMCRIMR_RGUFM_Pos   (17U)
    -
    - -
    -
    - -

    ◆ ETH_MMCRIMR_RGUFM_Msk

    - -
    -
    - - - - -
    #define ETH_MMCRIMR_RGUFM_Msk   (0x1UL << ETH_MMCRIMR_RGUFM_Pos)
    -
    -

    0x00020000

    - -
    -
    - -

    ◆ ETH_MMCRIMR_RGUFM

    - -
    -
    - - - - -
    #define ETH_MMCRIMR_RGUFM   ETH_MMCRIMR_RGUFM_Msk /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */
    -
    - -
    -
    - -

    ◆ ETH_MMCRIMR_RFAEM_Pos

    - -
    -
    - - - - -
    #define ETH_MMCRIMR_RFAEM_Pos   (6U)
    -
    - -
    -
    - -

    ◆ ETH_MMCRIMR_RFAEM_Msk

    - -
    -
    - - - - -
    #define ETH_MMCRIMR_RFAEM_Msk   (0x1UL << ETH_MMCRIMR_RFAEM_Pos)
    -
    -

    0x00000040

    - -
    -
    - -

    ◆ ETH_MMCRIMR_RFAEM

    - -
    -
    - - - - -
    #define ETH_MMCRIMR_RFAEM   ETH_MMCRIMR_RFAEM_Msk /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */
    -
    - -
    -
    - -

    ◆ ETH_MMCRIMR_RFCEM_Pos

    - -
    -
    - - - - -
    #define ETH_MMCRIMR_RFCEM_Pos   (5U)
    -
    - -
    -
    - -

    ◆ ETH_MMCRIMR_RFCEM_Msk

    - -
    -
    - - - - -
    #define ETH_MMCRIMR_RFCEM_Msk   (0x1UL << ETH_MMCRIMR_RFCEM_Pos)
    -
    -

    0x00000020

    - -
    -
    - -

    ◆ ETH_MMCRIMR_RFCEM

    - -
    -
    - - - - -
    #define ETH_MMCRIMR_RFCEM   ETH_MMCRIMR_RFCEM_Msk /* Mask the interrupt when Rx crc error counter reaches half the maximum value */
    -
    - -
    -
    - -

    ◆ ETH_MMCTIMR_TGFM_Pos

    - -
    -
    - - - - -
    #define ETH_MMCTIMR_TGFM_Pos   (21U)
    -
    - -
    -
    - -

    ◆ ETH_MMCTIMR_TGFM_Msk

    - -
    -
    - - - - -
    #define ETH_MMCTIMR_TGFM_Msk   (0x1UL << ETH_MMCTIMR_TGFM_Pos)
    -
    -

    0x00200000

    - -
    -
    - -

    ◆ ETH_MMCTIMR_TGFM

    - -
    -
    - - - - -
    #define ETH_MMCTIMR_TGFM   ETH_MMCTIMR_TGFM_Msk /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */
    -
    - -
    -
    - -

    ◆ ETH_MMCTIMR_TGFMSCM_Pos

    - -
    -
    - - - - -
    #define ETH_MMCTIMR_TGFMSCM_Pos   (15U)
    -
    - -
    -
    - -

    ◆ ETH_MMCTIMR_TGFMSCM_Msk

    - -
    -
    - - - - -
    #define ETH_MMCTIMR_TGFMSCM_Msk   (0x1UL << ETH_MMCTIMR_TGFMSCM_Pos)
    -
    -

    0x00008000

    - -
    -
    - -

    ◆ ETH_MMCTIMR_TGFMSCM

    - -
    -
    - - - - -
    #define ETH_MMCTIMR_TGFMSCM   ETH_MMCTIMR_TGFMSCM_Msk /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */
    -
    - -
    -
    - -

    ◆ ETH_MMCTIMR_TGFSCM_Pos

    - -
    -
    - - - - -
    #define ETH_MMCTIMR_TGFSCM_Pos   (14U)
    -
    - -
    -
    - -

    ◆ ETH_MMCTIMR_TGFSCM_Msk

    - -
    -
    - - - - -
    #define ETH_MMCTIMR_TGFSCM_Msk   (0x1UL << ETH_MMCTIMR_TGFSCM_Pos)
    -
    -

    0x00004000

    - -
    -
    - -

    ◆ ETH_MMCTIMR_TGFSCM

    - -
    -
    - - - - -
    #define ETH_MMCTIMR_TGFSCM   ETH_MMCTIMR_TGFSCM_Msk /* Mask the interrupt when Tx good single col counter reaches half the maximum value */
    -
    - -
    -
    - -

    ◆ ETH_MMCTGFSCCR_TGFSCC_Pos

    - -
    -
    - - - - -
    #define ETH_MMCTGFSCCR_TGFSCC_Pos   (0U)
    -
    - -
    -
    - -

    ◆ ETH_MMCTGFSCCR_TGFSCC_Msk

    - -
    -
    - - - - -
    #define ETH_MMCTGFSCCR_TGFSCC_Msk   (0xFFFFFFFFUL << ETH_MMCTGFSCCR_TGFSCC_Pos)
    -
    -

    0xFFFFFFFF

    - -
    -
    - -

    ◆ ETH_MMCTGFSCCR_TGFSCC

    - -
    -
    - - - - -
    #define ETH_MMCTGFSCCR_TGFSCC   ETH_MMCTGFSCCR_TGFSCC_Msk /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */
    -
    - -
    -
    - -

    ◆ ETH_MMCTGFMSCCR_TGFMSCC_Pos

    - -
    -
    - - - - -
    #define ETH_MMCTGFMSCCR_TGFMSCC_Pos   (0U)
    -
    - -
    -
    - -

    ◆ ETH_MMCTGFMSCCR_TGFMSCC_Msk

    - -
    -
    - - - - -
    #define ETH_MMCTGFMSCCR_TGFMSCC_Msk   (0xFFFFFFFFUL << ETH_MMCTGFMSCCR_TGFMSCC_Pos)
    -
    -

    0xFFFFFFFF

    - -
    -
    - -

    ◆ ETH_MMCTGFMSCCR_TGFMSCC

    - -
    -
    - - - - -
    #define ETH_MMCTGFMSCCR_TGFMSCC   ETH_MMCTGFMSCCR_TGFMSCC_Msk /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */
    -
    - -
    -
    - -

    ◆ ETH_MMCTGFCR_TGFC_Pos

    - -
    -
    - - - - -
    #define ETH_MMCTGFCR_TGFC_Pos   (0U)
    -
    - -
    -
    - -

    ◆ ETH_MMCTGFCR_TGFC_Msk

    - -
    -
    - - - - -
    #define ETH_MMCTGFCR_TGFC_Msk   (0xFFFFFFFFUL << ETH_MMCTGFCR_TGFC_Pos)
    -
    -

    0xFFFFFFFF

    - -
    -
    - -

    ◆ ETH_MMCTGFCR_TGFC

    - -
    -
    - - - - -
    #define ETH_MMCTGFCR_TGFC   ETH_MMCTGFCR_TGFC_Msk /* Number of good frames transmitted. */
    -
    - -
    -
    - -

    ◆ ETH_MMCRFCECR_RFCEC_Pos

    - -
    -
    - - - - -
    #define ETH_MMCRFCECR_RFCEC_Pos   (0U)
    -
    - -
    -
    - -

    ◆ ETH_MMCRFCECR_RFCEC_Msk

    - -
    -
    - - - - -
    #define ETH_MMCRFCECR_RFCEC_Msk   (0xFFFFFFFFUL << ETH_MMCRFCECR_RFCEC_Pos)
    -
    -

    0xFFFFFFFF

    - -
    -
    - -

    ◆ ETH_MMCRFCECR_RFCEC

    - -
    -
    - - - - -
    #define ETH_MMCRFCECR_RFCEC   ETH_MMCRFCECR_RFCEC_Msk /* Number of frames received with CRC error. */
    -
    - -
    -
    - -

    ◆ ETH_MMCRFAECR_RFAEC_Pos

    - -
    -
    - - - - -
    #define ETH_MMCRFAECR_RFAEC_Pos   (0U)
    -
    - -
    -
    - -

    ◆ ETH_MMCRFAECR_RFAEC_Msk

    - -
    -
    - - - - -
    #define ETH_MMCRFAECR_RFAEC_Msk   (0xFFFFFFFFUL << ETH_MMCRFAECR_RFAEC_Pos)
    -
    -

    0xFFFFFFFF

    - -
    -
    - -

    ◆ ETH_MMCRFAECR_RFAEC

    - -
    -
    - - - - -
    #define ETH_MMCRFAECR_RFAEC   ETH_MMCRFAECR_RFAEC_Msk /* Number of frames received with alignment (dribble) error */
    -
    - -
    -
    - -

    ◆ ETH_MMCRGUFCR_RGUFC_Pos

    - -
    -
    - - - - -
    #define ETH_MMCRGUFCR_RGUFC_Pos   (0U)
    -
    - -
    -
    - -

    ◆ ETH_MMCRGUFCR_RGUFC_Msk

    - -
    -
    - - - - -
    #define ETH_MMCRGUFCR_RGUFC_Msk   (0xFFFFFFFFUL << ETH_MMCRGUFCR_RGUFC_Pos)
    -
    -

    0xFFFFFFFF

    - -
    -
    - -

    ◆ ETH_MMCRGUFCR_RGUFC

    - -
    -
    - - - - -
    #define ETH_MMCRGUFCR_RGUFC   ETH_MMCRGUFCR_RGUFC_Msk /* Number of good unicast frames received. */
    -
    - -
    -
    - -

    ◆ ETH_PTPTSCR_TSPFFMAE_Pos

    - -
    -
    - - - - -
    #define ETH_PTPTSCR_TSPFFMAE_Pos   (18U)
    -
    - -
    -
    - -

    ◆ ETH_PTPTSCR_TSPFFMAE_Msk

    - -
    -
    - - - - -
    #define ETH_PTPTSCR_TSPFFMAE_Msk   (0x1UL << ETH_PTPTSCR_TSPFFMAE_Pos)
    -
    -

    0x00008000

    - -
    -
    - -

    ◆ ETH_PTPTSCR_TSPFFMAE

    - -
    -
    - - - - -
    #define ETH_PTPTSCR_TSPFFMAE   ETH_PTPTSCR_TSPFFMAE_Msk /* Time stamp PTP frame filtering MAC address enable */
    -
    - -
    -
    - -

    ◆ ETH_PTPTSCR_TSCNT_Pos

    - -
    -
    - - - - -
    #define ETH_PTPTSCR_TSCNT_Pos   (16U)
    -
    - -
    -
    - -

    ◆ ETH_PTPTSCR_TSCNT_Msk

    - -
    -
    - - - - -
    #define ETH_PTPTSCR_TSCNT_Msk   (0x3UL << ETH_PTPTSCR_TSCNT_Pos)
    -
    -

    0x00030000

    - -
    -
    - -

    ◆ ETH_PTPTSCR_TSCNT

    - -
    -
    - - - - -
    #define ETH_PTPTSCR_TSCNT   ETH_PTPTSCR_TSCNT_Msk /* Time stamp clock node type */
    -
    - -
    -
    - -

    ◆ ETH_PTPTSCR_TSSMRME_Pos

    - -
    -
    - - - - -
    #define ETH_PTPTSCR_TSSMRME_Pos   (15U)
    -
    - -
    -
    - -

    ◆ ETH_PTPTSCR_TSSMRME_Msk

    - -
    -
    - - - - -
    #define ETH_PTPTSCR_TSSMRME_Msk   (0x1UL << ETH_PTPTSCR_TSSMRME_Pos)
    -
    -

    0x00008000

    - -
    -
    - -

    ◆ ETH_PTPTSCR_TSSMRME

    - -
    -
    - - - - -
    #define ETH_PTPTSCR_TSSMRME   ETH_PTPTSCR_TSSMRME_Msk /* Time stamp snapshot for message relevant to master enable */
    -
    - -
    -
    - -

    ◆ ETH_PTPTSCR_TSSEME_Pos

    - -
    -
    - - - - -
    #define ETH_PTPTSCR_TSSEME_Pos   (14U)
    -
    - -
    -
    - -

    ◆ ETH_PTPTSCR_TSSEME_Msk

    - -
    -
    - - - - -
    #define ETH_PTPTSCR_TSSEME_Msk   (0x1UL << ETH_PTPTSCR_TSSEME_Pos)
    -
    -

    0x00004000

    - -
    -
    - -

    ◆ ETH_PTPTSCR_TSSEME

    - -
    -
    - - - - -
    #define ETH_PTPTSCR_TSSEME   ETH_PTPTSCR_TSSEME_Msk /* Time stamp snapshot for event message enable */
    -
    - -
    -
    - -

    ◆ ETH_PTPTSCR_TSSIPV4FE_Pos

    - -
    -
    - - - - -
    #define ETH_PTPTSCR_TSSIPV4FE_Pos   (13U)
    -
    - -
    -
    - -

    ◆ ETH_PTPTSCR_TSSIPV4FE_Msk

    - -
    -
    - - - - -
    #define ETH_PTPTSCR_TSSIPV4FE_Msk   (0x1UL << ETH_PTPTSCR_TSSIPV4FE_Pos)
    -
    -

    0x00002000

    - -
    -
    - -

    ◆ ETH_PTPTSCR_TSSIPV4FE

    - -
    -
    - - - - -
    #define ETH_PTPTSCR_TSSIPV4FE   ETH_PTPTSCR_TSSIPV4FE_Msk /* Time stamp snapshot for IPv4 frames enable */
    -
    - -
    -
    - -

    ◆ ETH_PTPTSCR_TSSIPV6FE_Pos

    - -
    -
    - - - - -
    #define ETH_PTPTSCR_TSSIPV6FE_Pos   (12U)
    -
    - -
    -
    - -

    ◆ ETH_PTPTSCR_TSSIPV6FE_Msk

    - -
    -
    - - - - -
    #define ETH_PTPTSCR_TSSIPV6FE_Msk   (0x1UL << ETH_PTPTSCR_TSSIPV6FE_Pos)
    -
    -

    0x00001000

    - -
    -
    - -

    ◆ ETH_PTPTSCR_TSSIPV6FE

    - -
    -
    - - - - -
    #define ETH_PTPTSCR_TSSIPV6FE   ETH_PTPTSCR_TSSIPV6FE_Msk /* Time stamp snapshot for IPv6 frames enable */
    -
    - -
    -
    - -

    ◆ ETH_PTPTSCR_TSSPTPOEFE_Pos

    - -
    -
    - - - - -
    #define ETH_PTPTSCR_TSSPTPOEFE_Pos   (11U)
    -
    - -
    -
    - -

    ◆ ETH_PTPTSCR_TSSPTPOEFE_Msk

    - -
    -
    - - - - -
    #define ETH_PTPTSCR_TSSPTPOEFE_Msk   (0x1UL << ETH_PTPTSCR_TSSPTPOEFE_Pos)
    -
    -

    0x00000800

    - -
    -
    - -

    ◆ ETH_PTPTSCR_TSSPTPOEFE

    - -
    -
    - - - - -
    #define ETH_PTPTSCR_TSSPTPOEFE   ETH_PTPTSCR_TSSPTPOEFE_Msk /* Time stamp snapshot for PTP over ethernet frames enable */
    -
    - -
    -
    - -

    ◆ ETH_PTPTSCR_TSPTPPSV2E_Pos

    - -
    -
    - - - - -
    #define ETH_PTPTSCR_TSPTPPSV2E_Pos   (10U)
    -
    - -
    -
    - -

    ◆ ETH_PTPTSCR_TSPTPPSV2E_Msk

    - -
    -
    - - - - -
    #define ETH_PTPTSCR_TSPTPPSV2E_Msk   (0x1UL << ETH_PTPTSCR_TSPTPPSV2E_Pos)
    -
    -

    0x00000400

    - -
    -
    - -

    ◆ ETH_PTPTSCR_TSPTPPSV2E

    - -
    -
    - - - - -
    #define ETH_PTPTSCR_TSPTPPSV2E   ETH_PTPTSCR_TSPTPPSV2E_Msk /* Time stamp PTP packet snooping for version2 format enable */
    -
    - -
    -
    - -

    ◆ ETH_PTPTSCR_TSSSR_Pos

    - -
    -
    - - - - -
    #define ETH_PTPTSCR_TSSSR_Pos   (9U)
    -
    - -
    -
    - -

    ◆ ETH_PTPTSCR_TSSSR_Msk

    - -
    -
    - - - - -
    #define ETH_PTPTSCR_TSSSR_Msk   (0x1UL << ETH_PTPTSCR_TSSSR_Pos)
    -
    -

    0x00000200

    - -
    -
    - -

    ◆ ETH_PTPTSCR_TSSSR

    - -
    -
    - - - - -
    #define ETH_PTPTSCR_TSSSR   ETH_PTPTSCR_TSSSR_Msk /* Time stamp Sub-seconds rollover */
    -
    - -
    -
    - -

    ◆ ETH_PTPTSCR_TSSARFE_Pos

    - -
    -
    - - - - -
    #define ETH_PTPTSCR_TSSARFE_Pos   (8U)
    -
    - -
    -
    - -

    ◆ ETH_PTPTSCR_TSSARFE_Msk

    - -
    -
    - - - - -
    #define ETH_PTPTSCR_TSSARFE_Msk   (0x1UL << ETH_PTPTSCR_TSSARFE_Pos)
    -
    -

    0x00000100

    - -
    -
    - -

    ◆ ETH_PTPTSCR_TSSARFE

    - -
    -
    - - - - -
    #define ETH_PTPTSCR_TSSARFE   ETH_PTPTSCR_TSSARFE_Msk /* Time stamp snapshot for all received frames enable */
    -
    - -
    -
    - -

    ◆ ETH_PTPTSCR_TSARU_Pos

    - -
    -
    - - - - -
    #define ETH_PTPTSCR_TSARU_Pos   (5U)
    -
    - -
    -
    - -

    ◆ ETH_PTPTSCR_TSARU_Msk

    - -
    -
    - - - - -
    #define ETH_PTPTSCR_TSARU_Msk   (0x1UL << ETH_PTPTSCR_TSARU_Pos)
    -
    -

    0x00000020

    - -
    -
    - -

    ◆ ETH_PTPTSCR_TSARU

    - -
    -
    - - - - -
    #define ETH_PTPTSCR_TSARU   ETH_PTPTSCR_TSARU_Msk /* Addend register update */
    -
    - -
    -
    - -

    ◆ ETH_PTPTSCR_TSITE_Pos

    - -
    -
    - - - - -
    #define ETH_PTPTSCR_TSITE_Pos   (4U)
    -
    - -
    -
    - -

    ◆ ETH_PTPTSCR_TSITE_Msk

    - -
    -
    - - - - -
    #define ETH_PTPTSCR_TSITE_Msk   (0x1UL << ETH_PTPTSCR_TSITE_Pos)
    -
    -

    0x00000010

    - -
    -
    - -

    ◆ ETH_PTPTSCR_TSITE

    - -
    -
    - - - - -
    #define ETH_PTPTSCR_TSITE   ETH_PTPTSCR_TSITE_Msk /* Time stamp interrupt trigger enable */
    -
    - -
    -
    - -

    ◆ ETH_PTPTSCR_TSSTU_Pos

    - -
    -
    - - - - -
    #define ETH_PTPTSCR_TSSTU_Pos   (3U)
    -
    - -
    -
    - -

    ◆ ETH_PTPTSCR_TSSTU_Msk

    - -
    -
    - - - - -
    #define ETH_PTPTSCR_TSSTU_Msk   (0x1UL << ETH_PTPTSCR_TSSTU_Pos)
    -
    -

    0x00000008

    - -
    -
    - -

    ◆ ETH_PTPTSCR_TSSTU

    - -
    -
    - - - - -
    #define ETH_PTPTSCR_TSSTU   ETH_PTPTSCR_TSSTU_Msk /* Time stamp update */
    -
    - -
    -
    - -

    ◆ ETH_PTPTSCR_TSSTI_Pos

    - -
    -
    - - - - -
    #define ETH_PTPTSCR_TSSTI_Pos   (2U)
    -
    - -
    -
    - -

    ◆ ETH_PTPTSCR_TSSTI_Msk

    - -
    -
    - - - - -
    #define ETH_PTPTSCR_TSSTI_Msk   (0x1UL << ETH_PTPTSCR_TSSTI_Pos)
    -
    -

    0x00000004

    - -
    -
    - -

    ◆ ETH_PTPTSCR_TSSTI

    - -
    -
    - - - - -
    #define ETH_PTPTSCR_TSSTI   ETH_PTPTSCR_TSSTI_Msk /* Time stamp initialize */
    -
    - -
    -
    - -

    ◆ ETH_PTPTSCR_TSFCU_Pos

    - -
    -
    - - - - -
    #define ETH_PTPTSCR_TSFCU_Pos   (1U)
    -
    - -
    -
    - -

    ◆ ETH_PTPTSCR_TSFCU_Msk

    - -
    -
    - - - - -
    #define ETH_PTPTSCR_TSFCU_Msk   (0x1UL << ETH_PTPTSCR_TSFCU_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ ETH_PTPTSCR_TSFCU

    - -
    -
    - - - - -
    #define ETH_PTPTSCR_TSFCU   ETH_PTPTSCR_TSFCU_Msk /* Time stamp fine or coarse update */
    -
    - -
    -
    - -

    ◆ ETH_PTPTSCR_TSE_Pos

    - -
    -
    - - - - -
    #define ETH_PTPTSCR_TSE_Pos   (0U)
    -
    - -
    -
    - -

    ◆ ETH_PTPTSCR_TSE_Msk

    - -
    -
    - - - - -
    #define ETH_PTPTSCR_TSE_Msk   (0x1UL << ETH_PTPTSCR_TSE_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ ETH_PTPTSCR_TSE

    - -
    -
    - - - - -
    #define ETH_PTPTSCR_TSE   ETH_PTPTSCR_TSE_Msk /* Time stamp enable */
    -
    - -
    -
    - -

    ◆ ETH_PTPSSIR_STSSI_Pos

    - -
    -
    - - - - -
    #define ETH_PTPSSIR_STSSI_Pos   (0U)
    -
    - -
    -
    - -

    ◆ ETH_PTPSSIR_STSSI_Msk

    - -
    -
    - - - - -
    #define ETH_PTPSSIR_STSSI_Msk   (0xFFUL << ETH_PTPSSIR_STSSI_Pos)
    -
    -

    0x000000FF

    - -
    -
    - -

    ◆ ETH_PTPSSIR_STSSI

    - -
    -
    - - - - -
    #define ETH_PTPSSIR_STSSI   ETH_PTPSSIR_STSSI_Msk /* System time Sub-second increment value */
    -
    - -
    -
    - -

    ◆ ETH_PTPTSHR_STS_Pos

    - -
    -
    - - - - -
    #define ETH_PTPTSHR_STS_Pos   (0U)
    -
    - -
    -
    - -

    ◆ ETH_PTPTSHR_STS_Msk

    - -
    -
    - - - - -
    #define ETH_PTPTSHR_STS_Msk   (0xFFFFFFFFUL << ETH_PTPTSHR_STS_Pos)
    -
    -

    0xFFFFFFFF

    - -
    -
    - -

    ◆ ETH_PTPTSHR_STS

    - -
    -
    - - - - -
    #define ETH_PTPTSHR_STS   ETH_PTPTSHR_STS_Msk /* System Time second */
    -
    - -
    -
    - -

    ◆ ETH_PTPTSLR_STPNS_Pos

    - -
    -
    - - - - -
    #define ETH_PTPTSLR_STPNS_Pos   (31U)
    -
    - -
    -
    - -

    ◆ ETH_PTPTSLR_STPNS_Msk

    - -
    -
    - - - - -
    #define ETH_PTPTSLR_STPNS_Msk   (0x1UL << ETH_PTPTSLR_STPNS_Pos)
    -
    -

    0x80000000

    - -
    -
    - -

    ◆ ETH_PTPTSLR_STPNS

    - -
    -
    - - - - -
    #define ETH_PTPTSLR_STPNS   ETH_PTPTSLR_STPNS_Msk /* System Time Positive or negative time */
    -
    - -
    -
    - -

    ◆ ETH_PTPTSLR_STSS_Pos

    - -
    -
    - - - - -
    #define ETH_PTPTSLR_STSS_Pos   (0U)
    -
    - -
    -
    - -

    ◆ ETH_PTPTSLR_STSS_Msk

    - -
    -
    - - - - -
    #define ETH_PTPTSLR_STSS_Msk   (0x7FFFFFFFUL << ETH_PTPTSLR_STSS_Pos)
    -
    -

    0x7FFFFFFF

    - -
    -
    - -

    ◆ ETH_PTPTSLR_STSS

    - -
    -
    - - - - -
    #define ETH_PTPTSLR_STSS   ETH_PTPTSLR_STSS_Msk /* System Time sub-seconds */
    -
    - -
    -
    - -

    ◆ ETH_PTPTSHUR_TSUS_Pos

    - -
    -
    - - - - -
    #define ETH_PTPTSHUR_TSUS_Pos   (0U)
    -
    - -
    -
    - -

    ◆ ETH_PTPTSHUR_TSUS_Msk

    - -
    -
    - - - - -
    #define ETH_PTPTSHUR_TSUS_Msk   (0xFFFFFFFFUL << ETH_PTPTSHUR_TSUS_Pos)
    -
    -

    0xFFFFFFFF

    - -
    -
    - -

    ◆ ETH_PTPTSHUR_TSUS

    - -
    -
    - - - - -
    #define ETH_PTPTSHUR_TSUS   ETH_PTPTSHUR_TSUS_Msk /* Time stamp update seconds */
    -
    - -
    -
    - -

    ◆ ETH_PTPTSLUR_TSUPNS_Pos

    - -
    -
    - - - - -
    #define ETH_PTPTSLUR_TSUPNS_Pos   (31U)
    -
    - -
    -
    - -

    ◆ ETH_PTPTSLUR_TSUPNS_Msk

    - -
    -
    - - - - -
    #define ETH_PTPTSLUR_TSUPNS_Msk   (0x1UL << ETH_PTPTSLUR_TSUPNS_Pos)
    -
    -

    0x80000000

    - -
    -
    - -

    ◆ ETH_PTPTSLUR_TSUPNS

    - -
    -
    - - - - -
    #define ETH_PTPTSLUR_TSUPNS   ETH_PTPTSLUR_TSUPNS_Msk /* Time stamp update Positive or negative time */
    -
    - -
    -
    - -

    ◆ ETH_PTPTSLUR_TSUSS_Pos

    - -
    -
    - - - - -
    #define ETH_PTPTSLUR_TSUSS_Pos   (0U)
    -
    - -
    -
    - -

    ◆ ETH_PTPTSLUR_TSUSS_Msk

    - -
    -
    - - - - -
    #define ETH_PTPTSLUR_TSUSS_Msk   (0x7FFFFFFFUL << ETH_PTPTSLUR_TSUSS_Pos)
    -
    -

    0x7FFFFFFF

    - -
    -
    - -

    ◆ ETH_PTPTSLUR_TSUSS

    - -
    -
    - - - - -
    #define ETH_PTPTSLUR_TSUSS   ETH_PTPTSLUR_TSUSS_Msk /* Time stamp update sub-seconds */
    -
    - -
    -
    - -

    ◆ ETH_PTPTSAR_TSA_Pos

    - -
    -
    - - - - -
    #define ETH_PTPTSAR_TSA_Pos   (0U)
    -
    - -
    -
    - -

    ◆ ETH_PTPTSAR_TSA_Msk

    - -
    -
    - - - - -
    #define ETH_PTPTSAR_TSA_Msk   (0xFFFFFFFFUL << ETH_PTPTSAR_TSA_Pos)
    -
    -

    0xFFFFFFFF

    - -
    -
    - -

    ◆ ETH_PTPTSAR_TSA

    - -
    -
    - - - - -
    #define ETH_PTPTSAR_TSA   ETH_PTPTSAR_TSA_Msk /* Time stamp addend */
    -
    - -
    -
    - -

    ◆ ETH_PTPTTHR_TTSH_Pos

    - -
    -
    - - - - -
    #define ETH_PTPTTHR_TTSH_Pos   (0U)
    -
    - -
    -
    - -

    ◆ ETH_PTPTTHR_TTSH_Msk

    - -
    -
    - - - - -
    #define ETH_PTPTTHR_TTSH_Msk   (0xFFFFFFFFUL << ETH_PTPTTHR_TTSH_Pos)
    -
    -

    0xFFFFFFFF

    - -
    -
    - -

    ◆ ETH_PTPTTHR_TTSH

    - -
    -
    - - - - -
    #define ETH_PTPTTHR_TTSH   ETH_PTPTTHR_TTSH_Msk /* Target time stamp high */
    -
    - -
    -
    - -

    ◆ ETH_PTPTTLR_TTSL_Pos

    - -
    -
    - - - - -
    #define ETH_PTPTTLR_TTSL_Pos   (0U)
    -
    - -
    -
    - -

    ◆ ETH_PTPTTLR_TTSL_Msk

    - -
    -
    - - - - -
    #define ETH_PTPTTLR_TTSL_Msk   (0xFFFFFFFFUL << ETH_PTPTTLR_TTSL_Pos)
    -
    -

    0xFFFFFFFF

    - -
    -
    - -

    ◆ ETH_PTPTTLR_TTSL

    - -
    -
    - - - - -
    #define ETH_PTPTTLR_TTSL   ETH_PTPTTLR_TTSL_Msk /* Target time stamp low */
    -
    - -
    -
    - -

    ◆ ETH_PTPTSSR_TSTTR_Pos

    - -
    -
    - - - - -
    #define ETH_PTPTSSR_TSTTR_Pos   (5U)
    -
    - -
    -
    - -

    ◆ ETH_PTPTSSR_TSTTR_Msk

    - -
    -
    - - - - -
    #define ETH_PTPTSSR_TSTTR_Msk   (0x1UL << ETH_PTPTSSR_TSTTR_Pos)
    -
    -

    0x00000020

    - -
    -
    - -

    ◆ ETH_PTPTSSR_TSTTR

    - -
    -
    - - - - -
    #define ETH_PTPTSSR_TSTTR   ETH_PTPTSSR_TSTTR_Msk /* Time stamp target time reached */
    -
    - -
    -
    - -

    ◆ ETH_PTPTSSR_TSSO_Pos

    - -
    -
    - - - - -
    #define ETH_PTPTSSR_TSSO_Pos   (4U)
    -
    - -
    -
    - -

    ◆ ETH_PTPTSSR_TSSO_Msk

    - -
    -
    - - - - -
    #define ETH_PTPTSSR_TSSO_Msk   (0x1UL << ETH_PTPTSSR_TSSO_Pos)
    -
    -

    0x00000010

    - -
    -
    - -

    ◆ ETH_PTPTSSR_TSSO

    - -
    -
    - - - - -
    #define ETH_PTPTSSR_TSSO   ETH_PTPTSSR_TSSO_Msk /* Time stamp seconds overflow */
    -
    - -
    -
    - -

    ◆ ETH_DMABMR_MB_Pos

    - -
    -
    - - - - -
    #define ETH_DMABMR_MB_Pos   (26U)
    -
    - -
    -
    - -

    ◆ ETH_DMABMR_MB_Msk

    - -
    -
    - - - - -
    #define ETH_DMABMR_MB_Msk   (0x1UL << ETH_DMABMR_MB_Pos)
    -
    -

    0x04000000

    - -
    -
    - -

    ◆ ETH_DMABMR_MB

    - -
    -
    - - - - -
    #define ETH_DMABMR_MB   ETH_DMABMR_MB_Msk /* Mixed Burst */
    -
    - -
    -
    - -

    ◆ ETH_DMABMR_AAB_Pos

    - -
    -
    - - - - -
    #define ETH_DMABMR_AAB_Pos   (25U)
    -
    - -
    -
    - -

    ◆ ETH_DMABMR_AAB_Msk

    - -
    -
    - - - - -
    #define ETH_DMABMR_AAB_Msk   (0x1UL << ETH_DMABMR_AAB_Pos)
    -
    -

    0x02000000

    - -
    -
    - -

    ◆ ETH_DMABMR_AAB

    - -
    -
    - - - - -
    #define ETH_DMABMR_AAB   ETH_DMABMR_AAB_Msk /* Address-Aligned beats */
    -
    - -
    -
    - -

    ◆ ETH_DMABMR_FPM_Pos

    - -
    -
    - - - - -
    #define ETH_DMABMR_FPM_Pos   (24U)
    -
    - -
    -
    - -

    ◆ ETH_DMABMR_FPM_Msk

    - -
    -
    - - - - -
    #define ETH_DMABMR_FPM_Msk   (0x1UL << ETH_DMABMR_FPM_Pos)
    -
    -

    0x01000000

    - -
    -
    - -

    ◆ ETH_DMABMR_FPM

    - -
    -
    - - - - -
    #define ETH_DMABMR_FPM   ETH_DMABMR_FPM_Msk /* 4xPBL mode */
    -
    - -
    -
    - -

    ◆ ETH_DMABMR_USP_Pos

    - -
    -
    - - - - -
    #define ETH_DMABMR_USP_Pos   (23U)
    -
    - -
    -
    - -

    ◆ ETH_DMABMR_USP_Msk

    - -
    -
    - - - - -
    #define ETH_DMABMR_USP_Msk   (0x1UL << ETH_DMABMR_USP_Pos)
    -
    -

    0x00800000

    - -
    -
    - -

    ◆ ETH_DMABMR_USP

    - -
    -
    - - - - -
    #define ETH_DMABMR_USP   ETH_DMABMR_USP_Msk /* Use separate PBL */
    -
    - -
    -
    - -

    ◆ ETH_DMABMR_RDP_Pos

    - -
    -
    - - - - -
    #define ETH_DMABMR_RDP_Pos   (17U)
    -
    - -
    -
    - -

    ◆ ETH_DMABMR_RDP_Msk

    - -
    -
    - - - - -
    #define ETH_DMABMR_RDP_Msk   (0x3FUL << ETH_DMABMR_RDP_Pos)
    -
    -

    0x007E0000

    - -
    -
    - -

    ◆ ETH_DMABMR_RDP

    - -
    -
    - - - - -
    #define ETH_DMABMR_RDP   ETH_DMABMR_RDP_Msk /* RxDMA PBL */
    -
    - -
    -
    - -

    ◆ ETH_DMABMR_RDP_1Beat

    - -
    -
    - - - - -
    #define ETH_DMABMR_RDP_1Beat   0x00020000U /* maximum number of beats to be transferred in one RxDMA transaction is 1 */
    -
    - -
    -
    - -

    ◆ ETH_DMABMR_RDP_2Beat

    - -
    -
    - - - - -
    #define ETH_DMABMR_RDP_2Beat   0x00040000U /* maximum number of beats to be transferred in one RxDMA transaction is 2 */
    -
    - -
    -
    - -

    ◆ ETH_DMABMR_RDP_4Beat

    - -
    -
    - - - - -
    #define ETH_DMABMR_RDP_4Beat   0x00080000U /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
    -
    - -
    -
    - -

    ◆ ETH_DMABMR_RDP_8Beat

    - -
    -
    - - - - -
    #define ETH_DMABMR_RDP_8Beat   0x00100000U /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
    -
    - -
    -
    - -

    ◆ ETH_DMABMR_RDP_16Beat

    - -
    -
    - - - - -
    #define ETH_DMABMR_RDP_16Beat   0x00200000U /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
    -
    - -
    -
    - -

    ◆ ETH_DMABMR_RDP_32Beat

    - -
    -
    - - - - -
    #define ETH_DMABMR_RDP_32Beat   0x00400000U /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
    -
    - -
    -
    - -

    ◆ ETH_DMABMR_RDP_4xPBL_4Beat

    - -
    -
    - - - - -
    #define ETH_DMABMR_RDP_4xPBL_4Beat   0x01020000U /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
    -
    - -
    -
    - -

    ◆ ETH_DMABMR_RDP_4xPBL_8Beat

    - -
    -
    - - - - -
    #define ETH_DMABMR_RDP_4xPBL_8Beat   0x01040000U /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
    -
    - -
    -
    - -

    ◆ ETH_DMABMR_RDP_4xPBL_16Beat

    - -
    -
    - - - - -
    #define ETH_DMABMR_RDP_4xPBL_16Beat   0x01080000U /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
    -
    - -
    -
    - -

    ◆ ETH_DMABMR_RDP_4xPBL_32Beat

    - -
    -
    - - - - -
    #define ETH_DMABMR_RDP_4xPBL_32Beat   0x01100000U /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
    -
    - -
    -
    - -

    ◆ ETH_DMABMR_RDP_4xPBL_64Beat

    - -
    -
    - - - - -
    #define ETH_DMABMR_RDP_4xPBL_64Beat   0x01200000U /* maximum number of beats to be transferred in one RxDMA transaction is 64 */
    -
    - -
    -
    - -

    ◆ ETH_DMABMR_RDP_4xPBL_128Beat

    - -
    -
    - - - - -
    #define ETH_DMABMR_RDP_4xPBL_128Beat   0x01400000U /* maximum number of beats to be transferred in one RxDMA transaction is 128 */
    -
    - -
    -
    - -

    ◆ ETH_DMABMR_FB_Pos

    - -
    -
    - - - - -
    #define ETH_DMABMR_FB_Pos   (16U)
    -
    - -
    -
    - -

    ◆ ETH_DMABMR_FB_Msk

    - -
    -
    - - - - -
    #define ETH_DMABMR_FB_Msk   (0x1UL << ETH_DMABMR_FB_Pos)
    -
    -

    0x00010000

    - -
    -
    - -

    ◆ ETH_DMABMR_FB

    - -
    -
    - - - - -
    #define ETH_DMABMR_FB   ETH_DMABMR_FB_Msk /* Fixed Burst */
    -
    - -
    -
    - -

    ◆ ETH_DMABMR_RTPR_Pos

    - -
    -
    - - - - -
    #define ETH_DMABMR_RTPR_Pos   (14U)
    -
    - -
    -
    - -

    ◆ ETH_DMABMR_RTPR_Msk

    - -
    -
    - - - - -
    #define ETH_DMABMR_RTPR_Msk   (0x3UL << ETH_DMABMR_RTPR_Pos)
    -
    -

    0x0000C000

    - -
    -
    - -

    ◆ ETH_DMABMR_RTPR

    - -
    -
    - - - - -
    #define ETH_DMABMR_RTPR   ETH_DMABMR_RTPR_Msk /* Rx Tx priority ratio */
    -
    - -
    -
    - -

    ◆ ETH_DMABMR_RTPR_1_1

    - -
    -
    - - - - -
    #define ETH_DMABMR_RTPR_1_1   0x00000000U /* Rx Tx priority ratio */
    -
    - -
    -
    - -

    ◆ ETH_DMABMR_RTPR_2_1

    - -
    -
    - - - - -
    #define ETH_DMABMR_RTPR_2_1   0x00004000U /* Rx Tx priority ratio */
    -
    - -
    -
    - -

    ◆ ETH_DMABMR_RTPR_3_1

    - -
    -
    - - - - -
    #define ETH_DMABMR_RTPR_3_1   0x00008000U /* Rx Tx priority ratio */
    -
    - -
    -
    - -

    ◆ ETH_DMABMR_RTPR_4_1

    - -
    -
    - - - - -
    #define ETH_DMABMR_RTPR_4_1   0x0000C000U /* Rx Tx priority ratio */
    -
    - -
    -
    - -

    ◆ ETH_DMABMR_PBL_Pos

    - -
    -
    - - - - -
    #define ETH_DMABMR_PBL_Pos   (8U)
    -
    - -
    -
    - -

    ◆ ETH_DMABMR_PBL_Msk

    - -
    -
    - - - - -
    #define ETH_DMABMR_PBL_Msk   (0x3FUL << ETH_DMABMR_PBL_Pos)
    -
    -

    0x00003F00

    - -
    -
    - -

    ◆ ETH_DMABMR_PBL

    - -
    -
    - - - - -
    #define ETH_DMABMR_PBL   ETH_DMABMR_PBL_Msk /* Programmable burst length */
    -
    - -
    -
    - -

    ◆ ETH_DMABMR_PBL_1Beat

    - -
    -
    - - - - -
    #define ETH_DMABMR_PBL_1Beat   0x00000100U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
    -
    - -
    -
    - -

    ◆ ETH_DMABMR_PBL_2Beat

    - -
    -
    - - - - -
    #define ETH_DMABMR_PBL_2Beat   0x00000200U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
    -
    - -
    -
    - -

    ◆ ETH_DMABMR_PBL_4Beat

    - -
    -
    - - - - -
    #define ETH_DMABMR_PBL_4Beat   0x00000400U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
    -
    - -
    -
    - -

    ◆ ETH_DMABMR_PBL_8Beat

    - -
    -
    - - - - -
    #define ETH_DMABMR_PBL_8Beat   0x00000800U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
    -
    - -
    -
    - -

    ◆ ETH_DMABMR_PBL_16Beat

    - -
    -
    - - - - -
    #define ETH_DMABMR_PBL_16Beat   0x00001000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
    -
    - -
    -
    - -

    ◆ ETH_DMABMR_PBL_32Beat

    - -
    -
    - - - - -
    #define ETH_DMABMR_PBL_32Beat   0x00002000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
    -
    - -
    -
    - -

    ◆ ETH_DMABMR_PBL_4xPBL_4Beat

    - -
    -
    - - - - -
    #define ETH_DMABMR_PBL_4xPBL_4Beat   0x01000100U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
    -
    - -
    -
    - -

    ◆ ETH_DMABMR_PBL_4xPBL_8Beat

    - -
    -
    - - - - -
    #define ETH_DMABMR_PBL_4xPBL_8Beat   0x01000200U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
    -
    - -
    -
    - -

    ◆ ETH_DMABMR_PBL_4xPBL_16Beat

    - -
    -
    - - - - -
    #define ETH_DMABMR_PBL_4xPBL_16Beat   0x01000400U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
    -
    - -
    -
    - -

    ◆ ETH_DMABMR_PBL_4xPBL_32Beat

    - -
    -
    - - - - -
    #define ETH_DMABMR_PBL_4xPBL_32Beat   0x01000800U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
    -
    - -
    -
    - -

    ◆ ETH_DMABMR_PBL_4xPBL_64Beat

    - -
    -
    - - - - -
    #define ETH_DMABMR_PBL_4xPBL_64Beat   0x01001000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
    -
    - -
    -
    - -

    ◆ ETH_DMABMR_PBL_4xPBL_128Beat

    - -
    -
    - - - - -
    #define ETH_DMABMR_PBL_4xPBL_128Beat   0x01002000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
    -
    - -
    -
    - -

    ◆ ETH_DMABMR_EDE_Pos

    - -
    -
    - - - - -
    #define ETH_DMABMR_EDE_Pos   (7U)
    -
    - -
    -
    - -

    ◆ ETH_DMABMR_EDE_Msk

    - -
    -
    - - - - -
    #define ETH_DMABMR_EDE_Msk   (0x1UL << ETH_DMABMR_EDE_Pos)
    -
    -

    0x00000080

    - -
    -
    - -

    ◆ ETH_DMABMR_EDE

    - -
    -
    - - - - -
    #define ETH_DMABMR_EDE   ETH_DMABMR_EDE_Msk /* Enhanced Descriptor Enable */
    -
    - -
    -
    - -

    ◆ ETH_DMABMR_DSL_Pos

    - -
    -
    - - - - -
    #define ETH_DMABMR_DSL_Pos   (2U)
    -
    - -
    -
    - -

    ◆ ETH_DMABMR_DSL_Msk

    - -
    -
    - - - - -
    #define ETH_DMABMR_DSL_Msk   (0x1FUL << ETH_DMABMR_DSL_Pos)
    -
    -

    0x0000007C

    - -
    -
    - -

    ◆ ETH_DMABMR_DSL

    - -
    -
    - - - - -
    #define ETH_DMABMR_DSL   ETH_DMABMR_DSL_Msk /* Descriptor Skip Length */
    -
    - -
    -
    - -

    ◆ ETH_DMABMR_DA_Pos

    - -
    -
    - - - - -
    #define ETH_DMABMR_DA_Pos   (1U)
    -
    - -
    -
    - -

    ◆ ETH_DMABMR_DA_Msk

    - -
    -
    - - - - -
    #define ETH_DMABMR_DA_Msk   (0x1UL << ETH_DMABMR_DA_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ ETH_DMABMR_DA

    - -
    -
    - - - - -
    #define ETH_DMABMR_DA   ETH_DMABMR_DA_Msk /* DMA arbitration scheme */
    -
    - -
    -
    - -

    ◆ ETH_DMABMR_SR_Pos

    - -
    -
    - - - - -
    #define ETH_DMABMR_SR_Pos   (0U)
    -
    - -
    -
    - -

    ◆ ETH_DMABMR_SR_Msk

    - -
    -
    - - - - -
    #define ETH_DMABMR_SR_Msk   (0x1UL << ETH_DMABMR_SR_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ ETH_DMABMR_SR

    - -
    -
    - - - - -
    #define ETH_DMABMR_SR   ETH_DMABMR_SR_Msk /* Software reset */
    -
    - -
    -
    - -

    ◆ ETH_DMATPDR_TPD_Pos

    - -
    -
    - - - - -
    #define ETH_DMATPDR_TPD_Pos   (0U)
    -
    - -
    -
    - -

    ◆ ETH_DMATPDR_TPD_Msk

    - -
    -
    - - - - -
    #define ETH_DMATPDR_TPD_Msk   (0xFFFFFFFFUL << ETH_DMATPDR_TPD_Pos)
    -
    -

    0xFFFFFFFF

    - -
    -
    - -

    ◆ ETH_DMATPDR_TPD

    - -
    -
    - - - - -
    #define ETH_DMATPDR_TPD   ETH_DMATPDR_TPD_Msk /* Transmit poll demand */
    -
    - -
    -
    - -

    ◆ ETH_DMARPDR_RPD_Pos

    - -
    -
    - - - - -
    #define ETH_DMARPDR_RPD_Pos   (0U)
    -
    - -
    -
    - -

    ◆ ETH_DMARPDR_RPD_Msk

    - -
    -
    - - - - -
    #define ETH_DMARPDR_RPD_Msk   (0xFFFFFFFFUL << ETH_DMARPDR_RPD_Pos)
    -
    -

    0xFFFFFFFF

    - -
    -
    - -

    ◆ ETH_DMARPDR_RPD

    - -
    -
    - - - - -
    #define ETH_DMARPDR_RPD   ETH_DMARPDR_RPD_Msk /* Receive poll demand */
    -
    - -
    -
    - -

    ◆ ETH_DMARDLAR_SRL_Pos

    - -
    -
    - - - - -
    #define ETH_DMARDLAR_SRL_Pos   (0U)
    -
    - -
    -
    - -

    ◆ ETH_DMARDLAR_SRL_Msk

    - -
    -
    - - - - -
    #define ETH_DMARDLAR_SRL_Msk   (0xFFFFFFFFUL << ETH_DMARDLAR_SRL_Pos)
    -
    -

    0xFFFFFFFF

    - -
    -
    - -

    ◆ ETH_DMARDLAR_SRL

    - -
    -
    - - - - -
    #define ETH_DMARDLAR_SRL   ETH_DMARDLAR_SRL_Msk /* Start of receive list */
    -
    - -
    -
    - -

    ◆ ETH_DMATDLAR_STL_Pos

    - -
    -
    - - - - -
    #define ETH_DMATDLAR_STL_Pos   (0U)
    -
    - -
    -
    - -

    ◆ ETH_DMATDLAR_STL_Msk

    - -
    -
    - - - - -
    #define ETH_DMATDLAR_STL_Msk   (0xFFFFFFFFUL << ETH_DMATDLAR_STL_Pos)
    -
    -

    0xFFFFFFFF

    - -
    -
    - -

    ◆ ETH_DMATDLAR_STL

    - -
    -
    - - - - -
    #define ETH_DMATDLAR_STL   ETH_DMATDLAR_STL_Msk /* Start of transmit list */
    -
    - -
    -
    - -

    ◆ ETH_DMASR_TSTS_Pos

    - -
    -
    - - - - -
    #define ETH_DMASR_TSTS_Pos   (29U)
    -
    - -
    -
    - -

    ◆ ETH_DMASR_TSTS_Msk

    - -
    -
    - - - - -
    #define ETH_DMASR_TSTS_Msk   (0x1UL << ETH_DMASR_TSTS_Pos)
    -
    -

    0x20000000

    - -
    -
    - -

    ◆ ETH_DMASR_TSTS

    - -
    -
    - - - - -
    #define ETH_DMASR_TSTS   ETH_DMASR_TSTS_Msk /* Time-stamp trigger status */
    -
    - -
    -
    - -

    ◆ ETH_DMASR_PMTS_Pos

    - -
    -
    - - - - -
    #define ETH_DMASR_PMTS_Pos   (28U)
    -
    - -
    -
    - -

    ◆ ETH_DMASR_PMTS_Msk

    - -
    -
    - - - - -
    #define ETH_DMASR_PMTS_Msk   (0x1UL << ETH_DMASR_PMTS_Pos)
    -
    -

    0x10000000

    - -
    -
    - -

    ◆ ETH_DMASR_PMTS

    - -
    -
    - - - - -
    #define ETH_DMASR_PMTS   ETH_DMASR_PMTS_Msk /* PMT status */
    -
    - -
    -
    - -

    ◆ ETH_DMASR_MMCS_Pos

    - -
    -
    - - - - -
    #define ETH_DMASR_MMCS_Pos   (27U)
    -
    - -
    -
    - -

    ◆ ETH_DMASR_MMCS_Msk

    - -
    -
    - - - - -
    #define ETH_DMASR_MMCS_Msk   (0x1UL << ETH_DMASR_MMCS_Pos)
    -
    -

    0x08000000

    - -
    -
    - -

    ◆ ETH_DMASR_MMCS

    - -
    -
    - - - - -
    #define ETH_DMASR_MMCS   ETH_DMASR_MMCS_Msk /* MMC status */
    -
    - -
    -
    - -

    ◆ ETH_DMASR_EBS_Pos

    - -
    -
    - - - - -
    #define ETH_DMASR_EBS_Pos   (23U)
    -
    - -
    -
    - -

    ◆ ETH_DMASR_EBS_Msk

    - -
    -
    - - - - -
    #define ETH_DMASR_EBS_Msk   (0x7UL << ETH_DMASR_EBS_Pos)
    -
    -

    0x03800000

    - -
    -
    - -

    ◆ ETH_DMASR_EBS

    - -
    -
    - - - - -
    #define ETH_DMASR_EBS   ETH_DMASR_EBS_Msk /* Error bits status */
    -
    - -
    -
    - -

    ◆ ETH_DMASR_EBS_DescAccess_Pos

    - -
    -
    - - - - -
    #define ETH_DMASR_EBS_DescAccess_Pos   (25U)
    -
    - -
    -
    - -

    ◆ ETH_DMASR_EBS_DescAccess_Msk

    - -
    -
    - - - - -
    #define ETH_DMASR_EBS_DescAccess_Msk   (0x1UL << ETH_DMASR_EBS_DescAccess_Pos)
    -
    -

    0x02000000

    - -
    -
    - -

    ◆ ETH_DMASR_EBS_DescAccess

    - -
    -
    - - - - -
    #define ETH_DMASR_EBS_DescAccess   ETH_DMASR_EBS_DescAccess_Msk /* Error bits 0-data buffer, 1-desc. access */
    -
    - -
    -
    - -

    ◆ ETH_DMASR_EBS_ReadTransf_Pos

    - -
    -
    - - - - -
    #define ETH_DMASR_EBS_ReadTransf_Pos   (24U)
    -
    - -
    -
    - -

    ◆ ETH_DMASR_EBS_ReadTransf_Msk

    - -
    -
    - - - - -
    #define ETH_DMASR_EBS_ReadTransf_Msk   (0x1UL << ETH_DMASR_EBS_ReadTransf_Pos)
    -
    -

    0x01000000

    - -
    -
    - -

    ◆ ETH_DMASR_EBS_ReadTransf

    - -
    -
    - - - - -
    #define ETH_DMASR_EBS_ReadTransf   ETH_DMASR_EBS_ReadTransf_Msk /* Error bits 0-write trnsf, 1-read transfr */
    -
    - -
    -
    - -

    ◆ ETH_DMASR_EBS_DataTransfTx_Pos

    - -
    -
    - - - - -
    #define ETH_DMASR_EBS_DataTransfTx_Pos   (23U)
    -
    - -
    -
    - -

    ◆ ETH_DMASR_EBS_DataTransfTx_Msk

    - -
    -
    - - - - -
    #define ETH_DMASR_EBS_DataTransfTx_Msk   (0x1UL << ETH_DMASR_EBS_DataTransfTx_Pos)
    -
    -

    0x00800000

    - -
    -
    - -

    ◆ ETH_DMASR_EBS_DataTransfTx

    - -
    -
    - - - - -
    #define ETH_DMASR_EBS_DataTransfTx   ETH_DMASR_EBS_DataTransfTx_Msk /* Error bits 0-Rx DMA, 1-Tx DMA */
    -
    - -
    -
    - -

    ◆ ETH_DMASR_TPS_Pos

    - -
    -
    - - - - -
    #define ETH_DMASR_TPS_Pos   (20U)
    -
    - -
    -
    - -

    ◆ ETH_DMASR_TPS_Msk

    - -
    -
    - - - - -
    #define ETH_DMASR_TPS_Msk   (0x7UL << ETH_DMASR_TPS_Pos)
    -
    -

    0x00700000

    - -
    -
    - -

    ◆ ETH_DMASR_TPS

    - -
    -
    - - - - -
    #define ETH_DMASR_TPS   ETH_DMASR_TPS_Msk /* Transmit process state */
    -
    - -
    -
    - -

    ◆ ETH_DMASR_TPS_Stopped

    - -
    -
    - - - - -
    #define ETH_DMASR_TPS_Stopped   0x00000000U /* Stopped - Reset or Stop Tx Command issued */
    -
    - -
    -
    - -

    ◆ ETH_DMASR_TPS_Fetching_Pos

    - -
    -
    - - - - -
    #define ETH_DMASR_TPS_Fetching_Pos   (20U)
    -
    - -
    -
    - -

    ◆ ETH_DMASR_TPS_Fetching_Msk

    - -
    -
    - - - - -
    #define ETH_DMASR_TPS_Fetching_Msk   (0x1UL << ETH_DMASR_TPS_Fetching_Pos)
    -
    -

    0x00100000

    - -
    -
    - -

    ◆ ETH_DMASR_TPS_Fetching

    - -
    -
    - - - - -
    #define ETH_DMASR_TPS_Fetching   ETH_DMASR_TPS_Fetching_Msk /* Running - fetching the Tx descriptor */
    -
    - -
    -
    - -

    ◆ ETH_DMASR_TPS_Waiting_Pos

    - -
    -
    - - - - -
    #define ETH_DMASR_TPS_Waiting_Pos   (21U)
    -
    - -
    -
    - -

    ◆ ETH_DMASR_TPS_Waiting_Msk

    - -
    -
    - - - - -
    #define ETH_DMASR_TPS_Waiting_Msk   (0x1UL << ETH_DMASR_TPS_Waiting_Pos)
    -
    -

    0x00200000

    - -
    -
    - -

    ◆ ETH_DMASR_TPS_Waiting

    - -
    -
    - - - - -
    #define ETH_DMASR_TPS_Waiting   ETH_DMASR_TPS_Waiting_Msk /* Running - waiting for status */
    -
    - -
    -
    - -

    ◆ ETH_DMASR_TPS_Reading_Pos

    - -
    -
    - - - - -
    #define ETH_DMASR_TPS_Reading_Pos   (20U)
    -
    - -
    -
    - -

    ◆ ETH_DMASR_TPS_Reading_Msk

    - -
    -
    - - - - -
    #define ETH_DMASR_TPS_Reading_Msk   (0x3UL << ETH_DMASR_TPS_Reading_Pos)
    -
    -

    0x00300000

    - -
    -
    - -

    ◆ ETH_DMASR_TPS_Reading

    - -
    -
    - - - - -
    #define ETH_DMASR_TPS_Reading   ETH_DMASR_TPS_Reading_Msk /* Running - reading the data from host memory */
    -
    - -
    -
    - -

    ◆ ETH_DMASR_TPS_Suspended_Pos

    - -
    -
    - - - - -
    #define ETH_DMASR_TPS_Suspended_Pos   (21U)
    -
    - -
    -
    - -

    ◆ ETH_DMASR_TPS_Suspended_Msk

    - -
    -
    - - - - -
    #define ETH_DMASR_TPS_Suspended_Msk   (0x3UL << ETH_DMASR_TPS_Suspended_Pos)
    -
    -

    0x00600000

    - -
    -
    - -

    ◆ ETH_DMASR_TPS_Suspended

    - -
    -
    - - - - -
    #define ETH_DMASR_TPS_Suspended   ETH_DMASR_TPS_Suspended_Msk /* Suspended - Tx Descriptor unavailable */
    -
    - -
    -
    - -

    ◆ ETH_DMASR_TPS_Closing_Pos

    - -
    -
    - - - - -
    #define ETH_DMASR_TPS_Closing_Pos   (20U)
    -
    - -
    -
    - -

    ◆ ETH_DMASR_TPS_Closing_Msk

    - -
    -
    - - - - -
    #define ETH_DMASR_TPS_Closing_Msk   (0x7UL << ETH_DMASR_TPS_Closing_Pos)
    -
    -

    0x00700000

    - -
    -
    - -

    ◆ ETH_DMASR_TPS_Closing

    - -
    -
    - - - - -
    #define ETH_DMASR_TPS_Closing   ETH_DMASR_TPS_Closing_Msk /* Running - closing Rx descriptor */
    -
    - -
    -
    - -

    ◆ ETH_DMASR_RPS_Pos

    - -
    -
    - - - - -
    #define ETH_DMASR_RPS_Pos   (17U)
    -
    - -
    -
    - -

    ◆ ETH_DMASR_RPS_Msk

    - -
    -
    - - - - -
    #define ETH_DMASR_RPS_Msk   (0x7UL << ETH_DMASR_RPS_Pos)
    -
    -

    0x000E0000

    - -
    -
    - -

    ◆ ETH_DMASR_RPS

    - -
    -
    - - - - -
    #define ETH_DMASR_RPS   ETH_DMASR_RPS_Msk /* Receive process state */
    -
    - -
    -
    - -

    ◆ ETH_DMASR_RPS_Stopped

    - -
    -
    - - - - -
    #define ETH_DMASR_RPS_Stopped   0x00000000U /* Stopped - Reset or Stop Rx Command issued */
    -
    - -
    -
    - -

    ◆ ETH_DMASR_RPS_Fetching_Pos

    - -
    -
    - - - - -
    #define ETH_DMASR_RPS_Fetching_Pos   (17U)
    -
    - -
    -
    - -

    ◆ ETH_DMASR_RPS_Fetching_Msk

    - -
    -
    - - - - -
    #define ETH_DMASR_RPS_Fetching_Msk   (0x1UL << ETH_DMASR_RPS_Fetching_Pos)
    -
    -

    0x00020000

    - -
    -
    - -

    ◆ ETH_DMASR_RPS_Fetching

    - -
    -
    - - - - -
    #define ETH_DMASR_RPS_Fetching   ETH_DMASR_RPS_Fetching_Msk /* Running - fetching the Rx descriptor */
    -
    - -
    -
    - -

    ◆ ETH_DMASR_RPS_Waiting_Pos

    - -
    -
    - - - - -
    #define ETH_DMASR_RPS_Waiting_Pos   (17U)
    -
    - -
    -
    - -

    ◆ ETH_DMASR_RPS_Waiting_Msk

    - -
    -
    - - - - -
    #define ETH_DMASR_RPS_Waiting_Msk   (0x3UL << ETH_DMASR_RPS_Waiting_Pos)
    -
    -

    0x00060000

    - -
    -
    - -

    ◆ ETH_DMASR_RPS_Waiting

    - -
    -
    - - - - -
    #define ETH_DMASR_RPS_Waiting   ETH_DMASR_RPS_Waiting_Msk /* Running - waiting for packet */
    -
    - -
    -
    - -

    ◆ ETH_DMASR_RPS_Suspended_Pos

    - -
    -
    - - - - -
    #define ETH_DMASR_RPS_Suspended_Pos   (19U)
    -
    - -
    -
    - -

    ◆ ETH_DMASR_RPS_Suspended_Msk

    - -
    -
    - - - - -
    #define ETH_DMASR_RPS_Suspended_Msk   (0x1UL << ETH_DMASR_RPS_Suspended_Pos)
    -
    -

    0x00080000

    - -
    -
    - -

    ◆ ETH_DMASR_RPS_Suspended

    - -
    -
    - - - - -
    #define ETH_DMASR_RPS_Suspended   ETH_DMASR_RPS_Suspended_Msk /* Suspended - Rx Descriptor unavailable */
    -
    - -
    -
    - -

    ◆ ETH_DMASR_RPS_Closing_Pos

    - -
    -
    - - - - -
    #define ETH_DMASR_RPS_Closing_Pos   (17U)
    -
    - -
    -
    - -

    ◆ ETH_DMASR_RPS_Closing_Msk

    - -
    -
    - - - - -
    #define ETH_DMASR_RPS_Closing_Msk   (0x5UL << ETH_DMASR_RPS_Closing_Pos)
    -
    -

    0x000A0000

    - -
    -
    - -

    ◆ ETH_DMASR_RPS_Closing

    - -
    -
    - - - - -
    #define ETH_DMASR_RPS_Closing   ETH_DMASR_RPS_Closing_Msk /* Running - closing descriptor */
    -
    - -
    -
    - -

    ◆ ETH_DMASR_RPS_Queuing_Pos

    - -
    -
    - - - - -
    #define ETH_DMASR_RPS_Queuing_Pos   (17U)
    -
    - -
    -
    - -

    ◆ ETH_DMASR_RPS_Queuing_Msk

    - -
    -
    - - - - -
    #define ETH_DMASR_RPS_Queuing_Msk   (0x7UL << ETH_DMASR_RPS_Queuing_Pos)
    -
    -

    0x000E0000

    - -
    -
    - -

    ◆ ETH_DMASR_RPS_Queuing

    - -
    -
    - - - - -
    #define ETH_DMASR_RPS_Queuing   ETH_DMASR_RPS_Queuing_Msk /* Running - queuing the receive frame into host memory */
    -
    - -
    -
    - -

    ◆ ETH_DMASR_NIS_Pos

    - -
    -
    - - - - -
    #define ETH_DMASR_NIS_Pos   (16U)
    -
    - -
    -
    - -

    ◆ ETH_DMASR_NIS_Msk

    - -
    -
    - - - - -
    #define ETH_DMASR_NIS_Msk   (0x1UL << ETH_DMASR_NIS_Pos)
    -
    -

    0x00010000

    - -
    -
    - -

    ◆ ETH_DMASR_NIS

    - -
    -
    - - - - -
    #define ETH_DMASR_NIS   ETH_DMASR_NIS_Msk /* Normal interrupt summary */
    -
    - -
    -
    - -

    ◆ ETH_DMASR_AIS_Pos

    - -
    -
    - - - - -
    #define ETH_DMASR_AIS_Pos   (15U)
    -
    - -
    -
    - -

    ◆ ETH_DMASR_AIS_Msk

    - -
    -
    - - - - -
    #define ETH_DMASR_AIS_Msk   (0x1UL << ETH_DMASR_AIS_Pos)
    -
    -

    0x00008000

    - -
    -
    - -

    ◆ ETH_DMASR_AIS

    - -
    -
    - - - - -
    #define ETH_DMASR_AIS   ETH_DMASR_AIS_Msk /* Abnormal interrupt summary */
    -
    - -
    -
    - -

    ◆ ETH_DMASR_ERS_Pos

    - -
    -
    - - - - -
    #define ETH_DMASR_ERS_Pos   (14U)
    -
    - -
    -
    - -

    ◆ ETH_DMASR_ERS_Msk

    - -
    -
    - - - - -
    #define ETH_DMASR_ERS_Msk   (0x1UL << ETH_DMASR_ERS_Pos)
    -
    -

    0x00004000

    - -
    -
    - -

    ◆ ETH_DMASR_ERS

    - -
    -
    - - - - -
    #define ETH_DMASR_ERS   ETH_DMASR_ERS_Msk /* Early receive status */
    -
    - -
    -
    - -

    ◆ ETH_DMASR_FBES_Pos

    - -
    -
    - - - - -
    #define ETH_DMASR_FBES_Pos   (13U)
    -
    - -
    -
    - -

    ◆ ETH_DMASR_FBES_Msk

    - -
    -
    - - - - -
    #define ETH_DMASR_FBES_Msk   (0x1UL << ETH_DMASR_FBES_Pos)
    -
    -

    0x00002000

    - -
    -
    - -

    ◆ ETH_DMASR_FBES

    - -
    -
    - - - - -
    #define ETH_DMASR_FBES   ETH_DMASR_FBES_Msk /* Fatal bus error status */
    -
    - -
    -
    - -

    ◆ ETH_DMASR_ETS_Pos

    - -
    -
    - - - - -
    #define ETH_DMASR_ETS_Pos   (10U)
    -
    - -
    -
    - -

    ◆ ETH_DMASR_ETS_Msk

    - -
    -
    - - - - -
    #define ETH_DMASR_ETS_Msk   (0x1UL << ETH_DMASR_ETS_Pos)
    -
    -

    0x00000400

    - -
    -
    - -

    ◆ ETH_DMASR_ETS

    - -
    -
    - - - - -
    #define ETH_DMASR_ETS   ETH_DMASR_ETS_Msk /* Early transmit status */
    -
    - -
    -
    - -

    ◆ ETH_DMASR_RWTS_Pos

    - -
    -
    - - - - -
    #define ETH_DMASR_RWTS_Pos   (9U)
    -
    - -
    -
    - -

    ◆ ETH_DMASR_RWTS_Msk

    - -
    -
    - - - - -
    #define ETH_DMASR_RWTS_Msk   (0x1UL << ETH_DMASR_RWTS_Pos)
    -
    -

    0x00000200

    - -
    -
    - -

    ◆ ETH_DMASR_RWTS

    - -
    -
    - - - - -
    #define ETH_DMASR_RWTS   ETH_DMASR_RWTS_Msk /* Receive watchdog timeout status */
    -
    - -
    -
    - -

    ◆ ETH_DMASR_RPSS_Pos

    - -
    -
    - - - - -
    #define ETH_DMASR_RPSS_Pos   (8U)
    -
    - -
    -
    - -

    ◆ ETH_DMASR_RPSS_Msk

    - -
    -
    - - - - -
    #define ETH_DMASR_RPSS_Msk   (0x1UL << ETH_DMASR_RPSS_Pos)
    -
    -

    0x00000100

    - -
    -
    - -

    ◆ ETH_DMASR_RPSS

    - -
    -
    - - - - -
    #define ETH_DMASR_RPSS   ETH_DMASR_RPSS_Msk /* Receive process stopped status */
    -
    - -
    -
    - -

    ◆ ETH_DMASR_RBUS_Pos

    - -
    -
    - - - - -
    #define ETH_DMASR_RBUS_Pos   (7U)
    -
    - -
    -
    - -

    ◆ ETH_DMASR_RBUS_Msk

    - -
    -
    - - - - -
    #define ETH_DMASR_RBUS_Msk   (0x1UL << ETH_DMASR_RBUS_Pos)
    -
    -

    0x00000080

    - -
    -
    - -

    ◆ ETH_DMASR_RBUS

    - -
    -
    - - - - -
    #define ETH_DMASR_RBUS   ETH_DMASR_RBUS_Msk /* Receive buffer unavailable status */
    -
    - -
    -
    - -

    ◆ ETH_DMASR_RS_Pos

    - -
    -
    - - - - -
    #define ETH_DMASR_RS_Pos   (6U)
    -
    - -
    -
    - -

    ◆ ETH_DMASR_RS_Msk

    - -
    -
    - - - - -
    #define ETH_DMASR_RS_Msk   (0x1UL << ETH_DMASR_RS_Pos)
    -
    -

    0x00000040

    - -
    -
    - -

    ◆ ETH_DMASR_RS

    - -
    -
    - - - - -
    #define ETH_DMASR_RS   ETH_DMASR_RS_Msk /* Receive status */
    -
    - -
    -
    - -

    ◆ ETH_DMASR_TUS_Pos

    - -
    -
    - - - - -
    #define ETH_DMASR_TUS_Pos   (5U)
    -
    - -
    -
    - -

    ◆ ETH_DMASR_TUS_Msk

    - -
    -
    - - - - -
    #define ETH_DMASR_TUS_Msk   (0x1UL << ETH_DMASR_TUS_Pos)
    -
    -

    0x00000020

    - -
    -
    - -

    ◆ ETH_DMASR_TUS

    - -
    -
    - - - - -
    #define ETH_DMASR_TUS   ETH_DMASR_TUS_Msk /* Transmit underflow status */
    -
    - -
    -
    - -

    ◆ ETH_DMASR_ROS_Pos

    - -
    -
    - - - - -
    #define ETH_DMASR_ROS_Pos   (4U)
    -
    - -
    -
    - -

    ◆ ETH_DMASR_ROS_Msk

    - -
    -
    - - - - -
    #define ETH_DMASR_ROS_Msk   (0x1UL << ETH_DMASR_ROS_Pos)
    -
    -

    0x00000010

    - -
    -
    - -

    ◆ ETH_DMASR_ROS

    - -
    -
    - - - - -
    #define ETH_DMASR_ROS   ETH_DMASR_ROS_Msk /* Receive overflow status */
    -
    - -
    -
    - -

    ◆ ETH_DMASR_TJTS_Pos

    - -
    -
    - - - - -
    #define ETH_DMASR_TJTS_Pos   (3U)
    -
    - -
    -
    - -

    ◆ ETH_DMASR_TJTS_Msk

    - -
    -
    - - - - -
    #define ETH_DMASR_TJTS_Msk   (0x1UL << ETH_DMASR_TJTS_Pos)
    -
    -

    0x00000008

    - -
    -
    - -

    ◆ ETH_DMASR_TJTS

    - -
    -
    - - - - -
    #define ETH_DMASR_TJTS   ETH_DMASR_TJTS_Msk /* Transmit jabber timeout status */
    -
    - -
    -
    - -

    ◆ ETH_DMASR_TBUS_Pos

    - -
    -
    - - - - -
    #define ETH_DMASR_TBUS_Pos   (2U)
    -
    - -
    -
    - -

    ◆ ETH_DMASR_TBUS_Msk

    - -
    -
    - - - - -
    #define ETH_DMASR_TBUS_Msk   (0x1UL << ETH_DMASR_TBUS_Pos)
    -
    -

    0x00000004

    - -
    -
    - -

    ◆ ETH_DMASR_TBUS

    - -
    -
    - - - - -
    #define ETH_DMASR_TBUS   ETH_DMASR_TBUS_Msk /* Transmit buffer unavailable status */
    -
    - -
    -
    - -

    ◆ ETH_DMASR_TPSS_Pos

    - -
    -
    - - - - -
    #define ETH_DMASR_TPSS_Pos   (1U)
    -
    - -
    -
    - -

    ◆ ETH_DMASR_TPSS_Msk

    - -
    -
    - - - - -
    #define ETH_DMASR_TPSS_Msk   (0x1UL << ETH_DMASR_TPSS_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ ETH_DMASR_TPSS

    - -
    -
    - - - - -
    #define ETH_DMASR_TPSS   ETH_DMASR_TPSS_Msk /* Transmit process stopped status */
    -
    - -
    -
    - -

    ◆ ETH_DMASR_TS_Pos

    - -
    -
    - - - - -
    #define ETH_DMASR_TS_Pos   (0U)
    -
    - -
    -
    - -

    ◆ ETH_DMASR_TS_Msk

    - -
    -
    - - - - -
    #define ETH_DMASR_TS_Msk   (0x1UL << ETH_DMASR_TS_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ ETH_DMASR_TS

    - -
    -
    - - - - -
    #define ETH_DMASR_TS   ETH_DMASR_TS_Msk /* Transmit status */
    -
    - -
    -
    - -

    ◆ ETH_DMAOMR_DTCEFD_Pos

    - -
    -
    - - - - -
    #define ETH_DMAOMR_DTCEFD_Pos   (26U)
    -
    - -
    -
    - -

    ◆ ETH_DMAOMR_DTCEFD_Msk

    - -
    -
    - - - - -
    #define ETH_DMAOMR_DTCEFD_Msk   (0x1UL << ETH_DMAOMR_DTCEFD_Pos)
    -
    -

    0x04000000

    - -
    -
    - -

    ◆ ETH_DMAOMR_DTCEFD

    - -
    -
    - - - - -
    #define ETH_DMAOMR_DTCEFD   ETH_DMAOMR_DTCEFD_Msk /* Disable Dropping of TCP/IP checksum error frames */
    -
    - -
    -
    - -

    ◆ ETH_DMAOMR_RSF_Pos

    - -
    -
    - - - - -
    #define ETH_DMAOMR_RSF_Pos   (25U)
    -
    - -
    -
    - -

    ◆ ETH_DMAOMR_RSF_Msk

    - -
    -
    - - - - -
    #define ETH_DMAOMR_RSF_Msk   (0x1UL << ETH_DMAOMR_RSF_Pos)
    -
    -

    0x02000000

    - -
    -
    - -

    ◆ ETH_DMAOMR_RSF

    - -
    -
    - - - - -
    #define ETH_DMAOMR_RSF   ETH_DMAOMR_RSF_Msk /* Receive store and forward */
    -
    - -
    -
    - -

    ◆ ETH_DMAOMR_DFRF_Pos

    - -
    -
    - - - - -
    #define ETH_DMAOMR_DFRF_Pos   (24U)
    -
    - -
    -
    - -

    ◆ ETH_DMAOMR_DFRF_Msk

    - -
    -
    - - - - -
    #define ETH_DMAOMR_DFRF_Msk   (0x1UL << ETH_DMAOMR_DFRF_Pos)
    -
    -

    0x01000000

    - -
    -
    - -

    ◆ ETH_DMAOMR_DFRF

    - -
    -
    - - - - -
    #define ETH_DMAOMR_DFRF   ETH_DMAOMR_DFRF_Msk /* Disable flushing of received frames */
    -
    - -
    -
    - -

    ◆ ETH_DMAOMR_TSF_Pos

    - -
    -
    - - - - -
    #define ETH_DMAOMR_TSF_Pos   (21U)
    -
    - -
    -
    - -

    ◆ ETH_DMAOMR_TSF_Msk

    - -
    -
    - - - - -
    #define ETH_DMAOMR_TSF_Msk   (0x1UL << ETH_DMAOMR_TSF_Pos)
    -
    -

    0x00200000

    - -
    -
    - -

    ◆ ETH_DMAOMR_TSF

    - -
    -
    - - - - -
    #define ETH_DMAOMR_TSF   ETH_DMAOMR_TSF_Msk /* Transmit store and forward */
    -
    - -
    -
    - -

    ◆ ETH_DMAOMR_FTF_Pos

    - -
    -
    - - - - -
    #define ETH_DMAOMR_FTF_Pos   (20U)
    -
    - -
    -
    - -

    ◆ ETH_DMAOMR_FTF_Msk

    - -
    -
    - - - - -
    #define ETH_DMAOMR_FTF_Msk   (0x1UL << ETH_DMAOMR_FTF_Pos)
    -
    -

    0x00100000

    - -
    -
    - -

    ◆ ETH_DMAOMR_FTF

    - -
    -
    - - - - -
    #define ETH_DMAOMR_FTF   ETH_DMAOMR_FTF_Msk /* Flush transmit FIFO */
    -
    - -
    -
    - -

    ◆ ETH_DMAOMR_TTC_Pos

    - -
    -
    - - - - -
    #define ETH_DMAOMR_TTC_Pos   (14U)
    -
    - -
    -
    - -

    ◆ ETH_DMAOMR_TTC_Msk

    - -
    -
    - - - - -
    #define ETH_DMAOMR_TTC_Msk   (0x7UL << ETH_DMAOMR_TTC_Pos)
    -
    -

    0x0001C000

    - -
    -
    - -

    ◆ ETH_DMAOMR_TTC

    - -
    -
    - - - - -
    #define ETH_DMAOMR_TTC   ETH_DMAOMR_TTC_Msk /* Transmit threshold control */
    -
    - -
    -
    - -

    ◆ ETH_DMAOMR_TTC_64Bytes

    - -
    -
    - - - - -
    #define ETH_DMAOMR_TTC_64Bytes   0x00000000U /* threshold level of the MTL Transmit FIFO is 64 Bytes */
    -
    - -
    -
    - -

    ◆ ETH_DMAOMR_TTC_128Bytes

    - -
    -
    - - - - -
    #define ETH_DMAOMR_TTC_128Bytes   0x00004000U /* threshold level of the MTL Transmit FIFO is 128 Bytes */
    -
    - -
    -
    - -

    ◆ ETH_DMAOMR_TTC_192Bytes

    - -
    -
    - - - - -
    #define ETH_DMAOMR_TTC_192Bytes   0x00008000U /* threshold level of the MTL Transmit FIFO is 192 Bytes */
    -
    - -
    -
    - -

    ◆ ETH_DMAOMR_TTC_256Bytes

    - -
    -
    - - - - -
    #define ETH_DMAOMR_TTC_256Bytes   0x0000C000U /* threshold level of the MTL Transmit FIFO is 256 Bytes */
    -
    - -
    -
    - -

    ◆ ETH_DMAOMR_TTC_40Bytes

    - -
    -
    - - - - -
    #define ETH_DMAOMR_TTC_40Bytes   0x00010000U /* threshold level of the MTL Transmit FIFO is 40 Bytes */
    -
    - -
    -
    - -

    ◆ ETH_DMAOMR_TTC_32Bytes

    - -
    -
    - - - - -
    #define ETH_DMAOMR_TTC_32Bytes   0x00014000U /* threshold level of the MTL Transmit FIFO is 32 Bytes */
    -
    - -
    -
    - -

    ◆ ETH_DMAOMR_TTC_24Bytes

    - -
    -
    - - - - -
    #define ETH_DMAOMR_TTC_24Bytes   0x00018000U /* threshold level of the MTL Transmit FIFO is 24 Bytes */
    -
    - -
    -
    - -

    ◆ ETH_DMAOMR_TTC_16Bytes

    - -
    -
    - - - - -
    #define ETH_DMAOMR_TTC_16Bytes   0x0001C000U /* threshold level of the MTL Transmit FIFO is 16 Bytes */
    -
    - -
    -
    - -

    ◆ ETH_DMAOMR_ST_Pos

    - -
    -
    - - - - -
    #define ETH_DMAOMR_ST_Pos   (13U)
    -
    - -
    -
    - -

    ◆ ETH_DMAOMR_ST_Msk

    - -
    -
    - - - - -
    #define ETH_DMAOMR_ST_Msk   (0x1UL << ETH_DMAOMR_ST_Pos)
    -
    -

    0x00002000

    - -
    -
    - -

    ◆ ETH_DMAOMR_ST

    - -
    -
    - - - - -
    #define ETH_DMAOMR_ST   ETH_DMAOMR_ST_Msk /* Start/stop transmission command */
    -
    - -
    -
    - -

    ◆ ETH_DMAOMR_FEF_Pos

    - -
    -
    - - - - -
    #define ETH_DMAOMR_FEF_Pos   (7U)
    -
    - -
    -
    - -

    ◆ ETH_DMAOMR_FEF_Msk

    - -
    -
    - - - - -
    #define ETH_DMAOMR_FEF_Msk   (0x1UL << ETH_DMAOMR_FEF_Pos)
    -
    -

    0x00000080

    - -
    -
    - -

    ◆ ETH_DMAOMR_FEF

    - -
    -
    - - - - -
    #define ETH_DMAOMR_FEF   ETH_DMAOMR_FEF_Msk /* Forward error frames */
    -
    - -
    -
    - -

    ◆ ETH_DMAOMR_FUGF_Pos

    - -
    -
    - - - - -
    #define ETH_DMAOMR_FUGF_Pos   (6U)
    -
    - -
    -
    - -

    ◆ ETH_DMAOMR_FUGF_Msk

    - -
    -
    - - - - -
    #define ETH_DMAOMR_FUGF_Msk   (0x1UL << ETH_DMAOMR_FUGF_Pos)
    -
    -

    0x00000040

    - -
    -
    - -

    ◆ ETH_DMAOMR_FUGF

    - -
    -
    - - - - -
    #define ETH_DMAOMR_FUGF   ETH_DMAOMR_FUGF_Msk /* Forward undersized good frames */
    -
    - -
    -
    - -

    ◆ ETH_DMAOMR_RTC_Pos

    - -
    -
    - - - - -
    #define ETH_DMAOMR_RTC_Pos   (3U)
    -
    - -
    -
    - -

    ◆ ETH_DMAOMR_RTC_Msk

    - -
    -
    - - - - -
    #define ETH_DMAOMR_RTC_Msk   (0x3UL << ETH_DMAOMR_RTC_Pos)
    -
    -

    0x00000018

    - -
    -
    - -

    ◆ ETH_DMAOMR_RTC

    - -
    -
    - - - - -
    #define ETH_DMAOMR_RTC   ETH_DMAOMR_RTC_Msk /* receive threshold control */
    -
    - -
    -
    - -

    ◆ ETH_DMAOMR_RTC_64Bytes

    - -
    -
    - - - - -
    #define ETH_DMAOMR_RTC_64Bytes   0x00000000U /* threshold level of the MTL Receive FIFO is 64 Bytes */
    -
    - -
    -
    - -

    ◆ ETH_DMAOMR_RTC_32Bytes

    - -
    -
    - - - - -
    #define ETH_DMAOMR_RTC_32Bytes   0x00000008U /* threshold level of the MTL Receive FIFO is 32 Bytes */
    -
    - -
    -
    - -

    ◆ ETH_DMAOMR_RTC_96Bytes

    - -
    -
    - - - - -
    #define ETH_DMAOMR_RTC_96Bytes   0x00000010U /* threshold level of the MTL Receive FIFO is 96 Bytes */
    -
    - -
    -
    - -

    ◆ ETH_DMAOMR_RTC_128Bytes

    - -
    -
    - - - - -
    #define ETH_DMAOMR_RTC_128Bytes   0x00000018U /* threshold level of the MTL Receive FIFO is 128 Bytes */
    -
    - -
    -
    - -

    ◆ ETH_DMAOMR_OSF_Pos

    - -
    -
    - - - - -
    #define ETH_DMAOMR_OSF_Pos   (2U)
    -
    - -
    -
    - -

    ◆ ETH_DMAOMR_OSF_Msk

    - -
    -
    - - - - -
    #define ETH_DMAOMR_OSF_Msk   (0x1UL << ETH_DMAOMR_OSF_Pos)
    -
    -

    0x00000004

    - -
    -
    - -

    ◆ ETH_DMAOMR_OSF

    - -
    -
    - - - - -
    #define ETH_DMAOMR_OSF   ETH_DMAOMR_OSF_Msk /* operate on second frame */
    -
    - -
    -
    - -

    ◆ ETH_DMAOMR_SR_Pos

    - -
    -
    - - - - -
    #define ETH_DMAOMR_SR_Pos   (1U)
    -
    - -
    -
    - -

    ◆ ETH_DMAOMR_SR_Msk

    - -
    -
    - - - - -
    #define ETH_DMAOMR_SR_Msk   (0x1UL << ETH_DMAOMR_SR_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ ETH_DMAOMR_SR

    - -
    -
    - - - - -
    #define ETH_DMAOMR_SR   ETH_DMAOMR_SR_Msk /* Start/stop receive */
    -
    - -
    -
    - -

    ◆ ETH_DMAIER_NISE_Pos

    - -
    -
    - - - - -
    #define ETH_DMAIER_NISE_Pos   (16U)
    -
    - -
    -
    - -

    ◆ ETH_DMAIER_NISE_Msk

    - -
    -
    - - - - -
    #define ETH_DMAIER_NISE_Msk   (0x1UL << ETH_DMAIER_NISE_Pos)
    -
    -

    0x00010000

    - -
    -
    - -

    ◆ ETH_DMAIER_NISE

    - -
    -
    - - - - -
    #define ETH_DMAIER_NISE   ETH_DMAIER_NISE_Msk /* Normal interrupt summary enable */
    -
    - -
    -
    - -

    ◆ ETH_DMAIER_AISE_Pos

    - -
    -
    - - - - -
    #define ETH_DMAIER_AISE_Pos   (15U)
    -
    - -
    -
    - -

    ◆ ETH_DMAIER_AISE_Msk

    - -
    -
    - - - - -
    #define ETH_DMAIER_AISE_Msk   (0x1UL << ETH_DMAIER_AISE_Pos)
    -
    -

    0x00008000

    - -
    -
    - -

    ◆ ETH_DMAIER_AISE

    - -
    -
    - - - - -
    #define ETH_DMAIER_AISE   ETH_DMAIER_AISE_Msk /* Abnormal interrupt summary enable */
    -
    - -
    -
    - -

    ◆ ETH_DMAIER_ERIE_Pos

    - -
    -
    - - - - -
    #define ETH_DMAIER_ERIE_Pos   (14U)
    -
    - -
    -
    - -

    ◆ ETH_DMAIER_ERIE_Msk

    - -
    -
    - - - - -
    #define ETH_DMAIER_ERIE_Msk   (0x1UL << ETH_DMAIER_ERIE_Pos)
    -
    -

    0x00004000

    - -
    -
    - -

    ◆ ETH_DMAIER_ERIE

    - -
    -
    - - - - -
    #define ETH_DMAIER_ERIE   ETH_DMAIER_ERIE_Msk /* Early receive interrupt enable */
    -
    - -
    -
    - -

    ◆ ETH_DMAIER_FBEIE_Pos

    - -
    -
    - - - - -
    #define ETH_DMAIER_FBEIE_Pos   (13U)
    -
    - -
    -
    - -

    ◆ ETH_DMAIER_FBEIE_Msk

    - -
    -
    - - - - -
    #define ETH_DMAIER_FBEIE_Msk   (0x1UL << ETH_DMAIER_FBEIE_Pos)
    -
    -

    0x00002000

    - -
    -
    - -

    ◆ ETH_DMAIER_FBEIE

    - -
    -
    - - - - -
    #define ETH_DMAIER_FBEIE   ETH_DMAIER_FBEIE_Msk /* Fatal bus error interrupt enable */
    -
    - -
    -
    - -

    ◆ ETH_DMAIER_ETIE_Pos

    - -
    -
    - - - - -
    #define ETH_DMAIER_ETIE_Pos   (10U)
    -
    - -
    -
    - -

    ◆ ETH_DMAIER_ETIE_Msk

    - -
    -
    - - - - -
    #define ETH_DMAIER_ETIE_Msk   (0x1UL << ETH_DMAIER_ETIE_Pos)
    -
    -

    0x00000400

    - -
    -
    - -

    ◆ ETH_DMAIER_ETIE

    - -
    -
    - - - - -
    #define ETH_DMAIER_ETIE   ETH_DMAIER_ETIE_Msk /* Early transmit interrupt enable */
    -
    - -
    -
    - -

    ◆ ETH_DMAIER_RWTIE_Pos

    - -
    -
    - - - - -
    #define ETH_DMAIER_RWTIE_Pos   (9U)
    -
    - -
    -
    - -

    ◆ ETH_DMAIER_RWTIE_Msk

    - -
    -
    - - - - -
    #define ETH_DMAIER_RWTIE_Msk   (0x1UL << ETH_DMAIER_RWTIE_Pos)
    -
    -

    0x00000200

    - -
    -
    - -

    ◆ ETH_DMAIER_RWTIE

    - -
    -
    - - - - -
    #define ETH_DMAIER_RWTIE   ETH_DMAIER_RWTIE_Msk /* Receive watchdog timeout interrupt enable */
    -
    - -
    -
    - -

    ◆ ETH_DMAIER_RPSIE_Pos

    - -
    -
    - - - - -
    #define ETH_DMAIER_RPSIE_Pos   (8U)
    -
    - -
    -
    - -

    ◆ ETH_DMAIER_RPSIE_Msk

    - -
    -
    - - - - -
    #define ETH_DMAIER_RPSIE_Msk   (0x1UL << ETH_DMAIER_RPSIE_Pos)
    -
    -

    0x00000100

    - -
    -
    - -

    ◆ ETH_DMAIER_RPSIE

    - -
    -
    - - - - -
    #define ETH_DMAIER_RPSIE   ETH_DMAIER_RPSIE_Msk /* Receive process stopped interrupt enable */
    -
    - -
    -
    - -

    ◆ ETH_DMAIER_RBUIE_Pos

    - -
    -
    - - - - -
    #define ETH_DMAIER_RBUIE_Pos   (7U)
    -
    - -
    -
    - -

    ◆ ETH_DMAIER_RBUIE_Msk

    - -
    -
    - - - - -
    #define ETH_DMAIER_RBUIE_Msk   (0x1UL << ETH_DMAIER_RBUIE_Pos)
    -
    -

    0x00000080

    - -
    -
    - -

    ◆ ETH_DMAIER_RBUIE

    - -
    -
    - - - - -
    #define ETH_DMAIER_RBUIE   ETH_DMAIER_RBUIE_Msk /* Receive buffer unavailable interrupt enable */
    -
    - -
    -
    - -

    ◆ ETH_DMAIER_RIE_Pos

    - -
    -
    - - - - -
    #define ETH_DMAIER_RIE_Pos   (6U)
    -
    - -
    -
    - -

    ◆ ETH_DMAIER_RIE_Msk

    - -
    -
    - - - - -
    #define ETH_DMAIER_RIE_Msk   (0x1UL << ETH_DMAIER_RIE_Pos)
    -
    -

    0x00000040

    - -
    -
    - -

    ◆ ETH_DMAIER_RIE

    - -
    -
    - - - - -
    #define ETH_DMAIER_RIE   ETH_DMAIER_RIE_Msk /* Receive interrupt enable */
    -
    - -
    -
    - -

    ◆ ETH_DMAIER_TUIE_Pos

    - -
    -
    - - - - -
    #define ETH_DMAIER_TUIE_Pos   (5U)
    -
    - -
    -
    - -

    ◆ ETH_DMAIER_TUIE_Msk

    - -
    -
    - - - - -
    #define ETH_DMAIER_TUIE_Msk   (0x1UL << ETH_DMAIER_TUIE_Pos)
    -
    -

    0x00000020

    - -
    -
    - -

    ◆ ETH_DMAIER_TUIE

    - -
    -
    - - - - -
    #define ETH_DMAIER_TUIE   ETH_DMAIER_TUIE_Msk /* Transmit Underflow interrupt enable */
    -
    - -
    -
    - -

    ◆ ETH_DMAIER_ROIE_Pos

    - -
    -
    - - - - -
    #define ETH_DMAIER_ROIE_Pos   (4U)
    -
    - -
    -
    - -

    ◆ ETH_DMAIER_ROIE_Msk

    - -
    -
    - - - - -
    #define ETH_DMAIER_ROIE_Msk   (0x1UL << ETH_DMAIER_ROIE_Pos)
    -
    -

    0x00000010

    - -
    -
    - -

    ◆ ETH_DMAIER_ROIE

    - -
    -
    - - - - -
    #define ETH_DMAIER_ROIE   ETH_DMAIER_ROIE_Msk /* Receive Overflow interrupt enable */
    -
    - -
    -
    - -

    ◆ ETH_DMAIER_TJTIE_Pos

    - -
    -
    - - - - -
    #define ETH_DMAIER_TJTIE_Pos   (3U)
    -
    - -
    -
    - -

    ◆ ETH_DMAIER_TJTIE_Msk

    - -
    -
    - - - - -
    #define ETH_DMAIER_TJTIE_Msk   (0x1UL << ETH_DMAIER_TJTIE_Pos)
    -
    -

    0x00000008

    - -
    -
    - -

    ◆ ETH_DMAIER_TJTIE

    - -
    -
    - - - - -
    #define ETH_DMAIER_TJTIE   ETH_DMAIER_TJTIE_Msk /* Transmit jabber timeout interrupt enable */
    -
    - -
    -
    - -

    ◆ ETH_DMAIER_TBUIE_Pos

    - -
    -
    - - - - -
    #define ETH_DMAIER_TBUIE_Pos   (2U)
    -
    - -
    -
    - -

    ◆ ETH_DMAIER_TBUIE_Msk

    - -
    -
    - - - - -
    #define ETH_DMAIER_TBUIE_Msk   (0x1UL << ETH_DMAIER_TBUIE_Pos)
    -
    -

    0x00000004

    - -
    -
    - -

    ◆ ETH_DMAIER_TBUIE

    - -
    -
    - - - - -
    #define ETH_DMAIER_TBUIE   ETH_DMAIER_TBUIE_Msk /* Transmit buffer unavailable interrupt enable */
    -
    - -
    -
    - -

    ◆ ETH_DMAIER_TPSIE_Pos

    - -
    -
    - - - - -
    #define ETH_DMAIER_TPSIE_Pos   (1U)
    -
    - -
    -
    - -

    ◆ ETH_DMAIER_TPSIE_Msk

    - -
    -
    - - - - -
    #define ETH_DMAIER_TPSIE_Msk   (0x1UL << ETH_DMAIER_TPSIE_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ ETH_DMAIER_TPSIE

    - -
    -
    - - - - -
    #define ETH_DMAIER_TPSIE   ETH_DMAIER_TPSIE_Msk /* Transmit process stopped interrupt enable */
    -
    - -
    -
    - -

    ◆ ETH_DMAIER_TIE_Pos

    - -
    -
    - - - - -
    #define ETH_DMAIER_TIE_Pos   (0U)
    -
    - -
    -
    - -

    ◆ ETH_DMAIER_TIE_Msk

    - -
    -
    - - - - -
    #define ETH_DMAIER_TIE_Msk   (0x1UL << ETH_DMAIER_TIE_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ ETH_DMAIER_TIE

    - -
    -
    - - - - -
    #define ETH_DMAIER_TIE   ETH_DMAIER_TIE_Msk /* Transmit interrupt enable */
    -
    - -
    -
    - -

    ◆ ETH_DMAMFBOCR_OFOC_Pos

    - -
    -
    - - - - -
    #define ETH_DMAMFBOCR_OFOC_Pos   (28U)
    -
    - -
    -
    - -

    ◆ ETH_DMAMFBOCR_OFOC_Msk

    - -
    -
    - - - - -
    #define ETH_DMAMFBOCR_OFOC_Msk   (0x1UL << ETH_DMAMFBOCR_OFOC_Pos)
    -
    -

    0x10000000

    - -
    -
    - -

    ◆ ETH_DMAMFBOCR_OFOC

    - -
    -
    - - - - -
    #define ETH_DMAMFBOCR_OFOC   ETH_DMAMFBOCR_OFOC_Msk /* Overflow bit for FIFO overflow counter */
    -
    - -
    -
    - -

    ◆ ETH_DMAMFBOCR_MFA_Pos

    - -
    -
    - - - - -
    #define ETH_DMAMFBOCR_MFA_Pos   (17U)
    -
    - -
    -
    - -

    ◆ ETH_DMAMFBOCR_MFA_Msk

    - -
    -
    - - - - -
    #define ETH_DMAMFBOCR_MFA_Msk   (0x7FFUL << ETH_DMAMFBOCR_MFA_Pos)
    -
    -

    0x0FFE0000

    - -
    -
    - -

    ◆ ETH_DMAMFBOCR_MFA

    - -
    -
    - - - - -
    #define ETH_DMAMFBOCR_MFA   ETH_DMAMFBOCR_MFA_Msk /* Number of frames missed by the application */
    -
    - -
    -
    - -

    ◆ ETH_DMAMFBOCR_OMFC_Pos

    - -
    -
    - - - - -
    #define ETH_DMAMFBOCR_OMFC_Pos   (16U)
    -
    - -
    -
    - -

    ◆ ETH_DMAMFBOCR_OMFC_Msk

    - -
    -
    - - - - -
    #define ETH_DMAMFBOCR_OMFC_Msk   (0x1UL << ETH_DMAMFBOCR_OMFC_Pos)
    -
    -

    0x00010000

    - -
    -
    - -

    ◆ ETH_DMAMFBOCR_OMFC

    - -
    -
    - - - - -
    #define ETH_DMAMFBOCR_OMFC   ETH_DMAMFBOCR_OMFC_Msk /* Overflow bit for missed frame counter */
    -
    - -
    -
    - -

    ◆ ETH_DMAMFBOCR_MFC_Pos

    - -
    -
    - - - - -
    #define ETH_DMAMFBOCR_MFC_Pos   (0U)
    -
    - -
    -
    - -

    ◆ ETH_DMAMFBOCR_MFC_Msk

    - -
    -
    - - - - -
    #define ETH_DMAMFBOCR_MFC_Msk   (0xFFFFUL << ETH_DMAMFBOCR_MFC_Pos)
    -
    -

    0x0000FFFF

    - -
    -
    - -

    ◆ ETH_DMAMFBOCR_MFC

    - -
    -
    - - - - -
    #define ETH_DMAMFBOCR_MFC   ETH_DMAMFBOCR_MFC_Msk /* Number of frames missed by the controller */
    -
    - -
    -
    - -

    ◆ ETH_DMACHTDR_HTDAP_Pos

    - -
    -
    - - - - -
    #define ETH_DMACHTDR_HTDAP_Pos   (0U)
    -
    - -
    -
    - -

    ◆ ETH_DMACHTDR_HTDAP_Msk

    - -
    -
    - - - - -
    #define ETH_DMACHTDR_HTDAP_Msk   (0xFFFFFFFFUL << ETH_DMACHTDR_HTDAP_Pos)
    -
    -

    0xFFFFFFFF

    - -
    -
    - -

    ◆ ETH_DMACHTDR_HTDAP

    - -
    -
    - - - - -
    #define ETH_DMACHTDR_HTDAP   ETH_DMACHTDR_HTDAP_Msk /* Host transmit descriptor address pointer */
    -
    - -
    -
    - -

    ◆ ETH_DMACHRDR_HRDAP_Pos

    - -
    -
    - - - - -
    #define ETH_DMACHRDR_HRDAP_Pos   (0U)
    -
    - -
    -
    - -

    ◆ ETH_DMACHRDR_HRDAP_Msk

    - -
    -
    - - - - -
    #define ETH_DMACHRDR_HRDAP_Msk   (0xFFFFFFFFUL << ETH_DMACHRDR_HRDAP_Pos)
    -
    -

    0xFFFFFFFF

    - -
    -
    - -

    ◆ ETH_DMACHRDR_HRDAP

    - -
    -
    - - - - -
    #define ETH_DMACHRDR_HRDAP   ETH_DMACHRDR_HRDAP_Msk /* Host receive descriptor address pointer */
    -
    - -
    -
    - -

    ◆ ETH_DMACHTBAR_HTBAP_Pos

    - -
    -
    - - - - -
    #define ETH_DMACHTBAR_HTBAP_Pos   (0U)
    -
    - -
    -
    - -

    ◆ ETH_DMACHTBAR_HTBAP_Msk

    - -
    -
    - - - - -
    #define ETH_DMACHTBAR_HTBAP_Msk   (0xFFFFFFFFUL << ETH_DMACHTBAR_HTBAP_Pos)
    -
    -

    0xFFFFFFFF

    - -
    -
    - -

    ◆ ETH_DMACHTBAR_HTBAP

    - -
    -
    - - - - -
    #define ETH_DMACHTBAR_HTBAP   ETH_DMACHTBAR_HTBAP_Msk /* Host transmit buffer address pointer */
    -
    - -
    -
    - -

    ◆ ETH_DMACHRBAR_HRBAP_Pos

    - -
    -
    - - - - -
    #define ETH_DMACHRBAR_HRBAP_Pos   (0U)
    -
    - -
    -
    - -

    ◆ ETH_DMACHRBAR_HRBAP_Msk

    - -
    -
    - - - - -
    #define ETH_DMACHRBAR_HRBAP_Msk   (0xFFFFFFFFUL << ETH_DMACHRBAR_HRBAP_Pos)
    -
    -

    0xFFFFFFFF

    - -
    -
    - -

    ◆ ETH_DMACHRBAR_HRBAP

    - -
    -
    - - - - -
    #define ETH_DMACHRBAR_HRBAP   ETH_DMACHRBAR_HRBAP_Msk /* Host receive buffer address pointer */
    -
    - -
    -
    - -

    ◆ USB_OTG_GOTGCTL_SRQSCS_Pos

    - -
    -
    - - - - -
    #define USB_OTG_GOTGCTL_SRQSCS_Pos   (0U)
    -
    - -
    -
    - -

    ◆ USB_OTG_GOTGCTL_SRQSCS_Msk

    - -
    -
    - - - - -
    #define USB_OTG_GOTGCTL_SRQSCS_Msk   (0x1UL << USB_OTG_GOTGCTL_SRQSCS_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ USB_OTG_GOTGCTL_SRQSCS

    - -
    -
    - - - - -
    #define USB_OTG_GOTGCTL_SRQSCS   USB_OTG_GOTGCTL_SRQSCS_Msk
    -
    -

    Session request success

    - -
    -
    - -

    ◆ USB_OTG_GOTGCTL_SRQ_Pos

    - -
    -
    - - - - -
    #define USB_OTG_GOTGCTL_SRQ_Pos   (1U)
    -
    - -
    -
    - -

    ◆ USB_OTG_GOTGCTL_SRQ_Msk

    - -
    -
    - - - - -
    #define USB_OTG_GOTGCTL_SRQ_Msk   (0x1UL << USB_OTG_GOTGCTL_SRQ_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ USB_OTG_GOTGCTL_SRQ

    - -
    -
    - - - - -
    #define USB_OTG_GOTGCTL_SRQ   USB_OTG_GOTGCTL_SRQ_Msk
    -
    -

    Session request

    - -
    -
    - -

    ◆ USB_OTG_GOTGCTL_HNGSCS_Pos

    - -
    -
    - - - - -
    #define USB_OTG_GOTGCTL_HNGSCS_Pos   (8U)
    -
    - -
    -
    - -

    ◆ USB_OTG_GOTGCTL_HNGSCS_Msk

    - -
    -
    - - - - -
    #define USB_OTG_GOTGCTL_HNGSCS_Msk   (0x1UL << USB_OTG_GOTGCTL_HNGSCS_Pos)
    -
    -

    0x00000100

    - -
    -
    - -

    ◆ USB_OTG_GOTGCTL_HNGSCS

    - -
    -
    - - - - -
    #define USB_OTG_GOTGCTL_HNGSCS   USB_OTG_GOTGCTL_HNGSCS_Msk
    -
    -

    Host set HNP enable

    - -
    -
    - -

    ◆ USB_OTG_GOTGCTL_HNPRQ_Pos

    - -
    -
    - - - - -
    #define USB_OTG_GOTGCTL_HNPRQ_Pos   (9U)
    -
    - -
    -
    - -

    ◆ USB_OTG_GOTGCTL_HNPRQ_Msk

    - -
    -
    - - - - -
    #define USB_OTG_GOTGCTL_HNPRQ_Msk   (0x1UL << USB_OTG_GOTGCTL_HNPRQ_Pos)
    -
    -

    0x00000200

    - -
    -
    - -

    ◆ USB_OTG_GOTGCTL_HNPRQ

    - -
    -
    - - - - -
    #define USB_OTG_GOTGCTL_HNPRQ   USB_OTG_GOTGCTL_HNPRQ_Msk
    -
    -

    HNP request

    - -
    -
    - -

    ◆ USB_OTG_GOTGCTL_HSHNPEN_Pos

    - -
    -
    - - - - -
    #define USB_OTG_GOTGCTL_HSHNPEN_Pos   (10U)
    -
    - -
    -
    - -

    ◆ USB_OTG_GOTGCTL_HSHNPEN_Msk

    - -
    -
    - - - - -
    #define USB_OTG_GOTGCTL_HSHNPEN_Msk   (0x1UL << USB_OTG_GOTGCTL_HSHNPEN_Pos)
    -
    -

    0x00000400

    - -
    -
    - -

    ◆ USB_OTG_GOTGCTL_HSHNPEN

    - -
    -
    - - - - -
    #define USB_OTG_GOTGCTL_HSHNPEN   USB_OTG_GOTGCTL_HSHNPEN_Msk
    -
    -

    Host set HNP enable

    - -
    -
    - -

    ◆ USB_OTG_GOTGCTL_DHNPEN_Pos

    - -
    -
    - - - - -
    #define USB_OTG_GOTGCTL_DHNPEN_Pos   (11U)
    -
    - -
    -
    - -

    ◆ USB_OTG_GOTGCTL_DHNPEN_Msk

    - -
    -
    - - - - -
    #define USB_OTG_GOTGCTL_DHNPEN_Msk   (0x1UL << USB_OTG_GOTGCTL_DHNPEN_Pos)
    -
    -

    0x00000800

    - -
    -
    - -

    ◆ USB_OTG_GOTGCTL_DHNPEN

    - -
    -
    - - - - -
    #define USB_OTG_GOTGCTL_DHNPEN   USB_OTG_GOTGCTL_DHNPEN_Msk
    -
    -

    Device HNP enabled

    - -
    -
    - -

    ◆ USB_OTG_GOTGCTL_CIDSTS_Pos

    - -
    -
    - - - - -
    #define USB_OTG_GOTGCTL_CIDSTS_Pos   (16U)
    -
    - -
    -
    - -

    ◆ USB_OTG_GOTGCTL_CIDSTS_Msk

    - -
    -
    - - - - -
    #define USB_OTG_GOTGCTL_CIDSTS_Msk   (0x1UL << USB_OTG_GOTGCTL_CIDSTS_Pos)
    -
    -

    0x00010000

    - -
    -
    - -

    ◆ USB_OTG_GOTGCTL_CIDSTS

    - -
    -
    - - - - -
    #define USB_OTG_GOTGCTL_CIDSTS   USB_OTG_GOTGCTL_CIDSTS_Msk
    -
    -

    Connector ID status

    - -
    -
    - -

    ◆ USB_OTG_GOTGCTL_DBCT_Pos

    - -
    -
    - - - - -
    #define USB_OTG_GOTGCTL_DBCT_Pos   (17U)
    -
    - -
    -
    - -

    ◆ USB_OTG_GOTGCTL_DBCT_Msk

    - -
    -
    - - - - -
    #define USB_OTG_GOTGCTL_DBCT_Msk   (0x1UL << USB_OTG_GOTGCTL_DBCT_Pos)
    -
    -

    0x00020000

    - -
    -
    - -

    ◆ USB_OTG_GOTGCTL_DBCT

    - -
    -
    - - - - -
    #define USB_OTG_GOTGCTL_DBCT   USB_OTG_GOTGCTL_DBCT_Msk
    -
    -

    Long/short debounce time

    - -
    -
    - -

    ◆ USB_OTG_GOTGCTL_ASVLD_Pos

    - -
    -
    - - - - -
    #define USB_OTG_GOTGCTL_ASVLD_Pos   (18U)
    -
    - -
    -
    - -

    ◆ USB_OTG_GOTGCTL_ASVLD_Msk

    - -
    -
    - - - - -
    #define USB_OTG_GOTGCTL_ASVLD_Msk   (0x1UL << USB_OTG_GOTGCTL_ASVLD_Pos)
    -
    -

    0x00040000

    - -
    -
    - -

    ◆ USB_OTG_GOTGCTL_ASVLD

    - -
    -
    - - - - -
    #define USB_OTG_GOTGCTL_ASVLD   USB_OTG_GOTGCTL_ASVLD_Msk
    -
    -

    A-session valid
    -

    - -
    -
    - -

    ◆ USB_OTG_GOTGCTL_BSVLD_Pos

    - -
    -
    - - - - -
    #define USB_OTG_GOTGCTL_BSVLD_Pos   (19U)
    -
    - -
    -
    - -

    ◆ USB_OTG_GOTGCTL_BSVLD_Msk

    - -
    -
    - - - - -
    #define USB_OTG_GOTGCTL_BSVLD_Msk   (0x1UL << USB_OTG_GOTGCTL_BSVLD_Pos)
    -
    -

    0x00080000

    - -
    -
    - -

    ◆ USB_OTG_GOTGCTL_BSVLD

    - -
    -
    - - - - -
    #define USB_OTG_GOTGCTL_BSVLD   USB_OTG_GOTGCTL_BSVLD_Msk
    -
    -

    B-session valid

    - -
    -
    - -

    ◆ USB_OTG_HCFG_FSLSPCS_Pos

    - -
    -
    - - - - -
    #define USB_OTG_HCFG_FSLSPCS_Pos   (0U)
    -
    - -
    -
    - -

    ◆ USB_OTG_HCFG_FSLSPCS_Msk

    - -
    -
    - - - - -
    #define USB_OTG_HCFG_FSLSPCS_Msk   (0x3UL << USB_OTG_HCFG_FSLSPCS_Pos)
    -
    -

    0x00000003

    - -
    -
    - -

    ◆ USB_OTG_HCFG_FSLSPCS

    - -
    -
    - - - - -
    #define USB_OTG_HCFG_FSLSPCS   USB_OTG_HCFG_FSLSPCS_Msk
    -
    -

    FS/LS PHY clock select
    -

    - -
    -
    - -

    ◆ USB_OTG_HCFG_FSLSPCS_0

    - -
    -
    - - - - -
    #define USB_OTG_HCFG_FSLSPCS_0   (0x1UL << USB_OTG_HCFG_FSLSPCS_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ USB_OTG_HCFG_FSLSPCS_1

    - -
    -
    - - - - -
    #define USB_OTG_HCFG_FSLSPCS_1   (0x2UL << USB_OTG_HCFG_FSLSPCS_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ USB_OTG_HCFG_FSLSS_Pos

    - -
    -
    - - - - -
    #define USB_OTG_HCFG_FSLSS_Pos   (2U)
    -
    - -
    -
    - -

    ◆ USB_OTG_HCFG_FSLSS_Msk

    - -
    -
    - - - - -
    #define USB_OTG_HCFG_FSLSS_Msk   (0x1UL << USB_OTG_HCFG_FSLSS_Pos)
    -
    -

    0x00000004

    - -
    -
    - -

    ◆ USB_OTG_HCFG_FSLSS

    - -
    -
    - - - - -
    #define USB_OTG_HCFG_FSLSS   USB_OTG_HCFG_FSLSS_Msk
    -
    -

    FS- and LS-only support

    - -
    -
    - -

    ◆ USB_OTG_DCFG_DSPD_Pos

    - -
    -
    - - - - -
    #define USB_OTG_DCFG_DSPD_Pos   (0U)
    -
    - -
    -
    - -

    ◆ USB_OTG_DCFG_DSPD_Msk

    - -
    -
    - - - - -
    #define USB_OTG_DCFG_DSPD_Msk   (0x3UL << USB_OTG_DCFG_DSPD_Pos)
    -
    -

    0x00000003

    - -
    -
    - -

    ◆ USB_OTG_DCFG_DSPD

    - -
    -
    - - - - -
    #define USB_OTG_DCFG_DSPD   USB_OTG_DCFG_DSPD_Msk
    -
    -

    Device speed

    - -
    -
    - -

    ◆ USB_OTG_DCFG_DSPD_0

    - -
    -
    - - - - -
    #define USB_OTG_DCFG_DSPD_0   (0x1UL << USB_OTG_DCFG_DSPD_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ USB_OTG_DCFG_DSPD_1

    - -
    -
    - - - - -
    #define USB_OTG_DCFG_DSPD_1   (0x2UL << USB_OTG_DCFG_DSPD_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ USB_OTG_DCFG_NZLSOHSK_Pos

    - -
    -
    - - - - -
    #define USB_OTG_DCFG_NZLSOHSK_Pos   (2U)
    -
    - -
    -
    - -

    ◆ USB_OTG_DCFG_NZLSOHSK_Msk

    - -
    -
    - - - - -
    #define USB_OTG_DCFG_NZLSOHSK_Msk   (0x1UL << USB_OTG_DCFG_NZLSOHSK_Pos)
    -
    -

    0x00000004

    - -
    -
    - -

    ◆ USB_OTG_DCFG_NZLSOHSK

    - -
    -
    - - - - -
    #define USB_OTG_DCFG_NZLSOHSK   USB_OTG_DCFG_NZLSOHSK_Msk
    -
    -

    Nonzero-length status OUT handshake

    - -
    -
    - -

    ◆ USB_OTG_DCFG_DAD_Pos

    - -
    -
    - - - - -
    #define USB_OTG_DCFG_DAD_Pos   (4U)
    -
    - -
    -
    - -

    ◆ USB_OTG_DCFG_DAD_Msk

    - -
    -
    - - - - -
    #define USB_OTG_DCFG_DAD_Msk   (0x7FUL << USB_OTG_DCFG_DAD_Pos)
    -
    -

    0x000007F0

    - -
    -
    - -

    ◆ USB_OTG_DCFG_DAD

    - -
    -
    - - - - -
    #define USB_OTG_DCFG_DAD   USB_OTG_DCFG_DAD_Msk
    -
    -

    Device address

    - -
    -
    - -

    ◆ USB_OTG_DCFG_DAD_0

    - -
    -
    - - - - -
    #define USB_OTG_DCFG_DAD_0   (0x01UL << USB_OTG_DCFG_DAD_Pos)
    -
    -

    0x00000010

    - -
    -
    - -

    ◆ USB_OTG_DCFG_DAD_1

    - -
    -
    - - - - -
    #define USB_OTG_DCFG_DAD_1   (0x02UL << USB_OTG_DCFG_DAD_Pos)
    -
    -

    0x00000020

    - -
    -
    - -

    ◆ USB_OTG_DCFG_DAD_2

    - -
    -
    - - - - -
    #define USB_OTG_DCFG_DAD_2   (0x04UL << USB_OTG_DCFG_DAD_Pos)
    -
    -

    0x00000040

    - -
    -
    - -

    ◆ USB_OTG_DCFG_DAD_3

    - -
    -
    - - - - -
    #define USB_OTG_DCFG_DAD_3   (0x08UL << USB_OTG_DCFG_DAD_Pos)
    -
    -

    0x00000080

    - -
    -
    - -

    ◆ USB_OTG_DCFG_DAD_4

    - -
    -
    - - - - -
    #define USB_OTG_DCFG_DAD_4   (0x10UL << USB_OTG_DCFG_DAD_Pos)
    -
    -

    0x00000100

    - -
    -
    - -

    ◆ USB_OTG_DCFG_DAD_5

    - -
    -
    - - - - -
    #define USB_OTG_DCFG_DAD_5   (0x20UL << USB_OTG_DCFG_DAD_Pos)
    -
    -

    0x00000200

    - -
    -
    - -

    ◆ USB_OTG_DCFG_DAD_6

    - -
    -
    - - - - -
    #define USB_OTG_DCFG_DAD_6   (0x40UL << USB_OTG_DCFG_DAD_Pos)
    -
    -

    0x00000400

    - -
    -
    - -

    ◆ USB_OTG_DCFG_PFIVL_Pos

    - -
    -
    - - - - -
    #define USB_OTG_DCFG_PFIVL_Pos   (11U)
    -
    - -
    -
    - -

    ◆ USB_OTG_DCFG_PFIVL_Msk

    - -
    -
    - - - - -
    #define USB_OTG_DCFG_PFIVL_Msk   (0x3UL << USB_OTG_DCFG_PFIVL_Pos)
    -
    -

    0x00001800

    - -
    -
    - -

    ◆ USB_OTG_DCFG_PFIVL

    - -
    -
    - - - - -
    #define USB_OTG_DCFG_PFIVL   USB_OTG_DCFG_PFIVL_Msk
    -
    -

    Periodic (micro)frame interval

    - -
    -
    - -

    ◆ USB_OTG_DCFG_PFIVL_0

    - -
    -
    - - - - -
    #define USB_OTG_DCFG_PFIVL_0   (0x1UL << USB_OTG_DCFG_PFIVL_Pos)
    -
    -

    0x00000800

    - -
    -
    - -

    ◆ USB_OTG_DCFG_PFIVL_1

    - -
    -
    - - - - -
    #define USB_OTG_DCFG_PFIVL_1   (0x2UL << USB_OTG_DCFG_PFIVL_Pos)
    -
    -

    0x00001000

    - -
    -
    - -

    ◆ USB_OTG_DCFG_XCVRDLY_Pos

    - -
    -
    - - - - -
    #define USB_OTG_DCFG_XCVRDLY_Pos   (14U)
    -
    - -
    -
    - -

    ◆ USB_OTG_DCFG_XCVRDLY_Msk

    - -
    -
    - - - - -
    #define USB_OTG_DCFG_XCVRDLY_Msk   (0x1UL << USB_OTG_DCFG_XCVRDLY_Pos)
    -
    -

    0x00004000

    - -
    -
    - -

    ◆ USB_OTG_DCFG_XCVRDLY

    - -
    -
    - - - - -
    #define USB_OTG_DCFG_XCVRDLY   USB_OTG_DCFG_XCVRDLY_Msk
    -
    -

    Transceiver delay

    - -
    -
    - -

    ◆ USB_OTG_DCFG_ERRATIM_Pos

    - -
    -
    - - - - -
    #define USB_OTG_DCFG_ERRATIM_Pos   (15U)
    -
    - -
    -
    - -

    ◆ USB_OTG_DCFG_ERRATIM_Msk

    - -
    -
    - - - - -
    #define USB_OTG_DCFG_ERRATIM_Msk   (0x1UL << USB_OTG_DCFG_ERRATIM_Pos)
    -
    -

    0x00008000

    - -
    -
    - -

    ◆ USB_OTG_DCFG_ERRATIM

    - -
    -
    - - - - -
    #define USB_OTG_DCFG_ERRATIM   USB_OTG_DCFG_ERRATIM_Msk
    -
    -

    Erratic error interrupt mask

    - -
    -
    - -

    ◆ USB_OTG_DCFG_PERSCHIVL_Pos

    - -
    -
    - - - - -
    #define USB_OTG_DCFG_PERSCHIVL_Pos   (24U)
    -
    - -
    -
    - -

    ◆ USB_OTG_DCFG_PERSCHIVL_Msk

    - -
    -
    - - - - -
    #define USB_OTG_DCFG_PERSCHIVL_Msk   (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos)
    -
    -

    0x03000000

    - -
    -
    - -

    ◆ USB_OTG_DCFG_PERSCHIVL

    - -
    -
    - - - - -
    #define USB_OTG_DCFG_PERSCHIVL   USB_OTG_DCFG_PERSCHIVL_Msk
    -
    -

    Periodic scheduling interval

    - -
    -
    - -

    ◆ USB_OTG_DCFG_PERSCHIVL_0

    - -
    -
    - - - - -
    #define USB_OTG_DCFG_PERSCHIVL_0   (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos)
    -
    -

    0x01000000

    - -
    -
    - -

    ◆ USB_OTG_DCFG_PERSCHIVL_1

    - -
    -
    - - - - -
    #define USB_OTG_DCFG_PERSCHIVL_1   (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos)
    -
    -

    0x02000000

    - -
    -
    - -

    ◆ USB_OTG_PCGCR_STPPCLK_Pos

    - -
    -
    - - - - -
    #define USB_OTG_PCGCR_STPPCLK_Pos   (0U)
    -
    - -
    -
    - -

    ◆ USB_OTG_PCGCR_STPPCLK_Msk

    - -
    -
    - - - - -
    #define USB_OTG_PCGCR_STPPCLK_Msk   (0x1UL << USB_OTG_PCGCR_STPPCLK_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ USB_OTG_PCGCR_STPPCLK

    - -
    -
    - - - - -
    #define USB_OTG_PCGCR_STPPCLK   USB_OTG_PCGCR_STPPCLK_Msk
    -
    -

    Stop PHY clock

    - -
    -
    - -

    ◆ USB_OTG_PCGCR_GATEHCLK_Pos

    - -
    -
    - - - - -
    #define USB_OTG_PCGCR_GATEHCLK_Pos   (1U)
    -
    - -
    -
    - -

    ◆ USB_OTG_PCGCR_GATEHCLK_Msk

    - -
    -
    - - - - -
    #define USB_OTG_PCGCR_GATEHCLK_Msk   (0x1UL << USB_OTG_PCGCR_GATEHCLK_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ USB_OTG_PCGCR_GATEHCLK

    - -
    -
    - - - - -
    #define USB_OTG_PCGCR_GATEHCLK   USB_OTG_PCGCR_GATEHCLK_Msk
    -
    -

    Gate HCLK

    - -
    -
    - -

    ◆ USB_OTG_PCGCR_PHYSUSP_Pos

    - -
    -
    - - - - -
    #define USB_OTG_PCGCR_PHYSUSP_Pos   (4U)
    -
    - -
    -
    - -

    ◆ USB_OTG_PCGCR_PHYSUSP_Msk

    - -
    -
    - - - - -
    #define USB_OTG_PCGCR_PHYSUSP_Msk   (0x1UL << USB_OTG_PCGCR_PHYSUSP_Pos)
    -
    -

    0x00000010

    - -
    -
    - -

    ◆ USB_OTG_PCGCR_PHYSUSP

    - -
    -
    - - - - -
    #define USB_OTG_PCGCR_PHYSUSP   USB_OTG_PCGCR_PHYSUSP_Msk
    -
    -

    PHY suspended

    - -
    -
    - -

    ◆ USB_OTG_GOTGINT_SEDET_Pos

    - -
    -
    - - - - -
    #define USB_OTG_GOTGINT_SEDET_Pos   (2U)
    -
    - -
    -
    - -

    ◆ USB_OTG_GOTGINT_SEDET_Msk

    - -
    -
    - - - - -
    #define USB_OTG_GOTGINT_SEDET_Msk   (0x1UL << USB_OTG_GOTGINT_SEDET_Pos)
    -
    -

    0x00000004

    - -
    -
    - -

    ◆ USB_OTG_GOTGINT_SEDET

    - -
    -
    - - - - -
    #define USB_OTG_GOTGINT_SEDET   USB_OTG_GOTGINT_SEDET_Msk
    -
    -

    Session end detected
    -

    - -
    -
    - -

    ◆ USB_OTG_GOTGINT_SRSSCHG_Pos

    - -
    -
    - - - - -
    #define USB_OTG_GOTGINT_SRSSCHG_Pos   (8U)
    -
    - -
    -
    - -

    ◆ USB_OTG_GOTGINT_SRSSCHG_Msk

    - -
    -
    - - - - -
    #define USB_OTG_GOTGINT_SRSSCHG_Msk   (0x1UL << USB_OTG_GOTGINT_SRSSCHG_Pos)
    -
    -

    0x00000100

    - -
    -
    - -

    ◆ USB_OTG_GOTGINT_SRSSCHG

    - -
    -
    - - - - -
    #define USB_OTG_GOTGINT_SRSSCHG   USB_OTG_GOTGINT_SRSSCHG_Msk
    -
    -

    Session request success status change
    -

    - -
    -
    - -

    ◆ USB_OTG_GOTGINT_HNSSCHG_Pos

    - -
    -
    - - - - -
    #define USB_OTG_GOTGINT_HNSSCHG_Pos   (9U)
    -
    - -
    -
    - -

    ◆ USB_OTG_GOTGINT_HNSSCHG_Msk

    - -
    -
    - - - - -
    #define USB_OTG_GOTGINT_HNSSCHG_Msk   (0x1UL << USB_OTG_GOTGINT_HNSSCHG_Pos)
    -
    -

    0x00000200

    - -
    -
    - -

    ◆ USB_OTG_GOTGINT_HNSSCHG

    - -
    -
    - - - - -
    #define USB_OTG_GOTGINT_HNSSCHG   USB_OTG_GOTGINT_HNSSCHG_Msk
    -
    -

    Host negotiation success status change

    - -
    -
    - -

    ◆ USB_OTG_GOTGINT_HNGDET_Pos

    - -
    -
    - - - - -
    #define USB_OTG_GOTGINT_HNGDET_Pos   (17U)
    -
    - -
    -
    - -

    ◆ USB_OTG_GOTGINT_HNGDET_Msk

    - -
    -
    - - - - -
    #define USB_OTG_GOTGINT_HNGDET_Msk   (0x1UL << USB_OTG_GOTGINT_HNGDET_Pos)
    -
    -

    0x00020000

    - -
    -
    - -

    ◆ USB_OTG_GOTGINT_HNGDET

    - -
    -
    - - - - -
    #define USB_OTG_GOTGINT_HNGDET   USB_OTG_GOTGINT_HNGDET_Msk
    -
    -

    Host negotiation detected
    -

    - -
    -
    - -

    ◆ USB_OTG_GOTGINT_ADTOCHG_Pos

    - -
    -
    - - - - -
    #define USB_OTG_GOTGINT_ADTOCHG_Pos   (18U)
    -
    - -
    -
    - -

    ◆ USB_OTG_GOTGINT_ADTOCHG_Msk

    - -
    -
    - - - - -
    #define USB_OTG_GOTGINT_ADTOCHG_Msk   (0x1UL << USB_OTG_GOTGINT_ADTOCHG_Pos)
    -
    -

    0x00040000

    - -
    -
    - -

    ◆ USB_OTG_GOTGINT_ADTOCHG

    - -
    -
    - - - - -
    #define USB_OTG_GOTGINT_ADTOCHG   USB_OTG_GOTGINT_ADTOCHG_Msk
    -
    -

    A-device timeout change
    -

    - -
    -
    - -

    ◆ USB_OTG_GOTGINT_DBCDNE_Pos

    - -
    -
    - - - - -
    #define USB_OTG_GOTGINT_DBCDNE_Pos   (19U)
    -
    - -
    -
    - -

    ◆ USB_OTG_GOTGINT_DBCDNE_Msk

    - -
    -
    - - - - -
    #define USB_OTG_GOTGINT_DBCDNE_Msk   (0x1UL << USB_OTG_GOTGINT_DBCDNE_Pos)
    -
    -

    0x00080000

    - -
    -
    - -

    ◆ USB_OTG_GOTGINT_DBCDNE

    - -
    -
    - - - - -
    #define USB_OTG_GOTGINT_DBCDNE   USB_OTG_GOTGINT_DBCDNE_Msk
    -
    -

    Debounce done
    -

    - -
    -
    - -

    ◆ USB_OTG_DCTL_RWUSIG_Pos

    - -
    -
    - - - - -
    #define USB_OTG_DCTL_RWUSIG_Pos   (0U)
    -
    - -
    -
    - -

    ◆ USB_OTG_DCTL_RWUSIG_Msk

    - -
    -
    - - - - -
    #define USB_OTG_DCTL_RWUSIG_Msk   (0x1UL << USB_OTG_DCTL_RWUSIG_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ USB_OTG_DCTL_RWUSIG

    - -
    -
    - - - - -
    #define USB_OTG_DCTL_RWUSIG   USB_OTG_DCTL_RWUSIG_Msk
    -
    -

    Remote wakeup signaling

    - -
    -
    - -

    ◆ USB_OTG_DCTL_SDIS_Pos

    - -
    -
    - - - - -
    #define USB_OTG_DCTL_SDIS_Pos   (1U)
    -
    - -
    -
    - -

    ◆ USB_OTG_DCTL_SDIS_Msk

    - -
    -
    - - - - -
    #define USB_OTG_DCTL_SDIS_Msk   (0x1UL << USB_OTG_DCTL_SDIS_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ USB_OTG_DCTL_SDIS

    - -
    -
    - - - - -
    #define USB_OTG_DCTL_SDIS   USB_OTG_DCTL_SDIS_Msk
    -
    -

    Soft disconnect
    -

    - -
    -
    - -

    ◆ USB_OTG_DCTL_GINSTS_Pos

    - -
    -
    - - - - -
    #define USB_OTG_DCTL_GINSTS_Pos   (2U)
    -
    - -
    -
    - -

    ◆ USB_OTG_DCTL_GINSTS_Msk

    - -
    -
    - - - - -
    #define USB_OTG_DCTL_GINSTS_Msk   (0x1UL << USB_OTG_DCTL_GINSTS_Pos)
    -
    -

    0x00000004

    - -
    -
    - -

    ◆ USB_OTG_DCTL_GINSTS

    - -
    -
    - - - - -
    #define USB_OTG_DCTL_GINSTS   USB_OTG_DCTL_GINSTS_Msk
    -
    -

    Global IN NAK status
    -

    - -
    -
    - -

    ◆ USB_OTG_DCTL_GONSTS_Pos

    - -
    -
    - - - - -
    #define USB_OTG_DCTL_GONSTS_Pos   (3U)
    -
    - -
    -
    - -

    ◆ USB_OTG_DCTL_GONSTS_Msk

    - -
    -
    - - - - -
    #define USB_OTG_DCTL_GONSTS_Msk   (0x1UL << USB_OTG_DCTL_GONSTS_Pos)
    -
    -

    0x00000008

    - -
    -
    - -

    ◆ USB_OTG_DCTL_GONSTS

    - -
    -
    - - - - -
    #define USB_OTG_DCTL_GONSTS   USB_OTG_DCTL_GONSTS_Msk
    -
    -

    Global OUT NAK status
    -

    - -
    -
    - -

    ◆ USB_OTG_DCTL_TCTL_Pos

    - -
    -
    - - - - -
    #define USB_OTG_DCTL_TCTL_Pos   (4U)
    -
    - -
    -
    - -

    ◆ USB_OTG_DCTL_TCTL_Msk

    - -
    -
    - - - - -
    #define USB_OTG_DCTL_TCTL_Msk   (0x7UL << USB_OTG_DCTL_TCTL_Pos)
    -
    -

    0x00000070

    - -
    -
    - -

    ◆ USB_OTG_DCTL_TCTL

    - -
    -
    - - - - -
    #define USB_OTG_DCTL_TCTL   USB_OTG_DCTL_TCTL_Msk
    -
    -

    Test control

    - -
    -
    - -

    ◆ USB_OTG_DCTL_TCTL_0

    - -
    -
    - - - - -
    #define USB_OTG_DCTL_TCTL_0   (0x1UL << USB_OTG_DCTL_TCTL_Pos)
    -
    -

    0x00000010

    - -
    -
    - -

    ◆ USB_OTG_DCTL_TCTL_1

    - -
    -
    - - - - -
    #define USB_OTG_DCTL_TCTL_1   (0x2UL << USB_OTG_DCTL_TCTL_Pos)
    -
    -

    0x00000020

    - -
    -
    - -

    ◆ USB_OTG_DCTL_TCTL_2

    - -
    -
    - - - - -
    #define USB_OTG_DCTL_TCTL_2   (0x4UL << USB_OTG_DCTL_TCTL_Pos)
    -
    -

    0x00000040

    - -
    -
    - -

    ◆ USB_OTG_DCTL_SGINAK_Pos

    - -
    -
    - - - - -
    #define USB_OTG_DCTL_SGINAK_Pos   (7U)
    -
    - -
    -
    - -

    ◆ USB_OTG_DCTL_SGINAK_Msk

    - -
    -
    - - - - -
    #define USB_OTG_DCTL_SGINAK_Msk   (0x1UL << USB_OTG_DCTL_SGINAK_Pos)
    -
    -

    0x00000080

    - -
    -
    - -

    ◆ USB_OTG_DCTL_SGINAK

    - -
    -
    - - - - -
    #define USB_OTG_DCTL_SGINAK   USB_OTG_DCTL_SGINAK_Msk
    -
    -

    Set global IN NAK
    -

    - -
    -
    - -

    ◆ USB_OTG_DCTL_CGINAK_Pos

    - -
    -
    - - - - -
    #define USB_OTG_DCTL_CGINAK_Pos   (8U)
    -
    - -
    -
    - -

    ◆ USB_OTG_DCTL_CGINAK_Msk

    - -
    -
    - - - - -
    #define USB_OTG_DCTL_CGINAK_Msk   (0x1UL << USB_OTG_DCTL_CGINAK_Pos)
    -
    -

    0x00000100

    - -
    -
    - -

    ◆ USB_OTG_DCTL_CGINAK

    - -
    -
    - - - - -
    #define USB_OTG_DCTL_CGINAK   USB_OTG_DCTL_CGINAK_Msk
    -
    -

    Clear global IN NAK
    -

    - -
    -
    - -

    ◆ USB_OTG_DCTL_SGONAK_Pos

    - -
    -
    - - - - -
    #define USB_OTG_DCTL_SGONAK_Pos   (9U)
    -
    - -
    -
    - -

    ◆ USB_OTG_DCTL_SGONAK_Msk

    - -
    -
    - - - - -
    #define USB_OTG_DCTL_SGONAK_Msk   (0x1UL << USB_OTG_DCTL_SGONAK_Pos)
    -
    -

    0x00000200

    - -
    -
    - -

    ◆ USB_OTG_DCTL_SGONAK

    - -
    -
    - - - - -
    #define USB_OTG_DCTL_SGONAK   USB_OTG_DCTL_SGONAK_Msk
    -
    -

    Set global OUT NAK
    -

    - -
    -
    - -

    ◆ USB_OTG_DCTL_CGONAK_Pos

    - -
    -
    - - - - -
    #define USB_OTG_DCTL_CGONAK_Pos   (10U)
    -
    - -
    -
    - -

    ◆ USB_OTG_DCTL_CGONAK_Msk

    - -
    -
    - - - - -
    #define USB_OTG_DCTL_CGONAK_Msk   (0x1UL << USB_OTG_DCTL_CGONAK_Pos)
    -
    -

    0x00000400

    - -
    -
    - -

    ◆ USB_OTG_DCTL_CGONAK

    - -
    -
    - - - - -
    #define USB_OTG_DCTL_CGONAK   USB_OTG_DCTL_CGONAK_Msk
    -
    -

    Clear global OUT NAK
    -

    - -
    -
    - -

    ◆ USB_OTG_DCTL_POPRGDNE_Pos

    - -
    -
    - - - - -
    #define USB_OTG_DCTL_POPRGDNE_Pos   (11U)
    -
    - -
    -
    - -

    ◆ USB_OTG_DCTL_POPRGDNE_Msk

    - -
    -
    - - - - -
    #define USB_OTG_DCTL_POPRGDNE_Msk   (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos)
    -
    -

    0x00000800

    - -
    -
    - -

    ◆ USB_OTG_DCTL_POPRGDNE

    - -
    -
    - - - - -
    #define USB_OTG_DCTL_POPRGDNE   USB_OTG_DCTL_POPRGDNE_Msk
    -
    -

    Power-on programming done

    - -
    -
    - -

    ◆ USB_OTG_HFIR_FRIVL_Pos

    - -
    -
    - - - - -
    #define USB_OTG_HFIR_FRIVL_Pos   (0U)
    -
    - -
    -
    - -

    ◆ USB_OTG_HFIR_FRIVL_Msk

    - -
    -
    - - - - -
    #define USB_OTG_HFIR_FRIVL_Msk   (0xFFFFUL << USB_OTG_HFIR_FRIVL_Pos)
    -
    -

    0x0000FFFF

    - -
    -
    - -

    ◆ USB_OTG_HFIR_FRIVL

    - -
    -
    - - - - -
    #define USB_OTG_HFIR_FRIVL   USB_OTG_HFIR_FRIVL_Msk
    -
    -

    Frame interval

    - -
    -
    - -

    ◆ USB_OTG_HFNUM_FRNUM_Pos

    - -
    -
    - - - - -
    #define USB_OTG_HFNUM_FRNUM_Pos   (0U)
    -
    - -
    -
    - -

    ◆ USB_OTG_HFNUM_FRNUM_Msk

    - -
    -
    - - - - -
    #define USB_OTG_HFNUM_FRNUM_Msk   (0xFFFFUL << USB_OTG_HFNUM_FRNUM_Pos)
    -
    -

    0x0000FFFF

    - -
    -
    - -

    ◆ USB_OTG_HFNUM_FRNUM

    - -
    -
    - - - - -
    #define USB_OTG_HFNUM_FRNUM   USB_OTG_HFNUM_FRNUM_Msk
    -
    -

    Frame number
    -

    - -
    -
    - -

    ◆ USB_OTG_HFNUM_FTREM_Pos

    - -
    -
    - - - - -
    #define USB_OTG_HFNUM_FTREM_Pos   (16U)
    -
    - -
    -
    - -

    ◆ USB_OTG_HFNUM_FTREM_Msk

    - -
    -
    - - - - -
    #define USB_OTG_HFNUM_FTREM_Msk   (0xFFFFUL << USB_OTG_HFNUM_FTREM_Pos)
    -
    -

    0xFFFF0000

    - -
    -
    - -

    ◆ USB_OTG_HFNUM_FTREM

    - -
    -
    - - - - -
    #define USB_OTG_HFNUM_FTREM   USB_OTG_HFNUM_FTREM_Msk
    -
    -

    Frame time remaining

    - -
    -
    - -

    ◆ USB_OTG_DSTS_SUSPSTS_Pos

    - -
    -
    - - - - -
    #define USB_OTG_DSTS_SUSPSTS_Pos   (0U)
    -
    - -
    -
    - -

    ◆ USB_OTG_DSTS_SUSPSTS_Msk

    - -
    -
    - - - - -
    #define USB_OTG_DSTS_SUSPSTS_Msk   (0x1UL << USB_OTG_DSTS_SUSPSTS_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ USB_OTG_DSTS_SUSPSTS

    - -
    -
    - - - - -
    #define USB_OTG_DSTS_SUSPSTS   USB_OTG_DSTS_SUSPSTS_Msk
    -
    -

    Suspend status
    -

    - -
    -
    - -

    ◆ USB_OTG_DSTS_ENUMSPD_Pos

    - -
    -
    - - - - -
    #define USB_OTG_DSTS_ENUMSPD_Pos   (1U)
    -
    - -
    -
    - -

    ◆ USB_OTG_DSTS_ENUMSPD_Msk

    - -
    -
    - - - - -
    #define USB_OTG_DSTS_ENUMSPD_Msk   (0x3UL << USB_OTG_DSTS_ENUMSPD_Pos)
    -
    -

    0x00000006

    - -
    -
    - -

    ◆ USB_OTG_DSTS_ENUMSPD

    - -
    -
    - - - - -
    #define USB_OTG_DSTS_ENUMSPD   USB_OTG_DSTS_ENUMSPD_Msk
    -
    -

    Enumerated speed

    - -
    -
    - -

    ◆ USB_OTG_DSTS_ENUMSPD_0

    - -
    -
    - - - - -
    #define USB_OTG_DSTS_ENUMSPD_0   (0x1UL << USB_OTG_DSTS_ENUMSPD_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ USB_OTG_DSTS_ENUMSPD_1

    - -
    -
    - - - - -
    #define USB_OTG_DSTS_ENUMSPD_1   (0x2UL << USB_OTG_DSTS_ENUMSPD_Pos)
    -
    -

    0x00000004

    - -
    -
    - -

    ◆ USB_OTG_DSTS_EERR_Pos

    - -
    -
    - - - - -
    #define USB_OTG_DSTS_EERR_Pos   (3U)
    -
    - -
    -
    - -

    ◆ USB_OTG_DSTS_EERR_Msk

    - -
    -
    - - - - -
    #define USB_OTG_DSTS_EERR_Msk   (0x1UL << USB_OTG_DSTS_EERR_Pos)
    -
    -

    0x00000008

    - -
    -
    - -

    ◆ USB_OTG_DSTS_EERR

    - -
    -
    - - - - -
    #define USB_OTG_DSTS_EERR   USB_OTG_DSTS_EERR_Msk
    -
    -

    Erratic error
    -

    - -
    -
    - -

    ◆ USB_OTG_DSTS_FNSOF_Pos

    - -
    -
    - - - - -
    #define USB_OTG_DSTS_FNSOF_Pos   (8U)
    -
    - -
    -
    - -

    ◆ USB_OTG_DSTS_FNSOF_Msk

    - -
    -
    - - - - -
    #define USB_OTG_DSTS_FNSOF_Msk   (0x3FFFUL << USB_OTG_DSTS_FNSOF_Pos)
    -
    -

    0x003FFF00

    - -
    -
    - -

    ◆ USB_OTG_DSTS_FNSOF

    - -
    -
    - - - - -
    #define USB_OTG_DSTS_FNSOF   USB_OTG_DSTS_FNSOF_Msk
    -
    -

    Frame number of the received SOF

    - -
    -
    - -

    ◆ USB_OTG_GAHBCFG_GINT_Pos

    - -
    -
    - - - - -
    #define USB_OTG_GAHBCFG_GINT_Pos   (0U)
    -
    - -
    -
    - -

    ◆ USB_OTG_GAHBCFG_GINT_Msk

    - -
    -
    - - - - -
    #define USB_OTG_GAHBCFG_GINT_Msk   (0x1UL << USB_OTG_GAHBCFG_GINT_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ USB_OTG_GAHBCFG_GINT

    - -
    -
    - - - - -
    #define USB_OTG_GAHBCFG_GINT   USB_OTG_GAHBCFG_GINT_Msk
    -
    -

    Global interrupt mask

    - -
    -
    - -

    ◆ USB_OTG_GAHBCFG_HBSTLEN_Pos

    - -
    -
    - - - - -
    #define USB_OTG_GAHBCFG_HBSTLEN_Pos   (1U)
    -
    - -
    -
    - -

    ◆ USB_OTG_GAHBCFG_HBSTLEN_Msk

    - -
    -
    - - - - -
    #define USB_OTG_GAHBCFG_HBSTLEN_Msk   (0xFUL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
    -
    -

    0x0000001E

    - -
    -
    - -

    ◆ USB_OTG_GAHBCFG_HBSTLEN

    - -
    -
    - - - - -
    #define USB_OTG_GAHBCFG_HBSTLEN   USB_OTG_GAHBCFG_HBSTLEN_Msk
    -
    -

    Burst length/type

    - -
    -
    - -

    ◆ USB_OTG_GAHBCFG_HBSTLEN_0

    - -
    -
    - - - - -
    #define USB_OTG_GAHBCFG_HBSTLEN_0   (0x0UL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
    -
    -

    Single

    - -
    -
    - -

    ◆ USB_OTG_GAHBCFG_HBSTLEN_1

    - -
    -
    - - - - -
    #define USB_OTG_GAHBCFG_HBSTLEN_1   (0x1UL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
    -
    -

    INCR

    - -
    -
    - -

    ◆ USB_OTG_GAHBCFG_HBSTLEN_2

    - -
    -
    - - - - -
    #define USB_OTG_GAHBCFG_HBSTLEN_2   (0x3UL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
    -
    -

    INCR4

    - -
    -
    - -

    ◆ USB_OTG_GAHBCFG_HBSTLEN_3

    - -
    -
    - - - - -
    #define USB_OTG_GAHBCFG_HBSTLEN_3   (0x5UL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
    -
    -

    INCR8

    - -
    -
    - -

    ◆ USB_OTG_GAHBCFG_HBSTLEN_4

    - -
    -
    - - - - -
    #define USB_OTG_GAHBCFG_HBSTLEN_4   (0x7UL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
    -
    -

    INCR16

    - -
    -
    - -

    ◆ USB_OTG_GAHBCFG_DMAEN_Pos

    - -
    -
    - - - - -
    #define USB_OTG_GAHBCFG_DMAEN_Pos   (5U)
    -
    - -
    -
    - -

    ◆ USB_OTG_GAHBCFG_DMAEN_Msk

    - -
    -
    - - - - -
    #define USB_OTG_GAHBCFG_DMAEN_Msk   (0x1UL << USB_OTG_GAHBCFG_DMAEN_Pos)
    -
    -

    0x00000020

    - -
    -
    - -

    ◆ USB_OTG_GAHBCFG_DMAEN

    - -
    -
    - - - - -
    #define USB_OTG_GAHBCFG_DMAEN   USB_OTG_GAHBCFG_DMAEN_Msk
    -
    -

    DMA enable

    - -
    -
    - -

    ◆ USB_OTG_GAHBCFG_TXFELVL_Pos

    - -
    -
    - - - - -
    #define USB_OTG_GAHBCFG_TXFELVL_Pos   (7U)
    -
    - -
    -
    - -

    ◆ USB_OTG_GAHBCFG_TXFELVL_Msk

    - -
    -
    - - - - -
    #define USB_OTG_GAHBCFG_TXFELVL_Msk   (0x1UL << USB_OTG_GAHBCFG_TXFELVL_Pos)
    -
    -

    0x00000080

    - -
    -
    - -

    ◆ USB_OTG_GAHBCFG_TXFELVL

    - -
    -
    - - - - -
    #define USB_OTG_GAHBCFG_TXFELVL   USB_OTG_GAHBCFG_TXFELVL_Msk
    -
    -

    TxFIFO empty level

    - -
    -
    - -

    ◆ USB_OTG_GAHBCFG_PTXFELVL_Pos

    - -
    -
    - - - - -
    #define USB_OTG_GAHBCFG_PTXFELVL_Pos   (8U)
    -
    - -
    -
    - -

    ◆ USB_OTG_GAHBCFG_PTXFELVL_Msk

    - -
    -
    - - - - -
    #define USB_OTG_GAHBCFG_PTXFELVL_Msk   (0x1UL << USB_OTG_GAHBCFG_PTXFELVL_Pos)
    -
    -

    0x00000100

    - -
    -
    - -

    ◆ USB_OTG_GAHBCFG_PTXFELVL

    - -
    -
    - - - - -
    #define USB_OTG_GAHBCFG_PTXFELVL   USB_OTG_GAHBCFG_PTXFELVL_Msk
    -
    -

    Periodic TxFIFO empty level

    - -
    -
    - -

    ◆ USB_OTG_GUSBCFG_TOCAL_Pos

    - -
    -
    - - - - -
    #define USB_OTG_GUSBCFG_TOCAL_Pos   (0U)
    -
    - -
    -
    - -

    ◆ USB_OTG_GUSBCFG_TOCAL_Msk

    - -
    -
    - - - - -
    #define USB_OTG_GUSBCFG_TOCAL_Msk   (0x7UL << USB_OTG_GUSBCFG_TOCAL_Pos)
    -
    -

    0x00000007

    - -
    -
    - -

    ◆ USB_OTG_GUSBCFG_TOCAL

    - -
    -
    - - - - -
    #define USB_OTG_GUSBCFG_TOCAL   USB_OTG_GUSBCFG_TOCAL_Msk
    -
    -

    FS timeout calibration

    - -
    -
    - -

    ◆ USB_OTG_GUSBCFG_TOCAL_0

    - -
    -
    - - - - -
    #define USB_OTG_GUSBCFG_TOCAL_0   (0x1UL << USB_OTG_GUSBCFG_TOCAL_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ USB_OTG_GUSBCFG_TOCAL_1

    - -
    -
    - - - - -
    #define USB_OTG_GUSBCFG_TOCAL_1   (0x2UL << USB_OTG_GUSBCFG_TOCAL_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ USB_OTG_GUSBCFG_TOCAL_2

    - -
    -
    - - - - -
    #define USB_OTG_GUSBCFG_TOCAL_2   (0x4UL << USB_OTG_GUSBCFG_TOCAL_Pos)
    -
    -

    0x00000004

    - -
    -
    - -

    ◆ USB_OTG_GUSBCFG_PHYSEL_Pos

    - -
    -
    - - - - -
    #define USB_OTG_GUSBCFG_PHYSEL_Pos   (6U)
    -
    - -
    -
    - -

    ◆ USB_OTG_GUSBCFG_PHYSEL_Msk

    - -
    -
    - - - - -
    #define USB_OTG_GUSBCFG_PHYSEL_Msk   (0x1UL << USB_OTG_GUSBCFG_PHYSEL_Pos)
    -
    -

    0x00000040

    - -
    -
    - -

    ◆ USB_OTG_GUSBCFG_PHYSEL

    - -
    -
    - - - - -
    #define USB_OTG_GUSBCFG_PHYSEL   USB_OTG_GUSBCFG_PHYSEL_Msk
    -
    -

    USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select

    - -
    -
    - -

    ◆ USB_OTG_GUSBCFG_SRPCAP_Pos

    - -
    -
    - - - - -
    #define USB_OTG_GUSBCFG_SRPCAP_Pos   (8U)
    -
    - -
    -
    - -

    ◆ USB_OTG_GUSBCFG_SRPCAP_Msk

    - -
    -
    - - - - -
    #define USB_OTG_GUSBCFG_SRPCAP_Msk   (0x1UL << USB_OTG_GUSBCFG_SRPCAP_Pos)
    -
    -

    0x00000100

    - -
    -
    - -

    ◆ USB_OTG_GUSBCFG_SRPCAP

    - -
    -
    - - - - -
    #define USB_OTG_GUSBCFG_SRPCAP   USB_OTG_GUSBCFG_SRPCAP_Msk
    -
    -

    SRP-capable

    - -
    -
    - -

    ◆ USB_OTG_GUSBCFG_HNPCAP_Pos

    - -
    -
    - - - - -
    #define USB_OTG_GUSBCFG_HNPCAP_Pos   (9U)
    -
    - -
    -
    - -

    ◆ USB_OTG_GUSBCFG_HNPCAP_Msk

    - -
    -
    - - - - -
    #define USB_OTG_GUSBCFG_HNPCAP_Msk   (0x1UL << USB_OTG_GUSBCFG_HNPCAP_Pos)
    -
    -

    0x00000200

    - -
    -
    - -

    ◆ USB_OTG_GUSBCFG_HNPCAP

    - -
    -
    - - - - -
    #define USB_OTG_GUSBCFG_HNPCAP   USB_OTG_GUSBCFG_HNPCAP_Msk
    -
    -

    HNP-capable

    - -
    -
    - -

    ◆ USB_OTG_GUSBCFG_TRDT_Pos

    - -
    -
    - - - - -
    #define USB_OTG_GUSBCFG_TRDT_Pos   (10U)
    -
    - -
    -
    - -

    ◆ USB_OTG_GUSBCFG_TRDT_Msk

    - -
    -
    - - - - -
    #define USB_OTG_GUSBCFG_TRDT_Msk   (0xFUL << USB_OTG_GUSBCFG_TRDT_Pos)
    -
    -

    0x00003C00

    - -
    -
    - -

    ◆ USB_OTG_GUSBCFG_TRDT

    - -
    -
    - - - - -
    #define USB_OTG_GUSBCFG_TRDT   USB_OTG_GUSBCFG_TRDT_Msk
    -
    -

    USB turnaround time

    - -
    -
    - -

    ◆ USB_OTG_GUSBCFG_TRDT_0

    - -
    -
    - - - - -
    #define USB_OTG_GUSBCFG_TRDT_0   (0x1UL << USB_OTG_GUSBCFG_TRDT_Pos)
    -
    -

    0x00000400

    - -
    -
    - -

    ◆ USB_OTG_GUSBCFG_TRDT_1

    - -
    -
    - - - - -
    #define USB_OTG_GUSBCFG_TRDT_1   (0x2UL << USB_OTG_GUSBCFG_TRDT_Pos)
    -
    -

    0x00000800

    - -
    -
    - -

    ◆ USB_OTG_GUSBCFG_TRDT_2

    - -
    -
    - - - - -
    #define USB_OTG_GUSBCFG_TRDT_2   (0x4UL << USB_OTG_GUSBCFG_TRDT_Pos)
    -
    -

    0x00001000

    - -
    -
    - -

    ◆ USB_OTG_GUSBCFG_TRDT_3

    - -
    -
    - - - - -
    #define USB_OTG_GUSBCFG_TRDT_3   (0x8UL << USB_OTG_GUSBCFG_TRDT_Pos)
    -
    -

    0x00002000

    - -
    -
    - -

    ◆ USB_OTG_GUSBCFG_PHYLPCS_Pos

    - -
    -
    - - - - -
    #define USB_OTG_GUSBCFG_PHYLPCS_Pos   (15U)
    -
    - -
    -
    - -

    ◆ USB_OTG_GUSBCFG_PHYLPCS_Msk

    - -
    -
    - - - - -
    #define USB_OTG_GUSBCFG_PHYLPCS_Msk   (0x1UL << USB_OTG_GUSBCFG_PHYLPCS_Pos)
    -
    -

    0x00008000

    - -
    -
    - -

    ◆ USB_OTG_GUSBCFG_PHYLPCS

    - -
    -
    - - - - -
    #define USB_OTG_GUSBCFG_PHYLPCS   USB_OTG_GUSBCFG_PHYLPCS_Msk
    -
    -

    PHY Low-power clock select

    - -
    -
    - -

    ◆ USB_OTG_GUSBCFG_ULPIFSLS_Pos

    - -
    -
    - - - - -
    #define USB_OTG_GUSBCFG_ULPIFSLS_Pos   (17U)
    -
    - -
    -
    - -

    ◆ USB_OTG_GUSBCFG_ULPIFSLS_Msk

    - -
    -
    - - - - -
    #define USB_OTG_GUSBCFG_ULPIFSLS_Msk   (0x1UL << USB_OTG_GUSBCFG_ULPIFSLS_Pos)
    -
    -

    0x00020000

    - -
    -
    - -

    ◆ USB_OTG_GUSBCFG_ULPIFSLS

    - -
    -
    - - - - -
    #define USB_OTG_GUSBCFG_ULPIFSLS   USB_OTG_GUSBCFG_ULPIFSLS_Msk
    -
    -

    ULPI FS/LS select
    -

    - -
    -
    - -

    ◆ USB_OTG_GUSBCFG_ULPIAR_Pos

    - -
    -
    - - - - -
    #define USB_OTG_GUSBCFG_ULPIAR_Pos   (18U)
    -
    - -
    -
    - -

    ◆ USB_OTG_GUSBCFG_ULPIAR_Msk

    - -
    -
    - - - - -
    #define USB_OTG_GUSBCFG_ULPIAR_Msk   (0x1UL << USB_OTG_GUSBCFG_ULPIAR_Pos)
    -
    -

    0x00040000

    - -
    -
    - -

    ◆ USB_OTG_GUSBCFG_ULPIAR

    - -
    -
    - - - - -
    #define USB_OTG_GUSBCFG_ULPIAR   USB_OTG_GUSBCFG_ULPIAR_Msk
    -
    -

    ULPI Auto-resume
    -

    - -
    -
    - -

    ◆ USB_OTG_GUSBCFG_ULPICSM_Pos

    - -
    -
    - - - - -
    #define USB_OTG_GUSBCFG_ULPICSM_Pos   (19U)
    -
    - -
    -
    - -

    ◆ USB_OTG_GUSBCFG_ULPICSM_Msk

    - -
    -
    - - - - -
    #define USB_OTG_GUSBCFG_ULPICSM_Msk   (0x1UL << USB_OTG_GUSBCFG_ULPICSM_Pos)
    -
    -

    0x00080000

    - -
    -
    - -

    ◆ USB_OTG_GUSBCFG_ULPICSM

    - -
    -
    - - - - -
    #define USB_OTG_GUSBCFG_ULPICSM   USB_OTG_GUSBCFG_ULPICSM_Msk
    -
    -

    ULPI Clock SuspendM
    -

    - -
    -
    - -

    ◆ USB_OTG_GUSBCFG_ULPIEVBUSD_Pos

    - -
    -
    - - - - -
    #define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos   (20U)
    -
    - -
    -
    - -

    ◆ USB_OTG_GUSBCFG_ULPIEVBUSD_Msk

    - -
    -
    - - - - -
    #define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk   (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos)
    -
    -

    0x00100000

    - -
    -
    - -

    ◆ USB_OTG_GUSBCFG_ULPIEVBUSD

    - -
    -
    - - - - -
    #define USB_OTG_GUSBCFG_ULPIEVBUSD   USB_OTG_GUSBCFG_ULPIEVBUSD_Msk
    -
    -

    ULPI External VBUS Drive
    -

    - -
    -
    - -

    ◆ USB_OTG_GUSBCFG_ULPIEVBUSI_Pos

    - -
    -
    - - - - -
    #define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos   (21U)
    -
    - -
    -
    - -

    ◆ USB_OTG_GUSBCFG_ULPIEVBUSI_Msk

    - -
    -
    - - - - -
    #define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk   (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos)
    -
    -

    0x00200000

    - -
    -
    - -

    ◆ USB_OTG_GUSBCFG_ULPIEVBUSI

    - -
    -
    - - - - -
    #define USB_OTG_GUSBCFG_ULPIEVBUSI   USB_OTG_GUSBCFG_ULPIEVBUSI_Msk
    -
    -

    ULPI external VBUS indicator
    -

    - -
    -
    - -

    ◆ USB_OTG_GUSBCFG_TSDPS_Pos

    - -
    -
    - - - - -
    #define USB_OTG_GUSBCFG_TSDPS_Pos   (22U)
    -
    - -
    -
    - -

    ◆ USB_OTG_GUSBCFG_TSDPS_Msk

    - -
    -
    - - - - -
    #define USB_OTG_GUSBCFG_TSDPS_Msk   (0x1UL << USB_OTG_GUSBCFG_TSDPS_Pos)
    -
    -

    0x00400000

    - -
    -
    - -

    ◆ USB_OTG_GUSBCFG_TSDPS

    - -
    -
    - - - - -
    #define USB_OTG_GUSBCFG_TSDPS   USB_OTG_GUSBCFG_TSDPS_Msk
    -
    -

    TermSel DLine pulsing selection

    - -
    -
    - -

    ◆ USB_OTG_GUSBCFG_PCCI_Pos

    - -
    -
    - - - - -
    #define USB_OTG_GUSBCFG_PCCI_Pos   (23U)
    -
    - -
    -
    - -

    ◆ USB_OTG_GUSBCFG_PCCI_Msk

    - -
    -
    - - - - -
    #define USB_OTG_GUSBCFG_PCCI_Msk   (0x1UL << USB_OTG_GUSBCFG_PCCI_Pos)
    -
    -

    0x00800000

    - -
    -
    - -

    ◆ USB_OTG_GUSBCFG_PCCI

    - -
    -
    - - - - -
    #define USB_OTG_GUSBCFG_PCCI   USB_OTG_GUSBCFG_PCCI_Msk
    -
    -

    Indicator complement
    -

    - -
    -
    - -

    ◆ USB_OTG_GUSBCFG_PTCI_Pos

    - -
    -
    - - - - -
    #define USB_OTG_GUSBCFG_PTCI_Pos   (24U)
    -
    - -
    -
    - -

    ◆ USB_OTG_GUSBCFG_PTCI_Msk

    - -
    -
    - - - - -
    #define USB_OTG_GUSBCFG_PTCI_Msk   (0x1UL << USB_OTG_GUSBCFG_PTCI_Pos)
    -
    -

    0x01000000

    - -
    -
    - -

    ◆ USB_OTG_GUSBCFG_PTCI

    - -
    -
    - - - - -
    #define USB_OTG_GUSBCFG_PTCI   USB_OTG_GUSBCFG_PTCI_Msk
    -
    -

    Indicator pass through
    -

    - -
    -
    - -

    ◆ USB_OTG_GUSBCFG_ULPIIPD_Pos

    - -
    -
    - - - - -
    #define USB_OTG_GUSBCFG_ULPIIPD_Pos   (25U)
    -
    - -
    -
    - -

    ◆ USB_OTG_GUSBCFG_ULPIIPD_Msk

    - -
    -
    - - - - -
    #define USB_OTG_GUSBCFG_ULPIIPD_Msk   (0x1UL << USB_OTG_GUSBCFG_ULPIIPD_Pos)
    -
    -

    0x02000000

    - -
    -
    - -

    ◆ USB_OTG_GUSBCFG_ULPIIPD

    - -
    -
    - - - - -
    #define USB_OTG_GUSBCFG_ULPIIPD   USB_OTG_GUSBCFG_ULPIIPD_Msk
    -
    -

    ULPI interface protect disable
    -

    - -
    -
    - -

    ◆ USB_OTG_GUSBCFG_FHMOD_Pos

    - -
    -
    - - - - -
    #define USB_OTG_GUSBCFG_FHMOD_Pos   (29U)
    -
    - -
    -
    - -

    ◆ USB_OTG_GUSBCFG_FHMOD_Msk

    - -
    -
    - - - - -
    #define USB_OTG_GUSBCFG_FHMOD_Msk   (0x1UL << USB_OTG_GUSBCFG_FHMOD_Pos)
    -
    -

    0x20000000

    - -
    -
    - -

    ◆ USB_OTG_GUSBCFG_FHMOD

    - -
    -
    - - - - -
    #define USB_OTG_GUSBCFG_FHMOD   USB_OTG_GUSBCFG_FHMOD_Msk
    -
    -

    Forced host mode
    -

    - -
    -
    - -

    ◆ USB_OTG_GUSBCFG_FDMOD_Pos

    - -
    -
    - - - - -
    #define USB_OTG_GUSBCFG_FDMOD_Pos   (30U)
    -
    - -
    -
    - -

    ◆ USB_OTG_GUSBCFG_FDMOD_Msk

    - -
    -
    - - - - -
    #define USB_OTG_GUSBCFG_FDMOD_Msk   (0x1UL << USB_OTG_GUSBCFG_FDMOD_Pos)
    -
    -

    0x40000000

    - -
    -
    - -

    ◆ USB_OTG_GUSBCFG_FDMOD

    - -
    -
    - - - - -
    #define USB_OTG_GUSBCFG_FDMOD   USB_OTG_GUSBCFG_FDMOD_Msk
    -
    -

    Forced peripheral mode
    -

    - -
    -
    - -

    ◆ USB_OTG_GUSBCFG_CTXPKT_Pos

    - -
    -
    - - - - -
    #define USB_OTG_GUSBCFG_CTXPKT_Pos   (31U)
    -
    - -
    -
    - -

    ◆ USB_OTG_GUSBCFG_CTXPKT_Msk

    - -
    -
    - - - - -
    #define USB_OTG_GUSBCFG_CTXPKT_Msk   (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos)
    -
    -

    0x80000000

    - -
    -
    - -

    ◆ USB_OTG_GUSBCFG_CTXPKT

    - -
    -
    - - - - -
    #define USB_OTG_GUSBCFG_CTXPKT   USB_OTG_GUSBCFG_CTXPKT_Msk
    -
    -

    Corrupt Tx packet
    -

    - -
    -
    - -

    ◆ USB_OTG_GRSTCTL_CSRST_Pos

    - -
    -
    - - - - -
    #define USB_OTG_GRSTCTL_CSRST_Pos   (0U)
    -
    - -
    -
    - -

    ◆ USB_OTG_GRSTCTL_CSRST_Msk

    - -
    -
    - - - - -
    #define USB_OTG_GRSTCTL_CSRST_Msk   (0x1UL << USB_OTG_GRSTCTL_CSRST_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ USB_OTG_GRSTCTL_CSRST

    - -
    -
    - - - - -
    #define USB_OTG_GRSTCTL_CSRST   USB_OTG_GRSTCTL_CSRST_Msk
    -
    -

    Core soft reset
    -

    - -
    -
    - -

    ◆ USB_OTG_GRSTCTL_HSRST_Pos

    - -
    -
    - - - - -
    #define USB_OTG_GRSTCTL_HSRST_Pos   (1U)
    -
    - -
    -
    - -

    ◆ USB_OTG_GRSTCTL_HSRST_Msk

    - -
    -
    - - - - -
    #define USB_OTG_GRSTCTL_HSRST_Msk   (0x1UL << USB_OTG_GRSTCTL_HSRST_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ USB_OTG_GRSTCTL_HSRST

    - -
    -
    - - - - -
    #define USB_OTG_GRSTCTL_HSRST   USB_OTG_GRSTCTL_HSRST_Msk
    -
    -

    HCLK soft reset
    -

    - -
    -
    - -

    ◆ USB_OTG_GRSTCTL_FCRST_Pos

    - -
    -
    - - - - -
    #define USB_OTG_GRSTCTL_FCRST_Pos   (2U)
    -
    - -
    -
    - -

    ◆ USB_OTG_GRSTCTL_FCRST_Msk

    - -
    -
    - - - - -
    #define USB_OTG_GRSTCTL_FCRST_Msk   (0x1UL << USB_OTG_GRSTCTL_FCRST_Pos)
    -
    -

    0x00000004

    - -
    -
    - -

    ◆ USB_OTG_GRSTCTL_FCRST

    - -
    -
    - - - - -
    #define USB_OTG_GRSTCTL_FCRST   USB_OTG_GRSTCTL_FCRST_Msk
    -
    -

    Host frame counter reset

    - -
    -
    - -

    ◆ USB_OTG_GRSTCTL_RXFFLSH_Pos

    - -
    -
    - - - - -
    #define USB_OTG_GRSTCTL_RXFFLSH_Pos   (4U)
    -
    - -
    -
    - -

    ◆ USB_OTG_GRSTCTL_RXFFLSH_Msk

    - -
    -
    - - - - -
    #define USB_OTG_GRSTCTL_RXFFLSH_Msk   (0x1UL << USB_OTG_GRSTCTL_RXFFLSH_Pos)
    -
    -

    0x00000010

    - -
    -
    - -

    ◆ USB_OTG_GRSTCTL_RXFFLSH

    - -
    -
    - - - - -
    #define USB_OTG_GRSTCTL_RXFFLSH   USB_OTG_GRSTCTL_RXFFLSH_Msk
    -
    -

    RxFIFO flush
    -

    - -
    -
    - -

    ◆ USB_OTG_GRSTCTL_TXFFLSH_Pos

    - -
    -
    - - - - -
    #define USB_OTG_GRSTCTL_TXFFLSH_Pos   (5U)
    -
    - -
    -
    - -

    ◆ USB_OTG_GRSTCTL_TXFFLSH_Msk

    - -
    -
    - - - - -
    #define USB_OTG_GRSTCTL_TXFFLSH_Msk   (0x1UL << USB_OTG_GRSTCTL_TXFFLSH_Pos)
    -
    -

    0x00000020

    - -
    -
    - -

    ◆ USB_OTG_GRSTCTL_TXFFLSH

    - -
    -
    - - - - -
    #define USB_OTG_GRSTCTL_TXFFLSH   USB_OTG_GRSTCTL_TXFFLSH_Msk
    -
    -

    TxFIFO flush
    -

    - -
    -
    - -

    ◆ USB_OTG_GRSTCTL_TXFNUM_Pos

    - -
    -
    - - - - -
    #define USB_OTG_GRSTCTL_TXFNUM_Pos   (6U)
    -
    - -
    -
    - -

    ◆ USB_OTG_GRSTCTL_TXFNUM_Msk

    - -
    -
    - - - - -
    #define USB_OTG_GRSTCTL_TXFNUM_Msk   (0x1FUL << USB_OTG_GRSTCTL_TXFNUM_Pos)
    -
    -

    0x000007C0

    - -
    -
    - -

    ◆ USB_OTG_GRSTCTL_TXFNUM

    - -
    -
    - - - - -
    #define USB_OTG_GRSTCTL_TXFNUM   USB_OTG_GRSTCTL_TXFNUM_Msk
    -
    -

    TxFIFO number

    - -
    -
    - -

    ◆ USB_OTG_GRSTCTL_TXFNUM_0

    - -
    -
    - - - - -
    #define USB_OTG_GRSTCTL_TXFNUM_0   (0x01UL << USB_OTG_GRSTCTL_TXFNUM_Pos)
    -
    -

    0x00000040

    - -
    -
    - -

    ◆ USB_OTG_GRSTCTL_TXFNUM_1

    - -
    -
    - - - - -
    #define USB_OTG_GRSTCTL_TXFNUM_1   (0x02UL << USB_OTG_GRSTCTL_TXFNUM_Pos)
    -
    -

    0x00000080

    - -
    -
    - -

    ◆ USB_OTG_GRSTCTL_TXFNUM_2

    - -
    -
    - - - - -
    #define USB_OTG_GRSTCTL_TXFNUM_2   (0x04UL << USB_OTG_GRSTCTL_TXFNUM_Pos)
    -
    -

    0x00000100

    - -
    -
    - -

    ◆ USB_OTG_GRSTCTL_TXFNUM_3

    - -
    -
    - - - - -
    #define USB_OTG_GRSTCTL_TXFNUM_3   (0x08UL << USB_OTG_GRSTCTL_TXFNUM_Pos)
    -
    -

    0x00000200

    - -
    -
    - -

    ◆ USB_OTG_GRSTCTL_TXFNUM_4

    - -
    -
    - - - - -
    #define USB_OTG_GRSTCTL_TXFNUM_4   (0x10UL << USB_OTG_GRSTCTL_TXFNUM_Pos)
    -
    -

    0x00000400

    - -
    -
    - -

    ◆ USB_OTG_GRSTCTL_DMAREQ_Pos

    - -
    -
    - - - - -
    #define USB_OTG_GRSTCTL_DMAREQ_Pos   (30U)
    -
    - -
    -
    - -

    ◆ USB_OTG_GRSTCTL_DMAREQ_Msk

    - -
    -
    - - - - -
    #define USB_OTG_GRSTCTL_DMAREQ_Msk   (0x1UL << USB_OTG_GRSTCTL_DMAREQ_Pos)
    -
    -

    0x40000000

    - -
    -
    - -

    ◆ USB_OTG_GRSTCTL_DMAREQ

    - -
    -
    - - - - -
    #define USB_OTG_GRSTCTL_DMAREQ   USB_OTG_GRSTCTL_DMAREQ_Msk
    -
    -

    DMA request signal

    - -
    -
    - -

    ◆ USB_OTG_GRSTCTL_AHBIDL_Pos

    - -
    -
    - - - - -
    #define USB_OTG_GRSTCTL_AHBIDL_Pos   (31U)
    -
    - -
    -
    - -

    ◆ USB_OTG_GRSTCTL_AHBIDL_Msk

    - -
    -
    - - - - -
    #define USB_OTG_GRSTCTL_AHBIDL_Msk   (0x1UL << USB_OTG_GRSTCTL_AHBIDL_Pos)
    -
    -

    0x80000000

    - -
    -
    - -

    ◆ USB_OTG_GRSTCTL_AHBIDL

    - -
    -
    - - - - -
    #define USB_OTG_GRSTCTL_AHBIDL   USB_OTG_GRSTCTL_AHBIDL_Msk
    -
    -

    AHB master idle

    - -
    -
    - -

    ◆ USB_OTG_DIEPMSK_XFRCM_Pos

    - -
    -
    - - - - -
    #define USB_OTG_DIEPMSK_XFRCM_Pos   (0U)
    -
    - -
    -
    - -

    ◆ USB_OTG_DIEPMSK_XFRCM_Msk

    - -
    -
    - - - - -
    #define USB_OTG_DIEPMSK_XFRCM_Msk   (0x1UL << USB_OTG_DIEPMSK_XFRCM_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ USB_OTG_DIEPMSK_XFRCM

    - -
    -
    - - - - -
    #define USB_OTG_DIEPMSK_XFRCM   USB_OTG_DIEPMSK_XFRCM_Msk
    -
    -

    Transfer completed interrupt mask
    -

    - -
    -
    - -

    ◆ USB_OTG_DIEPMSK_EPDM_Pos

    - -
    -
    - - - - -
    #define USB_OTG_DIEPMSK_EPDM_Pos   (1U)
    -
    - -
    -
    - -

    ◆ USB_OTG_DIEPMSK_EPDM_Msk

    - -
    -
    - - - - -
    #define USB_OTG_DIEPMSK_EPDM_Msk   (0x1UL << USB_OTG_DIEPMSK_EPDM_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ USB_OTG_DIEPMSK_EPDM

    - -
    -
    - - - - -
    #define USB_OTG_DIEPMSK_EPDM   USB_OTG_DIEPMSK_EPDM_Msk
    -
    -

    Endpoint disabled interrupt mask
    -

    - -
    -
    - -

    ◆ USB_OTG_DIEPMSK_TOM_Pos

    - -
    -
    - - - - -
    #define USB_OTG_DIEPMSK_TOM_Pos   (3U)
    -
    - -
    -
    - -

    ◆ USB_OTG_DIEPMSK_TOM_Msk

    - -
    -
    - - - - -
    #define USB_OTG_DIEPMSK_TOM_Msk   (0x1UL << USB_OTG_DIEPMSK_TOM_Pos)
    -
    -

    0x00000008

    - -
    -
    - -

    ◆ USB_OTG_DIEPMSK_TOM

    - -
    -
    - - - - -
    #define USB_OTG_DIEPMSK_TOM   USB_OTG_DIEPMSK_TOM_Msk
    -
    -

    Timeout condition mask (nonisochronous endpoints)

    - -
    -
    - -

    ◆ USB_OTG_DIEPMSK_ITTXFEMSK_Pos

    - -
    -
    - - - - -
    #define USB_OTG_DIEPMSK_ITTXFEMSK_Pos   (4U)
    -
    - -
    -
    - -

    ◆ USB_OTG_DIEPMSK_ITTXFEMSK_Msk

    - -
    -
    - - - - -
    #define USB_OTG_DIEPMSK_ITTXFEMSK_Msk   (0x1UL << USB_OTG_DIEPMSK_ITTXFEMSK_Pos)
    -
    -

    0x00000010

    - -
    -
    - -

    ◆ USB_OTG_DIEPMSK_ITTXFEMSK

    - -
    -
    - - - - -
    #define USB_OTG_DIEPMSK_ITTXFEMSK   USB_OTG_DIEPMSK_ITTXFEMSK_Msk
    -
    -

    IN token received when TxFIFO empty mask
    -

    - -
    -
    - -

    ◆ USB_OTG_DIEPMSK_INEPNMM_Pos

    - -
    -
    - - - - -
    #define USB_OTG_DIEPMSK_INEPNMM_Pos   (5U)
    -
    - -
    -
    - -

    ◆ USB_OTG_DIEPMSK_INEPNMM_Msk

    - -
    -
    - - - - -
    #define USB_OTG_DIEPMSK_INEPNMM_Msk   (0x1UL << USB_OTG_DIEPMSK_INEPNMM_Pos)
    -
    -

    0x00000020

    - -
    -
    - -

    ◆ USB_OTG_DIEPMSK_INEPNMM

    - -
    -
    - - - - -
    #define USB_OTG_DIEPMSK_INEPNMM   USB_OTG_DIEPMSK_INEPNMM_Msk
    -
    -

    IN token received with EP mismatch mask
    -

    - -
    -
    - -

    ◆ USB_OTG_DIEPMSK_INEPNEM_Pos

    - -
    -
    - - - - -
    #define USB_OTG_DIEPMSK_INEPNEM_Pos   (6U)
    -
    - -
    -
    - -

    ◆ USB_OTG_DIEPMSK_INEPNEM_Msk

    - -
    -
    - - - - -
    #define USB_OTG_DIEPMSK_INEPNEM_Msk   (0x1UL << USB_OTG_DIEPMSK_INEPNEM_Pos)
    -
    -

    0x00000040

    - -
    -
    - -

    ◆ USB_OTG_DIEPMSK_INEPNEM

    - -
    -
    - - - - -
    #define USB_OTG_DIEPMSK_INEPNEM   USB_OTG_DIEPMSK_INEPNEM_Msk
    -
    -

    IN endpoint NAK effective mask
    -

    - -
    -
    - -

    ◆ USB_OTG_DIEPMSK_TXFURM_Pos

    - -
    -
    - - - - -
    #define USB_OTG_DIEPMSK_TXFURM_Pos   (8U)
    -
    - -
    -
    - -

    ◆ USB_OTG_DIEPMSK_TXFURM_Msk

    - -
    -
    - - - - -
    #define USB_OTG_DIEPMSK_TXFURM_Msk   (0x1UL << USB_OTG_DIEPMSK_TXFURM_Pos)
    -
    -

    0x00000100

    - -
    -
    - -

    ◆ USB_OTG_DIEPMSK_TXFURM

    - -
    -
    - - - - -
    #define USB_OTG_DIEPMSK_TXFURM   USB_OTG_DIEPMSK_TXFURM_Msk
    -
    -

    FIFO underrun mask
    -

    - -
    -
    - -

    ◆ USB_OTG_DIEPMSK_BIM_Pos

    - -
    -
    - - - - -
    #define USB_OTG_DIEPMSK_BIM_Pos   (9U)
    -
    - -
    -
    - -

    ◆ USB_OTG_DIEPMSK_BIM_Msk

    - -
    -
    - - - - -
    #define USB_OTG_DIEPMSK_BIM_Msk   (0x1UL << USB_OTG_DIEPMSK_BIM_Pos)
    -
    -

    0x00000200

    - -
    -
    - -

    ◆ USB_OTG_DIEPMSK_BIM

    - -
    -
    - - - - -
    #define USB_OTG_DIEPMSK_BIM   USB_OTG_DIEPMSK_BIM_Msk
    -
    -

    BNA interrupt mask
    -

    - -
    -
    - -

    ◆ USB_OTG_HPTXSTS_PTXFSAVL_Pos

    - -
    -
    - - - - -
    #define USB_OTG_HPTXSTS_PTXFSAVL_Pos   (0U)
    -
    - -
    -
    - -

    ◆ USB_OTG_HPTXSTS_PTXFSAVL_Msk

    - -
    -
    - - - - -
    #define USB_OTG_HPTXSTS_PTXFSAVL_Msk   (0xFFFFUL << USB_OTG_HPTXSTS_PTXFSAVL_Pos)
    -
    -

    0x0000FFFF

    - -
    -
    - -

    ◆ USB_OTG_HPTXSTS_PTXFSAVL

    - -
    -
    - - - - -
    #define USB_OTG_HPTXSTS_PTXFSAVL   USB_OTG_HPTXSTS_PTXFSAVL_Msk
    -
    -

    Periodic transmit data FIFO space available
    -

    - -
    -
    - -

    ◆ USB_OTG_HPTXSTS_PTXQSAV_Pos

    - -
    -
    - - - - -
    #define USB_OTG_HPTXSTS_PTXQSAV_Pos   (16U)
    -
    - -
    -
    - -

    ◆ USB_OTG_HPTXSTS_PTXQSAV_Msk

    - -
    -
    - - - - -
    #define USB_OTG_HPTXSTS_PTXQSAV_Msk   (0xFFUL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
    -
    -

    0x00FF0000

    - -
    -
    - -

    ◆ USB_OTG_HPTXSTS_PTXQSAV

    - -
    -
    - - - - -
    #define USB_OTG_HPTXSTS_PTXQSAV   USB_OTG_HPTXSTS_PTXQSAV_Msk
    -
    -

    Periodic transmit request queue space available

    - -
    -
    - -

    ◆ USB_OTG_HPTXSTS_PTXQSAV_0

    - -
    -
    - - - - -
    #define USB_OTG_HPTXSTS_PTXQSAV_0   (0x01UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
    -
    -

    0x00010000

    - -
    -
    - -

    ◆ USB_OTG_HPTXSTS_PTXQSAV_1

    - -
    -
    - - - - -
    #define USB_OTG_HPTXSTS_PTXQSAV_1   (0x02UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
    -
    -

    0x00020000

    - -
    -
    - -

    ◆ USB_OTG_HPTXSTS_PTXQSAV_2

    - -
    -
    - - - - -
    #define USB_OTG_HPTXSTS_PTXQSAV_2   (0x04UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
    -
    -

    0x00040000

    - -
    -
    - -

    ◆ USB_OTG_HPTXSTS_PTXQSAV_3

    - -
    -
    - - - - -
    #define USB_OTG_HPTXSTS_PTXQSAV_3   (0x08UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
    -
    -

    0x00080000

    - -
    -
    - -

    ◆ USB_OTG_HPTXSTS_PTXQSAV_4

    - -
    -
    - - - - -
    #define USB_OTG_HPTXSTS_PTXQSAV_4   (0x10UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
    -
    -

    0x00100000

    - -
    -
    - -

    ◆ USB_OTG_HPTXSTS_PTXQSAV_5

    - -
    -
    - - - - -
    #define USB_OTG_HPTXSTS_PTXQSAV_5   (0x20UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
    -
    -

    0x00200000

    - -
    -
    - -

    ◆ USB_OTG_HPTXSTS_PTXQSAV_6

    - -
    -
    - - - - -
    #define USB_OTG_HPTXSTS_PTXQSAV_6   (0x40UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
    -
    -

    0x00400000

    - -
    -
    - -

    ◆ USB_OTG_HPTXSTS_PTXQSAV_7

    - -
    -
    - - - - -
    #define USB_OTG_HPTXSTS_PTXQSAV_7   (0x80UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
    -
    -

    0x00800000

    - -
    -
    - -

    ◆ USB_OTG_HPTXSTS_PTXQTOP_Pos

    - -
    -
    - - - - -
    #define USB_OTG_HPTXSTS_PTXQTOP_Pos   (24U)
    -
    - -
    -
    - -

    ◆ USB_OTG_HPTXSTS_PTXQTOP_Msk

    - -
    -
    - - - - -
    #define USB_OTG_HPTXSTS_PTXQTOP_Msk   (0xFFUL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
    -
    -

    0xFF000000

    - -
    -
    - -

    ◆ USB_OTG_HPTXSTS_PTXQTOP

    - -
    -
    - - - - -
    #define USB_OTG_HPTXSTS_PTXQTOP   USB_OTG_HPTXSTS_PTXQTOP_Msk
    -
    -

    Top of the periodic transmit request queue

    - -
    -
    - -

    ◆ USB_OTG_HPTXSTS_PTXQTOP_0

    - -
    -
    - - - - -
    #define USB_OTG_HPTXSTS_PTXQTOP_0   (0x01UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
    -
    -

    0x01000000

    - -
    -
    - -

    ◆ USB_OTG_HPTXSTS_PTXQTOP_1

    - -
    -
    - - - - -
    #define USB_OTG_HPTXSTS_PTXQTOP_1   (0x02UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
    -
    -

    0x02000000

    - -
    -
    - -

    ◆ USB_OTG_HPTXSTS_PTXQTOP_2

    - -
    -
    - - - - -
    #define USB_OTG_HPTXSTS_PTXQTOP_2   (0x04UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
    -
    -

    0x04000000

    - -
    -
    - -

    ◆ USB_OTG_HPTXSTS_PTXQTOP_3

    - -
    -
    - - - - -
    #define USB_OTG_HPTXSTS_PTXQTOP_3   (0x08UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
    -
    -

    0x08000000

    - -
    -
    - -

    ◆ USB_OTG_HPTXSTS_PTXQTOP_4

    - -
    -
    - - - - -
    #define USB_OTG_HPTXSTS_PTXQTOP_4   (0x10UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
    -
    -

    0x10000000

    - -
    -
    - -

    ◆ USB_OTG_HPTXSTS_PTXQTOP_5

    - -
    -
    - - - - -
    #define USB_OTG_HPTXSTS_PTXQTOP_5   (0x20UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
    -
    -

    0x20000000

    - -
    -
    - -

    ◆ USB_OTG_HPTXSTS_PTXQTOP_6

    - -
    -
    - - - - -
    #define USB_OTG_HPTXSTS_PTXQTOP_6   (0x40UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
    -
    -

    0x40000000

    - -
    -
    - -

    ◆ USB_OTG_HPTXSTS_PTXQTOP_7

    - -
    -
    - - - - -
    #define USB_OTG_HPTXSTS_PTXQTOP_7   (0x80UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
    -
    -

    0x80000000

    - -
    -
    - -

    ◆ USB_OTG_HAINT_HAINT_Pos

    - -
    -
    - - - - -
    #define USB_OTG_HAINT_HAINT_Pos   (0U)
    -
    - -
    -
    - -

    ◆ USB_OTG_HAINT_HAINT_Msk

    - -
    -
    - - - - -
    #define USB_OTG_HAINT_HAINT_Msk   (0xFFFFUL << USB_OTG_HAINT_HAINT_Pos)
    -
    -

    0x0000FFFF

    - -
    -
    - -

    ◆ USB_OTG_HAINT_HAINT

    - -
    -
    - - - - -
    #define USB_OTG_HAINT_HAINT   USB_OTG_HAINT_HAINT_Msk
    -
    -

    Channel interrupts

    - -
    -
    - -

    ◆ USB_OTG_DOEPMSK_XFRCM_Pos

    - -
    -
    - - - - -
    #define USB_OTG_DOEPMSK_XFRCM_Pos   (0U)
    -
    - -
    -
    - -

    ◆ USB_OTG_DOEPMSK_XFRCM_Msk

    - -
    -
    - - - - -
    #define USB_OTG_DOEPMSK_XFRCM_Msk   (0x1UL << USB_OTG_DOEPMSK_XFRCM_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ USB_OTG_DOEPMSK_XFRCM

    - -
    -
    - - - - -
    #define USB_OTG_DOEPMSK_XFRCM   USB_OTG_DOEPMSK_XFRCM_Msk
    -
    -

    Transfer completed interrupt mask
    -

    - -
    -
    - -

    ◆ USB_OTG_DOEPMSK_EPDM_Pos

    - -
    -
    - - - - -
    #define USB_OTG_DOEPMSK_EPDM_Pos   (1U)
    -
    - -
    -
    - -

    ◆ USB_OTG_DOEPMSK_EPDM_Msk

    - -
    -
    - - - - -
    #define USB_OTG_DOEPMSK_EPDM_Msk   (0x1UL << USB_OTG_DOEPMSK_EPDM_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ USB_OTG_DOEPMSK_EPDM

    - -
    -
    - - - - -
    #define USB_OTG_DOEPMSK_EPDM   USB_OTG_DOEPMSK_EPDM_Msk
    -
    -

    Endpoint disabled interrupt mask
    -

    - -
    -
    - -

    ◆ USB_OTG_DOEPMSK_AHBERRM_Pos

    - -
    -
    - - - - -
    #define USB_OTG_DOEPMSK_AHBERRM_Pos   (2U)
    -
    - -
    -
    - -

    ◆ USB_OTG_DOEPMSK_AHBERRM_Msk

    - -
    -
    - - - - -
    #define USB_OTG_DOEPMSK_AHBERRM_Msk   (0x1UL << USB_OTG_DOEPMSK_AHBERRM_Pos)
    -
    -

    0x00000004

    - -
    -
    - -

    ◆ USB_OTG_DOEPMSK_AHBERRM

    - -
    -
    - - - - -
    #define USB_OTG_DOEPMSK_AHBERRM   USB_OTG_DOEPMSK_AHBERRM_Msk
    -
    -

    OUT transaction AHB Error interrupt mask
    -

    - -
    -
    - -

    ◆ USB_OTG_DOEPMSK_STUPM_Pos

    - -
    -
    - - - - -
    #define USB_OTG_DOEPMSK_STUPM_Pos   (3U)
    -
    - -
    -
    - -

    ◆ USB_OTG_DOEPMSK_STUPM_Msk

    - -
    -
    - - - - -
    #define USB_OTG_DOEPMSK_STUPM_Msk   (0x1UL << USB_OTG_DOEPMSK_STUPM_Pos)
    -
    -

    0x00000008

    - -
    -
    - -

    ◆ USB_OTG_DOEPMSK_STUPM

    - -
    -
    - - - - -
    #define USB_OTG_DOEPMSK_STUPM   USB_OTG_DOEPMSK_STUPM_Msk
    -
    -

    SETUP phase done mask
    -

    - -
    -
    - -

    ◆ USB_OTG_DOEPMSK_OTEPDM_Pos

    - -
    -
    - - - - -
    #define USB_OTG_DOEPMSK_OTEPDM_Pos   (4U)
    -
    - -
    -
    - -

    ◆ USB_OTG_DOEPMSK_OTEPDM_Msk

    - -
    -
    - - - - -
    #define USB_OTG_DOEPMSK_OTEPDM_Msk   (0x1UL << USB_OTG_DOEPMSK_OTEPDM_Pos)
    -
    -

    0x00000010

    - -
    -
    - -

    ◆ USB_OTG_DOEPMSK_OTEPDM

    - -
    -
    - - - - -
    #define USB_OTG_DOEPMSK_OTEPDM   USB_OTG_DOEPMSK_OTEPDM_Msk
    -
    -

    OUT token received when endpoint disabled mask

    - -
    -
    - -

    ◆ USB_OTG_DOEPMSK_OTEPSPRM_Pos

    - -
    -
    - - - - -
    #define USB_OTG_DOEPMSK_OTEPSPRM_Pos   (5U)
    -
    - -
    -
    - -

    ◆ USB_OTG_DOEPMSK_OTEPSPRM_Msk

    - -
    -
    - - - - -
    #define USB_OTG_DOEPMSK_OTEPSPRM_Msk   (0x1UL << USB_OTG_DOEPMSK_OTEPSPRM_Pos)
    -
    -

    0x00000020

    - -
    -
    - -

    ◆ USB_OTG_DOEPMSK_OTEPSPRM

    - -
    -
    - - - - -
    #define USB_OTG_DOEPMSK_OTEPSPRM   USB_OTG_DOEPMSK_OTEPSPRM_Msk
    -
    -

    Status Phase Received mask
    -

    - -
    -
    - -

    ◆ USB_OTG_DOEPMSK_B2BSTUP_Pos

    - -
    -
    - - - - -
    #define USB_OTG_DOEPMSK_B2BSTUP_Pos   (6U)
    -
    - -
    -
    - -

    ◆ USB_OTG_DOEPMSK_B2BSTUP_Msk

    - -
    -
    - - - - -
    #define USB_OTG_DOEPMSK_B2BSTUP_Msk   (0x1UL << USB_OTG_DOEPMSK_B2BSTUP_Pos)
    -
    -

    0x00000040

    - -
    -
    - -

    ◆ USB_OTG_DOEPMSK_B2BSTUP

    - -
    -
    - - - - -
    #define USB_OTG_DOEPMSK_B2BSTUP   USB_OTG_DOEPMSK_B2BSTUP_Msk
    -
    -

    Back-to-back SETUP packets received mask
    -

    - -
    -
    - -

    ◆ USB_OTG_DOEPMSK_OPEM_Pos

    - -
    -
    - - - - -
    #define USB_OTG_DOEPMSK_OPEM_Pos   (8U)
    -
    - -
    -
    - -

    ◆ USB_OTG_DOEPMSK_OPEM_Msk

    - -
    -
    - - - - -
    #define USB_OTG_DOEPMSK_OPEM_Msk   (0x1UL << USB_OTG_DOEPMSK_OPEM_Pos)
    -
    -

    0x00000100

    - -
    -
    - -

    ◆ USB_OTG_DOEPMSK_OPEM

    - -
    -
    - - - - -
    #define USB_OTG_DOEPMSK_OPEM   USB_OTG_DOEPMSK_OPEM_Msk
    -
    -

    OUT packet error mask
    -

    - -
    -
    - -

    ◆ USB_OTG_DOEPMSK_BOIM_Pos

    - -
    -
    - - - - -
    #define USB_OTG_DOEPMSK_BOIM_Pos   (9U)
    -
    - -
    -
    - -

    ◆ USB_OTG_DOEPMSK_BOIM_Msk

    - -
    -
    - - - - -
    #define USB_OTG_DOEPMSK_BOIM_Msk   (0x1UL << USB_OTG_DOEPMSK_BOIM_Pos)
    -
    -

    0x00000200

    - -
    -
    - -

    ◆ USB_OTG_DOEPMSK_BOIM

    - -
    -
    - - - - -
    #define USB_OTG_DOEPMSK_BOIM   USB_OTG_DOEPMSK_BOIM_Msk
    -
    -

    BNA interrupt mask
    -

    - -
    -
    - -

    ◆ USB_OTG_DOEPMSK_BERRM_Pos

    - -
    -
    - - - - -
    #define USB_OTG_DOEPMSK_BERRM_Pos   (12U)
    -
    - -
    -
    - -

    ◆ USB_OTG_DOEPMSK_BERRM_Msk

    - -
    -
    - - - - -
    #define USB_OTG_DOEPMSK_BERRM_Msk   (0x1UL << USB_OTG_DOEPMSK_BERRM_Pos)
    -
    -

    0x00001000

    - -
    -
    - -

    ◆ USB_OTG_DOEPMSK_BERRM

    - -
    -
    - - - - -
    #define USB_OTG_DOEPMSK_BERRM   USB_OTG_DOEPMSK_BERRM_Msk
    -
    -

    Babble error interrupt mask
    -

    - -
    -
    - -

    ◆ USB_OTG_DOEPMSK_NAKM_Pos

    - -
    -
    - - - - -
    #define USB_OTG_DOEPMSK_NAKM_Pos   (13U)
    -
    - -
    -
    - -

    ◆ USB_OTG_DOEPMSK_NAKM_Msk

    - -
    -
    - - - - -
    #define USB_OTG_DOEPMSK_NAKM_Msk   (0x1UL << USB_OTG_DOEPMSK_NAKM_Pos)
    -
    -

    0x00002000

    - -
    -
    - -

    ◆ USB_OTG_DOEPMSK_NAKM

    - -
    -
    - - - - -
    #define USB_OTG_DOEPMSK_NAKM   USB_OTG_DOEPMSK_NAKM_Msk
    -
    -

    OUT Packet NAK interrupt mask
    -

    - -
    -
    - -

    ◆ USB_OTG_DOEPMSK_NYETM_Pos

    - -
    -
    - - - - -
    #define USB_OTG_DOEPMSK_NYETM_Pos   (14U)
    -
    - -
    -
    - -

    ◆ USB_OTG_DOEPMSK_NYETM_Msk

    - -
    -
    - - - - -
    #define USB_OTG_DOEPMSK_NYETM_Msk   (0x1UL << USB_OTG_DOEPMSK_NYETM_Pos)
    -
    -

    0x00004000

    - -
    -
    - -

    ◆ USB_OTG_DOEPMSK_NYETM

    - -
    -
    - - - - -
    #define USB_OTG_DOEPMSK_NYETM   USB_OTG_DOEPMSK_NYETM_Msk
    -
    -

    NYET interrupt mask
    -

    - -
    -
    - -

    ◆ USB_OTG_GINTSTS_CMOD_Pos

    - -
    -
    - - - - -
    #define USB_OTG_GINTSTS_CMOD_Pos   (0U)
    -
    - -
    -
    - -

    ◆ USB_OTG_GINTSTS_CMOD_Msk

    - -
    -
    - - - - -
    #define USB_OTG_GINTSTS_CMOD_Msk   (0x1UL << USB_OTG_GINTSTS_CMOD_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ USB_OTG_GINTSTS_CMOD

    - -
    -
    - - - - -
    #define USB_OTG_GINTSTS_CMOD   USB_OTG_GINTSTS_CMOD_Msk
    -
    -

    Current mode of operation
    -

    - -
    -
    - -

    ◆ USB_OTG_GINTSTS_MMIS_Pos

    - -
    -
    - - - - -
    #define USB_OTG_GINTSTS_MMIS_Pos   (1U)
    -
    - -
    -
    - -

    ◆ USB_OTG_GINTSTS_MMIS_Msk

    - -
    -
    - - - - -
    #define USB_OTG_GINTSTS_MMIS_Msk   (0x1UL << USB_OTG_GINTSTS_MMIS_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ USB_OTG_GINTSTS_MMIS

    - -
    -
    - - - - -
    #define USB_OTG_GINTSTS_MMIS   USB_OTG_GINTSTS_MMIS_Msk
    -
    -

    Mode mismatch interrupt
    -

    - -
    -
    - -

    ◆ USB_OTG_GINTSTS_OTGINT_Pos

    - -
    -
    - - - - -
    #define USB_OTG_GINTSTS_OTGINT_Pos   (2U)
    -
    - -
    -
    - -

    ◆ USB_OTG_GINTSTS_OTGINT_Msk

    - -
    -
    - - - - -
    #define USB_OTG_GINTSTS_OTGINT_Msk   (0x1UL << USB_OTG_GINTSTS_OTGINT_Pos)
    -
    -

    0x00000004

    - -
    -
    - -

    ◆ USB_OTG_GINTSTS_OTGINT

    - -
    -
    - - - - -
    #define USB_OTG_GINTSTS_OTGINT   USB_OTG_GINTSTS_OTGINT_Msk
    -
    -

    OTG interrupt
    -

    - -
    -
    - -

    ◆ USB_OTG_GINTSTS_SOF_Pos

    - -
    -
    - - - - -
    #define USB_OTG_GINTSTS_SOF_Pos   (3U)
    -
    - -
    -
    - -

    ◆ USB_OTG_GINTSTS_SOF_Msk

    - -
    -
    - - - - -
    #define USB_OTG_GINTSTS_SOF_Msk   (0x1UL << USB_OTG_GINTSTS_SOF_Pos)
    -
    -

    0x00000008

    - -
    -
    - -

    ◆ USB_OTG_GINTSTS_SOF

    - -
    -
    - - - - -
    #define USB_OTG_GINTSTS_SOF   USB_OTG_GINTSTS_SOF_Msk
    -
    -

    Start of frame
    -

    - -
    -
    - -

    ◆ USB_OTG_GINTSTS_RXFLVL_Pos

    - -
    -
    - - - - -
    #define USB_OTG_GINTSTS_RXFLVL_Pos   (4U)
    -
    - -
    -
    - -

    ◆ USB_OTG_GINTSTS_RXFLVL_Msk

    - -
    -
    - - - - -
    #define USB_OTG_GINTSTS_RXFLVL_Msk   (0x1UL << USB_OTG_GINTSTS_RXFLVL_Pos)
    -
    -

    0x00000010

    - -
    -
    - -

    ◆ USB_OTG_GINTSTS_RXFLVL

    - -
    -
    - - - - -
    #define USB_OTG_GINTSTS_RXFLVL   USB_OTG_GINTSTS_RXFLVL_Msk
    -
    -

    RxFIFO nonempty
    -

    - -
    -
    - -

    ◆ USB_OTG_GINTSTS_NPTXFE_Pos

    - -
    -
    - - - - -
    #define USB_OTG_GINTSTS_NPTXFE_Pos   (5U)
    -
    - -
    -
    - -

    ◆ USB_OTG_GINTSTS_NPTXFE_Msk

    - -
    -
    - - - - -
    #define USB_OTG_GINTSTS_NPTXFE_Msk   (0x1UL << USB_OTG_GINTSTS_NPTXFE_Pos)
    -
    -

    0x00000020

    - -
    -
    - -

    ◆ USB_OTG_GINTSTS_NPTXFE

    - -
    -
    - - - - -
    #define USB_OTG_GINTSTS_NPTXFE   USB_OTG_GINTSTS_NPTXFE_Msk
    -
    -

    Nonperiodic TxFIFO empty
    -

    - -
    -
    - -

    ◆ USB_OTG_GINTSTS_GINAKEFF_Pos

    - -
    -
    - - - - -
    #define USB_OTG_GINTSTS_GINAKEFF_Pos   (6U)
    -
    - -
    -
    - -

    ◆ USB_OTG_GINTSTS_GINAKEFF_Msk

    - -
    -
    - - - - -
    #define USB_OTG_GINTSTS_GINAKEFF_Msk   (0x1UL << USB_OTG_GINTSTS_GINAKEFF_Pos)
    -
    -

    0x00000040

    - -
    -
    - -

    ◆ USB_OTG_GINTSTS_GINAKEFF

    - -
    -
    - - - - -
    #define USB_OTG_GINTSTS_GINAKEFF   USB_OTG_GINTSTS_GINAKEFF_Msk
    -
    -

    Global IN nonperiodic NAK effective
    -

    - -
    -
    - -

    ◆ USB_OTG_GINTSTS_BOUTNAKEFF_Pos

    - -
    -
    - - - - -
    #define USB_OTG_GINTSTS_BOUTNAKEFF_Pos   (7U)
    -
    - -
    -
    - -

    ◆ USB_OTG_GINTSTS_BOUTNAKEFF_Msk

    - -
    -
    - - - - -
    #define USB_OTG_GINTSTS_BOUTNAKEFF_Msk   (0x1UL << USB_OTG_GINTSTS_BOUTNAKEFF_Pos)
    -
    -

    0x00000080

    - -
    -
    - -

    ◆ USB_OTG_GINTSTS_BOUTNAKEFF

    - -
    -
    - - - - -
    #define USB_OTG_GINTSTS_BOUTNAKEFF   USB_OTG_GINTSTS_BOUTNAKEFF_Msk
    -
    -

    Global OUT NAK effective
    -

    - -
    -
    - -

    ◆ USB_OTG_GINTSTS_ESUSP_Pos

    - -
    -
    - - - - -
    #define USB_OTG_GINTSTS_ESUSP_Pos   (10U)
    -
    - -
    -
    - -

    ◆ USB_OTG_GINTSTS_ESUSP_Msk

    - -
    -
    - - - - -
    #define USB_OTG_GINTSTS_ESUSP_Msk   (0x1UL << USB_OTG_GINTSTS_ESUSP_Pos)
    -
    -

    0x00000400

    - -
    -
    - -

    ◆ USB_OTG_GINTSTS_ESUSP

    - -
    -
    - - - - -
    #define USB_OTG_GINTSTS_ESUSP   USB_OTG_GINTSTS_ESUSP_Msk
    -
    -

    Early suspend
    -

    - -
    -
    - -

    ◆ USB_OTG_GINTSTS_USBSUSP_Pos

    - -
    -
    - - - - -
    #define USB_OTG_GINTSTS_USBSUSP_Pos   (11U)
    -
    - -
    -
    - -

    ◆ USB_OTG_GINTSTS_USBSUSP_Msk

    - -
    -
    - - - - -
    #define USB_OTG_GINTSTS_USBSUSP_Msk   (0x1UL << USB_OTG_GINTSTS_USBSUSP_Pos)
    -
    -

    0x00000800

    - -
    -
    - -

    ◆ USB_OTG_GINTSTS_USBSUSP

    - -
    -
    - - - - -
    #define USB_OTG_GINTSTS_USBSUSP   USB_OTG_GINTSTS_USBSUSP_Msk
    -
    -

    USB suspend
    -

    - -
    -
    - -

    ◆ USB_OTG_GINTSTS_USBRST_Pos

    - -
    -
    - - - - -
    #define USB_OTG_GINTSTS_USBRST_Pos   (12U)
    -
    - -
    -
    - -

    ◆ USB_OTG_GINTSTS_USBRST_Msk

    - -
    -
    - - - - -
    #define USB_OTG_GINTSTS_USBRST_Msk   (0x1UL << USB_OTG_GINTSTS_USBRST_Pos)
    -
    -

    0x00001000

    - -
    -
    - -

    ◆ USB_OTG_GINTSTS_USBRST

    - -
    -
    - - - - -
    #define USB_OTG_GINTSTS_USBRST   USB_OTG_GINTSTS_USBRST_Msk
    -
    -

    USB reset
    -

    - -
    -
    - -

    ◆ USB_OTG_GINTSTS_ENUMDNE_Pos

    - -
    -
    - - - - -
    #define USB_OTG_GINTSTS_ENUMDNE_Pos   (13U)
    -
    - -
    -
    - -

    ◆ USB_OTG_GINTSTS_ENUMDNE_Msk

    - -
    -
    - - - - -
    #define USB_OTG_GINTSTS_ENUMDNE_Msk   (0x1UL << USB_OTG_GINTSTS_ENUMDNE_Pos)
    -
    -

    0x00002000

    - -
    -
    - -

    ◆ USB_OTG_GINTSTS_ENUMDNE

    - -
    -
    - - - - -
    #define USB_OTG_GINTSTS_ENUMDNE   USB_OTG_GINTSTS_ENUMDNE_Msk
    -
    -

    Enumeration done
    -

    - -
    -
    - -

    ◆ USB_OTG_GINTSTS_ISOODRP_Pos

    - -
    -
    - - - - -
    #define USB_OTG_GINTSTS_ISOODRP_Pos   (14U)
    -
    - -
    -
    - -

    ◆ USB_OTG_GINTSTS_ISOODRP_Msk

    - -
    -
    - - - - -
    #define USB_OTG_GINTSTS_ISOODRP_Msk   (0x1UL << USB_OTG_GINTSTS_ISOODRP_Pos)
    -
    -

    0x00004000

    - -
    -
    - -

    ◆ USB_OTG_GINTSTS_ISOODRP

    - -
    -
    - - - - -
    #define USB_OTG_GINTSTS_ISOODRP   USB_OTG_GINTSTS_ISOODRP_Msk
    -
    -

    Isochronous OUT packet dropped interrupt
    -

    - -
    -
    - -

    ◆ USB_OTG_GINTSTS_EOPF_Pos

    - -
    -
    - - - - -
    #define USB_OTG_GINTSTS_EOPF_Pos   (15U)
    -
    - -
    -
    - -

    ◆ USB_OTG_GINTSTS_EOPF_Msk

    - -
    -
    - - - - -
    #define USB_OTG_GINTSTS_EOPF_Msk   (0x1UL << USB_OTG_GINTSTS_EOPF_Pos)
    -
    -

    0x00008000

    - -
    -
    - -

    ◆ USB_OTG_GINTSTS_EOPF

    - -
    -
    - - - - -
    #define USB_OTG_GINTSTS_EOPF   USB_OTG_GINTSTS_EOPF_Msk
    -
    -

    End of periodic frame interrupt
    -

    - -
    -
    - -

    ◆ USB_OTG_GINTSTS_IEPINT_Pos

    - -
    -
    - - - - -
    #define USB_OTG_GINTSTS_IEPINT_Pos   (18U)
    -
    - -
    -
    - -

    ◆ USB_OTG_GINTSTS_IEPINT_Msk

    - -
    -
    - - - - -
    #define USB_OTG_GINTSTS_IEPINT_Msk   (0x1UL << USB_OTG_GINTSTS_IEPINT_Pos)
    -
    -

    0x00040000

    - -
    -
    - -

    ◆ USB_OTG_GINTSTS_IEPINT

    - -
    -
    - - - - -
    #define USB_OTG_GINTSTS_IEPINT   USB_OTG_GINTSTS_IEPINT_Msk
    -
    -

    IN endpoint interrupt
    -

    - -
    -
    - -

    ◆ USB_OTG_GINTSTS_OEPINT_Pos

    - -
    -
    - - - - -
    #define USB_OTG_GINTSTS_OEPINT_Pos   (19U)
    -
    - -
    -
    - -

    ◆ USB_OTG_GINTSTS_OEPINT_Msk

    - -
    -
    - - - - -
    #define USB_OTG_GINTSTS_OEPINT_Msk   (0x1UL << USB_OTG_GINTSTS_OEPINT_Pos)
    -
    -

    0x00080000

    - -
    -
    - -

    ◆ USB_OTG_GINTSTS_OEPINT

    - -
    -
    - - - - -
    #define USB_OTG_GINTSTS_OEPINT   USB_OTG_GINTSTS_OEPINT_Msk
    -
    -

    OUT endpoint interrupt
    -

    - -
    -
    - -

    ◆ USB_OTG_GINTSTS_IISOIXFR_Pos

    - -
    -
    - - - - -
    #define USB_OTG_GINTSTS_IISOIXFR_Pos   (20U)
    -
    - -
    -
    - -

    ◆ USB_OTG_GINTSTS_IISOIXFR_Msk

    - -
    -
    - - - - -
    #define USB_OTG_GINTSTS_IISOIXFR_Msk   (0x1UL << USB_OTG_GINTSTS_IISOIXFR_Pos)
    -
    -

    0x00100000

    - -
    -
    - -

    ◆ USB_OTG_GINTSTS_IISOIXFR

    - -
    -
    - - - - -
    #define USB_OTG_GINTSTS_IISOIXFR   USB_OTG_GINTSTS_IISOIXFR_Msk
    -
    -

    Incomplete isochronous IN transfer
    -

    - -
    -
    - -

    ◆ USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos

    - -
    -
    - - - - -
    #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos   (21U)
    -
    - -
    -
    - -

    ◆ USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk

    - -
    -
    - - - - -
    #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk   (0x1UL << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos)
    -
    -

    0x00200000

    - -
    -
    - -

    ◆ USB_OTG_GINTSTS_PXFR_INCOMPISOOUT

    - -
    -
    - - - - -
    #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT   USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk
    -
    -

    Incomplete periodic transfer
    -

    - -
    -
    - -

    ◆ USB_OTG_GINTSTS_DATAFSUSP_Pos

    - -
    -
    - - - - -
    #define USB_OTG_GINTSTS_DATAFSUSP_Pos   (22U)
    -
    - -
    -
    - -

    ◆ USB_OTG_GINTSTS_DATAFSUSP_Msk

    - -
    -
    - - - - -
    #define USB_OTG_GINTSTS_DATAFSUSP_Msk   (0x1UL << USB_OTG_GINTSTS_DATAFSUSP_Pos)
    -
    -

    0x00400000

    - -
    -
    - -

    ◆ USB_OTG_GINTSTS_DATAFSUSP

    - -
    -
    - - - - -
    #define USB_OTG_GINTSTS_DATAFSUSP   USB_OTG_GINTSTS_DATAFSUSP_Msk
    -
    -

    Data fetch suspended
    -

    - -
    -
    - -

    ◆ USB_OTG_GINTSTS_HPRTINT_Pos

    - -
    -
    - - - - -
    #define USB_OTG_GINTSTS_HPRTINT_Pos   (24U)
    -
    - -
    -
    - -

    ◆ USB_OTG_GINTSTS_HPRTINT_Msk

    - -
    -
    - - - - -
    #define USB_OTG_GINTSTS_HPRTINT_Msk   (0x1UL << USB_OTG_GINTSTS_HPRTINT_Pos)
    -
    -

    0x01000000

    - -
    -
    - -

    ◆ USB_OTG_GINTSTS_HPRTINT

    - -
    -
    - - - - -
    #define USB_OTG_GINTSTS_HPRTINT   USB_OTG_GINTSTS_HPRTINT_Msk
    -
    -

    Host port interrupt
    -

    - -
    -
    - -

    ◆ USB_OTG_GINTSTS_HCINT_Pos

    - -
    -
    - - - - -
    #define USB_OTG_GINTSTS_HCINT_Pos   (25U)
    -
    - -
    -
    - -

    ◆ USB_OTG_GINTSTS_HCINT_Msk

    - -
    -
    - - - - -
    #define USB_OTG_GINTSTS_HCINT_Msk   (0x1UL << USB_OTG_GINTSTS_HCINT_Pos)
    -
    -

    0x02000000

    - -
    -
    - -

    ◆ USB_OTG_GINTSTS_HCINT

    - -
    -
    - - - - -
    #define USB_OTG_GINTSTS_HCINT   USB_OTG_GINTSTS_HCINT_Msk
    -
    -

    Host channels interrupt
    -

    - -
    -
    - -

    ◆ USB_OTG_GINTSTS_PTXFE_Pos

    - -
    -
    - - - - -
    #define USB_OTG_GINTSTS_PTXFE_Pos   (26U)
    -
    - -
    -
    - -

    ◆ USB_OTG_GINTSTS_PTXFE_Msk

    - -
    -
    - - - - -
    #define USB_OTG_GINTSTS_PTXFE_Msk   (0x1UL << USB_OTG_GINTSTS_PTXFE_Pos)
    -
    -

    0x04000000

    - -
    -
    - -

    ◆ USB_OTG_GINTSTS_PTXFE

    - -
    -
    - - - - -
    #define USB_OTG_GINTSTS_PTXFE   USB_OTG_GINTSTS_PTXFE_Msk
    -
    -

    Periodic TxFIFO empty
    -

    - -
    -
    - -

    ◆ USB_OTG_GINTSTS_CIDSCHG_Pos

    - -
    -
    - - - - -
    #define USB_OTG_GINTSTS_CIDSCHG_Pos   (28U)
    -
    - -
    -
    - -

    ◆ USB_OTG_GINTSTS_CIDSCHG_Msk

    - -
    -
    - - - - -
    #define USB_OTG_GINTSTS_CIDSCHG_Msk   (0x1UL << USB_OTG_GINTSTS_CIDSCHG_Pos)
    -
    -

    0x10000000

    - -
    -
    - -

    ◆ USB_OTG_GINTSTS_CIDSCHG

    - -
    -
    - - - - -
    #define USB_OTG_GINTSTS_CIDSCHG   USB_OTG_GINTSTS_CIDSCHG_Msk
    -
    -

    Connector ID status change
    -

    - -
    -
    - -

    ◆ USB_OTG_GINTSTS_DISCINT_Pos

    - -
    -
    - - - - -
    #define USB_OTG_GINTSTS_DISCINT_Pos   (29U)
    -
    - -
    -
    - -

    ◆ USB_OTG_GINTSTS_DISCINT_Msk

    - -
    -
    - - - - -
    #define USB_OTG_GINTSTS_DISCINT_Msk   (0x1UL << USB_OTG_GINTSTS_DISCINT_Pos)
    -
    -

    0x20000000

    - -
    -
    - -

    ◆ USB_OTG_GINTSTS_DISCINT

    - -
    -
    - - - - -
    #define USB_OTG_GINTSTS_DISCINT   USB_OTG_GINTSTS_DISCINT_Msk
    -
    -

    Disconnect detected interrupt
    -

    - -
    -
    - -

    ◆ USB_OTG_GINTSTS_SRQINT_Pos

    - -
    -
    - - - - -
    #define USB_OTG_GINTSTS_SRQINT_Pos   (30U)
    -
    - -
    -
    - -

    ◆ USB_OTG_GINTSTS_SRQINT_Msk

    - -
    -
    - - - - -
    #define USB_OTG_GINTSTS_SRQINT_Msk   (0x1UL << USB_OTG_GINTSTS_SRQINT_Pos)
    -
    -

    0x40000000

    - -
    -
    - -

    ◆ USB_OTG_GINTSTS_SRQINT

    - -
    -
    - - - - -
    #define USB_OTG_GINTSTS_SRQINT   USB_OTG_GINTSTS_SRQINT_Msk
    -
    -

    Session request/new session detected interrupt

    - -
    -
    - -

    ◆ USB_OTG_GINTSTS_WKUINT_Pos

    - -
    -
    - - - - -
    #define USB_OTG_GINTSTS_WKUINT_Pos   (31U)
    -
    - -
    -
    - -

    ◆ USB_OTG_GINTSTS_WKUINT_Msk

    - -
    -
    - - - - -
    #define USB_OTG_GINTSTS_WKUINT_Msk   (0x1UL << USB_OTG_GINTSTS_WKUINT_Pos)
    -
    -

    0x80000000

    - -
    -
    - -

    ◆ USB_OTG_GINTSTS_WKUINT

    - -
    -
    - - - - -
    #define USB_OTG_GINTSTS_WKUINT   USB_OTG_GINTSTS_WKUINT_Msk
    -
    -

    Resume/remote wakeup detected interrupt
    -

    - -
    -
    - -

    ◆ USB_OTG_GINTMSK_MMISM_Pos

    - -
    -
    - - - - -
    #define USB_OTG_GINTMSK_MMISM_Pos   (1U)
    -
    - -
    -
    - -

    ◆ USB_OTG_GINTMSK_MMISM_Msk

    - -
    -
    - - - - -
    #define USB_OTG_GINTMSK_MMISM_Msk   (0x1UL << USB_OTG_GINTMSK_MMISM_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ USB_OTG_GINTMSK_MMISM

    - -
    -
    - - - - -
    #define USB_OTG_GINTMSK_MMISM   USB_OTG_GINTMSK_MMISM_Msk
    -
    -

    Mode mismatch interrupt mask
    -

    - -
    -
    - -

    ◆ USB_OTG_GINTMSK_OTGINT_Pos

    - -
    -
    - - - - -
    #define USB_OTG_GINTMSK_OTGINT_Pos   (2U)
    -
    - -
    -
    - -

    ◆ USB_OTG_GINTMSK_OTGINT_Msk

    - -
    -
    - - - - -
    #define USB_OTG_GINTMSK_OTGINT_Msk   (0x1UL << USB_OTG_GINTMSK_OTGINT_Pos)
    -
    -

    0x00000004

    - -
    -
    - -

    ◆ USB_OTG_GINTMSK_OTGINT

    - -
    -
    - - - - -
    #define USB_OTG_GINTMSK_OTGINT   USB_OTG_GINTMSK_OTGINT_Msk
    -
    -

    OTG interrupt mask
    -

    - -
    -
    - -

    ◆ USB_OTG_GINTMSK_SOFM_Pos

    - -
    -
    - - - - -
    #define USB_OTG_GINTMSK_SOFM_Pos   (3U)
    -
    - -
    -
    - -

    ◆ USB_OTG_GINTMSK_SOFM_Msk

    - -
    -
    - - - - -
    #define USB_OTG_GINTMSK_SOFM_Msk   (0x1UL << USB_OTG_GINTMSK_SOFM_Pos)
    -
    -

    0x00000008

    - -
    -
    - -

    ◆ USB_OTG_GINTMSK_SOFM

    - -
    -
    - - - - -
    #define USB_OTG_GINTMSK_SOFM   USB_OTG_GINTMSK_SOFM_Msk
    -
    -

    Start of frame mask
    -

    - -
    -
    - -

    ◆ USB_OTG_GINTMSK_RXFLVLM_Pos

    - -
    -
    - - - - -
    #define USB_OTG_GINTMSK_RXFLVLM_Pos   (4U)
    -
    - -
    -
    - -

    ◆ USB_OTG_GINTMSK_RXFLVLM_Msk

    - -
    -
    - - - - -
    #define USB_OTG_GINTMSK_RXFLVLM_Msk   (0x1UL << USB_OTG_GINTMSK_RXFLVLM_Pos)
    -
    -

    0x00000010

    - -
    -
    - -

    ◆ USB_OTG_GINTMSK_RXFLVLM

    - -
    -
    - - - - -
    #define USB_OTG_GINTMSK_RXFLVLM   USB_OTG_GINTMSK_RXFLVLM_Msk
    -
    -

    Receive FIFO nonempty mask
    -

    - -
    -
    - -

    ◆ USB_OTG_GINTMSK_NPTXFEM_Pos

    - -
    -
    - - - - -
    #define USB_OTG_GINTMSK_NPTXFEM_Pos   (5U)
    -
    - -
    -
    - -

    ◆ USB_OTG_GINTMSK_NPTXFEM_Msk

    - -
    -
    - - - - -
    #define USB_OTG_GINTMSK_NPTXFEM_Msk   (0x1UL << USB_OTG_GINTMSK_NPTXFEM_Pos)
    -
    -

    0x00000020

    - -
    -
    - -

    ◆ USB_OTG_GINTMSK_NPTXFEM

    - -
    -
    - - - - -
    #define USB_OTG_GINTMSK_NPTXFEM   USB_OTG_GINTMSK_NPTXFEM_Msk
    -
    -

    Nonperiodic TxFIFO empty mask
    -

    - -
    -
    - -

    ◆ USB_OTG_GINTMSK_GINAKEFFM_Pos

    - -
    -
    - - - - -
    #define USB_OTG_GINTMSK_GINAKEFFM_Pos   (6U)
    -
    - -
    -
    - -

    ◆ USB_OTG_GINTMSK_GINAKEFFM_Msk

    - -
    -
    - - - - -
    #define USB_OTG_GINTMSK_GINAKEFFM_Msk   (0x1UL << USB_OTG_GINTMSK_GINAKEFFM_Pos)
    -
    -

    0x00000040

    - -
    -
    - -

    ◆ USB_OTG_GINTMSK_GINAKEFFM

    - -
    -
    - - - - -
    #define USB_OTG_GINTMSK_GINAKEFFM   USB_OTG_GINTMSK_GINAKEFFM_Msk
    -
    -

    Global nonperiodic IN NAK effective mask
    -

    - -
    -
    - -

    ◆ USB_OTG_GINTMSK_GONAKEFFM_Pos

    - -
    -
    - - - - -
    #define USB_OTG_GINTMSK_GONAKEFFM_Pos   (7U)
    -
    - -
    -
    - -

    ◆ USB_OTG_GINTMSK_GONAKEFFM_Msk

    - -
    -
    - - - - -
    #define USB_OTG_GINTMSK_GONAKEFFM_Msk   (0x1UL << USB_OTG_GINTMSK_GONAKEFFM_Pos)
    -
    -

    0x00000080

    - -
    -
    - -

    ◆ USB_OTG_GINTMSK_GONAKEFFM

    - -
    -
    - - - - -
    #define USB_OTG_GINTMSK_GONAKEFFM   USB_OTG_GINTMSK_GONAKEFFM_Msk
    -
    -

    Global OUT NAK effective mask
    -

    - -
    -
    - -

    ◆ USB_OTG_GINTMSK_ESUSPM_Pos

    - -
    -
    - - - - -
    #define USB_OTG_GINTMSK_ESUSPM_Pos   (10U)
    -
    - -
    -
    - -

    ◆ USB_OTG_GINTMSK_ESUSPM_Msk

    - -
    -
    - - - - -
    #define USB_OTG_GINTMSK_ESUSPM_Msk   (0x1UL << USB_OTG_GINTMSK_ESUSPM_Pos)
    -
    -

    0x00000400

    - -
    -
    - -

    ◆ USB_OTG_GINTMSK_ESUSPM

    - -
    -
    - - - - -
    #define USB_OTG_GINTMSK_ESUSPM   USB_OTG_GINTMSK_ESUSPM_Msk
    -
    -

    Early suspend mask
    -

    - -
    -
    - -

    ◆ USB_OTG_GINTMSK_USBSUSPM_Pos

    - -
    -
    - - - - -
    #define USB_OTG_GINTMSK_USBSUSPM_Pos   (11U)
    -
    - -
    -
    - -

    ◆ USB_OTG_GINTMSK_USBSUSPM_Msk

    - -
    -
    - - - - -
    #define USB_OTG_GINTMSK_USBSUSPM_Msk   (0x1UL << USB_OTG_GINTMSK_USBSUSPM_Pos)
    -
    -

    0x00000800

    - -
    -
    - -

    ◆ USB_OTG_GINTMSK_USBSUSPM

    - -
    -
    - - - - -
    #define USB_OTG_GINTMSK_USBSUSPM   USB_OTG_GINTMSK_USBSUSPM_Msk
    -
    -

    USB suspend mask
    -

    - -
    -
    - -

    ◆ USB_OTG_GINTMSK_USBRST_Pos

    - -
    -
    - - - - -
    #define USB_OTG_GINTMSK_USBRST_Pos   (12U)
    -
    - -
    -
    - -

    ◆ USB_OTG_GINTMSK_USBRST_Msk

    - -
    -
    - - - - -
    #define USB_OTG_GINTMSK_USBRST_Msk   (0x1UL << USB_OTG_GINTMSK_USBRST_Pos)
    -
    -

    0x00001000

    - -
    -
    - -

    ◆ USB_OTG_GINTMSK_USBRST

    - -
    -
    - - - - -
    #define USB_OTG_GINTMSK_USBRST   USB_OTG_GINTMSK_USBRST_Msk
    -
    -

    USB reset mask
    -

    - -
    -
    - -

    ◆ USB_OTG_GINTMSK_ENUMDNEM_Pos

    - -
    -
    - - - - -
    #define USB_OTG_GINTMSK_ENUMDNEM_Pos   (13U)
    -
    - -
    -
    - -

    ◆ USB_OTG_GINTMSK_ENUMDNEM_Msk

    - -
    -
    - - - - -
    #define USB_OTG_GINTMSK_ENUMDNEM_Msk   (0x1UL << USB_OTG_GINTMSK_ENUMDNEM_Pos)
    -
    -

    0x00002000

    - -
    -
    - -

    ◆ USB_OTG_GINTMSK_ENUMDNEM

    - -
    -
    - - - - -
    #define USB_OTG_GINTMSK_ENUMDNEM   USB_OTG_GINTMSK_ENUMDNEM_Msk
    -
    -

    Enumeration done mask
    -

    - -
    -
    - -

    ◆ USB_OTG_GINTMSK_ISOODRPM_Pos

    - -
    -
    - - - - -
    #define USB_OTG_GINTMSK_ISOODRPM_Pos   (14U)
    -
    - -
    -
    - -

    ◆ USB_OTG_GINTMSK_ISOODRPM_Msk

    - -
    -
    - - - - -
    #define USB_OTG_GINTMSK_ISOODRPM_Msk   (0x1UL << USB_OTG_GINTMSK_ISOODRPM_Pos)
    -
    -

    0x00004000

    - -
    -
    - -

    ◆ USB_OTG_GINTMSK_ISOODRPM

    - -
    -
    - - - - -
    #define USB_OTG_GINTMSK_ISOODRPM   USB_OTG_GINTMSK_ISOODRPM_Msk
    -
    -

    Isochronous OUT packet dropped interrupt mask
    -

    - -
    -
    - -

    ◆ USB_OTG_GINTMSK_EOPFM_Pos

    - -
    -
    - - - - -
    #define USB_OTG_GINTMSK_EOPFM_Pos   (15U)
    -
    - -
    -
    - -

    ◆ USB_OTG_GINTMSK_EOPFM_Msk

    - -
    -
    - - - - -
    #define USB_OTG_GINTMSK_EOPFM_Msk   (0x1UL << USB_OTG_GINTMSK_EOPFM_Pos)
    -
    -

    0x00008000

    - -
    -
    - -

    ◆ USB_OTG_GINTMSK_EOPFM

    - -
    -
    - - - - -
    #define USB_OTG_GINTMSK_EOPFM   USB_OTG_GINTMSK_EOPFM_Msk
    -
    -

    End of periodic frame interrupt mask
    -

    - -
    -
    - -

    ◆ USB_OTG_GINTMSK_EPMISM_Pos

    - -
    -
    - - - - -
    #define USB_OTG_GINTMSK_EPMISM_Pos   (17U)
    -
    - -
    -
    - -

    ◆ USB_OTG_GINTMSK_EPMISM_Msk

    - -
    -
    - - - - -
    #define USB_OTG_GINTMSK_EPMISM_Msk   (0x1UL << USB_OTG_GINTMSK_EPMISM_Pos)
    -
    -

    0x00020000

    - -
    -
    - -

    ◆ USB_OTG_GINTMSK_EPMISM

    - -
    -
    - - - - -
    #define USB_OTG_GINTMSK_EPMISM   USB_OTG_GINTMSK_EPMISM_Msk
    -
    -

    Endpoint mismatch interrupt mask
    -

    - -
    -
    - -

    ◆ USB_OTG_GINTMSK_IEPINT_Pos

    - -
    -
    - - - - -
    #define USB_OTG_GINTMSK_IEPINT_Pos   (18U)
    -
    - -
    -
    - -

    ◆ USB_OTG_GINTMSK_IEPINT_Msk

    - -
    -
    - - - - -
    #define USB_OTG_GINTMSK_IEPINT_Msk   (0x1UL << USB_OTG_GINTMSK_IEPINT_Pos)
    -
    -

    0x00040000

    - -
    -
    - -

    ◆ USB_OTG_GINTMSK_IEPINT

    - -
    -
    - - - - -
    #define USB_OTG_GINTMSK_IEPINT   USB_OTG_GINTMSK_IEPINT_Msk
    -
    -

    IN endpoints interrupt mask
    -

    - -
    -
    - -

    ◆ USB_OTG_GINTMSK_OEPINT_Pos

    - -
    -
    - - - - -
    #define USB_OTG_GINTMSK_OEPINT_Pos   (19U)
    -
    - -
    -
    - -

    ◆ USB_OTG_GINTMSK_OEPINT_Msk

    - -
    -
    - - - - -
    #define USB_OTG_GINTMSK_OEPINT_Msk   (0x1UL << USB_OTG_GINTMSK_OEPINT_Pos)
    -
    -

    0x00080000

    - -
    -
    - -

    ◆ USB_OTG_GINTMSK_OEPINT

    - -
    -
    - - - - -
    #define USB_OTG_GINTMSK_OEPINT   USB_OTG_GINTMSK_OEPINT_Msk
    -
    -

    OUT endpoints interrupt mask
    -

    - -
    -
    - -

    ◆ USB_OTG_GINTMSK_IISOIXFRM_Pos

    - -
    -
    - - - - -
    #define USB_OTG_GINTMSK_IISOIXFRM_Pos   (20U)
    -
    - -
    -
    - -

    ◆ USB_OTG_GINTMSK_IISOIXFRM_Msk

    - -
    -
    - - - - -
    #define USB_OTG_GINTMSK_IISOIXFRM_Msk   (0x1UL << USB_OTG_GINTMSK_IISOIXFRM_Pos)
    -
    -

    0x00100000

    - -
    -
    - -

    ◆ USB_OTG_GINTMSK_IISOIXFRM

    - -
    -
    - - - - -
    #define USB_OTG_GINTMSK_IISOIXFRM   USB_OTG_GINTMSK_IISOIXFRM_Msk
    -
    -

    Incomplete isochronous IN transfer mask
    -

    - -
    -
    - -

    ◆ USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos

    - -
    -
    - - - - -
    #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos   (21U)
    -
    - -
    -
    - -

    ◆ USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk

    - -
    -
    - - - - -
    #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk   (0x1UL << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos)
    -
    -

    0x00200000

    - -
    -
    - -

    ◆ USB_OTG_GINTMSK_PXFRM_IISOOXFRM

    - -
    -
    - - - - -
    #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM   USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk
    -
    -

    Incomplete periodic transfer mask
    -

    - -
    -
    - -

    ◆ USB_OTG_GINTMSK_FSUSPM_Pos

    - -
    -
    - - - - -
    #define USB_OTG_GINTMSK_FSUSPM_Pos   (22U)
    -
    - -
    -
    - -

    ◆ USB_OTG_GINTMSK_FSUSPM_Msk

    - -
    -
    - - - - -
    #define USB_OTG_GINTMSK_FSUSPM_Msk   (0x1UL << USB_OTG_GINTMSK_FSUSPM_Pos)
    -
    -

    0x00400000

    - -
    -
    - -

    ◆ USB_OTG_GINTMSK_FSUSPM

    - -
    -
    - - - - -
    #define USB_OTG_GINTMSK_FSUSPM   USB_OTG_GINTMSK_FSUSPM_Msk
    -
    -

    Data fetch suspended mask
    -

    - -
    -
    - -

    ◆ USB_OTG_GINTMSK_PRTIM_Pos

    - -
    -
    - - - - -
    #define USB_OTG_GINTMSK_PRTIM_Pos   (24U)
    -
    - -
    -
    - -

    ◆ USB_OTG_GINTMSK_PRTIM_Msk

    - -
    -
    - - - - -
    #define USB_OTG_GINTMSK_PRTIM_Msk   (0x1UL << USB_OTG_GINTMSK_PRTIM_Pos)
    -
    -

    0x01000000

    - -
    -
    - -

    ◆ USB_OTG_GINTMSK_PRTIM

    - -
    -
    - - - - -
    #define USB_OTG_GINTMSK_PRTIM   USB_OTG_GINTMSK_PRTIM_Msk
    -
    -

    Host port interrupt mask
    -

    - -
    -
    - -

    ◆ USB_OTG_GINTMSK_HCIM_Pos

    - -
    -
    - - - - -
    #define USB_OTG_GINTMSK_HCIM_Pos   (25U)
    -
    - -
    -
    - -

    ◆ USB_OTG_GINTMSK_HCIM_Msk

    - -
    -
    - - - - -
    #define USB_OTG_GINTMSK_HCIM_Msk   (0x1UL << USB_OTG_GINTMSK_HCIM_Pos)
    -
    -

    0x02000000

    - -
    -
    - -

    ◆ USB_OTG_GINTMSK_HCIM

    - -
    -
    - - - - -
    #define USB_OTG_GINTMSK_HCIM   USB_OTG_GINTMSK_HCIM_Msk
    -
    -

    Host channels interrupt mask
    -

    - -
    -
    - -

    ◆ USB_OTG_GINTMSK_PTXFEM_Pos

    - -
    -
    - - - - -
    #define USB_OTG_GINTMSK_PTXFEM_Pos   (26U)
    -
    - -
    -
    - -

    ◆ USB_OTG_GINTMSK_PTXFEM_Msk

    - -
    -
    - - - - -
    #define USB_OTG_GINTMSK_PTXFEM_Msk   (0x1UL << USB_OTG_GINTMSK_PTXFEM_Pos)
    -
    -

    0x04000000

    - -
    -
    - -

    ◆ USB_OTG_GINTMSK_PTXFEM

    - -
    -
    - - - - -
    #define USB_OTG_GINTMSK_PTXFEM   USB_OTG_GINTMSK_PTXFEM_Msk
    -
    -

    Periodic TxFIFO empty mask
    -

    - -
    -
    - -

    ◆ USB_OTG_GINTMSK_CIDSCHGM_Pos

    - -
    -
    - - - - -
    #define USB_OTG_GINTMSK_CIDSCHGM_Pos   (28U)
    -
    - -
    -
    - -

    ◆ USB_OTG_GINTMSK_CIDSCHGM_Msk

    - -
    -
    - - - - -
    #define USB_OTG_GINTMSK_CIDSCHGM_Msk   (0x1UL << USB_OTG_GINTMSK_CIDSCHGM_Pos)
    -
    -

    0x10000000

    - -
    -
    - -

    ◆ USB_OTG_GINTMSK_CIDSCHGM

    - -
    -
    - - - - -
    #define USB_OTG_GINTMSK_CIDSCHGM   USB_OTG_GINTMSK_CIDSCHGM_Msk
    -
    -

    Connector ID status change mask
    -

    - -
    -
    - -

    ◆ USB_OTG_GINTMSK_DISCINT_Pos

    - -
    -
    - - - - -
    #define USB_OTG_GINTMSK_DISCINT_Pos   (29U)
    -
    - -
    -
    - -

    ◆ USB_OTG_GINTMSK_DISCINT_Msk

    - -
    -
    - - - - -
    #define USB_OTG_GINTMSK_DISCINT_Msk   (0x1UL << USB_OTG_GINTMSK_DISCINT_Pos)
    -
    -

    0x20000000

    - -
    -
    - -

    ◆ USB_OTG_GINTMSK_DISCINT

    - -
    -
    - - - - -
    #define USB_OTG_GINTMSK_DISCINT   USB_OTG_GINTMSK_DISCINT_Msk
    -
    -

    Disconnect detected interrupt mask
    -

    - -
    -
    - -

    ◆ USB_OTG_GINTMSK_SRQIM_Pos

    - -
    -
    - - - - -
    #define USB_OTG_GINTMSK_SRQIM_Pos   (30U)
    -
    - -
    -
    - -

    ◆ USB_OTG_GINTMSK_SRQIM_Msk

    - -
    -
    - - - - -
    #define USB_OTG_GINTMSK_SRQIM_Msk   (0x1UL << USB_OTG_GINTMSK_SRQIM_Pos)
    -
    -

    0x40000000

    - -
    -
    - -

    ◆ USB_OTG_GINTMSK_SRQIM

    - -
    -
    - - - - -
    #define USB_OTG_GINTMSK_SRQIM   USB_OTG_GINTMSK_SRQIM_Msk
    -
    -

    Session request/new session detected interrupt mask

    - -
    -
    - -

    ◆ USB_OTG_GINTMSK_WUIM_Pos

    - -
    -
    - - - - -
    #define USB_OTG_GINTMSK_WUIM_Pos   (31U)
    -
    - -
    -
    - -

    ◆ USB_OTG_GINTMSK_WUIM_Msk

    - -
    -
    - - - - -
    #define USB_OTG_GINTMSK_WUIM_Msk   (0x1UL << USB_OTG_GINTMSK_WUIM_Pos)
    -
    -

    0x80000000

    - -
    -
    - -

    ◆ USB_OTG_GINTMSK_WUIM

    - -
    -
    - - - - -
    #define USB_OTG_GINTMSK_WUIM   USB_OTG_GINTMSK_WUIM_Msk
    -
    -

    Resume/remote wakeup detected interrupt mask
    -

    - -
    -
    - -

    ◆ USB_OTG_DAINT_IEPINT_Pos

    - -
    -
    - - - - -
    #define USB_OTG_DAINT_IEPINT_Pos   (0U)
    -
    - -
    -
    - -

    ◆ USB_OTG_DAINT_IEPINT_Msk

    - -
    -
    - - - - -
    #define USB_OTG_DAINT_IEPINT_Msk   (0xFFFFUL << USB_OTG_DAINT_IEPINT_Pos)
    -
    -

    0x0000FFFF

    - -
    -
    - -

    ◆ USB_OTG_DAINT_IEPINT

    - -
    -
    - - - - -
    #define USB_OTG_DAINT_IEPINT   USB_OTG_DAINT_IEPINT_Msk
    -
    -

    IN endpoint interrupt bits
    -

    - -
    -
    - -

    ◆ USB_OTG_DAINT_OEPINT_Pos

    - -
    -
    - - - - -
    #define USB_OTG_DAINT_OEPINT_Pos   (16U)
    -
    - -
    -
    - -

    ◆ USB_OTG_DAINT_OEPINT_Msk

    - -
    -
    - - - - -
    #define USB_OTG_DAINT_OEPINT_Msk   (0xFFFFUL << USB_OTG_DAINT_OEPINT_Pos)
    -
    -

    0xFFFF0000

    - -
    -
    - -

    ◆ USB_OTG_DAINT_OEPINT

    - -
    -
    - - - - -
    #define USB_OTG_DAINT_OEPINT   USB_OTG_DAINT_OEPINT_Msk
    -
    -

    OUT endpoint interrupt bits

    - -
    -
    - -

    ◆ USB_OTG_HAINTMSK_HAINTM_Pos

    - -
    -
    - - - - -
    #define USB_OTG_HAINTMSK_HAINTM_Pos   (0U)
    -
    - -
    -
    - -

    ◆ USB_OTG_HAINTMSK_HAINTM_Msk

    - -
    -
    - - - - -
    #define USB_OTG_HAINTMSK_HAINTM_Msk   (0xFFFFUL << USB_OTG_HAINTMSK_HAINTM_Pos)
    -
    -

    0x0000FFFF

    - -
    -
    - -

    ◆ USB_OTG_HAINTMSK_HAINTM

    - -
    -
    - - - - -
    #define USB_OTG_HAINTMSK_HAINTM   USB_OTG_HAINTMSK_HAINTM_Msk
    -
    -

    Channel interrupt mask

    - -
    -
    - -

    ◆ USB_OTG_GRXSTSP_EPNUM_Pos

    - -
    -
    - - - - -
    #define USB_OTG_GRXSTSP_EPNUM_Pos   (0U)
    -
    - -
    -
    - -

    ◆ USB_OTG_GRXSTSP_EPNUM_Msk

    - -
    -
    - - - - -
    #define USB_OTG_GRXSTSP_EPNUM_Msk   (0xFUL << USB_OTG_GRXSTSP_EPNUM_Pos)
    -
    -

    0x0000000F

    - -
    -
    - -

    ◆ USB_OTG_GRXSTSP_EPNUM

    - -
    -
    - - - - -
    #define USB_OTG_GRXSTSP_EPNUM   USB_OTG_GRXSTSP_EPNUM_Msk
    -
    -

    IN EP interrupt mask bits
    -

    - -
    -
    - -

    ◆ USB_OTG_GRXSTSP_BCNT_Pos

    - -
    -
    - - - - -
    #define USB_OTG_GRXSTSP_BCNT_Pos   (4U)
    -
    - -
    -
    - -

    ◆ USB_OTG_GRXSTSP_BCNT_Msk

    - -
    -
    - - - - -
    #define USB_OTG_GRXSTSP_BCNT_Msk   (0x7FFUL << USB_OTG_GRXSTSP_BCNT_Pos)
    -
    -

    0x00007FF0

    - -
    -
    - -

    ◆ USB_OTG_GRXSTSP_BCNT

    - -
    -
    - - - - -
    #define USB_OTG_GRXSTSP_BCNT   USB_OTG_GRXSTSP_BCNT_Msk
    -
    -

    OUT EP interrupt mask bits

    - -
    -
    - -

    ◆ USB_OTG_GRXSTSP_DPID_Pos

    - -
    -
    - - - - -
    #define USB_OTG_GRXSTSP_DPID_Pos   (15U)
    -
    - -
    -
    - -

    ◆ USB_OTG_GRXSTSP_DPID_Msk

    - -
    -
    - - - - -
    #define USB_OTG_GRXSTSP_DPID_Msk   (0x3UL << USB_OTG_GRXSTSP_DPID_Pos)
    -
    -

    0x00018000

    - -
    -
    - -

    ◆ USB_OTG_GRXSTSP_DPID

    - -
    -
    - - - - -
    #define USB_OTG_GRXSTSP_DPID   USB_OTG_GRXSTSP_DPID_Msk
    -
    -

    OUT EP interrupt mask bits

    - -
    -
    - -

    ◆ USB_OTG_GRXSTSP_PKTSTS_Pos

    - -
    -
    - - - - -
    #define USB_OTG_GRXSTSP_PKTSTS_Pos   (17U)
    -
    - -
    -
    - -

    ◆ USB_OTG_GRXSTSP_PKTSTS_Msk

    - -
    -
    - - - - -
    #define USB_OTG_GRXSTSP_PKTSTS_Msk   (0xFUL << USB_OTG_GRXSTSP_PKTSTS_Pos)
    -
    -

    0x001E0000

    - -
    -
    - -

    ◆ USB_OTG_GRXSTSP_PKTSTS

    - -
    -
    - - - - -
    #define USB_OTG_GRXSTSP_PKTSTS   USB_OTG_GRXSTSP_PKTSTS_Msk
    -
    -

    OUT EP interrupt mask bits

    - -
    -
    - -

    ◆ USB_OTG_DAINTMSK_IEPM_Pos

    - -
    -
    - - - - -
    #define USB_OTG_DAINTMSK_IEPM_Pos   (0U)
    -
    - -
    -
    - -

    ◆ USB_OTG_DAINTMSK_IEPM_Msk

    - -
    -
    - - - - -
    #define USB_OTG_DAINTMSK_IEPM_Msk   (0xFFFFUL << USB_OTG_DAINTMSK_IEPM_Pos)
    -
    -

    0x0000FFFF

    - -
    -
    - -

    ◆ USB_OTG_DAINTMSK_IEPM

    - -
    -
    - - - - -
    #define USB_OTG_DAINTMSK_IEPM   USB_OTG_DAINTMSK_IEPM_Msk
    -
    -

    IN EP interrupt mask bits

    - -
    -
    - -

    ◆ USB_OTG_DAINTMSK_OEPM_Pos

    - -
    -
    - - - - -
    #define USB_OTG_DAINTMSK_OEPM_Pos   (16U)
    -
    - -
    -
    - -

    ◆ USB_OTG_DAINTMSK_OEPM_Msk

    - -
    -
    - - - - -
    #define USB_OTG_DAINTMSK_OEPM_Msk   (0xFFFFUL << USB_OTG_DAINTMSK_OEPM_Pos)
    -
    -

    0xFFFF0000

    - -
    -
    - -

    ◆ USB_OTG_DAINTMSK_OEPM

    - -
    -
    - - - - -
    #define USB_OTG_DAINTMSK_OEPM   USB_OTG_DAINTMSK_OEPM_Msk
    -
    -

    OUT EP interrupt mask bits

    - -
    -
    - -

    ◆ USB_OTG_GRXFSIZ_RXFD_Pos

    - -
    -
    - - - - -
    #define USB_OTG_GRXFSIZ_RXFD_Pos   (0U)
    -
    - -
    -
    - -

    ◆ USB_OTG_GRXFSIZ_RXFD_Msk

    - -
    -
    - - - - -
    #define USB_OTG_GRXFSIZ_RXFD_Msk   (0xFFFFUL << USB_OTG_GRXFSIZ_RXFD_Pos)
    -
    -

    0x0000FFFF

    - -
    -
    - -

    ◆ USB_OTG_GRXFSIZ_RXFD

    - -
    -
    - - - - -
    #define USB_OTG_GRXFSIZ_RXFD   USB_OTG_GRXFSIZ_RXFD_Msk
    -
    -

    RxFIFO depth

    - -
    -
    - -

    ◆ USB_OTG_DVBUSDIS_VBUSDT_Pos

    - -
    -
    - - - - -
    #define USB_OTG_DVBUSDIS_VBUSDT_Pos   (0U)
    -
    - -
    -
    - -

    ◆ USB_OTG_DVBUSDIS_VBUSDT_Msk

    - -
    -
    - - - - -
    #define USB_OTG_DVBUSDIS_VBUSDT_Msk   (0xFFFFUL << USB_OTG_DVBUSDIS_VBUSDT_Pos)
    -
    -

    0x0000FFFF

    - -
    -
    - -

    ◆ USB_OTG_DVBUSDIS_VBUSDT

    - -
    -
    - - - - -
    #define USB_OTG_DVBUSDIS_VBUSDT   USB_OTG_DVBUSDIS_VBUSDT_Msk
    -
    -

    Device VBUS discharge time

    - -
    -
    - -

    ◆ USB_OTG_NPTXFSA_Pos

    - -
    -
    - - - - -
    #define USB_OTG_NPTXFSA_Pos   (0U)
    -
    - -
    -
    - -

    ◆ USB_OTG_NPTXFSA_Msk

    - -
    -
    - - - - -
    #define USB_OTG_NPTXFSA_Msk   (0xFFFFUL << USB_OTG_NPTXFSA_Pos)
    -
    -

    0x0000FFFF

    - -
    -
    - -

    ◆ USB_OTG_NPTXFSA

    - -
    -
    - - - - -
    #define USB_OTG_NPTXFSA   USB_OTG_NPTXFSA_Msk
    -
    -

    Nonperiodic transmit RAM start address

    - -
    -
    - -

    ◆ USB_OTG_NPTXFD_Pos

    - -
    -
    - - - - -
    #define USB_OTG_NPTXFD_Pos   (16U)
    -
    - -
    -
    - -

    ◆ USB_OTG_NPTXFD_Msk

    - -
    -
    - - - - -
    #define USB_OTG_NPTXFD_Msk   (0xFFFFUL << USB_OTG_NPTXFD_Pos)
    -
    -

    0xFFFF0000

    - -
    -
    - -

    ◆ USB_OTG_NPTXFD

    - -
    -
    - - - - -
    #define USB_OTG_NPTXFD   USB_OTG_NPTXFD_Msk
    -
    -

    Nonperiodic TxFIFO depth
    -

    - -
    -
    - -

    ◆ USB_OTG_TX0FSA_Pos

    - -
    -
    - - - - -
    #define USB_OTG_TX0FSA_Pos   (0U)
    -
    - -
    -
    - -

    ◆ USB_OTG_TX0FSA_Msk

    - -
    -
    - - - - -
    #define USB_OTG_TX0FSA_Msk   (0xFFFFUL << USB_OTG_TX0FSA_Pos)
    -
    -

    0x0000FFFF

    - -
    -
    - -

    ◆ USB_OTG_TX0FSA

    - -
    -
    - - - - -
    #define USB_OTG_TX0FSA   USB_OTG_TX0FSA_Msk
    -
    -

    Endpoint 0 transmit RAM start address
    -

    - -
    -
    - -

    ◆ USB_OTG_TX0FD_Pos

    - -
    -
    - - - - -
    #define USB_OTG_TX0FD_Pos   (16U)
    -
    - -
    -
    - -

    ◆ USB_OTG_TX0FD_Msk

    - -
    -
    - - - - -
    #define USB_OTG_TX0FD_Msk   (0xFFFFUL << USB_OTG_TX0FD_Pos)
    -
    -

    0xFFFF0000

    - -
    -
    - -

    ◆ USB_OTG_TX0FD

    - -
    -
    - - - - -
    #define USB_OTG_TX0FD   USB_OTG_TX0FD_Msk
    -
    -

    Endpoint 0 TxFIFO depth
    -

    - -
    -
    - -

    ◆ USB_OTG_DVBUSPULSE_DVBUSP_Pos

    - -
    -
    - - - - -
    #define USB_OTG_DVBUSPULSE_DVBUSP_Pos   (0U)
    -
    - -
    -
    - -

    ◆ USB_OTG_DVBUSPULSE_DVBUSP_Msk

    - -
    -
    - - - - -
    #define USB_OTG_DVBUSPULSE_DVBUSP_Msk   (0xFFFUL << USB_OTG_DVBUSPULSE_DVBUSP_Pos)
    -
    -

    0x00000FFF

    - -
    -
    - -

    ◆ USB_OTG_DVBUSPULSE_DVBUSP

    - -
    -
    - - - - -
    #define USB_OTG_DVBUSPULSE_DVBUSP   USB_OTG_DVBUSPULSE_DVBUSP_Msk
    -
    -

    Device VBUS pulsing time

    - -
    -
    - -

    ◆ USB_OTG_GNPTXSTS_NPTXFSAV_Pos

    - -
    -
    - - - - -
    #define USB_OTG_GNPTXSTS_NPTXFSAV_Pos   (0U)
    -
    - -
    -
    - -

    ◆ USB_OTG_GNPTXSTS_NPTXFSAV_Msk

    - -
    -
    - - - - -
    #define USB_OTG_GNPTXSTS_NPTXFSAV_Msk   (0xFFFFUL << USB_OTG_GNPTXSTS_NPTXFSAV_Pos)
    -
    -

    0x0000FFFF

    - -
    -
    - -

    ◆ USB_OTG_GNPTXSTS_NPTXFSAV

    - -
    -
    - - - - -
    #define USB_OTG_GNPTXSTS_NPTXFSAV   USB_OTG_GNPTXSTS_NPTXFSAV_Msk
    -
    -

    Nonperiodic TxFIFO space available

    - -
    -
    - -

    ◆ USB_OTG_GNPTXSTS_NPTQXSAV_Pos

    - -
    -
    - - - - -
    #define USB_OTG_GNPTXSTS_NPTQXSAV_Pos   (16U)
    -
    - -
    -
    - -

    ◆ USB_OTG_GNPTXSTS_NPTQXSAV_Msk

    - -
    -
    - - - - -
    #define USB_OTG_GNPTXSTS_NPTQXSAV_Msk   (0xFFUL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
    -
    -

    0x00FF0000

    - -
    -
    - -

    ◆ USB_OTG_GNPTXSTS_NPTQXSAV

    - -
    -
    - - - - -
    #define USB_OTG_GNPTXSTS_NPTQXSAV   USB_OTG_GNPTXSTS_NPTQXSAV_Msk
    -
    -

    Nonperiodic transmit request queue space available

    - -
    -
    - -

    ◆ USB_OTG_GNPTXSTS_NPTQXSAV_0

    - -
    -
    - - - - -
    #define USB_OTG_GNPTXSTS_NPTQXSAV_0   (0x01UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
    -
    -

    0x00010000

    - -
    -
    - -

    ◆ USB_OTG_GNPTXSTS_NPTQXSAV_1

    - -
    -
    - - - - -
    #define USB_OTG_GNPTXSTS_NPTQXSAV_1   (0x02UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
    -
    -

    0x00020000

    - -
    -
    - -

    ◆ USB_OTG_GNPTXSTS_NPTQXSAV_2

    - -
    -
    - - - - -
    #define USB_OTG_GNPTXSTS_NPTQXSAV_2   (0x04UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
    -
    -

    0x00040000

    - -
    -
    - -

    ◆ USB_OTG_GNPTXSTS_NPTQXSAV_3

    - -
    -
    - - - - -
    #define USB_OTG_GNPTXSTS_NPTQXSAV_3   (0x08UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
    -
    -

    0x00080000

    - -
    -
    - -

    ◆ USB_OTG_GNPTXSTS_NPTQXSAV_4

    - -
    -
    - - - - -
    #define USB_OTG_GNPTXSTS_NPTQXSAV_4   (0x10UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
    -
    -

    0x00100000

    - -
    -
    - -

    ◆ USB_OTG_GNPTXSTS_NPTQXSAV_5

    - -
    -
    - - - - -
    #define USB_OTG_GNPTXSTS_NPTQXSAV_5   (0x20UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
    -
    -

    0x00200000

    - -
    -
    - -

    ◆ USB_OTG_GNPTXSTS_NPTQXSAV_6

    - -
    -
    - - - - -
    #define USB_OTG_GNPTXSTS_NPTQXSAV_6   (0x40UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
    -
    -

    0x00400000

    - -
    -
    - -

    ◆ USB_OTG_GNPTXSTS_NPTQXSAV_7

    - -
    -
    - - - - -
    #define USB_OTG_GNPTXSTS_NPTQXSAV_7   (0x80UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
    -
    -

    0x00800000

    - -
    -
    - -

    ◆ USB_OTG_GNPTXSTS_NPTXQTOP_Pos

    - -
    -
    - - - - -
    #define USB_OTG_GNPTXSTS_NPTXQTOP_Pos   (24U)
    -
    - -
    -
    - -

    ◆ USB_OTG_GNPTXSTS_NPTXQTOP_Msk

    - -
    -
    - - - - -
    #define USB_OTG_GNPTXSTS_NPTXQTOP_Msk   (0x7FUL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
    -
    -

    0x7F000000

    - -
    -
    - -

    ◆ USB_OTG_GNPTXSTS_NPTXQTOP

    - -
    -
    - - - - -
    #define USB_OTG_GNPTXSTS_NPTXQTOP   USB_OTG_GNPTXSTS_NPTXQTOP_Msk
    -
    -

    Top of the nonperiodic transmit request queue

    - -
    -
    - -

    ◆ USB_OTG_GNPTXSTS_NPTXQTOP_0

    - -
    -
    - - - - -
    #define USB_OTG_GNPTXSTS_NPTXQTOP_0   (0x01UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
    -
    -

    0x01000000

    - -
    -
    - -

    ◆ USB_OTG_GNPTXSTS_NPTXQTOP_1

    - -
    -
    - - - - -
    #define USB_OTG_GNPTXSTS_NPTXQTOP_1   (0x02UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
    -
    -

    0x02000000

    - -
    -
    - -

    ◆ USB_OTG_GNPTXSTS_NPTXQTOP_2

    - -
    -
    - - - - -
    #define USB_OTG_GNPTXSTS_NPTXQTOP_2   (0x04UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
    -
    -

    0x04000000

    - -
    -
    - -

    ◆ USB_OTG_GNPTXSTS_NPTXQTOP_3

    - -
    -
    - - - - -
    #define USB_OTG_GNPTXSTS_NPTXQTOP_3   (0x08UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
    -
    -

    0x08000000

    - -
    -
    - -

    ◆ USB_OTG_GNPTXSTS_NPTXQTOP_4

    - -
    -
    - - - - -
    #define USB_OTG_GNPTXSTS_NPTXQTOP_4   (0x10UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
    -
    -

    0x10000000

    - -
    -
    - -

    ◆ USB_OTG_GNPTXSTS_NPTXQTOP_5

    - -
    -
    - - - - -
    #define USB_OTG_GNPTXSTS_NPTXQTOP_5   (0x20UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
    -
    -

    0x20000000

    - -
    -
    - -

    ◆ USB_OTG_GNPTXSTS_NPTXQTOP_6

    - -
    -
    - - - - -
    #define USB_OTG_GNPTXSTS_NPTXQTOP_6   (0x40UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
    -
    -

    0x40000000

    - -
    -
    - -

    ◆ USB_OTG_DTHRCTL_NONISOTHREN_Pos

    - -
    -
    - - - - -
    #define USB_OTG_DTHRCTL_NONISOTHREN_Pos   (0U)
    -
    - -
    -
    - -

    ◆ USB_OTG_DTHRCTL_NONISOTHREN_Msk

    - -
    -
    - - - - -
    #define USB_OTG_DTHRCTL_NONISOTHREN_Msk   (0x1UL << USB_OTG_DTHRCTL_NONISOTHREN_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ USB_OTG_DTHRCTL_NONISOTHREN

    - -
    -
    - - - - -
    #define USB_OTG_DTHRCTL_NONISOTHREN   USB_OTG_DTHRCTL_NONISOTHREN_Msk
    -
    -

    Nonisochronous IN endpoints threshold enable

    - -
    -
    - -

    ◆ USB_OTG_DTHRCTL_ISOTHREN_Pos

    - -
    -
    - - - - -
    #define USB_OTG_DTHRCTL_ISOTHREN_Pos   (1U)
    -
    - -
    -
    - -

    ◆ USB_OTG_DTHRCTL_ISOTHREN_Msk

    - -
    -
    - - - - -
    #define USB_OTG_DTHRCTL_ISOTHREN_Msk   (0x1UL << USB_OTG_DTHRCTL_ISOTHREN_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ USB_OTG_DTHRCTL_ISOTHREN

    - -
    -
    - - - - -
    #define USB_OTG_DTHRCTL_ISOTHREN   USB_OTG_DTHRCTL_ISOTHREN_Msk
    -
    -

    ISO IN endpoint threshold enable

    - -
    -
    - -

    ◆ USB_OTG_DTHRCTL_TXTHRLEN_Pos

    - -
    -
    - - - - -
    #define USB_OTG_DTHRCTL_TXTHRLEN_Pos   (2U)
    -
    - -
    -
    - -

    ◆ USB_OTG_DTHRCTL_TXTHRLEN_Msk

    - -
    -
    - - - - -
    #define USB_OTG_DTHRCTL_TXTHRLEN_Msk   (0x1FFUL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
    -
    -

    0x000007FC

    - -
    -
    - -

    ◆ USB_OTG_DTHRCTL_TXTHRLEN

    - -
    -
    - - - - -
    #define USB_OTG_DTHRCTL_TXTHRLEN   USB_OTG_DTHRCTL_TXTHRLEN_Msk
    -
    -

    Transmit threshold length

    - -
    -
    - -

    ◆ USB_OTG_DTHRCTL_TXTHRLEN_0

    - -
    -
    - - - - -
    #define USB_OTG_DTHRCTL_TXTHRLEN_0   (0x001UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
    -
    -

    0x00000004

    - -
    -
    - -

    ◆ USB_OTG_DTHRCTL_TXTHRLEN_1

    - -
    -
    - - - - -
    #define USB_OTG_DTHRCTL_TXTHRLEN_1   (0x002UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
    -
    -

    0x00000008

    - -
    -
    - -

    ◆ USB_OTG_DTHRCTL_TXTHRLEN_2

    - -
    -
    - - - - -
    #define USB_OTG_DTHRCTL_TXTHRLEN_2   (0x004UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
    -
    -

    0x00000010

    - -
    -
    - -

    ◆ USB_OTG_DTHRCTL_TXTHRLEN_3

    - -
    -
    - - - - -
    #define USB_OTG_DTHRCTL_TXTHRLEN_3   (0x008UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
    -
    -

    0x00000020

    - -
    -
    - -

    ◆ USB_OTG_DTHRCTL_TXTHRLEN_4

    - -
    -
    - - - - -
    #define USB_OTG_DTHRCTL_TXTHRLEN_4   (0x010UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
    -
    -

    0x00000040

    - -
    -
    - -

    ◆ USB_OTG_DTHRCTL_TXTHRLEN_5

    - -
    -
    - - - - -
    #define USB_OTG_DTHRCTL_TXTHRLEN_5   (0x020UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
    -
    -

    0x00000080

    - -
    -
    - -

    ◆ USB_OTG_DTHRCTL_TXTHRLEN_6

    - -
    -
    - - - - -
    #define USB_OTG_DTHRCTL_TXTHRLEN_6   (0x040UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
    -
    -

    0x00000100

    - -
    -
    - -

    ◆ USB_OTG_DTHRCTL_TXTHRLEN_7

    - -
    -
    - - - - -
    #define USB_OTG_DTHRCTL_TXTHRLEN_7   (0x080UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
    -
    -

    0x00000200

    - -
    -
    - -

    ◆ USB_OTG_DTHRCTL_TXTHRLEN_8

    - -
    -
    - - - - -
    #define USB_OTG_DTHRCTL_TXTHRLEN_8   (0x100UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
    -
    -

    0x00000400

    - -
    -
    - -

    ◆ USB_OTG_DTHRCTL_RXTHREN_Pos

    - -
    -
    - - - - -
    #define USB_OTG_DTHRCTL_RXTHREN_Pos   (16U)
    -
    - -
    -
    - -

    ◆ USB_OTG_DTHRCTL_RXTHREN_Msk

    - -
    -
    - - - - -
    #define USB_OTG_DTHRCTL_RXTHREN_Msk   (0x1UL << USB_OTG_DTHRCTL_RXTHREN_Pos)
    -
    -

    0x00010000

    - -
    -
    - -

    ◆ USB_OTG_DTHRCTL_RXTHREN

    - -
    -
    - - - - -
    #define USB_OTG_DTHRCTL_RXTHREN   USB_OTG_DTHRCTL_RXTHREN_Msk
    -
    -

    Receive threshold enable

    - -
    -
    - -

    ◆ USB_OTG_DTHRCTL_RXTHRLEN_Pos

    - -
    -
    - - - - -
    #define USB_OTG_DTHRCTL_RXTHRLEN_Pos   (17U)
    -
    - -
    -
    - -

    ◆ USB_OTG_DTHRCTL_RXTHRLEN_Msk

    - -
    -
    - - - - -
    #define USB_OTG_DTHRCTL_RXTHRLEN_Msk   (0x1FFUL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
    -
    -

    0x03FE0000

    - -
    -
    - -

    ◆ USB_OTG_DTHRCTL_RXTHRLEN

    - -
    -
    - - - - -
    #define USB_OTG_DTHRCTL_RXTHRLEN   USB_OTG_DTHRCTL_RXTHRLEN_Msk
    -
    -

    Receive threshold length

    - -
    -
    - -

    ◆ USB_OTG_DTHRCTL_RXTHRLEN_0

    - -
    -
    - - - - -
    #define USB_OTG_DTHRCTL_RXTHRLEN_0   (0x001UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
    -
    -

    0x00020000

    - -
    -
    - -

    ◆ USB_OTG_DTHRCTL_RXTHRLEN_1

    - -
    -
    - - - - -
    #define USB_OTG_DTHRCTL_RXTHRLEN_1   (0x002UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
    -
    -

    0x00040000

    - -
    -
    - -

    ◆ USB_OTG_DTHRCTL_RXTHRLEN_2

    - -
    -
    - - - - -
    #define USB_OTG_DTHRCTL_RXTHRLEN_2   (0x004UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
    -
    -

    0x00080000

    - -
    -
    - -

    ◆ USB_OTG_DTHRCTL_RXTHRLEN_3

    - -
    -
    - - - - -
    #define USB_OTG_DTHRCTL_RXTHRLEN_3   (0x008UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
    -
    -

    0x00100000

    - -
    -
    - -

    ◆ USB_OTG_DTHRCTL_RXTHRLEN_4

    - -
    -
    - - - - -
    #define USB_OTG_DTHRCTL_RXTHRLEN_4   (0x010UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
    -
    -

    0x00200000

    - -
    -
    - -

    ◆ USB_OTG_DTHRCTL_RXTHRLEN_5

    - -
    -
    - - - - -
    #define USB_OTG_DTHRCTL_RXTHRLEN_5   (0x020UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
    -
    -

    0x00400000

    - -
    -
    - -

    ◆ USB_OTG_DTHRCTL_RXTHRLEN_6

    - -
    -
    - - - - -
    #define USB_OTG_DTHRCTL_RXTHRLEN_6   (0x040UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
    -
    -

    0x00800000

    - -
    -
    - -

    ◆ USB_OTG_DTHRCTL_RXTHRLEN_7

    - -
    -
    - - - - -
    #define USB_OTG_DTHRCTL_RXTHRLEN_7   (0x080UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
    -
    -

    0x01000000

    - -
    -
    - -

    ◆ USB_OTG_DTHRCTL_RXTHRLEN_8

    - -
    -
    - - - - -
    #define USB_OTG_DTHRCTL_RXTHRLEN_8   (0x100UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
    -
    -

    0x02000000

    - -
    -
    - -

    ◆ USB_OTG_DTHRCTL_ARPEN_Pos

    - -
    -
    - - - - -
    #define USB_OTG_DTHRCTL_ARPEN_Pos   (27U)
    -
    - -
    -
    - -

    ◆ USB_OTG_DTHRCTL_ARPEN_Msk

    - -
    -
    - - - - -
    #define USB_OTG_DTHRCTL_ARPEN_Msk   (0x1UL << USB_OTG_DTHRCTL_ARPEN_Pos)
    -
    -

    0x08000000

    - -
    -
    - -

    ◆ USB_OTG_DTHRCTL_ARPEN

    - -
    -
    - - - - -
    #define USB_OTG_DTHRCTL_ARPEN   USB_OTG_DTHRCTL_ARPEN_Msk
    -
    -

    Arbiter parking enable

    - -
    -
    - -

    ◆ USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos

    - -
    -
    - - - - -
    #define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos   (0U)
    -
    - -
    -
    - -

    ◆ USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk

    - -
    -
    - - - - -
    #define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk   (0xFFFFUL << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos)
    -
    -

    0x0000FFFF

    - -
    -
    - -

    ◆ USB_OTG_DIEPEMPMSK_INEPTXFEM

    - -
    -
    - - - - -
    #define USB_OTG_DIEPEMPMSK_INEPTXFEM   USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk
    -
    -

    IN EP Tx FIFO empty interrupt mask bits

    - -
    -
    - -

    ◆ USB_OTG_DEACHINT_IEP1INT_Pos

    - -
    -
    - - - - -
    #define USB_OTG_DEACHINT_IEP1INT_Pos   (1U)
    -
    - -
    -
    - -

    ◆ USB_OTG_DEACHINT_IEP1INT_Msk

    - -
    -
    - - - - -
    #define USB_OTG_DEACHINT_IEP1INT_Msk   (0x1UL << USB_OTG_DEACHINT_IEP1INT_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ USB_OTG_DEACHINT_IEP1INT

    - -
    -
    - - - - -
    #define USB_OTG_DEACHINT_IEP1INT   USB_OTG_DEACHINT_IEP1INT_Msk
    -
    -

    IN endpoint 1interrupt bit
    -

    - -
    -
    - -

    ◆ USB_OTG_DEACHINT_OEP1INT_Pos

    - -
    -
    - - - - -
    #define USB_OTG_DEACHINT_OEP1INT_Pos   (17U)
    -
    - -
    -
    - -

    ◆ USB_OTG_DEACHINT_OEP1INT_Msk

    - -
    -
    - - - - -
    #define USB_OTG_DEACHINT_OEP1INT_Msk   (0x1UL << USB_OTG_DEACHINT_OEP1INT_Pos)
    -
    -

    0x00020000

    - -
    -
    - -

    ◆ USB_OTG_DEACHINT_OEP1INT

    - -
    -
    - - - - -
    #define USB_OTG_DEACHINT_OEP1INT   USB_OTG_DEACHINT_OEP1INT_Msk
    -
    -

    OUT endpoint 1 interrupt bit

    - -
    -
    - -

    ◆ USB_OTG_GCCFG_PWRDWN_Pos

    - -
    -
    - - - - -
    #define USB_OTG_GCCFG_PWRDWN_Pos   (16U)
    -
    - -
    -
    - -

    ◆ USB_OTG_GCCFG_PWRDWN_Msk

    - -
    -
    - - - - -
    #define USB_OTG_GCCFG_PWRDWN_Msk   (0x1UL << USB_OTG_GCCFG_PWRDWN_Pos)
    -
    -

    0x00010000

    - -
    -
    - -

    ◆ USB_OTG_GCCFG_PWRDWN

    - -
    -
    - - - - -
    #define USB_OTG_GCCFG_PWRDWN   USB_OTG_GCCFG_PWRDWN_Msk
    -
    -

    Power down

    - -
    -
    - -

    ◆ USB_OTG_GCCFG_I2CPADEN_Pos

    - -
    -
    - - - - -
    #define USB_OTG_GCCFG_I2CPADEN_Pos   (17U)
    -
    - -
    -
    - -

    ◆ USB_OTG_GCCFG_I2CPADEN_Msk

    - -
    -
    - - - - -
    #define USB_OTG_GCCFG_I2CPADEN_Msk   (0x1UL << USB_OTG_GCCFG_I2CPADEN_Pos)
    -
    -

    0x00020000

    - -
    -
    - -

    ◆ USB_OTG_GCCFG_I2CPADEN

    - -
    -
    - - - - -
    #define USB_OTG_GCCFG_I2CPADEN   USB_OTG_GCCFG_I2CPADEN_Msk
    -
    -

    Enable I2C bus connection for the external I2C PHY interface

    - -
    -
    - -

    ◆ USB_OTG_GCCFG_VBUSASEN_Pos

    - -
    -
    - - - - -
    #define USB_OTG_GCCFG_VBUSASEN_Pos   (18U)
    -
    - -
    -
    - -

    ◆ USB_OTG_GCCFG_VBUSASEN_Msk

    - -
    -
    - - - - -
    #define USB_OTG_GCCFG_VBUSASEN_Msk   (0x1UL << USB_OTG_GCCFG_VBUSASEN_Pos)
    -
    -

    0x00040000

    - -
    -
    - -

    ◆ USB_OTG_GCCFG_VBUSASEN

    - -
    -
    - - - - -
    #define USB_OTG_GCCFG_VBUSASEN   USB_OTG_GCCFG_VBUSASEN_Msk
    -
    -

    Enable the VBUS sensing device

    - -
    -
    - -

    ◆ USB_OTG_GCCFG_VBUSBSEN_Pos

    - -
    -
    - - - - -
    #define USB_OTG_GCCFG_VBUSBSEN_Pos   (19U)
    -
    - -
    -
    - -

    ◆ USB_OTG_GCCFG_VBUSBSEN_Msk

    - -
    -
    - - - - -
    #define USB_OTG_GCCFG_VBUSBSEN_Msk   (0x1UL << USB_OTG_GCCFG_VBUSBSEN_Pos)
    -
    -

    0x00080000

    - -
    -
    - -

    ◆ USB_OTG_GCCFG_VBUSBSEN

    - -
    -
    - - - - -
    #define USB_OTG_GCCFG_VBUSBSEN   USB_OTG_GCCFG_VBUSBSEN_Msk
    -
    -

    Enable the VBUS sensing device

    - -
    -
    - -

    ◆ USB_OTG_GCCFG_SOFOUTEN_Pos

    - -
    -
    - - - - -
    #define USB_OTG_GCCFG_SOFOUTEN_Pos   (20U)
    -
    - -
    -
    - -

    ◆ USB_OTG_GCCFG_SOFOUTEN_Msk

    - -
    -
    - - - - -
    #define USB_OTG_GCCFG_SOFOUTEN_Msk   (0x1UL << USB_OTG_GCCFG_SOFOUTEN_Pos)
    -
    -

    0x00100000

    - -
    -
    - -

    ◆ USB_OTG_GCCFG_SOFOUTEN

    - -
    -
    - - - - -
    #define USB_OTG_GCCFG_SOFOUTEN   USB_OTG_GCCFG_SOFOUTEN_Msk
    -
    -

    SOF output enable

    - -
    -
    - -

    ◆ USB_OTG_GCCFG_NOVBUSSENS_Pos

    - -
    -
    - - - - -
    #define USB_OTG_GCCFG_NOVBUSSENS_Pos   (21U)
    -
    - -
    -
    - -

    ◆ USB_OTG_GCCFG_NOVBUSSENS_Msk

    - -
    -
    - - - - -
    #define USB_OTG_GCCFG_NOVBUSSENS_Msk   (0x1UL << USB_OTG_GCCFG_NOVBUSSENS_Pos)
    -
    -

    0x00200000

    - -
    -
    - -

    ◆ USB_OTG_GCCFG_NOVBUSSENS

    - -
    -
    - - - - -
    #define USB_OTG_GCCFG_NOVBUSSENS   USB_OTG_GCCFG_NOVBUSSENS_Msk
    -
    -

    VBUS sensing disable option

    - -
    -
    - -

    ◆ USB_OTG_DEACHINTMSK_IEP1INTM_Pos

    - -
    -
    - - - - -
    #define USB_OTG_DEACHINTMSK_IEP1INTM_Pos   (1U)
    -
    - -
    -
    - -

    ◆ USB_OTG_DEACHINTMSK_IEP1INTM_Msk

    - -
    -
    - - - - -
    #define USB_OTG_DEACHINTMSK_IEP1INTM_Msk   (0x1UL << USB_OTG_DEACHINTMSK_IEP1INTM_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ USB_OTG_DEACHINTMSK_IEP1INTM

    - -
    -
    - - - - -
    #define USB_OTG_DEACHINTMSK_IEP1INTM   USB_OTG_DEACHINTMSK_IEP1INTM_Msk
    -
    -

    IN Endpoint 1 interrupt mask bit
    -

    - -
    -
    - -

    ◆ USB_OTG_DEACHINTMSK_OEP1INTM_Pos

    - -
    -
    - - - - -
    #define USB_OTG_DEACHINTMSK_OEP1INTM_Pos   (17U)
    -
    - -
    -
    - -

    ◆ USB_OTG_DEACHINTMSK_OEP1INTM_Msk

    - -
    -
    - - - - -
    #define USB_OTG_DEACHINTMSK_OEP1INTM_Msk   (0x1UL << USB_OTG_DEACHINTMSK_OEP1INTM_Pos)
    -
    -

    0x00020000

    - -
    -
    - -

    ◆ USB_OTG_DEACHINTMSK_OEP1INTM

    - -
    -
    - - - - -
    #define USB_OTG_DEACHINTMSK_OEP1INTM   USB_OTG_DEACHINTMSK_OEP1INTM_Msk
    -
    -

    OUT Endpoint 1 interrupt mask bit

    - -
    -
    - -

    ◆ USB_OTG_CID_PRODUCT_ID_Pos

    - -
    -
    - - - - -
    #define USB_OTG_CID_PRODUCT_ID_Pos   (0U)
    -
    - -
    -
    - -

    ◆ USB_OTG_CID_PRODUCT_ID_Msk

    - -
    -
    - - - - -
    #define USB_OTG_CID_PRODUCT_ID_Msk   (0xFFFFFFFFUL << USB_OTG_CID_PRODUCT_ID_Pos)
    -
    -

    0xFFFFFFFF

    - -
    -
    - -

    ◆ USB_OTG_CID_PRODUCT_ID

    - -
    -
    - - - - -
    #define USB_OTG_CID_PRODUCT_ID   USB_OTG_CID_PRODUCT_ID_Msk
    -
    -

    Product ID field

    - -
    -
    - -

    ◆ USB_OTG_DIEPEACHMSK1_XFRCM_Pos

    - -
    -
    - - - - -
    #define USB_OTG_DIEPEACHMSK1_XFRCM_Pos   (0U)
    -
    - -
    -
    - -

    ◆ USB_OTG_DIEPEACHMSK1_XFRCM_Msk

    - -
    -
    - - - - -
    #define USB_OTG_DIEPEACHMSK1_XFRCM_Msk   (0x1UL << USB_OTG_DIEPEACHMSK1_XFRCM_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ USB_OTG_DIEPEACHMSK1_XFRCM

    - -
    -
    - - - - -
    #define USB_OTG_DIEPEACHMSK1_XFRCM   USB_OTG_DIEPEACHMSK1_XFRCM_Msk
    -
    -

    Transfer completed interrupt mask
    -

    - -
    -
    - -

    ◆ USB_OTG_DIEPEACHMSK1_EPDM_Pos

    - -
    -
    - - - - -
    #define USB_OTG_DIEPEACHMSK1_EPDM_Pos   (1U)
    -
    - -
    -
    - -

    ◆ USB_OTG_DIEPEACHMSK1_EPDM_Msk

    - -
    -
    - - - - -
    #define USB_OTG_DIEPEACHMSK1_EPDM_Msk   (0x1UL << USB_OTG_DIEPEACHMSK1_EPDM_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ USB_OTG_DIEPEACHMSK1_EPDM

    - -
    -
    - - - - -
    #define USB_OTG_DIEPEACHMSK1_EPDM   USB_OTG_DIEPEACHMSK1_EPDM_Msk
    -
    -

    Endpoint disabled interrupt mask
    -

    - -
    -
    - -

    ◆ USB_OTG_DIEPEACHMSK1_TOM_Pos

    - -
    -
    - - - - -
    #define USB_OTG_DIEPEACHMSK1_TOM_Pos   (3U)
    -
    - -
    -
    - -

    ◆ USB_OTG_DIEPEACHMSK1_TOM_Msk

    - -
    -
    - - - - -
    #define USB_OTG_DIEPEACHMSK1_TOM_Msk   (0x1UL << USB_OTG_DIEPEACHMSK1_TOM_Pos)
    -
    -

    0x00000008

    - -
    -
    - -

    ◆ USB_OTG_DIEPEACHMSK1_TOM

    - -
    -
    - - - - -
    #define USB_OTG_DIEPEACHMSK1_TOM   USB_OTG_DIEPEACHMSK1_TOM_Msk
    -
    -

    Timeout condition mask (nonisochronous endpoints)

    - -
    -
    - -

    ◆ USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos

    - -
    -
    - - - - -
    #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos   (4U)
    -
    - -
    -
    - -

    ◆ USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk

    - -
    -
    - - - - -
    #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk   (0x1UL << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos)
    -
    -

    0x00000010

    - -
    -
    - -

    ◆ USB_OTG_DIEPEACHMSK1_ITTXFEMSK

    - -
    -
    - - - - -
    #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK   USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk
    -
    -

    IN token received when TxFIFO empty mask
    -

    - -
    -
    - -

    ◆ USB_OTG_DIEPEACHMSK1_INEPNMM_Pos

    - -
    -
    - - - - -
    #define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos   (5U)
    -
    - -
    -
    - -

    ◆ USB_OTG_DIEPEACHMSK1_INEPNMM_Msk

    - -
    -
    - - - - -
    #define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk   (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos)
    -
    -

    0x00000020

    - -
    -
    - -

    ◆ USB_OTG_DIEPEACHMSK1_INEPNMM

    - -
    -
    - - - - -
    #define USB_OTG_DIEPEACHMSK1_INEPNMM   USB_OTG_DIEPEACHMSK1_INEPNMM_Msk
    -
    -

    IN token received with EP mismatch mask
    -

    - -
    -
    - -

    ◆ USB_OTG_DIEPEACHMSK1_INEPNEM_Pos

    - -
    -
    - - - - -
    #define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos   (6U)
    -
    - -
    -
    - -

    ◆ USB_OTG_DIEPEACHMSK1_INEPNEM_Msk

    - -
    -
    - - - - -
    #define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk   (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos)
    -
    -

    0x00000040

    - -
    -
    - -

    ◆ USB_OTG_DIEPEACHMSK1_INEPNEM

    - -
    -
    - - - - -
    #define USB_OTG_DIEPEACHMSK1_INEPNEM   USB_OTG_DIEPEACHMSK1_INEPNEM_Msk
    -
    -

    IN endpoint NAK effective mask
    -

    - -
    -
    - -

    ◆ USB_OTG_DIEPEACHMSK1_TXFURM_Pos

    - -
    -
    - - - - -
    #define USB_OTG_DIEPEACHMSK1_TXFURM_Pos   (8U)
    -
    - -
    -
    - -

    ◆ USB_OTG_DIEPEACHMSK1_TXFURM_Msk

    - -
    -
    - - - - -
    #define USB_OTG_DIEPEACHMSK1_TXFURM_Msk   (0x1UL << USB_OTG_DIEPEACHMSK1_TXFURM_Pos)
    -
    -

    0x00000100

    - -
    -
    - -

    ◆ USB_OTG_DIEPEACHMSK1_TXFURM

    - -
    -
    - - - - -
    #define USB_OTG_DIEPEACHMSK1_TXFURM   USB_OTG_DIEPEACHMSK1_TXFURM_Msk
    -
    -

    FIFO underrun mask
    -

    - -
    -
    - -

    ◆ USB_OTG_DIEPEACHMSK1_BIM_Pos

    - -
    -
    - - - - -
    #define USB_OTG_DIEPEACHMSK1_BIM_Pos   (9U)
    -
    - -
    -
    - -

    ◆ USB_OTG_DIEPEACHMSK1_BIM_Msk

    - -
    -
    - - - - -
    #define USB_OTG_DIEPEACHMSK1_BIM_Msk   (0x1UL << USB_OTG_DIEPEACHMSK1_BIM_Pos)
    -
    -

    0x00000200

    - -
    -
    - -

    ◆ USB_OTG_DIEPEACHMSK1_BIM

    - -
    -
    - - - - -
    #define USB_OTG_DIEPEACHMSK1_BIM   USB_OTG_DIEPEACHMSK1_BIM_Msk
    -
    -

    BNA interrupt mask
    -

    - -
    -
    - -

    ◆ USB_OTG_DIEPEACHMSK1_NAKM_Pos

    - -
    -
    - - - - -
    #define USB_OTG_DIEPEACHMSK1_NAKM_Pos   (13U)
    -
    - -
    -
    - -

    ◆ USB_OTG_DIEPEACHMSK1_NAKM_Msk

    - -
    -
    - - - - -
    #define USB_OTG_DIEPEACHMSK1_NAKM_Msk   (0x1UL << USB_OTG_DIEPEACHMSK1_NAKM_Pos)
    -
    -

    0x00002000

    - -
    -
    - -

    ◆ USB_OTG_DIEPEACHMSK1_NAKM

    - -
    -
    - - - - -
    #define USB_OTG_DIEPEACHMSK1_NAKM   USB_OTG_DIEPEACHMSK1_NAKM_Msk
    -
    -

    NAK interrupt mask
    -

    - -
    -
    - -

    ◆ USB_OTG_HPRT_PCSTS_Pos

    - -
    -
    - - - - -
    #define USB_OTG_HPRT_PCSTS_Pos   (0U)
    -
    - -
    -
    - -

    ◆ USB_OTG_HPRT_PCSTS_Msk

    - -
    -
    - - - - -
    #define USB_OTG_HPRT_PCSTS_Msk   (0x1UL << USB_OTG_HPRT_PCSTS_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ USB_OTG_HPRT_PCSTS

    - -
    -
    - - - - -
    #define USB_OTG_HPRT_PCSTS   USB_OTG_HPRT_PCSTS_Msk
    -
    -

    Port connect status
    -

    - -
    -
    - -

    ◆ USB_OTG_HPRT_PCDET_Pos

    - -
    -
    - - - - -
    #define USB_OTG_HPRT_PCDET_Pos   (1U)
    -
    - -
    -
    - -

    ◆ USB_OTG_HPRT_PCDET_Msk

    - -
    -
    - - - - -
    #define USB_OTG_HPRT_PCDET_Msk   (0x1UL << USB_OTG_HPRT_PCDET_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ USB_OTG_HPRT_PCDET

    - -
    -
    - - - - -
    #define USB_OTG_HPRT_PCDET   USB_OTG_HPRT_PCDET_Msk
    -
    -

    Port connect detected
    -

    - -
    -
    - -

    ◆ USB_OTG_HPRT_PENA_Pos

    - -
    -
    - - - - -
    #define USB_OTG_HPRT_PENA_Pos   (2U)
    -
    - -
    -
    - -

    ◆ USB_OTG_HPRT_PENA_Msk

    - -
    -
    - - - - -
    #define USB_OTG_HPRT_PENA_Msk   (0x1UL << USB_OTG_HPRT_PENA_Pos)
    -
    -

    0x00000004

    - -
    -
    - -

    ◆ USB_OTG_HPRT_PENA

    - -
    -
    - - - - -
    #define USB_OTG_HPRT_PENA   USB_OTG_HPRT_PENA_Msk
    -
    -

    Port enable
    -

    - -
    -
    - -

    ◆ USB_OTG_HPRT_PENCHNG_Pos

    - -
    -
    - - - - -
    #define USB_OTG_HPRT_PENCHNG_Pos   (3U)
    -
    - -
    -
    - -

    ◆ USB_OTG_HPRT_PENCHNG_Msk

    - -
    -
    - - - - -
    #define USB_OTG_HPRT_PENCHNG_Msk   (0x1UL << USB_OTG_HPRT_PENCHNG_Pos)
    -
    -

    0x00000008

    - -
    -
    - -

    ◆ USB_OTG_HPRT_PENCHNG

    - -
    -
    - - - - -
    #define USB_OTG_HPRT_PENCHNG   USB_OTG_HPRT_PENCHNG_Msk
    -
    -

    Port enable/disable change

    - -
    -
    - -

    ◆ USB_OTG_HPRT_POCA_Pos

    - -
    -
    - - - - -
    #define USB_OTG_HPRT_POCA_Pos   (4U)
    -
    - -
    -
    - -

    ◆ USB_OTG_HPRT_POCA_Msk

    - -
    -
    - - - - -
    #define USB_OTG_HPRT_POCA_Msk   (0x1UL << USB_OTG_HPRT_POCA_Pos)
    -
    -

    0x00000010

    - -
    -
    - -

    ◆ USB_OTG_HPRT_POCA

    - -
    -
    - - - - -
    #define USB_OTG_HPRT_POCA   USB_OTG_HPRT_POCA_Msk
    -
    -

    Port overcurrent active
    -

    - -
    -
    - -

    ◆ USB_OTG_HPRT_POCCHNG_Pos

    - -
    -
    - - - - -
    #define USB_OTG_HPRT_POCCHNG_Pos   (5U)
    -
    - -
    -
    - -

    ◆ USB_OTG_HPRT_POCCHNG_Msk

    - -
    -
    - - - - -
    #define USB_OTG_HPRT_POCCHNG_Msk   (0x1UL << USB_OTG_HPRT_POCCHNG_Pos)
    -
    -

    0x00000020

    - -
    -
    - -

    ◆ USB_OTG_HPRT_POCCHNG

    - -
    -
    - - - - -
    #define USB_OTG_HPRT_POCCHNG   USB_OTG_HPRT_POCCHNG_Msk
    -
    -

    Port overcurrent change
    -

    - -
    -
    - -

    ◆ USB_OTG_HPRT_PRES_Pos

    - -
    -
    - - - - -
    #define USB_OTG_HPRT_PRES_Pos   (6U)
    -
    - -
    -
    - -

    ◆ USB_OTG_HPRT_PRES_Msk

    - -
    -
    - - - - -
    #define USB_OTG_HPRT_PRES_Msk   (0x1UL << USB_OTG_HPRT_PRES_Pos)
    -
    -

    0x00000040

    - -
    -
    - -

    ◆ USB_OTG_HPRT_PRES

    - -
    -
    - - - - -
    #define USB_OTG_HPRT_PRES   USB_OTG_HPRT_PRES_Msk
    -
    -

    Port resume
    -

    - -
    -
    - -

    ◆ USB_OTG_HPRT_PSUSP_Pos

    - -
    -
    - - - - -
    #define USB_OTG_HPRT_PSUSP_Pos   (7U)
    -
    - -
    -
    - -

    ◆ USB_OTG_HPRT_PSUSP_Msk

    - -
    -
    - - - - -
    #define USB_OTG_HPRT_PSUSP_Msk   (0x1UL << USB_OTG_HPRT_PSUSP_Pos)
    -
    -

    0x00000080

    - -
    -
    - -

    ◆ USB_OTG_HPRT_PSUSP

    - -
    -
    - - - - -
    #define USB_OTG_HPRT_PSUSP   USB_OTG_HPRT_PSUSP_Msk
    -
    -

    Port suspend
    -

    - -
    -
    - -

    ◆ USB_OTG_HPRT_PRST_Pos

    - -
    -
    - - - - -
    #define USB_OTG_HPRT_PRST_Pos   (8U)
    -
    - -
    -
    - -

    ◆ USB_OTG_HPRT_PRST_Msk

    - -
    -
    - - - - -
    #define USB_OTG_HPRT_PRST_Msk   (0x1UL << USB_OTG_HPRT_PRST_Pos)
    -
    -

    0x00000100

    - -
    -
    - -

    ◆ USB_OTG_HPRT_PRST

    - -
    -
    - - - - -
    #define USB_OTG_HPRT_PRST   USB_OTG_HPRT_PRST_Msk
    -
    -

    Port reset
    -

    - -
    -
    - -

    ◆ USB_OTG_HPRT_PLSTS_Pos

    - -
    -
    - - - - -
    #define USB_OTG_HPRT_PLSTS_Pos   (10U)
    -
    - -
    -
    - -

    ◆ USB_OTG_HPRT_PLSTS_Msk

    - -
    -
    - - - - -
    #define USB_OTG_HPRT_PLSTS_Msk   (0x3UL << USB_OTG_HPRT_PLSTS_Pos)
    -
    -

    0x00000C00

    - -
    -
    - -

    ◆ USB_OTG_HPRT_PLSTS

    - -
    -
    - - - - -
    #define USB_OTG_HPRT_PLSTS   USB_OTG_HPRT_PLSTS_Msk
    -
    -

    Port line status
    -

    - -
    -
    - -

    ◆ USB_OTG_HPRT_PLSTS_0

    - -
    -
    - - - - -
    #define USB_OTG_HPRT_PLSTS_0   (0x1UL << USB_OTG_HPRT_PLSTS_Pos)
    -
    -

    0x00000400

    - -
    -
    - -

    ◆ USB_OTG_HPRT_PLSTS_1

    - -
    -
    - - - - -
    #define USB_OTG_HPRT_PLSTS_1   (0x2UL << USB_OTG_HPRT_PLSTS_Pos)
    -
    -

    0x00000800

    - -
    -
    - -

    ◆ USB_OTG_HPRT_PPWR_Pos

    - -
    -
    - - - - -
    #define USB_OTG_HPRT_PPWR_Pos   (12U)
    -
    - -
    -
    - -

    ◆ USB_OTG_HPRT_PPWR_Msk

    - -
    -
    - - - - -
    #define USB_OTG_HPRT_PPWR_Msk   (0x1UL << USB_OTG_HPRT_PPWR_Pos)
    -
    -

    0x00001000

    - -
    -
    - -

    ◆ USB_OTG_HPRT_PPWR

    - -
    -
    - - - - -
    #define USB_OTG_HPRT_PPWR   USB_OTG_HPRT_PPWR_Msk
    -
    -

    Port power
    -

    - -
    -
    - -

    ◆ USB_OTG_HPRT_PTCTL_Pos

    - -
    -
    - - - - -
    #define USB_OTG_HPRT_PTCTL_Pos   (13U)
    -
    - -
    -
    - -

    ◆ USB_OTG_HPRT_PTCTL_Msk

    - -
    -
    - - - - -
    #define USB_OTG_HPRT_PTCTL_Msk   (0xFUL << USB_OTG_HPRT_PTCTL_Pos)
    -
    -

    0x0001E000

    - -
    -
    - -

    ◆ USB_OTG_HPRT_PTCTL

    - -
    -
    - - - - -
    #define USB_OTG_HPRT_PTCTL   USB_OTG_HPRT_PTCTL_Msk
    -
    -

    Port test control
    -

    - -
    -
    - -

    ◆ USB_OTG_HPRT_PTCTL_0

    - -
    -
    - - - - -
    #define USB_OTG_HPRT_PTCTL_0   (0x1UL << USB_OTG_HPRT_PTCTL_Pos)
    -
    -

    0x00002000

    - -
    -
    - -

    ◆ USB_OTG_HPRT_PTCTL_1

    - -
    -
    - - - - -
    #define USB_OTG_HPRT_PTCTL_1   (0x2UL << USB_OTG_HPRT_PTCTL_Pos)
    -
    -

    0x00004000

    - -
    -
    - -

    ◆ USB_OTG_HPRT_PTCTL_2

    - -
    -
    - - - - -
    #define USB_OTG_HPRT_PTCTL_2   (0x4UL << USB_OTG_HPRT_PTCTL_Pos)
    -
    -

    0x00008000

    - -
    -
    - -

    ◆ USB_OTG_HPRT_PTCTL_3

    - -
    -
    - - - - -
    #define USB_OTG_HPRT_PTCTL_3   (0x8UL << USB_OTG_HPRT_PTCTL_Pos)
    -
    -

    0x00010000

    - -
    -
    - -

    ◆ USB_OTG_HPRT_PSPD_Pos

    - -
    -
    - - - - -
    #define USB_OTG_HPRT_PSPD_Pos   (17U)
    -
    - -
    -
    - -

    ◆ USB_OTG_HPRT_PSPD_Msk

    - -
    -
    - - - - -
    #define USB_OTG_HPRT_PSPD_Msk   (0x3UL << USB_OTG_HPRT_PSPD_Pos)
    -
    -

    0x00060000

    - -
    -
    - -

    ◆ USB_OTG_HPRT_PSPD

    - -
    -
    - - - - -
    #define USB_OTG_HPRT_PSPD   USB_OTG_HPRT_PSPD_Msk
    -
    -

    Port speed
    -

    - -
    -
    - -

    ◆ USB_OTG_HPRT_PSPD_0

    - -
    -
    - - - - -
    #define USB_OTG_HPRT_PSPD_0   (0x1UL << USB_OTG_HPRT_PSPD_Pos)
    -
    -

    0x00020000

    - -
    -
    - -

    ◆ USB_OTG_HPRT_PSPD_1

    - -
    -
    - - - - -
    #define USB_OTG_HPRT_PSPD_1   (0x2UL << USB_OTG_HPRT_PSPD_Pos)
    -
    -

    0x00040000

    - -
    -
    - -

    ◆ USB_OTG_DOEPEACHMSK1_XFRCM_Pos

    - -
    -
    - - - - -
    #define USB_OTG_DOEPEACHMSK1_XFRCM_Pos   (0U)
    -
    - -
    -
    - -

    ◆ USB_OTG_DOEPEACHMSK1_XFRCM_Msk

    - -
    -
    - - - - -
    #define USB_OTG_DOEPEACHMSK1_XFRCM_Msk   (0x1UL << USB_OTG_DOEPEACHMSK1_XFRCM_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ USB_OTG_DOEPEACHMSK1_XFRCM

    - -
    -
    - - - - -
    #define USB_OTG_DOEPEACHMSK1_XFRCM   USB_OTG_DOEPEACHMSK1_XFRCM_Msk
    -
    -

    Transfer completed interrupt mask
    -

    - -
    -
    - -

    ◆ USB_OTG_DOEPEACHMSK1_EPDM_Pos

    - -
    -
    - - - - -
    #define USB_OTG_DOEPEACHMSK1_EPDM_Pos   (1U)
    -
    - -
    -
    - -

    ◆ USB_OTG_DOEPEACHMSK1_EPDM_Msk

    - -
    -
    - - - - -
    #define USB_OTG_DOEPEACHMSK1_EPDM_Msk   (0x1UL << USB_OTG_DOEPEACHMSK1_EPDM_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ USB_OTG_DOEPEACHMSK1_EPDM

    - -
    -
    - - - - -
    #define USB_OTG_DOEPEACHMSK1_EPDM   USB_OTG_DOEPEACHMSK1_EPDM_Msk
    -
    -

    Endpoint disabled interrupt mask
    -

    - -
    -
    - -

    ◆ USB_OTG_DOEPEACHMSK1_TOM_Pos

    - -
    -
    - - - - -
    #define USB_OTG_DOEPEACHMSK1_TOM_Pos   (3U)
    -
    - -
    -
    - -

    ◆ USB_OTG_DOEPEACHMSK1_TOM_Msk

    - -
    -
    - - - - -
    #define USB_OTG_DOEPEACHMSK1_TOM_Msk   (0x1UL << USB_OTG_DOEPEACHMSK1_TOM_Pos)
    -
    -

    0x00000008

    - -
    -
    - -

    ◆ USB_OTG_DOEPEACHMSK1_TOM

    - -
    -
    - - - - -
    #define USB_OTG_DOEPEACHMSK1_TOM   USB_OTG_DOEPEACHMSK1_TOM_Msk
    -
    -

    Timeout condition mask
    -

    - -
    -
    - -

    ◆ USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos

    - -
    -
    - - - - -
    #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos   (4U)
    -
    - -
    -
    - -

    ◆ USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk

    - -
    -
    - - - - -
    #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk   (0x1UL << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos)
    -
    -

    0x00000010

    - -
    -
    - -

    ◆ USB_OTG_DOEPEACHMSK1_ITTXFEMSK

    - -
    -
    - - - - -
    #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK   USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk
    -
    -

    IN token received when TxFIFO empty mask
    -

    - -
    -
    - -

    ◆ USB_OTG_DOEPEACHMSK1_INEPNMM_Pos

    - -
    -
    - - - - -
    #define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos   (5U)
    -
    - -
    -
    - -

    ◆ USB_OTG_DOEPEACHMSK1_INEPNMM_Msk

    - -
    -
    - - - - -
    #define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk   (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos)
    -
    -

    0x00000020

    - -
    -
    - -

    ◆ USB_OTG_DOEPEACHMSK1_INEPNMM

    - -
    -
    - - - - -
    #define USB_OTG_DOEPEACHMSK1_INEPNMM   USB_OTG_DOEPEACHMSK1_INEPNMM_Msk
    -
    -

    IN token received with EP mismatch mask
    -

    - -
    -
    - -

    ◆ USB_OTG_DOEPEACHMSK1_INEPNEM_Pos

    - -
    -
    - - - - -
    #define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos   (6U)
    -
    - -
    -
    - -

    ◆ USB_OTG_DOEPEACHMSK1_INEPNEM_Msk

    - -
    -
    - - - - -
    #define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk   (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos)
    -
    -

    0x00000040

    - -
    -
    - -

    ◆ USB_OTG_DOEPEACHMSK1_INEPNEM

    - -
    -
    - - - - -
    #define USB_OTG_DOEPEACHMSK1_INEPNEM   USB_OTG_DOEPEACHMSK1_INEPNEM_Msk
    -
    -

    IN endpoint NAK effective mask
    -

    - -
    -
    - -

    ◆ USB_OTG_DOEPEACHMSK1_TXFURM_Pos

    - -
    -
    - - - - -
    #define USB_OTG_DOEPEACHMSK1_TXFURM_Pos   (8U)
    -
    - -
    -
    - -

    ◆ USB_OTG_DOEPEACHMSK1_TXFURM_Msk

    - -
    -
    - - - - -
    #define USB_OTG_DOEPEACHMSK1_TXFURM_Msk   (0x1UL << USB_OTG_DOEPEACHMSK1_TXFURM_Pos)
    -
    -

    0x00000100

    - -
    -
    - -

    ◆ USB_OTG_DOEPEACHMSK1_TXFURM

    - -
    -
    - - - - -
    #define USB_OTG_DOEPEACHMSK1_TXFURM   USB_OTG_DOEPEACHMSK1_TXFURM_Msk
    -
    -

    OUT packet error mask
    -

    - -
    -
    - -

    ◆ USB_OTG_DOEPEACHMSK1_BIM_Pos

    - -
    -
    - - - - -
    #define USB_OTG_DOEPEACHMSK1_BIM_Pos   (9U)
    -
    - -
    -
    - -

    ◆ USB_OTG_DOEPEACHMSK1_BIM_Msk

    - -
    -
    - - - - -
    #define USB_OTG_DOEPEACHMSK1_BIM_Msk   (0x1UL << USB_OTG_DOEPEACHMSK1_BIM_Pos)
    -
    -

    0x00000200

    - -
    -
    - -

    ◆ USB_OTG_DOEPEACHMSK1_BIM

    - -
    -
    - - - - -
    #define USB_OTG_DOEPEACHMSK1_BIM   USB_OTG_DOEPEACHMSK1_BIM_Msk
    -
    -

    BNA interrupt mask
    -

    - -
    -
    - -

    ◆ USB_OTG_DOEPEACHMSK1_BERRM_Pos

    - -
    -
    - - - - -
    #define USB_OTG_DOEPEACHMSK1_BERRM_Pos   (12U)
    -
    - -
    -
    - -

    ◆ USB_OTG_DOEPEACHMSK1_BERRM_Msk

    - -
    -
    - - - - -
    #define USB_OTG_DOEPEACHMSK1_BERRM_Msk   (0x1UL << USB_OTG_DOEPEACHMSK1_BERRM_Pos)
    -
    -

    0x00001000

    - -
    -
    - -

    ◆ USB_OTG_DOEPEACHMSK1_BERRM

    - -
    -
    - - - - -
    #define USB_OTG_DOEPEACHMSK1_BERRM   USB_OTG_DOEPEACHMSK1_BERRM_Msk
    -
    -

    Bubble error interrupt mask
    -

    - -
    -
    - -

    ◆ USB_OTG_DOEPEACHMSK1_NAKM_Pos

    - -
    -
    - - - - -
    #define USB_OTG_DOEPEACHMSK1_NAKM_Pos   (13U)
    -
    - -
    -
    - -

    ◆ USB_OTG_DOEPEACHMSK1_NAKM_Msk

    - -
    -
    - - - - -
    #define USB_OTG_DOEPEACHMSK1_NAKM_Msk   (0x1UL << USB_OTG_DOEPEACHMSK1_NAKM_Pos)
    -
    -

    0x00002000

    - -
    -
    - -

    ◆ USB_OTG_DOEPEACHMSK1_NAKM

    - -
    -
    - - - - -
    #define USB_OTG_DOEPEACHMSK1_NAKM   USB_OTG_DOEPEACHMSK1_NAKM_Msk
    -
    -

    NAK interrupt mask
    -

    - -
    -
    - -

    ◆ USB_OTG_DOEPEACHMSK1_NYETM_Pos

    - -
    -
    - - - - -
    #define USB_OTG_DOEPEACHMSK1_NYETM_Pos   (14U)
    -
    - -
    -
    - -

    ◆ USB_OTG_DOEPEACHMSK1_NYETM_Msk

    - -
    -
    - - - - -
    #define USB_OTG_DOEPEACHMSK1_NYETM_Msk   (0x1UL << USB_OTG_DOEPEACHMSK1_NYETM_Pos)
    -
    -

    0x00004000

    - -
    -
    - -

    ◆ USB_OTG_DOEPEACHMSK1_NYETM

    - -
    -
    - - - - -
    #define USB_OTG_DOEPEACHMSK1_NYETM   USB_OTG_DOEPEACHMSK1_NYETM_Msk
    -
    -

    NYET interrupt mask
    -

    - -
    -
    - -

    ◆ USB_OTG_HPTXFSIZ_PTXSA_Pos

    - -
    -
    - - - - -
    #define USB_OTG_HPTXFSIZ_PTXSA_Pos   (0U)
    -
    - -
    -
    - -

    ◆ USB_OTG_HPTXFSIZ_PTXSA_Msk

    - -
    -
    - - - - -
    #define USB_OTG_HPTXFSIZ_PTXSA_Msk   (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXSA_Pos)
    -
    -

    0x0000FFFF

    - -
    -
    - -

    ◆ USB_OTG_HPTXFSIZ_PTXSA

    - -
    -
    - - - - -
    #define USB_OTG_HPTXFSIZ_PTXSA   USB_OTG_HPTXFSIZ_PTXSA_Msk
    -
    -

    Host periodic TxFIFO start address
    -

    - -
    -
    - -

    ◆ USB_OTG_HPTXFSIZ_PTXFD_Pos

    - -
    -
    - - - - -
    #define USB_OTG_HPTXFSIZ_PTXFD_Pos   (16U)
    -
    - -
    -
    - -

    ◆ USB_OTG_HPTXFSIZ_PTXFD_Msk

    - -
    -
    - - - - -
    #define USB_OTG_HPTXFSIZ_PTXFD_Msk   (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXFD_Pos)
    -
    -

    0xFFFF0000

    - -
    -
    - -

    ◆ USB_OTG_HPTXFSIZ_PTXFD

    - -
    -
    - - - - -
    #define USB_OTG_HPTXFSIZ_PTXFD   USB_OTG_HPTXFSIZ_PTXFD_Msk
    -
    -

    Host periodic TxFIFO depth
    -

    - -
    -
    - -

    ◆ USB_OTG_DIEPCTL_MPSIZ_Pos

    - -
    -
    - - - - -
    #define USB_OTG_DIEPCTL_MPSIZ_Pos   (0U)
    -
    - -
    -
    - -

    ◆ USB_OTG_DIEPCTL_MPSIZ_Msk

    - -
    -
    - - - - -
    #define USB_OTG_DIEPCTL_MPSIZ_Msk   (0x7FFUL << USB_OTG_DIEPCTL_MPSIZ_Pos)
    -
    -

    0x000007FF

    - -
    -
    - -

    ◆ USB_OTG_DIEPCTL_MPSIZ

    - -
    -
    - - - - -
    #define USB_OTG_DIEPCTL_MPSIZ   USB_OTG_DIEPCTL_MPSIZ_Msk
    -
    -

    Maximum packet size
    -

    - -
    -
    - -

    ◆ USB_OTG_DIEPCTL_USBAEP_Pos

    - -
    -
    - - - - -
    #define USB_OTG_DIEPCTL_USBAEP_Pos   (15U)
    -
    - -
    -
    - -

    ◆ USB_OTG_DIEPCTL_USBAEP_Msk

    - -
    -
    - - - - -
    #define USB_OTG_DIEPCTL_USBAEP_Msk   (0x1UL << USB_OTG_DIEPCTL_USBAEP_Pos)
    -
    -

    0x00008000

    - -
    -
    - -

    ◆ USB_OTG_DIEPCTL_USBAEP

    - -
    -
    - - - - -
    #define USB_OTG_DIEPCTL_USBAEP   USB_OTG_DIEPCTL_USBAEP_Msk
    -
    -

    USB active endpoint
    -

    - -
    -
    - -

    ◆ USB_OTG_DIEPCTL_EONUM_DPID_Pos

    - -
    -
    - - - - -
    #define USB_OTG_DIEPCTL_EONUM_DPID_Pos   (16U)
    -
    - -
    -
    - -

    ◆ USB_OTG_DIEPCTL_EONUM_DPID_Msk

    - -
    -
    - - - - -
    #define USB_OTG_DIEPCTL_EONUM_DPID_Msk   (0x1UL << USB_OTG_DIEPCTL_EONUM_DPID_Pos)
    -
    -

    0x00010000

    - -
    -
    - -

    ◆ USB_OTG_DIEPCTL_EONUM_DPID

    - -
    -
    - - - - -
    #define USB_OTG_DIEPCTL_EONUM_DPID   USB_OTG_DIEPCTL_EONUM_DPID_Msk
    -
    -

    Even/odd frame
    -

    - -
    -
    - -

    ◆ USB_OTG_DIEPCTL_NAKSTS_Pos

    - -
    -
    - - - - -
    #define USB_OTG_DIEPCTL_NAKSTS_Pos   (17U)
    -
    - -
    -
    - -

    ◆ USB_OTG_DIEPCTL_NAKSTS_Msk

    - -
    -
    - - - - -
    #define USB_OTG_DIEPCTL_NAKSTS_Msk   (0x1UL << USB_OTG_DIEPCTL_NAKSTS_Pos)
    -
    -

    0x00020000

    - -
    -
    - -

    ◆ USB_OTG_DIEPCTL_NAKSTS

    - -
    -
    - - - - -
    #define USB_OTG_DIEPCTL_NAKSTS   USB_OTG_DIEPCTL_NAKSTS_Msk
    -
    -

    NAK status
    -

    - -
    -
    - -

    ◆ USB_OTG_DIEPCTL_EPTYP_Pos

    - -
    -
    - - - - -
    #define USB_OTG_DIEPCTL_EPTYP_Pos   (18U)
    -
    - -
    -
    - -

    ◆ USB_OTG_DIEPCTL_EPTYP_Msk

    - -
    -
    - - - - -
    #define USB_OTG_DIEPCTL_EPTYP_Msk   (0x3UL << USB_OTG_DIEPCTL_EPTYP_Pos)
    -
    -

    0x000C0000

    - -
    -
    - -

    ◆ USB_OTG_DIEPCTL_EPTYP

    - -
    -
    - - - - -
    #define USB_OTG_DIEPCTL_EPTYP   USB_OTG_DIEPCTL_EPTYP_Msk
    -
    -

    Endpoint type
    -

    - -
    -
    - -

    ◆ USB_OTG_DIEPCTL_EPTYP_0

    - -
    -
    - - - - -
    #define USB_OTG_DIEPCTL_EPTYP_0   (0x1UL << USB_OTG_DIEPCTL_EPTYP_Pos)
    -
    -

    0x00040000

    - -
    -
    - -

    ◆ USB_OTG_DIEPCTL_EPTYP_1

    - -
    -
    - - - - -
    #define USB_OTG_DIEPCTL_EPTYP_1   (0x2UL << USB_OTG_DIEPCTL_EPTYP_Pos)
    -
    -

    0x00080000

    - -
    -
    - -

    ◆ USB_OTG_DIEPCTL_STALL_Pos

    - -
    -
    - - - - -
    #define USB_OTG_DIEPCTL_STALL_Pos   (21U)
    -
    - -
    -
    - -

    ◆ USB_OTG_DIEPCTL_STALL_Msk

    - -
    -
    - - - - -
    #define USB_OTG_DIEPCTL_STALL_Msk   (0x1UL << USB_OTG_DIEPCTL_STALL_Pos)
    -
    -

    0x00200000

    - -
    -
    - -

    ◆ USB_OTG_DIEPCTL_STALL

    - -
    -
    - - - - -
    #define USB_OTG_DIEPCTL_STALL   USB_OTG_DIEPCTL_STALL_Msk
    -
    -

    STALL handshake
    -

    - -
    -
    - -

    ◆ USB_OTG_DIEPCTL_TXFNUM_Pos

    - -
    -
    - - - - -
    #define USB_OTG_DIEPCTL_TXFNUM_Pos   (22U)
    -
    - -
    -
    - -

    ◆ USB_OTG_DIEPCTL_TXFNUM_Msk

    - -
    -
    - - - - -
    #define USB_OTG_DIEPCTL_TXFNUM_Msk   (0xFUL << USB_OTG_DIEPCTL_TXFNUM_Pos)
    -
    -

    0x03C00000

    - -
    -
    - -

    ◆ USB_OTG_DIEPCTL_TXFNUM

    - -
    -
    - - - - -
    #define USB_OTG_DIEPCTL_TXFNUM   USB_OTG_DIEPCTL_TXFNUM_Msk
    -
    -

    TxFIFO number
    -

    - -
    -
    - -

    ◆ USB_OTG_DIEPCTL_TXFNUM_0

    - -
    -
    - - - - -
    #define USB_OTG_DIEPCTL_TXFNUM_0   (0x1UL << USB_OTG_DIEPCTL_TXFNUM_Pos)
    -
    -

    0x00400000

    - -
    -
    - -

    ◆ USB_OTG_DIEPCTL_TXFNUM_1

    - -
    -
    - - - - -
    #define USB_OTG_DIEPCTL_TXFNUM_1   (0x2UL << USB_OTG_DIEPCTL_TXFNUM_Pos)
    -
    -

    0x00800000

    - -
    -
    - -

    ◆ USB_OTG_DIEPCTL_TXFNUM_2

    - -
    -
    - - - - -
    #define USB_OTG_DIEPCTL_TXFNUM_2   (0x4UL << USB_OTG_DIEPCTL_TXFNUM_Pos)
    -
    -

    0x01000000

    - -
    -
    - -

    ◆ USB_OTG_DIEPCTL_TXFNUM_3

    - -
    -
    - - - - -
    #define USB_OTG_DIEPCTL_TXFNUM_3   (0x8UL << USB_OTG_DIEPCTL_TXFNUM_Pos)
    -
    -

    0x02000000

    - -
    -
    - -

    ◆ USB_OTG_DIEPCTL_CNAK_Pos

    - -
    -
    - - - - -
    #define USB_OTG_DIEPCTL_CNAK_Pos   (26U)
    -
    - -
    -
    - -

    ◆ USB_OTG_DIEPCTL_CNAK_Msk

    - -
    -
    - - - - -
    #define USB_OTG_DIEPCTL_CNAK_Msk   (0x1UL << USB_OTG_DIEPCTL_CNAK_Pos)
    -
    -

    0x04000000

    - -
    -
    - -

    ◆ USB_OTG_DIEPCTL_CNAK

    - -
    -
    - - - - -
    #define USB_OTG_DIEPCTL_CNAK   USB_OTG_DIEPCTL_CNAK_Msk
    -
    -

    Clear NAK
    -

    - -
    -
    - -

    ◆ USB_OTG_DIEPCTL_SNAK_Pos

    - -
    -
    - - - - -
    #define USB_OTG_DIEPCTL_SNAK_Pos   (27U)
    -
    - -
    -
    - -

    ◆ USB_OTG_DIEPCTL_SNAK_Msk

    - -
    -
    - - - - -
    #define USB_OTG_DIEPCTL_SNAK_Msk   (0x1UL << USB_OTG_DIEPCTL_SNAK_Pos)
    -
    -

    0x08000000

    - -
    -
    - -

    ◆ USB_OTG_DIEPCTL_SNAK

    - -
    -
    - - - - -
    #define USB_OTG_DIEPCTL_SNAK   USB_OTG_DIEPCTL_SNAK_Msk
    -
    -

    Set NAK

    - -
    -
    - -

    ◆ USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos

    - -
    -
    - - - - -
    #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos   (28U)
    -
    - -
    -
    - -

    ◆ USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk

    - -
    -
    - - - - -
    #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk   (0x1UL << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos)
    -
    -

    0x10000000

    - -
    -
    - -

    ◆ USB_OTG_DIEPCTL_SD0PID_SEVNFRM

    - -
    -
    - - - - -
    #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM   USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk
    -
    -

    Set DATA0 PID
    -

    - -
    -
    - -

    ◆ USB_OTG_DIEPCTL_SODDFRM_Pos

    - -
    -
    - - - - -
    #define USB_OTG_DIEPCTL_SODDFRM_Pos   (29U)
    -
    - -
    -
    - -

    ◆ USB_OTG_DIEPCTL_SODDFRM_Msk

    - -
    -
    - - - - -
    #define USB_OTG_DIEPCTL_SODDFRM_Msk   (0x1UL << USB_OTG_DIEPCTL_SODDFRM_Pos)
    -
    -

    0x20000000

    - -
    -
    - -

    ◆ USB_OTG_DIEPCTL_SODDFRM

    - -
    -
    - - - - -
    #define USB_OTG_DIEPCTL_SODDFRM   USB_OTG_DIEPCTL_SODDFRM_Msk
    -
    -

    Set odd frame
    -

    - -
    -
    - -

    ◆ USB_OTG_DIEPCTL_EPDIS_Pos

    - -
    -
    - - - - -
    #define USB_OTG_DIEPCTL_EPDIS_Pos   (30U)
    -
    - -
    -
    - -

    ◆ USB_OTG_DIEPCTL_EPDIS_Msk

    - -
    -
    - - - - -
    #define USB_OTG_DIEPCTL_EPDIS_Msk   (0x1UL << USB_OTG_DIEPCTL_EPDIS_Pos)
    -
    -

    0x40000000

    - -
    -
    - -

    ◆ USB_OTG_DIEPCTL_EPDIS

    - -
    -
    - - - - -
    #define USB_OTG_DIEPCTL_EPDIS   USB_OTG_DIEPCTL_EPDIS_Msk
    -
    -

    Endpoint disable
    -

    - -
    -
    - -

    ◆ USB_OTG_DIEPCTL_EPENA_Pos

    - -
    -
    - - - - -
    #define USB_OTG_DIEPCTL_EPENA_Pos   (31U)
    -
    - -
    -
    - -

    ◆ USB_OTG_DIEPCTL_EPENA_Msk

    - -
    -
    - - - - -
    #define USB_OTG_DIEPCTL_EPENA_Msk   (0x1UL << USB_OTG_DIEPCTL_EPENA_Pos)
    -
    -

    0x80000000

    - -
    -
    - -

    ◆ USB_OTG_DIEPCTL_EPENA

    - -
    -
    - - - - -
    #define USB_OTG_DIEPCTL_EPENA   USB_OTG_DIEPCTL_EPENA_Msk
    -
    -

    Endpoint enable
    -

    - -
    -
    - -

    ◆ USB_OTG_HCCHAR_MPSIZ_Pos

    - -
    -
    - - - - -
    #define USB_OTG_HCCHAR_MPSIZ_Pos   (0U)
    -
    - -
    -
    - -

    ◆ USB_OTG_HCCHAR_MPSIZ_Msk

    - -
    -
    - - - - -
    #define USB_OTG_HCCHAR_MPSIZ_Msk   (0x7FFUL << USB_OTG_HCCHAR_MPSIZ_Pos)
    -
    -

    0x000007FF

    - -
    -
    - -

    ◆ USB_OTG_HCCHAR_MPSIZ

    - -
    -
    - - - - -
    #define USB_OTG_HCCHAR_MPSIZ   USB_OTG_HCCHAR_MPSIZ_Msk
    -
    -

    Maximum packet size

    - -
    -
    - -

    ◆ USB_OTG_HCCHAR_EPNUM_Pos

    - -
    -
    - - - - -
    #define USB_OTG_HCCHAR_EPNUM_Pos   (11U)
    -
    - -
    -
    - -

    ◆ USB_OTG_HCCHAR_EPNUM_Msk

    - -
    -
    - - - - -
    #define USB_OTG_HCCHAR_EPNUM_Msk   (0xFUL << USB_OTG_HCCHAR_EPNUM_Pos)
    -
    -

    0x00007800

    - -
    -
    - -

    ◆ USB_OTG_HCCHAR_EPNUM

    - -
    -
    - - - - -
    #define USB_OTG_HCCHAR_EPNUM   USB_OTG_HCCHAR_EPNUM_Msk
    -
    -

    Endpoint number

    - -
    -
    - -

    ◆ USB_OTG_HCCHAR_EPNUM_0

    - -
    -
    - - - - -
    #define USB_OTG_HCCHAR_EPNUM_0   (0x1UL << USB_OTG_HCCHAR_EPNUM_Pos)
    -
    -

    0x00000800

    - -
    -
    - -

    ◆ USB_OTG_HCCHAR_EPNUM_1

    - -
    -
    - - - - -
    #define USB_OTG_HCCHAR_EPNUM_1   (0x2UL << USB_OTG_HCCHAR_EPNUM_Pos)
    -
    -

    0x00001000

    - -
    -
    - -

    ◆ USB_OTG_HCCHAR_EPNUM_2

    - -
    -
    - - - - -
    #define USB_OTG_HCCHAR_EPNUM_2   (0x4UL << USB_OTG_HCCHAR_EPNUM_Pos)
    -
    -

    0x00002000

    - -
    -
    - -

    ◆ USB_OTG_HCCHAR_EPNUM_3

    - -
    -
    - - - - -
    #define USB_OTG_HCCHAR_EPNUM_3   (0x8UL << USB_OTG_HCCHAR_EPNUM_Pos)
    -
    -

    0x00004000

    - -
    -
    - -

    ◆ USB_OTG_HCCHAR_EPDIR_Pos

    - -
    -
    - - - - -
    #define USB_OTG_HCCHAR_EPDIR_Pos   (15U)
    -
    - -
    -
    - -

    ◆ USB_OTG_HCCHAR_EPDIR_Msk

    - -
    -
    - - - - -
    #define USB_OTG_HCCHAR_EPDIR_Msk   (0x1UL << USB_OTG_HCCHAR_EPDIR_Pos)
    -
    -

    0x00008000

    - -
    -
    - -

    ◆ USB_OTG_HCCHAR_EPDIR

    - -
    -
    - - - - -
    #define USB_OTG_HCCHAR_EPDIR   USB_OTG_HCCHAR_EPDIR_Msk
    -
    -

    Endpoint direction

    - -
    -
    - -

    ◆ USB_OTG_HCCHAR_LSDEV_Pos

    - -
    -
    - - - - -
    #define USB_OTG_HCCHAR_LSDEV_Pos   (17U)
    -
    - -
    -
    - -

    ◆ USB_OTG_HCCHAR_LSDEV_Msk

    - -
    -
    - - - - -
    #define USB_OTG_HCCHAR_LSDEV_Msk   (0x1UL << USB_OTG_HCCHAR_LSDEV_Pos)
    -
    -

    0x00020000

    - -
    -
    - -

    ◆ USB_OTG_HCCHAR_LSDEV

    - -
    -
    - - - - -
    #define USB_OTG_HCCHAR_LSDEV   USB_OTG_HCCHAR_LSDEV_Msk
    -
    -

    Low-speed device

    - -
    -
    - -

    ◆ USB_OTG_HCCHAR_EPTYP_Pos

    - -
    -
    - - - - -
    #define USB_OTG_HCCHAR_EPTYP_Pos   (18U)
    -
    - -
    -
    - -

    ◆ USB_OTG_HCCHAR_EPTYP_Msk

    - -
    -
    - - - - -
    #define USB_OTG_HCCHAR_EPTYP_Msk   (0x3UL << USB_OTG_HCCHAR_EPTYP_Pos)
    -
    -

    0x000C0000

    - -
    -
    - -

    ◆ USB_OTG_HCCHAR_EPTYP

    - -
    -
    - - - - -
    #define USB_OTG_HCCHAR_EPTYP   USB_OTG_HCCHAR_EPTYP_Msk
    -
    -

    Endpoint type

    - -
    -
    - -

    ◆ USB_OTG_HCCHAR_EPTYP_0

    - -
    -
    - - - - -
    #define USB_OTG_HCCHAR_EPTYP_0   (0x1UL << USB_OTG_HCCHAR_EPTYP_Pos)
    -
    -

    0x00040000

    - -
    -
    - -

    ◆ USB_OTG_HCCHAR_EPTYP_1

    - -
    -
    - - - - -
    #define USB_OTG_HCCHAR_EPTYP_1   (0x2UL << USB_OTG_HCCHAR_EPTYP_Pos)
    -
    -

    0x00080000

    - -
    -
    - -

    ◆ USB_OTG_HCCHAR_MC_Pos

    - -
    -
    - - - - -
    #define USB_OTG_HCCHAR_MC_Pos   (20U)
    -
    - -
    -
    - -

    ◆ USB_OTG_HCCHAR_MC_Msk

    - -
    -
    - - - - -
    #define USB_OTG_HCCHAR_MC_Msk   (0x3UL << USB_OTG_HCCHAR_MC_Pos)
    -
    -

    0x00300000

    - -
    -
    - -

    ◆ USB_OTG_HCCHAR_MC

    - -
    -
    - - - - -
    #define USB_OTG_HCCHAR_MC   USB_OTG_HCCHAR_MC_Msk
    -
    -

    Multi Count (MC) / Error Count (EC)

    - -
    -
    - -

    ◆ USB_OTG_HCCHAR_MC_0

    - -
    -
    - - - - -
    #define USB_OTG_HCCHAR_MC_0   (0x1UL << USB_OTG_HCCHAR_MC_Pos)
    -
    -

    0x00100000

    - -
    -
    - -

    ◆ USB_OTG_HCCHAR_MC_1

    - -
    -
    - - - - -
    #define USB_OTG_HCCHAR_MC_1   (0x2UL << USB_OTG_HCCHAR_MC_Pos)
    -
    -

    0x00200000

    - -
    -
    - -

    ◆ USB_OTG_HCCHAR_DAD_Pos

    - -
    -
    - - - - -
    #define USB_OTG_HCCHAR_DAD_Pos   (22U)
    -
    - -
    -
    - -

    ◆ USB_OTG_HCCHAR_DAD_Msk

    - -
    -
    - - - - -
    #define USB_OTG_HCCHAR_DAD_Msk   (0x7FUL << USB_OTG_HCCHAR_DAD_Pos)
    -
    -

    0x1FC00000

    - -
    -
    - -

    ◆ USB_OTG_HCCHAR_DAD

    - -
    -
    - - - - -
    #define USB_OTG_HCCHAR_DAD   USB_OTG_HCCHAR_DAD_Msk
    -
    -

    Device address

    - -
    -
    - -

    ◆ USB_OTG_HCCHAR_DAD_0

    - -
    -
    - - - - -
    #define USB_OTG_HCCHAR_DAD_0   (0x01UL << USB_OTG_HCCHAR_DAD_Pos)
    -
    -

    0x00400000

    - -
    -
    - -

    ◆ USB_OTG_HCCHAR_DAD_1

    - -
    -
    - - - - -
    #define USB_OTG_HCCHAR_DAD_1   (0x02UL << USB_OTG_HCCHAR_DAD_Pos)
    -
    -

    0x00800000

    - -
    -
    - -

    ◆ USB_OTG_HCCHAR_DAD_2

    - -
    -
    - - - - -
    #define USB_OTG_HCCHAR_DAD_2   (0x04UL << USB_OTG_HCCHAR_DAD_Pos)
    -
    -

    0x01000000

    - -
    -
    - -

    ◆ USB_OTG_HCCHAR_DAD_3

    - -
    -
    - - - - -
    #define USB_OTG_HCCHAR_DAD_3   (0x08UL << USB_OTG_HCCHAR_DAD_Pos)
    -
    -

    0x02000000

    - -
    -
    - -

    ◆ USB_OTG_HCCHAR_DAD_4

    - -
    -
    - - - - -
    #define USB_OTG_HCCHAR_DAD_4   (0x10UL << USB_OTG_HCCHAR_DAD_Pos)
    -
    -

    0x04000000

    - -
    -
    - -

    ◆ USB_OTG_HCCHAR_DAD_5

    - -
    -
    - - - - -
    #define USB_OTG_HCCHAR_DAD_5   (0x20UL << USB_OTG_HCCHAR_DAD_Pos)
    -
    -

    0x08000000

    - -
    -
    - -

    ◆ USB_OTG_HCCHAR_DAD_6

    - -
    -
    - - - - -
    #define USB_OTG_HCCHAR_DAD_6   (0x40UL << USB_OTG_HCCHAR_DAD_Pos)
    -
    -

    0x10000000

    - -
    -
    - -

    ◆ USB_OTG_HCCHAR_ODDFRM_Pos

    - -
    -
    - - - - -
    #define USB_OTG_HCCHAR_ODDFRM_Pos   (29U)
    -
    - -
    -
    - -

    ◆ USB_OTG_HCCHAR_ODDFRM_Msk

    - -
    -
    - - - - -
    #define USB_OTG_HCCHAR_ODDFRM_Msk   (0x1UL << USB_OTG_HCCHAR_ODDFRM_Pos)
    -
    -

    0x20000000

    - -
    -
    - -

    ◆ USB_OTG_HCCHAR_ODDFRM

    - -
    -
    - - - - -
    #define USB_OTG_HCCHAR_ODDFRM   USB_OTG_HCCHAR_ODDFRM_Msk
    -
    -

    Odd frame

    - -
    -
    - -

    ◆ USB_OTG_HCCHAR_CHDIS_Pos

    - -
    -
    - - - - -
    #define USB_OTG_HCCHAR_CHDIS_Pos   (30U)
    -
    - -
    -
    - -

    ◆ USB_OTG_HCCHAR_CHDIS_Msk

    - -
    -
    - - - - -
    #define USB_OTG_HCCHAR_CHDIS_Msk   (0x1UL << USB_OTG_HCCHAR_CHDIS_Pos)
    -
    -

    0x40000000

    - -
    -
    - -

    ◆ USB_OTG_HCCHAR_CHDIS

    - -
    -
    - - - - -
    #define USB_OTG_HCCHAR_CHDIS   USB_OTG_HCCHAR_CHDIS_Msk
    -
    -

    Channel disable

    - -
    -
    - -

    ◆ USB_OTG_HCCHAR_CHENA_Pos

    - -
    -
    - - - - -
    #define USB_OTG_HCCHAR_CHENA_Pos   (31U)
    -
    - -
    -
    - -

    ◆ USB_OTG_HCCHAR_CHENA_Msk

    - -
    -
    - - - - -
    #define USB_OTG_HCCHAR_CHENA_Msk   (0x1UL << USB_OTG_HCCHAR_CHENA_Pos)
    -
    -

    0x80000000

    - -
    -
    - -

    ◆ USB_OTG_HCCHAR_CHENA

    - -
    -
    - - - - -
    #define USB_OTG_HCCHAR_CHENA   USB_OTG_HCCHAR_CHENA_Msk
    -
    -

    Channel enable

    - -
    -
    - -

    ◆ USB_OTG_HCSPLT_PRTADDR_Pos

    - -
    -
    - - - - -
    #define USB_OTG_HCSPLT_PRTADDR_Pos   (0U)
    -
    - -
    -
    - -

    ◆ USB_OTG_HCSPLT_PRTADDR_Msk

    - -
    -
    - - - - -
    #define USB_OTG_HCSPLT_PRTADDR_Msk   (0x7FUL << USB_OTG_HCSPLT_PRTADDR_Pos)
    -
    -

    0x0000007F

    - -
    -
    - -

    ◆ USB_OTG_HCSPLT_PRTADDR

    - -
    -
    - - - - -
    #define USB_OTG_HCSPLT_PRTADDR   USB_OTG_HCSPLT_PRTADDR_Msk
    -
    -

    Port address

    - -
    -
    - -

    ◆ USB_OTG_HCSPLT_PRTADDR_0

    - -
    -
    - - - - -
    #define USB_OTG_HCSPLT_PRTADDR_0   (0x01UL << USB_OTG_HCSPLT_PRTADDR_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ USB_OTG_HCSPLT_PRTADDR_1

    - -
    -
    - - - - -
    #define USB_OTG_HCSPLT_PRTADDR_1   (0x02UL << USB_OTG_HCSPLT_PRTADDR_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ USB_OTG_HCSPLT_PRTADDR_2

    - -
    -
    - - - - -
    #define USB_OTG_HCSPLT_PRTADDR_2   (0x04UL << USB_OTG_HCSPLT_PRTADDR_Pos)
    -
    -

    0x00000004

    - -
    -
    - -

    ◆ USB_OTG_HCSPLT_PRTADDR_3

    - -
    -
    - - - - -
    #define USB_OTG_HCSPLT_PRTADDR_3   (0x08UL << USB_OTG_HCSPLT_PRTADDR_Pos)
    -
    -

    0x00000008

    - -
    -
    - -

    ◆ USB_OTG_HCSPLT_PRTADDR_4

    - -
    -
    - - - - -
    #define USB_OTG_HCSPLT_PRTADDR_4   (0x10UL << USB_OTG_HCSPLT_PRTADDR_Pos)
    -
    -

    0x00000010

    - -
    -
    - -

    ◆ USB_OTG_HCSPLT_PRTADDR_5

    - -
    -
    - - - - -
    #define USB_OTG_HCSPLT_PRTADDR_5   (0x20UL << USB_OTG_HCSPLT_PRTADDR_Pos)
    -
    -

    0x00000020

    - -
    -
    - -

    ◆ USB_OTG_HCSPLT_PRTADDR_6

    - -
    -
    - - - - -
    #define USB_OTG_HCSPLT_PRTADDR_6   (0x40UL << USB_OTG_HCSPLT_PRTADDR_Pos)
    -
    -

    0x00000040

    - -
    -
    - -

    ◆ USB_OTG_HCSPLT_HUBADDR_Pos

    - -
    -
    - - - - -
    #define USB_OTG_HCSPLT_HUBADDR_Pos   (7U)
    -
    - -
    -
    - -

    ◆ USB_OTG_HCSPLT_HUBADDR_Msk

    - -
    -
    - - - - -
    #define USB_OTG_HCSPLT_HUBADDR_Msk   (0x7FUL << USB_OTG_HCSPLT_HUBADDR_Pos)
    -
    -

    0x00003F80

    - -
    -
    - -

    ◆ USB_OTG_HCSPLT_HUBADDR

    - -
    -
    - - - - -
    #define USB_OTG_HCSPLT_HUBADDR   USB_OTG_HCSPLT_HUBADDR_Msk
    -
    -

    Hub address

    - -
    -
    - -

    ◆ USB_OTG_HCSPLT_HUBADDR_0

    - -
    -
    - - - - -
    #define USB_OTG_HCSPLT_HUBADDR_0   (0x01UL << USB_OTG_HCSPLT_HUBADDR_Pos)
    -
    -

    0x00000080

    - -
    -
    - -

    ◆ USB_OTG_HCSPLT_HUBADDR_1

    - -
    -
    - - - - -
    #define USB_OTG_HCSPLT_HUBADDR_1   (0x02UL << USB_OTG_HCSPLT_HUBADDR_Pos)
    -
    -

    0x00000100

    - -
    -
    - -

    ◆ USB_OTG_HCSPLT_HUBADDR_2

    - -
    -
    - - - - -
    #define USB_OTG_HCSPLT_HUBADDR_2   (0x04UL << USB_OTG_HCSPLT_HUBADDR_Pos)
    -
    -

    0x00000200

    - -
    -
    - -

    ◆ USB_OTG_HCSPLT_HUBADDR_3

    - -
    -
    - - - - -
    #define USB_OTG_HCSPLT_HUBADDR_3   (0x08UL << USB_OTG_HCSPLT_HUBADDR_Pos)
    -
    -

    0x00000400

    - -
    -
    - -

    ◆ USB_OTG_HCSPLT_HUBADDR_4

    - -
    -
    - - - - -
    #define USB_OTG_HCSPLT_HUBADDR_4   (0x10UL << USB_OTG_HCSPLT_HUBADDR_Pos)
    -
    -

    0x00000800

    - -
    -
    - -

    ◆ USB_OTG_HCSPLT_HUBADDR_5

    - -
    -
    - - - - -
    #define USB_OTG_HCSPLT_HUBADDR_5   (0x20UL << USB_OTG_HCSPLT_HUBADDR_Pos)
    -
    -

    0x00001000

    - -
    -
    - -

    ◆ USB_OTG_HCSPLT_HUBADDR_6

    - -
    -
    - - - - -
    #define USB_OTG_HCSPLT_HUBADDR_6   (0x40UL << USB_OTG_HCSPLT_HUBADDR_Pos)
    -
    -

    0x00002000

    - -
    -
    - -

    ◆ USB_OTG_HCSPLT_XACTPOS_Pos

    - -
    -
    - - - - -
    #define USB_OTG_HCSPLT_XACTPOS_Pos   (14U)
    -
    - -
    -
    - -

    ◆ USB_OTG_HCSPLT_XACTPOS_Msk

    - -
    -
    - - - - -
    #define USB_OTG_HCSPLT_XACTPOS_Msk   (0x3UL << USB_OTG_HCSPLT_XACTPOS_Pos)
    -
    -

    0x0000C000

    - -
    -
    - -

    ◆ USB_OTG_HCSPLT_XACTPOS

    - -
    -
    - - - - -
    #define USB_OTG_HCSPLT_XACTPOS   USB_OTG_HCSPLT_XACTPOS_Msk
    -
    -

    XACTPOS

    - -
    -
    - -

    ◆ USB_OTG_HCSPLT_XACTPOS_0

    - -
    -
    - - - - -
    #define USB_OTG_HCSPLT_XACTPOS_0   (0x1UL << USB_OTG_HCSPLT_XACTPOS_Pos)
    -
    -

    0x00004000

    - -
    -
    - -

    ◆ USB_OTG_HCSPLT_XACTPOS_1

    - -
    -
    - - - - -
    #define USB_OTG_HCSPLT_XACTPOS_1   (0x2UL << USB_OTG_HCSPLT_XACTPOS_Pos)
    -
    -

    0x00008000

    - -
    -
    - -

    ◆ USB_OTG_HCSPLT_COMPLSPLT_Pos

    - -
    -
    - - - - -
    #define USB_OTG_HCSPLT_COMPLSPLT_Pos   (16U)
    -
    - -
    -
    - -

    ◆ USB_OTG_HCSPLT_COMPLSPLT_Msk

    - -
    -
    - - - - -
    #define USB_OTG_HCSPLT_COMPLSPLT_Msk   (0x1UL << USB_OTG_HCSPLT_COMPLSPLT_Pos)
    -
    -

    0x00010000

    - -
    -
    - -

    ◆ USB_OTG_HCSPLT_COMPLSPLT

    - -
    -
    - - - - -
    #define USB_OTG_HCSPLT_COMPLSPLT   USB_OTG_HCSPLT_COMPLSPLT_Msk
    -
    -

    Do complete split

    - -
    -
    - -

    ◆ USB_OTG_HCSPLT_SPLITEN_Pos

    - -
    -
    - - - - -
    #define USB_OTG_HCSPLT_SPLITEN_Pos   (31U)
    -
    - -
    -
    - -

    ◆ USB_OTG_HCSPLT_SPLITEN_Msk

    - -
    -
    - - - - -
    #define USB_OTG_HCSPLT_SPLITEN_Msk   (0x1UL << USB_OTG_HCSPLT_SPLITEN_Pos)
    -
    -

    0x80000000

    - -
    -
    - -

    ◆ USB_OTG_HCSPLT_SPLITEN

    - -
    -
    - - - - -
    #define USB_OTG_HCSPLT_SPLITEN   USB_OTG_HCSPLT_SPLITEN_Msk
    -
    -

    Split enable

    - -
    -
    - -

    ◆ USB_OTG_HCINT_XFRC_Pos

    - -
    -
    - - - - -
    #define USB_OTG_HCINT_XFRC_Pos   (0U)
    -
    - -
    -
    - -

    ◆ USB_OTG_HCINT_XFRC_Msk

    - -
    -
    - - - - -
    #define USB_OTG_HCINT_XFRC_Msk   (0x1UL << USB_OTG_HCINT_XFRC_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ USB_OTG_HCINT_XFRC

    - -
    -
    - - - - -
    #define USB_OTG_HCINT_XFRC   USB_OTG_HCINT_XFRC_Msk
    -
    -

    Transfer completed

    - -
    -
    - -

    ◆ USB_OTG_HCINT_CHH_Pos

    - -
    -
    - - - - -
    #define USB_OTG_HCINT_CHH_Pos   (1U)
    -
    - -
    -
    - -

    ◆ USB_OTG_HCINT_CHH_Msk

    - -
    -
    - - - - -
    #define USB_OTG_HCINT_CHH_Msk   (0x1UL << USB_OTG_HCINT_CHH_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ USB_OTG_HCINT_CHH

    - -
    -
    - - - - -
    #define USB_OTG_HCINT_CHH   USB_OTG_HCINT_CHH_Msk
    -
    -

    Channel halted

    - -
    -
    - -

    ◆ USB_OTG_HCINT_AHBERR_Pos

    - -
    -
    - - - - -
    #define USB_OTG_HCINT_AHBERR_Pos   (2U)
    -
    - -
    -
    - -

    ◆ USB_OTG_HCINT_AHBERR_Msk

    - -
    -
    - - - - -
    #define USB_OTG_HCINT_AHBERR_Msk   (0x1UL << USB_OTG_HCINT_AHBERR_Pos)
    -
    -

    0x00000004

    - -
    -
    - -

    ◆ USB_OTG_HCINT_AHBERR

    - -
    -
    - - - - -
    #define USB_OTG_HCINT_AHBERR   USB_OTG_HCINT_AHBERR_Msk
    -
    -

    AHB error

    - -
    -
    - -

    ◆ USB_OTG_HCINT_STALL_Pos

    - -
    -
    - - - - -
    #define USB_OTG_HCINT_STALL_Pos   (3U)
    -
    - -
    -
    - -

    ◆ USB_OTG_HCINT_STALL_Msk

    - -
    -
    - - - - -
    #define USB_OTG_HCINT_STALL_Msk   (0x1UL << USB_OTG_HCINT_STALL_Pos)
    -
    -

    0x00000008

    - -
    -
    - -

    ◆ USB_OTG_HCINT_STALL

    - -
    -
    - - - - -
    #define USB_OTG_HCINT_STALL   USB_OTG_HCINT_STALL_Msk
    -
    -

    STALL response received interrupt

    - -
    -
    - -

    ◆ USB_OTG_HCINT_NAK_Pos

    - -
    -
    - - - - -
    #define USB_OTG_HCINT_NAK_Pos   (4U)
    -
    - -
    -
    - -

    ◆ USB_OTG_HCINT_NAK_Msk

    - -
    -
    - - - - -
    #define USB_OTG_HCINT_NAK_Msk   (0x1UL << USB_OTG_HCINT_NAK_Pos)
    -
    -

    0x00000010

    - -
    -
    - -

    ◆ USB_OTG_HCINT_NAK

    - -
    -
    - - - - -
    #define USB_OTG_HCINT_NAK   USB_OTG_HCINT_NAK_Msk
    -
    -

    NAK response received interrupt

    - -
    -
    - -

    ◆ USB_OTG_HCINT_ACK_Pos

    - -
    -
    - - - - -
    #define USB_OTG_HCINT_ACK_Pos   (5U)
    -
    - -
    -
    - -

    ◆ USB_OTG_HCINT_ACK_Msk

    - -
    -
    - - - - -
    #define USB_OTG_HCINT_ACK_Msk   (0x1UL << USB_OTG_HCINT_ACK_Pos)
    -
    -

    0x00000020

    - -
    -
    - -

    ◆ USB_OTG_HCINT_ACK

    - -
    -
    - - - - -
    #define USB_OTG_HCINT_ACK   USB_OTG_HCINT_ACK_Msk
    -
    -

    ACK response received/transmitted interrupt

    - -
    -
    - -

    ◆ USB_OTG_HCINT_NYET_Pos

    - -
    -
    - - - - -
    #define USB_OTG_HCINT_NYET_Pos   (6U)
    -
    - -
    -
    - -

    ◆ USB_OTG_HCINT_NYET_Msk

    - -
    -
    - - - - -
    #define USB_OTG_HCINT_NYET_Msk   (0x1UL << USB_OTG_HCINT_NYET_Pos)
    -
    -

    0x00000040

    - -
    -
    - -

    ◆ USB_OTG_HCINT_NYET

    - -
    -
    - - - - -
    #define USB_OTG_HCINT_NYET   USB_OTG_HCINT_NYET_Msk
    -
    -

    Response received interrupt

    - -
    -
    - -

    ◆ USB_OTG_HCINT_TXERR_Pos

    - -
    -
    - - - - -
    #define USB_OTG_HCINT_TXERR_Pos   (7U)
    -
    - -
    -
    - -

    ◆ USB_OTG_HCINT_TXERR_Msk

    - -
    -
    - - - - -
    #define USB_OTG_HCINT_TXERR_Msk   (0x1UL << USB_OTG_HCINT_TXERR_Pos)
    -
    -

    0x00000080

    - -
    -
    - -

    ◆ USB_OTG_HCINT_TXERR

    - -
    -
    - - - - -
    #define USB_OTG_HCINT_TXERR   USB_OTG_HCINT_TXERR_Msk
    -
    -

    Transaction error

    - -
    -
    - -

    ◆ USB_OTG_HCINT_BBERR_Pos

    - -
    -
    - - - - -
    #define USB_OTG_HCINT_BBERR_Pos   (8U)
    -
    - -
    -
    - -

    ◆ USB_OTG_HCINT_BBERR_Msk

    - -
    -
    - - - - -
    #define USB_OTG_HCINT_BBERR_Msk   (0x1UL << USB_OTG_HCINT_BBERR_Pos)
    -
    -

    0x00000100

    - -
    -
    - -

    ◆ USB_OTG_HCINT_BBERR

    - -
    -
    - - - - -
    #define USB_OTG_HCINT_BBERR   USB_OTG_HCINT_BBERR_Msk
    -
    -

    Babble error

    - -
    -
    - -

    ◆ USB_OTG_HCINT_FRMOR_Pos

    - -
    -
    - - - - -
    #define USB_OTG_HCINT_FRMOR_Pos   (9U)
    -
    - -
    -
    - -

    ◆ USB_OTG_HCINT_FRMOR_Msk

    - -
    -
    - - - - -
    #define USB_OTG_HCINT_FRMOR_Msk   (0x1UL << USB_OTG_HCINT_FRMOR_Pos)
    -
    -

    0x00000200

    - -
    -
    - -

    ◆ USB_OTG_HCINT_FRMOR

    - -
    -
    - - - - -
    #define USB_OTG_HCINT_FRMOR   USB_OTG_HCINT_FRMOR_Msk
    -
    -

    Frame overrun

    - -
    -
    - -

    ◆ USB_OTG_HCINT_DTERR_Pos

    - -
    -
    - - - - -
    #define USB_OTG_HCINT_DTERR_Pos   (10U)
    -
    - -
    -
    - -

    ◆ USB_OTG_HCINT_DTERR_Msk

    - -
    -
    - - - - -
    #define USB_OTG_HCINT_DTERR_Msk   (0x1UL << USB_OTG_HCINT_DTERR_Pos)
    -
    -

    0x00000400

    - -
    -
    - -

    ◆ USB_OTG_HCINT_DTERR

    - -
    -
    - - - - -
    #define USB_OTG_HCINT_DTERR   USB_OTG_HCINT_DTERR_Msk
    -
    -

    Data toggle error

    - -
    -
    - -

    ◆ USB_OTG_DIEPINT_XFRC_Pos

    - -
    -
    - - - - -
    #define USB_OTG_DIEPINT_XFRC_Pos   (0U)
    -
    - -
    -
    - -

    ◆ USB_OTG_DIEPINT_XFRC_Msk

    - -
    -
    - - - - -
    #define USB_OTG_DIEPINT_XFRC_Msk   (0x1UL << USB_OTG_DIEPINT_XFRC_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ USB_OTG_DIEPINT_XFRC

    - -
    -
    - - - - -
    #define USB_OTG_DIEPINT_XFRC   USB_OTG_DIEPINT_XFRC_Msk
    -
    -

    Transfer completed interrupt

    - -
    -
    - -

    ◆ USB_OTG_DIEPINT_EPDISD_Pos

    - -
    -
    - - - - -
    #define USB_OTG_DIEPINT_EPDISD_Pos   (1U)
    -
    - -
    -
    - -

    ◆ USB_OTG_DIEPINT_EPDISD_Msk

    - -
    -
    - - - - -
    #define USB_OTG_DIEPINT_EPDISD_Msk   (0x1UL << USB_OTG_DIEPINT_EPDISD_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ USB_OTG_DIEPINT_EPDISD

    - -
    -
    - - - - -
    #define USB_OTG_DIEPINT_EPDISD   USB_OTG_DIEPINT_EPDISD_Msk
    -
    -

    Endpoint disabled interrupt

    - -
    -
    - -

    ◆ USB_OTG_DIEPINT_AHBERR_Pos

    - -
    -
    - - - - -
    #define USB_OTG_DIEPINT_AHBERR_Pos   (2U)
    -
    - -
    -
    - -

    ◆ USB_OTG_DIEPINT_AHBERR_Msk

    - -
    -
    - - - - -
    #define USB_OTG_DIEPINT_AHBERR_Msk   (0x1UL << USB_OTG_DIEPINT_AHBERR_Pos)
    -
    -

    0x00000004

    - -
    -
    - -

    ◆ USB_OTG_DIEPINT_AHBERR

    - -
    -
    - - - - -
    #define USB_OTG_DIEPINT_AHBERR   USB_OTG_DIEPINT_AHBERR_Msk
    -
    -

    AHB Error (AHBErr) during an IN transaction

    - -
    -
    - -

    ◆ USB_OTG_DIEPINT_TOC_Pos

    - -
    -
    - - - - -
    #define USB_OTG_DIEPINT_TOC_Pos   (3U)
    -
    - -
    -
    - -

    ◆ USB_OTG_DIEPINT_TOC_Msk

    - -
    -
    - - - - -
    #define USB_OTG_DIEPINT_TOC_Msk   (0x1UL << USB_OTG_DIEPINT_TOC_Pos)
    -
    -

    0x00000008

    - -
    -
    - -

    ◆ USB_OTG_DIEPINT_TOC

    - -
    -
    - - - - -
    #define USB_OTG_DIEPINT_TOC   USB_OTG_DIEPINT_TOC_Msk
    -
    -

    Timeout condition

    - -
    -
    - -

    ◆ USB_OTG_DIEPINT_ITTXFE_Pos

    - -
    -
    - - - - -
    #define USB_OTG_DIEPINT_ITTXFE_Pos   (4U)
    -
    - -
    -
    - -

    ◆ USB_OTG_DIEPINT_ITTXFE_Msk

    - -
    -
    - - - - -
    #define USB_OTG_DIEPINT_ITTXFE_Msk   (0x1UL << USB_OTG_DIEPINT_ITTXFE_Pos)
    -
    -

    0x00000010

    - -
    -
    - -

    ◆ USB_OTG_DIEPINT_ITTXFE

    - -
    -
    - - - - -
    #define USB_OTG_DIEPINT_ITTXFE   USB_OTG_DIEPINT_ITTXFE_Msk
    -
    -

    IN token received when TxFIFO is empty

    - -
    -
    - -

    ◆ USB_OTG_DIEPINT_INEPNM_Pos

    - -
    -
    - - - - -
    #define USB_OTG_DIEPINT_INEPNM_Pos   (5U)
    -
    - -
    -
    - -

    ◆ USB_OTG_DIEPINT_INEPNM_Msk

    - -
    -
    - - - - -
    #define USB_OTG_DIEPINT_INEPNM_Msk   (0x1UL << USB_OTG_DIEPINT_INEPNM_Pos)
    -
    -

    0x00000004

    - -
    -
    - -

    ◆ USB_OTG_DIEPINT_INEPNM

    - -
    -
    - - - - -
    #define USB_OTG_DIEPINT_INEPNM   USB_OTG_DIEPINT_INEPNM_Msk
    -
    -

    IN token received with EP mismatch

    - -
    -
    - -

    ◆ USB_OTG_DIEPINT_INEPNE_Pos

    - -
    -
    - - - - -
    #define USB_OTG_DIEPINT_INEPNE_Pos   (6U)
    -
    - -
    -
    - -

    ◆ USB_OTG_DIEPINT_INEPNE_Msk

    - -
    -
    - - - - -
    #define USB_OTG_DIEPINT_INEPNE_Msk   (0x1UL << USB_OTG_DIEPINT_INEPNE_Pos)
    -
    -

    0x00000040

    - -
    -
    - -

    ◆ USB_OTG_DIEPINT_INEPNE

    - -
    -
    - - - - -
    #define USB_OTG_DIEPINT_INEPNE   USB_OTG_DIEPINT_INEPNE_Msk
    -
    -

    IN endpoint NAK effective

    - -
    -
    - -

    ◆ USB_OTG_DIEPINT_TXFE_Pos

    - -
    -
    - - - - -
    #define USB_OTG_DIEPINT_TXFE_Pos   (7U)
    -
    - -
    -
    - -

    ◆ USB_OTG_DIEPINT_TXFE_Msk

    - -
    -
    - - - - -
    #define USB_OTG_DIEPINT_TXFE_Msk   (0x1UL << USB_OTG_DIEPINT_TXFE_Pos)
    -
    -

    0x00000080

    - -
    -
    - -

    ◆ USB_OTG_DIEPINT_TXFE

    - -
    -
    - - - - -
    #define USB_OTG_DIEPINT_TXFE   USB_OTG_DIEPINT_TXFE_Msk
    -
    -

    Transmit FIFO empty

    - -
    -
    - -

    ◆ USB_OTG_DIEPINT_TXFIFOUDRN_Pos

    - -
    -
    - - - - -
    #define USB_OTG_DIEPINT_TXFIFOUDRN_Pos   (8U)
    -
    - -
    -
    - -

    ◆ USB_OTG_DIEPINT_TXFIFOUDRN_Msk

    - -
    -
    - - - - -
    #define USB_OTG_DIEPINT_TXFIFOUDRN_Msk   (0x1UL << USB_OTG_DIEPINT_TXFIFOUDRN_Pos)
    -
    -

    0x00000100

    - -
    -
    - -

    ◆ USB_OTG_DIEPINT_TXFIFOUDRN

    - -
    -
    - - - - -
    #define USB_OTG_DIEPINT_TXFIFOUDRN   USB_OTG_DIEPINT_TXFIFOUDRN_Msk
    -
    -

    Transmit Fifo Underrun

    - -
    -
    - -

    ◆ USB_OTG_DIEPINT_BNA_Pos

    - -
    -
    - - - - -
    #define USB_OTG_DIEPINT_BNA_Pos   (9U)
    -
    - -
    -
    - -

    ◆ USB_OTG_DIEPINT_BNA_Msk

    - -
    -
    - - - - -
    #define USB_OTG_DIEPINT_BNA_Msk   (0x1UL << USB_OTG_DIEPINT_BNA_Pos)
    -
    -

    0x00000200

    - -
    -
    - -

    ◆ USB_OTG_DIEPINT_BNA

    - -
    -
    - - - - -
    #define USB_OTG_DIEPINT_BNA   USB_OTG_DIEPINT_BNA_Msk
    -
    -

    Buffer not available interrupt

    - -
    -
    - -

    ◆ USB_OTG_DIEPINT_PKTDRPSTS_Pos

    - -
    -
    - - - - -
    #define USB_OTG_DIEPINT_PKTDRPSTS_Pos   (11U)
    -
    - -
    -
    - -

    ◆ USB_OTG_DIEPINT_PKTDRPSTS_Msk

    - -
    -
    - - - - -
    #define USB_OTG_DIEPINT_PKTDRPSTS_Msk   (0x1UL << USB_OTG_DIEPINT_PKTDRPSTS_Pos)
    -
    -

    0x00000800

    - -
    -
    - -

    ◆ USB_OTG_DIEPINT_PKTDRPSTS

    - -
    -
    - - - - -
    #define USB_OTG_DIEPINT_PKTDRPSTS   USB_OTG_DIEPINT_PKTDRPSTS_Msk
    -
    -

    Packet dropped status

    - -
    -
    - -

    ◆ USB_OTG_DIEPINT_BERR_Pos

    - -
    -
    - - - - -
    #define USB_OTG_DIEPINT_BERR_Pos   (12U)
    -
    - -
    -
    - -

    ◆ USB_OTG_DIEPINT_BERR_Msk

    - -
    -
    - - - - -
    #define USB_OTG_DIEPINT_BERR_Msk   (0x1UL << USB_OTG_DIEPINT_BERR_Pos)
    -
    -

    0x00001000

    - -
    -
    - -

    ◆ USB_OTG_DIEPINT_BERR

    - -
    -
    - - - - -
    #define USB_OTG_DIEPINT_BERR   USB_OTG_DIEPINT_BERR_Msk
    -
    -

    Babble error interrupt

    - -
    -
    - -

    ◆ USB_OTG_DIEPINT_NAK_Pos

    - -
    -
    - - - - -
    #define USB_OTG_DIEPINT_NAK_Pos   (13U)
    -
    - -
    -
    - -

    ◆ USB_OTG_DIEPINT_NAK_Msk

    - -
    -
    - - - - -
    #define USB_OTG_DIEPINT_NAK_Msk   (0x1UL << USB_OTG_DIEPINT_NAK_Pos)
    -
    -

    0x00002000

    - -
    -
    - -

    ◆ USB_OTG_DIEPINT_NAK

    - -
    -
    - - - - -
    #define USB_OTG_DIEPINT_NAK   USB_OTG_DIEPINT_NAK_Msk
    -
    -

    NAK interrupt

    - -
    -
    - -

    ◆ USB_OTG_HCINTMSK_XFRCM_Pos

    - -
    -
    - - - - -
    #define USB_OTG_HCINTMSK_XFRCM_Pos   (0U)
    -
    - -
    -
    - -

    ◆ USB_OTG_HCINTMSK_XFRCM_Msk

    - -
    -
    - - - - -
    #define USB_OTG_HCINTMSK_XFRCM_Msk   (0x1UL << USB_OTG_HCINTMSK_XFRCM_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ USB_OTG_HCINTMSK_XFRCM

    - -
    -
    - - - - -
    #define USB_OTG_HCINTMSK_XFRCM   USB_OTG_HCINTMSK_XFRCM_Msk
    -
    -

    Transfer completed mask

    - -
    -
    - -

    ◆ USB_OTG_HCINTMSK_CHHM_Pos

    - -
    -
    - - - - -
    #define USB_OTG_HCINTMSK_CHHM_Pos   (1U)
    -
    - -
    -
    - -

    ◆ USB_OTG_HCINTMSK_CHHM_Msk

    - -
    -
    - - - - -
    #define USB_OTG_HCINTMSK_CHHM_Msk   (0x1UL << USB_OTG_HCINTMSK_CHHM_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ USB_OTG_HCINTMSK_CHHM

    - -
    -
    - - - - -
    #define USB_OTG_HCINTMSK_CHHM   USB_OTG_HCINTMSK_CHHM_Msk
    -
    -

    Channel halted mask

    - -
    -
    - -

    ◆ USB_OTG_HCINTMSK_AHBERR_Pos

    - -
    -
    - - - - -
    #define USB_OTG_HCINTMSK_AHBERR_Pos   (2U)
    -
    - -
    -
    - -

    ◆ USB_OTG_HCINTMSK_AHBERR_Msk

    - -
    -
    - - - - -
    #define USB_OTG_HCINTMSK_AHBERR_Msk   (0x1UL << USB_OTG_HCINTMSK_AHBERR_Pos)
    -
    -

    0x00000004

    - -
    -
    - -

    ◆ USB_OTG_HCINTMSK_AHBERR

    - -
    -
    - - - - -
    #define USB_OTG_HCINTMSK_AHBERR   USB_OTG_HCINTMSK_AHBERR_Msk
    -
    -

    AHB error

    - -
    -
    - -

    ◆ USB_OTG_HCINTMSK_STALLM_Pos

    - -
    -
    - - - - -
    #define USB_OTG_HCINTMSK_STALLM_Pos   (3U)
    -
    - -
    -
    - -

    ◆ USB_OTG_HCINTMSK_STALLM_Msk

    - -
    -
    - - - - -
    #define USB_OTG_HCINTMSK_STALLM_Msk   (0x1UL << USB_OTG_HCINTMSK_STALLM_Pos)
    -
    -

    0x00000008

    - -
    -
    - -

    ◆ USB_OTG_HCINTMSK_STALLM

    - -
    -
    - - - - -
    #define USB_OTG_HCINTMSK_STALLM   USB_OTG_HCINTMSK_STALLM_Msk
    -
    -

    STALL response received interrupt mask

    - -
    -
    - -

    ◆ USB_OTG_HCINTMSK_NAKM_Pos

    - -
    -
    - - - - -
    #define USB_OTG_HCINTMSK_NAKM_Pos   (4U)
    -
    - -
    -
    - -

    ◆ USB_OTG_HCINTMSK_NAKM_Msk

    - -
    -
    - - - - -
    #define USB_OTG_HCINTMSK_NAKM_Msk   (0x1UL << USB_OTG_HCINTMSK_NAKM_Pos)
    -
    -

    0x00000010

    - -
    -
    - -

    ◆ USB_OTG_HCINTMSK_NAKM

    - -
    -
    - - - - -
    #define USB_OTG_HCINTMSK_NAKM   USB_OTG_HCINTMSK_NAKM_Msk
    -
    -

    NAK response received interrupt mask

    - -
    -
    - -

    ◆ USB_OTG_HCINTMSK_ACKM_Pos

    - -
    -
    - - - - -
    #define USB_OTG_HCINTMSK_ACKM_Pos   (5U)
    -
    - -
    -
    - -

    ◆ USB_OTG_HCINTMSK_ACKM_Msk

    - -
    -
    - - - - -
    #define USB_OTG_HCINTMSK_ACKM_Msk   (0x1UL << USB_OTG_HCINTMSK_ACKM_Pos)
    -
    -

    0x00000020

    - -
    -
    - -

    ◆ USB_OTG_HCINTMSK_ACKM

    - -
    -
    - - - - -
    #define USB_OTG_HCINTMSK_ACKM   USB_OTG_HCINTMSK_ACKM_Msk
    -
    -

    ACK response received/transmitted interrupt mask

    - -
    -
    - -

    ◆ USB_OTG_HCINTMSK_NYET_Pos

    - -
    -
    - - - - -
    #define USB_OTG_HCINTMSK_NYET_Pos   (6U)
    -
    - -
    -
    - -

    ◆ USB_OTG_HCINTMSK_NYET_Msk

    - -
    -
    - - - - -
    #define USB_OTG_HCINTMSK_NYET_Msk   (0x1UL << USB_OTG_HCINTMSK_NYET_Pos)
    -
    -

    0x00000040

    - -
    -
    - -

    ◆ USB_OTG_HCINTMSK_NYET

    - -
    -
    - - - - -
    #define USB_OTG_HCINTMSK_NYET   USB_OTG_HCINTMSK_NYET_Msk
    -
    -

    response received interrupt mask

    - -
    -
    - -

    ◆ USB_OTG_HCINTMSK_TXERRM_Pos

    - -
    -
    - - - - -
    #define USB_OTG_HCINTMSK_TXERRM_Pos   (7U)
    -
    - -
    -
    - -

    ◆ USB_OTG_HCINTMSK_TXERRM_Msk

    - -
    -
    - - - - -
    #define USB_OTG_HCINTMSK_TXERRM_Msk   (0x1UL << USB_OTG_HCINTMSK_TXERRM_Pos)
    -
    -

    0x00000080

    - -
    -
    - -

    ◆ USB_OTG_HCINTMSK_TXERRM

    - -
    -
    - - - - -
    #define USB_OTG_HCINTMSK_TXERRM   USB_OTG_HCINTMSK_TXERRM_Msk
    -
    -

    Transaction error mask

    - -
    -
    - -

    ◆ USB_OTG_HCINTMSK_BBERRM_Pos

    - -
    -
    - - - - -
    #define USB_OTG_HCINTMSK_BBERRM_Pos   (8U)
    -
    - -
    -
    - -

    ◆ USB_OTG_HCINTMSK_BBERRM_Msk

    - -
    -
    - - - - -
    #define USB_OTG_HCINTMSK_BBERRM_Msk   (0x1UL << USB_OTG_HCINTMSK_BBERRM_Pos)
    -
    -

    0x00000100

    - -
    -
    - -

    ◆ USB_OTG_HCINTMSK_BBERRM

    - -
    -
    - - - - -
    #define USB_OTG_HCINTMSK_BBERRM   USB_OTG_HCINTMSK_BBERRM_Msk
    -
    -

    Babble error mask

    - -
    -
    - -

    ◆ USB_OTG_HCINTMSK_FRMORM_Pos

    - -
    -
    - - - - -
    #define USB_OTG_HCINTMSK_FRMORM_Pos   (9U)
    -
    - -
    -
    - -

    ◆ USB_OTG_HCINTMSK_FRMORM_Msk

    - -
    -
    - - - - -
    #define USB_OTG_HCINTMSK_FRMORM_Msk   (0x1UL << USB_OTG_HCINTMSK_FRMORM_Pos)
    -
    -

    0x00000200

    - -
    -
    - -

    ◆ USB_OTG_HCINTMSK_FRMORM

    - -
    -
    - - - - -
    #define USB_OTG_HCINTMSK_FRMORM   USB_OTG_HCINTMSK_FRMORM_Msk
    -
    -

    Frame overrun mask

    - -
    -
    - -

    ◆ USB_OTG_HCINTMSK_DTERRM_Pos

    - -
    -
    - - - - -
    #define USB_OTG_HCINTMSK_DTERRM_Pos   (10U)
    -
    - -
    -
    - -

    ◆ USB_OTG_HCINTMSK_DTERRM_Msk

    - -
    -
    - - - - -
    #define USB_OTG_HCINTMSK_DTERRM_Msk   (0x1UL << USB_OTG_HCINTMSK_DTERRM_Pos)
    -
    -

    0x00000400

    - -
    -
    - -

    ◆ USB_OTG_HCINTMSK_DTERRM

    - -
    -
    - - - - -
    #define USB_OTG_HCINTMSK_DTERRM   USB_OTG_HCINTMSK_DTERRM_Msk
    -
    -

    Data toggle error mask

    - -
    -
    - -

    ◆ USB_OTG_DIEPTSIZ_XFRSIZ_Pos

    - -
    -
    - - - - -
    #define USB_OTG_DIEPTSIZ_XFRSIZ_Pos   (0U)
    -
    - -
    -
    - -

    ◆ USB_OTG_DIEPTSIZ_XFRSIZ_Msk

    - -
    -
    - - - - -
    #define USB_OTG_DIEPTSIZ_XFRSIZ_Msk   (0x7FFFFUL << USB_OTG_DIEPTSIZ_XFRSIZ_Pos)
    -
    -

    0x0007FFFF

    - -
    -
    - -

    ◆ USB_OTG_DIEPTSIZ_XFRSIZ

    - -
    -
    - - - - -
    #define USB_OTG_DIEPTSIZ_XFRSIZ   USB_OTG_DIEPTSIZ_XFRSIZ_Msk
    -
    -

    Transfer size

    - -
    -
    - -

    ◆ USB_OTG_DIEPTSIZ_PKTCNT_Pos

    - -
    -
    - - - - -
    #define USB_OTG_DIEPTSIZ_PKTCNT_Pos   (19U)
    -
    - -
    -
    - -

    ◆ USB_OTG_DIEPTSIZ_PKTCNT_Msk

    - -
    -
    - - - - -
    #define USB_OTG_DIEPTSIZ_PKTCNT_Msk   (0x3FFUL << USB_OTG_DIEPTSIZ_PKTCNT_Pos)
    -
    -

    0x1FF80000

    - -
    -
    - -

    ◆ USB_OTG_DIEPTSIZ_PKTCNT

    - -
    -
    - - - - -
    #define USB_OTG_DIEPTSIZ_PKTCNT   USB_OTG_DIEPTSIZ_PKTCNT_Msk
    -
    -

    Packet count

    - -
    -
    - -

    ◆ USB_OTG_DIEPTSIZ_MULCNT_Pos

    - -
    -
    - - - - -
    #define USB_OTG_DIEPTSIZ_MULCNT_Pos   (29U)
    -
    - -
    -
    - -

    ◆ USB_OTG_DIEPTSIZ_MULCNT_Msk

    - -
    -
    - - - - -
    #define USB_OTG_DIEPTSIZ_MULCNT_Msk   (0x3UL << USB_OTG_DIEPTSIZ_MULCNT_Pos)
    -
    -

    0x60000000

    - -
    -
    - -

    ◆ USB_OTG_DIEPTSIZ_MULCNT

    - -
    -
    - - - - -
    #define USB_OTG_DIEPTSIZ_MULCNT   USB_OTG_DIEPTSIZ_MULCNT_Msk
    -
    -

    Packet count

    - -
    -
    - -

    ◆ USB_OTG_HCTSIZ_XFRSIZ_Pos

    - -
    -
    - - - - -
    #define USB_OTG_HCTSIZ_XFRSIZ_Pos   (0U)
    -
    - -
    -
    - -

    ◆ USB_OTG_HCTSIZ_XFRSIZ_Msk

    - -
    -
    - - - - -
    #define USB_OTG_HCTSIZ_XFRSIZ_Msk   (0x7FFFFUL << USB_OTG_HCTSIZ_XFRSIZ_Pos)
    -
    -

    0x0007FFFF

    - -
    -
    - -

    ◆ USB_OTG_HCTSIZ_XFRSIZ

    - -
    -
    - - - - -
    #define USB_OTG_HCTSIZ_XFRSIZ   USB_OTG_HCTSIZ_XFRSIZ_Msk
    -
    -

    Transfer size

    - -
    -
    - -

    ◆ USB_OTG_HCTSIZ_PKTCNT_Pos

    - -
    -
    - - - - -
    #define USB_OTG_HCTSIZ_PKTCNT_Pos   (19U)
    -
    - -
    -
    - -

    ◆ USB_OTG_HCTSIZ_PKTCNT_Msk

    - -
    -
    - - - - -
    #define USB_OTG_HCTSIZ_PKTCNT_Msk   (0x3FFUL << USB_OTG_HCTSIZ_PKTCNT_Pos)
    -
    -

    0x1FF80000

    - -
    -
    - -

    ◆ USB_OTG_HCTSIZ_PKTCNT

    - -
    -
    - - - - -
    #define USB_OTG_HCTSIZ_PKTCNT   USB_OTG_HCTSIZ_PKTCNT_Msk
    -
    -

    Packet count

    - -
    -
    - -

    ◆ USB_OTG_HCTSIZ_DOPING_Pos

    - -
    -
    - - - - -
    #define USB_OTG_HCTSIZ_DOPING_Pos   (31U)
    -
    - -
    -
    - -

    ◆ USB_OTG_HCTSIZ_DOPING_Msk

    - -
    -
    - - - - -
    #define USB_OTG_HCTSIZ_DOPING_Msk   (0x1UL << USB_OTG_HCTSIZ_DOPING_Pos)
    -
    -

    0x80000000

    - -
    -
    - -

    ◆ USB_OTG_HCTSIZ_DOPING

    - -
    -
    - - - - -
    #define USB_OTG_HCTSIZ_DOPING   USB_OTG_HCTSIZ_DOPING_Msk
    -
    -

    Do PING

    - -
    -
    - -

    ◆ USB_OTG_HCTSIZ_DPID_Pos

    - -
    -
    - - - - -
    #define USB_OTG_HCTSIZ_DPID_Pos   (29U)
    -
    - -
    -
    - -

    ◆ USB_OTG_HCTSIZ_DPID_Msk

    - -
    -
    - - - - -
    #define USB_OTG_HCTSIZ_DPID_Msk   (0x3UL << USB_OTG_HCTSIZ_DPID_Pos)
    -
    -

    0x60000000

    - -
    -
    - -

    ◆ USB_OTG_HCTSIZ_DPID

    - -
    -
    - - - - -
    #define USB_OTG_HCTSIZ_DPID   USB_OTG_HCTSIZ_DPID_Msk
    -
    -

    Data PID

    - -
    -
    - -

    ◆ USB_OTG_HCTSIZ_DPID_0

    - -
    -
    - - - - -
    #define USB_OTG_HCTSIZ_DPID_0   (0x1UL << USB_OTG_HCTSIZ_DPID_Pos)
    -
    -

    0x20000000

    - -
    -
    - -

    ◆ USB_OTG_HCTSIZ_DPID_1

    - -
    -
    - - - - -
    #define USB_OTG_HCTSIZ_DPID_1   (0x2UL << USB_OTG_HCTSIZ_DPID_Pos)
    -
    -

    0x40000000

    - -
    -
    - -

    ◆ USB_OTG_DIEPDMA_DMAADDR_Pos

    - -
    -
    - - - - -
    #define USB_OTG_DIEPDMA_DMAADDR_Pos   (0U)
    -
    - -
    -
    - -

    ◆ USB_OTG_DIEPDMA_DMAADDR_Msk

    - -
    -
    - - - - -
    #define USB_OTG_DIEPDMA_DMAADDR_Msk   (0xFFFFFFFFUL << USB_OTG_DIEPDMA_DMAADDR_Pos)
    -
    -

    0xFFFFFFFF

    - -
    -
    - -

    ◆ USB_OTG_DIEPDMA_DMAADDR

    - -
    -
    - - - - -
    #define USB_OTG_DIEPDMA_DMAADDR   USB_OTG_DIEPDMA_DMAADDR_Msk
    -
    -

    DMA address

    - -
    -
    - -

    ◆ USB_OTG_HCDMA_DMAADDR_Pos

    - -
    -
    - - - - -
    #define USB_OTG_HCDMA_DMAADDR_Pos   (0U)
    -
    - -
    -
    - -

    ◆ USB_OTG_HCDMA_DMAADDR_Msk

    - -
    -
    - - - - -
    #define USB_OTG_HCDMA_DMAADDR_Msk   (0xFFFFFFFFUL << USB_OTG_HCDMA_DMAADDR_Pos)
    -
    -

    0xFFFFFFFF

    - -
    -
    - -

    ◆ USB_OTG_HCDMA_DMAADDR

    - -
    -
    - - - - -
    #define USB_OTG_HCDMA_DMAADDR   USB_OTG_HCDMA_DMAADDR_Msk
    -
    -

    DMA address

    - -
    -
    - -

    ◆ USB_OTG_DTXFSTS_INEPTFSAV_Pos

    - -
    -
    - - - - -
    #define USB_OTG_DTXFSTS_INEPTFSAV_Pos   (0U)
    -
    - -
    -
    - -

    ◆ USB_OTG_DTXFSTS_INEPTFSAV_Msk

    - -
    -
    - - - - -
    #define USB_OTG_DTXFSTS_INEPTFSAV_Msk   (0xFFFFUL << USB_OTG_DTXFSTS_INEPTFSAV_Pos)
    -
    -

    0x0000FFFF

    - -
    -
    - -

    ◆ USB_OTG_DTXFSTS_INEPTFSAV

    - -
    -
    - - - - -
    #define USB_OTG_DTXFSTS_INEPTFSAV   USB_OTG_DTXFSTS_INEPTFSAV_Msk
    -
    -

    IN endpoint TxFIFO space available

    - -
    -
    - -

    ◆ USB_OTG_DIEPTXF_INEPTXSA_Pos

    - -
    -
    - - - - -
    #define USB_OTG_DIEPTXF_INEPTXSA_Pos   (0U)
    -
    - -
    -
    - -

    ◆ USB_OTG_DIEPTXF_INEPTXSA_Msk

    - -
    -
    - - - - -
    #define USB_OTG_DIEPTXF_INEPTXSA_Msk   (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXSA_Pos)
    -
    -

    0x0000FFFF

    - -
    -
    - -

    ◆ USB_OTG_DIEPTXF_INEPTXSA

    - -
    -
    - - - - -
    #define USB_OTG_DIEPTXF_INEPTXSA   USB_OTG_DIEPTXF_INEPTXSA_Msk
    -
    -

    IN endpoint FIFOx transmit RAM start address

    - -
    -
    - -

    ◆ USB_OTG_DIEPTXF_INEPTXFD_Pos

    - -
    -
    - - - - -
    #define USB_OTG_DIEPTXF_INEPTXFD_Pos   (16U)
    -
    - -
    -
    - -

    ◆ USB_OTG_DIEPTXF_INEPTXFD_Msk

    - -
    -
    - - - - -
    #define USB_OTG_DIEPTXF_INEPTXFD_Msk   (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXFD_Pos)
    -
    -

    0xFFFF0000

    - -
    -
    - -

    ◆ USB_OTG_DIEPTXF_INEPTXFD

    - -
    -
    - - - - -
    #define USB_OTG_DIEPTXF_INEPTXFD   USB_OTG_DIEPTXF_INEPTXFD_Msk
    -
    -

    IN endpoint TxFIFO depth

    - -
    -
    - -

    ◆ USB_OTG_DOEPCTL_MPSIZ_Pos

    - -
    -
    - - - - -
    #define USB_OTG_DOEPCTL_MPSIZ_Pos   (0U)
    -
    - -
    -
    - -

    ◆ USB_OTG_DOEPCTL_MPSIZ_Msk

    - -
    -
    - - - - -
    #define USB_OTG_DOEPCTL_MPSIZ_Msk   (0x7FFUL << USB_OTG_DOEPCTL_MPSIZ_Pos)
    -
    -

    0x000007FF

    - -
    -
    - -

    ◆ USB_OTG_DOEPCTL_MPSIZ

    - -
    -
    - - - - -
    #define USB_OTG_DOEPCTL_MPSIZ   USB_OTG_DOEPCTL_MPSIZ_Msk /*!< Maximum packet size */
    -
    -

    Bit 1

    - -
    -
    - -

    ◆ USB_OTG_DOEPCTL_USBAEP_Pos

    - -
    -
    - - - - -
    #define USB_OTG_DOEPCTL_USBAEP_Pos   (15U)
    -
    - -
    -
    - -

    ◆ USB_OTG_DOEPCTL_USBAEP_Msk

    - -
    -
    - - - - -
    #define USB_OTG_DOEPCTL_USBAEP_Msk   (0x1UL << USB_OTG_DOEPCTL_USBAEP_Pos)
    -
    -

    0x00008000

    - -
    -
    - -

    ◆ USB_OTG_DOEPCTL_USBAEP

    - -
    -
    - - - - -
    #define USB_OTG_DOEPCTL_USBAEP   USB_OTG_DOEPCTL_USBAEP_Msk
    -
    -

    USB active endpoint

    - -
    -
    - -

    ◆ USB_OTG_DOEPCTL_NAKSTS_Pos

    - -
    -
    - - - - -
    #define USB_OTG_DOEPCTL_NAKSTS_Pos   (17U)
    -
    - -
    -
    - -

    ◆ USB_OTG_DOEPCTL_NAKSTS_Msk

    - -
    -
    - - - - -
    #define USB_OTG_DOEPCTL_NAKSTS_Msk   (0x1UL << USB_OTG_DOEPCTL_NAKSTS_Pos)
    -
    -

    0x00020000

    - -
    -
    - -

    ◆ USB_OTG_DOEPCTL_NAKSTS

    - -
    -
    - - - - -
    #define USB_OTG_DOEPCTL_NAKSTS   USB_OTG_DOEPCTL_NAKSTS_Msk
    -
    -

    NAK status

    - -
    -
    - -

    ◆ USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos

    - -
    -
    - - - - -
    #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos   (28U)
    -
    - -
    -
    - -

    ◆ USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk

    - -
    -
    - - - - -
    #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk   (0x1UL << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos)
    -
    -

    0x10000000

    - -
    -
    - -

    ◆ USB_OTG_DOEPCTL_SD0PID_SEVNFRM

    - -
    -
    - - - - -
    #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM   USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk
    -
    -

    Set DATA0 PID

    - -
    -
    - -

    ◆ USB_OTG_DOEPCTL_SODDFRM_Pos

    - -
    -
    - - - - -
    #define USB_OTG_DOEPCTL_SODDFRM_Pos   (29U)
    -
    - -
    -
    - -

    ◆ USB_OTG_DOEPCTL_SODDFRM_Msk

    - -
    -
    - - - - -
    #define USB_OTG_DOEPCTL_SODDFRM_Msk   (0x1UL << USB_OTG_DOEPCTL_SODDFRM_Pos)
    -
    -

    0x20000000

    - -
    -
    - -

    ◆ USB_OTG_DOEPCTL_SODDFRM

    - -
    -
    - - - - -
    #define USB_OTG_DOEPCTL_SODDFRM   USB_OTG_DOEPCTL_SODDFRM_Msk
    -
    -

    Set odd frame

    - -
    -
    - -

    ◆ USB_OTG_DOEPCTL_EPTYP_Pos

    - -
    -
    - - - - -
    #define USB_OTG_DOEPCTL_EPTYP_Pos   (18U)
    -
    - -
    -
    - -

    ◆ USB_OTG_DOEPCTL_EPTYP_Msk

    - -
    -
    - - - - -
    #define USB_OTG_DOEPCTL_EPTYP_Msk   (0x3UL << USB_OTG_DOEPCTL_EPTYP_Pos)
    -
    -

    0x000C0000

    - -
    -
    - -

    ◆ USB_OTG_DOEPCTL_EPTYP

    - -
    -
    - - - - -
    #define USB_OTG_DOEPCTL_EPTYP   USB_OTG_DOEPCTL_EPTYP_Msk
    -
    -

    Endpoint type

    - -
    -
    - -

    ◆ USB_OTG_DOEPCTL_EPTYP_0

    - -
    -
    - - - - -
    #define USB_OTG_DOEPCTL_EPTYP_0   (0x1UL << USB_OTG_DOEPCTL_EPTYP_Pos)
    -
    -

    0x00040000

    - -
    -
    - -

    ◆ USB_OTG_DOEPCTL_EPTYP_1

    - -
    -
    - - - - -
    #define USB_OTG_DOEPCTL_EPTYP_1   (0x2UL << USB_OTG_DOEPCTL_EPTYP_Pos)
    -
    -

    0x00080000

    - -
    -
    - -

    ◆ USB_OTG_DOEPCTL_SNPM_Pos

    - -
    -
    - - - - -
    #define USB_OTG_DOEPCTL_SNPM_Pos   (20U)
    -
    - -
    -
    - -

    ◆ USB_OTG_DOEPCTL_SNPM_Msk

    - -
    -
    - - - - -
    #define USB_OTG_DOEPCTL_SNPM_Msk   (0x1UL << USB_OTG_DOEPCTL_SNPM_Pos)
    -
    -

    0x00100000

    - -
    -
    - -

    ◆ USB_OTG_DOEPCTL_SNPM

    - -
    -
    - - - - -
    #define USB_OTG_DOEPCTL_SNPM   USB_OTG_DOEPCTL_SNPM_Msk
    -
    -

    Snoop mode

    - -
    -
    - -

    ◆ USB_OTG_DOEPCTL_STALL_Pos

    - -
    -
    - - - - -
    #define USB_OTG_DOEPCTL_STALL_Pos   (21U)
    -
    - -
    -
    - -

    ◆ USB_OTG_DOEPCTL_STALL_Msk

    - -
    -
    - - - - -
    #define USB_OTG_DOEPCTL_STALL_Msk   (0x1UL << USB_OTG_DOEPCTL_STALL_Pos)
    -
    -

    0x00200000

    - -
    -
    - -

    ◆ USB_OTG_DOEPCTL_STALL

    - -
    -
    - - - - -
    #define USB_OTG_DOEPCTL_STALL   USB_OTG_DOEPCTL_STALL_Msk
    -
    -

    STALL handshake

    - -
    -
    - -

    ◆ USB_OTG_DOEPCTL_CNAK_Pos

    - -
    -
    - - - - -
    #define USB_OTG_DOEPCTL_CNAK_Pos   (26U)
    -
    - -
    -
    - -

    ◆ USB_OTG_DOEPCTL_CNAK_Msk

    - -
    -
    - - - - -
    #define USB_OTG_DOEPCTL_CNAK_Msk   (0x1UL << USB_OTG_DOEPCTL_CNAK_Pos)
    -
    -

    0x04000000

    - -
    -
    - -

    ◆ USB_OTG_DOEPCTL_CNAK

    - -
    -
    - - - - -
    #define USB_OTG_DOEPCTL_CNAK   USB_OTG_DOEPCTL_CNAK_Msk
    -
    -

    Clear NAK

    - -
    -
    - -

    ◆ USB_OTG_DOEPCTL_SNAK_Pos

    - -
    -
    - - - - -
    #define USB_OTG_DOEPCTL_SNAK_Pos   (27U)
    -
    - -
    -
    - -

    ◆ USB_OTG_DOEPCTL_SNAK_Msk

    - -
    -
    - - - - -
    #define USB_OTG_DOEPCTL_SNAK_Msk   (0x1UL << USB_OTG_DOEPCTL_SNAK_Pos)
    -
    -

    0x08000000

    - -
    -
    - -

    ◆ USB_OTG_DOEPCTL_SNAK

    - -
    -
    - - - - -
    #define USB_OTG_DOEPCTL_SNAK   USB_OTG_DOEPCTL_SNAK_Msk
    -
    -

    Set NAK

    - -
    -
    - -

    ◆ USB_OTG_DOEPCTL_EPDIS_Pos

    - -
    -
    - - - - -
    #define USB_OTG_DOEPCTL_EPDIS_Pos   (30U)
    -
    - -
    -
    - -

    ◆ USB_OTG_DOEPCTL_EPDIS_Msk

    - -
    -
    - - - - -
    #define USB_OTG_DOEPCTL_EPDIS_Msk   (0x1UL << USB_OTG_DOEPCTL_EPDIS_Pos)
    -
    -

    0x40000000

    - -
    -
    - -

    ◆ USB_OTG_DOEPCTL_EPDIS

    - -
    -
    - - - - -
    #define USB_OTG_DOEPCTL_EPDIS   USB_OTG_DOEPCTL_EPDIS_Msk
    -
    -

    Endpoint disable

    - -
    -
    - -

    ◆ USB_OTG_DOEPCTL_EPENA_Pos

    - -
    -
    - - - - -
    #define USB_OTG_DOEPCTL_EPENA_Pos   (31U)
    -
    - -
    -
    - -

    ◆ USB_OTG_DOEPCTL_EPENA_Msk

    - -
    -
    - - - - -
    #define USB_OTG_DOEPCTL_EPENA_Msk   (0x1UL << USB_OTG_DOEPCTL_EPENA_Pos)
    -
    -

    0x80000000

    - -
    -
    - -

    ◆ USB_OTG_DOEPCTL_EPENA

    - -
    -
    - - - - -
    #define USB_OTG_DOEPCTL_EPENA   USB_OTG_DOEPCTL_EPENA_Msk
    -
    -

    Endpoint enable

    - -
    -
    - -

    ◆ USB_OTG_DOEPINT_XFRC_Pos

    - -
    -
    - - - - -
    #define USB_OTG_DOEPINT_XFRC_Pos   (0U)
    -
    - -
    -
    - -

    ◆ USB_OTG_DOEPINT_XFRC_Msk

    - -
    -
    - - - - -
    #define USB_OTG_DOEPINT_XFRC_Msk   (0x1UL << USB_OTG_DOEPINT_XFRC_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ USB_OTG_DOEPINT_XFRC

    - -
    -
    - - - - -
    #define USB_OTG_DOEPINT_XFRC   USB_OTG_DOEPINT_XFRC_Msk
    -
    -

    Transfer completed interrupt

    - -
    -
    - -

    ◆ USB_OTG_DOEPINT_EPDISD_Pos

    - -
    -
    - - - - -
    #define USB_OTG_DOEPINT_EPDISD_Pos   (1U)
    -
    - -
    -
    - -

    ◆ USB_OTG_DOEPINT_EPDISD_Msk

    - -
    -
    - - - - -
    #define USB_OTG_DOEPINT_EPDISD_Msk   (0x1UL << USB_OTG_DOEPINT_EPDISD_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ USB_OTG_DOEPINT_EPDISD

    - -
    -
    - - - - -
    #define USB_OTG_DOEPINT_EPDISD   USB_OTG_DOEPINT_EPDISD_Msk
    -
    -

    Endpoint disabled interrupt

    - -
    -
    - -

    ◆ USB_OTG_DOEPINT_AHBERR_Pos

    - -
    -
    - - - - -
    #define USB_OTG_DOEPINT_AHBERR_Pos   (2U)
    -
    - -
    -
    - -

    ◆ USB_OTG_DOEPINT_AHBERR_Msk

    - -
    -
    - - - - -
    #define USB_OTG_DOEPINT_AHBERR_Msk   (0x1UL << USB_OTG_DOEPINT_AHBERR_Pos)
    -
    -

    0x00000004

    - -
    -
    - -

    ◆ USB_OTG_DOEPINT_AHBERR

    - -
    -
    - - - - -
    #define USB_OTG_DOEPINT_AHBERR   USB_OTG_DOEPINT_AHBERR_Msk
    -
    -

    AHB Error (AHBErr) during an OUT transaction

    - -
    -
    - -

    ◆ USB_OTG_DOEPINT_STUP_Pos

    - -
    -
    - - - - -
    #define USB_OTG_DOEPINT_STUP_Pos   (3U)
    -
    - -
    -
    - -

    ◆ USB_OTG_DOEPINT_STUP_Msk

    - -
    -
    - - - - -
    #define USB_OTG_DOEPINT_STUP_Msk   (0x1UL << USB_OTG_DOEPINT_STUP_Pos)
    -
    -

    0x00000008

    - -
    -
    - -

    ◆ USB_OTG_DOEPINT_STUP

    - -
    -
    - - - - -
    #define USB_OTG_DOEPINT_STUP   USB_OTG_DOEPINT_STUP_Msk
    -
    -

    SETUP phase done

    - -
    -
    - -

    ◆ USB_OTG_DOEPINT_OTEPDIS_Pos

    - -
    -
    - - - - -
    #define USB_OTG_DOEPINT_OTEPDIS_Pos   (4U)
    -
    - -
    -
    - -

    ◆ USB_OTG_DOEPINT_OTEPDIS_Msk

    - -
    -
    - - - - -
    #define USB_OTG_DOEPINT_OTEPDIS_Msk   (0x1UL << USB_OTG_DOEPINT_OTEPDIS_Pos)
    -
    -

    0x00000010

    - -
    -
    - -

    ◆ USB_OTG_DOEPINT_OTEPDIS

    - -
    -
    - - - - -
    #define USB_OTG_DOEPINT_OTEPDIS   USB_OTG_DOEPINT_OTEPDIS_Msk
    -
    -

    OUT token received when endpoint disabled

    - -
    -
    - -

    ◆ USB_OTG_DOEPINT_OTEPSPR_Pos

    - -
    -
    - - - - -
    #define USB_OTG_DOEPINT_OTEPSPR_Pos   (5U)
    -
    - -
    -
    - -

    ◆ USB_OTG_DOEPINT_OTEPSPR_Msk

    - -
    -
    - - - - -
    #define USB_OTG_DOEPINT_OTEPSPR_Msk   (0x1UL << USB_OTG_DOEPINT_OTEPSPR_Pos)
    -
    -

    0x00000020

    - -
    -
    - -

    ◆ USB_OTG_DOEPINT_OTEPSPR

    - -
    -
    - - - - -
    #define USB_OTG_DOEPINT_OTEPSPR   USB_OTG_DOEPINT_OTEPSPR_Msk
    -
    -

    Status Phase Received For Control Write

    - -
    -
    - -

    ◆ USB_OTG_DOEPINT_B2BSTUP_Pos

    - -
    -
    - - - - -
    #define USB_OTG_DOEPINT_B2BSTUP_Pos   (6U)
    -
    - -
    -
    - -

    ◆ USB_OTG_DOEPINT_B2BSTUP_Msk

    - -
    -
    - - - - -
    #define USB_OTG_DOEPINT_B2BSTUP_Msk   (0x1UL << USB_OTG_DOEPINT_B2BSTUP_Pos)
    -
    -

    0x00000040

    - -
    -
    - -

    ◆ USB_OTG_DOEPINT_B2BSTUP

    - -
    -
    - - - - -
    #define USB_OTG_DOEPINT_B2BSTUP   USB_OTG_DOEPINT_B2BSTUP_Msk
    -
    -

    Back-to-back SETUP packets received

    - -
    -
    - -

    ◆ USB_OTG_DOEPINT_OUTPKTERR_Pos

    - -
    -
    - - - - -
    #define USB_OTG_DOEPINT_OUTPKTERR_Pos   (8U)
    -
    - -
    -
    - -

    ◆ USB_OTG_DOEPINT_OUTPKTERR_Msk

    - -
    -
    - - - - -
    #define USB_OTG_DOEPINT_OUTPKTERR_Msk   (0x1UL << USB_OTG_DOEPINT_OUTPKTERR_Pos)
    -
    -

    0x00000100

    - -
    -
    - -

    ◆ USB_OTG_DOEPINT_OUTPKTERR

    - -
    -
    - - - - -
    #define USB_OTG_DOEPINT_OUTPKTERR   USB_OTG_DOEPINT_OUTPKTERR_Msk
    -
    -

    OUT packet error

    - -
    -
    - -

    ◆ USB_OTG_DOEPINT_NAK_Pos

    - -
    -
    - - - - -
    #define USB_OTG_DOEPINT_NAK_Pos   (13U)
    -
    - -
    -
    - -

    ◆ USB_OTG_DOEPINT_NAK_Msk

    - -
    -
    - - - - -
    #define USB_OTG_DOEPINT_NAK_Msk   (0x1UL << USB_OTG_DOEPINT_NAK_Pos)
    -
    -

    0x00002000

    - -
    -
    - -

    ◆ USB_OTG_DOEPINT_NAK

    - -
    -
    - - - - -
    #define USB_OTG_DOEPINT_NAK   USB_OTG_DOEPINT_NAK_Msk
    -
    -

    NAK Packet is transmitted by the device

    - -
    -
    - -

    ◆ USB_OTG_DOEPINT_NYET_Pos

    - -
    -
    - - - - -
    #define USB_OTG_DOEPINT_NYET_Pos   (14U)
    -
    - -
    -
    - -

    ◆ USB_OTG_DOEPINT_NYET_Msk

    - -
    -
    - - - - -
    #define USB_OTG_DOEPINT_NYET_Msk   (0x1UL << USB_OTG_DOEPINT_NYET_Pos)
    -
    -

    0x00004000

    - -
    -
    - -

    ◆ USB_OTG_DOEPINT_NYET

    - -
    -
    - - - - -
    #define USB_OTG_DOEPINT_NYET   USB_OTG_DOEPINT_NYET_Msk
    -
    -

    NYET interrupt

    - -
    -
    - -

    ◆ USB_OTG_DOEPINT_STPKTRX_Pos

    - -
    -
    - - - - -
    #define USB_OTG_DOEPINT_STPKTRX_Pos   (15U)
    -
    - -
    -
    - -

    ◆ USB_OTG_DOEPINT_STPKTRX_Msk

    - -
    -
    - - - - -
    #define USB_OTG_DOEPINT_STPKTRX_Msk   (0x1UL << USB_OTG_DOEPINT_STPKTRX_Pos)
    -
    -

    0x00008000

    - -
    -
    - -

    ◆ USB_OTG_DOEPINT_STPKTRX

    - -
    -
    - - - - -
    #define USB_OTG_DOEPINT_STPKTRX   USB_OTG_DOEPINT_STPKTRX_Msk
    -
    -

    Setup Packet Received

    - -
    -
    - -

    ◆ USB_OTG_DOEPTSIZ_XFRSIZ_Pos

    - -
    -
    - - - - -
    #define USB_OTG_DOEPTSIZ_XFRSIZ_Pos   (0U)
    -
    - -
    -
    - -

    ◆ USB_OTG_DOEPTSIZ_XFRSIZ_Msk

    - -
    -
    - - - - -
    #define USB_OTG_DOEPTSIZ_XFRSIZ_Msk   (0x7FFFFUL << USB_OTG_DOEPTSIZ_XFRSIZ_Pos)
    -
    -

    0x0007FFFF

    - -
    -
    - -

    ◆ USB_OTG_DOEPTSIZ_XFRSIZ

    - -
    -
    - - - - -
    #define USB_OTG_DOEPTSIZ_XFRSIZ   USB_OTG_DOEPTSIZ_XFRSIZ_Msk
    -
    -

    Transfer size

    - -
    -
    - -

    ◆ USB_OTG_DOEPTSIZ_PKTCNT_Pos

    - -
    -
    - - - - -
    #define USB_OTG_DOEPTSIZ_PKTCNT_Pos   (19U)
    -
    - -
    -
    - -

    ◆ USB_OTG_DOEPTSIZ_PKTCNT_Msk

    - -
    -
    - - - - -
    #define USB_OTG_DOEPTSIZ_PKTCNT_Msk   (0x3FFUL << USB_OTG_DOEPTSIZ_PKTCNT_Pos)
    -
    -

    0x1FF80000

    - -
    -
    - -

    ◆ USB_OTG_DOEPTSIZ_PKTCNT

    - -
    -
    - - - - -
    #define USB_OTG_DOEPTSIZ_PKTCNT   USB_OTG_DOEPTSIZ_PKTCNT_Msk
    -
    -

    Packet count

    - -
    -
    - -

    ◆ USB_OTG_DOEPTSIZ_STUPCNT_Pos

    - -
    -
    - - - - -
    #define USB_OTG_DOEPTSIZ_STUPCNT_Pos   (29U)
    -
    - -
    -
    - -

    ◆ USB_OTG_DOEPTSIZ_STUPCNT_Msk

    - -
    -
    - - - - -
    #define USB_OTG_DOEPTSIZ_STUPCNT_Msk   (0x3UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos)
    -
    -

    0x60000000

    - -
    -
    - -

    ◆ USB_OTG_DOEPTSIZ_STUPCNT

    - -
    -
    - - - - -
    #define USB_OTG_DOEPTSIZ_STUPCNT   USB_OTG_DOEPTSIZ_STUPCNT_Msk
    -
    -

    SETUP packet count

    - -
    -
    - -

    ◆ USB_OTG_DOEPTSIZ_STUPCNT_0

    - -
    -
    - - - - -
    #define USB_OTG_DOEPTSIZ_STUPCNT_0   (0x1UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos)
    -
    -

    0x20000000

    - -
    -
    - -

    ◆ USB_OTG_DOEPTSIZ_STUPCNT_1

    - -
    -
    - - - - -
    #define USB_OTG_DOEPTSIZ_STUPCNT_1   (0x2UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos)
    -
    -

    0x40000000

    - -
    -
    - -

    ◆ USB_OTG_PCGCCTL_STOPCLK_Pos

    - -
    -
    - - - - -
    #define USB_OTG_PCGCCTL_STOPCLK_Pos   (0U)
    -
    - -
    -
    - -

    ◆ USB_OTG_PCGCCTL_STOPCLK_Msk

    - -
    -
    - - - - -
    #define USB_OTG_PCGCCTL_STOPCLK_Msk   (0x1UL << USB_OTG_PCGCCTL_STOPCLK_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ USB_OTG_PCGCCTL_STOPCLK

    - -
    -
    - - - - -
    #define USB_OTG_PCGCCTL_STOPCLK   USB_OTG_PCGCCTL_STOPCLK_Msk
    -
    -

    SETUP packet count

    - -
    -
    - -

    ◆ USB_OTG_PCGCCTL_GATECLK_Pos

    - -
    -
    - - - - -
    #define USB_OTG_PCGCCTL_GATECLK_Pos   (1U)
    -
    - -
    -
    - -

    ◆ USB_OTG_PCGCCTL_GATECLK_Msk

    - -
    -
    - - - - -
    #define USB_OTG_PCGCCTL_GATECLK_Msk   (0x1UL << USB_OTG_PCGCCTL_GATECLK_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ USB_OTG_PCGCCTL_GATECLK

    - -
    -
    - - - - -
    #define USB_OTG_PCGCCTL_GATECLK   USB_OTG_PCGCCTL_GATECLK_Msk
    -
    -

    Bit 0

    - -
    -
    - -

    ◆ USB_OTG_PCGCCTL_PHYSUSP_Pos

    - -
    -
    - - - - -
    #define USB_OTG_PCGCCTL_PHYSUSP_Pos   (4U)
    -
    - -
    -
    - -

    ◆ USB_OTG_PCGCCTL_PHYSUSP_Msk

    - -
    -
    - - - - -
    #define USB_OTG_PCGCCTL_PHYSUSP_Msk   (0x1UL << USB_OTG_PCGCCTL_PHYSUSP_Pos)
    -
    -

    0x00000010

    - -
    -
    - -

    ◆ USB_OTG_PCGCCTL_PHYSUSP

    - -
    -
    - - - - -
    #define USB_OTG_PCGCCTL_PHYSUSP   USB_OTG_PCGCCTL_PHYSUSP_Msk
    -
    -

    Bit 1

    - -
    -
    - -

    ◆ USB_OTG_CHNUM_Pos

    - -
    -
    - - - - -
    #define USB_OTG_CHNUM_Pos   (0U)
    -
    - -
    -
    - -

    ◆ USB_OTG_CHNUM_Msk

    - -
    -
    - - - - -
    #define USB_OTG_CHNUM_Msk   (0xFUL << USB_OTG_CHNUM_Pos)
    -
    -

    0x0000000F

    - -
    -
    - -

    ◆ USB_OTG_CHNUM

    - -
    -
    - - - - -
    #define USB_OTG_CHNUM   USB_OTG_CHNUM_Msk
    -
    -

    Channel number

    - -
    -
    - -

    ◆ USB_OTG_CHNUM_0

    - -
    -
    - - - - -
    #define USB_OTG_CHNUM_0   (0x1UL << USB_OTG_CHNUM_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ USB_OTG_CHNUM_1

    - -
    -
    - - - - -
    #define USB_OTG_CHNUM_1   (0x2UL << USB_OTG_CHNUM_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ USB_OTG_CHNUM_2

    - -
    -
    - - - - -
    #define USB_OTG_CHNUM_2   (0x4UL << USB_OTG_CHNUM_Pos)
    -
    -

    0x00000004

    - -
    -
    - -

    ◆ USB_OTG_CHNUM_3

    - -
    -
    - - - - -
    #define USB_OTG_CHNUM_3   (0x8UL << USB_OTG_CHNUM_Pos)
    -
    -

    0x00000008

    - -
    -
    - -

    ◆ USB_OTG_BCNT_Pos

    - -
    -
    - - - - -
    #define USB_OTG_BCNT_Pos   (4U)
    -
    - -
    -
    - -

    ◆ USB_OTG_BCNT_Msk

    - -
    -
    - - - - -
    #define USB_OTG_BCNT_Msk   (0x7FFUL << USB_OTG_BCNT_Pos)
    -
    -

    0x00007FF0

    - -
    -
    - -

    ◆ USB_OTG_BCNT

    - -
    -
    - - - - -
    #define USB_OTG_BCNT   USB_OTG_BCNT_Msk
    -
    -

    Byte count

    - -
    -
    - -

    ◆ USB_OTG_DPID_Pos

    - -
    -
    - - - - -
    #define USB_OTG_DPID_Pos   (15U)
    -
    - -
    -
    - -

    ◆ USB_OTG_DPID_Msk

    - -
    -
    - - - - -
    #define USB_OTG_DPID_Msk   (0x3UL << USB_OTG_DPID_Pos)
    -
    -

    0x00018000

    - -
    -
    - -

    ◆ USB_OTG_DPID

    - -
    -
    - - - - -
    #define USB_OTG_DPID   USB_OTG_DPID_Msk
    -
    -

    Data PID

    - -
    -
    - -

    ◆ USB_OTG_DPID_0

    - -
    -
    - - - - -
    #define USB_OTG_DPID_0   (0x1UL << USB_OTG_DPID_Pos)
    -
    -

    0x00008000

    - -
    -
    - -

    ◆ USB_OTG_DPID_1

    - -
    -
    - - - - -
    #define USB_OTG_DPID_1   (0x2UL << USB_OTG_DPID_Pos)
    -
    -

    0x00010000

    - -
    -
    - -

    ◆ USB_OTG_PKTSTS_Pos

    - -
    -
    - - - - -
    #define USB_OTG_PKTSTS_Pos   (17U)
    -
    - -
    -
    - -

    ◆ USB_OTG_PKTSTS_Msk

    - -
    -
    - - - - -
    #define USB_OTG_PKTSTS_Msk   (0xFUL << USB_OTG_PKTSTS_Pos)
    -
    -

    0x001E0000

    - -
    -
    - -

    ◆ USB_OTG_PKTSTS

    - -
    -
    - - - - -
    #define USB_OTG_PKTSTS   USB_OTG_PKTSTS_Msk
    -
    -

    Packet status

    - -
    -
    - -

    ◆ USB_OTG_PKTSTS_0

    - -
    -
    - - - - -
    #define USB_OTG_PKTSTS_0   (0x1UL << USB_OTG_PKTSTS_Pos)
    -
    -

    0x00020000

    - -
    -
    - -

    ◆ USB_OTG_PKTSTS_1

    - -
    -
    - - - - -
    #define USB_OTG_PKTSTS_1   (0x2UL << USB_OTG_PKTSTS_Pos)
    -
    -

    0x00040000

    - -
    -
    - -

    ◆ USB_OTG_PKTSTS_2

    - -
    -
    - - - - -
    #define USB_OTG_PKTSTS_2   (0x4UL << USB_OTG_PKTSTS_Pos)
    -
    -

    0x00080000

    - -
    -
    - -

    ◆ USB_OTG_PKTSTS_3

    - -
    -
    - - - - -
    #define USB_OTG_PKTSTS_3   (0x8UL << USB_OTG_PKTSTS_Pos)
    -
    -

    0x00100000

    - -
    -
    - -

    ◆ USB_OTG_EPNUM_Pos

    - -
    -
    - - - - -
    #define USB_OTG_EPNUM_Pos   (0U)
    -
    - -
    -
    - -

    ◆ USB_OTG_EPNUM_Msk

    - -
    -
    - - - - -
    #define USB_OTG_EPNUM_Msk   (0xFUL << USB_OTG_EPNUM_Pos)
    -
    -

    0x0000000F

    - -
    -
    - -

    ◆ USB_OTG_EPNUM

    - -
    -
    - - - - -
    #define USB_OTG_EPNUM   USB_OTG_EPNUM_Msk
    -
    -

    Endpoint number

    - -
    -
    - -

    ◆ USB_OTG_EPNUM_0

    - -
    -
    - - - - -
    #define USB_OTG_EPNUM_0   (0x1UL << USB_OTG_EPNUM_Pos)
    -
    -

    0x00000001

    - -
    -
    - -

    ◆ USB_OTG_EPNUM_1

    - -
    -
    - - - - -
    #define USB_OTG_EPNUM_1   (0x2UL << USB_OTG_EPNUM_Pos)
    -
    -

    0x00000002

    - -
    -
    - -

    ◆ USB_OTG_EPNUM_2

    - -
    -
    - - - - -
    #define USB_OTG_EPNUM_2   (0x4UL << USB_OTG_EPNUM_Pos)
    -
    -

    0x00000004

    - -
    -
    - -

    ◆ USB_OTG_EPNUM_3

    - -
    -
    - - - - -
    #define USB_OTG_EPNUM_3   (0x8UL << USB_OTG_EPNUM_Pos)
    -
    -

    0x00000008

    - -
    -
    - -

    ◆ USB_OTG_FRMNUM_Pos

    - -
    -
    - - - - -
    #define USB_OTG_FRMNUM_Pos   (21U)
    -
    - -
    -
    - -

    ◆ USB_OTG_FRMNUM_Msk

    - -
    -
    - - - - -
    #define USB_OTG_FRMNUM_Msk   (0xFUL << USB_OTG_FRMNUM_Pos)
    -
    -

    0x01E00000

    - -
    -
    - -

    ◆ USB_OTG_FRMNUM

    - -
    -
    - - - - -
    #define USB_OTG_FRMNUM   USB_OTG_FRMNUM_Msk
    -
    -

    Frame number

    - -
    -
    - -

    ◆ USB_OTG_FRMNUM_0

    - -
    -
    - - - - -
    #define USB_OTG_FRMNUM_0   (0x1UL << USB_OTG_FRMNUM_Pos)
    -
    -

    0x00200000

    - -
    -
    - -

    ◆ USB_OTG_FRMNUM_1

    - -
    -
    - - - - -
    #define USB_OTG_FRMNUM_1   (0x2UL << USB_OTG_FRMNUM_Pos)
    -
    -

    0x00400000

    - -
    -
    - -

    ◆ USB_OTG_FRMNUM_2

    - -
    -
    - - - - -
    #define USB_OTG_FRMNUM_2   (0x4UL << USB_OTG_FRMNUM_Pos)
    -
    -

    0x00800000

    - -
    -
    - -

    ◆ USB_OTG_FRMNUM_3

    - -
    -
    - - - - -
    #define USB_OTG_FRMNUM_3   (0x8UL << USB_OTG_FRMNUM_Pos)
    -
    -

    0x01000000

    - -
    -
    -
    - -
    -Generated by doxygen 1.10.0 -
    - - diff --git a/DOCS/html/group___peripheral___registers___bits___definition.map b/DOCS/html/group___peripheral___registers___bits___definition.map deleted file mode 100644 index 61e7e30..0000000 --- a/DOCS/html/group___peripheral___registers___bits___definition.map +++ /dev/null @@ -1,4 +0,0 @@ - - - - diff --git a/DOCS/html/group___peripheral___registers___bits___definition.md5 b/DOCS/html/group___peripheral___registers___bits___definition.md5 deleted file mode 100644 index e671dd2..0000000 --- a/DOCS/html/group___peripheral___registers___bits___definition.md5 +++ /dev/null @@ -1 +0,0 @@ -2f7d1e23a575d95a40bba7ebe51b620f \ No newline at end of file diff --git a/DOCS/html/group___peripheral___registers___bits___definition.png b/DOCS/html/group___peripheral___registers___bits___definition.png deleted file mode 100644 index 9238a91fd70efe73be3e14aa0a285410e6a9e6fc..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 1560 zcmV+z2Iu*SP)Q7H%2QdEXH`{A+uPP+1w#~5Q5272 z$3S_S&*z5#?zXovkhDUm~=XOnGbx?Lqz zSu%A!i{Ez%ZhK|m>eAlHWK&TT(pN5WiZye$0ek}B5WstpWAQ5VXi>M0R7TBx_efp0 zH?&?AXCuvxq^aizrE~lJ;%C|I0NJeq(SD*bef8QLi;GzM_A@;uSsONeGr-#b9s>9Sz*7KUp-G|u z@5!&coBEA7XTR98lW{Q$s_Xj2s7N$AYHySM-1pwLtVtsA)xM~lsIP3=u&Kw;8vs5A z@FjqE06Yh9>*}*xvYjX`swC%X)adKdI<{o)k=pL>;&OG7XneP?TUJ%Bua1!Ycye;` zCV(dZc5wYRk#6$*#kf&NE-o%&HN7O2WD+WlRF2oBpqE;*(Wp;3%*J;Ud0+pyI409J zMYguKexFXK_tC5Z^*Nf$`u1qF&$j@c88_^}`uh4xtXf531Wlx>OM72ZoIn!Mz04L} zlKXD6$DaVcyL!EaCaFFEunFK_052={eT+zxO>1ksT}$pH^V<|6x%z0sMV+>F3`wG% z`ujID6HO1%j7~oT@CAT7=ufIEM`wLcAG6x7zUJ9|jA`ils=3YJw*{MQYM;2GQEB^9 zQ?|YPnJkWOJEDDU?~9t$X>w0gwV&*mOpiggZyb3B;A;Ti0C*qGBT%~lUPbd56q73Y z*Z1_5R8`Mq>JU9UYTB-C9Vv41_|sx$SoCU_>Fy(|M^(S74p|wUdQB&dT*RuopK61K30J7}Q4qegyE3&qm3N%ZKz=5!WN7ke&nh3C(@fI{=R3hLb+kI;M;F zKGzu4T@zGyeO1-**sL*{O7c(U9%(96m&&yx`M4D29N+}k)`EKgpf$|+oO2-N$l1PcjT!?Q8rE=+n3w`0UZnK(W^ zM%}+2X|hsUkCgHuTaR>UL|T^R*?c}fJUTiG7ae7(EX%XlF%YF-DUnuHH3e{2P?m@c zgjnA*rFK^t?~xLD5-VvjS%$}1dm^HNm`I6;24W&5A{vN^l!#~`PBziXIzK z24&>(@=~~+iIi4SUDt;x{UuS#M_HEB*f9_h5fKp)5fKp)rR0AKQ#4KZjyAdg0000< KMNUMnLSTaH2jnLJ diff --git a/DOCS/html/group___peripheral__declaration.html b/DOCS/html/group___peripheral__declaration.html deleted file mode 100644 index b28c169..0000000 --- a/DOCS/html/group___peripheral__declaration.html +++ /dev/null @@ -1,1446 +0,0 @@ - - - - - - - -STM MATLAB Simulator: Peripheral_declaration - - - - - - - - - - - -
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    CMSIS_Device » Stm32f407xx » Peripheral_memory_map
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    -Macros

    #define TIM2   ((TIM_TypeDef *) TIM2_BASE)
     
    #define TIM3   ((TIM_TypeDef *) TIM3_BASE)
     
    #define TIM4   ((TIM_TypeDef *) TIM4_BASE)
     
    #define TIM5   ((TIM_TypeDef *) TIM5_BASE)
     
    #define TIM6   ((TIM_TypeDef *) TIM6_BASE)
     
    #define TIM7   ((TIM_TypeDef *) TIM7_BASE)
     
    #define TIM12   ((TIM_TypeDef *) TIM12_BASE)
     
    #define TIM13   ((TIM_TypeDef *) TIM13_BASE)
     
    #define TIM14   ((TIM_TypeDef *) TIM14_BASE)
     
    #define RTC   ((RTC_TypeDef *) RTC_BASE)
     
    #define WWDG   ((WWDG_TypeDef *) WWDG_BASE)
     
    #define IWDG   ((IWDG_TypeDef *) IWDG_BASE)
     
    #define I2S2ext   ((SPI_TypeDef *) I2S2ext_BASE)
     
    #define SPI2   ((SPI_TypeDef *) SPI2_BASE)
     
    #define SPI3   ((SPI_TypeDef *) SPI3_BASE)
     
    #define I2S3ext   ((SPI_TypeDef *) I2S3ext_BASE)
     
    #define USART2   ((USART_TypeDef *) USART2_BASE)
     
    #define USART3   ((USART_TypeDef *) USART3_BASE)
     
    #define UART4   ((USART_TypeDef *) UART4_BASE)
     
    #define UART5   ((USART_TypeDef *) UART5_BASE)
     
    #define I2C1   ((I2C_TypeDef *) I2C1_BASE)
     
    #define I2C2   ((I2C_TypeDef *) I2C2_BASE)
     
    #define I2C3   ((I2C_TypeDef *) I2C3_BASE)
     
    #define CAN1   ((CAN_TypeDef *) CAN1_BASE)
     
    #define CAN2   ((CAN_TypeDef *) CAN2_BASE)
     
    #define PWR   ((PWR_TypeDef *) PWR_BASE)
     
    #define DAC1   ((DAC_TypeDef *) DAC_BASE)
     
    #define DAC   ((DAC_TypeDef *) DAC_BASE) /* Kept for legacy purpose */
     
    #define TIM1   ((TIM_TypeDef *) TIM1_BASE)
     
    #define TIM8   ((TIM_TypeDef *) TIM8_BASE)
     
    #define USART1   ((USART_TypeDef *) USART1_BASE)
     
    #define USART6   ((USART_TypeDef *) USART6_BASE)
     
    #define ADC1   ((ADC_TypeDef *) ADC1_BASE)
     
    #define ADC2   ((ADC_TypeDef *) ADC2_BASE)
     
    #define ADC3   ((ADC_TypeDef *) ADC3_BASE)
     
    #define ADC123_COMMON   ((ADC_Common_TypeDef *) ADC123_COMMON_BASE)
     
    #define ADC   ADC123_COMMON
     
    #define SDIO   ((SDIO_TypeDef *) SDIO_BASE)
     
    #define SPI1   ((SPI_TypeDef *) SPI1_BASE)
     
    #define SYSCFG   ((SYSCFG_TypeDef *) SYSCFG_BASE)
     
    #define EXTI   ((EXTI_TypeDef *) EXTI_BASE)
     
    #define TIM9   ((TIM_TypeDef *) TIM9_BASE)
     
    #define TIM10   ((TIM_TypeDef *) TIM10_BASE)
     
    #define TIM11   ((TIM_TypeDef *) TIM11_BASE)
     
    #define GPIOA   ((GPIO_TypeDef *) GPIOA_BASE)
     
    #define GPIOB   ((GPIO_TypeDef *) GPIOB_BASE)
     
    #define GPIOC   ((GPIO_TypeDef *) GPIOC_BASE)
     
    #define GPIOD   ((GPIO_TypeDef *) GPIOD_BASE)
     
    #define GPIOE   ((GPIO_TypeDef *) GPIOE_BASE)
     
    #define GPIOF   ((GPIO_TypeDef *) GPIOF_BASE)
     
    #define GPIOG   ((GPIO_TypeDef *) GPIOG_BASE)
     
    #define GPIOH   ((GPIO_TypeDef *) GPIOH_BASE)
     
    #define GPIOI   ((GPIO_TypeDef *) GPIOI_BASE)
     
    #define CRC   ((CRC_TypeDef *) CRC_BASE)
     
    #define RCC   ((RCC_TypeDef *) RCC_BASE)
     
    #define FLASH   ((FLASH_TypeDef *) FLASH_R_BASE)
     
    #define DMA1   ((DMA_TypeDef *) DMA1_BASE)
     
    #define DMA1_Stream0   ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
     
    #define DMA1_Stream1   ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
     
    #define DMA1_Stream2   ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
     
    #define DMA1_Stream3   ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
     
    #define DMA1_Stream4   ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
     
    #define DMA1_Stream5   ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
     
    #define DMA1_Stream6   ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
     
    #define DMA1_Stream7   ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
     
    #define DMA2   ((DMA_TypeDef *) DMA2_BASE)
     
    #define DMA2_Stream0   ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
     
    #define DMA2_Stream1   ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
     
    #define DMA2_Stream2   ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
     
    #define DMA2_Stream3   ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
     
    #define DMA2_Stream4   ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
     
    #define DMA2_Stream5   ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
     
    #define DMA2_Stream6   ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
     
    #define DMA2_Stream7   ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
     
    #define ETH   ((ETH_TypeDef *) ETH_BASE)
     
    #define DCMI   ((DCMI_TypeDef *) DCMI_BASE)
     
    #define RNG   ((RNG_TypeDef *) RNG_BASE)
     
    #define FSMC_Bank1   ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE)
     
    #define FSMC_Bank1E   ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE)
     
    #define FSMC_Bank2_3   ((FSMC_Bank2_3_TypeDef *) FSMC_Bank2_3_R_BASE)
     
    #define FSMC_Bank4   ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE)
     
    #define DBGMCU   ((DBGMCU_TypeDef *) DBGMCU_BASE)
     
    #define USB_OTG_FS   ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
     
    #define USB_OTG_HS   ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE)
     
    -

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    ◆ TIM2

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    ◆ RTC

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    ◆ I2S2ext

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    #define I2S2ext   ((SPI_TypeDef *) I2S2ext_BASE)
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    ◆ SPI2

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    #define SPI2   ((SPI_TypeDef *) SPI2_BASE)
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    ◆ SPI3

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    ◆ I2S3ext

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    ◆ USART3

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    ◆ ETH

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    ◆ RNG

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    ◆ FSMC_Bank1

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    ◆ FSMC_Bank1E

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    #define FSMC_Bank1E   ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE)
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    ◆ FSMC_Bank2_3

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    ◆ DBGMCU

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    ◆ USB_OTG_FS

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    #define USB_OTG_FS   ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
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    ◆ USB_OTG_HS

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    #define USB_OTG_HS   ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE)
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    -Generated by doxygen 1.10.0 -
    - - diff --git a/DOCS/html/group___peripheral__declaration.map b/DOCS/html/group___peripheral__declaration.map deleted file mode 100644 index 2f47c10..0000000 --- a/DOCS/html/group___peripheral__declaration.map +++ /dev/null @@ -1,4 +0,0 @@ - - - - diff --git a/DOCS/html/group___peripheral__declaration.md5 b/DOCS/html/group___peripheral__declaration.md5 deleted file mode 100644 index 2a81505..0000000 --- a/DOCS/html/group___peripheral__declaration.md5 +++ /dev/null @@ -1 +0,0 @@ -da86f513d53ae34137098cb49f148598 \ No newline at end of file diff --git a/DOCS/html/group___peripheral__declaration.png b/DOCS/html/group___peripheral__declaration.png deleted file mode 100644 index 8ef6522980768ac59d34636203d5980b737dbf64..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 1234 zcmV;@1TFiCP)@7P`t|Ww55JEim7Z#DS>j0jF4#EV#Q{=*6FjxU_b#K{NQXk2(%y~dW zs?szK9YSNBP6xBIv!TPFNNjFyqTlb2l_vpWAtEA2nAC}gBEqCjL=+Jwbt0mOFsTy} zMTAM6h$tdflDZJ0^3|k2oAsLTF$Otx48RQl{{uJ|I2L7TnpVD=^k=hP6Q*O>h^@`X zXNz>5x~@FW$I65dmE|UV5otIG;7*|{BQytItyz(e{nzq#`uiEcwp4>&hPH&W!`Cdt)GhUlxncy zcvaI3p<Z63RciW_`YCE0r%Kf`evQ5r~i+*gGbRJDUM-6Mk*L?sN zQLItFg5u$$ABb@IZh4+rcfNhpR<)hZc;)_05@B7tx>!`>)QNFYUD-{}CZCb1vFz3D zcCQH`9*15)KjQ1ka=!?5KAVo4rYZ6~zuxQhbmpdy0Jwx=-TGeu{y?DVm!+kpye&VH zVQZBIg*E(`mkpKVy07*qoM6N<$f*rI~1ONa4 diff --git a/DOCS/html/group___peripheral__interrupt__number__definition.html b/DOCS/html/group___peripheral__interrupt__number__definition.html deleted file mode 100644 index 2fd9647..0000000 --- a/DOCS/html/group___peripheral__interrupt__number__definition.html +++ /dev/null @@ -1,522 +0,0 @@ - - - - - - - -STM MATLAB Simulator: Peripheral_interrupt_number_definition - - - - - - - - - - - -
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    Peripheral_interrupt_number_definition
    CMSIS_Device » Stm32f407xx
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    - + Collaboration diagram for Peripheral_interrupt_number_definition:
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    -Macros

    #define HASH_RNG_IRQn   RNG_IRQn
     
    - - - - -

    -Enumerations

    enum  IRQn_Type {
    -  NonMaskableInt_IRQn = -14 -, MemoryManagement_IRQn = -12 -, BusFault_IRQn = -11 -, UsageFault_IRQn = -10 -,
    -  SVCall_IRQn = -5 -, DebugMonitor_IRQn = -4 -, PendSV_IRQn = -2 -, SysTick_IRQn = -1 -,
    -  WWDG_IRQn = 0 -, PVD_IRQn = 1 -, TAMP_STAMP_IRQn = 2 -, RTC_WKUP_IRQn = 3 -,
    -  FLASH_IRQn = 4 -, RCC_IRQn = 5 -, EXTI0_IRQn = 6 -, EXTI1_IRQn = 7 -,
    -  EXTI2_IRQn = 8 -, EXTI3_IRQn = 9 -, EXTI4_IRQn = 10 -, DMA1_Stream0_IRQn = 11 -,
    -  DMA1_Stream1_IRQn = 12 -, DMA1_Stream2_IRQn = 13 -, DMA1_Stream3_IRQn = 14 -, DMA1_Stream4_IRQn = 15 -,
    -  DMA1_Stream5_IRQn = 16 -, DMA1_Stream6_IRQn = 17 -, ADC_IRQn = 18 -, CAN1_TX_IRQn = 19 -,
    -  CAN1_RX0_IRQn = 20 -, CAN1_RX1_IRQn = 21 -, CAN1_SCE_IRQn = 22 -, EXTI9_5_IRQn = 23 -,
    -  TIM1_BRK_TIM9_IRQn = 24 -, TIM1_UP_TIM10_IRQn = 25 -, TIM1_TRG_COM_TIM11_IRQn = 26 -, TIM1_CC_IRQn = 27 -,
    -  TIM2_IRQn = 28 -, TIM3_IRQn = 29 -, TIM4_IRQn = 30 -, I2C1_EV_IRQn = 31 -,
    -  I2C1_ER_IRQn = 32 -, I2C2_EV_IRQn = 33 -, I2C2_ER_IRQn = 34 -, SPI1_IRQn = 35 -,
    -  SPI2_IRQn = 36 -, USART1_IRQn = 37 -, USART2_IRQn = 38 -, USART3_IRQn = 39 -,
    -  EXTI15_10_IRQn = 40 -, RTC_Alarm_IRQn = 41 -, OTG_FS_WKUP_IRQn = 42 -, TIM8_BRK_TIM12_IRQn = 43 -,
    -  TIM8_UP_TIM13_IRQn = 44 -, TIM8_TRG_COM_TIM14_IRQn = 45 -, TIM8_CC_IRQn = 46 -, DMA1_Stream7_IRQn = 47 -,
    -  FSMC_IRQn = 48 -, SDIO_IRQn = 49 -, TIM5_IRQn = 50 -, SPI3_IRQn = 51 -,
    -  UART4_IRQn = 52 -, UART5_IRQn = 53 -, TIM6_DAC_IRQn = 54 -, TIM7_IRQn = 55 -,
    -  DMA2_Stream0_IRQn = 56 -, DMA2_Stream1_IRQn = 57 -, DMA2_Stream2_IRQn = 58 -, DMA2_Stream3_IRQn = 59 -,
    -  DMA2_Stream4_IRQn = 60 -, ETH_IRQn = 61 -, ETH_WKUP_IRQn = 62 -, CAN2_TX_IRQn = 63 -,
    -  CAN2_RX0_IRQn = 64 -, CAN2_RX1_IRQn = 65 -, CAN2_SCE_IRQn = 66 -, OTG_FS_IRQn = 67 -,
    -  DMA2_Stream5_IRQn = 68 -, DMA2_Stream6_IRQn = 69 -, DMA2_Stream7_IRQn = 70 -, USART6_IRQn = 71 -,
    -  I2C3_EV_IRQn = 72 -, I2C3_ER_IRQn = 73 -, OTG_HS_EP1_OUT_IRQn = 74 -, OTG_HS_EP1_IN_IRQn = 75 -,
    -  OTG_HS_WKUP_IRQn = 76 -, OTG_HS_IRQn = 77 -, DCMI_IRQn = 78 -, RNG_IRQn = 80 -,
    -  FPU_IRQn = 81 -
    - }
     STM32F4XX Interrupt Number Definition, according to the selected device in Library_configuration_section. More...
     
    -

    Detailed Description

    -

    Macro Definition Documentation

    - -

    ◆ HASH_RNG_IRQn

    - -
    -
    - - - - -
    #define HASH_RNG_IRQn   RNG_IRQn
    -
    - -
    -
    -

    Enumeration Type Documentation

    - -

    ◆ IRQn_Type

    - -
    -
    - - - - -
    enum IRQn_Type
    -
    - -

    STM32F4XX Interrupt Number Definition, according to the selected device in Library_configuration_section.

    - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
    Enumerator
    NonMaskableInt_IRQn 

    2 Non Maskable Interrupt
    -

    -
    MemoryManagement_IRQn 

    4 Cortex-M4 Memory Management Interrupt
    -

    -
    BusFault_IRQn 

    5 Cortex-M4 Bus Fault Interrupt
    -

    -
    UsageFault_IRQn 

    6 Cortex-M4 Usage Fault Interrupt
    -

    -
    SVCall_IRQn 

    11 Cortex-M4 SV Call Interrupt
    -

    -
    DebugMonitor_IRQn 

    12 Cortex-M4 Debug Monitor Interrupt
    -

    -
    PendSV_IRQn 

    14 Cortex-M4 Pend SV Interrupt
    -

    -
    SysTick_IRQn 

    15 Cortex-M4 System Tick Interrupt
    -

    -
    WWDG_IRQn 

    Window WatchDog Interrupt
    -

    -
    PVD_IRQn 

    PVD through EXTI Line detection Interrupt
    -

    -
    TAMP_STAMP_IRQn 

    Tamper and TimeStamp interrupts through the EXTI line
    -

    -
    RTC_WKUP_IRQn 

    RTC Wakeup interrupt through the EXTI line
    -

    -
    FLASH_IRQn 

    FLASH global Interrupt
    -

    -
    RCC_IRQn 

    RCC global Interrupt
    -

    -
    EXTI0_IRQn 

    EXTI Line0 Interrupt
    -

    -
    EXTI1_IRQn 

    EXTI Line1 Interrupt
    -

    -
    EXTI2_IRQn 

    EXTI Line2 Interrupt
    -

    -
    EXTI3_IRQn 

    EXTI Line3 Interrupt
    -

    -
    EXTI4_IRQn 

    EXTI Line4 Interrupt
    -

    -
    DMA1_Stream0_IRQn 

    DMA1 Stream 0 global Interrupt
    -

    -
    DMA1_Stream1_IRQn 

    DMA1 Stream 1 global Interrupt
    -

    -
    DMA1_Stream2_IRQn 

    DMA1 Stream 2 global Interrupt
    -

    -
    DMA1_Stream3_IRQn 

    DMA1 Stream 3 global Interrupt
    -

    -
    DMA1_Stream4_IRQn 

    DMA1 Stream 4 global Interrupt
    -

    -
    DMA1_Stream5_IRQn 

    DMA1 Stream 5 global Interrupt
    -

    -
    DMA1_Stream6_IRQn 

    DMA1 Stream 6 global Interrupt
    -

    -
    ADC_IRQn 

    ADC1, ADC2 and ADC3 global Interrupts
    -

    -
    CAN1_TX_IRQn 

    CAN1 TX Interrupt
    -

    -
    CAN1_RX0_IRQn 

    CAN1 RX0 Interrupt
    -

    -
    CAN1_RX1_IRQn 

    CAN1 RX1 Interrupt
    -

    -
    CAN1_SCE_IRQn 

    CAN1 SCE Interrupt
    -

    -
    EXTI9_5_IRQn 

    External Line[9:5] Interrupts
    -

    -
    TIM1_BRK_TIM9_IRQn 

    TIM1 Break interrupt and TIM9 global interrupt
    -

    -
    TIM1_UP_TIM10_IRQn 

    TIM1 Update Interrupt and TIM10 global interrupt
    -

    -
    TIM1_TRG_COM_TIM11_IRQn 

    TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt

    -
    TIM1_CC_IRQn 

    TIM1 Capture Compare Interrupt
    -

    -
    TIM2_IRQn 

    TIM2 global Interrupt
    -

    -
    TIM3_IRQn 

    TIM3 global Interrupt
    -

    -
    TIM4_IRQn 

    TIM4 global Interrupt
    -

    -
    I2C1_EV_IRQn 

    I2C1 Event Interrupt
    -

    -
    I2C1_ER_IRQn 

    I2C1 Error Interrupt
    -

    -
    I2C2_EV_IRQn 

    I2C2 Event Interrupt
    -

    -
    I2C2_ER_IRQn 

    I2C2 Error Interrupt
    -

    -
    SPI1_IRQn 

    SPI1 global Interrupt
    -

    -
    SPI2_IRQn 

    SPI2 global Interrupt
    -

    -
    USART1_IRQn 

    USART1 global Interrupt
    -

    -
    USART2_IRQn 

    USART2 global Interrupt
    -

    -
    USART3_IRQn 

    USART3 global Interrupt
    -

    -
    EXTI15_10_IRQn 

    External Line[15:10] Interrupts
    -

    -
    RTC_Alarm_IRQn 

    RTC Alarm (A and B) through EXTI Line Interrupt
    -

    -
    OTG_FS_WKUP_IRQn 

    USB OTG FS Wakeup through EXTI line interrupt
    -

    -
    TIM8_BRK_TIM12_IRQn 

    TIM8 Break Interrupt and TIM12 global interrupt
    -

    -
    TIM8_UP_TIM13_IRQn 

    TIM8 Update Interrupt and TIM13 global interrupt
    -

    -
    TIM8_TRG_COM_TIM14_IRQn 

    TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt

    -
    TIM8_CC_IRQn 

    TIM8 Capture Compare global interrupt
    -

    -
    DMA1_Stream7_IRQn 

    DMA1 Stream7 Interrupt
    -

    -
    FSMC_IRQn 

    FSMC global Interrupt
    -

    -
    SDIO_IRQn 

    SDIO global Interrupt
    -

    -
    TIM5_IRQn 

    TIM5 global Interrupt
    -

    -
    SPI3_IRQn 

    SPI3 global Interrupt
    -

    -
    UART4_IRQn 

    UART4 global Interrupt
    -

    -
    UART5_IRQn 

    UART5 global Interrupt
    -

    -
    TIM6_DAC_IRQn 

    TIM6 global and DAC1&2 underrun error interrupts
    -

    -
    TIM7_IRQn 

    TIM7 global interrupt
    -

    -
    DMA2_Stream0_IRQn 

    DMA2 Stream 0 global Interrupt
    -

    -
    DMA2_Stream1_IRQn 

    DMA2 Stream 1 global Interrupt
    -

    -
    DMA2_Stream2_IRQn 

    DMA2 Stream 2 global Interrupt
    -

    -
    DMA2_Stream3_IRQn 

    DMA2 Stream 3 global Interrupt
    -

    -
    DMA2_Stream4_IRQn 

    DMA2 Stream 4 global Interrupt
    -

    -
    ETH_IRQn 

    Ethernet global Interrupt
    -

    -
    ETH_WKUP_IRQn 

    Ethernet Wakeup through EXTI line Interrupt
    -

    -
    CAN2_TX_IRQn 

    CAN2 TX Interrupt
    -

    -
    CAN2_RX0_IRQn 

    CAN2 RX0 Interrupt
    -

    -
    CAN2_RX1_IRQn 

    CAN2 RX1 Interrupt
    -

    -
    CAN2_SCE_IRQn 

    CAN2 SCE Interrupt
    -

    -
    OTG_FS_IRQn 

    USB OTG FS global Interrupt
    -

    -
    DMA2_Stream5_IRQn 

    DMA2 Stream 5 global interrupt
    -

    -
    DMA2_Stream6_IRQn 

    DMA2 Stream 6 global interrupt
    -

    -
    DMA2_Stream7_IRQn 

    DMA2 Stream 7 global interrupt
    -

    -
    USART6_IRQn 

    USART6 global interrupt
    -

    -
    I2C3_EV_IRQn 

    I2C3 event interrupt
    -

    -
    I2C3_ER_IRQn 

    I2C3 error interrupt
    -

    -
    OTG_HS_EP1_OUT_IRQn 

    USB OTG HS End Point 1 Out global interrupt
    -

    -
    OTG_HS_EP1_IN_IRQn 

    USB OTG HS End Point 1 In global interrupt
    -

    -
    OTG_HS_WKUP_IRQn 

    USB OTG HS Wakeup through EXTI interrupt
    -

    -
    OTG_HS_IRQn 

    USB OTG HS global interrupt
    -

    -
    DCMI_IRQn 

    DCMI global interrupt
    -

    -
    RNG_IRQn 

    RNG global Interrupt
    -

    -
    FPU_IRQn 

    FPU global interrupt
    -

    -
    - -
    -
    -
    - -
    -Generated by doxygen 1.10.0 -
    - - diff --git a/DOCS/html/group___peripheral__interrupt__number__definition.map b/DOCS/html/group___peripheral__interrupt__number__definition.map deleted file mode 100644 index 4c49d2c..0000000 --- a/DOCS/html/group___peripheral__interrupt__number__definition.map +++ /dev/null @@ -1,4 +0,0 @@ - - - - diff --git a/DOCS/html/group___peripheral__interrupt__number__definition.md5 b/DOCS/html/group___peripheral__interrupt__number__definition.md5 deleted file mode 100644 index ffdef2a..0000000 --- a/DOCS/html/group___peripheral__interrupt__number__definition.md5 +++ /dev/null @@ -1 +0,0 @@ -c125f89d82d19ad7f76ee701688b8fe1 \ No newline at end of file diff --git a/DOCS/html/group___peripheral__interrupt__number__definition.png b/DOCS/html/group___peripheral__interrupt__number__definition.png deleted file mode 100644 index a9780cd72bafc05429bfcf52b62db942b0a318f9..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 1454 zcmV;f1yTBmP)K~#90?cB|4Bt;ko@TVGgMIo0UB4kzOq6a;M2nu@_uPVCBiik=k z^DpSli(Wl9ldFf7ARaskdo^N6$Yn7I!9%=77%&+8oc1s?(&?$s?)sX}^MfHwS9jGr zP5Pbcs-6Ofh=_=Yh=_>jx)Z4bp#B;Thj&uPK=~<(;;byo{ra{?QUyc(Cxp14ItI$m zbUNJw@OFJ06A=Y97!0t!zMeV^%EamEDJGN2()J=jEJQ?CFcA?^a!f=-lpGTg5hce& zL`2Cg&6;g*Z{HF^+)fb;Evu^PyWQR0UsA_G6w*>65<=YO^B-Bc3*gJtLBuc`jilSl zvTR+S&9S!ob&*pnIZ{4HbRADdZd4a$pUM93+FqQi_&;nLa}Ej1XAB%8BBJD&h-l@E zMx*~<&F!+k&26flrmD=gJ>9;xY+{zR>k_B#JavtsE&jxVR!Z}B!1P{qtnN75{ap8L zLsoxTmd@v)OKi3=biqVKS&@Ciy8N^2_HA2c+g^w<8((!c>+y9?ePJS^tk}*h#pKdn z$_a*5p4?y}qLmYSwy5n)R_w%(dKRq>nkIlD#nk=FK7K5bq_ic`~JI!J{%732qEsf zR30)BxwL27<{}a4_Otm+p^Zi(R8@6%JRa+wtbPf=djQ@AunypF%#zZ=%K#3-MX9#4 zvs2}=Fj@`|0Ink6=WV_)+TM6Pj<-T%{X$>-ZC?Dcq)>m~maI)#yRLPb5|%CzdQ4(3 zV7AoehX9@i@E3ra^RgSNgNSnFB@s0*?B>O0dmB|hR(27q>es~-y7y9Vr`evatc7O* zybfT9St6<@pPQB@SD$;tg_Z7Ghk;B;_EouE*20H?+CA`P0F{!94)? zFdGYc9>AXf9<{9EV*sbE8t-UhW8+$^8bI9zoi&Tarv3Vuk;`#5``OImbv#Eu1NdzI zT8s~U0N@#1y+xCGfJB4UYinyMnxz$#{f}NvgUYrS_+l!)J|&;&G`z_}0H0tsX7nO} z&jI{8FZ(A^Oudof`5)J3p@9Cl3L91mGzEuL1Z1!0!MmFe&v;{RgLj+p|#hI#gvTdFv51dmOTX=;n-4vt0FF zRj;f~T^pwMbg{eCV^ikYzW}}k@IHVi0K5g@8_dR%h_aXctrme@P;hdm>S{=%@yoW3;WJT#smLYb#n1 zBzJUlWV0SowsKmJi1J{)9#K&gXVd9)@9^+2UUZ~X6vbKU7>Gh!N -STM MATLAB Simulator: Peripheral_memory_map +STM MATLAB Simulator: Peripheral Memory Map @@ -14,6 +14,7 @@ + @@ -72,38 +73,25 @@ $(function() {
    -Topics | Data Structures | Macros | Typedefs | Variables
    -
    Peripheral_memory_map
    CMSIS_Device » Stm32f407xx
    +
    Peripheral Memory Map
    Core Definitions
    - + Collaboration diagram for Peripheral_memory_map:
    + + Collaboration diagram for Peripheral Memory Map:
    - - - - - - - -

    -Topics

     Peripheral_declaration
     
     Exported_constants
     
     Exported_macros
     
    @@ -165,6 +153,8 @@ Macros + + @@ -195,222 +185,8 @@ Macros - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

    Data Structures

    struct  _memory
     
    #define FSMC_R_SIZE   (MCU_MEM_END - FSMC_R_BASE_SHIFT)
     
    #define DEBUG_MCU_SIZE   (2)
     
    #define FLASH_BASE   (MCU_MEM.CCMDATARAM_BASE)
     
    #define CCMDATARAM_BASE   (MCU_MEM.CCMDATARAM_BASE)
     
    #define CCMDATARAM_END   (MCU_MEM.CCMDATARAM_END)
     
    #define SRAM_BASE   SRAM1_BASE
     
    #define SRAM_BB_BASE   SRAM1_BB_BASE
     
    #define APB1PERIPH_BASE   PERIPH_BASE
     
    #define APB2PERIPH_BASE   (PERIPH_BASE + 0x00010000UL)
     
    #define AHB1PERIPH_BASE   (PERIPH_BASE + 0x00020000UL)
     
    #define AHB2PERIPH_BASE   (PERIPH_BASE + 0x10000000UL)
     
    #define TIM2_BASE   (APB1PERIPH_BASE + 0x0000UL)
     
    #define TIM3_BASE   (APB1PERIPH_BASE + 0x0400UL)
     
    #define TIM4_BASE   (APB1PERIPH_BASE + 0x0800UL)
     
    #define TIM5_BASE   (APB1PERIPH_BASE + 0x0C00UL)
     
    #define TIM6_BASE   (APB1PERIPH_BASE + 0x1000UL)
     
    #define TIM7_BASE   (APB1PERIPH_BASE + 0x1400UL)
     
    #define TIM12_BASE   (APB1PERIPH_BASE + 0x1800UL)
     
    #define TIM13_BASE   (APB1PERIPH_BASE + 0x1C00UL)
     
    #define TIM14_BASE   (APB1PERIPH_BASE + 0x2000UL)
     
    #define RTC_BASE   (APB1PERIPH_BASE + 0x2800UL)
     
    #define WWDG_BASE   (APB1PERIPH_BASE + 0x2C00UL)
     
    #define IWDG_BASE   (APB1PERIPH_BASE + 0x3000UL)
     
    #define I2S2ext_BASE   (APB1PERIPH_BASE + 0x3400UL)
     
    #define SPI2_BASE   (APB1PERIPH_BASE + 0x3800UL)
     
    #define SPI3_BASE   (APB1PERIPH_BASE + 0x3C00UL)
     
    #define I2S3ext_BASE   (APB1PERIPH_BASE + 0x4000UL)
     
    #define USART2_BASE   (APB1PERIPH_BASE + 0x4400UL)
     
    #define USART3_BASE   (APB1PERIPH_BASE + 0x4800UL)
     
    #define UART4_BASE   (APB1PERIPH_BASE + 0x4C00UL)
     
    #define UART5_BASE   (APB1PERIPH_BASE + 0x5000UL)
     
    #define I2C1_BASE   (APB1PERIPH_BASE + 0x5400UL)
     
    #define I2C2_BASE   (APB1PERIPH_BASE + 0x5800UL)
     
    #define I2C3_BASE   (APB1PERIPH_BASE + 0x5C00UL)
     
    #define CAN1_BASE   (APB1PERIPH_BASE + 0x6400UL)
     
    #define CAN2_BASE   (APB1PERIPH_BASE + 0x6800UL)
     
    #define PWR_BASE   (APB1PERIPH_BASE + 0x7000UL)
     
    #define DAC_BASE   (APB1PERIPH_BASE + 0x7400UL)
     
    #define TIM1_BASE   (APB2PERIPH_BASE + 0x0000UL)
     
    #define TIM8_BASE   (APB2PERIPH_BASE + 0x0400UL)
     
    #define USART1_BASE   (APB2PERIPH_BASE + 0x1000UL)
     
    #define USART6_BASE   (APB2PERIPH_BASE + 0x1400UL)
     
    #define ADC1_BASE   (APB2PERIPH_BASE + 0x2000UL)
     
    #define ADC2_BASE   (APB2PERIPH_BASE + 0x2100UL)
     
    #define ADC3_BASE   (APB2PERIPH_BASE + 0x2200UL)
     
    #define ADC123_COMMON_BASE   (APB2PERIPH_BASE + 0x2300UL)
     
    #define ADC_BASE   ADC123_COMMON_BASE
     
    #define SDIO_BASE   (APB2PERIPH_BASE + 0x2C00UL)
     
    #define SPI1_BASE   (APB2PERIPH_BASE + 0x3000UL)
     
    #define SYSCFG_BASE   (APB2PERIPH_BASE + 0x3800UL)
     
    #define EXTI_BASE   (APB2PERIPH_BASE + 0x3C00UL)
     
    #define TIM9_BASE   (APB2PERIPH_BASE + 0x4000UL)
     
    #define TIM10_BASE   (APB2PERIPH_BASE + 0x4400UL)
     
    #define TIM11_BASE   (APB2PERIPH_BASE + 0x4800UL)
     
    #define GPIOA_BASE   (AHB1PERIPH_BASE + 0x0000UL)
     
    #define GPIOB_BASE   (AHB1PERIPH_BASE + 0x0400UL)
     
    #define GPIOC_BASE   (AHB1PERIPH_BASE + 0x0800UL)
     
    #define GPIOD_BASE   (AHB1PERIPH_BASE + 0x0C00UL)
     
    #define GPIOE_BASE   (AHB1PERIPH_BASE + 0x1000UL)
     
    #define GPIOF_BASE   (AHB1PERIPH_BASE + 0x1400UL)
     
    #define GPIOG_BASE   (AHB1PERIPH_BASE + 0x1800UL)
     
    #define GPIOH_BASE   (AHB1PERIPH_BASE + 0x1C00UL)
     
    #define GPIOI_BASE   (AHB1PERIPH_BASE + 0x2000UL)
     
    #define CRC_BASE   (AHB1PERIPH_BASE + 0x3000UL)
     
    #define RCC_BASE   (AHB1PERIPH_BASE + 0x3800UL)
     
    #define FLASH_R_BASE   (AHB1PERIPH_BASE + 0x3C00UL)
     
    #define DMA1_BASE   (AHB1PERIPH_BASE + 0x6000UL)
     
    #define DMA1_Stream0_BASE   (DMA1_BASE + 0x010UL)
     
    #define DMA1_Stream1_BASE   (DMA1_BASE + 0x028UL)
     
    #define DMA1_Stream2_BASE   (DMA1_BASE + 0x040UL)
     
    #define DMA1_Stream3_BASE   (DMA1_BASE + 0x058UL)
     
    #define DMA1_Stream4_BASE   (DMA1_BASE + 0x070UL)
     
    #define DMA1_Stream5_BASE   (DMA1_BASE + 0x088UL)
     
    #define DMA1_Stream6_BASE   (DMA1_BASE + 0x0A0UL)
     
    #define DMA1_Stream7_BASE   (DMA1_BASE + 0x0B8UL)
     
    #define DMA2_BASE   (AHB1PERIPH_BASE + 0x6400UL)
     
    #define DMA2_Stream0_BASE   (DMA2_BASE + 0x010UL)
     
    #define DMA2_Stream1_BASE   (DMA2_BASE + 0x028UL)
     
    #define DMA2_Stream2_BASE   (DMA2_BASE + 0x040UL)
     
    #define DMA2_Stream3_BASE   (DMA2_BASE + 0x058UL)
     
    #define DMA2_Stream4_BASE   (DMA2_BASE + 0x070UL)
     
    #define DMA2_Stream5_BASE   (DMA2_BASE + 0x088UL)
     
    #define DMA2_Stream6_BASE   (DMA2_BASE + 0x0A0UL)
     
    #define DMA2_Stream7_BASE   (DMA2_BASE + 0x0B8UL)
     
    #define ETH_BASE   (AHB1PERIPH_BASE + 0x8000UL)
     
    #define ETH_MAC_BASE   (ETH_BASE)
     
    #define ETH_MMC_BASE   (ETH_BASE + 0x0100UL)
     
    #define ETH_PTP_BASE   (ETH_BASE + 0x0700UL)
     
    #define ETH_DMA_BASE   (ETH_BASE + 0x1000UL)
     
    #define DCMI_BASE   (AHB2PERIPH_BASE + 0x50000UL)
     
    #define RNG_BASE   (AHB2PERIPH_BASE + 0x60800UL)
     
    #define FSMC_Bank1_R_BASE   (FSMC_R_BASE + 0x0000UL)
     
    #define FSMC_Bank1E_R_BASE   (FSMC_R_BASE + 0x0104UL)
     
    #define FSMC_Bank2_3_R_BASE   (FSMC_R_BASE + 0x0060UL)
     
    #define FSMC_Bank4_R_BASE   (FSMC_R_BASE + 0x00A0UL)
     
    #define DBGMCU_BASE   (&DEBUG_MCU)
    #define DBGMCU_BASE   (MCU_MEM.DEBUG_MCU_BASE)
     
    #define USB_OTG_HS_PERIPH_BASE   0x40040000UL
     
    #define USB_OTG_FS_PERIPH_BASE   0x50000000UL
     
    #define USB_OTG_GLOBAL_BASE   0x000UL
     
    #define USB_OTG_DEVICE_BASE   0x800UL
     
    #define USB_OTG_IN_ENDPOINT_BASE   0x900UL
     
    #define USB_OTG_OUT_ENDPOINT_BASE   0xB00UL
     
    #define USB_OTG_EP_REG_SIZE   0x20UL
     
    #define USB_OTG_HOST_BASE   0x400UL
     
    #define USB_OTG_HOST_PORT_BASE   0x440UL
     
    #define USB_OTG_HOST_CHANNEL_BASE   0x500UL
     
    #define USB_OTG_HOST_CHANNEL_SIZE   0x20UL
     
    #define USB_OTG_PCGCCTL_BASE   0xE00UL
     
    #define USB_OTG_FIFO_BASE   0x1000UL
     
    #define USB_OTG_FIFO_SIZE   0x1000UL
     
    #define UID_BASE   0x1FFF7A10UL
     
    #define FLASHSIZE_BASE   0x1FFF7A22UL
     
    #define PACKAGE_BASE   0x1FFF7BF0UL
     
    @@ -421,8 +197,6 @@ Typedefs Variables - -

    Typedefs

    MCU_MemoryTypeDef MCU_MEM
     
    DBGMCU_TypeDef DEBUG_MCU
     

    Detailed Description

    Macro Definition Documentation

    @@ -437,9 +211,11 @@ Variables
    -

    FLASH(up to 1 MB) base address in the alias region
    +

    FLASH(up to 1 MB) base address in the alias region

    +

    Definition at line 68 of file stm32f407xx_matlab_memory.h.

    +
    @@ -456,6 +232,8 @@ Variables

    FLASH end address

    +

    Definition at line 69 of file stm32f407xx_matlab_memory.h.

    + @@ -472,6 +250,8 @@ Variables

    CCM(core coupled memory) data RAM(64 KB) base address in the alias region

    +

    Definition at line 70 of file stm32f407xx_matlab_memory.h.

    + @@ -488,6 +268,8 @@ Variables

    CCM data RAM end address

    +

    Definition at line 71 of file stm32f407xx_matlab_memory.h.

    + @@ -504,6 +286,8 @@ Variables

    Base address of : (up to 528 Bytes) embedded FLASH OTP Area

    +

    Definition at line 72 of file stm32f407xx_matlab_memory.h.

    + @@ -520,6 +304,8 @@ Variables

    End address of : (up to 528 Bytes) embedded FLASH OTP Area

    +

    Definition at line 73 of file stm32f407xx_matlab_memory.h.

    + @@ -536,6 +322,8 @@ Variables

    SRAM1(112 KB) base address in the alias region

    +

    Definition at line 74 of file stm32f407xx_matlab_memory.h.

    + @@ -552,6 +340,8 @@ Variables

    SRAM2(16 KB) base address in the alias region

    +

    Definition at line 75 of file stm32f407xx_matlab_memory.h.

    + @@ -568,6 +358,8 @@ Variables

    SRAM1(112 KB) base address in the bit-band region

    +

    Definition at line 76 of file stm32f407xx_matlab_memory.h.

    + @@ -584,6 +376,8 @@ Variables

    SRAM2(16 KB) base address in the bit-band region

    +

    Definition at line 77 of file stm32f407xx_matlab_memory.h.

    + @@ -600,6 +394,8 @@ Variables

    Peripheral base address in the alias region

    +

    Definition at line 78 of file stm32f407xx_matlab_memory.h.

    + @@ -616,6 +412,8 @@ Variables

    Backup SRAM(4 KB) base address in the alias region

    +

    Definition at line 79 of file stm32f407xx_matlab_memory.h.

    + @@ -632,6 +430,8 @@ Variables

    Peripheral base address in the bit-band region

    +

    Definition at line 80 of file stm32f407xx_matlab_memory.h.

    + @@ -648,6 +448,8 @@ Variables

    Backup SRAM(4 KB) base address in the bit-band region

    +

    Definition at line 81 of file stm32f407xx_matlab_memory.h.

    + @@ -664,6 +466,8 @@ Variables

    FSMC registers base address

    +

    Definition at line 82 of file stm32f407xx_matlab_memory.h.

    + @@ -680,6 +484,8 @@ Variables

    CCM data RAM end address

    +

    Definition at line 84 of file stm32f407xx_matlab_memory.h.

    + @@ -694,6 +500,8 @@ Variables
    +

    Definition at line 86 of file stm32f407xx_matlab_memory.h.

    +
    @@ -708,6 +516,8 @@ Variables
    +

    Definition at line 87 of file stm32f407xx_matlab_memory.h.

    +
    @@ -722,6 +532,8 @@ Variables
    +

    Definition at line 88 of file stm32f407xx_matlab_memory.h.

    +
    @@ -736,6 +548,8 @@ Variables
    +

    Definition at line 89 of file stm32f407xx_matlab_memory.h.

    +
    @@ -750,6 +564,8 @@ Variables
    +

    Definition at line 91 of file stm32f407xx_matlab_memory.h.

    +
    @@ -764,6 +580,8 @@ Variables
    +

    Definition at line 93 of file stm32f407xx_matlab_memory.h.

    +
    @@ -778,6 +596,8 @@ Variables
    +

    Definition at line 96 of file stm32f407xx_matlab_memory.h.

    +
    @@ -792,6 +612,8 @@ Variables
    +

    Definition at line 97 of file stm32f407xx_matlab_memory.h.

    +
    @@ -806,6 +628,8 @@ Variables
    +

    Definition at line 98 of file stm32f407xx_matlab_memory.h.

    +
    @@ -820,6 +644,8 @@ Variables
    +

    Definition at line 100 of file stm32f407xx_matlab_memory.h.

    +
    @@ -834,6 +660,24 @@ Variables
    +

    Definition at line 102 of file stm32f407xx_matlab_memory.h.

    + +
    + + +

    ◆ DEBUG_MCU_SIZE

    + +
    +
    + + + + +
    #define DEBUG_MCU_SIZE   (2)
    +
    + +

    Definition at line 103 of file stm32f407xx_matlab_memory.h.

    +
    @@ -847,9 +691,11 @@ Variables
    -

    FLASH(up to 1 MB) base address in the alias region
    +

    FLASH(up to 1 MB) base address in the alias region

    +

    Definition at line 126 of file stm32f407xx_matlab_memory.h.

    +
    @@ -866,6 +712,8 @@ Variables

    CCM(core coupled memory) data RAM(64 KB) base address in the alias region

    +

    Definition at line 127 of file stm32f407xx_matlab_memory.h.

    + @@ -882,6 +730,8 @@ Variables

    SRAM1(112 KB) base address in the alias region

    +

    Definition at line 128 of file stm32f407xx_matlab_memory.h.

    + @@ -898,6 +748,8 @@ Variables

    SRAM2(16 KB) base address in the alias region

    +

    Definition at line 129 of file stm32f407xx_matlab_memory.h.

    + @@ -914,6 +766,8 @@ Variables

    Peripheral base address in the alias region

    +

    Definition at line 130 of file stm32f407xx_matlab_memory.h.

    + @@ -930,6 +784,8 @@ Variables

    Backup SRAM(4 KB) base address in the alias region

    +

    Definition at line 131 of file stm32f407xx_matlab_memory.h.

    + @@ -946,6 +802,8 @@ Variables

    FSMC registers base address

    +

    Definition at line 132 of file stm32f407xx_matlab_memory.h.

    + @@ -962,6 +820,8 @@ Variables

    SRAM1(112 KB) base address in the bit-band region

    +

    Definition at line 133 of file stm32f407xx_matlab_memory.h.

    + @@ -978,6 +838,8 @@ Variables

    SRAM2(16 KB) base address in the bit-band region

    +

    Definition at line 134 of file stm32f407xx_matlab_memory.h.

    + @@ -994,6 +856,8 @@ Variables

    Peripheral base address in the bit-band region

    +

    Definition at line 135 of file stm32f407xx_matlab_memory.h.

    + @@ -1010,6 +874,8 @@ Variables

    Backup SRAM(4 KB) base address in the bit-band region

    +

    Definition at line 136 of file stm32f407xx_matlab_memory.h.

    + @@ -1026,6 +892,8 @@ Variables

    FLASH end address

    +

    Definition at line 137 of file stm32f407xx_matlab_memory.h.

    + @@ -1042,6 +910,8 @@ Variables

    Base address of : (up to 528 Bytes) embedded FLASH OTP Area

    +

    Definition at line 138 of file stm32f407xx_matlab_memory.h.

    + @@ -1058,6 +928,8 @@ Variables

    End address of : (up to 528 Bytes) embedded FLASH OTP Area

    +

    Definition at line 139 of file stm32f407xx_matlab_memory.h.

    + @@ -1072,1274 +944,9 @@ Variables

    CCM data RAM end address
    -

    + Debug MCU registers base address

    -
    - - -

    ◆ SRAM_BASE

    - -
    -
    - - - - -
    #define SRAM_BASE   SRAM1_BASE
    -
    - -
    -
    - -

    ◆ SRAM_BB_BASE

    - -
    -
    - - - - -
    #define SRAM_BB_BASE   SRAM1_BB_BASE
    -
    -

    Peripheral memory map

    - -
    -
    - -

    ◆ APB1PERIPH_BASE

    - -
    -
    - - - - -
    #define APB1PERIPH_BASE   PERIPH_BASE
    -
    - -
    -
    - -

    ◆ APB2PERIPH_BASE

    - -
    -
    - - - - -
    #define APB2PERIPH_BASE   (PERIPH_BASE + 0x00010000UL)
    -
    - -
    -
    - -

    ◆ AHB1PERIPH_BASE

    - -
    -
    - - - - -
    #define AHB1PERIPH_BASE   (PERIPH_BASE + 0x00020000UL)
    -
    - -
    -
    - -

    ◆ AHB2PERIPH_BASE

    - -
    -
    - - - - -
    #define AHB2PERIPH_BASE   (PERIPH_BASE + 0x10000000UL)
    -
    -

    APB1 peripherals

    - -
    -
    - -

    ◆ TIM2_BASE

    - -
    -
    - - - - -
    #define TIM2_BASE   (APB1PERIPH_BASE + 0x0000UL)
    -
    - -
    -
    - -

    ◆ TIM3_BASE

    - -
    -
    - - - - -
    #define TIM3_BASE   (APB1PERIPH_BASE + 0x0400UL)
    -
    - -
    -
    - -

    ◆ TIM4_BASE

    - -
    -
    - - - - -
    #define TIM4_BASE   (APB1PERIPH_BASE + 0x0800UL)
    -
    - -
    -
    - -

    ◆ TIM5_BASE

    - -
    -
    - - - - -
    #define TIM5_BASE   (APB1PERIPH_BASE + 0x0C00UL)
    -
    - -
    -
    - -

    ◆ TIM6_BASE

    - -
    -
    - - - - -
    #define TIM6_BASE   (APB1PERIPH_BASE + 0x1000UL)
    -
    - -
    -
    - -

    ◆ TIM7_BASE

    - -
    -
    - - - - -
    #define TIM7_BASE   (APB1PERIPH_BASE + 0x1400UL)
    -
    - -
    -
    - -

    ◆ TIM12_BASE

    - -
    -
    - - - - -
    #define TIM12_BASE   (APB1PERIPH_BASE + 0x1800UL)
    -
    - -
    -
    - -

    ◆ TIM13_BASE

    - -
    -
    - - - - -
    #define TIM13_BASE   (APB1PERIPH_BASE + 0x1C00UL)
    -
    - -
    -
    - -

    ◆ TIM14_BASE

    - -
    -
    - - - - -
    #define TIM14_BASE   (APB1PERIPH_BASE + 0x2000UL)
    -
    - -
    -
    - -

    ◆ RTC_BASE

    - -
    -
    - - - - -
    #define RTC_BASE   (APB1PERIPH_BASE + 0x2800UL)
    -
    - -
    -
    - -

    ◆ WWDG_BASE

    - -
    -
    - - - - -
    #define WWDG_BASE   (APB1PERIPH_BASE + 0x2C00UL)
    -
    - -
    -
    - -

    ◆ IWDG_BASE

    - -
    -
    - - - - -
    #define IWDG_BASE   (APB1PERIPH_BASE + 0x3000UL)
    -
    - -
    -
    - -

    ◆ I2S2ext_BASE

    - -
    -
    - - - - -
    #define I2S2ext_BASE   (APB1PERIPH_BASE + 0x3400UL)
    -
    - -
    -
    - -

    ◆ SPI2_BASE

    - -
    -
    - - - - -
    #define SPI2_BASE   (APB1PERIPH_BASE + 0x3800UL)
    -
    - -
    -
    - -

    ◆ SPI3_BASE

    - -
    -
    - - - - -
    #define SPI3_BASE   (APB1PERIPH_BASE + 0x3C00UL)
    -
    - -
    -
    - -

    ◆ I2S3ext_BASE

    - -
    -
    - - - - -
    #define I2S3ext_BASE   (APB1PERIPH_BASE + 0x4000UL)
    -
    - -
    -
    - -

    ◆ USART2_BASE

    - -
    -
    - - - - -
    #define USART2_BASE   (APB1PERIPH_BASE + 0x4400UL)
    -
    - -
    -
    - -

    ◆ USART3_BASE

    - -
    -
    - - - - -
    #define USART3_BASE   (APB1PERIPH_BASE + 0x4800UL)
    -
    - -
    -
    - -

    ◆ UART4_BASE

    - -
    -
    - - - - -
    #define UART4_BASE   (APB1PERIPH_BASE + 0x4C00UL)
    -
    - -
    -
    - -

    ◆ UART5_BASE

    - -
    -
    - - - - -
    #define UART5_BASE   (APB1PERIPH_BASE + 0x5000UL)
    -
    - -
    -
    - -

    ◆ I2C1_BASE

    - -
    -
    - - - - -
    #define I2C1_BASE   (APB1PERIPH_BASE + 0x5400UL)
    -
    - -
    -
    - -

    ◆ I2C2_BASE

    - -
    -
    - - - - -
    #define I2C2_BASE   (APB1PERIPH_BASE + 0x5800UL)
    -
    - -
    -
    - -

    ◆ I2C3_BASE

    - -
    -
    - - - - -
    #define I2C3_BASE   (APB1PERIPH_BASE + 0x5C00UL)
    -
    - -
    -
    - -

    ◆ CAN1_BASE

    - -
    -
    - - - - -
    #define CAN1_BASE   (APB1PERIPH_BASE + 0x6400UL)
    -
    - -
    -
    - -

    ◆ CAN2_BASE

    - -
    -
    - - - - -
    #define CAN2_BASE   (APB1PERIPH_BASE + 0x6800UL)
    -
    - -
    -
    - -

    ◆ PWR_BASE

    - -
    -
    - - - - -
    #define PWR_BASE   (APB1PERIPH_BASE + 0x7000UL)
    -
    - -
    -
    - -

    ◆ DAC_BASE

    - -
    -
    - - - - -
    #define DAC_BASE   (APB1PERIPH_BASE + 0x7400UL)
    -
    -

    APB2 peripherals

    - -
    -
    - -

    ◆ TIM1_BASE

    - -
    -
    - - - - -
    #define TIM1_BASE   (APB2PERIPH_BASE + 0x0000UL)
    -
    - -
    -
    - -

    ◆ TIM8_BASE

    - -
    -
    - - - - -
    #define TIM8_BASE   (APB2PERIPH_BASE + 0x0400UL)
    -
    - -
    -
    - -

    ◆ USART1_BASE

    - -
    -
    - - - - -
    #define USART1_BASE   (APB2PERIPH_BASE + 0x1000UL)
    -
    - -
    -
    - -

    ◆ USART6_BASE

    - -
    -
    - - - - -
    #define USART6_BASE   (APB2PERIPH_BASE + 0x1400UL)
    -
    - -
    -
    - -

    ◆ ADC1_BASE

    - -
    -
    - - - - -
    #define ADC1_BASE   (APB2PERIPH_BASE + 0x2000UL)
    -
    - -
    -
    - -

    ◆ ADC2_BASE

    - -
    -
    - - - - -
    #define ADC2_BASE   (APB2PERIPH_BASE + 0x2100UL)
    -
    - -
    -
    - -

    ◆ ADC3_BASE

    - -
    -
    - - - - -
    #define ADC3_BASE   (APB2PERIPH_BASE + 0x2200UL)
    -
    - -
    -
    - -

    ◆ ADC123_COMMON_BASE

    - -
    -
    - - - - -
    #define ADC123_COMMON_BASE   (APB2PERIPH_BASE + 0x2300UL)
    -
    - -
    -
    - -

    ◆ ADC_BASE

    - -
    -
    - - - - -
    #define ADC_BASE   ADC123_COMMON_BASE
    -
    - -
    -
    - -

    ◆ SDIO_BASE

    - -
    -
    - - - - -
    #define SDIO_BASE   (APB2PERIPH_BASE + 0x2C00UL)
    -
    - -
    -
    - -

    ◆ SPI1_BASE

    - -
    -
    - - - - -
    #define SPI1_BASE   (APB2PERIPH_BASE + 0x3000UL)
    -
    - -
    -
    - -

    ◆ SYSCFG_BASE

    - -
    -
    - - - - -
    #define SYSCFG_BASE   (APB2PERIPH_BASE + 0x3800UL)
    -
    - -
    -
    - -

    ◆ EXTI_BASE

    - -
    -
    - - - - -
    #define EXTI_BASE   (APB2PERIPH_BASE + 0x3C00UL)
    -
    - -
    -
    - -

    ◆ TIM9_BASE

    - -
    -
    - - - - -
    #define TIM9_BASE   (APB2PERIPH_BASE + 0x4000UL)
    -
    - -
    -
    - -

    ◆ TIM10_BASE

    - -
    -
    - - - - -
    #define TIM10_BASE   (APB2PERIPH_BASE + 0x4400UL)
    -
    - -
    -
    - -

    ◆ TIM11_BASE

    - -
    -
    - - - - -
    #define TIM11_BASE   (APB2PERIPH_BASE + 0x4800UL)
    -
    -

    AHB1 peripherals

    - -
    -
    - -

    ◆ GPIOA_BASE

    - -
    -
    - - - - -
    #define GPIOA_BASE   (AHB1PERIPH_BASE + 0x0000UL)
    -
    - -
    -
    - -

    ◆ GPIOB_BASE

    - -
    -
    - - - - -
    #define GPIOB_BASE   (AHB1PERIPH_BASE + 0x0400UL)
    -
    - -
    -
    - -

    ◆ GPIOC_BASE

    - -
    -
    - - - - -
    #define GPIOC_BASE   (AHB1PERIPH_BASE + 0x0800UL)
    -
    - -
    -
    - -

    ◆ GPIOD_BASE

    - -
    -
    - - - - -
    #define GPIOD_BASE   (AHB1PERIPH_BASE + 0x0C00UL)
    -
    - -
    -
    - -

    ◆ GPIOE_BASE

    - -
    -
    - - - - -
    #define GPIOE_BASE   (AHB1PERIPH_BASE + 0x1000UL)
    -
    - -
    -
    - -

    ◆ GPIOF_BASE

    - -
    -
    - - - - -
    #define GPIOF_BASE   (AHB1PERIPH_BASE + 0x1400UL)
    -
    - -
    -
    - -

    ◆ GPIOG_BASE

    - -
    -
    - - - - -
    #define GPIOG_BASE   (AHB1PERIPH_BASE + 0x1800UL)
    -
    - -
    -
    - -

    ◆ GPIOH_BASE

    - -
    -
    - - - - -
    #define GPIOH_BASE   (AHB1PERIPH_BASE + 0x1C00UL)
    -
    - -
    -
    - -

    ◆ GPIOI_BASE

    - -
    -
    - - - - -
    #define GPIOI_BASE   (AHB1PERIPH_BASE + 0x2000UL)
    -
    - -
    -
    - -

    ◆ CRC_BASE

    - -
    -
    - - - - -
    #define CRC_BASE   (AHB1PERIPH_BASE + 0x3000UL)
    -
    - -
    -
    - -

    ◆ RCC_BASE

    - -
    -
    - - - - -
    #define RCC_BASE   (AHB1PERIPH_BASE + 0x3800UL)
    -
    - -
    -
    - -

    ◆ FLASH_R_BASE

    - -
    -
    - - - - -
    #define FLASH_R_BASE   (AHB1PERIPH_BASE + 0x3C00UL)
    -
    - -
    -
    - -

    ◆ DMA1_BASE

    - -
    -
    - - - - -
    #define DMA1_BASE   (AHB1PERIPH_BASE + 0x6000UL)
    -
    - -
    -
    - -

    ◆ DMA1_Stream0_BASE

    - -
    -
    - - - - -
    #define DMA1_Stream0_BASE   (DMA1_BASE + 0x010UL)
    -
    - -
    -
    - -

    ◆ DMA1_Stream1_BASE

    - -
    -
    - - - - -
    #define DMA1_Stream1_BASE   (DMA1_BASE + 0x028UL)
    -
    - -
    -
    - -

    ◆ DMA1_Stream2_BASE

    - -
    -
    - - - - -
    #define DMA1_Stream2_BASE   (DMA1_BASE + 0x040UL)
    -
    - -
    -
    - -

    ◆ DMA1_Stream3_BASE

    - -
    -
    - - - - -
    #define DMA1_Stream3_BASE   (DMA1_BASE + 0x058UL)
    -
    - -
    -
    - -

    ◆ DMA1_Stream4_BASE

    - -
    -
    - - - - -
    #define DMA1_Stream4_BASE   (DMA1_BASE + 0x070UL)
    -
    - -
    -
    - -

    ◆ DMA1_Stream5_BASE

    - -
    -
    - - - - -
    #define DMA1_Stream5_BASE   (DMA1_BASE + 0x088UL)
    -
    - -
    -
    - -

    ◆ DMA1_Stream6_BASE

    - -
    -
    - - - - -
    #define DMA1_Stream6_BASE   (DMA1_BASE + 0x0A0UL)
    -
    - -
    -
    - -

    ◆ DMA1_Stream7_BASE

    - -
    -
    - - - - -
    #define DMA1_Stream7_BASE   (DMA1_BASE + 0x0B8UL)
    -
    - -
    -
    - -

    ◆ DMA2_BASE

    - -
    -
    - - - - -
    #define DMA2_BASE   (AHB1PERIPH_BASE + 0x6400UL)
    -
    - -
    -
    - -

    ◆ DMA2_Stream0_BASE

    - -
    -
    - - - - -
    #define DMA2_Stream0_BASE   (DMA2_BASE + 0x010UL)
    -
    - -
    -
    - -

    ◆ DMA2_Stream1_BASE

    - -
    -
    - - - - -
    #define DMA2_Stream1_BASE   (DMA2_BASE + 0x028UL)
    -
    - -
    -
    - -

    ◆ DMA2_Stream2_BASE

    - -
    -
    - - - - -
    #define DMA2_Stream2_BASE   (DMA2_BASE + 0x040UL)
    -
    - -
    -
    - -

    ◆ DMA2_Stream3_BASE

    - -
    -
    - - - - -
    #define DMA2_Stream3_BASE   (DMA2_BASE + 0x058UL)
    -
    - -
    -
    - -

    ◆ DMA2_Stream4_BASE

    - -
    -
    - - - - -
    #define DMA2_Stream4_BASE   (DMA2_BASE + 0x070UL)
    -
    - -
    -
    - -

    ◆ DMA2_Stream5_BASE

    - -
    -
    - - - - -
    #define DMA2_Stream5_BASE   (DMA2_BASE + 0x088UL)
    -
    - -
    -
    - -

    ◆ DMA2_Stream6_BASE

    - -
    -
    - - - - -
    #define DMA2_Stream6_BASE   (DMA2_BASE + 0x0A0UL)
    -
    - -
    -
    - -

    ◆ DMA2_Stream7_BASE

    - -
    -
    - - - - -
    #define DMA2_Stream7_BASE   (DMA2_BASE + 0x0B8UL)
    -
    - -
    -
    - -

    ◆ ETH_BASE

    - -
    -
    - - - - -
    #define ETH_BASE   (AHB1PERIPH_BASE + 0x8000UL)
    -
    - -
    -
    - -

    ◆ ETH_MAC_BASE

    - -
    -
    - - - - -
    #define ETH_MAC_BASE   (ETH_BASE)
    -
    - -
    -
    - -

    ◆ ETH_MMC_BASE

    - -
    -
    - - - - -
    #define ETH_MMC_BASE   (ETH_BASE + 0x0100UL)
    -
    - -
    -
    - -

    ◆ ETH_PTP_BASE

    - -
    -
    - - - - -
    #define ETH_PTP_BASE   (ETH_BASE + 0x0700UL)
    -
    - -
    -
    - -

    ◆ ETH_DMA_BASE

    - -
    -
    - - - - -
    #define ETH_DMA_BASE   (ETH_BASE + 0x1000UL)
    -
    -

    AHB2 peripherals

    - -
    -
    - -

    ◆ DCMI_BASE

    - -
    -
    - - - - -
    #define DCMI_BASE   (AHB2PERIPH_BASE + 0x50000UL)
    -
    - -
    -
    - -

    ◆ RNG_BASE

    - -
    -
    - - - - -
    #define RNG_BASE   (AHB2PERIPH_BASE + 0x60800UL)
    -
    -

    FSMC Bankx registers base address

    - -
    -
    - -

    ◆ FSMC_Bank1_R_BASE

    - -
    -
    - - - - -
    #define FSMC_Bank1_R_BASE   (FSMC_R_BASE + 0x0000UL)
    -
    - -
    -
    - -

    ◆ FSMC_Bank1E_R_BASE

    - -
    -
    - - - - -
    #define FSMC_Bank1E_R_BASE   (FSMC_R_BASE + 0x0104UL)
    -
    - -
    -
    - -

    ◆ FSMC_Bank2_3_R_BASE

    - -
    -
    - - - - -
    #define FSMC_Bank2_3_R_BASE   (FSMC_R_BASE + 0x0060UL)
    -
    - -
    -
    - -

    ◆ FSMC_Bank4_R_BASE

    - -
    -
    - - - - -
    #define FSMC_Bank4_R_BASE   (FSMC_R_BASE + 0x00A0UL)
    -
    -

    Debug MCU registers base address

    +

    Definition at line 140 of file stm32f407xx_matlab_memory.h.

    @@ -2350,254 +957,12 @@ Variables
    - - -
    #define DBGMCU_BASE   (&DEBUG_MCU)
    -
    -

    USB registers base address

    - -
    - - -

    ◆ USB_OTG_HS_PERIPH_BASE

    - -
    -
    - - - +
    #define USB_OTG_HS_PERIPH_BASE   0x40040000UL#define DBGMCU_BASE   (MCU_MEM.DEBUG_MCU_BASE)
    -
    -
    - -

    ◆ USB_OTG_FS_PERIPH_BASE

    - -
    -
    - - - - -
    #define USB_OTG_FS_PERIPH_BASE   0x50000000UL
    -
    - -
    -
    - -

    ◆ USB_OTG_GLOBAL_BASE

    - -
    -
    - - - - -
    #define USB_OTG_GLOBAL_BASE   0x000UL
    -
    - -
    -
    - -

    ◆ USB_OTG_DEVICE_BASE

    - -
    -
    - - - - -
    #define USB_OTG_DEVICE_BASE   0x800UL
    -
    - -
    -
    - -

    ◆ USB_OTG_IN_ENDPOINT_BASE

    - -
    -
    - - - - -
    #define USB_OTG_IN_ENDPOINT_BASE   0x900UL
    -
    - -
    -
    - -

    ◆ USB_OTG_OUT_ENDPOINT_BASE

    - -
    -
    - - - - -
    #define USB_OTG_OUT_ENDPOINT_BASE   0xB00UL
    -
    - -
    -
    - -

    ◆ USB_OTG_EP_REG_SIZE

    - -
    -
    - - - - -
    #define USB_OTG_EP_REG_SIZE   0x20UL
    -
    - -
    -
    - -

    ◆ USB_OTG_HOST_BASE

    - -
    -
    - - - - -
    #define USB_OTG_HOST_BASE   0x400UL
    -
    - -
    -
    - -

    ◆ USB_OTG_HOST_PORT_BASE

    - -
    -
    - - - - -
    #define USB_OTG_HOST_PORT_BASE   0x440UL
    -
    - -
    -
    - -

    ◆ USB_OTG_HOST_CHANNEL_BASE

    - -
    -
    - - - - -
    #define USB_OTG_HOST_CHANNEL_BASE   0x500UL
    -
    - -
    -
    - -

    ◆ USB_OTG_HOST_CHANNEL_SIZE

    - -
    -
    - - - - -
    #define USB_OTG_HOST_CHANNEL_SIZE   0x20UL
    -
    - -
    -
    - -

    ◆ USB_OTG_PCGCCTL_BASE

    - -
    -
    - - - - -
    #define USB_OTG_PCGCCTL_BASE   0xE00UL
    -
    - -
    -
    - -

    ◆ USB_OTG_FIFO_BASE

    - -
    -
    - - - - -
    #define USB_OTG_FIFO_BASE   0x1000UL
    -
    - -
    -
    - -

    ◆ USB_OTG_FIFO_SIZE

    - -
    -
    - - - - -
    #define USB_OTG_FIFO_SIZE   0x1000UL
    -
    - -
    -
    - -

    ◆ UID_BASE

    - -
    -
    - - - - -
    #define UID_BASE   0x1FFF7A10UL
    -
    -

    Unique device ID register base address

    - -
    -
    - -

    ◆ FLASHSIZE_BASE

    - -
    -
    - - - - -
    #define FLASHSIZE_BASE   0x1FFF7A22UL
    -
    -

    FLASH Size register base address
    -

    - -
    -
    - -

    ◆ PACKAGE_BASE

    - -
    -
    - - - - -
    #define PACKAGE_BASE   0x1FFF7BF0UL
    -
    -

    Package size register base address
    -

    +

    Definition at line 143 of file stm32f407xx_matlab_memory.h.

    @@ -2637,19 +1002,7 @@ Variables
    -
    - - -

    ◆ DEBUG_MCU

    - -
    -
    - - - - -
    DBGMCU_TypeDef DEBUG_MCU
    -
    +

    Definition at line 13 of file stm32f4xx_matlab_conf.c.

    diff --git a/DOCS/html/group___peripheral__memory__map.map b/DOCS/html/group___peripheral__memory__map.map index 7fe6c8d..d9ae4f3 100644 --- a/DOCS/html/group___peripheral__memory__map.map +++ b/DOCS/html/group___peripheral__memory__map.map @@ -1,7 +1,4 @@ - - - - - - + + + diff --git a/DOCS/html/group___peripheral__memory__map.md5 b/DOCS/html/group___peripheral__memory__map.md5 index 852add4..c728e5a 100644 --- a/DOCS/html/group___peripheral__memory__map.md5 +++ b/DOCS/html/group___peripheral__memory__map.md5 @@ -1 +1 @@ -39b7405fdd1a86c8e81b2c9a14a3f42b \ No newline at end of file +149fe7b269a5b0d07ef1ec5c424d4517 \ No newline at end of file diff --git a/DOCS/html/group___peripheral__memory__map.png b/DOCS/html/group___peripheral__memory__map.png index 8bbd1593a7c7eddf41db95d97527730408be02ad..542eb37edebd35b3bc8a82c66c57cf0606f120b2 100644 GIT binary patch delta 1183 zcmV;Q1YrAt9ij;#iBL{Q4GJ0x0000DNk~Le0003^0000b2nGNE0LCD@N0A{Ee*{-a zL_t(|obBAdYb0eH$MN?w7Y!VOn)*P(RdQEYqzc#`R*Ho=Jk-W)#!dtqJMH`v95$te zCus$H53fl`;}r_2a&Se!Ekc5NvSYEk-ZDGCo|$=`XLk4Vf+5V0XP)mfm-*iF%rhAf z5fKp)5fKp)5m_E4yJ3HS|CTXke>X%h;zpXLzaAbQJ`Ej56NABEFLVsDzM?2PPm<*E z{I-qkLB^O}W6VQ;VTlL#fgeK$(S&{%C8Y6qd<1+jzilCD&Lm0VJRor|j^ofFw6?vy z&DPdd=rCl>oSmI98jTjVM*(6H5m{PFnj#_=lr%*|EGTJ;h*(h46cMqYf21iQVxiNd zX^i=Q@oB!^HucY!t$U8L<9uI-j=chW1pEZt4jfBuaUAC^ZO+%_acz{i}N_i>QITcZ}mWZuIW) zGQF={)W*T5BL~(75Eo;DP&M0edY9-W?sT7 z8bap{i(L%&^UhgRci#T0xQotFRCm?+%gVKM2ly6v2K)ki2E4}Pdju<=FpGxnv-RxH z?6#sFPtm@*^_3l4B}tOp^B48ls^ZCuscE~4_J?RoTb&Kh>!=#Sf6uSG815IHvrezH zEHoR%03Y(jy?AWIJ>ekox zrk?fC=6|+{r%g=Re|Fi%Ri{kVd0ZszUM0;e7qidHHlsc3!OpMS+S%Fp?ez5Yd*DMR z&n<5QfAeCZr^@F{hVkBQZf;tCovF@^;(J2DroPZK@yo_{Tbw4%wnJ(cy}Lg5W{Y$* zJpTjuX1d&A^0})|fm^^oz{@3Nf1Z~2ZezpEuc+@?@w)Zpe+@4~#?yDcuGhRyCW5lP zA?W^lrJ>Zvt(WMEUK zXriiXo&7gnXBcTS)U+LzW|K?X`kN|B)=len9P=1>G+n*~?lE~s^L-{m_Y}C%Wrcl^ zotbTN6Wf%tf2l8feit`=oA$dnPa9R&tI5Atm4$B1U@+J-#ynh=?)$onWoz`Mid0>zaOq_-HsB*86h1thH<4hw1V< z@K@MyMEXNXQ>rX}?_b1H*F)rxlr%+ZT7?@vlu*w*bzRV>;Y36%C~1m_SWwaw5wW18 zDI#K_a3V+#y`?WME-o02G>I>MU0+}4ZeK{6Q52nz$K#`ulN0Abi62oEorjL0sWeTG xE-x=bhaqb!ilWD%V-OJ$5fKp)5fKq-<3FF;YGaww0jU50002ovPDHLkV1ki{O%MP8 literal 3713 zcma)9c|25W_&=f|TXnOfM#>mukI*ofWEqS`k|q&qnnsx#`!@D_ZJ8L^Lb#?&#!fT# zt>julV@cL1G-InQBQAc&{eABJ{I)-S=bX=b-p_O1=Xsy^`#k4)zi$l2+D!P6)FA)> zgi+>~t^mM3ey|_Me*kRx%v|)r*8x{cvrEA4-ksBsp9BCR+Nev&tA3e_R?oLb@7?+3Lj`cT3?vO;p@{XJ38tOH1QL?T;8aK^z=FZ9nHG* zIm2FkPYNIC(?6FwoW20|^9an*tp}rxFBWt$Lx>MZFdSuMGnD6@Kaz69 z%?|_4nF|vQ4vRi@3+fmfPft&dPhCuBl}GG;02q)I*araLP9s5c22c=$<|sZM0N6;7 z0R^X|J^4a4Zeypi6X$fT!xCwD>@|1SVx^;efTXeA*P9u`9r#z5?R2%rT>nu&wd@`} z#ho{FND=d^b0zy9gBO2ZgAni5q zZivRJ3IPh80J3N~+TK+qPt>$&qvG`vAbm1|~Ny&z7Lheu42)Xh~E!RhqgQ z#`+y}_g9(IU_7B<#)U?Lo#_8x6MCc0ku@d6ISnf3@MxO{Tw}@AKz>@a{@Amm)vb!! zP4O}z<~PFF-_y?hEgLw1>NT&`_q!1B0f%Z@dtiAHOhCzDIkvFliSyqYdt$(uL(9ui z#Qdf|=FNm#o&MGu%c4#^#k!Wk*e^X=LDMFFrPO$-$alt|ufpZGSPthb57n1ywnYhQ zrOr6^5t-bNjBT&uEzPBaZVi2GFG>o;OscZ75*rjM{Pt4QrmWwJgMiJ7b4h zR2&%hTwA&L0~=OoG+~tCo;$y_-MG2kn39@0IKNgD-1KlQ0I{}3-fII8#l^)4_4DV& zuo6%R%ybPx#gqq{IR9+gW>NlDQ%G|a}5bMZ?)by-+h^L&A(h>VAg*#7>0 zTojKv)%v;q1s{QM=)3N2t?8ifdtfz4hw&G8yMa|89vKcI7_|34{g0e{$H20-xg zQQV-=o>00MEXT<)rhLCs6LUJJ|{LXySY^rV=`=RJiJxl zExVCM!+!~0-X@_86EjYl-=-d`8eOETE&s>~Y3OPt;v$PR-PPP2Y+Xo{qYl^Bgm&j0 zZ>tt}+x-o3gZ1ID_+SAiXMniN}p6-PZW53picJBHZ(l6q`Rmdkg&8qDDC z`PB(xbl|CL+J%{H9~2W^`D8xJS-c!))2r}fr1WVy+5)T!Oz5~gcT~o~qp4Yyv-?zz z{n^88$<2jCB6+gTkvvPMd)!@^0TDg(F3bJI3>ZqC9rYvnJON?SwIFVc!Amo5BV!^7 z+ayov@H>bAOyuYGC(8+|WRx#^g!vFwQ}~lGi#!ew*$J9HhqV6{1rIH7?=JzNpCp|YaGjjsEeS;_;5;69rxyqi`Irb=Zz_#k1a?^n{>XPpS|FUzMfB(#n_XTl6#+I%9_%dmYTK2*^nsLvBt zv4g9MIcIQwM9ph2f?=h1axIvWXLpe(QWIZ4Z}rZf)8F#qaCp4z#uHk0S5{fIEm+8R z^sf89$V}+8Ssf&^Q2r)o3*TumC0K_tn$sdoP*G5_HIcP#jCv?EYiWKlC6iK;FJc+VWtOruf7@; zOPXU$dAbdIEZ3Il)-UoUqv6Xk!pjE!w>8E~p<6cVCPmB9Jv}`J53ob0It@_G4Ocu) z&Lt9=TOO^yXFw4$I#@pxODX*z{!@p1w%6UeceM}*N7I!LQ%ORVc0=D!z8X)Gzs&jT z=Ss+ePaP`zVi|NXDMPtl&R6=PN_S6>^h71Tx8--!v`%U9Q~3X+I&iPA7}&=vGlmKR zFN-WT`#_M*`252`sUgDhu%Y;7$4HNV+#U+_3r@ZB-*(J&i|ACzBG(2h+jJZg4> zU|1)!ylw-rq=F4i_3jd_rL-%O9At|Q5K^~xf*8L08GCVy!og!;S(Vv)KBRV)Z zWPm8vE?+EDzK^D=yqwYP3EWrs2qrI|{pe)=sX=S{AUw-uIQfIyE2lE|tw$e80H7YL zLJgMFIZ`$gY?R2JUpqPtvcdhewyX@QYM1hbY6W)9l{5RLVnHfW_|>jv^6F;&SYl-L zL&b3guAVuu>w+qX!jU>CBsBvX880(TO*v@TB+KSf@0zrN>>|%SVfFEtg9wrdaZ1%= z2lP7E8Cu?uD$-M8<4}f@MZMg>Fdo2Y%0NZuxTG|iKO@8lRBM*}D8t6r25U_z9hfl( zxsfEVo?HWrfM#vkK9zR?c||S^ig@PY2o-7uLcRirA6#VN!6L?9p)RH9T_IVs458b$ zEF~(X0}Tx|-D9a8Q8v z?B0;Vut=Wdi(qUAFSUkVNt6MM5a3u0Xa#c_D)grq$k()Z1wf({{R+u)q&`nxwMQXp zVp{a5!8cuR76_PvMqzjHcu|KGZ*??wl(Du{x6J8I*L;?lIZ(`;c;@X_P;MM0^7BVn z%(;C$0Il+NyU2Lpasw_Z?6<@{uX8S(u%^N@F_c?x~&iCO*mmFm4(a38pVCX`n zWWa^}A9VfSoD{}kTe5$ZVCXOV(ECiq%V)|%OiotP{@vLhU+AhRX{_&x*jZDJlX}U2 z13%(4z(A$FNrPJVFIsWsIU6v7?7R)X0qO|wHVudMIN82IzW%Ym2Zs^ibM5uu-`p;kPe`%T=7u%-Q1J!uzenPwD(bLKI3VUJArFxCP zx?aOeX){!-4Z(~r_Oq9|3bte7-g}K!wJUdh33CtvQ!eTVcuH_@6K2aIKwpep?bt!| zqh`O5;&}c&2K|dG5R^va2hLYiRncl{YARkE8F%;gMwQ4S!I-3HXFt(@2`0sVyOP&K XCR4n_ZGMr!?a5Il)|W~yI*0!Ur184$ diff --git a/DOCS/html/group___peripheral__registers__structures.html b/DOCS/html/group___peripheral__registers__structures.html deleted file mode 100644 index 2c55014..0000000 --- a/DOCS/html/group___peripheral__registers__structures.html +++ /dev/null @@ -1,214 +0,0 @@ - - - - - - - -STM MATLAB Simulator: Peripheral_registers_structures - - - - - - - - - - - -
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    CMSIS_Device » Stm32f407xx
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    -Data Structures

    struct  ADC_TypeDef
     Analog to Digital Converter
    - More...
     
    struct  ADC_Common_TypeDef
     
    struct  CAN_TxMailBox_TypeDef
     Controller Area Network TxMailBox. More...
     
    struct  CAN_FIFOMailBox_TypeDef
     Controller Area Network FIFOMailBox. More...
     
    struct  CAN_FilterRegister_TypeDef
     Controller Area Network FilterRegister. More...
     
    struct  CAN_TypeDef
     Controller Area Network. More...
     
    struct  CRC_TypeDef
     CRC calculation unit. More...
     
    struct  DAC_TypeDef
     Digital to Analog Converter. More...
     
    struct  DBGMCU_TypeDef
     Debug MCU. More...
     
    struct  DCMI_TypeDef
     DCMI. More...
     
    struct  DMA_Stream_TypeDef
     DMA Controller. More...
     
    struct  DMA_TypeDef
     
    struct  ETH_TypeDef
     Ethernet MAC. More...
     
    struct  EXTI_TypeDef
     External Interrupt/Event Controller. More...
     
    struct  FLASH_TypeDef
     FLASH Registers. More...
     
    struct  FSMC_Bank1_TypeDef
     Flexible Static Memory Controller. More...
     
    struct  FSMC_Bank1E_TypeDef
     Flexible Static Memory Controller Bank1E. More...
     
    struct  FSMC_Bank2_3_TypeDef
     Flexible Static Memory Controller Bank2. More...
     
    struct  FSMC_Bank4_TypeDef
     Flexible Static Memory Controller Bank4. More...
     
    struct  GPIO_TypeDef
     General Purpose I/O. More...
     
    struct  SYSCFG_TypeDef
     System configuration controller. More...
     
    struct  I2C_TypeDef
     Inter-integrated Circuit Interface. More...
     
    struct  IWDG_TypeDef
     Independent WATCHDOG. More...
     
    struct  PWR_TypeDef
     Power Control. More...
     
    struct  RCC_TypeDef
     Reset and Clock Control. More...
     
    struct  RTC_TypeDef
     Real-Time Clock. More...
     
    struct  SDIO_TypeDef
     SD host Interface. More...
     
    struct  SPI_TypeDef
     Serial Peripheral Interface. More...
     
    struct  TIM_TypeDef
     TIM. More...
     
    struct  USART_TypeDef
     Universal Synchronous Asynchronous Receiver Transmitter. More...
     
    struct  WWDG_TypeDef
     Window WATCHDOG. More...
     
    struct  RNG_TypeDef
     RNG. More...
     
    struct  USB_OTG_GlobalTypeDef
     USB_OTG_Core_Registers. More...
     
    struct  USB_OTG_DeviceTypeDef
     USB_OTG_device_Registers. More...
     
    struct  USB_OTG_INEndpointTypeDef
     USB_OTG_IN_Endpoint-Specific_Register. More...
     
    struct  USB_OTG_OUTEndpointTypeDef
     USB_OTG_OUT_Endpoint-Specific_Registers. More...
     
    struct  USB_OTG_HostTypeDef
     USB_OTG_Host_Mode_Register_Structures. More...
     
    struct  USB_OTG_HostChannelTypeDef
     USB_OTG_Host_Channel_Specific_Registers. More...
     
    -

    Detailed Description

    -
    - -
    -Generated by doxygen 1.10.0 -
    - - diff --git a/DOCS/html/group___peripheral__registers__structures.map b/DOCS/html/group___peripheral__registers__structures.map deleted file mode 100644 index b5b4386..0000000 --- a/DOCS/html/group___peripheral__registers__structures.map +++ /dev/null @@ -1,4 +0,0 @@ - - - - diff --git a/DOCS/html/group___peripheral__registers__structures.md5 b/DOCS/html/group___peripheral__registers__structures.md5 deleted file mode 100644 index 42e2c80..0000000 --- a/DOCS/html/group___peripheral__registers__structures.md5 +++ /dev/null @@ -1 +0,0 @@ -18a7f0b672e30e602316d178a1bccb08 \ No newline at end of file diff --git a/DOCS/html/group___peripheral__registers__structures.png b/DOCS/html/group___peripheral__registers__structures.png deleted file mode 100644 index 37826c2ca3354996012f600d967b76c26806a2a7..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 1456 zcmV;h1yA~kP)eP(87c4u~GH{TCD zgx%SlmyrE+UiO&+L_|bHL_|bHM0P~z3Q&Iyhr{*Ib)dKp8vSDwe?5ndJwf`At(tUZu9+;sN4haZRkq0 zAx%^1`7Fz7=Vx-S>2*!CQAWt}TvEQL)YS&{iRvNkGuhu=-3RO<{|%eAJ;vb0IVB>B z3WE}LPMW6AKjrhXpXGC^9;hnKv^?Flrfl;po|m;(mxt^=U3os*E5omuP^XlK8&$`u zdv*7jUT1r4oi^Ik(%X2k1Q+NK%w71fv zo<4quWeiFb71PzSHrbTtqi#*}EC;Nr-?2?_v&q*KgA#R4+p9%&SF&6MC>QOu8D`b( znYtRjIh*JfLM(iIUpDu8tWj{vL%u8UV~_hL-*@YS2sP15_Q zi?4ijob;505XkdfdtP--oxJDgbZJ%fGA%=we`GEJcn82o0Nw}i;_Uoa!D{3|lOaR# zUeo(*$}8vZ;-S@*Z(3ee8;U)gy6vsH*2cm=`NQFGT?p~erU0Ko$)-HhGUq`_cb!R_ zd`r_5d7j@JjYhgRy59uw34o6QECcu#z~w^v+W>y@S4*|c&CNWPP2OUBNzk>fwQ;t| z+xBQQI=Azr*Y}i)4}I}x`J8OH)Re5u`ElK#q6%KBV_jN9ZvglL!0!Nl2JisWfCQWm zNYrC}edFKB@NGVnDjv(ytA<*|d&}4B^4HbLcdw>cPPsf?S`F6$ya!;2X;AtHz?E6r z71d1?7hNE+?dA9yK85CN^-UH)svbgF@G{N6&d|zrFR2X&2M4cXI{bR8lw=x+cB(J& zv|oPgH#gqrq}R##Vl+1=g!0KkWs&K=zV z@Hc=L472zgz^}CmZ)jy@lX{!>z-(6vE&K-H%h~59rpx`G z0(ceYhjB7LAkakj($Z3hVyWYz|3Yrn4sg7;(l^xgJYpH9!F@7Pp-~J3; zfiAJxcSv@Y|d zhCHVGB6XoHa~!@A&9pTk+{Wt#U7Or4Vo!-^#%AB4s(b6^YrEIB$zDscGGnIPPibwf z*Bcgg!v6lg$$m=FifKP3ijQhPrG=hSk|f8I$z*$PZ?C=Dky4T*$D!*$)TV`?lx5it zfV+}wi8{^YUPj~(=alHeVBqNnuD%gbR2Y -STM MATLAB Simulator: RCC_SIMULATOR +STM MATLAB Simulator: RCC Simulator @@ -14,6 +14,7 @@ + @@ -73,21 +74,21 @@ $(function() {
    Macros
    -
    RCC_SIMULATOR
    STM_SIMULATION » MAIN_SIMULATOR
    +
    RCC Simulator
    STM32 Simulation » STM32 Simulator
    -

    Simulator for RCC and Clocks. +

    СимулÑтор Ð´Ð»Ñ RCC и чаÑов таймера More...

    - + Collaboration diagram for RCC_SIMULATOR:
    + + Collaboration diagram for RCC Simulator:
    @@ -113,7 +114,7 @@ Macros
     

    Detailed Description

    -

    Simulator for RCC and Clocks.

    +

    СимулÑтор Ð´Ð»Ñ RCC и чаÑов таймера

    Определ¤ет параметры Ñ‚Ð°ÐºÑ‚Ð¸Ñ€Ð¾Ð²Ð°Ð½Ð¸Ñ ÐœÐš. Содержит дефайны дл¤ Ñкипа беÑконечных циклов ожидающих выÑтавление флагов

    Macro Definition Documentation

    @@ -128,6 +129,8 @@ Macros
    +

    Definition at line 28 of file stm32f4xx_matlab_rcc.h.

    +
    @@ -142,6 +145,8 @@ Macros
    +

    Definition at line 29 of file stm32f4xx_matlab_rcc.h.

    +
    @@ -156,6 +161,8 @@ Macros
    +

    Definition at line 30 of file stm32f4xx_matlab_rcc.h.

    +
    @@ -170,6 +177,8 @@ Macros
    +

    Definition at line 31 of file stm32f4xx_matlab_rcc.h.

    +
    @@ -184,6 +193,8 @@ Macros
    +

    Definition at line 32 of file stm32f4xx_matlab_rcc.h.

    +
    @@ -200,12 +211,13 @@ Macros
    -Value:
    if(((__FLAG__) >> 5U) == 1U) RCC->CR |= (1U << ((__FLAG__) & RCC_FLAG_MASK)); \
    -
    else if(((__FLAG__) >> 5U) == 2U) RCC->BDCR |= (1U << ((__FLAG__) & RCC_FLAG_MASK)); \
    -
    else if(((__FLAG__) >> 5U) == 3U) RCC->CSR |= (1U << ((__FLAG__) & RCC_FLAG_MASK)); \
    -
    else RCC->CIR |= (1U << ((__FLAG__) & RCC_FLAG_MASK))
    -
    RCC
    #define RCC
    Definition stm32f407xx_matlab.h:1184
    +Value:
    if(((__FLAG__) >> 5U) == 1U) RCC->CR |= (1U << ((__FLAG__) & RCC_FLAG_MASK)); \
    +
    else if(((__FLAG__) >> 5U) == 2U) RCC->BDCR |= (1U << ((__FLAG__) & RCC_FLAG_MASK)); \
    +
    else if(((__FLAG__) >> 5U) == 3U) RCC->CSR |= (1U << ((__FLAG__) & RCC_FLAG_MASK)); \
    +
    else RCC->CIR |= (1U << ((__FLAG__) & RCC_FLAG_MASK))
    +

    Definition at line 36 of file stm32f4xx_matlab_rcc.h.

    +
    @@ -222,11 +234,13 @@ Macros
    -Value:
    if(((__FLAG__) >> 5U) == 1U) RCC->CR &= ~(1U << ((__FLAG__) & RCC_FLAG_MASK)); \
    -
    else if(((__FLAG__) >> 5U) == 2U) RCC->BDCR &= ~(1U << ((__FLAG__) & RCC_FLAG_MASK)); \
    -
    else if(((__FLAG__) >> 5U) == 3U) RCC->CSR &= ~(1U << ((__FLAG__) & RCC_FLAG_MASK)); \
    -
    else RCC->CIR &= ~(1U << ((__FLAG__) & RCC_FLAG_MASK))
    +Value:
    if(((__FLAG__) >> 5U) == 1U) RCC->CR &= ~(1U << ((__FLAG__) & RCC_FLAG_MASK)); \
    +
    else if(((__FLAG__) >> 5U) == 2U) RCC->BDCR &= ~(1U << ((__FLAG__) & RCC_FLAG_MASK)); \
    +
    else if(((__FLAG__) >> 5U) == 3U) RCC->CSR &= ~(1U << ((__FLAG__) & RCC_FLAG_MASK)); \
    +
    else RCC->CIR &= ~(1U << ((__FLAG__) & RCC_FLAG_MASK))
    +

    Definition at line 42 of file stm32f4xx_matlab_rcc.h.

    +
    @@ -248,6 +262,8 @@ Macros
    +

    Definition at line 48 of file stm32f4xx_matlab_rcc.h.

    +
    @@ -269,6 +285,8 @@ Macros
    +

    Definition at line 51 of file stm32f4xx_matlab_rcc.h.

    +
    diff --git a/DOCS/html/group___r_c_c___s_i_m_u_l_a_t_o_r.map b/DOCS/html/group___r_c_c___s_i_m_u_l_a_t_o_r.map index 20edec8..0e451ff 100644 --- a/DOCS/html/group___r_c_c___s_i_m_u_l_a_t_o_r.map +++ b/DOCS/html/group___r_c_c___s_i_m_u_l_a_t_o_r.map @@ -1,4 +1,4 @@ - - - + + + diff --git a/DOCS/html/group___r_c_c___s_i_m_u_l_a_t_o_r.md5 b/DOCS/html/group___r_c_c___s_i_m_u_l_a_t_o_r.md5 index e353655..9767338 100644 --- a/DOCS/html/group___r_c_c___s_i_m_u_l_a_t_o_r.md5 +++ b/DOCS/html/group___r_c_c___s_i_m_u_l_a_t_o_r.md5 @@ -1 +1 @@ -00626786a3d20249c90721b67f65e51d \ No newline at end of file +0e697fc36bc816e0d1d9dc911ce00fa8 \ No newline at end of file diff --git a/DOCS/html/group___r_c_c___s_i_m_u_l_a_t_o_r.png b/DOCS/html/group___r_c_c___s_i_m_u_l_a_t_o_r.png index 1fc200c3e5c672ed8dd7c01ea5b2c688e67d9f18..cdb9c9717cca0fe25fc8122b56ce737c416028fe 100644 GIT binary patch delta 1166 zcmV;91abSG36cpRiBL{Q4GJ0x0000DNk~Le0003a0000b2nGNE00|C{gpnZ?e@96~ zK~#90?cL35Bt;m<@o)9UCG15E9z^$&+k!_A!bb6+2VX!CahF}+4rbCfJ$v*|@Hk9B zMOat~>>sdK%Hr@OkkySjU-Cj34Sn5nL*dID3=R8?0d zAR;0nA|fIpB65)_7Hn>AUN^?ve+&_fEMAsnKW%SsKMoy-kI`s!D|8IvCrOgS@p$|w zU$#=LWQ@6KjJdzKuq3eCzz?B=@S*qV@|sSkJHQ9|vQjdd8;{3>2P9#oX&O3&&eqr0 zSzB8R9fq`UaB#r!@o}j<2@s2jNQsh>h(tljNJOHbWF#U{P%;vcC@2|;e@GN6Z|%2b zOzHe2S(a5^v(=eDu4=!kz5MH3*V@M2BrYFAw7Fo<0Ph2Lfp>w^u;DaQb(Ep%7)!ps z>!?f9dUdhnUz?_B@5gI~XtPhfB%`XqH7{>ExLxhI>debr*L>oJ`eZhw$dcAIW{KxR z;7$I2?^J)%M94N6ZG*H}e^xb+o7SuAuUH;3X@p8zOSepO4bF%L?qzWWcmwzzI0Ehg zZ_(q7I!3m^I3ABnvzey#q?tjJQQPD&pWWnzm>pCt`{s|0F{N@_+^*-vYqmD4+Hv*g z>ZhRucm?`z9nF`ETl>Ds}vYC2o+omCWPSjER_nwH9Ke+km{ym-ylW>q_` z{`yG3y?nwIlgJ{HM<4z9#BJNVYP#=L*Ixd)ZQ0rOc}p)c`&*&Ufa}0tz}53>Px&?~ zWyRT3ljN13h0R}^f8I6$RxK~*vALF>K1dTgR99PY%)08#$CMD zHSzYDxP98%-Q9f|fA|WxQMh!~Qr+hF)}8j`^tAoHdELhGqS$6Zt~hMV!M^(Ms;{;N zS^IaHDfGps?@)2~u(a~Fv9a;<{{H@Vz#ZTd;CU|2it2m{{5eo~POGb{t-ozx=sQ+E zy3BC8h;46c(7S1&G>s>QxNS?V0Dd|D`4V`ESyH+SJPZ7TfBSv%05};sK%147Zf{@P zlEkHH-MV@)BthF!E3_!@rn#1Ab%QmA1mi2@3@K+1_yTwicop~t_yfp*zXQg#FkSAP z#gJ&)iXjofKpWWk^1j*nDsCt@J@`0e+*NJ6>eby%T=0#8e}Ny*e?AA^0X_oWW_Cx- z5b1|m8&$KTf2NzvKAX{1xBvS{Voi@0+H;a8l;qrk|a5tPNzG2dwYWiCE+DWau_-WUs;yzoSXzXZz&xmN%AOk3?d>T gA|fIpA`-v<0LQyTYSMD=CjbBd07*qoM6N<$f|w0LCIA2c delta 1178 zcmV;L1ZDe@37!cdiBL{Q4GJ0x0000DNk~Le0003^0000b2nGNE0LCD@N0A{Fe^W_B zK~#90?c6bM<76Di@$cip09z^s5VxeS0R}q2f;u3x-6L(Wn4@kTeBo?G7*_aAt zKn$om;-GapobyP7LjgCXtAl(&3(baf7e!4mBrF0`> z%%L&nti7^i2RsD64P8VPdap~K#bR*|JlLGJ6`E_~@woAVr2pbL4qZZR!{Lzq{r%8o zNXJ}WUNWE0x28t{Y7r6XErq6thy#VDh=>D)rih3Gg{Fvz1BIrDhy&{*e@8BiF(gUi zJiqL8*X8r-NXy%f%YN0}mom%Qq}P{jTQuL+u3`6BKHvEs@KKu^uEX|-mF*F|&GvbZ z@s(}oQrG5s;yBLzJ8OOG`L?#M>&#ouCcVCN+oJilc6E3OO~?<8y!KT?#Akg~1HUO* z$EIxXX3fi*=Ho-Cf_>lPYg(%%1-1vg4}1gs3H$)uXW6saqemaszLmY&@o`mDf3%LWAuccS);)KT z?sk?9A(ytcWjFusqN>NH10t4P?qlFHU;zBf|L?KAKy~fBbog~O^wM4Oz6P|{(A+%9 zyLhr^4Xn6^br<)milRX=7Z(>79{^thZ>DCId4IhI1UsO!*^J?E=(J4Hpi2l@11n`} z+6=G0hFDtD|DV>ce>B%8Yt=5Vuiz>g^$wx#v2jslMBnD<=;){EbUFn-UA+dtKfuc+ z7QX>Tl{a3~!NGy^uQSydv}r@psCNkKAZz1xK-2%9Al>t}N2Ay4?@Bo432|)deh?XB z65!|6>kF0xJx_o~z^lLld-wcr;JZp2_Fym=)LP#43a#p6e>uL|hSc^*{d$|ekB|2o z@_8p<-ihfl!W&{VxF}fa4jB13Hnw&xe_%Xk8J?#syWaPKGnV1_eD&ISbwe zsavD#x?S3Z_`nEqrRjrfaN64Y43n~hO-%-V)_%5m+au*K;K$YLbKqm(G4L+=SD(FN z3!Sn9G<64Ze{6x`Gfc|X*yNRC)_%I)xAkG`>>Z6p$HthmK3wigcySz)B+0|cWa4sf z@O75o26_yzGNfZ}Z*McFZ-r(QMOTZ(;(RunHC~kLhA4`zLf24Lk|gIhH#ecn skdBI?=xOL0L_|bHL_|bHL`3TN56QKrGf9WFivR!s07*qoM6N<$f`0>3x&QzG diff --git a/DOCS/html/group___s_i_m_u_l_a_t_o_r___c_o_n_f.html b/DOCS/html/group___s_i_m_u_l_a_t_o_r___c_o_n_f.html index 00568cc..fbb767d 100644 --- a/DOCS/html/group___s_i_m_u_l_a_t_o_r___c_o_n_f.html +++ b/DOCS/html/group___s_i_m_u_l_a_t_o_r___c_o_n_f.html @@ -5,7 +5,7 @@ -STM MATLAB Simulator: SIMULATOR_CONF +STM MATLAB Simulator: Simulator Configuration @@ -14,6 +14,7 @@ + @@ -73,21 +74,21 @@ $(function() {
    Macros
    -
    SIMULATOR_CONF
    STM_SIMULATION » MAIN_SIMULATOR
    +
    Simulator Configuration
    STM32 Simulation » STM32 Simulator
    -

    Configurations for simulator to simulating MCU. +

    Параметры конфигурации Ð´Ð»Ñ ÑимулÑтора МК More...

    - + Collaboration diagram for SIMULATOR_CONF:
    + + Collaboration diagram for Simulator Configuration:
    @@ -111,7 +112,7 @@ Macros
     

    Detailed Description

    -

    Configurations for simulator to simulating MCU.

    +

    Параметры конфигурации Ð´Ð»Ñ ÑимулÑтора МК

    ЗдеÑÑŒ дефайнами задаетÑÑ Ð¿ÐµÑ€Ð¸Ñ„ÐµÑ€Ð¸Ñ Ð´Ð»Ñ ÑимулÑции

    Macro Definition Documentation

    @@ -126,6 +127,8 @@ Macros
    +

    Definition at line 48 of file stm32f4xx_matlab_conf.h.

    +
    @@ -140,6 +143,8 @@ Macros
    +

    Definition at line 50 of file stm32f4xx_matlab_conf.h.

    +
    @@ -154,6 +159,8 @@ Macros
    +

    Definition at line 51 of file stm32f4xx_matlab_conf.h.

    +
    @@ -168,6 +175,8 @@ Macros
    +

    Definition at line 54 of file stm32f4xx_matlab_conf.h.

    +
    @@ -182,6 +191,8 @@ Macros
    +

    Definition at line 59 of file stm32f4xx_matlab_conf.h.

    +
    @@ -196,6 +207,8 @@ Macros
    +

    Definition at line 67 of file stm32f4xx_matlab_conf.h.

    +
    @@ -210,6 +223,8 @@ Macros
    +

    Definition at line 70 of file stm32f4xx_matlab_conf.h.

    +
    @@ -224,6 +239,8 @@ Macros
    +

    Definition at line 74 of file stm32f4xx_matlab_conf.h.

    +
    diff --git a/DOCS/html/group___s_i_m_u_l_a_t_o_r___c_o_n_f.map b/DOCS/html/group___s_i_m_u_l_a_t_o_r___c_o_n_f.map index 83f4961..4035d7c 100644 --- a/DOCS/html/group___s_i_m_u_l_a_t_o_r___c_o_n_f.map +++ b/DOCS/html/group___s_i_m_u_l_a_t_o_r___c_o_n_f.map @@ -1,4 +1,4 @@ - - - + + + diff --git a/DOCS/html/group___s_i_m_u_l_a_t_o_r___c_o_n_f.md5 b/DOCS/html/group___s_i_m_u_l_a_t_o_r___c_o_n_f.md5 index 50b699b..95f3519 100644 --- a/DOCS/html/group___s_i_m_u_l_a_t_o_r___c_o_n_f.md5 +++ b/DOCS/html/group___s_i_m_u_l_a_t_o_r___c_o_n_f.md5 @@ -1 +1 @@ -a18bd8fb30fb7be93d64a2adce70ec59 \ No newline at end of file +f4c8913c9e64f9965881b7cee27cf2bd \ No newline at end of file diff --git a/DOCS/html/group___s_i_m_u_l_a_t_o_r___c_o_n_f.png b/DOCS/html/group___s_i_m_u_l_a_t_o_r___c_o_n_f.png index 911c8bf2f9e53b25a56b3852bed346d5ab027353..a4c9b14113d2d692355eeac1cfe28c7ed472f3ff 100644 GIT binary patch delta 1233 zcmV;?1TOoo3DgN8iBL{Q4GJ0x0000DNk~Le0003}0000b2nGNE01$;?B9S2#e~C#% zK~#90?cBX(SBCZ`O6xF&qx}t!t3Y6Ncf{Xf%41+;%U0 zP!I&WK@c2wSC$xi0Q_KGL>>A)6${hp^aS`Ixos&(7e=E|>jjCeD2l90@HQ9>*xK5% zE<-lN<>e)l$z*AJXi$rY$XZd5iimhpkcxcv6sxhe=JCYAXs`7 z?aMl*to^+9it6yG+oi5L+Gw+5_kk~fpREh2DvF||M|yu7eOk$TolUmA_}P+m|GD>( zRuKdNaUADvPwvY*wyd3^V;0+r_SLBy$UV0UMYS7v0eBDi7}x`z0{$_rsG=x}GVhO0 zZnwODI)%7z9?9F6gunTS>PSud*Bb?Tb_id^jKDCjz%N% zk=wdzHAt%l+hSCiWHBmBkD${(=Pg|%Raqh^TIwiTy2xt3fn|dbcmw!`S$O`$?BC&@ zV-}!m7ozD=Tl(kp)YxT7peV4irrUW_9Ac7RWS&w!VKe|hrz@pRor`y@Rg zbD0h%M|O*Ilh3P8Df6b=i`t5&;%!XTtMpM+YhIgG!z!!4^u8+nyS^r0jRYxVkK*e5 zQ6~eWC>UG<#3fj&f7YGe=lh}2xzZ>@ev-Om-voi*RblJtS zMxRB0NLkZkA5E_1b+Ink#OtjRrd_Oiw$W~5L7L<&p4cZH$TV3&d!e4w^lVhDsiQCN_VUBUbTAFf8L5~J$ zunX)no94gBY>J;ZwU2=xyC^Wr_V#wARcQvswwMy-#*Iv&1&B@6sx>fdFL&jw{7V!eK;KM2SISWD#L%NFNz}KIDRl5kE^UT zz687vd7l+)!`slxReRYOzgrg|{bMn;wx%Ezk;ZL8cqVCTFCyYeK`J8RNkJ+i;z>a&BH}6c zV$-HA7Rze7zP@HMnOK)08{+o%Hgo$@kcMG+HJwgR&d<+VFG}o%VR&U-LtSwkpWNKs vSeGFiCngNTN7glnh=_=Yh=_=Yi1f*S+>?m$?Khei00000NkvXXu0mjf(XMS9 delta 1195 zcmV;c1XTOf39bntiBL{Q4GJ0x0000DNk~Le000410000b2nGNE0PR!JT@Vow z5fKp)5fKp)Q$c#d?(XhJ5Cq#ke~OWQisShA{r&wXzU!!BJRa}(u0i@M48!xuWOB4R z?N+)`5Cq#n5Ik(JEE#~izz@EQs6zkiQpbEgKL9>lopvo$6O+lL@q(oPqA2oRLT#hb zi1qb#-(^V8oSmI9o6W9G4?WZ(A~IMCRS^+~6sjU34k=VcL>yA6iikL*e^3<>aVYnd zDjPu%5XZ6geADT+%NNy=Rm&L`aq)tK=ibJKS zebtb0Szpx?LQ}H(#x$6-f97RPb8(WYAOzk5K4S5OfwkrIpPJmLOQr{{&2mjiwz;}( z(_qe;mo=?QUzD}C>0{GrS(0c4;Z=4}gz>JHUTD{~x>Ut0xKKYh!8 z(*oRNpUa-lR^>EQS3{tSVURWOV;kmO+^;Ii2JLK|o}O+1zXEUb;@yww|ChHPV>vlF zVKf?9Et56iVfqX&f9pACpOp>Tby-t&wtl6W9L!a3sa*wI*{Hn_b^FFfl{XUdY;A2l zIXpbP59|P+u((S72lK1bZ-ArHRt?zP+^iMoWux{!Bth54_f7_$! z$@;qzo<)50jiVFQQ{cPh=T+c6U>A4;_?zPAs7Jt$bv9nrf7+Vecv;tiBTw6J8YJ6v z)jxgd=Pb@g|BDXLq661vgxbewc3JS$9nf;oH+k(moKXG(z6IW75vpG=r@+N5 zsXL%$yKb9yO~GbYe7p(Z7JnmXA#~0i-@z3)L_T&*$^`!SV5N<3-6Z zgkgB@yN0UbI6k<%y!2g$^i&vzUVaEjL_|bHL_|bHL}V!b2MGGD;5#UPuK)l507*qo JM6N<$0fIc6R`37- diff --git a/DOCS/html/group___s_t_m32_f4xx___system___exported___constants.html b/DOCS/html/group___s_t_m32_f4xx___system___exported___constants.html deleted file mode 100644 index 751b9b2..0000000 --- a/DOCS/html/group___s_t_m32_f4xx___system___exported___constants.html +++ /dev/null @@ -1,94 +0,0 @@ - - - - - - - -STM MATLAB Simulator: STM32F4xx_System_Exported_Constants - - - - - - - - - - - -
    -
    - - - - - - -
    -
    STM MATLAB Simulator -
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    - + Collaboration diagram for STM32F4xx_System_Exported_Constants:
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    -Generated by doxygen 1.10.0 -
    - - diff --git a/DOCS/html/group___s_t_m32_f4xx___system___exported___constants.map b/DOCS/html/group___s_t_m32_f4xx___system___exported___constants.map deleted file mode 100644 index 94e7556..0000000 --- a/DOCS/html/group___s_t_m32_f4xx___system___exported___constants.map +++ /dev/null @@ -1,4 +0,0 @@ - - - - diff --git a/DOCS/html/group___s_t_m32_f4xx___system___exported___constants.md5 b/DOCS/html/group___s_t_m32_f4xx___system___exported___constants.md5 deleted file mode 100644 index d2531c7..0000000 --- a/DOCS/html/group___s_t_m32_f4xx___system___exported___constants.md5 +++ /dev/null @@ -1 +0,0 @@ -d133d47020d091ae9c9f367f3755cfc0 \ No newline at end of file diff --git a/DOCS/html/group___s_t_m32_f4xx___system___exported___constants.png b/DOCS/html/group___s_t_m32_f4xx___system___exported___constants.png deleted file mode 100644 index ce36be105bdd0087465839322e5cabebb1629d39..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 1734 zcmV;%208hOP)9h&h*d$d_*r!R4?qPUei z24Gt(m&+4L*P8oiFtAq+4i0qb(xu#C0HgNc!2>N8i?#h_hFAaqTZje&01$)*0{{?& z1_J;Pga!iu5M*tZ)QuZAUMq^?YK~wqepOZ7na}6H<&Fcu@YWiPqA0F1UmYITC4HYe zh@l)GAFu73PN&XewsY$LyV7^1*Ss#~nC%=}etq(l+qMb$JC9wezq|8$7~4`17>@6a zvx{7BvU{qeH%l4nCsq~7{dTYz*iCEt|WjO z4F(V?wgRu85}Jnov>5V~V{ZG7b>Ztqvu)Qe^PG@#&GXH4Qa^2ll%p%(nD|5Q-Iw1c z_-PQp!K~5)9muHb#wW;#oE%0jiqMh)$9Uv9Shm6V+tK#GGnr-uWu_W zGY(e_ZSi+GH)W$ig8_KhJ{5OqI6^DmkZ}>){?LK-p|q7-Ok=c3>@npOlg?1rr}(?s zo^ZRO!2kkv`DB_}A9?#K?bxRaSNc+T?6FTMW0{PRqO4*KeeX0FfWsJOr8ISk$JY1l z>dJ_nsg*KLQ|Jsd^W2=el+~t&zV~E<-bGQYz4}T!^jPz_Z9fKcS<=^%PI3p5ldm#q z`=r>l5~}zysr&(c}6}a!1&!*+p)+J?&D>jc< zZG+xzWz~$+wckAEiX-ISQ;u6St<{{9$>gXgid!)S-)DmnlV50_b%U`b74QG#Y%q?G zk5yIG_1SFZ`lk0wlHQl}g`~r?eTAMq$v%|yM!!+I-Mo3TVgaRb8C$nsAGYxx&lXTR znayUyt+>~$xa)t-%G|8HQ&r}+JZ<@!`)%94W1(?K@}^8hS}IbD?WkEC;F$7w8fn6IlN_InLu_~f19e)dJOCk$KV-c}je8kW%X+q%GP za`*ptZG<+7Ii`$5(z<>7_6L%_lk}=__?+bu(`8B7{s4=`LI(#2xw79GslFR97JbJu zrhDB~FI`f7j9auxk(aOXj(xglUeny}1O1HMHp$2Ak=cT|&NNF|o&X zNrjYS*F1Xgx1=Annkn^)R!<*yv>LN`s*Gb7=&t$0e|^pEcjY^#bg+`_(_cM{r}?rS zZ*H5%UE8j7ZF&0g2+hxyzwcZhS9x^3&bKe-o^0C*{UvE8>1|1`OZrCAuUa)6*b=TE zIiwQaUvw9sZ@)|WR??f2-pL#b5^(*rNz9rQzUyMwesJZ{Weo}VjeZPc%zRx_p@Z-_ zCktfoNA3WS-X`lb*v_;4v__Xax}*a?8jKC3{C)(mt73jbs%siK*PGZUG#CJ~$g%Fl zP(N0q_c7Ppo6m8-SHOowVT>Bpvyrqk(NN!Kjr0@xv}1A$nKVE}uIMgg&yB?SNoLW2PS2ttDa00=^Z z0RRZXpf~o)8W);4F>i`RaGZXo;=AN2Cx;%vb>u+1^@s600000 c0Dutx0mcd^Y?+7Fa{vGU07*qoM6N<$g1<{9 diff --git a/DOCS/html/group___s_t_m32_f4xx___system___exported___functions.html b/DOCS/html/group___s_t_m32_f4xx___system___exported___functions.html deleted file mode 100644 index 4c63ab3..0000000 --- a/DOCS/html/group___s_t_m32_f4xx___system___exported___functions.html +++ /dev/null @@ -1,156 +0,0 @@ - - - - - - - -STM MATLAB Simulator: STM32F4xx_System_Exported_Functions - - - - - - - - - - - -
    -
    - - - - - - -
    -
    STM MATLAB Simulator -
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    -Functions

    void SystemInit (void)
     
    void SystemCoreClockUpdate (void)
     
    -

    Detailed Description

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    Function Documentation

    - -

    ◆ SystemInit()

    - -
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    void SystemInit (void )
    -     		-extern
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    ◆ SystemCoreClockUpdate()

    - -
    -
    - - - - - -
    - - - - - - - -
    void SystemCoreClockUpdate (void )
    -     		-extern
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    - -
    -Generated by doxygen 1.10.0 -
    - - diff --git a/DOCS/html/group___s_t_m32_f4xx___system___exported___functions.map b/DOCS/html/group___s_t_m32_f4xx___system___exported___functions.map deleted file mode 100644 index b699351..0000000 --- a/DOCS/html/group___s_t_m32_f4xx___system___exported___functions.map +++ /dev/null @@ -1,4 +0,0 @@ - - - - diff --git a/DOCS/html/group___s_t_m32_f4xx___system___exported___functions.md5 b/DOCS/html/group___s_t_m32_f4xx___system___exported___functions.md5 deleted file mode 100644 index f909246..0000000 --- a/DOCS/html/group___s_t_m32_f4xx___system___exported___functions.md5 +++ /dev/null @@ -1 +0,0 @@ -ae8a986633f46dcc61c1582c45840718 \ No newline at end of file diff --git a/DOCS/html/group___s_t_m32_f4xx___system___exported___functions.png b/DOCS/html/group___s_t_m32_f4xx___system___exported___functions.png deleted file mode 100644 index 1509f839c38739f0bfd8903be251825cfb41ec84..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 1697 zcmV;S244AzP)YfKo&{(I7$4y#tg6DF`GAt^x{BE(PMB z6z2pl0A2>Pmi-0-*Fkeq8X8h11$~+XXo7GN>4XG$DeP62^~~(ddUt2n{(dAY*}wDb zST~P%X6%&!0000000000hR3810O-qPGC58i127g@mOYwIr+3Tio=p`D&^Keu?bI;< zW3gN=PbFP1uOne#uN)p8>fqoYbr`^)J$Udyi^XDNeU=~=0Kf>5FaQ8SNEiTsAS4U` zKoAlJ03gW5EUB9}Z@z4dxt1ar3}2q-KhNj$UsJ~cpnn?)!x(do`ReevA?dr+LGI}sFqdk0(5N)SuSD<9bc-(WK$epS69_I zTrt$e-(=r5lLiR`@UVRA%{Z$fE8*%G+)0(VHuhzLIpBI*^onjY-`n z#ior=(f41T20WAo)|aH38p_>9RUdKnQAR6w7{(aodG1~B+Na66i*>$jb#aYV(|Szc zMM=k!K9=;lR!?_)m^7kDuD;(c8eCgh)j`Xq1KU332D{pT`?mRPTW@t;Qnt8a%ZODs z=v`M=vLRl3wjLO1E3LZsj~cX;_BV?bn4dUgP=!N~g2g ztiLDjl^gEj-)duCZM@rR%xz`b%B`-qE&H~G#v#dj4%>3|INvq-%IK<&*PhcVIUGy+ zP}1{~mXe-nB4$D$zq53x;kRN*D!=n-fdjZzG&?Z!`8UhHAc3?5_lk}~mmnxetSPrSWA}QG$uvjc~czBqq_?^+#cLRo^>sW?# zt=sCPOR9@;i#lzTGMOBjDh z`m)0iy)Iq4v^T%93v{8=SyFuoDZkwR?>a7I_EnRl5ff*V-$R&I7cX8+RWz^@2LHvqwz`>o<0oASY3S?5cG@npW&cXLvwlq^ zy(8%}N$+blJE}ZG3L{lFrL?aYcByM;tU4L=F0U_Z(wN!KZJRaZD>pq&Ku05Fh-96S(!=SlhnGfb?4X^jFN{DZgyn%gfd6 zu4UJGZDsn(2rbW6zHeV2SA8@+&bKb+nrzE0`cu+O(wmZAk@U5sU$h$Q05DQ?7ocmu zN%}_8Ym(kd91A+o_Ol>dzkgMCT+{Lpj&6c2_+}@C4#KCLERewOsRKYW+x#p^?6V;1 zeuiY5=R(B%s3A6yFt*U<_alHIYx9{DU6hfsynRB#0I(PO`k}&IM#2EFH|Ubu4ujqR z2BGVLXa>5s#~lWMtu%f1LdAGcK06U21K_C=k7{Hz*DIgTH zqyPXxNEiTsAS4U`KoAlJ03Zm1-qTFlguJ=hpQk4D5|O&rhE`d6GH| rU=*?}yPG-&0000000000fDr!y)KUGQ_7HTh00000NkvXXu0mjfkorP2 diff --git a/DOCS/html/group___s_t_m32_f4xx___system___exported___macros.html b/DOCS/html/group___s_t_m32_f4xx___system___exported___macros.html deleted file mode 100644 index 25cd769..0000000 --- a/DOCS/html/group___s_t_m32_f4xx___system___exported___macros.html +++ /dev/null @@ -1,94 +0,0 @@ - - - - - - - -STM MATLAB Simulator: STM32F4xx_System_Exported_Macros - - - - - - - - - - - -
    -
    - - - - - - -
    -
    STM MATLAB Simulator -
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    - - diff --git a/DOCS/html/group___s_t_m32_f4xx___system___exported___macros.map b/DOCS/html/group___s_t_m32_f4xx___system___exported___macros.map deleted file mode 100644 index ad779a8..0000000 --- a/DOCS/html/group___s_t_m32_f4xx___system___exported___macros.map +++ /dev/null @@ -1,4 +0,0 @@ - - - - diff --git a/DOCS/html/group___s_t_m32_f4xx___system___exported___macros.md5 b/DOCS/html/group___s_t_m32_f4xx___system___exported___macros.md5 deleted file mode 100644 index ba7aa16..0000000 --- a/DOCS/html/group___s_t_m32_f4xx___system___exported___macros.md5 +++ /dev/null @@ -1 +0,0 @@ -7b317a98d223c620d4615fc1bd500b35 \ No newline at end of file diff --git a/DOCS/html/group___s_t_m32_f4xx___system___exported___macros.png b/DOCS/html/group___s_t_m32_f4xx___system___exported___macros.png deleted file mode 100644 index 93aba28433588a300883012a75f1e87fe82ff5df..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 1710 zcmV;f22uHmP)psT((Lyjc{*)f~ZK{Hm(DJDbgZ&m9MV;jJW$qA0F%zdAgwOZp*q z5JNdSI$BvbnM|D9Z2Q#zca`rduX$X|Hrqb7`cm>;w@nlBK95~r@4NGR7@Kk-FdW|> z&Ng!Wk=5(XM%(o_<15FvPrc5!trqh4I@J5ucHL5xo!S`M!(8Xy#2f}N0=|YIcOwDR zNEkq**ap1rB{U8FX)&aiV=nu)b>SOEvn|&zbDxlX&Hc@C`tEIoTt`>EG4Y3p|oAMm}In0>@n9VrktUU@8f;5 z^>Di)VE}=;d@}7@in@J`c5Ls$RlXD+du$J7EH`8HajjwveeNU-z+nt`r8ISk$2Ruu z8p?>hQ>)K7O`&(7nfvC{FIr$os zwoi&(8=-pazj+(*SQ=PglIm(Ky$#b4aSc&NFFlN+C{$IIcfD($E@jv2eB0XM+EiVy zV+OBDI*|0aq<6J^y5qyF5k+#1{ibMeZFQNGmR%>deVPrn*?{}D`K){0+J>ZTamCgV zt8LP|?OHYCbgehHx#9>p_de$>npRrQ!^6Xaq9|^~T=iTp#b$!$O6-ggT`cl&V*}6i{d$JEDy`45nx0^R_Ry;syT*fx+m%=8V4WY&Jxp!$-|yLmS1mm_i%H=Kkh!zHL5T6OHRQTm3Q1 zZPz$LDe0=74>?_w^sl6IXWK~@Tg*4q5&OM{F?{mw<9v2SZ#@iKm@g zjOkq0m1IaN#k@tEKI-x{-m$%l<}uCX6vquUiC+|j_V@RHnayT1NuO!i!?-BvslpP* zUy{B~7^2sO3m10gS9XCElHMgXl#u$H~h?Y*S;up6h>Rj*5_Ep}gWN>yji zo=Li+st0c?rJ$_@l+Y-E|8WhDUd9-Pj5X8^Ao&nvelgQ zHMhH#UFF*9^wkkspRIo1zCNz&(e*grx|nmaE%)eeNmEJhNqS4tw~~I-GI0RdP@^A` z!p8eU(sz>Hk@SA%Sdf72TgASgKw0Ox5bKnK_3`6_Yw!(Cg-*ifyjdWFKXV6wd{R8? zA+{W>haScnTti|plkmVcX!bIEKb0O+Ue{y$I1YC7FaQiD^)S&;KSsE#NEiSHVH++= zfg!1M7?J|ei - - - - - - -STM MATLAB Simulator: STM32F4xx_System_Exported_types - - - - - - - - - - - -
    -
    - - - - - - -
    -
    STM MATLAB Simulator -
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    -Variables

    uint32_t SystemCoreClock
     
    const uint8_t AHBPrescTable [16]
     
    const uint8_t APBPrescTable [8]
     
    -

    Detailed Description

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    Variable Documentation

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    ◆ SystemCoreClock

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    uint32_t SystemCoreClock
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    System Clock Frequency (Core Clock)

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    ◆ AHBPrescTable

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    const uint8_t AHBPrescTable[16]
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    AHB prescalers table values

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    ◆ APBPrescTable

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    - - - - - -
    - - - - -
    const uint8_t APBPrescTable[8]
    -     		-extern
    -
    -

    APB prescalers table values

    - -
    -
    -
    - -
    -Generated by doxygen 1.10.0 -
    - - diff --git a/DOCS/html/group___s_t_m32_f4xx___system___exported__types.map b/DOCS/html/group___s_t_m32_f4xx___system___exported__types.map deleted file mode 100644 index c66ed6c..0000000 --- a/DOCS/html/group___s_t_m32_f4xx___system___exported__types.map +++ /dev/null @@ -1,4 +0,0 @@ - - - - diff --git a/DOCS/html/group___s_t_m32_f4xx___system___exported__types.md5 b/DOCS/html/group___s_t_m32_f4xx___system___exported__types.md5 deleted file mode 100644 index e6317f6..0000000 --- a/DOCS/html/group___s_t_m32_f4xx___system___exported__types.md5 +++ /dev/null @@ -1 +0,0 @@ -0e8fb20957bf5495fabf96319b6073ee \ No newline at end of file diff --git a/DOCS/html/group___s_t_m32_f4xx___system___exported__types.png b/DOCS/html/group___s_t_m32_f4xx___system___exported__types.png deleted file mode 100644 index 35173796718533743a1b85c2ed7616ac860ed53b..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 1692 zcmV;N24ne&P)*>*(PmGRdrQQS69#O_X9)H|Eiv@ zVe6T$>Y0`R0000000000rpJ^H02s^R;o(8)7=T?-Rn^1UY<9Q3?)g%|0An-8d{;UK zU{|bGt7A#m+v`XeI9K-e_H^aSmC|7VlXn09eJz*EjrCQ5SO5S!h=c(Eh(f{u07M~S z005$pFaQ8iHtv$TdGqG$#+Yj*g2D9Fb$w^CSo~f(4gllZNEpVLYuvAnfE$v&FCD~K zj*gBt*3D)!?>5&y&HsJn`^sw{m$J>ZkE_0%LhZI|V&3Pe8|r=ceh*_;8Uo`9{o$NN zzCW^Nz1?a1{$@hug!XCHg|;2JHhS6Nh&CA{=W?y@MyPTn~wqn}RS8q!EvF9GDZyWqH z2;gCN^ka|xr_>jk;|OUFdAWwULc?NRWv0f`uq6VQ;@VYx+p&OG zBppclRMOj8Ki%;`(TEcH#(r~jxURbFNz1+y+ac`^+wQ6S6r!er0SaV z?rN)coWAw;HeVbu=RV}TMcYQtd3bnuV2t@LrQvfXjFkFf>ueInj&!{LQ!-&39UZBz z>l^d=-1klImn6L}>2pc@r|XQKUCBO>^k&{D{chd5Rr3I)X_?xvUk-QIp!_83{h98^G?0GXdlyF&T-sWllaCM?eFjZyjUz2l0MP;3gfb*CyGlLe@Xf> zV~9bQE?qh|zp@MDko7L9vBcEh9{=|p7jySjpQMozXP@K7Ym2y)vU{@EA~)w%2nsUo=W;f z>v@cqC4DIAN3G{Go@$*u0GttnB#frxvtL7Wgs!q(cMWa(g~4{Y_K;9$TT1MyLsBvA z*td=h{*m;P)^|$1s`b^!9j)gqo~Yp51;#biFVA6ngI!_RpWt1St@fm^z1_F$E7w(L zsE*kBT=j?c4e_-{-{V5-QqIY>JfOcN%_Y4f=?zI=OZrXg!~tMOO@2rUJMRxk-$;5( z(z}IYL1w<+u5#^T@1OFlh^}qOgC8Ho7dSvmmZ)#u0e`aCP5>)8;< zgDZ?J_=dz%CgFjzuKl}4sn7CAsRQ|Og#lo)LO=R9_R|nS!T>N~vCqL^NNOAmNdd@i zn`eQz_G6;E46ZN$3@+spf1hVXFeFumH(~Gw0O+IdlL1r9qK_KiM#8A7>fvg&I=*-B zUWs@xaaC14EFA-YGBy&%Y&N?q>AGWI07!m*#FU0DveY z3;;kB5(WSu3JC)M5QRx^oGXtWJ<@WyEFA_gX(uNq&h;b=oEvprA3uKlxO5o6PN=Ht mZs`~R0000000000V*Cf;isDb4RL`sc0000 - - - - - - -STM MATLAB Simulator: STM32F4xx_System_Includes - - - - - - - - - - - -
    -
    - - - - - - -
    -
    STM MATLAB Simulator -
    -
    -
    - - - - - - - -
    - -
    -
    - - -
    -
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    -
    -
    -
    Loading...
    -
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    -
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    -
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    -
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    STM32F4xx_System_Includes
    CMSIS » Stm32f4xx_system
    -
    -
    - -

    Define to prevent recursive inclusion. -

    -
    - + Collaboration diagram for STM32F4xx_System_Includes:
    -
    -
    - -

    Define to prevent recursive inclusion.

    -
    - -
    -Generated by doxygen 1.10.0 -
    - - diff --git a/DOCS/html/group___s_t_m32_f4xx___system___includes.map b/DOCS/html/group___s_t_m32_f4xx___system___includes.map deleted file mode 100644 index b699725..0000000 --- a/DOCS/html/group___s_t_m32_f4xx___system___includes.map +++ /dev/null @@ -1,4 +0,0 @@ - - - - diff --git a/DOCS/html/group___s_t_m32_f4xx___system___includes.md5 b/DOCS/html/group___s_t_m32_f4xx___system___includes.md5 deleted file mode 100644 index 0d11f69..0000000 --- a/DOCS/html/group___s_t_m32_f4xx___system___includes.md5 +++ /dev/null @@ -1 +0,0 @@ -a26b61f5bf267ad6f9b0ac3b6e1594dd \ No newline at end of file diff --git a/DOCS/html/group___s_t_m32_f4xx___system___includes.png b/DOCS/html/group___s_t_m32_f4xx___system___includes.png deleted file mode 100644 index a166c0d29abc3e40b233cd410a8ebc8a4b1af629..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 1439 zcmV;Q1z`G#P)YFnP;8d z8PAIofQX2Qh=_=Yh=_=YD852ZI5;?XqbQ2q6v0sbs;c_+=;-M8)Nyn%olf^t$3T>` zvMev>^Z9c%?XiAPQ53sHQ5+8!7LCkP0NbmiDawQ>IA^YYT8C4(U{NY(F3A! znayUYL+EWXnP6vUCv_M^*}1s5z;e0VNG}t_LPSI(!A63Jh^*L15D}3T8wnyJvSK4a zL_}6>B#4N}%DM#BS5a&{mxrpVqU5dSEA3PFo64 zmISNENXyC9{d#`tc|QA0$C%2CNxE)h6Y83E&1a~enN5&J!dBs`>0K*j(|Jvrw686$ zu^Lh1_7Z>(06at8FgybAZ_0eLaO*!DN;&N=OolSdi7sDO-~PTr*A5= z*>>q&m}0eUx5Z(4PcGZ0YvX#Xete8;yjB8u2f()g{sizN>Y=4A)Q!WvYao0p?WQ-N z8v2gdr8lE*OZ&QzhR96Y%}YPV6%MwmA@!)Z_VG8=gKf`&?rer>Cdy0{8~NMBC-^S$Yg0 z*$?3A>I##I9=6PM_uJ)*=UU;qe92Aeu9M?KX}fMd4N#xheXdiVeES|Jo!_-r5bC`~ znUe@~r|Km{SyF}V+lx@oQMY59H{?Y8-rnBN=jZ3&0r(WaXQ)>${R7|yhtu!Y=OwYd zz1{1#*M_(Q?JGvvQbq0Ci?HPnxX13>6S)t+c+!Wonk`1pH|px9p}3T9n-?+lP<&TZ zNxBR-`JR{H+W)qGeGOn2z&`4srI&`7_Ys$xE z6_rofA+DRxut`ooqanCni%_56>>s9UyGwShc$+c(=GCOd)E2wcAjK*(uoZw`0DJ}D zRn#k+jsg6QxetikxeE^@MZa9Du+>q#Oy@^&Pty0gwGEq?;_@vc7T0*Bxdxworg@&WvVCpT?9=IVzbK01 z)EE1qNIg{NV>X+is;Z}p#lmN7{}t3vT0aBuHtMCZNgN&?R{WzwdC6@^?;%_N(V>&Y zV)4JfOgFl_I~tw80L)Q8OYvsnScu3|_D@{rOd9`pok$-`FCvgXQU^f&Nn_tWliNPW z#}wlI+-GbgdIftxQ t%2rvH&r`=hL_|bHL_|bHL_|an(|-&#n(lsl1Xut7002ovPDHLkV1gNm$+Q3f diff --git a/DOCS/html/group___s_t_m___s_i_m_u_l_a_t_i_o_n.html b/DOCS/html/group___s_t_m___s_i_m_u_l_a_t_i_o_n.html index 44026c1..670860d 100644 --- a/DOCS/html/group___s_t_m___s_i_m_u_l_a_t_i_o_n.html +++ b/DOCS/html/group___s_t_m___s_i_m_u_l_a_t_i_o_n.html @@ -5,7 +5,7 @@ -STM MATLAB Simulator: STM_SIMULATION +STM MATLAB Simulator: STM32 Simulation @@ -14,6 +14,7 @@ + @@ -73,36 +74,36 @@ $(function() {
    Topics
    -
    STM_SIMULATION
    +
    STM32 Simulation
    -

    Stuff for simulating STM32 in MATLAB. +

    Ð’ÑÑкое Ð´Ð»Ñ ÑимулÑции STM32. More...

    - + Collaboration diagram for STM_SIMULATION:
    + + Collaboration diagram for STM32 Simulation:
    - - + + - - + +

    Topics

     MAIN_SIMULATOR
     Stuff for configuring, initializing and deinitializing simulator.
     STM32 Simulator
     Ð’ÑÑкое Ð´Ð»Ñ ÑимулÑтора STM32.
     
     PERIPH_VARS_FOR_DEBUG
     Varables of peripheral registers for debug watches.
     Periphs Variables for Debugging
     ÐŸÐµÑ€ÐµÐ¼ÐµÐ½Ð½Ñ‹Ðµ Ð´Ð»Ñ Ð´Ð¾Ñтупа к периферии в дебаге
     

    Detailed Description

    -

    Stuff for simulating STM32 in MATLAB.

    +

    Ð’ÑÑкое Ð´Ð»Ñ ÑимулÑции STM32.

    diff --git a/DOCS/html/group___s_t_m___s_i_m_u_l_a_t_i_o_n.map b/DOCS/html/group___s_t_m___s_i_m_u_l_a_t_i_o_n.map index 66a6041..549dd65 100644 --- a/DOCS/html/group___s_t_m___s_i_m_u_l_a_t_i_o_n.map +++ b/DOCS/html/group___s_t_m___s_i_m_u_l_a_t_i_o_n.map @@ -1,5 +1,5 @@ - - - - + + + + diff --git a/DOCS/html/group___s_t_m___s_i_m_u_l_a_t_i_o_n.md5 b/DOCS/html/group___s_t_m___s_i_m_u_l_a_t_i_o_n.md5 index f947cc0..d23c698 100644 --- a/DOCS/html/group___s_t_m___s_i_m_u_l_a_t_i_o_n.md5 +++ b/DOCS/html/group___s_t_m___s_i_m_u_l_a_t_i_o_n.md5 @@ -1 +1 @@ -ebac5ffdb4c5dce9a441ec1bf8e0d308 \ No newline at end of file +f600ae11e76a0b0267dafc6c73c45a25 \ No newline at end of file diff --git a/DOCS/html/group___s_t_m___s_i_m_u_l_a_t_i_o_n.png b/DOCS/html/group___s_t_m___s_i_m_u_l_a_t_i_o_n.png index 2daed6148203f53f348edf4215459b197f736fb6..cb3ed31a3c52a49178e5d9232fa2de775df28fcc 100644 GIT binary patch literal 2622 zcmV-E3c>Y>P)FxyAYi08r#Fu z?bO!vQ~gwRRae!__XAB&*UMA?PEx--Pd(k$AW4!WNs=TK%xmKzIdbRes{D{jMR5omVFEON!N8~F}An29{?^^-Oqs3zIEitkq@7F=9!Om zU5DCp_3Blge){R!`!6+EizMwS2BaiK7?6?_VL(b!gaIi@5eB3rMffovDN&Z~{$9ms zG>Wd9w$0@4So^W|^81yot6FzTU3Ik4W)}=dDM9RnpDa%eoU(SxwwWv|TUV!Um>sZf z>U)qn#Fl!dEHL^UCVPNoACXQF9?rGOTQ?H}WYA^qK+9iXkuiIuoN{OcRy6T*)`CuqJ;ZuSk zB`~ViU0gSBAT=3ii|%O~kWvlv^r)Ir=h$7m@<6`>?#~$O9`gUK2Me};#kE=lhhB3w^?_r?XvA=&Ej`48CJ%C zloF+$tSOT&vtFmRF;6`y$F2H0WxHALv&r{9FNfHY6k$M0QiK61Nf8F5_Mmt;D2Bh|~1HcOKFz_Sb72t2cjSCkpJkn)h8U|;v)wC7hodqBBZs7R%aU%D;0xSc! zfPVm&fD6FSPoF;h72x{|u2TbJK&mPC1J41cfcsiH#wUT#0ITc-;Oh9;ON1c2LI}cF z$IlnX&;QOhboA)a&$m>g_7DS7^ST#!3i!eJ^)eyIuFuitVRpjrMDF<*kO4P=w+Z3* zdv-$bGVoFAL2lf*abSIYeU38KciY?BbM0?Hs;;|%Cx9mj*ZP)o>y86&B(!mu-66P2 z2weyv`!*r`ULp+LF9B}>|DCh`i`(1VuWoK`&e@EHU^E)l`XBbNz8I-KH~>5bJPRD+ z_F#n2gL@o!Ik)USZV$l~;6dQXc>OhY!tY}4c?%fkmyWe3>{=SN4B=Mii;iso(E17hPGuN4?6&yBn*#V1AfWQ^}!oW*DAFs8j$zgbI&5{P>-gx;n!Xim~-m(gg%`Sa($0sNZKBOFm}QsiF3B+dsdlqW5W z-=xtlS(b73?Abp6p8y^Jz6bn*@FDB`^}<`@$F3#_*B+%ovj?d%Hwm-J7YoZj4SWIk z;`sR_@Hya4LT@u8%vSpu8V#BOsXG2Se!P}jwhVlho#1qMt-&)O)s&A2Gu4*~-)@lx z&ufs96wydPo;!Cgd3o8kDeKDGta7|rwX`X<{kH3nRBmuR$g-OYc;f*{O=>kDs|MEk z`ueV3)46l!79M>0nNTj#9ps?6edF)=3XH_b$lBVPcN0=&OG`_yudlB^pI>G`s*aQ! z=6+M9S^v38;Uzn3};NX_eA z;2dER=Q-dMq31V`YlQ2Vn}y|vfa8SFyq^%9-(}~T=!d}NH{X1-@&TuvbahYkMV`P- z>uc?8h3+f{q?&RW_&TBI*OvEz*T;{%y9t4L0yuH-;K2u5tf5y%qfsWSi95 zV(+C615!#b?c^+b9ox5TztruDV!@W$R%#El$}#Hf6KiAE`>WDcRR*NQ^og1(Cs^6G zb=TFcrRu(A!P{0%ZMWA{TLz>=+6fh#?QTPUSU!23vVCl5S-18k-gDWf1e&~z&;|oi zO0?(`xTzsy*|obi_A5&5LHBV|$(vP3HBAzBpOlG-E_;&2b{5$quge~!lwh9W z;H+8frjIx4_^H7(YrmBG%HBs)|4ggyTZI9seQ(~0lH&5%Ol;Ntn*5M@F_`MqP_|!c z8>#iCY*%-3sS1bKk`!S;N>YRYDYd9?v$CqjfRv;N15%PAoW+(pH1Ag&Cv7ZpDBs5q zbhpKTlsY!;Yk_?Zpgz~uG>6zy&s6y^x7uYuN&}H)+5aD9>x;`~z0TinF=gGfzhiZk zwLb(7v84fM;@*s9ZB7fv*t%Km#Qq*4dyvu|Fz zN&_*}Uf7U1#Fly{#aNru+OKmD$<+3T z!hn=I)Wi>i%`=HoXI*o-fY@=%iq_mGU@pA}u+aCgl z*pd`sKuS`C0Vzol2BaiKI7y>DX=7u9jg5`2%h13XklJ%bqtT;X*P!89T3Wi&bq$gv gNs=T~1zl*n<*fM-VlL>{SHO zBoYq>%`gZaJO~O#LJ%Yh3LZo{BdDNYG@cB2$=-w&Wey^O(QL--(M%$eq-Z7)Nm4YEh$JbRNkozq%_Y84OLRIN`u%?C z$3wT5eST3Kql)S&b6nFNOUU!`jP7r=?4-x@%C((IL~4>7&I<4@lB944`w8MWNs>4Q97>hH4D0~U1AhXZT3K0nY>x3t zGhq@@9c}_&fo^ga8QhcB#9_5N!$h8 zm@1#ui+C=z?H|BiWGquVd-g0_TU&Kiua*dWz11Q&i5xw8be?gjWhVSnzXNy(_&RWu zq~|fZHuPqa;jP_~?ME2zIi&C3!T#r)-T+=CzZdZg@OsHZo11>W|K$1e=j#qbEz#|E z&($467Ux7%r5l0I1K%K7-g-kp*)H&1lDUWU^49}{$M=9&Nah=MfZqcbQulX&S1Uh) zIojOZytnQcq-mK%RE0yp7fE^^tAzhweH{2J@HgNrNrJdAxV=a+Um>Z%Od^VQ@#4js zfX9F@kqlv#u}9Kl`FYiGNtz$OJ4@60BhVZC9L{g-GI`1CF7cD=k{ZIEh@#zk>#hF= zem%HB^8a)<@DX4Q_!!Absy@lk)WOu#yCicUl3L6pqAL9l*c#l1jsYJAJ_vjicrVF> z`wGcQD@iR@$#B-j#zye=qOviM#l$jNrcB+T#~KpvuuPfrm$yA+Ti$Vop4&(}z%PI= z1MeqU!F3PtRp8IFtXR_QIVZ9JHa0fs^?GC5d%fORg2>u7XIFvW0pB4>B$8Terb#5L zVVhJw>)mtN{lvsF%ep0LQB{&eh7E9;VW(MXQY=N%32NTGg9h|QBrS-_Cf3vM*oO^N z%)9tu1DF0euUM+6TauQ^Oop?1y9M>FyaYTqxDD?=Gl*%-`uh5>qK;5nV%=`{T(8&rUV2+@61jBg z((EJBqWTX>GWj9!An+(~3rQjwCX-hgPapu78NWJW+A7Jl*^do=rf+u-e!e|b{uRc1 zG8cAtcRzjV)F}=hJ{)y`(z4m!-pGqlO8V{N8UcloSSs{S^TXhor7tZM5I6=FWQh7XKX`1O@gS} zu-?4-Lt>pa>E+ckX5|JfkIx`p%d7X_ETm3bquM59%EL+In6vota&!t^PUqK-ACD2CNYUffvRd$LME4I zS${}9c@yWuMrgD#Dq3I=dW`ASN%MZ!9s4(Fo6yySWjH4y)u;)RuVwZ7{juAm@>$2& z)Z=dB-=t0^5lLf0=0>v0H%U?QnnzD#mi1&ETi(*;S)T)kv!n{eOsr2cIo%dn$C%f^ zRe2t=>IfZLEBiMIt*5Gq_0WY0vF9L^Nkj?|I~f{UX3_+CmHQ4=HiqPx#07*qoM6N<$f--~1d;kCd diff --git a/DOCS/html/group___t_i_m___s_i_m_u_l_a_t_o_r.html b/DOCS/html/group___t_i_m___s_i_m_u_l_a_t_o_r.html index 042278b..870bca3 100644 --- a/DOCS/html/group___t_i_m___s_i_m_u_l_a_t_o_r.html +++ b/DOCS/html/group___t_i_m___s_i_m_u_l_a_t_o_r.html @@ -5,7 +5,7 @@ -STM MATLAB Simulator: TIM_SIMULATOR +STM MATLAB Simulator: TIM Simulator @@ -14,6 +14,7 @@ + @@ -75,81 +76,104 @@ $(function() { Data Structures | Macros | Functions -
    TIM_SIMULATOR
    STM_SIMULATION » MAIN_SIMULATOR
    +
    TIM Simulator
    STM32 Simulation » STM32 Simulator
    -

    Simulator for TIM. +

    СимулÑтор Ð´Ð»Ñ Ñ‚Ð°Ð¹Ð¼ÐµÑ€Ð¾Ð² More...

    - + Collaboration diagram for TIM_SIMULATOR:
    + + Collaboration diagram for TIM Simulator:
    + + +

    Data Structures

    struct  SlaveChannels
     Ð¡Ñ‚руктура Ð´Ð»Ñ ÑƒÐ¿Ñ€Ð°Ð²Ð»ÐµÐ½Ð¸Ñ Ð¡Ð»ÐµÐ¹Ð² Таймерами More...
     
    struct  Channels_Sim
     Ð¡Ñ‚руктура Ð´Ð»Ñ Ð¼Ð¾Ð´ÐµÐ»Ð¸Ñ€Ð¾Ð²Ð°Ð½Ð¸Ñ ÐºÐ°Ð½Ð°Ð»Ð¾Ð² таймера More...
     
    struct  TIM_Sim
     Ð¡Ñ‚руктура Ð´Ð»Ñ Ð¼Ð¾Ð´ÐµÐ»Ð¸Ñ€Ð¾Ð²Ð°Ð½Ð¸Ñ Ñ‚Ð°Ð¹Ð¼ÐµÑ€Ð° More...
     
    - + + + + + + +

    Macros

    #define TIM_OCMODE_SECOND_SHIFT   (TIM_CCMR1_OC2M_Pos - TIM_CCMR1_OC1M_Pos)
    #define TIM_OCMODE_SECOND_SHIFT   (TIM_CCMR1_OC2M_Pos - TIM_CCMR1_OC1M_Pos)
     Ð”ефайн Ð´Ð»Ñ Ñдвига между первой и второй половиной CCMRx региÑтров
     
    #define Check_OCx_GPIO_Output(_tims_, _OCx_GPIOx_, _OCx_PIN_SHIFT_)   (_tims_->Channels._OCx_GPIOx_->MODER & (0b11<<(2*_tims_->Channels._OCx_PIN_SHIFT_))) == (0b10<<(2*_tims_->Channels._OCx_PIN_SHIFT_))
     Ð”ефайн Ð´Ð»Ñ Ð¿Ñ€Ð¾Ð²ÐµÑ€ÐºÐ¸ выводить ли канал таймера на GPIO.
     
    #define Check_OC1_GPIO_Output(_tims_)   Check_OCx_GPIO_Output(_tims_, OC1_GPIOx, OC1_PIN_SHIFT)
     Ð”ефайн Ð´Ð»Ñ Ð¿Ñ€Ð¾Ð²ÐµÑ€ÐºÐ¸ выводить ли канал 1 на GPIO (наÑтроен ли GPIO на альтернативную функцию)
     
    #define Check_OC2_GPIO_Output(_tims_)   Check_OCx_GPIO_Output(_tims_, OC2_GPIOx, OC2_PIN_SHIFT)
     Ð”ефайн Ð´Ð»Ñ Ð¿Ñ€Ð¾Ð²ÐµÑ€ÐºÐ¸ выводить ли канал 2 на GPIO (наÑтроен ли GPIO на альтернативную функцию)
     
    #define Check_OC3_GPIO_Output(_tims_)   Check_OCx_GPIO_Output(_tims_, OC3_GPIOx, OC3_PIN_SHIFT)
     Ð”ефайн Ð´Ð»Ñ Ð¿Ñ€Ð¾Ð²ÐµÑ€ÐºÐ¸ выводить ли канал 3 на GPIO (наÑтроен ли GPIO на альтернативную функцию)
     
    #define Check_OC4_GPIO_Output(_tims_)   Check_OCx_GPIO_Output(_tims_, OC4_GPIOx, OC4_PIN_SHIFT)
     Ð”ефайн Ð´Ð»Ñ Ð¿Ñ€Ð¾Ð²ÐµÑ€ÐºÐ¸ выводить ли канал 4 на GPIO (наÑтроен ли GPIO на альтернативную функцию)
     
    - + + - + + - + + - + + - + + - + + - + + - + + - + + - + + - + + - - + + + + +

    Functions

    void TIM_Simulation (TIM_TypeDef *TIMx, struct TIM_Sim *TIMS)
    void TIM_Simulation (TIM_TypeDef *TIMx, struct TIM_Sim *TIMS)
     Ð¡Ð¸Ð¼ÑƒÐ»ÑÑ†Ð¸Ñ Ñ‚Ð°Ð¹Ð¼ÐµÑ€Ð° на один такт ÑимулÑции.
     
    void TIMx_Count (TIM_TypeDef *TIMx, struct TIM_Sim *TIMS)
    void TIMx_Count (TIM_TypeDef *TIMx, struct TIM_Sim *TIMS)
     Ð¡Ð¸Ð¼ÑƒÐ»ÑÑ†Ð¸Ñ Ñчетчика таймера на один такт ÑимулÑции.
     
    void Overflow_Check (TIM_TypeDef *TIMx, struct TIM_Sim *TIMS)
    void Overflow_Check (TIM_TypeDef *TIMx, struct TIM_Sim *TIMS)
     ÐŸÑ€Ð¾Ð²ÐµÑ€ÐºÐ° на переполнение и Ð´Ð°Ð»ÑŒÐ½ÐµÐ¹ÑˆÐ°Ñ ÐµÐ³Ð¾ обработка.
     
    void call_IRQHandller (TIM_TypeDef *TIMx)
    void call_IRQHandller (TIM_TypeDef *TIMx)
     Ð’ызов Ð¿Ñ€ÐµÑ€Ñ‹Ð²Ð°Ð½Ð¸Ñ Ñ‚Ð°Ð¹Ð¼ÐµÑ€Ð° TIMx.
     
    void Channels_Simulation (TIM_TypeDef *TIMx, struct TIM_Sim *TIMS)
    void Channels_Simulation (TIM_TypeDef *TIMx, struct TIM_Sim *TIMS)
     Ð¡Ð¸Ð¼ÑƒÐ»ÑÑ†Ð¸Ñ ÐºÐ°Ð½Ð°Ð»Ð¾Ð² таймера.
     
    void CC_PWM_Ch1_Simulation (TIM_TypeDef *TIMx, struct TIM_Sim *TIMS)
    void CC_PWM_Ch1_Simulation (TIM_TypeDef *TIMx, struct TIM_Sim *TIMS)
     Ð’ыбор режима первого канала и его ÑимулÑциÑ.
     
    void CC_PWM_Ch2_Simulation (TIM_TypeDef *TIMx, struct TIM_Sim *TIMS)
    void CC_PWM_Ch2_Simulation (TIM_TypeDef *TIMx, struct TIM_Sim *TIMS)
     Ð’ыбор режима второго канала и его ÑимулÑциÑ.
     
    void CC_PWM_Ch3_Simulation (TIM_TypeDef *TIMx, struct TIM_Sim *TIMS)
    void CC_PWM_Ch3_Simulation (TIM_TypeDef *TIMx, struct TIM_Sim *TIMS)
     Ð’ыбор режима третьего канала и его ÑимулÑциÑ.
     
    void CC_PWM_Ch4_Simulation (TIM_TypeDef *TIMx, struct TIM_Sim *TIMS)
    void CC_PWM_Ch4_Simulation (TIM_TypeDef *TIMx, struct TIM_Sim *TIMS)
     Ð’ыбор режима четвертого канала и его ÑимулÑциÑ.
     
    void Write_OC_to_GPIO (TIM_TypeDef *TIMx, struct TIM_Sim *TIMS)
    void Write_OC_to_GPIO (TIM_TypeDef *TIMx, struct TIM_Sim *TIMS)
     Ð—апиÑÑŒ каналов таймера в порты GPIO.
     
    void Write_OC_to_TRGO (TIM_TypeDef *TIMx, struct TIM_Sim *TIMS)
    void Write_OC_to_TRGO (TIM_TypeDef *TIMx, struct TIM_Sim *TIMS)
     Ð—апиÑÑŒ каналов таймера в глабальную Ñтруктуру Ñ TRIGGER OUTPUT.
     
    void Slave_Mode_Check_Source (TIM_TypeDef *TIMx, struct TIM_Sim *TIMS)
     
    void Slave_Mode_Check_Source (TIM_TypeDef *TIMx)
     ÐžÐ¿Ñ€ÐµÐ´ÐµÐ»ÐµÐ½Ð¸Ðµ иÑточника Ð´Ð»Ñ Ð·Ð°Ð¿ÑƒÑка таймера в SLAVE MODE.
     
    void Simulate_TIMs (void)
     Ð¡Ð¸Ð¼ÑƒÐ»ÑÑ†Ð¸Ñ Ð²Ñ‹Ð±Ñ€Ð°Ð½Ð½Ñ‹Ñ… таймеров.
     
    void TIM_SIM_DEINIT (void)
     Ð”еинициализирование выбранных таймеров.
     

    Detailed Description

    -

    Simulator for TIM.

    +

    СимулÑтор Ð´Ð»Ñ Ñ‚Ð°Ð¹Ð¼ÐµÑ€Ð¾Ð²

    Дефайны и функции Ð´Ð»Ñ ÑимулÑции таймеров.

    Macro Definition Documentation

    @@ -159,12 +183,15 @@ Functions
    - +
    #define TIM_OCMODE_SECOND_SHIFT   (TIM_CCMR1_OC2M_Pos - TIM_CCMR1_OC1M_Pos)#define TIM_OCMODE_SECOND_SHIFT   (TIM_CCMR1_OC2M_Pos - TIM_CCMR1_OC1M_Pos)
    +

    Дефайн Ð´Ð»Ñ Ñдвига между первой и второй половиной CCMRx региÑтров

    +

    Definition at line 28 of file stm32f4xx_matlab_tim.h.

    +
    @@ -190,7 +217,11 @@ Functions
    -

    Дефайн Ð´Ð»Ñ Ð¿Ñ€Ð¾Ð²ÐµÑ€ÐºÐ¸ выводить ли канал на GPIO (наÑтроен ли GPIO на альтернативную функцию)

    + +

    Дефайн Ð´Ð»Ñ Ð¿Ñ€Ð¾Ð²ÐµÑ€ÐºÐ¸ выводить ли канал таймера на GPIO.

    +

    Данный дефайн проверÑет, наÑтроен ли пин GPIO на альтернативную функцию. ЕÑли да - то таймер выводитьÑÑ Ð½Ð° Ñтот пин

    + +

    Definition at line 34 of file stm32f4xx_matlab_tim.h.

    @@ -208,8 +239,11 @@ Functions
    +

    Дефайн Ð´Ð»Ñ Ð¿Ñ€Ð¾Ð²ÐµÑ€ÐºÐ¸ выводить ли канал 1 на GPIO (наÑтроен ли GPIO на альтернативную функцию)

    +

    Definition at line 38 of file stm32f4xx_matlab_tim.h.

    +
    @@ -226,8 +260,11 @@ Functions
    +

    Дефайн Ð´Ð»Ñ Ð¿Ñ€Ð¾Ð²ÐµÑ€ÐºÐ¸ выводить ли канал 2 на GPIO (наÑтроен ли GPIO на альтернативную функцию)

    +

    Definition at line 42 of file stm32f4xx_matlab_tim.h.

    +
    @@ -244,8 +281,11 @@ Functions
    +

    Дефайн Ð´Ð»Ñ Ð¿Ñ€Ð¾Ð²ÐµÑ€ÐºÐ¸ выводить ли канал 3 на GPIO (наÑтроен ли GPIO на альтернативную функцию)

    +

    Definition at line 46 of file stm32f4xx_matlab_tim.h.

    +
    @@ -262,8 +302,11 @@ Functions
    +

    Дефайн Ð´Ð»Ñ Ð¿Ñ€Ð¾Ð²ÐµÑ€ÐºÐ¸ выводить ли канал 4 на GPIO (наÑтроен ли GPIO на альтернативную функцию)

    +

    Definition at line 50 of file stm32f4xx_matlab_tim.h.

    +

    Function Documentation

    @@ -276,7 +319,7 @@ Functions void TIM_Simulation ( - TIM_TypeDef * TIMx, + TIM_TypeDef * TIMx, @@ -285,7 +328,23 @@ Functions
    -

    Ð‘Ð°Ð·Ð¾Ð²Ð°Ñ Ñ„ÑƒÐ½ÐºÑ†Ð¸Ñ Ð´Ð»Ñ ÑимулÑции таймера: она вызываетÑÑ ÐºÐ°Ð¶Ð´Ñ‹Ð¹ шаг ÑимулÑции

    + +

    СимулÑÑ†Ð¸Ñ Ñ‚Ð°Ð¹Ð¼ÐµÑ€Ð° на один такт ÑимулÑции.

    +
    Parameters
    + + + +
    TIMx– таймер, каналы которого надо запиÑать.
    TIMS– Ñтруктура таймера Ð´Ð»Ñ ÑимулÑции.
    +
    +
    +

    Это Ð±Ð°Ð·Ð¾Ð²Ð°Ñ Ñ„ÑƒÐ½ÐºÑ†Ð¸Ñ Ð´Ð»Ñ ÑимулÑции таймера: она вызываетÑÑ ÐºÐ°Ð¶Ð´Ñ‹Ð¹ шаг ÑимулÑции и вызывает вÑе другие функции, необходимые Ð´Ð»Ñ ÑимулÑции:

    + +

    Definition at line 28 of file stm32f4xx_matlab_tim.c.

    + Here is the call graph for this function:
    @@ -293,28 +352,28 @@ Functions
    -

    Счет таймера за один такт

    + +

    СимулÑÑ†Ð¸Ñ Ñчетчика таймера на один такт ÑимулÑции.

    +
    Parameters
    + + + +
    TIMx– таймер, каналы которого надо запиÑать.
    TIMS– Ñтруктура таймера Ð´Ð»Ñ ÑимулÑции.
    +
    +
    +

    Ð”Ð°Ð½Ð½Ð°Ñ Ñ„ÑƒÐ½ÐºÑ†Ð¸Ñ Ð¿Ñ€Ð¾Ð²ÐµÑ€Ñет направление таймера и увеличивает или уменьшает значение Ñчетчика на то чиÑло, на которое оно бы увеличилоÑÑŒ за шаг ÑимулÑции.

    Note
    Ð”Ð»Ñ Ñчетчика иÑпользуетÑÑ double формат, Ñ‚.к. кол-во Ñчетов за шаг ÑимулÑции может быть дробным. ПоÑле в конце функции double Ñчетчик запиÑывает Ñ Ð¾ÐºÑ€ÑƒÐ³Ð»ÐµÐ½Ð¸ÐµÐ¼ в региÑÑ‚Ñ€ таймера CNT.
    + +

    Definition at line 63 of file stm32f4xx_matlab_tim.c.

    @@ -376,7 +446,7 @@ Functions void Overflow_Check ( - TIM_TypeDef * TIMx, + TIM_TypeDef * TIMx, @@ -385,7 +455,20 @@ Functions
    -

    Проверка на переполнение и Ð´Ð°Ð»ÑŒÐ½ÐµÐ¹ÑˆÐ°Ñ ÐµÐ³Ð¾ обработка

    + +

    Проверка на переполнение и Ð´Ð°Ð»ÑŒÐ½ÐµÐ¹ÑˆÐ°Ñ ÐµÐ³Ð¾ обработка.

    +
    Parameters
    + + + +
    TIMx– таймер, каналы которого надо запиÑать.
    TIMS– Ñтруктура таймера Ð´Ð»Ñ ÑимулÑции.
    +
    +
    +

    Ð”Ð°Ð½Ð½Ð°Ñ Ñ„ÑƒÐ½ÐºÑ†Ð¸Ñ Ð¿Ñ€Ð¾Ð²ÐµÑ€Ñет когда таймер переполнитьÑÑ Ð¸ еÑли надо, вызывает ÑоответÑтвующее прерывание:

    + +

    Definition at line 80 of file stm32f4xx_matlab_tim.c.

    + Here is the call graph for this function:
    @@ -393,8 +476,8 @@ Functions
    -

    Вызов прерываниÑ

    + +

    Вызов Ð¿Ñ€ÐµÑ€Ñ‹Ð²Ð°Ð½Ð¸Ñ Ñ‚Ð°Ð¹Ð¼ÐµÑ€Ð° TIMx.

    +
    Parameters
    + + +
    TIMx– таймер, прерываний которого надо вызвать.
    +
    +
    +

    Ð”Ð°Ð½Ð½Ð°Ñ Ñ„ÑƒÐ½ÐºÑ†Ð¸Ñ Ñимулирует аппаратный вызов Ð¿Ñ€ÐµÑ€Ñ‹Ð²Ð°Ð½Ð¸Ñ Ñ‚Ð°Ð¹Ð¼ÐµÑ€Ð° по какому-либо Ñобытию.

    + +

    Definition at line 665 of file stm32f4xx_matlab_tim.c.

    + Here is the call graph for this function:
    @@ -447,7 +540,7 @@ Functions
    -

    СимулÑÑ†Ð¸Ñ ÐºÐ°Ð½Ð°Ð»Ð¾Ð² таймера

    + +

    СимулÑÑ†Ð¸Ñ ÐºÐ°Ð½Ð°Ð»Ð¾Ð² таймера.

    +
    Parameters
    + + + +
    TIMx– таймер, каналы которого надо запиÑать.
    TIMS– Ñтруктура таймера Ð´Ð»Ñ ÑимулÑции.
    +
    +
    +

    Ð”Ð°Ð½Ð½Ð°Ñ Ñ„ÑƒÐ½ÐºÑ†Ð¸Ñ Ñимулирует работу вÑех каналов таймера. Она вызывает функции:

    + +

    Definition at line 118 of file stm32f4xx_matlab_tim.c.

    + Here is the call graph for this function:
    @@ -503,18 +614,18 @@ Functions @@ -530,7 +641,7 @@ Functions void CC_PWM_Ch1_Simulation ( - TIM_TypeDef * TIMx, + TIM_TypeDef * TIMx, @@ -539,7 +650,18 @@ Functions
    -

    Выбор режима CaptureCompare или PWM и ÑимулÑÑ†Ð¸Ñ Ð´Ð»Ñ Ð¿ÐµÑ€Ð²Ð¾Ð³Ð¾ канала

    + +

    Выбор режима первого канала и его ÑимулÑциÑ.

    +
    Parameters
    + + + +
    TIMx– таймер, каналы которого надо запиÑать.
    TIMS– Ñтруктура таймера Ð´Ð»Ñ ÑимулÑции.
    +
    +
    +

    Ð”Ð°Ð½Ð½Ð°Ñ Ñ„ÑƒÐ½ÐºÑ†Ð¸Ñ Ð¿Ð¾ региÑтрам таймера проверÑет как наÑтроен первый канал и ÑоответÑтвующе Ñимулирует его работу.

    + +

    Definition at line 137 of file stm32f4xx_matlab_tim.c.

    @@ -552,7 +674,7 @@ Functions void CC_PWM_Ch2_Simulation ( - TIM_TypeDef * TIMx, + TIM_TypeDef * TIMx, @@ -561,7 +683,18 @@ Functions
    -

    Выбор режима CaptureCompare или PWM и ÑимулÑÑ†Ð¸Ñ Ð´Ð»Ñ Ð²Ñ‚Ð¾Ñ€Ð¾Ð³Ð¾ канала

    + +

    Выбор режима второго канала и его ÑимулÑциÑ.

    +
    Parameters
    + + + +
    TIMx– таймер, каналы которого надо запиÑать.
    TIMS– Ñтруктура таймера Ð´Ð»Ñ ÑимулÑции.
    +
    +
    +

    Ð”Ð°Ð½Ð½Ð°Ñ Ñ„ÑƒÐ½ÐºÑ†Ð¸Ñ Ð¿Ð¾ региÑтрам таймера проверÑет как наÑтроен второй канал и ÑоответÑтвующе Ñимулирует его работу.

    + +

    Definition at line 185 of file stm32f4xx_matlab_tim.c.

    @@ -574,7 +707,7 @@ Functions void CC_PWM_Ch3_Simulation ( - TIM_TypeDef * TIMx, + TIM_TypeDef * TIMx, @@ -583,7 +716,18 @@ Functions
    -

    Выбор режима CaptureCompare или PWM и ÑимулÑÑ†Ð¸Ñ Ð´Ð»Ñ Ñ‚Ñ€ÐµÑ‚ÑŒÐµÐ³Ð¾ канала

    + +

    Выбор режима третьего канала и его ÑимулÑциÑ.

    +
    Parameters
    + + + +
    TIMx– таймер, каналы которого надо запиÑать.
    TIMS– Ñтруктура таймера Ð´Ð»Ñ ÑимулÑции.
    +
    +
    +

    Ð”Ð°Ð½Ð½Ð°Ñ Ñ„ÑƒÐ½ÐºÑ†Ð¸Ñ Ð¿Ð¾ региÑтрам таймера проверÑет как наÑтроен третий канал и ÑоответÑтвующе Ñимулирует его работу.

    + +

    Definition at line 233 of file stm32f4xx_matlab_tim.c.

    @@ -596,7 +740,7 @@ Functions void CC_PWM_Ch4_Simulation ( - TIM_TypeDef * TIMx, + TIM_TypeDef * TIMx, @@ -605,7 +749,18 @@ Functions
    -

    Выбор режима CaptureCompare или PWM и ÑимулÑÑ†Ð¸Ñ Ð´Ð»Ñ Ñ‡ÐµÑ‚Ð²ÐµÑ€Ñ‚Ð¾Ð³Ð¾ канала

    + +

    Выбор режима четвертого канала и его ÑимулÑциÑ.

    +
    Parameters
    + + + +
    TIMx– таймер, каналы которого надо запиÑать.
    TIMS– Ñтруктура таймера Ð´Ð»Ñ ÑимулÑции.
    +
    +
    +

    Ð”Ð°Ð½Ð½Ð°Ñ Ñ„ÑƒÐ½ÐºÑ†Ð¸Ñ Ð¿Ð¾ региÑтрам таймера проверÑет как наÑтроен четвертый канал и ÑоответÑтвующе Ñимулирует его работу.

    + +

    Definition at line 281 of file stm32f4xx_matlab_tim.c.

    @@ -618,7 +773,7 @@ Functions void Write_OC_to_GPIO ( - TIM_TypeDef * TIMx, + TIM_TypeDef * TIMx, @@ -627,7 +782,18 @@ Functions
    -

    ЗапиÑÑŒ каналов таймера в порты GPIO

    + +

    ЗапиÑÑŒ каналов таймера в порты GPIO.

    +
    Parameters
    + + + +
    TIMx– таймер, каналы которого надо запиÑать.
    TIMS– Ñтруктура того же таймера Ð´Ð»Ñ ÑимулÑции.
    +
    +
    +

    Ð”Ð°Ð½Ð½Ð°Ñ Ñ„ÑƒÐ½ÐºÑ†Ð¸Ñ Ð·Ð°Ð¿Ð¸Ñывает каналы OC в порты GPIO, определенные в TIMS. ЗапиÑÑŒ проиÑходит только еÑли пин наÑтроен на альтернативную функцию.

    + +

    Definition at line 330 of file stm32f4xx_matlab_tim.c.

    @@ -640,7 +806,7 @@ Functions void Write_OC_to_TRGO ( - TIM_TypeDef * TIMx, + TIM_TypeDef * TIMx, @@ -649,12 +815,23 @@ Functions
    -

    ЗапиÑÑŒ результата compare в глабальную Ñтруктуру Ñ TRIGGER OUTPUT

    + +

    ЗапиÑÑŒ каналов таймера в глабальную Ñтруктуру Ñ TRIGGER OUTPUT.

    +

    ЗапиÑÑŒ результата compare в глабальную Ñтруктуру Ñ TRIGGER OUTPUT

    Parameters
    + + + +
    TIMx– таймер, каналы которого надо запиÑать.
    TIMS– Ñтруктура того же таймера Ð´Ð»Ñ ÑимулÑции.
    +
    +
    +

    Ð”Ð°Ð½Ð½Ð°Ñ Ñ„ÑƒÐ½ÐºÑ†Ð¸Ñ Ñчитывает каналы OC и запиÑывает их в внешний канал триггера TRGO.

    + +

    Definition at line 410 of file stm32f4xx_matlab_tim.c.

    - -

    ◆ Slave_Mode_Check_Source()

    + +

    ◆ Slave_Mode_Check_Source()

    @@ -662,16 +839,23 @@ Functions void Slave_Mode_Check_Source ( - TIM_TypeDef * TIMx, - - - + TIM_TypeDef * TIMx) - struct TIM_Sim * TIMS )
    -

    Определение иÑточника Ð´Ð»Ñ Ð·Ð°Ð¿ÑƒÑка таймера в SLAVE MODE

    + +

    Определение иÑточника Ð´Ð»Ñ Ð·Ð°Ð¿ÑƒÑка таймера в SLAVE MODE.

    +

    Определение иÑточника Ð´Ð»Ñ Ð·Ð°Ð¿ÑƒÑка таймера в SLAVE MODE

    Parameters
    + + + +
    TIMx– таймер, который надо включить.
    TIMx– таймер, прерываний которого надо вызвать.
    +
    +
    +

    Ð”Ð°Ð½Ð½Ð°Ñ Ñ„ÑƒÐ½ÐºÑ†Ð¸Ñ Ð¿Ñ€Ð¾Ð²ÐµÑ€Ñет какой триггер выбран Ð´Ð»Ñ Ð·Ð°Ð¿ÑƒÑка таймера, поÑле запиÑывает значение канала триггера в бит Ð²ÐºÐ»ÑŽÑ‡ÐµÐ½Ð¸Ñ Ñ‚Ð°Ð¹Ð¼ÐµÑ€Ð°. Таким образом, при лог.1 в канале триггера - таймер включитьÑÑ.

    + +

    Definition at line 464 of file stm32f4xx_matlab_tim.c.

    @@ -689,7 +873,12 @@ Functions
    -

    Симулирование выбранных через дефайн таймеров

    + +

    СимулÑÑ†Ð¸Ñ Ð²Ñ‹Ð±Ñ€Ð°Ð½Ð½Ñ‹Ñ… таймеров.

    +

    Симулирование выбранных через дефайн таймеров

    +

    Таймеры Ð´Ð»Ñ ÑимулÑции выбираютÑÑ Ñ‡ÐµÑ€ÐµÐ· дефайны в stm32f4xx_matlab_conf.h. Ð¤ÑƒÐ½ÐºÑ†Ð¸Ñ Ð²Ñ‹Ð·Ñ‹Ð²Ð°ÐµÑ‚ÑÑ Ð½Ð° каждом шаге ÑимулÑции.

    + +

    Definition at line 521 of file stm32f4xx_matlab_tim.c.

    + Here is the call graph for this function:
    @@ -697,30 +886,30 @@ Functions
    +

    Деинициализирование выбранных таймеров.

    +

    Таймеры Ð´Ð»Ñ Ð´ÐµÐ¸Ð½Ð¸Ñ†Ð¸Ð°Ð»Ð¸Ð·Ð¸Ð·Ð°Ñ†Ð¸Ð¸ выбираютÑÑ Ñ‡ÐµÑ€ÐµÐ· дефайны в stm32f4xx_matlab_conf.h. Ð¤ÑƒÐ½ÐºÑ†Ð¸Ñ Ð²Ñ‹Ð·Ñ‹Ð²Ð°ÐµÑ‚ÑÑ Ð² конце ÑимулÑции.

    + +

    Definition at line 571 of file stm32f4xx_matlab_tim.c.

    +
    diff --git a/DOCS/html/group___t_i_m___s_i_m_u_l_a_t_o_r.map b/DOCS/html/group___t_i_m___s_i_m_u_l_a_t_o_r.map index f7dbe07..5ce2322 100644 --- a/DOCS/html/group___t_i_m___s_i_m_u_l_a_t_o_r.map +++ b/DOCS/html/group___t_i_m___s_i_m_u_l_a_t_o_r.map @@ -1,4 +1,4 @@ - - - + + + diff --git a/DOCS/html/group___t_i_m___s_i_m_u_l_a_t_o_r.md5 b/DOCS/html/group___t_i_m___s_i_m_u_l_a_t_o_r.md5 index 49bad7c..5fceb58 100644 --- a/DOCS/html/group___t_i_m___s_i_m_u_l_a_t_o_r.md5 +++ b/DOCS/html/group___t_i_m___s_i_m_u_l_a_t_o_r.md5 @@ -1 +1 @@ -b59b0503a97da37e79f4901e62ecf9ca \ No newline at end of file +40aa5535ab7ef067e0acb0f593a710cf \ No newline at end of file diff --git a/DOCS/html/group___t_i_m___s_i_m_u_l_a_t_o_r.png b/DOCS/html/group___t_i_m___s_i_m_u_l_a_t_o_r.png index c895150ee59146f422d0aabda29ba2dd264cbdef..e14bd5ed0c7e9279a5c006c138993a20bdc6c668 100644 GIT binary patch delta 1127 zcmV-t1ep7U3F`X~7JB~)T!L1mx}Z3SvUMS0@C0Ewl41RK_q z39%GqEa?)pTc!X)N>GqeWdQV;!LjPt=kt%p_W2>7mlWyo*}nS@&wYJ&wx58A zh=_=Yh=_=coyiw$Y;3$?jJfV3e;65F9LK+GZEgMPJB~J{)9G#BF-W-}2o9nsdXz1D zF@KOT=DIQF;c#JzXLo=fd8 z2#Mpkbf4{*^mAGLW%XsxbM0#ycb&M}=%dboy#{;&d;UY(jIfOM3S<>M+}HbqN68)FLPwzyr}`F*xJ%j$8p=W3^ccY$w6rb<5n_kmYP z-o3j}$tH@T!f0lZ(LsKsmH!-uVWHgCzH2+b&sJwyJ+Ah;crv|{e-TbTQ4EnFx@fOW z+_tr(y6aF?^<}qhQ^cm*4ZTJ3-phU9P2g{yPn(u*BpXtuFk$lwoyTwFMqb9xjImtj#j4wHjO*KZ_(u1WpZv)*Urw)JHP|r?cA+6sA_V&Ibx#M&XxW@U>O_dNRzNI&S)z#IddCPr~k;)>*_JVG&cd2}-8_yWx zwoQvXcuF$Lc|bC?x(9p-Tmk;Uy>9a(@O$3@+N`Xs_-MA4e=*#iwoQwC8|5uc*L13? zLyjSdwB>W8lko)j8n_C)4}1&!1;ixD=R#^aof?}lBpc{y(KuV)HCtQxMcld%|MeMn zS>3MVs_xPayf{Axem?vA3iy!Z*7(OfAMuRxf;9%VyIW~_Uv;~VtGe6PW|6y%LXVhE zr?-tU50^EQe@lH~7!t?vo!M;GWG&=X;3mlffFF>o`FNR9ZEkMH`T?$SI{N{x?b&R0 z?ic@bg_5S80pF91cwPto^c#*W6Fpxci#YNffGih{a71J`VZH{uhY|0Yk48z1VL~xpU<~Z3$NL_|bHL_}n4{sTlE6!_X`??C_n002ovPDHLkV1nTADEj~a delta 1153 zcmV-{1b+ML2!#nDiBL{Q4GJ0x0000DNk~Le0003-0000b2nGNE06xG#u#q7Ze>zD- zK~#90?cKd=+-3mB@vqbuI+PZBC@mDqc{PD-hR|*u`UXvgCbYCA2|kPL9XgcGojdh7 zZzV&@jrk8!5shf`f+yP94tIoS)O%BR$e1$-fWWVCgwMj~-6H)1yZx zgNTTTh=_=Yh=@pefw^FNd;9Gme+aJlXpD4I9LEoLcX$8r-HtMb!{K$`Z4kf0FgzTM zMvs=4y=WE+g5XLJ1oxV2mh`|4;1}PGC_|rhnaySs;IrjrE5W!h8jWgikaS-ZMZTL* z*TXVe+&vn5fMY` z?K(DsARvxo>-9yK+rB@m9j2^$Z1$__z7%<18gqMQ*}U~>8EEfRBJLfscWg&z5&$Zse+ zqR!>Ii}qd8x};@g`ocyhK9IowK_ThVg3WW^g}}SOkHBBR1o(vKp(p~R2iqcKo8&AQ zlMcQH&Oj>5YhPFQs|7ZJAArAs2f!WRb>_d%f5~IJ8kclnyE?ncf7?c#b@!RGp|lNi zh*&geY|5s+clqx&D%&?LvB~^5r#FFjfTuh^GxYLV>kBjB+8S);@VToY?DWIBd?2^+ zfKHmsunpuk?pGOk6Hzwy_Vz9V-vO75RYix(hovfZU^<;L7z}E!XE`LwhDFk3Mv?8f zsJm_QCZeip{9Al+e?XQUp1KOByxC+Qs`ibIGBf3Awzjq&@9*#b%zTFVYgW$|^V|Xc zDcyhyHa0do`Bb31*<>FUVb#RYz3fC-QC@~OP0#W!w%?Wj%;KYO9DUjR4t#(1+62A= zZUJuq&&a;6cpvccJjb=QH6PVlYf}JbX?g~HQK#$vaXu@Ze|3;$9eg%3r#@y`^TMO* zB#n!{Nh{~!OW`-*Ti`9=J>VzcUm#{4k{6QCp=@5=RVQg|w{26-N1t`}g1Busrj>UY z7)2*|>J0Uy{cQ3Qg<%H#diMGT_yG6n*M-w|@h^%Z;yAuB9*=FV)x8RQ%KS#}_kjVPhSEDbJFy;AdvTpT zsCF_QkIy~9yE8XZX2855=;Gh6O0N! z=`w|1yJ#paB4SW5iij8#j3Oci1*3?FA$9Ua7lY-ZS2#L4O8lqm(toF?r-{o~f-wxk z!`W;$nNFv*H%j^;3`1{E$Ehlg6iZiIaPQk TfTaXr00000NkvXXu0mjfguf`d diff --git a/DOCS/html/group___t_i_m___s_i_m_u_l_a_t_o_r_ga05b798408f2179ae27731f231cf4b620_cgraph.map b/DOCS/html/group___t_i_m___s_i_m_u_l_a_t_o_r_ga05b798408f2179ae27731f231cf4b620_cgraph.map index a8f6bbd..60f2061 100644 --- a/DOCS/html/group___t_i_m___s_i_m_u_l_a_t_o_r_ga05b798408f2179ae27731f231cf4b620_cgraph.map +++ b/DOCS/html/group___t_i_m___s_i_m_u_l_a_t_o_r_ga05b798408f2179ae27731f231cf4b620_cgraph.map @@ -1,6 +1,6 @@ - - + + diff --git a/DOCS/html/group___t_i_m___s_i_m_u_l_a_t_o_r_ga05b798408f2179ae27731f231cf4b620_cgraph.md5 b/DOCS/html/group___t_i_m___s_i_m_u_l_a_t_o_r_ga05b798408f2179ae27731f231cf4b620_cgraph.md5 index c889355..717b1cd 100644 --- a/DOCS/html/group___t_i_m___s_i_m_u_l_a_t_o_r_ga05b798408f2179ae27731f231cf4b620_cgraph.md5 +++ b/DOCS/html/group___t_i_m___s_i_m_u_l_a_t_o_r_ga05b798408f2179ae27731f231cf4b620_cgraph.md5 @@ -1 +1 @@ -8825d0c8e85cdf41156bfaf4cb3f351d \ No newline at end of file +66f2c6ca0e4a404b0ee8ce4744b40efc \ No newline at end of file diff --git a/DOCS/html/group___t_i_m___s_i_m_u_l_a_t_o_r_ga3128cf64eeea541a8e25a72ce10da335_cgraph.map b/DOCS/html/group___t_i_m___s_i_m_u_l_a_t_o_r_ga3128cf64eeea541a8e25a72ce10da335_cgraph.map index 9d5afb0..6aed019 100644 --- a/DOCS/html/group___t_i_m___s_i_m_u_l_a_t_o_r_ga3128cf64eeea541a8e25a72ce10da335_cgraph.map +++ b/DOCS/html/group___t_i_m___s_i_m_u_l_a_t_o_r_ga3128cf64eeea541a8e25a72ce10da335_cgraph.map @@ -1,28 +1,28 @@ - - + + - + - + - + - + - + - + - + - + - + - + - + diff --git a/DOCS/html/group___t_i_m___s_i_m_u_l_a_t_o_r_ga3128cf64eeea541a8e25a72ce10da335_cgraph.md5 b/DOCS/html/group___t_i_m___s_i_m_u_l_a_t_o_r_ga3128cf64eeea541a8e25a72ce10da335_cgraph.md5 index ddb822b..0a28a9d 100644 --- a/DOCS/html/group___t_i_m___s_i_m_u_l_a_t_o_r_ga3128cf64eeea541a8e25a72ce10da335_cgraph.md5 +++ b/DOCS/html/group___t_i_m___s_i_m_u_l_a_t_o_r_ga3128cf64eeea541a8e25a72ce10da335_cgraph.md5 @@ -1 +1 @@ -5c2cf8f65c4e43946fd46eabc3c191b5 \ No newline at end of file +36492425220524bc6d06f1dbb8bae86e \ No newline at end of file diff --git a/DOCS/html/group___t_i_m___s_i_m_u_l_a_t_o_r_ga3fcb4dd48557c21fdd6c379ad16bd229_cgraph.map b/DOCS/html/group___t_i_m___s_i_m_u_l_a_t_o_r_ga3fcb4dd48557c21fdd6c379ad16bd229_cgraph.map index 9cf0722..7aabd42 100644 --- a/DOCS/html/group___t_i_m___s_i_m_u_l_a_t_o_r_ga3fcb4dd48557c21fdd6c379ad16bd229_cgraph.map +++ b/DOCS/html/group___t_i_m___s_i_m_u_l_a_t_o_r_ga3fcb4dd48557c21fdd6c379ad16bd229_cgraph.map @@ -1,26 +1,26 @@ - - + + - + - + - + - + - + - + - + - + - + - + diff --git a/DOCS/html/group___t_i_m___s_i_m_u_l_a_t_o_r_ga3fcb4dd48557c21fdd6c379ad16bd229_cgraph.md5 b/DOCS/html/group___t_i_m___s_i_m_u_l_a_t_o_r_ga3fcb4dd48557c21fdd6c379ad16bd229_cgraph.md5 index 9f63f1a..016858d 100644 --- a/DOCS/html/group___t_i_m___s_i_m_u_l_a_t_o_r_ga3fcb4dd48557c21fdd6c379ad16bd229_cgraph.md5 +++ b/DOCS/html/group___t_i_m___s_i_m_u_l_a_t_o_r_ga3fcb4dd48557c21fdd6c379ad16bd229_cgraph.md5 @@ -1 +1 @@ -72ffafa7fd5e2e3b6b81478dcca7d5bc \ No newline at end of file +4b6fa7c04a5d57daf51e4ca637c9ccba \ No newline at end of file diff --git a/DOCS/html/group___t_i_m___s_i_m_u_l_a_t_o_r_ga63dc3b53fe4b165b4c70e4d600258d50_cgraph.map b/DOCS/html/group___t_i_m___s_i_m_u_l_a_t_o_r_ga63dc3b53fe4b165b4c70e4d600258d50_cgraph.map index fb81bad..d0c73bc 100644 --- a/DOCS/html/group___t_i_m___s_i_m_u_l_a_t_o_r_ga63dc3b53fe4b165b4c70e4d600258d50_cgraph.map +++ b/DOCS/html/group___t_i_m___s_i_m_u_l_a_t_o_r_ga63dc3b53fe4b165b4c70e4d600258d50_cgraph.map @@ -1,15 +1,15 @@ - - + + - + - + - + - + - + diff --git a/DOCS/html/group___t_i_m___s_i_m_u_l_a_t_o_r_ga63dc3b53fe4b165b4c70e4d600258d50_cgraph.md5 b/DOCS/html/group___t_i_m___s_i_m_u_l_a_t_o_r_ga63dc3b53fe4b165b4c70e4d600258d50_cgraph.md5 index e9095d1..5892647 100644 --- a/DOCS/html/group___t_i_m___s_i_m_u_l_a_t_o_r_ga63dc3b53fe4b165b4c70e4d600258d50_cgraph.md5 +++ b/DOCS/html/group___t_i_m___s_i_m_u_l_a_t_o_r_ga63dc3b53fe4b165b4c70e4d600258d50_cgraph.md5 @@ -1 +1 @@ -8fdbd483a52da057b0d8703454ea2ecc \ No newline at end of file +87fa8ec8b403d666d12f7eacdeb02ed5 \ No newline at end of file diff --git a/DOCS/html/group___t_i_m___s_i_m_u_l_a_t_o_r_gaa2b3ab4507a894ffa6e4487d42054e67_cgraph.map b/DOCS/html/group___t_i_m___s_i_m_u_l_a_t_o_r_gaa2b3ab4507a894ffa6e4487d42054e67_cgraph.map index 7fd13f2..57b6b3a 100644 --- a/DOCS/html/group___t_i_m___s_i_m_u_l_a_t_o_r_gaa2b3ab4507a894ffa6e4487d42054e67_cgraph.map +++ b/DOCS/html/group___t_i_m___s_i_m_u_l_a_t_o_r_gaa2b3ab4507a894ffa6e4487d42054e67_cgraph.map @@ -1,5 +1,5 @@ - + diff --git a/DOCS/html/group___t_i_m___s_i_m_u_l_a_t_o_r_gaa2b3ab4507a894ffa6e4487d42054e67_cgraph.md5 b/DOCS/html/group___t_i_m___s_i_m_u_l_a_t_o_r_gaa2b3ab4507a894ffa6e4487d42054e67_cgraph.md5 index 2454122..55b89f0 100644 --- a/DOCS/html/group___t_i_m___s_i_m_u_l_a_t_o_r_gaa2b3ab4507a894ffa6e4487d42054e67_cgraph.md5 +++ b/DOCS/html/group___t_i_m___s_i_m_u_l_a_t_o_r_gaa2b3ab4507a894ffa6e4487d42054e67_cgraph.md5 @@ -1 +1 @@ -62cd3e08b1b1b2fcd4c081a53cb6ff93 \ No newline at end of file +0ec75ee8bb106742eab655c2a346476b \ No newline at end of file diff --git a/DOCS/html/group___w_r_a_p_p_e_r___c_o_n_f.html b/DOCS/html/group___w_r_a_p_p_e_r___c_o_n_f.html index 53e2704..7a1228f 100644 --- a/DOCS/html/group___w_r_a_p_p_e_r___c_o_n_f.html +++ b/DOCS/html/group___w_r_a_p_p_e_r___c_o_n_f.html @@ -5,7 +5,7 @@ -STM MATLAB Simulator: WRAPPER_CONF +STM MATLAB Simulator: Wrapper Configuration @@ -14,6 +14,7 @@ + @@ -72,22 +73,23 @@ $(function() {
    -Macros
    -
    WRAPPER_CONF
    MCU_WRAPPER
    +Macros | +Variables
    +
    Wrapper Configuration
    MCU Wrapper
    -

    Configurations for wrapper to simulating MCU. +

    Параметры конфигурации Ð´Ð»Ñ Ð¾Ð±Ð¾Ð»Ð¾Ñ‡ÐºÐ¸ МК More...

    - + Collaboration diagram for WRAPPER_CONF:
    + + Collaboration diagram for Wrapper Configuration:
    @@ -123,10 +125,25 @@ Macros +
    #define DISC_STATES_WIDTH   PORT_WIDTH*PORT_NUMB
     width of discrete states array
     
    + + + + + + + + + + + + +

    +Variables

    SIM__MCUHandleTypeDef hmcu
     Ð¥ÐµÐ½Ð´Ð» Ð´Ð»Ñ ÑƒÐ¿Ñ€Ð°Ð²Ð»ÐµÐ½Ð¸Ñ Ð¿Ð¾Ñ‚Ð¾ÐºÐ¾Ð¼ программы МК
     
    double SystemClockDouble = 0
     Ð¡Ñ‡ÐµÑ‚чик в формате double Ð´Ð»Ñ Ñ‚Ð¾Ñ‡Ð½Ð¾Ð¹ ÑимулÑции ÑиÑтемных тиков С промежуточными значений
     
    uint64_t SystemClock
     Ð¡Ñ‡ÐµÑ‚чик тактов Ð´Ð»Ñ ÑимулÑции ÑиÑтемных тиков (в целочиÑленном формате)
     
    double SystemClock_step = 0
     Ð¨Ð°Ð³ тиков Ð´Ð»Ñ Ð¸Ñ… ÑимулÑции, в формате double.
     

    Detailed Description

    -

    Configurations for wrapper to simulating MCU.

    -

    ЗдеÑÑŒ дефайнами задаетÑÑ Ð¿Ð°Ñ€Ð°Ð¼ÐµÑ‚Ñ€Ñ‹ оболочки, ÐºÐ¾Ñ‚Ð¾Ñ€Ð°Ñ ÑƒÐ¿Ñ€Ð°Ð²Ð»Ñет кодом МК

    +

    Параметры конфигурации Ð´Ð»Ñ Ð¾Ð±Ð¾Ð»Ð¾Ñ‡ÐºÐ¸ МК

    +

    ЗдеÑÑŒ дефайнами задаетÑÑ Ð¿Ð°Ñ€Ð°Ð¼ÐµÑ‚Ñ€Ñ‹ оболочки, которые определÑÑŽÑ‚ как она будет работать

    Macro Definition Documentation

    ◆ CREATE_SUSPENDED

    @@ -142,6 +159,8 @@ Macros

    define from WinBase.h. We dont wanna include "Windows.h" or smth like this, because of HAL there are a lot of redefine errors.

    +

    Definition at line 47 of file mcu_wrapper_conf.h.

    + @@ -158,6 +177,8 @@ Macros

    number of for() cycles after which MCU thread would be suspended

    +

    Definition at line 49 of file mcu_wrapper_conf.h.

    + @@ -174,6 +195,8 @@ Macros

    width of one port

    +

    Definition at line 50 of file mcu_wrapper_conf.h.

    + @@ -190,6 +213,8 @@ Macros

    amount of ports

    +

    Definition at line 51 of file mcu_wrapper_conf.h.

    + @@ -206,6 +231,8 @@ Macros

    number of input parametrs (only Ts)

    +

    Definition at line 54 of file mcu_wrapper_conf.h.

    + @@ -222,6 +249,8 @@ Macros

    width of input ports

    +

    Definition at line 55 of file mcu_wrapper_conf.h.

    + @@ -238,6 +267,8 @@ Macros

    number of input ports

    +

    Definition at line 56 of file mcu_wrapper_conf.h.

    + @@ -254,6 +285,8 @@ Macros

    width of output ports

    +

    Definition at line 57 of file mcu_wrapper_conf.h.

    + @@ -270,6 +303,8 @@ Macros

    number of output ports

    +

    Definition at line 58 of file mcu_wrapper_conf.h.

    + @@ -286,6 +321,81 @@ Macros

    width of discrete states array

    +

    Definition at line 59 of file mcu_wrapper_conf.h.

    + + + +

    Variable Documentation

    + +

    ◆ hmcu

    + +
    +
    + + + + +
    SIM__MCUHandleTypeDef hmcu
    +
    + +

    Хендл Ð´Ð»Ñ ÑƒÐ¿Ñ€Ð°Ð²Ð»ÐµÐ½Ð¸Ñ Ð¿Ð¾Ñ‚Ð¾ÐºÐ¾Ð¼ программы МК

    + +

    Definition at line 16 of file mcu_wrapper.c.

    + +
    +
    + +

    ◆ SystemClockDouble

    + +
    +
    + + + + +
    double SystemClockDouble = 0
    +
    + +

    Счетчик в формате double Ð´Ð»Ñ Ñ‚Ð¾Ñ‡Ð½Ð¾Ð¹ ÑимулÑции ÑиÑтемных тиков С промежуточными значений

    + +

    Definition at line 18 of file mcu_wrapper.c.

    + +
    +
    + +

    ◆ SystemClock

    + +
    +
    + + + + +
    uint64_t SystemClock
    +
    + +

    Счетчик тактов Ð´Ð»Ñ ÑимулÑции ÑиÑтемных тиков (в целочиÑленном формате)

    + +

    Definition at line 19 of file mcu_wrapper.c.

    + +
    +
    + +

    ◆ SystemClock_step

    + +
    +
    + + + + +
    double SystemClock_step = 0
    +
    + +

    Шаг тиков Ð´Ð»Ñ Ð¸Ñ… ÑимулÑции, в формате double.

    + +

    Definition at line 20 of file mcu_wrapper.c.

    +
    diff --git a/DOCS/html/group___w_r_a_p_p_e_r___c_o_n_f.map b/DOCS/html/group___w_r_a_p_p_e_r___c_o_n_f.map index af04b74..bd45fc3 100644 --- a/DOCS/html/group___w_r_a_p_p_e_r___c_o_n_f.map +++ b/DOCS/html/group___w_r_a_p_p_e_r___c_o_n_f.map @@ -1,4 +1,4 @@ - - - + + + diff --git a/DOCS/html/group___w_r_a_p_p_e_r___c_o_n_f.md5 b/DOCS/html/group___w_r_a_p_p_e_r___c_o_n_f.md5 index 126d2a7..8f245a1 100644 --- a/DOCS/html/group___w_r_a_p_p_e_r___c_o_n_f.md5 +++ b/DOCS/html/group___w_r_a_p_p_e_r___c_o_n_f.md5 @@ -1 +1 @@ -d6949868edaa45351aac03e324631671 \ No newline at end of file +b918bc2366f77e40eca7c15c14c9269c \ No newline at end of file diff --git a/DOCS/html/group___w_r_a_p_p_e_r___c_o_n_f.png b/DOCS/html/group___w_r_a_p_p_e_r___c_o_n_f.png index 96c58fd79305af9bf6b38a9dc6307719353b1f7e..e6959aadb53c54b9d13004014758d00714a7a23b 100644 GIT binary patch delta 1185 zcmV;S1YY}#38e`kiBL{Q4GJ0x0000DNk~Le0003w0000b2nGNE06Bu5rI8^Oe_BaI zK~#90?cFhGBvl;8@$Vb-P|Gwn;t>Q9&LV}4hnziYK5sd+yMOqOqlwXIbi;QH5~e7Mj*}$0 zn?Lth@gif)bz{t({=$-mZUSHX4x$PDeMwg)lgS?NcK+O4lFKAX(s@AAOdQ9)Ls;78 z<|Z2(8@|JkfE*niae8_>cRunEi-<^Xl;lJtXi9P-5;P?_5eb@-oQMQXe@RY6g4Rls zGiGj2ab>wN=JIfA(^sl~Qk#`XLV#c_OjbX9lu*eBoZw>FY< zNhHP?(lot1x=c1%TWgrmGLHkV178Av0bc=c%+9Z*IF3n@#QTS58Cf5)qs_kL>xTaK zycYZ7d(Um})732L=J4?F1>hd=8}KR91PApK+fP91_rT9x z1XZQ)mF}`BQ5)JGb*#$533T_KcA@pv)ofa5`%u?ipjc)hf5R3-RcuAJ1q7Gtm$}Z- zFH9F5t^zLspEKPu0`OlK4fe@)uczuBP?2o`!R7j8u7mQGR38bht;96s1P7i*a>WEz zHzD>h(#yA5mS~IRb;>;S<6w4t2)qis3%td2Gw=li8o~D=pH#{cOtHL9S+Slb_qVEE zzib;-?UvPFe>Y)Oy{ERM-9?|O%nd04!z{_}=uI}vYq(k}9OqZ3w5QWso*^g%KjmP6hei>NbU0oml0N(&_0#5@E z{Dvbw41H?Zg|(Wt$fdu12OxgF3yN$EcV7HR7I{Jix1T#}2T=y)=j>>V5&bRLv67e&#r?--g& z({%6b?96u<5}+uG?)r{FL_|bHL_|bHWZnG_nFo=^qRkT+00000NkvXXu0mjfdaF{^ delta 1159 zcmV;21bF+U35y9KiBL{Q4GJ0x0000DNk~Le0003(0000b2nGNE05>b(%8?-ze?Un@ zK~#90?cK3&++-Za@vp5mf+Z3e0|>552AB|2kzhisAVI3OAeLP2-++mM1;*25VJwOS z8)5+|Lpz|1NXd`^u2P2#86pL#pfkfcs^fcYzkcoW``-EaNLD5L_3PhV>L;)L`Ys?M zA|fIpA|fIpeHP_c?CtHn7Ddrre;>t2IFclJd~k5^)OQ^&hQr~m?;0draU4&_jYcEiB{Vh| z4A|P*@?C}m=Irc@i;Ihe^|6OqL_~t3AQX|_QxJ+s?WHFa*%tuKQoF&(@Vy_w`+`uj;Ewn`}Fmx|d)B_z1WU`~dvg z<-uKyMkC{+VpZ#l9x*C=?5wQMs=k`E$+mN;yGXXLs@Gk1EZd(!o3-b)5`<7M4DxMl z!>y@o*p(g6H9$?h#ZMW&mwM~<{ zi}E z?}O=mEDL?pDADJG{H=`$O{1c!%gy}$61+E=fAnr2xC8tP+)lUMe=gWZdSaD-NwgM( zeUuG;n@jGd$1>^Q7s#u?r_3*X-(?9I^!A*5{Ho2vVbu38Pk zY#4-axmi?CRh_2LaeXZ|ec80Jogk{}$JXiT>FdC6zz5vCg|cDZW5G{O2X4X1$q9qO zz`A|*1S|@zqWfB=f4*GU^kvh==J;*a-L+-asS%-p%|y<1=;Xtvtw|0SZB9V#?CeaB zj*cEOzZCugc!!&p!d1Qn{%|g!f$i<>P9|z>CkwLw7PaqkqQItZUzR;$E)q--hA@IO zahVYgK})0ZXTW#q@&@oRFl0Va@|^O~;bY+ECI@%5x!L`ke~rtGa0uEAp3p+Ij@D<5 zt4=`E6`_FXw8hDTS1Jw6{SEzUSyjFZ&)@8X& zmblcN534$Xe{Xvmpvy2^IJ<_!;cgT~k5+YvE6t5YBa$S!H + + + + + + +STM MATLAB Simulator: S-Function funtions + + + + + + + + + + + + +
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    +
    STM MATLAB Simulator +
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    +Macros | +Functions
    +
    S-Function funtions
    MCU Wrapper
    +
    +
    + +

    Дефайны и функции блока S-Function. +More...

    +
    + + Collaboration diagram for S-Function funtions:
    +
    +
    + + + + + + + + + + + + + + +

    +Macros

    #define S_FUNCTION_NAME   MCU
     
    #define S_FUNCTION_LEVEL   2
     
    #define MDL_UPDATE
     Ð´Ð»Ñ Ð¿Ð¾Ð´ÐºÐ»ÑŽÑ‡ÐµÐ½Ð¸Ñ mdlUpdate()
     
    #define MDL_CHECK_PARAMETERS   /* Change to #undef to remove function */
     
    #define MDL_START   /* Change to #undef to remove function */
     
    + + + + + + + + + + + + + + + + + + +

    +Functions

    static void mdlUpdate (SimStruct *S)
     Update S-Function at every step of simulation.
     
    static void mdlOutputs (SimStruct *S)
     Writting outputs of S-Function.
     
    static void mdlInitializeSizes (SimStruct *S)
     
    static void mdlStart (SimStruct *S)
     Initialize S-Function at start of simulation.
     
    static void mdlInitializeSampleTimes (SimStruct *S)
     Initialize Sample Time of Simulation.
     
    static void mdlTerminate (SimStruct *S)
     Terminate S-Function at the end of simulation.
     
    +

    Detailed Description

    +

    Дефайны и функции блока S-Function.

    +

    ЗдеÑÑŒ Ñобраны функции, Ñ ÐºÐ¾Ñ‚Ð¾Ñ€Ñ‹Ð¼Ð¸ непоÑредÑтвенно работает S-Function

    Note
    ОпиÑание функций по большей чаÑти Ñгенерировано MATLAB'ом, поÑтому на английÑком
    +

    Macro Definition Documentation

    + +

    ◆ S_FUNCTION_NAME

    + +
    +
    + + + + +
    #define S_FUNCTION_NAME   MCU
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    + +

    Definition at line 22 of file MCU.c.

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    ◆ S_FUNCTION_LEVEL

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    #define S_FUNCTION_LEVEL   2
    +
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    Definition at line 23 of file MCU.c.

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    ◆ MDL_UPDATE

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    + + + + +
    #define MDL_UPDATE
    +
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    Ð´Ð»Ñ Ð¿Ð¾Ð´ÐºÐ»ÑŽÑ‡ÐµÐ½Ð¸Ñ mdlUpdate()

    + +

    Definition at line 27 of file MCU.c.

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    ◆ MDL_CHECK_PARAMETERS

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    +
    + + + + +
    #define MDL_CHECK_PARAMETERS   /* Change to #undef to remove function */
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    + +

    Definition at line 60 of file MCU.c.

    + +
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    + +

    ◆ MDL_START

    + +
    +
    + + + + +
    #define MDL_START   /* Change to #undef to remove function */
    +
    + +

    Definition at line 143 of file MCU.c.

    + +
    +
    +

    Function Documentation

    + +

    ◆ mdlUpdate()

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    + + + + + +
    + + + + + + + +
    static void mdlUpdate (SimStruct * S)
    +     		+static
    +
    + +

    Update S-Function at every step of simulation.

    +
    Parameters
    + + +
    S- pointer to S-Function (library struct from "simstruc.h")
    +
    +
    +

    Abstract: This function is called once for every major integration time step. Discrete states are typically updated here, but this function is useful for performing any tasks that should only take place once per integration step.

    + +

    Definition at line 37 of file MCU.c.

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    ◆ mdlOutputs()

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    + + + + + + + +
    static void mdlOutputs (SimStruct * S)
    +     		+static
    +
    + +

    Writting outputs of S-Function.

    +
    Parameters
    + + +
    S- pointer to S-Function (library struct from "simstruc.h")
    +
    +
    +

    Abstract: In this function, you compute the outputs of your S-function block. Generally outputs are placed in the output vector(s), ssGetOutputPortSignal.

    + +

    Definition at line 55 of file MCU.c.

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    ◆ mdlInitializeSizes()

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    static void mdlInitializeSizes (SimStruct * S)
    +     		+static
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    Definition at line 95 of file MCU.c.

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    ◆ mdlStart()

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    + + + + + + + +
    static void mdlStart (SimStruct * S)
    +     		+static
    +
    + +

    Initialize S-Function at start of simulation.

    +
    Parameters
    + + +
    S- pointer to S-Function (library struct from "simstruc.h")
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    +
    +

    Abstract: This function is called once at start of model execution. If you have states that should be initialized once, this is the place to do it.

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    Definition at line 153 of file MCU.c.

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    ◆ mdlInitializeSampleTimes()

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    static void mdlInitializeSampleTimes (SimStruct * S)
    +     		+static
    +
    + +

    Initialize Sample Time of Simulation.

    +
    Parameters
    + + +
    S- pointer to S-Function (library struct from "simstruc.h")
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    Abstract: This function is used to specify the sample time(s) for your S-function. You must register the same number of sample times as specified in ssSetNumSampleTimes.

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    Definition at line 167 of file MCU.c.

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    ◆ mdlTerminate()

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    static void mdlTerminate (SimStruct * S)
    +     		+static
    +
    + +

    Terminate S-Function at the end of simulation.

    +
    Parameters
    + + +
    S- pointer to S-Function (library struct from "simstruc.h")
    +
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    Abstract: In this function, you should perform any actions that are necessary at the termination of a simulation. For example, if memory was allocated in mdlStart, this is the place to free it.

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    Definition at line 185 of file MCU.c.

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    +Generated by doxygen 1.10.0 +
    + + diff --git a/DOCS/html/group___w_r_a_p_p_e_r___s_f_u_n_c.map b/DOCS/html/group___w_r_a_p_p_e_r___s_f_u_n_c.map new file mode 100644 index 0000000..a475ac8 --- /dev/null +++ b/DOCS/html/group___w_r_a_p_p_e_r___s_f_u_n_c.map @@ -0,0 +1,4 @@ + + + + diff --git a/DOCS/html/group___w_r_a_p_p_e_r___s_f_u_n_c.md5 b/DOCS/html/group___w_r_a_p_p_e_r___s_f_u_n_c.md5 new file mode 100644 index 0000000..59823e2 --- /dev/null +++ b/DOCS/html/group___w_r_a_p_p_e_r___s_f_u_n_c.md5 @@ -0,0 +1 @@ +2113a9dc82dde03465a3f995864719a3 \ No newline at end of file diff --git a/DOCS/html/group___w_r_a_p_p_e_r___s_f_u_n_c.png b/DOCS/html/group___w_r_a_p_p_e_r___s_f_u_n_c.png new file mode 100644 index 0000000000000000000000000000000000000000..72e8e980cd2aef6b3bb1d03f4b1cd50dc7828ecc GIT binary patch literal 1123 zcmV-p1f2VcP)RYqCjxXc1V;INEZ-7GzcUlK-`Jr zTWoNQod2Bwp4OyXG9PXYKLM*puAvBdxTt zJu{E@<=L6ZtQSN?L_|bHL_|dTWvUytwzjStV{Qx)jI@{M`S&|JJ3kE_M;GJq_~y_t zNSu-+Im)u^UU}QY)q{*NH;gfN`wL4tx&?eabP!$W^(8jb>2w!(r@U<;Nfojz3m%Yk zlcwp=A*^gP8nLmlF?1Lbk;B77PESu4wkHF`A|le7l9Y%tjAj{|Q5w}Cf+--ivSy}D%=%a+O5 zmTC04v?fi{Ang_B=CkflvHIX8Nx||&&~$9bWKq=p04AiuHD(FvJ>XUDKj({2Or&gY zpr$ug-*38VJfRYlk9zxv)faC`s;#Y-!5{gc$8R+e);brMq3-Ua!u`3<98kI)zup+)~0e@ zc}-H~;nq;YDO(K7Vzb@1)!$`b*E((X_V%6!J_DYq>{_ciyv}dVje2r&a>8gdaw=1O z@mIGsm2uU!tgpG8P;){d>h1fnQBSIdhoM*SIyW~re>gZe_zHLz_z-xCi@m5OcYr^= z2G!E~`ua*&Z>WB9cj;w`f1#d>Xp&Sc6WMh`F&_e*+mG|xr@(W}lGSbC3E&@=Kfm7q zXCZ=WvbNSXkIuyQUp%o3G2HXMn6qi9*LH$^m5F#;46ega+XT4F@v9u?Xdn0lcoKLK z_yYI?$br8@G$>c&vN^tldMpO%NmUb2+l1CfPpjN!U81b+Z?muG^Y|C|Zhre1cpZ2j zc#YYA_zaiqn+DZkM0vaKI$g_EV`!T6ww3Fu>v@3xSVNuT!bkdeJicj+xvMVpqAsi5 zLrBwf-8YvN3PDx5cqNXGzB2iP45|OAWNr_0* z^y8p1h~wkq+8=_H2iN&|{i>LSB$Xt|(R4c9-QV929+Y&KB+1dxF?5yZ`R>`-AnQma pa!Hch8#)FN5fKp)5fKrQ{{S8ZK!{z?4qyNP002ovPDHLkV1fb#AU^;A literal 0 HcmV?d00001 diff --git a/DOCS/html/group___w_r_a_p_p_e_r___s_f_u_n_c_ga0dd07daf338cf84d1aee4bb8b6771720_cgraph.map b/DOCS/html/group___w_r_a_p_p_e_r___s_f_u_n_c_ga0dd07daf338cf84d1aee4bb8b6771720_cgraph.map new file mode 100644 index 0000000..c794c34 --- /dev/null +++ b/DOCS/html/group___w_r_a_p_p_e_r___s_f_u_n_c_ga0dd07daf338cf84d1aee4bb8b6771720_cgraph.map @@ -0,0 +1,13 @@ + + + + + + + + + + + + + diff --git a/DOCS/html/group___w_r_a_p_p_e_r___s_f_u_n_c_ga0dd07daf338cf84d1aee4bb8b6771720_cgraph.md5 b/DOCS/html/group___w_r_a_p_p_e_r___s_f_u_n_c_ga0dd07daf338cf84d1aee4bb8b6771720_cgraph.md5 new file mode 100644 index 0000000..7e197d9 --- /dev/null +++ b/DOCS/html/group___w_r_a_p_p_e_r___s_f_u_n_c_ga0dd07daf338cf84d1aee4bb8b6771720_cgraph.md5 @@ -0,0 +1 @@ +7b152ae28b1a41aac6a3ab50d2289389 \ No newline at end of file diff --git a/DOCS/html/group___w_r_a_p_p_e_r___s_f_u_n_c_ga0dd07daf338cf84d1aee4bb8b6771720_cgraph.png b/DOCS/html/group___w_r_a_p_p_e_r___s_f_u_n_c_ga0dd07daf338cf84d1aee4bb8b6771720_cgraph.png new file mode 100644 index 0000000000000000000000000000000000000000..dba53d9893bb71ab307b19a597161ef2f8557954 GIT binary patch literal 4454 zcmZXY2{csi|HntZsjNwoY$YZ88e^@P(V&Lx``&2mOh$H+t+9j{yOgnH%T9Je$k;-I zv5$QjAtQs|%=iEQpZ_`k|L2}_pL@=|&pprcdEWPVy+1cv7y6iq{suh&0ASLDfb;-> zbAgm=lZ$keb4ctXTS`M`r~McNIHMjPnhTNu09Gzd&?AFanOk`07>fhnp4}Y;%*T~J z^;^54%R?Mqw)At}=eBJIh+fyi0z+;!{Vzj|(f36>I9EV;=S7Id0ICTdJqeL*bmpR^ z>5-e5Y_AHj*AwslwsE=0)$aUGS;(9m-J&zkl+wx?!wzr}*N~kh;|Tk6m|!HMv_c-- z%k2NFe42BXNz4ELV}wz3?H>?mvc0XXt;Y7cRq{*Tk*^Vvk#z!D>Q|j7%9=-hlxZun zG`wqUZE?eYJ^cM(10u}Hnt;3#F|PtcnveKGw4HlD4*n>UsT$B+xiwmnKbNXEEXc1X zIAMWcqNSzPEVv~G+nH%*WML7^>W*PzX1<&C`iaoNj_%N$GKdlaG{S$WEsTaekUGGs zkhiL=tgH#955YN6QBmJTKYY}o+;+G&BxVi*U9o}HAIGeeA{CDI#;z#QS1lZ##NUwV zQ`Crlb}!h})4fXIzn{CZnD8wTfE9v^<>#8VsiE?a`ko zug&XCR#E^du*!aXC3NlfdbG%PfHood%(wAc0N@eFqwxls`di-Vx%&*K%BC&Bo4~2M zvPyl;6%Gt3&g=_X>Dp(*f!(Xdn_33@(NR$lXk_HH3z6Wvm-@spfUEmNbrKUwy1!b81>*#;p*XB!qGM2tU{D^w;Exg} zT%JHW$%b9k0KBBByYhPnryh`sC4F+14x-)mw(c$L32tuiA0{2Fu9a5D0PR-_3nY$KpYcsp^nAzllKq4wq=&v28dZ4$zVU3#?6u!DtQ-mixslhIUBjD ztLrMTjw$zJ;V-YPE8)B|V(+so04%=2RubaLDQQ8Nb_|6gf(YH+0J+`q<-w7><4R6h zeU>j2JtW9I+thP>k33pX*1QvV?gu;~sUqCbw6&x5F6%Lt^$cHSmA{I(8_Fyb7lDP% zRUGvDGRa(6-PkyG3Da}EG~l6}{E@oeOkD?EsCp>ObGGiO6LLJaGgJQ>vAQ!wr1978 z07fqDrCsd1B~m-kzIc_56)uH=UOb}xjtXS^^0V@{HNq7o_91ni(5&|jUhc`*+IAZvA7=2604rz_a@K03hyIJgNEGtT}zKfbrt1X}nr|18eJ>k^9B3Lcq=1utMIQ(VeSYRjRWh}2j~V^+@E z_3^NhT4X}ZRG)9c6kIVlv>1hrI33ANjvFHBUNpRxC_0(!>q(+!7}4#4wOQE#!`ccY z%K)d+vWh^EoXUbdZzaQG&D9uYiN#jLtX-y9qH;x-Z-c3sw%&0~a=ajQSwpzkbobrt zc~;J%<@JC$Qj7Y`fwxTj-gIsfCte-oNH|&4^7Ge>R{4NIAvc$35sJl`%_5SOZa|`! z+!7br?<@hh$Htl_bg&=&y~LwOJcrA{^qW9)={8cQkCwJ=HSNs~?SA~I|V6Mopwl_*_uqGSH(7jgX!IVp$-LcRx z^ly|3Yl6|U%7XHOf`SC!>NmT)yLtMl6&vNP*)uaUd83!pU@O=xZlK49rTxa7Lj}Rc zdOI^6%kTU)w={I<8867Ip6llBo_^JpIRLc3COJOVbsCv68Eq#uqC~#l-Sj$ski%bS zk*iZ4XO8jW=Hqkp@R00V?-xZbLHuJFhbm^tTGs;iRtDW2c*Syg-nPulSfz-XCceDE zKN=Gk*FnzKp4cWPulTP4C-fbMPJ+MOJOteHVODr@{fSB22CuX&7Brp)^nATrTD)nH zClKQkGWfI$sQ$1(VJa--cpU%Yfy9LD#n<>q7QSWTd}o3hs`~TIi!)4}#NOfI;XM5W zk8`_Yh5qI2tCU-=Xoz6Qk5T%b?T+g*dQf^CBoYt@#KxUTmdL30SYTuz+^vrc zaPFj^%F$)!=daME;A3EM)nAZJlvMA;d>Dv;Z}V41LHvgUDPL56;T&56GXKAspgTOF zHoi&RPe)rEnp3Hfe#dH`iILGDz*M$-!4nzz89yoNOtx7fE^_YeH;6MJ}scrBC`%7M!1TMKKk z+NCPnL?H^Jyp7S>Ef(cC3N@><>+MvWFskJm+i|l;QYf*;Un}7i<`s4BZ)t=g+p;9) z7%@=9i>KW=)=9gqN9*FP0@%52LeBE?HrO8^QX?W**JRfm{=Y=XF#Inf7>WcRUp0^H z01|4!MY9YA?B=i{5@9mAU!Ot}b-dqSIy$<1c88-@w4Ze!CBf%M8TfV*GqTTo#acO_ z&bCEOhw^DvoBQyHQO?PNzI zd}R|^8P#)Fmo9TQ%z>O6Q!^qxHKW>r$F5L4<_qG&y)-K2|tt8vDS}Yq^J`xb#9DLO5f8_c(dbGoO+2f|HWQ_6R*XP<5 z?(@s4?l8>Ta`J&tjayer@>#mGxeMo*8yZ;WT(e;aH#ewaLbRfyAkL{sB!x@n&tVxH z5>}ZY)u*m6UtaaG&iYBf*Kh_;&5zO@bMp?sa80|g;~b}{!^1;=YimC36wzpzrwI_c z3l}(fcmlm%y(0a|L$I>KAG`Yd*71a6>((45{&Km9u31pbQeI8rs`D)h(*Ncm3ejHZ zo8~8pwo2t0QBl?6?170L^}dO-LIeShB)zoQ9VN4=;O&X6?p@gwgFpVpBQose2kyxL<=Mgh zGb}5bP4N2c*FNZ&iaaUM=k#Vs#yE@&R^v6P8<{E0-=chLDinumzLS}Eu$lrIJ~%vl zu)1x0C#&a48m>`YUHwpiwb5bNheVv$SiZ$1EtlWe3_&P*EnVd1ebC|-u43)-7e9EM znPh3vPGt*flwsfRyLX%M^y($X40)D(Kl&cYZf@rEy`Zv!FU6>nXW1r;9_;#ua^9pX zG>xOTPb0#o8{NX2Ey`T4M@(RI9-P%?XJ?yrYGnYumZDBivU0Ilthq!h`S(mX1IOJg zEr$y%yh~v$s@G}Li&we$_$ZtB$W0}mZ3hZ6D7ILyYNxDvwC&f=L0O;8-wlsazzrXV z3f`(AR9QqjOjel-bgWITF2vAW@SLd&sTd`qdQxz`ei);(fXQ4ZW~c7elEF(-V*pFVeD&{D(74a)}& zenB|z)irCE|F*S_bnM-~`S`$!g*Bn@Ut6PZeR^+FzaADjYfp6jP~2gs2w*(@mX+oF znA`(A+%pJ1VY|j!l(0QYDJUKR@CJJy*cVHbaEPa*SS8DCvMF%qElT7*J8N`?9|aA< z9-q*!tyC|t%*AwO7O~89`r=}mw_|u8U^C2(ahxG7EiI+Q-fls0{=~;rdwZTP$MfP~ za~HR&?4mad&XvX=`W%-r#PkVl)}77~FdUJwd6Ku6IzSz&!Cd#$wu_9T&gU={b@@pp z&u$r+X>DsAaXI{E-K?z8cGt_RUM>#<><`4ML(sbZRM9ttAIbG6crwWj<9G z*?KslVE8HPPYu;?(T_`1WpMFSStJ<2XXuvL%yyC@OLj|ZIA>Rg zFX(F-#p=Q|1&y_oco0-mX=YNPR`~3E8U(}x$n~sg=X=`WL-7-W*LB|9(ot?2VZM`P z(?~7CM&7(-cRNyX8LQS&vyCJCF87H`wp+Gl#ugEzeJy+kjh3$u!2#WNHlCM>I?mFk zSH8fvxwGSbfB&}EFX7pgJQ7> zr^A*%!F+x~L)QN8c-E;jzFGl9neojZ^ zM@kK%4%~N6V!=fjnYmJ1Rw?6y_nue>?x7H~@(ll0CHKnIN+#W}%2zpwPZ5I95gtBj zGK{47%W_`nj&jpZJzU9cF1SN#>eEdy+Kq%3BJ1-OJ*VE>$z9!n4=Lu0kdyj(x+G?v zW%9QeLB-gov*xf?sA3&*=HE_c7W3Duw7N_&N9$=iMGG=m(%7<5s=BRP_+AY{YUl+G zxuEmYqZGapbNJ4kES-kHStwO+WVnLPRn$Gn=^TMc0&JPF`NW kUyLYFO8NgAkjhg&(Py06&-uD>lpiMmO)wNxre^c{KRsgXUjP6A literal 0 HcmV?d00001 diff --git a/DOCS/html/group___w_r_a_p_p_e_r___s_f_u_n_c_ga343acfd8b3b5308d6c94bbf40efbbac5_cgraph.map b/DOCS/html/group___w_r_a_p_p_e_r___s_f_u_n_c_ga343acfd8b3b5308d6c94bbf40efbbac5_cgraph.map new file mode 100644 index 0000000..c23ebd8 --- /dev/null +++ b/DOCS/html/group___w_r_a_p_p_e_r___s_f_u_n_c_ga343acfd8b3b5308d6c94bbf40efbbac5_cgraph.map @@ -0,0 +1,11 @@ + + + + + + + + + + + diff --git a/DOCS/html/group___w_r_a_p_p_e_r___s_f_u_n_c_ga343acfd8b3b5308d6c94bbf40efbbac5_cgraph.md5 b/DOCS/html/group___w_r_a_p_p_e_r___s_f_u_n_c_ga343acfd8b3b5308d6c94bbf40efbbac5_cgraph.md5 new file mode 100644 index 0000000..004c3e4 --- /dev/null +++ b/DOCS/html/group___w_r_a_p_p_e_r___s_f_u_n_c_ga343acfd8b3b5308d6c94bbf40efbbac5_cgraph.md5 @@ -0,0 +1 @@ +000cbcba6831485aef8883c0d7dd0e39 \ No newline at end of file diff --git a/DOCS/html/group___w_r_a_p_p_e_r___s_f_u_n_c_ga343acfd8b3b5308d6c94bbf40efbbac5_cgraph.png b/DOCS/html/group___w_r_a_p_p_e_r___s_f_u_n_c_ga343acfd8b3b5308d6c94bbf40efbbac5_cgraph.png new file mode 100644 index 0000000000000000000000000000000000000000..458a5d8bba5251d083a04dfe4da0e93dc1268ccb GIT binary patch literal 4170 zcmZ8k2UJtp*1p0BI)FGR;vhws0B>kYmtF-z070cU1*9jT1TayGI>;c^AYBBcN(mq} z0gR4AZ;=op3E)U?Ap!|V0C|`7|7-pKd*`lo_r2?!bN61~J$rxOPO`JL5cpa2X8-^M zpq6Gg0f6fh`0RX&2fVAT)EIz<#~Ws01{@t<#a)$|03dh-H8Z|_|0QD@nIguH>D?TS z-Z|rb^Rk9Ox269#;p^pA`|qR3*lGtwF3k(VF?UQQApat4Ph+dlCXxWPpU29 z<9~E?k3X^#D){5TI6ukIuAk;=+H-Q7nl(RtrpU+bEloSe)n zoTl%>T&Fii4q}PSp$#-~myL{7I01(E|A!ItZ6`MXuqwP8@53%WHAVM6TF`#-QF{IFaOq?F6s2<_JA&bvBF6-@A0=; zqSye?6kmrNqhpk8`5N>Zf8jZ}5df5=laA4HH4_p5`Vw3^nfuQ=yqaP%Q>X)}UT}o2PkUVySF_L+NGnW>a zPlSj9B$eR`DKmKeOufAqgNcXNbu~!+^fl6@DlmS6N#)Xx zta!aWc5uqKn0Sl@!9=d6o?YPu33O7bUscHpzAS0I1OTW)TgS+ziwe-9;l;4tE}(Im zPx!>&rZS=cXS}a@)VV4Go0gASe^{I&Nk=e!H9W_|Lt5x#R^LTs(kXM@9B*1^BjoNW}>WVGWxE;?t}Y!}yztnB*y$do(&l@W-Ghperz%OFALg|950 zbqiW4qtw1;;fHa>Y3JAm+womWUv24n0H;hXP4jk!QnEPtWsjAWpjV)xp(~*u*n4B* zJK?-%E&-TP#FOZ=0~j;{1R| zDUbSuk%|4R0i&ubwlkk-A~io5hlYfO*(WC_yCm=e9?9CDfQX=&!Ga`l@>*r>F&Siw>+T z2_P}QzZC{7-wzJDtMdUdDd6b_fPi11>YyP>V*|`+YK*xeoq4TAaj=dVY4z(TDPKsA zWLoG`hcQYsepBqd$AO6XjH9{b7e^mr$g%M3xjYy0Qt+-yQ(shSt4ylQN-Vk!7ExR4 z)5n?O21v?|OGc0!u82G?cvkTC%_^d3-qz9(>oflCE6l^nuB_-3&~;(9l?>r#jM9bV z8u`K0>OqEMh(gTx&Mk3RO(Uh|nU?NTbNKAvG&O709H@NX`COJgey5HP<>xza6ze;{ zJe+SPUKu<)RVrc`~f&SZ@v7>j6wCPK>hDGNUq{ zb}mv`R3A6(SU+k$XVH@U>>Lo^ezV3*B)NO{9j67W=xB&Q5vLnnW5k5rntX!BE4J=? zd%s@zjJaL11(qLoT9`{!{d(RG5|1hlO|8J<^xX>h+wy;EE7e&+WM^o>NWuHn({14| zQ#k>VomNF*^xi}6-}=|=nR@1h$&Q?w*r^TekR8zzz*(6V2tiXNCG%g7*pX(9WEq4I zJ%DH{_u)rJT>AqQ)z`pl^&d=Jraq4~*4n9kZ4PT-Z&2E;pLnoohcWr`uAVKmc3ayG z`aNI9DaWhEgS&@BPLJp(==)v?i3`Ac90DOPnmDw1}@Gozp zG*T@c2%X_>;VTVgH#|7on8g$9DQY!V0SQzS~YQ*$}zZ@%Q3W#s1oXc8P zUo@ufd|IhSvA?s^DhW3Wqif%U_H*O$Cio$nFQY+89p(|wb?pUG^LYy?C(~1feyncJ zj*Q~kT(6fi%QpS@Fn{ag{FbCgv}^TvfXhlX1|NEQdNwqhkRg+AWzz54`9wuIZp7aB zy>dmY^wy83Wda*Ihzbi{8(s+-0@(vMG%(ok@$sP%B7>jWa}{c+sFZ-RLJn3ww$bTx z0+=ra0WDP(hGiG6D2k@ms2`U?XX*<3kiPEz8gMuD6Uq5Kl8PK;O)bA5LdZo-I%3pJ15DT5#Jl%lufrZ` zvR2<_bbD`RgFva)FohSaM`p6>2L2GXnqJRaX^3fzp`S$CN{s5#p1 zTiSW}CW`(&Ow!$RoR^ErBdDQBZYaQM1wMgA4@71{od(PPLIr3&IM1E| zFexxoKY6V$w_vJxNG6MjwY79*I>Fne$-s$XK|4^Bc+L@|UId9$pK(HPV+T}+(N#;3 z!-mVl*-@Vrvc!9PdJLpJ=>315xHBwuyxK=JTOqXHMioEOhZ-*{_0wrZ<=H|!bp(O4 zd?2&1UY*Q)=Ub8{%)|O?9*Y_rN^&IZJkB^T_G7sctmFsAcc4gvOdZK$kI(5c>QKE_JH62HwewC>zG}&hM8h5^=1s9CBD)1MJBJc8~BQivS( z?pxJcC~FA6q`smF-M_-eUVIf87lNY2Awkg?rBiH$bygbwNxi<2Dlh*Dh_|$l;HT%g zxgfvzWmP!#*06qUi^+$Y>iS$Stb{}mgU^*gB8F<{GCDUdfB-TPb@rHt?6(;dWrUi? zS6n)bW44!aVOMOc*L3Cd(N2t?KGs?mUALXVB0NS^n`eRude=DB1+~O<%ta@+i`Z)j zwIIjfAhX&$n@b_@;IHsoRd6#R$Fkdb?fO$EI#!xwr^^M?#V25yF5Qtys}Pk`?VT{s zHT7OwA)or=E~vSjeAHEh>TFhiS#3#hHP%`lmzT|PHmHx$-O`mRO*~M_!==!Atzi;D zb`?cX%s{z?*1IbIFZX@CbB4@y&j(e9qwCZrlqdmUBV^>JvuEsx3^K(=Q8*>E34zlV zA_{}|RFyi`em%(v`YLK;gJ>xqI0Ke+bPrX?b8Q4XzCc+;rsO{^9;b304gwV;pN_w9 ziY34j?{PSUL3Z60WK+?CDCL=+LS0~bAtkI?w?$C^{OKUnl8!DOf1ht@4PlFoUXy&y zc6?vuc}cq_xq-IQv2%@_CIht&whX8!y<64$S0rZ<)OniB_^}te!5+F%bSXv4-810$3&I)6&J;MNVmQh z8f$=9FRK}!)w}rg>xa%c0F%%`yu9+NbIvH%apt(e{g2V$cVH;-;91>JYLeLT1oXPC K8P4R+<9`Emnj(k* literal 0 HcmV?d00001 diff --git a/DOCS/html/group___w_r_a_p_p_e_r___s_f_u_n_c_ga52f81157111c2436496e1a9630bdce5b_cgraph.map b/DOCS/html/group___w_r_a_p_p_e_r___s_f_u_n_c_ga52f81157111c2436496e1a9630bdce5b_cgraph.map new file mode 100644 index 0000000..8a8338e --- /dev/null +++ b/DOCS/html/group___w_r_a_p_p_e_r___s_f_u_n_c_ga52f81157111c2436496e1a9630bdce5b_cgraph.map @@ -0,0 +1,5 @@ + + + + + diff --git a/DOCS/html/group___w_r_a_p_p_e_r___s_f_u_n_c_ga52f81157111c2436496e1a9630bdce5b_cgraph.md5 b/DOCS/html/group___w_r_a_p_p_e_r___s_f_u_n_c_ga52f81157111c2436496e1a9630bdce5b_cgraph.md5 new file mode 100644 index 0000000..29737c2 --- /dev/null +++ b/DOCS/html/group___w_r_a_p_p_e_r___s_f_u_n_c_ga52f81157111c2436496e1a9630bdce5b_cgraph.md5 @@ -0,0 +1 @@ +0b8cebaa5c584510f1ab65d1fb65de8f \ No newline at end of file diff --git a/DOCS/html/group___w_r_a_p_p_e_r___s_f_u_n_c_ga52f81157111c2436496e1a9630bdce5b_cgraph.png b/DOCS/html/group___w_r_a_p_p_e_r___s_f_u_n_c_ga52f81157111c2436496e1a9630bdce5b_cgraph.png new file mode 100644 index 0000000000000000000000000000000000000000..e2903d4882ee39e036877f093951a3dc1dcab105 GIT binary patch literal 1186 zcmV;T1YP@yP)v!%oy3Kr3T_T<5kN=ng#1Qe0BW_}**;P&mCzi<9# zz8@&bzIprJZ(-*<^WJVKKtx1DL_|bH)IDN0EG;cPCnCq{D5gtP^_%f{e5dX@@)!<> zC+n_(>fw3bp6~lNr`sMgJBi3K5xG!ZS)KI;fQxk(kq6%&-4z7EI)K-w+h#%}G&eU_ zdO=;ay}ey`3C@PYA?D}j>n?*T5WHA}0(H zB61S>5pPvSqY-@HpZR_I_%!o4Ww$ud6#;Go`0{LDey(Cpk(uu`LRB9*9{1QbUfgk4 zuH&1px6E4WR(puVi3*jpL6W6!72`C9;&}*819)$6Reu1ms)7qEFU#FBri(fu^9F@2 zkcyTi&`h@eS;i#nP< zqE1{@tt9;FP)LY`C-rDFdgKH*A1AfD%x$a1JRVhN)^VoCXnUZELZEnD6av8#+4JLwLs$w;W2dOtFoV^ti=(Q@_6`ikI%)!)JquUW4L`KmNq!ODE-i)nPh2&zQk$AAdMF@o6o8$fm%9 z6y16c|Hk_X1&)j0_>m*{eQ8ra!R0gA=QQ5DW?S6z!Z&-?H@)q-abq<#+<%@pA(E5paz<`#+#0{xzf^QxX)JE)J28h39{$t-xCY?-eZj_BU;YX^EH5u- zny<}a5v8rKr;O!HV?UjVTI#s&KNPWiYWrrYNdX0LpaO;BI{tgX6Q`!k7`dEr-pH`fF_Lr!z#<4h#_@ za>5WHA}0(HB61SBvAVOfQ)M00GFw|)hvGlsqV#rmcdhL+A>w)7UJwN9`}_N)7u98+ z=k3*9Ltd)7&WlVpd7gJOxfc-;5fKp)5z*oIFO7$apcya12mk;807*qoM6N<$f-!(U AWB>pF literal 0 HcmV?d00001 diff --git a/DOCS/html/group___w_r_a_p_p_e_r___s_f_u_n_c_gad3d5b495abad2acd2ae68febd1d2c5ec_cgraph.map b/DOCS/html/group___w_r_a_p_p_e_r___s_f_u_n_c_gad3d5b495abad2acd2ae68febd1d2c5ec_cgraph.map new file mode 100644 index 0000000..9d0fd65 --- /dev/null +++ b/DOCS/html/group___w_r_a_p_p_e_r___s_f_u_n_c_gad3d5b495abad2acd2ae68febd1d2c5ec_cgraph.map @@ -0,0 +1,65 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/DOCS/html/group___w_r_a_p_p_e_r___s_f_u_n_c_gad3d5b495abad2acd2ae68febd1d2c5ec_cgraph.md5 b/DOCS/html/group___w_r_a_p_p_e_r___s_f_u_n_c_gad3d5b495abad2acd2ae68febd1d2c5ec_cgraph.md5 new file mode 100644 index 0000000..218a6ab --- /dev/null +++ b/DOCS/html/group___w_r_a_p_p_e_r___s_f_u_n_c_gad3d5b495abad2acd2ae68febd1d2c5ec_cgraph.md5 @@ -0,0 +1 @@ +a948c9ec16775abc07dc3eb3062d0727 \ No newline at end of file diff --git a/DOCS/html/group___w_r_a_p_p_e_r___s_f_u_n_c_gad3d5b495abad2acd2ae68febd1d2c5ec_cgraph.png b/DOCS/html/group___w_r_a_p_p_e_r___s_f_u_n_c_gad3d5b495abad2acd2ae68febd1d2c5ec_cgraph.png new file mode 100644 index 0000000000000000000000000000000000000000..8b51077f7afd9d495a216a83753ef90837069e1c GIT binary patch literal 63575 zcmafacQ~7E_;yOsqB_i)ZH=0>_k3w-h}xwjv}(^Hs7+g4YQ-vQRbp1`6|)1iNf29G zGh$Q)6~*^>%lrF%$MGG<_wpHLNI?wBVWq3#D94$L72n0F@zJ1de1fsqS z0#O8?p$7hCmfZRc_>0`A|i5Na$ zLjS)f{8h&fhQA+@7_6?T;kI+=Xv?5{iD)={Us<{NvCaqd(p-P?)ZdQ?C`l{#^)z$% zGhDHa;xBovd^-HGk=@__6HJ)zPU+w}_3}%FefN(TP`2i2FPi^eKm6(%<;gE>jIZfW ze!dS8lsfr2Tr%hD$!Ugs(#fgD-G5o=41@}7i-uuSaSoliD}y%L)uu6B{moz*_i?eZ`8t1=_d`QX?j^rhF_Ac;#8 z{C_`aTA+EJi@W>#mtg_)&fCJ)i^IRi$bG};w@-|gWV`R~7RY#({RRd&}*&8;bPG@IhhA2FfSnMvj+L3^I z+t~I-G7}QS&FUQ{RehPb?bX)Up_v)AoXK1im*uK>VyB>RTEoJLa5ERQu?ReAz^=m& z{P(yRq3F&s-M0#Fq-{_$91!}{KEAQdI&5u~uueqIz@GF)yS;$e(3afwfSSb)Y}k;x z!HF3&Liz7NW0)M9bz9^$a&*1?Zu6JkFR1#Vbv2-Z*;q=oZ)-=84D9(4P#isiI`My&P~Q-`)>al1bojqAqDZ%&RC)XHbLR6AZ7 z5~b#0v>@0a|3_NLcS9hCnft_0LH7}z)$eWRd{CAFMqt{I*vQPNI3hV%M6X>WCd3UsH4$0}2VpLG#+ zq-ThrPG=!(7??Xc{z(GTpAmXO_TCYQ5)Nj_lK&jwSquQFOShhBXSg@?~gaY zo7Qh9Au0TEcl2msfu8=kCBhF>K$4x+W_Rjq#fy-lL8i8OozI?T{oO&~FUz-*lZUS2 z9{t1m_PKsw7qZsmK1cwqO2gntmQJlS^#(qC@(L=+!U?*G5Zh7c`8*1)sWGS86csiQ z=(6E4au!_4IOo?=A6g8XxMFXYmk9PpF2m=#>bDoA+9^Tb?kOakxEx;sw~B<`x(vY< z>D_wT7y2OIljh2fAs ze8U(K_q;0T`np@i`j>Rhw~wi5Xc#%Do&8yeMkOj#N#pSXnmP|cvLNo+B{L^_FR>elzzmVGDV46?fqTw z72QrGjaAIxWvP%m*zU>d_w9*po>ea@VK^*t=WUgFoT1j9(6+|qSqirAD^~kkva(9O zT1`b^4dZvkD{|_jPbED`I*v5_Ba@5zR#2Nn5_<}|w(1Tc(=)8wKcnFW=cE1Y=h{SZ zEeNQAU;c3~<pmNWwYnr>v?LqQ2pf4lBq*A2hqOxQB-+Okh&xlL|vP#c`G z3wxu?8oub#JhpQ-ujp#x^aC^%VwwM(ZczfCJbwenN`-|M1@p_3X3;Zz)>QOlXN|mS zldUsSFNV@%UBPuYs+#zEnBr+6N8U z6R^J!k<1-dNhbNG#w5VCN(i|#PGvf?eN^AZo;*94g6VCmY)|?ia~jlYY%|?&Xvt&? zpO^>Ri)8DWe*Kg#-%O-_4xx_uoS*+>J;+YZ4Rc?&ptg%7HJ`>Kd#>BJe|wc|Iriz4 z*~=4mX}^+6`u6djQU|I(jo|DLn;g#e?CzQEqrOs`tQM95P3P0^9CXvb5*yf8o2A+) zii|HDNAPeLTwprSL96K08rIwn<7XJCZ=O4KJK|IU1MJ+kvUJGpJh!ZS{sc{0dW}%G zl+*trmtpoCb?KN?LF{A8lvL85VOsV3k87`heg0AJ`r2=mgh)<&yg-F3dqEEH&sCc3 zqBdnb2|`Tw2})tOr%y2xkQ7}^Rf~d)?ov(^cfcAt?Fj1i?H+dIY*7I zv`9V8^!(&-6-A-*LBn_=R$@qpf9fKVl-IYronPm3iYL=l$_;S_XYEks zti|!w_vm+H7RH`RcAPGvrcwW!AK49J7d;b-wXk$OaPT73_vflZc3|~3nQ$YdUq5Tr zqpW*dWd=)R)gwP?@L2Y!@NZ+gSfF%*zS@dGPuDryhquCY9GSaz`gmM4BM0ZcdBcN)TXyv9}}zOm0SPb)+Z%?b_-GtY(b z_zQq$@ipx`cc{n_;0dg+WmRDOxwee6Z=H@~XE@mPyRg9!o|sF!KU&$2vp}<_=)F}T;<$qTU(%|f~CW;rA;;F%4@L|ADSejnMskaI>J=jHl z+0%JA3}C2rn;=GJk-te|D-t(JbWDX;BU>;s#SMd@jKHJ@omV%dr+nj)JN`1G;y?N* zA$I>Qq8!GqpGKviywtHr#LMB&#!IZI?p*^Axfh4+rJFuBZ*Le?;If!>?XpZxehS{v_ z3Br5IN%vlh4%*}1&_PLoH(eiL*yZA=rKlI*IIZ9z#%S(*U%EF|Zj>XCYGyWX zA^4|8V}X$!CQ9wsMHk{-lWvuZ@V85Ee=Xns69Rt@N&ThDy>FSPRvDc|#6T5`jl7@Y zk&NVIWDCg?fBnb=)w%uZf3}F+z5B_MgNW2$xcyj~6)R6YDzk0Sa z(S1v|d6;weZqv<>(jUKCagP(1L(N=`9sqlGK2g#%YVKQ0|CN+g?(YJ|JJ}+^v9Pu|^ zo0ja59`6qUOOZ_@eeBb2P+EhaSQbz9B;}3nu(jR2<@L3y_ac(!1<5GY+A$&q+VmCc zwRlQE|sx@5k?oEnVnyS9SM-Cx(&a8fdXB>lRi^RXUUr6uQjs9OgnW0?kUb63gnAS)@3~}9U*OWmVb>_ z-6r!_sU~ZPQON+L-nt*ZXc4+YyFb+{KVq?F(<~_!ZQhk-g<=H@{jFxgm%n?6gV)sdMmzU3zwG)H zKOfdR#ug2;(U5~rz6f?0S;IfU_e;iEjeu%*(l}`rql-O{;c#=G3=r`{%hBf4$4&_4?l; zNyUmRDV9XAcQ$`Gd9O5vYO@P_<9_mSlUCq_M_$rSHTDrHA+G(QpkD7 zr}bvFxh88}x3LM_cknEe$|(gGSb|ung_2d{~oJCgbHNEoHcJIS> zDQlrHk0fh_6Q0Mm@==mOVJY4lyq-YXKx^-59(gIiJN*MLZpY~mQ&$Dd7p^@`g}f?6 zAfIjjF&F4W8de8gKTq!6R8N66t8f}nXHPyk)ufY0AXK4WE7OJdoP>Ofs*;V%1j`T` zZ2DwXcEiV!_KZS=e(HNG8X8&A!kTP4$YlFB42(@Kuwi z-%z)KZ#4h9$V7^|Wr-PYm($<4m}nB#T)MS1kiW)WPc# zxOy+gQ*j)}l!PIRSjhAT!)_R++2MI|b$`|OI%%`_KnhWA(BzN~ANiI&?Tob+a6f}$ zIkzm3UR3SPRqVKK7@rI`*R&i`OBtps2wey)O*dA{9`=&x*=kx$??{pJwhv ztcN`2Ft|S!|20%kw%zX5$u1-}RBtaE`|s!1t4$5tb=L8ky&vJunvdv1RNcmgBGx2u zZ6D+A){2*P>{J2fI*f1tk5{W=(W?pQrFHyupvKeea|H=!ruX?do9z%j_!aR*vQW{6 zFfdY{tV^o%oOLD20FNQKNrz-t4vx?EnS#ehe!np-nRYcU*3-F7&PYZ7Ol+Q#ojFJ* zq}|k%N8!j_YZRaF*0cD^j)kQtDj7MVg%y8?O81`DMGyagm2K~J;Te|9!)ZVbor`nQG=z?jW=u__3Zqr4tYe1!iJ`g2NENp$_wMAyl>8$zNt}D7hP5QM47?i&!S?U z*Gb-hv^px!=Da^1{~W{@2*!9eWAU%WAokL!Jv1g!fuW&Ts<>B4=NHTb4RB zcR>uRxS%uyj1b0^$PhM_JQh&E+OpwNx;AM zZ{0-HL9A_D&1n7spWyb-^L8a{$Ttuuweogu(@t%zN(?Cj9K>O?GKb+g6;qQdTjgfP z^CF}VPc-{)ef8a6`k_5!Q6iys4B)MGVyl}bFw1!?2A(n9R53{XqtEn)J4ch;{@cDd zfWqiVgO@^C_u|m&na?6w?tkc;`i7&X@eOuzd8JI(?g8Jpio1OFp;-(w&AX3=D#tm_ zeW)d#9HeDl3zg?qF)QgDO9oC)@tseUdRT$B9xj#`oNB#-PN#78b4=LhTXWNpWoI9n z;2#dOB>w1o^2yGsH;zF6Ow(M=j)T{#B@${5QKqGDJK2Ty4=8-UKfx8zJUU!(7&rDT zE5q4({e`8jyB3y)kIKXH;&XD>zrl4ZT-YChoI$^pSM2vLlu4zfiLC10`tx=1eccV4 zcFhjK?WXTzCs-;8&>nhxA=9uFxcnIFY@dlsuj~G4I(Uw8U<#6kFGLNNKQH1qF;Z7~ zit)?DB&o7a3na*J;)IEI*rzm(1eX-cso}{fI}yMKh3U)#Y_kG0F5XV5gCn7}4X)p> z`V$xIu%GHSPchz_a92~!7~yzom=&emZ5Qts5+>|9xDegS^t~J@1>VCgJ9KrCu-c9c`-<$i@Phw_xmVYf z?{;}8T1qyRP}N7>AhrfEQucppz`<$S%|OT%Xwty?Gv?vOIabae4J4Hi<3|YXdk88z zf4s6dJe8_-E$@IZ_<94}#r&!JOCX3Ip-Y+e;(3N;3b4uK5EpW*tuJ8v{^VGAXDce# zZk)}Z0rcN_c?a5Lse9%VUm#*=^?mNjj7|a3UAMdBz_@hq1rB`|tlZ;^N^hQ?x^K{) zaqcaoM+OHoZ_mhO18{Bg+nrug&|S_C8DX!K87^=f8`zcNnu*{*;gU?lKooLJgndOG z7*bQOv;_-e?X3C&Jr5>7wzc3|rE}8}YPSMPxogsU9zta5A3xTjl$Dh3M%QK?@jNi` zc+-u;X3^Cx-pMUL`Q9lhB%@f4`*wfJbU~rlb;=(nLVz8-Pwe1NPF0}3l0w{_HK(ee z**+O-y}M4`23VEIyaZMqFEDHOp($<>iDV@ z{S~36KC0OSi&%JDd^OSGZKAiyC+J$VK)|8$U&XBGCTwi(?>p95b?Y z@acP%M?$gM#pROK%@0L86o9R2ONaEpuIplOu=Qn+A@`-YW}G+yUss7@W2mboi2j!%BrqQDS~f<bGDZBJDu6792yO9jZas*WZbY!;0oAb!s7)BTp3cCp;<3Q&p0S( z&jnoEoyA!|e}YHS;~tw@Sm*swh;rh9P=?P6kC!8R)PkC)l({i>5Ha!$Yb27klKJ-G zsjscjQUsyjD|$WRlLq-^x{I4Z-W1jIMY+3zg)=UsHNej*B2NojoUm+$my=1m9|={V zqRxUz*hv>r37H-8yJYK@Zm6oj77h9#KzERsqnX&kU)u*Ji8No+^3UDZ&YN4K(7eO_ zwTExb(+ViAcy5}$){}iiZ%$%EE_112XCjQXDS;`G<<3YsdceB$MP#kaI+b`No zY-GmIN+?TO`i3aFtYn!99G5|`|tfO@zyL;djQ2)0w4V9gtm;BMj zlG61-BOPruBJg*E{f>c619(3BRpklSNV^_ckE`pY13{*cEF*T$W|s%(%ThvS#iO+E z{=#EOFVY9VKroF`8!{CuJt2?^afH>j9&np$XCsa?`TLh#>W6KLp2^*Apryz67Oqfy zUQ40_gFRD-3@LZkJSxt4EefL`2_2~dTXgR7+-)TD*WmSy<_?$4XIV?41N8o=^ZWG& zmpgttdj2f@n0+@LUIAWTdFv>j)zsILbS7&|PDqUK8cl7*sH2w6{-35hKioKd-b_X|o1uAO1fmlkPrQEo?$3GIE}qymC%WR@frP_NHIf$DcC@?sNoJ2%qUv9vq~Q#jkoWep55c7q2`=j!c~%0koHn z47wywyHmWlqFB|}LL*E;Q%m%`r5t(@{1eMb!NrQdN&-85OS{@o`>0=@N$`JS@vCe@ zJAA!}p|bbi$7tGl;I-($pB5R3v|HZ+i%U}GG1ULhD&AGM+aT@`I}qd-u0sRE76DYx zkMJQy*%f}$3lK?0rlw78U9V^HmmOQK^U;s1&i|!M7=;0_)F8`X& z_m>3T75@XB`4j7_mwTxKHo>2?I+J@8xhY|b*uj6Y6O`Cj@nfHj?t^Im`J2IqpY;I8 z@<^|5yZ*y6gcSQ(Ii z^MQ{tuwYHSN#9hYGXl+h#&`GJ<_C3P{A;)o%~XL#I(PFTNPVVwjlLwF1!vCBMEhPU zhn5~OSCmvJdaDiKS0ALR@e%d`(alP+{j>n($?FUOh#`@}J$!I)s)%2RETc2CeTk63 zvU#?Q_)ut83cRf0?wzxwLQffsvF1*wKCLSJvFHm%^Yo3zjzK(&Pe`6?6j#e=vrqL2 zk%ZQeMd&t*S^AWUOA(?3U_)b0_>@4E`%=dRaO-JOCU>bpe)XL^)_~|cP{j^_`^^I) zNaZbzCYESVZU*PWWyklu7K`8y72nmFKAdw&cSkh5?Rd!55O<at~%JrZQN6eM)( z(EjeMaZw^=6=`>3j+}>_&xqbe8OKmTv`^sgK9HJB6Etddm2P8SP5G=G{^-Gt6Fq%# zhu86vYvg8R+f?*+hl2E}0yfzNl!(;3rV$$fy#5+yKCZzxw6Oh@fb_{$T{%)0;U&%2 z31t#PuS6EcLcHvqt%;?QxUhN>gHOqM$|h70+Wn14zg@DcUZ(D-=Jmedq)<-*r4*MB zH$^VrSlYmFVO^y60WjaWp1_i9%Xz=z#BNWQKT5iuhbIQ6#K_}1fx#CPyx&z%@098j zu7P>H386k>%Wf6JUUnaEB&prw{#SNq%t$KxS|&YU&fg>uH;rv>^-Hv+2c4{(ZPJ~r zB<7DVl#=z88_o09u>ev(Kn~zU!BdeBz$u)@`Nav9CCI%J$^vVLqO+>xr&(5e!Q~Cf zsm?}0Pxr4bADsF_cbxSJgeO~vbn37B;FK{OD~|SDlT(&~zIhOvIFcsVoZ%Vf&+~v0 zn-NY>QA~qo!V|$gXkc-R61-ZEtn2tRM7*o{lnU$dP({#9%fm(pYuDBxhQr-GwL@)$ zOyW1xNf<6XQZaI< zm8UleP+D&mxn)YX@D|zqU#ka@TRCt$AXeu=XAMl9Q!b75U!@k{#@~@%Wj6CCu!r2m zM*LIod>haRmwesb-RY)6j7$~7UwxW7Y&z=xfw~_fn;|MKXrB_Hb{)Svr9Wa8BRK(N zxkF4LUC_m@t^C%i?A(tYLLH-wAKRlje3}m?B3PGGl&#-4J-s?i^R&o--o;V^8S><+ zzTOIXeOit$_d>+0PgS_jPOs_p$bZ=CZzL9?d@|?XG4+0XS!j~qOnk{3^Ab)J$hJI3 zPw%w3(2Gb+ym<^dukxz<`{8&q2ePSSF3ehp{plNAH^=mlypu&!f+kn!27i^hSI(1Y( ze6E6_Ex|xOlFNSYihjn8EG5{%pOk$5RK17>axdxC({-#YQ<$MxPZbWf7gL*+5piIG z?QYc0@9g1yNu8~6Y~%&k9A}nG{c-x<`#-+{{wmaAi5ZE#linvORy!;~=F&EP;iK~2dYpY8Ens3Y+lGa388lOc^F|JohHS?W zV;aG)8XAtOx{IcfMfyVnFz2*Y+drA9p_;81ktl=o!Wq=U8a1qcgcnswx*O)Jlygs@ z7XhFAmTi6A%(u7Wck!-QC#|{0R2mv zSiyg4l3R5O#l|q zhU)IAs;K-J%IYfviaZVk8dO#QB0uly2ex{|$LHZsB9&Yo8G1^ZlptSBRd*uA>xnUsisaDm+$sApHFzFb0u^s2 zyB{tboTc>J1J)^DBN?G0;M@YJVzs2``q zt!A9t4U1VI*CYME&LJqk@<gn2!=n!EP zqn%P0v;(NodmU&^TZJPv-x64FH0kB3rx&9t2R+0;PJnD3^E#l|`Demn86fFY|=4$cDZn1hi9vfk@;jghD1vP3{ge8siF8| zW`p`68&FZL01}Kbws?|sj%VO{gF);;@QYUtUxXuPVM-s7_jH|~`*F4Yv67#D0;jZgT?P4=hK>Qt~ii!jnGgz3IBWhNF_9S(E^Czz8uf4<$u!jV{`TjyZKW|CJ=NzQO#8Ig7mKbgh zo(JA~r4XQ+I((skK5$l6?%rwDsg)+L3vY5al%-v>A>zv zQ$gG|E9vnR1D?hXvye8nZCbc_DpJsH{#J9Pa79M71R3Bmd1Oye^C)swqmHaVvVT=c$F{|vb0NfM!$B5Po`m?Dd@_l0yEwY;YcppEs^tnCB|h{ zq2mA(&Eju;AM5RY7Ws6u*2g4EO^`s|)()y8eH1{yY8Eq6n2E-lX_~^Bl?gPu8}3%6txBHeuT4!`O~SpuN#wu@xoNn`%rX$ohxH8 zQ#dW7Q&fX>O6fhltOc-=D7~-4W#b13LAd>`oW*N%m{7PEuZtIR?8!@VBa4Ge;U%Gb zLXvIpWqFp-7~8!goOH&U0bNfp@7o#ZI{>oGJrMZ{;A!)X0V@jp*&KpkLX3$n;PjR` zp{o&VWrj8d=SVnDnbBOYMXI}7IiME?iD|fYPpcwckSh`CVP=kI}U$Q#^1bq!V7MZniK82mB%d! z8W5mEgq1&I+4!ML~FNE^I3FZ;5cXbl>E1ns33x5W@UW>3Rpejbd0}Tc_ zh!4gf0qTUB+iAb>xmy(ASUZ;lUDtSU^6e#>dHoctnpcyMgyA-ozTq7U>FC-S%{`&v zpxEV5rnH6uQ6r!kGDs%V&*(UV)}T)d3MoW}$>Z7#J$h<_UnqXyYL~H{1R=zGzigjr;_fsY^y?%@rONIE zB-Eq52njI#?UE-61f?bs^YZKx{CS8TP$;OSc$8PADJ@RSbfw6( zyenox9!e7!z+mb9KiSG##Ya52G-ZL)PAcj7pg}WGQD4V<-KhR@kya!0INj?ncN?pC z_*p_lVU3gV)%u@_Jyox7AN}yMSq1wY3-x*_H+skAntb)5^01$tR{l&CKG-KtJ3a_};pfrN@26Hib{KHjD;w58?EhXvla-7F(q}WTjt@*F zB_%YeV_sg1p!aiYElVpa!4j{Vdq}MH)3W4UB|K+}OaATJTapanOUI;?iVoXz9=S^C z**?kmQG?PrpudPTq>eU<(Gunt`aQ-hWuQm+e)ttHccXbDU3W-7fy^^)^-JDqM?MbL zuk)-Ocd}TNGIh}aP=pK*4qo(s^SUZ{_g5V+DE=k+kVkYNBs1AGU#pr(p8|tM-+-|a z?%z|{9)0Nh=aBn9eFg-wt;Uxfc#cYH!1(3j<|0J%{tF-#WsASjcLlIx+d z0-K9TVaGaf!N45b#G3_VeLF=n<~o6v9jEgi0)--ylD`wBPXAnK;dxBVfw3c{FxRm& zfIu5Q?hN`b)&raXvR7_KqF+}%e%-^JNJ>j2ia980qZ#LvG;=OFu+yTRfzPHw(W?St zf_gWyX-@=EBIea>Vvh&<01h_{qeH*ml)Q_JEYchHWHf+<}oQ4zepANWlg=m z*U=lyLvSgZ&`mm9p#9Iu?GaEbB%NQsq!i!Hqo7@iF!hX(OLl2o6WGgz*pz7$HjW`p zFDyS_)82C_`~@0*{kN?${Oj9&VsZ9b=EfGJzvF6=DDTWBH}9TUTM)NvRucTMxEJU> zn7OYplLCJTvsAC!Hr;cqZ|~cw7p{RdyXuVN3~FXFg8LWuGDNohrHaBHwo7~DZS20& z$wl8ur=gjb;^Mv?p{FLepOg4-+Y>jxwH4TcWEJVArA~N0wUyokD?#;8n2H?thh8gp zv~}&za!W{N>|EM;M`-F$9Fr$I8kR7|CfzU1w|7t)gJfvQ23Dc)ottr{3kdX~xOc-6CnkVy(TcOkNM}>kx*VnT@XnUwi1=@<@ z?+T8gISjJeYB<~tCTs-=+K#}qUaxxE@dOEI_~?I%*$SN-$?q8b=IXDo!IAx7KfDZAwY+TVq|Pwp>yVphXXkgb=N#vuO5YT?|xR_H<*#+2najvnKd9j_GZ=Z+R^S?oJG0 z8ycmWb$KE*cQmAMiBn;!tx(o3_ya)xSNqc)>#6@|p#k-p^%W$chd1oJwuga?_brW@ zMV+05Qhn23`gO6j25O5a=I7&XdCrK;>x2X2H-qDgI`zePl-R3hF)r$D+;PY+^dbEF zb(VZhKMvUiY^dJ??pH&!eP0qYiCs+w!EM2m0Z1KrJ@hTFj+eSu zRK;aV1PjWYEzp+o`>KyZaQZV0q5B#5qDx_Scujvi^Wp#DV{Pf{Jf&Ra+K$yEd@tDZ zT-~b05Lv)2x9N#*wzVh97psBtWD>imH|4u}zrY`$^R!jfBrYDuf<%a9!lP7%%IHrP z+oiFa;S;t=%gxa#s{3`AG&kQ##rNL->W9!uK>&T&Q^~4B{(P{RscdDt1w<8`fW>Pk zq0&Ot^-A6bN&aeSv*y?d`7qQUAOsC6+OI_6vl6Rp;;_6%+f(C<*BgiqVD&qAXD{>I zb8kFw!}rx)8+v1bY;EU$EMwP;sb{j%EP8o42Ln;2#p zt3B-KQ=0W1&A~r4I#W6VFzOj4?t4NtVntpNo#Dq3>eB3#w-f0>o)PzGnmEp)(y{w; z+njyQ&Xt*v?pmFLuN{J4GgnQp2#<46e12Y$VOL^;MJs~wkUZ9AQ1`y z-*#l0swVAH)HgpwyDD>ReN+{B1G@S2_%%{(+|%!fUNtSOo0e#Z5m%38PtXlHqD2J| zZ&JgJZ|o02@aK`fxO1Cbl^IVwOyz7 zrltB_v}Z$cLviPgH}4HV{o2RfJ6B>!Q6$q<#=uT_cF~GeE0Em+7KgZ0Lfnr$VlN)9 zE*{;;aKM;h$y#~KjZ2p(*iNnh-kTe5M$eCtVg!r<8jYe7D#e)XH9&`#jynmDuIb%71PvpxVJWjc=7b#wWA9Ytca6YR ziyP_yi0IK^#*i<94c8mJGtX(iyU=>(zo2Z&fRjn6iNt=tWkd9MsU3UlG4lxxMk?2Q(zIC7ybkoRw%*c zxo;gZYq23)4prRCbm#I&fc;l<@2#z^!nP<@X@BKTw<(NSv3Y5Xvi9I_;MO1TsOVfc z?XR{wmk{`?^ZIOzlpJs|YpE5#UK(-mk1BbuD1Br5^FqsHUQ69{*w$*V9BJs$WPsGh z=Y^&o8_B&##KXPWgMONt@!XcMN$&m6cRN)9@kQ`|u6=pwoVvz%`eQNzz9Myg$P>L< z@#hxMRd(P3j?#2KsLmf(*FzNcEH5u(r5*e1*8C7h&DTF-Bn1Avr#PBl=EL1z^ENTc zT9Sa^4fOThi6hCSPOqWmQ%MsCp|T%<;5gf7{$Zhcd*>~&SZQe~cWNshEwFcIGF96O zgWlJFU>UUdh)r0)GdCXz!VSlz16J$`R98t4>427;tM~PCV@U%Sj!>P>iKIJIr}2^HwT6(p zu3n8|)(j8$%DH<2opyaabNj(6)JoEe@7DK_(y4?UpXM3yzH*IJ|3_v1ewx+a-w?|Q zk6X1C-;fD4a%okBLD~5ZR*|$|@X{aAGrwDY2^^07_6pv7?z|m1v>WL1_96J&EA+&r zB~BPNe(rOG5A=)`XE{)SkscWL&; z7Rpa&!8isze#y!NwyL8ZM$fFE?&dz9z^s2TKYnR1tDy26a^dC##fKHls>1lG7+FW9 z_T7l4kgCrkB`Tv59pl$jPhEWVMtLIQ?3#*w`*gn8&JQaGK--J%F@MDMGoO6P+Y<$i zS9yQ!>C1l~JMqQy)aq*($Hu0DpDejtiw6s0!OFbA#U#wQX12rH)B(}r4G*TWO69x% zi@x2c?v?t2P1O6+L58ED--pMN*j69Cy4=9RS}8WYbck0S&yo1HBcD9l{qK%o{hpp> zGoX-D`$pONR8?Nk=HuccwUtMw9V{PN^Jxl8{hh?^ks|SGomu?@%6Fxd<)QL22!&qB z-w<<0KWoci#6F!u?)y&G2A`0g$JeHpW?ZMc%<3P{hvAbtpGNyBlun(M8UM$QUUIrs z$irh{?1!yo23Hh)WlCVrJI~oksEtFc_FL1NhVlR0{P(GVZn896L3=p;x21{s0~elL zJ~T6N5qD6q=5x_osjW;Q=OnzYA9&-*%qlIP`BQu($@1E=8*ls%rx&{pD|v$q*LJ(L zYG~RU*cU9MGJjT6?`;K#rht3AMrXb!7DzepN`Ky8eX10w?lGcBxF0s*r;f*OkX?C` zKa2n;_d`GQ)#aA#^)TEEHrAo!aUN+-F=Lqd zM%dvS`-9C-nxP<>?DB)R)3%7Iv!?=F$Gpq6`7ks_)*Bb8?yHv9Z*nD?Y zn4z$y$Q$q(=gTdlcoTWj3y=|a6DFh{E&OmOxu=3PT)K;~`RliQ_)pV-gc*fU&Y8vs zX-(X|&2XY?mDX;C+AA+km-g~CPQVf#G?c4OFU7)R{mL{C43(#>Uz1MXG~*13D*!~-+?H5MoEORt)_dHOasn-u=XTv5NC z@uW@O&Y=3!pq%npM1J(~!IMo7CAxE5t(#(fVXlJ)1>)6a!^MBJh*paDck5L(zdCwOjiH@9H5kcQmnYsciR`9pfCn4 zHPabce(lD=Zpk&mcopv>2VebsUX3joA_$!tR6E0R8tT&i{+IS)aL?~gpNxa9EeEF# z$=VNDlG#>4oHS6o_W6nE?Z=;Zd}h_&$tKV3_+B4V&+WM(HIlmV++RP%?$qHU$6uF4 zLUuOXA$LBVZ4J}rloTg5cBv)x{fzf}yEA-G9Wi^ZD(_}dhXHCo{>>U29ToNeIKb`T zNFHLz5T=~<(V*J-NAAAWkyHKnq%qGQXKhX=Qf`!wcx4u~T_0-+4@io(=3vK1{=6NK zaQH#Cv$n&<$f0$RVMKQPR3Gn=FT_jN%mS@VA90{^zP;yplzo71g``2)a zKE0o$f&c`Hz2`4;=-!t!OX-ku{m&2bB@ZlK z$J1NYl%eb1j$E0eWXqDTt8sN_>5Ll`JVS3!y1BFcc@R&!MUcCzEkb|u7WKc5ckz{} zeQpY0G?hmAWk-CnMX$z$c&0;o#JYn3Y>mi%wgTyrD!wlGO-h=jExq6j;{oaxYWva9 zZUwj~m&w^fjlohDj$wItrlpMhQrSz-MHqP*+Pm24n+i{SG5&2s*L4~(=tcG_VRvI*4~a896G6$7^14s z<$)<7^&wvd<6)bK+)~*K#$3AtHXQq0@=5#8E2b<&CBjdl*QJQZ3H=pvp$pnQ5Bx%2 zO>z6?mA|j~G6L#oOAk&~R*!D`4Y`$TGbWkYjSJupZN>ojaA$pxK_pmQ&-()nr{h(f z`|nooe7~)&Y|%RS?2E*W8#fl-JpNR?tSct@I$r=GJ2`gx0-tgeeZ)rNXD_x*-k9WJ zGV$A5F{66Y9s!!DIP6BLI=xvAUy&cm>b_mu?f73DX*c~q@_)Vxec@BYajx~=7OF;Q z8T!x&_DU?hX~>*~b(2cI`LZjjQRVv#5OMg89J^(=q}?b727HN%rL7$?3UnEd^JjS0(*lU%k4?M?c0C74g{v)%dY+!8gHa9ty?YC_?KHIO zZ3b8~ULz})tB>{pbjRsM>pe#H9S`?~X7DX05DiJe&awPsDtGJ5?AcNv!s&{IitGxH zrkXobVWQ~4(+^HPfEB88IZFiKG)&G$qeOnA5>5_Fs%Sxuyk}bmn!V}I62sF^1)y)AXMUXF zY#YESfZnaISJ36RFvV)~xlnK%2KPac2rFYb;Q^xSwh z^Pmq6;x0QkN*!J~oDtJ{hN}kj7Wbo_1LPn>+4-}4;{5$h-is)MXxg*b|CzGVWQi?R z(i-$^Bhzz;l?*PF$5)gv0|3IAo!K8}@3hrnm4Cacd`~erv)frMT_U?2yo)Rzs3{^+ zw@xyLYKYD`(JA&{b=LmSpAp@f5#}=+@oV0Cf|hk!3YR9$1mokK3^+Hs`X;Hl!M{u$ zbakDoqWLRGW&KqCH#X(%HviM7GNv}~ocTsgt-w_ORJkR(iS+w3lf7Ei*GF4s%&dQb z<8pk_e6vmCtC>0<)kmM7#hou|jpOZUME9`UuKr0^#Dj(>D7jF?vSqU<(%X1fA?K%F1Xlxy|bQ~dFGi} z>+LLvNhAt;`g!Mrh2NqYu8Q*7b+s3w{1H>H)|H8~;^wDq+6WVe%KtFGpjLeb*t|Ox z-2;7YG`e8_ayo+lh2;LIL^nHK?RWH*`?7nOU2qTu%Jch zT;JOEX)rIu_Rm#}-MhHxd4z*4u(G+(3!9&w7E^gDwT)?_Mm7qL=Wd)$Fr3d{UD-(0 zD*cN#;veQFt)s?uOS!LG(s!N9uZf`AQn4j%{Z$|(TFy2?7;Qwvxz%3?rG*g>8V7_d z5~B0=8NzQ|WqJ@;<7oX`&$a^Vv!pLa<%Of2eTz*^6Lqfbou_+&h}GRb7C$?jvzuy! zNA#=)-QK^{>on^5a#sLh7th$yyS@nm1%VJU-%Ln;lF?zC|Tt8*o zP<jXNDI3g3A4*cIbgT$3pNvG#Lxa6L$LSsUMZ#*=dYpvjXQYs60Q{-lo{##;%- zXXl$3)eBbb-SseXI`lpyitR}BqmISsKH&`wILx6Cs=lT6hcybYP^Ky}16y!FtFu_o z>$f}Q6srphM7o_`7dxRz74@FZW$;FI|0@wVY&K*3Y5ob9uBZ4kXte~ zDOk?pSv$WlbMyA^x3RN(tJUJLzJr7>gY!R|4wNO|1e;Qx2cnT`=)~8xB^=}^Z^w^V zrkdD-xGgIFWS|MQptO9_XR`Q7?CYnW#x0)3nle4wAe9fHh{u3~avPz(M6wmajfI+F z&C~Dc31_t~6(hhJE@7Sr=zrK&h$g(Cy+`7#mcD*(H*%!2Lzo-%t(ak>d#`wL;W1WM zRaF&3&0_7f_~eJb*_<%mBY`}}#VYWPd8R6FP)MrhR4dJSvRt!fU=-8wLcs z9FeczqNcRpQc*VyX6XahVgP<}Ch7k(x~~8eQK@$6>M{T=@S{;ik0N|Y<(qnZ_qp*_ z((8i^_pBV-<)IM$5S_S=yuXpYuyBuTwWuJ7{I{CG(((kPfwul21VGjwylhi{+wa^@$FYaMN3CZY{FO=1GJu{ooo$DoEq!b+C!SRYWr*LM?MQim4e&Av&aXbgI|b3dkR~EhTaCQhK3jxy$Ke_p;=CTg4aDsF}CppICw$sfw|qC z(L6cM)*oL=R?zk1E$Pp2Ds9Sefq?&N(PEE+F+2BcnAod;__kLW1#m%yR?pdmwVu2Y zzowhGnNTlbX#fW(hCeT{?D z)SFxyp>#EK+gCzGr!oooYrwjovfyJv#cNW6=GOD>m7yMh1V{i_;blp)tDZ@j!#82a zbg)PgZ2pnq!Mw6lUjX63OS{ltB^-i2*k)jwH}$b39p>|BZLN%5H7>sseXI7!iFIxUJu($wzph9`oF04I_$fkql z`vDnl&cig9X6pE_e=8U4XHdLic7b~E+A&x{_n*NB7~+XJ{j(yRGh_1I1j0Sc_7(06 zL&DyWf7!~}vQp%Ww1e@Z>dF<*yM55t{Bz;yk$JZRAcB(Fjl)W0VRi858-Hk9+)F1r zK@vbCq@PJy7;DhCu0VxU^X3IVeFxj)1+XLL@@fpT2zlLx`me)`L zVj}P7%{(~kdg0)U?LHwui3Rm?dXMh6dbjhDYR`n!uHcK7M2qMfh6l z_PcDE*6#5i%qnD&UC4)pmYT=ci|JL+sAycBgntzP)96Uv8|2w$C-M{OwYDvDkqWpV zQyt&Z$_kcs>CCY;9|l68xGi8!^=|HF+Os)J4*U+YXT6tyq}xRh;Z-^hM$o>k)$qfZiNpzJ4hg(&*_Hb7^Y%CywYk4;s)B}!r&hc1r|g1qqQZ;9Vb z%$`poTe$P;v`3*D6H|t~W2=k$ZoztyMThGw%!c36RT5sk$~J01?r9WPEBjwOjAN(i zS`tlMk|uSaVC!y8V=p2wL>wGBWF&;vML*&>j{g2U^U76{ za7l~w1)Gxcd&Cf9woA}w_Blcd0;z8<(sYEE78;w&kB@AU@Fxag^MG3Ay>J#8ZTy#u zM8g8PN#W;DJvcp-r4)2Nn^W{Vsi{`++sVeAYuwXdR)j7qFm0^{1bEybQ*1Ofn*lpz zmy)kZKfm?A!kQOmYiebGLE-WVrZ&KVufN>#3`eXO)?)#UufwmcQr<)_j$PjRKgnpL zH8R-0q9yeS9>M|5Y3tQWqoEJ~;wNpm|lkqT<2)`k&RL$jy}bruBg*nJ5kLL=!!7qd1& z)%3w6<#0jLUVqE9_~NpoQ++_gBMMvPzhC|!0#sYvsWCBRjDy6o=JRL(*YnFeC0k2D z5(P?|U4WbM0rJ3CfmN;9dd`k^=Z-s`M9kBbyUXS$>4k8{bBE}yTIU~je7d{oZ{P4# z)sz1c2xZfcZ~uwo7a}+d)zi`J-LB61Tv>plX?if}BJ;0q<5`kFVL_L$gz}m{Q`^u= zHXlO6q4F%efqq)>+*}~xr#pLABvt>w@w*8AMm+7w$MxW3wj`s-ck(-+pq-ONZr@rLJ%q$Q%#h?#%_oyvC-p|F#)9;(%PKM_=jfWG6XGHQ& zDfQMxW_p^eLNwAVm&BwA2+9TjL#q(B{hxVT#QV``ZGtCt%}>riVg{EuM?@zdeG+2^ z2MR}G_ydqA+f%QaC$5t|{_O9yQrB21XP!*zii?I8aOi?d_^C3Bv+hT(NzKD7`KT*F z&SgLX5I8jph&06iM!Z2+^%tw0*(ZzacFx+t#7UViF6xL+TA}#Q)Y^)+PvWw`7_Gv`BX<#e= zr!UgDw*n!1OuE<50h80j%QtPb-RwKJ6sbH7D)0oy$I3R>VUZYAt!5pZ*tvbHM1wCq zEaLKh-m-G2ae3lGequV}E=q7n{q84X)bWTu4mDA{=HZOYN#;mMjgi3qEm2 zfWN!eCgfsY*AoyTQ7h*u;vae;7X&D9O&P8V38q;Rp&Kk_HiyVd!@iUV)4?*SJSkcnsC=?fh9Gq#)7@&TEBG=y!cHv(5LQ z_sZMfcB08eMH~+sXSYTM)c#TnCvmf0EFCOYzA$)AUS7^_`_ZU;Q;yy}*ngIRfRS|WSX)9JayNwi3sFvWS zFD|81Oxh^Y+X#U$@#3PQ%^(nt^0su+-?Xn?<&}hAVZZt1m7-LZW6RcP2EHpoT!Z62Ge@w(WQ8-0*v^4f zN9VvdpCs8pG5BlgQRc<$^^yYfp~N?pt9L6`T%C&q^~QZjZ#(}?mYATY{ci;oLhE57 zs~hqoaEB02fl;el=*OA5~!J{OHu}s0%8_=)w>J*hwX_zWTwhy*G@IRg5k9q{KHBJ(^-3fFR-y_37>!Ir=I9HL|j{&OuI=%o3x? zf=k`0!Jy8ymPd+qPdj(I;@M`s%0E=d66~&KEuyQdq5AOB73SZPcwQNh6$MLE!vgCA z&@Md#p0rAUL|9VFKe@0kYb&Gw0@)<L{e)AiD`d0<@UMkhi+kl88o4!;8o64$7BjFBK6hKpRs9G*y2n(moiCIB zSNeNvXU&_9lJkfS&aeoAY7@EM`L=bfOQgsT0#WE>C%$WjgQxd=3x!m0f0LuQ)e&Qk z-pUSIfMm327$x#da_Uwx-r%c7vr8@g(k$3}Vh7%nN-d@_AnZ>sN%|W$?24bM4Tu{N zLui7wVrlMRqtQIfk5ENnt}FOg4TMH@@-Y~xa{sGDq)mUzi!jX$;h1OIK#KQ1+CcKt zECJEtdhe)Tjgo+&A_G<(*lpZwr7j%a85&0j)A1KnCVJdXU? zg1Mal8U>|T4cn*!zijHzJknskmcFO%_i&4+zzrP+37-awT0#_?Y&I`L`DgH472@>F zVcP{d@IZc;x=Zt8(H6g7tdehYg0}zRDw*@3hf411QJb(k_+9(Om8{*)X2Ore@Mfe| z#MGZPC3F7z72#_jcMyoer<0mb0bH|$Gh$%el?BF^$-x=`rR+e;a!YATYWXlu*S7%T zeT%u!66eSbs%OUWcyz+PCV|E`W5fb!Ce2PN;k@rx&IWo%box%$}x$eVb0 zH}?XJaKw-fJhz(eo@`Kg&uhCVfhDb9^$9{5kuOW}V35*P%C;W@A2Va2+nj&nv80U9 z`rWS|AHtvk<#fS%PKR>VF#;*!(N$I4ghT^6_<+&+E{2tgVs&>qO4*YE=$fgqq0?BVoVWcS1Fu#3G7Qv!ivtNzbYjWO}e}z zx`->QRWgG4`_q&E1!cHgqHA3gDHg`YFzQ%ZD(sRRLai=fE{y% zEMnf-BuwA+tFmc>5{Sm2)N_zKIta#wcbMy6a}5$^-^+*4_u)_DJ{Ab;PiUoLerEe0 zPGcB}9==_$EZKu;-?=(-N|k^psARt{mIE?}t9~h|DLC#(XbpT7fN@G^NMwJe4fGJ1 zr=hflo5^Q%qW-U`qr^X@WX+R;KDfaea6zdt7Xy=Ai!NOnc4_ogNJ+o#wV}Wt9v|7S zNQ#X?zb3_@b$9ownR6~VcgVuq)1O%uE=}RD=bAvjZHEs|qZATpG z?N0W8f69)b_i<$2NKQ|?l=HvKS=qpGRA5gfRlKJE#J)8Hln5Lis8j|0a~L4Fl}(6Y zAQXPCFDnF_epnV>KI!#OFSyS0KaG;T4rZTz^k``Z)glG;6% z!{7B?91#hda1P_w!A0Av@@m#blfG|3B#-!f^n@oaLhD$7yodkn+I~ct6eiV4Z+6mb7zAe@VLoLyySU|E@uuf>yM?LJ?08n> znI30RP9K6l1;YMKPlQcnW+If?C&OafSRhdo_Q%Sqsj8ByCbm5rs(4+z(FXc`*~4C6 zG9y-Zku6ApoewV_G{mD|Rd-@T9cVp&f(cVJb{Y39emOV1{s>TPf=&ML!k~~2WJ@H> z9j}2G+CWcrC7ew|LE3D6D{qDTNbOxvW84t5bMY{XX&PGO72S1o<$45fn=;h8NiCm3 z^AD@$KnFTr@mzQ??Wv9mwh`0fSu)~IhMI9_25T$xvJbKek!fb&?WLPt1$Mtz_Gg=T z9KR~9Y2X98=ey6L9tAnyNX7`Gis!c&&Z44IYq7GZ2_CZod>tvkEZD`b;$Z(aT{#e* zvqx?S(}#k|bvwAN>CqYtfCj|f|8m{DR599JQWxR3+%#R&i_W^8|B1rDVhLphNPRJ0 z(p(N_iUy4^`sEAba@b%J^YIzwAHsm{MvB1`@-3Pr{jJPD(gKYHkYUxw!GE#NQVT6eCq*s0qY0Ep-YAUiqd2lIfTqf z<}Uj61M~yAFN)`8P^crMQ5#O`{}s0tk2Gq(e8g&fm7(JaRBq z;ykcZQd+v}pQJd564Z!^FZj~?cPy*-Vw3wTw|7#+YvYfS+is+lYcfLfn1ej%xwdy6 zM(?LPJkiE8cTF^2BKWtTf{8_6y2d^tfb;TdM~z4nU?F1#5H2U}{k4ou-# z9xgQAZ}E0V2!z5k7P0{e1>S` z&c%FzYoXqg6H|9CZ0yH*B;~#2yvc9-@^==1V)q^LYkV=G^~!ggHS@-*MjgK?t3TPe zK^rMHxOolG$hB%L&dU{FztyUtSV)MAw*EXgTAlSD0~$!x>>NUyX?C)E^%nmBM4!$4 z!328ejW{VuVAXOGp$84K2Hv|5bZ@**f8u-IpY|8TvZrGG;+I#6>rn;b=BKH^(7wz~ zyG+DCZ}(oqss_A4$_k2%rg@pJx|0R{>1Vw7=&C3yJ8Wk?Q!!|2Ge~vRMZ1SC_E)lv z{`}kqnQc_DaH!$ew3#2e;?4>T50^GqXE}dCdIB3n@KPsUHy^^KhgZ`p2BB}1+4@9~ zC%6c=U9rH?-nxJKvj9(tX7oSQ#j%%KLpG{mRvoo$*)gkyC$b}fycs^AmB_qC5JaHx ziaL3ur!>B;5me>~dw9Jl$KHNDcBoi3>${rIJiE}~A$NYB^BmVQhn*S5>2=bP_ z?Un~F0pQE|CSdviOo8eH!)D9x!i28h*Td<3nm=r-ZrL~%JgLvbxaBUd6MKt-UNEvr zzx~T02sr`KBP%kh6`^H3+IyM5sA?)Z_MerdT8#X71G022rrhHb!|q;OwT3MYc0hIL zct4rtud{vos&-|uJpp}5 zoQ8Vn_>T;k6AFxET+d`UHAWf7I&#R#lY_aj&(u1`S~KS97XtUTdV7L1>FVWpq)^Ar zWb-X+42D7c|Grt;puDZ$eRpRq3^NJS-M!&F;$Iyd=rT#u6Zgvyz$y@*RJXk%ixg0` z2LuEme{^yx(`4eD7whlVaHA2xxH$0@Ex-&+S8LE+!6_XNoVSbcq%lO6Ag7Y4QB=|q zld3@Czc4nadm5aRDCbl_7=r2iT$xOznM#?5wqxDSSvGL%97Y#DObjIMo+ln~j$7OE zRrk4ceOIydFFam#>BhPhTu~xZyfSGWSw}-Mvf+g`*${o6h2n_>0-owBcKU93LUYK?O0-O0zTWw7ug1AD^e_jitMVw<%fOOHoaI%1C*A zrtXjQdvd42$5=j?d@R9N@c!;5?_rlTRIU6;d-GoL6$L7H)%-Xj%4(pRQ2kG)IQs~+ zsG9|6;SZ6Xv~@qZOJ>Q0vQC#jwO=&aj%_3FCGPL@1vQFJDs=VK6?#<#3D0`B`|PA9 zPE30jiXC668Xkw(rFr=lEhzAqDM;{`4F>a~-jK+Ac{xMefjzAz1FXgzTuSDIbfRpO zAlM9ldaH6o4B3e^#U4JyI4aHfTwN$!BaQc0H97mB-g|`}v%h?!=#DoD4siv7af$Qb z4$((!qZ&A|MAbJJDQ3C%r6RMdwGv1PdnjLQyq^Bh;&Xnb&E7!f(|T7Mrk62T8vhUK z=}(`Q_~02}1yEYh_-LC1BhslWeQEj)g+_UbX-lM&|JuMQqdke&(d(7pm-@lK^1IB} zuBt+^y~kZUe;Q8}TW7A=JcX&+%I?{tch#Re4MK~zQ6lVu9+6#fgt; z)@U=Ad%tCHOxOYCMwBxi#2*$qA_HS#^LYyr%6}1IP%(A zhS@KveOky|Ki(h@8x;yhsC>sC_$kn{qw**J6-#N?@2c*SM+lE4Bokdv2GwsyNeZHD9kvl-ugT&ystqUd; zW~m^!e7GP8K{uGM*)MdNm*_AeTH>$YDnvX>>4L6&-X$$e;N_q74q{;NYNfh3BU>54j>0Flvbyi5&xQx4gbrb`17CV)_BiwGiBMyUL=q- z{SzMF5~dwtHmrQbaDR%^+s%oEMw=7EALi`Ux~ex8${L0=+fjRBT{Zg)tQ71H38@9) zx_gPvtUd+-FJIYudk!B!9l#PyvJGC^vqJmjc;L}18)%hTuw)rYNZ) z_u*&C0b)YSt6~pEUTQ7$MAPIMsWqKyJ(KY)Ah$eGjSgG#tO0qHe4jEH5nmL`sur5w zzTF!q9(q`}6a3b5DQf{a1AaN{AJn9PL%fR;@Y8k7&j!O0tGfGY$@$F zo63%OmwlM{p@m}2`^aa>sHji*qUh3y=y&A*$WL4aw|D8Wn%)Sl@jwVDr{b^J!$jUF zz#5B{3M7MIzo8fNAU}!hJ0;lGP^^z# zCu3dNp*Qlu=K~w_JE&DgqEQhR{UXM&;HozKJ)Pe}Gp_E2H5Pdl78je44oVPQE- zXNr{OvyRs_H0B8MM1ihtnJ1&~YYqE$n}Vi6gYT%gVhz+j`72l(Var7PM}Okg6?Bh& zO0aiXLpoL=9jA#;}I+M27H>pCK}h zW=%ecR8i8X-~;@3|L9$VBAfCC=8zb^gb}{>rXN-SV@O6g!3ql!e3}zIerztpfy?VV z1`}%1>oyzY1g26^#RoASUtZCRLFhoEp71Tzen{QYH!w#Uacd2Qj)*l0{DzC(LcGzY zWwh8bSpSh^8mDKqy$Rg1l*t$!$~M^gJZr4HJtXzdzwtSy#lC-%bG5KCl5?Fy+kOD$ zrktiv90dqQq2{)E2ks0F4Nb(dQc<-IEcfDarJI1P)?P+AYL)$>NCslidmOZ-YXk?` zJjeBzqRX=qbG*33zdepPK&3m-fC>Z^3g%R>HVWoL5{DJ+&mw9uzazokrPs37utL<@ z9+!}C96^@-+V3~>altPEhFoMYpDV(d(82!&$&@1$n$*5mlnOxBp*UK`Kvbs%|a^6 zxIs-_UH|atPCQF26g)CBJ2mA)yGK$`R99C=xrg35Wazm^9olV-#p0KkJepHpQE{*L z8hBkxi+|4-L`|uQOC`0+%idUdxfhwjt2{(KX_57;wYuZ^bDAuk4;IQZ{oTsiSTfJ(r zLe|j6U_wD`ym!+RwgaDK_mw2>`n*Ms8F2NVGWQeDgTm(xIeEJcVI)LMqlPsbl(tA@ z^NJtZ*09!nc#j7Dk+!5C+wtn4$l<@tVc+jC+u3hVKC`W!*jmqXbB$^P;llHzgC@5_ z9iMws#`KPvb;ZE*ZFf~_ZO}!-y4CUM1Sh zd74hKn-btLYkivlW^B|&M5OERNrfdTTolx~a6SBq<@WfCl-;o@1Mb*(T)s+{hz44y zW{nBpj*eC^y`|#_^T_?J1ekc zLb+O<@mZ|x%iEmdJ)AYE^HN}ASR0&jiTi&8`OL=1uL3uU_f{wRE`Zy7sr~9fD1QR8 zU>i(qfB$ZZP#j6cFD1tYqD_!mkLa-{Ea6jJZ9CRA>~0(5*vhYt>F(O#JfnoVMD>d0 zZ}lE({OwK5iuFr)hhpI7mr2VdzDKt{E^p!As`EX>lu}E;uw4O!a=z4BWoma7MYMs*=C)vg=#x2A@>{>~bUQ|#&wXPozB0-EQxh2Sq#eJq zMCPQU=XHy9I|<;%bF$yLw*yAaX(w@B#$jvwziuY#z_LVi!_3r1vsj>B9_z>H${$f?A|3J_gJ1hwi3FI?`A%;++Fg$r$;qwF$RM-qbTFcJoPHj_ z0h%bTn()Gy=iHCY#<}DxJ(e+_;eTYk`WVZvrTfr0p;~r_)qI#|dSJb};zedn(@$11 zx=!NERku-=dOE)$`8J04))wLZQ_fwhdqXkNVA1T5!{VNzd+3U1=y^Lsj&?lp?-)M< z@R$jh)%xQ>b-|3r4}ZhfKYj$()nakA71qMvdL#uiXO9qw4k_aGw^r7V`))9dkSN)B zc|vrDar{CX9bSM}j+ik~(+rTvc3E z0ALdrj{YZ*Z?37}CNLR-wL9@RF25-&kw|{udA=(<5Q`qU%+R0K{Ag(q!FxL<22F|j zc(~rsoMcj+v`%nz9G-XomIxjl+KIF(EpX11e$R?2inZP(LE9vfg&}csm1KR4{BZP| zuw8}ZkZm=388{+CBk+7=M+=1Ga>+^8_iYS^jj}ba82yqmcP3_->ywL%>7KWlz@zUs zD}S-FuQHd0aqpE0Zm4#pA%-D}{{Bjz&J`fiCdWiZ|G zZ7fOed!$v~Yhyq*hV5qH@+(zf!j9WP2jyMGV&^}ON65RxY#M=-IQk9Wm18~ zLG#^?L3?1jonGNA>5h%^M&XBuphr6{1WS^`GGJj7J+*7Qr zOdH{v9El*^%4`N|&d{%DE zKDJxYO2{z-WcGiF?Et85xeRp6(;%9AzpMI|aypV1o_s83l{8m(1l0HklSs<9ZiJoT zO}2O^atPsP5z-ven_Itut*f+f@p52T2ytez-x7I^Z;guc?W)}~`A;RjTCb?3>8=(W zd?Yk;i?easa(cP~@im)JTM(zdFBhbr22Q}_L+Hd(hOUNOF4dzOx+#->Xp}5nW4q`Rt|0R+Wn$*O+-5h5 z!*#F*W(#(goX334X%4r0t!WnxH2Yd_JDb-w=~oA~X3aV#j(_lZej9CzGC6X}PUqHGh^vRz5@MWyU#q*?=nO~gTo{qzVC_LZt zI)XqH8bL)lOXHPfmZFoCn&$P_%PR%nYW3$$u#n(Cqts$!+a5n_CEQ+!8W@ zumn1*j>-`$D^ubd0#(J~uolTB+S(ctr4b*NHYlGrercic+7dDt+ARpgk~o{hUdu4F z(H5bZHmGIT_)Xt$4i+1xn<8LbX#4ALk7!O(1@1nf4GDC36r<^0l{@h%elwQ~J=XGV zlilmLX?rD0aaGMp5yx4|{>>1iXIqNf)L_l1ZCR5Kx$W{K^3>&-SaX#o*oZIelGL8$ zBXeoR|8(U%j4Kg~NzUui;5c0&+|#=@5f@algg^-{25FjELn_oypae|W_0aKE z%t4145GL|lFQ0~3;c++LL(cJ(#)-%FAumV^WIuP#(xJYOb${rfNBJ{jzX8+y_3Z#y zu3#{_+iM`6=AL7{M)r{uRLujT)j_b-)XHfoTPG(8)SoBcsL8g_$<%@I=Hy| z&#i{p+_oLdnYXLW5LaClC!4Z?Q%QEL;YLlfDWsbY0)Hg!c|9zD4U}U@AEHqx?K*y# z9}ApH+4BlYqqlJk&h=WFuZxi)8m3K?$wfA0BV`)=v6%5lru(owMk(eYzh;GdRKXO7 zU#D*SU8MSPYJT}lF9*x*kPEy~pFuz9?K8e;jQMVjl9Y*EK_x8WwuQ9a_p~l)L{kvq-rYdLdd?@y=rjdF+yd zWby?=JOP$JLht6!0ta~G$_ikl%jPhHaH$M$&u`+xcUZH-Nb>Nq8u3I<-6luTm&E!b z(G#{yl{MAHuVs7`%4`*2`={mOQk*)_g2MU*a!HNFi!}wkoTzJ9KSVInQeAh*+f<|M z;_wOOpQO4!eXSUsL1%OW5t)pzP3mfP`;63JHF?AgatYGQaUAgNcF!rV-ZE!cI`_2^ zT7Izn@cC8VplUip?(R3-4g-A_14+1-k5Y*Vs0%Gq82d@yUQ;Vv@;aO<(AUgi>>HwnINP(tH9Oab0S!>* z$)M?V^uS-APDEqJkKV}Q>glvrKf26^mbDmn<@MsC=D@53d3<@l7O^9(kR>Y9wBcol zgoC?Mc)a-5u-`VLHyb74lusd8*w;Ij40Zxtil5DG?6W{UO%OX6ox1h@YnQ0&VoU^k zd%bfnOiAb#?B$1Wbt}N~N9)f4M5}3g7ba%06 zF~%&jJb&4;!GOmF!B;keq|?}w&qhSOc>(r?@T8p-uV)IlWTos;!sv=)QmnoYUmgur z>lB65%9GUWBmN9?g2C)wtcD5y;H3|JLZXaeAK~6EDbl}**K+iye_UF%> z1La4`-s2gv{^sTIwjO2(i>XsJ@Qkj88&TN~Z77C4P?RSjQbct#manT@y>YYm>IhH(<(Fv+^VcbU|C31t$VT)kuK;-+G61QR59S&si~AxCb< zFV6!%M(5|II+IH+dDzz@PIyf7>Lpb)axCo7%S(+At#xFX@G3EO30`a*2RA0IolKkS z%Ic&Xow}aXb(2RmPePAYs=_hqkt5g5*g-SWSTOYFo%j=*6N0EB4eQ8DF6XpZ7oD_l zHedaY{@(X+_9d^d!(@H#UL6VaD@}h`X4QB{+uMqY9Dc$@b{u)4{Tew>U+C>BQI48W za=GttBBT?GVg>px>9pO895hEj!axyW@nUHtRqZ!D~P`1NYk{Xlc_im#1z-vMu# zX{;JTzEI7sUZfF2cR-j4@0*5njSNrgDS-kedI%nLzph%H=_M6ok248necp6AJR94P<|eUI6asw&@44w&00)FTUi*lFWop5E z(jjO8;wC}8jnE6HRllXJ(aPJ}a35-FK_j_GLJb+DHG~~wRBg)0 zS7HqB-1S9YZ<3PmFpPW~ORP%vm#P}jX`mC-c*Krqq7rP5Mh2Jfb!OqyzgjXYQ-kea zJ1r9k7Uwq*`l#l1;qTd}Y(Aa*kp|g&qPPxe*O0>`$A&lIhJ7u>7p>SpY-AqkTT zW6rnn%o>}9h0pW|@K&(@R^-3DDXe42{}6qhkk(i$@ALI{P!s9hAiQ@MKD#-JR-@Il zLnkr;ro-)Tq>Js0(@KVueW-_%H7so)FRSE9uX0VIGtFS zNRc;dOpYB_fpuhI=B^$ZiRN7F_$rj6Vb@x!!ZK&SWgB{l5;d{?)HSITi`yOm@iyw< z$(2(}>p5Odf*do6g~s;X@}*&#IuQ-LSrm-f0|XG+oVcP%V)pXFEvMiS9d{O5)+AOf zq=w7utR5@tb`6hBU8JH3Y4Rs_JV85p{l+RdF_O(&0-djET)?phIs4{B1{`ZFUHL=r(8nJb9Mxl^1X2gn;9ANtQ@R*O(7-?(HS#nL??2p- zD^<|_=%bOD{k~eJ^0|5lN1K5+;_KZbuL_voOfAE2R<`N6XYWm=c_D-ekqZk89S0EG z(B^d>Nsq0mS17*6j`JqR&eGsH5dmYi|rP%7D zi`MLVv>RUrNuU>uC=5)Irg4$WmSZvrh&6s(2yhQDSD%3|m(ZH?Jln|X-G6p0cpv;T zNG0uqEE~+!%uE%MMlm~y3CB=8I^a#TWkQik*;7Lw+Chui9GqHIvK%DoKzdEk+>}7bOWCSF z&p!!D@F@n9GEgH5siR7Gdxw;87xvqeir8&`#~ur4s?gw%rx@ic5~GXqpd$Zf&>p`Ka5^+<~n$2asAzC zxO-C6)w?DlUJn~UQGW(gtnx4=tPH9I)lSQPMx&}u z(hFF5pGFS~4EfLsh!T^_dngK%S>iXai(L3kzqr)m&%vqppPnlU8RZKO7Oh$Ewt89x zo3c?pqxYMRn6n0uD;0BT#*njq&SOdV4s~`v;j3f6NJe&S1J|{Rg;$<*_;=6r4xKJy zkkJ~V|J~otcJmITSQH*WJhKXWR&5Wxh$1pmpdxGc}*f_a3xz`maH5(*hz?2FSI2YnY8|JA~g{ib}P{J|AS{zFRZaB61lGrf12;4h_M^VBD%FReqac^}-b^cLS( z!d)2mR)sgsztxxrc3+K;X(t7rqaGjl?U9ojqq+`wJ(Wf+`&e*^WNT|n>Ny-`XT{2x zp{?BK1iNK!qq03V+c_>ecQ1kM10ODM>cMjzVLr!XJuWO6^P2!$;Zjv*x*v{?>ynZV-|peEk0T9sg*wS>`pWQB1@aWq>Dt@p zIB$;?o?DmB7@v(f+>_i1AOk~3s-CRzrPd6c&EV9$Q2@TF#>G~7M}#bEJF$gd&hiR- z5%WKPWOSi^W(LYt&lN!KckxHWMD@@MX{@&zc|9>F@u3&9i#jcR@%N7U#CvyE1AE6O z@8$_K7}AhVVpp9Bb?r^+>Dw!sue}pSwuQf4Q7_+_JK2}`#tx#_&&>MKI*ZT?X6iD! z5}J${837<3`R1-6E~-+JxyFEltq|EW2q)q4kr5_p|KmoZUcVK9)6_rGLdi4~Umb$UR*1fS^M>G-{h zr*MBB(etMCG0%U?%+6Lis_4eBxM5RvR&*lNeY-klDsn70xDD;0Vf~e3QkA_owsrb> z`wP1{!!yXt#|7Qf{9G)U`qAVh)54vY+v#y3&Lq7NwdsKG6L6xt(hx%o3TFi{Q_!zW z#mZvbmN7QtDt!E?c(ZDYZnH0&j~;1I&OYxX`9$>nS$$W9{16AcMJ@1heDJ3qU^pe? zXT#;aG}dtpGMJdXV+}`(Tt0-@Jn(Ma3*e zzp0qN3-1qU|7}ZY$tJpY@=dWTbcGP{<(ou`ov(Qv_I)z;&OsX=XPw!zgk9=74c*=n zm>~V*uV*WEG9lMv_%OxJDm|wjEq3V@!?uObzd^_x>Rp#t?AUjg?w!|cn@~!R6Jyyq zJ)v6xA7Pt&m-KODa3n0w%C~eTqiRfuxIYNEUtF}`X4G}^*XfG>!-Krs_kDrc9NPmu zHZZ!|a}wIfs>k1bjQt8#R>;pN`~q_AVi*Rh%I_p$|G?pW74^JQtyc8}fheiMV5k~B z|Do;gSr^6oMa`StGSOw6!OJEgQubmM$vU&|g5MvLP0keSa!fe7i&YdE`*jqn>2ahO z7cZ`Sj>cSnL9hWFngZsOgJj`Md~NJ=%!)^qD)0bxt7}s_=zCLQv8FN~Z}6%86ET%t zRX1owGHqIDUd~vDdDQ{AV}zo)-@t?ZX+!FWkei;WLiM?#ECR0W;Uyk6ld2Nq0;AhL zKa{Ed&sW0l7H{GOL8wshp zo|qliF5esHQH0N9uF+!e?Zu)tZr`l<#8%P+Amj9zJ5BRs6oFCZ(@5k*z=T1Cjf?`s zE_HjNbsZt^`Fr84Wi z-_!`OO$J$t2e+wKCgIKEvMDf+qXb2M_Zv%UEl&NWZ2@o(a}F`y zIe$|&;6kG(#{CvsgO~0OR4FS;y1I+wrwa$jF2|OzCMIlPY%r94MipGbrV(6#0ERPB z17SP#Eg*Hkb1_v&ea6d^F%}*_2)YmqnYCw)yK-*K0n(e<^NuX2hq%hgrIoO02SD^T2hsvbJZ7!-Cc#uTR*d@@e!J>a^C!Yr?*UeDUCS^FMs2O2D)d)dznVFp1X72{ zN1-3hgj&nL1pXgWUmX_J*1nBFNT-05bhk7^2q@j%jdZt^AYIZSA)P~aiiCtTGt$xw zBOsjv-^TNv^ZWK6TqxJI*Ix0&eLweFi#Hu6%Q&dJKnjo`QH+$*BnfVGz-DFaN9dxa zVIRmKKl&pq><(llJm_ejW`WEC5QGp~^Lc=)zSC~SWc<5Ni(J?V(dU7o(y{N-y( z-A6ALvBjrhX%Dve=Tj1Xl^>(HNY1_Pnr8il%JLcYmJWC7`W+dRGlRoJomR6hgVf4Bg{{@L_$grU#b5+;B#wrJeEIX;k% zXr7IYTWnx408|oW;D?9ve9a_xUPRpe8~z@#B;A|z5KfWa6$#+4@&o02AV4)^m5JtA zTTxZzK={ddQy4p0kB^TJG!ZUhZ)?!zd~l+Genl}wAW>=cLeZUcy$gQt z5rs@kn~z7v8{;jmY{d<_MOoRXBom|AcNMa&w8w>OZd3xw9u$rVMN4Zg)wu}>1adC8 zq}L6rWBdl30F(PeF#JKl&JLx<{K;JUx$p95!<{00*uVnCun#!a-uG-yX9jn4k~i?y zM_Fhq#W2E*C%?Qrs#qa?TR65;OHVHoj;ojkK;doSrxxmIBzEhNJuCedFUD1*J7@^w zaxGZma=$h8wz^%v)1m)(!M=vu`(VjI(@Igj4o3<1 z_0l0@yd1{rl0uy@9!jgKUQ1K9zL3YS38Q0dy}z|bDJN@tpGN;lVfc^nNy`Dn5oCb- z<_8MfAXuG)rNEQ%m5m#GYSe2KlBi4= zaiVsh=TGk3YKG{l$yvyP)q^z7MB*Ecm%UfFmc1P*?JUL)$cOaczAK<_=OXEs(g`)f z(E_=KtU$$NkC?TaiFI2P8|`fXTsA=Xva_)Zx>DDEP^W^I%#lgQ$!Yv!GzMBi`}DB2 zqR`UvNY>cDN)7@#;Wxe}Ac@~7qKCXs94ngJVV^Fz!1xJO8!Q{TG)mSUO2*&N%8cbv z&Yyfzv>R%SM?s(^1=!y-8@5tz?Oh_{&&2qMCl%VZW*!7L4DD43Qmwune^>c8Nt)AH4U2ea8Wq4!O1u3(h#ZCaMOGCpsRLkaixO zrJDlyi7x78s}~mG;cf0a;HTkdwT%Z*=PLo!0J8x~?!dF|Z!egy=G^y@Z@XWP#EhSk zL7>-G=ipSWfjF1yK=AL^VkTZHwbFsSzpf|B%2fpu5MpQaAV`2(ez!y`0)p@BpKpbu z6Gi!m`7GLnZiTE*V-Powa~hx^xYA zB^UfF2!ema;zjO|5K`aW1Qr<5%G~ncP6>04@SUinV!?dh#tyUp9~Fx76mg91@>K}0 z3%Hev!^O#rS_?og7otv|1(b}(JY#_zM^W?(CF29pzg!D>+(1DEl}({yzAdLIi1VaB z=0c)*5f-yt%U`&J8@bzhU4D!EDR4rE^i+XDRR?d%LNp`fxWQ|yJ-U`dqu6>$_CVn@ zlGip(u_h9jzLue#C<&5P&uKe6Y~=US)XlaRa+MAep+Ii?w(mN0@RZKQL6e0v^wT$J? zr0v6T6?x>PY__)hi|n z5bIir0BUQ`eZ01Lx_-7K!_c(QylWh-y2v1l0hCRAGyM##WA&B{)nI@b-#>IQeH5!f zQaK{Ygi4?yPmcZ>i9D?SEzdlY7WyOUO!korRvJG>Y#k_2rJ1f%8MOQxxBppT82C~m zY-M1Gc(qXOJtMXjlQ-DjLP|y!zJT6l`_+_Nn5a{J|NV=eYs~Yu*u}!BKv#>@on_zA~EXM&RB?RELOofQt6J&y^xYu-atqfWiD+Q(uW9c^d+Ns(?=?W( z8{ubSINjMeskiF^I_sFcfn)R&uq{BOxl4$3Rxh8GBqp20EC-?pf=4c`k1k)!=&FG8Sbi{xziq3fDH!rtZeHP3Am1Vk*)adeR;gch zQ_S0ZrLncuu3qkBYu5St8TOBgTWam^*&&JJp2RTXX}!GRD&*v?9Mh=I;99MhkR6mG zCmctK5GM5ZBc)@Ohew6HWaZp2E4gs9e4e5q?Kh{56xvw~O({(-swn-ZZX@;GIaF+e)B!g&$)Q*=Kmq2cofRv%E zU0?Jgqna{OSsqJea48`N63GQ&%VSopXI@Y*bpw`(OHpN{^EjgVPP;nFqyrMNQF_Ry z;PbCvdYfo&#mRGldfEsU9N9_tLe9I3!2(<{(5HI={6hAX-*v-`#~{( zJW1&!V+eE=)CF0Dmsc%booSB1Ydn4{2*ZDPk$+QC!@GHcQ531gdp&pZ+*Yk* zZxnjMsd2n@%STo6ntnu_mF7B$Y&vfo6K0lK#Yq9Zv`je59dEESRyZS(-{BTWyu9|K z(rEJ{v1r!`YImq){gh?;EKegMslWfz38Z;i6AxlCrdx*kH=2{qhNZrs5)i*DG`OYazBOy!vj`eN2}Mtxgz)DfGQGtWpMTcJfkFd?Sa#DDKG4^5?WTL98tx}5eZp;3k^yb#-^az1et`ox(|6BU@dkB1dSV7Qh+iPVL*|j1N=JeS!B4?u(YvJ`tObLd@VC;LPdf|x zcrK_x%rj=t)b9;v#XPLq{aBc>gm`1@u zPn)CrWJ`K7jpq2a_wN&8xn22YHs?&s4S!DeePvq3H^WJ}iHXsJho3D(M^fg(N#eMz zYv08k)BTc3-JllxRD;%1q3(OYgJ9~VmNDe4T?jSszYg>owXFwm9lmKBQ_K@H5G~o! zL>`^Np8RH7z6pa5<=e+W$Q-d>A7U1EnCBayT*pgRmqAD9rXEmEPR{nJVNbrudgYZb z-lxv?Bju9)m#NKR?;)$rRhkP_*DOJ03X7MyfaRJWEVXq6qI%tQl&N$UKI# ziK|DcJt(IIK7rg*ir75>$y#^hu9KtR<5|V_*Yuzl$_SE`p@+>&NRw%{Ip&(=KD-3F zcr=w~HGKDWHBY!>CeJ=>KBu1mOH55dP&?J)t?(^3E@YtBXur?I3BYPM8ea8K2zcm+ zgjh{CIP;0s&}Z%vsdc%bH~CXQ0wjF}MhCMHYloegY1zHMIe}(9o6dc}xeO)`HF7}h zps_ARxs3X&ksC_(bz*Tr5Tmu&FG-q}N*#LQBaHi{fYPpmwX)98D}`@Y;7!81H_a>U zu+wP3*N;QG$FdnXAE%EQmdqhLeg<<%rCjS$3$&YcDTqD?E_GsTAWFEZZ67|?23yFc zdjv+vw`eXRUtf2K@8g{3uyZ)dg@fY`hF|r0zXA;Cz;bWIE~%HfH~am3!jkjsds_e0 zgY7@k-;|w&UxEEgzOGIwNOUy$*gQ(c?(qm@b1~x6zT^MI(-ES5`f_(!&=goJR07PpMBM zzNy#l>?PIEcZaNMWz<0Q70?qIb&($ZN-7d-C>4kVe*zSyL({E47fAD(q}e@f@`pf z;;5Hb`Pvux=Za*5C`ptDT&_4$o9VuprpSM=sKrjU^h^6qFqU~Rol?noA0ef~p1gYP zhi}TYt1>~COflcyysbgQNz_G8gtFL8!fQzHC$RKnNds@{o0h9g27tK%Lw~kJsc`_L zngB-821qWl5w~AA0K7K_pmo}%!V=ok714NRiKnJ;Z4OS3ZTsAB?7gQe(U{j($}fxT zr7vf)v)joW^7aio$Zt(bNePzht_@E~Q%O@L5+JRlMo9nwM^z zmHqhl6|dj7(lLq|s#{rE2{8vAT)8+ZK}@6PNO%S54i-79!H`i1`A}4^9$JrE7#T}n z`&j5A#zI@Eb-TmF16P==uvceD{`o`BXEe6QXldUuoOG# z6*fP3{21cO81KoA|E5Tp2V+_s&zogp!qt#e%f(w;%Avf0+*s)Y3ariR@`^i3ILI^S zNBVt-Uo^eZk!8IDP-dtAjDj0-0)WJ-2GdsVjEABbC!5qF zyhZvDoUSQG!t+dG9fWkNg@^DMvOf#dLs_aAp|TMx3lO{FtC7wv2qqwW^J`;xB;vHJ z@lYZf&{44K(qM$rtBcW$Jfbm-^1X4<0ia&uRedt+fm!-=EQN{K3$t`{e{=kL#>xPo z2Yu;gF0MfIIDQo^;!)w<3%yD69I0pF@QeILI@0T`Q=xgeFCG4%c@%`^$Zsb-m7dZU zZ@bk8BBl#m(piGUPHibG!OuB)JTB5JR#NXDW%h?{fUvLHVyok$*VPba6vPctLB1 z?O-T^opBC&L#EI^s?hXX@pmaVL&ILFJg>_W7b(-I_;j!Fr{jbfT83lc(TV(ilP=#i zM7a|W(QIT+Y1}&Run(9@AcMGQ@J5{d$KU|dj0w9ab)nG4@gjp z()*iVa_`|p{BFH3eSLF{uoJ*xl?ArYjE$nVXoq%0m2s{pAbPI}AS~T9;zjm*<(y<5&c0iCSy7 z^(b9mfIP>8?WF0XL6^E%teA4HT#gpP%u+2_wY7_B1Vqs#8e4bxvZSFi=Tb;7G=PLQS*&7VLj?eB5rVP9sG<9<6VTSN zKgnQso7$XEfMnNzr_Y@QwzaQtnw*Mat6qxr$>u-zS;T^&3se#7h?V8-Ir-z2l;di+ z%x)A+4TzfHO;1>Pa{}G49nIlL2K4D4mzY!yMWab`OlmSY7PT_V0WrfDn$+kI^y)Qz zFf!pJMd&Nf<|LnVg0DJ~uyx=tu*BIWZ8?DWjhP7gTbZ z_r{%>&sX_Za~CU@=R0F*0r>3M8>{x3oB-VJ@X4pQvnNN+0#%jEwZ>#NB`hO~6I!q3+C?3xa9fIiZ&>1)?7Q- z$98TrGy3($!w-5fLc)9d^GELg=#31gImPt-ulRZ-r=ziH&&9Tx0zWLaxX_8qp51vCU10bxS8LgtktRwyg!r5j{C)9 z>KO9vR+FHtNn`6?G@&pAi$+v~bZX|BERf?>+GxCK`70ozwF{G@8^-fcZaEJObW%p{ zettly;0-_)9sZw&Z}7Cd&Tzp_fnI$lecn@p6qP)}rL;Fa z#6_a4+5WN>s4_u5hr1dTPZFT_Z(sxeq{1t%w^*Nyj*bqM+4RYOFI;H&47b=yT#kp4smrSDo5&;qFxF97bCm1_nI zz8XTdR2x`O{PA!H9yS?Jo=wB~Xl`!KZ(xBSBl6gYh(qE^=4DYrqzj{qGhn_CS*7Ck zX@;fGg^|d`57exzEH{b|r0dNN^GR^rV@Mji0U%4$0)OKoHHAV}=3RkFymHoon?t>Z% zfoSIiFun*xvA@wxkPCmPXJor(h_-mZ)PYNxv*28c-ShV3!rLdcM-RJLs3E!V$nc_) z5(fKN{%`7lkP|Eg(0wzgLtk-x=okW&UsH2ITzv#_r{Phzw@%H@1yxnCbrwU`9I6f3 z3Y=Yy0ULvHZP>u1*>P^J^)XEw_ofHmbZ~fw!9iQjA+>?s_Rb&o?2g9ccQN1kcKZ8KRuxqa}UT)t8o{A4}2&&5Y zjxF}zWytH(8gt6w$wVAkaG8iRal?qK^%JEL$w1l{)hxNx!FA~nbT;YZBk0dH zd}WMM0s*X;yf2)q%FipHE1-tilo06? zTba!OZ|C5&S2c0v=A;${m=X7OR*P+(i_X~hS~sVa^}uOIwj`bbs2Nqp=8N$9a7 z5hW@^;nJbK6_9Ocg+z|KO6fn0xd_ztUmrv&*7-W^iOAd#^D;ZIDI^1}M^dN*AY-SO zg#j%2+_Ma+TN`is5c^e0JAS!Z#0>83K%uV>VClakM#sFrYHY>jn{3ZsZIP&nC2*Of z;Nwxc({`?fpN2~S8*t|+)A$)w9>ny?t`9|&uj;l{oS!g01ZKWOj+MMhLr;it!|z*m zM0WW7*~8^qy9#)N|9|BPUXLGnbRr?C?=Iv}kZer0ACYyEi0|3vT$djw_L37hf%S{1 zsNNZ#X>3vd($zX=VKUXSl1-p^ml-N!RDMgVOVfjPy)}dVUOUC_X%Cu8D<0%2jW8qb zbX1xP7emj3UNza%GkL3eTrT4EnnYO5BL(3k?A}EuT^-cd!cZ*R`B?gP=l}0>8Y627 zGnO<8J4@#Gf7Vi^w4c*k^*JNB$L-4U>T>G*;_=;JI+!PpJCi7s9{YCh zH*Q`gDyLV6GM;-twc!%B_|rhhvaoOi)4yecFS@&umCEJ@Y8HG&tCUBlC8hRI2L~{xU68=F;7Vj`={Nhd&|X7$!-+ z*i%V&1d@OJ(@}cK9>q!RbM=f5lT0o}5;?+Eo>JF#FN@rtnB};7Ne^uaJN@GeMLnRC zH5Fawoqz-`LRQ*4V072kE*c6p{D$F@Ht`a z-tS1tbZ|XtL%b0A9^x2~lWp|!J%0N*COT%G91Y$lp= zif6}o4S+3GKs1k&tvO~sfvVkyUfDi!ddz{gR8#23TGKn^VA?S;)afx!tg6Fu{}blg z$WlqZr6y2C1Y_}MdXPs0F8W#8h_s5JCY_jGi^Q^QL<>NQ02_^vi4;zQ0TIlYs)hT5 z?xX8rZ&`0rKh6X4`Z)3oTk)x~`c{c}(rXRa+8=M>+w=z<3yUM-NC0Fs}Jb|+a* znO4FCf)7A7(H4uOEOys6_n0vy-9ptGXZnmCFbB6cJW8oGk7k0^dc|=mJ${9-8~9e# z8JY`W&tymrg)8t3V){OarGa&+uER3t8JM|lZ$qV}jIteB-@@XqY3ufF;rE-yFEj;O zsb(Oaf0x1UhLuNym?|`3uU2-KSWQHFP{h`Wcsgo4fz54LwfGStH!sY~#qAU}A2ALR z4hF}S7eBzk39ubUC@a?kPHN#SXLqQ!o~%P#DYp|3c)yAa$z3<6))>2n;V1X4%wcU z*i_XgqZYQ9^BJ9HARy*`Gqz~^T?VjKl0AkxJL$|D(IoVJPw_z%!DJvGKn3Op^bn}` z00LlcL{=|r_Yb3ifvSh%rN?2+U%Ud-EAeBd6RB(DW(XqsJ%nyriC!E~y=dHfCh>{z zY&qNPuDo6{?2zg6TDXU{u=zePkzTVm^e_8_dJ_ODaowHfx=wMHFU3=l+z4o&wtyT+ zr9+@07+QJ&0NaYLy#vz}X!vE*bsC6uAABt&GD8>vJ^%EHf{P)d3J|ajo_=|#vDDL9G~%2{+-m-S*hBWbXyX$ctG4J3_`tmlrN9 zfAsLY%8r@(q>N*~ciJACJ6pBl1)x}cVBrpH5?d2#qCb}QI`7RGYXDXP$xOta9DX%0 zZ=r#0;1$l9A)-2yg3@n?n)6S}w5_yW_JvF65(8z5)}dT%%KJij%z;w*5SH`-{-cSJ zM9SCy)EqbAQ(7UV^<9Uj-@f)}tPZXHUx?Vd^pMJotWmed?zGF+*H9rki_z-yI z%=}B@?2@t;Z%cj1tceVQMd2>gYPMW@avpNyNl0meg!`3|Yg|M7>2up3dUyy~Wv`Kp zSARRmEAgVNJ*3n?+0sA#in*tx? zl7+VvW-@?SV1~f+qM~w6&zn5G{13)24#%y}mVSmAvzj`U4M21GBb)u?2_`gm0r!W! z_#f$MZiCJbK;8TG2ltmZ$){Wr(U(tfc2)5bBFipRrJX%^(i$y-%`u{XL5gHFaS3If z(!E40Am84s<%ezKrV@Rc$+9FnCF~G8Ci;;P3=Mj?xH41$c(!} zHoe}BUNE6w*7@FznUrEb`7udTK=r3X_@=1;l3`vFe4{Ql$P8VLF-2BaY~JA+PWgPX zFQlx)BH%99?Ocd}9zSih`B;+24t49r8B6-Yl4na1t&)CaXCRG+Q_2i{>1?4B205?d z6zZNJW6hyrA_8uzS2d4n<4=iR$SIEuXkoO&xVbsIAA2=)BHw1)iIv-T;8&gPWIN#l z-GSVUvOIqQe5=KawpcalQJP0(Y9(ThM&3cMS+^H>xAoVj(-S&|y*V~NTQ(pJr{|M6 z>{M=08K@e$Kqrn$p|;L#cLvnUl%to#Z;cj+>FdnFpc#Uuyz^I!b>(GUUyYoTVWe_v zQ}F`K4jdSAdH!N!>LX=Fz=i7hW6eK2xMqSB3IqMt=$p^tA~J2K(%AiKK^rG5$@mX< zd7FY8iv*fW5!D~bsVZg$l8!^oh&nI6{$AZBPj}*;QF#MiHNn=A{vD;MsU~M5-_Dgb z*YxqZ3>Tl&ncs*~&F5V~@43v=!Oqic-N6YP?I(6vz~$>@xV!Sk2l?sFaX0?Cm6 zhFrFtLDPr!f~)z@;n1Wz6=aUgSSJPo~L8frIQ zVl_|byPOqr4)(ua-&q}chgVX~zQrI%PP~B>r_kpdzt_E}?If}r{_gqp5t7yVv}oM< zAy~m$Y}4T0MD{-8jcw9q+ZS5*iSt7;@v}bG-{q+H#%=v&k1xEvy;rF`BIRR-Hfnfz zIee^{yzf1EGT*=2B?m^tde5=JP;>*nX_w|9N4?`P4o}jf4p1verprh=&)A*_HgM__C*m$8UPu8pl=t z`|#E*>yFm<1@@?9O$J7_idPd8e3Cgk>g&)5J9hgr}e)^!`y=%g^MfFsjZqgz$ipjq_#j zIl=)#Y=T$E$TD^BVQpQ#(9V`hH~g)kIq*GKi_F4tm4j*W>Fb_GD-GT3n{O|EHlCfc zPdHJalKiAw?UYNSa!5RVAy>+U9bEpi)AvL~E5sG~!L%Nk!P-8N>H}UAD|Cp!Njd0!! z?*t`)EzCOw-Pbzft5&nTjrf?Bfxj1M&hn)01_>{ELXA+zg?2u_k@NFwXtW5`B(_UD zjVA61KKB1zH^g#%7Y*D-uPLE3d&dH+k=y}Rd>I2UnG3bRp?~+ul&<2;_U)%0j(Xc5l4d8+RBfx@DK~ zZqC#Kx+kgN#{Qo`j)q$LeGHpn?hWthOoJy@7TXX_g-g`!7gZ=jhT+He-< zUB?FYkDqZ@WJcXoVA5pMq)E?-7p9`ynuVGd#KE-(BhYe%=~6~AKOW=Hwn2()`vO_E zdSGL!=u$-TuysdGk`U4?c(Om@;qAb~E2|8Zv-7)(&obC$Hgb2ERI-s5E&*-a5Y8Cc zg@7DNRN7$QeFnu%9G28&`3!2@{1S@p-DfBOAFOuZfQDrH8gNa2pI|d}jNfK*7u!k^ z&)ruJTHr%Tf%fWCF<%&In;}IFhV6p6M?swDx9YO&wGlP~cHpA0qQick5fAHIK1s_* zsv=B0|GWr^wiV_l7xDbW_D;I*cw5+L`U{2LYR^xxWV{?&*qd~13iraE=AS1D)ZEZ; zb+w!34l$M)1NZ5mL7wiHk!(nIPXMp=_c5h|dM0@pbiO%c-EOpOIFr-Q^Ug8x$g@6p zqE82dUHhFigO9@t7MVWfT6eHR%e+S$m8X^JV!c~T4nQ6QC|&- zluSaeE$^z)uInBlAu$!_mLask5wBUChKq;;l%^xrZJn9hSEU@26&;h#SIXrS7^b|3 zt1|2-ifFtV74i~2GWhnqj~avMzAMfQ=pHT(`5zjO>GoRIm@u@jWR$H&EwE|VK}9ys zKoCB2YDAhmHPpH(5?HmfW#)IdS(!_S;u^afsqF(!#Jzb#T&MHEN{>3|`P_L1%8z5e z>>}q)!=QH)mx#KmyiP%Q!{~xd$i&A_Lxjhl%S#?Q@K(gS9-+iQTmyt>t~f(ZsM$d7 zLzql*(v;m{#5X>@G+;6BNr$~l7q+myH>}%9*H@Vh)OTJ`m9#^I&+m+17^SXRm*mQEu2)is7DVc(%rRMOF4BQ)wQn85!I2;)s8-T==I<5sVSueG*D2Aei#-&|+#An!+2tQZFvSWt3SQvea6Nu+p*-y6Z(O0uXLV9XmrSb~%{_xMn2zQff`F?0!uOvvoUrbX3z*Nu z7buY}5DuFYmCNrgiqniu0Q+uYpfft0wh`vN%L11nnljuqFn+J;E^v-!cTcrJf_?%C z30w313cvps-i?SYrTZ_B5JjG;oPYy0tlLk~r!n)DOZTt_CG(zzeQRgUJwM@hnwD=j zN%>a`(Bik~pfGt=((rol@tYOO(+o-G)axv#s-c>Ua|~Dz%f}46`{jqx*X+{2ebxV6 z04Ld3$`q$W=SBpl2b|Kz!bCkIf-cChqb^(WC>hKL)w-Tb%1NPO@e{sw*&rgSK>X0- zZeC7zGvU&dq9y>EWg@$2Dk+!a+*HD#_ayQUlu}+@QZKb|6Ut$M*(VQA5;gSA^%Vkvm3*fS|mv{DUf z%n!{?Edt^-|JDYg%c-|xi*-(vv ze|(IDL^x_Bo(%6DK8OP1Xu8~Wo}uiHGX2|%dB5c|N4fOD`oLbz1(pcQ{yP!UsrTv6 zvta~SzRScD*Kb3|`6#s9nq9dSII()f(2n)Z8t0JZ&oZ>u{dypSgntK^%dO#O)C#7e zhhbZswk!$j%=bKEw=o|?oM@nr!9b%1dx8}aNfMp=G8|k3X*15YYrZHgXtwl?0qKpz zqx*6^o%dqSr7GOYP)sX7H5oYvmb%@*b|*M})APyoPs{PcEQ`=)&!|G$g_*lA<(BgZ z>>LJWTIgI%gP1>yW9rAu3u(vVt)>LUAQx!6E`-yuXT=*+ctMeS4xX-VtfRHAZ&m<| z@$Vp>Czlp+1cdG@J_yJ)AJIduFG=8dEWAKf=%{t`TCCdeyKC|f{weOlGmu)znmFfq zM%{Sk?)mG5%smUe4L3K$Kv4sImk?3Y#kur;lDWVLD@1zYDc9&l(hc9Gl_n7Qj`(b>7NmG!&n z^%tnffZrHnb#m0Y@Psx>XoJnK1^MZ~yyl(IIOchWp?sAjoGjQ&*<&+c1 zZlp;&Co``^oJsCHRuz88fRM=?Gt;6I{u0E-D$?0Cx zKsN;jIdvdB!l!YTJS2DGx)GYkRfg~GD?712y(%r2OIInbcI%)qS1Bs+idCfg1XI#3 z74M(PE!$rI?xE!fC7(+}O_uuf2uZbeszgb-WlODOCO~p4Wv_{wz}Vu!BUadd0Xa|G z&2OeFCeeNLXfMif_q<-$6(H} zN=LiN$X(NbQW5*#>?t1?TuC3$8W4BLKhNN|y=dWd9j{o*p}${~Ygd#TSxisCI5Xc= zyCVrDCsUMhjDo_9lJ3^Qo^`P`hD$pgC^=ZYn*iSV=RxOsr4W#mn+pF^-q>JU$dP#J z(W)G!z9}!mZd-Dgl@eQw=v8mja{`_G{-QanKXxi7ck-HgnQG#4UAm97=BXVfr~W^0 z%0~i#wsodc?d@!uB7p9QEw953k7OzX4%ICc#-YsH`t&m@3Uk)kZqa7GSK zP<>t?!Qlzw!#Hxj%YPZ`JUe>E%R{CW!bhrrpGwW@s2Eugs#agXX zWX*|AYSA+KuJCt$hV1>YT3hGjy8~*3aN3zxj(xyIe#4^-U86}LyE8aDKeq#<OT%u=J^1_lapi)A_(?`DJ$+$lN?*Relq-)!6o59wxo4)w$pVa^ul)lnt{xx` zr~U?N#L2a1DEw`8~@|psl7NDFD5*Ri4PtITh0z{GQUBjYn@=Ih@A! zg>~yfblBx@fB``GCYhw_M<2+i3*%jsv<*T6-@7R3%7>tmuo2DoN)>cvap45n?Kg>lx! z=1sScv|tERa%ueEJ5Sq1PBG*X^nCUnoJ+;LQ(C#sbdn4_K%04CiGj39fj(eVadZJV ze3*F=`}KpRzNxCLQ}dUwOV9MIJB}C0ngN)&A|tY0J`z5*hw5M{YR4x;7*$(PWiph+ThbA49kn3&O$@S zQO4;0vokp^AkAG__;eniFlAgnK$!|RNK$4U8XW9c1t%-EQxi^O#qi#(sJBq1~G#KZG_ zT%bbTBPJYU&40eCmu^7&22KQ#;-N?btfJUXAot9E`D}duWWnDy1}mjv*%3fPM&WyB zqlvaI3cBt(fK>tSw5xm9bVz{>XHAMvIt^9;jvlG01k!P04}Mc&Q-&x1yqrr8$h>Pa z1IzJ&ji7Quu$Uw-f3YIYwEAVo_U8*4PFaUw3bOFV?bht~J8q{MSlVp0tHnSZX4xSUIpt9DgKL*(HCYYd1o%%cYq8TURPyq%lrK-K6tMTVtxK|^}{%-=70X9myjOfza0Ju#HOLbVs4XCzdzp8 ztsz!(LvNLY7n5GU9|U8CJCC*nI!zw}JZj8CnvfkladiP1j~ zheTRH8zurU!{ppa$QIbCT-71J;Qwo?ZecYE2mUp&vaMsj9`FHaM{v3>T7W%C_5XE0 zpt82g1_PG7u*1WWZ|Kp-9lgv=icj;1EfSDzA1Y4$B8(6enxLfeeeb_;*qFHeJ=I%7 z);FNTNhhGtJ|0V3P*_#_KhJ?5RgB=zq*RjG|E}J$+&$>s&`FtSYg?Xf`QpcVY>xn4 zb+U)O4{;N>;2q9U)xCkS@StH{+NoQcQ+hdc?=%^x8FZe!S*6#h8KVCfo|Be*dSfVC z&APo9gq%#y1p3d_M>Up$tV>4wLj4?pfLF1(Z-el0HzGv0T|Kz+axPz_DyN0t>=^0E z!J8-GvevI|8z5TU%gQ3QAqtLe?1{54p}-Csw9Mx>;>4tMwzBHR(>fYz2I^P+60rY# zwfv?#9AWk3iJ#&$6mXe=<%=qGqNm>juZ!h85r~DJS%2}^659QnZ6#8<9!G~+>IdIC zx@^O4XSB7*w_oJz)+B#j)b`rxUfnX0&O7<_wC6!|X~8)F^wCrB|I6CK%t=k0raO|< zZd%+Ld;ak(PI4wJZ>cR_)rkcqydIJFb8$CDHJLLCqguez33rl+yZG|v!3!rvhu=nlfPbp0JB;0V<+}Sv8 z6oi4pq94DNUlQuGAiiF5hD@2uJ8XEZ>_eP0#W#c^A|hh2+*Msgtv0uWD6-_adN(PA zF7sd1q4$olI?FHOD=(ukiRXwvJQ>`1-40d6DW+-8Cl83VR$Exb<*!bD1sr)h%ezWh zskz!jlXm2+Agrb?^{I5_lRL%yp9TwJK7Rh(IzZ_c*F1|~QuiZU03L!$nb^_O(9v;o zmw!U|K+DP@Xn9H)c8=-NM7EmvTHa7zYcu?eRu zv`BzeHH=rZ(L9;s`lreK{=M) z7s%a~p95x-y4SHlF}I_{vuvS0q6h$0u!0Rxy_d`T1he3v*reVk*yEojkxbiR`tMW*cmi`Wh3TuAbi_F~PmA@ae>5bv(^F`J z1K-GxHw*zaEAe{3BfBBortI>1%tH`hb%ahOu|U7IIPw_N*uQ!FNUx$%lGtS3;HnW= z3@9}O@-`_57lGh!Q!DeP3E?XI{)b$I+?}Li+k&kWLBB>|kYv?G`q4 zO9^$LUWwM6%$`5wbNXJ6T=~vZkc$GO`SYNn^{FY*|NzkSt@F?3Hy) zW18$l-x)Ohzw7$G!`1a%m*+X%=RWtjm*4N6d3s>sQzAxnv-QVNquM0Wg4OSTR?D?fZ}oXQI%ASi}X$gE}nurv6o1LA$2_ zJ9s}Lu0H5yZOd}vsNC^^Fq#=_DBQRuPFP*9SF~PeOs@JIii}HGYGm9bta+`1ZyqeS zOz$RM)#7wCC61DqvvU4!4)o>MyA^#M-X?Axn57TRRA#DTQ^FXomvy;M-b;Ue3J96W!tmYW zmM&-VQhNPeJrN>9SZ7%AW2Pumn=|j7)E^jg>f$)! z8?Ae_m+&lQ^p+csbtCT$Puz@D{NQEZoXJ4Wj@PQSD7iant|ZoWCBNR#o!c^o;sEVe z*{lquZNk3xu@56Y4?c{$Mw|5WzYxZj2kMJmy;HOESU z1ma=mBTCZUnk*Grugv)`TW!-Z9e1*am?8UUma8)AQvmzKUbrQiG$)?$svb{(Aja3~ z3H91batU_*jn26;HHzhTu2zdIELw(jNg27ZeJ@RZOG#*X@->iMSK5}>;e2QR&@oyx zJvvmOC94_m?^zSaoQ>~DM<%U}hr0ZLHbEP1#qqP2-R-QzVuqeS1>3P^rR=C;A1j@H zXM}WV)jhS7Zu>`7l%Qcur@@@(fMHRA6m46=m#WOWa@-To_>Iqvn7*7a?k|zT$HV5$ zD~7Et3qn35x>ju#UEge9uC8Aqx(J5$zbrfa=GwRwz;D>4vhw3q+&Mj%p4bcvSH$)< za=Ni%C~?A5je6Jqiv5z!I0aetQFacJ^u78{vf^D_>wjh+r>$6swLG&!lOuJ<;eU?b9-=R#v2a zLpGbiS?*o-EDbr#!;UD#yG0MKrH6GL`eIF6^26IR4i?;meD%Vufuse{YY{AF$%D_K zRt~T2cpYU*~D?ZX!ZVt1lpTtOCp)#bk88GxV0$fCwQfn3pt5aJH;%a+d! zlyAsY=@_@_b1Kw#^llDjH63mtnH_C618_eFA=>UV*|3t6rK+*k9wb06Tx7+87h0gW z2wPygl_HKE@~$>B;n%EfvaAk=WocD?exdwfzXP{S$X*4uf2M@29WWWE2NlUbR_;hB zL~KLEw~9c~#cUk+Fx6kkMdu2JDUDFcf%BL&|E<d#uJ~EtK$nj^ElK!otdG^CO%HqITdhJ0_vL52EY$!QI(0zQuMm~| z@QVfcl?RcRl9v;wp%c2F+9Qe?C3P;x%`fI^^!au6bM;BDXDDLpTQZM9&q|&y1%#|mjg+t*l#8{jFs$pK zuBk{06;K1iIFicgf(+66xKspk)1gH-pti)S(8APT7409@Kju30$)6;O_gUER6qyXB z6k#vV!J6P|f5KC~*x4FF#AlcL!B4pYj#uh|`00)t2WV)>Q**w_muHA%=PKJVpHR#g z?--|kVD{iqzN?kAjKnzMhuB6W=J)ce##8X*Y0;HXt!p|_Ex7F(^rEhYe)-s$adomM zzQ7$?Q=o;t+r2i5_TJZbi00g*KuA!o5t9(~?TpN-AY`kdQS3_ttJSlpxpYK{bU}46 zihL5D**@=5hQ*|ba^n*u*$u2qm0J5U|Ai9eWBkS+i$diySJc97_Di==iMgHe#k$h* zms(<1v1|h+DnbFw04f|yqr?!w0{3V_n5oA18Z<;t9dsZ#x!^nzU5KR&WY_SU8wH>` zjrAI}=50{%55B*G+OPrj^;MMvHzSZc9Sk6qV(E~bKdQw>Z)trL8qKp@HN?Aw9RcpG2{W}GMBbSsMs zgX+*;2L^I;e{<~#o?C9#iWMTTeN}FF4l+CzIER)?H^}1$Q{ldnE)&O~`UN09`aM#G z_T}iO5<;{bu?xPIn>%$EIfXfd(!=FFmg23R0@`8rX&ipJpN3!vRkpwjFtbnQeN=kP zs|b<90e-=QIpxFUA;vxa+V+63c^Wf(QW9(u=cv!}i%lZa%&_%u0SQe*RQk&Ca36fO z^!5z;=l+3*e^n8^1FpEA!?B4gea<`%?UpI4u;%IWT-a~|Hp2nWG$ex9>rZe*tn^T8 zNiB!-a8oRj8?b4X>yNJb(C{FG7MZ$6enBO(Jn@4l`!_>=b9P$hkTGhttvo9z&DMWk zC!kV8P(l+?H$NRvQ|BISAEa#Gx9@-Q#ujS+p3+FhMP6I>H|p`P(&7=}Wy;oiWoO&%9k`zN^`1vsISUU@X@DuFRjTz&s1J7wDTw~n7-K}>vorp1OwFXA_ zl}a=?Ky`DO+&^cN=}~#iP+ViF?&cdoo<20}*3|i@Qnz!Jha!H4H7sErTO>2nOj^#| z-tYQr&)E7yyNg#-7>~_yCDtb1kQbf1atV~KsW5yhq0_FpixJvwECPUD6|RP{p8?45 z3U9^I6r|f$$82SymY(}?yRM!WiH9)lMY`DMi*RV~uU2=dqcW7i)}dasv)>_0YYxiHd*W<4d<=D_?X`0Hcqv7V?fRM zl^-|)53(P~XO*1@D&PK@g8lW8M9YxQ_l`J-gFci8n8nH95KjQHGD7<_+as=fbk9rA z)bfqb((~Q=F01T#{u2nO&*i*lcBb;12wu&vE~h|tr7=(i;Korc{Q$GP!zg=W2dnDn zxTGZpCPHi6z;-hF(mnxBTF7HGAGSH*g%UQswh1lmSPrQLF3a|X1+PK|6ET-sW%MBF zp3&31UF##ioAH=yQkcH5F3IGNGsER3d4~`xU!O_>4kZr_+4nzKOe_HqoQN(-LMpZV zKrhDd0=S6j$?}a9-}dQeiok~*L>;;6Op7BfJ)pr+C^3Xh62%Emroh?l;vacI+j3;3 z--P&r{QEGtn?TF=T?_!W?Hz2H8%|=)VuNQ=;Nq{8!d0U*hgZX2g=CnKeL&`Aa2}}k zx%9;(I=ZuOsP72aQBdglfiYKet-E?qYk)_CC%dZyRdWw5q+#!rBL*`4q#Ry=mwDD9 zV*|feWySh-n$7C*>0I`YCfEugtAefDCLz6U;VagfnJRI@OI3ynnc+fHepc82?&1v2 zl;=}qY42BMN2I1-a|nqm7?yi!1V4vBFWz=_;PYdGwx-HGY?HA{zIb@G@NY1AysSp5 zMudC=FdBfd5275oL9=OW&6#u}1MsBsb62J%hnu`BkB#bMPRTI@2f2Kuq(!-vOSPsk zULGupr#OT$k8B(N)hMjXCr!81ZTJQSUCzu6k|1BxPE6l7XZ?dHeu0t0!%yzBK=KuT zjv6x4yX2fOBx!7p#rVchi&c|e`>F2M+ThnDeJY{6GtjNYPF24Xh?2-tyN>2)Z=b8M zZd4s11~>$8=)KMc3!ipgsHyw@|}Ww_3dZWo^$8K?a!@Tkab2 z4%sqC364UnI<%x(f>CN}Nl)u5Nf$&Ho#%)fx5SK|U?7vMN|)xY^!2tWFHnviOB93~ zhZzQOV|zXn^tYxH3>Zi{G_^Z_{TW7b);jx!FlFn$gg=bRGbo5y)`S9A|IJ(pc#yuK zdxsu<4V$ktb`tpT^LqIB?}Fpw@fq!g$4`IC6`=Mw?u;g>-igv^-mS_;tJy=SoO7V( z!4f)XIpNy9h7ap9(jGZnbk{8_Oq=C=?$0&j4Nvy<)MHueH=-IOI*MVzGy~0z1RTUS z9G)k*R)NHM6smtYAbZfQSskA?JLOcgsW?b>l?-O` zC`_H$Y&#atLBsaxPR~aU>+=>v`gkKB;rrLDL4PFpvb+VTd@^M*tP6rO3#+)~AwIL& zF6IasZhd!p`Ib|o%6*f$G9&+>R{7kgpOW|!^PY};7*m=ZT6;hn`iiFb$fon z{XdA1t_Tl`$2sd7V3xzW42z7*MHAr_7;(@LXR$x~@5})ALNFj*`KFj|A zEPn`@jUMXm&-a_E}|aAG@q-hDu&`K2&sE| z{Rs4<-ICM@e$N`wo>ofJ@s8sufQc`~2Nt0hY?&iG&Li zwcmR{a74y{w9y~nMeG@Y+J#h@5%`}q$G^9`_=Y8GZr6)pI5Q;p`-LUJ}sMU3_rh|Ve#U`m_*D6J7 zmJ?-R<(@C^vKpwli4-JrjSV7~s}G@$gi1~N+V5354r%|HeE==9UuvECqg1VMeA?)9Ad4bt0eKuX>@86fa><{EZ{II!ob#*>#ZZuu6qJck= zk|uCy#bdGuFTgVkv_Vv7JWvb6ao03Hb*Zuk-qL}arjKJMyVtOF@Ioz49Szb3dhwY` z;9$2D9?2&<^tm)KkVoan6zS9kBxk-%_*;1H!40%y&L@}yXd?K z!t)zgp3a8X6%rX7r2>)o&+K7gX_uTYy4DIOFCPHA(|PdkY8_VCYv1Jrj#d~i^f_oP zCoz!j1JO=uVG+V?`kTPM59<2$&2WOY>zxsPD}%E77$XmZHuAfe9z^9mJ9UIfVPhYP zT$0EeEM6bohy$oMD5`b;f*GtY6-cv4g13L4e9ARfRgg%ECNICA+IRrNGNfD7Wv}3Y zHTE%ntR4r`;*i^Z(&n5FsfHgt?xljW%~g5rtNb%My@aF2I8y_;l3xaAxT-0a7y~n(xt26N=5kc5OR58r@#D_B{7KRYJt3zs*8o-AGPC1#Nqb~m;A)9mn zA$S>LNi0zf1Wg<0MdNpr;PJH}&HIwhvMKYAe|KVn#-(qUFy&f&&qPb^ABg&s`_ozB z`dmTV8NGvcD}KH3VVBX7?k58x&Z`NB4g)s9E;j%<2rpS4I}kx{EdA#|(QUUo;Ey0O z7rA^uNErpCZ5Sqcsw3Xp45czGn9?__PTZPK>NwoL|9_siDLP0ldBH0h;TYrz)a#tb z$1YA_e0`)8FvZVZ5 z_QRL)`KzU=cL5A$3`%5qg}Gx*_eQtU78Vu;y(+CuOCIl?NnIweR3eO+)iDj%9}5*r zhQoT0FSV{+dot6BJPkkg#aiT6l`hDx{meK2NvibOv->_3K&VIPpu~b@GFS8uqv)^t z&|DSzqQZ^M0?fxTxc??}0;Dc<4{131)wduo=h0#sLYKH(PBSXc?mHnu+qk1u6)lH( zD%+O^+0&Pb(Tj9{sSi4JDxvM=leUy|ua$`r$`tyAmSq@J7?*FUl_ZIYl3~O;dLWAg zO`)mJM7e^ka1(&9M^f|Q*#ch&nHl^KTa8S}jda^e>ki$?t)Off{ue!qpc_8*Lurqq z_Ew;<{oqB~{1SoyF_80Scg_u#bshAl&atqK!#hpH+ZVl^P6!))KjOXm@Nf>pC#lz@ zvf(V(ILh!j^7h#@=b}Z18(kB(o}0g{Y}#$zqpDBh5cu#yx1}et@j~~;N#$AP|Ed@_ z;*E8m->Hz%kjF9y-;6F>&?%S9u~yLGX@iBHG|{+=X`Uin zF`?q1X1qvF`vZi93XU`=TPMTwRBBgJeYSr;?1J>Uvh{Fm-~4o-FIDlca$YyX*bL3C zX}&Dv#KrHl&gk~F|IlxVH@Pa%V)f4?t6SfsisA#M0Yhdt6`p2-iPw-Nc19l>EUOX+#K?R z@;Su=Hfz62W&Yl340^4!wQCC5QJUviR;SzXnIOES0?hl~XP3ZiqA)i;Ybqmzwh{}B7 z3LeFzFh26po3*s!gy*_QjyJ8_VL3^Od;{PP`~`23;#DJ*0hlC?mf@jYYhU~N~JD+q`ErDQ^1>wvCAj1G&T(D>};AzHq|0Y{C_IB?cDYT%pqBq{K#CX|IYe+pF(> z{a#rR*C=@zcVLa&DK^IVRH&K$bi!O%+8f1l>Zc=}UOqC>q>C-8M}J!I6&B|UewQks z6BBtpHu5lwlj*ZH{-WN4`6#ynX%|7Je*QjwVW!)*JZZ1czSU!Lins4rIy!)#nQ`QL z5F&SM2(lVNMk%7mquz9AiD*upc=cvowIEMlIZgp6Q|y57p(@BeYmfLR0k&084dL0L z>l$fByPi25TEVYy>SR{@g^3I~#OfK;lMR`aeOqav9xIsl7cboZEV$EY6#9;RII%I) zFz8awz5lAxJOrUkpDJq;7Jd22vf_^Y47U{Yl)bfgDp54^@p0x=wPq%xsGJ&?#^-Za zDm=W`UwM{>k*&MfUZF$MpvE8^cI7f;<@gP2c=q*%U*^oDU)rYF8} z`1#B8TQCn+jKicwjm&lmVke#mB#}omOiWF_t+Y|Q9rw@g=^>|F3N>hA z6{W8cH=)sdLtWL+&8jOuDJLAw!Mj5O7-&a59v`ZIX7GYH?6&aUQY)Al4czyx`@yx< z-t|&)Zr|{Ro$j^ff{6SDdBlV%obT%HnvX?1@yl5xo~BSD?!8R@hKCFU+4drD_s5>y zO}^1LnaJ9+XRl9N5?{3$awsTb)8Cg6t z>?(b~a!y1d%CL7gbrH=Tyje~4w7V1FRR`!B)2VL`bm}uN}@4ptJ_qg6o zPK{u?*4%!<(=|6u$r8+MvX^N-HtKRNIlnr?41OmXSBx*1nQ2yL+rE{!u_v0FuUxlU z99g}2@~)ubV%x$}HxT^QE7&Qj3y|nPPP!g_BQky}g3Wj8U%C4t)+4UJewF>I4Y3bX z&fBfPACEsz$F-k}XHsjnClV=3jnhHF4W5u|Kk4z}t?hMLZKlg|+{bwKHssV958eA5 zY|%vTW`afBM5oy7frQ1oIvukahP;g|g1LjOlRw5!`@e2_BXQ#Uu3f|=XY`HszTux; z^U|iQ4V!)6?2RRmy+5uSRYqjxUJz7=b;`w+)H7F$>E$hFUs5&SI}Hg^bs0*`av>K= zi`FDLPp)2TPM@q~xeZ=2L+QzsvNli?P}mdd^+E`@btRNzHILa(Bksa)Y;%xk&KmCR z7(rNlD(v;%LAc~bj{LPzwn#~dcvJs2#yO7J`-yK}%Qj!w&pilJ0@sTF#*kohEwR)t zuZ`04-K()7zU=nJdwY9j?v3rhPibewMzHJA=e8wGs_?dyfI0Fu5|4LuC+^@lO>G@X zYZh^DT!{}7xNVA(Cx0})Une!_9}ZLAQwOFld6DJhh-okSH_W-#*nbr3st5{!Om-p)GBh~ZA>Kp$Y@EBtK9pEW#wN1nZCNV}m^H%)t$CtOW z>9MS2({oe<3q_=*Wn}zn?(a9I5BzM!deUP);GzI-eQ|cO6A3walHug@T_baHnC(KH zT_H~>-GCn#2m^2SXbD~&!{a_5Pm`lg1U_G}OGx%`{kb^#|G!9}WbfX6Eb5uz`-$lc zYj$tK#BxZ9UuP`2*ss&XYk=*RxK8=^Tc{Ta?yyah(#rJe8<`I4#0Kop8xwM1wd*z( z7wui4v%Bz~Y+t?}Sr-}BF;`u2K7>4qnLJ(Tv1}nr)+xkKly=+pn2Q~u3K{xNI;~0E z#t>_s?4S>i;oj48{6KmJN0LWNbpYvoh`6D4>GsgCjn)a-0BhN}35LCW6nGGjNO`YF z8IOxy&DCAa8Q6~=@-m8Dv2d!gzLxiaEVDNmCrs$1%yz>K>;tLiA;4Uv>PJw(Pbwj}!4t`V)?R}?eS_u`)U&)iCZdy>@*!jY8>yF9q8JG)?6E5#k>8fq@mxy7j{uKi?~~5cU=}+FkZR{ z|A?Mu*Vy&0p$H=W(K=eMlgVQIj$I88^>+Y;>#)7Bu`}ua{ZG^nPDSEZ=B_7nbJRa*sb5zsQMvu_{{X&f By;J}I literal 0 HcmV?d00001 diff --git a/DOCS/html/group__stm32f407xx.html b/DOCS/html/group__stm32f407xx.html deleted file mode 100644 index c8c3511..0000000 --- a/DOCS/html/group__stm32f407xx.html +++ /dev/null @@ -1,113 +0,0 @@ - - - - - - - -STM MATLAB Simulator: Stm32f407xx - - - - - - - - - - - -
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    Detailed Description

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    -Generated by doxygen 1.10.0 -
    - - diff --git a/DOCS/html/group__stm32f407xx.map b/DOCS/html/group__stm32f407xx.map deleted file mode 100644 index e65d6d2..0000000 --- a/DOCS/html/group__stm32f407xx.map +++ /dev/null @@ -1,8 +0,0 @@ - - - - - - - - diff --git a/DOCS/html/group__stm32f407xx.md5 b/DOCS/html/group__stm32f407xx.md5 deleted file mode 100644 index 847820b..0000000 --- a/DOCS/html/group__stm32f407xx.md5 +++ /dev/null @@ -1 +0,0 @@ -24b3fb462bffc2941fb62d66e3a91c32 \ No newline at end of file diff --git a/DOCS/html/group__stm32f407xx.png b/DOCS/html/group__stm32f407xx.png deleted file mode 100644 index 33d8bb94d5169b6fc99cfd2a81052d41511a26d4..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 6911 zcmZvh2UJsAvw#yoAQUkmDkY#8K$_A)Kva|x5Re|ap@?*l-a&GeCTf7t!7Cjpp?Am) z3QCJY=n$d^D4_{L=)9x%f9tLH)?3L+&N^q8nLV>-&wMBTzJWG73oi=@1Y$?%+%*P) z!1KWMDl;SSo5TV;1pXKu^tA7SPJVx0ca)@nK)m&cySGh)b5>`=NO0!}%1`eOzqJ17 zf<(xhepS1ds%)jVdYa=Yyv&mE4)PGEcvFiHJcsXHVufnx%4Y!X|+5w z&t5_9Xg*}QB^r*v{O9XxE?h(ZvJiRh+_@po1}kDB>{)T|*RNkiwOhPGCS!DrP3o;G zn?wF(q zxVP-)`i+HGqYL)GkQHH9V*63L#vk{sKUsFs0`*H8+L>(S+|*(n#EhfJVd9(?WMyg~ zhjWdyB!Zidrq}s>yJN{v{GU{#wNmHQ07IGlYtypWLLQTJmzg8t^g#;B_G`rxK&Kwl zfb>P>;ns(aeanhoeJ)mvZDqn@CH1dHWH@~-A@YGjSB;~_T58q{*ct(4qfxeRLx?;j znG0?(OI8_w#RGFb(5ymf_Jez8%u}jwv@q(eOI42DQCddF}0x5%n6U zOWtnJ^>gzAeGilx;0kzo|Mzav);$;!C}7P22B$_{%sLa52CNO~jK1Cj{X``ZKoCU2 zfRiM`*eTFN&zOGOz%a{nGPX}pu}OtU5VA~+_}21p>bLb!A}yaj;0Dibw&&B@+xb+! zwG{tYDaOLVYvcSWfRem$Pa=73y?f^e%q(xTqBY=~XG`)hA$QDNWfzDUVa7W%Nuo?L+1x9?ttBLjIGl7MyVnA1n?DG@` z?Uul-l(mb1)j6f7URR)ONqxO8fF3^1r-Q}AHb}467Ste}9~AUm01G_jY1H=3qa|YV z1HyA6GMHfbi|?{~yxb5Np*p~J3UXx;(X;l=oxnnv%BAF-uL!Npw)%fO?|QV}@V&N^ zYS3EvqUL#9 z|6Ydf6gVQn4itVim_L|dSK)yrDGrXvf>L9s(e(I0iYNYy(Pa$Wl@X4Aj~~3nH$i6; z^I`{R(VT`ZY~y|e#r%B#r-4=ln9Lr|H^F4XnsZh`2!VO{j+fGb4~ntHd(+Kv{d)(B zZ(~O6%1~nQas^s&#Bh={1lUmV2w+3$v?78VQ4Q}7ni{a^n)Mnc-@C)mSToB1;md4WwW_br@Ypc@A9`|Cv#Uosp~H-DGn z%}o63<|%$b1ztdp4>IT<2t&G)^U6wI%78e@*C{L%C+O&c9Il(YC+e`L0JZ=N zf_6aZbV^#!b;_Z@UK3fBr zlo|>VyC@C4-7A#ys!@@EJ&d1E%3@86*H0Z|aLKN|Bc3+Yh*44QmIo!M$({<`x3>7kx_D~!e)G)nz$1WD* zpI4hD;yq9hDdJpyhphwfdMyR*i4R}AG-$s<@N`2wSQa@RJ>K^p@#i7*b?PiR`V-6d z@4yk8zuul4)#o3rv%7s}SHU)QR`_l8ars$wXnq~o&*^!7Nd(vlLgt`#x-|xK@HM7L z$b_I=Y4LY;6By~Q-0gt|+SKjwZ9xg+Ihf<ed6xgIUbsleO^US0L=%3UW%?~7~uI{6@NB@#?M1ZPAl2Yw%KjJwFnDHr`bm&KB zc|LXQANpcaMc)ZUmf^-G92u|qgO{&qZmfJ&|83_colfrP1Dy%t?yo0q@cY}2CD>TLH3%pgO%F0F zR|_b4pA~3tNy`ZIxX%-^?tOnoCNrt%p|$oS?j}gTMc`lnxed1KgKn0;WiBN481^#r zWi6-OREXwRM4~e?GlcU9M|_Cn(Oj!G&_g{TCKZWTpFTW=!^Cp=j>}Tg@MdO=MIO#8 zH`FR}YL_!e3TCO?1&6-C@+^i5`kb4*VFTG{!$Z>U7EZl&7?reG6d!VuR2X3-)KSz< zo?6gHX=RWLza-P!b$CuUIyx}PLb?^r9_hkHdR%&pxA@-=%NO51eFn3xPFasJgf0pQ zW(4~W{tPEP+A>kOX}ET%#`1tVR>|?6wUXCNO{sFaZn9ODM{jWJ8Nb?d2%+?c;+MH! zP0?Lob@oFTu4@_OzKA3Qz7(Y$s&OMnu6MFFpKs3IV2hO4NYlI8@{JZfZpQ7D8OF@P zYos>R`Azu)tP(KFC z3x#J#RBG_X!?P?lb9*5i8@c6l{Labr7nQp9 zn&F6{L}*eUaISl|?M%6MajPa9*#wN5Rlk7UfzA4l=%-g$H7pbD55Jy|+H0OqKJZ#v zb)io;C?9HRY4P@&s{gUWUm}8kLD!`pe6Ed6*>PYQn1u)bC3l_!%IWDn+`$?gJP@jl z9UZi3!XmM*EiXi_!+AszkL@t<{5WWm?zSUd)R9Ss<>a`iZG*rnQC&CcHVd**{8pdN zWxlJDj_b1sLemnN5h~Q_FrE!TNaZmKK{KGJXuPFeePCGAmf7x#Fdca;s4t7l4jn1h zH|zPEQ%X|u-D#A^*49>qZJT1?1v$VeJXfX~B&exe(Q_B;22^9X zgJVMVb7>JT5TyI4K9nVhL{#O2U0N@gl8KJ7>C)6`wHHo0#*(_7BwaHW@Y&J!qV13WOrcy!Ds84zgwWEWv@-g_F@)7!9^zVurK@*$qJ01dVL<{QUg7M%)^z zUcjC`jQxl-7BJ+@qeZ4kmo!nO38mjnAeRfrxj47$RC@ElYA-@7Sj=@?A_MZSj}1@g z>i2YyF-XWIux?E7^N91i;Y-4U8~#cD^%u6jKF?%=t9B3ttNgi>r7y{<82&8CYa$|6|>I?xgX@xg>?| zKgT7l|tCh_#tXx`xUZ zJIj}jB6k!*(qkUeOc2YColq{eIVMJ^V5esvAk6>NtpKK$pZ;arhE=qoSxt+5+f{%4( zFd{9FzGcl7RGs`*7WK)Gs^+`o>3bfwCsn4di|BEkt?lM?G|>`Uim##N7_GafidmoX zJQW#_GuQ~hQz0MsuJ9vn+_$tPvgf^lm(dk9B=rlZr713lB3popqWWZC?J_|d_T@%t z5`^QfJGd#(Zk@sIP6qjxJyQ3>^Grv!XQwI45nba~Akvj96-HC8+sP)q(j7F?9NmzL zNSWQ~k2V&z0i)Cu_#XP?QMNk@6%*KY@ueu1&x+9VwJ>>&I-uXS|U3A4ClIQ?l=#=2A$U^ z3Q<+AT+TT;yFna%CZ^DTPuP*G%5Ln8=xc`Zw_J692aUQ@ySFKHgqiKY zC4~W#+^r$_%4reT=*;C}tUQ*;nFsAUw+o|$eI&mPzU~9rC_ujpzlrKRh{(;S(b)^H z#7hp!|IQJu@Y{HMdT(%K?kC&a#z*()+S!6rr76_HAtGzE{Y8&i$i^AHk1YpV{b=a% z@VyHeNx3c+83K{JsKC{PTKPtmowY#^ocisFT`D|#<+%4e%UIo8kl^4>7=HlL>n}J8_=B_MCQ3Hkmls&wU%Auc)_e~ zwi87Z=<=>xnXGf!PKK$DsnJ@9v!gst3Q!=jHE~>b7DZ)_YEtO&RHT*Nwl(^0<qN z$(rHtnPNnM^=DBTHH5b){KqptGS*ZzWj0i27;dYLlv(A&d*ahos-qYLUYs52XC|g} zz4(+C;fh!o0&htQe_x~C#kRI}{WHAv{UCZ;H45tnL|uh(af%=_1gH7^oZaWWEk#Nq z`dfSEr^oyx-CT4cq%HQy_f)`kQ=uWFfpwGDZ1NWI=E*5;(lzeKg9_vPm@pV#SYbSp z@Mu8_FT>ydxi^uSh`J`46dcL2D@tJnX07%o=cA9SmJp%1t$hz-*hdMwp9v>*UbC&| z+n3F%%cak{;#Q}d{Q9Mu3I%|ZW^e~ac^0k8jA){rG^cML?ZGuLWF6$2O?i>@BuDpZ zo0iRw1uxXI>WJ#9fs(@`jKYrRk6vc2dr{c06K!wnOnAR{7B89txX#EIElQV6xN`+P z-X4l=PBrBcadZtmJhvfJ+m>f7IS9f2xzl>c_GQm^YGz(>V;!$2@my#4KG3d}|Kh-E zL>vyMWx*N@+SQ|6izd>SSio`$fkMx9Urplzsw4j;`qH8G9CLf7^tF&vC|yzjdJm5g z0`jVnA9j>p$mJ4iG}ullAbA$zaWM&hY>3|L^>*wjQ4vAx^XkNs^Zh&Y-`<%AYK#%8 z7NPa?0i+GS?Zy>ouL9k*B~YrvqQ^~nUKiql?7E2qe8RK4A3gtqex1qS5_~?J`K`;K z1=NO1_P$Q1`|AcC&S@hDbtl0q2jajfnH6dO!FQ;Ou9|5`6#liE zvr$Lw@e^MK0}Q-=dbPyf)qZR>aNl&D?9OC69#x?e(LDrP5NJcV*Sc45Rfp2}e)rcVsmCi+s+AHtIc7MR}7zvRInPg7-uK$c%jxM$t!W zYV2_BFdf6?j@3etwaI4oQ8YL1@?**JGxL57z~27S2)YSs&%$k)&_XtiWMa!>g``Sk ztt>T}B+bgoRoZMv&ES2vW7|aj0ZQ#^BAp9oV0h?d+;g7n{2A3Bh{j13EyL$Kj`y6QxD>4j_qf?Se>{Oz~9Q5r4ge=dyW< zmIg;cL-|40wIwp*(X>6yoEWD@*UpOM{=9nw+(^SHFf%$ILGh+Zh+?W{)52!~QUyi9P&@qnKFri$4TN415*b2r`5gYvuC( z5z3VAklE+_Cps@U+aW-fx%HS6|C;F={!UF)UDv}DCU{;PF!2Hh(OXce0st)REA9jH z0X66297(8u;TVh~oFSNh0^FXD^8>UfpOC?OpV={qJiB|w$L0@lGjfj(qT>J=f}&2h zOa8%LrQCRDyeAquk?o61ha*1cydQp0&GfUS7Puau7i0*e3yaprBmOf1#Dih&vSd?; z+*P4BnB8<8OlbRdrMGRJ_gv>Vn+n;hDP`KLZMDe$U~2s83_zCRdj+Eod#^TAo)ArW z3fxds0E&;*viRM90^go!@}Aqm!1vz0o=0GCsBT6@j|u$c7it8kHovbk25w;v^!Q={ z0>HQa@Ti6TU`?+8pDNqvr!ewX-Vw*mL!UC|p){*3I70kiXbZR(MhFPk{}-MY$_OJc z`@ALXvP3>@?tpg{)mL*|BoV@onx>z%13E7s6r?IhY?2R3^F3_=?({EgH*>mwK9EK` z{>^-r2{3<2?+DAKMYH+=GHql{>1|RywRSoC-4S*WV5#M|qMDX*b4<3`0k-6=ggn*0 z8|UKX3`07)nx4r8H>+k3Y1!+!WRp@Aw-Q^NLHvobz-Z ztI1YY1gtWOwBSC2;` z1p}(*E!`qi8xR=Yst=uAu1o1=UgX-W#&I8R0QC%~@?hKhCg@wr-CZt0V*ya))-F=@ zNMU*L%m~1C5GJo(ZQDYWUOggor2YfU?$%t+sA49g?}lac+^z+LWw&sen?sE!TY0^T zc)7I}kYm174;+KTXRm}+e|xil4OqiDj`aNx2)9_YBb1B&Rx1Y*v_A=8dSj>m>rwo8 zVT4#!*Kw$MwH@rYD>}Zo(fDRX76`SZf?2PdEHk(O>e$5JrNC>OpVt7y{ogN$%Fdn$ Zwo#rqUa31A2Ht3a5Sj*et27=w`7fyAggpQN diff --git a/DOCS/html/group__stm32f4xx.html b/DOCS/html/group__stm32f4xx.html deleted file mode 100644 index e2718d7..0000000 --- a/DOCS/html/group__stm32f4xx.html +++ /dev/null @@ -1,113 +0,0 @@ - - - - - - - -STM MATLAB Simulator: Stm32f4xx - - - - - - - - - - - -
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    - -
    -Generated by doxygen 1.10.0 -
    - - diff --git a/DOCS/html/group__stm32f4xx.map b/DOCS/html/group__stm32f4xx.map deleted file mode 100644 index e1559a4..0000000 --- a/DOCS/html/group__stm32f4xx.map +++ /dev/null @@ -1,8 +0,0 @@ - - - - - - - - diff --git a/DOCS/html/group__stm32f4xx.md5 b/DOCS/html/group__stm32f4xx.md5 deleted file mode 100644 index 5806374..0000000 --- a/DOCS/html/group__stm32f4xx.md5 +++ /dev/null @@ -1 +0,0 @@ -dd5eba9ad0e870a453ad2efb40437ca8 \ No newline at end of file diff --git a/DOCS/html/group__stm32f4xx.png b/DOCS/html/group__stm32f4xx.png deleted file mode 100644 index 0b18a401be5625da5f74cf03e0d91a54c22cd080..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 5941 zcmZu#2{=^k+aFs}RER7gj8T-r*s^CG4YKb`V;zH$eUxF|O4elTdl+Ni*D{zQLWqn) zmMD71GL|e^zf=F~yRPs0uKzVN_nC8_`#ksWoacG&f~hICO|cf2we|EW#!bsz{7sY%mNkB|Zdcv> zXnHO7=F6)y@9zq4azD9()3_qsH+{U(mfaQ-5WKsxHlgZ4!>Y?FPqZ!NEFBI#eTY3E zoEL4 z+;c6}0Cwlm7b!JoZ<1c<#Bp;8MEM84VY;;Pg@g(C{3HJRg*Y%$KLZMeWoG_&5hMn~ zw>x6eXYXQCXOT)rYSngXCBkK>R0FsEVHkd8+s4tY!g?GE{!wjOc5%nhy4`K`#h3!p z(0aR1Y+yJc>&>R8NQL0kpi;e~R*{QcZkxWmF^n3w52-N9s?ADG()(T2KX|}5iif2w zOUgX3{`A7Ubdp#ZjDFirrM}w{mx(xPZMG>kgvtLJjkGH%0lz;0^SH`RK(-sd0 zca{U~8kQwvfpM%hsja@j3~SBt!3eM2rQqFVN;9?&V}MV|lw*T^vTcCm$~+1Xf>*ouQc!ET$8y9GsS#3Wy!&UxZIkk zfBA0gU!z`nCwf7qV9+w|ha%hw54{hmrEg99Io81zs=mG=@)!?J9e6|jO`eADSdi%S zG+=ly63?D^;qQO%&&htV5{8va-x(7rH@v67fbL?yhbQnIaCEu!M!P;xmDhyfsUMi7 z808tJa3;>k0(KbQU}=I}64@Iq-mGpE7wV)QJ6$QS7aPc9LF5v zS{IQ7Eb0CwKM@-h9Tkra!OJXSu<`&#>4p^}gze_;g)MCuaKFslGFfWQ$XQN`2mvlb z>#*+>*U!$ub5!o(%{`>oxe9ry+;fI|8hPNdp@!%n$#Q|O6){{}VA!OKl=Q-i3t5Yk zwtE9A0yF)0MQaQq$cWWb@sO^0A4z~VCm6iT()l3sP}mQ&eqOs_tVo9`aP8HSU>3OV zQta){Fkn6;$AM|=nDW0|F3#n`7%ICCo2P59VQ-3Kjy-z~4D;8(gC*0X9Qs!#)b^zX z;u8`QXkY4F;;oxoBq3~NCysh!kTi~A`3y>d>r>@<9`+`pzso&lbow2z9LG(;maT=O+O37R;;{?VG*%6KU zFmr~)9jdS{Gxr*p!`Juoqf$EA=Zs^paTxNF_ze1{%++h>$DxErxvYn*trz#?{lL-^ z{Z9&zZwSIa7I;Kp_J)-iA@sFTq1MJ(@^C)WkaNObTrHrpxX%}~JR>Ze;o<3ESl8#5 zJOt}F*ZiolOdIXqonBlOC+(&fQA)@l)u8z21${i>;sdw`fGNC$F5>Q(j2hdc=NSo> zSv%f&c!c396YtJLx((-kMi*7SZJW#r(EgYwt!zFy?_~Mx65*aOdf0Og)k6pyL*yH*9!ag$AzxlVa0}PmfZ@ zyNbgcvyit>xFSGxEIk<#ha!D+VbXB5x0 z@^I=}@lj;L%6_`%77phtp!oPKdl^pbx3=Jj@rf;5Q4C*C6FH8j{#!%)SS6<1D)z7^ zZ@d!v6VAt{J1ipDo!vL~^u7B9fvH^(n!bZ_@-fOvodcE>PFKaz^OE(FJks;a2a&97 zZv64diSJw(oW}=6VRw9J2CwiL+mVFsldyJ0iqzrcVDGjgp4`$-;=Xmgqg7kyW5;@9 zt**rZ@<7b@BzNw0OT@mvn|YZzUx(LjnL5!#X|Nw{saq6YpOU?;n51 znF)o$)if%5Rg2zX+hVqFR>s^70>EN{aUE^!XP?8d}o5y`wCWQ)`k?iksQZ;!`4cpk`MGy zECGn9yC1LmXp>$eH=K@6t6V`{N(b&@$$E$Q-e=laFkl#Cbb zb95pPW*8s2%pZN}UV4}lMlBog?z9pG`~$8H@C2I!TCL*Q*214xZhwpD^qY?nU$h+G z+uKVe_s6%(5SZXSCM*5cQD9>{k$5Y&93@1vW9q&h?&2}D4iwX~-bbN}zK6%n}{@lmcuk_^1nLdByGK2#dWCkonjMC zigfsCGwLh*WZjD2Gj=y*@NTIUmT?s=w~4(wOlb^g;qmO_8f9kMHai!a#0DcI-L zU^B(n_<)q(^>%46yG3Acrn|yR2%@Jfz?`E2PN7;amBfH$;(A0&2{^pnsD9hGmSjaL zdS_K|_FrkG49&{+b<6p0HPm~3=wH+)7*rrb^%3b)cHra#%5atsipvV7!gly*-eTEV zB+1_@`Pdod(oIwj6pqhmOYE<(3**zdxKbLz7S(|UZ};y z#Y$vB$ubgZ8!myW5jB7!trFpvU?DwF!%ESTQMeXUbR{HNWF2Fs+4C;2bm-=P=|rfO}_i#}rPQn;!&B?pPYa zntI1+vz3SL(r#4=V{1+k_6_nb~9~7 zr^L4-+rvv%lNY}~S6*}O!;AR{BnLl62L%}3m9iN?Q=Z{__&dx=qvKGj1^O@->J~KG z;y-4hHytn?^tqi&kyDX>Pn9?>WBVIgM>d`n@P9AtU`RLOvlJq}sc6-Z^`wdQnvkj? z-*n)U5P$FUw`XYL#IQYj>HQyxIE(H=`6`b0+rO}EPt60ChJ4!15(?2oo1xiKC$Xwi zpVp#pz$Sj+p`%%uw$o&0zd*_~*#qJ@5dE!*c4c2>vJA(XO3KQK#TsduzON!Cg@^}E zUak0(l;F?GWnW+~hjMM)nzf5$;2{^ZYzusA%KuFLuA6Ha++bpZTpBEtZ{FwAY4A~P z&Im1~DIzeGmhACM%kXAVtXluQ`jUhTu|Jg|+micOVJfq{*=9XK1Z5JyqvjQ+2u z7e`f^!nUcgakqYWAlQkLdU|^NRbN|#q_;8K_d7VFwN1i5Hr)B(I@O1Oo0hS{_4Ytt zVBi=U{qU9E)OvG?xX4SKEOXX#T-|)UEYi#rsU6?)N>JyDOT6iD1~hD;FD9KB^Gq2?|)o+D;^q@JI9p$OdP*Y<3amjwW0l8**MQU z{3&1$_pc%65D0nK-nH@v=B{>j%Zd)`mIWmM@@{rD3cwe(8nnk99roaKymv{mMlo=oLnYm(Z*|Cb~ zBy&+hV$LKC{7+jnq{22X0}iGT{P}AA5C@iX=ZFwIn|6MmuYaQ#rQ8jMKa?1jv51ZX zYPsDy(iv0+H0rlf!oSX2i-SNYE&h3n_*6XqgUW?9@ovWS61sd*Vm7X|&Z7xAZ-G`b zvGR znT?GNN%ZS~iT1`&PhDNzwHvpij4UKlC50jmHwwG1K0R1#L%#v=EM2#6T_0gO%N_V= z>oPCztAd2-P92q+fOG3Co4iU*OsxP0loO(A(@VtWOb$GLvs_K`7s!mW&w+fS8)0(e zhQsR=psfqy?TGcGSXlkAJ$RBrsQZ)1qA{t^msu*WRN~zkPS{9ko|C_M*FVKXL>NK0 z<9FvsZMYf^fw_RNdsxajNJ*28(-y|Ivo9`YXop&Q{74k?`Cvw)xuDTTMQ(%IqI(1p)lMEC(Uwul3at+pOD<{_WbkcYsUMK9 zvaTz1+VIlIfI?XX>5Z7MaQKF)a>4h@g$xHeaJ6skaX-Hv(@DQOQrPG9PE3%^gm+lA ztU5zD`=r}KXxP3FnKL5L)Dt~VYws(0Nqf7ercj)H@Io68-jP=-*9CJz9nSgqt$henW1=))Af_7=BRfXiJs1e1wnS+}!Au%}yMZvvW(ymscjDVVA zMi!zwFWb~p$GOK*mqL3My`(qc~bULJmVD)MZ!jdvm>su-IZ`h0;vkGQPZr0}Yd-?7*<)1R}- zT;idCQ<*t&#p(oe)V#k+*>Y8C9{HUGQ`VErwYRE3N&N#(Ho?dAGrkddAv|prYDly)&ulDEOCSvpjBCm9pUV$N<=-tT@Dz~nS zka*74jW7r>+p#!B;rCWY|Ko;QETdd)rqasb53-?z^)9xQN*0`nGes7Adg)TY-~SX3MuqB<`&tol_wXF z-1IrNfnLKy@YDpPtZww;k)wF+vWM7rA)NP56TT`8<1iIT2}Y)UcVII#QllV)4}` zaP$LZEvRYI5}2`+M6ZZmCkC2peW#0Vk|qoTloh`x`dlM=Q^}WNj-RVvmAM*3G?BF{ zf|SX~32)`f3P7N2U4wOG2f+sJ%qbDTLQfa^x_5=asx$Cm_EN+=ErOt|&I|$;Psu zx5jV+%E8}f7`;Yc#BOUL&fvMawQ&5AcO#AI?9Rrc61SH>UlRD|_L8b&R?m*`?e{I9 zZ1I@`y_+yEFFKRuFGj3W4mRG3c!Fjv&)#imhXXdUWE`6w9(vl*sFF|d+#}BX>*-)O zzf*qvb;RFdWX*R`K+E2i*}d{=m%;c#xDfM2z9ewjuROXOgU((w%U6+)<3>&=?dSgAn zS;3EY{SeWW1Wt9JC(*TL>I+(d^tk`J(TzU0IfW~UdA_yuAHVK&9t1z9XlsHCp{JWk<&QmE`IEzJ%U1> zrB8HeNCn^>MStG_CHJ}9|7%+#k5R$(Y2i~eN82S|BTkM=2J_WVqCOd`AE7X*RsOsJ0_}yz4VgNOB4rUhy}h&P;J#Q= zf3|Xn)Ij=8kI&T(D>Lm6F?jI6mV{j~kUFDASj2P4S#qe@b6O1ZJ^X0bz(8owlzzTT z5}55)auoQQ?0*-8Yk0zjY-iI{)~Z4-7*@Yz8`rT|ID8)9sC-JzC3K#Bw1VO9m6`9@ zhji9-s=-pe?V?9tfZf~yD$vGuOW$Y9@Cds-Xk)YE)2NDigj{+bcHFqw;%?}lkX4=K zpfx^gsJt{BW{C0QV}}V;$j^>-qCM;;ho^f+2Y;io30dzfBH$%;^0CFaTP+WdrfZ49 zWiErh+D%io)3wyysw3jpe+R2`7hbm)G(UW#+?j2(U2c!!!|xZeibnK%y}&8}NLACv z0}F3?cJgPJfVVBuvJn+Khoqt8bkdN;&J#L-Q7qPP!xT@GQM)Kgr^$57PIw-5z-P>O zRASs{DBTh}j`H4aL#C)ad|+q;Fqno(dP~7Y+4gNe8Y`wVM%B>Vb`|-`N=^*{!C}Y2 z^WN!$X819jrl$dw2|!{{+*}4(-Gb`CYfQ|y?v23zsB(b@KUJFO2#^5)`v(Ko!XJ^v zGk%Vy3mBLe#iOiKV*cujO2BN5?p=;k(`oW;z74MmMu{S5sB7qJAQ13b=T;X;d;YNn zd=e9|mF**m{{0^SHWEjnmU-)`{Qx=`z0+U<+~OD==UZXOH0sv-3& UHIAMDJU9rZW29Yu$N8WC0d8G|1ONa4 diff --git a/DOCS/html/group__stm32f4xx__system.html b/DOCS/html/group__stm32f4xx__system.html deleted file mode 100644 index 40a5fbd..0000000 --- a/DOCS/html/group__stm32f4xx__system.html +++ /dev/null @@ -1,117 +0,0 @@ - - - - - - - -STM MATLAB Simulator: Stm32f4xx_system - - - - - - - - - - - -
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     STM32F4xx_System_Includes
     Define to prevent recursive inclusion.
     
     STM32F4xx_System_Exported_types
     
     STM32F4xx_System_Exported_Constants
     
     STM32F4xx_System_Exported_Macros
     
     STM32F4xx_System_Exported_Functions
     
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    Detailed Description

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    -Generated by doxygen 1.10.0 -
    - - diff --git a/DOCS/html/group__stm32f4xx__system.map b/DOCS/html/group__stm32f4xx__system.map deleted file mode 100644 index 69a68bf..0000000 --- a/DOCS/html/group__stm32f4xx__system.map +++ /dev/null @@ -1,9 +0,0 @@ - - - - - - - - - diff --git a/DOCS/html/group__stm32f4xx__system.md5 b/DOCS/html/group__stm32f4xx__system.md5 deleted file mode 100644 index 491ba18..0000000 --- a/DOCS/html/group__stm32f4xx__system.md5 +++ /dev/null @@ -1 +0,0 @@ -06111eb07fbac729f070aa92238ecd95 \ No newline at end of file diff --git a/DOCS/html/group__stm32f4xx__system.png b/DOCS/html/group__stm32f4xx__system.png deleted file mode 100644 index 85d292dbb1958e1b8058eed942f2d10a7dafe708..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 9919 zcma)icT`i|w`~9skS3sl6pp$3JJxA}he-Z5VJ%*oM;!npY>U-m3-9h>xA3tDT%q6lgxHRKk` znEJP)H8LAg6#n1e;zadoy4Pr7S2s5mDH)kOP7OA9yPn?OyD8xtRXj2JW;XHh@fm^Y zxy<*wgc3PY+R&Q;f0v6CH8l7%Sc*p*yl1+nr|ni6GC8`0;YeZmWkci@F{8goQDdf* zHc_~FJ6aY#lq&acGk=Y^`~3j**gn|UTA*TM!P@Xa*w~-izVRr#OfUBX^xaB$NWa(g znLk>McXP2p;8}60yE+qLu*~3E?c3XZDUBu@tr#yYUG0Hwq*d-otww0yOr5eQ*_xc^ zyxS(qDzVXlVHMmldj)qGx-F572rJl)d@oafw%AL*t#8Uw*FNR?ByrZ{5lZ*~N;b(W zTDN^A+%HdTahaD5-3S@yOCLQzLd_IxUbRSLdUm%a54U$z1kp<87nS5$)ZHemLy_Yv zJ~zKjS}q327QUlMBjpR01z<}yVhdkiI^H_8*eloA%-#_*E~^`IPg``j5_4`@{PkYs zVBeGX3QNstf3C_Kt-9oyXKp8~?5jumxGNcVfSJiUWnu6lz;k{wB(CwH1dMoiOLMPA ziT?e{TUC95{*p2tviDHNmE_5xJ1s>9n(khoY)0E%^iGeQcQYGI=J*!jRI*j}{OrQ) z+E;Nn{h}B`N35YF4n2Nu7S>rM4OiHRzhU7eu`8Y^Twyx%Q7i(^B~dC}7l+OaEO*u` zE6Ls6+7X{|=IonFcl$w5{tyb2uBaKmlSOnW~w;^k^fXae=G|Mr-ZD zX^~9cw&&K;n^+6@tk@IKEx9eV61-<|Um|S120Q22r}kh3u{}g`t*)C;3;?f zLQRsM-EOT8kMADn5WCzc5d#evPY=0LvKTyzGkr(Q-KaSo)2#qr;Eh6csnmbk!Gn>7 z2w)a1;W%_WTR)ObhJG}yHB9}eaWNDjBbMEjKXoc-LdxPocWmZ&FbeO33 zoufmu#6}?rFqQ%~Bv?vkL17b{37porVzm|zuIglX* z;fCj*i@=d9dnfQt2xsbfsR_{8?*fzEO`cG)^gX9(UtoKNO+29-8!Oj$bXGMiPZZ8Y z_=9VViNNtOnlBk3(M*pNe9z|39I4~0P2VSj(T4H(o_F*dG=A1edaiqsc<2n}p9ata_i5IVp z=Ti-+01sY{!&xzDZ9BXY*cF9msS4avbbONQ12Ku?OA>{9v^z0l+JDcNg}WX;D&K?oUuX2T$=-@}(!K;JBj|KgjElArh z$Tqa&RuwYjn8fhGEG(3*G~-j}O5W zfk`Q5H2jO~UV>ym9H0rUQKz8c?hnBczCALC3ya~Vi8A5|!}2J-qfyW86WR#)IMV~% z_RdjWz){)uuAr6cok?x?aZj^Ze?Ar6$bK&?!p00*w)jO6%{ZqALqBcX8I_z*HQJZL zHpIDn#$r8YL$>yoTQeHVi@q|1+HaK%za@-yHfN7LU%Wt^O#u$%%2z3pF8&<8I6n!GjM6*aRO9y6p-`-8#^lQpWl;x$SE+C%TzD;D zL%i7}IU?miyx%;iTrZjMCSXQkle?9SA+mm7iGaJ`q|rX5$q_8?_+Zu=4kem4KFesf zx6h8sJNo^!4*C=WeXc{0;xjbavZeG&*i5~|tbe{;ht*XmywbYBpjGP3ZzIq065HJt zARY;#6}mS1735>I+v$?sE;HNZI)g3QtbgKnxb(xY58OVPp5K}74$tR-?kV&a_k`RC z2p7OM)@2nsTDQs;7tvwPHRZ{%_-HxhkW&5{W>;TH#%*)@OqfNE{rRrhINPRMTJ(K& z3ay@JVI#jjgKQIJjQ@qsa(3XAgrV_W$avzg|uDZ37uR&=vjgD$=K`#%}*k7}jBhVo>$y^yEF@bJm+m*YPT+r!e z#(h~FHGwbbhIHj*laU)%;XtK0=^zsdjc^amVGO4Y<|o29m!{&di@<*{CK*FX8)XHy(U-Nl>#HsumXuX5zZ6Lo!>G0 z>irFLG7+^aJ+>ND?KU;6P)aWNR)>`9m^F;Hf^5X|CEe!@`1p8IHK_h6cvVe3nsEq> z0dso)py{W+2Xji>6`KpJ;g6R4-RM+4v+8+SImeBc35B{VcJKE8^G12$?wFrNWznPK zr>Z92D#2z{iLMKPao=H4r1zbuUt}=;qtVl{<#KMzR9#~Wp5jPHqQ}eNZQhVZi!u_z zU@ou9{jm*qeJ0=R6l{|3w_n$ApzS*uc}9i5II@)&!SkLS8V7ga^~pG`zIGRG{SV;? zjH`FKvRrP{%4sO$i#bCuAIS|zWcn5*?{PiL!&uxgC0uLut9T-+gUN6{j~#PnUw_*7 zN?%EO7DKrhYILw-m3OD(LQyOTWDCEn@#Y=4K;zhaN(ysZWnh7FLf_$+IQq!g?Oa`cvSry7t`qe0h2i~i?sW8 zk>{{vVN*%K=&#wwa)vg>!)Uqkbuw^F?m58dUg$Z;p6%cBO_x!wG$Ay`eXA&woh9K zB}qV|??QA2C1+yYwDh-td^3SN zUDO@qwmhN85*2MC|;K7XvUF&L+3r=MI8ORZ?3*b)~?Z2;~RZSuFU=8(m zf*^OIx1%jKucn9^*RYWYI2t@mH^~JlprgNJMe~sjuqeb z+K;qN@voPB?u16LRVmm%K#J0rMq`D0P*mn*r}HXZoCfPwG%(j@ky#f6a8>Z~>QnnC zgnm-Pr*D1vB7tbwCo)C|h6-%T*i1s3yV!5j@RF zDL1U_?<{B&gF6*sGmdPMo!p-)NdmQza!~`JRy~6}H_o}Bk`p*(Y z;ZDo17~x(V!J|WA0{C16BFY}!bfX-Y_=Rg^THA&>H;d$59)lylOm;AKY_vqcd``^X z`0ypt5i@XO-VuRld-fWiBCu&!eG_>_-jzvUuq6)l6w&9A@&VXTLP#DQB?X%tZy|W^ zGGtCjYgv}l0PDr`$Wo8R6Rcwe!|#{_oAnojmjOt0966lLc<DZj@MR=r$*nmK215Ke$nRZAlGVb*3wYnSYr0B8c9X zFyz<{!XS^ZadQW@{@G%53i0MY35)1 zsbaRLb>AJEh+~d^&*T>g*}sGTj#!*C$X51hX&7F%JAI5R?LvN~#fH0rqx?xmEcM;6 z0XAN$kxUgLncm1yMX}l$zuB!APseiZyWo2bD__y&>FMwE3mu}UlB9F(kFay+P0Q+4 zcSp?C4pwWOVuk7__tvKV^tfrKwDh87e`#FUw_r2gZ#i(!?e2*7-SxkrF-QO^j zFVlbMz<|jm72sLgov)&3?cvtDKI9kkWi#?!{2k}rayS5(-34Ap3HvR7^e+R`<@Q#N zeZ#BLxDWg$);$EmxAkHyPL)?9pf2a`aK3wRq{#f0ri?PtSWoG@E zzrX)@XVUwZz1b>_fn~cqll;W??d@#<{I&N9F?0-&AJ{0^jCTed1KZA#-9%VxQ`6V> zc3KAZ3nx^gI-aw#|7jdp3xuhwsHhYZPw4YrtQDCnG|s+pUau5z2A|m+A9M*uY3f}F zabA@h5!MJ=cixz7t?uB-yjgUuF>HxES4ZC7qd)2WU4!tJ=yLa?kyL=>_VkK+P|AI~ z+I7_xOl%Jt*6ZXbF0?EdvY1?EQwt5`@kpNe*cBKYN&FRYu~F!!zE%T3p^`2szLj;e zJ|hKPI!YYwmD>##gHaS60(e{YBT=$Mjn54D|nw@D~6)M?2SC&_z~+wl2no z4LTiUvm+f?wi?c={TIS-y&3<$hv>Y0BQvbqAn)Hquk81mnoX;T#`R7g0L80^42mp} zQG+M4$oYBXNP8psNi>62qk_Yw=W(q){*wNArUDLK8`9;4?mQq_HP1I-s`fUv(~#Xv zm;U9JEBLa@zM=4KoaCzHO0cEN=ca#|j*)cxDJ_e6xF>U8$vGK~CvW>yQ(le)qu2P% z)7+GfNdUdJzXCLNCp2XOFPbG@U_0b>Cpol0rN@AR?FJ+ctUi> zX@fmIuEMJVbv)g-Cjizh@OtS=?>I5*K%-2n$7#vU|2=B_|Bq(iEuZZtS`SsOHhxu~ z=V@1Of9VzkK`}(;z9u;u!FXzSkdJJ?VW_Q(2LY+BwH|bU=Q77iq1UXO?@oI)NLTX@3wuH;}=<`r@&-K%qG^>w$b>wjL|4e0UQYHdk^ z`;XrZDyIRyGC1$*pX*fUJ-21%aeNFzx9o0S`dbFE)H+!P-F}pXZNG*dE8P2%1y-Mh z%Rkf2t}{<7ED2(7tiMyVIS@6jYp~-(zsGX+y6#kimqrNX@2ggZ_TZ@@6Z_rB^l^xTk6fn_ajg8K@|S=DxS63|n`G|xm$D$L0K%iUiw;JQp>Ohc zpNg^8NqnkP@Z()v-8gjiV7YZ1ty4{i`1D{UOX=gY0f_+VpL4sYnrYE`x$b{N6K{Bl zQCc(xT@o)#Z|T14kw5$J&fgG4E(K><8-W>WBvw+1)}7GDclLGQjPPG4L+Ap=%jJG$ zDImV`YQ`Vnl=1br4Mm-6d#SRObLQFV#A5AO=dZ@u%9KY%!_A>tUAOxC`i9m5WplE# zKNjMJF2^{Wh)k2q{N{n5xLz_lhY9fy0>J&)cYXO)WUyM8tl-_cYZz=wh_DF$`FML6s-fBG<%igE=E z7o2X_sHw#^8|Q&5Kg*PZ`TTF1a`9NT+0Hqm!IF}Cm1_FqoVf492Vu>_#Ff%wm<%Ue#y_C z(X(C9WW+sZ<-0%o1f8xXx-8p!)#@=+z5dpul#%3GE^hRCmWAK95Wu?VvHkFgT<-te zMz*AhqV)PiZtEJKDBQ%`ZX48ypih~mP~mZ^Gby` z*S2zM&GqPk`f*eiq+O@6XAF<8>e+fP+_|aM-hR_ZSaj?2;f&yjm=UuyoE>1I<#mRJ z(JW85n{gmG=bH2xhNNoeFfj3T1Pmq3W(rS8Zl=Lqc$v1R2kA; zypmz1-f}HY9dF1YvsuYdaX%!)4h}4;twXdwUo#wwrO~6KvNk~Rt{3Olxj1)5GQGZn00Gw1Ay^#Q23|*b5?NYmrrfKk*%WFPP zt`79@%J^!2+jkqIsaj0?{D9tz5*vXev~x$JPHHpew4UkL%)dQXn{ul+>a1_)P$XZ> zILBY{@OS`OeV8Z^+nMsPgT1w8L4XxliJVv6TD<%E=ZCbp^=442Q@-CoYFi9a+jhp7azt25wj6x?J0ltJ zog=~ARj3_A6g#OWIA80!K(0UFom48suW(OecgTh>6s=-J;UWRN`KMr+q>ng0;V+|g zsEet4l{9-CS*IH~J?QgzWToK9tX~)xW(WeBk@cHlo0%l^ezlGmn4SI5dM7jTBQj77eW?xx1Bqtl+l63@-wqB68%%) zWH?F=v*sAF5yV(9N5T1vbdH`RGKw&IUksO@)Z;m|uW$qARSg(U)s&q-(yojPzc$3A zUMu!qpnC`vrO+XgSzD8$#dQ-5k?6^?i$)2xv2x_r_J=WiOru9+(m+yl(Pw6G?Ps}g zPfsIPitUg`dkc*f1cnEfD(Hpbyc&9^3%|B06?fweh7&dV?3m&DV4r=80@ z2FTkJg9wk+H5@jc|GTPc+Q9EQB4e=ZcLADLaXcBK@MoIHDq2(=Hpkq0ov{fe$KKA0 zkfkrWemo#M0Qe4rP8T*>sCCs$bC9|auF+lyR~ijN1Eg(H#=cKiCoG}EW}PvZ8~8mh zfX+Up(TKsN9p@{pqV#ZH2w4bBc!crciKLh3GDYEU_OnOkI7kV=eXV_-Tm>n_cxu1024W!5C!lyvKG&ULSQ*_W>%d@8VRawP)|4BiCXS@Nt{% z$Q75c^fPnSxH+zLG({Jm?bqR6G%+#33gocF{;!QrT}gV=;oH5$pw%CKU)mxL^6DP_ z>dxhM2;VF)cCad$0{pMiH}cRJea02rk4!1w50xDA^9VF5HxfTQJIBo}yY^U}`$|ME z*G<(J@S}+aer<1kCd>@Pm=?e&umZ6|y8hKb=Bg8}D2AIBmB?$#oE!Of84$u>*sgih z1K+BkqLR_lyIWeY*YpbT@wz-tN7I1e$+`lKD89=E;ij>oi=xA*0+Rli2l7BY1yd5l zfuvRfa(oC~W$fTlBtz0b{Bou~k@G%$`2k>yFwk{IMkL{U6oc;-((ez0`n;Z?i86a? zn(k1|QRdJ1mt#8TnE&}XgW#lwF^L_`3D;3B>lOJg9Xic;tM~&FxE1S`3nPY8y3!`n z8%!p5vr@^^UyPII{HI3$gsFhO3l!W1{53?eqr+96-$iF^1XEkdDRC;qYf2lMAqP9N z->1gR7wNQQLq^>P{5|KVjXkeDdKIt%-lul=_fp@2i% zZ%%%_^NPNW_7Ko-2^lr;CM(+wl@+r)$&=3)i5M@7MI|`8b)E7*;9#X<_tF-BZN(kv z(K~WpP^%;G^P7(^lcd@)6bGSjrdufc8t;`3MPur2ceun7tiq^_;-Ej2#Zq&O6-EhT zbKygR*EasT_ey??7;YfL#_J*&KBw-bUhQ- zUs#JGkb)%^uz%vA1DF#7DS_cszo(N_J;wq6%iGWHzxgqoXFj@(rrb_^zr3)btp@`< z;_SLu&p1`5T{5ELMoNA$()_%!D5J9&<%J6ro0S^B4Y<%X8KA%kvdV?y$OA|Ktc zpi^21p@=A^@PvVhev=M~bS2l;hr3aHoZ2J)u%~@6_`~50=o~F+3fGJH6%xf6tmZhX z4L9!uG_+R5i9WhKhH&2C+kjzA%mUo64E3KkMO4*$m-Bla{*}9j3Fq)ESBI#=q?b)U zKX|R4P-zBx^l?k>Gtc|SU{21!=ub@W~UYx2rQOp3NNy zJMJDm0Je9D_1maxJd;5pq+wH$A?xqiV*M+WK`=6d?U44WHbD+f>i73I-Y;#X6Qr}M zw$&Ltt^lJo)ATvIJbh&Q_Jl~i>xudz=1>W;)o4*UvqNBZ7ND9_-7f44;6LN&anw&M zM{!mzpR&rFw$9;-!~FPJU4g*V*%c$sRdPT*-*m!?nDQkF?qFs*M;940Ft}mD=y2i! zm>>(YK-SPwym&0QcAg>TdvtBgE^eHO>)=5`>fNW21Imf)K!cHNgJ{w>fds`@%{LgR zm#ogf`sfTIB<&X!E6#1zp* z{R1YDgJghDcf6^tsJNYW_hVqS=Xk|WkyH@g58T_QDGZEShgLumK#D54pZvkH>e77f z9}v!}x@b@|=NLzi^!{@V&{woS=%<+`S4KnfEYma{hC>zVaUHOqrg{*p$tq*0Yt0=yK>WC~%Jsej8WH$V>%7FVkZ{U635x-%vyF z<~U~1S?QBfsaRs7RohmYc#wK7%yZ?CfsNmKbIm8}pmS}i5%uVBvulo$;HJ6Yklm6# zl6teqzc&p4Ft5pmjvE3Aq86jekCOnm#GMm3>0V|(({uWemG45%6ydtvn3a<&K-KXF z*#t@XfS3+Ga`V~v&CN2UyT++mj z26CjrrfY;8Ay?c7H5(Q(75Y;28AetjfOls)OSLh}4OCc+ipnNuE{>c$CZviVa;~S1 z9VE7N+M*kT{;2!hIU8ck>0TKI`xfzXHG3KslIOTCM#MawhimA~63Z60`y3W0Eo@q4 z-QS6&?0%SP|86H+*$Xp?+Saj6(Xr?1cv`r|UjHJP80uW(B(!3`+{4b-5lSv#-^W;{(s}r|I;U_i(>-yf3?*^IUDC>fo1v zL;Z+7d1D$a>s~TqdX?XjYrM}8<6`*7h7dbnol!2qW5Mvb;VWPHpmQ$}8HcWW-Z9xM zvG`1hD$M<#0GC!==smpg;LJW70lX8t^3MsnX_Tctt zgIUz@=3)S*Ec>`RM!Hn1{y)_*ZWaGmbxfA}adpfCgTdgf$(8R94T<9NOOqC0QH?Q< z8V^}l^wSRqDmbrYvXdR>&;M3;Neej_pn0HBeOt>Xlc-YdWep^EP#`4*3PH|vduqrG zPgM3C8J8?X7RG=&kiuI6aaG3O>Wr)FGC>K-|Eq=yNM`P -STM MATLAB Simulator: Main Page +STM MATLAB Simulator: MATLAB STM32 EMULATOR @@ -14,6 +14,7 @@ + @@ -70,10 +71,155 @@ $(function() { -
    -
    STM MATLAB Simulator Documentation
    +
    +
    MATLAB STM32 EMULATOR
    +

    СОДЕРЖÐÐИЕ

    +

    +ÐžÐ±Ñ‰Ð°Ñ Ñтруктура ÑмулÑтора

    +

    ЭмулÑтор ÑоÑтоит из блух блоков:

      +
    • приложение МК
      • +
    • оболочка МК Ð´Ð»Ñ MATLAB, ÐºÐ¾Ñ‚Ð¾Ñ€Ð°Ñ Ð·Ð°Ð¿ÑƒÑкает приложение МК и Ñмулирует его периферию
      • +
    +

    Приложение МК в Ñвою очередь разделено еще на два блока:

      +
    • иÑходный код Ð¿Ð¾Ð»ÑŒÐ·Ð¾Ð²Ð°Ñ‚ÐµÐ»Ñ (код приложениÑ)
      • +
    • иÑходный код библиотек и драйверов
      • +
    +

    Ð”Ð»Ñ ÐºÐ°Ð¶Ð´Ð¾Ð³Ð¾ блока ÑÐ²Ð¾Ñ Ð¿Ð°Ð¿ÐºÐ°. Ð’Ñего три папки:

    +

    Далее приведена Ñтруктура ÑмулÑтора. ИнÑÑ‚Ñ€ÑƒÐºÑ†Ð¸Ñ Ð´Ð»Ñ Ð¿Ð¾Ñ€Ñ‚Ð¸Ñ€Ð¾Ð²Ð°Ð½Ð¸Ñ ÐºÐ¾Ð´Ð° в MATLAB приведена ниже

    +

    +ОпиÑание Ñтуктуры ÑмулÑтора (пример Ð´Ð»Ñ STM32)

    +

    ЗдеÑÑŒ ÑодержитьÑÑ Ð¾Ð¿Ð¸Ñание трех блоков ÑмулÑтора:

    +

    +Оболочка МК

    +

    Ð’ Ñтой папке ÑодержатьÑÑ Ð¾Ð±Ð¾Ð»Ð¾Ñ‡ÐºÐ°(англ. wrapper) Ð´Ð»Ñ Ð·Ð°Ð¿ÑƒÑка и ÐºÐ¾Ð½Ñ‚Ñ€Ð¾Ð»Ñ ÑмулÑции микроконтроллеров в MATLAB (любого МК, не только STM). Оболочка предÑтавлÑет Ñобой S-Function - блок в Simulink, который работает по Ñкомпилированому коду. КомпилÑÑ†Ð¸Ñ Ð¿Ñ€Ð¾Ð¸Ñходит Ñ Ð¿Ð¾Ð¼Ð¾Ñ‰ÑŒÑŽ MSVC-компилÑтора.

    +

    S-Function работает оÑобым образом: на шаге n она запуÑкает Ñкомпилированный код и ждет пока Ñтот код выполнитьÑÑ. Только когда завершаетÑÑ Ð²Ñ‹Ð¿Ð¾Ð»Ð½ÐµÐ½Ð¸Ðµ кода, S-Function переходит на Ñледующий шаг n+1.

    +

    Ðо программа МК Ñто беÑконечный цикл, который никогда не завершаетÑÑ. ПоÑтому еÑÑ‚ÑŒ неÑколько оÑобенноÑтей в выполнении такого кода в виде S-Function:

      +
    • Ð”Ð»Ñ ÑмулÑции ÑоздаетÑÑ Ð¾Ñ‚Ð´ÐµÐ»ÑŒÐ½Ñ‹Ð¹ поток Ð´Ð»Ñ Ð¿Ñ€Ð¾Ð³Ñ€Ð°Ð¼Ð¼Ñ‹ МК. Этот поток запуÑкаетÑÑ Ð² начале текущего шага ÑимулÑции, выполнÑетÑÑ ÐºÐ°ÐºÐ¾Ðµ-то времÑ, а потом приоÑтанавливаетÑÑ. Это позволÑет коду S-Function завершитьÑÑ Ð¸ перейти на Ñледующий шаг.
      • +
    • Ðеобходимо закрыть поток программы МК в конце ÑимулÑции. Ð”Ð»Ñ Ñтого иÑпользуетÑÑ Ð¾Ñобый дефайн Ð´Ð»Ñ while. Этот дефайн помимо уÑÐ»Ð¾Ð²Ð¸Ñ while, проверÑет уÑловие Ð¾ÐºÐ¾Ð½Ñ‡Ð°Ð½Ð¸Ñ ÑимулÑции. И еÑли ÑимулÑцию надо завершить, вÑе беÑконечные циклы while() пропуÑкаютÑÑ Ð¸ поток доходит до конца функции main() и завершает ÑебÑ.
      • +
    +

    Ð’Ñего оболочка Ñодержит 4 файла:

      +
    • mcu_wrapper.c     - файл, который запуÑкает код МК и управлÑет его ходом. Ð’ нем ÑодержатьÑÑ Ñ„ÑƒÐ½ÐºÑ†Ð¸Ð¸ Ð´Ð»Ñ Ð·Ð°Ð¿ÑƒÑка/оÑтановки потока программы МК, Ñчитывании входов и запиÑÑŒ входов S-Function в ÑоответÑтвии Ñ I/O портами МК.
      • +
    • MCU.c          - базовый файл, который предÑтавлÑет Ñобой иÑходный код Ð´Ð»Ñ ÐºÐ¾Ð¼Ð¿Ð¸Ð»Ñции S-Function в MATLAB. Вызывает функции из "mcu_wrapper.c"
      • +
    • mcu_wrapper_conf.h   - общий Ð´Ð»Ñ mcu_wrapper.c и MCU.c заголовочный файл. Содержит наÑтройки Ð´Ð»Ñ Ð±Ð»Ð¾ÐºÐ° S-Function, а также дефайны Ð´Ð»Ñ ÑƒÐ¿Ñ€Ð°Ð²Ð»ÐµÐ½Ð¸Ñ Ñ…Ð¾Ð´Ð¾Ð¼ программы МК.
      • +
    • run_mex.bat       - Ñкрипт Ð´Ð»Ñ ÐºÐ¾Ð¼Ð¿Ð¸Ð»Ñции кода компилÑтором MSVC. Ð’ нем пропиÑываютÑÑ Ð¿ÑƒÑ‚Ð¸ Ð´Ð»Ñ Ð·Ð°Ð³Ð¾Ð»Ð¾Ð²Ð¾Ñ‡Ð½Ñ‹Ñ… файлов ".h", указываютÑÑ Ñ„Ð°Ð¹Ð»Ñ‹ иÑходного кода ".c" и пропиÑываютÑÑ Ð´ÐµÑ„Ð°Ð¹Ð½Ñ‹ Ð´Ð»Ñ ÐºÐ¾Ð¼Ð¿Ð¸Ð»Ñции.
      • +
    +

    +ЭмулÑтор STM Ð´Ð»Ñ MATLAB

    +

    Ð’ папке "_\MCU_STM32xxx_Matlab_" еÑÑ‚ÑŒ два файла "stm32fxxx_matlab_conf.c/.h".

    +

    Ð’ них задаётÑÑ Ð¸ÑÐ¿Ð¾Ð»ÑŒÐ·ÑƒÐµÐ¼Ð°Ñ Ð¿ÐµÑ€Ð¸Ñ„ÐµÑ€Ð¸Ñ Ð¸ подключаютÑÑ Ð±Ð¸Ð±Ð»Ð¸Ð¾Ñ‚ÐµÐºÐ¸ Ð´Ð»Ñ Ð¿ÐµÑ€Ð¸Ñ„ÐµÑ€Ð¸Ð¸. Также объÑвлÑÑŽÑ‚ÑÑ Ñ„ÑƒÐ½ÐºÐºÑ†Ð¸Ð¸ Ð´Ð»Ñ Ð¸Ð½Ð¸Ñ†Ð¸Ð°Ð»Ð¸Ð·Ð°Ñ†Ð¸Ð¸/деинициализации периферии МК и Ñтруктуры Ð´Ð»Ñ ÑмулÑции периферии. СимулÑтор МК находитÑÑ Ð² папке STM32F4xx_SIMULINK.

    +

    Ð’ папке "_\MCU_STM32xxx_Matlab\Drivers_" находÑÑ‚ÑŒÑÑ Ñтандартные библиотеки Ð´Ð»Ñ STM/ARM, но переделанные под компилÑтор MSVC. Ð’Ñего там две папки: CMSIS, STM32F4xx_HAL_Driver.

    +
    Папка STM32F4xx_SIMULINK
    +

    Ð’ Ñтой папке ÑодержатьÑÑ Ñ„Ð°Ð¹Ð»Ñ‹ Ð´Ð»Ñ ÑмулÑции периферии STM32 в MATLAB. Структура файлов Ñ‚Ð°ÐºÐ°Ñ Ð¶Ðµ, как в библиотеке HAL:

      +
    • название Ñерии МК, который ÑмулируетÑÑ (matlab),
      • +
    • идентификатор, что Ñто Ð´Ð»Ñ MATLAB (matlab),
      • +
    • перифериÑ, функции Ð´Ð»Ñ ÑмулÑции которой Ñодержит конкретный файл (gpio, tim). Пример: "stm32f4xx_matlab_tim.c/.h"
      • +
    +
    Папка CMSIS
    +

    "Порт" библиотеки CMSIS Ð´Ð»Ñ MSVC. Ðиже приведен перечень вÑех файлов и краткое опиÑание зачем они нужны:

      +
    • arm_defines.h Содержит ARM дефайны Ð´Ð»Ñ ÐºÐ¾Ð¼Ð¿Ð¸Ð»Ñции в MSVC.
      • +
    • core_cm4_matlab.h Данный файл ÑвлÑетÑÑ ÐºÐ¾Ð¿Ð¸ÐµÐ¹ "core_cm4.h" Ñ Ð½ÐµÐºÐ¾Ñ‚Ð¾Ñ€Ñ‹Ð¼Ð¸ изменениÑми
        +
      • удалены первые ~160 Ñтрок, которые определÑÑŽÑ‚ компилÑтор ARM.
        • +
      • добавлена Ñтруктура Ð¸Ð¼Ð¸Ñ‚Ð¸Ñ€ÑƒÑŽÑ‰Ð°Ñ Ð¿Ð°Ð¼ÑÑ‚ÑŒ Ñдра *. Ð”Ð»Ñ Ñ‚Ð¾Ð³Ð¾, чтобы при обращении по адреÑам региÑтров МК не было иÑключений при чтении по недоÑтупному адреÑу.
        • +
      +
      • +
    • stdint.h Данный файл ÑвлÑетÑÑ ÐºÐ¾Ð¿Ð¸ÐµÐ¹ "stdint.h", из библиотеки Ð´Ð»Ñ STM32. (только вÑе дефайны uint32_t передалны как uint64_t. Т.к. в MATLAB вÑÑ‘ компилируетÑÑ Ð² 64-битном формате, то Ñохранении адреÑов в 32-битных переменных, адреÑа будут уÑекатьÑÑ Ð¸ будут ошибки.)
      • +
    • stm32f407xx_matlab.h Данный файл ÑвлÑетÑÑ ÐºÐ¾Ð¿Ð¸ÐµÐ¹ "stm32f407xx.h" Ñ Ð½ÐµÐºÐ¾Ñ‚Ð¾Ñ€Ñ‹Ð¼Ð¸ изменениÑми:
        +
      • добавлен каÑтомный "stdint.h" (через "", вмеÑто <>)
        • +
      • добавлен "arm_defines.h" Ñ ARM дефайнами Ð´Ð»Ñ MSVC
        • +
      • добавлен матлабовÑкий "cmsis_armcc_matlab.h" Ñ Ð²Ð¼ÐµÑто "cmsis_armcc.h"
        • +
      • добавлена Ñтруктура Ð¸Ð¼Ð¸Ñ‚Ð¸Ñ€ÑƒÑŽÑ‰Ð°Ñ Ð¿Ð°Ð¼ÑÑ‚ÑŒ Ñдра *. Ð”Ð»Ñ Ñ‚Ð¾Ð³Ð¾, чтобы при обращении по адреÑам региÑтров МК не было иÑключений при чтении по недоÑтупному адреÑу.
        • +
      +
      • +
    • stm32f4xx.h - оригинальный файл "stm32f4xx.h".
      • +
    • system_stm32f4xx.h - оригинальный файл "system_stm32f4xx.h".
      • +
    +

    *памÑÑ‚ÑŒ Ñдра не имитируетÑÑ Ð² полной мере, потому что STM32 - Ñто 32-битный процеÑÑор, он имеет 4 Гб памÑти. Ð MATLAB/MSVC делает ограничение на иÑпользование не больше 4Гб оперативной памÑти. При Ñтом еще еÑÑ‚ÑŒ матлабовÑкие переменные которые тоже занимают меÑто. ПоÑтому памÑÑ‚ÑŒ ÑмулируетÑÑ Ð»Ð¸ÑˆÑŒ чаÑтично. Как имено - задаетÑÑ Ð² дефайнах и Ñтруктуруре stm32f407xx_matlab.h.

    +
    Папка STM32F4xx_HAL_Driver
    +

    Ð”Ð°Ð½Ð½Ð°Ñ Ð±Ð¸Ð±Ð»Ð¸Ð¾Ñ‚ÐµÐºÐ° ÑвлÑетÑÑ ÐºÐ¾Ð¿Ð¸ÐµÐ¹ HAL, за некоторыми иÑключениÑми. Ð’ оÑновном каÑаютÑÑ Ð¼Ð°ÐºÑ€Ð¾Ñов Ð´Ð»Ñ Ð¾Ð¶Ð¸Ð´Ð°Ð½Ð¸Ñ Ñ„Ð»Ð°Ð³Ð°. Т.к. веÑÑŒ МК реализован програмно, то надо Ñамому пиÑать код, который будет выÑтавлÑÑ‚ÑŒ флаги по определенным уÑловиÑм. Только тогда библиотека HAL будет Ñто Ñчитывать и выполнÑÑ‚ÑŒ Ñвои функции. Ðо далеко не вÑегда еÑÑ‚ÑŒ необходимоÑÑ‚ÑŒ так делать.

    +

    ПоÑтому, вмеÑто того, чтобы пользоватьÑÑ Ð¾Ñ€Ð¸Ð³Ð¸Ð°Ð»ÑŒÐ½Ñ‹Ð¼ HAL и пиÑать ÑмулÑтор Ð´Ð»Ñ Ð²Ñего 32-битного контроллера, можно перепиÑать макроÑÑ‹ или даже функции целиком под Ñвои нужды.

    +

    +Код пользователÑ

    +

    Ð”Ð°Ð½Ð½Ð°Ñ Ð¿Ð°Ð¿ÐºÐ° Ñодержит иÑходный код Ð¿Ñ€Ð¸Ð»Ð¾Ð¶ÐµÐ½Ð¸Ñ ÐœÐš. При Ñтом драйверы и Ñтандартные/HAL библиотеки, которые общие Ð´Ð»Ñ Ð²Ñех проектов Ñледует помещать в папку Ñ ÑмулÑтором МК. Чтобы не редактировать иÑходники общих библиотек (CMSIS/HAL) в каждом проекте.

    +

    +ИнÑтрукциÑ

    +

    Общий алгоритм Ð¿Ð¾Ñ€Ñ‚Ð¸Ñ€Ð¾Ð²Ð°Ð½Ð¸Ñ ÐºÐ¾Ð´Ð° Ð´Ð»Ñ ÑимулÑции в MATLAB приведен ниже. Ð’ инÑтрукции еÑÑ‚ÑŒ ÑÑылки на более подробное опиÑание дейÑтвий.

      +
    1. Портировать код Ð´Ð»Ñ MATLAB (можно начать Ñ Ð¿Ð¾Ñ€Ñ‚Ð¸Ñ€Ð¾Ð²Ð°Ð½Ð¸Ñ Ð±ÐµÐ· изменений и далее дейÑтвовать от шага 2)
      2. +
    2. Проверить компилируетьÑÑ Ð»Ð¸ код. Рдалее:
        +
      • еÑли еÑÑ‚ÑŒ ошибки при компилÑции, иÑправить их и вернутьÑÑ Ð½Ð° шаг 2.
        • +
      • еÑли ошибок нет, перейти на шаг 3.
        • +
      +
      3. +
    3. Проверить нормально ли запуÑкаетÑÑ Ð¸ работает ÑимулÑÑ†Ð¸Ñ Ñ ÐœÐš. Рдалее: +
      4. +
    4. Оценить результаты ÑимулÑции. Рдалее:
        +
      • еÑли ÑимулÑÑ†Ð¸Ñ ÑходитÑÑ Ñ Ñ€ÐµÐ°Ð»ÑŒÐ½Ð¾Ñтью - то вÑÑ‘ работает корректно.
        • +
      • еÑли нет - необходимо иÑправить ошибки в драйверах и перейти на шаг 2.
        • +
      +
      5. +
    +

    +Портирование кода

    +
    Код программы
    +

    Ð”Ð»Ñ Ð½Ð°Ñ‡Ð°Ð»Ð° необходимо веÑÑŒ пользовательÑкий код портировать в отдельную папку Ð´Ð»Ñ ÑƒÐ´Ð¾Ð±Ñтва. Ðапример в "_\Code_".

    +

    Далее в "[run_bat.mex](#оболочка-мк)" надо пропиÑать пути Ð´Ð»Ñ Ð·Ð°Ð³Ð¾Ð»Ð¾Ð²Ð¾Ñ‡Ð½Ñ‹Ñ… файлов (_\Includes_). Ð’Ñе файлы иÑходников "_*.c_" пропиÑывать не обÑзательно. Можно пропиÑать только папки Ñ Ð¸Ñходниками, как Ñ Ð·Ð°Ð³Ð¾Ð»Ð¾Ð²Ð¾Ñ‡Ð½Ñ‹Ð¼Ð¸ файлами. Далее Ñкрипт Ñам Ñканирует и ищет вÑе иÑходники.

    +
    ЭмулÑтор и библиотеки
    +

    ЭмулÑтор и библиотеки ÑвÑзаны в том плане, что необходимо выбрать через что будет реализована перифериÑ

      +
    • полноценный ÑмулÑтор, тогда функции библиотек оÑтаютÑÑ Ð±ÐµÐ· изменений и проÑто работает не Ñ Ñ€ÐµÐ°Ð»ÑŒÐ½Ð¾Ð¹ периферией, а Ñ ÐµÑ‘ ÑмулÑтором
      • +
    • упрощенный ÑмулÑтор, тогда функции библиотек тоже надо или упроÑтить или Ñделать их-dummy.
      • +
    • игнорирование периферии. ЕÑли Ð¿ÐµÑ€Ð¸Ñ„ÐµÑ€Ð¸Ñ Ð½Ðµ важна Ð´Ð»Ñ ÑимулÑции, можно проÑто в программе МК убрать вÑе выховы функций, ÑвÑзанные Ñ Ð½ÐµÐ¹ или Ñделать их dummy.
      • +
    +

    Скрипты Ð´Ð»Ñ ÑмулÑции периферии необходимо пропиÑывать вручную. Ð’ Ñлучае STM32 руководÑтвоватьÑÑ Ñледует только региÑтрами CMSIS, чтобы не привÑзыватьÑÑ Ðº HAL, и была возможноÑÑ‚ÑŒ ÑимулÑции кода без него. Или же пробовать делать универÑальный через дефайны, которые будут определÑÑ‚ÑŒ доÑтуп к конкретным региÑтрам конкретного МК.

    +
    Примеры ÑмулÑции периферии
    +

    Пример 1 (полноценный ÑмулÑтор): можно напиÑать полный ÑмулÑтор Ð´Ð»Ñ Ñ‚Ð°Ð¹Ð¼ÐµÑ€Ð¾Ð², Ñ‚.к. Ñто очень важна чаÑÑ‚ÑŒ МК. ÐŸÐ»ÑŽÑ Ð¾Ð½Ð° чаÑто корректируетÑÑ: разные режимы таймеров, Ñ€Ð°Ð·Ð½Ð°Ñ Ñ‡Ð°Ñтота, разные каналы. И удобно, еÑли вÑÑ‘ Ñто можно менÑÑ‚ÑŒ "на ходу", а не только во Ð²Ñ€ÐµÐ¼Ñ ÐºÐ¾Ð¼Ð¿Ð¸Ð»Ñциию.

    +

    Пример 2 (упрощенный ÑмулÑтор): Ð’ Ñлучае, еÑли не нужна ÑмулÑÑ†Ð¸Ñ Ð¿ÐµÑ€Ð¸Ñ„ÐµÑ€Ð¸Ð¸. Ðапример Ð´Ð»Ñ Ð¿Ñ€Ð¾Ñ‚Ð¾ÐºÐ¾Ð»Ð¾Ð² общениÑ, типа UART/MODBUS, можно проÑто Ñделать отдельные входы в S-Function, и напрÑмую брать Ð·Ð½Ð°Ñ‡ÐµÐ½Ð¸Ñ Ð¾Ñ‚Ñ‚ÑƒÐ´Ð° и запиÑывать в переменные программы, без приёма отдельных битов, парÑинга и прочего. Ðо тогда надо будет редактировать библиотеки и делать dummy-функции, чтобы они не ждали ответа от периферии, ÐºÐ¾Ñ‚Ð¾Ñ€Ð°Ñ Ð½Ðµ ÑмулируетÑÑ. Или же редактировать пользовательÑкий код.

    +

    Пример 3 (игнорирование периферии): CubeMX иÑпользует функции RCC_Config, которые наÑтраивают тактирование МК. Ð’ HAL'e в функции инициализации поÑтоÑнно иÑпользуютÑÑ bit-banding, который реализован аппаратно. Это некоторые адреÑÑа, которые могут переключать отдельные биты через приÑваивание (Ñродни BSRR у GPIO, только Ð´Ð»Ñ Ð²Ñей периферии). ÐŸÐ»ÑŽÑ ÐµÑ‰Ðµ HAL дополнительно проверÑет реально ли выÑтавилиÑÑŒ Ñти биты в региÑтрах, поÑтому Ñ Ñтим надо что-то Ñделать. Т.к. региÑтры RCC не важны Ð´Ð»Ñ ÑимулÑции большинÑтва программ, можно проÑто убрать единÑтвенный вызов Ñтой функции в main, или Ñделать её dummy - в HAL-библиотеке.

    +

    ПоÑле Ð¿Ð¾Ñ€Ñ‚Ð¸Ñ€Ð¾Ð²Ð°Ð½Ð¸Ñ ÐºÐ¾Ð´Ð° надо Ñкомпилировать код МК и далее уже Ñмотреть по ошибкам, что надо иÑправлÑÑ‚ÑŒ.

    +

    +Как Ñкомпилировать код

    +

    Ð”Ð»Ñ ÐºÐ¾Ð¼Ð¿Ð¸Ð»Ñции кода необходимо открыть файл mexing.m. Это MATLAB-Ñкрипт, который запуÑкает Ñкрипт "[run_bat.mex](#оболочка-мк)" Ð´Ð»Ñ ÐºÐ¾Ð¼Ð¿Ð¸Ð»Ñции. Также Ñтот файл задает Ð²Ñ€ÐµÐ¼Ñ Ð´Ð¸Ñкретизации Ð´Ð»Ñ ÑимулÑции и дает возможноÑÑ‚ÑŒ компилÑции кода Ð´Ð»Ñ Ð¾Ñ‚Ð»Ð°Ð´ÐºÐ¸

    +

    +Как запуÑтить отладку

    +

    Ð”Ð»Ñ Ð¾Ñ‚Ð»Ð°Ð´ÐºÐ¸ ÑимулÑции необходимо припиÑать в mexing.m в вызове "run_mex.bat" Ñлово debug, тогда код ÑкомпилируетÑÑ Ð´Ð»Ñ Ð´ÐµÐ±Ð°Ð³Ð°. ПоÑле Ñтого необходимо открыть любой(?) редактор кода, например Visual Studio. Открыть папку проекта (там должны быть вÑе иÑходники программы и ÑмулÑтора). И подключитьÑÑ Ðº MATLAB.exe.

    +

    Теперь можно поÑтавить точку в иÑходном коде ÑмулÑтора или программы МК и запуÑтить ÑимулÑцию. Когда MATLAB дойдет до Ñтого меÑта, ÑимулÑÑ†Ð¸Ñ Ð¾ÑтановитьÑÑ Ð¸ в Visual Studio можно будет поÑмотреть вÑе переменные, пройти код по Ñтрокам и в общем делать вÑÑ‘ то, что можно делать в режиме отладки. Ðо отладка рабоатет только один раз. При повторном запуÑке ÑимулÑции оÑтановки не произойдет. ПоÑтому перед каждой отладкой надо перекомпилировать код.

    +

    +Ошибки

    +

    +Ошибки при компилÑции

    +

    Самые раÑпроÑтраненые ошибки компилÑтора при портировании нового кода - Ñто ошибки переопределениÑ. СвÑзаны Ñ weak-фукнциÑми. Ð’ MSVC их нет как таковых. ПоÑтому необходимо закомментировать вÑе weak-функции в HAL или пользовательÑком коде, чтобы на веÑÑŒ код было только одно определение функции.

    +

    +Ошибки при ÑимулÑции

    +

    Обычно Ñто иÑÐºÐ»ÑŽÑ‡ÐµÐ½Ð¸Ñ Ð¿Ñ€Ð¸ чтении по недоÑтупному адреÑу. СвÑзано Ñ Ñ€Ð°Ð·Ð½Ñ‹Ð¼ адреÑным проÑтранÑтвом МК и ПК. ПоÑтому надо выÑÑнить на какой Ñтроке произошло иÑключение. И Ñмотреть по какому адреÑу произошла попытка Ñ‡Ñ‚ÐµÐ½Ð¸Ñ Ð¸ по какому адреÑу надо на Ñамом деле Ñчитывать. И поÑле Ñтого Ñкорректировать код так, чтобы Ð°Ð´Ñ€ÐµÑ Ð±Ñ€Ð°Ð»ÑÑ ÐºÐ¾Ñ€Ñ€ÐµÐºÑ‚Ð½Ñ‹Ð¹.

    +

    Из общих решений - Ñто может быть при попытки Ñ‡Ñ‚ÐµÐ½Ð¸Ñ Ð¿Ð¾ "ÑкзотичеÑким" адреÑам (bit-banding), Ð´Ð»Ñ ÐºÐ¾Ñ‚Ð¾Ñ€Ñ‹Ñ… не определено адреÑное проÑтранÑтво в ÑимулÑции.

    +
    diff --git a/DOCS/html/mcu__wrapper_8c.html b/DOCS/html/mcu__wrapper_8c.html index 9155f56..f0eef5e 100644 --- a/DOCS/html/mcu__wrapper_8c.html +++ b/DOCS/html/mcu__wrapper_8c.html @@ -14,6 +14,7 @@ + @@ -81,6 +82,9 @@ $(function() {
    mcu_wrapper.c File Reference
    + +

    ИÑходный код оболочки МК. +More...

    #include "mcu_wrapper_conf.h"
    + Include dependency graph for mcu_wrapper.c:
    @@ -89,20 +93,20 @@ $(function() { -
    + +

    Go to the source code of this file.

    +
    - + - + - - - - - - - - - - - - + + + + + + + + + + + + - + - - - - - - + + + + + +

    Functions

    int main (void)
     Main function of MCU app.
     Ð“Ð»Ð°Ð²Ð½Ð°Ñ Ñ„ÑƒÐ½ÐºÑ†Ð¸Ñ Ð¿Ñ€Ð¸Ð»Ð¾Ð¶ÐµÐ½Ð¸Ñ ÐœÐš.
     
    unsigned __stdcall MCU_App_Thread (void)
     Thread that run MCU code.
     ÐŸÐ¾Ñ‚ок Ð¿Ñ€Ð¸Ð»Ð¾Ð¶ÐµÐ½Ð¸Ñ ÐœÐš.
     
    void MCU_Step_Simulation (SimStruct *S, time_T time)
     Read from simulink S-Block Inputs and write to MCU I/O ports.
     
    void MCU_Periph_Simulation (void)
     Simulate peripheral of MCU.
     
    void MCU_readInputs (SimStruct *S)
     Read from simulink S-Block Inputs and write to MCU I/O ports.
     
    void MCU_writeOutputs (SimStruct *S)
     Read from MCU I/O ports and write to simulink S-Block Outputs.
     
    void MCU_Step_Simulation (SimStruct *S, time_T time)
     Ð¡Ð¸Ð¼ÑƒÐ»ÑÑ†Ð¸Ñ ÐœÐš на один такт ÑимулÑции.
     
    void MCU_Periph_Simulation (void)
     Ð¡Ð¸Ð¼ÑƒÐ»ÑÑ†Ð¸Ñ Ð¿ÐµÑ€Ð¸Ñ„ÐµÑ€Ð¸Ð¸ МК
     
    void MCU_readInputs (SimStruct *S)
     Ð¡Ñ‡Ð¸Ñ‚ывание входов S-Function в порты ввода-вывода.
     
    void MCU_writeOutputs (SimStruct *S)
     Ð—апиÑÑŒ портов ввода-вывода в буфер выхода S-Function.
     
    void SIM_writeOutputs (SimStruct *S)
     Write S-Function Output ports to inputs.
     Ð¤Ð¾Ñ€Ð¼Ð¸Ñ€Ð¾Ð²Ð°Ð½Ð¸Ðµ выходов S-Function.
     
    void SIM_Initialize_Simulation (void)
     Initialize structures and variables for simulating MCU.
     
    void SIM_deInitialize_Simulation (void)
     Deinitialize structures and variables for simulating MCU.
     
    void SIM_Initialize_Simulation (void)
     Ð˜Ð½Ð¸Ñ†Ð¸Ð°Ð»Ð¸Ð·Ð°Ñ†Ð¸Ñ ÑимулÑции МК.
     
    void SIM_deInitialize_Simulation (void)
     Ð”ÐµÐ¸Ð½Ð¸Ñ†Ð¸Ð°Ð»Ð¸Ð·Ð°Ñ†Ð¸Ñ ÑимулÑции МК.
     
    - - - - - - - - - + + + + + + + + + + + +

    Variables

    SIM__MCUHandleTypeDef hmcu
     extern Ð´Ð»Ñ Ð²Ð¸Ð´Ð¸Ð¼Ð¾Ñти переменной во вÑех файлах
     
    double SystemClockDouble = 0
     
    double SystemClock_step = 0
     
    uint64_t SystemClock
     
    SIM__MCUHandleTypeDef hmcu
     Ð¥ÐµÐ½Ð´Ð» Ð´Ð»Ñ ÑƒÐ¿Ñ€Ð°Ð²Ð»ÐµÐ½Ð¸Ñ Ð¿Ð¾Ñ‚Ð¾ÐºÐ¾Ð¼ программы МК
     
    double SystemClockDouble = 0
     Ð¡Ñ‡ÐµÑ‚чик в формате double Ð´Ð»Ñ Ñ‚Ð¾Ñ‡Ð½Ð¾Ð¹ ÑимулÑции ÑиÑтемных тиков С промежуточными значений
     
    uint64_t SystemClock
     Ð¡Ñ‡ÐµÑ‚чик тактов Ð´Ð»Ñ ÑимулÑции ÑиÑтемных тиков (в целочиÑленном формате)
     
    double SystemClock_step = 0
     Ð¨Ð°Ð³ тиков Ð´Ð»Ñ Ð¸Ñ… ÑимулÑции, в формате double.
     
    -

    Function Documentation

    +

    Detailed Description

    +

    ИÑходный код оболочки МК.

    +

    Данный файл Ñодержит функции Ð´Ð»Ñ ÑимулÑции МК в Simulink (S-Function).

    + +

    Definition in file mcu_wrapper.c.

    +

    Function Documentation

    ◆ main()

    @@ -182,8 +196,8 @@ Variables
    -

    Main function of MCU app.

    -

    Ð¤ÑƒÐ½ÐºÑ†Ð¸Ñ Ñ ÐºÐ¾Ñ‚Ð¾Ñ€Ð¾Ð¹ начинаетÑÑ Ð²Ñ‹Ð¿Ð¾Ð»Ð½ÐµÐ½Ð¸Ðµ кода МК. Выход из данной функции проиÑходит только в конце ÑимулÑции mdlTerminate

    +

    Ð“Ð»Ð°Ð²Ð½Ð°Ñ Ñ„ÑƒÐ½ÐºÑ†Ð¸Ñ Ð¿Ñ€Ð¸Ð»Ð¾Ð¶ÐµÐ½Ð¸Ñ ÐœÐš.

    +

    Ð¤ÑƒÐ½ÐºÑ†Ð¸Ñ Ñ ÐºÐ¾Ñ‚Ð¾Ñ€Ð¾Ð¹ начинаетÑÑ Ð²Ñ‹Ð¿Ð¾Ð»Ð½ÐµÐ½Ð¸Ðµ кода МК. Выход из данной функции проиÑходит только в конце ÑимулÑции mdlTerminate

    @@ -202,9 +216,10 @@ Variables
    -

    Thread that run MCU code.

    -

    THREAD FOR MCU APP

    +

    Поток Ð¿Ñ€Ð¸Ð»Ð¾Ð¶ÐµÐ½Ð¸Ñ ÐœÐš.

    Поток, который запуÑкает и выполнÑет код МК (main).

    + +

    Definition at line 37 of file mcu_wrapper.c.

    + Here is the call graph for this function:
    @@ -212,269 +227,12 @@ Variables -
    -
    - -

    ◆ MCU_Step_Simulation()

    - -
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    - - - - - - - - - - - -
    void MCU_Step_Simulation (SimStruct * S,
    time_T time )
    -
    - -

    Read from simulink S-Block Inputs and write to MCU I/O ports.

    -

    SIMULATE MCU FOR ONE SIMULATION STEP

    Parameters
    - - -
    time- current time of simulation (in second).
    -
    -
    -

    ЗапуÑкает поток, который выполнÑет код МК и управлÑет ходом потока: ЕÑли прошел таймаут, поток прерываетÑÑ, ÑимулируетÑÑ Ð¿ÐµÑ€Ð¸Ñ„ÐµÑ€Ð¸Ñ Ð¸ на Ñледующем шаге поток возобнавлÑетÑÑ.

    -
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    -
    - - -
    -
    - -

    ◆ MCU_Periph_Simulation()

    - -
    -
    - - - - - - - -
    void MCU_Periph_Simulation (void )
    -
    - -

    Simulate peripheral of MCU.

    -

    SIMULATE MCU PERIPHERAL

    -

    ПользовательÑкий код, который Ñимулирует работу периферии МК.

    -
    - + Here is the call graph for this function:
    -
    -
    - - -
    -
    - -

    ◆ MCU_readInputs()

    - -
    -
    - - - - - - - -
    void MCU_readInputs (SimStruct * S)
    -
    - -

    Read from simulink S-Block Inputs and write to MCU I/O ports.

    -

    READ INPUTS S-FUNCTION TO MCU REGS

    Parameters
    - - -
    in- inputs of S-Function.
    -
    -
    -

    ПользовательÑкий код, который запиÑывает в порты ввода-вывода из disc.

    -
    - + Here is the call graph for this function:
    -
    -
    - - -
    -
    - -

    ◆ MCU_writeOutputs()

    - -
    -
    - - - - - - - -
    void MCU_writeOutputs (SimStruct * S)
    -
    - -

    Read from MCU I/O ports and write to simulink S-Block Outputs.

    -

    WRITE OUTPUTS BUFFER S-FUNCTION FROM MCU REGS

    Parameters
    - - -
    disc- discrete array of S-Function. Outputs would be written from disc.
    -
    -
    -

    ПользовательÑкий код, который запиÑывает в disc порты ввода-вывода.

    -
    - + Here is the call graph for this function:
    -
    -
    - -
    @@ -492,149 +250,16 @@ Variables
    -

    Write S-Function Output ports to inputs.

    -

    WRITE OUTPUTS OF S-BLOCK

    Parameters
    +

    Формирование выходов S-Function.

    +
    Parameters
    - +
    disc- discrete array of S-Function. Outputs would be written from disc.
    S- указатель на Ñтруктуру S-Function из "simstruc.h"
    -

    ПользовательÑкий код, который запиÑывает выходы S-Function.

    +

    ПользовательÑкий код, который запиÑывает выходы S-Function из буфера.

    -
    - - -

    ◆ SIM_Initialize_Simulation()

    - -
    -
    - - - - - - - -
    void SIM_Initialize_Simulation (void )
    -
    - -

    Initialize structures and variables for simulating MCU.

    -

    MCU WRAPPER DEINITIALIZATION

    -

    ПользовательÑкий код, который будет наÑтраивать вÑе Ñтруктуры Ð´Ð»Ñ ÑимулÑции.

    -
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    ◆ SIM_deInitialize_Simulation()

    - -
    -
    - - - - - - - -
    void SIM_deInitialize_Simulation (void )
    -
    - -

    Deinitialize structures and variables for simulating MCU.

    -

    MCU WRAPPER DEINITIALIZATION

    -

    ПользовательÑкий код, который будет очищать вÑе Ñтруктуры поÑле Ð¾ÐºÐ¾Ð½Ñ‡Ð°Ð½Ð¸Ñ ÑимулÑции.

    -
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    - - -
    -
    -

    Variable Documentation

    - -

    ◆ hmcu

    - -
    -
    - - - - -
    SIM__MCUHandleTypeDef hmcu
    -
    - -

    extern Ð´Ð»Ñ Ð²Ð¸Ð´Ð¸Ð¼Ð¾Ñти переменной во вÑех файлах

    - -
    -
    - -

    ◆ SystemClockDouble

    - -
    -
    - - - - -
    double SystemClockDouble = 0
    -
    - -
    -
    - -

    ◆ SystemClock_step

    - -
    -
    - - - - -
    double SystemClock_step = 0
    -
    - -
    -
    - -

    ◆ SystemClock

    - -
    -
    - - - - -
    uint64_t SystemClock
    -
    +

    Definition at line 122 of file mcu_wrapper.c.

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    +
    + + + + + + +
    +
    STM MATLAB Simulator +
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    mcu_wrapper.c
    +
    +
    +Go to the documentation of this file.
    1/**
    +
    2**************************************************************************
    +
    3* @file mcu_wrapper.c
    +
    4* @brief ИÑходный код оболочки МК.
    +
    5**************************************************************************
    +
    6@details
    +
    7Данный файл Ñодержит функции Ð´Ð»Ñ ÑимулÑции МК в Simulink (S-Function).
    +
    8**************************************************************************/
    +
    9#include "mcu_wrapper_conf.h"
    +
    10
    +
    11/**
    +
    12 * @addtogroup WRAPPER_CONF
    +
    13 * @{
    +
    14 */
    +
    15
    +
    16SIM__MCUHandleTypeDef hmcu; ///< Хендл Ð´Ð»Ñ ÑƒÐ¿Ñ€Ð°Ð²Ð»ÐµÐ½Ð¸Ñ Ð¿Ð¾Ñ‚Ð¾ÐºÐ¾Ð¼ программы МК
    +
    17
    +
    18double SystemClockDouble = 0; ///< Счетчик в формате double Ð´Ð»Ñ Ñ‚Ð¾Ñ‡Ð½Ð¾Ð¹ ÑимулÑции ÑиÑтемных тиков С промежуточными значений
    +
    19uint64_t SystemClock; ///< Счетчик тактов Ð´Ð»Ñ ÑимулÑции ÑиÑтемных тиков (в целочиÑленном формате)
    +
    20double SystemClock_step = 0; ///< Шаг тиков Ð´Ð»Ñ Ð¸Ñ… ÑимулÑции, в формате double
    +
    21
    +
    22/** MCU_WRAPPER
    +
    23 * @}
    +
    24 */
    +
    25//-------------------------------------------------------------//
    +
    26//-----------------CONTROLLER SIMULATE FUNCTIONS---------------//
    +
    27/* THREAD FOR MCU APP */
    +
    28/**
    +
    29 * @brief Ð“Ð»Ð°Ð²Ð½Ð°Ñ Ñ„ÑƒÐ½ÐºÑ†Ð¸Ñ Ð¿Ñ€Ð¸Ð»Ð¾Ð¶ÐµÐ½Ð¸Ñ ÐœÐš.
    +
    30 * @details Ð¤ÑƒÐ½ÐºÑ†Ð¸Ñ Ñ ÐºÐ¾Ñ‚Ð¾Ñ€Ð¾Ð¹ начинаетÑÑ Ð²Ñ‹Ð¿Ð¾Ð»Ð½ÐµÐ½Ð¸Ðµ кода МК. Выход из данной функции проиÑходит только в конце ÑимулÑции @ref mdlTerminate
    +
    31 */
    +
    32extern int main(void); // extern while from main.c
    +
    33/**
    +
    34 * @brief Поток Ð¿Ñ€Ð¸Ð»Ð¾Ð¶ÐµÐ½Ð¸Ñ ÐœÐš.
    +
    35 * @details Поток, который запуÑкает и выполнÑет код МК (@ref main).
    +
    36 */
    +
    +
    37unsigned __stdcall MCU_App_Thread(void) {
    +
    38 main(); // run MCU code
    +
    39 return 0; // end thread
    +
    40 // note: this return will reached only at the end of simulation, when all whiles will be skipped due to @ref sim_while
    +
    41}
    +
    +
    42/* SIMULATE MCU FOR ONE SIMULATION STEP */
    +
    43/**
    +
    44 * @brief СимулÑÑ†Ð¸Ñ ÐœÐš на один такт ÑимулÑции.
    +
    45 * @param S - указатель на Ñтруктуру S-Function из "simstruc.h"
    +
    46 * @param time - текущее Ð²Ñ€ÐµÐ¼Ñ ÑимулÑции.
    +
    47 * @details ЗапуÑкает поток, который выполнÑет код МК и управлÑет ходом потока:
    +
    48 * ЕÑли прошел таймаут, поток прерываетÑÑ, ÑимулируетÑÑ Ð¿ÐµÑ€Ð¸Ñ„ÐµÑ€Ð¸Ñ
    +
    49 * и на Ñледующем шаге поток возобнавлÑетÑÑ.
    +
    50 *
    +
    51 * ВызываетÑÑ Ð¸Ð· mdlUpdate()
    +
    52 */
    +
    +
    53void MCU_Step_Simulation(SimStruct* S, time_T time)
    +
    54{
    +
    55 MCU_readInputs(S); // Ñчитывание портов
    +
    56
    +
    57 MCU_Periph_Simulation(); // simulate peripheral
    +
    58
    +
    59 ResumeThread(hmcu.hMCUThread);
    +
    60 for (int i = DEKSTOP_CYCLES_FOR_MCU_APP; i > 0; i--)
    +
    61 {
    +
    62 }
    +
    63 SuspendThread(hmcu.hMCUThread);
    +
    64
    +
    65 MCU_writeOutputs(S); // запиÑÑŒ портов (по факту запиÑÑŒ в буфер. запиÑÑŒ в порты в mdlOutputs)
    +
    66}
    +
    +
    67
    +
    68/* SIMULATE MCU PERIPHERAL */
    +
    69/**
    +
    70 * @brief СимулÑÑ†Ð¸Ñ Ð¿ÐµÑ€Ð¸Ñ„ÐµÑ€Ð¸Ð¸ МК
    +
    71 * @details ПользовательÑкий код, который Ñимулирует работу периферии МК.
    +
    72 */
    +
    +
    73void MCU_Periph_Simulation(void)
    +
    74{
    +
    75 SystemClockDouble += SystemClock_step; // emulate core clock
    +
    76 SystemClock = SystemClockDouble;
    +
    77 uwTick = SystemClock / (SystemCoreClock / 1000);
    +
    78
    +
    79 Simulate_TIMs();
    +
    80}
    +
    +
    81
    +
    82/* READ INPUTS S-FUNCTION TO MCU REGS */
    +
    83/**
    +
    84 * @brief Считывание входов S-Function в порты ввода-вывода.
    +
    85 * @param S - указатель на Ñтруктуру S-Function из "simstruc.h"
    +
    86 * @details ПользовательÑкий код, который запиÑывает порты ввода-вывода из входов S-Function.
    +
    87 */
    +
    +
    88void MCU_readInputs(SimStruct* S)
    +
    89{
    +
    90 /* Get S-Function inputs */
    +
    91 real_T* IN = ssGetInputPortRealSignal(S, 0);
    +
    92
    +
    93 SFUNC_to_GPIO(IN);
    +
    94}
    +
    +
    95
    +
    96/* WRITE OUTPUTS BUFFER S-FUNCTION FROM MCU REGS*/
    +
    97/**
    +
    98 * @brief ЗапиÑÑŒ портов ввода-вывода в буфер выхода S-Function
    +
    99 * @param S - указатель на Ñтруктуру S-Function из "simstruc.h"
    +
    100 * @details ПользовательÑкий код, который запиÑывает буфер выходов S-Function из портов ввода-вывода.
    +
    101 */
    +
    +
    102void MCU_writeOutputs(SimStruct* S)
    +
    103{
    +
    104 /* Get S-Function descrete array */
    +
    105 real_T* Out_Buff = ssGetDiscStates(S);
    +
    106
    +
    107 GPIO_to_SFUNC(Out_Buff);
    +
    108}
    +
    +
    109//-----------------CONTROLLER SIMULATE FUNCTIONS---------------//
    +
    110//-------------------------------------------------------------//
    +
    111
    +
    112
    +
    113
    +
    114//-------------------------------------------------------------//
    +
    115//----------------------SIMULINK FUNCTIONS---------------------//
    +
    116/* WRITE OUTPUTS OF S-BLOCK */
    +
    117/**
    +
    118 * @brief Формирование выходов S-Function.
    +
    119 * @param S - указатель на Ñтруктуру S-Function из "simstruc.h"
    +
    120 * @details ПользовательÑкий код, который запиÑывает выходы S-Function из буфера.
    +
    121 */
    +
    +
    122void SIM_writeOutputs(SimStruct* S)
    +
    123{
    +
    124 real_T* GPIO;
    +
    125 real_T* Out_Buff = ssGetDiscStates(S);
    +
    126
    +
    127 //-------------WRITTING GPIOS---------------
    +
    128 for (int j = 0; j < PORT_NUMB; j++)
    +
    129 {
    +
    130 GPIO = ssGetOutputPortRealSignal(S, j);
    +
    131 for (int i = 0; i < PORT_WIDTH; i++)
    +
    132 {
    +
    133 GPIO[i] = Out_Buff[j * PORT_WIDTH + i];
    +
    134 Out_Buff[j * PORT_WIDTH + i] = 0;
    +
    135 }
    +
    136 }
    +
    137 //------------------------------------------
    +
    138}
    +
    +
    139/* MCU WRAPPER DEINITIALIZATION */
    +
    140/**
    +
    141 * @brief Ð˜Ð½Ð¸Ñ†Ð¸Ð°Ð»Ð¸Ð·Ð°Ñ†Ð¸Ñ ÑимулÑции МК.
    +
    142 * @details ПользовательÑкий код, который Ñоздает поток Ð´Ð»Ñ Ð¿Ñ€Ð¸Ð»Ð¾Ð¶ÐµÐ½Ð¸Ñ ÐœÐš
    +
    143 и наÑтраивает ÑимулÑтор МК Ð´Ð»Ñ ÑимулÑции.
    +
    144 */
    +
    +
    145void SIM_Initialize_Simulation(void)
    +
    146{
    +
    147 // Ð¸Ð½Ð¸Ñ†Ð¸Ð°Ð»Ð¸Ð·Ð°Ñ†Ð¸Ñ Ð¿Ð¾Ñ‚Ð¾ÐºÐ°, который будет выполнÑÑ‚ÑŒ код МК
    +
    148 hmcu.hMCUThread = (HANDLE)CreateThread(NULL, 0, MCU_App_Thread, 0, CREATE_SUSPENDED, &hmcu.idMCUThread);
    +
    149
    +
    150
    +
    151 /* user initialization */
    +
    152 Initialize_Periph_Sim();
    +
    153
    +
    154 /* wrapper initialization */
    +
    155 SystemClock_step = SystemCoreClock * hmcu.SIM_Sample_Time; // set system clock step
    +
    156}
    +
    +
    157/* MCU WRAPPER DEINITIALIZATION */
    +
    158/**
    +
    159 * @brief Ð”ÐµÐ¸Ð½Ð¸Ñ†Ð¸Ð°Ð»Ð¸Ð·Ð°Ñ†Ð¸Ñ ÑимулÑции МК.
    +
    160 * @details ПользовательÑкий код, который будет очищать вÑе Ñтруктуры поÑле Ð¾ÐºÐ¾Ð½Ñ‡Ð°Ð½Ð¸Ñ ÑимулÑции.
    +
    161 */
    +
    +
    162void SIM_deInitialize_Simulation(void)
    +
    163{
    +
    164 // simulate structures of peripheral deinitialization
    +
    165 deInitialize_Periph_Sim();
    +
    166 // mcu peripheral memory deinitialization
    +
    167 deInitialize_MCU();
    +
    168}
    +
    +
    169//-------------------------------------------------------------//
    +
    SFUNC_to_GPIO
    void SFUNC_to_GPIO(real_T *in)
    Считывание входов S-Function в МК.
    Definition stm32f4xx_matlab_gpio.c:49
    +
    GPIO_to_SFUNC
    void GPIO_to_SFUNC(real_T *out_buff)
    ЗапиÑÑŒ буфера выходов S-Function из GPIO.
    Definition stm32f4xx_matlab_gpio.c:20
    +
    Initialize_Periph_Sim
    void Initialize_Periph_Sim(void)
    Ð˜Ð½Ð¸Ñ†Ð¸Ð°Ð»Ð¸Ð·Ð°Ñ†Ð¸Ñ Ð¿ÐµÑ€Ð¸Ñ„ÐµÑ€Ð¸Ð¸ ÑимулÑтора МК.
    Definition stm32f4xx_matlab_conf.c:23
    +
    MCU_readInputs
    void MCU_readInputs(SimStruct *S)
    Считывание входов S-Function в порты ввода-вывода.
    Definition mcu_wrapper.c:88
    +
    SIM_Initialize_Simulation
    void SIM_Initialize_Simulation(void)
    Ð˜Ð½Ð¸Ñ†Ð¸Ð°Ð»Ð¸Ð·Ð°Ñ†Ð¸Ñ ÑимулÑции МК.
    Definition mcu_wrapper.c:145
    +
    SIM_deInitialize_Simulation
    void SIM_deInitialize_Simulation(void)
    Ð”ÐµÐ¸Ð½Ð¸Ñ†Ð¸Ð°Ð»Ð¸Ð·Ð°Ñ†Ð¸Ñ ÑимулÑции МК.
    Definition mcu_wrapper.c:162
    +
    HANDLE
    void * HANDLE
    MCU handle typedef.
    Definition mcu_wrapper_conf.h:71
    +
    MCU_Periph_Simulation
    void MCU_Periph_Simulation(void)
    СимулÑÑ†Ð¸Ñ Ð¿ÐµÑ€Ð¸Ñ„ÐµÑ€Ð¸Ð¸ МК
    Definition mcu_wrapper.c:73
    +
    MCU_Step_Simulation
    void MCU_Step_Simulation(SimStruct *S, time_T time)
    СимулÑÑ†Ð¸Ñ ÐœÐš на один такт ÑимулÑции.
    Definition mcu_wrapper.c:53
    +
    MCU_writeOutputs
    void MCU_writeOutputs(SimStruct *S)
    ЗапиÑÑŒ портов ввода-вывода в буфер выхода S-Function.
    Definition mcu_wrapper.c:102
    +
    Simulate_TIMs
    void Simulate_TIMs(void)
    СимулÑÑ†Ð¸Ñ Ð²Ñ‹Ð±Ñ€Ð°Ð½Ð½Ñ‹Ñ… таймеров.
    Definition stm32f4xx_matlab_tim.c:521
    +
    SystemClock
    uint64_t SystemClock
    Счетчик тактов Ð´Ð»Ñ ÑимулÑции ÑиÑтемных тиков (в целочиÑленном формате)
    Definition mcu_wrapper.c:19
    +
    hmcu
    SIM__MCUHandleTypeDef hmcu
    Хендл Ð´Ð»Ñ ÑƒÐ¿Ñ€Ð°Ð²Ð»ÐµÐ½Ð¸Ñ Ð¿Ð¾Ñ‚Ð¾ÐºÐ¾Ð¼ программы МК
    Definition mcu_wrapper.c:16
    +
    PORT_WIDTH
    #define PORT_WIDTH
    width of one port
    Definition mcu_wrapper_conf.h:50
    +
    CREATE_SUSPENDED
    #define CREATE_SUSPENDED
    define from WinBase.h. We dont wanna include "Windows.h" or smth like this, because of HAL there are ...
    Definition mcu_wrapper_conf.h:47
    +
    PORT_NUMB
    #define PORT_NUMB
    amount of ports
    Definition mcu_wrapper_conf.h:51
    +
    SystemClock_step
    double SystemClock_step
    Шаг тиков Ð´Ð»Ñ Ð¸Ñ… ÑимулÑции, в формате double.
    Definition mcu_wrapper.c:20
    +
    SystemClockDouble
    double SystemClockDouble
    Счетчик в формате double Ð´Ð»Ñ Ñ‚Ð¾Ñ‡Ð½Ð¾Ð¹ ÑимулÑции ÑиÑтемных тиков С промежуточными значений
    Definition mcu_wrapper.c:18
    +
    DEKSTOP_CYCLES_FOR_MCU_APP
    #define DEKSTOP_CYCLES_FOR_MCU_APP
    number of for() cycles after which MCU thread would be suspended
    Definition mcu_wrapper_conf.h:49
    +
    MCU_App_Thread
    unsigned __stdcall MCU_App_Thread(void)
    Поток Ð¿Ñ€Ð¸Ð»Ð¾Ð¶ÐµÐ½Ð¸Ñ ÐœÐš.
    Definition mcu_wrapper.c:37
    +
    SIM_writeOutputs
    void SIM_writeOutputs(SimStruct *S)
    Формирование выходов S-Function.
    Definition mcu_wrapper.c:122
    +
    main
    int main(void)
    Ð“Ð»Ð°Ð²Ð½Ð°Ñ Ñ„ÑƒÐ½ÐºÑ†Ð¸Ñ Ð¿Ñ€Ð¸Ð»Ð¾Ð¶ÐµÐ½Ð¸Ñ ÐœÐš.
    +
    mcu_wrapper_conf.h
    Заголовочный файл Ð´Ð»Ñ Ð¾Ð±Ð¾Ð»Ð¾Ñ‡ÐºÐ¸ МК.
    +
    deInitialize_MCU
    void deInitialize_MCU(void)
    Ð”ÐµÐ¸Ð½Ð¸Ñ†Ð¸Ð°Ð»Ð¸Ð·Ð°Ñ†Ð¸Ñ ÑимулÑтора МК.
    Definition stm32f4xx_matlab_conf.c:40
    +
    deInitialize_Periph_Sim
    void deInitialize_Periph_Sim(void)
    Ð”ÐµÐ¸Ð½Ð¸Ñ†Ð¸Ð°Ð»Ð¸Ð·Ð°Ñ†Ð¸Ñ Ð¿ÐµÑ€Ð¸Ñ„ÐµÑ€Ð¸Ð¸ ÑимулÑтора МК.
    Definition stm32f4xx_matlab_conf.c:31
    +
    SIM__MCUHandleTypeDef
    MCU handle Structure definition.
    Definition mcu_wrapper_conf.h:77
    +
    SIM__MCUHandleTypeDef::idMCUThread
    uint32_t idMCUThread
    id потока МК (unused)
    Definition mcu_wrapper_conf.h:80
    +
    SIM__MCUHandleTypeDef::SIM_Sample_Time
    double SIM_Sample_Time
    sample time of simulation
    Definition mcu_wrapper_conf.h:83
    +
    SIM__MCUHandleTypeDef::hMCUThread
    HANDLE hMCUThread
    Хендл Ð´Ð»Ñ Ð¿Ð¾Ñ‚Ð¾ÐºÐ° МК
    Definition mcu_wrapper_conf.h:79
    +
    + +
    +Generated by doxygen 1.10.0 +
    + + diff --git a/DOCS/html/mcu__wrapper__conf_8h.html b/DOCS/html/mcu__wrapper__conf_8h.html index 6839b40..5338136 100644 --- a/DOCS/html/mcu__wrapper__conf_8h.html +++ b/DOCS/html/mcu__wrapper__conf_8h.html @@ -14,6 +14,7 @@ + @@ -77,10 +78,16 @@ $(function() {
    Data Structures | -Macros
    +Macros | +Typedefs | +Functions | +Variables
    mcu_wrapper_conf.h File Reference
    + +

    Заголовочный файл Ð´Ð»Ñ Ð¾Ð±Ð¾Ð»Ð¾Ñ‡ÐºÐ¸ МК. +More...

    #include "stm32f4xx_matlab_conf.h"
    #include "simstruc.h"
    #include <process.h>
    @@ -91,18 +98,18 @@ $(function() { @@ -187,454 +194,61 @@ Macros #define DISC_STATES_WIDTH   PORT_WIDTH*PORT_NUMB  width of discrete states array
      -#define while(_expression_)   sim_while(_expression_) - Redefine C while statement with sim_while() macro.
    -  -#define sim_while(_expression_)   while((_expression_)&&(hmcu.MCU_Stop == 0)) - While statement for emulate MCU code in Simulink.
    -  -#define native_while(_expression_)   for(; (_expression_); ) - Default/Native C while statement.
    -  +#define while(_expression_)   sim_while(_expression_) + Redefine C while statement with sim_while() macro.
    +  +#define sim_while(_expression_)   while((_expression_)&&(hmcu.fMCU_Stop == 0)) + While statement for emulate MCU code in Simulink.
    +  +#define native_while(_expression_)   for(; (_expression_); ) + Default/Native C while statement.
    +  + + - - - - - - - - - - - - - - - - - - - - - +

    +Typedefs

    typedef void * HANDLE
     MCU handle typedef.
     
    SIM__MCUHandleTypeDef hmcu
     extern Ð´Ð»Ñ Ð²Ð¸Ð´Ð¸Ð¼Ð¾Ñти переменной во вÑех файлах
     
    void MCU_Step_Simulation (SimStruct *S, time_T time)
     Read from simulink S-Block Inputs and write to MCU I/O ports.
     
    void MCU_Periph_Simulation (void)
     Simulate peripheral of MCU.
     
    void SIM_Initialize_Simulation (void)
     Initialize structures and variables for simulating MCU.
     
    void SIM_deInitialize_Simulation (void)
     Deinitialize structures and variables for simulating MCU.
     
    void MCU_readInputs (real_T *in)
     
    void MCU_writeOutputs (real_T *disc)
     
    void SIM_writeOutput (SimStruct *S)
     
    + + + + + + + + + + + + + + + + + + + + + +

    +Functions

    void MCU_Step_Simulation (SimStruct *S, time_T time)
     Ð¡Ð¸Ð¼ÑƒÐ»ÑÑ†Ð¸Ñ ÐœÐš на один такт ÑимулÑции.
     
    void MCU_Periph_Simulation (void)
     Ð¡Ð¸Ð¼ÑƒÐ»ÑÑ†Ð¸Ñ Ð¿ÐµÑ€Ð¸Ñ„ÐµÑ€Ð¸Ð¸ МК
     
    void SIM_Initialize_Simulation (void)
     Ð˜Ð½Ð¸Ñ†Ð¸Ð°Ð»Ð¸Ð·Ð°Ñ†Ð¸Ñ ÑимулÑции МК.
     
    void SIM_deInitialize_Simulation (void)
     Ð”ÐµÐ¸Ð½Ð¸Ñ†Ð¸Ð°Ð»Ð¸Ð·Ð°Ñ†Ð¸Ñ ÑимулÑции МК.
     
    void MCU_readInputs (SimStruct *S)
     Ð¡Ñ‡Ð¸Ñ‚ывание входов S-Function в порты ввода-вывода.
     
    void MCU_writeOutputs (SimStruct *S)
     Ð—апиÑÑŒ портов ввода-вывода в буфер выхода S-Function.
     
    void SIM_writeOutput (SimStruct *S)
     
    + + + +

    +Variables

    SIM__MCUHandleTypeDef hmcu
     Ð¥ÐµÐ½Ð´Ð» Ð´Ð»Ñ ÑƒÐ¿Ñ€Ð°Ð²Ð»ÐµÐ½Ð¸Ñ Ð¿Ð¾Ñ‚Ð¾ÐºÐ¾Ð¼ программы МК
     
    -

    Macro Definition Documentation

    - -

    ◆ while

    +

    Detailed Description

    +

    Заголовочный файл Ð´Ð»Ñ Ð¾Ð±Ð¾Ð»Ð¾Ñ‡ÐºÐ¸ МК.

    +

    Главный заголовочный файл Ð´Ð»Ñ Ð¼Ð°Ñ‚Ð»Ð°Ð±Ð°. Включает дейфайны Ð´Ð»Ñ S-Function, объÑвлÑет базовые функции Ð´Ð»Ñ ÑимулÑции МК и подключает базовые библиотеки:

      +
    • Ð´Ð»Ñ ÑимулÑции "stm32fxxx_matlab_conf.h"
      • +
    • Ð´Ð»Ñ S-Function "simstruc.h"
      • +
    • Ð´Ð»Ñ Ð¿Ð¾Ñ‚Ð¾ÐºÐ¾Ð² <process.h>
      • +
    -
    -
    - - - - - - - -
    #define while( _expression_)   sim_while(_expression_)
    -
    - -

    Redefine C while statement with sim_while() macro.

    -
    Parameters
    - - -
    _expression_- expression for while.
    -
    -
    -

    Это while который будет иÑпользоватьÑÑ Ð² Ñимулинке sim_while Ð´Ð»Ñ Ð¿Ð¾Ð´Ñ€Ð¾Ð±Ð½Ð¾Ñтей.

    - -
    -
    - -

    ◆ sim_while

    - -
    -
    - - - - - - - -
    #define sim_while( _expression_)   while((_expression_)&&(hmcu.MCU_Stop == 0))
    -
    - -

    While statement for emulate MCU code in Simulink.

    -
    Parameters
    - - -
    _expression_- expression for while.
    -
    -
    -

    Данный while необходим, чтобы в конце ÑимулÑции, завершить поток МК: При выÑтавлении флага Ð¾ÐºÐ¾Ð½Ñ‡Ð°Ð½Ð¸Ñ ÑимулÑции, вÑе while будут пропуÑкатьÑÑ Ð¸ поток Ñможет дойти до конца функции main и завершить ÑебÑ.

    - -
    -
    - -

    ◆ native_while

    - -
    -
    - - - - - - - -
    #define native_while( _expression_)   for(; (_expression_); )
    -
    - -

    Default/Native C while statement.

    -
    Parameters
    - - -
    _expression_- expression for while.
    -
    -
    -

    Данный while - аналог обычного while, без дополнительного функционала.

    - -
    -
    -

    Function Documentation

    - -

    ◆ MCU_Step_Simulation()

    - -
    -
    - - - - - - - - - - - -
    void MCU_Step_Simulation (SimStruct * S,
    time_T time )
    -
    - -

    Read from simulink S-Block Inputs and write to MCU I/O ports.

    -

    SIMULATE MCU FOR ONE SIMULATION STEP

    Parameters
    - - -
    time- current time of simulation (in second).
    -
    -
    -

    ЗапуÑкает поток, который выполнÑет код МК и управлÑет ходом потока: ЕÑли прошел таймаут, поток прерываетÑÑ, ÑимулируетÑÑ Ð¿ÐµÑ€Ð¸Ñ„ÐµÑ€Ð¸Ñ Ð¸ на Ñледующем шаге поток возобнавлÑетÑÑ.

    -
    - + Here is the call graph for this function:
    -
    -
    - - -
    -
    - -

    ◆ MCU_Periph_Simulation()

    - -
    -
    - - - - - - - -
    void MCU_Periph_Simulation (void )
    -
    - -

    Simulate peripheral of MCU.

    -

    SIMULATE MCU PERIPHERAL

    -

    ПользовательÑкий код, который Ñимулирует работу периферии МК.

    -
    - + Here is the call graph for this function:
    -
    -
    - - -
    -
    - -

    ◆ SIM_Initialize_Simulation()

    - -
    -
    - - - - - - - -
    void SIM_Initialize_Simulation (void )
    -
    - -

    Initialize structures and variables for simulating MCU.

    -

    MCU WRAPPER DEINITIALIZATION

    -

    ПользовательÑкий код, который будет наÑтраивать вÑе Ñтруктуры Ð´Ð»Ñ ÑимулÑции.

    -
    - + Here is the call graph for this function:
    -
    -
    - - -
    -
    - -

    ◆ SIM_deInitialize_Simulation()

    - -
    -
    - - - - - - - -
    void SIM_deInitialize_Simulation (void )
    -
    - -

    Deinitialize structures and variables for simulating MCU.

    -

    MCU WRAPPER DEINITIALIZATION

    -

    ПользовательÑкий код, который будет очищать вÑе Ñтруктуры поÑле Ð¾ÐºÐ¾Ð½Ñ‡Ð°Ð½Ð¸Ñ ÑимулÑции.

    -
    - + Here is the call graph for this function:
    -
    -
    - - -
    -
    - -

    ◆ MCU_readInputs()

    - -
    -
    - - - - - - - -
    void MCU_readInputs (real_T * in)
    -
    - -
    -
    - -

    ◆ MCU_writeOutputs()

    - -
    -
    - - - - - - - -
    void MCU_writeOutputs (real_T * disc)
    -
    - -
    -
    - -

    ◆ SIM_writeOutput()

    - -
    -
    - - - - - - - -
    void SIM_writeOutput (SimStruct * S)
    -
    - -
    -
    -

    Variable Documentation

    - -

    ◆ hmcu

    - -
    -
    - - - - - -
    - - - - -
    SIM__MCUHandleTypeDef hmcu
    -     		-extern
    -
    - -

    extern Ð´Ð»Ñ Ð²Ð¸Ð´Ð¸Ð¼Ð¾Ñти переменной во вÑех файлах

    - -
    -
    -
    +

    Definition in file mcu_wrapper_conf.h.

    +
    Generated by doxygen 1.10.0 diff --git a/DOCS/html/mcu__wrapper__conf_8h__dep__incl.map b/DOCS/html/mcu__wrapper__conf_8h__dep__incl.map index e39ed17..ca2c6e4 100644 --- a/DOCS/html/mcu__wrapper__conf_8h__dep__incl.map +++ b/DOCS/html/mcu__wrapper__conf_8h__dep__incl.map @@ -1,24 +1,24 @@ - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + diff --git a/DOCS/html/mcu__wrapper__conf_8h__dep__incl.md5 b/DOCS/html/mcu__wrapper__conf_8h__dep__incl.md5 index 470efcc..95f2682 100644 --- a/DOCS/html/mcu__wrapper__conf_8h__dep__incl.md5 +++ b/DOCS/html/mcu__wrapper__conf_8h__dep__incl.md5 @@ -1 +1 @@ -bfaa42be625452a91c183f48d5d13387 \ No newline at end of file +8ccf91aa945ca964d1a32efcb11d9fa5 \ No newline at end of file diff --git a/DOCS/html/mcu__wrapper__conf_8h__dep__incl.png b/DOCS/html/mcu__wrapper__conf_8h__dep__incl.png index c8bc0dc73dd8ee402b647b1f6154a384499de518..aa263283ec9714e56289fad4e34c0a40cd492820 100644 GIT binary patch literal 33303 zcmb5W1yq#p7Y0Zpf*>73gMiY_&?O8YAR;2&-Q6WhHww~H(jeU>IP}on-7Q`F4gUVS zd(Q6Jb9OjqW|;WC``-7)bDw*^34N<1`|K&%Qv?KrXL1nfcL)fm-3SPXLQl|uSGIi( z7l8*fLj_rBga`QFkLJ911O#dXIcbUa?x}n8Uf$X+X%EMfn{VP06zoEna;vIPpN4A7 z7dScX7S@Tt)9;4abB0lN#>W(v>@3S^T&l}jA6JJqEkI((7;7unbGi>g|tMox)>Hj}B zWBT%Z%;&hcxIMDf)z!qG4cr~aTte0w*8396!Wz(kH*jMY2&8rVLqb9zqE9=HG`SmD zb_AtQ{E-~tZ}w$ z5{UKxdma)JA^-0P|D-m4|4y8Z_W!(P$Nf7E{8YHOq~8c)!vD{2cIUr;?t%#aXtson zjZJjzqJ76R3z5>ibxSKNbZ0NUSx8?(tMy_WxuEl4A($cSc^Y?v`d+oNPd|%BR3HL^Yz7jAyFI3_oN^R9xs zTLlzy4YQyfUz3JEih{cbFOSq?*x~YXx&J4A&szrA9@+PEq8x1cVnu#(Dr-o}{*Wv6 zt}-JF)t&>n?T*Bwa^wEnHDhrbwF*+GY1a6gi-ea+9N!BeA1(pF};D5%Aqt8cM=+>q@ghHV1iSr6xS6{6hcx%D`w_Vv?XbSFK(o6$*! zz1?yV#S`%JY3SN%Y1UXz@5se7=c>04lEMie)#;j6BFW?VxDM&8oPP@nO8eySxP%^5%X0Xa|GWLa8yr?PY++WVOl;O= zEybEL8s>6Q8<~DkR#GBz8-HLlGM(_aJo=Z^#BgO8)f0T)c*i=;HReMO`Jtnw)%T2l z&i>Mjhg=VS%Gl+fk1`m4cScL+^29n{Y|86;Ne}-jZjUhP8e9_Gtr^#BtF37*p~!Si zo1D=Gx-=pR(TMDb}@+_kKg|)qyYhb zqTxa-jv3Nq*Sp5Nhl6W3v#A*^^O@OI&skr=5<$i_0ieUvyfLFUmX*8v)9Kfr9{qKV{ok^{rFndm)85*CS>`XfQnQQEJ?FBD6(6@N zNao+>Rj|ZonvT)+I2ly^wV&Yl-XksKcX4L7p!aa;%y>$^laui%Xm;9vr>!fc*%C(@ zcBY(knGTp38C|Wwg_#zXC@6RRXkEV+T9~#5#~(CgTYAyKzsH65@n0xf%QoptC`sqB z7%|~CgGDqD#HRiQ!dAJ{rqa&t?pe}f;BrjREPmYC$Gh(Q93p1;K^#Bou|g`w8|cDp z9xXNGzgW0U8z!zvQ}_5`>DT|oxV4Df-McF4HKahdM$U}DeyiJG6d?_4@Qor(`Y)V8 z=q)EMheK&M$h1Sa2bU!!qmU)r2EbE4>>rJ`0`ku#r1NXS2dU1m(n=u5K+GFxsWMu`I;r$mzZAxNxCqb<9!VQ5Oes^bt8A~S1z_9e5)TA#ipuiH&>PYg?hmYHw{O#SyEy01 zuznr{ST~mOv22@bo2P*K_Gp8hIPXFBKeAi9G$2^n4TU{=g_b81I}D3&>tS~JmM4Si zC8uG%E~2fD*@O8-PCh^3ijI{~eGCPpE|OEkfjey&BGl$MKOED~52NaD7JO)!2O6l78Po;ygL6YCp5Mm{gj#yV^)q z+2Yx-IpWYiu^Qy~rt;Y2wN#SGlUtW{nTN1HSG4voo{z9H@pA+|XsFn>9=1ecvsH%`UpG+pZFFbV>l`deUkJr88Wkx+|o#oB9|3aCV$3OtQK-E$Xd&lb}$zTs}k zhMQL$@uM+!=T~}$z9>xgCbrkaaihZ6j`-g3MxRVyfHPW3EuMd-B%`O`LPg3VfHQTs z-$gL0Bd>hS6`?Po^t24!zJxRly)fU2RQXq9URSBE;eK1xm~wP!!#JZ00au5Vss0-@ zB@|PH+%~KTxdRS90rDS*obC+Ht{-1P+@_>x26=pA(!P7x&EmmTdizb4Y7ZV-g2G8J zJi6Z$KY%s*F@7U(Z~6ug@+Hhd;Q?S{E9;(8kj2xoAQmIrW<-&q%e+|IywP8I()#F- z9`Bao?dn_erSjV2e*MXtjKrBfafO{t#RS`vP*n7!9mG-lpGlmAW}3=2+J%#+4g6P1 z`n5uhf&TNKg>iqEenN6pW?Leyb^ye|?NR>c6P>%{a%6%p(Eeb*IOuokC@Di1)Te*q z&gZ}TbFL?>K@hW2#Ym4;9Bt&Lz7~Vr%j;I(OCRU&@pf}l@?f>*mW*fwyj*(PaGPj2Ua@{RA&u^ptCUPqoyHjcTszJpdzYF<`sJDy5koUftyhEh+w3QY?LfqCMRRST^xsW629T5- z1ir*eLv+*3aRCBiyqb@I4u`>YW$PQhq zWq5YYr!Rq3OT=O%r_U6Ynsk-c|Km-BClN(gyZiqIFPeQf@;|Q2Qh2e922zhN(2sA> ze;(!hndH<&I?mj?4_z)6QEfPr5aU9kU`XMdPs@H6Ub8AZ4&Iq#8Gj&8&-AC*34p_{ zI1#c(_ysP2tKh=1;ssOtOEh`^6-FF~pY6j1f6h^4thTDiie1g0;R}CG^%{bl*O#{iSU`$M+qM?V}1AbfvjS$=%yj zL-7b9x)pTw5pkU8D*KnbMz7wAlNTm~I|cn3to)-YJCIyIL(`$*Hbc!baQrDF z^q8da3aloszXu}b1r@|DQNE2(jdPFHK;xv2s+EfHAhaQ>j6l9_RIC3b4{1Z zLyToW608&u5ViaZNu zbI$%XYlHsb>&Xzud$Q0Lq`%1}x+H#~wP>(V5!5Y`(YeqhAY4#&di=~o5P9NWd`~;e zf9u5vS0dGzAza#^Kk#I7P8%kYBj9i77RCuf`1z9vEL|aXDJ2eqxgymZE_Trs=(drn zH^WjS^M;n3o`qY_ic_Yr13)8dr20?q$l~QJCQ{2Pv}<1OJMQk`aeCmteHZIUC2r<^% zaXFtH-}Od?K8-`P&7i3VJ1l)EWDqOOoYN%>;yRVLTv?I@&h0p$Np)(8%ZMvBci|mG z%KfAs;nIo!CwfpM6^@!>dTMQ^)0&4Ry&&q|_l6`L7Z)Pz&6ZF=DlEoGI4q5oD41Tt z{~e<$mDl-WDzh^#`*&WvceKM3ck=9U$r*A@^u`Hs)O>8CV3zlQ#DBn6TxS(!V=@$kI`aeh0>KoC8{!+l$xyvz zMb9YWORgNWwXyeP`Pe8`r{IS!uxa#mj}SRlG#B^tAvz`MjQ@vJ3c8n14kM8qV_VLM zV%&giuIk{6;{CkCdzs7rf?}jB4?dAB{`F6Oe|X%s{1fU}w0BtkZP%v) z>}0NP*>V7l# z+>xLfK-}G1+3*s>__Jn1490|WUd*q%3W_|Apd-tHDPe9>g{MCAy^R?{#O}->167mtp z-=*?1W%njJBRzTd;qot{H%2ec=gv26CJ!@u#yp*%7?lhsw;gmf13`ol7`IYd#wxAt1G*UIXs3MR1Y>Bb&Zj9cB!+ZMMmab~-|P8!E?_Tsg=-Ev3VOyWd0qJ-T9 z)FM%|-Pu}~#|(TytbNGuPp8_tHZi}pnCJRNr;htq)WJMr-UX9|a@iIz_3kHG@MY5v z>MZPa5s;ao(U{e%?m;yYuzu&|z}HQ&DdARwuWLpB-dZw21^;v~I50jFjHHNVwgf6Vp@5a}tkZq9++ltT{g~0*q zMrnwK`of~QA&jTI;>AD?Qm%1|MCB=|>#i{~O#24%L37wJ>gP10V;sQF&* z(Mw@H`i*P2;N$x1t~bV-2A@bNIp~~CDX|CRvj@9!iS`lF?cL|z(KLM7dlK1&Dd=A1 zTi#4GuL}<`Eh=z&B#zOt#?!!?ol)x(9%j-i;vaz*Z7gvH8bU`TGDTmiz*T56vnO0L zJaRKfMb;-ySO*kK9e5;K9Vp>;+Q#h0IZ=_K9V@p&Z?SLbv97FtPNXSV@?DNef6_to ztIe8g0lA1wzpsZC^?!uLUYyv<2r2E^rt3(xaO!`)LuWN)VR-B}P zAP~iwN+obAWfax!txs!@u<6S(-Pe>KIAD1eD|AijBO1B(fSK91bqaf+(rk-5qK@YA zox+x`!-V@u;G>_c{a_Pu5t_|%zNf_ObZ~7PHXYg-A_`1szVR?W!&8vftZM=wsMyw9 z>+R;vrw$)pKpoe6QC;oxXG^DdzJwCjlU)iPeI->dW2#)lc4@9JY?y9cg7F93fO_{+ z^LKk{dQDrQk}Vk%+DNh?ZbGCmwZeP%J)zKVgZKgZpy%kA@dFkjED)J8}rfN%iFipYY&Y6e#dkoE?z4L z8``yond2sgjq0Um7pRD0C`z20dgl~NprXW&x_^r(iwhb2V%8ENC>W-!t(}yibveaF zmgj@d9eo;Tz_3HI-u;zgVm`?+o~uv{BiqCtvCWvvXl-^YglKZW}FCN zQIq+c!yB4(atBIDxg~-;p_8WkkYK;MHr-HrIB!TF{0gQQ4s$Gi+%3^ z(=$dPyOZV(AZvaa%Skfoax4>#*(@7-a?t8{=|Dx-y?Wq`0+m(&I?F0GZwln?U?&kM zqra9Rr>F?ojKzDqBW@81t(`$v{+8j7rh4I3`3CRC_Z~t{FLI7sM0pl`jFRSgu}mT% zyjsm1xA zqAe3$RD`QlLoYd*T$#$(a<3VG63L-04_PMM>KM;GWOI3m_BOn5dX;jUijWX=#2L8C zsS8bNOOcIrLl{K+W$#g6jqTDnK5(CS;Ee+z(M}6(6VZFmdnJbWK+N=J{;#xDeHxyI zL`N}DW=Eca_v|r44_4ZOf*iGYQe7g^6ee#hI5#D6>W3mQr#Z{VU~a+yubY-M(=)DwNb$ z23HcyYwhqt&-k^%L=Hn#(NPRD#|EM@l34f`7Mw_@-~M{Zt;;^@(0wvF;1dfGGU1xeog=tSqm>MOBKONO{Y{{EM;K|&I zy{Zvut&7r%I>v{ zcY$o3XXY;@jOu;ZvMPcy8rAH6v`dvPK@^_&V@D7IdC%y|6&cTv#Iha=Z$+Q4B((1_QyKx-7C9ehxU(3IB9qhV3EHVexsk0j%hV{ z!LwTx#XSm=b#u$|fvXM&zx-3e!Y(!J0%XnvA6n3FpG6sYmuB|gyD;&N6`v(JWG_Tq zG#qzeUyclzobSAyNGf}ka_1$G!NauUI*EC6;k2^zA|WK_*OT|fCsUUWw~3@w+gzN* zLjAS?fAA`$iO1hgC^h`Jh{QX$rJpjaYD*>Gv01qW3dvHJ{rjgYuAozg%BsIo6G~_yb{6#AwfMIz-_$C>>+8f%-gB zxU5<$;3|+u-cu$Gz9DYpqbw4kU;2;z4O8)!u;Q{C&XJ?z$cM*QhIVK!=Igq3Ln>@T zl>k3BgPI(8<9&Z7YzXtiJz6C+si|!3(wkn}B(?s1Sp?j^dmm#ic7P#s#DZt=Y6v*Ki%mHBQkDC|XH!g2WiFjOdl7YE;}HK)<(SD~q& zq8oHt17u=?ERdiL+n%Ahh|xJPvb&aLxoa>58cxb_h)}e?@Vh5C7NYoo)wVz8Ou89( z!63yc-~WA8saygBYQ1C*FKQxd+TtbL^{djH8D|M4yLqjA`mH$G(Ac`JxR-dBCg-*C zbBY?K^YZY2UYJhX-Tvi(%Ex6ZwtAkBvgsqDnpBYJ^woBExBD@hlTUd# zTtWu@-0sS+c*FwM5?$SdZbdh&Uy}C`ot03g38EvTv@eTpa=%lDrom!e6?!fthAayZ zL^x*74>mK0$HL@+77`=eYv~W)19ay`KfG#&peeyw)buypsU($qlR9BJ2PtoulTRAR{Fb=%%I*&Z>UiyUCk=n zp;3~)UaAFmFIV2Zkc4N~-}I)Q-7Kl20|N7DqjEK0cT@FpDct)bg6BOtmkcCph=YW0 z;WW~)8qm1m@`h(y2&@oZn4y^EG4u+9R#{TrVz4?T_47zC8c+R6aXzNrT(tDAl3~2q z-kOkHr)y(AC`PiiWijg$*UC2@i&a@&M08C#4uywz4H0mD;q*g9%)`Ovyfyh|;xo+s z?2h*z7K#9fbWD7e57ztheFY|O=v{Jb=*6%zljAlHy0b}N(xGR(V|f8qmyEHjEXOqp z2c_7uR5H@BsX2B&R@q2Obl^69BIq`K$Eil!M}*+bXEPj>Xq3=tTWE*s!4gJw7Cw+2 zq~X~?dT{=gosl3#Dt;T-HdTs?AR}FK#bim;iSkJ#`dr;ZKCPz9%X%ysm&!qm<)==f zXylXAlDR(u^)@8?(wI~3*4iu(h)8ZvTkgCSv!RQ{4LyF#zj78)( zL?@076s7Wx`nKbO*XIIN&S^YO9;7z0Q5)Zy-2RY>75s|ngPaqJfu^u;1!9-F>Ip8@ z_^$8*sSpQ|6aegbkZ;wi_HEZ&G=Y45sz+aH>o%UW)~&gj8cMaxUg6WBwcI^K`n6FN zJ;E(J^GVA+9INci(EAjm|0PE0`Q@F?ILjA_c&^`*z_MXI{9u>MuE2lQ`N`GP^Lr}w z7;>0{X^geoq=%@lQJGWrfKe46z=3+&h60q>VMpY$ zR7FtqHIostB~>`bM@Lc^mxI(vzK&LZ>6M%%ck$6tD?Z7FDlTblc$3xD&)3P*rK6V? z_RKG{gZgaL#;PND;6<7=O`kt|jJ4Al)oX{A63RbU1*VZy6zogF3QD&cVVr|$+5Vg4 z_vXK*BO+A~^iwn~Abvp6LgQy>D!kTDt)C!N2|53hf%@hRYt7=aL0~XBB@!jJVHIk; zd$Dh+i}Z)4kdP;jPLI69=g~eI{GCwn588`N&Mtknqw_IZFDy-|>}Po|&{(}LPGda3 zDDXL3WS&g6p#&-(j2()#vDQx&<~TMFR>x!@;?Eb@YMZx4HT?9>^%uTjvpY8mOSKGU zCnZO{<=_mmE78{X$}UwzE3=I!79NLz)5#2?RG+>piWu-uz{rkEcAX|t5Y)48@(Eq<#09r0;UXZt>Fib;2 z+~LU!BCakZm_nrRE&}BX@T(@m?2_jPBe|DxHse-4Vd&oE`AAC0GyW;X{@L@t#^NWjwp*$GZH?AW2S!y4JC|qv*SrDdqk2Qg~_OcFAS)I)km^PGyooO8t?# z=-xwV>Wa8PJPla&_rY$(S#l$3ovn@bIy0%olKJyW%<{H8RiZ74zKlb-14s=FZ=ZY? zXq*Ew$-clWg(gmraL#E2(11;b_ujYF);%+`6L zT2~p~b$?qcdLDl3gO9AAAC<2Y&o-+}^1NfBj)oC}?pR+_Xs<%e{G}d~$xTt>)Gna? zX_fk6GZYMY3V8>jm{jWk}Oj;>S;jfKwR z$^~Svn(1KFQgs9;67ZqN6#Vzlr68Z1`VVC#{qMvno0EBcy|ZEl5hvZbSeivSgATWM zvSQ1$^zRXuSlbW-8wtKE@TrxZy)d+N1TcqK+~OU6(MTlIMkh)RAr9c--Od4HfX#+A=CbJ1dSyCm`b6iNx18C~ z<-j&4+u{loW;i0u-vxyLB?d3<31%u@YI4w*^HZP=7)lVc8O1z#trh4$n0##Eri;?z z<=h?Z`>PxKwN45a4(bM8H8bC})>HhiB&o{lb*lR^_ z6Ig+M`C9<=a7jAv6H}5o`MZ&(#x!_EODULz6NEds!IZR_vNd(m&>IIgC6^qzMbQWZ zt-JGxUd^lV-WaBSYpXPX{D}-NX5C4ad4;-GzZpN^D;ey>dQ{uyWa@1sj~fYRm|SeQ zni^0ysOZ7lo4$dKgx~w@;p`ew6*srDJXRQmJPY{RTgEcBxoy?iZanM!69B>z;3^YV z{l_O3qx83b#~1j6y%~G^gA|<-Q4`Xfc^GmWoFc!k981JH5)D^T>{7NkD@WRz)8z)o zni+r|iL**tNvel6p`_o$saxErUCcXvzr6Pxv)j7vM5n z_uOHen|El3UGD50?aLnAw)~st(%lR`nM@tqg<3u%nItbBgHgf7l#Xm_tA*nbM|&VM zd%0P5F|f~och-kMupg6bmy@O$i7ky2%aX8L6q2C7tQ=Y>kUhu+#KS$w6k75D;Ie`t zO5V0!K=jIM?(&6_kx~6Tv5SwCO7lcs-SO$z?%C+G^%`10vB-d8%K+OMKyERX$?Y&| zZEWi;Q*%k!U8{9jZCVw@qL4IB=KRSQV(_ewI zQNDlIT+{e59yvjMCZqz{?M1EO|6TD~+86;2r`AHE%g&CCA}U#@DRWQFh@K;#uL>_A zvI?*U3^&+O;S>XHML^kH;`5sM-sDVem%R3;J+F&F7};`(C8rfbml#J)nuS=vz`~W$ zwxHMxfA(Y*RN=j&{Q|cW{OZZ)5Y&xTfk9-^Ef{+L_Y5-fqdK8lRK!+A`b(P@T?2YL zDRw&8AZnB{Yem-&UY;2w^Jh{sJl_Ey=ZD9mQ1MOBj;+CE68&IbPanUkfjgF_QbYXy z(`WPMPOK5M!av-~e=rgD#I4NlNQmY9W^eeB96|xZSesihBHf(Q$;Y>egy- z@kAh6?z-_j3X!XEFi8hd!_{`SyKkeU4{P{B0W_E(8H5rIPit7e~z( zqp6>oSaCg4AQz~lq= z60<;}!5pf0c4q&Cv`*q$4Ll?vuijB|ET($2k#p-_!~nIYkTr`y`t0tertDaCn6sKk zcr+%|(R1r734vEd*OhjIG8Wm;$n?)#I{lQ=xA?d{EO3%15P*vr@1Ao^#s|1_5hw>O zQ;0MF8jtXT{9=XJ``sCOvG#htt|;&f%#cfMbzYU%e>G$%bGM7(dq4WRMr`N0BDbMu zarGCOJ1jzM6vc7)ow%su`?AwYk)=KXLTo>dP3G$pxe>L|HAaTiE9_iT78E5kUCz2u zgKScex^}-vgQSF`nqqtg3622s6L8-$MVp2xL7wL^qkmTb`kXt$rbOV4QcFCAWe*cA zmjE1XjSMv_K0RU!#D_#;F?xWF!-ZH;9S&4T*s|M46h+H_q`jbYM1=}3yAP~jeP9Ai!Z}tZHGOSgxcw^4)JBPpgXHK-urlPw~XZV zq9N?H^hqGxHf`Z-*JsXJg~6lJMDT%wIp@?Kj7VpNDO>T+tLRA3AW|T6e;roa@&~sa zP+y%5PXx3PXy|!}K>g}eF>X(L+)iFZPW3(mL@hNL@HN=dM)!Vhrm%H;7a6{H4i{Cm zyw?by!M;=|7yFcz^n3K^=Zv^Afa@6UJWfr3RJ&uP8U{NBtg42SC!Ib4nrAjZQINeX zk`e-G0K!mrehtub!oohmR)~6fc>7Xm{w@fE$DxMj>#V}C8Z%zn7>Z{ivO+-Z%A5fr z{}=SDGAPb$Ku8~m4}jK}(ufa%4n$DBB7R3(6>-rMATnH;YNNAoOqs(H6WFW7WB@ZQ zgR=~K)TbP5Ty;!@EJ1A)Xdpc3wfcFv3!E?4De4yg%Qe&F^ls=*07sxIdH83M{%hkZ zI6IInGk})yJlg3)EywMfxXs`EpO?#B5AyY_*=00;K|22pT)Z33{n8uXHfTuGw@W;| zsxrwx2lqRD*0&@<+K#KVR^bf{9(1T{*|H|_iDces#(kBM7?-z^>#oXUE^_w@KDZ6k z4pYfWTncYSuetCPugk|%1DauVgnH;@RY03&}C7`|;4u;(WvC2-ib)9_ll0zL>6 z0r^&YDG(;Wn8wlc{NP$8NrcLxoff=ek4cz~w%O4pu|yP{BBOx$EnRzhZ!_i8D$qRze9` zD4>VacV6Hf!PjU-hTpmv6ql;%oN8WloH*IT(0=9+d9*Kyx*hzf6N_D1P>nM6f)i>V zYeFD0Ks1kSayw%XJ71E3?GpvL>55(kam*RcHD`^bhga#xl8;SG{(+N-LR$F*gvXV` zqV=llf)632Vh)!g!TBVLtR^RsNGHQZ6+H^bmo**rB&}iX>N|aVnSlAl=KfcT9DF7F zD%g~&Fm)QGpU;f1r{!+dU*PEZuV+RnU#!EU*L4-$nQ5=Y zfsJ2db1TvqEUr6c5yz9d}#{@TAx~+H9xy$Fg-LdZer7NiW+F|Uu@`a=1TmQ60P0gtAJo&orL!l4mf5$Ay|s-7 zz-5H>JRmE|oA*LQq|XEyQL1CW|EnzL?dr1BeFk3B6T`PSRi(0>u@k?E+kPW&;bSvM zAbsqG_klHZ3NJ8W-K6SeH@=*n87AQmJooT+JE^+*j>~a?2(}zMTaOD<^Buc9zQtnd zs?RdWEQxAhkc&og+%8mjd+!oQ=jC^RI`;B=>@v^>fCn1eL|2wWI*&g_6%^r4yJL-) zQaWj0a1&p}5yE*3g9=_uyL9{=lT7 z@gY)K)=kw&>%`{()60M9$MKf3(H;=qxR{v;!(5WB)q_SK$sm$kl67$~2dO)DUJuel zePt#vs1R27Cbn3<85>5Y&nG)m*$;F`b(eI7r?XIvW_w->=bXFJa*@O1;;($5H^$m7 zjPu=&#tEX745Xqt|G`3c9p`@huOIc5Bd(|%$roSalqkP-RWk}&_qN)f;Lm4St?>kwObMLY0o~?<^EypPV7pzv* zSqxH}|Cp6=mmH78qBxwTxw7;PTCR_PI*i4~UcIK*1h}TDDG8!Rhc7R@zEfIcRt)jU z>gcs-G{BTYNkIYUQP^znlvi$nfo8O9fc{BiGA2DjUHZ5r7PjJjBgS5xNXMr5xi97J zyW}QP#Gj2@QVzmPe5f5Suq%zalBe};B=0hm8-q3)JT;^};WG=KYH)vBO*H`qKCUdk z(c+~QR*TLWdiSP1U1HKt6Jo|8U*ZR<1}|VUvXf24=$5TH+(oy36ay`C5*I}-U@J|S z{t-N_i1+MopWJc~t)`q2Pq&09;Dd{2w@xl%yh|;e>ml-+gs^$ZQ#Yj7ZKA2@gvsF$ zH@m0ZR#sN*Pdbifn8I*l_b@&!T>}>oEJrOIlzm(;Kkjm@LDdd%3IJ^)=lwkJ#j2Z4 zZL~iSeOdz_gxm49{%?jNW?knw>3o*z;Snj$NH-J$go=vv%eVJI3+ulq%@hq;6aj3#U|vKJ zstfc=X2Jy~r8YbrKVOkA0mOnXLQS%h8;N})*o_y!Bt9j|8Gf%%w19iehQ;SW%RQ#9 z(;k~?{K9IXkcoMxL6Oe}bz}nMF~D3T#xVzJ5J>w;Dh~PXuf<3qEMHTYjzntX4M>eN zXc@JO!fnoEG*5Z(Bt0a;bg<2-DAT|4JMTWrcfK{=gZaip3LzQ2#{Heh`x*{dNt@I@ z^mht-h5C(GM3N#$WnWl$IH{299>@EafhWBT-?cfu^f+aeN_!5^%#cwEI_DF1Py62n zW9|_y%>p0+#|BHi@%T?UG!MWgLgm=LKSHBlsKbW~5FXO5GYh8|muWBuK883r?LF76 zhxtX9|D-lnyrcCJ27+Q%tf1Wk%^5O%E0&E|=iV6o52yJ{E2oyH?!chI(>W7+VrW{s zR$VJVM>>msfa^z9FT-z<0GLuLDH+g|pyg@;t~9~O>j#$?*5Bh(I%bj*GvEQ@G#?O;qmV=$oh%-f-PH*R z3E!j(gB8X@BfRzQPZEW6-D$*rGRb|3UTiVUE@RqRBI9rQ%CuGqOhnG#-CW%RgJ+&& zykXAc!0ZYV4$_0;c!_9%h)e-#ct9Bg(tWjM+ToGEmcv9oVR(dV0lSo6#x>#(z)3Th z*1UsH2f&MwWvg$VJap~?lQ5JKfFV~!>WNrh|LwWHWsWnuzP_Ec0~~x9L-W@1o_>P8XJ@IAW7zYbqEU3zCw){wAnCHeP(}r%Z4HUSeK_ zI@zej>t&F1Tzp{r6;a)U*YkCZzOpD_{9mL05Rqt=1x@sBjYbz3-Ch)!6LiHIDERf( z_`QM-_%3A(CuZ;F&|w3gqe~Ljb(vxhBV@1eGjjeC27v;(ne@fe1C6Va#PG7xNn>AH zE=@H)kC#WUgOz#NDu4oyj`r#WVXF6XZ}t5=^-`s&H?M1mvKsG|TQv5S%H)-Xw4+=h zZ>OEASjM*CFyoP4FgET7{;NX@+iE1=7C43jW`5>|KUxa;Q?x0@qz+x>C#3kcTQuan zHKxbNViT7R3KsJ@Jbl^)fNEfBZ57Km;paIn2VRa^0R%CI`omHv^%zbG6 zJ9x;4@im|N`=evr_x56h4fhR?& zq!M7*fEmxo9Rv*~KX6>N!-Jg{GPIUeOt*TPRA!L7lmJ6MNjVA#z<`W#XQA${DtQaK zcWZh7#A}`C5M%ZKg68ucsGmywt%yNy(67sm%1>F@EsfUG6=4v|SX{HKlXVRbw(*Gx zT_7}7+cm73@yg!M8n&L|5Bi2@+`?Wqoka{1TkBjc07Ko|m}Wf|63?~$I)KY=a9t>X zkx?$Zm=ulZ+D0$U=v@miH)v?z$A&IVaL(ud^U^S`img=6OB=I57%A5~cthK`O|h-= z=Hm3v@n@w^_!HxIkcaxNsE_We11HzNakO9 zBf4(xtLV6ccwP{f!>4U49c11yBaR_rb>M=u8%)1^#@2<2*d8PHdgaZCzZ1M~1%Tf-pFk>Jia%%tv#6tgdtTeEszT-Eor&S?nE)#TH4>_*jRev zj6qN3?+XoR@`o5_=^U!GyAlgm(NmMPZ<|FJKrRskbT)p{g4?OF6pv4I>L2#^Gs{MU$aVP6e2pBu?Oct z4SGo}+Kg!~7tSXmau#bNU?ct639!^AmfWHhq8_s8+qQZ*3E8XZTnd`1aVZ_GR|4#m ze#Gl{fQ=Sh8TNIrM*^E}#GEJnZWq!CkUds%ZzQSq@Y!aS+X9Nk(unW%qgUQMP6%Ica=ID%rfI68-Zs{H2%POFXa-?xfYTVy$mZ*t zGb7ejCgXRVOLsG1E`VaVMz%!^9{#4=uYm{=J?s)qq}5~@CgXd2cJ^oUwe@NtKetmk zkIr0m{7TETWJ=##eN$yxlls0rZ!89^{nE3sRBUn*;L>U1u$vjl|M&kkX@Zs5*?C;3b*jKfNp9Kt zwU+E;a-~Z>gaPa9%k1bXkW-B>w^B2mp!!r93O9@$oA9EMH;-mfvuH~@&uRYgWqv&4 z6L(ip_UtD_XxEv(KX%FTGbsaGK83X;9QxXJON-pyHNxeE(^Iq-9=Km+?I;5pr(ZI^hsqshE#W*mc`tly_& z;c@DnUbXc0VSnDMiNeL_@ZrL2VnMDAFXXdU9a*QPWc5>4U0)mJS1~BLx-%#x=ufBR z2(50# z$%9u$C8*5dE=d|zrUS**x`SPT=o(HpzNRgwcLzy_-kU=B_kwa%Uw3Q09Lxz3t`eX{ z1Cc@a=Dcqt--!%b2FsZfDHN@f4OmsNI|RMU-$(tZks!+0n?18!(EOPlDA7V^;`j$Z$*if_7`+=y_ul`h);#c`RZH=Z z{?2tYsv=UJPDkiwX4`jML1^CwXT|F9Yl^#tsx1@0JL2T$ZaT7VRdE{h=jia`Her{1 zy3XH?QFnk1%*dqg1ZBuPlXM_U%i=q!o}K#Y3XZ6}V~X_Mr|hy-sC3{fW8&}0oNJ;U zJf;P&ah`;rIU*noITZ$ds1M3iL-<=H&>@vGy%f_KLs~5*MnA1uef=;#Dx^p^U_&SJ zHD!W{AHklUtQ!$QT=^wV$q6{<1LDvj*|VM)HF7yy#vUKbF?`;`Ss6hl{^MG$=DQ|4 z5W+~zmaO1t=~0$#M%V?!f-?F8)oTkPsiNq}oU=^AHFOslQ57@l!*tF_dC%z>D;svK z5=oszfMN?_?zKl#`I$#3TgxLfIg>PL>6c8=Wx6|Y-W16^V1t9#JAk>(2#$6fO{rt( zXDr2_S#Lu3nDFZ?Tz{ER<=hZGaF0-{>H0j1eIzmOlu5Zf=Zhe+MxEtvJ+l$J#=ikB ziBrfLUGZOp(;hs+Ua*e21hQ@mo4eJ0<{^8Q4IQzr|1g^$1un^?jT^Esl59RZt@4|f zsn49NYV=J%FC$*t7Nmh6)9Uwq!bfCq60iHrz^Uyyfw*t%VqmZ!a#|s&=6a<@7e4Cd z_EKi)E^A4YjZOB4xqY4;Fvw(Drghc2a{l8A%j9;8Y!cDtM;=XfrBoH^$V@5~V57gL zTwZ#Ky4Nx6v4&!ozf-w;DsdJcBU6Sp=4C_OYxP7$mp|m@J+~!`!v&{pvcstPS)-a~ zWRzQxk#@=XwyVhzDXNMn@Wywk=neLbv-_3o@IxrHlU`Uc_yqVhJkD=ee+QIsf z6gzOQsd0z{?31j{F+~aR(*gf}7XW=t!^Q(?h-@8geI}vLmZ-k!hV6C!^EnF@H25JI9H13%O;ykQ%t8eK}Zw_jhOOHSbJ?!RePxEij zhf#E(`vLDdq@-K?$xT!QBq&#sNn5N`GR zvX3UY-z!Gl%sjO}vO@Q)!ojGZR+o%X^Ici~m=Ib?f|X0tsJ9QpPEDmJz_q^ymN0BR zJ4SkE@;3NGZ2oTkZn9lU1KY!ib6|4b$B~h3Q9jL96*@g45hiqr^eB^bLpjX#pZxZU z-Mj{sHcpD)Q=>rLAi_>pKmKbs#@#=|dpWynZV48yj&n0 zKsX<(gm&^_>rbXy{%+PCj7xDx@cqzRZn#63id>@YlaqD&P&$82Ik#6N*#{2esQBb% z0L=&B2PWd22TU_;P<@m}(v154ZWpg2atIXaMVB7Lj+=k<_mo1DCjCU+`xbe>X@=rO zLfs7s|3IBZ)%Eyi8*9l2jfT@LaC|I6F z<)S=|C;mN0@o>r;WWDh;T<&Wg)H6F2`Cp5~IY287SB122bo}*7Row0ap`y74pGl?rCsuzLGE7i?U^;qcK(cA3J{WqMRyqmUe~UhEY5zZyrV;FYwvL8y5(E#}F_=!# z)BmXPZ-D@xJ`%{p2h^vN6;KNgbSib7n$q~ z*zwFkTBA1K)XNdAGu%7gg#Z@pxt|;(3~L<&?24kQ_iz3;y~=$at)CjXxp zNa}Rxh<(-7e7;B+8RhZytS~VWq|kgeBCx5IJAL4q#WK0$&Pb^B)m@AC=}%lKcKBW< z+ju?idp7xbfA^b}-|^?n16+>JUrpHd?m**&W#R-f8h`*kuqT|e_-%WRV{BJO zmbG6n-B${{m0q1G#`?-kFQ)e)%N`}(7XtPC)HMhh0bbtCo8DEL1#e`Pb!mVpe z7X)up)e7+3jIKNLaiRygBvHek!@KO|HbAQ4?Uk@?HFY=fc^r8p^LKO%gp^Jh_6$A`Olh6c$NGAkTq)SVvfq)7KAp`^xkP?^|{L9R& znYCu(T9QS0_uY5jIs5E$?%6LRG5D1eKJpkF0~^_laS77!L@?KgGLOJp z;}H%p=ZNw^O&v>w-Y}KT-{E#pb+`)Y@y9#2*jt(BvjT*Sq!18r1^+u*Ry$0R||*D-&H6n%%xk%+rsvEH!d5Btvp=H85R z8I;i`mMb$Cv!QoomKNoP&Wt}@#}P90Ee4Y71?tj`@Ec)QYgFY4pXv-l6@8ZKflzzvCNNlg{?BP& z<}N0T&tvUK!7}!N;WbxoeFYN;@EJqW)ueaBjX8CRx~7hmNz!cuY4)P%a+`gd9?f$x z?|27E$ku#d+d~{-%eB5Qj<8(P(D{UYpg9TNFy5F3}t6ArC%ti zR$QGW8TC1qPuOiA}BR*ZkTaf?zo?z-;5mB`{Fc3ta1{xYO1gCaN(d~syVze zr-3|@24~*TPKTBEq9@^mp&s7PLF0!0nBH2*W>(RpC$NtcpHWM>lVDRg&<#;pK8JLo zvL5Jwq-mP2wnsljO1 z>*aG3M(}Q_)yQGrW&mPUOeGep4MiYD6xD3m4a=+rfN1wme{^bt8vjMP(d zg4nM0DX}6;tomHaz2&pUy&~<%ny+a9OG}|I@pi{eN^f0IP0Rb7S)bM-Kb0I{sU0I+ zg$7uvgEGtalXg9H1X0>k?~^d;jmG=$Gpih`CR;3l1Y+9R%6AXQ0f0_y(ISzmdD-~# z9PcfL<%C~-KrDddT$HO9A$CprSfa8hXXkgLz@9!WBRu^|JjimkJ{Muv4>KQ4mp?YT za?#2snYb5Ez^^O@epJkjiP@X|)d#G4=s4c5D&B6vt~@YJRK|hhVbRQKj%}B3n}&C5 z)Ep~+Ciy?qa!~Cxw3^Ot@Oj>xOzyn0&E8N$!w2vsI=>m;RAU<97~$xrc;pQGv=%$W z33>yJ>`G(jG*!yE52iV`&KHic6`CSwo4HE*y0Q_{TxWtewokdoZYtT>d?h4zRa-qe z?4$Y0&>mG1JhE-<tE_>nOtAeE}E`*Xy~lslB^V? zRLC;IK~UJX4!1^SGBwQz)$Fs`!mhYp0)g^xu0}Q;l244|$@-Y+7OOLX==a+a%RM{` zWfs_XNb~C#Mo$(FmtX03^agw8Wnp;II^o@?0<|{-OJ&{_4lK2f+U<|7?y4xzwwm=< zqATV!T1|wGfj~)LX}+6*jfaUzp5y_Stycr3wmHgm#+k_ZvnCkXcj8l}>H?Lc@`XIi z!D>I-dTW(?apu+VsjDMr1er@^Yzqf;BQXLvV*0KNlP{fBNISrMtIgfpFdZv*lz(CEvDkpuCi~M4E;n%ima++4SD$&#uy`V#Oz|N6 z?slRj8K_-hr8cjpTYgjGnK#bubwRt{NW#;=9%x_zBOe`3h4E~+4KEOF(Kc{D*yce4 ziItDfZRfu1cG`5SX3wl|z`OnC^ZFDpcoqm3(yyIZzkTR#rUlTs~Q; zFnBqkaq&UbD3hlT)vA$lQ6|wb@`ZPwz&|eU=$;Zdbv*{WPu7rL#cVrbwlQn{O6T%R zOdwG!j}E!KfeBy&DhWN+?!l8rfj|gUSL+UtG6F3X51TRvvDRv!_Relnd+2%3#1pG{&=W}(IOYKss7<)|V&#EpSR zP&}r=6YHmF%}p~G^w<(|d~r5iF)q~QCPKMiVL%>j#ceGWW;Nyq!aQt`WlGk?zYe^r z-u5%=L_cMDXSm!?0q4gMQnjksTxd0zEaKO&_i`YA?oU3#QAG_dw`!C)z3kRY{ck44 z7lMKNYSy*(A_>;kVujyHO07dxeSt=jK&KUI??s%F+BC=AT7Nb3=r8x0+l zkYxLYcpjvyl@drlcY}RMdEN?Ec%eCH<>4M2z+d2HI{mmzMHF}N9vqFdNfnI|%|@mP zO1!EaLmJzZ_B5n*_V;HTfNe_?DUEOuZd+OF6Bt9%nv5TlP9{$7TYVF2 z-6E`+-Ha{T=0 z0lE#BF4a>Q?%B57#TwsiiJh46-?Ig>FWlQ(0YSh%^>Y$GABSBHaI=PHQPV%&PGZYr z)YTTSp7ZcJWTx1?&&aYNIm)~2MYhX=SL}E3DI|q4i8{vjZvKZ;vnv$}Z~K#qx{ zO9R+W6DQxadR=$>sZbgzlu4eWmzvMm44E^V!WI$KlPYq5R}EYa++p&q?gAE&pvkZU z;+p&!48~6QhiZ;h=htm}Z8ZfL9CjJ{);)I}M{;D!1I(|Xh?{rl#Vc@|KI-f=^+gOL zRcB7D@=c(DB6b;ks1;1`LEWDO$kbbaOab>+yxeE=s0EdY^rLXVHAWWZaRI>-xnAx6L-)y+j_>je&()ApH( z5(f=;Vr~!T%TmJ+$ST;KnURcPgZRkAubk-S5a>=qRePS>U-d&oI z4i!z$xnpcy*P-TKY}^YQoG`nsMtVG?!lZ_MalqO*l%dn)oR%wYFx z_tVH(q*S-;RCbuPK+1XJllbZW3(-MuC{?Sw{NR&dw#&!8?c{!lDM;2#)g&>QDOMzd zv(#h?4_^g}15;jN7LyP8@g{TGK+L21nbIJGM5<>s(kg_=U}r2gvh9HPz&4^+5i&Zn ztv)YkjksC{qMAKChmGnh=@3BkpUU_oSm^DkuFzO^nDTR5|(K8){IA2bek~S8VO~+!IYDg@0;A z?v-iS7mw>H*ytwO2OI zW8*F_$p$zG5e3paozc~Nghn3(c{Spzx^sE`pU5{98M#QrolGIO!6lWj%OCeFy*6wB zv*ZCACrONEn#8rTKMZp=H%`YVZuOoKV6 z(l*S&rBLbeaFFP6oE3q}39dQI0^?`EYp-SJu~veKgNRBg;hVW!LrE45I{^BBoKa4LOwaq%Rwty< z^;6YM?>45iXH$vHz^y+VIIvWb|04H?weiFVT+@%DmXY{&1CwYqN)(2P6kG5`g(d$qkaJc zwewo!MTMrOgVhgEvY|d1;nS(0tF5Cl5fXi1QT&5}k4f?U$IdVT4%MEjx~<&rUd~5~UCeyA#CO5yrW&iAOG9?k{8Q7>NFv5vJH< zV1+)}h+T1S4u^*_L@lP*2?o27q9Z#Jhf0W68%0MoPrd(wuN=Drf7AN*m0&{c!mEcc1@C&8| ze_oPll9~_>lDG>}0@9T+~)HP{9F?>!;XpNshsJ zut>Mjr^dQUGH)x#XFhyA?+R2?K%lJh@e4e9Rr18I8~;jq{KFhe!7#Dm=MbmP&wuJh zMs{jCxQ=~D8#}$p>eG@!=-8p%#S;v zVN@%c8m82jJ0Ky#99#17d^PVCH=2E=|Y%~K<}X_SZe%id){gaMH8&{nxuM`!f>TF{pOcwSmn&m%tlHozfhKZ z`c%*Ad&EH<;B@!c+BMmR)m1-f3x%f%Budn!+jKoS02Y>4Zkru5YH0NaR*f7gni5Q8 zHYBZ$J9rENvxN8k-MKh)DrNv&=aT9OBH@TT9`}|b=7o4)0H&rgIv0cXEYOeduhT8g zEF0O9mKZlu@UFqK|CnkwnSxo*7Vuw8;pJypm2{~0LwNTpvBH>v(WqWgw%NO4a=sv{;|7AS?V#m^@Y@2}Wsxz9juH`98D-*V)CaH|~ zn>?)vd8@;uE$xUch175P@a9fd;VMfzHq0~|!SSwesuS@|Z=AHCw*oZVfHaTic~ehT z%jf+q!42vb25#RCcnbentLc@J^UNfxdE09^E9l0)h5Z-7+FNH`^uzSbLPt<` ztsKl-0VfYIVX)n}L=Ax>_I$o3g^$;O!pAsdq2TC|tOukdb^Hyx2+<`nWLFOCsUuW} z6Q=QA_6VEvN6XBayfT;aOH}pT70e!1YP$bbGkwdxX3|ZKWl1Jg9;XPTEvJUxPlZL_ zk$AtO`|D>r_PT!$@_M>zYLf-FUo!mP8{SOkNvg34C!!8C7;Z&Y#ClD4E{63Z;ltiDaebDHXjAA=MTvQ)v!O;bL8%g z+$tbmfhg&q0t9mSiRb!7Qsz^6UQzfJXx+%uGPD~o+IPw%+#U9!-=&!a6lMP|`l`B5 z`hB++b8ODI*A}yi-B3rWrS5JX4rPqW{SClGahb`XZdLNh5>J-L#4E&z&aL*wDJt?@GOf($GBn zDObEtf$AdG@@#GRm^kfsv*6ZT#r84KkRAI&*QlFc&%j4t8b*vvI|mjZ`xfBY{|x~< z4+b7^ASi>~)V}uOjuwld=`1_i6(^0^SF%d=-&9}Gf&ak`2l~l*#_llpX}&vQD=>Zs z2*8xojfZ=JDtx%0rh2Q`yBwU@?J)-zV>dRHsEE!BVlgjx=0Wg*Bk%7|^=aK@%~Oy= z>I+uhfL170v~ePSN2Wqs9<>OK0d*jbxcJxHqRW~A$0hR42Ua43fn7Go#3cBKntZ0z z2|E%v)xZ;m$8XlnaiH%gopD~BVTY^15{fE zy16W&+UnF4ev9;G!+r52JP)bxhDcRbJPrbZ8zD7=s+X4*3Or4VF1Bp=eQPf&FclCB zzbbRXo7ut6kTV!s9$QOGxJ@+)vDN~Cq}%_x!_eSZ#OR<1EA@OD>Jc$8mB$a4dF8MB zlm4W%jItcu%9PBgee8u$Ne@&GF^hOyJL-@(**F~mq@MtXTC=8JQ7eA*dO$K(X$n~* znB!a=FikxJE_uzC{fhEIkGHEu?Gb_Z)UN6G-C>-uXV)J+F-ScF=mLXg#W^8(3d52< zN%A9iDk>dD&N_X6rO0uiO_UA``x@Zv=|EcN!dAN%zm^#ULQ;r3Pug4EMIy^TCJ7sh zj|8UXDnB-fOr_&5U!>*is<4fzTO6vUKd_!r$qrTH08EIb-9-BOYszyZZ%<$z`k?H> z(!s-0UZ$LUa!bJ}(2@lJhYu)xU3|7OKjJls{$Q)pkvUfY6WW~!-HLG-Ul*)YIw?;; zg4YhhV$+2)q;n6_%zI3o=4l|xtp(v07npz#%W7Ta$ zh*!Y@eev8Gq>ExqaUThyyxr$&!}WGQ(<%MA;A0>&9p;VCcY)$aVf57)FW5-TUyS%- zzm@@Ou@CN%_0in@5_^`sUg3N<)YAA5n=2gmO*|*G{nAt(Q0)5X@#XLfGEd?ZXVZ^| zd#?l>{Ls8=vW4E!lm(`~mE{WO6To+nGy#SY0m(2L{dRUP%8K)Ie{HvePCA>402FOt zXW?_ADvW*eyE**L4-?QiX@K6c0FjYhcOm&0;W}~PO7?zC*SFD2G7i^>#^Ks|S0{hY z)~YM0T8*&L&9Yn3{_6z;(zsh}UEPhMWPNxfP}_hz%n_^_)e{%;vW*gMmB zS0C~WZd-gO1Q4e>2<1rPZUaf48ibP%s5@3PUz|pE@VJ|Xh`g>5%Z@d`)cp){l*7+Z356|;64HF45B4i;Y!l@3EqEu8-SBDf~ycJ zc2%p}*bRLnj~REA=+E}IM=~hlRi;QkHcD? zAO@%?RdGI@p@2Xx-az0`uDM_0seM*Z;s){ca)HS_+(rapFU@`Pa<7_YGGps{Km5bi z+!WweA%7i&5g#y$%;RaCxlT{IT#9uxiTY>cTKy2M1BnI^75Jb05Zgu6{fWluRiN*o z7O4M41`-cVW7{2E=c9{lDK_DfZm-r*Z!0TMzt(6pe^fJ@44SQ3ypLPnM z6e&72kp);0XLs~~L)|1BP|hMye85#HloX^CtARp=orhYtypk^V{pq|L#EPF@G|Jz7 zd;$7alUy+Bylxi3rJ4i0H%%Rgh%f;h(#&xL^)& ziFVb(Se*>_b=Tv~pu_>qB(-x%qdNr(-dCmcb_btO`bZg5t3DkkLF%~=gssY}aP&7R%prp_Bas)3I44a;Y2!I?Z(i1&`en zybhziHNg2Z@!l*9GhZu^Kc7>2f3ff*&_3~zUeEniq(s(Y`d+}QtE6RaYi%<|d+zrs z*$X7)-USfd9uGBO*>>Ie7^9x1hhF@jF(3_c{C{Mi0uciDCfA!D77=> z5K%JU0yFg8dTLFu*F_aP(VkVvIOUNTjeMY|<;H6s&Qu;{WqoGq+yyVd6qV?UqXiU% zMTkM*hWo(sUcWk~MJFzg{jBq><$l~xmsNGEZw(_{+5;YxzEuq@tCjI?`s%J@qt0O! zQmtR9SReri+&HQb;z_Tpj3Jux91#KaDhpTZ1JK)jy!&a}y@G*Sb+<-XhP_)aEY{ww znRqVEi1Kb;sE1mM2x=rQ$NBS1WO;f+$D`nid0F+?dW0PU$Z>VBVySS09XcLHc zGeQ7V==aOcVI@+1lz!I=by?wmR5-8b0M&`x{^172o4W<;k4K-jbs~M$)IMM7tt~Pc z3O!;d?3^Hw;b_>28rhYev(8a%_SkBR__efN-c}g-eb_&^gsRQrk{roiJp;! zdUXgzIyc2d4oVXj1)gne_~POKW?AC$3vucch~0fK`B0_uq@~ZFAgSb&k`gJfF(=~E za`J=skaLeRfy6>g8M&uGPa_)?fc$HgzT3pXWd|`Xo3@VlFPs1$Qo5Z~fI@m3(qxV+ zlSq;c3xdE#zSO0)HZSdt-RxS5Nj*>|y-~XOCPEc<5`teuUE#`@9RHYf8Z>l>YH43Q zp(Rlo1~M;TeTuzq!P~BEE+hJytF2@nF8jfs`4N#v#(RN)ZM_vDOjh|7V<&sK}Dm^ z8s!}-tyX~a7=Kgxhg9&m8n<$(CwmPK=)x#HKq9V5h-8F@@ec3V*?urr>bt{Dj=sn9 zgNUpzp&8{2B_4 zd#Rdp$z0sj??3WJ2d@N8@9cfXC`j}x<>m&hKsO!$&!R1;;D;LD5O~(|D)&UN zS}<*wYF7i4a+NGpC@=1D9-@`!!BFu>bV^fhdF$TJlIs$lM;Cp?-D(N%m=eS*tpdZD zg$iY3jzxvp)sT+-J-_`VgAg>f#huj^+w0JT@c;%xqBU zgn$cdOZ#viK zD;Wp03Zi(nsYwLmpASgPFT5ZQKp=g*#JJ?yS`}IHuc^zRl-#+b+etw(`HUSt^nNK2 z2nGQH?N!x+w2FKgd)x0QbHN-ZEVKY-`#=fjAk3R_#vfeFkGQV0z{%)ZoI$c~vmHt*n|LuT2yS{i_nDLE|tUTk5;bPt4kZ_Yep%n!ZnYE||V6d>zPDfgkE9 z2YT5-206zdMg1*Ly!_1eLI&4oG0j|ey%OE`usv1r^jPIrwFCx&b2`r~R+0(2H{^$J zS`Et{aBlzxNMU#(o05%a*&jtTlECoc=5+Gtl+SeSJMmd@Oc2(<>^9VDEt&Fj&d#QI zrX?s@tEB5zau?5%@Cc4rkXxL4YN(YiJt=d_nJ+NfG!c%AHj*P=4#-(f*Y<^euE8pw zwIEWsn<z zHnK)GeI4MCR9yP0joLF%Eowb3;-dx79rO@-C7>`Q9qLzaUOrP@8g6?EG=l4Q_K{77 zbAIA`KlK~Xg@nFa_G`5`_ z&ZPoLL#cD}Xpc~i*}1?}gi#>z>!(^iSkArG_3)R-G!M?!ybMZdNYi)&(I`DMtUTZ0 z7hXo^>8b`p(%XT3O%JegTNow;?I z-EGhGOa!{CdJ0>Sf6T;K_yv6TWJnTQ6r~lc=4Y!kY5(dUR@Vul}OpI9GRJ3-*F5+}01KUqhMtFR4%vd>;o~Bh19O!6*;TsebRMr=sOv ziF@-jdaCx5{pOeVk>&Lb!O+ome{woB59yE^q_-PvLEVykv&A$x)_&A6S{n*LiN(>&PC9bILB^z+wBESmJMtT**dD6=HG7T`+k!XAOT&r@ZoFf?fqdKl%y z4n(ekyx|wAM*qYHzI>+C;~@M7_7Y(PBi>E#q^N2XMY72j>XmOh$*5c>`pKvWjk8FG z-!JYmgnua_oFu*|yQUH}_pDx_JRHc03GEp6?T2JkUI~p92mnJvZwj8}_G%EPic0)P zufkcs`bi&gzYG#=w$LCxK%BFZO?W`$T_-4CW&}t7rylTM2+A{vHZ@+$DV8~t?zv=Q zRyG`3MF}%rBltAW_F`K4YX^}I1<>u!GIy zUu$cReCVMkj3%7`3%?=WtugZj5H>jP-oYC13m(bsb;;lXL@MQJc91^&3sU&<(iH15 z7{L<^Z8!2zt#hIS-K*Rv)o?x24UfQztiG>HKF)u^&w~q?8!Z{}A^q2_#Ieg>$ zd_z4v%XbmK(6D!4;cV!^$m^ukT;Jar$e305w<2LfxEVGmv-KJ-Z3CMk3@lxH4P}B! z-z(B`?=&#`!A3Sso?-Re<7aMx=DDaqzNQoQNm_*2`;vzSyL)bWoYFe>@yuqf1a<5D zaj@u>AJ-AN^wfUO1usaHJll6DPu?=wJ5wA!7>nQ8(O*%A+@^ndDtJ2n+TSpv-ZeHu zZpRny#KmXvUY4D;7w!T6+tkGEt1A`kAM0Zg=$ATFdwjrH;?_$bE#H^T9(3 z4mu2z8L=!7xIdoa^7}2%)F1iVZx#;d%d*6L6iL5p(E}+PL(YX0O2b7gcW_}%zwGjN z{Bs1Lt@@jl(-RKUg(0c;L|!XAIMc^812ksLVR^vY;9V;P@@b^-ODz@o%kIXXDf4cU zV`ZyoOde)?VD=^`mDF4q@x`ZFos;D2MxKMzzPh+mzQDMkkW6=mCWN3;h6#D= zosSw(5sQa3AVa1_NwRz0cQ7HQ8}+8jn73@|W2GgVFW{Vhqe%pE(Rwq`G2mz|m(gIb zDbSxLdtZh#1AInI^D!wUy>oTO4S=5@G*L&RG+dILmRWqoVDDx0mUoLT8u}af%362k z?T0&GG3>|_T-`lUpK(69<91bMPLIwXBNiku@hlVf?SKwk6&3w1W<-)yEO54dSc`ra zn)ruLoHkoD*QbfNDg{LeSR@i8($4F`v4)}jbymd~X@WP_F_>JZ9;!0Jla_n#EI!~- z+g3tVZTln{=mz`r{kszU_amt>J2Rl~beJVo+t@%9N0OLYIZ@i+hygOm{L<>Lgsw(t zry>79TD#(3*;3V~u~p4->Mrr! zksg7DRcmc|iD2(@8~7*Jh*~F$wq{4$>{Pg+f&L2m{CeL^AHD#ZVUY+IPV%br+cPKB z*XV>n+gT#+#&v}#bgg>&H3Ov6v!a{mzLGE3%0@~ZpwsfuJVrdvQ+!Fjas{|FJl)CQ z{Ob4|z1NA53lKg&Z#qQ8hJlgMEi>Su<=}E+<=qfzTv;O&X?h{mh`)@T>&pJJUQF+? zZsuj;U*R8db>o5c54*$t=2!O}73_+B=o_WLDvZ_OY48J7f&Kd2TcUU}}840Jk_&20D5@DjJJXP7}FJ z;RP3ulP5s)Ec6v``}jyZ>(>5jW^QU!(^fOo_&eSXMrJyLw|hh;1gnQ~d;!1~Wb+-M zJU5Y2o2ND)bKA&jM=_fgp5cCBZNFr@jOt_EjLXnv;>&}I5{J)~ZF@RELNJ>ZC;%L& zE(bhOjjeoXFtmFAA0>i%D#vT8d9||g4iR$B5BFYtR&>w~BWkucQavnRD9H$Dfr&1r z#$ES;Z7C4@-RXG2_|WSAKh58#v!x|vCE4EDa3Bo_=`wCVoQ{{9lHY#VLu`z0G1c(e z4laxg{^)qM->BIr!VLit?y4j}O&`XapJs69rNWM+d@6wLfGE7H9Y-R*)eb(v8(--V zcl5%DY+kc$E}JA>hN}4W{A&o5phs}@Pv~L6DTV1CLkR1$_~T5VVN>HH>c0&bf(Ec> z@%M00RPyAtcU5-5a!KZDNB7*!kd;bzHq+|hr^6oU zn(6RQ(aNVblBK6rpyRlCLEvuzzld1l!GD7rLzw3MWI72X)kz}cl!9K>Buhz9o;G-W zt7+pzi6g!rTS0eTGGB7^j5dc)W#%%mlxSrPblTsgjk)KQMFIvFb!oN3mQ)m44ey={ z(C{&N^e|ak>U!N&<-Sikq>#Ey^Qq_FP^2lJ!rtXrJ%lUy z?AA@CkKD*<4B^;Tbjty%tsr&VMmEx6=uJSBwmNC%%a=)c$5I+(`<8t7R%yS{cL*-K zF(cq>U+5hf6tUF~Ku)#&aNh4A z5YYeG{x6!T?JLh@9lifvosmuk6~>BT6-`w{*(?J3R?raBbbL{ad<{Rxne!jsXXtyte#AzvndU(`!?J&7z3Z`NsIXA%x4&K+jp<}oSTEOzS6_n zgx*b&5X5#1-4?K^4W8Dk9ZL7BW`Z`5fI#cC!fBlIb`cn3Z$*jhktb+ z`4hTrU7HOtBh}r;5U7mTlB1Oi&UG1=++QXlxA^sJO@Emm0s;C#$|EUOwVa41Hcz^W zY0gJK{2U zWcixMB*1>9@)<)IR%a|@vnJzJg-m>HQ?tCYnYsSXgYSARqF~l#Onqiqpu%bbD=C}v zlJouo*c?-0mRLM$Wc(9qP$&#Z+$scI$|z4;>;EJ~!8@?B-=&%4-A$~KA8Xtj0$0!n z$7*GBcth#{m5GYak;=rVwP;jc{`Jz>a;ZdZh-5{bXtj>SCqP8DLlCK4hNjP11AX3h zqty+U+zvhdFLD#hDX%M5=)U7I72~9|Qa^b+c@LFoqoebsYG&JPF1X8(Frm{Td+frq zKfmH%0QywHQI%_Rxd|byA->eh#cAWWJQj5bmLuAejhna&fxJ_RVyicO-1h1g)$v_7 zs$7qC+g6PW`!x)M;UoOOWvFkt%M|ukAR-#OyzBaFA0`(9`NAl?vcdMPu!LVO^4^gE zF{Ea0I8m>OU?q|oK|QX%R;Ws^HlzsGB7pmGdev_#6Ht)QB2q{g>5Hy8%i~v@uPu|d z(hsc;(KA6=Ok$~HsupcL*a4D=-#EiiTd6U91zi&5Yj#OP5LVvp#+;rNKpkHP|6;Z_ zuebZc;4Modd{TRkU+_rYk-U7|)JC=H8Nab{2d70Cba`9tow~w8nJPE{O&@9ZtT&`` z7?N=Sw*gDfpdyhqaJVg0Hngsgpoo|FUHNOY{M=8TY>4v%1^D~Xf%U4S%KA$_@>17F z_c%&YlL3jk7n2sy;d1OP_^!sikKnInx7$YLJu=G)nd0|lj_;Z}lG5f`gK zRhS?;uLfSj#=wDq0v~}!QerrVK(PC1BS5FQZRORwwID=&XC*597D!dJ+ z?mxd2jILS&xf@qyR5~Wo-2$k(v#HDcm16Y&cf|a^dMwcEc65FqhD4A2=FbV94G&hB z1A)HE%E?*eqfX%)A`cHLH0dKV9 tOpo@UX3xDXvLV;he~kM7^keD$;aL-{9e#zPgBbb&U@fD&s5=jy{0|{0P)Ps) literal 36706 zcmbTdbwE^aw>C_pq)H7ft14x|33rCNF7Mi$8w;3w0= zd{YwjPhs^>!@j+LU$6O4v)`h8_`+;Ywp*W0*oMVRoHq6*kkP07L??1P?q(tTr0P^L*oYDJdz*IBr@wwPOOx zdhA9`zrpt4JvHoe;npMImiSu*lUm@R$Jmu7T_58U6N!L3tgME!L|aZK^eX>-6MI+_ z3i2=h>k1i1KKGyNiQxawpBkeIagip-3E+}(*q$6IB(rUdt>`u{c81_KA77lFj-(1D zv*|cb^*S+LDTgHYjxO8^`^3x&aXRkLxt?mz&O&`=$&ePstEg$S1J)oScJWArDeLlI zdtj{Y*cBJY98$<=Cee2)ls4*dVB{SL^^5^Eywb5(_Q{VlVvzL=P4o7tigL)_3bWyV-<{Pnl5GEz?#ad$H}_V!TF#b+ z?BR?{0sA94lV70=e9I+~srqX&uwPaBrkb_G3L3oGg|Dba{l(qlD)V6(;hD%O?@$RT za>*MM|9HJsQA;`?mj|>Hv=HxFNzMdRVcYPhd%aAnt&z-~nEajNTE_ybsC}wv~ z*@H$+FLP+4&Fqt^|?~B|-Wr|GXA$#7cJ2pR?AmnqpyVgQfZTW^4$K}_+aXdUI z70)obciis3H*IJ+=a@G1%3)zMhTp(u zj7=1Q?sds!G-g_7)8l@w$4)X=He0?Pt}%Mn?2fzgUrGgp@0ZlX%&>`ezqa6HIt!P; z>BE(Y+l9lGwWaD(lI>~2wI=~9!0M{Van$6)L&6bS^f0>X1TKjuYO&VO-} zijvfv9+#|@ZL7HC-k(!M%0KI}ADbx*R~IW|P>pK++rPU~mR0}EhUnfar~ho8Ebcrx zm-M_zCV@e>s7}{18^-iC)aP!EdWdpw`*oB|lW`8xP+6k__`Rp>$9Uqlo)2aAxc%CCqoIRD+=AbxgodqQ2jtuw=o~I9 zhm&Hzi(%P0WlHy3!Sb)TQzu@oK-;)2epe0s=m4hU<=|^Dt#`7*`v~D(20a>ZJe4*m zKtAHw5U2RwfK{~!&5NacJPt0isxFcPkH$}dIe}Oicmy%TgYOIh(7(_^KI0PQ zUxnqa!AJh0%Gurt#T}Dc^gx(dV$Te-4)xf?150ho7 zjJXL}(cl!UC=&u;l~5DuH_9jMzxH039ga_ILZFe!-LsxgvyZ(bGK=G&pR3AO)} z387mAo6&t-Hg`YP4$gpVPm4arVZ9MGF6c7M5Vh=Y@5%yg4^hEvHan3>6ff}{2^{e? zq!cnH*A$`iC%nY!m$;C0uDXUwrs|+|dCTcgQB?)4*Bh<`<)e-Ka)fz}r#SoKq#740 zX|KyXR%%Kc--K&`-Cd?xOtTJcC?oIRnG|!%II=V$DlE7){0`x1qq) zRu4z8=mEq*o1uB2yz)lWr5gz@2?Y1iEvrk(6-Iq>0tx5F(7{?ajlv$x&=yH_^v`Sm z&4_0Ey3W}4`9O8Mw7$?U?{&9V~`AJjz<}iOJ^H>!(q02G36rdL@ubPEBVTL5NkwL35MK;d@ z3c9?SzmMtuotc?za$fA3w}ft@6WEAtf78(%QSgqNG5kK63CaE_BRUOuWIh=mfQ zRN+I9ACh!SW=z=c#4tf+*+s)MmFk4otiVyzV=qX4zXv?`F~N8vI9sXmVZ1b)$pO;P zA!pgLu5=CmjgQ+@{3*G^WZ-2*>99aRX>EIb?M>H(F0_7HH*9*Ociuo{pqJJgKC@-4 zTyXTcsF%85a3@@VKoeevwUl*Da-05D;sU2fyzxjdgRMTMYg2i5g~1qlI8pRXL+mq~ z^oKYip#ro5G{H4If%PL$0VqR}=T}U-g0}XC16nz{&)k$$pUo>+8Dtyo>YlW!Q$NOu zG&)q}o+#yJ0)J%+o2w@iJTI6i`FBjRx4oGcEj6ezD{e0dUI9fVW!L@mJEA%N4=Bua z!Ln)8D+>N|niP8%bC+FveUyDQwBLzZlwPpFUk_>0P*%SWUZilB=qm9OlhX%LR4yEy z=Mlmz*pIq{I_1l;-J7cijO#m!X&7&5K5oynXB+fCH9(@oTgiKSBrR`s#mA$;L128i zGlXbm5EAvYTNY!ie2LfCQ#jokjR%iE&1D54;!`CEl!c`Bu zq-*|A%Tu%JO31mtlD0XaUX#S`bTGf&*>nl-C~gFl^RN%~W1|Zn97_E$?Ug$}a4vmd zhQXp=t4E_UJx!0p)}YA4Nc9g3On7_2Dq_>;lws}Evl8V3t?BTL8WuEX**k6P8UP8i zn>R|7Vs6jX$Ck1}XJtY(#BkSdHTh|OV_1r8!K3rQ+bW_?iaXKY|Nbmlnn0U4r3q*N zCpKT6!#87gY6X<@SlwLn>KH_04aP^STh*Qigb)f{zLU1-22qEq27zayN1b}!^gGga z)(8Gkot)O`f9a!gII&5!v!!`esYJfoZK7=)<*vf^DE0b^H!2>hGIkxRb-q=j{Rok^ z{;n&lgstw*y2$TWV(&9x#}Vnz?g7i*Y2I4APORtrsVoKpl;hNc4n=(W%!I#K(8wD)kf%ZPu&$ZKn)V!6VQPkH{a;`e*2Rv}`q_xAVQ<`k$w5}8K;iFoK z`otpRn%0{dced}J;OmvF>l=<|@kJ;t4O79QiGsD2@v4=9BXm(bX2fuiF|Q-q%g>&5 zd`plxOb`~g>})XwftIss-&x?yL|aySXZ1&_u7~W+)$@JaAS^|fb-bsuL6?`Y&DBKn zQ*au$e|E?GpJdr8<70rJ+D=%&Zt3nov9vKB!@_Tg%K*<>NTrK{ZwY8kx*cCf2@GEJ zstFv-!aoT8chcqpY2M?WAHio6iVZbG76=!+KIOcA8!20k5h&G?%=2N1;g4Nw@CC#u z4nQ)j?`~?oY52c3V`ebrqJrj9GH`!fi9(V7)dFHP?veR=l-6Mnb`Kdks!pt~+1i{+ z;>giN9_yxbA!NQ>RRb~!#G}U~iVw=xqn*JGDj1P`X?opLY-!u;g|;oN>eFi4pUt6EZ4mF%2 zJuRMr1|2s^_(Ja7};n6if-%#Sjgo;D@c?RjvTs=1h0i$xb1 z%uFNi_F#138Lr!^yMd8Nw%@^LUEMUBSW>bp!DeQj-i%px<2d0|YLODu^;!U1v|m|G zG70C+W@fe){uCd@=#p5kK~Z*r3}ueul_}qPsXvI5YXQ(6#gNaFWIgGTA^y@hv*$@o zP>Z3+c$)X_U!)g>RPH(RWl-`_t^|k{vO)!CcG?i+jol3_eaQ}o!=}7{uC)9j6Jqii z06mH?+@7uutzYoAS)cb<^z$AV9@bl7fnr=oQW{~uemXI;LOu7SoINdYJ+POXUk65% zH##+;XZiEYafKU`-Y_IxrEQP z*9AXBfkAs&=R_-11Rsg_mTlb%`OH{)G-Fj~N61V%vvzel*{B>W)Jwqs!esqY}|8$o_!bqJu@K zS_NGi4L#Ar4#Ti(S`NlKWWv8MZ^h^ve&baFo+No>4fzGo|RI|BSINs3??Jw|?^ z)Z$s|_*ed@Bi|Qma%WgTj+&WN)y5Cc7H!_TAl+AcvVu{q>wD2!B_h20>#ALKIMwNM zAb2|JIZXRW`Kwc*F_5hz)C>|gG*B=TL`;?D`c^fM(8WysZ-!;hGZj~JfkowIV=cdd zvTe!F)D@$dTBa=fX%j?14IIz#73m{JrF-l>BVVABM_&nYvW!x2XGPoQE5wg3MIHM{ zr?-^}4FHdB(zA)~0MKM*1nu0k#M}~L2|FscAH+%%d2Fhgygoe`Lvs~fn4;U@$NK}!hZ^wvHs(e7eo;{&^!+^am=KwC4Fm3tuxu4&S-aQ7nac)c{_WbQX z+n3-^ma1V&7G9^~%`Ijgth&9aP7N6APl6Sw;B+I6H>7YP(u#fwnlr4dXYDz-YnA~E2G87^D}XNiv9ieXpmW=htlBBk114!ScW_+7Py{PZy1CfvaL?y zsXqWdJO!^vYL#}BT#Q{{Z1Xt5 zXKSf4(0IXTmZ`x!BK%LgexE3{G*#NTbb_&eT+dxsi>!B!24e>tqR_V7sJ_^YNwXlN zTy^ugf>+{Gr1cjLgjNUa`Co0ph3;mJybUTWEt?hOVq z%9*5Zbww|Nfvh*A?>8a_=2m<&bqQJt4s@c6BFu0iSVv=F-b>K_%k?GSE8o=&mTa^> zv-qtk`wpMX-}dC74A zmjAD$UVyVQRDz5)ZR?FXgoZ2Q0*YxI;6$q24 zUns2+*Pp8=qArM3PhLDSYbIA&ZdrPxkU{p-vZ|O9^Gx*_0Fk87Ds08dxQ8IJ_`hxT zZ3z~^!j!SjS!1%{3l0amv~Ot5)aL{Ji zIP4)T6rv~crRO#O2e`z5<&3cEB* ztf;E?qJ$8f+Za%1Z`kB0C-k0U8#BA^`z1c=JvY-S^JDsvcjB>Pi`w#m{1i5;Bo6%`c?T0?chZ3eT_R$$lV> z9RSk&?vh!lA-(;*`NjN^EW-UB!@711G z_NYaVscx|ScvIB1GrukYf|X)TqHdYeEpntb$edMGw z&k+y;#UIN5X~GjXy_=coDbl0urg7HNDKAd&`BRG$76%rVa0@kvlA7k>YyJ$LIQAcE zrOy$jOn)NyeJn?>@EpvfPpufsD$u5E-cT~Ho2_i)MU@ud88^4706`QJh0LfMV4#w) z?Rz8^>12t7V`W28Mw_!%x{SqW%5`Ru^qcKPFEpz=f5Agh3Q z!|#9Ihk}R_<`L_tG9%yggdDAb<7+mS91yR?+bJQ$)Bcm?1D%xRAnNbkYXVr5&4u~W zl=;2@VMCE^lbx+YI+7}FnO#?tOMzIsAd8!^VCVJHv!F`v1*QWLyHgVbYL=1=J6b6X ztrsLEM;TAyL^S*4E#ojDJhZkJ*QWW!l^=2i#Ohb?(mubxCmqPl9WFR(W8R#LWyS*QoB*Q-mP^Tihxb zh*CDs2Eui(P+f3clUm|Pw^|y@bAx!_qZON7eU)#N?LAQmC2amz#otdmu50~^uv>aM z6kwFxr&vn*jmIy1DqHQyG(FoWJ+$f1Z#6IQuFBPERhq2LawF1@l7O5V+J~c1*(ra= z1}6ed`#O*OfK*U|HsAptxo=f-ULqD-`23yOf+HQ76aT{6Kz-fQ;gus%_-nTMX#<+A zuU>@0d)+|}a7dIYqhYMT?`?iF=sR2dgcT{CFLjK=fX>zqz`;Kq0IQrOG1@11=7V&= zHlfL|>{U&EWp=ctvPL&6?nDuM!roNaPGD|a;#`m`GF(L1>R=L5-qFYB=#dq}$DL!I z+&a5fH+lKp1ZIGxh3Y~3;9}XqQrF-`EX({*`Js3NI8uc}XlfN+bVz>cp*lWJM5=x+ z<+NgA92jH*fj8s#6e>a!I_zND9?2ne0?6Vds>yOAV{7ti1bZ_T#2ZV%&D;!r;5o1? z7mUAaJJ+7g0*DqL3%8PvD?CdHA&>T_xgP7sGFSdOf;@5P5is&YY|_U9Y=I-&8vEOK zeSjg>-oqYaT63OLPrPRke^Br|!VO07gcEK(_uUF_>TpZ{O3#%aC)iJcK$L3c$jU|Bu=27`3K8a*T`( z`1Af|KA{%dig9DT&ka@EA%oI&8$WpfG}*ads{Ehw{Svb(K?VXME@likB=jhdD8XZT z>y6o)tqMLYz5)?AE})4?>(n2MN@@6O&ZT0rp~Q4HEM_Jg>fer~?p~XJKJU75ySDvf z8(Ht3eKGEzAW(_%Ipk=d>E>F^DD%gh1}2FZC)dyGrDsXO8F7K{tMsoHAAg$2!709O zUt#O=wDKffA;{FwtNDrD3)aEAe((;%pT`%)!#dw?PeXsZV^=N;-0&%`-(FwZba@dS zwqh?r{NcLM>S=7Tp5~02V>Y45Bk1o8E63!}42vGflSmOuG`f9?9^C%L;<}JG>Esoq z3u$zY>QF*%iENBm{{P%SOTkN9Ew(8=W3b+d!+&t8Zoz%`2 zEeo}Xo1Z4^2(!^hN9YZ(Ox!@+z|jPw1zeGk${(2p;MZAjulHJG?Chcz3qs-yq;DS( zqxA}@qqJ|^lDTOSi!Mo|r=2&FOTo%pvm7>*KC3jjmu7=7w)1MgTz+Y=aFpNR^(ijc z+{DM3JeM_{!yD|FG6&=&uT$AEH@UMHMaL#iP)k3z z2c%OA!sWCz4r}mf!_nSXr}ZlR*~|z(c=;jg{Bvxc`R6aPP0k8T#aj(b@&aa~0^IJp zJ0r4F^Ss=lgvk>&Y=!%guUFP#Bm~7>ft1NA_0+19Oy5W3Jw-{wa`ttb`sXzK z<)xX;xO=d|7q@!6O{wFF5B|5UyIDD9mlfO*A zl)IWD{#X&(ncwWPv-50=B(?dcO8=la!M@$o-lbO_@*fFT+u!o73jq2VMcNQ273uG} z$b-^TQt0*`4(l~{R3tlhFu4a_m*X5Bwqswn*EidbN)dH4$C__8M)B;?dzz}*@EWZy zG)^r6|5^_LVnHt&$4TJxHAQA8KD7rTJ3Z34(~oHT(1A+$>T$}8);VOM(4#0F`VYHK zRKh8U2W@E*w&0EZsv^=`K@#zMwQZx|ozIGda$ z0S@Z?$=u6Dj)?dsPfHrw z2y=t&uW@Wng6!RZ@l9?;_`pyD)jG}-Gl|z;qLGs8h~^8w zq5n~}Wv7MDJDbQ9e8kEcnIQnoCq>a|IC}SJ|Ebfh>*iDbt!R9?q_s!0 zQ4e>+F=@Erm@&!=7Ui$(fV}^OA8)$I^5Nshs7NDQXHK?m{-R?;${W*}rn&v-xKO5I zk4mt|mc}rociQ|!>YeNOBn|3ip@Ze8i7nw?5UKuwD4W4&)Ag}NXXYMD*R^6J=>E8P zr-6-sM(qq#cACrIYG+b}*!VJX+heU6+w!dU0NOd@W)q_~?Qn}S+tg>=D2!Xn{m&A$ zBw-nam&+#7vclWvPh*XipQ*^fRFr*e}O zdaN7bHng%$X6^M00r9~moF0H;kM)8A{Os4<>F(DGp;{yp`Fh~8gcCY$0>d9Dn2jmi zN;p=1vy&4H8KuexN=Y#qPwW-C;7u;++8!!76{`c`T~DwWlxrc=C2)k1CsHV(qqYOw z?Zt2NXc#GiKeGD+bjxs%CmHbuI0{kiL(?>lUpu52?N@>npH$yv@tV2(wXKUQc-#6V zL$-(nK zY*cMYtCwu(*oQSu6;hJkgvcW+T5>^Vi<|n0f(TEHkgAt1k~XcX_2CN^77Jb;$TgD$vS=@*nsuHN%P_;v54jXHBLuLR&Mn{@*Yae_VVc zH^NXBSjqY21%et379x&x5$~HxuESM%ojFj~wM_|58*4H`c0^=gV2Iw}6wfpGQT=eu zmdy_UhSBZz=E2 zmJ=~9_dp$(hwPxlyk!NIwr(;sAi6;Wg|y^=+a&4^Lz#bN3+OAq9OFB2!zs?uYUq)9 zvSMjW(8KIv&o)#o^Q}z5JG+xl41u1H+2g9>YDkOSVlS=nw**|MoRWP;ANRMDIkFlb z&b`v|2wo`}=0_aPN?nhpH#q&ilBs0fDq8u;;|)P%*bt~8Wg$qSsIj~={20Ud>5u_M z4^~vPNk(tVPz@lOXyvkyXk6$xL1`*bAUG@j9`Zk3F4TnF9D!&~8EnAze7@^zae?Q< zx0!~_?;B>XLX3zh#Ieg9wW+b@Dtw!E!kRcXGXJ5~>$E(3Lg-Vkoz44hg=m1&L_yD? zv8qNuJ&vt!yPvw6awar}p&X4p)}8M87Iz{dEcYY8Hsh6_dBZ~ae>6UG%x7FzRKZYw z$_-zUI+Nro#e9?}uGcbw?fcHRKkA#g$2`FoHoWI5^#ZoY6#e&&z1uo1*KW~l?-_B{ zF%@85!52gU`5ac18&n76ocJCj_;%>1jN3Bxh-ry;$pI@?up~zKY(wd_9F!g1mJk#Q zrU5C?D@+4|0)<}fqoy!f02|opox`q4viOeQaXdh0W|r|%WIXu&Q|^O9`crO1PFYL= ziKASAfJ0{XW8CK$I6-FAF9MD7^~l_+kww-C_Bne`5&`bO(RNm$&87pfW&v`T!(GWd zrlS=0W{IGDoz&o#V?OW8j10C@zMx`PKW3GayO27iI;~@oKcK9CD^trAJ({@U?m> zNuIeK?Eos->9WWkD&G+5>6M%9=z9RdGYbH<{<5{P`1(@`8*?ML-{c#U|1uRyivo}z zi^G-fAwjo9Hmwg3&!;6Cn5U&~r2ZREq;~VO`-hUPiWxKZET;UK=~A5>qkUeY>>yR_ z>nM`=0~Q;IwUoS!-capX#3!Ync1-tUOVn%Q$RhFCgzm3~9keJlGU_2oWph+`qV_CvW6zKmm42TSHoKuuA-bL<<13&{IJS~X5@WO1|9t(& zktaOP`_UWdJ_cNxu(03SJh&-eN;icHe;*SZ;do2nN!btz@klbTD3>xY0@C|odBagV zHBEom!FU3zoe>b;P@H0)6d;llKmzD4T>PmnX29IV6E_2d2OsAcNT?C35ytrR;}NlR zQb>u|$-}H?9Cciqx>8N_fB+cNzgCirT8F70=j(Tf3J0^xgk>B;IR9ShOI}g}Fphv0 z+UVx`kZ4?1Kn5|(&_4=zsP-za#xjxVnvI>fMKqIWIx+04dC1G)t?D&x^Lqof6kwA0 ztG>IY0^H*Ua_j<}!m!ztyT{rv9EyQ{{+{LimWVO&e#|SW2R1yW>KjV38>MMRT~vr5 zKf3VB4{ng*TD*!AA!*4=A*2B|erBam!Uqiy$NYO!s1Q;&7E7Ek=ix88zJR*j)K>Pn zegPZnrFD`BtepVUeY_#^-+E!mhRcZ?IH zprgW9Xos8NwP}Sm#DY(
    JHV!_c(VONk^5VDB`Ac%OdR4yknUR$Ms0*BO$C%kN9 z7~L$<$h$-IU_ckN|GB9}vdP}RHhWcRucO9G>~i&uW>lj zh5B&ds6=QpZS`r$c&pK2bg3X#J(@(2a7&inPhfCIb&~mJ07+Rtf<_an%i1wA@LGPu z(Mc=39W&gJX`*n8Sn%y+`B@Gj)shI98P;209f&fu^@a$-NArfL$IEwG(T4@`9suM- z0P*A$N~4Y&s6ekwxf7uCQ}5^~O_fSGQ!VzS^-5*;_y8HN;fQ*v7$&njXMD z_8Jm8d@#8N>B>chvj8_Wc7P^8EzAj8Mu%C%Ucc}_1s3|1novU+4YLMcFxpafEL ze9arAXn>N!8+*JjxqfV{8+H638h;supA9Jl0eM3}p{*iy2X4A#n_w{Z3jNNIXFv?t zaR%=4PL)XVEk{#OBhY_)JI2>v@VsQ#XHE0!AXUki_MBt?1w3}(@Vs@cNd6PDSRQyf zX+ioV1)xCOvC zKin7B-+rA7I)-#@axGz%KBwDYym0wz9c)FQg|cMZscpf%%h`%B46Az`KlU7Gw=5e$ zSOo2z(BP}9X-rPW!fzygd-UKJi1m;f1U;n}l>-1TSMpVDEWvL@Ve^G!pd-S?4^iJM zH#2k4Z&1n=csC+-Kj&*^IiriOoQ7mmlo`1rx%u?y1;u(RU-80JCKgk__wAx~o!5Q~C@-(PpW#}kB7RO66(mN~{{$B(ufs?0>oDDlU`OmZw0|zJ5 zn$|g$Kr-sU=4OLEptZ>uB)Te^xZS-46tc4LLGFem$p@aHlP(Gue0AcRGm-=vK%X^z z!6Kq#9F`KK3bS{)m4(rs?W_!6wo6|IuVL=3^uuky`6y;`tFk`a{7bg31#8dN>8f~FFnG1amFYur_I`E1IC3BmI0HA(Ei^5D13=*v&QE#=cMzQv zMaE=qPg%~3BVcnN)42bOx8OdfMdNiLC#{W9PDN9|3*A4#E2(T){usO{^?0En7(q4WGHZP&>b+ZhQcfv9vchb zuZ|!Yde{I-ydhHia(#x>S%f~x5vVzFU~@26KJDFFyPjTtJg{UkbV{@#7&&cZEP$-5+_|AY&^S6iZ^PGvs!;@T zCNlBuZEKkMKi%ig@~~q9fE%o;k(QsJ()KiTn^>c$&8N!JXZVw!gL}HL2vgQ(SOFmi zu{Wr<4()!86ZCpXI}~Rr#jiE8Depq#mc+w9)Wv5SubB?85{P8nm&+8ia#86)f}r%l z#!B8{n(!u$c=$8jKPWeEon7kyhE88BiZ5EDxR8 zQk|Sk#CdVEhkx6(6oU}CG8{YUTLy9!JNy5pxFK|qgs&1^Kb#x)yd4 zw)N>|ijd4lPWT2aXG}~8bb94`E%#`{x|p{Ja^ZoWN7`dXLj70tA>)X&_ww16j+9&z znHDB}N(1Fp0y$+0xvXo*?hsblaa{3G0~X}r6i$gV)Xj^A^5ib%*aO+AWzMhBZg8Ud zh0*di>p?l#R7Bl5ZzrNb{c(68FpuGnROtnnc_xTbOq9A(rA>WdvzFK7&>V6~`GTWQ z{$8Zv3)eW=8$G7RP2@fgpZ|Ei<6tnx4zzLcTyAk23fNLYE_KG6pO+-p5d-pu4ZRDV zJ=1~oCAHx&`=80F+d>{Y|$86icP-v^neTvflf0k#Oj*0}0Qa%FGU%*zJS-o{9^bOt0HB zK464|WFI@q!eX>hne(l;IN;d$|3`6btm4h?(drTno4V+lF8BmPMBO{D^_R0Sa!m^}-hNl#E1IT( z7jV=JKZUs(9Jy5g7si4=uPN!rJVsGLKNA9S)XH*Fb?LI>86EvbUc0Ekdg&4P!39Hw ze>Y0Rai>AQ9Qpp`U+CZ1~aCuc5o zhl|s(O;7s=2hd}CQdI?ThcJLU6ej7vi-xWA&)S8?G`g-AbPMKJAjB)Ni0*VSj@uW% zN_j`tWu@DF9H&pnAAI2AaB;iq{Zp=l_coymefRnWLojyj`>L>GOe8yaO@m@+$JJJ( za3^(HUsb%#XT19!r(N_zwy=o)n~ndd?<~%YKqri32?`s=nY_Hf@Eyu1H@%MSln>~L z_IY>_dq`d<3RDP)SI*|jN0eerKuxxC65H@A`a4WLG{6ls$aiz^XbJvX_#!b>M?-zy*jwp_@57u&AKtZa9M9{p{^{9d_dp@h`A|U zEhb6Ze+ld-;Z)zNQtL3M(5{~fF5acD5t|T`XK53(VL+zk@L za%xNqE1TL;DZuz;Hty~b9l*X32FYtWb~;%%6=gAx3AE7oV6l{$^GC(k zgh#A5X+X730&v?6%Rja@&j9`8J&OWuR1@jr4P=!9D2SwhJP|g2M7d-eHMeSUM^9h+ zf}^fNWOz56&l$@RT+xTM?+jEB1)i;2IBz$=Ktt5iD@!Bg&-7fAkaBk_kx(kZU25h~ zI^dJsFP#OF$k!@lJ&;NtJ-wC5nWR6CzJ;TbPMIjJn;6P(WF zO!CSfMj_75R4bk9elT!o0PT>`CZ-bpYEALI-Ar$Nn=^1VhhJN(pKCsWhxqmiB*CxX z^}vdi!(FCmuU#e?#M55Lr(|cRx^+k45^;35f0l{keXHQW3zRb`3W0YTX*PK>O|4vb zq3P3F91TnF890^S7A!kKT+ZKtXxx|(AO8(pt@I`K$y9W_9^wT|;%0`PO&;Xz&YgCK=w2JF${wGt{{m(T7`bZi)h1Hh??6)jPu^5vB(VqP?_l!A ze`+$`)^l1ri34P9Jp)v-GKG!Fy)fYkh;m@98ybmKy(k7PRoSK<64Z?r*Wjy^| zc~WF^y3{d!t+j%Koq^3sgm{^FWYaX;^Rc4-)>>Ibce=FM;xQvhJ?>W+YO+sJ!#_R> z*^UKgU-j;GE_?b9W`JER;evbXE0wXU8Q`NEe@nRU@ZcF3yttfsqj!@|>e%&FVy?j| zdZUaq{>4~(w5F#1=3-F*rG}-M=CGe!E&N&jev=ju9hD7&uLIuc92 znk}*Js1h`}$#3ykuIsP-Y~8kA#s-&hPcaVW?gs4<;qm-xWL1n3qtfKr%)$xl&I~Y) zm?a$W;Ce1|i745`fbi`_aVWgH(hq|`1huvkj{H;MPyo6WJ z!AtPO^t*sT?QjvhLaFmljmt{);1tcbSLLF>@5XNPDA{xdv4YinUK{fHwo(5SqItZb zFCjr1Q&vNXqjoK{Z@8pX7npq#-R9wqCbt zf9uxYsn)H3-YsfF=FwR7tl5_m5vzRl=1S|zq0YAUZg*6C?QVXV&$46$ltzzu(M2|E zwxu;wt0pQ!2*NCz7w#aus=wSUF(a}H8Nsz(lr3*{n6AHY3q9hdabKqe+@x~%Il$O> zE<4>Vie5+UPV;8gazOL0PB5IQSV5q|+vw#*iu&ar%`3!;Z>1`wbM4ut-5VTb1KK>%Zm(ykQizzUx;7%-X~9t3TI)h2k%O5jI8xNNm`aeXx42CvHpIbUmnL>)+n-3nCB9 zY}jB=iG3b~QZf(!ML*<4W@@CFJ-S0(hJ5AFjh?Ri6SrKQI$6Mm5!3W5tsNtT`-OYJ zN0JNr{qj(nKQ}tP3;-J5NVzXwCb_4ET$92-b+sScohSthTyg94G6RldwYvlU&u$r% z<Y}8q@kkH-`TZ6Jfnn(3x}a%Vc+~+k2-46 z5=$X6Je>61X>G4{-hLLR8|Kgr42XH^!`1Bv4&9DmAP6<$+B zb8USzD87{zE3Ox*oiHo)N;kN(N@m}Y*=hH`vA#p}U-mRoG!PefbV;2WPaJ$Iat|c` zGcjyE$~R+4nd)z!CY_R#+BEv6Nu+i&wkgKO?dfm#OY3o+V&4mmqqU*tf+rt{ zl>3A}J&EnesfQ^TUT>B##Gh6N-1!qw0mDzSOgi{%$k$GbQ#g$l(u8wwu+Q6sE6B2( zxib(6FY=nH1f4$^G`pkXq1vUC0LRb&W^+-VK{ug9`4X3PFG`ACI69ienyog!SWDV! zFq*@MmDh*)JL1|)SIjDErhO(L=V;yPBG(ID?*=c_X2|obPyWh!;y^v&xHMjex`sLa zX}N}`{!m$PL;te;me}`V_f5ZYxw0$!O4A=W9Bt>nOS&G(bq@(F4xXQT7P+w*ws>wv zu$F1ZSu@eIS2-+-EgWT?nNv%%-5$XMXdzV$r4$U7|uzBo_t?9Q@UiK2w&ZvWDW#kq;dJr|v_KP{Te z{rwjsvrYua@CdQ7b`4}0ZoB>Xe9tE`TN7I-Jyk*b2zTlNp;E@940)|vX1*xd+KYk2 zom$iHWG=PC^0Y!kwHeMy6H=`v$N@zlpNc-$$$YQ7q7@+vRl6edDiVmf7;wCuTe73% zsA#T^DM&u-hK{j9DN2hC-$I7yn5+#*7I>E5{CgIF21@nU+hR#ig}36P?vf?_bpP6sx(Mk$jd5y-{)f~U z*YrowhDcsv5;?qPRWVRtL*BLf|nG!F|Ck?TjkM=Lis!)-*G2>X>HX#C)q_xXJ_dL~4puz3% z_QE5{?+R64PqS65?-Cw*;4UY^2x&wIq16N|R;nM1!Vdj)ooeJuPpA5zC&>jPq00PM zPkVR=l0D_ms83EAlGch(bu!Lu#vi-=D^`9DI=#$0D=tkzY@~_OD07`rlTwzKuBO?_waBaeTy(T{7fm3MJ?3uFAQv}kaqdX-{bHn%OK0-?na^YbhB6W;RtR#bnJ#A3OUOjLWM zwQ*xzzVd1M9h+0Wjr(*?3mMcvJ)KiILsc^RRh4Q}KzLKRoLTmm)m5Xi9*tMRjG~Z` zotIE%TlsFztz8?V5ME!#;jEkdVyt(g@27#i9DPgLGn~}I%5H<62DhHloP{m#6Ait^ zlL@Eq^7WlPR$r|9GGFZ&?XX#{I& zl5ABIB1M1Ct@Ui{yMWOXN`pBe#MH0EGKT0(U9St5?C%F2*tK`7n~Kc@z+uoExdWQkK-Y~w*^K;;IgK7nG;SU`l)}ond32Jt8L{%XB7Rc!8UJgP54 zfXi#!j=bw-KV>f$Yg&$NFbV?%3aBBY!j5*k+zrB z4t(o2*1R*3by`SSm2Aut_<3dZW8_6`U9Gg3%^KwC?!hZ6tK@lhz-1-k{ljCHGm)3| z{Qw8Kb>(3=Vl7r^uYedCe!7q^h^AD?yFg6EB{cCdY!WcRFO`q#;tMUHZd(yGACdW} zv}*izw(D0M_8H~gX!Y*+Z3JSQXF?t{mR?6W;jqATL(SVnE6)&~ z(%lAzS1M;Sctuff$1UdyR&$y;#Nh+(MV0dn7-AGlOKms!K2!*Nbp!EQ zGpRH2{npOooi_*x-5YOrE%&vs?tHqW++`+~8NVM-z!0oYi|{YrSV6)NJl5lCrGvUB zpYY0hMvt?h0?AuU^%9foBZXwCO?@VFr zBiq=GePZmx*!iB(=l-^Tesll1k4I+S=e*8&Jzvk)`gTnec20H0f8VJw2^hq9)qA|K zzc>9tzEPSqDg$`P(R)JI^PlC$#^~a>!laew^m2~ExC>$73P?#xTuGhu=U1Rg_Btu2X3D*!Kuy=C z*L%QBc@y9Uw~zJVwRNqVOrvxqky!?VAs*kiYbFo2o2%<9wO#R#X1(|qrDHx8PgX^5 zYl^?O)EN8rNY-AY4?55ouZem7*WjR#Rq1Q!H$*}?wX!oqjwgmMbw041jY~~!PPZ}Rz zJGm52faqF5)EQ#NIZ7LTNz*yy#tVyXUT?eIe#nYwlKqkArP^syhfve&SH$i?I#QIjL|3 z^p70^Oj|v_CAUuc+%>NW@9;jSPJVll)Q3l780{1Bz&Ck!A`f_4tDo}S)$TbHpMEJ< z%;~Oc!bn%zE`MRJZYr?qTRsdOvpI~WwXpSfoheWzfg9BeTDpHN{D)6o)Pp zk7eJ6;dKDdMJ!?E`L_9UORKhvd-ppU534H2b*0Ci;!88*5@mq8qz;00NaqZ*@nt7V z8XW}-YLU34X)ao2LHnQwvlJoE$?VQNS%$g=C>`6N^b-vSzn-s}(ce3ED4+Pe_$|94 zIE!NNU}4J2uQen+L&fl*rUvjkM*oN^tvU>+yL}Bb!nM@A7YJ2_Xm@`;!Qr16W?y?R2OG<6UzxwD5yA z7fi8xZXP^LY4du=u}lZR(uh^T{=AzJ;>qq1Xp266mv`kYl=n#rv;bX(f0AOyxr7zh zJQ_oFgl`&T+wCO{LetxAl~_H7931TgVfndfeMyCbUr|z(1?r~i@b5?2iYtL3qk;Qf zKGdj0piaQ8^>k=vyKUvsq!S zf84l*Rhu7>c8h6oVz5IezLUh??MPO&i>S*FEI(Pmb-o!5l+UYgF=Y*@lNH$X`}=@N z@POq)!)mSY+R2h|jXOFi+9}By;)Kk)eClmjO1dC5=@}!GjBL+ywFkzS*^XXL9PtIZ zt(B`GINy}@{L}K`rZeT^mn?+CVD4_6gF+3!U=%dW+nyr}@PczEKy?|rmi3P919a^^ z`_Aj}7wWQazs%Ex@sFw_tTao;CHu4LIarVGsVfw2!6np6f)j`pLqA@P@`O}*#NT?l zG(l_Z@OhKJ??*g~M~!EOc&tEq@@_vg04(dUP$)@G=L~I)x>JI47Jmy~{8Eseskj9JZk*Kt{LsE5+(gLI6a%uW3 zs{QhB`Ffi9b_^lwrLh~GEfJ193%y?b*N2W{#9 zQ)63(&Roddh8uQXoiDYXiN-uRh%${D4J?x$I5x5=2`&F8`ht9-hd^pUbj9@usLX|e zwfhFzZ~~#EF`VneY+99YrtyDP5wl!uTl+NS15vtDdeC|_cE551-;Rex?N{y%dNz^9 zSUtkiT=F5SyTA;oAE32?Xr(pFdAs)G@-xevfBh;KK8cW(zm^X5wIYcrp8htoM3TD0WNE^?O_ zxNA5_zR#;1lhoV!7VyraUif=#%z#%iSodIyQ>)MM>eomoll-Hu#klR>d}-GdM!UHE z%I?#+m`c`tV2=c=dIhVujtu(;q=)YW3U+JiynuSWD2t zH$-dhvF3~9?8W#h;MYp7VN;c^*l;G{luTn%EqTPoj4EOMTy6u6D<(_W1x5ANJk6Pp zak?kAN^)aQ;Np3hGFRor-y zevP`G+%O8Q0aL83)G(O{4W+m;VAv=-~;Fyi*1dFmv^t+3gk(JH5zr>9ju zRK66sDZPd-#?(!y0UPl>F!$K$Y7PzM(+1b_ml^hD4V%|kaMvAI!vszqIshlDtEzbJ z0jte)XLgDoWIG|Gy6Q*#b5=jO2zVmYnRDeK$!TOPKOx$laBNzK2eKJhVLPM~biXH- zMR$}OVZgQVrpUpYI2jZ?f$P*e4GXZG2=a+7xLf{=HJUDB1b} z+N>iTxF?-ESg={f5sRpp01*U09|jwpp54*YP0UR=f@O&=6%4w>*go^ohq(?IEg0H( zIK=Di*F2BW$JxO+SGefLihNU~-y!uwm+iY&;(W;MJD4 zatk^f`*us%Z(2uV+4deM;_eyYIOeILb#5$$ z&v+vg?>-}*dN#lHux$+X8Nl$rz{Tic9R$A3H5+Ant3`Z%xXNtq*3GmXPJ*wE$Q>tH zXkehL`0qYD{+8&LidcqEH$Bz z@>R6;voWgH`o8amR6^)2*KfH@Mo(KAp^)J3^%a`g&i$@D#oh6Rr78vgIBxqs_M4Q| zIT2SFXv{B+J*d3vgM7JokpJDGAkE(9Ow9WX3~hFAsy08y$Okgm;e0Dnh0VRb=Z+Y$ z3jgi-m^$m2YAq=^4~!?4xVD~+?EV{UQ{Lo6Y1aafsG|AQ~XlqQ1?=wID7?RTm!r%MHPW|mmhE&`jo`d(u5N(SgyNSJHO5vqds62R!YmdmzTW#2}SJtv2qhOaExyydGpwND~)T63SpnHw2E*+ zygtBl4UvOp--8@(VtfQ9zPVU=VDU4bQOr>On0rQRe!1vqWQk!^#J~_A5CJDJk03hq zHE=A3iZnCvQG-ErWy(f9@Mjx=kTWe-)j~IO^M4p8KVMvmGOU!qd@k(6xzbwWjXykH zEcNX)TI+~%u7C6R6w%eybSt0a8&M5hU|4hnp*EYuiDllGb?36dy10$!D_4H%#8$;0 zo9_GG+cVN}$OKpJGkBfr-ktjtFudF*QWwOMWrKbm=0l2tX|!$oYh+PW`ysfK08dahnKn zTZzt_jrQ*tgUg3u8IIr|0O!ce7(5!Qi@({Zrl*V3ua)h}hP=FLXS1?tbbST4K@lL? zvn(th4YnibMt4Kt|bFYh4`j*gmcw%KZ)#$vp(+gf77y;Qj7URgO>a*{Xf#Gd@(69+wzH_9GeFA?%yJs?OQ>tX}n-v&}ab^~>H4P0J2VgTNUV z*Myy~@BSS#D8}_YH|c+$7+TdH+%nTMoDZ|K0%QFAN+TaEIkX--W$k~Rt6|MiJQ|z3 zZIBwH22C@(l;Pj7sid91iLa0J4O1>}eulV@Zy9`)%(apS38emtV$3?0oL3{UxuT)! zb2k0^)GKK~@|FXv5`sNW`Np#e3;9Ns&a!xBrP1~p54zsQIh!tAK-r<=ZoHKlP2?dnueBs z&IV{&Ut%`)P1W`vFD@)NcM6ng3gKNeVFjHx`@gRw>>TIMMHS?s_4jmCJJ~GC$wxD~ z^rW2_il6yDw9miak=<`b;2NA?to&COGC%*lyE0K(-5Y|odw|R>jU?>|tWRfhzY@Bo z0Zb2sCs*eQ%!O!Jn0wTiyf=*6%yP)x`_NY%>&%gq~3YdYZy3Q%L zrg~xqh|a&`FR0?elLnE1-+P$71&e*p)8Sx;h#A~Glga}+NnWTkx+OOevMKMiODB|7 zA2hx}%`rlMIr^Q>Dz&@7lgswRVH_dL>xXYK#(To)_nxQj8(mMuZLT!@=4Gb9I8`B6 z(b8#Uq_h~FW0y4Tsmwfk3yzvSBaD9Z13yhDaX5b~(MEfwphCdMR6JV1eG~TDJ>l0G zJ<6UtNO1Q~_sjipkgfic2hBvL@xg}`*2-tu{G@n}^l*I2(I4op$ka`cH4Mc39iXdJ z?0o_Ihm(M-cH?v@{Am(?z`p7=3l|}#9Tv(;idvduia$Pjb(-i{G`k{qnDxM$d+t;f z0C+GY6PyqymZ)N+0dv2kGg>xf4^eNUv&=~d6<+niIS1D}k8?`;{Te$tp8Lfi=ldXY z;`XVMf4NsXqD2!f5xR~`H?oSdhL9#1y?Vjx{gb&uk_ZG>D>;u9svT(up`Q;O?Z-JH>=d7dT*S z#O=TdueZKli7tCqU$PG}W42c8TroH8Pq#Yli8@zfWO8=8aGrcA~<3;u} zkp&WbmoLA<&xr<0yl|u=%QLQJd~%|jIdP~~GCFZ`&D-f*@gucgrj1i&Q>#XBga`1E7BPUcRips=)JexP_vL?jbcSblxezQu@(DxxWH}vH4tcw{tjUrrFu3M1t z-W*dCZtP14{`o=Tx!tgnb((|rllrh$x;r;UDN0w$?gi7a9F9S;3t@Jx+$6N_3m;?) zI4-<9-G!8DopuaPq|7#x)TF=tEZKwA`?7xR@k2KLBalx;XB_I{azNn%T;^R_7U?@P zEz7=!ZLf?ChD^>?>~orrPyG%Sw$eO5b=mBU_h70R@+eBa!!89gJbU+|UX4ChcTFOr zQK*FnWaeK3W&AU?l$hii`!kTkz|OP>WXDMYe@cpJx#{Y+T@1&fcAdN;DL7iHDQDT3 zE2rz)rUFbni?e=~$-JiWx1aVu-mGz3VPd)avF!b((S#zM{<2FLV=;sGq+o=}R42$u z^hUg}P3L6Z2_4@nk)md2l->9;gb+J(Z1BO}?wZIdnTfny)Ed!=faR3y@w9>HNU)8r z%7J8eI&+GOZ~XVu!KIFuCRYi+(p^Jj3dwZI3a`&q|I-^$8w5EQ$bfX>g@?(6h6o^1 zDg(o?Yve--2{s}Dlg1|h25wQ*)@M=QOxA|y`rS5|n5H>qz8*A`fg1Nz@m+CnXgyrM zTwyLtZDaCwgd)7>8wa8-4{CvvbqU4^wRjykZsV&@BonP6r)fL)^y=Ji zu5dQowH8W5OIM3tC{06{TQJq~Z8Q$ghAvmNkKg_yxcl=fkF2wZp0QT<@zDqrJJX*9 zbz1cAfO*heqU`%QSvL{r^zu#U>vzcLv(%Ehm8i1p1|$ERcjIqd4O8EG^iGZ4Y zVnm!55?b(sXi|JcJ~PWR8FEM|jm#Z8je#srJDVNt#}jd+Vgm3U>jel7BoEfrN&`<%j%82|b;{s( zvckARXMsK03uD^YvCeZn-=QFploqhwY|NaVs?ZXm)!0F6effub^08~6AX-m@ATJE_{}_c&!1FXvaOAfku?i_=byp6 zxqXRgB-o&pKUIA%fAy=SN9YnK!RGVEC%^VVf@ZN$_XbIaXcS|utH+ScYo4=(e0ELN zkEQ&p$Rw_&cD{ZvWyfslY2)pl<~ogPZgnNn{u`0&pKvx)UCNwXnPowP>H zxT(7O!p;Q`N|EShO9?na6zdo?MpxjK>g8vWm zB00&J?r4(&C|u>FDyO6#b;kv@#bl}*A&84pMPpOqQ}wIM=b2vlJ#F%NFZvLOD}z5* zW&oLlU2vhzQdE}w!h-E<+L3NWR-G_;9n)vDrW*a2I42^s%Kz)r1Ce9qBu^YQ`Qb#{ zJ7O?nr~t&?wsvPZb*`9|jx6=uYTD-+f4R%sCQ7FN)dKJsC@OL+%ca09*bN)|(4?v! z@M({dfbE#3Af~!5>z+XylZ|YY>zG&_M0?Jr1y%nvw9Vr)1>lD688Ud zS;E=SBC7J%%f)Auvkjf8OoK_57ron32`V7OWq3_5n~j+uA)Uw1DCKsVh&naLkHpWx zh}nDoCWZ)&$1-_jCg-mPg}#O`SEji6F|SX6QYh03`mlj-;NJHMU5B(iG_g^MzKAXS zS+-Ney6b|!87mr|S5{bf^fCRYO>hrdZzq9ph$3rJRFp5lv76YT{*?)=v=v@k;UwU@ zcbD6`gt)khNzn3n}PT__cyvC3VmCbq)(jQNLqwB&$p~t zaB``lG><}APP5)Jcnziyfkt@zioNpVJ`R8izrMC0s9!j_&=+x5^*)prE9qG6k(9Ng zJhFh(ug86{W&e2Yi_}`WNgLIcOTyd>&(d^B7>5`6nlUH^>;8L%>?T11Be0zTe$(B= z8g=oZt{H;7i;6>R_TWno&Ahfikww$qct&%XI~R~fVnN=j&~(>bhJKUTTCt>i%nm_c zFv_=lD(xb!CD)JE1a_s<(U2W+tXCYnHnyiu_nI{PpuCau?a5T+%Z(3-I+72_PG-nY zM$BRv2HQU?MD55NmQ@8s+59y$%{w8kf%^}=p?~UVB(He06pg3)oNGkxHLzgMM?`HS zBeSq`t)*V=AKhjDTMMNHyt0Xa*RXNv0rf`Py3O1xcoO&u&oYRdgPvIrZc%t8`Lg-oz0SVlbm^{Vht4BtMk13qJb~Ae8D}?dh zB!-+>F$CLap$-@6(kItCtPe`QvBhC!9li*Wl(|?m+YEEfX6Wzh1}4QsP1oxapsPie z7X+R^S5r^ij_w>J@=mht=+zLOhZ0ovMk@qn@mB#}3NjOhOp&lfXDSk3@vru;Rk$hn zE3A{DU+@gY)OB=0Uvn8MiP7f{5KRiWw9YF@f^^fNSjKIO4m zcUF>e*c`Qf#(x!Ma$tqofXZ)29q74ez98N;`NpsGxnE+TPHv`!`x&P}a>#F=sa9?G0`RYr;+QqgI530CSKpjX+o3D$TN(q8ZpFgMU~P*o}zB;((G}g$2GVG zqu_MDWT))h;a}%&@mV5l$7Xo8j{CfKPLn!~NsZT=d8B_hbSm`Ri8cBl4Be>pYsW@# z2^_;MlB2J2u$8-feSPE0jgz@FH}5Q#;DtOvj;Y`yi-s?M{H>ebdBVVhD?Z)`gq%6- z_4k%pmoRAUciwM3OqL8J_qPN^k*0r1yZajwC6eNI(WFYC(Y8Wj4lJQyo?E5U*nzD&Tw~ho1)khnl;3N>xb2vNXODk<75RgXuW5O9s#34-!k_9-NpwjCCx`w@ z*Oo<62l>3-@ctvx6 zWR!g9Iu&PmoV9LcL(-(iYKOyILqi>Dr;fJPVWG5}788qnTrs9<;2L-4)waQDUbyXf za^7K|eu)5GQRRV%T4ncMwjK*R}cDG`6?kc^V!s#=**nr`(dcu;cyhRWfjZfWdXE}$RxY+q;_t4PSV&IWM}(ttLSiKU(eQFr-@;>Z zKZs{?al3h9$ogga=vSnTI!6GEA|Il?v=>T5H1XdxyNn~WP|A)gECgyrYZU?#)+w!N zH-2b0DKgT;$$4!ZhcvZ@XqnWxjwepPh}bBY4qN%>?{2$tV&dcj*3NWZVx;Jo1TPH` zlPGXETSlbyphs+m08l^6vMhf;H~IV1JEXYTn3crA2ZEnI8>^n-YcJaHy`gay_?FN~ zCjb4>o@`Sqs)N>}fYrLj6Mp%;SUQn6pXey)L9=rp1G|N;Vdl){RXc$ zBA3#{W!mAvsb5^#(7Y5DxG##!qh%Z)iTg*nI-~4K7Ki5`SZoyId`CBYOX>Ce1LWcjfyz(Um~F_yta+v0mv&Nmo+%Qc8EN4@ktbo&eP?=lU}HlI z0RC1;_iiHLd$=pP25Jgnp&f&Dbh96dS39=`!l4O2gw{z4lklsXal1NO=%pSm(pRO zC6VAg3?%c;)hBGtIsA&!rRhHli*M&RE`j9+a?IBB#uL{JTKS&WQ|{_wnFEC`ns!Jh z>DKz!3T|DPq#GCVeLazO>T|`w0Pxo>s_KjH{Hy4tnW~|7at{5HOoH}vX{UMi&s(9X z59qwQpZnl4h&qH5;D|GC`r+U7F$|-^vt{ z7%$qER^F$jYyt%08soaImwdUm@DR~yJK_NyCz}*@wM$wv znf~ozGS&EY(#EZ+Szul7z*u)?zabnRRuT72#=wz-BkuEcqm!Zu*HP5x=rXx0Cl!l8 znNjRsD7r!dNaQff<5#%#7NS0C8bm#~ACjKSn!z+G5d?d2d`+R@$y8&qYZem=^QnEU zbG%{7Dn0bAG_o`$BCq7&p!F~oSt~fUaN=^xH7)GlwSU?==u%0u`FuAhPo$MM3{rQtO4y!z6XjS9(9l;UQjyC<#)Nt z)3!~a47fcXgwOlK*Ul&auZQj8*#b6sEYT8TQ@MFz(uTUqe^T^>(%TQS!ELv0tzf9Dt8GV$sJxdyo~nRirCYgn$4*9 zzb4Wn-nV)mD99>yDKL1Ww-dI}<9Hee{>DubAiM@?3=R;MzUu$d`SB`p7Yx5^$Ifux zr_}~FA8^WcMdMNbU!yb zoQPscJcIhTDgS78ygR8-@Nsd&;YWRFPe$n8@=Qye)a^~UnFo->jigo<#**Q1I@xnD z2=h*5H9^va9JRJoVM1cjzWr645-hJipGAZaD5l;a!#;vRm)%=Aic|6;tH1UlStPE8 zjhFw6Og+uvv(;=~!p@@&J z_U+I61k+w6B$1=JUFcAnh`?9F*O+B^r&J|~_O}JWy17ZA=cg?$g-7SBzOCH~G%fn1 z@Cv6EY(#}R^drTE(gW*OUmPf7Ts?ny)K^pocEQAEZ&s!EuQnAkBVOwu$!-dT{!W73 zXdF{mJxQ^fY&hns6~s%DLhFO`V*%537t$nlTmU3oazNS zcVVTM?+PpW{9)-b6?N6C%%Kn?#w2j#G)bZ0Z=B{MFCLBtSXa@eu>6{pdfYRfKZkx0 zJV9HVRR3_4!jmd?e58Q48XRFwGD%f5k|32XY(-8kU0Sz)Ss_ygM|0$zh9POacgh8D&cANVs$pH=+o8w(uSc5>&q!%A=dlO z8(D7=$IVY5s2s`8Fe=Gz>x0}?_P5Eo8Qs;rsi}-be#ic+eFQ~tD$<>WG?XQvMM}(? z*dp*I`l>#e9JTrW`Kq+DeSG6b<#eBs1O$s6k5w{bYxz$hr<-Bw5hd_)#3}QX#sGs7Xc7WWS*~-ehLDwgZ#Ne z1;#0GB`$_Bkc%v#eXx`iaJxs`%;+RZfs>hRUvA3jXcitT)AS$E5sU32UxB@t^58B*rOj4zkOlg=>taYQ^02a(?k;KM5{r8ssiQ7Mw+F zI9_J#nbix3TECCughjoPpW#f3O44zgMqGQ(?lwLbGYG&K*kmz=zZcbPUm}*kvnD8C zxD7G}?pUCB&IKa@>>VZvbEYnt&xH_{Z46pRXcGcrFYTl^8GT$QpPI>={m>#6n?2br zdda`^$yCfVVdaU6Hdv6-)8l`dVy2}v&uZSZ>|Hi-X28LNCsq$H&vv?5JPK9aEiU-P z7%gzSktas0I2PQa7=%_q$ptgup^!Q`nKy5_O^U%je*y6wmf2anV9{7fq)1Olh`=%% z!He17$!xrbbFtj0G?MRQXT@G=(n1pNq|3u#L3ZiKC#0mlxh=pAttyfM5{uHog)F%Q zs=eIjqZ2*j*>mh9Vj=17+26FiMooOL=Hp1Th@lfy*%76yF{&?2bs=jP}u-RJ4W~9 zm#DrrH}n3VgXZtpK=|2^f2>TsJGXCgV2*KJ&>){Qc`HLibXy@qfZ(TiN>4(Z>#W?f z0&ex&0@Gz-+%Um(PB|grRwg7N#chA`f@a0Yak`AE3z6m2-lo+_@6S>Ag`mq9^Adpu zE0MyETwGE@|G)8!g`dC(*qU{z3QdCG88&Vw_xB|@rMG~KN&V_Ww$tpEooRebFOQz8 zpw*iz3*S=N3Yx+vkhfCmpMK`>j7qbq6)_^cxHX!Ulo)M~CXrSOPEOWMt;s-fe#Kd} z;NBT>`QHkwYlc{d41?ArDmhebHsVCOr<&CpWL^hmTo6rbd5ymtKoKaoEwDoDOjy)? z&5ahmOW7D;-( z-RpADi78wvsFDiDHt?TsI75!?PkX1Z7 zj5&4(w`C+WvU*sJnYs&bvITz8q9C7I@u52EEL!c()#!>c=ZTs;#mn?LKkV;IBcMtm zKi$ZKc|#Y?Zm|TUNFBt50~v!T*`hWaWLUo6uPv$BQvbOBE^DL3a}?DF+N1mI(9-Jd z*3s4^6K`NI$pR@-Y_|mk2bqVuq|Pnwngs6Le*3p>YMq(~0#CCx@hwjU7wpr!>zT4o zn-BMr`M`0~M;Cyc^(?!B6~Yk>McxnA39>@E1?ePB8E9#u6_Ei8<9L*l^|*RlfHH2< z^zhBeFv*v*egK&M-457bWc8>`2Mo#%dXPIM!uuk4S4x$)O@{m$llR&3Wz<;8Szq>b zJ~PqH=WH(PDA=0)T1wJuu9&wCDgN5#dInr2QKh~7{Wz?BpmB6wfv3zvT~}@c&6v(-D_vTXou}DdqQ@Yk>3ZiLqHW;u zW->453rPYiJb;0*sVkN`VBzPxgGR^TA&J|Fg+h z``&!i|Joz>+4k}#HwO%($`_nGkFx)^Y0izYp^g@*DKv?82{o=S%>>-^)!Ocd#|Fi6 z1Y0<<3JJ|_{I2c^uSc3lIP)S{B&5%e$ZU%e9VLe%E$j5bp?1KOznkvewNp}$8H5I! zM@-)NghE{rOEByo0kCm&(<(SqlLXoIj<0l1|qDi5r5DhXgiZw(q_4*xDh-imbd6H zsgC=Q4cin^S+L#M33Vxy@}pKJ(waI_l^EXv*Lx`r`xKtryGJPV_elh8e3KUiu`aU- zIxCN#$Jyo9N9tH-6gMXqj95i&njk#1of;%vRp`ae(SP{nj^o^(%DU3C%A4Px0E!~h zHif@lFknSTFv$^$epxB&i%QfVbWu`YB3>z?vk@tsRgzh@;W*GdKDR@A$slRsDL4a= zwgMNn17=moj{>l@sAR{JjEhT1B|h(q?!>~9ufmMr-1S$FRQo=NnlSxpOD=ts}ltS$!Ig;ptg3rpXmd+|(DWbw@x^bL0FQi%) zu~?f{^|l3Wl65tySu4hLN#t)Ea&$;D%PLoQFoHW|;t_tDBTF$dt`X}90Uh&P`Nh5& zoaKL#5y*kA%j}K!xm6d3f75;;N55_A5hhlba^gbIRWfwZ^qLn5iV_PI(vOlBTTfr* zJo=GjQu{tt(Y<;s6Up5PeU<#fcm%OiqMYff9s3)}^(~o&ne|psx`@oZGMQS+s(jfC zazD7sNVdUUh}1?V{ZHJNJ74S4b=mWu{;!!oLf*Y(WINq@gzJ>YO8N@7`XEc|+n&-% zCVa}07ZGT^@V4~AVsi7=uNdwv`l$y9Dt4kDvVg3CRr-L!qEYJL;cz27>qxe#<+R4J z{hd>(F?x(kiu*Brt?fY=GJx!T^gAaJQIwpkc&4X=4=P_?KSiY z!_{WJhjIm}yG{7=L51jm=e)IouRVDyQ?}&2^OC*Ok`}kfS6tXd^d4|hvFp7Jx-2B* zJsv^jN)&OMC+x5jEtcIZ0&mQ{{=mUeH!XW$@QoV07J{pouQ6T=aO6->-fsAFBD;63 zE?&>)V_B*1$`@H-wn~J(-b>Zwic!3zl{l+9V)3&v@%CDa0n^|@*cF?r+7_1=pXoVm zoNZj5HhA4bQ$3CDJ;z(sP1{Lda&^|$Y=m3j>-h&lB85L6m?;#|4X>f1x@|&c$cWd> z0)?mkMZE5Y`HR7ZLth)NC8xUbrS}YOar$5HS={uvWuThTIsC`z4j2_=J7)$}+5~0T z3iiDsk~Pa0|70WwFn_!zi`hf^>mYv%yy{Yoer(os-A);T~17mVhQAO%Mdw1t6 zGf5504iPtEQU7aL?m_=w&6w?BasHl>X#r%@ACNI6x#>|tgv-CGrzL19WL_W19~_S> zp4U3o<6vhk5el0JBN6EBc;+kPu%AJ-nA>MfUEaO3mI3GP(6Q<8TfDEG{5pC31orv% zELBS~=xoU}BIO#Hx^0AMbwFlrDQ85?Sy2dZ=3xhyAFK+SPX0vD9aDr30oD zv~STm@VU@^w5s^oXTgX|d^tuUck+XM`v;A%c9Y@^<;!`_#`Nv6nSp++6VPuPY{O`o zKcYiMi$D8MU~7{eJW?HGWG8Y9)~?Z>^%TqR&zl4#T_%@`jP@p@FbN8$x;}ee$&p*> z91Hyg0g5vhKD;}l|Il!4^x?yxdYkiTmfDHcf`T6n8a@8$?q&UzKN@puam#zPHPT!s z5mQpFp10HFIK$L8S4=rLMn*b_@4r zZ1u*}DJ&3Rbd?*+!_B3uMQkU&{KtF!dMUV+6;U#zW;<+N17?tYi18S%vk@cn3Gp4H z-ELT^b@2O~sAd*9v7)g})M!b&qP{4ffH5#sg$i!P5bsrIOeVUlt~L!59~1ITAquYE zyc`WKY;*h)JBPUpbb=4X;j`N?o9?7sO)wSnFBR}!tH@7>}~quUW= zmF1Y(_Kd>m%t*@eK=WJxe{n%8I!mCMO>F zSW^(2qlVX?@pE65Uij$h$S%|5J6?S>U}JiS5sWmo{p>xgBpaTV{(6ryYV5sc-`>i5 zZ(qk5JGby``i-&=yGEiLt+RIfmth=Slm2iv7<_KRn-Gs}>0b*dte!9%A}9L?9v0>a zdbWccO19a)Yt=M8&)ZH%RPR`z_c4(xG3=ZH!ZZBXqjqXeldbeBw#GdJ_O;N__q+Jw z4_JxT+O(dD8{)^?y0UwVx!ot2Nh&fjvVEv7<%@p@nA_DIC9K2D1u=C5(@|$5RE1af zSYXs{r(h$e>HcWX%~fCdlRpmK{rR&LWMpR2U=1RoHg8<<92ndu0b`MnKF?0bq=jQD zVxw3cBV)97C_@`~Ji_VRK-dOU<05zxL0Z80=WouH0D=yFK|noTO4k%x*d)e*MNi-m zub%c-k7Z%_q!N(Qnitx?aL@e~`&?>lzo(z9DEJI9rk`3qKbI$gnRIJOxU#1I((eN^ z8QBy=J8Uo-`*lEhJC6e&jq?9SBsAc=Uh&B^^(8(16T-x zb1#3p4a}c!@zbT_lWUt`a#zkf8GhwV*D?UfkCD00b1*(c5cIIQU2crslyaYC`3U=? zscR|_U^Tb(<_!3SBsI7L;t=DF*fd%*sD$BX;b zCY1yvB<$qzbZ(gtSFG=lpk){KWjEV@+DGhN2&s8pgy~ih)F8AfhTW^nh z-M1Ie-WhJG*gD3@GZZDNUU)S-KBLJC7VBa>SDA35(F6CHU=+ri+moN->m+dmT4?7p zR}qdINzE~1PG2%73butWfWJ0l!6le}!hUX;V4SN&IT7Eq80Lh%T(-=UE6Uz*)l|s# zap2qI(%+|j24&A;nqoijMw>nY-y@^nG_shhERbj{-=}6ABMg1dJz)H>9roWwt zypUje&U}4hzNuv+r z0cgJLg?nCTU$^|&+KB;+YD_UDS`fC^h{v`fi5%-iwWa3T3BM zH>bqUjRW%Y0x1l1pRyN5Gtqrfo>B>9WKXo+W~v%{gyB zeZ?7okIYRll*qD7Pxi!cIm;Y(8Q%iW4Ua)I|% zYn=m@!I2DeTIf_u3n- z>pw(T<=k&w;)inO^&aqNPwe{^%vYGNxa5|n1hssVVlL^l?^~;Hdc>U8Ym|fhi7xZWEHCJoRi4x_Gd1&>)o$vpk#T^23<`IHMh`$?0 zufRO_@(I@)<16zpfP1jkE9w~R7o)yM6b3M)Rw(S46iG$J(4@M!wLYm?{mm@rmV);m zncV}|iEJwtE6urSG<#2~vAp9iD&U{>{D!=inz7~FT2+oSOej&Q^}sXV@l#_jXWAMr zX$Y$?bHYfQCP*p-nNQ$v@6AtXOOe_|H(GQB2ApwWd=TN6c9qWmaQ# zQIpkKN@i$%;-fRlwDUl`#ReZEhY>$5}3Y#BnE!)o#mfgO+mlG`;vdxGFItMw7%z(-`#zR z#SyoLXH_f|-)1hgeUOqs57bmgJsxZZ_DzU)?`{IOK|L3f05Wt?9{$|u_{BUXK{!jk zQI(7=D1Wc^Ef27@MQr6wrp)5t7|GD-mSSYJzaUXZW+rIG^(Da1fRtIw1!1x~#^wfr3-rCkct>+$>I`^%oU=e_%V zXP%v{o86V-yo}uoe-&3f_8@#8 zwpW~=Iq#};c0cc3bH6Va7~Wa}Yn!>s)82jBXte8f>37wwdLY%mi~V-43#nCovgMj` z3%7H`-6S zD*CNz)AJ*-MlHZP0O)}2*Y}){dz^M7@imCcz~Hb+3Pd%W1tt;@V}s?%ED+6LX8xn; z=<$B}^^#zXXT0jTzoi;P))p6UP6I|iFy(3g)CJMFz=9M18B_U+^=;>Pf>Jhvr>mdK II;Vst01)YYS^xk5 diff --git a/DOCS/html/mcu__wrapper__conf_8h__incl.map b/DOCS/html/mcu__wrapper__conf_8h__incl.map index 176d1f0..e12aeef 100644 --- a/DOCS/html/mcu__wrapper__conf_8h__incl.map +++ b/DOCS/html/mcu__wrapper__conf_8h__incl.map @@ -1,16 +1,16 @@ - - + + - + - + - + diff --git a/DOCS/html/mcu__wrapper__conf_8h__incl.md5 b/DOCS/html/mcu__wrapper__conf_8h__incl.md5 index 66acacf..bdd2e3e 100644 --- a/DOCS/html/mcu__wrapper__conf_8h__incl.md5 +++ b/DOCS/html/mcu__wrapper__conf_8h__incl.md5 @@ -1 +1 @@ -1c98e33b1ef479b3bdc56bb1c2a8610f \ No newline at end of file +dc8e0a55410ab62b8c7abe256c206337 \ No newline at end of file diff --git a/DOCS/html/mcu__wrapper__conf_8h_a54429d6d68b1d72ce16bab374e3ffa08_cgraph.map b/DOCS/html/mcu__wrapper__conf_8h_a54429d6d68b1d72ce16bab374e3ffa08_cgraph.map deleted file mode 100644 index 30ee7f4..0000000 --- a/DOCS/html/mcu__wrapper__conf_8h_a54429d6d68b1d72ce16bab374e3ffa08_cgraph.map +++ /dev/null @@ -1,11 +0,0 @@ - - - - - - - - - - - diff --git a/DOCS/html/mcu__wrapper__conf_8h_a54429d6d68b1d72ce16bab374e3ffa08_cgraph.md5 b/DOCS/html/mcu__wrapper__conf_8h_a54429d6d68b1d72ce16bab374e3ffa08_cgraph.md5 deleted file mode 100644 index 7e9934e..0000000 --- a/DOCS/html/mcu__wrapper__conf_8h_a54429d6d68b1d72ce16bab374e3ffa08_cgraph.md5 +++ /dev/null @@ -1 +0,0 @@ -a1d04352ab0ca450d2e1c893b544265e \ No newline at end of file diff --git a/DOCS/html/mcu__wrapper__conf_8h_a54429d6d68b1d72ce16bab374e3ffa08_cgraph.png b/DOCS/html/mcu__wrapper__conf_8h_a54429d6d68b1d72ce16bab374e3ffa08_cgraph.png deleted file mode 100644 index 3bac598c9370d8f1cd6b87af83a2dee9190a7c5c..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 3934 zcmY*cXH*l>x&?zEh!GG}y2j9@28B>XK$;>=Iw-|N2+~O+ARs7$q8M7}NLOi6La5S| zUX(5nT7XbP4IT5syMOLIv)0V4nRU+Ev(Gns?=RBGQ0D>*4+|X~-32{eEfYGrGfcF5 z%X5shv%`X!4DG_`XrQA-M?F10*XPI5(OtZxr=?+rPF*7eNAc}hwQcS}0!X&HMDV@W zqi2r-^=vrx!5jwcMr?*zc^`O0T~|Y1e_QB9>9Dy-fEmQuM}x27LdHIY%+~s)J-(2M z)IT5TjkrsP`ScTWQNM{JSP_L)LKkAlFgSdDJH{MU3)wzV z+jfGdAM|#kG_?MAfRzlC=`ceuUtiyVF!8&nxl0kBEryg$gl&K%lay7yvsv zyVbppSG0#Wv*+&6pe7i5U!%S2S~R|gk%Ggjj^4FB$E9{|W(^X62hEGzNE(? zuTkd>yO-z9Xj@j7%{3qtNjYm zV|T*Yqt&=WAAjQhXAPSj#~0yjlnSqLK@5Zb+|TwJ=O1=`SyVwcsDv(RzlDGKEJr4( zlf}33^XT1q(nrbGKDs?LMqN;B-*jf6_RxY)6YEw>u`bL?Fut67OYCD!3T+F^^l{@1 zRvz%Uxd*Skrrfx&X4Z5c1^mMb)c%R2eRYF|rKnDq%cneQ@zQsnJA)QLKfB(BmqL?9 z-K(-LWx@>cIAJj;o7Ed0LNMFY8ht(T?-~a;f8r2{FR;vjD9q0FnyVd35U(&{69u|!x8J>^*CQhr@w3@NV>#hXj2Gg{OblQGs z$?V2Gwqi+ahCXY3zfk9_-ii{zk2;Q(MuLkt%hm~~j`b<`^Db?m4ioQd98F(QQ2$Nq zVwUO7-v<{U-l@)BI!)BB87m)P_zB;Hjn}1N*J1rB3IUARM2-RQqmdO(5#mLD$&~+x z&2WStZ}x0@SmpKNmqo+WjCE>sjTe@S`5wzZz_gIhzac=L&-pr;7X@keB{$-7sxRH& zl6&i{W4$83G9E)?EuuTIsrvYsetnOP$rIBe?R0#mH`zp8&ATz$Qnx8%|1K$%i`^wG zDBc(xnx?GU2nEWYe6oqqqtuqLlDm+(>zY?J z$*c};GM2%dK`d1fK56yxrt(gI(gH>}4?0gW%1r5;oSY(Cr9ovTBq65k?CkNL)f5+o z8~x&_2Gxwdbp(8@G_*uoDU6==u)pgGn-kk;1>KdKexL@rI-aXOKp$A$)n>lyg13l! zJZ8oWmqU);A@;YzY}VG0vz+XD284vLo)iU?91xSx)7yKS&)#pLf!;D&_BDhdu!`YI z%BvQTXaBS!iF{+fk{gl<(G-N_lU_WfB9+&-nmz)8!jyxJP7eAn_TQx2i)$0XZ@@jM|A={4(M4$i$#r3L9u3qn{ z$;Y?>uMr_o3?t!_Xp&R@V-fVfe|_U66V=Ke(wS*hJG&7VJTmR|cv?E1GeWn7CJuiu zU7n#((U2ag_XRCzoJZy zFs2lwlb+L|qPATzjw7>bIoeb~(urntQW(Qe{xeaYLJBvBlSzuwBEJ6B-himMuGzXAHar*@Zl&4?yXDT#9x06B<&aQc zhfz3UIuE`oc;Gs}9owW=nsXOPVZm5L!S;}wRYe(V*SfYAn0F_(Ck8q&Fi>^0b`Ti! zc&s!cVkfJ(s_>LELiS27&OEpTm(8gy|!%vriGB_hHZD0bp(dCbYyrnUNh6zj)Zi0vbA=rMy-TCe^3TO=3bb&cI|~p0Msj z<}~iZ#J`Eep){MK(T-8Ff2Z_5eVvl+20=qGxRN9sP##NpAMsP8_}Kd z#PqMo-~%A-KTzg=tJ`(c_Gk1lvFkDQWE>IXLJsVgwpoR@Ylh3*rdyE>@2=+Bm+AeL z%TZ|8HLKh7@Jt&5r;?gZivQA~`87l1Jbk-lJ$Z`*b>ZOwU~Uw*M?}`m)Flya%gg`F z#oF`aS}$EMFE1aX7KbF+Il}OEFDXN;tgJcwhT}j%HNJG!fL)p2b{$Qtt8OAhw#c4S zZEM`=Ur~9~(ejCxmvtDRP`%9_cG1XIUm)*TbVG^0%|=h4@Fy$^q<-v9A+j+{%=GdX zfteL1(Kl#OEE4XZyKw*heNkvcQ|0sV(eDnLV-6K-S4sw!?rNHj82wiXu=}t~e()t@>YQTw2k#R5LMM&oK#8mW~4fgWwS|RBG zb-nh@>RV8IGh?u)aj^_trP=D!J}pdv3a!`|whe(|pe0jv zCXg(PgQ)}&dXw&>QzO;7UD(H6#OQ|%4r*ubr5BHlXmHx-u%`D{s zXku@0GZ3r8$IClFM1W$HXo4bJy~=Srp07pBVQ#|H#~z6uP7Txe7$&$%YEUM~#_A?S z@o)W`KC-Pmf(1ydS(-ym=WO~EF$R-b4PI@|CULwKsQ)#oS7r!lA>6otf2Skn`oN~7 z8|H`Ob+RoyWXG_~A1ZShHO zLH4cx09@#4ec%r_muk4A++)~_1s6+)@bbA|JvRzbnSaQ*@nM$kp=#AoZw|k$YJEk| zX&e%A<(E`8H{cTe9~HUJx~c1zK7)7Xz&}w9vQR5+PKLMT?y^$!kQjnV;A4^dj zXI1;{`C$C0tq2F3ppUvh1+;~Rs?W7Lsi+MPhnpbkhivkT?3?vndC3ek8dN`TO{e6h z8D%TRCcjl&j*_!iX1MSB7e>JRQ7OTG2Lr%5tZ?)i^2Gm&-oaoC-_4KZ3RSbb=9$b47@e#?T%9&q7~0CFu4z+ zR``(mFXp1a;X|e5c)p082pE>r^@0b5Ib4)kEAFawz5V!wEEPHNQt_Fq_x_}boI`)H zNjF=Z_bZvZ|(CJwmI)9 zZ&rLvvq&isQF^u|R= - - - - - - - - diff --git a/DOCS/html/mcu__wrapper__conf_8h_a6f04b162923bada308d9668743425b92_cgraph.md5 b/DOCS/html/mcu__wrapper__conf_8h_a6f04b162923bada308d9668743425b92_cgraph.md5 deleted file mode 100644 index 1f7ab15..0000000 --- a/DOCS/html/mcu__wrapper__conf_8h_a6f04b162923bada308d9668743425b92_cgraph.md5 +++ /dev/null @@ -1 +0,0 @@ -580328931482f990def39a798f199152 \ No newline at end of file diff --git a/DOCS/html/mcu__wrapper__conf_8h_a6f04b162923bada308d9668743425b92_cgraph.png b/DOCS/html/mcu__wrapper__conf_8h_a6f04b162923bada308d9668743425b92_cgraph.png deleted file mode 100644 index 3c05a17dd46a239cf291bed7739feb50b8469a52..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 3633 zcmZ8kc{r5a`&TqdAuS@tyjk*+T?|c)Zy9EWOxd#&nQTd6!q{FhW1Wz^vXv!-ls(H( zG_sA?2-$}048{<~I^W0j`{Q?g-*c|(InVu^?92j1@;2LaCwuKlk-1G;aBL~wBq>zl@cWMJeh8gbL?S;q2MXq@<*T^nl)x49zz z5G7t*>fQ&N!`wZF;KYPi^AuSi?x*McA>&_oH-Dm&F2pkZqgCgR+Xvxhg(l%9)Z$hp zx8Y%d!hA*CpeFwjSwkgv*=To3ot|^3&?4yUzapAxrcSd)lHu z&NXWe*0a=&-%7)}-bDPn)TNyVhY_cXZIzf;u7TR^PxHi@nwrYSBd)!CJB z4jkd4e5wT--l*4hiRSf^P5k}#$>**FFf2wuS4~Yr_nY`2nh)-h#BAkDbM>)79b^(-~NB6TdY;XZWbl8tiJ)h=uxmDZJpxaU6(e7uQYWX zU`W!u0bQtHqx-Y#^WkKF>!h`E8YbtyYwd0~AxSiG@^HcSf2?VyhV3Mj&*50ZQcUmF zbbFXXZn=9w|3N&QWaHqwJuijcGu}u_4MbxqX7r>(ciQ=c+}>|G(ii_TzSs;=EH=J_ z%2gXK^)BtI?W{?zC8E4dNF-wGfSbwP-)nBg%NxctX`0xNDJe;Cdr*l1ZReuQ<%=Ft zG>1c-$hD=JLY%vN`;)4e#e8GIM3k!UdqadtGM0%J_LGsT=&#MIjd%kCD=12`3fqu* zgqKZA%oE&XA}dK$_Pse~bld1)z4^$=iuV;m`GdV~Zs0sI@TvzRHVFN!@yfS>4yyb? zVeQ8Bc@j#;bW)0@t1x|CCgcqJ1P*Q@Z+wjdr;BH^ytz2Dly;-ejJ;{XlF920O&C|( zjmRHMez|k#R1XXLVy&r%vJ`)Yak*5Iq6}Q}#`Hwl&-AH^kYm{O;UEDWKKyBRSmY@? zNEpjaM{w^7MNU1TX_sfbqudgO$g>1Yy`Vu2cy@(Vq}n=cb!KV|)HJ*5gfoa`PQ|mV zLfa>fkyq=rK_ls}GjExa;!xgw6RwF8sP2!B)L7LF3< zn_$Uq{R{|;j*gBSyoJaMl4A+Ax6^a&>-H_GceqBpB88y(;!)wtAgSi#hC04{3=PNL ziHw#`0S8sAs!GVE=TSqkqMa+xAKiAk&ibKL|6-#qn)sU!Fo;}qzYTZ9^9hRDYH-9! zk#()UW}J`Gy=J^0QJsJro(bHDyR*wj@$OGE({R>)ZczKxLHyuB{ogY?F~r|Fe$jV6 z+tRVF$e82$(jF@ZkMm8mU%L#ok*9GAf@-suoJB^$N=2O6@d$!U^*~n$|J*IdE&>(L zrF`G^cxC|TZ-|`FN;9VTaW9H7A;Ubj|il3>j2m4V6DI%<>_+Jo>e#_cc3Uo_k82m&p_5Q|;`@8)Y?_@Y+h* z$Jw*nijb;GcBkf~YSlEf7F(7*Vf}>L$hpXbwFI&02cq^GQ)OjhyxHV&`a^60E_Aai zP2DO|)=u*HUuX5&{-DKQr66~ryzBV&ncFu80zLlPqzw4-t3$MAnA){1uaXt)i_A9P zfs=@+vb&Q~!7U-HO+4A0WkJh>gR|LJuD!y@7zF}2lKIH-&)`<4nYxhbn}|FT;PZds z$RWrSNyC$qlNHBFRCR6bA>YsXeMyugUvf^WVa10M=kImPdI-d|e2M=DOJyRpJL~q!=%~^7_jR}ot$kuH&?{wD?n6Tj0fUStqH54Gtc56^g2Wt5eQ6`6+_qGj zg=^VF4GT+3N?I+(6xY$Ty3Zq_wkCA12eWT2r-X$P<7Jb-bXPI4r9-t@B_KPf0nMEe z3!@j(%`qMiWaD)@mxXYR)>V2LnzliTl9EZnv1DVV)UC9k#Cj&Vp7;!*rVfP?>UC_3 z%o2pbu|(pz+$$KrXd;m~eJL4G_+zQkpeYMvoDO`E?%Rka2~0DJjDQG`)LW#KD1Kv8 zrYUz`1aNEG8OVYZDF5wO_&Vu2vqpjcV{IsfvzVy7TOSjni^$9N+Xp68vP+rL4NO)~ z0%vjj0IWh%C8-PIFUk7v=>s;%8ct_fBAKgPox&aXtjt%U6zgit>?IEvzc_16&6g{cT3ZzA-Q* zwrz9BpnfCOLd2>u9C6}L?b|OWppeXs9`pD%!Er2S%yaw6XMD+imGHvt(>${8-o1lc z_==-%V=xCdMWUF>*97D+`6feR!DUX9>%$&p55(e8^jBqPG7bo-@}&LAx?T45wTAIC zB_HGEotrfyN(G#cjLuLc;+$@QczK;3znEc(a^R2OX4*@s>x)~|CbAt>rUgU8}0$iR5&uZ$Kg2KDnl zZ0(a)Umi)rq1q83t?PF+B*e2f+$`A101(&Y_>2ZI8<&25lG+EIE^>Bve_wDG64u*m zyzhyDT=QEr+iS&ce5kIgC`HBho7&7-LX-#63#`h7J`!HQ##a4m3`0BLX#dSJl=v9L ziR*cpp;Nq6?d|%}KvFUo?Tkm5(B2O|#8a}NY{%j!qoO=2KhIyRrxXNVoa)(@4fZ%M zwD3|1d!fB2v()wRN0q(_;13HA#3R-w9(9!~?o{7Ae_Z@%1eBkA z^ZQ8&6=-D_>rTjbrP6Mgsw%6<)>&9+C=7_^(-Y8l0k9*w?D#L;#m>R@Cv@$(FsFDj zu0MltBGWE_i;3U$-?bv8Axy4!s+iY4lf!%*R+mIjNHIRBsqaVR!blbW+J&)|ai1}J_py7vRbmbT^6vfPKEC#$R@>1ks zn#b@ycnU{!Ds8Y#CCD?|t|#Y%em4J`Uvm}aBQ?8CKMLszj7R3)727%MZSkLm@IH$R zF9D*3E*ZiowPWN-+|M$=KC%z;<*4D#xtDKvjBX1>@aq1=jd<-%^t$O>yx0?$F&)Xx zt8lw4%cb3=!t0#nD9@$XI;VYXq48%l+++E`dnWM*tb)Q${vRRr+#vOfY|}d2;|+Y z43xJ{NqjISmIh#p=iP2kjJh_xHB0BzJmP$^pdtGIk^yzjlw@s3& zX;r6;Tfu5IBy@ybS+@JO?RxDx{oVHPVmI8UT6FJM%zE1{c5lR0obT819?bOFhlC{0 zIZ0`-)Sx@(1r+dB@SDDsSq$#pSb0kXJ3?E`P1Bp^=EI1+tOi)Qc6oe*j&uCB7iSEE zSUKFt65YE>MRGrD9^W=KwEDKG>o+L=vrj}>7z-<~!X=3W0RWc>PuVIWZxo&u5<&P_>2>Jn&RX(F15jqlkltMs|x|#H9(??DZ*1LH6i_akG z2lac(CigpbxNdO@!8NC`bC%4GqT!%H7Y&ihOQI<>bhou6JNyTCyi12@Uj5e*utz9>F2e>u`kVX&mZ!iOS+OUv^*yVY0; zGDQ~DRPYCex16C?9Kl!DMTcrP^nI8y@#f=*b$7TGP)it?r{r2y=}cwC!}KBV%8ja# z1n#!j1YJ#Gz)|H+R~fgM6ncVvtYwni6Bt9iIt#c2Ln<+&iP(Teqd=RoU?u3aeV0fe z3jO8>W=KlXpuo0>MASIIH2^VKHzHjx5S4H8)}-hhI11IH6})p5pb&b5OLmB85{mSA zix8V|bLS3_6zR3SFgwiyIoYy$uh$1y<6i}Z=LkAJ3ejHW9kT~=KrXZ%2JzvR<6r*; D{q`zf diff --git a/DOCS/html/mcu__wrapper__conf_8h_accdef5b45f3d1646f248304e02b00e54_cgraph.md5 b/DOCS/html/mcu__wrapper__conf_8h_accdef5b45f3d1646f248304e02b00e54_cgraph.md5 deleted file mode 100644 index 4db8cf9..0000000 --- a/DOCS/html/mcu__wrapper__conf_8h_accdef5b45f3d1646f248304e02b00e54_cgraph.md5 +++ /dev/null @@ -1 +0,0 @@ -3ec1ddf1976b3ac1b4b5f81126e1f0ee \ No newline at end of file diff --git a/DOCS/html/mcu__wrapper__conf_8h_accdef5b45f3d1646f248304e02b00e54_cgraph.png b/DOCS/html/mcu__wrapper__conf_8h_accdef5b45f3d1646f248304e02b00e54_cgraph.png deleted file mode 100644 index ac21abd04704e2a301c9fda55c1a51bedd227536..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 57178 zcma%jbyQT}`!yk;5-LiUA|c&fN~cIkhYk%x4JobCB_JjBk?!tBVCWgTdw`KH>3T1M z-`~IQuvo0cx}1CBiT&(nAA;V!mBD>T`Va*L1y@d1QWXW|UL6Vwn#X-i;5VnIT?fDq z%#R8(k|@_VU;i~`N28!TN0F0!qwbotIqUAKr_p%5ckH74qw2M;@aH(Rb<~)UYDmWY z3AFd}5MPHUYL8K;X>f_&s7p$|LqpyV%#qbFw<%m$8CZJa$1BHhVA>;r-LvuiZp_5Ux3R=xxo+BKR8M60OupU3T`*dU6Jr4X$26N5;E%n{U$$ zPM**yGeHpHKL3-*(wzUzTa2r1Hd+)`q0hMXC-HaXAXGj^;At&?r*(*4x_+V}WO=B| zL&cOqBZQFUQ$)fg1F$lw&9d0o*j060_22k6GmHF=PoRZQ5IY3sBTV=c*K4nKn6M^* z$JQ4_qpGRdSyaDG>Vy-S=5Wx@_vp``KcQ1^?^e_;U+0(nF<~+~kDqTWO)YQI^ra#E z@KE->HMyHjTdJ~?URq}xZu9$>=Zf53c?i`NayTCU0!o&0D&^k+Hwvqv!xq`%aeuc& zmNJ9!%ot?+hILpQ9Q4p&lDSqPf?hwR<@q+C|$ff^C?#?&X zF|HuY#6p*@GlQ`z>}W=d&w^@;e0WW4dV_19UOP1*1ybe}U8%rrAlSKb*7$8Jih%Jc z!ArHu{)|hlGUF(|XbxzU#czATae9?R>o|y+L-?9-T)tIok>lLBxa$8*${<@SZiUdQ z$V0&ey6l>r8S>Y>RM~TzLJ8W4#$O!}oL5HfN1CVB{p{>$YOi=KRpeN#EFgR26(Kwy zIW9bTF!?8S<5=x(D;VNGUMvageLoGpoC-9iraJE?I8ZG5$mEk5O|Q+tHi%I7hD%-7 zX55`+U>84^2d|RoL%g6f1@+&u$QontfknkewE5Ar7Uyamd;I2^*^sv&B4VZCK%+wa zf75=*Iy))SZTeJ-B~IWW$1p>r2hrp7__eHm;|5AHj`o#Bx*RZPebf}qa1USGj*eMB z88n>;(|EQMy)+D3(37h!HcWFFaM?Y}jAl7Q`o zgSTVFhE#w#a=2gYb*6_ue_&jWRHu_l%n5NkZIUplbN`ZQnYc~deWrx0QJf-JZ@k-M z<0SiIT}sbCgPV9M>>SeU9MG?Ftw+t8P~rC^q0+2Fgi-=jWVL}J9!C*{j?PMKpD9GBIf)pF7&rU`4FM@IQBy~W zZVlc>q2lt7O&$H(SPf4m{GLe_QCJtdvgA)BuWv+f5Y$Tcd`qCcB!O!O3kY2c^9D+p0u z{%TUbm1#Z{92mIy&v`$nWNZ3CO#*jVZ~m3te&Im3AhjuO7=J^8hWSB>=|plWnVq;1-9 zWI`WT|LPTV4(}ce13Y@vA4nbYy^(7(jK2})d$zxgH`}g8l3|WY?O&XYNU`MJ+8kC!7HVaYOC1E55LLR^M*-K?~ z2x>?%z0EYC=t|Y6Z$Drd(kz5*TiYSi!Yyq&m?tR+q-d!7`zbHB-r+q+2Kh#ypBw!_ zw6lkP!*b_6XeBr(WLqzw?vTDc#YoQafvp3(B6Mdy-?|?4{tpZ*Pt}25 z<|I%*Kgk5eZw$Kafq~!E-$=kbM**)Kf}aW9oic-((rnYb4}=A#w-B($Z>Z;7aVY|f zP&S)?4)!BgW`oS;aR0_)#7f-MT6Pd$U;>svbC(!o69hJ#y(M<;{XoDbF^{pJ1!Iio zN+Y$B#xieO0_>*x>;jDJUf7%bf=Y|+o~KY2F&IfkMm?3Jc>OoKI;7W5emP?mYpnh( zmUtkyfbBlp7NEY2&+v9@vk)g0xAnU=3q8f>ooX`PJLp}Vdg-S`ullKir19q9WgiF? zPP?T1zQ}H?ZDE@gs7{Ach6~08W)ypc?I?+PbAs@TuT$oBptgdmoVqS@1SHA-UYp~W ze-YSX;WRNDT0Xrxl*jgqI+Oml8PR+b*7!1o0sBmHQ?SqQ;UuA4#2sj$HEq?I=b3w{#E;w@DLz{JAj`MAoFPYkd^uS~V6@11tz~op zGqRF;4Ql6*k`KRI@iQ)${GCzCIY8$ zN1oZm;U#-7j7{#=cqfUNOUTK_Ve;JLmJq<)=ATGCW6=ILrwl^pbAz!CPA)vGrpfYz z-uHdgn$W4@1W%8h#$(fQeV6_>@{#5uS0{*uUGX(Vn*!bKXoS6>FW=V(!FnhZJY$q^ zxFgH{yUjYXPb`1$tJyUL?1hp9RA@||=^c45N6K&lkWkN=0Y8XVA@=**pS`nLj`lB0 zZ2RH?$0SP+r%|=JgDVWwUle{2qG#6)Pf_ijCgxcy+!*gB>H7noP()vjO>UW(OtMS{ z`CZIWr6Co(>~c-Yd~ISxKCJ_;mPwYAbV&a>E#?P_BryXfz?KessakY5deFq@N>PR} z1ui?(-SVr4up0Yt5h{D;C*6_$qoUE@2wjRSi>qRD4g$Y(-62%!k%6t9%(z6K#(w_% zLV3f_Qa#ja|M|Za!$$~?fhX62r>oY* zLusQjv2=8Gsk)FTcUbV*=XxH;1E~co(~FP)MV;MbjvP>?mGL0;>}NIJj&SRTG9U(1 zTBf4RX=OTOd=9v-GaJ&M&deOv$CnbKmp#AgUNiWyB%=^|mH!T5GhGE{FIB7TVs>n1XYP62<8LnPX?kj(5lX{YLc_?MIc>wtxmNtHJdv}TJ0(O6Aq6SN zB4ez1a$+_BKUFcV`7@-DAnN()nM4SUQ#WngAJOy8ayP2GbQ&pax%nreW)Jiq8+W*t zj>)lfGK1z2%hWRkdwLCf066OhoxL^AnfEaGV%!0ZMDkvos&~?U64pyINtA%ol8TMm z=Q_mZW#g?-Lrn1<%zK5WNu4Mo_oQ8JvvGI8mWxKiKp2nd%+u7a<`}g|1!+F@mTsvR zxCTrkxR=J!9|{uusZw+Jd8YPt=$5`!-(Kr9tu&h$MV3@ap>rxo^OhQC~GiT8oD z#X@i2A0kK((poo(za;E zjZJ;Iu}t`#AsdGh797gGVVlPyMA59)w0~l1qJ}}-OF?+RGyQ6EsLe5!CfsE5BP*foj66joXp(md-%R-oPd1ZNKTgF+coerL{WzUB|S>HM%>>#GGQ&Ao2J8pUP zW?7%E@f%a*?D=LDa}B5p;nrT)LzkBn-~#KSd27}ZYj}*#x26_9s<_)RiGF5 zYMX$3M6i=GL{LpM^SpzO==^P1Cb&#ofi9w)!oA|^ppoRFOX+;Ln_Fi-cPh-JL2;TO zy?p$P)zi}hJv+T{Y&%F$Ijbx=AwCZ!3I?g|`fh`2THseLxy8kRVxsd}UgrCbE<@k) z2<2^^qiw!Y(vf8mYxZT$K1(t!pGq*NVW}b6s8A;c3c=g4_~~CGjeLfjPvxH2s6B4iaen_u+m6^ zyi%$6zwuNa?^6-O6`f-xlcgjL((l4P>3Y3~Gr0{1^1%}Mgnfkwi4)zEASe(iMMKs4 z1;F-&htkRP58KSJq)Ibb63MuhKdPPS1+AY+T{aPXKDsM0q$J|_NFB)vCP&%|oB^~A zt<(y==C1LEyVnY=Gb3W^o6orZ@DGDBgzv(CRA@bq^CzwWG!HAd`$>E7>5+VUt|X24 zq5c)BQ3^>MFP|>46J?NT+p+4jk(cn`kknroeGg`^QUAyJK!PvNSGiJiT1mwWKk|2i zJqL_R2U*6s&aA?8v|`)6ZxSUiin$GtyP~=dNy95xhA%%0FZVg zhigU0%8IG5uyB$>*iBQI_la=0pFQz!4D_?ARqk}zQj7JY%OzNlX;MagAz_?xN1|kT zBPYwQv4iHXk5gFI|2)_@9)MAH3p2rc*22sG-QfC>1c&}vWzycg#imNE^5Z9|%A&6) zkgmivk7@!u`L`Ea-lJe+8D!b^mLE+Yk%5Q(`$63=IBD*G4)Y_X-_}DBZa~gnxV(Te zWvF)~mI}Webt&RBIrm^KGoE5i+=%OUJ@uFmZgjnak6l2DDdsxyZ7crl6CI~9nFTCN z!pdr6zm(it$ECMN9!dTm=Ld9bM%>*GPsu`i_-wADuRp})(pT#r#CV6&ev$pjqPJ3y zp3Uze?G6cg#s-#VyQwibE7lt9%Z0{||JW(^s;p=)_xJ&+9b3A(^|cNb|BHo|alS+L zY;bsP7cDJ4p&i|>eDfY6r~JDhm%!!if)`Kn9bU92&inJgx zXt(*@ct+5@aA#<`_n}cNS*Me_wi#gTZ-zZZUw8z8MbDNB`R$Z(R;&9e&Gu6jX~clx zV9C|$>UN$Z+LAOpcVp;TuJ2bL9hKp`D%_W0E-aguO3uxx)dlgD`=~9!Rj@8XFsvQS z7++RP+Kc0$7p<)=F5Lv*HysHfg=&(e8f&^SDWgOVTlIPHokp9O?5P6c&5U`=D_vTqQu1flA9O#S3)#yM5_=%w)v#%Pjwo@iUh;?=Z%Xa(o&VHwF;;uz z_-su~wz13_Vb+l6+nz7CL7mfv+xfh6w)TP6=x`fQI!rSGheoJ$ zeEM})z*54z;u~o|9J|fYw{pQe?SRRRrYFvQmDyxvn@%*;HmZ%oxE2o?F&zd z`Phmo=W@zrSEC3jX7oFXI5ThKPbfC7zE_ISyaS@%wmuQg!#Dj~H#Y)3UsnOyoU#7-=$5^2Tbma1prEc_fJGI~N$kusB@-bR!xM0Y$h{fLLGOXF; zjQ@psfKTkx3C4%k3^D4KZ=+*m+574lkXp6_iyiOoX*lEg+mVE{Dx*T>U@$0!MCk?j z17Y-;Wr7OFzS2(4wO({DttSp@3YFWy{LN6_a-O)u>BgjzrS{n-n+#u0(=dwCeo9*3 zsr_w;uXfAp^t_*SC{E&yNhA+xzB@Gn=hY2?0VRWSbms=26nq4P+A~x;K8CI3XqRA0NZuhCA!U4`cJ0ccbd8BsWV;hkaL8(!UxT5J<0% zgZL)ny#M-wp0%(ND;-9siudc=OZF6P-f_wxAc`2@(GUz4xU-`01yeqooyqo_dfgB} zQkkX0^E*&K`}l}Gmxc8nRGlI*s6nV;qO3LtUgxRC2nRG;z4weeT8{JQtzUgF0BQ~r zBy>Q#&W+2gINo;eCL@62s8;QMO0eu=EvS{wY7KI>o!v~t=0~E)#QgxB7AX}o5@q$i zC_R;1o0eAvWv8w~RRd@#Mw4{I-Bm|j&X~D=P=vQ@%e2@}c`MK~r-*)cK`5eokvS1Q z=}x+h8>$ZL^%sf(JE-%&bE?>+lIi0xcm8wbhGn++Vp<6sy+7B}C3518+f#808s!yCLZsVq`L2J{m|`H>NN`FtMxV zBYEIKKu6^mnbUX0zb2zB=BVCLwJ>BNN_pyDMC`89qzyRo`CtCO3R>fAq4>Z^72}oa3?0iVyYAs_bjXWR}!Hn>*p? zHqw1z8#NnKh99B91WfVV7OEqWQqBXz!(2ZfBkp=H9sRTGnh+LfHpRM-?i`$&26dpd~?3{Do=?^90dMJ<~YfxaAT0h$8)a%Jv5+D?@Trj*@ z-kzm|n4d`iNh{e>Q9Qxaso(ZAVys{ZVSl?saT>EL#;o(lZZVeD&FrkCD&r6>F z5Z9E5yAH8s`wZ_8m`Uz_ohtNn!eHc=TV7$x^`~ps?(3S5zAgBns>e-XY*D7Z9QvHH+S?q2X12p_(8R_nMP>u$ZS9!r{ZpM2Z^>>`=W zpoYtIxkb6VQls)n*aVt=T#%9OR)s5>tR#sKLFl)rsq|M^Cw#aJb2*_GhF!LppOfGk zRRH{Nu(Y=pUJSzUwHO~I|YgnikgmShb=m48sIpgCwKk@>pY zr50)@zC!fz9L0rGUL;OggUp*pjW|t@BZiH4A1(Y!7PryTvuac^>&5!lx~oHkdWa5g ztTkcMYza+Ttr;uw*a#xywt0Fo;CiH1P51}W0Q124TB4dN;^5_%dhrv2-BjM1orYE) zteFV|6F#W~m5lg*Qy`s*-jEJJ^v93C*O-wi`iT}NpwuGf%N7Ii#l|OM|G!3G#IIg0 zcqz`qHzxTuwVgitU+!b;AL@J2!H#isj*{AIFM{pbUXY{rv9kxrfIO4PG(;m+?@!YE*jGFcNFSG}pN-C1zcY`Li?_VT@x4Z-?rPoJJDa zk5Qi3rl;MGRTEmBlwMxlrscFf-@6qX7RN1(Q-h#D$1pF+?+9wqP&)tMema9AkK?I8 zi<7BGCcvTa{_z-Q6l0;>rN{d9Eus=$UZ}GCf0jgZW1$jke54~EN2-V{A~&M*J=QaP z4$hO|WY)Y0NFwi`XbQGoREl-5Xl^KTmx*9Li%KigaGGk_=Lz%jDQTvR%)0k}oR4>< zmlobE-tNQ=8OTz3WDbh+e&JZf3?wJ)WTlLey9nclv{9?CoeM?yf`aYoH2-3pFpOM?QkQO!dBCWsLqG8nx za}2;&Zn@=rt+4X?y-acz57B>G0QEo!v;RiCQ_eyR0?_3Jqu75jTJCzfG10eZOjGiT^7)G(QIz(%=rQ?UMN7CB?GL zfHh`0^4_wJ(i9NKvwVllzF@t3s4?5mGP){rdgq`1g0p*-j?dPGq{*`0IRVDtz?SAh zk}b?)i>FF>T^I#-_R3%(|LX`zK`VbwVb7RMaz1fp{gY3;WLa@PN|QioLc*r?B%Zto zvniK6=b&&Bux-U+L`YbGx>5Uq$lIIB!M_0Qinw_B55RaHh-7uSrrpAcWqpb2Yb==G zsz+WS)C=D!E;zBxQwHcsd znrpZ<%#uN(b^ihb(SB5Wp+_bXB72`8wo_d5hEqhh;RRJcUuYZGoDMl9RWKI5LwWmI zKZoJa8Z^WK#b_0C9{Fu{-NSfviniMz6vAt}ngt|^o!;-pGP$vx1Z@sgf1AY&E~e_= zI>pERB~F6{WJoOnu#pN~s`C*h+N^8=4caQNlRU}kF73(Vu+J*UiY45mvKOfgIwi~Opc zl{)VylaaT{D@qOcLo8%7yUtYJ=8||svt10;<9m9zBH;;YU0tB+%f-?bR9aaL+SvlZ+IGAx}Cg^7!XL zWM<`2zPRb*$f1>zQKM|Vqf>P%O%y7eg@v205$ic&WcyvJPRiNYe?(kxZ){Ve`xjtK z*c{syvrUjp2%a6sZWM{xj@u)!A8E6mAD-zq4|m7Nef)b30BfdqI9@Vk_NnW1o4aCc z0)35gd}5*|TbuiwH24`8m+suqP}#={=Ue~kiU+`G6Q;|;#r#`XcYisHtqUs|XT@NH zfFYJM2Qm>oy2f(SdOCKew6_%$AriZP7}qB6wLf$oZ+xkUdlpZ+VIn`!%UUYx{NOAe z|4*qxK?HFgy?lkir?t$aKTrJ|KE@`BkJsjVERB653@uXJ;kPm!?%PCQk=vm}(<${x zkw-=yx1c}z3iMJR-O=u{UddjGJ0GO^cE=}B=$TW@8c!+9fxZ*ivB{?7k)5YE#Dy1bxr8+0Skr1zMq7WOFxU`zRM%pxqrJ)He4V+DkIbL!6We|sGw(9bLmH) z-X$1G%jGutmQp_JV7$QOOd9?$Sog-Ak#{g3fa9crE<=P1|R zN1lVt1H)}DfRDP0LZin=SdQaK;DU<8m8D!hi>rDZleG@^N>_2k!OJ>*6QqJ)*~+=T zjY18T5BD&P=C!)cJL@h~B+Kr|Q)B3CR-x&GcL=D8LjG2(2hQ-onvBinijI*XU(rt3 zLClR?h(e>b%2(-d?CwKf@CTq#p=D(VLUFO!YlKX>E7hk{u_HBTsBjEW?xS5{oaknC z^3AT+cO1i>SirC?7gEzmz3l2~ z(N|cvLOJckc;2!2Iw`@l@1xHpYMUD-f;FkQrhG1R!^c~Bpx>vJ&P8{)EARW!u3mQZ_A}kLFu>Efz#B;#7;iv(_->D zbagyY9+YAV{V~ zbvHO&#xyr!jVxRRVjA8rW^j|tBp!u{A-F3vCvCCq1gSBGXRJR+#5F(u))89d)wB%- z*(S=uuE2_M+WUz)b?5nD|ErYW_GzLrO`=mAYkwk{74kOI!y*-%;GWA9YX*s>Dc9zR zEcaQ6iEHyI=}Wb{z?1{f9_ic6=uPtmCgaNm^KY-aq!Bt_(CwPYQrlO0O?BTVzK+m* zU~1L>@WZ&Hsa0k=HB@Aee-+AvNwlNU{gL2BW~c~}jwx3i(BN%dP5KSnQ}N*CWLUz9 z%X@y)m-r6;0En>QQZMXk9N}W)h*+k(?38&nD%vLDg?Hgt?9R_d(sQXMaVd+OZ&5oRH8~iwAj23bVkY@Lz@Y}Xmm#K9hvAKPCA z76{hezX=TUpC-q{61Mx$@cy(4y}(N>bh2PIvkK}8$GKW7F|6A{z%W`~y3h9a2t)C^ zWd*qgq^IkdC+BouUZ;dyL6mN7)Gawn$U}#CXk}O48>4cod~2oPTxaFH9i$hehP12i z$h8ofO6fD1Q>`${Y^HtR`i9WqIkYdV(Svy6ff*N!s${FY@(gq#?ZW$v;W2_CDSgOd z>SmwNla_W9R9S={rD{A~*{_zwi1sjJh=l~qqC~NT+|wcue~_onb^VJ95AASWDeK@ea5M0k07Z zc!XZA8(xMx`3JzF2TL%g7BZjJ6v`%%vCN3fjNIONQa)3h{;^Ma5eazFJh}=QH3{W| zVL@g^rpIIpsohfmdC-k#M(SY(Fa(+3NHQBTh1!^BJ{sI=1o6cq{UoqyM}Jqt)hulJY+Rb1YLJYjHE@HSG_04Ygrtf)PYI;D5O=r zKr;i)7@-_dOZ~L!QC~$>L)hy)jAIqsuXJP^_2218BaUUsvN9f%bT>80f6P_<&@K6{ zsfYqNF^vl=mgw+%uo!%K;w<(2S^jd_0DouFdH<=MZsBZnc21-`hi-o7LNz~=u#pI? z?ugX=#d-sER8!FI$a}kagWo!-X=@fO6use9%|x$si8RL+#1t@XWGuFYf zFL(0dZAzJDt5lkfZ^Os^FnzChAu)Euk1ED<8@kRhm(z=ulUSkXK7KQ}yE#*wwgQ8x zRmZF=v6k)bB+A&9{i8=Qy>20)nt))bx~VtS#Qi7JPrrN*moJPEQH>UJ3%U1-vg+*J z%l3Iq<^9}aUc+1ThRBrsjYykq$MWT+8tbA#t*MnCx88%$yCIP9#4v2;4{VygZ`%VJ zu(w7W?^a-s+P)nC4dik+Y#o%te9t-otfjv8gv!!5bYHobW>y+UknzLLi4YYeLF5dV z*%$47@wg6tlI&`}1tPybTI#i1PSKd$s;=K91j|uSSY;5tw$>+`2LOX?rA6@oY~SX` zc3J>AsOeK9FxoK2l(LRMZ`=ONAM(u`W2vQ$c%#2&Fv+P_UR+Px5 z3fdD15a~ZX%j(xtVRTVb6x7A$CApx2g#orh-D23E^Y+iL&u_g0THl!J>HU7!k@Ze0 zQI!cVMrY39wp{6QUA9rHv*4S6CqJr=a4>7X>EX~RF32x%2TafMTUu0tncq!?-gdOy znoX^OWV8BQpSjX+^X||42m6q^7^ILRyWi5rH#q+c2>zS>3^sU8-O3tTa5z_ z9Vpg0+2Rez(k%t^3iFNL40AhFy}zh!FRxsRx%f0`?alyLooYkhX+Bv!vsOo9Tq~Z7 zhGRCVR(Z|Xr*t`B?AyH$)&YSKDW*q@Igsx$p84|>zmQu&PV<$AViRCMi*yjp6L!4= z-uZBy-fVpBaq_;tdWGnZZNiT{Pnx;?l-Xb3c2Mol47{RP;MX0z*M*}gb=OZ)PA|n! zW-j@*z+h#mqzdzAv+l1rrQbZZ)+;mao)uW@J7vOr(;`Ij{x@*WF)h|f*bbcGfy;h> ztxa{LZ?nzR88RZ!(_>io;A-!Al?9?UJ~=VZViR87hG_mg*MH!9nlWL_$9e7gZ9#Ls z#bE03%eiX45wP~i)GgSb#}M`8ULB! z9w%msdLHVUN$Lue)0FU8qi%iYNfSR}=?ry6#p<889s{&Vg+8?>x$NwQay&gr^>`#~ zF_aMoC}xB#Dx5{_b!e|Y{cb*MZaB~vbsOiKY-AC8U~q+GI)%~W|HK-y_$U1g>|)=( zm_!Sw{3Ps3Kkg0bI{&lO5khp#?vPtq&r@hR&rgoyaUW@ybjk6t<@Eyj=+Rd3rE*hw z(D%ERC?Ev%=c05#LV)Tn4PYs88d|XW60AAAbORUR043eADDi?^vFqnt{|oyGl0bBH z97E_z()fGOwOXJab>^L_2T;l{qEXTqFFn1yVA>7rIDHJw5*gpK6ZN}Uvb3pU=Z3ZHasTM#NGargYYyNsoH=X5(2}(7(%+x8xgdA?m}$8t-7||5%r{jUbk_anK=_Y`U_yDnKg?t&CIG!ZrHVx0}jmbHWu!`7S%YOFmfPe2F+%zFp90P&Z_?>K;3>l^g zgEGAhp)mpMN7WCHFm|6``xVKbxcoOHTf?Sl4qE|e65)9PN%@4oE8?`FIscVteL85a z@P*TpMI&{xN}+T2;BCb{=E0$o!B~kf-g>%8hjMj=fwI~;v{ho**Vg(nie(tzd9oRR z1LFXS_0uKXQ@#oMwmMLqnah2M1!gksLY;fX(lzQdXeKO%hInIyd=6`EfozQ)iHmkx z-D+uE>U<3oIXtclQIlfa=XzI8`<|=fF{a@?2P_IdbJ37D`qHzabFGP2Cv`0}MxIw8 zUV4?xOOMyEJ=%n-CpM4x+ty($MLbDqYcmyP%M;PaD*w05=vrgt38_FA%u@xET-o8$ zJsF`!|KDsg1+AVDz^XX|AMdZ=VjZxCis4DMo@}%SB}En2iw1vx z`ghBX^%RawEGyWwa}D5!L=}o>3f$!{qYG+Js8b$+)~g-Neu0{tAZ%ILa4h_s3zg&Ub{ zUejp>Ao1dqM6^=vb3iApJmYYuPijf9NRkEsJVNEMw&-tjEok=uO86xmYv&%rzw|*9 z0ZlgwpK**mGen>+jh91JRT2-{F`)rjfBr28NV0=Ape=};VTw&D2*DPY9;}H;+Q6f4&bVb}i8G$vieza}p}_=!5!FEz^x6*EZyl9oB1R=m(b3su$Y2fW(ROR(bP1vy}Ck%*!K9sB(o% zt!grQrEipCg;U=-p_^jcp;8Y*PKv_Vcj}GDhhNgr2z6*`f4F~rt}CA=DB}smX2Y3y zY#osjoygCuwPqXCS^IRtlAsTq01`-MprihaU1Ujm9VJfHBcd-wqQ_NDdPe;R6OtfV z+U4B_isM;*?e>&B2rN7?i{h$g!jA*iW-Ke9P<3!Lfexoz($+-6Q7YX2kc6r}*vsHP z({snH@XF#F_O;YU1Lb||3@@;deev5GCKCTCl)n&U<7H|S)WyzmhKe&M7;Cd0d%i4( zT8(NOF2ofFsC=UMZV}b@K=t0>U<=Hz%Z3a@wZWIi{5>8WUSR0UfMl#|58%+aiw}dt zrfW!CZBYWM$0wc&01)TFZTeNE{v)N?^QQEgQYN8zqPXAH7_}a!iRIjQy3^mF=powb zV`O?^<`aUSGqd@1c?FLzl&mlvK$X3 zoKdSt8ghZMhb0vMm4UoqJmq7g8J$0$;km%ndC;ENcQyHbbA3zkskhn(=nb#pFFpU~bc74?86;dAkom2$=%J2|j+Sl|)k{-IJltGOw59yLwiYBP4gH%GBhv`) zwL;l(Y#C6L~xJuWV058hh21NFO1)+=(m7F5MlQIU0GRio;;PgcU~IFq-?HFye;uy13o zr@J()BFD7c1x{Uiz{LOLk|rrE30mgEXlNGBi|== z2anm!DvsW~#)kFIbrL;%tSpIthoW(SPT9(czCf2mIEtz51XPiW4)G^}qm`mfpd3^b zqZf(&-_|Sl`^OUN^#c71iH(gOX-&Os>p4|q=`dbn08&4wG5u{15D7Lg-|aqbvsg0R zmJEN^dE;Gg{taOx&xR<&N0dy|QQyF+gHlGq#Dea;fNuXL3%a1}l;e7?&c&CQ0Z+@K--tbKGic0rq6K&_mMxz5Q))qd4d^!3zxStS zYeteXarK*8K6=yvGkvx0`qBwdSNUf9P8$UrTgSHf5@#dyNH=Kb238)S1C>$l-^wU3 zLFN-0wW@H^)nmGMtzURiK8T&8ABS24;wPs5Q(kEBk!3yC=L~Aj+Z#lY+{~N%k1(Of zOK`|@*u4o+5cd3)_qp!_A@T(rBVl~9|9&ofILK(6GC+al@BATn({d~Vy96>*;fdsr zIDke`K`LaK_#dKgV0rtDn|dzx8M~tvz&@x-@QIAAG*kRI)R=_p13tqh9cLg(ZDP%1 zmfg6$6ciRv67$?1sL7wfxDa6U7o$%yo<)AR-6y%Wud^qh3+*hUcFfc~n#qRLEtlWx zVOZqjqVOuhS07t%ZYK3xU49{RKjpS_vnF#2OZKwSeE@C{b{Nw<&?$D!i+F^Sc&HHo zu`uk|F!Q{rka++>>Dq%p*$-c>J0@~#Cx7{~dh-t^6D8Ul%q~G`zv?v>KvM#rX9nWj zvaPbDI;L9Qo^jqoNr%O-MR{oJqT0>%7mNo)zN?eGC?3c^(-*Nl4?KE5m;h1+7jqA1 zihS%9{o5}^61;b;@bYma}RNA_zuEMQ=m-+GJ)R@XXdL#=8`UPXEjS+pOd zy8!>X$ycV-5CyLO+ACY)A3a;4d`|oW1ljWxB%RKVZ5!qj}}`hy7^BIzxm3Q)gusb-gH`{G!R%@Qp)augs zc>t)+o1=+S8KCuCtKvP{hV0n!0gxB3C9=i*OY!>8@EIu3t!YuPC%coIe{k3%88$J5 z?T>WkGppm^#2)#V{L|!4BdW1EcHDnl&EIR*5_^f}!uST6%Ov4u!``(-zi(}sL~58q z6l~;^KdTK~S~BwCVq&c63gt4;|Mi;~l^(~&L9__h;L9*k(f*NEXa^ddA&1*|uu zvTBI=wEs*8xHX8MzwjJ_ch6K%ZxQzPrJ3hp=ShDUWb^dZK}c8l%!H+nfRNubw*Eb+ zknc5oF1fQ)WBi=T+Y?5kgw1VYpRQVh5yMndg+}0Ip2>}^KBJ>)*-gXnnV@|ojT-lr z-aAPQ25wy|?eAk41>Dg?R&PS2EL#1fR)!v$s65mkQvG29LmtcE-+$3dlhBtSHwO=h zG+j;FaZ5F(OE_IVxJ>b`tk|_M(&JqA4+O~*%4R+vpa0%Dmqp`z?IH-J>b~8EH3_No z)D%UBMv_z0zCxz5RP>~B7@M`t>dO`~a-5oyrY%#Smv7tBn> zq;SHw9s+h7ndG#Xv^cUo+c`Va@gmDAVvF32it7yNrlCQHvapna_rC6+grkkssae=< z45>~NI>93Uv#M5M#7Ou_2>!%KjBC=+G)Ao8bfF$D_MNqQ@ZIuV(frBLIlZ}Pw3g8k z)~+>4ia5}(2NS|eL%WD;K83AsBW$^A`XBj;l~Uy8iypi5LAz&}m_t%ywUpPVl$23;*}a7~Ky6*YT7RTeIxqb5dne&VF_)TWIdh-Tkg+@`r-!svqU#=$dFcmW zaHq_?zTpFJOppjnWZSyOoyD7cbM&=X`4l!TzDfS24Yt-hP3!A8=rDfwCp;k>JWTe9 zb?CDs^!+42`w8Y=W5&UCoXuB1d~dvAp;XXn&{%S=L7>LsoLL7x-jW7IV*fSwNR=Y% zLgg24!pP|BOZkiaiZ$U?jVee|-1T6v(5_z@X7dU?S+TS^J5W!W z)VIDt`6?W4j{-v<%{mM86(zjLU^g_R^!*QyQRQwC} zNn-NG+~&qiVVPmQ?34#SYlr35ppjbX^fUZ(EIS?TUuL8i_g!D5>{>M>^qwUOG8T{6 zj>mC51${6o-aeaZOcXm*Z{S3D;<2>EACYOP^QY|ZOBd&`lnHUUexg>H+@4eU{h1!s z&M`(mlKEEY9V)mdE#_>+<MrABHzclVvsrB|fk%A%bZ{BdZB z%updKde;I*(KSe|zFN;&%2w=PUb_|f zlMpQBU(R+TbI|7=>dlO_Yf#LxM)}3UE0DeiJv)EMe$j}Pe4FniyF^y(jn)ls?g0RR zh64Vj+1Y~`HNJZ6QMWDP9-n-_K=ycYn6L|;9Rf=?0y(@V9WhQY`6WS)HHrjJ$mb<0 zjwxC_4)6~F7HF5T}NZJiz6qsdSS)U>TTuAv3DF_ zn+5D46_N4@!Mz!*&9|5h`9%{&>XA%*BPo^Wl8TOD~%A8$w$u2?hLcbsjb~%XY(Ue`opViTUjYP%< zI}YVJT=r+XU0(f%NJq>QU-bWRCCK#Hpi|VNoM0Oz!QI)%Th_74x^PQxAxycXJykx^xi)WZw)gEOR^2Sim9U> zCK&MV?0)TaOxFKEDRZl(RSv=bMgQwXDn?(hpn6{43BkKbIBy}py97e*P-^VkPjl+F+tQvy zrH8D6J7F1fD%&VY!_c}HxXb$gc>2n?DBtI65CM@Ak&==Sl!lc?P-!WZ?pQ)PmTp9P zY3ceZ(y@eegDkyB2uQ;MOD^5@+`#YuyxSN1x%-+qbLPys*8UEeeQ+JKYGHc-3^mUz z;~8$ilYWV-oqd}@Bk??}lgw6i9WtH4_;B-gnXT?L$X(NJQm{dvs#?}KpIPs>FIdE4 zJI^qpytjsSCi9iwR`e%w>P|HKc#ZPnfJI~Ig+^v3R^gS2Sj3y|?ZmDY&D0jUbJkU? zv~=%9=(RO$uGcLCL+E{z^RhGo$3KruPt!z*bQs+sIHq=#9}<_ptF}GzJv70CGhOxd z6rj>iBFM_gIpT5f1j5rj%>}U!WAle^#VN*tbSIU;J-&?n zP+Yw9O;y==@|R^w=nG+UfbYZdn-pcX1t|_%dUrS zR_BA{S4JtOCJWj821!|gqm}Lmi0jYJ&&^e(v1=l#D6$brMIsM7Tf#*`IXeWmI#M``zVph)zm>I^(*Fkxxppo%*-klk4sk{DEhEGAkx;KDiSLV7*($c~r z=`FQ#1XWfMdv(^afSr=kfTaJ}yKm`tI=!Xh-mmmepN`k<8@pMhX28t*(ujJB3)%1k zmJ^CDP(9w{^}7S@?-rLMueS6X@<-GKq)p2>OhtKlC?#8&z9TWq{Jb*Ei?L0idj%e%s+#Y z=p>ow9(km9HB1E!6m!b-(#>iFNBSg75GL5|uHqP`|_Z>duR`zQzARl%?#1TmWU;b#v z;m*Ohsx8iD{%NfsN&qZjauOf@Ki`iYJau(CG2sj+w`SrCe4+B@?yDz`96e4|d6P`7 z(-r*U5i#4HCe!pP?n-<;Iep5NezE{tKRWU9D?)-&qzdt*vhgxrP~xv?U-6JA}Fd1CYhWo>CeSb<9?o0I(dy2Za# z`Qtr1D7Lxx3v%T3BHp#~a)vkqptg@Ao&K-MYob4Zg7#?ecfg?40kZF@_BLF_zrkcD zvED@YRSaWN_var`H_lBxItkRTB~EE5zB=IT@Gx|ZCrn~}M8!>ymK*t8rjz-Oe8uZ0 z&ah{V_ZH9G*%sh;j4b_=tZg3LK)iM|TdkzoT(fEQ`ZnxZB^ft{2=f5i55nk^<;dUeE z=XXpfO=n#zb1JRE_=_su*G)|mrZ`#oipRlWf1p52E$Q=@z&b(%`T4K5seF}x!utU8 z7s5E6Q*S_0u^!JlI|HI#$6>>h|KK%DAGABTIJ=}2`tk2DBc|&g>k89!J*EnK?y$GVL=tgpQEwLlU#j|2oU^W2$I&R+RDyALEP8qg!LOUbUs$LI zix1JZc*{z|Zg^gaqjhS0sp$G;?miGSjT^b|R z8s}BN?ov`}l$7R*4H)8fxOwDH%?N#mPu`(%5jf3aYX;&UAgPz2bv?ccPR=S@mrhp( z`Pp^E49=m7GHP%aCyUfYz#|9I{@(9;tKJ7CoBLBIrcZ5UXw-#Y&-J;7QkO(mvvYQ( zpd46MQ#}E9Inp47;DntgAO^V+zSSN@q((x8p>#6fxajeTd;O)E)M!{q{zBF&-!Ct&6MbNeDh(IgSSeC$yw?V(>%YB z5x1MO$GNAzq+J7mxfE5LUhjOM+{*;=!On-SCsbQ^xLdB@5QU3#UOSu)69#Ys=N;8;K;4eF{b^Ubx563IHS|5eQJSKly*ldK8{AxX50A?Vkc zs>h2Wix?s9zHkv2_`L8wJ;+Y4!HdH1?d}na!?fuY&(enM(o9LF*2sT{8juiM2Zx%C!GN^n!5r>opC^b>1%kyrHnE3HXkz zsi-Fexje6~C#ipM@)Q+_YHLfQ6>2v8Hki$*~GxjEB^i6IbL5CJ5jw}N9>X#s04 zokxC_Dr|R6kM5n+xq16=R&PT1;Pk2VTg>fzpi}_voGLu(i>8YzscdTbAL#Ifw?GpA z$zvCHLOpxw_{{o7&-2E-wJ^z)>g4rbUCuO2swt{em9TB;+`IsDLajFAQx%5Z)Y_*U{OVv)V*`(>@W;Omh8pI zi?NIi|BWO3l=@%YSClSXu?xf6JCjurFU`Hnt=o$D7D8k)R1C&^9vX~C+q~9b0VzZu z)%@4=$IN!gZ938ZU~Y&^#l5_Zb7lI2rqpt8oj^YJrZlsQ$E`D8Y;3kw2FliUrLXmQ zD-#1v%dZJ^v`CU%uCue1+MxDAAB&=qc-afQEKci#NikITx``LdVraGjOWsTlB$6X6 zs^cnPpB{H_Z&I}0A8Te}Xxw*~-CD`;zgg&h%8h_?Q1mT0(m{&h>MF%`38wcA0eyqO$ za>=b0LkOJcaL8zDw7C1 z`uDaK`}FiC$xxR>ZjYs#UqeN*Ll3O{(tRj@z1`cT5PtEXtSqk}0xeJ-n}tc*?vJ!j zH{&)Hw>#s|t1WYwYxe2DSWt){BF4@_g>{11Yc^{O`;@?}LxqKaBmwV;dZs#{?| zXfka;d>KzCyF%^;c@Jm6bfL1nkDDhWw^x4uK7kSO{56ZcWwL$ED0Xbs-8HeeQqPxpz{3<^FM4>z*PHa=%JigVu#5R&S*I z^W|P4TZ`p}voZ*kwlYm^zvK0wwxYCKLpsB;%*x6tzn~yYBv@`T+40TlCRUk1oUI4V z6QQL}gMYxccjDM;hW4&39YsenZ}MpW`bw9CJZSR41j)CjkBd9q zxM($^*9?{k>Y%;Pk)M`u?pHz{_Nhy4PQA6T0!IQ5*)nhnkTk?X7Y=Tug0OV!o_t7d z?~DYA3r>$6ARLMm>3E~2?osxa${H?y43K7lftZs=&3db;Er_n+e!ltAGn3MAHdyFg zweT`j@XW?~!BfzL2(lirMFChsP+0*{c5P&0 zK!m}=bf3q)?Ov3#1;pZQ5#vG^21WAj-?Nlz;r3d_J5S8v2q4bx3eerZ%A%@V54Srl1#+ZiE6$iVfniAcCHHM+-RmfbK>Ju*6JXQGz##{f#l+;y26)KXxyM zr2VOzoQH+j8p*$UDgE=VF~3CCJ9hHhz1_Z}_HTwE`IDWaNk(AyPmeMCZ^g*wT-9@p zzo}iZD|#q6#om-VU*^uTMafZ(G;nxke9?#cnansJ9)WAxV%-5@;p}Q9ukxWkw`*}7 zD7EM!_n#X5FJvAxz(NTcmO)#mlaGtoUd$`mc@w%DKH3550~k>gvN#OwRE{9gxFMZCP2(?oRV*4Z%Ki7*|fH^Br^ap>8r7D!A8z*2CqP zPF@gvCVW8DoR%a8n~TvI7(90+fw-*AU=Z5CDe%fq21Z;_U340>YV? zDOa9lAc{`lKMCQ<4Tdid1^3gLk8Q|~+tzQ7%q2HPO2p_DEGZr~o>8~7OobG}V0o*B zH)fLAI)6n5rzZRB}Gz2P-0hG!%Q~q8P7(T`a=Bu#E@hu7lVbGbF)Dn}t$- zdICK4c0MG0i4Q{5{s8>pkw^plJ`HvZfjh^8I;vXz7D2<6t37Piflack zVJiigmyTQEgp(}tsyTl@Y>7>f2-8)FCVbcVPxB)mK7TM_u1BlcM++LxA1^o#HU2oc zxqLF?y^ZBizW?EUj3g18UzFPgum1v5=t-dj`j;GDPfy_Oe|>ulkdlM#vf<&5cRny_y~Y)OG~>mc+y z9lQwD8|-wUd<_Gl{L(#Q;rmFB5Xpc%-dS5Xn38o-j}$-|`5QXg|J2Il%?4nI{tWup zCA4EBK20;?6T7k^cQ<(tqH$8&{*D~e&{4};{{4n>Wfy>67&~Cq-2#~S2)hIOsyB61 z7G80C?tw6uY`g22DbZ49R>m1EFWK>ZoGu};z~uZ-c`w(0>mer!p%f!-#GFt#*U{g; zUnt7;fI+y>8l{RtrSK#d$(WCv)V;ZVoJ?v!srMboQ;TXs(?er`3FS>%goMfcDm2%k zcA$39HESnUY8MN6n7)t1o4Y^#U|I_RaH>?WEsqsA>D7=Hv|?S=cHF_7BCNGd=o(HL z;rLAX0klUjQJPk9nDuW}(IIBaXjaB4 zrfdKi$CH+8@_e(Y)DW~W6#)xq=&wb`lK3-SHXgHKJ@-Rg^rbS-72qSVk)UG zU3R~6P~>DYjtP?d%`xW}mbK*B+qPRpvr(eS zjGxBKapIc1g4JrMOJ?*_Z(LXT-u(uMpQ1|2&%7rNwy`sGfLl_}>+vi*QGa?YiBg+` z?2Z_f)LqL!?k>_R?)kB2@;(EWM}zHnPlTUnoqH8fDihSQ%+6QBnNRh)v>1h7X6^(A z?Ap;_h*=?aDF>7qK0`%xx#Y}vPXm0#C)$<#x+wd%3YMOB|9}4e_QeaA0+dc%bV+O13!oy&i`;Yt+ zvAW;QWy!5h2H<~HDDZvFl_7SSOLZ;3Q{sK)@Y>A zeASzxz%=8PKXYgf8hUzReMvC2 z3uDBv{x?Qbtw`tc))%YFIE)YQ~`rUzv}qZbE_lV4m+qp79k-peY!i`P^W z^KEmwEQ-(HMr3B%HS#xv^nP(-DeM$ok?hq6e8F@gHn#M3YFArt;ugA#i!64RD z|3p9~7C0|tbH|oAvg&ZW!fE+EJc^e3@Sj{T@DvW6)n|(H3}t}aqn%saroxv^?jA^m z8b$oT0qHA$ew3?}Mh;vSU>aGW`u6QxCx9yUv}btfakiG19rcG>Fn3{-w;LB;EeyaR zOCEx!w9WrIXnE(K%|8oaD!$a{vV?Sly8Qj#xCeNh?1#|x_QFMbFhG5E_RYRjK*eMl z2Gk?%Unu7UQ21{GgZhi_dICTknbhi5`>!>Uw^br3VWNdG>eY)7vNB_95I4qoURfO` zFBXlJ4py@>veB&(qnK_ihSBoYWJ-?wh5gPaK|6=M)`en#ZMca)B(X#Jg}s5Sk?~EJ zg+Js4?ZQMxjMRbR$36R+Jnu>9VO{x9_{e?l(&mX@JIzZRx3QG*;B@Zf?Er77L-u2E z4y&-6Wq~a~u>*aK&xfPu?ja$H81J5~APVzAgfce}s6P5Q4Ky3+KTH1BVFyFdLfx7! zq0eG+pNfzz&iu9?E5$rJ57B{c5KQujf6_D+uDc2WjwTnUxYvf!&ePiO;bcid3|MNY zTL_$8ohp}8(a%oyTTP4#qMkmnv5mEjWNDH+yA{~Py+mt_b*JD+wEn|O*U>b&rgq@~j%=w}*L$qc zel8+DGx$zJ=4n2~KJ|qXFOnc|q$!dZ!*-?Et@Z^Ddtt;@sC|z=u z&8)qD1ogM21UfR7bwpO7f2RR7S>0%==ais1b9)SgHjaGfxb@Ujsr>b~wi8CGTW+bF zr?7BuzGv-Q!@keFVe0|V`BnX0{u8&UNqb|9(4A{z&0A*CVeoC%J5T@IQM z{PPE=#v@$hK#Jk)pwVaMyZv4W;!mwF26QE@9CNWWw<#)CCqG#O=D`F8h58>dJSVF+ zE`6GWH!ahzq9jHI(=N^A5B1I)VCSw(%Y+pK(P&!3nJk6ZuZcy>*2@#t9V=c!*eYHs zu-wqEUJLpwzv^~V|I`VG(?B%bZM+#k1S^>I*n974Nncp=`|>77?R0`{1~2%pqRgHj zeV)XMFr~U(7Q@B=<5Irr-4lD)z3Y;b2-38PYonH9C~RTW{5JB`t8ZBIN^N_?)+V<3 z=cIgs(qKmBlF7=DsXbI$2op{ovUS*bl%z=4(m0eC%rls-f*CSz(|TfFoRC%oh(RQ2 z{r+(PtqbQ{og#B&@8c^($-rpJuD~tn{kOL+5h{}OQ&vU)Io6ECOc(w8OtolX8u04C z#p>TFWHqd-l8!xaq)N3|)z7dGeGbiqHMN}*F~FtL*+Gu|dw+ekC_h;83}!G9T&*LH z#pW#(B3zzJ#kSp@k8lOHU+!^U`)7f=mA)g!Z9Hj00_c6GjE_+F#afjCv%k$UaUP!D zO*T9kCQV8OG;0W}1C?43Vqse-gg<0j#0D2qv&Y}>fT9Tj+-o2fDcI9`nx@1=Q;yOy zc(;!*_(d~Z<-pu(Ci#K4%W#ukk%CLKLEZEv&mXR$woGfb5kYAj_V6w>F0n+}$sfCG zgdP z!R}WIR%1M#S?J(6xwgw_is@>-AzAr;bsJjZTU6dc^TVkR(L>``1yLnLr1Bw|4_h*V z_b#?@@@5cBaqy0Glw-y!4|DyD`9I495p#K*7;-&fYG2F|8S#{(s zZhf#);ql=C-04{svFlXxL5-mZh{&9P>fi9L-dYJ|JX*2C2fEOmUOI)_pkJE*`2hA+ znE}ouq>6>wm!t*xhR`o~=o#5^U}W+lr#s*u4EZ}IhaYK6o!vT$$%QXQicjg(&PFB+ z(-(1819}+C-+V+kD>!A(z5-#Sk<$L)obc+Ah+lt%qv2rzV1UUhEye6MV2A?859rxp zD91~JmBMBOCwAGk4>~$xB4$!75TxjIpA#*+PXP+dmA6rHO%{+(`AqaiJBqJ3kUIF< zhS^4ojLVrLz;@oP4D_uTj;&$nMnRsvIQcK`?Z+6$Df^+U)wh3{gfizPeWpc5qPPL*jKY~f-GiXB4cko{1Pap-n+ z{3HgtEJ#~Ddztu-o8$@@;|)D?7C@d9&7!El^^HxU7$^SJtcy^*d!d3SEj(9`>@Iq+ z%2}^sdb+ix?Y~GHyo?_VbEZ`oL@ubu?tlRUA58iAH}lniVCwQsR~W!krPD7oBGR`b zAy=r$$JWYTMkMlg12?aeZwT+U$Iuk?XcTQ<5(Uum1tde9U;H`ITQho>JVpdt_G%{P zVyUl6d%P|(nO3u@-vN~vtdNbkT7>Y|b!shcvboIe8#n+E+-i53(&Gb`dzcLkT~jZ; zC>O)KF>Z6-a6&@@?0b7gk-uLE1HGP(m76TBHM36bB)$P<2el>my^*4$#X~^y^b$=& z`14bN74{x48b4ld;94yN zHPnV(r`C^luC2mt4yqqTm@?c31(DwX^BXxTlz!jauO&u$Jkjc`%}BjuzmYYL#;!yW zo@~P-{Iv&1m4;m15(QD-w6?e0k9x zdcgAFOHmS_qF`933H#bC0iOdvIs#Jtp1&Valu+Q$dXIt^4)P&Oj4ghr-y5qA zw9qZPc3wxZOvi0XWMpKqrUeBBDWp9CxU2guyMa3UDT~Hlf{EvSGupao!qd-S+1%Dy zqAIv>!2KYCs-^v(4Q865;@;{&&e*8W=H6Gsm8}g2m%rNclMlR`nkU8xueHMgp!7j~ zxh)>k`Zcoy3KNtooIX59U$s(lD7mM5Dvl7F*QDENJJUXL4mOc3Y;3&X0VxzbdchQ* zQj%XNPs>vVvj?PeIH&yU%2Q1FlBrq;?n~sf znagaT7{%{!IBUbDzu4`GXO*RWj@$HL$`>#GNHj=Zl}Ww~f>IW+pQY(3_u})*h$f6v z+_dy$*hwU(jK-2-M~t;jZ0-=iS**FOY+0fQ4)e;eD=|xoH_OOQU{NYl{$e4K0lSg) zjOVs&V4LY$$2TbUI)?P!xvVh1;xi>2>Mt4s>NlD=i>F(uX=z~3X8A(kYN>i0vxG9~ zwYo{{Hu;4f*5o*|N0EM}G>(nPO3cuK0-zooe|~RCEE2Bh(Q_ef$_Kd8yc! zX|?-eXms>j9xBbWvXazSkDcQ_59;N7(B-?UhMFyQARxvwj3d9@FJlgMG(Ie-W(NmU z_NNO&l7$>iMtPY#xawDbi~%&eG%dLGm&^@He=t6N(7ptr9l@X4LN2cbr449J2{-Xf zcS&pvmd&K}Z|x+vy*BQa#%g-@1`vrnH0tD$j?Y)u#QIPTXH5l>36Y?f10PPl2xaw7 zYV#2~c5lsHqV#RC36>st$M;Z8Q&SUDouup0n)(gHR25l88C;2tbV1Y1A-{D-MGP~? z>tSDXK~t(;x{^f5x!!?`u0v4MP6?;Oo8z^hj3AB>3;(@C{xh5g2kjCh({6K^7mkHsmbVhh(80x9LQ>0Vah?(YAMSV}VsKA(!vL(;mY zI7%6%e^j-(UTxMFTj+|N7ZIFYa9F-#NLu^xim~ptZx_ok?&7(i5LC=HLSSkB9#!q5 z#68`V(FI6vOw~}lAK09F-l(foY8a_@;R4#&zNv<0niU~vq+mtg<5ECPOj26h))K)> z__^{(;zCbN)uv^wen7kEvZ|c&8i~-RY{8#@&EI+SK`K_-H1rP73n1s-G`1xfE8?)Q zW+5YSFn>{05L64mJ;3Q+Freiwf8kf#L?Jqql-e%581xuAHYxT*PDb z1X@dBED9%CA`Q*(Ulj&}Z)2w)wRA-DAji>^f9_pa4L5l&f`r z3&6W7rUBB-w!p#HWC2a@#O}CJEc6A?Gu}{Hrn=;JJgAr%1mv$dA5o8}IP2YfZo{*# zyG2qdOjsyFXU|~f@DKnSKMQ-?Wq?|N$9_r(ha~J^vEUfyL4YO^p$(kD8b5RZZu2r_bm$+V=0j8Ul zbLjdg{%_^yA}dC4nkbHcFXWuSjcvef0d539%wVsh@R+by9>qR_& z=c+rjd8n+)i(ATvUnVRXd<)7!pUOza7D*BynS#gFnxW3NB)x zd$`&nzA;4AF+=0y=0EW=!pyy&lOs2Fajx^ICGenGW90u5o#|M6x1~#8j~(87XX?Ch zlF<^*rEjRhzpo*v?2P(}DCKsq+lYulz&ZqW{Og;g__7;g`R!GAabS@_uWt8G+n-VpCT|l1usY$6q7M{m-q}HzuB*pwSqPX-#+to0&sDuQKhgD5%I$B zA*I|%ziFzP!~3pX)E6+y4PNxeaiDV+3Oh=pHNQtWjoAoncEE6a|AQVNb0?AgMl+)O zwr@s#v)ANpJ}a8tu$LaAeP%@yB)3s;lR>}7K% zd~@r>XKP#&p=TDgu#^U-R1Mh1#Z*ap-uNAm?jW>LxCC8}Ue;Ax7d0tO>qlt6wbku? z^zq>~0bEEUdMbPl&MAIcd3uy{pu1_Q$%`Ac5n7J64{Q)4t$O4D~!}whxtP=wQ z^UYE)FyWvUeW*r%+_d~8HWpStky*fAp$>G@)OBt0=mdh>F{1d9?38H%|Abm_GNT1g zzyNi9qih3+03G#ZOD}yczNZPWU3$_TON@|=Rt~5v7V>xfV^MkO(oKOsERQlGKC2LmH?$*Iisxr0l(NHRX5IJ(h z?%OY0u)G1!PM)?3EvL`rn{{79k?}vh0{Zxm3apwmDcB}%|;!TEH#wi-7VPN4_ z#t;V~UXnhn8|tEok=R_LoId`M$14)~v&&OJB1DQ==SIXgGNoha@OVq#(6Gw35=TzE6=^{>5t7f2^Tlrx`we9l@a9#ym z%MY1%Hfvs{ubsWjzaF~1`o4;tjhZkA%j!kN?gq{atBAQt`WDlnWA9;CcllY3q zo?Cf3tg_frumq{}u05W?v!wuLmbJyYcA(^$Ye?5d?_co;4N&1zDu2d>sBP`8HGPhT+I(~oAw0HLX{sLh@lNv_tpbHSC=eos z|L@xd#k=m{?Y=kk8-N4!2hou$$(wY;F6L^)Aj@jW?X4|4uE}SpZ^$R|4Jehz;Hc_$ z@4$`#*%>OVWMS^=NVCNXq^-rMu$lW|b+A?aSg4X&v6}g_gPLoHmLurdp^Jc=*Y~0p z%ZS%AS?dXuppOrpcJo$z=iyIRTk@>ZeDXB?yubGO+{qfD^pVZzzu>+%ekbNX+@B%JmYqt>pU&MzW7e8ydM>!6m~-EE7j&J*5V$#C6B5FG{dC6WgTmn>1(#>_b$2^j1lFOBO-|e z|ArbPb58y0nGv}KeJRJ~R$7$JYyCQ>+Ag$pLx7$HVS+o zfD*~@E1>Llz0}8iPCIgcgp(RXm|SJJ+L|$7e!)z&Gh*Xs%=e-0NNd~rBHbGrCZ}8^ z{?`@LT2%ZDefItYM7iOJcC=8PwLS$OzOtr0Xxo1=H?FAd(LPwfSv@rZkzsTIH2(jY z(bKykM_LPT&Zlb!B8k%=P+yD}}9C<$I<-c1`U0BxwPy#|zPiohR)7JGPr3J(wXdFFAm zur&3df@d{&RMbx;^mS~GiJh;*!^0C)^OP@Z>-iuf@JMQ)#`|7hufu81$j8j>;v>u& z1Xl|r4G8pqE#$ZBuS8xU?u>rg{pw^-rls#P=TKogv{NYWOwG$gOZlBlV^C3(kv&u! z?cF<1@NDiouY(=lWNi~?G$W`vnitRBezc5Ia2&Cu*e`=>IKc$i1Xfiqs4MhZ$d_~AMvO~G$JRlOCyzP?_VUr8V} zRy_1Pt_0AcZ{~x#R{;WkE?gu~iX-%+YeO{sda7R_nf;FHgJe?tT0MIMX(!DVeM5vI zG$^2{e#83M?&=pHv~{M305f9?jWvBrm2vV{+OzYTo09{}ueX?nXKs{`W9D+)J(*nuq3V?~RkeBVcj^tk%b}RlGZ18d!>bw#g zsgh=fc`8tQCV$5P>vk?*|&YO?8nhY9o!$G}?OJb4%8G6Cx=JH;TH zV@n6*+Bnew85-Q5m0{Wda2a|F_stjkzo&rwvHWrSPmSlNwe+o`G1Ztak^%kCpV^s1 znl0(ndx5m&l$DA76_G<3(rCPW_rkfbu&AM3ycbA(TmIsav-v;9Zh|+j~u6 z{nhXap;yV^qU7h97JV8nWQ&Bh$(E6a|tuKimhXka?mW?>InnfoEyi`mLlc36vyA>Y5Erf+dfB+uBk1Mt7# zl@U=+LKseniK64iiCeeSBxSdEhlb!@|7lK$o}R81v8I|DjUfwm;{ zYq+g<*39)nL87ndy4>OEf}UPUL*nlcCG1sap~|d$>KkJA`*a3bNnHz=G!JQ3;MA7f zCQ44I4PjMq&7_$&?#c0;-E~VP zOC@Gp|1?MSId0fqlgEctd zMxWT|K@wy!aO<|#%W*fF4}$dSP^tXViE6B(fWKyV5+i3`#Kuc?jxoZ0i;-#*83x*3 zg|Fjc%N~b?f2AjFUlXe2owYzjFkA@mG{@l9%m4#*t~1Ryt&f>5S)S$x>0fvMYwHl| zaxU&LBf=w25sblqz7&4C;cXLRYLdiN9Omo{CaJ#mvId2qP&E?cB5a+a{uccnlM8tB z29rsG?(q4wKkm6#YME;VWqO%A5Sl17!}~O<5{6MDy?<35%FIc(bR^%G1N8^G0Q;B< zR{oxM&>vcdc1^>i)8|{*+$abb?x6AS+G2aQ16f#f8Qn6T`Sayx z)erY|EI&48Ur0&Sg*vQTrpf>JgHBhBu_{BpU5QJUxcy`70-JlI{{y+yl(8T8B71Y5 zgH*#qLmHm_AQxkM@I*&Ujq7DnZqMf7Ig>mdLy|mSd=GQh_8ABer&EYz_pXr`617F? zG&HvHG@8RIj&H?#ZqV=5SD4nsE{ASrv&84AljXu1I)~02m$6y5Ib;QJp5Fq$Aot+9 z0aLG+=?W}$zH()=SyCVu^O-z-dxRhc4KaP+eM&W>xti;C-2=32X&d28B!OVyah ztv0WoK#q|vQHDrSH>s2VsB4I*`s*JWy#4wdFjj}woRJBm-ZeDu8i5+BTMGblL0QbA z_Zh#n9FZ9K<-Yg}%AaLIsNW8Lv%m;UBFKEWz{D;6xwvc|_dsI*WAC?;79zhz<;_#p z*{|nfZhi~HX1E5^l|Bn>(TYXpQB;w%h}c$*5K)3FVxiG{PLyawH3nike^HcuWnyeN z0n>%E_e-)jIUT~>cgtS z`k0&?dSYx8AJn@Cp(_d^Ltsx#B^2dS7q-7 zjbicaKV3mxh}QL&oE!oN&|)}Z_r#RDN#C}TGKi7mP5gN^Xs}BAqr7|WuY(+tFOVpi^{b!ruBOssrC6|47AwOR$5AGNz~8-8&6?V$>RaK_lU?mjwP5~ zy5X*QsomsU@MXlnKZ`7V=&0#M5u3|Brrr8?Ney%IONRlpE%AIk~Jd>seyHe5S zs`RvS1Eh2;x```h0WY_6)nvc; zZm`9e1#o4MK^=8eFWS7aAjPDfsqILQba&I#curj-)`y%Cw0nV1HdSl0a+xj~hbS*l z&9j@RcPT2hV5vFGQ8ubI&|F=WjR4}7JFKKU5w>Rj_lQ{ zCixDTx!-|W*5!~N-olrEZu{{jD!eapc$T&Th9L21WrL>k#dyq%=#JL`yHhB``GBij zu~)BNLCxwJ`GP-Hx#|}{Vs_n^Ni7+=SmHCeoMs~3UYs}1yzoW0aB!;Mz{eOM?n z^3rWBC#m}Tng2Jck{gK=pFdjkbp}aG4{XODmJ&PZ@GP%$#8g%&I45_^BqrJMtTq#w*(15^} z*Kgb?G*nQ34Vvo9%L5e(XHBZl&IXMc( zI<@?nk#QF%WzzHfSqDyRS8Z0&zdiXLxLbwLP&aH-axlgT-rb$0N8}9Fg*68f;@B+R zdbwMCEoR~E)9HO~U9e9|Lh_P~l^{TH9@vlkeXC45uD{ZOA}dD+_KfsT@4H6vyMp|Z zj?2Uoov2n}?#1Hh93Kx0R#dT`kxGI{i<8OabivS!VP(_te)+4>38sOP7}V(b#<*d> ziT9-pDI|Zp1`yx)`mLNBY&97AZL3nAG)=l)H=h%JlP&jcCOqJOaWtsfmtI$T+S_+s z@);{Mlz`!d%RNBbWH!(r&tL61HUk($eh#clNDzCfaGua*<}>~&Pm{=#tNu(Jr@osb zD8Pw|SorAjEHWe=N0n&KK9=sZS@Yb>P-X1+R}d}f5#l%FC%W4w{?cEnz1_5=YAJWm zH)Les#5rU?=?t3X;asGdBqEWLe74b_+)pvVn8WiSX)XA!z;R|&g06K_R-H0=RWk8TOc*4H~i&&A9JbyZH~-`bH?s&TQu)T z)@Z<;74AM%cF&9tHy(Vg&@oNNSm3!N-L!L2`M&3RV zupBmQoLb(|tjsR7jo`2R$M-?~wzY;Mu~Dyw3xbfH?!FS;e`NM6jhOd*VA0i|)x!6O zQE#MJ9^bBk_y6V1tE+d~08oH1zGb@?YTGGhgY-XOc`;y`B{!k!ZKM{BqT;#<&?&Yq;~bI?q$W1 z>td@PCMz7|OSQ9QI-1F88w@PTK%xH@0?P+q>C3mu1QHUZ5eUrNj9wcv@{!+NaY#MB zLDFx#ohRz)raNZyCt8!-#B6o79;KJrqr%Eh0+n`Oy2y68BW#~7Cs!&GdD=(Of@YTy z-&<`0X}t_!gJzFCTvE6n#h)JGU042VEjVD1n}2Xo938lDh$c+H~CPdAeOf1&&N9V~4B zghbm(*NI3|yzfrLlr*L-TE-W_x;@^pk+f$he>5%^uFajTg zTP3D#wuv@Oxs7tEK%Vs-{il>Xq+r27f8~ikbxoqhMJLNPn`=b)8L~`eYs)c&5+#+@ z<-)2YRQPuv_IIiFcSihZ>qTo}MrQ;MD$0Fw``P@DCGRn#Tn`Z-M;kAV(7Jvq(ri*| zOT)4V4%rOijW1n`1r1E}Wz-2(60k`cS?yT4C2PCAg`$;tx7VL!$3<4!qsr0OUec!N zw{tZ=(^EViYhV>^j9hVlcMKL5gjb5m!CR)r;8inzFDXb!Qg-S^vqCnBM13Q-r?uPq zY5M1ZBK5Sb#@6E-~n#O;n~z8)itX#Ma$U}IAd8sMR-?(JqxJxH{UEqf8pvp zt`fe@zC)Dl=g;mfDVGIu1@az34Fv@+Kdv(eOWt_J#Nz#^8}lW+5Sd-4XPlP^SUOnq zX3yNEUn=~p!`lUHNvc=cxYt|$^u1JXKWEK!`{l8;$A0(s~wfr0rCsLg>{0Guzs8=?KjO=1xCG_Va@UK9Jno@*yAIe);9_$?t0JpAykZ z;7J!-@7DBqNJ6?s)-FBC-pq=Kmy-|!IhS6yvgnptF@afn{n4bg=+tDdy*cbQ`jIMD zAm}in44mTqav0}@pdiMrbSj1OK}Lo-eb?H{94#>J+cE}%j;swv4VFN_QRACPh!YYm zakJO``wW?$uiH`01GyTS|L8R??cKZmXpGXX_xz4fV_of+QNCHWR~r&rVP03esh7m! zr%dE{5770SzT2CWm%r-%;cl*Y`R!pH{hskd!D__bcJ*N!=D&XMrQsoMrJ6>6c?kip z`s4cg4iUBn@P^UK_j3K2)4*j`2+_`FZJrzh<8$pxu^DCR+a8(r@F% zZ;#~45NbPwS_mm;d(xuiwfv*K5^q1&39s#@6k&)t!*DF0)8*kf>ITez>!Zg7!jtJ& z6Ty>LMT|J!R1+QF$xvU^N|cf#fS2j?Xz;8~C?f8omx>s&FCd!5`s9r_=lCMc{Fe8B z=UfdKqZXH>Xgv!D`w4`Fr#*GpgwEXDyJk!pA{$KK_i}~j#LSK4tW^8G*UvVa=y(YK8ji<5@d7W!wEATMQ?2bO|l4! z441@*`tg4Rn|C9REHXV-+MUws^KUk(>1G~s&(d5GsQfd}PIQjh;)rUf+%}FRpCBW7 z*?jhEysn&u;NL*T3=;|6t8A7DI9ANracT4NUy5f zwkspe78VY0BpGSR6{vyIQcG7oL7$9`pjt{vb#RxbWUygl^tk)Jz zMnv~f@nk9mkwtt<&t_f}w7;_SjJ@ubxih8pnChn=sgfe8DPeygJw|VfJ1_2{U=iI8 zYa;%NOBqBHND65jGI9ub=x9w(Ppm11Bs4S1D1?=?4xZToj08W{s6;ox!fXP?TUaHA z8zhE3r;YWBnl~RyO_v>_kDn}g0JNuj&6hRMf_mu+RbWOGGIZe=+WUTc^t>S`3+mmX zx}koP?uN8~(teOC0fTv4#MH4&dGti_wBRu2BdBp#Ll{cs;hjQ-xn)VB| zVb{je?C%5)VH~5jE4Y-W*6Lit-zi`xx#oWVj%8To!T_Je5h7}Kqjo5j&rUmEgHDCE zpjPu)39g;p4W6RxJIZ|9v!3fQ8Xr2*we+>O{00<9631M|yFvmf*gn))x-C({zL2OP z#_?ezj${W_Qd|7Ws!^n;F4>IQvrWIhaf^(AQzMjK_Tr2^20-#5^fb$Y{iv6SN{Ntb z_$V=x473c=el}-VI2526vkv2Cd8)0Qu6WsaUZk5~JRg9wF@UoY*jzDn&|5!7i=+Pt zqvs>;qfN>|46?yFmy?lvKCo5OojHYAG8A`td#iGG5T&9%(8Yu$kAvMYWz zDB=*18QzD(5>{YAAz7?fYhqx7>NIdrlywYx`whQlEcIH{jR4@$8;=SFX=C;T?>hLh z1b$4K(e7~zBf#Pn2|5ni!jZq?tU5YTXgN$Oh|n7<`&z{Hv)}r(BzAb;gO|#Ec4qSW zgmX>pLW*Hy2|lyQ{k!uHJW+p@KKj$AnE5w2cGD(-z5%sW{G@@`Y&+M>K*vM^4JtuI z9$2R#u>?t+zU#Hcs~>k+o(XFxz|Ja!g)>P93R*d!X|Du3tvxY z=RNEFyliZv#+2nbP+0$x`Pn*rcDmL*bVtjtt;AO0SUxoE_3aD_XMXQaoYA_NW}%I@ zWM5U~9M3I>RnUdT%~$d3BrOzU+Fz~d&Vq+`rN-{(bpEvpK` zXLY`R@gCJ}<&hxsI;~=+k0#`8ubKSyDLuiht+jb$b%YwbU&|suVEM`G9V)|98l1PF z&(ypTIE@s22W2olUGAvTM--LH`J<$&tCn88jcYE?Y^SLD4y5<&)P6eu5&w`DvcSAD zcU-<{?PK343ux3meTybLAY{dglr$c(QSWi^;A^?F3W^)s<9NKqAO0nvw>;^BRJ*t; zT45&HVdG4zh-Mwt!-uqdVofV$GSwBZ8hDnI`J>oO*P}7m!-Ej~+rf z%avqRF4(_qa|igw=!laY3RzqTa3g%m(%g}~5)EHF_uX2F&_cLL?Ijuo~IDs#8XO>&)nsl537EqGCOshRj2kC-7eMI&^USB z$1i)E`J!aK#A$Dn%%nmO+_El6o1(5~KxIT3O z>qF^Z`;I1+qEce3pOD!dk!H8$-_Y8KsMwy^7Kp!S&#M~Wh=#=cN=sIIx(_mA#5Lpx z+26O26sD#b=%3LQO+`QLLf^$2c~y^!!wcSW_DqE-O&|Vn)t{|gUUY0j1TAwc;7Yd| z*EXmB@suDCBX4%x4x=*(JK2c~n<$^wq}s=u!)f-&bp0k8@FDjU4R(CGOF_c~CRp79fy&3oI5p4mAzsd&vH3VN@x`G_)vnBqP=Q470YO{@n2(Igy?_7+1r zvwEZh4Zs}kJU8M|hxN+wgxuRMMRRs%LYp5QP2oDnyJvU4pE>^pC^e3b)ONp>=7Nt3 z=}cFq~zgiE}Z`)XeBt+u~kPWBW6hA?bM45@mcMBwaM2waj0U{ugq7qQoj{ zQA6D@p%5lJ?d2$jZ&R|F7arLT9OrYd{FT>3Gq!3NSm^g6_*18jmp*R! z|2+Uq#PXR0^1=ZUekw*$8L;E&$KR*tQ8Xtvf%|0=Hkc zmgR)k2ch8~Bb%(HI|zfO-BR?&ju$%wRB_U8;uLo{VDUN^S6*$?fJ8v&v5Jj>`+fNA z=o;*_IK0wRf&7pEoJ}(s1Uulvg#nL1pI>E33kqfTGo^#?M5%UD*@yX>(7jM8`Sr6~ zP%fbFSakn8x_fzwiT*F`x9rIQGt*m%j?o$>UC1Bn{iPRjD=bc@l@~L`>D!v5CFp7b zLC>6Wfq3*#o6`QPcM1W3O|c2>6QK=q@f2vCB5@>fRky_BO6-CfsL7RX+gsR~MsEpq zQXa!7DnZrP;-&bUqOY`ai;o{Uw*o3t^eg*UA^ZKSFeMeWOdv#_0 zWSU}u!;{(B05mUasv9PSPP|gU<((FW|B{`1)%7$TxG6X=Ymqsp;?k`moa^=G)RwP$h1-MI`KkLBE}%LdjC)2+Gxo?HLt zV$-5>wmD#9NT0d zexp?FXUgD`meGcLr%*~>iLCwgJirf5SZ@dyZE@G;fdUDv2@L$Ht&<6|jt#ifFZ$y@ z{Fa1O(DAJiKP&^TN@a9nvGXg!P zfwkpe79gwrx(2^z7jTUQ6vtFXZ+U0umhe$8LT!Al#87z9(ZyRhp9yL=|BDk64gQ_w z-4+1zPHU=tlgmK=Mwo1)Z6<9?zIrYsKO_~(fM?G*pUyDmSarOf@u6vQv z)0bT6E_4>EvyOR(RikrWw0|=Es`(M))6HIw8j1T3L_ugvz!-aCF>a&x)A_CH~bJ!iIR*iEN@x)yvwmg*(h9TbOIDL zs`?&41lC0ODQZiVu{4It!Mtc@xMsqO8W}4qb7bX$_q*iO5dx}8{b1@j|Lzl*?2PkJlb%)5knPH$8jEtnl;0cikv3CJ0}3CX1V%5$2L!`KcGArLFQqo<#-R}JkL zAeX1&Yb!q);q_Pf@7LPWOSDTKgd}SIqS6u5b>xjd$J1YagjLsXPaaid?EfHzJL+53 zc6D_zc#T^nG+6ia*R@$#4Si90G4t(E9b7k*R3VblD*7`eLW!& z@@r5>(&lBF_z?6M=>8Amw@WBa_6G|~j7==|Z+o3AiPS^4?Pr_HUV*arR;`|(kU@f5lHdd zE$illPFJu;bv{Vnu59K7J965~5U>Sq-A?3^(I{Bc2$~J2ZFWKIt>S$1*-ek8U`K$I zD$Ut?ov5#!$n)4sQY)rzvqt@%dygZO82DBwgLjO?`-UDxP@IbTq}CdBdsc98@P5j8 z#?!Qr*x_-IvGiVpnVb5rYl$jDBv}+czM6%@{OSBv0uEQw&Xu+ug1%(fc-r#2-?FS< z)(8XXHCU^$&V%aBmKp^4I7$|4z1pWQIJqjW4m;`~cV<=C)YLCs!F@d5i)CtN3R6GW4kBPA|&d*XH_wb6fS z$HwF!6S(il6Ru(nf~tm*l$O~&7aQD)%f;j-&YdN($n9^!ealbMs{@xg+ION@#AZQ! zl$^coJ#+d&E38XbCR>oOru7M@(O?&@PBY!H)7IBH+_*H~TAl^HIjCQC2?(By@w?p7MkFCjLF(#kgc4n1 z6`Bffz0NNMH>2r)B8tE`Q;g&oOd2bK4L~j6znz6pgK0;hbCG@tvxu!kZoeb<_}dj~ z59XAbyJtG%Y9jOV?vqsFGPwNrTdmJkO?otvT;-cve?_y2>ZpMdt3BS2kJa<3_NA{M zcjbGF#G~W&+Q?`CO^X%LC8D^fy#)HjXx+xqY!<%%(kft5m)c29l-+AN4BQ3yG~k%8 zx18*D1a`#NzK9n^#fYCDCce-}6SN#!tr*eu9js=B>vP5<#(6sp>Uk(CYnzJ++AWm% z4?6GKK-iIhGMZA?f6t8rFMG-H7cl^p>1pAR9_}~T4g~?ZZN`6`S3NTX!utp-)F8uW zxI(kPM8Pn+RJ=6)%QFqH_+G2|B!QB&1H%;|;3N#>fN`y1oiCrOu*Rl;>0!OL1{gqV z_YQ^WUqehp!Ng1TdjOiz*nXR&oc!>;!b?5w*|S?>q|H-6L^QFWqV~6MLjZ;PY?BkO zxv*ZCs%CP|<}K?}#w^eGRPr_I2?YyiM!NvR`}6TBGqNRTUx0qvm@ly|pSQxOA@Wzp zeRn&i-Z@}*-}fF4N%}40g|)OkJ(7AYEn=2;rnUIrRLP`dI}V#CbJdp1aZoV|dbao5 zvFbzOe5;>z=Ge32`woYNzH>EYN8*q!GQFM|qH6g_A!OS2GDcJq#+v@###e6jqu~?Z(S{~AgxCc^&hrv0xI((Eoz^ez{m_10w9bF0mw)tbaE}L)STj}BV%@jo zNn6GZ4Cn;@bJ}=!0{^SWvZr7KWVunVjV{9G^p$s;q=;Tf`nv@+x(Ap&$E~$NuLFxS zY^1kpSHuY+)NTfaaA?pD9ghM^PceclL585k`I>#BNxxChqK9V+)v;)WAv596!L!vT zk=*JP>}8IfU#&olf1|KIX%*g%Z{R9{JGJvO=tZcN7)kd*lN~oSD(V7oSyHdDyvr+n zz*FlWf7AM3E`YZb+aref#dG|s*)oG;j*kStzGa4*15m7aBNxY}t=!)hd+1u-=5-1k z*M}}e6ioox{&?aQslo>|4-C7Zs4M{kouK=h;5FWrL@Sp{?QNsJIuj*Bzb%brHVxIw z%@X1hYV=lb|EYt```E~FuRo%5bW6kdl_eB5=Dsx&ya!tHfy2K3H>Tc|+jpuoLhrkw z908C^4l~GVxigo&I#ioOj#Splt3})L*eCGGJJObl!kfHG);)awE0st`%bVLZ@ucrv z!$fF^2p62TD>6Pk$yTRBsYimDx zAlg4&O+sZ3^kKJXfRc6lio_C}mV{)A%ygZOtxbqnA1ntnyR~FNsBv!+&dD9*vs9{r zfzoMuiU1psT-`K8=fx-|aiV*$y++ z%h*%9J%S>k%)k=qJ$Od`D-z@jgphtucrWK{i&=f@S*Uv5M;9)wE1yqK$#_Fu>2az2O_Gn0M$&_dA2&{ZU~bn^fKD5l{~p9rSLT zFuOR3b$f&h9`Blm3+nTYj5Bn8HI5FOI8neA745+-Yc}$7$}3)~Jqnwp2Bv&Z|J+6L z{u1))rq&hBohpf=k48eGBt7au z0*}MHv^vyI0auILg#~Ay$ZC_cU+Kd&`L?Y{sqKdN- z#^n=5xiaZ@Zv}-5c^qyuvD>e6`{K6Jieg#|HCo&-=Ab>{`yn!e7qRn}2DE-;~Ggl6y zMNuK@8`5{{e8_`DammHVyS-m;CbKMNe;&Shaqn5jdQz0<@`n$I!xV6eGJv4+9D~Kv z(b@zyjCW?D6~+RGhJ6b1=f}{Vo7;gI8N+KK7+0Uw=igzJ@x6gFebG|z4BCRdQSF_^ z)w?WaWy_rAuCX^-WSAx1*AiZI{LEPQu#P6JzegIk{r&UN`Z?Q83H}?RT=q3foeU>$ zVv1oAMYXUFQ>N@a47!vg#kufnAiPR&4O?*8ZGlxZ52v_mIZ>f`TzFYcjkb9?C}RQA zgK=8HDJMf_Z=j|TAPIfy;UGLCiTPKw-o%z5a;;01R&QdhoxP-dvd!}3=8N^wqVk@N ziS%XbV4OF?E8Y|!8M#V=5ak$D*+f28MP}weRpA`u$YqY=`ccJEidw`PqX2Ro^FXhf zp9(V230sP*PIP zI9msZtQVFi3PYF-s~%fnX^yPXGyV>D_RTs?vPrKk1tD8*Qsk;5C)izA+&w+huPSqS z(8j3P*ev6L)F?}_^1$`!Lsh_1U_hTq?c=7Q@wMo>dv>JpMs9A&F z$W>BqBbRz|Bl~kz8Tb1BQfh|mlTDD{5Fh{|40=oV=oeMIsz3w@d?<1?b{rX8O1?*d zGiZaI*QB(cwdR38qe@+#GRq^~6J1s2b?A1M-hH7whFFpjJX(fs8WHs!^kH0p-tv9= zMa7G|4vC_+dus2ylY%Hwoo>d^jhxw#5} z)A9EYo`6jW$Wo&a;rvOy1ag_nXwks+sm%3%xBqqsjf(ZrUOyA0UfON#ULO14WQ66L zC$a8Kw^@@%d7Rg>c)c??tSO+TovaJ&Lnewv1zuG*p`5y8C?=j1%SuN?aZ$PqGfwBl zf(OGcg!$gQl2-)Yz>^p#+?A+IJrAUBAZS3o60Ks`t4BLal=VNt`~s^K-W&r>njG$~ zN|Bg^f3VV^Hfs?aD*WtZU?HxL`>>6=_^k1IOQ-AC)9WIh4{DbzO1GSaFE9`AC8?0* z>vJ?MC`ZY;8M^tl+mJjH|jaD;j>oFnjn-0;|qJYE1E%4(J3OgNwO+oV!==FPt|NpiWKf-;i z6ju6{t+fdxt^f6tfpCaCkLQljvHX9(6+>R9Pj&6f-O2iR=O$i^di{ey!W7v< z5ng_7MA?0i8r8;9x1nkc)O~Lgzb}+8A)aYI zf;!XLQrbyqN`-_D#*sw_fr1HsIaIA(0A&35|yl@gic$czV+q`Aa>Oz9zrT zT0-g0k%rJ5jSpPX5kv5PE(QZyy*27x3O@L?ey z_1JHf#)JtY*|BV}oYN%2k#fn>-Sp76foj-85aD7I5G7;?*S-xPGn;O!|I&$|3p^O- z01&V(77r5*qeJ&6d$}Lqrux>8$QeqlP2ShN&2VTCLH5s&#=igbO6T5`PUpKXbOMO6 z*&w=_D7|m+S+PMeU~;lVGpfCF(vJ$a=5M4y5>y4o>PfI~;QxYxbLAHm5i_a0i}MmX$Df{DLPX0oq^n zq{F#~$HbA5+3$u$M_u5V&IE^>xqokSzzo_KhoF~AhNm11!a^R|j^BlG4+b#=ao|C8 zA&d^`i%7NfYm<~n)@vQCX!78bM@?Z#+!lgwnd>(#fULIg9Jr$xWud5jcAvZmela;- zd8D<-%(LaxzV+8dtNf|nhi&8=Cm|xmO(mMbcN_knX* zp|LDLv6t4RyC!-XUhQjX`M>t@K5njTP8~DI5FRA&tsGr5UiULjRXF%sj1Pi9Y$P<) zH{E@39U?l9sN{%C#sDl;W6r7?`$gO=3K6CqG~cr*Y07(_^R0Wc|84`ZW z-~8cmN3J|^yL9924L}in%_@X3`TS8I4Z_6P(j2-nZDT_xiVP>l`ck+0EA>wO_KN(U z=k472M<7AKqo)vL&#oGfIs6)s02C!xiKSsRyR-Ol^rBEpZ(zat8*AH+gYJH>X$wETS2%A7fIpr84>~(jZ z!muI8`^M)Ku;B9YpF^c)fV2=0bq^XwAhyh`vsnE@??xvTflBH26fv+i^9w*i#PaQD zk;%4Z!gj4;BVnQtJn*P)j zZW*ji$uMP=oo8OmJI{D4;;8*b?X=mf)-Wx*LQhz3(DcN_fkHQZHwnFU1Cg>=50dcX5k*z}=Rk5O}H z^UP4b9r%+LNEy5~c~l_x_iW@zJ69ZV*$fnwbe`l;?Aaee7NI+OeiOv<)jl5J{6Ny} zzZGgh6M3+I^7uzQ{#Fz|{&uYyAc`jLd9w~EMtuc+W0Xg zJHs`D2q2tztOx!>V$e)X>$Lv0E(z+)2Jg?5oli^!Y%f+h$GIPGq{0 z{uUz!+fDf%=#=yCV3174<}&pm5Gf)u23@=Y&Ho64Vkp9zz5lJ@;I~)t1J@0Y06sk&l#Xv*-SmVCMex*y? z)+0wshn_L!K;iDsRgH`D7pkyTWK#z5zl z=Y9nKl@%lVoJ-zFV~mm$HZia3wh`e<4|mFhAc;|8+8NthT)hYWr!-`)5sy}W-Uuwu z)!j*HOYuXK=W_8d{r^sG<@LYil3vZr3osUo_eq7#bmD37M?bEjax{1&DzUK1EOhAB zH)it_CC%{D+C*er%#qG)3r@uK`R4k-_NkhvkMZetq1$1z!4L(nOgvtZCpIaMEkKBn z&FqN&+TW_rV1;&Et-u84%VKh;ggLbx*ly8C`p0Z3zS$EZV{$-!1FtFo*-+`-Fw(?T z_>@-BsWYsdoo!PmV+l);)XbMO@tW8M9N#+ix{OJA{ja4&VaYU}I3#C=1y}q7=cp_H z<5#ajZTv{!P9UVI6LtWr$gpm!CH?g`q;DQJV2DWx(A6Hu}o}Cp&41$!@k%vIr}dI$E8tM>xU{>*z^sV=A=n+R3Qf@(#JUxQcJo zeR_v2qx&q6`J*C}*6)gNX41}{isvMEpB+zTtiSSR=iDp3MXy4V%)~o;iqpk)n>QxO z(t1<)n<*j=?@!Op)V@vn;}W)vb^lFltWUD|_%AJwxsT!$5s|wSPzUaIsR=?}yMk;; zbc2A#2jM?yf}6&K^1FIM{zgw7@BVhbN*xc^?Yj&c1 zg{6D#X%#7Cfofu&W|EnoHE-7VG|LaYwU=0(RH$?~AUw3sR@brMrc$#WwxWw0U}x>c zpKI^)~38wVq;YN!cyxNNmKrgW!@y4 z&?QOnxWnCX^XCV-tl5)55IHXb7eDz8ZwTcKu%J>SC z;ty6w%(d4S*93>$yc&KOg}e+&uYYc!mX`Pop-|$%1V!0JrErbk+wXVA`Few`4)eNC zt+GZp1;dLJ56cC2$4l(F+g&oO%5og?)Q)% ztgZK0f)XW6>qatt>q9c9?czzpE!le+|pgt81zhuzYjL^q)Q z70D9Uk=qqb1v5K1wzn@Qbv`(LqC$~sA(YT*4{p#4@ryi_B`S)tvtmcujM}H0gCCkD z%`6U*z$(g~8)6Q<`yiZ79VmtanL7=Zo}y=$h!Z ztK>tO2v2is*#PVGn1J3F7V(tzQ$~vm?E8Mb0%tGUmkWkZuga2Po>~#!G31ezJuA;p zX*$9`XmPGPxVTwo-pdr=U$o4YnAzw5V0A3DKvR8M_#?XI$$~A}=GlQ-=IjTS+=t1+ zqdnUNQ67D2usa2*JN-hJJyUrQ0qQ<8E*Ml>f8Z+I^Bur(hh=BTxJ{J$WXU^-o8D&- z_jE>7nEWbsWOCFO-E4o`5wujEyU-;+J~DRsjBpucgu(=uNZv?gI-6^(iflHoiimlW zQ$xe(4hdvW5uMurF<{bVx}(k%j~0B}^@^EIi<*Qj$r@TTKmxtWb57K2j?lI^(UHF# zy$1shO}wiP(K7~-hrv*kQv#>QYMEY}DJbKNcerpXMH#)O5PhmnMZX36+jAYb8W$Mnu=SZ5~^v zZ&dCuHnga0eaP|iw*BCBwfl8@FT3>`EVC<==~f!=B>7?wZ$=m@@bZbuW$jLJ zyIHBLQ$9U{qt5zXX)HsTAz%{|>0+K6=IA@pT$ zj!d$!4x_BTf3RDhL+p>znSTpRUq@HT;G1of&Zq-?U=eKyNn>FlRXViWORkPBh@Z$H ztdq`7-X*G)GiNy`PZb)s<89(BWPxR3NJXol$SZ<%-aW zTrq@IoLhhi#*s}E;9vcyks(BVPa@O05u@%Ta?Aq}3C>t)lIBx-*!F&bM8j(eC^S}x&zsnpRBsF%u! zgSI#p#%@%md={qRU?J**4w?VZzKmTel2)316u6;IoP2KGgDY*;FwQQc2Di4iIh+*fr_Z||DCP@@Zv)Qkkd`tb*J ztCd#wm*~C?5O#3%6HZt1k7ps?>gnqgk5KtN_NwNL+U>KhyI*Gb`n@(7EQdE5eRFIYl;$l-=V0D7yGZo$F&7JR9pxR)uNeQNzZtijv!D zc(yhd;~dx?&RMO(bQ)r`MG$9}jc|%ty;6I|pT2#Mt(%p5!p6&zY)zrIN}-NB9=+#K zb?~FVHqi5D)(6ZO2Qt6QIpIr^U|#)bS#nCRaKr0^<6u+mdd(^ejq5b)vC2nklF%IA zN?@&ho_z_jjGU$vA?{bzyV(BTuimFo#<-VcdtJvfTQbJudp?MhhPS(j>1-)Gi2{0D zPs=CMNHX4`TdJ$%rBd7eP0(zz%Vsl^uU8i;t}_-HLt-R(wIVP(d)gz^NQo4c%l2gP ztJY_Pf5JvNqQfION!57nsIL;~Z-g1MPb*h2Z5QiwPl%4D4fR|px(^9MkE`|a*%nvh zXP<_B)Mt&`D2Ju4x+qFU%D5}BFVb0fkUcZpxM=o65KrB&-6hBvE|*iQO1obUPKg1v z`in)hxTkIhJA|nFAkc^|ijRonhIC&_&Zq8MZqM0QDxv~fGP)bH22}FFEfnH zV(yoxx|T~8K@226RyevQ_=LnyxOa#_NYoAsAYTep4A@r(-{17J1UL-ykidTrp&wj~ zCh#7sU~-RNSFMngqZg4K?5^G#T+H0*8Bxgab69>8(VsnRXF>=Sg9l~)cePOC)S(}OCSX0o}xil|WKmMdaAM6(+qK00)9!_2F} z3OZY~z+kd@o&mHSvu;5{Bf<#l@f_x2>8HM21rJ&7jD$Q8hcr2*(TaR{5RRVEo!T?w z^|NnWtR zzJ(Vv+rt`<&dx@XdaZtx8>4ct?O@oa$)ZvgvA2IJZ(QBwPb@OzTQsvWuqhi_zj`M| zgs~`6Zf{$hty-0Cf0J|QJkgFzacI-0*_hd={)a!cfbc);f>lmQy}xYDaP&T9Gz>kq zEWI3+{k^x*RG?r>ae|vWQ#W#Nk|C2f>U=F zrkSfU5!bt#?VvkWjU#uR^7;kR`os6bU-D z!)J-vQpn3q63aMXA<4bk&1B5Sw}8L1zo1Yu%`~LX*}$B>{k{KXJ_ndg86#*npY}Xo zx2*esRF~v{LI(ab=aY6q%qDv{>8?Zfv0?$iHRK>|lf*J^krB5ly?LZ1hHMW3Edf>= zn=_47*CubL$I4p73lOx4weUvWhCkThZ!Y&t6+RoP>4Bd%5kCJ!SLT9S10sj3-r>cx z%9&T@j+RoDCXUV-?WB5)jyu;N$FgrrhQ`oyDIEK+=bC@_IbY+uU4O3zm*ehXI+1ST z#6$Sa)(5BbWFz4=QyXe{GzvH-;ND{t8f`lzmI!xoY- zNhsY!_KEh=(U5$|Iei(u>58ZukeK{WM6FS8B4c^bi_!0VjF zc1Lh_(hq74dHPAIzn7U;Y|xQ^cMsFvz@_+&O4FabXZniLz^jwB9XWcfDDyHxQDndm zMDO;ZV(Ol1wD?mYA?Z8RX)Zr*W?EpWSWH$q)-A>x-fEP)FnWnG3Ni_nQPAa?U|9%j^!=SGPx$5~ALYy{hwE0`tvFT9ioEx7reo zUUO^Ub&vntJX8YY9Z4;lt znj3YsmU$1H86iE)L+P{KwUXsDY+h$>e_|mfwe9&HlHJ;H8xx01CzwAboT;uT`Js*z zFU?8-v#%30BbA0|XeRC|9cxP4JTbFo@*NIRlm<}GyS>EvLzm;sqn2MYq_h zj*5o!Yo4~3T)%wUNEpcMjBd305`dqUL){sNo*jRu`e^9!coYBl zjRjM~@K^czT{UvLE9ETi5%rR1nuQ150YzimwGpQHm;JIAH64Uua0*Q}HC6m%U#^PM zqKLPd%xVyoulkDeh(Ni~LoLqx!Gl^u z-`W18d@D7(!57CSBLy4DeW!VVm^U%=>NaazI9C`HEK*;#C0XxL(Fc`K872?274|rV z-7&Q?eU1e8j)iO|`w;v!=@)XQia{eCZ1sPd;z}nXmr0;otrF$6J>rnUrxN=ow-?jf zFQ;#)_UOTJOcE#0sv{0dz+-?$#!3gzxb`*PzXp%Pq;D$j zckD*>>$CEg^=wAD7aFN`dah04q?|POCt<~2TAQy)F#qnlUC$U*$_{T+&>YHD7&ME< zfHiN(?a119ittui-pnoWc)dvHK8IcQMcb-xMVEB>nPyf)RjaZo02{9j!LCn#${0WH zH=1eDTQSLS1fQ#s6mwd8dM+Vo?%K=5S`a^mfBWocRGftK)!NJFT!oxZOUV zN|YIb>1}@@GfN2$DrWLxd-Gh5S#Nl{?c`LY$>1@Sqs6`(qs}@3oa3_M$x-VQ zE6jK4FTd-zF^bEG>f-FjeIlP!fUktgj9}q_tis=|r>yh%Ypf_^ok?DP)i^Bug=p`d zQ|)ML`)OkT%OzI8k!OT65q0YjVFUt6L3catW^m~Esc*pXA}4EKLQLJjG8UkB|yAN z9KI%|hAPgv!l-Mtv-!ud^8OXRU!vX`3qs6c;Y%-dC9aBuYPxWwl064h9%uMIf(%Ig?Q26QT zqp0i*pr>Z{zqDse-+t`nH<+VR%h_Pnq5*vfhFkmh$_1*q9|oXnZR&iq4uA^5;M-Q& z?RS{cYzLzT6#c-NJ2Dbc!Sp|w9w{fkeU@;NDK11=EPRl9(ATkdq&kErIb;!VBQ00w z`p_9d-!3aDqDS$Zr_LxNI%(^rcszPJ$vrX~H*P4Z=s<}1nd9Y5@WmSIHy92w3<>+O zyT=PWc*BAf!(Un$uTfH6Lhkz@ zlk=rwNtfqpE2`A&7-M>;>nmrBxszyjQ_;Md?rkjkF~wA?l|j$%2VHN!Tx!90(*`A< zuDw%TBhD-zZqZgk^)ZN(_SF_gt+TvjOn4w`EW#WA2k+I@tI1gZM#;gr3+nbIRw);- zn>H}Gs9o1B6Y>FpgmnAXb89a}8!$yjKGrzN*#G+lSPh$$0;{|jxz;`1U_Eq&Uhz2Y zVeNy2Bs;$JZRC2wZCip%yBaJ&G9bz*KKCVi$`IX|4NxK(Or8$G{_?ZpCXbgNs7A&0 zRZZlR@Usg7M>(-4jwZv%h&N#s*QJ;9C=mL>0WTO6Sk?zO@7TyQq8z{U+Sr^>cy!|O z1;so5_^YQBfvG0!+N)B~k-uG1kpVy)IARG!WH9)cX^HgYv^=26lRvLrfoXawt_^3& zCMb7x?zPZ}?sZ`Rv9kRq*UPsj|CrO+>X|8-v`S7+?1urIg`bvZaviYU@l*m$)euFW z_sa6McCbTa03yI+JIz2Gtn81%LH(E3O2q3KV)xVPTlc3cmAC{} z&l6W&PC;EDhw6Z%T)=yCZW9tBb|*Di{)*~YDpvOvxA=xa=!*g#r zH;J(nFK3U5f6!(&dR3aI$h5kXkT4Bb%KP#^Un&m>8fJ~Fm)$0WTwZhC0{_zc_b+}h zD(}{n71h)eBxpql155u6kE7+=(+L%u#0nsNSHFSd+@t>204fwLHk*ynnE&G+vN!Od zm7cW*)+Z3c}gd;9phCS{twkS4Z^~CF@IPUa;zlH}7v6-&<|B zKI-}lQeILfVX)iEzIiAK^`UHc&-PS9p?UU{@}UJ8RY0-u({S~*(}a|~vAxBwi_1Dr z@p7EC4=$VX0cbbV!b5qS;(l%#i0%g1IlX-E221)MZ4FNn%B=pqk;DS^yHKv)OAgr2 zQ;dS4NC#M=b=r82miu2Cs4&W^WhFb09vacDoyCbd3$wLQo|b>PY-;R++i|h-IsK|M ztYSYHKIDXsW#tW^Y@mL;e(CBfQY|BmSrB{C5|S?El7K?!@IXACW!@>Egj&RD*fOBq zbm)7%G>`0)P-pyW-+KSAvMUX0D$BwdKv9`ip+uUXNH^dDG>oDsksTrgBBWUYA`+zq zLKJ92*bQLQXbVCl>|LzqH7tE8Jwaot3bHZd+>Y*N~5i0k9wPzBI%!2DMfXAQKxc z%G~~jMzC!Sex?zqC_x}~g>4$&_`ywG(td5fXVZ95!aH7aSO;le?$hDnNc{~jxYHT@ zEa~LsTd#Ni`5s(F-C00@Uh`;)0*GiWbG6&w0tDOvq z!Mz7D-@=@l-bObEvK`L*`rY;D{Y9Lkg`~?@pQ7W z0j`*2168&W4lu(}9$Q<^Y20gPCc|G-D~DU%^gF$mD;Fg8RK{|d>pqQd3ln3NO*IIr zsWhf4`n7EZo?&@If{RMZcikfHLXOG{_8#%MeQO?Bl4q>xYSKj=0m~NH8zN$Jy37Qz z?}A4|d*CWiwb`9mKBoRKGD?phcHMB!-EgMh9EkNvJDr-ts{OWz!*stXu^aE^yD;)F z>m>7oS_OMr(3~}oPHRvuhuA=`1hgfxYkLY`j})meR0LF@q~k&H!kK8IDF0p`l4$cW zof_ydy&4hoUwb7_^aH9&zcPM(`9-cYBF${>cK1)}r0E4PIAmUXWh>MRtxT=GDb!7T zliNXg@gGH=zgjgaAcovS2Bv=Gg-4$KCoz0iqNPU3ZH8}Ya|aorKut0Xk{?)quy1i0ND1$ z{8M7oYd|JwBGe<5oI+eMTLp2qSJc??Vt~Y)>N(z|OW~AJ|LojY8!_)u1Y7ftsNld7 zs^zdq&m$Bw$6-sC0HVYET+(%wt*xXWaweF5G5y zLJ6oswIDIwEZU}PAn&Y*hw&Nm_pP{LpI*rF|A^f;5{b*d_N+od)J2SzTgI1ypyFEy z)1(Xh?DkWW@_?Wo0FFcn8Bi*QYPxJDPM#@ZEuzN*EqtXWc7q}eN>ja?qv{=8QOID} zPu2URn3@6%Fc)+(6kL?G({qy27D@d%0avz{B7ibWMr0iD!KmrVnTw6u8H1uM@uG;? zgI<%rQ>28;2A4Vv?9?Y314I!Z=jcu!p6Hz+LvBVhvD}SX4@}-z>78wT43NaZ5QUPJ zesr5Y#|tELtM;}8%vuSFK*Qzl`{CQqE?gzh{ktyk91#wDKmWu;p&ek7`#0b$23KFB zZ+Z-9YixSRPeC1oZ;Kd5-f@J($CQ~+$(R&erx~9+N%2IeT-mS%ww9+0Q|b@G0^c=N zUm^yoE!j!8%VaA=ii7)p8=aZuhl_Z`3{a+GFQjlB^gV^g=+uWirJxqC!oH{jx`1#E zw!90gHb;A4#nTL3Vq~$x{7J;+oWM1wkkENoa--(OZaxYPi?DpWsddvmzY4T=|CmU+ z)_Ah0k$e1OEO%o1dzdxV9zpiAHQcP%f07YZ+_|;?v<~w**audId(dw2P{O=Acfpa> zI^mQ3C5Jn4xW8&tFouyTl7T|O$z|^9F&g)Er7upB@#}g`j6`3n;)wp;u0#Xk9d336CFo~^p%)8lI{+<+H^7S_Ra&@VO{rdM`W?OV9~=&`dgdz z8$ATeai!m{%jW`n0q#RPq_X#bd=>k5y`MkI9^DM@sG1@d%jNl#o2bCKDzlA+(tojF z>_0?Yc9f#owE$24E&WaK?{@cWCalTGY@YSkVvL$!XnQSiU|+yKC=?3;VR!oe*u^a! zcyI|)4?n7qm4vd7_AR#7DRWH%ssa|iG8Uj;=9{>GEjW#{7e{3prI`>gdPV;32 z5MjMO{DooIr{~g^oe=2DI3>?>z_Ij#j9^`m@IhkI&BWT$|M86}i5QtG`q~@WO{P(d zyl6dMB;};9=VfdU9XHrK9h zI@(Z3a;g4$sWgb)s8yc+SPvZKUB$_0%QzG*&3+x%(%@Rs@(Khb1Zqat?paN>S-AvH z$2@bnTq2dyJHMTeV4YUN3ACJBzPQ?6?uQMQWrcHB+heY0T_06-`Dva2OvxdCAlOaH zL<+uGaVR2X%WDU^D*S_ENbjL?ps3Vke0J8?K|FtEa>vm}4`?B~Hi@k};AaesANLup zgfFM5YFitwxI{GP^p%qr*?1B=$g}RVIBSML+@(MVFoW9~x1xI$&-1gNx{D+w5SS3f zQdhshn{%j|Ie)m3I7#@QNO=wh&eNF*dadUOGWp4bw8-zlvHHgA{mZyXpp4AF%QTGH kNeG?ap4$KNVWz)<*+Efz&@lTZT67BnZf`}kxcbY#0Kv^U6#xJL diff --git a/DOCS/html/mcu__wrapper__conf_8h_ad3c4ea41584d0367dfbfb697f5e57456_cgraph.md5 b/DOCS/html/mcu__wrapper__conf_8h_ad3c4ea41584d0367dfbfb697f5e57456_cgraph.md5 deleted file mode 100644 index 240f8c6..0000000 --- a/DOCS/html/mcu__wrapper__conf_8h_ad3c4ea41584d0367dfbfb697f5e57456_cgraph.md5 +++ /dev/null @@ -1 +0,0 @@ -d09b1880f61e65d8588fed43ba460a98 \ No newline at end of file diff --git a/DOCS/html/mcu__wrapper__conf_8h_ad3c4ea41584d0367dfbfb697f5e57456_cgraph.png b/DOCS/html/mcu__wrapper__conf_8h_ad3c4ea41584d0367dfbfb697f5e57456_cgraph.png deleted file mode 100644 index ea27a37339593f25dc1bb7fd754039d8e05390e8..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 62656 zcmaHScR1T`^mbZpwY1e?6h((UYu8q#gxGtlS-T_=d$d)p+B?*aSQS+>vAR&ZV#Eq< zjffC!1x4}3m;SEb^}g5j#vgK#e4cU6xu5&o=R7YB^fWKfvC#nlfD1q^bt3@abUFZV zGW6^j>R+DU)c2wOI^(FLsSY?e{3&QHO$7jM0D$WEOafo8;DbVKp}7aYwg}V0F7Ae> z7!iU^AMfm6vpR)%!t^LbO(TlgIn`CD;Kh@(K2ENThN>|dQLdh}pG#aISsC1o?;+Rj z8CYM}xTk)v+$jB|_eAzW-r!nd!=;aSFj;Afx0*1QOxxc|2yI^jr%--ro}^Cb z|NANnWriJnfVW8F6*C9(^Y4@3ep_E z|4n_&@!K!#B@)MPZ}|SdA2ztxw^EYGpU?~S!T3qU!$}*V5-d5jA9pXLKCPLd!&_FojJs z^V@rim+D2E?`arD;#ehrB%Cx!tM|k$N6~VY^+T^8uY^f>_Da2x*&A1(k6qS3U9B~g zHuuWbG?9)GEA{c=N>f2ZWiD?@E1QBVX1g{wQ-t8$fU^s6U+jbXbpZr>b~Z>G)B)xd z6OJ|-U{d9E+EctUV>TK!re`k7QtPdWQM-%tShXpEj%?ArpVv6r&G+1CKBGU!)7yxf zh69wHalhaAr$H^+;sKcS_K8Jcqp7CJy5`F(tg0sb>Hlq4)-(QV>sN6-cAHPm7<4~r zIx-?t;V8Ci|G-uV* z-LR>rzq}F+zQ|3)uG&<`Z=DE0qr~%ny=ql)Qjv(aT#|NUlO6UWF7^^y%G#O71&3AW z5JLO49M)fc&2<}T&8RJ2(?_o66TlHz4&#*!)o2?hb0gr2-k=zyAkHU=@ztwa@M<3%kS!M1vRK>iifBD z&*)dKwQAQfF4$pyVbf!`UuP1>je4LF*s5ht{mwF-KcKDlq+jds2t}N2MZ}GQBPRp^ zc*{b~t6Z&k*czo)EtoILX z`SC~ov`hZw|7-!s;;yJK5W&%`zr*L(tY@yDcv7sAxa?_>uxp7j?R|6X^6H!+E8-${ zEqBS+-ZyzqH;I$aY87WGJ)sxSniKsz%+ykHO$BE+Fpuh*L z*IXW3Im#tTm8r*MyhMnHep_*BJleIJkQMryF}0F$t8_d?YSvSDek0VM$=^HRG3)gj@MMDD~WN6pJszowl@gT0ud3 zdGCO?nU}~Wtry8YZ@aXwGpK?ZRBnjkyPOA%y5YQ6wT~X}xQH6?u1s9NYchMzuGA@G zKql|?8NiFvAxF4(sa7DWP379MXU|{jDN*3!4vx%A;x`us0IjsBT+(uBolF8x1cr#M95)maxX8f8v`Be z$Byc|GpttIXjzjCk%*n7v1Z(wI55u1SdASDab2Yz{=W0 zi5F71hu_*H3YI)aIj!o~oT23{;L8hC^BjBgQsIn&VP4>mmn{j!$L{iZk~VbkGI5=^ z9=MYV^3IVZhV-(Gf8BJFmlyT|1~;Nb{ko^2IES*UzRF`VUDr6Wl8nkne(r6}R`0I0 ztC0CsJI+0ExQi2qa~)wfptHo~Jxm(MHw}qG=%%2i#YZmS2I@aRx@2d+?@qo5U&H>8 z9VN9SOvo6`dG39fKnt$J4F@cV)f{g|r*DkJOiP(#6H>xkoyy?w{hMdA-W-SS z3j%Ry|lt6ed112yR8( zgD*F7q+A2{yg-LbhsBDD`5F}j8yq>E!Fiac-tu{{Eg5MAWbvJO<11qCP~KF0B5(pJ zziJ~}t94n}q?8{+o;5_da)S)R> zw130MJ6sbw);0(Nozhpn5cZWx2@RTxE61@DnXb|&dXmb8=J>{EU>Lg7lPaST0*-cmp^T?{1>A0h4r&45{{T2#7#+&CHFe(9|Nau zL<~n%RHGD3G~rUc!w^T_3nAKWM*KABV?vRnu^YL@n%%aFV(1>N?|=^VgT2AiXaM7) z>~3W^ODbCEq0v%shuJkz;+#^~Wd4sHT9bbfX5H{~`Ol$Z>Uo$n9EvZTLF9b~mi_j4WZ);YFpjcRFixHU_EqWI*+cxLM1+eP;T4Bdl#s{;0;`cLa}M z<2_<%a*glL3+5ckn`YN7nF+j~+sRAuVDsI9r%$bJx`&0eG7BHZkK~D~Oh>-%@KK>^ zuyiyB_1L%>k+V#KlA*P$=qB)q7X#l4Fg&fwQvKfu?EE6f13Vj>UWwa z3amM$oB%K3ki?PTGlS4@WjXq8$<1jHfgtINS*LGJ2qg%+_8B>s^V08zZheKmLZr9G zW8T@UH`LclYfYBete-eNIWjt$F1&E+*tX|N>St%ykZam(bh>NySO=AO1>?3(=4aa( z%^i%dI@0Rq1QH~fCbkodzepn$WMKbOQnl6v!)&mA56c*AB3>&Q51^mk(2|mtcAsepT6oR;#l0hzNt-wI zrP1L1qm3&IK3uSa>TEJm3&;{6J3i{?7OUNM+P#Fad?NOznz>LZyF%{jT*hxsXTi-b zyQw7{mAsSJhp^szHGB1tbvFeu>j95ZnQsT*u(3X*L|d za;^RUBJ>34|048)qKD{Fe{a?gCpKeJtur@31A1`pIMn%Lo9oa2>F~jP0&SHnLvKX; z@As{kaye}+>o!Wr43ml%z#tRt8jY^aldxUryw$^8pUQ+^{G)pnV^@OSjGPHG!-n5e ztKz8j=00?q&qr>lI%+viXr78}6B`cchuFcM+H%2=9+HN1oi?4;9$oeCU@g|sAd{-b z-S9lDo9<5NmiVT@bWmh>?9nM@V47{d4Wi%R@{i{q327!wiv1Wc(e_imQ;lT|jyLpD zx*X%R%dPLao*DGf*h-L?nIl80Xj%uPvQF9m2m2Kdz*zlS0~jz^3c@id8AZ1MVR)xw z{`g;(A>*dpH7^gV^JnZyf1$SRGK};{MnupdG8X8CnP8j_5>7|aSnvb-W-}Z5l!_nu z$&l^E{+++-!s)-mv~0u~QY&TV(49lOa)}(ZUxQx3+rQS-a+qs&N>J8OF$W>GSy<#oQ7X5ZiTBxK;hzc&NBlKWlcQ3~iiM>Fk90u8T&JXcVVCLKY8|$4@sjG#90-Hxw1i?8A@=nkkyy}nM(&&ldYHprYr^W0 zWlrMVc50T#PInx9vGtGNGteQpfNUwmw|NhCq0?|cnmH8{%MJP$<@XlR4RU0~bk~rV ztmc>Do(rKhAsRASMB8pvwvY5T#@n$rLB?}A&>41eI~hVd!k#!v%cA1W=&dU^H`&E0J*und1e=ll(A)8$#VFHj%!X1y~=W))7Ix)zKg|;&=*c2F^-&8tQ|DFMOScp zuXagh7ymuwD>Vi$X$#H&zBBSrXL0iBA&BRza1|Nza1^MPcILXg6I^@yt- zi&NE@#At74pdRe%P8YpPWju{M;?8?24zFhx4rC*IO2>|z2R#KNo7 z>>IVkdIXLLgv)4X%$nzID*<;F2FgD5h~g!KO5O(k`Vqo|SI85$BG~#pvEfQfySAGL z=Rv4{yqc0WelJC_u&OfKmi=UT)$TCg-@(8|+8>v)mEEzqw&0Zms-N6Y+B`}=()vFt zt6(2cBs25YRcZA{)Z_#UDO~NT&0~vpuXTmV zOzxz_&}iQPEv2S#hRwAuzf#bt2XDo3rON3@&sUuBiuf;w;YVkjP_f6#;we?K_)2{! z#DZMJNT*40&D_5=3~{l$CUa{T%(*mA-H?jc+mZaa$&}oAd0V8|FW4!AiDT#Dk)-+t zQg3)PWdMrnXpIlhn1&1Dsgxz-8Raru4@v|8_1)wYd5CS#>I%RYD^m^e%eM436%58Z zdefEwXU(JYjQ?e=*>2kBB%d_WQ_)=Plyfh2Y2`;5&rpl1{HKy)Ztt`@Y>9sK#tzic zAR?&a9Lj(<6|!)Mn!itH#NL*@#FNR~10kiLH=U;~d4(iHI>s2_o6G}sN}tE)x;SM6 z{@PS0;+Fh$q`RDtg@6|}y^(7b_wa)55vd78_d2ew+;Z&e`pHu6hNb%wxys!A;_hEc ztah@l6w|LBp{-4(bYu`%+)x-mJV%V1mfk+R11Yaxob?Ry1WXp+CI zEheaTKYCU4&QMdGDpn-a*Qt5P+C2`R;uK=3wAngDSP*=-&YCZwD0w^*_hd@A&C*UA zoLo^o+^rP9X)_J~F_ukXeOMMCnY)O3cCzX*PQ3L3#@IEekqLic(_&pvr4E)*CE#Lr z<6{5bz8;YF3#F#1wtynBI;^;v1<~-u4A$<+#r{g>Jf^7ARw?^KUq`)>5wp#DZm_Nn0tS(lwD>Z}wLlnQE+8O&zShVRwjI%jBloZ==}s z+BpFm$<-m7FMqcCRDz|!h5TvYW4wve0b>VKNrFIg$l#D0y=9a_avk>`036m=GQ1!G z!wciemB6bker_~^aGfr+r-o)sw4d9D%8vRcjpJ%fMxFWp2(N}G>(5sUm_Az;D*0xj z9>k5?y^7-AEd7VF05nY}B8kETv~AVhgiLQoYUA2I!gPR=B41tn-0t~olcit(CxCHT zyK2UdewjNacKqWF5*t(g^_a@4#_nKh5a_w_g(Y6b-O3!uAZ>`^7o*rh5{Fh(p(Qc~ zaVAyS-0^>y@vJarMqjUq*FK4Jj_FPs;vxJj$8xMe(spl)&!iNd9~WaIk8bSVzfA@$ zU{feG^YRhnPz-{=11+_Y7509o(s}(tnI2M(bD2Cdw>r^Od_x6pCR950>F#WLKYa0v zl#eoj$^Uw^|M%m_4^lYH_0c}bQoSW}!R)IEO_J&N!R>=7L`QVO=$MG8D60f?mg>-5 zxfjYjP`96|zM4yjs=_jLY+uh@-59FY@Uuh3Z4VeO)qhX__e?prlJ7?)G=6P2R8|AgX~ip(auW-4QcAGIeau-{337L{;k z_?5!*oggZ7yz;WX|5lA9`k2W(9|o`D2uDi8c?Qx?cEW@`)hu*wsGqW9W6LLjt0~X9 z!z#xptL$tmYvP(Tyu8ET$veb)u=gD@f9mND@glV&jQdiCo}DG4rd%d3J@;tx%Tr>d zo}$uJwMejJy?<2HJr&({d1Pr;KCwoZ>U_KsFb-k&8|3Q%x?_ygs@w>e9W=(=NAWp( zSV-XV5)_QnvT6Swz#)YXAQd(dDZ~_$R%WqWZ>kP)1_W6Z3hhd(YuCx_%ss98&uZ20 zs0{3PT1pBhLANLLJHH`Ov0 z?FG!bIIC+e4~X$n&$iDmkErxdI`6&k$4wjN*ocOpT0M)l_jYj#!+}sp;9K$?4k04g zpF=_Vl#&apg;Q^tvIMo0|*Ir3+arF^wo9%oPLQv-ZhV60F!f&^P*{ueQj~4QBQ&))66HIVmwtX5 zj3MSzyyj$Jhcv51g8 zjg1H_v-S+Y!KsJCT{5Uc{xBvmlSb^2C}1^=xX3pAGWWvfl>cI2zo%U>T+%HAtX<$- zB%DsAWHyQFGT-h>Q61on0EY-M3yN}@pVYu6fuvJT0#nNMkPk~BKMwQr&CN~ge5#yD zOzSCAcWpq8fRB%r5yfwO*`#I(eBHLCh}Dcq?k;^k^^jh+sq(kIS6;iZQ+@7R`XTw{ zTXhmgnOsD`Fm;bdbXXN6BroXfRFls%w^69t*>UEdYT=31_s79>cg$cOu?g z4DYBHWcV-A2yz_7KFCO9Px+uk4LzjH1j|$N5=*sz90o+$PLEtQ;-xYDpw{|Hm(J0q zd|G_!ftBypuwse5tHJ=cr8XZ-W*m7a44yoGklNJd)mBTCXLHUQkIgf=?R}(x2@N-I zp;Y@hB$*9|lV^XUnAl8v$Hyl)2T>Zrwo1GUhHyDCP<6vh=bhLFm87+FwN%liJkPCk z1$G1Ck>@z1xO4tI&5IW%X6NxX-yth*kK6I;?6|>J7f}(_;!p!#n$fNjC7wMw^7Yb< zZK+IUhZIlJ)13!f&Ywi_L&IgBPO-EmQpe^|w@M9v*W5OT9c_)@BsQ(jr=UP)Y6n<_ zuDllt)&g1ZX{9+rG-u|TqLaP;R(RVQu;*?7a_e_@miJ63N^Ca7BqByChFS>c@@RABRO4P{8RAP~Hzxj92`Ucyq_ zo*60Rx31))NXJ^u$U_LMu9?)qy%dG4GFya}{QjssJFABGL6#a}Z|bml*{(-MjM>a4 z2_)$(?);3`oHF)vIrTs0J6W|Cj%m)&re+I6qAwNnc{wUuUGW72DHI;+79j`Nh@QE+ zsj!?^q4Zd70i#-`?^EVNiEb+pI@{AqGiXhFd!*?kQG)5+$I$;(wsgDRSC^B+8RtaK zKyZCSDex%$b=2;{E8=8yusP&m=|rxIZQfS%C{d!11DDH<97s;me+5R~q%lPPN<+N? zxqL)z0#Ds-Eau*x6&9Le7Ff`@DKoyE8=u-}@W5xP7Yiw=hqqD;wd7QGS{x;udrg)C ziLu|jG$5FDiG{c!pV)`Hug0drRM0-MM3{1!QzJ`H%E-{ehYs?1go_fG67TOuQ*q%) z)pR)NN#0^;Ch-DiD@N4NLGKeAPS`FYStal(68+ZlU7Rl!aO#;Tlk2u-33h&pn6&=G z8md3X)pRc>mgY4GwTikukV+a?BP1G?ym8H>$b-|No-Yp2{A5>hc~Ihkv~Q0KofGqY~fZQ`-34-SwXyhEvTU)%*&9BZ~VVn%dcD#0PSs z0?yg+-f1U|-nxGE@{X32rV%@W%d~OOLu_g9s4sH%)O~p}GH6q+^Qk~uRLc=`y+1{j z>k0fLiQIU_J>}f0&K?2n?A^Uw=B3_35;srVFj(@sD7iM6O!F37E z($2?+-L*&3k{8(8ue6IT=Nao(n9gk?rsxogoy|1S6OHI2~gLj)VP?A9LpWn zqY}pZQ(vi!pS+w2aia?T2q)LjX#XPx{uV6E5X+c~dQ*vOx0RjBdnI%=vd6%w!VmcH zoVj4*`M^qqem1F&swB6X9O`LDIBSA#nEK06NRmknZ@XV+jLLQYB^M zI6h`ftM&pSj0H=kc$BQns~PMSrq0ZL85&!o4JiH`dX)>FH%dxq& zX}8N>wf)!-U|3>N9y;a`5znw3`-Xy6lF20?3+g6h5KlY5_NRkraJxmRSZjPw4K8PuHPv{$@>GJDp@52S)cibtkIG5Pl4r{a|3BTwyd<6~7FXZdMRZDwCR zt&WmQZ)AJFZ6;9O5Nk`Vq&9yT%Ltx%IX|Sy)oEMOe6 zWwQ$wck0U$zrViN&+g0Upk`6y7@gAXY}aMQTUO+(%{qon$9g62kO1Dd zoyYRH?iAbbZAnf1HX4w-Ol^1SA0#wo?02lY>_j1|avUt)?&*u^jA$#Yiq5*j&{9R2 z2NC<`WclXCZgRZvT>~`^4(5jQf4&8p3l7>ZLQ{gLq2|6%Gt?OwRP&A<<6}MV-W6CF z7E~G_Z56KbBKGUh_Yau+qry1zX%ivh@GuE_zsqaWj-N+=iId*m^tPLl2DSj*)7c`YAP`A6jroB);OgRnQEi>z4!K|K+JeCF{>Bc74N}EZQqPAa$9aQ*773ovM zzsM5>(XNdOU^`hp zo;sDfk4ht5k+mHUfdp-4(EdE`%rGeYPtvgZfi$SYHoa>R|5Hp zby|%w>N|Z{zmJ%KB!Oa1VIPWe@VaBTGlkLwv_gv9#}RI7#G;u8%{6Zdqn4CJ+;NWj zdT45gLLpUF^VMWIr+V{vzfOvPc5W7uc2hDaGLtHrO5wY7v*K@t+!&W6{rBKusXE0$ z>1!@1R(}pr+#42y!aM7m;Rs9sdA=hNf?$#aMG2o(n60opU8u1f1-eKjHt5#wUziDd7G>YG31yxz*-1#b7f zGi?4Kky_Ly-b=M=&R!ubw6YaIP7a^R3=sRH4x>-q$p%(7XKOdMD@INqFa1f~=JrhC z2p{qL=NEb}f8Px1uM9ctBs zPj!-o*lYU+v5>9Igo%9uB)^m$yt0cP=yr<(S-x`_l-A@eY1^y;6GD7DL-x>%{abCC zE|jK{>|%qXG}GYbK+7k4!fh)acQF1%LTh+l>!t1{p}+C<^%zj0UM5jA^Ww61o&5vx zP3J?%`cz6GXPVvAsb%!wTBxCu<2q~x$v_-vTbtiKc+6d*FG{V0TRqV^;m8vBUFZ-I z&I+IISOT~E+6({qXr804r(JPoCnkwBrO!vj_7ZoU_m+Fm{r_8*$%wbz(Q8Q_0m4UH9si#9$;XQM!+x!{!$BmET zQ)c@!j#!0hX-{Br75iG22+d5^WI-j*stC@dTma)w^qRVIZ~7cxzu^3qz=$>Dkl=hM zRCYqTrIk!=*C|P0DS@~+W3E7NWu&KWPipo;s+`s| zkX0)F`25gLu?{8Vf8u%MU9`1exgJmxLt2{Q4GC2IR8RFI&ZWwffyeGHOCA=J&Jl6k zq*KYROus?Ejg>v%UJ*1%irRu>{P@H$Hf*4iZB>M95><4EBq*AtQx@7rUfv5ww zr~$z+`5P+RZ{7^l;~>b^l&*cM3|ahd%^rHobimSVVpHCO=EiY9D*NN0mOx(NsU139 zJklF7ld8`5DowIYzi9H0_GPaw#%5_Pfi>Bqll(IR`d(!b zdpbprYfu>@0?g;bjf$>5L{<9+o7vm8y?=fy&PtkE$+XMBe&>9Y5uGjW!SvhS*6M0g z#&cw|=ktx!fft<5&K9WFTb14mQp*+hkBO3&Lyfz?qLYmegSmUd1upyx5=KbSO3~*71^f$GeBlwH0CUp+@A-*bMs%Q5? z--4hiW6hr4-!M0&@Ovw+_}b8@)@v|3032Q?YF-{n_LvQNY`~WdF|0o*HYjh1__BGY zMceS4wf(%O*BB(^I!onsq1fJ_{G-xOLEM1Nci-~}Yo5K(b=O?urEL+K@CqAqO!*8b zf3gmk+sk56amvt1I)Le2b3&a#2*Ngc`ceB!1+mDFft)43Gw$U&7_Azp_4cG!vc==U zjch$rp@=D+yFH%0CIN2QjaeT9C>GHx@vqlv{K8j{2L&BU^Yu|X+}_%wq-ScIN#hK6%hAcp+wU!xLP{aEQ2vP#G!%aB=J1lr?Re{B*6ru`j49O zpiDpwyi>uaZ7ywjvKYg)y*MDN!$@EPCw78uMvjs9{3MnAc|7$=t_!(Uct6B-sxx#T zr@aqG?bHy}+t#tR?W5vYh)zyJ-GJ??g6~8Tjpl0f-|*ff!3 zBVG*B?Qw9x{IU4gb7Q)I+HNK49&nhGC==?q!}4r!O_bx-Ez>zO7OKq{E-ov%R*W{7 ze&G%KWV`juxX$$uE~q9eAz-<5Cqwons&#g)*#&ZWhZl2g!o)vUUYlr8ec{jJfnI#6 zUB8g~;&>sSt#0Qx3Vn$0;Jve!@xhXDO9rt-#upjKtoi>ii}tCx=g zFU^1|O$FfEwRhBE#rW*iac^tq*Cebt$Z9Q$EtoJ~A)z6nz0T2A{Xj|w$+{>X`q<#W z8L9e4?MzaKLD{VSIc^4uOuRrk%jPzjx8I;ZtcyySj?29Ux2kCNm0^3$aMX&=TVEH2 zfQR{9@W}#FUtOY_ZQE1QJ5P2Y&*+&l(=Rd2QoV@#(nWag3%wgcviRFL>BAv<5BtT| zBM$Z(@Bv!q(FDSc<`TWh5sj_$1 z-y>h%`$g{Z3e*ui`vm%mMGUnZbM}GzP?1JV^uxPK)Ry!#3f>RLj!OdkaKmANT-V_UR zQIL7?0dL;@JTJAuYtj}=p4|ENp{kGZ`FD|&#jf;f?6Ze~QSe+w*u@);$>}{&ln}03 zBXsenr(Gq*{SXamO8Mfbh!mMwS6_eBqOQth)e=}UhO%Xc#l?cZ-lIL7IJI-V)4M-g zntFR676QuLzkw?(wzr0rxn|eJAfmMRbZ(#jG}4nURPVpgW2ArDBwqbiau4C|5ncfR zX}M@lzhPx+<4Xe=c|j+o*%eOg&O5UUEhliXvdZaWMJE!@J+WGs?VlE^p9=TIiTZ|m zI^qZSaS@rJh>?lNrntB`umAl(+aAi}8>7ntt)^ICo^H^ZAF*^HtG%*PNN%&fHnpwm zE#w7atBLf}Aefp!HnfI82?D;Dy6Y2>+Q+p4K;*khjxk^3db&>ryPnqN!bBxr5s|LH zZdIEC_4noZ(=H~HE=l&Y1+*H9cGq-Pt%DuGdF@+1zC2%NOz)Im)`y0RHDQjE{D zo1IZgwiO^%X}W(`F(SLWK@1r82%rS<1~73ZuujReVjGDgT z-kJnOdK{H<9c&J-UVzrjW6R#fwJkz$cCntK0e#w-gHdG3tiC(zPaZ1c9H4fn@#9+1 z;Yd0qQ5>4sDL^3v?UJ^gMP&$qo$P}xf8#Q^f za5oJRtaPEFDD8hnEqFw|!4W|$Uha)ojBBNiN+#DVvWpA|j}DyFO(hA_r@xlbjqqLF z@;p>&(3vajO0)Up{NbDaVO(z6wc|gUvK(b&+wD6Q#8l>Zn3r$DR)78xZsn1pYSisQ z8)^9XO()4Pb0j5%JLkFXj^Wnzu+|aFe`_w_pL&%!#H&*i*ZqlNM69dKVTKd=M1WPk zdOM?4!2HWZo1lGA`kY&J(l6`+tJr=xT+uF#Gi_d`Xb%+JjOG;BczxJLW-zIVdSLGp$Xyr%@z{xOe)>!lA9o673o%uF1@<@&HkL8j>EchYxk zDj!ICTPAt4KXoL_+8H&jwpVA8ykJ$-E!VW#Z7p_rKWkP2To>^Ya_R7B(+I3_DotHo zds0TGSD7pETeq3=Lh^C9YGOULTaD1v-aL*|JLPC(FGU*u(a^VaK3Il_V@ht&j^E{C z!Q_zu#g86p*Hdmd-@Qp%g%7X~W<_(#j%_;83%GW=_6OKTC&&iJt(KTK{HPk=jW>Un zNx#^LCW2Eq-HBWF)Qoo9joL^0LUPLa>c*Cc%G?40MeC9+0KEOFL@3>wTI|RPzeOCZ zN5Y5KMp{=K^4)uXFOSM8A}xp8zKz1B2a1#78WTxB85 zO$w~d^w3yt0*8HD*Q|RzZpqr~a{HSo+^!~8Jk<)ALd2(_w7Dtqizn7_5fNxFhAp87 z7$ZN**89yLew2vXR^@=#HeKpG<{#u|#J5?+UeWS!2)Y04oTI1<@KW1hspKdd;j3Sb zE0uShdciGn{ih6g&xRN7X=q-&hhSW%xq9KhSdO$vcdWNjc6zY!t!kB!j=9TTnPSG; zHvfH}7W!p^D^cNriSXAUvPbuvL1vo2@kg62G{mX@tTD9_9Na2| z{f#XC;fBIeZHSijtz7o3Z%310=PI@dVG@7i82BhTlb3Ug5-+%-~4W+MU$;j zVLqA>3D-eU4b@r!-bo~+>W&@NWG#%t={viP*`J~DRP32OEQW~CC^Jq(l4YdJMS=9( z9J5o8Xp-YEs2;VeNBRj;9)?UP4^jwfGrbuC6*2Bi{{7LeBD~aQrJR?%X?dxhXpn3> zu@pnau-`$CXPX$C*%}%Dm*#7`^rz%?X8x})=bKHqI#jDFDbP$kSzHVzhd(XK=(y;8 zBi=zvWtviyA!_e1R8?>)3HS(wi-RR)oM<1n%?~gK>!)sLTt5H4@>mn*p9q(3J!!sK z_)MNK@w`cru@c*!ICt1R=lafH;0|$PjJOP|7&RWme4a=~R)!OlZrP^NgQv^627e4_vWDYwt z!${#hPX$)Zm$p}F+DhT!H_Cl?!gdH>Xif$){X4KfBYoUf>sAv7d9F;hCxHh^>pN+b z{FFRhZpx6qBIqjM_|gmD#slN4*%B)$zz8FYaqR_`leR*{T(Uf3{o0gC(F;K5@#X+j zy&B^9wYaH7PcwSE+Qf(B=bWtv7+x7XGGlVWEq`z7&iPqZ*u~Gc&pwIqZTkM4 z+Fo0H>Bvv){0X@*kJZU~zb;j#;FX%L9|;D@|JQ}48fPaQkFx+U56jgLQKPc!>YsQc ztRt|MI!19yv{0)0EyIv+QM4YNajbrt_uy5w&1MXWKUKY_<>-!%MAejea^v6c3=uCB z9{dUj|8#M3oeQ?Eg5Nb~5B9lBzI*!I$?flicFl-`e*4vA1x|Adxb>5rl~=QsJMId9 zBqM@*WR&;gsv{ikzugua^o>wC`y_;FQTHb|nzo3g`D4`kQyehHf};3S67(fE3cD0X z@(ynV*-;yqQ#W3-+4^E1SJ<&+2)UK7*5mB5<-o4f;s&lHTs4k{LGcnS?#YqsByk^V zlZguVZ(60cCF*E4k+guCIa2r%v8`~|4=P=`RR)BOpuJa7sNYJPo?A3}!5^;3H||~w z;V0WT)#r@_Q8P2FUNhHX$l&Wj8oje>L_c)+t>LiS$lXOQ=zaX}(=v>(G3~>CKHtvV z6J=*^KYcf8C2)R2GgZo{a*unDd-&I3)`z%iBOgrk62f2c03263%IFSTmf#6VL@hAK z0!mg(8?Gb4V`H_4+#R_L?kloUz@6dAt$qBy`6N+ZpP1PXY`3$fME}=6v+j+>HD4ESIW3l}nbaw$)IK!j#Y`_`}fPz<`w-5BCXExe){hkW7`rYvy%4Fqm{>*^dS zg<6W+dY5)_OSM*bH?wC zlv}7|&vLPer>5#!`>#HQzYW)*(gBl4RhcmzWIW2eDjzB zYQ2ab3<4A%p+(uX!|N1aELWOm6gRr^LB<9n3|AVwI2q=0&f0;@Ngxz_oGz_i8V$)rbk)~cuh|`pJ{B%sQ8ilGkSf1Y3)H~3iJI{nuom~e&zr%O3 zVw@LWuWf~4;oW_1%Iiuewq)vdaly#PmgSJ`i%YI;SI(@u?pvH?3d8qB)!vjE^I3Di z$8I+WVQDTUKN+9t9;nbhtG4+#@a){Pn=*UPSsA!2fI9bRV!!B|GNiq9`S3+t`$o4< zI~QKy_DnbAycxI0N^|rVrgZgs{N)f6x>8ARM*n~hVSDEh?X*o6A%n8eoDBt{IzAJV+;|wOU{FLIU z>(h1E(#_e$*9flDeLVBS{k7hRc7|IiZp$Xjhm%Pz!YWP$|ET;c9JlcaBCzG4$Vo;P zMh@K?mKerFRp+Mu<~lvlD8kL8zoUyl-|>r8VurT;YHFJdxML$*3zmATitoF1bw=+b z^5oWuF{a1-KO@3qJL3kM!SxgkRbe<$7E9do_--R7x=sVU`i>i$~=Pw_E#Z`b6MhT&W# zdHFy@MeLokfgILPdz z4gkG7=maWRI~4}sN`41EvRHBbbTrV-5}ZX_f|@J?pg5DNsb!K?>09Xbak5xC$82a~`vd4gI+5FQD-~q^58mB)-ZUf1#yE^cw4hM@d$ymJWalW2J4^i#9->u=&U}?HRVE*}-uk*r-CERH z_}_MEN%8Le)J=LXNB3v3!Q1AYV;l6sG&u%3HuROeacad*2Di_7ZzN@C+Uw?9;XI0c zQ_Yvx4bMkMhRFxj^<(?jplxL?8RsXG&;T*AYbSi+&fr6B#SR&r9sFIAqQia6li9;_ zp;$*u;`=JMvpxW}@7P(%8KM9^(Zb98^$N79o0seKw;_n;mbVJ?QxVN%&(sq3pu7KE z|DJT!)^7^4==twPaUq|ieA(SEd>gZ}HZ2RidatN6@3iP6uPv@;KW*bKTv!c{XYYqk zaXU5nxW*KV4|G~GlKLWK!JhI(skQNE${Tq`LDJg<`$H`4Rn+L>VHP_rnlW%d4v-f7&AD%`eE$OKtpX%ncQUth-F?xM;p~*34P(YD-^;+dXW%^ISKN?)yV7s6H2>Pr z%?-VkN73i?Sji|`Pk$nefe*65WNVv~=kLlQEx+iq8?_0Zz1z6p9HQ8+$!8>$cY5=* zML>#@asF@HMUWWSC-$znA$vuEoW+n#PChv3N~>4x1z6Yt$-idyQH0nW-shI_F%5T9>Z8$i26Ll?lAyI`z4r_ZCU-Ue@i(93ffR&??&wroi8Ep_)wn?=`u5Y~AL5Q7bTYc(#t_fMQ|<>Qgkazb2?2mHm^izEt0G??7Y z*#8&zujRH_+VtJxdi&fzT3kkM|4ES#kzclvXzG*T?qz=SE1x=HsmDR4O!RZW_B)17 z-DT^#QdQ8+Q$JJtqJw%{9e3=mGo88q6kLAc7bpJ4naK6RJpY-gq~EWs32*OK)@M@# z?U(Syd$PM{PJpM07vqSAT|J#qq(AFOr@*RDy?~|0XTF!d(p-|Cf$1P;W#0?H&h~Go zcu!5|%IOzs0na{|`R|lbcXs}jHn=J{7cRMoS&ve$?>E1PmO8|gtJ0gq8~xVeWZFqm zYTG;abS^e%!%MG@P?ASgtpbtz;ahX&<}@b|m@pX_tH9>7A-kxA(29Ddq)6*9(8eh- zm8&AxBDicb@yMs)k`r3t|Iqc8VO2g~)G(o-q)4|QNO!kNhae^0EzO}D=?3XmT2i{< z2y*CybR7E7-5t-(Pyf&Re0e|c#mfusnc1`V+H0+uL7o!jbL*dH;44O8ywL+slkmHg z*G9``@fNYB@x90J|z@X%1r!tF@_o(wD@AmAI|DXu2!>bH;%b`QfZH82KpQ zV8OXGMWVs*2U_8wYqhtZUCanB-CIn$pe#K1z}$}<7(K4Bj$OOR{%r7 z@hu#xG*sN{bi(~}A-aojN}DmKN#a;?z~B)Dg!QI&!+a2r)2DK2gMoY&2;&{UB=0sK`M~>ltc|gkcT}#Is^I8PD<}pDtw47ET=Tf?` z_GKwl!TUje%LC2*mx%%fz~|n&xA?ItcPZ6o+bfd8D!*mAy3Z~-B2n;eIJ!~rO`AeY z){=xLeY%?D&*$A1u_>H-soJ_reLPrhD9H6Z85ngM?A8DaO|&4SxIEP!z%XL=4tPr< z9Q$Dfzq0NEI;67f=}(fqY&`Lc?6y};>~_uC=m?|QOvUqHnORsCwG*=}fzfpyC+2`# zJLjNR#gx~6fy^a{L-}7utKP7~EVXjpAO)Lzcbxl5(!#W@`BiKx^Ybubjws#QVols| z#u3~-qNQz~4L~?`${QKa1}%@`1_t`wZ~ZxW`GD-dTyJke`3&agUGSfr(%*ti&k^=>ApE=o#lUIlb zN@_63FNl26*gRl6!Ulen5J%;!o`3na+B~WL5B8J+7*kv4L#a>?;$kLA^=66SPLyB@ z9^~t1*c0Y5gS|-P4YZ{g_kO>Z@+WD@f?hP+-UZCcwoG}@S1L5wm|1~?jSnT-J5h9P zT}BVZ;%6EivliODMPm->T{S53##E6y+q>~68XjvE{wL&xNR7+uM2b2+C*H>0-lXo- z9fZ1Gdv&4s`}7hJB}ubKAdf@*>4bz0Hr_`UAV2RxA7qj|o~r%h&5wG4dJ1>I4Wz`m z0o(Eq-G=$dYGLPCr&;UdLg}b!_XMIE8c$9Jhn3*n%4(t(Ne^Cz-pO$S{5zP?^zFIv zhpvgz?XsHh^L_!2f=lbp%^-7~EJb}L+}MAqm^1%6pR(#lLJ+aNlZCQ0szzC={Z=tZ z_H_31ZhhgIujwVm27-Y?%E>SH(GFgoRoJ#6VLS&%eR@p;DYjXK2LSVuc3?gP4nK$w zerbgsElBWm5PjD32+ct_8M^8Kdvvt-QQ;>2`)kK9(I+nxtLMFEmutX!M!oU2b>|zv zUvuos9IRYx@_Jt?T{D1F z0$%&82RPoYklgIa+^8#lZ>vdQ@+v&s0?vfHEd)kLNc@{vk9bHTWy(IyG6WIajXK|_ zJ~Tuil_eiBHBqzY@lC)tl8p+Yfss5}q)8-y)g4(X&Dt3jh7flpj~jBDJqVo+KdVsE zr9YDuqxNSaQ{;pfnP=9x$IPef-KTAIJq(&i#OHp?t^P0PAp8NkwZefW8fR8snQmjX zhD@7S=`49U=@mRL4E{XdIzJ|dif36aKo3C%2LaGkY}=b!Wsa<$-CLGLhf`x0?CwFe zZYOumve?ig}M;b&6rimmmI?LGWbjQro&WSoIA*R}(@YyM;D zb}5GKUW3;EmC2UJRmYl#%TYAyq}~}Uezxa3|3&8(U)dsK@ER>$9A6BTL=$7kCFVZm z7lg8L-jYiq-eZY(W)4`6Vne;S+Z|laVdc#3eWCq4vC?N1l`7&I7-)U zV@bO8&h@s@f-4e}8mWVYaGo6Uz8NSF`+*@WdOg*N0XEpp>niJb4*ogR!-Y95)vH)D z=f*g!v+t#*UPbTBilRc`WNe)!62Idi@rDyWN%FC@zDWy#-7X3bsq>%AX^!YYng$fB zEpnl>xHxg^B24y!2UlB>MW8bp5Rc-XsZI8ZHK zv8X@6V?4=cxL(&;&-d07*+sTNH1aaI2*pIn4KLx00u& zwQX|F*(Q8`9_jcja|>aM+Y3?C9~tf|YS}oksJT4%)cbcd7XU-rlS#asTHz52=Kn%k z!E}Ez?)VM*74BgnyQ!;AIm_Ql$c^Jq>vHa#3laU0&ewQi9Yr}&)L1IIMJJi{p_)t0 z$R&4YaZh;8R^0YA+vMDCfR4TLOj$#56fVNDJEUCcia2}yg1==jb>@?;7@40o&cAA9 z`sK6sS|~(yZXbH#Us@E>>LHtT2Y@;1K-o;=*t&_?PJ|eCxIIb(1mPXxudpFSxkmJYC`g7o@BOdCX=!eB;Mm1V_#k$Er8C<*=NVH^JmNFdT5eaQ)gwFX&e@q-$f65|Pb$KH#nPC!7oO6*m&8c+qhh!(t6} zH}+idQ>bNW9jOz^CyDVN|Mg&;@yw0gi^uMC9Zy-gHg>8~j$H8*3-D-5_F^QWhu#<_ z6Yo1nx6V&Z()qZK&%9~5*X#7@{!>*(D(tZM{hV@`OxcVg(mO_v`ur)_LzJxNnD7JB zof$q=2T}~((r<}qAa<_4{o9<+zge}V6g4fgx9ygZ6?LK&~u1y$QOdM(y%gz9>l4%VV`CxYenZ zeq+X!*C{XmFg`82-#YM}OI24N_GkYfMld5RDyJ(Of#A=Y;!}UE^Q``j{M&EbbIUKB z-A*c!1%YI9ESvS0$f7N=Dp2~60($Nc-({Oz$od~~#v1Sa2wuS9Y0xz`!Lsm%o8~`P znTirx!XZNO`V}pXARY}Wt^xU`D!QMfMYwrn;3!TvPpR39O!f8-fzqLAbu7BNp}L}D z3Qg0m|3F~=lWtYt_p??{&-vi3zsU$p3QIy2NYYl0y{;n$0**>U@)whNMLY6m_ag)s zO*ML{ZCIzclQ&bVQiO#3Sx**nt3!A9Ad}1ILMBNX-AG@t)&fqlt*zBQ5->br@uT{W zlzX3UceVwjW^!mH+5O!7P=-!vx#Ux`v@*^C<5s#FW+|BjqAc1Z=6_MMH5%1McU0&8!dhofvDo&Z_r=Dqn)CIK*I?mVAIcx5d3Xf{Fks$`Mt6yS_x|+*>u{dttYwh7*CUsd#6)Zhr9=TI67Pv zg^BbN$S?Jj39Di?WPOHrrLRLG-+}DB)}MTTHyFpfVxh;~s^~v)D`qMQX2M(nZre;VzK=Cb(Eq;%&~$2U z_nmluMp>vB3gQha)X{drHQ+I6)#O97?aJ%S4^}6@gh>2tt(nqrS%XiD`}SdiIlVNs zMFK+pKkRnPfO7YfedsknAbBx6RJd$R*-q3-k*Z7lYj49p3a{BOIAe5xHd?@L4Ynrh zE7~nWK;S1x!T`!!*+jz*2EhoGS|T?W*33Cgir%|FFFpxZp!N#>iJWQst1h$$^nHH84hvH0#A|=2^DOJAJ60j5I9Qj&2!8TX){Y- z^0@kqzmt^sm*<`m8mvhdHaHMEJpWmo7wGom8?y>odIpPv8mzzm^8ztH&uKRQF2qWG zj?(@j_>p-YCzgCe&2{cgOCE27Zd z^;-Mer=NTWUs(&UOn~A-Pv$N7~sY-zD=C{l_ zJuFUK(hGaIZeOu_7;uo>9Wf=hYt-Y6?T&R=h8=b%WVSS_cPG`~$ne9^RNI*`t|mvdZ**!IB;};d=x%~J9EuS}=OMoQYvyDq3VW<@9c7Em zXV($6fh>_6BM}XEu@;SRa+~nzUlo)Cm$*Jn82>8o>U2}bq0ct#PLR*;S7S|CMwj|W zg0xiaQd{v{2vn{}fT(dW^P(q8n&hi5Fs~rT9L*$>cwrgT-IS|gk)ccJO)|t?*Hr7n zKr^}-F6H%%sKMP}c@BK(n~m)jjQSym0n5`4pW*_s5TsREVjr!HNT-?%v-D`It=3l`ZSv}IE|pw zJn%L7z4>7wcP6n*dw9Md;hsbH@JQyWJ%1p+MUScj`L={l9 zw7f$94?7+?G+gKB0KX0a3LE7AQ9emf@{O6gyzab5B05WqXElkRl4BZoWBo&xFon{! z*-?H6FRW_Y{@iMd<@UR8-SD7=c|5&)udlf<9AeEu0Wx_5EyV=-#Wzg}wigE<2eeJC zmyYqS{`lSYjiw35{i{eO<8jC0Br0XRnk!JHW~7B#ZQBlj841Hn0eA#1WossF>s?be zcpcI6C5)wI_tB}}s=nvMrLCVEIleHABieIsG#uso<-YnQiS`@m91$Sym!PbmbM~U5 z>aUd2S+>+9c3YA3f)1zz88?;c!V6z)sbVauU0F*1mSIl0p&<(H{MNoKF~L?O{(4~4 z`UbW_z*kdum+#SdaVy&zY;G>`tY@MLM}p=lIPP(ju8!UN7v1g|E6EyjLNl>WmlBZ| zf7oASJffbbVhHiV4jbzG!pOViL}TpD9KNn+HeRCJHVGdLIQR_cwnPfRDSM> zOAA(lS&#DR(n z=!0CERa{F~?xPyUW&Fio&MjPVU^osXSLg@JLs6<-ai~z)t1bDGy^75kU~ghzpyP*7D8f^k~zNTg6oA=6t9a+2xyE9B^;Q_@7SK_x>L{B;JVU9vA2K zW_x!5Cten<#p??Qan*mSzyp69Xy*^seCfzcEV20f6s4ti^&h_I zeYH}0clj;BYyOgLX(e!fb^b586yCeaSssDwAhrM2wcqg`)5KPIixBTsx{PAuQOKYl z#TQ3*DL1#L4U!~s5>oj*f4lu_EA1^+pf>*w3E4ZG@`?_Et)xRwZJ1r<-!742tl|r@5m-UZ=uJp{4Z-oxsO_pt_eTkPII)& zomEtRrzJrRw_6|NDjNKbo+kt%K5ALVIw}8p2CP8t3uQ?NBe#BR6}}165|*v9#mo5k zAFBV!$Zy&Jcz0mPmxBC(h^dpC(m=&RNjj?(@9|ngs_y6g^M2KUCC5W~BXw|v;T(~` zWVbek&VWML=_VNA)cJjC$WPQ!y``A5T_kXeTVN5@d|*L~er)Ik4-b!|JD$oDR$D78 zs~ExG9|t{15vVvY`dhS!9rKk-?JxLig;EIoUVlHzDa&f24bC~@`yfj6)AS6GfxXL0x5&_`RLo;TA zffJY}2W`^&##&F7Af)!YTbr9?kj#B75+E5aWb&{ zP2zf)*a%_>_ce8s+0lX;4Cx#uC|nlMD8Z1`KOvZ;xiPQA-N!N(ej}oiy>P)`z!AHd z86H)(AcC44Ed4|%M8s+o8pwrm6WC7Na%3B$A65r62<$%HT|4YVp30PVqAwy^s^+&O=Kw8p*ll9*X(3_8If8jwig+PuaFZJE(e_jBfaw}M*5#r!5{7iLB z6i;7}mn4E)C|i)=a?x$=5m7=ID6K$z{r=n#pCE63Wotjyw{r2Bqv6;8?c7n#Kl_#8 z4PI#Qp8Z>UGg^CfAi^YQNT^zwRMjdRHbx3SyKKNO3#Fl|Vy>5m2Z8a)VeS?g0GpKi zk1oK?Y2hg=9LZwx?_pWJl*pPVc3}o6jK0Ar?Qck%D9O@f7K4wnkSDhN?-2V1?oG!H zO00*GPbSvrNlG-7e?f8lbC&GWsjtRWUCc|Qs^SEC>K0i*M}vctHV9Q;&mx71_NX073R_97BU?;&)=CA*oxS;V? z$N;a)vFtbEOVG0eT@{lH2{L(L{GM%esvog1?-#U(=9N)Npsi~Z8NAUZ&r>g+WbQ*t z{X3eDK$%Kpx_y<|o2x3Jk(+z%`(saqW2;_0Qu?xNU%mbH^3;o(ro72Upj; zbSo<*Xw5qNXfP*MAy`zAL9}ZgxROC^aLtDicGYupIdld$EIyI~`BYRgsXyx4L_KDL zNktyuh+?iY0ly@T{U{Dp3w;vBo*%!PaN(s}{uv=cX@)jpz9|cxicuo|S^OKc0768B zN8&~O`yeXr!rR8537`1%F?F5(=y|s_&2$!n`XVva@rXa92dV8gj9qO5Ubb$&kLOwT2}Pmju-HioxwPy57sZtS5cwQEP>X z5Z{Jp3=l>XVj&l)BdgGxfTDn)VDE-HXm;sFiJ~T6`*^nw`xW@! z4q3PEhAWZ`ZXzxqc-sSFc>l!ZBSns8IlG!^;ZPh}_IybkRdIP^TaKVl8pQy-9a($q9A*BGiE$)glz_RZ&?_9-Qh` zyAy5h1v7k_IdUsJX&cHl>f1EPpUh#pGSCe-EAF(Y;9B#F@iv7{oSDp5;CbJ^S+wW# z#@qbGPjsmdWG>EZj$uH3Z!ylya!n6ljFM;$tz;GHzK@R_q~;X?<;UV<3Umq`Jb_1L~)S-%j*lCW<;#$E8F?4r0OIV?cJxKe$>H-%#)?L)poD?nROXh*# zqL?U{+~ZZ&s}*`4LEg#F&~hHR}g#Z zhpNt$H`05*_(!KnHMU8+@aPK2L;s z``ObE_ea-9Q*N}Y#@-2CPv#8`pO#@xxI34tKd&FW?(5;S4FV!XbwJEV1gLQ@kFp8MD zzl7kygtt0CmpFVZ%pYf0@{ALD#VqL$Mr`E|xi44g1_@f&x zce*&+gH<;UBmW3^0L&N*cDy8w{NMT{W12qc<>84=h-BcbY0nY!c_Q2eZJkHe-FVDy z^lj94(z9!|7fWfKZ$p0_2QoGpae0e9$Vy7&qS zneWQ|bNK{%he8LqSoy97nW<;~X(ZGmKl@{4?Wqu3Q5sFX{;I-ZCLd%r?mI8GSS>fT$#&c1O# zlu>V+M+>`yGvs6_f_NZmODi#0?WI%Csk_DhinR>I9s@qHC5!|Dx~33qH%0mJX@fkd zdOwNXiCdL)0>C>zvTEx92bPA8|@l{`Jt*r zDIY$7_S9V_wf+R+;>3R)o7??WC}-F6-2a9>=2gFICRz*G8?ePdQ z5sf2z>4A#GDFuL2rd;T&QG*vxI$HLdciM?vV!SOaE&2Zpw&S~C5sPr?ER2qFQsuA_ zvg*3q0IwrSW#!S7->6Am?kf#r-PfOE-)U$Gpqb9qZRV>E&B> z{ieJx8Y5#cqum9VV-y#%d)CEANrblz0vY~vEQVard2?YB!B`bYo-JLqloiehRL`BCdmN@U`|q=l0DIF0fYh)yBr{Y^0pQo9rbf7i@fVR7K^01*m$&ueolPfX9rcy$;&)VyHWT z8~r`bXDsq!;`z*Z=LbbE3;Ei@8B_};$fc`Kfp>|5fJ+9k5pb)E$wHRjnVjN)&f1VRGOEEX$`67245*k680Ec7Z?{|b=Y|qQRfZ(#HaOSsQCLMuQ~Ee#NV9a? z>`azlem@Xk&$ekIgS%}}?CW|)+`Zn`MZy-ne3ijxA0rr&7zTwxaZ>pE>k4)5Shlzc z0pEzhT-tV)w`ZddLD~6~Em{+ndkU$BTbD&8kSL!%*QMzn7*O(>8PMm2CslfzjVtGa zf#yNB-e%^Q9^im_O&wRl={P~_gT*Fc4!}x&*vxgx@iYC`a`(~Vrss8`vi(cpu*MlJ%U zqP<}s7Orxk?bL*!2z=b*8tuNEFO$Fsj~I*y8xYM8=|a2S^Sk!F@M~FTxrneDyNU|- zhAhW|2kSrIh*NP9CgjD6rZ<5$03iVlI9!#KukxeVBr5%Ho}(7{X&9~ae3Xp+_e=cB zgD+NTF44gEpW#O%Ylc>NG}1C2Ghj>;1rF_dn|+osuC;#CP+P0nUM)NBIb5XfSEH2o z<@F%{f>E+SN)TjV`n{X*mY=f;IW*)?lgVRZn;pcR0v_<8L^yR%$R*fWm2%U^+I4`R zfuG8M-p&41Uv7V4GNft4-enZ8IL)M@{f~C<>qM7VJ7psoYtaoB;@Vt&LF5r0u{V6I z$P82Vw0W-T~6jK6npM^9KOE<7t@CTsoG3I;Bi_BE>%+0H>5@?#cuT z2g1byEu&2wEh8i2O+~%jLdHzeNgAcXU_$9HzaU~Cr;@W zG?*JABkBM|;AmxY!uUCBh3jQ34WT6nh#xyNDRas%11Jc*K7t>tHU_|UAkp;VI!eg| zO$mtn-|U!H+c}dXz~t*WfD|f@p+ELil~Z2L8Oe{!B(KYW>=PeX8J{9x%Ff;^}db+9@Pu=xTP(>^->2Ry93E1|5DI4=!tx;*OV+zoOU;mrVR zSQ~fH3`!&g?(Vqi#NH`;-9JaoDf++0)oe}m0`YzuqPK5@VfdPgRLA2ZV;=AoAIMT6`oACV<;Z|&| zpUpE6`zgnyE;;i(}e=tKner3t-1B3nuU__T9 zm&`RO?QmEFLMKH!OWc%`=+BThEynE7ZPg3L>*h3M3vtV``GsH2_$Rg+`KYg`*_3lu zLcz;#XEQD4QriF~hi85pHIypFy>|x7k7pyWyv|j1+(VMa4G1uX7hGLFn;}KN?D%e` z`m#`AZp9qZ>DI*p*8{E(RZx-isK7m;j}KK4u5$-ajM<>KDT8{lxku~#g&X`P;3)5X zS&^pPMN$=%C$Sv^`6Ozs$ujrz>{~4oUY>k!TOubPv-FJPru=u~5BdeC?x_kF;_-cU zhI}WFD!%Y)FOc_MKzTIP)FqXKx3F7k2u!j7D}64Z(zPG*!}1c!1IB>Bua@aYz8A=9 z2uf*3M}dr%*4efq${SfSXjjcnwUvCRPyt=YuX9Sf7F|=a=zI9~*_J$j&Q;!ai6F+* z+KT3Yov!jT59nrW?!zRmB*fTr?l*5ENzG6y`5MQw*m_jkf4#3bc&^nBkm}ME8%)5R zubNS30><3Kk_m5_ofX;LH8hB)APL!=@M~MxrALL(O786iV_i>RwvgnT%AHbM)Gik; zA!%gv@ge4y<<~ksqFW1RV*x!#@F-{Oji-nk=|^M^%k{Q2fG50y9;B!i?5UR)d4W1J zNm|{e7!eAjA4$ufbc$|MxFrgBW(fOa(T=7cAq{ZZ2a&@(O+GOj!2U)JrAvqkFd}+^ zz(b*uu@$BhesmXOn|~T2BS9m$ZBD?zYO%ONr`a2e$WFnt@$i0QD&T0CeHERYTsIHf z-IP0|#HAQZW$tm!zx~R7apMbJ#|0O+^r8%mh&_Per0zCdKGf-zF+<-uF?bIwo4ZhN zd`|WF<^bXQN(8IbHkXtARk8r)q=KP&b0!mTe23`}ZU^_{nwJw$FS|(kUOyB%B20+S zsEQLl;?;|9-Z~|&SXr_HP{e-QKX;deuFOC+!NC~Z3mxRIqeUDBe?g`|MPYae%q?ld zSl>CbPyP7I4tC60ch(yo?LLWDl5#V2pRSEsjBn9;{IN2LQFO$^dd}g}<&Om*inDg4 z9lN)CXQ(*p?98OTlBuRVUcnUDxV>Rgj6_jtZ+p!@6xrlBpx!GFnCAolZZLahrBiY8 z9vMG=sS__UdDg|7r8c0avR4zrkLzmhnj_n}!44F7`=J2zLA+&g6@oo5%eIiYFu~D$ zCAZtI(o1V!ofN6y3y!a(pS&@c@j9C0*U>l0NoJm>zq#GDnC9#85 zEhO)G&v-}hAJ*%-N^Xoc_V`RFSAsROGq{`hB8D4G5U2neIq$9QMhmOHva8NX@kVCx zMUpPj0BA%rhE4eVZSc! zf=;oj2M~SoQigW=btf4iI`+Nhivgf0?t4v=St*n1R#A08mapE|WRg;LDZ+;zbWvQ+ z80b8lB)-mrawJ~oFIpW!ad_q7L{hN=4T$o9>U*-#;Ct_q>SH5(lG5o@Fuku~vSmkJ zY_peCs;#ZP5I>;XH2R;GOyp5+T7;g5WD$uv_qI2po@A1Tmn9=~=IPV0bWp*e`wN`D zy1$2JPVdQ|{r{htNwXobKbrCaOV4Q{v^F2GxeKl`$?xofaHJAm;;N(Cw;Q-^yOaal zn3lF5x^8@xUryBA5~{PK3ZeO6KWvFGw+tC&NSbp7l$dt=K){rtjIAAUkyLzwWzOjv z&6Jn1FeNL*vQ&gMfL)T`=23sv`m>v8KSh}##7{`XEkdTsYD@3NMSLBpwK0R(BDqUA zl;H>u#=PYQFFWza+(PrMdG!CWw#n>IEbfjKFFA86t92+v}(7GL|)K{-M9eDVU-W?7FP1-8`TO39y{B!v$5zTIYkwFXx*uX}OM|7umA0;B7 z?#*dT&01bVKhEbgH?lu)QlK2fe76o^Q0^UHO^ZCC zlglSOfRg%iD%8ZbglNmfg7+rcyru8@S`AnvB;u_g=^5|$se9A#KAzbPFlWJDT)S@y9cUsx()cCb;pNwAn|W@zcc#k@=3RLL(k! z=-_m2g9m++G|*32p0Ds`ld43-%>Q=)24mNJpOMsnuSTF}={LKmDo<7o39QY^vAp2e z-IDVcPsMpdFx5lVbI~Xe`=Rubbrq4=F>7JIiFenMTIP$_2-z6oF)|8E_PFc)h-Nkm ziN4DhC?A&{$e;=!#=<8-n6isRf(<5R=uwNcpI{K(!K{O+B)CVLz$}NfXKZ5R-SJ&B zh_j92F+WJ4<<`xT{MVrt-s~>sL8(UMl*Amg6Hj^)7VIEXI;DFl%Ih!Us|Ly%a%}&e z9-49H%5cmSf0npRMnux*-creFVFb8bmA`c*yqros?V3;9fP{9%@gXQRIwlA$8UXZq zW=;PE-(^|PWn;WRfTO*U^WJz|0^lrw%3yz!;0CBa_t6HVn|r_WePQALYwe}Wi`IlE z%rABSpfP@Go-RF~B&aa{z9I zZQ6$sl#8d!sF~8N9^L=aM*a6U8JTsF3*dC`Zv{?S^FAlh;RIC9gJYqCK_RX*t__h6 z*T`c_21^$_QKnAdc}sPgk9qb~w@=NYUzeF}brZ+JQWt*aS92iiTBO*WcH95C)@g<0 zXNb@#aPA6k38Wo&@I68EbtUa5z}eOCOB?|B971f5kH{q>B7!f<2Q)}?yU6zU1PBnaeG>Oyg z5EQ%eY=){bvTs{svov3aot96Yk*Z&EvC^-9NBros_uXTHY57N)H%%5 z_Hyvt@l+gm-1x_w{(g4HY>>ErjT%2RIEz{_C&#(-ex2J^OJyb%ku`&DSA-b05EeD_ ze}{8rF*LMKsN|&@^cp_~j~^v9hFu$9IQm7{W(%4NR%^wfVE@kcvWw#nYfD2DCAt-> zpw~K;@#_4DMlP~yQ{Be8A{{amvh&I$Ce&z9#v)vZ91Ys--dhdbYE*yR2 zeT~qYt}#=eo#vWPJH7(SZS(|iPHkurHa-@Cq`#Xmg(7PX=VJ(9CJ=jMAev3&smw>7B!CgoUh1g;A=mG z$Rvux{Lfdy&C-hA*p-2pHhM;6)=t#~^&Wyg)AW3)$AZwvVPZ?yteBvTb~bu<11eMPr;1`dLgtCP3=k1{pmGfRr=%*d=C`*=Y-kvH#JnF2-M&fj zxs7XgsmHh)Hgv}Ew%Fa>c$2-ieU+;e=8$xz%WJ+A*|9H-B}@^v`Hr6M)v8OiYz+O9 z(d5T93_l4r>>E=f^IV>pkM$DLyc;Ssoz98WhLph_kxteMKhh0o*lHIGor5U|L017_ zE$Y_FLo$ai;E~y{ujeDW1`oNlQjU=2YO2rDVXe`DWM+vFrU*ykz4~^yF3Y7uqS`D2 zqm=g|{hxw72|vjX9JrwA^cDC&Nzd41`I(EC7$r4V?ox1veAwuUF|$MdGwDc&l1@u?8hzsAV#?1u zi(7DYt+m)qT<}APPj$0P@aX7h8iOda$u&)nBkxcK-$9j4PrMPXV=rwQ(~u4$CHBip z@mINvw2-F)*jZw;F7sVu2Xn+g$TGz>|sV&d{BIDHW$dxbyF6L+3al5i6xGKKP74xy+Fh_3} ziu{V5;!<8V`o23jCkTCw1E+~??HB17YEy-m*vHI0e$IkMIT7%YWhV+zi}FV*z6H^u zv+C;xwJSUd-&HJf$42kkyV|Iywxg9EblE%|!54huHW%)Ow^;>rx_?}gW(LkIdzOWR zXG)^*mN|k+5>@d;(N}+W6l;DN=>D#{HpEOOn=)&FIj*gzU_IKnrg@&1Hfizp_0JE9 zo40) zNy(@9`1s_kV|i$fu>x>7X}a4xIBIXjh0#Wf3>@n;Z|~2vKQ}K}`rvho+gmu+&-Dw4 z^X9B|<&f*MLaz|#Hn|5r3uvZI=$`|t1$G*XXS;LBdmlNCfmeBu*iyzf1G3H(_WVmb z`;h!F$2X&y+rvh|Hjr4#ob0#JTgdA}89jiDpqgAt3X>Ev0xmjlR-U2iBnY08_@Npa zO;6fwmIpsHzv5naZ#o@OzDS2bsb zvI9Ifn33>YIxXZyp4od*3HN@N)G^nUc7^mh?NC7usfHh{_rFcuo|(AzfYgzStI>hTox#@wfKZo|wGO9+$xg zCcCj4o5jWuo{kQsxkBHIPUGq>$IK5iF;sdXSme!CQx$qyVjBtuXW^3w$iXF|Xwx2P zNc-W0gR9`-tT!;eig8Rgu}vGl*Cq)cx+#02m?~6aJE>|FlE<^rc3p#ol_i$-l(S#B ztB~`q@>HG2Y#r-sY0a#q#m*5W*fmki5$P_`lS;aCxjnOA5S0||b=57jAGsBOE^!(# z&rV)|qgi&CPcO-s`Fyv~?7cLqnTUf~0h>=kM}0Y~`2mfiwabwuiNKS%%bNweB|Xa@ z^pnXRsGoI8BSn7lO!h(!x2j+3aTLwAA8O}?a;&MY-DTS>&dqsquv2#%rTOMIH8n|Z zeBga7&J-oZ#h1Soj%<_4*@oB1D^Nmwoqjxv8#^BE!5hbMZC2cm?X>XW9h_;fxPyH% zx&8uhue=CZq8m|twf+75L%_VeGz0ZhIxm{l@4Nlx$#j}9CA5piT)uv)YU)*QBA;T^ zB|v6nWgGA(UoOV~+wKeZ_rcPVS2`7krqXwu(HzJc!AjW{2!0IKD&oQd#nl~PdtIa2 zo@IqZ;kObFj(y^qfnDm~^%XibbPGJXE=){eefuj3WA(QkX4NgPUAx$)Peis@6FtA1 zRSP9*8#0x%FgX2KtcvCTiEnIu3(+UxcrOHN@KX)$g}MAGmgVZf9)<-^3BQxQ=W?RSm( zvHnat;xN9mrcs#jkT3Sw)FZw%d2brXq;lZozuf0wUAjvnr_IDD`_FWmX7^`wOXPf+qvHX6i1m|@l|BDe)(KRQFRwT=} zy;dvXBR5|uGpUDWV!DCSBIdlwugfn1E+~+@bP3LIYZ~lmks)E#EV)UMaM87PaojO= zi(%*0*YhTd8}2!H&oa^7|A}l{hpt5&-WCP=K?yg?YqKXd(SD2;JbtgHb!-=Y*`U4> z1(bHVffH+!&YXI2{_y-hRVz5UJqO>(s93F zO^K%a^Eis^tMPjod4m-{1bZX_`V9=1M(P(MN(XjZMHnn&;0O62Pvv_0R_dQp!O@I1 zXN@*E*cs)`(?nx>j~g77Rk!?R|Fh|rw}|~TLGS=wmmjLdl8r1qU0nxlJvvuc+z8_5 zvjKmCs>Oq=e`-+l_P=|CTRys17#^sN)iwnS3v+`L;JvG>+gBg+rb5sP1Yt+S!2i%1 zYu#AM8bNsGa^!n^W=q!sqiwC~Wui1^QZN|=o5`A)e0^LT;?C#gva1lO7{cCY12i@C zL?KqcAIx8e_8M5iHy82V0OC+nfuNR0F++*~I{NCo0%hbQ%2`ZQN{R+&eogXBXx2ra zBMjR%E78S2?*ndpp2`XHc1lN8pSSjaEpq)Rt@0w#VT}E;cQ-X6I_CIrW}c%bvH&^# z1UuoH0oC1kl4ljgUFzC)_}-ko?2fOPYLK{i*KDA)R2~Y#;D>i$f{@sZ8Ra$zFD`QuZ$;gJp zg^VLYv6h15#}IDG(wUT`KNGiidEKl)r|p?rLsV0qC!uN3v?w@ANnvlIP3u+h#tZgs zN!!}QM8Oq^6QZTtVv4yZbl((K;WV6J`I0jHOBYpEzb#p_s-5F7_!9kKUOc5n?P)mo zBl^J(_CDtO2BsWAT6*}H%^YsYL-FP4cMS)_gz~5yK+bRuq%zB#de>~^azIQ&X_JP& zsi~CaOcM1pyot|9tQ;LpUs;=^;p{AlQ>s66Wu6bEn~P251p0$5m!(IbJ@a}uL0e7Z z>UCzoA;|dl^~XH*isO?j$>aC+@Ex}1&jKU9ZKjN_EuV2mw3x%s7u&U)YB;o0T-49z zU^HqPDI0DZzOuX(3vY(Mk~h@!H0_y;p4ack7+oj-x+HRSxpzC$-G}?||$4C`5@aY?1=m#|$(knq(Gc3C;zX(g(2Q%Jc`5jp?DP>udGs2Yfj1T1Qj z5Y)hTdaYX$icc$Cf;Mh(^jKNN(DC~gYsifaMnpMa>c_c7dlZ}_Z>ZCPEOs7hh;=OP z)D!e3wQjRy*N^sx?&7yixMq0%P;{AUuRFWw_6esX*ba?lRYh?Wb^vW9aa=#OAY-Az z=MU84@-MYc;WSP*^h|^b@q05dkDHdGjSwROo%x-MmEqGda@u079hRonhL|@!a*4g0 zyXVfICJUS%$kq9abQt$z)z04UL*es!S$jQSP3{a}J?yx#7A15^3Wa=L8aGPjw`y&W zX%G{+t=QY{y-aM9$?{5`%Gg$;;45XctmYa6NqV|gr`|FDfks>2MI;h?Ae9B`Z zYcqY@1L|%+qRLw?tdx58W#2cl=_xL1tgwrWWlVj^mN{n(Uih?V0dE8vwO2r5-XgrM z6HGRL^IZYYh>=ygUY1&eX?)+(Q149PiXK+=SU3u?tx|Le)<^=*0tK4paLM&}7seAmCZnWB7%;W6vEAfq=2k!E^C&6`?CxM0e zaHcSm^)~>x!gjNCMfDPMejJ;=%EfN#tX%h63%3d7|LE-60iAjV8<_MhSY!iIbOzsM&)FG__7GYSb( z!l@nffS`yN^U)|3p-T6egfpR>$WQ!G&qP5(Cb_oGPk#YW`SuLa7>+z+hCYB!hkdWS zt9Zg&Wd)w{BbbGPanblRU(P&k{JSqKgGhChO;lP$o(ZnC&2f5g0no;$OJ**|D6l3-6xg2fMZqCf}QJkT+!!L`O$JRpMYk z>TUkv__-f~B5TW?qDkLWfdB75*idW)D0Fc?W5*4U?2A>%EFRP~G)zOUo+zjvRumS} z54#fkfC2Y=ZHTwvyhGw1JsX>%P)-!P&wC&vMS*Y#7Pq^^k`>!~F!x>};k0tTUYkNL zfa%Ugjsj!cA8S&a9#-OoC)Zwy_lki3mDI%nvB%x{v?}fxf-{Vv;H~T4jCHWlnBioxddtO} z)ht$yB9Wjgb3v-3OkLMoLN!gzzGC%~Dw5Cai#*FrDIXsgbhF#dhu0`$F@#B3*+O^p zvKO>gV*<&_Rc(N0SkHX@?vl@bm+oV_-8gOFmj*aqpn~DP;yv$b{G9C;+I+m~#NX=x zm>t4eoIWsRWqZnlWtnE8WcZ3TXVD$Grjt({3-vS8aq*UG3}&5%aL)0?o5qQ#dN)^Ia0K4zq_bD^?d`UV`tk57Dr$e^XR#xU zn}Uos6OFMPC2;2A#;4BsC#|1EJM&S^&5)piQ>?hURxj^>U%CCOP9K4bTv^7}sw$Ve z=(!Wc@j;Hu^$cI+gzWShR&%Q<%SE<=Z&uDT@3!o_Lo=KxvSsME$m4a|SJGwkcdj0( zr7mJD=UC+(jtkrv%uec9s;8eD5h@jd>7T$+6gw>P)PE#ho%Lbm#3)=(JU*g!;I#d2 zVtyv!p-pu?z%JfE7c)8Dn;Qc#S&w}R2P5M=7iUr0HON|{>BYvgorfRAh^pCzZYVbz zemTpqijQE=&mcPG8?j05xQRTfm0@$c&S?oey8EgKlgakXXWZD5I-il$zj~2bC3^3& zYI%3qD^={EwPujDjIJ1iCrkpm*YUG(h|~WDLS(Zq7ggUQas6XeGv`0gh_NxNMpAL5 zbt}8TT9Q7m!13N{vbs)=hh9lkcJlNQtgVwf4n!rE^J+(`eHXR}3okn~@I}UbiPas= zlZ4k#J3b9HUqQ*UdAYchNEM^sjN3it^pCTZ_zDB~;B!Y36sL7ieUl!tVX?mDAEMFs zVd49V8r*N1j|eC@aWKE=z8s}f=g0Xbm>RP5#lFj<_PSkx6TfHWN+^N+C}+yXHiMGv zl_ng1)pZrnz|0W3;}NIdSi$R{HWIto@zSv0L-y>~0%RD6UNwvP#prX&*sTqRk$u(m zfF+Vjc)1BJp%8Cz*M)yqN}MucaHu^!YYq;UG#^$X>ybsrczz(iau|j*LOqTDUGwcK zL{%lHo(p?}_NH_8OcTh>ALoaiRvzY4g@<;Hzk8UPm0AR&A;lg+v2-S}KV22~_{AE) z-J3X}>i&ukqr>8ZFLT1~$%okZoAvAHLj59pFN+8b^;fW%viZmM7N+Bc9K8why5sgV zZ%|ShlQCJvoJG79AeeZ=qp)J)fBG?n=*<|pm3zCq>JqblE0ztSVRzqru+lVrvVI+H%@O{KM^IJui3{m5>yX(EX5-;P0P0tlX* zF{TX)wmwF=o-ESUCHaUJZIzrKRWt$|kHK*e;gsO0QG4L*>j_~Mt`>rKyLIcPhC+^* zVXZ(QY|83DUpLgeP|5cxgt5~O2o0p_V09%R{2FCUeD-$KcOuP^Y#{y<-67*AVSp)d z_T@Ck)4sTu6Rr+O85m|iW9b!W(g-lo1bN7TeX>oykT<*&i zmCjqQMg=UC$#etLUwpuH-Qoy8wCD)Gov#GaybRjx$9J`GjITMq`u;vB%(&4SOTsw| zlx;BV8Ulpg7u}za_*ORE`LZ@pY?U`&T9aZLFnkh#_P{G{V$8boBpka&iw zX$7k|(|;>jr|Fp|v>sCt@|M&H`Dl$68UxCfMda2=jdYMFDn##m_bk5msg8gN{UL<} zo^LS>Ea>{(0GgHh@&sn*kb+w~{5D@v20UgpoXS6#1RP<4>fNPp*A3eq4ma7@9S+}n zGUD|`!yGtC`V6U#mLt2mQWSER$VQjr0UkxC5BFW}8XK3O&eY^#sO|3Fg`DLZaoXQ- zjJ^f3bq4XL2S06o8~BGz{mJpX2r6+|c8*9GFq}md>}b9`~xYA_yJRIbZ7TYmHl0gMKS{`T@%T4G;E&q9T>( zq`#sosETLFty$CarZGPUDttHJMwh|cZX|Z9QfFsLsaeIaTlxkjxUU2*kt2xNX!@L zSPAX7&+eA)RF^;(2{}i3lNXDY4z>xJzDy!~q9X5jf!9XSnQ?kLtMPJD(!X%{{T7Wk zoG-zPX*Q9=rR}`u<|hH}^c+za-SU?n0;F4%#Dh){B95NH%gHLIoMh{EDdTX$v!|rE zM&4HbUAL4TPu+E5$wXyA5Pt+%gFKzRZ}y#<`-bxL2K7qFB7bR`dQL{a#O;Q@N6{D) z$ku#C3AqC8Iojo(v-^NS&gm_;07Kkey8Ot#ioS&-0nSCgLzY-$X_eBwnl||Z%oVav z6C=2-z?#J-d&XZ}y&!50kSSLeF73qKB#pM#`L4c zzwT4vL&lS%S6^jZ+X#*4bnJ^;kpDkOeiHlUmit;-`2h1TH&Xx<$j~7yD`D0fOtN7< z9ohr&mDhNiY4s8nT72SlYOi6{G&rsAf_BZMUHZK%tar=}PQ%uNszTCNI#r^Mv@9ah zHI(TUO@H$ho5^4nB3s@uIoC9#QgvQ_tP+jI58Wn9PHwOQ;z@L<`yd_52`m^;DB@JE z_!%dgQt-ETF4Nb^_MCLXVrk>%Y3XldK2_#et}Jy=j@vZ9k(PdTwDf-3cog^m+Iab$ z@5=nfvVt<7PkKx7n|Xn2 zpYJ<+QJsWhNHL5@qd|lEhuq5>-G4PbXf|$YNqDT!^DDI9 z%IiOqs9ADIloKjyi5d_VB=L=l86aLUJDx9}hueS78AST>a=&7MPL~Z*7W3xKRSpwi zir>~=74x8{LdC^Tr#-KM^q-`Rg^;dwHg;e;IbA_BrO0rDgCguNMP(h6C&09BzwYan z)(KSZJaTeunp2(vJQeV5O#2D}8c>l^ezG5(q)tC!7AGejZVcQiP{ zt?ifJd3zIMRi_G1&Zi8vUW0SQ8auAaaI=S5qNUVj5bVga&0Ol5=L>$KK7XEy#r$ej z@xD+$bqVQxX(!!Cu(u;r94VM0)nB}ov3`?57ud7gQRe=&eQy`zc1Do)L1rd9r&3Lz zdR_fY?ArGC(oiSG%UR9e@69lMXe#$g8#brDeEIT3y^=6wo9*KOE{oB zL4T0f;aP1>J3SLqGoA5|UTASuWA$rfJ#~c(n%34*N&UzcZI7#Z(|mz)Yrq_Wu(GJ2 zsp3ktp4F1mDZJgc&n6=)Tf%?xF}H7*Y4T71wj#iOT|dKl-eqa%0_egqpj0?xDyq=e z48?$UsS&S^m>vUCvNMv_Xj!L*iT^Hf1=< z(#CB68GxIt0CGc>ZBL}nos3D>#{Nvw5NZmmx+2Mbr11|SCGV_P-b7$RQs#L%>ct&= zV(&izr4o6hqMTw_PWZY;wciB)n+0Rsm5D+WA z46u>>u`X0nK)YJsR6AEa*g+PUeRk(5cx=G&vbC^)Gb{Cr&*gcb8`;ED`lBp9HHuW% zKT1+Tt&ZRZr72U++0pS+A>~>}+H~H2nODY)zrkB=5$uaVD@D-pWL#$GIE6@i8E;>& z?o!@zzu4%BCVKuDmCXbdfa?3T@)SZB@8RY^S$*7%NeTTVdO~g4`r>mC3Q=_&rAv#CD*_U@}J5iZlVj{B|@VFD1jBuwFtrdO4c&<~KOsVO3iQ2u+$tJtH zHLlr7?E~^R86JYkoOJ4C!ki950o;mT<775W=*oBdpSq>lWSE0&VkY|)4yM!Gqa$+Y zqHS_UMGj1GFIs&tQ7YrvtOIFdAuBF;_bV2gOJ7tsGG;NEXP*s6>#^aj)#*)*dKP*5 z+kzCTjB9+TWY6z7$QjDfDZlH+_OLFr8l!%5N0zkwyiHv>pK^Cr*Y3tR9Ho|KN79p6 ze9E16!_#{Pxl)@&yM6fwC@=bu%!-tD(57Q0&iPkF)DJMO)+hI*EW_E8R982U{bKz} z222dQ(vh)vvr9Adx~8|fsD5$GCWEr`5KC^Ag$4KGnw#hR@-z=Fr?+3@yzX<<_VHCS zJBtI)FnON{*+YTiNLVO?;kQygY+SN;UU6)2YiU)9j+`$1UKgZX#W&g@3}$wV zH+~PqnNnUY5Qfk1bVe4IGzQAch&Q~fZ;sC_e6k{XM5}-!`hcvARCCueiT0qf!7ANQ zKgRT?Y2j^oX{ns7tSlkO*PAGZ*!x-rZ==QIbOyLG`VNrvduAhP;x201l|G;`sW(`e zlZM#=r4Mzr4?x?TH#n@d*=VX@vI3W(6l7=3!_46XncJg=X-jI!x ztm5xy7eQr4augO*Zq(G5QNJy6{-Lti&XDlIg&*69^82#})WRAzlIq>;Fjmi@-Sfya zc4MhJadyHwlm3_4qvne?^@|s?)_r3n0hZY!#vJcfjixu+vHikFjWQrhX@GKZH))%t zy!t60B0|DwrDF2W3vdE9nqhLIOHl$Utr!uYssKXXx38M4K)IWv#t#m1K}+xooJPX& z5qUAXd&ezM)EvXV!GMoU+2nrVC`_++42V}>N}nj8qtyCftzULn?9V^-NNzxM*Cpxf zZ{zvwePXGKWq?%I9V>0dHr>wFk&PcK0Wq(vJ^|p4?}_fx(fpp58oHu& z_G4Cm7hOsNE@<^6(q7?{xKn;kJuXJ2%UA#l6MfsD<5yXP!`6AJ)+qV;=tflHVV&O1 zZuy;!_XjcKJ*SXa*>(j+GXbM{?L#wTl$866&!fw~xsg;Ey@-H;v;*j8T0`jVRyGhC zb7a_ALVuH4Tduc?s#&RP&uyPTz)zOc^@_lY+&>#4X1A(?9A({enhpFb=M>wz(J8zw5jc3kmm6hS-| z(S}9oTl~nYZ0~vpd^Qw~?e0C2Q1)JLmACZeojQRP^#*l{;UI+h5C?}F==0~d5?M8CzYH?ZBV(o7jnMkw<_mTkV{m|MfXNNp`(C?F6P&Qlqg!$Vg z&>R8h&woq^L3Q6JF%PQsm=q=-j!75(SF4nO@9|a!!gEE{q!7oXoIGb+@HL=|qFW0$ zWcwVt%gw9XX9#!;LXSciW9I3C9}|MkGD?V6or-jgo(2#!RE**~{ZO+Z6N~I!`bkV; z-_Rw~rAX6ACcC`6h?CSr)E}4r?pMXO?T$*sF!e<7mIp`j>;xdS3aBP2V5b%QXD17X z{{j+u!Sy)%pL7L+&4d7mNP0*H9wT~W%!u}fYO)#}v~{iJ4V+;lMa>Zy3%oFn>-cd` z|1j&T92q>15Yb3>scy@?%%q6W{?ryt;(X=+OBWs&*KypTB<;~sBlS>%I%=i|*fy}Q z)?uGfuv8P#TM%xu!9{GL+W=!QA_!FbRgW!lx_0@;^2wRT0;|3w0C=m%bk}8*)?&aB z&2*O&kPY&!Z^TdeW<#OSo?-#cJDijYwezt@Z^>+ASE4l<-ib3gY#!?s!U!--BI--n z5?s_rpdNKkSwP=ebiG;?|8tcu)k2Q}klA848+wuZF`6U#<+z{u7WUDBdby^iO6fr6 zhY=LwJ=Ug^dGQ!2jj5LHSFQc+(;a025EX!tVUxg$%W1v2d(Z5i#lYt4Yz9n-dlPwp zn?b8cK7nKQ=j+V`14XQEF7`_e?40~CX)kol2eBPU@4a3)We?pE1Xdsvhl#DofW%lSt&5F#fjmji#Aa6di zCm3_A7z*Dut2R7c2Up=ZR}dt~;^OKdYxL*ejKWl)j0aUCBOqjw-t%c92mHP``&z{! z!oEvsIQpnFudOyCnl*`;s8ZRXX6ux(UPgL+lD;{0FjevKY4xEc3f$S9))g;3oYb_@kHOh42_TPs07dABs$Z|YZ(ktka*?iQz zQ1x9MRbv=PCg)n1G*R5w*LOUX-|2HMo6NX|kB{)QzLyO^*3;eus?+o8w?KjiS)zOE z!WhF$oHC^jB^xLSCW7{3GB+eofancEv`uM+Xb!SPOE(F619wgVo7n)_cAm?BB<;=Q z;bW20Do`$B_@n6LwLPxA>Z}Y2ZrJhjSSQH_`|+ndH#ygIkm4?psapNU4;Qb)dXm#U zcNlb|CE$^v9qix+ zcKrF?rf@7oSuJmk5>H)3Y=+`UE&qBP_kIFuwkI>J8m%C>r7Aba=c(lxMWC@;Be9#?H?A|T z_zv{6LRP<*?qLK4K?-raUQHEkrCiy4g({_;+8tZ|ydQ6bIzKs9w8SoM148_xEM?Q9 zzC+0VX-zFD@GVXr!VH=Di$5u1WoWg*!oAD;FY*79vHr%cYS@?bTg@=n!2N7%%~fII zy08IPMcjGm!-0$8YxDTHIAm;r?Mx`P>AMdg@6SKq}>TZLomX0>njm4$yO4?i_U%=uX0?-lB>EGl38hVv@` zgJ(K`n0GO-6~+ii`=XDsA~1Y`Vr7iGj#$4#Pmae9VOM|2aJd~V75-BIoCf<4aac6@ zX!l}5pT(153;C|q89rhaNHjUO|ekcMFHzF0r2uX3Tfk&3TDR*FLLs-#m^&yrHJ@TLrGM^4mgHuehhLM`h4ZEYE19(d?2twgxnIl0u`G zkibHy-!Zi`AbIJlUHmv%T7gW)?7sLRh3aqLj7#&+Vs&6*ts)kcoXL3nWa1PT;eYS+ zrxXpOHd8DnY6$fenU|q#s>+oLxDR;^X@Qh^0)DZ-u~!ZTfVJC4GY3AJQ32pE!Q1Z| zfh8}?oNiuSbp&xrCf2~8mcN&@&Jw$#Vpl+Edl`0I53HeWwY~cGLf{Yq(1Yh*8_}Op zq>3D)(Q6qYXe|IgcS^%e#H?GMG2~j>O8}_S%(F2j7yTX-8N{TD90soyIYwSZOTp_duJ-t~DC&>!HVHStJ;WU?xVMeJhdAOC#f-bjvagoa)EY z9`9EOqJk@Oi=jO|11>)mf*VDj9i?=UZ596*Gi&7B_k25ofQ68bLK@!VZVvz;Bwn1$ z^w;-vz!idy|DHq%l{t_HY??^_R&@nkk!r|4L9II1ZL? zZ~|mwFO9Rs{6(L1YGo3-qZCSN)id={x#5GwKH=;(CfNW#`qWOk{<3DSL9l4}#bWiG!ROi!6a!sO9V>JfXphGlo9Cy^hcZIg@8RkM1HsN5L-A8-S z5mym5P?I+(Z3d!mRPWf+!?cU75ll0MxF%K?MJ1+DDLsA2i#cH$J0aG6fb9Wj?{#Ed z=)AKUVf{h%d4XVS!o2OgNTc=Suimrtk_mG6fD-OwyameQ&T~d@w<+{HZ?hXf8^fb- z$6wX(iy)1IX)(1{{cs_~wifdMNXnj~g$GgP)tD_N3>t!qe!uPyw{&mu|Gb2WUtL)P zwm~w0R*Z1U5nu+KM4T_QZZJ5>0}H^yN+b_i%-J~~V2?&JnJ2I)WA+8$pofN0T0?2X zbLa+;YYR7j`)}Hv&2{4z$mUhf>fIyYcB#acT)l@p+zyD}Sw}qum$ss=uAU0BY9jg% zU%>f8N&vHdG}VGCB#$n?io@0STMG%KY@CPt1S9a~Ryi%!i98_zFs`UYuz&6LVgjK; zG+$0q=_S~ady5C&oW=q=EZJ)<#?C64ik9?!;C)f0cR_@&Oj*Xog|O&)Vg_;jD-c<~ z)Ags~=eT~qEZ}%t0N{GL+II7shhZIk=eom#-m#b&&t_)Asr$~vNMy@1?m#bbkt?v- z?v<5uJX)MWcn*_7oS$pmK`Gv~N7R5SVqBa^BUdd>-&*L-Z1x~hx=Qe2Z&<0^%i)qq zB&QTUev$rVOhZttfQ#0bDrz(8D6QRKK$V36?oj?|NEo{l#L80FeBH|B0qdInXbp2 z5)ly;!N6#f*{{$_!&|#_{R=gKdl*Y|H9(6gm5AKei+`2254`ymmF=G4Plls*e#qM+ zvZxOtcWC|&(^r9(iP`{0N^RhYu5QcK3A-kJMzx(nL{|=foM*p{{TE!WzsYGZx@}!9 zX)w{LKCy`dP8hJ{DW@GUVi$E8>8alU@XGquAkMfm=)_U;28cOAIHs0ZYn{j{300Z% zk(FA(g5rg0f8y!e`SzZbW1#fN_h|*ZgLB-84H^m97o*XQs)RIRY0=8$RwubL}>5rqx2w&c)YX5|8H@|4PF?Fu%Cm?g?TBmRWU5uC~ z826fAHj6`RCQe`l<#2P^M|Cn$Led7?7PBCfN_0cF7E_iab2sK72Jfc5!n1xii3X*h z5*`J^V`N#E2j_5Z0<~1e2TXj}VONmjm%grd=w{DaoPJM8^P3u%fsQ+A00QX;Kw*+FNArN1YVHE_ z@%p=xkav+|aZ6(Nbq3ND(qoRshrCL=UNH)$TtMaGmvNBH5=sJYEc}n+cJ@aMszCDS z!031xG)MBh)IyNmn7nwoiza-JVbfadN;GKfyCUh&UUq^QOCbIEKg+b38F-Tz8@v6I z)NW&I9AWP+3vAvA4MvAvd(Xb>l!07xEL*ne^ionQwDOc`yx`4fH6W3!- z{T>i>w88uBQeim7YJ7A61E>1Z8Ih*;+QMd2ABPs(1mH&VKa`bhCH~#D- zwiBDrY4BNF#+e?5A>DsN$?PauG%T$)VcQn8)&{sHd#QP>f_#_OP80+CDJn|gmUq#G zzS41CAJ`*x?TdvH1_}Q9ywaurQ~-JQ#7!YC;E7YbNBcyt`DC&g0y_W-E$2x78Dz?9 z{#Xk%eM9uO#34`8pQdnS?J3be!-oYBVoW5ys!oUX=5_$a(ibQF0QBARt;gWjd_yu% zlKk^LFtUCBHStp=1v?demQYJ=TI2tm1|+JJfgr%!2?dlwWOsEv^cd}j?|p?R_utl5 z>G~s&iwF{)ur({GL-KCU-cIBKmIAGxOrXhl#<>b?7xy}oMuqoVi2-^)=_)>>Z(Mv; zRJaUZ7uDoX=za$M2r&fV+`j?@hpovSe?s)h#8|*c#BT9IM9($Q`{ffzY$~h9$de0~ zRfPxih{4F6RYJ5!@7LpE#3YxAK$Gk*eS`T0ILwLn4Q}TbhT!I_MR|ghcGE*BvI|} z`&H`no&29sPn$|f;6U;{V)1XeiN5oC|M%i>Flagp<O1rz>N@F~U)4hhhu~ zm2+`Rk<2rhBv7&0CD+tJq5-vCaO*2X5TY+>$jO$d1oqGFnScd`VsKrGx}*9G*~X9P z!uu@iyvX-X*1frMns~9jiKJt0S8Rsn(gRN+l6q=S`Yi6^RYcXUV%K;Ul^jQU2?raG zL>y8+B!$nLO#jLfr*hgFCUF)X*&IxA%HD0#$OFAsS5s4i3ZgtV7E|Arv_v>!&pL7y znXw57ytPslc&q+nc%G0RE)Rhu2LM400iVnl6@8VQ5p_WAYmI1?r6l^4f~0)c+#y^n zM52{t_Bp@5sU}MJeQbQZr#}utWDFC#ix1m6ob%@tdM^E++1WH!OQ zD7lqSL_Eo6Tak#|_zDlOQ?XJN=x}=y{mp>0Onry}wumItE^N5p?92qQVz>cJcm$*= z=0wWoTb#SF4(DhvBa#uBAC`p2T!aJ3Ey(MVbjwtG>*3)JoUf`tqS3R+W~Dr>KGB1# z^aL-c{FfXGI`hnLR@8ZF&eV6BkQc9dk`0e1eR`Z2tgzWuv707GE4S3T+2o>CM0>bGt9Hl^n2_B;%Aog;z<&OnM|NPN7%!iKm;>_udvXCE41lQP_7|R$5lJf8s6j zzyoG<-ebfLqHg56jkewnN?1N^KWpJ?C>lbk|M|J@eLzZHSxRme%UIof%lDXEH`(jg z!U&9bSiujvV+ZGnVJd`$-;}hHy!Dsuti}(6=g!to8tYuq@E= z&4A0$5)}AW12c^?BM;gie9tcv&f1=fhI#B16_}nRV`u(Yu*{c@8n}v_mf8yfNAWm~ zTs6`@2ilJm?=qW~CpRWIEu}DcHQH54HO2xJEco8j=NAsUe5rP|R3pST zJ4`|YFONfsD)0W;D+GiN=idh<)WXEhk#O_o{knMqXOv9k+7u1!=J;V}N$N!ij2|8X z{jI(H0v$dOEdtqrXiDw%yH7<$p9Mr>rP0A}VJey{8~bnDa7H|)a(9JugI^MY7zk_M z?8IjU4Pmz5K9NKH?>_sT{Py;Tgyhe=I`DmY%|KV+8OriPo8#?FsRrOk#X`eirg;ypJJezl0b zLq+)eLrb-&l?}eIJ&ML($rIQYX>D=o)%5aeEsdnXt1Y3 zy@#1}FR3!Ul1Um4y+t}7ev--m-(B+vA1&BYr&*%)Z)U!Vs0@1?2n^^QdRrUZ={7nY zDE%s86;}DVyJ?KllCyAHLV;I#sFQN>^(-XG_v=sh!%uO;v{(qV5=EGQ8UI-8sKLmsg36N$2I;~T79Z*X%Pfr?wBDr?w`6sOOE-YG8s zombZ!%*fK*YDz3Hxu^K7xg=!T-b3{|z2NBMt>7l(5vW;;5S;*wu zNq(v2de8Nqbp@T>icqt=3$5O@FrGil6IM(8=@`cCB1;aqcg$R!r=_vCxFo7OBc3!B zc<(?wK!YYX^CzR18u$u?2ly)v4R6vQveaq#y8G3zG+x5WL$JVf9tJKyr~w!$2Et0z z6VBTD+&tFvzG{&dx?6r^Cixo5dv2GZzJ6>4*o9}pgC>Xkv?*>?>;vitUg@EmtQR7c zu^uIPv6p5;Awc6_ZnSJCB`w^IkVRZ%ZyfmDKWv!3@mhwp`b~N=6YaA#h5XzA{uflgn;l-O!L%>iyPGzrR|j$7$}9t0b5m*sX(Svz5@YkFnHh8( zz9wIjbbib%Ps`rjwZ@7V79SeH_}%6qxEsY6H$f`P)AHvIqHy{+|JT*~$j&ty9ylb2 zZQwGe2c7pRxe88;zecmRervZgq@P}4Xn1ztVMpu`h5LGW9BRI zP8gKXu5A?9i5Zr0%{_robg(7wxDn&_R3w%#?#MNFWhvRj{4V#+p<->u?nZInDb@B3 zU%J%bQv?L1XMT-pzKVOUezJ{Q!>L7KG_8Dl0wvLn2_v;-S1plWYmD7XG|p^~>STJ0 z^3PW5_(^JU#mWo8WU*%h?o-&$1g4!iCPgxFxKyV`zqCfB6v`%UU&!>@sR018lReX} z5qS@^a`N|xT5pQoUTWT;=HbH7upZ~xNmpe|b0m+&UGLplu+}hJ1l0TC& zGL7+snBRnB7DcOKKADV8%+KpFV8c^wL)>e1*j$P3mfDh*1;c%?)%&Nidzu1O1V5|v z*{S(IgyDZ2v+?>yc-I~g3(dBUxE0e1vyKagSKOiEVF}%2{ZaN&9~q|~tg*oepHA6z zPEv?6yVJbBa`B6(D&AGWJbxKwWgHWDwW zqC~(H9&`1H^{X?4hA`e`P7#;?A+TAax9a|V)A%(LVZogK>~CWup*1qMap-)I^Lyqk zx?HOGX9BtV6T=|eyxZbl| zC&ciuMwL<5?$g(6XJdMeFC$io&C(pa>cOYcob*OiIiyQYd;-2ic zqjfV|?fu4gocmRDK=OT0TjmPy?LoS~hU#6Y@o$yun2U#|W^9zl9hVxU@6_Bd_J0kZ zkv}f=>&az$js2$r2ykg};i?!#g^TWEIwQ|NyJUfpj#DepvEl2QGGqSXc+ws2s9#^*XT??BUxR&v&cMti$J*mk(92QA^vgFqZ}?>e~LA zevBsNv08Y@f$xSG{m#Kbxj1ZdTnY>aeRY%LS@D4ooEHu2r6<&OcDg0{Wk3~^o z8M?q5%YsC})}K>6NchOFMb_l(9zCV?!Ms(Inm55P412Vya1|6?a6CET;sxx(U3`YyWPKUk{MQX znH@1{TGBHRwCOO@NH*?=%tyPCu)+`L^`_4*JiA=@eNg95;e~02`61xLWOi}v-fI0( z-?73$wdF3g(^hriB{sP_G}FD?xL0*OO`jZxQ_Po4{R}4U*(4C|=S=W7hz^6y=G%Y9 zRS{Ljt}zbr%(AZy32Wz%8n9g^e%O+8^xk+9<_9{m<>iAeHvpt!S>Wo?o}B{j&>QFBW?%?zkZ{O>)7Oft1}`|h7)v& z3+Rq5w-QWQsP6@XuF$;M#5(`VnHC7qhKysu^QLalL1*VYV+iN6FWY#JW7>RmuUnEzdf_58 zU$J3#(0xiV4W?B)!Mm(4=Q1}-F)mHr%5!+FEwsBO53S|-*ehOynOS&zzvo*8TJAWT z;O+Zd5k3?1ZmTfC^3M8*69wq>3`BQR^$oyAQcDuTPrO9h;3F_GZrw{;=z<{|m4SOL;AintLb_%0Lk$BQELQmR)Qe zlsOwHfhMnkv&tZ2pff|IHdeXvOmY(EIctJSbld1?7FjQ<_eiGG6MC|LPs0IZ`foKJy_i1MjBB}qHUY9$ zWtkP4#zD5%_VarbF5qNtA@O>yfuN&!;5IF|g5WsBt9czAey`PAp(C_Xfi3Xn5XGbCCi$4AeL8tQVWOx6%A>hU|Q)d};F& zw$i;=x6y#X$a5(BYO$Xk-tOTsabGcJbWM5jo^nlg@hndA&8;A?m16xUWF+^p+^0ac zW63iD!pZS%ZztJz8SpB(g{^KQ#ZvCOEF^wEOMO)?T)t1Q#RB2uBwo-l`9UblTk@2*5GnpXO|CN!FZx2iW_X!rvQp)=MsCb!vnf0IhMbP-IyD!{ zS{A-_OEpPUzoeqvY+UbkuAk6E!?MJh`w(GvS1S3&yBS!c?u7qaRUOnkc4H`DKWitJ z)DuHf{jUmf7VQ!meR9H!2EB_lV7kT{jdJeeC(G5A#?#tBDKVDjDt{BQ#L8fif7%t` z$@T3t9jHi&oka|rjBkJx1^9h@+3n;T1SV6E+7nhMI+SUQL<>H@XbUK_oYvI-J~nUW zvaJzwfxc1e_ds#6YZ*Zj+x>BbHBrPazadw8{aTFCvgFe+vYckA8h|9gkA4Ws{Qqus}R}ouI`0OKHYA!hSM!MHBkOKPbhr_WK! z4~s>x)gAXFF^IlDU|+K+ge4Y^z`MU*o&gXF;v*j)jDO93ga`f)I5M9C^ukx?R!E=v zE}~cUp|Z-DV%O@9evM-E_2&Gz#xEgo^=DJ_m4?(qt)b(9*e^5KDmcK!uBXho!Y34W z0_mr5mErBe+twY!wl_;I`Sm5%cgNN#sOdTD?%axRNQNS;j6c>oVslsF^4}vJYvA+IuG@)u z;w9Yc+^Dmhv}tT`)!Mlx3gMBdewWf*RUpgNVc9f)9Ckoo90o$>@IuoVb zWoqKQzt22w7VsF216xkiqkM^Y>?`dAl(baW$^CFY<-%+1?O(oip`nIR0GR$W3$914`_FK>E=uh zO;y`WUT)H`tkm8oouToN4}^ZrL1zpxk#5r(G38iE<-fCiMJ@idk@3aIHAl=+%wA1v z3IBlu|8nKxxxwbOGKXcKhSOf<2g0b7B7<@#RplE?mMu#OVJq(hvF4WtJKxSs!EP{@ z$^4-vk4dpNj9#K{C6jeDqEuP`+m(eKzn_4}UyWUgQ|!-zMtt>$DvkN0lC8*1l9$OU zYbS}lQX3UGr=iiqGA=p;`W<$Zf0t6mCRjjuEQ?jxc&zHXg$I90!kYHOr$+CKsB_5+ zD=DU&e~%Ar?s2-V&7B8!XuladFI=ZvG`4r*iKcLr8(LE#7@Nis0}jjo@h3)U$v(2wmVU@l@AwDVfTH7s3Q7 z)BhM7M(0~1zpik?>#`(~bfDImBn8Ev+s4EvTP&M&lNMh5G484MP0!WmOiK*c0_qy8 z*N@wZq}sVKC6c#Db?i0R%0#CY?y;f4Qj?`MrN{->jqZ%5)_h0n#4yWKs(3L}j~~#2 zEz12b&da?M+9gavFA7ojQ!j4rscKr3s{oS2%S)h+EFNK(6529|-X(TB&&`Q1KKCA? z1qM;L6gm1ethOQ-lmw3#dw0k_u0N;2_|Ovqe$f5;I$v-f|6CDMjcnfFzwwjvmmOID z!aRIst4_8s*adt)1HOM{<}5YYM<&hqAtS*#GUa$1XYwfn=dIrF`W$gUT%7-4 zg+a#TmV?(NpVG5=uw`zoT?O(mq30*(wv(wd$eu1S?6pvE4=LC@7=puG7&CnwNcO;PALFx~eW{?PjS3)4OOHuL|zw(yhI)FDQr zZ(8_VWovi3RZzxfHSL9E(Mk=IDxV~~*P0=R|aO)K7ty@IofpV z&+zmz6r`#o_*D5@{vYmqq8NX^U;e-~?hwsd-a|a?GMle8g)ggvKk|nKU<$OtJbGgy zwP@2%6~I;}io5a1Og=w~gDzBBH|^Bm9(4+1O_@#z=daKO{_Bk>lRI<+?qa(0&1*6oeoD*L%vCYib|sE=jk=Y9XEEmI)zbMe0y)8dj5`8?I+sb)yRj)v))`Gz z!Pm~^xyv5!;huH@6kwmU3yB*!67q4yMHe%n-QWqqE@xv?Nsts7=S6CNZ>ss8ic?&4 z^~4SL?4OuL5p`VQ^na_qu-J;~;*;Dm&-k-iR^Tp_s&{zKElDE8Bk)+AVf8^Et$^0M zk{p!pQkO+S@4Cqy%+h zG)^srHH!y)Y2hW&tUGN(ZWZU=Yj9v410_E>91;`X>*#Cof~jECyABU#tjx^I^KYv& z>P|tiWt*xquS-dnZ1UTvr@Ml_$Fl(?n&%*Yx>|wWdU?;L0K>QOlk^)ODJAVA%eA6kM)|on zE?C;8F$v279&$SlJ1f0R3m6QTQihQZ8P|`|YvlevWqf%&lwH`rQWWi?2$e0_wt+m zPul0BA6ofKgS4tS{;};^a^`|525Pn6g07m?tYS_G6_ ziMhv!{$#`w*1R{Goc@MK?2fdm029x2wl%tAcs#-*|TxG0fqziQNtg!!3guRRM%NoSn-8;vEsYLHXI zZ9oLdZkEVN5KPVL9_7QlE(Tm}D+`43!Q0DfMAxArY33aPpFhJV#-?+MK?)J!Em5m_ zBO{RD)s@yPTIpQ$j~4g`m}vQ7%BY8%eCK`4P^B@` z^wGDQuD*rK=3-T=vGM`sIfrxadMY~PnZrYay74qU30Hre0TZl%(>DU^3--0pOvPQ| zhnb8&iar5OtRe>$9f+?fY@1G?*(xF>lV&SPKGV<85c+27C8O1r`EY%m%I30Qo>eL3 zijqO2gwor4%uno$VL9v&?paO5a4{^#h1V);foa0jWXEdHk8rPI$`F?sz*FdPsx!<9 zzG4W?IW@W7mx-{e{8zkU?;b2WbA2GcYLj#Zvg$JJXqUW3_)qzfX5)rC<#kVV`%J@7 z0r_1r(#H{R(X3AIr*9T6`LhXde)z)7l9M)O$*Q8%K$Kd~AkCL`@pCKpg+@2|fK=7Eb5dSVQ{((b-e-*W1WnrKNXOIol9L*}=9GJa zHoh`gkic&U0pm7=KtgG{JRZO3fI5CJ-nknlVS5;bcw&*kVY`v_@<#0Z;{k+S$GV#E z(*s;pwQX!&X@2>7n?lsl|1?zzKssXF-SZwQycHE10sxIYMVF5UdVz%98?-T9IAic~ z+K1#o%|%uW&n4$O)iuaxkfP#-$FT9lqct)Udgb0k*tvB`Mn{A61pmHk7x_14z%P$Z z3nHSucg{pS1KK8{Ph%lPDo^*7L^ii~%Xa;j_q1rg(3SIn$`1ycG?8Y+kQRhdy`?G; zM|?CX`4!XC(@)W9;rK@%pd%wA8JrNUOFIiJl|IX5U#*luN=-g(8?sO23cff|QUO}1 zT8#2)I4pD}@5iN#863K*;yuD0;<~gaZT~BLpV7ADm5KMeC!IX+E{;|VYn3arJXbaU zE%HK<^OyBRZQZNx*K4TcxL_CT>87&ayV*``=1k>4BaIPRGRQW)b4!Iw8WpOhAdp&o zAM4Es23#B2Cv@c!4v2zzHv~M1yp9mn&B$QDMDBzGVz14tNV}XlX&f*$g*WM$3h3;` zTvXsU-#{r^GkapTy<_^+JITvLt8rjCh0hjdfY3o$Xb6<#{MFVp0RF$$GCxbnAl+er z;Sb(F*9?6cuMq3k(-zw@y%Rv8w`Ag6Jt}4;q3;6O_P#_XI+@fKMSI(|Wr7x860LI85z07KGc{E6iXr7GU4?e+g9Z{ybDJ!(P}fQKSSk_phuP zYTTt1(zMPQ z={Z2{mK0vJXH4J&Gbe;%#{0=}^`{R}eKeh7(QA5XLe!%j${i7_P4JGgW+2nm!n9k; zN8Zv*N(w`~LB5e4TN^$&Y)p&PD0}l4HaoL8uEgoGH!9SJ5X_Q*Ie3@4Pm!L`L2KHQ zm9TJ86_15)sFialoC38#Kp;>&eNI>m`jvd)&?Gzg(xy$C?e6Ol%-XO^M0imZ=8xLj zP+2On;5)z-5yqpFGFVa;7>-xuX7mZ%`hqVB8y2HlRe45J*3wOz)a8a}OJ1u*Ek=d`x2$sUVFbWh*U)5iG#4;wN8HAve?k#}8X<2!a@a+}>dpD8IEaUzZaA@ISAe<53Jq>+QD z&9Lpl@kZR!Nv1j3B54$ys$TV1v~0?}`*67dw!!_+e{oL`W`XHy=M@jjC=pJY{*57m zj)ip+qVGrH3^yXdBYmXsCTt~G$Gqkur3P%E#5X8!Nvh*W_7aNfj2bq3Dfms7#!W1E zVHaPRX~bn_+2zyFu}@r{AooAx4N0eW-LzjBx%GvIO~5G?_?&jDZ>POYg2(lc4}kk} z41vw}u6$s8+DM1=^&ijs?nIrBh$S1VCzd3K)JcJ(&c~UmowJCeCzf+;#S}`J;eg;T zFmQTo*rE7$wC^vC8B#gyrmL7E?&ZI?Pd4Z$i6jqPCbCx^rZzv@m0{WO;D2-mXSuSO z&i1(AF`Q2rUSZ&O?z(l$Kh`)_707&f=G?7R-JDl0_Md>6VX>ke;p=5v*HC8FAA0T6 z;)(4zKPVnMmreGq)0?>t1m?`SNS==6-6-Q0UsnlN-7vh-K~>g`7~#9?l>shD6iisA zF85`%;oQ`;Ifa#PKa;of>3gRe!&hXh>W?6jN(>F|h~}AKb!!v__d{;}^YhB2d@}0R zOP4;hCM?|hAS|RVupe_lx!q9nl&zV1{>HOM-`_GLRI|}1__2lZ6N}YFZTdM)N5Aq7+O8<#H|=QkY5NMw^}OlB#m7 z>b{GmTXLXiMqhI+dFIzyCLb}M@CZa=F**kvKWBnj(`40%QzW$LA2E93Vd|AON`DA@ znhTUnCUdsCUu_rLR}S+~#AKZi4QR*i3j02-y|lDc%#XZtNB{2j^6AG}!BASg>aVBX zon{kod@w%JvuRwTj1yZ7bh<$}8j3Y6yfuCq`FHDZ z`UHvyQYmSnO4EtAqf{nH!b1NRF?GOFGEn&BuoCA0o*%&eE^AW}`>1M5|YJALMZ80F!_? z?`{)Xw1ZWq&;WWKew%g!;#!&FR-)?!aF#J4faR9;=X#cHLG^pjCv2HWo!e+IL~KHe z3wDh@D3&HeEtrkWID!yl>AA{0t0I7%Jw=bj)tA~}yiVVHyS%>3U zGXt6RJmu*VL_L~>m?|^^A&)n`wv#~UflgsP}8W?+3i&gPq?d&Lo=G9eYO zFxQ^yTdM0uM!5Oo)lVYO=Dfwu?g?-F6c$>{CP%vt#E@>e--)nvFZU_AP39_El<{B7 z+e!Kg)XyGeFzfpy7ggGNlqLoBEk7dZaKnveo$BoGfXV;S4#OW$@MxTzi1CJZmr#te z4|pd1sOgMas^gtG>AyLrT@r_!B0VQtQJ0N&R`~I!8s}%|=HJ3AwgfYHC-5ad*EnaP z2gl6I09#;7%j3CrB4CvJft_xHccsC}AkUH?Z@Yg~4d1z_x44{;%||gQ%RD_3q&O@e zA7#)AHTr6La3^kZy`m4cEd-#VUmRXe*QA`k3QGR)I~b=ZQvGLZV_E%80?NFz&(P=1 z<*GQ_nxnVu8a?u2jLNUSi>u;oO5WL7<9s8@pDTHntHmdzFrfGB-wPhZ-O0h?E|&gH zBc~Bq;|m6Nq19R*SlcR|LEnVH%^bk0Ec2{5A7 zxxW@OF1g@_5mZTRc6wt6uR3WZ8UT-%SQcPmIer$VrFp9g`9}3s8*g#9yjaa9hTo(W zS+IvmXySGK`t8P7{za*c#4lKasu|r@<9@G8On{Dy)T{J!f*u3(forFL@9OaCy&9J; z{i^;rBFVc5w49_W(?(^A#9w({w_j_?RNQ;Fwn#d^uJMYZ zBEy&T!?E@k83gD}?c@GkiJs=XZ7Z{yPWhF#gDQLOe{8tcYWUo-ZE%XY$>v(6M#}JN z6|ZWo>Gn#ku5Vp)^RQ$Y`SSv851wGNX)ZX~ z)I9arxw7!+J>PqF#?%2S$T+b_!4d%)I1WH=V&V*F|4^0uEswOVR0am63356gS(Dqn zl{nwM(oa>BbTO`>&1pKJp4;bGp6xO?Yveu}yn+u)tVa@1EIJ;{R!I$CQP5~8R=N?8 zECVvpihZ}>0f-R>xKo}|qo@DrN=frKcI;$RxBX)ggo`TyEvy@^&8%2aW-Rh3ty)Qw z-)BVobXEQg4*dq5&`X4C)6=I5PwU@v_!M64b|0VJCR9-}bbn=a)$QovSAHoo5}Df> zUK|GOxf)utOe4crBm`i$8I_4K@sNT*%JaS}nohg1!i!9-Xz=x^>UUzI*g9pla+MZ_ zSG*0{KW0SeveZg%a$3s+69Ouf%EZT+5eIn?(daB*;T1!IS^n7`mk!SXbhs#a3VR3i zm`YCQeL#F>q6BG~*jYO=qMUm^%RZS5@}et4iiVxgg+KA{{EGB(zsR_psgcMX{Gt%7 z-7>G-;YCy{;4xR5fc6|~3+T2`hObYZ#YuBXYVK)L6=ia`H zK~p&Il25cP-v!IEL&QEPl?24sOHnJ&o)=w88sI4}?n>{=%8YqWbyY+vr!R0a+%5)i z?>3Yb{QEk6KVHwA@+Q-9S`gPZaE3Sm@O8o#3@wcEVzalJIlu$<{|(a*N}%OU+0q;e z2qlg|C?Pkczpy{N88I&a^Vr)J=5TcNK3I6;kIcpF(sMSYzykxXr6#eZVT=te7t4OV zU5uUAX<1l*fVXRmzJ6dixFj+J8$BC}WtMQc_IY4lSWYHU30in{9z?o1HP!2;*8nlEU0Z5Z!_YFUknCvADH?Xhhlb>c23VE=hoE4qBaoO66NZoyk}j+Jx2k{t5{xyYn1&_o0- z4q=xpd|s+@A<_e%f-Ypom8@&rt=R{31I3|*>#O5~FMOlfl%O)*+da;5?PE@p$6>AT%Oe5J>ON!FG2h8mlYkh{E zHf`+p`&Sp@4{egwR?O?XceOKXJqsM@;NvSvRk#VW8847-+TW)>@vVAZY`DQ`)S{OW z?X>oDfSomk{cnh{h`@vgsp=xCNga~XOG&jnB%q1g;{0_uYQB!~d4GM8ZWE`M>`z%E zR7dRLv(T--xcy?83NOm)O?0YB7EWT>erALK*H2_y|B2I=KL=)@m)^h2(G5za9*h&| zdTSw*x1QKxiPKc1XGHd~e%#B>$I5)Tm1xr3T)S_D-ptJ{h~KT-5jaxyk`!bSSd3n3 zEsxQgAy~JLsk>^eVh@#!u<;$=cXH=mjDL6~_=LbRZa~?C7+k1Z7Zvo!F1oMbvarBWpK8Z^=9N7ihLqx95_3ue#%we^0PFicofuq#pY>kSp<324-t znwp?2RM9>NyWCNK_3DO(5Qm~BuY#Tr+w*p|qUNfmwEW2#DhC}DGv|aW)F$+ze&!e8 zI3T;_a9lSoW{vwic2(P^jVvjK3bvrhBkTK$-_2hCg8->EF;h|Kn}N!%XJV?!$+$aj ziJ%c>*AeL7z+yRGZjbYj?`nXpd@nqd#tqQuM`pNxcpP^$=mVzg`pRXX#j>ZdYwSd^ zTpmIzc}r9c>|K^&49L$MP!IoYQ2Tg%LPsUdwdxKbmSqnUPOylYF}fem3J8;GO>a1X z5aWGi))~{;9I5J5D*qzNx?PV8i7b_uG?@Go-+miEYBI^+vr&Ir(d`KH^yrs%Lu>Bf z=JZzhRwZxZ$(w6HP;ERe$<>^clHKgH6bElHRE!d+>03@5f8`wcY&s+l^*qh`xq0vi zyq%aEQOd-)p$Zs?Z&r5*>Y9HeCJ3=fL6_HG2|x<*AKIsU_p8!trj3wcP*moBF`xdU!8=T z-Bsz~T)f?8A7h=3A3U&mac57T1JR=#W}P@+1gPMC$l-ja+7~^EL5Iw_m|=^xU#wfH z)$`X`@!XDxeA%Zj{@YteytFUdU8Yx4k@ss0S- z0=J}ZL9E@>$@s)C7O&+@nG2cw9DoOOu}{AF|G7NX(`on*21M=Je={l@W6$qoL3tXzX*cWmtSGU9;-mm1q7DTR-b=-Y{`tGepzr(-(N% zui;y51Hi55{$yW(k(XzltUW(KuWEv9u92Y{zp-a0+h%H}V%9^uw(-s&?wjRri<;rK z#*)c9Ve!bU*Wo7Wyo5{guS`$Xfbbd6=6c-3z5I8@VDogH1?;X0=t_oDOL*a`(TS~N z%hr0yS()Z`GGFA@$ME!}}$6pJX~Z zEPQN@-taPVx$;uas~lAwWy|Y) zfEkF+rr>q{yR5k>MJ>8ubP9YVHo^v^{po?QL)&GBMb92sFSX*Mrw^p|9z21#*%8`7 zqm^#%SLnKJV#)n;UL$ko9eyQg(>IS*u0BC(p=zm5N(!|Z9g2aJeG!*WaYlT)ei-^o zqb`RH&chLLq1XFi!PxihXK4JBR{PPPkFQ%=hF80dohxoEO9ve`k(r|` zT{}&XnR!4*!&+F!yHGvpkZfT40aL@-VP|Cm!M7<6#2zuSqMa6JGRR>Z5H3Rg&Sa0- znuQd@D&c$_spCsmr(zlK`zhz&7P(AOaL`WNby0_Pj9dDj^WNxS!0n^V)N6jtI!84& zBahXd@16;OZbks<|9xR+#550RkDV=~*zq>x17N|eqEs>9w6F+yA^Ygq?B{Ky8ro|& zo_C|BMQ@XbgZe%y+#Gb>xiza+Se|en(mp}Dbe8b$z5eO#ASe&LPM!KFx;KTDsZ$b&E7^B7S5~rVi|Qy{1qFye6#e%s>{9ekD8b=OsI>~{qaq&nT>!^@lO|7 z8b;?t&uH!|jkve#GUC~>V_)~Fu^d11HrIepg7YjUYxI=9fdTL3uP1(;k302yuc0AE zL+3bKgho*eZ@Io&Kd}|JWy6k0lWM=ah zEKs4N+J<-E79KN|T#fPZ|D}|!^(8g73H+SV4<(^!qjSTnv!CZl7MzdwQZm&TtJ@3T zoLN@DJlD7+B&4k@kStl~ zZKHNrZ+;CA_RLjsz7D6xgolS0%eqxwim_$P-6j@ML++@ktQ;Bc??=_n(flW6_nG@W ze8_+9+_{FUkM*}arfdCVa#USiT}4}H#JvX(PHJmwU-eMt!|i1Z5y~yJ&C4@iZC@Q~ zyZtUK&-ZWRVsWv*7xXy}Zr$=hNcViyx)f!tw*5~>cJOK6j{oYjr_BsWxfR*2dHL(5 zPLW2Q0$csK2KGbFLdl?-^xQ8;g0!)ol%18+=4Y`Dk{TFn-RN32Q@WM#l z_TxFCIH#{g#A6yd_}F^ypBa+sKsijsTS*%Hu7wpR*A~N8t}AMny(>ul+b%2axSb-T zGV`U6Oj + @@ -83,112 +84,186 @@ $(function() { codefold.init(0); });
    mcu_wrapper_conf.h
     @@ -162,6 +167,8 @@ Variables
    +

    Definition at line 12 of file mexing.m.

    +
    diff --git a/DOCS/html/mexing_8m_source.html b/DOCS/html/mexing_8m_source.html new file mode 100644 index 0000000..d21171f --- /dev/null +++ b/DOCS/html/mexing_8m_source.html @@ -0,0 +1,111 @@ + + + + + + + +STM MATLAB Simulator: F:/Work/Projects/MATLAB/matlab_stm_emulate/mexing.m Source File + + + + + + + + + + + + +
    +
    + + + + + + +
    +
    STM MATLAB Simulator +
    +
    +
    + + + + + + + + +
    + +
    +
    + + +
    +
    +
    +
    +
    +
    Loading...
    +
    Searching...
    +
    No Matches
    +
    +
    +
    +
    + +
    +
    F:/Work/Projects/MATLAB/matlab_stm_emulate/mexing.m
    +
    +
    +Go to the documentation of this file.
    1% Компилирует S-function
    +
    2clear, clc,
    +
    3
    +
    4set = mex.getCompilerConfigurations('C', 'Selected');
    +
    5
    +
    6Ts = 0.000001;
    +
    7
    +
    8delete("*.mexw64")
    +
    9delete("*.mexw64.pdb")
    +
    10delete(".\MCU_Wrapper\Outputs\*.*");
    +
    11
    +
    12status=system('.\MCU_Wrapper\run_mex.bat debug');
    +
    13
    +
    14if status==0
    +
    15 beep
    +
    16else
    +
    17 error('Error!');
    +
    18end
    +
    19
    +
    getCompilerConfigurations
    'C', 'Selected' getCompilerConfigurations()
    +
    status
    status
    Definition mexing.m:12
    +
    Ts
    Ts
    Definition mexing.m:6
    +
    + +
    +Generated by doxygen 1.10.0 +
    + + diff --git a/DOCS/html/pages.html b/DOCS/html/pages.html deleted file mode 100644 index 7fcd71e..0000000 --- a/DOCS/html/pages.html +++ /dev/null @@ -1,88 +0,0 @@ - - - - - - - -STM MATLAB Simulator: Related Pages - - - - - - - - - - - -
    -
    - - - - - - -
    -
    STM MATLAB Simulator -
    -
    -
    - - - - - - - -
    - -
    -
    - - -
    -
    -
    -
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    -
    Loading...
    -
    Searching...
    -
    No Matches
    -
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    -
    -
    - -
    -
    Related Pages
    -
    -
    -
    Here is a list of all related documentation pages:
    - - -
     MATLAB STM32 EMULATOR
    -
    -
    - -
    -Generated by doxygen 1.10.0 -
    - - diff --git a/DOCS/html/run__mex_8bat.html b/DOCS/html/run__mex_8bat.html index f599062..b85a6a1 100644 --- a/DOCS/html/run__mex_8bat.html +++ b/DOCS/html/run__mex_8bat.html @@ -14,6 +14,7 @@ + @@ -78,7 +79,110 @@ $(function() {
    run_mex.bat File Reference
    -
    + +

    Батник Ð´Ð»Ñ ÐºÐ¾Ð¼Ð¿Ð¸Ð»Ñции оболочки МК. +More...

    + +

    Go to the source code of this file.

    +

    Detailed Description

    +

    Батник Ð´Ð»Ñ ÐºÐ¾Ð¼Ð¿Ð¸Ð»Ñции оболочки МК.

    +

    ВызываетÑÑ Ð² матлабе из mexing.m.

    +

    ИÑходный код батника:

    @echo off
    +
    +
    set defines=-D"STM32F407xx" -D"USE_HAL_DRIVER"^
    +
    -D"MATLAB"^
    +
    -D"__sizeof_ptr=8"
    +
    :: -------------------------USERS PATHS AND CODE---------------------------
    +
    :: заголовочные файлы (не добавлÑÑ‚ÑŒ CMSIS и HAL, они добавлены ниже)
    +
    set includes_USER= -I".\Code\Core\Inc" -I".\Code\GENERAL"^
    +
    -I".\Code\Modbus" -I".\Code\PWM"
    +
    +
    :: Ð´Ð»Ñ Ð´Ð¾Ð±Ð°Ð²Ð»ÐµÐ½Ð¸Ñ Ð² переменую новых файлов. иначе будет перезапиÑÑŒ
    +
    setlocal enabledelayedexpansion
    +
    :: иÑходный код
    +
    set code_USER=
    +
    +
    for %%f in (.\Code\Core\Src\*.c) do (
    +
    set code_USER=!code_USER! %%f
    +
    )
    +
    +
    for %%f in (.\Code\GENERAL\*.c) do (
    +
    set code_USER=!code_USER! %%f
    +
    )
    +
    +
    for %%f in (.\Code\Modbus\*.c) do (
    +
    set code_USER=!code_USER! %%f
    +
    )
    +
    +
    for %%f in (.\Code\PWM\*.c) do (
    +
    set code_USER=!code_USER! %%f
    +
    )
    +
    ::-------------------------------------------------------------------------
    +
    +
    +
    :: -----------------------MCU LIBRARIES & SIMULATOR------------------------
    +
    :: -----MCU LIBRARIES STUFF----
    +
    :: заголовочные файлы
    +
    set includes_MCU= -I".\MCU_STM32F4xx_Matlab"^
    +
    -I".\MCU_STM32F4xx_Matlab\STM32F4xx_SIMULINK"^
    +
    -I".\MCU_STM32F4xx_Matlab\Drivers\CMSIS"^
    +
    -I".\MCU_STM32F4xx_Matlab\Drivers\STM32F4xx_HAL_Driver\Inc"^
    +
    -I".\MCU_STM32F4xx_Matlab\Drivers\STM32F4xx_HAL_Driver\Inc\Legacy"
    +
    +
    :: код библиотек МК, переделанный Ð´Ð»Ñ Ð¼Ð°Ñ‚Ð»Ð°Ð±
    +
    set code_MCU=.\MCU_STM32F4xx_Matlab\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_tim.c^
    +
    .\MCU_STM32F4xx_Matlab\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_tim_ex.c^
    +
    .\MCU_STM32F4xx_Matlab\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rcc.c^
    +
    .\MCU_STM32F4xx_Matlab\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_gpio.c^
    +
    .\MCU_STM32F4xx_Matlab\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_uart.c^
    +
    .\MCU_STM32F4xx_Matlab\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_usart.c^
    +
    .\MCU_STM32F4xx_Matlab\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dma.c^
    +
    .\MCU_STM32F4xx_Matlab\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_pwr.c^
    +
    .\MCU_STM32F4xx_Matlab\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_pwr_ex.c^
    +
    .\MCU_STM32F4xx_Matlab\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_cortex.c^
    +
    .\MCU_STM32F4xx_Matlab\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal.c^
    +
    .\MCU_STM32F4xx_Matlab\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_exti.c
    +
    +
    :: .\MCU_STM32F4xx_Matlab\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_flash_ramfunc.c^
    +
    :: .\MCU_STM32F4xx_Matlab\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_flash.c^
    +
    :: .\MCU_STM32F4xx_Matlab\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_flash_ex.c^
    +
    :: .\MCU_STM32F4xx_Matlab\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rcc_ex.c^
    +
    +
    :: --------MCU SIMULATOR-------
    +
    :: код, ÐºÐ¾Ñ‚Ð¾Ñ€Ð°Ñ Ð±ÑƒÐ´ÐµÑ‚ Ñимулировать перефирию МК в Ñимулинке
    +
    set code_MCU_Sim= .\MCU_STM32F4xx_Matlab\stm32f4xx_matlab_conf.c^
    +
    .\MCU_STM32F4xx_Matlab\STM32F4xx_SIMULINK\stm32f4xx_matlab_gpio.c^
    +
    .\MCU_STM32F4xx_Matlab\STM32F4xx_SIMULINK\stm32f4xx_matlab_tim.c^
    +
    .\MCU_STM32F4xx_Matlab\STM32F4xx_SIMULINK\stm32f4xx_periph_registers.c
    +
    ::-------------------------------------------------------------------------
    +
    +
    +
    :: -------------------------WRAPPER PATHS AND CODE---------------------------
    +
    :: оболочка, ÐºÐ¾Ñ‚Ð¾Ñ€Ð°Ñ Ð±ÑƒÐ´ÐµÑ‚ моделировать работу МК в Ñимулинке
    +
    set includes_WRAPPER= -I".\MCU_Wrapper"
    +
    set code_WRAPPER= .\MCU_Wrapper\MCU.c^
    +
    .\MCU_Wrapper\mcu_wrapper.c
    +
    ::-------------------------------------------------------------------------
    +
    +
    +
    :: ---------------------SET PARAMS FOR MEX COMPILING-----------------------
    +
    :: --------ALL INCLUDES--------
    +
    set includes= %includes_USER% %includes_MCU% %includes_WRAPPER%
    +
    set codes= %code_WRAPPER% %code_USER% %code_MCU% %code_MCU_Sim%
    +
    :: -------OUTPUT FOLDER--------
    +
    set output= -outdir "."
    +
    +
    :: еÑли нужен дебаг, до запуÑкаем run mex Ñ Ð¿Ñ€Ð¸Ð¿Ð¸Ñкой debug
    +
    IF [%1]==[debug] (set debug= -g)
    +
    ::-------------------------------------------------------------------------
    +
    +
    +
    ::------START COMPILING-------
    +
    echo Compiling...
    +
    mex %output% %defines% %includes% %codes% %debug%
    +
    +

    Definition in file run_mex.bat.

    +
    Generated by doxygen 1.10.0 diff --git a/DOCS/html/run__mex_8bat_source.html b/DOCS/html/run__mex_8bat_source.html new file mode 100644 index 0000000..1e7a3c5 --- /dev/null +++ b/DOCS/html/run__mex_8bat_source.html @@ -0,0 +1,186 @@ + + + + + + + +STM MATLAB Simulator: F:/Work/Projects/MATLAB/matlab_stm_emulate/MCU_Wrapper/run_mex.bat Source File + + + + + + + + + + + + +
    +
    + + + + + + +
    +
    STM MATLAB Simulator +
    +
    +
    + + + + + + + + + +
    +
    + + +
    +
    +
    +
    +
    +
    Loading...
    +
    Searching...
    +
    No Matches
    +
    +
    +
    +
    + + +
    +
    +
    run_mex.bat
    +
    +
    +Go to the documentation of this file.
    1@echo off
    +
    2
    +
    3set defines=-D"STM32F407xx" -D"USE_HAL_DRIVER"^
    +
    4 -D"MATLAB"^
    +
    5 -D"__sizeof_ptr=8"
    +
    6:: -------------------------USERS PATHS AND CODE---------------------------
    +
    7:: заголовочные файлы (не добавлÑÑ‚ÑŒ CMSIS и HAL, они добавлены ниже)
    +
    8set includes_USER= -I".\Code\Core\Inc" -I".\Code\GENERAL"^
    +
    9 -I".\Code\Modbus" -I".\Code\PWM"
    +
    10
    +
    11:: Ð´Ð»Ñ Ð´Ð¾Ð±Ð°Ð²Ð»ÐµÐ½Ð¸Ñ Ð² переменую новых файлов. иначе будет перезапиÑÑŒ
    +
    12setlocal enabledelayedexpansion
    +
    13:: иÑходный код
    +
    14set code_USER=
    +
    15
    +
    16for %%f in (.\Code\Core\Src\*.c) do (
    +
    17 set code_USER=!code_USER! %%f
    +
    18)
    +
    19
    +
    20for %%f in (.\Code\GENERAL\*.c) do (
    +
    21 set code_USER=!code_USER! %%f
    +
    22)
    +
    23
    +
    24for %%f in (.\Code\Modbus\*.c) do (
    +
    25 set code_USER=!code_USER! %%f
    +
    26)
    +
    27
    +
    28for %%f in (.\Code\PWM\*.c) do (
    +
    29 set code_USER=!code_USER! %%f
    +
    30)
    +
    31::-------------------------------------------------------------------------
    +
    32
    +
    33
    +
    34:: -----------------------MCU LIBRARIES & SIMULATOR------------------------
    +
    35:: -----MCU LIBRARIES STUFF----
    +
    36:: заголовочные файлы
    +
    37set includes_MCU= -I".\MCU_STM32F4xx_Matlab"^
    +
    38 -I".\MCU_STM32F4xx_Matlab\STM32F4xx_SIMULINK"^
    +
    39 -I".\MCU_STM32F4xx_Matlab\Drivers\CMSIS"^
    +
    40 -I".\MCU_STM32F4xx_Matlab\Drivers\STM32F4xx_HAL_Driver\Inc"^
    +
    41 -I".\MCU_STM32F4xx_Matlab\Drivers\STM32F4xx_HAL_Driver\Inc\Legacy"
    +
    42
    +
    43:: код библиотек МК, переделанный Ð´Ð»Ñ Ð¼Ð°Ñ‚Ð»Ð°Ð±
    +
    44set code_MCU=.\MCU_STM32F4xx_Matlab\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_tim.c^
    +
    45 .\MCU_STM32F4xx_Matlab\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_tim_ex.c^
    +
    46 .\MCU_STM32F4xx_Matlab\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rcc.c^
    +
    47 .\MCU_STM32F4xx_Matlab\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_gpio.c^
    +
    48 .\MCU_STM32F4xx_Matlab\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_uart.c^
    +
    49 .\MCU_STM32F4xx_Matlab\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_usart.c^
    +
    50 .\MCU_STM32F4xx_Matlab\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dma.c^
    +
    51 .\MCU_STM32F4xx_Matlab\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_pwr.c^
    +
    52 .\MCU_STM32F4xx_Matlab\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_pwr_ex.c^
    +
    53 .\MCU_STM32F4xx_Matlab\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_cortex.c^
    +
    54 .\MCU_STM32F4xx_Matlab\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal.c^
    +
    55 .\MCU_STM32F4xx_Matlab\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_exti.c
    +
    56
    +
    57:: .\MCU_STM32F4xx_Matlab\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_flash_ramfunc.c^
    +
    58:: .\MCU_STM32F4xx_Matlab\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_flash.c^
    +
    59:: .\MCU_STM32F4xx_Matlab\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_flash_ex.c^
    +
    60:: .\MCU_STM32F4xx_Matlab\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rcc_ex.c^
    +
    61
    +
    62:: --------MCU SIMULATOR-------
    +
    63:: код, ÐºÐ¾Ñ‚Ð¾Ñ€Ð°Ñ Ð±ÑƒÐ´ÐµÑ‚ Ñимулировать перефирию МК в Ñимулинке
    +
    64set code_MCU_Sim= .\MCU_STM32F4xx_Matlab\stm32f4xx_matlab_conf.c^
    +
    65 .\MCU_STM32F4xx_Matlab\STM32F4xx_SIMULINK\stm32f4xx_matlab_gpio.c^
    +
    66 .\MCU_STM32F4xx_Matlab\STM32F4xx_SIMULINK\stm32f4xx_matlab_tim.c^
    +
    67 .\MCU_STM32F4xx_Matlab\STM32F4xx_SIMULINK\stm32f4xx_periph_registers.c
    +
    68::-------------------------------------------------------------------------
    +
    69
    +
    70
    +
    71:: -------------------------WRAPPER PATHS AND CODE---------------------------
    +
    72:: оболочка, ÐºÐ¾Ñ‚Ð¾Ñ€Ð°Ñ Ð±ÑƒÐ´ÐµÑ‚ моделировать работу МК в Ñимулинке
    +
    73set includes_WRAPPER= -I".\MCU_Wrapper"
    +
    74set code_WRAPPER= .\MCU_Wrapper\MCU.c^
    +
    75 .\MCU_Wrapper\mcu_wrapper.c
    +
    76::-------------------------------------------------------------------------
    +
    77
    +
    78
    +
    79:: ---------------------SET PARAMS FOR MEX COMPILING-----------------------
    +
    80:: --------ALL INCLUDES--------
    +
    81set includes= %includes_USER% %includes_MCU% %includes_WRAPPER%
    +
    82set codes= %code_WRAPPER% %code_USER% %code_MCU% %code_MCU_Sim%
    +
    83:: -------OUTPUT FOLDER--------
    +
    84set output= -outdir "."
    +
    85
    +
    86:: еÑли нужен дебаг, до запуÑкаем run mex Ñ Ð¿Ñ€Ð¸Ð¿Ð¸Ñкой debug
    +
    87IF [%1]==[debug] (set debug= -g)
    +
    88::-------------------------------------------------------------------------
    +
    89
    +
    90
    +
    91::------START COMPILING-------
    +
    92echo Compiling...
    +
    93mex %output% %defines% %includes% %codes% %debug%
    +
    + +
    +Generated by doxygen 1.10.0 +
    + + diff --git a/DOCS/html/search/all_0.js b/DOCS/html/search/all_0.js index 99cafc3..0aa2249 100644 --- a/DOCS/html/search/all_0.js +++ b/DOCS/html/search/all_0.js @@ -1,93 +1,7 @@ var searchData= [ - ['_5f_5faligned_0',['__ALIGNED',['../arm__defines_8h.html#aa65ef8f7a5e8b7a6ea6c1d48b4c78e55',1,'arm_defines.h']]], - ['_5f_5farmclib_5fversion_1',['__ARMCLIB_VERSION',['../stdint_8h.html#a069d06d08ec1fd2e3bef945d23718106',1,'stdint.h']]], - ['_5f_5fasm_2',['__ASM',['../arm__defines_8h.html#a1378040bcf22428955c6e3ce9c2053cd',1,'arm_defines.h']]], - ['_5f_5fbkpt_3',['__BKPT',['../arm__defines_8h.html#a15ea6bd3c507d3e81c3b3a1258e46397',1,'arm_defines.h']]], - ['_5f_5fclibns_4',['__CLIBNS',['../stdint_8h.html#a49324e794e54deaab7cb5dc166780120',1,'stdint.h']]], - ['_5f_5fclrex_5',['__CLREX',['../arm__defines_8h.html#a7f7b66103530fadcce226375af3c2c03',1,'arm_defines.h']]], - ['_5f_5fclz_6',['__CLZ',['../arm__defines_8h.html#ad435395be5d5f9eaacba4c5441e62796',1,'arm_defines.h']]], - ['_5f_5fcm4_5frev_7',['__CM4_REV',['../group___configuration__section__for___c_m_s_i_s.html#ga45a97e4bb8b6ce7c334acc5f45ace3ba',1,'stm32f407xx_matlab.h']]], - ['_5f_5fdisable_5firq_8',['__disable_irq',['../arm__defines_8h.html#aff0484414d77b54006e638548b081d64',1,'arm_defines.h']]], - ['_5f_5fdmb_9',['__DMB',['../arm__defines_8h.html#a671101179b5943990785f36f8c1e2269',1,'arm_defines.h']]], - ['_5f_5fdsb_10',['__DSB',['../arm__defines_8h.html#a067d257a2b34565410acefb5afef2203',1,'arm_defines.h']]], - ['_5f_5ffpu_5fpresent_11',['__FPU_PRESENT',['../group___configuration__section__for___c_m_s_i_s.html#gac1ba8a48ca926bddc88be9bfd7d42641',1,'stm32f407xx_matlab.h']]], - ['_5f_5fi_12',['__I',['../core__cm4__matlab_8h.html#af63697ed9952cc71e1225efe205f6cd3',1,'core_cm4_matlab.h']]], - ['_5f_5fim_13',['__IM',['../core__cm4__matlab_8h.html#a4cc1649793116d7c2d8afce7a4ffce43',1,'core_cm4_matlab.h']]], - ['_5f_5finline_14',['__INLINE',['../arm__defines_8h.html#ade2d8d7118f8ff49547f60aa0c3382bb',1,'arm_defines.h']]], - ['_5f_5finline_15',['__inline',['../arm__defines_8h.html#a96deb7ba5a74848afb710cc4ee6d2c08',1,'arm_defines.h']]], - ['_5f_5fint64_16',['__INT64',['../stdint_8h.html#a151a46d8d0c3ff2df4c26eb0c3494fb5',1,'stdint.h']]], - ['_5f_5fint64_5fc_17',['__INT64_C',['../stdint_8h.html#aba0b23b9278a0f12ef402626eeebfa13',1,'stdint.h']]], - ['_5f_5fint64_5fc_5fsuffix_5f_5f_18',['__INT64_C_SUFFIX__',['../stdint_8h.html#a33c4c9f9f182bf7e8a0e57fd5f68a8fc',1,'stdint.h']]], - ['_5f_5fio_19',['__IO',['../arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be',1,'__IO: arm_defines.h'],['../core__cm4__matlab_8h.html#aec43007d9998a0a0e01faede4133d6be',1,'__IO: core_cm4_matlab.h']]], - ['_5f_5fiom_20',['__IOM',['../core__cm4__matlab_8h.html#ab6caba5853a60a17e8e04499b52bf691',1,'core_cm4_matlab.h']]], - ['_5f_5fisb_21',['__ISB',['../arm__defines_8h.html#aad233022e850a009fc6f7602be1182f6',1,'arm_defines.h']]], - ['_5f_5fldrexb_22',['__LDREXB',['../arm__defines_8h.html#a8876672c1f185d3253fea6b06bdba771',1,'arm_defines.h']]], - ['_5f_5fldrexh_23',['__LDREXH',['../arm__defines_8h.html#aa7f6f01cf534bc8daccc421dc823fc6f',1,'arm_defines.h']]], - ['_5f_5fldrexw_24',['__LDREXW',['../arm__defines_8h.html#aa872ae25197f1dddc52835fdfed9a881',1,'arm_defines.h']]], - ['_5f_5flonglong_25',['__LONGLONG',['../stdint_8h.html#af6b8bce81cb81cef5df097a396496a69',1,'stdint.h']]], - ['_5f_5fmpu_5fpresent_26',['__MPU_PRESENT',['../group___configuration__section__for___c_m_s_i_s.html#ga4127d1b31aaf336fab3d7329d117f448',1,'stm32f407xx_matlab.h']]], - ['_5f_5fno_5freturn_27',['__NO_RETURN',['../arm__defines_8h.html#a153a4a31b276a9758959580538720a51',1,'arm_defines.h']]], - ['_5f_5fnop_28',['__NOP',['../arm__defines_8h.html#a0b13f3617dd4af2cd2eb3a311073f717',1,'arm_defines.h']]], - ['_5f_5fnvic_5fclearpendingirq_29',['__NVIC_ClearPendingIRQ',['../group___c_m_s_i_s___core___n_v_i_c_functions.html#ga562a86dbdf14827d0fee8fdafb04d191',1,'core_cm4_matlab.h']]], - ['_5f_5fnvic_5fdisableirq_30',['__NVIC_DisableIRQ',['../group___c_m_s_i_s___core___n_v_i_c_functions.html#gae016e4c1986312044ee768806537d52f',1,'core_cm4_matlab.h']]], - ['_5f_5fnvic_5fenableirq_31',['__NVIC_EnableIRQ',['../group___c_m_s_i_s___core___n_v_i_c_functions.html#ga71227e1376cde11eda03fcb62f1b33ea',1,'core_cm4_matlab.h']]], - ['_5f_5fnvic_5fgetactive_32',['__NVIC_GetActive',['../group___c_m_s_i_s___core___n_v_i_c_functions.html#gaa2837003c28c45abf193fe5e8d27f593',1,'core_cm4_matlab.h']]], - ['_5f_5fnvic_5fgetenableirq_33',['__NVIC_GetEnableIRQ',['../group___c_m_s_i_s___core___n_v_i_c_functions.html#gaaeb5e7cc0eaad4e2817272e7bf742083',1,'core_cm4_matlab.h']]], - ['_5f_5fnvic_5fgetpendingirq_34',['__NVIC_GetPendingIRQ',['../group___c_m_s_i_s___core___n_v_i_c_functions.html#ga5a92ca5fa801ad7adb92be7257ab9694',1,'core_cm4_matlab.h']]], - ['_5f_5fnvic_5fgetpriority_35',['__NVIC_GetPriority',['../group___c_m_s_i_s___core___n_v_i_c_functions.html#gaeb9dc99c8e7700668813144261b0bc73',1,'core_cm4_matlab.h']]], - ['_5f_5fnvic_5fgetprioritygrouping_36',['__NVIC_GetPriorityGrouping',['../group___c_m_s_i_s___core___n_v_i_c_functions.html#ga9b894af672df4373eb637f8288845c05',1,'core_cm4_matlab.h']]], - ['_5f_5fnvic_5fgetvector_37',['__NVIC_GetVector',['../group___c_m_s_i_s___core___n_v_i_c_functions.html#ga44b665d2afb708121d9b10c76ff00ee5',1,'core_cm4_matlab.h']]], - ['_5f_5fnvic_5fprio_5fbits_38',['__NVIC_PRIO_BITS',['../group___configuration__section__for___c_m_s_i_s.html#gae3fe3587d5100c787e02102ce3944460',1,'stm32f407xx_matlab.h']]], - ['_5f_5fnvic_5fsetpendingirq_39',['__NVIC_SetPendingIRQ',['../group___c_m_s_i_s___core___n_v_i_c_functions.html#gaabefdd4b790b9a7308929938c0c1e1ad',1,'core_cm4_matlab.h']]], - ['_5f_5fnvic_5fsetpriority_40',['__NVIC_SetPriority',['../group___c_m_s_i_s___core___n_v_i_c_functions.html#ga505338e23563a9c074910fb14e7d45fd',1,'core_cm4_matlab.h']]], - ['_5f_5fnvic_5fsetprioritygrouping_41',['__NVIC_SetPriorityGrouping',['../group___c_m_s_i_s___core___n_v_i_c_functions.html#gafc94dcbaee03e4746ade1f5bb9aaa56d',1,'core_cm4_matlab.h']]], - ['_5f_5fnvic_5fsetvector_42',['__NVIC_SetVector',['../group___c_m_s_i_s___core___n_v_i_c_functions.html#ga0df355460bc1783d58f9d72ee4884208',1,'core_cm4_matlab.h']]], - ['_5f_5fnvic_5fsystemreset_43',['__NVIC_SystemReset',['../group___c_m_s_i_s___core___n_v_i_c_functions.html#ga0d9aa2d30fa54b41eb780c16e35b676c',1,'core_cm4_matlab.h']]], - ['_5f_5fo_44',['__O',['../core__cm4__matlab_8h.html#a7e25d9380f9ef903923964322e71f2f6',1,'core_cm4_matlab.h']]], - ['_5f_5fom_45',['__OM',['../core__cm4__matlab_8h.html#a0ea2009ed8fd9ef35b48708280fdb758',1,'core_cm4_matlab.h']]], - ['_5f_5fpacked_46',['__PACKED',['../arm__defines_8h.html#abe8996d3d985ee1529475443cc635bf1',1,'arm_defines.h']]], - ['_5f_5fpacked_5fstruct_47',['__PACKED_STRUCT',['../arm__defines_8h.html#a4dbb70fab85207c27b581ecb6532b314',1,'arm_defines.h']]], - ['_5f_5fpacked_5funion_48',['__PACKED_UNION',['../arm__defines_8h.html#a6fba34d08b0a526830b4231d2ea0b89a',1,'arm_defines.h']]], - ['_5f_5fpaste_49',['__PASTE',['../stdint_8h.html#ac3ae5768889bec57a63f08b6a6e5f58d',1,'stdint.h']]], - ['_5f_5fpaste2_50',['__PASTE2',['../stdint_8h.html#a9a494f36bdb6e7a465eecff7fc6c2a31',1,'stdint.h']]], - ['_5f_5frbit_51',['__RBIT',['../arm__defines_8h.html#a3a468db3bc52465a88269bfb34e675a7',1,'arm_defines.h']]], - ['_5f_5frestrict_52',['__RESTRICT',['../arm__defines_8h.html#a378ac21329d33f561f90265eef89f564',1,'arm_defines.h']]], - ['_5f_5frev_53',['__REV',['../arm__defines_8h.html#aca25a02e09983da5558f5242f2f635bc',1,'arm_defines.h']]], - ['_5f_5frev16_54',['__REV16',['../arm__defines_8h.html#ad35497777af37e7809271b5e6f9510ba',1,'arm_defines.h']]], - ['_5f_5frevsh_55',['__REVSH',['../arm__defines_8h.html#ae580812686119c9c5cf3c11a7519a404',1,'arm_defines.h']]], - ['_5f_5fror_56',['__ROR',['../arm__defines_8h.html#a27ffb10344b90805b21307493c319cb4',1,'arm_defines.h']]], - ['_5f_5fsev_57',['__SEV',['../arm__defines_8h.html#afa58e60fcd2176ad58f96947466ea1fa',1,'arm_defines.h']]], - ['_5f_5fssat_58',['__SSAT',['../arm__defines_8h.html#a3c013c2ed76ebc48c283c8bae17b9ab8',1,'arm_defines.h']]], - ['_5f_5fstatic_5fforceinline_59',['__STATIC_FORCEINLINE',['../arm__defines_8h.html#ab904513442afdf77d4f8c74f23cbb040',1,'arm_defines.h']]], - ['_5f_5fstatic_5finline_60',['__STATIC_INLINE',['../arm__defines_8h.html#aba87361bfad2ae52cfe2f40c1a1dbf9c',1,'arm_defines.h']]], - ['_5f_5fstdint_5fdecls_61',['__STDINT_DECLS',['../stdint_8h.html#a60a7be5011232f989fededd98181467b',1,'stdint.h']]], - ['_5f_5fstm32f4xx_5fcmsis_5fversion_62',['__STM32F4xx_CMSIS_VERSION',['../group___library__configuration__section.html#ga9e8a65cc42b85335938665a12c37cacf',1,'stm32f4xx.h']]], - ['_5f_5fstm32f4xx_5fcmsis_5fversion_5fmain_63',['__STM32F4xx_CMSIS_VERSION_MAIN',['../group___library__configuration__section.html#gaf867da11218022a14245b854f6be6a40',1,'stm32f4xx.h']]], - ['_5f_5fstm32f4xx_5fcmsis_5fversion_5frc_64',['__STM32F4xx_CMSIS_VERSION_RC',['../group___library__configuration__section.html#gafbd304f122892833ce0d4daa3dc4ff13',1,'stm32f4xx.h']]], - ['_5f_5fstm32f4xx_5fcmsis_5fversion_5fsub1_65',['__STM32F4xx_CMSIS_VERSION_SUB1',['../group___library__configuration__section.html#ga4841e20bc5159a594936808c113ae3bc',1,'stm32f4xx.h']]], - ['_5f_5fstm32f4xx_5fcmsis_5fversion_5fsub2_66',['__STM32F4xx_CMSIS_VERSION_SUB2',['../group___library__configuration__section.html#ga6ccbf6336bfb67bf4daeb05eba18a5e3',1,'stm32f4xx.h']]], - ['_5f_5fstrexb_67',['__STREXB',['../arm__defines_8h.html#a503ba30a93e83963de38e5171fbbabce',1,'arm_defines.h']]], - ['_5f_5fstrexh_68',['__STREXH',['../arm__defines_8h.html#a63d19c6c7852ada9a1c1aab80e6294b1',1,'arm_defines.h']]], - ['_5f_5fstrexw_69',['__STREXW',['../arm__defines_8h.html#a0c3704e33e90ba0491cee56cfb553090',1,'arm_defines.h']]], - ['_5f_5fuint64_5fc_70',['__UINT64_C',['../stdint_8h.html#a3b5e01fc50cf47627f362b514e5ca9dd',1,'stdint.h']]], - ['_5f_5funaligned_5fuint16_5fread_71',['__UNALIGNED_UINT16_READ',['../arm__defines_8h.html#ab71b66e5ce403158d3dee62a59f9175f',1,'arm_defines.h']]], - ['_5f_5funaligned_5fuint16_5fwrite_72',['__UNALIGNED_UINT16_WRITE',['../arm__defines_8h.html#a5103fb373cae9837cc4a384be55dc87f',1,'arm_defines.h']]], - ['_5f_5funaligned_5fuint32_73',['__UNALIGNED_UINT32',['../arm__defines_8h.html#ac8a13aacd0453758fdfd01a57a2a6a3d',1,'arm_defines.h']]], - ['_5f_5funaligned_5fuint32_5fread_74',['__UNALIGNED_UINT32_READ',['../arm__defines_8h.html#a3b931f0b051b8c1a6377a3dcc7559b5e',1,'arm_defines.h']]], - ['_5f_5funaligned_5fuint32_5fwrite_75',['__UNALIGNED_UINT32_WRITE',['../arm__defines_8h.html#a203f593d140ed88b81bc189edc861110',1,'arm_defines.h']]], - ['_5f_5fusat_76',['__USAT',['../arm__defines_8h.html#ad0e4fa951d563740462d837bb6ddd7bb',1,'arm_defines.h']]], - ['_5f_5fused_77',['__USED',['../arm__defines_8h.html#a3e40e4c553fc11588f7a4c2a19e789e0',1,'arm_defines.h']]], - ['_5f_5fvendor_5fsystickconfig_78',['__Vendor_SysTickConfig',['../group___configuration__section__for___c_m_s_i_s.html#gab58771b4ec03f9bdddc84770f7c95c68',1,'stm32f407xx_matlab.h']]], - ['_5f_5fweak_79',['__WEAK',['../arm__defines_8h.html#ac607bf387b29162be6a9b77fc7999539',1,'arm_defines.h']]], - ['_5f_5fwfe_80',['__WFE',['../arm__defines_8h.html#af0330712223f4cfb6091e4ab84775f73',1,'arm_defines.h']]], - ['_5f_5fwfi_81',['__WFI',['../arm__defines_8h.html#ab28e2b328c4cf23c917ab18a23194f8e',1,'arm_defines.h']]], - ['_5fcortex_5fmemory_82',['_cortex_memory',['../struct__cortex__memory.html',1,'']]], - ['_5ffld2val_83',['_FLD2VAL',['../group___c_m_s_i_s__core__bitfield.html#ga139b6e261c981f014f386927ca4a8444',1,'core_cm4_matlab.h']]], - ['_5fmemory_84',['_memory',['../struct__memory.html',1,'']]], - ['_5frcc_5fclear_5fflag_85',['_RCC_CLEAR_FLAG',['../group___r_c_c___s_i_m_u_l_a_t_o_r.html#gafedee1520e942548e0b8818122ecef97',1,'stm32f4xx_matlab_rcc.h']]], - ['_5frcc_5fset_5fflag_86',['_RCC_SET_FLAG',['../group___r_c_c___s_i_m_u_l_a_t_o_r.html#gae06dd862c75ec6de931ae3c350d61325',1,'stm32f4xx_matlab_rcc.h']]], - ['_5freserved0_87',['_reserved0',['../group___c_m_s_i_s__core___debug_functions.html#gac8a6a13838a897c8d0b8bc991bbaf7c1',1,'APSR_Type::_reserved0'],['../group___c_m_s_i_s__core___debug_functions.html#gac8a6a13838a897c8d0b8bc991bbaf7c1',1,'APSR_Type::@0::_reserved0'],['../group___c_m_s_i_s__core___debug_functions.html#gac8a6a13838a897c8d0b8bc991bbaf7c1',1,'IPSR_Type::_reserved0'],['../group___c_m_s_i_s__core___debug_functions.html#gac8a6a13838a897c8d0b8bc991bbaf7c1',1,'IPSR_Type::@1::_reserved0'],['../group___c_m_s_i_s__core___debug_functions.html#gac8a6a13838a897c8d0b8bc991bbaf7c1',1,'xPSR_Type::_reserved0'],['../group___c_m_s_i_s__core___debug_functions.html#gac8a6a13838a897c8d0b8bc991bbaf7c1',1,'xPSR_Type::@2::_reserved0'],['../group___c_m_s_i_s__core___debug_functions.html#gac8a6a13838a897c8d0b8bc991bbaf7c1',1,'CONTROL_Type::_reserved0'],['../group___c_m_s_i_s__core___debug_functions.html#gac8a6a13838a897c8d0b8bc991bbaf7c1',1,'CONTROL_Type::@3::_reserved0']]], - ['_5freserved1_88',['_reserved1',['../group___c_m_s_i_s__core___debug_functions.html#ga959a73d8faee56599b7e792a7c5a2d16',1,'APSR_Type::_reserved1'],['../group___c_m_s_i_s__core___debug_functions.html#ga959a73d8faee56599b7e792a7c5a2d16',1,'APSR_Type::@0::_reserved1'],['../group___c_m_s_i_s__core___debug_functions.html#ga959a73d8faee56599b7e792a7c5a2d16',1,'xPSR_Type::_reserved1'],['../group___c_m_s_i_s__core___debug_functions.html#ga959a73d8faee56599b7e792a7c5a2d16',1,'xPSR_Type::@2::_reserved1']]], - ['_5fval2fld_89',['_VAL2FLD',['../group___c_m_s_i_s__core__bitfield.html#ga286e3b913dbd236c7f48ea70c8821f4e',1,'core_cm4_matlab.h']]] + ['_5fcortex_5fmemory_0',['_cortex_memory',['../struct__cortex__memory.html',1,'']]], + ['_5fmemory_1',['_memory',['../struct__memory.html',1,'']]], + ['_5frcc_5fclear_5fflag_2',['_RCC_CLEAR_FLAG',['../group___r_c_c___s_i_m_u_l_a_t_o_r.html#gafedee1520e942548e0b8818122ecef97',1,'stm32f4xx_matlab_rcc.h']]], + ['_5frcc_5fset_5fflag_3',['_RCC_SET_FLAG',['../group___r_c_c___s_i_m_u_l_a_t_o_r.html#gae06dd862c75ec6de931ae3c350d61325',1,'stm32f4xx_matlab_rcc.h']]] ]; diff --git a/DOCS/html/search/all_1.js b/DOCS/html/search/all_1.js index bfd7609..4715e43 100644 --- a/DOCS/html/search/all_1.js +++ b/DOCS/html/search/all_1.js @@ -4,622 +4,9 @@ var searchData= ['abp1_5fvalue_1',['ABP1_Value',['../group___r_c_c___s_i_m_u_l_a_t_o_r.html#gabce7fd8ef9ea39fb4f77b5a0016338ea',1,'stm32f4xx_matlab_rcc.h']]], ['abp2_5ftims_5fvalue_2',['ABP2_TIMS_Value',['../group___r_c_c___s_i_m_u_l_a_t_o_r.html#gab8af0c48743a9c568167d7d99c377861',1,'stm32f4xx_matlab_rcc.h']]], ['abp2_5fvalue_3',['ABP2_Value',['../group___r_c_c___s_i_m_u_l_a_t_o_r.html#ga142081f515cc585408786f7745733ef5',1,'stm32f4xx_matlab_rcc.h']]], - ['acpr_4',['ACPR',['../group___c_m_s_i_s__core___debug_functions.html#ga49a770cf0b7ec970f919f8ac22634fff',1,'TPI_Type']]], - ['acr_5',['ACR',['../group___c_m_s_i_s___device.html#ga9cb55206b29a8c16354747c556ab8bea',1,'FLASH_TypeDef']]], - ['actlr_6',['ACTLR',['../group___c_m_s_i_s__core___debug_functions.html#gafabed911b9f91f9df848999e1b5d6504',1,'SCnSCB_Type']]], - ['adc_7',['adc',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#gac69e5457edf5f5639c4532688de406ae',1,'stm32f4xx_periph_registers.c']]], - ['adc_8',['ADC',['../group___peripheral__declaration.html#ga54d148b91f3d356713f7e367a2243bea',1,'stm32f407xx_matlab.h']]], - ['adc1_9',['adc1',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#gaf1cc5fa4068a793827866bc4be7e3799',1,'stm32f4xx_periph_registers.c']]], - ['adc1_10',['ADC1',['../group___peripheral__declaration.html#ga90d2d5c526ce5c0a551f533eccbee71a',1,'stm32f407xx_matlab.h']]], - ['adc123_5fcommon_11',['adc123_common',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#gad98be8090528df1e3edb79ec46438b0a',1,'stm32f4xx_periph_registers.c']]], - ['adc123_5fcommon_12',['ADC123_COMMON',['../group___peripheral__declaration.html#ga813de18391e45c0854aafd470c2d547f',1,'stm32f407xx_matlab.h']]], - ['adc123_5fcommon_5fbase_13',['ADC123_COMMON_BASE',['../group___peripheral__memory__map.html#ga58b9980508ab28022e3be7edc4eda72e',1,'stm32f407xx_matlab.h']]], - ['adc1_5fbase_14',['ADC1_BASE',['../group___peripheral__memory__map.html#ga695c9a2f892363a1c942405c8d351b91',1,'stm32f407xx_matlab.h']]], - ['adc2_15',['ADC2',['../group___peripheral__declaration.html#gac5503ae96c26b4475226f96715a1bf1e',1,'stm32f407xx_matlab.h']]], - ['adc2_16',['adc2',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#gaa94271247e5f041f9097ef16d6450c68',1,'stm32f4xx_periph_registers.c']]], - ['adc2_5fbase_17',['ADC2_BASE',['../group___peripheral__memory__map.html#ga6544abc57f9759f610eee09a02442ae6',1,'stm32f407xx_matlab.h']]], - ['adc3_18',['adc3',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga6f330240512375fb7e4e23ba73e4b612',1,'stm32f4xx_periph_registers.c']]], - ['adc3_19',['ADC3',['../group___peripheral__declaration.html#gae917784606daf6b04c9b7b96b40c2f74',1,'stm32f407xx_matlab.h']]], - ['adc3_5fbase_20',['ADC3_BASE',['../group___peripheral__memory__map.html#gaca766f86c8e0b00a8e2b0224dcbb4c82',1,'stm32f407xx_matlab.h']]], - ['adc_5fbase_21',['ADC_BASE',['../group___peripheral__memory__map.html#gad06cb9e5985bd216a376f26f22303cd6',1,'stm32f407xx_matlab.h']]], - ['adc_5fccr_5fadcpre_22',['ADC_CCR_ADCPRE',['../group___peripheral___registers___bits___definition.html#ga3a2ee019aef4c64fffc72141f7aaab2c',1,'stm32f407xx_matlab.h']]], - ['adc_5fccr_5fadcpre_5f0_23',['ADC_CCR_ADCPRE_0',['../group___peripheral___registers___bits___definition.html#gaf3108cc8fb81f6efd1e93fa5f82ac313',1,'stm32f407xx_matlab.h']]], - ['adc_5fccr_5fadcpre_5f1_24',['ADC_CCR_ADCPRE_1',['../group___peripheral___registers___bits___definition.html#gafa090830d2d359db04f365d46c6644d5',1,'stm32f407xx_matlab.h']]], - ['adc_5fccr_5fadcpre_5fmsk_25',['ADC_CCR_ADCPRE_Msk',['../group___peripheral___registers___bits___definition.html#ga2458ab94917987a44a275e1ed886e825',1,'stm32f407xx_matlab.h']]], - ['adc_5fccr_5fadcpre_5fpos_26',['ADC_CCR_ADCPRE_Pos',['../group___peripheral___registers___bits___definition.html#gafceea99dc2287c360b275732f9862bca',1,'stm32f407xx_matlab.h']]], - ['adc_5fccr_5fdds_27',['ADC_CCR_DDS',['../group___peripheral___registers___bits___definition.html#ga7e745513bbc2e5e5a76ae999d5d535af',1,'stm32f407xx_matlab.h']]], - ['adc_5fccr_5fdds_5fmsk_28',['ADC_CCR_DDS_Msk',['../group___peripheral___registers___bits___definition.html#gad41720d885d32a33cb04782a2a2a74f9',1,'stm32f407xx_matlab.h']]], - ['adc_5fccr_5fdds_5fpos_29',['ADC_CCR_DDS_Pos',['../group___peripheral___registers___bits___definition.html#ga27c6d297e452d728c075a6f9b953d0a5',1,'stm32f407xx_matlab.h']]], - ['adc_5fccr_5fdelay_30',['ADC_CCR_DELAY',['../group___peripheral___registers___bits___definition.html#ga9c13aa04949ed520cf92613d3a619198',1,'stm32f407xx_matlab.h']]], - ['adc_5fccr_5fdelay_5f0_31',['ADC_CCR_DELAY_0',['../group___peripheral___registers___bits___definition.html#ga22b71e9df8b1fca93802ad602341eb0b',1,'stm32f407xx_matlab.h']]], - ['adc_5fccr_5fdelay_5f1_32',['ADC_CCR_DELAY_1',['../group___peripheral___registers___bits___definition.html#ga6d0d5785cb6c75e700517e88af188573',1,'stm32f407xx_matlab.h']]], - ['adc_5fccr_5fdelay_5f2_33',['ADC_CCR_DELAY_2',['../group___peripheral___registers___bits___definition.html#ga17f85cbda5dcf9a392a29befb73c6ceb',1,'stm32f407xx_matlab.h']]], - ['adc_5fccr_5fdelay_5f3_34',['ADC_CCR_DELAY_3',['../group___peripheral___registers___bits___definition.html#gae0216de7d6fcfa507c9aa1400972d862',1,'stm32f407xx_matlab.h']]], - ['adc_5fccr_5fdelay_5fmsk_35',['ADC_CCR_DELAY_Msk',['../group___peripheral___registers___bits___definition.html#ga7c1c63139684661c857ece4937a72415',1,'stm32f407xx_matlab.h']]], - ['adc_5fccr_5fdelay_5fpos_36',['ADC_CCR_DELAY_Pos',['../group___peripheral___registers___bits___definition.html#ga702c581a6341f08b3198cd41b0cb69a3',1,'stm32f407xx_matlab.h']]], - ['adc_5fccr_5fdma_37',['ADC_CCR_DMA',['../group___peripheral___registers___bits___definition.html#ga9e346b21afcaeced784e6c80b3aa1fb4',1,'stm32f407xx_matlab.h']]], - ['adc_5fccr_5fdma_5f0_38',['ADC_CCR_DMA_0',['../group___peripheral___registers___bits___definition.html#ga3a42ee6ec5115244aef8f60d35abcc47',1,'stm32f407xx_matlab.h']]], - ['adc_5fccr_5fdma_5f1_39',['ADC_CCR_DMA_1',['../group___peripheral___registers___bits___definition.html#gacdc9d29cafdd54e5c0dd752c358e1bc8',1,'stm32f407xx_matlab.h']]], - ['adc_5fccr_5fdma_5fmsk_40',['ADC_CCR_DMA_Msk',['../group___peripheral___registers___bits___definition.html#gab7933afb88d395724816248ec8fa9b76',1,'stm32f407xx_matlab.h']]], - ['adc_5fccr_5fdma_5fpos_41',['ADC_CCR_DMA_Pos',['../group___peripheral___registers___bits___definition.html#ga2cdf117dd6f678b5d2121253b4e452c6',1,'stm32f407xx_matlab.h']]], - ['adc_5fccr_5fmulti_42',['ADC_CCR_MULTI',['../group___peripheral___registers___bits___definition.html#gaf70ab04667c7c7da0f29c0e5a6c48e68',1,'stm32f407xx_matlab.h']]], - ['adc_5fccr_5fmulti_5f0_43',['ADC_CCR_MULTI_0',['../group___peripheral___registers___bits___definition.html#gae4e7104ce01e3a79b8f6138d87dc3684',1,'stm32f407xx_matlab.h']]], - ['adc_5fccr_5fmulti_5f1_44',['ADC_CCR_MULTI_1',['../group___peripheral___registers___bits___definition.html#ga8781dec7f076b475b85f8470aee94d06',1,'stm32f407xx_matlab.h']]], - ['adc_5fccr_5fmulti_5f2_45',['ADC_CCR_MULTI_2',['../group___peripheral___registers___bits___definition.html#gae6a5be6cff1227431b8d54dffcc1ce88',1,'stm32f407xx_matlab.h']]], - ['adc_5fccr_5fmulti_5f3_46',['ADC_CCR_MULTI_3',['../group___peripheral___registers___bits___definition.html#gae55be7b911b4c0272543f98a0dba5f20',1,'stm32f407xx_matlab.h']]], - ['adc_5fccr_5fmulti_5f4_47',['ADC_CCR_MULTI_4',['../group___peripheral___registers___bits___definition.html#ga5087b3cb0d4570b80b3138c277bcbf6c',1,'stm32f407xx_matlab.h']]], - ['adc_5fccr_5fmulti_5fmsk_48',['ADC_CCR_MULTI_Msk',['../group___peripheral___registers___bits___definition.html#ga535eaa79d3a77403b2e0981641f10f81',1,'stm32f407xx_matlab.h']]], - ['adc_5fccr_5fmulti_5fpos_49',['ADC_CCR_MULTI_Pos',['../group___peripheral___registers___bits___definition.html#ga9f9e95bcdc01cb070e8b42441839b517',1,'stm32f407xx_matlab.h']]], - ['adc_5fccr_5ftsvrefe_50',['ADC_CCR_TSVREFE',['../group___peripheral___registers___bits___definition.html#gafc020d85a8740491ce3f218a0706f1dc',1,'stm32f407xx_matlab.h']]], - ['adc_5fccr_5ftsvrefe_5fmsk_51',['ADC_CCR_TSVREFE_Msk',['../group___peripheral___registers___bits___definition.html#ga5e1a3df0d33a0c78197ad8c161c22a7a',1,'stm32f407xx_matlab.h']]], - ['adc_5fccr_5ftsvrefe_5fpos_52',['ADC_CCR_TSVREFE_Pos',['../group___peripheral___registers___bits___definition.html#ga9741df391649af046f8310352ca3b3be',1,'stm32f407xx_matlab.h']]], - ['adc_5fccr_5fvbate_53',['ADC_CCR_VBATE',['../group___peripheral___registers___bits___definition.html#ga519645e42dcf6b19af9c05dc40300abb',1,'stm32f407xx_matlab.h']]], - ['adc_5fccr_5fvbate_5fmsk_54',['ADC_CCR_VBATE_Msk',['../group___peripheral___registers___bits___definition.html#gac3d86d837c7c40d14882728116a3722b',1,'stm32f407xx_matlab.h']]], - ['adc_5fccr_5fvbate_5fpos_55',['ADC_CCR_VBATE_Pos',['../group___peripheral___registers___bits___definition.html#ga8ece9c9847db39ff9782d07ed5104bbf',1,'stm32f407xx_matlab.h']]], - ['adc_5fcdr_5fdata1_56',['ADC_CDR_DATA1',['../group___peripheral___registers___bits___definition.html#ga6d7a0a18c77816c45c5682c3884e3d56',1,'stm32f407xx_matlab.h']]], - ['adc_5fcdr_5fdata1_5fmsk_57',['ADC_CDR_DATA1_Msk',['../group___peripheral___registers___bits___definition.html#gadb4c80caea7b29ec5b2b863e84288cf1',1,'stm32f407xx_matlab.h']]], - ['adc_5fcdr_5fdata1_5fpos_58',['ADC_CDR_DATA1_Pos',['../group___peripheral___registers___bits___definition.html#gaa14929dd3fe8ae466d2ad41c395ca2c1',1,'stm32f407xx_matlab.h']]], - ['adc_5fcdr_5fdata2_59',['ADC_CDR_DATA2',['../group___peripheral___registers___bits___definition.html#ga55f0776b9bf2612c194c1ab478d8a371',1,'stm32f407xx_matlab.h']]], - ['adc_5fcdr_5fdata2_5fmsk_60',['ADC_CDR_DATA2_Msk',['../group___peripheral___registers___bits___definition.html#ga2e8ac90ba8958b4d858c24e2896f7733',1,'stm32f407xx_matlab.h']]], - ['adc_5fcdr_5fdata2_5fpos_61',['ADC_CDR_DATA2_Pos',['../group___peripheral___registers___bits___definition.html#gab562b2adbf577b621d81758fa806e5fc',1,'stm32f407xx_matlab.h']]], - ['adc_5fcdr_5frdata_5fmst_62',['ADC_CDR_RDATA_MST',['../group___peripheral___registers___bits___definition.html#ga588fd6c0f172ca0e7683bb54034564fe',1,'stm32f407xx_matlab.h']]], - ['adc_5fcdr_5frdata_5fslv_63',['ADC_CDR_RDATA_SLV',['../group___peripheral___registers___bits___definition.html#gad582026e4b62991d8281b51494902a33',1,'stm32f407xx_matlab.h']]], - ['adc_5fcommon_5ftypedef_64',['ADC_Common_TypeDef',['../struct_a_d_c___common___type_def.html',1,'']]], - ['adc_5fcr1_5fawdch_65',['ADC_CR1_AWDCH',['../group___peripheral___registers___bits___definition.html#gad8bb755c7059bb2d4f5e2e999d2a2677',1,'stm32f407xx_matlab.h']]], - ['adc_5fcr1_5fawdch_5f0_66',['ADC_CR1_AWDCH_0',['../group___peripheral___registers___bits___definition.html#ga18725d77c35c173cdb5bdab658d9dace',1,'stm32f407xx_matlab.h']]], - ['adc_5fcr1_5fawdch_5f1_67',['ADC_CR1_AWDCH_1',['../group___peripheral___registers___bits___definition.html#gafcd37244d74db7c9a34a4f08b94301ae',1,'stm32f407xx_matlab.h']]], - ['adc_5fcr1_5fawdch_5f2_68',['ADC_CR1_AWDCH_2',['../group___peripheral___registers___bits___definition.html#ga625eebdc95937325cad90a151853f5a0',1,'stm32f407xx_matlab.h']]], - ['adc_5fcr1_5fawdch_5f3_69',['ADC_CR1_AWDCH_3',['../group___peripheral___registers___bits___definition.html#gafb768d4aafbabc114d4650cf962392ec',1,'stm32f407xx_matlab.h']]], - ['adc_5fcr1_5fawdch_5f4_70',['ADC_CR1_AWDCH_4',['../group___peripheral___registers___bits___definition.html#gaf37f3c0d7c72192803d0772e076cf8ee',1,'stm32f407xx_matlab.h']]], - ['adc_5fcr1_5fawdch_5fmsk_71',['ADC_CR1_AWDCH_Msk',['../group___peripheral___registers___bits___definition.html#ga0cc3a347eb0150e7f476f67df64e2276',1,'stm32f407xx_matlab.h']]], - ['adc_5fcr1_5fawdch_5fpos_72',['ADC_CR1_AWDCH_Pos',['../group___peripheral___registers___bits___definition.html#ga593a52bc26648e0eceef061f5a8c32e0',1,'stm32f407xx_matlab.h']]], - ['adc_5fcr1_5fawden_73',['ADC_CR1_AWDEN',['../group___peripheral___registers___bits___definition.html#ga6e006d43fcb9fe1306745c95a1bdd651',1,'stm32f407xx_matlab.h']]], - ['adc_5fcr1_5fawden_5fmsk_74',['ADC_CR1_AWDEN_Msk',['../group___peripheral___registers___bits___definition.html#ga815cfd0e3ad3eed4424caf312550da16',1,'stm32f407xx_matlab.h']]], - ['adc_5fcr1_5fawden_5fpos_75',['ADC_CR1_AWDEN_Pos',['../group___peripheral___registers___bits___definition.html#gaf4078327f9219b87d0627ad53f27e25a',1,'stm32f407xx_matlab.h']]], - ['adc_5fcr1_5fawdie_76',['ADC_CR1_AWDIE',['../group___peripheral___registers___bits___definition.html#gacd44f86b189696d5a3780342516de722',1,'stm32f407xx_matlab.h']]], - ['adc_5fcr1_5fawdie_5fmsk_77',['ADC_CR1_AWDIE_Msk',['../group___peripheral___registers___bits___definition.html#ga34c5eb25f1b9dc807fabc06c90fe9df6',1,'stm32f407xx_matlab.h']]], - ['adc_5fcr1_5fawdie_5fpos_78',['ADC_CR1_AWDIE_Pos',['../group___peripheral___registers___bits___definition.html#ga553aa50487015ce07880bd3c62887698',1,'stm32f407xx_matlab.h']]], - ['adc_5fcr1_5fawdsgl_79',['ADC_CR1_AWDSGL',['../group___peripheral___registers___bits___definition.html#ga5c9fc31f19c04033dfa98e982519c451',1,'stm32f407xx_matlab.h']]], - ['adc_5fcr1_5fawdsgl_5fmsk_80',['ADC_CR1_AWDSGL_Msk',['../group___peripheral___registers___bits___definition.html#ga2a58382bba04769e4baef8f36390f648',1,'stm32f407xx_matlab.h']]], - ['adc_5fcr1_5fawdsgl_5fpos_81',['ADC_CR1_AWDSGL_Pos',['../group___peripheral___registers___bits___definition.html#ga1cc219fd4025d88bd77dfb2824e4a42b',1,'stm32f407xx_matlab.h']]], - ['adc_5fcr1_5fdiscen_82',['ADC_CR1_DISCEN',['../group___peripheral___registers___bits___definition.html#gabd690297fc73fca40d797f4c90800b9a',1,'stm32f407xx_matlab.h']]], - ['adc_5fcr1_5fdiscen_5fmsk_83',['ADC_CR1_DISCEN_Msk',['../group___peripheral___registers___bits___definition.html#gad69e1c5ba0421fe9b33109a3789be1a5',1,'stm32f407xx_matlab.h']]], - ['adc_5fcr1_5fdiscen_5fpos_84',['ADC_CR1_DISCEN_Pos',['../group___peripheral___registers___bits___definition.html#ga394271f323587db3ea21731046b69004',1,'stm32f407xx_matlab.h']]], - ['adc_5fcr1_5fdiscnum_85',['ADC_CR1_DISCNUM',['../group___peripheral___registers___bits___definition.html#gaeaa416a291023449ae82e7ef39844075',1,'stm32f407xx_matlab.h']]], - ['adc_5fcr1_5fdiscnum_5f0_86',['ADC_CR1_DISCNUM_0',['../group___peripheral___registers___bits___definition.html#ga59ff81db7def261f0e84d5dbb6cca1ce',1,'stm32f407xx_matlab.h']]], - ['adc_5fcr1_5fdiscnum_5f1_87',['ADC_CR1_DISCNUM_1',['../group___peripheral___registers___bits___definition.html#ga39940d3611126052f4f748934c629ebf',1,'stm32f407xx_matlab.h']]], - ['adc_5fcr1_5fdiscnum_5f2_88',['ADC_CR1_DISCNUM_2',['../group___peripheral___registers___bits___definition.html#gab73d5fdf276f5ef3965afdda78ac9e1e',1,'stm32f407xx_matlab.h']]], - ['adc_5fcr1_5fdiscnum_5fmsk_89',['ADC_CR1_DISCNUM_Msk',['../group___peripheral___registers___bits___definition.html#gafee42b4ef0f4cb5b0ab45fc78f3e27f9',1,'stm32f407xx_matlab.h']]], - ['adc_5fcr1_5fdiscnum_5fpos_90',['ADC_CR1_DISCNUM_Pos',['../group___peripheral___registers___bits___definition.html#ga418d84715b6f383cea1ca241d0c76194',1,'stm32f407xx_matlab.h']]], - ['adc_5fcr1_5feocie_91',['ADC_CR1_EOCIE',['../group___peripheral___registers___bits___definition.html#gaa39fee2e812a7ca45998cccf32e90aea',1,'stm32f407xx_matlab.h']]], - ['adc_5fcr1_5feocie_5fmsk_92',['ADC_CR1_EOCIE_Msk',['../group___peripheral___registers___bits___definition.html#ga4cb8db4061b4ebb927dbf6bef84e9ae0',1,'stm32f407xx_matlab.h']]], - ['adc_5fcr1_5feocie_5fpos_93',['ADC_CR1_EOCIE_Pos',['../group___peripheral___registers___bits___definition.html#gac14738c525ee769e8971601f631ef594',1,'stm32f407xx_matlab.h']]], - ['adc_5fcr1_5fjauto_94',['ADC_CR1_JAUTO',['../group___peripheral___registers___bits___definition.html#ga6353cb0d564410358b3a086dd0241f8c',1,'stm32f407xx_matlab.h']]], - ['adc_5fcr1_5fjauto_5fmsk_95',['ADC_CR1_JAUTO_Msk',['../group___peripheral___registers___bits___definition.html#ga7cfa0d38cd6dfd5ed09673558ccadacf',1,'stm32f407xx_matlab.h']]], - ['adc_5fcr1_5fjauto_5fpos_96',['ADC_CR1_JAUTO_Pos',['../group___peripheral___registers___bits___definition.html#gac65ab808d9f67501a3e032f6e093baa7',1,'stm32f407xx_matlab.h']]], - ['adc_5fcr1_5fjawden_97',['ADC_CR1_JAWDEN',['../group___peripheral___registers___bits___definition.html#ga4886de74bcd3a1e545094089f76fd0b3',1,'stm32f407xx_matlab.h']]], - ['adc_5fcr1_5fjawden_5fmsk_98',['ADC_CR1_JAWDEN_Msk',['../group___peripheral___registers___bits___definition.html#ga29a30d56ef1ba75b52db631e367b13bb',1,'stm32f407xx_matlab.h']]], - ['adc_5fcr1_5fjawden_5fpos_99',['ADC_CR1_JAWDEN_Pos',['../group___peripheral___registers___bits___definition.html#ga78cb5899a747da3e5013ad44934b5c7d',1,'stm32f407xx_matlab.h']]], - ['adc_5fcr1_5fjdiscen_100',['ADC_CR1_JDISCEN',['../group___peripheral___registers___bits___definition.html#gacd06a2840346bf45ff335707db0b6e30',1,'stm32f407xx_matlab.h']]], - ['adc_5fcr1_5fjdiscen_5fmsk_101',['ADC_CR1_JDISCEN_Msk',['../group___peripheral___registers___bits___definition.html#gaae5059f8684f70119fff571d8c79bbaf',1,'stm32f407xx_matlab.h']]], - ['adc_5fcr1_5fjdiscen_5fpos_102',['ADC_CR1_JDISCEN_Pos',['../group___peripheral___registers___bits___definition.html#gad2e2019ed8fe62389fe06843f9bbc265',1,'stm32f407xx_matlab.h']]], - ['adc_5fcr1_5fjeocie_103',['ADC_CR1_JEOCIE',['../group___peripheral___registers___bits___definition.html#ga5c46fc1dc6c63acf88821f46a8f6d5e7',1,'stm32f407xx_matlab.h']]], - ['adc_5fcr1_5fjeocie_5fmsk_104',['ADC_CR1_JEOCIE_Msk',['../group___peripheral___registers___bits___definition.html#ga4c41e259f643939c71619ce4f743554a',1,'stm32f407xx_matlab.h']]], - ['adc_5fcr1_5fjeocie_5fpos_105',['ADC_CR1_JEOCIE_Pos',['../group___peripheral___registers___bits___definition.html#ga89dc37165238a2b3a31bad4bf2241b12',1,'stm32f407xx_matlab.h']]], - ['adc_5fcr1_5fovrie_106',['ADC_CR1_OVRIE',['../group___peripheral___registers___bits___definition.html#gaa892fda7c204bf18a33a059f28be0fba',1,'stm32f407xx_matlab.h']]], - ['adc_5fcr1_5fovrie_5fmsk_107',['ADC_CR1_OVRIE_Msk',['../group___peripheral___registers___bits___definition.html#gada4ec8e732a43f37a4568049593aa146',1,'stm32f407xx_matlab.h']]], - ['adc_5fcr1_5fovrie_5fpos_108',['ADC_CR1_OVRIE_Pos',['../group___peripheral___registers___bits___definition.html#ga0c72d6e0c41f98ea9b378d8455de2f13',1,'stm32f407xx_matlab.h']]], - ['adc_5fcr1_5fres_109',['ADC_CR1_RES',['../group___peripheral___registers___bits___definition.html#ga71e4a4c233895a2e7b6dd3ca6ca849e5',1,'stm32f407xx_matlab.h']]], - ['adc_5fcr1_5fres_5f0_110',['ADC_CR1_RES_0',['../group___peripheral___registers___bits___definition.html#gacfc432ddbd2140a92d877f6d9dc52417',1,'stm32f407xx_matlab.h']]], - ['adc_5fcr1_5fres_5f1_111',['ADC_CR1_RES_1',['../group___peripheral___registers___bits___definition.html#ga674904864f540043692a5b5ead9fae10',1,'stm32f407xx_matlab.h']]], - ['adc_5fcr1_5fres_5fmsk_112',['ADC_CR1_RES_Msk',['../group___peripheral___registers___bits___definition.html#ga5645a309568931b9f783dbca969ff487',1,'stm32f407xx_matlab.h']]], - ['adc_5fcr1_5fres_5fpos_113',['ADC_CR1_RES_Pos',['../group___peripheral___registers___bits___definition.html#gacae7156287b4fc60bc71114529b7b868',1,'stm32f407xx_matlab.h']]], - ['adc_5fcr1_5fscan_114',['ADC_CR1_SCAN',['../group___peripheral___registers___bits___definition.html#gaaeab75ece0c73dd97e8f21911ed22d06',1,'stm32f407xx_matlab.h']]], - ['adc_5fcr1_5fscan_5fmsk_115',['ADC_CR1_SCAN_Msk',['../group___peripheral___registers___bits___definition.html#ga3ae87fc99e54856233fe19c05947821d',1,'stm32f407xx_matlab.h']]], - ['adc_5fcr1_5fscan_5fpos_116',['ADC_CR1_SCAN_Pos',['../group___peripheral___registers___bits___definition.html#ga4dcc7aec82792bc0439ebf0eaa871d5c',1,'stm32f407xx_matlab.h']]], - ['adc_5fcr2_5fadon_117',['ADC_CR2_ADON',['../group___peripheral___registers___bits___definition.html#ga89b646f092b052d8488d2016f6290f0e',1,'stm32f407xx_matlab.h']]], - ['adc_5fcr2_5fadon_5fmsk_118',['ADC_CR2_ADON_Msk',['../group___peripheral___registers___bits___definition.html#ga523c9c51b9eefe42cc33dec9dbcd7091',1,'stm32f407xx_matlab.h']]], - ['adc_5fcr2_5fadon_5fpos_119',['ADC_CR2_ADON_Pos',['../group___peripheral___registers___bits___definition.html#ga234ecbd845e8f7b48fab4b3f1e12e788',1,'stm32f407xx_matlab.h']]], - ['adc_5fcr2_5falign_120',['ADC_CR2_ALIGN',['../group___peripheral___registers___bits___definition.html#gaf5950b5a7438a447584f6dd86c343362',1,'stm32f407xx_matlab.h']]], - ['adc_5fcr2_5falign_5fmsk_121',['ADC_CR2_ALIGN_Msk',['../group___peripheral___registers___bits___definition.html#gada0bca3543546c0f5c893a4a99a4ddcc',1,'stm32f407xx_matlab.h']]], - ['adc_5fcr2_5falign_5fpos_122',['ADC_CR2_ALIGN_Pos',['../group___peripheral___registers___bits___definition.html#ga6422927e869ce87e289e796dcf0067c2',1,'stm32f407xx_matlab.h']]], - ['adc_5fcr2_5fcont_123',['ADC_CR2_CONT',['../group___peripheral___registers___bits___definition.html#ga49bb71a868c9d88a0f7bbe48918b2140',1,'stm32f407xx_matlab.h']]], - ['adc_5fcr2_5fcont_5fmsk_124',['ADC_CR2_CONT_Msk',['../group___peripheral___registers___bits___definition.html#ga69a1c4bf40a36bd05804f1083f745914',1,'stm32f407xx_matlab.h']]], - ['adc_5fcr2_5fcont_5fpos_125',['ADC_CR2_CONT_Pos',['../group___peripheral___registers___bits___definition.html#gab4401869d89774c7f187aa72c3f9fae2',1,'stm32f407xx_matlab.h']]], - ['adc_5fcr2_5fdds_126',['ADC_CR2_DDS',['../group___peripheral___registers___bits___definition.html#ga0d7d75f0c4c8fa190fbf9f86fbe6dfc8',1,'stm32f407xx_matlab.h']]], - ['adc_5fcr2_5fdds_5fmsk_127',['ADC_CR2_DDS_Msk',['../group___peripheral___registers___bits___definition.html#ga96fbc51781aa1e2cb18d72ac67e748fe',1,'stm32f407xx_matlab.h']]], - ['adc_5fcr2_5fdds_5fpos_128',['ADC_CR2_DDS_Pos',['../group___peripheral___registers___bits___definition.html#ga25e88283dda37ac8153f8f2d5aa8fd4b',1,'stm32f407xx_matlab.h']]], - ['adc_5fcr2_5fdma_129',['ADC_CR2_DMA',['../group___peripheral___registers___bits___definition.html#ga017309ac4b532bc8c607388f4e2cbbec',1,'stm32f407xx_matlab.h']]], - ['adc_5fcr2_5fdma_5fmsk_130',['ADC_CR2_DMA_Msk',['../group___peripheral___registers___bits___definition.html#gad9bfa1dd15f4531ef79131a4a2810342',1,'stm32f407xx_matlab.h']]], - ['adc_5fcr2_5fdma_5fpos_131',['ADC_CR2_DMA_Pos',['../group___peripheral___registers___bits___definition.html#ga8edaebc5ec9c7cf465e7810189052ffd',1,'stm32f407xx_matlab.h']]], - ['adc_5fcr2_5feocs_132',['ADC_CR2_EOCS',['../group___peripheral___registers___bits___definition.html#gaf9dac2004ab20295e04012060ab24aeb',1,'stm32f407xx_matlab.h']]], - ['adc_5fcr2_5feocs_5fmsk_133',['ADC_CR2_EOCS_Msk',['../group___peripheral___registers___bits___definition.html#gacee54d4669ca3fd1c2e760cbe1a0dcbd',1,'stm32f407xx_matlab.h']]], - ['adc_5fcr2_5feocs_5fpos_134',['ADC_CR2_EOCS_Pos',['../group___peripheral___registers___bits___definition.html#ga375e2be253b645381365c90ae8c4cb1f',1,'stm32f407xx_matlab.h']]], - ['adc_5fcr2_5fexten_135',['ADC_CR2_EXTEN',['../group___peripheral___registers___bits___definition.html#ga574b4d8e90655d0432882d620e629234',1,'stm32f407xx_matlab.h']]], - ['adc_5fcr2_5fexten_5f0_136',['ADC_CR2_EXTEN_0',['../group___peripheral___registers___bits___definition.html#ga3519da0cc6fbd31444a16244c70232e6',1,'stm32f407xx_matlab.h']]], - ['adc_5fcr2_5fexten_5f1_137',['ADC_CR2_EXTEN_1',['../group___peripheral___registers___bits___definition.html#ga17e37edddbb6ad791bffb350cca23d4d',1,'stm32f407xx_matlab.h']]], - ['adc_5fcr2_5fexten_5fmsk_138',['ADC_CR2_EXTEN_Msk',['../group___peripheral___registers___bits___definition.html#gac97138f7c2e3ecbb31756679589c9b62',1,'stm32f407xx_matlab.h']]], - ['adc_5fcr2_5fexten_5fpos_139',['ADC_CR2_EXTEN_Pos',['../group___peripheral___registers___bits___definition.html#ga902a845718958f3db26c7d56e9c3a286',1,'stm32f407xx_matlab.h']]], - ['adc_5fcr2_5fextsel_140',['ADC_CR2_EXTSEL',['../group___peripheral___registers___bits___definition.html#ga6d1054d6cd017e305cf6e8a864ce96c8',1,'stm32f407xx_matlab.h']]], - ['adc_5fcr2_5fextsel_5f0_141',['ADC_CR2_EXTSEL_0',['../group___peripheral___registers___bits___definition.html#ga9410c7fd93f6d0b157ede745ee269d7b',1,'stm32f407xx_matlab.h']]], - ['adc_5fcr2_5fextsel_5f1_142',['ADC_CR2_EXTSEL_1',['../group___peripheral___registers___bits___definition.html#ga5a6725419743a8d01b4a223609952893',1,'stm32f407xx_matlab.h']]], - ['adc_5fcr2_5fextsel_5f2_143',['ADC_CR2_EXTSEL_2',['../group___peripheral___registers___bits___definition.html#ga5c2322988b5fff19d012d9179d412ad0',1,'stm32f407xx_matlab.h']]], - ['adc_5fcr2_5fextsel_5f3_144',['ADC_CR2_EXTSEL_3',['../group___peripheral___registers___bits___definition.html#ga387de6160834197888efa43e164c2db9',1,'stm32f407xx_matlab.h']]], - ['adc_5fcr2_5fextsel_5fmsk_145',['ADC_CR2_EXTSEL_Msk',['../group___peripheral___registers___bits___definition.html#gaef4979d74537d34ce18573d072e33408',1,'stm32f407xx_matlab.h']]], - ['adc_5fcr2_5fextsel_5fpos_146',['ADC_CR2_EXTSEL_Pos',['../group___peripheral___registers___bits___definition.html#ga98246071e8135d0b92366024e474511c',1,'stm32f407xx_matlab.h']]], - ['adc_5fcr2_5fjexten_147',['ADC_CR2_JEXTEN',['../group___peripheral___registers___bits___definition.html#ga07330f702208792faca3a563dc4fd9c6',1,'stm32f407xx_matlab.h']]], - ['adc_5fcr2_5fjexten_5f0_148',['ADC_CR2_JEXTEN_0',['../group___peripheral___registers___bits___definition.html#ga0b3c99510de210ff3137ff8de328889b',1,'stm32f407xx_matlab.h']]], - ['adc_5fcr2_5fjexten_5f1_149',['ADC_CR2_JEXTEN_1',['../group___peripheral___registers___bits___definition.html#ga949c70fdf36a32a6afcbf44fec123832',1,'stm32f407xx_matlab.h']]], - ['adc_5fcr2_5fjexten_5fmsk_150',['ADC_CR2_JEXTEN_Msk',['../group___peripheral___registers___bits___definition.html#gac444a034ccfbea8f0a0a1b3a40abb600',1,'stm32f407xx_matlab.h']]], - ['adc_5fcr2_5fjexten_5fpos_151',['ADC_CR2_JEXTEN_Pos',['../group___peripheral___registers___bits___definition.html#gacf91b9e9943eb12821746a1fe4a68988',1,'stm32f407xx_matlab.h']]], - ['adc_5fcr2_5fjextsel_152',['ADC_CR2_JEXTSEL',['../group___peripheral___registers___bits___definition.html#gaab3aa5d0e2a4b77960ec8f3b425a3eac',1,'stm32f407xx_matlab.h']]], - ['adc_5fcr2_5fjextsel_5f0_153',['ADC_CR2_JEXTSEL_0',['../group___peripheral___registers___bits___definition.html#gaa70c1f30e2101e2177ce564440203ba3',1,'stm32f407xx_matlab.h']]], - ['adc_5fcr2_5fjextsel_5f1_154',['ADC_CR2_JEXTSEL_1',['../group___peripheral___registers___bits___definition.html#ga99fa4a240d34ce231d6d0543bac7fd9b',1,'stm32f407xx_matlab.h']]], - ['adc_5fcr2_5fjextsel_5f2_155',['ADC_CR2_JEXTSEL_2',['../group___peripheral___registers___bits___definition.html#ga571bb97f950181fedbc0d4756482713d',1,'stm32f407xx_matlab.h']]], - ['adc_5fcr2_5fjextsel_5f3_156',['ADC_CR2_JEXTSEL_3',['../group___peripheral___registers___bits___definition.html#gae34f5dda7a153ffd927c9cd38999f822',1,'stm32f407xx_matlab.h']]], - ['adc_5fcr2_5fjextsel_5fmsk_157',['ADC_CR2_JEXTSEL_Msk',['../group___peripheral___registers___bits___definition.html#ga57147ca3b182775bc6708bd7edad0a8d',1,'stm32f407xx_matlab.h']]], - ['adc_5fcr2_5fjextsel_5fpos_158',['ADC_CR2_JEXTSEL_Pos',['../group___peripheral___registers___bits___definition.html#ga6d64811b8292d3145622b767f859e3b0',1,'stm32f407xx_matlab.h']]], - ['adc_5fcr2_5fjswstart_159',['ADC_CR2_JSWSTART',['../group___peripheral___registers___bits___definition.html#gac12fe8a6cc24eef2ed2e1f1525855678',1,'stm32f407xx_matlab.h']]], - ['adc_5fcr2_5fjswstart_5fmsk_160',['ADC_CR2_JSWSTART_Msk',['../group___peripheral___registers___bits___definition.html#gac1555cd00a88accf874a2bda2c0ac8d4',1,'stm32f407xx_matlab.h']]], - ['adc_5fcr2_5fjswstart_5fpos_161',['ADC_CR2_JSWSTART_Pos',['../group___peripheral___registers___bits___definition.html#ga3c5de0a53e5697dcb16759a12c47c7a4',1,'stm32f407xx_matlab.h']]], - ['adc_5fcr2_5fswstart_162',['ADC_CR2_SWSTART',['../group___peripheral___registers___bits___definition.html#ga5eae65bad1a6c975e1911eb5ba117468',1,'stm32f407xx_matlab.h']]], - ['adc_5fcr2_5fswstart_5fmsk_163',['ADC_CR2_SWSTART_Msk',['../group___peripheral___registers___bits___definition.html#gaa5c16a177295208be4bed45f350c315e',1,'stm32f407xx_matlab.h']]], - ['adc_5fcr2_5fswstart_5fpos_164',['ADC_CR2_SWSTART_Pos',['../group___peripheral___registers___bits___definition.html#gaf78afe48fe6fdadf00d3c37cfed860a7',1,'stm32f407xx_matlab.h']]], - ['adc_5fcsr_5fawd1_165',['ADC_CSR_AWD1',['../group___peripheral___registers___bits___definition.html#ga3e640f7443f14d01a37e29cff004223f',1,'stm32f407xx_matlab.h']]], - ['adc_5fcsr_5fawd1_5fmsk_166',['ADC_CSR_AWD1_Msk',['../group___peripheral___registers___bits___definition.html#ga8fc1dc3f69bc55d0dc278a8cfe172200',1,'stm32f407xx_matlab.h']]], - ['adc_5fcsr_5fawd1_5fpos_167',['ADC_CSR_AWD1_Pos',['../group___peripheral___registers___bits___definition.html#gaabf05dcdb9f298564bf23c2c012e0471',1,'stm32f407xx_matlab.h']]], - ['adc_5fcsr_5fawd2_168',['ADC_CSR_AWD2',['../group___peripheral___registers___bits___definition.html#ga80d8090a99ec65807ed831fea0d5524c',1,'stm32f407xx_matlab.h']]], - ['adc_5fcsr_5fawd2_5fmsk_169',['ADC_CSR_AWD2_Msk',['../group___peripheral___registers___bits___definition.html#gaf07d606cd2ac81d17e0a9cf425261d33',1,'stm32f407xx_matlab.h']]], - ['adc_5fcsr_5fawd2_5fpos_170',['ADC_CSR_AWD2_Pos',['../group___peripheral___registers___bits___definition.html#ga2f64205df755a2aef86ebb9f9cbe912f',1,'stm32f407xx_matlab.h']]], - ['adc_5fcsr_5fawd3_171',['ADC_CSR_AWD3',['../group___peripheral___registers___bits___definition.html#gad8883de33c5a7b30c611db11340fec6d',1,'stm32f407xx_matlab.h']]], - ['adc_5fcsr_5fawd3_5fmsk_172',['ADC_CSR_AWD3_Msk',['../group___peripheral___registers___bits___definition.html#gab466d762c126698b9be1d851411e13b9',1,'stm32f407xx_matlab.h']]], - ['adc_5fcsr_5fawd3_5fpos_173',['ADC_CSR_AWD3_Pos',['../group___peripheral___registers___bits___definition.html#ga0cc0cb58fe0e65bf12a871cd5b4f5a3a',1,'stm32f407xx_matlab.h']]], - ['adc_5fcsr_5fdovr1_174',['ADC_CSR_DOVR1',['../group___peripheral___registers___bits___definition.html#ga321ed2ccdf98d3a3307947056a8c401a',1,'stm32f407xx_matlab.h']]], - ['adc_5fcsr_5fdovr2_175',['ADC_CSR_DOVR2',['../group___peripheral___registers___bits___definition.html#ga00e2a30df5568b5663e9f016743b3a35',1,'stm32f407xx_matlab.h']]], - ['adc_5fcsr_5fdovr3_176',['ADC_CSR_DOVR3',['../group___peripheral___registers___bits___definition.html#ga396513974cf26f2a4aa0f36e755e227c',1,'stm32f407xx_matlab.h']]], - ['adc_5fcsr_5feoc1_177',['ADC_CSR_EOC1',['../group___peripheral___registers___bits___definition.html#ga715bcb019d713187aacd46f4482fa5f9',1,'stm32f407xx_matlab.h']]], - ['adc_5fcsr_5feoc1_5fmsk_178',['ADC_CSR_EOC1_Msk',['../group___peripheral___registers___bits___definition.html#gacaca4cc88bbeca3aee454610c500d2fc',1,'stm32f407xx_matlab.h']]], - ['adc_5fcsr_5feoc1_5fpos_179',['ADC_CSR_EOC1_Pos',['../group___peripheral___registers___bits___definition.html#ga193522f6fdf87c39545d2697f3650547',1,'stm32f407xx_matlab.h']]], - ['adc_5fcsr_5feoc2_180',['ADC_CSR_EOC2',['../group___peripheral___registers___bits___definition.html#ga411d79254769bbb4eeb14964abad497a',1,'stm32f407xx_matlab.h']]], - ['adc_5fcsr_5feoc2_5fmsk_181',['ADC_CSR_EOC2_Msk',['../group___peripheral___registers___bits___definition.html#ga8d50d5f274525ebcca937eac9f52d2d1',1,'stm32f407xx_matlab.h']]], - ['adc_5fcsr_5feoc2_5fpos_182',['ADC_CSR_EOC2_Pos',['../group___peripheral___registers___bits___definition.html#ga4c366fb2cc8fe08c701b8b8f5babe5f8',1,'stm32f407xx_matlab.h']]], - ['adc_5fcsr_5feoc3_183',['ADC_CSR_EOC3',['../group___peripheral___registers___bits___definition.html#ga4a94c410343ba459146b2bb17833a795',1,'stm32f407xx_matlab.h']]], - ['adc_5fcsr_5feoc3_5fmsk_184',['ADC_CSR_EOC3_Msk',['../group___peripheral___registers___bits___definition.html#ga337e83ffa1ec72fe00ab4b9c889a5acd',1,'stm32f407xx_matlab.h']]], - ['adc_5fcsr_5feoc3_5fpos_185',['ADC_CSR_EOC3_Pos',['../group___peripheral___registers___bits___definition.html#ga17e2ab7d373bb1befc8891719de8c437',1,'stm32f407xx_matlab.h']]], - ['adc_5fcsr_5fjeoc1_186',['ADC_CSR_JEOC1',['../group___peripheral___registers___bits___definition.html#ga1a8a134d8b946f3549390294ef94b8d6',1,'stm32f407xx_matlab.h']]], - ['adc_5fcsr_5fjeoc1_5fmsk_187',['ADC_CSR_JEOC1_Msk',['../group___peripheral___registers___bits___definition.html#ga954441bd559cdbe9da94c7ff0172c859',1,'stm32f407xx_matlab.h']]], - ['adc_5fcsr_5fjeoc1_5fpos_188',['ADC_CSR_JEOC1_Pos',['../group___peripheral___registers___bits___definition.html#gabff4c4fa606c1a8c035b453d95da53fd',1,'stm32f407xx_matlab.h']]], - ['adc_5fcsr_5fjeoc2_189',['ADC_CSR_JEOC2',['../group___peripheral___registers___bits___definition.html#gaf24dbb77fadc6f928b8e38199a08abc7',1,'stm32f407xx_matlab.h']]], - ['adc_5fcsr_5fjeoc2_5fmsk_190',['ADC_CSR_JEOC2_Msk',['../group___peripheral___registers___bits___definition.html#ga8a92cfaa1c1cf45b621a52cdea84dfb4',1,'stm32f407xx_matlab.h']]], - ['adc_5fcsr_5fjeoc2_5fpos_191',['ADC_CSR_JEOC2_Pos',['../group___peripheral___registers___bits___definition.html#ga5615f8b2030741d5188cb255da51a409',1,'stm32f407xx_matlab.h']]], - ['adc_5fcsr_5fjeoc3_192',['ADC_CSR_JEOC3',['../group___peripheral___registers___bits___definition.html#gae7d3c36f449ef1ee9ee20c5686b4e974',1,'stm32f407xx_matlab.h']]], - ['adc_5fcsr_5fjeoc3_5fmsk_193',['ADC_CSR_JEOC3_Msk',['../group___peripheral___registers___bits___definition.html#ga48e83374e0184b6a6ba6f3216d0d2ecc',1,'stm32f407xx_matlab.h']]], - ['adc_5fcsr_5fjeoc3_5fpos_194',['ADC_CSR_JEOC3_Pos',['../group___peripheral___registers___bits___definition.html#ga6d7e8c14892467a1d198b169c3c0bb78',1,'stm32f407xx_matlab.h']]], - ['adc_5fcsr_5fjstrt1_195',['ADC_CSR_JSTRT1',['../group___peripheral___registers___bits___definition.html#ga3f1e6578b14d71c6d972c6d6f6d48eaa',1,'stm32f407xx_matlab.h']]], - ['adc_5fcsr_5fjstrt1_5fmsk_196',['ADC_CSR_JSTRT1_Msk',['../group___peripheral___registers___bits___definition.html#ga6e0c41a114f966849054e2e43ee9b115',1,'stm32f407xx_matlab.h']]], - ['adc_5fcsr_5fjstrt1_5fpos_197',['ADC_CSR_JSTRT1_Pos',['../group___peripheral___registers___bits___definition.html#gaa094512686f5c37d85ec4c41b9fe1d21',1,'stm32f407xx_matlab.h']]], - ['adc_5fcsr_5fjstrt2_198',['ADC_CSR_JSTRT2',['../group___peripheral___registers___bits___definition.html#ga0ca65d6d580299518fb7491e1cebac1d',1,'stm32f407xx_matlab.h']]], - ['adc_5fcsr_5fjstrt2_5fmsk_199',['ADC_CSR_JSTRT2_Msk',['../group___peripheral___registers___bits___definition.html#ga1f6fcf838fd219679c57c9b87eba1444',1,'stm32f407xx_matlab.h']]], - ['adc_5fcsr_5fjstrt2_5fpos_200',['ADC_CSR_JSTRT2_Pos',['../group___peripheral___registers___bits___definition.html#gaa7624f0eb95cc1a44180577d68273a13',1,'stm32f407xx_matlab.h']]], - ['adc_5fcsr_5fjstrt3_201',['ADC_CSR_JSTRT3',['../group___peripheral___registers___bits___definition.html#ga94140d21b4c83d9f401cc459a7ec6060',1,'stm32f407xx_matlab.h']]], - ['adc_5fcsr_5fjstrt3_5fmsk_202',['ADC_CSR_JSTRT3_Msk',['../group___peripheral___registers___bits___definition.html#gaa137f40aeea09749a280b436c560a8e6',1,'stm32f407xx_matlab.h']]], - ['adc_5fcsr_5fjstrt3_5fpos_203',['ADC_CSR_JSTRT3_Pos',['../group___peripheral___registers___bits___definition.html#ga6e64575250e915936cf02785b3068c95',1,'stm32f407xx_matlab.h']]], - ['adc_5fcsr_5fovr1_204',['ADC_CSR_OVR1',['../group___peripheral___registers___bits___definition.html#ga52c109fe013835222183c22b26d6edec',1,'stm32f407xx_matlab.h']]], - ['adc_5fcsr_5fovr1_5fmsk_205',['ADC_CSR_OVR1_Msk',['../group___peripheral___registers___bits___definition.html#ga7ab0daf58c1ac552862c36465fc864cc',1,'stm32f407xx_matlab.h']]], - ['adc_5fcsr_5fovr1_5fpos_206',['ADC_CSR_OVR1_Pos',['../group___peripheral___registers___bits___definition.html#ga94e77ef740b6a1dccec74746261be4f1',1,'stm32f407xx_matlab.h']]], - ['adc_5fcsr_5fovr2_207',['ADC_CSR_OVR2',['../group___peripheral___registers___bits___definition.html#ga3b0e80da58202660466f6916c0bbb9da',1,'stm32f407xx_matlab.h']]], - ['adc_5fcsr_5fovr2_5fmsk_208',['ADC_CSR_OVR2_Msk',['../group___peripheral___registers___bits___definition.html#ga592e0a5440edb75e0af2cbb8f8e9f4ca',1,'stm32f407xx_matlab.h']]], - ['adc_5fcsr_5fovr2_5fpos_209',['ADC_CSR_OVR2_Pos',['../group___peripheral___registers___bits___definition.html#ga6ad98b43be125be93ecac83e636b9b30',1,'stm32f407xx_matlab.h']]], - ['adc_5fcsr_5fovr3_210',['ADC_CSR_OVR3',['../group___peripheral___registers___bits___definition.html#gab76495b35a2bc7fc5f1b51ab1ee92384',1,'stm32f407xx_matlab.h']]], - ['adc_5fcsr_5fovr3_5fmsk_211',['ADC_CSR_OVR3_Msk',['../group___peripheral___registers___bits___definition.html#gaef6f4ccc5a845954e07699858b868c9b',1,'stm32f407xx_matlab.h']]], - ['adc_5fcsr_5fovr3_5fpos_212',['ADC_CSR_OVR3_Pos',['../group___peripheral___registers___bits___definition.html#gab46fd70aefec77d01f6fba4d19d677b6',1,'stm32f407xx_matlab.h']]], - ['adc_5fcsr_5fstrt1_213',['ADC_CSR_STRT1',['../group___peripheral___registers___bits___definition.html#ga78ff468cfaa299ef62ab7b8b9910e142',1,'stm32f407xx_matlab.h']]], - ['adc_5fcsr_5fstrt1_5fmsk_214',['ADC_CSR_STRT1_Msk',['../group___peripheral___registers___bits___definition.html#ga1d9691131e58b26068e792ad4b458bd6',1,'stm32f407xx_matlab.h']]], - ['adc_5fcsr_5fstrt1_5fpos_215',['ADC_CSR_STRT1_Pos',['../group___peripheral___registers___bits___definition.html#ga186066448c230ab12a99cd67a22aaea5',1,'stm32f407xx_matlab.h']]], - ['adc_5fcsr_5fstrt2_216',['ADC_CSR_STRT2',['../group___peripheral___registers___bits___definition.html#gac9e79005049b17d08c28aeca86677655',1,'stm32f407xx_matlab.h']]], - ['adc_5fcsr_5fstrt2_5fmsk_217',['ADC_CSR_STRT2_Msk',['../group___peripheral___registers___bits___definition.html#gae765e2672e081170cb86dc14096b2c9d',1,'stm32f407xx_matlab.h']]], - ['adc_5fcsr_5fstrt2_5fpos_218',['ADC_CSR_STRT2_Pos',['../group___peripheral___registers___bits___definition.html#gaf06d7d8b3b81c9fca7b92449c039a859',1,'stm32f407xx_matlab.h']]], - ['adc_5fcsr_5fstrt3_219',['ADC_CSR_STRT3',['../group___peripheral___registers___bits___definition.html#ga13ca665cc575b64588475723f5289d4a',1,'stm32f407xx_matlab.h']]], - ['adc_5fcsr_5fstrt3_5fmsk_220',['ADC_CSR_STRT3_Msk',['../group___peripheral___registers___bits___definition.html#ga774dbbb3929e4d525c6fce448459a711',1,'stm32f407xx_matlab.h']]], - ['adc_5fcsr_5fstrt3_5fpos_221',['ADC_CSR_STRT3_Pos',['../group___peripheral___registers___bits___definition.html#ga1f2699ef95e89fb1803e46d4670ce1f2',1,'stm32f407xx_matlab.h']]], - ['adc_5fdr_5fadc2data_222',['ADC_DR_ADC2DATA',['../group___peripheral___registers___bits___definition.html#ga67c396288ac97bfab2d37017bd536b98',1,'stm32f407xx_matlab.h']]], - ['adc_5fdr_5fadc2data_5fmsk_223',['ADC_DR_ADC2DATA_Msk',['../group___peripheral___registers___bits___definition.html#ga86da874944121326b9f268295d8ce9b9',1,'stm32f407xx_matlab.h']]], - ['adc_5fdr_5fadc2data_5fpos_224',['ADC_DR_ADC2DATA_Pos',['../group___peripheral___registers___bits___definition.html#gad6fdf317d06706f2a57b4aca8334eb37',1,'stm32f407xx_matlab.h']]], - ['adc_5fdr_5fdata_225',['ADC_DR_DATA',['../group___peripheral___registers___bits___definition.html#gada596183c4087696c486546e88176038',1,'stm32f407xx_matlab.h']]], - ['adc_5fdr_5fdata_5fmsk_226',['ADC_DR_DATA_Msk',['../group___peripheral___registers___bits___definition.html#ga85ec9cca38cafd77f3d56fdf80f84eb7',1,'stm32f407xx_matlab.h']]], - ['adc_5fdr_5fdata_5fpos_227',['ADC_DR_DATA_Pos',['../group___peripheral___registers___bits___definition.html#ga84a231db4b53876ee3823b0ea3c92a06',1,'stm32f407xx_matlab.h']]], - ['adc_5fhtr_5fht_228',['ADC_HTR_HT',['../group___peripheral___registers___bits___definition.html#gad685f031174465e636ef75a5bd7b637d',1,'stm32f407xx_matlab.h']]], - ['adc_5fhtr_5fht_5fmsk_229',['ADC_HTR_HT_Msk',['../group___peripheral___registers___bits___definition.html#ga9097907041c9d3893ab46b359ade4b00',1,'stm32f407xx_matlab.h']]], - ['adc_5fhtr_5fht_5fpos_230',['ADC_HTR_HT_Pos',['../group___peripheral___registers___bits___definition.html#ga4a635538ea4e4daa6b302e0d2d5c0932',1,'stm32f407xx_matlab.h']]], - ['adc_5firqn_231',['ADC_IRQn',['../group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a4d69175258ae261dd545001e810421b3',1,'stm32f407xx_matlab.h']]], - ['adc_5fjdr1_5fjdata_232',['ADC_JDR1_JDATA',['../group___peripheral___registers___bits___definition.html#gad02fcd8fd97b2f7d70a5a04fed60b558',1,'stm32f407xx_matlab.h']]], - ['adc_5fjdr1_5fjdata_5fmsk_233',['ADC_JDR1_JDATA_Msk',['../group___peripheral___registers___bits___definition.html#ga6440d03419f23870bf5bf1a38a57c79d',1,'stm32f407xx_matlab.h']]], - ['adc_5fjdr1_5fjdata_5fpos_234',['ADC_JDR1_JDATA_Pos',['../group___peripheral___registers___bits___definition.html#gadb0c0f7960a790d485b1ae99aed0e8c7',1,'stm32f407xx_matlab.h']]], - ['adc_5fjdr2_5fjdata_235',['ADC_JDR2_JDATA',['../group___peripheral___registers___bits___definition.html#ga9fbd8801b9c60269ca477062985a08e8',1,'stm32f407xx_matlab.h']]], - ['adc_5fjdr2_5fjdata_5fmsk_236',['ADC_JDR2_JDATA_Msk',['../group___peripheral___registers___bits___definition.html#gad0ff8b95da1c11baf16aa35dd8672670',1,'stm32f407xx_matlab.h']]], - ['adc_5fjdr2_5fjdata_5fpos_237',['ADC_JDR2_JDATA_Pos',['../group___peripheral___registers___bits___definition.html#ga2e02f5dbe30f9da55c112634b5636b3d',1,'stm32f407xx_matlab.h']]], - ['adc_5fjdr3_5fjdata_238',['ADC_JDR3_JDATA',['../group___peripheral___registers___bits___definition.html#gaae84e9e5928bb9ed1aef6c83089fb5ef',1,'stm32f407xx_matlab.h']]], - ['adc_5fjdr3_5fjdata_5fmsk_239',['ADC_JDR3_JDATA_Msk',['../group___peripheral___registers___bits___definition.html#gaee0994ddf4fa21f7e6cedc0c3d599683',1,'stm32f407xx_matlab.h']]], - ['adc_5fjdr3_5fjdata_5fpos_240',['ADC_JDR3_JDATA_Pos',['../group___peripheral___registers___bits___definition.html#ga382b9639cc85f4dc0c4603b83e4e3246',1,'stm32f407xx_matlab.h']]], - ['adc_5fjdr4_5fjdata_241',['ADC_JDR4_JDATA',['../group___peripheral___registers___bits___definition.html#ga48d8fafdad1fb1bb0f761fd833e7b0c1',1,'stm32f407xx_matlab.h']]], - ['adc_5fjdr4_5fjdata_5fmsk_242',['ADC_JDR4_JDATA_Msk',['../group___peripheral___registers___bits___definition.html#gad42adbc5ae1c70cdc1926642fcc2baef',1,'stm32f407xx_matlab.h']]], - ['adc_5fjdr4_5fjdata_5fpos_243',['ADC_JDR4_JDATA_Pos',['../group___peripheral___registers___bits___definition.html#gaa993f3df2df14e7be95b96543bd4873f',1,'stm32f407xx_matlab.h']]], - ['adc_5fjofr1_5fjoffset1_244',['ADC_JOFR1_JOFFSET1',['../group___peripheral___registers___bits___definition.html#gad76f97130b391455094605a6c803026c',1,'stm32f407xx_matlab.h']]], - ['adc_5fjofr1_5fjoffset1_5fmsk_245',['ADC_JOFR1_JOFFSET1_Msk',['../group___peripheral___registers___bits___definition.html#ga4aeb01e5e14a55e3de62770ff3b3d0fd',1,'stm32f407xx_matlab.h']]], - ['adc_5fjofr1_5fjoffset1_5fpos_246',['ADC_JOFR1_JOFFSET1_Pos',['../group___peripheral___registers___bits___definition.html#ga593196324c441869e2b7629db926aafd',1,'stm32f407xx_matlab.h']]], - ['adc_5fjofr2_5fjoffset2_247',['ADC_JOFR2_JOFFSET2',['../group___peripheral___registers___bits___definition.html#ga1b15a9e9ce10303e233059c1de6d956c',1,'stm32f407xx_matlab.h']]], - ['adc_5fjofr2_5fjoffset2_5fmsk_248',['ADC_JOFR2_JOFFSET2_Msk',['../group___peripheral___registers___bits___definition.html#ga21ef3d2ed0de640e567ecefb4c902df4',1,'stm32f407xx_matlab.h']]], - ['adc_5fjofr2_5fjoffset2_5fpos_249',['ADC_JOFR2_JOFFSET2_Pos',['../group___peripheral___registers___bits___definition.html#ga15e0dc116f3623901fdda1e743838334',1,'stm32f407xx_matlab.h']]], - ['adc_5fjofr3_5fjoffset3_250',['ADC_JOFR3_JOFFSET3',['../group___peripheral___registers___bits___definition.html#ga743e4c3a7cefc1a193146e77791c3985',1,'stm32f407xx_matlab.h']]], - ['adc_5fjofr3_5fjoffset3_5fmsk_251',['ADC_JOFR3_JOFFSET3_Msk',['../group___peripheral___registers___bits___definition.html#ga8e742777e82d2e3a58f789f7785fa530',1,'stm32f407xx_matlab.h']]], - ['adc_5fjofr3_5fjoffset3_5fpos_252',['ADC_JOFR3_JOFFSET3_Pos',['../group___peripheral___registers___bits___definition.html#gad339e95766c1c4dd3ec3ef2fa5856f8b',1,'stm32f407xx_matlab.h']]], - ['adc_5fjofr4_5fjoffset4_253',['ADC_JOFR4_JOFFSET4',['../group___peripheral___registers___bits___definition.html#gada0937f2f6a64bd6b7531ad553471b8d',1,'stm32f407xx_matlab.h']]], - ['adc_5fjofr4_5fjoffset4_5fmsk_254',['ADC_JOFR4_JOFFSET4_Msk',['../group___peripheral___registers___bits___definition.html#ga983eba37929e630bc6bec3c1ab411db5',1,'stm32f407xx_matlab.h']]], - ['adc_5fjofr4_5fjoffset4_5fpos_255',['ADC_JOFR4_JOFFSET4_Pos',['../group___peripheral___registers___bits___definition.html#gaeb1f1ccebbb9c41f3b6bae1f8c587618',1,'stm32f407xx_matlab.h']]], - ['adc_5fjsqr_5fjl_256',['ADC_JSQR_JL',['../group___peripheral___registers___bits___definition.html#gaa624d1fe34014b88873e2dfa91f79232',1,'stm32f407xx_matlab.h']]], - ['adc_5fjsqr_5fjl_5f0_257',['ADC_JSQR_JL_0',['../group___peripheral___registers___bits___definition.html#ga117a6719241f20dbd765bc34f9ffcd58',1,'stm32f407xx_matlab.h']]], - ['adc_5fjsqr_5fjl_5f1_258',['ADC_JSQR_JL_1',['../group___peripheral___registers___bits___definition.html#ga1f82ef3b6e6350b9e52e622daeaa3e6e',1,'stm32f407xx_matlab.h']]], - ['adc_5fjsqr_5fjl_5fmsk_259',['ADC_JSQR_JL_Msk',['../group___peripheral___registers___bits___definition.html#ga11fbbdaa929d9ecf3054aaaed0285b05',1,'stm32f407xx_matlab.h']]], - ['adc_5fjsqr_5fjl_5fpos_260',['ADC_JSQR_JL_Pos',['../group___peripheral___registers___bits___definition.html#gab1dd38cefe9e4ca58d8535c9b2386cb1',1,'stm32f407xx_matlab.h']]], - ['adc_5fjsqr_5fjsq1_261',['ADC_JSQR_JSQ1',['../group___peripheral___registers___bits___definition.html#gad7fa15dfe51b084b36cb5df2fbf44bb2',1,'stm32f407xx_matlab.h']]], - ['adc_5fjsqr_5fjsq1_5f0_262',['ADC_JSQR_JSQ1_0',['../group___peripheral___registers___bits___definition.html#gaf3ea38b080462c4571524b5fcbfed292',1,'stm32f407xx_matlab.h']]], - ['adc_5fjsqr_5fjsq1_5f1_263',['ADC_JSQR_JSQ1_1',['../group___peripheral___registers___bits___definition.html#gabae36d7655fb1dce11e60ffa8e57b509',1,'stm32f407xx_matlab.h']]], - ['adc_5fjsqr_5fjsq1_5f2_264',['ADC_JSQR_JSQ1_2',['../group___peripheral___registers___bits___definition.html#gad3e7a96d33f640444b40b70e9ee28671',1,'stm32f407xx_matlab.h']]], - ['adc_5fjsqr_5fjsq1_5f3_265',['ADC_JSQR_JSQ1_3',['../group___peripheral___registers___bits___definition.html#ga6066a6aef47f317a5df0c9bbf59121fb',1,'stm32f407xx_matlab.h']]], - ['adc_5fjsqr_5fjsq1_5f4_266',['ADC_JSQR_JSQ1_4',['../group___peripheral___registers___bits___definition.html#gaf2c4baf98380a477cebb01be3e8f0594',1,'stm32f407xx_matlab.h']]], - ['adc_5fjsqr_5fjsq1_5fmsk_267',['ADC_JSQR_JSQ1_Msk',['../group___peripheral___registers___bits___definition.html#ga3d51f520a176b598792f5019ef4e1f7e',1,'stm32f407xx_matlab.h']]], - ['adc_5fjsqr_5fjsq1_5fpos_268',['ADC_JSQR_JSQ1_Pos',['../group___peripheral___registers___bits___definition.html#gab9c01f684cb7d1dc5db5d91d29706d1e',1,'stm32f407xx_matlab.h']]], - ['adc_5fjsqr_5fjsq2_269',['ADC_JSQR_JSQ2',['../group___peripheral___registers___bits___definition.html#ga3e8446a5857e5379cff8cadf822e15d4',1,'stm32f407xx_matlab.h']]], - ['adc_5fjsqr_5fjsq2_5f0_270',['ADC_JSQR_JSQ2_0',['../group___peripheral___registers___bits___definition.html#gaabf0889d056b56e4a113142b3694166d',1,'stm32f407xx_matlab.h']]], - ['adc_5fjsqr_5fjsq2_5f1_271',['ADC_JSQR_JSQ2_1',['../group___peripheral___registers___bits___definition.html#ga048f97e9e332adb21eca27b647af1378',1,'stm32f407xx_matlab.h']]], - ['adc_5fjsqr_5fjsq2_5f2_272',['ADC_JSQR_JSQ2_2',['../group___peripheral___registers___bits___definition.html#ga18bee187ed94e73b16eeea7501394581',1,'stm32f407xx_matlab.h']]], - ['adc_5fjsqr_5fjsq2_5f3_273',['ADC_JSQR_JSQ2_3',['../group___peripheral___registers___bits___definition.html#ga78b031d11b56e49b2c28c1a79136b48a',1,'stm32f407xx_matlab.h']]], - ['adc_5fjsqr_5fjsq2_5f4_274',['ADC_JSQR_JSQ2_4',['../group___peripheral___registers___bits___definition.html#ga064d6ccde30a22430c658b8efc431e59',1,'stm32f407xx_matlab.h']]], - ['adc_5fjsqr_5fjsq2_5fmsk_275',['ADC_JSQR_JSQ2_Msk',['../group___peripheral___registers___bits___definition.html#ga1fb22b426f041225a2383fbb9a014c74',1,'stm32f407xx_matlab.h']]], - ['adc_5fjsqr_5fjsq2_5fpos_276',['ADC_JSQR_JSQ2_Pos',['../group___peripheral___registers___bits___definition.html#ga086dad3b0d75e5a34736717f639f54bc',1,'stm32f407xx_matlab.h']]], - ['adc_5fjsqr_5fjsq3_277',['ADC_JSQR_JSQ3',['../group___peripheral___registers___bits___definition.html#gae2fbdc1b854a54c4288402c2d3a7fca9',1,'stm32f407xx_matlab.h']]], - ['adc_5fjsqr_5fjsq3_5f0_278',['ADC_JSQR_JSQ3_0',['../group___peripheral___registers___bits___definition.html#ga12fbc27c3543f23125f632dfa60fdc98',1,'stm32f407xx_matlab.h']]], - ['adc_5fjsqr_5fjsq3_5f1_279',['ADC_JSQR_JSQ3_1',['../group___peripheral___registers___bits___definition.html#ga169ec7d371e3ee897b73c3ad84b6ed32',1,'stm32f407xx_matlab.h']]], - ['adc_5fjsqr_5fjsq3_5f2_280',['ADC_JSQR_JSQ3_2',['../group___peripheral___registers___bits___definition.html#ga693542d5a536304f364476589ba0bec9',1,'stm32f407xx_matlab.h']]], - ['adc_5fjsqr_5fjsq3_5f3_281',['ADC_JSQR_JSQ3_3',['../group___peripheral___registers___bits___definition.html#ga139ddd01c0faf219dca844477453149e',1,'stm32f407xx_matlab.h']]], - ['adc_5fjsqr_5fjsq3_5f4_282',['ADC_JSQR_JSQ3_4',['../group___peripheral___registers___bits___definition.html#gac1452b8cf4acc90fb522d90751043aac',1,'stm32f407xx_matlab.h']]], - ['adc_5fjsqr_5fjsq3_5fmsk_283',['ADC_JSQR_JSQ3_Msk',['../group___peripheral___registers___bits___definition.html#ga4b87c9c110f68556c6d266cd9808165b',1,'stm32f407xx_matlab.h']]], - ['adc_5fjsqr_5fjsq3_5fpos_284',['ADC_JSQR_JSQ3_Pos',['../group___peripheral___registers___bits___definition.html#ga9af86c6e6cd2d134f389580a03449e9e',1,'stm32f407xx_matlab.h']]], - ['adc_5fjsqr_5fjsq4_285',['ADC_JSQR_JSQ4',['../group___peripheral___registers___bits___definition.html#ga39a279051ef198ee34cad73743b996f4',1,'stm32f407xx_matlab.h']]], - ['adc_5fjsqr_5fjsq4_5f0_286',['ADC_JSQR_JSQ4_0',['../group___peripheral___registers___bits___definition.html#ga13e250d329673c02f7a0d24d25e83649',1,'stm32f407xx_matlab.h']]], - ['adc_5fjsqr_5fjsq4_5f1_287',['ADC_JSQR_JSQ4_1',['../group___peripheral___registers___bits___definition.html#ga30dad81d708c35136e2da4e96cfe07b7',1,'stm32f407xx_matlab.h']]], - ['adc_5fjsqr_5fjsq4_5f2_288',['ADC_JSQR_JSQ4_2',['../group___peripheral___registers___bits___definition.html#ga6ceab97acb95b31cb7448c9da38fc11a',1,'stm32f407xx_matlab.h']]], - ['adc_5fjsqr_5fjsq4_5f3_289',['ADC_JSQR_JSQ4_3',['../group___peripheral___registers___bits___definition.html#ga52f6571e7efed6a0f72df19c66d3c917',1,'stm32f407xx_matlab.h']]], - ['adc_5fjsqr_5fjsq4_5f4_290',['ADC_JSQR_JSQ4_4',['../group___peripheral___registers___bits___definition.html#gaede3a17ef541039943d9dcd85df223ca',1,'stm32f407xx_matlab.h']]], - ['adc_5fjsqr_5fjsq4_5fmsk_291',['ADC_JSQR_JSQ4_Msk',['../group___peripheral___registers___bits___definition.html#gaa3c43ea620dd89338b58bf89feab30fd',1,'stm32f407xx_matlab.h']]], - ['adc_5fjsqr_5fjsq4_5fpos_292',['ADC_JSQR_JSQ4_Pos',['../group___peripheral___registers___bits___definition.html#ga24746201bf3845f70dc4e442d61d470a',1,'stm32f407xx_matlab.h']]], - ['adc_5fltr_5flt_293',['ADC_LTR_LT',['../group___peripheral___registers___bits___definition.html#gac7ac18b970378acf726f04ae68232c24',1,'stm32f407xx_matlab.h']]], - ['adc_5fltr_5flt_5fmsk_294',['ADC_LTR_LT_Msk',['../group___peripheral___registers___bits___definition.html#gad1c59cf6098c3ba86d00ff2eabbee680',1,'stm32f407xx_matlab.h']]], - ['adc_5fltr_5flt_5fpos_295',['ADC_LTR_LT_Pos',['../group___peripheral___registers___bits___definition.html#ga309e0c5c17cfe008132dbc95924ba0cd',1,'stm32f407xx_matlab.h']]], - ['adc_5fmultimode_5fsupport_296',['ADC_MULTIMODE_SUPPORT',['../group___peripheral___registers___bits___definition.html#ga4e2d417bccd8d576e16729c3e5a25cb8',1,'stm32f407xx_matlab.h']]], - ['adc_5fsmpr1_5fsmp10_297',['ADC_SMPR1_SMP10',['../group___peripheral___registers___bits___definition.html#ga32242a2c2156a012a7343bcb43d490d0',1,'stm32f407xx_matlab.h']]], - ['adc_5fsmpr1_5fsmp10_5f0_298',['ADC_SMPR1_SMP10_0',['../group___peripheral___registers___bits___definition.html#ga8a8996c53042759f01e966fb00351ebf',1,'stm32f407xx_matlab.h']]], - ['adc_5fsmpr1_5fsmp10_5f1_299',['ADC_SMPR1_SMP10_1',['../group___peripheral___registers___bits___definition.html#ga42b96f058436c8bdcfabe1e08c7edd61',1,'stm32f407xx_matlab.h']]], - ['adc_5fsmpr1_5fsmp10_5f2_300',['ADC_SMPR1_SMP10_2',['../group___peripheral___registers___bits___definition.html#ga289d89b4d92d7f685a8e44aeb9ddcded',1,'stm32f407xx_matlab.h']]], - ['adc_5fsmpr1_5fsmp10_5fmsk_301',['ADC_SMPR1_SMP10_Msk',['../group___peripheral___registers___bits___definition.html#gaa436e3f99d6260a7c0d93c2c7b9e06e0',1,'stm32f407xx_matlab.h']]], - ['adc_5fsmpr1_5fsmp10_5fpos_302',['ADC_SMPR1_SMP10_Pos',['../group___peripheral___registers___bits___definition.html#gad2d3f858e16869682edb4fd672167f9e',1,'stm32f407xx_matlab.h']]], - ['adc_5fsmpr1_5fsmp11_303',['ADC_SMPR1_SMP11',['../group___peripheral___registers___bits___definition.html#ga4c74d559f2a70a2e8c807b7bcaccd800',1,'stm32f407xx_matlab.h']]], - ['adc_5fsmpr1_5fsmp11_5f0_304',['ADC_SMPR1_SMP11_0',['../group___peripheral___registers___bits___definition.html#ga60780d613953f48a2dfc8debce72fb28',1,'stm32f407xx_matlab.h']]], - ['adc_5fsmpr1_5fsmp11_5f1_305',['ADC_SMPR1_SMP11_1',['../group___peripheral___registers___bits___definition.html#gaa61e1dbafcae3e1c8eae4320a6e5ec5d',1,'stm32f407xx_matlab.h']]], - ['adc_5fsmpr1_5fsmp11_5f2_306',['ADC_SMPR1_SMP11_2',['../group___peripheral___registers___bits___definition.html#ga93a876a9a6d90cd30456433b7e38c3f2',1,'stm32f407xx_matlab.h']]], - ['adc_5fsmpr1_5fsmp11_5fmsk_307',['ADC_SMPR1_SMP11_Msk',['../group___peripheral___registers___bits___definition.html#ga2bed6ca83db1864feb7eb926d8228c85',1,'stm32f407xx_matlab.h']]], - ['adc_5fsmpr1_5fsmp11_5fpos_308',['ADC_SMPR1_SMP11_Pos',['../group___peripheral___registers___bits___definition.html#ga6b0f3653aea6b1db3875f59d5c3bdc74',1,'stm32f407xx_matlab.h']]], - ['adc_5fsmpr1_5fsmp12_309',['ADC_SMPR1_SMP12',['../group___peripheral___registers___bits___definition.html#ga433b5a7d944666fb7abed3b107c352fc',1,'stm32f407xx_matlab.h']]], - ['adc_5fsmpr1_5fsmp12_5f0_310',['ADC_SMPR1_SMP12_0',['../group___peripheral___registers___bits___definition.html#gaaaac6ae97c00276d7472bc92a9edd6e2',1,'stm32f407xx_matlab.h']]], - ['adc_5fsmpr1_5fsmp12_5f1_311',['ADC_SMPR1_SMP12_1',['../group___peripheral___registers___bits___definition.html#ga6020f9d742e15650ad919aaccaf2ff6c',1,'stm32f407xx_matlab.h']]], - ['adc_5fsmpr1_5fsmp12_5f2_312',['ADC_SMPR1_SMP12_2',['../group___peripheral___registers___bits___definition.html#gadb59adb544d416e91ea0c12d4f39ccc9',1,'stm32f407xx_matlab.h']]], - ['adc_5fsmpr1_5fsmp12_5fmsk_313',['ADC_SMPR1_SMP12_Msk',['../group___peripheral___registers___bits___definition.html#gae18d279a21d7ce940d6969500a25a13b',1,'stm32f407xx_matlab.h']]], - ['adc_5fsmpr1_5fsmp12_5fpos_314',['ADC_SMPR1_SMP12_Pos',['../group___peripheral___registers___bits___definition.html#gaeb6169f9cd1e9c488526140dcbf464c2',1,'stm32f407xx_matlab.h']]], - ['adc_5fsmpr1_5fsmp13_315',['ADC_SMPR1_SMP13',['../group___peripheral___registers___bits___definition.html#ga2df120cd93a177ea17946a656259129e',1,'stm32f407xx_matlab.h']]], - ['adc_5fsmpr1_5fsmp13_5f0_316',['ADC_SMPR1_SMP13_0',['../group___peripheral___registers___bits___definition.html#ga49e7444d6cf630eccfd52fb4155bd553',1,'stm32f407xx_matlab.h']]], - ['adc_5fsmpr1_5fsmp13_5f1_317',['ADC_SMPR1_SMP13_1',['../group___peripheral___registers___bits___definition.html#gad5d5ad9d8d08feaee18d1f2d8d6787a1',1,'stm32f407xx_matlab.h']]], - ['adc_5fsmpr1_5fsmp13_5f2_318',['ADC_SMPR1_SMP13_2',['../group___peripheral___registers___bits___definition.html#gac4cd285d46485136deb6223377d0b17c',1,'stm32f407xx_matlab.h']]], - ['adc_5fsmpr1_5fsmp13_5fmsk_319',['ADC_SMPR1_SMP13_Msk',['../group___peripheral___registers___bits___definition.html#gaa0b2a1ff66bccc991c783ceca1d69cfd',1,'stm32f407xx_matlab.h']]], - ['adc_5fsmpr1_5fsmp13_5fpos_320',['ADC_SMPR1_SMP13_Pos',['../group___peripheral___registers___bits___definition.html#ga9093533a0a301bae03822d9f8bfc7597',1,'stm32f407xx_matlab.h']]], - ['adc_5fsmpr1_5fsmp14_321',['ADC_SMPR1_SMP14',['../group___peripheral___registers___bits___definition.html#gab1574fc02a40f22fc751073e02ebb781',1,'stm32f407xx_matlab.h']]], - ['adc_5fsmpr1_5fsmp14_5f0_322',['ADC_SMPR1_SMP14_0',['../group___peripheral___registers___bits___definition.html#ga9243898272b1d27018c971eecfa57f78',1,'stm32f407xx_matlab.h']]], - ['adc_5fsmpr1_5fsmp14_5f1_323',['ADC_SMPR1_SMP14_1',['../group___peripheral___registers___bits___definition.html#ga1016b8ca359247491a2a0a5d77aa1c22',1,'stm32f407xx_matlab.h']]], - ['adc_5fsmpr1_5fsmp14_5f2_324',['ADC_SMPR1_SMP14_2',['../group___peripheral___registers___bits___definition.html#ga8e658a8b72bac244bf919a874690e49e',1,'stm32f407xx_matlab.h']]], - ['adc_5fsmpr1_5fsmp14_5fmsk_325',['ADC_SMPR1_SMP14_Msk',['../group___peripheral___registers___bits___definition.html#ga410946d711bfd8069e7eb95d6d83e832',1,'stm32f407xx_matlab.h']]], - ['adc_5fsmpr1_5fsmp14_5fpos_326',['ADC_SMPR1_SMP14_Pos',['../group___peripheral___registers___bits___definition.html#ga2da550ca91822740c151e660e6725475',1,'stm32f407xx_matlab.h']]], - ['adc_5fsmpr1_5fsmp15_327',['ADC_SMPR1_SMP15',['../group___peripheral___registers___bits___definition.html#ga5ae0043ad863f7710834217bc82c8ecf',1,'stm32f407xx_matlab.h']]], - ['adc_5fsmpr1_5fsmp15_5f0_328',['ADC_SMPR1_SMP15_0',['../group___peripheral___registers___bits___definition.html#gac5f8e555f5ece2ee632dd9d6c60d9584',1,'stm32f407xx_matlab.h']]], - ['adc_5fsmpr1_5fsmp15_5f1_329',['ADC_SMPR1_SMP15_1',['../group___peripheral___registers___bits___definition.html#gab978e10b7dcfe6c1b88dd4fef50498ac',1,'stm32f407xx_matlab.h']]], - ['adc_5fsmpr1_5fsmp15_5f2_330',['ADC_SMPR1_SMP15_2',['../group___peripheral___registers___bits___definition.html#ga045285e1c5ab9ae570e37fe627b0e117',1,'stm32f407xx_matlab.h']]], - ['adc_5fsmpr1_5fsmp15_5fmsk_331',['ADC_SMPR1_SMP15_Msk',['../group___peripheral___registers___bits___definition.html#ga2bd307278f68d42fad28c9a549cee495',1,'stm32f407xx_matlab.h']]], - ['adc_5fsmpr1_5fsmp15_5fpos_332',['ADC_SMPR1_SMP15_Pos',['../group___peripheral___registers___bits___definition.html#gaf4a9dac15edbf7dbc2fa521e57cd0929',1,'stm32f407xx_matlab.h']]], - ['adc_5fsmpr1_5fsmp16_333',['ADC_SMPR1_SMP16',['../group___peripheral___registers___bits___definition.html#ga2925d05347e46e9c6a970214fa76bbec',1,'stm32f407xx_matlab.h']]], - ['adc_5fsmpr1_5fsmp16_5f0_334',['ADC_SMPR1_SMP16_0',['../group___peripheral___registers___bits___definition.html#gae1a7d0ef695bd2017bcda3949f0134be',1,'stm32f407xx_matlab.h']]], - ['adc_5fsmpr1_5fsmp16_5f1_335',['ADC_SMPR1_SMP16_1',['../group___peripheral___registers___bits___definition.html#ga793ff2f46f51e1d485a9bd728687bf15',1,'stm32f407xx_matlab.h']]], - ['adc_5fsmpr1_5fsmp16_5f2_336',['ADC_SMPR1_SMP16_2',['../group___peripheral___registers___bits___definition.html#gade321fdbf74f830e54951ccfca285686',1,'stm32f407xx_matlab.h']]], - ['adc_5fsmpr1_5fsmp16_5fmsk_337',['ADC_SMPR1_SMP16_Msk',['../group___peripheral___registers___bits___definition.html#gabbf22b25f0b78dab59b1f8d2e1bbceeb',1,'stm32f407xx_matlab.h']]], - ['adc_5fsmpr1_5fsmp16_5fpos_338',['ADC_SMPR1_SMP16_Pos',['../group___peripheral___registers___bits___definition.html#gad299a50233bbf403f796758fbce28a27',1,'stm32f407xx_matlab.h']]], - ['adc_5fsmpr1_5fsmp17_339',['ADC_SMPR1_SMP17',['../group___peripheral___registers___bits___definition.html#ga9867370ecef7b99c32b8ecb44ad9e581',1,'stm32f407xx_matlab.h']]], - ['adc_5fsmpr1_5fsmp17_5f0_340',['ADC_SMPR1_SMP17_0',['../group___peripheral___registers___bits___definition.html#ga42b004d74f288cb191bfc6a327f94480',1,'stm32f407xx_matlab.h']]], - ['adc_5fsmpr1_5fsmp17_5f1_341',['ADC_SMPR1_SMP17_1',['../group___peripheral___registers___bits___definition.html#ga3ac4c21586d6a353c208a5175906ecc1',1,'stm32f407xx_matlab.h']]], - ['adc_5fsmpr1_5fsmp17_5f2_342',['ADC_SMPR1_SMP17_2',['../group___peripheral___registers___bits___definition.html#gac81ceec799a7da2def4f33339bd5e273',1,'stm32f407xx_matlab.h']]], - ['adc_5fsmpr1_5fsmp17_5fmsk_343',['ADC_SMPR1_SMP17_Msk',['../group___peripheral___registers___bits___definition.html#gac9ca754667b1437b01fb0da560d36e10',1,'stm32f407xx_matlab.h']]], - ['adc_5fsmpr1_5fsmp17_5fpos_344',['ADC_SMPR1_SMP17_Pos',['../group___peripheral___registers___bits___definition.html#ga5f0af7a5db877331daa8770222909d4d',1,'stm32f407xx_matlab.h']]], - ['adc_5fsmpr1_5fsmp18_345',['ADC_SMPR1_SMP18',['../group___peripheral___registers___bits___definition.html#gac3c7d84a92899d950de236fe9d14df2c',1,'stm32f407xx_matlab.h']]], - ['adc_5fsmpr1_5fsmp18_5f0_346',['ADC_SMPR1_SMP18_0',['../group___peripheral___registers___bits___definition.html#ga6862168bb7688638764defc72120716b',1,'stm32f407xx_matlab.h']]], - ['adc_5fsmpr1_5fsmp18_5f1_347',['ADC_SMPR1_SMP18_1',['../group___peripheral___registers___bits___definition.html#ga72a01c59a0a785b18235641b36735090',1,'stm32f407xx_matlab.h']]], - ['adc_5fsmpr1_5fsmp18_5f2_348',['ADC_SMPR1_SMP18_2',['../group___peripheral___registers___bits___definition.html#gaec1addc9c417b4b7693768817b058059',1,'stm32f407xx_matlab.h']]], - ['adc_5fsmpr1_5fsmp18_5fmsk_349',['ADC_SMPR1_SMP18_Msk',['../group___peripheral___registers___bits___definition.html#ga4c670627d1f5c73fae79914ba1f04475',1,'stm32f407xx_matlab.h']]], - ['adc_5fsmpr1_5fsmp18_5fpos_350',['ADC_SMPR1_SMP18_Pos',['../group___peripheral___registers___bits___definition.html#ga6d49003824f10f93348569e720865899',1,'stm32f407xx_matlab.h']]], - ['adc_5fsmpr2_5fsmp0_351',['ADC_SMPR2_SMP0',['../group___peripheral___registers___bits___definition.html#ga5a13b3c652e5759e2d8bc7e38889bc5e',1,'stm32f407xx_matlab.h']]], - ['adc_5fsmpr2_5fsmp0_5f0_352',['ADC_SMPR2_SMP0_0',['../group___peripheral___registers___bits___definition.html#ga1bde59fce56980a59a3dfdb0da7ebe0c',1,'stm32f407xx_matlab.h']]], - ['adc_5fsmpr2_5fsmp0_5f1_353',['ADC_SMPR2_SMP0_1',['../group___peripheral___registers___bits___definition.html#ga1d5b6e025d8e70767914c144793b93e6',1,'stm32f407xx_matlab.h']]], - ['adc_5fsmpr2_5fsmp0_5f2_354',['ADC_SMPR2_SMP0_2',['../group___peripheral___registers___bits___definition.html#ga361de56c56c45834fc837df349f155dc',1,'stm32f407xx_matlab.h']]], - ['adc_5fsmpr2_5fsmp0_5fmsk_355',['ADC_SMPR2_SMP0_Msk',['../group___peripheral___registers___bits___definition.html#gaa46fc7c440c9969355b4fd542b9a6447',1,'stm32f407xx_matlab.h']]], - ['adc_5fsmpr2_5fsmp0_5fpos_356',['ADC_SMPR2_SMP0_Pos',['../group___peripheral___registers___bits___definition.html#ga8509ff53fa9599b3e2756b0029701a12',1,'stm32f407xx_matlab.h']]], - ['adc_5fsmpr2_5fsmp1_357',['ADC_SMPR2_SMP1',['../group___peripheral___registers___bits___definition.html#ga5b85dd0b1708cdf1bf403b07ad51da36',1,'stm32f407xx_matlab.h']]], - ['adc_5fsmpr2_5fsmp1_5f0_358',['ADC_SMPR2_SMP1_0',['../group___peripheral___registers___bits___definition.html#gaaa99de1a2d2bbe8921353114d03cb7f6',1,'stm32f407xx_matlab.h']]], - ['adc_5fsmpr2_5fsmp1_5f1_359',['ADC_SMPR2_SMP1_1',['../group___peripheral___registers___bits___definition.html#gaf6ceb41e5e3cb6ae7da28070bc0b07d2',1,'stm32f407xx_matlab.h']]], - ['adc_5fsmpr2_5fsmp1_5f2_360',['ADC_SMPR2_SMP1_2',['../group___peripheral___registers___bits___definition.html#ga8b9efc8f9488d389301c4a6f9ef4427a',1,'stm32f407xx_matlab.h']]], - ['adc_5fsmpr2_5fsmp1_5fmsk_361',['ADC_SMPR2_SMP1_Msk',['../group___peripheral___registers___bits___definition.html#ga39b8904a2aa672a622471712507c39c7',1,'stm32f407xx_matlab.h']]], - ['adc_5fsmpr2_5fsmp1_5fpos_362',['ADC_SMPR2_SMP1_Pos',['../group___peripheral___registers___bits___definition.html#ga3a7d6076724526beda6cb481eb3ea5e7',1,'stm32f407xx_matlab.h']]], - ['adc_5fsmpr2_5fsmp2_363',['ADC_SMPR2_SMP2',['../group___peripheral___registers___bits___definition.html#gaea6e1e298372596bcdcdf93e763b3683',1,'stm32f407xx_matlab.h']]], - ['adc_5fsmpr2_5fsmp2_5f0_364',['ADC_SMPR2_SMP2_0',['../group___peripheral___registers___bits___definition.html#ga97e2ac0d4d8afb3aa0b4c09c8fa1d018',1,'stm32f407xx_matlab.h']]], - ['adc_5fsmpr2_5fsmp2_5f1_365',['ADC_SMPR2_SMP2_1',['../group___peripheral___registers___bits___definition.html#ga83fe79e3e10b689a209dc5a724f89199',1,'stm32f407xx_matlab.h']]], - ['adc_5fsmpr2_5fsmp2_5f2_366',['ADC_SMPR2_SMP2_2',['../group___peripheral___registers___bits___definition.html#gad580d376e0a0bcb34183a6d6735b3122',1,'stm32f407xx_matlab.h']]], - ['adc_5fsmpr2_5fsmp2_5fmsk_367',['ADC_SMPR2_SMP2_Msk',['../group___peripheral___registers___bits___definition.html#gaf47f3ef6dad5ad4ab6a70f7256cce7bf',1,'stm32f407xx_matlab.h']]], - ['adc_5fsmpr2_5fsmp2_5fpos_368',['ADC_SMPR2_SMP2_Pos',['../group___peripheral___registers___bits___definition.html#ga8f3716b7531126383d5f4f26c55b17a0',1,'stm32f407xx_matlab.h']]], - ['adc_5fsmpr2_5fsmp3_369',['ADC_SMPR2_SMP3',['../group___peripheral___registers___bits___definition.html#ga081c3d61e5311a11cb046d56630e1fd0',1,'stm32f407xx_matlab.h']]], - ['adc_5fsmpr2_5fsmp3_5f0_370',['ADC_SMPR2_SMP3_0',['../group___peripheral___registers___bits___definition.html#gaa1679a42f67ca4b9b9496dd6000fec01',1,'stm32f407xx_matlab.h']]], - ['adc_5fsmpr2_5fsmp3_5f1_371',['ADC_SMPR2_SMP3_1',['../group___peripheral___registers___bits___definition.html#ga1bf92b0a67dcec9b3c325d58e7e517b0',1,'stm32f407xx_matlab.h']]], - ['adc_5fsmpr2_5fsmp3_5f2_372',['ADC_SMPR2_SMP3_2',['../group___peripheral___registers___bits___definition.html#ga40682268fa8534bd369eb64a329bdf46',1,'stm32f407xx_matlab.h']]], - ['adc_5fsmpr2_5fsmp3_5fmsk_373',['ADC_SMPR2_SMP3_Msk',['../group___peripheral___registers___bits___definition.html#ga305cad42f0aae469c0f63a79de6bbf2a',1,'stm32f407xx_matlab.h']]], - ['adc_5fsmpr2_5fsmp3_5fpos_374',['ADC_SMPR2_SMP3_Pos',['../group___peripheral___registers___bits___definition.html#ga46bbf950a5d9f629a48b7f9faebbcc55',1,'stm32f407xx_matlab.h']]], - ['adc_5fsmpr2_5fsmp4_375',['ADC_SMPR2_SMP4',['../group___peripheral___registers___bits___definition.html#gaeab838fcf0aace87b2163b96d208bb64',1,'stm32f407xx_matlab.h']]], - ['adc_5fsmpr2_5fsmp4_5f0_376',['ADC_SMPR2_SMP4_0',['../group___peripheral___registers___bits___definition.html#gae4123bce64dc4f1831f992b09d6db4f2',1,'stm32f407xx_matlab.h']]], - ['adc_5fsmpr2_5fsmp4_5f1_377',['ADC_SMPR2_SMP4_1',['../group___peripheral___registers___bits___definition.html#gad3edf57b459804d17d5a588dd446c763',1,'stm32f407xx_matlab.h']]], - ['adc_5fsmpr2_5fsmp4_5f2_378',['ADC_SMPR2_SMP4_2',['../group___peripheral___registers___bits___definition.html#gac2a2fd74311c4ffcaed4a8d1a3be2245',1,'stm32f407xx_matlab.h']]], - ['adc_5fsmpr2_5fsmp4_5fmsk_379',['ADC_SMPR2_SMP4_Msk',['../group___peripheral___registers___bits___definition.html#ga41d006fba68f1e84ff3bd0ec21f61233',1,'stm32f407xx_matlab.h']]], - ['adc_5fsmpr2_5fsmp4_5fpos_380',['ADC_SMPR2_SMP4_Pos',['../group___peripheral___registers___bits___definition.html#gad8fe44c9dc72211b7255b4355462f680',1,'stm32f407xx_matlab.h']]], - ['adc_5fsmpr2_5fsmp5_381',['ADC_SMPR2_SMP5',['../group___peripheral___registers___bits___definition.html#ga9500281fa740994b9cfa6a7df8227849',1,'stm32f407xx_matlab.h']]], - ['adc_5fsmpr2_5fsmp5_5f0_382',['ADC_SMPR2_SMP5_0',['../group___peripheral___registers___bits___definition.html#ga22dd2b1695a4e7a4b1d4ec2b8e244ffc',1,'stm32f407xx_matlab.h']]], - ['adc_5fsmpr2_5fsmp5_5f1_383',['ADC_SMPR2_SMP5_1',['../group___peripheral___registers___bits___definition.html#gab4de4f6c62646be62d0710dc46eb5e88',1,'stm32f407xx_matlab.h']]], - ['adc_5fsmpr2_5fsmp5_5f2_384',['ADC_SMPR2_SMP5_2',['../group___peripheral___registers___bits___definition.html#ga6c19081d82f2c6478c6aefc207778e1e',1,'stm32f407xx_matlab.h']]], - ['adc_5fsmpr2_5fsmp5_5fmsk_385',['ADC_SMPR2_SMP5_Msk',['../group___peripheral___registers___bits___definition.html#ga9b8b4a18f347d72459aa84fd6a2629a8',1,'stm32f407xx_matlab.h']]], - ['adc_5fsmpr2_5fsmp5_5fpos_386',['ADC_SMPR2_SMP5_Pos',['../group___peripheral___registers___bits___definition.html#gafdd88f74dea228c26eeb5bcbd9513012',1,'stm32f407xx_matlab.h']]], - ['adc_5fsmpr2_5fsmp6_387',['ADC_SMPR2_SMP6',['../group___peripheral___registers___bits___definition.html#ga64cd99c27d07298913541dbdc31aa8ae',1,'stm32f407xx_matlab.h']]], - ['adc_5fsmpr2_5fsmp6_5f0_388',['ADC_SMPR2_SMP6_0',['../group___peripheral___registers___bits___definition.html#gadbebc0a7f368e5846408d768603d9b44',1,'stm32f407xx_matlab.h']]], - ['adc_5fsmpr2_5fsmp6_5f1_389',['ADC_SMPR2_SMP6_1',['../group___peripheral___registers___bits___definition.html#ga27f59166864f7cd0a5e8e6b4450e72d3',1,'stm32f407xx_matlab.h']]], - ['adc_5fsmpr2_5fsmp6_5f2_390',['ADC_SMPR2_SMP6_2',['../group___peripheral___registers___bits___definition.html#ga4139fac7e8ba3e604e35ba906880f909',1,'stm32f407xx_matlab.h']]], - ['adc_5fsmpr2_5fsmp6_5fmsk_391',['ADC_SMPR2_SMP6_Msk',['../group___peripheral___registers___bits___definition.html#ga63b337299939afb7336f2579bd3a727c',1,'stm32f407xx_matlab.h']]], - ['adc_5fsmpr2_5fsmp6_5fpos_392',['ADC_SMPR2_SMP6_Pos',['../group___peripheral___registers___bits___definition.html#gac7ad6181795d9407c499d6c5d87c7056',1,'stm32f407xx_matlab.h']]], - ['adc_5fsmpr2_5fsmp7_393',['ADC_SMPR2_SMP7',['../group___peripheral___registers___bits___definition.html#ga6ec6ee971fc8b2d1890858df94a5c500',1,'stm32f407xx_matlab.h']]], - ['adc_5fsmpr2_5fsmp7_5f0_394',['ADC_SMPR2_SMP7_0',['../group___peripheral___registers___bits___definition.html#ga6f30003c59ab6c232d73aa446c77651a',1,'stm32f407xx_matlab.h']]], - ['adc_5fsmpr2_5fsmp7_5f1_395',['ADC_SMPR2_SMP7_1',['../group___peripheral___registers___bits___definition.html#ga0c8708fc97082257b43fa4534c721068',1,'stm32f407xx_matlab.h']]], - ['adc_5fsmpr2_5fsmp7_5f2_396',['ADC_SMPR2_SMP7_2',['../group___peripheral___registers___bits___definition.html#ga2e42897bdc25951a73bac060a7a065ca',1,'stm32f407xx_matlab.h']]], - ['adc_5fsmpr2_5fsmp7_5fmsk_397',['ADC_SMPR2_SMP7_Msk',['../group___peripheral___registers___bits___definition.html#ga8f8b7b73b7ac647dd48d114f683afc55',1,'stm32f407xx_matlab.h']]], - ['adc_5fsmpr2_5fsmp7_5fpos_398',['ADC_SMPR2_SMP7_Pos',['../group___peripheral___registers___bits___definition.html#gaeb68d22ee2b8a9a6238d08b3c5f0417c',1,'stm32f407xx_matlab.h']]], - ['adc_5fsmpr2_5fsmp8_399',['ADC_SMPR2_SMP8',['../group___peripheral___registers___bits___definition.html#ga0695c289e658b772070a7f29797e9cc3',1,'stm32f407xx_matlab.h']]], - ['adc_5fsmpr2_5fsmp8_5f0_400',['ADC_SMPR2_SMP8_0',['../group___peripheral___registers___bits___definition.html#gab5f1d2290107eda2dfee33810779b0f6',1,'stm32f407xx_matlab.h']]], - ['adc_5fsmpr2_5fsmp8_5f1_401',['ADC_SMPR2_SMP8_1',['../group___peripheral___registers___bits___definition.html#gabb9ce9d71f989bad0ed686caf4dd5250',1,'stm32f407xx_matlab.h']]], - ['adc_5fsmpr2_5fsmp8_5f2_402',['ADC_SMPR2_SMP8_2',['../group___peripheral___registers___bits___definition.html#ga3756c6141f55c60da0bcd4d599e7d60d',1,'stm32f407xx_matlab.h']]], - ['adc_5fsmpr2_5fsmp8_5fmsk_403',['ADC_SMPR2_SMP8_Msk',['../group___peripheral___registers___bits___definition.html#ga0390786a9cb491305c18fe615acfd13f',1,'stm32f407xx_matlab.h']]], - ['adc_5fsmpr2_5fsmp8_5fpos_404',['ADC_SMPR2_SMP8_Pos',['../group___peripheral___registers___bits___definition.html#gab45620208290dbe572341227dd291c5d',1,'stm32f407xx_matlab.h']]], - ['adc_5fsmpr2_5fsmp9_405',['ADC_SMPR2_SMP9',['../group___peripheral___registers___bits___definition.html#ga5348f83daaa38060702d7b9cfe2e4005',1,'stm32f407xx_matlab.h']]], - ['adc_5fsmpr2_5fsmp9_5f0_406',['ADC_SMPR2_SMP9_0',['../group___peripheral___registers___bits___definition.html#ga892f18c89fbaafc74b7d67db74b41423',1,'stm32f407xx_matlab.h']]], - ['adc_5fsmpr2_5fsmp9_5f1_407',['ADC_SMPR2_SMP9_1',['../group___peripheral___registers___bits___definition.html#ga3a6949e61c5845a7ff2331b64cb579bc',1,'stm32f407xx_matlab.h']]], - ['adc_5fsmpr2_5fsmp9_5f2_408',['ADC_SMPR2_SMP9_2',['../group___peripheral___registers___bits___definition.html#ga070135017850599b1e19766c6aa31cd1',1,'stm32f407xx_matlab.h']]], - ['adc_5fsmpr2_5fsmp9_5fmsk_409',['ADC_SMPR2_SMP9_Msk',['../group___peripheral___registers___bits___definition.html#ga1b124d3d088448db3cd97db242b125cf',1,'stm32f407xx_matlab.h']]], - ['adc_5fsmpr2_5fsmp9_5fpos_410',['ADC_SMPR2_SMP9_Pos',['../group___peripheral___registers___bits___definition.html#ga39bc8143f781965172d5e6e023529abc',1,'stm32f407xx_matlab.h']]], - ['adc_5fsqr1_5fl_411',['ADC_SQR1_L',['../group___peripheral___registers___bits___definition.html#gae68a19a18d72f6d87c6f2b8cc8bfc6dc',1,'stm32f407xx_matlab.h']]], - ['adc_5fsqr1_5fl_5f0_412',['ADC_SQR1_L_0',['../group___peripheral___registers___bits___definition.html#ga00ec56fbf232492ec12c954e27d03c6c',1,'stm32f407xx_matlab.h']]], - ['adc_5fsqr1_5fl_5f1_413',['ADC_SQR1_L_1',['../group___peripheral___registers___bits___definition.html#ga52708c6570da08c295603e5b52461ecd',1,'stm32f407xx_matlab.h']]], - ['adc_5fsqr1_5fl_5f2_414',['ADC_SQR1_L_2',['../group___peripheral___registers___bits___definition.html#ga8b914eeb128157c4acf6f6b9a4be5558',1,'stm32f407xx_matlab.h']]], - ['adc_5fsqr1_5fl_5f3_415',['ADC_SQR1_L_3',['../group___peripheral___registers___bits___definition.html#gaffdd34daa55da53d18055417ae895c47',1,'stm32f407xx_matlab.h']]], - ['adc_5fsqr1_5fl_5fmsk_416',['ADC_SQR1_L_Msk',['../group___peripheral___registers___bits___definition.html#gac11490606e7ecc26985deed271f7ff57',1,'stm32f407xx_matlab.h']]], - ['adc_5fsqr1_5fl_5fpos_417',['ADC_SQR1_L_Pos',['../group___peripheral___registers___bits___definition.html#ga58db108cdbc75716bedb45ba9fabe727',1,'stm32f407xx_matlab.h']]], - ['adc_5fsqr1_5fsq13_418',['ADC_SQR1_SQ13',['../group___peripheral___registers___bits___definition.html#ga1ae1998c0dd11275958e7347a92852fc',1,'stm32f407xx_matlab.h']]], - ['adc_5fsqr1_5fsq13_5f0_419',['ADC_SQR1_SQ13_0',['../group___peripheral___registers___bits___definition.html#ga40d24ddd458198e7731d5abf9d15fc08',1,'stm32f407xx_matlab.h']]], - ['adc_5fsqr1_5fsq13_5f1_420',['ADC_SQR1_SQ13_1',['../group___peripheral___registers___bits___definition.html#gaccdca8b0f3cab9f62ae2ffbb9c30546f',1,'stm32f407xx_matlab.h']]], - ['adc_5fsqr1_5fsq13_5f2_421',['ADC_SQR1_SQ13_2',['../group___peripheral___registers___bits___definition.html#ga37e8723bfdc43da0b86e40a49b78c9ad',1,'stm32f407xx_matlab.h']]], - ['adc_5fsqr1_5fsq13_5f3_422',['ADC_SQR1_SQ13_3',['../group___peripheral___registers___bits___definition.html#ga412374f7ce1f62ee187c819391898778',1,'stm32f407xx_matlab.h']]], - ['adc_5fsqr1_5fsq13_5f4_423',['ADC_SQR1_SQ13_4',['../group___peripheral___registers___bits___definition.html#ga05ca5e303f844f512c9a9cb5df9a1028',1,'stm32f407xx_matlab.h']]], - ['adc_5fsqr1_5fsq13_5fmsk_424',['ADC_SQR1_SQ13_Msk',['../group___peripheral___registers___bits___definition.html#ga08e9c7dc59718bbfbf1a3db4eba22f86',1,'stm32f407xx_matlab.h']]], - ['adc_5fsqr1_5fsq13_5fpos_425',['ADC_SQR1_SQ13_Pos',['../group___peripheral___registers___bits___definition.html#ga881b03d9be116c006dab51c6c46aee4e',1,'stm32f407xx_matlab.h']]], - ['adc_5fsqr1_5fsq14_426',['ADC_SQR1_SQ14',['../group___peripheral___registers___bits___definition.html#gab0251199146cb3d0d2c1c0608fbca585',1,'stm32f407xx_matlab.h']]], - ['adc_5fsqr1_5fsq14_5f0_427',['ADC_SQR1_SQ14_0',['../group___peripheral___registers___bits___definition.html#gacde3a6d9e94aa1c2399e335911fd6212',1,'stm32f407xx_matlab.h']]], - ['adc_5fsqr1_5fsq14_5f1_428',['ADC_SQR1_SQ14_1',['../group___peripheral___registers___bits___definition.html#ga1bc61e4d3ea200e1fc3e9d621ebbd2b4',1,'stm32f407xx_matlab.h']]], - ['adc_5fsqr1_5fsq14_5f2_429',['ADC_SQR1_SQ14_2',['../group___peripheral___registers___bits___definition.html#gaeea616e444521cd58c5d8d574c47ccf0',1,'stm32f407xx_matlab.h']]], - ['adc_5fsqr1_5fsq14_5f3_430',['ADC_SQR1_SQ14_3',['../group___peripheral___registers___bits___definition.html#ga0e0c9439633fb5c67c8f2138c9d2efae',1,'stm32f407xx_matlab.h']]], - ['adc_5fsqr1_5fsq14_5f4_431',['ADC_SQR1_SQ14_4',['../group___peripheral___registers___bits___definition.html#gaea22b4dd0fbb26d2a0babbc483778b0e',1,'stm32f407xx_matlab.h']]], - ['adc_5fsqr1_5fsq14_5fmsk_432',['ADC_SQR1_SQ14_Msk',['../group___peripheral___registers___bits___definition.html#gac16eaf610307245433e59aee05bfe254',1,'stm32f407xx_matlab.h']]], - ['adc_5fsqr1_5fsq14_5fpos_433',['ADC_SQR1_SQ14_Pos',['../group___peripheral___registers___bits___definition.html#ga6ca511d19962e09ad2294844874a00de',1,'stm32f407xx_matlab.h']]], - ['adc_5fsqr1_5fsq15_434',['ADC_SQR1_SQ15',['../group___peripheral___registers___bits___definition.html#ga23222c591c6d926f7a741bc9346f1d8f',1,'stm32f407xx_matlab.h']]], - ['adc_5fsqr1_5fsq15_5f0_435',['ADC_SQR1_SQ15_0',['../group___peripheral___registers___bits___definition.html#gacbfbc70f67ce1d8f227e17a7f19c123b',1,'stm32f407xx_matlab.h']]], - ['adc_5fsqr1_5fsq15_5f1_436',['ADC_SQR1_SQ15_1',['../group___peripheral___registers___bits___definition.html#gac00e343ff0dd8f1f29e897148e3e070a',1,'stm32f407xx_matlab.h']]], - ['adc_5fsqr1_5fsq15_5f2_437',['ADC_SQR1_SQ15_2',['../group___peripheral___registers___bits___definition.html#gab63443b0c5a2eca60a8c9714f6f31c03',1,'stm32f407xx_matlab.h']]], - ['adc_5fsqr1_5fsq15_5f3_438',['ADC_SQR1_SQ15_3',['../group___peripheral___registers___bits___definition.html#gadf676d45ba227a2dc641b2afadfa7852',1,'stm32f407xx_matlab.h']]], - ['adc_5fsqr1_5fsq15_5f4_439',['ADC_SQR1_SQ15_4',['../group___peripheral___registers___bits___definition.html#ga7dbc07d0904f60abcc15827ccab1a8c2',1,'stm32f407xx_matlab.h']]], - ['adc_5fsqr1_5fsq15_5fmsk_440',['ADC_SQR1_SQ15_Msk',['../group___peripheral___registers___bits___definition.html#ga2dcdc56b5476a5cbed60e74735574831',1,'stm32f407xx_matlab.h']]], - ['adc_5fsqr1_5fsq15_5fpos_441',['ADC_SQR1_SQ15_Pos',['../group___peripheral___registers___bits___definition.html#ga21eb97eeceffa9eb2cd4aea37af8b13f',1,'stm32f407xx_matlab.h']]], - ['adc_5fsqr1_5fsq16_442',['ADC_SQR1_SQ16',['../group___peripheral___registers___bits___definition.html#gafecb33099669a080cede6ce0236389e7',1,'stm32f407xx_matlab.h']]], - ['adc_5fsqr1_5fsq16_5f0_443',['ADC_SQR1_SQ16_0',['../group___peripheral___registers___bits___definition.html#ga3404d0bf04b8561bf93455d968b77ea9',1,'stm32f407xx_matlab.h']]], - ['adc_5fsqr1_5fsq16_5f1_444',['ADC_SQR1_SQ16_1',['../group___peripheral___registers___bits___definition.html#ga7ea6af777051f14be5cf166dd4ae69d1',1,'stm32f407xx_matlab.h']]], - ['adc_5fsqr1_5fsq16_5f2_445',['ADC_SQR1_SQ16_2',['../group___peripheral___registers___bits___definition.html#gaf59e4a113346ac3daf6829c3321444f5',1,'stm32f407xx_matlab.h']]], - ['adc_5fsqr1_5fsq16_5f3_446',['ADC_SQR1_SQ16_3',['../group___peripheral___registers___bits___definition.html#ga6052517e5fcab3f58c42b59fb3ffee55',1,'stm32f407xx_matlab.h']]], - ['adc_5fsqr1_5fsq16_5f4_447',['ADC_SQR1_SQ16_4',['../group___peripheral___registers___bits___definition.html#ga7af851b5898b4421958e7a100602c8cd',1,'stm32f407xx_matlab.h']]], - ['adc_5fsqr1_5fsq16_5fmsk_448',['ADC_SQR1_SQ16_Msk',['../group___peripheral___registers___bits___definition.html#gabddb795f3c7a42aba72d3961e19cc7fc',1,'stm32f407xx_matlab.h']]], - ['adc_5fsqr1_5fsq16_5fpos_449',['ADC_SQR1_SQ16_Pos',['../group___peripheral___registers___bits___definition.html#ga175666e476ceceebaa0f3267aeb6ea09',1,'stm32f407xx_matlab.h']]], - ['adc_5fsqr2_5fsq10_450',['ADC_SQR2_SQ10',['../group___peripheral___registers___bits___definition.html#ga22e474b65f217ac21137b1d3f3cbb6bb',1,'stm32f407xx_matlab.h']]], - ['adc_5fsqr2_5fsq10_5f0_451',['ADC_SQR2_SQ10_0',['../group___peripheral___registers___bits___definition.html#gab5a36056dbfce703d22387432ac12262',1,'stm32f407xx_matlab.h']]], - ['adc_5fsqr2_5fsq10_5f1_452',['ADC_SQR2_SQ10_1',['../group___peripheral___registers___bits___definition.html#ga09a1de734fe67156af26edf3b8a61044',1,'stm32f407xx_matlab.h']]], - ['adc_5fsqr2_5fsq10_5f2_453',['ADC_SQR2_SQ10_2',['../group___peripheral___registers___bits___definition.html#ga3b1d6ad0a40e7171d40a964b361d1eb9',1,'stm32f407xx_matlab.h']]], - ['adc_5fsqr2_5fsq10_5f3_454',['ADC_SQR2_SQ10_3',['../group___peripheral___registers___bits___definition.html#ga24d63e60eabad897aa9b19dbe56da71e',1,'stm32f407xx_matlab.h']]], - ['adc_5fsqr2_5fsq10_5f4_455',['ADC_SQR2_SQ10_4',['../group___peripheral___registers___bits___definition.html#ga7df899f74116e6cb3205af2767840cfb',1,'stm32f407xx_matlab.h']]], - ['adc_5fsqr2_5fsq10_5fmsk_456',['ADC_SQR2_SQ10_Msk',['../group___peripheral___registers___bits___definition.html#ga8a438cb8cfa6116018759eca4d2c2fbb',1,'stm32f407xx_matlab.h']]], - ['adc_5fsqr2_5fsq10_5fpos_457',['ADC_SQR2_SQ10_Pos',['../group___peripheral___registers___bits___definition.html#ga48d10816801feffec06a224ee726a97e',1,'stm32f407xx_matlab.h']]], - ['adc_5fsqr2_5fsq11_458',['ADC_SQR2_SQ11',['../group___peripheral___registers___bits___definition.html#ga7bf491b9c1542fb0d0b83fc96166362e',1,'stm32f407xx_matlab.h']]], - ['adc_5fsqr2_5fsq11_5f0_459',['ADC_SQR2_SQ11_0',['../group___peripheral___registers___bits___definition.html#ga5bc91fec2ef468c5d39d19beda9ecd3e',1,'stm32f407xx_matlab.h']]], - ['adc_5fsqr2_5fsq11_5f1_460',['ADC_SQR2_SQ11_1',['../group___peripheral___registers___bits___definition.html#ga3e142789d2bd0584480e923754544ff5',1,'stm32f407xx_matlab.h']]], - ['adc_5fsqr2_5fsq11_5f2_461',['ADC_SQR2_SQ11_2',['../group___peripheral___registers___bits___definition.html#gad6b844fe698c16437e91c9e05a367a4c',1,'stm32f407xx_matlab.h']]], - ['adc_5fsqr2_5fsq11_5f3_462',['ADC_SQR2_SQ11_3',['../group___peripheral___registers___bits___definition.html#ga1a8127191e3c48f4e0952bdb5e196225',1,'stm32f407xx_matlab.h']]], - ['adc_5fsqr2_5fsq11_5f4_463',['ADC_SQR2_SQ11_4',['../group___peripheral___registers___bits___definition.html#ga5e8a39f645505ef84cb94bbc8d21b8e0',1,'stm32f407xx_matlab.h']]], - ['adc_5fsqr2_5fsq11_5fmsk_464',['ADC_SQR2_SQ11_Msk',['../group___peripheral___registers___bits___definition.html#ga0f72a350259ac99fdcda7a97eb6fe2a8',1,'stm32f407xx_matlab.h']]], - ['adc_5fsqr2_5fsq11_5fpos_465',['ADC_SQR2_SQ11_Pos',['../group___peripheral___registers___bits___definition.html#ga6148bba86967003cb581b42e6eaa29e5',1,'stm32f407xx_matlab.h']]], - ['adc_5fsqr2_5fsq12_466',['ADC_SQR2_SQ12',['../group___peripheral___registers___bits___definition.html#ga8731660b1710e63d5423cd31c11be184',1,'stm32f407xx_matlab.h']]], - ['adc_5fsqr2_5fsq12_5f0_467',['ADC_SQR2_SQ12_0',['../group___peripheral___registers___bits___definition.html#ga5b2da909e54f8f6f61bf2bd2cd3e93e0',1,'stm32f407xx_matlab.h']]], - ['adc_5fsqr2_5fsq12_5f1_468',['ADC_SQR2_SQ12_1',['../group___peripheral___registers___bits___definition.html#gab5930c4a07d594aa23bc868526b42601',1,'stm32f407xx_matlab.h']]], - ['adc_5fsqr2_5fsq12_5f2_469',['ADC_SQR2_SQ12_2',['../group___peripheral___registers___bits___definition.html#ga377805a21e7da2a66a3913a77bcc1e66',1,'stm32f407xx_matlab.h']]], - ['adc_5fsqr2_5fsq12_5f3_470',['ADC_SQR2_SQ12_3',['../group___peripheral___registers___bits___definition.html#ga2e3b45cac9aeb68d33b31a0914692857',1,'stm32f407xx_matlab.h']]], - ['adc_5fsqr2_5fsq12_5f4_471',['ADC_SQR2_SQ12_4',['../group___peripheral___registers___bits___definition.html#ga6043d31a6cb9bd7c1542c3d41eb296c7',1,'stm32f407xx_matlab.h']]], - ['adc_5fsqr2_5fsq12_5fmsk_472',['ADC_SQR2_SQ12_Msk',['../group___peripheral___registers___bits___definition.html#ga3a8e8248a0fe8bbf43de3e6f06984a85',1,'stm32f407xx_matlab.h']]], - ['adc_5fsqr2_5fsq12_5fpos_473',['ADC_SQR2_SQ12_Pos',['../group___peripheral___registers___bits___definition.html#gac2490bed33c8e2523dd8fd0f48cf1ab4',1,'stm32f407xx_matlab.h']]], - ['adc_5fsqr2_5fsq7_474',['ADC_SQR2_SQ7',['../group___peripheral___registers___bits___definition.html#gaa9f66f702fc124040956117f20ef8df4',1,'stm32f407xx_matlab.h']]], - ['adc_5fsqr2_5fsq7_5f0_475',['ADC_SQR2_SQ7_0',['../group___peripheral___registers___bits___definition.html#ga12bbc822c10582a80f7e20a11038ce96',1,'stm32f407xx_matlab.h']]], - ['adc_5fsqr2_5fsq7_5f1_476',['ADC_SQR2_SQ7_1',['../group___peripheral___registers___bits___definition.html#ga3d0d7daf3b6db6ff4fa382495f6127c6',1,'stm32f407xx_matlab.h']]], - ['adc_5fsqr2_5fsq7_5f2_477',['ADC_SQR2_SQ7_2',['../group___peripheral___registers___bits___definition.html#ga74bda24f18a95261661a944cecf45a52',1,'stm32f407xx_matlab.h']]], - ['adc_5fsqr2_5fsq7_5f3_478',['ADC_SQR2_SQ7_3',['../group___peripheral___registers___bits___definition.html#ga2697675d008dda4e6a4905fc0f8d22af',1,'stm32f407xx_matlab.h']]], - ['adc_5fsqr2_5fsq7_5f4_479',['ADC_SQR2_SQ7_4',['../group___peripheral___registers___bits___definition.html#ga2c46dd0f30ef85094ca0cde2e8c00dac',1,'stm32f407xx_matlab.h']]], - ['adc_5fsqr2_5fsq7_5fmsk_480',['ADC_SQR2_SQ7_Msk',['../group___peripheral___registers___bits___definition.html#gaee89c65015de91a4fc92b922bcef81fe',1,'stm32f407xx_matlab.h']]], - ['adc_5fsqr2_5fsq7_5fpos_481',['ADC_SQR2_SQ7_Pos',['../group___peripheral___registers___bits___definition.html#ga589d869844063982a6fc59daa2d49aee',1,'stm32f407xx_matlab.h']]], - ['adc_5fsqr2_5fsq8_482',['ADC_SQR2_SQ8',['../group___peripheral___registers___bits___definition.html#ga308ec58a8d20dcb3a348c30c332a0a8e',1,'stm32f407xx_matlab.h']]], - ['adc_5fsqr2_5fsq8_5f0_483',['ADC_SQR2_SQ8_0',['../group___peripheral___registers___bits___definition.html#ga858717a28d6c26612ad4ced46863ba13',1,'stm32f407xx_matlab.h']]], - ['adc_5fsqr2_5fsq8_5f1_484',['ADC_SQR2_SQ8_1',['../group___peripheral___registers___bits___definition.html#ga2d06168a43b4845409f2fb9193ee474a',1,'stm32f407xx_matlab.h']]], - ['adc_5fsqr2_5fsq8_5f2_485',['ADC_SQR2_SQ8_2',['../group___peripheral___registers___bits___definition.html#gaa5eaea65d6719a8199639ec30bb8a07b',1,'stm32f407xx_matlab.h']]], - ['adc_5fsqr2_5fsq8_5f3_486',['ADC_SQR2_SQ8_3',['../group___peripheral___registers___bits___definition.html#ga23e22da18926dd107adc69282a445412',1,'stm32f407xx_matlab.h']]], - ['adc_5fsqr2_5fsq8_5f4_487',['ADC_SQR2_SQ8_4',['../group___peripheral___registers___bits___definition.html#gacadd092f31f37bb129065be175673c63',1,'stm32f407xx_matlab.h']]], - ['adc_5fsqr2_5fsq8_5fmsk_488',['ADC_SQR2_SQ8_Msk',['../group___peripheral___registers___bits___definition.html#ga9152be162b9262d76b7a59b4c0f25956',1,'stm32f407xx_matlab.h']]], - ['adc_5fsqr2_5fsq8_5fpos_489',['ADC_SQR2_SQ8_Pos',['../group___peripheral___registers___bits___definition.html#gaab83e34058c7c593c58b4fc8f7d27084',1,'stm32f407xx_matlab.h']]], - ['adc_5fsqr2_5fsq9_490',['ADC_SQR2_SQ9',['../group___peripheral___registers___bits___definition.html#gaf5d91ecfc3d40cc6b1960544e526eb91',1,'stm32f407xx_matlab.h']]], - ['adc_5fsqr2_5fsq9_5f0_491',['ADC_SQR2_SQ9_0',['../group___peripheral___registers___bits___definition.html#gace032949b436d9af8a20ea10a349d55b',1,'stm32f407xx_matlab.h']]], - ['adc_5fsqr2_5fsq9_5f1_492',['ADC_SQR2_SQ9_1',['../group___peripheral___registers___bits___definition.html#ga5cf43f1c5de0e73d6159fabc3681b891',1,'stm32f407xx_matlab.h']]], - ['adc_5fsqr2_5fsq9_5f2_493',['ADC_SQR2_SQ9_2',['../group___peripheral___registers___bits___definition.html#ga3389c07a9de242151ffa434908fee39d',1,'stm32f407xx_matlab.h']]], - ['adc_5fsqr2_5fsq9_5f3_494',['ADC_SQR2_SQ9_3',['../group___peripheral___registers___bits___definition.html#ga13f30540b9f2d33640ea7d9652dc3c71',1,'stm32f407xx_matlab.h']]], - ['adc_5fsqr2_5fsq9_5f4_495',['ADC_SQR2_SQ9_4',['../group___peripheral___registers___bits___definition.html#ga910e5bda9852d49117b76b0d9f420ef2',1,'stm32f407xx_matlab.h']]], - ['adc_5fsqr2_5fsq9_5fmsk_496',['ADC_SQR2_SQ9_Msk',['../group___peripheral___registers___bits___definition.html#ga03bc5dff92603b8e5dfe5ac87552f40a',1,'stm32f407xx_matlab.h']]], - ['adc_5fsqr2_5fsq9_5fpos_497',['ADC_SQR2_SQ9_Pos',['../group___peripheral___registers___bits___definition.html#ga8585b815abcb076901d4f1a4c8d6c80b',1,'stm32f407xx_matlab.h']]], - ['adc_5fsqr3_5fsq1_498',['ADC_SQR3_SQ1',['../group___peripheral___registers___bits___definition.html#ga52491114e8394648559004f3bae718d9',1,'stm32f407xx_matlab.h']]], - ['adc_5fsqr3_5fsq1_5f0_499',['ADC_SQR3_SQ1_0',['../group___peripheral___registers___bits___definition.html#ga53d3bb1c8bb48c7bcb0f7409db69f7b4',1,'stm32f407xx_matlab.h']]], - ['adc_5fsqr3_5fsq1_5f1_500',['ADC_SQR3_SQ1_1',['../group___peripheral___registers___bits___definition.html#gaddb9af3a3b23a103fbc34c4f422fd2af',1,'stm32f407xx_matlab.h']]], - ['adc_5fsqr3_5fsq1_5f2_501',['ADC_SQR3_SQ1_2',['../group___peripheral___registers___bits___definition.html#gadf591f43a15c0c2c5afae2598b8f2afc',1,'stm32f407xx_matlab.h']]], - ['adc_5fsqr3_5fsq1_5f3_502',['ADC_SQR3_SQ1_3',['../group___peripheral___registers___bits___definition.html#ga05cfde0ef0e6a8dd6311f5cd7a806556',1,'stm32f407xx_matlab.h']]], - ['adc_5fsqr3_5fsq1_5f4_503',['ADC_SQR3_SQ1_4',['../group___peripheral___registers___bits___definition.html#ga9981512f99a6c41ce107a9428d9cfdd0',1,'stm32f407xx_matlab.h']]], - ['adc_5fsqr3_5fsq1_5fmsk_504',['ADC_SQR3_SQ1_Msk',['../group___peripheral___registers___bits___definition.html#ga158e02c01bc2ee902ff9d4ca8c767184',1,'stm32f407xx_matlab.h']]], - ['adc_5fsqr3_5fsq1_5fpos_505',['ADC_SQR3_SQ1_Pos',['../group___peripheral___registers___bits___definition.html#gac825474ea3bcec005557a9fe47526a4f',1,'stm32f407xx_matlab.h']]], - ['adc_5fsqr3_5fsq2_506',['ADC_SQR3_SQ2',['../group___peripheral___registers___bits___definition.html#ga60637fb25c099f8da72a8a36211f7a8c',1,'stm32f407xx_matlab.h']]], - ['adc_5fsqr3_5fsq2_5f0_507',['ADC_SQR3_SQ2_0',['../group___peripheral___registers___bits___definition.html#gaede0302eb64f023913c7a9e588d77937',1,'stm32f407xx_matlab.h']]], - ['adc_5fsqr3_5fsq2_5f1_508',['ADC_SQR3_SQ2_1',['../group___peripheral___registers___bits___definition.html#ga158ab7429a864634a46c81fdb51d7508',1,'stm32f407xx_matlab.h']]], - ['adc_5fsqr3_5fsq2_5f2_509',['ADC_SQR3_SQ2_2',['../group___peripheral___registers___bits___definition.html#gae729e21d590271c59c0d653300d5581c',1,'stm32f407xx_matlab.h']]], - ['adc_5fsqr3_5fsq2_5f3_510',['ADC_SQR3_SQ2_3',['../group___peripheral___registers___bits___definition.html#gaf65c33275178a8777fa8fed8a01f7389',1,'stm32f407xx_matlab.h']]], - ['adc_5fsqr3_5fsq2_5f4_511',['ADC_SQR3_SQ2_4',['../group___peripheral___registers___bits___definition.html#ga990aeb689b7cc8f0bebb3dd6af7b27a6',1,'stm32f407xx_matlab.h']]], - ['adc_5fsqr3_5fsq2_5fmsk_512',['ADC_SQR3_SQ2_Msk',['../group___peripheral___registers___bits___definition.html#ga1e5a7d30b953796355d6e134aefa7fc3',1,'stm32f407xx_matlab.h']]], - ['adc_5fsqr3_5fsq2_5fpos_513',['ADC_SQR3_SQ2_Pos',['../group___peripheral___registers___bits___definition.html#ga92d0269f674151ea3e8e38760675099c',1,'stm32f407xx_matlab.h']]], - ['adc_5fsqr3_5fsq3_514',['ADC_SQR3_SQ3',['../group___peripheral___registers___bits___definition.html#ga601f21b7c1e571fb8c5ff310aca021e1',1,'stm32f407xx_matlab.h']]], - ['adc_5fsqr3_5fsq3_5f0_515',['ADC_SQR3_SQ3_0',['../group___peripheral___registers___bits___definition.html#ga7fd2c154b5852cb08ce60b4adfa36313',1,'stm32f407xx_matlab.h']]], - ['adc_5fsqr3_5fsq3_5f1_516',['ADC_SQR3_SQ3_1',['../group___peripheral___registers___bits___definition.html#ga214580377dd3a424ad819f14f6b025d4',1,'stm32f407xx_matlab.h']]], - ['adc_5fsqr3_5fsq3_5f2_517',['ADC_SQR3_SQ3_2',['../group___peripheral___registers___bits___definition.html#gabae2353b109c9cda2a176ea1f44db4fe',1,'stm32f407xx_matlab.h']]], - ['adc_5fsqr3_5fsq3_5f3_518',['ADC_SQR3_SQ3_3',['../group___peripheral___registers___bits___definition.html#ga7d2f00d3372bd1d64bf4eb2271277ab0',1,'stm32f407xx_matlab.h']]], - ['adc_5fsqr3_5fsq3_5f4_519',['ADC_SQR3_SQ3_4',['../group___peripheral___registers___bits___definition.html#ga5279e505b1a59b223f30e5be139d5042',1,'stm32f407xx_matlab.h']]], - ['adc_5fsqr3_5fsq3_5fmsk_520',['ADC_SQR3_SQ3_Msk',['../group___peripheral___registers___bits___definition.html#gaea87ead7a01cad5a05b3212eb1b5ce35',1,'stm32f407xx_matlab.h']]], - ['adc_5fsqr3_5fsq3_5fpos_521',['ADC_SQR3_SQ3_Pos',['../group___peripheral___registers___bits___definition.html#ga70ca80250d365fa475d9afed6d03ca8b',1,'stm32f407xx_matlab.h']]], - ['adc_5fsqr3_5fsq4_522',['ADC_SQR3_SQ4',['../group___peripheral___registers___bits___definition.html#ga3fc43f70bb3c67c639678b91d852390b',1,'stm32f407xx_matlab.h']]], - ['adc_5fsqr3_5fsq4_5f0_523',['ADC_SQR3_SQ4_0',['../group___peripheral___registers___bits___definition.html#gab2a501b20cf758a7353efcb3f95a3a93',1,'stm32f407xx_matlab.h']]], - ['adc_5fsqr3_5fsq4_5f1_524',['ADC_SQR3_SQ4_1',['../group___peripheral___registers___bits___definition.html#gaffafa27fd561e4c7d419e3f665d80f2c',1,'stm32f407xx_matlab.h']]], - ['adc_5fsqr3_5fsq4_5f2_525',['ADC_SQR3_SQ4_2',['../group___peripheral___registers___bits___definition.html#gad0251fa70e400ee74f442d8fba2b1afb',1,'stm32f407xx_matlab.h']]], - ['adc_5fsqr3_5fsq4_5f3_526',['ADC_SQR3_SQ4_3',['../group___peripheral___registers___bits___definition.html#ga3dc48c3c6b304517261486d8a63637ae',1,'stm32f407xx_matlab.h']]], - ['adc_5fsqr3_5fsq4_5f4_527',['ADC_SQR3_SQ4_4',['../group___peripheral___registers___bits___definition.html#gafe23b9e640df96ca84eab4b6b4f44083',1,'stm32f407xx_matlab.h']]], - ['adc_5fsqr3_5fsq4_5fmsk_528',['ADC_SQR3_SQ4_Msk',['../group___peripheral___registers___bits___definition.html#ga2f6ee00d27c507e9b088b1f6b825ab55',1,'stm32f407xx_matlab.h']]], - ['adc_5fsqr3_5fsq4_5fpos_529',['ADC_SQR3_SQ4_Pos',['../group___peripheral___registers___bits___definition.html#ga01430f2ace37e28c2c79a923632d094a',1,'stm32f407xx_matlab.h']]], - ['adc_5fsqr3_5fsq5_530',['ADC_SQR3_SQ5',['../group___peripheral___registers___bits___definition.html#gaae841d68049442e4568b86322ed4be6f',1,'stm32f407xx_matlab.h']]], - ['adc_5fsqr3_5fsq5_5f0_531',['ADC_SQR3_SQ5_0',['../group___peripheral___registers___bits___definition.html#gaa1de9fc24755b715c700c6442f4a396b',1,'stm32f407xx_matlab.h']]], - ['adc_5fsqr3_5fsq5_5f1_532',['ADC_SQR3_SQ5_1',['../group___peripheral___registers___bits___definition.html#ga3f704feb58eecb39bc7f199577064172',1,'stm32f407xx_matlab.h']]], - ['adc_5fsqr3_5fsq5_5f2_533',['ADC_SQR3_SQ5_2',['../group___peripheral___registers___bits___definition.html#ga88a7994f637a75d105cc5975b154c373',1,'stm32f407xx_matlab.h']]], - ['adc_5fsqr3_5fsq5_5f3_534',['ADC_SQR3_SQ5_3',['../group___peripheral___registers___bits___definition.html#ga31c6fce8f01e75c68124124061f67f0e',1,'stm32f407xx_matlab.h']]], - ['adc_5fsqr3_5fsq5_5f4_535',['ADC_SQR3_SQ5_4',['../group___peripheral___registers___bits___definition.html#ga6b0cad694c068ea8874b6504bd6ae885',1,'stm32f407xx_matlab.h']]], - ['adc_5fsqr3_5fsq5_5fmsk_536',['ADC_SQR3_SQ5_Msk',['../group___peripheral___registers___bits___definition.html#gaade1e4985264c9bc583a6803cc54e7cf',1,'stm32f407xx_matlab.h']]], - ['adc_5fsqr3_5fsq5_5fpos_537',['ADC_SQR3_SQ5_Pos',['../group___peripheral___registers___bits___definition.html#ga834a04bad696f9b1a363e828441e5d6a',1,'stm32f407xx_matlab.h']]], - ['adc_5fsqr3_5fsq6_538',['ADC_SQR3_SQ6',['../group___peripheral___registers___bits___definition.html#ga723792274b16b342d16d6a02fce74ba6',1,'stm32f407xx_matlab.h']]], - ['adc_5fsqr3_5fsq6_5f0_539',['ADC_SQR3_SQ6_0',['../group___peripheral___registers___bits___definition.html#ga91b8b5293abd0601c543c13a0b53b335',1,'stm32f407xx_matlab.h']]], - ['adc_5fsqr3_5fsq6_5f1_540',['ADC_SQR3_SQ6_1',['../group___peripheral___registers___bits___definition.html#gab29847362a613b43eeeda6db758d781e',1,'stm32f407xx_matlab.h']]], - ['adc_5fsqr3_5fsq6_5f2_541',['ADC_SQR3_SQ6_2',['../group___peripheral___registers___bits___definition.html#gaa92c8ea1bfb42ed80622770ae2dc41ab',1,'stm32f407xx_matlab.h']]], - ['adc_5fsqr3_5fsq6_5f3_542',['ADC_SQR3_SQ6_3',['../group___peripheral___registers___bits___definition.html#gaed2d7edb11fb84b02c175acff305a922',1,'stm32f407xx_matlab.h']]], - ['adc_5fsqr3_5fsq6_5f4_543',['ADC_SQR3_SQ6_4',['../group___peripheral___registers___bits___definition.html#ga78f9e51811549a6797ecfe1468def4ff',1,'stm32f407xx_matlab.h']]], - ['adc_5fsqr3_5fsq6_5fmsk_544',['ADC_SQR3_SQ6_Msk',['../group___peripheral___registers___bits___definition.html#gab01b48333516c485500fcf186f861bf3',1,'stm32f407xx_matlab.h']]], - ['adc_5fsqr3_5fsq6_5fpos_545',['ADC_SQR3_SQ6_Pos',['../group___peripheral___registers___bits___definition.html#ga972ec9142a3fdc4969c91b9743372a9c',1,'stm32f407xx_matlab.h']]], - ['adc_5fsr_5fawd_546',['ADC_SR_AWD',['../group___peripheral___registers___bits___definition.html#ga8b7f27694281e4cad956da567e5583b2',1,'stm32f407xx_matlab.h']]], - ['adc_5fsr_5fawd_5fmsk_547',['ADC_SR_AWD_Msk',['../group___peripheral___registers___bits___definition.html#gad1f5cef448ce47b4bf2e3d71ed7debf3',1,'stm32f407xx_matlab.h']]], - ['adc_5fsr_5fawd_5fpos_548',['ADC_SR_AWD_Pos',['../group___peripheral___registers___bits___definition.html#gaa1c2e0f2c5f57df27447e2c4055d1a3b',1,'stm32f407xx_matlab.h']]], - ['adc_5fsr_5feoc_549',['ADC_SR_EOC',['../group___peripheral___registers___bits___definition.html#ga3dc295c5253743aeb2cda582953b7b53',1,'stm32f407xx_matlab.h']]], - ['adc_5fsr_5feoc_5fmsk_550',['ADC_SR_EOC_Msk',['../group___peripheral___registers___bits___definition.html#ga370d791b736d2b691df00221dbd3041a',1,'stm32f407xx_matlab.h']]], - ['adc_5fsr_5feoc_5fpos_551',['ADC_SR_EOC_Pos',['../group___peripheral___registers___bits___definition.html#ga4a468d077f5722ce97ae2d5d907b6fc5',1,'stm32f407xx_matlab.h']]], - ['adc_5fsr_5fjeoc_552',['ADC_SR_JEOC',['../group___peripheral___registers___bits___definition.html#gabc9f07589bb1a4e398781df372389b56',1,'stm32f407xx_matlab.h']]], - ['adc_5fsr_5fjeoc_5fmsk_553',['ADC_SR_JEOC_Msk',['../group___peripheral___registers___bits___definition.html#ga2e5d245721d37e76b53660c9d2094000',1,'stm32f407xx_matlab.h']]], - ['adc_5fsr_5fjeoc_5fpos_554',['ADC_SR_JEOC_Pos',['../group___peripheral___registers___bits___definition.html#gaf45ea3ec6ba328fe2eb3d57cc061fcf6',1,'stm32f407xx_matlab.h']]], - ['adc_5fsr_5fjstrt_555',['ADC_SR_JSTRT',['../group___peripheral___registers___bits___definition.html#ga7340a01ffec051c06e80a037eee58a14',1,'stm32f407xx_matlab.h']]], - ['adc_5fsr_5fjstrt_5fmsk_556',['ADC_SR_JSTRT_Msk',['../group___peripheral___registers___bits___definition.html#ga72dec61b0a9eaf8380b4ba19e8bd3750',1,'stm32f407xx_matlab.h']]], - ['adc_5fsr_5fjstrt_5fpos_557',['ADC_SR_JSTRT_Pos',['../group___peripheral___registers___bits___definition.html#ga66b7ea4bf6dc5c2b0406d52f5c728716',1,'stm32f407xx_matlab.h']]], - ['adc_5fsr_5fovr_558',['ADC_SR_OVR',['../group___peripheral___registers___bits___definition.html#ga1e5211d5e3e53cdedf4d9d6fe4ce2a45',1,'stm32f407xx_matlab.h']]], - ['adc_5fsr_5fovr_5fmsk_559',['ADC_SR_OVR_Msk',['../group___peripheral___registers___bits___definition.html#ga3f963f57c46a01cd982b88b3a71574eb',1,'stm32f407xx_matlab.h']]], - ['adc_5fsr_5fovr_5fpos_560',['ADC_SR_OVR_Pos',['../group___peripheral___registers___bits___definition.html#ga50c7432adead5e587179e4c67713f193',1,'stm32f407xx_matlab.h']]], - ['adc_5fsr_5fstrt_561',['ADC_SR_STRT',['../group___peripheral___registers___bits___definition.html#ga45eb11ad986d8220cde9fa47a91ed222',1,'stm32f407xx_matlab.h']]], - ['adc_5fsr_5fstrt_5fmsk_562',['ADC_SR_STRT_Msk',['../group___peripheral___registers___bits___definition.html#gaabffe4cd9e85d28f2e29d16acf305c48',1,'stm32f407xx_matlab.h']]], - ['adc_5fsr_5fstrt_5fpos_563',['ADC_SR_STRT_Pos',['../group___peripheral___registers___bits___definition.html#ga21a6327becffbd34525a0960e7be990e',1,'stm32f407xx_matlab.h']]], - ['adc_5ftypedef_564',['ADC_TypeDef',['../struct_a_d_c___type_def.html',1,'']]], - ['adr_565',['ADR',['../group___c_m_s_i_s__core___debug_functions.html#ga72572af6d5dece4947453aeabd52575f',1,'SCB_Type']]], - ['afr_566',['AFR',['../group___c_m_s_i_s___device.html#gab67c1158c04450d19ad483dcd2192e43',1,'GPIO_TypeDef']]], - ['afsr_567',['AFSR',['../group___c_m_s_i_s__core___debug_functions.html#ga3ef0057e48fdef798f2ee12125a80d9f',1,'SCB_Type']]], - ['ahb1enr_568',['AHB1ENR',['../group___c_m_s_i_s___device.html#ga1e9c75b06c99d0611535f38c7b4aa845',1,'RCC_TypeDef']]], - ['ahb1lpenr_569',['AHB1LPENR',['../group___c_m_s_i_s___device.html#gaae70b1922167eb58d564cb82d39fd10b',1,'RCC_TypeDef']]], - ['ahb1periph_5fbase_570',['AHB1PERIPH_BASE',['../group___peripheral__memory__map.html#ga811a9a4ca17f0a50354a9169541d56c4',1,'stm32f407xx_matlab.h']]], - ['ahb1rstr_571',['AHB1RSTR',['../group___c_m_s_i_s___device.html#ga46c20c598e9e12f919f0ea47ebcbc90f',1,'RCC_TypeDef']]], - ['ahb2enr_572',['AHB2ENR',['../group___c_m_s_i_s___device.html#ga5e92ed32c33c92e7ebf6919400ad535b',1,'RCC_TypeDef']]], - ['ahb2lpenr_573',['AHB2LPENR',['../group___c_m_s_i_s___device.html#ga2b30982547fae7d545d260312771b5c9',1,'RCC_TypeDef']]], - ['ahb2periph_5fbase_574',['AHB2PERIPH_BASE',['../group___peripheral__memory__map.html#gaeedaa71d22a1948492365e2cd26cfd46',1,'stm32f407xx_matlab.h']]], - ['ahb2rstr_575',['AHB2RSTR',['../group___c_m_s_i_s___device.html#ga78a5aa9dd5694c48a7d8e66888a46450',1,'RCC_TypeDef']]], - ['ahb3enr_576',['AHB3ENR',['../group___c_m_s_i_s___device.html#gacdaa650fcd63730825479f6e8f70d4c0',1,'RCC_TypeDef']]], - ['ahb3lpenr_577',['AHB3LPENR',['../group___c_m_s_i_s___device.html#ga2ff82b9bf0231645108965aa0febd766',1,'RCC_TypeDef']]], - ['ahb3rstr_578',['AHB3RSTR',['../group___c_m_s_i_s___device.html#ga28560c5bfeb45326ea7f2019dba57bea',1,'RCC_TypeDef']]], - ['ahbpresctable_579',['AHBPrescTable',['../group___s_t_m32_f4xx___system___exported__types.html#ga6e1d9cd666f0eacbfde31e9932a93466',1,'system_stm32f4xx.h']]], - ['aircr_580',['AIRCR',['../group___c_m_s_i_s__core___debug_functions.html#ga9b6ccd9c0c0865f8facad77ea37240b0',1,'SCB_Type']]], - ['alrmar_581',['ALRMAR',['../group___c_m_s_i_s___device.html#gac005b1a5bc52634d5a34578cc9d2c3f6',1,'RTC_TypeDef']]], - ['alrmassr_582',['ALRMASSR',['../group___c_m_s_i_s___device.html#ga61282fa74cede526af85fd9d20513646',1,'RTC_TypeDef']]], - ['alrmbr_583',['ALRMBR',['../group___c_m_s_i_s___device.html#ga4e513deb9f58a138ad9f317cc5a3555d',1,'RTC_TypeDef']]], - ['alrmbssr_584',['ALRMBSSR',['../group___c_m_s_i_s___device.html#ga4ef7499da5d5beb1cfc81f7be057a7b2',1,'RTC_TypeDef']]], - ['and_20control_20registers_585',['Status and Control Registers',['../group___c_m_s_i_s___c_o_r_e.html',1,'']]], - ['and_20instructions_20reference_586',['Functions and Instructions Reference',['../group___c_m_s_i_s___core___function_interface.html',1,'']]], - ['and_20trace_20dwt_587',['Data Watchpoint and Trace (DWT)',['../group___c_m_s_i_s___d_w_t.html',1,'']]], - ['and_20type_20definitions_588',['Defines and Type Definitions',['../group___c_m_s_i_s__core__register.html',1,'']]], - ['apb1enr_589',['APB1ENR',['../group___c_m_s_i_s___device.html#gac88901e2eb35079b7b58a185e6bf554c',1,'RCC_TypeDef']]], - ['apb1fz_590',['APB1FZ',['../group___c_m_s_i_s___device.html#ga5eaefc557573ae7bdc632ef6b6d574b5',1,'DBGMCU_TypeDef']]], - ['apb1lpenr_591',['APB1LPENR',['../group___c_m_s_i_s___device.html#gad85a9951a7be79fe08ffc90f796f071b',1,'RCC_TypeDef']]], - ['apb1periph_5fbase_592',['APB1PERIPH_BASE',['../group___peripheral__memory__map.html#ga45666d911f39addd4c8c0a0ac3388cfb',1,'stm32f407xx_matlab.h']]], - ['apb1rstr_593',['APB1RSTR',['../group___c_m_s_i_s___device.html#ga7da5d372374bc59e9b9af750b01d6a78',1,'RCC_TypeDef']]], - ['apb2enr_594',['APB2ENR',['../group___c_m_s_i_s___device.html#gacc7bb47dddd2d94de124f74886d919be',1,'RCC_TypeDef']]], - ['apb2fz_595',['APB2FZ',['../group___c_m_s_i_s___device.html#ga4628a8c32f97ef93b15b2b503ef90c75',1,'DBGMCU_TypeDef']]], - ['apb2lpenr_596',['APB2LPENR',['../group___c_m_s_i_s___device.html#gaba51c57f9506e14a6f5983526c78943b',1,'RCC_TypeDef']]], - ['apb2periph_5fbase_597',['APB2PERIPH_BASE',['../group___peripheral__memory__map.html#ga25b99d6065f1c8f751e78f43ade652cb',1,'stm32f407xx_matlab.h']]], - ['apb2rstr_598',['APB2RSTR',['../group___c_m_s_i_s___device.html#gab2c5389c9ff4ac188cd498b8f7170968',1,'RCC_TypeDef']]], - ['apbpresctable_599',['APBPrescTable',['../group___s_t_m32_f4xx___system___exported__types.html#ga5b4f8b768465842cf854a8f993b375e9',1,'system_stm32f4xx.h']]], - ['apsr_5fc_5fmsk_600',['APSR_C_Msk',['../group___c_m_s_i_s___c_o_r_e.html#ga6d47803fbad455bc10bd1ce59f2f335d',1,'core_cm4_matlab.h']]], - ['apsr_5fc_5fpos_601',['APSR_C_Pos',['../group___c_m_s_i_s___c_o_r_e.html#ga6cf72aa6f09a168f9e5beda1a4a887b9',1,'core_cm4_matlab.h']]], - ['apsr_5fge_5fmsk_602',['APSR_GE_Msk',['../group___c_m_s_i_s___c_o_r_e.html#ga8a3ecbc0ea2029462b0f4ce50e227db1',1,'core_cm4_matlab.h']]], - ['apsr_5fge_5fpos_603',['APSR_GE_Pos',['../group___c_m_s_i_s___c_o_r_e.html#ga722cb42b5c75af3e8909fac6fd40dfdc',1,'core_cm4_matlab.h']]], - ['apsr_5fn_5fmsk_604',['APSR_N_Msk',['../group___c_m_s_i_s___c_o_r_e.html#gadbc2cf55a026f661b53fadfcf822cef1',1,'core_cm4_matlab.h']]], - ['apsr_5fn_5fpos_605',['APSR_N_Pos',['../group___c_m_s_i_s___c_o_r_e.html#gac469528d210043c7bd3f12f0e6824766',1,'core_cm4_matlab.h']]], - ['apsr_5fq_5fmsk_606',['APSR_Q_Msk',['../group___c_m_s_i_s___c_o_r_e.html#ga90ffd4ec4149c2f5dd7747c1533fb002',1,'core_cm4_matlab.h']]], - ['apsr_5fq_5fpos_607',['APSR_Q_Pos',['../group___c_m_s_i_s___c_o_r_e.html#ga298749e176f12827328bb7b92a6b2411',1,'core_cm4_matlab.h']]], - ['apsr_5ftype_608',['APSR_Type',['../union_a_p_s_r___type.html',1,'']]], - ['apsr_5fv_5fmsk_609',['APSR_V_Msk',['../group___c_m_s_i_s___c_o_r_e.html#ga33305d6701356bff6890b315fe8b5489',1,'core_cm4_matlab.h']]], - ['apsr_5fv_5fpos_610',['APSR_V_Pos',['../group___c_m_s_i_s___c_o_r_e.html#gac62830f67679ccd11658c4172c3e6ea7',1,'core_cm4_matlab.h']]], - ['apsr_5fz_5fmsk_611',['APSR_Z_Msk',['../group___c_m_s_i_s___c_o_r_e.html#ga1deb4d1aa72bb83d1f79329406f15711',1,'core_cm4_matlab.h']]], - ['apsr_5fz_5fpos_612',['APSR_Z_Pos',['../group___c_m_s_i_s___c_o_r_e.html#ga3661286d108b1aca308d7445685eae3a',1,'core_cm4_matlab.h']]], - ['arg_613',['ARG',['../group___c_m_s_i_s___device.html#ga07d4e63efcbde252c667e64a8d818aa9',1,'SDIO_TypeDef']]], - ['arm_5fdefines_2eh_614',['arm_defines.h',['../arm__defines_8h.html',1,'']]], - ['arr_615',['ARR',['../group___c_m_s_i_s___device.html#gaf17f19bb4aeea3cc14fa73dfa7772cb8',1,'TIM_TypeDef']]], - ['atomic_5fclear_5fbit_616',['ATOMIC_CLEAR_BIT',['../group___exported__macro.html#ga08dfef58d3b054b80745eda49e8907fb',1,'stm32f4xx.h']]], - ['atomic_5fclearh_5fbit_617',['ATOMIC_CLEARH_BIT',['../group___exported__macro.html#ga72150176ac8514f3a9f71b354d344661',1,'stm32f4xx.h']]], - ['atomic_5fmodify_5freg_618',['ATOMIC_MODIFY_REG',['../group___exported__macro.html#ga89dc36b64605a58fd1666d76b51bde1c',1,'stm32f4xx.h']]], - ['atomic_5fmodifyh_5freg_619',['ATOMIC_MODIFYH_REG',['../group___exported__macro.html#ga8774e17ec273484ebb30efd3f9307f3a',1,'stm32f4xx.h']]], - ['atomic_5fset_5fbit_620',['ATOMIC_SET_BIT',['../group___exported__macro.html#ga5daccb3b4245b833e81ff60fd1f4cf80',1,'stm32f4xx.h']]], - ['atomic_5fseth_5fbit_621',['ATOMIC_SETH_BIT',['../group___exported__macro.html#ga567c489b25ec989c6ffcda6e1a49c4c2',1,'stm32f4xx.h']]] + ['adc_4',['adc',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#gac69e5457edf5f5639c4532688de406ae',1,'stm32f4xx_periph_registers.c']]], + ['adc1_5',['adc1',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#gaf1cc5fa4068a793827866bc4be7e3799',1,'stm32f4xx_periph_registers.c']]], + ['adc123_5fcommon_6',['adc123_common',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#gad98be8090528df1e3edb79ec46438b0a',1,'stm32f4xx_periph_registers.c']]], + ['adc2_7',['adc2',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#gaa94271247e5f041f9097ef16d6450c68',1,'stm32f4xx_periph_registers.c']]], + ['adc3_8',['adc3',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga6f330240512375fb7e4e23ba73e4b612',1,'stm32f4xx_periph_registers.c']]] ]; diff --git a/DOCS/html/search/all_10.js b/DOCS/html/search/all_10.js index 069393a..32db009 100644 --- a/DOCS/html/search/all_10.js +++ b/DOCS/html/search/all_10.js @@ -1,130 +1,54 @@ var searchData= [ - ['package_5fbase_0',['PACKAGE_BASE',['../group___peripheral__memory__map.html#ga88fc8a2912bd1ac72c6eddb456f0b096',1,'stm32f407xx_matlab.h']]], - ['par_1',['PAR',['../group___c_m_s_i_s___device.html#gaef55be3d948c22dd32a97e8d4f8761fd',1,'DMA_Stream_TypeDef']]], - ['patt2_2',['PATT2',['../group___c_m_s_i_s___device.html#ga9c1bc909ec5ed32df45444488ea6668b',1,'FSMC_Bank2_3_TypeDef']]], - ['patt3_3',['PATT3',['../group___c_m_s_i_s___device.html#gaba03fea9c1bb2242d963e29f1b94d25e',1,'FSMC_Bank2_3_TypeDef']]], - ['patt4_4',['PATT4',['../group___c_m_s_i_s___device.html#ga955cad1aab7fb2d5b6e216cb29b5e7e2',1,'FSMC_Bank4_TypeDef']]], - ['pcr2_5',['PCR2',['../group___c_m_s_i_s___device.html#gab0cb1d704ee64c62ad5be55522a2683a',1,'FSMC_Bank2_3_TypeDef']]], - ['pcr3_6',['PCR3',['../group___c_m_s_i_s___device.html#ga73861fa74b83973fa1b5f92735c042ef',1,'FSMC_Bank2_3_TypeDef']]], - ['pcr4_7',['PCR4',['../group___c_m_s_i_s___device.html#ga2f02e7acfbd7e549ede84633215eb6a1',1,'FSMC_Bank4_TypeDef']]], - ['pcsr_8',['PCSR',['../group___c_m_s_i_s__core___debug_functions.html#ga72e52fffe9ac6af0ee15877e2d5dac41',1,'DWT_Type']]], - ['pendsv_5firqn_9',['PendSV_IRQn',['../group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a03c3cc89984928816d81793fc7bce4a2',1,'stm32f407xx_matlab.h']]], - ['periph_5fbase_10',['PERIPH_BASE',['../group___c_m_s_i_s___device.html#ga535f5001cfe9967fb7040cd5b081d944',1,'_memory::PERIPH_BASE'],['../group___peripheral__memory__map.html#ga9171f49478fa86d932f89e78e73b88b0',1,'PERIPH_BASE: stm32f407xx_matlab.h']]], - ['periph_5fbase_5fshift_11',['PERIPH_BASE_SHIFT',['../group___peripheral__memory__map.html#ga1294c8e27eb23b591c5195504e4dfd23',1,'stm32f407xx_matlab.h']]], - ['periph_5fbb_5fbase_12',['PERIPH_BB_BASE',['../group___c_m_s_i_s___device.html#ga9fbcd0d73c2b2229b9f95743f280382c',1,'_memory::PERIPH_BB_BASE'],['../group___peripheral__memory__map.html#gaed7efc100877000845c236ccdc9e144a',1,'PERIPH_BB_BASE: stm32f407xx_matlab.h']]], - ['periph_5fbb_5fbase_5fshift_13',['PERIPH_BB_BASE_SHIFT',['../group___peripheral__memory__map.html#ga33c4df718741b5cb60ca3fffe8969672',1,'stm32f407xx_matlab.h']]], - ['periph_5fbb_5fsize_14',['PERIPH_BB_SIZE',['../group___peripheral__memory__map.html#ga16c53e8ec3bcf87a7d170220d774956c',1,'stm32f407xx_matlab.h']]], - ['periph_5fsize_15',['PERIPH_SIZE',['../group___peripheral__memory__map.html#gaf91d23524f40a61d32fea568949043d0',1,'stm32f407xx_matlab.h']]], - ['periph_5fvars_5ffor_5fdebug_16',['PERIPH_VARS_FOR_DEBUG',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html',1,'']]], - ['peripheral_5fdeclaration_17',['Peripheral_declaration',['../group___peripheral__declaration.html',1,'']]], - ['peripheral_5finterrupt_5fnumber_5fdefinition_18',['Peripheral_interrupt_number_definition',['../group___peripheral__interrupt__number__definition.html',1,'']]], - ['peripheral_5fmemory_5fmap_19',['Peripheral_memory_map',['../group___peripheral__memory__map.html',1,'']]], - ['peripheral_5fregisters_5fbits_5fdefinition_20',['Peripheral_Registers_Bits_Definition',['../group___peripheral___registers___bits___definition.html',1,'']]], - ['peripheral_5fregisters_5fstructures_21',['Peripheral_registers_structures',['../group___peripheral__registers__structures.html',1,'']]], - ['pfr_22',['PFR',['../group___c_m_s_i_s__core___debug_functions.html#ga602fa5eae6a772dbb09970d304e75690',1,'SCB_Type']]], - ['pid0_23',['PID0',['../group___c_m_s_i_s__core___debug_functions.html#ga6e3343cc3c4a8a5a6f14937882e9202a',1,'ITM_Type']]], - ['pid1_24',['PID1',['../group___c_m_s_i_s__core___debug_functions.html#gafa06959344f4991b00e6c545dd2fa30b',1,'ITM_Type']]], - ['pid2_25',['PID2',['../group___c_m_s_i_s__core___debug_functions.html#ga63db39f871596d28e69c283288ea2eba',1,'ITM_Type']]], - ['pid3_26',['PID3',['../group___c_m_s_i_s__core___debug_functions.html#gac2d006eed52ba550a309e5f61ed9c401',1,'ITM_Type']]], - ['pid4_27',['PID4',['../group___c_m_s_i_s__core___debug_functions.html#ga4c002e97cda2375d7421ad6415b6a02f',1,'ITM_Type']]], - ['pid5_28',['PID5',['../group___c_m_s_i_s__core___debug_functions.html#gac085b26f43fefeef9a4cf5c2af5e4a38',1,'ITM_Type']]], - ['pid6_29',['PID6',['../group___c_m_s_i_s__core___debug_functions.html#ga83ac5d00dee24cc7f805b5c147625593',1,'ITM_Type']]], - ['pid7_30',['PID7',['../group___c_m_s_i_s__core___debug_functions.html#gaf8aa73aeaf37bdf7dfd9f6c437ff2d2f',1,'ITM_Type']]], - ['pio4_31',['PIO4',['../group___c_m_s_i_s___device.html#gac53cd7a08093a4ae8f4de4bcff67a64f',1,'FSMC_Bank4_TypeDef']]], - ['pllcfgr_32',['PLLCFGR',['../group___c_m_s_i_s___device.html#gae6ff257862eba6b4b367feea786bf1fd',1,'RCC_TypeDef']]], - ['plli2scfgr_33',['PLLI2SCFGR',['../group___c_m_s_i_s___device.html#ga2d08d5f995ed77228eb56741184a1bb6',1,'RCC_TypeDef']]], - ['pmc_34',['PMC',['../group___c_m_s_i_s___device.html#ga2130abf1fefb63ce4c4b138fd8c9822a',1,'SYSCFG_TypeDef']]], - ['pmem2_35',['PMEM2',['../group___c_m_s_i_s___device.html#ga2e5a7a96de68a6612affa6df8c309c3d',1,'FSMC_Bank2_3_TypeDef']]], - ['pmem3_36',['PMEM3',['../group___c_m_s_i_s___device.html#gaba8981e4f06cfb3db7d9959242052f80',1,'FSMC_Bank2_3_TypeDef']]], - ['pmem4_37',['PMEM4',['../group___c_m_s_i_s___device.html#ga3f82cc749845fb0dd7dfa8121d96b663',1,'FSMC_Bank4_TypeDef']]], - ['point_20unit_20fpu_38',['Floating Point Unit (FPU)',['../group___c_m_s_i_s___f_p_u.html',1,'']]], - ['port_39',['PORT',['../group___c_m_s_i_s__core___debug_functions.html#ga1f5da59fa27aae410806b7dbe9e499c6',1,'ITM_Type']]], - ['port_20interface_20tpi_40',['Trace Port Interface (TPI)',['../group___c_m_s_i_s___t_p_i.html',1,'']]], - ['port_5fnumb_41',['PORT_NUMB',['../group___w_r_a_p_p_e_r___c_o_n_f.html#gab59d8303ff443409a05cef11e3e7176e',1,'mcu_wrapper_conf.h']]], - ['port_5fwidth_42',['PORT_WIDTH',['../group___w_r_a_p_p_e_r___c_o_n_f.html#ga80d9b6ce1525c1148d94c021f0b8c83e',1,'mcu_wrapper_conf.h']]], - ['position_5fval_43',['POSITION_VAL',['../group___exported__macro.html#ga47a8870d71d55cefb3df47cd8c815ec8',1,'stm32f4xx.h']]], - ['power_44',['POWER',['../group___c_m_s_i_s___device.html#ga65bff76f3af24c37708a1006d54720c7',1,'SDIO_TypeDef']]], - ['pr_45',['PR',['../group___c_m_s_i_s___device.html#gaf8d25514079514d38c104402f46470af',1,'EXTI_TypeDef::PR'],['../group___c_m_s_i_s___device.html#gaf8d25514079514d38c104402f46470af',1,'IWDG_TypeDef::PR']]], - ['prer_46',['PRER',['../group___c_m_s_i_s___device.html#gac9b4c6c5b29f3461ce3f875eea69f35b',1,'RTC_TypeDef']]], - ['psc_47',['PSC',['../group___c_m_s_i_s___device.html#ga9d4c753f09cbffdbe5c55008f0e8b180',1,'TIM_TypeDef']]], - ['ptpssir_48',['PTPSSIR',['../group___c_m_s_i_s___device.html#gaf34b7e8815984e272daa3f089014af4e',1,'ETH_TypeDef']]], - ['ptptsar_49',['PTPTSAR',['../group___c_m_s_i_s___device.html#ga8f47c0f21e22b98bbc2c9f3b6342fbb8',1,'ETH_TypeDef']]], - ['ptptscr_50',['PTPTSCR',['../group___c_m_s_i_s___device.html#gaa657aa42398bc8294976632d778b6db4',1,'ETH_TypeDef']]], - ['ptptshr_51',['PTPTSHR',['../group___c_m_s_i_s___device.html#ga1ebbda0d742e80ca3d53edfa3a95f627',1,'ETH_TypeDef']]], - ['ptptshur_52',['PTPTSHUR',['../group___c_m_s_i_s___device.html#gae8e4ef158db1de28bfd759e40677ba4c',1,'ETH_TypeDef']]], - ['ptptslr_53',['PTPTSLR',['../group___c_m_s_i_s___device.html#ga55c1058cd74dba0ed0cb8963684b9199',1,'ETH_TypeDef']]], - ['ptptslur_54',['PTPTSLUR',['../group___c_m_s_i_s___device.html#ga646bf44e807d10a09f980ace333d33ab',1,'ETH_TypeDef']]], - ['ptptssr_55',['PTPTSSR',['../group___c_m_s_i_s___device.html#gadca0624d09f2c72eee9807cea80a4d0c',1,'ETH_TypeDef']]], - ['ptptthr_56',['PTPTTHR',['../group___c_m_s_i_s___device.html#gaf90723c7aee9c32113a2667b0a5c69f1',1,'ETH_TypeDef']]], - ['ptpttlr_57',['PTPTTLR',['../group___c_m_s_i_s___device.html#ga28e7b0195ce457d20f585f6587fc1cb8',1,'ETH_TypeDef']]], - ['ptrdiff_5fmax_58',['PTRDIFF_MAX',['../stdint_8h.html#add2ef7bffac19cfdd1f4b5495409672f',1,'stdint.h']]], - ['ptrdiff_5fmin_59',['PTRDIFF_MIN',['../stdint_8h.html#ad9b88ba2fb858f98b50b38e49875d90e',1,'stdint.h']]], - ['pupdr_60',['PUPDR',['../group___c_m_s_i_s___device.html#gabeed38529bd7b8de082e490e5d4f1727',1,'GPIO_TypeDef']]], - ['pvd_5firqn_61',['PVD_IRQn',['../group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8ab0b51ffcc4dcf5661141b79c8e5bd924',1,'stm32f407xx_matlab.h']]], - ['pwr_62',['PWR',['../group___peripheral__declaration.html#ga04651c526497822a859942b928e57f8e',1,'stm32f407xx_matlab.h']]], - ['pwr_63',['pwr',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#gaba54a48e7552e8a1301cc87cdfcacfee',1,'stm32f4xx_periph_registers.c']]], - ['pwr_5fbase_64',['PWR_BASE',['../group___peripheral__memory__map.html#gac691ec23dace8b7a649a25acb110217a',1,'stm32f407xx_matlab.h']]], - ['pwr_5fcr_5fcsbf_65',['PWR_CR_CSBF',['../group___peripheral___registers___bits___definition.html#gab44484cacc35c80cf82eb011d6cbe13a',1,'stm32f407xx_matlab.h']]], - ['pwr_5fcr_5fcsbf_5fmsk_66',['PWR_CR_CSBF_Msk',['../group___peripheral___registers___bits___definition.html#ga8e25040e042ac06128a8cd5f858d8912',1,'stm32f407xx_matlab.h']]], - ['pwr_5fcr_5fcsbf_5fpos_67',['PWR_CR_CSBF_Pos',['../group___peripheral___registers___bits___definition.html#ga657c1dc4aa1d976d5cb8870ad7791a09',1,'stm32f407xx_matlab.h']]], - ['pwr_5fcr_5fcwuf_68',['PWR_CR_CWUF',['../group___peripheral___registers___bits___definition.html#ga3928de64f633b84770b1cfecea702fa7',1,'stm32f407xx_matlab.h']]], - ['pwr_5fcr_5fcwuf_5fmsk_69',['PWR_CR_CWUF_Msk',['../group___peripheral___registers___bits___definition.html#ga0b3f54b99913b0d6413df2b3d2e4790a',1,'stm32f407xx_matlab.h']]], - ['pwr_5fcr_5fcwuf_5fpos_70',['PWR_CR_CWUF_Pos',['../group___peripheral___registers___bits___definition.html#ga8725c4a6e67a667c4de1087c9639221f',1,'stm32f407xx_matlab.h']]], - ['pwr_5fcr_5fdbp_71',['PWR_CR_DBP',['../group___peripheral___registers___bits___definition.html#gaf5c65ab845794ef48f09faa2ee44f718',1,'stm32f407xx_matlab.h']]], - ['pwr_5fcr_5fdbp_5fmsk_72',['PWR_CR_DBP_Msk',['../group___peripheral___registers___bits___definition.html#gae4dc0f910dd014d87bdb0259f89de5f8',1,'stm32f407xx_matlab.h']]], - ['pwr_5fcr_5fdbp_5fpos_73',['PWR_CR_DBP_Pos',['../group___peripheral___registers___bits___definition.html#gaa3c90e817e3ccc0031b20014ef7d434e',1,'stm32f407xx_matlab.h']]], - ['pwr_5fcr_5ffpds_74',['PWR_CR_FPDS',['../group___peripheral___registers___bits___definition.html#gafc01f8b6d4bd0294f745fde6d8e57002',1,'stm32f407xx_matlab.h']]], - ['pwr_5fcr_5ffpds_5fmsk_75',['PWR_CR_FPDS_Msk',['../group___peripheral___registers___bits___definition.html#ga86e13d0b0eb3f05a11893752cc372677',1,'stm32f407xx_matlab.h']]], - ['pwr_5fcr_5ffpds_5fpos_76',['PWR_CR_FPDS_Pos',['../group___peripheral___registers___bits___definition.html#gaa7d09308d258629a5feea487cf8746c3',1,'stm32f407xx_matlab.h']]], - ['pwr_5fcr_5flpds_77',['PWR_CR_LPDS',['../group___peripheral___registers___bits___definition.html#ga3aeb8d6f2539b0a3a4b851aeba0eea66',1,'stm32f407xx_matlab.h']]], - ['pwr_5fcr_5flpds_5fmsk_78',['PWR_CR_LPDS_Msk',['../group___peripheral___registers___bits___definition.html#ga15a3e5d29f5816a97918b938fe9882d8',1,'stm32f407xx_matlab.h']]], - ['pwr_5fcr_5flpds_5fpos_79',['PWR_CR_LPDS_Pos',['../group___peripheral___registers___bits___definition.html#gaeff985ca572b03cb2b8fb57d72f04163',1,'stm32f407xx_matlab.h']]], - ['pwr_5fcr_5fpdds_80',['PWR_CR_PDDS',['../group___peripheral___registers___bits___definition.html#ga8c8075e98772470804c9e3fe74984115',1,'stm32f407xx_matlab.h']]], - ['pwr_5fcr_5fpdds_5fmsk_81',['PWR_CR_PDDS_Msk',['../group___peripheral___registers___bits___definition.html#gabc8e1dc6252707c24412500e6695fd05',1,'stm32f407xx_matlab.h']]], - ['pwr_5fcr_5fpdds_5fpos_82',['PWR_CR_PDDS_Pos',['../group___peripheral___registers___bits___definition.html#gaf1038bf2ac726320cfe05865bda0a07e',1,'stm32f407xx_matlab.h']]], - ['pwr_5fcr_5fpls_83',['PWR_CR_PLS',['../group___peripheral___registers___bits___definition.html#gac73c24d43953c7598e42acdd4c4e7435',1,'stm32f407xx_matlab.h']]], - ['pwr_5fcr_5fpls_5f0_84',['PWR_CR_PLS_0',['../group___peripheral___registers___bits___definition.html#gacef447510818c468c202e3b4991ea08e',1,'stm32f407xx_matlab.h']]], - ['pwr_5fcr_5fpls_5f1_85',['PWR_CR_PLS_1',['../group___peripheral___registers___bits___definition.html#gafcd19d78943514a2f695a39b45594623',1,'stm32f407xx_matlab.h']]], - ['pwr_5fcr_5fpls_5f2_86',['PWR_CR_PLS_2',['../group___peripheral___registers___bits___definition.html#ga1a8986ee557f443d4a8eebf68026bd52',1,'stm32f407xx_matlab.h']]], - ['pwr_5fcr_5fpls_5flev0_87',['PWR_CR_PLS_LEV0',['../group___peripheral___registers___bits___definition.html#gacb6b904b20d7e4fff958c75748861216',1,'stm32f407xx_matlab.h']]], - ['pwr_5fcr_5fpls_5flev1_88',['PWR_CR_PLS_LEV1',['../group___peripheral___registers___bits___definition.html#ga15b71263f73f0c4e53ca91fc8d096818',1,'stm32f407xx_matlab.h']]], - ['pwr_5fcr_5fpls_5flev2_89',['PWR_CR_PLS_LEV2',['../group___peripheral___registers___bits___definition.html#ga2ea128abc2fc4252b53d09ca2850e69e',1,'stm32f407xx_matlab.h']]], - ['pwr_5fcr_5fpls_5flev3_90',['PWR_CR_PLS_LEV3',['../group___peripheral___registers___bits___definition.html#ga9c1782980a2fb12de80058729a74f174',1,'stm32f407xx_matlab.h']]], - ['pwr_5fcr_5fpls_5flev4_91',['PWR_CR_PLS_LEV4',['../group___peripheral___registers___bits___definition.html#ga0fe79f097ea6c30a4ccf69ed3e177f85',1,'stm32f407xx_matlab.h']]], - ['pwr_5fcr_5fpls_5flev5_92',['PWR_CR_PLS_LEV5',['../group___peripheral___registers___bits___definition.html#ga326781d09a07b4d215424fbbae11b7b2',1,'stm32f407xx_matlab.h']]], - ['pwr_5fcr_5fpls_5flev6_93',['PWR_CR_PLS_LEV6',['../group___peripheral___registers___bits___definition.html#gaaff17e9c7fe7d837523b1e9a2f4e9baf',1,'stm32f407xx_matlab.h']]], - ['pwr_5fcr_5fpls_5flev7_94',['PWR_CR_PLS_LEV7',['../group___peripheral___registers___bits___definition.html#ga95e3b301b5470ae94d32c53a9fbdfc8b',1,'stm32f407xx_matlab.h']]], - ['pwr_5fcr_5fpls_5fmsk_95',['PWR_CR_PLS_Msk',['../group___peripheral___registers___bits___definition.html#ga5c4e8550b3c0d62156604ce5cdb659a7',1,'stm32f407xx_matlab.h']]], - ['pwr_5fcr_5fpls_5fpos_96',['PWR_CR_PLS_Pos',['../group___peripheral___registers___bits___definition.html#ga73dc96cce80c352f7bda9a3919023eef',1,'stm32f407xx_matlab.h']]], - ['pwr_5fcr_5fpmode_97',['PWR_CR_PMODE',['../group___peripheral___registers___bits___definition.html#ga56b78f2f76a841d2e8ddd56299b8d3e2',1,'stm32f407xx_matlab.h']]], - ['pwr_5fcr_5fpvde_98',['PWR_CR_PVDE',['../group___peripheral___registers___bits___definition.html#ga05d5c39759e69a294c0ab9bea8f142e5',1,'stm32f407xx_matlab.h']]], - ['pwr_5fcr_5fpvde_5fmsk_99',['PWR_CR_PVDE_Msk',['../group___peripheral___registers___bits___definition.html#ga1f556d56181a41dc59ba75be574155ad',1,'stm32f407xx_matlab.h']]], - ['pwr_5fcr_5fpvde_5fpos_100',['PWR_CR_PVDE_Pos',['../group___peripheral___registers___bits___definition.html#gadb4073cd8adfdba51b106072bab82fc3',1,'stm32f407xx_matlab.h']]], - ['pwr_5fcr_5fvos_101',['PWR_CR_VOS',['../group___peripheral___registers___bits___definition.html#gaccc33f1ba4e374e116ffa50f3a503030',1,'stm32f407xx_matlab.h']]], - ['pwr_5fcr_5fvos_5fmsk_102',['PWR_CR_VOS_Msk',['../group___peripheral___registers___bits___definition.html#ga3e94ecdd78a53924cc35417d24fc974a',1,'stm32f407xx_matlab.h']]], - ['pwr_5fcr_5fvos_5fpos_103',['PWR_CR_VOS_Pos',['../group___peripheral___registers___bits___definition.html#ga2f4f27bd20dad692917746ce1f184d28',1,'stm32f407xx_matlab.h']]], - ['pwr_5fcsr_5fbre_104',['PWR_CSR_BRE',['../group___peripheral___registers___bits___definition.html#ga0f99becaceb185431dbf46fb22718d0a',1,'stm32f407xx_matlab.h']]], - ['pwr_5fcsr_5fbre_5fmsk_105',['PWR_CSR_BRE_Msk',['../group___peripheral___registers___bits___definition.html#gacaed35bfe3de356d9e6def115ef87b9d',1,'stm32f407xx_matlab.h']]], - ['pwr_5fcsr_5fbre_5fpos_106',['PWR_CSR_BRE_Pos',['../group___peripheral___registers___bits___definition.html#gaa593af0ab76fabc71e48dce7b04f8acf',1,'stm32f407xx_matlab.h']]], - ['pwr_5fcsr_5fbrr_107',['PWR_CSR_BRR',['../group___peripheral___registers___bits___definition.html#ga939410de980c5bc297ff04bcf30875cc',1,'stm32f407xx_matlab.h']]], - ['pwr_5fcsr_5fbrr_5fmsk_108',['PWR_CSR_BRR_Msk',['../group___peripheral___registers___bits___definition.html#ga06752058548d6fbcc57dbc032fdde76d',1,'stm32f407xx_matlab.h']]], - ['pwr_5fcsr_5fbrr_5fpos_109',['PWR_CSR_BRR_Pos',['../group___peripheral___registers___bits___definition.html#gaa51171d8f6200d89b50ebd63f678b7c1',1,'stm32f407xx_matlab.h']]], - ['pwr_5fcsr_5fewup_110',['PWR_CSR_EWUP',['../group___peripheral___registers___bits___definition.html#ga7ac8c15a08bbee754ea720b0d4a4f580',1,'stm32f407xx_matlab.h']]], - ['pwr_5fcsr_5fewup_5fmsk_111',['PWR_CSR_EWUP_Msk',['../group___peripheral___registers___bits___definition.html#gac0b862445449f084acf74d1105f687da',1,'stm32f407xx_matlab.h']]], - ['pwr_5fcsr_5fewup_5fpos_112',['PWR_CSR_EWUP_Pos',['../group___peripheral___registers___bits___definition.html#ga20d629ea754e9d5942a97e037d515816',1,'stm32f407xx_matlab.h']]], - ['pwr_5fcsr_5fpvdo_113',['PWR_CSR_PVDO',['../group___peripheral___registers___bits___definition.html#ga3535ce181895cc00afeb28dcac68d04c',1,'stm32f407xx_matlab.h']]], - ['pwr_5fcsr_5fpvdo_5fmsk_114',['PWR_CSR_PVDO_Msk',['../group___peripheral___registers___bits___definition.html#ga4c27c44a96fdf582f2b25d00666a9548',1,'stm32f407xx_matlab.h']]], - ['pwr_5fcsr_5fpvdo_5fpos_115',['PWR_CSR_PVDO_Pos',['../group___peripheral___registers___bits___definition.html#gacdec9406a561d29e05ca2e2f69fd4532',1,'stm32f407xx_matlab.h']]], - ['pwr_5fcsr_5fregrdy_116',['PWR_CSR_REGRDY',['../group___peripheral___registers___bits___definition.html#ga017220a84cc5ab813eee18edd6309827',1,'stm32f407xx_matlab.h']]], - ['pwr_5fcsr_5fsbf_117',['PWR_CSR_SBF',['../group___peripheral___registers___bits___definition.html#gab4fd42f153660593cad6f4fe22ff76bb',1,'stm32f407xx_matlab.h']]], - ['pwr_5fcsr_5fsbf_5fmsk_118',['PWR_CSR_SBF_Msk',['../group___peripheral___registers___bits___definition.html#gab46cab51c4455b5ab8264684e0ca5783',1,'stm32f407xx_matlab.h']]], - ['pwr_5fcsr_5fsbf_5fpos_119',['PWR_CSR_SBF_Pos',['../group___peripheral___registers___bits___definition.html#ga28df9eb1abdd9d2f29b3f471f9aa096f',1,'stm32f407xx_matlab.h']]], - ['pwr_5fcsr_5fvosrdy_120',['PWR_CSR_VOSRDY',['../group___peripheral___registers___bits___definition.html#ga4126ed19cce54a5411ff8dd440171695',1,'stm32f407xx_matlab.h']]], - ['pwr_5fcsr_5fvosrdy_5fmsk_121',['PWR_CSR_VOSRDY_Msk',['../group___peripheral___registers___bits___definition.html#gaac90d2b7cd8836e014ee405815273ba9',1,'stm32f407xx_matlab.h']]], - ['pwr_5fcsr_5fvosrdy_5fpos_122',['PWR_CSR_VOSRDY_Pos',['../group___peripheral___registers___bits___definition.html#gad2938c00bca7b4425b8289498e781b48',1,'stm32f407xx_matlab.h']]], - ['pwr_5fcsr_5fwuf_123',['PWR_CSR_WUF',['../group___peripheral___registers___bits___definition.html#ga9465bb7ad9ca936688344e2a077539e6',1,'stm32f407xx_matlab.h']]], - ['pwr_5fcsr_5fwuf_5fmsk_124',['PWR_CSR_WUF_Msk',['../group___peripheral___registers___bits___definition.html#ga506641083e85de1202465b9be1712c24',1,'stm32f407xx_matlab.h']]], - ['pwr_5fcsr_5fwuf_5fpos_125',['PWR_CSR_WUF_Pos',['../group___peripheral___registers___bits___definition.html#gae7e519f8bd84379dc4a94dd5acaff305',1,'stm32f407xx_matlab.h']]], - ['pwr_5ftypedef_126',['PWR_TypeDef',['../struct_p_w_r___type_def.html',1,'']]] + ['tim_20simulator_0',['TIM Simulator',['../group___t_i_m___s_i_m_u_l_a_t_o_r.html',1,'']]], + ['tim1_1',['tim1',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#gaedba2af9d3a451898c4116468f63e31c',1,'stm32f4xx_periph_registers.c']]], + ['tim10_2',['tim10',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga5fc888fc63ae5329a954de3db43caefd',1,'stm32f4xx_periph_registers.c']]], + ['tim11_3',['tim11',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga720638f02cb775a2bdd6b866847b106f',1,'stm32f4xx_periph_registers.c']]], + ['tim12_4',['tim12',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#gaf7e88c4f7e226298777e23ce86e0f68e',1,'stm32f4xx_periph_registers.c']]], + ['tim12s_5',['tim12s',['../stm32f4xx__matlab__conf_8h.html#ad582b36106c35060b40bddfca929350e',1,'stm32f4xx_matlab_conf.h']]], + ['tim13_6',['tim13',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga5b7e61840360c6a797a1d137d1937c91',1,'stm32f4xx_periph_registers.c']]], + ['tim14_7',['tim14',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga8ade2aee59ea8e56c5b2b9fdd81e4480',1,'stm32f4xx_periph_registers.c']]], + ['tim1_5fbrk_5ftim9_5firqhandler_8',['TIM1_BRK_TIM9_IRQHandler',['../stm32f4xx__matlab__tim_8c.html#a3b60f6118cdd3449f4ed29fde4704236',1,'stm32f4xx_matlab_tim.c']]], + ['tim1_5ftrg_5fcom_5ftim11_5firqhandler_9',['TIM1_TRG_COM_TIM11_IRQHandler',['../stm32f4xx__matlab__tim_8c.html#a098245bf4e2f8844b22692b034a266fb',1,'stm32f4xx_matlab_tim.c']]], + ['tim1_5ftrgo_10',['TIM1_TRGO',['../struct_slave_channels.html#a1bb1d8089ac5eff5af1df34649b50a94',1,'SlaveChannels']]], + ['tim1_5fup_5ftim10_5firqhandler_11',['TIM1_UP_TIM10_IRQHandler',['../stm32f4xx__matlab__tim_8c.html#ad1fd361bc5ad89facee67c76d1ff8dc0',1,'stm32f4xx_matlab_tim.c']]], + ['tim1s_12',['tim1s',['../stm32f4xx__matlab__conf_8h.html#ab3aec69c8e446c577e391796728e4742',1,'stm32f4xx_matlab_conf.h']]], + ['tim2_13',['tim2',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#gaced1e82df483246f3faed614153db985',1,'stm32f4xx_periph_registers.c']]], + ['tim2_5firqhandler_14',['TIM2_IRQHandler',['../stm32f4xx__matlab__tim_8c.html#a38ad4725462bdc5e86c4ead4f04b9fc2',1,'stm32f4xx_matlab_tim.c']]], + ['tim2_5ftrgo_15',['TIM2_TRGO',['../struct_slave_channels.html#a7b0ea9ba4357a49b11b9c1ef79252613',1,'SlaveChannels']]], + ['tim3_16',['tim3',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga8a9462732233ea58ea84b420b20866ee',1,'stm32f4xx_periph_registers.c']]], + ['tim3_5firqhandler_17',['TIM3_IRQHandler',['../stm32f4xx__matlab__tim_8c.html#ac8e51d2183b5230cbd5481f8867adce9',1,'stm32f4xx_matlab_tim.c']]], + ['tim3_5ftrgo_18',['TIM3_TRGO',['../struct_slave_channels.html#aab5be57f956df4be03effc282a0479e5',1,'SlaveChannels']]], + ['tim3s_19',['tim3s',['../stm32f4xx__matlab__conf_8h.html#aefb416b7445ce7c77f15d96cd54cd2f5',1,'stm32f4xx_matlab_conf.h']]], + ['tim4_20',['tim4',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#gab15912b4a5af74002ab2c14632e0c538',1,'stm32f4xx_periph_registers.c']]], + ['tim4_5firqhandler_21',['TIM4_IRQHandler',['../stm32f4xx__matlab__tim_8c.html#a7133f3f78767503641d307386e68bd28',1,'stm32f4xx_matlab_tim.c']]], + ['tim4_5ftrgo_22',['TIM4_TRGO',['../struct_slave_channels.html#ab9bff03506a4f82f55b13a1065bccaa6',1,'SlaveChannels']]], + ['tim4s_23',['tim4s',['../stm32f4xx__matlab__conf_8h.html#ab42529334dbaea26f59721c40f7a7782',1,'stm32f4xx_matlab_conf.h']]], + ['tim5_24',['tim5',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga7f9bc8648d83bd2b1959b43b1f11b70e',1,'stm32f4xx_periph_registers.c']]], + ['tim5_5firqhandler_25',['TIM5_IRQHandler',['../stm32f4xx__matlab__tim_8c.html#a5e66446caf21dd90191dc07a13ce2378',1,'stm32f4xx_matlab_tim.c']]], + ['tim5_5ftrgo_26',['TIM5_TRGO',['../struct_slave_channels.html#a9780a406b85390dddcc18d4c6e606462',1,'SlaveChannels']]], + ['tim6_27',['tim6',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#gac7a5702d9b22c89aa44e3f5161cd8c9d',1,'stm32f4xx_periph_registers.c']]], + ['tim6_5fdac_5firqhandler_28',['TIM6_DAC_IRQHandler',['../stm32f4xx__matlab__tim_8c.html#a0839a45f331c4c067939b9c4533bbf4d',1,'stm32f4xx_matlab_tim.c']]], + ['tim6_5ftrgo_29',['TIM6_TRGO',['../struct_slave_channels.html#a2b1207a49068c13e3257396b4f369932',1,'SlaveChannels']]], + ['tim7_30',['tim7',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#gad32365c7344044f1d4b358b16faf768b',1,'stm32f4xx_periph_registers.c']]], + ['tim7_5firqhandler_31',['TIM7_IRQHandler',['../stm32f4xx__matlab__tim_8c.html#a98cff83252098363b2dbca9608df964e',1,'stm32f4xx_matlab_tim.c']]], + ['tim7_5ftrgo_32',['TIM7_TRGO',['../struct_slave_channels.html#a8a06a1b3f32a6abaf0a7ad38e27cf0e1',1,'SlaveChannels']]], + ['tim7s_33',['tim7s',['../stm32f4xx__matlab__conf_8h.html#af4ae2f8710078d4b2c0f07a4265ba66a',1,'stm32f4xx_matlab_conf.h']]], + ['tim8_34',['tim8',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga7cd2675665015ace1ee986d66c9cbfb2',1,'stm32f4xx_periph_registers.c']]], + ['tim8_5fbrk_5ftim12_5firqhandler_35',['TIM8_BRK_TIM12_IRQHandler',['../stm32f4xx__matlab__tim_8c.html#a301e0d3520f05f672ce047976f75ff6a',1,'stm32f4xx_matlab_tim.c']]], + ['tim8_5ftrg_5fcom_5ftim14_5firqhandler_36',['TIM8_TRG_COM_TIM14_IRQHandler',['../stm32f4xx__matlab__tim_8c.html#a4c8359a023f7ede4a9d9f94ea6fb92da',1,'stm32f4xx_matlab_tim.c']]], + ['tim8_5ftrgo_37',['TIM8_TRGO',['../struct_slave_channels.html#a591c0247b983b782f88fb92aea40f0c7',1,'SlaveChannels']]], + ['tim8_5fup_5ftim13_5firqhandler_38',['TIM8_UP_TIM13_IRQHandler',['../stm32f4xx__matlab__tim_8c.html#a7fb516f8826d882ac91cfc093884fcf5',1,'stm32f4xx_matlab_tim.c']]], + ['tim9_39',['tim9',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga3d6c0e6c095d01dac6c94c83c2e9e55f',1,'stm32f4xx_periph_registers.c']]], + ['tim_5focmode_5fsecond_5fshift_40',['TIM_OCMODE_SECOND_SHIFT',['../group___t_i_m___s_i_m_u_l_a_t_o_r.html#gae44a51b8c43872a8186ef4740d8f83d4',1,'stm32f4xx_matlab_tim.h']]], + ['tim_5fsim_41',['TIM_Sim',['../struct_t_i_m___sim.html',1,'']]], + ['tim_5fsim_5fdeinit_42',['TIM_SIM_DEINIT',['../group___t_i_m___s_i_m_u_l_a_t_o_r.html#ga52ac5ac026ea57787d19cd1a8611abba',1,'TIM_SIM_DEINIT(void): stm32f4xx_matlab_tim.c'],['../group___t_i_m___s_i_m_u_l_a_t_o_r.html#ga52ac5ac026ea57787d19cd1a8611abba',1,'TIM_SIM_DEINIT(void): stm32f4xx_matlab_tim.c']]], + ['tim_5fsimulation_43',['TIM_Simulation',['../group___t_i_m___s_i_m_u_l_a_t_o_r.html#ga3fcb4dd48557c21fdd6c379ad16bd229',1,'TIM_Simulation(TIM_TypeDef *TIMx, struct TIM_Sim *TIMS): stm32f4xx_matlab_tim.c'],['../group___t_i_m___s_i_m_u_l_a_t_o_r.html#ga3fcb4dd48557c21fdd6c379ad16bd229',1,'TIM_Simulation(TIM_TypeDef *TIMx, struct TIM_Sim *TIMS): stm32f4xx_matlab_tim.c']]], + ['timx_5fcount_44',['TIMx_Count',['../group___t_i_m___s_i_m_u_l_a_t_o_r.html#ga55e7ce9aae452502d5104acbe8fa4237',1,'TIMx_Count(TIM_TypeDef *TIMx, struct TIM_Sim *TIMS): stm32f4xx_matlab_tim.c'],['../group___t_i_m___s_i_m_u_l_a_t_o_r.html#ga55e7ce9aae452502d5104acbe8fa4237',1,'TIMx_Count(TIM_TypeDef *TIMx, struct TIM_Sim *TIMS): stm32f4xx_matlab_tim.c']]], + ['tpi_45',['TPI',['../group___c_m_s_i_s__core__base.html#ga8b4dd00016aed25a0ea54e9a9acd1239',1,'stm32f407xx_matlab_memory.h']]], + ['tpi_5fbase_46',['TPI_BASE',['../group___c_m_s_i_s__core__base.html#ga2b1eeff850a7e418844ca847145a1a68',1,'stm32f407xx_matlab_memory.h']]], + ['tpi_5fbase_5fshift_47',['TPI_BASE_SHIFT',['../group___c_m_s_i_s__core__base.html#ga688b0af5b023485e742d8906117e0dcb',1,'stm32f407xx_matlab_memory.h']]], + ['ts_48',['Ts',['../mexing_8m.html#ac910fa4e03fcc57ffc78b3693e910e1a',1,'mexing.m']]], + ['tx_5fcnt_49',['tx_cnt',['../struct_t_i_m___sim.html#a369177ee20a3798f0d7b98cf7c549498',1,'TIM_Sim']]], + ['tx_5fstep_50',['tx_step',['../struct_t_i_m___sim.html#a838a96dee1a1980434ae35295f85141e',1,'TIM_Sim']]] ]; diff --git a/DOCS/html/search/all_11.js b/DOCS/html/search/all_11.js index f9523d9..4b0cd4d 100644 --- a/DOCS/html/search/all_11.js +++ b/DOCS/html/search/all_11.js @@ -1,4 +1,19 @@ var searchData= [ - ['q_0',['Q',['../group___c_m_s_i_s__core___debug_functions.html#ga65f27ddc4f7e09c14ce7c5211b2e000a',1,'APSR_Type::Q'],['../group___c_m_s_i_s__core___debug_functions.html#ga65f27ddc4f7e09c14ce7c5211b2e000a',1,'APSR_Type::@0::Q'],['../group___c_m_s_i_s__core___debug_functions.html#ga65f27ddc4f7e09c14ce7c5211b2e000a',1,'xPSR_Type::Q'],['../group___c_m_s_i_s__core___debug_functions.html#ga65f27ddc4f7e09c14ce7c5211b2e000a',1,'xPSR_Type::@2::Q']]] + ['uart4_0',['uart4',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#gaeac987df31348c6546d30bf20d1202b1',1,'stm32f4xx_periph_registers.c']]], + ['uart5_1',['uart5',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga334a742f4e47d9275a7ca0b6a64f3b9b',1,'stm32f4xx_periph_registers.c']]], + ['usart1_2',['usart1',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga6008378d0a594dbb3373976f11998c07',1,'stm32f4xx_periph_registers.c']]], + ['usart2_3',['usart2',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga6704391eb1d9b549ec4a30bff051c840',1,'stm32f4xx_periph_registers.c']]], + ['usart3_4',['usart3',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga34a4f060994660316b3ccf64ef2ca061',1,'stm32f4xx_periph_registers.c']]], + ['usart6_5',['usart6',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#gac976d368ba60c6c4fb520f15ffc973ed',1,'stm32f4xx_periph_registers.c']]], + ['usb_5fotg_5ffs_5fperiph_6',['usb_otg_fs_periph',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#gab7326fc264f9026f7d5be1914a222257',1,'stm32f4xx_periph_registers.c']]], + ['usb_5fotg_5fhs_5fperiph_7',['usb_otg_hs_periph',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga4e565603c7406e27b1f5503de3a8c41b',1,'stm32f4xx_periph_registers.c']]], + ['use_5ftim1_8',['USE_TIM1',['../group___s_i_m_u_l_a_t_o_r___c_o_n_f.html#ga54a98c21365e0bc45b81555d2b101f2b',1,'stm32f4xx_matlab_conf.h']]], + ['use_5ftim12_9',['USE_TIM12',['../group___s_i_m_u_l_a_t_o_r___c_o_n_f.html#ga4e2b0e6cdf9eed74581b575c3fd9516b',1,'stm32f4xx_matlab_conf.h']]], + ['use_5ftim3_10',['USE_TIM3',['../group___s_i_m_u_l_a_t_o_r___c_o_n_f.html#ga5b5685a43273b6e37242a4aba3ee0617',1,'stm32f4xx_matlab_conf.h']]], + ['use_5ftim4_11',['USE_TIM4',['../group___s_i_m_u_l_a_t_o_r___c_o_n_f.html#ga1493b39c9214501180b81b4c892f9be0',1,'stm32f4xx_matlab_conf.h']]], + ['use_5ftim4_5fhandler_12',['USE_TIM4_HANDLER',['../group___s_i_m_u_l_a_t_o_r___c_o_n_f.html#gae500122af1918af2cf69bc107315d15f',1,'stm32f4xx_matlab_conf.h']]], + ['use_5ftim7_13',['USE_TIM7',['../group___s_i_m_u_l_a_t_o_r___c_o_n_f.html#ga7cdc54cc8cbbb6e9f60001f1e3e6ec67',1,'stm32f4xx_matlab_conf.h']]], + ['use_5ftim7_5fhandler_14',['USE_TIM7_HANDLER',['../group___s_i_m_u_l_a_t_o_r___c_o_n_f.html#ga989acf15c18c3016a65fcc888d2f641b',1,'stm32f4xx_matlab_conf.h']]], + ['use_5ftim8_5fbrk_5ftim12_5fhandler_15',['USE_TIM8_BRK_TIM12_HANDLER',['../group___s_i_m_u_l_a_t_o_r___c_o_n_f.html#gae38cd8ed529da5815f8619b9bad8c97d',1,'stm32f4xx_matlab_conf.h']]] ]; diff --git a/DOCS/html/search/all_12.js b/DOCS/html/search/all_12.js index d094276..c68f11c 100644 --- a/DOCS/html/search/all_12.js +++ b/DOCS/html/search/all_12.js @@ -1,1531 +1,4 @@ var searchData= [ - ['rcc_0',['RCC',['../group___peripheral__declaration.html#ga74944438a086975793d26ae48d5882d4',1,'stm32f407xx_matlab.h']]], - ['rcc_1',['rcc',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga33f5f83bbcee4994fef4f29192860875',1,'stm32f4xx_periph_registers.c']]], - ['rcc_5fahb1enr_5fbkpsramen_2',['RCC_AHB1ENR_BKPSRAMEN',['../group___peripheral___registers___bits___definition.html#gaee10e5e11a2043e4ff865c3d7b804233',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb1enr_5fbkpsramen_5fmsk_3',['RCC_AHB1ENR_BKPSRAMEN_Msk',['../group___peripheral___registers___bits___definition.html#ga67735d069e447a3cbd8b1cf0ac1e69ca',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb1enr_5fbkpsramen_5fpos_4',['RCC_AHB1ENR_BKPSRAMEN_Pos',['../group___peripheral___registers___bits___definition.html#ga6732dcee9b2bf278527a55f9c14d703c',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb1enr_5fccmdataramen_5',['RCC_AHB1ENR_CCMDATARAMEN',['../group___peripheral___registers___bits___definition.html#ga29bbdcc191708a9e6a46ef197a3b2c65',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb1enr_5fccmdataramen_5fmsk_6',['RCC_AHB1ENR_CCMDATARAMEN_Msk',['../group___peripheral___registers___bits___definition.html#gae56a123a2131232460f2a1d4d7b5fb87',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb1enr_5fccmdataramen_5fpos_7',['RCC_AHB1ENR_CCMDATARAMEN_Pos',['../group___peripheral___registers___bits___definition.html#gac74e8dc5505978a1b2cb109d0c77c559',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb1enr_5fcrcen_8',['RCC_AHB1ENR_CRCEN',['../group___peripheral___registers___bits___definition.html#gafa3d41f31401e812f839defee241df83',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb1enr_5fcrcen_5fmsk_9',['RCC_AHB1ENR_CRCEN_Msk',['../group___peripheral___registers___bits___definition.html#ga3b467a2c6329ecb8ca42c1d9e1116035',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb1enr_5fcrcen_5fpos_10',['RCC_AHB1ENR_CRCEN_Pos',['../group___peripheral___registers___bits___definition.html#gadf0c26180146aedeec41861fd765a05c',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb1enr_5fdma1en_11',['RCC_AHB1ENR_DMA1EN',['../group___peripheral___registers___bits___definition.html#gae07b00778a51a4e52b911aeccb897aba',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb1enr_5fdma1en_5fmsk_12',['RCC_AHB1ENR_DMA1EN_Msk',['../group___peripheral___registers___bits___definition.html#gab04b66dc0d69d098db894416722e9871',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb1enr_5fdma1en_5fpos_13',['RCC_AHB1ENR_DMA1EN_Pos',['../group___peripheral___registers___bits___definition.html#ga0114d8249d989c5ab3feac252e30509e',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb1enr_5fdma2en_14',['RCC_AHB1ENR_DMA2EN',['../group___peripheral___registers___bits___definition.html#ga664a5d572a39a0c084e4ee7c1cf7df0d',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb1enr_5fdma2en_5fmsk_15',['RCC_AHB1ENR_DMA2EN_Msk',['../group___peripheral___registers___bits___definition.html#gaeb95b569d5ea1d4c9483fbfd7df37f3a',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb1enr_5fdma2en_5fpos_16',['RCC_AHB1ENR_DMA2EN_Pos',['../group___peripheral___registers___bits___definition.html#gaf754f312ede73c0d5d35e1a08b614f94',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb1enr_5fethmacen_17',['RCC_AHB1ENR_ETHMACEN',['../group___peripheral___registers___bits___definition.html#ga507020c3c3945dfbf3d628ffa42afdba',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb1enr_5fethmacen_5fmsk_18',['RCC_AHB1ENR_ETHMACEN_Msk',['../group___peripheral___registers___bits___definition.html#gaf7f4087101bf2a82c3ac9ea31ca3504f',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb1enr_5fethmacen_5fpos_19',['RCC_AHB1ENR_ETHMACEN_Pos',['../group___peripheral___registers___bits___definition.html#ga43785491862d48d7a9f0651f6e94a388',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb1enr_5fethmacptpen_20',['RCC_AHB1ENR_ETHMACPTPEN',['../group___peripheral___registers___bits___definition.html#ga2bf11a8d105bc59e4f509d91cbf05e0e',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb1enr_5fethmacptpen_5fmsk_21',['RCC_AHB1ENR_ETHMACPTPEN_Msk',['../group___peripheral___registers___bits___definition.html#ga41c39ec61603f15cf1916d743f1e3673',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb1enr_5fethmacptpen_5fpos_22',['RCC_AHB1ENR_ETHMACPTPEN_Pos',['../group___peripheral___registers___bits___definition.html#ga9bedafca82770123ee737720df26612e',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb1enr_5fethmacrxen_23',['RCC_AHB1ENR_ETHMACRXEN',['../group___peripheral___registers___bits___definition.html#ga8933482a90a769d0cdd332b170132b77',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb1enr_5fethmacrxen_5fmsk_24',['RCC_AHB1ENR_ETHMACRXEN_Msk',['../group___peripheral___registers___bits___definition.html#ga9872ba78cf86d347267020336489be40',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb1enr_5fethmacrxen_5fpos_25',['RCC_AHB1ENR_ETHMACRXEN_Pos',['../group___peripheral___registers___bits___definition.html#gac12dfc1c179aa47c0bf97a005974182e',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb1enr_5fethmactxen_26',['RCC_AHB1ENR_ETHMACTXEN',['../group___peripheral___registers___bits___definition.html#ga001f617c29d950ee1aa91773331ae6f6',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb1enr_5fethmactxen_5fmsk_27',['RCC_AHB1ENR_ETHMACTXEN_Msk',['../group___peripheral___registers___bits___definition.html#gaf7e9fa8c5b341bd2c8e1354ea0452990',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb1enr_5fethmactxen_5fpos_28',['RCC_AHB1ENR_ETHMACTXEN_Pos',['../group___peripheral___registers___bits___definition.html#gab032942ed246f6386d792915da6519e7',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb1enr_5fgpioaen_29',['RCC_AHB1ENR_GPIOAEN',['../group___peripheral___registers___bits___definition.html#ga6ff46fb3b30fc6792e4fd18fcb0941b5',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb1enr_5fgpioaen_5fmsk_30',['RCC_AHB1ENR_GPIOAEN_Msk',['../group___peripheral___registers___bits___definition.html#gaa1610c0bcc3f778000c9ffe4ceaaf7a8',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb1enr_5fgpioaen_5fpos_31',['RCC_AHB1ENR_GPIOAEN_Pos',['../group___peripheral___registers___bits___definition.html#ga46ac0ea3dfd9fd9dc25a6fc974c0b2e7',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb1enr_5fgpioben_32',['RCC_AHB1ENR_GPIOBEN',['../group___peripheral___registers___bits___definition.html#gad7f408f92e7fd49b0957b8cb4ff31ca5',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb1enr_5fgpioben_5fmsk_33',['RCC_AHB1ENR_GPIOBEN_Msk',['../group___peripheral___registers___bits___definition.html#ga79f6e5e212dee1b54f1103aa6c5b63c8',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb1enr_5fgpioben_5fpos_34',['RCC_AHB1ENR_GPIOBEN_Pos',['../group___peripheral___registers___bits___definition.html#ga9e283561bd4c7f47c8ba5a3affae294a',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb1enr_5fgpiocen_35',['RCC_AHB1ENR_GPIOCEN',['../group___peripheral___registers___bits___definition.html#gae8a8b42e33aef2a7bc2d41ad9d231733',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb1enr_5fgpiocen_5fmsk_36',['RCC_AHB1ENR_GPIOCEN_Msk',['../group___peripheral___registers___bits___definition.html#ga6d7e8d23a1214b25dca4d0838324371b',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb1enr_5fgpiocen_5fpos_37',['RCC_AHB1ENR_GPIOCEN_Pos',['../group___peripheral___registers___bits___definition.html#ga2b008be82ceb7ff8fc8b5b89c42d5956',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb1enr_5fgpioden_38',['RCC_AHB1ENR_GPIODEN',['../group___peripheral___registers___bits___definition.html#gaebd8146e91c76f14af8dfe78a1c2d916',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb1enr_5fgpioden_5fmsk_39',['RCC_AHB1ENR_GPIODEN_Msk',['../group___peripheral___registers___bits___definition.html#ga5da72a3a599290c99b251cf0e40d579a',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb1enr_5fgpioden_5fpos_40',['RCC_AHB1ENR_GPIODEN_Pos',['../group___peripheral___registers___bits___definition.html#ga57c3badb1f83e08ab09719c58d70e1b4',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb1enr_5fgpioeen_41',['RCC_AHB1ENR_GPIOEEN',['../group___peripheral___registers___bits___definition.html#ga67a9094e0e464eaa8e25f854f90abfc6',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb1enr_5fgpioeen_5fmsk_42',['RCC_AHB1ENR_GPIOEEN_Msk',['../group___peripheral___registers___bits___definition.html#ga574a0ff2d711679c81d62a365efe9b25',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb1enr_5fgpioeen_5fpos_43',['RCC_AHB1ENR_GPIOEEN_Pos',['../group___peripheral___registers___bits___definition.html#ga2313a0beb0ceb64be0c3c2906c9d11c1',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb1enr_5fgpiofen_44',['RCC_AHB1ENR_GPIOFEN',['../group___peripheral___registers___bits___definition.html#gaefa8e0fbecedb4167a4d7ef51e2a48b5',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb1enr_5fgpiofen_5fmsk_45',['RCC_AHB1ENR_GPIOFEN_Msk',['../group___peripheral___registers___bits___definition.html#gac40bd7a86de787e99ecf69881e8d8803',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb1enr_5fgpiofen_5fpos_46',['RCC_AHB1ENR_GPIOFEN_Pos',['../group___peripheral___registers___bits___definition.html#ga086e36c7f473c1290b8b837dbb6cefbd',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb1enr_5fgpiogen_47',['RCC_AHB1ENR_GPIOGEN',['../group___peripheral___registers___bits___definition.html#ga5304e897036391c916ef82258919a08b',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb1enr_5fgpiogen_5fmsk_48',['RCC_AHB1ENR_GPIOGEN_Msk',['../group___peripheral___registers___bits___definition.html#ga84f85f90ddfceebacab190e14cf0de75',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb1enr_5fgpiogen_5fpos_49',['RCC_AHB1ENR_GPIOGEN_Pos',['../group___peripheral___registers___bits___definition.html#ga746fd16f381b86d549e73d73977b408d',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb1enr_5fgpiohen_50',['RCC_AHB1ENR_GPIOHEN',['../group___peripheral___registers___bits___definition.html#gadb16afc550121895822ebb22108196b6',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb1enr_5fgpiohen_5fmsk_51',['RCC_AHB1ENR_GPIOHEN_Msk',['../group___peripheral___registers___bits___definition.html#gaee11e4e6ddeff9db3ddd22873d1ca8d5',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb1enr_5fgpiohen_5fpos_52',['RCC_AHB1ENR_GPIOHEN_Pos',['../group___peripheral___registers___bits___definition.html#ga37d856370c08a4704127d615939510e8',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb1enr_5fgpioien_53',['RCC_AHB1ENR_GPIOIEN',['../group___peripheral___registers___bits___definition.html#gadee44347a6a62429ee74753fe1dea5d7',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb1enr_5fgpioien_5fmsk_54',['RCC_AHB1ENR_GPIOIEN_Msk',['../group___peripheral___registers___bits___definition.html#ga3d542abb9e4477f575afe1066062ce34',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb1enr_5fgpioien_5fpos_55',['RCC_AHB1ENR_GPIOIEN_Pos',['../group___peripheral___registers___bits___definition.html#gaea6afabe8b46415f972a1e54a605decf',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb1enr_5fotghsen_56',['RCC_AHB1ENR_OTGHSEN',['../group___peripheral___registers___bits___definition.html#gab18d15ea68876f7a42ee7350074b05f4',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb1enr_5fotghsen_5fmsk_57',['RCC_AHB1ENR_OTGHSEN_Msk',['../group___peripheral___registers___bits___definition.html#ga44e119c40f74b0caf89d18b8e784d7cd',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb1enr_5fotghsen_5fpos_58',['RCC_AHB1ENR_OTGHSEN_Pos',['../group___peripheral___registers___bits___definition.html#gadd0aa66629d449a07dea64c30ca67c5e',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb1enr_5fotghsulpien_59',['RCC_AHB1ENR_OTGHSULPIEN',['../group___peripheral___registers___bits___definition.html#ga784be313f54862d3670723f2334fa51f',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb1enr_5fotghsulpien_5fmsk_60',['RCC_AHB1ENR_OTGHSULPIEN_Msk',['../group___peripheral___registers___bits___definition.html#ga162543647ebac3ea7cf992bf229acb56',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb1enr_5fotghsulpien_5fpos_61',['RCC_AHB1ENR_OTGHSULPIEN_Pos',['../group___peripheral___registers___bits___definition.html#ga073b5e5498b3a169555570dc126d11fb',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb1lpenr_5fbkpsramlpen_62',['RCC_AHB1LPENR_BKPSRAMLPEN',['../group___peripheral___registers___bits___definition.html#ga777dc76d2a216f8b51b360e8054342e4',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb1lpenr_5fbkpsramlpen_5fmsk_63',['RCC_AHB1LPENR_BKPSRAMLPEN_Msk',['../group___peripheral___registers___bits___definition.html#ga192203e1375323694da43336c59f036e',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb1lpenr_5fbkpsramlpen_5fpos_64',['RCC_AHB1LPENR_BKPSRAMLPEN_Pos',['../group___peripheral___registers___bits___definition.html#ga3100beebfa0db32c2c193e8fbad16cec',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb1lpenr_5fcrclpen_65',['RCC_AHB1LPENR_CRCLPEN',['../group___peripheral___registers___bits___definition.html#ga7333e14b5ccf6d608232ea52a10f7052',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb1lpenr_5fcrclpen_5fmsk_66',['RCC_AHB1LPENR_CRCLPEN_Msk',['../group___peripheral___registers___bits___definition.html#ga87b177e8246a207541fbce277d4f48ab',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb1lpenr_5fcrclpen_5fpos_67',['RCC_AHB1LPENR_CRCLPEN_Pos',['../group___peripheral___registers___bits___definition.html#ga2fb1b796b4ad84e3dd60b14b958d6f98',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb1lpenr_5fdma1lpen_68',['RCC_AHB1LPENR_DMA1LPEN',['../group___peripheral___registers___bits___definition.html#ga7d6c8ae1441d545d18c54b30c6a0da77',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb1lpenr_5fdma1lpen_5fmsk_69',['RCC_AHB1LPENR_DMA1LPEN_Msk',['../group___peripheral___registers___bits___definition.html#ga8c9b77b3b402f07fd5196bc6ced33032',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb1lpenr_5fdma1lpen_5fpos_70',['RCC_AHB1LPENR_DMA1LPEN_Pos',['../group___peripheral___registers___bits___definition.html#ga014095a10051377b3cbdd6e5392d4625',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb1lpenr_5fdma2lpen_71',['RCC_AHB1LPENR_DMA2LPEN',['../group___peripheral___registers___bits___definition.html#ga9e2d376f6c7db4266a5b039a3aa6c207',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb1lpenr_5fdma2lpen_5fmsk_72',['RCC_AHB1LPENR_DMA2LPEN_Msk',['../group___peripheral___registers___bits___definition.html#ga8a4daa369b439dbff3744661225897bc',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb1lpenr_5fdma2lpen_5fpos_73',['RCC_AHB1LPENR_DMA2LPEN_Pos',['../group___peripheral___registers___bits___definition.html#ga7b8cac0542554d72d2b230feed936194',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb1lpenr_5fethmaclpen_74',['RCC_AHB1LPENR_ETHMACLPEN',['../group___peripheral___registers___bits___definition.html#ga421fd0aec3671e054ef18cd290bc164e',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb1lpenr_5fethmaclpen_5fmsk_75',['RCC_AHB1LPENR_ETHMACLPEN_Msk',['../group___peripheral___registers___bits___definition.html#ga1da28307db95580ebba7ee61b0a8f9cb',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb1lpenr_5fethmaclpen_5fpos_76',['RCC_AHB1LPENR_ETHMACLPEN_Pos',['../group___peripheral___registers___bits___definition.html#ga05fd12d343bf91b0cb39a9db295f1c72',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb1lpenr_5fethmacptplpen_77',['RCC_AHB1LPENR_ETHMACPTPLPEN',['../group___peripheral___registers___bits___definition.html#gaa04c4dfda05aebb5efe66518a28e29de',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb1lpenr_5fethmacptplpen_5fmsk_78',['RCC_AHB1LPENR_ETHMACPTPLPEN_Msk',['../group___peripheral___registers___bits___definition.html#ga9db17131964299ee8997a3bd9f4d5544',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb1lpenr_5fethmacptplpen_5fpos_79',['RCC_AHB1LPENR_ETHMACPTPLPEN_Pos',['../group___peripheral___registers___bits___definition.html#gaea2001b38e0bac5fd64303d9bb8df6a5',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb1lpenr_5fethmacrxlpen_80',['RCC_AHB1LPENR_ETHMACRXLPEN',['../group___peripheral___registers___bits___definition.html#ga28dc3cec4693215c0db36dcfd8a55ee8',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb1lpenr_5fethmacrxlpen_5fmsk_81',['RCC_AHB1LPENR_ETHMACRXLPEN_Msk',['../group___peripheral___registers___bits___definition.html#ga793010bfe42e5e13b9ebed488352b3b3',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb1lpenr_5fethmacrxlpen_5fpos_82',['RCC_AHB1LPENR_ETHMACRXLPEN_Pos',['../group___peripheral___registers___bits___definition.html#gabe363b3bbbef9025b6b05d007d8e3423',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb1lpenr_5fethmactxlpen_83',['RCC_AHB1LPENR_ETHMACTXLPEN',['../group___peripheral___registers___bits___definition.html#ga09935984b92821f18c3e00f7e4fbeb62',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb1lpenr_5fethmactxlpen_5fmsk_84',['RCC_AHB1LPENR_ETHMACTXLPEN_Msk',['../group___peripheral___registers___bits___definition.html#ga7a38ff160774afae91d03db40b2cfde1',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb1lpenr_5fethmactxlpen_5fpos_85',['RCC_AHB1LPENR_ETHMACTXLPEN_Pos',['../group___peripheral___registers___bits___definition.html#ga748b751a0809106ddb4c874b11bf36fa',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb1lpenr_5fflitflpen_86',['RCC_AHB1LPENR_FLITFLPEN',['../group___peripheral___registers___bits___definition.html#ga378f6e2ad9fef59f28db829d2074e796',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb1lpenr_5fflitflpen_5fmsk_87',['RCC_AHB1LPENR_FLITFLPEN_Msk',['../group___peripheral___registers___bits___definition.html#gaafb7485a44d40e2da16270de53aa8171',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb1lpenr_5fflitflpen_5fpos_88',['RCC_AHB1LPENR_FLITFLPEN_Pos',['../group___peripheral___registers___bits___definition.html#ga07b410fb7c23f0ee3f8d100c5a409078',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb1lpenr_5fgpioalpen_89',['RCC_AHB1LPENR_GPIOALPEN',['../group___peripheral___registers___bits___definition.html#gaf1076b0644c026ab480efdb6aa8c74fb',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb1lpenr_5fgpioalpen_5fmsk_90',['RCC_AHB1LPENR_GPIOALPEN_Msk',['../group___peripheral___registers___bits___definition.html#gab01076ddb6708e4c0ff9d6c4f22fa809',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb1lpenr_5fgpioalpen_5fpos_91',['RCC_AHB1LPENR_GPIOALPEN_Pos',['../group___peripheral___registers___bits___definition.html#gacded6b0f52a7b9ef3bde81ce8d4cd657',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb1lpenr_5fgpioblpen_92',['RCC_AHB1LPENR_GPIOBLPEN',['../group___peripheral___registers___bits___definition.html#ga55f6ff35a37c4b9106c9e8aa18ab4545',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb1lpenr_5fgpioblpen_5fmsk_93',['RCC_AHB1LPENR_GPIOBLPEN_Msk',['../group___peripheral___registers___bits___definition.html#gad765dcf02bb5f215ff3a77a63c16f746',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb1lpenr_5fgpioblpen_5fpos_94',['RCC_AHB1LPENR_GPIOBLPEN_Pos',['../group___peripheral___registers___bits___definition.html#ga1408e65a8ca8d481d713a171adb4a8b9',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb1lpenr_5fgpioclpen_95',['RCC_AHB1LPENR_GPIOCLPEN',['../group___peripheral___registers___bits___definition.html#gac86ad592684edae0ba2cafd22a4f04d1',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb1lpenr_5fgpioclpen_5fmsk_96',['RCC_AHB1LPENR_GPIOCLPEN_Msk',['../group___peripheral___registers___bits___definition.html#ga26ff370d6adef4823a87bd98c5767a42',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb1lpenr_5fgpioclpen_5fpos_97',['RCC_AHB1LPENR_GPIOCLPEN_Pos',['../group___peripheral___registers___bits___definition.html#ga30cd4b8a99bb64ebbcac917ea64ccacc',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb1lpenr_5fgpiodlpen_98',['RCC_AHB1LPENR_GPIODLPEN',['../group___peripheral___registers___bits___definition.html#ga89002894839d323b05c4b3f674b54470',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb1lpenr_5fgpiodlpen_5fmsk_99',['RCC_AHB1LPENR_GPIODLPEN_Msk',['../group___peripheral___registers___bits___definition.html#ga4b81052c9334056e60b2b47e12d8ccef',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb1lpenr_5fgpiodlpen_5fpos_100',['RCC_AHB1LPENR_GPIODLPEN_Pos',['../group___peripheral___registers___bits___definition.html#gaceb2e30709973666017a04023286fb71',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb1lpenr_5fgpioelpen_101',['RCC_AHB1LPENR_GPIOELPEN',['../group___peripheral___registers___bits___definition.html#ga2980a6e02550369d05e121ff6f16505c',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb1lpenr_5fgpioelpen_5fmsk_102',['RCC_AHB1LPENR_GPIOELPEN_Msk',['../group___peripheral___registers___bits___definition.html#ga379b06aa2db224e0e6e2812e33e5bc88',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb1lpenr_5fgpioelpen_5fpos_103',['RCC_AHB1LPENR_GPIOELPEN_Pos',['../group___peripheral___registers___bits___definition.html#ga76748b3f35e4bc4481110d4be1ebdef9',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb1lpenr_5fgpioflpen_104',['RCC_AHB1LPENR_GPIOFLPEN',['../group___peripheral___registers___bits___definition.html#gaa7a50c0506b1014d89224933c6c42e6f',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb1lpenr_5fgpioflpen_5fmsk_105',['RCC_AHB1LPENR_GPIOFLPEN_Msk',['../group___peripheral___registers___bits___definition.html#gad1d321cff7127cb7bee72a680b40bcaf',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb1lpenr_5fgpioflpen_5fpos_106',['RCC_AHB1LPENR_GPIOFLPEN_Pos',['../group___peripheral___registers___bits___definition.html#ga0bdc53d83d3aec2d5c5fb2ae6a97b268',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb1lpenr_5fgpioglpen_107',['RCC_AHB1LPENR_GPIOGLPEN',['../group___peripheral___registers___bits___definition.html#gab1dc004ecb0a2950100a062cda47586f',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb1lpenr_5fgpioglpen_5fmsk_108',['RCC_AHB1LPENR_GPIOGLPEN_Msk',['../group___peripheral___registers___bits___definition.html#gab8cbc273b51b62d59dbe58f68a330231',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb1lpenr_5fgpioglpen_5fpos_109',['RCC_AHB1LPENR_GPIOGLPEN_Pos',['../group___peripheral___registers___bits___definition.html#ga2050b38f2df4a69119c402d384e5b862',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb1lpenr_5fgpiohlpen_110',['RCC_AHB1LPENR_GPIOHLPEN',['../group___peripheral___registers___bits___definition.html#ga197be77b89e9eae127a536bd2601ded9',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb1lpenr_5fgpiohlpen_5fmsk_111',['RCC_AHB1LPENR_GPIOHLPEN_Msk',['../group___peripheral___registers___bits___definition.html#ga5420182a12449790d9316927e05bab4b',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb1lpenr_5fgpiohlpen_5fpos_112',['RCC_AHB1LPENR_GPIOHLPEN_Pos',['../group___peripheral___registers___bits___definition.html#ga64e54771be85afdd10ad93c3acdef080',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb1lpenr_5fgpioilpen_113',['RCC_AHB1LPENR_GPIOILPEN',['../group___peripheral___registers___bits___definition.html#ga70d927cfb1d110133bd64989b216a375',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb1lpenr_5fgpioilpen_5fmsk_114',['RCC_AHB1LPENR_GPIOILPEN_Msk',['../group___peripheral___registers___bits___definition.html#ga285f894641272c773dac56c0eb5d14cc',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb1lpenr_5fgpioilpen_5fpos_115',['RCC_AHB1LPENR_GPIOILPEN_Pos',['../group___peripheral___registers___bits___definition.html#gaa6334fbcfede5da166dab8b2e15d69d9',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb1lpenr_5fotghslpen_116',['RCC_AHB1LPENR_OTGHSLPEN',['../group___peripheral___registers___bits___definition.html#ga934a7c19bd6f6b34941058c5c3552b91',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb1lpenr_5fotghslpen_5fmsk_117',['RCC_AHB1LPENR_OTGHSLPEN_Msk',['../group___peripheral___registers___bits___definition.html#gaf645b65fa1f722e0909ea5768f5e39d1',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb1lpenr_5fotghslpen_5fpos_118',['RCC_AHB1LPENR_OTGHSLPEN_Pos',['../group___peripheral___registers___bits___definition.html#ga4f86b4c6131db2afce3db43a4b5242c9',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb1lpenr_5fotghsulpilpen_119',['RCC_AHB1LPENR_OTGHSULPILPEN',['../group___peripheral___registers___bits___definition.html#gab9567cabb8058c53bae64ed4b77c05dd',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb1lpenr_5fotghsulpilpen_5fmsk_120',['RCC_AHB1LPENR_OTGHSULPILPEN_Msk',['../group___peripheral___registers___bits___definition.html#ga9468c1e5269479e8009174e2dbdfd871',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb1lpenr_5fotghsulpilpen_5fpos_121',['RCC_AHB1LPENR_OTGHSULPILPEN_Pos',['../group___peripheral___registers___bits___definition.html#gaa7f913b7278276c84700eba1ab154d16',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb1lpenr_5fsram1lpen_122',['RCC_AHB1LPENR_SRAM1LPEN',['../group___peripheral___registers___bits___definition.html#ga4cd1fbd9113809a6a3c904617647219c',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb1lpenr_5fsram1lpen_5fmsk_123',['RCC_AHB1LPENR_SRAM1LPEN_Msk',['../group___peripheral___registers___bits___definition.html#ga3165c825e9a88a606803cd08a85d9dd9',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb1lpenr_5fsram1lpen_5fpos_124',['RCC_AHB1LPENR_SRAM1LPEN_Pos',['../group___peripheral___registers___bits___definition.html#gab1719fa2c00b2554e679b7bd52e648b3',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb1lpenr_5fsram2lpen_125',['RCC_AHB1LPENR_SRAM2LPEN',['../group___peripheral___registers___bits___definition.html#gaaf7a4c822fa3073035a04487c4cca320',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb1lpenr_5fsram2lpen_5fmsk_126',['RCC_AHB1LPENR_SRAM2LPEN_Msk',['../group___peripheral___registers___bits___definition.html#ga54ed7528aecee29c5498e649bb9851eb',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb1lpenr_5fsram2lpen_5fpos_127',['RCC_AHB1LPENR_SRAM2LPEN_Pos',['../group___peripheral___registers___bits___definition.html#ga14b6f62bdc1eeab17de120a32d3ef25e',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb1rstr_5fcrcrst_128',['RCC_AHB1RSTR_CRCRST',['../group___peripheral___registers___bits___definition.html#ga94f45f591e5e217833c6ab36a958543b',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb1rstr_5fcrcrst_5fmsk_129',['RCC_AHB1RSTR_CRCRST_Msk',['../group___peripheral___registers___bits___definition.html#gaaf0f9e76b934af78155abddaacf568e4',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb1rstr_5fcrcrst_5fpos_130',['RCC_AHB1RSTR_CRCRST_Pos',['../group___peripheral___registers___bits___definition.html#ga250ad2c8a4d0fbfd4360afcdce858075',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb1rstr_5fdma1rst_131',['RCC_AHB1RSTR_DMA1RST',['../group___peripheral___registers___bits___definition.html#ga4d1655ddfb777fce28b1d6b9a9c2d0e0',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb1rstr_5fdma1rst_5fmsk_132',['RCC_AHB1RSTR_DMA1RST_Msk',['../group___peripheral___registers___bits___definition.html#ga9c336fca84fc656b8412d0a0dab8317e',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb1rstr_5fdma1rst_5fpos_133',['RCC_AHB1RSTR_DMA1RST_Pos',['../group___peripheral___registers___bits___definition.html#ga577ac0ee66f5e320ea4450234e709a03',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb1rstr_5fdma2rst_134',['RCC_AHB1RSTR_DMA2RST',['../group___peripheral___registers___bits___definition.html#ga827aea44c35a0c3eb815a5d7d8546c7b',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb1rstr_5fdma2rst_5fmsk_135',['RCC_AHB1RSTR_DMA2RST_Msk',['../group___peripheral___registers___bits___definition.html#gae5e2d5af9f21f5df26e53863392f46ce',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb1rstr_5fdma2rst_5fpos_136',['RCC_AHB1RSTR_DMA2RST_Pos',['../group___peripheral___registers___bits___definition.html#ga16e38f17a99cc2e1f91d622f11ac8c89',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb1rstr_5fethmacrst_137',['RCC_AHB1RSTR_ETHMACRST',['../group___peripheral___registers___bits___definition.html#ga1e1dca7f08a971d2c3bf39a928c49586',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb1rstr_5fethmacrst_5fmsk_138',['RCC_AHB1RSTR_ETHMACRST_Msk',['../group___peripheral___registers___bits___definition.html#ga9c088bbef40582644da68cebbce2c455',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb1rstr_5fethmacrst_5fpos_139',['RCC_AHB1RSTR_ETHMACRST_Pos',['../group___peripheral___registers___bits___definition.html#ga9e5a9384f957af95226d03414e7500e3',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb1rstr_5fgpioarst_140',['RCC_AHB1RSTR_GPIOARST',['../group___peripheral___registers___bits___definition.html#ga6c171937e46c2b9a58f16ee82010509e',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb1rstr_5fgpioarst_5fmsk_141',['RCC_AHB1RSTR_GPIOARST_Msk',['../group___peripheral___registers___bits___definition.html#ga1ca733a89ed0ddeb8c6ad7d4df334baf',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb1rstr_5fgpioarst_5fpos_142',['RCC_AHB1RSTR_GPIOARST_Pos',['../group___peripheral___registers___bits___definition.html#gac1a30c30184844a5d3a71f73669375e7',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb1rstr_5fgpiobrst_143',['RCC_AHB1RSTR_GPIOBRST',['../group___peripheral___registers___bits___definition.html#ga8e60d32cb67768339fc47a2ba11b7a97',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb1rstr_5fgpiobrst_5fmsk_144',['RCC_AHB1RSTR_GPIOBRST_Msk',['../group___peripheral___registers___bits___definition.html#ga70a227671a2b417929ad0959d9e899c8',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb1rstr_5fgpiobrst_5fpos_145',['RCC_AHB1RSTR_GPIOBRST_Pos',['../group___peripheral___registers___bits___definition.html#ga3154d462e29e472394d62113b4a3fadc',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb1rstr_5fgpiocrst_146',['RCC_AHB1RSTR_GPIOCRST',['../group___peripheral___registers___bits___definition.html#ga8d02a09e1dafda744c7b27dca99fa3ef',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb1rstr_5fgpiocrst_5fmsk_147',['RCC_AHB1RSTR_GPIOCRST_Msk',['../group___peripheral___registers___bits___definition.html#ga1f25d081a1bb38f34f8d11fc32bdc7d7',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb1rstr_5fgpiocrst_5fpos_148',['RCC_AHB1RSTR_GPIOCRST_Pos',['../group___peripheral___registers___bits___definition.html#ga23de6a59e935f9e205e35aa713204d77',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb1rstr_5fgpiodrst_149',['RCC_AHB1RSTR_GPIODRST',['../group___peripheral___registers___bits___definition.html#gad16f3ce75bba03d8de4f5bc89c561337',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb1rstr_5fgpiodrst_5fmsk_150',['RCC_AHB1RSTR_GPIODRST_Msk',['../group___peripheral___registers___bits___definition.html#ga45e4b57d9e0d9c72055b51a222d388f5',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb1rstr_5fgpiodrst_5fpos_151',['RCC_AHB1RSTR_GPIODRST_Pos',['../group___peripheral___registers___bits___definition.html#ga296b1b5d6eaac638fc714115bb8fb79b',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb1rstr_5fgpioerst_152',['RCC_AHB1RSTR_GPIOERST',['../group___peripheral___registers___bits___definition.html#gad9baeb0fd247300501274a9259a4b184',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb1rstr_5fgpioerst_5fmsk_153',['RCC_AHB1RSTR_GPIOERST_Msk',['../group___peripheral___registers___bits___definition.html#ga2330cc824d6e097fc95f311730778243',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb1rstr_5fgpioerst_5fpos_154',['RCC_AHB1RSTR_GPIOERST_Pos',['../group___peripheral___registers___bits___definition.html#gac9d31d86453dfa221ced7ff4668a4b40',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb1rstr_5fgpiofrst_155',['RCC_AHB1RSTR_GPIOFRST',['../group___peripheral___registers___bits___definition.html#gab00b21dc4408295d374a4970ea5ae751',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb1rstr_5fgpiofrst_5fmsk_156',['RCC_AHB1RSTR_GPIOFRST_Msk',['../group___peripheral___registers___bits___definition.html#gae5758110647b39258af5b6c4259a59c0',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb1rstr_5fgpiofrst_5fpos_157',['RCC_AHB1RSTR_GPIOFRST_Pos',['../group___peripheral___registers___bits___definition.html#gabc279604f2a9a7f4bc29702d784cf22c',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb1rstr_5fgpiogrst_158',['RCC_AHB1RSTR_GPIOGRST',['../group___peripheral___registers___bits___definition.html#ga50322b0db25b2204aa114c4c29847051',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb1rstr_5fgpiogrst_5fmsk_159',['RCC_AHB1RSTR_GPIOGRST_Msk',['../group___peripheral___registers___bits___definition.html#ga7ca12c8d01be2d47518003a30d836a68',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb1rstr_5fgpiogrst_5fpos_160',['RCC_AHB1RSTR_GPIOGRST_Pos',['../group___peripheral___registers___bits___definition.html#ga5b38704ba9c53025641de7d5ed93add4',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb1rstr_5fgpiohrst_161',['RCC_AHB1RSTR_GPIOHRST',['../group___peripheral___registers___bits___definition.html#ga587e3e32701cbd127d2afb19b9bff5fd',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb1rstr_5fgpiohrst_5fmsk_162',['RCC_AHB1RSTR_GPIOHRST_Msk',['../group___peripheral___registers___bits___definition.html#gaa6853aabc577ec17d0d7f894e520a693',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb1rstr_5fgpiohrst_5fpos_163',['RCC_AHB1RSTR_GPIOHRST_Pos',['../group___peripheral___registers___bits___definition.html#gada3768676df15e5d248404ba29df27ce',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb1rstr_5fgpioirst_164',['RCC_AHB1RSTR_GPIOIRST',['../group___peripheral___registers___bits___definition.html#gab5180658a02a87b501ab3f250593905b',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb1rstr_5fgpioirst_5fmsk_165',['RCC_AHB1RSTR_GPIOIRST_Msk',['../group___peripheral___registers___bits___definition.html#gad771106a6653644a43c7d3d572d70220',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb1rstr_5fgpioirst_5fpos_166',['RCC_AHB1RSTR_GPIOIRST_Pos',['../group___peripheral___registers___bits___definition.html#gacf265743558660a1035f0456bede8322',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb1rstr_5fotghrst_167',['RCC_AHB1RSTR_OTGHRST',['../group___peripheral___registers___bits___definition.html#ga236682929d2641e851f175ab3aa1f520',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb1rstr_5fotghrst_5fmsk_168',['RCC_AHB1RSTR_OTGHRST_Msk',['../group___peripheral___registers___bits___definition.html#ga351abffe0a0e32b6e74378a5e4b82a9e',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb1rstr_5fotghrst_5fpos_169',['RCC_AHB1RSTR_OTGHRST_Pos',['../group___peripheral___registers___bits___definition.html#ga355532707d1260d362e518e645be8753',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb2_5fsupport_170',['RCC_AHB2_SUPPORT',['../group___peripheral___registers___bits___definition.html#gad47614352bcc5025572abc4277cf28e9',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb2enr_5fdcmien_171',['RCC_AHB2ENR_DCMIEN',['../group___peripheral___registers___bits___definition.html#gafe6b7edde44307072327fcae3c15c8d0',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb2enr_5fdcmien_5fmsk_172',['RCC_AHB2ENR_DCMIEN_Msk',['../group___peripheral___registers___bits___definition.html#ga392371f5ae1fc6417aa8111e46184b17',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb2enr_5fdcmien_5fpos_173',['RCC_AHB2ENR_DCMIEN_Pos',['../group___peripheral___registers___bits___definition.html#ga2491b75f6353ed39e93a2c9e8ea81052',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb2enr_5fotgfsen_174',['RCC_AHB2ENR_OTGFSEN',['../group___peripheral___registers___bits___definition.html#ga22576caeba7c7a1e6afdd0b90394c76d',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb2enr_5fotgfsen_5fmsk_175',['RCC_AHB2ENR_OTGFSEN_Msk',['../group___peripheral___registers___bits___definition.html#ga9c92c5e4271a2a493a92fb41fbc7e3fd',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb2enr_5fotgfsen_5fpos_176',['RCC_AHB2ENR_OTGFSEN_Pos',['../group___peripheral___registers___bits___definition.html#ga80a6b042ea1a1362cba76f697a2b941c',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb2enr_5frngen_177',['RCC_AHB2ENR_RNGEN',['../group___peripheral___registers___bits___definition.html#gadea5123ece7df53e695697e3a7d11a6b',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb2enr_5frngen_5fmsk_178',['RCC_AHB2ENR_RNGEN_Msk',['../group___peripheral___registers___bits___definition.html#gabe2170ecd918ffe5d888e76c3dcd5cab',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb2enr_5frngen_5fpos_179',['RCC_AHB2ENR_RNGEN_Pos',['../group___peripheral___registers___bits___definition.html#gadf92e60b54c63999846b0e8392131a6c',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb2lpenr_5fdcmilpen_180',['RCC_AHB2LPENR_DCMILPEN',['../group___peripheral___registers___bits___definition.html#ga51ec4f41dcfdedeedef75a64ec65863a',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb2lpenr_5fdcmilpen_5fmsk_181',['RCC_AHB2LPENR_DCMILPEN_Msk',['../group___peripheral___registers___bits___definition.html#ga9e9e48b4b6b730a3fc71ecc7bad6f4c7',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb2lpenr_5fdcmilpen_5fpos_182',['RCC_AHB2LPENR_DCMILPEN_Pos',['../group___peripheral___registers___bits___definition.html#ga88eed976ee3304bdf4ba0a514d2f9d17',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb2lpenr_5fotgfslpen_183',['RCC_AHB2LPENR_OTGFSLPEN',['../group___peripheral___registers___bits___definition.html#gac0fd858d073b14216ae0d716ba4f1dd3',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb2lpenr_5fotgfslpen_5fmsk_184',['RCC_AHB2LPENR_OTGFSLPEN_Msk',['../group___peripheral___registers___bits___definition.html#ga235d86e1b22afa92651c1cb0c31660cd',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb2lpenr_5fotgfslpen_5fpos_185',['RCC_AHB2LPENR_OTGFSLPEN_Pos',['../group___peripheral___registers___bits___definition.html#gad3383a619f30eef365e0f6031aaf2423',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb2lpenr_5frnglpen_186',['RCC_AHB2LPENR_RNGLPEN',['../group___peripheral___registers___bits___definition.html#gaab54623c517f1450a7fde279c2cae864',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb2lpenr_5frnglpen_5fmsk_187',['RCC_AHB2LPENR_RNGLPEN_Msk',['../group___peripheral___registers___bits___definition.html#ga082f00df13212bc37c2528b69330a304',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb2lpenr_5frnglpen_5fpos_188',['RCC_AHB2LPENR_RNGLPEN_Pos',['../group___peripheral___registers___bits___definition.html#gad53ba64643a3daa4220a3515ae089822',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb2rstr_5fdcmirst_189',['RCC_AHB2RSTR_DCMIRST',['../group___peripheral___registers___bits___definition.html#gae909f90338c129e116b7d49bebfb31c5',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb2rstr_5fdcmirst_5fmsk_190',['RCC_AHB2RSTR_DCMIRST_Msk',['../group___peripheral___registers___bits___definition.html#gad65d3d99d10ccb38170740b9dbc30f0f',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb2rstr_5fdcmirst_5fpos_191',['RCC_AHB2RSTR_DCMIRST_Pos',['../group___peripheral___registers___bits___definition.html#ga457063d004551e2cce80472b190372c2',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb2rstr_5fotgfsrst_192',['RCC_AHB2RSTR_OTGFSRST',['../group___peripheral___registers___bits___definition.html#gae1b8b894a2f1ea24b4799c7a30abbb5a',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb2rstr_5fotgfsrst_5fmsk_193',['RCC_AHB2RSTR_OTGFSRST_Msk',['../group___peripheral___registers___bits___definition.html#gacba439d5c37535fc904630d55dd8d204',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb2rstr_5fotgfsrst_5fpos_194',['RCC_AHB2RSTR_OTGFSRST_Pos',['../group___peripheral___registers___bits___definition.html#ga5f5fe9c74c695fe79917ce4828d2e24b',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb2rstr_5frngrst_195',['RCC_AHB2RSTR_RNGRST',['../group___peripheral___registers___bits___definition.html#gace46c6461c8b4ddd78510bc2c529c91b',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb2rstr_5frngrst_5fmsk_196',['RCC_AHB2RSTR_RNGRST_Msk',['../group___peripheral___registers___bits___definition.html#ga7ac557e9b39e599539fb5cc2a100de60',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb2rstr_5frngrst_5fpos_197',['RCC_AHB2RSTR_RNGRST_Pos',['../group___peripheral___registers___bits___definition.html#gaadeefbc7de6773eedfba70fb6cd83890',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb3_5fsupport_198',['RCC_AHB3_SUPPORT',['../group___peripheral___registers___bits___definition.html#gab59e70532c57e0a7917acac00de9db57',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb3enr_5ffsmcen_199',['RCC_AHB3ENR_FSMCEN',['../group___peripheral___registers___bits___definition.html#ga30d723abc39a230a71760dff91bb6d7b',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb3enr_5ffsmcen_5fmsk_200',['RCC_AHB3ENR_FSMCEN_Msk',['../group___peripheral___registers___bits___definition.html#ga518c0730a8f98a8b8ed6f75f0101f7fb',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb3enr_5ffsmcen_5fpos_201',['RCC_AHB3ENR_FSMCEN_Pos',['../group___peripheral___registers___bits___definition.html#gaa90ab430537857e2683deb2c628a4ca7',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb3lpenr_5ffsmclpen_202',['RCC_AHB3LPENR_FSMCLPEN',['../group___peripheral___registers___bits___definition.html#gabf56147909fa8e7f8629c7fd7349ecb3',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb3lpenr_5ffsmclpen_5fmsk_203',['RCC_AHB3LPENR_FSMCLPEN_Msk',['../group___peripheral___registers___bits___definition.html#ga7d006571ef2ef5c0fb68621fdb5835b7',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb3lpenr_5ffsmclpen_5fpos_204',['RCC_AHB3LPENR_FSMCLPEN_Pos',['../group___peripheral___registers___bits___definition.html#ga25502d2b4fe408f7fb0238bbe4595754',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb3rstr_5ffsmcrst_205',['RCC_AHB3RSTR_FSMCRST',['../group___peripheral___registers___bits___definition.html#ga915aa42b819649f5ee7abdf5319d6bb8',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb3rstr_5ffsmcrst_5fmsk_206',['RCC_AHB3RSTR_FSMCRST_Msk',['../group___peripheral___registers___bits___definition.html#gab498285653979d8739b94dcbe1a32048',1,'stm32f407xx_matlab.h']]], - ['rcc_5fahb3rstr_5ffsmcrst_5fpos_207',['RCC_AHB3RSTR_FSMCRST_Pos',['../group___peripheral___registers___bits___definition.html#ga3aa38c40a38fe2a2e7d7bb26cdbfff36',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1enr_5fcan1en_208',['RCC_APB1ENR_CAN1EN',['../group___peripheral___registers___bits___definition.html#ga66b5172158cf0170d29091064ea63a29',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1enr_5fcan1en_5fmsk_209',['RCC_APB1ENR_CAN1EN_Msk',['../group___peripheral___registers___bits___definition.html#ga8adf13f0648b09c215dfd69d3ef933b5',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1enr_5fcan1en_5fpos_210',['RCC_APB1ENR_CAN1EN_Pos',['../group___peripheral___registers___bits___definition.html#gad1a9a8c0f5081081046044070e17d93b',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1enr_5fcan2en_211',['RCC_APB1ENR_CAN2EN',['../group___peripheral___registers___bits___definition.html#gae64f792b7a3401cff4d95e31d3867422',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1enr_5fcan2en_5fmsk_212',['RCC_APB1ENR_CAN2EN_Msk',['../group___peripheral___registers___bits___definition.html#ga4bffa56c0080897dc6cbe28ad888f22b',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1enr_5fcan2en_5fpos_213',['RCC_APB1ENR_CAN2EN_Pos',['../group___peripheral___registers___bits___definition.html#gace880a61cc0e55b67c8d4bf47374cf49',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1enr_5fdacen_214',['RCC_APB1ENR_DACEN',['../group___peripheral___registers___bits___definition.html#ga087968e2786321fb8645c46b22eea132',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1enr_5fdacen_5fmsk_215',['RCC_APB1ENR_DACEN_Msk',['../group___peripheral___registers___bits___definition.html#gacd51394bb1f7c10cef36c5dd2e19766d',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1enr_5fdacen_5fpos_216',['RCC_APB1ENR_DACEN_Pos',['../group___peripheral___registers___bits___definition.html#gac7982505dca41bc51c29dcdcc03eb789',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1enr_5fi2c1en_217',['RCC_APB1ENR_I2C1EN',['../group___peripheral___registers___bits___definition.html#ga5ca3afe0c517702b2d1366b692c8db0e',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1enr_5fi2c1en_5fmsk_218',['RCC_APB1ENR_I2C1EN_Msk',['../group___peripheral___registers___bits___definition.html#ga2b2a4e92cb0eba09a147ee9770195eee',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1enr_5fi2c1en_5fpos_219',['RCC_APB1ENR_I2C1EN_Pos',['../group___peripheral___registers___bits___definition.html#ga0f1cab341f8320372dfd95bce3d2d918',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1enr_5fi2c2en_220',['RCC_APB1ENR_I2C2EN',['../group___peripheral___registers___bits___definition.html#gafd7d1c3c7dbe20aea87a694ae15840f6',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1enr_5fi2c2en_5fmsk_221',['RCC_APB1ENR_I2C2EN_Msk',['../group___peripheral___registers___bits___definition.html#gadb344f4fbe0d1286860e8c47f73339ce',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1enr_5fi2c2en_5fpos_222',['RCC_APB1ENR_I2C2EN_Pos',['../group___peripheral___registers___bits___definition.html#ga94ad0c869b4e644dacba6b170797fcf6',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1enr_5fi2c3en_223',['RCC_APB1ENR_I2C3EN',['../group___peripheral___registers___bits___definition.html#ga96621806b8fb96891efa9364e370f3f7',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1enr_5fi2c3en_5fmsk_224',['RCC_APB1ENR_I2C3EN_Msk',['../group___peripheral___registers___bits___definition.html#ga3287ea960eceb4499698cfc8e4ffbf36',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1enr_5fi2c3en_5fpos_225',['RCC_APB1ENR_I2C3EN_Pos',['../group___peripheral___registers___bits___definition.html#ga007431fc8e6cbe66fff71273e9245ad3',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1enr_5fpwren_226',['RCC_APB1ENR_PWREN',['../group___peripheral___registers___bits___definition.html#ga5c19997ccd28464b80a7c3325da0ca60',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1enr_5fpwren_5fmsk_227',['RCC_APB1ENR_PWREN_Msk',['../group___peripheral___registers___bits___definition.html#ga4ba08580eae539419497cdd62c530bad',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1enr_5fpwren_5fpos_228',['RCC_APB1ENR_PWREN_Pos',['../group___peripheral___registers___bits___definition.html#ga9d869630ea19b70ec5c740cc6b37f49c',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1enr_5fspi2en_229',['RCC_APB1ENR_SPI2EN',['../group___peripheral___registers___bits___definition.html#gafdce64692c44bf95efbf2fed054e59be',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1enr_5fspi2en_5fmsk_230',['RCC_APB1ENR_SPI2EN_Msk',['../group___peripheral___registers___bits___definition.html#ga5fd0ff191b4b6253b499258e4625cc65',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1enr_5fspi2en_5fpos_231',['RCC_APB1ENR_SPI2EN_Pos',['../group___peripheral___registers___bits___definition.html#gaea7eb0710266a43edcd813440b159f8e',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1enr_5fspi3en_232',['RCC_APB1ENR_SPI3EN',['../group___peripheral___registers___bits___definition.html#ga8757f8d1e1ff1447e08e5abea4615083',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1enr_5fspi3en_5fmsk_233',['RCC_APB1ENR_SPI3EN_Msk',['../group___peripheral___registers___bits___definition.html#ga3852cf58a863e5b0133d5bc84bcede3f',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1enr_5fspi3en_5fpos_234',['RCC_APB1ENR_SPI3EN_Pos',['../group___peripheral___registers___bits___definition.html#ga59915518ddf7e60fc5da8072b3ce6dd9',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1enr_5ftim12en_235',['RCC_APB1ENR_TIM12EN',['../group___peripheral___registers___bits___definition.html#gaecd88b56485ee4ee3e406b1d6c062081',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1enr_5ftim12en_5fmsk_236',['RCC_APB1ENR_TIM12EN_Msk',['../group___peripheral___registers___bits___definition.html#gabca933b42794cadbf3580851e625779e',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1enr_5ftim12en_5fpos_237',['RCC_APB1ENR_TIM12EN_Pos',['../group___peripheral___registers___bits___definition.html#gaec84991ddba58f7037cd8113725a26f7',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1enr_5ftim13en_238',['RCC_APB1ENR_TIM13EN',['../group___peripheral___registers___bits___definition.html#ga1a95079e68e7c76584ef0b3de371288a',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1enr_5ftim13en_5fmsk_239',['RCC_APB1ENR_TIM13EN_Msk',['../group___peripheral___registers___bits___definition.html#ga7c6f74911cd1852c3a58e969e48013d8',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1enr_5ftim13en_5fpos_240',['RCC_APB1ENR_TIM13EN_Pos',['../group___peripheral___registers___bits___definition.html#ga3865266fac7bea00e89cd1c19eb3b39f',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1enr_5ftim14en_241',['RCC_APB1ENR_TIM14EN',['../group___peripheral___registers___bits___definition.html#gaca040bd66d4a54d4d9e9b261c8102799',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1enr_5ftim14en_5fmsk_242',['RCC_APB1ENR_TIM14EN_Msk',['../group___peripheral___registers___bits___definition.html#gaecb332ea40285657d968307a8cef8951',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1enr_5ftim14en_5fpos_243',['RCC_APB1ENR_TIM14EN_Pos',['../group___peripheral___registers___bits___definition.html#ga3341bca36df7d92a24e7e1355265421c',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1enr_5ftim2en_244',['RCC_APB1ENR_TIM2EN',['../group___peripheral___registers___bits___definition.html#gacd3966a4d6ae47f06b3c095eaf26a610',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1enr_5ftim2en_5fmsk_245',['RCC_APB1ENR_TIM2EN_Msk',['../group___peripheral___registers___bits___definition.html#ga7ed542e8a186c731ad3221c61b4aa81a',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1enr_5ftim2en_5fpos_246',['RCC_APB1ENR_TIM2EN_Pos',['../group___peripheral___registers___bits___definition.html#gaa7c1e030bdf85faeae65b74850497e29',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1enr_5ftim3en_247',['RCC_APB1ENR_TIM3EN',['../group___peripheral___registers___bits___definition.html#ga75bfa33eb00ee30c6e22f7ceea464ac7',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1enr_5ftim3en_5fmsk_248',['RCC_APB1ENR_TIM3EN_Msk',['../group___peripheral___registers___bits___definition.html#ga39d58d377cd38e5685344b7d9a88ce1c',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1enr_5ftim3en_5fpos_249',['RCC_APB1ENR_TIM3EN_Pos',['../group___peripheral___registers___bits___definition.html#ga512bf591e0527e83b8ae823c42da2f1e',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1enr_5ftim4en_250',['RCC_APB1ENR_TIM4EN',['../group___peripheral___registers___bits___definition.html#gad4fbbf6b1beeec92c7d80e9e05bd1461',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1enr_5ftim4en_5fmsk_251',['RCC_APB1ENR_TIM4EN_Msk',['../group___peripheral___registers___bits___definition.html#gaef489da1fe7bd776d2fc27eb689fd9c4',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1enr_5ftim4en_5fpos_252',['RCC_APB1ENR_TIM4EN_Pos',['../group___peripheral___registers___bits___definition.html#gad32ced9621c44cd74f36cbfdec22582e',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1enr_5ftim5en_253',['RCC_APB1ENR_TIM5EN',['../group___peripheral___registers___bits___definition.html#ga49abbbc8fd297c544df2d337b28f80e4',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1enr_5ftim5en_5fmsk_254',['RCC_APB1ENR_TIM5EN_Msk',['../group___peripheral___registers___bits___definition.html#ga50e3f7f788191131f045cd40594e5c15',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1enr_5ftim5en_5fpos_255',['RCC_APB1ENR_TIM5EN_Pos',['../group___peripheral___registers___bits___definition.html#ga9022ea1b9729864c70216a4f04326f22',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1enr_5ftim6en_256',['RCC_APB1ENR_TIM6EN',['../group___peripheral___registers___bits___definition.html#gafb0279b1f0ff35c2df728d9653cabc0c',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1enr_5ftim6en_5fmsk_257',['RCC_APB1ENR_TIM6EN_Msk',['../group___peripheral___registers___bits___definition.html#ga34240ad1a5f4eb5ed19e7104da631d1e',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1enr_5ftim6en_5fpos_258',['RCC_APB1ENR_TIM6EN_Pos',['../group___peripheral___registers___bits___definition.html#gae48475ae28539f1a2ce3852fbd7c1e71',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1enr_5ftim7en_259',['RCC_APB1ENR_TIM7EN',['../group___peripheral___registers___bits___definition.html#gab595fbaf4167297d8fe2825e41f41990',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1enr_5ftim7en_5fmsk_260',['RCC_APB1ENR_TIM7EN_Msk',['../group___peripheral___registers___bits___definition.html#ga6d3160c7aa3480db783e4cc7f50ed721',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1enr_5ftim7en_5fpos_261',['RCC_APB1ENR_TIM7EN_Pos',['../group___peripheral___registers___bits___definition.html#ga4c3d0403cb8a2a9daa5f789e3547d27d',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1enr_5fuart4en_262',['RCC_APB1ENR_UART4EN',['../group___peripheral___registers___bits___definition.html#gae6b0fe571aa29ed30389f87bdbf37b46',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1enr_5fuart4en_5fmsk_263',['RCC_APB1ENR_UART4EN_Msk',['../group___peripheral___registers___bits___definition.html#ga33f02158e2eaba91c9cbc6e499aa4471',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1enr_5fuart4en_5fpos_264',['RCC_APB1ENR_UART4EN_Pos',['../group___peripheral___registers___bits___definition.html#gadad62b6567db40949d10c876718780f6',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1enr_5fuart5en_265',['RCC_APB1ENR_UART5EN',['../group___peripheral___registers___bits___definition.html#ga24a9eea153892405f53007f521efee2e',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1enr_5fuart5en_5fmsk_266',['RCC_APB1ENR_UART5EN_Msk',['../group___peripheral___registers___bits___definition.html#gab01815c1b0ced6d002d1b7590e9b8b15',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1enr_5fuart5en_5fpos_267',['RCC_APB1ENR_UART5EN_Pos',['../group___peripheral___registers___bits___definition.html#ga99f56067e63f26f0ecb64bdf36be19df',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1enr_5fusart2en_268',['RCC_APB1ENR_USART2EN',['../group___peripheral___registers___bits___definition.html#gab840af4f735ec36419d61c7db3cfa00d',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1enr_5fusart2en_5fmsk_269',['RCC_APB1ENR_USART2EN_Msk',['../group___peripheral___registers___bits___definition.html#ga510e179108a8914b0830b1ff30951caf',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1enr_5fusart2en_5fpos_270',['RCC_APB1ENR_USART2EN_Pos',['../group___peripheral___registers___bits___definition.html#ga9a410d2ae7f9133227d2a35cde9188d6',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1enr_5fusart3en_271',['RCC_APB1ENR_USART3EN',['../group___peripheral___registers___bits___definition.html#ga8033e0312aea02ae7eb2d57da13e8298',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1enr_5fusart3en_5fmsk_272',['RCC_APB1ENR_USART3EN_Msk',['../group___peripheral___registers___bits___definition.html#gac98f52fa1ae42a405334a2cc84f993b2',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1enr_5fusart3en_5fpos_273',['RCC_APB1ENR_USART3EN_Pos',['../group___peripheral___registers___bits___definition.html#ga5bfba28e5987744972af99c83dfd0a68',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1enr_5fwwdgen_274',['RCC_APB1ENR_WWDGEN',['../group___peripheral___registers___bits___definition.html#gaf712b922ee776a972d2efa3da0ea4733',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1enr_5fwwdgen_5fmsk_275',['RCC_APB1ENR_WWDGEN_Msk',['../group___peripheral___registers___bits___definition.html#ga09ad274a2f953fdb7c7ce0e6d69e8798',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1enr_5fwwdgen_5fpos_276',['RCC_APB1ENR_WWDGEN_Pos',['../group___peripheral___registers___bits___definition.html#gaf3fd18a8801d86093018dfe2ea3b2b4a',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1lpenr_5fcan1lpen_277',['RCC_APB1LPENR_CAN1LPEN',['../group___peripheral___registers___bits___definition.html#gafb93b42a94b988f4a03bed9ea78b4519',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1lpenr_5fcan1lpen_5fmsk_278',['RCC_APB1LPENR_CAN1LPEN_Msk',['../group___peripheral___registers___bits___definition.html#ga8b99fe06fe55b8c9df8e192df0caf4fa',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1lpenr_5fcan1lpen_5fpos_279',['RCC_APB1LPENR_CAN1LPEN_Pos',['../group___peripheral___registers___bits___definition.html#ga6f780db5faed548d72f11abf461502e6',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1lpenr_5fcan2lpen_280',['RCC_APB1LPENR_CAN2LPEN',['../group___peripheral___registers___bits___definition.html#ga167ad9fc43674d6993a9550ac3b6e70f',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1lpenr_5fcan2lpen_5fmsk_281',['RCC_APB1LPENR_CAN2LPEN_Msk',['../group___peripheral___registers___bits___definition.html#ga6da195ab0281bf251ae19040f072b8ac',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1lpenr_5fcan2lpen_5fpos_282',['RCC_APB1LPENR_CAN2LPEN_Pos',['../group___peripheral___registers___bits___definition.html#gaee1a0ced3d5d4088ba28a34e150ffaee',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1lpenr_5fdaclpen_283',['RCC_APB1LPENR_DACLPEN',['../group___peripheral___registers___bits___definition.html#gaf36a11e89644548702385d548f3f9ec4',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1lpenr_5fdaclpen_5fmsk_284',['RCC_APB1LPENR_DACLPEN_Msk',['../group___peripheral___registers___bits___definition.html#gaecbfaa2f91227a9bdb7c6dcabddb75c7',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1lpenr_5fdaclpen_5fpos_285',['RCC_APB1LPENR_DACLPEN_Pos',['../group___peripheral___registers___bits___definition.html#gad83f868ee37a8885c4ff2e293e4df4f6',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1lpenr_5fi2c1lpen_286',['RCC_APB1LPENR_I2C1LPEN',['../group___peripheral___registers___bits___definition.html#ga33286469d0a9b9fedbc2b60aa6cd7da7',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1lpenr_5fi2c1lpen_5fmsk_287',['RCC_APB1LPENR_I2C1LPEN_Msk',['../group___peripheral___registers___bits___definition.html#ga1afe0c2a2e36921403357bb10f168790',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1lpenr_5fi2c1lpen_5fpos_288',['RCC_APB1LPENR_I2C1LPEN_Pos',['../group___peripheral___registers___bits___definition.html#ga3a099cd3cde1ab16cb0a8805d15df425',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1lpenr_5fi2c2lpen_289',['RCC_APB1LPENR_I2C2LPEN',['../group___peripheral___registers___bits___definition.html#gaf6a53d37df11a56412ae06f73626f637',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1lpenr_5fi2c2lpen_5fmsk_290',['RCC_APB1LPENR_I2C2LPEN_Msk',['../group___peripheral___registers___bits___definition.html#ga76e2c1200c865395531d57931327097d',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1lpenr_5fi2c2lpen_5fpos_291',['RCC_APB1LPENR_I2C2LPEN_Pos',['../group___peripheral___registers___bits___definition.html#gaede8bc79a31bfe414f4c9bb6829b5804',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1lpenr_5fi2c3lpen_292',['RCC_APB1LPENR_I2C3LPEN',['../group___peripheral___registers___bits___definition.html#ga5abf01e4149d71e8427eefcd2e429fe9',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1lpenr_5fi2c3lpen_5fmsk_293',['RCC_APB1LPENR_I2C3LPEN_Msk',['../group___peripheral___registers___bits___definition.html#ga336e724329c3f2adaba3ed13af63de09',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1lpenr_5fi2c3lpen_5fpos_294',['RCC_APB1LPENR_I2C3LPEN_Pos',['../group___peripheral___registers___bits___definition.html#ga59cb6740257f6c8f1a40b9ce6e5bf498',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1lpenr_5fpwrlpen_295',['RCC_APB1LPENR_PWRLPEN',['../group___peripheral___registers___bits___definition.html#ga274fa282ad1ff40b747644bf9360feb4',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1lpenr_5fpwrlpen_5fmsk_296',['RCC_APB1LPENR_PWRLPEN_Msk',['../group___peripheral___registers___bits___definition.html#ga653ef9d97213f971b3ace653a8f7f4f0',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1lpenr_5fpwrlpen_5fpos_297',['RCC_APB1LPENR_PWRLPEN_Pos',['../group___peripheral___registers___bits___definition.html#ga67fd356139c695e461be99af8aafa297',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1lpenr_5fspi2lpen_298',['RCC_APB1LPENR_SPI2LPEN',['../group___peripheral___registers___bits___definition.html#ga41dcbf845448cbb1b75c0ad7e83b77cb',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1lpenr_5fspi2lpen_5fmsk_299',['RCC_APB1LPENR_SPI2LPEN_Msk',['../group___peripheral___registers___bits___definition.html#gada9dd21c62e16d73115a855bffc5a98a',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1lpenr_5fspi2lpen_5fpos_300',['RCC_APB1LPENR_SPI2LPEN_Pos',['../group___peripheral___registers___bits___definition.html#ga6c7bc3dcdc95f9245977cc4de874bb1f',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1lpenr_5fspi3lpen_301',['RCC_APB1LPENR_SPI3LPEN',['../group___peripheral___registers___bits___definition.html#gae8acbff235a15b58d1be0f065cdb5472',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1lpenr_5fspi3lpen_5fmsk_302',['RCC_APB1LPENR_SPI3LPEN_Msk',['../group___peripheral___registers___bits___definition.html#ga7a00b05657ebd904eb04349ce6625799',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1lpenr_5fspi3lpen_5fpos_303',['RCC_APB1LPENR_SPI3LPEN_Pos',['../group___peripheral___registers___bits___definition.html#gaf82b15d2ca1965ca72eb372345bb4dc1',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1lpenr_5ftim12lpen_304',['RCC_APB1LPENR_TIM12LPEN',['../group___peripheral___registers___bits___definition.html#ga3b47fde44967a5a600a042398a9cf3c6',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1lpenr_5ftim12lpen_5fmsk_305',['RCC_APB1LPENR_TIM12LPEN_Msk',['../group___peripheral___registers___bits___definition.html#gafe9cf962cc29a62ff4cc27ac9984f1d1',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1lpenr_5ftim12lpen_5fpos_306',['RCC_APB1LPENR_TIM12LPEN_Pos',['../group___peripheral___registers___bits___definition.html#ga5108a41416096f47d46c7fd69e810e50',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1lpenr_5ftim13lpen_307',['RCC_APB1LPENR_TIM13LPEN',['../group___peripheral___registers___bits___definition.html#ga9897d5f0033623a05997ca222d3a132b',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1lpenr_5ftim13lpen_5fmsk_308',['RCC_APB1LPENR_TIM13LPEN_Msk',['../group___peripheral___registers___bits___definition.html#ga5df15d5e47024a72fe127a81d8a2e3cf',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1lpenr_5ftim13lpen_5fpos_309',['RCC_APB1LPENR_TIM13LPEN_Pos',['../group___peripheral___registers___bits___definition.html#gaa2d2664523f65db375f5883e6fba692c',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1lpenr_5ftim14lpen_310',['RCC_APB1LPENR_TIM14LPEN',['../group___peripheral___registers___bits___definition.html#gacd1af8912fedadb9edead5b31167a310',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1lpenr_5ftim14lpen_5fmsk_311',['RCC_APB1LPENR_TIM14LPEN_Msk',['../group___peripheral___registers___bits___definition.html#ga8e28132e6a8eb793e4e21b4334c56ee7',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1lpenr_5ftim14lpen_5fpos_312',['RCC_APB1LPENR_TIM14LPEN_Pos',['../group___peripheral___registers___bits___definition.html#ga7a961758cd246c0ef98ffbb703feef88',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1lpenr_5ftim2lpen_313',['RCC_APB1LPENR_TIM2LPEN',['../group___peripheral___registers___bits___definition.html#ga1f561f8bfc556b52335ec2a32ba81c44',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1lpenr_5ftim2lpen_5fmsk_314',['RCC_APB1LPENR_TIM2LPEN_Msk',['../group___peripheral___registers___bits___definition.html#ga1ef88837af2b396c012ec1225a4d8a65',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1lpenr_5ftim2lpen_5fpos_315',['RCC_APB1LPENR_TIM2LPEN_Pos',['../group___peripheral___registers___bits___definition.html#ga66d7d011a4a85de1091644162d0fea68',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1lpenr_5ftim3lpen_316',['RCC_APB1LPENR_TIM3LPEN',['../group___peripheral___registers___bits___definition.html#ga9391d99885a0a6fbaf3447117ac0f7aa',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1lpenr_5ftim3lpen_5fmsk_317',['RCC_APB1LPENR_TIM3LPEN_Msk',['../group___peripheral___registers___bits___definition.html#gab0231e0f1fbb26813e6a67b4e17d2578',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1lpenr_5ftim3lpen_5fpos_318',['RCC_APB1LPENR_TIM3LPEN_Pos',['../group___peripheral___registers___bits___definition.html#ga00f72d8c0899d67b6a428e4ed6167630',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1lpenr_5ftim4lpen_319',['RCC_APB1LPENR_TIM4LPEN',['../group___peripheral___registers___bits___definition.html#ga6f04aff278b72fbf6acbe0ad947b06ae',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1lpenr_5ftim4lpen_5fmsk_320',['RCC_APB1LPENR_TIM4LPEN_Msk',['../group___peripheral___registers___bits___definition.html#ga4a807ed1ed77d84c24ad990e689b1600',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1lpenr_5ftim4lpen_5fpos_321',['RCC_APB1LPENR_TIM4LPEN_Pos',['../group___peripheral___registers___bits___definition.html#gafaff851f048550c86bb301ed2e1dac9d',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1lpenr_5ftim5lpen_322',['RCC_APB1LPENR_TIM5LPEN',['../group___peripheral___registers___bits___definition.html#ga5741a6c45b9de1d0c927beb87f399dd9',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1lpenr_5ftim5lpen_5fmsk_323',['RCC_APB1LPENR_TIM5LPEN_Msk',['../group___peripheral___registers___bits___definition.html#ga73c7205ba8d0f5e12584ccf932efbc74',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1lpenr_5ftim5lpen_5fpos_324',['RCC_APB1LPENR_TIM5LPEN_Pos',['../group___peripheral___registers___bits___definition.html#ga93219e40400c9b6541b633c0412ac43c',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1lpenr_5ftim6lpen_325',['RCC_APB1LPENR_TIM6LPEN',['../group___peripheral___registers___bits___definition.html#ga439a5998fd60c3375411c7db2129ac89',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1lpenr_5ftim6lpen_5fmsk_326',['RCC_APB1LPENR_TIM6LPEN_Msk',['../group___peripheral___registers___bits___definition.html#gaec6b200cfb1a2c2d2dd473b4d19213b7',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1lpenr_5ftim6lpen_5fpos_327',['RCC_APB1LPENR_TIM6LPEN_Pos',['../group___peripheral___registers___bits___definition.html#ga36d3ba67d01b7993c45c0888a25ba77c',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1lpenr_5ftim7lpen_328',['RCC_APB1LPENR_TIM7LPEN',['../group___peripheral___registers___bits___definition.html#gab7867dc2695855fa9084a13d06a4299f',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1lpenr_5ftim7lpen_5fmsk_329',['RCC_APB1LPENR_TIM7LPEN_Msk',['../group___peripheral___registers___bits___definition.html#ga0e9c974f3ef148d502bb9898a230dd71',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1lpenr_5ftim7lpen_5fpos_330',['RCC_APB1LPENR_TIM7LPEN_Pos',['../group___peripheral___registers___bits___definition.html#ga32da6d7364c7a5e303c22098fd748078',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1lpenr_5fuart4lpen_331',['RCC_APB1LPENR_UART4LPEN',['../group___peripheral___registers___bits___definition.html#ga88fe1e9cf93caa4e02de35e92e55834d',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1lpenr_5fuart4lpen_5fmsk_332',['RCC_APB1LPENR_UART4LPEN_Msk',['../group___peripheral___registers___bits___definition.html#gaff134f37108abd0d043c9f62eb250bbc',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1lpenr_5fuart4lpen_5fpos_333',['RCC_APB1LPENR_UART4LPEN_Pos',['../group___peripheral___registers___bits___definition.html#gac8a9e913d67a5976a41240ccacbe6e14',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1lpenr_5fuart5lpen_334',['RCC_APB1LPENR_UART5LPEN',['../group___peripheral___registers___bits___definition.html#ga3de908135d9c9e74c598f7bf1e88fb34',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1lpenr_5fuart5lpen_5fmsk_335',['RCC_APB1LPENR_UART5LPEN_Msk',['../group___peripheral___registers___bits___definition.html#gab22aca4251bd69be2f39c31e27344975',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1lpenr_5fuart5lpen_5fpos_336',['RCC_APB1LPENR_UART5LPEN_Pos',['../group___peripheral___registers___bits___definition.html#ga4c9f855673b672b235461f4cc6480beb',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1lpenr_5fusart2lpen_337',['RCC_APB1LPENR_USART2LPEN',['../group___peripheral___registers___bits___definition.html#ga6055c39af369463e14d6ff2017043671',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1lpenr_5fusart2lpen_5fmsk_338',['RCC_APB1LPENR_USART2LPEN_Msk',['../group___peripheral___registers___bits___definition.html#gaaffb3fa84a480055b7b9547cc09ed8cb',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1lpenr_5fusart2lpen_5fpos_339',['RCC_APB1LPENR_USART2LPEN_Pos',['../group___peripheral___registers___bits___definition.html#ga36666e20226da8c9ddb2cbeb2aef1330',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1lpenr_5fusart3lpen_340',['RCC_APB1LPENR_USART3LPEN',['../group___peripheral___registers___bits___definition.html#gae11baa29f4e6d122dabdd54c6b4be052',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1lpenr_5fusart3lpen_5fmsk_341',['RCC_APB1LPENR_USART3LPEN_Msk',['../group___peripheral___registers___bits___definition.html#gabeccde78822839765663f2482e0fd3f2',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1lpenr_5fusart3lpen_5fpos_342',['RCC_APB1LPENR_USART3LPEN_Pos',['../group___peripheral___registers___bits___definition.html#ga215925022960bd4c07052109c70bc999',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1lpenr_5fwwdglpen_343',['RCC_APB1LPENR_WWDGLPEN',['../group___peripheral___registers___bits___definition.html#ga13f3db4ac67bf32c994364cc43f4fe8b',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1lpenr_5fwwdglpen_5fmsk_344',['RCC_APB1LPENR_WWDGLPEN_Msk',['../group___peripheral___registers___bits___definition.html#ga24b3760635c135839bffebcdce62aa90',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1lpenr_5fwwdglpen_5fpos_345',['RCC_APB1LPENR_WWDGLPEN_Pos',['../group___peripheral___registers___bits___definition.html#ga96ef3e58ec8ebab942b958e1efc365a2',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1rstr_5fcan1rst_346',['RCC_APB1RSTR_CAN1RST',['../group___peripheral___registers___bits___definition.html#ga23f9a8bfc02baedd992d13e489234242',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1rstr_5fcan1rst_5fmsk_347',['RCC_APB1RSTR_CAN1RST_Msk',['../group___peripheral___registers___bits___definition.html#ga91aa2d3e18674c6f02c7112da9a2e30c',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1rstr_5fcan1rst_5fpos_348',['RCC_APB1RSTR_CAN1RST_Pos',['../group___peripheral___registers___bits___definition.html#ga4ac1f35767bba5fa2ab823d17dcf9b31',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1rstr_5fcan2rst_349',['RCC_APB1RSTR_CAN2RST',['../group___peripheral___registers___bits___definition.html#ga86b5d7042e23d54c7ecfcef2fbedad6e',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1rstr_5fcan2rst_5fmsk_350',['RCC_APB1RSTR_CAN2RST_Msk',['../group___peripheral___registers___bits___definition.html#ga86dc2776b9926f9335e72b433290bb8a',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1rstr_5fcan2rst_5fpos_351',['RCC_APB1RSTR_CAN2RST_Pos',['../group___peripheral___registers___bits___definition.html#gad5695d6d01e07d1aba83edb9614fd108',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1rstr_5fdacrst_352',['RCC_APB1RSTR_DACRST',['../group___peripheral___registers___bits___definition.html#ga7fb9c125237cfe5b6436ca795e7f3564',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1rstr_5fdacrst_5fmsk_353',['RCC_APB1RSTR_DACRST_Msk',['../group___peripheral___registers___bits___definition.html#ga09759c3881f10d9210653490a651f995',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1rstr_5fdacrst_5fpos_354',['RCC_APB1RSTR_DACRST_Pos',['../group___peripheral___registers___bits___definition.html#ga0612cbad1c01508c2c3acd8502a16f76',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1rstr_5fi2c1rst_355',['RCC_APB1RSTR_I2C1RST',['../group___peripheral___registers___bits___definition.html#gadcd25346a7d7b0009090adfbca899b93',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1rstr_5fi2c1rst_5fmsk_356',['RCC_APB1RSTR_I2C1RST_Msk',['../group___peripheral___registers___bits___definition.html#ga95fda0adab6e9d4daa6417c17d905214',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1rstr_5fi2c1rst_5fpos_357',['RCC_APB1RSTR_I2C1RST_Pos',['../group___peripheral___registers___bits___definition.html#gac3f6df08a3eae853a3fc8b2d0fcc0882',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1rstr_5fi2c2rst_358',['RCC_APB1RSTR_I2C2RST',['../group___peripheral___registers___bits___definition.html#ga412d59407e5dad43cf8ae1ea6f8bc5c3',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1rstr_5fi2c2rst_5fmsk_359',['RCC_APB1RSTR_I2C2RST_Msk',['../group___peripheral___registers___bits___definition.html#ga914a46fcb3b028610d9badb471c82bd3',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1rstr_5fi2c2rst_5fpos_360',['RCC_APB1RSTR_I2C2RST_Pos',['../group___peripheral___registers___bits___definition.html#ga0a1c1f07b2b2cc274c0b297d779b936f',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1rstr_5fi2c3rst_361',['RCC_APB1RSTR_I2C3RST',['../group___peripheral___registers___bits___definition.html#gab8dd6bd89cdf6b6b7affee5594bda87f',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1rstr_5fi2c3rst_5fmsk_362',['RCC_APB1RSTR_I2C3RST_Msk',['../group___peripheral___registers___bits___definition.html#ga49214147f146965ef75c3bfa906cd3d9',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1rstr_5fi2c3rst_5fpos_363',['RCC_APB1RSTR_I2C3RST_Pos',['../group___peripheral___registers___bits___definition.html#ga53079edbe7a089db7497d49b242b7e53',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1rstr_5fpwrrst_364',['RCC_APB1RSTR_PWRRST',['../group___peripheral___registers___bits___definition.html#ga274d8cb48f0e89831efabea66d64af2a',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1rstr_5fpwrrst_5fmsk_365',['RCC_APB1RSTR_PWRRST_Msk',['../group___peripheral___registers___bits___definition.html#gabe9ed6c6cee6df40b16793fe7479ea7a',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1rstr_5fpwrrst_5fpos_366',['RCC_APB1RSTR_PWRRST_Pos',['../group___peripheral___registers___bits___definition.html#ga48d1ad283fb0cc11c6394cc28e4da4d0',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1rstr_5fspi2rst_367',['RCC_APB1RSTR_SPI2RST',['../group___peripheral___registers___bits___definition.html#ga0a6289a35547cf0d5300706f9baa18ea',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1rstr_5fspi2rst_5fmsk_368',['RCC_APB1RSTR_SPI2RST_Msk',['../group___peripheral___registers___bits___definition.html#gae378c28cf590c56f5487bd92705d6d54',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1rstr_5fspi2rst_5fpos_369',['RCC_APB1RSTR_SPI2RST_Pos',['../group___peripheral___registers___bits___definition.html#ga148b63aa15907eac1bd4894a7c157100',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1rstr_5fspi3rst_370',['RCC_APB1RSTR_SPI3RST',['../group___peripheral___registers___bits___definition.html#ga261e0f1b39cd1cab41ec6bf40c21867b',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1rstr_5fspi3rst_5fmsk_371',['RCC_APB1RSTR_SPI3RST_Msk',['../group___peripheral___registers___bits___definition.html#gae0566a08a6cbd33046ff893d7c3b7bf1',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1rstr_5fspi3rst_5fpos_372',['RCC_APB1RSTR_SPI3RST_Pos',['../group___peripheral___registers___bits___definition.html#ga9458442b1f7afb7bb8c858eceb8a7e22',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1rstr_5ftim12rst_373',['RCC_APB1RSTR_TIM12RST',['../group___peripheral___registers___bits___definition.html#ga067deb756dd4100c901c6b25229678e4',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1rstr_5ftim12rst_5fmsk_374',['RCC_APB1RSTR_TIM12RST_Msk',['../group___peripheral___registers___bits___definition.html#ga91170571df0e2ed7675a5b3091736507',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1rstr_5ftim12rst_5fpos_375',['RCC_APB1RSTR_TIM12RST_Pos',['../group___peripheral___registers___bits___definition.html#ga5874ca2fef163308e575153b945eaa53',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1rstr_5ftim13rst_376',['RCC_APB1RSTR_TIM13RST',['../group___peripheral___registers___bits___definition.html#gad59f66b35bdc0953428eb8c345397a7f',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1rstr_5ftim13rst_5fmsk_377',['RCC_APB1RSTR_TIM13RST_Msk',['../group___peripheral___registers___bits___definition.html#gac1b75cafab3889092a34ddfb502c5d6a',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1rstr_5ftim13rst_5fpos_378',['RCC_APB1RSTR_TIM13RST_Pos',['../group___peripheral___registers___bits___definition.html#gac4a9d1c4213a8dc4484ba58f49433806',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1rstr_5ftim14rst_379',['RCC_APB1RSTR_TIM14RST',['../group___peripheral___registers___bits___definition.html#ga773e6d5b419eb2d4b6291c862e04b002',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1rstr_5ftim14rst_5fmsk_380',['RCC_APB1RSTR_TIM14RST_Msk',['../group___peripheral___registers___bits___definition.html#gac1887a28578dd003746b62f95b48d06a',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1rstr_5ftim14rst_5fpos_381',['RCC_APB1RSTR_TIM14RST_Pos',['../group___peripheral___registers___bits___definition.html#gafced8b214c9803f4961f1f4f1324f28f',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1rstr_5ftim2rst_382',['RCC_APB1RSTR_TIM2RST',['../group___peripheral___registers___bits___definition.html#ga51ca4659706d0e00333d4abff049dc0d',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1rstr_5ftim2rst_5fmsk_383',['RCC_APB1RSTR_TIM2RST_Msk',['../group___peripheral___registers___bits___definition.html#gaf4b0f4bc33ed5d6d5806e5074349bedb',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1rstr_5ftim2rst_5fpos_384',['RCC_APB1RSTR_TIM2RST_Pos',['../group___peripheral___registers___bits___definition.html#gaef7278dbd9406107fbccefa358501f2c',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1rstr_5ftim3rst_385',['RCC_APB1RSTR_TIM3RST',['../group___peripheral___registers___bits___definition.html#ga8680c562fd372b494a160594525d7ce9',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1rstr_5ftim3rst_5fmsk_386',['RCC_APB1RSTR_TIM3RST_Msk',['../group___peripheral___registers___bits___definition.html#ga6f1a098d575d81ac443b3d6f837a09e1',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1rstr_5ftim3rst_5fpos_387',['RCC_APB1RSTR_TIM3RST_Pos',['../group___peripheral___registers___bits___definition.html#ga28531a8d644672fa950cce78175c3fc0',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1rstr_5ftim4rst_388',['RCC_APB1RSTR_TIM4RST',['../group___peripheral___registers___bits___definition.html#ga6a720364de988965b6d2f91ed6519570',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1rstr_5ftim4rst_5fmsk_389',['RCC_APB1RSTR_TIM4RST_Msk',['../group___peripheral___registers___bits___definition.html#gaa1adc26ee7ca9aeb6316ca372633c95e',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1rstr_5ftim4rst_5fpos_390',['RCC_APB1RSTR_TIM4RST_Pos',['../group___peripheral___registers___bits___definition.html#gacfd941245012a7ff32409d3858a0c369',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1rstr_5ftim5rst_391',['RCC_APB1RSTR_TIM5RST',['../group___peripheral___registers___bits___definition.html#ga1d1233dd5266ba55d9951e3b1a334552',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1rstr_5ftim5rst_5fmsk_392',['RCC_APB1RSTR_TIM5RST_Msk',['../group___peripheral___registers___bits___definition.html#ga9a5cfd79c37096bf00916e7bda1df220',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1rstr_5ftim5rst_5fpos_393',['RCC_APB1RSTR_TIM5RST_Pos',['../group___peripheral___registers___bits___definition.html#ga6ec5440469b072778617b76dd55faf23',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1rstr_5ftim6rst_394',['RCC_APB1RSTR_TIM6RST',['../group___peripheral___registers___bits___definition.html#ga8d64bd82cf47a209afebc7d663e28383',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1rstr_5ftim6rst_5fmsk_395',['RCC_APB1RSTR_TIM6RST_Msk',['../group___peripheral___registers___bits___definition.html#ga4f222bd16fca5ae0a0475a83f9a69d0f',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1rstr_5ftim6rst_5fpos_396',['RCC_APB1RSTR_TIM6RST_Pos',['../group___peripheral___registers___bits___definition.html#ga4f910529f471272ed5218c5067115cc8',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1rstr_5ftim7rst_397',['RCC_APB1RSTR_TIM7RST',['../group___peripheral___registers___bits___definition.html#ga40b1d355ee76ad9a044ad37f1629e760',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1rstr_5ftim7rst_5fmsk_398',['RCC_APB1RSTR_TIM7RST_Msk',['../group___peripheral___registers___bits___definition.html#gab9af08f1ff685c0027708d909086b748',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1rstr_5ftim7rst_5fpos_399',['RCC_APB1RSTR_TIM7RST_Pos',['../group___peripheral___registers___bits___definition.html#ga033243ec3d5cdaa7030b8b38d39e9989',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1rstr_5fuart4rst_400',['RCC_APB1RSTR_UART4RST',['../group___peripheral___registers___bits___definition.html#ga0802e99fa9eb9388393af3135ca2cb2b',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1rstr_5fuart4rst_5fmsk_401',['RCC_APB1RSTR_UART4RST_Msk',['../group___peripheral___registers___bits___definition.html#ga1c84c3ac04f075c4571c4518e9dc6f5d',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1rstr_5fuart4rst_5fpos_402',['RCC_APB1RSTR_UART4RST_Pos',['../group___peripheral___registers___bits___definition.html#gaff8420398d7b2ac7a1845643b0e2010b',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1rstr_5fuart5rst_403',['RCC_APB1RSTR_UART5RST',['../group___peripheral___registers___bits___definition.html#ga5e4d54359192c58725e5ece2b539f8ee',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1rstr_5fuart5rst_5fmsk_404',['RCC_APB1RSTR_UART5RST_Msk',['../group___peripheral___registers___bits___definition.html#ga5aaecac95d9e201eb6a3ee127881381b',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1rstr_5fuart5rst_5fpos_405',['RCC_APB1RSTR_UART5RST_Pos',['../group___peripheral___registers___bits___definition.html#gaddedfda3a5db9ea42104b43d23a64495',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1rstr_5fusart2rst_406',['RCC_APB1RSTR_USART2RST',['../group___peripheral___registers___bits___definition.html#ga195c39f08384ca1fa13b53a31d65d0a5',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1rstr_5fusart2rst_5fmsk_407',['RCC_APB1RSTR_USART2RST_Msk',['../group___peripheral___registers___bits___definition.html#ga0beb24842078f8a070ba7f96ca579f43',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1rstr_5fusart2rst_5fpos_408',['RCC_APB1RSTR_USART2RST_Pos',['../group___peripheral___registers___bits___definition.html#gaa2ca9ee6dbf794ec18d25721123a1119',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1rstr_5fusart3rst_409',['RCC_APB1RSTR_USART3RST',['../group___peripheral___registers___bits___definition.html#ga766478ebdcbb647eb3f32962543bd194',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1rstr_5fusart3rst_5fmsk_410',['RCC_APB1RSTR_USART3RST_Msk',['../group___peripheral___registers___bits___definition.html#gaafe9da843ef3eb19c556b8eeed4e56bf',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1rstr_5fusart3rst_5fpos_411',['RCC_APB1RSTR_USART3RST_Pos',['../group___peripheral___registers___bits___definition.html#ga8d88961277f1aaaaa0088ee671319522',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1rstr_5fwwdgrst_412',['RCC_APB1RSTR_WWDGRST',['../group___peripheral___registers___bits___definition.html#ga0d2591ac0655a8798f4c16cef97e6f94',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1rstr_5fwwdgrst_5fmsk_413',['RCC_APB1RSTR_WWDGRST_Msk',['../group___peripheral___registers___bits___definition.html#ga919c04abb655aa94b244dcebbf647748',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb1rstr_5fwwdgrst_5fpos_414',['RCC_APB1RSTR_WWDGRST_Pos',['../group___peripheral___registers___bits___definition.html#gaf9d96e880c3040ba8dbe155a6129ca69',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb2enr_5fadc1en_415',['RCC_APB2ENR_ADC1EN',['../group___peripheral___registers___bits___definition.html#ga57b9f50cb96a2e4ceba37728b4a32a42',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb2enr_5fadc1en_5fmsk_416',['RCC_APB2ENR_ADC1EN_Msk',['../group___peripheral___registers___bits___definition.html#ga11c50e2378b7a8d15c9a2eb89f561efe',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb2enr_5fadc1en_5fpos_417',['RCC_APB2ENR_ADC1EN_Pos',['../group___peripheral___registers___bits___definition.html#gabad54999d05c830541de19027fb92c97',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb2enr_5fadc2en_418',['RCC_APB2ENR_ADC2EN',['../group___peripheral___registers___bits___definition.html#ga11a9732e1cef24f107e815caecdbb445',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb2enr_5fadc2en_5fmsk_419',['RCC_APB2ENR_ADC2EN_Msk',['../group___peripheral___registers___bits___definition.html#ga55e486391860d774ac8613c6848b62de',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb2enr_5fadc2en_5fpos_420',['RCC_APB2ENR_ADC2EN_Pos',['../group___peripheral___registers___bits___definition.html#gaaa0ab86ac5dc8b87216901e91c950cc0',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb2enr_5fadc3en_421',['RCC_APB2ENR_ADC3EN',['../group___peripheral___registers___bits___definition.html#ga5df23f931ddad97274ce7e2050b90a5a',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb2enr_5fadc3en_5fmsk_422',['RCC_APB2ENR_ADC3EN_Msk',['../group___peripheral___registers___bits___definition.html#gaa3126f80244d91d2d13c1a40e5f64df0',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb2enr_5fadc3en_5fpos_423',['RCC_APB2ENR_ADC3EN_Pos',['../group___peripheral___registers___bits___definition.html#ga5a7fff458c028a5b1d43cd3a5e299121',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb2enr_5fsdioen_424',['RCC_APB2ENR_SDIOEN',['../group___peripheral___registers___bits___definition.html#gabf714bbe5b378910693dbfe824b70de8',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb2enr_5fsdioen_5fmsk_425',['RCC_APB2ENR_SDIOEN_Msk',['../group___peripheral___registers___bits___definition.html#ga06f570456b6725105e600c0700cdc0bd',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb2enr_5fsdioen_5fpos_426',['RCC_APB2ENR_SDIOEN_Pos',['../group___peripheral___registers___bits___definition.html#ga4fd687b860d719def07032d6cfd1cc3a',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb2enr_5fspi1en_427',['RCC_APB2ENR_SPI1EN',['../group___peripheral___registers___bits___definition.html#gae08a3510371b9234eb96369c91d3552f',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb2enr_5fspi1en_5fmsk_428',['RCC_APB2ENR_SPI1EN_Msk',['../group___peripheral___registers___bits___definition.html#gaefba87e52830d0d82cd94eb11089aa1b',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb2enr_5fspi1en_5fpos_429',['RCC_APB2ENR_SPI1EN_Pos',['../group___peripheral___registers___bits___definition.html#ga77b08db44a4ccc823a4ecaf89c3b4309',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb2enr_5fsyscfgen_430',['RCC_APB2ENR_SYSCFGEN',['../group___peripheral___registers___bits___definition.html#ga7a9d56a8aa1fa0f519ecbdf0d19dd4da',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb2enr_5fsyscfgen_5fmsk_431',['RCC_APB2ENR_SYSCFGEN_Msk',['../group___peripheral___registers___bits___definition.html#ga781c030e54df45c8f190c9f03d20f4a5',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb2enr_5fsyscfgen_5fpos_432',['RCC_APB2ENR_SYSCFGEN_Pos',['../group___peripheral___registers___bits___definition.html#ga2e61727e044998a6ebee3dcf48614554',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb2enr_5ftim10en_433',['RCC_APB2ENR_TIM10EN',['../group___peripheral___registers___bits___definition.html#gaa98e28e157787e24b93af95273ab3055',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb2enr_5ftim10en_5fmsk_434',['RCC_APB2ENR_TIM10EN_Msk',['../group___peripheral___registers___bits___definition.html#ga539dc20498c8b8abdf208bd2b98a46c6',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb2enr_5ftim10en_5fpos_435',['RCC_APB2ENR_TIM10EN_Pos',['../group___peripheral___registers___bits___definition.html#ga595f4318939fac8cef4cfb6a886a0811',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb2enr_5ftim11en_436',['RCC_APB2ENR_TIM11EN',['../group___peripheral___registers___bits___definition.html#gab1d2aeebc8ccf4e2ee18f4d924a35188',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb2enr_5ftim11en_5fmsk_437',['RCC_APB2ENR_TIM11EN_Msk',['../group___peripheral___registers___bits___definition.html#gaa5273bcf1abc8db0bf1617c747bab5ec',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb2enr_5ftim11en_5fpos_438',['RCC_APB2ENR_TIM11EN_Pos',['../group___peripheral___registers___bits___definition.html#ga4175c4afc573a7bdd6fa19faaaf9f735',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb2enr_5ftim1en_439',['RCC_APB2ENR_TIM1EN',['../group___peripheral___registers___bits___definition.html#ga25852ad4ebc09edc724814de967816bc',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb2enr_5ftim1en_5fmsk_440',['RCC_APB2ENR_TIM1EN_Msk',['../group___peripheral___registers___bits___definition.html#ga1216bf89d48094b55a4abcc859b037fa',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb2enr_5ftim1en_5fpos_441',['RCC_APB2ENR_TIM1EN_Pos',['../group___peripheral___registers___bits___definition.html#ga5b330cc86756aa87e3f7466e82eaf64b',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb2enr_5ftim8en_442',['RCC_APB2ENR_TIM8EN',['../group___peripheral___registers___bits___definition.html#ga3669393b3538bc4543184d4bccd0b292',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb2enr_5ftim8en_5fmsk_443',['RCC_APB2ENR_TIM8EN_Msk',['../group___peripheral___registers___bits___definition.html#gace08df04fccb33baccbda0fa4697dc04',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb2enr_5ftim8en_5fpos_444',['RCC_APB2ENR_TIM8EN_Pos',['../group___peripheral___registers___bits___definition.html#gadddecaa60d969169a1ba2944371b2414',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb2enr_5ftim9en_445',['RCC_APB2ENR_TIM9EN',['../group___peripheral___registers___bits___definition.html#ga987ebd8255dc8f9c09127e1d608d1065',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb2enr_5ftim9en_5fmsk_446',['RCC_APB2ENR_TIM9EN_Msk',['../group___peripheral___registers___bits___definition.html#gad7973b960b45268bd0160c1f5f21acf2',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb2enr_5ftim9en_5fpos_447',['RCC_APB2ENR_TIM9EN_Pos',['../group___peripheral___registers___bits___definition.html#gac1023b40804156535a7fd0b0fd17da26',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb2enr_5fusart1en_448',['RCC_APB2ENR_USART1EN',['../group___peripheral___registers___bits___definition.html#ga4666bb90842e8134b32e6a34a0f165f3',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb2enr_5fusart1en_5fmsk_449',['RCC_APB2ENR_USART1EN_Msk',['../group___peripheral___registers___bits___definition.html#ga6a185f9bf1e72599fc7d2e02716ee40b',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb2enr_5fusart1en_5fpos_450',['RCC_APB2ENR_USART1EN_Pos',['../group___peripheral___registers___bits___definition.html#ga603eb3c42e7ee50f31fb6fade0b4e43b',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb2enr_5fusart6en_451',['RCC_APB2ENR_USART6EN',['../group___peripheral___registers___bits___definition.html#ga0569d91f3b18ae130b7a09e0100c4459',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb2enr_5fusart6en_5fmsk_452',['RCC_APB2ENR_USART6EN_Msk',['../group___peripheral___registers___bits___definition.html#ga3d196a71620aa24b125657dfdc9c85bf',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb2enr_5fusart6en_5fpos_453',['RCC_APB2ENR_USART6EN_Pos',['../group___peripheral___registers___bits___definition.html#ga7e600f524eab6bd8a909babd0dde5466',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb2lpenr_5fadc1lpen_454',['RCC_APB2LPENR_ADC1LPEN',['../group___peripheral___registers___bits___definition.html#ga126a8791f77cecc599e32d2c882a4dab',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb2lpenr_5fadc1lpen_5fmsk_455',['RCC_APB2LPENR_ADC1LPEN_Msk',['../group___peripheral___registers___bits___definition.html#ga116ac44e1a83643de5be822458c9f42b',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb2lpenr_5fadc1lpen_5fpos_456',['RCC_APB2LPENR_ADC1LPEN_Pos',['../group___peripheral___registers___bits___definition.html#gae30aac03ac0c319cc528d35e7f459997',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb2lpenr_5fadc2lpen_457',['RCC_APB2LPENR_ADC2LPEN',['../group___peripheral___registers___bits___definition.html#gab7d578d9d9a12e3f0b4246e196040c13',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb2lpenr_5fadc2lpen_5fmsk_458',['RCC_APB2LPENR_ADC2LPEN_Msk',['../group___peripheral___registers___bits___definition.html#gab6de7661abce7e5d9b3d9d47938095b0',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb2lpenr_5fadc2lpen_5fpos_459',['RCC_APB2LPENR_ADC2LPEN_Pos',['../group___peripheral___registers___bits___definition.html#ga20aaf3952e7679b2535befd5db14781b',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb2lpenr_5fadc3lpen_460',['RCC_APB2LPENR_ADC3LPEN',['../group___peripheral___registers___bits___definition.html#ga12c8300ba9b1ce9b14fc8e0f3ec4c127',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb2lpenr_5fadc3lpen_5fmsk_461',['RCC_APB2LPENR_ADC3LPEN_Msk',['../group___peripheral___registers___bits___definition.html#ga94f89563dfe984830b279fe3d358ca27',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb2lpenr_5fadc3lpen_5fpos_462',['RCC_APB2LPENR_ADC3LPEN_Pos',['../group___peripheral___registers___bits___definition.html#ga287cf6c970a88095bdabcb50dbebd196',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb2lpenr_5fsdiolpen_463',['RCC_APB2LPENR_SDIOLPEN',['../group___peripheral___registers___bits___definition.html#ga7a740fdf8313fbdd00dd97eb73afc4dc',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb2lpenr_5fsdiolpen_5fmsk_464',['RCC_APB2LPENR_SDIOLPEN_Msk',['../group___peripheral___registers___bits___definition.html#ga407fda261b548cac4ba4f70d13250a0e',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb2lpenr_5fsdiolpen_5fpos_465',['RCC_APB2LPENR_SDIOLPEN_Pos',['../group___peripheral___registers___bits___definition.html#ga7e852d24cc37b0873db77eec05211616',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb2lpenr_5fspi1lpen_466',['RCC_APB2LPENR_SPI1LPEN',['../group___peripheral___registers___bits___definition.html#ga2c6729058e54f4b8f8ae01d5b3586aaa',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb2lpenr_5fspi1lpen_5fmsk_467',['RCC_APB2LPENR_SPI1LPEN_Msk',['../group___peripheral___registers___bits___definition.html#gae3b71e51ae5bffdaf53ceb522f147892',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb2lpenr_5fspi1lpen_5fpos_468',['RCC_APB2LPENR_SPI1LPEN_Pos',['../group___peripheral___registers___bits___definition.html#ga2ddb35d5536b1e28be09ba48b0726721',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb2lpenr_5fsyscfglpen_469',['RCC_APB2LPENR_SYSCFGLPEN',['../group___peripheral___registers___bits___definition.html#gaaa82cfc33f0cf71220398bbe1c4b412e',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb2lpenr_5fsyscfglpen_5fmsk_470',['RCC_APB2LPENR_SYSCFGLPEN_Msk',['../group___peripheral___registers___bits___definition.html#gab4d070a25b830752decd55b74a452cda',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb2lpenr_5fsyscfglpen_5fpos_471',['RCC_APB2LPENR_SYSCFGLPEN_Pos',['../group___peripheral___registers___bits___definition.html#gaa4bb28885c56bf8b04da2633393c5b47',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb2lpenr_5ftim10lpen_472',['RCC_APB2LPENR_TIM10LPEN',['../group___peripheral___registers___bits___definition.html#gae7999e2ebeb1300d0cf6a59ad92c41b6',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb2lpenr_5ftim10lpen_5fmsk_473',['RCC_APB2LPENR_TIM10LPEN_Msk',['../group___peripheral___registers___bits___definition.html#gac8e04154247e0db474da2cc8eccac1f2',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb2lpenr_5ftim10lpen_5fpos_474',['RCC_APB2LPENR_TIM10LPEN_Pos',['../group___peripheral___registers___bits___definition.html#gaf74626f4a9c7d80ee37c80c18b76c9af',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb2lpenr_5ftim11lpen_475',['RCC_APB2LPENR_TIM11LPEN',['../group___peripheral___registers___bits___definition.html#gad43fcaa4f4d6fb2b590a6ffee31f8c94',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb2lpenr_5ftim11lpen_5fmsk_476',['RCC_APB2LPENR_TIM11LPEN_Msk',['../group___peripheral___registers___bits___definition.html#ga4cabf028115d0694b1bba23610d23da8',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb2lpenr_5ftim11lpen_5fpos_477',['RCC_APB2LPENR_TIM11LPEN_Pos',['../group___peripheral___registers___bits___definition.html#gabcc3b8ef34620fa6f4e82cbbf527fc27',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb2lpenr_5ftim1lpen_478',['RCC_APB2LPENR_TIM1LPEN',['../group___peripheral___registers___bits___definition.html#ga82580245686c32761e8354fb174ba5dd',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb2lpenr_5ftim1lpen_5fmsk_479',['RCC_APB2LPENR_TIM1LPEN_Msk',['../group___peripheral___registers___bits___definition.html#ga858c7e6effbead8e2953c8af89451f05',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb2lpenr_5ftim1lpen_5fpos_480',['RCC_APB2LPENR_TIM1LPEN_Pos',['../group___peripheral___registers___bits___definition.html#ga5ac0ea3808afc94624b680e8b3749a66',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb2lpenr_5ftim8lpen_481',['RCC_APB2LPENR_TIM8LPEN',['../group___peripheral___registers___bits___definition.html#ga8a1a808f511ff563f05f32ad3ae6d7c1',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb2lpenr_5ftim8lpen_5fmsk_482',['RCC_APB2LPENR_TIM8LPEN_Msk',['../group___peripheral___registers___bits___definition.html#ga193680b82d9cdcefad8ff2ac9e7ed2da',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb2lpenr_5ftim8lpen_5fpos_483',['RCC_APB2LPENR_TIM8LPEN_Pos',['../group___peripheral___registers___bits___definition.html#ga04afe23491647fcdf2a0cfeadce36cf0',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb2lpenr_5ftim9lpen_484',['RCC_APB2LPENR_TIM9LPEN',['../group___peripheral___registers___bits___definition.html#ga91b882f3dc2b939a53ed3f4caa537de1',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb2lpenr_5ftim9lpen_5fmsk_485',['RCC_APB2LPENR_TIM9LPEN_Msk',['../group___peripheral___registers___bits___definition.html#gae3d30a083acde66ba393ef2e7e2d3424',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb2lpenr_5ftim9lpen_5fpos_486',['RCC_APB2LPENR_TIM9LPEN_Pos',['../group___peripheral___registers___bits___definition.html#gae087736e445764bceba754d1d424f8d1',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb2lpenr_5fusart1lpen_487',['RCC_APB2LPENR_USART1LPEN',['../group___peripheral___registers___bits___definition.html#gab8b429bc8d52abd1ba3818a82542bb98',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb2lpenr_5fusart1lpen_5fmsk_488',['RCC_APB2LPENR_USART1LPEN_Msk',['../group___peripheral___registers___bits___definition.html#ga294b9579075d948ff613d153a7a3c3ca',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb2lpenr_5fusart1lpen_5fpos_489',['RCC_APB2LPENR_USART1LPEN_Pos',['../group___peripheral___registers___bits___definition.html#ga4bcb3fc3f4b2e68f667724cdd2e04ce8',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb2lpenr_5fusart6lpen_490',['RCC_APB2LPENR_USART6LPEN',['../group___peripheral___registers___bits___definition.html#ga2b82eb1986da9ed32e6701d01fffe55d',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb2lpenr_5fusart6lpen_5fmsk_491',['RCC_APB2LPENR_USART6LPEN_Msk',['../group___peripheral___registers___bits___definition.html#ga4262d6ef04c2c0ebe14c133021f0ae03',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb2lpenr_5fusart6lpen_5fpos_492',['RCC_APB2LPENR_USART6LPEN_Pos',['../group___peripheral___registers___bits___definition.html#gaa70231e7e2fbbac64535106f4aa48e3f',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb2rstr_5fadcrst_493',['RCC_APB2RSTR_ADCRST',['../group___peripheral___registers___bits___definition.html#ga1374d6eae8e7d02d1ad457b65f374a67',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb2rstr_5fadcrst_5fmsk_494',['RCC_APB2RSTR_ADCRST_Msk',['../group___peripheral___registers___bits___definition.html#ga1a4836f2cd9be43193d6eb4d19d5dde6',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb2rstr_5fadcrst_5fpos_495',['RCC_APB2RSTR_ADCRST_Pos',['../group___peripheral___registers___bits___definition.html#gafb93c28e2b44e753d961ee83fb829ad0',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb2rstr_5fsdiorst_496',['RCC_APB2RSTR_SDIORST',['../group___peripheral___registers___bits___definition.html#ga754451a96f4c4faf63a29ca1a132c64d',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb2rstr_5fsdiorst_5fmsk_497',['RCC_APB2RSTR_SDIORST_Msk',['../group___peripheral___registers___bits___definition.html#gae67f4f982e0636f1d86be7d4223cdaf1',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb2rstr_5fsdiorst_5fpos_498',['RCC_APB2RSTR_SDIORST_Pos',['../group___peripheral___registers___bits___definition.html#ga964b8835939769ac1b9bd4984854757d',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb2rstr_5fspi1_499',['RCC_APB2RSTR_SPI1',['../group___peripheral___registers___bits___definition.html#ga38f676c6c842fc9471d51a50584fbe91',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb2rstr_5fspi1rst_500',['RCC_APB2RSTR_SPI1RST',['../group___peripheral___registers___bits___definition.html#ga345f05d3508a9fd5128208761feb29fb',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb2rstr_5fspi1rst_5fmsk_501',['RCC_APB2RSTR_SPI1RST_Msk',['../group___peripheral___registers___bits___definition.html#ga4fb7fb16a3052da4a7d11cbdbe838689',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb2rstr_5fspi1rst_5fpos_502',['RCC_APB2RSTR_SPI1RST_Pos',['../group___peripheral___registers___bits___definition.html#ga5f284f64839f82231c3e375e01105946',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb2rstr_5fsyscfgrst_503',['RCC_APB2RSTR_SYSCFGRST',['../group___peripheral___registers___bits___definition.html#ga813d42b8d48ae6379c053a44870af49d',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb2rstr_5fsyscfgrst_5fmsk_504',['RCC_APB2RSTR_SYSCFGRST_Msk',['../group___peripheral___registers___bits___definition.html#ga89f656408c45d2f67a99cc1c093d3e45',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb2rstr_5fsyscfgrst_5fpos_505',['RCC_APB2RSTR_SYSCFGRST_Pos',['../group___peripheral___registers___bits___definition.html#ga613a32917030cbb38e7897bdec0cad47',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb2rstr_5ftim10rst_506',['RCC_APB2RSTR_TIM10RST',['../group___peripheral___registers___bits___definition.html#gac76155acdc99c8c6502ba3beba818f42',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb2rstr_5ftim10rst_5fmsk_507',['RCC_APB2RSTR_TIM10RST_Msk',['../group___peripheral___registers___bits___definition.html#ga077ef7ed92b0241e49f2ecad1a8bd241',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb2rstr_5ftim10rst_5fpos_508',['RCC_APB2RSTR_TIM10RST_Pos',['../group___peripheral___registers___bits___definition.html#ga01379fcaf1119cd7a25cdf930fe10458',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb2rstr_5ftim11rst_509',['RCC_APB2RSTR_TIM11RST',['../group___peripheral___registers___bits___definition.html#ga9651c8201d42ba03bb1bf89d9d39e60c',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb2rstr_5ftim11rst_5fmsk_510',['RCC_APB2RSTR_TIM11RST_Msk',['../group___peripheral___registers___bits___definition.html#ga6ffe8d460fb9abc55ec65d00d39564b3',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb2rstr_5ftim11rst_5fpos_511',['RCC_APB2RSTR_TIM11RST_Pos',['../group___peripheral___registers___bits___definition.html#ga8d1b402b6082b891cf838cc69119b2a1',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb2rstr_5ftim1rst_512',['RCC_APB2RSTR_TIM1RST',['../group___peripheral___registers___bits___definition.html#ga5bd060cbefaef05487963bbd6c48d7c6',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb2rstr_5ftim1rst_5fmsk_513',['RCC_APB2RSTR_TIM1RST_Msk',['../group___peripheral___registers___bits___definition.html#ga6fc9f88241816d51a87a8b4a537c5a2e',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb2rstr_5ftim1rst_5fpos_514',['RCC_APB2RSTR_TIM1RST_Pos',['../group___peripheral___registers___bits___definition.html#gae3439757d01e0c351ad8bc0193e3d90e',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb2rstr_5ftim8rst_515',['RCC_APB2RSTR_TIM8RST',['../group___peripheral___registers___bits___definition.html#gaa129b34dbaf6c5301f751410ab4668ca',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb2rstr_5ftim8rst_5fmsk_516',['RCC_APB2RSTR_TIM8RST_Msk',['../group___peripheral___registers___bits___definition.html#gab14242f5f656c5860137bd75f2a0515e',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb2rstr_5ftim8rst_5fpos_517',['RCC_APB2RSTR_TIM8RST_Pos',['../group___peripheral___registers___bits___definition.html#gaaab98fc817a93527229f575e6b642969',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb2rstr_5ftim9rst_518',['RCC_APB2RSTR_TIM9RST',['../group___peripheral___registers___bits___definition.html#gab3aa588d4814a289d939e111492724af',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb2rstr_5ftim9rst_5fmsk_519',['RCC_APB2RSTR_TIM9RST_Msk',['../group___peripheral___registers___bits___definition.html#gad71d516052c6afded3292ada76c392a2',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb2rstr_5ftim9rst_5fpos_520',['RCC_APB2RSTR_TIM9RST_Pos',['../group___peripheral___registers___bits___definition.html#gaed9b13161f4dbf0f960abe15c7f9f045',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb2rstr_5fusart1rst_521',['RCC_APB2RSTR_USART1RST',['../group___peripheral___registers___bits___definition.html#gae7ae8e338b3b42ad037e9e5b6eeb2c41',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb2rstr_5fusart1rst_5fmsk_522',['RCC_APB2RSTR_USART1RST_Msk',['../group___peripheral___registers___bits___definition.html#ga49f18e05ca4a63d5b8fe937eb8613005',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb2rstr_5fusart1rst_5fpos_523',['RCC_APB2RSTR_USART1RST_Pos',['../group___peripheral___registers___bits___definition.html#gac07b0f4aae1366a80486993aa71c6237',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb2rstr_5fusart6rst_524',['RCC_APB2RSTR_USART6RST',['../group___peripheral___registers___bits___definition.html#gada1df682293e15ed44b081d626220178',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb2rstr_5fusart6rst_5fmsk_525',['RCC_APB2RSTR_USART6RST_Msk',['../group___peripheral___registers___bits___definition.html#ga63e37e8ac731047e3df29ca5c7e553cc',1,'stm32f407xx_matlab.h']]], - ['rcc_5fapb2rstr_5fusart6rst_5fpos_526',['RCC_APB2RSTR_USART6RST_Pos',['../group___peripheral___registers___bits___definition.html#ga1aa2e760b59afddec0efc53fd80e60bf',1,'stm32f407xx_matlab.h']]], - ['rcc_5fbase_527',['RCC_BASE',['../group___peripheral__memory__map.html#ga0e681b03f364532055d88f63fec0d99d',1,'stm32f407xx_matlab.h']]], - ['rcc_5fbdcr_5fbdrst_528',['RCC_BDCR_BDRST',['../group___peripheral___registers___bits___definition.html#ga2b85b3ab656dfa2809b15e6e530c17a2',1,'stm32f407xx_matlab.h']]], - ['rcc_5fbdcr_5fbdrst_5fmsk_529',['RCC_BDCR_BDRST_Msk',['../group___peripheral___registers___bits___definition.html#ga0a3b3c81018daa0d5b80480a86bc7a17',1,'stm32f407xx_matlab.h']]], - ['rcc_5fbdcr_5fbdrst_5fpos_530',['RCC_BDCR_BDRST_Pos',['../group___peripheral___registers___bits___definition.html#gac787de49ce5fa9a2e0123ddf33f4e26e',1,'stm32f407xx_matlab.h']]], - ['rcc_5fbdcr_5flsebyp_531',['RCC_BDCR_LSEBYP',['../group___peripheral___registers___bits___definition.html#ga542dffd7f8dc4da5401b54d822a22af0',1,'stm32f407xx_matlab.h']]], - ['rcc_5fbdcr_5flsebyp_5fmsk_532',['RCC_BDCR_LSEBYP_Msk',['../group___peripheral___registers___bits___definition.html#ga7e5eba5220ddabddf14901a8d44abaf2',1,'stm32f407xx_matlab.h']]], - ['rcc_5fbdcr_5flsebyp_5fpos_533',['RCC_BDCR_LSEBYP_Pos',['../group___peripheral___registers___bits___definition.html#ga8900b556c097b54266370f197517c2b4',1,'stm32f407xx_matlab.h']]], - ['rcc_5fbdcr_5flseon_534',['RCC_BDCR_LSEON',['../group___peripheral___registers___bits___definition.html#ga00145f8814cb9a5b180d76499d97aead',1,'stm32f407xx_matlab.h']]], - ['rcc_5fbdcr_5flseon_5fmsk_535',['RCC_BDCR_LSEON_Msk',['../group___peripheral___registers___bits___definition.html#ga85556465021c4272f4788d52251b29f4',1,'stm32f407xx_matlab.h']]], - ['rcc_5fbdcr_5flseon_5fpos_536',['RCC_BDCR_LSEON_Pos',['../group___peripheral___registers___bits___definition.html#ga016de845d59f61611054d27511a3fa68',1,'stm32f407xx_matlab.h']]], - ['rcc_5fbdcr_5flserdy_537',['RCC_BDCR_LSERDY',['../group___peripheral___registers___bits___definition.html#gaafca81172ed857ce6b94582fcaada87c',1,'stm32f407xx_matlab.h']]], - ['rcc_5fbdcr_5flserdy_5fmsk_538',['RCC_BDCR_LSERDY_Msk',['../group___peripheral___registers___bits___definition.html#ga35093bcccacfeda073a2fb815687549c',1,'stm32f407xx_matlab.h']]], - ['rcc_5fbdcr_5flserdy_5fpos_539',['RCC_BDCR_LSERDY_Pos',['../group___peripheral___registers___bits___definition.html#ga1d373419116fa0446eee779da5292b02',1,'stm32f407xx_matlab.h']]], - ['rcc_5fbdcr_5frtcen_540',['RCC_BDCR_RTCEN',['../group___peripheral___registers___bits___definition.html#ga79ea6f2df75f09b17df9582037ed6a53',1,'stm32f407xx_matlab.h']]], - ['rcc_5fbdcr_5frtcen_5fmsk_541',['RCC_BDCR_RTCEN_Msk',['../group___peripheral___registers___bits___definition.html#gad4b2e482dc6f5c75861f08de8057d1e2',1,'stm32f407xx_matlab.h']]], - ['rcc_5fbdcr_5frtcen_5fpos_542',['RCC_BDCR_RTCEN_Pos',['../group___peripheral___registers___bits___definition.html#gad32e3fd78eebb6ac9bb446a9fdda3d0d',1,'stm32f407xx_matlab.h']]], - ['rcc_5fbdcr_5frtcsel_543',['RCC_BDCR_RTCSEL',['../group___peripheral___registers___bits___definition.html#gabe30dbd38f6456990ee641648bc05d40',1,'stm32f407xx_matlab.h']]], - ['rcc_5fbdcr_5frtcsel_5f0_544',['RCC_BDCR_RTCSEL_0',['../group___peripheral___registers___bits___definition.html#ga6701d58e40e4c16e9be49436fcbe23d0',1,'stm32f407xx_matlab.h']]], - ['rcc_5fbdcr_5frtcsel_5f1_545',['RCC_BDCR_RTCSEL_1',['../group___peripheral___registers___bits___definition.html#gaac4e378027f3293ec520ed6d18c633f4',1,'stm32f407xx_matlab.h']]], - ['rcc_5fbdcr_5frtcsel_5fmsk_546',['RCC_BDCR_RTCSEL_Msk',['../group___peripheral___registers___bits___definition.html#ga57377b1880634589201dfe8887287e0e',1,'stm32f407xx_matlab.h']]], - ['rcc_5fbdcr_5frtcsel_5fpos_547',['RCC_BDCR_RTCSEL_Pos',['../group___peripheral___registers___bits___definition.html#ga1ba11e8b21a7165e4b8e9a2cbf5a323d',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcfgr_5fhpre_548',['RCC_CFGR_HPRE',['../group___peripheral___registers___bits___definition.html#gafe10e66938644ee8054a2426ff23efea',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcfgr_5fhpre_5f0_549',['RCC_CFGR_HPRE_0',['../group___peripheral___registers___bits___definition.html#ga88ece6ca270b3ecf6f63bf20893bc172',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcfgr_5fhpre_5f1_550',['RCC_CFGR_HPRE_1',['../group___peripheral___registers___bits___definition.html#gacbdd3a02814178ba02b8ebbaccd91599',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcfgr_5fhpre_5f2_551',['RCC_CFGR_HPRE_2',['../group___peripheral___registers___bits___definition.html#gadac734bddb507eed4a62a0af4cef74a3',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcfgr_5fhpre_5f3_552',['RCC_CFGR_HPRE_3',['../group___peripheral___registers___bits___definition.html#ga5a1180512cc5f3dde7895040a9037286',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcfgr_5fhpre_5fdiv1_553',['RCC_CFGR_HPRE_DIV1',['../group___peripheral___registers___bits___definition.html#ga2b7d7f29b09a49c31404fc0d44645c84',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcfgr_5fhpre_5fdiv128_554',['RCC_CFGR_HPRE_DIV128',['../group___peripheral___registers___bits___definition.html#ga280da821f0da1bec1f4c0e132ddf8eab',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcfgr_5fhpre_5fdiv16_555',['RCC_CFGR_HPRE_DIV16',['../group___peripheral___registers___bits___definition.html#ga3806da4f1afc9e5be0fca001c8c57815',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcfgr_5fhpre_5fdiv2_556',['RCC_CFGR_HPRE_DIV2',['../group___peripheral___registers___bits___definition.html#gaa9eeb5e38e53e79b08a4ac438497ebea',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcfgr_5fhpre_5fdiv256_557',['RCC_CFGR_HPRE_DIV256',['../group___peripheral___registers___bits___definition.html#ga089930cedd5b2cb201e717438f29d25b',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcfgr_5fhpre_5fdiv4_558',['RCC_CFGR_HPRE_DIV4',['../group___peripheral___registers___bits___definition.html#gaffe860867ae4b1b6d28473ded1546d91',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcfgr_5fhpre_5fdiv512_559',['RCC_CFGR_HPRE_DIV512',['../group___peripheral___registers___bits___definition.html#gae5088dcbaefc55d4b6693e9b1e595ed0',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcfgr_5fhpre_5fdiv64_560',['RCC_CFGR_HPRE_DIV64',['../group___peripheral___registers___bits___definition.html#ga1caeba8dc2b4c0bb11be600e983e3370',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcfgr_5fhpre_5fdiv8_561',['RCC_CFGR_HPRE_DIV8',['../group___peripheral___registers___bits___definition.html#gaca71d6b42bdb83b5ff5320578869a058',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcfgr_5fhpre_5fmsk_562',['RCC_CFGR_HPRE_Msk',['../group___peripheral___registers___bits___definition.html#ga65804e0ce7ec3204e9a56bb848428460',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcfgr_5fhpre_5fpos_563',['RCC_CFGR_HPRE_Pos',['../group___peripheral___registers___bits___definition.html#ga2447eb7ab6388f0446e7550df8f50d90',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcfgr_5fi2ssrc_564',['RCC_CFGR_I2SSRC',['../group___peripheral___registers___bits___definition.html#ga5d43413fd6b17bd988ccae9e34296412',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcfgr_5fi2ssrc_5fmsk_565',['RCC_CFGR_I2SSRC_Msk',['../group___peripheral___registers___bits___definition.html#gadaa5cae9d2b4ddc11fbe5a1858ead900',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcfgr_5fi2ssrc_5fpos_566',['RCC_CFGR_I2SSRC_Pos',['../group___peripheral___registers___bits___definition.html#ga3345cb612da061eb09e7f41b42409e42',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcfgr_5fmco1_567',['RCC_CFGR_MCO1',['../group___peripheral___registers___bits___definition.html#ga26eb4a66eeff0ba17e9d2a06cf937ca4',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcfgr_5fmco1_5f0_568',['RCC_CFGR_MCO1_0',['../group___peripheral___registers___bits___definition.html#gafe73b3ad484eeecfa1556021677ecf4a',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcfgr_5fmco1_5f1_569',['RCC_CFGR_MCO1_1',['../group___peripheral___registers___bits___definition.html#ga1c7e8d1da534f052ce835f06227a9b7a',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcfgr_5fmco1_5fmsk_570',['RCC_CFGR_MCO1_Msk',['../group___peripheral___registers___bits___definition.html#ga83b21a49230470856ce978e05fb9c47b',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcfgr_5fmco1_5fpos_571',['RCC_CFGR_MCO1_Pos',['../group___peripheral___registers___bits___definition.html#gaf44071a1145774e7c5a5ea41cc709c42',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcfgr_5fmco1pre_572',['RCC_CFGR_MCO1PRE',['../group___peripheral___registers___bits___definition.html#ga23171ca70972a106109a6e0804385ec5',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcfgr_5fmco1pre_5f0_573',['RCC_CFGR_MCO1PRE_0',['../group___peripheral___registers___bits___definition.html#gac8007a9d6ee3fd88912aaf290746ae0e',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcfgr_5fmco1pre_5f1_574',['RCC_CFGR_MCO1PRE_1',['../group___peripheral___registers___bits___definition.html#gaaf7c1280f61d56b4897f9c876987e092',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcfgr_5fmco1pre_5f2_575',['RCC_CFGR_MCO1PRE_2',['../group___peripheral___registers___bits___definition.html#ga11e1d10d1b55e0d88d24212ea2c8ba6e',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcfgr_5fmco1pre_5fmsk_576',['RCC_CFGR_MCO1PRE_Msk',['../group___peripheral___registers___bits___definition.html#gada571dab4e704e380153b6e901b60ba8',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcfgr_5fmco1pre_5fpos_577',['RCC_CFGR_MCO1PRE_Pos',['../group___peripheral___registers___bits___definition.html#ga12578e7f44e1e03ec5c4fd5987303b1e',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcfgr_5fmco2_578',['RCC_CFGR_MCO2',['../group___peripheral___registers___bits___definition.html#ga022248a1167714f4d847b89243dc5244',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcfgr_5fmco2_5f0_579',['RCC_CFGR_MCO2_0',['../group___peripheral___registers___bits___definition.html#ga203156a3f57e2c4498999c7901e0defd',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcfgr_5fmco2_5f1_580',['RCC_CFGR_MCO2_1',['../group___peripheral___registers___bits___definition.html#ga2fdba9682ff474255248f84e6851932a',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcfgr_5fmco2_5fmsk_581',['RCC_CFGR_MCO2_Msk',['../group___peripheral___registers___bits___definition.html#ga193bf927828d92f9249975a792c738d5',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcfgr_5fmco2_5fpos_582',['RCC_CFGR_MCO2_Pos',['../group___peripheral___registers___bits___definition.html#ga06b28dad6a8c9bd84cf1f659ddb976a8',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcfgr_5fmco2pre_583',['RCC_CFGR_MCO2PRE',['../group___peripheral___registers___bits___definition.html#gae387252f29b6f98cc1fffc4fa0719b6e',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcfgr_5fmco2pre_5f0_584',['RCC_CFGR_MCO2PRE_0',['../group___peripheral___registers___bits___definition.html#ga83dfcd5a1ce89869c82723f7eb9223ed',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcfgr_5fmco2pre_5f1_585',['RCC_CFGR_MCO2PRE_1',['../group___peripheral___registers___bits___definition.html#ga0e8d7cb746efc7511fa97ddfef2df793',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcfgr_5fmco2pre_5f2_586',['RCC_CFGR_MCO2PRE_2',['../group___peripheral___registers___bits___definition.html#gac8773dfae91e6576d490fbee4aa2a639',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcfgr_5fmco2pre_5fmsk_587',['RCC_CFGR_MCO2PRE_Msk',['../group___peripheral___registers___bits___definition.html#ga56af08fd6ae55e0047d84c2e5cb44877',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcfgr_5fmco2pre_5fpos_588',['RCC_CFGR_MCO2PRE_Pos',['../group___peripheral___registers___bits___definition.html#ga1d6ccde3c82ee001935b7cf3d5273923',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcfgr_5fppre1_589',['RCC_CFGR_PPRE1',['../group___peripheral___registers___bits___definition.html#ga50b2423a5fea74a47b9eb8ab51869412',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcfgr_5fppre1_5f0_590',['RCC_CFGR_PPRE1_0',['../group___peripheral___registers___bits___definition.html#ga2d37c20686faa340a77021117f5908b7',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcfgr_5fppre1_5f1_591',['RCC_CFGR_PPRE1_1',['../group___peripheral___registers___bits___definition.html#gad41049f8a28fdced6bb4d9267845ffa2',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcfgr_5fppre1_5f2_592',['RCC_CFGR_PPRE1_2',['../group___peripheral___registers___bits___definition.html#ga5fcb524f6ca203ddff1862c124d4f89f',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcfgr_5fppre1_5fdiv1_593',['RCC_CFGR_PPRE1_DIV1',['../group___peripheral___registers___bits___definition.html#gac8f6562bb2ecf65055a2f42cbb48ef11',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcfgr_5fppre1_5fdiv16_594',['RCC_CFGR_PPRE1_DIV16',['../group___peripheral___registers___bits___definition.html#ga5c38ba326bde7c7a18c4f7f2aacf823f',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcfgr_5fppre1_5fdiv2_595',['RCC_CFGR_PPRE1_DIV2',['../group___peripheral___registers___bits___definition.html#gaf832ad6844c907d9bb37c1536defcb0d',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcfgr_5fppre1_5fdiv4_596',['RCC_CFGR_PPRE1_DIV4',['../group___peripheral___registers___bits___definition.html#ga0e340725f46e9462d9b02a079b9fa8ae',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcfgr_5fppre1_5fdiv8_597',['RCC_CFGR_PPRE1_DIV8',['../group___peripheral___registers___bits___definition.html#ga9ddd6d657837e1971bb86e3bf1c15e72',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcfgr_5fppre1_5fmsk_598',['RCC_CFGR_PPRE1_Msk',['../group___peripheral___registers___bits___definition.html#ga48842716ad7c2280b8ddbac071cdc773',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcfgr_5fppre1_5fpos_599',['RCC_CFGR_PPRE1_Pos',['../group___peripheral___registers___bits___definition.html#gaf0f0825acc89712f58b97844fbac93ca',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcfgr_5fppre2_600',['RCC_CFGR_PPRE2',['../group___peripheral___registers___bits___definition.html#gad61bd4f9f345ba41806813b0bfff1311',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcfgr_5fppre2_5f0_601',['RCC_CFGR_PPRE2_0',['../group___peripheral___registers___bits___definition.html#ga82ca63155494ed59eb5e34bec1e5f4e9',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcfgr_5fppre2_5f1_602',['RCC_CFGR_PPRE2_1',['../group___peripheral___registers___bits___definition.html#gafdb19c9e76fe8e8a7c991714c92e937f',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcfgr_5fppre2_5f2_603',['RCC_CFGR_PPRE2_2',['../group___peripheral___registers___bits___definition.html#ga9adc802687eab5b6ece99a20793219db',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcfgr_5fppre2_5fdiv1_604',['RCC_CFGR_PPRE2_DIV1',['../group___peripheral___registers___bits___definition.html#ga247aebf1999a38ea07785558d277bb1a',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcfgr_5fppre2_5fdiv16_605',['RCC_CFGR_PPRE2_DIV16',['../group___peripheral___registers___bits___definition.html#gaece3ee58d4138f7452733bfa1ad37eb9',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcfgr_5fppre2_5fdiv2_606',['RCC_CFGR_PPRE2_DIV2',['../group___peripheral___registers___bits___definition.html#ga99d9c91eaad122460d324a71cc939d1b',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcfgr_5fppre2_5fdiv4_607',['RCC_CFGR_PPRE2_DIV4',['../group___peripheral___registers___bits___definition.html#ga4340fc3fc52eca36eb302959fbecb715',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcfgr_5fppre2_5fdiv8_608',['RCC_CFGR_PPRE2_DIV8',['../group___peripheral___registers___bits___definition.html#ga412b382a1134e0ee5614e0f4bcf97552',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcfgr_5fppre2_5fmsk_609',['RCC_CFGR_PPRE2_Msk',['../group___peripheral___registers___bits___definition.html#ga489e055e843ee5090c0174bbb9af9a67',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcfgr_5fppre2_5fpos_610',['RCC_CFGR_PPRE2_Pos',['../group___peripheral___registers___bits___definition.html#ga562db8b1e75fa862a3652b56a29b9fb6',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcfgr_5frtcpre_611',['RCC_CFGR_RTCPRE',['../group___peripheral___registers___bits___definition.html#gad7c067c52ecd135252c691aad32c0b83',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcfgr_5frtcpre_5f0_612',['RCC_CFGR_RTCPRE_0',['../group___peripheral___registers___bits___definition.html#ga702f887571365eeb42d74b9b9cc6fe0d',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcfgr_5frtcpre_5f1_613',['RCC_CFGR_RTCPRE_1',['../group___peripheral___registers___bits___definition.html#ga1191ba4a2e089f9921d77be57394dec4',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcfgr_5frtcpre_5f2_614',['RCC_CFGR_RTCPRE_2',['../group___peripheral___registers___bits___definition.html#gae62885f29418cc83a57964fe631282cb',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcfgr_5frtcpre_5f3_615',['RCC_CFGR_RTCPRE_3',['../group___peripheral___registers___bits___definition.html#ga9c703b8d9827f58e7ea783c6a9b74e41',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcfgr_5frtcpre_5f4_616',['RCC_CFGR_RTCPRE_4',['../group___peripheral___registers___bits___definition.html#ga02b93e5154259a1a201bbb9c9b903c0a',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcfgr_5frtcpre_5fmsk_617',['RCC_CFGR_RTCPRE_Msk',['../group___peripheral___registers___bits___definition.html#ga850304b36d321ade71b90ca011ee5f74',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcfgr_5frtcpre_5fpos_618',['RCC_CFGR_RTCPRE_Pos',['../group___peripheral___registers___bits___definition.html#ga2eaafc6a34ae561f23f1139a746cbfd8',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcfgr_5fsw_619',['RCC_CFGR_SW',['../group___peripheral___registers___bits___definition.html#ga0eea5e5f7743a7e8995b8beeb18355c1',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcfgr_5fsw_5f0_620',['RCC_CFGR_SW_0',['../group___peripheral___registers___bits___definition.html#ga99f08d86fd41824058a7fdf817f7e2fd',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcfgr_5fsw_5f1_621',['RCC_CFGR_SW_1',['../group___peripheral___registers___bits___definition.html#ga72d51cb5d66ee1aa4d2c6f14796a072f',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcfgr_5fsw_5fhse_622',['RCC_CFGR_SW_HSE',['../group___peripheral___registers___bits___definition.html#gafb563f217242d969f4355d0818fde705',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcfgr_5fsw_5fhsi_623',['RCC_CFGR_SW_HSI',['../group___peripheral___registers___bits___definition.html#gacbac8bae4f0808b3c3a5185aa10081fb',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcfgr_5fsw_5fmsk_624',['RCC_CFGR_SW_Msk',['../group___peripheral___registers___bits___definition.html#ga06ad7777386bbf5555ef8b02939197aa',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcfgr_5fsw_5fpll_625',['RCC_CFGR_SW_PLL',['../group___peripheral___registers___bits___definition.html#ga87389cacb2eaf53730da13a2a33cd487',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcfgr_5fsw_5fpos_626',['RCC_CFGR_SW_Pos',['../group___peripheral___registers___bits___definition.html#ga0cf9dd749ab13a3b9d55308e24f60160',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcfgr_5fsws_627',['RCC_CFGR_SWS',['../group___peripheral___registers___bits___definition.html#ga15bf2269500dc97e137315f44aa015c9',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcfgr_5fsws_5f0_628',['RCC_CFGR_SWS_0',['../group___peripheral___registers___bits___definition.html#ga1eae59112c51def51979e31e8695b39f',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcfgr_5fsws_5f1_629',['RCC_CFGR_SWS_1',['../group___peripheral___registers___bits___definition.html#gaad3a5718999d7259f216137a23c2a379',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcfgr_5fsws_5fhse_630',['RCC_CFGR_SWS_HSE',['../group___peripheral___registers___bits___definition.html#gae09a0202f441c1a43e69c62331d50a08',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcfgr_5fsws_5fhsi_631',['RCC_CFGR_SWS_HSI',['../group___peripheral___registers___bits___definition.html#ga6764639cf221e1ebc0b5448dcaed590a',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcfgr_5fsws_5fmsk_632',['RCC_CFGR_SWS_Msk',['../group___peripheral___registers___bits___definition.html#gaef0b6cd7629c047bcc4ac3e88d920e25',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcfgr_5fsws_5fpll_633',['RCC_CFGR_SWS_PLL',['../group___peripheral___registers___bits___definition.html#ga2c67e2279804a83ef24438267d9d4a6c',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcfgr_5fsws_5fpos_634',['RCC_CFGR_SWS_Pos',['../group___peripheral___registers___bits___definition.html#gab79d13a977d5b0c2e132b4939663158d',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcir_5fcssc_635',['RCC_CIR_CSSC',['../group___peripheral___registers___bits___definition.html#ga46edb2b9568f002feba7b4312ed92c1f',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcir_5fcssc_5fmsk_636',['RCC_CIR_CSSC_Msk',['../group___peripheral___registers___bits___definition.html#ga66a9cf76bbf90f432815527965cb5c3e',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcir_5fcssc_5fpos_637',['RCC_CIR_CSSC_Pos',['../group___peripheral___registers___bits___definition.html#ga5c7cf29f8c4b46a59751e6fdc44f8153',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcir_5fcssf_638',['RCC_CIR_CSSF',['../group___peripheral___registers___bits___definition.html#gad66b719e4061294de35af58cc27aba7f',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcir_5fcssf_5fmsk_639',['RCC_CIR_CSSF_Msk',['../group___peripheral___registers___bits___definition.html#ga8eb3ec455be7a5e4ffbe0abc9e2a77eb',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcir_5fcssf_5fpos_640',['RCC_CIR_CSSF_Pos',['../group___peripheral___registers___bits___definition.html#gab82aae1efb70d76f85bcad7ec0632d4c',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcir_5fhserdyc_641',['RCC_CIR_HSERDYC',['../group___peripheral___registers___bits___definition.html#ga9464e8188d717902990b467a9396d238',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcir_5fhserdyc_5fmsk_642',['RCC_CIR_HSERDYC_Msk',['../group___peripheral___registers___bits___definition.html#ga2211dd40005f6152d0e8258d380a6713',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcir_5fhserdyc_5fpos_643',['RCC_CIR_HSERDYC_Pos',['../group___peripheral___registers___bits___definition.html#ga34e713e2755ef1c9210e3b8c8f2c718e',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcir_5fhserdyf_644',['RCC_CIR_HSERDYF',['../group___peripheral___registers___bits___definition.html#ga11ea196450aac9ac35e283a66afc3da6',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcir_5fhserdyf_5fmsk_645',['RCC_CIR_HSERDYF_Msk',['../group___peripheral___registers___bits___definition.html#ga1cbcd4b04177bd2420126b0de418de2e',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcir_5fhserdyf_5fpos_646',['RCC_CIR_HSERDYF_Pos',['../group___peripheral___registers___bits___definition.html#ga37a0fe34b1b1c44c6982a69fa082f6c0',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcir_5fhserdyie_647',['RCC_CIR_HSERDYIE',['../group___peripheral___registers___bits___definition.html#ga5492f9b58600cf66616eb931b48b3c11',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcir_5fhserdyie_5fmsk_648',['RCC_CIR_HSERDYIE_Msk',['../group___peripheral___registers___bits___definition.html#ga2f6db5519f1bbb1d42ee0f43367e7fd9',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcir_5fhserdyie_5fpos_649',['RCC_CIR_HSERDYIE_Pos',['../group___peripheral___registers___bits___definition.html#ga8a258b8f9041e6a3e30a12f371e1e289',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcir_5fhsirdyc_650',['RCC_CIR_HSIRDYC',['../group___peripheral___registers___bits___definition.html#gad1b58377908e5c31a684747d0a80ecb2',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcir_5fhsirdyc_5fmsk_651',['RCC_CIR_HSIRDYC_Msk',['../group___peripheral___registers___bits___definition.html#ga657cffa4be41e26f7b5383719dd7781a',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcir_5fhsirdyc_5fpos_652',['RCC_CIR_HSIRDYC_Pos',['../group___peripheral___registers___bits___definition.html#gaf2ccc89ed1b4d16c5f2804c216c5adc3',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcir_5fhsirdyf_653',['RCC_CIR_HSIRDYF',['../group___peripheral___registers___bits___definition.html#gad38877547c4cbbb94659d5726f377163',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcir_5fhsirdyf_5fmsk_654',['RCC_CIR_HSIRDYF_Msk',['../group___peripheral___registers___bits___definition.html#ga8c72d692b99c4539982fea718b2ba8a6',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcir_5fhsirdyf_5fpos_655',['RCC_CIR_HSIRDYF_Pos',['../group___peripheral___registers___bits___definition.html#gab8f2d94fb254c9a2fe2c9aadcef7e147',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcir_5fhsirdyie_656',['RCC_CIR_HSIRDYIE',['../group___peripheral___registers___bits___definition.html#gac714351a6f9dab4741354fb017638580',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcir_5fhsirdyie_5fmsk_657',['RCC_CIR_HSIRDYIE_Msk',['../group___peripheral___registers___bits___definition.html#gac7aeb42d0a5ef8e7bac1876e0689814e',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcir_5fhsirdyie_5fpos_658',['RCC_CIR_HSIRDYIE_Pos',['../group___peripheral___registers___bits___definition.html#gafc61d466aac29f7fbd88b0245d6cf8c1',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcir_5flserdyc_659',['RCC_CIR_LSERDYC',['../group___peripheral___registers___bits___definition.html#ga144b5147f3a8d0bfda04618e301986aa',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcir_5flserdyc_5fmsk_660',['RCC_CIR_LSERDYC_Msk',['../group___peripheral___registers___bits___definition.html#gaba1367e36a992aae85f9e8f9921e9426',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcir_5flserdyc_5fpos_661',['RCC_CIR_LSERDYC_Pos',['../group___peripheral___registers___bits___definition.html#ga0f106e06b78f78c5a520faa1b180de2e',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcir_5flserdyf_662',['RCC_CIR_LSERDYF',['../group___peripheral___registers___bits___definition.html#gabfc100e7ae673dfcec7be79af0d91dfe',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcir_5flserdyf_5fmsk_663',['RCC_CIR_LSERDYF_Msk',['../group___peripheral___registers___bits___definition.html#ga58e246b3d87483bf3ca4a55d470acf4f',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcir_5flserdyf_5fpos_664',['RCC_CIR_LSERDYF_Pos',['../group___peripheral___registers___bits___definition.html#ga9a2be1b77680f922f877e6d1b56287f3',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcir_5flserdyie_665',['RCC_CIR_LSERDYIE',['../group___peripheral___registers___bits___definition.html#ga6a0ad2672c9ba1b26012cbc6d423dff8',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcir_5flserdyie_5fmsk_666',['RCC_CIR_LSERDYIE_Msk',['../group___peripheral___registers___bits___definition.html#ga24446323cbae3ab353f248d23655b822',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcir_5flserdyie_5fpos_667',['RCC_CIR_LSERDYIE_Pos',['../group___peripheral___registers___bits___definition.html#ga7eabf777f7d12a95038d5408cd9a3225',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcir_5flsirdyc_668',['RCC_CIR_LSIRDYC',['../group___peripheral___registers___bits___definition.html#ga982989563f1a95c89bf7f4a25d99f704',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcir_5flsirdyc_5fmsk_669',['RCC_CIR_LSIRDYC_Msk',['../group___peripheral___registers___bits___definition.html#ga11edf191b118ca860e0eca011f113ad9',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcir_5flsirdyc_5fpos_670',['RCC_CIR_LSIRDYC_Pos',['../group___peripheral___registers___bits___definition.html#ga1baeac3a2504113deb0a65d46d7314e2',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcir_5flsirdyf_671',['RCC_CIR_LSIRDYF',['../group___peripheral___registers___bits___definition.html#gacb94ccfe6a212f020e732d1dd787a6fb',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcir_5flsirdyf_5fmsk_672',['RCC_CIR_LSIRDYF_Msk',['../group___peripheral___registers___bits___definition.html#gac2542dd9dbe634971278d2f4e24c3091',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcir_5flsirdyf_5fpos_673',['RCC_CIR_LSIRDYF_Pos',['../group___peripheral___registers___bits___definition.html#ga9e24ddcd9380a97107db8d483fdd9cb2',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcir_5flsirdyie_674',['RCC_CIR_LSIRDYIE',['../group___peripheral___registers___bits___definition.html#ga872ba937149a7372138df06f8188ab56',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcir_5flsirdyie_5fmsk_675',['RCC_CIR_LSIRDYIE_Msk',['../group___peripheral___registers___bits___definition.html#ga7ba1782e2e14efd1bd9feabf1608fd5a',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcir_5flsirdyie_5fpos_676',['RCC_CIR_LSIRDYIE_Pos',['../group___peripheral___registers___bits___definition.html#ga085c2d83db641a456df4a5f67582bff5',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcir_5fplli2srdyc_677',['RCC_CIR_PLLI2SRDYC',['../group___peripheral___registers___bits___definition.html#ga73e79cc7236f5f76cb97c8012771e6bb',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcir_5fplli2srdyc_5fmsk_678',['RCC_CIR_PLLI2SRDYC_Msk',['../group___peripheral___registers___bits___definition.html#gad6a1a17873c5e712e9ed47d92fbc99cd',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcir_5fplli2srdyc_5fpos_679',['RCC_CIR_PLLI2SRDYC_Pos',['../group___peripheral___registers___bits___definition.html#gadca4503c3752588bd3efeea2b5f0c99a',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcir_5fplli2srdyf_680',['RCC_CIR_PLLI2SRDYF',['../group___peripheral___registers___bits___definition.html#gad338d8663c078cf3d73e4bfaa44da093',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcir_5fplli2srdyf_5fmsk_681',['RCC_CIR_PLLI2SRDYF_Msk',['../group___peripheral___registers___bits___definition.html#ga61e88621c6cbc397e6c0872c98f11151',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcir_5fplli2srdyf_5fpos_682',['RCC_CIR_PLLI2SRDYF_Pos',['../group___peripheral___registers___bits___definition.html#ga23921a147e121d49592e590f773f3c6c',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcir_5fplli2srdyie_683',['RCC_CIR_PLLI2SRDYIE',['../group___peripheral___registers___bits___definition.html#ga1ca3cbf69c7cce53e974316dbf38d3dc',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcir_5fplli2srdyie_5fmsk_684',['RCC_CIR_PLLI2SRDYIE_Msk',['../group___peripheral___registers___bits___definition.html#ga6af4a5b0b017c2dde04fa660950578cc',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcir_5fplli2srdyie_5fpos_685',['RCC_CIR_PLLI2SRDYIE_Pos',['../group___peripheral___registers___bits___definition.html#gac69e15926ecae3167dfbc860e784e7f3',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcir_5fpllrdyc_686',['RCC_CIR_PLLRDYC',['../group___peripheral___registers___bits___definition.html#ga245af864b194f0c2b2389ea1ee49a396',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcir_5fpllrdyc_5fmsk_687',['RCC_CIR_PLLRDYC_Msk',['../group___peripheral___registers___bits___definition.html#ga1ee90d2a5649fe386ba87eeead64ada1',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcir_5fpllrdyc_5fpos_688',['RCC_CIR_PLLRDYC_Pos',['../group___peripheral___registers___bits___definition.html#ga2884b24e49761690cfc68a9929c7b10d',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcir_5fpllrdyf_689',['RCC_CIR_PLLRDYF',['../group___peripheral___registers___bits___definition.html#ga0f007895a17e668f22f7b8b24ca90aec',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcir_5fpllrdyf_5fmsk_690',['RCC_CIR_PLLRDYF_Msk',['../group___peripheral___registers___bits___definition.html#ga88d53f154b50703f3ab18f017b7ace1c',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcir_5fpllrdyf_5fpos_691',['RCC_CIR_PLLRDYF_Pos',['../group___peripheral___registers___bits___definition.html#ga4be890d102ccff40b4e370d575940af5',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcir_5fpllrdyie_692',['RCC_CIR_PLLRDYIE',['../group___peripheral___registers___bits___definition.html#ga1b70927cab2ba9cf82d1620cf88b0f95',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcir_5fpllrdyie_5fmsk_693',['RCC_CIR_PLLRDYIE_Msk',['../group___peripheral___registers___bits___definition.html#ga6fdb478ae8c7d99d780c78bb68830dd5',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcir_5fpllrdyie_5fpos_694',['RCC_CIR_PLLRDYIE_Pos',['../group___peripheral___registers___bits___definition.html#ga54f619655facb49336e0baf439ef130b',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcr_5fcsson_695',['RCC_CR_CSSON',['../group___peripheral___registers___bits___definition.html#gacc05308869ad055e1e6f2c32d738aecd',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcr_5fcsson_5fmsk_696',['RCC_CR_CSSON_Msk',['../group___peripheral___registers___bits___definition.html#gaaf02f4983b7cd9e1b664729cf6abb1f5',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcr_5fcsson_5fpos_697',['RCC_CR_CSSON_Pos',['../group___peripheral___registers___bits___definition.html#gabf8f4f358e06d0c2b8a040474c0c75aa',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcr_5fhsebyp_698',['RCC_CR_HSEBYP',['../group___peripheral___registers___bits___definition.html#gaa3288090671af5a959aae4d7f7696d55',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcr_5fhsebyp_5fmsk_699',['RCC_CR_HSEBYP_Msk',['../group___peripheral___registers___bits___definition.html#gac04d2021b54bf9a1b66578c67a436b45',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcr_5fhsebyp_5fpos_700',['RCC_CR_HSEBYP_Pos',['../group___peripheral___registers___bits___definition.html#gac11714ac23d6cbef2f25c8b6c38e07f9',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcr_5fhseon_701',['RCC_CR_HSEON',['../group___peripheral___registers___bits___definition.html#gadb8228c9020595b4cf9995137b8c9a7d',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcr_5fhseon_5fmsk_702',['RCC_CR_HSEON_Msk',['../group___peripheral___registers___bits___definition.html#ga71f5167bea85df0b393de9d3846ea8d1',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcr_5fhseon_5fpos_703',['RCC_CR_HSEON_Pos',['../group___peripheral___registers___bits___definition.html#gacf45a431682229e7131fab4a9df6bb8a',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcr_5fhserdy_704',['RCC_CR_HSERDY',['../group___peripheral___registers___bits___definition.html#ga86a34e00182c83409d89ff566cb02cc4',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcr_5fhserdy_5fmsk_705',['RCC_CR_HSERDY_Msk',['../group___peripheral___registers___bits___definition.html#ga993e8ee50d7049e18ec9ee1e5ddcaa64',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcr_5fhserdy_5fpos_706',['RCC_CR_HSERDY_Pos',['../group___peripheral___registers___bits___definition.html#ga0b35f100d3353d0d73ef1f9099a70285',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcr_5fhsical_707',['RCC_CR_HSICAL',['../group___peripheral___registers___bits___definition.html#ga67ae770db9851f14ad7c14a693f0f6d3',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcr_5fhsical_5f0_708',['RCC_CR_HSICAL_0',['../group___peripheral___registers___bits___definition.html#gad7daa7754e54d65916ddc54f37274d3a',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcr_5fhsical_5f1_709',['RCC_CR_HSICAL_1',['../group___peripheral___registers___bits___definition.html#ga78054087161dee567cadbb4b4b96fb08',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcr_5fhsical_5f2_710',['RCC_CR_HSICAL_2',['../group___peripheral___registers___bits___definition.html#gab0c4bac85beb7de5916897f88150dc3f',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcr_5fhsical_5f3_711',['RCC_CR_HSICAL_3',['../group___peripheral___registers___bits___definition.html#ga03f71cd53f075e9d35fcbfe7ed3f6e12',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcr_5fhsical_5f4_712',['RCC_CR_HSICAL_4',['../group___peripheral___registers___bits___definition.html#gaf26eb00e1872a3754f200a3c32019e50',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcr_5fhsical_5f5_713',['RCC_CR_HSICAL_5',['../group___peripheral___registers___bits___definition.html#ga4c5b733061a3c4c6d69a7a15cbcb0b87',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcr_5fhsical_5f6_714',['RCC_CR_HSICAL_6',['../group___peripheral___registers___bits___definition.html#gaee2d6b30ee4bf41d2b171adf273a6ee7',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcr_5fhsical_5f7_715',['RCC_CR_HSICAL_7',['../group___peripheral___registers___bits___definition.html#gab42d5e412867df093ec2ea4b8dc2bf29',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcr_5fhsical_5fmsk_716',['RCC_CR_HSICAL_Msk',['../group___peripheral___registers___bits___definition.html#ga6b0cd0084e6349428abdb91755f0a3d3',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcr_5fhsical_5fpos_717',['RCC_CR_HSICAL_Pos',['../group___peripheral___registers___bits___definition.html#gaaca19ae5be8263a15a6122f80820ddab',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcr_5fhsion_718',['RCC_CR_HSION',['../group___peripheral___registers___bits___definition.html#gaf4fcacf94a97f7d49a70e089b39cf474',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcr_5fhsion_5fmsk_719',['RCC_CR_HSION_Msk',['../group___peripheral___registers___bits___definition.html#ga21adcb31640b6407baff549c0e7d1af0',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcr_5fhsion_5fpos_720',['RCC_CR_HSION_Pos',['../group___peripheral___registers___bits___definition.html#ga24995a185bfa02f4ed0624e1a5921585',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcr_5fhsirdy_721',['RCC_CR_HSIRDY',['../group___peripheral___registers___bits___definition.html#ga9dbac3f2bc04f04ebafe1e66ae3fcf0d',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcr_5fhsirdy_5fmsk_722',['RCC_CR_HSIRDY_Msk',['../group___peripheral___registers___bits___definition.html#ga55c613573a83b8399c228dca39063947',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcr_5fhsirdy_5fpos_723',['RCC_CR_HSIRDY_Pos',['../group___peripheral___registers___bits___definition.html#ga77c32f27431ef9437aa34fb0f1d41da9',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcr_5fhsitrim_724',['RCC_CR_HSITRIM',['../group___peripheral___registers___bits___definition.html#ga5cb4397b2095c31660a01b748386aa70',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcr_5fhsitrim_5f0_725',['RCC_CR_HSITRIM_0',['../group___peripheral___registers___bits___definition.html#gaab999bbbc1d365d0100d34eaa9f426eb',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcr_5fhsitrim_5f1_726',['RCC_CR_HSITRIM_1',['../group___peripheral___registers___bits___definition.html#ga569d6a29d774e0f125b0c2b3671fae3c',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcr_5fhsitrim_5f2_727',['RCC_CR_HSITRIM_2',['../group___peripheral___registers___bits___definition.html#ga10d80d64137e36f5183f6aa7002de6f5',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcr_5fhsitrim_5f3_728',['RCC_CR_HSITRIM_3',['../group___peripheral___registers___bits___definition.html#gafe20245d2d971238dba9ee371a299ba9',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcr_5fhsitrim_5f4_729',['RCC_CR_HSITRIM_4',['../group___peripheral___registers___bits___definition.html#ga1f9ab2e93a0b9b70d33812bcc5e920c1',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcr_5fhsitrim_5fmsk_730',['RCC_CR_HSITRIM_Msk',['../group___peripheral___registers___bits___definition.html#ga47c875ded980268c8d87803fde1d3add',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcr_5fhsitrim_5fpos_731',['RCC_CR_HSITRIM_Pos',['../group___peripheral___registers___bits___definition.html#ga1eb6ab7cdd2569af23f9688384d577bb',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcr_5fplli2son_732',['RCC_CR_PLLI2SON',['../group___peripheral___registers___bits___definition.html#ga3ccb8964b640530f1080f9ea549d8133',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcr_5fplli2son_5fmsk_733',['RCC_CR_PLLI2SON_Msk',['../group___peripheral___registers___bits___definition.html#ga82caf73e368dd6e0af79ffff40c4c158',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcr_5fplli2son_5fpos_734',['RCC_CR_PLLI2SON_Pos',['../group___peripheral___registers___bits___definition.html#ga6c0b3e1822ce926499c6912929b96733',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcr_5fplli2srdy_735',['RCC_CR_PLLI2SRDY',['../group___peripheral___registers___bits___definition.html#ga7354703f289244a71753debf3ae26e46',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcr_5fplli2srdy_5fmsk_736',['RCC_CR_PLLI2SRDY_Msk',['../group___peripheral___registers___bits___definition.html#gac102f1739d82c9f002f6d107e37c6d63',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcr_5fplli2srdy_5fpos_737',['RCC_CR_PLLI2SRDY_Pos',['../group___peripheral___registers___bits___definition.html#gadcd54f910af8002a097dd8f827960112',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcr_5fpllon_738',['RCC_CR_PLLON',['../group___peripheral___registers___bits___definition.html#gad0e73d5b0a4883e074d40029b49ee47e',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcr_5fpllon_5fmsk_739',['RCC_CR_PLLON_Msk',['../group___peripheral___registers___bits___definition.html#ga60dd7c471ec3ba4587e0cecdc8238f87',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcr_5fpllon_5fpos_740',['RCC_CR_PLLON_Pos',['../group___peripheral___registers___bits___definition.html#ga9969597c000e9ed714c2472e019f7df3',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcr_5fpllrdy_741',['RCC_CR_PLLRDY',['../group___peripheral___registers___bits___definition.html#gafa12d7ac6a7f0f91d066aeb2c6071888',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcr_5fpllrdy_5fmsk_742',['RCC_CR_PLLRDY_Msk',['../group___peripheral___registers___bits___definition.html#ga237ae9216a3ae5c1f6833a52995413df',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcr_5fpllrdy_5fpos_743',['RCC_CR_PLLRDY_Pos',['../group___peripheral___registers___bits___definition.html#gaa99ebf56183320b517b804fbc76e8ce4',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcsr_5fborrstf_744',['RCC_CSR_BORRSTF',['../group___peripheral___registers___bits___definition.html#ga6685c7bd94a46c82c7ca69afa1707c39',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcsr_5fborrstf_5fmsk_745',['RCC_CSR_BORRSTF_Msk',['../group___peripheral___registers___bits___definition.html#ga55345f6a3e5c36cad82d85c3c7c9114c',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcsr_5fborrstf_5fpos_746',['RCC_CSR_BORRSTF_Pos',['../group___peripheral___registers___bits___definition.html#ga9c08aed9f0628271098706c4b46be813',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcsr_5fiwdgrstf_747',['RCC_CSR_IWDGRSTF',['../group___peripheral___registers___bits___definition.html#ga22a7079ba87dd7acd5ed7fe7b704e85f',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcsr_5fiwdgrstf_5fmsk_748',['RCC_CSR_IWDGRSTF_Msk',['../group___peripheral___registers___bits___definition.html#gabb81cb1777e6e846b6199b64132bcb97',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcsr_5fiwdgrstf_5fpos_749',['RCC_CSR_IWDGRSTF_Pos',['../group___peripheral___registers___bits___definition.html#ga8fbb93c907ec9ca631e6657eb22b85a3',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcsr_5flpwrrstf_750',['RCC_CSR_LPWRRSTF',['../group___peripheral___registers___bits___definition.html#ga675455250b91f125d52f5d347c2c0fbf',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcsr_5flpwrrstf_5fmsk_751',['RCC_CSR_LPWRRSTF_Msk',['../group___peripheral___registers___bits___definition.html#ga8b42e835fb77d45779cdf4d22a0ea22a',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcsr_5flpwrrstf_5fpos_752',['RCC_CSR_LPWRRSTF_Pos',['../group___peripheral___registers___bits___definition.html#ga2761b43e9b00d52102efb7375a86e6e0',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcsr_5flsion_753',['RCC_CSR_LSION',['../group___peripheral___registers___bits___definition.html#ga803cbf97bda1ebaf9afee2a3c9f0851b',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcsr_5flsion_5fmsk_754',['RCC_CSR_LSION_Msk',['../group___peripheral___registers___bits___definition.html#gabe63b332158f8886948205ff9edcf248',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcsr_5flsion_5fpos_755',['RCC_CSR_LSION_Pos',['../group___peripheral___registers___bits___definition.html#gafc156654e34b1b6206760ba8d864c6c8',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcsr_5flsirdy_756',['RCC_CSR_LSIRDY',['../group___peripheral___registers___bits___definition.html#gab569110e757aee573ebf9ad80812e8bb',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcsr_5flsirdy_5fmsk_757',['RCC_CSR_LSIRDY_Msk',['../group___peripheral___registers___bits___definition.html#ga49a5c93576efd3e5d284351db6125373',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcsr_5flsirdy_5fpos_758',['RCC_CSR_LSIRDY_Pos',['../group___peripheral___registers___bits___definition.html#ga68272a20b7fe83a0e08b1deb4aeacf55',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcsr_5fpadrstf_759',['RCC_CSR_PADRSTF',['../group___peripheral___registers___bits___definition.html#gaf600bc53fc80265347f6c76c6b8b728a',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcsr_5fpinrstf_760',['RCC_CSR_PINRSTF',['../group___peripheral___registers___bits___definition.html#ga4e26d2902d11e638cd0b702332f53ab1',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcsr_5fpinrstf_5fmsk_761',['RCC_CSR_PINRSTF_Msk',['../group___peripheral___registers___bits___definition.html#ga13e888e00c5b2226b70179c6c69b77a6',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcsr_5fpinrstf_5fpos_762',['RCC_CSR_PINRSTF_Pos',['../group___peripheral___registers___bits___definition.html#ga47a45faed934912e57c0dea6d6af8227',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcsr_5fporrstf_763',['RCC_CSR_PORRSTF',['../group___peripheral___registers___bits___definition.html#ga837e2d7e2395ac45ebe2aea95ecde9bf',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcsr_5fporrstf_5fmsk_764',['RCC_CSR_PORRSTF_Msk',['../group___peripheral___registers___bits___definition.html#ga6ea00bd02372ecbc60c5fa71a37dc8dd',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcsr_5fporrstf_5fpos_765',['RCC_CSR_PORRSTF_Pos',['../group___peripheral___registers___bits___definition.html#gab8d531dd5cf68eb67b1bce22ceddaac4',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcsr_5frmvf_766',['RCC_CSR_RMVF',['../group___peripheral___registers___bits___definition.html#gafc26c5996b14005a70afbeaa29aae716',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcsr_5frmvf_5fmsk_767',['RCC_CSR_RMVF_Msk',['../group___peripheral___registers___bits___definition.html#ga82a7f8a2897bcc1313d58389fc18ad4c',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcsr_5frmvf_5fpos_768',['RCC_CSR_RMVF_Pos',['../group___peripheral___registers___bits___definition.html#gae97ee308ed96cdb97bc991b34aa95be4',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcsr_5fsftrstf_769',['RCC_CSR_SFTRSTF',['../group___peripheral___registers___bits___definition.html#ga16e89534934436ee8958440882b71e6f',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcsr_5fsftrstf_5fmsk_770',['RCC_CSR_SFTRSTF_Msk',['../group___peripheral___registers___bits___definition.html#ga7217efb6cbdb6fbf39721fe496249225',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcsr_5fsftrstf_5fpos_771',['RCC_CSR_SFTRSTF_Pos',['../group___peripheral___registers___bits___definition.html#ga02078fdb0a3610702b75d5e05dbb92af',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcsr_5fwdgrstf_772',['RCC_CSR_WDGRSTF',['../group___peripheral___registers___bits___definition.html#ga1507e79ffc475547f2a9c9238965b57f',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcsr_5fwwdgrstf_773',['RCC_CSR_WWDGRSTF',['../group___peripheral___registers___bits___definition.html#gacabd7bbde7e78c9c8f5fd46e34771826',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcsr_5fwwdgrstf_5fmsk_774',['RCC_CSR_WWDGRSTF_Msk',['../group___peripheral___registers___bits___definition.html#ga6d9afc0a5d27d08ef63dde9f0a39514d',1,'stm32f407xx_matlab.h']]], - ['rcc_5fcsr_5fwwdgrstf_5fpos_775',['RCC_CSR_WWDGRSTF_Pos',['../group___peripheral___registers___bits___definition.html#gac3b146c508145d8e03143a991615ed81',1,'stm32f407xx_matlab.h']]], - ['rcc_5firqn_776',['RCC_IRQn',['../group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a5710b22392997bac63daa5c999730f77',1,'stm32f407xx_matlab.h']]], - ['rcc_5fmax_5ffrequency_777',['RCC_MAX_FREQUENCY',['../group___exported__macros.html#ga08aeea283003a2c787227347087b5b1f',1,'stm32f407xx_matlab.h']]], - ['rcc_5fmax_5ffrequency_5fscale1_778',['RCC_MAX_FREQUENCY_SCALE1',['../group___exported__macros.html#ga152c4bb0b78589a06d72e0170dd3b304',1,'stm32f407xx_matlab.h']]], - ['rcc_5fmax_5ffrequency_5fscale2_779',['RCC_MAX_FREQUENCY_SCALE2',['../group___exported__macros.html#gafcb2c5211d9cbed86b111c83a0ce427b',1,'stm32f407xx_matlab.h']]], - ['rcc_5fpllcfgr_5fpllm_780',['RCC_PLLCFGR_PLLM',['../group___peripheral___registers___bits___definition.html#ga9a42e8b9ee60126976d9be056e5e66b1',1,'stm32f407xx_matlab.h']]], - ['rcc_5fpllcfgr_5fpllm_5f0_781',['RCC_PLLCFGR_PLLM_0',['../group___peripheral___registers___bits___definition.html#ga813e3d6b41b4338ae5aea47a2bdbab01',1,'stm32f407xx_matlab.h']]], - ['rcc_5fpllcfgr_5fpllm_5f1_782',['RCC_PLLCFGR_PLLM_1',['../group___peripheral___registers___bits___definition.html#ga84ae6e7405926717249a9852acda1f10',1,'stm32f407xx_matlab.h']]], - ['rcc_5fpllcfgr_5fpllm_5f2_783',['RCC_PLLCFGR_PLLM_2',['../group___peripheral___registers___bits___definition.html#ga989f5ea1ac0275a2c15bf09408c8a4c6',1,'stm32f407xx_matlab.h']]], - ['rcc_5fpllcfgr_5fpllm_5f3_784',['RCC_PLLCFGR_PLLM_3',['../group___peripheral___registers___bits___definition.html#ga9cdeab6a08889692656228ab1186e28c',1,'stm32f407xx_matlab.h']]], - ['rcc_5fpllcfgr_5fpllm_5f4_785',['RCC_PLLCFGR_PLLM_4',['../group___peripheral___registers___bits___definition.html#ga20af5f07ceef21b957db9391fd8bd898',1,'stm32f407xx_matlab.h']]], - ['rcc_5fpllcfgr_5fpllm_5f5_786',['RCC_PLLCFGR_PLLM_5',['../group___peripheral___registers___bits___definition.html#ga195dfe1b9b158aa00996867bebd9c225',1,'stm32f407xx_matlab.h']]], - ['rcc_5fpllcfgr_5fpllm_5fmsk_787',['RCC_PLLCFGR_PLLM_Msk',['../group___peripheral___registers___bits___definition.html#ga04d893187396788d18a3eb1cc7028686',1,'stm32f407xx_matlab.h']]], - ['rcc_5fpllcfgr_5fpllm_5fpos_788',['RCC_PLLCFGR_PLLM_Pos',['../group___peripheral___registers___bits___definition.html#ga681f0ec251dffb419df8fa23137fe810',1,'stm32f407xx_matlab.h']]], - ['rcc_5fpllcfgr_5fplln_789',['RCC_PLLCFGR_PLLN',['../group___peripheral___registers___bits___definition.html#ga4b571901d7cdc93ca1ecc1531f26ba6a',1,'stm32f407xx_matlab.h']]], - ['rcc_5fpllcfgr_5fplln_5f0_790',['RCC_PLLCFGR_PLLN_0',['../group___peripheral___registers___bits___definition.html#gade84dfb497ed82c0cbbc40049ef3da2c',1,'stm32f407xx_matlab.h']]], - ['rcc_5fpllcfgr_5fplln_5f1_791',['RCC_PLLCFGR_PLLN_1',['../group___peripheral___registers___bits___definition.html#gad54b80f8edb3a1f34d390382580edaf3',1,'stm32f407xx_matlab.h']]], - ['rcc_5fpllcfgr_5fplln_5f2_792',['RCC_PLLCFGR_PLLN_2',['../group___peripheral___registers___bits___definition.html#ga6c165a47d134f31f9dff12d1e6f709f3',1,'stm32f407xx_matlab.h']]], - ['rcc_5fpllcfgr_5fplln_5f3_793',['RCC_PLLCFGR_PLLN_3',['../group___peripheral___registers___bits___definition.html#ga5b19e3e1f2dbe4c2327ebee7e9647365',1,'stm32f407xx_matlab.h']]], - ['rcc_5fpllcfgr_5fplln_5f4_794',['RCC_PLLCFGR_PLLN_4',['../group___peripheral___registers___bits___definition.html#gaeb4707942496f45d3cf85acfdeb37475',1,'stm32f407xx_matlab.h']]], - ['rcc_5fpllcfgr_5fplln_5f5_795',['RCC_PLLCFGR_PLLN_5',['../group___peripheral___registers___bits___definition.html#gaefb9ac3678faab95ddc7d42b2316b8ab',1,'stm32f407xx_matlab.h']]], - ['rcc_5fpllcfgr_5fplln_5f6_796',['RCC_PLLCFGR_PLLN_6',['../group___peripheral___registers___bits___definition.html#gaddfba8f0f4b9b772986a0d214dcced39',1,'stm32f407xx_matlab.h']]], - ['rcc_5fpllcfgr_5fplln_5f7_797',['RCC_PLLCFGR_PLLN_7',['../group___peripheral___registers___bits___definition.html#ga0df4b12cec2263d6acec32015035fe54',1,'stm32f407xx_matlab.h']]], - ['rcc_5fpllcfgr_5fplln_5f8_798',['RCC_PLLCFGR_PLLN_8',['../group___peripheral___registers___bits___definition.html#gaff473b6dc417ef6fa361017b2f107c06',1,'stm32f407xx_matlab.h']]], - ['rcc_5fpllcfgr_5fplln_5fmsk_799',['RCC_PLLCFGR_PLLN_Msk',['../group___peripheral___registers___bits___definition.html#gafc41ec903faa2ebee1356f88451a70be',1,'stm32f407xx_matlab.h']]], - ['rcc_5fpllcfgr_5fplln_5fpos_800',['RCC_PLLCFGR_PLLN_Pos',['../group___peripheral___registers___bits___definition.html#ga78a5913e3fc53a740fe874ece04b2d84',1,'stm32f407xx_matlab.h']]], - ['rcc_5fpllcfgr_5fpllp_801',['RCC_PLLCFGR_PLLP',['../group___peripheral___registers___bits___definition.html#ga2561745be271ee828e26de601f72162d',1,'stm32f407xx_matlab.h']]], - ['rcc_5fpllcfgr_5fpllp_5f0_802',['RCC_PLLCFGR_PLLP_0',['../group___peripheral___registers___bits___definition.html#ga46e5cb0fc1122e12425c26b5ed91bcfd',1,'stm32f407xx_matlab.h']]], - ['rcc_5fpllcfgr_5fpllp_5f1_803',['RCC_PLLCFGR_PLLP_1',['../group___peripheral___registers___bits___definition.html#gaba4ddc9eb3b629852127551eeae77f73',1,'stm32f407xx_matlab.h']]], - ['rcc_5fpllcfgr_5fpllp_5fmsk_804',['RCC_PLLCFGR_PLLP_Msk',['../group___peripheral___registers___bits___definition.html#ga944643170311f50335c87c581ee11eca',1,'stm32f407xx_matlab.h']]], - ['rcc_5fpllcfgr_5fpllp_5fpos_805',['RCC_PLLCFGR_PLLP_Pos',['../group___peripheral___registers___bits___definition.html#gaa67d9c488f8ce7cc078b2c7ca607d742',1,'stm32f407xx_matlab.h']]], - ['rcc_5fpllcfgr_5fpllq_806',['RCC_PLLCFGR_PLLQ',['../group___peripheral___registers___bits___definition.html#ga546495f69f570cb4b81d4a59054c7ed1',1,'stm32f407xx_matlab.h']]], - ['rcc_5fpllcfgr_5fpllq_5f0_807',['RCC_PLLCFGR_PLLQ_0',['../group___peripheral___registers___bits___definition.html#ga56fe140a22f66d2dd7250bb1f39ab451',1,'stm32f407xx_matlab.h']]], - ['rcc_5fpllcfgr_5fpllq_5f1_808',['RCC_PLLCFGR_PLLQ_1',['../group___peripheral___registers___bits___definition.html#ga7703def670b8ef3ec634f8f09a56ce00',1,'stm32f407xx_matlab.h']]], - ['rcc_5fpllcfgr_5fpllq_5f2_809',['RCC_PLLCFGR_PLLQ_2',['../group___peripheral___registers___bits___definition.html#ga45ab5c1d1a26d34915a53de7013f6cf6',1,'stm32f407xx_matlab.h']]], - ['rcc_5fpllcfgr_5fpllq_5f3_810',['RCC_PLLCFGR_PLLQ_3',['../group___peripheral___registers___bits___definition.html#ga182a9e6e5d5e1c63a1d20daf9b1874b5',1,'stm32f407xx_matlab.h']]], - ['rcc_5fpllcfgr_5fpllq_5fmsk_811',['RCC_PLLCFGR_PLLQ_Msk',['../group___peripheral___registers___bits___definition.html#ga61e97c300a1e833572204b270398158f',1,'stm32f407xx_matlab.h']]], - ['rcc_5fpllcfgr_5fpllq_5fpos_812',['RCC_PLLCFGR_PLLQ_Pos',['../group___peripheral___registers___bits___definition.html#gac574324eee39c3dcee75b37d7728c9ae',1,'stm32f407xx_matlab.h']]], - ['rcc_5fpllcfgr_5fpllsrc_813',['RCC_PLLCFGR_PLLSRC',['../group___peripheral___registers___bits___definition.html#ga92cb53ea81d2c47537eb217cc6659a2e',1,'stm32f407xx_matlab.h']]], - ['rcc_5fpllcfgr_5fpllsrc_5fhse_814',['RCC_PLLCFGR_PLLSRC_HSE',['../group___peripheral___registers___bits___definition.html#gae3a86c3918526efe2258ecbb34b91587',1,'stm32f407xx_matlab.h']]], - ['rcc_5fpllcfgr_5fpllsrc_5fhse_5fmsk_815',['RCC_PLLCFGR_PLLSRC_HSE_Msk',['../group___peripheral___registers___bits___definition.html#ga858f2c21bc43e423136f370f6c410909',1,'stm32f407xx_matlab.h']]], - ['rcc_5fpllcfgr_5fpllsrc_5fhse_5fpos_816',['RCC_PLLCFGR_PLLSRC_HSE_Pos',['../group___peripheral___registers___bits___definition.html#ga21e65d80de700a9c5f202f1c7c777679',1,'stm32f407xx_matlab.h']]], - ['rcc_5fpllcfgr_5fpllsrc_5fhsi_817',['RCC_PLLCFGR_PLLSRC_HSI',['../group___peripheral___registers___bits___definition.html#gadf688c4f038f29247cc0280dbdda24a7',1,'stm32f407xx_matlab.h']]], - ['rcc_5fpllcfgr_5fpllsrc_5fmsk_818',['RCC_PLLCFGR_PLLSRC_Msk',['../group___peripheral___registers___bits___definition.html#ga30516f483e85323f76dab980af3be393',1,'stm32f407xx_matlab.h']]], - ['rcc_5fpllcfgr_5fpllsrc_5fpos_819',['RCC_PLLCFGR_PLLSRC_Pos',['../group___peripheral___registers___bits___definition.html#gae44f5b0b3eaa9d6f11eac2a8b1328cd7',1,'stm32f407xx_matlab.h']]], - ['rcc_5fpllcfgr_5frst_5fvalue_820',['RCC_PLLCFGR_RST_VALUE',['../group___exported__macros.html#gab0a3c8475d96f7bb0c8a6b8a7e0c943c',1,'stm32f407xx_matlab.h']]], - ['rcc_5fplli2s_5fsupport_821',['RCC_PLLI2S_SUPPORT',['../group___peripheral___registers___bits___definition.html#gac48c0893e590b49fa8079830a0ae8abb',1,'stm32f407xx_matlab.h']]], - ['rcc_5fplli2scfgr_5fplli2sn_822',['RCC_PLLI2SCFGR_PLLI2SN',['../group___peripheral___registers___bits___definition.html#ga68db5b1d90f9b62359888ed1175a0cef',1,'stm32f407xx_matlab.h']]], - ['rcc_5fplli2scfgr_5fplli2sn_5f0_823',['RCC_PLLI2SCFGR_PLLI2SN_0',['../group___peripheral___registers___bits___definition.html#gaee6ea60de76e294b8ba23d229b2c8a1d',1,'stm32f407xx_matlab.h']]], - ['rcc_5fplli2scfgr_5fplli2sn_5f1_824',['RCC_PLLI2SCFGR_PLLI2SN_1',['../group___peripheral___registers___bits___definition.html#ga60eec842a298febfaadd7b5f79898b00',1,'stm32f407xx_matlab.h']]], - ['rcc_5fplli2scfgr_5fplli2sn_5f2_825',['RCC_PLLI2SCFGR_PLLI2SN_2',['../group___peripheral___registers___bits___definition.html#gae2be70f723d8e89b4566a9438a671f49',1,'stm32f407xx_matlab.h']]], - ['rcc_5fplli2scfgr_5fplli2sn_5f3_826',['RCC_PLLI2SCFGR_PLLI2SN_3',['../group___peripheral___registers___bits___definition.html#ga63743438e947f632c0757a6daf2838af',1,'stm32f407xx_matlab.h']]], - ['rcc_5fplli2scfgr_5fplli2sn_5f4_827',['RCC_PLLI2SCFGR_PLLI2SN_4',['../group___peripheral___registers___bits___definition.html#gae1f94003cdc00380b298b54c485ca743',1,'stm32f407xx_matlab.h']]], - ['rcc_5fplli2scfgr_5fplli2sn_5f5_828',['RCC_PLLI2SCFGR_PLLI2SN_5',['../group___peripheral___registers___bits___definition.html#ga03c368d0e6199b212e7c185663dd2aa8',1,'stm32f407xx_matlab.h']]], - ['rcc_5fplli2scfgr_5fplli2sn_5f6_829',['RCC_PLLI2SCFGR_PLLI2SN_6',['../group___peripheral___registers___bits___definition.html#ga32d9931c3638779af7042d901a01aabf',1,'stm32f407xx_matlab.h']]], - ['rcc_5fplli2scfgr_5fplli2sn_5f7_830',['RCC_PLLI2SCFGR_PLLI2SN_7',['../group___peripheral___registers___bits___definition.html#ga8dc32ee35e426332598db98b5e0b230b',1,'stm32f407xx_matlab.h']]], - ['rcc_5fplli2scfgr_5fplli2sn_5f8_831',['RCC_PLLI2SCFGR_PLLI2SN_8',['../group___peripheral___registers___bits___definition.html#ga9ec1c1bad2b7126f36b2ba26e657e84a',1,'stm32f407xx_matlab.h']]], - ['rcc_5fplli2scfgr_5fplli2sn_5fmsk_832',['RCC_PLLI2SCFGR_PLLI2SN_Msk',['../group___peripheral___registers___bits___definition.html#gafb8781000aaf194d241cee23a637e95e',1,'stm32f407xx_matlab.h']]], - ['rcc_5fplli2scfgr_5fplli2sn_5fpos_833',['RCC_PLLI2SCFGR_PLLI2SN_Pos',['../group___peripheral___registers___bits___definition.html#gab3cf5415c0debb40f8932d59677103a2',1,'stm32f407xx_matlab.h']]], - ['rcc_5fplli2scfgr_5fplli2sr_834',['RCC_PLLI2SCFGR_PLLI2SR',['../group___peripheral___registers___bits___definition.html#ga0c599fc84dcde859974ed5b334e90f50',1,'stm32f407xx_matlab.h']]], - ['rcc_5fplli2scfgr_5fplli2sr_5f0_835',['RCC_PLLI2SCFGR_PLLI2SR_0',['../group___peripheral___registers___bits___definition.html#gab2b9c8dc6b0e853ace99e16818d55d12',1,'stm32f407xx_matlab.h']]], - ['rcc_5fplli2scfgr_5fplli2sr_5f1_836',['RCC_PLLI2SCFGR_PLLI2SR_1',['../group___peripheral___registers___bits___definition.html#gabb49236fe3c41edb56f8ffb8ab505d86',1,'stm32f407xx_matlab.h']]], - ['rcc_5fplli2scfgr_5fplli2sr_5f2_837',['RCC_PLLI2SCFGR_PLLI2SR_2',['../group___peripheral___registers___bits___definition.html#ga03e58dd5ac710e271fc6ca9113b7e846',1,'stm32f407xx_matlab.h']]], - ['rcc_5fplli2scfgr_5fplli2sr_5fmsk_838',['RCC_PLLI2SCFGR_PLLI2SR_Msk',['../group___peripheral___registers___bits___definition.html#gad8ab724070f564a647a4a1ef4e46183e',1,'stm32f407xx_matlab.h']]], - ['rcc_5fplli2scfgr_5fplli2sr_5fpos_839',['RCC_PLLI2SCFGR_PLLI2SR_Pos',['../group___peripheral___registers___bits___definition.html#ga93e7478c8a17f7d07b937e180f8f13f4',1,'stm32f407xx_matlab.h']]], - ['rcc_5fplli2scfgr_5frst_5fvalue_840',['RCC_PLLI2SCFGR_RST_VALUE',['../group___exported__macros.html#gab5ca7e3fcb49274bb60c660221bbca5b',1,'stm32f407xx_matlab.h']]], - ['rcc_5fplln_5fmax_5fvalue_841',['RCC_PLLN_MAX_VALUE',['../group___exported__macros.html#ga9d6c2fd92a420bb80caf8ca2cadb6a62',1,'stm32f407xx_matlab.h']]], - ['rcc_5fplln_5fmin_5fvalue_842',['RCC_PLLN_MIN_VALUE',['../group___exported__macros.html#ga6015e60e123ddde47bb3ddfab170c5a1',1,'stm32f407xx_matlab.h']]], - ['rcc_5fpllvco_5finput_5fmax_843',['RCC_PLLVCO_INPUT_MAX',['../group___exported__macros.html#gad3fd37dbfa74739a3c698ab4755fa27e',1,'stm32f407xx_matlab.h']]], - ['rcc_5fpllvco_5finput_5fmin_844',['RCC_PLLVCO_INPUT_MIN',['../group___exported__macros.html#ga288d68c2604cea8548eccdef3873923f',1,'stm32f407xx_matlab.h']]], - ['rcc_5fpllvco_5foutput_5fmax_845',['RCC_PLLVCO_OUTPUT_MAX',['../group___exported__macros.html#gaba6ddae0375763847f8dc3e91173d714',1,'stm32f407xx_matlab.h']]], - ['rcc_5fpllvco_5foutput_5fmin_846',['RCC_PLLVCO_OUTPUT_MIN',['../group___exported__macros.html#ga85746dffdc6d015f5142d7e16489ca84',1,'stm32f407xx_matlab.h']]], - ['rcc_5fsimulator_847',['RCC_SIMULATOR',['../group___r_c_c___s_i_m_u_l_a_t_o_r.html',1,'']]], - ['rcc_5fsscgr_5fincstep_848',['RCC_SSCGR_INCSTEP',['../group___peripheral___registers___bits___definition.html#ga0f801e25eb841262467f54e7325b7806',1,'stm32f407xx_matlab.h']]], - ['rcc_5fsscgr_5fincstep_5fmsk_849',['RCC_SSCGR_INCSTEP_Msk',['../group___peripheral___registers___bits___definition.html#gaea77ceb4a2430c2d297ac24a7ad9303d',1,'stm32f407xx_matlab.h']]], - ['rcc_5fsscgr_5fincstep_5fpos_850',['RCC_SSCGR_INCSTEP_Pos',['../group___peripheral___registers___bits___definition.html#ga0dee22588439c5aa7bc9ee69cb89cce9',1,'stm32f407xx_matlab.h']]], - ['rcc_5fsscgr_5fmodper_851',['RCC_SSCGR_MODPER',['../group___peripheral___registers___bits___definition.html#gaf6fd9fde5cf03700de4c304b9c5dfb7c',1,'stm32f407xx_matlab.h']]], - ['rcc_5fsscgr_5fmodper_5fmsk_852',['RCC_SSCGR_MODPER_Msk',['../group___peripheral___registers___bits___definition.html#gaa4446b54ba7ada897a42e3311b946182',1,'stm32f407xx_matlab.h']]], - ['rcc_5fsscgr_5fmodper_5fpos_853',['RCC_SSCGR_MODPER_Pos',['../group___peripheral___registers___bits___definition.html#ga76dd9dc93a74d66a6cb8241d11fb2bf5',1,'stm32f407xx_matlab.h']]], - ['rcc_5fsscgr_5fspreadsel_854',['RCC_SSCGR_SPREADSEL',['../group___peripheral___registers___bits___definition.html#ga392689f6486224a7f19d7ad0cd195687',1,'stm32f407xx_matlab.h']]], - ['rcc_5fsscgr_5fspreadsel_5fmsk_855',['RCC_SSCGR_SPREADSEL_Msk',['../group___peripheral___registers___bits___definition.html#ga0a8dce731d21ecb6c8bcb873023b979b',1,'stm32f407xx_matlab.h']]], - ['rcc_5fsscgr_5fspreadsel_5fpos_856',['RCC_SSCGR_SPREADSEL_Pos',['../group___peripheral___registers___bits___definition.html#ga25f92667802ad9c8dc1549d65666a03f',1,'stm32f407xx_matlab.h']]], - ['rcc_5fsscgr_5fsscgen_857',['RCC_SSCGR_SSCGEN',['../group___peripheral___registers___bits___definition.html#ga8885c04bcb786b89e26f066f4ccf06e0',1,'stm32f407xx_matlab.h']]], - ['rcc_5fsscgr_5fsscgen_5fmsk_858',['RCC_SSCGR_SSCGEN_Msk',['../group___peripheral___registers___bits___definition.html#ga77656e179e5741014ea95703f65a4f99',1,'stm32f407xx_matlab.h']]], - ['rcc_5fsscgr_5fsscgen_5fpos_859',['RCC_SSCGR_SSCGEN_Pos',['../group___peripheral___registers___bits___definition.html#gae934eed92c2081acbeee062e1932943d',1,'stm32f407xx_matlab.h']]], - ['rcc_5ftypedef_860',['RCC_TypeDef',['../struct_r_c_c___type_def.html',1,'']]], - ['rcr_861',['RCR',['../group___c_m_s_i_s___device.html#gaa1b1b7107fcf35abe39d20f5dfc230ee',1,'TIM_TypeDef']]], - ['rdhr_862',['RDHR',['../group___c_m_s_i_s___device.html#ga7f11f42ba9d3bc5cd4a4f5ea0214608e',1,'CAN_FIFOMailBox_TypeDef']]], - ['rdlr_863',['RDLR',['../group___c_m_s_i_s___device.html#gae1c569688eedd49219cd505b9c22121b',1,'CAN_FIFOMailBox_TypeDef']]], - ['rdtr_864',['RDTR',['../group___c_m_s_i_s___device.html#ga9563d8a88d0db403b8357331bea83a2e',1,'CAN_FIFOMailBox_TypeDef']]], - ['read_5fbit_865',['READ_BIT',['../group___exported__macro.html#ga822bb1bb9710d5f2fa6396b84e583c33',1,'stm32f4xx.h']]], - ['read_5freg_866',['READ_REG',['../group___exported__macro.html#gae7f188a4d26c9e713a48414783421071',1,'stm32f4xx.h']]], - ['readme_2emd_867',['README.md',['../_r_e_a_d_m_e_8md.html',1,'']]], - ['reference_868',['Functions and Instructions Reference',['../group___c_m_s_i_s___core___function_interface.html',1,'']]], - ['register_20bit_20field_20macros_869',['Core register bit field macros',['../group___c_m_s_i_s__core__bitfield.html',1,'']]], - ['registers_870',['Status and Control Registers',['../group___c_m_s_i_s___c_o_r_e.html',1,'']]], - ['registers_20coredebug_871',['Core Debug Registers (CoreDebug)',['../group___c_m_s_i_s___core_debug.html',1,'']]], - ['reload_872',['RELOAD',['../struct_t_i_m___sim.html#a1798863b8849972c8e0cf75abbbd116b',1,'TIM_Sim']]], - ['reserved_873',['RESERVED',['../group___c_m_s_i_s___device.html#gafaf27b66c1edc60064db3fa6e693fb59',1,'SYSCFG_TypeDef']]], - ['reserved_874',['Reserved',['../group___c_m_s_i_s___device.html#gae930d94b6a3272fed7c42c1a02929924',1,'USB_OTG_HostChannelTypeDef']]], - ['reserved0_875',['RESERVED0',['../group___c_m_s_i_s__core___debug_functions.html#gafd37041a76931e7c95a4970aa0170ad0',1,'NVIC_Type::RESERVED0'],['../group___c_m_s_i_s__core___debug_functions.html#ga9361cfd01123913b78dd5d0dc8301bfd',1,'SCB_Type::RESERVED0'],['../group___c_m_s_i_s__core___debug_functions.html#ga37ff1c5ca91c4a545bde7f8a3301a563',1,'SCnSCB_Type::RESERVED0'],['../group___c_m_s_i_s__core___debug_functions.html#gaf3c010726422d9433474d4315fe1bbcd',1,'ITM_Type::RESERVED0'],['../group___c_m_s_i_s__core___debug_functions.html#ga37ff1c5ca91c4a545bde7f8a3301a563',1,'DWT_Type::RESERVED0'],['../group___c_m_s_i_s__core___debug_functions.html#gac9b95db444f893c84f01e49a91d22651',1,'TPI_Type::RESERVED0'],['../group___c_m_s_i_s__core___debug_functions.html#ga37ff1c5ca91c4a545bde7f8a3301a563',1,'FPU_Type::RESERVED0'],['../group___c_m_s_i_s___device.html#gaae28ab86a4ae57ed057ed1ea89a6d34b',1,'CAN_TypeDef::RESERVED0'],['../group___c_m_s_i_s___device.html#gaa7d2bd5481ee985778c410a7e5826b71',1,'CRC_TypeDef::RESERVED0'],['../group___c_m_s_i_s___device.html#ga8be676577db129a84a9a2689519a8502',1,'ETH_TypeDef::RESERVED0'],['../group___c_m_s_i_s___device.html#gaf86c61a5d38a4fc9cef942a12744486b',1,'FSMC_Bank2_3_TypeDef::RESERVED0'],['../group___c_m_s_i_s___device.html#gaf86c61a5d38a4fc9cef942a12744486b',1,'RCC_TypeDef::RESERVED0'],['../group___c_m_s_i_s___device.html#ga8be676577db129a84a9a2689519a8502',1,'SDIO_TypeDef::RESERVED0']]], - ['reserved04_876',['Reserved04',['../group___c_m_s_i_s___device.html#gacfe7efaa61db86840767dff6d73f8695',1,'USB_OTG_INEndpointTypeDef::Reserved04'],['../group___c_m_s_i_s___device.html#gacfe7efaa61db86840767dff6d73f8695',1,'USB_OTG_OUTEndpointTypeDef::Reserved04']]], - ['reserved0c_877',['Reserved0C',['../group___c_m_s_i_s___device.html#ga1bcc039378b4ed4ac1261a0a758c3d1d',1,'USB_OTG_DeviceTypeDef::Reserved0C'],['../group___c_m_s_i_s___device.html#ga1bcc039378b4ed4ac1261a0a758c3d1d',1,'USB_OTG_INEndpointTypeDef::Reserved0C'],['../group___c_m_s_i_s___device.html#ga1bcc039378b4ed4ac1261a0a758c3d1d',1,'USB_OTG_OUTEndpointTypeDef::Reserved0C']]], - ['reserved1_878',['RESERVED1',['../group___c_m_s_i_s__core___debug_functions.html#ga696e12d22e5f6693aeab2859440e5d58',1,'ITM_Type::RESERVED1'],['../group___c_m_s_i_s__core___debug_functions.html#ga22597a52981a247dfd72fc83fb1a54a3',1,'DWT_Type::RESERVED1'],['../group___c_m_s_i_s__core___debug_functions.html#gad6c93f857de1c48aa3a21aabb47e6c08',1,'TPI_Type::RESERVED1'],['../group___c_m_s_i_s___device.html#ga4bb07a7828fbd5fe86f6a5a3545c177d',1,'CAN_TypeDef::RESERVED1'],['../group___c_m_s_i_s___device.html#ga8249a3955aace28d92109b391311eb30',1,'CRC_TypeDef::RESERVED1'],['../group___c_m_s_i_s___device.html#gac4ac04e673b5b8320d53f7b0947db902',1,'ETH_TypeDef::RESERVED1'],['../group___c_m_s_i_s___device.html#gac4ac04e673b5b8320d53f7b0947db902',1,'FSMC_Bank2_3_TypeDef::RESERVED1'],['../group___c_m_s_i_s___device.html#ga28d88d9a08aab1adbebea61c42ef901e',1,'RCC_TypeDef::RESERVED1'],['../group___c_m_s_i_s___device.html#ga2d531df35272b1f3d787e5726ed5c52c',1,'SDIO_TypeDef::RESERVED1']]], - ['reserved10_879',['RESERVED10',['../group___c_m_s_i_s___device.html#ga57d552323802fb4dd0bac95a02e814f0',1,'ETH_TypeDef']]], - ['reserved18_880',['Reserved18',['../group___c_m_s_i_s___device.html#ga716e172ed03ae049eb501ad83207b4ed',1,'USB_OTG_INEndpointTypeDef::Reserved18'],['../group___c_m_s_i_s___device.html#ga78fbe0aab076cfbf9df51dd6f67eaf82',1,'USB_OTG_OUTEndpointTypeDef::Reserved18']]], - ['reserved2_881',['RESERVED2',['../group___c_m_s_i_s__core___debug_functions.html#gaf42026bc68849adde0d2972b717e2c63',1,'NVIC_Type::RESERVED2'],['../group___c_m_s_i_s__core___debug_functions.html#ga5d1c1ef815721bb6591f5ab016e2262b',1,'ITM_Type::RESERVED2'],['../group___c_m_s_i_s__core___debug_functions.html#gafc320edff930c9d2db6be3af044bff2a',1,'DWT_Type::RESERVED2'],['../group___c_m_s_i_s__core___debug_functions.html#gae33b1ff4c22f5f0743b1c76ebd6ceb7f',1,'TPI_Type::RESERVED2'],['../group___c_m_s_i_s___device.html#ga4c9b972a304c0e08ca27cbe57627c496',1,'CAN_TypeDef::RESERVED2'],['../group___c_m_s_i_s___device.html#ga1cf0d9299ef58b327f4e3d03da1c1aaf',1,'ETH_TypeDef::RESERVED2'],['../group___c_m_s_i_s___device.html#ga4c9b972a304c0e08ca27cbe57627c496',1,'FSMC_Bank2_3_TypeDef::RESERVED2'],['../group___c_m_s_i_s___device.html#ga4c9b972a304c0e08ca27cbe57627c496',1,'RCC_TypeDef::RESERVED2']]], - ['reserved20_882',['Reserved20',['../group___c_m_s_i_s___device.html#ga17d14644b0d28710722b1c2c0149e472',1,'USB_OTG_DeviceTypeDef']]], - ['reserved3_883',['RESERVED3',['../group___c_m_s_i_s__core___debug_functions.html#ga4a73c83f30b388bdeb158c9926d1f038',1,'NVIC_Type::RESERVED3'],['../group___c_m_s_i_s__core___debug_functions.html#ga8275b6f047f2640021fbef1f766e9d8f',1,'ITM_Type::RESERVED3'],['../group___c_m_s_i_s__core___debug_functions.html#gaf2f12e10edc6d605022706316e417534',1,'TPI_Type::RESERVED3'],['../group___c_m_s_i_s___device.html#gaf2b40c5e36a5e861490988275499e158',1,'CAN_TypeDef::RESERVED3'],['../group___c_m_s_i_s___device.html#gaf6446adf612691721c62fc68aff4fe39',1,'ETH_TypeDef::RESERVED3'],['../group___c_m_s_i_s___device.html#gaf2b40c5e36a5e861490988275499e158',1,'FSMC_Bank2_3_TypeDef::RESERVED3'],['../group___c_m_s_i_s___device.html#gab6f0f833dbe064708de75d95c68c32fd',1,'RCC_TypeDef::RESERVED3']]], - ['reserved30_884',['Reserved30',['../group___c_m_s_i_s___device.html#ga577856159d58c037352ee10609b2a99c',1,'USB_OTG_GlobalTypeDef']]], - ['reserved4_885',['RESERVED4',['../group___c_m_s_i_s__core___debug_functions.html#gacc89b6183e50c95d19287044abda0707',1,'NVIC_Type::RESERVED4'],['../group___c_m_s_i_s__core___debug_functions.html#gaab51ad96474c7f0bc4f8320a03dee762',1,'ITM_Type::RESERVED4'],['../group___c_m_s_i_s__core___debug_functions.html#ga85bb9b58f27f0189553adc1da97771e5',1,'TPI_Type::RESERVED4'],['../group___c_m_s_i_s___device.html#gac0018930ee9f18afda25b695b9a4ec16',1,'CAN_TypeDef::RESERVED4'],['../group___c_m_s_i_s___device.html#gabca175d3acfbc2a0806452fd57ea5fc4',1,'ETH_TypeDef::RESERVED4'],['../group___c_m_s_i_s___device.html#gac0018930ee9f18afda25b695b9a4ec16',1,'RCC_TypeDef::RESERVED4']]], - ['reserved40_886',['Reserved40',['../group___c_m_s_i_s___device.html#gaea9d4b7970a55a4c87d8482ba1ed1b8b',1,'USB_OTG_GlobalTypeDef::Reserved40'],['../group___c_m_s_i_s___device.html#ga9e0c029846e94bf08ac8edb35b30ecb2',1,'USB_OTG_DeviceTypeDef::Reserved40']]], - ['reserved40c_887',['Reserved40C',['../group___c_m_s_i_s___device.html#gaf66e42cdb83dc2eb156dfbbf42890f79',1,'USB_OTG_HostTypeDef']]], - ['reserved44_888',['Reserved44',['../group___c_m_s_i_s___device.html#ga8b1e044bd34b12074334270cfd18c931',1,'USB_OTG_DeviceTypeDef']]], - ['reserved5_889',['RESERVED5',['../group___c_m_s_i_s__core___debug_functions.html#ga91ec3c12a77345411c4f8caca5ef4e6c',1,'NVIC_Type::RESERVED5'],['../group___c_m_s_i_s__core___debug_functions.html#ga2b0ee1fd79c3162a6bf47581ed42b491',1,'ITM_Type::RESERVED5'],['../group___c_m_s_i_s__core___debug_functions.html#ga0be075c11181d8a44c3a019b8690e829',1,'TPI_Type::RESERVED5'],['../group___c_m_s_i_s___device.html#ga269f31b91d0f38a48061b76ecc346f55',1,'CAN_TypeDef::RESERVED5'],['../group___c_m_s_i_s___device.html#ga3c1a316c73bb5f0eae7fbe66177cbca6',1,'ETH_TypeDef::RESERVED5'],['../group___c_m_s_i_s___device.html#gac0eb05794aeee3b4ed69c8fe54c9be3b',1,'RCC_TypeDef::RESERVED5']]], - ['reserved6_890',['RESERVED6',['../group___c_m_s_i_s___device.html#ga7e9a9bba62d1d98e3058b29a892b3877',1,'ETH_TypeDef::RESERVED6'],['../group___c_m_s_i_s___device.html#ga10da398d74a1f88d5b42bd40718d9447',1,'RCC_TypeDef::RESERVED6']]], - ['reserved7_891',['RESERVED7',['../group___c_m_s_i_s__core___debug_functions.html#gaa0279d9a6b589b11dab6e3d22f87bac8',1,'TPI_Type::RESERVED7'],['../group___c_m_s_i_s___device.html#gab1b7eacec3f164ed04001e9c806f73f9',1,'ETH_TypeDef::RESERVED7'],['../group___c_m_s_i_s___device.html#ga6be3d40baea405ecaf6b38462357dac0',1,'RTC_TypeDef::RESERVED7']]], - ['reserved8_892',['RESERVED8',['../group___c_m_s_i_s___device.html#ga2e60bc2eefc18398fb2459d1b44453e5',1,'ETH_TypeDef']]], - ['reserved9_893',['Reserved9',['../group___c_m_s_i_s___device.html#ga5dc05e38e6d591cd88f820b7a0b3f727',1,'USB_OTG_DeviceTypeDef']]], - ['reserved9_894',['RESERVED9',['../group___c_m_s_i_s___device.html#gae62fffd7d8f9f69b15edacdea4ba27f2',1,'ETH_TypeDef']]], - ['reset_895',['RESET',['../group___exported__types.html#gga89136caac2e14c55151f527ac02daaffa589b7d94a3d91d145720e2fed0eb3a05',1,'stm32f4xx.h']]], - ['resp1_896',['RESP1',['../group___c_m_s_i_s___device.html#ga7da778413f6db1f83ae25caed03382d4',1,'SDIO_TypeDef']]], - ['resp2_897',['RESP2',['../group___c_m_s_i_s___device.html#ga44614d7422faffd14af83884e76b2d3e',1,'SDIO_TypeDef']]], - ['resp3_898',['RESP3',['../group___c_m_s_i_s___device.html#ga270ee3c6e9f87e5851422ae0ef255fd4',1,'SDIO_TypeDef']]], - ['resp4_899',['RESP4',['../group___c_m_s_i_s___device.html#gaa74faef460a0c655439bcf20caac1653',1,'SDIO_TypeDef']]], - ['respcmd_900',['RESPCMD',['../group___c_m_s_i_s___device.html#ga195d1a8a6ae4f6072f4e4b62298051fe',1,'SDIO_TypeDef']]], - ['rf0r_901',['RF0R',['../group___c_m_s_i_s___device.html#gaccf4141cee239380d0ad4634ee21dbf6',1,'CAN_TypeDef']]], - ['rf1r_902',['RF1R',['../group___c_m_s_i_s___device.html#ga02b589bb589df4f39e549dca4d5abb08',1,'CAN_TypeDef']]], - ['rir_903',['RIR',['../group___c_m_s_i_s___device.html#ga0acc8eb90b17bef5b9e03c7ddaacfb0b',1,'CAN_FIFOMailBox_TypeDef']]], - ['risr_904',['RISR',['../group___c_m_s_i_s___device.html#gaa196fddf0ba7d6e3ce29bdb04eb38b94',1,'DCMI_TypeDef']]], - ['rlr_905',['RLR',['../group___c_m_s_i_s___device.html#ga7015e1046dbd3ea8783b33dc11a69e52',1,'IWDG_TypeDef']]], - ['rng_906',['rng',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#gae5244ff1d33b8f1c69abb81fda62b538',1,'stm32f4xx_periph_registers.c']]], - ['rng_907',['RNG',['../group___peripheral__declaration.html#ga5b0885b8b55bbc13691092b704d9309f',1,'stm32f407xx_matlab.h']]], - ['rng_5fbase_908',['RNG_BASE',['../group___peripheral__memory__map.html#gab92662976cfe62457141e5b4f83d541c',1,'stm32f407xx_matlab.h']]], - ['rng_5fcr_5fie_909',['RNG_CR_IE',['../group___peripheral___registers___bits___definition.html#ga27424b682bcee7fff22f92a2dbcea57a',1,'stm32f407xx_matlab.h']]], - ['rng_5fcr_5fie_5fmsk_910',['RNG_CR_IE_Msk',['../group___peripheral___registers___bits___definition.html#ga8253017bd1f0d7652f107266ffb0297b',1,'stm32f407xx_matlab.h']]], - ['rng_5fcr_5fie_5fpos_911',['RNG_CR_IE_Pos',['../group___peripheral___registers___bits___definition.html#ga8d1a529728903ae8659aa26f869f6537',1,'stm32f407xx_matlab.h']]], - ['rng_5fcr_5frngen_912',['RNG_CR_RNGEN',['../group___peripheral___registers___bits___definition.html#ga6ee81827bb1d78e84e78a74449c8d56a',1,'stm32f407xx_matlab.h']]], - ['rng_5fcr_5frngen_5fmsk_913',['RNG_CR_RNGEN_Msk',['../group___peripheral___registers___bits___definition.html#gaeee66d4dd5c33fa16a98b001dd63bd73',1,'stm32f407xx_matlab.h']]], - ['rng_5fcr_5frngen_5fpos_914',['RNG_CR_RNGEN_Pos',['../group___peripheral___registers___bits___definition.html#gaf2013ef5a17240897df5b7bf00b7b290',1,'stm32f407xx_matlab.h']]], - ['rng_5firqn_915',['RNG_IRQn',['../group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a90c4647e57cff99fac635c532802c4b5',1,'stm32f407xx_matlab.h']]], - ['rng_5fsr_5fcecs_916',['RNG_SR_CECS',['../group___peripheral___registers___bits___definition.html#ga4bb49d327474c3c61877bb20290f51d0',1,'stm32f407xx_matlab.h']]], - ['rng_5fsr_5fcecs_5fmsk_917',['RNG_SR_CECS_Msk',['../group___peripheral___registers___bits___definition.html#ga699d24eb133814c5be46fe6e588cc093',1,'stm32f407xx_matlab.h']]], - ['rng_5fsr_5fcecs_5fpos_918',['RNG_SR_CECS_Pos',['../group___peripheral___registers___bits___definition.html#ga164b5050473dff67a5cd6ca400bb5a89',1,'stm32f407xx_matlab.h']]], - ['rng_5fsr_5fceis_919',['RNG_SR_CEIS',['../group___peripheral___registers___bits___definition.html#ga3b89a08bcc8a7a6078bd9f5f2f34bb53',1,'stm32f407xx_matlab.h']]], - ['rng_5fsr_5fceis_5fmsk_920',['RNG_SR_CEIS_Msk',['../group___peripheral___registers___bits___definition.html#ga3efcca0c0381982a8044d09aaa6b6df9',1,'stm32f407xx_matlab.h']]], - ['rng_5fsr_5fceis_5fpos_921',['RNG_SR_CEIS_Pos',['../group___peripheral___registers___bits___definition.html#ga341c152f61c352b96fb0c3c245e3d958',1,'stm32f407xx_matlab.h']]], - ['rng_5fsr_5fdrdy_922',['RNG_SR_DRDY',['../group___peripheral___registers___bits___definition.html#ga54434ed74bdb00fd0f13422d3e85a2fc',1,'stm32f407xx_matlab.h']]], - ['rng_5fsr_5fdrdy_5fmsk_923',['RNG_SR_DRDY_Msk',['../group___peripheral___registers___bits___definition.html#gafd19bcfa8894faf2ac5f57d287f00a8b',1,'stm32f407xx_matlab.h']]], - ['rng_5fsr_5fdrdy_5fpos_924',['RNG_SR_DRDY_Pos',['../group___peripheral___registers___bits___definition.html#ga17cb7add2587efeea18a208c76d73727',1,'stm32f407xx_matlab.h']]], - ['rng_5fsr_5fsecs_925',['RNG_SR_SECS',['../group___peripheral___registers___bits___definition.html#ga5562bc13afe295893dc3997a4917fee2',1,'stm32f407xx_matlab.h']]], - ['rng_5fsr_5fsecs_5fmsk_926',['RNG_SR_SECS_Msk',['../group___peripheral___registers___bits___definition.html#ga8a312837097b7b3c2528e17a2cfc5f7d',1,'stm32f407xx_matlab.h']]], - ['rng_5fsr_5fsecs_5fpos_927',['RNG_SR_SECS_Pos',['../group___peripheral___registers___bits___definition.html#ga51e0238194c400f9c6ac0b34826e55eb',1,'stm32f407xx_matlab.h']]], - ['rng_5fsr_5fseis_928',['RNG_SR_SEIS',['../group___peripheral___registers___bits___definition.html#gaa6b0e11930f20484f0d0aca79959d9b2',1,'stm32f407xx_matlab.h']]], - ['rng_5fsr_5fseis_5fmsk_929',['RNG_SR_SEIS_Msk',['../group___peripheral___registers___bits___definition.html#ga1d78e80e064c7746b98ed89304aab367',1,'stm32f407xx_matlab.h']]], - ['rng_5fsr_5fseis_5fpos_930',['RNG_SR_SEIS_Pos',['../group___peripheral___registers___bits___definition.html#gaecf22f4de968dc9aa29d55760ebdb980',1,'stm32f407xx_matlab.h']]], - ['rng_5ftypedef_931',['RNG_TypeDef',['../struct_r_n_g___type_def.html',1,'']]], - ['rserved1_932',['RSERVED1',['../group___c_m_s_i_s__core___debug_functions.html#ga1f2355d51336450dbe986c766006aa8a',1,'NVIC_Type']]], - ['rtc_933',['RTC',['../group___peripheral__declaration.html#ga5359a088f5d8b20ce74d920e46059304',1,'stm32f407xx_matlab.h']]], - ['rtc_934',['rtc',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga423742450422a8873970b076a7e25028',1,'stm32f4xx_periph_registers.c']]], - ['rtc_5faf2_5fsupport_935',['RTC_AF2_SUPPORT',['../group___peripheral___registers___bits___definition.html#ga8b082d5bb4b8d9801fc7370e813b1b3c',1,'stm32f407xx_matlab.h']]], - ['rtc_5falarm_5firqn_936',['RTC_Alarm_IRQn',['../group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8afe09d6563a21a1540f658163a76a3b37',1,'stm32f407xx_matlab.h']]], - ['rtc_5falrmar_5fdt_937',['RTC_ALRMAR_DT',['../group___peripheral___registers___bits___definition.html#ga934ea7910b5f5988f6c46ae4703dc29b',1,'stm32f407xx_matlab.h']]], - ['rtc_5falrmar_5fdt_5f0_938',['RTC_ALRMAR_DT_0',['../group___peripheral___registers___bits___definition.html#ga0cb880cece843ba5314120abcf14e9fc',1,'stm32f407xx_matlab.h']]], - ['rtc_5falrmar_5fdt_5f1_939',['RTC_ALRMAR_DT_1',['../group___peripheral___registers___bits___definition.html#ga6e2e76ce2645d0c9d2587d4172edcd58',1,'stm32f407xx_matlab.h']]], - ['rtc_5falrmar_5fdt_5fmsk_940',['RTC_ALRMAR_DT_Msk',['../group___peripheral___registers___bits___definition.html#ga5b864018e7de62c954d6fff34bde926f',1,'stm32f407xx_matlab.h']]], - ['rtc_5falrmar_5fdt_5fpos_941',['RTC_ALRMAR_DT_Pos',['../group___peripheral___registers___bits___definition.html#gab4d605cd74901b7544c8a6cc9f446436',1,'stm32f407xx_matlab.h']]], - ['rtc_5falrmar_5fdu_942',['RTC_ALRMAR_DU',['../group___peripheral___registers___bits___definition.html#ga784589946bdf3ca0d675cc22d9bafbbf',1,'stm32f407xx_matlab.h']]], - ['rtc_5falrmar_5fdu_5f0_943',['RTC_ALRMAR_DU_0',['../group___peripheral___registers___bits___definition.html#ga687a85ed4e7623bdb60196f706ab62e9',1,'stm32f407xx_matlab.h']]], - ['rtc_5falrmar_5fdu_5f1_944',['RTC_ALRMAR_DU_1',['../group___peripheral___registers___bits___definition.html#ga8d2ec65de047fdece20083f030cc6cfd',1,'stm32f407xx_matlab.h']]], - ['rtc_5falrmar_5fdu_5f2_945',['RTC_ALRMAR_DU_2',['../group___peripheral___registers___bits___definition.html#gaeb0050d5e8d64e4f684e325446ea173a',1,'stm32f407xx_matlab.h']]], - ['rtc_5falrmar_5fdu_5f3_946',['RTC_ALRMAR_DU_3',['../group___peripheral___registers___bits___definition.html#ga79a55db963d0707fc0ae14bffc51c297',1,'stm32f407xx_matlab.h']]], - ['rtc_5falrmar_5fdu_5fmsk_947',['RTC_ALRMAR_DU_Msk',['../group___peripheral___registers___bits___definition.html#ga6f818fa2666247ad93611752020097b1',1,'stm32f407xx_matlab.h']]], - ['rtc_5falrmar_5fdu_5fpos_948',['RTC_ALRMAR_DU_Pos',['../group___peripheral___registers___bits___definition.html#gaab5a8a73b82a0e8c16f7f5dc35166622',1,'stm32f407xx_matlab.h']]], - ['rtc_5falrmar_5fht_949',['RTC_ALRMAR_HT',['../group___peripheral___registers___bits___definition.html#ga55bc04190e9eaa916144fa2d1777cbfb',1,'stm32f407xx_matlab.h']]], - ['rtc_5falrmar_5fht_5f0_950',['RTC_ALRMAR_HT_0',['../group___peripheral___registers___bits___definition.html#ga4165b904cdf6bdf4ed6c892d73953453',1,'stm32f407xx_matlab.h']]], - ['rtc_5falrmar_5fht_5f1_951',['RTC_ALRMAR_HT_1',['../group___peripheral___registers___bits___definition.html#gab50f98903ad0183c52c40375d45d4d77',1,'stm32f407xx_matlab.h']]], - ['rtc_5falrmar_5fht_5fmsk_952',['RTC_ALRMAR_HT_Msk',['../group___peripheral___registers___bits___definition.html#gacfbc262cd63d3a1c5cdf4937cc57ec37',1,'stm32f407xx_matlab.h']]], - ['rtc_5falrmar_5fht_5fpos_953',['RTC_ALRMAR_HT_Pos',['../group___peripheral___registers___bits___definition.html#gadeb1eb233c192d56b4a4f106b3fb4be2',1,'stm32f407xx_matlab.h']]], - ['rtc_5falrmar_5fhu_954',['RTC_ALRMAR_HU',['../group___peripheral___registers___bits___definition.html#ga491fda42cfad244596737347fe157142',1,'stm32f407xx_matlab.h']]], - ['rtc_5falrmar_5fhu_5f0_955',['RTC_ALRMAR_HU_0',['../group___peripheral___registers___bits___definition.html#ga756c2c137f6d1f89bba95347245b014c',1,'stm32f407xx_matlab.h']]], - ['rtc_5falrmar_5fhu_5f1_956',['RTC_ALRMAR_HU_1',['../group___peripheral___registers___bits___definition.html#ga2068b4116fca73a63b1c98f51902acef',1,'stm32f407xx_matlab.h']]], - ['rtc_5falrmar_5fhu_5f2_957',['RTC_ALRMAR_HU_2',['../group___peripheral___registers___bits___definition.html#gab7642e83ff425a1fe2695d1100ce7c35',1,'stm32f407xx_matlab.h']]], - ['rtc_5falrmar_5fhu_5f3_958',['RTC_ALRMAR_HU_3',['../group___peripheral___registers___bits___definition.html#ga9f516916142b3ea6110619e8dc600d2a',1,'stm32f407xx_matlab.h']]], - ['rtc_5falrmar_5fhu_5fmsk_959',['RTC_ALRMAR_HU_Msk',['../group___peripheral___registers___bits___definition.html#ga0d3da70f04ca3c7c2f90ee0d0d3c9201',1,'stm32f407xx_matlab.h']]], - ['rtc_5falrmar_5fhu_5fpos_960',['RTC_ALRMAR_HU_Pos',['../group___peripheral___registers___bits___definition.html#ga914c62bbd3ce817fd1d6f871ed894222',1,'stm32f407xx_matlab.h']]], - ['rtc_5falrmar_5fmnt_961',['RTC_ALRMAR_MNT',['../group___peripheral___registers___bits___definition.html#ga02edb2d87b7fe9936a0cffa96d4a7297',1,'stm32f407xx_matlab.h']]], - ['rtc_5falrmar_5fmnt_5f0_962',['RTC_ALRMAR_MNT_0',['../group___peripheral___registers___bits___definition.html#ga0dab36fbc475b7ec4442020f159601c6',1,'stm32f407xx_matlab.h']]], - ['rtc_5falrmar_5fmnt_5f1_963',['RTC_ALRMAR_MNT_1',['../group___peripheral___registers___bits___definition.html#ga6782f11cc7f8edf401dec2ff436d7968',1,'stm32f407xx_matlab.h']]], - ['rtc_5falrmar_5fmnt_5f2_964',['RTC_ALRMAR_MNT_2',['../group___peripheral___registers___bits___definition.html#gaf766f39637efe114b38a1aceb352328d',1,'stm32f407xx_matlab.h']]], - ['rtc_5falrmar_5fmnt_5fmsk_965',['RTC_ALRMAR_MNT_Msk',['../group___peripheral___registers___bits___definition.html#gac320cc91348b22f3e5c0d6106594c09e',1,'stm32f407xx_matlab.h']]], - ['rtc_5falrmar_5fmnt_5fpos_966',['RTC_ALRMAR_MNT_Pos',['../group___peripheral___registers___bits___definition.html#gaee274022f516021cba28dede0ff60450',1,'stm32f407xx_matlab.h']]], - ['rtc_5falrmar_5fmnu_967',['RTC_ALRMAR_MNU',['../group___peripheral___registers___bits___definition.html#ga22d67ff770aa27509d79afde1865c845',1,'stm32f407xx_matlab.h']]], - ['rtc_5falrmar_5fmnu_5f0_968',['RTC_ALRMAR_MNU_0',['../group___peripheral___registers___bits___definition.html#gaeb5ead84647f92b0d1efcf8decb0dd8f',1,'stm32f407xx_matlab.h']]], - ['rtc_5falrmar_5fmnu_5f1_969',['RTC_ALRMAR_MNU_1',['../group___peripheral___registers___bits___definition.html#ga656311cb5632dbc9b4fb5dd2288a6e66',1,'stm32f407xx_matlab.h']]], - ['rtc_5falrmar_5fmnu_5f2_970',['RTC_ALRMAR_MNU_2',['../group___peripheral___registers___bits___definition.html#gadc164d7ff70842858281cfaff5f29374',1,'stm32f407xx_matlab.h']]], - ['rtc_5falrmar_5fmnu_5f3_971',['RTC_ALRMAR_MNU_3',['../group___peripheral___registers___bits___definition.html#ga4e1199b4140613e8a1dbe283dd89c772',1,'stm32f407xx_matlab.h']]], - ['rtc_5falrmar_5fmnu_5fmsk_972',['RTC_ALRMAR_MNU_Msk',['../group___peripheral___registers___bits___definition.html#gac05e67cdb4da1882dd5b8f5a8fe51bb2',1,'stm32f407xx_matlab.h']]], - ['rtc_5falrmar_5fmnu_5fpos_973',['RTC_ALRMAR_MNU_Pos',['../group___peripheral___registers___bits___definition.html#gac4fd9dea59596ad989af2bce818b1b93',1,'stm32f407xx_matlab.h']]], - ['rtc_5falrmar_5fmsk1_974',['RTC_ALRMAR_MSK1',['../group___peripheral___registers___bits___definition.html#ga8862250866a358ff3095852f45a160c1',1,'stm32f407xx_matlab.h']]], - ['rtc_5falrmar_5fmsk1_5fmsk_975',['RTC_ALRMAR_MSK1_Msk',['../group___peripheral___registers___bits___definition.html#ga838b33a3595df6fe68152bb31f812beb',1,'stm32f407xx_matlab.h']]], - ['rtc_5falrmar_5fmsk1_5fpos_976',['RTC_ALRMAR_MSK1_Pos',['../group___peripheral___registers___bits___definition.html#gacbad0bb69a65557c15042154b66eab52',1,'stm32f407xx_matlab.h']]], - ['rtc_5falrmar_5fmsk2_977',['RTC_ALRMAR_MSK2',['../group___peripheral___registers___bits___definition.html#ga478d62d55a42779c558e9ba16aec74cc',1,'stm32f407xx_matlab.h']]], - ['rtc_5falrmar_5fmsk2_5fmsk_978',['RTC_ALRMAR_MSK2_Msk',['../group___peripheral___registers___bits___definition.html#gabe0fda62acb0b820b859291e4b45e409',1,'stm32f407xx_matlab.h']]], - ['rtc_5falrmar_5fmsk2_5fpos_979',['RTC_ALRMAR_MSK2_Pos',['../group___peripheral___registers___bits___definition.html#gae87ea1c4a907654aa4565047647afa30',1,'stm32f407xx_matlab.h']]], - ['rtc_5falrmar_5fmsk3_980',['RTC_ALRMAR_MSK3',['../group___peripheral___registers___bits___definition.html#ga337fba397cab4beb204f4f6e6ddc4bf3',1,'stm32f407xx_matlab.h']]], - ['rtc_5falrmar_5fmsk3_5fmsk_981',['RTC_ALRMAR_MSK3_Msk',['../group___peripheral___registers___bits___definition.html#ga9b72eca3af2788a6df2aab8efdf48c7e',1,'stm32f407xx_matlab.h']]], - ['rtc_5falrmar_5fmsk3_5fpos_982',['RTC_ALRMAR_MSK3_Pos',['../group___peripheral___registers___bits___definition.html#ga4744abec80afe01487c6133d9325f47b',1,'stm32f407xx_matlab.h']]], - ['rtc_5falrmar_5fmsk4_983',['RTC_ALRMAR_MSK4',['../group___peripheral___registers___bits___definition.html#ga8ed557e4451ffd3e869bb9ca393d47f9',1,'stm32f407xx_matlab.h']]], - ['rtc_5falrmar_5fmsk4_5fmsk_984',['RTC_ALRMAR_MSK4_Msk',['../group___peripheral___registers___bits___definition.html#ga4ade8f686276ed4761f3741cd928b500',1,'stm32f407xx_matlab.h']]], - ['rtc_5falrmar_5fmsk4_5fpos_985',['RTC_ALRMAR_MSK4_Pos',['../group___peripheral___registers___bits___definition.html#gaf4c443ed6c81b3ce75dd5e8dd97939fb',1,'stm32f407xx_matlab.h']]], - ['rtc_5falrmar_5fpm_986',['RTC_ALRMAR_PM',['../group___peripheral___registers___bits___definition.html#gaab68dc30427951b19aecf399b0ae2900',1,'stm32f407xx_matlab.h']]], - ['rtc_5falrmar_5fpm_5fmsk_987',['RTC_ALRMAR_PM_Msk',['../group___peripheral___registers___bits___definition.html#ga1ed4ff622a2ac83edfaadc596995c61a',1,'stm32f407xx_matlab.h']]], - ['rtc_5falrmar_5fpm_5fpos_988',['RTC_ALRMAR_PM_Pos',['../group___peripheral___registers___bits___definition.html#ga85bfa4c2296c553269373a411323b21f',1,'stm32f407xx_matlab.h']]], - ['rtc_5falrmar_5fst_989',['RTC_ALRMAR_ST',['../group___peripheral___registers___bits___definition.html#ga0b623884457edb89f48a2a100aff183a',1,'stm32f407xx_matlab.h']]], - ['rtc_5falrmar_5fst_5f0_990',['RTC_ALRMAR_ST_0',['../group___peripheral___registers___bits___definition.html#gaae5c1ad41702da26788f5ef52c0d05ca',1,'stm32f407xx_matlab.h']]], - ['rtc_5falrmar_5fst_5f1_991',['RTC_ALRMAR_ST_1',['../group___peripheral___registers___bits___definition.html#ga2e771d8055c52a1186d3f47dd567457a',1,'stm32f407xx_matlab.h']]], - ['rtc_5falrmar_5fst_5f2_992',['RTC_ALRMAR_ST_2',['../group___peripheral___registers___bits___definition.html#ga7fdfe4a92c7ab0c326dc9f2638318f97',1,'stm32f407xx_matlab.h']]], - ['rtc_5falrmar_5fst_5fmsk_993',['RTC_ALRMAR_ST_Msk',['../group___peripheral___registers___bits___definition.html#ga5f558ae0134c82f7f64c31a4d8bb33f0',1,'stm32f407xx_matlab.h']]], - ['rtc_5falrmar_5fst_5fpos_994',['RTC_ALRMAR_ST_Pos',['../group___peripheral___registers___bits___definition.html#ga83d9812296958846b0fd24484b205ebd',1,'stm32f407xx_matlab.h']]], - ['rtc_5falrmar_5fsu_995',['RTC_ALRMAR_SU',['../group___peripheral___registers___bits___definition.html#gab8ec4171be73457bc3dba78bd246e35b',1,'stm32f407xx_matlab.h']]], - ['rtc_5falrmar_5fsu_5f0_996',['RTC_ALRMAR_SU_0',['../group___peripheral___registers___bits___definition.html#gaaaf99585af681202a201178f8156dffe',1,'stm32f407xx_matlab.h']]], - ['rtc_5falrmar_5fsu_5f1_997',['RTC_ALRMAR_SU_1',['../group___peripheral___registers___bits___definition.html#ga9d7edbd0609415ca3a328f8498c4a63c',1,'stm32f407xx_matlab.h']]], - ['rtc_5falrmar_5fsu_5f2_998',['RTC_ALRMAR_SU_2',['../group___peripheral___registers___bits___definition.html#ga485a8c274aa56f705dc1363484d7085f',1,'stm32f407xx_matlab.h']]], - ['rtc_5falrmar_5fsu_5f3_999',['RTC_ALRMAR_SU_3',['../group___peripheral___registers___bits___definition.html#gad9d41833996dbd77a0bfbcd9889957a2',1,'stm32f407xx_matlab.h']]], - ['rtc_5falrmar_5fsu_5fmsk_1000',['RTC_ALRMAR_SU_Msk',['../group___peripheral___registers___bits___definition.html#ga37bf69143ae7921782d1baa390c1c866',1,'stm32f407xx_matlab.h']]], - ['rtc_5falrmar_5fsu_5fpos_1001',['RTC_ALRMAR_SU_Pos',['../group___peripheral___registers___bits___definition.html#ga30f4084231cdc1f72bec8c63dac981a3',1,'stm32f407xx_matlab.h']]], - ['rtc_5falrmar_5fwdsel_1002',['RTC_ALRMAR_WDSEL',['../group___peripheral___registers___bits___definition.html#ga5a7fdc1719b3159e099c3979da26dd92',1,'stm32f407xx_matlab.h']]], - ['rtc_5falrmar_5fwdsel_5fmsk_1003',['RTC_ALRMAR_WDSEL_Msk',['../group___peripheral___registers___bits___definition.html#gaccf0424c522933862730917c9c79f81b',1,'stm32f407xx_matlab.h']]], - ['rtc_5falrmar_5fwdsel_5fpos_1004',['RTC_ALRMAR_WDSEL_Pos',['../group___peripheral___registers___bits___definition.html#gadd589f750a310c033dafdab213642649',1,'stm32f407xx_matlab.h']]], - ['rtc_5falrmassr_5fmaskss_1005',['RTC_ALRMASSR_MASKSS',['../group___peripheral___registers___bits___definition.html#ga7b0550ccc175ff54e560cc5fb96fbb2c',1,'stm32f407xx_matlab.h']]], - ['rtc_5falrmassr_5fmaskss_5f0_1006',['RTC_ALRMASSR_MASKSS_0',['../group___peripheral___registers___bits___definition.html#gaeebbc0dfc0a20887ef3582feaa5f1c2b',1,'stm32f407xx_matlab.h']]], - ['rtc_5falrmassr_5fmaskss_5f1_1007',['RTC_ALRMASSR_MASKSS_1',['../group___peripheral___registers___bits___definition.html#gabbdb202f388835593843f480c3b3af57',1,'stm32f407xx_matlab.h']]], - ['rtc_5falrmassr_5fmaskss_5f2_1008',['RTC_ALRMASSR_MASKSS_2',['../group___peripheral___registers___bits___definition.html#ga95feb5de45a74d7c75c1fc6515c32870',1,'stm32f407xx_matlab.h']]], - ['rtc_5falrmassr_5fmaskss_5f3_1009',['RTC_ALRMASSR_MASKSS_3',['../group___peripheral___registers___bits___definition.html#gae94c65876a1baf0984a6f85aa836b8d0',1,'stm32f407xx_matlab.h']]], - ['rtc_5falrmassr_5fmaskss_5fmsk_1010',['RTC_ALRMASSR_MASKSS_Msk',['../group___peripheral___registers___bits___definition.html#ga77d71d0606814b6d20253a645bdb5936',1,'stm32f407xx_matlab.h']]], - ['rtc_5falrmassr_5fmaskss_5fpos_1011',['RTC_ALRMASSR_MASKSS_Pos',['../group___peripheral___registers___bits___definition.html#ga97b73051e1ea4d40a4877f9580c2eb63',1,'stm32f407xx_matlab.h']]], - ['rtc_5falrmassr_5fss_1012',['RTC_ALRMASSR_SS',['../group___peripheral___registers___bits___definition.html#ga4a6b683531fded4e2a77d047da7eb203',1,'stm32f407xx_matlab.h']]], - ['rtc_5falrmassr_5fss_5fmsk_1013',['RTC_ALRMASSR_SS_Msk',['../group___peripheral___registers___bits___definition.html#gadba25e1519a8aa3222912425ae4c4229',1,'stm32f407xx_matlab.h']]], - ['rtc_5falrmassr_5fss_5fpos_1014',['RTC_ALRMASSR_SS_Pos',['../group___peripheral___registers___bits___definition.html#gaf5c69419fc862f5012e842942dd755be',1,'stm32f407xx_matlab.h']]], - ['rtc_5falrmbr_5fdt_1015',['RTC_ALRMBR_DT',['../group___peripheral___registers___bits___definition.html#ga9f8662da4b5f9f0dc0cdd8eac037052b',1,'stm32f407xx_matlab.h']]], - ['rtc_5falrmbr_5fdt_5f0_1016',['RTC_ALRMBR_DT_0',['../group___peripheral___registers___bits___definition.html#ga34531fadcc9d2a702b3b7138831fb4c8',1,'stm32f407xx_matlab.h']]], - ['rtc_5falrmbr_5fdt_5f1_1017',['RTC_ALRMBR_DT_1',['../group___peripheral___registers___bits___definition.html#gabeb8410cfd578e600049846a694dc00d',1,'stm32f407xx_matlab.h']]], - ['rtc_5falrmbr_5fdt_5fmsk_1018',['RTC_ALRMBR_DT_Msk',['../group___peripheral___registers___bits___definition.html#gadf438133a0350e3c1f9e956ea59c165e',1,'stm32f407xx_matlab.h']]], - ['rtc_5falrmbr_5fdt_5fpos_1019',['RTC_ALRMBR_DT_Pos',['../group___peripheral___registers___bits___definition.html#gade6a75b6e4614f322bf046e07cabc022',1,'stm32f407xx_matlab.h']]], - ['rtc_5falrmbr_5fdu_1020',['RTC_ALRMBR_DU',['../group___peripheral___registers___bits___definition.html#ga0beeb5e7c9237d688d5784dba0a5c671',1,'stm32f407xx_matlab.h']]], - ['rtc_5falrmbr_5fdu_5f0_1021',['RTC_ALRMBR_DU_0',['../group___peripheral___registers___bits___definition.html#gaf9886cb39e9c89c40ddc33c6e7659db5',1,'stm32f407xx_matlab.h']]], - ['rtc_5falrmbr_5fdu_5f1_1022',['RTC_ALRMBR_DU_1',['../group___peripheral___registers___bits___definition.html#ga121e8284bdc7ebd634f71e5810dc4f85',1,'stm32f407xx_matlab.h']]], - ['rtc_5falrmbr_5fdu_5f2_1023',['RTC_ALRMBR_DU_2',['../group___peripheral___registers___bits___definition.html#ga78b99f99d3666212ab673dbc9f7f3192',1,'stm32f407xx_matlab.h']]], - ['rtc_5falrmbr_5fdu_5f3_1024',['RTC_ALRMBR_DU_3',['../group___peripheral___registers___bits___definition.html#ga8551995a404be9f58511ea22dca71f1a',1,'stm32f407xx_matlab.h']]], - ['rtc_5falrmbr_5fdu_5fmsk_1025',['RTC_ALRMBR_DU_Msk',['../group___peripheral___registers___bits___definition.html#gaba5234dbab35f4bcc6b1a49b633c9d83',1,'stm32f407xx_matlab.h']]], - ['rtc_5falrmbr_5fdu_5fpos_1026',['RTC_ALRMBR_DU_Pos',['../group___peripheral___registers___bits___definition.html#ga553d2edb82ee8d85c71f795276bb4bba',1,'stm32f407xx_matlab.h']]], - ['rtc_5falrmbr_5fht_1027',['RTC_ALRMBR_HT',['../group___peripheral___registers___bits___definition.html#ga552fbb873fbab8cefd1c5c3536d0989d',1,'stm32f407xx_matlab.h']]], - ['rtc_5falrmbr_5fht_5f0_1028',['RTC_ALRMBR_HT_0',['../group___peripheral___registers___bits___definition.html#gabbddfb1b1ff41f1b76f5ccfb6eb29362',1,'stm32f407xx_matlab.h']]], - ['rtc_5falrmbr_5fht_5f1_1029',['RTC_ALRMBR_HT_1',['../group___peripheral___registers___bits___definition.html#ga3219c5b314ca459c8dcb93c140b210cb',1,'stm32f407xx_matlab.h']]], - ['rtc_5falrmbr_5fht_5fmsk_1030',['RTC_ALRMBR_HT_Msk',['../group___peripheral___registers___bits___definition.html#gad1a64e9998a2032590d32d8e93ac89ad',1,'stm32f407xx_matlab.h']]], - ['rtc_5falrmbr_5fht_5fpos_1031',['RTC_ALRMBR_HT_Pos',['../group___peripheral___registers___bits___definition.html#gadbe2cd364c4d4701876832245cf20ce1',1,'stm32f407xx_matlab.h']]], - ['rtc_5falrmbr_5fhu_1032',['RTC_ALRMBR_HU',['../group___peripheral___registers___bits___definition.html#ga1a01e42db93b9bc9097766d7ccf2d21d',1,'stm32f407xx_matlab.h']]], - ['rtc_5falrmbr_5fhu_5f0_1033',['RTC_ALRMBR_HU_0',['../group___peripheral___registers___bits___definition.html#ga0223058b7ae0a4ae57a7a7997440385e',1,'stm32f407xx_matlab.h']]], - ['rtc_5falrmbr_5fhu_5f1_1034',['RTC_ALRMBR_HU_1',['../group___peripheral___registers___bits___definition.html#ga9a7c34c4e83f374790e3ed27a3e23443',1,'stm32f407xx_matlab.h']]], - ['rtc_5falrmbr_5fhu_5f2_1035',['RTC_ALRMBR_HU_2',['../group___peripheral___registers___bits___definition.html#gad5e6d673134918e74d9a0f06ca4dc479',1,'stm32f407xx_matlab.h']]], - ['rtc_5falrmbr_5fhu_5f3_1036',['RTC_ALRMBR_HU_3',['../group___peripheral___registers___bits___definition.html#gae538b44aa24031a294442dc47f6849f5',1,'stm32f407xx_matlab.h']]], - ['rtc_5falrmbr_5fhu_5fmsk_1037',['RTC_ALRMBR_HU_Msk',['../group___peripheral___registers___bits___definition.html#ga16f950667f6001e8b23b88b355cc072a',1,'stm32f407xx_matlab.h']]], - ['rtc_5falrmbr_5fhu_5fpos_1038',['RTC_ALRMBR_HU_Pos',['../group___peripheral___registers___bits___definition.html#gaf5880949c342cf52cc4596e73dc1f84e',1,'stm32f407xx_matlab.h']]], - ['rtc_5falrmbr_5fmnt_1039',['RTC_ALRMBR_MNT',['../group___peripheral___registers___bits___definition.html#ga05e2ef0960c04023b98a104202f44571',1,'stm32f407xx_matlab.h']]], - ['rtc_5falrmbr_5fmnt_5f0_1040',['RTC_ALRMBR_MNT_0',['../group___peripheral___registers___bits___definition.html#gaf1170e6bedeafe4da96568080fe3bbe3',1,'stm32f407xx_matlab.h']]], - ['rtc_5falrmbr_5fmnt_5f1_1041',['RTC_ALRMBR_MNT_1',['../group___peripheral___registers___bits___definition.html#ga56977652001bc709e4c37fce5647eb40',1,'stm32f407xx_matlab.h']]], - ['rtc_5falrmbr_5fmnt_5f2_1042',['RTC_ALRMBR_MNT_2',['../group___peripheral___registers___bits___definition.html#gafbdfd2b2b1fc039fe8efdd6df612b220',1,'stm32f407xx_matlab.h']]], - ['rtc_5falrmbr_5fmnt_5fmsk_1043',['RTC_ALRMBR_MNT_Msk',['../group___peripheral___registers___bits___definition.html#ga4abe6f205a3aafc2fdd5930b06ca5250',1,'stm32f407xx_matlab.h']]], - ['rtc_5falrmbr_5fmnt_5fpos_1044',['RTC_ALRMBR_MNT_Pos',['../group___peripheral___registers___bits___definition.html#ga995f7d294d4b202db6a6c06c0c40b325',1,'stm32f407xx_matlab.h']]], - ['rtc_5falrmbr_5fmnu_1045',['RTC_ALRMBR_MNU',['../group___peripheral___registers___bits___definition.html#ga3ca0feaf431b9f9dde4a9d97cae39056',1,'stm32f407xx_matlab.h']]], - ['rtc_5falrmbr_5fmnu_5f0_1046',['RTC_ALRMBR_MNU_0',['../group___peripheral___registers___bits___definition.html#ga93830709da4736a2e8da1cf3a3596dda',1,'stm32f407xx_matlab.h']]], - ['rtc_5falrmbr_5fmnu_5f1_1047',['RTC_ALRMBR_MNU_1',['../group___peripheral___registers___bits___definition.html#gae9cab4a9df6a1e45e2a3212b357e1bef',1,'stm32f407xx_matlab.h']]], - ['rtc_5falrmbr_5fmnu_5f2_1048',['RTC_ALRMBR_MNU_2',['../group___peripheral___registers___bits___definition.html#ga869e14a514b3d140a2dcad669e2ab3e0',1,'stm32f407xx_matlab.h']]], - ['rtc_5falrmbr_5fmnu_5f3_1049',['RTC_ALRMBR_MNU_3',['../group___peripheral___registers___bits___definition.html#gaec666ddc3d2c205d46d4e1e5bdcf9243',1,'stm32f407xx_matlab.h']]], - ['rtc_5falrmbr_5fmnu_5fmsk_1050',['RTC_ALRMBR_MNU_Msk',['../group___peripheral___registers___bits___definition.html#ga14ee879ec288fff19824ee589b54972b',1,'stm32f407xx_matlab.h']]], - ['rtc_5falrmbr_5fmnu_5fpos_1051',['RTC_ALRMBR_MNU_Pos',['../group___peripheral___registers___bits___definition.html#gabec1334e452f9f973603fa7de232ec93',1,'stm32f407xx_matlab.h']]], - ['rtc_5falrmbr_5fmsk1_1052',['RTC_ALRMBR_MSK1',['../group___peripheral___registers___bits___definition.html#gaa472193eb2ace80c95874c850236b489',1,'stm32f407xx_matlab.h']]], - ['rtc_5falrmbr_5fmsk1_5fmsk_1053',['RTC_ALRMBR_MSK1_Msk',['../group___peripheral___registers___bits___definition.html#ga7f741db655cf45b9b6b254c491f3738d',1,'stm32f407xx_matlab.h']]], - ['rtc_5falrmbr_5fmsk1_5fpos_1054',['RTC_ALRMBR_MSK1_Pos',['../group___peripheral___registers___bits___definition.html#ga46564dcbbf9eec8854fa091155045f90',1,'stm32f407xx_matlab.h']]], - ['rtc_5falrmbr_5fmsk2_1055',['RTC_ALRMBR_MSK2',['../group___peripheral___registers___bits___definition.html#ga124c24eb148681777758f1298776f5a1',1,'stm32f407xx_matlab.h']]], - ['rtc_5falrmbr_5fmsk2_5fmsk_1056',['RTC_ALRMBR_MSK2_Msk',['../group___peripheral___registers___bits___definition.html#ga8a678de5920eddb36f8edc45c992aa10',1,'stm32f407xx_matlab.h']]], - ['rtc_5falrmbr_5fmsk2_5fpos_1057',['RTC_ALRMBR_MSK2_Pos',['../group___peripheral___registers___bits___definition.html#ga757c08763995ee18cb34d7dd04a8f2d0',1,'stm32f407xx_matlab.h']]], - ['rtc_5falrmbr_5fmsk3_1058',['RTC_ALRMBR_MSK3',['../group___peripheral___registers___bits___definition.html#gaca7cd93178102c8769d0874d5b8394c4',1,'stm32f407xx_matlab.h']]], - ['rtc_5falrmbr_5fmsk3_5fmsk_1059',['RTC_ALRMBR_MSK3_Msk',['../group___peripheral___registers___bits___definition.html#ga8a10ef06416ab43ddcc978f7c484fd30',1,'stm32f407xx_matlab.h']]], - ['rtc_5falrmbr_5fmsk3_5fpos_1060',['RTC_ALRMBR_MSK3_Pos',['../group___peripheral___registers___bits___definition.html#ga2424f9d237a98722a6276d7effa078b7',1,'stm32f407xx_matlab.h']]], - ['rtc_5falrmbr_5fmsk4_1061',['RTC_ALRMBR_MSK4',['../group___peripheral___registers___bits___definition.html#ga934df96e83f72268528e62c55c03b50d',1,'stm32f407xx_matlab.h']]], - ['rtc_5falrmbr_5fmsk4_5fmsk_1062',['RTC_ALRMBR_MSK4_Msk',['../group___peripheral___registers___bits___definition.html#ga6359d5b79cd667e4f7f093e0d0ee8320',1,'stm32f407xx_matlab.h']]], - ['rtc_5falrmbr_5fmsk4_5fpos_1063',['RTC_ALRMBR_MSK4_Pos',['../group___peripheral___registers___bits___definition.html#ga2383d51761039ce9b70e6a33bfde165a',1,'stm32f407xx_matlab.h']]], - ['rtc_5falrmbr_5fpm_1064',['RTC_ALRMBR_PM',['../group___peripheral___registers___bits___definition.html#ga4fc947f41bd2a091b13ffeff4312b67b',1,'stm32f407xx_matlab.h']]], - ['rtc_5falrmbr_5fpm_5fmsk_1065',['RTC_ALRMBR_PM_Msk',['../group___peripheral___registers___bits___definition.html#gafb73d11c2f8f01d03b143bf0eb50a3c1',1,'stm32f407xx_matlab.h']]], - ['rtc_5falrmbr_5fpm_5fpos_1066',['RTC_ALRMBR_PM_Pos',['../group___peripheral___registers___bits___definition.html#ga7b091bf9f116760614f434cd54a8132e',1,'stm32f407xx_matlab.h']]], - ['rtc_5falrmbr_5fst_1067',['RTC_ALRMBR_ST',['../group___peripheral___registers___bits___definition.html#gad7a6c70156cd32b6aa855e4f2e32406c',1,'stm32f407xx_matlab.h']]], - ['rtc_5falrmbr_5fst_5f0_1068',['RTC_ALRMBR_ST_0',['../group___peripheral___registers___bits___definition.html#ga2514a54011c9ff7b48939e9cbd13f859',1,'stm32f407xx_matlab.h']]], - ['rtc_5falrmbr_5fst_5f1_1069',['RTC_ALRMBR_ST_1',['../group___peripheral___registers___bits___definition.html#gad6b6e10efeaeac2898a754e2a360fb27',1,'stm32f407xx_matlab.h']]], - ['rtc_5falrmbr_5fst_5f2_1070',['RTC_ALRMBR_ST_2',['../group___peripheral___registers___bits___definition.html#ga423e1673ab928b5e43e9fa9b65d2122c',1,'stm32f407xx_matlab.h']]], - ['rtc_5falrmbr_5fst_5fmsk_1071',['RTC_ALRMBR_ST_Msk',['../group___peripheral___registers___bits___definition.html#ga2c1a51469b2ad8675eeee8a39ea29ff7',1,'stm32f407xx_matlab.h']]], - ['rtc_5falrmbr_5fst_5fpos_1072',['RTC_ALRMBR_ST_Pos',['../group___peripheral___registers___bits___definition.html#ga62ce834a2d4f2d1b2d338b1e8da054d5',1,'stm32f407xx_matlab.h']]], - ['rtc_5falrmbr_5fsu_1073',['RTC_ALRMBR_SU',['../group___peripheral___registers___bits___definition.html#gae2fdd1ad6a4b7db36ece6145cba49ccf',1,'stm32f407xx_matlab.h']]], - ['rtc_5falrmbr_5fsu_5f0_1074',['RTC_ALRMBR_SU_0',['../group___peripheral___registers___bits___definition.html#ga1aa325b93084bf6fdc494842e1f0b652',1,'stm32f407xx_matlab.h']]], - ['rtc_5falrmbr_5fsu_5f1_1075',['RTC_ALRMBR_SU_1',['../group___peripheral___registers___bits___definition.html#ga72ed3dd8ae6a59462a99f8c3d8c316e5',1,'stm32f407xx_matlab.h']]], - ['rtc_5falrmbr_5fsu_5f2_1076',['RTC_ALRMBR_SU_2',['../group___peripheral___registers___bits___definition.html#gac21f97b7b207139ffb0d1e6ede81bb91',1,'stm32f407xx_matlab.h']]], - ['rtc_5falrmbr_5fsu_5f3_1077',['RTC_ALRMBR_SU_3',['../group___peripheral___registers___bits___definition.html#ga9b548175b400ee92c11c2c446d6d129b',1,'stm32f407xx_matlab.h']]], - ['rtc_5falrmbr_5fsu_5fmsk_1078',['RTC_ALRMBR_SU_Msk',['../group___peripheral___registers___bits___definition.html#ga8b09e067d4a36bd9c6a85ec3193da6d2',1,'stm32f407xx_matlab.h']]], - ['rtc_5falrmbr_5fsu_5fpos_1079',['RTC_ALRMBR_SU_Pos',['../group___peripheral___registers___bits___definition.html#gaef14da4012b4e250c549154393537c3b',1,'stm32f407xx_matlab.h']]], - ['rtc_5falrmbr_5fwdsel_1080',['RTC_ALRMBR_WDSEL',['../group___peripheral___registers___bits___definition.html#ga3acc5db599b055a0c1eca04024bf0285',1,'stm32f407xx_matlab.h']]], - ['rtc_5falrmbr_5fwdsel_5fmsk_1081',['RTC_ALRMBR_WDSEL_Msk',['../group___peripheral___registers___bits___definition.html#gaff53d89da5c55043f8d32e800319b0c0',1,'stm32f407xx_matlab.h']]], - ['rtc_5falrmbr_5fwdsel_5fpos_1082',['RTC_ALRMBR_WDSEL_Pos',['../group___peripheral___registers___bits___definition.html#gac975a5ed682b832e8600dba67aa9ad37',1,'stm32f407xx_matlab.h']]], - ['rtc_5falrmbssr_5fmaskss_1083',['RTC_ALRMBSSR_MASKSS',['../group___peripheral___registers___bits___definition.html#gaf287b0ec7dbf8e9d436cb78da287b244',1,'stm32f407xx_matlab.h']]], - ['rtc_5falrmbssr_5fmaskss_5f0_1084',['RTC_ALRMBSSR_MASKSS_0',['../group___peripheral___registers___bits___definition.html#gad4d60185d1ac432b24b0a95e2918902f',1,'stm32f407xx_matlab.h']]], - ['rtc_5falrmbssr_5fmaskss_5f1_1085',['RTC_ALRMBSSR_MASKSS_1',['../group___peripheral___registers___bits___definition.html#ga9763a1a382e40cc2ebfa6d84369580df',1,'stm32f407xx_matlab.h']]], - ['rtc_5falrmbssr_5fmaskss_5f2_1086',['RTC_ALRMBSSR_MASKSS_2',['../group___peripheral___registers___bits___definition.html#ga598283f8a8926f0dcb7916a2224f79bc',1,'stm32f407xx_matlab.h']]], - ['rtc_5falrmbssr_5fmaskss_5f3_1087',['RTC_ALRMBSSR_MASKSS_3',['../group___peripheral___registers___bits___definition.html#gadf017c71fc7eb34519de3945a028677b',1,'stm32f407xx_matlab.h']]], - ['rtc_5falrmbssr_5fmaskss_5fmsk_1088',['RTC_ALRMBSSR_MASKSS_Msk',['../group___peripheral___registers___bits___definition.html#ga54f65537e9a664f30ca7f3099c6fcc5f',1,'stm32f407xx_matlab.h']]], - ['rtc_5falrmbssr_5fmaskss_5fpos_1089',['RTC_ALRMBSSR_MASKSS_Pos',['../group___peripheral___registers___bits___definition.html#ga0bedfef79d265b81f561e7f2c5a6249a',1,'stm32f407xx_matlab.h']]], - ['rtc_5falrmbssr_5fss_1090',['RTC_ALRMBSSR_SS',['../group___peripheral___registers___bits___definition.html#ga33ae74f38392431aa631d397a7e7c305',1,'stm32f407xx_matlab.h']]], - ['rtc_5falrmbssr_5fss_5fmsk_1091',['RTC_ALRMBSSR_SS_Msk',['../group___peripheral___registers___bits___definition.html#gaaea93544826ca1a8e920ffd0f46c2bbe',1,'stm32f407xx_matlab.h']]], - ['rtc_5falrmbssr_5fss_5fpos_1092',['RTC_ALRMBSSR_SS_Pos',['../group___peripheral___registers___bits___definition.html#ga2f2a25c58bddba6df25d75825eff3f76',1,'stm32f407xx_matlab.h']]], - ['rtc_5fbase_1093',['RTC_BASE',['../group___peripheral__memory__map.html#ga4265e665d56225412e57a61d87417022',1,'stm32f407xx_matlab.h']]], - ['rtc_5fbkp0r_1094',['RTC_BKP0R',['../group___peripheral___registers___bits___definition.html#gae0d7c3115465079f04cfb97a7faabc59',1,'stm32f407xx_matlab.h']]], - ['rtc_5fbkp0r_5fmsk_1095',['RTC_BKP0R_Msk',['../group___peripheral___registers___bits___definition.html#ga65152adac13a55042ab984b782cf785b',1,'stm32f407xx_matlab.h']]], - ['rtc_5fbkp0r_5fpos_1096',['RTC_BKP0R_Pos',['../group___peripheral___registers___bits___definition.html#ga8d2a1d81a7e8f12510f865312caea186',1,'stm32f407xx_matlab.h']]], - ['rtc_5fbkp10r_1097',['RTC_BKP10R',['../group___peripheral___registers___bits___definition.html#ga2179063a3078a211c3b697ce012ab5a0',1,'stm32f407xx_matlab.h']]], - ['rtc_5fbkp10r_5fmsk_1098',['RTC_BKP10R_Msk',['../group___peripheral___registers___bits___definition.html#ga425836775a344f3d199760028c01b22f',1,'stm32f407xx_matlab.h']]], - ['rtc_5fbkp10r_5fpos_1099',['RTC_BKP10R_Pos',['../group___peripheral___registers___bits___definition.html#ga68a6b8b6fd6e38bcbb396de36791b97d',1,'stm32f407xx_matlab.h']]], - ['rtc_5fbkp11r_1100',['RTC_BKP11R',['../group___peripheral___registers___bits___definition.html#gab250f9423dee41b165aa8f02d2fc1fe7',1,'stm32f407xx_matlab.h']]], - ['rtc_5fbkp11r_5fmsk_1101',['RTC_BKP11R_Msk',['../group___peripheral___registers___bits___definition.html#ga803ec730ae4020d5b80df83b21990b31',1,'stm32f407xx_matlab.h']]], - ['rtc_5fbkp11r_5fpos_1102',['RTC_BKP11R_Pos',['../group___peripheral___registers___bits___definition.html#ga71f7a489ec11b5547afa3470d76ea62a',1,'stm32f407xx_matlab.h']]], - ['rtc_5fbkp12r_1103',['RTC_BKP12R',['../group___peripheral___registers___bits___definition.html#gaefe1b6108ac49197b28c9bee31bbaf3b',1,'stm32f407xx_matlab.h']]], - ['rtc_5fbkp12r_5fmsk_1104',['RTC_BKP12R_Msk',['../group___peripheral___registers___bits___definition.html#gaaed050277146eb1c2fa2a8e8eb778888',1,'stm32f407xx_matlab.h']]], - ['rtc_5fbkp12r_5fpos_1105',['RTC_BKP12R_Pos',['../group___peripheral___registers___bits___definition.html#ga2e64139e8db6dcca0efbb9e3a4e6a524',1,'stm32f407xx_matlab.h']]], - ['rtc_5fbkp13r_1106',['RTC_BKP13R',['../group___peripheral___registers___bits___definition.html#ga0e77435e16bdebf3491eb0e30bd10b0d',1,'stm32f407xx_matlab.h']]], - ['rtc_5fbkp13r_5fmsk_1107',['RTC_BKP13R_Msk',['../group___peripheral___registers___bits___definition.html#ga2f1c04da88aaae10d0bcf45816608b8e',1,'stm32f407xx_matlab.h']]], - ['rtc_5fbkp13r_5fpos_1108',['RTC_BKP13R_Pos',['../group___peripheral___registers___bits___definition.html#ga704dac9c54b7afd7e51c026ef0093eed',1,'stm32f407xx_matlab.h']]], - ['rtc_5fbkp14r_1109',['RTC_BKP14R',['../group___peripheral___registers___bits___definition.html#ga5f07ee6d227deaa11e0ae035121185b0',1,'stm32f407xx_matlab.h']]], - ['rtc_5fbkp14r_5fmsk_1110',['RTC_BKP14R_Msk',['../group___peripheral___registers___bits___definition.html#gaceeefc705b2bd138b6ec84bd606dbe86',1,'stm32f407xx_matlab.h']]], - ['rtc_5fbkp14r_5fpos_1111',['RTC_BKP14R_Pos',['../group___peripheral___registers___bits___definition.html#ga35ea3d3c00bb891b7702428ab6b13526',1,'stm32f407xx_matlab.h']]], - ['rtc_5fbkp15r_1112',['RTC_BKP15R',['../group___peripheral___registers___bits___definition.html#gae543b0dd58f03c2f70bb6b3b65232863',1,'stm32f407xx_matlab.h']]], - ['rtc_5fbkp15r_5fmsk_1113',['RTC_BKP15R_Msk',['../group___peripheral___registers___bits___definition.html#gae55844e319f165ba23ba0b2d5a9ff2ee',1,'stm32f407xx_matlab.h']]], - ['rtc_5fbkp15r_5fpos_1114',['RTC_BKP15R_Pos',['../group___peripheral___registers___bits___definition.html#gab300e7778a3b5f5e69b9e3c6a2f00244',1,'stm32f407xx_matlab.h']]], - ['rtc_5fbkp16r_1115',['RTC_BKP16R',['../group___peripheral___registers___bits___definition.html#gaf0add0c768094f0de71bb4e50fbcce6e',1,'stm32f407xx_matlab.h']]], - ['rtc_5fbkp16r_5fmsk_1116',['RTC_BKP16R_Msk',['../group___peripheral___registers___bits___definition.html#gad53cd82e4d08160a2169cf0d6122ba7a',1,'stm32f407xx_matlab.h']]], - ['rtc_5fbkp16r_5fpos_1117',['RTC_BKP16R_Pos',['../group___peripheral___registers___bits___definition.html#gae8a577b0955f75ea83804f5d16b7361a',1,'stm32f407xx_matlab.h']]], - ['rtc_5fbkp17r_1118',['RTC_BKP17R',['../group___peripheral___registers___bits___definition.html#ga059aaedb55963f39e8724d50d55d5282',1,'stm32f407xx_matlab.h']]], - ['rtc_5fbkp17r_5fmsk_1119',['RTC_BKP17R_Msk',['../group___peripheral___registers___bits___definition.html#gaeb00d71ec7bae68636740347f971bb05',1,'stm32f407xx_matlab.h']]], - ['rtc_5fbkp17r_5fpos_1120',['RTC_BKP17R_Pos',['../group___peripheral___registers___bits___definition.html#ga6036f283574a87f4d27610040c53eb1e',1,'stm32f407xx_matlab.h']]], - ['rtc_5fbkp18r_1121',['RTC_BKP18R',['../group___peripheral___registers___bits___definition.html#ga66154eb091275e87a4bd53e87ef9214e',1,'stm32f407xx_matlab.h']]], - ['rtc_5fbkp18r_5fmsk_1122',['RTC_BKP18R_Msk',['../group___peripheral___registers___bits___definition.html#gad06553479e94b2bbd23fde19bbcf0667',1,'stm32f407xx_matlab.h']]], - ['rtc_5fbkp18r_5fpos_1123',['RTC_BKP18R_Pos',['../group___peripheral___registers___bits___definition.html#gad55ca335d5c133a1b773affcb87e421c',1,'stm32f407xx_matlab.h']]], - ['rtc_5fbkp19r_1124',['RTC_BKP19R',['../group___peripheral___registers___bits___definition.html#gafa4c31e33d851fde2715059ea28dac6f',1,'stm32f407xx_matlab.h']]], - ['rtc_5fbkp19r_5fmsk_1125',['RTC_BKP19R_Msk',['../group___peripheral___registers___bits___definition.html#ga9dd25b421b61fc893df921c7ea4d58f1',1,'stm32f407xx_matlab.h']]], - ['rtc_5fbkp19r_5fpos_1126',['RTC_BKP19R_Pos',['../group___peripheral___registers___bits___definition.html#ga5eee6977105e1d1972deedeeb87efe2c',1,'stm32f407xx_matlab.h']]], - ['rtc_5fbkp1r_1127',['RTC_BKP1R',['../group___peripheral___registers___bits___definition.html#gafbc4b6dfeff87332124f271b86eb0c56',1,'stm32f407xx_matlab.h']]], - ['rtc_5fbkp1r_5fmsk_1128',['RTC_BKP1R_Msk',['../group___peripheral___registers___bits___definition.html#ga1232543b3a22da7aac7131e173182686',1,'stm32f407xx_matlab.h']]], - ['rtc_5fbkp1r_5fpos_1129',['RTC_BKP1R_Pos',['../group___peripheral___registers___bits___definition.html#gaa2eff670c07a820b705ec3745683dc75',1,'stm32f407xx_matlab.h']]], - ['rtc_5fbkp2r_1130',['RTC_BKP2R',['../group___peripheral___registers___bits___definition.html#ga34fda9ee6115f0de9588e22c46602d89',1,'stm32f407xx_matlab.h']]], - ['rtc_5fbkp2r_5fmsk_1131',['RTC_BKP2R_Msk',['../group___peripheral___registers___bits___definition.html#gafe778fc6aa04076af499bfe4eef8f5e1',1,'stm32f407xx_matlab.h']]], - ['rtc_5fbkp2r_5fpos_1132',['RTC_BKP2R_Pos',['../group___peripheral___registers___bits___definition.html#ga61b179787d35514914d2e103e3cc5388',1,'stm32f407xx_matlab.h']]], - ['rtc_5fbkp3r_1133',['RTC_BKP3R',['../group___peripheral___registers___bits___definition.html#ga90403ff99c08f0abc379447823e5e841',1,'stm32f407xx_matlab.h']]], - ['rtc_5fbkp3r_5fmsk_1134',['RTC_BKP3R_Msk',['../group___peripheral___registers___bits___definition.html#ga6e99106bc39a8e81bf48352827d0ddaf',1,'stm32f407xx_matlab.h']]], - ['rtc_5fbkp3r_5fpos_1135',['RTC_BKP3R_Pos',['../group___peripheral___registers___bits___definition.html#gad53baa189d917e48c2c274655adc9483',1,'stm32f407xx_matlab.h']]], - ['rtc_5fbkp4r_1136',['RTC_BKP4R',['../group___peripheral___registers___bits___definition.html#gaeed1b338e9526d817a1fd01304b8851c',1,'stm32f407xx_matlab.h']]], - ['rtc_5fbkp4r_5fmsk_1137',['RTC_BKP4R_Msk',['../group___peripheral___registers___bits___definition.html#ga64613b1fe898ececd40ffe481df742ab',1,'stm32f407xx_matlab.h']]], - ['rtc_5fbkp4r_5fpos_1138',['RTC_BKP4R_Pos',['../group___peripheral___registers___bits___definition.html#gad62cbb0c17b02ce23ca2bdd29b0ed349',1,'stm32f407xx_matlab.h']]], - ['rtc_5fbkp5r_1139',['RTC_BKP5R',['../group___peripheral___registers___bits___definition.html#ga4e8954ab0ead8bb788d5d8eebf2f5c4c',1,'stm32f407xx_matlab.h']]], - ['rtc_5fbkp5r_5fmsk_1140',['RTC_BKP5R_Msk',['../group___peripheral___registers___bits___definition.html#ga2335682b85414d8d53d4fffdfc3bf190',1,'stm32f407xx_matlab.h']]], - ['rtc_5fbkp5r_5fpos_1141',['RTC_BKP5R_Pos',['../group___peripheral___registers___bits___definition.html#ga025745144302ad1dd444f09687634674',1,'stm32f407xx_matlab.h']]], - ['rtc_5fbkp6r_1142',['RTC_BKP6R',['../group___peripheral___registers___bits___definition.html#ga4b9ee9eb5d024ccd5809fcc20fd51f5b',1,'stm32f407xx_matlab.h']]], - ['rtc_5fbkp6r_5fmsk_1143',['RTC_BKP6R_Msk',['../group___peripheral___registers___bits___definition.html#ga2cca326be267e10381f4d4f9d5951c32',1,'stm32f407xx_matlab.h']]], - ['rtc_5fbkp6r_5fpos_1144',['RTC_BKP6R_Pos',['../group___peripheral___registers___bits___definition.html#gac2e7347300206d08a294ba300b9dcdfd',1,'stm32f407xx_matlab.h']]], - ['rtc_5fbkp7r_1145',['RTC_BKP7R',['../group___peripheral___registers___bits___definition.html#gab0f1ae07f7b1815bf58b464dc7366731',1,'stm32f407xx_matlab.h']]], - ['rtc_5fbkp7r_5fmsk_1146',['RTC_BKP7R_Msk',['../group___peripheral___registers___bits___definition.html#gaf3ad5bf67535cba7d3de78d72ae79d79',1,'stm32f407xx_matlab.h']]], - ['rtc_5fbkp7r_5fpos_1147',['RTC_BKP7R_Pos',['../group___peripheral___registers___bits___definition.html#gab37f3f4b5f12182f8fd48431c5b5d9fb',1,'stm32f407xx_matlab.h']]], - ['rtc_5fbkp8r_1148',['RTC_BKP8R',['../group___peripheral___registers___bits___definition.html#ga2bd10acb9e5ce5225af4ff895bd3bb82',1,'stm32f407xx_matlab.h']]], - ['rtc_5fbkp8r_5fmsk_1149',['RTC_BKP8R_Msk',['../group___peripheral___registers___bits___definition.html#ga61ae366e9c0ad90225479d0d6d4e1544',1,'stm32f407xx_matlab.h']]], - ['rtc_5fbkp8r_5fpos_1150',['RTC_BKP8R_Pos',['../group___peripheral___registers___bits___definition.html#ga0a01cc89fbe70d722025ba445143da77',1,'stm32f407xx_matlab.h']]], - ['rtc_5fbkp9r_1151',['RTC_BKP9R',['../group___peripheral___registers___bits___definition.html#ga9aa3d0d90de22a1dbf3b6de2b7ed4c9e',1,'stm32f407xx_matlab.h']]], - ['rtc_5fbkp9r_5fmsk_1152',['RTC_BKP9R_Msk',['../group___peripheral___registers___bits___definition.html#gaf039d5e2bf31dc293bd3b84a186bd8c8',1,'stm32f407xx_matlab.h']]], - ['rtc_5fbkp9r_5fpos_1153',['RTC_BKP9R_Pos',['../group___peripheral___registers___bits___definition.html#gaf98c5146f622b5e7a9aef16b75f0a76f',1,'stm32f407xx_matlab.h']]], - ['rtc_5fbkp_5fnumber_1154',['RTC_BKP_NUMBER',['../group___peripheral___registers___bits___definition.html#ga70de60adf3ddd7d029bb2c6ae26d9584',1,'stm32f407xx_matlab.h']]], - ['rtc_5fcalibr_5fdc_1155',['RTC_CALIBR_DC',['../group___peripheral___registers___bits___definition.html#gab5523cf582ebc0a987c6a2c2007bc10d',1,'stm32f407xx_matlab.h']]], - ['rtc_5fcalibr_5fdc_5fmsk_1156',['RTC_CALIBR_DC_Msk',['../group___peripheral___registers___bits___definition.html#gabb0820dbde8c1188a5c045e6e264c1f8',1,'stm32f407xx_matlab.h']]], - ['rtc_5fcalibr_5fdc_5fpos_1157',['RTC_CALIBR_DC_Pos',['../group___peripheral___registers___bits___definition.html#ga612c3ec0e88f91fd34cfb4910b5b46fb',1,'stm32f407xx_matlab.h']]], - ['rtc_5fcalibr_5fdcs_1158',['RTC_CALIBR_DCS',['../group___peripheral___registers___bits___definition.html#gaa63841fd7262fd307f211ee8e9e8a6f0',1,'stm32f407xx_matlab.h']]], - ['rtc_5fcalibr_5fdcs_5fmsk_1159',['RTC_CALIBR_DCS_Msk',['../group___peripheral___registers___bits___definition.html#gac975f6abc1ae98deb38d1c523a564431',1,'stm32f407xx_matlab.h']]], - ['rtc_5fcalibr_5fdcs_5fpos_1160',['RTC_CALIBR_DCS_Pos',['../group___peripheral___registers___bits___definition.html#ga79b734efd7f580384b76364f8159ce2a',1,'stm32f407xx_matlab.h']]], - ['rtc_5fcalr_5fcalm_1161',['RTC_CALR_CALM',['../group___peripheral___registers___bits___definition.html#ga44fcacd12e1cfc1fa823c798cb6a7663',1,'stm32f407xx_matlab.h']]], - ['rtc_5fcalr_5fcalm_5f0_1162',['RTC_CALR_CALM_0',['../group___peripheral___registers___bits___definition.html#gaeffec95cc4cbbdbc77e907818b8c7ebd',1,'stm32f407xx_matlab.h']]], - ['rtc_5fcalr_5fcalm_5f1_1163',['RTC_CALR_CALM_1',['../group___peripheral___registers___bits___definition.html#ga4b908b77786838e5e2e8a1ee2cbbeeff',1,'stm32f407xx_matlab.h']]], - ['rtc_5fcalr_5fcalm_5f2_1164',['RTC_CALR_CALM_2',['../group___peripheral___registers___bits___definition.html#gad09f14c1ff24a01d51d5b6c0bba220d6',1,'stm32f407xx_matlab.h']]], - ['rtc_5fcalr_5fcalm_5f3_1165',['RTC_CALR_CALM_3',['../group___peripheral___registers___bits___definition.html#gac9146fbef6a53896f3160c89ed651b90',1,'stm32f407xx_matlab.h']]], - ['rtc_5fcalr_5fcalm_5f4_1166',['RTC_CALR_CALM_4',['../group___peripheral___registers___bits___definition.html#ga5fe04fc9762d3f680f9145a50898c27b',1,'stm32f407xx_matlab.h']]], - ['rtc_5fcalr_5fcalm_5f5_1167',['RTC_CALR_CALM_5',['../group___peripheral___registers___bits___definition.html#gadc4966c71cab83be4069e0566222d375',1,'stm32f407xx_matlab.h']]], - ['rtc_5fcalr_5fcalm_5f6_1168',['RTC_CALR_CALM_6',['../group___peripheral___registers___bits___definition.html#gae240b185d0c9c6e314a456627e6e4834',1,'stm32f407xx_matlab.h']]], - ['rtc_5fcalr_5fcalm_5f7_1169',['RTC_CALR_CALM_7',['../group___peripheral___registers___bits___definition.html#gab8880325073e167137366402f15d5683',1,'stm32f407xx_matlab.h']]], - ['rtc_5fcalr_5fcalm_5f8_1170',['RTC_CALR_CALM_8',['../group___peripheral___registers___bits___definition.html#ga8381cc75166acfc4b4c686ad7e5e599a',1,'stm32f407xx_matlab.h']]], - ['rtc_5fcalr_5fcalm_5fmsk_1171',['RTC_CALR_CALM_Msk',['../group___peripheral___registers___bits___definition.html#ga347a7b8bed29029bd0d8a78ce03268c8',1,'stm32f407xx_matlab.h']]], - ['rtc_5fcalr_5fcalm_5fpos_1172',['RTC_CALR_CALM_Pos',['../group___peripheral___registers___bits___definition.html#ga702670ae12e1600fea81ef41ea485fd6',1,'stm32f407xx_matlab.h']]], - ['rtc_5fcalr_5fcalp_1173',['RTC_CALR_CALP',['../group___peripheral___registers___bits___definition.html#ga9b13b9724302c25fbca76684f5968528',1,'stm32f407xx_matlab.h']]], - ['rtc_5fcalr_5fcalp_5fmsk_1174',['RTC_CALR_CALP_Msk',['../group___peripheral___registers___bits___definition.html#ga5632e54eb1a07b95a3024c2a52665a24',1,'stm32f407xx_matlab.h']]], - ['rtc_5fcalr_5fcalp_5fpos_1175',['RTC_CALR_CALP_Pos',['../group___peripheral___registers___bits___definition.html#ga5458d41d3893259a7c1adcb12626552d',1,'stm32f407xx_matlab.h']]], - ['rtc_5fcalr_5fcalw16_1176',['RTC_CALR_CALW16',['../group___peripheral___registers___bits___definition.html#ga70857526590d6f7e25d9551187105583',1,'stm32f407xx_matlab.h']]], - ['rtc_5fcalr_5fcalw16_5fmsk_1177',['RTC_CALR_CALW16_Msk',['../group___peripheral___registers___bits___definition.html#gaa75bb89101a1da73b2d78c1486dbf2e2',1,'stm32f407xx_matlab.h']]], - ['rtc_5fcalr_5fcalw16_5fpos_1178',['RTC_CALR_CALW16_Pos',['../group___peripheral___registers___bits___definition.html#ga9ac54a062e43b815b226acdb30888ca9',1,'stm32f407xx_matlab.h']]], - ['rtc_5fcalr_5fcalw8_1179',['RTC_CALR_CALW8',['../group___peripheral___registers___bits___definition.html#ga28f8c7f5f5bf772c81170a2eab055557',1,'stm32f407xx_matlab.h']]], - ['rtc_5fcalr_5fcalw8_5fmsk_1180',['RTC_CALR_CALW8_Msk',['../group___peripheral___registers___bits___definition.html#gac4a1d426d16a747f07e8d8cf98c7275e',1,'stm32f407xx_matlab.h']]], - ['rtc_5fcalr_5fcalw8_5fpos_1181',['RTC_CALR_CALW8_Pos',['../group___peripheral___registers___bits___definition.html#ga4ad4a6054ae32e1332b456d59e0aa36c',1,'stm32f407xx_matlab.h']]], - ['rtc_5fcr_5fadd1h_1182',['RTC_CR_ADD1H',['../group___peripheral___registers___bits___definition.html#gaae1a8439d08e28289398dcf3c2b4b47b',1,'stm32f407xx_matlab.h']]], - ['rtc_5fcr_5fadd1h_5fmsk_1183',['RTC_CR_ADD1H_Msk',['../group___peripheral___registers___bits___definition.html#ga01aac32ee74fbafd54de75ee53bf1417',1,'stm32f407xx_matlab.h']]], - ['rtc_5fcr_5fadd1h_5fpos_1184',['RTC_CR_ADD1H_Pos',['../group___peripheral___registers___bits___definition.html#gab04a33865dc30af95c633750711fc6d0',1,'stm32f407xx_matlab.h']]], - ['rtc_5fcr_5falrae_1185',['RTC_CR_ALRAE',['../group___peripheral___registers___bits___definition.html#ga8a8cdeac61f06e4737800b64a901d584',1,'stm32f407xx_matlab.h']]], - ['rtc_5fcr_5falrae_5fmsk_1186',['RTC_CR_ALRAE_Msk',['../group___peripheral___registers___bits___definition.html#ga1adc6f86be463291c228b8a2bd3cfa40',1,'stm32f407xx_matlab.h']]], - ['rtc_5fcr_5falrae_5fpos_1187',['RTC_CR_ALRAE_Pos',['../group___peripheral___registers___bits___definition.html#ga54e3cfdf0409a6e26568fa59c9b5283b',1,'stm32f407xx_matlab.h']]], - ['rtc_5fcr_5falraie_1188',['RTC_CR_ALRAIE',['../group___peripheral___registers___bits___definition.html#ga9138f75267bd93f8de6738225217d583',1,'stm32f407xx_matlab.h']]], - ['rtc_5fcr_5falraie_5fmsk_1189',['RTC_CR_ALRAIE_Msk',['../group___peripheral___registers___bits___definition.html#ga0efcbd64f981117d73fe6d631c48f45e',1,'stm32f407xx_matlab.h']]], - ['rtc_5fcr_5falraie_5fpos_1190',['RTC_CR_ALRAIE_Pos',['../group___peripheral___registers___bits___definition.html#gacd69cebbc7fc4a81655a7e53a7284b70',1,'stm32f407xx_matlab.h']]], - ['rtc_5fcr_5falrbe_1191',['RTC_CR_ALRBE',['../group___peripheral___registers___bits___definition.html#ga17d0850002ed42742ff75a82dc4e8586',1,'stm32f407xx_matlab.h']]], - ['rtc_5fcr_5falrbe_5fmsk_1192',['RTC_CR_ALRBE_Msk',['../group___peripheral___registers___bits___definition.html#gaae811bd5a731a4d12d5fabc1c1701e7a',1,'stm32f407xx_matlab.h']]], - ['rtc_5fcr_5falrbe_5fpos_1193',['RTC_CR_ALRBE_Pos',['../group___peripheral___registers___bits___definition.html#gae534f6bb5933c05bc2b63aa70907bfb2',1,'stm32f407xx_matlab.h']]], - ['rtc_5fcr_5falrbie_1194',['RTC_CR_ALRBIE',['../group___peripheral___registers___bits___definition.html#gac6269c9dd5cee650024ede0b0c42e87d',1,'stm32f407xx_matlab.h']]], - ['rtc_5fcr_5falrbie_5fmsk_1195',['RTC_CR_ALRBIE_Msk',['../group___peripheral___registers___bits___definition.html#ga1e79f603f18cfbc266cc55162b739260',1,'stm32f407xx_matlab.h']]], - ['rtc_5fcr_5falrbie_5fpos_1196',['RTC_CR_ALRBIE_Pos',['../group___peripheral___registers___bits___definition.html#gad21245a52288246fbca5b954f38c65e8',1,'stm32f407xx_matlab.h']]], - ['rtc_5fcr_5fbck_1197',['RTC_CR_BCK',['../group___peripheral___registers___bits___definition.html#ga2a793580db48c66a98e44cbda6e0daef',1,'stm32f407xx_matlab.h']]], - ['rtc_5fcr_5fbkp_1198',['RTC_CR_BKP',['../group___peripheral___registers___bits___definition.html#ga0e7a474de1a01816bc9d9b6fa7272289',1,'stm32f407xx_matlab.h']]], - ['rtc_5fcr_5fbkp_5fmsk_1199',['RTC_CR_BKP_Msk',['../group___peripheral___registers___bits___definition.html#ga3675c7d64de46ab9f1cf279d7abaffe2',1,'stm32f407xx_matlab.h']]], - ['rtc_5fcr_5fbkp_5fpos_1200',['RTC_CR_BKP_Pos',['../group___peripheral___registers___bits___definition.html#gafd9f44a96fafedd6c89600a0a14fe87f',1,'stm32f407xx_matlab.h']]], - ['rtc_5fcr_5fbypshad_1201',['RTC_CR_BYPSHAD',['../group___peripheral___registers___bits___definition.html#ga34d50a3eff3364e6da4fefed9962a054',1,'stm32f407xx_matlab.h']]], - ['rtc_5fcr_5fbypshad_5fmsk_1202',['RTC_CR_BYPSHAD_Msk',['../group___peripheral___registers___bits___definition.html#ga93e690c1dc87dff6f36fea71cf6bb57c',1,'stm32f407xx_matlab.h']]], - ['rtc_5fcr_5fbypshad_5fpos_1203',['RTC_CR_BYPSHAD_Pos',['../group___peripheral___registers___bits___definition.html#gace008c8514db9131ae301e7577979130',1,'stm32f407xx_matlab.h']]], - ['rtc_5fcr_5fcoe_1204',['RTC_CR_COE',['../group___peripheral___registers___bits___definition.html#ga3cdfa862acfa6068b7ba847f77269d60',1,'stm32f407xx_matlab.h']]], - ['rtc_5fcr_5fcoe_5fmsk_1205',['RTC_CR_COE_Msk',['../group___peripheral___registers___bits___definition.html#ga35471924ed2a9a83b6af8bd8e2251f8b',1,'stm32f407xx_matlab.h']]], - ['rtc_5fcr_5fcoe_5fpos_1206',['RTC_CR_COE_Pos',['../group___peripheral___registers___bits___definition.html#ga12e2706cb9754f06d60cb87d3ec364ac',1,'stm32f407xx_matlab.h']]], - ['rtc_5fcr_5fcosel_1207',['RTC_CR_COSEL',['../group___peripheral___registers___bits___definition.html#ga197c587884b9c1dcb2970e9ec2589b41',1,'stm32f407xx_matlab.h']]], - ['rtc_5fcr_5fcosel_5fmsk_1208',['RTC_CR_COSEL_Msk',['../group___peripheral___registers___bits___definition.html#gad8dc824636e99382fcd50b39a6fce8dc',1,'stm32f407xx_matlab.h']]], - ['rtc_5fcr_5fcosel_5fpos_1209',['RTC_CR_COSEL_Pos',['../group___peripheral___registers___bits___definition.html#gac3ae962f1f8c748682a3136ea5ab76e1',1,'stm32f407xx_matlab.h']]], - ['rtc_5fcr_5fdce_1210',['RTC_CR_DCE',['../group___peripheral___registers___bits___definition.html#ga4ce7cb8b575142e125863d61ea4765ba',1,'stm32f407xx_matlab.h']]], - ['rtc_5fcr_5fdce_5fmsk_1211',['RTC_CR_DCE_Msk',['../group___peripheral___registers___bits___definition.html#ga005e60bfb5de91f5d9635d1e8e63f6d3',1,'stm32f407xx_matlab.h']]], - ['rtc_5fcr_5fdce_5fpos_1212',['RTC_CR_DCE_Pos',['../group___peripheral___registers___bits___definition.html#gab362e94b8e99714082eb0981045a28b7',1,'stm32f407xx_matlab.h']]], - ['rtc_5fcr_5ffmt_1213',['RTC_CR_FMT',['../group___peripheral___registers___bits___definition.html#gab2706e31a1bc8d95b682fe47611e0dd3',1,'stm32f407xx_matlab.h']]], - ['rtc_5fcr_5ffmt_5fmsk_1214',['RTC_CR_FMT_Msk',['../group___peripheral___registers___bits___definition.html#ga6634873135b509b3a483abcbd1e0f347',1,'stm32f407xx_matlab.h']]], - ['rtc_5fcr_5ffmt_5fpos_1215',['RTC_CR_FMT_Pos',['../group___peripheral___registers___bits___definition.html#ga262f18e12c214c9f172860b3a1234f0e',1,'stm32f407xx_matlab.h']]], - ['rtc_5fcr_5fosel_1216',['RTC_CR_OSEL',['../group___peripheral___registers___bits___definition.html#ga8f81115ef3fd366de73e84ab667d369b',1,'stm32f407xx_matlab.h']]], - ['rtc_5fcr_5fosel_5f0_1217',['RTC_CR_OSEL_0',['../group___peripheral___registers___bits___definition.html#gabe506838823e3b172a9ed4a3fec7321a',1,'stm32f407xx_matlab.h']]], - ['rtc_5fcr_5fosel_5f1_1218',['RTC_CR_OSEL_1',['../group___peripheral___registers___bits___definition.html#ga15fb33aaad62c71bbba2f96652eefb8c',1,'stm32f407xx_matlab.h']]], - ['rtc_5fcr_5fosel_5fmsk_1219',['RTC_CR_OSEL_Msk',['../group___peripheral___registers___bits___definition.html#gaeb684c910bd8e726378e0b51732f952f',1,'stm32f407xx_matlab.h']]], - ['rtc_5fcr_5fosel_5fpos_1220',['RTC_CR_OSEL_Pos',['../group___peripheral___registers___bits___definition.html#ga6513acc17cb4c17769ed5dcd03ebde8c',1,'stm32f407xx_matlab.h']]], - ['rtc_5fcr_5fpol_1221',['RTC_CR_POL',['../group___peripheral___registers___bits___definition.html#ga53f21b5adadbcc5eb255683d5decc9cb',1,'stm32f407xx_matlab.h']]], - ['rtc_5fcr_5fpol_5fmsk_1222',['RTC_CR_POL_Msk',['../group___peripheral___registers___bits___definition.html#ga717b2d78f96be49ba9d262f3a0eb09e4',1,'stm32f407xx_matlab.h']]], - ['rtc_5fcr_5fpol_5fpos_1223',['RTC_CR_POL_Pos',['../group___peripheral___registers___bits___definition.html#ga013304c1d6002a7c9ec57de637def511',1,'stm32f407xx_matlab.h']]], - ['rtc_5fcr_5frefckon_1224',['RTC_CR_REFCKON',['../group___peripheral___registers___bits___definition.html#ga646ef1071cacc2d30bbef5597c817021',1,'stm32f407xx_matlab.h']]], - ['rtc_5fcr_5frefckon_5fmsk_1225',['RTC_CR_REFCKON_Msk',['../group___peripheral___registers___bits___definition.html#gabd611d89bc17e379525602d5ea3a7d54',1,'stm32f407xx_matlab.h']]], - ['rtc_5fcr_5frefckon_5fpos_1226',['RTC_CR_REFCKON_Pos',['../group___peripheral___registers___bits___definition.html#gae970d1c321c777685111e4a4f70ce44c',1,'stm32f407xx_matlab.h']]], - ['rtc_5fcr_5fsub1h_1227',['RTC_CR_SUB1H',['../group___peripheral___registers___bits___definition.html#ga220cf6237eac208acc8ae4c55e0b5e6f',1,'stm32f407xx_matlab.h']]], - ['rtc_5fcr_5fsub1h_5fmsk_1228',['RTC_CR_SUB1H_Msk',['../group___peripheral___registers___bits___definition.html#ga62402c843252c70670b4b6c9ffec5880',1,'stm32f407xx_matlab.h']]], - ['rtc_5fcr_5fsub1h_5fpos_1229',['RTC_CR_SUB1H_Pos',['../group___peripheral___registers___bits___definition.html#ga7614f35a94291525f1dd8cc8f41f960f',1,'stm32f407xx_matlab.h']]], - ['rtc_5fcr_5ftse_1230',['RTC_CR_TSE',['../group___peripheral___registers___bits___definition.html#ga94fa98ca8cac9078b9bb82c89593d3c0',1,'stm32f407xx_matlab.h']]], - ['rtc_5fcr_5ftse_5fmsk_1231',['RTC_CR_TSE_Msk',['../group___peripheral___registers___bits___definition.html#gab2675d723ea5e54a4e6a7c7bd975efcc',1,'stm32f407xx_matlab.h']]], - ['rtc_5fcr_5ftse_5fpos_1232',['RTC_CR_TSE_Pos',['../group___peripheral___registers___bits___definition.html#gaf95c6afbdb29aa5241dc3e52d28ce884',1,'stm32f407xx_matlab.h']]], - ['rtc_5fcr_5ftsedge_1233',['RTC_CR_TSEDGE',['../group___peripheral___registers___bits___definition.html#gad076bde34be7d24f088fd2c003b7a7f7',1,'stm32f407xx_matlab.h']]], - ['rtc_5fcr_5ftsedge_5fmsk_1234',['RTC_CR_TSEDGE_Msk',['../group___peripheral___registers___bits___definition.html#ga3ea0c6b68ad8797d97693cbc7fe76d8e',1,'stm32f407xx_matlab.h']]], - ['rtc_5fcr_5ftsedge_5fpos_1235',['RTC_CR_TSEDGE_Pos',['../group___peripheral___registers___bits___definition.html#ga18a34610d5a2a22e66b027341ac6191b',1,'stm32f407xx_matlab.h']]], - ['rtc_5fcr_5ftsie_1236',['RTC_CR_TSIE',['../group___peripheral___registers___bits___definition.html#gaf376dffb9f2777ef275f23410e35600d',1,'stm32f407xx_matlab.h']]], - ['rtc_5fcr_5ftsie_5fmsk_1237',['RTC_CR_TSIE_Msk',['../group___peripheral___registers___bits___definition.html#ga4b81fdfb0dbd9719e0eee7b39450bb31',1,'stm32f407xx_matlab.h']]], - ['rtc_5fcr_5ftsie_5fpos_1238',['RTC_CR_TSIE_Pos',['../group___peripheral___registers___bits___definition.html#ga82db8f745799c761201a13235132a700',1,'stm32f407xx_matlab.h']]], - ['rtc_5fcr_5fwucksel_1239',['RTC_CR_WUCKSEL',['../group___peripheral___registers___bits___definition.html#ga54a2d55571417d9dfb05826b40d997b0',1,'stm32f407xx_matlab.h']]], - ['rtc_5fcr_5fwucksel_5f0_1240',['RTC_CR_WUCKSEL_0',['../group___peripheral___registers___bits___definition.html#ga6f03056e9aa78c133af90b60af72ba79',1,'stm32f407xx_matlab.h']]], - ['rtc_5fcr_5fwucksel_5f1_1241',['RTC_CR_WUCKSEL_1',['../group___peripheral___registers___bits___definition.html#ga360f7ccf7a89c5091f4affe6d1019215',1,'stm32f407xx_matlab.h']]], - ['rtc_5fcr_5fwucksel_5f2_1242',['RTC_CR_WUCKSEL_2',['../group___peripheral___registers___bits___definition.html#gad247ac722f6900744cdc16f8f45ed923',1,'stm32f407xx_matlab.h']]], - ['rtc_5fcr_5fwucksel_5fmsk_1243',['RTC_CR_WUCKSEL_Msk',['../group___peripheral___registers___bits___definition.html#gad1961b22823e4f592ac8d1733e079e2a',1,'stm32f407xx_matlab.h']]], - ['rtc_5fcr_5fwucksel_5fpos_1244',['RTC_CR_WUCKSEL_Pos',['../group___peripheral___registers___bits___definition.html#gad30da1c2029c23889c4dd29ee8fa7eea',1,'stm32f407xx_matlab.h']]], - ['rtc_5fcr_5fwute_1245',['RTC_CR_WUTE',['../group___peripheral___registers___bits___definition.html#ga061be0d3cdea721e5cb695cda0699bc3',1,'stm32f407xx_matlab.h']]], - ['rtc_5fcr_5fwute_5fmsk_1246',['RTC_CR_WUTE_Msk',['../group___peripheral___registers___bits___definition.html#gac5b45d595cd44d31a7f34609b6e7bf1a',1,'stm32f407xx_matlab.h']]], - ['rtc_5fcr_5fwute_5fpos_1247',['RTC_CR_WUTE_Pos',['../group___peripheral___registers___bits___definition.html#gaf919254119ed634798f3b936dc01e66d',1,'stm32f407xx_matlab.h']]], - ['rtc_5fcr_5fwutie_1248',['RTC_CR_WUTIE',['../group___peripheral___registers___bits___definition.html#ga5e0a1419830a16667cea4f6454913226',1,'stm32f407xx_matlab.h']]], - ['rtc_5fcr_5fwutie_5fmsk_1249',['RTC_CR_WUTIE_Msk',['../group___peripheral___registers___bits___definition.html#ga83d862c5a5e56813b86246d22821ac9b',1,'stm32f407xx_matlab.h']]], - ['rtc_5fcr_5fwutie_5fpos_1250',['RTC_CR_WUTIE_Pos',['../group___peripheral___registers___bits___definition.html#ga1432b0a0a031fe1143d153fe3073d7d2',1,'stm32f407xx_matlab.h']]], - ['rtc_5fdr_5fdt_1251',['RTC_DR_DT',['../group___peripheral___registers___bits___definition.html#ga52e40cec8161ee20176d92d547fef350',1,'stm32f407xx_matlab.h']]], - ['rtc_5fdr_5fdt_5f0_1252',['RTC_DR_DT_0',['../group___peripheral___registers___bits___definition.html#ga8823ee9be7a191912aeef8252517b8a6',1,'stm32f407xx_matlab.h']]], - ['rtc_5fdr_5fdt_5f1_1253',['RTC_DR_DT_1',['../group___peripheral___registers___bits___definition.html#ga546b218e45c1297e39a586204268cf9d',1,'stm32f407xx_matlab.h']]], - ['rtc_5fdr_5fdt_5fmsk_1254',['RTC_DR_DT_Msk',['../group___peripheral___registers___bits___definition.html#ga47c3834615b1c186a5122c0735e03e09',1,'stm32f407xx_matlab.h']]], - ['rtc_5fdr_5fdt_5fpos_1255',['RTC_DR_DT_Pos',['../group___peripheral___registers___bits___definition.html#gab12b2bb2b80f5a17c4d6717708cf9d5a',1,'stm32f407xx_matlab.h']]], - ['rtc_5fdr_5fdu_1256',['RTC_DR_DU',['../group___peripheral___registers___bits___definition.html#gaba04cbc99cf442c7e6155bef625c5663',1,'stm32f407xx_matlab.h']]], - ['rtc_5fdr_5fdu_5f0_1257',['RTC_DR_DU_0',['../group___peripheral___registers___bits___definition.html#ga0ffd9b610a0ba3f1caad707ff2fb0a3f',1,'stm32f407xx_matlab.h']]], - ['rtc_5fdr_5fdu_5f1_1258',['RTC_DR_DU_1',['../group___peripheral___registers___bits___definition.html#ga79b5d9f674be2ecf85c964da6ac0a2a4',1,'stm32f407xx_matlab.h']]], - ['rtc_5fdr_5fdu_5f2_1259',['RTC_DR_DU_2',['../group___peripheral___registers___bits___definition.html#ga1668f84ec4ddec10f6bcff65983df05b',1,'stm32f407xx_matlab.h']]], - ['rtc_5fdr_5fdu_5f3_1260',['RTC_DR_DU_3',['../group___peripheral___registers___bits___definition.html#gad54e249241aebdda778618f35dce9f66',1,'stm32f407xx_matlab.h']]], - ['rtc_5fdr_5fdu_5fmsk_1261',['RTC_DR_DU_Msk',['../group___peripheral___registers___bits___definition.html#ga4549c0127eff71ac5e1e3b7ef07bf158',1,'stm32f407xx_matlab.h']]], - ['rtc_5fdr_5fdu_5fpos_1262',['RTC_DR_DU_Pos',['../group___peripheral___registers___bits___definition.html#ga4689a554a699f3df0a5939efdbebb94d',1,'stm32f407xx_matlab.h']]], - ['rtc_5fdr_5fmt_1263',['RTC_DR_MT',['../group___peripheral___registers___bits___definition.html#ga26f0d3ce1c6c6785bd8fbae556f68b31',1,'stm32f407xx_matlab.h']]], - ['rtc_5fdr_5fmt_5fmsk_1264',['RTC_DR_MT_Msk',['../group___peripheral___registers___bits___definition.html#ga5358d94c842b122b8bd260a855afb483',1,'stm32f407xx_matlab.h']]], - ['rtc_5fdr_5fmt_5fpos_1265',['RTC_DR_MT_Pos',['../group___peripheral___registers___bits___definition.html#ga1d26f621d89bd024ff988b5ecab316ab',1,'stm32f407xx_matlab.h']]], - ['rtc_5fdr_5fmu_1266',['RTC_DR_MU',['../group___peripheral___registers___bits___definition.html#gac9221f60ccf3581f3c543fdedddf4372',1,'stm32f407xx_matlab.h']]], - ['rtc_5fdr_5fmu_5f0_1267',['RTC_DR_MU_0',['../group___peripheral___registers___bits___definition.html#ga54f64678df9fe08a2afd732c275ae7a0',1,'stm32f407xx_matlab.h']]], - ['rtc_5fdr_5fmu_5f1_1268',['RTC_DR_MU_1',['../group___peripheral___registers___bits___definition.html#gac7845ded502c4cc9faeeb6215955f6f1',1,'stm32f407xx_matlab.h']]], - ['rtc_5fdr_5fmu_5f2_1269',['RTC_DR_MU_2',['../group___peripheral___registers___bits___definition.html#ga47a14479cfe6791d300b9a556d158abe',1,'stm32f407xx_matlab.h']]], - ['rtc_5fdr_5fmu_5f3_1270',['RTC_DR_MU_3',['../group___peripheral___registers___bits___definition.html#ga2a420b221dec229c053295c44bcac1b1',1,'stm32f407xx_matlab.h']]], - ['rtc_5fdr_5fmu_5fmsk_1271',['RTC_DR_MU_Msk',['../group___peripheral___registers___bits___definition.html#ga614964ed52cb7da4ee76a0f3d16e57bb',1,'stm32f407xx_matlab.h']]], - ['rtc_5fdr_5fmu_5fpos_1272',['RTC_DR_MU_Pos',['../group___peripheral___registers___bits___definition.html#ga5781bd4d99f08d25b2741a43c0e694a4',1,'stm32f407xx_matlab.h']]], - ['rtc_5fdr_5fwdu_1273',['RTC_DR_WDU',['../group___peripheral___registers___bits___definition.html#ga6f46c349f75a31973e094729fe96543f',1,'stm32f407xx_matlab.h']]], - ['rtc_5fdr_5fwdu_5f0_1274',['RTC_DR_WDU_0',['../group___peripheral___registers___bits___definition.html#ga30cb803b191670a41aea89a91e53fe61',1,'stm32f407xx_matlab.h']]], - ['rtc_5fdr_5fwdu_5f1_1275',['RTC_DR_WDU_1',['../group___peripheral___registers___bits___definition.html#gabd26d3601bf8b119af8f96a65a1de60e',1,'stm32f407xx_matlab.h']]], - ['rtc_5fdr_5fwdu_5f2_1276',['RTC_DR_WDU_2',['../group___peripheral___registers___bits___definition.html#ga77e907e5efced7628e9933e7cfb4cac6',1,'stm32f407xx_matlab.h']]], - ['rtc_5fdr_5fwdu_5fmsk_1277',['RTC_DR_WDU_Msk',['../group___peripheral___registers___bits___definition.html#gacaa60c7147ae02cf5d6e2ee2c87fb5e7',1,'stm32f407xx_matlab.h']]], - ['rtc_5fdr_5fwdu_5fpos_1278',['RTC_DR_WDU_Pos',['../group___peripheral___registers___bits___definition.html#ga751a29a9ead0d70b6104bd366b7ab6af',1,'stm32f407xx_matlab.h']]], - ['rtc_5fdr_5fyt_1279',['RTC_DR_YT',['../group___peripheral___registers___bits___definition.html#ga14d55b6d841825ec65736e08c09b1d83',1,'stm32f407xx_matlab.h']]], - ['rtc_5fdr_5fyt_5f0_1280',['RTC_DR_YT_0',['../group___peripheral___registers___bits___definition.html#ga4a733698a85cc8f26d346ec8c61c7937',1,'stm32f407xx_matlab.h']]], - ['rtc_5fdr_5fyt_5f1_1281',['RTC_DR_YT_1',['../group___peripheral___registers___bits___definition.html#gaa48c7c9f31a74b6d3b04443ce0414ce9',1,'stm32f407xx_matlab.h']]], - ['rtc_5fdr_5fyt_5f2_1282',['RTC_DR_YT_2',['../group___peripheral___registers___bits___definition.html#ga5c15cd22daf2ef6f9ea6f7341897a435',1,'stm32f407xx_matlab.h']]], - ['rtc_5fdr_5fyt_5f3_1283',['RTC_DR_YT_3',['../group___peripheral___registers___bits___definition.html#ga4e7cf7875d489f89d949178e0294d555',1,'stm32f407xx_matlab.h']]], - ['rtc_5fdr_5fyt_5fmsk_1284',['RTC_DR_YT_Msk',['../group___peripheral___registers___bits___definition.html#ga0ad13d2dbed87fd51194b4d7b080f759',1,'stm32f407xx_matlab.h']]], - ['rtc_5fdr_5fyt_5fpos_1285',['RTC_DR_YT_Pos',['../group___peripheral___registers___bits___definition.html#gaee7ed9c50764bdf02c200c9acf963609',1,'stm32f407xx_matlab.h']]], - ['rtc_5fdr_5fyu_1286',['RTC_DR_YU',['../group___peripheral___registers___bits___definition.html#gafd1bdc8fad3fdeb14058c9158f39ae9e',1,'stm32f407xx_matlab.h']]], - ['rtc_5fdr_5fyu_5f0_1287',['RTC_DR_YU_0',['../group___peripheral___registers___bits___definition.html#gaeda03e9857e9009b6212df5f97a5d09f',1,'stm32f407xx_matlab.h']]], - ['rtc_5fdr_5fyu_5f1_1288',['RTC_DR_YU_1',['../group___peripheral___registers___bits___definition.html#gadb0b5f7684e31cb1665a848b91601249',1,'stm32f407xx_matlab.h']]], - ['rtc_5fdr_5fyu_5f2_1289',['RTC_DR_YU_2',['../group___peripheral___registers___bits___definition.html#ga01f200469dbc8159adc3b4f25375b601',1,'stm32f407xx_matlab.h']]], - ['rtc_5fdr_5fyu_5f3_1290',['RTC_DR_YU_3',['../group___peripheral___registers___bits___definition.html#ga592372ccddc93b10e81ed705c9c0f9bc',1,'stm32f407xx_matlab.h']]], - ['rtc_5fdr_5fyu_5fmsk_1291',['RTC_DR_YU_Msk',['../group___peripheral___registers___bits___definition.html#ga261de093e10c99df510d650bea7b65bb',1,'stm32f407xx_matlab.h']]], - ['rtc_5fdr_5fyu_5fpos_1292',['RTC_DR_YU_Pos',['../group___peripheral___registers___bits___definition.html#gaf2a117731b1eddef15cf9fa4f3c7a062',1,'stm32f407xx_matlab.h']]], - ['rtc_5fisr_5falraf_1293',['RTC_ISR_ALRAF',['../group___peripheral___registers___bits___definition.html#ga96605e50a347507b7f274e9cd894a02c',1,'stm32f407xx_matlab.h']]], - ['rtc_5fisr_5falraf_5fmsk_1294',['RTC_ISR_ALRAF_Msk',['../group___peripheral___registers___bits___definition.html#gaf5aeb3a57686a3bca74ebce43559161e',1,'stm32f407xx_matlab.h']]], - ['rtc_5fisr_5falraf_5fpos_1295',['RTC_ISR_ALRAF_Pos',['../group___peripheral___registers___bits___definition.html#ga4bbb887fab178f2ad6c26fe28bd16cd6',1,'stm32f407xx_matlab.h']]], - ['rtc_5fisr_5falrawf_1296',['RTC_ISR_ALRAWF',['../group___peripheral___registers___bits___definition.html#ga4d420b5c3f8623cf1116d42fa164be7e',1,'stm32f407xx_matlab.h']]], - ['rtc_5fisr_5falrawf_5fmsk_1297',['RTC_ISR_ALRAWF_Msk',['../group___peripheral___registers___bits___definition.html#gac4d96dae4fdd343fe6e9ebc7c5f7d80d',1,'stm32f407xx_matlab.h']]], - ['rtc_5fisr_5falrawf_5fpos_1298',['RTC_ISR_ALRAWF_Pos',['../group___peripheral___registers___bits___definition.html#gab296f795ad4fa25ad0cb3c92967f9565',1,'stm32f407xx_matlab.h']]], - ['rtc_5fisr_5falrbf_1299',['RTC_ISR_ALRBF',['../group___peripheral___registers___bits___definition.html#ga7976972a5fc6705fede85536520367d6',1,'stm32f407xx_matlab.h']]], - ['rtc_5fisr_5falrbf_5fmsk_1300',['RTC_ISR_ALRBF_Msk',['../group___peripheral___registers___bits___definition.html#gac80e30a64a34bd547229f68b76d63a87',1,'stm32f407xx_matlab.h']]], - ['rtc_5fisr_5falrbf_5fpos_1301',['RTC_ISR_ALRBF_Pos',['../group___peripheral___registers___bits___definition.html#ga4891bf442ab59fa4488bc0ed308c56c2',1,'stm32f407xx_matlab.h']]], - ['rtc_5fisr_5falrbwf_1302',['RTC_ISR_ALRBWF',['../group___peripheral___registers___bits___definition.html#ga5a0c34bff6dc9fce29e2be35d32d9d05',1,'stm32f407xx_matlab.h']]], - ['rtc_5fisr_5falrbwf_5fmsk_1303',['RTC_ISR_ALRBWF_Msk',['../group___peripheral___registers___bits___definition.html#ga6cf9f3b0159c2f29749babdc55ef1a1b',1,'stm32f407xx_matlab.h']]], - ['rtc_5fisr_5falrbwf_5fpos_1304',['RTC_ISR_ALRBWF_Pos',['../group___peripheral___registers___bits___definition.html#ga011f9bc215e39c91f33f0472e0b59643',1,'stm32f407xx_matlab.h']]], - ['rtc_5fisr_5finit_1305',['RTC_ISR_INIT',['../group___peripheral___registers___bits___definition.html#gae0eb2f998cd3e7325974347cb2a3d25a',1,'stm32f407xx_matlab.h']]], - ['rtc_5fisr_5finit_5fmsk_1306',['RTC_ISR_INIT_Msk',['../group___peripheral___registers___bits___definition.html#gae5e864e670cc4643c1e65b21da150c74',1,'stm32f407xx_matlab.h']]], - ['rtc_5fisr_5finit_5fpos_1307',['RTC_ISR_INIT_Pos',['../group___peripheral___registers___bits___definition.html#gab9a0e0b639b59be3c662267184bddf69',1,'stm32f407xx_matlab.h']]], - ['rtc_5fisr_5finitf_1308',['RTC_ISR_INITF',['../group___peripheral___registers___bits___definition.html#gab16dcc6973c611e087030cdb15203972',1,'stm32f407xx_matlab.h']]], - ['rtc_5fisr_5finitf_5fmsk_1309',['RTC_ISR_INITF_Msk',['../group___peripheral___registers___bits___definition.html#ga6a29ce1f3e261024726679c17f42a9b1',1,'stm32f407xx_matlab.h']]], - ['rtc_5fisr_5finitf_5fpos_1310',['RTC_ISR_INITF_Pos',['../group___peripheral___registers___bits___definition.html#ga601564e925eefdbde3aafdcbf0a978c5',1,'stm32f407xx_matlab.h']]], - ['rtc_5fisr_5finits_1311',['RTC_ISR_INITS',['../group___peripheral___registers___bits___definition.html#ga7b229bace5ba0c0b48bfeb5efc445292',1,'stm32f407xx_matlab.h']]], - ['rtc_5fisr_5finits_5fmsk_1312',['RTC_ISR_INITS_Msk',['../group___peripheral___registers___bits___definition.html#ga25131777233cef2dfffdc178667559e4',1,'stm32f407xx_matlab.h']]], - ['rtc_5fisr_5finits_5fpos_1313',['RTC_ISR_INITS_Pos',['../group___peripheral___registers___bits___definition.html#gae6f7e11d89c6480d68013ce7c0478045',1,'stm32f407xx_matlab.h']]], - ['rtc_5fisr_5frecalpf_1314',['RTC_ISR_RECALPF',['../group___peripheral___registers___bits___definition.html#ga05189137cfd0e73903d9b70d071656b9',1,'stm32f407xx_matlab.h']]], - ['rtc_5fisr_5frecalpf_5fmsk_1315',['RTC_ISR_RECALPF_Msk',['../group___peripheral___registers___bits___definition.html#ga8ab18f49ac6ab32322ebb58131a456ea',1,'stm32f407xx_matlab.h']]], - ['rtc_5fisr_5frecalpf_5fpos_1316',['RTC_ISR_RECALPF_Pos',['../group___peripheral___registers___bits___definition.html#gaa59397ca25b1fc9fbc43cfca986c14e4',1,'stm32f407xx_matlab.h']]], - ['rtc_5fisr_5frsf_1317',['RTC_ISR_RSF',['../group___peripheral___registers___bits___definition.html#ga9bd683e789841f7d3f138709ffdbfbf8',1,'stm32f407xx_matlab.h']]], - ['rtc_5fisr_5frsf_5fmsk_1318',['RTC_ISR_RSF_Msk',['../group___peripheral___registers___bits___definition.html#ga3f87ecd7737391a4ff0c236a17dbfd32',1,'stm32f407xx_matlab.h']]], - ['rtc_5fisr_5frsf_5fpos_1319',['RTC_ISR_RSF_Pos',['../group___peripheral___registers___bits___definition.html#ga8dd0bed53ed3cc1bbc70efa82bcac846',1,'stm32f407xx_matlab.h']]], - ['rtc_5fisr_5fshpf_1320',['RTC_ISR_SHPF',['../group___peripheral___registers___bits___definition.html#ga1c4536a874336778ac11109f14573eb9',1,'stm32f407xx_matlab.h']]], - ['rtc_5fisr_5fshpf_5fmsk_1321',['RTC_ISR_SHPF_Msk',['../group___peripheral___registers___bits___definition.html#ga36cc41c7b626c5047f97fac12337395d',1,'stm32f407xx_matlab.h']]], - ['rtc_5fisr_5fshpf_5fpos_1322',['RTC_ISR_SHPF_Pos',['../group___peripheral___registers___bits___definition.html#gad4312f68d569942ac8d1b6abfb0f5aad',1,'stm32f407xx_matlab.h']]], - ['rtc_5fisr_5ftamp1f_1323',['RTC_ISR_TAMP1F',['../group___peripheral___registers___bits___definition.html#gae738b22f6a8123026921a1d14f9547c0',1,'stm32f407xx_matlab.h']]], - ['rtc_5fisr_5ftamp1f_5fmsk_1324',['RTC_ISR_TAMP1F_Msk',['../group___peripheral___registers___bits___definition.html#ga84bbb84dba6aef26a16b2410c3a3ec5d',1,'stm32f407xx_matlab.h']]], - ['rtc_5fisr_5ftamp1f_5fpos_1325',['RTC_ISR_TAMP1F_Pos',['../group___peripheral___registers___bits___definition.html#gaf18fa672ae72db52c7a6c5a2658a5190',1,'stm32f407xx_matlab.h']]], - ['rtc_5fisr_5ftamp2f_1326',['RTC_ISR_TAMP2F',['../group___peripheral___registers___bits___definition.html#gabdb176578e53b2d8e24a94c8d0212845',1,'stm32f407xx_matlab.h']]], - ['rtc_5fisr_5ftamp2f_5fmsk_1327',['RTC_ISR_TAMP2F_Msk',['../group___peripheral___registers___bits___definition.html#ga436cbba9b17ad91735e876596c8a6914',1,'stm32f407xx_matlab.h']]], - ['rtc_5fisr_5ftamp2f_5fpos_1328',['RTC_ISR_TAMP2F_Pos',['../group___peripheral___registers___bits___definition.html#ga0347e70fa9f25a6a52d3ceac1713ccee',1,'stm32f407xx_matlab.h']]], - ['rtc_5fisr_5ftsf_1329',['RTC_ISR_TSF',['../group___peripheral___registers___bits___definition.html#ga68c0a60dbfc5f1570a48afe450395484',1,'stm32f407xx_matlab.h']]], - ['rtc_5fisr_5ftsf_5fmsk_1330',['RTC_ISR_TSF_Msk',['../group___peripheral___registers___bits___definition.html#ga8f5151d79a2761d423ddbc0b6c3cca1f',1,'stm32f407xx_matlab.h']]], - ['rtc_5fisr_5ftsf_5fpos_1331',['RTC_ISR_TSF_Pos',['../group___peripheral___registers___bits___definition.html#ga09bb6ceebab0b76cd2121816e787749a',1,'stm32f407xx_matlab.h']]], - ['rtc_5fisr_5ftsovf_1332',['RTC_ISR_TSOVF',['../group___peripheral___registers___bits___definition.html#ga766c238f964072decba204c7fce850ff',1,'stm32f407xx_matlab.h']]], - ['rtc_5fisr_5ftsovf_5fmsk_1333',['RTC_ISR_TSOVF_Msk',['../group___peripheral___registers___bits___definition.html#ga1a44c6cf950526be3f768c9175e3e62e',1,'stm32f407xx_matlab.h']]], - ['rtc_5fisr_5ftsovf_5fpos_1334',['RTC_ISR_TSOVF_Pos',['../group___peripheral___registers___bits___definition.html#gaa38f2ee43244798276792a0c5a64f41e',1,'stm32f407xx_matlab.h']]], - ['rtc_5fisr_5fwutf_1335',['RTC_ISR_WUTF',['../group___peripheral___registers___bits___definition.html#ga4eb5960300a402210e5378d78ce22766',1,'stm32f407xx_matlab.h']]], - ['rtc_5fisr_5fwutf_5fmsk_1336',['RTC_ISR_WUTF_Msk',['../group___peripheral___registers___bits___definition.html#ga53360cc2baf2a2142289493b2a16c372',1,'stm32f407xx_matlab.h']]], - ['rtc_5fisr_5fwutf_5fpos_1337',['RTC_ISR_WUTF_Pos',['../group___peripheral___registers___bits___definition.html#gae6c5050a881336d0a8710d096fe4b01a',1,'stm32f407xx_matlab.h']]], - ['rtc_5fisr_5fwutwf_1338',['RTC_ISR_WUTWF',['../group___peripheral___registers___bits___definition.html#ga0e753321211e19bc48736fe0d30a7f40',1,'stm32f407xx_matlab.h']]], - ['rtc_5fisr_5fwutwf_5fmsk_1339',['RTC_ISR_WUTWF_Msk',['../group___peripheral___registers___bits___definition.html#ga673f0ff6267142391ca1d37289b305f2',1,'stm32f407xx_matlab.h']]], - ['rtc_5fisr_5fwutwf_5fpos_1340',['RTC_ISR_WUTWF_Pos',['../group___peripheral___registers___bits___definition.html#ga8d75a29fa323d93d3d0bb2cb60b24474',1,'stm32f407xx_matlab.h']]], - ['rtc_5fprer_5fprediv_5fa_1341',['RTC_PRER_PREDIV_A',['../group___peripheral___registers___bits___definition.html#gad248dca1e9532ba31f98d3ec9d2f8711',1,'stm32f407xx_matlab.h']]], - ['rtc_5fprer_5fprediv_5fa_5fmsk_1342',['RTC_PRER_PREDIV_A_Msk',['../group___peripheral___registers___bits___definition.html#ga2f883861bb963a097885c5773f3c0b15',1,'stm32f407xx_matlab.h']]], - ['rtc_5fprer_5fprediv_5fa_5fpos_1343',['RTC_PRER_PREDIV_A_Pos',['../group___peripheral___registers___bits___definition.html#gae8240c029696ad91531c3fec1ef1e7fe',1,'stm32f407xx_matlab.h']]], - ['rtc_5fprer_5fprediv_5fs_1344',['RTC_PRER_PREDIV_S',['../group___peripheral___registers___bits___definition.html#ga17bbd4e569a76446df089752cb41b1cb',1,'stm32f407xx_matlab.h']]], - ['rtc_5fprer_5fprediv_5fs_5fmsk_1345',['RTC_PRER_PREDIV_S_Msk',['../group___peripheral___registers___bits___definition.html#ga776acde6c1789c37371eb440492825ab',1,'stm32f407xx_matlab.h']]], - ['rtc_5fprer_5fprediv_5fs_5fpos_1346',['RTC_PRER_PREDIV_S_Pos',['../group___peripheral___registers___bits___definition.html#ga234f46098c91b34aa12502d70cdb93bf',1,'stm32f407xx_matlab.h']]], - ['rtc_5fshiftr_5fadd1s_1347',['RTC_SHIFTR_ADD1S',['../group___peripheral___registers___bits___definition.html#ga8fee932563d21382db9ecad458356af2',1,'stm32f407xx_matlab.h']]], - ['rtc_5fshiftr_5fadd1s_5fmsk_1348',['RTC_SHIFTR_ADD1S_Msk',['../group___peripheral___registers___bits___definition.html#ga145edd31d622a96121168d7f54af1f63',1,'stm32f407xx_matlab.h']]], - ['rtc_5fshiftr_5fadd1s_5fpos_1349',['RTC_SHIFTR_ADD1S_Pos',['../group___peripheral___registers___bits___definition.html#gab0fdeb64a850c9840a1c140203e61d2f',1,'stm32f407xx_matlab.h']]], - ['rtc_5fshiftr_5fsubfs_1350',['RTC_SHIFTR_SUBFS',['../group___peripheral___registers___bits___definition.html#ga6131eb8c293b98bc5a6c7a4bb1920450',1,'stm32f407xx_matlab.h']]], - ['rtc_5fshiftr_5fsubfs_5fmsk_1351',['RTC_SHIFTR_SUBFS_Msk',['../group___peripheral___registers___bits___definition.html#ga58c15ddd7f663060a1e540ded10aab86',1,'stm32f407xx_matlab.h']]], - ['rtc_5fshiftr_5fsubfs_5fpos_1352',['RTC_SHIFTR_SUBFS_Pos',['../group___peripheral___registers___bits___definition.html#ga043d4cba6c3d17ce136ed8e8fc6ae318',1,'stm32f407xx_matlab.h']]], - ['rtc_5fssr_5fss_1353',['RTC_SSR_SS',['../group___peripheral___registers___bits___definition.html#ga3881f27b6c7a5c7609b1393682144aed',1,'stm32f407xx_matlab.h']]], - ['rtc_5fssr_5fss_5fmsk_1354',['RTC_SSR_SS_Msk',['../group___peripheral___registers___bits___definition.html#ga7e04530ca01c9863f847c09f51f64304',1,'stm32f407xx_matlab.h']]], - ['rtc_5fssr_5fss_5fpos_1355',['RTC_SSR_SS_Pos',['../group___peripheral___registers___bits___definition.html#gaf8cf2c5e2058a406fcb12ef8263f4bf7',1,'stm32f407xx_matlab.h']]], - ['rtc_5ftafcr_5falarmouttype_1356',['RTC_TAFCR_ALARMOUTTYPE',['../group___peripheral___registers___bits___definition.html#ga8d9515fd74e3bcf03f4e62d8c7e1b070',1,'stm32f407xx_matlab.h']]], - ['rtc_5ftafcr_5falarmouttype_5fmsk_1357',['RTC_TAFCR_ALARMOUTTYPE_Msk',['../group___peripheral___registers___bits___definition.html#ga070badc7e2d642aeff89371370f5cb7d',1,'stm32f407xx_matlab.h']]], - ['rtc_5ftafcr_5falarmouttype_5fpos_1358',['RTC_TAFCR_ALARMOUTTYPE_Pos',['../group___peripheral___registers___bits___definition.html#ga288c98bc30ac4f55ee038b66deef21eb',1,'stm32f407xx_matlab.h']]], - ['rtc_5ftafcr_5ftamp1e_1359',['RTC_TAFCR_TAMP1E',['../group___peripheral___registers___bits___definition.html#gaa68c195cf709d18cd426560302b97852',1,'stm32f407xx_matlab.h']]], - ['rtc_5ftafcr_5ftamp1e_5fmsk_1360',['RTC_TAFCR_TAMP1E_Msk',['../group___peripheral___registers___bits___definition.html#gad775a4255d5762b8871f79826d48e5cb',1,'stm32f407xx_matlab.h']]], - ['rtc_5ftafcr_5ftamp1e_5fpos_1361',['RTC_TAFCR_TAMP1E_Pos',['../group___peripheral___registers___bits___definition.html#gae207869690b2ec429b0422006ecae9ee',1,'stm32f407xx_matlab.h']]], - ['rtc_5ftafcr_5ftamp1insel_1362',['RTC_TAFCR_TAMP1INSEL',['../group___peripheral___registers___bits___definition.html#ga5934e2b2ada22a92862a9ea5356a2665',1,'stm32f407xx_matlab.h']]], - ['rtc_5ftafcr_5ftamp1insel_5fmsk_1363',['RTC_TAFCR_TAMP1INSEL_Msk',['../group___peripheral___registers___bits___definition.html#ga6032dc793590fd715ea61340429b1848',1,'stm32f407xx_matlab.h']]], - ['rtc_5ftafcr_5ftamp1insel_5fpos_1364',['RTC_TAFCR_TAMP1INSEL_Pos',['../group___peripheral___registers___bits___definition.html#ga0b8c154291563140f9ab1b938b20e39a',1,'stm32f407xx_matlab.h']]], - ['rtc_5ftafcr_5ftamp1trg_1365',['RTC_TAFCR_TAMP1TRG',['../group___peripheral___registers___bits___definition.html#ga76f85925873bcd3f795417053bfc5f33',1,'stm32f407xx_matlab.h']]], - ['rtc_5ftafcr_5ftamp1trg_5fmsk_1366',['RTC_TAFCR_TAMP1TRG_Msk',['../group___peripheral___registers___bits___definition.html#ga81d7cfb15da3ed9689baa85471ff2f02',1,'stm32f407xx_matlab.h']]], - ['rtc_5ftafcr_5ftamp1trg_5fpos_1367',['RTC_TAFCR_TAMP1TRG_Pos',['../group___peripheral___registers___bits___definition.html#ga6904e60d49c241ecb2347a3da9df8054',1,'stm32f407xx_matlab.h']]], - ['rtc_5ftafcr_5ftamp2e_1368',['RTC_TAFCR_TAMP2E',['../group___peripheral___registers___bits___definition.html#ga7e98a0062ef81bcbc790a8d77720a61c',1,'stm32f407xx_matlab.h']]], - ['rtc_5ftafcr_5ftamp2e_5fmsk_1369',['RTC_TAFCR_TAMP2E_Msk',['../group___peripheral___registers___bits___definition.html#gad539217084c83e84eb27ec76eca40152',1,'stm32f407xx_matlab.h']]], - ['rtc_5ftafcr_5ftamp2e_5fpos_1370',['RTC_TAFCR_TAMP2E_Pos',['../group___peripheral___registers___bits___definition.html#gac46ab34c29b3dfa1dc0c3866cb52ce9f',1,'stm32f407xx_matlab.h']]], - ['rtc_5ftafcr_5ftamp2trg_1371',['RTC_TAFCR_TAMP2TRG',['../group___peripheral___registers___bits___definition.html#gad2c4d227971b56e3160c71b7479c769d',1,'stm32f407xx_matlab.h']]], - ['rtc_5ftafcr_5ftamp2trg_5fmsk_1372',['RTC_TAFCR_TAMP2TRG_Msk',['../group___peripheral___registers___bits___definition.html#ga92f7e43c7127ffa0dac5c94233360852',1,'stm32f407xx_matlab.h']]], - ['rtc_5ftafcr_5ftamp2trg_5fpos_1373',['RTC_TAFCR_TAMP2TRG_Pos',['../group___peripheral___registers___bits___definition.html#ga5d0e27811bd76fcf94c2f802df2a742f',1,'stm32f407xx_matlab.h']]], - ['rtc_5ftafcr_5ftampflt_1374',['RTC_TAFCR_TAMPFLT',['../group___peripheral___registers___bits___definition.html#gab1cb37c43747c779f7db2842a2582e67',1,'stm32f407xx_matlab.h']]], - ['rtc_5ftafcr_5ftampflt_5f0_1375',['RTC_TAFCR_TAMPFLT_0',['../group___peripheral___registers___bits___definition.html#gaa356fb5db5ab398728afef0ae39214c4',1,'stm32f407xx_matlab.h']]], - ['rtc_5ftafcr_5ftampflt_5f1_1376',['RTC_TAFCR_TAMPFLT_1',['../group___peripheral___registers___bits___definition.html#ga472efa1bd3c9462cbd058d73a7d6525e',1,'stm32f407xx_matlab.h']]], - ['rtc_5ftafcr_5ftampflt_5fmsk_1377',['RTC_TAFCR_TAMPFLT_Msk',['../group___peripheral___registers___bits___definition.html#gacf978c259714ae9072766be91c8d982c',1,'stm32f407xx_matlab.h']]], - ['rtc_5ftafcr_5ftampflt_5fpos_1378',['RTC_TAFCR_TAMPFLT_Pos',['../group___peripheral___registers___bits___definition.html#ga978ec86db46d77d83e1627a563e5a622',1,'stm32f407xx_matlab.h']]], - ['rtc_5ftafcr_5ftampfreq_1379',['RTC_TAFCR_TAMPFREQ',['../group___peripheral___registers___bits___definition.html#ga8ad84446486b8c9f640fa54d50ecc0e1',1,'stm32f407xx_matlab.h']]], - ['rtc_5ftafcr_5ftampfreq_5f0_1380',['RTC_TAFCR_TAMPFREQ_0',['../group___peripheral___registers___bits___definition.html#ga54e7f69e04759d1b0667e56830a6f2ea',1,'stm32f407xx_matlab.h']]], - ['rtc_5ftafcr_5ftampfreq_5f1_1381',['RTC_TAFCR_TAMPFREQ_1',['../group___peripheral___registers___bits___definition.html#gabb533067640fcf87ad77027ce936e9b7',1,'stm32f407xx_matlab.h']]], - ['rtc_5ftafcr_5ftampfreq_5f2_1382',['RTC_TAFCR_TAMPFREQ_2',['../group___peripheral___registers___bits___definition.html#gaf532e727bfe6c7fc7822d15f9436e1b5',1,'stm32f407xx_matlab.h']]], - ['rtc_5ftafcr_5ftampfreq_5fmsk_1383',['RTC_TAFCR_TAMPFREQ_Msk',['../group___peripheral___registers___bits___definition.html#ga2e169834a26329219aa2271781756dfb',1,'stm32f407xx_matlab.h']]], - ['rtc_5ftafcr_5ftampfreq_5fpos_1384',['RTC_TAFCR_TAMPFREQ_Pos',['../group___peripheral___registers___bits___definition.html#ga487bd3ad7900df341c4fe63fb409d2bd',1,'stm32f407xx_matlab.h']]], - ['rtc_5ftafcr_5ftampie_1385',['RTC_TAFCR_TAMPIE',['../group___peripheral___registers___bits___definition.html#gaa0fb33b24d2ebc19e7fe52f0661a3085',1,'stm32f407xx_matlab.h']]], - ['rtc_5ftafcr_5ftampie_5fmsk_1386',['RTC_TAFCR_TAMPIE_Msk',['../group___peripheral___registers___bits___definition.html#ga028b4854bd356dc30a8b02ab5ed1eb48',1,'stm32f407xx_matlab.h']]], - ['rtc_5ftafcr_5ftampie_5fpos_1387',['RTC_TAFCR_TAMPIE_Pos',['../group___peripheral___registers___bits___definition.html#ga9b58fa23a2a04d3a4a46d42fa4673ec5',1,'stm32f407xx_matlab.h']]], - ['rtc_5ftafcr_5ftampinsel_1388',['RTC_TAFCR_TAMPINSEL',['../group___peripheral___registers___bits___definition.html#ga989cde7332b2ec0b3934cb909514938d',1,'stm32f407xx_matlab.h']]], - ['rtc_5ftafcr_5ftampprch_1389',['RTC_TAFCR_TAMPPRCH',['../group___peripheral___registers___bits___definition.html#ga7b73d2b8da78967a6f594dbffe58c222',1,'stm32f407xx_matlab.h']]], - ['rtc_5ftafcr_5ftampprch_5f0_1390',['RTC_TAFCR_TAMPPRCH_0',['../group___peripheral___registers___bits___definition.html#gae010ed965c1e968cc14f988d50662546',1,'stm32f407xx_matlab.h']]], - ['rtc_5ftafcr_5ftampprch_5f1_1391',['RTC_TAFCR_TAMPPRCH_1',['../group___peripheral___registers___bits___definition.html#ga16f0faa59aa4490d696d1fec767aae41',1,'stm32f407xx_matlab.h']]], - ['rtc_5ftafcr_5ftampprch_5fmsk_1392',['RTC_TAFCR_TAMPPRCH_Msk',['../group___peripheral___registers___bits___definition.html#ga76638587b6e5989ffe219851a96e4f8f',1,'stm32f407xx_matlab.h']]], - ['rtc_5ftafcr_5ftampprch_5fpos_1393',['RTC_TAFCR_TAMPPRCH_Pos',['../group___peripheral___registers___bits___definition.html#ga0650b78abfcc5a3a6b247fb9791b9292',1,'stm32f407xx_matlab.h']]], - ['rtc_5ftafcr_5ftamppudis_1394',['RTC_TAFCR_TAMPPUDIS',['../group___peripheral___registers___bits___definition.html#ga9ef294e75771913e4a47386f42a23f72',1,'stm32f407xx_matlab.h']]], - ['rtc_5ftafcr_5ftamppudis_5fmsk_1395',['RTC_TAFCR_TAMPPUDIS_Msk',['../group___peripheral___registers___bits___definition.html#gabaa57d1e8d33a2b5c8ab6aad4ec6fba0',1,'stm32f407xx_matlab.h']]], - ['rtc_5ftafcr_5ftamppudis_5fpos_1396',['RTC_TAFCR_TAMPPUDIS_Pos',['../group___peripheral___registers___bits___definition.html#gad46c537f405a4424f17cf6f47a0bdc7c',1,'stm32f407xx_matlab.h']]], - ['rtc_5ftafcr_5ftampts_1397',['RTC_TAFCR_TAMPTS',['../group___peripheral___registers___bits___definition.html#gac929fab94fdca2d1b3b3cf7c93fe6e49',1,'stm32f407xx_matlab.h']]], - ['rtc_5ftafcr_5ftampts_5fmsk_1398',['RTC_TAFCR_TAMPTS_Msk',['../group___peripheral___registers___bits___definition.html#ga195a1c8285f2826479b6afb75576ac3d',1,'stm32f407xx_matlab.h']]], - ['rtc_5ftafcr_5ftampts_5fpos_1399',['RTC_TAFCR_TAMPTS_Pos',['../group___peripheral___registers___bits___definition.html#ga73e4ad22e6610c5c39fbc548b621b244',1,'stm32f407xx_matlab.h']]], - ['rtc_5ftafcr_5ftsinsel_1400',['RTC_TAFCR_TSINSEL',['../group___peripheral___registers___bits___definition.html#ga872cbfe2e79e7fe2a4bfad6086f4ac49',1,'stm32f407xx_matlab.h']]], - ['rtc_5ftafcr_5ftsinsel_5fmsk_1401',['RTC_TAFCR_TSINSEL_Msk',['../group___peripheral___registers___bits___definition.html#gafffa3d4d97beee57ef7c1b80a20fee7e',1,'stm32f407xx_matlab.h']]], - ['rtc_5ftafcr_5ftsinsel_5fpos_1402',['RTC_TAFCR_TSINSEL_Pos',['../group___peripheral___registers___bits___definition.html#gab5a7a74b471a19d3b24624ed76c9123d',1,'stm32f407xx_matlab.h']]], - ['rtc_5ftamper2_5fsupport_1403',['RTC_TAMPER2_SUPPORT',['../group___peripheral___registers___bits___definition.html#ga8c33bacdb5372bad482df029d77a9e5e',1,'stm32f407xx_matlab.h']]], - ['rtc_5ftr_5fht_1404',['RTC_TR_HT',['../group___peripheral___registers___bits___definition.html#gad42435e015e9f5052245c366ae08d655',1,'stm32f407xx_matlab.h']]], - ['rtc_5ftr_5fht_5f0_1405',['RTC_TR_HT_0',['../group___peripheral___registers___bits___definition.html#ga1c9af54381689d893ba1b11eb33cd866',1,'stm32f407xx_matlab.h']]], - ['rtc_5ftr_5fht_5f1_1406',['RTC_TR_HT_1',['../group___peripheral___registers___bits___definition.html#ga7b3ba2cc471b86d041df3c2a1a9ef121',1,'stm32f407xx_matlab.h']]], - ['rtc_5ftr_5fht_5fmsk_1407',['RTC_TR_HT_Msk',['../group___peripheral___registers___bits___definition.html#gab3f00fc20610b447daa4b2fcf4730e94',1,'stm32f407xx_matlab.h']]], - ['rtc_5ftr_5fht_5fpos_1408',['RTC_TR_HT_Pos',['../group___peripheral___registers___bits___definition.html#ga26458edfa3da49a421547e540b7fef0c',1,'stm32f407xx_matlab.h']]], - ['rtc_5ftr_5fhu_1409',['RTC_TR_HU',['../group___peripheral___registers___bits___definition.html#gac8211df481853649722383e0d8fb06d5',1,'stm32f407xx_matlab.h']]], - ['rtc_5ftr_5fhu_5f0_1410',['RTC_TR_HU_0',['../group___peripheral___registers___bits___definition.html#gaddad920d5681960fa702b988ef1f82be',1,'stm32f407xx_matlab.h']]], - ['rtc_5ftr_5fhu_5f1_1411',['RTC_TR_HU_1',['../group___peripheral___registers___bits___definition.html#gae6206d385d3b3e127b1e63be48f83a63',1,'stm32f407xx_matlab.h']]], - ['rtc_5ftr_5fhu_5f2_1412',['RTC_TR_HU_2',['../group___peripheral___registers___bits___definition.html#ga6e264504542ec2d9b06036e938f7f79d',1,'stm32f407xx_matlab.h']]], - ['rtc_5ftr_5fhu_5f3_1413',['RTC_TR_HU_3',['../group___peripheral___registers___bits___definition.html#ga40763d3ed48e9f707784bdfd65a9c3ca',1,'stm32f407xx_matlab.h']]], - ['rtc_5ftr_5fhu_5fmsk_1414',['RTC_TR_HU_Msk',['../group___peripheral___registers___bits___definition.html#ga4be6ca68f00b9467ddad84d37f1b6a63',1,'stm32f407xx_matlab.h']]], - ['rtc_5ftr_5fhu_5fpos_1415',['RTC_TR_HU_Pos',['../group___peripheral___registers___bits___definition.html#ga1412e72836e362ccfe5a927b7760fd14',1,'stm32f407xx_matlab.h']]], - ['rtc_5ftr_5fmnt_1416',['RTC_TR_MNT',['../group___peripheral___registers___bits___definition.html#ga64cf91576871a8108d6ee2f48970bb4a',1,'stm32f407xx_matlab.h']]], - ['rtc_5ftr_5fmnt_5f0_1417',['RTC_TR_MNT_0',['../group___peripheral___registers___bits___definition.html#ga752747aa90bf35bd57b16bffc7294dfc',1,'stm32f407xx_matlab.h']]], - ['rtc_5ftr_5fmnt_5f1_1418',['RTC_TR_MNT_1',['../group___peripheral___registers___bits___definition.html#gaa1837f65a11192dd9b8bf249c31ccef7',1,'stm32f407xx_matlab.h']]], - ['rtc_5ftr_5fmnt_5f2_1419',['RTC_TR_MNT_2',['../group___peripheral___registers___bits___definition.html#ga5f27fb43718df0797664acd2d9c95c1a',1,'stm32f407xx_matlab.h']]], - ['rtc_5ftr_5fmnt_5fmsk_1420',['RTC_TR_MNT_Msk',['../group___peripheral___registers___bits___definition.html#ga87978332f15306d7db05c3bce2df2c7f',1,'stm32f407xx_matlab.h']]], - ['rtc_5ftr_5fmnt_5fpos_1421',['RTC_TR_MNT_Pos',['../group___peripheral___registers___bits___definition.html#gaf169c6a3845063073e546f372e90a61a',1,'stm32f407xx_matlab.h']]], - ['rtc_5ftr_5fmnu_1422',['RTC_TR_MNU',['../group___peripheral___registers___bits___definition.html#ga84e86f4fc04232fd0294966434708e06',1,'stm32f407xx_matlab.h']]], - ['rtc_5ftr_5fmnu_5f0_1423',['RTC_TR_MNU_0',['../group___peripheral___registers___bits___definition.html#gad91d7700822050a352e53aff372a697b',1,'stm32f407xx_matlab.h']]], - ['rtc_5ftr_5fmnu_5f1_1424',['RTC_TR_MNU_1',['../group___peripheral___registers___bits___definition.html#gad9c3087e3d4cd490af8334e99467f1dc',1,'stm32f407xx_matlab.h']]], - ['rtc_5ftr_5fmnu_5f2_1425',['RTC_TR_MNU_2',['../group___peripheral___registers___bits___definition.html#gac01a9e4b358ea062bf1c66069a28c126',1,'stm32f407xx_matlab.h']]], - ['rtc_5ftr_5fmnu_5f3_1426',['RTC_TR_MNU_3',['../group___peripheral___registers___bits___definition.html#ga75b76249e63af249061c0c5532a2a4e5',1,'stm32f407xx_matlab.h']]], - ['rtc_5ftr_5fmnu_5fmsk_1427',['RTC_TR_MNU_Msk',['../group___peripheral___registers___bits___definition.html#ga8240cd693ae8c3bf069e10ab08f3adcd',1,'stm32f407xx_matlab.h']]], - ['rtc_5ftr_5fmnu_5fpos_1428',['RTC_TR_MNU_Pos',['../group___peripheral___registers___bits___definition.html#gab5d682cf0198141f2a323981ec266173',1,'stm32f407xx_matlab.h']]], - ['rtc_5ftr_5fpm_1429',['RTC_TR_PM',['../group___peripheral___registers___bits___definition.html#ga3152952ac385ee1ce8dd868978d3fce9',1,'stm32f407xx_matlab.h']]], - ['rtc_5ftr_5fpm_5fmsk_1430',['RTC_TR_PM_Msk',['../group___peripheral___registers___bits___definition.html#gaa98be62b42b64aa8dee5df4f84ec1679',1,'stm32f407xx_matlab.h']]], - ['rtc_5ftr_5fpm_5fpos_1431',['RTC_TR_PM_Pos',['../group___peripheral___registers___bits___definition.html#ga2920dc4e941e569491e856c74f655a73',1,'stm32f407xx_matlab.h']]], - ['rtc_5ftr_5fst_1432',['RTC_TR_ST',['../group___peripheral___registers___bits___definition.html#gaae39b22025a36d1e4e185e4be2bf326f',1,'stm32f407xx_matlab.h']]], - ['rtc_5ftr_5fst_5f0_1433',['RTC_TR_ST_0',['../group___peripheral___registers___bits___definition.html#gaf0a53dc60816e0790ba69eaff3e87cb0',1,'stm32f407xx_matlab.h']]], - ['rtc_5ftr_5fst_5f1_1434',['RTC_TR_ST_1',['../group___peripheral___registers___bits___definition.html#ga948beb7166b70f1fa9e9148a8b6bd3f9',1,'stm32f407xx_matlab.h']]], - ['rtc_5ftr_5fst_5f2_1435',['RTC_TR_ST_2',['../group___peripheral___registers___bits___definition.html#ga4d5f0413990c26a5cf9a857d10243e9b',1,'stm32f407xx_matlab.h']]], - ['rtc_5ftr_5fst_5fmsk_1436',['RTC_TR_ST_Msk',['../group___peripheral___registers___bits___definition.html#gaf3ae841c3e4f90face971c95f1228419',1,'stm32f407xx_matlab.h']]], - ['rtc_5ftr_5fst_5fpos_1437',['RTC_TR_ST_Pos',['../group___peripheral___registers___bits___definition.html#ga641ca04f0ccdab58ac9fe27211719a66',1,'stm32f407xx_matlab.h']]], - ['rtc_5ftr_5fsu_1438',['RTC_TR_SU',['../group___peripheral___registers___bits___definition.html#ga747711823db36121b78c0eebb6140ca1',1,'stm32f407xx_matlab.h']]], - ['rtc_5ftr_5fsu_5f0_1439',['RTC_TR_SU_0',['../group___peripheral___registers___bits___definition.html#ga4132b0e9d72ff72df7e0062a1e081ca3',1,'stm32f407xx_matlab.h']]], - ['rtc_5ftr_5fsu_5f1_1440',['RTC_TR_SU_1',['../group___peripheral___registers___bits___definition.html#ga6eef03c1de3719d801c970eec53e7500',1,'stm32f407xx_matlab.h']]], - ['rtc_5ftr_5fsu_5f2_1441',['RTC_TR_SU_2',['../group___peripheral___registers___bits___definition.html#gabbe7e738c8adaaf24f6faca467d6fde2',1,'stm32f407xx_matlab.h']]], - ['rtc_5ftr_5fsu_5f3_1442',['RTC_TR_SU_3',['../group___peripheral___registers___bits___definition.html#gab44e19720b6691f63ba4f0c38a1fd7f3',1,'stm32f407xx_matlab.h']]], - ['rtc_5ftr_5fsu_5fmsk_1443',['RTC_TR_SU_Msk',['../group___peripheral___registers___bits___definition.html#gac65138b7d68cf4db6e391a5e3d31d4a5',1,'stm32f407xx_matlab.h']]], - ['rtc_5ftr_5fsu_5fpos_1444',['RTC_TR_SU_Pos',['../group___peripheral___registers___bits___definition.html#ga2a5251e75005627144d7a044045484ca',1,'stm32f407xx_matlab.h']]], - ['rtc_5ftsdr_5fdt_1445',['RTC_TSDR_DT',['../group___peripheral___registers___bits___definition.html#ga39c9ff61f3b622b829aa9354ca84e44e',1,'stm32f407xx_matlab.h']]], - ['rtc_5ftsdr_5fdt_5f0_1446',['RTC_TSDR_DT_0',['../group___peripheral___registers___bits___definition.html#ga81e02a917946bddaa027a04538576533',1,'stm32f407xx_matlab.h']]], - ['rtc_5ftsdr_5fdt_5f1_1447',['RTC_TSDR_DT_1',['../group___peripheral___registers___bits___definition.html#ga886739ae0e8c0f6144dbd774c203ed5f',1,'stm32f407xx_matlab.h']]], - ['rtc_5ftsdr_5fdt_5fmsk_1448',['RTC_TSDR_DT_Msk',['../group___peripheral___registers___bits___definition.html#gaa4e5fcdf15ef6bff31a9fa1857f88811',1,'stm32f407xx_matlab.h']]], - ['rtc_5ftsdr_5fdt_5fpos_1449',['RTC_TSDR_DT_Pos',['../group___peripheral___registers___bits___definition.html#ga02d8e7630640b836002e20b25726e7f8',1,'stm32f407xx_matlab.h']]], - ['rtc_5ftsdr_5fdu_1450',['RTC_TSDR_DU',['../group___peripheral___registers___bits___definition.html#gace7ca73ebca21ed3a17315f06757042a',1,'stm32f407xx_matlab.h']]], - ['rtc_5ftsdr_5fdu_5f0_1451',['RTC_TSDR_DU_0',['../group___peripheral___registers___bits___definition.html#ga08b7eccac0c3cd20a3f3cd8bce1693ad',1,'stm32f407xx_matlab.h']]], - ['rtc_5ftsdr_5fdu_5f1_1452',['RTC_TSDR_DU_1',['../group___peripheral___registers___bits___definition.html#gaa43ed53b8109ff32755885127ba987ce',1,'stm32f407xx_matlab.h']]], - ['rtc_5ftsdr_5fdu_5f2_1453',['RTC_TSDR_DU_2',['../group___peripheral___registers___bits___definition.html#ga1b3d774b7df9cff6e6eecafa7c42a059',1,'stm32f407xx_matlab.h']]], - ['rtc_5ftsdr_5fdu_5f3_1454',['RTC_TSDR_DU_3',['../group___peripheral___registers___bits___definition.html#ga209573a43dd1f21ef569d75593ad03f8',1,'stm32f407xx_matlab.h']]], - ['rtc_5ftsdr_5fdu_5fmsk_1455',['RTC_TSDR_DU_Msk',['../group___peripheral___registers___bits___definition.html#ga3f1e801e7d2a8c93a4ac5272a6037dde',1,'stm32f407xx_matlab.h']]], - ['rtc_5ftsdr_5fdu_5fpos_1456',['RTC_TSDR_DU_Pos',['../group___peripheral___registers___bits___definition.html#ga031ca4fddcc1f40b7db8b46ec32ed60c',1,'stm32f407xx_matlab.h']]], - ['rtc_5ftsdr_5fmt_1457',['RTC_TSDR_MT',['../group___peripheral___registers___bits___definition.html#ga7bce43482443f2038a8eebc681067dd7',1,'stm32f407xx_matlab.h']]], - ['rtc_5ftsdr_5fmt_5fmsk_1458',['RTC_TSDR_MT_Msk',['../group___peripheral___registers___bits___definition.html#gab11fc35bffeed3dbfb7f08e75f8319da',1,'stm32f407xx_matlab.h']]], - ['rtc_5ftsdr_5fmt_5fpos_1459',['RTC_TSDR_MT_Pos',['../group___peripheral___registers___bits___definition.html#ga2b1a8d81075b72d48e99990de9a22f98',1,'stm32f407xx_matlab.h']]], - ['rtc_5ftsdr_5fmu_1460',['RTC_TSDR_MU',['../group___peripheral___registers___bits___definition.html#ga2a5912337df16624b4703d2065c5fdf4',1,'stm32f407xx_matlab.h']]], - ['rtc_5ftsdr_5fmu_5f0_1461',['RTC_TSDR_MU_0',['../group___peripheral___registers___bits___definition.html#ga9cf9d23d49e121268a25445a7eed2f35',1,'stm32f407xx_matlab.h']]], - ['rtc_5ftsdr_5fmu_5f1_1462',['RTC_TSDR_MU_1',['../group___peripheral___registers___bits___definition.html#ga49093134e4ead8b4990e5e1628db0692',1,'stm32f407xx_matlab.h']]], - ['rtc_5ftsdr_5fmu_5f2_1463',['RTC_TSDR_MU_2',['../group___peripheral___registers___bits___definition.html#gad7f31eb674f5a67402b6a3eb578b70a5',1,'stm32f407xx_matlab.h']]], - ['rtc_5ftsdr_5fmu_5f3_1464',['RTC_TSDR_MU_3',['../group___peripheral___registers___bits___definition.html#gad67666c54ef1be79a500484a5e755827',1,'stm32f407xx_matlab.h']]], - ['rtc_5ftsdr_5fmu_5fmsk_1465',['RTC_TSDR_MU_Msk',['../group___peripheral___registers___bits___definition.html#ga85638fe2912aec33b38fcfc51e97aa2e',1,'stm32f407xx_matlab.h']]], - ['rtc_5ftsdr_5fmu_5fpos_1466',['RTC_TSDR_MU_Pos',['../group___peripheral___registers___bits___definition.html#ga30556fea7362882afb160a1108ef0539',1,'stm32f407xx_matlab.h']]], - ['rtc_5ftsdr_5fwdu_1467',['RTC_TSDR_WDU',['../group___peripheral___registers___bits___definition.html#ga4c76ea431470b87f22e7854bd5438d2f',1,'stm32f407xx_matlab.h']]], - ['rtc_5ftsdr_5fwdu_5f0_1468',['RTC_TSDR_WDU_0',['../group___peripheral___registers___bits___definition.html#ga4e9cbf062e41eecacccde522e24452c1',1,'stm32f407xx_matlab.h']]], - ['rtc_5ftsdr_5fwdu_5f1_1469',['RTC_TSDR_WDU_1',['../group___peripheral___registers___bits___definition.html#ga44259df3c6dc88e8168c7dcd5e6abf91',1,'stm32f407xx_matlab.h']]], - ['rtc_5ftsdr_5fwdu_5f2_1470',['RTC_TSDR_WDU_2',['../group___peripheral___registers___bits___definition.html#ga7f2add59486679cc53f521c139d72852',1,'stm32f407xx_matlab.h']]], - ['rtc_5ftsdr_5fwdu_5fmsk_1471',['RTC_TSDR_WDU_Msk',['../group___peripheral___registers___bits___definition.html#gaa9022409e82c29cf18da7efe49032caf',1,'stm32f407xx_matlab.h']]], - ['rtc_5ftsdr_5fwdu_5fpos_1472',['RTC_TSDR_WDU_Pos',['../group___peripheral___registers___bits___definition.html#gac365337a0d8e54ad40e3d4abeba10d33',1,'stm32f407xx_matlab.h']]], - ['rtc_5ftsssr_5fss_1473',['RTC_TSSSR_SS',['../group___peripheral___registers___bits___definition.html#ga2fb913ce5f1c0e341b308d9b5858bfa9',1,'stm32f407xx_matlab.h']]], - ['rtc_5ftsssr_5fss_5fmsk_1474',['RTC_TSSSR_SS_Msk',['../group___peripheral___registers___bits___definition.html#ga1d13c3c83f99d3bdf8fc33ea42b3aecd',1,'stm32f407xx_matlab.h']]], - ['rtc_5ftsssr_5fss_5fpos_1475',['RTC_TSSSR_SS_Pos',['../group___peripheral___registers___bits___definition.html#gac381e2fe1c99a95a6a41f1845d6f207f',1,'stm32f407xx_matlab.h']]], - ['rtc_5ftstr_5fht_1476',['RTC_TSTR_HT',['../group___peripheral___registers___bits___definition.html#ga5765274cda5284899563191cb505235a',1,'stm32f407xx_matlab.h']]], - ['rtc_5ftstr_5fht_5f0_1477',['RTC_TSTR_HT_0',['../group___peripheral___registers___bits___definition.html#ga3b682daaa79917786d55c2bf44a80325',1,'stm32f407xx_matlab.h']]], - ['rtc_5ftstr_5fht_5f1_1478',['RTC_TSTR_HT_1',['../group___peripheral___registers___bits___definition.html#ga9a35c1a1f98f2aeb73235d940922f9cf',1,'stm32f407xx_matlab.h']]], - ['rtc_5ftstr_5fht_5fmsk_1479',['RTC_TSTR_HT_Msk',['../group___peripheral___registers___bits___definition.html#gae1c592f62a64ad486af67101a02badba',1,'stm32f407xx_matlab.h']]], - ['rtc_5ftstr_5fht_5fpos_1480',['RTC_TSTR_HT_Pos',['../group___peripheral___registers___bits___definition.html#ga380cea6fd8d7736ad8d83bce9c6f4379',1,'stm32f407xx_matlab.h']]], - ['rtc_5ftstr_5fhu_1481',['RTC_TSTR_HU',['../group___peripheral___registers___bits___definition.html#gaf12107fe82e4f9de5ae4fdd6c169a846',1,'stm32f407xx_matlab.h']]], - ['rtc_5ftstr_5fhu_5f0_1482',['RTC_TSTR_HU_0',['../group___peripheral___registers___bits___definition.html#ga1a235fd8965c706e7f57327f6e5ce72d',1,'stm32f407xx_matlab.h']]], - ['rtc_5ftstr_5fhu_5f1_1483',['RTC_TSTR_HU_1',['../group___peripheral___registers___bits___definition.html#ga56f2bc31a8d01d7621de40d146b15fb7',1,'stm32f407xx_matlab.h']]], - ['rtc_5ftstr_5fhu_5f2_1484',['RTC_TSTR_HU_2',['../group___peripheral___registers___bits___definition.html#ga5d848f11cf3130bb6560d117f97b7da3',1,'stm32f407xx_matlab.h']]], - ['rtc_5ftstr_5fhu_5f3_1485',['RTC_TSTR_HU_3',['../group___peripheral___registers___bits___definition.html#ga703c813d88b2c9ab350cb0218ff4bbe7',1,'stm32f407xx_matlab.h']]], - ['rtc_5ftstr_5fhu_5fmsk_1486',['RTC_TSTR_HU_Msk',['../group___peripheral___registers___bits___definition.html#ga4bd9c8067bccd2967bbbb5cd3bad9375',1,'stm32f407xx_matlab.h']]], - ['rtc_5ftstr_5fhu_5fpos_1487',['RTC_TSTR_HU_Pos',['../group___peripheral___registers___bits___definition.html#gab82c3482dd42a99d0a28d52cfb89be11',1,'stm32f407xx_matlab.h']]], - ['rtc_5ftstr_5fmnt_1488',['RTC_TSTR_MNT',['../group___peripheral___registers___bits___definition.html#ga9743a3843868c712945a7c408183ad73',1,'stm32f407xx_matlab.h']]], - ['rtc_5ftstr_5fmnt_5f0_1489',['RTC_TSTR_MNT_0',['../group___peripheral___registers___bits___definition.html#gaf04bea9e3f4645257b8bd955f3ba80ce',1,'stm32f407xx_matlab.h']]], - ['rtc_5ftstr_5fmnt_5f1_1490',['RTC_TSTR_MNT_1',['../group___peripheral___registers___bits___definition.html#gadf30459ae8455ad0fb382dd866446c83',1,'stm32f407xx_matlab.h']]], - ['rtc_5ftstr_5fmnt_5f2_1491',['RTC_TSTR_MNT_2',['../group___peripheral___registers___bits___definition.html#ga513f78562b18cfc36f52e80be9cb20d5',1,'stm32f407xx_matlab.h']]], - ['rtc_5ftstr_5fmnt_5fmsk_1492',['RTC_TSTR_MNT_Msk',['../group___peripheral___registers___bits___definition.html#ga7eefd1e26e643f63b5550cebcfb7a597',1,'stm32f407xx_matlab.h']]], - ['rtc_5ftstr_5fmnt_5fpos_1493',['RTC_TSTR_MNT_Pos',['../group___peripheral___registers___bits___definition.html#gae41110f902c7d1b538021d157da48a23',1,'stm32f407xx_matlab.h']]], - ['rtc_5ftstr_5fmnu_1494',['RTC_TSTR_MNU',['../group___peripheral___registers___bits___definition.html#ga64b186af486822cc015cfec613f5cba9',1,'stm32f407xx_matlab.h']]], - ['rtc_5ftstr_5fmnu_5f0_1495',['RTC_TSTR_MNU_0',['../group___peripheral___registers___bits___definition.html#gab8ff1f79f2ab33d00a979979d486bc44',1,'stm32f407xx_matlab.h']]], - ['rtc_5ftstr_5fmnu_5f1_1496',['RTC_TSTR_MNU_1',['../group___peripheral___registers___bits___definition.html#ga506d192fef16558c9b0b7ed9e1a9147c',1,'stm32f407xx_matlab.h']]], - ['rtc_5ftstr_5fmnu_5f2_1497',['RTC_TSTR_MNU_2',['../group___peripheral___registers___bits___definition.html#ga407a93c758b95a1ebf3c41c36fb6f07e',1,'stm32f407xx_matlab.h']]], - ['rtc_5ftstr_5fmnu_5f3_1498',['RTC_TSTR_MNU_3',['../group___peripheral___registers___bits___definition.html#gac55cd85d2e58a819637d15f70f7179a0',1,'stm32f407xx_matlab.h']]], - ['rtc_5ftstr_5fmnu_5fmsk_1499',['RTC_TSTR_MNU_Msk',['../group___peripheral___registers___bits___definition.html#ga989ebeea3d902970e5189c667f08dd57',1,'stm32f407xx_matlab.h']]], - ['rtc_5ftstr_5fmnu_5fpos_1500',['RTC_TSTR_MNU_Pos',['../group___peripheral___registers___bits___definition.html#gada4e4f24245be3e28d06c606bb1bd9e8',1,'stm32f407xx_matlab.h']]], - ['rtc_5ftstr_5fpm_1501',['RTC_TSTR_PM',['../group___peripheral___registers___bits___definition.html#ga84b3d044be3e63573a5f0d4d14d8e3b0',1,'stm32f407xx_matlab.h']]], - ['rtc_5ftstr_5fpm_5fmsk_1502',['RTC_TSTR_PM_Msk',['../group___peripheral___registers___bits___definition.html#ga844125f323c84655caa5d09de90d676a',1,'stm32f407xx_matlab.h']]], - ['rtc_5ftstr_5fpm_5fpos_1503',['RTC_TSTR_PM_Pos',['../group___peripheral___registers___bits___definition.html#ga9c6a72f9bab0b1783762c3c612d5a0e6',1,'stm32f407xx_matlab.h']]], - ['rtc_5ftstr_5fst_1504',['RTC_TSTR_ST',['../group___peripheral___registers___bits___definition.html#ga9fbdebcd1da2ea191cca51c222345f15',1,'stm32f407xx_matlab.h']]], - ['rtc_5ftstr_5fst_5f0_1505',['RTC_TSTR_ST_0',['../group___peripheral___registers___bits___definition.html#ga90d733a561ad71ee4c63c4e0a3ed5f32',1,'stm32f407xx_matlab.h']]], - ['rtc_5ftstr_5fst_5f1_1506',['RTC_TSTR_ST_1',['../group___peripheral___registers___bits___definition.html#ga807073dc98612721530a79df5b5c265a',1,'stm32f407xx_matlab.h']]], - ['rtc_5ftstr_5fst_5f2_1507',['RTC_TSTR_ST_2',['../group___peripheral___registers___bits___definition.html#gaee05d278bdd457b4f61d797e45520d13',1,'stm32f407xx_matlab.h']]], - ['rtc_5ftstr_5fst_5fmsk_1508',['RTC_TSTR_ST_Msk',['../group___peripheral___registers___bits___definition.html#ga653df3d0cdd6c8235762f5152dda55c9',1,'stm32f407xx_matlab.h']]], - ['rtc_5ftstr_5fst_5fpos_1509',['RTC_TSTR_ST_Pos',['../group___peripheral___registers___bits___definition.html#ga8a4e53ced662f212e19f30ccf60fdf74',1,'stm32f407xx_matlab.h']]], - ['rtc_5ftstr_5fsu_1510',['RTC_TSTR_SU',['../group___peripheral___registers___bits___definition.html#gac0d8fa76d45faccfe931d6227b29565a',1,'stm32f407xx_matlab.h']]], - ['rtc_5ftstr_5fsu_5f0_1511',['RTC_TSTR_SU_0',['../group___peripheral___registers___bits___definition.html#ga8990f4d1d493012289778e854c52e97e',1,'stm32f407xx_matlab.h']]], - ['rtc_5ftstr_5fsu_5f1_1512',['RTC_TSTR_SU_1',['../group___peripheral___registers___bits___definition.html#gaab6f4275d2a15e7307363124c03a64a4',1,'stm32f407xx_matlab.h']]], - ['rtc_5ftstr_5fsu_5f2_1513',['RTC_TSTR_SU_2',['../group___peripheral___registers___bits___definition.html#ga5610b3103a8a6653204f4fe7e9ea8587',1,'stm32f407xx_matlab.h']]], - ['rtc_5ftstr_5fsu_5f3_1514',['RTC_TSTR_SU_3',['../group___peripheral___registers___bits___definition.html#ga28790ae937a50ba6fb4aff5a9f5afbcb',1,'stm32f407xx_matlab.h']]], - ['rtc_5ftstr_5fsu_5fmsk_1515',['RTC_TSTR_SU_Msk',['../group___peripheral___registers___bits___definition.html#gaf868c2dda50075428856aa7551f712c4',1,'stm32f407xx_matlab.h']]], - ['rtc_5ftstr_5fsu_5fpos_1516',['RTC_TSTR_SU_Pos',['../group___peripheral___registers___bits___definition.html#ga24f2a25eab6521118adf40765216cfe4',1,'stm32f407xx_matlab.h']]], - ['rtc_5ftypedef_1517',['RTC_TypeDef',['../struct_r_t_c___type_def.html',1,'']]], - ['rtc_5fwkup_5firqn_1518',['RTC_WKUP_IRQn',['../group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a173ccc3f31df1f7e43de2ddeab3d1777',1,'stm32f407xx_matlab.h']]], - ['rtc_5fwpr_5fkey_1519',['RTC_WPR_KEY',['../group___peripheral___registers___bits___definition.html#ga2d21f29da0e92b2744719aab37278b07',1,'stm32f407xx_matlab.h']]], - ['rtc_5fwpr_5fkey_5fmsk_1520',['RTC_WPR_KEY_Msk',['../group___peripheral___registers___bits___definition.html#ga81983eda15eb251ae9e94a8290450cb1',1,'stm32f407xx_matlab.h']]], - ['rtc_5fwpr_5fkey_5fpos_1521',['RTC_WPR_KEY_Pos',['../group___peripheral___registers___bits___definition.html#ga8567138f5a3dddde68b6cdda56e41846',1,'stm32f407xx_matlab.h']]], - ['rtc_5fwutr_5fwut_1522',['RTC_WUTR_WUT',['../group___peripheral___registers___bits___definition.html#ga2e412c1448a7e20974f5b46129799eeb',1,'stm32f407xx_matlab.h']]], - ['rtc_5fwutr_5fwut_5fmsk_1523',['RTC_WUTR_WUT_Msk',['../group___peripheral___registers___bits___definition.html#ga1c2d178daf42c0febdbf67583a83b6a0',1,'stm32f407xx_matlab.h']]], - ['rtc_5fwutr_5fwut_5fpos_1524',['RTC_WUTR_WUT_Pos',['../group___peripheral___registers___bits___definition.html#gae50a0fcd154d36aa0b506a875e8d100e',1,'stm32f407xx_matlab.h']]], - ['rtsr_1525',['RTSR',['../group___c_m_s_i_s___device.html#ga0d952a17455687d6e9053730d028fa1d',1,'EXTI_TypeDef']]], - ['run_5fmex_2ebat_1526',['run_mex.bat',['../run__mex_8bat.html',1,'']]], - ['rxcrcr_1527',['RXCRCR',['../group___c_m_s_i_s___device.html#ga2cf9dcd9008924334f20f0dc6b57042e',1,'SPI_TypeDef']]] + ['variables_20for_20debugging_0',['Periphs Variables for Debugging',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html',1,'']]] ]; diff --git a/DOCS/html/search/all_13.js b/DOCS/html/search/all_13.js index a5360b8..e6ecb8f 100644 --- a/DOCS/html/search/all_13.js +++ b/DOCS/html/search/all_13.js @@ -1,978 +1,9 @@ var searchData= [ - ['s_5ffunction_5flevel_0',['S_FUNCTION_LEVEL',['../_m_c_u_8c.html#a9a4ab27953070e39249f3fad28e93749',1,'MCU.c']]], - ['s_5ffunction_5fname_1',['S_FUNCTION_NAME',['../_m_c_u_8c.html#a0f61df833e166c743295eebf43f0b142',1,'MCU.c']]], - ['scb_2',['SCB',['../group___c_m_s_i_s__core__base.html#gaaaf6477c2bde2f00f99e3c2fd1060b01',1,'SCB: core_cm4_matlab.h'],['../group___c_m_s_i_s___s_c_b.html',1,'System Control Block (SCB)']]], - ['scb_20scnscb_3',['System Controls not in SCB (SCnSCB)',['../group___c_m_s_i_s___s_cn_s_c_b.html',1,'']]], - ['scb_5faircr_5fendianess_5fmsk_4',['SCB_AIRCR_ENDIANESS_Msk',['../group___c_m_s_i_s___s_c_b.html#ga2f571f93d3d4a6eac9a3040756d3d951',1,'core_cm4_matlab.h']]], - ['scb_5faircr_5fendianess_5fpos_5',['SCB_AIRCR_ENDIANESS_Pos',['../group___c_m_s_i_s___s_c_b.html#gad31dec98fbc0d33ace63cb1f1a927923',1,'core_cm4_matlab.h']]], - ['scb_5faircr_5fprigroup_5fmsk_6',['SCB_AIRCR_PRIGROUP_Msk',['../group___c_m_s_i_s___s_c_b.html#ga8be60fff03f48d0d345868060dc6dae7',1,'core_cm4_matlab.h']]], - ['scb_5faircr_5fprigroup_5fpos_7',['SCB_AIRCR_PRIGROUP_Pos',['../group___c_m_s_i_s___s_c_b.html#gaca155deccdeca0f2c76b8100d24196c8',1,'core_cm4_matlab.h']]], - ['scb_5faircr_5fsysresetreq_5fmsk_8',['SCB_AIRCR_SYSRESETREQ_Msk',['../group___c_m_s_i_s___s_c_b.html#gaae1181119559a5bd36e62afa373fa720',1,'core_cm4_matlab.h']]], - ['scb_5faircr_5fsysresetreq_5fpos_9',['SCB_AIRCR_SYSRESETREQ_Pos',['../group___c_m_s_i_s___s_c_b.html#gaffb2737eca1eac0fc1c282a76a40953c',1,'core_cm4_matlab.h']]], - ['scb_5faircr_5fvectclractive_5fmsk_10',['SCB_AIRCR_VECTCLRACTIVE_Msk',['../group___c_m_s_i_s___s_c_b.html#ga212c5ab1c1c82c807d30d2307aa8d218',1,'core_cm4_matlab.h']]], - ['scb_5faircr_5fvectclractive_5fpos_11',['SCB_AIRCR_VECTCLRACTIVE_Pos',['../group___c_m_s_i_s___s_c_b.html#gaa30a12e892bb696e61626d71359a9029',1,'core_cm4_matlab.h']]], - ['scb_5faircr_5fvectkey_5fmsk_12',['SCB_AIRCR_VECTKEY_Msk',['../group___c_m_s_i_s___s_c_b.html#ga90c7cf0c490e7ae55f9503a7fda1dd22',1,'core_cm4_matlab.h']]], - ['scb_5faircr_5fvectkey_5fpos_13',['SCB_AIRCR_VECTKEY_Pos',['../group___c_m_s_i_s___s_c_b.html#gaaa27c0ba600bf82c3da08c748845b640',1,'core_cm4_matlab.h']]], - ['scb_5faircr_5fvectkeystat_5fmsk_14',['SCB_AIRCR_VECTKEYSTAT_Msk',['../group___c_m_s_i_s___s_c_b.html#gabacedaefeefc73d666bbe59ece904493',1,'core_cm4_matlab.h']]], - ['scb_5faircr_5fvectkeystat_5fpos_15',['SCB_AIRCR_VECTKEYSTAT_Pos',['../group___c_m_s_i_s___s_c_b.html#gaec404750ff5ca07f499a3c06b62051ef',1,'core_cm4_matlab.h']]], - ['scb_5faircr_5fvectreset_5fmsk_16',['SCB_AIRCR_VECTRESET_Msk',['../group___c_m_s_i_s___s_c_b.html#ga3006e31968bb9725e7b4ee0784d99f7f',1,'core_cm4_matlab.h']]], - ['scb_5faircr_5fvectreset_5fpos_17',['SCB_AIRCR_VECTRESET_Pos',['../group___c_m_s_i_s___s_c_b.html#ga0d483d9569cd9d1b46ec0d171b1f18d8',1,'core_cm4_matlab.h']]], - ['scb_5fbase_18',['SCB_BASE',['../group___c_m_s_i_s__core__base.html#gad55a7ddb8d4b2398b0c1cfec76c0d9fd',1,'core_cm4_matlab.h']]], - ['scb_5fccr_5fbfhfnmign_5fmsk_19',['SCB_CCR_BFHFNMIGN_Msk',['../group___c_m_s_i_s___s_c_b.html#ga89a28cc31cfc7d52d9d7a8fcc69c7eac',1,'core_cm4_matlab.h']]], - ['scb_5fccr_5fbfhfnmign_5fpos_20',['SCB_CCR_BFHFNMIGN_Pos',['../group___c_m_s_i_s___s_c_b.html#ga4010a4f9e2a745af1b58abe1f791ebbf',1,'core_cm4_matlab.h']]], - ['scb_5fccr_5fdiv_5f0_5ftrp_5fmsk_21',['SCB_CCR_DIV_0_TRP_Msk',['../group___c_m_s_i_s___s_c_b.html#gabb9aeac71b3abd8586d0297070f61dcb',1,'core_cm4_matlab.h']]], - ['scb_5fccr_5fdiv_5f0_5ftrp_5fpos_22',['SCB_CCR_DIV_0_TRP_Pos',['../group___c_m_s_i_s___s_c_b.html#gac8d512998bb8cd9333fb7627ddf59bba',1,'core_cm4_matlab.h']]], - ['scb_5fccr_5fnonbasethrdena_5fmsk_23',['SCB_CCR_NONBASETHRDENA_Msk',['../group___c_m_s_i_s___s_c_b.html#gafe0f6be81b35d72d0736a0a1e3b4fbb3',1,'core_cm4_matlab.h']]], - ['scb_5fccr_5fnonbasethrdena_5fpos_24',['SCB_CCR_NONBASETHRDENA_Pos',['../group___c_m_s_i_s___s_c_b.html#gab4615f7deb07386350365b10240a3c83',1,'core_cm4_matlab.h']]], - ['scb_5fccr_5fstkalign_5fmsk_25',['SCB_CCR_STKALIGN_Msk',['../group___c_m_s_i_s___s_c_b.html#ga33cf22d3d46af158a03aad25ddea1bcb',1,'core_cm4_matlab.h']]], - ['scb_5fccr_5fstkalign_5fpos_26',['SCB_CCR_STKALIGN_Pos',['../group___c_m_s_i_s___s_c_b.html#gac2d20a250960a432cc74da59d20e2f86',1,'core_cm4_matlab.h']]], - ['scb_5fccr_5funalign_5ftrp_5fmsk_27',['SCB_CCR_UNALIGN_TRP_Msk',['../group___c_m_s_i_s___s_c_b.html#ga68c96ad594af70c007923979085c99e0',1,'core_cm4_matlab.h']]], - ['scb_5fccr_5funalign_5ftrp_5fpos_28',['SCB_CCR_UNALIGN_TRP_Pos',['../group___c_m_s_i_s___s_c_b.html#gac4e4928b864ea10fc24dbbc57d976229',1,'core_cm4_matlab.h']]], - ['scb_5fccr_5fusersetmpend_5fmsk_29',['SCB_CCR_USERSETMPEND_Msk',['../group___c_m_s_i_s___s_c_b.html#ga4cf59b6343ca962c80e1885710da90aa',1,'core_cm4_matlab.h']]], - ['scb_5fccr_5fusersetmpend_5fpos_30',['SCB_CCR_USERSETMPEND_Pos',['../group___c_m_s_i_s___s_c_b.html#ga789e41f45f59a8cd455fd59fa7652e5e',1,'core_cm4_matlab.h']]], - ['scb_5fcfsr_5fbfarvalid_5fmsk_31',['SCB_CFSR_BFARVALID_Msk',['../group___c_m_s_i_s___s_c_b.html#ga56dd2218996bebbf2a38180ae6f9fcf7',1,'core_cm4_matlab.h']]], - ['scb_5fcfsr_5fbfarvalid_5fpos_32',['SCB_CFSR_BFARVALID_Pos',['../group___c_m_s_i_s___s_c_b.html#ga1cdff62f1f5730c14c809fef9009bfbb',1,'core_cm4_matlab.h']]], - ['scb_5fcfsr_5fbusfaultsr_5fmsk_33',['SCB_CFSR_BUSFAULTSR_Msk',['../group___c_m_s_i_s___s_c_b.html#ga26dc1ddfdc37a6b92597a6f7e498c1d6',1,'core_cm4_matlab.h']]], - ['scb_5fcfsr_5fbusfaultsr_5fpos_34',['SCB_CFSR_BUSFAULTSR_Pos',['../group___c_m_s_i_s___s_c_b.html#ga555a24f4f57d199f91d1d1ab7c8c3c8a',1,'core_cm4_matlab.h']]], - ['scb_5fcfsr_5fdaccviol_5fmsk_35',['SCB_CFSR_DACCVIOL_Msk',['../group___c_m_s_i_s___s_c_b.html#gacd585d5b620c175f80dd99aecbe42bcf',1,'core_cm4_matlab.h']]], - ['scb_5fcfsr_5fdaccviol_5fpos_36',['SCB_CFSR_DACCVIOL_Pos',['../group___c_m_s_i_s___s_c_b.html#gaa9c22daf6e72e64259673b55ae095725',1,'core_cm4_matlab.h']]], - ['scb_5fcfsr_5fdivbyzero_5fmsk_37',['SCB_CFSR_DIVBYZERO_Msk',['../group___c_m_s_i_s___s_c_b.html#ga9d91a0850b4962ad1335b2eadac6777e',1,'core_cm4_matlab.h']]], - ['scb_5fcfsr_5fdivbyzero_5fpos_38',['SCB_CFSR_DIVBYZERO_Pos',['../group___c_m_s_i_s___s_c_b.html#gaa8fc61d57be3e94db000367f521aa1fc',1,'core_cm4_matlab.h']]], - ['scb_5fcfsr_5fiaccviol_5fmsk_39',['SCB_CFSR_IACCVIOL_Msk',['../group___c_m_s_i_s___s_c_b.html#gac0a8e6525cd6c610f05d99640b40e6b7',1,'core_cm4_matlab.h']]], - ['scb_5fcfsr_5fiaccviol_5fpos_40',['SCB_CFSR_IACCVIOL_Pos',['../group___c_m_s_i_s___s_c_b.html#ga964f0465dfaca775e31db26e50f395d5',1,'core_cm4_matlab.h']]], - ['scb_5fcfsr_5fibuserr_5fmsk_41',['SCB_CFSR_IBUSERR_Msk',['../group___c_m_s_i_s___s_c_b.html#ga2a0907c95aabc4b9d77c3e28d14a717f',1,'core_cm4_matlab.h']]], - ['scb_5fcfsr_5fibuserr_5fpos_42',['SCB_CFSR_IBUSERR_Pos',['../group___c_m_s_i_s___s_c_b.html#gad01f4e7c1daa67e2ca8eb4411fd80df4',1,'core_cm4_matlab.h']]], - ['scb_5fcfsr_5fimpreciserr_5fmsk_43',['SCB_CFSR_IMPRECISERR_Msk',['../group___c_m_s_i_s___s_c_b.html#ga6e6b3b643e1c2e14c96f10b42d59fc64',1,'core_cm4_matlab.h']]], - ['scb_5fcfsr_5fimpreciserr_5fpos_44',['SCB_CFSR_IMPRECISERR_Pos',['../group___c_m_s_i_s___s_c_b.html#gaec426f59eb8d75acd48b32953ac154f5',1,'core_cm4_matlab.h']]], - ['scb_5fcfsr_5finvpc_5fmsk_45',['SCB_CFSR_INVPC_Msk',['../group___c_m_s_i_s___s_c_b.html#gafd7f0192bfedbde5d313fe7e637f55f1',1,'core_cm4_matlab.h']]], - ['scb_5fcfsr_5finvpc_5fpos_46',['SCB_CFSR_INVPC_Pos',['../group___c_m_s_i_s___s_c_b.html#ga526d3cebe0e96962941e5e3a729307c2',1,'core_cm4_matlab.h']]], - ['scb_5fcfsr_5finvstate_5fmsk_47',['SCB_CFSR_INVSTATE_Msk',['../group___c_m_s_i_s___s_c_b.html#ga8088a459ac3900a43a54f5cd4252484d',1,'core_cm4_matlab.h']]], - ['scb_5fcfsr_5finvstate_5fpos_48',['SCB_CFSR_INVSTATE_Pos',['../group___c_m_s_i_s___s_c_b.html#ga85ecc14a387d790129e9a3fb1312407a',1,'core_cm4_matlab.h']]], - ['scb_5fcfsr_5flsperr_5fmsk_49',['SCB_CFSR_LSPERR_Msk',['../group___c_m_s_i_s___s_c_b.html#ga8af8c68915f63358325fb4ebc5d7acc1',1,'core_cm4_matlab.h']]], - ['scb_5fcfsr_5flsperr_5fpos_50',['SCB_CFSR_LSPERR_Pos',['../group___c_m_s_i_s___s_c_b.html#gaf9b4a695a4f8d14a17be613423ef30e1',1,'core_cm4_matlab.h']]], - ['scb_5fcfsr_5fmemfaultsr_5fmsk_51',['SCB_CFSR_MEMFAULTSR_Msk',['../group___c_m_s_i_s___s_c_b.html#gad46716159a3808c9e7da22067d6bec98',1,'core_cm4_matlab.h']]], - ['scb_5fcfsr_5fmemfaultsr_5fpos_52',['SCB_CFSR_MEMFAULTSR_Pos',['../group___c_m_s_i_s___s_c_b.html#ga91f41491cec5b5acca3fbc94efbd799e',1,'core_cm4_matlab.h']]], - ['scb_5fcfsr_5fmlsperr_5fmsk_53',['SCB_CFSR_MLSPERR_Msk',['../group___c_m_s_i_s___s_c_b.html#gac0602ef4ef443ef6ccb1f24d6886661a',1,'core_cm4_matlab.h']]], - ['scb_5fcfsr_5fmlsperr_5fpos_54',['SCB_CFSR_MLSPERR_Pos',['../group___c_m_s_i_s___s_c_b.html#ga1390a486a538d1bb8e9661b678e88e39',1,'core_cm4_matlab.h']]], - ['scb_5fcfsr_5fmmarvalid_5fmsk_55',['SCB_CFSR_MMARVALID_Msk',['../group___c_m_s_i_s___s_c_b.html#ga33f17b24b05b0405de908ce185bef5c3',1,'core_cm4_matlab.h']]], - ['scb_5fcfsr_5fmmarvalid_5fpos_56',['SCB_CFSR_MMARVALID_Pos',['../group___c_m_s_i_s___s_c_b.html#gaf9a595a3a8e0171473d486b490669165',1,'core_cm4_matlab.h']]], - ['scb_5fcfsr_5fmstkerr_5fmsk_57',['SCB_CFSR_MSTKERR_Msk',['../group___c_m_s_i_s___s_c_b.html#ga30331822fa13db8ee288173cfbcbbf72',1,'core_cm4_matlab.h']]], - ['scb_5fcfsr_5fmstkerr_5fpos_58',['SCB_CFSR_MSTKERR_Pos',['../group___c_m_s_i_s___s_c_b.html#ga76517c60f54396e7cf075876e8af7a62',1,'core_cm4_matlab.h']]], - ['scb_5fcfsr_5fmunstkerr_5fmsk_59',['SCB_CFSR_MUNSTKERR_Msk',['../group___c_m_s_i_s___s_c_b.html#ga2d77850270c5ca96e63e456315609876',1,'core_cm4_matlab.h']]], - ['scb_5fcfsr_5fmunstkerr_5fpos_60',['SCB_CFSR_MUNSTKERR_Pos',['../group___c_m_s_i_s___s_c_b.html#ga9e5bd9bcd654e271a3e78c5c0a39444d',1,'core_cm4_matlab.h']]], - ['scb_5fcfsr_5fnocp_5fmsk_61',['SCB_CFSR_NOCP_Msk',['../group___c_m_s_i_s___s_c_b.html#ga6cbafe22a9550ca20427cd7e2f2bed7f',1,'core_cm4_matlab.h']]], - ['scb_5fcfsr_5fnocp_5fpos_62',['SCB_CFSR_NOCP_Pos',['../group___c_m_s_i_s___s_c_b.html#ga769b841a38d4e7b8c5e7e74cf0455754',1,'core_cm4_matlab.h']]], - ['scb_5fcfsr_5fpreciserr_5fmsk_63',['SCB_CFSR_PRECISERR_Msk',['../group___c_m_s_i_s___s_c_b.html#gad8fc0d1f80364470e52d3dcf941f38cc',1,'core_cm4_matlab.h']]], - ['scb_5fcfsr_5fpreciserr_5fpos_64',['SCB_CFSR_PRECISERR_Pos',['../group___c_m_s_i_s___s_c_b.html#gaf4744e87d7f6eddbff803977901d6ad0',1,'core_cm4_matlab.h']]], - ['scb_5fcfsr_5fstkerr_5fmsk_65',['SCB_CFSR_STKERR_Msk',['../group___c_m_s_i_s___s_c_b.html#ga77076fdfa5941327d4d8f0cb99653872',1,'core_cm4_matlab.h']]], - ['scb_5fcfsr_5fstkerr_5fpos_66',['SCB_CFSR_STKERR_Pos',['../group___c_m_s_i_s___s_c_b.html#ga62a8fe875fb6cc28e0e36ddf27d81a8f',1,'core_cm4_matlab.h']]], - ['scb_5fcfsr_5funaligned_5fmsk_67',['SCB_CFSR_UNALIGNED_Msk',['../group___c_m_s_i_s___s_c_b.html#gac7d2aa508a08a2cab97aa8683c87d125',1,'core_cm4_matlab.h']]], - ['scb_5fcfsr_5funaligned_5fpos_68',['SCB_CFSR_UNALIGNED_Pos',['../group___c_m_s_i_s___s_c_b.html#ga8836da99a7e569d7a5a79ab4eaa85690',1,'core_cm4_matlab.h']]], - ['scb_5fcfsr_5fundefinstr_5fmsk_69',['SCB_CFSR_UNDEFINSTR_Msk',['../group___c_m_s_i_s___s_c_b.html#ga96e201c8da2bd76df35e184f31b89f1e',1,'core_cm4_matlab.h']]], - ['scb_5fcfsr_5fundefinstr_5fpos_70',['SCB_CFSR_UNDEFINSTR_Pos',['../group___c_m_s_i_s___s_c_b.html#ga28219a6a1ae6b6118ffd1682c362c63d',1,'core_cm4_matlab.h']]], - ['scb_5fcfsr_5funstkerr_5fmsk_71',['SCB_CFSR_UNSTKERR_Msk',['../group___c_m_s_i_s___s_c_b.html#ga2dfce5c289681884651f92377d09380e',1,'core_cm4_matlab.h']]], - ['scb_5fcfsr_5funstkerr_5fpos_72',['SCB_CFSR_UNSTKERR_Pos',['../group___c_m_s_i_s___s_c_b.html#ga7f70b590d3d8f11145e4ff20f7c9f3e8',1,'core_cm4_matlab.h']]], - ['scb_5fcfsr_5fusgfaultsr_5fmsk_73',['SCB_CFSR_USGFAULTSR_Msk',['../group___c_m_s_i_s___s_c_b.html#ga565807b1a3f31891f1f967d0fa30d03f',1,'core_cm4_matlab.h']]], - ['scb_5fcfsr_5fusgfaultsr_5fpos_74',['SCB_CFSR_USGFAULTSR_Pos',['../group___c_m_s_i_s___s_c_b.html#gac8e4197b295c8560e68e2d71285c7879',1,'core_cm4_matlab.h']]], - ['scb_5fcpuid_5farchitecture_5fmsk_75',['SCB_CPUID_ARCHITECTURE_Msk',['../group___c_m_s_i_s___s_c_b.html#gafae4a1f27a927338ae9dc51a0e146213',1,'core_cm4_matlab.h']]], - ['scb_5fcpuid_5farchitecture_5fpos_76',['SCB_CPUID_ARCHITECTURE_Pos',['../group___c_m_s_i_s___s_c_b.html#gaf8b3236b08fb8e840efb682645fb0e98',1,'core_cm4_matlab.h']]], - ['scb_5fcpuid_5fimplementer_5fmsk_77',['SCB_CPUID_IMPLEMENTER_Msk',['../group___c_m_s_i_s___s_c_b.html#ga0932b31faafd47656a03ced75a31d99b',1,'core_cm4_matlab.h']]], - ['scb_5fcpuid_5fimplementer_5fpos_78',['SCB_CPUID_IMPLEMENTER_Pos',['../group___c_m_s_i_s___s_c_b.html#ga58686b88f94f789d4e6f429fe1ff58cf',1,'core_cm4_matlab.h']]], - ['scb_5fcpuid_5fpartno_5fmsk_79',['SCB_CPUID_PARTNO_Msk',['../group___c_m_s_i_s___s_c_b.html#ga98e581423ca016680c238c469aba546d',1,'core_cm4_matlab.h']]], - ['scb_5fcpuid_5fpartno_5fpos_80',['SCB_CPUID_PARTNO_Pos',['../group___c_m_s_i_s___s_c_b.html#ga705f68eaa9afb042ca2407dc4e4629ac',1,'core_cm4_matlab.h']]], - ['scb_5fcpuid_5frevision_5fmsk_81',['SCB_CPUID_REVISION_Msk',['../group___c_m_s_i_s___s_c_b.html#ga2ec0448b6483f77e7f5d08b4b81d85df',1,'core_cm4_matlab.h']]], - ['scb_5fcpuid_5frevision_5fpos_82',['SCB_CPUID_REVISION_Pos',['../group___c_m_s_i_s___s_c_b.html#ga3c3d9071e574de11fb27ba57034838b1',1,'core_cm4_matlab.h']]], - ['scb_5fcpuid_5fvariant_5fmsk_83',['SCB_CPUID_VARIANT_Msk',['../group___c_m_s_i_s___s_c_b.html#gad358dfbd04300afc1824329d128b99e8',1,'core_cm4_matlab.h']]], - ['scb_5fcpuid_5fvariant_5fpos_84',['SCB_CPUID_VARIANT_Pos',['../group___c_m_s_i_s___s_c_b.html#ga104462bd0815391b4044a70bd15d3a71',1,'core_cm4_matlab.h']]], - ['scb_5fdfsr_5fbkpt_5fmsk_85',['SCB_DFSR_BKPT_Msk',['../group___c_m_s_i_s___s_c_b.html#ga609edf8f50bc49adb51ae28bcecefe1f',1,'core_cm4_matlab.h']]], - ['scb_5fdfsr_5fbkpt_5fpos_86',['SCB_DFSR_BKPT_Pos',['../group___c_m_s_i_s___s_c_b.html#gaf28fdce48655f0dcefb383aebf26b050',1,'core_cm4_matlab.h']]], - ['scb_5fdfsr_5fdwttrap_5fmsk_87',['SCB_DFSR_DWTTRAP_Msk',['../group___c_m_s_i_s___s_c_b.html#ga3f7384b8a761704655fd45396a305663',1,'core_cm4_matlab.h']]], - ['scb_5fdfsr_5fdwttrap_5fpos_88',['SCB_DFSR_DWTTRAP_Pos',['../group___c_m_s_i_s___s_c_b.html#gaccf82364c6d0ed7206f1084277b7cc61',1,'core_cm4_matlab.h']]], - ['scb_5fdfsr_5fexternal_5fmsk_89',['SCB_DFSR_EXTERNAL_Msk',['../group___c_m_s_i_s___s_c_b.html#ga3cba2ec1f588ce0b10b191d6b0d23399',1,'core_cm4_matlab.h']]], - ['scb_5fdfsr_5fexternal_5fpos_90',['SCB_DFSR_EXTERNAL_Pos',['../group___c_m_s_i_s___s_c_b.html#ga13f502fb5ac673df9c287488c40b0c1d',1,'core_cm4_matlab.h']]], - ['scb_5fdfsr_5fhalted_5fmsk_91',['SCB_DFSR_HALTED_Msk',['../group___c_m_s_i_s___s_c_b.html#ga200bcf918d57443b5e29e8ce552e4bdf',1,'core_cm4_matlab.h']]], - ['scb_5fdfsr_5fhalted_5fpos_92',['SCB_DFSR_HALTED_Pos',['../group___c_m_s_i_s___s_c_b.html#gaef4ec28427f9f88ac70a13ae4e541378',1,'core_cm4_matlab.h']]], - ['scb_5fdfsr_5fvcatch_5fmsk_93',['SCB_DFSR_VCATCH_Msk',['../group___c_m_s_i_s___s_c_b.html#gacbb931575c07b324ec793775b7c44d05',1,'core_cm4_matlab.h']]], - ['scb_5fdfsr_5fvcatch_5fpos_94',['SCB_DFSR_VCATCH_Pos',['../group___c_m_s_i_s___s_c_b.html#gad02d3eaf062ac184c18a7889c9b6de57',1,'core_cm4_matlab.h']]], - ['scb_5fgetfputype_95',['SCB_GetFPUType',['../group___c_m_s_i_s___core___fpu_functions.html#ga6bcad99ce80a0e7e4ddc6f2379081756',1,'core_cm4_matlab.h']]], - ['scb_5fhfsr_5fdebugevt_5fmsk_96',['SCB_HFSR_DEBUGEVT_Msk',['../group___c_m_s_i_s___s_c_b.html#gababd60e94756bb33929d5e6f25d8dba3',1,'core_cm4_matlab.h']]], - ['scb_5fhfsr_5fdebugevt_5fpos_97',['SCB_HFSR_DEBUGEVT_Pos',['../group___c_m_s_i_s___s_c_b.html#ga300c90cfb7b35c82b4d44ad16c757ffb',1,'core_cm4_matlab.h']]], - ['scb_5fhfsr_5fforced_5fmsk_98',['SCB_HFSR_FORCED_Msk',['../group___c_m_s_i_s___s_c_b.html#ga6560d97ed043bc01152a7247bafa3157',1,'core_cm4_matlab.h']]], - ['scb_5fhfsr_5fforced_5fpos_99',['SCB_HFSR_FORCED_Pos',['../group___c_m_s_i_s___s_c_b.html#gab361e54183a378474cb419ae2a55d6f4',1,'core_cm4_matlab.h']]], - ['scb_5fhfsr_5fvecttbl_5fmsk_100',['SCB_HFSR_VECTTBL_Msk',['../group___c_m_s_i_s___s_c_b.html#gaac5e289211d0a63fe879a9691cb9e1a9',1,'core_cm4_matlab.h']]], - ['scb_5fhfsr_5fvecttbl_5fpos_101',['SCB_HFSR_VECTTBL_Pos',['../group___c_m_s_i_s___s_c_b.html#ga77993da8de35adea7bda6a4475f036ab',1,'core_cm4_matlab.h']]], - ['scb_5ficsr_5fisrpending_5fmsk_102',['SCB_ICSR_ISRPENDING_Msk',['../group___c_m_s_i_s___s_c_b.html#ga056d74fd538e5d36d3be1f28d399c877',1,'core_cm4_matlab.h']]], - ['scb_5ficsr_5fisrpending_5fpos_103',['SCB_ICSR_ISRPENDING_Pos',['../group___c_m_s_i_s___s_c_b.html#ga10749d92b9b744094b845c2eb46d4319',1,'core_cm4_matlab.h']]], - ['scb_5ficsr_5fisrpreempt_5fmsk_104',['SCB_ICSR_ISRPREEMPT_Msk',['../group___c_m_s_i_s___s_c_b.html#gaa966600396290808d596fe96e92ca2b5',1,'core_cm4_matlab.h']]], - ['scb_5ficsr_5fisrpreempt_5fpos_105',['SCB_ICSR_ISRPREEMPT_Pos',['../group___c_m_s_i_s___s_c_b.html#ga11cb5b1f9ce167b81f31787a77e575df',1,'core_cm4_matlab.h']]], - ['scb_5ficsr_5fnmipendset_5fmsk_106',['SCB_ICSR_NMIPENDSET_Msk',['../group___c_m_s_i_s___s_c_b.html#ga340e3f79e9c3607dee9f2c048b6b22e8',1,'core_cm4_matlab.h']]], - ['scb_5ficsr_5fnmipendset_5fpos_107',['SCB_ICSR_NMIPENDSET_Pos',['../group___c_m_s_i_s___s_c_b.html#ga750d4b52624a46d71356db4ea769573b',1,'core_cm4_matlab.h']]], - ['scb_5ficsr_5fpendstclr_5fmsk_108',['SCB_ICSR_PENDSTCLR_Msk',['../group___c_m_s_i_s___s_c_b.html#gab241827d2a793269d8cd99b9b28c2157',1,'core_cm4_matlab.h']]], - ['scb_5ficsr_5fpendstclr_5fpos_109',['SCB_ICSR_PENDSTCLR_Pos',['../group___c_m_s_i_s___s_c_b.html#gadbe25e4b333ece1341beb1a740168fdc',1,'core_cm4_matlab.h']]], - ['scb_5ficsr_5fpendstset_5fmsk_110',['SCB_ICSR_PENDSTSET_Msk',['../group___c_m_s_i_s___s_c_b.html#ga7325b61ea0ec323ef2d5c893b112e546',1,'core_cm4_matlab.h']]], - ['scb_5ficsr_5fpendstset_5fpos_111',['SCB_ICSR_PENDSTSET_Pos',['../group___c_m_s_i_s___s_c_b.html#ga9dbb3358c6167c9c3f85661b90fb2794',1,'core_cm4_matlab.h']]], - ['scb_5ficsr_5fpendsvclr_5fmsk_112',['SCB_ICSR_PENDSVCLR_Msk',['../group___c_m_s_i_s___s_c_b.html#ga4a901ace381d3c1c74ac82b22fae2e1e',1,'core_cm4_matlab.h']]], - ['scb_5ficsr_5fpendsvclr_5fpos_113',['SCB_ICSR_PENDSVCLR_Pos',['../group___c_m_s_i_s___s_c_b.html#gae218d9022288f89faf57187c4d542ecd',1,'core_cm4_matlab.h']]], - ['scb_5ficsr_5fpendsvset_5fmsk_114',['SCB_ICSR_PENDSVSET_Msk',['../group___c_m_s_i_s___s_c_b.html#ga1e40d93efb402763c8c00ddcc56724ff',1,'core_cm4_matlab.h']]], - ['scb_5ficsr_5fpendsvset_5fpos_115',['SCB_ICSR_PENDSVSET_Pos',['../group___c_m_s_i_s___s_c_b.html#gab5ded23d2ab1d5ff7cc7ce746205e9fe',1,'core_cm4_matlab.h']]], - ['scb_5ficsr_5frettobase_5fmsk_116',['SCB_ICSR_RETTOBASE_Msk',['../group___c_m_s_i_s___s_c_b.html#gaca6fc3f79bb550f64fd7df782ed4a5f6',1,'core_cm4_matlab.h']]], - ['scb_5ficsr_5frettobase_5fpos_117',['SCB_ICSR_RETTOBASE_Pos',['../group___c_m_s_i_s___s_c_b.html#ga403d154200242629e6d2764bfc12a7ec',1,'core_cm4_matlab.h']]], - ['scb_5ficsr_5fvectactive_5fmsk_118',['SCB_ICSR_VECTACTIVE_Msk',['../group___c_m_s_i_s___s_c_b.html#ga5533791a4ecf1b9301c883047b3e8396',1,'core_cm4_matlab.h']]], - ['scb_5ficsr_5fvectactive_5fpos_119',['SCB_ICSR_VECTACTIVE_Pos',['../group___c_m_s_i_s___s_c_b.html#gae4f602c7c5c895d5fb687b71b0979fc3',1,'core_cm4_matlab.h']]], - ['scb_5ficsr_5fvectpending_5fmsk_120',['SCB_ICSR_VECTPENDING_Msk',['../group___c_m_s_i_s___s_c_b.html#gacb6992e7c7ddc27a370f62878a21ef72',1,'core_cm4_matlab.h']]], - ['scb_5ficsr_5fvectpending_5fpos_121',['SCB_ICSR_VECTPENDING_Pos',['../group___c_m_s_i_s___s_c_b.html#gada60c92bf88d6fd21a8f49efa4a127b8',1,'core_cm4_matlab.h']]], - ['scb_5fscr_5fsevonpend_5fmsk_122',['SCB_SCR_SEVONPEND_Msk',['../group___c_m_s_i_s___s_c_b.html#gafb98656644a14342e467505f69a997c9',1,'core_cm4_matlab.h']]], - ['scb_5fscr_5fsevonpend_5fpos_123',['SCB_SCR_SEVONPEND_Pos',['../group___c_m_s_i_s___s_c_b.html#ga3bddcec40aeaf3d3a998446100fa0e44',1,'core_cm4_matlab.h']]], - ['scb_5fscr_5fsleepdeep_5fmsk_124',['SCB_SCR_SLEEPDEEP_Msk',['../group___c_m_s_i_s___s_c_b.html#ga77c06a69c63f4b3f6ec1032e911e18e7',1,'core_cm4_matlab.h']]], - ['scb_5fscr_5fsleepdeep_5fpos_125',['SCB_SCR_SLEEPDEEP_Pos',['../group___c_m_s_i_s___s_c_b.html#gab304f6258ec03bd9a6e7a360515c3cfe',1,'core_cm4_matlab.h']]], - ['scb_5fscr_5fsleeponexit_5fmsk_126',['SCB_SCR_SLEEPONEXIT_Msk',['../group___c_m_s_i_s___s_c_b.html#ga50a243e317b9a70781b02758d45b05ee',1,'core_cm4_matlab.h']]], - ['scb_5fscr_5fsleeponexit_5fpos_127',['SCB_SCR_SLEEPONEXIT_Pos',['../group___c_m_s_i_s___s_c_b.html#ga3680a15114d7fdc1e25043b881308fe9',1,'core_cm4_matlab.h']]], - ['scb_5fshcsr_5fbusfaultact_5fmsk_128',['SCB_SHCSR_BUSFAULTACT_Msk',['../group___c_m_s_i_s___s_c_b.html#ga9d7a8b1054b655ad08d85c3c535d4f73',1,'core_cm4_matlab.h']]], - ['scb_5fshcsr_5fbusfaultact_5fpos_129',['SCB_SHCSR_BUSFAULTACT_Pos',['../group___c_m_s_i_s___s_c_b.html#gaf272760f2df9ecdd8a5fbbd65c0b767a',1,'core_cm4_matlab.h']]], - ['scb_5fshcsr_5fbusfaultena_5fmsk_130',['SCB_SHCSR_BUSFAULTENA_Msk',['../group___c_m_s_i_s___s_c_b.html#ga43e8cbe619c9980e0d1aacc85d9b9e47',1,'core_cm4_matlab.h']]], - ['scb_5fshcsr_5fbusfaultena_5fpos_131',['SCB_SHCSR_BUSFAULTENA_Pos',['../group___c_m_s_i_s___s_c_b.html#ga3d32edbe4a5c0335f808cfc19ec7e844',1,'core_cm4_matlab.h']]], - ['scb_5fshcsr_5fbusfaultpended_5fmsk_132',['SCB_SHCSR_BUSFAULTPENDED_Msk',['../group___c_m_s_i_s___s_c_b.html#ga677c23749c4d348f30fb471d1223e783',1,'core_cm4_matlab.h']]], - ['scb_5fshcsr_5fbusfaultpended_5fpos_133',['SCB_SHCSR_BUSFAULTPENDED_Pos',['../group___c_m_s_i_s___s_c_b.html#gaa22551e24a72b65f1e817f7ab462203b',1,'core_cm4_matlab.h']]], - ['scb_5fshcsr_5fmemfaultact_5fmsk_134',['SCB_SHCSR_MEMFAULTACT_Msk',['../group___c_m_s_i_s___s_c_b.html#ga9147fd4e1b12394ae26eadf900a023a3',1,'core_cm4_matlab.h']]], - ['scb_5fshcsr_5fmemfaultact_5fpos_135',['SCB_SHCSR_MEMFAULTACT_Pos',['../group___c_m_s_i_s___s_c_b.html#ga7c856f79a75dcc1d1517b19a67691803',1,'core_cm4_matlab.h']]], - ['scb_5fshcsr_5fmemfaultena_5fmsk_136',['SCB_SHCSR_MEMFAULTENA_Msk',['../group___c_m_s_i_s___s_c_b.html#gaf084424fa1f69bea36a1c44899d83d17',1,'core_cm4_matlab.h']]], - ['scb_5fshcsr_5fmemfaultena_5fpos_137',['SCB_SHCSR_MEMFAULTENA_Pos',['../group___c_m_s_i_s___s_c_b.html#ga685b4564a8760b4506f14ec4307b7251',1,'core_cm4_matlab.h']]], - ['scb_5fshcsr_5fmemfaultpended_5fmsk_138',['SCB_SHCSR_MEMFAULTPENDED_Msk',['../group___c_m_s_i_s___s_c_b.html#ga9abc6c2e395f9e5af4ce05fc420fb04c',1,'core_cm4_matlab.h']]], - ['scb_5fshcsr_5fmemfaultpended_5fpos_139',['SCB_SHCSR_MEMFAULTPENDED_Pos',['../group___c_m_s_i_s___s_c_b.html#gaceb60fe2d8a8cb17fcd1c1f6b5aa924f',1,'core_cm4_matlab.h']]], - ['scb_5fshcsr_5fmonitoract_5fmsk_140',['SCB_SHCSR_MONITORACT_Msk',['../group___c_m_s_i_s___s_c_b.html#gaad09b4bc36e9bccccc2e110d20b16e1a',1,'core_cm4_matlab.h']]], - ['scb_5fshcsr_5fmonitoract_5fpos_141',['SCB_SHCSR_MONITORACT_Pos',['../group___c_m_s_i_s___s_c_b.html#ga8b71cf4c61803752a41c96deb00d26af',1,'core_cm4_matlab.h']]], - ['scb_5fshcsr_5fpendsvact_5fmsk_142',['SCB_SHCSR_PENDSVACT_Msk',['../group___c_m_s_i_s___s_c_b.html#gae0e837241a515d4cbadaaae1faa8e039',1,'core_cm4_matlab.h']]], - ['scb_5fshcsr_5fpendsvact_5fpos_143',['SCB_SHCSR_PENDSVACT_Pos',['../group___c_m_s_i_s___s_c_b.html#ga9b9fa69ce4c5ce7fe0861dbccfb15939',1,'core_cm4_matlab.h']]], - ['scb_5fshcsr_5fsvcallact_5fmsk_144',['SCB_SHCSR_SVCALLACT_Msk',['../group___c_m_s_i_s___s_c_b.html#ga634c0f69a233475289023ae5cb158fdf',1,'core_cm4_matlab.h']]], - ['scb_5fshcsr_5fsvcallact_5fpos_145',['SCB_SHCSR_SVCALLACT_Pos',['../group___c_m_s_i_s___s_c_b.html#ga977f5176be2bc8b123873861b38bc02f',1,'core_cm4_matlab.h']]], - ['scb_5fshcsr_5fsvcallpended_5fmsk_146',['SCB_SHCSR_SVCALLPENDED_Msk',['../group___c_m_s_i_s___s_c_b.html#ga6095a7acfbad66f52822b1392be88652',1,'core_cm4_matlab.h']]], - ['scb_5fshcsr_5fsvcallpended_5fpos_147',['SCB_SHCSR_SVCALLPENDED_Pos',['../group___c_m_s_i_s___s_c_b.html#ga2f93ec9b243f94cdd3e94b8f0bf43641',1,'core_cm4_matlab.h']]], - ['scb_5fshcsr_5fsystickact_5fmsk_148',['SCB_SHCSR_SYSTICKACT_Msk',['../group___c_m_s_i_s___s_c_b.html#gafef530088dc6d6bfc9f1893d52853684',1,'core_cm4_matlab.h']]], - ['scb_5fshcsr_5fsystickact_5fpos_149',['SCB_SHCSR_SYSTICKACT_Pos',['../group___c_m_s_i_s___s_c_b.html#gaec9ca3b1213c49e2442373445e1697de',1,'core_cm4_matlab.h']]], - ['scb_5fshcsr_5fusgfaultact_5fmsk_150',['SCB_SHCSR_USGFAULTACT_Msk',['../group___c_m_s_i_s___s_c_b.html#gab3166103b5a5f7931d0df90949c47dfe',1,'core_cm4_matlab.h']]], - ['scb_5fshcsr_5fusgfaultact_5fpos_151',['SCB_SHCSR_USGFAULTACT_Pos',['../group___c_m_s_i_s___s_c_b.html#gae06f54f5081f01ed3f6824e451ad3656',1,'core_cm4_matlab.h']]], - ['scb_5fshcsr_5fusgfaultena_5fmsk_152',['SCB_SHCSR_USGFAULTENA_Msk',['../group___c_m_s_i_s___s_c_b.html#ga056fb6be590857bbc029bed48b21dd79',1,'core_cm4_matlab.h']]], - ['scb_5fshcsr_5fusgfaultena_5fpos_153',['SCB_SHCSR_USGFAULTENA_Pos',['../group___c_m_s_i_s___s_c_b.html#gae71949507636fda388ec11d5c2d30b52',1,'core_cm4_matlab.h']]], - ['scb_5fshcsr_5fusgfaultpended_5fmsk_154',['SCB_SHCSR_USGFAULTPENDED_Msk',['../group___c_m_s_i_s___s_c_b.html#ga122b4f732732010895e438803a29d3cc',1,'core_cm4_matlab.h']]], - ['scb_5fshcsr_5fusgfaultpended_5fpos_155',['SCB_SHCSR_USGFAULTPENDED_Pos',['../group___c_m_s_i_s___s_c_b.html#ga3cf03acf1fdc2edc3b047ddd47ebbf87',1,'core_cm4_matlab.h']]], - ['scb_5ftype_156',['SCB_Type',['../struct_s_c_b___type.html',1,'']]], - ['scb_5fvtor_5ftbloff_5fmsk_157',['SCB_VTOR_TBLOFF_Msk',['../group___c_m_s_i_s___s_c_b.html#ga75e395ed74042923e8c93edf50f0996c',1,'core_cm4_matlab.h']]], - ['scb_5fvtor_5ftbloff_5fpos_158',['SCB_VTOR_TBLOFF_Pos',['../group___c_m_s_i_s___s_c_b.html#gac6a55451ddd38bffcff5a211d29cea78',1,'core_cm4_matlab.h']]], - ['scnscb_159',['SCnSCB',['../group___c_m_s_i_s__core__base.html#ga9fe0cd2eef83a8adad94490d9ecca63f',1,'SCnSCB: core_cm4_matlab.h'],['../group___c_m_s_i_s___s_cn_s_c_b.html',1,'System Controls not in SCB (SCnSCB)']]], - ['scnscb_5factlr_5fdisdefwbuf_5fmsk_160',['SCnSCB_ACTLR_DISDEFWBUF_Msk',['../group___c_m_s_i_s___s_cn_s_c_b.html#ga6cda7b7219232a008ec52cc8e89d5d08',1,'core_cm4_matlab.h']]], - ['scnscb_5factlr_5fdisdefwbuf_5fpos_161',['SCnSCB_ACTLR_DISDEFWBUF_Pos',['../group___c_m_s_i_s___s_cn_s_c_b.html#gafa2eb37493c0f8dae77cde81ecf80f77',1,'core_cm4_matlab.h']]], - ['scnscb_5factlr_5fdisfold_5fmsk_162',['SCnSCB_ACTLR_DISFOLD_Msk',['../group___c_m_s_i_s___s_cn_s_c_b.html#gaa9dd2d4a2350499188f438d0aa9fd982',1,'core_cm4_matlab.h']]], - ['scnscb_5factlr_5fdisfold_5fpos_163',['SCnSCB_ACTLR_DISFOLD_Pos',['../group___c_m_s_i_s___s_cn_s_c_b.html#gaab395870643a0bee78906bb15ca5bd02',1,'core_cm4_matlab.h']]], - ['scnscb_5factlr_5fdisfpca_5fmsk_164',['SCnSCB_ACTLR_DISFPCA_Msk',['../group___c_m_s_i_s___s_cn_s_c_b.html#ga10d5aa4a196dcde6f476016ece2c1b69',1,'core_cm4_matlab.h']]], - ['scnscb_5factlr_5fdisfpca_5fpos_165',['SCnSCB_ACTLR_DISFPCA_Pos',['../group___c_m_s_i_s___s_cn_s_c_b.html#gaa194809383bc72ecf3416d85709281d7',1,'core_cm4_matlab.h']]], - ['scnscb_5factlr_5fdismcycint_5fmsk_166',['SCnSCB_ACTLR_DISMCYCINT_Msk',['../group___c_m_s_i_s___s_cn_s_c_b.html#ga2a2818f0489ad10b6ea2964e899d4cbc',1,'core_cm4_matlab.h']]], - ['scnscb_5factlr_5fdismcycint_5fpos_167',['SCnSCB_ACTLR_DISMCYCINT_Pos',['../group___c_m_s_i_s___s_cn_s_c_b.html#gaaa3e79f5ead4a32c0ea742b2a9ffc0cd',1,'core_cm4_matlab.h']]], - ['scnscb_5factlr_5fdisoofp_5fmsk_168',['SCnSCB_ACTLR_DISOOFP_Msk',['../group___c_m_s_i_s___s_cn_s_c_b.html#ga1ecd6adafa43464d7097b132c19e8640',1,'core_cm4_matlab.h']]], - ['scnscb_5factlr_5fdisoofp_5fpos_169',['SCnSCB_ACTLR_DISOOFP_Pos',['../group___c_m_s_i_s___s_cn_s_c_b.html#gaff0b57464c60fea8182b903676f8de49',1,'core_cm4_matlab.h']]], - ['scnscb_5fictr_5fintlinesnum_5fmsk_170',['SCnSCB_ICTR_INTLINESNUM_Msk',['../group___c_m_s_i_s___s_cn_s_c_b.html#ga3efa0f5210051464e1034b19fc7b33c7',1,'core_cm4_matlab.h']]], - ['scnscb_5fictr_5fintlinesnum_5fpos_171',['SCnSCB_ICTR_INTLINESNUM_Pos',['../group___c_m_s_i_s___s_cn_s_c_b.html#ga0777ddf379af50f9ca41d40573bfffc5',1,'core_cm4_matlab.h']]], - ['scnscb_5ftype_172',['SCnSCB_Type',['../struct_s_cn_s_c_b___type.html',1,'']]], - ['scr_173',['SCR',['../group___c_m_s_i_s__core___debug_functions.html#gacac65f229cb3fcb5369a0a9e0393b8c0',1,'SCB_Type']]], - ['scs_5fbase_174',['SCS_BASE',['../group___c_m_s_i_s__core__base.html#ga3c14ed93192c8d9143322bbf77ebf770',1,'core_cm4_matlab.h']]], - ['scs_5fbase_5fshift_175',['SCS_BASE_SHIFT',['../group___c_m_s_i_s__core__base.html#ga48d67e0906624018a8dc1ff5409f31ca',1,'core_cm4_matlab.h']]], - ['sdio_176',['SDIO',['../group___peripheral__declaration.html#ga8149aa2760fffac16bc75216d5fd9331',1,'stm32f407xx_matlab.h']]], - ['sdio_177',['sdio',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga8b6edf2e7d9debf95d77d172c8c32cb7',1,'stm32f4xx_periph_registers.c']]], - ['sdio_5farg_5fcmdarg_178',['SDIO_ARG_CMDARG',['../group___peripheral___registers___bits___definition.html#ga2d917a4fdc7442e270c2c727df78b819',1,'stm32f407xx_matlab.h']]], - ['sdio_5farg_5fcmdarg_5fmsk_179',['SDIO_ARG_CMDARG_Msk',['../group___peripheral___registers___bits___definition.html#ga2c0c162d6eb9a15399e1fdc00a8a711f',1,'stm32f407xx_matlab.h']]], - ['sdio_5farg_5fcmdarg_5fpos_180',['SDIO_ARG_CMDARG_Pos',['../group___peripheral___registers___bits___definition.html#gafd212d9a3891e8c282f50e82c207cce7',1,'stm32f407xx_matlab.h']]], - ['sdio_5fbase_181',['SDIO_BASE',['../group___peripheral__memory__map.html#ga95dd0abbc6767893b4b02935fa846f52',1,'stm32f407xx_matlab.h']]], - ['sdio_5fclkcr_5fbypass_182',['SDIO_CLKCR_BYPASS',['../group___peripheral___registers___bits___definition.html#ga1f362c1d228156c50639d79b9be99c9b',1,'stm32f407xx_matlab.h']]], - ['sdio_5fclkcr_5fbypass_5fmsk_183',['SDIO_CLKCR_BYPASS_Msk',['../group___peripheral___registers___bits___definition.html#ga590aa2168f77032139685f5880229c2d',1,'stm32f407xx_matlab.h']]], - ['sdio_5fclkcr_5fbypass_5fpos_184',['SDIO_CLKCR_BYPASS_Pos',['../group___peripheral___registers___bits___definition.html#ga1d2200f69dd69acf657ed6f3711d5dad',1,'stm32f407xx_matlab.h']]], - ['sdio_5fclkcr_5fclkdiv_185',['SDIO_CLKCR_CLKDIV',['../group___peripheral___registers___bits___definition.html#ga316271d0147b22c6267fc563d4c24424',1,'stm32f407xx_matlab.h']]], - ['sdio_5fclkcr_5fclkdiv_5fmsk_186',['SDIO_CLKCR_CLKDIV_Msk',['../group___peripheral___registers___bits___definition.html#gaa9207dc12eed614d38a8faa4397a6c27',1,'stm32f407xx_matlab.h']]], - ['sdio_5fclkcr_5fclkdiv_5fpos_187',['SDIO_CLKCR_CLKDIV_Pos',['../group___peripheral___registers___bits___definition.html#ga5b024ad152edaf86ad825ab3fe7450dd',1,'stm32f407xx_matlab.h']]], - ['sdio_5fclkcr_5fclken_188',['SDIO_CLKCR_CLKEN',['../group___peripheral___registers___bits___definition.html#gaf27847573683f91dbfe387a2571b514f',1,'stm32f407xx_matlab.h']]], - ['sdio_5fclkcr_5fclken_5fmsk_189',['SDIO_CLKCR_CLKEN_Msk',['../group___peripheral___registers___bits___definition.html#ga0952e49876e16cf5b7a15c2523b210d7',1,'stm32f407xx_matlab.h']]], - ['sdio_5fclkcr_5fclken_5fpos_190',['SDIO_CLKCR_CLKEN_Pos',['../group___peripheral___registers___bits___definition.html#ga44234ca6af02a8e44da30f14f77acf09',1,'stm32f407xx_matlab.h']]], - ['sdio_5fclkcr_5fhwfc_5fen_191',['SDIO_CLKCR_HWFC_EN',['../group___peripheral___registers___bits___definition.html#ga693d7b533dd5a5a668bc13b4365b18dc',1,'stm32f407xx_matlab.h']]], - ['sdio_5fclkcr_5fhwfc_5fen_5fmsk_192',['SDIO_CLKCR_HWFC_EN_Msk',['../group___peripheral___registers___bits___definition.html#gaae43747a95ebebe7388114ed6990b976',1,'stm32f407xx_matlab.h']]], - ['sdio_5fclkcr_5fhwfc_5fen_5fpos_193',['SDIO_CLKCR_HWFC_EN_Pos',['../group___peripheral___registers___bits___definition.html#ga1318e107062a376681c0d8cdc18332f3',1,'stm32f407xx_matlab.h']]], - ['sdio_5fclkcr_5fnegedge_194',['SDIO_CLKCR_NEGEDGE',['../group___peripheral___registers___bits___definition.html#gad124bd76f6543497c90372e182ec48a2',1,'stm32f407xx_matlab.h']]], - ['sdio_5fclkcr_5fnegedge_5fmsk_195',['SDIO_CLKCR_NEGEDGE_Msk',['../group___peripheral___registers___bits___definition.html#ga5a4df6f204feaf9a52a36b6bbf8987ef',1,'stm32f407xx_matlab.h']]], - ['sdio_5fclkcr_5fnegedge_5fpos_196',['SDIO_CLKCR_NEGEDGE_Pos',['../group___peripheral___registers___bits___definition.html#gae3e9d0be4756855a1e5e9753a6605077',1,'stm32f407xx_matlab.h']]], - ['sdio_5fclkcr_5fpwrsav_197',['SDIO_CLKCR_PWRSAV',['../group___peripheral___registers___bits___definition.html#gafbb618f32aef2970fd8b8b285f7b4118',1,'stm32f407xx_matlab.h']]], - ['sdio_5fclkcr_5fpwrsav_5fmsk_198',['SDIO_CLKCR_PWRSAV_Msk',['../group___peripheral___registers___bits___definition.html#ga258035422cd74f19e644272dc0eb2fa8',1,'stm32f407xx_matlab.h']]], - ['sdio_5fclkcr_5fpwrsav_5fpos_199',['SDIO_CLKCR_PWRSAV_Pos',['../group___peripheral___registers___bits___definition.html#ga72c1fdc5e585d2846743b06743c76639',1,'stm32f407xx_matlab.h']]], - ['sdio_5fclkcr_5fwidbus_200',['SDIO_CLKCR_WIDBUS',['../group___peripheral___registers___bits___definition.html#gae9d57d7917c39bdc5309506e8c28b7d7',1,'stm32f407xx_matlab.h']]], - ['sdio_5fclkcr_5fwidbus_5f0_201',['SDIO_CLKCR_WIDBUS_0',['../group___peripheral___registers___bits___definition.html#gab532dbf366c3fb731488017b0a794151',1,'stm32f407xx_matlab.h']]], - ['sdio_5fclkcr_5fwidbus_5f1_202',['SDIO_CLKCR_WIDBUS_1',['../group___peripheral___registers___bits___definition.html#ga49f3e7998bca487f5354ef6f8dffbb21',1,'stm32f407xx_matlab.h']]], - ['sdio_5fclkcr_5fwidbus_5fmsk_203',['SDIO_CLKCR_WIDBUS_Msk',['../group___peripheral___registers___bits___definition.html#ga9d6f1ccab2c96629906dcf01ed68439f',1,'stm32f407xx_matlab.h']]], - ['sdio_5fclkcr_5fwidbus_5fpos_204',['SDIO_CLKCR_WIDBUS_Pos',['../group___peripheral___registers___bits___definition.html#ga9d70e8c1461dadda0df1d84176764b6d',1,'stm32f407xx_matlab.h']]], - ['sdio_5fcmd_5fceatacmd_205',['SDIO_CMD_CEATACMD',['../group___peripheral___registers___bits___definition.html#ga87422225274de986e7abe6b2a91a79c5',1,'stm32f407xx_matlab.h']]], - ['sdio_5fcmd_5fceatacmd_5fmsk_206',['SDIO_CMD_CEATACMD_Msk',['../group___peripheral___registers___bits___definition.html#ga68429f74d1213129ab97de545b433d83',1,'stm32f407xx_matlab.h']]], - ['sdio_5fcmd_5fceatacmd_5fpos_207',['SDIO_CMD_CEATACMD_Pos',['../group___peripheral___registers___bits___definition.html#ga9e4c944917a79c48b8393a4ca0208580',1,'stm32f407xx_matlab.h']]], - ['sdio_5fcmd_5fcmdindex_208',['SDIO_CMD_CMDINDEX',['../group___peripheral___registers___bits___definition.html#gaf91b593b5681a68db5ff9fd11600c9c8',1,'stm32f407xx_matlab.h']]], - ['sdio_5fcmd_5fcmdindex_5fmsk_209',['SDIO_CMD_CMDINDEX_Msk',['../group___peripheral___registers___bits___definition.html#ga5864df752017e82b545ecbef7a434000',1,'stm32f407xx_matlab.h']]], - ['sdio_5fcmd_5fcmdindex_5fpos_210',['SDIO_CMD_CMDINDEX_Pos',['../group___peripheral___registers___bits___definition.html#ga63a301afc3b24e6825aca5911f2292f7',1,'stm32f407xx_matlab.h']]], - ['sdio_5fcmd_5fcpsmen_211',['SDIO_CMD_CPSMEN',['../group___peripheral___registers___bits___definition.html#ga982f3fd09ce7e31709e0628b1fae86b8',1,'stm32f407xx_matlab.h']]], - ['sdio_5fcmd_5fcpsmen_5fmsk_212',['SDIO_CMD_CPSMEN_Msk',['../group___peripheral___registers___bits___definition.html#ga6f7c4c45069c802f2118cc0135d12dfe',1,'stm32f407xx_matlab.h']]], - ['sdio_5fcmd_5fcpsmen_5fpos_213',['SDIO_CMD_CPSMEN_Pos',['../group___peripheral___registers___bits___definition.html#ga0bcdcc89ef5863164462de6750a74caf',1,'stm32f407xx_matlab.h']]], - ['sdio_5fcmd_5fencmdcompl_214',['SDIO_CMD_ENCMDCOMPL',['../group___peripheral___registers___bits___definition.html#ga905b78ecf464857e6501ef5fd5e6ef1b',1,'stm32f407xx_matlab.h']]], - ['sdio_5fcmd_5fencmdcompl_5fmsk_215',['SDIO_CMD_ENCMDCOMPL_Msk',['../group___peripheral___registers___bits___definition.html#gafcf48c2b726056d5e994836644481617',1,'stm32f407xx_matlab.h']]], - ['sdio_5fcmd_5fencmdcompl_5fpos_216',['SDIO_CMD_ENCMDCOMPL_Pos',['../group___peripheral___registers___bits___definition.html#gae2bceb6b0e29e84ad08434948b17059c',1,'stm32f407xx_matlab.h']]], - ['sdio_5fcmd_5fnien_217',['SDIO_CMD_NIEN',['../group___peripheral___registers___bits___definition.html#ga3a9d5b2366ec7ca38db9d6d9f0f63f81',1,'stm32f407xx_matlab.h']]], - ['sdio_5fcmd_5fnien_5fmsk_218',['SDIO_CMD_NIEN_Msk',['../group___peripheral___registers___bits___definition.html#gaa07629f3e99beeb0e3d2ec96a6584f5a',1,'stm32f407xx_matlab.h']]], - ['sdio_5fcmd_5fnien_5fpos_219',['SDIO_CMD_NIEN_Pos',['../group___peripheral___registers___bits___definition.html#gacdc4381d56669dc173b95c161cf92954',1,'stm32f407xx_matlab.h']]], - ['sdio_5fcmd_5fsdiosuspend_220',['SDIO_CMD_SDIOSUSPEND',['../group___peripheral___registers___bits___definition.html#gad560080c3e7ab5aeafe151dafcc64368',1,'stm32f407xx_matlab.h']]], - ['sdio_5fcmd_5fsdiosuspend_5fmsk_221',['SDIO_CMD_SDIOSUSPEND_Msk',['../group___peripheral___registers___bits___definition.html#gaeecad1b553de683cb5cf9010d84b70d6',1,'stm32f407xx_matlab.h']]], - ['sdio_5fcmd_5fsdiosuspend_5fpos_222',['SDIO_CMD_SDIOSUSPEND_Pos',['../group___peripheral___registers___bits___definition.html#ga69aeafb35e44b4b432e71cd4cc29e15b',1,'stm32f407xx_matlab.h']]], - ['sdio_5fcmd_5fwaitint_223',['SDIO_CMD_WAITINT',['../group___peripheral___registers___bits___definition.html#ga4b037f34e297f38d56b14d46d008ef58',1,'stm32f407xx_matlab.h']]], - ['sdio_5fcmd_5fwaitint_5fmsk_224',['SDIO_CMD_WAITINT_Msk',['../group___peripheral___registers___bits___definition.html#ga214e7747364d52fe038e33df70453c7b',1,'stm32f407xx_matlab.h']]], - ['sdio_5fcmd_5fwaitint_5fpos_225',['SDIO_CMD_WAITINT_Pos',['../group___peripheral___registers___bits___definition.html#gad6a63d6e5b6dbabf23b6c8da0a3582c9',1,'stm32f407xx_matlab.h']]], - ['sdio_5fcmd_5fwaitpend_226',['SDIO_CMD_WAITPEND',['../group___peripheral___registers___bits___definition.html#gaf4118c9200bae6732764f6c87a0962a9',1,'stm32f407xx_matlab.h']]], - ['sdio_5fcmd_5fwaitpend_5fmsk_227',['SDIO_CMD_WAITPEND_Msk',['../group___peripheral___registers___bits___definition.html#gae565c2ebe48768e1e6a8638c5f8df583',1,'stm32f407xx_matlab.h']]], - ['sdio_5fcmd_5fwaitpend_5fpos_228',['SDIO_CMD_WAITPEND_Pos',['../group___peripheral___registers___bits___definition.html#ga5a1219464c590ed80ea38fcf28c8335a',1,'stm32f407xx_matlab.h']]], - ['sdio_5fcmd_5fwaitresp_229',['SDIO_CMD_WAITRESP',['../group___peripheral___registers___bits___definition.html#ga5d617f0e08d697c3b263e6a79f417d0f',1,'stm32f407xx_matlab.h']]], - ['sdio_5fcmd_5fwaitresp_5f0_230',['SDIO_CMD_WAITRESP_0',['../group___peripheral___registers___bits___definition.html#gae5797a389fecf611dccd483658b822fa',1,'stm32f407xx_matlab.h']]], - ['sdio_5fcmd_5fwaitresp_5f1_231',['SDIO_CMD_WAITRESP_1',['../group___peripheral___registers___bits___definition.html#ga8f5457b48feda0056466e5c380c44373',1,'stm32f407xx_matlab.h']]], - ['sdio_5fcmd_5fwaitresp_5fmsk_232',['SDIO_CMD_WAITRESP_Msk',['../group___peripheral___registers___bits___definition.html#ga41c83bc85012033738be4722741c644e',1,'stm32f407xx_matlab.h']]], - ['sdio_5fcmd_5fwaitresp_5fpos_233',['SDIO_CMD_WAITRESP_Pos',['../group___peripheral___registers___bits___definition.html#gada8d884fac89d07c59f335635ba5cc6a',1,'stm32f407xx_matlab.h']]], - ['sdio_5fdcount_5fdatacount_234',['SDIO_DCOUNT_DATACOUNT',['../group___peripheral___registers___bits___definition.html#ga2f8ab9dfe9d4f809b61fa2b7826adbde',1,'stm32f407xx_matlab.h']]], - ['sdio_5fdcount_5fdatacount_5fmsk_235',['SDIO_DCOUNT_DATACOUNT_Msk',['../group___peripheral___registers___bits___definition.html#gac482f1add1ce39f8fb7c3bc9d8653f77',1,'stm32f407xx_matlab.h']]], - ['sdio_5fdcount_5fdatacount_5fpos_236',['SDIO_DCOUNT_DATACOUNT_Pos',['../group___peripheral___registers___bits___definition.html#ga403440b7adc8fe670be0dc8786a0911b',1,'stm32f407xx_matlab.h']]], - ['sdio_5fdctrl_5fdblocksize_237',['SDIO_DCTRL_DBLOCKSIZE',['../group___peripheral___registers___bits___definition.html#ga948072d8a6db53d0c377944523a4b15a',1,'stm32f407xx_matlab.h']]], - ['sdio_5fdctrl_5fdblocksize_5f0_238',['SDIO_DCTRL_DBLOCKSIZE_0',['../group___peripheral___registers___bits___definition.html#ga51e2cb99cf325bb32c8910204b1507db',1,'stm32f407xx_matlab.h']]], - ['sdio_5fdctrl_5fdblocksize_5f1_239',['SDIO_DCTRL_DBLOCKSIZE_1',['../group___peripheral___registers___bits___definition.html#ga0add3ad2b72a21e7f8d48da3ea0b3d0f',1,'stm32f407xx_matlab.h']]], - ['sdio_5fdctrl_5fdblocksize_5f2_240',['SDIO_DCTRL_DBLOCKSIZE_2',['../group___peripheral___registers___bits___definition.html#ga93825036eceb86872e2ca179c63163ec',1,'stm32f407xx_matlab.h']]], - ['sdio_5fdctrl_5fdblocksize_5f3_241',['SDIO_DCTRL_DBLOCKSIZE_3',['../group___peripheral___registers___bits___definition.html#gac2025aa63b595bfccc747b99caec8799',1,'stm32f407xx_matlab.h']]], - ['sdio_5fdctrl_5fdblocksize_5fmsk_242',['SDIO_DCTRL_DBLOCKSIZE_Msk',['../group___peripheral___registers___bits___definition.html#gaed2493217bf1583aa33c8f1d755904a6',1,'stm32f407xx_matlab.h']]], - ['sdio_5fdctrl_5fdblocksize_5fpos_243',['SDIO_DCTRL_DBLOCKSIZE_Pos',['../group___peripheral___registers___bits___definition.html#ga119e44ccdca8f6bad3f3ad773bdd37c4',1,'stm32f407xx_matlab.h']]], - ['sdio_5fdctrl_5fdmaen_244',['SDIO_DCTRL_DMAEN',['../group___peripheral___registers___bits___definition.html#ga03a2148910ae02dde7e4cd63e0f5e008',1,'stm32f407xx_matlab.h']]], - ['sdio_5fdctrl_5fdmaen_5fmsk_245',['SDIO_DCTRL_DMAEN_Msk',['../group___peripheral___registers___bits___definition.html#ga947764dd929d0a703312d684ea22f214',1,'stm32f407xx_matlab.h']]], - ['sdio_5fdctrl_5fdmaen_5fpos_246',['SDIO_DCTRL_DMAEN_Pos',['../group___peripheral___registers___bits___definition.html#ga69e2071d77bd39d1d206ad785ea4b1f7',1,'stm32f407xx_matlab.h']]], - ['sdio_5fdctrl_5fdtdir_247',['SDIO_DCTRL_DTDIR',['../group___peripheral___registers___bits___definition.html#ga801fe27f7175a308d56776db19776c93',1,'stm32f407xx_matlab.h']]], - ['sdio_5fdctrl_5fdtdir_5fmsk_248',['SDIO_DCTRL_DTDIR_Msk',['../group___peripheral___registers___bits___definition.html#ga5f8fcebfcdcd58383a72b8503f74597f',1,'stm32f407xx_matlab.h']]], - ['sdio_5fdctrl_5fdtdir_5fpos_249',['SDIO_DCTRL_DTDIR_Pos',['../group___peripheral___registers___bits___definition.html#ga306751502891360398d0046e484e418b',1,'stm32f407xx_matlab.h']]], - ['sdio_5fdctrl_5fdten_250',['SDIO_DCTRL_DTEN',['../group___peripheral___registers___bits___definition.html#gaa03ff8fb9ff70e0a623a5c1f7aa2bc9a',1,'stm32f407xx_matlab.h']]], - ['sdio_5fdctrl_5fdten_5fmsk_251',['SDIO_DCTRL_DTEN_Msk',['../group___peripheral___registers___bits___definition.html#ga01116e33cb68129902284211af9f0e2e',1,'stm32f407xx_matlab.h']]], - ['sdio_5fdctrl_5fdten_5fpos_252',['SDIO_DCTRL_DTEN_Pos',['../group___peripheral___registers___bits___definition.html#gac5833159c058fcd329336b2259f33d20',1,'stm32f407xx_matlab.h']]], - ['sdio_5fdctrl_5fdtmode_253',['SDIO_DCTRL_DTMODE',['../group___peripheral___registers___bits___definition.html#gaa90cd50ae364b992ca8ccab319eb5513',1,'stm32f407xx_matlab.h']]], - ['sdio_5fdctrl_5fdtmode_5fmsk_254',['SDIO_DCTRL_DTMODE_Msk',['../group___peripheral___registers___bits___definition.html#ga78a712204e817e6ce1a96ffa421107fb',1,'stm32f407xx_matlab.h']]], - ['sdio_5fdctrl_5fdtmode_5fpos_255',['SDIO_DCTRL_DTMODE_Pos',['../group___peripheral___registers___bits___definition.html#gaa6f10964c5da8676885eda5000d33c1a',1,'stm32f407xx_matlab.h']]], - ['sdio_5fdctrl_5frwmod_256',['SDIO_DCTRL_RWMOD',['../group___peripheral___registers___bits___definition.html#ga4bf721a25f656b3de6fa0b0fe32edb6a',1,'stm32f407xx_matlab.h']]], - ['sdio_5fdctrl_5frwmod_5fmsk_257',['SDIO_DCTRL_RWMOD_Msk',['../group___peripheral___registers___bits___definition.html#ga5cbe9685d3f55431f7492463b902655b',1,'stm32f407xx_matlab.h']]], - ['sdio_5fdctrl_5frwmod_5fpos_258',['SDIO_DCTRL_RWMOD_Pos',['../group___peripheral___registers___bits___definition.html#ga0745b75ed0809ab27ddee511b7821595',1,'stm32f407xx_matlab.h']]], - ['sdio_5fdctrl_5frwstart_259',['SDIO_DCTRL_RWSTART',['../group___peripheral___registers___bits___definition.html#gafe9600da3e751118d49ea14ce44e91b9',1,'stm32f407xx_matlab.h']]], - ['sdio_5fdctrl_5frwstart_5fmsk_260',['SDIO_DCTRL_RWSTART_Msk',['../group___peripheral___registers___bits___definition.html#gad7c075ad5172d81d8a0ebbba7bd368a1',1,'stm32f407xx_matlab.h']]], - ['sdio_5fdctrl_5frwstart_5fpos_261',['SDIO_DCTRL_RWSTART_Pos',['../group___peripheral___registers___bits___definition.html#ga2799704f4cb1d6a7165360302ad5487e',1,'stm32f407xx_matlab.h']]], - ['sdio_5fdctrl_5frwstop_262',['SDIO_DCTRL_RWSTOP',['../group___peripheral___registers___bits___definition.html#ga3f1b5b6a32ce712fbb3767090b1b045e',1,'stm32f407xx_matlab.h']]], - ['sdio_5fdctrl_5frwstop_5fmsk_263',['SDIO_DCTRL_RWSTOP_Msk',['../group___peripheral___registers___bits___definition.html#ga4b25f8c2f40d6767bd6b61edb4891e7b',1,'stm32f407xx_matlab.h']]], - ['sdio_5fdctrl_5frwstop_5fpos_264',['SDIO_DCTRL_RWSTOP_Pos',['../group___peripheral___registers___bits___definition.html#ga22dbec68a4c108406a71258aa0b42cba',1,'stm32f407xx_matlab.h']]], - ['sdio_5fdctrl_5fsdioen_265',['SDIO_DCTRL_SDIOEN',['../group___peripheral___registers___bits___definition.html#gaa16b4c4037cf974162a591aea753fc21',1,'stm32f407xx_matlab.h']]], - ['sdio_5fdctrl_5fsdioen_5fmsk_266',['SDIO_DCTRL_SDIOEN_Msk',['../group___peripheral___registers___bits___definition.html#gafbedb5de0b884547782c44dc914795c9',1,'stm32f407xx_matlab.h']]], - ['sdio_5fdctrl_5fsdioen_5fpos_267',['SDIO_DCTRL_SDIOEN_Pos',['../group___peripheral___registers___bits___definition.html#ga998b276365f499e3af5dc3e784c728bf',1,'stm32f407xx_matlab.h']]], - ['sdio_5fdlen_5fdatalength_268',['SDIO_DLEN_DATALENGTH',['../group___peripheral___registers___bits___definition.html#ga4d3b07bca9aec8ef5456ba9b73f13adb',1,'stm32f407xx_matlab.h']]], - ['sdio_5fdlen_5fdatalength_5fmsk_269',['SDIO_DLEN_DATALENGTH_Msk',['../group___peripheral___registers___bits___definition.html#ga5c419dbe5ccdf09fe276a876c5b644cf',1,'stm32f407xx_matlab.h']]], - ['sdio_5fdlen_5fdatalength_5fpos_270',['SDIO_DLEN_DATALENGTH_Pos',['../group___peripheral___registers___bits___definition.html#gabb3ed134b1944407d86a64baff57bfbc',1,'stm32f407xx_matlab.h']]], - ['sdio_5fdtimer_5fdatatime_271',['SDIO_DTIMER_DATATIME',['../group___peripheral___registers___bits___definition.html#ga27e45eea9ce17b7251f10ea763180690',1,'stm32f407xx_matlab.h']]], - ['sdio_5fdtimer_5fdatatime_5fmsk_272',['SDIO_DTIMER_DATATIME_Msk',['../group___peripheral___registers___bits___definition.html#ga8ca7786fe8c3ebf5bf4b107ad2693b77',1,'stm32f407xx_matlab.h']]], - ['sdio_5fdtimer_5fdatatime_5fpos_273',['SDIO_DTIMER_DATATIME_Pos',['../group___peripheral___registers___bits___definition.html#ga5fe60be41b16f6fb05af07517115eda1',1,'stm32f407xx_matlab.h']]], - ['sdio_5ffifo_5ffifodata_274',['SDIO_FIFO_FIFODATA',['../group___peripheral___registers___bits___definition.html#ga5fc0d1e12c55398e2881fe917672da25',1,'stm32f407xx_matlab.h']]], - ['sdio_5ffifo_5ffifodata_5fmsk_275',['SDIO_FIFO_FIFODATA_Msk',['../group___peripheral___registers___bits___definition.html#gaf2000ca9b6103ee2ad7588b34283cfff',1,'stm32f407xx_matlab.h']]], - ['sdio_5ffifo_5ffifodata_5fpos_276',['SDIO_FIFO_FIFODATA_Pos',['../group___peripheral___registers___bits___definition.html#ga801e95e916e2fefcab25aad333e63c0c',1,'stm32f407xx_matlab.h']]], - ['sdio_5ffifocnt_5ffifocount_277',['SDIO_FIFOCNT_FIFOCOUNT',['../group___peripheral___registers___bits___definition.html#gaa45f5e0a2be89267f79cad57f456f0a2',1,'stm32f407xx_matlab.h']]], - ['sdio_5ffifocnt_5ffifocount_5fmsk_278',['SDIO_FIFOCNT_FIFOCOUNT_Msk',['../group___peripheral___registers___bits___definition.html#ga8f6da07732f3b3e77ffabfed13a613ea',1,'stm32f407xx_matlab.h']]], - ['sdio_5ffifocnt_5ffifocount_5fpos_279',['SDIO_FIFOCNT_FIFOCOUNT_Pos',['../group___peripheral___registers___bits___definition.html#ga078938dbe175e28e4d3898a04db76fc9',1,'stm32f407xx_matlab.h']]], - ['sdio_5ficr_5fccrcfailc_280',['SDIO_ICR_CCRCFAILC',['../group___peripheral___registers___bits___definition.html#ga44708c45f675cf065f1c7fc9311d6e43',1,'stm32f407xx_matlab.h']]], - ['sdio_5ficr_5fccrcfailc_5fmsk_281',['SDIO_ICR_CCRCFAILC_Msk',['../group___peripheral___registers___bits___definition.html#gac9217341f3df0a8ff9f874c86a12ce2b',1,'stm32f407xx_matlab.h']]], - ['sdio_5ficr_5fccrcfailc_5fpos_282',['SDIO_ICR_CCRCFAILC_Pos',['../group___peripheral___registers___bits___definition.html#gab10c6948f7bdd82257df5c11a367162c',1,'stm32f407xx_matlab.h']]], - ['sdio_5ficr_5fceataendc_283',['SDIO_ICR_CEATAENDC',['../group___peripheral___registers___bits___definition.html#ga6f1cebd40fd1eafb59635b284c5a3f34',1,'stm32f407xx_matlab.h']]], - ['sdio_5ficr_5fceataendc_5fmsk_284',['SDIO_ICR_CEATAENDC_Msk',['../group___peripheral___registers___bits___definition.html#ga51b6347d4f3229d35547e5ce5a27f481',1,'stm32f407xx_matlab.h']]], - ['sdio_5ficr_5fceataendc_5fpos_285',['SDIO_ICR_CEATAENDC_Pos',['../group___peripheral___registers___bits___definition.html#ga3cb5a4fcac3d143b45a4a0092c3f3664',1,'stm32f407xx_matlab.h']]], - ['sdio_5ficr_5fcmdrendc_286',['SDIO_ICR_CMDRENDC',['../group___peripheral___registers___bits___definition.html#ga8fb5c67aef48d5ee27b60107d938a58f',1,'stm32f407xx_matlab.h']]], - ['sdio_5ficr_5fcmdrendc_5fmsk_287',['SDIO_ICR_CMDRENDC_Msk',['../group___peripheral___registers___bits___definition.html#ga338691a5f364aa9d5c2e31741bf5e520',1,'stm32f407xx_matlab.h']]], - ['sdio_5ficr_5fcmdrendc_5fpos_288',['SDIO_ICR_CMDRENDC_Pos',['../group___peripheral___registers___bits___definition.html#ga24e00e57f1e28f8983ec21d94adbcdd7',1,'stm32f407xx_matlab.h']]], - ['sdio_5ficr_5fcmdsentc_289',['SDIO_ICR_CMDSENTC',['../group___peripheral___registers___bits___definition.html#gaa27fe45ef7461caf704186630b26a196',1,'stm32f407xx_matlab.h']]], - ['sdio_5ficr_5fcmdsentc_5fmsk_290',['SDIO_ICR_CMDSENTC_Msk',['../group___peripheral___registers___bits___definition.html#ga5f77128e853dcdb4202ef930d242cc80',1,'stm32f407xx_matlab.h']]], - ['sdio_5ficr_5fcmdsentc_5fpos_291',['SDIO_ICR_CMDSENTC_Pos',['../group___peripheral___registers___bits___definition.html#gadbd31121662a8f43e9d1e93f7809a78c',1,'stm32f407xx_matlab.h']]], - ['sdio_5ficr_5fctimeoutc_292',['SDIO_ICR_CTIMEOUTC',['../group___peripheral___registers___bits___definition.html#gac4d128bee8a97ae9971d42f844d2e297',1,'stm32f407xx_matlab.h']]], - ['sdio_5ficr_5fctimeoutc_5fmsk_293',['SDIO_ICR_CTIMEOUTC_Msk',['../group___peripheral___registers___bits___definition.html#ga5e808d2c69f391700674c1a5e438b453',1,'stm32f407xx_matlab.h']]], - ['sdio_5ficr_5fctimeoutc_5fpos_294',['SDIO_ICR_CTIMEOUTC_Pos',['../group___peripheral___registers___bits___definition.html#ga96cc705eed0b33038e018d6b72096de3',1,'stm32f407xx_matlab.h']]], - ['sdio_5ficr_5fdataendc_295',['SDIO_ICR_DATAENDC',['../group___peripheral___registers___bits___definition.html#ga527e1f9cd295845d5be9975cf26bae7e',1,'stm32f407xx_matlab.h']]], - ['sdio_5ficr_5fdataendc_5fmsk_296',['SDIO_ICR_DATAENDC_Msk',['../group___peripheral___registers___bits___definition.html#ga7f3222f8b80e53b265fca0c903baaf3f',1,'stm32f407xx_matlab.h']]], - ['sdio_5ficr_5fdataendc_5fpos_297',['SDIO_ICR_DATAENDC_Pos',['../group___peripheral___registers___bits___definition.html#ga8762bbd49f834e5cda527dada339a4ca',1,'stm32f407xx_matlab.h']]], - ['sdio_5ficr_5fdbckendc_298',['SDIO_ICR_DBCKENDC',['../group___peripheral___registers___bits___definition.html#gadc5518c07e39dc1f91603737d1a7180b',1,'stm32f407xx_matlab.h']]], - ['sdio_5ficr_5fdbckendc_5fmsk_299',['SDIO_ICR_DBCKENDC_Msk',['../group___peripheral___registers___bits___definition.html#ga79f2c2204f0e3ea155189811ce855802',1,'stm32f407xx_matlab.h']]], - ['sdio_5ficr_5fdbckendc_5fpos_300',['SDIO_ICR_DBCKENDC_Pos',['../group___peripheral___registers___bits___definition.html#ga5a5675867470f147be32bd684344d6c5',1,'stm32f407xx_matlab.h']]], - ['sdio_5ficr_5fdcrcfailc_301',['SDIO_ICR_DCRCFAILC',['../group___peripheral___registers___bits___definition.html#ga2cb6cde5f88a5d2b635a830dd401c4e0',1,'stm32f407xx_matlab.h']]], - ['sdio_5ficr_5fdcrcfailc_5fmsk_302',['SDIO_ICR_DCRCFAILC_Msk',['../group___peripheral___registers___bits___definition.html#gab1da8c0983fb1afa1403cbb59e453ad8',1,'stm32f407xx_matlab.h']]], - ['sdio_5ficr_5fdcrcfailc_5fpos_303',['SDIO_ICR_DCRCFAILC_Pos',['../group___peripheral___registers___bits___definition.html#ga4b4ddca0c23778a5863dceeb2bbfbeb2',1,'stm32f407xx_matlab.h']]], - ['sdio_5ficr_5fdtimeoutc_304',['SDIO_ICR_DTIMEOUTC',['../group___peripheral___registers___bits___definition.html#gadcb64d3d07a5841ee9f18ff6bc75350b',1,'stm32f407xx_matlab.h']]], - ['sdio_5ficr_5fdtimeoutc_5fmsk_305',['SDIO_ICR_DTIMEOUTC_Msk',['../group___peripheral___registers___bits___definition.html#ga8ca4ee048763e8a5a9205b8e3238ac2d',1,'stm32f407xx_matlab.h']]], - ['sdio_5ficr_5fdtimeoutc_5fpos_306',['SDIO_ICR_DTIMEOUTC_Pos',['../group___peripheral___registers___bits___definition.html#gada71c35f6df85b0c2193cf39745308fd',1,'stm32f407xx_matlab.h']]], - ['sdio_5ficr_5frxoverrc_307',['SDIO_ICR_RXOVERRC',['../group___peripheral___registers___bits___definition.html#ga2513d040c7695b152b0b423ad6f5c81e',1,'stm32f407xx_matlab.h']]], - ['sdio_5ficr_5frxoverrc_5fmsk_308',['SDIO_ICR_RXOVERRC_Msk',['../group___peripheral___registers___bits___definition.html#gafab6dbc8ca0e4e78139131e59683aad7',1,'stm32f407xx_matlab.h']]], - ['sdio_5ficr_5frxoverrc_5fpos_309',['SDIO_ICR_RXOVERRC_Pos',['../group___peripheral___registers___bits___definition.html#gae8ed5c5350b9bc9edb9043d7cc0feda3',1,'stm32f407xx_matlab.h']]], - ['sdio_5ficr_5fsdioitc_310',['SDIO_ICR_SDIOITC',['../group___peripheral___registers___bits___definition.html#ga2990db729fb017dfd659dc6cf8823761',1,'stm32f407xx_matlab.h']]], - ['sdio_5ficr_5fsdioitc_5fmsk_311',['SDIO_ICR_SDIOITC_Msk',['../group___peripheral___registers___bits___definition.html#ga6439a7e034a5af888f93c0e393119573',1,'stm32f407xx_matlab.h']]], - ['sdio_5ficr_5fsdioitc_5fpos_312',['SDIO_ICR_SDIOITC_Pos',['../group___peripheral___registers___bits___definition.html#ga2f237d6521d4dcdcb4bdb5049b4d8c16',1,'stm32f407xx_matlab.h']]], - ['sdio_5ficr_5fstbiterrc_313',['SDIO_ICR_STBITERRC',['../group___peripheral___registers___bits___definition.html#gae614b5ab8a8aecbc3c1ce74645cdc28c',1,'stm32f407xx_matlab.h']]], - ['sdio_5ficr_5fstbiterrc_5fmsk_314',['SDIO_ICR_STBITERRC_Msk',['../group___peripheral___registers___bits___definition.html#gaccd50f6a808007427eec1f2c823e78c5',1,'stm32f407xx_matlab.h']]], - ['sdio_5ficr_5fstbiterrc_5fpos_315',['SDIO_ICR_STBITERRC_Pos',['../group___peripheral___registers___bits___definition.html#ga374e5a92d4f2de580f73d098bba0dc52',1,'stm32f407xx_matlab.h']]], - ['sdio_5ficr_5ftxunderrc_316',['SDIO_ICR_TXUNDERRC',['../group___peripheral___registers___bits___definition.html#ga9628d77973f35d628924172831b029f8',1,'stm32f407xx_matlab.h']]], - ['sdio_5ficr_5ftxunderrc_5fmsk_317',['SDIO_ICR_TXUNDERRC_Msk',['../group___peripheral___registers___bits___definition.html#ga54a396bca8fa34f0e4d8387b814b9832',1,'stm32f407xx_matlab.h']]], - ['sdio_5ficr_5ftxunderrc_5fpos_318',['SDIO_ICR_TXUNDERRC_Pos',['../group___peripheral___registers___bits___definition.html#ga991a111fad2d762541ba63c49ac2a8b8',1,'stm32f407xx_matlab.h']]], - ['sdio_5firqn_319',['SDIO_IRQn',['../group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a16fe70a39348f3f27906dc268b5654e3',1,'stm32f407xx_matlab.h']]], - ['sdio_5fmask_5fccrcfailie_320',['SDIO_MASK_CCRCFAILIE',['../group___peripheral___registers___bits___definition.html#ga5e24d12a6c9af91337cb391d3ba698f3',1,'stm32f407xx_matlab.h']]], - ['sdio_5fmask_5fccrcfailie_5fmsk_321',['SDIO_MASK_CCRCFAILIE_Msk',['../group___peripheral___registers___bits___definition.html#gac74c97fa260e2834d977ab7537bdd4ef',1,'stm32f407xx_matlab.h']]], - ['sdio_5fmask_5fccrcfailie_5fpos_322',['SDIO_MASK_CCRCFAILIE_Pos',['../group___peripheral___registers___bits___definition.html#gafd6b95c5dfb466ba4fe1d6ba24a69167',1,'stm32f407xx_matlab.h']]], - ['sdio_5fmask_5fceataendie_323',['SDIO_MASK_CEATAENDIE',['../group___peripheral___registers___bits___definition.html#ga0a19dd3039888ebdc40b2406be400749',1,'stm32f407xx_matlab.h']]], - ['sdio_5fmask_5fceataendie_5fmsk_324',['SDIO_MASK_CEATAENDIE_Msk',['../group___peripheral___registers___bits___definition.html#ga7131c534b24505a7ec74cfbcd2d2fbca',1,'stm32f407xx_matlab.h']]], - ['sdio_5fmask_5fceataendie_5fpos_325',['SDIO_MASK_CEATAENDIE_Pos',['../group___peripheral___registers___bits___definition.html#gacc625ef424192b5a0875466d58b7d32a',1,'stm32f407xx_matlab.h']]], - ['sdio_5fmask_5fcmdactie_326',['SDIO_MASK_CMDACTIE',['../group___peripheral___registers___bits___definition.html#gad63b504f02ea0b1e5ec48962799fde88',1,'stm32f407xx_matlab.h']]], - ['sdio_5fmask_5fcmdactie_5fmsk_327',['SDIO_MASK_CMDACTIE_Msk',['../group___peripheral___registers___bits___definition.html#gae44d7772868e54b7a90f90a4a52520ec',1,'stm32f407xx_matlab.h']]], - ['sdio_5fmask_5fcmdactie_5fpos_328',['SDIO_MASK_CMDACTIE_Pos',['../group___peripheral___registers___bits___definition.html#ga2447a1963bd315c20f05574acd8efac0',1,'stm32f407xx_matlab.h']]], - ['sdio_5fmask_5fcmdrendie_329',['SDIO_MASK_CMDRENDIE',['../group___peripheral___registers___bits___definition.html#ga5fdedfc60a2019ff5f64533fcdd0c3f1',1,'stm32f407xx_matlab.h']]], - ['sdio_5fmask_5fcmdrendie_5fmsk_330',['SDIO_MASK_CMDRENDIE_Msk',['../group___peripheral___registers___bits___definition.html#ga74564e18483f0efdea46c242d9c3b3a5',1,'stm32f407xx_matlab.h']]], - ['sdio_5fmask_5fcmdrendie_5fpos_331',['SDIO_MASK_CMDRENDIE_Pos',['../group___peripheral___registers___bits___definition.html#gafbd0400c13633977796a92dd74adeaf9',1,'stm32f407xx_matlab.h']]], - ['sdio_5fmask_5fcmdsentie_332',['SDIO_MASK_CMDSENTIE',['../group___peripheral___registers___bits___definition.html#ga0d541aea02974c03bd8a8426125c35ff',1,'stm32f407xx_matlab.h']]], - ['sdio_5fmask_5fcmdsentie_5fmsk_333',['SDIO_MASK_CMDSENTIE_Msk',['../group___peripheral___registers___bits___definition.html#ga3cbd551da11e6e93c52b6727075baf9f',1,'stm32f407xx_matlab.h']]], - ['sdio_5fmask_5fcmdsentie_5fpos_334',['SDIO_MASK_CMDSENTIE_Pos',['../group___peripheral___registers___bits___definition.html#ga6ad32e7a435cc2eaaf3fb38a908a206e',1,'stm32f407xx_matlab.h']]], - ['sdio_5fmask_5fctimeoutie_335',['SDIO_MASK_CTIMEOUTIE',['../group___peripheral___registers___bits___definition.html#ga23f5a8c06e289522af0a679b08bdb014',1,'stm32f407xx_matlab.h']]], - ['sdio_5fmask_5fctimeoutie_5fmsk_336',['SDIO_MASK_CTIMEOUTIE_Msk',['../group___peripheral___registers___bits___definition.html#ga01b92fda0043d94bfef382fb74bf588b',1,'stm32f407xx_matlab.h']]], - ['sdio_5fmask_5fctimeoutie_5fpos_337',['SDIO_MASK_CTIMEOUTIE_Pos',['../group___peripheral___registers___bits___definition.html#ga6023176201d68b77f056f32e85d5e4fc',1,'stm32f407xx_matlab.h']]], - ['sdio_5fmask_5fdataendie_338',['SDIO_MASK_DATAENDIE',['../group___peripheral___registers___bits___definition.html#gae6398bd3e8312eea3b986ab59b80b466',1,'stm32f407xx_matlab.h']]], - ['sdio_5fmask_5fdataendie_5fmsk_339',['SDIO_MASK_DATAENDIE_Msk',['../group___peripheral___registers___bits___definition.html#ga28535e2fb4bbf3caf2764a47535e837f',1,'stm32f407xx_matlab.h']]], - ['sdio_5fmask_5fdataendie_5fpos_340',['SDIO_MASK_DATAENDIE_Pos',['../group___peripheral___registers___bits___definition.html#gae6fa6436185588c5ea061ea7f214e81f',1,'stm32f407xx_matlab.h']]], - ['sdio_5fmask_5fdbckendie_341',['SDIO_MASK_DBCKENDIE',['../group___peripheral___registers___bits___definition.html#ga947e5da36c9eeca0b48f3356067dff00',1,'stm32f407xx_matlab.h']]], - ['sdio_5fmask_5fdbckendie_5fmsk_342',['SDIO_MASK_DBCKENDIE_Msk',['../group___peripheral___registers___bits___definition.html#gaafd5167ec8f17f72e3d604c3f628bd06',1,'stm32f407xx_matlab.h']]], - ['sdio_5fmask_5fdbckendie_5fpos_343',['SDIO_MASK_DBCKENDIE_Pos',['../group___peripheral___registers___bits___definition.html#ga75e2c1e3ade0e06784c004b34410e9ef',1,'stm32f407xx_matlab.h']]], - ['sdio_5fmask_5fdcrcfailie_344',['SDIO_MASK_DCRCFAILIE',['../group___peripheral___registers___bits___definition.html#ga5e2e106a1f7792f054c6cc1f60906a09',1,'stm32f407xx_matlab.h']]], - ['sdio_5fmask_5fdcrcfailie_5fmsk_345',['SDIO_MASK_DCRCFAILIE_Msk',['../group___peripheral___registers___bits___definition.html#gafd0eb870977ae895b80ac57187a1d112',1,'stm32f407xx_matlab.h']]], - ['sdio_5fmask_5fdcrcfailie_5fpos_346',['SDIO_MASK_DCRCFAILIE_Pos',['../group___peripheral___registers___bits___definition.html#gaa3cc4b96a34db55f9e9862e615f8c243',1,'stm32f407xx_matlab.h']]], - ['sdio_5fmask_5fdtimeoutie_347',['SDIO_MASK_DTIMEOUTIE',['../group___peripheral___registers___bits___definition.html#ga7b4cc63338fe72abd76e5b399c47379b',1,'stm32f407xx_matlab.h']]], - ['sdio_5fmask_5fdtimeoutie_5fmsk_348',['SDIO_MASK_DTIMEOUTIE_Msk',['../group___peripheral___registers___bits___definition.html#gafc92448e7adf15a3410f4c0a4c760eeb',1,'stm32f407xx_matlab.h']]], - ['sdio_5fmask_5fdtimeoutie_5fpos_349',['SDIO_MASK_DTIMEOUTIE_Pos',['../group___peripheral___registers___bits___definition.html#ga6ee212e4944c5dd21acb553da80e84a5',1,'stm32f407xx_matlab.h']]], - ['sdio_5fmask_5frxactie_350',['SDIO_MASK_RXACTIE',['../group___peripheral___registers___bits___definition.html#ga9768c39a5d9d3c5519eb522c62a75eae',1,'stm32f407xx_matlab.h']]], - ['sdio_5fmask_5frxactie_5fmsk_351',['SDIO_MASK_RXACTIE_Msk',['../group___peripheral___registers___bits___definition.html#ga70e765da34a593f616c4435093d0a1d8',1,'stm32f407xx_matlab.h']]], - ['sdio_5fmask_5frxactie_5fpos_352',['SDIO_MASK_RXACTIE_Pos',['../group___peripheral___registers___bits___definition.html#ga243af5a2aca3b596fa214416a70f969f',1,'stm32f407xx_matlab.h']]], - ['sdio_5fmask_5frxdavlie_353',['SDIO_MASK_RXDAVLIE',['../group___peripheral___registers___bits___definition.html#gafa9da7d15902e6f94b79968a07250696',1,'stm32f407xx_matlab.h']]], - ['sdio_5fmask_5frxdavlie_5fmsk_354',['SDIO_MASK_RXDAVLIE_Msk',['../group___peripheral___registers___bits___definition.html#ga20d7d199042e90d08b1542fbf551d756',1,'stm32f407xx_matlab.h']]], - ['sdio_5fmask_5frxdavlie_5fpos_355',['SDIO_MASK_RXDAVLIE_Pos',['../group___peripheral___registers___bits___definition.html#gadb8703a3b6e980002afae732dc62f40e',1,'stm32f407xx_matlab.h']]], - ['sdio_5fmask_5frxfifoeie_356',['SDIO_MASK_RXFIFOEIE',['../group___peripheral___registers___bits___definition.html#gadbc23fa1c153a9e5216baeef7922e412',1,'stm32f407xx_matlab.h']]], - ['sdio_5fmask_5frxfifoeie_5fmsk_357',['SDIO_MASK_RXFIFOEIE_Msk',['../group___peripheral___registers___bits___definition.html#ga432a6fa01c2c45135e5d7c43fef9f21b',1,'stm32f407xx_matlab.h']]], - ['sdio_5fmask_5frxfifoeie_5fpos_358',['SDIO_MASK_RXFIFOEIE_Pos',['../group___peripheral___registers___bits___definition.html#gac80b2ced5391058cad7184a273b7c8fd',1,'stm32f407xx_matlab.h']]], - ['sdio_5fmask_5frxfifofie_359',['SDIO_MASK_RXFIFOFIE',['../group___peripheral___registers___bits___definition.html#gaf18c4bdf8fa4ee85596a89de00158fbb',1,'stm32f407xx_matlab.h']]], - ['sdio_5fmask_5frxfifofie_5fmsk_360',['SDIO_MASK_RXFIFOFIE_Msk',['../group___peripheral___registers___bits___definition.html#ga4550fadc2377f998ad61c94f37047e41',1,'stm32f407xx_matlab.h']]], - ['sdio_5fmask_5frxfifofie_5fpos_361',['SDIO_MASK_RXFIFOFIE_Pos',['../group___peripheral___registers___bits___definition.html#gadcac0bf1f49c1677a8fee6aab994a453',1,'stm32f407xx_matlab.h']]], - ['sdio_5fmask_5frxfifohfie_362',['SDIO_MASK_RXFIFOHFIE',['../group___peripheral___registers___bits___definition.html#ga04d50028fc671494508aecb04e727102',1,'stm32f407xx_matlab.h']]], - ['sdio_5fmask_5frxfifohfie_5fmsk_363',['SDIO_MASK_RXFIFOHFIE_Msk',['../group___peripheral___registers___bits___definition.html#ga4590335a3dcdb764c68d8f31bc58d2ba',1,'stm32f407xx_matlab.h']]], - ['sdio_5fmask_5frxfifohfie_5fpos_364',['SDIO_MASK_RXFIFOHFIE_Pos',['../group___peripheral___registers___bits___definition.html#gad002b428c2d95c229b914fac2a620ef8',1,'stm32f407xx_matlab.h']]], - ['sdio_5fmask_5frxoverrie_365',['SDIO_MASK_RXOVERRIE',['../group___peripheral___registers___bits___definition.html#ga39f494cf2a6af6ced9eaeac751ea81e4',1,'stm32f407xx_matlab.h']]], - ['sdio_5fmask_5frxoverrie_5fmsk_366',['SDIO_MASK_RXOVERRIE_Msk',['../group___peripheral___registers___bits___definition.html#ga1a0b758cbc6aed0e4a7633e451b55303',1,'stm32f407xx_matlab.h']]], - ['sdio_5fmask_5frxoverrie_5fpos_367',['SDIO_MASK_RXOVERRIE_Pos',['../group___peripheral___registers___bits___definition.html#ga15463333aaa2b90d2339b6dc4bd4e3ea',1,'stm32f407xx_matlab.h']]], - ['sdio_5fmask_5fsdioitie_368',['SDIO_MASK_SDIOITIE',['../group___peripheral___registers___bits___definition.html#gad73b7c7d480d2d71613995cfecc59138',1,'stm32f407xx_matlab.h']]], - ['sdio_5fmask_5fsdioitie_5fmsk_369',['SDIO_MASK_SDIOITIE_Msk',['../group___peripheral___registers___bits___definition.html#gab53292cf69bf87c65f8b41970b06c4fd',1,'stm32f407xx_matlab.h']]], - ['sdio_5fmask_5fsdioitie_5fpos_370',['SDIO_MASK_SDIOITIE_Pos',['../group___peripheral___registers___bits___definition.html#gac5b99a0d2f0e9d1629e5fe9904c8d042',1,'stm32f407xx_matlab.h']]], - ['sdio_5fmask_5fstbiterrie_371',['SDIO_MASK_STBITERRIE',['../group___peripheral___registers___bits___definition.html#ga4194bed51eb4a951a58a5d4062ba978f',1,'stm32f407xx_matlab.h']]], - ['sdio_5fmask_5fstbiterrie_5fmsk_372',['SDIO_MASK_STBITERRIE_Msk',['../group___peripheral___registers___bits___definition.html#gad0192872018530a05a2cec00d61a6a39',1,'stm32f407xx_matlab.h']]], - ['sdio_5fmask_5fstbiterrie_5fpos_373',['SDIO_MASK_STBITERRIE_Pos',['../group___peripheral___registers___bits___definition.html#ga962af1aaad7bc9eb55689d694b3949a4',1,'stm32f407xx_matlab.h']]], - ['sdio_5fmask_5ftxactie_374',['SDIO_MASK_TXACTIE',['../group___peripheral___registers___bits___definition.html#ga9bbfbc3f69ab77171eb1a0058783b1e0',1,'stm32f407xx_matlab.h']]], - ['sdio_5fmask_5ftxactie_5fmsk_375',['SDIO_MASK_TXACTIE_Msk',['../group___peripheral___registers___bits___definition.html#gad3bc5a7e08f3f427ccd7769c67233e5d',1,'stm32f407xx_matlab.h']]], - ['sdio_5fmask_5ftxactie_5fpos_376',['SDIO_MASK_TXACTIE_Pos',['../group___peripheral___registers___bits___definition.html#ga985a6a5e37ed6fb963deb83f0acd457b',1,'stm32f407xx_matlab.h']]], - ['sdio_5fmask_5ftxdavlie_377',['SDIO_MASK_TXDAVLIE',['../group___peripheral___registers___bits___definition.html#ga9a1988093a6df087ebb8ff41a51962da',1,'stm32f407xx_matlab.h']]], - ['sdio_5fmask_5ftxdavlie_5fmsk_378',['SDIO_MASK_TXDAVLIE_Msk',['../group___peripheral___registers___bits___definition.html#ga36e2a9aae5673ab117a1e33c2af0d801',1,'stm32f407xx_matlab.h']]], - ['sdio_5fmask_5ftxdavlie_5fpos_379',['SDIO_MASK_TXDAVLIE_Pos',['../group___peripheral___registers___bits___definition.html#ga5efa0b963adeda521a951841b9da44e5',1,'stm32f407xx_matlab.h']]], - ['sdio_5fmask_5ftxfifoeie_380',['SDIO_MASK_TXFIFOEIE',['../group___peripheral___registers___bits___definition.html#ga11e1d67150fad62dc1ca7783f3a19372',1,'stm32f407xx_matlab.h']]], - ['sdio_5fmask_5ftxfifoeie_5fmsk_381',['SDIO_MASK_TXFIFOEIE_Msk',['../group___peripheral___registers___bits___definition.html#ga05690f47ab17f3296f9e7c1f775546f1',1,'stm32f407xx_matlab.h']]], - ['sdio_5fmask_5ftxfifoeie_5fpos_382',['SDIO_MASK_TXFIFOEIE_Pos',['../group___peripheral___registers___bits___definition.html#ga1c795dfbbb4b28e0acdec9ad9ec7f590',1,'stm32f407xx_matlab.h']]], - ['sdio_5fmask_5ftxfifofie_383',['SDIO_MASK_TXFIFOFIE',['../group___peripheral___registers___bits___definition.html#ga03a602b975ce16ef03083947aded0172',1,'stm32f407xx_matlab.h']]], - ['sdio_5fmask_5ftxfifofie_5fmsk_384',['SDIO_MASK_TXFIFOFIE_Msk',['../group___peripheral___registers___bits___definition.html#gae60848e2a91f045224142d4a9ba87baf',1,'stm32f407xx_matlab.h']]], - ['sdio_5fmask_5ftxfifofie_5fpos_385',['SDIO_MASK_TXFIFOFIE_Pos',['../group___peripheral___registers___bits___definition.html#gaadb33e583b2dd534458a807d4efa4d97',1,'stm32f407xx_matlab.h']]], - ['sdio_5fmask_5ftxfifoheie_386',['SDIO_MASK_TXFIFOHEIE',['../group___peripheral___registers___bits___definition.html#gad9cf28de8489fee023ea353df0e13fa7',1,'stm32f407xx_matlab.h']]], - ['sdio_5fmask_5ftxfifoheie_5fmsk_387',['SDIO_MASK_TXFIFOHEIE_Msk',['../group___peripheral___registers___bits___definition.html#ga31a0538971e372ab926c3a9f935b2502',1,'stm32f407xx_matlab.h']]], - ['sdio_5fmask_5ftxfifoheie_5fpos_388',['SDIO_MASK_TXFIFOHEIE_Pos',['../group___peripheral___registers___bits___definition.html#gad10c89cc7329707f9c9aa1c3ad259980',1,'stm32f407xx_matlab.h']]], - ['sdio_5fmask_5ftxunderrie_389',['SDIO_MASK_TXUNDERRIE',['../group___peripheral___registers___bits___definition.html#ga1e02e525dc6ca1bb294b174e7391753d',1,'stm32f407xx_matlab.h']]], - ['sdio_5fmask_5ftxunderrie_5fmsk_390',['SDIO_MASK_TXUNDERRIE_Msk',['../group___peripheral___registers___bits___definition.html#ga245c0ebe407cfe97f42c98563070a7ef',1,'stm32f407xx_matlab.h']]], - ['sdio_5fmask_5ftxunderrie_5fpos_391',['SDIO_MASK_TXUNDERRIE_Pos',['../group___peripheral___registers___bits___definition.html#ga0289babaca7a9d6ae404e78709152f20',1,'stm32f407xx_matlab.h']]], - ['sdio_5fpower_5fpwrctrl_392',['SDIO_POWER_PWRCTRL',['../group___peripheral___registers___bits___definition.html#gaf125c56eeb40163b617c9fb6329da67f',1,'stm32f407xx_matlab.h']]], - ['sdio_5fpower_5fpwrctrl_5f0_393',['SDIO_POWER_PWRCTRL_0',['../group___peripheral___registers___bits___definition.html#gaa82b7689b02f54318d3f629d70b85098',1,'stm32f407xx_matlab.h']]], - ['sdio_5fpower_5fpwrctrl_5f1_394',['SDIO_POWER_PWRCTRL_1',['../group___peripheral___registers___bits___definition.html#gadd149efb1d6062f37165ac01268a875e',1,'stm32f407xx_matlab.h']]], - ['sdio_5fpower_5fpwrctrl_5fmsk_395',['SDIO_POWER_PWRCTRL_Msk',['../group___peripheral___registers___bits___definition.html#ga85685239a200e250d95c38f310fb9609',1,'stm32f407xx_matlab.h']]], - ['sdio_5fpower_5fpwrctrl_5fpos_396',['SDIO_POWER_PWRCTRL_Pos',['../group___peripheral___registers___bits___definition.html#ga980203971a9f5f4c5e02733c6106249f',1,'stm32f407xx_matlab.h']]], - ['sdio_5fresp0_5fcardstatus0_397',['SDIO_RESP0_CARDSTATUS0',['../group___peripheral___registers___bits___definition.html#ga56a55231f7a91cfd2cefaca0f6135cbc',1,'stm32f407xx_matlab.h']]], - ['sdio_5fresp0_5fcardstatus0_5fmsk_398',['SDIO_RESP0_CARDSTATUS0_Msk',['../group___peripheral___registers___bits___definition.html#ga3f6aa725abdb56f38c3c8783b9f15e47',1,'stm32f407xx_matlab.h']]], - ['sdio_5fresp0_5fcardstatus0_5fpos_399',['SDIO_RESP0_CARDSTATUS0_Pos',['../group___peripheral___registers___bits___definition.html#ga0050e8b5acaf5716002877e15744cea1',1,'stm32f407xx_matlab.h']]], - ['sdio_5fresp1_5fcardstatus1_400',['SDIO_RESP1_CARDSTATUS1',['../group___peripheral___registers___bits___definition.html#ga1d20abddfc99835a2954eda5899f6db1',1,'stm32f407xx_matlab.h']]], - ['sdio_5fresp1_5fcardstatus1_5fmsk_401',['SDIO_RESP1_CARDSTATUS1_Msk',['../group___peripheral___registers___bits___definition.html#gaccbe896832554a212ce0eb8d7650b850',1,'stm32f407xx_matlab.h']]], - ['sdio_5fresp1_5fcardstatus1_5fpos_402',['SDIO_RESP1_CARDSTATUS1_Pos',['../group___peripheral___registers___bits___definition.html#gacdf3d65acd80e89c5b3a85759cbf11ae',1,'stm32f407xx_matlab.h']]], - ['sdio_5fresp2_5fcardstatus2_403',['SDIO_RESP2_CARDSTATUS2',['../group___peripheral___registers___bits___definition.html#ga31a482ff36bde1df56ab603c864c4066',1,'stm32f407xx_matlab.h']]], - ['sdio_5fresp2_5fcardstatus2_5fmsk_404',['SDIO_RESP2_CARDSTATUS2_Msk',['../group___peripheral___registers___bits___definition.html#gafb0ef49057b923f3518c6f055a79b605',1,'stm32f407xx_matlab.h']]], - ['sdio_5fresp2_5fcardstatus2_5fpos_405',['SDIO_RESP2_CARDSTATUS2_Pos',['../group___peripheral___registers___bits___definition.html#gac4fe5348e4b89d1b8307a399d2696684',1,'stm32f407xx_matlab.h']]], - ['sdio_5fresp3_5fcardstatus3_406',['SDIO_RESP3_CARDSTATUS3',['../group___peripheral___registers___bits___definition.html#ga1075c96b5818b0500d5cce231ace89cf',1,'stm32f407xx_matlab.h']]], - ['sdio_5fresp3_5fcardstatus3_5fmsk_407',['SDIO_RESP3_CARDSTATUS3_Msk',['../group___peripheral___registers___bits___definition.html#gab48a641918cdc42f1f8da11703329a04',1,'stm32f407xx_matlab.h']]], - ['sdio_5fresp3_5fcardstatus3_5fpos_408',['SDIO_RESP3_CARDSTATUS3_Pos',['../group___peripheral___registers___bits___definition.html#ga6cc1aa3203ce39c556e1631c05d911ea',1,'stm32f407xx_matlab.h']]], - ['sdio_5fresp4_5fcardstatus4_409',['SDIO_RESP4_CARDSTATUS4',['../group___peripheral___registers___bits___definition.html#ga407ab1e46a80426602ab36e86457da26',1,'stm32f407xx_matlab.h']]], - ['sdio_5fresp4_5fcardstatus4_5fmsk_410',['SDIO_RESP4_CARDSTATUS4_Msk',['../group___peripheral___registers___bits___definition.html#ga38cdffc0bf0950e987e8380d8f89f4c0',1,'stm32f407xx_matlab.h']]], - ['sdio_5fresp4_5fcardstatus4_5fpos_411',['SDIO_RESP4_CARDSTATUS4_Pos',['../group___peripheral___registers___bits___definition.html#gae5fc053049c54b41a638649c8990c5b1',1,'stm32f407xx_matlab.h']]], - ['sdio_5frespcmd_5frespcmd_412',['SDIO_RESPCMD_RESPCMD',['../group___peripheral___registers___bits___definition.html#ga27f9a6cbfd364bbb050b526ebc01d2d7',1,'stm32f407xx_matlab.h']]], - ['sdio_5frespcmd_5frespcmd_5fmsk_413',['SDIO_RESPCMD_RESPCMD_Msk',['../group___peripheral___registers___bits___definition.html#ga0f937e878d203e9f9dda3e12cec73153',1,'stm32f407xx_matlab.h']]], - ['sdio_5frespcmd_5frespcmd_5fpos_414',['SDIO_RESPCMD_RESPCMD_Pos',['../group___peripheral___registers___bits___definition.html#ga53f5c709c72c524a03ed26cc6a246f1a',1,'stm32f407xx_matlab.h']]], - ['sdio_5fsta_5fccrcfail_415',['SDIO_STA_CCRCFAIL',['../group___peripheral___registers___bits___definition.html#gad6dbe59c4bdd8b9a12b092cf84a9daef',1,'stm32f407xx_matlab.h']]], - ['sdio_5fsta_5fccrcfail_5fmsk_416',['SDIO_STA_CCRCFAIL_Msk',['../group___peripheral___registers___bits___definition.html#gae72a4ab40725d2063cb2900512f79e57',1,'stm32f407xx_matlab.h']]], - ['sdio_5fsta_5fccrcfail_5fpos_417',['SDIO_STA_CCRCFAIL_Pos',['../group___peripheral___registers___bits___definition.html#gaeb2c0bead439847c163d2b4166d3b7c8',1,'stm32f407xx_matlab.h']]], - ['sdio_5fsta_5fceataend_418',['SDIO_STA_CEATAEND',['../group___peripheral___registers___bits___definition.html#ga5d8ef3b4157374fd2b5fc8ed12b77a0c',1,'stm32f407xx_matlab.h']]], - ['sdio_5fsta_5fceataend_5fmsk_419',['SDIO_STA_CEATAEND_Msk',['../group___peripheral___registers___bits___definition.html#gaa51fdc310e3b16750da76a9d850278a3',1,'stm32f407xx_matlab.h']]], - ['sdio_5fsta_5fceataend_5fpos_420',['SDIO_STA_CEATAEND_Pos',['../group___peripheral___registers___bits___definition.html#ga66310759b05b535f231c7750a2cba57e',1,'stm32f407xx_matlab.h']]], - ['sdio_5fsta_5fcmdact_421',['SDIO_STA_CMDACT',['../group___peripheral___registers___bits___definition.html#ga99ccdac7a223635ee5b38a4bae8f30cc',1,'stm32f407xx_matlab.h']]], - ['sdio_5fsta_5fcmdact_5fmsk_422',['SDIO_STA_CMDACT_Msk',['../group___peripheral___registers___bits___definition.html#gaa9c9c8a3be5f8615d36927da8c7152c2',1,'stm32f407xx_matlab.h']]], - ['sdio_5fsta_5fcmdact_5fpos_423',['SDIO_STA_CMDACT_Pos',['../group___peripheral___registers___bits___definition.html#ga2390484299f14b720b5f5e3fa5811538',1,'stm32f407xx_matlab.h']]], - ['sdio_5fsta_5fcmdrend_424',['SDIO_STA_CMDREND',['../group___peripheral___registers___bits___definition.html#ga096f11117736a2252f1cd5c4cccdc6e6',1,'stm32f407xx_matlab.h']]], - ['sdio_5fsta_5fcmdrend_5fmsk_425',['SDIO_STA_CMDREND_Msk',['../group___peripheral___registers___bits___definition.html#ga3ab895524d8a5cbf1b1104abcdf013fe',1,'stm32f407xx_matlab.h']]], - ['sdio_5fsta_5fcmdrend_5fpos_426',['SDIO_STA_CMDREND_Pos',['../group___peripheral___registers___bits___definition.html#gafa10e00ee0c79b38dd2aa074d4d7d604',1,'stm32f407xx_matlab.h']]], - ['sdio_5fsta_5fcmdsent_427',['SDIO_STA_CMDSENT',['../group___peripheral___registers___bits___definition.html#gaa550641dc6aa942e1b524ad0e557a284',1,'stm32f407xx_matlab.h']]], - ['sdio_5fsta_5fcmdsent_5fmsk_428',['SDIO_STA_CMDSENT_Msk',['../group___peripheral___registers___bits___definition.html#ga7ff987cbe6f2afc731016591f7dca4f7',1,'stm32f407xx_matlab.h']]], - ['sdio_5fsta_5fcmdsent_5fpos_429',['SDIO_STA_CMDSENT_Pos',['../group___peripheral___registers___bits___definition.html#gaeec49be725a39b21c24769feb4f43b89',1,'stm32f407xx_matlab.h']]], - ['sdio_5fsta_5fctimeout_430',['SDIO_STA_CTIMEOUT',['../group___peripheral___registers___bits___definition.html#gae72c4f34bb3ccffeef1d7cdcb7415bdc',1,'stm32f407xx_matlab.h']]], - ['sdio_5fsta_5fctimeout_5fmsk_431',['SDIO_STA_CTIMEOUT_Msk',['../group___peripheral___registers___bits___definition.html#ga27433ab3bb7c09bfd6c7e65daee2c1c2',1,'stm32f407xx_matlab.h']]], - ['sdio_5fsta_5fctimeout_5fpos_432',['SDIO_STA_CTIMEOUT_Pos',['../group___peripheral___registers___bits___definition.html#ga1c834436a9afa85d118ef4a83f7cb283',1,'stm32f407xx_matlab.h']]], - ['sdio_5fsta_5fdataend_433',['SDIO_STA_DATAEND',['../group___peripheral___registers___bits___definition.html#gafe7e354a903b957943cf5b6bed4cdf6b',1,'stm32f407xx_matlab.h']]], - ['sdio_5fsta_5fdataend_5fmsk_434',['SDIO_STA_DATAEND_Msk',['../group___peripheral___registers___bits___definition.html#ga39ffad41e1ac6eb225eb1f06f320a9c2',1,'stm32f407xx_matlab.h']]], - ['sdio_5fsta_5fdataend_5fpos_435',['SDIO_STA_DATAEND_Pos',['../group___peripheral___registers___bits___definition.html#gaaaa45c46418b926d742e8c557eca124d',1,'stm32f407xx_matlab.h']]], - ['sdio_5fsta_5fdbckend_436',['SDIO_STA_DBCKEND',['../group___peripheral___registers___bits___definition.html#ga2fabf2c02cba6d4de1e90d8d1dc9793c',1,'stm32f407xx_matlab.h']]], - ['sdio_5fsta_5fdbckend_5fmsk_437',['SDIO_STA_DBCKEND_Msk',['../group___peripheral___registers___bits___definition.html#gac9c1646ceeca1e8e93ca1f4bbb2fd12f',1,'stm32f407xx_matlab.h']]], - ['sdio_5fsta_5fdbckend_5fpos_438',['SDIO_STA_DBCKEND_Pos',['../group___peripheral___registers___bits___definition.html#ga56b7b1a0c443227a070222af9cd212f5',1,'stm32f407xx_matlab.h']]], - ['sdio_5fsta_5fdcrcfail_439',['SDIO_STA_DCRCFAIL',['../group___peripheral___registers___bits___definition.html#ga554d1f9986bf5c715dd6f27a6493ce31',1,'stm32f407xx_matlab.h']]], - ['sdio_5fsta_5fdcrcfail_5fmsk_440',['SDIO_STA_DCRCFAIL_Msk',['../group___peripheral___registers___bits___definition.html#gad51a35e09d9332c7402e7db2dd3b63d2',1,'stm32f407xx_matlab.h']]], - ['sdio_5fsta_5fdcrcfail_5fpos_441',['SDIO_STA_DCRCFAIL_Pos',['../group___peripheral___registers___bits___definition.html#gad788ced0bde93f188aed790a18cdde65',1,'stm32f407xx_matlab.h']]], - ['sdio_5fsta_5fdtimeout_442',['SDIO_STA_DTIMEOUT',['../group___peripheral___registers___bits___definition.html#ga8a2cad7ef3406a46ddba51f7ab5df94b',1,'stm32f407xx_matlab.h']]], - ['sdio_5fsta_5fdtimeout_5fmsk_443',['SDIO_STA_DTIMEOUT_Msk',['../group___peripheral___registers___bits___definition.html#gab9c4e52bb9c5041bd2be2eb216dd9e7c',1,'stm32f407xx_matlab.h']]], - ['sdio_5fsta_5fdtimeout_5fpos_444',['SDIO_STA_DTIMEOUT_Pos',['../group___peripheral___registers___bits___definition.html#ga889faf1ecb5ebaf770074f4228e0f372',1,'stm32f407xx_matlab.h']]], - ['sdio_5fsta_5frxact_445',['SDIO_STA_RXACT',['../group___peripheral___registers___bits___definition.html#gaad2f52b50765fa449dcfabc39b099796',1,'stm32f407xx_matlab.h']]], - ['sdio_5fsta_5frxact_5fmsk_446',['SDIO_STA_RXACT_Msk',['../group___peripheral___registers___bits___definition.html#ga6804febb98fae68a60c58b4c1e0935e3',1,'stm32f407xx_matlab.h']]], - ['sdio_5fsta_5frxact_5fpos_447',['SDIO_STA_RXACT_Pos',['../group___peripheral___registers___bits___definition.html#ga3a48d2dd6535975e9d584964067f41a6',1,'stm32f407xx_matlab.h']]], - ['sdio_5fsta_5frxdavl_448',['SDIO_STA_RXDAVL',['../group___peripheral___registers___bits___definition.html#gadcad9b8c0e3ccba1aa389d7713db6803',1,'stm32f407xx_matlab.h']]], - ['sdio_5fsta_5frxdavl_5fmsk_449',['SDIO_STA_RXDAVL_Msk',['../group___peripheral___registers___bits___definition.html#gaf3c400c578bed5233c91c6e9570a651d',1,'stm32f407xx_matlab.h']]], - ['sdio_5fsta_5frxdavl_5fpos_450',['SDIO_STA_RXDAVL_Pos',['../group___peripheral___registers___bits___definition.html#ga5eff3fcfe1a6b51137bb2faa735ede8d',1,'stm32f407xx_matlab.h']]], - ['sdio_5fsta_5frxfifoe_451',['SDIO_STA_RXFIFOE',['../group___peripheral___registers___bits___definition.html#ga44bf9f7321d65a3effd2df469a58a464',1,'stm32f407xx_matlab.h']]], - ['sdio_5fsta_5frxfifoe_5fmsk_452',['SDIO_STA_RXFIFOE_Msk',['../group___peripheral___registers___bits___definition.html#gad68af59ab8a514fc2ec9735db58bc4bf',1,'stm32f407xx_matlab.h']]], - ['sdio_5fsta_5frxfifoe_5fpos_453',['SDIO_STA_RXFIFOE_Pos',['../group___peripheral___registers___bits___definition.html#gaa66efed771cee7e43274a73357e77036',1,'stm32f407xx_matlab.h']]], - ['sdio_5fsta_5frxfifof_454',['SDIO_STA_RXFIFOF',['../group___peripheral___registers___bits___definition.html#ga85f46f873ca5fe91a1e8206d157b9446',1,'stm32f407xx_matlab.h']]], - ['sdio_5fsta_5frxfifof_5fmsk_455',['SDIO_STA_RXFIFOF_Msk',['../group___peripheral___registers___bits___definition.html#ga7af9ed233f8115b8d3123bb274d197ec',1,'stm32f407xx_matlab.h']]], - ['sdio_5fsta_5frxfifof_5fpos_456',['SDIO_STA_RXFIFOF_Pos',['../group___peripheral___registers___bits___definition.html#ga86b297852e15be2ce6b2c08b7432f868',1,'stm32f407xx_matlab.h']]], - ['sdio_5fsta_5frxfifohf_457',['SDIO_STA_RXFIFOHF',['../group___peripheral___registers___bits___definition.html#ga7916c47ee972376a0eaee584133ca36d',1,'stm32f407xx_matlab.h']]], - ['sdio_5fsta_5frxfifohf_5fmsk_458',['SDIO_STA_RXFIFOHF_Msk',['../group___peripheral___registers___bits___definition.html#ga0a590a016f50e757d6eb58248f9af026',1,'stm32f407xx_matlab.h']]], - ['sdio_5fsta_5frxfifohf_5fpos_459',['SDIO_STA_RXFIFOHF_Pos',['../group___peripheral___registers___bits___definition.html#ga7f8b161fe0ebbd71a38e85c8caa3a466',1,'stm32f407xx_matlab.h']]], - ['sdio_5fsta_5frxoverr_460',['SDIO_STA_RXOVERR',['../group___peripheral___registers___bits___definition.html#gad4b91289c9f6b773f928706ae8a5ddfc',1,'stm32f407xx_matlab.h']]], - ['sdio_5fsta_5frxoverr_5fmsk_461',['SDIO_STA_RXOVERR_Msk',['../group___peripheral___registers___bits___definition.html#ga8cd1da9061309343205c1421250ec2ac',1,'stm32f407xx_matlab.h']]], - ['sdio_5fsta_5frxoverr_5fpos_462',['SDIO_STA_RXOVERR_Pos',['../group___peripheral___registers___bits___definition.html#gae72faf7690680a4a9fbeb3da74699d0d',1,'stm32f407xx_matlab.h']]], - ['sdio_5fsta_5fsdioit_463',['SDIO_STA_SDIOIT',['../group___peripheral___registers___bits___definition.html#ga5df3c10c37285faedb2d853aea4e63dc',1,'stm32f407xx_matlab.h']]], - ['sdio_5fsta_5fsdioit_5fmsk_464',['SDIO_STA_SDIOIT_Msk',['../group___peripheral___registers___bits___definition.html#gae20bfd0933cc814ac479a82f720ab423',1,'stm32f407xx_matlab.h']]], - ['sdio_5fsta_5fsdioit_5fpos_465',['SDIO_STA_SDIOIT_Pos',['../group___peripheral___registers___bits___definition.html#gac1d1c55503940b44780c405d6e6f7581',1,'stm32f407xx_matlab.h']]], - ['sdio_5fsta_5fstbiterr_466',['SDIO_STA_STBITERR',['../group___peripheral___registers___bits___definition.html#ga7a9ef8e72604e9997da23601a2dd84a4',1,'stm32f407xx_matlab.h']]], - ['sdio_5fsta_5fstbiterr_5fmsk_467',['SDIO_STA_STBITERR_Msk',['../group___peripheral___registers___bits___definition.html#ga0c826404242f6e6ff56c3b6b3e42863a',1,'stm32f407xx_matlab.h']]], - ['sdio_5fsta_5fstbiterr_5fpos_468',['SDIO_STA_STBITERR_Pos',['../group___peripheral___registers___bits___definition.html#gac2d7138c3bcb7ccf0d90c93daac3a43a',1,'stm32f407xx_matlab.h']]], - ['sdio_5fsta_5ftxact_469',['SDIO_STA_TXACT',['../group___peripheral___registers___bits___definition.html#ga908feb4957f48390bc2fc0bde47ac784',1,'stm32f407xx_matlab.h']]], - ['sdio_5fsta_5ftxact_5fmsk_470',['SDIO_STA_TXACT_Msk',['../group___peripheral___registers___bits___definition.html#ga8013f5e0b7c82bd29351e0428af7240f',1,'stm32f407xx_matlab.h']]], - ['sdio_5fsta_5ftxact_5fpos_471',['SDIO_STA_TXACT_Pos',['../group___peripheral___registers___bits___definition.html#ga47ef38c70701b9ca0d77927071bfdd10',1,'stm32f407xx_matlab.h']]], - ['sdio_5fsta_5ftxdavl_472',['SDIO_STA_TXDAVL',['../group___peripheral___registers___bits___definition.html#ga19b374518e813f7a1ac4aec3b24b7517',1,'stm32f407xx_matlab.h']]], - ['sdio_5fsta_5ftxdavl_5fmsk_473',['SDIO_STA_TXDAVL_Msk',['../group___peripheral___registers___bits___definition.html#ga5ce2c8660375bdf8f10e49af1966f64f',1,'stm32f407xx_matlab.h']]], - ['sdio_5fsta_5ftxdavl_5fpos_474',['SDIO_STA_TXDAVL_Pos',['../group___peripheral___registers___bits___definition.html#gae685d8223202af5aaf85779c9b9c33ce',1,'stm32f407xx_matlab.h']]], - ['sdio_5fsta_5ftxfifoe_475',['SDIO_STA_TXFIFOE',['../group___peripheral___registers___bits___definition.html#ga4624f95c5224c631f99571b5454acd86',1,'stm32f407xx_matlab.h']]], - ['sdio_5fsta_5ftxfifoe_5fmsk_476',['SDIO_STA_TXFIFOE_Msk',['../group___peripheral___registers___bits___definition.html#gadae851570f79529e3027cd6ae80b9a19',1,'stm32f407xx_matlab.h']]], - ['sdio_5fsta_5ftxfifoe_5fpos_477',['SDIO_STA_TXFIFOE_Pos',['../group___peripheral___registers___bits___definition.html#ga08db94989b17f7ad2e47a029afc89ae2',1,'stm32f407xx_matlab.h']]], - ['sdio_5fsta_5ftxfifof_478',['SDIO_STA_TXFIFOF',['../group___peripheral___registers___bits___definition.html#gae1497b46f9a906001dabb7d7604f6c05',1,'stm32f407xx_matlab.h']]], - ['sdio_5fsta_5ftxfifof_5fmsk_479',['SDIO_STA_TXFIFOF_Msk',['../group___peripheral___registers___bits___definition.html#gab9d17bbac6dd7388ed367c5ccfa5be1c',1,'stm32f407xx_matlab.h']]], - ['sdio_5fsta_5ftxfifof_5fpos_480',['SDIO_STA_TXFIFOF_Pos',['../group___peripheral___registers___bits___definition.html#ga634b30add702067001f17455bc691740',1,'stm32f407xx_matlab.h']]], - ['sdio_5fsta_5ftxfifohe_481',['SDIO_STA_TXFIFOHE',['../group___peripheral___registers___bits___definition.html#ga62b9e38be5956dde69049154facc62fd',1,'stm32f407xx_matlab.h']]], - ['sdio_5fsta_5ftxfifohe_5fmsk_482',['SDIO_STA_TXFIFOHE_Msk',['../group___peripheral___registers___bits___definition.html#ga41135726ff869b6aa9a2f0ed1383ea53',1,'stm32f407xx_matlab.h']]], - ['sdio_5fsta_5ftxfifohe_5fpos_483',['SDIO_STA_TXFIFOHE_Pos',['../group___peripheral___registers___bits___definition.html#gaf3a623bdff29b95c5a45c523a90fe12e',1,'stm32f407xx_matlab.h']]], - ['sdio_5fsta_5ftxunderr_484',['SDIO_STA_TXUNDERR',['../group___peripheral___registers___bits___definition.html#ga4b9dcdb8b90d8266eb0c5a2be81238aa',1,'stm32f407xx_matlab.h']]], - ['sdio_5fsta_5ftxunderr_5fmsk_485',['SDIO_STA_TXUNDERR_Msk',['../group___peripheral___registers___bits___definition.html#gac651b75734596780cc225b1c1688741d',1,'stm32f407xx_matlab.h']]], - ['sdio_5fsta_5ftxunderr_5fpos_486',['SDIO_STA_TXUNDERR_Pos',['../group___peripheral___registers___bits___definition.html#ga3c4f937a15d62a7e9a6d761104aab35e',1,'stm32f407xx_matlab.h']]], - ['sdio_5ftypedef_487',['SDIO_TypeDef',['../struct_s_d_i_o___type_def.html',1,'']]], - ['set_488',['SET',['../group___exported__types.html#gga89136caac2e14c55151f527ac02daaffab44c8101cc294c074709ec1b14211792',1,'stm32f4xx.h']]], - ['set_5fbit_489',['SET_BIT',['../group___exported__macro.html#ga26474f43799fbade9cf300e21dd3a91a',1,'stm32f4xx.h']]], - ['set_5fflag_5fif_5fits_5fexpected_490',['Set_Flag_If_Its_Expected',['../group___r_c_c___s_i_m_u_l_a_t_o_r.html#gadf8f9d228ec9091df7d092a298f11b17',1,'stm32f4xx_matlab_rcc.h']]], - ['sfifomailbox_491',['sFIFOMailBox',['../group___c_m_s_i_s___device.html#ga21b030b34e131f7ef6ea273416449fe4',1,'CAN_TypeDef']]], - ['sfilterregister_492',['sFilterRegister',['../group___c_m_s_i_s___device.html#ga31bd74513e6e599319702ad34113bf59',1,'CAN_TypeDef']]], - ['sfunc_5fto_5fgpio_493',['SFUNC_to_GPIO',['../group___g_p_i_o___s_i_m_u_l_a_t_o_r.html#ga9bce93a37f6835a1824bec5f235c9ef5',1,'SFUNC_to_GPIO(real_T *in): stm32f4xx_matlab_gpio.c'],['../group___g_p_i_o___s_i_m_u_l_a_t_o_r.html#ga9bce93a37f6835a1824bec5f235c9ef5',1,'SFUNC_to_GPIO(real_T *disc): stm32f4xx_matlab_gpio.c']]], - ['shcsr_494',['SHCSR',['../group___c_m_s_i_s__core___debug_functions.html#ga44ad5c292dbd77e72f310902375a8a06',1,'SCB_Type']]], - ['shiftr_495',['SHIFTR',['../group___c_m_s_i_s___device.html#ga2372c05a6c5508e0a9adada793f68b4f',1,'RTC_TypeDef']]], - ['shp_496',['SHP',['../group___c_m_s_i_s__core___debug_functions.html#ga293826a2c44f754e80af03d62f62f9e6',1,'SCB_Type']]], - ['sig_5fatomic_5fmax_497',['SIG_ATOMIC_MAX',['../stdint_8h.html#a1f5fe9445d0ad0bee21bab1de4cc3e58',1,'stdint.h']]], - ['sig_5fatomic_5fmin_498',['SIG_ATOMIC_MIN',['../stdint_8h.html#a21e605b9ac3a03b6de93cdf5a69e129f',1,'stdint.h']]], - ['sim_5f_5fmcuhandletypedef_499',['SIM__MCUHandleTypeDef',['../struct_s_i_m_____m_c_u_handle_type_def.html',1,'']]], - ['sim_5fdeinitialize_5fsimulation_500',['SIM_deInitialize_Simulation',['../mcu__wrapper_8c.html#a6f04b162923bada308d9668743425b92',1,'SIM_deInitialize_Simulation(void): mcu_wrapper.c'],['../mcu__wrapper__conf_8h.html#a6f04b162923bada308d9668743425b92',1,'SIM_deInitialize_Simulation(void): mcu_wrapper.c']]], - ['sim_5finitialize_5fsimulation_501',['SIM_Initialize_Simulation',['../mcu__wrapper_8c.html#a54429d6d68b1d72ce16bab374e3ffa08',1,'SIM_Initialize_Simulation(void): mcu_wrapper.c'],['../mcu__wrapper__conf_8h.html#a54429d6d68b1d72ce16bab374e3ffa08',1,'SIM_Initialize_Simulation(void): mcu_wrapper.c']]], - ['sim_5fsample_5ftime_502',['SIM_Sample_Time',['../struct_s_i_m_____m_c_u_handle_type_def.html#ab19a05224f30fab089c5d5e18fdcca36',1,'SIM__MCUHandleTypeDef']]], - ['sim_5fwhile_503',['sim_while',['../mcu__wrapper__conf_8h.html#a1fef2893362ee1f5032b523ff8c7fd9d',1,'mcu_wrapper_conf.h']]], - ['sim_5fwriteoutput_504',['SIM_writeOutput',['../mcu__wrapper__conf_8h.html#ad38bfad0ee1e186c0663565abb6bc71a',1,'mcu_wrapper_conf.h']]], - ['sim_5fwriteoutputs_505',['SIM_writeOutputs',['../mcu__wrapper_8c.html#a47b40a9825bcaeb3a1dfba8b27a0be3f',1,'mcu_wrapper.c']]], - ['simulate_5ftims_506',['Simulate_TIMs',['../group___t_i_m___s_i_m_u_l_a_t_o_r.html#ga3128cf64eeea541a8e25a72ce10da335',1,'Simulate_TIMs(void): stm32f4xx_matlab_tim.c'],['../group___t_i_m___s_i_m_u_l_a_t_o_r.html#ga3128cf64eeea541a8e25a72ce10da335',1,'Simulate_TIMs(void): stm32f4xx_matlab_tim.c']]], - ['simulator_5fconf_507',['SIMULATOR_CONF',['../group___s_i_m_u_l_a_t_o_r___c_o_n_f.html',1,'']]], - ['size_5fmax_508',['SIZE_MAX',['../stdint_8h.html#a3c75bb398badb69c7577b21486f9963f',1,'stdint.h']]], - ['slave_5fchannels_509',['Slave_Channels',['../stm32f4xx__matlab__tim_8c.html#a66e48ba3c30d98536e05b7f5435e9828',1,'stm32f4xx_matlab_tim.c']]], - ['slave_5fmode_5fcheck_5fsource_510',['Slave_Mode_Check_Source',['../group___t_i_m___s_i_m_u_l_a_t_o_r.html#ga9689b1f2e04622487f039dfb74d8e0db',1,'Slave_Mode_Check_Source(TIM_TypeDef *TIMx, struct TIM_Sim *TIMS): stm32f4xx_matlab_tim.c'],['../group___t_i_m___s_i_m_u_l_a_t_o_r.html#ga9689b1f2e04622487f039dfb74d8e0db',1,'Slave_Mode_Check_Source(TIM_TypeDef *TIMx, struct TIM_Sim *TIMS): stm32f4xx_matlab_tim.c']]], - ['slavechannels_511',['SlaveChannels',['../struct_slave_channels.html',1,'']]], - ['sleepcnt_512',['SLEEPCNT',['../group___c_m_s_i_s__core___debug_functions.html#gaafa1400cd3168b21652b86599ad3ed83',1,'DWT_Type']]], - ['smcr_513',['SMCR',['../group___c_m_s_i_s___device.html#ga2870732a4fc2ecd7bbecfbcbbf5528b7',1,'TIM_TypeDef']]], - ['smpr1_514',['SMPR1',['../group___c_m_s_i_s___device.html#gaf9d6c604e365c7d9d7601bf4ef373498',1,'ADC_TypeDef']]], - ['smpr2_515',['SMPR2',['../group___c_m_s_i_s___device.html#ga6ac83fae8377c7b7fcae50fa4211b0e8',1,'ADC_TypeDef']]], - ['spi1_516',['spi1',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga8cc3430b6591549759eb42cc2004a889',1,'stm32f4xx_periph_registers.c']]], - ['spi1_517',['SPI1',['../group___peripheral__declaration.html#gad483be344a28ac800be8f03654a9612f',1,'stm32f407xx_matlab.h']]], - ['spi1_5fbase_518',['SPI1_BASE',['../group___peripheral__memory__map.html#ga50cd8b47929f18b05efbd0f41253bf8d',1,'stm32f407xx_matlab.h']]], - ['spi1_5firqn_519',['SPI1_IRQn',['../group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8aacdff1a9c42582ed663214cbe62c1174',1,'stm32f407xx_matlab.h']]], - ['spi2_520',['spi2',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#gaafd9bde301b8cacea574ec4eea0e474f',1,'stm32f4xx_periph_registers.c']]], - ['spi2_521',['SPI2',['../group___peripheral__declaration.html#gaf2c3d8ce359dcfbb2261e07ed42af72b',1,'stm32f407xx_matlab.h']]], - ['spi2_5fbase_522',['SPI2_BASE',['../group___peripheral__memory__map.html#gac3e357b4c25106ed375fb1affab6bb86',1,'stm32f407xx_matlab.h']]], - ['spi2_5firqn_523',['SPI2_IRQn',['../group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a505fbd4ccf7c2a14c8b76dc9e58f7ede',1,'stm32f407xx_matlab.h']]], - ['spi3_524',['spi3',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga050e08b3b630957cd79c0e69968308bd',1,'stm32f4xx_periph_registers.c']]], - ['spi3_525',['SPI3',['../group___peripheral__declaration.html#gab2339cbf25502bf562b19208b1b257fc',1,'stm32f407xx_matlab.h']]], - ['spi3_5fbase_526',['SPI3_BASE',['../group___peripheral__memory__map.html#gae634fe8faa6922690e90fbec2fc86162',1,'stm32f407xx_matlab.h']]], - ['spi3_5firqn_527',['SPI3_IRQn',['../group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a4e9331739fb76a2ca7781fede070ae44',1,'stm32f407xx_matlab.h']]], - ['spi_5fcr1_5fbidimode_528',['SPI_CR1_BIDIMODE',['../group___peripheral___registers___bits___definition.html#ga43608d3c2959fc9ca64398d61cbf484e',1,'stm32f407xx_matlab.h']]], - ['spi_5fcr1_5fbidimode_5fmsk_529',['SPI_CR1_BIDIMODE_Msk',['../group___peripheral___registers___bits___definition.html#gae2c9301aa73d6795e9739f8d12d42c15',1,'stm32f407xx_matlab.h']]], - ['spi_5fcr1_5fbidimode_5fpos_530',['SPI_CR1_BIDIMODE_Pos',['../group___peripheral___registers___bits___definition.html#gab07c9facbfdb0a7d5d89b1fd6a3ef711',1,'stm32f407xx_matlab.h']]], - ['spi_5fcr1_5fbidioe_531',['SPI_CR1_BIDIOE',['../group___peripheral___registers___bits___definition.html#ga378953916b7701bd49f063c0366b703f',1,'stm32f407xx_matlab.h']]], - ['spi_5fcr1_5fbidioe_5fmsk_532',['SPI_CR1_BIDIOE_Msk',['../group___peripheral___registers___bits___definition.html#ga5bcee503ed5669187bb980faf90d57ca',1,'stm32f407xx_matlab.h']]], - ['spi_5fcr1_5fbidioe_5fpos_533',['SPI_CR1_BIDIOE_Pos',['../group___peripheral___registers___bits___definition.html#ga2975c27caad9e31aad719d78d591ac1d',1,'stm32f407xx_matlab.h']]], - ['spi_5fcr1_5fbr_534',['SPI_CR1_BR',['../group___peripheral___registers___bits___definition.html#ga261af22667719a32b3ce566c1e261936',1,'stm32f407xx_matlab.h']]], - ['spi_5fcr1_5fbr_5f0_535',['SPI_CR1_BR_0',['../group___peripheral___registers___bits___definition.html#gaa364b123cf797044094cc229330ce321',1,'stm32f407xx_matlab.h']]], - ['spi_5fcr1_5fbr_5f1_536',['SPI_CR1_BR_1',['../group___peripheral___registers___bits___definition.html#ga45e93d18c8966964ed1926d5ca87ef46',1,'stm32f407xx_matlab.h']]], - ['spi_5fcr1_5fbr_5f2_537',['SPI_CR1_BR_2',['../group___peripheral___registers___bits___definition.html#ga28b823d564e9d90150bcc6744b4ed622',1,'stm32f407xx_matlab.h']]], - ['spi_5fcr1_5fbr_5fmsk_538',['SPI_CR1_BR_Msk',['../group___peripheral___registers___bits___definition.html#gaec378749f03998b5d2769c3d83deef23',1,'stm32f407xx_matlab.h']]], - ['spi_5fcr1_5fbr_5fpos_539',['SPI_CR1_BR_Pos',['../group___peripheral___registers___bits___definition.html#gac6a71c219a81b476e66c3579d72120b9',1,'stm32f407xx_matlab.h']]], - ['spi_5fcr1_5fcpha_540',['SPI_CR1_CPHA',['../group___peripheral___registers___bits___definition.html#ga97602d8ded14bbd2c1deadaf308755a3',1,'stm32f407xx_matlab.h']]], - ['spi_5fcr1_5fcpha_5fmsk_541',['SPI_CR1_CPHA_Msk',['../group___peripheral___registers___bits___definition.html#ga07233629d8982af09168080501d30522',1,'stm32f407xx_matlab.h']]], - ['spi_5fcr1_5fcpha_5fpos_542',['SPI_CR1_CPHA_Pos',['../group___peripheral___registers___bits___definition.html#ga2f1d2c5a9e481ca06d0e29332f6f948a',1,'stm32f407xx_matlab.h']]], - ['spi_5fcr1_5fcpol_543',['SPI_CR1_CPOL',['../group___peripheral___registers___bits___definition.html#ga2616a10f5118cdc68fbdf0582481e124',1,'stm32f407xx_matlab.h']]], - ['spi_5fcr1_5fcpol_5fmsk_544',['SPI_CR1_CPOL_Msk',['../group___peripheral___registers___bits___definition.html#ga95caab18b821909a9547771f9316e2b0',1,'stm32f407xx_matlab.h']]], - ['spi_5fcr1_5fcpol_5fpos_545',['SPI_CR1_CPOL_Pos',['../group___peripheral___registers___bits___definition.html#gadd3274c0dce6293370773c5050f9c4be',1,'stm32f407xx_matlab.h']]], - ['spi_5fcr1_5fcrcen_546',['SPI_CR1_CRCEN',['../group___peripheral___registers___bits___definition.html#gac9339b7c6466f09ad26c26b3bb81c51b',1,'stm32f407xx_matlab.h']]], - ['spi_5fcr1_5fcrcen_5fmsk_547',['SPI_CR1_CRCEN_Msk',['../group___peripheral___registers___bits___definition.html#ga2a5a712f31c65ea8ee829377edc5ede3',1,'stm32f407xx_matlab.h']]], - ['spi_5fcr1_5fcrcen_5fpos_548',['SPI_CR1_CRCEN_Pos',['../group___peripheral___registers___bits___definition.html#ga54cb3022c5e3d98cd81a7ff1cb087fac',1,'stm32f407xx_matlab.h']]], - ['spi_5fcr1_5fcrcnext_549',['SPI_CR1_CRCNEXT',['../group___peripheral___registers___bits___definition.html#ga57072f13c2e54c12186ae8c5fdecb250',1,'stm32f407xx_matlab.h']]], - ['spi_5fcr1_5fcrcnext_5fmsk_550',['SPI_CR1_CRCNEXT_Msk',['../group___peripheral___registers___bits___definition.html#gaebbf9ed4a9723901f5414654f151d816',1,'stm32f407xx_matlab.h']]], - ['spi_5fcr1_5fcrcnext_5fpos_551',['SPI_CR1_CRCNEXT_Pos',['../group___peripheral___registers___bits___definition.html#ga4280bd0e8bcc3a268fa3a17b684499d7',1,'stm32f407xx_matlab.h']]], - ['spi_5fcr1_5fdff_552',['SPI_CR1_DFF',['../group___peripheral___registers___bits___definition.html#ga3ffabea0de695a19198d906bf6a1d9fd',1,'stm32f407xx_matlab.h']]], - ['spi_5fcr1_5fdff_5fmsk_553',['SPI_CR1_DFF_Msk',['../group___peripheral___registers___bits___definition.html#ga3a87fe55ac0f85e207a58fcd73610f46',1,'stm32f407xx_matlab.h']]], - ['spi_5fcr1_5fdff_5fpos_554',['SPI_CR1_DFF_Pos',['../group___peripheral___registers___bits___definition.html#ga5290662db14690d4bcf30ed9e4694462',1,'stm32f407xx_matlab.h']]], - ['spi_5fcr1_5flsbfirst_555',['SPI_CR1_LSBFIRST',['../group___peripheral___registers___bits___definition.html#gab929e9d5ddbb66f229c501ab18d0e6e8',1,'stm32f407xx_matlab.h']]], - ['spi_5fcr1_5flsbfirst_5fmsk_556',['SPI_CR1_LSBFIRST_Msk',['../group___peripheral___registers___bits___definition.html#gadfc0bbf312eaf7e0a5bbe54fdcc2f12e',1,'stm32f407xx_matlab.h']]], - ['spi_5fcr1_5flsbfirst_5fpos_557',['SPI_CR1_LSBFIRST_Pos',['../group___peripheral___registers___bits___definition.html#ga982b564879d1dc60a3be787409df0c27',1,'stm32f407xx_matlab.h']]], - ['spi_5fcr1_5fmstr_558',['SPI_CR1_MSTR',['../group___peripheral___registers___bits___definition.html#ga5b3b6ae107fc37bf18e14506298d7a55',1,'stm32f407xx_matlab.h']]], - ['spi_5fcr1_5fmstr_5fmsk_559',['SPI_CR1_MSTR_Msk',['../group___peripheral___registers___bits___definition.html#gab94621170d4ce16d6e7f2310461df97d',1,'stm32f407xx_matlab.h']]], - ['spi_5fcr1_5fmstr_5fpos_560',['SPI_CR1_MSTR_Pos',['../group___peripheral___registers___bits___definition.html#ga27567886a2c76d088e01ad16851cdb71',1,'stm32f407xx_matlab.h']]], - ['spi_5fcr1_5frxonly_561',['SPI_CR1_RXONLY',['../group___peripheral___registers___bits___definition.html#ga9ffecf774b84a8cdc11ab1f931791883',1,'stm32f407xx_matlab.h']]], - ['spi_5fcr1_5frxonly_5fmsk_562',['SPI_CR1_RXONLY_Msk',['../group___peripheral___registers___bits___definition.html#ga02d6321808ed988c60d703e062d58b64',1,'stm32f407xx_matlab.h']]], - ['spi_5fcr1_5frxonly_5fpos_563',['SPI_CR1_RXONLY_Pos',['../group___peripheral___registers___bits___definition.html#gadd702fae4dcca65f3b43b2e02f67ee7b',1,'stm32f407xx_matlab.h']]], - ['spi_5fcr1_5fspe_564',['SPI_CR1_SPE',['../group___peripheral___registers___bits___definition.html#gac5a646d978d3b98eb7c6a5d95d75c3f9',1,'stm32f407xx_matlab.h']]], - ['spi_5fcr1_5fspe_5fmsk_565',['SPI_CR1_SPE_Msk',['../group___peripheral___registers___bits___definition.html#ga5cf4679f3fe8cfa50ecbac5b45d084bb',1,'stm32f407xx_matlab.h']]], - ['spi_5fcr1_5fspe_5fpos_566',['SPI_CR1_SPE_Pos',['../group___peripheral___registers___bits___definition.html#ga3f5515b536f82c1d91a64bd534030284',1,'stm32f407xx_matlab.h']]], - ['spi_5fcr1_5fssi_567',['SPI_CR1_SSI',['../group___peripheral___registers___bits___definition.html#ga5f154374b58c0234f82ea326cb303a1e',1,'stm32f407xx_matlab.h']]], - ['spi_5fcr1_5fssi_5fmsk_568',['SPI_CR1_SSI_Msk',['../group___peripheral___registers___bits___definition.html#gaf0bfe153c59ffd52199d4b37e3287f89',1,'stm32f407xx_matlab.h']]], - ['spi_5fcr1_5fssi_5fpos_569',['SPI_CR1_SSI_Pos',['../group___peripheral___registers___bits___definition.html#gad99cf4909aa9307e01f61645451a9d0e',1,'stm32f407xx_matlab.h']]], - ['spi_5fcr1_5fssm_570',['SPI_CR1_SSM',['../group___peripheral___registers___bits___definition.html#ga0e236047e05106cf1ba7929766311382',1,'stm32f407xx_matlab.h']]], - ['spi_5fcr1_5fssm_5fmsk_571',['SPI_CR1_SSM_Msk',['../group___peripheral___registers___bits___definition.html#ga43417092a8ed735def35b386a251a7bb',1,'stm32f407xx_matlab.h']]], - ['spi_5fcr1_5fssm_5fpos_572',['SPI_CR1_SSM_Pos',['../group___peripheral___registers___bits___definition.html#gab2909290fab17ee930afc335811f574c',1,'stm32f407xx_matlab.h']]], - ['spi_5fcr2_5ferrie_573',['SPI_CR2_ERRIE',['../group___peripheral___registers___bits___definition.html#gaf18705567de7ab52a62e5ef3ba27418b',1,'stm32f407xx_matlab.h']]], - ['spi_5fcr2_5ferrie_5fmsk_574',['SPI_CR2_ERRIE_Msk',['../group___peripheral___registers___bits___definition.html#ga0fb21a03a7b4e7bd38520e2909063c92',1,'stm32f407xx_matlab.h']]], - ['spi_5fcr2_5ferrie_5fpos_575',['SPI_CR2_ERRIE_Pos',['../group___peripheral___registers___bits___definition.html#ga632cdba8557df9c3bbd2561b93f4e0f7',1,'stm32f407xx_matlab.h']]], - ['spi_5fcr2_5ffrf_576',['SPI_CR2_FRF',['../group___peripheral___registers___bits___definition.html#ga09e3f41fa2150831afaac191046087f2',1,'stm32f407xx_matlab.h']]], - ['spi_5fcr2_5ffrf_5fmsk_577',['SPI_CR2_FRF_Msk',['../group___peripheral___registers___bits___definition.html#ga47060f3941e2410bd9bc3b570f39a3d1',1,'stm32f407xx_matlab.h']]], - ['spi_5fcr2_5ffrf_5fpos_578',['SPI_CR2_FRF_Pos',['../group___peripheral___registers___bits___definition.html#gaa192ac1c1066c8867a6fec7de630d222',1,'stm32f407xx_matlab.h']]], - ['spi_5fcr2_5frxdmaen_579',['SPI_CR2_RXDMAEN',['../group___peripheral___registers___bits___definition.html#gaf23c590d98279634af05550702a806da',1,'stm32f407xx_matlab.h']]], - ['spi_5fcr2_5frxdmaen_5fmsk_580',['SPI_CR2_RXDMAEN_Msk',['../group___peripheral___registers___bits___definition.html#gae038c9a5d545c01038bf6628492cdc6e',1,'stm32f407xx_matlab.h']]], - ['spi_5fcr2_5frxdmaen_5fpos_581',['SPI_CR2_RXDMAEN_Pos',['../group___peripheral___registers___bits___definition.html#ga3079c4eebd0aef7bd22817bb99f21021',1,'stm32f407xx_matlab.h']]], - ['spi_5fcr2_5frxneie_582',['SPI_CR2_RXNEIE',['../group___peripheral___registers___bits___definition.html#gaa7d4c37fbbcced7f2a0421e6ffd103ea',1,'stm32f407xx_matlab.h']]], - ['spi_5fcr2_5frxneie_5fmsk_583',['SPI_CR2_RXNEIE_Msk',['../group___peripheral___registers___bits___definition.html#ga3ad371f3900a415251ab34cd186d9a44',1,'stm32f407xx_matlab.h']]], - ['spi_5fcr2_5frxneie_5fpos_584',['SPI_CR2_RXNEIE_Pos',['../group___peripheral___registers___bits___definition.html#gaf2e1e16fa6007b96880333d0321c5971',1,'stm32f407xx_matlab.h']]], - ['spi_5fcr2_5fssoe_585',['SPI_CR2_SSOE',['../group___peripheral___registers___bits___definition.html#gae94612b95395eff626f5f3d7d28352dd',1,'stm32f407xx_matlab.h']]], - ['spi_5fcr2_5fssoe_5fmsk_586',['SPI_CR2_SSOE_Msk',['../group___peripheral___registers___bits___definition.html#ga4de245d8ff3e31709fd9a665e58f15c1',1,'stm32f407xx_matlab.h']]], - ['spi_5fcr2_5fssoe_5fpos_587',['SPI_CR2_SSOE_Pos',['../group___peripheral___registers___bits___definition.html#gaa0d0f5f51a5804e1a204bf1643516896',1,'stm32f407xx_matlab.h']]], - ['spi_5fcr2_5ftxdmaen_588',['SPI_CR2_TXDMAEN',['../group___peripheral___registers___bits___definition.html#ga3eee671793983a3bd669c9173b2ce210',1,'stm32f407xx_matlab.h']]], - ['spi_5fcr2_5ftxdmaen_5fmsk_589',['SPI_CR2_TXDMAEN_Msk',['../group___peripheral___registers___bits___definition.html#ga884bb8bbd8b60cea7b7fb11a23231678',1,'stm32f407xx_matlab.h']]], - ['spi_5fcr2_5ftxdmaen_5fpos_590',['SPI_CR2_TXDMAEN_Pos',['../group___peripheral___registers___bits___definition.html#ga24ae89d7e48296566cd18fb7495a2c81',1,'stm32f407xx_matlab.h']]], - ['spi_5fcr2_5ftxeie_591',['SPI_CR2_TXEIE',['../group___peripheral___registers___bits___definition.html#ga23f683a1252ccaf625cae1a978989b2c',1,'stm32f407xx_matlab.h']]], - ['spi_5fcr2_5ftxeie_5fmsk_592',['SPI_CR2_TXEIE_Msk',['../group___peripheral___registers___bits___definition.html#ga64d3cd4fd2b7dca5e43332a3e2a36641',1,'stm32f407xx_matlab.h']]], - ['spi_5fcr2_5ftxeie_5fpos_593',['SPI_CR2_TXEIE_Pos',['../group___peripheral___registers___bits___definition.html#ga01e9b00dc195c10d1baefd0687ab9262',1,'stm32f407xx_matlab.h']]], - ['spi_5fcrcpr_5fcrcpoly_594',['SPI_CRCPR_CRCPOLY',['../group___peripheral___registers___bits___definition.html#gae968658ab837800723eafcc21af10247',1,'stm32f407xx_matlab.h']]], - ['spi_5fcrcpr_5fcrcpoly_5fmsk_595',['SPI_CRCPR_CRCPOLY_Msk',['../group___peripheral___registers___bits___definition.html#ga67c234978a817dee4fc561201b3ef056',1,'stm32f407xx_matlab.h']]], - ['spi_5fcrcpr_5fcrcpoly_5fpos_596',['SPI_CRCPR_CRCPOLY_Pos',['../group___peripheral___registers___bits___definition.html#ga0244eb48f4c5158b03dd4b26cc0d2eac',1,'stm32f407xx_matlab.h']]], - ['spi_5fdr_5fdr_597',['SPI_DR_DR',['../group___peripheral___registers___bits___definition.html#gaa4da7d7f05a28d1aaa52ec557e55e1ad',1,'stm32f407xx_matlab.h']]], - ['spi_5fdr_5fdr_5fmsk_598',['SPI_DR_DR_Msk',['../group___peripheral___registers___bits___definition.html#gaf50021b52352481a497f21c72c33e966',1,'stm32f407xx_matlab.h']]], - ['spi_5fdr_5fdr_5fpos_599',['SPI_DR_DR_Pos',['../group___peripheral___registers___bits___definition.html#ga5b57ca6bca45cfdaed4a26fefc0da85f',1,'stm32f407xx_matlab.h']]], - ['spi_5fi2s_5ffullduplex_5fsupport_600',['SPI_I2S_FULLDUPLEX_SUPPORT',['../group___peripheral___registers___bits___definition.html#gadf384b964839c07357ce8503464436ed',1,'stm32f407xx_matlab.h']]], - ['spi_5fi2scfgr_5fchlen_601',['SPI_I2SCFGR_CHLEN',['../group___peripheral___registers___bits___definition.html#ga9c362b3d703698a7891f032f6b29056f',1,'stm32f407xx_matlab.h']]], - ['spi_5fi2scfgr_5fchlen_5fmsk_602',['SPI_I2SCFGR_CHLEN_Msk',['../group___peripheral___registers___bits___definition.html#ga7a842b52587ad0e434153bf9df2ecc50',1,'stm32f407xx_matlab.h']]], - ['spi_5fi2scfgr_5fchlen_5fpos_603',['SPI_I2SCFGR_CHLEN_Pos',['../group___peripheral___registers___bits___definition.html#ga7ea301a1a44423c53d2d388a9c7677bd',1,'stm32f407xx_matlab.h']]], - ['spi_5fi2scfgr_5fckpol_604',['SPI_I2SCFGR_CKPOL',['../group___peripheral___registers___bits___definition.html#ga5c5be1f1c8b4689643e04cd5034e7f5f',1,'stm32f407xx_matlab.h']]], - ['spi_5fi2scfgr_5fckpol_5fmsk_605',['SPI_I2SCFGR_CKPOL_Msk',['../group___peripheral___registers___bits___definition.html#ga7b3b7c3f4fc9a499410bff94553534f5',1,'stm32f407xx_matlab.h']]], - ['spi_5fi2scfgr_5fckpol_5fpos_606',['SPI_I2SCFGR_CKPOL_Pos',['../group___peripheral___registers___bits___definition.html#ga2bf83ceaefcb4190b2fb5ae09f659d8d',1,'stm32f407xx_matlab.h']]], - ['spi_5fi2scfgr_5fdatlen_607',['SPI_I2SCFGR_DATLEN',['../group___peripheral___registers___bits___definition.html#gacc12f9d2003ab169a3f68e9d809f84ae',1,'stm32f407xx_matlab.h']]], - ['spi_5fi2scfgr_5fdatlen_5f0_608',['SPI_I2SCFGR_DATLEN_0',['../group___peripheral___registers___bits___definition.html#gaa20ad624085d2e533eea3662cb03d8fa',1,'stm32f407xx_matlab.h']]], - ['spi_5fi2scfgr_5fdatlen_5f1_609',['SPI_I2SCFGR_DATLEN_1',['../group___peripheral___registers___bits___definition.html#gadf6e940d195fa1633cb1b23414f00412',1,'stm32f407xx_matlab.h']]], - ['spi_5fi2scfgr_5fdatlen_5fmsk_610',['SPI_I2SCFGR_DATLEN_Msk',['../group___peripheral___registers___bits___definition.html#gabbffb30650c0d4c84232813213271169',1,'stm32f407xx_matlab.h']]], - ['spi_5fi2scfgr_5fdatlen_5fpos_611',['SPI_I2SCFGR_DATLEN_Pos',['../group___peripheral___registers___bits___definition.html#ga5a60bd1db55a2dfcf20a834e9ad05a66',1,'stm32f407xx_matlab.h']]], - ['spi_5fi2scfgr_5fi2scfg_612',['SPI_I2SCFGR_I2SCFG',['../group___peripheral___registers___bits___definition.html#gaf09fd11f6f97000266b30b015bf2cb68',1,'stm32f407xx_matlab.h']]], - ['spi_5fi2scfgr_5fi2scfg_5f0_613',['SPI_I2SCFGR_I2SCFG_0',['../group___peripheral___registers___bits___definition.html#ga421c94680ee8a2583419e2b0c89e995e',1,'stm32f407xx_matlab.h']]], - ['spi_5fi2scfgr_5fi2scfg_5f1_614',['SPI_I2SCFGR_I2SCFG_1',['../group___peripheral___registers___bits___definition.html#ga80c398b9e79fcc61a497f9d7dd910352',1,'stm32f407xx_matlab.h']]], - ['spi_5fi2scfgr_5fi2scfg_5fmsk_615',['SPI_I2SCFGR_I2SCFG_Msk',['../group___peripheral___registers___bits___definition.html#gac3ca3fbea0bb2c306c0d7f4bcaee8b0d',1,'stm32f407xx_matlab.h']]], - ['spi_5fi2scfgr_5fi2scfg_5fpos_616',['SPI_I2SCFGR_I2SCFG_Pos',['../group___peripheral___registers___bits___definition.html#ga7c7f5184bc8db838c594b07965e81619',1,'stm32f407xx_matlab.h']]], - ['spi_5fi2scfgr_5fi2se_617',['SPI_I2SCFGR_I2SE',['../group___peripheral___registers___bits___definition.html#ga30d76c7552c91bbd5cbac70d9c56ebb3',1,'stm32f407xx_matlab.h']]], - ['spi_5fi2scfgr_5fi2se_5fmsk_618',['SPI_I2SCFGR_I2SE_Msk',['../group___peripheral___registers___bits___definition.html#gafefdd032e0fcf3d4d73f5bf167f74c6b',1,'stm32f407xx_matlab.h']]], - ['spi_5fi2scfgr_5fi2se_5fpos_619',['SPI_I2SCFGR_I2SE_Pos',['../group___peripheral___registers___bits___definition.html#ga967de848b594a623b10019d912266ed3',1,'stm32f407xx_matlab.h']]], - ['spi_5fi2scfgr_5fi2smod_620',['SPI_I2SCFGR_I2SMOD',['../group___peripheral___registers___bits___definition.html#gae99763414b3c2f11fcfecb1f93eb6701',1,'stm32f407xx_matlab.h']]], - ['spi_5fi2scfgr_5fi2smod_5fmsk_621',['SPI_I2SCFGR_I2SMOD_Msk',['../group___peripheral___registers___bits___definition.html#gaa67cab1dd9189de25a0aec2cce90479a',1,'stm32f407xx_matlab.h']]], - ['spi_5fi2scfgr_5fi2smod_5fpos_622',['SPI_I2SCFGR_I2SMOD_Pos',['../group___peripheral___registers___bits___definition.html#ga443830d47e0ebc5e0141dad4a7d43978',1,'stm32f407xx_matlab.h']]], - ['spi_5fi2scfgr_5fi2sstd_623',['SPI_I2SCFGR_I2SSTD',['../group___peripheral___registers___bits___definition.html#ga7a822a80be3a51524b42491248f8031f',1,'stm32f407xx_matlab.h']]], - ['spi_5fi2scfgr_5fi2sstd_5f0_624',['SPI_I2SCFGR_I2SSTD_0',['../group___peripheral___registers___bits___definition.html#gafeba0a45703463dfe05334364bdacbe8',1,'stm32f407xx_matlab.h']]], - ['spi_5fi2scfgr_5fi2sstd_5f1_625',['SPI_I2SCFGR_I2SSTD_1',['../group___peripheral___registers___bits___definition.html#ga0142a3667f59bce9bae80d31e88a124a',1,'stm32f407xx_matlab.h']]], - ['spi_5fi2scfgr_5fi2sstd_5fmsk_626',['SPI_I2SCFGR_I2SSTD_Msk',['../group___peripheral___registers___bits___definition.html#gaff08fac3bb90bd73b0bdadddb6a1411a',1,'stm32f407xx_matlab.h']]], - ['spi_5fi2scfgr_5fi2sstd_5fpos_627',['SPI_I2SCFGR_I2SSTD_Pos',['../group___peripheral___registers___bits___definition.html#ga8d794bb7f4327025db354ad26bf83986',1,'stm32f407xx_matlab.h']]], - ['spi_5fi2scfgr_5fpcmsync_628',['SPI_I2SCFGR_PCMSYNC',['../group___peripheral___registers___bits___definition.html#ga66a29efc32a31f903e89b7ddcd20857b',1,'stm32f407xx_matlab.h']]], - ['spi_5fi2scfgr_5fpcmsync_5fmsk_629',['SPI_I2SCFGR_PCMSYNC_Msk',['../group___peripheral___registers___bits___definition.html#gaeecf52a47dc8d82d6e3d3951c51f4dc1',1,'stm32f407xx_matlab.h']]], - ['spi_5fi2scfgr_5fpcmsync_5fpos_630',['SPI_I2SCFGR_PCMSYNC_Pos',['../group___peripheral___registers___bits___definition.html#gaf486d8ce50abc465f372b6fcc7a0704d',1,'stm32f407xx_matlab.h']]], - ['spi_5fi2spr_5fi2sdiv_631',['SPI_I2SPR_I2SDIV',['../group___peripheral___registers___bits___definition.html#ga406ce88b2580a421f5b28bdbeb303543',1,'stm32f407xx_matlab.h']]], - ['spi_5fi2spr_5fi2sdiv_5fmsk_632',['SPI_I2SPR_I2SDIV_Msk',['../group___peripheral___registers___bits___definition.html#ga1ae53c9d1c862f377fb76fb253324ac4',1,'stm32f407xx_matlab.h']]], - ['spi_5fi2spr_5fi2sdiv_5fpos_633',['SPI_I2SPR_I2SDIV_Pos',['../group___peripheral___registers___bits___definition.html#gab840a9d53e7de5f0de74d20d5e11e0fa',1,'stm32f407xx_matlab.h']]], - ['spi_5fi2spr_5fmckoe_634',['SPI_I2SPR_MCKOE',['../group___peripheral___registers___bits___definition.html#ga25669c3686c0c577d2d371ac09200ff0',1,'stm32f407xx_matlab.h']]], - ['spi_5fi2spr_5fmckoe_5fmsk_635',['SPI_I2SPR_MCKOE_Msk',['../group___peripheral___registers___bits___definition.html#gaa466ff1b4340cc07fd6362f7bfb173f4',1,'stm32f407xx_matlab.h']]], - ['spi_5fi2spr_5fmckoe_5fpos_636',['SPI_I2SPR_MCKOE_Pos',['../group___peripheral___registers___bits___definition.html#ga1219b3f0097930dd635f434a019d38c6',1,'stm32f407xx_matlab.h']]], - ['spi_5fi2spr_5fodd_637',['SPI_I2SPR_ODD',['../group___peripheral___registers___bits___definition.html#ga3d6d4136a5ae12f9bd5940324282355a',1,'stm32f407xx_matlab.h']]], - ['spi_5fi2spr_5fodd_5fmsk_638',['SPI_I2SPR_ODD_Msk',['../group___peripheral___registers___bits___definition.html#gad8892fa60c17ea6a9a645671d4d6ffdc',1,'stm32f407xx_matlab.h']]], - ['spi_5fi2spr_5fodd_5fpos_639',['SPI_I2SPR_ODD_Pos',['../group___peripheral___registers___bits___definition.html#gabfb7274ed8833e66663a995ca074c1d9',1,'stm32f407xx_matlab.h']]], - ['spi_5frxcrcr_5frxcrc_640',['SPI_RXCRCR_RXCRC',['../group___peripheral___registers___bits___definition.html#ga3a01a578c2c7bb4e587a8f1610843181',1,'stm32f407xx_matlab.h']]], - ['spi_5frxcrcr_5frxcrc_5fmsk_641',['SPI_RXCRCR_RXCRC_Msk',['../group___peripheral___registers___bits___definition.html#ga3318f05b5d1bebf96434ae4bc88e46da',1,'stm32f407xx_matlab.h']]], - ['spi_5frxcrcr_5frxcrc_5fpos_642',['SPI_RXCRCR_RXCRC_Pos',['../group___peripheral___registers___bits___definition.html#ga2b80d92a2b51c4c61d5a646ac2b36129',1,'stm32f407xx_matlab.h']]], - ['spi_5fsr_5fbsy_643',['SPI_SR_BSY',['../group___peripheral___registers___bits___definition.html#gaa3498df67729ae048dc5f315ef7c16bf',1,'stm32f407xx_matlab.h']]], - ['spi_5fsr_5fbsy_5fmsk_644',['SPI_SR_BSY_Msk',['../group___peripheral___registers___bits___definition.html#gafcecff7ba1632cf4035a83dd588c4421',1,'stm32f407xx_matlab.h']]], - ['spi_5fsr_5fbsy_5fpos_645',['SPI_SR_BSY_Pos',['../group___peripheral___registers___bits___definition.html#ga8313629719f8dc81536dd8faa824e6c8',1,'stm32f407xx_matlab.h']]], - ['spi_5fsr_5fchside_646',['SPI_SR_CHSIDE',['../group___peripheral___registers___bits___definition.html#ga81bd052f0b2e819ddd6bb16c2292a2de',1,'stm32f407xx_matlab.h']]], - ['spi_5fsr_5fchside_5fmsk_647',['SPI_SR_CHSIDE_Msk',['../group___peripheral___registers___bits___definition.html#ga226666adbdbd46974bcc4a05772bbfc4',1,'stm32f407xx_matlab.h']]], - ['spi_5fsr_5fchside_5fpos_648',['SPI_SR_CHSIDE_Pos',['../group___peripheral___registers___bits___definition.html#gae5b742da8b06539f6119d020885a6e0c',1,'stm32f407xx_matlab.h']]], - ['spi_5fsr_5fcrcerr_649',['SPI_SR_CRCERR',['../group___peripheral___registers___bits___definition.html#ga69e543fa9584fd636032a3ee735f750b',1,'stm32f407xx_matlab.h']]], - ['spi_5fsr_5fcrcerr_5fmsk_650',['SPI_SR_CRCERR_Msk',['../group___peripheral___registers___bits___definition.html#gad4f508924f9e531136bf0d4fadb68d48',1,'stm32f407xx_matlab.h']]], - ['spi_5fsr_5fcrcerr_5fpos_651',['SPI_SR_CRCERR_Pos',['../group___peripheral___registers___bits___definition.html#ga411b6a4aa85d06e425050130f82db35c',1,'stm32f407xx_matlab.h']]], - ['spi_5fsr_5ffre_652',['SPI_SR_FRE',['../group___peripheral___registers___bits___definition.html#gace2c7cac9431231663af42e6f5aabce6',1,'stm32f407xx_matlab.h']]], - ['spi_5fsr_5ffre_5fmsk_653',['SPI_SR_FRE_Msk',['../group___peripheral___registers___bits___definition.html#gabd7e467f149f7b4f7c6eb2deb8be5338',1,'stm32f407xx_matlab.h']]], - ['spi_5fsr_5ffre_5fpos_654',['SPI_SR_FRE_Pos',['../group___peripheral___registers___bits___definition.html#gafb0e70677f5775a55044111eb83e1ba6',1,'stm32f407xx_matlab.h']]], - ['spi_5fsr_5fmodf_655',['SPI_SR_MODF',['../group___peripheral___registers___bits___definition.html#gabaa043349833dc7b8138969c64f63adf',1,'stm32f407xx_matlab.h']]], - ['spi_5fsr_5fmodf_5fmsk_656',['SPI_SR_MODF_Msk',['../group___peripheral___registers___bits___definition.html#ga3db9b07f317546b9f724067956b07e9c',1,'stm32f407xx_matlab.h']]], - ['spi_5fsr_5fmodf_5fpos_657',['SPI_SR_MODF_Pos',['../group___peripheral___registers___bits___definition.html#gafb7ef73b03bbd542c54fc4e9c9124e73',1,'stm32f407xx_matlab.h']]], - ['spi_5fsr_5fovr_658',['SPI_SR_OVR',['../group___peripheral___registers___bits___definition.html#gaa8d902302c5eb81ce4a57029de281232',1,'stm32f407xx_matlab.h']]], - ['spi_5fsr_5fovr_5fmsk_659',['SPI_SR_OVR_Msk',['../group___peripheral___registers___bits___definition.html#ga73daf0783ad13468420bbf4d05e150dd',1,'stm32f407xx_matlab.h']]], - ['spi_5fsr_5fovr_5fpos_660',['SPI_SR_OVR_Pos',['../group___peripheral___registers___bits___definition.html#ga6137ac3afbbc8b50c7a998368d2cb9be',1,'stm32f407xx_matlab.h']]], - ['spi_5fsr_5frxne_661',['SPI_SR_RXNE',['../group___peripheral___registers___bits___definition.html#ga40e14de547aa06864abcd4b0422d8b48',1,'stm32f407xx_matlab.h']]], - ['spi_5fsr_5frxne_5fmsk_662',['SPI_SR_RXNE_Msk',['../group___peripheral___registers___bits___definition.html#ga85e7198d3d1f577cae637c8295e7691e',1,'stm32f407xx_matlab.h']]], - ['spi_5fsr_5frxne_5fpos_663',['SPI_SR_RXNE_Pos',['../group___peripheral___registers___bits___definition.html#ga306a27b203d1275f848f2767d76c9e3b',1,'stm32f407xx_matlab.h']]], - ['spi_5fsr_5ftxe_664',['SPI_SR_TXE',['../group___peripheral___registers___bits___definition.html#ga5bd5d21816947fcb25ccae7d3bf8eb2c',1,'stm32f407xx_matlab.h']]], - ['spi_5fsr_5ftxe_5fmsk_665',['SPI_SR_TXE_Msk',['../group___peripheral___registers___bits___definition.html#gaee9564d438c48424c767347324a2eb03',1,'stm32f407xx_matlab.h']]], - ['spi_5fsr_5ftxe_5fpos_666',['SPI_SR_TXE_Pos',['../group___peripheral___registers___bits___definition.html#ga92e10388eb117c22b63994b491d9ec9d',1,'stm32f407xx_matlab.h']]], - ['spi_5fsr_5fudr_667',['SPI_SR_UDR',['../group___peripheral___registers___bits___definition.html#ga13d3292e963499c0e9a36869909229e6',1,'stm32f407xx_matlab.h']]], - ['spi_5fsr_5fudr_5fmsk_668',['SPI_SR_UDR_Msk',['../group___peripheral___registers___bits___definition.html#ga1ceaae6d492b8b844ff2b83e3251d28e',1,'stm32f407xx_matlab.h']]], - ['spi_5fsr_5fudr_5fpos_669',['SPI_SR_UDR_Pos',['../group___peripheral___registers___bits___definition.html#ga93586e3966e74b1df8dbda75e68b26f0',1,'stm32f407xx_matlab.h']]], - ['spi_5ftxcrcr_5ftxcrc_670',['SPI_TXCRCR_TXCRC',['../group___peripheral___registers___bits___definition.html#ga1c69dc721e89e40056999b64572dff09',1,'stm32f407xx_matlab.h']]], - ['spi_5ftxcrcr_5ftxcrc_5fmsk_671',['SPI_TXCRCR_TXCRC_Msk',['../group___peripheral___registers___bits___definition.html#gaca1f646ca0bb6ae44744956b39b0702d',1,'stm32f407xx_matlab.h']]], - ['spi_5ftxcrcr_5ftxcrc_5fpos_672',['SPI_TXCRCR_TXCRC_Pos',['../group___peripheral___registers___bits___definition.html#ga0a0e6e24778c36e45838350d052916d1',1,'stm32f407xx_matlab.h']]], - ['spi_5ftypedef_673',['SPI_TypeDef',['../struct_s_p_i___type_def.html',1,'']]], - ['sppr_674',['SPPR',['../group___c_m_s_i_s__core___debug_functions.html#gae9673e1acb75a46ed9852fd7a557cb7d',1,'TPI_Type']]], - ['spsel_675',['SPSEL',['../group___c_m_s_i_s__core___debug_functions.html#gae185aac93686ffc78e998a9daf41415b',1,'CONTROL_Type::SPSEL'],['../group___c_m_s_i_s__core___debug_functions.html#gae185aac93686ffc78e998a9daf41415b',1,'CONTROL_Type::@3::SPSEL']]], - ['sqr1_676',['SQR1',['../group___c_m_s_i_s___device.html#ga3302e1bcfdfbbfeb58779d0761fb377c',1,'ADC_TypeDef']]], - ['sqr2_677',['SQR2',['../group___c_m_s_i_s___device.html#gaab440b0ad8631f5666dd32768a89cf60',1,'ADC_TypeDef']]], - ['sqr3_678',['SQR3',['../group___c_m_s_i_s___device.html#ga97e40d9928fa25a5628d6442f0aa6c0f',1,'ADC_TypeDef']]], - ['sr_679',['SR',['../group___c_m_s_i_s___device.html#ga081f4304e18753e5e8d0afd71ccca45e',1,'ADC_TypeDef::SR'],['../group___c_m_s_i_s___device.html#gaf6aca2bbd40c0fb6df7c3aebe224a360',1,'DAC_TypeDef::SR'],['../group___c_m_s_i_s___device.html#gaf6aca2bbd40c0fb6df7c3aebe224a360',1,'DCMI_TypeDef::SR'],['../group___c_m_s_i_s___device.html#gaf6aca2bbd40c0fb6df7c3aebe224a360',1,'FLASH_TypeDef::SR'],['../group___c_m_s_i_s___device.html#gaf6aca2bbd40c0fb6df7c3aebe224a360',1,'IWDG_TypeDef::SR'],['../group___c_m_s_i_s___device.html#gaf6aca2bbd40c0fb6df7c3aebe224a360',1,'SPI_TypeDef::SR'],['../group___c_m_s_i_s___device.html#gaf6aca2bbd40c0fb6df7c3aebe224a360',1,'TIM_TypeDef::SR'],['../group___c_m_s_i_s___device.html#gaf6aca2bbd40c0fb6df7c3aebe224a360',1,'USART_TypeDef::SR'],['../group___c_m_s_i_s___device.html#gaf6aca2bbd40c0fb6df7c3aebe224a360',1,'WWDG_TypeDef::SR'],['../group___c_m_s_i_s___device.html#gaf6aca2bbd40c0fb6df7c3aebe224a360',1,'RNG_TypeDef::SR']]], - ['sr1_680',['SR1',['../group___c_m_s_i_s___device.html#gacefca4fd83c4b7846ae6d3cfe7bb8df9',1,'I2C_TypeDef']]], - ['sr2_681',['SR2',['../group___c_m_s_i_s___device.html#ga89623ee198737b29dc0a803310605a83',1,'FSMC_Bank2_3_TypeDef::SR2'],['../group___c_m_s_i_s___device.html#ga89623ee198737b29dc0a803310605a83',1,'I2C_TypeDef::SR2']]], - ['sr3_682',['SR3',['../group___c_m_s_i_s___device.html#gaf30c34f7c606cb9416a413ec5fa36491',1,'FSMC_Bank2_3_TypeDef']]], - ['sr4_683',['SR4',['../group___c_m_s_i_s___device.html#ga8218d6e11dae5d4468c69303dec0b4fc',1,'FSMC_Bank4_TypeDef']]], - ['sram1_5fbase_684',['SRAM1_BASE',['../group___c_m_s_i_s___device.html#gac7c83f52956da4c75f4946348f7bfa1a',1,'_memory::SRAM1_BASE'],['../group___peripheral__memory__map.html#ga7d0fbfb8894012dbbb96754b95e562cd',1,'SRAM1_BASE: stm32f407xx_matlab.h']]], - ['sram1_5fbase_5fshift_685',['SRAM1_BASE_SHIFT',['../group___peripheral__memory__map.html#gac53e3a39a0ebd3520aaa373ae44ff838',1,'stm32f407xx_matlab.h']]], - ['sram1_5fbb_5fbase_686',['SRAM1_BB_BASE',['../group___c_m_s_i_s___device.html#gac88d0add27755615a9390fec8c64dafc',1,'_memory::SRAM1_BB_BASE'],['../group___peripheral__memory__map.html#gac4c4f61082e4b168f29d9cf97dc3ca5c',1,'SRAM1_BB_BASE: stm32f407xx_matlab.h']]], - ['sram1_5fbb_5fbase_5fshift_687',['SRAM1_BB_BASE_SHIFT',['../group___peripheral__memory__map.html#ga9d4c99653d22992b3b4b1537ade15d21',1,'stm32f407xx_matlab.h']]], - ['sram1_5fbb_5fsize_688',['SRAM1_BB_SIZE',['../group___peripheral__memory__map.html#ga4d759a2722aeeb47a81dd047d4e1790e',1,'stm32f407xx_matlab.h']]], - ['sram1_5fsize_689',['SRAM1_SIZE',['../group___peripheral__memory__map.html#gacf1c7f7eb345f8e1b617fd1b16320111',1,'stm32f407xx_matlab.h']]], - ['sram2_5fbase_690',['SRAM2_BASE',['../group___c_m_s_i_s___device.html#ga57bfa1d7c82d97792cbb6c2d366dd48d',1,'_memory::SRAM2_BASE'],['../group___peripheral__memory__map.html#gadbb42a3d0a8a90a79d2146e4014241b1',1,'SRAM2_BASE: stm32f407xx_matlab.h']]], - ['sram2_5fbase_5fshift_691',['SRAM2_BASE_SHIFT',['../group___peripheral__memory__map.html#gaff8892343768799209d59c2c33848222',1,'stm32f407xx_matlab.h']]], - ['sram2_5fbb_5fbase_692',['SRAM2_BB_BASE',['../group___c_m_s_i_s___device.html#ga5db33a541cebb596c2976d4fc409a611',1,'_memory::SRAM2_BB_BASE'],['../group___peripheral__memory__map.html#gac33cb6edadf184ab9860d77089503922',1,'SRAM2_BB_BASE: stm32f407xx_matlab.h']]], - ['sram2_5fbb_5fbase_5fshift_693',['SRAM2_BB_BASE_SHIFT',['../group___peripheral__memory__map.html#ga1654496a485d04270e2208afa8e4fd5c',1,'stm32f407xx_matlab.h']]], - ['sram2_5fbb_5fsize_694',['SRAM2_BB_SIZE',['../group___peripheral__memory__map.html#ga146845582d93b1fa90c52f43f704c178',1,'stm32f407xx_matlab.h']]], - ['sram2_5fsize_695',['SRAM2_SIZE',['../group___peripheral__memory__map.html#gad89e757d25db6160b1aedeb58fcdac09',1,'stm32f407xx_matlab.h']]], - ['sram_5fbase_696',['SRAM_BASE',['../group___peripheral__memory__map.html#ga05e8f3d2e5868754a7cd88614955aecc',1,'stm32f407xx_matlab.h']]], - ['sram_5fbb_5fbase_697',['SRAM_BB_BASE',['../group___peripheral__memory__map.html#gad3548b6e2f017f39d399358f3ac98454',1,'stm32f407xx_matlab.h']]], - ['sscgr_698',['SSCGR',['../group___c_m_s_i_s___device.html#gaaef3da59eaf7c6dfdf9a12fd60ce58a8',1,'RCC_TypeDef']]], - ['sspsr_699',['SSPSR',['../group___c_m_s_i_s__core___debug_functions.html#ga1585b32a1ab860d0d77803475d08c7c6',1,'TPI_Type']]], - ['ssr_700',['SSR',['../group___c_m_s_i_s___device.html#ga8a868e5e76b52ced04c536be3dee08ec',1,'RTC_TypeDef']]], - ['sta_701',['STA',['../group___c_m_s_i_s___device.html#ga0633c88accff51e7cc9d1e9c3db950d9',1,'SDIO_TypeDef']]], - ['status_702',['status',['../mexing_8m.html#ab1dc10c44c3fef32dbb7508037a5a3d6',1,'mexing.m']]], - ['status_20and_20control_20registers_703',['Status and Control Registers',['../group___c_m_s_i_s___c_o_r_e.html',1,'']]], - ['stdint_2eh_704',['stdint.h',['../stdint_8h.html',1,'']]], - ['stir_705',['STIR',['../group___c_m_s_i_s__core___debug_functions.html#gada9cbba14ab1cc3fddd585f870932db8',1,'NVIC_Type']]], - ['stm_20длÑ_20matlab_706',['ЭмулÑтор STM Ð´Ð»Ñ MATLAB',['../md__f_1_2_work_2_projects_2_m_a_t_l_a_b_2matlab__stm__emulate_2_r_e_a_d_m_e.html#autotoc_md4',1,'']]], - ['stm32_707',['ОпиÑание Ñтуктуры ÑмулÑтора (пример Ð´Ð»Ñ STM32)',['../md__f_1_2_work_2_projects_2_m_a_t_l_a_b_2matlab__stm__emulate_2_r_e_a_d_m_e.html#autotoc_md2',1,'']]], - ['stm32_20emulator_708',['MATLAB STM32 EMULATOR',['../md__f_1_2_work_2_projects_2_m_a_t_l_a_b_2matlab__stm__emulate_2_r_e_a_d_m_e.html',1,'']]], - ['stm32f4_709',['STM32F4',['../group___library__configuration__section.html#ga84d985cb5667176091597f71ffdb9307',1,'stm32f4xx.h']]], - ['stm32f407xx_710',['Stm32f407xx',['../group__stm32f407xx.html',1,'']]], - ['stm32f407xx_5fmatlab_2eh_711',['stm32f407xx_matlab.h',['../stm32f407xx__matlab_8h.html',1,'']]], - ['stm32f4xx_712',['Stm32f4xx',['../group__stm32f4xx.html',1,'']]], - ['stm32f4xx_2eh_713',['stm32f4xx.h',['../stm32f4xx_8h.html',1,'']]], - ['stm32f4xx_5fmatlab_5fconf_2ec_714',['stm32f4xx_matlab_conf.c',['../stm32f4xx__matlab__conf_8c.html',1,'']]], - ['stm32f4xx_5fmatlab_5fconf_2eh_715',['stm32f4xx_matlab_conf.h',['../stm32f4xx__matlab__conf_8h.html',1,'']]], - ['stm32f4xx_5fmatlab_5fgpio_2ec_716',['stm32f4xx_matlab_gpio.c',['../stm32f4xx__matlab__gpio_8c.html',1,'']]], - ['stm32f4xx_5fmatlab_5fgpio_2eh_717',['stm32f4xx_matlab_gpio.h',['../stm32f4xx__matlab__gpio_8h.html',1,'']]], - ['stm32f4xx_5fmatlab_5frcc_2ec_718',['stm32f4xx_matlab_rcc.c',['../stm32f4xx__matlab__rcc_8c.html',1,'']]], - ['stm32f4xx_5fmatlab_5frcc_2eh_719',['stm32f4xx_matlab_rcc.h',['../stm32f4xx__matlab__rcc_8h.html',1,'']]], - ['stm32f4xx_5fmatlab_5ftim_2ec_720',['stm32f4xx_matlab_tim.c',['../stm32f4xx__matlab__tim_8c.html',1,'']]], - ['stm32f4xx_5fmatlab_5ftim_2eh_721',['stm32f4xx_matlab_tim.h',['../stm32f4xx__matlab__tim_8h.html',1,'']]], - ['stm32f4xx_5fperiph_5fregisters_2ec_722',['stm32f4xx_periph_registers.c',['../stm32f4xx__periph__registers_8c.html',1,'']]], - ['stm32f4xx_5fsystem_723',['Stm32f4xx_system',['../group__stm32f4xx__system.html',1,'']]], - ['stm32f4xx_5fsystem_5fexported_5fconstants_724',['STM32F4xx_System_Exported_Constants',['../group___s_t_m32_f4xx___system___exported___constants.html',1,'']]], - ['stm32f4xx_5fsystem_5fexported_5ffunctions_725',['STM32F4xx_System_Exported_Functions',['../group___s_t_m32_f4xx___system___exported___functions.html',1,'']]], - ['stm32f4xx_5fsystem_5fexported_5fmacros_726',['STM32F4xx_System_Exported_Macros',['../group___s_t_m32_f4xx___system___exported___macros.html',1,'']]], - ['stm32f4xx_5fsystem_5fexported_5ftypes_727',['STM32F4xx_System_Exported_types',['../group___s_t_m32_f4xx___system___exported__types.html',1,'']]], - ['stm32f4xx_5fsystem_5fincludes_728',['STM32F4xx_System_Includes',['../group___s_t_m32_f4xx___system___includes.html',1,'']]], - ['stm_5fsimulation_729',['STM_SIMULATION',['../group___s_t_m___s_i_m_u_l_a_t_i_o_n.html',1,'']]], - ['stxmailbox_730',['sTxMailBox',['../group___c_m_s_i_s___device.html#gae37503ab1a7bbd29846f94cdadf0a9ef',1,'CAN_TypeDef']]], - ['success_731',['SUCCESS',['../group___exported__types.html#gga8333b96c67f83cba354b3407fcbb6ee8ac7f69f7c9e5aea9b8f54cf02870e2bf8',1,'stm32f4xx.h']]], - ['svcall_5firqn_732',['SVCall_IRQn',['../group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a4ce820b3cc6cf3a796b41aadc0cf1237',1,'stm32f407xx_matlab.h']]], - ['swier_733',['SWIER',['../group___c_m_s_i_s___device.html#ga9eae93b6cc13d4d25e12f2224e2369c9',1,'EXTI_TypeDef']]], - ['swtrigr_734',['SWTRIGR',['../group___c_m_s_i_s___device.html#ga896bbb7153af0b67ad772360feaceeb4',1,'DAC_TypeDef']]], - ['syscfg_735',['syscfg',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga973efd19b15b8e1452258c3a02fda513',1,'stm32f4xx_periph_registers.c']]], - ['syscfg_736',['SYSCFG',['../group___peripheral__declaration.html#ga3c833fe1c486cb62250ccbca32899cb8',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fbase_737',['SYSCFG_BASE',['../group___peripheral__memory__map.html#ga62246020bf3b34b6a4d8d0e84ec79d3d',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fcmpcr_5fcmp_5fpd_738',['SYSCFG_CMPCR_CMP_PD',['../group___peripheral___registers___bits___definition.html#ga261292a3a7ca1f767915b2e2ec3a7806',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fcmpcr_5fcmp_5fpd_5fmsk_739',['SYSCFG_CMPCR_CMP_PD_Msk',['../group___peripheral___registers___bits___definition.html#ga1ff39240a251120eebbc18e4955be5db',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fcmpcr_5fcmp_5fpd_5fpos_740',['SYSCFG_CMPCR_CMP_PD_Pos',['../group___peripheral___registers___bits___definition.html#gad1747204ad5b1221e47a6610e46790e9',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fcmpcr_5fready_741',['SYSCFG_CMPCR_READY',['../group___peripheral___registers___bits___definition.html#gae16bcca9b727e68f11467b6b3dad6215',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fcmpcr_5fready_5fmsk_742',['SYSCFG_CMPCR_READY_Msk',['../group___peripheral___registers___bits___definition.html#gaa4d9717bd2df4c0742d09a2db4caa1ea',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fcmpcr_5fready_5fpos_743',['SYSCFG_CMPCR_READY_Pos',['../group___peripheral___registers___bits___definition.html#ga7d5884039c7c13bdef0f45090f48e275',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr1_5fexti0_744',['SYSCFG_EXTICR1_EXTI0',['../group___peripheral___registers___bits___definition.html#ga75b70d07448c3037234bc2abb8e3d884',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr1_5fexti0_5fmsk_745',['SYSCFG_EXTICR1_EXTI0_Msk',['../group___peripheral___registers___bits___definition.html#ga7c2b219e4d77fac522233905dc0d8de8',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr1_5fexti0_5fpa_746',['SYSCFG_EXTICR1_EXTI0_PA',['../group___peripheral___registers___bits___definition.html#ga6de6aa8e32ae5cd07fd69e42e7226bd1',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr1_5fexti0_5fpb_747',['SYSCFG_EXTICR1_EXTI0_PB',['../group___peripheral___registers___bits___definition.html#gaf43c9ef6b61e39655cbe969967c79a69',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr1_5fexti0_5fpc_748',['SYSCFG_EXTICR1_EXTI0_PC',['../group___peripheral___registers___bits___definition.html#ga861a4d7b48ffd93997267baaad12fd51',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr1_5fexti0_5fpd_749',['SYSCFG_EXTICR1_EXTI0_PD',['../group___peripheral___registers___bits___definition.html#gaf6439042c8cd14f99fe3813cff47c0ee',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr1_5fexti0_5fpe_750',['SYSCFG_EXTICR1_EXTI0_PE',['../group___peripheral___registers___bits___definition.html#gacb087e2ded8ac927ee9e1fc0234bfdef',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr1_5fexti0_5fpf_751',['SYSCFG_EXTICR1_EXTI0_PF',['../group___peripheral___registers___bits___definition.html#gaa897f1ac8311e57339eaf7813239eaf4',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr1_5fexti0_5fpg_752',['SYSCFG_EXTICR1_EXTI0_PG',['../group___peripheral___registers___bits___definition.html#ga98b2d929e79e5cc2ee7961a75a0ab094',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr1_5fexti0_5fph_753',['SYSCFG_EXTICR1_EXTI0_PH',['../group___peripheral___registers___bits___definition.html#ga766d0bf3501e207b0baa066cf756688f',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr1_5fexti0_5fpi_754',['SYSCFG_EXTICR1_EXTI0_PI',['../group___peripheral___registers___bits___definition.html#gacfc4b69ff5f5d9b35bf01f26d6aa4e60',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr1_5fexti0_5fpos_755',['SYSCFG_EXTICR1_EXTI0_Pos',['../group___peripheral___registers___bits___definition.html#gae40db3f75cc81dcb1b6b8c18194d07a8',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr1_5fexti1_756',['SYSCFG_EXTICR1_EXTI1',['../group___peripheral___registers___bits___definition.html#ga7fc84838c77f799cb7e57d6e97c6c16d',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr1_5fexti1_5fmsk_757',['SYSCFG_EXTICR1_EXTI1_Msk',['../group___peripheral___registers___bits___definition.html#gac033e65cf79968349e0fa5e52ebf4ccd',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr1_5fexti1_5fpa_758',['SYSCFG_EXTICR1_EXTI1_PA',['../group___peripheral___registers___bits___definition.html#gaf4b78c30e4ef4fa441582eb3c102865d',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr1_5fexti1_5fpb_759',['SYSCFG_EXTICR1_EXTI1_PB',['../group___peripheral___registers___bits___definition.html#ga19a11fce288d19546c76257483e0dcb6',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr1_5fexti1_5fpc_760',['SYSCFG_EXTICR1_EXTI1_PC',['../group___peripheral___registers___bits___definition.html#gae45a8c814b13fa19f157364dc715c08a',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr1_5fexti1_5fpd_761',['SYSCFG_EXTICR1_EXTI1_PD',['../group___peripheral___registers___bits___definition.html#ga93cb136eaf357affc4a28a8d423cabbb',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr1_5fexti1_5fpe_762',['SYSCFG_EXTICR1_EXTI1_PE',['../group___peripheral___registers___bits___definition.html#ga8f5c3d1e914af78112179a13e9c736d6',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr1_5fexti1_5fpf_763',['SYSCFG_EXTICR1_EXTI1_PF',['../group___peripheral___registers___bits___definition.html#ga43ea410456aa31dfe6ec4889de62428b',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr1_5fexti1_5fpg_764',['SYSCFG_EXTICR1_EXTI1_PG',['../group___peripheral___registers___bits___definition.html#gaf9118efcafa89eeada012ff5ab98387d',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr1_5fexti1_5fph_765',['SYSCFG_EXTICR1_EXTI1_PH',['../group___peripheral___registers___bits___definition.html#ga0ac69d7f391e837d8e8adce27704d87d',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr1_5fexti1_5fpi_766',['SYSCFG_EXTICR1_EXTI1_PI',['../group___peripheral___registers___bits___definition.html#ga010784c7bdee3c742b48c500ee52e223',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr1_5fexti1_5fpos_767',['SYSCFG_EXTICR1_EXTI1_Pos',['../group___peripheral___registers___bits___definition.html#ga1e187825ececb74bc0dc9bb16a22e8af',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr1_5fexti2_768',['SYSCFG_EXTICR1_EXTI2',['../group___peripheral___registers___bits___definition.html#ga6d0a0a6b8223777937d8c9012658d6cd',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr1_5fexti2_5fmsk_769',['SYSCFG_EXTICR1_EXTI2_Msk',['../group___peripheral___registers___bits___definition.html#ga1383ce11441c048c62e317e78eff0545',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr1_5fexti2_5fpa_770',['SYSCFG_EXTICR1_EXTI2_PA',['../group___peripheral___registers___bits___definition.html#ga4096f472e87e021f4d4c94457ddaf5f1',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr1_5fexti2_5fpb_771',['SYSCFG_EXTICR1_EXTI2_PB',['../group___peripheral___registers___bits___definition.html#ga8cd240d61fd8a9666621f0dee07a08e5',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr1_5fexti2_5fpc_772',['SYSCFG_EXTICR1_EXTI2_PC',['../group___peripheral___registers___bits___definition.html#ga03ce7faaf56aa9efcc74af65619e275e',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr1_5fexti2_5fpd_773',['SYSCFG_EXTICR1_EXTI2_PD',['../group___peripheral___registers___bits___definition.html#gafc35fcdcc89b487fab2901e1f5a7f41b',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr1_5fexti2_5fpe_774',['SYSCFG_EXTICR1_EXTI2_PE',['../group___peripheral___registers___bits___definition.html#gac3f2b7465d81745f7a772e7689a29618',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr1_5fexti2_5fpf_775',['SYSCFG_EXTICR1_EXTI2_PF',['../group___peripheral___registers___bits___definition.html#gab538769f1da056b3f57fb984adeef252',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr1_5fexti2_5fpg_776',['SYSCFG_EXTICR1_EXTI2_PG',['../group___peripheral___registers___bits___definition.html#gabe4f5fa56e98b42b64e894f7a9216e05',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr1_5fexti2_5fph_777',['SYSCFG_EXTICR1_EXTI2_PH',['../group___peripheral___registers___bits___definition.html#gada5ffab92c39cbfc695ce57a4e6177e5',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr1_5fexti2_5fpi_778',['SYSCFG_EXTICR1_EXTI2_PI',['../group___peripheral___registers___bits___definition.html#ga00bc1224b7bfd46dcec32676a601de51',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr1_5fexti2_5fpos_779',['SYSCFG_EXTICR1_EXTI2_Pos',['../group___peripheral___registers___bits___definition.html#ga283584ecd69e2dfd310b2b09d1028457',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr1_5fexti3_780',['SYSCFG_EXTICR1_EXTI3',['../group___peripheral___registers___bits___definition.html#gac3bf2306f79ebb709da5ecf83e59ded4',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr1_5fexti3_5fmsk_781',['SYSCFG_EXTICR1_EXTI3_Msk',['../group___peripheral___registers___bits___definition.html#ga90072fd2defc44f0975836484c9d9bbf',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr1_5fexti3_5fpa_782',['SYSCFG_EXTICR1_EXTI3_PA',['../group___peripheral___registers___bits___definition.html#ga45ed24773c389f4477944c2c43d106c0',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr1_5fexti3_5fpb_783',['SYSCFG_EXTICR1_EXTI3_PB',['../group___peripheral___registers___bits___definition.html#ga652183838bb096717551bf8a1917c257',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr1_5fexti3_5fpc_784',['SYSCFG_EXTICR1_EXTI3_PC',['../group___peripheral___registers___bits___definition.html#gacb1809e5b8a9ebc4b1cbc8967d985929',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr1_5fexti3_5fpd_785',['SYSCFG_EXTICR1_EXTI3_PD',['../group___peripheral___registers___bits___definition.html#ga205440ffa174509d57c2b6a1814f8202',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr1_5fexti3_5fpe_786',['SYSCFG_EXTICR1_EXTI3_PE',['../group___peripheral___registers___bits___definition.html#gab2b33beb6294fd7a257f0f3a36e0dcda',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr1_5fexti3_5fpf_787',['SYSCFG_EXTICR1_EXTI3_PF',['../group___peripheral___registers___bits___definition.html#ga40240ee616b6e06ecd8dabe9d8e56e71',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr1_5fexti3_5fpg_788',['SYSCFG_EXTICR1_EXTI3_PG',['../group___peripheral___registers___bits___definition.html#gaaa73420dbafb7f20f16c350a12b0a0f5',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr1_5fexti3_5fph_789',['SYSCFG_EXTICR1_EXTI3_PH',['../group___peripheral___registers___bits___definition.html#gae49def2961bf528448a4fbb4aa9c9d94',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr1_5fexti3_5fpi_790',['SYSCFG_EXTICR1_EXTI3_PI',['../group___peripheral___registers___bits___definition.html#ga337e37f58e8710ea8305a16c08e390b9',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr1_5fexti3_5fpos_791',['SYSCFG_EXTICR1_EXTI3_Pos',['../group___peripheral___registers___bits___definition.html#ga08a505d92a83c5fc8d5d0c8202119f61',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr2_5fexti4_792',['SYSCFG_EXTICR2_EXTI4',['../group___peripheral___registers___bits___definition.html#gad2a57b4872977812e60d521268190e1e',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr2_5fexti4_5fmsk_793',['SYSCFG_EXTICR2_EXTI4_Msk',['../group___peripheral___registers___bits___definition.html#gaf05f6030b07cf7ca730a2ea8325e7640',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr2_5fexti4_5fpa_794',['SYSCFG_EXTICR2_EXTI4_PA',['../group___peripheral___registers___bits___definition.html#ga51147f1747daf48dbcfad03285ae8889',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr2_5fexti4_5fpb_795',['SYSCFG_EXTICR2_EXTI4_PB',['../group___peripheral___registers___bits___definition.html#ga917aeb0df688d6b34785085fc85d9e47',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr2_5fexti4_5fpc_796',['SYSCFG_EXTICR2_EXTI4_PC',['../group___peripheral___registers___bits___definition.html#ga14ac312beeb19d3bb34a552546477613',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr2_5fexti4_5fpd_797',['SYSCFG_EXTICR2_EXTI4_PD',['../group___peripheral___registers___bits___definition.html#gaec62164e18d1b525e8272169b1efe642',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr2_5fexti4_5fpe_798',['SYSCFG_EXTICR2_EXTI4_PE',['../group___peripheral___registers___bits___definition.html#gac1d2292b6a856a8a71d82f595b580b9b',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr2_5fexti4_5fpf_799',['SYSCFG_EXTICR2_EXTI4_PF',['../group___peripheral___registers___bits___definition.html#ga0adc3c72bddc65977e3ef56df74ed40e',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr2_5fexti4_5fpg_800',['SYSCFG_EXTICR2_EXTI4_PG',['../group___peripheral___registers___bits___definition.html#gad5aad8ed8589e28677332ea0b200617b',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr2_5fexti4_5fph_801',['SYSCFG_EXTICR2_EXTI4_PH',['../group___peripheral___registers___bits___definition.html#ga339f8994c317190a387a96b857aa79d0',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr2_5fexti4_5fpi_802',['SYSCFG_EXTICR2_EXTI4_PI',['../group___peripheral___registers___bits___definition.html#gaad36a509bf6deabd5446a07c20964f83',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr2_5fexti4_5fpos_803',['SYSCFG_EXTICR2_EXTI4_Pos',['../group___peripheral___registers___bits___definition.html#gae2d0b453a61771de5591f5eb58ccb174',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr2_5fexti5_804',['SYSCFG_EXTICR2_EXTI5',['../group___peripheral___registers___bits___definition.html#ga6682a1b97b04c5c33085ffd2827ccd17',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr2_5fexti5_5fmsk_805',['SYSCFG_EXTICR2_EXTI5_Msk',['../group___peripheral___registers___bits___definition.html#gaa47b595915b1cd571357a04f31c79656',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr2_5fexti5_5fpa_806',['SYSCFG_EXTICR2_EXTI5_PA',['../group___peripheral___registers___bits___definition.html#gafb9581c515a4bdf1ed88fe96d8c24794',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr2_5fexti5_5fpb_807',['SYSCFG_EXTICR2_EXTI5_PB',['../group___peripheral___registers___bits___definition.html#ga90a3f610234dfa13f56e72c76a12be74',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr2_5fexti5_5fpc_808',['SYSCFG_EXTICR2_EXTI5_PC',['../group___peripheral___registers___bits___definition.html#ga33b6bdc1b4bfeda0d4034dc67f1a6046',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr2_5fexti5_5fpd_809',['SYSCFG_EXTICR2_EXTI5_PD',['../group___peripheral___registers___bits___definition.html#ga0eea392f1530c7cb794a63d04e268a70',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr2_5fexti5_5fpe_810',['SYSCFG_EXTICR2_EXTI5_PE',['../group___peripheral___registers___bits___definition.html#ga8a4e6644d0144bfb0f913cf20eaf2f8e',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr2_5fexti5_5fpf_811',['SYSCFG_EXTICR2_EXTI5_PF',['../group___peripheral___registers___bits___definition.html#ga740e27c5bead2c914a134ac4ed4d05b3',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr2_5fexti5_5fpg_812',['SYSCFG_EXTICR2_EXTI5_PG',['../group___peripheral___registers___bits___definition.html#ga7d78839e577ab90090abcdcff88e18c8',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr2_5fexti5_5fph_813',['SYSCFG_EXTICR2_EXTI5_PH',['../group___peripheral___registers___bits___definition.html#ga4a06842a64138b5010186d980cb594f9',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr2_5fexti5_5fpi_814',['SYSCFG_EXTICR2_EXTI5_PI',['../group___peripheral___registers___bits___definition.html#ga4f3c4ebe4d750f89465acd067ab0ee30',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr2_5fexti5_5fpos_815',['SYSCFG_EXTICR2_EXTI5_Pos',['../group___peripheral___registers___bits___definition.html#gade15c38da4f70df1a360337abac37314',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr2_5fexti6_816',['SYSCFG_EXTICR2_EXTI6',['../group___peripheral___registers___bits___definition.html#ga6c50caf6019fd7d5038d77e61f57ad7b',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr2_5fexti6_5fmsk_817',['SYSCFG_EXTICR2_EXTI6_Msk',['../group___peripheral___registers___bits___definition.html#gaadbcd9e40a5da23a133cd3479d326c66',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr2_5fexti6_5fpa_818',['SYSCFG_EXTICR2_EXTI6_PA',['../group___peripheral___registers___bits___definition.html#ga3e87c78fb6dfde7c8b7f81fe3b65aae9',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr2_5fexti6_5fpb_819',['SYSCFG_EXTICR2_EXTI6_PB',['../group___peripheral___registers___bits___definition.html#ga6528de8e4ca8741e86ae254e1d6b2a70',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr2_5fexti6_5fpc_820',['SYSCFG_EXTICR2_EXTI6_PC',['../group___peripheral___registers___bits___definition.html#ga53d8745705d5eb84c70a8554f61d59ac',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr2_5fexti6_5fpd_821',['SYSCFG_EXTICR2_EXTI6_PD',['../group___peripheral___registers___bits___definition.html#ga26c97cdece451441e49120e754020cdc',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr2_5fexti6_5fpe_822',['SYSCFG_EXTICR2_EXTI6_PE',['../group___peripheral___registers___bits___definition.html#ga804218f2dd83c72e672143ec4f283ad3',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr2_5fexti6_5fpf_823',['SYSCFG_EXTICR2_EXTI6_PF',['../group___peripheral___registers___bits___definition.html#ga0d36de53e52c8a4c7991513fec326df6',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr2_5fexti6_5fpg_824',['SYSCFG_EXTICR2_EXTI6_PG',['../group___peripheral___registers___bits___definition.html#ga278997204184bfe7c951c1da327e6fb5',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr2_5fexti6_5fph_825',['SYSCFG_EXTICR2_EXTI6_PH',['../group___peripheral___registers___bits___definition.html#ga283486dccd660fbf830e8c44b0161a63',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr2_5fexti6_5fpi_826',['SYSCFG_EXTICR2_EXTI6_PI',['../group___peripheral___registers___bits___definition.html#ga4222e7d9ed672ea2de3a038c23f9566b',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr2_5fexti6_5fpos_827',['SYSCFG_EXTICR2_EXTI6_Pos',['../group___peripheral___registers___bits___definition.html#gab355e39e166c83c356999c3da7fd7893',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr2_5fexti7_828',['SYSCFG_EXTICR2_EXTI7',['../group___peripheral___registers___bits___definition.html#ga638ea3bb014752813d064d37b3388950',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr2_5fexti7_5fmsk_829',['SYSCFG_EXTICR2_EXTI7_Msk',['../group___peripheral___registers___bits___definition.html#ga97160d2262cb4ab1ae9098809391f52e',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr2_5fexti7_5fpa_830',['SYSCFG_EXTICR2_EXTI7_PA',['../group___peripheral___registers___bits___definition.html#ga2f1bfd3af524288b6ce54d7f9aef410a',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr2_5fexti7_5fpb_831',['SYSCFG_EXTICR2_EXTI7_PB',['../group___peripheral___registers___bits___definition.html#gab18d324986b18858f901febbcc2a57b7',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr2_5fexti7_5fpc_832',['SYSCFG_EXTICR2_EXTI7_PC',['../group___peripheral___registers___bits___definition.html#gae9f53618d9cf13af2b2ecf191da8595a',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr2_5fexti7_5fpd_833',['SYSCFG_EXTICR2_EXTI7_PD',['../group___peripheral___registers___bits___definition.html#gae38aa3b76227bb8e9d8cedc31c023f63',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr2_5fexti7_5fpe_834',['SYSCFG_EXTICR2_EXTI7_PE',['../group___peripheral___registers___bits___definition.html#ga90d097c1b5cbb62dc86327604907dcd4',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr2_5fexti7_5fpf_835',['SYSCFG_EXTICR2_EXTI7_PF',['../group___peripheral___registers___bits___definition.html#gaaf2c3a661be3569fffe11515e37de1e4',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr2_5fexti7_5fpg_836',['SYSCFG_EXTICR2_EXTI7_PG',['../group___peripheral___registers___bits___definition.html#ga987bc0488e57b14b0a98e4952df2b539',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr2_5fexti7_5fph_837',['SYSCFG_EXTICR2_EXTI7_PH',['../group___peripheral___registers___bits___definition.html#gab0ce56e15f4eb86a3e262deaa845cb99',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr2_5fexti7_5fpi_838',['SYSCFG_EXTICR2_EXTI7_PI',['../group___peripheral___registers___bits___definition.html#gae68ca6758cf36232dd5ac63afae97cbc',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr2_5fexti7_5fpos_839',['SYSCFG_EXTICR2_EXTI7_Pos',['../group___peripheral___registers___bits___definition.html#gaa503d2cda916e0b9d0f621317c3f1601',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr3_5fexti10_840',['SYSCFG_EXTICR3_EXTI10',['../group___peripheral___registers___bits___definition.html#ga8fc06b17c3b3d393b749bf9924a43a80',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr3_5fexti10_5fmsk_841',['SYSCFG_EXTICR3_EXTI10_Msk',['../group___peripheral___registers___bits___definition.html#ga1803c2719fb53533547496e02c8b07d4',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr3_5fexti10_5fpa_842',['SYSCFG_EXTICR3_EXTI10_PA',['../group___peripheral___registers___bits___definition.html#ga25acdbb9e916c440c41a060d861130ee',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr3_5fexti10_5fpb_843',['SYSCFG_EXTICR3_EXTI10_PB',['../group___peripheral___registers___bits___definition.html#gab8d9aec4349bf38a4a9753b267b7de7e',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr3_5fexti10_5fpc_844',['SYSCFG_EXTICR3_EXTI10_PC',['../group___peripheral___registers___bits___definition.html#ga62d2b81d49e30ab4fe96572be5da8484',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr3_5fexti10_5fpd_845',['SYSCFG_EXTICR3_EXTI10_PD',['../group___peripheral___registers___bits___definition.html#gaab3553c540cd836d465824939c2e3b79',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr3_5fexti10_5fpe_846',['SYSCFG_EXTICR3_EXTI10_PE',['../group___peripheral___registers___bits___definition.html#gabde568ef1c8f4bfaf18954e8ee0716a9',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr3_5fexti10_5fpf_847',['SYSCFG_EXTICR3_EXTI10_PF',['../group___peripheral___registers___bits___definition.html#ga09ed841a11367cda67c7a416ed6d9b99',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr3_5fexti10_5fpg_848',['SYSCFG_EXTICR3_EXTI10_PG',['../group___peripheral___registers___bits___definition.html#ga6dff840a6986b440e7633a3671ce57cc',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr3_5fexti10_5fph_849',['SYSCFG_EXTICR3_EXTI10_PH',['../group___peripheral___registers___bits___definition.html#ga791e7d2bd23ae969540e5509c6718255',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr3_5fexti10_5fpi_850',['SYSCFG_EXTICR3_EXTI10_PI',['../group___peripheral___registers___bits___definition.html#ga8bee76cf4bed88ff7b51145393b2cd19',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr3_5fexti10_5fpos_851',['SYSCFG_EXTICR3_EXTI10_Pos',['../group___peripheral___registers___bits___definition.html#ga8d6efb981e6435ae15643e438196ffba',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr3_5fexti11_852',['SYSCFG_EXTICR3_EXTI11',['../group___peripheral___registers___bits___definition.html#gaa66cc9a579696c8f5c41f5f138ee1e67',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr3_5fexti11_5fmsk_853',['SYSCFG_EXTICR3_EXTI11_Msk',['../group___peripheral___registers___bits___definition.html#ga4c7d37c95e30bf30ac80d455bfa9a842',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr3_5fexti11_5fpa_854',['SYSCFG_EXTICR3_EXTI11_PA',['../group___peripheral___registers___bits___definition.html#ga0ca8a85d4512677eff6ed2aac897a366',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr3_5fexti11_5fpb_855',['SYSCFG_EXTICR3_EXTI11_PB',['../group___peripheral___registers___bits___definition.html#gaedb3a8cc6b1763e303986553c0e4e7f8',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr3_5fexti11_5fpc_856',['SYSCFG_EXTICR3_EXTI11_PC',['../group___peripheral___registers___bits___definition.html#ga0b01c8ba6cb27899a4f5fa494bf2b3f5',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr3_5fexti11_5fpd_857',['SYSCFG_EXTICR3_EXTI11_PD',['../group___peripheral___registers___bits___definition.html#ga6a69d636cda0352da0982c54f582787d',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr3_5fexti11_5fpe_858',['SYSCFG_EXTICR3_EXTI11_PE',['../group___peripheral___registers___bits___definition.html#ga44affe06868a0490f8d0cbbba51ff412',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr3_5fexti11_5fpf_859',['SYSCFG_EXTICR3_EXTI11_PF',['../group___peripheral___registers___bits___definition.html#ga66fb050835077047b576b3a510700d64',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr3_5fexti11_5fpg_860',['SYSCFG_EXTICR3_EXTI11_PG',['../group___peripheral___registers___bits___definition.html#gaf7b66390eeb4a8d50ebb7e87e2f281b3',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr3_5fexti11_5fph_861',['SYSCFG_EXTICR3_EXTI11_PH',['../group___peripheral___registers___bits___definition.html#gaa58cfe5d03072c259582ba8fefa322bf',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr3_5fexti11_5fpi_862',['SYSCFG_EXTICR3_EXTI11_PI',['../group___peripheral___registers___bits___definition.html#gafadb14df8764208abeeaf6197489f1b4',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr3_5fexti11_5fpos_863',['SYSCFG_EXTICR3_EXTI11_Pos',['../group___peripheral___registers___bits___definition.html#ga29b9c2241040cf831bbb18391cda402c',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr3_5fexti8_864',['SYSCFG_EXTICR3_EXTI8',['../group___peripheral___registers___bits___definition.html#gaf2a656b18cc728e38acb72cf8d7e7935',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr3_5fexti8_5fmsk_865',['SYSCFG_EXTICR3_EXTI8_Msk',['../group___peripheral___registers___bits___definition.html#gab693b7e686ba5646959113dd6b408673',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr3_5fexti8_5fpa_866',['SYSCFG_EXTICR3_EXTI8_PA',['../group___peripheral___registers___bits___definition.html#gae1c6843a871f1a06ca25c0de50048b10',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr3_5fexti8_5fpb_867',['SYSCFG_EXTICR3_EXTI8_PB',['../group___peripheral___registers___bits___definition.html#ga4818dc7bffc8dfc2acc48995a62e66c5',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr3_5fexti8_5fpc_868',['SYSCFG_EXTICR3_EXTI8_PC',['../group___peripheral___registers___bits___definition.html#gaba0d34ff57632d7753981404cef548e2',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr3_5fexti8_5fpd_869',['SYSCFG_EXTICR3_EXTI8_PD',['../group___peripheral___registers___bits___definition.html#gaa15260ba354dee354f0a71e7913009c3',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr3_5fexti8_5fpe_870',['SYSCFG_EXTICR3_EXTI8_PE',['../group___peripheral___registers___bits___definition.html#ga185287204b8cead31d3760f65c5ca19d',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr3_5fexti8_5fpf_871',['SYSCFG_EXTICR3_EXTI8_PF',['../group___peripheral___registers___bits___definition.html#ga425e41001af4b205b8fbfba723572a81',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr3_5fexti8_5fpg_872',['SYSCFG_EXTICR3_EXTI8_PG',['../group___peripheral___registers___bits___definition.html#ga2ecc7a12103b805da045093eb626614d',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr3_5fexti8_5fph_873',['SYSCFG_EXTICR3_EXTI8_PH',['../group___peripheral___registers___bits___definition.html#ga0bf3fc7a2e35b7cbb9f08f2e3b06a3c4',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr3_5fexti8_5fpi_874',['SYSCFG_EXTICR3_EXTI8_PI',['../group___peripheral___registers___bits___definition.html#gaf0b679636c97041f5584012c78f6d7a3',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr3_5fexti8_5fpos_875',['SYSCFG_EXTICR3_EXTI8_Pos',['../group___peripheral___registers___bits___definition.html#ga0e1169e4f50e721a7c6b9d9c2b722035',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr3_5fexti9_876',['SYSCFG_EXTICR3_EXTI9',['../group___peripheral___registers___bits___definition.html#ga002462e4c233adc6dd502de726994575',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr3_5fexti9_5fmsk_877',['SYSCFG_EXTICR3_EXTI9_Msk',['../group___peripheral___registers___bits___definition.html#ga8ea1b3c5cb074a305ad06709a7023689',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr3_5fexti9_5fpa_878',['SYSCFG_EXTICR3_EXTI9_PA',['../group___peripheral___registers___bits___definition.html#ga93e284e59c4ff887b2e79851ac0a81c4',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr3_5fexti9_5fpb_879',['SYSCFG_EXTICR3_EXTI9_PB',['../group___peripheral___registers___bits___definition.html#gaa9271cbc1ed09774a5fef4b379cab260',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr3_5fexti9_5fpc_880',['SYSCFG_EXTICR3_EXTI9_PC',['../group___peripheral___registers___bits___definition.html#ga1cc355176941881870c620c0837cab48',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr3_5fexti9_5fpd_881',['SYSCFG_EXTICR3_EXTI9_PD',['../group___peripheral___registers___bits___definition.html#ga75af3c7a94cfc78361c94b054f9fe064',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr3_5fexti9_5fpe_882',['SYSCFG_EXTICR3_EXTI9_PE',['../group___peripheral___registers___bits___definition.html#gafce176ef4b389251dadb98d9f59f8fe6',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr3_5fexti9_5fpf_883',['SYSCFG_EXTICR3_EXTI9_PF',['../group___peripheral___registers___bits___definition.html#ga76ef2422b4d021d0cc038cb6325ed311',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr3_5fexti9_5fpg_884',['SYSCFG_EXTICR3_EXTI9_PG',['../group___peripheral___registers___bits___definition.html#gae1b37bf746ccfe0750aebd28cfa52a0c',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr3_5fexti9_5fph_885',['SYSCFG_EXTICR3_EXTI9_PH',['../group___peripheral___registers___bits___definition.html#ga31fdedc4a90328881fe8817f4eef61b2',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr3_5fexti9_5fpi_886',['SYSCFG_EXTICR3_EXTI9_PI',['../group___peripheral___registers___bits___definition.html#ga8cd8a0da1b9ede601094f6c651a499e4',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr3_5fexti9_5fpos_887',['SYSCFG_EXTICR3_EXTI9_Pos',['../group___peripheral___registers___bits___definition.html#ga6f6d994a483df2e705db0343cb88fb53',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr4_5fexti12_888',['SYSCFG_EXTICR4_EXTI12',['../group___peripheral___registers___bits___definition.html#ga9d4b31f4a75d935b6a52afe6a16463d1',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr4_5fexti12_5fmsk_889',['SYSCFG_EXTICR4_EXTI12_Msk',['../group___peripheral___registers___bits___definition.html#gaabcd55b42c6aa84cdd8c36d7df16fcf5',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr4_5fexti12_5fpa_890',['SYSCFG_EXTICR4_EXTI12_PA',['../group___peripheral___registers___bits___definition.html#ga3ceaa63866465faa8145ce0c5d9a44d0',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr4_5fexti12_5fpb_891',['SYSCFG_EXTICR4_EXTI12_PB',['../group___peripheral___registers___bits___definition.html#gad8b00a462533a83c75c588340a2fa710',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr4_5fexti12_5fpc_892',['SYSCFG_EXTICR4_EXTI12_PC',['../group___peripheral___registers___bits___definition.html#ga4d27668b1fa6b1accde06aa144faa970',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr4_5fexti12_5fpd_893',['SYSCFG_EXTICR4_EXTI12_PD',['../group___peripheral___registers___bits___definition.html#gaa46ddd43a361d82abcb3cb7779ac74ff',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr4_5fexti12_5fpe_894',['SYSCFG_EXTICR4_EXTI12_PE',['../group___peripheral___registers___bits___definition.html#ga102ee111e27fd67228c169836dd0849e',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr4_5fexti12_5fpf_895',['SYSCFG_EXTICR4_EXTI12_PF',['../group___peripheral___registers___bits___definition.html#gad9785209e7e13fcf9c4f82d57bae0837',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr4_5fexti12_5fpg_896',['SYSCFG_EXTICR4_EXTI12_PG',['../group___peripheral___registers___bits___definition.html#ga5c78af5f130089bec32d6f782288765c',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr4_5fexti12_5fph_897',['SYSCFG_EXTICR4_EXTI12_PH',['../group___peripheral___registers___bits___definition.html#ga0b7baa5b844b78d3e05326607b2910a6',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr4_5fexti12_5fpos_898',['SYSCFG_EXTICR4_EXTI12_Pos',['../group___peripheral___registers___bits___definition.html#ga81bcb273eca8dad24924a1402c31411e',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr4_5fexti13_899',['SYSCFG_EXTICR4_EXTI13',['../group___peripheral___registers___bits___definition.html#ga7f04cda5bfe876431d5ad864302d7fa1',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr4_5fexti13_5fmsk_900',['SYSCFG_EXTICR4_EXTI13_Msk',['../group___peripheral___registers___bits___definition.html#gafaf1614a726586aeefae87ca1d803656',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr4_5fexti13_5fpa_901',['SYSCFG_EXTICR4_EXTI13_PA',['../group___peripheral___registers___bits___definition.html#ga0514aaa894c9be44ba47c1346756f90b',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr4_5fexti13_5fpb_902',['SYSCFG_EXTICR4_EXTI13_PB',['../group___peripheral___registers___bits___definition.html#ga34e6776e3ebfecc9e78c5aec77c48eff',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr4_5fexti13_5fpc_903',['SYSCFG_EXTICR4_EXTI13_PC',['../group___peripheral___registers___bits___definition.html#ga1c7833d4e3c6b7f3878f62a200a6ab14',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr4_5fexti13_5fpd_904',['SYSCFG_EXTICR4_EXTI13_PD',['../group___peripheral___registers___bits___definition.html#gabed530f628b3c37281f7a583af1cdb3c',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr4_5fexti13_5fpe_905',['SYSCFG_EXTICR4_EXTI13_PE',['../group___peripheral___registers___bits___definition.html#ga7dc5424bf39509a989464a81ec0714da',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr4_5fexti13_5fpf_906',['SYSCFG_EXTICR4_EXTI13_PF',['../group___peripheral___registers___bits___definition.html#gaaf4c995587d7bae6436e6793b8214627',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr4_5fexti13_5fpg_907',['SYSCFG_EXTICR4_EXTI13_PG',['../group___peripheral___registers___bits___definition.html#ga4dedb6adbf49c40e5a15ad2afc471155',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr4_5fexti13_5fph_908',['SYSCFG_EXTICR4_EXTI13_PH',['../group___peripheral___registers___bits___definition.html#ga61214ec3d87450f54b959aab49ea65b6',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr4_5fexti13_5fpos_909',['SYSCFG_EXTICR4_EXTI13_Pos',['../group___peripheral___registers___bits___definition.html#ga09cc7a3ec956c6849e56f0deb4bf94cc',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr4_5fexti14_910',['SYSCFG_EXTICR4_EXTI14',['../group___peripheral___registers___bits___definition.html#gabde06df3ec6e357374820a5a615991aa',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr4_5fexti14_5fmsk_911',['SYSCFG_EXTICR4_EXTI14_Msk',['../group___peripheral___registers___bits___definition.html#ga95bb6740c8bc08eb716e3ef71841e81a',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr4_5fexti14_5fpa_912',['SYSCFG_EXTICR4_EXTI14_PA',['../group___peripheral___registers___bits___definition.html#ga7ad140a68e3e4e0406a182a504679ea9',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr4_5fexti14_5fpb_913',['SYSCFG_EXTICR4_EXTI14_PB',['../group___peripheral___registers___bits___definition.html#gae5c1b8a0f2b4f79bd868bbb2b4eff617',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr4_5fexti14_5fpc_914',['SYSCFG_EXTICR4_EXTI14_PC',['../group___peripheral___registers___bits___definition.html#ga8ca668cdd447acb1740566f46de5eb19',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr4_5fexti14_5fpd_915',['SYSCFG_EXTICR4_EXTI14_PD',['../group___peripheral___registers___bits___definition.html#ga2f20b2bfa9dc8b57a987c127c6dfa6fe',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr4_5fexti14_5fpe_916',['SYSCFG_EXTICR4_EXTI14_PE',['../group___peripheral___registers___bits___definition.html#ga4c13c49f6d93865ba05361cd86fddabf',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr4_5fexti14_5fpf_917',['SYSCFG_EXTICR4_EXTI14_PF',['../group___peripheral___registers___bits___definition.html#ga9df1ee6f60db93301acaa9220a591da9',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr4_5fexti14_5fpg_918',['SYSCFG_EXTICR4_EXTI14_PG',['../group___peripheral___registers___bits___definition.html#gae8ae4d091bb2c7148188ef430734020a',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr4_5fexti14_5fph_919',['SYSCFG_EXTICR4_EXTI14_PH',['../group___peripheral___registers___bits___definition.html#ga07b38f38fa3957c6bc45ef4282b58377',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr4_5fexti14_5fpos_920',['SYSCFG_EXTICR4_EXTI14_Pos',['../group___peripheral___registers___bits___definition.html#ga525a67279d0e7f222fd770de959a96d5',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr4_5fexti15_921',['SYSCFG_EXTICR4_EXTI15',['../group___peripheral___registers___bits___definition.html#gabd325c27cff1ae3de773d5e205a33f4e',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr4_5fexti15_5fmsk_922',['SYSCFG_EXTICR4_EXTI15_Msk',['../group___peripheral___registers___bits___definition.html#ga08ef44dcc2fb1d5cb2fab3ca7eb1a45a',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr4_5fexti15_5fpa_923',['SYSCFG_EXTICR4_EXTI15_PA',['../group___peripheral___registers___bits___definition.html#gae2f28920677dd99f9132ed28f7b1d5e2',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr4_5fexti15_5fpb_924',['SYSCFG_EXTICR4_EXTI15_PB',['../group___peripheral___registers___bits___definition.html#ga412f44d6a8f8f60420d7e7f8b5635e09',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr4_5fexti15_5fpc_925',['SYSCFG_EXTICR4_EXTI15_PC',['../group___peripheral___registers___bits___definition.html#ga49778592caef3a176ee82c9b83e25148',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr4_5fexti15_5fpd_926',['SYSCFG_EXTICR4_EXTI15_PD',['../group___peripheral___registers___bits___definition.html#gac23e07d92a68cf7f8c3e58b479638885',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr4_5fexti15_5fpe_927',['SYSCFG_EXTICR4_EXTI15_PE',['../group___peripheral___registers___bits___definition.html#gaefd64bc0ea005d03068f2e9b8f425944',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr4_5fexti15_5fpf_928',['SYSCFG_EXTICR4_EXTI15_PF',['../group___peripheral___registers___bits___definition.html#ga5e88d51ebabe9f70e5b7c2ad60899d54',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr4_5fexti15_5fpg_929',['SYSCFG_EXTICR4_EXTI15_PG',['../group___peripheral___registers___bits___definition.html#ga51d341c45e98ccbd82bf7003bfa56e6b',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr4_5fexti15_5fph_930',['SYSCFG_EXTICR4_EXTI15_PH',['../group___peripheral___registers___bits___definition.html#ga701c1065ec215a34329017bae69046c3',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fexticr4_5fexti15_5fpos_931',['SYSCFG_EXTICR4_EXTI15_Pos',['../group___peripheral___registers___bits___definition.html#gaa2d829ebf74fc207970f57a960bd8b4a',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fmemrmp_5fmem_5fmode_932',['SYSCFG_MEMRMP_MEM_MODE',['../group___peripheral___registers___bits___definition.html#ga3c05039ec67573c00da29f58b914f258',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fmemrmp_5fmem_5fmode_5f0_933',['SYSCFG_MEMRMP_MEM_MODE_0',['../group___peripheral___registers___bits___definition.html#ga30d5f406535f94faea2e7f924d50201b',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fmemrmp_5fmem_5fmode_5f1_934',['SYSCFG_MEMRMP_MEM_MODE_1',['../group___peripheral___registers___bits___definition.html#gab5d76e8b4d801b35c31ef352b33407be',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fmemrmp_5fmem_5fmode_5fmsk_935',['SYSCFG_MEMRMP_MEM_MODE_Msk',['../group___peripheral___registers___bits___definition.html#ga1309dcedba4fee11e085cdfaf974cc3d',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fmemrmp_5fmem_5fmode_5fpos_936',['SYSCFG_MEMRMP_MEM_MODE_Pos',['../group___peripheral___registers___bits___definition.html#ga20a445ef41a942b3ec617cfce8297931',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fpmc_5fmii_5frmii_937',['SYSCFG_PMC_MII_RMII',['../group___peripheral___registers___bits___definition.html#gaaf7af9191fbf95433bc0a76454118ce9',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fpmc_5fmii_5frmii_5fsel_938',['SYSCFG_PMC_MII_RMII_SEL',['../group___peripheral___registers___bits___definition.html#gae9d8ca35cdab213cb2400c49434de326',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fpmc_5fmii_5frmii_5fsel_5fmsk_939',['SYSCFG_PMC_MII_RMII_SEL_Msk',['../group___peripheral___registers___bits___definition.html#gaf63c23642e3d3c0f1a2c67f6a60957e1',1,'stm32f407xx_matlab.h']]], - ['syscfg_5fpmc_5fmii_5frmii_5fsel_5fpos_940',['SYSCFG_PMC_MII_RMII_SEL_Pos',['../group___peripheral___registers___bits___definition.html#ga1f2f7440818b83b95e29d526516e8d27',1,'stm32f407xx_matlab.h']]], - ['syscfg_5ftypedef_941',['SYSCFG_TypeDef',['../struct_s_y_s_c_f_g___type_def.html',1,'']]], - ['system_20control_20block_20scb_942',['System Control Block (SCB)',['../group___c_m_s_i_s___s_c_b.html',1,'']]], - ['system_20controls_20not_20in_20scb_20scnscb_943',['System Controls not in SCB (SCnSCB)',['../group___c_m_s_i_s___s_cn_s_c_b.html',1,'']]], - ['system_20tick_20timer_20systick_944',['System Tick Timer (SysTick)',['../group___c_m_s_i_s___sys_tick.html',1,'']]], - ['system_5fstm32f4xx_2eh_945',['system_stm32f4xx.h',['../system__stm32f4xx_8h.html',1,'']]], - ['systemclock_946',['SystemClock',['../mcu__wrapper_8c.html#a6a1676e08289f73141f9fa8419311385',1,'mcu_wrapper.c']]], - ['systemclock_5fstep_947',['SystemClock_step',['../mcu__wrapper_8c.html#ae50392991204ce9a89dd9aa8bf43634f',1,'mcu_wrapper.c']]], - ['systemclockdouble_948',['SystemClockDouble',['../mcu__wrapper_8c.html#af1cb3ba542e380d1f12d30579598c48c',1,'mcu_wrapper.c']]], - ['systemcoreclock_949',['SystemCoreClock',['../group___s_t_m32_f4xx___system___exported__types.html#gaa3cd3e43291e81e795d642b79b6088e6',1,'system_stm32f4xx.h']]], - ['systemcoreclockupdate_950',['SystemCoreClockUpdate',['../group___s_t_m32_f4xx___system___exported___functions.html#gae0c36a9591fe6e9c45ecb21a794f0f0f',1,'system_stm32f4xx.h']]], - ['systeminit_951',['SystemInit',['../group___s_t_m32_f4xx___system___exported___functions.html#ga93f514700ccf00d08dbdcff7f1224eb2',1,'system_stm32f4xx.h']]], - ['systick_952',['SysTick',['../group___c_m_s_i_s___sys_tick.html',1,'System Tick Timer (SysTick)'],['../group___c_m_s_i_s__core__base.html#gacd96c53beeaff8f603fcda425eb295de',1,'SysTick: core_cm4_matlab.h']]], - ['systick_20functions_953',['SysTick Functions',['../group___c_m_s_i_s___core___sys_tick_functions.html',1,'']]], - ['systick_5fbase_954',['SysTick_BASE',['../group___c_m_s_i_s__core__base.html#ga58effaac0b93006b756d33209e814646',1,'core_cm4_matlab.h']]], - ['systick_5fcalib_5fnoref_5fmsk_955',['SysTick_CALIB_NOREF_Msk',['../group___c_m_s_i_s___sys_tick.html#ga3af0d891fdd99bcc8d8912d37830edb6',1,'core_cm4_matlab.h']]], - ['systick_5fcalib_5fnoref_5fpos_956',['SysTick_CALIB_NOREF_Pos',['../group___c_m_s_i_s___sys_tick.html#ga534dbe414e7a46a6ce4c1eca1fbff409',1,'core_cm4_matlab.h']]], - ['systick_5fcalib_5fskew_5fmsk_957',['SysTick_CALIB_SKEW_Msk',['../group___c_m_s_i_s___sys_tick.html#ga8a6a85a87334776f33d77fd147587431',1,'core_cm4_matlab.h']]], - ['systick_5fcalib_5fskew_5fpos_958',['SysTick_CALIB_SKEW_Pos',['../group___c_m_s_i_s___sys_tick.html#gadd0c9cd6641b9f6a0c618e7982954860',1,'core_cm4_matlab.h']]], - ['systick_5fcalib_5ftenms_5fmsk_959',['SysTick_CALIB_TENMS_Msk',['../group___c_m_s_i_s___sys_tick.html#gaf1e68865c5aece2ad58971225bd3e95e',1,'core_cm4_matlab.h']]], - ['systick_5fcalib_5ftenms_5fpos_960',['SysTick_CALIB_TENMS_Pos',['../group___c_m_s_i_s___sys_tick.html#gacae558f6e75a0bed5d826f606d8e695e',1,'core_cm4_matlab.h']]], - ['systick_5fctrl_5fclksource_5fmsk_961',['SysTick_CTRL_CLKSOURCE_Msk',['../group___c_m_s_i_s___sys_tick.html#gaa41d06039797423a46596bd313d57373',1,'core_cm4_matlab.h']]], - ['systick_5fctrl_5fclksource_5fpos_962',['SysTick_CTRL_CLKSOURCE_Pos',['../group___c_m_s_i_s___sys_tick.html#ga24fbc69a5f0b78d67fda2300257baff1',1,'core_cm4_matlab.h']]], - ['systick_5fctrl_5fcountflag_5fmsk_963',['SysTick_CTRL_COUNTFLAG_Msk',['../group___c_m_s_i_s___sys_tick.html#ga1bf3033ecccf200f59baefe15dbb367c',1,'core_cm4_matlab.h']]], - ['systick_5fctrl_5fcountflag_5fpos_964',['SysTick_CTRL_COUNTFLAG_Pos',['../group___c_m_s_i_s___sys_tick.html#gadbb65d4a815759649db41df216ed4d60',1,'core_cm4_matlab.h']]], - ['systick_5fctrl_5fenable_5fmsk_965',['SysTick_CTRL_ENABLE_Msk',['../group___c_m_s_i_s___sys_tick.html#ga16c9fee0ed0235524bdeb38af328fd1f',1,'core_cm4_matlab.h']]], - ['systick_5fctrl_5fenable_5fpos_966',['SysTick_CTRL_ENABLE_Pos',['../group___c_m_s_i_s___sys_tick.html#ga0b48cc1e36d92a92e4bf632890314810',1,'core_cm4_matlab.h']]], - ['systick_5fctrl_5ftickint_5fmsk_967',['SysTick_CTRL_TICKINT_Msk',['../group___c_m_s_i_s___sys_tick.html#ga95bb984266ca764024836a870238a027',1,'core_cm4_matlab.h']]], - ['systick_5fctrl_5ftickint_5fpos_968',['SysTick_CTRL_TICKINT_Pos',['../group___c_m_s_i_s___sys_tick.html#ga88f45bbb89ce8df3cd2b2613c7b48214',1,'core_cm4_matlab.h']]], - ['systick_5firqn_969',['SysTick_IRQn',['../group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a6dbff8f8543325f3474cbae2446776e7',1,'stm32f407xx_matlab.h']]], - ['systick_5fload_5freload_5fmsk_970',['SysTick_LOAD_RELOAD_Msk',['../group___c_m_s_i_s___sys_tick.html#ga265912a7962f0e1abd170336e579b1b1',1,'core_cm4_matlab.h']]], - ['systick_5fload_5freload_5fpos_971',['SysTick_LOAD_RELOAD_Pos',['../group___c_m_s_i_s___sys_tick.html#gaf44d10df359dc5bf5752b0894ae3bad2',1,'core_cm4_matlab.h']]], - ['systick_5ftype_972',['SysTick_Type',['../struct_sys_tick___type.html',1,'']]], - ['systick_5fval_5fcurrent_5fmsk_973',['SysTick_VAL_CURRENT_Msk',['../group___c_m_s_i_s___sys_tick.html#gafc77b56d568930b49a2474debc75ab45',1,'core_cm4_matlab.h']]], - ['systick_5fval_5fcurrent_5fpos_974',['SysTick_VAL_CURRENT_Pos',['../group___c_m_s_i_s___sys_tick.html#ga3208104c3b019b5de35ae8c21d5c34dd',1,'core_cm4_matlab.h']]] + ['while_0',['while',['../group___m_c_u___w_r_a_p_p_e_r.html#ga866c2dad3e54488a018e859b3dc6feba',1,'mcu_wrapper_conf.h']]], + ['wrapper_1',['MCU Wrapper',['../group___m_c_u___w_r_a_p_p_e_r.html',1,'']]], + ['wrapper_20configuration_2',['Wrapper Configuration',['../group___w_r_a_p_p_e_r___c_o_n_f.html',1,'']]], + ['write_5foc_5fto_5fgpio_3',['Write_OC_to_GPIO',['../group___t_i_m___s_i_m_u_l_a_t_o_r.html#ga28ab1124ab4cfbd21acb613cb0873d2d',1,'Write_OC_to_GPIO(TIM_TypeDef *TIMx, struct TIM_Sim *TIMS): stm32f4xx_matlab_tim.c'],['../group___t_i_m___s_i_m_u_l_a_t_o_r.html#ga28ab1124ab4cfbd21acb613cb0873d2d',1,'Write_OC_to_GPIO(TIM_TypeDef *TIMx, struct TIM_Sim *TIMS): stm32f4xx_matlab_tim.c']]], + ['write_5foc_5fto_5ftrgo_4',['Write_OC_to_TRGO',['../group___t_i_m___s_i_m_u_l_a_t_o_r.html#ga4ac3f9a63d2433519bd5137bab286080',1,'Write_OC_to_TRGO(TIM_TypeDef *TIMx, struct TIM_Sim *TIMS): stm32f4xx_matlab_tim.c'],['../group___t_i_m___s_i_m_u_l_a_t_o_r.html#ga4ac3f9a63d2433519bd5137bab286080',1,'Write_OC_to_TRGO(TIM_TypeDef *TIMx, struct TIM_Sim *TIMS): stm32f4xx_matlab_tim.c']]], + ['wwdg_5',['wwdg',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga8702a9a8de59f4e7f66b061c980a1c23',1,'stm32f4xx_periph_registers.c']]] ]; diff --git a/DOCS/html/search/all_14.js b/DOCS/html/search/all_14.js index 47dc998..111cc88 100644 --- a/DOCS/html/search/all_14.js +++ b/DOCS/html/search/all_14.js @@ -1,664 +1,5 @@ var searchData= [ - ['t_0',['T',['../group___c_m_s_i_s__core___debug_functions.html#ga6e1cf12e53a20224f6f62c001d9be972',1,'xPSR_Type::T'],['../group___c_m_s_i_s__core___debug_functions.html#ga6e1cf12e53a20224f6f62c001d9be972',1,'xPSR_Type::@2::T']]], - ['tafcr_1',['TAFCR',['../group___c_m_s_i_s___device.html#ga14d03244a7fda1d94b51ae9ed144ca12',1,'RTC_TypeDef']]], - ['tamp_5fstamp_5firqn_2',['TAMP_STAMP_IRQn',['../group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8ac127cca7ae48bcf93924209f04e5e5a1',1,'stm32f407xx_matlab.h']]], - ['tcr_3',['TCR',['../group___c_m_s_i_s__core___debug_functions.html#ga4111c001c1e56fd3f51d27c5a63b04e6',1,'ITM_Type']]], - ['tdhr_4',['TDHR',['../group___c_m_s_i_s___device.html#ga90f7c1cf22683459c632d6040366eddf',1,'CAN_TxMailBox_TypeDef']]], - ['tdlr_5',['TDLR',['../group___c_m_s_i_s___device.html#gaded1359e1a32512910bff534d57ade68',1,'CAN_TxMailBox_TypeDef']]], - ['tdtr_6',['TDTR',['../group___c_m_s_i_s___device.html#gaed87bed042dd9523ce086119a3bab0ea',1,'CAN_TxMailBox_TypeDef']]], - ['ter_7',['TER',['../group___c_m_s_i_s__core___debug_functions.html#gaa6530efad3a727fb3cc8f509403b9948',1,'ITM_Type']]], - ['tick_20timer_20systick_8',['System Tick Timer (SysTick)',['../group___c_m_s_i_s___sys_tick.html',1,'']]], - ['tim1_9',['tim1',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#gaedba2af9d3a451898c4116468f63e31c',1,'stm32f4xx_periph_registers.c']]], - ['tim1_10',['TIM1',['../group___peripheral__declaration.html#ga2e87451fea8dc9380056d3cfc5ed81fb',1,'stm32f407xx_matlab.h']]], - ['tim10_11',['tim10',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga5fc888fc63ae5329a954de3db43caefd',1,'stm32f4xx_periph_registers.c']]], - ['tim10_12',['TIM10',['../group___peripheral__declaration.html#ga46b2ad3f5f506f0f8df0d2ec3e767267',1,'stm32f407xx_matlab.h']]], - ['tim10_5fbase_13',['TIM10_BASE',['../group___peripheral__memory__map.html#ga3eff32f3801db31fb4b61d5618cad54a',1,'stm32f407xx_matlab.h']]], - ['tim11_14',['tim11',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga720638f02cb775a2bdd6b866847b106f',1,'stm32f4xx_periph_registers.c']]], - ['tim11_15',['TIM11',['../group___peripheral__declaration.html#gacfd11ef966c7165f57e2cebe0abc71ad',1,'stm32f407xx_matlab.h']]], - ['tim11_5fbase_16',['TIM11_BASE',['../group___peripheral__memory__map.html#ga3a4a06bb84c703084f0509e105ffaf1d',1,'stm32f407xx_matlab.h']]], - ['tim12_17',['TIM12',['../group___peripheral__declaration.html#ga2397f8a0f8e7aa10cf8e8c049e431e53',1,'stm32f407xx_matlab.h']]], - ['tim12_18',['tim12',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#gaf7e88c4f7e226298777e23ce86e0f68e',1,'stm32f4xx_periph_registers.c']]], - ['tim12_5fbase_19',['TIM12_BASE',['../group___peripheral__memory__map.html#ga33dea32fadbaecea161c2ef7927992fd',1,'stm32f407xx_matlab.h']]], - ['tim12s_20',['tim12s',['../group___m_a_i_n___s_i_m_u_l_a_t_o_r.html#gad582b36106c35060b40bddfca929350e',1,'stm32f4xx_matlab_conf.h']]], - ['tim13_21',['tim13',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga5b7e61840360c6a797a1d137d1937c91',1,'stm32f4xx_periph_registers.c']]], - ['tim13_22',['TIM13',['../group___peripheral__declaration.html#ga5a959a833074d59bf6cc7fb437c65b18',1,'stm32f407xx_matlab.h']]], - ['tim13_5fbase_23',['TIM13_BASE',['../group___peripheral__memory__map.html#gad20f79948e9359125a40bbf6ed063590',1,'stm32f407xx_matlab.h']]], - ['tim14_24',['tim14',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga8ade2aee59ea8e56c5b2b9fdd81e4480',1,'stm32f4xx_periph_registers.c']]], - ['tim14_25',['TIM14',['../group___peripheral__declaration.html#ga2dd30f46fad69dd73e1d8941a43daffe',1,'stm32f407xx_matlab.h']]], - ['tim14_5fbase_26',['TIM14_BASE',['../group___peripheral__memory__map.html#ga862855347d6e1d92730dfe17ee8e90b8',1,'stm32f407xx_matlab.h']]], - ['tim1_5fbase_27',['TIM1_BASE',['../group___peripheral__memory__map.html#gaf8aa324ca5011b8173ab16585ed7324a',1,'stm32f407xx_matlab.h']]], - ['tim1_5fbrk_5ftim9_5firqhandler_28',['TIM1_BRK_TIM9_IRQHandler',['../stm32f4xx__matlab__tim_8c.html#a3b60f6118cdd3449f4ed29fde4704236',1,'stm32f4xx_matlab_tim.c']]], - ['tim1_5fbrk_5ftim9_5firqn_29',['TIM1_BRK_TIM9_IRQn',['../group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8ab35b4ce63cfb11453f84a3695c6df368',1,'stm32f407xx_matlab.h']]], - ['tim1_5fcc_5firqn_30',['TIM1_CC_IRQn',['../group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8af312f0a21f600f9b286427e50c549ca9',1,'stm32f407xx_matlab.h']]], - ['tim1_5ftrg_5fcom_5ftim11_5firqhandler_31',['TIM1_TRG_COM_TIM11_IRQHandler',['../stm32f4xx__matlab__tim_8c.html#a098245bf4e2f8844b22692b034a266fb',1,'stm32f4xx_matlab_tim.c']]], - ['tim1_5ftrg_5fcom_5ftim11_5firqn_32',['TIM1_TRG_COM_TIM11_IRQn',['../group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8ab1a744bdceb8eface6ff57dd036e608e',1,'stm32f407xx_matlab.h']]], - ['tim1_5ftrgo_33',['TIM1_TRGO',['../struct_slave_channels.html#a1bb1d8089ac5eff5af1df34649b50a94',1,'SlaveChannels']]], - ['tim1_5fup_5ftim10_5firqhandler_34',['TIM1_UP_TIM10_IRQHandler',['../stm32f4xx__matlab__tim_8c.html#ad1fd361bc5ad89facee67c76d1ff8dc0',1,'stm32f4xx_matlab_tim.c']]], - ['tim1_5fup_5ftim10_5firqn_35',['TIM1_UP_TIM10_IRQn',['../group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8aa3879e49013035601e17f83a51e0829f',1,'stm32f407xx_matlab.h']]], - ['tim1s_36',['tim1s',['../group___m_a_i_n___s_i_m_u_l_a_t_o_r.html#gab3aec69c8e446c577e391796728e4742',1,'stm32f4xx_matlab_conf.h']]], - ['tim2_37',['tim2',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#gaced1e82df483246f3faed614153db985',1,'stm32f4xx_periph_registers.c']]], - ['tim2_38',['TIM2',['../group___peripheral__declaration.html#ga3cfac9f2e43673f790f8668d48b4b92b',1,'stm32f407xx_matlab.h']]], - ['tim2_5fbase_39',['TIM2_BASE',['../group___peripheral__memory__map.html#ga00d0fe6ad532ab32f0f81cafca8d3aa5',1,'stm32f407xx_matlab.h']]], - ['tim2_5firqhandler_40',['TIM2_IRQHandler',['../stm32f4xx__matlab__tim_8c.html#a38ad4725462bdc5e86c4ead4f04b9fc2',1,'stm32f4xx_matlab_tim.c']]], - ['tim2_5firqn_41',['TIM2_IRQn',['../group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a3a4e2095a926e4095d3c846eb1c98afa',1,'stm32f407xx_matlab.h']]], - ['tim2_5ftrgo_42',['TIM2_TRGO',['../struct_slave_channels.html#a7b0ea9ba4357a49b11b9c1ef79252613',1,'SlaveChannels']]], - ['tim3_43',['TIM3',['../group___peripheral__declaration.html#ga61ee4c391385607d7af432b63905fcc9',1,'stm32f407xx_matlab.h']]], - ['tim3_44',['tim3',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga8a9462732233ea58ea84b420b20866ee',1,'stm32f4xx_periph_registers.c']]], - ['tim3_5fbase_45',['TIM3_BASE',['../group___peripheral__memory__map.html#gaf0c34a518f87e1e505cd2332e989564a',1,'stm32f407xx_matlab.h']]], - ['tim3_5firqhandler_46',['TIM3_IRQHandler',['../stm32f4xx__matlab__tim_8c.html#ac8e51d2183b5230cbd5481f8867adce9',1,'stm32f4xx_matlab_tim.c']]], - ['tim3_5firqn_47',['TIM3_IRQn',['../group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a985574288f66e2a00e97387424a9a2d8',1,'stm32f407xx_matlab.h']]], - ['tim3_5ftrgo_48',['TIM3_TRGO',['../struct_slave_channels.html#aab5be57f956df4be03effc282a0479e5',1,'SlaveChannels']]], - ['tim3s_49',['tim3s',['../group___m_a_i_n___s_i_m_u_l_a_t_o_r.html#gaefb416b7445ce7c77f15d96cd54cd2f5',1,'stm32f4xx_matlab_conf.h']]], - ['tim4_50',['TIM4',['../group___peripheral__declaration.html#ga91a09bad8bdc7a1cb3d85cf49c94c8ec',1,'stm32f407xx_matlab.h']]], - ['tim4_51',['tim4',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#gab15912b4a5af74002ab2c14632e0c538',1,'stm32f4xx_periph_registers.c']]], - ['tim4_5fbase_52',['TIM4_BASE',['../group___peripheral__memory__map.html#ga56e2d44b0002f316527b8913866a370d',1,'stm32f407xx_matlab.h']]], - ['tim4_5firqhandler_53',['TIM4_IRQHandler',['../stm32f4xx__matlab__tim_8c.html#a7133f3f78767503641d307386e68bd28',1,'stm32f4xx_matlab_tim.c']]], - ['tim4_5firqn_54',['TIM4_IRQn',['../group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a368b899ca740b9ae0d75841f3abf68c4',1,'stm32f407xx_matlab.h']]], - ['tim4_5ftrgo_55',['TIM4_TRGO',['../struct_slave_channels.html#ab9bff03506a4f82f55b13a1065bccaa6',1,'SlaveChannels']]], - ['tim4s_56',['tim4s',['../group___m_a_i_n___s_i_m_u_l_a_t_o_r.html#gab42529334dbaea26f59721c40f7a7782',1,'stm32f4xx_matlab_conf.h']]], - ['tim5_57',['TIM5',['../group___peripheral__declaration.html#ga5125ff6a23a2ed66e2e19bd196128c14',1,'stm32f407xx_matlab.h']]], - ['tim5_58',['tim5',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga7f9bc8648d83bd2b1959b43b1f11b70e',1,'stm32f4xx_periph_registers.c']]], - ['tim5_5fbase_59',['TIM5_BASE',['../group___peripheral__memory__map.html#ga3e1671477190d065ba7c944558336d7e',1,'stm32f407xx_matlab.h']]], - ['tim5_5firqhandler_60',['TIM5_IRQHandler',['../stm32f4xx__matlab__tim_8c.html#a5e66446caf21dd90191dc07a13ce2378',1,'stm32f4xx_matlab_tim.c']]], - ['tim5_5firqn_61',['TIM5_IRQn',['../group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8aed2eb3f4bb721d55fcc1003125956645',1,'stm32f407xx_matlab.h']]], - ['tim5_5ftrgo_62',['TIM5_TRGO',['../struct_slave_channels.html#a9780a406b85390dddcc18d4c6e606462',1,'SlaveChannels']]], - ['tim6_63',['tim6',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#gac7a5702d9b22c89aa44e3f5161cd8c9d',1,'stm32f4xx_periph_registers.c']]], - ['tim6_64',['TIM6',['../group___peripheral__declaration.html#gac7b4ed55f9201b498b38c962cca97314',1,'stm32f407xx_matlab.h']]], - ['tim6_5fbase_65',['TIM6_BASE',['../group___peripheral__memory__map.html#ga8268ec947929f192559f28c6bf7d1eac',1,'stm32f407xx_matlab.h']]], - ['tim6_5fdac_5firqhandler_66',['TIM6_DAC_IRQHandler',['../stm32f4xx__matlab__tim_8c.html#a0839a45f331c4c067939b9c4533bbf4d',1,'stm32f4xx_matlab_tim.c']]], - ['tim6_5fdac_5firqn_67',['TIM6_DAC_IRQn',['../group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a5f581e9aedfaccd9b1db9ec793804b45',1,'stm32f407xx_matlab.h']]], - ['tim6_5ftrgo_68',['TIM6_TRGO',['../struct_slave_channels.html#a2b1207a49068c13e3257396b4f369932',1,'SlaveChannels']]], - ['tim7_69',['TIM7',['../group___peripheral__declaration.html#ga49267c49946fd61db6af8b49bcf16394',1,'stm32f407xx_matlab.h']]], - ['tim7_70',['tim7',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#gad32365c7344044f1d4b358b16faf768b',1,'stm32f4xx_periph_registers.c']]], - ['tim7_5fbase_71',['TIM7_BASE',['../group___peripheral__memory__map.html#ga0ebf54364c6a2be6eb19ded6b18b6387',1,'stm32f407xx_matlab.h']]], - ['tim7_5firqhandler_72',['TIM7_IRQHandler',['../stm32f4xx__matlab__tim_8c.html#a98cff83252098363b2dbca9608df964e',1,'stm32f4xx_matlab_tim.c']]], - ['tim7_5firqn_73',['TIM7_IRQn',['../group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a53cadc1e164ec85d0ea4cd143608e8e1',1,'stm32f407xx_matlab.h']]], - ['tim7_5ftrgo_74',['TIM7_TRGO',['../struct_slave_channels.html#a8a06a1b3f32a6abaf0a7ad38e27cf0e1',1,'SlaveChannels']]], - ['tim7s_75',['tim7s',['../group___m_a_i_n___s_i_m_u_l_a_t_o_r.html#gaf4ae2f8710078d4b2c0f07a4265ba66a',1,'stm32f4xx_matlab_conf.h']]], - ['tim8_76',['TIM8',['../group___peripheral__declaration.html#ga9a3660400b17735e91331f256095810e',1,'stm32f407xx_matlab.h']]], - ['tim8_77',['tim8',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga7cd2675665015ace1ee986d66c9cbfb2',1,'stm32f4xx_periph_registers.c']]], - ['tim8_5fbase_78',['TIM8_BASE',['../group___peripheral__memory__map.html#ga5b72f698b7a048a6f9fcfe2efe5bc1db',1,'stm32f407xx_matlab.h']]], - ['tim8_5fbrk_5ftim12_5firqhandler_79',['TIM8_BRK_TIM12_IRQHandler',['../stm32f4xx__matlab__tim_8c.html#a301e0d3520f05f672ce047976f75ff6a',1,'stm32f4xx_matlab_tim.c']]], - ['tim8_5fbrk_5ftim12_5firqn_80',['TIM8_BRK_TIM12_IRQn',['../group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a3e01328006d19f7d32354271b9f61dce',1,'stm32f407xx_matlab.h']]], - ['tim8_5fcc_5firqn_81',['TIM8_CC_IRQn',['../group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a637750639eff4e2b4aae80ed6f3cf67f',1,'stm32f407xx_matlab.h']]], - ['tim8_5ftrg_5fcom_5ftim14_5firqhandler_82',['TIM8_TRG_COM_TIM14_IRQHandler',['../stm32f4xx__matlab__tim_8c.html#a4c8359a023f7ede4a9d9f94ea6fb92da',1,'stm32f4xx_matlab_tim.c']]], - ['tim8_5ftrg_5fcom_5ftim14_5firqn_83',['TIM8_TRG_COM_TIM14_IRQn',['../group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8ae252b31c3a341acbe9a467e243137307',1,'stm32f407xx_matlab.h']]], - ['tim8_5ftrgo_84',['TIM8_TRGO',['../struct_slave_channels.html#a591c0247b983b782f88fb92aea40f0c7',1,'SlaveChannels']]], - ['tim8_5fup_5ftim13_5firqhandler_85',['TIM8_UP_TIM13_IRQHandler',['../stm32f4xx__matlab__tim_8c.html#a7fb516f8826d882ac91cfc093884fcf5',1,'stm32f4xx_matlab_tim.c']]], - ['tim8_5fup_5ftim13_5firqn_86',['TIM8_UP_TIM13_IRQn',['../group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8aa8d8f67a98f24de6f0b36ad6b1f29a7d',1,'stm32f407xx_matlab.h']]], - ['tim9_87',['TIM9',['../group___peripheral__declaration.html#gaf52b4b4c36110a0addfa98059f54a50e',1,'stm32f407xx_matlab.h']]], - ['tim9_88',['tim9',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga3d6c0e6c095d01dac6c94c83c2e9e55f',1,'stm32f4xx_periph_registers.c']]], - ['tim9_5fbase_89',['TIM9_BASE',['../group___peripheral__memory__map.html#ga92ae902be7902560939223dd765ece08',1,'stm32f407xx_matlab.h']]], - ['tim_5farr_5farr_90',['TIM_ARR_ARR',['../group___peripheral___registers___bits___definition.html#gace50256fdecc38f641050a4a3266e4d9',1,'stm32f407xx_matlab.h']]], - ['tim_5farr_5farr_5fmsk_91',['TIM_ARR_ARR_Msk',['../group___peripheral___registers___bits___definition.html#ga166174bde137aa84aec495eef6907ed3',1,'stm32f407xx_matlab.h']]], - ['tim_5farr_5farr_5fpos_92',['TIM_ARR_ARR_Pos',['../group___peripheral___registers___bits___definition.html#ga8430ae919aa2e98c8a4cb32049ae5c3b',1,'stm32f407xx_matlab.h']]], - ['tim_5fbdtr_5faoe_93',['TIM_BDTR_AOE',['../group___peripheral___registers___bits___definition.html#ga59f15008050f91fa3ecc9eaaa971a509',1,'stm32f407xx_matlab.h']]], - ['tim_5fbdtr_5faoe_5fmsk_94',['TIM_BDTR_AOE_Msk',['../group___peripheral___registers___bits___definition.html#gaa9f2a293cb57e4e53908ff3968b44eda',1,'stm32f407xx_matlab.h']]], - ['tim_5fbdtr_5faoe_5fpos_95',['TIM_BDTR_AOE_Pos',['../group___peripheral___registers___bits___definition.html#ga7c59af6d6570d3f4c7bff1efcde8fd5a',1,'stm32f407xx_matlab.h']]], - ['tim_5fbdtr_5fbke_96',['TIM_BDTR_BKE',['../group___peripheral___registers___bits___definition.html#ga74250b040dd9fd9c09dcc54cdd6d86d8',1,'stm32f407xx_matlab.h']]], - ['tim_5fbdtr_5fbke_5fmsk_97',['TIM_BDTR_BKE_Msk',['../group___peripheral___registers___bits___definition.html#ga2272c6e4c575623c1f46f482cd957415',1,'stm32f407xx_matlab.h']]], - ['tim_5fbdtr_5fbke_5fpos_98',['TIM_BDTR_BKE_Pos',['../group___peripheral___registers___bits___definition.html#ga27bff46bd1b077d0a152e4600397f98d',1,'stm32f407xx_matlab.h']]], - ['tim_5fbdtr_5fbkp_99',['TIM_BDTR_BKP',['../group___peripheral___registers___bits___definition.html#ga3247abbbf0d00260be051d176d88020e',1,'stm32f407xx_matlab.h']]], - ['tim_5fbdtr_5fbkp_5fmsk_100',['TIM_BDTR_BKP_Msk',['../group___peripheral___registers___bits___definition.html#ga101b7d11ccc8db986ee394ec26167130',1,'stm32f407xx_matlab.h']]], - ['tim_5fbdtr_5fbkp_5fpos_101',['TIM_BDTR_BKP_Pos',['../group___peripheral___registers___bits___definition.html#gaf42525a0a24fac15595720c1ef01d57a',1,'stm32f407xx_matlab.h']]], - ['tim_5fbdtr_5fdtg_102',['TIM_BDTR_DTG',['../group___peripheral___registers___bits___definition.html#gabcf985e9c78f15e1e44b2bc4d2bafc67',1,'stm32f407xx_matlab.h']]], - ['tim_5fbdtr_5fdtg_5f0_103',['TIM_BDTR_DTG_0',['../group___peripheral___registers___bits___definition.html#ga4b575cca31b0e22ef1d5b842aa162bfc',1,'stm32f407xx_matlab.h']]], - ['tim_5fbdtr_5fdtg_5f1_104',['TIM_BDTR_DTG_1',['../group___peripheral___registers___bits___definition.html#ga0f33ae1e9b7847a60032a60d0cc7f81d',1,'stm32f407xx_matlab.h']]], - ['tim_5fbdtr_5fdtg_5f2_105',['TIM_BDTR_DTG_2',['../group___peripheral___registers___bits___definition.html#ga2f06a132eba960bd6cc972e3580d537c',1,'stm32f407xx_matlab.h']]], - ['tim_5fbdtr_5fdtg_5f3_106',['TIM_BDTR_DTG_3',['../group___peripheral___registers___bits___definition.html#gae7868643a65285fc7132f040c8950f43',1,'stm32f407xx_matlab.h']]], - ['tim_5fbdtr_5fdtg_5f4_107',['TIM_BDTR_DTG_4',['../group___peripheral___registers___bits___definition.html#ga503b44e30a5fb77c34630d1faca70213',1,'stm32f407xx_matlab.h']]], - ['tim_5fbdtr_5fdtg_5f5_108',['TIM_BDTR_DTG_5',['../group___peripheral___registers___bits___definition.html#ga83a12ecb0a8dd21bc164d9a345ea564f',1,'stm32f407xx_matlab.h']]], - ['tim_5fbdtr_5fdtg_5f6_109',['TIM_BDTR_DTG_6',['../group___peripheral___registers___bits___definition.html#gaf7d418cbd0db89991522cb6be34a017e',1,'stm32f407xx_matlab.h']]], - ['tim_5fbdtr_5fdtg_5f7_110',['TIM_BDTR_DTG_7',['../group___peripheral___registers___bits___definition.html#gac945c8bcf5567912a88eb2acee53c45b',1,'stm32f407xx_matlab.h']]], - ['tim_5fbdtr_5fdtg_5fmsk_111',['TIM_BDTR_DTG_Msk',['../group___peripheral___registers___bits___definition.html#ga2c52bd0a743ce97111f4f7210f4f0875',1,'stm32f407xx_matlab.h']]], - ['tim_5fbdtr_5fdtg_5fpos_112',['TIM_BDTR_DTG_Pos',['../group___peripheral___registers___bits___definition.html#ga20f8f8f7a4e2e060b4b51e0a8adc6201',1,'stm32f407xx_matlab.h']]], - ['tim_5fbdtr_5flock_113',['TIM_BDTR_LOCK',['../group___peripheral___registers___bits___definition.html#ga7e4215d17f0548dfcf0b15fe4d0f4651',1,'stm32f407xx_matlab.h']]], - ['tim_5fbdtr_5flock_5f0_114',['TIM_BDTR_LOCK_0',['../group___peripheral___registers___bits___definition.html#gabbd1736c8172e7cd098bb591264b07bf',1,'stm32f407xx_matlab.h']]], - ['tim_5fbdtr_5flock_5f1_115',['TIM_BDTR_LOCK_1',['../group___peripheral___registers___bits___definition.html#ga756df80ff8c34399435f52dca18e6eee',1,'stm32f407xx_matlab.h']]], - ['tim_5fbdtr_5flock_5fmsk_116',['TIM_BDTR_LOCK_Msk',['../group___peripheral___registers___bits___definition.html#ga31c7b82190b30d879c3c7b3a46b9ab82',1,'stm32f407xx_matlab.h']]], - ['tim_5fbdtr_5flock_5fpos_117',['TIM_BDTR_LOCK_Pos',['../group___peripheral___registers___bits___definition.html#ga71810028fd9aba73ee3b92d59017cb8d',1,'stm32f407xx_matlab.h']]], - ['tim_5fbdtr_5fmoe_118',['TIM_BDTR_MOE',['../group___peripheral___registers___bits___definition.html#ga277a096614829feba2d0a4fbb7d3dffc',1,'stm32f407xx_matlab.h']]], - ['tim_5fbdtr_5fmoe_5fmsk_119',['TIM_BDTR_MOE_Msk',['../group___peripheral___registers___bits___definition.html#gaead4c63fdacf9c85e3c997275649aa8e',1,'stm32f407xx_matlab.h']]], - ['tim_5fbdtr_5fmoe_5fpos_120',['TIM_BDTR_MOE_Pos',['../group___peripheral___registers___bits___definition.html#gae1874eb52559400db69885a6dee768c4',1,'stm32f407xx_matlab.h']]], - ['tim_5fbdtr_5fossi_121',['TIM_BDTR_OSSI',['../group___peripheral___registers___bits___definition.html#gab1cf04e70ccf3d4aba5afcf2496a411a',1,'stm32f407xx_matlab.h']]], - ['tim_5fbdtr_5fossi_5fmsk_122',['TIM_BDTR_OSSI_Msk',['../group___peripheral___registers___bits___definition.html#ga05ff8c5f843f6587554de55163a0f420',1,'stm32f407xx_matlab.h']]], - ['tim_5fbdtr_5fossi_5fpos_123',['TIM_BDTR_OSSI_Pos',['../group___peripheral___registers___bits___definition.html#ga508a8d8aea6def7bd3dd689ff5f47312',1,'stm32f407xx_matlab.h']]], - ['tim_5fbdtr_5fossr_124',['TIM_BDTR_OSSR',['../group___peripheral___registers___bits___definition.html#gaf9435f36d53c6be1107e57ab6a82c16e',1,'stm32f407xx_matlab.h']]], - ['tim_5fbdtr_5fossr_5fmsk_125',['TIM_BDTR_OSSR_Msk',['../group___peripheral___registers___bits___definition.html#ga396c60115df4f4f217ae3b2df15d130c',1,'stm32f407xx_matlab.h']]], - ['tim_5fbdtr_5fossr_5fpos_126',['TIM_BDTR_OSSR_Pos',['../group___peripheral___registers___bits___definition.html#ga5738bf6a27c598bc93b37db41f1a21c1',1,'stm32f407xx_matlab.h']]], - ['tim_5fccer_5fcc1e_127',['TIM_CCER_CC1E',['../group___peripheral___registers___bits___definition.html#ga3f494b9881e7b97bb2d79f7ad4e79937',1,'stm32f407xx_matlab.h']]], - ['tim_5fccer_5fcc1e_5fmsk_128',['TIM_CCER_CC1E_Msk',['../group___peripheral___registers___bits___definition.html#ga871be5249ffb7666a32f4e2e60e50a8c',1,'stm32f407xx_matlab.h']]], - ['tim_5fccer_5fcc1e_5fpos_129',['TIM_CCER_CC1E_Pos',['../group___peripheral___registers___bits___definition.html#ga6da61acdf3f1662c2a522820260f0ca1',1,'stm32f407xx_matlab.h']]], - ['tim_5fccer_5fcc1ne_130',['TIM_CCER_CC1NE',['../group___peripheral___registers___bits___definition.html#ga813056b3f90a13c4432aeba55f28957e',1,'stm32f407xx_matlab.h']]], - ['tim_5fccer_5fcc1ne_5fmsk_131',['TIM_CCER_CC1NE_Msk',['../group___peripheral___registers___bits___definition.html#ga6f84300589fc23c7ad7c688b77adffd6',1,'stm32f407xx_matlab.h']]], - ['tim_5fccer_5fcc1ne_5fpos_132',['TIM_CCER_CC1NE_Pos',['../group___peripheral___registers___bits___definition.html#gac27744605da2a44ce88bcd692a6dd639',1,'stm32f407xx_matlab.h']]], - ['tim_5fccer_5fcc1np_133',['TIM_CCER_CC1NP',['../group___peripheral___registers___bits___definition.html#ga403fc501d4d8de6cabee6b07acb81a36',1,'stm32f407xx_matlab.h']]], - ['tim_5fccer_5fcc1np_5fmsk_134',['TIM_CCER_CC1NP_Msk',['../group___peripheral___registers___bits___definition.html#ga22ca6b2d577776a67d48e9a7e1863700',1,'stm32f407xx_matlab.h']]], - ['tim_5fccer_5fcc1np_5fpos_135',['TIM_CCER_CC1NP_Pos',['../group___peripheral___registers___bits___definition.html#ga17cab7ddc6363d68c881d424dc2f95b3',1,'stm32f407xx_matlab.h']]], - ['tim_5fccer_5fcc1p_136',['TIM_CCER_CC1P',['../group___peripheral___registers___bits___definition.html#ga0ca0aedba14241caff739afb3c3ee291',1,'stm32f407xx_matlab.h']]], - ['tim_5fccer_5fcc1p_5fmsk_137',['TIM_CCER_CC1P_Msk',['../group___peripheral___registers___bits___definition.html#ga3006ecce72e486321261536ae385732f',1,'stm32f407xx_matlab.h']]], - ['tim_5fccer_5fcc1p_5fpos_138',['TIM_CCER_CC1P_Pos',['../group___peripheral___registers___bits___definition.html#ga15c77329fadbcb3c84bde50fca4531fb',1,'stm32f407xx_matlab.h']]], - ['tim_5fccer_5fcc2e_139',['TIM_CCER_CC2E',['../group___peripheral___registers___bits___definition.html#ga76392a4d63674cd0db0a55762458f16c',1,'stm32f407xx_matlab.h']]], - ['tim_5fccer_5fcc2e_5fmsk_140',['TIM_CCER_CC2E_Msk',['../group___peripheral___registers___bits___definition.html#ga91010bed31fbd01d7013fe9be759b215',1,'stm32f407xx_matlab.h']]], - ['tim_5fccer_5fcc2e_5fpos_141',['TIM_CCER_CC2E_Pos',['../group___peripheral___registers___bits___definition.html#ga4a7e6fef34c0f02a97140620a2429b84',1,'stm32f407xx_matlab.h']]], - ['tim_5fccer_5fcc2ne_142',['TIM_CCER_CC2NE',['../group___peripheral___registers___bits___definition.html#ga6a784649120eddec31998f34323d4156',1,'stm32f407xx_matlab.h']]], - ['tim_5fccer_5fcc2ne_5fmsk_143',['TIM_CCER_CC2NE_Msk',['../group___peripheral___registers___bits___definition.html#ga395e49f88082d5e2144801c98047e03b',1,'stm32f407xx_matlab.h']]], - ['tim_5fccer_5fcc2ne_5fpos_144',['TIM_CCER_CC2NE_Pos',['../group___peripheral___registers___bits___definition.html#ga5a035ed74e6d62a0fcf54bd0b31f785a',1,'stm32f407xx_matlab.h']]], - ['tim_5fccer_5fcc2np_145',['TIM_CCER_CC2NP',['../group___peripheral___registers___bits___definition.html#ga387de559d8b16b16f3934fddd2aa969f',1,'stm32f407xx_matlab.h']]], - ['tim_5fccer_5fcc2np_5fmsk_146',['TIM_CCER_CC2NP_Msk',['../group___peripheral___registers___bits___definition.html#ga1b294ed91060a15ee77651cd8e688e70',1,'stm32f407xx_matlab.h']]], - ['tim_5fccer_5fcc2np_5fpos_147',['TIM_CCER_CC2NP_Pos',['../group___peripheral___registers___bits___definition.html#ga8de88ef55a7e82a4fe7379a0568da7ab',1,'stm32f407xx_matlab.h']]], - ['tim_5fccer_5fcc2p_148',['TIM_CCER_CC2P',['../group___peripheral___registers___bits___definition.html#ga3136c6e776c6066509d298b6a9b34912',1,'stm32f407xx_matlab.h']]], - ['tim_5fccer_5fcc2p_5fmsk_149',['TIM_CCER_CC2P_Msk',['../group___peripheral___registers___bits___definition.html#ga95f10f70479dce9444a304a58dfa52e1',1,'stm32f407xx_matlab.h']]], - ['tim_5fccer_5fcc2p_5fpos_150',['TIM_CCER_CC2P_Pos',['../group___peripheral___registers___bits___definition.html#gab6eed48ffae9d0a886c124b2993b8a9f',1,'stm32f407xx_matlab.h']]], - ['tim_5fccer_5fcc3e_151',['TIM_CCER_CC3E',['../group___peripheral___registers___bits___definition.html#ga1da114e666b61f09cf25f50cdaa7f81f',1,'stm32f407xx_matlab.h']]], - ['tim_5fccer_5fcc3e_5fmsk_152',['TIM_CCER_CC3E_Msk',['../group___peripheral___registers___bits___definition.html#ga800a18a966d63d71dfc6cf7e3c18ca08',1,'stm32f407xx_matlab.h']]], - ['tim_5fccer_5fcc3e_5fpos_153',['TIM_CCER_CC3E_Pos',['../group___peripheral___registers___bits___definition.html#gaaee67670829d7a6333cae4b5eada7899',1,'stm32f407xx_matlab.h']]], - ['tim_5fccer_5fcc3ne_154',['TIM_CCER_CC3NE',['../group___peripheral___registers___bits___definition.html#gad46cce61d3bd83b64257ba75e54ee1aa',1,'stm32f407xx_matlab.h']]], - ['tim_5fccer_5fcc3ne_5fmsk_155',['TIM_CCER_CC3NE_Msk',['../group___peripheral___registers___bits___definition.html#ga34cbf30b58b4fa02ddc7c1bab93420b3',1,'stm32f407xx_matlab.h']]], - ['tim_5fccer_5fcc3ne_5fpos_156',['TIM_CCER_CC3NE_Pos',['../group___peripheral___registers___bits___definition.html#ga0e4ec9ec3d3f6b778c7750f4861de8dc',1,'stm32f407xx_matlab.h']]], - ['tim_5fccer_5fcc3np_157',['TIM_CCER_CC3NP',['../group___peripheral___registers___bits___definition.html#ga4029686d3307111d3f9f4400e29e4521',1,'stm32f407xx_matlab.h']]], - ['tim_5fccer_5fcc3np_5fmsk_158',['TIM_CCER_CC3NP_Msk',['../group___peripheral___registers___bits___definition.html#ga013c6bc2ba905dea2713cdef67f39c6f',1,'stm32f407xx_matlab.h']]], - ['tim_5fccer_5fcc3np_5fpos_159',['TIM_CCER_CC3NP_Pos',['../group___peripheral___registers___bits___definition.html#gacc4768173a56472e6f19ca49bb229e6a',1,'stm32f407xx_matlab.h']]], - ['tim_5fccer_5fcc3p_160',['TIM_CCER_CC3P',['../group___peripheral___registers___bits___definition.html#ga6220a5cd34c7a7a39e10c854aa00d2e5',1,'stm32f407xx_matlab.h']]], - ['tim_5fccer_5fcc3p_5fmsk_161',['TIM_CCER_CC3P_Msk',['../group___peripheral___registers___bits___definition.html#ga647aadf30c1f4c7850a025bce9e264a6',1,'stm32f407xx_matlab.h']]], - ['tim_5fccer_5fcc3p_5fpos_162',['TIM_CCER_CC3P_Pos',['../group___peripheral___registers___bits___definition.html#gab92731a4de3cb45962bfc34f3986a3bb',1,'stm32f407xx_matlab.h']]], - ['tim_5fccer_5fcc4e_163',['TIM_CCER_CC4E',['../group___peripheral___registers___bits___definition.html#ga940b041ab5975311f42f26d314a4b621',1,'stm32f407xx_matlab.h']]], - ['tim_5fccer_5fcc4e_5fmsk_164',['TIM_CCER_CC4E_Msk',['../group___peripheral___registers___bits___definition.html#gae8f00da3ce9a145e9c7c0ece18706d05',1,'stm32f407xx_matlab.h']]], - ['tim_5fccer_5fcc4e_5fpos_165',['TIM_CCER_CC4E_Pos',['../group___peripheral___registers___bits___definition.html#ga8e4f1890df26547229ce711eed7a30c3',1,'stm32f407xx_matlab.h']]], - ['tim_5fccer_5fcc4np_166',['TIM_CCER_CC4NP',['../group___peripheral___registers___bits___definition.html#ga41b88bff3f38cec0617ce66fa5aef260',1,'stm32f407xx_matlab.h']]], - ['tim_5fccer_5fcc4np_5fmsk_167',['TIM_CCER_CC4NP_Msk',['../group___peripheral___registers___bits___definition.html#ga7e263b29e870a454c029f4a825f4f50e',1,'stm32f407xx_matlab.h']]], - ['tim_5fccer_5fcc4np_5fpos_168',['TIM_CCER_CC4NP_Pos',['../group___peripheral___registers___bits___definition.html#ga451b690ca839a363b6b911bcacafffb4',1,'stm32f407xx_matlab.h']]], - ['tim_5fccer_5fcc4p_169',['TIM_CCER_CC4P',['../group___peripheral___registers___bits___definition.html#ga3faf23dc47e1b0877352d7f5a00f72e1',1,'stm32f407xx_matlab.h']]], - ['tim_5fccer_5fcc4p_5fmsk_170',['TIM_CCER_CC4P_Msk',['../group___peripheral___registers___bits___definition.html#ga22962f81c9abfc88ae30f50b5592d3a7',1,'stm32f407xx_matlab.h']]], - ['tim_5fccer_5fcc4p_5fpos_171',['TIM_CCER_CC4P_Pos',['../group___peripheral___registers___bits___definition.html#ga0b16bb9029a386a09ca24796a74f7fa8',1,'stm32f407xx_matlab.h']]], - ['tim_5fccmr1_5fcc1s_172',['TIM_CCMR1_CC1S',['../group___peripheral___registers___bits___definition.html#ga95291df1eaf532c5c996d176648938eb',1,'stm32f407xx_matlab.h']]], - ['tim_5fccmr1_5fcc1s_5f0_173',['TIM_CCMR1_CC1S_0',['../group___peripheral___registers___bits___definition.html#ga1e4968b5500d58d1aebce888da31eb5d',1,'stm32f407xx_matlab.h']]], - ['tim_5fccmr1_5fcc1s_5f1_174',['TIM_CCMR1_CC1S_1',['../group___peripheral___registers___bits___definition.html#ga299207b757f31c9c02471ab5f4f59dbe',1,'stm32f407xx_matlab.h']]], - ['tim_5fccmr1_5fcc1s_5fmsk_175',['TIM_CCMR1_CC1S_Msk',['../group___peripheral___registers___bits___definition.html#gae45972a14def2a4e25e20a688e535b80',1,'stm32f407xx_matlab.h']]], - ['tim_5fccmr1_5fcc1s_5fpos_176',['TIM_CCMR1_CC1S_Pos',['../group___peripheral___registers___bits___definition.html#ga8824b80350897e1b65c1b98f1b7e9469',1,'stm32f407xx_matlab.h']]], - ['tim_5fccmr1_5fcc2s_177',['TIM_CCMR1_CC2S',['../group___peripheral___registers___bits___definition.html#gacdb0986b78bea5b53ea61e4ddd667cbf',1,'stm32f407xx_matlab.h']]], - ['tim_5fccmr1_5fcc2s_5f0_178',['TIM_CCMR1_CC2S_0',['../group___peripheral___registers___bits___definition.html#ga52bb0e50c11c35dcf42aeff7f1c22874',1,'stm32f407xx_matlab.h']]], - ['tim_5fccmr1_5fcc2s_5f1_179',['TIM_CCMR1_CC2S_1',['../group___peripheral___registers___bits___definition.html#ga78303c37fdbe0be80f5fc7d21e9eba45',1,'stm32f407xx_matlab.h']]], - ['tim_5fccmr1_5fcc2s_5fmsk_180',['TIM_CCMR1_CC2S_Msk',['../group___peripheral___registers___bits___definition.html#ga1df8354fa71992fddecba93c6309c7f3',1,'stm32f407xx_matlab.h']]], - ['tim_5fccmr1_5fcc2s_5fpos_181',['TIM_CCMR1_CC2S_Pos',['../group___peripheral___registers___bits___definition.html#ga2e06c5ff5024706a767be3454512401e',1,'stm32f407xx_matlab.h']]], - ['tim_5fccmr1_5fic1f_182',['TIM_CCMR1_IC1F',['../group___peripheral___registers___bits___definition.html#gab0ee123675d8b8f98b5a6eeeccf37912',1,'stm32f407xx_matlab.h']]], - ['tim_5fccmr1_5fic1f_5f0_183',['TIM_CCMR1_IC1F_0',['../group___peripheral___registers___bits___definition.html#ga7dde4afee556d2d8d22885f191da65a6',1,'stm32f407xx_matlab.h']]], - ['tim_5fccmr1_5fic1f_5f1_184',['TIM_CCMR1_IC1F_1',['../group___peripheral___registers___bits___definition.html#ga201491465e6864088210bccb8491be84',1,'stm32f407xx_matlab.h']]], - ['tim_5fccmr1_5fic1f_5f2_185',['TIM_CCMR1_IC1F_2',['../group___peripheral___registers___bits___definition.html#gabaa55ab1e0109b055cabef579c32d67b',1,'stm32f407xx_matlab.h']]], - ['tim_5fccmr1_5fic1f_5f3_186',['TIM_CCMR1_IC1F_3',['../group___peripheral___registers___bits___definition.html#ga23da95530eb6d6451c7c9e451a580f42',1,'stm32f407xx_matlab.h']]], - ['tim_5fccmr1_5fic1f_5fmsk_187',['TIM_CCMR1_IC1F_Msk',['../group___peripheral___registers___bits___definition.html#gade8750e792254e281c4999de3fbf9e13',1,'stm32f407xx_matlab.h']]], - ['tim_5fccmr1_5fic1f_5fpos_188',['TIM_CCMR1_IC1F_Pos',['../group___peripheral___registers___bits___definition.html#ga4b270ce595ea92cabc0e62576b5cbdb0',1,'stm32f407xx_matlab.h']]], - ['tim_5fccmr1_5fic1psc_189',['TIM_CCMR1_IC1PSC',['../group___peripheral___registers___bits___definition.html#gab46b7186665f5308cd2ca52acfb63e72',1,'stm32f407xx_matlab.h']]], - ['tim_5fccmr1_5fic1psc_5f0_190',['TIM_CCMR1_IC1PSC_0',['../group___peripheral___registers___bits___definition.html#ga05673358a44aeaa56daefca67341b29d',1,'stm32f407xx_matlab.h']]], - ['tim_5fccmr1_5fic1psc_5f1_191',['TIM_CCMR1_IC1PSC_1',['../group___peripheral___registers___bits___definition.html#gaf42b75da9b2f127dca98b6ca616f7add',1,'stm32f407xx_matlab.h']]], - ['tim_5fccmr1_5fic1psc_5fmsk_192',['TIM_CCMR1_IC1PSC_Msk',['../group___peripheral___registers___bits___definition.html#ga0a7ca2ec3b7bc576b7883702a45823d2',1,'stm32f407xx_matlab.h']]], - ['tim_5fccmr1_5fic1psc_5fpos_193',['TIM_CCMR1_IC1PSC_Pos',['../group___peripheral___registers___bits___definition.html#ga84059edcc2ee8d02b8bc6757b667b47a',1,'stm32f407xx_matlab.h']]], - ['tim_5fccmr1_5fic2f_194',['TIM_CCMR1_IC2F',['../group___peripheral___registers___bits___definition.html#ga2b942752d686c23323880ff576e7dffb',1,'stm32f407xx_matlab.h']]], - ['tim_5fccmr1_5fic2f_5f0_195',['TIM_CCMR1_IC2F_0',['../group___peripheral___registers___bits___definition.html#ga5d75acd7072f28844074702683d8493f',1,'stm32f407xx_matlab.h']]], - ['tim_5fccmr1_5fic2f_5f1_196',['TIM_CCMR1_IC2F_1',['../group___peripheral___registers___bits___definition.html#ga40e49318b54b16bda6fd7feea7c9a7dd',1,'stm32f407xx_matlab.h']]], - ['tim_5fccmr1_5fic2f_5f2_197',['TIM_CCMR1_IC2F_2',['../group___peripheral___registers___bits___definition.html#ga932148c784f5cbee4dfcafcbadaf0107',1,'stm32f407xx_matlab.h']]], - ['tim_5fccmr1_5fic2f_5f3_198',['TIM_CCMR1_IC2F_3',['../group___peripheral___registers___bits___definition.html#gafece48b6f595ef9717d523fa23cea1e8',1,'stm32f407xx_matlab.h']]], - ['tim_5fccmr1_5fic2f_5fmsk_199',['TIM_CCMR1_IC2F_Msk',['../group___peripheral___registers___bits___definition.html#ga4b1456053707716ae50feded2a118887',1,'stm32f407xx_matlab.h']]], - ['tim_5fccmr1_5fic2f_5fpos_200',['TIM_CCMR1_IC2F_Pos',['../group___peripheral___registers___bits___definition.html#gaed5a16f773b95122caa60dbdd5b22964',1,'stm32f407xx_matlab.h']]], - ['tim_5fccmr1_5fic2psc_201',['TIM_CCMR1_IC2PSC',['../group___peripheral___registers___bits___definition.html#ga5e8e704f9ce5742f45e15e3b3126aa9d',1,'stm32f407xx_matlab.h']]], - ['tim_5fccmr1_5fic2psc_5f0_202',['TIM_CCMR1_IC2PSC_0',['../group___peripheral___registers___bits___definition.html#ga39206b27b5b1c5941b2a14ee8e2f1223',1,'stm32f407xx_matlab.h']]], - ['tim_5fccmr1_5fic2psc_5f1_203',['TIM_CCMR1_IC2PSC_1',['../group___peripheral___registers___bits___definition.html#gae861d74943f3c045421f9fdc8b966841',1,'stm32f407xx_matlab.h']]], - ['tim_5fccmr1_5fic2psc_5fmsk_204',['TIM_CCMR1_IC2PSC_Msk',['../group___peripheral___registers___bits___definition.html#gafa7570c3a71156c52b0d95b4199f5d3e',1,'stm32f407xx_matlab.h']]], - ['tim_5fccmr1_5fic2psc_5fpos_205',['TIM_CCMR1_IC2PSC_Pos',['../group___peripheral___registers___bits___definition.html#ga5eb62126e13b62bf9ed83bcb358532b3',1,'stm32f407xx_matlab.h']]], - ['tim_5fccmr1_5foc1ce_206',['TIM_CCMR1_OC1CE',['../group___peripheral___registers___bits___definition.html#ga8f44c50cf9928d2afab014e2ca29baba',1,'stm32f407xx_matlab.h']]], - ['tim_5fccmr1_5foc1ce_5fmsk_207',['TIM_CCMR1_OC1CE_Msk',['../group___peripheral___registers___bits___definition.html#ga574f991bc328a80c9b44224e9a74d045',1,'stm32f407xx_matlab.h']]], - ['tim_5fccmr1_5foc1ce_5fpos_208',['TIM_CCMR1_OC1CE_Pos',['../group___peripheral___registers___bits___definition.html#ga78c5f97f5378df55d6b5bdf60219ecd2',1,'stm32f407xx_matlab.h']]], - ['tim_5fccmr1_5foc1fe_209',['TIM_CCMR1_OC1FE',['../group___peripheral___registers___bits___definition.html#gab9c5878e85ce02c22d8a374deebd1b6e',1,'stm32f407xx_matlab.h']]], - ['tim_5fccmr1_5foc1fe_5fmsk_210',['TIM_CCMR1_OC1FE_Msk',['../group___peripheral___registers___bits___definition.html#gaae9383afb4e7ea68c9254f69461ec626',1,'stm32f407xx_matlab.h']]], - ['tim_5fccmr1_5foc1fe_5fpos_211',['TIM_CCMR1_OC1FE_Pos',['../group___peripheral___registers___bits___definition.html#ga99fec0329d7dfc1ebe7d3cb9ca9b5bb1',1,'stm32f407xx_matlab.h']]], - ['tim_5fccmr1_5foc1m_212',['TIM_CCMR1_OC1M',['../group___peripheral___registers___bits___definition.html#ga6ddb3dc889733e71d812baa3873cb13b',1,'stm32f407xx_matlab.h']]], - ['tim_5fccmr1_5foc1m_5f0_213',['TIM_CCMR1_OC1M_0',['../group___peripheral___registers___bits___definition.html#ga410a4752a98081bad8ab3f72b28e7c5f',1,'stm32f407xx_matlab.h']]], - ['tim_5fccmr1_5foc1m_5f1_214',['TIM_CCMR1_OC1M_1',['../group___peripheral___registers___bits___definition.html#ga8b5f6ec25063483641d6dc065d96d2b5',1,'stm32f407xx_matlab.h']]], - ['tim_5fccmr1_5foc1m_5f2_215',['TIM_CCMR1_OC1M_2',['../group___peripheral___registers___bits___definition.html#gac024f6b9972b940925ab5786ee38701b',1,'stm32f407xx_matlab.h']]], - ['tim_5fccmr1_5foc1m_5fmsk_216',['TIM_CCMR1_OC1M_Msk',['../group___peripheral___registers___bits___definition.html#ga45e26a7685848c6cd8572038f06ceab1',1,'stm32f407xx_matlab.h']]], - ['tim_5fccmr1_5foc1m_5fpos_217',['TIM_CCMR1_OC1M_Pos',['../group___peripheral___registers___bits___definition.html#gac4e6a8f6b0480f58e9632780bb393c4d',1,'stm32f407xx_matlab.h']]], - ['tim_5fccmr1_5foc1pe_218',['TIM_CCMR1_OC1PE',['../group___peripheral___registers___bits___definition.html#ga1aa54ddf87a4b339881a8d5368ec80eb',1,'stm32f407xx_matlab.h']]], - ['tim_5fccmr1_5foc1pe_5fmsk_219',['TIM_CCMR1_OC1PE_Msk',['../group___peripheral___registers___bits___definition.html#gad6ad2b511f62760051b61edc1d666b02',1,'stm32f407xx_matlab.h']]], - ['tim_5fccmr1_5foc1pe_5fpos_220',['TIM_CCMR1_OC1PE_Pos',['../group___peripheral___registers___bits___definition.html#gaf34f1ffb1956f71bb24fb8229d76a6a7',1,'stm32f407xx_matlab.h']]], - ['tim_5fccmr1_5foc2ce_221',['TIM_CCMR1_OC2CE',['../group___peripheral___registers___bits___definition.html#ga19a8dd4ea04d262ec4e97b5c7a8677a5',1,'stm32f407xx_matlab.h']]], - ['tim_5fccmr1_5foc2ce_5fmsk_222',['TIM_CCMR1_OC2CE_Msk',['../group___peripheral___registers___bits___definition.html#ga3c788cd4e4e8549585b21e050bf91de5',1,'stm32f407xx_matlab.h']]], - ['tim_5fccmr1_5foc2ce_5fpos_223',['TIM_CCMR1_OC2CE_Pos',['../group___peripheral___registers___bits___definition.html#ga2e30d09989e2a51517b5962e63baf1dd',1,'stm32f407xx_matlab.h']]], - ['tim_5fccmr1_5foc2fe_224',['TIM_CCMR1_OC2FE',['../group___peripheral___registers___bits___definition.html#ga3bf610cf77c3c6c936ce7c4f85992e6c',1,'stm32f407xx_matlab.h']]], - ['tim_5fccmr1_5foc2fe_5fmsk_225',['TIM_CCMR1_OC2FE_Msk',['../group___peripheral___registers___bits___definition.html#ga376f7fd88a0dc62039e03bbc2fdd9569',1,'stm32f407xx_matlab.h']]], - ['tim_5fccmr1_5foc2fe_5fpos_226',['TIM_CCMR1_OC2FE_Pos',['../group___peripheral___registers___bits___definition.html#gab7240668687c24e88a8738b3a84be511',1,'stm32f407xx_matlab.h']]], - ['tim_5fccmr1_5foc2m_227',['TIM_CCMR1_OC2M',['../group___peripheral___registers___bits___definition.html#ga2326bafe64ba2ebdde908d66219eaa6f',1,'stm32f407xx_matlab.h']]], - ['tim_5fccmr1_5foc2m_5f0_228',['TIM_CCMR1_OC2M_0',['../group___peripheral___registers___bits___definition.html#gadbb68b91da16ffd509a6c7a2a397083c',1,'stm32f407xx_matlab.h']]], - ['tim_5fccmr1_5foc2m_5f1_229',['TIM_CCMR1_OC2M_1',['../group___peripheral___registers___bits___definition.html#gaedb673b7e2c016191579de704eb842e4',1,'stm32f407xx_matlab.h']]], - ['tim_5fccmr1_5foc2m_5f2_230',['TIM_CCMR1_OC2M_2',['../group___peripheral___registers___bits___definition.html#gad039a41e5fe97ddf904a0f9f95eb539e',1,'stm32f407xx_matlab.h']]], - ['tim_5fccmr1_5foc2m_5fmsk_231',['TIM_CCMR1_OC2M_Msk',['../group___peripheral___registers___bits___definition.html#ga7082e88c67576a8ce483e0534b0ae8cb',1,'stm32f407xx_matlab.h']]], - ['tim_5fccmr1_5foc2m_5fpos_232',['TIM_CCMR1_OC2M_Pos',['../group___peripheral___registers___bits___definition.html#gae31265c2d3adef5873acc64f2f0045a1',1,'stm32f407xx_matlab.h']]], - ['tim_5fccmr1_5foc2pe_233',['TIM_CCMR1_OC2PE',['../group___peripheral___registers___bits___definition.html#gabddbf508732039730125ab3e87e9d370',1,'stm32f407xx_matlab.h']]], - ['tim_5fccmr1_5foc2pe_5fmsk_234',['TIM_CCMR1_OC2PE_Msk',['../group___peripheral___registers___bits___definition.html#ga664936de978a62b290fe7da4c2b1c395',1,'stm32f407xx_matlab.h']]], - ['tim_5fccmr1_5foc2pe_5fpos_235',['TIM_CCMR1_OC2PE_Pos',['../group___peripheral___registers___bits___definition.html#ga819513a7183766b4427cddfb08413eb7',1,'stm32f407xx_matlab.h']]], - ['tim_5fccmr2_5fcc3s_236',['TIM_CCMR2_CC3S',['../group___peripheral___registers___bits___definition.html#ga2eabcc7e322b02c9c406b3ff70308260',1,'stm32f407xx_matlab.h']]], - ['tim_5fccmr2_5fcc3s_5f0_237',['TIM_CCMR2_CC3S_0',['../group___peripheral___registers___bits___definition.html#ga68c04aea2e89f1e89bd323d6d6e5e6c0',1,'stm32f407xx_matlab.h']]], - ['tim_5fccmr2_5fcc3s_5f1_238',['TIM_CCMR2_CC3S_1',['../group___peripheral___registers___bits___definition.html#ga4bed6648aad6e8d16196246b355452dc',1,'stm32f407xx_matlab.h']]], - ['tim_5fccmr2_5fcc3s_5fmsk_239',['TIM_CCMR2_CC3S_Msk',['../group___peripheral___registers___bits___definition.html#gac236d456c1635745129611f040e50392',1,'stm32f407xx_matlab.h']]], - ['tim_5fccmr2_5fcc3s_5fpos_240',['TIM_CCMR2_CC3S_Pos',['../group___peripheral___registers___bits___definition.html#gaab00cf673f46bb5a112370ff94d5495b',1,'stm32f407xx_matlab.h']]], - ['tim_5fccmr2_5fcc4s_241',['TIM_CCMR2_CC4S',['../group___peripheral___registers___bits___definition.html#ga294e216b50edd1c2f891143e1f971048',1,'stm32f407xx_matlab.h']]], - ['tim_5fccmr2_5fcc4s_5f0_242',['TIM_CCMR2_CC4S_0',['../group___peripheral___registers___bits___definition.html#gabebaa6bffd90b32563bd0fc1ff4a9499',1,'stm32f407xx_matlab.h']]], - ['tim_5fccmr2_5fcc4s_5f1_243',['TIM_CCMR2_CC4S_1',['../group___peripheral___registers___bits___definition.html#ga6386ec77a3a451954325a1512d44f893',1,'stm32f407xx_matlab.h']]], - ['tim_5fccmr2_5fcc4s_5fmsk_244',['TIM_CCMR2_CC4S_Msk',['../group___peripheral___registers___bits___definition.html#ga66957133f2ac46cacb14834a6ad46b9b',1,'stm32f407xx_matlab.h']]], - ['tim_5fccmr2_5fcc4s_5fpos_245',['TIM_CCMR2_CC4S_Pos',['../group___peripheral___registers___bits___definition.html#ga5774c57db57a50e9a1b7e6fa6c2833f6',1,'stm32f407xx_matlab.h']]], - ['tim_5fccmr2_5fic3f_246',['TIM_CCMR2_IC3F',['../group___peripheral___registers___bits___definition.html#gad218af6bd1de72891e1b85d582b766cd',1,'stm32f407xx_matlab.h']]], - ['tim_5fccmr2_5fic3f_5f0_247',['TIM_CCMR2_IC3F_0',['../group___peripheral___registers___bits___definition.html#ga31d5450ebc9ac6ea833a2b341ceea061',1,'stm32f407xx_matlab.h']]], - ['tim_5fccmr2_5fic3f_5f1_248',['TIM_CCMR2_IC3F_1',['../group___peripheral___registers___bits___definition.html#ga26f92a3f831685d6df7ab69e68181849',1,'stm32f407xx_matlab.h']]], - ['tim_5fccmr2_5fic3f_5f2_249',['TIM_CCMR2_IC3F_2',['../group___peripheral___registers___bits___definition.html#ga5e7d7a3c2686a6e31adc1adf2ce65df9',1,'stm32f407xx_matlab.h']]], - ['tim_5fccmr2_5fic3f_5f3_250',['TIM_CCMR2_IC3F_3',['../group___peripheral___registers___bits___definition.html#ga9696c3da027f2b292d077f1ab4cdd14b',1,'stm32f407xx_matlab.h']]], - ['tim_5fccmr2_5fic3f_5fmsk_251',['TIM_CCMR2_IC3F_Msk',['../group___peripheral___registers___bits___definition.html#gaac13900fc61a22d5b43f579e5854fa2c',1,'stm32f407xx_matlab.h']]], - ['tim_5fccmr2_5fic3f_5fpos_252',['TIM_CCMR2_IC3F_Pos',['../group___peripheral___registers___bits___definition.html#gaf23e70bb3dfe3c685a26e6ae00786b62',1,'stm32f407xx_matlab.h']]], - ['tim_5fccmr2_5fic3psc_253',['TIM_CCMR2_IC3PSC',['../group___peripheral___registers___bits___definition.html#gafc3d11f2e968752bc9ec7131c986c3a6',1,'stm32f407xx_matlab.h']]], - ['tim_5fccmr2_5fic3psc_5f0_254',['TIM_CCMR2_IC3PSC_0',['../group___peripheral___registers___bits___definition.html#ga588513395cbf8be6f4749c140fbf811c',1,'stm32f407xx_matlab.h']]], - ['tim_5fccmr2_5fic3psc_5f1_255',['TIM_CCMR2_IC3PSC_1',['../group___peripheral___registers___bits___definition.html#gacd27b9bdcc161c90dc1712074a66f29d',1,'stm32f407xx_matlab.h']]], - ['tim_5fccmr2_5fic3psc_5fmsk_256',['TIM_CCMR2_IC3PSC_Msk',['../group___peripheral___registers___bits___definition.html#gabec127dfbd39286e7467a88e42b0e2a2',1,'stm32f407xx_matlab.h']]], - ['tim_5fccmr2_5fic3psc_5fpos_257',['TIM_CCMR2_IC3PSC_Pos',['../group___peripheral___registers___bits___definition.html#gae531e77cc77a9a76a0f32074ad371cf2',1,'stm32f407xx_matlab.h']]], - ['tim_5fccmr2_5fic4f_258',['TIM_CCMR2_IC4F',['../group___peripheral___registers___bits___definition.html#gad51653fd06a591294d432385e794a19e',1,'stm32f407xx_matlab.h']]], - ['tim_5fccmr2_5fic4f_5f0_259',['TIM_CCMR2_IC4F_0',['../group___peripheral___registers___bits___definition.html#ga7d5fc8b9a6ea27582cb6c25f9654888c',1,'stm32f407xx_matlab.h']]], - ['tim_5fccmr2_5fic4f_5f1_260',['TIM_CCMR2_IC4F_1',['../group___peripheral___registers___bits___definition.html#gac4dcc1562c0c017493e4ee6b32354e85',1,'stm32f407xx_matlab.h']]], - ['tim_5fccmr2_5fic4f_5f2_261',['TIM_CCMR2_IC4F_2',['../group___peripheral___registers___bits___definition.html#ga2b96de7db8b71ac7e414f247b871a53c',1,'stm32f407xx_matlab.h']]], - ['tim_5fccmr2_5fic4f_5f3_262',['TIM_CCMR2_IC4F_3',['../group___peripheral___registers___bits___definition.html#ga25d0f55e5b751f2caed6a943f5682a09',1,'stm32f407xx_matlab.h']]], - ['tim_5fccmr2_5fic4f_5fmsk_263',['TIM_CCMR2_IC4F_Msk',['../group___peripheral___registers___bits___definition.html#gaa9f59cf5cc82d482d733a365cc7d887c',1,'stm32f407xx_matlab.h']]], - ['tim_5fccmr2_5fic4f_5fpos_264',['TIM_CCMR2_IC4F_Pos',['../group___peripheral___registers___bits___definition.html#gafdce62241567cc540d3b7ce61084c1e2',1,'stm32f407xx_matlab.h']]], - ['tim_5fccmr2_5fic4psc_265',['TIM_CCMR2_IC4PSC',['../group___peripheral___registers___bits___definition.html#ga6fd7591e2de10272f7fafb08cdd1b7b0',1,'stm32f407xx_matlab.h']]], - ['tim_5fccmr2_5fic4psc_5f0_266',['TIM_CCMR2_IC4PSC_0',['../group___peripheral___registers___bits___definition.html#ga80f7d206409bc551eab06819e17451e4',1,'stm32f407xx_matlab.h']]], - ['tim_5fccmr2_5fic4psc_5f1_267',['TIM_CCMR2_IC4PSC_1',['../group___peripheral___registers___bits___definition.html#gaf6690f5e98e02addd5e75643767c6d66',1,'stm32f407xx_matlab.h']]], - ['tim_5fccmr2_5fic4psc_5fmsk_268',['TIM_CCMR2_IC4PSC_Msk',['../group___peripheral___registers___bits___definition.html#ga289328a0304739b4459fa74978be5aa4',1,'stm32f407xx_matlab.h']]], - ['tim_5fccmr2_5fic4psc_5fpos_269',['TIM_CCMR2_IC4PSC_Pos',['../group___peripheral___registers___bits___definition.html#ga1df596e58e5b71467be3d85988fb302f',1,'stm32f407xx_matlab.h']]], - ['tim_5fccmr2_5foc3ce_270',['TIM_CCMR2_OC3CE',['../group___peripheral___registers___bits___definition.html#ga4209d414df704ce96c54abb2ea2df66a',1,'stm32f407xx_matlab.h']]], - ['tim_5fccmr2_5foc3ce_5fmsk_271',['TIM_CCMR2_OC3CE_Msk',['../group___peripheral___registers___bits___definition.html#ga040e81b609666fec1f0476346bb8b942',1,'stm32f407xx_matlab.h']]], - ['tim_5fccmr2_5foc3ce_5fpos_272',['TIM_CCMR2_OC3CE_Pos',['../group___peripheral___registers___bits___definition.html#ga03695b16c15f57bd329b050603e11ff6',1,'stm32f407xx_matlab.h']]], - ['tim_5fccmr2_5foc3fe_273',['TIM_CCMR2_OC3FE',['../group___peripheral___registers___bits___definition.html#gae6d8d2847058747ce23a648668ce4dba',1,'stm32f407xx_matlab.h']]], - ['tim_5fccmr2_5foc3fe_5fmsk_274',['TIM_CCMR2_OC3FE_Msk',['../group___peripheral___registers___bits___definition.html#gaef7fdd716098d6370d1fbef9ec6de226',1,'stm32f407xx_matlab.h']]], - ['tim_5fccmr2_5foc3fe_5fpos_275',['TIM_CCMR2_OC3FE_Pos',['../group___peripheral___registers___bits___definition.html#ga3fada082e0cea460d9722f5dca1fe1a8',1,'stm32f407xx_matlab.h']]], - ['tim_5fccmr2_5foc3m_276',['TIM_CCMR2_OC3M',['../group___peripheral___registers___bits___definition.html#ga52095cae524adb237339bfee92e8168a',1,'stm32f407xx_matlab.h']]], - ['tim_5fccmr2_5foc3m_5f0_277',['TIM_CCMR2_OC3M_0',['../group___peripheral___registers___bits___definition.html#ga899b26ffa9c5f30f143306b8598a537f',1,'stm32f407xx_matlab.h']]], - ['tim_5fccmr2_5foc3m_5f1_278',['TIM_CCMR2_OC3M_1',['../group___peripheral___registers___bits___definition.html#ga91476ae2cc3449facafcad82569e14f8',1,'stm32f407xx_matlab.h']]], - ['tim_5fccmr2_5foc3m_5f2_279',['TIM_CCMR2_OC3M_2',['../group___peripheral___registers___bits___definition.html#ga20394da7afcada6c3fc455b05004cff5',1,'stm32f407xx_matlab.h']]], - ['tim_5fccmr2_5foc3m_5fmsk_280',['TIM_CCMR2_OC3M_Msk',['../group___peripheral___registers___bits___definition.html#ga8e306d8b3f5f98f8bfb6002dc2a7ff06',1,'stm32f407xx_matlab.h']]], - ['tim_5fccmr2_5foc3m_5fpos_281',['TIM_CCMR2_OC3M_Pos',['../group___peripheral___registers___bits___definition.html#gafc968db76163687538732d31cf4d4d91',1,'stm32f407xx_matlab.h']]], - ['tim_5fccmr2_5foc3pe_282',['TIM_CCMR2_OC3PE',['../group___peripheral___registers___bits___definition.html#ga276fd2250d2b085b73ef51cb4c099d24',1,'stm32f407xx_matlab.h']]], - ['tim_5fccmr2_5foc3pe_5fmsk_283',['TIM_CCMR2_OC3PE_Msk',['../group___peripheral___registers___bits___definition.html#ga340c7064a44bc7478982f5ef7a7655f9',1,'stm32f407xx_matlab.h']]], - ['tim_5fccmr2_5foc3pe_5fpos_284',['TIM_CCMR2_OC3PE_Pos',['../group___peripheral___registers___bits___definition.html#ga5ebdd2a0a808080fac30e5ee1514f4cf',1,'stm32f407xx_matlab.h']]], - ['tim_5fccmr2_5foc4ce_285',['TIM_CCMR2_OC4CE',['../group___peripheral___registers___bits___definition.html#ga1447dfe94bdd234382bb1f43307ea5c3',1,'stm32f407xx_matlab.h']]], - ['tim_5fccmr2_5foc4ce_5fmsk_286',['TIM_CCMR2_OC4CE_Msk',['../group___peripheral___registers___bits___definition.html#ga3a3897ea2b9197cbc75507df645faefc',1,'stm32f407xx_matlab.h']]], - ['tim_5fccmr2_5foc4ce_5fpos_287',['TIM_CCMR2_OC4CE_Pos',['../group___peripheral___registers___bits___definition.html#ga8b06f4781d9ec977f5be9f010ee44b6b',1,'stm32f407xx_matlab.h']]], - ['tim_5fccmr2_5foc4fe_288',['TIM_CCMR2_OC4FE',['../group___peripheral___registers___bits___definition.html#ga70dc197250c2699d470aea1a7a42ad57',1,'stm32f407xx_matlab.h']]], - ['tim_5fccmr2_5foc4fe_5fmsk_289',['TIM_CCMR2_OC4FE_Msk',['../group___peripheral___registers___bits___definition.html#ga01f0c4e1d96b5dde5af64ea95b2c3880',1,'stm32f407xx_matlab.h']]], - ['tim_5fccmr2_5foc4fe_5fpos_290',['TIM_CCMR2_OC4FE_Pos',['../group___peripheral___registers___bits___definition.html#ga69ec4d183286e02653876ead0a835a09',1,'stm32f407xx_matlab.h']]], - ['tim_5fccmr2_5foc4m_291',['TIM_CCMR2_OC4M',['../group___peripheral___registers___bits___definition.html#gacbed61ff3ba57c7fe6d3386ce3b7af2b',1,'stm32f407xx_matlab.h']]], - ['tim_5fccmr2_5foc4m_5f0_292',['TIM_CCMR2_OC4M_0',['../group___peripheral___registers___bits___definition.html#gad866f52cce9ce32e3c0d181007b82de5',1,'stm32f407xx_matlab.h']]], - ['tim_5fccmr2_5foc4m_5f1_293',['TIM_CCMR2_OC4M_1',['../group___peripheral___registers___bits___definition.html#gafd97b1c86dd4953f3382fea317d165af',1,'stm32f407xx_matlab.h']]], - ['tim_5fccmr2_5foc4m_5f2_294',['TIM_CCMR2_OC4M_2',['../group___peripheral___registers___bits___definition.html#ga431e5cdc0f3dc02fa5a54aa5193ddbab',1,'stm32f407xx_matlab.h']]], - ['tim_5fccmr2_5foc4m_5fmsk_295',['TIM_CCMR2_OC4M_Msk',['../group___peripheral___registers___bits___definition.html#ga0ffb46fed2d65aab83a895d8f791f84f',1,'stm32f407xx_matlab.h']]], - ['tim_5fccmr2_5foc4m_5fpos_296',['TIM_CCMR2_OC4M_Pos',['../group___peripheral___registers___bits___definition.html#ga67d4d6f1f9b93ff94a941d8c574ca400',1,'stm32f407xx_matlab.h']]], - ['tim_5fccmr2_5foc4pe_297',['TIM_CCMR2_OC4PE',['../group___peripheral___registers___bits___definition.html#ga3e951cd3f6593e321cf79b662a1deaaa',1,'stm32f407xx_matlab.h']]], - ['tim_5fccmr2_5foc4pe_5fmsk_298',['TIM_CCMR2_OC4PE_Msk',['../group___peripheral___registers___bits___definition.html#ga28c07cee007c349ef4ba4a954b341ff4',1,'stm32f407xx_matlab.h']]], - ['tim_5fccmr2_5foc4pe_5fpos_299',['TIM_CCMR2_OC4PE_Pos',['../group___peripheral___registers___bits___definition.html#gaf1271844d8091a2494487cd082a585ca',1,'stm32f407xx_matlab.h']]], - ['tim_5fccr1_5fccr1_300',['TIM_CCR1_CCR1',['../group___peripheral___registers___bits___definition.html#gac927cc11eff415210dcf94657d8dfbe0',1,'stm32f407xx_matlab.h']]], - ['tim_5fccr1_5fccr1_5fmsk_301',['TIM_CCR1_CCR1_Msk',['../group___peripheral___registers___bits___definition.html#ga1052d30a540b5332d39cc9e1e23587bb',1,'stm32f407xx_matlab.h']]], - ['tim_5fccr1_5fccr1_5fpos_302',['TIM_CCR1_CCR1_Pos',['../group___peripheral___registers___bits___definition.html#ga815f704b96c35f8f2b4a9160913e36f6',1,'stm32f407xx_matlab.h']]], - ['tim_5fccr2_5fccr2_303',['TIM_CCR2_CCR2',['../group___peripheral___registers___bits___definition.html#ga751e5efd90bdd1fd5f38609f3f5762ba',1,'stm32f407xx_matlab.h']]], - ['tim_5fccr2_5fccr2_5fmsk_304',['TIM_CCR2_CCR2_Msk',['../group___peripheral___registers___bits___definition.html#gab4ef3300e4399d1b036c2e28061d9dd1',1,'stm32f407xx_matlab.h']]], - ['tim_5fccr2_5fccr2_5fpos_305',['TIM_CCR2_CCR2_Pos',['../group___peripheral___registers___bits___definition.html#ga22f43b4f1a39a8ff5124a31e2e37efbf',1,'stm32f407xx_matlab.h']]], - ['tim_5fccr3_5fccr3_306',['TIM_CCR3_CCR3',['../group___peripheral___registers___bits___definition.html#ga4e85064d37d387851e95c5c1f35315a1',1,'stm32f407xx_matlab.h']]], - ['tim_5fccr3_5fccr3_5fmsk_307',['TIM_CCR3_CCR3_Msk',['../group___peripheral___registers___bits___definition.html#ga3983e861f1f4418bf3df69d263550024',1,'stm32f407xx_matlab.h']]], - ['tim_5fccr3_5fccr3_5fpos_308',['TIM_CCR3_CCR3_Pos',['../group___peripheral___registers___bits___definition.html#ga69a2438c905cf2e7f0c15b06090be697',1,'stm32f407xx_matlab.h']]], - ['tim_5fccr4_5fccr4_309',['TIM_CCR4_CCR4',['../group___peripheral___registers___bits___definition.html#ga15c9dd67a6701b5498926ae536773eca',1,'stm32f407xx_matlab.h']]], - ['tim_5fccr4_5fccr4_5fmsk_310',['TIM_CCR4_CCR4_Msk',['../group___peripheral___registers___bits___definition.html#ga2e2e10599fa35e837f604584c742551f',1,'stm32f407xx_matlab.h']]], - ['tim_5fccr4_5fccr4_5fpos_311',['TIM_CCR4_CCR4_Pos',['../group___peripheral___registers___bits___definition.html#ga812691bb8cabc5eef6093926c6afb0fa',1,'stm32f407xx_matlab.h']]], - ['tim_5fcnt_5fcnt_312',['TIM_CNT_CNT',['../group___peripheral___registers___bits___definition.html#ga8bc45c0315de82c1c3a38a243bcd00fc',1,'stm32f407xx_matlab.h']]], - ['tim_5fcnt_5fcnt_5fmsk_313',['TIM_CNT_CNT_Msk',['../group___peripheral___registers___bits___definition.html#gac54bb0107f222981fe8c8416af521fd0',1,'stm32f407xx_matlab.h']]], - ['tim_5fcnt_5fcnt_5fpos_314',['TIM_CNT_CNT_Pos',['../group___peripheral___registers___bits___definition.html#gaf110ca46cc8cf7b55f63cafa563073b2',1,'stm32f407xx_matlab.h']]], - ['tim_5fcr1_5farpe_315',['TIM_CR1_ARPE',['../group___peripheral___registers___bits___definition.html#ga4a3ad409f6b147cdcbafbfe29102f3fd',1,'stm32f407xx_matlab.h']]], - ['tim_5fcr1_5farpe_5fmsk_316',['TIM_CR1_ARPE_Msk',['../group___peripheral___registers___bits___definition.html#ga4e508ecc8ac453c2999b2ca7885f24a8',1,'stm32f407xx_matlab.h']]], - ['tim_5fcr1_5farpe_5fpos_317',['TIM_CR1_ARPE_Pos',['../group___peripheral___registers___bits___definition.html#ga517317561e18e823ac75a35ae05b2c29',1,'stm32f407xx_matlab.h']]], - ['tim_5fcr1_5fcen_318',['TIM_CR1_CEN',['../group___peripheral___registers___bits___definition.html#ga93d86355e5e3b399ed45e1ca83abed2a',1,'stm32f407xx_matlab.h']]], - ['tim_5fcr1_5fcen_5fmsk_319',['TIM_CR1_CEN_Msk',['../group___peripheral___registers___bits___definition.html#gab39f58b244f6d1eb12be39b714e434e5',1,'stm32f407xx_matlab.h']]], - ['tim_5fcr1_5fcen_5fpos_320',['TIM_CR1_CEN_Pos',['../group___peripheral___registers___bits___definition.html#ga9cdca91d88f73215ab00bc9a84938584',1,'stm32f407xx_matlab.h']]], - ['tim_5fcr1_5fckd_321',['TIM_CR1_CKD',['../group___peripheral___registers___bits___definition.html#gacacc4ff7e5b75fd2e4e6b672ccd33a72',1,'stm32f407xx_matlab.h']]], - ['tim_5fcr1_5fckd_5f0_322',['TIM_CR1_CKD_0',['../group___peripheral___registers___bits___definition.html#ga458d536d82aa3db7d227b0f00b36808f',1,'stm32f407xx_matlab.h']]], - ['tim_5fcr1_5fckd_5f1_323',['TIM_CR1_CKD_1',['../group___peripheral___registers___bits___definition.html#ga7ff2d6c2c350e8b719a8ad49c9a6bcbe',1,'stm32f407xx_matlab.h']]], - ['tim_5fcr1_5fckd_5fmsk_324',['TIM_CR1_CKD_Msk',['../group___peripheral___registers___bits___definition.html#ga0894ca61f67f8ce59882c5a9645f68bd',1,'stm32f407xx_matlab.h']]], - ['tim_5fcr1_5fckd_5fpos_325',['TIM_CR1_CKD_Pos',['../group___peripheral___registers___bits___definition.html#gaee3940e6580a2f924894f6f2f80ca856',1,'stm32f407xx_matlab.h']]], - ['tim_5fcr1_5fcms_326',['TIM_CR1_CMS',['../group___peripheral___registers___bits___definition.html#ga352b3c389bde13dd6049de0afdd874f1',1,'stm32f407xx_matlab.h']]], - ['tim_5fcr1_5fcms_5f0_327',['TIM_CR1_CMS_0',['../group___peripheral___registers___bits___definition.html#ga83ca6f7810aba73dc8c12f22092d97a2',1,'stm32f407xx_matlab.h']]], - ['tim_5fcr1_5fcms_5f1_328',['TIM_CR1_CMS_1',['../group___peripheral___registers___bits___definition.html#gab3ee4adcde3c001d3b97d2eae1730ea9',1,'stm32f407xx_matlab.h']]], - ['tim_5fcr1_5fcms_5fmsk_329',['TIM_CR1_CMS_Msk',['../group___peripheral___registers___bits___definition.html#gaee4916455eb6d08d131dd9ae5b8013ee',1,'stm32f407xx_matlab.h']]], - ['tim_5fcr1_5fcms_5fpos_330',['TIM_CR1_CMS_Pos',['../group___peripheral___registers___bits___definition.html#gaa8f425763d1d4c1483ca41a34cda2b2a',1,'stm32f407xx_matlab.h']]], - ['tim_5fcr1_5fdir_331',['TIM_CR1_DIR',['../group___peripheral___registers___bits___definition.html#gacea10770904af189f3aaeb97b45722aa',1,'stm32f407xx_matlab.h']]], - ['tim_5fcr1_5fdir_5fmsk_332',['TIM_CR1_DIR_Msk',['../group___peripheral___registers___bits___definition.html#gad5f92c5c62905feea73880ccbf6836aa',1,'stm32f407xx_matlab.h']]], - ['tim_5fcr1_5fdir_5fpos_333',['TIM_CR1_DIR_Pos',['../group___peripheral___registers___bits___definition.html#ga161776b682c51f69581800125bf89a48',1,'stm32f407xx_matlab.h']]], - ['tim_5fcr1_5fopm_334',['TIM_CR1_OPM',['../group___peripheral___registers___bits___definition.html#ga6d3d1488296350af6d36fbbf71905d29',1,'stm32f407xx_matlab.h']]], - ['tim_5fcr1_5fopm_5fmsk_335',['TIM_CR1_OPM_Msk',['../group___peripheral___registers___bits___definition.html#ga6fbbf98af8ecd146d7eae1874c0f115a',1,'stm32f407xx_matlab.h']]], - ['tim_5fcr1_5fopm_5fpos_336',['TIM_CR1_OPM_Pos',['../group___peripheral___registers___bits___definition.html#ga2cae3644294078a1a12ac19f86ece98e',1,'stm32f407xx_matlab.h']]], - ['tim_5fcr1_5fudis_337',['TIM_CR1_UDIS',['../group___peripheral___registers___bits___definition.html#gaa4f2a9f0cf7b60e3c623af451f141f3c',1,'stm32f407xx_matlab.h']]], - ['tim_5fcr1_5fudis_5fmsk_338',['TIM_CR1_UDIS_Msk',['../group___peripheral___registers___bits___definition.html#gab930af301c357d666089faef3fe38982',1,'stm32f407xx_matlab.h']]], - ['tim_5fcr1_5fudis_5fpos_339',['TIM_CR1_UDIS_Pos',['../group___peripheral___registers___bits___definition.html#ga014a0f9d40c6a34b7fdf70bd8908d14d',1,'stm32f407xx_matlab.h']]], - ['tim_5fcr1_5furs_340',['TIM_CR1_URS',['../group___peripheral___registers___bits___definition.html#ga06c997c2c23e8bef7ca07579762c113b',1,'stm32f407xx_matlab.h']]], - ['tim_5fcr1_5furs_5fmsk_341',['TIM_CR1_URS_Msk',['../group___peripheral___registers___bits___definition.html#ga86b7788d2996e1a0b729c23f6c01df18',1,'stm32f407xx_matlab.h']]], - ['tim_5fcr1_5furs_5fpos_342',['TIM_CR1_URS_Pos',['../group___peripheral___registers___bits___definition.html#gaa68d9cdf8e673e01035272fa228ab239',1,'stm32f407xx_matlab.h']]], - ['tim_5fcr2_5fccds_343',['TIM_CR2_CCDS',['../group___peripheral___registers___bits___definition.html#gade656832d3ec303a2a7a422638dd560e',1,'stm32f407xx_matlab.h']]], - ['tim_5fcr2_5fccds_5fmsk_344',['TIM_CR2_CCDS_Msk',['../group___peripheral___registers___bits___definition.html#ga57abe8dfa0dc138ec4c9f4b0dd72299b',1,'stm32f407xx_matlab.h']]], - ['tim_5fcr2_5fccds_5fpos_345',['TIM_CR2_CCDS_Pos',['../group___peripheral___registers___bits___definition.html#ga159a232ac14d50dc779712b5917e2ab5',1,'stm32f407xx_matlab.h']]], - ['tim_5fcr2_5fccpc_346',['TIM_CR2_CCPC',['../group___peripheral___registers___bits___definition.html#gaae22c9c1197107d6fa629f419a29541e',1,'stm32f407xx_matlab.h']]], - ['tim_5fcr2_5fccpc_5fmsk_347',['TIM_CR2_CCPC_Msk',['../group___peripheral___registers___bits___definition.html#ga2ccf78eb52ea83a81ed28e4815860df9',1,'stm32f407xx_matlab.h']]], - ['tim_5fcr2_5fccpc_5fpos_348',['TIM_CR2_CCPC_Pos',['../group___peripheral___registers___bits___definition.html#ga86a631cdfa58f91c731b709e27ee6d0d',1,'stm32f407xx_matlab.h']]], - ['tim_5fcr2_5fccus_349',['TIM_CR2_CCUS',['../group___peripheral___registers___bits___definition.html#gaf0328c1339b2b1633ef7a8db4c02d0d5',1,'stm32f407xx_matlab.h']]], - ['tim_5fcr2_5fccus_5fmsk_350',['TIM_CR2_CCUS_Msk',['../group___peripheral___registers___bits___definition.html#gaac9908b05b59b90ba3e42124e7ad4347',1,'stm32f407xx_matlab.h']]], - ['tim_5fcr2_5fccus_5fpos_351',['TIM_CR2_CCUS_Pos',['../group___peripheral___registers___bits___definition.html#ga944661589a5e77ab328c5df5569d967a',1,'stm32f407xx_matlab.h']]], - ['tim_5fcr2_5fmms_352',['TIM_CR2_MMS',['../group___peripheral___registers___bits___definition.html#gaaa6987d980e5c4c71c7d0faa1eb97a45',1,'stm32f407xx_matlab.h']]], - ['tim_5fcr2_5fmms_5f0_353',['TIM_CR2_MMS_0',['../group___peripheral___registers___bits___definition.html#gaf3e55308e84106d6501201e66bd46ab6',1,'stm32f407xx_matlab.h']]], - ['tim_5fcr2_5fmms_5f1_354',['TIM_CR2_MMS_1',['../group___peripheral___registers___bits___definition.html#ga4b1036929b0a4ba5bd5cced9b8e0f4c3',1,'stm32f407xx_matlab.h']]], - ['tim_5fcr2_5fmms_5f2_355',['TIM_CR2_MMS_2',['../group___peripheral___registers___bits___definition.html#gacb74a815afdd856d51cfcf1ddf3fce6a',1,'stm32f407xx_matlab.h']]], - ['tim_5fcr2_5fmms_5fmsk_356',['TIM_CR2_MMS_Msk',['../group___peripheral___registers___bits___definition.html#ga8f6c31bf38844218cb8c8ee98aef46c4',1,'stm32f407xx_matlab.h']]], - ['tim_5fcr2_5fmms_5fpos_357',['TIM_CR2_MMS_Pos',['../group___peripheral___registers___bits___definition.html#ga7e8f8be33b5a8e48b67524b93e521a91',1,'stm32f407xx_matlab.h']]], - ['tim_5fcr2_5fois1_358',['TIM_CR2_OIS1',['../group___peripheral___registers___bits___definition.html#ga31b26bf058f88d771c33aff85ec89358',1,'stm32f407xx_matlab.h']]], - ['tim_5fcr2_5fois1_5fmsk_359',['TIM_CR2_OIS1_Msk',['../group___peripheral___registers___bits___definition.html#ga2a08d73020c32fdaa4cc403f234792b1',1,'stm32f407xx_matlab.h']]], - ['tim_5fcr2_5fois1_5fpos_360',['TIM_CR2_OIS1_Pos',['../group___peripheral___registers___bits___definition.html#gaa5a3877d7270c1ddf25da016cc40ed21',1,'stm32f407xx_matlab.h']]], - ['tim_5fcr2_5fois1n_361',['TIM_CR2_OIS1N',['../group___peripheral___registers___bits___definition.html#gae61f8d54923999fffb6db381e81f2b69',1,'stm32f407xx_matlab.h']]], - ['tim_5fcr2_5fois1n_5fmsk_362',['TIM_CR2_OIS1N_Msk',['../group___peripheral___registers___bits___definition.html#ga146f505a2802837aa5799069416206bc',1,'stm32f407xx_matlab.h']]], - ['tim_5fcr2_5fois1n_5fpos_363',['TIM_CR2_OIS1N_Pos',['../group___peripheral___registers___bits___definition.html#ga820e5a3fe5cf4265bc144c8bd697d839',1,'stm32f407xx_matlab.h']]], - ['tim_5fcr2_5fois2_364',['TIM_CR2_OIS2',['../group___peripheral___registers___bits___definition.html#ga61467648a433bd887683b9a4760021fa',1,'stm32f407xx_matlab.h']]], - ['tim_5fcr2_5fois2_5fmsk_365',['TIM_CR2_OIS2_Msk',['../group___peripheral___registers___bits___definition.html#gaeb2bd7f9b2666aa8205981e1c7ddb446',1,'stm32f407xx_matlab.h']]], - ['tim_5fcr2_5fois2_5fpos_366',['TIM_CR2_OIS2_Pos',['../group___peripheral___registers___bits___definition.html#gae7e01ac6a03a0903067f24c11540e2f0',1,'stm32f407xx_matlab.h']]], - ['tim_5fcr2_5fois2n_367',['TIM_CR2_OIS2N',['../group___peripheral___registers___bits___definition.html#ga769146db660b832f3ef26f892b567bd4',1,'stm32f407xx_matlab.h']]], - ['tim_5fcr2_5fois2n_5fmsk_368',['TIM_CR2_OIS2N_Msk',['../group___peripheral___registers___bits___definition.html#ga831140b7e39cda6b158041797be1ed37',1,'stm32f407xx_matlab.h']]], - ['tim_5fcr2_5fois2n_5fpos_369',['TIM_CR2_OIS2N_Pos',['../group___peripheral___registers___bits___definition.html#ga60d70395acf83574da7c53ca126bdd4d',1,'stm32f407xx_matlab.h']]], - ['tim_5fcr2_5fois3_370',['TIM_CR2_OIS3',['../group___peripheral___registers___bits___definition.html#gad974d7c91edf6f1bd47e892b3b6f7565',1,'stm32f407xx_matlab.h']]], - ['tim_5fcr2_5fois3_5fmsk_371',['TIM_CR2_OIS3_Msk',['../group___peripheral___registers___bits___definition.html#ga4d5376e0d45eef0125cf133db5a7189a',1,'stm32f407xx_matlab.h']]], - ['tim_5fcr2_5fois3_5fpos_372',['TIM_CR2_OIS3_Pos',['../group___peripheral___registers___bits___definition.html#gaf56da9ea6f82692b87573a45abab7447',1,'stm32f407xx_matlab.h']]], - ['tim_5fcr2_5fois3n_373',['TIM_CR2_OIS3N',['../group___peripheral___registers___bits___definition.html#ga20fb9b62a7e8d114fbd180abd9f8ceae',1,'stm32f407xx_matlab.h']]], - ['tim_5fcr2_5fois3n_5fmsk_374',['TIM_CR2_OIS3N_Msk',['../group___peripheral___registers___bits___definition.html#gad1c25a6a16e1d0e6e3ae26eac52d8e08',1,'stm32f407xx_matlab.h']]], - ['tim_5fcr2_5fois3n_5fpos_375',['TIM_CR2_OIS3N_Pos',['../group___peripheral___registers___bits___definition.html#ga0849600336151b9eb3a0b405913bdd96',1,'stm32f407xx_matlab.h']]], - ['tim_5fcr2_5fois4_376',['TIM_CR2_OIS4',['../group___peripheral___registers___bits___definition.html#gad644f2f4b26e46587abedc8d3164e56e',1,'stm32f407xx_matlab.h']]], - ['tim_5fcr2_5fois4_5fmsk_377',['TIM_CR2_OIS4_Msk',['../group___peripheral___registers___bits___definition.html#ga8644bc052bc6251ddf877b79a2ef6f48',1,'stm32f407xx_matlab.h']]], - ['tim_5fcr2_5fois4_5fpos_378',['TIM_CR2_OIS4_Pos',['../group___peripheral___registers___bits___definition.html#gab672f9b97f3346360d6d740328a780f7',1,'stm32f407xx_matlab.h']]], - ['tim_5fcr2_5fti1s_379',['TIM_CR2_TI1S',['../group___peripheral___registers___bits___definition.html#gad07504497b70af628fa1aee8fe7ef63c',1,'stm32f407xx_matlab.h']]], - ['tim_5fcr2_5fti1s_5fmsk_380',['TIM_CR2_TI1S_Msk',['../group___peripheral___registers___bits___definition.html#ga5aef7ed878a1f55f901cfdb25d3842ed',1,'stm32f407xx_matlab.h']]], - ['tim_5fcr2_5fti1s_5fpos_381',['TIM_CR2_TI1S_Pos',['../group___peripheral___registers___bits___definition.html#ga493bce1bb3c1243de9e4a9069c261e54',1,'stm32f407xx_matlab.h']]], - ['tim_5fdcr_5fdba_382',['TIM_DCR_DBA',['../group___peripheral___registers___bits___definition.html#gabf9051ecac123cd89f9d2a835e4cde2e',1,'stm32f407xx_matlab.h']]], - ['tim_5fdcr_5fdba_5f0_383',['TIM_DCR_DBA_0',['../group___peripheral___registers___bits___definition.html#gaaaf610e5fe4bb4b10736242df3b62bba',1,'stm32f407xx_matlab.h']]], - ['tim_5fdcr_5fdba_5f1_384',['TIM_DCR_DBA_1',['../group___peripheral___registers___bits___definition.html#ga9a0185643c163930e30f0a1cf5fe364e',1,'stm32f407xx_matlab.h']]], - ['tim_5fdcr_5fdba_5f2_385',['TIM_DCR_DBA_2',['../group___peripheral___registers___bits___definition.html#gaaa5a89b93b97b0968a7d5563a18ab9d1',1,'stm32f407xx_matlab.h']]], - ['tim_5fdcr_5fdba_5f3_386',['TIM_DCR_DBA_3',['../group___peripheral___registers___bits___definition.html#ga105f44ff18cbbd4ff4d60368c9184430',1,'stm32f407xx_matlab.h']]], - ['tim_5fdcr_5fdba_5f4_387',['TIM_DCR_DBA_4',['../group___peripheral___registers___bits___definition.html#gabe1bc4b6dd7265dee2857f23d835b2dc',1,'stm32f407xx_matlab.h']]], - ['tim_5fdcr_5fdba_5fmsk_388',['TIM_DCR_DBA_Msk',['../group___peripheral___registers___bits___definition.html#ga603bd90bfdd7e08fb4c749c926ae8d0d',1,'stm32f407xx_matlab.h']]], - ['tim_5fdcr_5fdba_5fpos_389',['TIM_DCR_DBA_Pos',['../group___peripheral___registers___bits___definition.html#ga3a306a1cb19e8538984d63e2728f18c9',1,'stm32f407xx_matlab.h']]], - ['tim_5fdcr_5fdbl_390',['TIM_DCR_DBL',['../group___peripheral___registers___bits___definition.html#gab9e197a78484567d4c6093c28265f3eb',1,'stm32f407xx_matlab.h']]], - ['tim_5fdcr_5fdbl_5f0_391',['TIM_DCR_DBL_0',['../group___peripheral___registers___bits___definition.html#ga677195c0b4892bb6717564c0528126a9',1,'stm32f407xx_matlab.h']]], - ['tim_5fdcr_5fdbl_5f1_392',['TIM_DCR_DBL_1',['../group___peripheral___registers___bits___definition.html#gad427ba987877e491f7a2be60e320dbea',1,'stm32f407xx_matlab.h']]], - ['tim_5fdcr_5fdbl_5f2_393',['TIM_DCR_DBL_2',['../group___peripheral___registers___bits___definition.html#ga369926f2a8ca5cf635ded9bb4619189c',1,'stm32f407xx_matlab.h']]], - ['tim_5fdcr_5fdbl_5f3_394',['TIM_DCR_DBL_3',['../group___peripheral___registers___bits___definition.html#ga7f1ec849c41d1abd46c528a4ac378c03',1,'stm32f407xx_matlab.h']]], - ['tim_5fdcr_5fdbl_5f4_395',['TIM_DCR_DBL_4',['../group___peripheral___registers___bits___definition.html#ga607d7b87b1b4bf167aabad36f922a8f9',1,'stm32f407xx_matlab.h']]], - ['tim_5fdcr_5fdbl_5fmsk_396',['TIM_DCR_DBL_Msk',['../group___peripheral___registers___bits___definition.html#ga19d5bc5ed6177c1603a35d52918e5068',1,'stm32f407xx_matlab.h']]], - ['tim_5fdcr_5fdbl_5fpos_397',['TIM_DCR_DBL_Pos',['../group___peripheral___registers___bits___definition.html#ga2e78721748388667766590962b29f610',1,'stm32f407xx_matlab.h']]], - ['tim_5fdier_5fbie_398',['TIM_DIER_BIE',['../group___peripheral___registers___bits___definition.html#ga1fcb0d6d9fb7486a5901032fd81aef6a',1,'stm32f407xx_matlab.h']]], - ['tim_5fdier_5fbie_5fmsk_399',['TIM_DIER_BIE_Msk',['../group___peripheral___registers___bits___definition.html#gad054244795a6fcd3bc1ff35e4c651982',1,'stm32f407xx_matlab.h']]], - ['tim_5fdier_5fbie_5fpos_400',['TIM_DIER_BIE_Pos',['../group___peripheral___registers___bits___definition.html#ga68f1acf20b177e729494b03d389fc879',1,'stm32f407xx_matlab.h']]], - ['tim_5fdier_5fcc1de_401',['TIM_DIER_CC1DE',['../group___peripheral___registers___bits___definition.html#gae181bb16ec916aba8ba86f58f745fdfd',1,'stm32f407xx_matlab.h']]], - ['tim_5fdier_5fcc1de_5fmsk_402',['TIM_DIER_CC1DE_Msk',['../group___peripheral___registers___bits___definition.html#ga40247fa7b772b644df2754b599e71e22',1,'stm32f407xx_matlab.h']]], - ['tim_5fdier_5fcc1de_5fpos_403',['TIM_DIER_CC1DE_Pos',['../group___peripheral___registers___bits___definition.html#ga15a2b408f82591fcffc36fb1b71e0ee4',1,'stm32f407xx_matlab.h']]], - ['tim_5fdier_5fcc1ie_404',['TIM_DIER_CC1IE',['../group___peripheral___registers___bits___definition.html#ga1ba7f7ca97eeaf6cc23cd6765c6bf678',1,'stm32f407xx_matlab.h']]], - ['tim_5fdier_5fcc1ie_5fmsk_405',['TIM_DIER_CC1IE_Msk',['../group___peripheral___registers___bits___definition.html#ga9cdfb1dc6e58a5f1ba2e4379b02f8be7',1,'stm32f407xx_matlab.h']]], - ['tim_5fdier_5fcc1ie_5fpos_406',['TIM_DIER_CC1IE_Pos',['../group___peripheral___registers___bits___definition.html#ga0ca1de767246ce92802bca84ae436364',1,'stm32f407xx_matlab.h']]], - ['tim_5fdier_5fcc2de_407',['TIM_DIER_CC2DE',['../group___peripheral___registers___bits___definition.html#ga58f97064991095b28c91028ca3cca28e',1,'stm32f407xx_matlab.h']]], - ['tim_5fdier_5fcc2de_5fmsk_408',['TIM_DIER_CC2DE_Msk',['../group___peripheral___registers___bits___definition.html#ga74a3a6d017bcc45df793e9b1d19c013d',1,'stm32f407xx_matlab.h']]], - ['tim_5fdier_5fcc2de_5fpos_409',['TIM_DIER_CC2DE_Pos',['../group___peripheral___registers___bits___definition.html#ga567e807487bdcf4d7db0c50c02154420',1,'stm32f407xx_matlab.h']]], - ['tim_5fdier_5fcc2ie_410',['TIM_DIER_CC2IE',['../group___peripheral___registers___bits___definition.html#ga757c59b690770adebf33e20d3d9dec15',1,'stm32f407xx_matlab.h']]], - ['tim_5fdier_5fcc2ie_5fmsk_411',['TIM_DIER_CC2IE_Msk',['../group___peripheral___registers___bits___definition.html#ga5db58d01a8e92e3403fb44ecc09e5e5e',1,'stm32f407xx_matlab.h']]], - ['tim_5fdier_5fcc2ie_5fpos_412',['TIM_DIER_CC2IE_Pos',['../group___peripheral___registers___bits___definition.html#gab5dcc06e124f3980a1d8a949787acc90',1,'stm32f407xx_matlab.h']]], - ['tim_5fdier_5fcc3de_413',['TIM_DIER_CC3DE',['../group___peripheral___registers___bits___definition.html#ga1567bff5dc0564b26a8b3cff1f0fe0a4',1,'stm32f407xx_matlab.h']]], - ['tim_5fdier_5fcc3de_5fmsk_414',['TIM_DIER_CC3DE_Msk',['../group___peripheral___registers___bits___definition.html#gade4d3ce6b292c28e2fd7c9e9bd8f6ab6',1,'stm32f407xx_matlab.h']]], - ['tim_5fdier_5fcc3de_5fpos_415',['TIM_DIER_CC3DE_Pos',['../group___peripheral___registers___bits___definition.html#ga3e08651981fedc16b1ed9925c4f84373',1,'stm32f407xx_matlab.h']]], - ['tim_5fdier_5fcc3ie_416',['TIM_DIER_CC3IE',['../group___peripheral___registers___bits___definition.html#ga4edf003f04bcf250bddf5ed284201c2e',1,'stm32f407xx_matlab.h']]], - ['tim_5fdier_5fcc3ie_5fmsk_417',['TIM_DIER_CC3IE_Msk',['../group___peripheral___registers___bits___definition.html#ga78bd5f90a0f2d2d34132ef5568e18779',1,'stm32f407xx_matlab.h']]], - ['tim_5fdier_5fcc3ie_5fpos_418',['TIM_DIER_CC3IE_Pos',['../group___peripheral___registers___bits___definition.html#gae3a26f9fd83be5be909cdbbf59fb138d',1,'stm32f407xx_matlab.h']]], - ['tim_5fdier_5fcc4de_419',['TIM_DIER_CC4DE',['../group___peripheral___registers___bits___definition.html#gaaba034412c54fa07024e516492748614',1,'stm32f407xx_matlab.h']]], - ['tim_5fdier_5fcc4de_5fmsk_420',['TIM_DIER_CC4DE_Msk',['../group___peripheral___registers___bits___definition.html#gad81dbfb6c7c8907ec2debd892b48e9ba',1,'stm32f407xx_matlab.h']]], - ['tim_5fdier_5fcc4de_5fpos_421',['TIM_DIER_CC4DE_Pos',['../group___peripheral___registers___bits___definition.html#ga4c72cedbdd1f3c2390f25bb181b76b39',1,'stm32f407xx_matlab.h']]], - ['tim_5fdier_5fcc4ie_422',['TIM_DIER_CC4IE',['../group___peripheral___registers___bits___definition.html#ga6ad0f562a014572793b49fe87184338b',1,'stm32f407xx_matlab.h']]], - ['tim_5fdier_5fcc4ie_5fmsk_423',['TIM_DIER_CC4IE_Msk',['../group___peripheral___registers___bits___definition.html#ga66b5230621c6d2f44c44ff672a07ffaf',1,'stm32f407xx_matlab.h']]], - ['tim_5fdier_5fcc4ie_5fpos_424',['TIM_DIER_CC4IE_Pos',['../group___peripheral___registers___bits___definition.html#gac98032297756f6e341f92fa243278e98',1,'stm32f407xx_matlab.h']]], - ['tim_5fdier_5fcomde_425',['TIM_DIER_COMDE',['../group___peripheral___registers___bits___definition.html#ga79c3fab9d33de953a0a7f7d6516c73bc',1,'stm32f407xx_matlab.h']]], - ['tim_5fdier_5fcomde_5fmsk_426',['TIM_DIER_COMDE_Msk',['../group___peripheral___registers___bits___definition.html#ga9ed00410aeabe33fef5feebbaec1a0a6',1,'stm32f407xx_matlab.h']]], - ['tim_5fdier_5fcomde_5fpos_427',['TIM_DIER_COMDE_Pos',['../group___peripheral___registers___bits___definition.html#ga0311dbc32a6e1b38dd0e6a5a7ae6c4ed',1,'stm32f407xx_matlab.h']]], - ['tim_5fdier_5fcomie_428',['TIM_DIER_COMIE',['../group___peripheral___registers___bits___definition.html#gade8a374e04740aac1ece248b868522fe',1,'stm32f407xx_matlab.h']]], - ['tim_5fdier_5fcomie_5fmsk_429',['TIM_DIER_COMIE_Msk',['../group___peripheral___registers___bits___definition.html#gabe9af339214666b3251fff9598277b1f',1,'stm32f407xx_matlab.h']]], - ['tim_5fdier_5fcomie_5fpos_430',['TIM_DIER_COMIE_Pos',['../group___peripheral___registers___bits___definition.html#ga2f87983f6cb8450b975286079c19ff29',1,'stm32f407xx_matlab.h']]], - ['tim_5fdier_5ftde_431',['TIM_DIER_TDE',['../group___peripheral___registers___bits___definition.html#ga5a752d4295f100708df9b8be5a7f439d',1,'stm32f407xx_matlab.h']]], - ['tim_5fdier_5ftde_5fmsk_432',['TIM_DIER_TDE_Msk',['../group___peripheral___registers___bits___definition.html#gadbd5aee3b64fd928be288ae86b4fa020',1,'stm32f407xx_matlab.h']]], - ['tim_5fdier_5ftde_5fpos_433',['TIM_DIER_TDE_Pos',['../group___peripheral___registers___bits___definition.html#ga8b1014527f96f63edc7dfa3b79297557',1,'stm32f407xx_matlab.h']]], - ['tim_5fdier_5ftie_434',['TIM_DIER_TIE',['../group___peripheral___registers___bits___definition.html#gaa755fef2c4e96c63f2ea1cd9a32f956a',1,'stm32f407xx_matlab.h']]], - ['tim_5fdier_5ftie_5fmsk_435',['TIM_DIER_TIE_Msk',['../group___peripheral___registers___bits___definition.html#gadf3e781c907ca4774fae5c089e445f5a',1,'stm32f407xx_matlab.h']]], - ['tim_5fdier_5ftie_5fpos_436',['TIM_DIER_TIE_Pos',['../group___peripheral___registers___bits___definition.html#gaa348f21e19ac18be00577cc2844941d6',1,'stm32f407xx_matlab.h']]], - ['tim_5fdier_5fude_437',['TIM_DIER_UDE',['../group___peripheral___registers___bits___definition.html#gab9f47792b1c2f123464a2955f445c811',1,'stm32f407xx_matlab.h']]], - ['tim_5fdier_5fude_5fmsk_438',['TIM_DIER_UDE_Msk',['../group___peripheral___registers___bits___definition.html#ga66544291fb58960e9f4018509a4dee09',1,'stm32f407xx_matlab.h']]], - ['tim_5fdier_5fude_5fpos_439',['TIM_DIER_UDE_Pos',['../group___peripheral___registers___bits___definition.html#ga5078f4d6a9f542a502194cd1499f90a3',1,'stm32f407xx_matlab.h']]], - ['tim_5fdier_5fuie_440',['TIM_DIER_UIE',['../group___peripheral___registers___bits___definition.html#ga5c6d3e0495e6c06da4bdd0ad8995a32b',1,'stm32f407xx_matlab.h']]], - ['tim_5fdier_5fuie_5fmsk_441',['TIM_DIER_UIE_Msk',['../group___peripheral___registers___bits___definition.html#gab47c8f36981860ff345f922f6ba02662',1,'stm32f407xx_matlab.h']]], - ['tim_5fdier_5fuie_5fpos_442',['TIM_DIER_UIE_Pos',['../group___peripheral___registers___bits___definition.html#ga177019595c3a462255e7ea4a64cde2a6',1,'stm32f407xx_matlab.h']]], - ['tim_5fdmar_5fdmab_443',['TIM_DMAR_DMAB',['../group___peripheral___registers___bits___definition.html#ga1afa2fc02bcd75c15122c4eb87d6cf83',1,'stm32f407xx_matlab.h']]], - ['tim_5fdmar_5fdmab_5fmsk_444',['TIM_DMAR_DMAB_Msk',['../group___peripheral___registers___bits___definition.html#gaa5d6d71391fa416ce5c1aa65e459d92a',1,'stm32f407xx_matlab.h']]], - ['tim_5fdmar_5fdmab_5fpos_445',['TIM_DMAR_DMAB_Pos',['../group___peripheral___registers___bits___definition.html#ga404a796ef83390218d4aed467f779ca0',1,'stm32f407xx_matlab.h']]], - ['tim_5fegr_5fbg_446',['TIM_EGR_BG',['../group___peripheral___registers___bits___definition.html#ga08c5635a0ac0ce5618485319a4fa0f18',1,'stm32f407xx_matlab.h']]], - ['tim_5fegr_5fbg_5fmsk_447',['TIM_EGR_BG_Msk',['../group___peripheral___registers___bits___definition.html#ga3cbac05839c59f31bd13664890685941',1,'stm32f407xx_matlab.h']]], - ['tim_5fegr_5fbg_5fpos_448',['TIM_EGR_BG_Pos',['../group___peripheral___registers___bits___definition.html#ga068531a673c44015bef074e6c926ce77',1,'stm32f407xx_matlab.h']]], - ['tim_5fegr_5fcc1g_449',['TIM_EGR_CC1G',['../group___peripheral___registers___bits___definition.html#ga0a1318609761df5de5213e9e75b5aa6a',1,'stm32f407xx_matlab.h']]], - ['tim_5fegr_5fcc1g_5fmsk_450',['TIM_EGR_CC1G_Msk',['../group___peripheral___registers___bits___definition.html#gaba7a2fa9e7341df84a32cf5d54e61ad3',1,'stm32f407xx_matlab.h']]], - ['tim_5fegr_5fcc1g_5fpos_451',['TIM_EGR_CC1G_Pos',['../group___peripheral___registers___bits___definition.html#gaee06d20dfa5d132d221a28193dedd211',1,'stm32f407xx_matlab.h']]], - ['tim_5fegr_5fcc2g_452',['TIM_EGR_CC2G',['../group___peripheral___registers___bits___definition.html#ga5423de00e86aeb8a4657a509af485055',1,'stm32f407xx_matlab.h']]], - ['tim_5fegr_5fcc2g_5fmsk_453',['TIM_EGR_CC2G_Msk',['../group___peripheral___registers___bits___definition.html#gacfa4c983163836490441a78e7bf89b67',1,'stm32f407xx_matlab.h']]], - ['tim_5fegr_5fcc2g_5fpos_454',['TIM_EGR_CC2G_Pos',['../group___peripheral___registers___bits___definition.html#ga49003c85e8c92b159faee96d1c6a8cea',1,'stm32f407xx_matlab.h']]], - ['tim_5fegr_5fcc3g_455',['TIM_EGR_CC3G',['../group___peripheral___registers___bits___definition.html#ga064d2030abccc099ded418fd81d6aa07',1,'stm32f407xx_matlab.h']]], - ['tim_5fegr_5fcc3g_5fmsk_456',['TIM_EGR_CC3G_Msk',['../group___peripheral___registers___bits___definition.html#gab73c2e5ea59b860e342d2ea5f99ff672',1,'stm32f407xx_matlab.h']]], - ['tim_5fegr_5fcc3g_5fpos_457',['TIM_EGR_CC3G_Pos',['../group___peripheral___registers___bits___definition.html#ga8006ffc22a9a37d21364e8023d7eb145',1,'stm32f407xx_matlab.h']]], - ['tim_5fegr_5fcc4g_458',['TIM_EGR_CC4G',['../group___peripheral___registers___bits___definition.html#ga1c4e5555dd3be8ab1e631d1053f4a305',1,'stm32f407xx_matlab.h']]], - ['tim_5fegr_5fcc4g_5fmsk_459',['TIM_EGR_CC4G_Msk',['../group___peripheral___registers___bits___definition.html#ga8ae87478438e43366db04ac05db1db0e',1,'stm32f407xx_matlab.h']]], - ['tim_5fegr_5fcc4g_5fpos_460',['TIM_EGR_CC4G_Pos',['../group___peripheral___registers___bits___definition.html#ga49b4e300af06da863900ba29d894eb26',1,'stm32f407xx_matlab.h']]], - ['tim_5fegr_5fcomg_461',['TIM_EGR_COMG',['../group___peripheral___registers___bits___definition.html#gadb06f8bb364307695c7d6a028391de7b',1,'stm32f407xx_matlab.h']]], - ['tim_5fegr_5fcomg_5fmsk_462',['TIM_EGR_COMG_Msk',['../group___peripheral___registers___bits___definition.html#gab04646da2ee78ff6e2d4c483c8050d20',1,'stm32f407xx_matlab.h']]], - ['tim_5fegr_5fcomg_5fpos_463',['TIM_EGR_COMG_Pos',['../group___peripheral___registers___bits___definition.html#ga235c6ad9b108e6640f0c3fb7b3b9e278',1,'stm32f407xx_matlab.h']]], - ['tim_5fegr_5ftg_464',['TIM_EGR_TG',['../group___peripheral___registers___bits___definition.html#ga2eabface433d6adaa2dee3df49852585',1,'stm32f407xx_matlab.h']]], - ['tim_5fegr_5ftg_5fmsk_465',['TIM_EGR_TG_Msk',['../group___peripheral___registers___bits___definition.html#gaedb01f674152f674c87c21b6147963d5',1,'stm32f407xx_matlab.h']]], - ['tim_5fegr_5ftg_5fpos_466',['TIM_EGR_TG_Pos',['../group___peripheral___registers___bits___definition.html#gad68094deb44a74ef649c243ec840b9a2',1,'stm32f407xx_matlab.h']]], - ['tim_5fegr_5fug_467',['TIM_EGR_UG',['../group___peripheral___registers___bits___definition.html#ga16f52a8e9aad153223405b965566ae91',1,'stm32f407xx_matlab.h']]], - ['tim_5fegr_5fug_5fmsk_468',['TIM_EGR_UG_Msk',['../group___peripheral___registers___bits___definition.html#ga5ff315da1492025d608eb2c71e1e4462',1,'stm32f407xx_matlab.h']]], - ['tim_5fegr_5fug_5fpos_469',['TIM_EGR_UG_Pos',['../group___peripheral___registers___bits___definition.html#ga71cd5b80d699afa003cb407a74dc0593',1,'stm32f407xx_matlab.h']]], - ['tim_5focmode_5fsecond_5fshift_470',['TIM_OCMODE_SECOND_SHIFT',['../group___t_i_m___s_i_m_u_l_a_t_o_r.html#gae44a51b8c43872a8186ef4740d8f83d4',1,'stm32f4xx_matlab_tim.h']]], - ['tim_5for_5fitr1_5frmp_471',['TIM_OR_ITR1_RMP',['../group___peripheral___registers___bits___definition.html#ga4f413eac7f503dfddc9a9914efa555ac',1,'stm32f407xx_matlab.h']]], - ['tim_5for_5fitr1_5frmp_5f0_472',['TIM_OR_ITR1_RMP_0',['../group___peripheral___registers___bits___definition.html#gad7141f22c81a83134d9bb35cdeca5549',1,'stm32f407xx_matlab.h']]], - ['tim_5for_5fitr1_5frmp_5f1_473',['TIM_OR_ITR1_RMP_1',['../group___peripheral___registers___bits___definition.html#ga7ba54d02d962d04d2bdf16df11c7ccd0',1,'stm32f407xx_matlab.h']]], - ['tim_5for_5fitr1_5frmp_5fmsk_474',['TIM_OR_ITR1_RMP_Msk',['../group___peripheral___registers___bits___definition.html#ga8bc0672804e61da192e6063e0bb82ed3',1,'stm32f407xx_matlab.h']]], - ['tim_5for_5fitr1_5frmp_5fpos_475',['TIM_OR_ITR1_RMP_Pos',['../group___peripheral___registers___bits___definition.html#ga50c5d626671e911a5d0943e6477e4aa7',1,'stm32f407xx_matlab.h']]], - ['tim_5for_5fti1_5frmp_476',['TIM_OR_TI1_RMP',['../group___peripheral___registers___bits___definition.html#gacd0ec0e64e354c9670015c91aaf54c2e',1,'stm32f407xx_matlab.h']]], - ['tim_5for_5fti1_5frmp_5f0_477',['TIM_OR_TI1_RMP_0',['../group___peripheral___registers___bits___definition.html#ga59fa1246d851959d5231b5b0796fd3a5',1,'stm32f407xx_matlab.h']]], - ['tim_5for_5fti1_5frmp_5f1_478',['TIM_OR_TI1_RMP_1',['../group___peripheral___registers___bits___definition.html#ga98d9cdc55111a548e48df0819922852b',1,'stm32f407xx_matlab.h']]], - ['tim_5for_5fti1_5frmp_5fmsk_479',['TIM_OR_TI1_RMP_Msk',['../group___peripheral___registers___bits___definition.html#ga3e8ec8a0faf4bc51e04f909e3b13708e',1,'stm32f407xx_matlab.h']]], - ['tim_5for_5fti1_5frmp_5fpos_480',['TIM_OR_TI1_RMP_Pos',['../group___peripheral___registers___bits___definition.html#ga3f62ec5e16705319b0d7ecdc54471788',1,'stm32f407xx_matlab.h']]], - ['tim_5for_5fti4_5frmp_481',['TIM_OR_TI4_RMP',['../group___peripheral___registers___bits___definition.html#ga2916847c3545c06578d7ba8c381a4c20',1,'stm32f407xx_matlab.h']]], - ['tim_5for_5fti4_5frmp_5f0_482',['TIM_OR_TI4_RMP_0',['../group___peripheral___registers___bits___definition.html#ga9aea4f8a0abedbf08bb1e686933c1120',1,'stm32f407xx_matlab.h']]], - ['tim_5for_5fti4_5frmp_5f1_483',['TIM_OR_TI4_RMP_1',['../group___peripheral___registers___bits___definition.html#gaa2a46aa18f15f2074b93233a18e85629',1,'stm32f407xx_matlab.h']]], - ['tim_5for_5fti4_5frmp_5fmsk_484',['TIM_OR_TI4_RMP_Msk',['../group___peripheral___registers___bits___definition.html#gaef046d565911337566adcc67904847ea',1,'stm32f407xx_matlab.h']]], - ['tim_5for_5fti4_5frmp_5fpos_485',['TIM_OR_TI4_RMP_Pos',['../group___peripheral___registers___bits___definition.html#gaaecd8b0b125d46d02c35f990903d6fcb',1,'stm32f407xx_matlab.h']]], - ['tim_5fpsc_5fpsc_486',['TIM_PSC_PSC',['../group___peripheral___registers___bits___definition.html#gaefb85e4000ddab0ada67c5964810da35',1,'stm32f407xx_matlab.h']]], - ['tim_5fpsc_5fpsc_5fmsk_487',['TIM_PSC_PSC_Msk',['../group___peripheral___registers___bits___definition.html#gacff3a421342fafac2e25421084bd85df',1,'stm32f407xx_matlab.h']]], - ['tim_5fpsc_5fpsc_5fpos_488',['TIM_PSC_PSC_Pos',['../group___peripheral___registers___bits___definition.html#gac11163ae1ef14d3e7a1f047c40a501f4',1,'stm32f407xx_matlab.h']]], - ['tim_5frcr_5frep_489',['TIM_RCR_REP',['../group___peripheral___registers___bits___definition.html#gadcef8f28580e36cdfda3be1f7561afc7',1,'stm32f407xx_matlab.h']]], - ['tim_5frcr_5frep_5fmsk_490',['TIM_RCR_REP_Msk',['../group___peripheral___registers___bits___definition.html#ga06e8380ec8ac6138f401fa53833978fc',1,'stm32f407xx_matlab.h']]], - ['tim_5frcr_5frep_5fpos_491',['TIM_RCR_REP_Pos',['../group___peripheral___registers___bits___definition.html#gab062a3ee5ed93cef0fd1de937719fe5c',1,'stm32f407xx_matlab.h']]], - ['tim_5fsim_492',['TIM_Sim',['../struct_t_i_m___sim.html',1,'']]], - ['tim_5fsim_5fdeinit_493',['TIM_SIM_DEINIT',['../group___t_i_m___s_i_m_u_l_a_t_o_r.html#ga52ac5ac026ea57787d19cd1a8611abba',1,'TIM_SIM_DEINIT(void): stm32f4xx_matlab_tim.c'],['../group___t_i_m___s_i_m_u_l_a_t_o_r.html#ga52ac5ac026ea57787d19cd1a8611abba',1,'TIM_SIM_DEINIT(void): stm32f4xx_matlab_tim.c']]], - ['tim_5fsimulation_494',['TIM_Simulation',['../group___t_i_m___s_i_m_u_l_a_t_o_r.html#ga3fcb4dd48557c21fdd6c379ad16bd229',1,'TIM_Simulation(TIM_TypeDef *TIMx, struct TIM_Sim *TIMS): stm32f4xx_matlab_tim.c'],['../group___t_i_m___s_i_m_u_l_a_t_o_r.html#ga3fcb4dd48557c21fdd6c379ad16bd229',1,'TIM_Simulation(TIM_TypeDef *TIMx, struct TIM_Sim *TIMS): stm32f4xx_matlab_tim.c']]], - ['tim_5fsimulator_495',['TIM_SIMULATOR',['../group___t_i_m___s_i_m_u_l_a_t_o_r.html',1,'']]], - ['tim_5fsmcr_5fece_496',['TIM_SMCR_ECE',['../group___peripheral___registers___bits___definition.html#ga331a1d5f39d5f47b5409054e693fc651',1,'stm32f407xx_matlab.h']]], - ['tim_5fsmcr_5fece_5fmsk_497',['TIM_SMCR_ECE_Msk',['../group___peripheral___registers___bits___definition.html#ga7322ee5f5ebf6e9c70b7ffe4afe1fa3d',1,'stm32f407xx_matlab.h']]], - ['tim_5fsmcr_5fece_5fpos_498',['TIM_SMCR_ECE_Pos',['../group___peripheral___registers___bits___definition.html#gaaef2d4adcfd438a4d19ea54ef7031ed0',1,'stm32f407xx_matlab.h']]], - ['tim_5fsmcr_5fetf_499',['TIM_SMCR_ETF',['../group___peripheral___registers___bits___definition.html#gae2ed8b32d9eb8eea251bd1dac4f34668',1,'stm32f407xx_matlab.h']]], - ['tim_5fsmcr_5fetf_5f0_500',['TIM_SMCR_ETF_0',['../group___peripheral___registers___bits___definition.html#ga43745c2894cfc1e5ee619ac85d8d5a62',1,'stm32f407xx_matlab.h']]], - ['tim_5fsmcr_5fetf_5f1_501',['TIM_SMCR_ETF_1',['../group___peripheral___registers___bits___definition.html#ga661e6cce23553cf0ad3a60d8573b9a2c',1,'stm32f407xx_matlab.h']]], - ['tim_5fsmcr_5fetf_5f2_502',['TIM_SMCR_ETF_2',['../group___peripheral___registers___bits___definition.html#gafb5528381fb64ffbcc719de478391ae2',1,'stm32f407xx_matlab.h']]], - ['tim_5fsmcr_5fetf_5f3_503',['TIM_SMCR_ETF_3',['../group___peripheral___registers___bits___definition.html#ga6082700946fc61a6f9d6209e258fcc14',1,'stm32f407xx_matlab.h']]], - ['tim_5fsmcr_5fetf_5fmsk_504',['TIM_SMCR_ETF_Msk',['../group___peripheral___registers___bits___definition.html#ga423e64cbb40275055b1b92a6d3ab0a12',1,'stm32f407xx_matlab.h']]], - ['tim_5fsmcr_5fetf_5fpos_505',['TIM_SMCR_ETF_Pos',['../group___peripheral___registers___bits___definition.html#gafbb493ebc2ecb4f3759eb97f9496a1dd',1,'stm32f407xx_matlab.h']]], - ['tim_5fsmcr_5fetp_506',['TIM_SMCR_ETP',['../group___peripheral___registers___bits___definition.html#ga2a5f335c3d7a4f82d1e91dc1511e3322',1,'stm32f407xx_matlab.h']]], - ['tim_5fsmcr_5fetp_5fmsk_507',['TIM_SMCR_ETP_Msk',['../group___peripheral___registers___bits___definition.html#ga77f8984e6ac3422454b0a586a2b973e3',1,'stm32f407xx_matlab.h']]], - ['tim_5fsmcr_5fetp_5fpos_508',['TIM_SMCR_ETP_Pos',['../group___peripheral___registers___bits___definition.html#gada5b5864ba9fe393be0bcd168e3cf439',1,'stm32f407xx_matlab.h']]], - ['tim_5fsmcr_5fetps_509',['TIM_SMCR_ETPS',['../group___peripheral___registers___bits___definition.html#ga0ebb9e631876435e276211d88e797386',1,'stm32f407xx_matlab.h']]], - ['tim_5fsmcr_5fetps_5f0_510',['TIM_SMCR_ETPS_0',['../group___peripheral___registers___bits___definition.html#ga00b43cd09557a69ed10471ed76b228d8',1,'stm32f407xx_matlab.h']]], - ['tim_5fsmcr_5fetps_5f1_511',['TIM_SMCR_ETPS_1',['../group___peripheral___registers___bits___definition.html#gabf12f04862dbc92ca238d1518b27b16b',1,'stm32f407xx_matlab.h']]], - ['tim_5fsmcr_5fetps_5fmsk_512',['TIM_SMCR_ETPS_Msk',['../group___peripheral___registers___bits___definition.html#gab319df2e386dc55f421f20a7f4c8a5d4',1,'stm32f407xx_matlab.h']]], - ['tim_5fsmcr_5fetps_5fpos_513',['TIM_SMCR_ETPS_Pos',['../group___peripheral___registers___bits___definition.html#gac0f059d7026ed8c8b644ec62d416323b',1,'stm32f407xx_matlab.h']]], - ['tim_5fsmcr_5fmsm_514',['TIM_SMCR_MSM',['../group___peripheral___registers___bits___definition.html#ga52101db4ca2c7b3003f1b16a49b2032c',1,'stm32f407xx_matlab.h']]], - ['tim_5fsmcr_5fmsm_5fmsk_515',['TIM_SMCR_MSM_Msk',['../group___peripheral___registers___bits___definition.html#gafba3fb13f79aeb124c0f496bef33e4b2',1,'stm32f407xx_matlab.h']]], - ['tim_5fsmcr_5fmsm_5fpos_516',['TIM_SMCR_MSM_Pos',['../group___peripheral___registers___bits___definition.html#ga904f429175a5ab1cfb78af1487d8b187',1,'stm32f407xx_matlab.h']]], - ['tim_5fsmcr_5fsms_517',['TIM_SMCR_SMS',['../group___peripheral___registers___bits___definition.html#gae92349731a6107e0f3a251b44a67c7ea',1,'stm32f407xx_matlab.h']]], - ['tim_5fsmcr_5fsms_5f0_518',['TIM_SMCR_SMS_0',['../group___peripheral___registers___bits___definition.html#ga7d1ebece401aeb12abd466d2eafa78b2',1,'stm32f407xx_matlab.h']]], - ['tim_5fsmcr_5fsms_5f1_519',['TIM_SMCR_SMS_1',['../group___peripheral___registers___bits___definition.html#gaa980a3121ab6cda5a4a42b959da8421e',1,'stm32f407xx_matlab.h']]], - ['tim_5fsmcr_5fsms_5f2_520',['TIM_SMCR_SMS_2',['../group___peripheral___registers___bits___definition.html#ga63847fc3c71f582403e6301b1229c3ed',1,'stm32f407xx_matlab.h']]], - ['tim_5fsmcr_5fsms_5fmsk_521',['TIM_SMCR_SMS_Msk',['../group___peripheral___registers___bits___definition.html#ga34db507d082a38eb597b9a27bb659ace',1,'stm32f407xx_matlab.h']]], - ['tim_5fsmcr_5fsms_5fpos_522',['TIM_SMCR_SMS_Pos',['../group___peripheral___registers___bits___definition.html#ga40905e02ce0cff7e929a9e78e7f46bcb',1,'stm32f407xx_matlab.h']]], - ['tim_5fsmcr_5fts_523',['TIM_SMCR_TS',['../group___peripheral___registers___bits___definition.html#ga8680e719bca2b672d850504220ae51fc',1,'stm32f407xx_matlab.h']]], - ['tim_5fsmcr_5fts_5f0_524',['TIM_SMCR_TS_0',['../group___peripheral___registers___bits___definition.html#ga8d1f040f9259acb3c2fba7b0c7eb3d96',1,'stm32f407xx_matlab.h']]], - ['tim_5fsmcr_5fts_5f1_525',['TIM_SMCR_TS_1',['../group___peripheral___registers___bits___definition.html#gacb82212fcc89166a43ff97542da9182d',1,'stm32f407xx_matlab.h']]], - ['tim_5fsmcr_5fts_5f2_526',['TIM_SMCR_TS_2',['../group___peripheral___registers___bits___definition.html#gacf0dbaf4a2ec8759f283f82a958ef6a8',1,'stm32f407xx_matlab.h']]], - ['tim_5fsmcr_5fts_5fmsk_527',['TIM_SMCR_TS_Msk',['../group___peripheral___registers___bits___definition.html#ga2aa1e898f53a002c3bddaa336e8888b1',1,'stm32f407xx_matlab.h']]], - ['tim_5fsmcr_5fts_5fpos_528',['TIM_SMCR_TS_Pos',['../group___peripheral___registers___bits___definition.html#gafcaa765c40260187fc144e9e8138cc4b',1,'stm32f407xx_matlab.h']]], - ['tim_5fsr_5fbif_529',['TIM_SR_BIF',['../group___peripheral___registers___bits___definition.html#ga6d52cd5a57c9a26b0d993c93d9875097',1,'stm32f407xx_matlab.h']]], - ['tim_5fsr_5fbif_5fmsk_530',['TIM_SR_BIF_Msk',['../group___peripheral___registers___bits___definition.html#ga778093c3983d94f88d6da49de96c9826',1,'stm32f407xx_matlab.h']]], - ['tim_5fsr_5fbif_5fpos_531',['TIM_SR_BIF_Pos',['../group___peripheral___registers___bits___definition.html#ga61bc5fc1383047eb82dd66cb44a52ff3',1,'stm32f407xx_matlab.h']]], - ['tim_5fsr_5fcc1if_532',['TIM_SR_CC1IF',['../group___peripheral___registers___bits___definition.html#ga449a61344a97608d85384c29f003c0e9',1,'stm32f407xx_matlab.h']]], - ['tim_5fsr_5fcc1if_5fmsk_533',['TIM_SR_CC1IF_Msk',['../group___peripheral___registers___bits___definition.html#ga2ce1be8a563567338d87977ddc0aa2c5',1,'stm32f407xx_matlab.h']]], - ['tim_5fsr_5fcc1if_5fpos_534',['TIM_SR_CC1IF_Pos',['../group___peripheral___registers___bits___definition.html#ga61c518804171ea0813d7dd5702adde4c',1,'stm32f407xx_matlab.h']]], - ['tim_5fsr_5fcc1of_535',['TIM_SR_CC1OF',['../group___peripheral___registers___bits___definition.html#ga819c4b27f8fa99b537c4407521f9780c',1,'stm32f407xx_matlab.h']]], - ['tim_5fsr_5fcc1of_5fmsk_536',['TIM_SR_CC1OF_Msk',['../group___peripheral___registers___bits___definition.html#gae38020b672e525cf31f3a21a01ee680f',1,'stm32f407xx_matlab.h']]], - ['tim_5fsr_5fcc1of_5fpos_537',['TIM_SR_CC1OF_Pos',['../group___peripheral___registers___bits___definition.html#ga6d3dd0efe5e5b6c21a10091bbb61d2c6',1,'stm32f407xx_matlab.h']]], - ['tim_5fsr_5fcc2if_538',['TIM_SR_CC2IF',['../group___peripheral___registers___bits___definition.html#ga25a48bf099467169aa50464fbf462bd8',1,'stm32f407xx_matlab.h']]], - ['tim_5fsr_5fcc2if_5fmsk_539',['TIM_SR_CC2IF_Msk',['../group___peripheral___registers___bits___definition.html#gac970c8ac8779185ba8f313e280c40902',1,'stm32f407xx_matlab.h']]], - ['tim_5fsr_5fcc2if_5fpos_540',['TIM_SR_CC2IF_Pos',['../group___peripheral___registers___bits___definition.html#gaef088105198e8850e542fc8e0fd362ae',1,'stm32f407xx_matlab.h']]], - ['tim_5fsr_5fcc2of_541',['TIM_SR_CC2OF',['../group___peripheral___registers___bits___definition.html#ga3b7798da5863d559ea9a642af6658050',1,'stm32f407xx_matlab.h']]], - ['tim_5fsr_5fcc2of_5fmsk_542',['TIM_SR_CC2OF_Msk',['../group___peripheral___registers___bits___definition.html#ga772886dce929789865cf7053728488d4',1,'stm32f407xx_matlab.h']]], - ['tim_5fsr_5fcc2of_5fpos_543',['TIM_SR_CC2OF_Pos',['../group___peripheral___registers___bits___definition.html#ga9a0188211bdf0406c2712d92e7d644c3',1,'stm32f407xx_matlab.h']]], - ['tim_5fsr_5fcc3if_544',['TIM_SR_CC3IF',['../group___peripheral___registers___bits___definition.html#gad3cf234a1059c0a04799e88382cdc0f2',1,'stm32f407xx_matlab.h']]], - ['tim_5fsr_5fcc3if_5fmsk_545',['TIM_SR_CC3IF_Msk',['../group___peripheral___registers___bits___definition.html#ga77b2e69acc55c8d12f789fc5bf9a5f54',1,'stm32f407xx_matlab.h']]], - ['tim_5fsr_5fcc3if_5fpos_546',['TIM_SR_CC3IF_Pos',['../group___peripheral___registers___bits___definition.html#gad9d4e629577fc5a15dd907a0a2d6f43a',1,'stm32f407xx_matlab.h']]], - ['tim_5fsr_5fcc3of_547',['TIM_SR_CC3OF',['../group___peripheral___registers___bits___definition.html#gaf7a2d4c831eb641ba082156e41d03358',1,'stm32f407xx_matlab.h']]], - ['tim_5fsr_5fcc3of_5fmsk_548',['TIM_SR_CC3OF_Msk',['../group___peripheral___registers___bits___definition.html#ga36d466016b806136b3e0251363e7e38d',1,'stm32f407xx_matlab.h']]], - ['tim_5fsr_5fcc3of_5fpos_549',['TIM_SR_CC3OF_Pos',['../group___peripheral___registers___bits___definition.html#ga131fff23ae52a9ae98267f06f35b9abb',1,'stm32f407xx_matlab.h']]], - ['tim_5fsr_5fcc4if_550',['TIM_SR_CC4IF',['../group___peripheral___registers___bits___definition.html#gacade8a06303bf216bfb03140c7e16cac',1,'stm32f407xx_matlab.h']]], - ['tim_5fsr_5fcc4if_5fmsk_551',['TIM_SR_CC4IF_Msk',['../group___peripheral___registers___bits___definition.html#ga62087fa2c5fa8166d6b4be7e32c60442',1,'stm32f407xx_matlab.h']]], - ['tim_5fsr_5fcc4if_5fpos_552',['TIM_SR_CC4IF_Pos',['../group___peripheral___registers___bits___definition.html#ga1f5a114b99523c3f6766951ab28026f9',1,'stm32f407xx_matlab.h']]], - ['tim_5fsr_5fcc4of_553',['TIM_SR_CC4OF',['../group___peripheral___registers___bits___definition.html#ga81ba979e8309b66808e06e4de34bc740',1,'stm32f407xx_matlab.h']]], - ['tim_5fsr_5fcc4of_5fmsk_554',['TIM_SR_CC4OF_Msk',['../group___peripheral___registers___bits___definition.html#ga36421d430d4fd0d34d02444b5da804b5',1,'stm32f407xx_matlab.h']]], - ['tim_5fsr_5fcc4of_5fpos_555',['TIM_SR_CC4OF_Pos',['../group___peripheral___registers___bits___definition.html#gaa692368f903e95550c110a8cdbece996',1,'stm32f407xx_matlab.h']]], - ['tim_5fsr_5fcomif_556',['TIM_SR_COMIF',['../group___peripheral___registers___bits___definition.html#ga91775c029171c4585e9cca6ebf1cd57a',1,'stm32f407xx_matlab.h']]], - ['tim_5fsr_5fcomif_5fmsk_557',['TIM_SR_COMIF_Msk',['../group___peripheral___registers___bits___definition.html#ga8af1c1f93eee747aaa7fdc3a5aeb5337',1,'stm32f407xx_matlab.h']]], - ['tim_5fsr_5fcomif_5fpos_558',['TIM_SR_COMIF_Pos',['../group___peripheral___registers___bits___definition.html#gaa44f0ec2b4134ef80ce28d7a878772af',1,'stm32f407xx_matlab.h']]], - ['tim_5fsr_5ftif_559',['TIM_SR_TIF',['../group___peripheral___registers___bits___definition.html#ga7c8b16f3ced6ec03e9001276b134846e',1,'stm32f407xx_matlab.h']]], - ['tim_5fsr_5ftif_5fmsk_560',['TIM_SR_TIF_Msk',['../group___peripheral___registers___bits___definition.html#ga6ad9bed9cae745d41a987675821b202a',1,'stm32f407xx_matlab.h']]], - ['tim_5fsr_5ftif_5fpos_561',['TIM_SR_TIF_Pos',['../group___peripheral___registers___bits___definition.html#gabc65e5e222f7625dda796d36e0c0d563',1,'stm32f407xx_matlab.h']]], - ['tim_5fsr_5fuif_562',['TIM_SR_UIF',['../group___peripheral___registers___bits___definition.html#gac8c03fabc10654d2a3f76ea40fcdbde6',1,'stm32f407xx_matlab.h']]], - ['tim_5fsr_5fuif_5fmsk_563',['TIM_SR_UIF_Msk',['../group___peripheral___registers___bits___definition.html#ga7a713154f9408c97cd7b193f23affab2',1,'stm32f407xx_matlab.h']]], - ['tim_5fsr_5fuif_5fpos_564',['TIM_SR_UIF_Pos',['../group___peripheral___registers___bits___definition.html#ga558df2cd4bfe780f9381149b4e0eab19',1,'stm32f407xx_matlab.h']]], - ['tim_5ftypedef_565',['TIM_TypeDef',['../struct_t_i_m___type_def.html',1,'']]], - ['timer_20systick_566',['System Tick Timer (SysTick)',['../group___c_m_s_i_s___sys_tick.html',1,'']]], - ['timx_5fcount_567',['TIMx_Count',['../group___t_i_m___s_i_m_u_l_a_t_o_r.html#ga55e7ce9aae452502d5104acbe8fa4237',1,'TIMx_Count(TIM_TypeDef *TIMx, struct TIM_Sim *TIMS): stm32f4xx_matlab_tim.c'],['../group___t_i_m___s_i_m_u_l_a_t_o_r.html#ga55e7ce9aae452502d5104acbe8fa4237',1,'TIMx_Count(TIM_TypeDef *TIMx, struct TIM_Sim *TIMS): stm32f4xx_matlab_tim.c']]], - ['tir_568',['TIR',['../group___c_m_s_i_s___device.html#ga6921aa1c578a7d17c6e0eb33a73b6630',1,'CAN_TxMailBox_TypeDef']]], - ['tpi_569',['TPI',['../group___c_m_s_i_s__core__base.html#ga8b4dd00016aed25a0ea54e9a9acd1239',1,'TPI: core_cm4_matlab.h'],['../group___c_m_s_i_s___t_p_i.html',1,'Trace Port Interface (TPI)']]], - ['tpi_5facpr_5fprescaler_5fmsk_570',['TPI_ACPR_PRESCALER_Msk',['../group___c_m_s_i_s___t_p_i.html#ga4fcacd27208419929921aec8457a8c13',1,'core_cm4_matlab.h']]], - ['tpi_5facpr_5fprescaler_5fpos_571',['TPI_ACPR_PRESCALER_Pos',['../group___c_m_s_i_s___t_p_i.html#ga5a82d274eb2df8b0c92dd4ed63535928',1,'core_cm4_matlab.h']]], - ['tpi_5fbase_572',['TPI_BASE',['../group___c_m_s_i_s__core__base.html#ga2b1eeff850a7e418844ca847145a1a68',1,'core_cm4_matlab.h']]], - ['tpi_5fbase_5fshift_573',['TPI_BASE_SHIFT',['../group___c_m_s_i_s__core__base.html#ga688b0af5b023485e742d8906117e0dcb',1,'core_cm4_matlab.h']]], - ['tpi_5fdevid_5fasynclkin_5fmsk_574',['TPI_DEVID_AsynClkIn_Msk',['../group___c_m_s_i_s___t_p_i.html#gab67830557d2d10be882284275025a2d3',1,'core_cm4_matlab.h']]], - ['tpi_5fdevid_5fasynclkin_5fpos_575',['TPI_DEVID_AsynClkIn_Pos',['../group___c_m_s_i_s___t_p_i.html#gab382b1296b5efd057be606eb8f768df8',1,'core_cm4_matlab.h']]], - ['tpi_5fdevid_5fmancvalid_5fmsk_576',['TPI_DEVID_MANCVALID_Msk',['../group___c_m_s_i_s___t_p_i.html#ga4c3ee4b1a34ad1960a6b2d6e7e0ff942',1,'core_cm4_matlab.h']]], - ['tpi_5fdevid_5fmancvalid_5fpos_577',['TPI_DEVID_MANCVALID_Pos',['../group___c_m_s_i_s___t_p_i.html#ga675534579d9e25477bb38970e3ef973c',1,'core_cm4_matlab.h']]], - ['tpi_5fdevid_5fminbufsz_5fmsk_578',['TPI_DEVID_MinBufSz_Msk',['../group___c_m_s_i_s___t_p_i.html#ga939e068ff3f1a65b35187ab34a342cd8',1,'core_cm4_matlab.h']]], - ['tpi_5fdevid_5fminbufsz_5fpos_579',['TPI_DEVID_MinBufSz_Pos',['../group___c_m_s_i_s___t_p_i.html#ga3f7da5de2a34be41a092e5eddd22ac4d',1,'core_cm4_matlab.h']]], - ['tpi_5fdevid_5fnrtraceinput_5fmsk_580',['TPI_DEVID_NrTraceInput_Msk',['../group___c_m_s_i_s___t_p_i.html#gabed454418d2140043cd65ec899abd97f',1,'core_cm4_matlab.h']]], - ['tpi_5fdevid_5fnrtraceinput_5fpos_581',['TPI_DEVID_NrTraceInput_Pos',['../group___c_m_s_i_s___t_p_i.html#ga80ecae7fec479e80e583f545996868ed',1,'core_cm4_matlab.h']]], - ['tpi_5fdevid_5fnrzvalid_5fmsk_582',['TPI_DEVID_NRZVALID_Msk',['../group___c_m_s_i_s___t_p_i.html#gacecc8710a8f6a23a7d1d4f5674daf02a',1,'core_cm4_matlab.h']]], - ['tpi_5fdevid_5fnrzvalid_5fpos_583',['TPI_DEVID_NRZVALID_Pos',['../group___c_m_s_i_s___t_p_i.html#ga9f46cf1a1708575f56d6b827766277f4',1,'core_cm4_matlab.h']]], - ['tpi_5fdevid_5fptinvalid_5fmsk_584',['TPI_DEVID_PTINVALID_Msk',['../group___c_m_s_i_s___t_p_i.html#ga1ca84d62243e475836bba02516ba6b97',1,'core_cm4_matlab.h']]], - ['tpi_5fdevid_5fptinvalid_5fpos_585',['TPI_DEVID_PTINVALID_Pos',['../group___c_m_s_i_s___t_p_i.html#ga974cccf4c958b4a45cb71c7b5de39b7b',1,'core_cm4_matlab.h']]], - ['tpi_5fdevtype_5fmajortype_5fmsk_586',['TPI_DEVTYPE_MajorType_Msk',['../group___c_m_s_i_s___t_p_i.html#gaecbceed6d08ec586403b37ad47b38c88',1,'core_cm4_matlab.h']]], - ['tpi_5fdevtype_5fmajortype_5fpos_587',['TPI_DEVTYPE_MajorType_Pos',['../group___c_m_s_i_s___t_p_i.html#ga69c4892d332755a9f64c1680497cebdd',1,'core_cm4_matlab.h']]], - ['tpi_5fdevtype_5fsubtype_5fmsk_588',['TPI_DEVTYPE_SubType_Msk',['../group___c_m_s_i_s___t_p_i.html#ga5b2fd7dddaf5f64855d9c0696acd65c1',1,'core_cm4_matlab.h']]], - ['tpi_5fdevtype_5fsubtype_5fpos_589',['TPI_DEVTYPE_SubType_Pos',['../group___c_m_s_i_s___t_p_i.html#ga0c799ff892af5eb3162d152abc00af7a',1,'core_cm4_matlab.h']]], - ['tpi_5fffcr_5fenfcont_5fmsk_590',['TPI_FFCR_EnFCont_Msk',['../group___c_m_s_i_s___t_p_i.html#ga27d1ecf2e0ff496df03457a2a97cb2c9',1,'core_cm4_matlab.h']]], - ['tpi_5fffcr_5fenfcont_5fpos_591',['TPI_FFCR_EnFCont_Pos',['../group___c_m_s_i_s___t_p_i.html#ga99e58a0960b275a773b245e2b69b9a64',1,'core_cm4_matlab.h']]], - ['tpi_5fffcr_5ftrigin_5fmsk_592',['TPI_FFCR_TrigIn_Msk',['../group___c_m_s_i_s___t_p_i.html#ga360b413bc5da61f751546a7133c3e4dd',1,'core_cm4_matlab.h']]], - ['tpi_5fffcr_5ftrigin_5fpos_593',['TPI_FFCR_TrigIn_Pos',['../group___c_m_s_i_s___t_p_i.html#gaa7ea11ba6ea75b541cd82e185c725b5b',1,'core_cm4_matlab.h']]], - ['tpi_5fffsr_5fflinprog_5fmsk_594',['TPI_FFSR_FlInProg_Msk',['../group___c_m_s_i_s___t_p_i.html#ga63dfb09259893958962914fc3a9e3824',1,'core_cm4_matlab.h']]], - ['tpi_5fffsr_5fflinprog_5fpos_595',['TPI_FFSR_FlInProg_Pos',['../group___c_m_s_i_s___t_p_i.html#ga542ca74a081588273e6d5275ba5da6bf',1,'core_cm4_matlab.h']]], - ['tpi_5fffsr_5fftnonstop_5fmsk_596',['TPI_FFSR_FtNonStop_Msk',['../group___c_m_s_i_s___t_p_i.html#gaaa313f980974a8cfc7dac68c4d805ab1',1,'core_cm4_matlab.h']]], - ['tpi_5fffsr_5fftnonstop_5fpos_597',['TPI_FFSR_FtNonStop_Pos',['../group___c_m_s_i_s___t_p_i.html#ga9537b8a660cc8803f57cbbee320b2fc8',1,'core_cm4_matlab.h']]], - ['tpi_5fffsr_5fftstopped_5fmsk_598',['TPI_FFSR_FtStopped_Msk',['../group___c_m_s_i_s___t_p_i.html#ga1ab6c3abe1cf6311ee07e7c479ce5f78',1,'core_cm4_matlab.h']]], - ['tpi_5fffsr_5fftstopped_5fpos_599',['TPI_FFSR_FtStopped_Pos',['../group___c_m_s_i_s___t_p_i.html#gaedf31fd453a878021b542b644e2869d2',1,'core_cm4_matlab.h']]], - ['tpi_5fffsr_5ftcpresent_5fmsk_600',['TPI_FFSR_TCPresent_Msk',['../group___c_m_s_i_s___t_p_i.html#ga0d6bfd263ff2fdec72d6ec9415fb1135',1,'core_cm4_matlab.h']]], - ['tpi_5fffsr_5ftcpresent_5fpos_601',['TPI_FFSR_TCPresent_Pos',['../group___c_m_s_i_s___t_p_i.html#gad30fde0c058da2ffb2b0a213be7a1b5c',1,'core_cm4_matlab.h']]], - ['tpi_5ffifo0_5fetm0_5fmsk_602',['TPI_FIFO0_ETM0_Msk',['../group___c_m_s_i_s___t_p_i.html#gaf924f7d1662f3f6c1da12052390cb118',1,'core_cm4_matlab.h']]], - ['tpi_5ffifo0_5fetm0_5fpos_603',['TPI_FIFO0_ETM0_Pos',['../group___c_m_s_i_s___t_p_i.html#ga48783ce3c695d8c06b1352a526110a87',1,'core_cm4_matlab.h']]], - ['tpi_5ffifo0_5fetm1_5fmsk_604',['TPI_FIFO0_ETM1_Msk',['../group___c_m_s_i_s___t_p_i.html#gaad9c1a6ed34a70905005a0cc14d5f01b',1,'core_cm4_matlab.h']]], - ['tpi_5ffifo0_5fetm1_5fpos_605',['TPI_FIFO0_ETM1_Pos',['../group___c_m_s_i_s___t_p_i.html#gac5a2ef4b7f811d1f3d81ec919d794413',1,'core_cm4_matlab.h']]], - ['tpi_5ffifo0_5fetm2_5fmsk_606',['TPI_FIFO0_ETM2_Msk',['../group___c_m_s_i_s___t_p_i.html#gaa82a7b9b99c990fb12eafb3c84b68254',1,'core_cm4_matlab.h']]], - ['tpi_5ffifo0_5fetm2_5fpos_607',['TPI_FIFO0_ETM2_Pos',['../group___c_m_s_i_s___t_p_i.html#ga5f0037cc80c65e86d9e94e5005077a48',1,'core_cm4_matlab.h']]], - ['tpi_5ffifo0_5fetm_5fatvalid_5fmsk_608',['TPI_FIFO0_ETM_ATVALID_Msk',['../group___c_m_s_i_s___t_p_i.html#ga4f0005dc420b28f2369179a935b9a9d3',1,'core_cm4_matlab.h']]], - ['tpi_5ffifo0_5fetm_5fatvalid_5fpos_609',['TPI_FIFO0_ETM_ATVALID_Pos',['../group___c_m_s_i_s___t_p_i.html#ga7fdeb3e465ca4aa9e3b2f424ab3bbd1d',1,'core_cm4_matlab.h']]], - ['tpi_5ffifo0_5fetm_5fbytecount_5fmsk_610',['TPI_FIFO0_ETM_bytecount_Msk',['../group___c_m_s_i_s___t_p_i.html#gad2536b3a935361c68453cd068640af92',1,'core_cm4_matlab.h']]], - ['tpi_5ffifo0_5fetm_5fbytecount_5fpos_611',['TPI_FIFO0_ETM_bytecount_Pos',['../group___c_m_s_i_s___t_p_i.html#ga2f738e45386ebf58c4d406f578e7ddaf',1,'core_cm4_matlab.h']]], - ['tpi_5ffifo0_5fitm_5fatvalid_5fmsk_612',['TPI_FIFO0_ITM_ATVALID_Msk',['../group___c_m_s_i_s___t_p_i.html#ga94cb2493ed35d2dab7bd4092b88a05bc',1,'core_cm4_matlab.h']]], - ['tpi_5ffifo0_5fitm_5fatvalid_5fpos_613',['TPI_FIFO0_ITM_ATVALID_Pos',['../group___c_m_s_i_s___t_p_i.html#gaa7e050e9eb6528241ebc6835783b6bae',1,'core_cm4_matlab.h']]], - ['tpi_5ffifo0_5fitm_5fbytecount_5fmsk_614',['TPI_FIFO0_ITM_bytecount_Msk',['../group___c_m_s_i_s___t_p_i.html#ga07bafa971b8daf0d63b3f92b9ae7fa16',1,'core_cm4_matlab.h']]], - ['tpi_5ffifo0_5fitm_5fbytecount_5fpos_615',['TPI_FIFO0_ITM_bytecount_Pos',['../group___c_m_s_i_s___t_p_i.html#gac2b6f7f13a2fa0be4aa7645a47dcac52',1,'core_cm4_matlab.h']]], - ['tpi_5ffifo1_5fetm_5fatvalid_5fmsk_616',['TPI_FIFO1_ETM_ATVALID_Msk',['../group___c_m_s_i_s___t_p_i.html#ga0e8f29a1e9378d1ceb0708035edbb86d',1,'core_cm4_matlab.h']]], - ['tpi_5ffifo1_5fetm_5fatvalid_5fpos_617',['TPI_FIFO1_ETM_ATVALID_Pos',['../group___c_m_s_i_s___t_p_i.html#ga3177b8d815cf4a707a2d3d3d5499315d',1,'core_cm4_matlab.h']]], - ['tpi_5ffifo1_5fetm_5fbytecount_5fmsk_618',['TPI_FIFO1_ETM_bytecount_Msk',['../group___c_m_s_i_s___t_p_i.html#gab554305459953b80554fdb1908b73291',1,'core_cm4_matlab.h']]], - ['tpi_5ffifo1_5fetm_5fbytecount_5fpos_619',['TPI_FIFO1_ETM_bytecount_Pos',['../group___c_m_s_i_s___t_p_i.html#gaab31238152b5691af633a7475eaf1f06',1,'core_cm4_matlab.h']]], - ['tpi_5ffifo1_5fitm0_5fmsk_620',['TPI_FIFO1_ITM0_Msk',['../group___c_m_s_i_s___t_p_i.html#ga8ae09f544fc1a428797e2a150f14a4c9',1,'core_cm4_matlab.h']]], - ['tpi_5ffifo1_5fitm0_5fpos_621',['TPI_FIFO1_ITM0_Pos',['../group___c_m_s_i_s___t_p_i.html#ga2188671488417a52abb075bcd4d73440',1,'core_cm4_matlab.h']]], - ['tpi_5ffifo1_5fitm1_5fmsk_622',['TPI_FIFO1_ITM1_Msk',['../group___c_m_s_i_s___t_p_i.html#ga3347f42828920dfe56e3130ad319a9e6',1,'core_cm4_matlab.h']]], - ['tpi_5ffifo1_5fitm1_5fpos_623',['TPI_FIFO1_ITM1_Pos',['../group___c_m_s_i_s___t_p_i.html#gaece86ab513bc3d0e0a9dbd82258af49f',1,'core_cm4_matlab.h']]], - ['tpi_5ffifo1_5fitm2_5fmsk_624',['TPI_FIFO1_ITM2_Msk',['../group___c_m_s_i_s___t_p_i.html#gae54512f926ebc00f2e056232aa21d335',1,'core_cm4_matlab.h']]], - ['tpi_5ffifo1_5fitm2_5fpos_625',['TPI_FIFO1_ITM2_Pos',['../group___c_m_s_i_s___t_p_i.html#ga1828c228f3940005f48fb8dd88ada35b',1,'core_cm4_matlab.h']]], - ['tpi_5ffifo1_5fitm_5fatvalid_5fmsk_626',['TPI_FIFO1_ITM_ATVALID_Msk',['../group___c_m_s_i_s___t_p_i.html#gabc1f6a3b6cac0099d7c01ca949b4dd08',1,'core_cm4_matlab.h']]], - ['tpi_5ffifo1_5fitm_5fatvalid_5fpos_627',['TPI_FIFO1_ITM_ATVALID_Pos',['../group___c_m_s_i_s___t_p_i.html#ga08edfc862b2c8c415854cc4ae2067dfb',1,'core_cm4_matlab.h']]], - ['tpi_5ffifo1_5fitm_5fbytecount_5fmsk_628',['TPI_FIFO1_ITM_bytecount_Msk',['../group___c_m_s_i_s___t_p_i.html#gacba2edfc0499828019550141356b0dcb',1,'core_cm4_matlab.h']]], - ['tpi_5ffifo1_5fitm_5fbytecount_5fpos_629',['TPI_FIFO1_ITM_bytecount_Pos',['../group___c_m_s_i_s___t_p_i.html#gaa22ebf7c86e4f4b2c98cfd0b5981375a',1,'core_cm4_matlab.h']]], - ['tpi_5fitatbctr0_5fatready1_5fmsk_630',['TPI_ITATBCTR0_ATREADY1_Msk',['../group___c_m_s_i_s___t_p_i.html#ga21e1f9c5532e75ee2edc8eb4cf69b1f0',1,'core_cm4_matlab.h']]], - ['tpi_5fitatbctr0_5fatready1_5fpos_631',['TPI_ITATBCTR0_ATREADY1_Pos',['../group___c_m_s_i_s___t_p_i.html#gaded82241155665db59493d912d44c65c',1,'core_cm4_matlab.h']]], - ['tpi_5fitatbctr0_5fatready2_5fmsk_632',['TPI_ITATBCTR0_ATREADY2_Msk',['../group___c_m_s_i_s___t_p_i.html#gaf985067de6e6e68fbbd2350646b9125e',1,'core_cm4_matlab.h']]], - ['tpi_5fitatbctr0_5fatready2_5fpos_633',['TPI_ITATBCTR0_ATREADY2_Pos',['../group___c_m_s_i_s___t_p_i.html#ga3f0249dfcfd58090c08fd4a0adea6b22',1,'core_cm4_matlab.h']]], - ['tpi_5fitatbctr2_5fatready1_5fmsk_634',['TPI_ITATBCTR2_ATREADY1_Msk',['../group___c_m_s_i_s___t_p_i.html#ga32573fb2508a35660ab785a85c5b38a7',1,'core_cm4_matlab.h']]], - ['tpi_5fitatbctr2_5fatready1_5fpos_635',['TPI_ITATBCTR2_ATREADY1_Pos',['../group___c_m_s_i_s___t_p_i.html#gae0edc53203a2373fef7734be91e6125a',1,'core_cm4_matlab.h']]], - ['tpi_5fitatbctr2_5fatready2_5fmsk_636',['TPI_ITATBCTR2_ATREADY2_Msk',['../group___c_m_s_i_s___t_p_i.html#gaef520d45da3808f8ffde92b915cd6c7c',1,'core_cm4_matlab.h']]], - ['tpi_5fitatbctr2_5fatready2_5fpos_637',['TPI_ITATBCTR2_ATREADY2_Pos',['../group___c_m_s_i_s___t_p_i.html#ga36b77b6a6a9808dec534802232ffcaa4',1,'core_cm4_matlab.h']]], - ['tpi_5fitctrl_5fmode_5fmsk_638',['TPI_ITCTRL_Mode_Msk',['../group___c_m_s_i_s___t_p_i.html#gad6f87550b468ad0920d5f405bfd3f017',1,'core_cm4_matlab.h']]], - ['tpi_5fitctrl_5fmode_5fpos_639',['TPI_ITCTRL_Mode_Pos',['../group___c_m_s_i_s___t_p_i.html#gaa847adb71a1bc811d2e3190528f495f0',1,'core_cm4_matlab.h']]], - ['tpi_5fsppr_5ftxmode_5fmsk_640',['TPI_SPPR_TXMODE_Msk',['../group___c_m_s_i_s___t_p_i.html#gaca085c8a954393d70dbd7240bb02cc1f',1,'core_cm4_matlab.h']]], - ['tpi_5fsppr_5ftxmode_5fpos_641',['TPI_SPPR_TXMODE_Pos',['../group___c_m_s_i_s___t_p_i.html#ga0f302797b94bb2da24052082ab630858',1,'core_cm4_matlab.h']]], - ['tpi_5ftrigger_5ftrigger_5fmsk_642',['TPI_TRIGGER_TRIGGER_Msk',['../group___c_m_s_i_s___t_p_i.html#ga814227af2b2665a0687bb49345e21110',1,'core_cm4_matlab.h']]], - ['tpi_5ftrigger_5ftrigger_5fpos_643',['TPI_TRIGGER_TRIGGER_Pos',['../group___c_m_s_i_s___t_p_i.html#ga5517fa2ced64efbbd413720329c50b99',1,'core_cm4_matlab.h']]], - ['tpi_5ftype_644',['TPI_Type',['../struct_t_p_i___type.html',1,'']]], - ['tpr_645',['TPR',['../group___c_m_s_i_s__core___debug_functions.html#gafe5e266862734ca1082ceddff7180688',1,'ITM_Type']]], - ['tr_646',['TR',['../group___c_m_s_i_s___device.html#ga63d179b7a36a715dce7203858d3be132',1,'RTC_TypeDef']]], - ['trace_20dwt_647',['Data Watchpoint and Trace (DWT)',['../group___c_m_s_i_s___d_w_t.html',1,'']]], - ['trace_20macrocell_20itm_648',['Instrumentation Trace Macrocell (ITM)',['../group___c_m_s_i_s___i_t_m.html',1,'']]], - ['trace_20port_20interface_20tpi_649',['Trace Port Interface (TPI)',['../group___c_m_s_i_s___t_p_i.html',1,'']]], - ['trigger_650',['TRIGGER',['../group___c_m_s_i_s__core___debug_functions.html#ga5590387d8f44b477fd69951a737b0d7e',1,'TPI_Type']]], - ['trise_651',['TRISE',['../group___c_m_s_i_s___device.html#ga5d5764c0ec44b661da957e6343f9e7b5',1,'I2C_TypeDef']]], - ['ts_652',['Ts',['../mexing_8m.html#ac910fa4e03fcc57ffc78b3693e910e1a',1,'mexing.m']]], - ['tsdr_653',['TSDR',['../group___c_m_s_i_s___device.html#gabeb6fb580a8fd128182aa9ba2738ac2c',1,'RTC_TypeDef']]], - ['tsr_654',['TSR',['../group___c_m_s_i_s___device.html#ga87e3001757a0cd493785f1f3337dd0e8',1,'CAN_TypeDef']]], - ['tsssr_655',['TSSSR',['../group___c_m_s_i_s___device.html#ga1d6c2bc4c067d6a64ef30d16a5925796',1,'RTC_TypeDef']]], - ['tstr_656',['TSTR',['../group___c_m_s_i_s___device.html#ga042059c8b4168681d6aecf30211dd7b8',1,'RTC_TypeDef']]], - ['tx_5fcnt_657',['tx_cnt',['../struct_t_i_m___sim.html#a369177ee20a3798f0d7b98cf7c549498',1,'TIM_Sim']]], - ['tx_5fstep_658',['tx_step',['../struct_t_i_m___sim.html#a838a96dee1a1980434ae35295f85141e',1,'TIM_Sim']]], - ['txcrcr_659',['TXCRCR',['../group___c_m_s_i_s___device.html#gab4e4328504fd66285df8264d410deefd',1,'SPI_TypeDef']]], - ['type_20definitions_660',['Defines and Type Definitions',['../group___c_m_s_i_s__core__register.html',1,'']]] + ['длÑ_20matlab_0',['ЭмулÑтор STM Ð´Ð»Ñ MATLAB',['../index.html#ÑмулÑтор-stm-длÑ-matlab',1,'']]], + ['длÑ_20stm32_1',['ОпиÑание Ñтуктуры ÑмулÑтора (пример Ð´Ð»Ñ STM32)',['../index.html#опиÑание-Ñтуктуры-ÑмулÑтора-пример-длÑ-stm32',1,'']]] ]; diff --git a/DOCS/html/search/all_15.js b/DOCS/html/search/all_15.js index a6e94ac..ad69bd1 100644 --- a/DOCS/html/search/all_15.js +++ b/DOCS/html/search/all_15.js @@ -1,1427 +1,4 @@ var searchData= [ - ['u16_0',['u16',['../group___c_m_s_i_s__core___debug_functions.html#gae93660eefe2482a8564fae9a1ca39739',1,'ITM_Type::u16'],['../group___c_m_s_i_s__core___debug_functions.html#gae93660eefe2482a8564fae9a1ca39739',1,'ITM_Type::@4::u16']]], - ['u32_1',['u32',['../group___c_m_s_i_s__core___debug_functions.html#gae89dd50f788f12863c681fba1a5b60d1',1,'ITM_Type::u32'],['../group___c_m_s_i_s__core___debug_functions.html#gae89dd50f788f12863c681fba1a5b60d1',1,'ITM_Type::@4::u32']]], - ['u8_2',['u8',['../group___c_m_s_i_s__core___debug_functions.html#ga4c0550e859d614c607bd4b575f05425c',1,'ITM_Type::u8'],['../group___c_m_s_i_s__core___debug_functions.html#ga4c0550e859d614c607bd4b575f05425c',1,'ITM_Type::@4::u8']]], - ['uart4_3',['UART4',['../group___peripheral__declaration.html#ga7c035f6f443c999fc043b2b7fb598800',1,'stm32f407xx_matlab.h']]], - ['uart4_4',['uart4',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#gaeac987df31348c6546d30bf20d1202b1',1,'stm32f4xx_periph_registers.c']]], - ['uart4_5fbase_5',['UART4_BASE',['../group___peripheral__memory__map.html#ga94d92270bf587ccdc3a37a5bb5d20467',1,'stm32f407xx_matlab.h']]], - ['uart4_5firqn_6',['UART4_IRQn',['../group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8aded5314b20c6e4e80cb6ab0668ffb8d5',1,'stm32f407xx_matlab.h']]], - ['uart5_7',['UART5',['../group___peripheral__declaration.html#ga9274e37cf5e8a174fc5dd627b98ec0fe',1,'stm32f407xx_matlab.h']]], - ['uart5_8',['uart5',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga334a742f4e47d9275a7ca0b6a64f3b9b',1,'stm32f4xx_periph_registers.c']]], - ['uart5_5fbase_9',['UART5_BASE',['../group___peripheral__memory__map.html#gaa155689c0e206e6994951dc3cf31052a',1,'stm32f407xx_matlab.h']]], - ['uart5_5firqn_10',['UART5_IRQn',['../group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8ac55a11a64aae7432544d0ab0d4f7de09',1,'stm32f407xx_matlab.h']]], - ['uid_5fbase_11',['UID_BASE',['../group___peripheral__memory__map.html#ga664eda42b83c919b153b07b23348be67',1,'stm32f407xx_matlab.h']]], - ['uint16_5fc_12',['UINT16_C',['../stdint_8h.html#a1cb39a2cfaf899fd38730c7637807708',1,'stdint.h']]], - ['uint16_5fmax_13',['UINT16_MAX',['../stdint_8h.html#a3ea490c9b3617d4479bd80ef93cd5602',1,'stdint.h']]], - ['uint16_5ft_14',['uint16_t',['../stdint_8h.html#adf4d876453337156dde61095e1f20223',1,'stdint.h']]], - ['uint32_5fc_15',['UINT32_C',['../stdint_8h.html#a2451a7ede7ebd810357f1503e9898ea6',1,'stdint.h']]], - ['uint32_5fmax_16',['UINT32_MAX',['../stdint_8h.html#ab5eb23180f7cc12b7d6c04a8ec067fdd',1,'stdint.h']]], - ['uint32_5ft_17',['uint32_t',['../stdint_8h.html#a435d1572bf3f880d55459d9805097f62',1,'stdint.h']]], - ['uint64_5fc_18',['UINT64_C',['../stdint_8h.html#a134ae84400d184ed2570e3270d5472c2',1,'stdint.h']]], - ['uint64_5fmax_19',['UINT64_MAX',['../stdint_8h.html#a30654b4b67d97c42ca3f9b6052dda916',1,'stdint.h']]], - ['uint64_5ft_20',['uint64_t',['../stdint_8h.html#aeaec22c681a555c831cfc2337189a4da',1,'stdint.h']]], - ['uint8_5fc_21',['UINT8_C',['../stdint_8h.html#acd2aa09844a8a245cf7fdbb808e215e5',1,'stdint.h']]], - ['uint8_5fmax_22',['UINT8_MAX',['../stdint_8h.html#aeb4e270a084ee26fe73e799861bd0252',1,'stdint.h']]], - ['uint8_5ft_23',['uint8_t',['../stdint_8h.html#aba7bc1797add20fe3efdf37ced1182c5',1,'stdint.h']]], - ['uint_5ffast16_5fmax_24',['UINT_FAST16_MAX',['../stdint_8h.html#aed28ca63d9b222f6f1377358fe73a183',1,'stdint.h']]], - ['uint_5ffast16_5ft_25',['uint_fast16_t',['../stdint_8h.html#a226d967fb6d06433caf43f20dc876aae',1,'stdint.h']]], - ['uint_5ffast32_5fmax_26',['UINT_FAST32_MAX',['../stdint_8h.html#ad51246a178143208b2db3315efd21c45',1,'stdint.h']]], - ['uint_5ffast32_5ft_27',['uint_fast32_t',['../stdint_8h.html#a633264eb9df8f0520acccbbfb406f806',1,'stdint.h']]], - ['uint_5ffast64_5fmax_28',['UINT_FAST64_MAX',['../stdint_8h.html#aeb74410af7781bc84b5f64ae7a8f4a17',1,'stdint.h']]], - ['uint_5ffast64_5ft_29',['uint_fast64_t',['../stdint_8h.html#a231d03c9e26ec4bdeddf882b02354b40',1,'stdint.h']]], - ['uint_5ffast8_5fmax_30',['UINT_FAST8_MAX',['../stdint_8h.html#a2c6f97ea2d76d0cf6260c84046cdb44e',1,'stdint.h']]], - ['uint_5ffast8_5ft_31',['uint_fast8_t',['../stdint_8h.html#ad0906fbe05a45fbdb000c58fe8929e70',1,'stdint.h']]], - ['uint_5fleast16_5fmax_32',['UINT_LEAST16_MAX',['../stdint_8h.html#a6ef6a1a518bbf516ca8b0180b11c358f',1,'stdint.h']]], - ['uint_5fleast16_5ft_33',['uint_least16_t',['../stdint_8h.html#a1bae72af13d35bac8eb9424db7e27bf1',1,'stdint.h']]], - ['uint_5fleast32_5fmax_34',['UINT_LEAST32_MAX',['../stdint_8h.html#a70cad8bacc9a6db301e1cdc86cc8d571',1,'stdint.h']]], - ['uint_5fleast32_5ft_35',['uint_least32_t',['../stdint_8h.html#a9a3e3b9785e918fb2c7d964efebd2130',1,'stdint.h']]], - ['uint_5fleast64_5fmax_36',['UINT_LEAST64_MAX',['../stdint_8h.html#aab530113fa96e280e49c3c138b0f917d',1,'stdint.h']]], - ['uint_5fleast64_5ft_37',['uint_least64_t',['../stdint_8h.html#a3fd9527296a9f56a6bf1ea978fc2be3f',1,'stdint.h']]], - ['uint_5fleast8_5fmax_38',['UINT_LEAST8_MAX',['../stdint_8h.html#a2a80bde77ee1698d0f42f334adad4f2b',1,'stdint.h']]], - ['uint_5fleast8_5ft_39',['uint_least8_t',['../stdint_8h.html#ab0fdd2a9dc9606590ecccc0a5d8b5b7c',1,'stdint.h']]], - ['uintmax_5fc_40',['UINTMAX_C',['../stdint_8h.html#ad99c338b32fbeaa158cba21e532dfe5d',1,'stdint.h']]], - ['uintmax_5fmax_41',['UINTMAX_MAX',['../stdint_8h.html#aa54fd5210434219e9027bfa0f0e325c8',1,'stdint.h']]], - ['uintmax_5ft_42',['uintmax_t',['../stdint_8h.html#a3173cf7a59047054a5933f8e9aa56eae',1,'stdint.h']]], - ['uintptr_5fmax_43',['UINTPTR_MAX',['../stdint_8h.html#ab2355300ea19395357e62d780f4dd073',1,'stdint.h']]], - ['uintptr_5ft_44',['uintptr_t',['../stdint_8h.html#a728e973c799f206f0151c8a3bd1e5699',1,'stdint.h']]], - ['unit_20fpu_45',['Floating Point Unit (FPU)',['../group___c_m_s_i_s___f_p_u.html',1,'']]], - ['usagefault_5firqn_46',['UsageFault_IRQn',['../group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a6895237c9443601ac832efa635dd8bbf',1,'stm32f407xx_matlab.h']]], - ['usart1_47',['USART1',['../group___peripheral__declaration.html#ga92871691058ff7ccffd7635930cb08da',1,'stm32f407xx_matlab.h']]], - ['usart1_48',['usart1',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga6008378d0a594dbb3373976f11998c07',1,'stm32f4xx_periph_registers.c']]], - ['usart1_5fbase_49',['USART1_BASE',['../group___peripheral__memory__map.html#ga86162ab3f740db9026c1320d46938b4d',1,'stm32f407xx_matlab.h']]], - ['usart1_5firqn_50',['USART1_IRQn',['../group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8ad97cb163e1f678367e37c50d54d161ab',1,'stm32f407xx_matlab.h']]], - ['usart2_51',['USART2',['../group___peripheral__declaration.html#gaf114a9eab03ca08a6fb720e511595930',1,'stm32f407xx_matlab.h']]], - ['usart2_52',['usart2',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga6704391eb1d9b549ec4a30bff051c840',1,'stm32f4xx_periph_registers.c']]], - ['usart2_5fbase_53',['USART2_BASE',['../group___peripheral__memory__map.html#gade83162a04bca0b15b39018a8e8ec090',1,'stm32f407xx_matlab.h']]], - ['usart2_5firqn_54',['USART2_IRQn',['../group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a3f9c48714d0e5baaba6613343f0da68e',1,'stm32f407xx_matlab.h']]], - ['usart3_55',['USART3',['../group___peripheral__declaration.html#ga2350115553c1fe0a7bc14e6a7ec6a225',1,'stm32f407xx_matlab.h']]], - ['usart3_56',['usart3',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga34a4f060994660316b3ccf64ef2ca061',1,'stm32f4xx_periph_registers.c']]], - ['usart3_5fbase_57',['USART3_BASE',['../group___peripheral__memory__map.html#gabe0d6539ac0026d598274ee7f45b0251',1,'stm32f407xx_matlab.h']]], - ['usart3_5firqn_58',['USART3_IRQn',['../group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8afb13802afc1f5fdf5c90e73ee99e5ff3',1,'stm32f407xx_matlab.h']]], - ['usart6_59',['USART6',['../group___peripheral__declaration.html#ga2dab39a19ce3dd05fe360dcbb7b5dc84',1,'stm32f407xx_matlab.h']]], - ['usart6_60',['usart6',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#gac976d368ba60c6c4fb520f15ffc973ed',1,'stm32f4xx_periph_registers.c']]], - ['usart6_5fbase_61',['USART6_BASE',['../group___peripheral__memory__map.html#gade4d3907fd0387ee832f426f52d568bb',1,'stm32f407xx_matlab.h']]], - ['usart6_5firqn_62',['USART6_IRQn',['../group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8aa92bcb2bc3a87be869f05c5b07f04b8c',1,'stm32f407xx_matlab.h']]], - ['usart_5fbrr_5fdiv_5ffraction_63',['USART_BRR_DIV_Fraction',['../group___peripheral___registers___bits___definition.html#ga9dfae31be4ec2c8a3b0905eff30c7046',1,'stm32f407xx_matlab.h']]], - ['usart_5fbrr_5fdiv_5ffraction_5fmsk_64',['USART_BRR_DIV_Fraction_Msk',['../group___peripheral___registers___bits___definition.html#ga1cc35155a1120da23f3fc72cb26b4aea',1,'stm32f407xx_matlab.h']]], - ['usart_5fbrr_5fdiv_5ffraction_5fpos_65',['USART_BRR_DIV_Fraction_Pos',['../group___peripheral___registers___bits___definition.html#gaa4c70e9b7c797d9a6e1e7a4e4e645ef1',1,'stm32f407xx_matlab.h']]], - ['usart_5fbrr_5fdiv_5fmantissa_66',['USART_BRR_DIV_Mantissa',['../group___peripheral___registers___bits___definition.html#ga60cfa3802798306b86231f828ed2e71e',1,'stm32f407xx_matlab.h']]], - ['usart_5fbrr_5fdiv_5fmantissa_5fmsk_67',['USART_BRR_DIV_Mantissa_Msk',['../group___peripheral___registers___bits___definition.html#gace4259fb84cf5a9096ad62cd2453d28e',1,'stm32f407xx_matlab.h']]], - ['usart_5fbrr_5fdiv_5fmantissa_5fpos_68',['USART_BRR_DIV_Mantissa_Pos',['../group___peripheral___registers___bits___definition.html#ga21895f823b1422a7af307b0656560058',1,'stm32f407xx_matlab.h']]], - ['usart_5fcr1_5fidleie_69',['USART_CR1_IDLEIE',['../group___peripheral___registers___bits___definition.html#ga5221d09eebd12445a20f221bf98066f8',1,'stm32f407xx_matlab.h']]], - ['usart_5fcr1_5fidleie_5fmsk_70',['USART_CR1_IDLEIE_Msk',['../group___peripheral___registers___bits___definition.html#ga8ad37a38ae2c8a059a922f5b33c5c2aa',1,'stm32f407xx_matlab.h']]], - ['usart_5fcr1_5fidleie_5fpos_71',['USART_CR1_IDLEIE_Pos',['../group___peripheral___registers___bits___definition.html#ga5ba3e0fc695108b77498a9fdbacc95d3',1,'stm32f407xx_matlab.h']]], - ['usart_5fcr1_5fm_72',['USART_CR1_M',['../group___peripheral___registers___bits___definition.html#ga95f0288b9c6aaeca7cb6550a2e6833e2',1,'stm32f407xx_matlab.h']]], - ['usart_5fcr1_5fm_5fmsk_73',['USART_CR1_M_Msk',['../group___peripheral___registers___bits___definition.html#ga3b5f5bc798207f9cc9e54ab080637634',1,'stm32f407xx_matlab.h']]], - ['usart_5fcr1_5fm_5fpos_74',['USART_CR1_M_Pos',['../group___peripheral___registers___bits___definition.html#ga8b16c1bf94dba8a889397c5933322308',1,'stm32f407xx_matlab.h']]], - ['usart_5fcr1_5fover8_75',['USART_CR1_OVER8',['../group___peripheral___registers___bits___definition.html#gaed6caeb0cb48f1a7b34090f31a92a8e2',1,'stm32f407xx_matlab.h']]], - ['usart_5fcr1_5fover8_5fmsk_76',['USART_CR1_OVER8_Msk',['../group___peripheral___registers___bits___definition.html#gac009e53008167c20955efe87a147ea02',1,'stm32f407xx_matlab.h']]], - ['usart_5fcr1_5fover8_5fpos_77',['USART_CR1_OVER8_Pos',['../group___peripheral___registers___bits___definition.html#ga7f51c380de00d417c76712183070ff01',1,'stm32f407xx_matlab.h']]], - ['usart_5fcr1_5fpce_78',['USART_CR1_PCE',['../group___peripheral___registers___bits___definition.html#ga60f8fcf084f9a8514efafb617c70b074',1,'stm32f407xx_matlab.h']]], - ['usart_5fcr1_5fpce_5fmsk_79',['USART_CR1_PCE_Msk',['../group___peripheral___registers___bits___definition.html#ga60894c2937928b5ca83fe73e60e1c9c1',1,'stm32f407xx_matlab.h']]], - ['usart_5fcr1_5fpce_5fpos_80',['USART_CR1_PCE_Pos',['../group___peripheral___registers___bits___definition.html#ga1029c679b6ce540fc8343e074387fa5b',1,'stm32f407xx_matlab.h']]], - ['usart_5fcr1_5fpeie_81',['USART_CR1_PEIE',['../group___peripheral___registers___bits___definition.html#ga27405d413b6d355ccdb076d52fef6875',1,'stm32f407xx_matlab.h']]], - ['usart_5fcr1_5fpeie_5fmsk_82',['USART_CR1_PEIE_Msk',['../group___peripheral___registers___bits___definition.html#gad99fb4719a46d6d1d423d7ffe7ce06e1',1,'stm32f407xx_matlab.h']]], - ['usart_5fcr1_5fpeie_5fpos_83',['USART_CR1_PEIE_Pos',['../group___peripheral___registers___bits___definition.html#ga46a693e8924defd8e57b0b08323afa0b',1,'stm32f407xx_matlab.h']]], - ['usart_5fcr1_5fps_84',['USART_CR1_PS',['../group___peripheral___registers___bits___definition.html#ga2e159d36ab2c93a2c1942df60e9eebbe',1,'stm32f407xx_matlab.h']]], - ['usart_5fcr1_5fps_5fmsk_85',['USART_CR1_PS_Msk',['../group___peripheral___registers___bits___definition.html#ga08638afebc30caad3337f1faac6d904e',1,'stm32f407xx_matlab.h']]], - ['usart_5fcr1_5fps_5fpos_86',['USART_CR1_PS_Pos',['../group___peripheral___registers___bits___definition.html#gaf2e65e62ab989658fec2bdaad7892c16',1,'stm32f407xx_matlab.h']]], - ['usart_5fcr1_5fre_87',['USART_CR1_RE',['../group___peripheral___registers___bits___definition.html#gada0d5d407a22264de847bc1b40a17aeb',1,'stm32f407xx_matlab.h']]], - ['usart_5fcr1_5fre_5fmsk_88',['USART_CR1_RE_Msk',['../group___peripheral___registers___bits___definition.html#ga625927bbfd40ce911de7183cae92e682',1,'stm32f407xx_matlab.h']]], - ['usart_5fcr1_5fre_5fpos_89',['USART_CR1_RE_Pos',['../group___peripheral___registers___bits___definition.html#ga678b98c07ad61dec17131716d1ddfa58',1,'stm32f407xx_matlab.h']]], - ['usart_5fcr1_5frwu_90',['USART_CR1_RWU',['../group___peripheral___registers___bits___definition.html#gaa7d61ab5a4e2beaa3f591c56bd15a27b',1,'stm32f407xx_matlab.h']]], - ['usart_5fcr1_5frwu_5fmsk_91',['USART_CR1_RWU_Msk',['../group___peripheral___registers___bits___definition.html#ga8e0cafa55c289e39145287325f9d7cf4',1,'stm32f407xx_matlab.h']]], - ['usart_5fcr1_5frwu_5fpos_92',['USART_CR1_RWU_Pos',['../group___peripheral___registers___bits___definition.html#ga64a90f545fa1ee315c277fd0f06f2274',1,'stm32f407xx_matlab.h']]], - ['usart_5fcr1_5frxneie_93',['USART_CR1_RXNEIE',['../group___peripheral___registers___bits___definition.html#ga91118f867adfdb2e805beea86666de04',1,'stm32f407xx_matlab.h']]], - ['usart_5fcr1_5frxneie_5fmsk_94',['USART_CR1_RXNEIE_Msk',['../group___peripheral___registers___bits___definition.html#gac2e4ba1ab97599cbf7f182d2cfc80543',1,'stm32f407xx_matlab.h']]], - ['usart_5fcr1_5frxneie_5fpos_95',['USART_CR1_RXNEIE_Pos',['../group___peripheral___registers___bits___definition.html#ga2232ea76bad178a6e945fe573c2dc984',1,'stm32f407xx_matlab.h']]], - ['usart_5fcr1_5fsbk_96',['USART_CR1_SBK',['../group___peripheral___registers___bits___definition.html#gac457c519baa28359ab7959fbe0c5cda1',1,'stm32f407xx_matlab.h']]], - ['usart_5fcr1_5fsbk_5fmsk_97',['USART_CR1_SBK_Msk',['../group___peripheral___registers___bits___definition.html#ga4f06150e7efb4ee5858a0863c0af36e1',1,'stm32f407xx_matlab.h']]], - ['usart_5fcr1_5fsbk_5fpos_98',['USART_CR1_SBK_Pos',['../group___peripheral___registers___bits___definition.html#ga23eec4bbb3ac06c22aff3355f965457a',1,'stm32f407xx_matlab.h']]], - ['usart_5fcr1_5ftcie_99',['USART_CR1_TCIE',['../group___peripheral___registers___bits___definition.html#gaa17130690a1ca95b972429eb64d4254e',1,'stm32f407xx_matlab.h']]], - ['usart_5fcr1_5ftcie_5fmsk_100',['USART_CR1_TCIE_Msk',['../group___peripheral___registers___bits___definition.html#gad3ff7666f8e81e2cf6d40bebaf0a84b7',1,'stm32f407xx_matlab.h']]], - ['usart_5fcr1_5ftcie_5fpos_101',['USART_CR1_TCIE_Pos',['../group___peripheral___registers___bits___definition.html#ga3ee92ad658865410023fc8508325024a',1,'stm32f407xx_matlab.h']]], - ['usart_5fcr1_5fte_102',['USART_CR1_TE',['../group___peripheral___registers___bits___definition.html#gade7f090b04fd78b755b43357ecaa9622',1,'stm32f407xx_matlab.h']]], - ['usart_5fcr1_5fte_5fmsk_103',['USART_CR1_TE_Msk',['../group___peripheral___registers___bits___definition.html#ga0c5e02008c2fde7c5f0070d94ee77bce',1,'stm32f407xx_matlab.h']]], - ['usart_5fcr1_5fte_5fpos_104',['USART_CR1_TE_Pos',['../group___peripheral___registers___bits___definition.html#ga53df187761bfed354686b47e0a691564',1,'stm32f407xx_matlab.h']]], - ['usart_5fcr1_5ftxeie_105',['USART_CR1_TXEIE',['../group___peripheral___registers___bits___definition.html#ga70422871d15f974b464365e7fe1877e9',1,'stm32f407xx_matlab.h']]], - ['usart_5fcr1_5ftxeie_5fmsk_106',['USART_CR1_TXEIE_Msk',['../group___peripheral___registers___bits___definition.html#ga65436dd25155a36250ee090dd940caa5',1,'stm32f407xx_matlab.h']]], - ['usart_5fcr1_5ftxeie_5fpos_107',['USART_CR1_TXEIE_Pos',['../group___peripheral___registers___bits___definition.html#ga6931210415f36d727f75bfc856aed9ef',1,'stm32f407xx_matlab.h']]], - ['usart_5fcr1_5fue_108',['USART_CR1_UE',['../group___peripheral___registers___bits___definition.html#ga2bb650676aaae4a5203f372d497d5947',1,'stm32f407xx_matlab.h']]], - ['usart_5fcr1_5fue_5fmsk_109',['USART_CR1_UE_Msk',['../group___peripheral___registers___bits___definition.html#gab8b32c050e6d9482a819e0107ceb9f83',1,'stm32f407xx_matlab.h']]], - ['usart_5fcr1_5fue_5fpos_110',['USART_CR1_UE_Pos',['../group___peripheral___registers___bits___definition.html#ga64f40c78bbc597ada96c2ec828722eeb',1,'stm32f407xx_matlab.h']]], - ['usart_5fcr1_5fwake_111',['USART_CR1_WAKE',['../group___peripheral___registers___bits___definition.html#gad831dfc169fcf14b7284984dbecf322d',1,'stm32f407xx_matlab.h']]], - ['usart_5fcr1_5fwake_5fmsk_112',['USART_CR1_WAKE_Msk',['../group___peripheral___registers___bits___definition.html#gab0bc41f3a11fced743f19684211eacd6',1,'stm32f407xx_matlab.h']]], - ['usart_5fcr1_5fwake_5fpos_113',['USART_CR1_WAKE_Pos',['../group___peripheral___registers___bits___definition.html#ga86cc2060fef5dc3ce6820e31f0156492',1,'stm32f407xx_matlab.h']]], - ['usart_5fcr2_5fadd_114',['USART_CR2_ADD',['../group___peripheral___registers___bits___definition.html#ga3ee77fac25142271ad56d49685e518b3',1,'stm32f407xx_matlab.h']]], - ['usart_5fcr2_5fadd_5fmsk_115',['USART_CR2_ADD_Msk',['../group___peripheral___registers___bits___definition.html#gad7ee87cc9cdc865b0f5a61af0c26ec28',1,'stm32f407xx_matlab.h']]], - ['usart_5fcr2_5fadd_5fpos_116',['USART_CR2_ADD_Pos',['../group___peripheral___registers___bits___definition.html#ga2d1320f17e2f61e21a867e538c737ac3',1,'stm32f407xx_matlab.h']]], - ['usart_5fcr2_5fclken_117',['USART_CR2_CLKEN',['../group___peripheral___registers___bits___definition.html#ga42a396cde02ffa0c4d3fd9817b6af853',1,'stm32f407xx_matlab.h']]], - ['usart_5fcr2_5fclken_5fmsk_118',['USART_CR2_CLKEN_Msk',['../group___peripheral___registers___bits___definition.html#ga2f6a20180f8b2ad531009b33ecec1ed2',1,'stm32f407xx_matlab.h']]], - ['usart_5fcr2_5fclken_5fpos_119',['USART_CR2_CLKEN_Pos',['../group___peripheral___registers___bits___definition.html#gaff740ebbb84ac8db332d177cd6cc9235',1,'stm32f407xx_matlab.h']]], - ['usart_5fcr2_5fcpha_120',['USART_CR2_CPHA',['../group___peripheral___registers___bits___definition.html#ga362976ce813e58310399d113d2cf09cb',1,'stm32f407xx_matlab.h']]], - ['usart_5fcr2_5fcpha_5fmsk_121',['USART_CR2_CPHA_Msk',['../group___peripheral___registers___bits___definition.html#ga65c8198c5780edaa8ef67706d7d1ea34',1,'stm32f407xx_matlab.h']]], - ['usart_5fcr2_5fcpha_5fpos_122',['USART_CR2_CPHA_Pos',['../group___peripheral___registers___bits___definition.html#ga4188976dbf7f6455ba79d1afd830cf7a',1,'stm32f407xx_matlab.h']]], - ['usart_5fcr2_5fcpol_123',['USART_CR2_CPOL',['../group___peripheral___registers___bits___definition.html#gafbb4336ac93d94d4e78f9fb7b3a0dc68',1,'stm32f407xx_matlab.h']]], - ['usart_5fcr2_5fcpol_5fmsk_124',['USART_CR2_CPOL_Msk',['../group___peripheral___registers___bits___definition.html#ga182e2b837ab775c53868a37a1e4eb05a',1,'stm32f407xx_matlab.h']]], - ['usart_5fcr2_5fcpol_5fpos_125',['USART_CR2_CPOL_Pos',['../group___peripheral___registers___bits___definition.html#ga110f164794e57c70b9d7b0b26577e86a',1,'stm32f407xx_matlab.h']]], - ['usart_5fcr2_5flbcl_126',['USART_CR2_LBCL',['../group___peripheral___registers___bits___definition.html#ga4a62e93ae7864e89622bdd92508b615e',1,'stm32f407xx_matlab.h']]], - ['usart_5fcr2_5flbcl_5fmsk_127',['USART_CR2_LBCL_Msk',['../group___peripheral___registers___bits___definition.html#ga3d515f33359c44365712bfbcf34c7e94',1,'stm32f407xx_matlab.h']]], - ['usart_5fcr2_5flbcl_5fpos_128',['USART_CR2_LBCL_Pos',['../group___peripheral___registers___bits___definition.html#ga0262849ac25bc43d23d46945c85851b0',1,'stm32f407xx_matlab.h']]], - ['usart_5fcr2_5flbdie_129',['USART_CR2_LBDIE',['../group___peripheral___registers___bits___definition.html#gaa02ef5d22553f028ea48e5d9f08192b4',1,'stm32f407xx_matlab.h']]], - ['usart_5fcr2_5flbdie_5fmsk_130',['USART_CR2_LBDIE_Msk',['../group___peripheral___registers___bits___definition.html#gad55383a0b8d928fd50c18c62faf44a7b',1,'stm32f407xx_matlab.h']]], - ['usart_5fcr2_5flbdie_5fpos_131',['USART_CR2_LBDIE_Pos',['../group___peripheral___registers___bits___definition.html#gae9af36362bd69d0008e46a7ea7633b0f',1,'stm32f407xx_matlab.h']]], - ['usart_5fcr2_5flbdl_132',['USART_CR2_LBDL',['../group___peripheral___registers___bits___definition.html#ga7f9bc41700717fd93548e0e95b6072ed',1,'stm32f407xx_matlab.h']]], - ['usart_5fcr2_5flbdl_5fmsk_133',['USART_CR2_LBDL_Msk',['../group___peripheral___registers___bits___definition.html#gad8d54a2e633ef8dda121c9d5670a5de5',1,'stm32f407xx_matlab.h']]], - ['usart_5fcr2_5flbdl_5fpos_134',['USART_CR2_LBDL_Pos',['../group___peripheral___registers___bits___definition.html#gadf0b33cd8b6a3eb4a21bb6c34922a624',1,'stm32f407xx_matlab.h']]], - ['usart_5fcr2_5flinen_135',['USART_CR2_LINEN',['../group___peripheral___registers___bits___definition.html#gac8931efa62c29d92f5c0ec5a05f907ef',1,'stm32f407xx_matlab.h']]], - ['usart_5fcr2_5flinen_5fmsk_136',['USART_CR2_LINEN_Msk',['../group___peripheral___registers___bits___definition.html#ga500c59de0f57986002b962dc9bccfbe8',1,'stm32f407xx_matlab.h']]], - ['usart_5fcr2_5flinen_5fpos_137',['USART_CR2_LINEN_Pos',['../group___peripheral___registers___bits___definition.html#ga4f06b1d9300507573ffbf99f9a6ee57f',1,'stm32f407xx_matlab.h']]], - ['usart_5fcr2_5fstop_138',['USART_CR2_STOP',['../group___peripheral___registers___bits___definition.html#gaf993e483318ebcecffd18649de766dc6',1,'stm32f407xx_matlab.h']]], - ['usart_5fcr2_5fstop_5f0_139',['USART_CR2_STOP_0',['../group___peripheral___registers___bits___definition.html#gaee6ee01c6e5325b378b2209ef20d0a61',1,'stm32f407xx_matlab.h']]], - ['usart_5fcr2_5fstop_5f1_140',['USART_CR2_STOP_1',['../group___peripheral___registers___bits___definition.html#ga2b24d14f0e5d1c76c878b08aad44d02b',1,'stm32f407xx_matlab.h']]], - ['usart_5fcr2_5fstop_5fmsk_141',['USART_CR2_STOP_Msk',['../group___peripheral___registers___bits___definition.html#gaf73b228efa85f04a6b9a42e01b7f916c',1,'stm32f407xx_matlab.h']]], - ['usart_5fcr2_5fstop_5fpos_142',['USART_CR2_STOP_Pos',['../group___peripheral___registers___bits___definition.html#ga4a46b8272a2fe5ae5e5ce7123db22d51',1,'stm32f407xx_matlab.h']]], - ['usart_5fcr3_5fctse_143',['USART_CR3_CTSE',['../group___peripheral___registers___bits___definition.html#gaa125f026b1ca2d76eab48b191baed265',1,'stm32f407xx_matlab.h']]], - ['usart_5fcr3_5fctse_5fmsk_144',['USART_CR3_CTSE_Msk',['../group___peripheral___registers___bits___definition.html#ga97e4c254d292233d827a898bda170fa4',1,'stm32f407xx_matlab.h']]], - ['usart_5fcr3_5fctse_5fpos_145',['USART_CR3_CTSE_Pos',['../group___peripheral___registers___bits___definition.html#gae3bfa28091d9c8781aeb03fcb371dd01',1,'stm32f407xx_matlab.h']]], - ['usart_5fcr3_5fctsie_146',['USART_CR3_CTSIE',['../group___peripheral___registers___bits___definition.html#ga636d5ec2e9556949fc68d13ad45a1e90',1,'stm32f407xx_matlab.h']]], - ['usart_5fcr3_5fctsie_5fmsk_147',['USART_CR3_CTSIE_Msk',['../group___peripheral___registers___bits___definition.html#ga8ca77aa980a93f5b35bf318c20f500cc',1,'stm32f407xx_matlab.h']]], - ['usart_5fcr3_5fctsie_5fpos_148',['USART_CR3_CTSIE_Pos',['../group___peripheral___registers___bits___definition.html#ga660c0090fb7c6c17bce5f15a7b07ce7d',1,'stm32f407xx_matlab.h']]], - ['usart_5fcr3_5fdmar_149',['USART_CR3_DMAR',['../group___peripheral___registers___bits___definition.html#gaff130f15493c765353ec2fd605667c5a',1,'stm32f407xx_matlab.h']]], - ['usart_5fcr3_5fdmar_5fmsk_150',['USART_CR3_DMAR_Msk',['../group___peripheral___registers___bits___definition.html#ga4dd0232a385ce9760635c92556c3eadf',1,'stm32f407xx_matlab.h']]], - ['usart_5fcr3_5fdmar_5fpos_151',['USART_CR3_DMAR_Pos',['../group___peripheral___registers___bits___definition.html#ga173f2f38fdb5ba3db30d3b2686bd9773',1,'stm32f407xx_matlab.h']]], - ['usart_5fcr3_5fdmat_152',['USART_CR3_DMAT',['../group___peripheral___registers___bits___definition.html#ga5bb515d3814d448f84e2c98bf44f3993',1,'stm32f407xx_matlab.h']]], - ['usart_5fcr3_5fdmat_5fmsk_153',['USART_CR3_DMAT_Msk',['../group___peripheral___registers___bits___definition.html#ga114a52251ccd0dae87055bbd336add29',1,'stm32f407xx_matlab.h']]], - ['usart_5fcr3_5fdmat_5fpos_154',['USART_CR3_DMAT_Pos',['../group___peripheral___registers___bits___definition.html#ga00afc87870cbe74aabf127179dedca3f',1,'stm32f407xx_matlab.h']]], - ['usart_5fcr3_5feie_155',['USART_CR3_EIE',['../group___peripheral___registers___bits___definition.html#gaaed1a39c551b1641128f81893ff558d0',1,'stm32f407xx_matlab.h']]], - ['usart_5fcr3_5feie_5fmsk_156',['USART_CR3_EIE_Msk',['../group___peripheral___registers___bits___definition.html#gaac0414669386ae8dd26b993ddf96d7b0',1,'stm32f407xx_matlab.h']]], - ['usart_5fcr3_5feie_5fpos_157',['USART_CR3_EIE_Pos',['../group___peripheral___registers___bits___definition.html#gafeb00f27cc04dab7e9bcca92d6e7ad9e',1,'stm32f407xx_matlab.h']]], - ['usart_5fcr3_5fhdsel_158',['USART_CR3_HDSEL',['../group___peripheral___registers___bits___definition.html#gac71129810fab0b46d91161a39e3f8d01',1,'stm32f407xx_matlab.h']]], - ['usart_5fcr3_5fhdsel_5fmsk_159',['USART_CR3_HDSEL_Msk',['../group___peripheral___registers___bits___definition.html#ga5553c10996ceb918244202407347848d',1,'stm32f407xx_matlab.h']]], - ['usart_5fcr3_5fhdsel_5fpos_160',['USART_CR3_HDSEL_Pos',['../group___peripheral___registers___bits___definition.html#ga7df0071641a9cc2d70e4957c28f923c9',1,'stm32f407xx_matlab.h']]], - ['usart_5fcr3_5firen_161',['USART_CR3_IREN',['../group___peripheral___registers___bits___definition.html#ga31c66373bfbae7724c836ac63b8411dd',1,'stm32f407xx_matlab.h']]], - ['usart_5fcr3_5firen_5fmsk_162',['USART_CR3_IREN_Msk',['../group___peripheral___registers___bits___definition.html#gad3c0575491453dbd478d5a3413ac759c',1,'stm32f407xx_matlab.h']]], - ['usart_5fcr3_5firen_5fpos_163',['USART_CR3_IREN_Pos',['../group___peripheral___registers___bits___definition.html#ga22ce6319d8acdb4a57215aeb933c7a57',1,'stm32f407xx_matlab.h']]], - ['usart_5fcr3_5firlp_164',['USART_CR3_IRLP',['../group___peripheral___registers___bits___definition.html#ga22af8d399f1adda62e31186f0309af80',1,'stm32f407xx_matlab.h']]], - ['usart_5fcr3_5firlp_5fmsk_165',['USART_CR3_IRLP_Msk',['../group___peripheral___registers___bits___definition.html#ga67262b96751aebc3a04d3a6d46213633',1,'stm32f407xx_matlab.h']]], - ['usart_5fcr3_5firlp_5fpos_166',['USART_CR3_IRLP_Pos',['../group___peripheral___registers___bits___definition.html#ga73290a1bb7594fc2016662ba4b927dd5',1,'stm32f407xx_matlab.h']]], - ['usart_5fcr3_5fnack_167',['USART_CR3_NACK',['../group___peripheral___registers___bits___definition.html#ga3f3b70b2ee9ff0b59e952fd7ab04373c',1,'stm32f407xx_matlab.h']]], - ['usart_5fcr3_5fnack_5fmsk_168',['USART_CR3_NACK_Msk',['../group___peripheral___registers___bits___definition.html#ga214ed21d5354e7a14f013fd4954e4d3a',1,'stm32f407xx_matlab.h']]], - ['usart_5fcr3_5fnack_5fpos_169',['USART_CR3_NACK_Pos',['../group___peripheral___registers___bits___definition.html#ga818bd165232f86477503e8f9bc9de049',1,'stm32f407xx_matlab.h']]], - ['usart_5fcr3_5fonebit_170',['USART_CR3_ONEBIT',['../group___peripheral___registers___bits___definition.html#ga9a96fb1a7beab602cbc8cb0393593826',1,'stm32f407xx_matlab.h']]], - ['usart_5fcr3_5fonebit_5fmsk_171',['USART_CR3_ONEBIT_Msk',['../group___peripheral___registers___bits___definition.html#ga09e3e99ce53ca74ca3396b63a51f18ac',1,'stm32f407xx_matlab.h']]], - ['usart_5fcr3_5fonebit_5fpos_172',['USART_CR3_ONEBIT_Pos',['../group___peripheral___registers___bits___definition.html#ga8d9eb170fd3fa98254e243f588e5a068',1,'stm32f407xx_matlab.h']]], - ['usart_5fcr3_5frtse_173',['USART_CR3_RTSE',['../group___peripheral___registers___bits___definition.html#ga7c5d6fcd84a4728cda578a0339b4cac2',1,'stm32f407xx_matlab.h']]], - ['usart_5fcr3_5frtse_5fmsk_174',['USART_CR3_RTSE_Msk',['../group___peripheral___registers___bits___definition.html#gae20cda51a847495ad5f32c5f5c252152',1,'stm32f407xx_matlab.h']]], - ['usart_5fcr3_5frtse_5fpos_175',['USART_CR3_RTSE_Pos',['../group___peripheral___registers___bits___definition.html#ga790491b1c83dd6a84a6f86945cf74563',1,'stm32f407xx_matlab.h']]], - ['usart_5fcr3_5fscen_176',['USART_CR3_SCEN',['../group___peripheral___registers___bits___definition.html#ga9180b9249a26988f71d4bb2b0c3eec27',1,'stm32f407xx_matlab.h']]], - ['usart_5fcr3_5fscen_5fmsk_177',['USART_CR3_SCEN_Msk',['../group___peripheral___registers___bits___definition.html#gaff592b0d891ba78201de2e08cd9305b8',1,'stm32f407xx_matlab.h']]], - ['usart_5fcr3_5fscen_5fpos_178',['USART_CR3_SCEN_Pos',['../group___peripheral___registers___bits___definition.html#gaae269fb759007c1043534a3794f7b98d',1,'stm32f407xx_matlab.h']]], - ['usart_5fdr_5fdr_179',['USART_DR_DR',['../group___peripheral___registers___bits___definition.html#gad84ad1e1d0202b41021e2d6e40486bff',1,'stm32f407xx_matlab.h']]], - ['usart_5fdr_5fdr_5fmsk_180',['USART_DR_DR_Msk',['../group___peripheral___registers___bits___definition.html#ga911912bd628fd1fc33a1d8819d27e81f',1,'stm32f407xx_matlab.h']]], - ['usart_5fdr_5fdr_5fpos_181',['USART_DR_DR_Pos',['../group___peripheral___registers___bits___definition.html#gab1d7d8f36a92c78b93ab1a3e4011b771',1,'stm32f407xx_matlab.h']]], - ['usart_5fgtpr_5fgt_182',['USART_GTPR_GT',['../group___peripheral___registers___bits___definition.html#ga8e927fad0bfa430f54007e158e01f43b',1,'stm32f407xx_matlab.h']]], - ['usart_5fgtpr_5fgt_5fmsk_183',['USART_GTPR_GT_Msk',['../group___peripheral___registers___bits___definition.html#gaddc06fc01cf5031610706007672f2780',1,'stm32f407xx_matlab.h']]], - ['usart_5fgtpr_5fgt_5fpos_184',['USART_GTPR_GT_Pos',['../group___peripheral___registers___bits___definition.html#ga219c2c6c797f288ff792f0b6c792070b',1,'stm32f407xx_matlab.h']]], - ['usart_5fgtpr_5fpsc_185',['USART_GTPR_PSC',['../group___peripheral___registers___bits___definition.html#gaa0b423f0f4baf7d510ea70477e5c9203',1,'stm32f407xx_matlab.h']]], - ['usart_5fgtpr_5fpsc_5f0_186',['USART_GTPR_PSC_0',['../group___peripheral___registers___bits___definition.html#ga2c49c90d83a0e3746b56b2a0a3b0ddcb',1,'stm32f407xx_matlab.h']]], - ['usart_5fgtpr_5fpsc_5f1_187',['USART_GTPR_PSC_1',['../group___peripheral___registers___bits___definition.html#ga8eab5000ab993991d0da8ffbd386c92b',1,'stm32f407xx_matlab.h']]], - ['usart_5fgtpr_5fpsc_5f2_188',['USART_GTPR_PSC_2',['../group___peripheral___registers___bits___definition.html#ga9d74604b6e1ab08a45ea4fe6b3f6b5cd',1,'stm32f407xx_matlab.h']]], - ['usart_5fgtpr_5fpsc_5f3_189',['USART_GTPR_PSC_3',['../group___peripheral___registers___bits___definition.html#ga1b6b237fcac675f8f047c4ff64248486',1,'stm32f407xx_matlab.h']]], - ['usart_5fgtpr_5fpsc_5f4_190',['USART_GTPR_PSC_4',['../group___peripheral___registers___bits___definition.html#gad1c0e92df8edb974008b3d37d12f655a',1,'stm32f407xx_matlab.h']]], - ['usart_5fgtpr_5fpsc_5f5_191',['USART_GTPR_PSC_5',['../group___peripheral___registers___bits___definition.html#ga12dda4877432bc181c9684b0830b1b7b',1,'stm32f407xx_matlab.h']]], - ['usart_5fgtpr_5fpsc_5f6_192',['USART_GTPR_PSC_6',['../group___peripheral___registers___bits___definition.html#ga045e834b03e7a06b2005a13923af424a',1,'stm32f407xx_matlab.h']]], - ['usart_5fgtpr_5fpsc_5f7_193',['USART_GTPR_PSC_7',['../group___peripheral___registers___bits___definition.html#gad3da67d3c9c3abf436098a86477d2dfc',1,'stm32f407xx_matlab.h']]], - ['usart_5fgtpr_5fpsc_5fmsk_194',['USART_GTPR_PSC_Msk',['../group___peripheral___registers___bits___definition.html#ga742100366bd139204afb3402a052a588',1,'stm32f407xx_matlab.h']]], - ['usart_5fgtpr_5fpsc_5fpos_195',['USART_GTPR_PSC_Pos',['../group___peripheral___registers___bits___definition.html#gab09117d544d70ca803eb3831fc86b4a2',1,'stm32f407xx_matlab.h']]], - ['usart_5fsr_5fcts_196',['USART_SR_CTS',['../group___peripheral___registers___bits___definition.html#ga9250ae2793db0541e6c4bb8837424541',1,'stm32f407xx_matlab.h']]], - ['usart_5fsr_5fcts_5fmsk_197',['USART_SR_CTS_Msk',['../group___peripheral___registers___bits___definition.html#ga4d241b440c4595aac4bdf1ffee9c22f9',1,'stm32f407xx_matlab.h']]], - ['usart_5fsr_5fcts_5fpos_198',['USART_SR_CTS_Pos',['../group___peripheral___registers___bits___definition.html#ga8d2b04e34749fc2ef806327e991dcad8',1,'stm32f407xx_matlab.h']]], - ['usart_5fsr_5ffe_199',['USART_SR_FE',['../group___peripheral___registers___bits___definition.html#ga9eb6fd3f820bd12e0b5a981de1894804',1,'stm32f407xx_matlab.h']]], - ['usart_5fsr_5ffe_5fmsk_200',['USART_SR_FE_Msk',['../group___peripheral___registers___bits___definition.html#gad3050686c973903a8821196e0a7166f3',1,'stm32f407xx_matlab.h']]], - ['usart_5fsr_5ffe_5fpos_201',['USART_SR_FE_Pos',['../group___peripheral___registers___bits___definition.html#ga780d79584f83d2873c4026cdaa93d848',1,'stm32f407xx_matlab.h']]], - ['usart_5fsr_5fidle_202',['USART_SR_IDLE',['../group___peripheral___registers___bits___definition.html#ga336fa8c9965ce18c10972ac80ded611f',1,'stm32f407xx_matlab.h']]], - ['usart_5fsr_5fidle_5fmsk_203',['USART_SR_IDLE_Msk',['../group___peripheral___registers___bits___definition.html#gae2b2420f9c84d2adbb47dce8d0e65497',1,'stm32f407xx_matlab.h']]], - ['usart_5fsr_5fidle_5fpos_204',['USART_SR_IDLE_Pos',['../group___peripheral___registers___bits___definition.html#gae2a7cf252454c0c27e5d4327bbd3206f',1,'stm32f407xx_matlab.h']]], - ['usart_5fsr_5flbd_205',['USART_SR_LBD',['../group___peripheral___registers___bits___definition.html#ga5b868b59576f42421226d35628c6b628',1,'stm32f407xx_matlab.h']]], - ['usart_5fsr_5flbd_5fmsk_206',['USART_SR_LBD_Msk',['../group___peripheral___registers___bits___definition.html#ga233a2963e3a24a14f98865224183d93d',1,'stm32f407xx_matlab.h']]], - ['usart_5fsr_5flbd_5fpos_207',['USART_SR_LBD_Pos',['../group___peripheral___registers___bits___definition.html#gae347aead943d5b4c1044a226380b3fda',1,'stm32f407xx_matlab.h']]], - ['usart_5fsr_5fne_208',['USART_SR_NE',['../group___peripheral___registers___bits___definition.html#ga8938468c5666a8305ade6d80d467c572',1,'stm32f407xx_matlab.h']]], - ['usart_5fsr_5fne_5fmsk_209',['USART_SR_NE_Msk',['../group___peripheral___registers___bits___definition.html#ga4150c4eff1939e0c1c474dce82ed76bf',1,'stm32f407xx_matlab.h']]], - ['usart_5fsr_5fne_5fpos_210',['USART_SR_NE_Pos',['../group___peripheral___registers___bits___definition.html#ga92528c798c4fa8ecfda09d6058cbb7f3',1,'stm32f407xx_matlab.h']]], - ['usart_5fsr_5fore_211',['USART_SR_ORE',['../group___peripheral___registers___bits___definition.html#ga4560fc7a60df4bdf402fc7219ae7b558',1,'stm32f407xx_matlab.h']]], - ['usart_5fsr_5fore_5fmsk_212',['USART_SR_ORE_Msk',['../group___peripheral___registers___bits___definition.html#ga654b0cd0fb1fdf02de8f1af223eca9d5',1,'stm32f407xx_matlab.h']]], - ['usart_5fsr_5fore_5fpos_213',['USART_SR_ORE_Pos',['../group___peripheral___registers___bits___definition.html#ga1413d933bfe380829bd883ce5ae6f27b',1,'stm32f407xx_matlab.h']]], - ['usart_5fsr_5fpe_214',['USART_SR_PE',['../group___peripheral___registers___bits___definition.html#gac88be3484245af8c1b271ae5c1b97a14',1,'stm32f407xx_matlab.h']]], - ['usart_5fsr_5fpe_5fmsk_215',['USART_SR_PE_Msk',['../group___peripheral___registers___bits___definition.html#ga83b7f81b87e70796a8cffaae0eb9ba9a',1,'stm32f407xx_matlab.h']]], - ['usart_5fsr_5fpe_5fpos_216',['USART_SR_PE_Pos',['../group___peripheral___registers___bits___definition.html#ga0635e2ab8eac81f2a10164602121ccf2',1,'stm32f407xx_matlab.h']]], - ['usart_5fsr_5frxne_217',['USART_SR_RXNE',['../group___peripheral___registers___bits___definition.html#gaa0c99e2bb265b3d58a91aca7a93f7836',1,'stm32f407xx_matlab.h']]], - ['usart_5fsr_5frxne_5fmsk_218',['USART_SR_RXNE_Msk',['../group___peripheral___registers___bits___definition.html#ga64611f0aa4ba3dcafb6d934e831279e9',1,'stm32f407xx_matlab.h']]], - ['usart_5fsr_5frxne_5fpos_219',['USART_SR_RXNE_Pos',['../group___peripheral___registers___bits___definition.html#gaf5895ff1c2d076cb10c291c873eedc55',1,'stm32f407xx_matlab.h']]], - ['usart_5fsr_5ftc_220',['USART_SR_TC',['../group___peripheral___registers___bits___definition.html#ga76229b05ac37a5a688e6ba45851a29f1',1,'stm32f407xx_matlab.h']]], - ['usart_5fsr_5ftc_5fmsk_221',['USART_SR_TC_Msk',['../group___peripheral___registers___bits___definition.html#ga972584d838f708691ef3c153ad8233ac',1,'stm32f407xx_matlab.h']]], - ['usart_5fsr_5ftc_5fpos_222',['USART_SR_TC_Pos',['../group___peripheral___registers___bits___definition.html#gac8cdb6c85343e4287d5c07bcff25d58e',1,'stm32f407xx_matlab.h']]], - ['usart_5fsr_5ftxe_223',['USART_SR_TXE',['../group___peripheral___registers___bits___definition.html#ga65e9cddf0890113d405342f1d8b5b980',1,'stm32f407xx_matlab.h']]], - ['usart_5fsr_5ftxe_5fmsk_224',['USART_SR_TXE_Msk',['../group___peripheral___registers___bits___definition.html#gabe75a9021a84919f6c1ea3e3c08a23e0',1,'stm32f407xx_matlab.h']]], - ['usart_5fsr_5ftxe_5fpos_225',['USART_SR_TXE_Pos',['../group___peripheral___registers___bits___definition.html#gaa708cd1b36e1ee1cfed89e85620a7c00',1,'stm32f407xx_matlab.h']]], - ['usart_5ftypedef_226',['USART_TypeDef',['../struct_u_s_a_r_t___type_def.html',1,'']]], - ['usb_5fotg_5fbcnt_227',['USB_OTG_BCNT',['../group___peripheral___registers___bits___definition.html#ga85cc2bdcb428f49f2de38db43a6da61b',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fbcnt_5fmsk_228',['USB_OTG_BCNT_Msk',['../group___peripheral___registers___bits___definition.html#ga8835a43d2c40f61caee8af97be8de8d3',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fbcnt_5fpos_229',['USB_OTG_BCNT_Pos',['../group___peripheral___registers___bits___definition.html#gace8389218deec60cbc2cc42db1ff5870',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fchnum_230',['USB_OTG_CHNUM',['../group___peripheral___registers___bits___definition.html#ga5e22ae686ec18ff21f8f576178463115',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fchnum_5f0_231',['USB_OTG_CHNUM_0',['../group___peripheral___registers___bits___definition.html#ga1901249182b97582cbe4a3644f31d20f',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fchnum_5f1_232',['USB_OTG_CHNUM_1',['../group___peripheral___registers___bits___definition.html#gabda64fd2296cefde4a9f304c0b5150e3',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fchnum_5f2_233',['USB_OTG_CHNUM_2',['../group___peripheral___registers___bits___definition.html#ga0e852ea3f7aca27ba6cd281d1fdc5117',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fchnum_5f3_234',['USB_OTG_CHNUM_3',['../group___peripheral___registers___bits___definition.html#ga045af9896fe21c27d155de0bb98eb3bb',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fchnum_5fmsk_235',['USB_OTG_CHNUM_Msk',['../group___peripheral___registers___bits___definition.html#ga46419059b5b49059f5bdebe1b72722ef',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fchnum_5fpos_236',['USB_OTG_CHNUM_Pos',['../group___peripheral___registers___bits___definition.html#ga45900186e59c0e66989c65180095d603',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fcid_5fproduct_5fid_237',['USB_OTG_CID_PRODUCT_ID',['../group___peripheral___registers___bits___definition.html#ga2bad40ec1b2cb101eaa49a5605f7a097',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fcid_5fproduct_5fid_5fmsk_238',['USB_OTG_CID_PRODUCT_ID_Msk',['../group___peripheral___registers___bits___definition.html#ga2c0749f0863635f439e2d8b760eeee17',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fcid_5fproduct_5fid_5fpos_239',['USB_OTG_CID_PRODUCT_ID_Pos',['../group___peripheral___registers___bits___definition.html#ga812e14aa406ecfa45f30df73aacbd611',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdaint_5fiepint_240',['USB_OTG_DAINT_IEPINT',['../group___peripheral___registers___bits___definition.html#gac640d7686606412f8b3593fc3bc76976',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdaint_5fiepint_5fmsk_241',['USB_OTG_DAINT_IEPINT_Msk',['../group___peripheral___registers___bits___definition.html#ga0458c7203562b2f88f6301ee5914b5be',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdaint_5fiepint_5fpos_242',['USB_OTG_DAINT_IEPINT_Pos',['../group___peripheral___registers___bits___definition.html#gae63137414d813c9639e678ce3f59d214',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdaint_5foepint_243',['USB_OTG_DAINT_OEPINT',['../group___peripheral___registers___bits___definition.html#gad1da6e6b0cb689727710c7c23162fb5d',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdaint_5foepint_5fmsk_244',['USB_OTG_DAINT_OEPINT_Msk',['../group___peripheral___registers___bits___definition.html#gaae1224c9e9728d40025d9326e31a0c6b',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdaint_5foepint_5fpos_245',['USB_OTG_DAINT_OEPINT_Pos',['../group___peripheral___registers___bits___definition.html#ga25afe9767c710d1e25db2f40719e2d1e',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdaintmsk_5fiepm_246',['USB_OTG_DAINTMSK_IEPM',['../group___peripheral___registers___bits___definition.html#gaa9eaacec55a1e6d5ea06babfacf6a77c',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdaintmsk_5fiepm_5fmsk_247',['USB_OTG_DAINTMSK_IEPM_Msk',['../group___peripheral___registers___bits___definition.html#gafff61f58b2d93be3d36f44794981e80c',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdaintmsk_5fiepm_5fpos_248',['USB_OTG_DAINTMSK_IEPM_Pos',['../group___peripheral___registers___bits___definition.html#ga7c30ee057efc639e21534e6d8cff9a1f',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdaintmsk_5foepm_249',['USB_OTG_DAINTMSK_OEPM',['../group___peripheral___registers___bits___definition.html#gad1e90f8633158170a810a7b739d280aa',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdaintmsk_5foepm_5fmsk_250',['USB_OTG_DAINTMSK_OEPM_Msk',['../group___peripheral___registers___bits___definition.html#ga86dad56d8d5e8ced81ff1486b8f8b82c',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdaintmsk_5foepm_5fpos_251',['USB_OTG_DAINTMSK_OEPM_Pos',['../group___peripheral___registers___bits___definition.html#ga24fb9df620319cb9d09fb93822cf9673',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdcfg_5fdad_252',['USB_OTG_DCFG_DAD',['../group___peripheral___registers___bits___definition.html#gaf9fd5819883e2d18cad4c19af8146e1d',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdcfg_5fdad_5f0_253',['USB_OTG_DCFG_DAD_0',['../group___peripheral___registers___bits___definition.html#ga34aa0076cdeff59113e9880458ae79ba',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdcfg_5fdad_5f1_254',['USB_OTG_DCFG_DAD_1',['../group___peripheral___registers___bits___definition.html#ga646ba21ce25f42e2fbf706295a5ad031',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdcfg_5fdad_5f2_255',['USB_OTG_DCFG_DAD_2',['../group___peripheral___registers___bits___definition.html#ga2d495202852341acc620ce02043281a6',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdcfg_5fdad_5f3_256',['USB_OTG_DCFG_DAD_3',['../group___peripheral___registers___bits___definition.html#ga1fa407810d17c7f3795fe268bd01120b',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdcfg_5fdad_5f4_257',['USB_OTG_DCFG_DAD_4',['../group___peripheral___registers___bits___definition.html#ga72351ad7cdbbd7992f70892b49a2a669',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdcfg_5fdad_5f5_258',['USB_OTG_DCFG_DAD_5',['../group___peripheral___registers___bits___definition.html#ga61f0d5b909af5196782bbe6e03855f06',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdcfg_5fdad_5f6_259',['USB_OTG_DCFG_DAD_6',['../group___peripheral___registers___bits___definition.html#gaae949fe90d15c793eb011958a4f600ac',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdcfg_5fdad_5fmsk_260',['USB_OTG_DCFG_DAD_Msk',['../group___peripheral___registers___bits___definition.html#ga67fabe86ac6ef650b9ad01a026b67a5d',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdcfg_5fdad_5fpos_261',['USB_OTG_DCFG_DAD_Pos',['../group___peripheral___registers___bits___definition.html#gae76878ba65b726eb3baca6db5a9c4397',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdcfg_5fdspd_262',['USB_OTG_DCFG_DSPD',['../group___peripheral___registers___bits___definition.html#ga6f008e2b969946597b56824fef3cc7ef',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdcfg_5fdspd_5f0_263',['USB_OTG_DCFG_DSPD_0',['../group___peripheral___registers___bits___definition.html#ga5f73c1cb1213fd6e28ce7409fc3c63d1',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdcfg_5fdspd_5f1_264',['USB_OTG_DCFG_DSPD_1',['../group___peripheral___registers___bits___definition.html#gab7d4f6f3e5002c73be03457ab3ac4023',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdcfg_5fdspd_5fmsk_265',['USB_OTG_DCFG_DSPD_Msk',['../group___peripheral___registers___bits___definition.html#ga0b6bf36ee06f07105efb0568bfb3c06d',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdcfg_5fdspd_5fpos_266',['USB_OTG_DCFG_DSPD_Pos',['../group___peripheral___registers___bits___definition.html#ga0f814fca4fbed44bc00dc4fd248cba7f',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdcfg_5ferratim_267',['USB_OTG_DCFG_ERRATIM',['../group___peripheral___registers___bits___definition.html#ga36b7cce75bb4e60fe38760c78167b2ac',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdcfg_5ferratim_5fmsk_268',['USB_OTG_DCFG_ERRATIM_Msk',['../group___peripheral___registers___bits___definition.html#gacd12755447b5773fd5db5b71b5ea292a',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdcfg_5ferratim_5fpos_269',['USB_OTG_DCFG_ERRATIM_Pos',['../group___peripheral___registers___bits___definition.html#gaa6e3c2d9632a9ab98fae27f4e1de639c',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdcfg_5fnzlsohsk_270',['USB_OTG_DCFG_NZLSOHSK',['../group___peripheral___registers___bits___definition.html#ga7c492b6fc8389b58b1879aa7d822137f',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdcfg_5fnzlsohsk_5fmsk_271',['USB_OTG_DCFG_NZLSOHSK_Msk',['../group___peripheral___registers___bits___definition.html#gaaa785273cbe79b53e609ed2715cfbf98',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdcfg_5fnzlsohsk_5fpos_272',['USB_OTG_DCFG_NZLSOHSK_Pos',['../group___peripheral___registers___bits___definition.html#ga7e34cb67fa67ee5ea04ca8ade51d10e5',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdcfg_5fperschivl_273',['USB_OTG_DCFG_PERSCHIVL',['../group___peripheral___registers___bits___definition.html#ga8fb78d02bad573871d6b9d92100561a4',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdcfg_5fperschivl_5f0_274',['USB_OTG_DCFG_PERSCHIVL_0',['../group___peripheral___registers___bits___definition.html#ga4eef8bf8e73d8b94b0caf98caa978c11',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdcfg_5fperschivl_5f1_275',['USB_OTG_DCFG_PERSCHIVL_1',['../group___peripheral___registers___bits___definition.html#ga4e47455432a6c8c7c7400024427c25d8',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdcfg_5fperschivl_5fmsk_276',['USB_OTG_DCFG_PERSCHIVL_Msk',['../group___peripheral___registers___bits___definition.html#ga4407194cfda70b7408523c537ba03060',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdcfg_5fperschivl_5fpos_277',['USB_OTG_DCFG_PERSCHIVL_Pos',['../group___peripheral___registers___bits___definition.html#gad22746397a7c2cfeba819d38a172c212',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdcfg_5fpfivl_278',['USB_OTG_DCFG_PFIVL',['../group___peripheral___registers___bits___definition.html#ga08ae423d6325aa35bb037304ba8f8235',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdcfg_5fpfivl_5f0_279',['USB_OTG_DCFG_PFIVL_0',['../group___peripheral___registers___bits___definition.html#gaf4e78c573f8cd0548bce86ce8593353d',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdcfg_5fpfivl_5f1_280',['USB_OTG_DCFG_PFIVL_1',['../group___peripheral___registers___bits___definition.html#gab9cc973db831fb86b1e122443a58aa7c',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdcfg_5fpfivl_5fmsk_281',['USB_OTG_DCFG_PFIVL_Msk',['../group___peripheral___registers___bits___definition.html#ga273b5f0a16f8276d0f0e76f216caa03f',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdcfg_5fpfivl_5fpos_282',['USB_OTG_DCFG_PFIVL_Pos',['../group___peripheral___registers___bits___definition.html#ga27759af8c6692f16b6fd717fba4c7fd1',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdcfg_5fxcvrdly_283',['USB_OTG_DCFG_XCVRDLY',['../group___peripheral___registers___bits___definition.html#ga0fbc004fabda6fa9cda2977d45755e42',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdcfg_5fxcvrdly_5fmsk_284',['USB_OTG_DCFG_XCVRDLY_Msk',['../group___peripheral___registers___bits___definition.html#gac9a4c6ac40e44ccfe90a65c583c202b2',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdcfg_5fxcvrdly_5fpos_285',['USB_OTG_DCFG_XCVRDLY_Pos',['../group___peripheral___registers___bits___definition.html#gad13016a80c9fcb7f2219d7d6c5a15420',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdctl_5fcginak_286',['USB_OTG_DCTL_CGINAK',['../group___peripheral___registers___bits___definition.html#ga200f87e323c35612737fbaeb7b1c52f2',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdctl_5fcginak_5fmsk_287',['USB_OTG_DCTL_CGINAK_Msk',['../group___peripheral___registers___bits___definition.html#ga45fb8854f9cb1d9e5aa9b55e4392af8b',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdctl_5fcginak_5fpos_288',['USB_OTG_DCTL_CGINAK_Pos',['../group___peripheral___registers___bits___definition.html#ga2110acce46d292ea06baa8816332b516',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdctl_5fcgonak_289',['USB_OTG_DCTL_CGONAK',['../group___peripheral___registers___bits___definition.html#ga232f28bae3c9cd354b2fca1be518d043',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdctl_5fcgonak_5fmsk_290',['USB_OTG_DCTL_CGONAK_Msk',['../group___peripheral___registers___bits___definition.html#ga07b9fd237b82bf4b3556a7a344a0058c',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdctl_5fcgonak_5fpos_291',['USB_OTG_DCTL_CGONAK_Pos',['../group___peripheral___registers___bits___definition.html#ga57d32c2416c40902c1095f2e3e84c2c1',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdctl_5fginsts_292',['USB_OTG_DCTL_GINSTS',['../group___peripheral___registers___bits___definition.html#ga6d3d6c5c6827fad61f6f8fa5553935fa',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdctl_5fginsts_5fmsk_293',['USB_OTG_DCTL_GINSTS_Msk',['../group___peripheral___registers___bits___definition.html#gaf928315cb36f5a39a14f58cb15468ec8',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdctl_5fginsts_5fpos_294',['USB_OTG_DCTL_GINSTS_Pos',['../group___peripheral___registers___bits___definition.html#ga5b3fab019e98600e57b4416eff4b0c6c',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdctl_5fgonsts_295',['USB_OTG_DCTL_GONSTS',['../group___peripheral___registers___bits___definition.html#ga199625403480a432df8f653b9bee0bd4',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdctl_5fgonsts_5fmsk_296',['USB_OTG_DCTL_GONSTS_Msk',['../group___peripheral___registers___bits___definition.html#gaa880c9c7c5ee16534e0156380cf04d28',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdctl_5fgonsts_5fpos_297',['USB_OTG_DCTL_GONSTS_Pos',['../group___peripheral___registers___bits___definition.html#ga62e7c5f4b5a7e317f9691805596a54cb',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdctl_5fpoprgdne_298',['USB_OTG_DCTL_POPRGDNE',['../group___peripheral___registers___bits___definition.html#gace837326945cc056aef6969fc24e1a09',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdctl_5fpoprgdne_5fmsk_299',['USB_OTG_DCTL_POPRGDNE_Msk',['../group___peripheral___registers___bits___definition.html#gac2daaa82f3b3ea2bbfb3c0677c46b93b',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdctl_5fpoprgdne_5fpos_300',['USB_OTG_DCTL_POPRGDNE_Pos',['../group___peripheral___registers___bits___definition.html#ga607c004ead13d867f5712fc7c46d335d',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdctl_5frwusig_301',['USB_OTG_DCTL_RWUSIG',['../group___peripheral___registers___bits___definition.html#ga8e87febbcda52c3b0b4679ce4fc10aae',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdctl_5frwusig_5fmsk_302',['USB_OTG_DCTL_RWUSIG_Msk',['../group___peripheral___registers___bits___definition.html#ga6caa072b60a7c1c580d47f5ac1d4a63d',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdctl_5frwusig_5fpos_303',['USB_OTG_DCTL_RWUSIG_Pos',['../group___peripheral___registers___bits___definition.html#ga4c2fa606dfe64d8839dbfd7cb059eb1f',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdctl_5fsdis_304',['USB_OTG_DCTL_SDIS',['../group___peripheral___registers___bits___definition.html#ga148c9f1be1abbca2c8568a079894c9d0',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdctl_5fsdis_5fmsk_305',['USB_OTG_DCTL_SDIS_Msk',['../group___peripheral___registers___bits___definition.html#ga34f43895b41cdf03141fd07278679e9c',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdctl_5fsdis_5fpos_306',['USB_OTG_DCTL_SDIS_Pos',['../group___peripheral___registers___bits___definition.html#gaebac09e13aa5eb753c567253f7a7be17',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdctl_5fsginak_307',['USB_OTG_DCTL_SGINAK',['../group___peripheral___registers___bits___definition.html#gafde278c400411575329026a0a8a67fa0',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdctl_5fsginak_5fmsk_308',['USB_OTG_DCTL_SGINAK_Msk',['../group___peripheral___registers___bits___definition.html#gaa822717fd13eed433f8496f8c0b81482',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdctl_5fsginak_5fpos_309',['USB_OTG_DCTL_SGINAK_Pos',['../group___peripheral___registers___bits___definition.html#ga3a6d0efe73a56eb7e63594717cd3784e',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdctl_5fsgonak_310',['USB_OTG_DCTL_SGONAK',['../group___peripheral___registers___bits___definition.html#ga717ea6d52263b0b9938ebf1f3ef4b409',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdctl_5fsgonak_5fmsk_311',['USB_OTG_DCTL_SGONAK_Msk',['../group___peripheral___registers___bits___definition.html#ga54678325db99694db585d8ec50f46ae6',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdctl_5fsgonak_5fpos_312',['USB_OTG_DCTL_SGONAK_Pos',['../group___peripheral___registers___bits___definition.html#ga7701014b6f5ba7a52bd48e8c8a1d1821',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdctl_5ftctl_313',['USB_OTG_DCTL_TCTL',['../group___peripheral___registers___bits___definition.html#gaebcf7c6c98c93f075f635cf0969c16f4',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdctl_5ftctl_5f0_314',['USB_OTG_DCTL_TCTL_0',['../group___peripheral___registers___bits___definition.html#ga48750394a0e7d020b3b1e4c4b73b981f',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdctl_5ftctl_5f1_315',['USB_OTG_DCTL_TCTL_1',['../group___peripheral___registers___bits___definition.html#ga27636cb092fce5a35e0dd25debc50294',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdctl_5ftctl_5f2_316',['USB_OTG_DCTL_TCTL_2',['../group___peripheral___registers___bits___definition.html#ga82ad49a50f4cb5a7c310e94d92daa889',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdctl_5ftctl_5fmsk_317',['USB_OTG_DCTL_TCTL_Msk',['../group___peripheral___registers___bits___definition.html#gad771cd9b6f19e1f335016426d41dec48',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdctl_5ftctl_5fpos_318',['USB_OTG_DCTL_TCTL_Pos',['../group___peripheral___registers___bits___definition.html#gaf2949c49bf972e4db35cd85649ccb3c6',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdeachint_5fiep1int_319',['USB_OTG_DEACHINT_IEP1INT',['../group___peripheral___registers___bits___definition.html#gadc58bf6e4389a56f5482f3c3b9f0afae',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdeachint_5fiep1int_5fmsk_320',['USB_OTG_DEACHINT_IEP1INT_Msk',['../group___peripheral___registers___bits___definition.html#gad029d48387a2d3e0e29661bab1848c41',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdeachint_5fiep1int_5fpos_321',['USB_OTG_DEACHINT_IEP1INT_Pos',['../group___peripheral___registers___bits___definition.html#ga199c8da83c26360084406b7ead8f5d3b',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdeachint_5foep1int_322',['USB_OTG_DEACHINT_OEP1INT',['../group___peripheral___registers___bits___definition.html#ga303cb170236d7f710cc125fb1af37179',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdeachint_5foep1int_5fmsk_323',['USB_OTG_DEACHINT_OEP1INT_Msk',['../group___peripheral___registers___bits___definition.html#ga15176fb77b4e56480776944239113e2d',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdeachint_5foep1int_5fpos_324',['USB_OTG_DEACHINT_OEP1INT_Pos',['../group___peripheral___registers___bits___definition.html#ga68088b39445739349ceaf47186f57b80',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdeachintmsk_5fiep1intm_325',['USB_OTG_DEACHINTMSK_IEP1INTM',['../group___peripheral___registers___bits___definition.html#ga258a2e60f2796217e28607252d4c57bf',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdeachintmsk_5fiep1intm_5fmsk_326',['USB_OTG_DEACHINTMSK_IEP1INTM_Msk',['../group___peripheral___registers___bits___definition.html#gaa8771cbb994263301333d9847621094e',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdeachintmsk_5fiep1intm_5fpos_327',['USB_OTG_DEACHINTMSK_IEP1INTM_Pos',['../group___peripheral___registers___bits___definition.html#ga2ee42186200d9099506cd4c8f877eba3',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdeachintmsk_5foep1intm_328',['USB_OTG_DEACHINTMSK_OEP1INTM',['../group___peripheral___registers___bits___definition.html#ga1fc88b5e76ded044e77ec4bebbe91ec5',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdeachintmsk_5foep1intm_5fmsk_329',['USB_OTG_DEACHINTMSK_OEP1INTM_Msk',['../group___peripheral___registers___bits___definition.html#ga429749723f28d5ac2c69768ec5340d17',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdeachintmsk_5foep1intm_5fpos_330',['USB_OTG_DEACHINTMSK_OEP1INTM_Pos',['../group___peripheral___registers___bits___definition.html#ga2ddea2717e85931ae3085ef697f30311',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdevice_5fbase_331',['USB_OTG_DEVICE_BASE',['../group___peripheral__memory__map.html#ga4d74a337597a77b1fca978202b519a18',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdevicetypedef_332',['USB_OTG_DeviceTypeDef',['../struct_u_s_b___o_t_g___device_type_def.html',1,'']]], - ['usb_5fotg_5fdiepctl_5fcnak_333',['USB_OTG_DIEPCTL_CNAK',['../group___peripheral___registers___bits___definition.html#gab7aa93621e2379266fd2901742f9d652',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdiepctl_5fcnak_5fmsk_334',['USB_OTG_DIEPCTL_CNAK_Msk',['../group___peripheral___registers___bits___definition.html#ga4398c0cf3ff27735935e0ec567d28dcc',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdiepctl_5fcnak_5fpos_335',['USB_OTG_DIEPCTL_CNAK_Pos',['../group___peripheral___registers___bits___definition.html#ga34262b1369356b472f2f5fd07ab00329',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdiepctl_5feonum_5fdpid_336',['USB_OTG_DIEPCTL_EONUM_DPID',['../group___peripheral___registers___bits___definition.html#ga1f908cbb98598542f631c746bc3a85a1',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdiepctl_5feonum_5fdpid_5fmsk_337',['USB_OTG_DIEPCTL_EONUM_DPID_Msk',['../group___peripheral___registers___bits___definition.html#gab4d849a015e877f7b9e4a82291a9997b',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdiepctl_5feonum_5fdpid_5fpos_338',['USB_OTG_DIEPCTL_EONUM_DPID_Pos',['../group___peripheral___registers___bits___definition.html#gae4ea8a7d612c65303a2d6e6c89a6e99c',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdiepctl_5fepdis_339',['USB_OTG_DIEPCTL_EPDIS',['../group___peripheral___registers___bits___definition.html#ga9cc396ddf6cd0c0781acec4e278aa815',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdiepctl_5fepdis_5fmsk_340',['USB_OTG_DIEPCTL_EPDIS_Msk',['../group___peripheral___registers___bits___definition.html#ga6c56726a11ab538f4108a37ffd15f254',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdiepctl_5fepdis_5fpos_341',['USB_OTG_DIEPCTL_EPDIS_Pos',['../group___peripheral___registers___bits___definition.html#ga2daf3ac53bfdfdbb7835126c245b34c2',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdiepctl_5fepena_342',['USB_OTG_DIEPCTL_EPENA',['../group___peripheral___registers___bits___definition.html#gad6951a1febc2510628114a0297170bce',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdiepctl_5fepena_5fmsk_343',['USB_OTG_DIEPCTL_EPENA_Msk',['../group___peripheral___registers___bits___definition.html#gab5eb8f53ab834ffe44f784baab031791',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdiepctl_5fepena_5fpos_344',['USB_OTG_DIEPCTL_EPENA_Pos',['../group___peripheral___registers___bits___definition.html#ga465665c0a5926a0b27ec5288e46d2394',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdiepctl_5feptyp_345',['USB_OTG_DIEPCTL_EPTYP',['../group___peripheral___registers___bits___definition.html#ga2fc1b4e978ef3a22450da75f2608dff2',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdiepctl_5feptyp_5f0_346',['USB_OTG_DIEPCTL_EPTYP_0',['../group___peripheral___registers___bits___definition.html#ga4da4d418faa4245347a4ad3c1b8334d9',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdiepctl_5feptyp_5f1_347',['USB_OTG_DIEPCTL_EPTYP_1',['../group___peripheral___registers___bits___definition.html#gae2ca76cb985239ed613062b1087075ab',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdiepctl_5feptyp_5fmsk_348',['USB_OTG_DIEPCTL_EPTYP_Msk',['../group___peripheral___registers___bits___definition.html#gaf416ce016be26169bcb25b1eea153f08',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdiepctl_5feptyp_5fpos_349',['USB_OTG_DIEPCTL_EPTYP_Pos',['../group___peripheral___registers___bits___definition.html#gaadfa549c62330bf01de4ddb187ce5e96',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdiepctl_5fmpsiz_350',['USB_OTG_DIEPCTL_MPSIZ',['../group___peripheral___registers___bits___definition.html#gabda35dcaaa3faa8443bec36b9edc438e',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdiepctl_5fmpsiz_5fmsk_351',['USB_OTG_DIEPCTL_MPSIZ_Msk',['../group___peripheral___registers___bits___definition.html#ga9ea4a7999fe1ba166d761a56a5f045aa',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdiepctl_5fmpsiz_5fpos_352',['USB_OTG_DIEPCTL_MPSIZ_Pos',['../group___peripheral___registers___bits___definition.html#ga6f340944f765c7e6ed22c40b337d8fc1',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdiepctl_5fnaksts_353',['USB_OTG_DIEPCTL_NAKSTS',['../group___peripheral___registers___bits___definition.html#ga3aa35782f7d920f0c6520db137bce768',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdiepctl_5fnaksts_5fmsk_354',['USB_OTG_DIEPCTL_NAKSTS_Msk',['../group___peripheral___registers___bits___definition.html#ga48e2e960476f1b5e1e205bef19c30b5b',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdiepctl_5fnaksts_5fpos_355',['USB_OTG_DIEPCTL_NAKSTS_Pos',['../group___peripheral___registers___bits___definition.html#ga78ccc71651a434402bef238206f3cd32',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdiepctl_5fsd0pid_5fsevnfrm_356',['USB_OTG_DIEPCTL_SD0PID_SEVNFRM',['../group___peripheral___registers___bits___definition.html#gac5ea132b2710076fcc0ef9ebaffe7e1e',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdiepctl_5fsd0pid_5fsevnfrm_5fmsk_357',['USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk',['../group___peripheral___registers___bits___definition.html#ga7cabb03e5a98b0496a9f019d337362dc',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdiepctl_5fsd0pid_5fsevnfrm_5fpos_358',['USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos',['../group___peripheral___registers___bits___definition.html#gaaa2ed3b1957b14db8a12ba9553356607',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdiepctl_5fsnak_359',['USB_OTG_DIEPCTL_SNAK',['../group___peripheral___registers___bits___definition.html#ga04939f2cc7cab01a34b516197883c542',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdiepctl_5fsnak_5fmsk_360',['USB_OTG_DIEPCTL_SNAK_Msk',['../group___peripheral___registers___bits___definition.html#ga79c45bf1dcfa6b08ee039f3dde83926a',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdiepctl_5fsnak_5fpos_361',['USB_OTG_DIEPCTL_SNAK_Pos',['../group___peripheral___registers___bits___definition.html#gae02f66b28850f4cde25bc3c4d844d7f5',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdiepctl_5fsoddfrm_362',['USB_OTG_DIEPCTL_SODDFRM',['../group___peripheral___registers___bits___definition.html#gae874b1d1b15b4ada193bab411634a37a',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdiepctl_5fsoddfrm_5fmsk_363',['USB_OTG_DIEPCTL_SODDFRM_Msk',['../group___peripheral___registers___bits___definition.html#ga06e1743fc6505d240ba8929c579a807a',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdiepctl_5fsoddfrm_5fpos_364',['USB_OTG_DIEPCTL_SODDFRM_Pos',['../group___peripheral___registers___bits___definition.html#gad2f39c24ed8d37c04b07b7decd807af2',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdiepctl_5fstall_365',['USB_OTG_DIEPCTL_STALL',['../group___peripheral___registers___bits___definition.html#gab313ac4b4a0d85f45af3733d574cb9a9',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdiepctl_5fstall_5fmsk_366',['USB_OTG_DIEPCTL_STALL_Msk',['../group___peripheral___registers___bits___definition.html#ga72b289fbf1a810cefd61091e9affcf62',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdiepctl_5fstall_5fpos_367',['USB_OTG_DIEPCTL_STALL_Pos',['../group___peripheral___registers___bits___definition.html#ga740abf97e28d1670808797448f75d062',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdiepctl_5ftxfnum_368',['USB_OTG_DIEPCTL_TXFNUM',['../group___peripheral___registers___bits___definition.html#gad2a4ce33e0e644c9439c9cce59b2edfa',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdiepctl_5ftxfnum_5f0_369',['USB_OTG_DIEPCTL_TXFNUM_0',['../group___peripheral___registers___bits___definition.html#gaf0cd18c0071ac8c9676fbc010a07ef49',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdiepctl_5ftxfnum_5f1_370',['USB_OTG_DIEPCTL_TXFNUM_1',['../group___peripheral___registers___bits___definition.html#ga3e710b13ec4621897335fe9e18c7398c',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdiepctl_5ftxfnum_5f2_371',['USB_OTG_DIEPCTL_TXFNUM_2',['../group___peripheral___registers___bits___definition.html#ga1bf5811bde53bd29c3c91ab07fdc2a5b',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdiepctl_5ftxfnum_5f3_372',['USB_OTG_DIEPCTL_TXFNUM_3',['../group___peripheral___registers___bits___definition.html#gae67a96234e062d1304a4af3afc938164',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdiepctl_5ftxfnum_5fmsk_373',['USB_OTG_DIEPCTL_TXFNUM_Msk',['../group___peripheral___registers___bits___definition.html#ga6e8e627baaad5f7ed0176d106ec0f43a',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdiepctl_5ftxfnum_5fpos_374',['USB_OTG_DIEPCTL_TXFNUM_Pos',['../group___peripheral___registers___bits___definition.html#ga84597138dd8b05b14b586fd8d51013ff',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdiepctl_5fusbaep_375',['USB_OTG_DIEPCTL_USBAEP',['../group___peripheral___registers___bits___definition.html#ga52604d4a0d7b24ad619a2860003e8fe3',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdiepctl_5fusbaep_5fmsk_376',['USB_OTG_DIEPCTL_USBAEP_Msk',['../group___peripheral___registers___bits___definition.html#gaf2847317d82bfe14ae48839902c177dd',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdiepctl_5fusbaep_5fpos_377',['USB_OTG_DIEPCTL_USBAEP_Pos',['../group___peripheral___registers___bits___definition.html#gad3259dc5bb86cce573ba8469dc82573f',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdiepdma_5fdmaaddr_378',['USB_OTG_DIEPDMA_DMAADDR',['../group___peripheral___registers___bits___definition.html#gab177fc20463978ff09c399cb56e904bb',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdiepdma_5fdmaaddr_5fmsk_379',['USB_OTG_DIEPDMA_DMAADDR_Msk',['../group___peripheral___registers___bits___definition.html#ga17d3f62d2f03495bb28e7b65f00dbafa',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdiepdma_5fdmaaddr_5fpos_380',['USB_OTG_DIEPDMA_DMAADDR_Pos',['../group___peripheral___registers___bits___definition.html#ga2f8a6b9128f9e824a0ae68346fb8fe73',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdiepeachmsk1_5fbim_381',['USB_OTG_DIEPEACHMSK1_BIM',['../group___peripheral___registers___bits___definition.html#gaac4445e5439cad7796d3fc5de74a2ed8',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdiepeachmsk1_5fbim_5fmsk_382',['USB_OTG_DIEPEACHMSK1_BIM_Msk',['../group___peripheral___registers___bits___definition.html#ga942df01e1be13f057f2e7ecc286d1621',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdiepeachmsk1_5fbim_5fpos_383',['USB_OTG_DIEPEACHMSK1_BIM_Pos',['../group___peripheral___registers___bits___definition.html#ga2c87f9f2c5c5eeedc735b455a1921afd',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdiepeachmsk1_5fepdm_384',['USB_OTG_DIEPEACHMSK1_EPDM',['../group___peripheral___registers___bits___definition.html#ga62e4b8c28bb41136e5d6d3de217e5afd',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdiepeachmsk1_5fepdm_5fmsk_385',['USB_OTG_DIEPEACHMSK1_EPDM_Msk',['../group___peripheral___registers___bits___definition.html#ga8cd0e0b574eba98114663d2eafcd3efd',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdiepeachmsk1_5fepdm_5fpos_386',['USB_OTG_DIEPEACHMSK1_EPDM_Pos',['../group___peripheral___registers___bits___definition.html#gae21af2079e378d491e4fb43a5048b422',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdiepeachmsk1_5finepnem_387',['USB_OTG_DIEPEACHMSK1_INEPNEM',['../group___peripheral___registers___bits___definition.html#gae8ee1bc04de47f522a90619d57086b06',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdiepeachmsk1_5finepnem_5fmsk_388',['USB_OTG_DIEPEACHMSK1_INEPNEM_Msk',['../group___peripheral___registers___bits___definition.html#ga720ea28b3588862d6054ca5b13a7a883',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdiepeachmsk1_5finepnem_5fpos_389',['USB_OTG_DIEPEACHMSK1_INEPNEM_Pos',['../group___peripheral___registers___bits___definition.html#gae45a7ceb9a2a0fe26a60b723e80d7f4b',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdiepeachmsk1_5finepnmm_390',['USB_OTG_DIEPEACHMSK1_INEPNMM',['../group___peripheral___registers___bits___definition.html#gafcc0f1fab9aac10d6edff07dde25d5bc',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdiepeachmsk1_5finepnmm_5fmsk_391',['USB_OTG_DIEPEACHMSK1_INEPNMM_Msk',['../group___peripheral___registers___bits___definition.html#gafdc16990fc5f01933112bbba2fa079a9',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdiepeachmsk1_5finepnmm_5fpos_392',['USB_OTG_DIEPEACHMSK1_INEPNMM_Pos',['../group___peripheral___registers___bits___definition.html#gabffd6dd8a5069f4eb0ceacde6f8b1c81',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdiepeachmsk1_5fittxfemsk_393',['USB_OTG_DIEPEACHMSK1_ITTXFEMSK',['../group___peripheral___registers___bits___definition.html#ga96b7b0c15d5b36f6f3925e51d56990ac',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdiepeachmsk1_5fittxfemsk_5fmsk_394',['USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk',['../group___peripheral___registers___bits___definition.html#ga6f86ddcb79c7f4467cdcd206e95dec7e',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdiepeachmsk1_5fittxfemsk_5fpos_395',['USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos',['../group___peripheral___registers___bits___definition.html#gad8f0a7616486631d230baade93ed84d8',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdiepeachmsk1_5fnakm_396',['USB_OTG_DIEPEACHMSK1_NAKM',['../group___peripheral___registers___bits___definition.html#gaa4089e9aeb641963584d76c932f78e06',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdiepeachmsk1_5fnakm_5fmsk_397',['USB_OTG_DIEPEACHMSK1_NAKM_Msk',['../group___peripheral___registers___bits___definition.html#ga63e3d316ebc4d1b530ac5da37be23e6e',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdiepeachmsk1_5fnakm_5fpos_398',['USB_OTG_DIEPEACHMSK1_NAKM_Pos',['../group___peripheral___registers___bits___definition.html#gabe57f29d04c457e07e50a6cbcd273505',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdiepeachmsk1_5ftom_399',['USB_OTG_DIEPEACHMSK1_TOM',['../group___peripheral___registers___bits___definition.html#gae910eb3d34714653d43579dcface4ead',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdiepeachmsk1_5ftom_5fmsk_400',['USB_OTG_DIEPEACHMSK1_TOM_Msk',['../group___peripheral___registers___bits___definition.html#ga460e8e6ba9daf019aa81f13d097a19fc',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdiepeachmsk1_5ftom_5fpos_401',['USB_OTG_DIEPEACHMSK1_TOM_Pos',['../group___peripheral___registers___bits___definition.html#ga7759259bb9b0d42d020b79d0fe3a8d1a',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdiepeachmsk1_5ftxfurm_402',['USB_OTG_DIEPEACHMSK1_TXFURM',['../group___peripheral___registers___bits___definition.html#gaa6c8f64ad39f7ca4fe195b0b03067866',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdiepeachmsk1_5ftxfurm_5fmsk_403',['USB_OTG_DIEPEACHMSK1_TXFURM_Msk',['../group___peripheral___registers___bits___definition.html#ga227ade985d4eb585dc25efe080981d66',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdiepeachmsk1_5ftxfurm_5fpos_404',['USB_OTG_DIEPEACHMSK1_TXFURM_Pos',['../group___peripheral___registers___bits___definition.html#ga0e8c4451b16845ea560b21c80640b4d6',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdiepeachmsk1_5fxfrcm_405',['USB_OTG_DIEPEACHMSK1_XFRCM',['../group___peripheral___registers___bits___definition.html#gaf3720d0a07deae3c6ff0c6c30c03543c',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdiepeachmsk1_5fxfrcm_5fmsk_406',['USB_OTG_DIEPEACHMSK1_XFRCM_Msk',['../group___peripheral___registers___bits___definition.html#ga3e1c74dcd04816e72d4dcb0cb87407bb',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdiepeachmsk1_5fxfrcm_5fpos_407',['USB_OTG_DIEPEACHMSK1_XFRCM_Pos',['../group___peripheral___registers___bits___definition.html#ga5be6178b3fbce4257db1b3272e5108b1',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdiepempmsk_5fineptxfem_408',['USB_OTG_DIEPEMPMSK_INEPTXFEM',['../group___peripheral___registers___bits___definition.html#gac8129b6a9f51c5131fb60ae0b92887af',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdiepempmsk_5fineptxfem_5fmsk_409',['USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk',['../group___peripheral___registers___bits___definition.html#ga8e5d9742bbb59530bdf7648a369aa31a',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdiepempmsk_5fineptxfem_5fpos_410',['USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos',['../group___peripheral___registers___bits___definition.html#ga417e459f4724862c9832ec1a3762774c',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdiepint_5fahberr_411',['USB_OTG_DIEPINT_AHBERR',['../group___peripheral___registers___bits___definition.html#ga630e92ca04288a83f7f515cedbf01ca9',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdiepint_5fahberr_5fmsk_412',['USB_OTG_DIEPINT_AHBERR_Msk',['../group___peripheral___registers___bits___definition.html#ga3854f2057e03eb6e282a34d4d26f5093',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdiepint_5fahberr_5fpos_413',['USB_OTG_DIEPINT_AHBERR_Pos',['../group___peripheral___registers___bits___definition.html#ga928709eec43877b93798c748fdb8fe6e',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdiepint_5fberr_414',['USB_OTG_DIEPINT_BERR',['../group___peripheral___registers___bits___definition.html#ga496c09a9096346e6141acc2464742b4c',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdiepint_5fberr_5fmsk_415',['USB_OTG_DIEPINT_BERR_Msk',['../group___peripheral___registers___bits___definition.html#ga7902d1f040d0669ad22a9cb4a1e88bdd',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdiepint_5fberr_5fpos_416',['USB_OTG_DIEPINT_BERR_Pos',['../group___peripheral___registers___bits___definition.html#ga2b3a9433ebbf032f80b3a26b2b10e4c9',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdiepint_5fbna_417',['USB_OTG_DIEPINT_BNA',['../group___peripheral___registers___bits___definition.html#ga22983c7c561dedc17e8688d313a50fb0',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdiepint_5fbna_5fmsk_418',['USB_OTG_DIEPINT_BNA_Msk',['../group___peripheral___registers___bits___definition.html#ga92124e1fe13558df5464e356658e67b2',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdiepint_5fbna_5fpos_419',['USB_OTG_DIEPINT_BNA_Pos',['../group___peripheral___registers___bits___definition.html#ga5c35d8a426e47ad0a81add3adb9adbad',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdiepint_5fepdisd_420',['USB_OTG_DIEPINT_EPDISD',['../group___peripheral___registers___bits___definition.html#ga657c139dc16514808c516bff6e523531',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdiepint_5fepdisd_5fmsk_421',['USB_OTG_DIEPINT_EPDISD_Msk',['../group___peripheral___registers___bits___definition.html#gaa8a90367a919959f753ed93ac388259d',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdiepint_5fepdisd_5fpos_422',['USB_OTG_DIEPINT_EPDISD_Pos',['../group___peripheral___registers___bits___definition.html#gaa8e3323ea3b0713a2308da446c5d627b',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdiepint_5finepne_423',['USB_OTG_DIEPINT_INEPNE',['../group___peripheral___registers___bits___definition.html#ga40fbe18a5838e768b9afca5c1695dbb3',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdiepint_5finepne_5fmsk_424',['USB_OTG_DIEPINT_INEPNE_Msk',['../group___peripheral___registers___bits___definition.html#ga98ecb4c61f48a1fc073cda01f1599ad6',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdiepint_5finepne_5fpos_425',['USB_OTG_DIEPINT_INEPNE_Pos',['../group___peripheral___registers___bits___definition.html#ga99e5d6f548490c1a8e3c3b8f8332a6d0',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdiepint_5finepnm_426',['USB_OTG_DIEPINT_INEPNM',['../group___peripheral___registers___bits___definition.html#gafb8ac53eab340e711478e5509be40e13',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdiepint_5finepnm_5fmsk_427',['USB_OTG_DIEPINT_INEPNM_Msk',['../group___peripheral___registers___bits___definition.html#ga6c72659090e081560681486217bc9e21',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdiepint_5finepnm_5fpos_428',['USB_OTG_DIEPINT_INEPNM_Pos',['../group___peripheral___registers___bits___definition.html#ga8c1240b1526225892f7518ed1e6ad3f8',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdiepint_5fittxfe_429',['USB_OTG_DIEPINT_ITTXFE',['../group___peripheral___registers___bits___definition.html#gad0f91471274c3411579a7ede5a7d80f8',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdiepint_5fittxfe_5fmsk_430',['USB_OTG_DIEPINT_ITTXFE_Msk',['../group___peripheral___registers___bits___definition.html#gad15ffda9000245db34322f4a75b31780',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdiepint_5fittxfe_5fpos_431',['USB_OTG_DIEPINT_ITTXFE_Pos',['../group___peripheral___registers___bits___definition.html#ga72bfd0fc0d049c2b27634300aba27e28',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdiepint_5fnak_432',['USB_OTG_DIEPINT_NAK',['../group___peripheral___registers___bits___definition.html#ga9d91e68b693b9c8ff6fb2236093975cf',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdiepint_5fnak_5fmsk_433',['USB_OTG_DIEPINT_NAK_Msk',['../group___peripheral___registers___bits___definition.html#gaafb6909297147bb09786d5e20715656c',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdiepint_5fnak_5fpos_434',['USB_OTG_DIEPINT_NAK_Pos',['../group___peripheral___registers___bits___definition.html#ga78a4751b6393d56bdd1d4e1c837c217e',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdiepint_5fpktdrpsts_435',['USB_OTG_DIEPINT_PKTDRPSTS',['../group___peripheral___registers___bits___definition.html#ga5bf74048c663e9dcc21c282a8c7be576',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdiepint_5fpktdrpsts_5fmsk_436',['USB_OTG_DIEPINT_PKTDRPSTS_Msk',['../group___peripheral___registers___bits___definition.html#ga5bbb4304aaa31dceb651eb6ebea21ca4',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdiepint_5fpktdrpsts_5fpos_437',['USB_OTG_DIEPINT_PKTDRPSTS_Pos',['../group___peripheral___registers___bits___definition.html#ga45fcaff3092226af9b6df98e6f4e3c5f',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdiepint_5ftoc_438',['USB_OTG_DIEPINT_TOC',['../group___peripheral___registers___bits___definition.html#ga253fce8bc78be1504c85d684f232dc43',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdiepint_5ftoc_5fmsk_439',['USB_OTG_DIEPINT_TOC_Msk',['../group___peripheral___registers___bits___definition.html#ga1ca3db2648c05083065675eda6aaef0e',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdiepint_5ftoc_5fpos_440',['USB_OTG_DIEPINT_TOC_Pos',['../group___peripheral___registers___bits___definition.html#ga86a45c7c6fc7a421171a0d6179646f85',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdiepint_5ftxfe_441',['USB_OTG_DIEPINT_TXFE',['../group___peripheral___registers___bits___definition.html#gae4770cce2b4f601e88fb512f6db688ec',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdiepint_5ftxfe_5fmsk_442',['USB_OTG_DIEPINT_TXFE_Msk',['../group___peripheral___registers___bits___definition.html#gadea85fa99c59be521a394f7cfeeadf25',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdiepint_5ftxfe_5fpos_443',['USB_OTG_DIEPINT_TXFE_Pos',['../group___peripheral___registers___bits___definition.html#gaab28f246cb52201b01baa4f85be3c196',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdiepint_5ftxfifoudrn_444',['USB_OTG_DIEPINT_TXFIFOUDRN',['../group___peripheral___registers___bits___definition.html#ga934d166eae0af7663585c903567ebe2b',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdiepint_5ftxfifoudrn_5fmsk_445',['USB_OTG_DIEPINT_TXFIFOUDRN_Msk',['../group___peripheral___registers___bits___definition.html#gaffc8a052f72319f433728b6571098ba0',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdiepint_5ftxfifoudrn_5fpos_446',['USB_OTG_DIEPINT_TXFIFOUDRN_Pos',['../group___peripheral___registers___bits___definition.html#ga795f1914ee10b65cd745129afc32b51f',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdiepint_5fxfrc_447',['USB_OTG_DIEPINT_XFRC',['../group___peripheral___registers___bits___definition.html#gab01f771d126cb58a8cb83841e08bec9b',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdiepint_5fxfrc_5fmsk_448',['USB_OTG_DIEPINT_XFRC_Msk',['../group___peripheral___registers___bits___definition.html#gac2947aa5667ae63ee9bcb747ae955a0b',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdiepint_5fxfrc_5fpos_449',['USB_OTG_DIEPINT_XFRC_Pos',['../group___peripheral___registers___bits___definition.html#ga48ad51eeb41d7d5a2708467685dc81b3',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdiepmsk_5fbim_450',['USB_OTG_DIEPMSK_BIM',['../group___peripheral___registers___bits___definition.html#ga2dd5dbb2c67a3dd71a8fe6563441d243',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdiepmsk_5fbim_5fmsk_451',['USB_OTG_DIEPMSK_BIM_Msk',['../group___peripheral___registers___bits___definition.html#gaaf510f548548201cdaef6370c77bd644',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdiepmsk_5fbim_5fpos_452',['USB_OTG_DIEPMSK_BIM_Pos',['../group___peripheral___registers___bits___definition.html#ga16c9b6bfc32bc4fe2109567cc99efc3d',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdiepmsk_5fepdm_453',['USB_OTG_DIEPMSK_EPDM',['../group___peripheral___registers___bits___definition.html#gafd42de5994316c7c765e349aceaf1718',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdiepmsk_5fepdm_5fmsk_454',['USB_OTG_DIEPMSK_EPDM_Msk',['../group___peripheral___registers___bits___definition.html#ga5f93bf9a17e71b2f6d82c485ec81c464',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdiepmsk_5fepdm_5fpos_455',['USB_OTG_DIEPMSK_EPDM_Pos',['../group___peripheral___registers___bits___definition.html#gaf33e7f717470ec3ffbaf5655caeb5042',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdiepmsk_5finepnem_456',['USB_OTG_DIEPMSK_INEPNEM',['../group___peripheral___registers___bits___definition.html#ga26a366ee28afa322e37670c3eb5d0722',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdiepmsk_5finepnem_5fmsk_457',['USB_OTG_DIEPMSK_INEPNEM_Msk',['../group___peripheral___registers___bits___definition.html#gac4413974123f59fa698d3f79b8218016',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdiepmsk_5finepnem_5fpos_458',['USB_OTG_DIEPMSK_INEPNEM_Pos',['../group___peripheral___registers___bits___definition.html#ga62f0c997d4ec1a2a00c07963d66f4a19',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdiepmsk_5finepnmm_459',['USB_OTG_DIEPMSK_INEPNMM',['../group___peripheral___registers___bits___definition.html#ga34f85531f0e6f963d30dbc284c23fb92',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdiepmsk_5finepnmm_5fmsk_460',['USB_OTG_DIEPMSK_INEPNMM_Msk',['../group___peripheral___registers___bits___definition.html#ga9558bbbb276b63f32baf0dc2c9e37a87',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdiepmsk_5finepnmm_5fpos_461',['USB_OTG_DIEPMSK_INEPNMM_Pos',['../group___peripheral___registers___bits___definition.html#ga4e89f316e156b4d99a97be6c55c697ef',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdiepmsk_5fittxfemsk_462',['USB_OTG_DIEPMSK_ITTXFEMSK',['../group___peripheral___registers___bits___definition.html#ga52a6c7819bcf9554d7f20c9ba4ad99dd',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdiepmsk_5fittxfemsk_5fmsk_463',['USB_OTG_DIEPMSK_ITTXFEMSK_Msk',['../group___peripheral___registers___bits___definition.html#gafa7c9ebfa6013f1aed7b853573298a0a',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdiepmsk_5fittxfemsk_5fpos_464',['USB_OTG_DIEPMSK_ITTXFEMSK_Pos',['../group___peripheral___registers___bits___definition.html#ga8b2199466036aae72f41437ca8d12305',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdiepmsk_5ftom_465',['USB_OTG_DIEPMSK_TOM',['../group___peripheral___registers___bits___definition.html#ga7329fbd5f4d78564704e80cbdcfb6a8f',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdiepmsk_5ftom_5fmsk_466',['USB_OTG_DIEPMSK_TOM_Msk',['../group___peripheral___registers___bits___definition.html#gae3ef8fc38aa3179714c5ac82ac381e94',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdiepmsk_5ftom_5fpos_467',['USB_OTG_DIEPMSK_TOM_Pos',['../group___peripheral___registers___bits___definition.html#ga23c48c84904e681f9f973b9e102dd45b',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdiepmsk_5ftxfurm_468',['USB_OTG_DIEPMSK_TXFURM',['../group___peripheral___registers___bits___definition.html#ga8d10ab688d3bf47aaf8180daf0624e9d',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdiepmsk_5ftxfurm_5fmsk_469',['USB_OTG_DIEPMSK_TXFURM_Msk',['../group___peripheral___registers___bits___definition.html#ga3e7e1dc554fdd79e23762aac9e2338b0',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdiepmsk_5ftxfurm_5fpos_470',['USB_OTG_DIEPMSK_TXFURM_Pos',['../group___peripheral___registers___bits___definition.html#ga1a917fb1c83934de74f903f2d5fb68ae',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdiepmsk_5fxfrcm_471',['USB_OTG_DIEPMSK_XFRCM',['../group___peripheral___registers___bits___definition.html#ga6f5c0badd33dc95fa7897bd4bb558ad6',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdiepmsk_5fxfrcm_5fmsk_472',['USB_OTG_DIEPMSK_XFRCM_Msk',['../group___peripheral___registers___bits___definition.html#ga4d4f31482f2ac26051500e0c8f3a0869',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdiepmsk_5fxfrcm_5fpos_473',['USB_OTG_DIEPMSK_XFRCM_Pos',['../group___peripheral___registers___bits___definition.html#ga77a95aac6875bc11ee78ffec7381ec24',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdieptsiz_5fmulcnt_474',['USB_OTG_DIEPTSIZ_MULCNT',['../group___peripheral___registers___bits___definition.html#ga428da482bfd499096cff02a3d8aa6738',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdieptsiz_5fmulcnt_5fmsk_475',['USB_OTG_DIEPTSIZ_MULCNT_Msk',['../group___peripheral___registers___bits___definition.html#ga5b2138444cba4a94fea9ab112d212e1c',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdieptsiz_5fmulcnt_5fpos_476',['USB_OTG_DIEPTSIZ_MULCNT_Pos',['../group___peripheral___registers___bits___definition.html#ga1d027496fed28964c3a0ec36bfe5c03c',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdieptsiz_5fpktcnt_477',['USB_OTG_DIEPTSIZ_PKTCNT',['../group___peripheral___registers___bits___definition.html#ga664b39d163f9f2e400aa9fe2577ffc06',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdieptsiz_5fpktcnt_5fmsk_478',['USB_OTG_DIEPTSIZ_PKTCNT_Msk',['../group___peripheral___registers___bits___definition.html#ga4032f4b698ca8efd7417e13471d834e0',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdieptsiz_5fpktcnt_5fpos_479',['USB_OTG_DIEPTSIZ_PKTCNT_Pos',['../group___peripheral___registers___bits___definition.html#ga623bbf2a88cfc42a0e43ede442a58eca',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdieptsiz_5fxfrsiz_480',['USB_OTG_DIEPTSIZ_XFRSIZ',['../group___peripheral___registers___bits___definition.html#ga5497667d259391162884390afd456f62',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdieptsiz_5fxfrsiz_5fmsk_481',['USB_OTG_DIEPTSIZ_XFRSIZ_Msk',['../group___peripheral___registers___bits___definition.html#ga3b953496e53318844d2444b0d3982d2d',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdieptsiz_5fxfrsiz_5fpos_482',['USB_OTG_DIEPTSIZ_XFRSIZ_Pos',['../group___peripheral___registers___bits___definition.html#gaa981fab712cf94125aa509221dc26720',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdieptxf_5fineptxfd_483',['USB_OTG_DIEPTXF_INEPTXFD',['../group___peripheral___registers___bits___definition.html#ga015ec5caee27272afa335fa9d5892a40',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdieptxf_5fineptxfd_5fmsk_484',['USB_OTG_DIEPTXF_INEPTXFD_Msk',['../group___peripheral___registers___bits___definition.html#gafccb927bfa114a368eea25db7d46c85f',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdieptxf_5fineptxfd_5fpos_485',['USB_OTG_DIEPTXF_INEPTXFD_Pos',['../group___peripheral___registers___bits___definition.html#ga8c94d7d7bd4526bc8cef42790a10af14',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdieptxf_5fineptxsa_486',['USB_OTG_DIEPTXF_INEPTXSA',['../group___peripheral___registers___bits___definition.html#ga731c1eaaf15ec1b7f24e055172f7e0cf',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdieptxf_5fineptxsa_5fmsk_487',['USB_OTG_DIEPTXF_INEPTXSA_Msk',['../group___peripheral___registers___bits___definition.html#gac5b86ac57a1176451f435dda801dbddb',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdieptxf_5fineptxsa_5fpos_488',['USB_OTG_DIEPTXF_INEPTXSA_Pos',['../group___peripheral___registers___bits___definition.html#ga129f8f89a1a613ce6f86fdb826238e16',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdoepctl_5fcnak_489',['USB_OTG_DOEPCTL_CNAK',['../group___peripheral___registers___bits___definition.html#gabd05c0aa7833e7467e0ff66cfa1f20cb',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdoepctl_5fcnak_5fmsk_490',['USB_OTG_DOEPCTL_CNAK_Msk',['../group___peripheral___registers___bits___definition.html#ga92c45d7d3e789caf1b5a8967592939ae',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdoepctl_5fcnak_5fpos_491',['USB_OTG_DOEPCTL_CNAK_Pos',['../group___peripheral___registers___bits___definition.html#ga8ce77ba5437dc8c547c7fe2b2851af15',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdoepctl_5fepdis_492',['USB_OTG_DOEPCTL_EPDIS',['../group___peripheral___registers___bits___definition.html#gaf170f97217b0a2e3f66a33a67257674e',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdoepctl_5fepdis_5fmsk_493',['USB_OTG_DOEPCTL_EPDIS_Msk',['../group___peripheral___registers___bits___definition.html#ga46881c1a50c0a2b48f4d107a9cdc540f',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdoepctl_5fepdis_5fpos_494',['USB_OTG_DOEPCTL_EPDIS_Pos',['../group___peripheral___registers___bits___definition.html#ga06d18faa6f215148241b0aa16a2708dc',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdoepctl_5fepena_495',['USB_OTG_DOEPCTL_EPENA',['../group___peripheral___registers___bits___definition.html#ga8875f7311dfde66125b78dd715fd2d7c',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdoepctl_5fepena_5fmsk_496',['USB_OTG_DOEPCTL_EPENA_Msk',['../group___peripheral___registers___bits___definition.html#ga891f80e6cdbf19579db62d0214bc09b5',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdoepctl_5fepena_5fpos_497',['USB_OTG_DOEPCTL_EPENA_Pos',['../group___peripheral___registers___bits___definition.html#ga67d45681d84c4e5a4a1050291a2f1c4c',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdoepctl_5feptyp_498',['USB_OTG_DOEPCTL_EPTYP',['../group___peripheral___registers___bits___definition.html#ga4e347921b96b8435ec2ef6cc9b3470d8',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdoepctl_5feptyp_5f0_499',['USB_OTG_DOEPCTL_EPTYP_0',['../group___peripheral___registers___bits___definition.html#ga48b0660b499862424b72cd59bca9226e',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdoepctl_5feptyp_5f1_500',['USB_OTG_DOEPCTL_EPTYP_1',['../group___peripheral___registers___bits___definition.html#ga89595201dd98cc05712d046e98c142fd',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdoepctl_5feptyp_5fmsk_501',['USB_OTG_DOEPCTL_EPTYP_Msk',['../group___peripheral___registers___bits___definition.html#gab5fea8cfdb01a643000019dc830fc30f',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdoepctl_5feptyp_5fpos_502',['USB_OTG_DOEPCTL_EPTYP_Pos',['../group___peripheral___registers___bits___definition.html#ga3dd2ea9b1c00daf741f7ac74f32bebc3',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdoepctl_5fmpsiz_503',['USB_OTG_DOEPCTL_MPSIZ',['../group___peripheral___registers___bits___definition.html#ga0ebce086e91feb566f223ae07d01ff57',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdoepctl_5fmpsiz_5fmsk_504',['USB_OTG_DOEPCTL_MPSIZ_Msk',['../group___peripheral___registers___bits___definition.html#ga103ef4c7123cb64007a1eb050d96c4b7',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdoepctl_5fmpsiz_5fpos_505',['USB_OTG_DOEPCTL_MPSIZ_Pos',['../group___peripheral___registers___bits___definition.html#gaef51a2cbd7e13a734ffdfded5b1e772d',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdoepctl_5fnaksts_506',['USB_OTG_DOEPCTL_NAKSTS',['../group___peripheral___registers___bits___definition.html#gaa1735002d3abf233ca0cbe473da2d8fb',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdoepctl_5fnaksts_5fmsk_507',['USB_OTG_DOEPCTL_NAKSTS_Msk',['../group___peripheral___registers___bits___definition.html#gacca51b95d03a684417745d2870bc02aa',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdoepctl_5fnaksts_5fpos_508',['USB_OTG_DOEPCTL_NAKSTS_Pos',['../group___peripheral___registers___bits___definition.html#gab721aee46a6d9aaabb0c1449155777c9',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdoepctl_5fsd0pid_5fsevnfrm_509',['USB_OTG_DOEPCTL_SD0PID_SEVNFRM',['../group___peripheral___registers___bits___definition.html#ga0a06b55e9caa25873e734fb15cafbc51',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdoepctl_5fsd0pid_5fsevnfrm_5fmsk_510',['USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk',['../group___peripheral___registers___bits___definition.html#gac1b8b770cb957bf0f4148311ddfef503',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdoepctl_5fsd0pid_5fsevnfrm_5fpos_511',['USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos',['../group___peripheral___registers___bits___definition.html#gae0a8dc23aee4dc031e4f2e85b8a09dbb',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdoepctl_5fsnak_512',['USB_OTG_DOEPCTL_SNAK',['../group___peripheral___registers___bits___definition.html#ga05a3e120b2c56a13ff622b0a507f48ee',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdoepctl_5fsnak_5fmsk_513',['USB_OTG_DOEPCTL_SNAK_Msk',['../group___peripheral___registers___bits___definition.html#ga6be0f6d6ed75219981fc07465ba09298',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdoepctl_5fsnak_5fpos_514',['USB_OTG_DOEPCTL_SNAK_Pos',['../group___peripheral___registers___bits___definition.html#gaa3f8d51a7d585bca9ab215fd90fcba33',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdoepctl_5fsnpm_515',['USB_OTG_DOEPCTL_SNPM',['../group___peripheral___registers___bits___definition.html#ga14ef1fba78e67a55f665495ae7f8732e',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdoepctl_5fsnpm_5fmsk_516',['USB_OTG_DOEPCTL_SNPM_Msk',['../group___peripheral___registers___bits___definition.html#ga592d0d387403b49dd841153e1c8ef922',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdoepctl_5fsnpm_5fpos_517',['USB_OTG_DOEPCTL_SNPM_Pos',['../group___peripheral___registers___bits___definition.html#gaed30bbeec479174dbaeb4ec6342e7acc',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdoepctl_5fsoddfrm_518',['USB_OTG_DOEPCTL_SODDFRM',['../group___peripheral___registers___bits___definition.html#ga77ddb336230fa5a497dbb2393a180ae6',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdoepctl_5fsoddfrm_5fmsk_519',['USB_OTG_DOEPCTL_SODDFRM_Msk',['../group___peripheral___registers___bits___definition.html#ga4f4b73b3f5f6813412b392b8b619a1ae',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdoepctl_5fsoddfrm_5fpos_520',['USB_OTG_DOEPCTL_SODDFRM_Pos',['../group___peripheral___registers___bits___definition.html#gab617807c602f3dd930adca64b0c5fed1',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdoepctl_5fstall_521',['USB_OTG_DOEPCTL_STALL',['../group___peripheral___registers___bits___definition.html#ga5e6aea29335780171f8ce42aba031699',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdoepctl_5fstall_5fmsk_522',['USB_OTG_DOEPCTL_STALL_Msk',['../group___peripheral___registers___bits___definition.html#ga600dc33e80274fdf8ec793bce5df9ad4',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdoepctl_5fstall_5fpos_523',['USB_OTG_DOEPCTL_STALL_Pos',['../group___peripheral___registers___bits___definition.html#ga713faf56d7526c1671e9920f96207902',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdoepctl_5fusbaep_524',['USB_OTG_DOEPCTL_USBAEP',['../group___peripheral___registers___bits___definition.html#gabed242624f140356cc793039988d89df',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdoepctl_5fusbaep_5fmsk_525',['USB_OTG_DOEPCTL_USBAEP_Msk',['../group___peripheral___registers___bits___definition.html#ga31ba8e0d0b5bf08b034ba5cf27eaef4c',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdoepctl_5fusbaep_5fpos_526',['USB_OTG_DOEPCTL_USBAEP_Pos',['../group___peripheral___registers___bits___definition.html#gaf003bdf82be8bff3e23452c7a83a9ed2',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdoepeachmsk1_5fberrm_527',['USB_OTG_DOEPEACHMSK1_BERRM',['../group___peripheral___registers___bits___definition.html#ga3eecdae7aa0c9b1b40f219e8b0c18879',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdoepeachmsk1_5fberrm_5fmsk_528',['USB_OTG_DOEPEACHMSK1_BERRM_Msk',['../group___peripheral___registers___bits___definition.html#gadb8873ed6ca0091147855a58b22054ed',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdoepeachmsk1_5fberrm_5fpos_529',['USB_OTG_DOEPEACHMSK1_BERRM_Pos',['../group___peripheral___registers___bits___definition.html#ga7d940b15d335a584cb074297e330804c',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdoepeachmsk1_5fbim_530',['USB_OTG_DOEPEACHMSK1_BIM',['../group___peripheral___registers___bits___definition.html#gaa99f230d086cf41692cfab0c1aad0f26',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdoepeachmsk1_5fbim_5fmsk_531',['USB_OTG_DOEPEACHMSK1_BIM_Msk',['../group___peripheral___registers___bits___definition.html#gad4b101ae377598650c667420a8465cef',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdoepeachmsk1_5fbim_5fpos_532',['USB_OTG_DOEPEACHMSK1_BIM_Pos',['../group___peripheral___registers___bits___definition.html#ga85a209e39fa583a74b58fa30ccc01496',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdoepeachmsk1_5fepdm_533',['USB_OTG_DOEPEACHMSK1_EPDM',['../group___peripheral___registers___bits___definition.html#ga866580df1a60ef8b3347d63b1369f76e',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdoepeachmsk1_5fepdm_5fmsk_534',['USB_OTG_DOEPEACHMSK1_EPDM_Msk',['../group___peripheral___registers___bits___definition.html#ga6c0d1dc807789f08756d5eebc35065e5',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdoepeachmsk1_5fepdm_5fpos_535',['USB_OTG_DOEPEACHMSK1_EPDM_Pos',['../group___peripheral___registers___bits___definition.html#gac39a208617e70f246d83e7ca33f2d63a',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdoepeachmsk1_5finepnem_536',['USB_OTG_DOEPEACHMSK1_INEPNEM',['../group___peripheral___registers___bits___definition.html#ga73a879622564efeb3244262bf9419818',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdoepeachmsk1_5finepnem_5fmsk_537',['USB_OTG_DOEPEACHMSK1_INEPNEM_Msk',['../group___peripheral___registers___bits___definition.html#gaa6b4fd478ae41b36f08356f9c98840d5',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdoepeachmsk1_5finepnem_5fpos_538',['USB_OTG_DOEPEACHMSK1_INEPNEM_Pos',['../group___peripheral___registers___bits___definition.html#ga773825312f8b0edbb607a5fea843c882',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdoepeachmsk1_5finepnmm_539',['USB_OTG_DOEPEACHMSK1_INEPNMM',['../group___peripheral___registers___bits___definition.html#ga20d91d742e89a430937207cca6dd0a1a',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdoepeachmsk1_5finepnmm_5fmsk_540',['USB_OTG_DOEPEACHMSK1_INEPNMM_Msk',['../group___peripheral___registers___bits___definition.html#gaa0193a714c31b0cf57e25588071cc637',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdoepeachmsk1_5finepnmm_5fpos_541',['USB_OTG_DOEPEACHMSK1_INEPNMM_Pos',['../group___peripheral___registers___bits___definition.html#gabe0a86e9dbdf4a15922a6503e78c2f67',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdoepeachmsk1_5fittxfemsk_542',['USB_OTG_DOEPEACHMSK1_ITTXFEMSK',['../group___peripheral___registers___bits___definition.html#gace8821806fb4cb204d97dbb965e5067d',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdoepeachmsk1_5fittxfemsk_5fmsk_543',['USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk',['../group___peripheral___registers___bits___definition.html#ga958f2820ea10558695b00400bfed9927',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdoepeachmsk1_5fittxfemsk_5fpos_544',['USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos',['../group___peripheral___registers___bits___definition.html#ga20102cf4a07490f60bd525bce51de6b6',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdoepeachmsk1_5fnakm_545',['USB_OTG_DOEPEACHMSK1_NAKM',['../group___peripheral___registers___bits___definition.html#ga98fa7db10f7b8e4998d30646a9e8e266',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdoepeachmsk1_5fnakm_5fmsk_546',['USB_OTG_DOEPEACHMSK1_NAKM_Msk',['../group___peripheral___registers___bits___definition.html#ga94cf1998cd40af00f7295c221fd4850b',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdoepeachmsk1_5fnakm_5fpos_547',['USB_OTG_DOEPEACHMSK1_NAKM_Pos',['../group___peripheral___registers___bits___definition.html#ga6935021f39b8b2ba43e5e963c441c0bf',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdoepeachmsk1_5fnyetm_548',['USB_OTG_DOEPEACHMSK1_NYETM',['../group___peripheral___registers___bits___definition.html#ga5bcea3bd49b83367b4f62c554815770e',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdoepeachmsk1_5fnyetm_5fmsk_549',['USB_OTG_DOEPEACHMSK1_NYETM_Msk',['../group___peripheral___registers___bits___definition.html#ga5cfdf8dc17970f375d544ff23c3369fc',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdoepeachmsk1_5fnyetm_5fpos_550',['USB_OTG_DOEPEACHMSK1_NYETM_Pos',['../group___peripheral___registers___bits___definition.html#ga9738465ddedbad09f63f86d8932235ca',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdoepeachmsk1_5ftom_551',['USB_OTG_DOEPEACHMSK1_TOM',['../group___peripheral___registers___bits___definition.html#ga038706cd615636fe5bf10e6636b3c035',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdoepeachmsk1_5ftom_5fmsk_552',['USB_OTG_DOEPEACHMSK1_TOM_Msk',['../group___peripheral___registers___bits___definition.html#gaae427974c1d2cd44962a72e5ad4d9e68',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdoepeachmsk1_5ftom_5fpos_553',['USB_OTG_DOEPEACHMSK1_TOM_Pos',['../group___peripheral___registers___bits___definition.html#gae2a3e66bdba3af962f77a2643a8dfe38',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdoepeachmsk1_5ftxfurm_554',['USB_OTG_DOEPEACHMSK1_TXFURM',['../group___peripheral___registers___bits___definition.html#gaa3ca9111b1b74380566ce72b6c985560',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdoepeachmsk1_5ftxfurm_5fmsk_555',['USB_OTG_DOEPEACHMSK1_TXFURM_Msk',['../group___peripheral___registers___bits___definition.html#ga3bd6db454cff3d758f6d9d36f8bac8c1',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdoepeachmsk1_5ftxfurm_5fpos_556',['USB_OTG_DOEPEACHMSK1_TXFURM_Pos',['../group___peripheral___registers___bits___definition.html#gae23cef3a94a622721e9f36176b8ee292',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdoepeachmsk1_5fxfrcm_557',['USB_OTG_DOEPEACHMSK1_XFRCM',['../group___peripheral___registers___bits___definition.html#ga4f709b5af2c771d66d240adef5d8be21',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdoepeachmsk1_5fxfrcm_5fmsk_558',['USB_OTG_DOEPEACHMSK1_XFRCM_Msk',['../group___peripheral___registers___bits___definition.html#gaa1124b10adb855eb49ab052fd8f7adf5',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdoepeachmsk1_5fxfrcm_5fpos_559',['USB_OTG_DOEPEACHMSK1_XFRCM_Pos',['../group___peripheral___registers___bits___definition.html#ga50c80b485139155fd7ede8a5b78af293',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdoepint_5fahberr_560',['USB_OTG_DOEPINT_AHBERR',['../group___peripheral___registers___bits___definition.html#ga8957520b45ebd1ed0000d8a0c0cc9ef6',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdoepint_5fahberr_5fmsk_561',['USB_OTG_DOEPINT_AHBERR_Msk',['../group___peripheral___registers___bits___definition.html#ga7dfe74336fa143f3b5a536a74ff77dcb',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdoepint_5fahberr_5fpos_562',['USB_OTG_DOEPINT_AHBERR_Pos',['../group___peripheral___registers___bits___definition.html#ga0e071c9b55a563d90d1ab1c0577390a4',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdoepint_5fb2bstup_563',['USB_OTG_DOEPINT_B2BSTUP',['../group___peripheral___registers___bits___definition.html#ga82261faaf818baade125d4de42f78fa5',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdoepint_5fb2bstup_5fmsk_564',['USB_OTG_DOEPINT_B2BSTUP_Msk',['../group___peripheral___registers___bits___definition.html#gab7623d1db984217c12acc54117994337',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdoepint_5fb2bstup_5fpos_565',['USB_OTG_DOEPINT_B2BSTUP_Pos',['../group___peripheral___registers___bits___definition.html#gafb2f0d32861f239d7cf694ce1f34d019',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdoepint_5fepdisd_566',['USB_OTG_DOEPINT_EPDISD',['../group___peripheral___registers___bits___definition.html#ga32e18140ad2c7902fe788947cea557d2',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdoepint_5fepdisd_5fmsk_567',['USB_OTG_DOEPINT_EPDISD_Msk',['../group___peripheral___registers___bits___definition.html#gad2bee78f4eead58dd6e9d772d77c843d',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdoepint_5fepdisd_5fpos_568',['USB_OTG_DOEPINT_EPDISD_Pos',['../group___peripheral___registers___bits___definition.html#gabd8ea7d7381b81fc6ace42213c39c909',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdoepint_5fnak_569',['USB_OTG_DOEPINT_NAK',['../group___peripheral___registers___bits___definition.html#ga1d1b7add4ca4362bb47501b456d3bb8b',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdoepint_5fnak_5fmsk_570',['USB_OTG_DOEPINT_NAK_Msk',['../group___peripheral___registers___bits___definition.html#gaaaa6114d1a7f5860c94bc9eb1ef1207c',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdoepint_5fnak_5fpos_571',['USB_OTG_DOEPINT_NAK_Pos',['../group___peripheral___registers___bits___definition.html#ga3b77b085273952d4999950d52cd674c7',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdoepint_5fnyet_572',['USB_OTG_DOEPINT_NYET',['../group___peripheral___registers___bits___definition.html#gaf63ba909dd472b7ce95b05e8ed984ac3',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdoepint_5fnyet_5fmsk_573',['USB_OTG_DOEPINT_NYET_Msk',['../group___peripheral___registers___bits___definition.html#ga8ea8387720c1dd29d7c4689f4b83792f',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdoepint_5fnyet_5fpos_574',['USB_OTG_DOEPINT_NYET_Pos',['../group___peripheral___registers___bits___definition.html#gad3e46923e595b9049270b43fece30784',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdoepint_5fotepdis_575',['USB_OTG_DOEPINT_OTEPDIS',['../group___peripheral___registers___bits___definition.html#ga3f4c92b08606cf934de16b353053dd78',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdoepint_5fotepdis_5fmsk_576',['USB_OTG_DOEPINT_OTEPDIS_Msk',['../group___peripheral___registers___bits___definition.html#gab8a3dd1c173d5cd66abf1d5aff97f894',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdoepint_5fotepdis_5fpos_577',['USB_OTG_DOEPINT_OTEPDIS_Pos',['../group___peripheral___registers___bits___definition.html#gaa3e353ea229f93246f7fb4ef0efc90a9',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdoepint_5fotepspr_578',['USB_OTG_DOEPINT_OTEPSPR',['../group___peripheral___registers___bits___definition.html#ga2451732dfee15831f09e28041dabf9ce',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdoepint_5fotepspr_5fmsk_579',['USB_OTG_DOEPINT_OTEPSPR_Msk',['../group___peripheral___registers___bits___definition.html#ga0c064a7156878cca72817277cce28cef',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdoepint_5fotepspr_5fpos_580',['USB_OTG_DOEPINT_OTEPSPR_Pos',['../group___peripheral___registers___bits___definition.html#ga0cd4ee8b333b45244a950aec7b6d1756',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdoepint_5foutpkterr_581',['USB_OTG_DOEPINT_OUTPKTERR',['../group___peripheral___registers___bits___definition.html#gadf82df64a03b0a9f6915a36a750488ac',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdoepint_5foutpkterr_5fmsk_582',['USB_OTG_DOEPINT_OUTPKTERR_Msk',['../group___peripheral___registers___bits___definition.html#ga7f5870176a1b59ee2048b23087b677ae',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdoepint_5foutpkterr_5fpos_583',['USB_OTG_DOEPINT_OUTPKTERR_Pos',['../group___peripheral___registers___bits___definition.html#ga92efd02af8d099a47efd3e038bada011',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdoepint_5fstpktrx_584',['USB_OTG_DOEPINT_STPKTRX',['../group___peripheral___registers___bits___definition.html#ga90d44e256af7596e109c61925dbdb6fd',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdoepint_5fstpktrx_5fmsk_585',['USB_OTG_DOEPINT_STPKTRX_Msk',['../group___peripheral___registers___bits___definition.html#ga2c90fbb29ef97f0974e4040889d12e34',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdoepint_5fstpktrx_5fpos_586',['USB_OTG_DOEPINT_STPKTRX_Pos',['../group___peripheral___registers___bits___definition.html#ga05052a0dcef08b6e6acaf900e3f4b39d',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdoepint_5fstup_587',['USB_OTG_DOEPINT_STUP',['../group___peripheral___registers___bits___definition.html#ga76444bdecd4d6def6c718ed1bb8e8b8c',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdoepint_5fstup_5fmsk_588',['USB_OTG_DOEPINT_STUP_Msk',['../group___peripheral___registers___bits___definition.html#ga42dda03dc0034c884c0a51c1f749edfb',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdoepint_5fstup_5fpos_589',['USB_OTG_DOEPINT_STUP_Pos',['../group___peripheral___registers___bits___definition.html#ga74a9a1fec27e8dd4a5a603a0d63fc104',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdoepint_5fxfrc_590',['USB_OTG_DOEPINT_XFRC',['../group___peripheral___registers___bits___definition.html#ga0e51a7b1cc412e304246176c207cbcb8',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdoepint_5fxfrc_5fmsk_591',['USB_OTG_DOEPINT_XFRC_Msk',['../group___peripheral___registers___bits___definition.html#ga71bec204f2c5886251295d5ea7739331',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdoepint_5fxfrc_5fpos_592',['USB_OTG_DOEPINT_XFRC_Pos',['../group___peripheral___registers___bits___definition.html#ga22c42c63b15338fb0f80bc252ab8a1f9',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdoepmsk_5fahberrm_593',['USB_OTG_DOEPMSK_AHBERRM',['../group___peripheral___registers___bits___definition.html#gafc5eeb0500ce7832cf607829de07dc06',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdoepmsk_5fahberrm_5fmsk_594',['USB_OTG_DOEPMSK_AHBERRM_Msk',['../group___peripheral___registers___bits___definition.html#gaec4375fe9d10b890e84c603398653dbd',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdoepmsk_5fahberrm_5fpos_595',['USB_OTG_DOEPMSK_AHBERRM_Pos',['../group___peripheral___registers___bits___definition.html#ga3cee72a98e75f37cc4e9c71002ed9e74',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdoepmsk_5fb2bstup_596',['USB_OTG_DOEPMSK_B2BSTUP',['../group___peripheral___registers___bits___definition.html#ga59ef878371c32d6157a619ec42144c09',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdoepmsk_5fb2bstup_5fmsk_597',['USB_OTG_DOEPMSK_B2BSTUP_Msk',['../group___peripheral___registers___bits___definition.html#ga990e43476d2858b9b8b0a1e10ddd3ca1',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdoepmsk_5fb2bstup_5fpos_598',['USB_OTG_DOEPMSK_B2BSTUP_Pos',['../group___peripheral___registers___bits___definition.html#gaab4e6b15ce4e8b36a49a8e46d6354ab2',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdoepmsk_5fberrm_599',['USB_OTG_DOEPMSK_BERRM',['../group___peripheral___registers___bits___definition.html#gaaac35f8747cd753d8534cfd8d6f4e6f2',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdoepmsk_5fberrm_5fmsk_600',['USB_OTG_DOEPMSK_BERRM_Msk',['../group___peripheral___registers___bits___definition.html#gaad22af854eb20c0c8f6c718703aa06cc',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdoepmsk_5fberrm_5fpos_601',['USB_OTG_DOEPMSK_BERRM_Pos',['../group___peripheral___registers___bits___definition.html#ga4f60404d296c1b736ed763904914bbc4',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdoepmsk_5fboim_602',['USB_OTG_DOEPMSK_BOIM',['../group___peripheral___registers___bits___definition.html#ga980f37cfb000d12f7752530986d5069c',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdoepmsk_5fboim_5fmsk_603',['USB_OTG_DOEPMSK_BOIM_Msk',['../group___peripheral___registers___bits___definition.html#gaa93f1e928648830df23013e8868ed53a',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdoepmsk_5fboim_5fpos_604',['USB_OTG_DOEPMSK_BOIM_Pos',['../group___peripheral___registers___bits___definition.html#gaf13c76bdd8af0056459a0ec9e8b38a50',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdoepmsk_5fepdm_605',['USB_OTG_DOEPMSK_EPDM',['../group___peripheral___registers___bits___definition.html#ga6078d0855016e26c85d0a5b935e6f6ba',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdoepmsk_5fepdm_5fmsk_606',['USB_OTG_DOEPMSK_EPDM_Msk',['../group___peripheral___registers___bits___definition.html#gab3b3d4b03a79afdb9c3a5b9e40d07158',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdoepmsk_5fepdm_5fpos_607',['USB_OTG_DOEPMSK_EPDM_Pos',['../group___peripheral___registers___bits___definition.html#ga7b5c2c8efd16702ac54250eef9e71f5f',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdoepmsk_5fnakm_608',['USB_OTG_DOEPMSK_NAKM',['../group___peripheral___registers___bits___definition.html#ga377812e187288777184fec2d96929ac3',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdoepmsk_5fnakm_5fmsk_609',['USB_OTG_DOEPMSK_NAKM_Msk',['../group___peripheral___registers___bits___definition.html#ga4282f15a3f24294c3de271447aa0b53a',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdoepmsk_5fnakm_5fpos_610',['USB_OTG_DOEPMSK_NAKM_Pos',['../group___peripheral___registers___bits___definition.html#ga849d7e79fa347faa484a293e99337c37',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdoepmsk_5fnyetm_611',['USB_OTG_DOEPMSK_NYETM',['../group___peripheral___registers___bits___definition.html#ga1a60db81ca4a7ab4ce864d70c5235498',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdoepmsk_5fnyetm_5fmsk_612',['USB_OTG_DOEPMSK_NYETM_Msk',['../group___peripheral___registers___bits___definition.html#gaa7d2f79cc4d6c27cc7d24cc63b2103d0',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdoepmsk_5fnyetm_5fpos_613',['USB_OTG_DOEPMSK_NYETM_Pos',['../group___peripheral___registers___bits___definition.html#ga60d3e6971b726ef17a4f7518838813b5',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdoepmsk_5fopem_614',['USB_OTG_DOEPMSK_OPEM',['../group___peripheral___registers___bits___definition.html#ga26bf486957377a746a55ae6203ea697c',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdoepmsk_5fopem_5fmsk_615',['USB_OTG_DOEPMSK_OPEM_Msk',['../group___peripheral___registers___bits___definition.html#gaf413b92fd7377313378c481fbf28c6f0',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdoepmsk_5fopem_5fpos_616',['USB_OTG_DOEPMSK_OPEM_Pos',['../group___peripheral___registers___bits___definition.html#gaf5e214436522dcf78ba7057e0cd9e463',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdoepmsk_5fotepdm_617',['USB_OTG_DOEPMSK_OTEPDM',['../group___peripheral___registers___bits___definition.html#gad472667f09c79f0ca122586ae032e9df',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdoepmsk_5fotepdm_5fmsk_618',['USB_OTG_DOEPMSK_OTEPDM_Msk',['../group___peripheral___registers___bits___definition.html#gae7df1cf9a2583c2a2c079c2743db0c0a',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdoepmsk_5fotepdm_5fpos_619',['USB_OTG_DOEPMSK_OTEPDM_Pos',['../group___peripheral___registers___bits___definition.html#ga71b98d5a957803fef609dcc8ce29e5e7',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdoepmsk_5fotepsprm_620',['USB_OTG_DOEPMSK_OTEPSPRM',['../group___peripheral___registers___bits___definition.html#ga22b959b8d57d5bace18e35d95de09a77',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdoepmsk_5fotepsprm_5fmsk_621',['USB_OTG_DOEPMSK_OTEPSPRM_Msk',['../group___peripheral___registers___bits___definition.html#gaf2715f06a8df58db51a00016f761d6b0',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdoepmsk_5fotepsprm_5fpos_622',['USB_OTG_DOEPMSK_OTEPSPRM_Pos',['../group___peripheral___registers___bits___definition.html#gae44f78310897990a88aaef41fb7e0ec3',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdoepmsk_5fstupm_623',['USB_OTG_DOEPMSK_STUPM',['../group___peripheral___registers___bits___definition.html#gabb61e805f1e512b80a7b33efcca6182e',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdoepmsk_5fstupm_5fmsk_624',['USB_OTG_DOEPMSK_STUPM_Msk',['../group___peripheral___registers___bits___definition.html#gafccb9d1a7a0af8c8ed2be97eff94a8d1',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdoepmsk_5fstupm_5fpos_625',['USB_OTG_DOEPMSK_STUPM_Pos',['../group___peripheral___registers___bits___definition.html#ga7cc448d81a686805e6929bfa1b0733a0',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdoepmsk_5fxfrcm_626',['USB_OTG_DOEPMSK_XFRCM',['../group___peripheral___registers___bits___definition.html#ga9e4371d47a5b0cfcc1235fbb9fbd7931',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdoepmsk_5fxfrcm_5fmsk_627',['USB_OTG_DOEPMSK_XFRCM_Msk',['../group___peripheral___registers___bits___definition.html#ga722790431dd642e348bcded588d7e824',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdoepmsk_5fxfrcm_5fpos_628',['USB_OTG_DOEPMSK_XFRCM_Pos',['../group___peripheral___registers___bits___definition.html#gaf6f7cf9e1a76b015dd90de4a3d5b3c2c',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdoeptsiz_5fpktcnt_629',['USB_OTG_DOEPTSIZ_PKTCNT',['../group___peripheral___registers___bits___definition.html#gae7bc1fb16d2d5b7a8d92fce5a61a038f',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdoeptsiz_5fpktcnt_5fmsk_630',['USB_OTG_DOEPTSIZ_PKTCNT_Msk',['../group___peripheral___registers___bits___definition.html#ga285281ff18968724fb73d8dc292b930b',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdoeptsiz_5fpktcnt_5fpos_631',['USB_OTG_DOEPTSIZ_PKTCNT_Pos',['../group___peripheral___registers___bits___definition.html#gad4b9ba7c05cf5f15d1d68d5f01097daf',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdoeptsiz_5fstupcnt_632',['USB_OTG_DOEPTSIZ_STUPCNT',['../group___peripheral___registers___bits___definition.html#ga5a99a82646ef5a7a7785bec2d07334b5',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdoeptsiz_5fstupcnt_5f0_633',['USB_OTG_DOEPTSIZ_STUPCNT_0',['../group___peripheral___registers___bits___definition.html#ga0cabae65ef4f05c5314de57beed11000',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdoeptsiz_5fstupcnt_5f1_634',['USB_OTG_DOEPTSIZ_STUPCNT_1',['../group___peripheral___registers___bits___definition.html#ga3b109418cfad831c4f292eb86d132f0e',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdoeptsiz_5fstupcnt_5fmsk_635',['USB_OTG_DOEPTSIZ_STUPCNT_Msk',['../group___peripheral___registers___bits___definition.html#gadcb0c6895cd600227f3a037dfbddbbc5',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdoeptsiz_5fstupcnt_5fpos_636',['USB_OTG_DOEPTSIZ_STUPCNT_Pos',['../group___peripheral___registers___bits___definition.html#gaaa3ab3c0bc7a7e35ff98521b58230188',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdoeptsiz_5fxfrsiz_637',['USB_OTG_DOEPTSIZ_XFRSIZ',['../group___peripheral___registers___bits___definition.html#gab954bdd4334a2643622e3d33fee16ad5',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdoeptsiz_5fxfrsiz_5fmsk_638',['USB_OTG_DOEPTSIZ_XFRSIZ_Msk',['../group___peripheral___registers___bits___definition.html#gaab5ef41f398424f0a7e6a4c7cd6010c2',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdoeptsiz_5fxfrsiz_5fpos_639',['USB_OTG_DOEPTSIZ_XFRSIZ_Pos',['../group___peripheral___registers___bits___definition.html#ga5fe13401b6bd1b7d884f5250ac4863bc',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdpid_640',['USB_OTG_DPID',['../group___peripheral___registers___bits___definition.html#gaba9fdf0a57d7a204dff9217d6b7e7a60',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdpid_5f0_641',['USB_OTG_DPID_0',['../group___peripheral___registers___bits___definition.html#ga0cb8aeddd0bc7c194224de1c601c3aea',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdpid_5f1_642',['USB_OTG_DPID_1',['../group___peripheral___registers___bits___definition.html#ga8822d847cc21c903bfe427927f3ebd8f',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdpid_5fmsk_643',['USB_OTG_DPID_Msk',['../group___peripheral___registers___bits___definition.html#ga2a99858955bd807f3b3ab817ccb22dbf',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdpid_5fpos_644',['USB_OTG_DPID_Pos',['../group___peripheral___registers___bits___definition.html#ga161e93b8ccc61342eb405c9956841d93',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdsts_5feerr_645',['USB_OTG_DSTS_EERR',['../group___peripheral___registers___bits___definition.html#gab9787add94a212edfffa82dd2fe47863',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdsts_5feerr_5fmsk_646',['USB_OTG_DSTS_EERR_Msk',['../group___peripheral___registers___bits___definition.html#ga3125d311d52b88b33109ffd3b1c2b194',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdsts_5feerr_5fpos_647',['USB_OTG_DSTS_EERR_Pos',['../group___peripheral___registers___bits___definition.html#ga7f6d51148141137f5b622379f7966cca',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdsts_5fenumspd_648',['USB_OTG_DSTS_ENUMSPD',['../group___peripheral___registers___bits___definition.html#gaf68e749d3365b8b6aba2002718a16e94',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdsts_5fenumspd_5f0_649',['USB_OTG_DSTS_ENUMSPD_0',['../group___peripheral___registers___bits___definition.html#ga4b85a30093b2120bd2f0dca9a2fabd46',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdsts_5fenumspd_5f1_650',['USB_OTG_DSTS_ENUMSPD_1',['../group___peripheral___registers___bits___definition.html#ga38dcfba81d842a0514d24f42fbea815c',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdsts_5fenumspd_5fmsk_651',['USB_OTG_DSTS_ENUMSPD_Msk',['../group___peripheral___registers___bits___definition.html#ga270bfa6f7139f8a15af6a55c4b48c167',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdsts_5fenumspd_5fpos_652',['USB_OTG_DSTS_ENUMSPD_Pos',['../group___peripheral___registers___bits___definition.html#ga86eea0eb8d965de29d5e33c0996001eb',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdsts_5ffnsof_653',['USB_OTG_DSTS_FNSOF',['../group___peripheral___registers___bits___definition.html#ga047ff56c1d9fbd02b738f2a5bf768a45',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdsts_5ffnsof_5fmsk_654',['USB_OTG_DSTS_FNSOF_Msk',['../group___peripheral___registers___bits___definition.html#ga9aa7bb17de01b147c98b6c23e4f146cd',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdsts_5ffnsof_5fpos_655',['USB_OTG_DSTS_FNSOF_Pos',['../group___peripheral___registers___bits___definition.html#ga27e73ebdbb3e3c257187546cda07466a',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdsts_5fsuspsts_656',['USB_OTG_DSTS_SUSPSTS',['../group___peripheral___registers___bits___definition.html#ga8faf1dcd3fb686cc4acf23ca6f4b71ec',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdsts_5fsuspsts_5fmsk_657',['USB_OTG_DSTS_SUSPSTS_Msk',['../group___peripheral___registers___bits___definition.html#ga474e845231f3f8f1de1d4be1e99167ca',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdsts_5fsuspsts_5fpos_658',['USB_OTG_DSTS_SUSPSTS_Pos',['../group___peripheral___registers___bits___definition.html#gac2c34163004ae2c55ba72739f5accd8d',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdthrctl_5farpen_659',['USB_OTG_DTHRCTL_ARPEN',['../group___peripheral___registers___bits___definition.html#gababbacdcc33bdd2be91513fd31c4efbc',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdthrctl_5farpen_5fmsk_660',['USB_OTG_DTHRCTL_ARPEN_Msk',['../group___peripheral___registers___bits___definition.html#gac23e9fc77b37f86b49a3e6f9bb4f711b',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdthrctl_5farpen_5fpos_661',['USB_OTG_DTHRCTL_ARPEN_Pos',['../group___peripheral___registers___bits___definition.html#ga1905c98a839664f140afc08295b0e5a2',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdthrctl_5fisothren_662',['USB_OTG_DTHRCTL_ISOTHREN',['../group___peripheral___registers___bits___definition.html#ga04e741a79f38ab24adc52bd7143af049',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdthrctl_5fisothren_5fmsk_663',['USB_OTG_DTHRCTL_ISOTHREN_Msk',['../group___peripheral___registers___bits___definition.html#gace1a2aa524f45130efc83e053acb865b',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdthrctl_5fisothren_5fpos_664',['USB_OTG_DTHRCTL_ISOTHREN_Pos',['../group___peripheral___registers___bits___definition.html#gacad27878401eaeb8cbf31bcca1aec333',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdthrctl_5fnonisothren_665',['USB_OTG_DTHRCTL_NONISOTHREN',['../group___peripheral___registers___bits___definition.html#ga90deedb84e953f01c80f382926cc07f7',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdthrctl_5fnonisothren_5fmsk_666',['USB_OTG_DTHRCTL_NONISOTHREN_Msk',['../group___peripheral___registers___bits___definition.html#gafb5a75e2c30cc44403d12a7fa3f3bbd6',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdthrctl_5fnonisothren_5fpos_667',['USB_OTG_DTHRCTL_NONISOTHREN_Pos',['../group___peripheral___registers___bits___definition.html#gaa27b3b7a9c8d5bd43eeed11c120b6b94',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdthrctl_5frxthren_668',['USB_OTG_DTHRCTL_RXTHREN',['../group___peripheral___registers___bits___definition.html#gaccd6ccdda30038743b8857ec89c897d0',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdthrctl_5frxthren_5fmsk_669',['USB_OTG_DTHRCTL_RXTHREN_Msk',['../group___peripheral___registers___bits___definition.html#gad7ea756a244f4f1c30f3d1feab40f90d',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdthrctl_5frxthren_5fpos_670',['USB_OTG_DTHRCTL_RXTHREN_Pos',['../group___peripheral___registers___bits___definition.html#ga18423f010a887869d9240587099fb245',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdthrctl_5frxthrlen_671',['USB_OTG_DTHRCTL_RXTHRLEN',['../group___peripheral___registers___bits___definition.html#ga33dd5d34180983c398a1944eafd47fac',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdthrctl_5frxthrlen_5f0_672',['USB_OTG_DTHRCTL_RXTHRLEN_0',['../group___peripheral___registers___bits___definition.html#gabfb6edd2de6ee8c4680a604711920b83',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdthrctl_5frxthrlen_5f1_673',['USB_OTG_DTHRCTL_RXTHRLEN_1',['../group___peripheral___registers___bits___definition.html#ga933148ffeb4784606b66a3229d77b921',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdthrctl_5frxthrlen_5f2_674',['USB_OTG_DTHRCTL_RXTHRLEN_2',['../group___peripheral___registers___bits___definition.html#ga4208cac73e194db119277ed12a69eedd',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdthrctl_5frxthrlen_5f3_675',['USB_OTG_DTHRCTL_RXTHRLEN_3',['../group___peripheral___registers___bits___definition.html#ga1c499a8120b848257819105790c44aef',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdthrctl_5frxthrlen_5f4_676',['USB_OTG_DTHRCTL_RXTHRLEN_4',['../group___peripheral___registers___bits___definition.html#ga5b8e7493d15184845243110b44ef4e45',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdthrctl_5frxthrlen_5f5_677',['USB_OTG_DTHRCTL_RXTHRLEN_5',['../group___peripheral___registers___bits___definition.html#gac1a10cc9b79775c3c0067a1b005862f0',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdthrctl_5frxthrlen_5f6_678',['USB_OTG_DTHRCTL_RXTHRLEN_6',['../group___peripheral___registers___bits___definition.html#gaee1447a1041c5a2b2a88fd2edacb9cdf',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdthrctl_5frxthrlen_5f7_679',['USB_OTG_DTHRCTL_RXTHRLEN_7',['../group___peripheral___registers___bits___definition.html#ga2f753e4d8650b04a44a092c7581cda36',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdthrctl_5frxthrlen_5f8_680',['USB_OTG_DTHRCTL_RXTHRLEN_8',['../group___peripheral___registers___bits___definition.html#gabb2dbf9b5e747cff136273b67258c36e',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdthrctl_5frxthrlen_5fmsk_681',['USB_OTG_DTHRCTL_RXTHRLEN_Msk',['../group___peripheral___registers___bits___definition.html#ga86e3d673a7dffea2edb0212199ca55d8',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdthrctl_5frxthrlen_5fpos_682',['USB_OTG_DTHRCTL_RXTHRLEN_Pos',['../group___peripheral___registers___bits___definition.html#ga989aba6821e2352c5690961510aad20c',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdthrctl_5ftxthrlen_683',['USB_OTG_DTHRCTL_TXTHRLEN',['../group___peripheral___registers___bits___definition.html#ga89abc875678e55dd6f0404d06fd71ac4',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdthrctl_5ftxthrlen_5f0_684',['USB_OTG_DTHRCTL_TXTHRLEN_0',['../group___peripheral___registers___bits___definition.html#ga6dc7e5363efa0a295aa92980b6cc04fa',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdthrctl_5ftxthrlen_5f1_685',['USB_OTG_DTHRCTL_TXTHRLEN_1',['../group___peripheral___registers___bits___definition.html#ga77e5b0ffa7872b1a86a5c1b595e1010e',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdthrctl_5ftxthrlen_5f2_686',['USB_OTG_DTHRCTL_TXTHRLEN_2',['../group___peripheral___registers___bits___definition.html#ga05f69f648818f4c055d939afc66946ae',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdthrctl_5ftxthrlen_5f3_687',['USB_OTG_DTHRCTL_TXTHRLEN_3',['../group___peripheral___registers___bits___definition.html#gaf30c1d04c0cdd9d55beae15953ec7693',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdthrctl_5ftxthrlen_5f4_688',['USB_OTG_DTHRCTL_TXTHRLEN_4',['../group___peripheral___registers___bits___definition.html#ga49b7ac9081652b86cba455dd0241ec67',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdthrctl_5ftxthrlen_5f5_689',['USB_OTG_DTHRCTL_TXTHRLEN_5',['../group___peripheral___registers___bits___definition.html#ga5adde0e7e9543650a413afa08241a990',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdthrctl_5ftxthrlen_5f6_690',['USB_OTG_DTHRCTL_TXTHRLEN_6',['../group___peripheral___registers___bits___definition.html#ga13d34b0ad2fc0bb5c9fef41cf8d139a2',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdthrctl_5ftxthrlen_5f7_691',['USB_OTG_DTHRCTL_TXTHRLEN_7',['../group___peripheral___registers___bits___definition.html#ga86ac850ea713f1545dcd207e2e5bd104',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdthrctl_5ftxthrlen_5f8_692',['USB_OTG_DTHRCTL_TXTHRLEN_8',['../group___peripheral___registers___bits___definition.html#ga4eafc52de58d4605d63ba125ceb08e93',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdthrctl_5ftxthrlen_5fmsk_693',['USB_OTG_DTHRCTL_TXTHRLEN_Msk',['../group___peripheral___registers___bits___definition.html#ga43e14dc940b6baf117c256d9c60aa2e0',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdthrctl_5ftxthrlen_5fpos_694',['USB_OTG_DTHRCTL_TXTHRLEN_Pos',['../group___peripheral___registers___bits___definition.html#gab8369129264871f2a808694ae56b143a',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdtxfsts_5fineptfsav_695',['USB_OTG_DTXFSTS_INEPTFSAV',['../group___peripheral___registers___bits___definition.html#gae1789e8c79b7a271a58f56cbff4bd03a',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdtxfsts_5fineptfsav_5fmsk_696',['USB_OTG_DTXFSTS_INEPTFSAV_Msk',['../group___peripheral___registers___bits___definition.html#ga9c1a0115d517ac979a61c81763f4ce8f',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdtxfsts_5fineptfsav_5fpos_697',['USB_OTG_DTXFSTS_INEPTFSAV_Pos',['../group___peripheral___registers___bits___definition.html#ga7bd1cf28f02f4bd52c71afee6f718e27',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdvbusdis_5fvbusdt_698',['USB_OTG_DVBUSDIS_VBUSDT',['../group___peripheral___registers___bits___definition.html#ga749c7152aea411faaaeec1b43afb43e5',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdvbusdis_5fvbusdt_5fmsk_699',['USB_OTG_DVBUSDIS_VBUSDT_Msk',['../group___peripheral___registers___bits___definition.html#ga05d481daeec0e3867bc14ddbf33c668b',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdvbusdis_5fvbusdt_5fpos_700',['USB_OTG_DVBUSDIS_VBUSDT_Pos',['../group___peripheral___registers___bits___definition.html#ga068bb85a1956e5ef91ed2556a68814da',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdvbuspulse_5fdvbusp_701',['USB_OTG_DVBUSPULSE_DVBUSP',['../group___peripheral___registers___bits___definition.html#ga4dc9a44df3a6bf09319feb0ade70219b',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdvbuspulse_5fdvbusp_5fmsk_702',['USB_OTG_DVBUSPULSE_DVBUSP_Msk',['../group___peripheral___registers___bits___definition.html#gaa0f53728ef57cfd0c9099458e5ede08b',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fdvbuspulse_5fdvbusp_5fpos_703',['USB_OTG_DVBUSPULSE_DVBUSP_Pos',['../group___peripheral___registers___bits___definition.html#gaa1debd748822446b78fd35dd4e5bffb2',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fep_5freg_5fsize_704',['USB_OTG_EP_REG_SIZE',['../group___peripheral__memory__map.html#ga6fdb7429ad88e2d69440d6ecc4f4199e',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fepnum_705',['USB_OTG_EPNUM',['../group___peripheral___registers___bits___definition.html#ga91d336fd8272e4c22fc474e468b81af9',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fepnum_5f0_706',['USB_OTG_EPNUM_0',['../group___peripheral___registers___bits___definition.html#ga61585b0ce43fd0b1e6b228598afc219c',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fepnum_5f1_707',['USB_OTG_EPNUM_1',['../group___peripheral___registers___bits___definition.html#ga483d3ad09cb1f0a2c0b162c8a55ed7c6',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fepnum_5f2_708',['USB_OTG_EPNUM_2',['../group___peripheral___registers___bits___definition.html#gac2438798104047b9b51f8c773d02858a',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fepnum_5f3_709',['USB_OTG_EPNUM_3',['../group___peripheral___registers___bits___definition.html#ga42c2df6bfed558ca73545573166296bf',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fepnum_5fmsk_710',['USB_OTG_EPNUM_Msk',['../group___peripheral___registers___bits___definition.html#gaa45e8d6116688de705fd0d55680e1a87',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fepnum_5fpos_711',['USB_OTG_EPNUM_Pos',['../group___peripheral___registers___bits___definition.html#ga0b40ae8187cbd4c17738b04c43cf7fbb',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5ffifo_5fbase_712',['USB_OTG_FIFO_BASE',['../group___peripheral__memory__map.html#gace340350802904868673f0e839c4fa04',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5ffifo_5fsize_713',['USB_OTG_FIFO_SIZE',['../group___peripheral__memory__map.html#ga8781c4b2406c740d9fe540737a6a0188',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5ffrmnum_714',['USB_OTG_FRMNUM',['../group___peripheral___registers___bits___definition.html#ga69105bca4abdabe5c66a1c44ae714776',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5ffrmnum_5f0_715',['USB_OTG_FRMNUM_0',['../group___peripheral___registers___bits___definition.html#ga6a9a2d9f4d804f38e9ee29038139498d',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5ffrmnum_5f1_716',['USB_OTG_FRMNUM_1',['../group___peripheral___registers___bits___definition.html#ga4d93a3bde8de46b481691a1e87b36bfd',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5ffrmnum_5f2_717',['USB_OTG_FRMNUM_2',['../group___peripheral___registers___bits___definition.html#ga8f8be72a63a9942462f0752d5371e619',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5ffrmnum_5f3_718',['USB_OTG_FRMNUM_3',['../group___peripheral___registers___bits___definition.html#ga9b50095fee4cb94be4d1d02aadd3964e',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5ffrmnum_5fmsk_719',['USB_OTG_FRMNUM_Msk',['../group___peripheral___registers___bits___definition.html#gab3dde44ba66dda008f4f22e73d6de3eb',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5ffrmnum_5fpos_720',['USB_OTG_FRMNUM_Pos',['../group___peripheral___registers___bits___definition.html#ga1b5bcd968b0874ed977dfafacb1d51f1',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5ffs_721',['USB_OTG_FS',['../group___peripheral__declaration.html#ga9ebb053ee138fb47cdfede0e3371123d',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5ffs_5fhost_5fmax_5fchannel_5fnbr_722',['USB_OTG_FS_HOST_MAX_CHANNEL_NBR',['../group___exported__macros.html#ga4c58971ce9062c1c7bc42e1c7ea4df32',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5ffs_5fmax_5fin_5fendpoints_723',['USB_OTG_FS_MAX_IN_ENDPOINTS',['../group___exported__macros.html#gaccec7ca403e63ea963c363ceb7301ca6',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5ffs_5fmax_5fout_5fendpoints_724',['USB_OTG_FS_MAX_OUT_ENDPOINTS',['../group___exported__macros.html#ga1d58ab8276cfdef9aa868bfdd2590aae',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5ffs_5fperiph_725',['usb_otg_fs_periph',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#gab7326fc264f9026f7d5be1914a222257',1,'stm32f4xx_periph_registers.c']]], - ['usb_5fotg_5ffs_5fperiph_5fbase_726',['USB_OTG_FS_PERIPH_BASE',['../group___peripheral__memory__map.html#gaa86d4c80849a74938924e73937b904e7',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5ffs_5ftotal_5ffifo_5fsize_727',['USB_OTG_FS_TOTAL_FIFO_SIZE',['../group___exported__macros.html#ga1e726d88af0f77cb8a49ff7b666fd990',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgahbcfg_5fdmaen_728',['USB_OTG_GAHBCFG_DMAEN',['../group___peripheral___registers___bits___definition.html#ga46b9ace9572bb6ec977594c8b4b0825f',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgahbcfg_5fdmaen_5fmsk_729',['USB_OTG_GAHBCFG_DMAEN_Msk',['../group___peripheral___registers___bits___definition.html#ga67d9f42ed7111f4a498e213ceae2d357',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgahbcfg_5fdmaen_5fpos_730',['USB_OTG_GAHBCFG_DMAEN_Pos',['../group___peripheral___registers___bits___definition.html#gad4dbb305ea29c5269f275bb2f727fc0a',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgahbcfg_5fgint_731',['USB_OTG_GAHBCFG_GINT',['../group___peripheral___registers___bits___definition.html#gafd1bbe9e90d56d2aa225ff5532e15c6e',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgahbcfg_5fgint_5fmsk_732',['USB_OTG_GAHBCFG_GINT_Msk',['../group___peripheral___registers___bits___definition.html#gadfab3e804f69049a10d08b30d986ecf0',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgahbcfg_5fgint_5fpos_733',['USB_OTG_GAHBCFG_GINT_Pos',['../group___peripheral___registers___bits___definition.html#ga02c768ed073f3aaa6a43cf514e44a1d5',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgahbcfg_5fhbstlen_734',['USB_OTG_GAHBCFG_HBSTLEN',['../group___peripheral___registers___bits___definition.html#ga2ffbca11bd10b4d94843a5084078fdd4',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgahbcfg_5fhbstlen_5f0_735',['USB_OTG_GAHBCFG_HBSTLEN_0',['../group___peripheral___registers___bits___definition.html#gacccaf834ac65b3859e6f0519d2c4d75d',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgahbcfg_5fhbstlen_5f1_736',['USB_OTG_GAHBCFG_HBSTLEN_1',['../group___peripheral___registers___bits___definition.html#ga944e91046cd27e0bea8954bd56a45a94',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgahbcfg_5fhbstlen_5f2_737',['USB_OTG_GAHBCFG_HBSTLEN_2',['../group___peripheral___registers___bits___definition.html#ga3b9994176dc5115431b0a537ad26900c',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgahbcfg_5fhbstlen_5f3_738',['USB_OTG_GAHBCFG_HBSTLEN_3',['../group___peripheral___registers___bits___definition.html#ga1ac6781cf82fd4c21a342b4e8c8f25f8',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgahbcfg_5fhbstlen_5f4_739',['USB_OTG_GAHBCFG_HBSTLEN_4',['../group___peripheral___registers___bits___definition.html#gae60a1aed37523932d2cbfa6e78963e28',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgahbcfg_5fhbstlen_5fmsk_740',['USB_OTG_GAHBCFG_HBSTLEN_Msk',['../group___peripheral___registers___bits___definition.html#ga0f129cc1f698c1a272851d848541397c',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgahbcfg_5fhbstlen_5fpos_741',['USB_OTG_GAHBCFG_HBSTLEN_Pos',['../group___peripheral___registers___bits___definition.html#gabaef2f23bb565f244cae0c2fed8655bf',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgahbcfg_5fptxfelvl_742',['USB_OTG_GAHBCFG_PTXFELVL',['../group___peripheral___registers___bits___definition.html#ga7443f8ddb5b67b506637b282923a0c57',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgahbcfg_5fptxfelvl_5fmsk_743',['USB_OTG_GAHBCFG_PTXFELVL_Msk',['../group___peripheral___registers___bits___definition.html#ga1ce05358bc5a54302af1f296bd1338c4',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgahbcfg_5fptxfelvl_5fpos_744',['USB_OTG_GAHBCFG_PTXFELVL_Pos',['../group___peripheral___registers___bits___definition.html#gaf86fe83bcec3b4ce6a21c18bb0996af8',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgahbcfg_5ftxfelvl_745',['USB_OTG_GAHBCFG_TXFELVL',['../group___peripheral___registers___bits___definition.html#ga6a8af9d1d89b731426db773905ae4450',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgahbcfg_5ftxfelvl_5fmsk_746',['USB_OTG_GAHBCFG_TXFELVL_Msk',['../group___peripheral___registers___bits___definition.html#gadbed93fcc3e44debab0f9a6b8f56a4e4',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgahbcfg_5ftxfelvl_5fpos_747',['USB_OTG_GAHBCFG_TXFELVL_Pos',['../group___peripheral___registers___bits___definition.html#ga59620c8a8f85f5f5986b0382152e2564',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgccfg_5fi2cpaden_748',['USB_OTG_GCCFG_I2CPADEN',['../group___peripheral___registers___bits___definition.html#ga048469450e7d634cafa2e5677e5182b3',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgccfg_5fi2cpaden_5fmsk_749',['USB_OTG_GCCFG_I2CPADEN_Msk',['../group___peripheral___registers___bits___definition.html#gaa4d5a74bbfa9c61ca56b7b1f5a511dd3',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgccfg_5fi2cpaden_5fpos_750',['USB_OTG_GCCFG_I2CPADEN_Pos',['../group___peripheral___registers___bits___definition.html#ga5bd96a2a753042888490b2d8b5cdae0f',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgccfg_5fnovbussens_751',['USB_OTG_GCCFG_NOVBUSSENS',['../group___peripheral___registers___bits___definition.html#ga4b38845c9338d0637983b3d81fc0c95d',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgccfg_5fnovbussens_5fmsk_752',['USB_OTG_GCCFG_NOVBUSSENS_Msk',['../group___peripheral___registers___bits___definition.html#ga84a118dc6bff7012b8a6d944b15089b8',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgccfg_5fnovbussens_5fpos_753',['USB_OTG_GCCFG_NOVBUSSENS_Pos',['../group___peripheral___registers___bits___definition.html#ga198d2b56aa36042fd5874d004d8a71f5',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgccfg_5fpwrdwn_754',['USB_OTG_GCCFG_PWRDWN',['../group___peripheral___registers___bits___definition.html#ga4c298cedbc73302fae613084ad098b22',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgccfg_5fpwrdwn_5fmsk_755',['USB_OTG_GCCFG_PWRDWN_Msk',['../group___peripheral___registers___bits___definition.html#ga29705f28087b457d2e6d6ade469b8da8',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgccfg_5fpwrdwn_5fpos_756',['USB_OTG_GCCFG_PWRDWN_Pos',['../group___peripheral___registers___bits___definition.html#gaa044953a65f22022f0b54cf1f35216cc',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgccfg_5fsofouten_757',['USB_OTG_GCCFG_SOFOUTEN',['../group___peripheral___registers___bits___definition.html#gac3caba9befa711f3bdeb99e0ed33d608',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgccfg_5fsofouten_5fmsk_758',['USB_OTG_GCCFG_SOFOUTEN_Msk',['../group___peripheral___registers___bits___definition.html#ga3e05968150501b4f565898b43d33aed8',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgccfg_5fsofouten_5fpos_759',['USB_OTG_GCCFG_SOFOUTEN_Pos',['../group___peripheral___registers___bits___definition.html#ga36422f7842d3381290b5c7f1e1d920c8',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgccfg_5fvbusasen_760',['USB_OTG_GCCFG_VBUSASEN',['../group___peripheral___registers___bits___definition.html#ga83a0db31f98476dc46d77a77475c2991',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgccfg_5fvbusasen_5fmsk_761',['USB_OTG_GCCFG_VBUSASEN_Msk',['../group___peripheral___registers___bits___definition.html#gaa234c38562741de2c25aa2d87a53b2b9',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgccfg_5fvbusasen_5fpos_762',['USB_OTG_GCCFG_VBUSASEN_Pos',['../group___peripheral___registers___bits___definition.html#gaa59fa04d9f6d8e352b2a880b2cdd6163',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgccfg_5fvbusbsen_763',['USB_OTG_GCCFG_VBUSBSEN',['../group___peripheral___registers___bits___definition.html#ga1aa57c29a5c04621f54b2125536d11b2',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgccfg_5fvbusbsen_5fmsk_764',['USB_OTG_GCCFG_VBUSBSEN_Msk',['../group___peripheral___registers___bits___definition.html#ga11b625bb997a725e1965d4a678f0bea4',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgccfg_5fvbusbsen_5fpos_765',['USB_OTG_GCCFG_VBUSBSEN_Pos',['../group___peripheral___registers___bits___definition.html#ga90a2fb91409323a578610f09cac80a12',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgintmsk_5fcidschgm_766',['USB_OTG_GINTMSK_CIDSCHGM',['../group___peripheral___registers___bits___definition.html#gabe390b69b7379dc93f9c25b6b35a71f2',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgintmsk_5fcidschgm_5fmsk_767',['USB_OTG_GINTMSK_CIDSCHGM_Msk',['../group___peripheral___registers___bits___definition.html#gaae4b71ca238b78977cad1c0362044065',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgintmsk_5fcidschgm_5fpos_768',['USB_OTG_GINTMSK_CIDSCHGM_Pos',['../group___peripheral___registers___bits___definition.html#ga17256c345931101867a6244fffd296e5',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgintmsk_5fdiscint_769',['USB_OTG_GINTMSK_DISCINT',['../group___peripheral___registers___bits___definition.html#ga6de24048cab1948503c26d09ee5a4397',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgintmsk_5fdiscint_5fmsk_770',['USB_OTG_GINTMSK_DISCINT_Msk',['../group___peripheral___registers___bits___definition.html#ga34f387040509ac1ea94b3dbc95302e54',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgintmsk_5fdiscint_5fpos_771',['USB_OTG_GINTMSK_DISCINT_Pos',['../group___peripheral___registers___bits___definition.html#ga9413f2f7748902aa9b9e6997fdb2e59c',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgintmsk_5fenumdnem_772',['USB_OTG_GINTMSK_ENUMDNEM',['../group___peripheral___registers___bits___definition.html#ga6066078d17a4216093855cc210ab6764',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgintmsk_5fenumdnem_5fmsk_773',['USB_OTG_GINTMSK_ENUMDNEM_Msk',['../group___peripheral___registers___bits___definition.html#gabc647118b4e7ef089e014a6da2e42f9e',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgintmsk_5fenumdnem_5fpos_774',['USB_OTG_GINTMSK_ENUMDNEM_Pos',['../group___peripheral___registers___bits___definition.html#ga7bafbc1ce354519f9b0d53d8d8f4187f',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgintmsk_5feopfm_775',['USB_OTG_GINTMSK_EOPFM',['../group___peripheral___registers___bits___definition.html#gabd06eee1627ac5ba7212a728f19e4fe8',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgintmsk_5feopfm_5fmsk_776',['USB_OTG_GINTMSK_EOPFM_Msk',['../group___peripheral___registers___bits___definition.html#ga53404953b235600349f7f631caff940b',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgintmsk_5feopfm_5fpos_777',['USB_OTG_GINTMSK_EOPFM_Pos',['../group___peripheral___registers___bits___definition.html#gac9dc782a42d4b724d28494d0030b9a71',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgintmsk_5fepmism_778',['USB_OTG_GINTMSK_EPMISM',['../group___peripheral___registers___bits___definition.html#ga35ecb8ef940b0ace19712f5fefa1193c',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgintmsk_5fepmism_5fmsk_779',['USB_OTG_GINTMSK_EPMISM_Msk',['../group___peripheral___registers___bits___definition.html#gaf538166d934b884ae39bdfe98cbd16b6',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgintmsk_5fepmism_5fpos_780',['USB_OTG_GINTMSK_EPMISM_Pos',['../group___peripheral___registers___bits___definition.html#gad2c92fa81e0b29cbf873ac24bdcbc1ac',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgintmsk_5fesuspm_781',['USB_OTG_GINTMSK_ESUSPM',['../group___peripheral___registers___bits___definition.html#gafa0fc70a7e7198d7d6f179d9cae29394',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgintmsk_5fesuspm_5fmsk_782',['USB_OTG_GINTMSK_ESUSPM_Msk',['../group___peripheral___registers___bits___definition.html#gabed33a7a408afafbce8c6243e2345433',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgintmsk_5fesuspm_5fpos_783',['USB_OTG_GINTMSK_ESUSPM_Pos',['../group___peripheral___registers___bits___definition.html#ga7751043116b431d9ad344b0a58d57a9b',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgintmsk_5ffsuspm_784',['USB_OTG_GINTMSK_FSUSPM',['../group___peripheral___registers___bits___definition.html#gae29d6ecd5e6c802a6214b814f6466b58',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgintmsk_5ffsuspm_5fmsk_785',['USB_OTG_GINTMSK_FSUSPM_Msk',['../group___peripheral___registers___bits___definition.html#ga941f4e537d06501247b906cbd37410c7',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgintmsk_5ffsuspm_5fpos_786',['USB_OTG_GINTMSK_FSUSPM_Pos',['../group___peripheral___registers___bits___definition.html#ga2fc5d32a7e8a6828c986edb99360bb61',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgintmsk_5fginakeffm_787',['USB_OTG_GINTMSK_GINAKEFFM',['../group___peripheral___registers___bits___definition.html#ga3eb2bbcd11ddee87630472eb01897d3d',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgintmsk_5fginakeffm_5fmsk_788',['USB_OTG_GINTMSK_GINAKEFFM_Msk',['../group___peripheral___registers___bits___definition.html#ga53aed86becf8549f65f3038d0d5da115',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgintmsk_5fginakeffm_5fpos_789',['USB_OTG_GINTMSK_GINAKEFFM_Pos',['../group___peripheral___registers___bits___definition.html#ga2bc09652469952607ef86af53e1faa20',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgintmsk_5fgonakeffm_790',['USB_OTG_GINTMSK_GONAKEFFM',['../group___peripheral___registers___bits___definition.html#gaba9de7677f70e7fcb4dab90228bdb484',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgintmsk_5fgonakeffm_5fmsk_791',['USB_OTG_GINTMSK_GONAKEFFM_Msk',['../group___peripheral___registers___bits___definition.html#ga360c770dba2809d002ba1cf317179988',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgintmsk_5fgonakeffm_5fpos_792',['USB_OTG_GINTMSK_GONAKEFFM_Pos',['../group___peripheral___registers___bits___definition.html#ga8cd00e95e293a7cf81e2912b02a7cf58',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgintmsk_5fhcim_793',['USB_OTG_GINTMSK_HCIM',['../group___peripheral___registers___bits___definition.html#ga1ff8e84db67f2f7c46998c2236f9c6cc',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgintmsk_5fhcim_5fmsk_794',['USB_OTG_GINTMSK_HCIM_Msk',['../group___peripheral___registers___bits___definition.html#ga91482bd34447d0e44c2bf4ad9b9e3aa0',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgintmsk_5fhcim_5fpos_795',['USB_OTG_GINTMSK_HCIM_Pos',['../group___peripheral___registers___bits___definition.html#gad83cad33689d2b786e2ea01faece0f6a',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgintmsk_5fiepint_796',['USB_OTG_GINTMSK_IEPINT',['../group___peripheral___registers___bits___definition.html#gaa7b0d0879e3d57e3a21610ab590da6ae',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgintmsk_5fiepint_5fmsk_797',['USB_OTG_GINTMSK_IEPINT_Msk',['../group___peripheral___registers___bits___definition.html#gae283ace2a396c147245a581322b25761',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgintmsk_5fiepint_5fpos_798',['USB_OTG_GINTMSK_IEPINT_Pos',['../group___peripheral___registers___bits___definition.html#ga6cf4b99bff0d732dfc46a83947266fce',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgintmsk_5fiisoixfrm_799',['USB_OTG_GINTMSK_IISOIXFRM',['../group___peripheral___registers___bits___definition.html#ga9a505c6af38c507dfe84028d6194e08e',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgintmsk_5fiisoixfrm_5fmsk_800',['USB_OTG_GINTMSK_IISOIXFRM_Msk',['../group___peripheral___registers___bits___definition.html#ga932753540aef5f14f8801ea26789cef4',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgintmsk_5fiisoixfrm_5fpos_801',['USB_OTG_GINTMSK_IISOIXFRM_Pos',['../group___peripheral___registers___bits___definition.html#ga7f677a85809f7741c7bce7d6486f4f0b',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgintmsk_5fisoodrpm_802',['USB_OTG_GINTMSK_ISOODRPM',['../group___peripheral___registers___bits___definition.html#ga1e01710480bf4d5edf5c344798c88624',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgintmsk_5fisoodrpm_5fmsk_803',['USB_OTG_GINTMSK_ISOODRPM_Msk',['../group___peripheral___registers___bits___definition.html#ga442bbb88091efa2c2f707909e51477f3',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgintmsk_5fisoodrpm_5fpos_804',['USB_OTG_GINTMSK_ISOODRPM_Pos',['../group___peripheral___registers___bits___definition.html#ga594d179afd1c73ca5c341fe09a67cbe7',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgintmsk_5fmmism_805',['USB_OTG_GINTMSK_MMISM',['../group___peripheral___registers___bits___definition.html#ga49ccdddf721bcdb2d44915f210b3e2e2',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgintmsk_5fmmism_5fmsk_806',['USB_OTG_GINTMSK_MMISM_Msk',['../group___peripheral___registers___bits___definition.html#gaf5ccb0f8c7955022c74175b060f1a5e4',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgintmsk_5fmmism_5fpos_807',['USB_OTG_GINTMSK_MMISM_Pos',['../group___peripheral___registers___bits___definition.html#ga2c01134b517eb3df18e9f5ef8468aa00',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgintmsk_5fnptxfem_808',['USB_OTG_GINTMSK_NPTXFEM',['../group___peripheral___registers___bits___definition.html#ga40b7860f3dc90a9f46e46e2dc133f2e4',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgintmsk_5fnptxfem_5fmsk_809',['USB_OTG_GINTMSK_NPTXFEM_Msk',['../group___peripheral___registers___bits___definition.html#ga67278c309dddbbaa4cc520416c60d9be',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgintmsk_5fnptxfem_5fpos_810',['USB_OTG_GINTMSK_NPTXFEM_Pos',['../group___peripheral___registers___bits___definition.html#ga980f36264fcd2e20e5d0f53fbde196f1',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgintmsk_5foepint_811',['USB_OTG_GINTMSK_OEPINT',['../group___peripheral___registers___bits___definition.html#gaff1341cabf6155e197f657b12237dbb8',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgintmsk_5foepint_5fmsk_812',['USB_OTG_GINTMSK_OEPINT_Msk',['../group___peripheral___registers___bits___definition.html#gafcdffda36a1a980f7d77038e2e5acb29',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgintmsk_5foepint_5fpos_813',['USB_OTG_GINTMSK_OEPINT_Pos',['../group___peripheral___registers___bits___definition.html#ga7e646bf0709fd1662301a3e81e167e8f',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgintmsk_5fotgint_814',['USB_OTG_GINTMSK_OTGINT',['../group___peripheral___registers___bits___definition.html#ga1138fd4386ac29900b5c46ec7754b4ff',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgintmsk_5fotgint_5fmsk_815',['USB_OTG_GINTMSK_OTGINT_Msk',['../group___peripheral___registers___bits___definition.html#gaaff43c3b891b1e76c1e0242a2bab658c',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgintmsk_5fotgint_5fpos_816',['USB_OTG_GINTMSK_OTGINT_Pos',['../group___peripheral___registers___bits___definition.html#gaa6855459d5f63d37ac78e68e3b4e1c6c',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgintmsk_5fprtim_817',['USB_OTG_GINTMSK_PRTIM',['../group___peripheral___registers___bits___definition.html#gab8b1d4a903966e3ad62a8c299875a082',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgintmsk_5fprtim_5fmsk_818',['USB_OTG_GINTMSK_PRTIM_Msk',['../group___peripheral___registers___bits___definition.html#gaf2f3349ecf1e586219b22452f93d3725',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgintmsk_5fprtim_5fpos_819',['USB_OTG_GINTMSK_PRTIM_Pos',['../group___peripheral___registers___bits___definition.html#gaa2401d68c3c2a2d7229572c214377615',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgintmsk_5fptxfem_820',['USB_OTG_GINTMSK_PTXFEM',['../group___peripheral___registers___bits___definition.html#ga2744ae4d8e4c018a9a541af8ce68d01d',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgintmsk_5fptxfem_5fmsk_821',['USB_OTG_GINTMSK_PTXFEM_Msk',['../group___peripheral___registers___bits___definition.html#ga7146797fddc3a6bae1b081568810f35e',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgintmsk_5fptxfem_5fpos_822',['USB_OTG_GINTMSK_PTXFEM_Pos',['../group___peripheral___registers___bits___definition.html#gafe3c9998d70dd959dfa2afa021984bf6',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgintmsk_5fpxfrm_5fiisooxfrm_823',['USB_OTG_GINTMSK_PXFRM_IISOOXFRM',['../group___peripheral___registers___bits___definition.html#ga7fb0cdc2b7f0d8de8bbd8beaf3d69ae1',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgintmsk_5fpxfrm_5fiisooxfrm_5fmsk_824',['USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk',['../group___peripheral___registers___bits___definition.html#gae7fc2d5326991ca1857dcc4825688d21',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgintmsk_5fpxfrm_5fiisooxfrm_5fpos_825',['USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos',['../group___peripheral___registers___bits___definition.html#gad6a04d965084d298bd9902072771750f',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgintmsk_5frxflvlm_826',['USB_OTG_GINTMSK_RXFLVLM',['../group___peripheral___registers___bits___definition.html#gacca853066f092884b6c6af005eee77ed',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgintmsk_5frxflvlm_5fmsk_827',['USB_OTG_GINTMSK_RXFLVLM_Msk',['../group___peripheral___registers___bits___definition.html#ga2e0f9299eaf0a9987bb07d6d4ba05228',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgintmsk_5frxflvlm_5fpos_828',['USB_OTG_GINTMSK_RXFLVLM_Pos',['../group___peripheral___registers___bits___definition.html#ga18b2b2a3983a115a57c5a8187568b1f5',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgintmsk_5fsofm_829',['USB_OTG_GINTMSK_SOFM',['../group___peripheral___registers___bits___definition.html#gabbd83cf86e077c35fdc47e2a2666b391',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgintmsk_5fsofm_5fmsk_830',['USB_OTG_GINTMSK_SOFM_Msk',['../group___peripheral___registers___bits___definition.html#ga03618e5abf25fbd2f495b47e6121402a',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgintmsk_5fsofm_5fpos_831',['USB_OTG_GINTMSK_SOFM_Pos',['../group___peripheral___registers___bits___definition.html#ga9d66ca67546aa82347d6c35b525d514e',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgintmsk_5fsrqim_832',['USB_OTG_GINTMSK_SRQIM',['../group___peripheral___registers___bits___definition.html#ga896592b90dc012f3c4d004cd2280fb8f',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgintmsk_5fsrqim_5fmsk_833',['USB_OTG_GINTMSK_SRQIM_Msk',['../group___peripheral___registers___bits___definition.html#ga075abd906877496518197feccbd33643',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgintmsk_5fsrqim_5fpos_834',['USB_OTG_GINTMSK_SRQIM_Pos',['../group___peripheral___registers___bits___definition.html#ga2b7fa3ef7a96e9fc563a90bdd46348e9',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgintmsk_5fusbrst_835',['USB_OTG_GINTMSK_USBRST',['../group___peripheral___registers___bits___definition.html#ga0935f9f5fb77fee0755ceaaa787bb7f6',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgintmsk_5fusbrst_5fmsk_836',['USB_OTG_GINTMSK_USBRST_Msk',['../group___peripheral___registers___bits___definition.html#gaa9356341b405c61209433fd206e5edc4',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgintmsk_5fusbrst_5fpos_837',['USB_OTG_GINTMSK_USBRST_Pos',['../group___peripheral___registers___bits___definition.html#ga4e9ba2c03e49bbe6da21b73e57e73c26',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgintmsk_5fusbsuspm_838',['USB_OTG_GINTMSK_USBSUSPM',['../group___peripheral___registers___bits___definition.html#gaa7afb2b0396964430aeb1c7650012fe6',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgintmsk_5fusbsuspm_5fmsk_839',['USB_OTG_GINTMSK_USBSUSPM_Msk',['../group___peripheral___registers___bits___definition.html#ga44cee5301fb072bbea3e3b095d12e08d',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgintmsk_5fusbsuspm_5fpos_840',['USB_OTG_GINTMSK_USBSUSPM_Pos',['../group___peripheral___registers___bits___definition.html#gae7dc3bfe1c4f58eee80c49b1382df3a9',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgintmsk_5fwuim_841',['USB_OTG_GINTMSK_WUIM',['../group___peripheral___registers___bits___definition.html#gab641d285c79ab1b54c1d0c615afe87f5',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgintmsk_5fwuim_5fmsk_842',['USB_OTG_GINTMSK_WUIM_Msk',['../group___peripheral___registers___bits___definition.html#gaaf042e8854e22eacdba2faa356fe1b58',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgintmsk_5fwuim_5fpos_843',['USB_OTG_GINTMSK_WUIM_Pos',['../group___peripheral___registers___bits___definition.html#ga5cfe069353fb275d12afa3e0a55e7e11',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgintsts_5fboutnakeff_844',['USB_OTG_GINTSTS_BOUTNAKEFF',['../group___peripheral___registers___bits___definition.html#ga2966f09bafa5de7b1ee2bbddfc2628fc',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgintsts_5fboutnakeff_5fmsk_845',['USB_OTG_GINTSTS_BOUTNAKEFF_Msk',['../group___peripheral___registers___bits___definition.html#gad2197d4cc945121d9c75d7d9701e64c5',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgintsts_5fboutnakeff_5fpos_846',['USB_OTG_GINTSTS_BOUTNAKEFF_Pos',['../group___peripheral___registers___bits___definition.html#ga317bd1c94486fbce8c5fad17a0c1a888',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgintsts_5fcidschg_847',['USB_OTG_GINTSTS_CIDSCHG',['../group___peripheral___registers___bits___definition.html#ga931ec3cde136bc655953191000a16855',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgintsts_5fcidschg_5fmsk_848',['USB_OTG_GINTSTS_CIDSCHG_Msk',['../group___peripheral___registers___bits___definition.html#ga99288d13e884a0c4c554d3219bf56f51',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgintsts_5fcidschg_5fpos_849',['USB_OTG_GINTSTS_CIDSCHG_Pos',['../group___peripheral___registers___bits___definition.html#ga2695d008efbfc9c58c739542f8b5a3da',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgintsts_5fcmod_850',['USB_OTG_GINTSTS_CMOD',['../group___peripheral___registers___bits___definition.html#ga357496f2734867ddaf5a00cc61ff0191',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgintsts_5fcmod_5fmsk_851',['USB_OTG_GINTSTS_CMOD_Msk',['../group___peripheral___registers___bits___definition.html#gac38b6e32c779099c6cdba55e857f33e0',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgintsts_5fcmod_5fpos_852',['USB_OTG_GINTSTS_CMOD_Pos',['../group___peripheral___registers___bits___definition.html#gacd85c4ebf2f92718d17fe2d03542046a',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgintsts_5fdatafsusp_853',['USB_OTG_GINTSTS_DATAFSUSP',['../group___peripheral___registers___bits___definition.html#ga3e3ca6a1a8087c2c60a6980fa365776d',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgintsts_5fdatafsusp_5fmsk_854',['USB_OTG_GINTSTS_DATAFSUSP_Msk',['../group___peripheral___registers___bits___definition.html#gaa7b0f4c8c2bbc97f303685f3d236bb0b',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgintsts_5fdatafsusp_5fpos_855',['USB_OTG_GINTSTS_DATAFSUSP_Pos',['../group___peripheral___registers___bits___definition.html#gaf89d028cf11771da190cb02568a7c711',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgintsts_5fdiscint_856',['USB_OTG_GINTSTS_DISCINT',['../group___peripheral___registers___bits___definition.html#gaa7ef887fec0170857c82ad7a142cce98',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgintsts_5fdiscint_5fmsk_857',['USB_OTG_GINTSTS_DISCINT_Msk',['../group___peripheral___registers___bits___definition.html#ga9bf091e3d68accaeb0237700d77c9fc3',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgintsts_5fdiscint_5fpos_858',['USB_OTG_GINTSTS_DISCINT_Pos',['../group___peripheral___registers___bits___definition.html#ga2f782ddcb6d950f66177624dd4945906',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgintsts_5fenumdne_859',['USB_OTG_GINTSTS_ENUMDNE',['../group___peripheral___registers___bits___definition.html#ga88d4e3bdfdfc08a0cc2db20a34cbd598',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgintsts_5fenumdne_5fmsk_860',['USB_OTG_GINTSTS_ENUMDNE_Msk',['../group___peripheral___registers___bits___definition.html#ga4300a8cbfa6b81490d1747b67966f63b',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgintsts_5fenumdne_5fpos_861',['USB_OTG_GINTSTS_ENUMDNE_Pos',['../group___peripheral___registers___bits___definition.html#ga0fd05b6cfa6b54ec8258ccd9c4957859',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgintsts_5feopf_862',['USB_OTG_GINTSTS_EOPF',['../group___peripheral___registers___bits___definition.html#ga3e72bb03e22a40500af8f0cf4a34d4a8',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgintsts_5feopf_5fmsk_863',['USB_OTG_GINTSTS_EOPF_Msk',['../group___peripheral___registers___bits___definition.html#gab1c09e625f1d9bc1b803c5930d0e0298',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgintsts_5feopf_5fpos_864',['USB_OTG_GINTSTS_EOPF_Pos',['../group___peripheral___registers___bits___definition.html#ga3812f09bf415a4f1ee087e527f2f8ff2',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgintsts_5fesusp_865',['USB_OTG_GINTSTS_ESUSP',['../group___peripheral___registers___bits___definition.html#ga99d72bb12c0c5bf1d17290c49b392027',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgintsts_5fesusp_5fmsk_866',['USB_OTG_GINTSTS_ESUSP_Msk',['../group___peripheral___registers___bits___definition.html#ga6d506f6959a079205ed975944e8e1189',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgintsts_5fesusp_5fpos_867',['USB_OTG_GINTSTS_ESUSP_Pos',['../group___peripheral___registers___bits___definition.html#ga7cad1cf9f3eb790549029467955ec3ca',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgintsts_5fginakeff_868',['USB_OTG_GINTSTS_GINAKEFF',['../group___peripheral___registers___bits___definition.html#gafcf16d8b480c90018eaf6a717c989100',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgintsts_5fginakeff_5fmsk_869',['USB_OTG_GINTSTS_GINAKEFF_Msk',['../group___peripheral___registers___bits___definition.html#gaac8bce3f4c26db797f4d5bc1fbbf56a3',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgintsts_5fginakeff_5fpos_870',['USB_OTG_GINTSTS_GINAKEFF_Pos',['../group___peripheral___registers___bits___definition.html#ga99b72bc7ac0386f0db4fe4525c29e29a',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgintsts_5fhcint_871',['USB_OTG_GINTSTS_HCINT',['../group___peripheral___registers___bits___definition.html#gaedc1e52a9576a68e762d473c74225d2a',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgintsts_5fhcint_5fmsk_872',['USB_OTG_GINTSTS_HCINT_Msk',['../group___peripheral___registers___bits___definition.html#ga367de65d703dfe6cb6db52c76f996f85',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgintsts_5fhcint_5fpos_873',['USB_OTG_GINTSTS_HCINT_Pos',['../group___peripheral___registers___bits___definition.html#ga2ee336f2248571aab4d92adab169cff9',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgintsts_5fhprtint_874',['USB_OTG_GINTSTS_HPRTINT',['../group___peripheral___registers___bits___definition.html#gaaea3470d78914a470f9aba4367f7609d',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgintsts_5fhprtint_5fmsk_875',['USB_OTG_GINTSTS_HPRTINT_Msk',['../group___peripheral___registers___bits___definition.html#ga6d8553b58efc1196c9390088c8c28cac',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgintsts_5fhprtint_5fpos_876',['USB_OTG_GINTSTS_HPRTINT_Pos',['../group___peripheral___registers___bits___definition.html#gae42486a050eb3f8d9b546a06c955f831',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgintsts_5fiepint_877',['USB_OTG_GINTSTS_IEPINT',['../group___peripheral___registers___bits___definition.html#gaba3464cca97f65b232975c7ede5f3928',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgintsts_5fiepint_5fmsk_878',['USB_OTG_GINTSTS_IEPINT_Msk',['../group___peripheral___registers___bits___definition.html#gaa17b5ac65578ca653e41479144a6f1fc',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgintsts_5fiepint_5fpos_879',['USB_OTG_GINTSTS_IEPINT_Pos',['../group___peripheral___registers___bits___definition.html#gac190f90afc7a7800ce530536635c84db',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgintsts_5fiisoixfr_880',['USB_OTG_GINTSTS_IISOIXFR',['../group___peripheral___registers___bits___definition.html#ga64d9ad7356460a81cfb01e4a39d9fe14',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgintsts_5fiisoixfr_5fmsk_881',['USB_OTG_GINTSTS_IISOIXFR_Msk',['../group___peripheral___registers___bits___definition.html#gaf380deb48e6ff5e99ab18c74684dd51e',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgintsts_5fiisoixfr_5fpos_882',['USB_OTG_GINTSTS_IISOIXFR_Pos',['../group___peripheral___registers___bits___definition.html#gaac5e42d68b484721ee831b67ded60c83',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgintsts_5fisoodrp_883',['USB_OTG_GINTSTS_ISOODRP',['../group___peripheral___registers___bits___definition.html#gad550fd1c59868de214b47c06ef72af16',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgintsts_5fisoodrp_5fmsk_884',['USB_OTG_GINTSTS_ISOODRP_Msk',['../group___peripheral___registers___bits___definition.html#ga1ca4fde1933a925bf08275f0dc66fab3',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgintsts_5fisoodrp_5fpos_885',['USB_OTG_GINTSTS_ISOODRP_Pos',['../group___peripheral___registers___bits___definition.html#ga23417bce86919951f9fa8b03d99d9017',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgintsts_5fmmis_886',['USB_OTG_GINTSTS_MMIS',['../group___peripheral___registers___bits___definition.html#gab0c1ac0fa6a6a1b95d1dfc2b90383a39',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgintsts_5fmmis_5fmsk_887',['USB_OTG_GINTSTS_MMIS_Msk',['../group___peripheral___registers___bits___definition.html#ga6421c9e8b57f5343e197c85008ae82d5',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgintsts_5fmmis_5fpos_888',['USB_OTG_GINTSTS_MMIS_Pos',['../group___peripheral___registers___bits___definition.html#gaabeb493e86d2c0348c72313101d37d35',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgintsts_5fnptxfe_889',['USB_OTG_GINTSTS_NPTXFE',['../group___peripheral___registers___bits___definition.html#gaa84f417f4c311418505bcd04e6b9cbdf',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgintsts_5fnptxfe_5fmsk_890',['USB_OTG_GINTSTS_NPTXFE_Msk',['../group___peripheral___registers___bits___definition.html#ga750ef2111fed4186378990d5b4604911',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgintsts_5fnptxfe_5fpos_891',['USB_OTG_GINTSTS_NPTXFE_Pos',['../group___peripheral___registers___bits___definition.html#ga445da8fb063099b3ad27f761ccbb5717',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgintsts_5foepint_892',['USB_OTG_GINTSTS_OEPINT',['../group___peripheral___registers___bits___definition.html#ga7191a4ff25e5834f2ebdf0b61103294b',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgintsts_5foepint_5fmsk_893',['USB_OTG_GINTSTS_OEPINT_Msk',['../group___peripheral___registers___bits___definition.html#ga005e49f60424a85b2abd5315691093dd',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgintsts_5foepint_5fpos_894',['USB_OTG_GINTSTS_OEPINT_Pos',['../group___peripheral___registers___bits___definition.html#ga8df58b4dcba0c0e787cd6b5943342c52',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgintsts_5fotgint_895',['USB_OTG_GINTSTS_OTGINT',['../group___peripheral___registers___bits___definition.html#ga4a7ff1e46bfa5481522003726a1b6304',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgintsts_5fotgint_5fmsk_896',['USB_OTG_GINTSTS_OTGINT_Msk',['../group___peripheral___registers___bits___definition.html#ga7154d80c30c1c71720c35ce47aed996b',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgintsts_5fotgint_5fpos_897',['USB_OTG_GINTSTS_OTGINT_Pos',['../group___peripheral___registers___bits___definition.html#gaea398db5607b71a1f2502cf2070114b3',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgintsts_5fptxfe_898',['USB_OTG_GINTSTS_PTXFE',['../group___peripheral___registers___bits___definition.html#ga2ce397157106fc508c7f067d8efb7396',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgintsts_5fptxfe_5fmsk_899',['USB_OTG_GINTSTS_PTXFE_Msk',['../group___peripheral___registers___bits___definition.html#ga16028501b6619df3019f71876b649884',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgintsts_5fptxfe_5fpos_900',['USB_OTG_GINTSTS_PTXFE_Pos',['../group___peripheral___registers___bits___definition.html#ga5f8c0100f49bf442ec3aedc4b4d24d1c',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgintsts_5fpxfr_5fincompisoout_901',['USB_OTG_GINTSTS_PXFR_INCOMPISOOUT',['../group___peripheral___registers___bits___definition.html#ga590d7ef0d41e8499b968429da4bbe289',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgintsts_5fpxfr_5fincompisoout_5fmsk_902',['USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk',['../group___peripheral___registers___bits___definition.html#ga038bf029239a7327a134697d89adf4d2',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgintsts_5fpxfr_5fincompisoout_5fpos_903',['USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos',['../group___peripheral___registers___bits___definition.html#ga58cee872eb24af9fbf28c6e5d736f6ea',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgintsts_5frxflvl_904',['USB_OTG_GINTSTS_RXFLVL',['../group___peripheral___registers___bits___definition.html#gabd7c264becfe7a116ae20933173b1e5b',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgintsts_5frxflvl_5fmsk_905',['USB_OTG_GINTSTS_RXFLVL_Msk',['../group___peripheral___registers___bits___definition.html#ga7fb089db587ace41b14385dda34247e5',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgintsts_5frxflvl_5fpos_906',['USB_OTG_GINTSTS_RXFLVL_Pos',['../group___peripheral___registers___bits___definition.html#ga0b883fbb67ff958f65920e91e1bef891',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgintsts_5fsof_907',['USB_OTG_GINTSTS_SOF',['../group___peripheral___registers___bits___definition.html#ga478373e0aea76bfad1c9d8e93c33a2f8',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgintsts_5fsof_5fmsk_908',['USB_OTG_GINTSTS_SOF_Msk',['../group___peripheral___registers___bits___definition.html#ga574b32ff2365c138b8454bec261a44e5',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgintsts_5fsof_5fpos_909',['USB_OTG_GINTSTS_SOF_Pos',['../group___peripheral___registers___bits___definition.html#ga241c59b3b0a4716cdfeae02bee7ee6f7',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgintsts_5fsrqint_910',['USB_OTG_GINTSTS_SRQINT',['../group___peripheral___registers___bits___definition.html#gad6f152a76e8a4457cf7f2cd93a95d3fd',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgintsts_5fsrqint_5fmsk_911',['USB_OTG_GINTSTS_SRQINT_Msk',['../group___peripheral___registers___bits___definition.html#ga37cf1033876ca51d197c2652b87bd084',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgintsts_5fsrqint_5fpos_912',['USB_OTG_GINTSTS_SRQINT_Pos',['../group___peripheral___registers___bits___definition.html#ga5f3e7b8b9ed0fbb3398b29a092e775bb',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgintsts_5fusbrst_913',['USB_OTG_GINTSTS_USBRST',['../group___peripheral___registers___bits___definition.html#ga446f240725aaa8a702b70763cef41661',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgintsts_5fusbrst_5fmsk_914',['USB_OTG_GINTSTS_USBRST_Msk',['../group___peripheral___registers___bits___definition.html#ga2cc0c061635f5ac73557643af51a1441',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgintsts_5fusbrst_5fpos_915',['USB_OTG_GINTSTS_USBRST_Pos',['../group___peripheral___registers___bits___definition.html#gaf52cb564c30e26f503da97e15c1404cd',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgintsts_5fusbsusp_916',['USB_OTG_GINTSTS_USBSUSP',['../group___peripheral___registers___bits___definition.html#gadd16c90192e1c43d95c16265f86cdd5d',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgintsts_5fusbsusp_5fmsk_917',['USB_OTG_GINTSTS_USBSUSP_Msk',['../group___peripheral___registers___bits___definition.html#ga4e012bb063b871af8f27698f652d757d',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgintsts_5fusbsusp_5fpos_918',['USB_OTG_GINTSTS_USBSUSP_Pos',['../group___peripheral___registers___bits___definition.html#gae44254e287488e465ba70a9a19d1b95a',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgintsts_5fwkuint_919',['USB_OTG_GINTSTS_WKUINT',['../group___peripheral___registers___bits___definition.html#ga60bc942876444a039c20070d3a91055e',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgintsts_5fwkuint_5fmsk_920',['USB_OTG_GINTSTS_WKUINT_Msk',['../group___peripheral___registers___bits___definition.html#gaa0607db8d81e1637d4f91fbddb26bc25',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgintsts_5fwkuint_5fpos_921',['USB_OTG_GINTSTS_WKUINT_Pos',['../group___peripheral___registers___bits___definition.html#gae3a4034786904e2e3e8d6125d0e8c43d',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fglobal_5fbase_922',['USB_OTG_GLOBAL_BASE',['../group___peripheral__memory__map.html#ga044aa4388e72d9d47a03f387fb8926fb',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fglobaltypedef_923',['USB_OTG_GlobalTypeDef',['../struct_u_s_b___o_t_g___global_type_def.html',1,'']]], - ['usb_5fotg_5fgnptxsts_5fnptqxsav_924',['USB_OTG_GNPTXSTS_NPTQXSAV',['../group___peripheral___registers___bits___definition.html#ga0dbb974d940609afd19b073574c40019',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgnptxsts_5fnptqxsav_5f0_925',['USB_OTG_GNPTXSTS_NPTQXSAV_0',['../group___peripheral___registers___bits___definition.html#ga7731a3940c52add8741a9102d1d921b4',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgnptxsts_5fnptqxsav_5f1_926',['USB_OTG_GNPTXSTS_NPTQXSAV_1',['../group___peripheral___registers___bits___definition.html#gaaead027a78b6c561c4ab16a7b138373c',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgnptxsts_5fnptqxsav_5f2_927',['USB_OTG_GNPTXSTS_NPTQXSAV_2',['../group___peripheral___registers___bits___definition.html#gae0af12c08cce383a26e0eef3c6a6fa72',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgnptxsts_5fnptqxsav_5f3_928',['USB_OTG_GNPTXSTS_NPTQXSAV_3',['../group___peripheral___registers___bits___definition.html#ga896f6671b046ebcba5dde1f267508c2f',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgnptxsts_5fnptqxsav_5f4_929',['USB_OTG_GNPTXSTS_NPTQXSAV_4',['../group___peripheral___registers___bits___definition.html#ga207fc30605e39e471f9790f69e3fac74',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgnptxsts_5fnptqxsav_5f5_930',['USB_OTG_GNPTXSTS_NPTQXSAV_5',['../group___peripheral___registers___bits___definition.html#ga0d2c61ea0a8811b95ea5880adf869e0b',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgnptxsts_5fnptqxsav_5f6_931',['USB_OTG_GNPTXSTS_NPTQXSAV_6',['../group___peripheral___registers___bits___definition.html#ga787291b79ab2b19dcd87a188a8ad0c7b',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgnptxsts_5fnptqxsav_5f7_932',['USB_OTG_GNPTXSTS_NPTQXSAV_7',['../group___peripheral___registers___bits___definition.html#gac1212da7f367d7ccc3bb3db806c0293c',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgnptxsts_5fnptqxsav_5fmsk_933',['USB_OTG_GNPTXSTS_NPTQXSAV_Msk',['../group___peripheral___registers___bits___definition.html#gaca3b71a13949ca23c81dfd7901d5078e',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgnptxsts_5fnptqxsav_5fpos_934',['USB_OTG_GNPTXSTS_NPTQXSAV_Pos',['../group___peripheral___registers___bits___definition.html#ga5cc6b3fe2c33634188cb47dd7c4c79be',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgnptxsts_5fnptxfsav_935',['USB_OTG_GNPTXSTS_NPTXFSAV',['../group___peripheral___registers___bits___definition.html#ga8e0f0efb60ff9965a1ef407bb36b0c9b',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgnptxsts_5fnptxfsav_5fmsk_936',['USB_OTG_GNPTXSTS_NPTXFSAV_Msk',['../group___peripheral___registers___bits___definition.html#ga8f2d1e26e3ce0e261b8fbe6fe2797edc',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgnptxsts_5fnptxfsav_5fpos_937',['USB_OTG_GNPTXSTS_NPTXFSAV_Pos',['../group___peripheral___registers___bits___definition.html#ga39a026cf1344c10820c26d7b2c6e6d05',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgnptxsts_5fnptxqtop_938',['USB_OTG_GNPTXSTS_NPTXQTOP',['../group___peripheral___registers___bits___definition.html#ga111271d7bfdc7155f029c2402d2bac41',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgnptxsts_5fnptxqtop_5f0_939',['USB_OTG_GNPTXSTS_NPTXQTOP_0',['../group___peripheral___registers___bits___definition.html#ga6e940aac39f5922c0b7c6ffa797ce691',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgnptxsts_5fnptxqtop_5f1_940',['USB_OTG_GNPTXSTS_NPTXQTOP_1',['../group___peripheral___registers___bits___definition.html#ga4ff80fe229f3a0ca31450cf037ad3117',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgnptxsts_5fnptxqtop_5f2_941',['USB_OTG_GNPTXSTS_NPTXQTOP_2',['../group___peripheral___registers___bits___definition.html#gacb3f5554d1d052c25cba115f406d6f07',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgnptxsts_5fnptxqtop_5f3_942',['USB_OTG_GNPTXSTS_NPTXQTOP_3',['../group___peripheral___registers___bits___definition.html#gab9fd208770d7a63c0c031fed2b650d19',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgnptxsts_5fnptxqtop_5f4_943',['USB_OTG_GNPTXSTS_NPTXQTOP_4',['../group___peripheral___registers___bits___definition.html#ga963a180ae1705b5161555d23fc8f9a1e',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgnptxsts_5fnptxqtop_5f5_944',['USB_OTG_GNPTXSTS_NPTXQTOP_5',['../group___peripheral___registers___bits___definition.html#gad681db11aef73b8b65b2528f31fa9668',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgnptxsts_5fnptxqtop_5f6_945',['USB_OTG_GNPTXSTS_NPTXQTOP_6',['../group___peripheral___registers___bits___definition.html#gaba22a705c0bd9f3c18a22afcddd3edc4',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgnptxsts_5fnptxqtop_5fmsk_946',['USB_OTG_GNPTXSTS_NPTXQTOP_Msk',['../group___peripheral___registers___bits___definition.html#ga730120d7b71007fb05f5e74b8d3e6264',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgnptxsts_5fnptxqtop_5fpos_947',['USB_OTG_GNPTXSTS_NPTXQTOP_Pos',['../group___peripheral___registers___bits___definition.html#gac3fecb494258b9c4565f90696e76a599',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgotgctl_5fasvld_948',['USB_OTG_GOTGCTL_ASVLD',['../group___peripheral___registers___bits___definition.html#gafd37f8bf64b304c6e4d053849f56748c',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgotgctl_5fasvld_5fmsk_949',['USB_OTG_GOTGCTL_ASVLD_Msk',['../group___peripheral___registers___bits___definition.html#ga845bbc4c94240d4de22010b542f47ba8',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgotgctl_5fasvld_5fpos_950',['USB_OTG_GOTGCTL_ASVLD_Pos',['../group___peripheral___registers___bits___definition.html#ga61b0ea0a085b2f7608a51fdb0a842b14',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgotgctl_5fbsvld_951',['USB_OTG_GOTGCTL_BSVLD',['../group___peripheral___registers___bits___definition.html#gacc2ae24138663e92bdca36c8017b6c13',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgotgctl_5fbsvld_5fmsk_952',['USB_OTG_GOTGCTL_BSVLD_Msk',['../group___peripheral___registers___bits___definition.html#ga4110e90ebb7c55aeb8b429fb5171e378',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgotgctl_5fbsvld_5fpos_953',['USB_OTG_GOTGCTL_BSVLD_Pos',['../group___peripheral___registers___bits___definition.html#gaf05b62615285fd77bc354c072b7ba0cd',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgotgctl_5fcidsts_954',['USB_OTG_GOTGCTL_CIDSTS',['../group___peripheral___registers___bits___definition.html#gad2ab7a1464a20fd128370a41c6b2c5db',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgotgctl_5fcidsts_5fmsk_955',['USB_OTG_GOTGCTL_CIDSTS_Msk',['../group___peripheral___registers___bits___definition.html#gadcbeabffac3327cd545d469b58baf2f2',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgotgctl_5fcidsts_5fpos_956',['USB_OTG_GOTGCTL_CIDSTS_Pos',['../group___peripheral___registers___bits___definition.html#ga61f4a444a7765ed3acc31d88e20a145b',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgotgctl_5fdbct_957',['USB_OTG_GOTGCTL_DBCT',['../group___peripheral___registers___bits___definition.html#gac28cd7384fa1d08b1aa518d5d8ed622d',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgotgctl_5fdbct_5fmsk_958',['USB_OTG_GOTGCTL_DBCT_Msk',['../group___peripheral___registers___bits___definition.html#ga4cb7bd418b6f7625dd90c36be4a20008',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgotgctl_5fdbct_5fpos_959',['USB_OTG_GOTGCTL_DBCT_Pos',['../group___peripheral___registers___bits___definition.html#gada74ca38296ae390167d8d6ef705b79c',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgotgctl_5fdhnpen_960',['USB_OTG_GOTGCTL_DHNPEN',['../group___peripheral___registers___bits___definition.html#gad29b2224940ad3324855355f4fb52c51',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgotgctl_5fdhnpen_5fmsk_961',['USB_OTG_GOTGCTL_DHNPEN_Msk',['../group___peripheral___registers___bits___definition.html#gaa5c847c2f7db2b4f25a4b807847cf5fd',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgotgctl_5fdhnpen_5fpos_962',['USB_OTG_GOTGCTL_DHNPEN_Pos',['../group___peripheral___registers___bits___definition.html#gaa13365d4746a4b49753d9f4852995063',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgotgctl_5fhngscs_963',['USB_OTG_GOTGCTL_HNGSCS',['../group___peripheral___registers___bits___definition.html#ga0325825760f66d4792be59cde2a6fb36',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgotgctl_5fhngscs_5fmsk_964',['USB_OTG_GOTGCTL_HNGSCS_Msk',['../group___peripheral___registers___bits___definition.html#gaf1172acd99753812214a91f822770fad',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgotgctl_5fhngscs_5fpos_965',['USB_OTG_GOTGCTL_HNGSCS_Pos',['../group___peripheral___registers___bits___definition.html#gaa11f463747ce5e1444256f11fd57e3bc',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgotgctl_5fhnprq_966',['USB_OTG_GOTGCTL_HNPRQ',['../group___peripheral___registers___bits___definition.html#gab5db1466d8363575ab2cc8e61855b6d9',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgotgctl_5fhnprq_5fmsk_967',['USB_OTG_GOTGCTL_HNPRQ_Msk',['../group___peripheral___registers___bits___definition.html#ga00ce59b4eac11aed163f9b0a40ebd830',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgotgctl_5fhnprq_5fpos_968',['USB_OTG_GOTGCTL_HNPRQ_Pos',['../group___peripheral___registers___bits___definition.html#ga500945c12339a4e1350eaa5ca75c2767',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgotgctl_5fhshnpen_969',['USB_OTG_GOTGCTL_HSHNPEN',['../group___peripheral___registers___bits___definition.html#ga62b67d7ea4c4a3d92b031b1dc4e2d014',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgotgctl_5fhshnpen_5fmsk_970',['USB_OTG_GOTGCTL_HSHNPEN_Msk',['../group___peripheral___registers___bits___definition.html#gac02604ee9f359f998fac804332d8e82e',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgotgctl_5fhshnpen_5fpos_971',['USB_OTG_GOTGCTL_HSHNPEN_Pos',['../group___peripheral___registers___bits___definition.html#ga49a2918e796f1451a374f53af914d19e',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgotgctl_5fsrq_972',['USB_OTG_GOTGCTL_SRQ',['../group___peripheral___registers___bits___definition.html#gade39c1039ab30f1ca7ff7c33dd3e1c1b',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgotgctl_5fsrq_5fmsk_973',['USB_OTG_GOTGCTL_SRQ_Msk',['../group___peripheral___registers___bits___definition.html#ga911bbd5c9dff39b1539db5afda218133',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgotgctl_5fsrq_5fpos_974',['USB_OTG_GOTGCTL_SRQ_Pos',['../group___peripheral___registers___bits___definition.html#ga46b2b4067f78896b9de20b00d78beae7',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgotgctl_5fsrqscs_975',['USB_OTG_GOTGCTL_SRQSCS',['../group___peripheral___registers___bits___definition.html#gae09ab672e632dfd87bfb97e10563dfac',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgotgctl_5fsrqscs_5fmsk_976',['USB_OTG_GOTGCTL_SRQSCS_Msk',['../group___peripheral___registers___bits___definition.html#ga27144da12fabf5f20058022b7a060375',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgotgctl_5fsrqscs_5fpos_977',['USB_OTG_GOTGCTL_SRQSCS_Pos',['../group___peripheral___registers___bits___definition.html#gab8ebcd754d775e8f9c405194f2b2258d',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgotgint_5fadtochg_978',['USB_OTG_GOTGINT_ADTOCHG',['../group___peripheral___registers___bits___definition.html#gac73e4e50f0fbe8376e87b833872f4b40',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgotgint_5fadtochg_5fmsk_979',['USB_OTG_GOTGINT_ADTOCHG_Msk',['../group___peripheral___registers___bits___definition.html#ga6e2f3eeb46b9addf20afbc0f4e0c3196',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgotgint_5fadtochg_5fpos_980',['USB_OTG_GOTGINT_ADTOCHG_Pos',['../group___peripheral___registers___bits___definition.html#gae10eaf27601d24b1501f70242905fee9',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgotgint_5fdbcdne_981',['USB_OTG_GOTGINT_DBCDNE',['../group___peripheral___registers___bits___definition.html#gafa17e41c826fded604c1837cacae0b66',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgotgint_5fdbcdne_5fmsk_982',['USB_OTG_GOTGINT_DBCDNE_Msk',['../group___peripheral___registers___bits___definition.html#ga9e2ad3f6e96de9fbe88f1e5f6d3be7d4',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgotgint_5fdbcdne_5fpos_983',['USB_OTG_GOTGINT_DBCDNE_Pos',['../group___peripheral___registers___bits___definition.html#ga1d9e656b9e43f0959f16a86b21aef45e',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgotgint_5fhngdet_984',['USB_OTG_GOTGINT_HNGDET',['../group___peripheral___registers___bits___definition.html#gab16a656720e4914c0935ef597f9719ef',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgotgint_5fhngdet_5fmsk_985',['USB_OTG_GOTGINT_HNGDET_Msk',['../group___peripheral___registers___bits___definition.html#ga1c87ba48d57c205ce011dfa8b6888a9f',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgotgint_5fhngdet_5fpos_986',['USB_OTG_GOTGINT_HNGDET_Pos',['../group___peripheral___registers___bits___definition.html#gad417dfa3c157c52bd339c8a832017bcd',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgotgint_5fhnsschg_987',['USB_OTG_GOTGINT_HNSSCHG',['../group___peripheral___registers___bits___definition.html#ga50fcdec0f5ff7e594b726dc63175a1f3',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgotgint_5fhnsschg_5fmsk_988',['USB_OTG_GOTGINT_HNSSCHG_Msk',['../group___peripheral___registers___bits___definition.html#ga83eeecbc4aa4d8bc1c1c6cac82695577',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgotgint_5fhnsschg_5fpos_989',['USB_OTG_GOTGINT_HNSSCHG_Pos',['../group___peripheral___registers___bits___definition.html#ga747d0bf0c6cd7caaaa24b7263689b6f7',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgotgint_5fsedet_990',['USB_OTG_GOTGINT_SEDET',['../group___peripheral___registers___bits___definition.html#ga46e79a60810179da2479104fbf514a70',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgotgint_5fsedet_5fmsk_991',['USB_OTG_GOTGINT_SEDET_Msk',['../group___peripheral___registers___bits___definition.html#gaa244dfb48bb953763802745e978649b2',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgotgint_5fsedet_5fpos_992',['USB_OTG_GOTGINT_SEDET_Pos',['../group___peripheral___registers___bits___definition.html#ga7880e1cd896eb997da0931d7ec2382bd',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgotgint_5fsrsschg_993',['USB_OTG_GOTGINT_SRSSCHG',['../group___peripheral___registers___bits___definition.html#ga7c5094462de3569f89fdcc641ead7d47',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgotgint_5fsrsschg_5fmsk_994',['USB_OTG_GOTGINT_SRSSCHG_Msk',['../group___peripheral___registers___bits___definition.html#ga750e5c8cbb573197c89318c8b99771e0',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgotgint_5fsrsschg_5fpos_995',['USB_OTG_GOTGINT_SRSSCHG_Pos',['../group___peripheral___registers___bits___definition.html#ga9485401fa0f22f9eece9f372d8189343',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgrstctl_5fahbidl_996',['USB_OTG_GRSTCTL_AHBIDL',['../group___peripheral___registers___bits___definition.html#gabfc525ece665c5448d652166bf962b7a',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgrstctl_5fahbidl_5fmsk_997',['USB_OTG_GRSTCTL_AHBIDL_Msk',['../group___peripheral___registers___bits___definition.html#ga4dd9f38aa1f6dcc20c4eeb13a6547a46',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgrstctl_5fahbidl_5fpos_998',['USB_OTG_GRSTCTL_AHBIDL_Pos',['../group___peripheral___registers___bits___definition.html#ga25e845d8586bdcf102f99fde5ba85f40',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgrstctl_5fcsrst_999',['USB_OTG_GRSTCTL_CSRST',['../group___peripheral___registers___bits___definition.html#gad2e85306ee6705e7120877dee47d50b0',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgrstctl_5fcsrst_5fmsk_1000',['USB_OTG_GRSTCTL_CSRST_Msk',['../group___peripheral___registers___bits___definition.html#ga1ff29d2fa7bd837e8130717b43e71a04',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgrstctl_5fcsrst_5fpos_1001',['USB_OTG_GRSTCTL_CSRST_Pos',['../group___peripheral___registers___bits___definition.html#gae5123d9d21428692a45e351595b14954',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgrstctl_5fdmareq_1002',['USB_OTG_GRSTCTL_DMAREQ',['../group___peripheral___registers___bits___definition.html#gaf152b268977d411b34bf47e674a8239a',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgrstctl_5fdmareq_5fmsk_1003',['USB_OTG_GRSTCTL_DMAREQ_Msk',['../group___peripheral___registers___bits___definition.html#gac32cd68230279be0476ab2bafd5f8e1d',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgrstctl_5fdmareq_5fpos_1004',['USB_OTG_GRSTCTL_DMAREQ_Pos',['../group___peripheral___registers___bits___definition.html#ga8e0e58f272fdcbb69d964319b0cf58db',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgrstctl_5ffcrst_1005',['USB_OTG_GRSTCTL_FCRST',['../group___peripheral___registers___bits___definition.html#gae6417d13d2568b05676800c9eda4bdfb',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgrstctl_5ffcrst_5fmsk_1006',['USB_OTG_GRSTCTL_FCRST_Msk',['../group___peripheral___registers___bits___definition.html#ga0e8b8125ce36876edcb9041304fb0d81',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgrstctl_5ffcrst_5fpos_1007',['USB_OTG_GRSTCTL_FCRST_Pos',['../group___peripheral___registers___bits___definition.html#gace5718ced264cecb7108c689b6cf3d66',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgrstctl_5fhsrst_1008',['USB_OTG_GRSTCTL_HSRST',['../group___peripheral___registers___bits___definition.html#ga88a5f9be64498b49d12a3dc7b5bb4d0c',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgrstctl_5fhsrst_5fmsk_1009',['USB_OTG_GRSTCTL_HSRST_Msk',['../group___peripheral___registers___bits___definition.html#gaff92f8742438f99c8e81d37c63e8fbf0',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgrstctl_5fhsrst_5fpos_1010',['USB_OTG_GRSTCTL_HSRST_Pos',['../group___peripheral___registers___bits___definition.html#gab2d70beddcb07affa73404fb00c02e9d',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgrstctl_5frxfflsh_1011',['USB_OTG_GRSTCTL_RXFFLSH',['../group___peripheral___registers___bits___definition.html#gacbe28fdd671e34e48f5d96119fd91cab',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgrstctl_5frxfflsh_5fmsk_1012',['USB_OTG_GRSTCTL_RXFFLSH_Msk',['../group___peripheral___registers___bits___definition.html#ga6e6d47098a622dd1002f38438db5db6d',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgrstctl_5frxfflsh_5fpos_1013',['USB_OTG_GRSTCTL_RXFFLSH_Pos',['../group___peripheral___registers___bits___definition.html#gae4801088b836b002fe4b2c7525cf8a4a',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgrstctl_5ftxfflsh_1014',['USB_OTG_GRSTCTL_TXFFLSH',['../group___peripheral___registers___bits___definition.html#gac92d0ccd406f33733199edbee13eeb7b',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgrstctl_5ftxfflsh_5fmsk_1015',['USB_OTG_GRSTCTL_TXFFLSH_Msk',['../group___peripheral___registers___bits___definition.html#ga7a3ea77b9f0bdd2cb5e6c104d28278de',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgrstctl_5ftxfflsh_5fpos_1016',['USB_OTG_GRSTCTL_TXFFLSH_Pos',['../group___peripheral___registers___bits___definition.html#ga4a3cc0fc41e913807924741e7f197cbf',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgrstctl_5ftxfnum_1017',['USB_OTG_GRSTCTL_TXFNUM',['../group___peripheral___registers___bits___definition.html#ga1d15f7c8d94dbf1b67b6d7fda680a5ad',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgrstctl_5ftxfnum_5f0_1018',['USB_OTG_GRSTCTL_TXFNUM_0',['../group___peripheral___registers___bits___definition.html#ga30d4785ae9db0a59b8e945be32582fa3',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgrstctl_5ftxfnum_5f1_1019',['USB_OTG_GRSTCTL_TXFNUM_1',['../group___peripheral___registers___bits___definition.html#ga260a76595ceb569e47b30fc946ce7f84',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgrstctl_5ftxfnum_5f2_1020',['USB_OTG_GRSTCTL_TXFNUM_2',['../group___peripheral___registers___bits___definition.html#ga82fc2f146c00833e94244fdb640fcbd4',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgrstctl_5ftxfnum_5f3_1021',['USB_OTG_GRSTCTL_TXFNUM_3',['../group___peripheral___registers___bits___definition.html#ga625608800e950e7540f7888a281ab91e',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgrstctl_5ftxfnum_5f4_1022',['USB_OTG_GRSTCTL_TXFNUM_4',['../group___peripheral___registers___bits___definition.html#gafacdf091f563680eafdd5500809c912f',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgrstctl_5ftxfnum_5fmsk_1023',['USB_OTG_GRSTCTL_TXFNUM_Msk',['../group___peripheral___registers___bits___definition.html#ga15516a0193e467d3a42dfe24a7a20b09',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgrstctl_5ftxfnum_5fpos_1024',['USB_OTG_GRSTCTL_TXFNUM_Pos',['../group___peripheral___registers___bits___definition.html#gabaa3cd465651e6d08fa0507cffaeb1ce',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgrxfsiz_5frxfd_1025',['USB_OTG_GRXFSIZ_RXFD',['../group___peripheral___registers___bits___definition.html#ga645e153273d36f18999be31a5f9c152b',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgrxfsiz_5frxfd_5fmsk_1026',['USB_OTG_GRXFSIZ_RXFD_Msk',['../group___peripheral___registers___bits___definition.html#ga19912b7862dbda078a7c986251282051',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgrxfsiz_5frxfd_5fpos_1027',['USB_OTG_GRXFSIZ_RXFD_Pos',['../group___peripheral___registers___bits___definition.html#gac57cf2cc40ef0ecb3f7162af3bde8417',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgrxstsp_5fbcnt_1028',['USB_OTG_GRXSTSP_BCNT',['../group___peripheral___registers___bits___definition.html#gaa7cc28354cac4479286e02df84b82eaa',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgrxstsp_5fbcnt_5fmsk_1029',['USB_OTG_GRXSTSP_BCNT_Msk',['../group___peripheral___registers___bits___definition.html#gaffd3da88ae4fb7c15b79e072e2230441',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgrxstsp_5fbcnt_5fpos_1030',['USB_OTG_GRXSTSP_BCNT_Pos',['../group___peripheral___registers___bits___definition.html#gac000307f9a9c2cd3f342ea9bb1d5c53f',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgrxstsp_5fdpid_1031',['USB_OTG_GRXSTSP_DPID',['../group___peripheral___registers___bits___definition.html#ga89a85cea9c8ee8cea016f80c1354b0e2',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgrxstsp_5fdpid_5fmsk_1032',['USB_OTG_GRXSTSP_DPID_Msk',['../group___peripheral___registers___bits___definition.html#ga76f9198db9bcb93fc1823fe6278c06ad',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgrxstsp_5fdpid_5fpos_1033',['USB_OTG_GRXSTSP_DPID_Pos',['../group___peripheral___registers___bits___definition.html#ga13cf2cc9c798b4048a80c993020c4306',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgrxstsp_5fepnum_1034',['USB_OTG_GRXSTSP_EPNUM',['../group___peripheral___registers___bits___definition.html#ga09b6ae9c0db0348ae11d171912651bf2',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgrxstsp_5fepnum_5fmsk_1035',['USB_OTG_GRXSTSP_EPNUM_Msk',['../group___peripheral___registers___bits___definition.html#ga34de745d37102b0c8d8bc0daac0437a4',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgrxstsp_5fepnum_5fpos_1036',['USB_OTG_GRXSTSP_EPNUM_Pos',['../group___peripheral___registers___bits___definition.html#ga7c7c5fd797eed7457c60a0edfa2578e5',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgrxstsp_5fpktsts_1037',['USB_OTG_GRXSTSP_PKTSTS',['../group___peripheral___registers___bits___definition.html#ga968cdd119ee75647a2ab2a6beecd54fc',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgrxstsp_5fpktsts_5fmsk_1038',['USB_OTG_GRXSTSP_PKTSTS_Msk',['../group___peripheral___registers___bits___definition.html#ga02d6c9af341038ba6622a9ac14e0aeda',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgrxstsp_5fpktsts_5fpos_1039',['USB_OTG_GRXSTSP_PKTSTS_Pos',['../group___peripheral___registers___bits___definition.html#ga27644858023a064bac6755fcdff30ab9',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgusbcfg_5fctxpkt_1040',['USB_OTG_GUSBCFG_CTXPKT',['../group___peripheral___registers___bits___definition.html#ga0efb62f80533abcf9cecd96815200380',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgusbcfg_5fctxpkt_5fmsk_1041',['USB_OTG_GUSBCFG_CTXPKT_Msk',['../group___peripheral___registers___bits___definition.html#ga90ac2f68e29f0584ba980f3d396eb1e2',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgusbcfg_5fctxpkt_5fpos_1042',['USB_OTG_GUSBCFG_CTXPKT_Pos',['../group___peripheral___registers___bits___definition.html#ga58fa0446165b4a2d5dbb3998ca3c8030',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgusbcfg_5ffdmod_1043',['USB_OTG_GUSBCFG_FDMOD',['../group___peripheral___registers___bits___definition.html#ga012379ec9a2c86e7d28f5dc882fed0c5',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgusbcfg_5ffdmod_5fmsk_1044',['USB_OTG_GUSBCFG_FDMOD_Msk',['../group___peripheral___registers___bits___definition.html#ga93cc2f6447eb4b2e36588e604b66d2b8',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgusbcfg_5ffdmod_5fpos_1045',['USB_OTG_GUSBCFG_FDMOD_Pos',['../group___peripheral___registers___bits___definition.html#gaaa1338a2855521cf8b23de215e0a24d4',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgusbcfg_5ffhmod_1046',['USB_OTG_GUSBCFG_FHMOD',['../group___peripheral___registers___bits___definition.html#gac2bafa204b663017c8c08dcd42c1c031',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgusbcfg_5ffhmod_5fmsk_1047',['USB_OTG_GUSBCFG_FHMOD_Msk',['../group___peripheral___registers___bits___definition.html#ga8b9aae8e1a49ed8a7d8b3d8a779581a3',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgusbcfg_5ffhmod_5fpos_1048',['USB_OTG_GUSBCFG_FHMOD_Pos',['../group___peripheral___registers___bits___definition.html#ga78d129fd19d35e210ec7dcf9e50dfd07',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgusbcfg_5fhnpcap_1049',['USB_OTG_GUSBCFG_HNPCAP',['../group___peripheral___registers___bits___definition.html#ga6e220d23f5739e07442461204a70a2c7',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgusbcfg_5fhnpcap_5fmsk_1050',['USB_OTG_GUSBCFG_HNPCAP_Msk',['../group___peripheral___registers___bits___definition.html#ga014d25d1f767f3db5ad0c60e7c752607',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgusbcfg_5fhnpcap_5fpos_1051',['USB_OTG_GUSBCFG_HNPCAP_Pos',['../group___peripheral___registers___bits___definition.html#ga6f1e032b4bf712c5f02f8fcbf6493f9c',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgusbcfg_5fpcci_1052',['USB_OTG_GUSBCFG_PCCI',['../group___peripheral___registers___bits___definition.html#gae325703f616d90c6c22198c288fa4f28',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgusbcfg_5fpcci_5fmsk_1053',['USB_OTG_GUSBCFG_PCCI_Msk',['../group___peripheral___registers___bits___definition.html#ga013f30e987d548455287896e9f5600a6',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgusbcfg_5fpcci_5fpos_1054',['USB_OTG_GUSBCFG_PCCI_Pos',['../group___peripheral___registers___bits___definition.html#ga68a28d51da909433ba4244ba2a5e42d8',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgusbcfg_5fphylpcs_1055',['USB_OTG_GUSBCFG_PHYLPCS',['../group___peripheral___registers___bits___definition.html#ga87e134cc67f7b77efcb1506f7ca57b64',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgusbcfg_5fphylpcs_5fmsk_1056',['USB_OTG_GUSBCFG_PHYLPCS_Msk',['../group___peripheral___registers___bits___definition.html#ga754ace191e8556620eec7c93ba53a914',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgusbcfg_5fphylpcs_5fpos_1057',['USB_OTG_GUSBCFG_PHYLPCS_Pos',['../group___peripheral___registers___bits___definition.html#gac9374168e3afcc350fa7645900bec121',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgusbcfg_5fphysel_1058',['USB_OTG_GUSBCFG_PHYSEL',['../group___peripheral___registers___bits___definition.html#ga2148059ec3e6a804d102ed9964c9a005',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgusbcfg_5fphysel_5fmsk_1059',['USB_OTG_GUSBCFG_PHYSEL_Msk',['../group___peripheral___registers___bits___definition.html#ga3373712099429d9b7186af1f2bf1e662',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgusbcfg_5fphysel_5fpos_1060',['USB_OTG_GUSBCFG_PHYSEL_Pos',['../group___peripheral___registers___bits___definition.html#ga55cc06db9db1914662fbcf8ad9de06b8',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgusbcfg_5fptci_1061',['USB_OTG_GUSBCFG_PTCI',['../group___peripheral___registers___bits___definition.html#ga55174040ef4566af2326b0a424bff30a',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgusbcfg_5fptci_5fmsk_1062',['USB_OTG_GUSBCFG_PTCI_Msk',['../group___peripheral___registers___bits___definition.html#gab89a6d18ebdbf9a78551b167eedf7c2f',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgusbcfg_5fptci_5fpos_1063',['USB_OTG_GUSBCFG_PTCI_Pos',['../group___peripheral___registers___bits___definition.html#gaa08ed9b2e729e9b8ff29283ed8fadb84',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgusbcfg_5fsrpcap_1064',['USB_OTG_GUSBCFG_SRPCAP',['../group___peripheral___registers___bits___definition.html#ga26cadf8d7d278615a2681c308d69a1f4',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgusbcfg_5fsrpcap_5fmsk_1065',['USB_OTG_GUSBCFG_SRPCAP_Msk',['../group___peripheral___registers___bits___definition.html#gaffdc662f62192d4b3b04c2967dc17499',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgusbcfg_5fsrpcap_5fpos_1066',['USB_OTG_GUSBCFG_SRPCAP_Pos',['../group___peripheral___registers___bits___definition.html#ga24275f2398ac98c01acd951a7a03d3dc',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgusbcfg_5ftocal_1067',['USB_OTG_GUSBCFG_TOCAL',['../group___peripheral___registers___bits___definition.html#gadb035573c48f1055126d94a3c15dd5f3',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgusbcfg_5ftocal_5f0_1068',['USB_OTG_GUSBCFG_TOCAL_0',['../group___peripheral___registers___bits___definition.html#gaa9afeebc0fdfffa134586228627d0994',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgusbcfg_5ftocal_5f1_1069',['USB_OTG_GUSBCFG_TOCAL_1',['../group___peripheral___registers___bits___definition.html#gad406f5ebd83521f075d973f1afae39f8',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgusbcfg_5ftocal_5f2_1070',['USB_OTG_GUSBCFG_TOCAL_2',['../group___peripheral___registers___bits___definition.html#ga5c336a75d6e5035c376667f9794d9aae',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgusbcfg_5ftocal_5fmsk_1071',['USB_OTG_GUSBCFG_TOCAL_Msk',['../group___peripheral___registers___bits___definition.html#gaa03324441e7f1d314a3d553097a97d98',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgusbcfg_5ftocal_5fpos_1072',['USB_OTG_GUSBCFG_TOCAL_Pos',['../group___peripheral___registers___bits___definition.html#ga652452baf3a68648d58eda39f8b95b17',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgusbcfg_5ftrdt_1073',['USB_OTG_GUSBCFG_TRDT',['../group___peripheral___registers___bits___definition.html#gaedf4c990f79714f2747232ccb7470d4c',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgusbcfg_5ftrdt_5f0_1074',['USB_OTG_GUSBCFG_TRDT_0',['../group___peripheral___registers___bits___definition.html#ga09f21fcd7d2ba96955088e33afa034e5',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgusbcfg_5ftrdt_5f1_1075',['USB_OTG_GUSBCFG_TRDT_1',['../group___peripheral___registers___bits___definition.html#gad316e69d3679d7fa0a73caf577e1d2b8',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgusbcfg_5ftrdt_5f2_1076',['USB_OTG_GUSBCFG_TRDT_2',['../group___peripheral___registers___bits___definition.html#gad8ecdc45ec0654c353bee6da6d17a9a6',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgusbcfg_5ftrdt_5f3_1077',['USB_OTG_GUSBCFG_TRDT_3',['../group___peripheral___registers___bits___definition.html#ga019e347f4b9b5a2bf980b90e921c23f0',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgusbcfg_5ftrdt_5fmsk_1078',['USB_OTG_GUSBCFG_TRDT_Msk',['../group___peripheral___registers___bits___definition.html#gaec02000199e190ce726adc091bd9fc18',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgusbcfg_5ftrdt_5fpos_1079',['USB_OTG_GUSBCFG_TRDT_Pos',['../group___peripheral___registers___bits___definition.html#ga5bb11f994508c0f3582a561c67784df2',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgusbcfg_5ftsdps_1080',['USB_OTG_GUSBCFG_TSDPS',['../group___peripheral___registers___bits___definition.html#gabe1cdbe63bf7a5b2212e602f88a16796',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgusbcfg_5ftsdps_5fmsk_1081',['USB_OTG_GUSBCFG_TSDPS_Msk',['../group___peripheral___registers___bits___definition.html#gac4f3f8f8230c13d226cfc088d2ef2f5b',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgusbcfg_5ftsdps_5fpos_1082',['USB_OTG_GUSBCFG_TSDPS_Pos',['../group___peripheral___registers___bits___definition.html#ga72a8efdaa2432c74a2e7e81a79ee96b0',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgusbcfg_5fulpiar_1083',['USB_OTG_GUSBCFG_ULPIAR',['../group___peripheral___registers___bits___definition.html#ga9996da3f96fd45ce80d12a1db533b89d',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgusbcfg_5fulpiar_5fmsk_1084',['USB_OTG_GUSBCFG_ULPIAR_Msk',['../group___peripheral___registers___bits___definition.html#ga2787eb50165fdc318425a15808e195d7',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgusbcfg_5fulpiar_5fpos_1085',['USB_OTG_GUSBCFG_ULPIAR_Pos',['../group___peripheral___registers___bits___definition.html#ga3d99b3198a804e57d5b103de896cbae1',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgusbcfg_5fulpicsm_1086',['USB_OTG_GUSBCFG_ULPICSM',['../group___peripheral___registers___bits___definition.html#gae7f25e19a542791bcb97956262637e9b',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgusbcfg_5fulpicsm_5fmsk_1087',['USB_OTG_GUSBCFG_ULPICSM_Msk',['../group___peripheral___registers___bits___definition.html#gacb75fefda7133445f8372502ee6dc415',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgusbcfg_5fulpicsm_5fpos_1088',['USB_OTG_GUSBCFG_ULPICSM_Pos',['../group___peripheral___registers___bits___definition.html#ga8c0898ecb1e370e25eda1e7b4296f497',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgusbcfg_5fulpievbusd_1089',['USB_OTG_GUSBCFG_ULPIEVBUSD',['../group___peripheral___registers___bits___definition.html#gafad0b734f8f4511d7839385a01f105b6',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgusbcfg_5fulpievbusd_5fmsk_1090',['USB_OTG_GUSBCFG_ULPIEVBUSD_Msk',['../group___peripheral___registers___bits___definition.html#ga51f99055d4e1309feeba94e88c767f03',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgusbcfg_5fulpievbusd_5fpos_1091',['USB_OTG_GUSBCFG_ULPIEVBUSD_Pos',['../group___peripheral___registers___bits___definition.html#ga971bd3927ed8382dc26b7031f44140ab',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgusbcfg_5fulpievbusi_1092',['USB_OTG_GUSBCFG_ULPIEVBUSI',['../group___peripheral___registers___bits___definition.html#ga3a57c032717ceeeef110b7fd33cddd79',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgusbcfg_5fulpievbusi_5fmsk_1093',['USB_OTG_GUSBCFG_ULPIEVBUSI_Msk',['../group___peripheral___registers___bits___definition.html#ga04c1b32f50469cd6f5b5728b85af1ad0',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgusbcfg_5fulpievbusi_5fpos_1094',['USB_OTG_GUSBCFG_ULPIEVBUSI_Pos',['../group___peripheral___registers___bits___definition.html#gad3c02da8d9118f5fb97e6ba78fd4d04f',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgusbcfg_5fulpifsls_1095',['USB_OTG_GUSBCFG_ULPIFSLS',['../group___peripheral___registers___bits___definition.html#ga9ad0a14d1e0b69f72209ac0de8290862',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgusbcfg_5fulpifsls_5fmsk_1096',['USB_OTG_GUSBCFG_ULPIFSLS_Msk',['../group___peripheral___registers___bits___definition.html#gaff2a24486b52bc1e86707e5e4f9ebbd9',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgusbcfg_5fulpifsls_5fpos_1097',['USB_OTG_GUSBCFG_ULPIFSLS_Pos',['../group___peripheral___registers___bits___definition.html#ga1cf18014a20add68d69f8cceb62e012e',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgusbcfg_5fulpiipd_1098',['USB_OTG_GUSBCFG_ULPIIPD',['../group___peripheral___registers___bits___definition.html#ga240a106dc942384f0c0dae11a7efc018',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgusbcfg_5fulpiipd_5fmsk_1099',['USB_OTG_GUSBCFG_ULPIIPD_Msk',['../group___peripheral___registers___bits___definition.html#ga3c2349edc84b6a82c2e350ae60c3c49b',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fgusbcfg_5fulpiipd_5fpos_1100',['USB_OTG_GUSBCFG_ULPIIPD_Pos',['../group___peripheral___registers___bits___definition.html#ga8a20078b3fc4f5aad413fe73b96c7ed3',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhaint_5fhaint_1101',['USB_OTG_HAINT_HAINT',['../group___peripheral___registers___bits___definition.html#ga13f6ce630f54df1a49314012a612d98d',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhaint_5fhaint_5fmsk_1102',['USB_OTG_HAINT_HAINT_Msk',['../group___peripheral___registers___bits___definition.html#ga6d40f68bf4ce28cec78ad449152f16e2',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhaint_5fhaint_5fpos_1103',['USB_OTG_HAINT_HAINT_Pos',['../group___peripheral___registers___bits___definition.html#gabb914e0dfd6e2f21aa41ce6e2ac289bf',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhaintmsk_5fhaintm_1104',['USB_OTG_HAINTMSK_HAINTM',['../group___peripheral___registers___bits___definition.html#gac1f2419baf94819340bd759b09004121',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhaintmsk_5fhaintm_5fmsk_1105',['USB_OTG_HAINTMSK_HAINTM_Msk',['../group___peripheral___registers___bits___definition.html#ga326da6d7c5280028f57cf69bc5958b4a',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhaintmsk_5fhaintm_5fpos_1106',['USB_OTG_HAINTMSK_HAINTM_Pos',['../group___peripheral___registers___bits___definition.html#gaa567788f5117a97c9ac2f72065e49365',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhcchar_5fchdis_1107',['USB_OTG_HCCHAR_CHDIS',['../group___peripheral___registers___bits___definition.html#ga39de05e23016253698aa5348fffdf8a2',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhcchar_5fchdis_5fmsk_1108',['USB_OTG_HCCHAR_CHDIS_Msk',['../group___peripheral___registers___bits___definition.html#ga917118333ba8be9747a356d0a27e71ae',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhcchar_5fchdis_5fpos_1109',['USB_OTG_HCCHAR_CHDIS_Pos',['../group___peripheral___registers___bits___definition.html#ga74f85c58e9d1ba64d4bdb8f049cd11e2',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhcchar_5fchena_1110',['USB_OTG_HCCHAR_CHENA',['../group___peripheral___registers___bits___definition.html#ga1e7dc29241b644b8bcce53440658c93f',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhcchar_5fchena_5fmsk_1111',['USB_OTG_HCCHAR_CHENA_Msk',['../group___peripheral___registers___bits___definition.html#gacfdd5a74cad64a4655be2486fce7230b',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhcchar_5fchena_5fpos_1112',['USB_OTG_HCCHAR_CHENA_Pos',['../group___peripheral___registers___bits___definition.html#gaee61eaf9a8783c6a440b7835074818e5',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhcchar_5fdad_1113',['USB_OTG_HCCHAR_DAD',['../group___peripheral___registers___bits___definition.html#gad1ef60bbb223f7605a2b58d99b0c1734',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhcchar_5fdad_5f0_1114',['USB_OTG_HCCHAR_DAD_0',['../group___peripheral___registers___bits___definition.html#gae3fd299a559b62badc881da2a5372ebc',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhcchar_5fdad_5f1_1115',['USB_OTG_HCCHAR_DAD_1',['../group___peripheral___registers___bits___definition.html#ga172f14d42d36a6782891fc2bb8069258',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhcchar_5fdad_5f2_1116',['USB_OTG_HCCHAR_DAD_2',['../group___peripheral___registers___bits___definition.html#ga6dc7e9e1a9dee8376aaa948b7caf6f8e',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhcchar_5fdad_5f3_1117',['USB_OTG_HCCHAR_DAD_3',['../group___peripheral___registers___bits___definition.html#ga9209069e0fc607042c54ef7394aa6b61',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhcchar_5fdad_5f4_1118',['USB_OTG_HCCHAR_DAD_4',['../group___peripheral___registers___bits___definition.html#ga835ff39312f6b7b6b8610cdf0dcd3b99',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhcchar_5fdad_5f5_1119',['USB_OTG_HCCHAR_DAD_5',['../group___peripheral___registers___bits___definition.html#ga79ad8aecc4f86e9d3446691c747a48da',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhcchar_5fdad_5f6_1120',['USB_OTG_HCCHAR_DAD_6',['../group___peripheral___registers___bits___definition.html#gad0063e054d76ae8962838b7bf9d14ef2',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhcchar_5fdad_5fmsk_1121',['USB_OTG_HCCHAR_DAD_Msk',['../group___peripheral___registers___bits___definition.html#ga08d35b165b6c8ca666c72993bee4a098',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhcchar_5fdad_5fpos_1122',['USB_OTG_HCCHAR_DAD_Pos',['../group___peripheral___registers___bits___definition.html#gafeea28ea8c54145ee049e740da932291',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhcchar_5fepdir_1123',['USB_OTG_HCCHAR_EPDIR',['../group___peripheral___registers___bits___definition.html#ga303898c1943aede8d1ed6b9f259b9d0c',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhcchar_5fepdir_5fmsk_1124',['USB_OTG_HCCHAR_EPDIR_Msk',['../group___peripheral___registers___bits___definition.html#ga93cab809dbd5a48454d9370b5cc83571',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhcchar_5fepdir_5fpos_1125',['USB_OTG_HCCHAR_EPDIR_Pos',['../group___peripheral___registers___bits___definition.html#gacdd23192fd35d666bd97f831304d45d2',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhcchar_5fepnum_1126',['USB_OTG_HCCHAR_EPNUM',['../group___peripheral___registers___bits___definition.html#gae0ac25b2f10b80c3f529c97f225be728',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhcchar_5fepnum_5f0_1127',['USB_OTG_HCCHAR_EPNUM_0',['../group___peripheral___registers___bits___definition.html#ga8fa97e03ed82c3f48b7b8ceb38db62bf',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhcchar_5fepnum_5f1_1128',['USB_OTG_HCCHAR_EPNUM_1',['../group___peripheral___registers___bits___definition.html#gac3898f15c5f3db168ab867f1dbfc8d3b',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhcchar_5fepnum_5f2_1129',['USB_OTG_HCCHAR_EPNUM_2',['../group___peripheral___registers___bits___definition.html#gaeb6e82877f06b262cc0ec2143821ebf3',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhcchar_5fepnum_5f3_1130',['USB_OTG_HCCHAR_EPNUM_3',['../group___peripheral___registers___bits___definition.html#gab3977b57bb81f942fcdde8f4d5e9fe24',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhcchar_5fepnum_5fmsk_1131',['USB_OTG_HCCHAR_EPNUM_Msk',['../group___peripheral___registers___bits___definition.html#ga7341e59397aba116872d63a3606d0cb6',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhcchar_5fepnum_5fpos_1132',['USB_OTG_HCCHAR_EPNUM_Pos',['../group___peripheral___registers___bits___definition.html#gabb71f23c0ec214d2ffc8d8bc81aa2ab2',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhcchar_5feptyp_1133',['USB_OTG_HCCHAR_EPTYP',['../group___peripheral___registers___bits___definition.html#ga1dcca7cc02f8f9f2adf14fdd36b36055',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhcchar_5feptyp_5f0_1134',['USB_OTG_HCCHAR_EPTYP_0',['../group___peripheral___registers___bits___definition.html#ga1a360a7769f0c9ec5a44bdf11b0787b5',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhcchar_5feptyp_5f1_1135',['USB_OTG_HCCHAR_EPTYP_1',['../group___peripheral___registers___bits___definition.html#ga88b483febece6e61c20347d02dd98b8e',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhcchar_5feptyp_5fmsk_1136',['USB_OTG_HCCHAR_EPTYP_Msk',['../group___peripheral___registers___bits___definition.html#ga108a8e59d323596cb35aae675e3422eb',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhcchar_5feptyp_5fpos_1137',['USB_OTG_HCCHAR_EPTYP_Pos',['../group___peripheral___registers___bits___definition.html#ga13ea0363e5157b965e6a96756bc1068d',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhcchar_5flsdev_1138',['USB_OTG_HCCHAR_LSDEV',['../group___peripheral___registers___bits___definition.html#ga20e48f56546fe73be76efe518c239114',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhcchar_5flsdev_5fmsk_1139',['USB_OTG_HCCHAR_LSDEV_Msk',['../group___peripheral___registers___bits___definition.html#gaf3a41d259407f924e05803713ee882b5',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhcchar_5flsdev_5fpos_1140',['USB_OTG_HCCHAR_LSDEV_Pos',['../group___peripheral___registers___bits___definition.html#ga20cb6423ef24ca58ed85c86a008849fc',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhcchar_5fmc_1141',['USB_OTG_HCCHAR_MC',['../group___peripheral___registers___bits___definition.html#ga373dce758b81f5555b484092be97f4f7',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhcchar_5fmc_5f0_1142',['USB_OTG_HCCHAR_MC_0',['../group___peripheral___registers___bits___definition.html#ga0f3c212ab7781f5f354c8081d4ef1a60',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhcchar_5fmc_5f1_1143',['USB_OTG_HCCHAR_MC_1',['../group___peripheral___registers___bits___definition.html#gad5ecb48ef55ed2a5c7cf5f4ab6f0fac9',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhcchar_5fmc_5fmsk_1144',['USB_OTG_HCCHAR_MC_Msk',['../group___peripheral___registers___bits___definition.html#gab76a960e55c3396d2d3ef9b790ff9d44',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhcchar_5fmc_5fpos_1145',['USB_OTG_HCCHAR_MC_Pos',['../group___peripheral___registers___bits___definition.html#ga18e4b603f645b249c583dfe4f04f2518',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhcchar_5fmpsiz_1146',['USB_OTG_HCCHAR_MPSIZ',['../group___peripheral___registers___bits___definition.html#gaf7d25c42363f797cf4c2c308006de784',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhcchar_5fmpsiz_5fmsk_1147',['USB_OTG_HCCHAR_MPSIZ_Msk',['../group___peripheral___registers___bits___definition.html#gaacaf54f4394f57b2eea234e1aeb4bb43',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhcchar_5fmpsiz_5fpos_1148',['USB_OTG_HCCHAR_MPSIZ_Pos',['../group___peripheral___registers___bits___definition.html#gaca874060952d9d5d5a31d3ce095d0358',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhcchar_5foddfrm_1149',['USB_OTG_HCCHAR_ODDFRM',['../group___peripheral___registers___bits___definition.html#gad866d817dedea4edb9514815ab3f5ae6',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhcchar_5foddfrm_5fmsk_1150',['USB_OTG_HCCHAR_ODDFRM_Msk',['../group___peripheral___registers___bits___definition.html#gaf3b86db5b44b232005a73d7c660ee326',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhcchar_5foddfrm_5fpos_1151',['USB_OTG_HCCHAR_ODDFRM_Pos',['../group___peripheral___registers___bits___definition.html#ga2b18ec4af69c872fde54266c33774b51',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhcdma_5fdmaaddr_1152',['USB_OTG_HCDMA_DMAADDR',['../group___peripheral___registers___bits___definition.html#gab2980c7f7c60bf5ff4842dc9e363ea7b',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhcdma_5fdmaaddr_5fmsk_1153',['USB_OTG_HCDMA_DMAADDR_Msk',['../group___peripheral___registers___bits___definition.html#ga2a98df839cd4108ef0b1b814d0f7020b',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhcdma_5fdmaaddr_5fpos_1154',['USB_OTG_HCDMA_DMAADDR_Pos',['../group___peripheral___registers___bits___definition.html#ga3c69fd9913335fdca15a7dc32d1193cc',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhcfg_5ffslspcs_1155',['USB_OTG_HCFG_FSLSPCS',['../group___peripheral___registers___bits___definition.html#ga8a881de3c707878018490b8b3db282f7',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhcfg_5ffslspcs_5f0_1156',['USB_OTG_HCFG_FSLSPCS_0',['../group___peripheral___registers___bits___definition.html#gad229aff8e0584e5b5abbf80629e141cc',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhcfg_5ffslspcs_5f1_1157',['USB_OTG_HCFG_FSLSPCS_1',['../group___peripheral___registers___bits___definition.html#ga981001cbade2d922b72e1b06d6069da0',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhcfg_5ffslspcs_5fmsk_1158',['USB_OTG_HCFG_FSLSPCS_Msk',['../group___peripheral___registers___bits___definition.html#gaad2eed76dce0ee687f52e08f16bc4c1b',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhcfg_5ffslspcs_5fpos_1159',['USB_OTG_HCFG_FSLSPCS_Pos',['../group___peripheral___registers___bits___definition.html#ga473714ba284e49803fdf522f88151914',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhcfg_5ffslss_1160',['USB_OTG_HCFG_FSLSS',['../group___peripheral___registers___bits___definition.html#ga98190493ea5b039322c77341e3cf61f8',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhcfg_5ffslss_5fmsk_1161',['USB_OTG_HCFG_FSLSS_Msk',['../group___peripheral___registers___bits___definition.html#gaebb27b8d77f15f8100c1d27149fb7186',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhcfg_5ffslss_5fpos_1162',['USB_OTG_HCFG_FSLSS_Pos',['../group___peripheral___registers___bits___definition.html#gab662285d2cc3bfd61c664e572fb69f5e',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhcint_5fack_1163',['USB_OTG_HCINT_ACK',['../group___peripheral___registers___bits___definition.html#ga7bdbdb2fe8526b144ca06b537c5acdd0',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhcint_5fack_5fmsk_1164',['USB_OTG_HCINT_ACK_Msk',['../group___peripheral___registers___bits___definition.html#ga9ab325ca96f65ccaea0b7abb66b33702',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhcint_5fack_5fpos_1165',['USB_OTG_HCINT_ACK_Pos',['../group___peripheral___registers___bits___definition.html#ga24055327fbeb5884d6df6de0657ae195',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhcint_5fahberr_1166',['USB_OTG_HCINT_AHBERR',['../group___peripheral___registers___bits___definition.html#gae8b909ca659271857d9f3fcc817d8a4a',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhcint_5fahberr_5fmsk_1167',['USB_OTG_HCINT_AHBERR_Msk',['../group___peripheral___registers___bits___definition.html#gaab7250908e6d8ad8ab40adccafdae4f9',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhcint_5fahberr_5fpos_1168',['USB_OTG_HCINT_AHBERR_Pos',['../group___peripheral___registers___bits___definition.html#ga2a20fc8de6dd01708697f76f73b9844b',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhcint_5fbberr_1169',['USB_OTG_HCINT_BBERR',['../group___peripheral___registers___bits___definition.html#gaa3b7e21abc4b3e5ea1eff06eb0850441',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhcint_5fbberr_5fmsk_1170',['USB_OTG_HCINT_BBERR_Msk',['../group___peripheral___registers___bits___definition.html#ga71fa9e120a3bfed31484cfd157f11fbc',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhcint_5fbberr_5fpos_1171',['USB_OTG_HCINT_BBERR_Pos',['../group___peripheral___registers___bits___definition.html#gaace090462b379413a409acffad4d33ca',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhcint_5fchh_1172',['USB_OTG_HCINT_CHH',['../group___peripheral___registers___bits___definition.html#gaf4ecd695c1cc06335445a49780888bb1',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhcint_5fchh_5fmsk_1173',['USB_OTG_HCINT_CHH_Msk',['../group___peripheral___registers___bits___definition.html#ga177761d89d797f8d6194e6618792be8d',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhcint_5fchh_5fpos_1174',['USB_OTG_HCINT_CHH_Pos',['../group___peripheral___registers___bits___definition.html#ga356d30f2a7cbe9b63ac9dd149c872bd7',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhcint_5fdterr_1175',['USB_OTG_HCINT_DTERR',['../group___peripheral___registers___bits___definition.html#ga0089841c8301b5e572e29da28ef95467',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhcint_5fdterr_5fmsk_1176',['USB_OTG_HCINT_DTERR_Msk',['../group___peripheral___registers___bits___definition.html#gac35a8a3f2a57b8881cb825c07f263570',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhcint_5fdterr_5fpos_1177',['USB_OTG_HCINT_DTERR_Pos',['../group___peripheral___registers___bits___definition.html#ga69cbb7f274c4d4f82666599af8dd5428',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhcint_5ffrmor_1178',['USB_OTG_HCINT_FRMOR',['../group___peripheral___registers___bits___definition.html#gad7805a112e2897572bffee4c25042cc9',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhcint_5ffrmor_5fmsk_1179',['USB_OTG_HCINT_FRMOR_Msk',['../group___peripheral___registers___bits___definition.html#gaa98c0c3233732702f627741e818b08ae',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhcint_5ffrmor_5fpos_1180',['USB_OTG_HCINT_FRMOR_Pos',['../group___peripheral___registers___bits___definition.html#gab72d52c361d7fc77fcca26897e5a1bd9',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhcint_5fnak_1181',['USB_OTG_HCINT_NAK',['../group___peripheral___registers___bits___definition.html#ga069dfb657cf84125520ec5e4f20b8da0',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhcint_5fnak_5fmsk_1182',['USB_OTG_HCINT_NAK_Msk',['../group___peripheral___registers___bits___definition.html#ga62c4fd21ba532f275b90104da9c69825',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhcint_5fnak_5fpos_1183',['USB_OTG_HCINT_NAK_Pos',['../group___peripheral___registers___bits___definition.html#gad31cbff32e8f912b9dd70fa421465fab',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhcint_5fnyet_1184',['USB_OTG_HCINT_NYET',['../group___peripheral___registers___bits___definition.html#ga0f54751dc8abdbd65c786d2736cc2038',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhcint_5fnyet_5fmsk_1185',['USB_OTG_HCINT_NYET_Msk',['../group___peripheral___registers___bits___definition.html#ga516eea514a6024132cc66218882582dd',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhcint_5fnyet_5fpos_1186',['USB_OTG_HCINT_NYET_Pos',['../group___peripheral___registers___bits___definition.html#ga4c596c2aae4b88e04a122a9af560730e',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhcint_5fstall_1187',['USB_OTG_HCINT_STALL',['../group___peripheral___registers___bits___definition.html#gabe1d65156f846dcecac479a451b5109e',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhcint_5fstall_5fmsk_1188',['USB_OTG_HCINT_STALL_Msk',['../group___peripheral___registers___bits___definition.html#gadd9b71968e54876f10fca2af973a95fb',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhcint_5fstall_5fpos_1189',['USB_OTG_HCINT_STALL_Pos',['../group___peripheral___registers___bits___definition.html#ga4d9beff066b9b48480c25194af3004aa',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhcint_5ftxerr_1190',['USB_OTG_HCINT_TXERR',['../group___peripheral___registers___bits___definition.html#ga7e34974081aceef1865b83e47d48d158',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhcint_5ftxerr_5fmsk_1191',['USB_OTG_HCINT_TXERR_Msk',['../group___peripheral___registers___bits___definition.html#ga158802078f5364292b4b93103aef6b1f',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhcint_5ftxerr_5fpos_1192',['USB_OTG_HCINT_TXERR_Pos',['../group___peripheral___registers___bits___definition.html#ga7cf2523fa4c59105d01a17d4caac3cbf',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhcint_5fxfrc_1193',['USB_OTG_HCINT_XFRC',['../group___peripheral___registers___bits___definition.html#ga332b761dd88ddfacac9ebff6fced8846',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhcint_5fxfrc_5fmsk_1194',['USB_OTG_HCINT_XFRC_Msk',['../group___peripheral___registers___bits___definition.html#gae073b77821aa500ba31c336cc510a2dd',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhcint_5fxfrc_5fpos_1195',['USB_OTG_HCINT_XFRC_Pos',['../group___peripheral___registers___bits___definition.html#ga56016189953a9cbb4085baf96bb4d6c8',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhcintmsk_5fackm_1196',['USB_OTG_HCINTMSK_ACKM',['../group___peripheral___registers___bits___definition.html#ga21eb5c0fa8aafa12a725ab52f85023d1',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhcintmsk_5fackm_5fmsk_1197',['USB_OTG_HCINTMSK_ACKM_Msk',['../group___peripheral___registers___bits___definition.html#ga372e5e68431087f0fb3b25408ce9eec9',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhcintmsk_5fackm_5fpos_1198',['USB_OTG_HCINTMSK_ACKM_Pos',['../group___peripheral___registers___bits___definition.html#ga67b66f3e3480ac1542b1a1f4ce8d0970',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhcintmsk_5fahberr_1199',['USB_OTG_HCINTMSK_AHBERR',['../group___peripheral___registers___bits___definition.html#gaf281bb6b61c559e8b068ab32114572af',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhcintmsk_5fahberr_5fmsk_1200',['USB_OTG_HCINTMSK_AHBERR_Msk',['../group___peripheral___registers___bits___definition.html#ga70c101e1a4e376d61f77fcf4f5f32bf6',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhcintmsk_5fahberr_5fpos_1201',['USB_OTG_HCINTMSK_AHBERR_Pos',['../group___peripheral___registers___bits___definition.html#ga0d753e4c1acd73bd24b7e4d07405d94a',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhcintmsk_5fbberrm_1202',['USB_OTG_HCINTMSK_BBERRM',['../group___peripheral___registers___bits___definition.html#ga9ae263bd38eec1c423b0a70904b5099a',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhcintmsk_5fbberrm_5fmsk_1203',['USB_OTG_HCINTMSK_BBERRM_Msk',['../group___peripheral___registers___bits___definition.html#ga2f9165c1fbf87679bb83efa46571b96c',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhcintmsk_5fbberrm_5fpos_1204',['USB_OTG_HCINTMSK_BBERRM_Pos',['../group___peripheral___registers___bits___definition.html#gabadb45319c35046abce6475a1105a3d6',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhcintmsk_5fchhm_1205',['USB_OTG_HCINTMSK_CHHM',['../group___peripheral___registers___bits___definition.html#ga8f359b89c79fba4414e0838645f13a6b',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhcintmsk_5fchhm_5fmsk_1206',['USB_OTG_HCINTMSK_CHHM_Msk',['../group___peripheral___registers___bits___definition.html#gaa6cb390f8f0cf8a561f41a88a8339d7e',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhcintmsk_5fchhm_5fpos_1207',['USB_OTG_HCINTMSK_CHHM_Pos',['../group___peripheral___registers___bits___definition.html#ga5a9e51a34d9b5145d7c4d92a342ffb9c',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhcintmsk_5fdterrm_1208',['USB_OTG_HCINTMSK_DTERRM',['../group___peripheral___registers___bits___definition.html#ga7ab7105e77ce288988037b1df3406ab3',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhcintmsk_5fdterrm_5fmsk_1209',['USB_OTG_HCINTMSK_DTERRM_Msk',['../group___peripheral___registers___bits___definition.html#ga1cbd167749a70c575efd955503111f5c',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhcintmsk_5fdterrm_5fpos_1210',['USB_OTG_HCINTMSK_DTERRM_Pos',['../group___peripheral___registers___bits___definition.html#gab10e5fcf2df7005211ca7b39160ee4a3',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhcintmsk_5ffrmorm_1211',['USB_OTG_HCINTMSK_FRMORM',['../group___peripheral___registers___bits___definition.html#gad2178eb0791f9ea69122edfbd567ba48',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhcintmsk_5ffrmorm_5fmsk_1212',['USB_OTG_HCINTMSK_FRMORM_Msk',['../group___peripheral___registers___bits___definition.html#gada017fb34e00a15702d759ff174d33ff',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhcintmsk_5ffrmorm_5fpos_1213',['USB_OTG_HCINTMSK_FRMORM_Pos',['../group___peripheral___registers___bits___definition.html#gac75612d12f30f20d62f93d75bfe2d93a',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhcintmsk_5fnakm_1214',['USB_OTG_HCINTMSK_NAKM',['../group___peripheral___registers___bits___definition.html#ga51b9246da6c3a45ab697edc1cac74651',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhcintmsk_5fnakm_5fmsk_1215',['USB_OTG_HCINTMSK_NAKM_Msk',['../group___peripheral___registers___bits___definition.html#ga51cc9dd53764be5f1d2ff3d5c7241fd3',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhcintmsk_5fnakm_5fpos_1216',['USB_OTG_HCINTMSK_NAKM_Pos',['../group___peripheral___registers___bits___definition.html#ga5163e183955b5eca93ec5dcaf1915a5f',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhcintmsk_5fnyet_1217',['USB_OTG_HCINTMSK_NYET',['../group___peripheral___registers___bits___definition.html#ga059e35d45f848183cf19399ac1e21ff5',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhcintmsk_5fnyet_5fmsk_1218',['USB_OTG_HCINTMSK_NYET_Msk',['../group___peripheral___registers___bits___definition.html#gac6b099d2da095f8d31fe49ad9b9ecc90',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhcintmsk_5fnyet_5fpos_1219',['USB_OTG_HCINTMSK_NYET_Pos',['../group___peripheral___registers___bits___definition.html#ga49e120401dd9574089323f30a21ce886',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhcintmsk_5fstallm_1220',['USB_OTG_HCINTMSK_STALLM',['../group___peripheral___registers___bits___definition.html#ga001d17d4511b40850fd7c338be250f08',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhcintmsk_5fstallm_5fmsk_1221',['USB_OTG_HCINTMSK_STALLM_Msk',['../group___peripheral___registers___bits___definition.html#ga60f5b08f1a892221f86f3cb370260ef6',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhcintmsk_5fstallm_5fpos_1222',['USB_OTG_HCINTMSK_STALLM_Pos',['../group___peripheral___registers___bits___definition.html#gafafbf0f454f7c9f2ca81e29897782cd7',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhcintmsk_5ftxerrm_1223',['USB_OTG_HCINTMSK_TXERRM',['../group___peripheral___registers___bits___definition.html#ga5322b79193b042004614b21c391d4880',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhcintmsk_5ftxerrm_5fmsk_1224',['USB_OTG_HCINTMSK_TXERRM_Msk',['../group___peripheral___registers___bits___definition.html#ga5bbe2d77401d28701eb827ac3d4cd149',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhcintmsk_5ftxerrm_5fpos_1225',['USB_OTG_HCINTMSK_TXERRM_Pos',['../group___peripheral___registers___bits___definition.html#gad7091461a6aef6b084ca11343b1fcb8a',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhcintmsk_5fxfrcm_1226',['USB_OTG_HCINTMSK_XFRCM',['../group___peripheral___registers___bits___definition.html#gaa3647bba98a8f2c2234aadb2f9441874',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhcintmsk_5fxfrcm_5fmsk_1227',['USB_OTG_HCINTMSK_XFRCM_Msk',['../group___peripheral___registers___bits___definition.html#ga6e1633eb41c92d2a0716e893d10ea404',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhcintmsk_5fxfrcm_5fpos_1228',['USB_OTG_HCINTMSK_XFRCM_Pos',['../group___peripheral___registers___bits___definition.html#gaa3a724642ee5e5c4fb980d2091e5f1b4',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhcsplt_5fcomplsplt_1229',['USB_OTG_HCSPLT_COMPLSPLT',['../group___peripheral___registers___bits___definition.html#gab3f351343c90321b0a43d3a86902bff1',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhcsplt_5fcomplsplt_5fmsk_1230',['USB_OTG_HCSPLT_COMPLSPLT_Msk',['../group___peripheral___registers___bits___definition.html#ga74893ad7550eb4c2d08e5568f1c75c6b',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhcsplt_5fcomplsplt_5fpos_1231',['USB_OTG_HCSPLT_COMPLSPLT_Pos',['../group___peripheral___registers___bits___definition.html#ga2d085f79d265bd2588856d35fa1c83d1',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhcsplt_5fhubaddr_1232',['USB_OTG_HCSPLT_HUBADDR',['../group___peripheral___registers___bits___definition.html#ga01754e9ee191528767bb4e9c4acb92d8',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhcsplt_5fhubaddr_5f0_1233',['USB_OTG_HCSPLT_HUBADDR_0',['../group___peripheral___registers___bits___definition.html#ga6181cfe518eacf85a1fac93dd66327ec',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhcsplt_5fhubaddr_5f1_1234',['USB_OTG_HCSPLT_HUBADDR_1',['../group___peripheral___registers___bits___definition.html#gaeb05271f1a273bc14380c9ad00288701',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhcsplt_5fhubaddr_5f2_1235',['USB_OTG_HCSPLT_HUBADDR_2',['../group___peripheral___registers___bits___definition.html#ga6d1c70b3d92a311b13635ff67f491ec0',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhcsplt_5fhubaddr_5f3_1236',['USB_OTG_HCSPLT_HUBADDR_3',['../group___peripheral___registers___bits___definition.html#gafbb8d9ca0465a572fa7be1afcfa430a8',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhcsplt_5fhubaddr_5f4_1237',['USB_OTG_HCSPLT_HUBADDR_4',['../group___peripheral___registers___bits___definition.html#gad738cccdb8cd3c9db582d8f4aebc3e25',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhcsplt_5fhubaddr_5f5_1238',['USB_OTG_HCSPLT_HUBADDR_5',['../group___peripheral___registers___bits___definition.html#gaeaa7e01257224ccaedb6ac4b34b962cf',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhcsplt_5fhubaddr_5f6_1239',['USB_OTG_HCSPLT_HUBADDR_6',['../group___peripheral___registers___bits___definition.html#ga32808c2fdb053958a30c5ca464534557',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhcsplt_5fhubaddr_5fmsk_1240',['USB_OTG_HCSPLT_HUBADDR_Msk',['../group___peripheral___registers___bits___definition.html#ga16a3d74ca420462ff6493c0a299b49f8',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhcsplt_5fhubaddr_5fpos_1241',['USB_OTG_HCSPLT_HUBADDR_Pos',['../group___peripheral___registers___bits___definition.html#ga9664e8f0ddccc220bf3e13df322de47c',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhcsplt_5fprtaddr_1242',['USB_OTG_HCSPLT_PRTADDR',['../group___peripheral___registers___bits___definition.html#ga4fdaef6145025430a8d9d3742b11bf06',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhcsplt_5fprtaddr_5f0_1243',['USB_OTG_HCSPLT_PRTADDR_0',['../group___peripheral___registers___bits___definition.html#ga212d74a7af2379f1b7065bb46fbb9d2a',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhcsplt_5fprtaddr_5f1_1244',['USB_OTG_HCSPLT_PRTADDR_1',['../group___peripheral___registers___bits___definition.html#ga0704e2d889ef64707ab85a66962e1004',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhcsplt_5fprtaddr_5f2_1245',['USB_OTG_HCSPLT_PRTADDR_2',['../group___peripheral___registers___bits___definition.html#gab33fa67bd58f2fa736d8f64bfbea4e5c',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhcsplt_5fprtaddr_5f3_1246',['USB_OTG_HCSPLT_PRTADDR_3',['../group___peripheral___registers___bits___definition.html#gac813f65324490b9885be03ff12328185',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhcsplt_5fprtaddr_5f4_1247',['USB_OTG_HCSPLT_PRTADDR_4',['../group___peripheral___registers___bits___definition.html#gab6201a61e92821955efb64d3ccffb0da',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhcsplt_5fprtaddr_5f5_1248',['USB_OTG_HCSPLT_PRTADDR_5',['../group___peripheral___registers___bits___definition.html#ga2617f8146fa1656b415f31e9717fd875',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhcsplt_5fprtaddr_5f6_1249',['USB_OTG_HCSPLT_PRTADDR_6',['../group___peripheral___registers___bits___definition.html#ga6c80e6a85b5960c708594433db74b713',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhcsplt_5fprtaddr_5fmsk_1250',['USB_OTG_HCSPLT_PRTADDR_Msk',['../group___peripheral___registers___bits___definition.html#ga2bf43d5ac1fcccf90a4a257da69fe9b9',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhcsplt_5fprtaddr_5fpos_1251',['USB_OTG_HCSPLT_PRTADDR_Pos',['../group___peripheral___registers___bits___definition.html#ga58473c053e85bca6cd888f694dfc054a',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhcsplt_5fspliten_1252',['USB_OTG_HCSPLT_SPLITEN',['../group___peripheral___registers___bits___definition.html#gaa189a5468eabc8d2e05b2c94660060e4',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhcsplt_5fspliten_5fmsk_1253',['USB_OTG_HCSPLT_SPLITEN_Msk',['../group___peripheral___registers___bits___definition.html#gafa1a7031a99e4d180e1510827a84f09a',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhcsplt_5fspliten_5fpos_1254',['USB_OTG_HCSPLT_SPLITEN_Pos',['../group___peripheral___registers___bits___definition.html#ga166c9d0c9c88d3331c2ad15ce365d8d0',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhcsplt_5fxactpos_1255',['USB_OTG_HCSPLT_XACTPOS',['../group___peripheral___registers___bits___definition.html#gac8a144d40531b5f7565d81ca90012f2f',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhcsplt_5fxactpos_5f0_1256',['USB_OTG_HCSPLT_XACTPOS_0',['../group___peripheral___registers___bits___definition.html#gae22d65d33e06b57429f285a7ae7e655e',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhcsplt_5fxactpos_5f1_1257',['USB_OTG_HCSPLT_XACTPOS_1',['../group___peripheral___registers___bits___definition.html#ga0d1c8241b689b9771dce804274470e08',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhcsplt_5fxactpos_5fmsk_1258',['USB_OTG_HCSPLT_XACTPOS_Msk',['../group___peripheral___registers___bits___definition.html#ga6229c6f4ebd9ee5ca4cc7feeda5d3e15',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhcsplt_5fxactpos_5fpos_1259',['USB_OTG_HCSPLT_XACTPOS_Pos',['../group___peripheral___registers___bits___definition.html#ga96c57d899d1d4e67d86d4f8d34712a7c',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhctsiz_5fdoping_1260',['USB_OTG_HCTSIZ_DOPING',['../group___peripheral___registers___bits___definition.html#ga2dcc4677244eb50d430a62870b90c30c',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhctsiz_5fdoping_5fmsk_1261',['USB_OTG_HCTSIZ_DOPING_Msk',['../group___peripheral___registers___bits___definition.html#ga63444676f787b5850bcd74a3dac24c06',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhctsiz_5fdoping_5fpos_1262',['USB_OTG_HCTSIZ_DOPING_Pos',['../group___peripheral___registers___bits___definition.html#gaabd15ce174827e22c8ebd38fd41d4dcd',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhctsiz_5fdpid_1263',['USB_OTG_HCTSIZ_DPID',['../group___peripheral___registers___bits___definition.html#ga7037fb804f6e2a4a3e0c08bd3e345f18',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhctsiz_5fdpid_5f0_1264',['USB_OTG_HCTSIZ_DPID_0',['../group___peripheral___registers___bits___definition.html#gae5509a0f869a4c7ba34f45be4b733b23',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhctsiz_5fdpid_5f1_1265',['USB_OTG_HCTSIZ_DPID_1',['../group___peripheral___registers___bits___definition.html#ga5ae95b441c770521507da1d1d4c51d18',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhctsiz_5fdpid_5fmsk_1266',['USB_OTG_HCTSIZ_DPID_Msk',['../group___peripheral___registers___bits___definition.html#ga66d5133c860991521246501b6e1c055d',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhctsiz_5fdpid_5fpos_1267',['USB_OTG_HCTSIZ_DPID_Pos',['../group___peripheral___registers___bits___definition.html#ga015e511e5d6f38252ca6006e8b984bb7',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhctsiz_5fpktcnt_1268',['USB_OTG_HCTSIZ_PKTCNT',['../group___peripheral___registers___bits___definition.html#gab2177151366a5539b446104cb87d3059',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhctsiz_5fpktcnt_5fmsk_1269',['USB_OTG_HCTSIZ_PKTCNT_Msk',['../group___peripheral___registers___bits___definition.html#gae242d5b51bdad2968cc7f59f2356195b',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhctsiz_5fpktcnt_5fpos_1270',['USB_OTG_HCTSIZ_PKTCNT_Pos',['../group___peripheral___registers___bits___definition.html#ga386ed2405e9608d8846b344d4061eff0',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhctsiz_5fxfrsiz_1271',['USB_OTG_HCTSIZ_XFRSIZ',['../group___peripheral___registers___bits___definition.html#ga983ec8ca0ffac66eea9219acb008fe9c',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhctsiz_5fxfrsiz_5fmsk_1272',['USB_OTG_HCTSIZ_XFRSIZ_Msk',['../group___peripheral___registers___bits___definition.html#ga3d0ecc462bdb146edeb44b1e1bf3ae08',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhctsiz_5fxfrsiz_5fpos_1273',['USB_OTG_HCTSIZ_XFRSIZ_Pos',['../group___peripheral___registers___bits___definition.html#ga4879da0413028804a012612d7459804f',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhfir_5ffrivl_1274',['USB_OTG_HFIR_FRIVL',['../group___peripheral___registers___bits___definition.html#ga8345933ec4180c4ea9013291ce085a2d',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhfir_5ffrivl_5fmsk_1275',['USB_OTG_HFIR_FRIVL_Msk',['../group___peripheral___registers___bits___definition.html#gaadcdb6f745b118b51a607d89bbf864a0',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhfir_5ffrivl_5fpos_1276',['USB_OTG_HFIR_FRIVL_Pos',['../group___peripheral___registers___bits___definition.html#ga97444625f6ff4b49606dc6f571bc66ff',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhfnum_5ffrnum_1277',['USB_OTG_HFNUM_FRNUM',['../group___peripheral___registers___bits___definition.html#gab240bcea196fe42725639b82a3ceac75',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhfnum_5ffrnum_5fmsk_1278',['USB_OTG_HFNUM_FRNUM_Msk',['../group___peripheral___registers___bits___definition.html#ga34a555bd57d9e8f2a41d5b9499ad7c44',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhfnum_5ffrnum_5fpos_1279',['USB_OTG_HFNUM_FRNUM_Pos',['../group___peripheral___registers___bits___definition.html#ga0d39ecc57d3e50e398dcca940eaf4a17',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhfnum_5fftrem_1280',['USB_OTG_HFNUM_FTREM',['../group___peripheral___registers___bits___definition.html#ga51a24f44589040844690a0d6d2f23c13',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhfnum_5fftrem_5fmsk_1281',['USB_OTG_HFNUM_FTREM_Msk',['../group___peripheral___registers___bits___definition.html#gad58aef8796a09f03191b07f54244b67f',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhfnum_5fftrem_5fpos_1282',['USB_OTG_HFNUM_FTREM_Pos',['../group___peripheral___registers___bits___definition.html#gae3bc7db92586a96e7a4c3cebb97644a5',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhost_5fbase_1283',['USB_OTG_HOST_BASE',['../group___peripheral__memory__map.html#ga3bb2dd6c82eefd8587b6146ba36ae071',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhost_5fchannel_5fbase_1284',['USB_OTG_HOST_CHANNEL_BASE',['../group___peripheral__memory__map.html#ga942c8c5241b80fbcf638fea0fa18bebd',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhost_5fchannel_5fsize_1285',['USB_OTG_HOST_CHANNEL_SIZE',['../group___peripheral__memory__map.html#ga266cb1dbb50faf447f9c15d2ee93a522',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhost_5fport_5fbase_1286',['USB_OTG_HOST_PORT_BASE',['../group___peripheral__memory__map.html#ga42f433cb79ca69f09972e690fda6737a',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhostchanneltypedef_1287',['USB_OTG_HostChannelTypeDef',['../struct_u_s_b___o_t_g___host_channel_type_def.html',1,'']]], - ['usb_5fotg_5fhosttypedef_1288',['USB_OTG_HostTypeDef',['../struct_u_s_b___o_t_g___host_type_def.html',1,'']]], - ['usb_5fotg_5fhprt_5fpcdet_1289',['USB_OTG_HPRT_PCDET',['../group___peripheral___registers___bits___definition.html#ga1bd9f8a9da09f9d52f19b8e68551c285',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhprt_5fpcdet_5fmsk_1290',['USB_OTG_HPRT_PCDET_Msk',['../group___peripheral___registers___bits___definition.html#gafd445d6f75df03444eb8b978d39f1e6f',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhprt_5fpcdet_5fpos_1291',['USB_OTG_HPRT_PCDET_Pos',['../group___peripheral___registers___bits___definition.html#ga20a5c1b6c67d02966503ed2867676c03',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhprt_5fpcsts_1292',['USB_OTG_HPRT_PCSTS',['../group___peripheral___registers___bits___definition.html#ga01b303083e66f3018e57dbb275b6f4b5',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhprt_5fpcsts_5fmsk_1293',['USB_OTG_HPRT_PCSTS_Msk',['../group___peripheral___registers___bits___definition.html#ga6277ab1fc490e322b3da7f1ebab56dce',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhprt_5fpcsts_5fpos_1294',['USB_OTG_HPRT_PCSTS_Pos',['../group___peripheral___registers___bits___definition.html#gacd91baead77bc3be91bf92566210fca2',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhprt_5fpena_1295',['USB_OTG_HPRT_PENA',['../group___peripheral___registers___bits___definition.html#ga95ad10f10631095aeb7a27e0475242f0',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhprt_5fpena_5fmsk_1296',['USB_OTG_HPRT_PENA_Msk',['../group___peripheral___registers___bits___definition.html#ga8068309917d8be1de7bc9a2d9dea22e6',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhprt_5fpena_5fpos_1297',['USB_OTG_HPRT_PENA_Pos',['../group___peripheral___registers___bits___definition.html#gaa45a500ec95308387eebdfb881c0fcfc',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhprt_5fpenchng_1298',['USB_OTG_HPRT_PENCHNG',['../group___peripheral___registers___bits___definition.html#ga7d84be9a2f9c7f8750ee448c99164821',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhprt_5fpenchng_5fmsk_1299',['USB_OTG_HPRT_PENCHNG_Msk',['../group___peripheral___registers___bits___definition.html#gae2e7655490c7bdff631166769d46838d',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhprt_5fpenchng_5fpos_1300',['USB_OTG_HPRT_PENCHNG_Pos',['../group___peripheral___registers___bits___definition.html#ga47e25510c52062775f4155eb233a4bca',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhprt_5fplsts_1301',['USB_OTG_HPRT_PLSTS',['../group___peripheral___registers___bits___definition.html#gad0a3c8eb0d6b7eea1f4aaf60bb27b15c',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhprt_5fplsts_5f0_1302',['USB_OTG_HPRT_PLSTS_0',['../group___peripheral___registers___bits___definition.html#ga2bbb5a9719331ba00d44ff01b267bf7d',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhprt_5fplsts_5f1_1303',['USB_OTG_HPRT_PLSTS_1',['../group___peripheral___registers___bits___definition.html#gae87cecc544d0c1d8e778c3a598da9276',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhprt_5fplsts_5fmsk_1304',['USB_OTG_HPRT_PLSTS_Msk',['../group___peripheral___registers___bits___definition.html#ga2b757dac879fce7dae5214b192863ea2',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhprt_5fplsts_5fpos_1305',['USB_OTG_HPRT_PLSTS_Pos',['../group___peripheral___registers___bits___definition.html#ga4b46c779a0b842af9f269ad488a9ed58',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhprt_5fpoca_1306',['USB_OTG_HPRT_POCA',['../group___peripheral___registers___bits___definition.html#gac4d510d6215d72faac65ad3109f009af',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhprt_5fpoca_5fmsk_1307',['USB_OTG_HPRT_POCA_Msk',['../group___peripheral___registers___bits___definition.html#gaf14c79e04bc40d676bb24be0b41145ca',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhprt_5fpoca_5fpos_1308',['USB_OTG_HPRT_POCA_Pos',['../group___peripheral___registers___bits___definition.html#gab3602a595b6dd2c43483e6df37567ebc',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhprt_5fpocchng_1309',['USB_OTG_HPRT_POCCHNG',['../group___peripheral___registers___bits___definition.html#gabc46d2c0e7f2525ad2d1dcb41c5e3814',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhprt_5fpocchng_5fmsk_1310',['USB_OTG_HPRT_POCCHNG_Msk',['../group___peripheral___registers___bits___definition.html#ga63a4749bf5614ee8388364463ef039d6',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhprt_5fpocchng_5fpos_1311',['USB_OTG_HPRT_POCCHNG_Pos',['../group___peripheral___registers___bits___definition.html#gac12d375e01d04a960d38b26dd2e8685f',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhprt_5fppwr_1312',['USB_OTG_HPRT_PPWR',['../group___peripheral___registers___bits___definition.html#ga20965e6de30c19d8b0f355f62680c180',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhprt_5fppwr_5fmsk_1313',['USB_OTG_HPRT_PPWR_Msk',['../group___peripheral___registers___bits___definition.html#ga6cd2ac835835be4a80bc43659d300ebe',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhprt_5fppwr_5fpos_1314',['USB_OTG_HPRT_PPWR_Pos',['../group___peripheral___registers___bits___definition.html#ga88c07618a453428a840a89100f6dab38',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhprt_5fpres_1315',['USB_OTG_HPRT_PRES',['../group___peripheral___registers___bits___definition.html#ga643fdc3285aa718952214857d15dadfb',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhprt_5fpres_5fmsk_1316',['USB_OTG_HPRT_PRES_Msk',['../group___peripheral___registers___bits___definition.html#gad3cf39420fbe05f13da97b9d4f54c753',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhprt_5fpres_5fpos_1317',['USB_OTG_HPRT_PRES_Pos',['../group___peripheral___registers___bits___definition.html#ga33aaef70a252270021a2aaef1c33b726',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhprt_5fprst_1318',['USB_OTG_HPRT_PRST',['../group___peripheral___registers___bits___definition.html#ga5741bb0728c8ccf320ef609699c3425a',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhprt_5fprst_5fmsk_1319',['USB_OTG_HPRT_PRST_Msk',['../group___peripheral___registers___bits___definition.html#ga26c4eb727f6b37a90e1b9a2aaa64414d',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhprt_5fprst_5fpos_1320',['USB_OTG_HPRT_PRST_Pos',['../group___peripheral___registers___bits___definition.html#gaac3ce670bb14739add1077513f30a91e',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhprt_5fpspd_1321',['USB_OTG_HPRT_PSPD',['../group___peripheral___registers___bits___definition.html#ga5a28ddd62304e263536ff9b5cd855ff5',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhprt_5fpspd_5f0_1322',['USB_OTG_HPRT_PSPD_0',['../group___peripheral___registers___bits___definition.html#gac47d8caa24e4f5e6b66e4d70d549d5fa',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhprt_5fpspd_5f1_1323',['USB_OTG_HPRT_PSPD_1',['../group___peripheral___registers___bits___definition.html#ga1b8f7977f0d956d6955efd2640530f73',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhprt_5fpspd_5fmsk_1324',['USB_OTG_HPRT_PSPD_Msk',['../group___peripheral___registers___bits___definition.html#ga66c65cc05ea21eebd9013f9f84880385',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhprt_5fpspd_5fpos_1325',['USB_OTG_HPRT_PSPD_Pos',['../group___peripheral___registers___bits___definition.html#ga55160c4571f2bcfb4a77c907b0b7c07c',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhprt_5fpsusp_1326',['USB_OTG_HPRT_PSUSP',['../group___peripheral___registers___bits___definition.html#ga98db6454c00ab942c1ca969ebb192f67',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhprt_5fpsusp_5fmsk_1327',['USB_OTG_HPRT_PSUSP_Msk',['../group___peripheral___registers___bits___definition.html#gad5b1f55077b63ba7fda82f1d5d06de23',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhprt_5fpsusp_5fpos_1328',['USB_OTG_HPRT_PSUSP_Pos',['../group___peripheral___registers___bits___definition.html#ga017663af01aba7f6745732a92f731668',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhprt_5fptctl_1329',['USB_OTG_HPRT_PTCTL',['../group___peripheral___registers___bits___definition.html#ga01677a7e4ccb6c54d7bce0cba3899bfb',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhprt_5fptctl_5f0_1330',['USB_OTG_HPRT_PTCTL_0',['../group___peripheral___registers___bits___definition.html#ga3f4faf063b47c7bc83c090e6000e9162',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhprt_5fptctl_5f1_1331',['USB_OTG_HPRT_PTCTL_1',['../group___peripheral___registers___bits___definition.html#ga791b063b5e86ffbbfd6980f447408e83',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhprt_5fptctl_5f2_1332',['USB_OTG_HPRT_PTCTL_2',['../group___peripheral___registers___bits___definition.html#ga6491b21dbe177ecb91628169d02b8c76',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhprt_5fptctl_5f3_1333',['USB_OTG_HPRT_PTCTL_3',['../group___peripheral___registers___bits___definition.html#ga087d26522b46212d380ca5a1e1c16fed',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhprt_5fptctl_5fmsk_1334',['USB_OTG_HPRT_PTCTL_Msk',['../group___peripheral___registers___bits___definition.html#ga3a02e11d6a1f700ee19fcc08117ebe16',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhprt_5fptctl_5fpos_1335',['USB_OTG_HPRT_PTCTL_Pos',['../group___peripheral___registers___bits___definition.html#ga07ff20317b07fd8655f12cdc0e4dba61',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhptxfsiz_5fptxfd_1336',['USB_OTG_HPTXFSIZ_PTXFD',['../group___peripheral___registers___bits___definition.html#ga85a628f9094f55c620b2846635803781',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhptxfsiz_5fptxfd_5fmsk_1337',['USB_OTG_HPTXFSIZ_PTXFD_Msk',['../group___peripheral___registers___bits___definition.html#ga1b5b79b979f2e9443324066faaa92245',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhptxfsiz_5fptxfd_5fpos_1338',['USB_OTG_HPTXFSIZ_PTXFD_Pos',['../group___peripheral___registers___bits___definition.html#gab930c4f0f50e3f18256064a8f2bdb2b4',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhptxfsiz_5fptxsa_1339',['USB_OTG_HPTXFSIZ_PTXSA',['../group___peripheral___registers___bits___definition.html#ga62a28fc8c8ab16a52858febfbb0382ef',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhptxfsiz_5fptxsa_5fmsk_1340',['USB_OTG_HPTXFSIZ_PTXSA_Msk',['../group___peripheral___registers___bits___definition.html#ga9be1af071c308f74cf353d2ce3d691b9',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhptxfsiz_5fptxsa_5fpos_1341',['USB_OTG_HPTXFSIZ_PTXSA_Pos',['../group___peripheral___registers___bits___definition.html#ga249c1794df3b2690031184ae330118e7',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhptxsts_5fptxfsavl_1342',['USB_OTG_HPTXSTS_PTXFSAVL',['../group___peripheral___registers___bits___definition.html#gab37734d4115211633d584e59cbeabe19',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhptxsts_5fptxfsavl_5fmsk_1343',['USB_OTG_HPTXSTS_PTXFSAVL_Msk',['../group___peripheral___registers___bits___definition.html#gab49ec3e222a628b813a802f9ebb28448',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhptxsts_5fptxfsavl_5fpos_1344',['USB_OTG_HPTXSTS_PTXFSAVL_Pos',['../group___peripheral___registers___bits___definition.html#ga4a6aedb1b39e4e5adaacbc690e30515a',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhptxsts_5fptxqsav_1345',['USB_OTG_HPTXSTS_PTXQSAV',['../group___peripheral___registers___bits___definition.html#ga338e5e7a3613da0d1dbca7bcdced15ca',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhptxsts_5fptxqsav_5f0_1346',['USB_OTG_HPTXSTS_PTXQSAV_0',['../group___peripheral___registers___bits___definition.html#ga0029668daec1137fa7373e7b151099ac',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhptxsts_5fptxqsav_5f1_1347',['USB_OTG_HPTXSTS_PTXQSAV_1',['../group___peripheral___registers___bits___definition.html#ga96badb4855acc006656a4045db4170f2',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhptxsts_5fptxqsav_5f2_1348',['USB_OTG_HPTXSTS_PTXQSAV_2',['../group___peripheral___registers___bits___definition.html#ga51e29269f12dd3a01bdccd31b5fefcdf',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhptxsts_5fptxqsav_5f3_1349',['USB_OTG_HPTXSTS_PTXQSAV_3',['../group___peripheral___registers___bits___definition.html#gac36241d1f9e6a781b55952f6ae8ca4ea',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhptxsts_5fptxqsav_5f4_1350',['USB_OTG_HPTXSTS_PTXQSAV_4',['../group___peripheral___registers___bits___definition.html#gaccf8f748b5a048fd46fc3c710daddf2a',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhptxsts_5fptxqsav_5f5_1351',['USB_OTG_HPTXSTS_PTXQSAV_5',['../group___peripheral___registers___bits___definition.html#gaac0ab79df9fad1b945edb6384dbc8e3d',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhptxsts_5fptxqsav_5f6_1352',['USB_OTG_HPTXSTS_PTXQSAV_6',['../group___peripheral___registers___bits___definition.html#gaba458280e9d6532dd12837a90742f408',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhptxsts_5fptxqsav_5f7_1353',['USB_OTG_HPTXSTS_PTXQSAV_7',['../group___peripheral___registers___bits___definition.html#ga873ee2b3f86e357de46cd936a899ed31',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhptxsts_5fptxqsav_5fmsk_1354',['USB_OTG_HPTXSTS_PTXQSAV_Msk',['../group___peripheral___registers___bits___definition.html#ga57a34e5dc4826091ab53667fa1d0d6d7',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhptxsts_5fptxqsav_5fpos_1355',['USB_OTG_HPTXSTS_PTXQSAV_Pos',['../group___peripheral___registers___bits___definition.html#gad838ab2d271e69a85003600c33fa636e',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhptxsts_5fptxqtop_1356',['USB_OTG_HPTXSTS_PTXQTOP',['../group___peripheral___registers___bits___definition.html#ga4c9381ee78a71b8c91e76a974fd633f1',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhptxsts_5fptxqtop_5f0_1357',['USB_OTG_HPTXSTS_PTXQTOP_0',['../group___peripheral___registers___bits___definition.html#gadc4f9d82388f22aedd70ffc2074f8526',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhptxsts_5fptxqtop_5f1_1358',['USB_OTG_HPTXSTS_PTXQTOP_1',['../group___peripheral___registers___bits___definition.html#ga4b75ae59aa46eb3f366e0c0eb18a953e',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhptxsts_5fptxqtop_5f2_1359',['USB_OTG_HPTXSTS_PTXQTOP_2',['../group___peripheral___registers___bits___definition.html#ga49c079a1cad8c676ff57e997fddcc939',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhptxsts_5fptxqtop_5f3_1360',['USB_OTG_HPTXSTS_PTXQTOP_3',['../group___peripheral___registers___bits___definition.html#ga37f71961a65f5c88a0bcfea71c88bfab',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhptxsts_5fptxqtop_5f4_1361',['USB_OTG_HPTXSTS_PTXQTOP_4',['../group___peripheral___registers___bits___definition.html#ga10291d16c7f539b1fb2d6e0b22fd7cbf',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhptxsts_5fptxqtop_5f5_1362',['USB_OTG_HPTXSTS_PTXQTOP_5',['../group___peripheral___registers___bits___definition.html#ga8bac7d58ce0353c4570601a5a8c04090',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhptxsts_5fptxqtop_5f6_1363',['USB_OTG_HPTXSTS_PTXQTOP_6',['../group___peripheral___registers___bits___definition.html#ga164af5e3ff7a7c104028840b5ccb8447',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhptxsts_5fptxqtop_5f7_1364',['USB_OTG_HPTXSTS_PTXQTOP_7',['../group___peripheral___registers___bits___definition.html#gad66e43fdfea8df808ae46b41537c5b0a',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhptxsts_5fptxqtop_5fmsk_1365',['USB_OTG_HPTXSTS_PTXQTOP_Msk',['../group___peripheral___registers___bits___definition.html#ga4378a888dfbf5185446cdf184521471b',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhptxsts_5fptxqtop_5fpos_1366',['USB_OTG_HPTXSTS_PTXQTOP_Pos',['../group___peripheral___registers___bits___definition.html#ga6a19e1bb99e39af155bffbdaed9f001d',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhs_1367',['USB_OTG_HS',['../group___peripheral__declaration.html#ga820f5f7cb0a7af72a2444a1903fd83bc',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhs_5fhost_5fmax_5fchannel_5fnbr_1368',['USB_OTG_HS_HOST_MAX_CHANNEL_NBR',['../group___exported__macros.html#ga974d43b38d7e7578fa7ac69c64dcc473',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhs_5fmax_5fin_5fendpoints_1369',['USB_OTG_HS_MAX_IN_ENDPOINTS',['../group___exported__macros.html#gae79bbfa7391870814f10c8025ade8a2a',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhs_5fmax_5fout_5fendpoints_1370',['USB_OTG_HS_MAX_OUT_ENDPOINTS',['../group___exported__macros.html#gace63bb65e2fb24f0df6ebe1e65efa560',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhs_5fperiph_1371',['usb_otg_hs_periph',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga4e565603c7406e27b1f5503de3a8c41b',1,'stm32f4xx_periph_registers.c']]], - ['usb_5fotg_5fhs_5fperiph_5fbase_1372',['USB_OTG_HS_PERIPH_BASE',['../group___peripheral__memory__map.html#gaa405d2ebfd7e9394237b6639f16a5409',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fhs_5ftotal_5ffifo_5fsize_1373',['USB_OTG_HS_TOTAL_FIFO_SIZE',['../group___exported__macros.html#ga55a4488eac406bcff895de59782fd6a7',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fin_5fendpoint_5fbase_1374',['USB_OTG_IN_ENDPOINT_BASE',['../group___peripheral__memory__map.html#gad8f69041452615aeb3948600e3882246',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5finendpointtypedef_1375',['USB_OTG_INEndpointTypeDef',['../struct_u_s_b___o_t_g___i_n_endpoint_type_def.html',1,'']]], - ['usb_5fotg_5fnptxfd_1376',['USB_OTG_NPTXFD',['../group___peripheral___registers___bits___definition.html#gaa42909f04dfa46977d5d95ba84a81f7a',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fnptxfd_5fmsk_1377',['USB_OTG_NPTXFD_Msk',['../group___peripheral___registers___bits___definition.html#ga925ee7600d2f4c33f4ada106ad2da436',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fnptxfd_5fpos_1378',['USB_OTG_NPTXFD_Pos',['../group___peripheral___registers___bits___definition.html#ga954d5cbcea939dfff88dcbf8be48fcb8',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fnptxfsa_1379',['USB_OTG_NPTXFSA',['../group___peripheral___registers___bits___definition.html#ga7288bc9a03bd0068584bfbf7a00de132',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fnptxfsa_5fmsk_1380',['USB_OTG_NPTXFSA_Msk',['../group___peripheral___registers___bits___definition.html#ga8d574718d661d828fdbd50dd9de84f79',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fnptxfsa_5fpos_1381',['USB_OTG_NPTXFSA_Pos',['../group___peripheral___registers___bits___definition.html#gad33e0dcd0891b3d9175d22596f37335e',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fout_5fendpoint_5fbase_1382',['USB_OTG_OUT_ENDPOINT_BASE',['../group___peripheral__memory__map.html#gaf0e972b8f028ecf44a652029efbd4642',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5foutendpointtypedef_1383',['USB_OTG_OUTEndpointTypeDef',['../struct_u_s_b___o_t_g___o_u_t_endpoint_type_def.html',1,'']]], - ['usb_5fotg_5fpcgcctl_5fbase_1384',['USB_OTG_PCGCCTL_BASE',['../group___peripheral__memory__map.html#gaa9766975aca084c257730879568bc7cf',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fpcgcctl_5fgateclk_1385',['USB_OTG_PCGCCTL_GATECLK',['../group___peripheral___registers___bits___definition.html#gad8756280c79db9bdd546f6dabce92849',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fpcgcctl_5fgateclk_5fmsk_1386',['USB_OTG_PCGCCTL_GATECLK_Msk',['../group___peripheral___registers___bits___definition.html#gaa05b7e567009a05c0fbc460de78ece1f',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fpcgcctl_5fgateclk_5fpos_1387',['USB_OTG_PCGCCTL_GATECLK_Pos',['../group___peripheral___registers___bits___definition.html#ga742b5f249d0b9b10fd616990149cf6c7',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fpcgcctl_5fphysusp_1388',['USB_OTG_PCGCCTL_PHYSUSP',['../group___peripheral___registers___bits___definition.html#ga8f07a7549ecc61ab2df0775ea177df12',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fpcgcctl_5fphysusp_5fmsk_1389',['USB_OTG_PCGCCTL_PHYSUSP_Msk',['../group___peripheral___registers___bits___definition.html#gac29bcd967dad8f66da440480b32b7b5d',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fpcgcctl_5fphysusp_5fpos_1390',['USB_OTG_PCGCCTL_PHYSUSP_Pos',['../group___peripheral___registers___bits___definition.html#ga370573700a56720b49363b5a166303de',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fpcgcctl_5fstopclk_1391',['USB_OTG_PCGCCTL_STOPCLK',['../group___peripheral___registers___bits___definition.html#ga77cb2d7ab53783663a7a6dd457d3ba25',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fpcgcctl_5fstopclk_5fmsk_1392',['USB_OTG_PCGCCTL_STOPCLK_Msk',['../group___peripheral___registers___bits___definition.html#ga1d4f9a974fab851fcfb0803ba5380b8d',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fpcgcctl_5fstopclk_5fpos_1393',['USB_OTG_PCGCCTL_STOPCLK_Pos',['../group___peripheral___registers___bits___definition.html#ga7cf33736f41c6c0098df1ac2cb9dcb00',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fpcgcr_5fgatehclk_1394',['USB_OTG_PCGCR_GATEHCLK',['../group___peripheral___registers___bits___definition.html#ga6d6bcb65b4cb112d17466cf24c42e37f',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fpcgcr_5fgatehclk_5fmsk_1395',['USB_OTG_PCGCR_GATEHCLK_Msk',['../group___peripheral___registers___bits___definition.html#ga14c302139df9ab546ce190277ecbc090',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fpcgcr_5fgatehclk_5fpos_1396',['USB_OTG_PCGCR_GATEHCLK_Pos',['../group___peripheral___registers___bits___definition.html#gaf87ca67c6646747e2fbea26cda8890b5',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fpcgcr_5fphysusp_1397',['USB_OTG_PCGCR_PHYSUSP',['../group___peripheral___registers___bits___definition.html#ga0b8c8a29c623fc354c03942a6a414c06',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fpcgcr_5fphysusp_5fmsk_1398',['USB_OTG_PCGCR_PHYSUSP_Msk',['../group___peripheral___registers___bits___definition.html#ga6bd9eee61333c5bd9565e74be8daacb2',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fpcgcr_5fphysusp_5fpos_1399',['USB_OTG_PCGCR_PHYSUSP_Pos',['../group___peripheral___registers___bits___definition.html#ga0d0ac8d8fabee0eea8a1711ea7fafe02',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fpcgcr_5fstppclk_1400',['USB_OTG_PCGCR_STPPCLK',['../group___peripheral___registers___bits___definition.html#gac696153ff9f165deadff3fe0225849e8',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fpcgcr_5fstppclk_5fmsk_1401',['USB_OTG_PCGCR_STPPCLK_Msk',['../group___peripheral___registers___bits___definition.html#ga7f118ddd4551c474f8edc23058876fdf',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fpcgcr_5fstppclk_5fpos_1402',['USB_OTG_PCGCR_STPPCLK_Pos',['../group___peripheral___registers___bits___definition.html#ga3b40c8b9e9f41a6d908e918591093dea',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fpktsts_1403',['USB_OTG_PKTSTS',['../group___peripheral___registers___bits___definition.html#ga04a5d91a12a215c4eeeb06ce604c22e5',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fpktsts_5f0_1404',['USB_OTG_PKTSTS_0',['../group___peripheral___registers___bits___definition.html#ga77111a987b72536f21bfd7bb08594b35',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fpktsts_5f1_1405',['USB_OTG_PKTSTS_1',['../group___peripheral___registers___bits___definition.html#gafa2fb9acefebdda4d1178fd41152354a',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fpktsts_5f2_1406',['USB_OTG_PKTSTS_2',['../group___peripheral___registers___bits___definition.html#gab280bdccc1f515e8b031ca572a40dbeb',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fpktsts_5f3_1407',['USB_OTG_PKTSTS_3',['../group___peripheral___registers___bits___definition.html#gad095ea293b9f4a79f215502575bc3c70',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fpktsts_5fmsk_1408',['USB_OTG_PKTSTS_Msk',['../group___peripheral___registers___bits___definition.html#gac0bbc3a438b82f7739fdb08721163c3b',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5fpktsts_5fpos_1409',['USB_OTG_PKTSTS_Pos',['../group___peripheral___registers___bits___definition.html#ga68c44befbf867cd110ad202dfbaf89bc',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5ftx0fd_1410',['USB_OTG_TX0FD',['../group___peripheral___registers___bits___definition.html#gabd6ed0dba3c92506928f19a8dae4a4cd',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5ftx0fd_5fmsk_1411',['USB_OTG_TX0FD_Msk',['../group___peripheral___registers___bits___definition.html#gae9db88da5ed817b0e836a7fe631b8a3c',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5ftx0fd_5fpos_1412',['USB_OTG_TX0FD_Pos',['../group___peripheral___registers___bits___definition.html#ga1230d9e57244b6175d180f4055043add',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5ftx0fsa_1413',['USB_OTG_TX0FSA',['../group___peripheral___registers___bits___definition.html#ga878564768aedb86dd987f933edd56ded',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5ftx0fsa_5fmsk_1414',['USB_OTG_TX0FSA_Msk',['../group___peripheral___registers___bits___definition.html#ga1135e855d8d6bd816ab72978a82217d5',1,'stm32f407xx_matlab.h']]], - ['usb_5fotg_5ftx0fsa_5fpos_1415',['USB_OTG_TX0FSA_Pos',['../group___peripheral___registers___bits___definition.html#ga09477e07dbd7bb519ed546c5a609f9e2',1,'stm32f407xx_matlab.h']]], - ['use_5ftim1_1416',['USE_TIM1',['../group___s_i_m_u_l_a_t_o_r___c_o_n_f.html#ga54a98c21365e0bc45b81555d2b101f2b',1,'stm32f4xx_matlab_conf.h']]], - ['use_5ftim12_1417',['USE_TIM12',['../group___s_i_m_u_l_a_t_o_r___c_o_n_f.html#ga4e2b0e6cdf9eed74581b575c3fd9516b',1,'stm32f4xx_matlab_conf.h']]], - ['use_5ftim3_1418',['USE_TIM3',['../group___s_i_m_u_l_a_t_o_r___c_o_n_f.html#ga5b5685a43273b6e37242a4aba3ee0617',1,'stm32f4xx_matlab_conf.h']]], - ['use_5ftim4_1419',['USE_TIM4',['../group___s_i_m_u_l_a_t_o_r___c_o_n_f.html#ga1493b39c9214501180b81b4c892f9be0',1,'stm32f4xx_matlab_conf.h']]], - ['use_5ftim4_5fhandler_1420',['USE_TIM4_HANDLER',['../group___s_i_m_u_l_a_t_o_r___c_o_n_f.html#gae500122af1918af2cf69bc107315d15f',1,'stm32f4xx_matlab_conf.h']]], - ['use_5ftim7_1421',['USE_TIM7',['../group___s_i_m_u_l_a_t_o_r___c_o_n_f.html#ga7cdc54cc8cbbb6e9f60001f1e3e6ec67',1,'stm32f4xx_matlab_conf.h']]], - ['use_5ftim7_5fhandler_1422',['USE_TIM7_HANDLER',['../group___s_i_m_u_l_a_t_o_r___c_o_n_f.html#ga989acf15c18c3016a65fcc888d2f641b',1,'stm32f4xx_matlab_conf.h']]], - ['use_5ftim8_5fbrk_5ftim12_5fhandler_1423',['USE_TIM8_BRK_TIM12_HANDLER',['../group___s_i_m_u_l_a_t_o_r___c_o_n_f.html#gae38cd8ed529da5815f8619b9bad8c97d',1,'stm32f4xx_matlab_conf.h']]] + ['запуÑтить_20отладку_0',['Как запуÑтить отладку',['../index.html#как-запуÑтить-отладку',1,'']]] ]; diff --git a/DOCS/html/search/all_16.js b/DOCS/html/search/all_16.js index 6633d5d..a726b9d 100644 --- a/DOCS/html/search/all_16.js +++ b/DOCS/html/search/all_16.js @@ -1,7 +1,4 @@ var searchData= [ - ['v_0',['V',['../group___c_m_s_i_s__core___debug_functions.html#gacd4a2b64faee91e4a9eef300667fa222',1,'APSR_Type::V'],['../group___c_m_s_i_s__core___debug_functions.html#gacd4a2b64faee91e4a9eef300667fa222',1,'APSR_Type::@0::V'],['../group___c_m_s_i_s__core___debug_functions.html#gacd4a2b64faee91e4a9eef300667fa222',1,'xPSR_Type::V'],['../group___c_m_s_i_s__core___debug_functions.html#gacd4a2b64faee91e4a9eef300667fa222',1,'xPSR_Type::@2::V']]], - ['val_1',['VAL',['../group___c_m_s_i_s__core___debug_functions.html#gae7a655a853654127f3dfb7fa32c3f457',1,'SysTick_Type']]], - ['vectored_20interrupt_20controller_20nvic_2',['Nested Vectored Interrupt Controller (NVIC)',['../group___c_m_s_i_s___n_v_i_c.html',1,'']]], - ['vtor_3',['VTOR',['../group___c_m_s_i_s__core___debug_functions.html#gae457d2615e203c3d5904a43a1bc9df71',1,'SCB_Type']]] + ['инÑтрукциÑ_0',['ИнÑтрукциÑ',['../index.html#инÑтрукциÑ',1,'']]] ]; diff --git a/DOCS/html/search/all_17.js b/DOCS/html/search/all_17.js index 282b69c..a7296e4 100644 --- a/DOCS/html/search/all_17.js +++ b/DOCS/html/search/all_17.js @@ -1,71 +1,9 @@ var searchData= [ - ['w_0',['w',['../group___c_m_s_i_s__core___debug_functions.html#gad0fb62e7a08e70fc5e0a76b67809f84b',1,'APSR_Type::w'],['../group___c_m_s_i_s__core___debug_functions.html#gad0fb62e7a08e70fc5e0a76b67809f84b',1,'IPSR_Type::w'],['../group___c_m_s_i_s__core___debug_functions.html#gad0fb62e7a08e70fc5e0a76b67809f84b',1,'xPSR_Type::w'],['../group___c_m_s_i_s__core___debug_functions.html#gad0fb62e7a08e70fc5e0a76b67809f84b',1,'CONTROL_Type::w']]], - ['watchpoint_20and_20trace_20dwt_1',['Data Watchpoint and Trace (DWT)',['../group___c_m_s_i_s___d_w_t.html',1,'']]], - ['wchar_5fmax_2',['WCHAR_MAX',['../stdint_8h.html#a2a823f3ccf2306cfbaa34d8addf66010',1,'stdint.h']]], - ['wchar_5fmin_3',['WCHAR_MIN',['../stdint_8h.html#a051084d5ebcabf282d9ca9bb2b891a78',1,'stdint.h']]], - ['while_4',['while',['../mcu__wrapper__conf_8h.html#a866c2dad3e54488a018e859b3dc6feba',1,'mcu_wrapper_conf.h']]], - ['wint_5fmax_5',['WINT_MAX',['../stdint_8h.html#ad3f7b6bb8aa7d619017a91d3b2edc1ee',1,'stdint.h']]], - ['wint_5fmin_6',['WINT_MIN',['../stdint_8h.html#a5285bc55170ae1701e599decacc7f001',1,'stdint.h']]], - ['wpr_7',['WPR',['../group___c_m_s_i_s___device.html#ga6204786b050eb135fabb15784698e86e',1,'RTC_TypeDef']]], - ['wrapper_5fconf_8',['WRAPPER_CONF',['../group___w_r_a_p_p_e_r___c_o_n_f.html',1,'']]], - ['write_5foc_5fto_5fgpio_9',['Write_OC_to_GPIO',['../group___t_i_m___s_i_m_u_l_a_t_o_r.html#ga28ab1124ab4cfbd21acb613cb0873d2d',1,'Write_OC_to_GPIO(TIM_TypeDef *TIMx, struct TIM_Sim *TIMS): stm32f4xx_matlab_tim.c'],['../group___t_i_m___s_i_m_u_l_a_t_o_r.html#ga28ab1124ab4cfbd21acb613cb0873d2d',1,'Write_OC_to_GPIO(TIM_TypeDef *TIMx, struct TIM_Sim *TIMS): stm32f4xx_matlab_tim.c']]], - ['write_5foc_5fto_5ftrgo_10',['Write_OC_to_TRGO',['../group___t_i_m___s_i_m_u_l_a_t_o_r.html#ga4ac3f9a63d2433519bd5137bab286080',1,'Write_OC_to_TRGO(TIM_TypeDef *TIMx, struct TIM_Sim *TIMS): stm32f4xx_matlab_tim.c'],['../group___t_i_m___s_i_m_u_l_a_t_o_r.html#ga4ac3f9a63d2433519bd5137bab286080',1,'Write_OC_to_TRGO(TIM_TypeDef *TIMx, struct TIM_Sim *TIMS): stm32f4xx_matlab_tim.c']]], - ['write_5freg_11',['WRITE_REG',['../group___exported__macro.html#ga32f78bffcaf6d13023dcd7f05e0c4d57',1,'stm32f4xx.h']]], - ['wutr_12',['WUTR',['../group___c_m_s_i_s___device.html#gac5b3c8be61045a304d3076d4714d29f2',1,'RTC_TypeDef']]], - ['wwdg_13',['WWDG',['../group___peripheral__declaration.html#ga9821fd01757986612ddb8982e2fe27f1',1,'stm32f407xx_matlab.h']]], - ['wwdg_14',['wwdg',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga8702a9a8de59f4e7f66b061c980a1c23',1,'stm32f4xx_periph_registers.c']]], - ['wwdg_5fbase_15',['WWDG_BASE',['../group___peripheral__memory__map.html#ga9a5bf4728ab93dea5b569f5b972cbe62',1,'stm32f407xx_matlab.h']]], - ['wwdg_5fcfr_5fewi_16',['WWDG_CFR_EWI',['../group___peripheral___registers___bits___definition.html#ga931941dc5d795502371ac5dd8fbac1e9',1,'stm32f407xx_matlab.h']]], - ['wwdg_5fcfr_5fewi_5fmsk_17',['WWDG_CFR_EWI_Msk',['../group___peripheral___registers___bits___definition.html#gaca4ed7e970421b1b4b4b0f94e3296117',1,'stm32f407xx_matlab.h']]], - ['wwdg_5fcfr_5fewi_5fpos_18',['WWDG_CFR_EWI_Pos',['../group___peripheral___registers___bits___definition.html#ga6b4e702f6496841d60bc7ada8d68d648',1,'stm32f407xx_matlab.h']]], - ['wwdg_5fcfr_5fw_19',['WWDG_CFR_W',['../group___peripheral___registers___bits___definition.html#gabfbb9991bd6a3699399ca569c71fe8c9',1,'stm32f407xx_matlab.h']]], - ['wwdg_5fcfr_5fw0_20',['WWDG_CFR_W0',['../group___peripheral___registers___bits___definition.html#gae37e08098d003f44eb8770a9d9bd40d0',1,'stm32f407xx_matlab.h']]], - ['wwdg_5fcfr_5fw1_21',['WWDG_CFR_W1',['../group___peripheral___registers___bits___definition.html#ga698b68239773862647ef5f9d963b80c4',1,'stm32f407xx_matlab.h']]], - ['wwdg_5fcfr_5fw2_22',['WWDG_CFR_W2',['../group___peripheral___registers___bits___definition.html#ga166845425e89d01552bac0baeec686d9',1,'stm32f407xx_matlab.h']]], - ['wwdg_5fcfr_5fw3_23',['WWDG_CFR_W3',['../group___peripheral___registers___bits___definition.html#ga344253edc9710aa6db6047b76cce723b',1,'stm32f407xx_matlab.h']]], - ['wwdg_5fcfr_5fw4_24',['WWDG_CFR_W4',['../group___peripheral___registers___bits___definition.html#gaec3a0817a2dcde78414d02c0cb5d201d',1,'stm32f407xx_matlab.h']]], - ['wwdg_5fcfr_5fw5_25',['WWDG_CFR_W5',['../group___peripheral___registers___bits___definition.html#ga8032c21626b10fcf5cd8ad36bc051663',1,'stm32f407xx_matlab.h']]], - ['wwdg_5fcfr_5fw6_26',['WWDG_CFR_W6',['../group___peripheral___registers___bits___definition.html#ga106cdb96da03ce192628f54cefcbec2f',1,'stm32f407xx_matlab.h']]], - ['wwdg_5fcfr_5fw_5f0_27',['WWDG_CFR_W_0',['../group___peripheral___registers___bits___definition.html#ga26f4016f9990c2657acdf7521233d16d',1,'stm32f407xx_matlab.h']]], - ['wwdg_5fcfr_5fw_5f1_28',['WWDG_CFR_W_1',['../group___peripheral___registers___bits___definition.html#ga546410b3ec62e976c0f590cf9f216bb3',1,'stm32f407xx_matlab.h']]], - ['wwdg_5fcfr_5fw_5f2_29',['WWDG_CFR_W_2',['../group___peripheral___registers___bits___definition.html#gac3de841283deaea061d977392805211d',1,'stm32f407xx_matlab.h']]], - ['wwdg_5fcfr_5fw_5f3_30',['WWDG_CFR_W_3',['../group___peripheral___registers___bits___definition.html#ga0394248f2a4e4b6ba6c28024fa961a99',1,'stm32f407xx_matlab.h']]], - ['wwdg_5fcfr_5fw_5f4_31',['WWDG_CFR_W_4',['../group___peripheral___registers___bits___definition.html#ga25594b7ced3e1277b636caf02416a4e7',1,'stm32f407xx_matlab.h']]], - ['wwdg_5fcfr_5fw_5f5_32',['WWDG_CFR_W_5',['../group___peripheral___registers___bits___definition.html#ga7e730800b000f6fe3be5ea43a6e29cf9',1,'stm32f407xx_matlab.h']]], - ['wwdg_5fcfr_5fw_5f6_33',['WWDG_CFR_W_6',['../group___peripheral___registers___bits___definition.html#ga9fc25f8d5c23a76d364c1cb5d7518a17',1,'stm32f407xx_matlab.h']]], - ['wwdg_5fcfr_5fw_5fmsk_34',['WWDG_CFR_W_Msk',['../group___peripheral___registers___bits___definition.html#ga3aed21af49014ce535798f9beead136d',1,'stm32f407xx_matlab.h']]], - ['wwdg_5fcfr_5fw_5fpos_35',['WWDG_CFR_W_Pos',['../group___peripheral___registers___bits___definition.html#gae9c98c783bea6069765360fcd6df341b',1,'stm32f407xx_matlab.h']]], - ['wwdg_5fcfr_5fwdgtb_36',['WWDG_CFR_WDGTB',['../group___peripheral___registers___bits___definition.html#ga067b1d8238f1d5613481aba71a946638',1,'stm32f407xx_matlab.h']]], - ['wwdg_5fcfr_5fwdgtb0_37',['WWDG_CFR_WDGTB0',['../group___peripheral___registers___bits___definition.html#ga4858525604534e493b8a09e0b04ace61',1,'stm32f407xx_matlab.h']]], - ['wwdg_5fcfr_5fwdgtb1_38',['WWDG_CFR_WDGTB1',['../group___peripheral___registers___bits___definition.html#ga9d53e6fa74c43522ebacd6dd6f450d33',1,'stm32f407xx_matlab.h']]], - ['wwdg_5fcfr_5fwdgtb_5f0_39',['WWDG_CFR_WDGTB_0',['../group___peripheral___registers___bits___definition.html#gaab94b761166186987f91d342a5f79695',1,'stm32f407xx_matlab.h']]], - ['wwdg_5fcfr_5fwdgtb_5f1_40',['WWDG_CFR_WDGTB_1',['../group___peripheral___registers___bits___definition.html#ga9120ceb094ab327ec766a06fc66ef401',1,'stm32f407xx_matlab.h']]], - ['wwdg_5fcfr_5fwdgtb_5fmsk_41',['WWDG_CFR_WDGTB_Msk',['../group___peripheral___registers___bits___definition.html#ga627018d443463abccf249b1b848e2b64',1,'stm32f407xx_matlab.h']]], - ['wwdg_5fcfr_5fwdgtb_5fpos_42',['WWDG_CFR_WDGTB_Pos',['../group___peripheral___registers___bits___definition.html#ga496363a4b305b4aa94d9ec6c80d232f1',1,'stm32f407xx_matlab.h']]], - ['wwdg_5fcr_5ft_43',['WWDG_CR_T',['../group___peripheral___registers___bits___definition.html#ga400774feb33ed7544d57d6a0a76e0f70',1,'stm32f407xx_matlab.h']]], - ['wwdg_5fcr_5ft0_44',['WWDG_CR_T0',['../group___peripheral___registers___bits___definition.html#ga4d510237467b8e10ca1001574671ad8e',1,'stm32f407xx_matlab.h']]], - ['wwdg_5fcr_5ft1_45',['WWDG_CR_T1',['../group___peripheral___registers___bits___definition.html#gaed4b5d3f4d2e0540058fd2253a8feb95',1,'stm32f407xx_matlab.h']]], - ['wwdg_5fcr_5ft2_46',['WWDG_CR_T2',['../group___peripheral___registers___bits___definition.html#gaa4e9559da387f10bac2dc8ab0d4f6e6c',1,'stm32f407xx_matlab.h']]], - ['wwdg_5fcr_5ft3_47',['WWDG_CR_T3',['../group___peripheral___registers___bits___definition.html#gab1e344f4a12c60e57cb643511379b261',1,'stm32f407xx_matlab.h']]], - ['wwdg_5fcr_5ft4_48',['WWDG_CR_T4',['../group___peripheral___registers___bits___definition.html#gaf1f89d17eb4b3bb1b67c2b0185061e45',1,'stm32f407xx_matlab.h']]], - ['wwdg_5fcr_5ft5_49',['WWDG_CR_T5',['../group___peripheral___registers___bits___definition.html#gadc9870e0e3a5c171b9c1db817afcf0ee',1,'stm32f407xx_matlab.h']]], - ['wwdg_5fcr_5ft6_50',['WWDG_CR_T6',['../group___peripheral___registers___bits___definition.html#gab3a493575c9a7c6006a3af9d13399268',1,'stm32f407xx_matlab.h']]], - ['wwdg_5fcr_5ft_5f0_51',['WWDG_CR_T_0',['../group___peripheral___registers___bits___definition.html#ga305c0da4633020b9696d64a1785fa29c',1,'stm32f407xx_matlab.h']]], - ['wwdg_5fcr_5ft_5f1_52',['WWDG_CR_T_1',['../group___peripheral___registers___bits___definition.html#ga44e5ea3baea1e37b0446e56e910c3409',1,'stm32f407xx_matlab.h']]], - ['wwdg_5fcr_5ft_5f2_53',['WWDG_CR_T_2',['../group___peripheral___registers___bits___definition.html#ga67e7b9fa1867ecd6a9dd4b28381e4229',1,'stm32f407xx_matlab.h']]], - ['wwdg_5fcr_5ft_5f3_54',['WWDG_CR_T_3',['../group___peripheral___registers___bits___definition.html#ga64ede5bff80b5b979a44d073205f5930',1,'stm32f407xx_matlab.h']]], - ['wwdg_5fcr_5ft_5f4_55',['WWDG_CR_T_4',['../group___peripheral___registers___bits___definition.html#gabbc9c4a71473ceb1fde58a1d6054a7fe',1,'stm32f407xx_matlab.h']]], - ['wwdg_5fcr_5ft_5f5_56',['WWDG_CR_T_5',['../group___peripheral___registers___bits___definition.html#ga9f41b8c9b91c0632521373203bcb5b64',1,'stm32f407xx_matlab.h']]], - ['wwdg_5fcr_5ft_5f6_57',['WWDG_CR_T_6',['../group___peripheral___registers___bits___definition.html#ga8abc0d44e390aabc2c7f787f2ed0b632',1,'stm32f407xx_matlab.h']]], - ['wwdg_5fcr_5ft_5fmsk_58',['WWDG_CR_T_Msk',['../group___peripheral___registers___bits___definition.html#gaa8676c7d294b92a9ea0d0f1b088308ed',1,'stm32f407xx_matlab.h']]], - ['wwdg_5fcr_5ft_5fpos_59',['WWDG_CR_T_Pos',['../group___peripheral___registers___bits___definition.html#ga1a1da6274cc0fb20e75dfbe1a20ab62e',1,'stm32f407xx_matlab.h']]], - ['wwdg_5fcr_5fwdga_60',['WWDG_CR_WDGA',['../group___peripheral___registers___bits___definition.html#gab647e9997b8b8e67de72af1aaea3f52f',1,'stm32f407xx_matlab.h']]], - ['wwdg_5fcr_5fwdga_5fmsk_61',['WWDG_CR_WDGA_Msk',['../group___peripheral___registers___bits___definition.html#ga06bd586be3859790f803c1275ea52390',1,'stm32f407xx_matlab.h']]], - ['wwdg_5fcr_5fwdga_5fpos_62',['WWDG_CR_WDGA_Pos',['../group___peripheral___registers___bits___definition.html#ga51b9fed94bc5fdbc67446173e1b3676c',1,'stm32f407xx_matlab.h']]], - ['wwdg_5firqn_63',['WWDG_IRQn',['../group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a971089d7566ef902dfa0c80ac3a8fd52',1,'stm32f407xx_matlab.h']]], - ['wwdg_5fsr_5fewif_64',['WWDG_SR_EWIF',['../group___peripheral___registers___bits___definition.html#ga96cf9ddd91b6079c5aceef6f3e857b69',1,'stm32f407xx_matlab.h']]], - ['wwdg_5fsr_5fewif_5fmsk_65',['WWDG_SR_EWIF_Msk',['../group___peripheral___registers___bits___definition.html#ga284cdb5e7c17598a03a9a0790dd7508c',1,'stm32f407xx_matlab.h']]], - ['wwdg_5fsr_5fewif_5fpos_66',['WWDG_SR_EWIF_Pos',['../group___peripheral___registers___bits___definition.html#gac4c37d2819f82d4cec6c8c9a9250ee43',1,'stm32f407xx_matlab.h']]], - ['wwdg_5ftypedef_67',['WWDG_TypeDef',['../struct_w_w_d_g___type_def.html',1,'']]] + ['как_20запуÑтить_20отладку_0',['Как запуÑтить отладку',['../index.html#как-запуÑтить-отладку',1,'']]], + ['как_20Ñкомпилировать_20код_1',['Как Ñкомпилировать код',['../index.html#как-Ñкомпилировать-код',1,'']]], + ['кода_2',['Портирование кода',['../index.html#портирование-кода',1,'']]], + ['код_3',['Как Ñкомпилировать код',['../index.html#как-Ñкомпилировать-код',1,'']]], + ['код_20пользователÑ_4',['Код пользователÑ',['../index.html#код-пользователÑ',1,'']]], + ['компилÑции_5',['Ошибки при компилÑции',['../index.html#ошибки-при-компилÑции',1,'']]] ]; diff --git a/DOCS/html/search/all_18.js b/DOCS/html/search/all_18.js index 6aac8b8..7eec7cf 100644 --- a/DOCS/html/search/all_18.js +++ b/DOCS/html/search/all_18.js @@ -1,24 +1,4 @@ var searchData= [ - ['xpsr_5fc_5fmsk_0',['xPSR_C_Msk',['../group___c_m_s_i_s___c_o_r_e.html#ga21e2497255d380f956ca0f48d11d0775',1,'core_cm4_matlab.h']]], - ['xpsr_5fc_5fpos_1',['xPSR_C_Pos',['../group___c_m_s_i_s___c_o_r_e.html#ga14adb79b91f6634b351a1b57394e2db6',1,'core_cm4_matlab.h']]], - ['xpsr_5fge_5fmsk_2',['xPSR_GE_Msk',['../group___c_m_s_i_s___c_o_r_e.html#ga967634e605d013e9b07002eca31f7903',1,'core_cm4_matlab.h']]], - ['xpsr_5fge_5fpos_3',['xPSR_GE_Pos',['../group___c_m_s_i_s___c_o_r_e.html#gae2b0f3def0f378e9f1d10a4c727a064b',1,'core_cm4_matlab.h']]], - ['xpsr_5fici_5fit_5f1_5fmsk_4',['xPSR_ICI_IT_1_Msk',['../group___c_m_s_i_s___c_o_r_e.html#gae98918458d70d79b32ce200b55ffe744',1,'core_cm4_matlab.h']]], - ['xpsr_5fici_5fit_5f1_5fpos_5',['xPSR_ICI_IT_1_Pos',['../group___c_m_s_i_s___c_o_r_e.html#gafdcd08cbd7116d65ae1a5b8182dc55ae',1,'core_cm4_matlab.h']]], - ['xpsr_5fici_5fit_5f2_5fmsk_6',['xPSR_ICI_IT_2_Msk',['../group___c_m_s_i_s___c_o_r_e.html#gaa47c89b028499f8d9ebe6d554439a2b3',1,'core_cm4_matlab.h']]], - ['xpsr_5fici_5fit_5f2_5fpos_7',['xPSR_ICI_IT_2_Pos',['../group___c_m_s_i_s___c_o_r_e.html#gaffb36d1bb0280b1caafcf9b00f6a6da0',1,'core_cm4_matlab.h']]], - ['xpsr_5fisr_5fmsk_8',['xPSR_ISR_Msk',['../group___c_m_s_i_s___c_o_r_e.html#gadf8eed87e0081dfe1ef1c78a0ea91afd',1,'core_cm4_matlab.h']]], - ['xpsr_5fisr_5fpos_9',['xPSR_ISR_Pos',['../group___c_m_s_i_s___c_o_r_e.html#ga21bff245fb1aef9683f693d9d7bb2233',1,'core_cm4_matlab.h']]], - ['xpsr_5fn_5fmsk_10',['xPSR_N_Msk',['../group___c_m_s_i_s___c_o_r_e.html#gaf600f4ff41b62cf2f3b0a59b6d2e93d6',1,'core_cm4_matlab.h']]], - ['xpsr_5fn_5fpos_11',['xPSR_N_Pos',['../group___c_m_s_i_s___c_o_r_e.html#ga031eb1b8ebcdb3d602d0b9f2ec82a7ae',1,'core_cm4_matlab.h']]], - ['xpsr_5fq_5fmsk_12',['xPSR_Q_Msk',['../group___c_m_s_i_s___c_o_r_e.html#ga133ac393c38559ae43ac36383e731dd4',1,'core_cm4_matlab.h']]], - ['xpsr_5fq_5fpos_13',['xPSR_Q_Pos',['../group___c_m_s_i_s___c_o_r_e.html#gaabb4178d50676a8f19cf8f727f38ace8',1,'core_cm4_matlab.h']]], - ['xpsr_5ft_5fmsk_14',['xPSR_T_Msk',['../group___c_m_s_i_s___c_o_r_e.html#ga30ae2111816e82d47636a8d4577eb6ee',1,'core_cm4_matlab.h']]], - ['xpsr_5ft_5fpos_15',['xPSR_T_Pos',['../group___c_m_s_i_s___c_o_r_e.html#ga98d801da9a49cda944f52aeae104dd38',1,'core_cm4_matlab.h']]], - ['xpsr_5ftype_16',['xPSR_Type',['../unionx_p_s_r___type.html',1,'']]], - ['xpsr_5fv_5fmsk_17',['xPSR_V_Msk',['../group___c_m_s_i_s___c_o_r_e.html#gab07f94ed3b6ee695f5af719dc27995c2',1,'core_cm4_matlab.h']]], - ['xpsr_5fv_5fpos_18',['xPSR_V_Pos',['../group___c_m_s_i_s___c_o_r_e.html#gae0cfbb394490db402623d97e6a979e00',1,'core_cm4_matlab.h']]], - ['xpsr_5fz_5fmsk_19',['xPSR_Z_Msk',['../group___c_m_s_i_s___c_o_r_e.html#ga907599209fba99f579778e662021c4f2',1,'core_cm4_matlab.h']]], - ['xpsr_5fz_5fpos_20',['xPSR_Z_Pos',['../group___c_m_s_i_s___c_o_r_e.html#ga5869dd608eea73c80f0567d781d2230b',1,'core_cm4_matlab.h']]] + ['мк_0',['Оболочка МК',['../index.html#оболочка-мк',1,'']]] ]; diff --git a/DOCS/html/search/all_19.js b/DOCS/html/search/all_19.js index da6bf00..531c420 100644 --- a/DOCS/html/search/all_19.js +++ b/DOCS/html/search/all_19.js @@ -1,4 +1,10 @@ var searchData= [ - ['z_0',['Z',['../group___c_m_s_i_s__core___debug_functions.html#ga5ae954cbd9986cd64625d7fa00943c8e',1,'APSR_Type::Z'],['../group___c_m_s_i_s__core___debug_functions.html#ga5ae954cbd9986cd64625d7fa00943c8e',1,'APSR_Type::@0::Z'],['../group___c_m_s_i_s__core___debug_functions.html#ga5ae954cbd9986cd64625d7fa00943c8e',1,'xPSR_Type::Z'],['../group___c_m_s_i_s__core___debug_functions.html#ga5ae954cbd9986cd64625d7fa00943c8e',1,'xPSR_Type::@2::Z']]] + ['оболочка_20мк_0',['Оболочка МК',['../index.html#оболочка-мк',1,'']]], + ['общаÑ_20Ñтруктура_20ÑмулÑтора_1',['ÐžÐ±Ñ‰Ð°Ñ Ñтруктура ÑмулÑтора',['../index.html#общаÑ-Ñтруктура-ÑмулÑтора',1,'']]], + ['опиÑание_20Ñтуктуры_20ÑмулÑтора_20пример_20длÑ_20stm32_2',['ОпиÑание Ñтуктуры ÑмулÑтора (пример Ð´Ð»Ñ STM32)',['../index.html#опиÑание-Ñтуктуры-ÑмулÑтора-пример-длÑ-stm32',1,'']]], + ['отладку_3',['Как запуÑтить отладку',['../index.html#как-запуÑтить-отладку',1,'']]], + ['ошибки_4',['Ошибки',['../index.html#ошибки',1,'']]], + ['ошибки_20при_20компилÑции_5',['Ошибки при компилÑции',['../index.html#ошибки-при-компилÑции',1,'']]], + ['ошибки_20при_20ÑимулÑции_6',['Ошибки при ÑимулÑции',['../index.html#ошибки-при-ÑимулÑции',1,'']]] ]; diff --git a/DOCS/html/search/all_1a.js b/DOCS/html/search/all_1a.js index 723400e..0de802b 100644 --- a/DOCS/html/search/all_1a.js +++ b/DOCS/html/search/all_1a.js @@ -1,5 +1,8 @@ var searchData= [ - ['длÑ_20matlab_0',['ЭмулÑтор STM Ð´Ð»Ñ MATLAB',['../md__f_1_2_work_2_projects_2_m_a_t_l_a_b_2matlab__stm__emulate_2_r_e_a_d_m_e.html#autotoc_md4',1,'']]], - ['длÑ_20stm32_1',['ОпиÑание Ñтуктуры ÑмулÑтора (пример Ð´Ð»Ñ STM32)',['../md__f_1_2_work_2_projects_2_m_a_t_l_a_b_2matlab__stm__emulate_2_r_e_a_d_m_e.html#autotoc_md2',1,'']]] + ['пользователÑ_0',['Код пользователÑ',['../index.html#код-пользователÑ',1,'']]], + ['портирование_20кода_1',['Портирование кода',['../index.html#портирование-кода',1,'']]], + ['пример_20длÑ_20stm32_2',['ОпиÑание Ñтуктуры ÑмулÑтора (пример Ð´Ð»Ñ STM32)',['../index.html#опиÑание-Ñтуктуры-ÑмулÑтора-пример-длÑ-stm32',1,'']]], + ['при_20компилÑции_3',['Ошибки при компилÑции',['../index.html#ошибки-при-компилÑции',1,'']]], + ['при_20ÑимулÑции_4',['Ошибки при ÑимулÑции',['../index.html#ошибки-при-ÑимулÑции',1,'']]] ]; diff --git a/DOCS/html/search/all_1b.js b/DOCS/html/search/all_1b.js index 8767121..3717725 100644 --- a/DOCS/html/search/all_1b.js +++ b/DOCS/html/search/all_1b.js @@ -1,4 +1,7 @@ var searchData= [ - ['запуÑтить_20отладку_0',['Как запуÑтить отладку',['../md__f_1_2_work_2_projects_2_m_a_t_l_a_b_2matlab__stm__emulate_2_r_e_a_d_m_e.html#autotoc_md9',1,'']]] + ['ÑимулÑции_0',['Ошибки при ÑимулÑции',['../index.html#ошибки-при-ÑимулÑции',1,'']]], + ['Ñкомпилировать_20код_1',['Как Ñкомпилировать код',['../index.html#как-Ñкомпилировать-код',1,'']]], + ['Ñтруктура_20ÑмулÑтора_2',['ÐžÐ±Ñ‰Ð°Ñ Ñтруктура ÑмулÑтора',['../index.html#общаÑ-Ñтруктура-ÑмулÑтора',1,'']]], + ['Ñтуктуры_20ÑмулÑтора_20пример_20длÑ_20stm32_3',['ОпиÑание Ñтуктуры ÑмулÑтора (пример Ð´Ð»Ñ STM32)',['../index.html#опиÑание-Ñтуктуры-ÑмулÑтора-пример-длÑ-stm32',1,'']]] ]; diff --git a/DOCS/html/search/all_1c.js b/DOCS/html/search/all_1c.js index 96e5dc5..744f970 100644 --- a/DOCS/html/search/all_1c.js +++ b/DOCS/html/search/all_1c.js @@ -1,4 +1,6 @@ var searchData= [ - ['инÑтрукциÑ_0',['ИнÑтрукциÑ',['../md__f_1_2_work_2_projects_2_m_a_t_l_a_b_2matlab__stm__emulate_2_r_e_a_d_m_e.html#autotoc_md6',1,'']]] + ['ÑмулÑтора_0',['ÐžÐ±Ñ‰Ð°Ñ Ñтруктура ÑмулÑтора',['../index.html#общаÑ-Ñтруктура-ÑмулÑтора',1,'']]], + ['ÑмулÑтора_20пример_20длÑ_20stm32_1',['ОпиÑание Ñтуктуры ÑмулÑтора (пример Ð´Ð»Ñ STM32)',['../index.html#опиÑание-Ñтуктуры-ÑмулÑтора-пример-длÑ-stm32',1,'']]], + ['ÑмулÑтор_20stm_20длÑ_20matlab_2',['ЭмулÑтор STM Ð´Ð»Ñ MATLAB',['../index.html#ÑмулÑтор-stm-длÑ-matlab',1,'']]] ]; diff --git a/DOCS/html/search/all_1d.js b/DOCS/html/search/all_1d.js deleted file mode 100644 index 11f1784..0000000 --- a/DOCS/html/search/all_1d.js +++ /dev/null @@ -1,9 +0,0 @@ -var searchData= -[ - ['как_20запуÑтить_20отладку_0',['Как запуÑтить отладку',['../md__f_1_2_work_2_projects_2_m_a_t_l_a_b_2matlab__stm__emulate_2_r_e_a_d_m_e.html#autotoc_md9',1,'']]], - ['как_20Ñкомпилировать_20код_1',['Как Ñкомпилировать код',['../md__f_1_2_work_2_projects_2_m_a_t_l_a_b_2matlab__stm__emulate_2_r_e_a_d_m_e.html#autotoc_md8',1,'']]], - ['кода_2',['Портирование кода',['../md__f_1_2_work_2_projects_2_m_a_t_l_a_b_2matlab__stm__emulate_2_r_e_a_d_m_e.html#autotoc_md7',1,'']]], - ['код_3',['Как Ñкомпилировать код',['../md__f_1_2_work_2_projects_2_m_a_t_l_a_b_2matlab__stm__emulate_2_r_e_a_d_m_e.html#autotoc_md8',1,'']]], - ['код_20пользователÑ_4',['Код пользователÑ',['../md__f_1_2_work_2_projects_2_m_a_t_l_a_b_2matlab__stm__emulate_2_r_e_a_d_m_e.html#autotoc_md5',1,'']]], - ['компилÑции_5',['Ошибки при компилÑции',['../md__f_1_2_work_2_projects_2_m_a_t_l_a_b_2matlab__stm__emulate_2_r_e_a_d_m_e.html#autotoc_md11',1,'']]] -]; diff --git a/DOCS/html/search/all_1e.js b/DOCS/html/search/all_1e.js deleted file mode 100644 index 08a19b8..0000000 --- a/DOCS/html/search/all_1e.js +++ /dev/null @@ -1,4 +0,0 @@ -var searchData= -[ - ['мк_0',['Оболочка МК',['../md__f_1_2_work_2_projects_2_m_a_t_l_a_b_2matlab__stm__emulate_2_r_e_a_d_m_e.html#autotoc_md3',1,'']]] -]; diff --git a/DOCS/html/search/all_1f.js b/DOCS/html/search/all_1f.js deleted file mode 100644 index a32689e..0000000 --- a/DOCS/html/search/all_1f.js +++ /dev/null @@ -1,10 +0,0 @@ -var searchData= -[ - ['оболочка_20мк_0',['Оболочка МК',['../md__f_1_2_work_2_projects_2_m_a_t_l_a_b_2matlab__stm__emulate_2_r_e_a_d_m_e.html#autotoc_md3',1,'']]], - ['общаÑ_20Ñтруктура_20ÑмулÑтора_1',['ÐžÐ±Ñ‰Ð°Ñ Ñтруктура ÑмулÑтора',['../md__f_1_2_work_2_projects_2_m_a_t_l_a_b_2matlab__stm__emulate_2_r_e_a_d_m_e.html#autotoc_md1',1,'']]], - ['опиÑание_20Ñтуктуры_20ÑмулÑтора_20пример_20длÑ_20stm32_2',['ОпиÑание Ñтуктуры ÑмулÑтора (пример Ð´Ð»Ñ STM32)',['../md__f_1_2_work_2_projects_2_m_a_t_l_a_b_2matlab__stm__emulate_2_r_e_a_d_m_e.html#autotoc_md2',1,'']]], - ['отладку_3',['Как запуÑтить отладку',['../md__f_1_2_work_2_projects_2_m_a_t_l_a_b_2matlab__stm__emulate_2_r_e_a_d_m_e.html#autotoc_md9',1,'']]], - ['ошибки_4',['Ошибки',['../md__f_1_2_work_2_projects_2_m_a_t_l_a_b_2matlab__stm__emulate_2_r_e_a_d_m_e.html#autotoc_md10',1,'']]], - ['ошибки_20при_20компилÑции_5',['Ошибки при компилÑции',['../md__f_1_2_work_2_projects_2_m_a_t_l_a_b_2matlab__stm__emulate_2_r_e_a_d_m_e.html#autotoc_md11',1,'']]], - ['ошибки_20при_20ÑимулÑции_6',['Ошибки при ÑимулÑции',['../md__f_1_2_work_2_projects_2_m_a_t_l_a_b_2matlab__stm__emulate_2_r_e_a_d_m_e.html#autotoc_md12',1,'']]] -]; diff --git a/DOCS/html/search/all_2.js b/DOCS/html/search/all_2.js index 4e27977..cc550bb 100644 --- a/DOCS/html/search/all_2.js +++ b/DOCS/html/search/all_2.js @@ -1,40 +1,8 @@ var searchData= [ - ['b_0',['b',['../group___c_m_s_i_s__core___debug_functions.html#ga84de5f534817cdbf8bd9064080effca2',1,'APSR_Type::b'],['../group___c_m_s_i_s__core___debug_functions.html#ga6e920e9d2e9a2738f8face0863888c0e',1,'IPSR_Type::b'],['../group___c_m_s_i_s__core___debug_functions.html#ga61873807b9abee3dfa090c036e580d2e',1,'xPSR_Type::b'],['../group___c_m_s_i_s__core___debug_functions.html#ga5d690aa9e65fccaa320e1b8613f502c9',1,'CONTROL_Type::b']]], - ['bdcr_1',['BDCR',['../group___c_m_s_i_s___device.html#ga0b9a3ced775287c8585a6a61af4b40e9',1,'RCC_TypeDef']]], - ['bdtr_2',['BDTR',['../group___c_m_s_i_s___device.html#ga476bae602205d6a49c7e71e2bda28c0a',1,'TIM_TypeDef']]], - ['bfar_3',['BFAR',['../group___c_m_s_i_s__core___debug_functions.html#ga3fde073744418e2fe476333cb4d55d0d',1,'SCB_Type']]], - ['bit_20field_20macros_4',['Core register bit field macros',['../group___c_m_s_i_s__core__bitfield.html',1,'']]], - ['bkp0r_5',['BKP0R',['../group___c_m_s_i_s___device.html#ga4808ec597e5a5fefd8a83a9127dd1aec',1,'RTC_TypeDef']]], - ['bkp10r_6',['BKP10R',['../group___c_m_s_i_s___device.html#gaade2881a3e408bfd106b27f78bbbcfc9',1,'RTC_TypeDef']]], - ['bkp11r_7',['BKP11R',['../group___c_m_s_i_s___device.html#gac66d5e2d3459cff89794c47dbc8f7228',1,'RTC_TypeDef']]], - ['bkp12r_8',['BKP12R',['../group___c_m_s_i_s___device.html#ga6f7eee5ae8a32c07f9c8fe14281bdaf3',1,'RTC_TypeDef']]], - ['bkp13r_9',['BKP13R',['../group___c_m_s_i_s___device.html#ga6ed4c3a0d4588a75078e9f8e376b4d06',1,'RTC_TypeDef']]], - ['bkp14r_10',['BKP14R',['../group___c_m_s_i_s___device.html#gac60f13e6619724747e61cfbff55b9fab',1,'RTC_TypeDef']]], - ['bkp15r_11',['BKP15R',['../group___c_m_s_i_s___device.html#gafafaddc3a983eb71332b7526d82191ad',1,'RTC_TypeDef']]], - ['bkp16r_12',['BKP16R',['../group___c_m_s_i_s___device.html#gad2f2eb2fb4b93e21515b10e920e719b6',1,'RTC_TypeDef']]], - ['bkp17r_13',['BKP17R',['../group___c_m_s_i_s___device.html#ga2842aa523df62f3508316eb3b2e08f4e',1,'RTC_TypeDef']]], - ['bkp18r_14',['BKP18R',['../group___c_m_s_i_s___device.html#ga640ccb2ccfb6316b88c070362dc29339',1,'RTC_TypeDef']]], - ['bkp19r_15',['BKP19R',['../group___c_m_s_i_s___device.html#ga4ec1dd54d976989b7c9e59fb14d974fb',1,'RTC_TypeDef']]], - ['bkp1r_16',['BKP1R',['../group___c_m_s_i_s___device.html#gaf85290529fb82acef7c9fcea3718346c',1,'RTC_TypeDef']]], - ['bkp2r_17',['BKP2R',['../group___c_m_s_i_s___device.html#gaaa251a80daa57ad0bd7db75cb3b9cdec',1,'RTC_TypeDef']]], - ['bkp3r_18',['BKP3R',['../group___c_m_s_i_s___device.html#ga0b1eeda834c3cfd4d2c67f242f7b2a1c',1,'RTC_TypeDef']]], - ['bkp4r_19',['BKP4R',['../group___c_m_s_i_s___device.html#gab13e106cc2eca92d1f4022df3bfdbcd7',1,'RTC_TypeDef']]], - ['bkp5r_20',['BKP5R',['../group___c_m_s_i_s___device.html#gab6bed862c0d0476ff4f89f7b9bf3e130',1,'RTC_TypeDef']]], - ['bkp6r_21',['BKP6R',['../group___c_m_s_i_s___device.html#ga1d854d2d7f0452f4c90035952b92d2ba',1,'RTC_TypeDef']]], - ['bkp7r_22',['BKP7R',['../group___c_m_s_i_s___device.html#ga2ca54ce1a8d2fa9d1ba6d5987ed5e2cf',1,'RTC_TypeDef']]], - ['bkp8r_23',['BKP8R',['../group___c_m_s_i_s___device.html#gac1085f6aae54b353c30871fe90c59851',1,'RTC_TypeDef']]], - ['bkp9r_24',['BKP9R',['../group___c_m_s_i_s___device.html#ga6c33564df6eaf97400e0457dde9b14ef',1,'RTC_TypeDef']]], - ['bkpsram_5fbase_25',['BKPSRAM_BASE',['../group___c_m_s_i_s___device.html#gae20eaf17d134d9c2136072bca05f36c0',1,'_memory::BKPSRAM_BASE'],['../group___peripheral__memory__map.html#ga52e57051bdf8909222b36e5408a48f32',1,'BKPSRAM_BASE: stm32f407xx_matlab.h']]], - ['bkpsram_5fbase_5fshift_26',['BKPSRAM_BASE_SHIFT',['../group___peripheral__memory__map.html#gabac8d912551188d0039d016d16f7c0b0',1,'stm32f407xx_matlab.h']]], - ['bkpsram_5fbb_5fbase_27',['BKPSRAM_BB_BASE',['../group___c_m_s_i_s___device.html#ga90eb3fc2642288d3e7ca2416493bf8ae',1,'_memory::BKPSRAM_BB_BASE'],['../group___peripheral__memory__map.html#gaee19a30c9fa326bb10b547e4eaf4e250',1,'BKPSRAM_BB_BASE: stm32f407xx_matlab.h']]], - ['bkpsram_5fbb_5fbase_5fshift_28',['BKPSRAM_BB_BASE_SHIFT',['../group___peripheral__memory__map.html#gaa850b97b5338b2a9891acbf23788fd14',1,'stm32f407xx_matlab.h']]], - ['bkpsram_5fsize_29',['BKPSRAM_SIZE',['../group___peripheral__memory__map.html#gafe7470549838cd29d6f2d7245f17176c',1,'stm32f407xx_matlab.h']]], - ['block_20scb_30',['System Control Block (SCB)',['../group___c_m_s_i_s___s_c_b.html',1,'']]], - ['brr_31',['BRR',['../group___c_m_s_i_s___device.html#ga092e59d908b2ca112e31047e942340cb',1,'USART_TypeDef']]], - ['bsrr_32',['BSRR',['../group___c_m_s_i_s___device.html#gac25dd6b9e3d55e17589195b461c5ec80',1,'GPIO_TypeDef']]], - ['btcr_33',['BTCR',['../group___c_m_s_i_s___device.html#ga80a6708b507f6eecbc10424fdb088b79',1,'FSMC_Bank1_TypeDef']]], - ['btr_34',['BTR',['../group___c_m_s_i_s___device.html#ga5c0fcd3e7b4c59ab1dd68f6bd8f74e07',1,'CAN_TypeDef']]], - ['busfault_5firqn_35',['BusFault_IRQn',['../group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a8693500eff174f16119e96234fee73af',1,'stm32f407xx_matlab.h']]], - ['bwtr_36',['BWTR',['../group___c_m_s_i_s___device.html#ga20f13b79c0f8670af319af0c5ebd5c91',1,'FSMC_Bank1E_TypeDef']]] + ['bkpsram_5fbase_0',['BKPSRAM_BASE',['../struct__memory.html#ae20eaf17d134d9c2136072bca05f36c0',1,'_memory::BKPSRAM_BASE'],['../group___peripheral__memory__map.html#ga52e57051bdf8909222b36e5408a48f32',1,'BKPSRAM_BASE: stm32f407xx_matlab_memory.h']]], + ['bkpsram_5fbase_5fshift_1',['BKPSRAM_BASE_SHIFT',['../group___peripheral__memory__map.html#gabac8d912551188d0039d016d16f7c0b0',1,'stm32f407xx_matlab_memory.h']]], + ['bkpsram_5fbb_5fbase_2',['BKPSRAM_BB_BASE',['../struct__memory.html#a90eb3fc2642288d3e7ca2416493bf8ae',1,'_memory::BKPSRAM_BB_BASE'],['../group___peripheral__memory__map.html#gaee19a30c9fa326bb10b547e4eaf4e250',1,'BKPSRAM_BB_BASE: stm32f407xx_matlab_memory.h']]], + ['bkpsram_5fbb_5fbase_5fshift_3',['BKPSRAM_BB_BASE_SHIFT',['../group___peripheral__memory__map.html#gaa850b97b5338b2a9891acbf23788fd14',1,'stm32f407xx_matlab_memory.h']]], + ['bkpsram_5fsize_4',['BKPSRAM_SIZE',['../group___peripheral__memory__map.html#gafe7470549838cd29d6f2d7245f17176c',1,'stm32f407xx_matlab_memory.h']]] ]; diff --git a/DOCS/html/search/all_20.js b/DOCS/html/search/all_20.js deleted file mode 100644 index 4ca3372..0000000 --- a/DOCS/html/search/all_20.js +++ /dev/null @@ -1,8 +0,0 @@ -var searchData= -[ - ['пользователÑ_0',['Код пользователÑ',['../md__f_1_2_work_2_projects_2_m_a_t_l_a_b_2matlab__stm__emulate_2_r_e_a_d_m_e.html#autotoc_md5',1,'']]], - ['портирование_20кода_1',['Портирование кода',['../md__f_1_2_work_2_projects_2_m_a_t_l_a_b_2matlab__stm__emulate_2_r_e_a_d_m_e.html#autotoc_md7',1,'']]], - ['пример_20длÑ_20stm32_2',['ОпиÑание Ñтуктуры ÑмулÑтора (пример Ð´Ð»Ñ STM32)',['../md__f_1_2_work_2_projects_2_m_a_t_l_a_b_2matlab__stm__emulate_2_r_e_a_d_m_e.html#autotoc_md2',1,'']]], - ['при_20компилÑции_3',['Ошибки при компилÑции',['../md__f_1_2_work_2_projects_2_m_a_t_l_a_b_2matlab__stm__emulate_2_r_e_a_d_m_e.html#autotoc_md11',1,'']]], - ['при_20ÑимулÑции_4',['Ошибки при ÑимулÑции',['../md__f_1_2_work_2_projects_2_m_a_t_l_a_b_2matlab__stm__emulate_2_r_e_a_d_m_e.html#autotoc_md12',1,'']]] -]; diff --git a/DOCS/html/search/all_21.js b/DOCS/html/search/all_21.js deleted file mode 100644 index b23d487..0000000 --- a/DOCS/html/search/all_21.js +++ /dev/null @@ -1,7 +0,0 @@ -var searchData= -[ - ['ÑимулÑции_0',['Ошибки при ÑимулÑции',['../md__f_1_2_work_2_projects_2_m_a_t_l_a_b_2matlab__stm__emulate_2_r_e_a_d_m_e.html#autotoc_md12',1,'']]], - ['Ñкомпилировать_20код_1',['Как Ñкомпилировать код',['../md__f_1_2_work_2_projects_2_m_a_t_l_a_b_2matlab__stm__emulate_2_r_e_a_d_m_e.html#autotoc_md8',1,'']]], - ['Ñтруктура_20ÑмулÑтора_2',['ÐžÐ±Ñ‰Ð°Ñ Ñтруктура ÑмулÑтора',['../md__f_1_2_work_2_projects_2_m_a_t_l_a_b_2matlab__stm__emulate_2_r_e_a_d_m_e.html#autotoc_md1',1,'']]], - ['Ñтуктуры_20ÑмулÑтора_20пример_20длÑ_20stm32_3',['ОпиÑание Ñтуктуры ÑмулÑтора (пример Ð´Ð»Ñ STM32)',['../md__f_1_2_work_2_projects_2_m_a_t_l_a_b_2matlab__stm__emulate_2_r_e_a_d_m_e.html#autotoc_md2',1,'']]] -]; diff --git a/DOCS/html/search/all_22.js b/DOCS/html/search/all_22.js deleted file mode 100644 index efd4657..0000000 --- a/DOCS/html/search/all_22.js +++ /dev/null @@ -1,6 +0,0 @@ -var searchData= -[ - ['ÑмулÑтора_0',['ÐžÐ±Ñ‰Ð°Ñ Ñтруктура ÑмулÑтора',['../md__f_1_2_work_2_projects_2_m_a_t_l_a_b_2matlab__stm__emulate_2_r_e_a_d_m_e.html#autotoc_md1',1,'']]], - ['ÑмулÑтора_20пример_20длÑ_20stm32_1',['ОпиÑание Ñтуктуры ÑмулÑтора (пример Ð´Ð»Ñ STM32)',['../md__f_1_2_work_2_projects_2_m_a_t_l_a_b_2matlab__stm__emulate_2_r_e_a_d_m_e.html#autotoc_md2',1,'']]], - ['ÑмулÑтор_20stm_20длÑ_20matlab_2',['ЭмулÑтор STM Ð´Ð»Ñ MATLAB',['../md__f_1_2_work_2_projects_2_m_a_t_l_a_b_2matlab__stm__emulate_2_r_e_a_d_m_e.html#autotoc_md4',1,'']]] -]; diff --git a/DOCS/html/search/all_3.js b/DOCS/html/search/all_3.js index a760c67..e8bdbb8 100644 --- a/DOCS/html/search/all_3.js +++ b/DOCS/html/search/all_3.js @@ -1,3699 +1,31 @@ var searchData= [ - ['c_0',['C',['../group___c_m_s_i_s__core___debug_functions.html#ga7a1caf92f32fe9ebd8d1fe89b06c7776',1,'APSR_Type::C'],['../group___c_m_s_i_s__core___debug_functions.html#ga7a1caf92f32fe9ebd8d1fe89b06c7776',1,'APSR_Type::@0::C'],['../group___c_m_s_i_s__core___debug_functions.html#ga7a1caf92f32fe9ebd8d1fe89b06c7776',1,'xPSR_Type::C'],['../group___c_m_s_i_s__core___debug_functions.html#ga7a1caf92f32fe9ebd8d1fe89b06c7776',1,'xPSR_Type::@2::C']]], - ['calib_1',['CALIB',['../group___c_m_s_i_s__core___debug_functions.html#gaedf0dff29a9cacdaa2fb7eec6b116a13',1,'SysTick_Type']]], - ['calibr_2',['CALIBR',['../group___c_m_s_i_s___device.html#gab97f3e9584dda705dc10a5f4c5f6e636',1,'RTC_TypeDef']]], - ['call_5firqhandller_3',['call_IRQHandller',['../group___t_i_m___s_i_m_u_l_a_t_o_r.html#gaa2b3ab4507a894ffa6e4487d42054e67',1,'call_IRQHandller(TIM_TypeDef *TIMx): stm32f4xx_matlab_tim.c'],['../group___t_i_m___s_i_m_u_l_a_t_o_r.html#gaa2b3ab4507a894ffa6e4487d42054e67',1,'call_IRQHandller(TIM_TypeDef *TIMx): stm32f4xx_matlab_tim.c']]], - ['calr_4',['CALR',['../group___c_m_s_i_s___device.html#ga2ce7c3842792c506635bb87a21588b58',1,'RTC_TypeDef']]], - ['can1_5',['CAN1',['../group___peripheral__declaration.html#ga4964ecb6a5c689aaf8ee2832b8093aac',1,'stm32f407xx_matlab.h']]], - ['can1_6',['can1',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga047c365ed69ab08e79c499adcedff87b',1,'stm32f4xx_periph_registers.c']]], - ['can1_5fbase_7',['CAN1_BASE',['../group___peripheral__memory__map.html#gad8e45ea6c032d9fce1b0516fff9d8eaa',1,'stm32f407xx_matlab.h']]], - ['can1_5frx0_5firqn_8',['CAN1_RX0_IRQn',['../group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8ab6bf73ac43a9856b3f2759a59f3d25b5',1,'stm32f407xx_matlab.h']]], - ['can1_5frx1_5firqn_9',['CAN1_RX1_IRQn',['../group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8af71ef06c4f9ff0e1691c21ff3670acd4',1,'stm32f407xx_matlab.h']]], - ['can1_5fsce_5firqn_10',['CAN1_SCE_IRQn',['../group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a0f5f129d88a5606a378811e43039e274',1,'stm32f407xx_matlab.h']]], - ['can1_5ftx_5firqn_11',['CAN1_TX_IRQn',['../group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a9ceb5175f7c10cf436955173c2246877',1,'stm32f407xx_matlab.h']]], - ['can2_12',['can2',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#gae4b5c771c41468ea4ffa1af4de9ce39e',1,'stm32f4xx_periph_registers.c']]], - ['can2_13',['CAN2',['../group___peripheral__declaration.html#gac5e4c86ed487dc91418b156e24808033',1,'stm32f407xx_matlab.h']]], - ['can2_5fbase_14',['CAN2_BASE',['../group___peripheral__memory__map.html#gaf7b8267b0d439f8f3e82f86be4b9fba1',1,'stm32f407xx_matlab.h']]], - ['can2_5frx0_5firqn_15',['CAN2_RX0_IRQn',['../group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a851fd2f2ab1418710e7da80e1bdf348a',1,'stm32f407xx_matlab.h']]], - ['can2_5frx1_5firqn_16',['CAN2_RX1_IRQn',['../group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8ab5023ff845be31a488ab63a0b8cf2b7a',1,'stm32f407xx_matlab.h']]], - ['can2_5fsce_5firqn_17',['CAN2_SCE_IRQn',['../group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a56c0b5758f26f31494e74aab9273f9fd',1,'stm32f407xx_matlab.h']]], - ['can2_5ftx_5firqn_18',['CAN2_TX_IRQn',['../group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8af6b8fbc990ac71c8425647bb684788a4',1,'stm32f407xx_matlab.h']]], - ['can_5fbtr_5fbrp_19',['CAN_BTR_BRP',['../group___peripheral___registers___bits___definition.html#ga96a5522b4c06551856f7185bdd448b02',1,'stm32f407xx_matlab.h']]], - ['can_5fbtr_5fbrp_5fmsk_20',['CAN_BTR_BRP_Msk',['../group___peripheral___registers___bits___definition.html#gad530ac34faa377b770d56624f009934d',1,'stm32f407xx_matlab.h']]], - ['can_5fbtr_5fbrp_5fpos_21',['CAN_BTR_BRP_Pos',['../group___peripheral___registers___bits___definition.html#gac3a0f2dc6767c5297f2f3475fdea8bef',1,'stm32f407xx_matlab.h']]], - ['can_5fbtr_5flbkm_22',['CAN_BTR_LBKM',['../group___peripheral___registers___bits___definition.html#gac6c0a81d8dcde61a1f2772232f5343b8',1,'stm32f407xx_matlab.h']]], - ['can_5fbtr_5flbkm_5fmsk_23',['CAN_BTR_LBKM_Msk',['../group___peripheral___registers___bits___definition.html#gaa32a82ff55c8008f4c0a1e16c0492d6c',1,'stm32f407xx_matlab.h']]], - ['can_5fbtr_5flbkm_5fpos_24',['CAN_BTR_LBKM_Pos',['../group___peripheral___registers___bits___definition.html#ga4d6dac3caae5bf3f69716d7417e920d7',1,'stm32f407xx_matlab.h']]], - ['can_5fbtr_5fsilm_25',['CAN_BTR_SILM',['../group___peripheral___registers___bits___definition.html#gaa36bc23e833190cbee9b8cf5cf49159d',1,'stm32f407xx_matlab.h']]], - ['can_5fbtr_5fsilm_5fmsk_26',['CAN_BTR_SILM_Msk',['../group___peripheral___registers___bits___definition.html#ga8a7f4e5e22b9959994c790ac9c7f03d3',1,'stm32f407xx_matlab.h']]], - ['can_5fbtr_5fsilm_5fpos_27',['CAN_BTR_SILM_Pos',['../group___peripheral___registers___bits___definition.html#gac19407ed54b60ae709840db37855a0a4',1,'stm32f407xx_matlab.h']]], - ['can_5fbtr_5fsjw_28',['CAN_BTR_SJW',['../group___peripheral___registers___bits___definition.html#ga04c8b91ddacdcbb779bae42398c94cf2',1,'stm32f407xx_matlab.h']]], - ['can_5fbtr_5fsjw_5f0_29',['CAN_BTR_SJW_0',['../group___peripheral___registers___bits___definition.html#ga08ae9e8258ef5c241733f6d58eb2a4e4',1,'stm32f407xx_matlab.h']]], - ['can_5fbtr_5fsjw_5f1_30',['CAN_BTR_SJW_1',['../group___peripheral___registers___bits___definition.html#ga8178f0abe0f854f4503ded1ad1adb531',1,'stm32f407xx_matlab.h']]], - ['can_5fbtr_5fsjw_5fmsk_31',['CAN_BTR_SJW_Msk',['../group___peripheral___registers___bits___definition.html#gaddf7f2fb84354e7e4756bdc25569d6cc',1,'stm32f407xx_matlab.h']]], - ['can_5fbtr_5fsjw_5fpos_32',['CAN_BTR_SJW_Pos',['../group___peripheral___registers___bits___definition.html#ga6cc4270d185b17bd0ce09ebb14c30121',1,'stm32f407xx_matlab.h']]], - ['can_5fbtr_5fts1_33',['CAN_BTR_TS1',['../group___peripheral___registers___bits___definition.html#ga4d7ae8f06f8fbbf5dcfbbbb887057be9',1,'stm32f407xx_matlab.h']]], - ['can_5fbtr_5fts1_5f0_34',['CAN_BTR_TS1_0',['../group___peripheral___registers___bits___definition.html#ga164ffd2240a76982894ce41143a12d82',1,'stm32f407xx_matlab.h']]], - ['can_5fbtr_5fts1_5f1_35',['CAN_BTR_TS1_1',['../group___peripheral___registers___bits___definition.html#gae4365204ebb29eb5595027a4ee9c5f0d',1,'stm32f407xx_matlab.h']]], - ['can_5fbtr_5fts1_5f2_36',['CAN_BTR_TS1_2',['../group___peripheral___registers___bits___definition.html#ga43dc43f11ee173cf07f77aa6e41f1275',1,'stm32f407xx_matlab.h']]], - ['can_5fbtr_5fts1_5f3_37',['CAN_BTR_TS1_3',['../group___peripheral___registers___bits___definition.html#ga7a5cd639329fe3eef8cde846247a4be9',1,'stm32f407xx_matlab.h']]], - ['can_5fbtr_5fts1_5fmsk_38',['CAN_BTR_TS1_Msk',['../group___peripheral___registers___bits___definition.html#gaf97266c03c918c7ff4a0d90b9f80b4f2',1,'stm32f407xx_matlab.h']]], - ['can_5fbtr_5fts1_5fpos_39',['CAN_BTR_TS1_Pos',['../group___peripheral___registers___bits___definition.html#gac00e3a010662ce93bd9e67f340bd2646',1,'stm32f407xx_matlab.h']]], - ['can_5fbtr_5fts2_40',['CAN_BTR_TS2',['../group___peripheral___registers___bits___definition.html#gac006aa2ab26c50227ccaa18e0a79bff3',1,'stm32f407xx_matlab.h']]], - ['can_5fbtr_5fts2_5f0_41',['CAN_BTR_TS2_0',['../group___peripheral___registers___bits___definition.html#gaee307fe50e8d3cfdc9513da803808880',1,'stm32f407xx_matlab.h']]], - ['can_5fbtr_5fts2_5f1_42',['CAN_BTR_TS2_1',['../group___peripheral___registers___bits___definition.html#ga33265730e1d25198d9fb4347bdce8019',1,'stm32f407xx_matlab.h']]], - ['can_5fbtr_5fts2_5f2_43',['CAN_BTR_TS2_2',['../group___peripheral___registers___bits___definition.html#gaac4720d91283fc1fc74c1f0baaa8a3da',1,'stm32f407xx_matlab.h']]], - ['can_5fbtr_5fts2_5fmsk_44',['CAN_BTR_TS2_Msk',['../group___peripheral___registers___bits___definition.html#gaf7c657a3c97363915a9d739defa0f516',1,'stm32f407xx_matlab.h']]], - ['can_5fbtr_5fts2_5fpos_45',['CAN_BTR_TS2_Pos',['../group___peripheral___registers___bits___definition.html#gac80e236530969bf1f520e8e0dd7b7e79',1,'stm32f407xx_matlab.h']]], - ['can_5fesr_5fboff_46',['CAN_ESR_BOFF',['../group___peripheral___registers___bits___definition.html#ga619d49f67f1835a7efc457205fea1225',1,'stm32f407xx_matlab.h']]], - ['can_5fesr_5fboff_5fmsk_47',['CAN_ESR_BOFF_Msk',['../group___peripheral___registers___bits___definition.html#gaa6607245f6b97f83691b9f9d9a3cf592',1,'stm32f407xx_matlab.h']]], - ['can_5fesr_5fboff_5fpos_48',['CAN_ESR_BOFF_Pos',['../group___peripheral___registers___bits___definition.html#gabe022d4e68fb0eca8278904fcfe3c783',1,'stm32f407xx_matlab.h']]], - ['can_5fesr_5fepvf_49',['CAN_ESR_EPVF',['../group___peripheral___registers___bits___definition.html#ga633c961d528cbf8093b0e05e92225ff0',1,'stm32f407xx_matlab.h']]], - ['can_5fesr_5fepvf_5fmsk_50',['CAN_ESR_EPVF_Msk',['../group___peripheral___registers___bits___definition.html#gab80e2d629b9aaf329dee50e9e4ee4a3e',1,'stm32f407xx_matlab.h']]], - ['can_5fesr_5fepvf_5fpos_51',['CAN_ESR_EPVF_Pos',['../group___peripheral___registers___bits___definition.html#ga6c53494946cb6ee312e947da2e4329b6',1,'stm32f407xx_matlab.h']]], - ['can_5fesr_5fewgf_52',['CAN_ESR_EWGF',['../group___peripheral___registers___bits___definition.html#ga2c0c02829fb41ac2a1b1852c19931de8',1,'stm32f407xx_matlab.h']]], - ['can_5fesr_5fewgf_5fmsk_53',['CAN_ESR_EWGF_Msk',['../group___peripheral___registers___bits___definition.html#gaace0e3b331bea3a3f35a3bdf88a40b86',1,'stm32f407xx_matlab.h']]], - ['can_5fesr_5fewgf_5fpos_54',['CAN_ESR_EWGF_Pos',['../group___peripheral___registers___bits___definition.html#gaecadeaf7d9cadf19529cab6314ccc5e6',1,'stm32f407xx_matlab.h']]], - ['can_5fesr_5flec_55',['CAN_ESR_LEC',['../group___peripheral___registers___bits___definition.html#gab9f86741dd89034900e300499ae2272e',1,'stm32f407xx_matlab.h']]], - ['can_5fesr_5flec_5f0_56',['CAN_ESR_LEC_0',['../group___peripheral___registers___bits___definition.html#ga054ebb41578d890d4d9dffb4828f02e7',1,'stm32f407xx_matlab.h']]], - ['can_5fesr_5flec_5f1_57',['CAN_ESR_LEC_1',['../group___peripheral___registers___bits___definition.html#gae570e9ba39dbe11808db929392250cf4',1,'stm32f407xx_matlab.h']]], - ['can_5fesr_5flec_5f2_58',['CAN_ESR_LEC_2',['../group___peripheral___registers___bits___definition.html#ga4998e7bfd002999413c68107911c6e8c',1,'stm32f407xx_matlab.h']]], - ['can_5fesr_5flec_5fmsk_59',['CAN_ESR_LEC_Msk',['../group___peripheral___registers___bits___definition.html#gad88ad0a905fbbe60fa2900f2cec42f5c',1,'stm32f407xx_matlab.h']]], - ['can_5fesr_5flec_5fpos_60',['CAN_ESR_LEC_Pos',['../group___peripheral___registers___bits___definition.html#ga0d2dfedaf48ce2f4787afd43cad691bf',1,'stm32f407xx_matlab.h']]], - ['can_5fesr_5frec_61',['CAN_ESR_REC',['../group___peripheral___registers___bits___definition.html#ga0df5b2ea3f419182e9bd885f55ee5dc9',1,'stm32f407xx_matlab.h']]], - ['can_5fesr_5frec_5fmsk_62',['CAN_ESR_REC_Msk',['../group___peripheral___registers___bits___definition.html#ga0143dc7eea1099168ef7fef24192949e',1,'stm32f407xx_matlab.h']]], - ['can_5fesr_5frec_5fpos_63',['CAN_ESR_REC_Pos',['../group___peripheral___registers___bits___definition.html#ga804f28bce21721cd4e9fcabf772f0f9d',1,'stm32f407xx_matlab.h']]], - ['can_5fesr_5ftec_64',['CAN_ESR_TEC',['../group___peripheral___registers___bits___definition.html#gae3de2080f48cc851c20d920acfd1737d',1,'stm32f407xx_matlab.h']]], - ['can_5fesr_5ftec_5fmsk_65',['CAN_ESR_TEC_Msk',['../group___peripheral___registers___bits___definition.html#ga56c7759712292904bf0d15c2d968bbad',1,'stm32f407xx_matlab.h']]], - ['can_5fesr_5ftec_5fpos_66',['CAN_ESR_TEC_Pos',['../group___peripheral___registers___bits___definition.html#ga11fde56e8a41fc98f69d84636121a361',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r1_5ffb0_67',['CAN_F0R1_FB0',['../group___peripheral___registers___bits___definition.html#ga38014ea45b62975627f8e222390f6819',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r1_5ffb0_5fmsk_68',['CAN_F0R1_FB0_Msk',['../group___peripheral___registers___bits___definition.html#gaf41ce0d3efb93360593d51fc1507ef37',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r1_5ffb0_5fpos_69',['CAN_F0R1_FB0_Pos',['../group___peripheral___registers___bits___definition.html#ga7c98aba7c4d97ff22da1127911917846',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r1_5ffb1_70',['CAN_F0R1_FB1',['../group___peripheral___registers___bits___definition.html#ga9e01c05df79304035c7aab1c7295bf3f',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r1_5ffb10_71',['CAN_F0R1_FB10',['../group___peripheral___registers___bits___definition.html#ga6b8a688856ca6b53417948f79932534d',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r1_5ffb10_5fmsk_72',['CAN_F0R1_FB10_Msk',['../group___peripheral___registers___bits___definition.html#gabcb7c073dbc77461d7519a85f6377a08',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r1_5ffb10_5fpos_73',['CAN_F0R1_FB10_Pos',['../group___peripheral___registers___bits___definition.html#ga5df4d89fa55adb9f8984b482e8b84598',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r1_5ffb11_74',['CAN_F0R1_FB11',['../group___peripheral___registers___bits___definition.html#ga72b81011a2d626ac398a387c89055935',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r1_5ffb11_5fmsk_75',['CAN_F0R1_FB11_Msk',['../group___peripheral___registers___bits___definition.html#ga8f982ab6a096e4421079c592b6791d47',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r1_5ffb11_5fpos_76',['CAN_F0R1_FB11_Pos',['../group___peripheral___registers___bits___definition.html#ga51c39129e454b5f9ea84e7ff296d977b',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r1_5ffb12_77',['CAN_F0R1_FB12',['../group___peripheral___registers___bits___definition.html#gac178a6710aeb6c58f725dd7f00af5d5a',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r1_5ffb12_5fmsk_78',['CAN_F0R1_FB12_Msk',['../group___peripheral___registers___bits___definition.html#gac70bfdc26446118697edbcd2d95b7676',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r1_5ffb12_5fpos_79',['CAN_F0R1_FB12_Pos',['../group___peripheral___registers___bits___definition.html#ga83390adff1d103861b00e3a6a7ff4eb2',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r1_5ffb13_80',['CAN_F0R1_FB13',['../group___peripheral___registers___bits___definition.html#ga8aee1182bef65da056242c4ed49dd0ef',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r1_5ffb13_5fmsk_81',['CAN_F0R1_FB13_Msk',['../group___peripheral___registers___bits___definition.html#gad67a5fe07e6f9e3b3330ad2a46d69d98',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r1_5ffb13_5fpos_82',['CAN_F0R1_FB13_Pos',['../group___peripheral___registers___bits___definition.html#ga6cb3bc6c8af39e8e548d35945c4b4ec0',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r1_5ffb14_83',['CAN_F0R1_FB14',['../group___peripheral___registers___bits___definition.html#gafe16c95f454da44949977e4225590658',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r1_5ffb14_5fmsk_84',['CAN_F0R1_FB14_Msk',['../group___peripheral___registers___bits___definition.html#gac932d38da89bcc4fe8cde14ebb59a29e',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r1_5ffb14_5fpos_85',['CAN_F0R1_FB14_Pos',['../group___peripheral___registers___bits___definition.html#ga0802c1f18214f151a01a44be1669efac',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r1_5ffb15_86',['CAN_F0R1_FB15',['../group___peripheral___registers___bits___definition.html#gabb07dca9fddf64a3476f25f227e33e1f',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r1_5ffb15_5fmsk_87',['CAN_F0R1_FB15_Msk',['../group___peripheral___registers___bits___definition.html#ga71b253d3185e16b606150fee2a19760d',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r1_5ffb15_5fpos_88',['CAN_F0R1_FB15_Pos',['../group___peripheral___registers___bits___definition.html#gaa270d9f780ab40ae9dc1a3650d4bd8d5',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r1_5ffb16_89',['CAN_F0R1_FB16',['../group___peripheral___registers___bits___definition.html#gaf019423a4b07e564dfe917b859e68e80',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r1_5ffb16_5fmsk_90',['CAN_F0R1_FB16_Msk',['../group___peripheral___registers___bits___definition.html#gab87631b267fd39cfee4d253a3d7295b2',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r1_5ffb16_5fpos_91',['CAN_F0R1_FB16_Pos',['../group___peripheral___registers___bits___definition.html#gad7ff7c8fd59e93239bfc6b509e3698ce',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r1_5ffb17_92',['CAN_F0R1_FB17',['../group___peripheral___registers___bits___definition.html#ga6ee508d40637a9d558d2ab85753395bd',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r1_5ffb17_5fmsk_93',['CAN_F0R1_FB17_Msk',['../group___peripheral___registers___bits___definition.html#gaa35416758e3db5bceaff708bdbe5bdc0',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r1_5ffb17_5fpos_94',['CAN_F0R1_FB17_Pos',['../group___peripheral___registers___bits___definition.html#ga594b502afc2b215e7b712f53a14bc5bc',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r1_5ffb18_95',['CAN_F0R1_FB18',['../group___peripheral___registers___bits___definition.html#ga827a459cd51a193d571a16e1d38fac22',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r1_5ffb18_5fmsk_96',['CAN_F0R1_FB18_Msk',['../group___peripheral___registers___bits___definition.html#gac1a49c7f4d13a4e4b4038caaea711391',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r1_5ffb18_5fpos_97',['CAN_F0R1_FB18_Pos',['../group___peripheral___registers___bits___definition.html#gaf097e8cb0757c526b83c45390ffa4b26',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r1_5ffb19_98',['CAN_F0R1_FB19',['../group___peripheral___registers___bits___definition.html#ga1ecfbfd6f5e129d690f1cb62ee344d78',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r1_5ffb19_5fmsk_99',['CAN_F0R1_FB19_Msk',['../group___peripheral___registers___bits___definition.html#ga75a34023fcd221fc010aaa51065d59dc',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r1_5ffb19_5fpos_100',['CAN_F0R1_FB19_Pos',['../group___peripheral___registers___bits___definition.html#ga467f1f2d0208a355d18cdd375eef9aed',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r1_5ffb1_5fmsk_101',['CAN_F0R1_FB1_Msk',['../group___peripheral___registers___bits___definition.html#gaaf16111eec26fa5058aeac0945c0a481',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r1_5ffb1_5fpos_102',['CAN_F0R1_FB1_Pos',['../group___peripheral___registers___bits___definition.html#gaa503478584d6bd0535d29df9839816a0',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r1_5ffb2_103',['CAN_F0R1_FB2',['../group___peripheral___registers___bits___definition.html#ga083282146d4db7f757fef86cf302eded',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r1_5ffb20_104',['CAN_F0R1_FB20',['../group___peripheral___registers___bits___definition.html#ga3a0568e276f245e1f167e673a1f5b92e',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r1_5ffb20_5fmsk_105',['CAN_F0R1_FB20_Msk',['../group___peripheral___registers___bits___definition.html#ga574954093b93f62bcfa5cd31e366c2e8',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r1_5ffb20_5fpos_106',['CAN_F0R1_FB20_Pos',['../group___peripheral___registers___bits___definition.html#gaffdb169bfcc229d44b6f2cbd39327458',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r1_5ffb21_107',['CAN_F0R1_FB21',['../group___peripheral___registers___bits___definition.html#gabb71599bae1e35e750524708ac5824f1',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r1_5ffb21_5fmsk_108',['CAN_F0R1_FB21_Msk',['../group___peripheral___registers___bits___definition.html#ga41cb6ebc16634fc1a187d536575f47dc',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r1_5ffb21_5fpos_109',['CAN_F0R1_FB21_Pos',['../group___peripheral___registers___bits___definition.html#gad9e0fc7eadce21f8851416d9cecbdb22',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r1_5ffb22_110',['CAN_F0R1_FB22',['../group___peripheral___registers___bits___definition.html#ga7589f9a62f9f5406934266820a265f3a',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r1_5ffb22_5fmsk_111',['CAN_F0R1_FB22_Msk',['../group___peripheral___registers___bits___definition.html#ga56eff75e99dbbdd3e4ffe99ae98cd769',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r1_5ffb22_5fpos_112',['CAN_F0R1_FB22_Pos',['../group___peripheral___registers___bits___definition.html#gaeb02ba4a871b3e83ba9ffddc0aa283da',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r1_5ffb23_113',['CAN_F0R1_FB23',['../group___peripheral___registers___bits___definition.html#ga7a0db2ff3fcf3ecd929d61e548905685',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r1_5ffb23_5fmsk_114',['CAN_F0R1_FB23_Msk',['../group___peripheral___registers___bits___definition.html#ga95d558afd743b97060008ebad600c249',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r1_5ffb23_5fpos_115',['CAN_F0R1_FB23_Pos',['../group___peripheral___registers___bits___definition.html#gaf4fab79aa6648f9590bb08efd5ad74f4',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r1_5ffb24_116',['CAN_F0R1_FB24',['../group___peripheral___registers___bits___definition.html#ga2161321c3b0857a9ca07bc45ac9cd1be',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r1_5ffb24_5fmsk_117',['CAN_F0R1_FB24_Msk',['../group___peripheral___registers___bits___definition.html#ga05249fde15f0ea5a4447a370ba33f344',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r1_5ffb24_5fpos_118',['CAN_F0R1_FB24_Pos',['../group___peripheral___registers___bits___definition.html#ga13b36c39c67b88f41d78466dabf1fc68',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r1_5ffb25_119',['CAN_F0R1_FB25',['../group___peripheral___registers___bits___definition.html#gaa85c1d5ccfd6241059822a3aadc1053d',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r1_5ffb25_5fmsk_120',['CAN_F0R1_FB25_Msk',['../group___peripheral___registers___bits___definition.html#gae2e99f0edf1d250d640fda6790e5f8e7',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r1_5ffb25_5fpos_121',['CAN_F0R1_FB25_Pos',['../group___peripheral___registers___bits___definition.html#ga32f93a785540423f910b0fbba693c50c',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r1_5ffb26_122',['CAN_F0R1_FB26',['../group___peripheral___registers___bits___definition.html#ga2d82ba565f065b4dec733d002c02498b',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r1_5ffb26_5fmsk_123',['CAN_F0R1_FB26_Msk',['../group___peripheral___registers___bits___definition.html#ga5d00a7d84706b341bf587c7f329ddf88',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r1_5ffb26_5fpos_124',['CAN_F0R1_FB26_Pos',['../group___peripheral___registers___bits___definition.html#gafd7f7ef5b97b2df3a159a4f5d0c62485',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r1_5ffb27_125',['CAN_F0R1_FB27',['../group___peripheral___registers___bits___definition.html#ga199d63d7155cb5212982d4902e31e70c',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r1_5ffb27_5fmsk_126',['CAN_F0R1_FB27_Msk',['../group___peripheral___registers___bits___definition.html#gaf334329b9d4faf3443e12317303b45d6',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r1_5ffb27_5fpos_127',['CAN_F0R1_FB27_Pos',['../group___peripheral___registers___bits___definition.html#ga080266e7390127c1e4efa9bf8a1d3894',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r1_5ffb28_128',['CAN_F0R1_FB28',['../group___peripheral___registers___bits___definition.html#gac82d92ad6fb51b340e8a52da903e1009',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r1_5ffb28_5fmsk_129',['CAN_F0R1_FB28_Msk',['../group___peripheral___registers___bits___definition.html#gaeb63f1377b7f9dfd87c3ef59a5977ee3',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r1_5ffb28_5fpos_130',['CAN_F0R1_FB28_Pos',['../group___peripheral___registers___bits___definition.html#ga828088c9ccc3e6f4a3b16fe6cf527a58',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r1_5ffb29_131',['CAN_F0R1_FB29',['../group___peripheral___registers___bits___definition.html#gaaa0a651933135336bc14baa3e0a56ab1',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r1_5ffb29_5fmsk_132',['CAN_F0R1_FB29_Msk',['../group___peripheral___registers___bits___definition.html#gabe7e2b3d7caf0ff01c856374d60f8345',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r1_5ffb29_5fpos_133',['CAN_F0R1_FB29_Pos',['../group___peripheral___registers___bits___definition.html#ga4b9440886e48f1f2f9c8737120f2458c',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r1_5ffb2_5fmsk_134',['CAN_F0R1_FB2_Msk',['../group___peripheral___registers___bits___definition.html#ga269a36e254bdc397d46b7b04b25cf58c',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r1_5ffb2_5fpos_135',['CAN_F0R1_FB2_Pos',['../group___peripheral___registers___bits___definition.html#ga30edb71ea81cfa7a3e881e2692093d70',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r1_5ffb3_136',['CAN_F0R1_FB3',['../group___peripheral___registers___bits___definition.html#gae4a1adc2e4e550a38649a2bfd3662680',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r1_5ffb30_137',['CAN_F0R1_FB30',['../group___peripheral___registers___bits___definition.html#gaad2a1d8bb83dfcd9f13d25e8ed098b54',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r1_5ffb30_5fmsk_138',['CAN_F0R1_FB30_Msk',['../group___peripheral___registers___bits___definition.html#gaa9766eac13c78b86a31cd64e0d6bea0d',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r1_5ffb30_5fpos_139',['CAN_F0R1_FB30_Pos',['../group___peripheral___registers___bits___definition.html#ga0fcf33bc1f1bcea9c87040747e2aa6ad',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r1_5ffb31_140',['CAN_F0R1_FB31',['../group___peripheral___registers___bits___definition.html#ga6c9745bc78a65538cbe0fb0d09911554',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r1_5ffb31_5fmsk_141',['CAN_F0R1_FB31_Msk',['../group___peripheral___registers___bits___definition.html#ga5e5e5a0416bc721a85eb46e256c35262',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r1_5ffb31_5fpos_142',['CAN_F0R1_FB31_Pos',['../group___peripheral___registers___bits___definition.html#ga0c57e8d1ef05bc7b1c23812904b290f3',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r1_5ffb3_5fmsk_143',['CAN_F0R1_FB3_Msk',['../group___peripheral___registers___bits___definition.html#gad40133f8c3bdff4edac51999e63eb616',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r1_5ffb3_5fpos_144',['CAN_F0R1_FB3_Pos',['../group___peripheral___registers___bits___definition.html#ga3365da181d4986260f3f1d0adfe2337a',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r1_5ffb4_145',['CAN_F0R1_FB4',['../group___peripheral___registers___bits___definition.html#gaa0bfa15bf30fefb21f351228cde87981',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r1_5ffb4_5fmsk_146',['CAN_F0R1_FB4_Msk',['../group___peripheral___registers___bits___definition.html#gac5be6df46bddda042bca88f23939d6cf',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r1_5ffb4_5fpos_147',['CAN_F0R1_FB4_Pos',['../group___peripheral___registers___bits___definition.html#ga5732df35cf88b47553b239d79818d29f',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r1_5ffb5_148',['CAN_F0R1_FB5',['../group___peripheral___registers___bits___definition.html#ga5381c154ba89611bf4381657305ecb85',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r1_5ffb5_5fmsk_149',['CAN_F0R1_FB5_Msk',['../group___peripheral___registers___bits___definition.html#gae0d0c4979d148b7aadf88999d127a8e4',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r1_5ffb5_5fpos_150',['CAN_F0R1_FB5_Pos',['../group___peripheral___registers___bits___definition.html#ga1ef90325b70b6dbc93a5468d6571ae60',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r1_5ffb6_151',['CAN_F0R1_FB6',['../group___peripheral___registers___bits___definition.html#gae224160853946732608f00ad008a6b1a',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r1_5ffb6_5fmsk_152',['CAN_F0R1_FB6_Msk',['../group___peripheral___registers___bits___definition.html#ga559e44745ca384b08f8e3d370539e2a4',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r1_5ffb6_5fpos_153',['CAN_F0R1_FB6_Pos',['../group___peripheral___registers___bits___definition.html#ga58c06570c4e947c9f58d0fa0ec81490b',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r1_5ffb7_154',['CAN_F0R1_FB7',['../group___peripheral___registers___bits___definition.html#gaa0c44034b5f42fa8250dbb8e46bc83eb',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r1_5ffb7_5fmsk_155',['CAN_F0R1_FB7_Msk',['../group___peripheral___registers___bits___definition.html#ga6d0b187d74d01d2d7a9e0946287a523f',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r1_5ffb7_5fpos_156',['CAN_F0R1_FB7_Pos',['../group___peripheral___registers___bits___definition.html#ga19c4bdfb75f490af25c59c8feabf2be0',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r1_5ffb8_157',['CAN_F0R1_FB8',['../group___peripheral___registers___bits___definition.html#ga465e092af3e73882f9eaffad13f36dea',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r1_5ffb8_5fmsk_158',['CAN_F0R1_FB8_Msk',['../group___peripheral___registers___bits___definition.html#gae373e9d2f9a170895ffab6051243a0f6',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r1_5ffb8_5fpos_159',['CAN_F0R1_FB8_Pos',['../group___peripheral___registers___bits___definition.html#gac6ba4e35ff552a0750f809d3749a5861',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r1_5ffb9_160',['CAN_F0R1_FB9',['../group___peripheral___registers___bits___definition.html#gad1cb7ff6d513fec365eb5a830c3746f0',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r1_5ffb9_5fmsk_161',['CAN_F0R1_FB9_Msk',['../group___peripheral___registers___bits___definition.html#ga4ac0f1442cbee02cb21fca28b5fc61f6',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r1_5ffb9_5fpos_162',['CAN_F0R1_FB9_Pos',['../group___peripheral___registers___bits___definition.html#gaea4ec2d33b8ef0f635bfac9654be0551',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r2_5ffb0_163',['CAN_F0R2_FB0',['../group___peripheral___registers___bits___definition.html#ga34282ddec559ecea4b613f2430334237',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r2_5ffb0_5fmsk_164',['CAN_F0R2_FB0_Msk',['../group___peripheral___registers___bits___definition.html#gaa061083b9a300dcb531acbb0ca426943',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r2_5ffb0_5fpos_165',['CAN_F0R2_FB0_Pos',['../group___peripheral___registers___bits___definition.html#ga2f183a8e746831c98ca9cdb8eabe867b',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r2_5ffb1_166',['CAN_F0R2_FB1',['../group___peripheral___registers___bits___definition.html#ga6f23fc3814e0eb6af35c01e22c5dc6a7',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r2_5ffb10_167',['CAN_F0R2_FB10',['../group___peripheral___registers___bits___definition.html#gaa43bba65dd777c71e07130fde3fa6216',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r2_5ffb10_5fmsk_168',['CAN_F0R2_FB10_Msk',['../group___peripheral___registers___bits___definition.html#gadb8eae7e6372cafdfbb97cee0d3a5906',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r2_5ffb10_5fpos_169',['CAN_F0R2_FB10_Pos',['../group___peripheral___registers___bits___definition.html#ga228d943d2ac8c3e3ca52bcc68bdd0b71',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r2_5ffb11_170',['CAN_F0R2_FB11',['../group___peripheral___registers___bits___definition.html#ga9077b9c35c6721d2a0e090a42af0eaaf',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r2_5ffb11_5fmsk_171',['CAN_F0R2_FB11_Msk',['../group___peripheral___registers___bits___definition.html#ga15c19ccbf1f927445c99e0075e4743f4',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r2_5ffb11_5fpos_172',['CAN_F0R2_FB11_Pos',['../group___peripheral___registers___bits___definition.html#gaef610b498994f7ba1842966f9390548c',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r2_5ffb12_173',['CAN_F0R2_FB12',['../group___peripheral___registers___bits___definition.html#ga23af8df7d4e843a6e196b1542421ef45',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r2_5ffb12_5fmsk_174',['CAN_F0R2_FB12_Msk',['../group___peripheral___registers___bits___definition.html#gaec6f3f414927987a2409f6a4fcee1950',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r2_5ffb12_5fpos_175',['CAN_F0R2_FB12_Pos',['../group___peripheral___registers___bits___definition.html#ga7158038c6c98cd727869fa152286ac06',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r2_5ffb13_176',['CAN_F0R2_FB13',['../group___peripheral___registers___bits___definition.html#ga0fe7776af3adce7d203aeb16d55d86d4',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r2_5ffb13_5fmsk_177',['CAN_F0R2_FB13_Msk',['../group___peripheral___registers___bits___definition.html#ga0f965255e5ae450386165052ebc91266',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r2_5ffb13_5fpos_178',['CAN_F0R2_FB13_Pos',['../group___peripheral___registers___bits___definition.html#gaa0430b63b617ae1318cbb17291a67035',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r2_5ffb14_179',['CAN_F0R2_FB14',['../group___peripheral___registers___bits___definition.html#ga81168efb90a776e44a96d1fe5e3b88c3',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r2_5ffb14_5fmsk_180',['CAN_F0R2_FB14_Msk',['../group___peripheral___registers___bits___definition.html#ga541cda96227f171eeaef984ec3f3bfde',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r2_5ffb14_5fpos_181',['CAN_F0R2_FB14_Pos',['../group___peripheral___registers___bits___definition.html#ga5f653bbe8993cfe6546ea2947fe85837',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r2_5ffb15_182',['CAN_F0R2_FB15',['../group___peripheral___registers___bits___definition.html#gae9708e7cde70a19e8e8fa33291e1b9d5',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r2_5ffb15_5fmsk_183',['CAN_F0R2_FB15_Msk',['../group___peripheral___registers___bits___definition.html#ga9ec4acee70dd0bad3bcfb650e47f99b5',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r2_5ffb15_5fpos_184',['CAN_F0R2_FB15_Pos',['../group___peripheral___registers___bits___definition.html#ga07875079d9eb2ea959eeec1f42e8e469',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r2_5ffb16_185',['CAN_F0R2_FB16',['../group___peripheral___registers___bits___definition.html#gab2f2154c3030cebcfc3f1e4aed74fbf1',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r2_5ffb16_5fmsk_186',['CAN_F0R2_FB16_Msk',['../group___peripheral___registers___bits___definition.html#gaae046a3f26c0161e3c40dc1bc568db3b',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r2_5ffb16_5fpos_187',['CAN_F0R2_FB16_Pos',['../group___peripheral___registers___bits___definition.html#ga7867b900606b53808ce9dbe518513e55',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r2_5ffb17_188',['CAN_F0R2_FB17',['../group___peripheral___registers___bits___definition.html#gae87c14b75911aa0a9d0349d02d342711',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r2_5ffb17_5fmsk_189',['CAN_F0R2_FB17_Msk',['../group___peripheral___registers___bits___definition.html#ga06f28b2b9fdaaba93dd8268b5567a8ad',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r2_5ffb17_5fpos_190',['CAN_F0R2_FB17_Pos',['../group___peripheral___registers___bits___definition.html#ga7f2272ba668cd632f30d77814bc8e465',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r2_5ffb18_191',['CAN_F0R2_FB18',['../group___peripheral___registers___bits___definition.html#ga6fd7859cfc05300f68b175f520ddc31e',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r2_5ffb18_5fmsk_192',['CAN_F0R2_FB18_Msk',['../group___peripheral___registers___bits___definition.html#ga134eae58ad5e99cc09201e3f806390b2',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r2_5ffb18_5fpos_193',['CAN_F0R2_FB18_Pos',['../group___peripheral___registers___bits___definition.html#gad72df4766cb512aa607194c64484d9fb',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r2_5ffb19_194',['CAN_F0R2_FB19',['../group___peripheral___registers___bits___definition.html#gaaea36db8fcada46357137efeea256457',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r2_5ffb19_5fmsk_195',['CAN_F0R2_FB19_Msk',['../group___peripheral___registers___bits___definition.html#ga2288da969d823cf883f0a11d0e66db51',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r2_5ffb19_5fpos_196',['CAN_F0R2_FB19_Pos',['../group___peripheral___registers___bits___definition.html#ga935ebc3c9dd606d36290e38c265ef7dc',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r2_5ffb1_5fmsk_197',['CAN_F0R2_FB1_Msk',['../group___peripheral___registers___bits___definition.html#ga95c94101334ccda880f2c3a2e9e35803',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r2_5ffb1_5fpos_198',['CAN_F0R2_FB1_Pos',['../group___peripheral___registers___bits___definition.html#ga7e70a04e0d25e9e87d225a66110b5a26',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r2_5ffb2_199',['CAN_F0R2_FB2',['../group___peripheral___registers___bits___definition.html#ga82ee32b6ec44d763b4364fa032d3439c',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r2_5ffb20_200',['CAN_F0R2_FB20',['../group___peripheral___registers___bits___definition.html#ga57872dcfea1f8a56170640842edf9c1a',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r2_5ffb20_5fmsk_201',['CAN_F0R2_FB20_Msk',['../group___peripheral___registers___bits___definition.html#ga5e695a429859e9c143330c5cf6ad3229',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r2_5ffb20_5fpos_202',['CAN_F0R2_FB20_Pos',['../group___peripheral___registers___bits___definition.html#ga392416946fa28a09ba37f510aa39ee2f',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r2_5ffb21_203',['CAN_F0R2_FB21',['../group___peripheral___registers___bits___definition.html#gacc01e7f26d0e85da93ca78d0d71a4fed',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r2_5ffb21_5fmsk_204',['CAN_F0R2_FB21_Msk',['../group___peripheral___registers___bits___definition.html#ga9b4a66ffe52286fd25f6bb36fa2e6f21',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r2_5ffb21_5fpos_205',['CAN_F0R2_FB21_Pos',['../group___peripheral___registers___bits___definition.html#gac77ccf85d70f580674fcce170c086071',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r2_5ffb22_206',['CAN_F0R2_FB22',['../group___peripheral___registers___bits___definition.html#ga07d8c3c8c3eb3c97b5979388c548e2fc',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r2_5ffb22_5fmsk_207',['CAN_F0R2_FB22_Msk',['../group___peripheral___registers___bits___definition.html#ga6d02ac9f9a07b7c47059c84a2b0782ee',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r2_5ffb22_5fpos_208',['CAN_F0R2_FB22_Pos',['../group___peripheral___registers___bits___definition.html#ga7de0dedff4a0a111022b7f750c52d8a9',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r2_5ffb23_209',['CAN_F0R2_FB23',['../group___peripheral___registers___bits___definition.html#gade31bd75624afeaef9b5ab45a5057db9',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r2_5ffb23_5fmsk_210',['CAN_F0R2_FB23_Msk',['../group___peripheral___registers___bits___definition.html#ga8cd190536d4b825b086f682b40886f7f',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r2_5ffb23_5fpos_211',['CAN_F0R2_FB23_Pos',['../group___peripheral___registers___bits___definition.html#ga46768113fa95f91e263d6a4b62cffdd3',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r2_5ffb24_212',['CAN_F0R2_FB24',['../group___peripheral___registers___bits___definition.html#gaa78ff8fcfe0f14655aaf94ecc92d7532',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r2_5ffb24_5fmsk_213',['CAN_F0R2_FB24_Msk',['../group___peripheral___registers___bits___definition.html#ga49d6929299df0a13244f0e7958eb711a',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r2_5ffb24_5fpos_214',['CAN_F0R2_FB24_Pos',['../group___peripheral___registers___bits___definition.html#ga8c235ae356a2cce22c4c3a46099e3395',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r2_5ffb25_215',['CAN_F0R2_FB25',['../group___peripheral___registers___bits___definition.html#gaad577ebd9a8cedd1b8b13d5a41d2fbab',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r2_5ffb25_5fmsk_216',['CAN_F0R2_FB25_Msk',['../group___peripheral___registers___bits___definition.html#gaaf6e6acb5b23357732909d4bec0eb95e',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r2_5ffb25_5fpos_217',['CAN_F0R2_FB25_Pos',['../group___peripheral___registers___bits___definition.html#gafc439d9206a0fe829811ba950c98cbb7',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r2_5ffb26_218',['CAN_F0R2_FB26',['../group___peripheral___registers___bits___definition.html#gab814105bcd2a2c636c26197b21ead2b0',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r2_5ffb26_5fmsk_219',['CAN_F0R2_FB26_Msk',['../group___peripheral___registers___bits___definition.html#gab0c77950c4ec1c45ab5c4c2936186d36',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r2_5ffb26_5fpos_220',['CAN_F0R2_FB26_Pos',['../group___peripheral___registers___bits___definition.html#ga3102f1fa9437f6fcd9fa4a51074a837d',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r2_5ffb27_221',['CAN_F0R2_FB27',['../group___peripheral___registers___bits___definition.html#gaea82daeaa71ecddb187613df9517e51c',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r2_5ffb27_5fmsk_222',['CAN_F0R2_FB27_Msk',['../group___peripheral___registers___bits___definition.html#ga47a37ea3a0bc9d4232ee89f18782ff53',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r2_5ffb27_5fpos_223',['CAN_F0R2_FB27_Pos',['../group___peripheral___registers___bits___definition.html#gacf09a3ca077d2274a12ecbf0f8d0aab6',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r2_5ffb28_224',['CAN_F0R2_FB28',['../group___peripheral___registers___bits___definition.html#gaef5036edf5bd310e5e06f3ea5cb818a2',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r2_5ffb28_5fmsk_225',['CAN_F0R2_FB28_Msk',['../group___peripheral___registers___bits___definition.html#gadfb99d019f1abf788685338176fa8595',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r2_5ffb28_5fpos_226',['CAN_F0R2_FB28_Pos',['../group___peripheral___registers___bits___definition.html#ga90c21de25c1da4b3a3c5715e6212c1e9',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r2_5ffb29_227',['CAN_F0R2_FB29',['../group___peripheral___registers___bits___definition.html#gaa0c2db96ddbcfa1b838c283e20ca554b',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r2_5ffb29_5fmsk_228',['CAN_F0R2_FB29_Msk',['../group___peripheral___registers___bits___definition.html#ga875a0587956149206e0df84242e5c38a',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r2_5ffb29_5fpos_229',['CAN_F0R2_FB29_Pos',['../group___peripheral___registers___bits___definition.html#ga168f5225f2ca892513f4d58e7c348c58',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r2_5ffb2_5fmsk_230',['CAN_F0R2_FB2_Msk',['../group___peripheral___registers___bits___definition.html#ga81d454ef34d31e40aeecb2da25e5004d',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r2_5ffb2_5fpos_231',['CAN_F0R2_FB2_Pos',['../group___peripheral___registers___bits___definition.html#ga85d2b4b2c0ce324d0b1356c60cf63257',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r2_5ffb3_232',['CAN_F0R2_FB3',['../group___peripheral___registers___bits___definition.html#ga7867b1d377088c63cdcc615932101997',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r2_5ffb30_233',['CAN_F0R2_FB30',['../group___peripheral___registers___bits___definition.html#ga5afb46a2d4ccb3f28e8579b26e2b2e2e',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r2_5ffb30_5fmsk_234',['CAN_F0R2_FB30_Msk',['../group___peripheral___registers___bits___definition.html#ga4ee59bc46345bde430c9ecf20c8df7a2',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r2_5ffb30_5fpos_235',['CAN_F0R2_FB30_Pos',['../group___peripheral___registers___bits___definition.html#gac273be775b429ef41f46885be62c040d',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r2_5ffb31_236',['CAN_F0R2_FB31',['../group___peripheral___registers___bits___definition.html#ga1ace83e798931f35c123507e1ef59fbb',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r2_5ffb31_5fmsk_237',['CAN_F0R2_FB31_Msk',['../group___peripheral___registers___bits___definition.html#ga90f146c0436009e8b77597db4f06dc88',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r2_5ffb31_5fpos_238',['CAN_F0R2_FB31_Pos',['../group___peripheral___registers___bits___definition.html#gafa39384b9da02ee18353528a10b08920',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r2_5ffb3_5fmsk_239',['CAN_F0R2_FB3_Msk',['../group___peripheral___registers___bits___definition.html#ga526563dd72eb6023c8c6b70ed3eef49f',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r2_5ffb3_5fpos_240',['CAN_F0R2_FB3_Pos',['../group___peripheral___registers___bits___definition.html#gad65a92a16e022fd160904677f2aa2232',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r2_5ffb4_241',['CAN_F0R2_FB4',['../group___peripheral___registers___bits___definition.html#ga37fc5c9115eb669f1ac493b1c7296250',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r2_5ffb4_5fmsk_242',['CAN_F0R2_FB4_Msk',['../group___peripheral___registers___bits___definition.html#ga3e2ad8285cf2dbc13f19cde26aa841ee',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r2_5ffb4_5fpos_243',['CAN_F0R2_FB4_Pos',['../group___peripheral___registers___bits___definition.html#ga34c12a03bd031d6e0f15091903bebca4',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r2_5ffb5_244',['CAN_F0R2_FB5',['../group___peripheral___registers___bits___definition.html#gae04b27aad09a3027f20a4eb48884c463',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r2_5ffb5_5fmsk_245',['CAN_F0R2_FB5_Msk',['../group___peripheral___registers___bits___definition.html#gae572f8b4bb3bfa4dca31b1d4b189c277',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r2_5ffb5_5fpos_246',['CAN_F0R2_FB5_Pos',['../group___peripheral___registers___bits___definition.html#ga6e4adcc243dd4cd40a7221755e583c91',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r2_5ffb6_247',['CAN_F0R2_FB6',['../group___peripheral___registers___bits___definition.html#gae58d87c9513c11593041c3d43b955e8b',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r2_5ffb6_5fmsk_248',['CAN_F0R2_FB6_Msk',['../group___peripheral___registers___bits___definition.html#ga1d86d510a3fa0f7bb396b2535ff7412f',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r2_5ffb6_5fpos_249',['CAN_F0R2_FB6_Pos',['../group___peripheral___registers___bits___definition.html#gaf319616807592f75d1a61ee9d8607265',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r2_5ffb7_250',['CAN_F0R2_FB7',['../group___peripheral___registers___bits___definition.html#ga03a6328d408b8015bb472c76f96a4dd8',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r2_5ffb7_5fmsk_251',['CAN_F0R2_FB7_Msk',['../group___peripheral___registers___bits___definition.html#ga931a307d0830015fa4494ed6a34e3fb5',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r2_5ffb7_5fpos_252',['CAN_F0R2_FB7_Pos',['../group___peripheral___registers___bits___definition.html#ga9e7fb85c2a88f84eb38d43bf730a11c1',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r2_5ffb8_253',['CAN_F0R2_FB8',['../group___peripheral___registers___bits___definition.html#ga92fd1acf48665f966b670a0457456deb',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r2_5ffb8_5fmsk_254',['CAN_F0R2_FB8_Msk',['../group___peripheral___registers___bits___definition.html#ga4f123f65007d2d150da67e5114b8354f',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r2_5ffb8_5fpos_255',['CAN_F0R2_FB8_Pos',['../group___peripheral___registers___bits___definition.html#ga8dfb2cfa716e20ca94c9461d0c75dc1f',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r2_5ffb9_256',['CAN_F0R2_FB9',['../group___peripheral___registers___bits___definition.html#gaa853cff5493c4e857b7bb1ad28678ed4',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r2_5ffb9_5fmsk_257',['CAN_F0R2_FB9_Msk',['../group___peripheral___registers___bits___definition.html#ga31eeb8ac004bb1a829c442474a019b05',1,'stm32f407xx_matlab.h']]], - ['can_5ff0r2_5ffb9_5fpos_258',['CAN_F0R2_FB9_Pos',['../group___peripheral___registers___bits___definition.html#gaf66c4a2200af005c5035aca282158e29',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r1_5ffb0_259',['CAN_F10R1_FB0',['../group___peripheral___registers___bits___definition.html#ga1d5b5b7bc147da430d9c8fbe03679ca3',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r1_5ffb0_5fmsk_260',['CAN_F10R1_FB0_Msk',['../group___peripheral___registers___bits___definition.html#ga7a05b74c330bf04f1f6f3ae982306f57',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r1_5ffb0_5fpos_261',['CAN_F10R1_FB0_Pos',['../group___peripheral___registers___bits___definition.html#ga34b8639dd16a3b599266e6a777fb604d',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r1_5ffb1_262',['CAN_F10R1_FB1',['../group___peripheral___registers___bits___definition.html#ga3ed7be0180fd7096f10cfde27261ecc9',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r1_5ffb10_263',['CAN_F10R1_FB10',['../group___peripheral___registers___bits___definition.html#ga6d525825fe4bfc1d4ffccc21ab89a3fa',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r1_5ffb10_5fmsk_264',['CAN_F10R1_FB10_Msk',['../group___peripheral___registers___bits___definition.html#ga159afb7939de25a56d4a7c72e3669b8c',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r1_5ffb10_5fpos_265',['CAN_F10R1_FB10_Pos',['../group___peripheral___registers___bits___definition.html#ga52a16b6466cddacc04e9200bea868510',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r1_5ffb11_266',['CAN_F10R1_FB11',['../group___peripheral___registers___bits___definition.html#ga33336e283eeee9b77f1f289d77f2304e',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r1_5ffb11_5fmsk_267',['CAN_F10R1_FB11_Msk',['../group___peripheral___registers___bits___definition.html#gaa37f47760352e40a33327441fa44917a',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r1_5ffb11_5fpos_268',['CAN_F10R1_FB11_Pos',['../group___peripheral___registers___bits___definition.html#ga77878bda5d61d09fa0b3ea54a208c889',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r1_5ffb12_269',['CAN_F10R1_FB12',['../group___peripheral___registers___bits___definition.html#gadf74ee01e72b3de69d6e8fcc092f7461',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r1_5ffb12_5fmsk_270',['CAN_F10R1_FB12_Msk',['../group___peripheral___registers___bits___definition.html#ga6456e18d6659ec3437ab1b5c84b60681',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r1_5ffb12_5fpos_271',['CAN_F10R1_FB12_Pos',['../group___peripheral___registers___bits___definition.html#gafb667a50ca9535347b011c47aa7f7f8a',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r1_5ffb13_272',['CAN_F10R1_FB13',['../group___peripheral___registers___bits___definition.html#ga8ee416ff22b47bb289bab34afbc74f19',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r1_5ffb13_5fmsk_273',['CAN_F10R1_FB13_Msk',['../group___peripheral___registers___bits___definition.html#ga1f0b809ab8b05e662982533d29d34196',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r1_5ffb13_5fpos_274',['CAN_F10R1_FB13_Pos',['../group___peripheral___registers___bits___definition.html#gaf29dbf589e4978181256649c864076da',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r1_5ffb14_275',['CAN_F10R1_FB14',['../group___peripheral___registers___bits___definition.html#ga97a8d8586c64910b0f6c09fef44c4ea7',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r1_5ffb14_5fmsk_276',['CAN_F10R1_FB14_Msk',['../group___peripheral___registers___bits___definition.html#gae1553e078a11eeb8d8ea8c0e0448b4d0',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r1_5ffb14_5fpos_277',['CAN_F10R1_FB14_Pos',['../group___peripheral___registers___bits___definition.html#ga1630e20424cfa65e81a05cce2c1f7337',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r1_5ffb15_278',['CAN_F10R1_FB15',['../group___peripheral___registers___bits___definition.html#gab9e8e43adc56ba1e593b97e062c79075',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r1_5ffb15_5fmsk_279',['CAN_F10R1_FB15_Msk',['../group___peripheral___registers___bits___definition.html#ga372ca9243e9a38085b93d717f05b885a',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r1_5ffb15_5fpos_280',['CAN_F10R1_FB15_Pos',['../group___peripheral___registers___bits___definition.html#ga1651020c3774aaad2dcda820e38a4b61',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r1_5ffb16_281',['CAN_F10R1_FB16',['../group___peripheral___registers___bits___definition.html#gaa64a0b16c073b51cb5e90b94c638fd95',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r1_5ffb16_5fmsk_282',['CAN_F10R1_FB16_Msk',['../group___peripheral___registers___bits___definition.html#ga90ecfd894be7f8a4d1eb0cbfe995f7a8',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r1_5ffb16_5fpos_283',['CAN_F10R1_FB16_Pos',['../group___peripheral___registers___bits___definition.html#gad18243430f119e7ed075890d0c4ee9bd',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r1_5ffb17_284',['CAN_F10R1_FB17',['../group___peripheral___registers___bits___definition.html#ga65f5cc396cfcf3bad71a71326e64f7d9',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r1_5ffb17_5fmsk_285',['CAN_F10R1_FB17_Msk',['../group___peripheral___registers___bits___definition.html#ga4d4bfbfb134e99de69fe63974eae0eba',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r1_5ffb17_5fpos_286',['CAN_F10R1_FB17_Pos',['../group___peripheral___registers___bits___definition.html#ga7d5b824a1aa2f34e1c413feffd1503fd',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r1_5ffb18_287',['CAN_F10R1_FB18',['../group___peripheral___registers___bits___definition.html#ga424940f535aa9a1520e25df53673d01f',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r1_5ffb18_5fmsk_288',['CAN_F10R1_FB18_Msk',['../group___peripheral___registers___bits___definition.html#ga59843c48e4723e0d3cb389b8dc31e95a',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r1_5ffb18_5fpos_289',['CAN_F10R1_FB18_Pos',['../group___peripheral___registers___bits___definition.html#ga3ca233f5cf20e9ec03df3088fdf56f06',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r1_5ffb19_290',['CAN_F10R1_FB19',['../group___peripheral___registers___bits___definition.html#ga166a4035770c58147d583c3dc571d10a',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r1_5ffb19_5fmsk_291',['CAN_F10R1_FB19_Msk',['../group___peripheral___registers___bits___definition.html#ga028e9c16a75cfe1a4209db5761793d65',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r1_5ffb19_5fpos_292',['CAN_F10R1_FB19_Pos',['../group___peripheral___registers___bits___definition.html#ga6910b732b7855530c3a345d1b027a7f4',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r1_5ffb1_5fmsk_293',['CAN_F10R1_FB1_Msk',['../group___peripheral___registers___bits___definition.html#gaccc10e15c593cf151539aaf626131cd6',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r1_5ffb1_5fpos_294',['CAN_F10R1_FB1_Pos',['../group___peripheral___registers___bits___definition.html#ga61d255693dabbb9177ad7a611aac5958',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r1_5ffb2_295',['CAN_F10R1_FB2',['../group___peripheral___registers___bits___definition.html#gad099442eb6b71912a81d1f6fccbaec0a',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r1_5ffb20_296',['CAN_F10R1_FB20',['../group___peripheral___registers___bits___definition.html#ga302214ece439e8913b47949bd07d118a',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r1_5ffb20_5fmsk_297',['CAN_F10R1_FB20_Msk',['../group___peripheral___registers___bits___definition.html#ga0d3e3967b90e93cdf5d2dff50ccd6467',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r1_5ffb20_5fpos_298',['CAN_F10R1_FB20_Pos',['../group___peripheral___registers___bits___definition.html#gab55c921e020738e5610d97fe033855c7',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r1_5ffb21_299',['CAN_F10R1_FB21',['../group___peripheral___registers___bits___definition.html#gad9abe6ae1dcb2bd140e7e28d37fd8abb',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r1_5ffb21_5fmsk_300',['CAN_F10R1_FB21_Msk',['../group___peripheral___registers___bits___definition.html#ga4f7d08dc1418dc7260c85dcd41c3f2f7',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r1_5ffb21_5fpos_301',['CAN_F10R1_FB21_Pos',['../group___peripheral___registers___bits___definition.html#ga971d242e49fe7359b6e741466d305411',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r1_5ffb22_302',['CAN_F10R1_FB22',['../group___peripheral___registers___bits___definition.html#ga99063956b41c4dcf6c78cc29305b1cd1',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r1_5ffb22_5fmsk_303',['CAN_F10R1_FB22_Msk',['../group___peripheral___registers___bits___definition.html#ga33f696dbd8db5370eb9701e521227e2e',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r1_5ffb22_5fpos_304',['CAN_F10R1_FB22_Pos',['../group___peripheral___registers___bits___definition.html#gabf28c54456414ccbb9b51ce644d47601',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r1_5ffb23_305',['CAN_F10R1_FB23',['../group___peripheral___registers___bits___definition.html#ga81ae64786c3a83bdd21cf72c560c7c1e',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r1_5ffb23_5fmsk_306',['CAN_F10R1_FB23_Msk',['../group___peripheral___registers___bits___definition.html#gab4b78077f4a9d949debb3c345fcc8203',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r1_5ffb23_5fpos_307',['CAN_F10R1_FB23_Pos',['../group___peripheral___registers___bits___definition.html#ga9adb7b8a937732924faef5a13b6d691c',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r1_5ffb24_308',['CAN_F10R1_FB24',['../group___peripheral___registers___bits___definition.html#ga0f9083faf8395701c892814694b45d2c',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r1_5ffb24_5fmsk_309',['CAN_F10R1_FB24_Msk',['../group___peripheral___registers___bits___definition.html#gadaa800d4dbab113869136419067683b7',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r1_5ffb24_5fpos_310',['CAN_F10R1_FB24_Pos',['../group___peripheral___registers___bits___definition.html#ga3774098d002351e5997edddd0c0ce5d0',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r1_5ffb25_311',['CAN_F10R1_FB25',['../group___peripheral___registers___bits___definition.html#gaaeb6942affe306b407940fdf01534e4a',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r1_5ffb25_5fmsk_312',['CAN_F10R1_FB25_Msk',['../group___peripheral___registers___bits___definition.html#gab2755b753aff086d43feba71cc367da2',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r1_5ffb25_5fpos_313',['CAN_F10R1_FB25_Pos',['../group___peripheral___registers___bits___definition.html#ga91439fb8d069e77aeb88065b1c685f89',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r1_5ffb26_314',['CAN_F10R1_FB26',['../group___peripheral___registers___bits___definition.html#ga1e4ee946a9614316f666852bc266c1f7',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r1_5ffb26_5fmsk_315',['CAN_F10R1_FB26_Msk',['../group___peripheral___registers___bits___definition.html#gaea7c4b309760f303d4bbd9ef507673d9',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r1_5ffb26_5fpos_316',['CAN_F10R1_FB26_Pos',['../group___peripheral___registers___bits___definition.html#gaed8963dfbdac3df92f96632e9f8973a9',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r1_5ffb27_317',['CAN_F10R1_FB27',['../group___peripheral___registers___bits___definition.html#ga99153cddc8fc7e846fcc44383936541f',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r1_5ffb27_5fmsk_318',['CAN_F10R1_FB27_Msk',['../group___peripheral___registers___bits___definition.html#ga713459bb360bab56e68cd562bcc86992',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r1_5ffb27_5fpos_319',['CAN_F10R1_FB27_Pos',['../group___peripheral___registers___bits___definition.html#gaacffecbefab44f2d80330ff6b3316404',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r1_5ffb28_320',['CAN_F10R1_FB28',['../group___peripheral___registers___bits___definition.html#ga0e2ba1740577246368e60d94fd3d7c69',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r1_5ffb28_5fmsk_321',['CAN_F10R1_FB28_Msk',['../group___peripheral___registers___bits___definition.html#ga904044b84be51c67151570af41280109',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r1_5ffb28_5fpos_322',['CAN_F10R1_FB28_Pos',['../group___peripheral___registers___bits___definition.html#gac8670b0f5b08f2106aed385abe471988',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r1_5ffb29_323',['CAN_F10R1_FB29',['../group___peripheral___registers___bits___definition.html#gaca062686821fba26a0e5e5b0a6c5b855',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r1_5ffb29_5fmsk_324',['CAN_F10R1_FB29_Msk',['../group___peripheral___registers___bits___definition.html#gabb9254a4f5e458db48b99024ee4dcf28',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r1_5ffb29_5fpos_325',['CAN_F10R1_FB29_Pos',['../group___peripheral___registers___bits___definition.html#gac47d24136b51470d74e9e0416110e608',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r1_5ffb2_5fmsk_326',['CAN_F10R1_FB2_Msk',['../group___peripheral___registers___bits___definition.html#ga3cc815403ff9f3643971ecd50b8e1c0a',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r1_5ffb2_5fpos_327',['CAN_F10R1_FB2_Pos',['../group___peripheral___registers___bits___definition.html#ga2e899e29234df6b50a1866c607823ca8',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r1_5ffb3_328',['CAN_F10R1_FB3',['../group___peripheral___registers___bits___definition.html#ga4024c53b7b0cec550baed99ae92e3465',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r1_5ffb30_329',['CAN_F10R1_FB30',['../group___peripheral___registers___bits___definition.html#ga8981f420ef4c8fe1976a09f27a9c13f1',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r1_5ffb30_5fmsk_330',['CAN_F10R1_FB30_Msk',['../group___peripheral___registers___bits___definition.html#gadc17c37afd6e8048e5561cc76204de98',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r1_5ffb30_5fpos_331',['CAN_F10R1_FB30_Pos',['../group___peripheral___registers___bits___definition.html#ga29cf8efcf620782b10885d84e0ebd370',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r1_5ffb31_332',['CAN_F10R1_FB31',['../group___peripheral___registers___bits___definition.html#ga0424bf38917058b166a8bfd861d22b40',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r1_5ffb31_5fmsk_333',['CAN_F10R1_FB31_Msk',['../group___peripheral___registers___bits___definition.html#gaa0010aac3ddd9cb356328c22fcab2fd9',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r1_5ffb31_5fpos_334',['CAN_F10R1_FB31_Pos',['../group___peripheral___registers___bits___definition.html#ga486a9b2d165733097746c0e075332056',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r1_5ffb3_5fmsk_335',['CAN_F10R1_FB3_Msk',['../group___peripheral___registers___bits___definition.html#gabc1db4c0b25f68a6bd3c6cbb2d2c82ee',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r1_5ffb3_5fpos_336',['CAN_F10R1_FB3_Pos',['../group___peripheral___registers___bits___definition.html#ga5b6414ba4791274ad1dedeae302deb8c',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r1_5ffb4_337',['CAN_F10R1_FB4',['../group___peripheral___registers___bits___definition.html#ga1859eaac9ae1220c752218e5ad526179',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r1_5ffb4_5fmsk_338',['CAN_F10R1_FB4_Msk',['../group___peripheral___registers___bits___definition.html#gad91329ef7b3229b4f06f31c8fbaa8507',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r1_5ffb4_5fpos_339',['CAN_F10R1_FB4_Pos',['../group___peripheral___registers___bits___definition.html#gab1468d4f971fefa12ac2373e9059fcc4',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r1_5ffb5_340',['CAN_F10R1_FB5',['../group___peripheral___registers___bits___definition.html#ga5683dc25f0aae9a802a5f57c88bec856',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r1_5ffb5_5fmsk_341',['CAN_F10R1_FB5_Msk',['../group___peripheral___registers___bits___definition.html#gadf7af08619a0d22a111e253c1059024d',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r1_5ffb5_5fpos_342',['CAN_F10R1_FB5_Pos',['../group___peripheral___registers___bits___definition.html#ga5059f789c76d31ef43d2933a6794ebef',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r1_5ffb6_343',['CAN_F10R1_FB6',['../group___peripheral___registers___bits___definition.html#gae83dd9ce8a2c7917e278ce4755f8f43e',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r1_5ffb6_5fmsk_344',['CAN_F10R1_FB6_Msk',['../group___peripheral___registers___bits___definition.html#ga9fcb5577636b7acc70f13f92cbfa3f9a',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r1_5ffb6_5fpos_345',['CAN_F10R1_FB6_Pos',['../group___peripheral___registers___bits___definition.html#ga4c9f5e78c2fbffbca7976837c901ae11',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r1_5ffb7_346',['CAN_F10R1_FB7',['../group___peripheral___registers___bits___definition.html#ga93ad070c9f5abca3c9b9095e3a13db9c',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r1_5ffb7_5fmsk_347',['CAN_F10R1_FB7_Msk',['../group___peripheral___registers___bits___definition.html#ga557466eedc11bcfb78333511b3465921',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r1_5ffb7_5fpos_348',['CAN_F10R1_FB7_Pos',['../group___peripheral___registers___bits___definition.html#ga3456bf703efc85fb20bc9ccae394e575',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r1_5ffb8_349',['CAN_F10R1_FB8',['../group___peripheral___registers___bits___definition.html#gadd32db3ffec3536cd842e17c34c210d9',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r1_5ffb8_5fmsk_350',['CAN_F10R1_FB8_Msk',['../group___peripheral___registers___bits___definition.html#ga451e0f30e41e5216fb223e52bdadce7a',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r1_5ffb8_5fpos_351',['CAN_F10R1_FB8_Pos',['../group___peripheral___registers___bits___definition.html#gac77280ec33da757f550aa90612a3e45c',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r1_5ffb9_352',['CAN_F10R1_FB9',['../group___peripheral___registers___bits___definition.html#ga85673ce7a92ae8ca9a13ed2fb5574a76',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r1_5ffb9_5fmsk_353',['CAN_F10R1_FB9_Msk',['../group___peripheral___registers___bits___definition.html#ga434ad62e086a866ca425960236216d34',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r1_5ffb9_5fpos_354',['CAN_F10R1_FB9_Pos',['../group___peripheral___registers___bits___definition.html#ga5340c5e8483f2ab61e51f7f4b0d6a78a',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r2_5ffb0_355',['CAN_F10R2_FB0',['../group___peripheral___registers___bits___definition.html#ga616898121d5befed0eb5ab61492872f2',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r2_5ffb0_5fmsk_356',['CAN_F10R2_FB0_Msk',['../group___peripheral___registers___bits___definition.html#gac774a841f16adc00aaa2ec9fc7e19fcb',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r2_5ffb0_5fpos_357',['CAN_F10R2_FB0_Pos',['../group___peripheral___registers___bits___definition.html#ga067cb17fa931fc8ec805a317221d553f',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r2_5ffb1_358',['CAN_F10R2_FB1',['../group___peripheral___registers___bits___definition.html#gaa24b6ba1e723098e55e4affc793558c5',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r2_5ffb10_359',['CAN_F10R2_FB10',['../group___peripheral___registers___bits___definition.html#ga4da658bf0a044b327c5efcc592e0ebe1',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r2_5ffb10_5fmsk_360',['CAN_F10R2_FB10_Msk',['../group___peripheral___registers___bits___definition.html#ga2bb490d175c5c7ea273dc5a2ed089028',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r2_5ffb10_5fpos_361',['CAN_F10R2_FB10_Pos',['../group___peripheral___registers___bits___definition.html#ga1e968d8513a58a5be0ce2cbce6cd7642',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r2_5ffb11_362',['CAN_F10R2_FB11',['../group___peripheral___registers___bits___definition.html#gae6ec91db97da763ae1da98ef3a3f7fea',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r2_5ffb11_5fmsk_363',['CAN_F10R2_FB11_Msk',['../group___peripheral___registers___bits___definition.html#ga898eafb1c345981f1feaa3e1750f7c32',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r2_5ffb11_5fpos_364',['CAN_F10R2_FB11_Pos',['../group___peripheral___registers___bits___definition.html#gafb10c3617ae2bd30b86196797e26ecba',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r2_5ffb12_365',['CAN_F10R2_FB12',['../group___peripheral___registers___bits___definition.html#ga62bba82d177602a29448acf481a7f691',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r2_5ffb12_5fmsk_366',['CAN_F10R2_FB12_Msk',['../group___peripheral___registers___bits___definition.html#gae0d87b23898f43c4c310c9e9098e78b9',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r2_5ffb12_5fpos_367',['CAN_F10R2_FB12_Pos',['../group___peripheral___registers___bits___definition.html#gafedb8df9e02ae3bbe23bba2d1afb8e2e',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r2_5ffb13_368',['CAN_F10R2_FB13',['../group___peripheral___registers___bits___definition.html#ga6ce79aa37f7a175695fb910f986b7d81',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r2_5ffb13_5fmsk_369',['CAN_F10R2_FB13_Msk',['../group___peripheral___registers___bits___definition.html#gad7044a16f8b7a80cfaeaca7c1c8b244f',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r2_5ffb13_5fpos_370',['CAN_F10R2_FB13_Pos',['../group___peripheral___registers___bits___definition.html#gabec06c12b62b4aa0ee4391e6e663ced3',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r2_5ffb14_371',['CAN_F10R2_FB14',['../group___peripheral___registers___bits___definition.html#gadf31488587e33ea32b60a5c21f3e3aff',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r2_5ffb14_5fmsk_372',['CAN_F10R2_FB14_Msk',['../group___peripheral___registers___bits___definition.html#gaccaaa620579ebfb8e1d78f1c3a0960c8',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r2_5ffb14_5fpos_373',['CAN_F10R2_FB14_Pos',['../group___peripheral___registers___bits___definition.html#ga50210bdcea0f100cf7bb58790cdace47',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r2_5ffb15_374',['CAN_F10R2_FB15',['../group___peripheral___registers___bits___definition.html#gad8c7c289c07afb023bb3eedfe4d5a9b1',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r2_5ffb15_5fmsk_375',['CAN_F10R2_FB15_Msk',['../group___peripheral___registers___bits___definition.html#gad44ba649751e52a75f36d5279ae51668',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r2_5ffb15_5fpos_376',['CAN_F10R2_FB15_Pos',['../group___peripheral___registers___bits___definition.html#ga5fe557c8dc9f510fed958662e88e3e7a',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r2_5ffb16_377',['CAN_F10R2_FB16',['../group___peripheral___registers___bits___definition.html#ga74258ab493246fefc21ddc475dcfda4a',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r2_5ffb16_5fmsk_378',['CAN_F10R2_FB16_Msk',['../group___peripheral___registers___bits___definition.html#ga4b8427af5b1aa6b8275902848c766a6a',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r2_5ffb16_5fpos_379',['CAN_F10R2_FB16_Pos',['../group___peripheral___registers___bits___definition.html#gae18123a344ee82992f3a7af5e7f901fa',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r2_5ffb17_380',['CAN_F10R2_FB17',['../group___peripheral___registers___bits___definition.html#gabcf9f2daaa27f340a8cd4e64533f5caf',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r2_5ffb17_5fmsk_381',['CAN_F10R2_FB17_Msk',['../group___peripheral___registers___bits___definition.html#ga3bc510b54127fe09c9fc93d265f197fd',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r2_5ffb17_5fpos_382',['CAN_F10R2_FB17_Pos',['../group___peripheral___registers___bits___definition.html#ga3ae29a19824d47f5c97c8ccbd6f6b663',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r2_5ffb18_383',['CAN_F10R2_FB18',['../group___peripheral___registers___bits___definition.html#ga2b8ad53931f4cb3bebb3f557d8686066',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r2_5ffb18_5fmsk_384',['CAN_F10R2_FB18_Msk',['../group___peripheral___registers___bits___definition.html#ga15818be97fc1df403386e5fa3791f02f',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r2_5ffb18_5fpos_385',['CAN_F10R2_FB18_Pos',['../group___peripheral___registers___bits___definition.html#gac05d35a5ccbe652b9d4c5d8ac19a3188',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r2_5ffb19_386',['CAN_F10R2_FB19',['../group___peripheral___registers___bits___definition.html#ga9f0b00c508bddf59fd290091e738a340',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r2_5ffb19_5fmsk_387',['CAN_F10R2_FB19_Msk',['../group___peripheral___registers___bits___definition.html#gabdc7ed5a571a970931be36e0883c9821',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r2_5ffb19_5fpos_388',['CAN_F10R2_FB19_Pos',['../group___peripheral___registers___bits___definition.html#ga8425c341a53e4648190d86ea2c452fa7',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r2_5ffb1_5fmsk_389',['CAN_F10R2_FB1_Msk',['../group___peripheral___registers___bits___definition.html#ga6a4ed750a26abda88304eac5be92b6a5',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r2_5ffb1_5fpos_390',['CAN_F10R2_FB1_Pos',['../group___peripheral___registers___bits___definition.html#ga742179253216598663252628f54678a8',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r2_5ffb2_391',['CAN_F10R2_FB2',['../group___peripheral___registers___bits___definition.html#ga1b7fc9db4e77e216f37bf088d7b7703c',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r2_5ffb20_392',['CAN_F10R2_FB20',['../group___peripheral___registers___bits___definition.html#gadb9db852d4bf1332f748a0cfc0063364',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r2_5ffb20_5fmsk_393',['CAN_F10R2_FB20_Msk',['../group___peripheral___registers___bits___definition.html#ga31df60197cdd2e5914c14a7dd75e026b',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r2_5ffb20_5fpos_394',['CAN_F10R2_FB20_Pos',['../group___peripheral___registers___bits___definition.html#gaf22b16751fb337af287331048cfcae91',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r2_5ffb21_395',['CAN_F10R2_FB21',['../group___peripheral___registers___bits___definition.html#ga616164fcd20341e4eed5b10a8fd2837c',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r2_5ffb21_5fmsk_396',['CAN_F10R2_FB21_Msk',['../group___peripheral___registers___bits___definition.html#ga19dd43ea7d9942f810f2d93169ff5ca6',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r2_5ffb21_5fpos_397',['CAN_F10R2_FB21_Pos',['../group___peripheral___registers___bits___definition.html#ga0f49963bc7d859f4d79f5f9f55649013',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r2_5ffb22_398',['CAN_F10R2_FB22',['../group___peripheral___registers___bits___definition.html#gae70893925ea53547e9ce780c0480587b',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r2_5ffb22_5fmsk_399',['CAN_F10R2_FB22_Msk',['../group___peripheral___registers___bits___definition.html#gace06a38396f56ff90887b648c8683acc',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r2_5ffb22_5fpos_400',['CAN_F10R2_FB22_Pos',['../group___peripheral___registers___bits___definition.html#gabb17a1d300b8ffde0b9ef278aead2bbc',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r2_5ffb23_401',['CAN_F10R2_FB23',['../group___peripheral___registers___bits___definition.html#gaed74e80c74c6c5e12d26abbc0d923787',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r2_5ffb23_5fmsk_402',['CAN_F10R2_FB23_Msk',['../group___peripheral___registers___bits___definition.html#ga2806783fb4a13314098d247596f8ac9c',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r2_5ffb23_5fpos_403',['CAN_F10R2_FB23_Pos',['../group___peripheral___registers___bits___definition.html#ga55d1af80d3c1e3fa6474ccf0509abf83',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r2_5ffb24_404',['CAN_F10R2_FB24',['../group___peripheral___registers___bits___definition.html#gaecb5b90d073107f3c5612379aaffa7ce',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r2_5ffb24_5fmsk_405',['CAN_F10R2_FB24_Msk',['../group___peripheral___registers___bits___definition.html#gad57d7ec2281a4b5a7ecd3db7a80110ba',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r2_5ffb24_5fpos_406',['CAN_F10R2_FB24_Pos',['../group___peripheral___registers___bits___definition.html#ga869fa5f46955a937b321cdc30d0c08b1',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r2_5ffb25_407',['CAN_F10R2_FB25',['../group___peripheral___registers___bits___definition.html#ga678702522f87f63edfcad21194be3c53',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r2_5ffb25_5fmsk_408',['CAN_F10R2_FB25_Msk',['../group___peripheral___registers___bits___definition.html#ga9b18d4f50852e67f214d2c885ab1d96b',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r2_5ffb25_5fpos_409',['CAN_F10R2_FB25_Pos',['../group___peripheral___registers___bits___definition.html#ga8dc7dc1019cca26cba0b729119ba43b1',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r2_5ffb26_410',['CAN_F10R2_FB26',['../group___peripheral___registers___bits___definition.html#gaf4523c34e7f333636fade643b895b8f5',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r2_5ffb26_5fmsk_411',['CAN_F10R2_FB26_Msk',['../group___peripheral___registers___bits___definition.html#gac022d750541154d1c25ae0b342ff3c8d',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r2_5ffb26_5fpos_412',['CAN_F10R2_FB26_Pos',['../group___peripheral___registers___bits___definition.html#ga1cc3ae2b65d3e4aca044242f0f8b4a29',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r2_5ffb27_413',['CAN_F10R2_FB27',['../group___peripheral___registers___bits___definition.html#gacf0e55fcb496970abe8fea481561f886',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r2_5ffb27_5fmsk_414',['CAN_F10R2_FB27_Msk',['../group___peripheral___registers___bits___definition.html#ga441739ed3bdd065bee7417d50afc96ab',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r2_5ffb27_5fpos_415',['CAN_F10R2_FB27_Pos',['../group___peripheral___registers___bits___definition.html#ga3aa23672b58bce5c01c0964f8588e5bd',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r2_5ffb28_416',['CAN_F10R2_FB28',['../group___peripheral___registers___bits___definition.html#ga4e4683223d46d60897b2c46b02addec5',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r2_5ffb28_5fmsk_417',['CAN_F10R2_FB28_Msk',['../group___peripheral___registers___bits___definition.html#ga906bacdcf21c6bffaa9d45fa6746f80e',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r2_5ffb28_5fpos_418',['CAN_F10R2_FB28_Pos',['../group___peripheral___registers___bits___definition.html#gab0b2954975958605274276c9ae1ea7a6',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r2_5ffb29_419',['CAN_F10R2_FB29',['../group___peripheral___registers___bits___definition.html#ga6df50371abf968f0638faf7e0bf76cc8',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r2_5ffb29_5fmsk_420',['CAN_F10R2_FB29_Msk',['../group___peripheral___registers___bits___definition.html#gafe8c560adab03768e49cad994a71cccb',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r2_5ffb29_5fpos_421',['CAN_F10R2_FB29_Pos',['../group___peripheral___registers___bits___definition.html#ga382e8caf7bca3cea6323f83220c5f04c',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r2_5ffb2_5fmsk_422',['CAN_F10R2_FB2_Msk',['../group___peripheral___registers___bits___definition.html#gaf87f405ddb1abb90958df292c6fc0a4a',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r2_5ffb2_5fpos_423',['CAN_F10R2_FB2_Pos',['../group___peripheral___registers___bits___definition.html#ga36eff8cda50911988d0a0d6d36d8c267',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r2_5ffb3_424',['CAN_F10R2_FB3',['../group___peripheral___registers___bits___definition.html#ga2348cdfff622628147e2c1df0a35363c',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r2_5ffb30_425',['CAN_F10R2_FB30',['../group___peripheral___registers___bits___definition.html#gab294aa73a3fdfc60672b206bd57a1e08',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r2_5ffb30_5fmsk_426',['CAN_F10R2_FB30_Msk',['../group___peripheral___registers___bits___definition.html#ga9d7ed61987ecdd8236e5236edc35946f',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r2_5ffb30_5fpos_427',['CAN_F10R2_FB30_Pos',['../group___peripheral___registers___bits___definition.html#ga20abbd298e588db3094637ad1b76b0fb',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r2_5ffb31_428',['CAN_F10R2_FB31',['../group___peripheral___registers___bits___definition.html#ga2de1906dc4119b37b29bbe25e3e6dbe0',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r2_5ffb31_5fmsk_429',['CAN_F10R2_FB31_Msk',['../group___peripheral___registers___bits___definition.html#ga6278728b6cc74ad7d4bc41d6014839f3',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r2_5ffb31_5fpos_430',['CAN_F10R2_FB31_Pos',['../group___peripheral___registers___bits___definition.html#ga1c0d5f4f54822978cc2fb6d8e46d532f',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r2_5ffb3_5fmsk_431',['CAN_F10R2_FB3_Msk',['../group___peripheral___registers___bits___definition.html#ga0fd1293748da16cb1139224b528082c4',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r2_5ffb3_5fpos_432',['CAN_F10R2_FB3_Pos',['../group___peripheral___registers___bits___definition.html#gae61032600bc3bbd5751c1883555311ae',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r2_5ffb4_433',['CAN_F10R2_FB4',['../group___peripheral___registers___bits___definition.html#gaebde0ea1e0aaf38fdcf1584e9c9b2063',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r2_5ffb4_5fmsk_434',['CAN_F10R2_FB4_Msk',['../group___peripheral___registers___bits___definition.html#ga445fedfbaf84b454483c73e6b72bedfe',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r2_5ffb4_5fpos_435',['CAN_F10R2_FB4_Pos',['../group___peripheral___registers___bits___definition.html#ga3bde5e4239f61759d51e0eda6b788e7e',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r2_5ffb5_436',['CAN_F10R2_FB5',['../group___peripheral___registers___bits___definition.html#ga3b5b32b71c86c6dc7040b3044be61af7',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r2_5ffb5_5fmsk_437',['CAN_F10R2_FB5_Msk',['../group___peripheral___registers___bits___definition.html#ga26b37e77455ba2d98eee41464c2fe039',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r2_5ffb5_5fpos_438',['CAN_F10R2_FB5_Pos',['../group___peripheral___registers___bits___definition.html#gabdd558b92af16682b2ebd3b573a1a07b',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r2_5ffb6_439',['CAN_F10R2_FB6',['../group___peripheral___registers___bits___definition.html#ga9df7daa799c7c73d9a56de5f92285aca',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r2_5ffb6_5fmsk_440',['CAN_F10R2_FB6_Msk',['../group___peripheral___registers___bits___definition.html#ga42f57e8c16bb81bb9291c5ebb4a04b1a',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r2_5ffb6_5fpos_441',['CAN_F10R2_FB6_Pos',['../group___peripheral___registers___bits___definition.html#ga7351a6a4b667479d490e6146b8cd9b41',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r2_5ffb7_442',['CAN_F10R2_FB7',['../group___peripheral___registers___bits___definition.html#gaed755173b9d4375b40d73cab90396adc',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r2_5ffb7_5fmsk_443',['CAN_F10R2_FB7_Msk',['../group___peripheral___registers___bits___definition.html#gac6d86237a0fff09a8f49360d47f28d05',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r2_5ffb7_5fpos_444',['CAN_F10R2_FB7_Pos',['../group___peripheral___registers___bits___definition.html#ga061fd86dd7cab205318a1b63c443c0f9',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r2_5ffb8_445',['CAN_F10R2_FB8',['../group___peripheral___registers___bits___definition.html#ga8a8d08fea6e7307f6d1d602e113a6d27',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r2_5ffb8_5fmsk_446',['CAN_F10R2_FB8_Msk',['../group___peripheral___registers___bits___definition.html#gad459c18ab4e613bb142e5c1f78691bb8',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r2_5ffb8_5fpos_447',['CAN_F10R2_FB8_Pos',['../group___peripheral___registers___bits___definition.html#ga31ba127731d0de563aabf8397b0011ac',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r2_5ffb9_448',['CAN_F10R2_FB9',['../group___peripheral___registers___bits___definition.html#ga6aecdda55a484aa0e96c89f5d0f42aba',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r2_5ffb9_5fmsk_449',['CAN_F10R2_FB9_Msk',['../group___peripheral___registers___bits___definition.html#gae5ac6067a7226de096a846276a7770e9',1,'stm32f407xx_matlab.h']]], - ['can_5ff10r2_5ffb9_5fpos_450',['CAN_F10R2_FB9_Pos',['../group___peripheral___registers___bits___definition.html#ga3d043efe65c029bd4849d543b3d5b9c4',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r1_5ffb0_451',['CAN_F11R1_FB0',['../group___peripheral___registers___bits___definition.html#gad059cc9b2fe5634b9330b44c37dadf06',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r1_5ffb0_5fmsk_452',['CAN_F11R1_FB0_Msk',['../group___peripheral___registers___bits___definition.html#ga29cf61e4385aa30fbdff533d51bdd612',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r1_5ffb0_5fpos_453',['CAN_F11R1_FB0_Pos',['../group___peripheral___registers___bits___definition.html#gad825b1610c2deb52c7e2a14d4ffb33ae',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r1_5ffb1_454',['CAN_F11R1_FB1',['../group___peripheral___registers___bits___definition.html#gad74b116cda63fcd1a662c4de835616e7',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r1_5ffb10_455',['CAN_F11R1_FB10',['../group___peripheral___registers___bits___definition.html#ga1e858dd29f741910c8ed8c512cae81b1',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r1_5ffb10_5fmsk_456',['CAN_F11R1_FB10_Msk',['../group___peripheral___registers___bits___definition.html#gab7cb55bd09dade7046aa52361411fb68',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r1_5ffb10_5fpos_457',['CAN_F11R1_FB10_Pos',['../group___peripheral___registers___bits___definition.html#ga8ccf16da47b6e8c9a396eaca7ae390d7',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r1_5ffb11_458',['CAN_F11R1_FB11',['../group___peripheral___registers___bits___definition.html#gaf6ba167c6cd5bc080065430e24c3a866',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r1_5ffb11_5fmsk_459',['CAN_F11R1_FB11_Msk',['../group___peripheral___registers___bits___definition.html#ga6235ef02d18d862d4018aa9d3f2612bd',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r1_5ffb11_5fpos_460',['CAN_F11R1_FB11_Pos',['../group___peripheral___registers___bits___definition.html#ga91b2fe2b66aa2708feafdf1b5fac1a5d',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r1_5ffb12_461',['CAN_F11R1_FB12',['../group___peripheral___registers___bits___definition.html#ga4629ab1e8632c82f3fb2648a574963b1',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r1_5ffb12_5fmsk_462',['CAN_F11R1_FB12_Msk',['../group___peripheral___registers___bits___definition.html#ga488ce892527f6e05b74c72d3540e86e9',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r1_5ffb12_5fpos_463',['CAN_F11R1_FB12_Pos',['../group___peripheral___registers___bits___definition.html#gac8638152a30201e227efb08a7239a9a1',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r1_5ffb13_464',['CAN_F11R1_FB13',['../group___peripheral___registers___bits___definition.html#ga833c408a165cc4ac87a242c08d4ba9b9',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r1_5ffb13_5fmsk_465',['CAN_F11R1_FB13_Msk',['../group___peripheral___registers___bits___definition.html#ga34726d941ba918d973035cdfd4956f22',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r1_5ffb13_5fpos_466',['CAN_F11R1_FB13_Pos',['../group___peripheral___registers___bits___definition.html#ga0b4ada853a29ea4b6975619939ad6aeb',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r1_5ffb14_467',['CAN_F11R1_FB14',['../group___peripheral___registers___bits___definition.html#gabfecd6bbe1a15cd341942d1840b476cc',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r1_5ffb14_5fmsk_468',['CAN_F11R1_FB14_Msk',['../group___peripheral___registers___bits___definition.html#ga0a261d1beaaa14ef8021eaa305b4cdf6',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r1_5ffb14_5fpos_469',['CAN_F11R1_FB14_Pos',['../group___peripheral___registers___bits___definition.html#ga623aadd0e75b5b15052e0ee6db31b9e8',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r1_5ffb15_470',['CAN_F11R1_FB15',['../group___peripheral___registers___bits___definition.html#gaf50e1747d1d9369b7b22c5d591ae82b9',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r1_5ffb15_5fmsk_471',['CAN_F11R1_FB15_Msk',['../group___peripheral___registers___bits___definition.html#gaddc324a22f00abfe9bcf15478238eeda',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r1_5ffb15_5fpos_472',['CAN_F11R1_FB15_Pos',['../group___peripheral___registers___bits___definition.html#ga2162c84a2aee3dc40f2822bbf8967b5d',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r1_5ffb16_473',['CAN_F11R1_FB16',['../group___peripheral___registers___bits___definition.html#ga603d63333a621594a15696cb03f59eeb',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r1_5ffb16_5fmsk_474',['CAN_F11R1_FB16_Msk',['../group___peripheral___registers___bits___definition.html#ga67cc7cf7f00a9e32c2bd48dcd4941eeb',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r1_5ffb16_5fpos_475',['CAN_F11R1_FB16_Pos',['../group___peripheral___registers___bits___definition.html#gaf2464caefce933de15008f8e10a0229a',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r1_5ffb17_476',['CAN_F11R1_FB17',['../group___peripheral___registers___bits___definition.html#gadb361a00177e6aa2ee19aa5a2d1781aa',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r1_5ffb17_5fmsk_477',['CAN_F11R1_FB17_Msk',['../group___peripheral___registers___bits___definition.html#ga5442d8600f85b1f2efb8cd2a0a9ec764',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r1_5ffb17_5fpos_478',['CAN_F11R1_FB17_Pos',['../group___peripheral___registers___bits___definition.html#gac59287ed65d1bab31859947cf1c0e520',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r1_5ffb18_479',['CAN_F11R1_FB18',['../group___peripheral___registers___bits___definition.html#gaf111110e0f5dbda31962f7732e3480c7',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r1_5ffb18_5fmsk_480',['CAN_F11R1_FB18_Msk',['../group___peripheral___registers___bits___definition.html#ga882ce3ab193542e376fb5f6d4f497a46',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r1_5ffb18_5fpos_481',['CAN_F11R1_FB18_Pos',['../group___peripheral___registers___bits___definition.html#gadd205d1cabe770ac20592d94a9a59a02',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r1_5ffb19_482',['CAN_F11R1_FB19',['../group___peripheral___registers___bits___definition.html#gabf2c4828b07b2b315d27b382818de285',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r1_5ffb19_5fmsk_483',['CAN_F11R1_FB19_Msk',['../group___peripheral___registers___bits___definition.html#ga3d345cf87d73bed1e41d1fdd1da16378',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r1_5ffb19_5fpos_484',['CAN_F11R1_FB19_Pos',['../group___peripheral___registers___bits___definition.html#gacdda7d2445b53f67f690c62be9246090',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r1_5ffb1_5fmsk_485',['CAN_F11R1_FB1_Msk',['../group___peripheral___registers___bits___definition.html#ga1e4ad3f7a5ffa1fd9136447924950ea6',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r1_5ffb1_5fpos_486',['CAN_F11R1_FB1_Pos',['../group___peripheral___registers___bits___definition.html#ga786a94d3ab775de9da9195130b1b76bb',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r1_5ffb2_487',['CAN_F11R1_FB2',['../group___peripheral___registers___bits___definition.html#ga4e05bb0c2a5bdcebb974f7dd409724bc',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r1_5ffb20_488',['CAN_F11R1_FB20',['../group___peripheral___registers___bits___definition.html#ga5afa52941bb68a03ec9804b817d5a90e',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r1_5ffb20_5fmsk_489',['CAN_F11R1_FB20_Msk',['../group___peripheral___registers___bits___definition.html#gad7955a656970b266f1398cdfc4bdb6cb',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r1_5ffb20_5fpos_490',['CAN_F11R1_FB20_Pos',['../group___peripheral___registers___bits___definition.html#ga0bc43b832b438ebbad185e628f43c46c',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r1_5ffb21_491',['CAN_F11R1_FB21',['../group___peripheral___registers___bits___definition.html#gac042471dbcb1a32ce161f38a144ac5aa',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r1_5ffb21_5fmsk_492',['CAN_F11R1_FB21_Msk',['../group___peripheral___registers___bits___definition.html#ga0a5b2c12419c4cff708970be601ad3e2',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r1_5ffb21_5fpos_493',['CAN_F11R1_FB21_Pos',['../group___peripheral___registers___bits___definition.html#ga407a5d20941e9430ed2d0a146328ac31',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r1_5ffb22_494',['CAN_F11R1_FB22',['../group___peripheral___registers___bits___definition.html#gaac46f233c9692cb2a2e246daf6547a38',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r1_5ffb22_5fmsk_495',['CAN_F11R1_FB22_Msk',['../group___peripheral___registers___bits___definition.html#ga5ad2a3cd3442663331b96444d1ed798e',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r1_5ffb22_5fpos_496',['CAN_F11R1_FB22_Pos',['../group___peripheral___registers___bits___definition.html#gae2af39e6af45c497fc6f8f9e21892aff',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r1_5ffb23_497',['CAN_F11R1_FB23',['../group___peripheral___registers___bits___definition.html#gab8b379e3832482f2b18f01713d3338d5',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r1_5ffb23_5fmsk_498',['CAN_F11R1_FB23_Msk',['../group___peripheral___registers___bits___definition.html#ga0869365b6223739ccb3b62cfadd9f1db',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r1_5ffb23_5fpos_499',['CAN_F11R1_FB23_Pos',['../group___peripheral___registers___bits___definition.html#ga413238cb6d5869b63b343f15b589a7d0',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r1_5ffb24_500',['CAN_F11R1_FB24',['../group___peripheral___registers___bits___definition.html#ga60eabd8db9ec6b439d60dbc2374ce84d',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r1_5ffb24_5fmsk_501',['CAN_F11R1_FB24_Msk',['../group___peripheral___registers___bits___definition.html#ga4ed24f7ad9ae64b130e3e2ce65cf5d04',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r1_5ffb24_5fpos_502',['CAN_F11R1_FB24_Pos',['../group___peripheral___registers___bits___definition.html#gac72a9af5034ed0aedfb37bf45717785f',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r1_5ffb25_503',['CAN_F11R1_FB25',['../group___peripheral___registers___bits___definition.html#ga351a183cfab10d3daab415c85cc16203',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r1_5ffb25_5fmsk_504',['CAN_F11R1_FB25_Msk',['../group___peripheral___registers___bits___definition.html#ga9c2fdd934f06f41139da93cf271c9e5b',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r1_5ffb25_5fpos_505',['CAN_F11R1_FB25_Pos',['../group___peripheral___registers___bits___definition.html#ga3375fdb7a20bb2603e470ceefb5ea811',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r1_5ffb26_506',['CAN_F11R1_FB26',['../group___peripheral___registers___bits___definition.html#gabb854a85c7a575a45cdade37efb4edee',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r1_5ffb26_5fmsk_507',['CAN_F11R1_FB26_Msk',['../group___peripheral___registers___bits___definition.html#ga547f899b4aaa6323c75dc4660cc6dd4e',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r1_5ffb26_5fpos_508',['CAN_F11R1_FB26_Pos',['../group___peripheral___registers___bits___definition.html#ga856a5c13143c62e9fe351bc40419273a',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r1_5ffb27_509',['CAN_F11R1_FB27',['../group___peripheral___registers___bits___definition.html#ga131776c359f81500d3d2a97535d7e718',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r1_5ffb27_5fmsk_510',['CAN_F11R1_FB27_Msk',['../group___peripheral___registers___bits___definition.html#ga5499db54e781ed6a09c987857d851e4b',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r1_5ffb27_5fpos_511',['CAN_F11R1_FB27_Pos',['../group___peripheral___registers___bits___definition.html#ga4bc7863389837d8c6e58d46c87543339',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r1_5ffb28_512',['CAN_F11R1_FB28',['../group___peripheral___registers___bits___definition.html#ga680d7e4c7ebc431a8c72c00e9f110563',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r1_5ffb28_5fmsk_513',['CAN_F11R1_FB28_Msk',['../group___peripheral___registers___bits___definition.html#ga80b8ed435fa7866580be0ec7cfada3ce',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r1_5ffb28_5fpos_514',['CAN_F11R1_FB28_Pos',['../group___peripheral___registers___bits___definition.html#ga6146861f9546873f507b6ec159010caf',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r1_5ffb29_515',['CAN_F11R1_FB29',['../group___peripheral___registers___bits___definition.html#ga9c1fa00ee18804c169541d18995dc3c1',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r1_5ffb29_5fmsk_516',['CAN_F11R1_FB29_Msk',['../group___peripheral___registers___bits___definition.html#ga2fa11c1e2e43d9234f768ca5f3db3521',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r1_5ffb29_5fpos_517',['CAN_F11R1_FB29_Pos',['../group___peripheral___registers___bits___definition.html#ga14db22bec110547f85af0a1d37723bdc',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r1_5ffb2_5fmsk_518',['CAN_F11R1_FB2_Msk',['../group___peripheral___registers___bits___definition.html#ga5614e1e331777400a4903b74f3398d1c',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r1_5ffb2_5fpos_519',['CAN_F11R1_FB2_Pos',['../group___peripheral___registers___bits___definition.html#ga9b59aee05e1add366c493e4ccd2637c5',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r1_5ffb3_520',['CAN_F11R1_FB3',['../group___peripheral___registers___bits___definition.html#gaa17242aed4365034dc660ef9e8b9f1bf',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r1_5ffb30_521',['CAN_F11R1_FB30',['../group___peripheral___registers___bits___definition.html#gaec35d8d1097816c5ef8e28ff61469669',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r1_5ffb30_5fmsk_522',['CAN_F11R1_FB30_Msk',['../group___peripheral___registers___bits___definition.html#ga665b624ef9be8a7b67fd0d0c8a2cc28d',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r1_5ffb30_5fpos_523',['CAN_F11R1_FB30_Pos',['../group___peripheral___registers___bits___definition.html#gaed80cbf06c649fa59a60cc19bffb3ca5',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r1_5ffb31_524',['CAN_F11R1_FB31',['../group___peripheral___registers___bits___definition.html#ga96180b8c64aabd33f016fb97ba152f07',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r1_5ffb31_5fmsk_525',['CAN_F11R1_FB31_Msk',['../group___peripheral___registers___bits___definition.html#gafb79224e74be4064c186c1fd8f430b3f',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r1_5ffb31_5fpos_526',['CAN_F11R1_FB31_Pos',['../group___peripheral___registers___bits___definition.html#gac933da1992c44dc61bea38e44c376f01',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r1_5ffb3_5fmsk_527',['CAN_F11R1_FB3_Msk',['../group___peripheral___registers___bits___definition.html#ga3cf6f2e8167bd44d1f02ff8de4574d4d',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r1_5ffb3_5fpos_528',['CAN_F11R1_FB3_Pos',['../group___peripheral___registers___bits___definition.html#ga9db6817cdb088212132aebd6b1e6fadb',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r1_5ffb4_529',['CAN_F11R1_FB4',['../group___peripheral___registers___bits___definition.html#ga450dbed19882423d70ed7606aada2453',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r1_5ffb4_5fmsk_530',['CAN_F11R1_FB4_Msk',['../group___peripheral___registers___bits___definition.html#ga1ab99e31bdf86aaad8ba7d6ad75ba7dc',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r1_5ffb4_5fpos_531',['CAN_F11R1_FB4_Pos',['../group___peripheral___registers___bits___definition.html#gaefa798693295399620c2a62defb02ad5',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r1_5ffb5_532',['CAN_F11R1_FB5',['../group___peripheral___registers___bits___definition.html#gad7ace73f2d3db1e2a1e55257d210fa04',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r1_5ffb5_5fmsk_533',['CAN_F11R1_FB5_Msk',['../group___peripheral___registers___bits___definition.html#ga554f40a4480434bf6e3633e52d45e6bd',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r1_5ffb5_5fpos_534',['CAN_F11R1_FB5_Pos',['../group___peripheral___registers___bits___definition.html#gabf95e8d5586045005c6fc0dbb9d42017',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r1_5ffb6_535',['CAN_F11R1_FB6',['../group___peripheral___registers___bits___definition.html#ga1459d395a3b08a948c3f5002e0914516',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r1_5ffb6_5fmsk_536',['CAN_F11R1_FB6_Msk',['../group___peripheral___registers___bits___definition.html#ga4aed14b088705fde497369d39675369e',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r1_5ffb6_5fpos_537',['CAN_F11R1_FB6_Pos',['../group___peripheral___registers___bits___definition.html#ga33946da5363485ee484a5fd3b977068d',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r1_5ffb7_538',['CAN_F11R1_FB7',['../group___peripheral___registers___bits___definition.html#ga30fc2236c2a18b7cb6e493fad36d8efe',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r1_5ffb7_5fmsk_539',['CAN_F11R1_FB7_Msk',['../group___peripheral___registers___bits___definition.html#ga8580e565ee4bc7966aa7c515d6fab446',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r1_5ffb7_5fpos_540',['CAN_F11R1_FB7_Pos',['../group___peripheral___registers___bits___definition.html#ga390e032609e5d44f7dd0c7e9d2f5ee16',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r1_5ffb8_541',['CAN_F11R1_FB8',['../group___peripheral___registers___bits___definition.html#ga74ab4a6f6b5a751acda410e0c39b87af',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r1_5ffb8_5fmsk_542',['CAN_F11R1_FB8_Msk',['../group___peripheral___registers___bits___definition.html#ga639a8dc5a46ee8b2a380ac7978fb0672',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r1_5ffb8_5fpos_543',['CAN_F11R1_FB8_Pos',['../group___peripheral___registers___bits___definition.html#ga73563f8f0592450f6c15ad9d91495e62',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r1_5ffb9_544',['CAN_F11R1_FB9',['../group___peripheral___registers___bits___definition.html#ga4e69f7001534264fd027371fa188ac52',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r1_5ffb9_5fmsk_545',['CAN_F11R1_FB9_Msk',['../group___peripheral___registers___bits___definition.html#ga0cd49481651b80f8fdcf08efd0e07f8c',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r1_5ffb9_5fpos_546',['CAN_F11R1_FB9_Pos',['../group___peripheral___registers___bits___definition.html#ga01de290d95f18b06e6aed12bb01cbe88',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r2_5ffb0_547',['CAN_F11R2_FB0',['../group___peripheral___registers___bits___definition.html#gacad6560088b586891d446952bbd8fbbe',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r2_5ffb0_5fmsk_548',['CAN_F11R2_FB0_Msk',['../group___peripheral___registers___bits___definition.html#ga756b9a7f35ddb243019a737cc9c5d4aa',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r2_5ffb0_5fpos_549',['CAN_F11R2_FB0_Pos',['../group___peripheral___registers___bits___definition.html#gad70c5d7ca84956020778f4467b9e66ba',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r2_5ffb1_550',['CAN_F11R2_FB1',['../group___peripheral___registers___bits___definition.html#gac81bc667cb0c63aa0448f6e0eb1d105d',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r2_5ffb10_551',['CAN_F11R2_FB10',['../group___peripheral___registers___bits___definition.html#ga9dad5ea347a6a928997a0a1c149369ce',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r2_5ffb10_5fmsk_552',['CAN_F11R2_FB10_Msk',['../group___peripheral___registers___bits___definition.html#ga3d867bbf2aeec0751fb8d9bc028a3e20',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r2_5ffb10_5fpos_553',['CAN_F11R2_FB10_Pos',['../group___peripheral___registers___bits___definition.html#ga3cda459a8f36d3ebc3b572df16998ad2',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r2_5ffb11_554',['CAN_F11R2_FB11',['../group___peripheral___registers___bits___definition.html#ga9285109080a523012f27b3bdbabc6949',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r2_5ffb11_5fmsk_555',['CAN_F11R2_FB11_Msk',['../group___peripheral___registers___bits___definition.html#ga6f02c0270c8560877a6849dc3ec12734',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r2_5ffb11_5fpos_556',['CAN_F11R2_FB11_Pos',['../group___peripheral___registers___bits___definition.html#gae9aed466e0487ccf8da142590ea6a0c9',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r2_5ffb12_557',['CAN_F11R2_FB12',['../group___peripheral___registers___bits___definition.html#ga65cdf759738f8b0cb8c4c3231453aad8',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r2_5ffb12_5fmsk_558',['CAN_F11R2_FB12_Msk',['../group___peripheral___registers___bits___definition.html#ga7f27deb61d7cecd98a3707baeee44c33',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r2_5ffb12_5fpos_559',['CAN_F11R2_FB12_Pos',['../group___peripheral___registers___bits___definition.html#gac9f6c874f151de08d9e16f7f25e69519',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r2_5ffb13_560',['CAN_F11R2_FB13',['../group___peripheral___registers___bits___definition.html#ga24a40efa6debcdcfef0f7ab6d8b3eb04',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r2_5ffb13_5fmsk_561',['CAN_F11R2_FB13_Msk',['../group___peripheral___registers___bits___definition.html#ga4e89abf41152c9c443eec298c3c4ee0a',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r2_5ffb13_5fpos_562',['CAN_F11R2_FB13_Pos',['../group___peripheral___registers___bits___definition.html#ga466d8e9611e69bfd911aeab18a24f790',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r2_5ffb14_563',['CAN_F11R2_FB14',['../group___peripheral___registers___bits___definition.html#gaa923634a3432436c4c84e65be1fd39d6',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r2_5ffb14_5fmsk_564',['CAN_F11R2_FB14_Msk',['../group___peripheral___registers___bits___definition.html#gaf385990b78e0ad2903adf8ca5d31592d',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r2_5ffb14_5fpos_565',['CAN_F11R2_FB14_Pos',['../group___peripheral___registers___bits___definition.html#ga06aa722740f4a12a01fcec5930b44e4e',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r2_5ffb15_566',['CAN_F11R2_FB15',['../group___peripheral___registers___bits___definition.html#ga65bae4ee01f83fe051acee8ee4c8a10e',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r2_5ffb15_5fmsk_567',['CAN_F11R2_FB15_Msk',['../group___peripheral___registers___bits___definition.html#gac617eb6a2c9da89608e9a1fd20bedb05',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r2_5ffb15_5fpos_568',['CAN_F11R2_FB15_Pos',['../group___peripheral___registers___bits___definition.html#ga1084133f89fd1b056a0001b496010b9e',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r2_5ffb16_569',['CAN_F11R2_FB16',['../group___peripheral___registers___bits___definition.html#ga7b6762f3642ce7a06fff58270ac9f53f',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r2_5ffb16_5fmsk_570',['CAN_F11R2_FB16_Msk',['../group___peripheral___registers___bits___definition.html#ga2f7a12de16318eca8c069f7a4a107ba4',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r2_5ffb16_5fpos_571',['CAN_F11R2_FB16_Pos',['../group___peripheral___registers___bits___definition.html#ga7c28a61b0bd631ca5fe08c4aa30f9567',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r2_5ffb17_572',['CAN_F11R2_FB17',['../group___peripheral___registers___bits___definition.html#ga69c7d6a41708543278980035b64bd31b',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r2_5ffb17_5fmsk_573',['CAN_F11R2_FB17_Msk',['../group___peripheral___registers___bits___definition.html#ga6194082f1b79eacc5490d6c4571f2993',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r2_5ffb17_5fpos_574',['CAN_F11R2_FB17_Pos',['../group___peripheral___registers___bits___definition.html#gae4a696446a3ba4010fe43d401efc22b8',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r2_5ffb18_575',['CAN_F11R2_FB18',['../group___peripheral___registers___bits___definition.html#ga88d6d67020cbc5a4d5f0b7c5dc488aa6',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r2_5ffb18_5fmsk_576',['CAN_F11R2_FB18_Msk',['../group___peripheral___registers___bits___definition.html#ga578e9b0b0fc78522d232926aa5a474b4',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r2_5ffb18_5fpos_577',['CAN_F11R2_FB18_Pos',['../group___peripheral___registers___bits___definition.html#ga87528786c246818857315a7728117d16',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r2_5ffb19_578',['CAN_F11R2_FB19',['../group___peripheral___registers___bits___definition.html#ga07f4a8d606f2063be35b52e1fc5e4b58',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r2_5ffb19_5fmsk_579',['CAN_F11R2_FB19_Msk',['../group___peripheral___registers___bits___definition.html#ga4aa7935ffacb2eb500c03e6f297c9abf',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r2_5ffb19_5fpos_580',['CAN_F11R2_FB19_Pos',['../group___peripheral___registers___bits___definition.html#gaeb57ae932a28d7bae3af99c7cc73d6f0',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r2_5ffb1_5fmsk_581',['CAN_F11R2_FB1_Msk',['../group___peripheral___registers___bits___definition.html#ga73175a30063e3781dd1b5ee2b9ff5c7c',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r2_5ffb1_5fpos_582',['CAN_F11R2_FB1_Pos',['../group___peripheral___registers___bits___definition.html#gaa225421da3627c8bf8e836c516c36ff9',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r2_5ffb2_583',['CAN_F11R2_FB2',['../group___peripheral___registers___bits___definition.html#ga8dab8868637d6d6fb707b6a37a5989b5',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r2_5ffb20_584',['CAN_F11R2_FB20',['../group___peripheral___registers___bits___definition.html#ga58c6e5b0076c31b7bee1c9aea94e11fb',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r2_5ffb20_5fmsk_585',['CAN_F11R2_FB20_Msk',['../group___peripheral___registers___bits___definition.html#gaecca1f88d1ccfd94c942c1dba195f566',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r2_5ffb20_5fpos_586',['CAN_F11R2_FB20_Pos',['../group___peripheral___registers___bits___definition.html#gac77f12ec2cab52d721629fe0ae73c093',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r2_5ffb21_587',['CAN_F11R2_FB21',['../group___peripheral___registers___bits___definition.html#ga93bf815d462dc3a40725f73e107e11f5',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r2_5ffb21_5fmsk_588',['CAN_F11R2_FB21_Msk',['../group___peripheral___registers___bits___definition.html#ga26b076a8a45e423f12d66b72888a62c1',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r2_5ffb21_5fpos_589',['CAN_F11R2_FB21_Pos',['../group___peripheral___registers___bits___definition.html#gabbc3adfab5e37044e4b71efcd3e045c3',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r2_5ffb22_590',['CAN_F11R2_FB22',['../group___peripheral___registers___bits___definition.html#gaeebe934727476f5fde11c888c424c417',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r2_5ffb22_5fmsk_591',['CAN_F11R2_FB22_Msk',['../group___peripheral___registers___bits___definition.html#ga69a3601ecccef7d68dceacf69694f57c',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r2_5ffb22_5fpos_592',['CAN_F11R2_FB22_Pos',['../group___peripheral___registers___bits___definition.html#gabfb18cb42280379ea211f97dda828964',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r2_5ffb23_593',['CAN_F11R2_FB23',['../group___peripheral___registers___bits___definition.html#ga8324877e56a61c15119f2ebf929894cc',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r2_5ffb23_5fmsk_594',['CAN_F11R2_FB23_Msk',['../group___peripheral___registers___bits___definition.html#ga9acb53490837c29f03538f37e92ab7b0',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r2_5ffb23_5fpos_595',['CAN_F11R2_FB23_Pos',['../group___peripheral___registers___bits___definition.html#ga56baa11c41451f4e27adb7df35046d74',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r2_5ffb24_596',['CAN_F11R2_FB24',['../group___peripheral___registers___bits___definition.html#gadfd994c36da11529ac494df973b5759c',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r2_5ffb24_5fmsk_597',['CAN_F11R2_FB24_Msk',['../group___peripheral___registers___bits___definition.html#ga54d08ee868e97a722b5e25b145581435',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r2_5ffb24_5fpos_598',['CAN_F11R2_FB24_Pos',['../group___peripheral___registers___bits___definition.html#ga09624fe67ae7144c103e70325bb4bbd9',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r2_5ffb25_599',['CAN_F11R2_FB25',['../group___peripheral___registers___bits___definition.html#ga8f3e9d272b625f7d6269057aee5d7761',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r2_5ffb25_5fmsk_600',['CAN_F11R2_FB25_Msk',['../group___peripheral___registers___bits___definition.html#ga1e9aaac92b7b5c524dfd488651f66d1b',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r2_5ffb25_5fpos_601',['CAN_F11R2_FB25_Pos',['../group___peripheral___registers___bits___definition.html#gadeeb62a3987c1ad5b7bd6ed7424c4a1b',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r2_5ffb26_602',['CAN_F11R2_FB26',['../group___peripheral___registers___bits___definition.html#ga5da4d794a9797d14536197679b7b2b14',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r2_5ffb26_5fmsk_603',['CAN_F11R2_FB26_Msk',['../group___peripheral___registers___bits___definition.html#ga769efd27c8d450433589d3a59e4b49b7',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r2_5ffb26_5fpos_604',['CAN_F11R2_FB26_Pos',['../group___peripheral___registers___bits___definition.html#gaa50568c5112b9d364a4a1a6a7d668ba2',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r2_5ffb27_605',['CAN_F11R2_FB27',['../group___peripheral___registers___bits___definition.html#gad9b9a815f36e7c2929f4313ca424c83a',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r2_5ffb27_5fmsk_606',['CAN_F11R2_FB27_Msk',['../group___peripheral___registers___bits___definition.html#ga38daca04f9249b41d451122bfcb63b2d',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r2_5ffb27_5fpos_607',['CAN_F11R2_FB27_Pos',['../group___peripheral___registers___bits___definition.html#gabc07b263056b681c3834e366c8cb060e',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r2_5ffb28_608',['CAN_F11R2_FB28',['../group___peripheral___registers___bits___definition.html#gaf162471f4c070d13fa409d44467373fc',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r2_5ffb28_5fmsk_609',['CAN_F11R2_FB28_Msk',['../group___peripheral___registers___bits___definition.html#gadb214fcb4208a4d5db09465c5260d5e4',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r2_5ffb28_5fpos_610',['CAN_F11R2_FB28_Pos',['../group___peripheral___registers___bits___definition.html#ga70db281007bc66b283e8bb8f0dc05af4',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r2_5ffb29_611',['CAN_F11R2_FB29',['../group___peripheral___registers___bits___definition.html#ga2c301fd37e3fa27d3bd28a1f3f553e77',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r2_5ffb29_5fmsk_612',['CAN_F11R2_FB29_Msk',['../group___peripheral___registers___bits___definition.html#ga10d6ff5e482dc1d88d0f39a0e2329427',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r2_5ffb29_5fpos_613',['CAN_F11R2_FB29_Pos',['../group___peripheral___registers___bits___definition.html#ga111f04007588ff775bbd03d30f7e1bb7',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r2_5ffb2_5fmsk_614',['CAN_F11R2_FB2_Msk',['../group___peripheral___registers___bits___definition.html#ga43042d452e6efb4e24fecc0ef71f0b53',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r2_5ffb2_5fpos_615',['CAN_F11R2_FB2_Pos',['../group___peripheral___registers___bits___definition.html#ga70986cdccec7c3a2997094e5a026ea7d',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r2_5ffb3_616',['CAN_F11R2_FB3',['../group___peripheral___registers___bits___definition.html#ga559246cfa4658a5adaa282e4a3b35dd5',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r2_5ffb30_617',['CAN_F11R2_FB30',['../group___peripheral___registers___bits___definition.html#ga2bdc4ba1d0e44ba4d7a03cfd3197b687',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r2_5ffb30_5fmsk_618',['CAN_F11R2_FB30_Msk',['../group___peripheral___registers___bits___definition.html#ga7be4778f941b5287fcc39a5ce3724e71',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r2_5ffb30_5fpos_619',['CAN_F11R2_FB30_Pos',['../group___peripheral___registers___bits___definition.html#ga537283f338bc941c2749698732cba679',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r2_5ffb31_620',['CAN_F11R2_FB31',['../group___peripheral___registers___bits___definition.html#ga6525c1ff364a229c9ea1b353b11be8c3',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r2_5ffb31_5fmsk_621',['CAN_F11R2_FB31_Msk',['../group___peripheral___registers___bits___definition.html#ga4f08f45859f87d045ab080dd511302bd',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r2_5ffb31_5fpos_622',['CAN_F11R2_FB31_Pos',['../group___peripheral___registers___bits___definition.html#gaa7120051826cab6e84712aafd60e7f0e',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r2_5ffb3_5fmsk_623',['CAN_F11R2_FB3_Msk',['../group___peripheral___registers___bits___definition.html#ga603a033a522647ec072b27204f411c27',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r2_5ffb3_5fpos_624',['CAN_F11R2_FB3_Pos',['../group___peripheral___registers___bits___definition.html#gae4404f58525379b7462074c1f4d94abc',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r2_5ffb4_625',['CAN_F11R2_FB4',['../group___peripheral___registers___bits___definition.html#ga499aebdfc0c14b9c399698e28fde3e50',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r2_5ffb4_5fmsk_626',['CAN_F11R2_FB4_Msk',['../group___peripheral___registers___bits___definition.html#gaf7f3cc6f8734688ffd55f0eae6d8a3e1',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r2_5ffb4_5fpos_627',['CAN_F11R2_FB4_Pos',['../group___peripheral___registers___bits___definition.html#ga83a62db93a855fc670d041db3f95f7ce',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r2_5ffb5_628',['CAN_F11R2_FB5',['../group___peripheral___registers___bits___definition.html#ga1613d097fe5b7107ff36f97a9263bd38',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r2_5ffb5_5fmsk_629',['CAN_F11R2_FB5_Msk',['../group___peripheral___registers___bits___definition.html#ga100d5a8929cac40dc2d8d6bfaf2effb0',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r2_5ffb5_5fpos_630',['CAN_F11R2_FB5_Pos',['../group___peripheral___registers___bits___definition.html#ga24cd2b60689ccae14ae3254487a564b9',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r2_5ffb6_631',['CAN_F11R2_FB6',['../group___peripheral___registers___bits___definition.html#ga9db1830185822d66619059a644d86ffe',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r2_5ffb6_5fmsk_632',['CAN_F11R2_FB6_Msk',['../group___peripheral___registers___bits___definition.html#gab2541f8510aa2f59dd2b2cfbf1bc99c1',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r2_5ffb6_5fpos_633',['CAN_F11R2_FB6_Pos',['../group___peripheral___registers___bits___definition.html#ga595220fc83b10a19867b00b7bc58221f',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r2_5ffb7_634',['CAN_F11R2_FB7',['../group___peripheral___registers___bits___definition.html#gab35bedade0c9f71455abfbbac2edee14',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r2_5ffb7_5fmsk_635',['CAN_F11R2_FB7_Msk',['../group___peripheral___registers___bits___definition.html#ga2739365d7644847c2b2e9424b5361782',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r2_5ffb7_5fpos_636',['CAN_F11R2_FB7_Pos',['../group___peripheral___registers___bits___definition.html#ga196fb045bc38774e8d3b9c18345f799e',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r2_5ffb8_637',['CAN_F11R2_FB8',['../group___peripheral___registers___bits___definition.html#gac79ac007ffed536eedddffdd2615c5f7',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r2_5ffb8_5fmsk_638',['CAN_F11R2_FB8_Msk',['../group___peripheral___registers___bits___definition.html#ga7159e2db436359c52f6db1dda067a7c2',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r2_5ffb8_5fpos_639',['CAN_F11R2_FB8_Pos',['../group___peripheral___registers___bits___definition.html#ga94ab78b385a77559abd1bc055656fa5a',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r2_5ffb9_640',['CAN_F11R2_FB9',['../group___peripheral___registers___bits___definition.html#gad5900c2273c405ce35b9bd52b189c102',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r2_5ffb9_5fmsk_641',['CAN_F11R2_FB9_Msk',['../group___peripheral___registers___bits___definition.html#gad2d8d29dcf8047b47275915562036f6e',1,'stm32f407xx_matlab.h']]], - ['can_5ff11r2_5ffb9_5fpos_642',['CAN_F11R2_FB9_Pos',['../group___peripheral___registers___bits___definition.html#ga818a9cf4d1a1ebfc566869487c5ede4e',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r1_5ffb0_643',['CAN_F12R1_FB0',['../group___peripheral___registers___bits___definition.html#gaccbe3637fb55f28496ca7f692a69f6ca',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r1_5ffb0_5fmsk_644',['CAN_F12R1_FB0_Msk',['../group___peripheral___registers___bits___definition.html#ga493ad4f71737d83380a81e3df1fafca6',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r1_5ffb0_5fpos_645',['CAN_F12R1_FB0_Pos',['../group___peripheral___registers___bits___definition.html#ga3f295f2367e770b2d0a6c376512bf73a',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r1_5ffb1_646',['CAN_F12R1_FB1',['../group___peripheral___registers___bits___definition.html#gae625d21947ae82cc3509b06363ad0635',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r1_5ffb10_647',['CAN_F12R1_FB10',['../group___peripheral___registers___bits___definition.html#ga1b8594ab0c5d9124accd2d6ca85cf4bd',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r1_5ffb10_5fmsk_648',['CAN_F12R1_FB10_Msk',['../group___peripheral___registers___bits___definition.html#ga3becedeec4964364eb6a6ca51af6c7a7',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r1_5ffb10_5fpos_649',['CAN_F12R1_FB10_Pos',['../group___peripheral___registers___bits___definition.html#gae32861a7d09171945a044611c0799be5',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r1_5ffb11_650',['CAN_F12R1_FB11',['../group___peripheral___registers___bits___definition.html#ga4025ed76892f23e5a63d0d8ac6a2be5f',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r1_5ffb11_5fmsk_651',['CAN_F12R1_FB11_Msk',['../group___peripheral___registers___bits___definition.html#ga0ab33464326b0107849ae73eb2d74649',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r1_5ffb11_5fpos_652',['CAN_F12R1_FB11_Pos',['../group___peripheral___registers___bits___definition.html#ga038226b9a5057333b93511a33a628df5',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r1_5ffb12_653',['CAN_F12R1_FB12',['../group___peripheral___registers___bits___definition.html#ga6e2e318cc14828c118bd40d982922e14',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r1_5ffb12_5fmsk_654',['CAN_F12R1_FB12_Msk',['../group___peripheral___registers___bits___definition.html#gac55c96f63d9cb2115cf779e2108cd2c2',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r1_5ffb12_5fpos_655',['CAN_F12R1_FB12_Pos',['../group___peripheral___registers___bits___definition.html#ga50aa1cdae5ac88b5dfb35f4e7fa1efa6',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r1_5ffb13_656',['CAN_F12R1_FB13',['../group___peripheral___registers___bits___definition.html#ga4e0ff698b5e9f3f99a421166611b041d',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r1_5ffb13_5fmsk_657',['CAN_F12R1_FB13_Msk',['../group___peripheral___registers___bits___definition.html#gaf6754922701ae479453231e3082f5995',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r1_5ffb13_5fpos_658',['CAN_F12R1_FB13_Pos',['../group___peripheral___registers___bits___definition.html#ga4705c5fa21a51b511e077c3812068f53',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r1_5ffb14_659',['CAN_F12R1_FB14',['../group___peripheral___registers___bits___definition.html#ga6b0666538a7646ddc0fcd882a261f5d9',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r1_5ffb14_5fmsk_660',['CAN_F12R1_FB14_Msk',['../group___peripheral___registers___bits___definition.html#ga40af5057b396387a1162d0091b2d826e',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r1_5ffb14_5fpos_661',['CAN_F12R1_FB14_Pos',['../group___peripheral___registers___bits___definition.html#gabece220b17e1d4e3d305e083f7a8cdf6',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r1_5ffb15_662',['CAN_F12R1_FB15',['../group___peripheral___registers___bits___definition.html#ga846d84b3d53e305b093198379f442528',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r1_5ffb15_5fmsk_663',['CAN_F12R1_FB15_Msk',['../group___peripheral___registers___bits___definition.html#gae4a4f362ed99f3b71078c88c720f7603',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r1_5ffb15_5fpos_664',['CAN_F12R1_FB15_Pos',['../group___peripheral___registers___bits___definition.html#gabdd867683a9a1ea022cfa4211a5079d0',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r1_5ffb16_665',['CAN_F12R1_FB16',['../group___peripheral___registers___bits___definition.html#gad7940c0898c2ef1d9f829bf1b6b5fcf3',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r1_5ffb16_5fmsk_666',['CAN_F12R1_FB16_Msk',['../group___peripheral___registers___bits___definition.html#ga44038ad11ff535489420a521d43090cd',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r1_5ffb16_5fpos_667',['CAN_F12R1_FB16_Pos',['../group___peripheral___registers___bits___definition.html#gab018f535eba98e6869cb39a15b6b27d6',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r1_5ffb17_668',['CAN_F12R1_FB17',['../group___peripheral___registers___bits___definition.html#ga6bdc7bd4dbad1f8e3bb622343bd7c522',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r1_5ffb17_5fmsk_669',['CAN_F12R1_FB17_Msk',['../group___peripheral___registers___bits___definition.html#gab1462a6bf5fd7f197bf4fc6b40f3531e',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r1_5ffb17_5fpos_670',['CAN_F12R1_FB17_Pos',['../group___peripheral___registers___bits___definition.html#ga518951f7f8d5f8a22f7782ea13a2ac0c',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r1_5ffb18_671',['CAN_F12R1_FB18',['../group___peripheral___registers___bits___definition.html#ga7c870a6fbae41b4f1c6d66ab690789d6',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r1_5ffb18_5fmsk_672',['CAN_F12R1_FB18_Msk',['../group___peripheral___registers___bits___definition.html#ga1ded4d9316004285d4c49d62eb48cce6',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r1_5ffb18_5fpos_673',['CAN_F12R1_FB18_Pos',['../group___peripheral___registers___bits___definition.html#gac1f6af451262400037581950b32da4b8',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r1_5ffb19_674',['CAN_F12R1_FB19',['../group___peripheral___registers___bits___definition.html#ga09e179b38460e47b81616c46a5f356f8',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r1_5ffb19_5fmsk_675',['CAN_F12R1_FB19_Msk',['../group___peripheral___registers___bits___definition.html#ga38b5a9bb84c7973eb3aee9bcc751a402',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r1_5ffb19_5fpos_676',['CAN_F12R1_FB19_Pos',['../group___peripheral___registers___bits___definition.html#ga3f9e3a6b9cf0673647bd9adfeadb887c',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r1_5ffb1_5fmsk_677',['CAN_F12R1_FB1_Msk',['../group___peripheral___registers___bits___definition.html#ga2a4cc96e515fe07094a824e27ad4d925',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r1_5ffb1_5fpos_678',['CAN_F12R1_FB1_Pos',['../group___peripheral___registers___bits___definition.html#ga17093a08b107416231f3d9028b7e161d',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r1_5ffb2_679',['CAN_F12R1_FB2',['../group___peripheral___registers___bits___definition.html#ga9de7cc313f2b6b16a564b13b1bc30157',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r1_5ffb20_680',['CAN_F12R1_FB20',['../group___peripheral___registers___bits___definition.html#gad42e298d4d97c98cc5149bc552a598fa',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r1_5ffb20_5fmsk_681',['CAN_F12R1_FB20_Msk',['../group___peripheral___registers___bits___definition.html#ga33e4aaef17496cf40db364d4c7ead7d5',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r1_5ffb20_5fpos_682',['CAN_F12R1_FB20_Pos',['../group___peripheral___registers___bits___definition.html#ga4a25348307ed3392337ad2a40bdfe73a',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r1_5ffb21_683',['CAN_F12R1_FB21',['../group___peripheral___registers___bits___definition.html#ga318e2a6ae62d5172dcdb45e011d5e0c4',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r1_5ffb21_5fmsk_684',['CAN_F12R1_FB21_Msk',['../group___peripheral___registers___bits___definition.html#ga776befd35d22caa64a1754b75134f2a6',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r1_5ffb21_5fpos_685',['CAN_F12R1_FB21_Pos',['../group___peripheral___registers___bits___definition.html#ga752faf78fd8e420905118261b231241c',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r1_5ffb22_686',['CAN_F12R1_FB22',['../group___peripheral___registers___bits___definition.html#ga90e95cb0020289335acd5d7f4b62a880',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r1_5ffb22_5fmsk_687',['CAN_F12R1_FB22_Msk',['../group___peripheral___registers___bits___definition.html#ga2d5b00cf1faf748d52633ee2a1989b49',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r1_5ffb22_5fpos_688',['CAN_F12R1_FB22_Pos',['../group___peripheral___registers___bits___definition.html#ga3238cf7161e4270d40115f5b61431a22',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r1_5ffb23_689',['CAN_F12R1_FB23',['../group___peripheral___registers___bits___definition.html#ga2e2720e18fdff00c9fb75d5136e485dc',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r1_5ffb23_5fmsk_690',['CAN_F12R1_FB23_Msk',['../group___peripheral___registers___bits___definition.html#gaaa9c58f403ed9bfc19a23aff1960065e',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r1_5ffb23_5fpos_691',['CAN_F12R1_FB23_Pos',['../group___peripheral___registers___bits___definition.html#gabd7d9b502598ae8cc04847d5cf9c0b52',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r1_5ffb24_692',['CAN_F12R1_FB24',['../group___peripheral___registers___bits___definition.html#gae4a87123ae5ff76992162152fbb4c92a',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r1_5ffb24_5fmsk_693',['CAN_F12R1_FB24_Msk',['../group___peripheral___registers___bits___definition.html#ga7efaf0ba941dc22a8a322e75d6495237',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r1_5ffb24_5fpos_694',['CAN_F12R1_FB24_Pos',['../group___peripheral___registers___bits___definition.html#ga1b9e2a2787690c33948183acf3e600fd',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r1_5ffb25_695',['CAN_F12R1_FB25',['../group___peripheral___registers___bits___definition.html#ga9582717e16455f97c7dff65f7beadd6e',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r1_5ffb25_5fmsk_696',['CAN_F12R1_FB25_Msk',['../group___peripheral___registers___bits___definition.html#ga495bdfd934bc40aeabfcb0454e47a2c7',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r1_5ffb25_5fpos_697',['CAN_F12R1_FB25_Pos',['../group___peripheral___registers___bits___definition.html#gae772d3a7da965bbd759aa2ffceeb3ae4',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r1_5ffb26_698',['CAN_F12R1_FB26',['../group___peripheral___registers___bits___definition.html#gaf15e362beb5a3b733c08c8c2ab81efcb',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r1_5ffb26_5fmsk_699',['CAN_F12R1_FB26_Msk',['../group___peripheral___registers___bits___definition.html#ga26edbc0aad33ae916a2c765f8a463023',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r1_5ffb26_5fpos_700',['CAN_F12R1_FB26_Pos',['../group___peripheral___registers___bits___definition.html#ga48905689b327cf537df7a4e7f12ed097',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r1_5ffb27_701',['CAN_F12R1_FB27',['../group___peripheral___registers___bits___definition.html#ga3d600a7a39c7069c216db511d3a5d866',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r1_5ffb27_5fmsk_702',['CAN_F12R1_FB27_Msk',['../group___peripheral___registers___bits___definition.html#gabb051023923964df52386c58e0ee26ed',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r1_5ffb27_5fpos_703',['CAN_F12R1_FB27_Pos',['../group___peripheral___registers___bits___definition.html#gaece06032650d7777a44ada0b8cc4a85b',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r1_5ffb28_704',['CAN_F12R1_FB28',['../group___peripheral___registers___bits___definition.html#gab9a6addc248c6db2118d1ce6e049d331',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r1_5ffb28_5fmsk_705',['CAN_F12R1_FB28_Msk',['../group___peripheral___registers___bits___definition.html#ga8e1bbde0fef2e2dab933da257a3afd66',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r1_5ffb28_5fpos_706',['CAN_F12R1_FB28_Pos',['../group___peripheral___registers___bits___definition.html#ga3fe5041f598b90c619dfa60edee91ced',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r1_5ffb29_707',['CAN_F12R1_FB29',['../group___peripheral___registers___bits___definition.html#ga31d3a46845cd9ca6670472aae2aa2ebe',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r1_5ffb29_5fmsk_708',['CAN_F12R1_FB29_Msk',['../group___peripheral___registers___bits___definition.html#ga9d988431331cf581558317c045e1117b',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r1_5ffb29_5fpos_709',['CAN_F12R1_FB29_Pos',['../group___peripheral___registers___bits___definition.html#ga89f3ef59e719e677cd850e299d9961a5',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r1_5ffb2_5fmsk_710',['CAN_F12R1_FB2_Msk',['../group___peripheral___registers___bits___definition.html#ga6c8d6c0e2c177e40ff60568beffac86b',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r1_5ffb2_5fpos_711',['CAN_F12R1_FB2_Pos',['../group___peripheral___registers___bits___definition.html#ga9311ab17c937d6e57b9e2e5ae93494b4',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r1_5ffb3_712',['CAN_F12R1_FB3',['../group___peripheral___registers___bits___definition.html#gac039cc1ce2281cf10be62cbc44748f5f',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r1_5ffb30_713',['CAN_F12R1_FB30',['../group___peripheral___registers___bits___definition.html#gaa06596dcbb545fbeea2ec20f629d9555',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r1_5ffb30_5fmsk_714',['CAN_F12R1_FB30_Msk',['../group___peripheral___registers___bits___definition.html#ga03b733b7cb7755ebe4678bf011a490f5',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r1_5ffb30_5fpos_715',['CAN_F12R1_FB30_Pos',['../group___peripheral___registers___bits___definition.html#ga0704718cb8d28fcbdb546e660b109e73',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r1_5ffb31_716',['CAN_F12R1_FB31',['../group___peripheral___registers___bits___definition.html#gac441b11b1be9b3608b9a09c2b8069722',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r1_5ffb31_5fmsk_717',['CAN_F12R1_FB31_Msk',['../group___peripheral___registers___bits___definition.html#ga47ce05849eef3967db74c9dcab8d936e',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r1_5ffb31_5fpos_718',['CAN_F12R1_FB31_Pos',['../group___peripheral___registers___bits___definition.html#ga5b666278c8cbde1fda669c22af52c2ab',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r1_5ffb3_5fmsk_719',['CAN_F12R1_FB3_Msk',['../group___peripheral___registers___bits___definition.html#ga34c79794004930e3de57c8417f7c5d6d',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r1_5ffb3_5fpos_720',['CAN_F12R1_FB3_Pos',['../group___peripheral___registers___bits___definition.html#ga8158fab7bc36d56b1202e637d45e0ee9',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r1_5ffb4_721',['CAN_F12R1_FB4',['../group___peripheral___registers___bits___definition.html#gabc3a35b6f6b3a46c176398ec322fd6fb',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r1_5ffb4_5fmsk_722',['CAN_F12R1_FB4_Msk',['../group___peripheral___registers___bits___definition.html#ga93b358c5c72ac735e4c7c802287f9903',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r1_5ffb4_5fpos_723',['CAN_F12R1_FB4_Pos',['../group___peripheral___registers___bits___definition.html#ga2db6bf56bfc0ceb513363931e2f032dc',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r1_5ffb5_724',['CAN_F12R1_FB5',['../group___peripheral___registers___bits___definition.html#ga4d005c10fe75169336104c3155294000',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r1_5ffb5_5fmsk_725',['CAN_F12R1_FB5_Msk',['../group___peripheral___registers___bits___definition.html#ga9cc058f703f84921bf889c9ce3c000d0',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r1_5ffb5_5fpos_726',['CAN_F12R1_FB5_Pos',['../group___peripheral___registers___bits___definition.html#ga2298551f803cc3ee122b170a68369c63',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r1_5ffb6_727',['CAN_F12R1_FB6',['../group___peripheral___registers___bits___definition.html#ga51256bfed734a95da3e7880e279432bf',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r1_5ffb6_5fmsk_728',['CAN_F12R1_FB6_Msk',['../group___peripheral___registers___bits___definition.html#ga86849d0bdcd7b03a0770c9fb4e1c0cf8',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r1_5ffb6_5fpos_729',['CAN_F12R1_FB6_Pos',['../group___peripheral___registers___bits___definition.html#ga2183cc81753585bdca7ca731db48f6ae',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r1_5ffb7_730',['CAN_F12R1_FB7',['../group___peripheral___registers___bits___definition.html#ga2c967f124b03968372d801e1393fa209',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r1_5ffb7_5fmsk_731',['CAN_F12R1_FB7_Msk',['../group___peripheral___registers___bits___definition.html#gabd7e08cb6960016b6a352bd8353733dd',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r1_5ffb7_5fpos_732',['CAN_F12R1_FB7_Pos',['../group___peripheral___registers___bits___definition.html#ga7f008c792182223c7f2ed45c5cec3461',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r1_5ffb8_733',['CAN_F12R1_FB8',['../group___peripheral___registers___bits___definition.html#ga592f9953deeb56888144c72060d04e24',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r1_5ffb8_5fmsk_734',['CAN_F12R1_FB8_Msk',['../group___peripheral___registers___bits___definition.html#gad138ae340d080c7b69b9dfe0814234f6',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r1_5ffb8_5fpos_735',['CAN_F12R1_FB8_Pos',['../group___peripheral___registers___bits___definition.html#gadb125f5efb6b0daae3758f92a2aadcbb',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r1_5ffb9_736',['CAN_F12R1_FB9',['../group___peripheral___registers___bits___definition.html#ga4d1613eac2aaeafda711cf3308ccd44c',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r1_5ffb9_5fmsk_737',['CAN_F12R1_FB9_Msk',['../group___peripheral___registers___bits___definition.html#gadb0713b2abf45e4c66dfc0c2f4aa902c',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r1_5ffb9_5fpos_738',['CAN_F12R1_FB9_Pos',['../group___peripheral___registers___bits___definition.html#gacf5573719f28f6259a0c06f933691797',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r2_5ffb0_739',['CAN_F12R2_FB0',['../group___peripheral___registers___bits___definition.html#gac5fd095552b3108c685514e78e43e52d',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r2_5ffb0_5fmsk_740',['CAN_F12R2_FB0_Msk',['../group___peripheral___registers___bits___definition.html#gab8707c57f295a01f74ba15708f138c27',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r2_5ffb0_5fpos_741',['CAN_F12R2_FB0_Pos',['../group___peripheral___registers___bits___definition.html#ga761234dc8a340812052ad359ca15346e',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r2_5ffb1_742',['CAN_F12R2_FB1',['../group___peripheral___registers___bits___definition.html#ga450e88e19b2e478e73cbc5eef74a72d2',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r2_5ffb10_743',['CAN_F12R2_FB10',['../group___peripheral___registers___bits___definition.html#ga854c2b7108e33d263cc8269648f8bbbe',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r2_5ffb10_5fmsk_744',['CAN_F12R2_FB10_Msk',['../group___peripheral___registers___bits___definition.html#gab2fe14171ea2823a2cc42bd77f8285f5',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r2_5ffb10_5fpos_745',['CAN_F12R2_FB10_Pos',['../group___peripheral___registers___bits___definition.html#gabf3a83fdb8ed55330b72d88624d3eeca',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r2_5ffb11_746',['CAN_F12R2_FB11',['../group___peripheral___registers___bits___definition.html#ga2ed3de0039e458bac5530d08c2e9af51',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r2_5ffb11_5fmsk_747',['CAN_F12R2_FB11_Msk',['../group___peripheral___registers___bits___definition.html#gaf995048a494eef63803ad6d1ee208669',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r2_5ffb11_5fpos_748',['CAN_F12R2_FB11_Pos',['../group___peripheral___registers___bits___definition.html#ga7506fa1356769f671cc4ac661aca30df',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r2_5ffb12_749',['CAN_F12R2_FB12',['../group___peripheral___registers___bits___definition.html#gadad0db6fe916794156f773e98b524b07',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r2_5ffb12_5fmsk_750',['CAN_F12R2_FB12_Msk',['../group___peripheral___registers___bits___definition.html#ga2b1c705252d4dda9fc1e08a83bf44014',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r2_5ffb12_5fpos_751',['CAN_F12R2_FB12_Pos',['../group___peripheral___registers___bits___definition.html#ga842fb02b43bc973392d1befc14475398',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r2_5ffb13_752',['CAN_F12R2_FB13',['../group___peripheral___registers___bits___definition.html#gaa7a50bd0de8b4e85d9e90c1f48ef7bc8',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r2_5ffb13_5fmsk_753',['CAN_F12R2_FB13_Msk',['../group___peripheral___registers___bits___definition.html#ga8a5720bd6028451390e7e09643a959eb',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r2_5ffb13_5fpos_754',['CAN_F12R2_FB13_Pos',['../group___peripheral___registers___bits___definition.html#ga584c1f14c88da55dfb8846e31b6fad4f',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r2_5ffb14_755',['CAN_F12R2_FB14',['../group___peripheral___registers___bits___definition.html#ga2c5558cc37c62c5570a5e2716e30ed99',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r2_5ffb14_5fmsk_756',['CAN_F12R2_FB14_Msk',['../group___peripheral___registers___bits___definition.html#gaac46f9e9d46f1bebfa7abcb094e87536',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r2_5ffb14_5fpos_757',['CAN_F12R2_FB14_Pos',['../group___peripheral___registers___bits___definition.html#ga199bffabf961f45cd68a0cafcc4be3e4',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r2_5ffb15_758',['CAN_F12R2_FB15',['../group___peripheral___registers___bits___definition.html#ga9fa511d56f90a2ee10e44e56e378f7ed',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r2_5ffb15_5fmsk_759',['CAN_F12R2_FB15_Msk',['../group___peripheral___registers___bits___definition.html#ga1114ed600ca719c7df01b6e0ebd1b46e',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r2_5ffb15_5fpos_760',['CAN_F12R2_FB15_Pos',['../group___peripheral___registers___bits___definition.html#gaba0f51aaeeb7e039aa521f88a20bacd6',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r2_5ffb16_761',['CAN_F12R2_FB16',['../group___peripheral___registers___bits___definition.html#ga77ae08ea078773a1aecbf74e89dc2a5d',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r2_5ffb16_5fmsk_762',['CAN_F12R2_FB16_Msk',['../group___peripheral___registers___bits___definition.html#ga94b484b519e43973af447f5f39fa9ea6',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r2_5ffb16_5fpos_763',['CAN_F12R2_FB16_Pos',['../group___peripheral___registers___bits___definition.html#ga02f84ccd7431b78532fed1e1b219cc5f',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r2_5ffb17_764',['CAN_F12R2_FB17',['../group___peripheral___registers___bits___definition.html#ga3a94ac3d4ba5c16a98fc04144ae3bb86',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r2_5ffb17_5fmsk_765',['CAN_F12R2_FB17_Msk',['../group___peripheral___registers___bits___definition.html#ga0a2460e4afab4b8dc064ffc0342f4d9d',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r2_5ffb17_5fpos_766',['CAN_F12R2_FB17_Pos',['../group___peripheral___registers___bits___definition.html#ga2dd4b026306377b126988db6f40b925b',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r2_5ffb18_767',['CAN_F12R2_FB18',['../group___peripheral___registers___bits___definition.html#gae9070c9b9eec5dea6b5c4cdbaa1d5918',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r2_5ffb18_5fmsk_768',['CAN_F12R2_FB18_Msk',['../group___peripheral___registers___bits___definition.html#gae63f4ec2056e1d8cee09e7582dd0cc4f',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r2_5ffb18_5fpos_769',['CAN_F12R2_FB18_Pos',['../group___peripheral___registers___bits___definition.html#ga6b9aaf58c37cc1c397c235b6f3359a8e',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r2_5ffb19_770',['CAN_F12R2_FB19',['../group___peripheral___registers___bits___definition.html#ga758cacc8b96577bb3663da1fae36040b',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r2_5ffb19_5fmsk_771',['CAN_F12R2_FB19_Msk',['../group___peripheral___registers___bits___definition.html#ga17513f0a12a63dd49ef869f7f69c89b0',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r2_5ffb19_5fpos_772',['CAN_F12R2_FB19_Pos',['../group___peripheral___registers___bits___definition.html#ga7b87a32833eb49ae6e9d6016b23f1a77',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r2_5ffb1_5fmsk_773',['CAN_F12R2_FB1_Msk',['../group___peripheral___registers___bits___definition.html#ga9c445b90087e01550b4d69a41d01920b',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r2_5ffb1_5fpos_774',['CAN_F12R2_FB1_Pos',['../group___peripheral___registers___bits___definition.html#ga30aeb440ddfed5b394b5d2a24e3ae6a9',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r2_5ffb2_775',['CAN_F12R2_FB2',['../group___peripheral___registers___bits___definition.html#ga17875db304b98c38e627f7d7db339136',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r2_5ffb20_776',['CAN_F12R2_FB20',['../group___peripheral___registers___bits___definition.html#ga80db4704807d6df4aaee2eebfcf5210a',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r2_5ffb20_5fmsk_777',['CAN_F12R2_FB20_Msk',['../group___peripheral___registers___bits___definition.html#ga98344bb2606581ffe2826c660c129f8b',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r2_5ffb20_5fpos_778',['CAN_F12R2_FB20_Pos',['../group___peripheral___registers___bits___definition.html#ga9723713bf9c96c6e2a843cc4c8851512',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r2_5ffb21_779',['CAN_F12R2_FB21',['../group___peripheral___registers___bits___definition.html#gac3d3fb3a9b4b6b90139024bef933bc3d',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r2_5ffb21_5fmsk_780',['CAN_F12R2_FB21_Msk',['../group___peripheral___registers___bits___definition.html#ga27369d641bde06fff00068460db1fad7',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r2_5ffb21_5fpos_781',['CAN_F12R2_FB21_Pos',['../group___peripheral___registers___bits___definition.html#ga1e7ede0dcef51b6f58598345d03231b2',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r2_5ffb22_782',['CAN_F12R2_FB22',['../group___peripheral___registers___bits___definition.html#ga24e87973f51235e81195d84f78489cb0',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r2_5ffb22_5fmsk_783',['CAN_F12R2_FB22_Msk',['../group___peripheral___registers___bits___definition.html#ga0293d477ec5d1c58228b05da05d5ab9a',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r2_5ffb22_5fpos_784',['CAN_F12R2_FB22_Pos',['../group___peripheral___registers___bits___definition.html#gafda2d00458700d6f0d9bc992032c143a',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r2_5ffb23_785',['CAN_F12R2_FB23',['../group___peripheral___registers___bits___definition.html#ga4e917f2a362569d86a75a34eddce636c',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r2_5ffb23_5fmsk_786',['CAN_F12R2_FB23_Msk',['../group___peripheral___registers___bits___definition.html#ga9bb02cff06985ebc935cd0c71033e309',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r2_5ffb23_5fpos_787',['CAN_F12R2_FB23_Pos',['../group___peripheral___registers___bits___definition.html#ga6f0bf90c297ea4e534fa8dc777f84308',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r2_5ffb24_788',['CAN_F12R2_FB24',['../group___peripheral___registers___bits___definition.html#gad6e5f2c5de8981fbfc152926fc8fb057',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r2_5ffb24_5fmsk_789',['CAN_F12R2_FB24_Msk',['../group___peripheral___registers___bits___definition.html#gae5942038c40cb69a4523cf59d41addaf',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r2_5ffb24_5fpos_790',['CAN_F12R2_FB24_Pos',['../group___peripheral___registers___bits___definition.html#ga0d42baff6206f76c15caec946f2e163f',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r2_5ffb25_791',['CAN_F12R2_FB25',['../group___peripheral___registers___bits___definition.html#gaaad1149501e8f926a247aa532405c0b9',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r2_5ffb25_5fmsk_792',['CAN_F12R2_FB25_Msk',['../group___peripheral___registers___bits___definition.html#gab77c232170c49225690370bd7b94cc34',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r2_5ffb25_5fpos_793',['CAN_F12R2_FB25_Pos',['../group___peripheral___registers___bits___definition.html#gacf89410be942af8dd01a4a82d2419ebc',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r2_5ffb26_794',['CAN_F12R2_FB26',['../group___peripheral___registers___bits___definition.html#ga53538969afd7e43cc7fed4c400ab6f5a',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r2_5ffb26_5fmsk_795',['CAN_F12R2_FB26_Msk',['../group___peripheral___registers___bits___definition.html#ga051ec82cb86668c1907e9091bf7db162',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r2_5ffb26_5fpos_796',['CAN_F12R2_FB26_Pos',['../group___peripheral___registers___bits___definition.html#ga099dae9dd45974395166a31031a7a9a4',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r2_5ffb27_797',['CAN_F12R2_FB27',['../group___peripheral___registers___bits___definition.html#ga74e04fa5d17a7cc7687c0ca40dd571ce',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r2_5ffb27_5fmsk_798',['CAN_F12R2_FB27_Msk',['../group___peripheral___registers___bits___definition.html#gae1eb6cc6be0e68041cb7e72b9ef73e22',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r2_5ffb27_5fpos_799',['CAN_F12R2_FB27_Pos',['../group___peripheral___registers___bits___definition.html#ga5ed6233846959dbe830448c085f9895d',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r2_5ffb28_800',['CAN_F12R2_FB28',['../group___peripheral___registers___bits___definition.html#gadc1d97354c1649fa5ddc46f4271297d9',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r2_5ffb28_5fmsk_801',['CAN_F12R2_FB28_Msk',['../group___peripheral___registers___bits___definition.html#ga2c63cc29f569c165a9b93cb0cb2d7557',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r2_5ffb28_5fpos_802',['CAN_F12R2_FB28_Pos',['../group___peripheral___registers___bits___definition.html#gaefa74afb06c20c7d6fdfadd641e55047',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r2_5ffb29_803',['CAN_F12R2_FB29',['../group___peripheral___registers___bits___definition.html#ga71b870003e469dcb24979e835a2f81a4',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r2_5ffb29_5fmsk_804',['CAN_F12R2_FB29_Msk',['../group___peripheral___registers___bits___definition.html#gaa58b7118e577b7ea51f92ed3d6a86a56',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r2_5ffb29_5fpos_805',['CAN_F12R2_FB29_Pos',['../group___peripheral___registers___bits___definition.html#gab2d97a557450fc2f40af9032f9e6c123',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r2_5ffb2_5fmsk_806',['CAN_F12R2_FB2_Msk',['../group___peripheral___registers___bits___definition.html#gae07ef8899e2a3d28d760dfd1ecc26534',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r2_5ffb2_5fpos_807',['CAN_F12R2_FB2_Pos',['../group___peripheral___registers___bits___definition.html#ga453ef335bb8ebc552ac07085c3c1787b',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r2_5ffb3_808',['CAN_F12R2_FB3',['../group___peripheral___registers___bits___definition.html#ga2960fee8bc56574e1b51975da7d2f041',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r2_5ffb30_809',['CAN_F12R2_FB30',['../group___peripheral___registers___bits___definition.html#ga2894b732a9683d32620fb90b06ba9f62',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r2_5ffb30_5fmsk_810',['CAN_F12R2_FB30_Msk',['../group___peripheral___registers___bits___definition.html#ga1fe16c8a9c44110d181e931e96458cee',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r2_5ffb30_5fpos_811',['CAN_F12R2_FB30_Pos',['../group___peripheral___registers___bits___definition.html#ga87899a68fb53be2c0c66183254f8e74c',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r2_5ffb31_812',['CAN_F12R2_FB31',['../group___peripheral___registers___bits___definition.html#gab11cddebcb4e1ab70b7222a999d0c58a',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r2_5ffb31_5fmsk_813',['CAN_F12R2_FB31_Msk',['../group___peripheral___registers___bits___definition.html#ga677ce6a45ad5da29fbe4b3674294c356',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r2_5ffb31_5fpos_814',['CAN_F12R2_FB31_Pos',['../group___peripheral___registers___bits___definition.html#ga6180d0787f865b2a5da3c308dc9df3ee',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r2_5ffb3_5fmsk_815',['CAN_F12R2_FB3_Msk',['../group___peripheral___registers___bits___definition.html#ga5918b1d48e5c6e30363e5f5274428f6f',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r2_5ffb3_5fpos_816',['CAN_F12R2_FB3_Pos',['../group___peripheral___registers___bits___definition.html#gaaac55989758901512f579aef6dc250d5',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r2_5ffb4_817',['CAN_F12R2_FB4',['../group___peripheral___registers___bits___definition.html#ga6b3b6f518fae0cb1123aa187138d90b6',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r2_5ffb4_5fmsk_818',['CAN_F12R2_FB4_Msk',['../group___peripheral___registers___bits___definition.html#ga7278ef3ee9707ed890c9fe0e6100898e',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r2_5ffb4_5fpos_819',['CAN_F12R2_FB4_Pos',['../group___peripheral___registers___bits___definition.html#ga0582dd4f64bdf4f05d1049191cd0ead5',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r2_5ffb5_820',['CAN_F12R2_FB5',['../group___peripheral___registers___bits___definition.html#ga39cedc414fa80ef987825daf32e11ac4',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r2_5ffb5_5fmsk_821',['CAN_F12R2_FB5_Msk',['../group___peripheral___registers___bits___definition.html#ga9db42645316b7d12f6761201dde5266e',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r2_5ffb5_5fpos_822',['CAN_F12R2_FB5_Pos',['../group___peripheral___registers___bits___definition.html#ga50ff5f436b22533d9c3d008b3b5ad936',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r2_5ffb6_823',['CAN_F12R2_FB6',['../group___peripheral___registers___bits___definition.html#ga10aa07474c2e7cf7f2845d0d2b2bd383',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r2_5ffb6_5fmsk_824',['CAN_F12R2_FB6_Msk',['../group___peripheral___registers___bits___definition.html#ga105d22692de0996a549d7381117a9343',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r2_5ffb6_5fpos_825',['CAN_F12R2_FB6_Pos',['../group___peripheral___registers___bits___definition.html#ga1f48821b5d51b30776a550c461e9f39e',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r2_5ffb7_826',['CAN_F12R2_FB7',['../group___peripheral___registers___bits___definition.html#ga227ef5f36f6e03969cd952d62a3bc0a9',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r2_5ffb7_5fmsk_827',['CAN_F12R2_FB7_Msk',['../group___peripheral___registers___bits___definition.html#ga7ef9a09cde9defbbef26f0fdb18e2eab',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r2_5ffb7_5fpos_828',['CAN_F12R2_FB7_Pos',['../group___peripheral___registers___bits___definition.html#gaa3bda5bd0a94bb8f667f350b5d1bd575',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r2_5ffb8_829',['CAN_F12R2_FB8',['../group___peripheral___registers___bits___definition.html#ga7a946c991cee617b322ff9a372af3512',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r2_5ffb8_5fmsk_830',['CAN_F12R2_FB8_Msk',['../group___peripheral___registers___bits___definition.html#ga997778eae60bd7c86e4ac5f512cf37d1',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r2_5ffb8_5fpos_831',['CAN_F12R2_FB8_Pos',['../group___peripheral___registers___bits___definition.html#ga5c35633aeeaa4b60f618d6b59d5450d1',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r2_5ffb9_832',['CAN_F12R2_FB9',['../group___peripheral___registers___bits___definition.html#gad0ab582743e96fcd36662a9434b875bd',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r2_5ffb9_5fmsk_833',['CAN_F12R2_FB9_Msk',['../group___peripheral___registers___bits___definition.html#ga0d597dd76bca430d66ce6cdc1dab0039',1,'stm32f407xx_matlab.h']]], - ['can_5ff12r2_5ffb9_5fpos_834',['CAN_F12R2_FB9_Pos',['../group___peripheral___registers___bits___definition.html#gaab378df5d0ef5f7b73f9cc93d9deb28d',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r1_5ffb0_835',['CAN_F13R1_FB0',['../group___peripheral___registers___bits___definition.html#gaa20d063950ad122a1965527a17d93c37',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r1_5ffb0_5fmsk_836',['CAN_F13R1_FB0_Msk',['../group___peripheral___registers___bits___definition.html#gae0775804606cd66638da3f6ba1b3b493',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r1_5ffb0_5fpos_837',['CAN_F13R1_FB0_Pos',['../group___peripheral___registers___bits___definition.html#ga02ab98a53a5893c727ea9957188ee26a',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r1_5ffb1_838',['CAN_F13R1_FB1',['../group___peripheral___registers___bits___definition.html#gaf60decd61c8a8dc9e4342de8ad67ea76',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r1_5ffb10_839',['CAN_F13R1_FB10',['../group___peripheral___registers___bits___definition.html#ga14640c225c434428ef1870f462eb9bbd',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r1_5ffb10_5fmsk_840',['CAN_F13R1_FB10_Msk',['../group___peripheral___registers___bits___definition.html#ga2439f107e699d239c00b630979ba87e1',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r1_5ffb10_5fpos_841',['CAN_F13R1_FB10_Pos',['../group___peripheral___registers___bits___definition.html#ga25a6f5d5b2e92245427b68c7961e76c6',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r1_5ffb11_842',['CAN_F13R1_FB11',['../group___peripheral___registers___bits___definition.html#ga7d8c9f5879cc4e31fe2e63f82febbc69',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r1_5ffb11_5fmsk_843',['CAN_F13R1_FB11_Msk',['../group___peripheral___registers___bits___definition.html#ga9103107051eb07e5ae903489b76eb2c4',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r1_5ffb11_5fpos_844',['CAN_F13R1_FB11_Pos',['../group___peripheral___registers___bits___definition.html#gab5f5353506ab2189b95cc97232c4fae4',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r1_5ffb12_845',['CAN_F13R1_FB12',['../group___peripheral___registers___bits___definition.html#ga8e0e3cfe033bb34f62312cfe47d1b84a',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r1_5ffb12_5fmsk_846',['CAN_F13R1_FB12_Msk',['../group___peripheral___registers___bits___definition.html#ga9dabd107a2de9ccd6461da5926e4d4e4',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r1_5ffb12_5fpos_847',['CAN_F13R1_FB12_Pos',['../group___peripheral___registers___bits___definition.html#gaef2be27cb238beb59c18bdb3b874f96e',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r1_5ffb13_848',['CAN_F13R1_FB13',['../group___peripheral___registers___bits___definition.html#ga93d91a28c1ffca3f72f10e0b44040791',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r1_5ffb13_5fmsk_849',['CAN_F13R1_FB13_Msk',['../group___peripheral___registers___bits___definition.html#ga1db0ef6756bc958994e6fc702ce75b81',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r1_5ffb13_5fpos_850',['CAN_F13R1_FB13_Pos',['../group___peripheral___registers___bits___definition.html#ga7c3512eefb28504e6db269b9cd68202e',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r1_5ffb14_851',['CAN_F13R1_FB14',['../group___peripheral___registers___bits___definition.html#ga355b438a5abccec89e13bdd00206b36f',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r1_5ffb14_5fmsk_852',['CAN_F13R1_FB14_Msk',['../group___peripheral___registers___bits___definition.html#ga1412e4fcd6edb251cf356694de9f3f42',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r1_5ffb14_5fpos_853',['CAN_F13R1_FB14_Pos',['../group___peripheral___registers___bits___definition.html#gac817b1dbf5b97572d61f4cb97ac35395',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r1_5ffb15_854',['CAN_F13R1_FB15',['../group___peripheral___registers___bits___definition.html#ga89b23d147d2c040eb2317633b3ef46da',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r1_5ffb15_5fmsk_855',['CAN_F13R1_FB15_Msk',['../group___peripheral___registers___bits___definition.html#ga0cc8b54a2836661fdd482c004556cba1',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r1_5ffb15_5fpos_856',['CAN_F13R1_FB15_Pos',['../group___peripheral___registers___bits___definition.html#gaba2fba83e1654499f506bfe603b877a6',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r1_5ffb16_857',['CAN_F13R1_FB16',['../group___peripheral___registers___bits___definition.html#ga81d184cd46306fe24b46087a90e8f8f2',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r1_5ffb16_5fmsk_858',['CAN_F13R1_FB16_Msk',['../group___peripheral___registers___bits___definition.html#ga7d570ecd25032c69017c3c117f0aebdf',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r1_5ffb16_5fpos_859',['CAN_F13R1_FB16_Pos',['../group___peripheral___registers___bits___definition.html#ga0cdea57e0dff6ff19f5cc60f4307e25c',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r1_5ffb17_860',['CAN_F13R1_FB17',['../group___peripheral___registers___bits___definition.html#ga151a0e903046edc92bddcd0ef4a23449',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r1_5ffb17_5fmsk_861',['CAN_F13R1_FB17_Msk',['../group___peripheral___registers___bits___definition.html#gaef2321a184dc8aa13baef70a5cb6193f',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r1_5ffb17_5fpos_862',['CAN_F13R1_FB17_Pos',['../group___peripheral___registers___bits___definition.html#gaa862da872daa901ad2449731d9218b4d',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r1_5ffb18_863',['CAN_F13R1_FB18',['../group___peripheral___registers___bits___definition.html#ga9e95e6d0d060fb2cfdf31e1b5fdfe3de',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r1_5ffb18_5fmsk_864',['CAN_F13R1_FB18_Msk',['../group___peripheral___registers___bits___definition.html#gae27c24ba203819e140dfddb8bc05c473',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r1_5ffb18_5fpos_865',['CAN_F13R1_FB18_Pos',['../group___peripheral___registers___bits___definition.html#ga8f93c38f644d676c7241d539765e044a',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r1_5ffb19_866',['CAN_F13R1_FB19',['../group___peripheral___registers___bits___definition.html#ga1e0fb1cf032c57f954dd2679a05f8115',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r1_5ffb19_5fmsk_867',['CAN_F13R1_FB19_Msk',['../group___peripheral___registers___bits___definition.html#ga471095d382cce78017304b5db76f7a04',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r1_5ffb19_5fpos_868',['CAN_F13R1_FB19_Pos',['../group___peripheral___registers___bits___definition.html#ga962217baf4c2af30fc495a0eb0b51879',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r1_5ffb1_5fmsk_869',['CAN_F13R1_FB1_Msk',['../group___peripheral___registers___bits___definition.html#ga5af825390c54a3a65aac39d6a998ca48',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r1_5ffb1_5fpos_870',['CAN_F13R1_FB1_Pos',['../group___peripheral___registers___bits___definition.html#ga35f9a2ceccf6229be57bb4145d593543',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r1_5ffb2_871',['CAN_F13R1_FB2',['../group___peripheral___registers___bits___definition.html#ga7863b3af06385d0e9037c57a5d2091e2',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r1_5ffb20_872',['CAN_F13R1_FB20',['../group___peripheral___registers___bits___definition.html#gaeb775bb1ded6a8f55f2a0849bec2eeac',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r1_5ffb20_5fmsk_873',['CAN_F13R1_FB20_Msk',['../group___peripheral___registers___bits___definition.html#ga5c097cf8909e3cc7825d9500a891be52',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r1_5ffb20_5fpos_874',['CAN_F13R1_FB20_Pos',['../group___peripheral___registers___bits___definition.html#ga48c0363bcb1ee7fa09ecf22f6b94ed2a',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r1_5ffb21_875',['CAN_F13R1_FB21',['../group___peripheral___registers___bits___definition.html#ga8743dfb60255d98911ea66605efd3b2f',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r1_5ffb21_5fmsk_876',['CAN_F13R1_FB21_Msk',['../group___peripheral___registers___bits___definition.html#ga3523d0b622d476255e22d07d76831a75',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r1_5ffb21_5fpos_877',['CAN_F13R1_FB21_Pos',['../group___peripheral___registers___bits___definition.html#ga556fb1d9d20383d707a69806152d2571',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r1_5ffb22_878',['CAN_F13R1_FB22',['../group___peripheral___registers___bits___definition.html#ga54b067c38f3be3ad6041ea12fec15700',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r1_5ffb22_5fmsk_879',['CAN_F13R1_FB22_Msk',['../group___peripheral___registers___bits___definition.html#gae50e71fdf75fcc3e59b95b855d3bf30a',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r1_5ffb22_5fpos_880',['CAN_F13R1_FB22_Pos',['../group___peripheral___registers___bits___definition.html#gaec41136c74e99a37d9aca5c92ac9a93c',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r1_5ffb23_881',['CAN_F13R1_FB23',['../group___peripheral___registers___bits___definition.html#ga00fe1942d9a8767a76f139bd74eafea0',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r1_5ffb23_5fmsk_882',['CAN_F13R1_FB23_Msk',['../group___peripheral___registers___bits___definition.html#ga45b6b1f5126bfa15739a086d6734cfd5',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r1_5ffb23_5fpos_883',['CAN_F13R1_FB23_Pos',['../group___peripheral___registers___bits___definition.html#ga7686cf2ffa6e927845c1064994c8d392',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r1_5ffb24_884',['CAN_F13R1_FB24',['../group___peripheral___registers___bits___definition.html#ga05db1c0a2e6e051d616b59f386dc7b1e',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r1_5ffb24_5fmsk_885',['CAN_F13R1_FB24_Msk',['../group___peripheral___registers___bits___definition.html#ga710ae584f88078c05820eede3729b65c',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r1_5ffb24_5fpos_886',['CAN_F13R1_FB24_Pos',['../group___peripheral___registers___bits___definition.html#gab03f0061f54b4b410c91e61836225912',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r1_5ffb25_887',['CAN_F13R1_FB25',['../group___peripheral___registers___bits___definition.html#ga66dd0da9fd8ef27b30f1ad56a9982caf',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r1_5ffb25_5fmsk_888',['CAN_F13R1_FB25_Msk',['../group___peripheral___registers___bits___definition.html#ga0f2580d7250fa56c7a1e25f9d282c942',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r1_5ffb25_5fpos_889',['CAN_F13R1_FB25_Pos',['../group___peripheral___registers___bits___definition.html#ga2e9fea689cdeac8918508a183517d0db',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r1_5ffb26_890',['CAN_F13R1_FB26',['../group___peripheral___registers___bits___definition.html#gaf3b8381bc6ce5ab107cc1a92e565387a',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r1_5ffb26_5fmsk_891',['CAN_F13R1_FB26_Msk',['../group___peripheral___registers___bits___definition.html#gafdd8f8b38bc3d56b97c8909c7dbb7560',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r1_5ffb26_5fpos_892',['CAN_F13R1_FB26_Pos',['../group___peripheral___registers___bits___definition.html#ga9eb77bfba6b6a7db4562bce8bb35316b',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r1_5ffb27_893',['CAN_F13R1_FB27',['../group___peripheral___registers___bits___definition.html#ga91c99de5ae099ecdee50ebd62e552df5',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r1_5ffb27_5fmsk_894',['CAN_F13R1_FB27_Msk',['../group___peripheral___registers___bits___definition.html#gafc69c07f91f2c9d6b85c3f26532fad1f',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r1_5ffb27_5fpos_895',['CAN_F13R1_FB27_Pos',['../group___peripheral___registers___bits___definition.html#gadb78e36a1d8975246d7437b4b3d8c0aa',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r1_5ffb28_896',['CAN_F13R1_FB28',['../group___peripheral___registers___bits___definition.html#ga83713f9e2c3c90f001ab378d9ca1f488',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r1_5ffb28_5fmsk_897',['CAN_F13R1_FB28_Msk',['../group___peripheral___registers___bits___definition.html#ga1dd7a2e1000f7df336489982291d76d8',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r1_5ffb28_5fpos_898',['CAN_F13R1_FB28_Pos',['../group___peripheral___registers___bits___definition.html#ga4ab2ee1db50c027b505177c9b65af835',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r1_5ffb29_899',['CAN_F13R1_FB29',['../group___peripheral___registers___bits___definition.html#ga050fb1e9555d0d24f81682e194677684',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r1_5ffb29_5fmsk_900',['CAN_F13R1_FB29_Msk',['../group___peripheral___registers___bits___definition.html#ga3ed837627ac02698016cdf0439782fec',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r1_5ffb29_5fpos_901',['CAN_F13R1_FB29_Pos',['../group___peripheral___registers___bits___definition.html#ga9eed6320b23de2023e8c8ddeb7efaa1b',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r1_5ffb2_5fmsk_902',['CAN_F13R1_FB2_Msk',['../group___peripheral___registers___bits___definition.html#ga34ca97bf95c63ac91fe0bbf664f96c5a',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r1_5ffb2_5fpos_903',['CAN_F13R1_FB2_Pos',['../group___peripheral___registers___bits___definition.html#gad6613018ad3a9b1086f63172d3fa5322',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r1_5ffb3_904',['CAN_F13R1_FB3',['../group___peripheral___registers___bits___definition.html#ga043282b30813ce88dbdb320936ff6aca',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r1_5ffb30_905',['CAN_F13R1_FB30',['../group___peripheral___registers___bits___definition.html#ga761164856a25bc246396c7c82fdeb447',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r1_5ffb30_5fmsk_906',['CAN_F13R1_FB30_Msk',['../group___peripheral___registers___bits___definition.html#ga6e7f63726fd4dffa870717dbf3079be8',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r1_5ffb30_5fpos_907',['CAN_F13R1_FB30_Pos',['../group___peripheral___registers___bits___definition.html#ga86ba01c60b4b90ff0c58dab1c7e8bc6a',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r1_5ffb31_908',['CAN_F13R1_FB31',['../group___peripheral___registers___bits___definition.html#ga1a750d71e94876d2f6e73a0e8b7217b2',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r1_5ffb31_5fmsk_909',['CAN_F13R1_FB31_Msk',['../group___peripheral___registers___bits___definition.html#gad950a42557716b1e66d0e675d4ed0388',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r1_5ffb31_5fpos_910',['CAN_F13R1_FB31_Pos',['../group___peripheral___registers___bits___definition.html#gaaa0459499e89cee6ff87bb40d6b6a0d7',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r1_5ffb3_5fmsk_911',['CAN_F13R1_FB3_Msk',['../group___peripheral___registers___bits___definition.html#gaf217b9312083ea4fee7d1e808d6abb84',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r1_5ffb3_5fpos_912',['CAN_F13R1_FB3_Pos',['../group___peripheral___registers___bits___definition.html#ga38212e081d0a3d8b9b5384f034a5407a',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r1_5ffb4_913',['CAN_F13R1_FB4',['../group___peripheral___registers___bits___definition.html#ga3bbc9e9866f20d9d2f3cea1c6777c673',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r1_5ffb4_5fmsk_914',['CAN_F13R1_FB4_Msk',['../group___peripheral___registers___bits___definition.html#ga325e27d4b7557c9da7685eaaefdd9bbe',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r1_5ffb4_5fpos_915',['CAN_F13R1_FB4_Pos',['../group___peripheral___registers___bits___definition.html#gacdcbf72e68c8d4c217a3cc35c9a6a19d',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r1_5ffb5_916',['CAN_F13R1_FB5',['../group___peripheral___registers___bits___definition.html#ga885b36e017b013ab6deedd91d9ac2c66',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r1_5ffb5_5fmsk_917',['CAN_F13R1_FB5_Msk',['../group___peripheral___registers___bits___definition.html#ga53dda4ae54ad09328863f96688745173',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r1_5ffb5_5fpos_918',['CAN_F13R1_FB5_Pos',['../group___peripheral___registers___bits___definition.html#ga6317c62241dd862ad43be5bd0ce74696',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r1_5ffb6_919',['CAN_F13R1_FB6',['../group___peripheral___registers___bits___definition.html#gaa389b53582e5cacf326fff4512626d68',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r1_5ffb6_5fmsk_920',['CAN_F13R1_FB6_Msk',['../group___peripheral___registers___bits___definition.html#gaae396c50fbe96dbdd418620ffd2fa5b4',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r1_5ffb6_5fpos_921',['CAN_F13R1_FB6_Pos',['../group___peripheral___registers___bits___definition.html#ga097998c68e6f03b713fe2eae37670c72',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r1_5ffb7_922',['CAN_F13R1_FB7',['../group___peripheral___registers___bits___definition.html#gad09b75feeda08b16962db7da6a32dc9b',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r1_5ffb7_5fmsk_923',['CAN_F13R1_FB7_Msk',['../group___peripheral___registers___bits___definition.html#gad0a54488273ee23a74dfe0a0deca7d7d',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r1_5ffb7_5fpos_924',['CAN_F13R1_FB7_Pos',['../group___peripheral___registers___bits___definition.html#gad30d6f9e145dbaf24c55480181072280',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r1_5ffb8_925',['CAN_F13R1_FB8',['../group___peripheral___registers___bits___definition.html#gaaba75675c019979882ecd8c6ef82d7a4',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r1_5ffb8_5fmsk_926',['CAN_F13R1_FB8_Msk',['../group___peripheral___registers___bits___definition.html#gad8c2421189d009e0b2630cf53f0caaf1',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r1_5ffb8_5fpos_927',['CAN_F13R1_FB8_Pos',['../group___peripheral___registers___bits___definition.html#ga1b8cb9dd079a3116919ec1e48f3267b7',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r1_5ffb9_928',['CAN_F13R1_FB9',['../group___peripheral___registers___bits___definition.html#gac579473f666edec0e0fcce278b642a9d',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r1_5ffb9_5fmsk_929',['CAN_F13R1_FB9_Msk',['../group___peripheral___registers___bits___definition.html#gaa365ae887f59e0e1684a5ed96fb50042',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r1_5ffb9_5fpos_930',['CAN_F13R1_FB9_Pos',['../group___peripheral___registers___bits___definition.html#gacd53ccc27879017d3a67b404b6cc2e8e',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r2_5ffb0_931',['CAN_F13R2_FB0',['../group___peripheral___registers___bits___definition.html#ga0b6865be0c757b49a250a537d73ae85e',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r2_5ffb0_5fmsk_932',['CAN_F13R2_FB0_Msk',['../group___peripheral___registers___bits___definition.html#ga5829958d09421fd61fcf0b77d51d2da9',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r2_5ffb0_5fpos_933',['CAN_F13R2_FB0_Pos',['../group___peripheral___registers___bits___definition.html#gaf65fd29198dc6498a41e5fc67ab0092c',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r2_5ffb1_934',['CAN_F13R2_FB1',['../group___peripheral___registers___bits___definition.html#gaf18df9b2fd549b8991fdd9f8f94e7cbb',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r2_5ffb10_935',['CAN_F13R2_FB10',['../group___peripheral___registers___bits___definition.html#gafb4be9c1da46b251c43c0aafe7b04497',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r2_5ffb10_5fmsk_936',['CAN_F13R2_FB10_Msk',['../group___peripheral___registers___bits___definition.html#ga7ad8207a0741ab38136b3b5c3b1d3d91',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r2_5ffb10_5fpos_937',['CAN_F13R2_FB10_Pos',['../group___peripheral___registers___bits___definition.html#ga7c9c5a2239ce7d523894181eacd0a52e',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r2_5ffb11_938',['CAN_F13R2_FB11',['../group___peripheral___registers___bits___definition.html#ga47f5215de00574378a489f90eb11eff4',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r2_5ffb11_5fmsk_939',['CAN_F13R2_FB11_Msk',['../group___peripheral___registers___bits___definition.html#ga001860328be3ee22113d0c10f4d3cf23',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r2_5ffb11_5fpos_940',['CAN_F13R2_FB11_Pos',['../group___peripheral___registers___bits___definition.html#ga9228d8f828f658636990f7cd5896ccf4',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r2_5ffb12_941',['CAN_F13R2_FB12',['../group___peripheral___registers___bits___definition.html#gac3bbd5350aeb18966e2a40e2dc4223e3',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r2_5ffb12_5fmsk_942',['CAN_F13R2_FB12_Msk',['../group___peripheral___registers___bits___definition.html#gadd232459994d381a778abd4aa43bbb70',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r2_5ffb12_5fpos_943',['CAN_F13R2_FB12_Pos',['../group___peripheral___registers___bits___definition.html#gae031e0a0fe7facb0d7d56c7efd3aa2ea',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r2_5ffb13_944',['CAN_F13R2_FB13',['../group___peripheral___registers___bits___definition.html#gab2d97199e363dd56cd9a455aec75ef1c',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r2_5ffb13_5fmsk_945',['CAN_F13R2_FB13_Msk',['../group___peripheral___registers___bits___definition.html#ga078d3a3cfba178ef1d8b0499e04326e1',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r2_5ffb13_5fpos_946',['CAN_F13R2_FB13_Pos',['../group___peripheral___registers___bits___definition.html#gac5bd52b9aa672bbd50a4a60f2e01c2d1',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r2_5ffb14_947',['CAN_F13R2_FB14',['../group___peripheral___registers___bits___definition.html#ga0731f4e60125130bebf88d33fd4ae3ca',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r2_5ffb14_5fmsk_948',['CAN_F13R2_FB14_Msk',['../group___peripheral___registers___bits___definition.html#ga47b3e370df1a4ec6f8a69cd648a823cb',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r2_5ffb14_5fpos_949',['CAN_F13R2_FB14_Pos',['../group___peripheral___registers___bits___definition.html#gab32e372353ed3e56c1aad445b2616c58',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r2_5ffb15_950',['CAN_F13R2_FB15',['../group___peripheral___registers___bits___definition.html#ga1683c0cc3b3143a919f4dd59243eba9f',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r2_5ffb15_5fmsk_951',['CAN_F13R2_FB15_Msk',['../group___peripheral___registers___bits___definition.html#ga760672a8bb29f0054fbef52bc3b71c0a',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r2_5ffb15_5fpos_952',['CAN_F13R2_FB15_Pos',['../group___peripheral___registers___bits___definition.html#gacb6696be0087357ad560cf24aa616021',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r2_5ffb16_953',['CAN_F13R2_FB16',['../group___peripheral___registers___bits___definition.html#gad2ed74a0929c6d397c14f49f114f13bf',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r2_5ffb16_5fmsk_954',['CAN_F13R2_FB16_Msk',['../group___peripheral___registers___bits___definition.html#ga2ce486f2da389ec7cf80e6d102b7bc56',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r2_5ffb16_5fpos_955',['CAN_F13R2_FB16_Pos',['../group___peripheral___registers___bits___definition.html#ga83eca0eb5bea5956eeb4ab174c366f75',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r2_5ffb17_956',['CAN_F13R2_FB17',['../group___peripheral___registers___bits___definition.html#gafde6cdff22bf29d31b5be1b309fe4dde',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r2_5ffb17_5fmsk_957',['CAN_F13R2_FB17_Msk',['../group___peripheral___registers___bits___definition.html#ga9d552599612053845141e0db3c89ca86',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r2_5ffb17_5fpos_958',['CAN_F13R2_FB17_Pos',['../group___peripheral___registers___bits___definition.html#ga8db0458a7ddad624a4fe50458f06ebe7',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r2_5ffb18_959',['CAN_F13R2_FB18',['../group___peripheral___registers___bits___definition.html#gabb873fa1c32fbf6c5a2f3be93ba2f2e6',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r2_5ffb18_5fmsk_960',['CAN_F13R2_FB18_Msk',['../group___peripheral___registers___bits___definition.html#ga34fcf71e30ba700e1b975c6273a99de5',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r2_5ffb18_5fpos_961',['CAN_F13R2_FB18_Pos',['../group___peripheral___registers___bits___definition.html#ga041ea608c1e920eca8e6b12027331761',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r2_5ffb19_962',['CAN_F13R2_FB19',['../group___peripheral___registers___bits___definition.html#gaf82a4dfd4d3c7a13232479be997ed1f9',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r2_5ffb19_5fmsk_963',['CAN_F13R2_FB19_Msk',['../group___peripheral___registers___bits___definition.html#gaa5b5c1ede34327d024575f334f3895b7',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r2_5ffb19_5fpos_964',['CAN_F13R2_FB19_Pos',['../group___peripheral___registers___bits___definition.html#gac7e96e3beea2a3c1bffb610cebf01012',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r2_5ffb1_5fmsk_965',['CAN_F13R2_FB1_Msk',['../group___peripheral___registers___bits___definition.html#ga5d158b5eebb1632e54e5be5d97c8ac26',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r2_5ffb1_5fpos_966',['CAN_F13R2_FB1_Pos',['../group___peripheral___registers___bits___definition.html#ga44b45587e81d3899b99a4292ef37ea94',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r2_5ffb2_967',['CAN_F13R2_FB2',['../group___peripheral___registers___bits___definition.html#ga034e8f5b7675ce34eb2792531c7e174d',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r2_5ffb20_968',['CAN_F13R2_FB20',['../group___peripheral___registers___bits___definition.html#gaa7bf4384e44f002392339a71bc9c912c',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r2_5ffb20_5fmsk_969',['CAN_F13R2_FB20_Msk',['../group___peripheral___registers___bits___definition.html#gaae823f61c39d0a97b05947308792e122',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r2_5ffb20_5fpos_970',['CAN_F13R2_FB20_Pos',['../group___peripheral___registers___bits___definition.html#gaa79bef1cef0cab3783a6351067a28670',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r2_5ffb21_971',['CAN_F13R2_FB21',['../group___peripheral___registers___bits___definition.html#gaa7023986be02dd8f736e04e658844061',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r2_5ffb21_5fmsk_972',['CAN_F13R2_FB21_Msk',['../group___peripheral___registers___bits___definition.html#gabea7b7f481ba0bc31d2909460e0bc54e',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r2_5ffb21_5fpos_973',['CAN_F13R2_FB21_Pos',['../group___peripheral___registers___bits___definition.html#ga6c135cf4d4773022ff4a284d13672082',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r2_5ffb22_974',['CAN_F13R2_FB22',['../group___peripheral___registers___bits___definition.html#gafd059121f2a882342a409ebef8a96999',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r2_5ffb22_5fmsk_975',['CAN_F13R2_FB22_Msk',['../group___peripheral___registers___bits___definition.html#ga66fb2f382a4967515fa63a8454131fb9',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r2_5ffb22_5fpos_976',['CAN_F13R2_FB22_Pos',['../group___peripheral___registers___bits___definition.html#ga06db7af2bea27dea18c2c36b0ff73afa',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r2_5ffb23_977',['CAN_F13R2_FB23',['../group___peripheral___registers___bits___definition.html#ga5ef57f88bf1e6e34b0096013278926c0',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r2_5ffb23_5fmsk_978',['CAN_F13R2_FB23_Msk',['../group___peripheral___registers___bits___definition.html#ga2bee64a9c633df1a34f5435406103085',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r2_5ffb23_5fpos_979',['CAN_F13R2_FB23_Pos',['../group___peripheral___registers___bits___definition.html#gaeb354c4f61952c7a85f0ef302163b0e9',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r2_5ffb24_980',['CAN_F13R2_FB24',['../group___peripheral___registers___bits___definition.html#ga4847de9f5b54fc5ce00e0fba69564d2d',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r2_5ffb24_5fmsk_981',['CAN_F13R2_FB24_Msk',['../group___peripheral___registers___bits___definition.html#ga0b4176f0f14ef22173c436763a6c483e',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r2_5ffb24_5fpos_982',['CAN_F13R2_FB24_Pos',['../group___peripheral___registers___bits___definition.html#ga7b46be4b9570584370ce39342df1d8c5',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r2_5ffb25_983',['CAN_F13R2_FB25',['../group___peripheral___registers___bits___definition.html#ga2c415fa87c556bd8a4fc0f680d25f160',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r2_5ffb25_5fmsk_984',['CAN_F13R2_FB25_Msk',['../group___peripheral___registers___bits___definition.html#gad55a497a172eeaeb711d04f5cc81f411',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r2_5ffb25_5fpos_985',['CAN_F13R2_FB25_Pos',['../group___peripheral___registers___bits___definition.html#ga0d1923954a761ac8ae84432354317806',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r2_5ffb26_986',['CAN_F13R2_FB26',['../group___peripheral___registers___bits___definition.html#ga20487222c41a08fe68b9ce58dfd52fff',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r2_5ffb26_5fmsk_987',['CAN_F13R2_FB26_Msk',['../group___peripheral___registers___bits___definition.html#ga117bfac3184445e41ca1709495cd1603',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r2_5ffb26_5fpos_988',['CAN_F13R2_FB26_Pos',['../group___peripheral___registers___bits___definition.html#ga27b86a7f094043e077a15a6b36cab7fe',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r2_5ffb27_989',['CAN_F13R2_FB27',['../group___peripheral___registers___bits___definition.html#gaa0d5ca021778a6e84fd3c0ad8981255d',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r2_5ffb27_5fmsk_990',['CAN_F13R2_FB27_Msk',['../group___peripheral___registers___bits___definition.html#ga2716a8a28de7a05f7f448d6b581928fe',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r2_5ffb27_5fpos_991',['CAN_F13R2_FB27_Pos',['../group___peripheral___registers___bits___definition.html#ga4e7f1c6169d847c9acf1cc737ecf4e6f',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r2_5ffb28_992',['CAN_F13R2_FB28',['../group___peripheral___registers___bits___definition.html#ga2f0c8c09be20a14f29ab46d53dd712ba',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r2_5ffb28_5fmsk_993',['CAN_F13R2_FB28_Msk',['../group___peripheral___registers___bits___definition.html#gabf9c86580fedab6d11c0e935e787fd31',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r2_5ffb28_5fpos_994',['CAN_F13R2_FB28_Pos',['../group___peripheral___registers___bits___definition.html#ga63a19687e787196f324bf380130defc4',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r2_5ffb29_995',['CAN_F13R2_FB29',['../group___peripheral___registers___bits___definition.html#ga26161b84a5fc507f959b620c8e380703',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r2_5ffb29_5fmsk_996',['CAN_F13R2_FB29_Msk',['../group___peripheral___registers___bits___definition.html#gabed854c540fda686a9c51d21cf45cff3',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r2_5ffb29_5fpos_997',['CAN_F13R2_FB29_Pos',['../group___peripheral___registers___bits___definition.html#ga6229421e0e7697e0210ab0281c949f45',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r2_5ffb2_5fmsk_998',['CAN_F13R2_FB2_Msk',['../group___peripheral___registers___bits___definition.html#ga4433c9b9f1466001eaf2305aa5abcf88',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r2_5ffb2_5fpos_999',['CAN_F13R2_FB2_Pos',['../group___peripheral___registers___bits___definition.html#ga16867534ce37ae3319f3e8a5cf087cb8',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r2_5ffb3_1000',['CAN_F13R2_FB3',['../group___peripheral___registers___bits___definition.html#gaf19767c0892dffb6eff8c5a3b0e254f5',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r2_5ffb30_1001',['CAN_F13R2_FB30',['../group___peripheral___registers___bits___definition.html#ga1e753550a0a8547c7f64346e22925012',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r2_5ffb30_5fmsk_1002',['CAN_F13R2_FB30_Msk',['../group___peripheral___registers___bits___definition.html#ga812a202cba22a21b94811b815cc57611',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r2_5ffb30_5fpos_1003',['CAN_F13R2_FB30_Pos',['../group___peripheral___registers___bits___definition.html#ga36f10ded80a4a78d7cf92f8b6f3ed078',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r2_5ffb31_1004',['CAN_F13R2_FB31',['../group___peripheral___registers___bits___definition.html#ga305ac04b1c5198a4f82c78c570ce7f97',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r2_5ffb31_5fmsk_1005',['CAN_F13R2_FB31_Msk',['../group___peripheral___registers___bits___definition.html#ga6eceafce3dabadee19db4afd0e0884d6',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r2_5ffb31_5fpos_1006',['CAN_F13R2_FB31_Pos',['../group___peripheral___registers___bits___definition.html#ga6af7dbbe2d835ab3d050971ac07a0ea3',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r2_5ffb3_5fmsk_1007',['CAN_F13R2_FB3_Msk',['../group___peripheral___registers___bits___definition.html#gaab05ac64cc9be63004a672f439a7ab70',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r2_5ffb3_5fpos_1008',['CAN_F13R2_FB3_Pos',['../group___peripheral___registers___bits___definition.html#gaed05bb756f656fb754091e64b176bd78',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r2_5ffb4_1009',['CAN_F13R2_FB4',['../group___peripheral___registers___bits___definition.html#gad03b0ab4d686a1ad858f1ba4b679fff9',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r2_5ffb4_5fmsk_1010',['CAN_F13R2_FB4_Msk',['../group___peripheral___registers___bits___definition.html#ga0b936b6b027a2936ab21bd3f46c830aa',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r2_5ffb4_5fpos_1011',['CAN_F13R2_FB4_Pos',['../group___peripheral___registers___bits___definition.html#ga44666780046b34e5f5b14ba31f39cefc',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r2_5ffb5_1012',['CAN_F13R2_FB5',['../group___peripheral___registers___bits___definition.html#ga8e37522978ae2e88c27f5604c5517d42',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r2_5ffb5_5fmsk_1013',['CAN_F13R2_FB5_Msk',['../group___peripheral___registers___bits___definition.html#gaff4ab0ef27b2b9cc09019b73f3cffed1',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r2_5ffb5_5fpos_1014',['CAN_F13R2_FB5_Pos',['../group___peripheral___registers___bits___definition.html#gaa84e2ee25ea5266c9ebc55eb15b232ce',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r2_5ffb6_1015',['CAN_F13R2_FB6',['../group___peripheral___registers___bits___definition.html#ga2bf6fff2ca4adf6e093a13b2db77adbb',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r2_5ffb6_5fmsk_1016',['CAN_F13R2_FB6_Msk',['../group___peripheral___registers___bits___definition.html#gaf96e3c22df9a1af249c91056375c24dc',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r2_5ffb6_5fpos_1017',['CAN_F13R2_FB6_Pos',['../group___peripheral___registers___bits___definition.html#gabf66b4b2eff656482af6adcf8afc007b',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r2_5ffb7_1018',['CAN_F13R2_FB7',['../group___peripheral___registers___bits___definition.html#gabca970c306c9c9b576ef3424f686f324',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r2_5ffb7_5fmsk_1019',['CAN_F13R2_FB7_Msk',['../group___peripheral___registers___bits___definition.html#ga2d3accaea73cb0bb14c61c8327adff66',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r2_5ffb7_5fpos_1020',['CAN_F13R2_FB7_Pos',['../group___peripheral___registers___bits___definition.html#gaa23426711b2a872dc4c34147415f101c',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r2_5ffb8_1021',['CAN_F13R2_FB8',['../group___peripheral___registers___bits___definition.html#gae44e1d120c773c9dc26f418acf3cb6de',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r2_5ffb8_5fmsk_1022',['CAN_F13R2_FB8_Msk',['../group___peripheral___registers___bits___definition.html#ga5134cad65b0825f53f4f4e78f0c8e11c',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r2_5ffb8_5fpos_1023',['CAN_F13R2_FB8_Pos',['../group___peripheral___registers___bits___definition.html#ga3559eca84f9b7d1f99f2a7aee2e4393c',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r2_5ffb9_1024',['CAN_F13R2_FB9',['../group___peripheral___registers___bits___definition.html#ga891d1d97e1a57c4cfa1a714b61b083eb',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r2_5ffb9_5fmsk_1025',['CAN_F13R2_FB9_Msk',['../group___peripheral___registers___bits___definition.html#gaf13c3a79fcb1bc2bb884dcda8e10ffd0',1,'stm32f407xx_matlab.h']]], - ['can_5ff13r2_5ffb9_5fpos_1026',['CAN_F13R2_FB9_Pos',['../group___peripheral___registers___bits___definition.html#ga1c54a85b5280816543e0e415fbc96d09',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r1_5ffb0_1027',['CAN_F1R1_FB0',['../group___peripheral___registers___bits___definition.html#gaf74bbd84aff2eb3891f6f6d0c418793c',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r1_5ffb0_5fmsk_1028',['CAN_F1R1_FB0_Msk',['../group___peripheral___registers___bits___definition.html#ga7196f5a41c5a7692fa31249177a70de5',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r1_5ffb0_5fpos_1029',['CAN_F1R1_FB0_Pos',['../group___peripheral___registers___bits___definition.html#ga27eb131cdda754065a82c251b02d26ec',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r1_5ffb1_1030',['CAN_F1R1_FB1',['../group___peripheral___registers___bits___definition.html#gaa2cb33663f4220e5a0d416cbddcec193',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r1_5ffb10_1031',['CAN_F1R1_FB10',['../group___peripheral___registers___bits___definition.html#ga7f049fa606d557a8a468747c6d285357',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r1_5ffb10_5fmsk_1032',['CAN_F1R1_FB10_Msk',['../group___peripheral___registers___bits___definition.html#ga0dbe75098babb0ad9de21a966115c4cb',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r1_5ffb10_5fpos_1033',['CAN_F1R1_FB10_Pos',['../group___peripheral___registers___bits___definition.html#gaf483657f1c8087691588ad2b4e8aa007',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r1_5ffb11_1034',['CAN_F1R1_FB11',['../group___peripheral___registers___bits___definition.html#ga43409866ee9e6ea1712f50679a4bb212',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r1_5ffb11_5fmsk_1035',['CAN_F1R1_FB11_Msk',['../group___peripheral___registers___bits___definition.html#ga5b5ea83ec6fdbcc28d0f2c907276bec9',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r1_5ffb11_5fpos_1036',['CAN_F1R1_FB11_Pos',['../group___peripheral___registers___bits___definition.html#gad6ebfb27d5d594fdb472d31751a25092',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r1_5ffb12_1037',['CAN_F1R1_FB12',['../group___peripheral___registers___bits___definition.html#ga3f86fb2f2080f513d8392d389cdaa1fd',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r1_5ffb12_5fmsk_1038',['CAN_F1R1_FB12_Msk',['../group___peripheral___registers___bits___definition.html#gadd728a049ed7528b585dd56bd4e1d2cd',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r1_5ffb12_5fpos_1039',['CAN_F1R1_FB12_Pos',['../group___peripheral___registers___bits___definition.html#ga8f87b433c7752b209f54f04ecb3f2e40',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r1_5ffb13_1040',['CAN_F1R1_FB13',['../group___peripheral___registers___bits___definition.html#ga2c1b7aeeb196a6564b2b3f049590520e',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r1_5ffb13_5fmsk_1041',['CAN_F1R1_FB13_Msk',['../group___peripheral___registers___bits___definition.html#gabf67d90e15499f16cb9903c75ffa2cdd',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r1_5ffb13_5fpos_1042',['CAN_F1R1_FB13_Pos',['../group___peripheral___registers___bits___definition.html#gadcf14a236c390185aa76b3223e2ab573',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r1_5ffb14_1043',['CAN_F1R1_FB14',['../group___peripheral___registers___bits___definition.html#ga45bad406315318f9cecb0c783ac7218d',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r1_5ffb14_5fmsk_1044',['CAN_F1R1_FB14_Msk',['../group___peripheral___registers___bits___definition.html#ga5dd92e83b650c454a58a4e5bb0a2bae0',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r1_5ffb14_5fpos_1045',['CAN_F1R1_FB14_Pos',['../group___peripheral___registers___bits___definition.html#ga166ab6b1478e95f89a920b63c1fe83b3',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r1_5ffb15_1046',['CAN_F1R1_FB15',['../group___peripheral___registers___bits___definition.html#ga9b105deaf668c0e04950be0de975bcde',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r1_5ffb15_5fmsk_1047',['CAN_F1R1_FB15_Msk',['../group___peripheral___registers___bits___definition.html#ga303d03c806b2cd4ae51703db085ff55b',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r1_5ffb15_5fpos_1048',['CAN_F1R1_FB15_Pos',['../group___peripheral___registers___bits___definition.html#gae8dc185faf155706578f28896e413294',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r1_5ffb16_1049',['CAN_F1R1_FB16',['../group___peripheral___registers___bits___definition.html#ga84fabcf9736d7ef78587ff63cb6b1373',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r1_5ffb16_5fmsk_1050',['CAN_F1R1_FB16_Msk',['../group___peripheral___registers___bits___definition.html#gabd648d6b54d04ac636e7536a08d11ebb',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r1_5ffb16_5fpos_1051',['CAN_F1R1_FB16_Pos',['../group___peripheral___registers___bits___definition.html#ga9e9dd89c5bb2dbfb38154cf3d0f52f19',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r1_5ffb17_1052',['CAN_F1R1_FB17',['../group___peripheral___registers___bits___definition.html#ga966d41aca2269fd8cb6830dbbd176140',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r1_5ffb17_5fmsk_1053',['CAN_F1R1_FB17_Msk',['../group___peripheral___registers___bits___definition.html#ga48d839533fbd0dcc34aee11644d5f849',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r1_5ffb17_5fpos_1054',['CAN_F1R1_FB17_Pos',['../group___peripheral___registers___bits___definition.html#ga9816f741200a82b429a0ea6e18d4f481',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r1_5ffb18_1055',['CAN_F1R1_FB18',['../group___peripheral___registers___bits___definition.html#ga9a53cd0cf8722dc63b8ff26d4b0fa0f7',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r1_5ffb18_5fmsk_1056',['CAN_F1R1_FB18_Msk',['../group___peripheral___registers___bits___definition.html#gab67914799f407244afdbf1ade349dbf3',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r1_5ffb18_5fpos_1057',['CAN_F1R1_FB18_Pos',['../group___peripheral___registers___bits___definition.html#gae67138d3787bf67035e1eb1d7420b999',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r1_5ffb19_1058',['CAN_F1R1_FB19',['../group___peripheral___registers___bits___definition.html#ga3fb64b2b59f73045b3ead12ab1211b4b',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r1_5ffb19_5fmsk_1059',['CAN_F1R1_FB19_Msk',['../group___peripheral___registers___bits___definition.html#ga7e0c47dda83f3ce3f3e5b18f3fb93b35',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r1_5ffb19_5fpos_1060',['CAN_F1R1_FB19_Pos',['../group___peripheral___registers___bits___definition.html#gac725ea9b9e3b26ac347f66ccc4ddfae4',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r1_5ffb1_5fmsk_1061',['CAN_F1R1_FB1_Msk',['../group___peripheral___registers___bits___definition.html#gaa957dafcd250c1c36d38a0da7a94d0b6',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r1_5ffb1_5fpos_1062',['CAN_F1R1_FB1_Pos',['../group___peripheral___registers___bits___definition.html#ga1aecffb61aa34f1bfd36d4230fbf1e87',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r1_5ffb2_1063',['CAN_F1R1_FB2',['../group___peripheral___registers___bits___definition.html#ga86d75200e9ead1afbe88add086ac4bb4',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r1_5ffb20_1064',['CAN_F1R1_FB20',['../group___peripheral___registers___bits___definition.html#gad558faeeeaf748bdface31d4bd3ed5b6',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r1_5ffb20_5fmsk_1065',['CAN_F1R1_FB20_Msk',['../group___peripheral___registers___bits___definition.html#ga122f1435ff77893cee8ec0d39fbfb178',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r1_5ffb20_5fpos_1066',['CAN_F1R1_FB20_Pos',['../group___peripheral___registers___bits___definition.html#gaeba0bf91f16395564def3f873084dc0b',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r1_5ffb21_1067',['CAN_F1R1_FB21',['../group___peripheral___registers___bits___definition.html#gab16bc53f206b1f318e5fe8c248294fec',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r1_5ffb21_5fmsk_1068',['CAN_F1R1_FB21_Msk',['../group___peripheral___registers___bits___definition.html#ga7164f10425d3caf734b284f3bc3b5449',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r1_5ffb21_5fpos_1069',['CAN_F1R1_FB21_Pos',['../group___peripheral___registers___bits___definition.html#ga16a40175f3f3d5fdb28dc172aa7a1595',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r1_5ffb22_1070',['CAN_F1R1_FB22',['../group___peripheral___registers___bits___definition.html#ga42841c82744146dc70e8e679b5904e02',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r1_5ffb22_5fmsk_1071',['CAN_F1R1_FB22_Msk',['../group___peripheral___registers___bits___definition.html#ga3ddbed5a2b9531b528d32857123af10a',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r1_5ffb22_5fpos_1072',['CAN_F1R1_FB22_Pos',['../group___peripheral___registers___bits___definition.html#ga069b7dc2e0e3e0ab6445a2bf2bfc3bed',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r1_5ffb23_1073',['CAN_F1R1_FB23',['../group___peripheral___registers___bits___definition.html#gad1f961b642e42faaaf495c9ec099c128',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r1_5ffb23_5fmsk_1074',['CAN_F1R1_FB23_Msk',['../group___peripheral___registers___bits___definition.html#gaccc01c86ecce551ede43bfeafbbbb384',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r1_5ffb23_5fpos_1075',['CAN_F1R1_FB23_Pos',['../group___peripheral___registers___bits___definition.html#gaf1be33c0c1d5b547f65b90e763ac7bbd',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r1_5ffb24_1076',['CAN_F1R1_FB24',['../group___peripheral___registers___bits___definition.html#ga96670686c71a15631ec2f772973dd7d5',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r1_5ffb24_5fmsk_1077',['CAN_F1R1_FB24_Msk',['../group___peripheral___registers___bits___definition.html#ga9660622aa2fe3253f7b29e7591462002',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r1_5ffb24_5fpos_1078',['CAN_F1R1_FB24_Pos',['../group___peripheral___registers___bits___definition.html#ga2cf527d0f7d4dfa543c7961d56909885',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r1_5ffb25_1079',['CAN_F1R1_FB25',['../group___peripheral___registers___bits___definition.html#gaa2d8b1a30c3a6ae1f75369abc445ab7d',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r1_5ffb25_5fmsk_1080',['CAN_F1R1_FB25_Msk',['../group___peripheral___registers___bits___definition.html#gad0f80f8443876e5a992b6b320f19d537',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r1_5ffb25_5fpos_1081',['CAN_F1R1_FB25_Pos',['../group___peripheral___registers___bits___definition.html#gab6c5577c558a7f155db47732b868711c',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r1_5ffb26_1082',['CAN_F1R1_FB26',['../group___peripheral___registers___bits___definition.html#gaf027c958889ab93acfb1b86988269874',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r1_5ffb26_5fmsk_1083',['CAN_F1R1_FB26_Msk',['../group___peripheral___registers___bits___definition.html#gad90d82d2f8485e7e9a530992ac4a84e0',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r1_5ffb26_5fpos_1084',['CAN_F1R1_FB26_Pos',['../group___peripheral___registers___bits___definition.html#ga27cc17673e3a875235664981d3ca221a',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r1_5ffb27_1085',['CAN_F1R1_FB27',['../group___peripheral___registers___bits___definition.html#ga32400e283bc0037da21f0c913bb860b6',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r1_5ffb27_5fmsk_1086',['CAN_F1R1_FB27_Msk',['../group___peripheral___registers___bits___definition.html#ga1dd73fe9a0c9c29fcb103e241ed3c4af',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r1_5ffb27_5fpos_1087',['CAN_F1R1_FB27_Pos',['../group___peripheral___registers___bits___definition.html#ga2db09a50ddde24f79862191ca42bc451',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r1_5ffb28_1088',['CAN_F1R1_FB28',['../group___peripheral___registers___bits___definition.html#gadb0467d664f27b3ca8ef4ad220593c46',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r1_5ffb28_5fmsk_1089',['CAN_F1R1_FB28_Msk',['../group___peripheral___registers___bits___definition.html#gae1bc410d11b14bfa426de7b7977bee14',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r1_5ffb28_5fpos_1090',['CAN_F1R1_FB28_Pos',['../group___peripheral___registers___bits___definition.html#ga1e0fe7f80eac137fc59498aaf1a4cda5',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r1_5ffb29_1091',['CAN_F1R1_FB29',['../group___peripheral___registers___bits___definition.html#ga1c3e3090ab67a54830be208a628efd8f',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r1_5ffb29_5fmsk_1092',['CAN_F1R1_FB29_Msk',['../group___peripheral___registers___bits___definition.html#gac48a223c7f7282dc22db7c2e0d557f35',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r1_5ffb29_5fpos_1093',['CAN_F1R1_FB29_Pos',['../group___peripheral___registers___bits___definition.html#gaa51f300d424e7cd192b6af1f81cc2019',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r1_5ffb2_5fmsk_1094',['CAN_F1R1_FB2_Msk',['../group___peripheral___registers___bits___definition.html#gab76348b5edccc3dff80131b8c8c66d91',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r1_5ffb2_5fpos_1095',['CAN_F1R1_FB2_Pos',['../group___peripheral___registers___bits___definition.html#ga9e4d64e1f9cacf34eb857db24e2aaed7',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r1_5ffb3_1096',['CAN_F1R1_FB3',['../group___peripheral___registers___bits___definition.html#gaa4dbe3b567fca94f5d5e4c877e0383d4',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r1_5ffb30_1097',['CAN_F1R1_FB30',['../group___peripheral___registers___bits___definition.html#ga85034e026be1af5e45e5d15537449e6d',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r1_5ffb30_5fmsk_1098',['CAN_F1R1_FB30_Msk',['../group___peripheral___registers___bits___definition.html#gaf45ba201e41f2fd71cda39c7010f65e0',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r1_5ffb30_5fpos_1099',['CAN_F1R1_FB30_Pos',['../group___peripheral___registers___bits___definition.html#ga20dd3f33af971def89d8e3ca8abd8f63',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r1_5ffb31_1100',['CAN_F1R1_FB31',['../group___peripheral___registers___bits___definition.html#ga6ddfc083d58a190057fb67e4eb31136b',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r1_5ffb31_5fmsk_1101',['CAN_F1R1_FB31_Msk',['../group___peripheral___registers___bits___definition.html#gac1345bf0889997c6316180e9754c3e18',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r1_5ffb31_5fpos_1102',['CAN_F1R1_FB31_Pos',['../group___peripheral___registers___bits___definition.html#ga9e42f6407392d9744b324a3b9bca2ab8',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r1_5ffb3_5fmsk_1103',['CAN_F1R1_FB3_Msk',['../group___peripheral___registers___bits___definition.html#ga489dfc442d364861f5f985aae7651179',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r1_5ffb3_5fpos_1104',['CAN_F1R1_FB3_Pos',['../group___peripheral___registers___bits___definition.html#ga70b163a4031c8c84fd3b1691a0310ffa',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r1_5ffb4_1105',['CAN_F1R1_FB4',['../group___peripheral___registers___bits___definition.html#gab74c1e5fba0af06b783289d56a8d743a',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r1_5ffb4_5fmsk_1106',['CAN_F1R1_FB4_Msk',['../group___peripheral___registers___bits___definition.html#ga48fba4b8013f5aa76ca9008eb1942423',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r1_5ffb4_5fpos_1107',['CAN_F1R1_FB4_Pos',['../group___peripheral___registers___bits___definition.html#gadfea6ec572e4c78a63141351020434f3',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r1_5ffb5_1108',['CAN_F1R1_FB5',['../group___peripheral___registers___bits___definition.html#ga163dda15630c6f057bac420a8cb393d8',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r1_5ffb5_5fmsk_1109',['CAN_F1R1_FB5_Msk',['../group___peripheral___registers___bits___definition.html#ga13b02c35ea2380f0f839784fc618090a',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r1_5ffb5_5fpos_1110',['CAN_F1R1_FB5_Pos',['../group___peripheral___registers___bits___definition.html#ga07413947413c933237227a8f37ac6728',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r1_5ffb6_1111',['CAN_F1R1_FB6',['../group___peripheral___registers___bits___definition.html#gadd27041e24d500c940abed9aaa53910d',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r1_5ffb6_5fmsk_1112',['CAN_F1R1_FB6_Msk',['../group___peripheral___registers___bits___definition.html#gacbe821726bd0ab42de7eb6ba9b497e56',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r1_5ffb6_5fpos_1113',['CAN_F1R1_FB6_Pos',['../group___peripheral___registers___bits___definition.html#ga0428081f736b6a2888514dccd2af1f28',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r1_5ffb7_1114',['CAN_F1R1_FB7',['../group___peripheral___registers___bits___definition.html#gaadfffc15f309b85cc3abd7439ea4b8c6',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r1_5ffb7_5fmsk_1115',['CAN_F1R1_FB7_Msk',['../group___peripheral___registers___bits___definition.html#ga655b773dfa0dfe1e62cd8560a8dcb150',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r1_5ffb7_5fpos_1116',['CAN_F1R1_FB7_Pos',['../group___peripheral___registers___bits___definition.html#ga5f7fad2e9157b6680041f1a4ff200af4',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r1_5ffb8_1117',['CAN_F1R1_FB8',['../group___peripheral___registers___bits___definition.html#gadf2588b13464de27f12768d33a75d2ba',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r1_5ffb8_5fmsk_1118',['CAN_F1R1_FB8_Msk',['../group___peripheral___registers___bits___definition.html#gaa1dd516a1cf52c63b64b028d7528da7b',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r1_5ffb8_5fpos_1119',['CAN_F1R1_FB8_Pos',['../group___peripheral___registers___bits___definition.html#ga72753a76f8413d0a00ace38793d7ec9a',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r1_5ffb9_1120',['CAN_F1R1_FB9',['../group___peripheral___registers___bits___definition.html#ga979839e5c63f94eb294a09b74f5c09bf',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r1_5ffb9_5fmsk_1121',['CAN_F1R1_FB9_Msk',['../group___peripheral___registers___bits___definition.html#ga4645154d1f265dee267626ae43e35eae',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r1_5ffb9_5fpos_1122',['CAN_F1R1_FB9_Pos',['../group___peripheral___registers___bits___definition.html#ga80f45f8de5ab075f633d21443c8b2226',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r2_5ffb0_1123',['CAN_F1R2_FB0',['../group___peripheral___registers___bits___definition.html#ga7ea3c5d8ab8962d9cd0e2b067167d3d4',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r2_5ffb0_5fmsk_1124',['CAN_F1R2_FB0_Msk',['../group___peripheral___registers___bits___definition.html#gac37390e12fa87a072599d57c581f82b1',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r2_5ffb0_5fpos_1125',['CAN_F1R2_FB0_Pos',['../group___peripheral___registers___bits___definition.html#ga0dec2c89cd678f3fd1fa90ba991c77c8',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r2_5ffb1_1126',['CAN_F1R2_FB1',['../group___peripheral___registers___bits___definition.html#gacfa5449488e7330d8f11f75fcf3e75cd',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r2_5ffb10_1127',['CAN_F1R2_FB10',['../group___peripheral___registers___bits___definition.html#ga915236a6b5081c2c30bd4d49144bc463',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r2_5ffb10_5fmsk_1128',['CAN_F1R2_FB10_Msk',['../group___peripheral___registers___bits___definition.html#gac4fa9a6d11d4066ce8cbed7772e5c4c1',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r2_5ffb10_5fpos_1129',['CAN_F1R2_FB10_Pos',['../group___peripheral___registers___bits___definition.html#ga4282afc9cf64def8be2dfe7cab903113',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r2_5ffb11_1130',['CAN_F1R2_FB11',['../group___peripheral___registers___bits___definition.html#gabf1aa2e62d4eede199196f81795d309c',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r2_5ffb11_5fmsk_1131',['CAN_F1R2_FB11_Msk',['../group___peripheral___registers___bits___definition.html#gaa1aef88c920add1bcec693ba43f890cf',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r2_5ffb11_5fpos_1132',['CAN_F1R2_FB11_Pos',['../group___peripheral___registers___bits___definition.html#ga796f12ffae3a26f7e0211f55db51da75',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r2_5ffb12_1133',['CAN_F1R2_FB12',['../group___peripheral___registers___bits___definition.html#ga7db0ae3dcaab35e4c496c8a800b5c994',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r2_5ffb12_5fmsk_1134',['CAN_F1R2_FB12_Msk',['../group___peripheral___registers___bits___definition.html#ga4486004019a70c1c41822611cfbc24a7',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r2_5ffb12_5fpos_1135',['CAN_F1R2_FB12_Pos',['../group___peripheral___registers___bits___definition.html#ga4000100330d542f8d6375d4ccd450d6d',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r2_5ffb13_1136',['CAN_F1R2_FB13',['../group___peripheral___registers___bits___definition.html#ga02cdb71c56a5d9994ecd2dee668c7184',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r2_5ffb13_5fmsk_1137',['CAN_F1R2_FB13_Msk',['../group___peripheral___registers___bits___definition.html#ga32ef2954ebc503eaf6c44eb4ec9a593e',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r2_5ffb13_5fpos_1138',['CAN_F1R2_FB13_Pos',['../group___peripheral___registers___bits___definition.html#gaadc9998290934d01441ce5d05b335868',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r2_5ffb14_1139',['CAN_F1R2_FB14',['../group___peripheral___registers___bits___definition.html#gac66691ca840db6c861460d311a942a87',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r2_5ffb14_5fmsk_1140',['CAN_F1R2_FB14_Msk',['../group___peripheral___registers___bits___definition.html#gace28daab139f94dc2ed7e388fd1b9b59',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r2_5ffb14_5fpos_1141',['CAN_F1R2_FB14_Pos',['../group___peripheral___registers___bits___definition.html#ga412671533d237ac1b2abce675e53e41e',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r2_5ffb15_1142',['CAN_F1R2_FB15',['../group___peripheral___registers___bits___definition.html#gabcdd57022e26859db1f81f2df08c8725',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r2_5ffb15_5fmsk_1143',['CAN_F1R2_FB15_Msk',['../group___peripheral___registers___bits___definition.html#gadbb0a0b5dd87d593fc1cf8b9269bf365',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r2_5ffb15_5fpos_1144',['CAN_F1R2_FB15_Pos',['../group___peripheral___registers___bits___definition.html#ga2face19f24a4459fc7aff4ca49fcb300',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r2_5ffb16_1145',['CAN_F1R2_FB16',['../group___peripheral___registers___bits___definition.html#ga211795b36769a0b87044f0d82a7a72b1',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r2_5ffb16_5fmsk_1146',['CAN_F1R2_FB16_Msk',['../group___peripheral___registers___bits___definition.html#ga427c05edd87c70fb5bfede3ece583106',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r2_5ffb16_5fpos_1147',['CAN_F1R2_FB16_Pos',['../group___peripheral___registers___bits___definition.html#gaf4e63a8d7f11fab2b9970eb9402164a1',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r2_5ffb17_1148',['CAN_F1R2_FB17',['../group___peripheral___registers___bits___definition.html#gabc8c427731f33c76fad0873bb29a4b4c',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r2_5ffb17_5fmsk_1149',['CAN_F1R2_FB17_Msk',['../group___peripheral___registers___bits___definition.html#ga4e7423c9dd0740125ba2dc7a9068c449',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r2_5ffb17_5fpos_1150',['CAN_F1R2_FB17_Pos',['../group___peripheral___registers___bits___definition.html#gac5972a3d5d5b18772e834e3f56e6d3b1',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r2_5ffb18_1151',['CAN_F1R2_FB18',['../group___peripheral___registers___bits___definition.html#ga10a3e6be9968b8007562e7afe6b3b342',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r2_5ffb18_5fmsk_1152',['CAN_F1R2_FB18_Msk',['../group___peripheral___registers___bits___definition.html#gadcea3b8cd42bcc687c67e62a0ccf7471',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r2_5ffb18_5fpos_1153',['CAN_F1R2_FB18_Pos',['../group___peripheral___registers___bits___definition.html#gab5916963935ba1112457ff7f497a3105',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r2_5ffb19_1154',['CAN_F1R2_FB19',['../group___peripheral___registers___bits___definition.html#ga4aac6ab4bd4cdeecbe621adf1d11b95a',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r2_5ffb19_5fmsk_1155',['CAN_F1R2_FB19_Msk',['../group___peripheral___registers___bits___definition.html#gae3e119637508ebc998e04873befdea02',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r2_5ffb19_5fpos_1156',['CAN_F1R2_FB19_Pos',['../group___peripheral___registers___bits___definition.html#ga925a99e3a206a826cc1abf0bd4adb42f',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r2_5ffb1_5fmsk_1157',['CAN_F1R2_FB1_Msk',['../group___peripheral___registers___bits___definition.html#ga4f4652769a8b81aefaa5acbaddc83e47',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r2_5ffb1_5fpos_1158',['CAN_F1R2_FB1_Pos',['../group___peripheral___registers___bits___definition.html#gaa6841efe21767654ecaee1bb96755970',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r2_5ffb2_1159',['CAN_F1R2_FB2',['../group___peripheral___registers___bits___definition.html#gafe49a3e224459f1bd9b3279ebfa8803b',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r2_5ffb20_1160',['CAN_F1R2_FB20',['../group___peripheral___registers___bits___definition.html#ga30140ced3da0d0a526c4f4f5881987c1',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r2_5ffb20_5fmsk_1161',['CAN_F1R2_FB20_Msk',['../group___peripheral___registers___bits___definition.html#ga6adb312018dfbe719072be0d6444b62a',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r2_5ffb20_5fpos_1162',['CAN_F1R2_FB20_Pos',['../group___peripheral___registers___bits___definition.html#ga9fe55799241f27062746e57409e2e9f4',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r2_5ffb21_1163',['CAN_F1R2_FB21',['../group___peripheral___registers___bits___definition.html#ga49f36aec2e851ed18c5a382a0708bbcb',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r2_5ffb21_5fmsk_1164',['CAN_F1R2_FB21_Msk',['../group___peripheral___registers___bits___definition.html#ga23a75816e8e01c5c9a90d7b2afa4716f',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r2_5ffb21_5fpos_1165',['CAN_F1R2_FB21_Pos',['../group___peripheral___registers___bits___definition.html#gacfa97c392ee8e456dd9ffd6498590c11',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r2_5ffb22_1166',['CAN_F1R2_FB22',['../group___peripheral___registers___bits___definition.html#ga99ccab06a8a97616a2fc3e026f36351d',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r2_5ffb22_5fmsk_1167',['CAN_F1R2_FB22_Msk',['../group___peripheral___registers___bits___definition.html#gace263ed2b1dcb26232c8be718c733490',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r2_5ffb22_5fpos_1168',['CAN_F1R2_FB22_Pos',['../group___peripheral___registers___bits___definition.html#ga948b363bcf4905731e758e1353c58bde',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r2_5ffb23_1169',['CAN_F1R2_FB23',['../group___peripheral___registers___bits___definition.html#gaaa408889ff6478d6558d4c53c9114bde',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r2_5ffb23_5fmsk_1170',['CAN_F1R2_FB23_Msk',['../group___peripheral___registers___bits___definition.html#ga15089c114f7120bd834ecddd74795989',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r2_5ffb23_5fpos_1171',['CAN_F1R2_FB23_Pos',['../group___peripheral___registers___bits___definition.html#ga166035cac78d72360b8019ede0ec3bf7',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r2_5ffb24_1172',['CAN_F1R2_FB24',['../group___peripheral___registers___bits___definition.html#ga032dd8dc11aa9013cc0e824e31932951',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r2_5ffb24_5fmsk_1173',['CAN_F1R2_FB24_Msk',['../group___peripheral___registers___bits___definition.html#ga256936e5e1dc313a5846bcdb38746940',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r2_5ffb24_5fpos_1174',['CAN_F1R2_FB24_Pos',['../group___peripheral___registers___bits___definition.html#ga6b63bc70f339f5773288cb786e9c4459',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r2_5ffb25_1175',['CAN_F1R2_FB25',['../group___peripheral___registers___bits___definition.html#ga76f29020524ec6403a40de4e260a2ea8',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r2_5ffb25_5fmsk_1176',['CAN_F1R2_FB25_Msk',['../group___peripheral___registers___bits___definition.html#ga8861d429f3e5a4cf24015dd24d1035a2',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r2_5ffb25_5fpos_1177',['CAN_F1R2_FB25_Pos',['../group___peripheral___registers___bits___definition.html#gab5bd608220a283001eb3e0739c4b9971',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r2_5ffb26_1178',['CAN_F1R2_FB26',['../group___peripheral___registers___bits___definition.html#ga0bb51cd27fea671be51a59ce7a83008e',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r2_5ffb26_5fmsk_1179',['CAN_F1R2_FB26_Msk',['../group___peripheral___registers___bits___definition.html#gaaca03affd919dc4618d7e47f545714fe',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r2_5ffb26_5fpos_1180',['CAN_F1R2_FB26_Pos',['../group___peripheral___registers___bits___definition.html#ga244707ad262266c922ff70945babc147',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r2_5ffb27_1181',['CAN_F1R2_FB27',['../group___peripheral___registers___bits___definition.html#ga085c38b511aa4895b6c939a06070c916',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r2_5ffb27_5fmsk_1182',['CAN_F1R2_FB27_Msk',['../group___peripheral___registers___bits___definition.html#ga4685d281238d461eb78b7f846411f6f3',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r2_5ffb27_5fpos_1183',['CAN_F1R2_FB27_Pos',['../group___peripheral___registers___bits___definition.html#ga3cee8ad67d0accf75e5808747e189153',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r2_5ffb28_1184',['CAN_F1R2_FB28',['../group___peripheral___registers___bits___definition.html#gabe299378c771da8d7d8e72a6f6e41f7f',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r2_5ffb28_5fmsk_1185',['CAN_F1R2_FB28_Msk',['../group___peripheral___registers___bits___definition.html#ga2a6e9dc7e9d061ce75e04aceae3cfd6b',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r2_5ffb28_5fpos_1186',['CAN_F1R2_FB28_Pos',['../group___peripheral___registers___bits___definition.html#ga28c98f10f41c0d71c4d462d4d12dfa66',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r2_5ffb29_1187',['CAN_F1R2_FB29',['../group___peripheral___registers___bits___definition.html#gaabc8bef79b09bcfcb0df6ba467ed906b',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r2_5ffb29_5fmsk_1188',['CAN_F1R2_FB29_Msk',['../group___peripheral___registers___bits___definition.html#ga7fee7c49b899c8af5ae4b60d47461ea2',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r2_5ffb29_5fpos_1189',['CAN_F1R2_FB29_Pos',['../group___peripheral___registers___bits___definition.html#gae336a2f0d44c4ca3a991014f28c2bdff',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r2_5ffb2_5fmsk_1190',['CAN_F1R2_FB2_Msk',['../group___peripheral___registers___bits___definition.html#ga550988821dc17b71e58d745367d552fb',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r2_5ffb2_5fpos_1191',['CAN_F1R2_FB2_Pos',['../group___peripheral___registers___bits___definition.html#ga622010c50665f9ae395641902d1834d4',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r2_5ffb3_1192',['CAN_F1R2_FB3',['../group___peripheral___registers___bits___definition.html#ga77cf2217ec29e2043bada827249dedd5',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r2_5ffb30_1193',['CAN_F1R2_FB30',['../group___peripheral___registers___bits___definition.html#gabc4aba2c95f27229987d9eb4cda9890c',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r2_5ffb30_5fmsk_1194',['CAN_F1R2_FB30_Msk',['../group___peripheral___registers___bits___definition.html#gab87ec718cd11264085752c85b44e6ef3',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r2_5ffb30_5fpos_1195',['CAN_F1R2_FB30_Pos',['../group___peripheral___registers___bits___definition.html#ga461e28c08af3e31dacf1b1cd7b8ffcc4',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r2_5ffb31_1196',['CAN_F1R2_FB31',['../group___peripheral___registers___bits___definition.html#ga21cbfc217d67062d265753964c871065',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r2_5ffb31_5fmsk_1197',['CAN_F1R2_FB31_Msk',['../group___peripheral___registers___bits___definition.html#ga9cebad85393ecc2a9214f9788b77c676',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r2_5ffb31_5fpos_1198',['CAN_F1R2_FB31_Pos',['../group___peripheral___registers___bits___definition.html#gafe23be59ff4543be1a357b9bc235ac6e',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r2_5ffb3_5fmsk_1199',['CAN_F1R2_FB3_Msk',['../group___peripheral___registers___bits___definition.html#gad52c7978074227730285d698cdcb15c7',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r2_5ffb3_5fpos_1200',['CAN_F1R2_FB3_Pos',['../group___peripheral___registers___bits___definition.html#ga24e392fb487c7c70667c53e868bd8ec7',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r2_5ffb4_1201',['CAN_F1R2_FB4',['../group___peripheral___registers___bits___definition.html#gaf35643f0148ed0f93e3ba52e95a4cf6b',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r2_5ffb4_5fmsk_1202',['CAN_F1R2_FB4_Msk',['../group___peripheral___registers___bits___definition.html#gab404d9e8cd80526beb5b83ea62236c40',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r2_5ffb4_5fpos_1203',['CAN_F1R2_FB4_Pos',['../group___peripheral___registers___bits___definition.html#ga937b036cc35761691dae4719da547038',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r2_5ffb5_1204',['CAN_F1R2_FB5',['../group___peripheral___registers___bits___definition.html#gae08798adabd9cc0fb2b07eaff6444878',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r2_5ffb5_5fmsk_1205',['CAN_F1R2_FB5_Msk',['../group___peripheral___registers___bits___definition.html#ga3210b70ca25333f077035c8178683b3c',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r2_5ffb5_5fpos_1206',['CAN_F1R2_FB5_Pos',['../group___peripheral___registers___bits___definition.html#gaf9021382fb04157c3a4ea991a1a0d654',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r2_5ffb6_1207',['CAN_F1R2_FB6',['../group___peripheral___registers___bits___definition.html#ga06659c9a418d7f4a8729d87bc397be23',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r2_5ffb6_5fmsk_1208',['CAN_F1R2_FB6_Msk',['../group___peripheral___registers___bits___definition.html#gab840206e4408eeadf35ca5ce492121b7',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r2_5ffb6_5fpos_1209',['CAN_F1R2_FB6_Pos',['../group___peripheral___registers___bits___definition.html#ga282ffe71282dcacb6bd4a49da646a7ae',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r2_5ffb7_1210',['CAN_F1R2_FB7',['../group___peripheral___registers___bits___definition.html#ga36bb9ca8dadd6714052f8d31cb01cb7b',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r2_5ffb7_5fmsk_1211',['CAN_F1R2_FB7_Msk',['../group___peripheral___registers___bits___definition.html#ga93f9f5471e1a8abd2ca55fe5a4cf120f',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r2_5ffb7_5fpos_1212',['CAN_F1R2_FB7_Pos',['../group___peripheral___registers___bits___definition.html#ga34ffa785ed1b4ab61dfcb4e5d203ec57',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r2_5ffb8_1213',['CAN_F1R2_FB8',['../group___peripheral___registers___bits___definition.html#ga2d400044261146be3deb722d9cf3d5c1',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r2_5ffb8_5fmsk_1214',['CAN_F1R2_FB8_Msk',['../group___peripheral___registers___bits___definition.html#gade520b46b08abd462743828dfdb211e1',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r2_5ffb8_5fpos_1215',['CAN_F1R2_FB8_Pos',['../group___peripheral___registers___bits___definition.html#ga83f47b48b80736f5526b826a9150e32a',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r2_5ffb9_1216',['CAN_F1R2_FB9',['../group___peripheral___registers___bits___definition.html#gab3e5769ea8faaed16c6cb2ce979d28a9',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r2_5ffb9_5fmsk_1217',['CAN_F1R2_FB9_Msk',['../group___peripheral___registers___bits___definition.html#ga28e355feec329b328d200ea79a3c4e73',1,'stm32f407xx_matlab.h']]], - ['can_5ff1r2_5ffb9_5fpos_1218',['CAN_F1R2_FB9_Pos',['../group___peripheral___registers___bits___definition.html#gad5018a74c3736b3246b93e642100f1d9',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r1_5ffb0_1219',['CAN_F2R1_FB0',['../group___peripheral___registers___bits___definition.html#gaf17f4c3e553020ee893415796bd29d84',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r1_5ffb0_5fmsk_1220',['CAN_F2R1_FB0_Msk',['../group___peripheral___registers___bits___definition.html#gac32a7356281dd4bfe7825df1f7cf2cb9',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r1_5ffb0_5fpos_1221',['CAN_F2R1_FB0_Pos',['../group___peripheral___registers___bits___definition.html#ga6d22e35b14dc0fd47606ec3e9f5433f0',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r1_5ffb1_1222',['CAN_F2R1_FB1',['../group___peripheral___registers___bits___definition.html#gae97de172023462e5f40d4b420209809b',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r1_5ffb10_1223',['CAN_F2R1_FB10',['../group___peripheral___registers___bits___definition.html#ga022da7a86e8174aff1054eb1aef2c73c',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r1_5ffb10_5fmsk_1224',['CAN_F2R1_FB10_Msk',['../group___peripheral___registers___bits___definition.html#gae64a55a94cadc65b398bd15569223715',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r1_5ffb10_5fpos_1225',['CAN_F2R1_FB10_Pos',['../group___peripheral___registers___bits___definition.html#ga4bb1104df1f5ea9a52bad81c16a10f93',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r1_5ffb11_1226',['CAN_F2R1_FB11',['../group___peripheral___registers___bits___definition.html#gaedf715fa1ef43c8461408944e4aecec7',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r1_5ffb11_5fmsk_1227',['CAN_F2R1_FB11_Msk',['../group___peripheral___registers___bits___definition.html#gaaeac622ae5a702f2f5ca04eb6d07ba57',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r1_5ffb11_5fpos_1228',['CAN_F2R1_FB11_Pos',['../group___peripheral___registers___bits___definition.html#gab8284e29a6acceb7cc51554bb5c1f4e9',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r1_5ffb12_1229',['CAN_F2R1_FB12',['../group___peripheral___registers___bits___definition.html#ga47960a79c582cbc9bfef85c411a2be94',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r1_5ffb12_5fmsk_1230',['CAN_F2R1_FB12_Msk',['../group___peripheral___registers___bits___definition.html#ga6dae1f468ba956371b53f200658cb93e',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r1_5ffb12_5fpos_1231',['CAN_F2R1_FB12_Pos',['../group___peripheral___registers___bits___definition.html#gacccd6d7c8fed17e8a960cdea12e9937c',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r1_5ffb13_1232',['CAN_F2R1_FB13',['../group___peripheral___registers___bits___definition.html#gae8c6e3cf3a4d1e9d722e820a3a0c1b6a',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r1_5ffb13_5fmsk_1233',['CAN_F2R1_FB13_Msk',['../group___peripheral___registers___bits___definition.html#ga82190e04cc99936f1670f81b3e3306d5',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r1_5ffb13_5fpos_1234',['CAN_F2R1_FB13_Pos',['../group___peripheral___registers___bits___definition.html#ga859f236a687e19660de99278b9f5639e',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r1_5ffb14_1235',['CAN_F2R1_FB14',['../group___peripheral___registers___bits___definition.html#ga421a366074fb422686461a92abd1259e',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r1_5ffb14_5fmsk_1236',['CAN_F2R1_FB14_Msk',['../group___peripheral___registers___bits___definition.html#gae6722c1954e4dc9dce4931ca68545afd',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r1_5ffb14_5fpos_1237',['CAN_F2R1_FB14_Pos',['../group___peripheral___registers___bits___definition.html#ga719777f190551358a8e55b4551246985',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r1_5ffb15_1238',['CAN_F2R1_FB15',['../group___peripheral___registers___bits___definition.html#ga178a0308db954b97818401be1f28a990',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r1_5ffb15_5fmsk_1239',['CAN_F2R1_FB15_Msk',['../group___peripheral___registers___bits___definition.html#ga3f6b097d716445b57eb181592d9543c7',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r1_5ffb15_5fpos_1240',['CAN_F2R1_FB15_Pos',['../group___peripheral___registers___bits___definition.html#ga37fe8abfa46f0bd92db7f7a8c67f89b5',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r1_5ffb16_1241',['CAN_F2R1_FB16',['../group___peripheral___registers___bits___definition.html#gab60aef7e45f8d12777032321a33cdb38',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r1_5ffb16_5fmsk_1242',['CAN_F2R1_FB16_Msk',['../group___peripheral___registers___bits___definition.html#ga0d3c41f4d8ac19d40bc8ce0a6c4bf7bf',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r1_5ffb16_5fpos_1243',['CAN_F2R1_FB16_Pos',['../group___peripheral___registers___bits___definition.html#ga16b5440836903f347ea7693c40da4a01',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r1_5ffb17_1244',['CAN_F2R1_FB17',['../group___peripheral___registers___bits___definition.html#ga0483dac5b6986246a3ba106fbeb8e3bd',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r1_5ffb17_5fmsk_1245',['CAN_F2R1_FB17_Msk',['../group___peripheral___registers___bits___definition.html#gaa515e5239f2fb3f7669106b0a42ce00b',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r1_5ffb17_5fpos_1246',['CAN_F2R1_FB17_Pos',['../group___peripheral___registers___bits___definition.html#ga5a962747d2c8ba69f77cccef2add0bf9',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r1_5ffb18_1247',['CAN_F2R1_FB18',['../group___peripheral___registers___bits___definition.html#ga259b472c9c9f158e1701c8b8d5a940b9',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r1_5ffb18_5fmsk_1248',['CAN_F2R1_FB18_Msk',['../group___peripheral___registers___bits___definition.html#ga7132daf6ddf622a30b31b0dc82b77bcf',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r1_5ffb18_5fpos_1249',['CAN_F2R1_FB18_Pos',['../group___peripheral___registers___bits___definition.html#ga70c37fe14d32d847ebb6880849d71e11',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r1_5ffb19_1250',['CAN_F2R1_FB19',['../group___peripheral___registers___bits___definition.html#ga23db612c79422bee815e437d6aaf5a6c',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r1_5ffb19_5fmsk_1251',['CAN_F2R1_FB19_Msk',['../group___peripheral___registers___bits___definition.html#ga55a8f0a1951ca9c9e8cdbac39f64ec6e',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r1_5ffb19_5fpos_1252',['CAN_F2R1_FB19_Pos',['../group___peripheral___registers___bits___definition.html#gab020e6235fe4c66882df3b253b4898ef',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r1_5ffb1_5fmsk_1253',['CAN_F2R1_FB1_Msk',['../group___peripheral___registers___bits___definition.html#ga63a45584a55de290532b6835fadf480a',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r1_5ffb1_5fpos_1254',['CAN_F2R1_FB1_Pos',['../group___peripheral___registers___bits___definition.html#ga0bde9b889c0e03d67ce1432aecbd75ce',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r1_5ffb2_1255',['CAN_F2R1_FB2',['../group___peripheral___registers___bits___definition.html#ga23008ac61893eb6a65ab9041c53a84ee',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r1_5ffb20_1256',['CAN_F2R1_FB20',['../group___peripheral___registers___bits___definition.html#gaef9a469e877bfa29f4edb66730c43d43',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r1_5ffb20_5fmsk_1257',['CAN_F2R1_FB20_Msk',['../group___peripheral___registers___bits___definition.html#ga58042a29bd588ca97015f8de46239641',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r1_5ffb20_5fpos_1258',['CAN_F2R1_FB20_Pos',['../group___peripheral___registers___bits___definition.html#ga32775644499bea180ed6be905e3ac7bc',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r1_5ffb21_1259',['CAN_F2R1_FB21',['../group___peripheral___registers___bits___definition.html#ga4edc4a54cc13f63afe8dbe3aa37776a5',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r1_5ffb21_5fmsk_1260',['CAN_F2R1_FB21_Msk',['../group___peripheral___registers___bits___definition.html#gad6e2ea1ce258fc480fb8b2b12a885c9f',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r1_5ffb21_5fpos_1261',['CAN_F2R1_FB21_Pos',['../group___peripheral___registers___bits___definition.html#gaaeb4b573d828f2498db857114f0b554f',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r1_5ffb22_1262',['CAN_F2R1_FB22',['../group___peripheral___registers___bits___definition.html#ga169f5fb3dd35ae2b048c8c05c3e202d7',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r1_5ffb22_5fmsk_1263',['CAN_F2R1_FB22_Msk',['../group___peripheral___registers___bits___definition.html#gacc6ff16cdc9d4b088573f668d99747af',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r1_5ffb22_5fpos_1264',['CAN_F2R1_FB22_Pos',['../group___peripheral___registers___bits___definition.html#ga4ed5841ad79cc5cf7e76cc3315b65497',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r1_5ffb23_1265',['CAN_F2R1_FB23',['../group___peripheral___registers___bits___definition.html#ga0073b206235b3c33a9b831e5027e3bf0',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r1_5ffb23_5fmsk_1266',['CAN_F2R1_FB23_Msk',['../group___peripheral___registers___bits___definition.html#gad9dd3a87b66e7f305670c551b67bff47',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r1_5ffb23_5fpos_1267',['CAN_F2R1_FB23_Pos',['../group___peripheral___registers___bits___definition.html#gae3ced515beee7bd23f0d93610bab275b',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r1_5ffb24_1268',['CAN_F2R1_FB24',['../group___peripheral___registers___bits___definition.html#ga459caea38417d17c042e52ba38eb3c1b',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r1_5ffb24_5fmsk_1269',['CAN_F2R1_FB24_Msk',['../group___peripheral___registers___bits___definition.html#ga353eaadcd9e7a6ffd389c81f75e5b860',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r1_5ffb24_5fpos_1270',['CAN_F2R1_FB24_Pos',['../group___peripheral___registers___bits___definition.html#gafe33b16774b21585c3661fbe2d9123cd',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r1_5ffb25_1271',['CAN_F2R1_FB25',['../group___peripheral___registers___bits___definition.html#gae0da8cd8657f6e67f1d86fc9f695bb4e',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r1_5ffb25_5fmsk_1272',['CAN_F2R1_FB25_Msk',['../group___peripheral___registers___bits___definition.html#ga6516de993c142d8a23cc647e9b06ecd2',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r1_5ffb25_5fpos_1273',['CAN_F2R1_FB25_Pos',['../group___peripheral___registers___bits___definition.html#ga56ce415708ca6b0de210d624e9a5f606',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r1_5ffb26_1274',['CAN_F2R1_FB26',['../group___peripheral___registers___bits___definition.html#ga80c9ae7f2eca3db813737c49d49f2b08',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r1_5ffb26_5fmsk_1275',['CAN_F2R1_FB26_Msk',['../group___peripheral___registers___bits___definition.html#ga14b6583d5cb48decd72eb2bee4113c48',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r1_5ffb26_5fpos_1276',['CAN_F2R1_FB26_Pos',['../group___peripheral___registers___bits___definition.html#ga110456643d2876e34dd02e537d9c0453',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r1_5ffb27_1277',['CAN_F2R1_FB27',['../group___peripheral___registers___bits___definition.html#ga1d6b6c109e359e3d2a07e6626c2b4aff',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r1_5ffb27_5fmsk_1278',['CAN_F2R1_FB27_Msk',['../group___peripheral___registers___bits___definition.html#ga14b6942aff7b854ed29d7bb8affba388',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r1_5ffb27_5fpos_1279',['CAN_F2R1_FB27_Pos',['../group___peripheral___registers___bits___definition.html#ga5bfbbc6638ac01d28fe719942ed800cd',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r1_5ffb28_1280',['CAN_F2R1_FB28',['../group___peripheral___registers___bits___definition.html#ga3c4d05997d8930291c8ab2bb19545714',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r1_5ffb28_5fmsk_1281',['CAN_F2R1_FB28_Msk',['../group___peripheral___registers___bits___definition.html#gab6d262f3000a3723269b53cf0c4f3ad2',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r1_5ffb28_5fpos_1282',['CAN_F2R1_FB28_Pos',['../group___peripheral___registers___bits___definition.html#ga782f72de6bdfb681a0790934b38ff480',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r1_5ffb29_1283',['CAN_F2R1_FB29',['../group___peripheral___registers___bits___definition.html#gad5431f98aafd2a7f8158a335d65ebea1',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r1_5ffb29_5fmsk_1284',['CAN_F2R1_FB29_Msk',['../group___peripheral___registers___bits___definition.html#ga7dc1ecaa773500c32c41363b2dff8e72',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r1_5ffb29_5fpos_1285',['CAN_F2R1_FB29_Pos',['../group___peripheral___registers___bits___definition.html#ga0cb04ee516341a536f69fb6c4b87f8b9',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r1_5ffb2_5fmsk_1286',['CAN_F2R1_FB2_Msk',['../group___peripheral___registers___bits___definition.html#ga42aa2e179dd31d2ef7373acb814223f2',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r1_5ffb2_5fpos_1287',['CAN_F2R1_FB2_Pos',['../group___peripheral___registers___bits___definition.html#gacccd928df24722f7ac8cc22de452ab4b',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r1_5ffb3_1288',['CAN_F2R1_FB3',['../group___peripheral___registers___bits___definition.html#gad559580b386d0c621a6bf7292c706e36',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r1_5ffb30_1289',['CAN_F2R1_FB30',['../group___peripheral___registers___bits___definition.html#gad79345a758898023543bd5384be09758',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r1_5ffb30_5fmsk_1290',['CAN_F2R1_FB30_Msk',['../group___peripheral___registers___bits___definition.html#ga317461fc99abac5a1b3c44487499d315',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r1_5ffb30_5fpos_1291',['CAN_F2R1_FB30_Pos',['../group___peripheral___registers___bits___definition.html#gabb8ecceb7be34c41af7c161d223689a8',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r1_5ffb31_1292',['CAN_F2R1_FB31',['../group___peripheral___registers___bits___definition.html#gaada8442f47c1fffb00c13e404d036122',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r1_5ffb31_5fmsk_1293',['CAN_F2R1_FB31_Msk',['../group___peripheral___registers___bits___definition.html#ga4ef1c89364eec52f78811d7a8e40d0b4',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r1_5ffb31_5fpos_1294',['CAN_F2R1_FB31_Pos',['../group___peripheral___registers___bits___definition.html#gab22488fb69df08c9ffc310f3ab575d02',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r1_5ffb3_5fmsk_1295',['CAN_F2R1_FB3_Msk',['../group___peripheral___registers___bits___definition.html#gafc7f6fc0a5744d9f9246ae814dde3a00',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r1_5ffb3_5fpos_1296',['CAN_F2R1_FB3_Pos',['../group___peripheral___registers___bits___definition.html#gaca191ad3d0d9a8452f6dd9e8465695e5',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r1_5ffb4_1297',['CAN_F2R1_FB4',['../group___peripheral___registers___bits___definition.html#ga0e52ca421788d68f3edb9a52434374dd',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r1_5ffb4_5fmsk_1298',['CAN_F2R1_FB4_Msk',['../group___peripheral___registers___bits___definition.html#ga7555733c5e81d91c22ef16a2954e58a0',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r1_5ffb4_5fpos_1299',['CAN_F2R1_FB4_Pos',['../group___peripheral___registers___bits___definition.html#gadc3a2fcc279f4d100b4bf0a3e56c027d',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r1_5ffb5_1300',['CAN_F2R1_FB5',['../group___peripheral___registers___bits___definition.html#ga96a97a9711a0a53a7ee18907e95d8887',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r1_5ffb5_5fmsk_1301',['CAN_F2R1_FB5_Msk',['../group___peripheral___registers___bits___definition.html#ga3302502cfe80c87773630dbb3fe8eab1',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r1_5ffb5_5fpos_1302',['CAN_F2R1_FB5_Pos',['../group___peripheral___registers___bits___definition.html#ga2706c0511eea92c7c23717696e2039ef',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r1_5ffb6_1303',['CAN_F2R1_FB6',['../group___peripheral___registers___bits___definition.html#ga6f73f1bd0d3246f27d7a91a620fb3cc7',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r1_5ffb6_5fmsk_1304',['CAN_F2R1_FB6_Msk',['../group___peripheral___registers___bits___definition.html#ga1c22e704c9d4404892df4086290e68ec',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r1_5ffb6_5fpos_1305',['CAN_F2R1_FB6_Pos',['../group___peripheral___registers___bits___definition.html#ga26f556ca64f9a621435b46e87266ceed',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r1_5ffb7_1306',['CAN_F2R1_FB7',['../group___peripheral___registers___bits___definition.html#ga72bf4a6050af614eb1ac85c76feb95cc',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r1_5ffb7_5fmsk_1307',['CAN_F2R1_FB7_Msk',['../group___peripheral___registers___bits___definition.html#ga569ec796b80a5c48de939b628a2368d8',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r1_5ffb7_5fpos_1308',['CAN_F2R1_FB7_Pos',['../group___peripheral___registers___bits___definition.html#ga417d9fb1cd03584958223984f973ae45',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r1_5ffb8_1309',['CAN_F2R1_FB8',['../group___peripheral___registers___bits___definition.html#gad484c083bc2023deda5840facc549908',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r1_5ffb8_5fmsk_1310',['CAN_F2R1_FB8_Msk',['../group___peripheral___registers___bits___definition.html#gacc5dd0d405b5a0e37c5a7b44e3ddb27d',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r1_5ffb8_5fpos_1311',['CAN_F2R1_FB8_Pos',['../group___peripheral___registers___bits___definition.html#ga2ecf568bb243c39cb4b591e10ee4c264',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r1_5ffb9_1312',['CAN_F2R1_FB9',['../group___peripheral___registers___bits___definition.html#ga0d0e05e4824f05e2cf12b3d0a0b7f319',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r1_5ffb9_5fmsk_1313',['CAN_F2R1_FB9_Msk',['../group___peripheral___registers___bits___definition.html#ga6c52c1e2532edd862c9480c22ee72340',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r1_5ffb9_5fpos_1314',['CAN_F2R1_FB9_Pos',['../group___peripheral___registers___bits___definition.html#gadb6429e869387e036a72125c767616a2',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r2_5ffb0_1315',['CAN_F2R2_FB0',['../group___peripheral___registers___bits___definition.html#ga36964e4bf6aa10467b3d95781da56814',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r2_5ffb0_5fmsk_1316',['CAN_F2R2_FB0_Msk',['../group___peripheral___registers___bits___definition.html#gaf4399948716780ec8c4dd96270469843',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r2_5ffb0_5fpos_1317',['CAN_F2R2_FB0_Pos',['../group___peripheral___registers___bits___definition.html#gaf63fb260c0953b77b1c331f22f38ba67',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r2_5ffb1_1318',['CAN_F2R2_FB1',['../group___peripheral___registers___bits___definition.html#ga0d0541eb1a4f8ae0afe429ac0757de6a',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r2_5ffb10_1319',['CAN_F2R2_FB10',['../group___peripheral___registers___bits___definition.html#ga360e02860472400a9000ef2fc8ba7bb1',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r2_5ffb10_5fmsk_1320',['CAN_F2R2_FB10_Msk',['../group___peripheral___registers___bits___definition.html#gaebf3a00b21dc2a665b2e8e7b99cefaae',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r2_5ffb10_5fpos_1321',['CAN_F2R2_FB10_Pos',['../group___peripheral___registers___bits___definition.html#gac5fd8ddf4d48ae6b4b8375791a9fe081',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r2_5ffb11_1322',['CAN_F2R2_FB11',['../group___peripheral___registers___bits___definition.html#ga4c917a5b5e1a010229caaa5b3a41d7a6',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r2_5ffb11_5fmsk_1323',['CAN_F2R2_FB11_Msk',['../group___peripheral___registers___bits___definition.html#gadb77bebe0b062fe55efc6304cf8840b4',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r2_5ffb11_5fpos_1324',['CAN_F2R2_FB11_Pos',['../group___peripheral___registers___bits___definition.html#ga62d108467a53b2dd5992d6bde9ed771e',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r2_5ffb12_1325',['CAN_F2R2_FB12',['../group___peripheral___registers___bits___definition.html#ga0956873246e63b41c0a640bc8d117319',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r2_5ffb12_5fmsk_1326',['CAN_F2R2_FB12_Msk',['../group___peripheral___registers___bits___definition.html#ga04dd0cb91d888b98351e33516a4547e1',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r2_5ffb12_5fpos_1327',['CAN_F2R2_FB12_Pos',['../group___peripheral___registers___bits___definition.html#ga831b9df6d417ca891d10d42826a7412d',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r2_5ffb13_1328',['CAN_F2R2_FB13',['../group___peripheral___registers___bits___definition.html#ga53202218de27d073d577c27427fe0cbe',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r2_5ffb13_5fmsk_1329',['CAN_F2R2_FB13_Msk',['../group___peripheral___registers___bits___definition.html#ga7f6af8fc2890a6b457435f0ab29908e4',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r2_5ffb13_5fpos_1330',['CAN_F2R2_FB13_Pos',['../group___peripheral___registers___bits___definition.html#ga0a22208eb5078a7bfc81c4d9425d3768',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r2_5ffb14_1331',['CAN_F2R2_FB14',['../group___peripheral___registers___bits___definition.html#ga960a1ffd4b153168494d91df69e30742',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r2_5ffb14_5fmsk_1332',['CAN_F2R2_FB14_Msk',['../group___peripheral___registers___bits___definition.html#gac7f01b289ae8ae3eecedd8a29ddc1eb1',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r2_5ffb14_5fpos_1333',['CAN_F2R2_FB14_Pos',['../group___peripheral___registers___bits___definition.html#gafa084d675b30eec4c52eda4e06ef7e79',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r2_5ffb15_1334',['CAN_F2R2_FB15',['../group___peripheral___registers___bits___definition.html#gafc81e9ab9ab926d1ca30c5b6060a126b',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r2_5ffb15_5fmsk_1335',['CAN_F2R2_FB15_Msk',['../group___peripheral___registers___bits___definition.html#ga1c79b4445a4d0eb87b2121d58c73d9bc',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r2_5ffb15_5fpos_1336',['CAN_F2R2_FB15_Pos',['../group___peripheral___registers___bits___definition.html#ga956077f7bdb372a7bf0c608b13c8f7f8',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r2_5ffb16_1337',['CAN_F2R2_FB16',['../group___peripheral___registers___bits___definition.html#gaa5f9a5279398454a3a2493b3e1783f52',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r2_5ffb16_5fmsk_1338',['CAN_F2R2_FB16_Msk',['../group___peripheral___registers___bits___definition.html#ga3ae7788f7206aca6e83ba0cd081af5b2',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r2_5ffb16_5fpos_1339',['CAN_F2R2_FB16_Pos',['../group___peripheral___registers___bits___definition.html#gadcb245f4a5552692ce95229e29c99b1d',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r2_5ffb17_1340',['CAN_F2R2_FB17',['../group___peripheral___registers___bits___definition.html#ga0275ec7527a223a33289118f9e0a2edd',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r2_5ffb17_5fmsk_1341',['CAN_F2R2_FB17_Msk',['../group___peripheral___registers___bits___definition.html#gaa0d302da92dc7ff48bfb3935a739c56f',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r2_5ffb17_5fpos_1342',['CAN_F2R2_FB17_Pos',['../group___peripheral___registers___bits___definition.html#ga3e7149f9b6d387983aa9cfddda59c1ac',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r2_5ffb18_1343',['CAN_F2R2_FB18',['../group___peripheral___registers___bits___definition.html#ga34028a240868ca7dd365ce98e31e84ca',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r2_5ffb18_5fmsk_1344',['CAN_F2R2_FB18_Msk',['../group___peripheral___registers___bits___definition.html#ga7ee8abd5207088cb6f59a3fd5af3b89a',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r2_5ffb18_5fpos_1345',['CAN_F2R2_FB18_Pos',['../group___peripheral___registers___bits___definition.html#ga67d39926ab846913f9cc5a077ab2451a',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r2_5ffb19_1346',['CAN_F2R2_FB19',['../group___peripheral___registers___bits___definition.html#ga807cfa122b6c74d85fdab233dd9ed502',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r2_5ffb19_5fmsk_1347',['CAN_F2R2_FB19_Msk',['../group___peripheral___registers___bits___definition.html#gab6ad53d41a895d341e102901c2e4113b',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r2_5ffb19_5fpos_1348',['CAN_F2R2_FB19_Pos',['../group___peripheral___registers___bits___definition.html#ga711201f0da7b487c7111c4e587f84d12',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r2_5ffb1_5fmsk_1349',['CAN_F2R2_FB1_Msk',['../group___peripheral___registers___bits___definition.html#gad77d91c1c72f554e0e99650a3f47e737',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r2_5ffb1_5fpos_1350',['CAN_F2R2_FB1_Pos',['../group___peripheral___registers___bits___definition.html#gab8f29d00c90b617c2336012358753e59',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r2_5ffb2_1351',['CAN_F2R2_FB2',['../group___peripheral___registers___bits___definition.html#ga14fd5aff8767df509b396190ddf7fa28',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r2_5ffb20_1352',['CAN_F2R2_FB20',['../group___peripheral___registers___bits___definition.html#ga1187f1ab7514c90af34b44eff80858fa',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r2_5ffb20_5fmsk_1353',['CAN_F2R2_FB20_Msk',['../group___peripheral___registers___bits___definition.html#gae6b747f768a440c5e8fe08febc1d0683',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r2_5ffb20_5fpos_1354',['CAN_F2R2_FB20_Pos',['../group___peripheral___registers___bits___definition.html#ga2664848f3b5f6f02d916a85c2995377e',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r2_5ffb21_1355',['CAN_F2R2_FB21',['../group___peripheral___registers___bits___definition.html#gacecb18e779a44989b724901f6c2af84f',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r2_5ffb21_5fmsk_1356',['CAN_F2R2_FB21_Msk',['../group___peripheral___registers___bits___definition.html#gafc046157f775cb1a2c5b2b90aa15d745',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r2_5ffb21_5fpos_1357',['CAN_F2R2_FB21_Pos',['../group___peripheral___registers___bits___definition.html#ga803f8529db84971c2b5c425cf5ece37b',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r2_5ffb22_1358',['CAN_F2R2_FB22',['../group___peripheral___registers___bits___definition.html#ga3f2a6017895d8d139dcbc3d0e6e69e69',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r2_5ffb22_5fmsk_1359',['CAN_F2R2_FB22_Msk',['../group___peripheral___registers___bits___definition.html#ga23fdd1fa55e6729712aad51a2ce62834',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r2_5ffb22_5fpos_1360',['CAN_F2R2_FB22_Pos',['../group___peripheral___registers___bits___definition.html#ga007e6dcd0caab8184192fb9780535e88',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r2_5ffb23_1361',['CAN_F2R2_FB23',['../group___peripheral___registers___bits___definition.html#gaceff2f283cbd4935ec5d45ceaa18efe0',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r2_5ffb23_5fmsk_1362',['CAN_F2R2_FB23_Msk',['../group___peripheral___registers___bits___definition.html#ga4508040a17ba6d514e9c5db40131a196',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r2_5ffb23_5fpos_1363',['CAN_F2R2_FB23_Pos',['../group___peripheral___registers___bits___definition.html#ga5ed215ff7fa7ffdb6fe61431c3634a53',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r2_5ffb24_1364',['CAN_F2R2_FB24',['../group___peripheral___registers___bits___definition.html#ga3086667a209f91ed6d6b496b83111044',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r2_5ffb24_5fmsk_1365',['CAN_F2R2_FB24_Msk',['../group___peripheral___registers___bits___definition.html#gae17fde946459dc3fc90da9e8809d6d05',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r2_5ffb24_5fpos_1366',['CAN_F2R2_FB24_Pos',['../group___peripheral___registers___bits___definition.html#ga838adce88b9370f7a2559bbb2ce268ce',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r2_5ffb25_1367',['CAN_F2R2_FB25',['../group___peripheral___registers___bits___definition.html#ga5c8c7b240bb0dd2a3ec8b6c4c25af7ba',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r2_5ffb25_5fmsk_1368',['CAN_F2R2_FB25_Msk',['../group___peripheral___registers___bits___definition.html#ga03da1089ea38abbe1093471a67a971fa',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r2_5ffb25_5fpos_1369',['CAN_F2R2_FB25_Pos',['../group___peripheral___registers___bits___definition.html#ga93be5f2dee61eb1a67711f9037864725',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r2_5ffb26_1370',['CAN_F2R2_FB26',['../group___peripheral___registers___bits___definition.html#ga51498379a1e3b81a83bf8d164c4f7e5e',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r2_5ffb26_5fmsk_1371',['CAN_F2R2_FB26_Msk',['../group___peripheral___registers___bits___definition.html#gacef46477e39c33367b4cc071c1e3fc69',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r2_5ffb26_5fpos_1372',['CAN_F2R2_FB26_Pos',['../group___peripheral___registers___bits___definition.html#ga3b2487dff59abf0a4aff74d5a8e5bf85',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r2_5ffb27_1373',['CAN_F2R2_FB27',['../group___peripheral___registers___bits___definition.html#gaa1f78e7c530a3ef26d44b9353fa9ee36',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r2_5ffb27_5fmsk_1374',['CAN_F2R2_FB27_Msk',['../group___peripheral___registers___bits___definition.html#ga833458f427d74480b7a400ace687432e',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r2_5ffb27_5fpos_1375',['CAN_F2R2_FB27_Pos',['../group___peripheral___registers___bits___definition.html#ga7470e371f95c91d7222c919e63d3c92f',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r2_5ffb28_1376',['CAN_F2R2_FB28',['../group___peripheral___registers___bits___definition.html#ga7e30d0e50fca346ca8cb427a6c85f9dc',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r2_5ffb28_5fmsk_1377',['CAN_F2R2_FB28_Msk',['../group___peripheral___registers___bits___definition.html#gafc909d367700acef6e2bf8954fcbed1c',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r2_5ffb28_5fpos_1378',['CAN_F2R2_FB28_Pos',['../group___peripheral___registers___bits___definition.html#gab7bc089024482b8555fc44374c3ff5bc',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r2_5ffb29_1379',['CAN_F2R2_FB29',['../group___peripheral___registers___bits___definition.html#ga77586d252cad5a0a866b1d9deb6835ba',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r2_5ffb29_5fmsk_1380',['CAN_F2R2_FB29_Msk',['../group___peripheral___registers___bits___definition.html#gac030b2a517b48686820ece2c433e2f13',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r2_5ffb29_5fpos_1381',['CAN_F2R2_FB29_Pos',['../group___peripheral___registers___bits___definition.html#gae76e0f99ff3d94336ea5da68bcd0761a',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r2_5ffb2_5fmsk_1382',['CAN_F2R2_FB2_Msk',['../group___peripheral___registers___bits___definition.html#ga96dff14e0209cd48bf0c29dc53ede26b',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r2_5ffb2_5fpos_1383',['CAN_F2R2_FB2_Pos',['../group___peripheral___registers___bits___definition.html#ga3ac519efc7774827b8a0acf9c6d84d6e',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r2_5ffb3_1384',['CAN_F2R2_FB3',['../group___peripheral___registers___bits___definition.html#ga7283e2a71983078144fa9a8e5ae563a9',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r2_5ffb30_1385',['CAN_F2R2_FB30',['../group___peripheral___registers___bits___definition.html#ga6a10903e507b35b7425b3ae98a8c6800',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r2_5ffb30_5fmsk_1386',['CAN_F2R2_FB30_Msk',['../group___peripheral___registers___bits___definition.html#ga1fbf050f9c8c01df6dd11938eb663221',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r2_5ffb30_5fpos_1387',['CAN_F2R2_FB30_Pos',['../group___peripheral___registers___bits___definition.html#ga13dcafb2960be76467f3aa3f5e11c9cd',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r2_5ffb31_1388',['CAN_F2R2_FB31',['../group___peripheral___registers___bits___definition.html#gac34bca92730b6f7cd0de8af1a2d0014f',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r2_5ffb31_5fmsk_1389',['CAN_F2R2_FB31_Msk',['../group___peripheral___registers___bits___definition.html#ga38b5f7d56afc77679c64cc8559c9637c',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r2_5ffb31_5fpos_1390',['CAN_F2R2_FB31_Pos',['../group___peripheral___registers___bits___definition.html#ga1e2628938146647cf456f8800cc4c6cc',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r2_5ffb3_5fmsk_1391',['CAN_F2R2_FB3_Msk',['../group___peripheral___registers___bits___definition.html#ga4f3b7ec530ba7d4f3effd0c42ab49ca9',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r2_5ffb3_5fpos_1392',['CAN_F2R2_FB3_Pos',['../group___peripheral___registers___bits___definition.html#gace335e7b5360756df41deae31f2abe97',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r2_5ffb4_1393',['CAN_F2R2_FB4',['../group___peripheral___registers___bits___definition.html#gaeba1324d32b084c477a0ece7b904a4cd',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r2_5ffb4_5fmsk_1394',['CAN_F2R2_FB4_Msk',['../group___peripheral___registers___bits___definition.html#gafbcaf819adc61da902e94fc549c5eca7',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r2_5ffb4_5fpos_1395',['CAN_F2R2_FB4_Pos',['../group___peripheral___registers___bits___definition.html#gac0ff06cee35fcd839c589a9354debd14',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r2_5ffb5_1396',['CAN_F2R2_FB5',['../group___peripheral___registers___bits___definition.html#ga1a367cf9f2f7e604e9f5e30b5ed30779',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r2_5ffb5_5fmsk_1397',['CAN_F2R2_FB5_Msk',['../group___peripheral___registers___bits___definition.html#gafb028302ad008b6326533727d4fb75b0',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r2_5ffb5_5fpos_1398',['CAN_F2R2_FB5_Pos',['../group___peripheral___registers___bits___definition.html#gaff548790426c82595b210472f7962e60',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r2_5ffb6_1399',['CAN_F2R2_FB6',['../group___peripheral___registers___bits___definition.html#ga6b92ac9785e2f7c890130e9b7d792c79',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r2_5ffb6_5fmsk_1400',['CAN_F2R2_FB6_Msk',['../group___peripheral___registers___bits___definition.html#ga8d23fc25f4bfb50a6f590e31e11c4838',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r2_5ffb6_5fpos_1401',['CAN_F2R2_FB6_Pos',['../group___peripheral___registers___bits___definition.html#gab8d334bdd60f7c353f3be0e0f43ab068',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r2_5ffb7_1402',['CAN_F2R2_FB7',['../group___peripheral___registers___bits___definition.html#gac969a33d20353d5cd7fb317f5fa71138',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r2_5ffb7_5fmsk_1403',['CAN_F2R2_FB7_Msk',['../group___peripheral___registers___bits___definition.html#ga42c27ede1b3c0ad55b1d3ceeb774abbd',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r2_5ffb7_5fpos_1404',['CAN_F2R2_FB7_Pos',['../group___peripheral___registers___bits___definition.html#ga7f1f47aa543e3b89fd13f489408ca8a4',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r2_5ffb8_1405',['CAN_F2R2_FB8',['../group___peripheral___registers___bits___definition.html#gafeaac84fa5eec0173c531e9940327f86',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r2_5ffb8_5fmsk_1406',['CAN_F2R2_FB8_Msk',['../group___peripheral___registers___bits___definition.html#gaace122156ecd18b6abea1a5f23e1cfce',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r2_5ffb8_5fpos_1407',['CAN_F2R2_FB8_Pos',['../group___peripheral___registers___bits___definition.html#ga3338bc9837ac1f00d007a2ae6d79f27f',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r2_5ffb9_1408',['CAN_F2R2_FB9',['../group___peripheral___registers___bits___definition.html#ga532413ea309fa031e65397a5b31ac92c',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r2_5ffb9_5fmsk_1409',['CAN_F2R2_FB9_Msk',['../group___peripheral___registers___bits___definition.html#ga95a5442d9fc437bc2acdf878279cf7c6',1,'stm32f407xx_matlab.h']]], - ['can_5ff2r2_5ffb9_5fpos_1410',['CAN_F2R2_FB9_Pos',['../group___peripheral___registers___bits___definition.html#ga7c4389614bb6ca7bd50b0a72d6e6dd90',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r1_5ffb0_1411',['CAN_F3R1_FB0',['../group___peripheral___registers___bits___definition.html#ga6bc065319a9862c1f5ca7326b790ef53',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r1_5ffb0_5fmsk_1412',['CAN_F3R1_FB0_Msk',['../group___peripheral___registers___bits___definition.html#ga1c1d5628f543d31326f122516ae8d36c',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r1_5ffb0_5fpos_1413',['CAN_F3R1_FB0_Pos',['../group___peripheral___registers___bits___definition.html#ga30d5a0c988cb0f7bded01fd1c5bcd9bb',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r1_5ffb1_1414',['CAN_F3R1_FB1',['../group___peripheral___registers___bits___definition.html#ga42e636521c72a20aa8380fe4fe150b91',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r1_5ffb10_1415',['CAN_F3R1_FB10',['../group___peripheral___registers___bits___definition.html#gadcfc2559b456c3af3804a22e0fb5c50d',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r1_5ffb10_5fmsk_1416',['CAN_F3R1_FB10_Msk',['../group___peripheral___registers___bits___definition.html#ga8a3ae8c895b853d340ff7a133870164a',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r1_5ffb10_5fpos_1417',['CAN_F3R1_FB10_Pos',['../group___peripheral___registers___bits___definition.html#gac5bff557fd63b73e4490b972bb5ac946',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r1_5ffb11_1418',['CAN_F3R1_FB11',['../group___peripheral___registers___bits___definition.html#ga7df8031e3a2f661b45fdbde58a26c6b6',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r1_5ffb11_5fmsk_1419',['CAN_F3R1_FB11_Msk',['../group___peripheral___registers___bits___definition.html#ga68222a41a14bb43bc6d2f0fc4dee1e0f',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r1_5ffb11_5fpos_1420',['CAN_F3R1_FB11_Pos',['../group___peripheral___registers___bits___definition.html#gab9f0a4a347f318e110ce2139acb78b13',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r1_5ffb12_1421',['CAN_F3R1_FB12',['../group___peripheral___registers___bits___definition.html#ga6c6baa9ac6a1cdd55c2d51ee40cf8f2d',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r1_5ffb12_5fmsk_1422',['CAN_F3R1_FB12_Msk',['../group___peripheral___registers___bits___definition.html#gaec2bac1777b3ebef8b3a22d22514a4b2',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r1_5ffb12_5fpos_1423',['CAN_F3R1_FB12_Pos',['../group___peripheral___registers___bits___definition.html#gaf2d38f5393492a54b470fa2b985cec67',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r1_5ffb13_1424',['CAN_F3R1_FB13',['../group___peripheral___registers___bits___definition.html#ga95fc8c778ffa6deac5a202985fdd98ae',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r1_5ffb13_5fmsk_1425',['CAN_F3R1_FB13_Msk',['../group___peripheral___registers___bits___definition.html#ga47f4c6942bebdcb179b5092520842e91',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r1_5ffb13_5fpos_1426',['CAN_F3R1_FB13_Pos',['../group___peripheral___registers___bits___definition.html#gafaf1ceb6b25d05652aba0ef3a04caf40',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r1_5ffb14_1427',['CAN_F3R1_FB14',['../group___peripheral___registers___bits___definition.html#ga0c4a4998f2ddc12771da116b1c20d765',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r1_5ffb14_5fmsk_1428',['CAN_F3R1_FB14_Msk',['../group___peripheral___registers___bits___definition.html#gaf3cbf7b6b28dce1e65f4377273b060b7',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r1_5ffb14_5fpos_1429',['CAN_F3R1_FB14_Pos',['../group___peripheral___registers___bits___definition.html#ga2792beb7bfcf3e2ca26e092bb4ed2d50',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r1_5ffb15_1430',['CAN_F3R1_FB15',['../group___peripheral___registers___bits___definition.html#ga5fb6157fc48147e6c74ed348d156bfa1',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r1_5ffb15_5fmsk_1431',['CAN_F3R1_FB15_Msk',['../group___peripheral___registers___bits___definition.html#ga3d5afdf5c983489b0bcd8029a6e1c45a',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r1_5ffb15_5fpos_1432',['CAN_F3R1_FB15_Pos',['../group___peripheral___registers___bits___definition.html#ga7087ca402b574d4cce164525a75942c1',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r1_5ffb16_1433',['CAN_F3R1_FB16',['../group___peripheral___registers___bits___definition.html#gaadcf2a14e752519bf8a90129fb9d42b1',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r1_5ffb16_5fmsk_1434',['CAN_F3R1_FB16_Msk',['../group___peripheral___registers___bits___definition.html#gaadc1997d8f970761e068263b8aa9f439',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r1_5ffb16_5fpos_1435',['CAN_F3R1_FB16_Pos',['../group___peripheral___registers___bits___definition.html#ga69cf5d074fb4b4a823b2f2071b5a391d',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r1_5ffb17_1436',['CAN_F3R1_FB17',['../group___peripheral___registers___bits___definition.html#ga47c5296c991b481548302478df85e477',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r1_5ffb17_5fmsk_1437',['CAN_F3R1_FB17_Msk',['../group___peripheral___registers___bits___definition.html#ga8221248c305454dd5071679742a56383',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r1_5ffb17_5fpos_1438',['CAN_F3R1_FB17_Pos',['../group___peripheral___registers___bits___definition.html#gadccd15d0bba8530373bb5beafd51ccff',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r1_5ffb18_1439',['CAN_F3R1_FB18',['../group___peripheral___registers___bits___definition.html#ga657b8cda94fd736a4831ab4086ae746f',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r1_5ffb18_5fmsk_1440',['CAN_F3R1_FB18_Msk',['../group___peripheral___registers___bits___definition.html#gad84e18a8d220d1dbf071afcbe969b976',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r1_5ffb18_5fpos_1441',['CAN_F3R1_FB18_Pos',['../group___peripheral___registers___bits___definition.html#ga667df86ec3ab1ef7d9a90d3e69a97ef7',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r1_5ffb19_1442',['CAN_F3R1_FB19',['../group___peripheral___registers___bits___definition.html#ga435edc4b2055ac2d1c3ce616a9c1b236',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r1_5ffb19_5fmsk_1443',['CAN_F3R1_FB19_Msk',['../group___peripheral___registers___bits___definition.html#gaa3806303c3cfe2dcee6e3409eb1492b6',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r1_5ffb19_5fpos_1444',['CAN_F3R1_FB19_Pos',['../group___peripheral___registers___bits___definition.html#ga4e23acb5ecf6e18637060239a690c034',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r1_5ffb1_5fmsk_1445',['CAN_F3R1_FB1_Msk',['../group___peripheral___registers___bits___definition.html#gad4654a2f7909715abd47c047c550d2ca',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r1_5ffb1_5fpos_1446',['CAN_F3R1_FB1_Pos',['../group___peripheral___registers___bits___definition.html#ga423e569040031dc2b17a3923d02c7b0a',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r1_5ffb2_1447',['CAN_F3R1_FB2',['../group___peripheral___registers___bits___definition.html#ga217f5b77e4fefb2d1135187ee2b5bbf2',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r1_5ffb20_1448',['CAN_F3R1_FB20',['../group___peripheral___registers___bits___definition.html#gaaa508de7087eb832ecaf353a4b6821ef',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r1_5ffb20_5fmsk_1449',['CAN_F3R1_FB20_Msk',['../group___peripheral___registers___bits___definition.html#ga05e8b9d7e4cdc6856c6ad61d15fae9f2',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r1_5ffb20_5fpos_1450',['CAN_F3R1_FB20_Pos',['../group___peripheral___registers___bits___definition.html#gaf81dbe7a19466ef9c89804d77b695a8a',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r1_5ffb21_1451',['CAN_F3R1_FB21',['../group___peripheral___registers___bits___definition.html#ga643ceb9293665b8307e63ae0e1700d91',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r1_5ffb21_5fmsk_1452',['CAN_F3R1_FB21_Msk',['../group___peripheral___registers___bits___definition.html#gae1c6bf19e9356adcb47a75895b653025',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r1_5ffb21_5fpos_1453',['CAN_F3R1_FB21_Pos',['../group___peripheral___registers___bits___definition.html#ga504f3a0b162d61b85df522610ce39ef7',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r1_5ffb22_1454',['CAN_F3R1_FB22',['../group___peripheral___registers___bits___definition.html#ga91f5887e884fcf423d680798f4e372bb',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r1_5ffb22_5fmsk_1455',['CAN_F3R1_FB22_Msk',['../group___peripheral___registers___bits___definition.html#ga12f9cc55362b508457dae2a22f3577b9',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r1_5ffb22_5fpos_1456',['CAN_F3R1_FB22_Pos',['../group___peripheral___registers___bits___definition.html#ga802dd3b3cb24cf29fef5a437d611f374',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r1_5ffb23_1457',['CAN_F3R1_FB23',['../group___peripheral___registers___bits___definition.html#ga6adc9c7706f39f7c33760fe6b8c5d17e',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r1_5ffb23_5fmsk_1458',['CAN_F3R1_FB23_Msk',['../group___peripheral___registers___bits___definition.html#ga53b384413c96686c5b6d955edf3605e7',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r1_5ffb23_5fpos_1459',['CAN_F3R1_FB23_Pos',['../group___peripheral___registers___bits___definition.html#ga3b4c505b76333edc055ec8185ce9cca3',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r1_5ffb24_1460',['CAN_F3R1_FB24',['../group___peripheral___registers___bits___definition.html#gad7581186f0241f6db9f63a0a0db22919',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r1_5ffb24_5fmsk_1461',['CAN_F3R1_FB24_Msk',['../group___peripheral___registers___bits___definition.html#ga84c095337bdce797f169006a2b79ecda',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r1_5ffb24_5fpos_1462',['CAN_F3R1_FB24_Pos',['../group___peripheral___registers___bits___definition.html#gae72365189f731236a0347f2577b26ad1',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r1_5ffb25_1463',['CAN_F3R1_FB25',['../group___peripheral___registers___bits___definition.html#ga43b4c084e802398ad265ceb69cfd7519',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r1_5ffb25_5fmsk_1464',['CAN_F3R1_FB25_Msk',['../group___peripheral___registers___bits___definition.html#gad411d7ebb23972f68d8d3622a89de73e',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r1_5ffb25_5fpos_1465',['CAN_F3R1_FB25_Pos',['../group___peripheral___registers___bits___definition.html#gaf7eb5954b6b37e1c895c7e5379b9ed89',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r1_5ffb26_1466',['CAN_F3R1_FB26',['../group___peripheral___registers___bits___definition.html#gade732503a8d41e3f1bb338a2a8103bd2',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r1_5ffb26_5fmsk_1467',['CAN_F3R1_FB26_Msk',['../group___peripheral___registers___bits___definition.html#ga56aa4a1d23228828e880810e6d644054',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r1_5ffb26_5fpos_1468',['CAN_F3R1_FB26_Pos',['../group___peripheral___registers___bits___definition.html#gaa963a783c31dfb619f95c5f36fbbbfbb',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r1_5ffb27_1469',['CAN_F3R1_FB27',['../group___peripheral___registers___bits___definition.html#ga7539a7f651425a757a549205544e508c',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r1_5ffb27_5fmsk_1470',['CAN_F3R1_FB27_Msk',['../group___peripheral___registers___bits___definition.html#ga8a14d8e964a880b27705af96225917cb',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r1_5ffb27_5fpos_1471',['CAN_F3R1_FB27_Pos',['../group___peripheral___registers___bits___definition.html#ga402faf6e5640540970f69b796fec57bc',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r1_5ffb28_1472',['CAN_F3R1_FB28',['../group___peripheral___registers___bits___definition.html#ga1ec25e4ba3ebaf53780e2b8da63e4a3b',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r1_5ffb28_5fmsk_1473',['CAN_F3R1_FB28_Msk',['../group___peripheral___registers___bits___definition.html#ga62dea0d389306d34595416ca334c7bf1',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r1_5ffb28_5fpos_1474',['CAN_F3R1_FB28_Pos',['../group___peripheral___registers___bits___definition.html#gac25fde9cd308c5fde521c6c649112109',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r1_5ffb29_1475',['CAN_F3R1_FB29',['../group___peripheral___registers___bits___definition.html#gae8268be8b5477f813c165e851acd41a2',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r1_5ffb29_5fmsk_1476',['CAN_F3R1_FB29_Msk',['../group___peripheral___registers___bits___definition.html#ga04da25e051a24c10b8d59f6a87818fb0',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r1_5ffb29_5fpos_1477',['CAN_F3R1_FB29_Pos',['../group___peripheral___registers___bits___definition.html#gaf98ffdf9966c92a5cbbcb23ad6c36b1a',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r1_5ffb2_5fmsk_1478',['CAN_F3R1_FB2_Msk',['../group___peripheral___registers___bits___definition.html#ga06d554341693c4f1e9cb5ec2d90c74ca',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r1_5ffb2_5fpos_1479',['CAN_F3R1_FB2_Pos',['../group___peripheral___registers___bits___definition.html#ga183cdb0180529bd94bc2dfd3a2169316',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r1_5ffb3_1480',['CAN_F3R1_FB3',['../group___peripheral___registers___bits___definition.html#ga7693dcf6c0011bbeb19e0413a5ce1f56',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r1_5ffb30_1481',['CAN_F3R1_FB30',['../group___peripheral___registers___bits___definition.html#ga494ad7f35d8552b8494379916a987074',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r1_5ffb30_5fmsk_1482',['CAN_F3R1_FB30_Msk',['../group___peripheral___registers___bits___definition.html#gadc9b888a2c0f23588c4f79d7e1545c61',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r1_5ffb30_5fpos_1483',['CAN_F3R1_FB30_Pos',['../group___peripheral___registers___bits___definition.html#ga5a6f8058f778d1ec69794aa937d96337',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r1_5ffb31_1484',['CAN_F3R1_FB31',['../group___peripheral___registers___bits___definition.html#ga15bbe0d2d24dc95e10156c2541feb4c4',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r1_5ffb31_5fmsk_1485',['CAN_F3R1_FB31_Msk',['../group___peripheral___registers___bits___definition.html#gaaf5486013f92f3646e9ac903676b6743',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r1_5ffb31_5fpos_1486',['CAN_F3R1_FB31_Pos',['../group___peripheral___registers___bits___definition.html#gab45325d0fb96d86f848601a582e47a5d',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r1_5ffb3_5fmsk_1487',['CAN_F3R1_FB3_Msk',['../group___peripheral___registers___bits___definition.html#ga496aa97ec5c7995b3a6da8e9b33c660e',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r1_5ffb3_5fpos_1488',['CAN_F3R1_FB3_Pos',['../group___peripheral___registers___bits___definition.html#ga264110432e8f853262985289f403cf69',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r1_5ffb4_1489',['CAN_F3R1_FB4',['../group___peripheral___registers___bits___definition.html#ga0bffde5d3e1e2e75f4facc98903620f7',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r1_5ffb4_5fmsk_1490',['CAN_F3R1_FB4_Msk',['../group___peripheral___registers___bits___definition.html#ga62eb0d7464f228fd13f2d567e66b0225',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r1_5ffb4_5fpos_1491',['CAN_F3R1_FB4_Pos',['../group___peripheral___registers___bits___definition.html#gad686b1dae4008be31598e02f433f4d6c',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r1_5ffb5_1492',['CAN_F3R1_FB5',['../group___peripheral___registers___bits___definition.html#ga30ccdfd3676f314e749cc205ffcfe1cf',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r1_5ffb5_5fmsk_1493',['CAN_F3R1_FB5_Msk',['../group___peripheral___registers___bits___definition.html#ga6e25fcc0e53a3e2d271e06f8985a1e98',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r1_5ffb5_5fpos_1494',['CAN_F3R1_FB5_Pos',['../group___peripheral___registers___bits___definition.html#ga38b58c76fcd660c939b781c7e82a8b81',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r1_5ffb6_1495',['CAN_F3R1_FB6',['../group___peripheral___registers___bits___definition.html#ga2b2aa80397b4961a33b41303aa348ea1',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r1_5ffb6_5fmsk_1496',['CAN_F3R1_FB6_Msk',['../group___peripheral___registers___bits___definition.html#ga1fa5eeffce32825d18dd6ae540691a43',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r1_5ffb6_5fpos_1497',['CAN_F3R1_FB6_Pos',['../group___peripheral___registers___bits___definition.html#ga9c71ff110c18c45c1111ff2ec255da30',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r1_5ffb7_1498',['CAN_F3R1_FB7',['../group___peripheral___registers___bits___definition.html#ga7b7072c9b829c7df660eb2dea05ee8d8',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r1_5ffb7_5fmsk_1499',['CAN_F3R1_FB7_Msk',['../group___peripheral___registers___bits___definition.html#ga8f51e4b529f2c096fb6fec2b6d7df1f5',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r1_5ffb7_5fpos_1500',['CAN_F3R1_FB7_Pos',['../group___peripheral___registers___bits___definition.html#ga2e1076d0bccc07adfcfdd9b10ef70d49',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r1_5ffb8_1501',['CAN_F3R1_FB8',['../group___peripheral___registers___bits___definition.html#gad016208d1aa9008aaba9a887a1e8b6fa',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r1_5ffb8_5fmsk_1502',['CAN_F3R1_FB8_Msk',['../group___peripheral___registers___bits___definition.html#gafa223fb562425adcb7022b2b5e6f0da6',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r1_5ffb8_5fpos_1503',['CAN_F3R1_FB8_Pos',['../group___peripheral___registers___bits___definition.html#ga99ec42fffa4e19dd6841adeb7c581bbe',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r1_5ffb9_1504',['CAN_F3R1_FB9',['../group___peripheral___registers___bits___definition.html#gad4f4f0d2b56860e36f7777ab397e8609',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r1_5ffb9_5fmsk_1505',['CAN_F3R1_FB9_Msk',['../group___peripheral___registers___bits___definition.html#ga900e4c0c595155e852cbc17fda96e9ee',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r1_5ffb9_5fpos_1506',['CAN_F3R1_FB9_Pos',['../group___peripheral___registers___bits___definition.html#ga1a409b79ae2582691f8998c525f259fc',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r2_5ffb0_1507',['CAN_F3R2_FB0',['../group___peripheral___registers___bits___definition.html#ga46730b7e64aa771087b6c9d5deb273e1',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r2_5ffb0_5fmsk_1508',['CAN_F3R2_FB0_Msk',['../group___peripheral___registers___bits___definition.html#gaa00bc043a80895a2364fdb9e51b3c110',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r2_5ffb0_5fpos_1509',['CAN_F3R2_FB0_Pos',['../group___peripheral___registers___bits___definition.html#ga3e56069f9e4901fdf5d593117c00f56c',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r2_5ffb1_1510',['CAN_F3R2_FB1',['../group___peripheral___registers___bits___definition.html#gaeb12b61624912b90382a4ad95281e7f4',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r2_5ffb10_1511',['CAN_F3R2_FB10',['../group___peripheral___registers___bits___definition.html#gabb635843951fb42ffeb776d8564d7e14',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r2_5ffb10_5fmsk_1512',['CAN_F3R2_FB10_Msk',['../group___peripheral___registers___bits___definition.html#gafbdde33568809be7611190d6b1b81012',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r2_5ffb10_5fpos_1513',['CAN_F3R2_FB10_Pos',['../group___peripheral___registers___bits___definition.html#ga4c8ef622ab70278942e2dff25afb0ed6',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r2_5ffb11_1514',['CAN_F3R2_FB11',['../group___peripheral___registers___bits___definition.html#ga5db557239646008004286de15847ced4',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r2_5ffb11_5fmsk_1515',['CAN_F3R2_FB11_Msk',['../group___peripheral___registers___bits___definition.html#gaaed31d50f1d71f70a49a880e2c743663',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r2_5ffb11_5fpos_1516',['CAN_F3R2_FB11_Pos',['../group___peripheral___registers___bits___definition.html#ga6ceab55d83e6190c4b159baffae431a1',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r2_5ffb12_1517',['CAN_F3R2_FB12',['../group___peripheral___registers___bits___definition.html#ga118b2044dae4c93c66aaa4f28c5b695c',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r2_5ffb12_5fmsk_1518',['CAN_F3R2_FB12_Msk',['../group___peripheral___registers___bits___definition.html#ga66fcb0196d04b5e606b1c4a2287a3f36',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r2_5ffb12_5fpos_1519',['CAN_F3R2_FB12_Pos',['../group___peripheral___registers___bits___definition.html#gae836a910f4fa7d303000f82a1eef47ab',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r2_5ffb13_1520',['CAN_F3R2_FB13',['../group___peripheral___registers___bits___definition.html#ga8c041a2b8162a8055a1894d0a0b3d682',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r2_5ffb13_5fmsk_1521',['CAN_F3R2_FB13_Msk',['../group___peripheral___registers___bits___definition.html#gae7c0fc4c6e615f3274c846c5f63319bb',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r2_5ffb13_5fpos_1522',['CAN_F3R2_FB13_Pos',['../group___peripheral___registers___bits___definition.html#gaf8a1b5f346de27041c6dcf3d30239664',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r2_5ffb14_1523',['CAN_F3R2_FB14',['../group___peripheral___registers___bits___definition.html#gafb6e0947fcb7594d12dcbca38d60c9f8',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r2_5ffb14_5fmsk_1524',['CAN_F3R2_FB14_Msk',['../group___peripheral___registers___bits___definition.html#ga7318a2aa45622bb3ff2067b295c89839',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r2_5ffb14_5fpos_1525',['CAN_F3R2_FB14_Pos',['../group___peripheral___registers___bits___definition.html#ga1a4239e4164239d1ec1f6fa7e378f245',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r2_5ffb15_1526',['CAN_F3R2_FB15',['../group___peripheral___registers___bits___definition.html#ga1dae8addc6fa59e824e1a67fc8c91ddd',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r2_5ffb15_5fmsk_1527',['CAN_F3R2_FB15_Msk',['../group___peripheral___registers___bits___definition.html#gacdf5ab40d21a35f3bd2330139043b4c6',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r2_5ffb15_5fpos_1528',['CAN_F3R2_FB15_Pos',['../group___peripheral___registers___bits___definition.html#ga0abb9b1be5c5538b70b95c29f5f8feb0',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r2_5ffb16_1529',['CAN_F3R2_FB16',['../group___peripheral___registers___bits___definition.html#ga992795c5e0b3b8a8c5d4d6e9eceb7366',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r2_5ffb16_5fmsk_1530',['CAN_F3R2_FB16_Msk',['../group___peripheral___registers___bits___definition.html#gae505ba19e3d139a3e51aa661927c2f79',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r2_5ffb16_5fpos_1531',['CAN_F3R2_FB16_Pos',['../group___peripheral___registers___bits___definition.html#gaf3ee39cb4edc55608b96077047dc790a',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r2_5ffb17_1532',['CAN_F3R2_FB17',['../group___peripheral___registers___bits___definition.html#ga1637eff70416eb85d5d2a54e1f5d412e',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r2_5ffb17_5fmsk_1533',['CAN_F3R2_FB17_Msk',['../group___peripheral___registers___bits___definition.html#ga45fcd762f60b60e56fe4bd937ac7950b',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r2_5ffb17_5fpos_1534',['CAN_F3R2_FB17_Pos',['../group___peripheral___registers___bits___definition.html#gabe35a463b0df8233fd2c252d9e476671',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r2_5ffb18_1535',['CAN_F3R2_FB18',['../group___peripheral___registers___bits___definition.html#ga7bbfdfa29b84ea60e67d41f775c6ffc6',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r2_5ffb18_5fmsk_1536',['CAN_F3R2_FB18_Msk',['../group___peripheral___registers___bits___definition.html#ga347cadef74e15229097c45f255cdeb8e',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r2_5ffb18_5fpos_1537',['CAN_F3R2_FB18_Pos',['../group___peripheral___registers___bits___definition.html#gaa713ee3afe34a389483703fe9f8246da',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r2_5ffb19_1538',['CAN_F3R2_FB19',['../group___peripheral___registers___bits___definition.html#ga827747e8cc66e4dcd22498c59e45c776',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r2_5ffb19_5fmsk_1539',['CAN_F3R2_FB19_Msk',['../group___peripheral___registers___bits___definition.html#ga31404c72668cd4b409b16a1335a73dae',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r2_5ffb19_5fpos_1540',['CAN_F3R2_FB19_Pos',['../group___peripheral___registers___bits___definition.html#ga79eb2b7440516e0a76367dc2fa83bad5',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r2_5ffb1_5fmsk_1541',['CAN_F3R2_FB1_Msk',['../group___peripheral___registers___bits___definition.html#gaa9f4626256cd6e806d02f8ddd1abc6d6',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r2_5ffb1_5fpos_1542',['CAN_F3R2_FB1_Pos',['../group___peripheral___registers___bits___definition.html#ga67bcdd4d126db81bcece2a81de89c904',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r2_5ffb2_1543',['CAN_F3R2_FB2',['../group___peripheral___registers___bits___definition.html#ga6621759dddc575c01f5bbaab43d1f04e',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r2_5ffb20_1544',['CAN_F3R2_FB20',['../group___peripheral___registers___bits___definition.html#gabe0bb6919615ec6311e8c39f62bca618',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r2_5ffb20_5fmsk_1545',['CAN_F3R2_FB20_Msk',['../group___peripheral___registers___bits___definition.html#gafd69af5b3822a2a480bb9041a8011074',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r2_5ffb20_5fpos_1546',['CAN_F3R2_FB20_Pos',['../group___peripheral___registers___bits___definition.html#ga464afddcd2bbd06df0bb2ee572a9cfd4',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r2_5ffb21_1547',['CAN_F3R2_FB21',['../group___peripheral___registers___bits___definition.html#ga3c3e4716d3e52ec99451a942dceb59de',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r2_5ffb21_5fmsk_1548',['CAN_F3R2_FB21_Msk',['../group___peripheral___registers___bits___definition.html#gab102b108170e7865f895d7ca6c40f12e',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r2_5ffb21_5fpos_1549',['CAN_F3R2_FB21_Pos',['../group___peripheral___registers___bits___definition.html#ga8770034c4717ac38141892bd84b23079',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r2_5ffb22_1550',['CAN_F3R2_FB22',['../group___peripheral___registers___bits___definition.html#gaffefb44a948d36dcd94248f63aa68d2b',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r2_5ffb22_5fmsk_1551',['CAN_F3R2_FB22_Msk',['../group___peripheral___registers___bits___definition.html#ga22a42411bd3d2c7a7dc3e41bd40777ae',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r2_5ffb22_5fpos_1552',['CAN_F3R2_FB22_Pos',['../group___peripheral___registers___bits___definition.html#ga033a69b00a00cef04f5526c727bad275',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r2_5ffb23_1553',['CAN_F3R2_FB23',['../group___peripheral___registers___bits___definition.html#ga79ce25d44a38f520b4a93384d6f5ac40',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r2_5ffb23_5fmsk_1554',['CAN_F3R2_FB23_Msk',['../group___peripheral___registers___bits___definition.html#gaf5cae3507194258095f48d348f1307b0',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r2_5ffb23_5fpos_1555',['CAN_F3R2_FB23_Pos',['../group___peripheral___registers___bits___definition.html#ga03beb9a7aeb8179ceed1d97083e28bbd',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r2_5ffb24_1556',['CAN_F3R2_FB24',['../group___peripheral___registers___bits___definition.html#ga3fe1ced752dc811f9418181275c8c3fe',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r2_5ffb24_5fmsk_1557',['CAN_F3R2_FB24_Msk',['../group___peripheral___registers___bits___definition.html#ga9218c367ef6f00e60b093f3f23a7a0b9',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r2_5ffb24_5fpos_1558',['CAN_F3R2_FB24_Pos',['../group___peripheral___registers___bits___definition.html#ga7099835a0d2250cc0cbd274f7f4390ff',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r2_5ffb25_1559',['CAN_F3R2_FB25',['../group___peripheral___registers___bits___definition.html#ga9fb2f469246193f6fc9e4ade42192d28',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r2_5ffb25_5fmsk_1560',['CAN_F3R2_FB25_Msk',['../group___peripheral___registers___bits___definition.html#ga3f46cde0b8517ab5b9625a614ea3d922',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r2_5ffb25_5fpos_1561',['CAN_F3R2_FB25_Pos',['../group___peripheral___registers___bits___definition.html#gac02382c65073c2552fc97fae6cf64b23',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r2_5ffb26_1562',['CAN_F3R2_FB26',['../group___peripheral___registers___bits___definition.html#gaae85be7f7d7a9ddb8a60edb30d2a5727',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r2_5ffb26_5fmsk_1563',['CAN_F3R2_FB26_Msk',['../group___peripheral___registers___bits___definition.html#gab13acbfad9a6174945e4b814d2b3e5a8',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r2_5ffb26_5fpos_1564',['CAN_F3R2_FB26_Pos',['../group___peripheral___registers___bits___definition.html#gae5cce1ce749c1341320ab27c5ccaf9c7',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r2_5ffb27_1565',['CAN_F3R2_FB27',['../group___peripheral___registers___bits___definition.html#ga850c21b26100c68b9cb57608c0249543',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r2_5ffb27_5fmsk_1566',['CAN_F3R2_FB27_Msk',['../group___peripheral___registers___bits___definition.html#gaeb6f5115c365c1103bfb0c2e447de450',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r2_5ffb27_5fpos_1567',['CAN_F3R2_FB27_Pos',['../group___peripheral___registers___bits___definition.html#ga8bda0fbf28a49b2b7513f6d6810d9979',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r2_5ffb28_1568',['CAN_F3R2_FB28',['../group___peripheral___registers___bits___definition.html#ga82ec6ad2ad1b6115496adcb3e66fae25',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r2_5ffb28_5fmsk_1569',['CAN_F3R2_FB28_Msk',['../group___peripheral___registers___bits___definition.html#ga969752803fe126111b3cd5149859c94e',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r2_5ffb28_5fpos_1570',['CAN_F3R2_FB28_Pos',['../group___peripheral___registers___bits___definition.html#ga77eba2b30abdf4a2a9b5ecb3f8616519',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r2_5ffb29_1571',['CAN_F3R2_FB29',['../group___peripheral___registers___bits___definition.html#gaf4fa34cc998edfdd1b3db93395ee6500',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r2_5ffb29_5fmsk_1572',['CAN_F3R2_FB29_Msk',['../group___peripheral___registers___bits___definition.html#ga83e06415202aa98552793b9fa28ee9a7',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r2_5ffb29_5fpos_1573',['CAN_F3R2_FB29_Pos',['../group___peripheral___registers___bits___definition.html#ga59cecf28681a17397c201f6ee9dc450f',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r2_5ffb2_5fmsk_1574',['CAN_F3R2_FB2_Msk',['../group___peripheral___registers___bits___definition.html#ga9d2e95083cd9cba8a5e1dea50a2647b5',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r2_5ffb2_5fpos_1575',['CAN_F3R2_FB2_Pos',['../group___peripheral___registers___bits___definition.html#ga2560be72957af6d4f7449908671d8b46',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r2_5ffb3_1576',['CAN_F3R2_FB3',['../group___peripheral___registers___bits___definition.html#ga29d052fc2597171767d8cf5d72388ad5',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r2_5ffb30_1577',['CAN_F3R2_FB30',['../group___peripheral___registers___bits___definition.html#ga7f4fea5ecec28e7f47647067b75cb24e',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r2_5ffb30_5fmsk_1578',['CAN_F3R2_FB30_Msk',['../group___peripheral___registers___bits___definition.html#ga367133e3ee7501aef9513944565cea6f',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r2_5ffb30_5fpos_1579',['CAN_F3R2_FB30_Pos',['../group___peripheral___registers___bits___definition.html#ga0238173e08b65c4ddffb5f300616bbd5',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r2_5ffb31_1580',['CAN_F3R2_FB31',['../group___peripheral___registers___bits___definition.html#ga58a154f4d0cb787f23429b3f7cf70fd6',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r2_5ffb31_5fmsk_1581',['CAN_F3R2_FB31_Msk',['../group___peripheral___registers___bits___definition.html#ga994e84701ba2b7c21cdc7392a46e9d80',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r2_5ffb31_5fpos_1582',['CAN_F3R2_FB31_Pos',['../group___peripheral___registers___bits___definition.html#gacda1d6cbc1ba76b6fbf6b69d5b805969',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r2_5ffb3_5fmsk_1583',['CAN_F3R2_FB3_Msk',['../group___peripheral___registers___bits___definition.html#gaa1586ad1b9e7dc5ea9060b11c91c64df',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r2_5ffb3_5fpos_1584',['CAN_F3R2_FB3_Pos',['../group___peripheral___registers___bits___definition.html#gabda68247678b28226021fdfad9efab7a',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r2_5ffb4_1585',['CAN_F3R2_FB4',['../group___peripheral___registers___bits___definition.html#ga731e9949d77054ba176340652083ad46',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r2_5ffb4_5fmsk_1586',['CAN_F3R2_FB4_Msk',['../group___peripheral___registers___bits___definition.html#ga6e602cc571c125a4b0a37ef41a35944b',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r2_5ffb4_5fpos_1587',['CAN_F3R2_FB4_Pos',['../group___peripheral___registers___bits___definition.html#ga3d8222da6dc5c339fc0b0f189a25cc49',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r2_5ffb5_1588',['CAN_F3R2_FB5',['../group___peripheral___registers___bits___definition.html#ga93c52f51fe9eefe7f0cf094522a592b6',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r2_5ffb5_5fmsk_1589',['CAN_F3R2_FB5_Msk',['../group___peripheral___registers___bits___definition.html#gafb8c785ed06bbd1d49756b36134e7acb',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r2_5ffb5_5fpos_1590',['CAN_F3R2_FB5_Pos',['../group___peripheral___registers___bits___definition.html#ga55736898b14b121dec11e82b5aefe05c',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r2_5ffb6_1591',['CAN_F3R2_FB6',['../group___peripheral___registers___bits___definition.html#gad675c2d3f72d8bc42e0f3088ddbcc3c9',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r2_5ffb6_5fmsk_1592',['CAN_F3R2_FB6_Msk',['../group___peripheral___registers___bits___definition.html#gaaf8497045acac1d2e6704dcefa92d3b0',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r2_5ffb6_5fpos_1593',['CAN_F3R2_FB6_Pos',['../group___peripheral___registers___bits___definition.html#ga11e7b32a226938156cb9f39271523da5',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r2_5ffb7_1594',['CAN_F3R2_FB7',['../group___peripheral___registers___bits___definition.html#ga1734cf6a5a72d403cd043eb704246c85',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r2_5ffb7_5fmsk_1595',['CAN_F3R2_FB7_Msk',['../group___peripheral___registers___bits___definition.html#ga655169f5704760518f05c635259c7177',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r2_5ffb7_5fpos_1596',['CAN_F3R2_FB7_Pos',['../group___peripheral___registers___bits___definition.html#ga6117333279671f33e6cb91c69434711e',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r2_5ffb8_1597',['CAN_F3R2_FB8',['../group___peripheral___registers___bits___definition.html#ga97d82554ce38567e44cd87ed99175928',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r2_5ffb8_5fmsk_1598',['CAN_F3R2_FB8_Msk',['../group___peripheral___registers___bits___definition.html#gafad82eee295a8a2858712b7a8e78b2a0',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r2_5ffb8_5fpos_1599',['CAN_F3R2_FB8_Pos',['../group___peripheral___registers___bits___definition.html#ga927026c4212e401f403b68ed66b2c1c3',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r2_5ffb9_1600',['CAN_F3R2_FB9',['../group___peripheral___registers___bits___definition.html#ga505f85fadba4397e6d9a241bbc9229bc',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r2_5ffb9_5fmsk_1601',['CAN_F3R2_FB9_Msk',['../group___peripheral___registers___bits___definition.html#ga13711889ff55a6b01f7141db5f702c7a',1,'stm32f407xx_matlab.h']]], - ['can_5ff3r2_5ffb9_5fpos_1602',['CAN_F3R2_FB9_Pos',['../group___peripheral___registers___bits___definition.html#ga931d7f76fa1e6a1a49faaf5338829448',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r1_5ffb0_1603',['CAN_F4R1_FB0',['../group___peripheral___registers___bits___definition.html#ga0eb0d4d21c082c8381271ab146431993',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r1_5ffb0_5fmsk_1604',['CAN_F4R1_FB0_Msk',['../group___peripheral___registers___bits___definition.html#ga7988e6a122cc6084ea40df4b66de5f0f',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r1_5ffb0_5fpos_1605',['CAN_F4R1_FB0_Pos',['../group___peripheral___registers___bits___definition.html#ga5573bdc4becbeaab63e285f60bb316c6',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r1_5ffb1_1606',['CAN_F4R1_FB1',['../group___peripheral___registers___bits___definition.html#ga91922c78bf92f051b8e8abbf9cc1f6e9',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r1_5ffb10_1607',['CAN_F4R1_FB10',['../group___peripheral___registers___bits___definition.html#gad06bc748776a78f008895be9e0cc7a1d',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r1_5ffb10_5fmsk_1608',['CAN_F4R1_FB10_Msk',['../group___peripheral___registers___bits___definition.html#ga2d5e8f2c67a528aa361922158ae8eb92',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r1_5ffb10_5fpos_1609',['CAN_F4R1_FB10_Pos',['../group___peripheral___registers___bits___definition.html#ga34153173f76d8b1aacbdd013a733fdd2',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r1_5ffb11_1610',['CAN_F4R1_FB11',['../group___peripheral___registers___bits___definition.html#gaf612f239dcf45bd933136a5c8c5909f9',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r1_5ffb11_5fmsk_1611',['CAN_F4R1_FB11_Msk',['../group___peripheral___registers___bits___definition.html#ga50cb96e2d638c18f5ce23bed3342f39d',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r1_5ffb11_5fpos_1612',['CAN_F4R1_FB11_Pos',['../group___peripheral___registers___bits___definition.html#gac8adba35f6ed518c3d762d8c791cfb85',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r1_5ffb12_1613',['CAN_F4R1_FB12',['../group___peripheral___registers___bits___definition.html#ga6dc611a52acf6dfa1df7ebf867bc7e2f',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r1_5ffb12_5fmsk_1614',['CAN_F4R1_FB12_Msk',['../group___peripheral___registers___bits___definition.html#ga613094782d73b0e3e5272eff72f04d42',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r1_5ffb12_5fpos_1615',['CAN_F4R1_FB12_Pos',['../group___peripheral___registers___bits___definition.html#gafa308445d00347d34a263c82c0b5cc5a',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r1_5ffb13_1616',['CAN_F4R1_FB13',['../group___peripheral___registers___bits___definition.html#ga1736bc2808a37aa82358fe1c36c963a6',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r1_5ffb13_5fmsk_1617',['CAN_F4R1_FB13_Msk',['../group___peripheral___registers___bits___definition.html#ga07c564a28ae0d2958891d26110e4c411',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r1_5ffb13_5fpos_1618',['CAN_F4R1_FB13_Pos',['../group___peripheral___registers___bits___definition.html#gaa6329ecd1b3904d370e9db06936fd0f5',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r1_5ffb14_1619',['CAN_F4R1_FB14',['../group___peripheral___registers___bits___definition.html#ga7d7ec466bbf196a41f6da2a7b506675d',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r1_5ffb14_5fmsk_1620',['CAN_F4R1_FB14_Msk',['../group___peripheral___registers___bits___definition.html#ga3c7d95aae3c918a4c446ecd57f876383',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r1_5ffb14_5fpos_1621',['CAN_F4R1_FB14_Pos',['../group___peripheral___registers___bits___definition.html#ga2e223d1503fe560272d3851eef5850e0',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r1_5ffb15_1622',['CAN_F4R1_FB15',['../group___peripheral___registers___bits___definition.html#gad30ff7e7b0c0f7e56821ecbcd6fcc23c',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r1_5ffb15_5fmsk_1623',['CAN_F4R1_FB15_Msk',['../group___peripheral___registers___bits___definition.html#gaf226c102853cbf2918931586573641bf',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r1_5ffb15_5fpos_1624',['CAN_F4R1_FB15_Pos',['../group___peripheral___registers___bits___definition.html#ga801c05f9333d89c49f62aca3b77152c1',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r1_5ffb16_1625',['CAN_F4R1_FB16',['../group___peripheral___registers___bits___definition.html#ga199bd29b6f3ff56150a9dcd71c8ea13f',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r1_5ffb16_5fmsk_1626',['CAN_F4R1_FB16_Msk',['../group___peripheral___registers___bits___definition.html#ga5885429c36cad6e1bae78efccc6f4c59',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r1_5ffb16_5fpos_1627',['CAN_F4R1_FB16_Pos',['../group___peripheral___registers___bits___definition.html#ga9961594daf8302213f375760ba658031',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r1_5ffb17_1628',['CAN_F4R1_FB17',['../group___peripheral___registers___bits___definition.html#ga893837534cbc7a043fa995de4619e2da',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r1_5ffb17_5fmsk_1629',['CAN_F4R1_FB17_Msk',['../group___peripheral___registers___bits___definition.html#gafa31c54bcaf590c65c626253362949c8',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r1_5ffb17_5fpos_1630',['CAN_F4R1_FB17_Pos',['../group___peripheral___registers___bits___definition.html#ga9b0f6c8b0cd3bedcb4d900b936cb1206',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r1_5ffb18_1631',['CAN_F4R1_FB18',['../group___peripheral___registers___bits___definition.html#ga551e80c41958417cbcf1d0c53e4947a3',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r1_5ffb18_5fmsk_1632',['CAN_F4R1_FB18_Msk',['../group___peripheral___registers___bits___definition.html#ga6d6925aa9feee56fba36b3a4e399c2d8',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r1_5ffb18_5fpos_1633',['CAN_F4R1_FB18_Pos',['../group___peripheral___registers___bits___definition.html#ga618cffe573cd6ccff53130f3beb6bfcb',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r1_5ffb19_1634',['CAN_F4R1_FB19',['../group___peripheral___registers___bits___definition.html#ga80d9a946bd39dae4b0a862cf21f262ed',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r1_5ffb19_5fmsk_1635',['CAN_F4R1_FB19_Msk',['../group___peripheral___registers___bits___definition.html#gaebb1f9e546b4c8bb2bcb3d6e9a1f0949',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r1_5ffb19_5fpos_1636',['CAN_F4R1_FB19_Pos',['../group___peripheral___registers___bits___definition.html#gafe302668b9837570409f0e5dafca0480',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r1_5ffb1_5fmsk_1637',['CAN_F4R1_FB1_Msk',['../group___peripheral___registers___bits___definition.html#gaa88382bdd2a166258413d39fbb436050',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r1_5ffb1_5fpos_1638',['CAN_F4R1_FB1_Pos',['../group___peripheral___registers___bits___definition.html#ga279a547f6c7143c59c912d85973493d1',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r1_5ffb2_1639',['CAN_F4R1_FB2',['../group___peripheral___registers___bits___definition.html#gae56f77f869114e69525353f96004f955',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r1_5ffb20_1640',['CAN_F4R1_FB20',['../group___peripheral___registers___bits___definition.html#ga5646609987ce174cf3b94bb4538172f4',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r1_5ffb20_5fmsk_1641',['CAN_F4R1_FB20_Msk',['../group___peripheral___registers___bits___definition.html#ga119fbe324a31a61a0b5aa989658cf15d',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r1_5ffb20_5fpos_1642',['CAN_F4R1_FB20_Pos',['../group___peripheral___registers___bits___definition.html#ga27b7d0c5f497cf6c9bc7e7fa16eccfd9',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r1_5ffb21_1643',['CAN_F4R1_FB21',['../group___peripheral___registers___bits___definition.html#ga356faa77de97c61e9b5f6b763173a987',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r1_5ffb21_5fmsk_1644',['CAN_F4R1_FB21_Msk',['../group___peripheral___registers___bits___definition.html#gaa57165c0d07048b0024f56e0febdaccd',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r1_5ffb21_5fpos_1645',['CAN_F4R1_FB21_Pos',['../group___peripheral___registers___bits___definition.html#gaec476098d3c0d9c6025f6a2bd35a7f9b',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r1_5ffb22_1646',['CAN_F4R1_FB22',['../group___peripheral___registers___bits___definition.html#gac6b246b3df35cc1db06e8c809137562f',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r1_5ffb22_5fmsk_1647',['CAN_F4R1_FB22_Msk',['../group___peripheral___registers___bits___definition.html#ga91bdc8395c27e8e23092b3f9784b7994',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r1_5ffb22_5fpos_1648',['CAN_F4R1_FB22_Pos',['../group___peripheral___registers___bits___definition.html#gadd5edc6ee520a4896e71f9613676f744',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r1_5ffb23_1649',['CAN_F4R1_FB23',['../group___peripheral___registers___bits___definition.html#ga4882da3ee5be3aed3d5eb46923859674',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r1_5ffb23_5fmsk_1650',['CAN_F4R1_FB23_Msk',['../group___peripheral___registers___bits___definition.html#gac32276ab0a34c8ae46eee73ad1f208d7',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r1_5ffb23_5fpos_1651',['CAN_F4R1_FB23_Pos',['../group___peripheral___registers___bits___definition.html#gabb9a14d13a2ce6fb41594c8ebc9d1a62',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r1_5ffb24_1652',['CAN_F4R1_FB24',['../group___peripheral___registers___bits___definition.html#ga1e178aa8c6f98a866aaae511b9da86c8',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r1_5ffb24_5fmsk_1653',['CAN_F4R1_FB24_Msk',['../group___peripheral___registers___bits___definition.html#ga4e1033412ffe01f17f87d0287af5bd70',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r1_5ffb24_5fpos_1654',['CAN_F4R1_FB24_Pos',['../group___peripheral___registers___bits___definition.html#gae5666249f8189bddecf0c24687fb8e1a',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r1_5ffb25_1655',['CAN_F4R1_FB25',['../group___peripheral___registers___bits___definition.html#ga9a5ca327060530761d71362d39b2d364',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r1_5ffb25_5fmsk_1656',['CAN_F4R1_FB25_Msk',['../group___peripheral___registers___bits___definition.html#ga9d8fcea6cb9dd0d6240208ed38acecdc',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r1_5ffb25_5fpos_1657',['CAN_F4R1_FB25_Pos',['../group___peripheral___registers___bits___definition.html#ga6aedd4cfb249867dc58b58f6f4cbedbb',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r1_5ffb26_1658',['CAN_F4R1_FB26',['../group___peripheral___registers___bits___definition.html#gaeabe4836aed74af4adba72b2c7684a6e',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r1_5ffb26_5fmsk_1659',['CAN_F4R1_FB26_Msk',['../group___peripheral___registers___bits___definition.html#gae2abd932d950db3d7aafbb9af2639a57',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r1_5ffb26_5fpos_1660',['CAN_F4R1_FB26_Pos',['../group___peripheral___registers___bits___definition.html#ga2e69fe695c9a2aa5f7ebf5f8674022bd',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r1_5ffb27_1661',['CAN_F4R1_FB27',['../group___peripheral___registers___bits___definition.html#gaaa8e7d74919e74723f7df71357cc994a',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r1_5ffb27_5fmsk_1662',['CAN_F4R1_FB27_Msk',['../group___peripheral___registers___bits___definition.html#gac34b9b4abc8d9196ce7aab200c99787c',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r1_5ffb27_5fpos_1663',['CAN_F4R1_FB27_Pos',['../group___peripheral___registers___bits___definition.html#gae89e6768b343f3cf2702266b2832ecdc',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r1_5ffb28_1664',['CAN_F4R1_FB28',['../group___peripheral___registers___bits___definition.html#ga6e2b2b9bd5b397e58d57fb379546110b',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r1_5ffb28_5fmsk_1665',['CAN_F4R1_FB28_Msk',['../group___peripheral___registers___bits___definition.html#ga008f59ed84fb846c36803d37e52c09d0',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r1_5ffb28_5fpos_1666',['CAN_F4R1_FB28_Pos',['../group___peripheral___registers___bits___definition.html#ga06a31d8ddb814f830f830b8831821bc4',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r1_5ffb29_1667',['CAN_F4R1_FB29',['../group___peripheral___registers___bits___definition.html#gaeb165ede225dc35a825647e5efcab437',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r1_5ffb29_5fmsk_1668',['CAN_F4R1_FB29_Msk',['../group___peripheral___registers___bits___definition.html#gacd6c2fc9688b65bda0ca6b9e18e0c072',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r1_5ffb29_5fpos_1669',['CAN_F4R1_FB29_Pos',['../group___peripheral___registers___bits___definition.html#ga6fcd8e8ee759e498a068f300ebd67923',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r1_5ffb2_5fmsk_1670',['CAN_F4R1_FB2_Msk',['../group___peripheral___registers___bits___definition.html#gaf6564dfdae0be64785df0d766aa5c149',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r1_5ffb2_5fpos_1671',['CAN_F4R1_FB2_Pos',['../group___peripheral___registers___bits___definition.html#gae735647331c284d403b4917ff3b213ce',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r1_5ffb3_1672',['CAN_F4R1_FB3',['../group___peripheral___registers___bits___definition.html#ga951a8213e55b01ecedcef870c85841e7',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r1_5ffb30_1673',['CAN_F4R1_FB30',['../group___peripheral___registers___bits___definition.html#ga7898b1f422424fd7fc0896b908748e7c',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r1_5ffb30_5fmsk_1674',['CAN_F4R1_FB30_Msk',['../group___peripheral___registers___bits___definition.html#ga2012557ac8ac7ddd510c1dd771062dc2',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r1_5ffb30_5fpos_1675',['CAN_F4R1_FB30_Pos',['../group___peripheral___registers___bits___definition.html#ga905946914d80198f6e0ecc939097904d',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r1_5ffb31_1676',['CAN_F4R1_FB31',['../group___peripheral___registers___bits___definition.html#ga92d7e6a44e87911e9cc14f6bff854fa2',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r1_5ffb31_5fmsk_1677',['CAN_F4R1_FB31_Msk',['../group___peripheral___registers___bits___definition.html#gafe91e1b46bc8af15c5d727b81e51bfdb',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r1_5ffb31_5fpos_1678',['CAN_F4R1_FB31_Pos',['../group___peripheral___registers___bits___definition.html#ga1788952bedbeb5ee6a7aff15180cdd85',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r1_5ffb3_5fmsk_1679',['CAN_F4R1_FB3_Msk',['../group___peripheral___registers___bits___definition.html#ga786fe254e7a86a2ac517ea453f78e120',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r1_5ffb3_5fpos_1680',['CAN_F4R1_FB3_Pos',['../group___peripheral___registers___bits___definition.html#gac731872ee45a7e0569871bfb02c6b6e9',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r1_5ffb4_1681',['CAN_F4R1_FB4',['../group___peripheral___registers___bits___definition.html#ga453f90cdd0b520b7d65e19af3868d4ec',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r1_5ffb4_5fmsk_1682',['CAN_F4R1_FB4_Msk',['../group___peripheral___registers___bits___definition.html#gabd92184f0f30164e14b07a7a4e5208a2',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r1_5ffb4_5fpos_1683',['CAN_F4R1_FB4_Pos',['../group___peripheral___registers___bits___definition.html#ga17f4894ca5438e060ea17fcb6d0d2f9b',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r1_5ffb5_1684',['CAN_F4R1_FB5',['../group___peripheral___registers___bits___definition.html#gace348ba56c1f9676e5b605a6fe0cd52e',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r1_5ffb5_5fmsk_1685',['CAN_F4R1_FB5_Msk',['../group___peripheral___registers___bits___definition.html#ga4a8707829180a6a5ea26822a408facce',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r1_5ffb5_5fpos_1686',['CAN_F4R1_FB5_Pos',['../group___peripheral___registers___bits___definition.html#gaf3eff06bd3294a077a43d55419ecbfbb',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r1_5ffb6_1687',['CAN_F4R1_FB6',['../group___peripheral___registers___bits___definition.html#gae99d36b50a16c38b2006fdba4683ddd9',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r1_5ffb6_5fmsk_1688',['CAN_F4R1_FB6_Msk',['../group___peripheral___registers___bits___definition.html#ga270fa51a92450225b554f19353f38f0e',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r1_5ffb6_5fpos_1689',['CAN_F4R1_FB6_Pos',['../group___peripheral___registers___bits___definition.html#gaaea2a7ac1148da335845a257f1dde33e',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r1_5ffb7_1690',['CAN_F4R1_FB7',['../group___peripheral___registers___bits___definition.html#ga5d61ae4af9acc61476493b640cfb4745',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r1_5ffb7_5fmsk_1691',['CAN_F4R1_FB7_Msk',['../group___peripheral___registers___bits___definition.html#ga474765e4a523545019ad84e02c9af69c',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r1_5ffb7_5fpos_1692',['CAN_F4R1_FB7_Pos',['../group___peripheral___registers___bits___definition.html#gac4c8a70e48e55e45b8d3322a344bfa45',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r1_5ffb8_1693',['CAN_F4R1_FB8',['../group___peripheral___registers___bits___definition.html#ga89ded00ec0b6c0918b019457d6cf43f5',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r1_5ffb8_5fmsk_1694',['CAN_F4R1_FB8_Msk',['../group___peripheral___registers___bits___definition.html#gaa256896c733d9155ab9c60d6f2d58a3b',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r1_5ffb8_5fpos_1695',['CAN_F4R1_FB8_Pos',['../group___peripheral___registers___bits___definition.html#gab4e861543c2dd0e3bfbd34fd6e97927f',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r1_5ffb9_1696',['CAN_F4R1_FB9',['../group___peripheral___registers___bits___definition.html#gac658a1ced873fd9dff54833d8c413536',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r1_5ffb9_5fmsk_1697',['CAN_F4R1_FB9_Msk',['../group___peripheral___registers___bits___definition.html#ga4fdff1d01f74ad524f97bd3a138e6c4d',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r1_5ffb9_5fpos_1698',['CAN_F4R1_FB9_Pos',['../group___peripheral___registers___bits___definition.html#ga8fe495bcc370cfd21bdf1b6e751aa23a',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r2_5ffb0_1699',['CAN_F4R2_FB0',['../group___peripheral___registers___bits___definition.html#ga97250d3eed2504846f39c50dce71c9d0',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r2_5ffb0_5fmsk_1700',['CAN_F4R2_FB0_Msk',['../group___peripheral___registers___bits___definition.html#ga0f9048515e8f37041f6aff9999aff569',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r2_5ffb0_5fpos_1701',['CAN_F4R2_FB0_Pos',['../group___peripheral___registers___bits___definition.html#ga1419ddd39b1b989b7bd57df584d40e93',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r2_5ffb1_1702',['CAN_F4R2_FB1',['../group___peripheral___registers___bits___definition.html#ga145e11678ee6062df5164894ad8f80b1',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r2_5ffb10_1703',['CAN_F4R2_FB10',['../group___peripheral___registers___bits___definition.html#gad8794112fcbb0dca0c7d0316ac8725e8',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r2_5ffb10_5fmsk_1704',['CAN_F4R2_FB10_Msk',['../group___peripheral___registers___bits___definition.html#ga3152ad433d216935b86e5014dd69626e',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r2_5ffb10_5fpos_1705',['CAN_F4R2_FB10_Pos',['../group___peripheral___registers___bits___definition.html#ga30c085eaa270c21b83fb471ae334e59f',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r2_5ffb11_1706',['CAN_F4R2_FB11',['../group___peripheral___registers___bits___definition.html#ga0d22e782a9ca087f99ab9f53b2626aed',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r2_5ffb11_5fmsk_1707',['CAN_F4R2_FB11_Msk',['../group___peripheral___registers___bits___definition.html#gaabc14b1315fea6d9b3948d9f00f07de7',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r2_5ffb11_5fpos_1708',['CAN_F4R2_FB11_Pos',['../group___peripheral___registers___bits___definition.html#ga0a4b0466c13c7c8259301cd2f23cc8de',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r2_5ffb12_1709',['CAN_F4R2_FB12',['../group___peripheral___registers___bits___definition.html#gaaa8d5c2635a62bdfa6e3a5a12b127fc8',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r2_5ffb12_5fmsk_1710',['CAN_F4R2_FB12_Msk',['../group___peripheral___registers___bits___definition.html#gaa8d1eae74bfd099a0512f44a4bd928c9',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r2_5ffb12_5fpos_1711',['CAN_F4R2_FB12_Pos',['../group___peripheral___registers___bits___definition.html#ga6e89e50734d1ff90c8246f14bcb4d83a',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r2_5ffb13_1712',['CAN_F4R2_FB13',['../group___peripheral___registers___bits___definition.html#gad491689799985f0c8f17b270cd8873c4',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r2_5ffb13_5fmsk_1713',['CAN_F4R2_FB13_Msk',['../group___peripheral___registers___bits___definition.html#ga6ad9d3c7bbf0cf276350b00a04b43c37',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r2_5ffb13_5fpos_1714',['CAN_F4R2_FB13_Pos',['../group___peripheral___registers___bits___definition.html#gae7394fbd307de3a0701d41b984658940',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r2_5ffb14_1715',['CAN_F4R2_FB14',['../group___peripheral___registers___bits___definition.html#gab1b80d40d87204de4687735de852f47f',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r2_5ffb14_5fmsk_1716',['CAN_F4R2_FB14_Msk',['../group___peripheral___registers___bits___definition.html#ga31079d3271fc34363eed112cb9a3ed23',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r2_5ffb14_5fpos_1717',['CAN_F4R2_FB14_Pos',['../group___peripheral___registers___bits___definition.html#gaedcf4b945f92674309ef9535166dc473',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r2_5ffb15_1718',['CAN_F4R2_FB15',['../group___peripheral___registers___bits___definition.html#ga0994b341ba8a73b950f01d83d012780d',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r2_5ffb15_5fmsk_1719',['CAN_F4R2_FB15_Msk',['../group___peripheral___registers___bits___definition.html#gacd57e61b87f3e1e9632ad2075732fa5a',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r2_5ffb15_5fpos_1720',['CAN_F4R2_FB15_Pos',['../group___peripheral___registers___bits___definition.html#gadc517c539daa4ed10cd59739b5eac588',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r2_5ffb16_1721',['CAN_F4R2_FB16',['../group___peripheral___registers___bits___definition.html#ga6ae8b77d791ba7403618989a77e62922',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r2_5ffb16_5fmsk_1722',['CAN_F4R2_FB16_Msk',['../group___peripheral___registers___bits___definition.html#gac24f6b4c83f05dfbd05e15c128ad6fbf',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r2_5ffb16_5fpos_1723',['CAN_F4R2_FB16_Pos',['../group___peripheral___registers___bits___definition.html#ga3f7127ca82dc78b93a37e7cf80a5ceb8',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r2_5ffb17_1724',['CAN_F4R2_FB17',['../group___peripheral___registers___bits___definition.html#gabc116988117a7e7fabc722855351d257',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r2_5ffb17_5fmsk_1725',['CAN_F4R2_FB17_Msk',['../group___peripheral___registers___bits___definition.html#ga973be88ab5b27952acbdb24e0b817d78',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r2_5ffb17_5fpos_1726',['CAN_F4R2_FB17_Pos',['../group___peripheral___registers___bits___definition.html#ga0189abc764580a8777fff47521d38303',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r2_5ffb18_1727',['CAN_F4R2_FB18',['../group___peripheral___registers___bits___definition.html#ga07b1fc6ee0dc4cc892d69ed496b59007',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r2_5ffb18_5fmsk_1728',['CAN_F4R2_FB18_Msk',['../group___peripheral___registers___bits___definition.html#gaf85749ab4396b250aac41526571cecf3',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r2_5ffb18_5fpos_1729',['CAN_F4R2_FB18_Pos',['../group___peripheral___registers___bits___definition.html#gaad6a2d9360b2d898f9f52098f68ea290',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r2_5ffb19_1730',['CAN_F4R2_FB19',['../group___peripheral___registers___bits___definition.html#gaa58785812f0d3e73a657426b81f0b78b',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r2_5ffb19_5fmsk_1731',['CAN_F4R2_FB19_Msk',['../group___peripheral___registers___bits___definition.html#gab74002038e0de0bebc00117c89343be6',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r2_5ffb19_5fpos_1732',['CAN_F4R2_FB19_Pos',['../group___peripheral___registers___bits___definition.html#ga610320557b86dc3210d49af3a2ff476b',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r2_5ffb1_5fmsk_1733',['CAN_F4R2_FB1_Msk',['../group___peripheral___registers___bits___definition.html#ga63b07509549c3a1b2559040dd01c9a0e',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r2_5ffb1_5fpos_1734',['CAN_F4R2_FB1_Pos',['../group___peripheral___registers___bits___definition.html#ga960af74ce166416ac55bc7c945adaec8',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r2_5ffb2_1735',['CAN_F4R2_FB2',['../group___peripheral___registers___bits___definition.html#ga9d19193baf5412ec2e38822d062196b8',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r2_5ffb20_1736',['CAN_F4R2_FB20',['../group___peripheral___registers___bits___definition.html#ga363da353073d7ee6421cf171688ef52b',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r2_5ffb20_5fmsk_1737',['CAN_F4R2_FB20_Msk',['../group___peripheral___registers___bits___definition.html#ga814015c75ef6ae829af165ba84aa7692',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r2_5ffb20_5fpos_1738',['CAN_F4R2_FB20_Pos',['../group___peripheral___registers___bits___definition.html#ga338e34091813fe910437c7f4b07f4a15',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r2_5ffb21_1739',['CAN_F4R2_FB21',['../group___peripheral___registers___bits___definition.html#ga4f22695359aa9a1b07763aef44a9a1c4',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r2_5ffb21_5fmsk_1740',['CAN_F4R2_FB21_Msk',['../group___peripheral___registers___bits___definition.html#gac7d83298755e6833a20617ab15f8712d',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r2_5ffb21_5fpos_1741',['CAN_F4R2_FB21_Pos',['../group___peripheral___registers___bits___definition.html#gab3b436d0a50503f95b84d596659fb1a4',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r2_5ffb22_1742',['CAN_F4R2_FB22',['../group___peripheral___registers___bits___definition.html#gac0f8c1ef382225198407474f2b7fa073',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r2_5ffb22_5fmsk_1743',['CAN_F4R2_FB22_Msk',['../group___peripheral___registers___bits___definition.html#gac94ecf7d43f6a018320c3d25bc9b46c2',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r2_5ffb22_5fpos_1744',['CAN_F4R2_FB22_Pos',['../group___peripheral___registers___bits___definition.html#ga2906d67400ef4a87ffb17a1f26d6ae7b',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r2_5ffb23_1745',['CAN_F4R2_FB23',['../group___peripheral___registers___bits___definition.html#ga9476c54044db3182ee789e9df1d1aa19',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r2_5ffb23_5fmsk_1746',['CAN_F4R2_FB23_Msk',['../group___peripheral___registers___bits___definition.html#ga55e657b91bf8789bccd4f52b8f865b2d',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r2_5ffb23_5fpos_1747',['CAN_F4R2_FB23_Pos',['../group___peripheral___registers___bits___definition.html#gaa3b071adef809e00edf9cb9d891d6d44',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r2_5ffb24_1748',['CAN_F4R2_FB24',['../group___peripheral___registers___bits___definition.html#ga73158a3669d2ef96db84e4f196d040bf',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r2_5ffb24_5fmsk_1749',['CAN_F4R2_FB24_Msk',['../group___peripheral___registers___bits___definition.html#ga1696522c0eecd85f864be345e40a29ea',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r2_5ffb24_5fpos_1750',['CAN_F4R2_FB24_Pos',['../group___peripheral___registers___bits___definition.html#ga5da4e3d58f6f15b8c756e0bb38be4cc4',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r2_5ffb25_1751',['CAN_F4R2_FB25',['../group___peripheral___registers___bits___definition.html#ga17d36fcf8e08c76597a7b2c05e831f98',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r2_5ffb25_5fmsk_1752',['CAN_F4R2_FB25_Msk',['../group___peripheral___registers___bits___definition.html#ga92bfc25c457c753a6e6635781a348471',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r2_5ffb25_5fpos_1753',['CAN_F4R2_FB25_Pos',['../group___peripheral___registers___bits___definition.html#ga4f7d61b349c5bca004c6af7eaaee0a05',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r2_5ffb26_1754',['CAN_F4R2_FB26',['../group___peripheral___registers___bits___definition.html#gaa683635426f418ead45032c25e0179ee',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r2_5ffb26_5fmsk_1755',['CAN_F4R2_FB26_Msk',['../group___peripheral___registers___bits___definition.html#ga03b9b82299251b22f45b8ead71dc2675',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r2_5ffb26_5fpos_1756',['CAN_F4R2_FB26_Pos',['../group___peripheral___registers___bits___definition.html#ga6ad5b4c8debdf28b0c25c49b678ea058',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r2_5ffb27_1757',['CAN_F4R2_FB27',['../group___peripheral___registers___bits___definition.html#ga23c77145ea84805a785b49c0a7f31774',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r2_5ffb27_5fmsk_1758',['CAN_F4R2_FB27_Msk',['../group___peripheral___registers___bits___definition.html#gad9295be11108120ae840e8c0f12f0ed5',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r2_5ffb27_5fpos_1759',['CAN_F4R2_FB27_Pos',['../group___peripheral___registers___bits___definition.html#gacaf248d9dc1f65a0536fa18819437aea',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r2_5ffb28_1760',['CAN_F4R2_FB28',['../group___peripheral___registers___bits___definition.html#ga18492e954ec07174a1b140104062f941',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r2_5ffb28_5fmsk_1761',['CAN_F4R2_FB28_Msk',['../group___peripheral___registers___bits___definition.html#gad9d7545d55253cd33e9bc8a186692071',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r2_5ffb28_5fpos_1762',['CAN_F4R2_FB28_Pos',['../group___peripheral___registers___bits___definition.html#ga380250b4976a40ee70fbe9f86f566de1',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r2_5ffb29_1763',['CAN_F4R2_FB29',['../group___peripheral___registers___bits___definition.html#gaaf94626a8450c20e241ad6298660ec23',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r2_5ffb29_5fmsk_1764',['CAN_F4R2_FB29_Msk',['../group___peripheral___registers___bits___definition.html#ga9db3158da58bb55ec0b8e038214bf57c',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r2_5ffb29_5fpos_1765',['CAN_F4R2_FB29_Pos',['../group___peripheral___registers___bits___definition.html#ga98aa4a050c05406a714f4046fc7e7461',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r2_5ffb2_5fmsk_1766',['CAN_F4R2_FB2_Msk',['../group___peripheral___registers___bits___definition.html#ga5f84ea90801ae445733a36c8f10ec608',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r2_5ffb2_5fpos_1767',['CAN_F4R2_FB2_Pos',['../group___peripheral___registers___bits___definition.html#ga6b9fe6bf1b80f4cc053b9e9f8bddb224',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r2_5ffb3_1768',['CAN_F4R2_FB3',['../group___peripheral___registers___bits___definition.html#ga94b8b1428b640932aced6446f8b41f83',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r2_5ffb30_1769',['CAN_F4R2_FB30',['../group___peripheral___registers___bits___definition.html#ga4d7da9aa234705aff3ddc9845b1589d4',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r2_5ffb30_5fmsk_1770',['CAN_F4R2_FB30_Msk',['../group___peripheral___registers___bits___definition.html#ga172377c09e98ed68359ffe7bb49f556c',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r2_5ffb30_5fpos_1771',['CAN_F4R2_FB30_Pos',['../group___peripheral___registers___bits___definition.html#ga1c597a7985c16b24ef4cca5c0a14e60b',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r2_5ffb31_1772',['CAN_F4R2_FB31',['../group___peripheral___registers___bits___definition.html#ga70293ff8a71e353d84a3da134eb427d9',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r2_5ffb31_5fmsk_1773',['CAN_F4R2_FB31_Msk',['../group___peripheral___registers___bits___definition.html#ga1a9da9f03b531cb1019a2a401e9177d6',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r2_5ffb31_5fpos_1774',['CAN_F4R2_FB31_Pos',['../group___peripheral___registers___bits___definition.html#ga43fc86c148a9c62cf94e0c4b1827b4ad',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r2_5ffb3_5fmsk_1775',['CAN_F4R2_FB3_Msk',['../group___peripheral___registers___bits___definition.html#ga4c4fe680c0484c7757d15d939a50e8b1',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r2_5ffb3_5fpos_1776',['CAN_F4R2_FB3_Pos',['../group___peripheral___registers___bits___definition.html#ga81bfbead828bc1a65eee77e210a82107',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r2_5ffb4_1777',['CAN_F4R2_FB4',['../group___peripheral___registers___bits___definition.html#ga93164ec00412eb5eed168e8a30557f25',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r2_5ffb4_5fmsk_1778',['CAN_F4R2_FB4_Msk',['../group___peripheral___registers___bits___definition.html#ga91056080450f8e5f68b3120ed7b609fb',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r2_5ffb4_5fpos_1779',['CAN_F4R2_FB4_Pos',['../group___peripheral___registers___bits___definition.html#ga84bb4ceedefb72e55d9b84543e1e7996',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r2_5ffb5_1780',['CAN_F4R2_FB5',['../group___peripheral___registers___bits___definition.html#ga04e44c5a14e44c20f3b81044a915db13',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r2_5ffb5_5fmsk_1781',['CAN_F4R2_FB5_Msk',['../group___peripheral___registers___bits___definition.html#ga96484b04cb3e058e3f70b722713990dc',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r2_5ffb5_5fpos_1782',['CAN_F4R2_FB5_Pos',['../group___peripheral___registers___bits___definition.html#ga74b468294e8df41868bf3c06bdf481bd',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r2_5ffb6_1783',['CAN_F4R2_FB6',['../group___peripheral___registers___bits___definition.html#ga37e57dec99c33f462a2dbb6273df2f57',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r2_5ffb6_5fmsk_1784',['CAN_F4R2_FB6_Msk',['../group___peripheral___registers___bits___definition.html#gacde7359de773b8b427dddca91f99a3c2',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r2_5ffb6_5fpos_1785',['CAN_F4R2_FB6_Pos',['../group___peripheral___registers___bits___definition.html#gad305c1f3555c0dc3ccdf8da5bc775504',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r2_5ffb7_1786',['CAN_F4R2_FB7',['../group___peripheral___registers___bits___definition.html#gaf6c7d3ec0375e356192583142f7fccca',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r2_5ffb7_5fmsk_1787',['CAN_F4R2_FB7_Msk',['../group___peripheral___registers___bits___definition.html#ga87bfab19292dba8c2e7c6f6d366f1490',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r2_5ffb7_5fpos_1788',['CAN_F4R2_FB7_Pos',['../group___peripheral___registers___bits___definition.html#ga74a2c4a85e2ced48f8e8c14e28e8a527',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r2_5ffb8_1789',['CAN_F4R2_FB8',['../group___peripheral___registers___bits___definition.html#gad33f7d788aea161826a86bc2c5567450',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r2_5ffb8_5fmsk_1790',['CAN_F4R2_FB8_Msk',['../group___peripheral___registers___bits___definition.html#gad82667269e283535191eb3439f4ad6a2',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r2_5ffb8_5fpos_1791',['CAN_F4R2_FB8_Pos',['../group___peripheral___registers___bits___definition.html#gaf0e0dd86f16cceefbb63044d48a7f4ae',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r2_5ffb9_1792',['CAN_F4R2_FB9',['../group___peripheral___registers___bits___definition.html#gaab998448b0bd20ff6384c26ad9e6baaf',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r2_5ffb9_5fmsk_1793',['CAN_F4R2_FB9_Msk',['../group___peripheral___registers___bits___definition.html#gae060ee50f1193b9e8a2b2ad84789eed7',1,'stm32f407xx_matlab.h']]], - ['can_5ff4r2_5ffb9_5fpos_1794',['CAN_F4R2_FB9_Pos',['../group___peripheral___registers___bits___definition.html#gaad6bc30c3c453102c6ff321a9b74ff94',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r1_5ffb0_1795',['CAN_F5R1_FB0',['../group___peripheral___registers___bits___definition.html#ga5cdf98e317662e286ad2a3344ee516df',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r1_5ffb0_5fmsk_1796',['CAN_F5R1_FB0_Msk',['../group___peripheral___registers___bits___definition.html#ga18f8312b10016a8ad987ceaa48f7a67f',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r1_5ffb0_5fpos_1797',['CAN_F5R1_FB0_Pos',['../group___peripheral___registers___bits___definition.html#ga6d79dff94ff5fac00e5f6a357e44f85e',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r1_5ffb1_1798',['CAN_F5R1_FB1',['../group___peripheral___registers___bits___definition.html#gaac814c424ed2ccc11645da6e62f3fb81',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r1_5ffb10_1799',['CAN_F5R1_FB10',['../group___peripheral___registers___bits___definition.html#gae7de15e73395473569a447023dae53c4',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r1_5ffb10_5fmsk_1800',['CAN_F5R1_FB10_Msk',['../group___peripheral___registers___bits___definition.html#ga1eba02afe3b8e8f8eebaa38b8499604c',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r1_5ffb10_5fpos_1801',['CAN_F5R1_FB10_Pos',['../group___peripheral___registers___bits___definition.html#ga0d808208c09dd6604510d037d65d804a',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r1_5ffb11_1802',['CAN_F5R1_FB11',['../group___peripheral___registers___bits___definition.html#ga39b60e0befdf681694bc4123b4b7f7bd',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r1_5ffb11_5fmsk_1803',['CAN_F5R1_FB11_Msk',['../group___peripheral___registers___bits___definition.html#gae735eeb78cc75daa1870ea4d2141e40e',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r1_5ffb11_5fpos_1804',['CAN_F5R1_FB11_Pos',['../group___peripheral___registers___bits___definition.html#ga8551f14a24c6f6dabb131b9e817a013e',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r1_5ffb12_1805',['CAN_F5R1_FB12',['../group___peripheral___registers___bits___definition.html#ga0bc4598d0d603c802b7140f967d84e5c',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r1_5ffb12_5fmsk_1806',['CAN_F5R1_FB12_Msk',['../group___peripheral___registers___bits___definition.html#gafa57169fb0310c42945b03d791c2f54b',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r1_5ffb12_5fpos_1807',['CAN_F5R1_FB12_Pos',['../group___peripheral___registers___bits___definition.html#ga4c27662a1518dfbd5d0217709864fc8c',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r1_5ffb13_1808',['CAN_F5R1_FB13',['../group___peripheral___registers___bits___definition.html#gac8b4439ac4bc79ff74d21060ff533b12',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r1_5ffb13_5fmsk_1809',['CAN_F5R1_FB13_Msk',['../group___peripheral___registers___bits___definition.html#ga65f520a74c377435d6bbbaf002bd72bf',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r1_5ffb13_5fpos_1810',['CAN_F5R1_FB13_Pos',['../group___peripheral___registers___bits___definition.html#gab7b7acc6d79a2decd37c40676d6a2aa7',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r1_5ffb14_1811',['CAN_F5R1_FB14',['../group___peripheral___registers___bits___definition.html#ga0d117ee64d9c1673f22f12f24bd481a4',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r1_5ffb14_5fmsk_1812',['CAN_F5R1_FB14_Msk',['../group___peripheral___registers___bits___definition.html#ga35a677ded1b04b0ba090b33e4558f658',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r1_5ffb14_5fpos_1813',['CAN_F5R1_FB14_Pos',['../group___peripheral___registers___bits___definition.html#ga37ae18d19c8de2e1d7700aa436fbf0bb',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r1_5ffb15_1814',['CAN_F5R1_FB15',['../group___peripheral___registers___bits___definition.html#gaf761c448bf29c4d93f4c2a75981fa049',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r1_5ffb15_5fmsk_1815',['CAN_F5R1_FB15_Msk',['../group___peripheral___registers___bits___definition.html#gacfe4d49efd13e228ed872dbe7f8b5a6c',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r1_5ffb15_5fpos_1816',['CAN_F5R1_FB15_Pos',['../group___peripheral___registers___bits___definition.html#ga5fb993ec1c88ae403c53a086db275ac2',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r1_5ffb16_1817',['CAN_F5R1_FB16',['../group___peripheral___registers___bits___definition.html#ga87543e5b7c48580ca9925402ab6ca5a7',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r1_5ffb16_5fmsk_1818',['CAN_F5R1_FB16_Msk',['../group___peripheral___registers___bits___definition.html#ga6533312fc17838e6d13acb30b3920cb6',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r1_5ffb16_5fpos_1819',['CAN_F5R1_FB16_Pos',['../group___peripheral___registers___bits___definition.html#ga092e685d17984f38bb1a88432ffc54ee',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r1_5ffb17_1820',['CAN_F5R1_FB17',['../group___peripheral___registers___bits___definition.html#ga9b9c39ec4649cd68a540c88c3c64d506',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r1_5ffb17_5fmsk_1821',['CAN_F5R1_FB17_Msk',['../group___peripheral___registers___bits___definition.html#gac6f582e0d54bfd7467f6feed9834672a',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r1_5ffb17_5fpos_1822',['CAN_F5R1_FB17_Pos',['../group___peripheral___registers___bits___definition.html#gac82d98dee909d969dc96f564795027e2',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r1_5ffb18_1823',['CAN_F5R1_FB18',['../group___peripheral___registers___bits___definition.html#ga4992301536d388de215273769708b843',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r1_5ffb18_5fmsk_1824',['CAN_F5R1_FB18_Msk',['../group___peripheral___registers___bits___definition.html#ga241cc69a215db80ad1e1028462f05400',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r1_5ffb18_5fpos_1825',['CAN_F5R1_FB18_Pos',['../group___peripheral___registers___bits___definition.html#ga52662c9e857187de4de1d65d6951bc7a',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r1_5ffb19_1826',['CAN_F5R1_FB19',['../group___peripheral___registers___bits___definition.html#gab21c0b793d7aff03497a95d5c6528ab2',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r1_5ffb19_5fmsk_1827',['CAN_F5R1_FB19_Msk',['../group___peripheral___registers___bits___definition.html#ga1ce1dc2e2a4b715e83aeee7419bb9640',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r1_5ffb19_5fpos_1828',['CAN_F5R1_FB19_Pos',['../group___peripheral___registers___bits___definition.html#ga3c0a5a14d7c4b76f8e6682dd9ef5956f',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r1_5ffb1_5fmsk_1829',['CAN_F5R1_FB1_Msk',['../group___peripheral___registers___bits___definition.html#ga4421f59236d1bd77fadc2e093c988466',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r1_5ffb1_5fpos_1830',['CAN_F5R1_FB1_Pos',['../group___peripheral___registers___bits___definition.html#ga0a8d5c8f4366ceabcfe2f90c570bb475',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r1_5ffb2_1831',['CAN_F5R1_FB2',['../group___peripheral___registers___bits___definition.html#ga4b0af1936dd43bd319614e3298fd28d1',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r1_5ffb20_1832',['CAN_F5R1_FB20',['../group___peripheral___registers___bits___definition.html#gaf1c4c5d06a9da5f853aaede3470b07f4',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r1_5ffb20_5fmsk_1833',['CAN_F5R1_FB20_Msk',['../group___peripheral___registers___bits___definition.html#gaf0c7bd885ecb532509cd74d87eef62dc',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r1_5ffb20_5fpos_1834',['CAN_F5R1_FB20_Pos',['../group___peripheral___registers___bits___definition.html#gab743a0f6dd5ac3c4bac9a036b29081ef',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r1_5ffb21_1835',['CAN_F5R1_FB21',['../group___peripheral___registers___bits___definition.html#ga91214f1f7dbb4b75b0c425624640fd76',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r1_5ffb21_5fmsk_1836',['CAN_F5R1_FB21_Msk',['../group___peripheral___registers___bits___definition.html#ga481485aaa4f39fcdbc5e687452e08cab',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r1_5ffb21_5fpos_1837',['CAN_F5R1_FB21_Pos',['../group___peripheral___registers___bits___definition.html#gafe48131ff33f7f9fbc7714c3d8c7bfeb',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r1_5ffb22_1838',['CAN_F5R1_FB22',['../group___peripheral___registers___bits___definition.html#ga1b24151a68c59fe0f3aa15e498fdc739',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r1_5ffb22_5fmsk_1839',['CAN_F5R1_FB22_Msk',['../group___peripheral___registers___bits___definition.html#ga4629b22e7deeac3e00278086311c7494',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r1_5ffb22_5fpos_1840',['CAN_F5R1_FB22_Pos',['../group___peripheral___registers___bits___definition.html#gaa43bab79ebaba0ef928bdd3a1e63402e',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r1_5ffb23_1841',['CAN_F5R1_FB23',['../group___peripheral___registers___bits___definition.html#gadea89ef2e5c3dafae174b671c8e083d2',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r1_5ffb23_5fmsk_1842',['CAN_F5R1_FB23_Msk',['../group___peripheral___registers___bits___definition.html#ga9a285e060706ab40c834d30f23584f21',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r1_5ffb23_5fpos_1843',['CAN_F5R1_FB23_Pos',['../group___peripheral___registers___bits___definition.html#ga805d068ed5f42588a3cd264fdeaed117',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r1_5ffb24_1844',['CAN_F5R1_FB24',['../group___peripheral___registers___bits___definition.html#ga2acccf9ab5708116cd888f2d65da54cc',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r1_5ffb24_5fmsk_1845',['CAN_F5R1_FB24_Msk',['../group___peripheral___registers___bits___definition.html#gaafb36d512d79bbf393fd07152d0128b3',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r1_5ffb24_5fpos_1846',['CAN_F5R1_FB24_Pos',['../group___peripheral___registers___bits___definition.html#ga11e981a2d5ffc5c12b41ee861e7bf776',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r1_5ffb25_1847',['CAN_F5R1_FB25',['../group___peripheral___registers___bits___definition.html#ga3c0b9425117a2409b61032a9c746c2b5',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r1_5ffb25_5fmsk_1848',['CAN_F5R1_FB25_Msk',['../group___peripheral___registers___bits___definition.html#gaad908c2a3a6d777350aa5a7c926523d4',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r1_5ffb25_5fpos_1849',['CAN_F5R1_FB25_Pos',['../group___peripheral___registers___bits___definition.html#ga37c511b19288ec9ba0732c9aff018656',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r1_5ffb26_1850',['CAN_F5R1_FB26',['../group___peripheral___registers___bits___definition.html#ga0a0d31d96e75ea32299e78845f584632',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r1_5ffb26_5fmsk_1851',['CAN_F5R1_FB26_Msk',['../group___peripheral___registers___bits___definition.html#gab9d0db33c0e7a81c01f442cd914348b7',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r1_5ffb26_5fpos_1852',['CAN_F5R1_FB26_Pos',['../group___peripheral___registers___bits___definition.html#gac24657fe7c1ff00ab6b3a5750ba99bd7',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r1_5ffb27_1853',['CAN_F5R1_FB27',['../group___peripheral___registers___bits___definition.html#gade5db4ad8b19580b895356fff66bb6be',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r1_5ffb27_5fmsk_1854',['CAN_F5R1_FB27_Msk',['../group___peripheral___registers___bits___definition.html#gaffa42eeb73609e01712771d123cf5d9b',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r1_5ffb27_5fpos_1855',['CAN_F5R1_FB27_Pos',['../group___peripheral___registers___bits___definition.html#ga840bed18d4fe71ed9e31e9df74daa351',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r1_5ffb28_1856',['CAN_F5R1_FB28',['../group___peripheral___registers___bits___definition.html#ga4acec834c3eaf55af5e745d6988ddc1e',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r1_5ffb28_5fmsk_1857',['CAN_F5R1_FB28_Msk',['../group___peripheral___registers___bits___definition.html#gaa88a15489fa10cf7d251f7faa5955ba5',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r1_5ffb28_5fpos_1858',['CAN_F5R1_FB28_Pos',['../group___peripheral___registers___bits___definition.html#ga47b688950a4a528471aa72a2fb4ee35b',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r1_5ffb29_1859',['CAN_F5R1_FB29',['../group___peripheral___registers___bits___definition.html#ga923a0086ada8e09a9202338b588f27d1',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r1_5ffb29_5fmsk_1860',['CAN_F5R1_FB29_Msk',['../group___peripheral___registers___bits___definition.html#ga8c619cf4d0662ee07d2621300d0a22e0',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r1_5ffb29_5fpos_1861',['CAN_F5R1_FB29_Pos',['../group___peripheral___registers___bits___definition.html#gabd871efe11f26d251caa7bd258791e5b',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r1_5ffb2_5fmsk_1862',['CAN_F5R1_FB2_Msk',['../group___peripheral___registers___bits___definition.html#ga39beb5641b129903d6d43a152b9b1fc2',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r1_5ffb2_5fpos_1863',['CAN_F5R1_FB2_Pos',['../group___peripheral___registers___bits___definition.html#ga95b23df31b5f7c3556c2702e20c923d6',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r1_5ffb3_1864',['CAN_F5R1_FB3',['../group___peripheral___registers___bits___definition.html#ga013f84e3f3f0e148d3a9a071ccbf6738',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r1_5ffb30_1865',['CAN_F5R1_FB30',['../group___peripheral___registers___bits___definition.html#ga840d2b3f751753e9d21b2e23506e6995',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r1_5ffb30_5fmsk_1866',['CAN_F5R1_FB30_Msk',['../group___peripheral___registers___bits___definition.html#gad45b2c10d0637cb1279cfdaccd186e11',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r1_5ffb30_5fpos_1867',['CAN_F5R1_FB30_Pos',['../group___peripheral___registers___bits___definition.html#gaa9f1a63c02db020d08a6337a5c35c72c',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r1_5ffb31_1868',['CAN_F5R1_FB31',['../group___peripheral___registers___bits___definition.html#gac8d28066798958e5730a95353690bcd0',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r1_5ffb31_5fmsk_1869',['CAN_F5R1_FB31_Msk',['../group___peripheral___registers___bits___definition.html#ga3cca1e8863cc27c3c8afb9d7cee55fe5',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r1_5ffb31_5fpos_1870',['CAN_F5R1_FB31_Pos',['../group___peripheral___registers___bits___definition.html#ga83ac5fc7a98ea52047846b17abbf45f6',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r1_5ffb3_5fmsk_1871',['CAN_F5R1_FB3_Msk',['../group___peripheral___registers___bits___definition.html#ga8c30456c58159fc9c8b5fc705a897c4b',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r1_5ffb3_5fpos_1872',['CAN_F5R1_FB3_Pos',['../group___peripheral___registers___bits___definition.html#gabca05592268e423c5ebe595aa0b66bab',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r1_5ffb4_1873',['CAN_F5R1_FB4',['../group___peripheral___registers___bits___definition.html#ga7cfc330921811d76ed6476d6935e84e7',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r1_5ffb4_5fmsk_1874',['CAN_F5R1_FB4_Msk',['../group___peripheral___registers___bits___definition.html#gaecdbb3ad483c253075f585fb453e6fb8',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r1_5ffb4_5fpos_1875',['CAN_F5R1_FB4_Pos',['../group___peripheral___registers___bits___definition.html#ga3c9a7e1161697ffdc810058033c3c915',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r1_5ffb5_1876',['CAN_F5R1_FB5',['../group___peripheral___registers___bits___definition.html#gaf9aebaa8e61198240c1564ce73acb1d2',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r1_5ffb5_5fmsk_1877',['CAN_F5R1_FB5_Msk',['../group___peripheral___registers___bits___definition.html#gafa323c7e6521417879450a4d5996e256',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r1_5ffb5_5fpos_1878',['CAN_F5R1_FB5_Pos',['../group___peripheral___registers___bits___definition.html#ga7703402af1cdf92f4711ced3fc67c1ca',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r1_5ffb6_1879',['CAN_F5R1_FB6',['../group___peripheral___registers___bits___definition.html#gadea331fb6273fda80a8f5a3dc8eaf6f4',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r1_5ffb6_5fmsk_1880',['CAN_F5R1_FB6_Msk',['../group___peripheral___registers___bits___definition.html#gaa7e09b9fe8aeb61f4253d15d6bd808f0',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r1_5ffb6_5fpos_1881',['CAN_F5R1_FB6_Pos',['../group___peripheral___registers___bits___definition.html#ga256f07a9ee561dfc60a6a3f75d9802e9',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r1_5ffb7_1882',['CAN_F5R1_FB7',['../group___peripheral___registers___bits___definition.html#gafc7dfaacfba6a42a17b16281f690f952',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r1_5ffb7_5fmsk_1883',['CAN_F5R1_FB7_Msk',['../group___peripheral___registers___bits___definition.html#gaa8ddbee4662088695a19791d9754f060',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r1_5ffb7_5fpos_1884',['CAN_F5R1_FB7_Pos',['../group___peripheral___registers___bits___definition.html#ga6f5bf9e5ed786525dbe37eda02710a47',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r1_5ffb8_1885',['CAN_F5R1_FB8',['../group___peripheral___registers___bits___definition.html#gaba0938e0f55773406fd59c2a0bd7c46e',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r1_5ffb8_5fmsk_1886',['CAN_F5R1_FB8_Msk',['../group___peripheral___registers___bits___definition.html#ga3b80299e85591ee7bb2669dfbd7beced',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r1_5ffb8_5fpos_1887',['CAN_F5R1_FB8_Pos',['../group___peripheral___registers___bits___definition.html#ga4d5f9ec2683178e836dabd60294ed4b5',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r1_5ffb9_1888',['CAN_F5R1_FB9',['../group___peripheral___registers___bits___definition.html#ga9715c4445159d0068172309092e574e3',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r1_5ffb9_5fmsk_1889',['CAN_F5R1_FB9_Msk',['../group___peripheral___registers___bits___definition.html#gad909d1a8817b8daf42ad0ebd18551ae8',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r1_5ffb9_5fpos_1890',['CAN_F5R1_FB9_Pos',['../group___peripheral___registers___bits___definition.html#gaefafeaebf2f2d7db4ec1c34ab58b7d0d',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r2_5ffb0_1891',['CAN_F5R2_FB0',['../group___peripheral___registers___bits___definition.html#ga17b264aaa84a3c6ab5a35014eb5dfb09',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r2_5ffb0_5fmsk_1892',['CAN_F5R2_FB0_Msk',['../group___peripheral___registers___bits___definition.html#gab01f1756425341377c80a011da4cfcb1',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r2_5ffb0_5fpos_1893',['CAN_F5R2_FB0_Pos',['../group___peripheral___registers___bits___definition.html#ga31ac96e599e5acbc734ad3ae742ba942',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r2_5ffb1_1894',['CAN_F5R2_FB1',['../group___peripheral___registers___bits___definition.html#gaa871f5bc692996efc8c1bad1d08b43c5',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r2_5ffb10_1895',['CAN_F5R2_FB10',['../group___peripheral___registers___bits___definition.html#ga392844657c800d2e16e7916ed5fb9891',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r2_5ffb10_5fmsk_1896',['CAN_F5R2_FB10_Msk',['../group___peripheral___registers___bits___definition.html#ga860f7fadc560b00fe1878226c9a847be',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r2_5ffb10_5fpos_1897',['CAN_F5R2_FB10_Pos',['../group___peripheral___registers___bits___definition.html#gaef3f52dc2809f93b4bc777b1ef062556',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r2_5ffb11_1898',['CAN_F5R2_FB11',['../group___peripheral___registers___bits___definition.html#gabb35a3bbc447c46929643115490e250d',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r2_5ffb11_5fmsk_1899',['CAN_F5R2_FB11_Msk',['../group___peripheral___registers___bits___definition.html#gab3cf1650e026cc5bb83c111dc8e9ce5e',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r2_5ffb11_5fpos_1900',['CAN_F5R2_FB11_Pos',['../group___peripheral___registers___bits___definition.html#ga998e4248e08394cf031b6d25a909a654',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r2_5ffb12_1901',['CAN_F5R2_FB12',['../group___peripheral___registers___bits___definition.html#ga974bae58f9819eee0377d709c985bcbe',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r2_5ffb12_5fmsk_1902',['CAN_F5R2_FB12_Msk',['../group___peripheral___registers___bits___definition.html#gaed02925c42bc722b25c350bc00ec815f',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r2_5ffb12_5fpos_1903',['CAN_F5R2_FB12_Pos',['../group___peripheral___registers___bits___definition.html#ga1bf1445ca1ebcf7eed420cf412e07f05',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r2_5ffb13_1904',['CAN_F5R2_FB13',['../group___peripheral___registers___bits___definition.html#ga2823bb25e138cc52d11b154456947ab7',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r2_5ffb13_5fmsk_1905',['CAN_F5R2_FB13_Msk',['../group___peripheral___registers___bits___definition.html#gaf6a2dbe8f45f7a844a2dd0dcf07786d6',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r2_5ffb13_5fpos_1906',['CAN_F5R2_FB13_Pos',['../group___peripheral___registers___bits___definition.html#ga80ab623333a37c66175f1b9b239cce27',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r2_5ffb14_1907',['CAN_F5R2_FB14',['../group___peripheral___registers___bits___definition.html#ga98cf223bdcc1a106f7573b57f836f9ed',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r2_5ffb14_5fmsk_1908',['CAN_F5R2_FB14_Msk',['../group___peripheral___registers___bits___definition.html#gac6d471b7cf1edcabeba6eb8af6a2ca83',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r2_5ffb14_5fpos_1909',['CAN_F5R2_FB14_Pos',['../group___peripheral___registers___bits___definition.html#ga019a3a59115f5994ef92a14ea8373bef',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r2_5ffb15_1910',['CAN_F5R2_FB15',['../group___peripheral___registers___bits___definition.html#ga26bfd14720495dd180f1524f2fdb3743',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r2_5ffb15_5fmsk_1911',['CAN_F5R2_FB15_Msk',['../group___peripheral___registers___bits___definition.html#gab3dde50a6686b9be1d26d3d855e85f7c',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r2_5ffb15_5fpos_1912',['CAN_F5R2_FB15_Pos',['../group___peripheral___registers___bits___definition.html#ga9dac6309c6bf54e66e6fdae4771190ad',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r2_5ffb16_1913',['CAN_F5R2_FB16',['../group___peripheral___registers___bits___definition.html#ga41b457c721dc855d05b2f353c22a83a7',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r2_5ffb16_5fmsk_1914',['CAN_F5R2_FB16_Msk',['../group___peripheral___registers___bits___definition.html#ga0ee326307cb31cf3cc82c36765a14f5f',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r2_5ffb16_5fpos_1915',['CAN_F5R2_FB16_Pos',['../group___peripheral___registers___bits___definition.html#ga2f6cb58d414c1819c65d080328db8044',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r2_5ffb17_1916',['CAN_F5R2_FB17',['../group___peripheral___registers___bits___definition.html#ga1bc89534aaf3f810a2151b04b0086717',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r2_5ffb17_5fmsk_1917',['CAN_F5R2_FB17_Msk',['../group___peripheral___registers___bits___definition.html#gae4d64f35fb861a436083a675a4d55087',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r2_5ffb17_5fpos_1918',['CAN_F5R2_FB17_Pos',['../group___peripheral___registers___bits___definition.html#gaf5c8011137b67c4ad3a51b1139a3e0ed',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r2_5ffb18_1919',['CAN_F5R2_FB18',['../group___peripheral___registers___bits___definition.html#ga070940536728fad3c0e5336926131b4b',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r2_5ffb18_5fmsk_1920',['CAN_F5R2_FB18_Msk',['../group___peripheral___registers___bits___definition.html#gae05e7364c82e1f610e927785ec039d6a',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r2_5ffb18_5fpos_1921',['CAN_F5R2_FB18_Pos',['../group___peripheral___registers___bits___definition.html#ga96dcca6b4fa2e2cf12ffe3af72a1b679',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r2_5ffb19_1922',['CAN_F5R2_FB19',['../group___peripheral___registers___bits___definition.html#gaddf2e4aa8107150a86d37ce03a0e1c0e',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r2_5ffb19_5fmsk_1923',['CAN_F5R2_FB19_Msk',['../group___peripheral___registers___bits___definition.html#gac707fb2bec18e9152234fc5c58b5cbc9',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r2_5ffb19_5fpos_1924',['CAN_F5R2_FB19_Pos',['../group___peripheral___registers___bits___definition.html#ga60046c4ebf351deeaf74223758d53675',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r2_5ffb1_5fmsk_1925',['CAN_F5R2_FB1_Msk',['../group___peripheral___registers___bits___definition.html#gaa669537bb8f8adf60f0d40d76f5d9fb9',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r2_5ffb1_5fpos_1926',['CAN_F5R2_FB1_Pos',['../group___peripheral___registers___bits___definition.html#gaf76834e934a1e6431cc7d604747050e1',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r2_5ffb2_1927',['CAN_F5R2_FB2',['../group___peripheral___registers___bits___definition.html#gaf44a72156023a5889a1c22d77e188e2e',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r2_5ffb20_1928',['CAN_F5R2_FB20',['../group___peripheral___registers___bits___definition.html#ga1788704faad47f1d45017df41a35f053',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r2_5ffb20_5fmsk_1929',['CAN_F5R2_FB20_Msk',['../group___peripheral___registers___bits___definition.html#ga543013c958dcfd0719772fcea3ec7442',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r2_5ffb20_5fpos_1930',['CAN_F5R2_FB20_Pos',['../group___peripheral___registers___bits___definition.html#gae3ae858c989b3736de3373c42fac5775',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r2_5ffb21_1931',['CAN_F5R2_FB21',['../group___peripheral___registers___bits___definition.html#ga11c4aeffb6646643c412e19e6f5cc015',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r2_5ffb21_5fmsk_1932',['CAN_F5R2_FB21_Msk',['../group___peripheral___registers___bits___definition.html#gab64136662c15ae221d5a0c1a5dd54b08',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r2_5ffb21_5fpos_1933',['CAN_F5R2_FB21_Pos',['../group___peripheral___registers___bits___definition.html#gafb635f8a3ff310a99ae6ef459d681ac6',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r2_5ffb22_1934',['CAN_F5R2_FB22',['../group___peripheral___registers___bits___definition.html#gaef348c2d37f96f5e5324368f90c80d42',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r2_5ffb22_5fmsk_1935',['CAN_F5R2_FB22_Msk',['../group___peripheral___registers___bits___definition.html#ga61b1a77cc46c59213948b974f622090d',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r2_5ffb22_5fpos_1936',['CAN_F5R2_FB22_Pos',['../group___peripheral___registers___bits___definition.html#ga684958cea52e6120dcdc40a55c1442e2',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r2_5ffb23_1937',['CAN_F5R2_FB23',['../group___peripheral___registers___bits___definition.html#ga398d842cfcb2d441d999e1407fc54f83',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r2_5ffb23_5fmsk_1938',['CAN_F5R2_FB23_Msk',['../group___peripheral___registers___bits___definition.html#ga99c053ca550685ca82a4068cb35dcf1e',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r2_5ffb23_5fpos_1939',['CAN_F5R2_FB23_Pos',['../group___peripheral___registers___bits___definition.html#gaa8ecdc64db223884f8a2a539045a52a2',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r2_5ffb24_1940',['CAN_F5R2_FB24',['../group___peripheral___registers___bits___definition.html#ga6575f8d4d154e2e8342b3f88352a9d52',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r2_5ffb24_5fmsk_1941',['CAN_F5R2_FB24_Msk',['../group___peripheral___registers___bits___definition.html#ga95a78f8f2aa15cad8513b89355533e9c',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r2_5ffb24_5fpos_1942',['CAN_F5R2_FB24_Pos',['../group___peripheral___registers___bits___definition.html#gab98edeba8a885855d8ab39e4da3b2a23',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r2_5ffb25_1943',['CAN_F5R2_FB25',['../group___peripheral___registers___bits___definition.html#gae9e6ad77b1d8ac7303e920658aceb354',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r2_5ffb25_5fmsk_1944',['CAN_F5R2_FB25_Msk',['../group___peripheral___registers___bits___definition.html#ga008957461f388566b56639ecbc17cebb',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r2_5ffb25_5fpos_1945',['CAN_F5R2_FB25_Pos',['../group___peripheral___registers___bits___definition.html#ga0a4842fb46f7a105bbd49413c6eee911',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r2_5ffb26_1946',['CAN_F5R2_FB26',['../group___peripheral___registers___bits___definition.html#ga911ade78e30d1a037d35dda5eb7cbd4b',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r2_5ffb26_5fmsk_1947',['CAN_F5R2_FB26_Msk',['../group___peripheral___registers___bits___definition.html#ga933f9591f9dd20f70ba06053f261fac2',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r2_5ffb26_5fpos_1948',['CAN_F5R2_FB26_Pos',['../group___peripheral___registers___bits___definition.html#ga7170d32e10c78e3fc54d039496f53506',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r2_5ffb27_1949',['CAN_F5R2_FB27',['../group___peripheral___registers___bits___definition.html#ga49542b9334bc4917e25d6808c78787d1',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r2_5ffb27_5fmsk_1950',['CAN_F5R2_FB27_Msk',['../group___peripheral___registers___bits___definition.html#gadb9d77aef830c128d7c7582c5b05799b',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r2_5ffb27_5fpos_1951',['CAN_F5R2_FB27_Pos',['../group___peripheral___registers___bits___definition.html#ga36212c15d8fb9e6fd90221aa199ce898',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r2_5ffb28_1952',['CAN_F5R2_FB28',['../group___peripheral___registers___bits___definition.html#ga255da64f4a66ff888f6633d6e51658c6',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r2_5ffb28_5fmsk_1953',['CAN_F5R2_FB28_Msk',['../group___peripheral___registers___bits___definition.html#ga28c9aaa77d535cf3323afecae54f2014',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r2_5ffb28_5fpos_1954',['CAN_F5R2_FB28_Pos',['../group___peripheral___registers___bits___definition.html#gafe87106ef6da9830afb1aa98c5e65823',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r2_5ffb29_1955',['CAN_F5R2_FB29',['../group___peripheral___registers___bits___definition.html#ga8335d23f9fd156f40dc7fd63ba6783cb',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r2_5ffb29_5fmsk_1956',['CAN_F5R2_FB29_Msk',['../group___peripheral___registers___bits___definition.html#gae3a0ff1fd4b5ea4e84e5ef7c11553ac6',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r2_5ffb29_5fpos_1957',['CAN_F5R2_FB29_Pos',['../group___peripheral___registers___bits___definition.html#gae96aac0fb32c68c6803fa56115592c4d',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r2_5ffb2_5fmsk_1958',['CAN_F5R2_FB2_Msk',['../group___peripheral___registers___bits___definition.html#gaa81eadbcd56cc52d9c0b7435ba5b40e9',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r2_5ffb2_5fpos_1959',['CAN_F5R2_FB2_Pos',['../group___peripheral___registers___bits___definition.html#gab8245d1c94d1b1b37f88fbb8361d0995',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r2_5ffb3_1960',['CAN_F5R2_FB3',['../group___peripheral___registers___bits___definition.html#ga3d8828885a79299bc65c2011f71240e2',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r2_5ffb30_1961',['CAN_F5R2_FB30',['../group___peripheral___registers___bits___definition.html#gaf81786b7519b39f705729de2c55e4faa',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r2_5ffb30_5fmsk_1962',['CAN_F5R2_FB30_Msk',['../group___peripheral___registers___bits___definition.html#gae3d4abd59ef329e2a4cdacd80450b71e',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r2_5ffb30_5fpos_1963',['CAN_F5R2_FB30_Pos',['../group___peripheral___registers___bits___definition.html#ga1e488b1f7932407cda7b439bf69df464',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r2_5ffb31_1964',['CAN_F5R2_FB31',['../group___peripheral___registers___bits___definition.html#ga4f7122b0ad8cb4fc1797d0dbecbb4a05',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r2_5ffb31_5fmsk_1965',['CAN_F5R2_FB31_Msk',['../group___peripheral___registers___bits___definition.html#ga872287cb1dc75d841a74fef1df7d04c4',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r2_5ffb31_5fpos_1966',['CAN_F5R2_FB31_Pos',['../group___peripheral___registers___bits___definition.html#gabb423f7f26c55460925e1d1a7e5a073d',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r2_5ffb3_5fmsk_1967',['CAN_F5R2_FB3_Msk',['../group___peripheral___registers___bits___definition.html#ga4271ce693ee149054334055f32083514',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r2_5ffb3_5fpos_1968',['CAN_F5R2_FB3_Pos',['../group___peripheral___registers___bits___definition.html#ga53e88ec5a445a1a06d1106bb8d306ef6',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r2_5ffb4_1969',['CAN_F5R2_FB4',['../group___peripheral___registers___bits___definition.html#gadfa978108927c827e3021499a20d0372',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r2_5ffb4_5fmsk_1970',['CAN_F5R2_FB4_Msk',['../group___peripheral___registers___bits___definition.html#gac4dd49575e4657b373fd5cdc67067e0d',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r2_5ffb4_5fpos_1971',['CAN_F5R2_FB4_Pos',['../group___peripheral___registers___bits___definition.html#ga4516eaeaa55e303db71ed3ae9babff88',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r2_5ffb5_1972',['CAN_F5R2_FB5',['../group___peripheral___registers___bits___definition.html#gaf3b3c48011935170a9bd120b724030fe',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r2_5ffb5_5fmsk_1973',['CAN_F5R2_FB5_Msk',['../group___peripheral___registers___bits___definition.html#gac14329fcf8b7c680e02b7967e8cb98ea',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r2_5ffb5_5fpos_1974',['CAN_F5R2_FB5_Pos',['../group___peripheral___registers___bits___definition.html#gaa4cd2ba17430db1908a126f95f8b3811',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r2_5ffb6_1975',['CAN_F5R2_FB6',['../group___peripheral___registers___bits___definition.html#ga56cf7f6d0bf48847f3d8f72777774e58',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r2_5ffb6_5fmsk_1976',['CAN_F5R2_FB6_Msk',['../group___peripheral___registers___bits___definition.html#ga119d967c2b9dff5291f892ed55650722',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r2_5ffb6_5fpos_1977',['CAN_F5R2_FB6_Pos',['../group___peripheral___registers___bits___definition.html#gab9c07be713f85a6784c934880b47fac6',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r2_5ffb7_1978',['CAN_F5R2_FB7',['../group___peripheral___registers___bits___definition.html#ga2cb8a5551d90c8d79b09b4d82f3f59c2',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r2_5ffb7_5fmsk_1979',['CAN_F5R2_FB7_Msk',['../group___peripheral___registers___bits___definition.html#gae72af802de3283727835678b4d783b7e',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r2_5ffb7_5fpos_1980',['CAN_F5R2_FB7_Pos',['../group___peripheral___registers___bits___definition.html#gaa0853bd11144bb38e99488b1bb31899a',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r2_5ffb8_1981',['CAN_F5R2_FB8',['../group___peripheral___registers___bits___definition.html#ga423b7b77bfd5dd6791f1b1dd16e9807a',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r2_5ffb8_5fmsk_1982',['CAN_F5R2_FB8_Msk',['../group___peripheral___registers___bits___definition.html#gaa770d4e9ecd17918854fc97a3d96bdfd',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r2_5ffb8_5fpos_1983',['CAN_F5R2_FB8_Pos',['../group___peripheral___registers___bits___definition.html#gafef8fdd804993ad8b9cbce7223f888c8',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r2_5ffb9_1984',['CAN_F5R2_FB9',['../group___peripheral___registers___bits___definition.html#ga9c50420a128a70341e63ad23b0bedba5',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r2_5ffb9_5fmsk_1985',['CAN_F5R2_FB9_Msk',['../group___peripheral___registers___bits___definition.html#gab4d4e4451476d46716de06cef008beb1',1,'stm32f407xx_matlab.h']]], - ['can_5ff5r2_5ffb9_5fpos_1986',['CAN_F5R2_FB9_Pos',['../group___peripheral___registers___bits___definition.html#ga6eed4d57ced26b73f1b76bdfbabfe980',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r1_5ffb0_1987',['CAN_F6R1_FB0',['../group___peripheral___registers___bits___definition.html#gacb57fe42259bd37deffe11eded640c76',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r1_5ffb0_5fmsk_1988',['CAN_F6R1_FB0_Msk',['../group___peripheral___registers___bits___definition.html#ga8aaf448c354a5a325c540df29f7af6ad',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r1_5ffb0_5fpos_1989',['CAN_F6R1_FB0_Pos',['../group___peripheral___registers___bits___definition.html#ga2a05745a737f85b835db1099ff6e7263',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r1_5ffb1_1990',['CAN_F6R1_FB1',['../group___peripheral___registers___bits___definition.html#ga1de288e28d5547106645ecc5b0c47f2a',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r1_5ffb10_1991',['CAN_F6R1_FB10',['../group___peripheral___registers___bits___definition.html#gaa63ca9ec114f553d68e0b0d38ae57ff0',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r1_5ffb10_5fmsk_1992',['CAN_F6R1_FB10_Msk',['../group___peripheral___registers___bits___definition.html#ga0a103dac7595c91ff96149735c5ce964',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r1_5ffb10_5fpos_1993',['CAN_F6R1_FB10_Pos',['../group___peripheral___registers___bits___definition.html#ga19bca6dcb49673694c6ac968da048d79',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r1_5ffb11_1994',['CAN_F6R1_FB11',['../group___peripheral___registers___bits___definition.html#gadf3394a2675a7cb30556a40cc5b77c08',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r1_5ffb11_5fmsk_1995',['CAN_F6R1_FB11_Msk',['../group___peripheral___registers___bits___definition.html#gaf418fcb1f3c27715523268e65cacab77',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r1_5ffb11_5fpos_1996',['CAN_F6R1_FB11_Pos',['../group___peripheral___registers___bits___definition.html#gaf750a53eaea8fac3215da663a4d1fbd7',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r1_5ffb12_1997',['CAN_F6R1_FB12',['../group___peripheral___registers___bits___definition.html#gae9c9c04edb492e48619de926196ab695',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r1_5ffb12_5fmsk_1998',['CAN_F6R1_FB12_Msk',['../group___peripheral___registers___bits___definition.html#gaf975da091767c6f1106d725426874602',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r1_5ffb12_5fpos_1999',['CAN_F6R1_FB12_Pos',['../group___peripheral___registers___bits___definition.html#ga7fe4fd95f7cac5eda54ed4260e350d8e',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r1_5ffb13_2000',['CAN_F6R1_FB13',['../group___peripheral___registers___bits___definition.html#ga070e91897e07ae11a9d2f60ff31e196a',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r1_5ffb13_5fmsk_2001',['CAN_F6R1_FB13_Msk',['../group___peripheral___registers___bits___definition.html#gaf024ad0a5286c193a57e761ae8dd78ab',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r1_5ffb13_5fpos_2002',['CAN_F6R1_FB13_Pos',['../group___peripheral___registers___bits___definition.html#ga0854e19abe416754a29c04869c5dd57b',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r1_5ffb14_2003',['CAN_F6R1_FB14',['../group___peripheral___registers___bits___definition.html#ga3479321a85f1f55e24a1b56d13226a22',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r1_5ffb14_5fmsk_2004',['CAN_F6R1_FB14_Msk',['../group___peripheral___registers___bits___definition.html#ga2dcc33648e9130b7b12dd082032e1e02',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r1_5ffb14_5fpos_2005',['CAN_F6R1_FB14_Pos',['../group___peripheral___registers___bits___definition.html#ga06cb4f011cdc5345ffd410b209ae38ef',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r1_5ffb15_2006',['CAN_F6R1_FB15',['../group___peripheral___registers___bits___definition.html#ga9a998a2b37fde5207b286a58c115a9e8',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r1_5ffb15_5fmsk_2007',['CAN_F6R1_FB15_Msk',['../group___peripheral___registers___bits___definition.html#gad577265745548ad4066ee66d7db968f5',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r1_5ffb15_5fpos_2008',['CAN_F6R1_FB15_Pos',['../group___peripheral___registers___bits___definition.html#ga2a55b3fc85269d073d5cda9c98e2e1ef',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r1_5ffb16_2009',['CAN_F6R1_FB16',['../group___peripheral___registers___bits___definition.html#ga891ad3d341cee397d49fc982c509f7d5',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r1_5ffb16_5fmsk_2010',['CAN_F6R1_FB16_Msk',['../group___peripheral___registers___bits___definition.html#gaba4c35e9c340e717ba471e6913120bac',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r1_5ffb16_5fpos_2011',['CAN_F6R1_FB16_Pos',['../group___peripheral___registers___bits___definition.html#ga2d3df4af8b5925814763b952a9c6f328',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r1_5ffb17_2012',['CAN_F6R1_FB17',['../group___peripheral___registers___bits___definition.html#gac4a70606f1b07a6bbb5ae4fe8ad374e5',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r1_5ffb17_5fmsk_2013',['CAN_F6R1_FB17_Msk',['../group___peripheral___registers___bits___definition.html#ga4b71b0660dd705a9ebe22c2e768e4172',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r1_5ffb17_5fpos_2014',['CAN_F6R1_FB17_Pos',['../group___peripheral___registers___bits___definition.html#ga96c2447a18f72f6dd8d73e51d72ca71f',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r1_5ffb18_2015',['CAN_F6R1_FB18',['../group___peripheral___registers___bits___definition.html#ga1542ea54030e3052c8991b249cd0e504',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r1_5ffb18_5fmsk_2016',['CAN_F6R1_FB18_Msk',['../group___peripheral___registers___bits___definition.html#ga42fa5a606d58f2a30da9a58581178127',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r1_5ffb18_5fpos_2017',['CAN_F6R1_FB18_Pos',['../group___peripheral___registers___bits___definition.html#gae3aa83c6161527cef489d960584af040',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r1_5ffb19_2018',['CAN_F6R1_FB19',['../group___peripheral___registers___bits___definition.html#ga1e1a7c680bcfc57c6cc521cbaa0749d6',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r1_5ffb19_5fmsk_2019',['CAN_F6R1_FB19_Msk',['../group___peripheral___registers___bits___definition.html#ga433c7e51a79cc95f7aa5593c5d347dfc',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r1_5ffb19_5fpos_2020',['CAN_F6R1_FB19_Pos',['../group___peripheral___registers___bits___definition.html#gaa6a4e2993cf15d28b3ff030793d110a6',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r1_5ffb1_5fmsk_2021',['CAN_F6R1_FB1_Msk',['../group___peripheral___registers___bits___definition.html#gae3154b0f8cb4e1e230e37da1e696659f',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r1_5ffb1_5fpos_2022',['CAN_F6R1_FB1_Pos',['../group___peripheral___registers___bits___definition.html#gabc9c5707374ef1577ec2a5c7dec11322',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r1_5ffb2_2023',['CAN_F6R1_FB2',['../group___peripheral___registers___bits___definition.html#gaaa8662caaa28aee37b2689f55400b75c',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r1_5ffb20_2024',['CAN_F6R1_FB20',['../group___peripheral___registers___bits___definition.html#ga6fba31d938ab3492c8855c26bebfbef2',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r1_5ffb20_5fmsk_2025',['CAN_F6R1_FB20_Msk',['../group___peripheral___registers___bits___definition.html#ga6b843a11577d4891e11238810c01ccea',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r1_5ffb20_5fpos_2026',['CAN_F6R1_FB20_Pos',['../group___peripheral___registers___bits___definition.html#ga9841eeaf6951092200c67ee2e1d8959d',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r1_5ffb21_2027',['CAN_F6R1_FB21',['../group___peripheral___registers___bits___definition.html#ga556f3b08cee839e038109e604e5bba4c',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r1_5ffb21_5fmsk_2028',['CAN_F6R1_FB21_Msk',['../group___peripheral___registers___bits___definition.html#gab49834ceca6245c6bed6b011c37cb51c',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r1_5ffb21_5fpos_2029',['CAN_F6R1_FB21_Pos',['../group___peripheral___registers___bits___definition.html#gaef6fa85c2d4ef60e08f9cc04e5531c48',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r1_5ffb22_2030',['CAN_F6R1_FB22',['../group___peripheral___registers___bits___definition.html#gafdc41162219ed6f5be1b5ae7ba328754',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r1_5ffb22_5fmsk_2031',['CAN_F6R1_FB22_Msk',['../group___peripheral___registers___bits___definition.html#gabbd32cd4a51845ae3257bec44dea5f36',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r1_5ffb22_5fpos_2032',['CAN_F6R1_FB22_Pos',['../group___peripheral___registers___bits___definition.html#gad7fbd8ee1cf6970c9065f5afa0a7f3d8',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r1_5ffb23_2033',['CAN_F6R1_FB23',['../group___peripheral___registers___bits___definition.html#ga89f4fd5c28d2fd7475081b39b2b358c6',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r1_5ffb23_5fmsk_2034',['CAN_F6R1_FB23_Msk',['../group___peripheral___registers___bits___definition.html#ga601aa03929a9eed61e4191a049c75fb8',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r1_5ffb23_5fpos_2035',['CAN_F6R1_FB23_Pos',['../group___peripheral___registers___bits___definition.html#gaa12596b4ab04f15a4de2a08772365def',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r1_5ffb24_2036',['CAN_F6R1_FB24',['../group___peripheral___registers___bits___definition.html#gac5eb9d0f3cad0eeea398f2ba5fd83cf2',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r1_5ffb24_5fmsk_2037',['CAN_F6R1_FB24_Msk',['../group___peripheral___registers___bits___definition.html#ga2707b11422d80fcc55e5759c7d7a3983',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r1_5ffb24_5fpos_2038',['CAN_F6R1_FB24_Pos',['../group___peripheral___registers___bits___definition.html#gadfa75de907e614398eb71f98ebcd4f9e',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r1_5ffb25_2039',['CAN_F6R1_FB25',['../group___peripheral___registers___bits___definition.html#gaa3fa46e9d1fafcb3eb1189d6d43692cd',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r1_5ffb25_5fmsk_2040',['CAN_F6R1_FB25_Msk',['../group___peripheral___registers___bits___definition.html#ga50ed60d8e8930a207039da6873a403b4',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r1_5ffb25_5fpos_2041',['CAN_F6R1_FB25_Pos',['../group___peripheral___registers___bits___definition.html#gaafc2b7e2fbf01700501b1d5fb0ed54d6',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r1_5ffb26_2042',['CAN_F6R1_FB26',['../group___peripheral___registers___bits___definition.html#gab9168b4d12ddb654b397ce3ffb66af4c',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r1_5ffb26_5fmsk_2043',['CAN_F6R1_FB26_Msk',['../group___peripheral___registers___bits___definition.html#gae2202fe7314b833d290f25a0e5234169',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r1_5ffb26_5fpos_2044',['CAN_F6R1_FB26_Pos',['../group___peripheral___registers___bits___definition.html#ga63a7a5394639689f077cd23a1bc2a2c3',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r1_5ffb27_2045',['CAN_F6R1_FB27',['../group___peripheral___registers___bits___definition.html#ga610fdf301fb1cff5af38f83b4e0c81b1',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r1_5ffb27_5fmsk_2046',['CAN_F6R1_FB27_Msk',['../group___peripheral___registers___bits___definition.html#ga45b34d58ea8416ea9ccdadd87259d810',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r1_5ffb27_5fpos_2047',['CAN_F6R1_FB27_Pos',['../group___peripheral___registers___bits___definition.html#ga193993f46c36ffb52f560dd38e2f2b14',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r1_5ffb28_2048',['CAN_F6R1_FB28',['../group___peripheral___registers___bits___definition.html#ga8a3e033aae51ff31b75fb801599232f5',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r1_5ffb28_5fmsk_2049',['CAN_F6R1_FB28_Msk',['../group___peripheral___registers___bits___definition.html#gab87f159252e6a934b1ecfb6082d8ac50',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r1_5ffb28_5fpos_2050',['CAN_F6R1_FB28_Pos',['../group___peripheral___registers___bits___definition.html#ga2064cf4f9bff8a3880b2b3f80225de4f',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r1_5ffb29_2051',['CAN_F6R1_FB29',['../group___peripheral___registers___bits___definition.html#ga868ae6fc3bbe273b44d250791a80df58',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r1_5ffb29_5fmsk_2052',['CAN_F6R1_FB29_Msk',['../group___peripheral___registers___bits___definition.html#ga87baee8a9cefd8158caf141f29881051',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r1_5ffb29_5fpos_2053',['CAN_F6R1_FB29_Pos',['../group___peripheral___registers___bits___definition.html#ga8b8ac47a8b593b2d941f2df07adc8f65',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r1_5ffb2_5fmsk_2054',['CAN_F6R1_FB2_Msk',['../group___peripheral___registers___bits___definition.html#ga5c19eddf607d2cf5941d3b6807ff89cd',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r1_5ffb2_5fpos_2055',['CAN_F6R1_FB2_Pos',['../group___peripheral___registers___bits___definition.html#ga7015e00f7ebf7b7727c89dd1e4d39aa6',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r1_5ffb3_2056',['CAN_F6R1_FB3',['../group___peripheral___registers___bits___definition.html#gae4ccedde67989fcbaa84cae9cae4b1eb',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r1_5ffb30_2057',['CAN_F6R1_FB30',['../group___peripheral___registers___bits___definition.html#gafe08696e215f9e8f1605e60e4817dd8b',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r1_5ffb30_5fmsk_2058',['CAN_F6R1_FB30_Msk',['../group___peripheral___registers___bits___definition.html#gabdec0e767a520aa7bcffac3e5652181b',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r1_5ffb30_5fpos_2059',['CAN_F6R1_FB30_Pos',['../group___peripheral___registers___bits___definition.html#ga208a9734e163cf973b02b3e7a8d9271a',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r1_5ffb31_2060',['CAN_F6R1_FB31',['../group___peripheral___registers___bits___definition.html#ga69b2dffd9969ff8658b45a7a2bb1c5ee',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r1_5ffb31_5fmsk_2061',['CAN_F6R1_FB31_Msk',['../group___peripheral___registers___bits___definition.html#ga8f2f09b2ada8e9ea6e28a7abe6dfd678',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r1_5ffb31_5fpos_2062',['CAN_F6R1_FB31_Pos',['../group___peripheral___registers___bits___definition.html#ga76a4f2683f6acc00c48fadadcc75f877',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r1_5ffb3_5fmsk_2063',['CAN_F6R1_FB3_Msk',['../group___peripheral___registers___bits___definition.html#gaec1656844d8617834262a5b6e24936bd',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r1_5ffb3_5fpos_2064',['CAN_F6R1_FB3_Pos',['../group___peripheral___registers___bits___definition.html#gac97c920c1437c8ac5df50b171f4aee5f',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r1_5ffb4_2065',['CAN_F6R1_FB4',['../group___peripheral___registers___bits___definition.html#ga45b063b3c14fd27bd63c03f878ac6cfc',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r1_5ffb4_5fmsk_2066',['CAN_F6R1_FB4_Msk',['../group___peripheral___registers___bits___definition.html#ga53a812ea22c8f0cfb484edc70dd19d6b',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r1_5ffb4_5fpos_2067',['CAN_F6R1_FB4_Pos',['../group___peripheral___registers___bits___definition.html#ga3d7ff307582eac29ccb7608880ff227d',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r1_5ffb5_2068',['CAN_F6R1_FB5',['../group___peripheral___registers___bits___definition.html#ga32f8566fab72dec6d52ad7262e67cbcc',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r1_5ffb5_5fmsk_2069',['CAN_F6R1_FB5_Msk',['../group___peripheral___registers___bits___definition.html#ga9afe1da36ff17919dc17466458f924a2',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r1_5ffb5_5fpos_2070',['CAN_F6R1_FB5_Pos',['../group___peripheral___registers___bits___definition.html#gabf3202c6c2ba274ba1a5920c47b2141d',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r1_5ffb6_2071',['CAN_F6R1_FB6',['../group___peripheral___registers___bits___definition.html#ga8636ecdacc3ca05d69e66737b7f2e7cf',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r1_5ffb6_5fmsk_2072',['CAN_F6R1_FB6_Msk',['../group___peripheral___registers___bits___definition.html#gacd31d2b1806cf454d51d956eb339d096',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r1_5ffb6_5fpos_2073',['CAN_F6R1_FB6_Pos',['../group___peripheral___registers___bits___definition.html#ga43e24b0fe81f24078bdd007cbe832c07',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r1_5ffb7_2074',['CAN_F6R1_FB7',['../group___peripheral___registers___bits___definition.html#gadb555ddab4853625c9b48b24e88d0dd8',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r1_5ffb7_5fmsk_2075',['CAN_F6R1_FB7_Msk',['../group___peripheral___registers___bits___definition.html#ga87b36413ac64900c2398a530bbe647a6',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r1_5ffb7_5fpos_2076',['CAN_F6R1_FB7_Pos',['../group___peripheral___registers___bits___definition.html#gad2438dd17101c15d44b533cf1904f2fc',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r1_5ffb8_2077',['CAN_F6R1_FB8',['../group___peripheral___registers___bits___definition.html#gaa1e7ca2d014d77152ff0e6bbb8d5fb63',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r1_5ffb8_5fmsk_2078',['CAN_F6R1_FB8_Msk',['../group___peripheral___registers___bits___definition.html#ga45055999ce3c93c3f0e13f6a5fa1da30',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r1_5ffb8_5fpos_2079',['CAN_F6R1_FB8_Pos',['../group___peripheral___registers___bits___definition.html#ga32fdb53fc39d6a2e09fcbbafb6d2ec81',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r1_5ffb9_2080',['CAN_F6R1_FB9',['../group___peripheral___registers___bits___definition.html#gafe4dc5e57c209eb4d3c5ed94b3a2e897',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r1_5ffb9_5fmsk_2081',['CAN_F6R1_FB9_Msk',['../group___peripheral___registers___bits___definition.html#gac1904252fa35eca764e319ae3d124caa',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r1_5ffb9_5fpos_2082',['CAN_F6R1_FB9_Pos',['../group___peripheral___registers___bits___definition.html#gadad128a04f722f5190105f598e2b6ac8',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r2_5ffb0_2083',['CAN_F6R2_FB0',['../group___peripheral___registers___bits___definition.html#ga71ad6452660daed3d6c436533a25efc2',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r2_5ffb0_5fmsk_2084',['CAN_F6R2_FB0_Msk',['../group___peripheral___registers___bits___definition.html#ga3f57610bbf8a5efd029417aae54d4bbb',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r2_5ffb0_5fpos_2085',['CAN_F6R2_FB0_Pos',['../group___peripheral___registers___bits___definition.html#ga20cc3ea8010fbf026315233056de5b0d',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r2_5ffb1_2086',['CAN_F6R2_FB1',['../group___peripheral___registers___bits___definition.html#gac9e24abd8d2f0775661415b6565f4f6d',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r2_5ffb10_2087',['CAN_F6R2_FB10',['../group___peripheral___registers___bits___definition.html#ga47baa2c9c05c7c422a49994b8f80016f',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r2_5ffb10_5fmsk_2088',['CAN_F6R2_FB10_Msk',['../group___peripheral___registers___bits___definition.html#gaf6ee3ac5a1ecd2c3e5a1805bbcfe6611',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r2_5ffb10_5fpos_2089',['CAN_F6R2_FB10_Pos',['../group___peripheral___registers___bits___definition.html#ga681ae7ccefdd04ea0b9fac2b6d8ce2c7',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r2_5ffb11_2090',['CAN_F6R2_FB11',['../group___peripheral___registers___bits___definition.html#ga55d7665b118e98586c2a9b1900ce7292',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r2_5ffb11_5fmsk_2091',['CAN_F6R2_FB11_Msk',['../group___peripheral___registers___bits___definition.html#gaacbaa9f91a1fc5474ecf6e149dbd309d',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r2_5ffb11_5fpos_2092',['CAN_F6R2_FB11_Pos',['../group___peripheral___registers___bits___definition.html#ga9a088bdcb4c43b019ccc2916cefc597c',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r2_5ffb12_2093',['CAN_F6R2_FB12',['../group___peripheral___registers___bits___definition.html#ga5095a203d07244e75dd6deca125b4468',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r2_5ffb12_5fmsk_2094',['CAN_F6R2_FB12_Msk',['../group___peripheral___registers___bits___definition.html#gaf7899cda2b27c9f78f33a3050f975a22',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r2_5ffb12_5fpos_2095',['CAN_F6R2_FB12_Pos',['../group___peripheral___registers___bits___definition.html#ga1041051f130d6cccb3b866a899bbd865',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r2_5ffb13_2096',['CAN_F6R2_FB13',['../group___peripheral___registers___bits___definition.html#ga533dbb10e8fce9aa6ec23573fb49c339',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r2_5ffb13_5fmsk_2097',['CAN_F6R2_FB13_Msk',['../group___peripheral___registers___bits___definition.html#gae07a6c5c781e5f858d27a824a3228ad6',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r2_5ffb13_5fpos_2098',['CAN_F6R2_FB13_Pos',['../group___peripheral___registers___bits___definition.html#gaf408b8462d783790125f047604eb7201',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r2_5ffb14_2099',['CAN_F6R2_FB14',['../group___peripheral___registers___bits___definition.html#ga8b95be922291e534609302c0c833f1f7',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r2_5ffb14_5fmsk_2100',['CAN_F6R2_FB14_Msk',['../group___peripheral___registers___bits___definition.html#gada5ad2ab34322414451520650bf405b8',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r2_5ffb14_5fpos_2101',['CAN_F6R2_FB14_Pos',['../group___peripheral___registers___bits___definition.html#ga116e5b298af1faddc25c9a2be1c0f2bf',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r2_5ffb15_2102',['CAN_F6R2_FB15',['../group___peripheral___registers___bits___definition.html#ga17301d50c7b6ad30ffc05ee2c63f6171',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r2_5ffb15_5fmsk_2103',['CAN_F6R2_FB15_Msk',['../group___peripheral___registers___bits___definition.html#ga8109424b373ae93010f98f0c7ad80e5c',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r2_5ffb15_5fpos_2104',['CAN_F6R2_FB15_Pos',['../group___peripheral___registers___bits___definition.html#gac87bd58b70908b22b5fd39b0a62a95a3',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r2_5ffb16_2105',['CAN_F6R2_FB16',['../group___peripheral___registers___bits___definition.html#gaf23dfb03247544122ed01472b8a31b4d',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r2_5ffb16_5fmsk_2106',['CAN_F6R2_FB16_Msk',['../group___peripheral___registers___bits___definition.html#gaf5a59865040cac5815a6a4099e72e0e4',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r2_5ffb16_5fpos_2107',['CAN_F6R2_FB16_Pos',['../group___peripheral___registers___bits___definition.html#ga2636cde6a4bc3ba023bc4c0fe5de75b4',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r2_5ffb17_2108',['CAN_F6R2_FB17',['../group___peripheral___registers___bits___definition.html#gadf8d35fbfa677fc446da68f4043b633e',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r2_5ffb17_5fmsk_2109',['CAN_F6R2_FB17_Msk',['../group___peripheral___registers___bits___definition.html#gadd1ca2f91f8ea1af952b18ebd27dc725',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r2_5ffb17_5fpos_2110',['CAN_F6R2_FB17_Pos',['../group___peripheral___registers___bits___definition.html#gab93f20ff2225a03f65492b6e5d499ddb',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r2_5ffb18_2111',['CAN_F6R2_FB18',['../group___peripheral___registers___bits___definition.html#ga6c81a1972ec8d87421c6113bb9747c3e',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r2_5ffb18_5fmsk_2112',['CAN_F6R2_FB18_Msk',['../group___peripheral___registers___bits___definition.html#gaa3c4bcd69ad9af4bd97c63269e95278a',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r2_5ffb18_5fpos_2113',['CAN_F6R2_FB18_Pos',['../group___peripheral___registers___bits___definition.html#ga362d1f3ea3b3bfb78fc3ccb70b813de0',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r2_5ffb19_2114',['CAN_F6R2_FB19',['../group___peripheral___registers___bits___definition.html#ga11ea1bd4bae8b27a5fd73d210eb83d39',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r2_5ffb19_5fmsk_2115',['CAN_F6R2_FB19_Msk',['../group___peripheral___registers___bits___definition.html#ga8b19c8600e4c828eab5759dae7cf2fc5',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r2_5ffb19_5fpos_2116',['CAN_F6R2_FB19_Pos',['../group___peripheral___registers___bits___definition.html#ga2a05fd66da3b0a785893d7e4ae4c38ec',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r2_5ffb1_5fmsk_2117',['CAN_F6R2_FB1_Msk',['../group___peripheral___registers___bits___definition.html#ga6b30db0682c6a7847de91680b2532808',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r2_5ffb1_5fpos_2118',['CAN_F6R2_FB1_Pos',['../group___peripheral___registers___bits___definition.html#ga57ea3c021bd5598a314a2dc310b2c242',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r2_5ffb2_2119',['CAN_F6R2_FB2',['../group___peripheral___registers___bits___definition.html#gaf6dc3f6ce4dde435743aadbe17cc78b9',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r2_5ffb20_2120',['CAN_F6R2_FB20',['../group___peripheral___registers___bits___definition.html#ga4c48dcd1ac5e23827813ed695bdff0d1',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r2_5ffb20_5fmsk_2121',['CAN_F6R2_FB20_Msk',['../group___peripheral___registers___bits___definition.html#ga21e7a0134b94773f327e99d20877707b',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r2_5ffb20_5fpos_2122',['CAN_F6R2_FB20_Pos',['../group___peripheral___registers___bits___definition.html#ga126bec7490158480e1c8011828bc900b',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r2_5ffb21_2123',['CAN_F6R2_FB21',['../group___peripheral___registers___bits___definition.html#gacd115d29d9f0a8fddc13a32c013af26b',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r2_5ffb21_5fmsk_2124',['CAN_F6R2_FB21_Msk',['../group___peripheral___registers___bits___definition.html#ga049c4c90a51a7370af5575dd2ce43b25',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r2_5ffb21_5fpos_2125',['CAN_F6R2_FB21_Pos',['../group___peripheral___registers___bits___definition.html#ga003e56f189cb2d03ceb4d86ebbfb1a96',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r2_5ffb22_2126',['CAN_F6R2_FB22',['../group___peripheral___registers___bits___definition.html#gaa3f116b2e31dd40bcdd6617fee83907e',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r2_5ffb22_5fmsk_2127',['CAN_F6R2_FB22_Msk',['../group___peripheral___registers___bits___definition.html#ga70456f1faf630198eb6a6aa9d014465b',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r2_5ffb22_5fpos_2128',['CAN_F6R2_FB22_Pos',['../group___peripheral___registers___bits___definition.html#ga178f147b77209ef59f0d73059ff40734',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r2_5ffb23_2129',['CAN_F6R2_FB23',['../group___peripheral___registers___bits___definition.html#ga090da76d2d9379dbfc54f7c3fcf69fe4',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r2_5ffb23_5fmsk_2130',['CAN_F6R2_FB23_Msk',['../group___peripheral___registers___bits___definition.html#ga1523937cea2319fb9c692056b8599861',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r2_5ffb23_5fpos_2131',['CAN_F6R2_FB23_Pos',['../group___peripheral___registers___bits___definition.html#ga252f65a784a6e484323ecbb340a06540',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r2_5ffb24_2132',['CAN_F6R2_FB24',['../group___peripheral___registers___bits___definition.html#gae9c8a59a8065400f4a75be49a78e2a9e',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r2_5ffb24_5fmsk_2133',['CAN_F6R2_FB24_Msk',['../group___peripheral___registers___bits___definition.html#ga1b080d0ae18594e56bc64fa67e298d6d',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r2_5ffb24_5fpos_2134',['CAN_F6R2_FB24_Pos',['../group___peripheral___registers___bits___definition.html#ga1e75f6bf8e5658bb7539704812be0267',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r2_5ffb25_2135',['CAN_F6R2_FB25',['../group___peripheral___registers___bits___definition.html#ga3854a1a11c72e64d3c4722494f463421',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r2_5ffb25_5fmsk_2136',['CAN_F6R2_FB25_Msk',['../group___peripheral___registers___bits___definition.html#gacb8abbda99bc68f0dcfe984ee985bd5d',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r2_5ffb25_5fpos_2137',['CAN_F6R2_FB25_Pos',['../group___peripheral___registers___bits___definition.html#gac10f8f8e4e72fae0d0b8f910c1fe96d9',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r2_5ffb26_2138',['CAN_F6R2_FB26',['../group___peripheral___registers___bits___definition.html#ga7b5ceb9d7ae0c6e34490b8d8659919c9',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r2_5ffb26_5fmsk_2139',['CAN_F6R2_FB26_Msk',['../group___peripheral___registers___bits___definition.html#gab5cf38e7dad669f04679189c848749f3',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r2_5ffb26_5fpos_2140',['CAN_F6R2_FB26_Pos',['../group___peripheral___registers___bits___definition.html#ga266f93b0c8f656140718c98f2c93d0bd',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r2_5ffb27_2141',['CAN_F6R2_FB27',['../group___peripheral___registers___bits___definition.html#gac01a4accedd624ceccf8f8976a043177',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r2_5ffb27_5fmsk_2142',['CAN_F6R2_FB27_Msk',['../group___peripheral___registers___bits___definition.html#ga607397b46ace68583b5b13f6d6f23cb7',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r2_5ffb27_5fpos_2143',['CAN_F6R2_FB27_Pos',['../group___peripheral___registers___bits___definition.html#ga5ef9ca5e08378882d65e1f754e8b197c',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r2_5ffb28_2144',['CAN_F6R2_FB28',['../group___peripheral___registers___bits___definition.html#gacc2d754207055a5a87696eb1bb7d8cae',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r2_5ffb28_5fmsk_2145',['CAN_F6R2_FB28_Msk',['../group___peripheral___registers___bits___definition.html#gaed265f9447716d0d3bc7dad1a295630c',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r2_5ffb28_5fpos_2146',['CAN_F6R2_FB28_Pos',['../group___peripheral___registers___bits___definition.html#gaea647666f32db62170873fb233f9eeda',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r2_5ffb29_2147',['CAN_F6R2_FB29',['../group___peripheral___registers___bits___definition.html#ga471631ee112af3bde77d848c22d743ef',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r2_5ffb29_5fmsk_2148',['CAN_F6R2_FB29_Msk',['../group___peripheral___registers___bits___definition.html#ga61e13bb0d4c0c6e131e3989c5a5d88b0',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r2_5ffb29_5fpos_2149',['CAN_F6R2_FB29_Pos',['../group___peripheral___registers___bits___definition.html#ga68de26372621969702f54818909e3d45',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r2_5ffb2_5fmsk_2150',['CAN_F6R2_FB2_Msk',['../group___peripheral___registers___bits___definition.html#gaa901630470057df2e214f14994a714aa',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r2_5ffb2_5fpos_2151',['CAN_F6R2_FB2_Pos',['../group___peripheral___registers___bits___definition.html#gadb418d7998996d8fbbbe6a7f9f81a6d3',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r2_5ffb3_2152',['CAN_F6R2_FB3',['../group___peripheral___registers___bits___definition.html#gae1f5163490dffe1f4d7c635458359c2f',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r2_5ffb30_2153',['CAN_F6R2_FB30',['../group___peripheral___registers___bits___definition.html#ga9574ec7dddcea6b80368778c01f62598',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r2_5ffb30_5fmsk_2154',['CAN_F6R2_FB30_Msk',['../group___peripheral___registers___bits___definition.html#ga9ef6901cea91b3ea9b40c0d40980f554',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r2_5ffb30_5fpos_2155',['CAN_F6R2_FB30_Pos',['../group___peripheral___registers___bits___definition.html#ga5e57f1bffaa844b03cdb0743f9b78c2b',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r2_5ffb31_2156',['CAN_F6R2_FB31',['../group___peripheral___registers___bits___definition.html#ga64bcb159347ad8e2a2609ce89ed030df',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r2_5ffb31_5fmsk_2157',['CAN_F6R2_FB31_Msk',['../group___peripheral___registers___bits___definition.html#gaaf6098323e8ea2d82b3dd9b355977d6b',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r2_5ffb31_5fpos_2158',['CAN_F6R2_FB31_Pos',['../group___peripheral___registers___bits___definition.html#ga245979ba9e0a5c2d545fae929eb99892',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r2_5ffb3_5fmsk_2159',['CAN_F6R2_FB3_Msk',['../group___peripheral___registers___bits___definition.html#gaa0d1bbfb93db519a92310ca7074289e7',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r2_5ffb3_5fpos_2160',['CAN_F6R2_FB3_Pos',['../group___peripheral___registers___bits___definition.html#ga2a70af83c83018fdb987a9121ef6bba7',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r2_5ffb4_2161',['CAN_F6R2_FB4',['../group___peripheral___registers___bits___definition.html#ga89e9191d214d05f4d90fbcd38daa73e1',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r2_5ffb4_5fmsk_2162',['CAN_F6R2_FB4_Msk',['../group___peripheral___registers___bits___definition.html#ga747c01d82b012765a96bf20ae2d1e614',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r2_5ffb4_5fpos_2163',['CAN_F6R2_FB4_Pos',['../group___peripheral___registers___bits___definition.html#gaaff0bb055714dfce4422592cc05805c2',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r2_5ffb5_2164',['CAN_F6R2_FB5',['../group___peripheral___registers___bits___definition.html#ga97d29588281c546d98e09760cc5ef593',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r2_5ffb5_5fmsk_2165',['CAN_F6R2_FB5_Msk',['../group___peripheral___registers___bits___definition.html#ga731205c17b0265b0aed17e7335d665f1',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r2_5ffb5_5fpos_2166',['CAN_F6R2_FB5_Pos',['../group___peripheral___registers___bits___definition.html#ga69724e09645446cfec63ef3720f3424e',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r2_5ffb6_2167',['CAN_F6R2_FB6',['../group___peripheral___registers___bits___definition.html#ga53f5717aca9932255049b133661765bf',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r2_5ffb6_5fmsk_2168',['CAN_F6R2_FB6_Msk',['../group___peripheral___registers___bits___definition.html#gab107baf898c53eca495a0cec40383c4a',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r2_5ffb6_5fpos_2169',['CAN_F6R2_FB6_Pos',['../group___peripheral___registers___bits___definition.html#ga3cee5f9332b40105e0594c546910a2e2',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r2_5ffb7_2170',['CAN_F6R2_FB7',['../group___peripheral___registers___bits___definition.html#ga7ec93958e936379d891bc3450dba3d1d',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r2_5ffb7_5fmsk_2171',['CAN_F6R2_FB7_Msk',['../group___peripheral___registers___bits___definition.html#gacec3cbdfadb57b83f4a10629f5ff93a6',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r2_5ffb7_5fpos_2172',['CAN_F6R2_FB7_Pos',['../group___peripheral___registers___bits___definition.html#gac4ca498cfaea259d91ac4f15692a3bcc',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r2_5ffb8_2173',['CAN_F6R2_FB8',['../group___peripheral___registers___bits___definition.html#ga8f97c7eb9d6e69d589db38d745ae321c',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r2_5ffb8_5fmsk_2174',['CAN_F6R2_FB8_Msk',['../group___peripheral___registers___bits___definition.html#gaecb8cf6a22127fde7bbef7da331362fa',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r2_5ffb8_5fpos_2175',['CAN_F6R2_FB8_Pos',['../group___peripheral___registers___bits___definition.html#ga3f8b7c262d5a1e51c7cd479cf7a47719',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r2_5ffb9_2176',['CAN_F6R2_FB9',['../group___peripheral___registers___bits___definition.html#ga372ebb5d42d147d41688f7c0fcf467d2',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r2_5ffb9_5fmsk_2177',['CAN_F6R2_FB9_Msk',['../group___peripheral___registers___bits___definition.html#ga1625345e2205b59ee47e4522833a023f',1,'stm32f407xx_matlab.h']]], - ['can_5ff6r2_5ffb9_5fpos_2178',['CAN_F6R2_FB9_Pos',['../group___peripheral___registers___bits___definition.html#ga2541190f9817b863fcaea7925a9ab152',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r1_5ffb0_2179',['CAN_F7R1_FB0',['../group___peripheral___registers___bits___definition.html#ga2217bcc5b82de25751d3984884b0e0c1',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r1_5ffb0_5fmsk_2180',['CAN_F7R1_FB0_Msk',['../group___peripheral___registers___bits___definition.html#gad19ad30a6bd063074a8e787ce24f7d3f',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r1_5ffb0_5fpos_2181',['CAN_F7R1_FB0_Pos',['../group___peripheral___registers___bits___definition.html#ga07592cc9f142c86800624b80ac659191',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r1_5ffb1_2182',['CAN_F7R1_FB1',['../group___peripheral___registers___bits___definition.html#gaf71cbdd5cbe109fde119adb86d64f0a7',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r1_5ffb10_2183',['CAN_F7R1_FB10',['../group___peripheral___registers___bits___definition.html#gaf56408d9914f566396d64609830e2d4f',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r1_5ffb10_5fmsk_2184',['CAN_F7R1_FB10_Msk',['../group___peripheral___registers___bits___definition.html#gad708e8bc52c416ee38bc5bb93822a877',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r1_5ffb10_5fpos_2185',['CAN_F7R1_FB10_Pos',['../group___peripheral___registers___bits___definition.html#ga7e458cf6d5da73505414aa25098d9282',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r1_5ffb11_2186',['CAN_F7R1_FB11',['../group___peripheral___registers___bits___definition.html#ga65947100832111c7fb427d1982f801eb',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r1_5ffb11_5fmsk_2187',['CAN_F7R1_FB11_Msk',['../group___peripheral___registers___bits___definition.html#gad8fa9afddd282899c92a7647e6f1eb8e',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r1_5ffb11_5fpos_2188',['CAN_F7R1_FB11_Pos',['../group___peripheral___registers___bits___definition.html#ga9c05b416f990eebb80363c022661be43',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r1_5ffb12_2189',['CAN_F7R1_FB12',['../group___peripheral___registers___bits___definition.html#ga175ed9cdbbf756ec76b9c6fb1f69adff',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r1_5ffb12_5fmsk_2190',['CAN_F7R1_FB12_Msk',['../group___peripheral___registers___bits___definition.html#gad694f31ad366db83ec659c93fb75db7f',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r1_5ffb12_5fpos_2191',['CAN_F7R1_FB12_Pos',['../group___peripheral___registers___bits___definition.html#gae496f5c9c04aa8d161b380cfc46c1a89',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r1_5ffb13_2192',['CAN_F7R1_FB13',['../group___peripheral___registers___bits___definition.html#ga91af48b8cd11f119d257311dcf2cc291',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r1_5ffb13_5fmsk_2193',['CAN_F7R1_FB13_Msk',['../group___peripheral___registers___bits___definition.html#gafc73cd4c1973c6d575b12ef8a34aefdf',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r1_5ffb13_5fpos_2194',['CAN_F7R1_FB13_Pos',['../group___peripheral___registers___bits___definition.html#ga0706b04b0ddfa96c5ab1120d8973c8fd',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r1_5ffb14_2195',['CAN_F7R1_FB14',['../group___peripheral___registers___bits___definition.html#ga7108bc449a6e328748dd8d2209b83753',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r1_5ffb14_5fmsk_2196',['CAN_F7R1_FB14_Msk',['../group___peripheral___registers___bits___definition.html#gaa51f245c33277eb5e09db8b8302e2df6',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r1_5ffb14_5fpos_2197',['CAN_F7R1_FB14_Pos',['../group___peripheral___registers___bits___definition.html#gace9cd9b7f8196e5831e7a68cc063eabb',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r1_5ffb15_2198',['CAN_F7R1_FB15',['../group___peripheral___registers___bits___definition.html#gacc47acac1bb59603f58d9aef661d9334',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r1_5ffb15_5fmsk_2199',['CAN_F7R1_FB15_Msk',['../group___peripheral___registers___bits___definition.html#ga3dd14c5855dfe51bc8a1a44266d1c925',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r1_5ffb15_5fpos_2200',['CAN_F7R1_FB15_Pos',['../group___peripheral___registers___bits___definition.html#ga6a5c4ef28847f4fa0d27a781b0b8a986',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r1_5ffb16_2201',['CAN_F7R1_FB16',['../group___peripheral___registers___bits___definition.html#ga7b07b4ebfaac9e60d6042b1bff98ec33',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r1_5ffb16_5fmsk_2202',['CAN_F7R1_FB16_Msk',['../group___peripheral___registers___bits___definition.html#gafc661e05b2422313bf88f39f049ce53e',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r1_5ffb16_5fpos_2203',['CAN_F7R1_FB16_Pos',['../group___peripheral___registers___bits___definition.html#ga9d07c069c5aca9e42f268ab32a062c75',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r1_5ffb17_2204',['CAN_F7R1_FB17',['../group___peripheral___registers___bits___definition.html#gad3328e95d8ae911adc0e5dd4128f8161',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r1_5ffb17_5fmsk_2205',['CAN_F7R1_FB17_Msk',['../group___peripheral___registers___bits___definition.html#ga58a27e2e7fd333f0aba9fbd5919e260d',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r1_5ffb17_5fpos_2206',['CAN_F7R1_FB17_Pos',['../group___peripheral___registers___bits___definition.html#ga648db438e1aef7f7b35396757e7c7b52',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r1_5ffb18_2207',['CAN_F7R1_FB18',['../group___peripheral___registers___bits___definition.html#ga473e4917f35772cd08b06e166d6e475e',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r1_5ffb18_5fmsk_2208',['CAN_F7R1_FB18_Msk',['../group___peripheral___registers___bits___definition.html#ga278e31f437817faa9cad12cc69e3112b',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r1_5ffb18_5fpos_2209',['CAN_F7R1_FB18_Pos',['../group___peripheral___registers___bits___definition.html#gaf56090225bc33669e07141a1243cec88',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r1_5ffb19_2210',['CAN_F7R1_FB19',['../group___peripheral___registers___bits___definition.html#gaf40a4dd0979fb7ffba4b4192fe6dde5f',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r1_5ffb19_5fmsk_2211',['CAN_F7R1_FB19_Msk',['../group___peripheral___registers___bits___definition.html#gaf1422787fd4beb2c5679f45908214fd6',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r1_5ffb19_5fpos_2212',['CAN_F7R1_FB19_Pos',['../group___peripheral___registers___bits___definition.html#ga2ab1b958322e9e8924570497657ef396',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r1_5ffb1_5fmsk_2213',['CAN_F7R1_FB1_Msk',['../group___peripheral___registers___bits___definition.html#gab83bdd3955b202a00602bff176ab3cd8',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r1_5ffb1_5fpos_2214',['CAN_F7R1_FB1_Pos',['../group___peripheral___registers___bits___definition.html#gab323a7481c5d75df36e9e2b25c7e6e32',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r1_5ffb2_2215',['CAN_F7R1_FB2',['../group___peripheral___registers___bits___definition.html#gaa0a7a004058a6b10b5cb3374eb82dd1d',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r1_5ffb20_2216',['CAN_F7R1_FB20',['../group___peripheral___registers___bits___definition.html#ga5854aa102655334a6242e43c0b25aede',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r1_5ffb20_5fmsk_2217',['CAN_F7R1_FB20_Msk',['../group___peripheral___registers___bits___definition.html#gad71fb64ea19cf98ac384fed6babe5fdc',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r1_5ffb20_5fpos_2218',['CAN_F7R1_FB20_Pos',['../group___peripheral___registers___bits___definition.html#ga638a9090ca2ae17ea3d000deca166de3',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r1_5ffb21_2219',['CAN_F7R1_FB21',['../group___peripheral___registers___bits___definition.html#ga505dbdeaf89d103795046fb689b81664',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r1_5ffb21_5fmsk_2220',['CAN_F7R1_FB21_Msk',['../group___peripheral___registers___bits___definition.html#ga5c1d29a629499734298ff81b9892cb0a',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r1_5ffb21_5fpos_2221',['CAN_F7R1_FB21_Pos',['../group___peripheral___registers___bits___definition.html#gaacf70e06346fa4c3754533c7743bd04f',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r1_5ffb22_2222',['CAN_F7R1_FB22',['../group___peripheral___registers___bits___definition.html#ga692f7a0bbc73be14e9d554394dceb176',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r1_5ffb22_5fmsk_2223',['CAN_F7R1_FB22_Msk',['../group___peripheral___registers___bits___definition.html#ga4535f6c9da894cc9ef7a6ba6f6bc6525',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r1_5ffb22_5fpos_2224',['CAN_F7R1_FB22_Pos',['../group___peripheral___registers___bits___definition.html#gafcea76ba56f67ee953e46d4a2730b36a',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r1_5ffb23_2225',['CAN_F7R1_FB23',['../group___peripheral___registers___bits___definition.html#ga5a93f243e7acf3f749f2b6ec8ae7bc5f',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r1_5ffb23_5fmsk_2226',['CAN_F7R1_FB23_Msk',['../group___peripheral___registers___bits___definition.html#ga14b9c180bade4dad957697b4f5b4354f',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r1_5ffb23_5fpos_2227',['CAN_F7R1_FB23_Pos',['../group___peripheral___registers___bits___definition.html#ga4853c3d121f3c2d11833d11b395e0038',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r1_5ffb24_2228',['CAN_F7R1_FB24',['../group___peripheral___registers___bits___definition.html#ga68815c969c231268a63c8809a55bc866',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r1_5ffb24_5fmsk_2229',['CAN_F7R1_FB24_Msk',['../group___peripheral___registers___bits___definition.html#ga347cad693a28b872fe402439c9548f35',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r1_5ffb24_5fpos_2230',['CAN_F7R1_FB24_Pos',['../group___peripheral___registers___bits___definition.html#ga3c2567b1837c81aba2759686438547cc',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r1_5ffb25_2231',['CAN_F7R1_FB25',['../group___peripheral___registers___bits___definition.html#ga7055881b4a6d9fe51e8dcfb99a546139',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r1_5ffb25_5fmsk_2232',['CAN_F7R1_FB25_Msk',['../group___peripheral___registers___bits___definition.html#ga2aefee2f7b7c851315fd09a2ef4df5ed',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r1_5ffb25_5fpos_2233',['CAN_F7R1_FB25_Pos',['../group___peripheral___registers___bits___definition.html#gab5867f7e9cb965e6a3768f6bb02f080e',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r1_5ffb26_2234',['CAN_F7R1_FB26',['../group___peripheral___registers___bits___definition.html#ga19ab918d9499635e8199a143833c6fdb',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r1_5ffb26_5fmsk_2235',['CAN_F7R1_FB26_Msk',['../group___peripheral___registers___bits___definition.html#ga8ae7335a105fc044215160bdafda2485',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r1_5ffb26_5fpos_2236',['CAN_F7R1_FB26_Pos',['../group___peripheral___registers___bits___definition.html#gaeb741309bad1c9aef3ede7c187c05a92',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r1_5ffb27_2237',['CAN_F7R1_FB27',['../group___peripheral___registers___bits___definition.html#ga8360f2a2ba21a1b2f361d4330026edfd',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r1_5ffb27_5fmsk_2238',['CAN_F7R1_FB27_Msk',['../group___peripheral___registers___bits___definition.html#gaf1f9cbef574790752e5579402adbfcf9',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r1_5ffb27_5fpos_2239',['CAN_F7R1_FB27_Pos',['../group___peripheral___registers___bits___definition.html#gadae02d56cf4acb7e92586c65c2da805d',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r1_5ffb28_2240',['CAN_F7R1_FB28',['../group___peripheral___registers___bits___definition.html#ga681e922052442801310265bab7356fc4',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r1_5ffb28_5fmsk_2241',['CAN_F7R1_FB28_Msk',['../group___peripheral___registers___bits___definition.html#gab5accb398c1b8d49f33264729b9248ba',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r1_5ffb28_5fpos_2242',['CAN_F7R1_FB28_Pos',['../group___peripheral___registers___bits___definition.html#gab06f238fd2c787b94e9022a874f0e4f7',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r1_5ffb29_2243',['CAN_F7R1_FB29',['../group___peripheral___registers___bits___definition.html#gab12aa3a716a85bf96a1496ecaeae0cec',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r1_5ffb29_5fmsk_2244',['CAN_F7R1_FB29_Msk',['../group___peripheral___registers___bits___definition.html#gaed2a0882ce4432f84db55f3f699cbd93',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r1_5ffb29_5fpos_2245',['CAN_F7R1_FB29_Pos',['../group___peripheral___registers___bits___definition.html#gaec347619871661fb58366eb358f0d3c8',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r1_5ffb2_5fmsk_2246',['CAN_F7R1_FB2_Msk',['../group___peripheral___registers___bits___definition.html#gaffbf82ffead59ec0190dec25b9c8c621',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r1_5ffb2_5fpos_2247',['CAN_F7R1_FB2_Pos',['../group___peripheral___registers___bits___definition.html#ga4b06796d92491cd5111bad5c6c380190',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r1_5ffb3_2248',['CAN_F7R1_FB3',['../group___peripheral___registers___bits___definition.html#ga2224329373b490c8dd4f0c148ef58997',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r1_5ffb30_2249',['CAN_F7R1_FB30',['../group___peripheral___registers___bits___definition.html#ga6774583920f7cd42976daa4cf389eff3',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r1_5ffb30_5fmsk_2250',['CAN_F7R1_FB30_Msk',['../group___peripheral___registers___bits___definition.html#ga63bedd413e3ab8e91f9d779ef40e45b5',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r1_5ffb30_5fpos_2251',['CAN_F7R1_FB30_Pos',['../group___peripheral___registers___bits___definition.html#ga920c885a992444b856bc4df2862f44ae',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r1_5ffb31_2252',['CAN_F7R1_FB31',['../group___peripheral___registers___bits___definition.html#ga9990b9fd20bbe0ff114acace0cb47ad7',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r1_5ffb31_5fmsk_2253',['CAN_F7R1_FB31_Msk',['../group___peripheral___registers___bits___definition.html#gaa85d8f6af8cfade40eaef271291512ef',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r1_5ffb31_5fpos_2254',['CAN_F7R1_FB31_Pos',['../group___peripheral___registers___bits___definition.html#ga099ccfbf473ed4897db9b4d16ac3c150',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r1_5ffb3_5fmsk_2255',['CAN_F7R1_FB3_Msk',['../group___peripheral___registers___bits___definition.html#gab477aa17c626cac52ef965f21579dc69',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r1_5ffb3_5fpos_2256',['CAN_F7R1_FB3_Pos',['../group___peripheral___registers___bits___definition.html#ga548972b3e8900613c72d584ac0550d81',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r1_5ffb4_2257',['CAN_F7R1_FB4',['../group___peripheral___registers___bits___definition.html#gad3574ea4882319ac08e0df065bdd3566',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r1_5ffb4_5fmsk_2258',['CAN_F7R1_FB4_Msk',['../group___peripheral___registers___bits___definition.html#ga4e6552b734a4618cff826b853d8e5ac7',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r1_5ffb4_5fpos_2259',['CAN_F7R1_FB4_Pos',['../group___peripheral___registers___bits___definition.html#ga428d061d3d6cd26401f09a0a9d888582',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r1_5ffb5_2260',['CAN_F7R1_FB5',['../group___peripheral___registers___bits___definition.html#ga76f63e712a9a57dacab2874dd695254d',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r1_5ffb5_5fmsk_2261',['CAN_F7R1_FB5_Msk',['../group___peripheral___registers___bits___definition.html#gad4b90d78121983740c8d803352b68cef',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r1_5ffb5_5fpos_2262',['CAN_F7R1_FB5_Pos',['../group___peripheral___registers___bits___definition.html#ga51f21f5d42dc175f69e397d8a021ec17',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r1_5ffb6_2263',['CAN_F7R1_FB6',['../group___peripheral___registers___bits___definition.html#ga22d969f17f8a25a63cb056ee2cb622d3',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r1_5ffb6_5fmsk_2264',['CAN_F7R1_FB6_Msk',['../group___peripheral___registers___bits___definition.html#ga0e3a549c7bf229dda892b600b320b4e0',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r1_5ffb6_5fpos_2265',['CAN_F7R1_FB6_Pos',['../group___peripheral___registers___bits___definition.html#gafaf5d52b07d0fb670d7b754f293193b2',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r1_5ffb7_2266',['CAN_F7R1_FB7',['../group___peripheral___registers___bits___definition.html#gaae89ec51b51c83c108880e361caf17ac',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r1_5ffb7_5fmsk_2267',['CAN_F7R1_FB7_Msk',['../group___peripheral___registers___bits___definition.html#gafb8ad36251e272dd1487dfec8f4b6cfd',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r1_5ffb7_5fpos_2268',['CAN_F7R1_FB7_Pos',['../group___peripheral___registers___bits___definition.html#ga85318a4750085acc0f67eaf5d748f0b0',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r1_5ffb8_2269',['CAN_F7R1_FB8',['../group___peripheral___registers___bits___definition.html#ga67fca99c67cab6713605e14d96a9df62',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r1_5ffb8_5fmsk_2270',['CAN_F7R1_FB8_Msk',['../group___peripheral___registers___bits___definition.html#gad2be453e8e7320b77bc242044038ab02',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r1_5ffb8_5fpos_2271',['CAN_F7R1_FB8_Pos',['../group___peripheral___registers___bits___definition.html#gad3977b859e97377959d730d66dba4cea',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r1_5ffb9_2272',['CAN_F7R1_FB9',['../group___peripheral___registers___bits___definition.html#gaacd1ef8f0870bc5a5422a6bedbb61d40',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r1_5ffb9_5fmsk_2273',['CAN_F7R1_FB9_Msk',['../group___peripheral___registers___bits___definition.html#ga271c074cc3a12f895a531d0cfb29a883',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r1_5ffb9_5fpos_2274',['CAN_F7R1_FB9_Pos',['../group___peripheral___registers___bits___definition.html#ga8aaaf940b9f64ff8cf14a1ccb1f01353',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r2_5ffb0_2275',['CAN_F7R2_FB0',['../group___peripheral___registers___bits___definition.html#gaec0803330590bf9aba9d09342034b2c1',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r2_5ffb0_5fmsk_2276',['CAN_F7R2_FB0_Msk',['../group___peripheral___registers___bits___definition.html#gaa7e6ac71d87a53fb60da7f7d7bb4a31c',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r2_5ffb0_5fpos_2277',['CAN_F7R2_FB0_Pos',['../group___peripheral___registers___bits___definition.html#ga5f4317b3af8e10a0d4b70433d705208f',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r2_5ffb1_2278',['CAN_F7R2_FB1',['../group___peripheral___registers___bits___definition.html#ga8c633d4cbfdf79f09ae1df5e75c98439',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r2_5ffb10_2279',['CAN_F7R2_FB10',['../group___peripheral___registers___bits___definition.html#gaae60d566699df87580584ed496681562',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r2_5ffb10_5fmsk_2280',['CAN_F7R2_FB10_Msk',['../group___peripheral___registers___bits___definition.html#ga81766a9d745aeadd4ba0a34d3ded18e7',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r2_5ffb10_5fpos_2281',['CAN_F7R2_FB10_Pos',['../group___peripheral___registers___bits___definition.html#ga1bc252c24c4748c4596a5fbd9bcff7b1',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r2_5ffb11_2282',['CAN_F7R2_FB11',['../group___peripheral___registers___bits___definition.html#ga6325b37cc369b92b2334e482dbe3bf06',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r2_5ffb11_5fmsk_2283',['CAN_F7R2_FB11_Msk',['../group___peripheral___registers___bits___definition.html#ga33730db505f710ba327f8c6c1f04da4f',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r2_5ffb11_5fpos_2284',['CAN_F7R2_FB11_Pos',['../group___peripheral___registers___bits___definition.html#ga14f3c2bf58159e154369752dae336477',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r2_5ffb12_2285',['CAN_F7R2_FB12',['../group___peripheral___registers___bits___definition.html#gace846d293ac11d535ee2aad17cf099bc',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r2_5ffb12_5fmsk_2286',['CAN_F7R2_FB12_Msk',['../group___peripheral___registers___bits___definition.html#ga02c278c9bfd9314c34ac6da260c08403',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r2_5ffb12_5fpos_2287',['CAN_F7R2_FB12_Pos',['../group___peripheral___registers___bits___definition.html#gaf1f505ec544d393c5f905b294bce4401',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r2_5ffb13_2288',['CAN_F7R2_FB13',['../group___peripheral___registers___bits___definition.html#ga91b26397a75fc4c0124e84903d31221e',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r2_5ffb13_5fmsk_2289',['CAN_F7R2_FB13_Msk',['../group___peripheral___registers___bits___definition.html#ga40fec0160eec943f81f05ad9d48ce9b2',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r2_5ffb13_5fpos_2290',['CAN_F7R2_FB13_Pos',['../group___peripheral___registers___bits___definition.html#gac30df90b8299022e421c729f7088cf11',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r2_5ffb14_2291',['CAN_F7R2_FB14',['../group___peripheral___registers___bits___definition.html#gada2e01c05c216ba6ff4756d043297c0e',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r2_5ffb14_5fmsk_2292',['CAN_F7R2_FB14_Msk',['../group___peripheral___registers___bits___definition.html#ga906faed52246a867bbe9675b588c2fe0',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r2_5ffb14_5fpos_2293',['CAN_F7R2_FB14_Pos',['../group___peripheral___registers___bits___definition.html#gad8eb41c28b8059b9d0f25f05341cff65',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r2_5ffb15_2294',['CAN_F7R2_FB15',['../group___peripheral___registers___bits___definition.html#gaeef08aa6565ff24bd9863b4b8a9c2ff5',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r2_5ffb15_5fmsk_2295',['CAN_F7R2_FB15_Msk',['../group___peripheral___registers___bits___definition.html#gacf54c82654d230ba010300b9b879f606',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r2_5ffb15_5fpos_2296',['CAN_F7R2_FB15_Pos',['../group___peripheral___registers___bits___definition.html#ga66ab5a2d62ff7650618d15f893046efa',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r2_5ffb16_2297',['CAN_F7R2_FB16',['../group___peripheral___registers___bits___definition.html#ga16c3ccb033b9541b57c338b9737f18dd',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r2_5ffb16_5fmsk_2298',['CAN_F7R2_FB16_Msk',['../group___peripheral___registers___bits___definition.html#gac23ba211219c2ece524f3867e2b1cc4e',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r2_5ffb16_5fpos_2299',['CAN_F7R2_FB16_Pos',['../group___peripheral___registers___bits___definition.html#ga14b6874b4f61096d8e2f21efddb07831',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r2_5ffb17_2300',['CAN_F7R2_FB17',['../group___peripheral___registers___bits___definition.html#gad898ca382f57efb1842884d46217245c',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r2_5ffb17_5fmsk_2301',['CAN_F7R2_FB17_Msk',['../group___peripheral___registers___bits___definition.html#ga714ba087c8c662749a5e1db9f82af81d',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r2_5ffb17_5fpos_2302',['CAN_F7R2_FB17_Pos',['../group___peripheral___registers___bits___definition.html#ga9070f003ab14a0a9e619c82acc6d357f',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r2_5ffb18_2303',['CAN_F7R2_FB18',['../group___peripheral___registers___bits___definition.html#gaf419938e132cc1a0bf59a6c058e2c7c5',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r2_5ffb18_5fmsk_2304',['CAN_F7R2_FB18_Msk',['../group___peripheral___registers___bits___definition.html#ga228a38b1060b3ff498d35aed4e128917',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r2_5ffb18_5fpos_2305',['CAN_F7R2_FB18_Pos',['../group___peripheral___registers___bits___definition.html#ga69277e05f3cfeb8c75d9b008c7db5d37',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r2_5ffb19_2306',['CAN_F7R2_FB19',['../group___peripheral___registers___bits___definition.html#gae991abb6f2e64443be7e39633f192aba',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r2_5ffb19_5fmsk_2307',['CAN_F7R2_FB19_Msk',['../group___peripheral___registers___bits___definition.html#gaa4893f06f2a927a5e1a38e9faf3edb90',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r2_5ffb19_5fpos_2308',['CAN_F7R2_FB19_Pos',['../group___peripheral___registers___bits___definition.html#gab6251821d862bf793711e13753c7ae5a',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r2_5ffb1_5fmsk_2309',['CAN_F7R2_FB1_Msk',['../group___peripheral___registers___bits___definition.html#gac046be844d45ddd93b750c2b3fdeffb5',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r2_5ffb1_5fpos_2310',['CAN_F7R2_FB1_Pos',['../group___peripheral___registers___bits___definition.html#ga24c69591a6d5b2f86f6e57027640dd73',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r2_5ffb2_2311',['CAN_F7R2_FB2',['../group___peripheral___registers___bits___definition.html#ga31a0c4ece8b73760ad295344b8558ddb',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r2_5ffb20_2312',['CAN_F7R2_FB20',['../group___peripheral___registers___bits___definition.html#ga3738a42e2767c928de21a2f784ce6bce',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r2_5ffb20_5fmsk_2313',['CAN_F7R2_FB20_Msk',['../group___peripheral___registers___bits___definition.html#ga9074bda7aca4edf2e11e8125a57cbc5a',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r2_5ffb20_5fpos_2314',['CAN_F7R2_FB20_Pos',['../group___peripheral___registers___bits___definition.html#gacb34c2b052df01aa362473d670d42ed0',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r2_5ffb21_2315',['CAN_F7R2_FB21',['../group___peripheral___registers___bits___definition.html#gae5cb252582e6b7bd706b37447f71d6cd',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r2_5ffb21_5fmsk_2316',['CAN_F7R2_FB21_Msk',['../group___peripheral___registers___bits___definition.html#gaa8dacdf1e167c8a3f7509e4ddf5757e1',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r2_5ffb21_5fpos_2317',['CAN_F7R2_FB21_Pos',['../group___peripheral___registers___bits___definition.html#ga2d955eb8acf2decac2bd58e6746fd407',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r2_5ffb22_2318',['CAN_F7R2_FB22',['../group___peripheral___registers___bits___definition.html#gae616e53b9d961571eea4ff2df31f8399',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r2_5ffb22_5fmsk_2319',['CAN_F7R2_FB22_Msk',['../group___peripheral___registers___bits___definition.html#gad37f85aab2fa384e5d0643b17eae8440',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r2_5ffb22_5fpos_2320',['CAN_F7R2_FB22_Pos',['../group___peripheral___registers___bits___definition.html#gade58525a8af1d2246aea9a8f494dc3a7',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r2_5ffb23_2321',['CAN_F7R2_FB23',['../group___peripheral___registers___bits___definition.html#gab2049c9bb27af3cde01334b1901aa417',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r2_5ffb23_5fmsk_2322',['CAN_F7R2_FB23_Msk',['../group___peripheral___registers___bits___definition.html#gad01aed48c87877406fcd8a0da994b8b6',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r2_5ffb23_5fpos_2323',['CAN_F7R2_FB23_Pos',['../group___peripheral___registers___bits___definition.html#gaa07aee43f61765d654ba4f1a965c3d15',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r2_5ffb24_2324',['CAN_F7R2_FB24',['../group___peripheral___registers___bits___definition.html#ga8e69c2fd32e2c523c9e939df825fc605',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r2_5ffb24_5fmsk_2325',['CAN_F7R2_FB24_Msk',['../group___peripheral___registers___bits___definition.html#ga3274b8fc32c7104c1ae6015fe725c63b',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r2_5ffb24_5fpos_2326',['CAN_F7R2_FB24_Pos',['../group___peripheral___registers___bits___definition.html#gaed455c42e4814928236cee53101a2863',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r2_5ffb25_2327',['CAN_F7R2_FB25',['../group___peripheral___registers___bits___definition.html#ga659cc84b9186e279c37e88b94e1c9829',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r2_5ffb25_5fmsk_2328',['CAN_F7R2_FB25_Msk',['../group___peripheral___registers___bits___definition.html#ga9ee9ad1b18fe010798526b61b23773b7',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r2_5ffb25_5fpos_2329',['CAN_F7R2_FB25_Pos',['../group___peripheral___registers___bits___definition.html#gaebdd728474eecad67ed5816c533f575b',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r2_5ffb26_2330',['CAN_F7R2_FB26',['../group___peripheral___registers___bits___definition.html#ga43c9da5ad4c2d261858f73b779cc3dae',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r2_5ffb26_5fmsk_2331',['CAN_F7R2_FB26_Msk',['../group___peripheral___registers___bits___definition.html#ga649a2979cf8c968b94a82ade9eb7aa77',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r2_5ffb26_5fpos_2332',['CAN_F7R2_FB26_Pos',['../group___peripheral___registers___bits___definition.html#ga68cc77bf1d501625c5e639909e29c118',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r2_5ffb27_2333',['CAN_F7R2_FB27',['../group___peripheral___registers___bits___definition.html#ga0a1ea8d66ada6cea7268fba151c00d91',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r2_5ffb27_5fmsk_2334',['CAN_F7R2_FB27_Msk',['../group___peripheral___registers___bits___definition.html#ga005b8dfa3d1f6eb19c33deed337fab12',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r2_5ffb27_5fpos_2335',['CAN_F7R2_FB27_Pos',['../group___peripheral___registers___bits___definition.html#ga5d61a9597fe302aa59b1bf6944f69aad',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r2_5ffb28_2336',['CAN_F7R2_FB28',['../group___peripheral___registers___bits___definition.html#gabbd6032652515423412ad73b8a004bbb',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r2_5ffb28_5fmsk_2337',['CAN_F7R2_FB28_Msk',['../group___peripheral___registers___bits___definition.html#gadaa906c94d6d83a7a5c1d8645e814fa3',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r2_5ffb28_5fpos_2338',['CAN_F7R2_FB28_Pos',['../group___peripheral___registers___bits___definition.html#ga317154057e36bcfb50408ffa8c106559',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r2_5ffb29_2339',['CAN_F7R2_FB29',['../group___peripheral___registers___bits___definition.html#ga3a991a0bb5a81748b091d6b96c59fc37',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r2_5ffb29_5fmsk_2340',['CAN_F7R2_FB29_Msk',['../group___peripheral___registers___bits___definition.html#gabd1f2f87a2de3ef977b9f042559110f7',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r2_5ffb29_5fpos_2341',['CAN_F7R2_FB29_Pos',['../group___peripheral___registers___bits___definition.html#ga5ed2a1e8330f343d50d3ead9b7426715',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r2_5ffb2_5fmsk_2342',['CAN_F7R2_FB2_Msk',['../group___peripheral___registers___bits___definition.html#gae222910542a55154e8b02affd43c1bb1',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r2_5ffb2_5fpos_2343',['CAN_F7R2_FB2_Pos',['../group___peripheral___registers___bits___definition.html#ga91c5dc8630c3f5d987bdbd9000dbde85',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r2_5ffb3_2344',['CAN_F7R2_FB3',['../group___peripheral___registers___bits___definition.html#gafe2fc15309540b87538ea3e8460d8d11',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r2_5ffb30_2345',['CAN_F7R2_FB30',['../group___peripheral___registers___bits___definition.html#gaedae5e816af0dd734311bf44be7571f2',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r2_5ffb30_5fmsk_2346',['CAN_F7R2_FB30_Msk',['../group___peripheral___registers___bits___definition.html#gac67c413d3294aa6762edf76c05352d13',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r2_5ffb30_5fpos_2347',['CAN_F7R2_FB30_Pos',['../group___peripheral___registers___bits___definition.html#gaa60296ad3c0c0597363499038128c431',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r2_5ffb31_2348',['CAN_F7R2_FB31',['../group___peripheral___registers___bits___definition.html#ga2f88a239b8a39ff3343b1cfe70b06139',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r2_5ffb31_5fmsk_2349',['CAN_F7R2_FB31_Msk',['../group___peripheral___registers___bits___definition.html#ga0d0df32a1bad3f616506614c53de9a18',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r2_5ffb31_5fpos_2350',['CAN_F7R2_FB31_Pos',['../group___peripheral___registers___bits___definition.html#ga0b8852c12eaf0286767bf738087f5774',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r2_5ffb3_5fmsk_2351',['CAN_F7R2_FB3_Msk',['../group___peripheral___registers___bits___definition.html#gaf47bc62b248184ab11796b147fd12fa4',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r2_5ffb3_5fpos_2352',['CAN_F7R2_FB3_Pos',['../group___peripheral___registers___bits___definition.html#ga86e2b7893638f3661915edb722d2adde',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r2_5ffb4_2353',['CAN_F7R2_FB4',['../group___peripheral___registers___bits___definition.html#gac81d4c021f4579021ddf9485472a84f5',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r2_5ffb4_5fmsk_2354',['CAN_F7R2_FB4_Msk',['../group___peripheral___registers___bits___definition.html#ga6532dbd923dbc1ae43394d64065b01f9',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r2_5ffb4_5fpos_2355',['CAN_F7R2_FB4_Pos',['../group___peripheral___registers___bits___definition.html#gaf8f96b4a3fa62b12e2529a91b67f1f4c',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r2_5ffb5_2356',['CAN_F7R2_FB5',['../group___peripheral___registers___bits___definition.html#ga5dd6a00bb403a3e19e66c68f5ee308e2',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r2_5ffb5_5fmsk_2357',['CAN_F7R2_FB5_Msk',['../group___peripheral___registers___bits___definition.html#ga791664168f6ee37eea4331bf0f17f878',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r2_5ffb5_5fpos_2358',['CAN_F7R2_FB5_Pos',['../group___peripheral___registers___bits___definition.html#ga996bd937bc577755b88acdaee8493640',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r2_5ffb6_2359',['CAN_F7R2_FB6',['../group___peripheral___registers___bits___definition.html#ga9b5eaf37458d0426fd7f847775fd41e9',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r2_5ffb6_5fmsk_2360',['CAN_F7R2_FB6_Msk',['../group___peripheral___registers___bits___definition.html#ga4f12b37158633c7274a01feacbf342c6',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r2_5ffb6_5fpos_2361',['CAN_F7R2_FB6_Pos',['../group___peripheral___registers___bits___definition.html#ga7fcf07c4563ff3e099d9d88926d135d5',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r2_5ffb7_2362',['CAN_F7R2_FB7',['../group___peripheral___registers___bits___definition.html#ga780440ce173cde12fd117b519419424c',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r2_5ffb7_5fmsk_2363',['CAN_F7R2_FB7_Msk',['../group___peripheral___registers___bits___definition.html#gae323bdff49096a4afee6dec3d9d9aebd',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r2_5ffb7_5fpos_2364',['CAN_F7R2_FB7_Pos',['../group___peripheral___registers___bits___definition.html#gafe34ced987191e7acda093c4b726148d',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r2_5ffb8_2365',['CAN_F7R2_FB8',['../group___peripheral___registers___bits___definition.html#ga99ae0e27d14b42fef4551d83ee88b4ac',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r2_5ffb8_5fmsk_2366',['CAN_F7R2_FB8_Msk',['../group___peripheral___registers___bits___definition.html#ga5ec8c5b0a88b30a17f9afb284bcc95c1',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r2_5ffb8_5fpos_2367',['CAN_F7R2_FB8_Pos',['../group___peripheral___registers___bits___definition.html#ga1c5cd0875fa5ecc52ab306eb47020388',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r2_5ffb9_2368',['CAN_F7R2_FB9',['../group___peripheral___registers___bits___definition.html#gace90c0624446480421fac233739413dc',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r2_5ffb9_5fmsk_2369',['CAN_F7R2_FB9_Msk',['../group___peripheral___registers___bits___definition.html#gaaf18ed7d215a3e4a3ebbca297626877c',1,'stm32f407xx_matlab.h']]], - ['can_5ff7r2_5ffb9_5fpos_2370',['CAN_F7R2_FB9_Pos',['../group___peripheral___registers___bits___definition.html#gae07c159d533af5bd5d2a6733db52e400',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r1_5ffb0_2371',['CAN_F8R1_FB0',['../group___peripheral___registers___bits___definition.html#ga13cd870005a4712c3a8b9675a962c642',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r1_5ffb0_5fmsk_2372',['CAN_F8R1_FB0_Msk',['../group___peripheral___registers___bits___definition.html#ga43a1537e2aeed84464aed2c398cb24c5',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r1_5ffb0_5fpos_2373',['CAN_F8R1_FB0_Pos',['../group___peripheral___registers___bits___definition.html#ga2e21006790f44d0394235edb9533fe9f',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r1_5ffb1_2374',['CAN_F8R1_FB1',['../group___peripheral___registers___bits___definition.html#ga49082d55960382ded8b2f7235dd3b33d',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r1_5ffb10_2375',['CAN_F8R1_FB10',['../group___peripheral___registers___bits___definition.html#gab5de7f304ca7bfcb9e78c9c2d346d300',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r1_5ffb10_5fmsk_2376',['CAN_F8R1_FB10_Msk',['../group___peripheral___registers___bits___definition.html#ga250ae96856872467bd01177a14cbd757',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r1_5ffb10_5fpos_2377',['CAN_F8R1_FB10_Pos',['../group___peripheral___registers___bits___definition.html#gad9d988713272210141906dbbf7c86e9a',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r1_5ffb11_2378',['CAN_F8R1_FB11',['../group___peripheral___registers___bits___definition.html#ga0d5a19fa7032ef2b68e2feebd0db15e6',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r1_5ffb11_5fmsk_2379',['CAN_F8R1_FB11_Msk',['../group___peripheral___registers___bits___definition.html#ga8f936dea8e23ad47f01a690e3144442c',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r1_5ffb11_5fpos_2380',['CAN_F8R1_FB11_Pos',['../group___peripheral___registers___bits___definition.html#ga0b1a8d858999311a306e931621b57f21',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r1_5ffb12_2381',['CAN_F8R1_FB12',['../group___peripheral___registers___bits___definition.html#ga943a685663474ed7aa509eaccbda2ffb',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r1_5ffb12_5fmsk_2382',['CAN_F8R1_FB12_Msk',['../group___peripheral___registers___bits___definition.html#gad340588e0f2e4424892bf86a3df02297',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r1_5ffb12_5fpos_2383',['CAN_F8R1_FB12_Pos',['../group___peripheral___registers___bits___definition.html#ga6dee94be5857587a290a91b8e69ebd75',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r1_5ffb13_2384',['CAN_F8R1_FB13',['../group___peripheral___registers___bits___definition.html#ga668cb8a75c4166b5287a09ba98c8ec70',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r1_5ffb13_5fmsk_2385',['CAN_F8R1_FB13_Msk',['../group___peripheral___registers___bits___definition.html#ga38c0634095cd3178f8b2836d6855d3f3',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r1_5ffb13_5fpos_2386',['CAN_F8R1_FB13_Pos',['../group___peripheral___registers___bits___definition.html#gaaa36fb31c4e4460571555e84cb306cf0',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r1_5ffb14_2387',['CAN_F8R1_FB14',['../group___peripheral___registers___bits___definition.html#ga84727d6a0fdcb2870529d7a371a0b660',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r1_5ffb14_5fmsk_2388',['CAN_F8R1_FB14_Msk',['../group___peripheral___registers___bits___definition.html#gaac0c83e006384165f5d1cb982728cc50',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r1_5ffb14_5fpos_2389',['CAN_F8R1_FB14_Pos',['../group___peripheral___registers___bits___definition.html#gaf6c42fee1e932aebc586aa5cfa634be5',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r1_5ffb15_2390',['CAN_F8R1_FB15',['../group___peripheral___registers___bits___definition.html#ga9eb9c851eb03c49bc02f686aee490a28',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r1_5ffb15_5fmsk_2391',['CAN_F8R1_FB15_Msk',['../group___peripheral___registers___bits___definition.html#ga42f23b1489ef4904d4f0a629f4fff1da',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r1_5ffb15_5fpos_2392',['CAN_F8R1_FB15_Pos',['../group___peripheral___registers___bits___definition.html#ga1b62ff2f6a779932be13dfa2eba51c8c',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r1_5ffb16_2393',['CAN_F8R1_FB16',['../group___peripheral___registers___bits___definition.html#ga4ccc46770c70da8546bbbcf492bcdd95',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r1_5ffb16_5fmsk_2394',['CAN_F8R1_FB16_Msk',['../group___peripheral___registers___bits___definition.html#ga98a05e0a87d907888aed8f07c72d00f9',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r1_5ffb16_5fpos_2395',['CAN_F8R1_FB16_Pos',['../group___peripheral___registers___bits___definition.html#gaab6b2bfaa28bb99475c1ffe09c55bedb',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r1_5ffb17_2396',['CAN_F8R1_FB17',['../group___peripheral___registers___bits___definition.html#gaf24b0628e89b2c27cb9e13b0492876eb',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r1_5ffb17_5fmsk_2397',['CAN_F8R1_FB17_Msk',['../group___peripheral___registers___bits___definition.html#ga0b5980d9a8107fa12b63f1ee0abe74cd',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r1_5ffb17_5fpos_2398',['CAN_F8R1_FB17_Pos',['../group___peripheral___registers___bits___definition.html#gae3e73d311df6235cbf5fc02a800628db',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r1_5ffb18_2399',['CAN_F8R1_FB18',['../group___peripheral___registers___bits___definition.html#ga36b946c123c3c3f1cdbd1272db24c58b',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r1_5ffb18_5fmsk_2400',['CAN_F8R1_FB18_Msk',['../group___peripheral___registers___bits___definition.html#gae850211d9876f0063e13b5610cf8ac65',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r1_5ffb18_5fpos_2401',['CAN_F8R1_FB18_Pos',['../group___peripheral___registers___bits___definition.html#gaf59f6130156da5081b0eee3acb154374',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r1_5ffb19_2402',['CAN_F8R1_FB19',['../group___peripheral___registers___bits___definition.html#gab91129b8b7746111a31a968c1f1a8b19',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r1_5ffb19_5fmsk_2403',['CAN_F8R1_FB19_Msk',['../group___peripheral___registers___bits___definition.html#ga666296673c08dd22ca95dab553d430ef',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r1_5ffb19_5fpos_2404',['CAN_F8R1_FB19_Pos',['../group___peripheral___registers___bits___definition.html#ga0fe27087a9da8f3202a319dbaf07b6d6',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r1_5ffb1_5fmsk_2405',['CAN_F8R1_FB1_Msk',['../group___peripheral___registers___bits___definition.html#ga136ab0937c4919934d7dc1185d3c4064',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r1_5ffb1_5fpos_2406',['CAN_F8R1_FB1_Pos',['../group___peripheral___registers___bits___definition.html#gab537c0b3bf184ffb31d73312facd8d44',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r1_5ffb2_2407',['CAN_F8R1_FB2',['../group___peripheral___registers___bits___definition.html#gafdb99f376b40d3933ce6a28ad31f496a',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r1_5ffb20_2408',['CAN_F8R1_FB20',['../group___peripheral___registers___bits___definition.html#ga19663b29868ae926896961451768d748',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r1_5ffb20_5fmsk_2409',['CAN_F8R1_FB20_Msk',['../group___peripheral___registers___bits___definition.html#ga82b241f62e465fede05a749af4f6d46d',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r1_5ffb20_5fpos_2410',['CAN_F8R1_FB20_Pos',['../group___peripheral___registers___bits___definition.html#ga55046c532cef29a6df857a821d8d9750',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r1_5ffb21_2411',['CAN_F8R1_FB21',['../group___peripheral___registers___bits___definition.html#ga19d8c89621a78de5177481d217bb5033',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r1_5ffb21_5fmsk_2412',['CAN_F8R1_FB21_Msk',['../group___peripheral___registers___bits___definition.html#ga894777fbc3a4cfc64d779ee1bb28447a',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r1_5ffb21_5fpos_2413',['CAN_F8R1_FB21_Pos',['../group___peripheral___registers___bits___definition.html#gaef11cb2b0be6f8a07ca34699c89a7098',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r1_5ffb22_2414',['CAN_F8R1_FB22',['../group___peripheral___registers___bits___definition.html#gab265fadfeb8674b869264ad25bedcac4',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r1_5ffb22_5fmsk_2415',['CAN_F8R1_FB22_Msk',['../group___peripheral___registers___bits___definition.html#ga95a971879dd5369d39b1b5a2d55af7f2',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r1_5ffb22_5fpos_2416',['CAN_F8R1_FB22_Pos',['../group___peripheral___registers___bits___definition.html#ga44d6b1387dd6af3f5f6ad71dc57738bb',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r1_5ffb23_2417',['CAN_F8R1_FB23',['../group___peripheral___registers___bits___definition.html#ga102fdb92fecd6aa86e5dbd2fea2b2e79',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r1_5ffb23_5fmsk_2418',['CAN_F8R1_FB23_Msk',['../group___peripheral___registers___bits___definition.html#ga7c136499422980d6a619619b67024115',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r1_5ffb23_5fpos_2419',['CAN_F8R1_FB23_Pos',['../group___peripheral___registers___bits___definition.html#ga928556e1ce80afd85bc49deca2f1dc2a',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r1_5ffb24_2420',['CAN_F8R1_FB24',['../group___peripheral___registers___bits___definition.html#ga0b73f4ab4941e6d920e75f7197ed025b',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r1_5ffb24_5fmsk_2421',['CAN_F8R1_FB24_Msk',['../group___peripheral___registers___bits___definition.html#gad5cb63c9cc186f5a6a188e50e9440b71',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r1_5ffb24_5fpos_2422',['CAN_F8R1_FB24_Pos',['../group___peripheral___registers___bits___definition.html#ga6287f1cbffc6c85b5a8c540bdd238dd1',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r1_5ffb25_2423',['CAN_F8R1_FB25',['../group___peripheral___registers___bits___definition.html#ga9d72a1b4728fa13d4a2a3f7478f8398b',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r1_5ffb25_5fmsk_2424',['CAN_F8R1_FB25_Msk',['../group___peripheral___registers___bits___definition.html#gad66fb66d8e41424f6a5df8645e889aed',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r1_5ffb25_5fpos_2425',['CAN_F8R1_FB25_Pos',['../group___peripheral___registers___bits___definition.html#ga5b42664c93972b8ceef0bb224465868a',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r1_5ffb26_2426',['CAN_F8R1_FB26',['../group___peripheral___registers___bits___definition.html#ga5826d272442cf9b69336172a039bc439',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r1_5ffb26_5fmsk_2427',['CAN_F8R1_FB26_Msk',['../group___peripheral___registers___bits___definition.html#ga4e4ac7b030b72119e7ff52cd7ed2c22b',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r1_5ffb26_5fpos_2428',['CAN_F8R1_FB26_Pos',['../group___peripheral___registers___bits___definition.html#ga4046289146213969c12a1a9c88756853',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r1_5ffb27_2429',['CAN_F8R1_FB27',['../group___peripheral___registers___bits___definition.html#gacdb656881f89c0da122383403a816ce1',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r1_5ffb27_5fmsk_2430',['CAN_F8R1_FB27_Msk',['../group___peripheral___registers___bits___definition.html#ga36df86343d04760bb4fef8b027e668d6',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r1_5ffb27_5fpos_2431',['CAN_F8R1_FB27_Pos',['../group___peripheral___registers___bits___definition.html#ga32f7d4b16bb82b31e2fb4879e64a7632',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r1_5ffb28_2432',['CAN_F8R1_FB28',['../group___peripheral___registers___bits___definition.html#ga2d8c536aab73553ff1913ba806be351c',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r1_5ffb28_5fmsk_2433',['CAN_F8R1_FB28_Msk',['../group___peripheral___registers___bits___definition.html#ga647ae349a353febc85e2d06384798e35',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r1_5ffb28_5fpos_2434',['CAN_F8R1_FB28_Pos',['../group___peripheral___registers___bits___definition.html#ga7d24f22e4e970b13528482d65e0bcd21',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r1_5ffb29_2435',['CAN_F8R1_FB29',['../group___peripheral___registers___bits___definition.html#ga8fb8328cdbf23c9982b769bd39a24113',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r1_5ffb29_5fmsk_2436',['CAN_F8R1_FB29_Msk',['../group___peripheral___registers___bits___definition.html#gaaddb3d32fc778601342a863d0a6612f5',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r1_5ffb29_5fpos_2437',['CAN_F8R1_FB29_Pos',['../group___peripheral___registers___bits___definition.html#ga270dce4d4b698b43b0f9eed16a95b336',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r1_5ffb2_5fmsk_2438',['CAN_F8R1_FB2_Msk',['../group___peripheral___registers___bits___definition.html#gab9fac3bd96ed91e471081a51b6b08ca3',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r1_5ffb2_5fpos_2439',['CAN_F8R1_FB2_Pos',['../group___peripheral___registers___bits___definition.html#ga6d30a98a695d270dbff8e07b9079e5d8',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r1_5ffb3_2440',['CAN_F8R1_FB3',['../group___peripheral___registers___bits___definition.html#ga2cd97fc37fa6ffadbb7af4f9ddf1d014',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r1_5ffb30_2441',['CAN_F8R1_FB30',['../group___peripheral___registers___bits___definition.html#ga78861665c78657330f9fcfc17283529f',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r1_5ffb30_5fmsk_2442',['CAN_F8R1_FB30_Msk',['../group___peripheral___registers___bits___definition.html#gae8cfc8c264df5fef0511b3cd66e459c3',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r1_5ffb30_5fpos_2443',['CAN_F8R1_FB30_Pos',['../group___peripheral___registers___bits___definition.html#ga1ac7d47b043f02ea1fe15f4ed1ea69ea',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r1_5ffb31_2444',['CAN_F8R1_FB31',['../group___peripheral___registers___bits___definition.html#ga6b2fa38175302b2d91f2b45ae16c5db7',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r1_5ffb31_5fmsk_2445',['CAN_F8R1_FB31_Msk',['../group___peripheral___registers___bits___definition.html#gacf1306a969e63813c78f15304cfeef9d',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r1_5ffb31_5fpos_2446',['CAN_F8R1_FB31_Pos',['../group___peripheral___registers___bits___definition.html#ga85f280f7adb7d1b1f1a2fd964496d382',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r1_5ffb3_5fmsk_2447',['CAN_F8R1_FB3_Msk',['../group___peripheral___registers___bits___definition.html#gaa5b9c8ec036840da8f0b04aaa715d031',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r1_5ffb3_5fpos_2448',['CAN_F8R1_FB3_Pos',['../group___peripheral___registers___bits___definition.html#gaa1894d0455f9488198430c70db97c865',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r1_5ffb4_2449',['CAN_F8R1_FB4',['../group___peripheral___registers___bits___definition.html#ga5842614b55172086992fc085955168d7',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r1_5ffb4_5fmsk_2450',['CAN_F8R1_FB4_Msk',['../group___peripheral___registers___bits___definition.html#gab9829df8a13336ccf61d59be6c282d52',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r1_5ffb4_5fpos_2451',['CAN_F8R1_FB4_Pos',['../group___peripheral___registers___bits___definition.html#ga1a0ded25fe64917e6868d95b1d468771',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r1_5ffb5_2452',['CAN_F8R1_FB5',['../group___peripheral___registers___bits___definition.html#ga373c77cab88912e816a6e12195bd3205',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r1_5ffb5_5fmsk_2453',['CAN_F8R1_FB5_Msk',['../group___peripheral___registers___bits___definition.html#ga70d67631dbfe1a1f15fb712df7cca4d8',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r1_5ffb5_5fpos_2454',['CAN_F8R1_FB5_Pos',['../group___peripheral___registers___bits___definition.html#ga5792df4298b71222586c057d8c783ed2',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r1_5ffb6_2455',['CAN_F8R1_FB6',['../group___peripheral___registers___bits___definition.html#ga5937607627dd44c4fb79f9063534e2b1',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r1_5ffb6_5fmsk_2456',['CAN_F8R1_FB6_Msk',['../group___peripheral___registers___bits___definition.html#gaf1d9da45066db64dcc7b6d6ea9d8d3f8',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r1_5ffb6_5fpos_2457',['CAN_F8R1_FB6_Pos',['../group___peripheral___registers___bits___definition.html#ga28d2bdc498bb762e71c06682ddcffcd0',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r1_5ffb7_2458',['CAN_F8R1_FB7',['../group___peripheral___registers___bits___definition.html#ga5b6765194a47f1a6d7dfbf78e0b4139c',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r1_5ffb7_5fmsk_2459',['CAN_F8R1_FB7_Msk',['../group___peripheral___registers___bits___definition.html#ga14a2fe60539e333588226dbc4de4fffa',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r1_5ffb7_5fpos_2460',['CAN_F8R1_FB7_Pos',['../group___peripheral___registers___bits___definition.html#ga40a3d24b2ddf64251f6257500549eb78',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r1_5ffb8_2461',['CAN_F8R1_FB8',['../group___peripheral___registers___bits___definition.html#gaa79159b413994d12b593cc4f1b23d1fa',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r1_5ffb8_5fmsk_2462',['CAN_F8R1_FB8_Msk',['../group___peripheral___registers___bits___definition.html#ga3f57e77aa8ea032bc07463d82e451e1b',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r1_5ffb8_5fpos_2463',['CAN_F8R1_FB8_Pos',['../group___peripheral___registers___bits___definition.html#gabc32c5836d51b1c7aa00509af2f84335',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r1_5ffb9_2464',['CAN_F8R1_FB9',['../group___peripheral___registers___bits___definition.html#ga2b959e903cdac33f5da71aa5c7477a0d',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r1_5ffb9_5fmsk_2465',['CAN_F8R1_FB9_Msk',['../group___peripheral___registers___bits___definition.html#gab30a05da2419398ee1eb3cc0d0c468f3',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r1_5ffb9_5fpos_2466',['CAN_F8R1_FB9_Pos',['../group___peripheral___registers___bits___definition.html#ga33e709811995d99e00d150e9bc96fa27',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r2_5ffb0_2467',['CAN_F8R2_FB0',['../group___peripheral___registers___bits___definition.html#ga3cfe399fb494ff6ab1d5b91258c42764',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r2_5ffb0_5fmsk_2468',['CAN_F8R2_FB0_Msk',['../group___peripheral___registers___bits___definition.html#ga8a5424a898996971be642271b0cb305d',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r2_5ffb0_5fpos_2469',['CAN_F8R2_FB0_Pos',['../group___peripheral___registers___bits___definition.html#ga272fec3946dc588a9c312573c358a162',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r2_5ffb1_2470',['CAN_F8R2_FB1',['../group___peripheral___registers___bits___definition.html#ga9ca04b514b4d6a3b19619932513b8953',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r2_5ffb10_2471',['CAN_F8R2_FB10',['../group___peripheral___registers___bits___definition.html#ga315a7e30b95c05db01b7f56f4d825e62',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r2_5ffb10_5fmsk_2472',['CAN_F8R2_FB10_Msk',['../group___peripheral___registers___bits___definition.html#gab4781d01da4573f59d5bf3d87e3f55c3',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r2_5ffb10_5fpos_2473',['CAN_F8R2_FB10_Pos',['../group___peripheral___registers___bits___definition.html#ga9536c00d19421f818bf61a281ca53852',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r2_5ffb11_2474',['CAN_F8R2_FB11',['../group___peripheral___registers___bits___definition.html#ga353aad2279bf6b72bd861f6c79253635',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r2_5ffb11_5fmsk_2475',['CAN_F8R2_FB11_Msk',['../group___peripheral___registers___bits___definition.html#ga34eab8d93d53237b1f29ca2989602250',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r2_5ffb11_5fpos_2476',['CAN_F8R2_FB11_Pos',['../group___peripheral___registers___bits___definition.html#gab2c8b3acb216b4a20646195872c91cc3',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r2_5ffb12_2477',['CAN_F8R2_FB12',['../group___peripheral___registers___bits___definition.html#ga25193c4b44d05db08ba40f0e0f2c45e1',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r2_5ffb12_5fmsk_2478',['CAN_F8R2_FB12_Msk',['../group___peripheral___registers___bits___definition.html#gaee44ebdb7cb153d4776813386c72d379',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r2_5ffb12_5fpos_2479',['CAN_F8R2_FB12_Pos',['../group___peripheral___registers___bits___definition.html#ga35aa0762c3b9e705075fb629b92f3d52',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r2_5ffb13_2480',['CAN_F8R2_FB13',['../group___peripheral___registers___bits___definition.html#ga4469bfc90525f84d9d04d3a4996997e6',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r2_5ffb13_5fmsk_2481',['CAN_F8R2_FB13_Msk',['../group___peripheral___registers___bits___definition.html#ga6a533bc42a75cb20b6d2225af3259335',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r2_5ffb13_5fpos_2482',['CAN_F8R2_FB13_Pos',['../group___peripheral___registers___bits___definition.html#ga0af605c2d87e6f02f3bfee167a40b818',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r2_5ffb14_2483',['CAN_F8R2_FB14',['../group___peripheral___registers___bits___definition.html#ga3b17ebf3dd1e53d8417f955ebcf743b3',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r2_5ffb14_5fmsk_2484',['CAN_F8R2_FB14_Msk',['../group___peripheral___registers___bits___definition.html#gaf5d8dd791898a26610ad5c99e04c7b85',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r2_5ffb14_5fpos_2485',['CAN_F8R2_FB14_Pos',['../group___peripheral___registers___bits___definition.html#ga52e8448ddc34d6068dad3607d6485056',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r2_5ffb15_2486',['CAN_F8R2_FB15',['../group___peripheral___registers___bits___definition.html#ga6db6c2262434fc76213a441d8ce2edf1',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r2_5ffb15_5fmsk_2487',['CAN_F8R2_FB15_Msk',['../group___peripheral___registers___bits___definition.html#gab9a10d9b3c535b4c04f30d1976a74003',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r2_5ffb15_5fpos_2488',['CAN_F8R2_FB15_Pos',['../group___peripheral___registers___bits___definition.html#ga0f802cc15926cffb97f3a6bc7642501d',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r2_5ffb16_2489',['CAN_F8R2_FB16',['../group___peripheral___registers___bits___definition.html#ga8a1e1e9aa84af36845402d19236c1214',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r2_5ffb16_5fmsk_2490',['CAN_F8R2_FB16_Msk',['../group___peripheral___registers___bits___definition.html#ga79a44278629e098fdeefef5c6e699a21',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r2_5ffb16_5fpos_2491',['CAN_F8R2_FB16_Pos',['../group___peripheral___registers___bits___definition.html#ga7064892926519c2643608a52959b7d19',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r2_5ffb17_2492',['CAN_F8R2_FB17',['../group___peripheral___registers___bits___definition.html#gae0a9ee665444a6b42e98e0f988d1ba7a',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r2_5ffb17_5fmsk_2493',['CAN_F8R2_FB17_Msk',['../group___peripheral___registers___bits___definition.html#ga743f3fc9128154a5e10a49378b39dde0',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r2_5ffb17_5fpos_2494',['CAN_F8R2_FB17_Pos',['../group___peripheral___registers___bits___definition.html#gac7b91a4fcae3e6ffb8acace86ba3106a',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r2_5ffb18_2495',['CAN_F8R2_FB18',['../group___peripheral___registers___bits___definition.html#ga16cde37565a3d3ec3a8c41013df6f6f1',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r2_5ffb18_5fmsk_2496',['CAN_F8R2_FB18_Msk',['../group___peripheral___registers___bits___definition.html#ga6355102db61d562b19aea995401360f5',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r2_5ffb18_5fpos_2497',['CAN_F8R2_FB18_Pos',['../group___peripheral___registers___bits___definition.html#ga49483e1f9418b80826fb30374977b711',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r2_5ffb19_2498',['CAN_F8R2_FB19',['../group___peripheral___registers___bits___definition.html#ga57ca000fea3be225ddf5f295437b6e36',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r2_5ffb19_5fmsk_2499',['CAN_F8R2_FB19_Msk',['../group___peripheral___registers___bits___definition.html#ga7fd103af2e8859f67477580800625162',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r2_5ffb19_5fpos_2500',['CAN_F8R2_FB19_Pos',['../group___peripheral___registers___bits___definition.html#gac0718c73bddee55cbf8c17f5e5393982',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r2_5ffb1_5fmsk_2501',['CAN_F8R2_FB1_Msk',['../group___peripheral___registers___bits___definition.html#gad4bdeb68c24f386e0181eb04937cf109',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r2_5ffb1_5fpos_2502',['CAN_F8R2_FB1_Pos',['../group___peripheral___registers___bits___definition.html#ga4d5a712e64c1b04b7114f562f2605e87',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r2_5ffb2_2503',['CAN_F8R2_FB2',['../group___peripheral___registers___bits___definition.html#gac4c3c099bf7db702b7bf5f71cddaaec2',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r2_5ffb20_2504',['CAN_F8R2_FB20',['../group___peripheral___registers___bits___definition.html#gad60ee9ebdce23be6d2adca113ca918e8',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r2_5ffb20_5fmsk_2505',['CAN_F8R2_FB20_Msk',['../group___peripheral___registers___bits___definition.html#gac32a8af72eea61e6976bb97fdff7fe51',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r2_5ffb20_5fpos_2506',['CAN_F8R2_FB20_Pos',['../group___peripheral___registers___bits___definition.html#ga5c8ae876dd909a399bd06bca0e991f9d',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r2_5ffb21_2507',['CAN_F8R2_FB21',['../group___peripheral___registers___bits___definition.html#gae186c9794783eb47b460532801afe43a',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r2_5ffb21_5fmsk_2508',['CAN_F8R2_FB21_Msk',['../group___peripheral___registers___bits___definition.html#ga47bb6e52fcfdf43778db13faf53a6591',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r2_5ffb21_5fpos_2509',['CAN_F8R2_FB21_Pos',['../group___peripheral___registers___bits___definition.html#ga36935ee8104559d55726f7a19ccc510e',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r2_5ffb22_2510',['CAN_F8R2_FB22',['../group___peripheral___registers___bits___definition.html#ga106a5e5b8ae8d683fcec85b076688f34',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r2_5ffb22_5fmsk_2511',['CAN_F8R2_FB22_Msk',['../group___peripheral___registers___bits___definition.html#ga1d5d496538d2bf3157c80523c0c5fb45',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r2_5ffb22_5fpos_2512',['CAN_F8R2_FB22_Pos',['../group___peripheral___registers___bits___definition.html#gaad26f6f6f8960a65ceac0a9ffb52c075',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r2_5ffb23_2513',['CAN_F8R2_FB23',['../group___peripheral___registers___bits___definition.html#ga1643a77c219a9b2706f438c5123bccc8',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r2_5ffb23_5fmsk_2514',['CAN_F8R2_FB23_Msk',['../group___peripheral___registers___bits___definition.html#gaa768932cd5eef5a2ee54bfe8a0ac41ea',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r2_5ffb23_5fpos_2515',['CAN_F8R2_FB23_Pos',['../group___peripheral___registers___bits___definition.html#gaa6a23988caae50f093de7fd6ee0442fa',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r2_5ffb24_2516',['CAN_F8R2_FB24',['../group___peripheral___registers___bits___definition.html#gab21aa6ed09bed09347e07dbcbd0e9e93',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r2_5ffb24_5fmsk_2517',['CAN_F8R2_FB24_Msk',['../group___peripheral___registers___bits___definition.html#ga0989578ce3e5a1a533853538f3b649ff',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r2_5ffb24_5fpos_2518',['CAN_F8R2_FB24_Pos',['../group___peripheral___registers___bits___definition.html#ga3064ef4c61853f56528fb7649e723d4f',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r2_5ffb25_2519',['CAN_F8R2_FB25',['../group___peripheral___registers___bits___definition.html#gab8267e4cdc484abd75634469f9b255c5',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r2_5ffb25_5fmsk_2520',['CAN_F8R2_FB25_Msk',['../group___peripheral___registers___bits___definition.html#gab5a4af539b9ed1e260226c5a2f4c8242',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r2_5ffb25_5fpos_2521',['CAN_F8R2_FB25_Pos',['../group___peripheral___registers___bits___definition.html#ga1a918c2c68e3e3a6ed3208377e7eb11c',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r2_5ffb26_2522',['CAN_F8R2_FB26',['../group___peripheral___registers___bits___definition.html#ga697d286473e81666c91f28e853aab4ad',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r2_5ffb26_5fmsk_2523',['CAN_F8R2_FB26_Msk',['../group___peripheral___registers___bits___definition.html#ga2d064f4e04559c8ceeb38759b0332381',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r2_5ffb26_5fpos_2524',['CAN_F8R2_FB26_Pos',['../group___peripheral___registers___bits___definition.html#ga8a749b77630a78e7ab323f7f7fcd1930',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r2_5ffb27_2525',['CAN_F8R2_FB27',['../group___peripheral___registers___bits___definition.html#ga295c26638700a849ee3c6504caf6ceab',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r2_5ffb27_5fmsk_2526',['CAN_F8R2_FB27_Msk',['../group___peripheral___registers___bits___definition.html#ga11bcaf39d0176157117636c373492ded',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r2_5ffb27_5fpos_2527',['CAN_F8R2_FB27_Pos',['../group___peripheral___registers___bits___definition.html#ga6cdc04f6f8ebf42d24d0ea4ad895205e',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r2_5ffb28_2528',['CAN_F8R2_FB28',['../group___peripheral___registers___bits___definition.html#ga0f8469008983b405bfc5855258f4f6e6',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r2_5ffb28_5fmsk_2529',['CAN_F8R2_FB28_Msk',['../group___peripheral___registers___bits___definition.html#ga2b60416465405bc628ede32f1ca22221',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r2_5ffb28_5fpos_2530',['CAN_F8R2_FB28_Pos',['../group___peripheral___registers___bits___definition.html#gadb1387b35a958f97ce27f663dfe35c06',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r2_5ffb29_2531',['CAN_F8R2_FB29',['../group___peripheral___registers___bits___definition.html#gad18d894a75ebe73c0185d905cfb81dbf',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r2_5ffb29_5fmsk_2532',['CAN_F8R2_FB29_Msk',['../group___peripheral___registers___bits___definition.html#gae62518d43230d7fe0907da3068092020',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r2_5ffb29_5fpos_2533',['CAN_F8R2_FB29_Pos',['../group___peripheral___registers___bits___definition.html#ga910e2428c8fa737c1779f3536d97bff1',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r2_5ffb2_5fmsk_2534',['CAN_F8R2_FB2_Msk',['../group___peripheral___registers___bits___definition.html#gad180babb8dfebb2d725c57d12ee6c434',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r2_5ffb2_5fpos_2535',['CAN_F8R2_FB2_Pos',['../group___peripheral___registers___bits___definition.html#gaa5cead607181f44f52c174e67034ea71',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r2_5ffb3_2536',['CAN_F8R2_FB3',['../group___peripheral___registers___bits___definition.html#gae1e53037e7f7171d8a7358590f0e7420',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r2_5ffb30_2537',['CAN_F8R2_FB30',['../group___peripheral___registers___bits___definition.html#gaccdf92a69572b56641ddd2967c034a7a',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r2_5ffb30_5fmsk_2538',['CAN_F8R2_FB30_Msk',['../group___peripheral___registers___bits___definition.html#gaf1cd28b7dd676bb4df664b0f4c886dba',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r2_5ffb30_5fpos_2539',['CAN_F8R2_FB30_Pos',['../group___peripheral___registers___bits___definition.html#gae383ae7f7183c4fe7ce61ffb0e90b8aa',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r2_5ffb31_2540',['CAN_F8R2_FB31',['../group___peripheral___registers___bits___definition.html#ga0636c9c9fd84e5e8d12e78f236f2a56c',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r2_5ffb31_5fmsk_2541',['CAN_F8R2_FB31_Msk',['../group___peripheral___registers___bits___definition.html#ga3cdbb1cd26bdd6c1690ac3b208a27898',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r2_5ffb31_5fpos_2542',['CAN_F8R2_FB31_Pos',['../group___peripheral___registers___bits___definition.html#ga45effc10b4b4f084d64ee099dee2537d',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r2_5ffb3_5fmsk_2543',['CAN_F8R2_FB3_Msk',['../group___peripheral___registers___bits___definition.html#ga4b411230765103ce07b48d181683a8ff',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r2_5ffb3_5fpos_2544',['CAN_F8R2_FB3_Pos',['../group___peripheral___registers___bits___definition.html#ga2b2a97e11174175e038a5e49de693d81',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r2_5ffb4_2545',['CAN_F8R2_FB4',['../group___peripheral___registers___bits___definition.html#ga51e2af45725e06538c4d09ad07296316',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r2_5ffb4_5fmsk_2546',['CAN_F8R2_FB4_Msk',['../group___peripheral___registers___bits___definition.html#ga6f5f223e200cbe85d62785c1c1411780',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r2_5ffb4_5fpos_2547',['CAN_F8R2_FB4_Pos',['../group___peripheral___registers___bits___definition.html#ga08ad27ee47d20cf06c110a7a921f6bb1',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r2_5ffb5_2548',['CAN_F8R2_FB5',['../group___peripheral___registers___bits___definition.html#ga2ee5e9d68190f0d41a5b8603d1933922',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r2_5ffb5_5fmsk_2549',['CAN_F8R2_FB5_Msk',['../group___peripheral___registers___bits___definition.html#ga715b276f569abd0659cef3d6041ca97f',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r2_5ffb5_5fpos_2550',['CAN_F8R2_FB5_Pos',['../group___peripheral___registers___bits___definition.html#ga102d50c9df36acfccfadb2129cc7e933',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r2_5ffb6_2551',['CAN_F8R2_FB6',['../group___peripheral___registers___bits___definition.html#ga66c636150cfad43a32652dba3ded8383',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r2_5ffb6_5fmsk_2552',['CAN_F8R2_FB6_Msk',['../group___peripheral___registers___bits___definition.html#ga3bc83f8b713c699af6c4a058d97a0212',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r2_5ffb6_5fpos_2553',['CAN_F8R2_FB6_Pos',['../group___peripheral___registers___bits___definition.html#ga5650f6465760671e23d1ba17e7d1a9fb',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r2_5ffb7_2554',['CAN_F8R2_FB7',['../group___peripheral___registers___bits___definition.html#ga0fc81a4ee32f76ce3a6fdbb3fc49425c',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r2_5ffb7_5fmsk_2555',['CAN_F8R2_FB7_Msk',['../group___peripheral___registers___bits___definition.html#ga1b34be24a3201f24c3c5fb3e4518496a',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r2_5ffb7_5fpos_2556',['CAN_F8R2_FB7_Pos',['../group___peripheral___registers___bits___definition.html#ga6913723330621f154c8c69d67fc8eabf',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r2_5ffb8_2557',['CAN_F8R2_FB8',['../group___peripheral___registers___bits___definition.html#ga68a36336242e8259c779f1c8f4544737',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r2_5ffb8_5fmsk_2558',['CAN_F8R2_FB8_Msk',['../group___peripheral___registers___bits___definition.html#ga246521830f06fc6e78fa76e3460c0c90',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r2_5ffb8_5fpos_2559',['CAN_F8R2_FB8_Pos',['../group___peripheral___registers___bits___definition.html#ga1e6f7d79c9bcd9461cca14ea772df10e',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r2_5ffb9_2560',['CAN_F8R2_FB9',['../group___peripheral___registers___bits___definition.html#gad0014717b3c4c65afb7542308980803d',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r2_5ffb9_5fmsk_2561',['CAN_F8R2_FB9_Msk',['../group___peripheral___registers___bits___definition.html#ga109bccb45d80c850a1753d91810b17e6',1,'stm32f407xx_matlab.h']]], - ['can_5ff8r2_5ffb9_5fpos_2562',['CAN_F8R2_FB9_Pos',['../group___peripheral___registers___bits___definition.html#gab9ccf2f0df421c8136a57c0c60a28bd9',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r1_5ffb0_2563',['CAN_F9R1_FB0',['../group___peripheral___registers___bits___definition.html#ga930a17d830cb9a95a79531dac2220785',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r1_5ffb0_5fmsk_2564',['CAN_F9R1_FB0_Msk',['../group___peripheral___registers___bits___definition.html#gaedc0e0cbb432679fb469888559cd8ba0',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r1_5ffb0_5fpos_2565',['CAN_F9R1_FB0_Pos',['../group___peripheral___registers___bits___definition.html#ga2e408d4dcf2104036587654b320ef837',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r1_5ffb1_2566',['CAN_F9R1_FB1',['../group___peripheral___registers___bits___definition.html#ga8671eac978ebea75e6345adbcdf78026',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r1_5ffb10_2567',['CAN_F9R1_FB10',['../group___peripheral___registers___bits___definition.html#ga3db445a3214057317d84269116c9a3de',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r1_5ffb10_5fmsk_2568',['CAN_F9R1_FB10_Msk',['../group___peripheral___registers___bits___definition.html#gabd756a032170c40a6e99e78c1c52eb95',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r1_5ffb10_5fpos_2569',['CAN_F9R1_FB10_Pos',['../group___peripheral___registers___bits___definition.html#ga382c3bfb429d3dcb4dc665af752e569b',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r1_5ffb11_2570',['CAN_F9R1_FB11',['../group___peripheral___registers___bits___definition.html#gadf09c1d038af593122315a878c15f608',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r1_5ffb11_5fmsk_2571',['CAN_F9R1_FB11_Msk',['../group___peripheral___registers___bits___definition.html#ga7239e8ffb07b9aea8013fec8dded9153',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r1_5ffb11_5fpos_2572',['CAN_F9R1_FB11_Pos',['../group___peripheral___registers___bits___definition.html#ga8154705ae1b389be82edd66ab25b9f81',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r1_5ffb12_2573',['CAN_F9R1_FB12',['../group___peripheral___registers___bits___definition.html#ga12b2a29143ddf47eb1eddf76f9289cb9',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r1_5ffb12_5fmsk_2574',['CAN_F9R1_FB12_Msk',['../group___peripheral___registers___bits___definition.html#gad7fdb5f76ff7140ead344e774d2a7624',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r1_5ffb12_5fpos_2575',['CAN_F9R1_FB12_Pos',['../group___peripheral___registers___bits___definition.html#gae584c59edb1f026fe49dc993eb084dd3',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r1_5ffb13_2576',['CAN_F9R1_FB13',['../group___peripheral___registers___bits___definition.html#ga691bc907b71c30dffdf246c95240ac9b',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r1_5ffb13_5fmsk_2577',['CAN_F9R1_FB13_Msk',['../group___peripheral___registers___bits___definition.html#ga156dc983e417d37a94dd165f5d3d2f93',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r1_5ffb13_5fpos_2578',['CAN_F9R1_FB13_Pos',['../group___peripheral___registers___bits___definition.html#gaf8bce562ccc80042ac70f70fc9c0bc35',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r1_5ffb14_2579',['CAN_F9R1_FB14',['../group___peripheral___registers___bits___definition.html#gaf8669ceaa46f5aecada88accedfb4dbb',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r1_5ffb14_5fmsk_2580',['CAN_F9R1_FB14_Msk',['../group___peripheral___registers___bits___definition.html#ga396a55b76a656a8592faa6c6910dbb40',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r1_5ffb14_5fpos_2581',['CAN_F9R1_FB14_Pos',['../group___peripheral___registers___bits___definition.html#ga6618206f24c69189d2e432bd4efc0651',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r1_5ffb15_2582',['CAN_F9R1_FB15',['../group___peripheral___registers___bits___definition.html#ga35e8769a1e21c4cf3714667e07201804',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r1_5ffb15_5fmsk_2583',['CAN_F9R1_FB15_Msk',['../group___peripheral___registers___bits___definition.html#gadd456c2656ca51201b43ed9831d24d4d',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r1_5ffb15_5fpos_2584',['CAN_F9R1_FB15_Pos',['../group___peripheral___registers___bits___definition.html#gaee8557da5e6de53987fbd0a185596107',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r1_5ffb16_2585',['CAN_F9R1_FB16',['../group___peripheral___registers___bits___definition.html#gad7060a1863aa5b08ce8469001d46c630',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r1_5ffb16_5fmsk_2586',['CAN_F9R1_FB16_Msk',['../group___peripheral___registers___bits___definition.html#ga9fc59d106067ea2d6a18fd5f08ba2767',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r1_5ffb16_5fpos_2587',['CAN_F9R1_FB16_Pos',['../group___peripheral___registers___bits___definition.html#gabe418890b1a83c8846daace95b47edf9',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r1_5ffb17_2588',['CAN_F9R1_FB17',['../group___peripheral___registers___bits___definition.html#gacf015fb7231bd315f82948019dcfc725',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r1_5ffb17_5fmsk_2589',['CAN_F9R1_FB17_Msk',['../group___peripheral___registers___bits___definition.html#gaf4ff327faa1fe85083a3ef4f071e86e9',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r1_5ffb17_5fpos_2590',['CAN_F9R1_FB17_Pos',['../group___peripheral___registers___bits___definition.html#ga04c61d64fef04b48caeba748a9a22aa6',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r1_5ffb18_2591',['CAN_F9R1_FB18',['../group___peripheral___registers___bits___definition.html#ga02c06b01abb3414394747a7cf8eac888',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r1_5ffb18_5fmsk_2592',['CAN_F9R1_FB18_Msk',['../group___peripheral___registers___bits___definition.html#ga1580585e09b20a6bc206c033139649a6',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r1_5ffb18_5fpos_2593',['CAN_F9R1_FB18_Pos',['../group___peripheral___registers___bits___definition.html#ga35916c6399028aaf16c864a1b37f191e',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r1_5ffb19_2594',['CAN_F9R1_FB19',['../group___peripheral___registers___bits___definition.html#ga99a1a20417252e33a4817c0530745239',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r1_5ffb19_5fmsk_2595',['CAN_F9R1_FB19_Msk',['../group___peripheral___registers___bits___definition.html#gaa356b4a420c19ac07bfa409d55e53adc',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r1_5ffb19_5fpos_2596',['CAN_F9R1_FB19_Pos',['../group___peripheral___registers___bits___definition.html#gafa5760e3a9d5b2ae2596c1a203ac772a',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r1_5ffb1_5fmsk_2597',['CAN_F9R1_FB1_Msk',['../group___peripheral___registers___bits___definition.html#ga311d13b8b6763e76d9c889e49c7f5254',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r1_5ffb1_5fpos_2598',['CAN_F9R1_FB1_Pos',['../group___peripheral___registers___bits___definition.html#gaf4b2c5ddbad8e4d30df6bae1553ae95f',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r1_5ffb2_2599',['CAN_F9R1_FB2',['../group___peripheral___registers___bits___definition.html#gaee3585fb5ee4081dffeb2a2dda1ce72f',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r1_5ffb20_2600',['CAN_F9R1_FB20',['../group___peripheral___registers___bits___definition.html#ga09c0f503e2ef85b3b6332ccbca7b0251',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r1_5ffb20_5fmsk_2601',['CAN_F9R1_FB20_Msk',['../group___peripheral___registers___bits___definition.html#ga8f43ec3ddec319e7dfbda3b44c7c2df4',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r1_5ffb20_5fpos_2602',['CAN_F9R1_FB20_Pos',['../group___peripheral___registers___bits___definition.html#ga8e961ee93fb85b21e152e98eb2d69e08',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r1_5ffb21_2603',['CAN_F9R1_FB21',['../group___peripheral___registers___bits___definition.html#gacab12d06dee3d6dad5fd7c56c23c70d1',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r1_5ffb21_5fmsk_2604',['CAN_F9R1_FB21_Msk',['../group___peripheral___registers___bits___definition.html#ga8a5361a1933b142476427e60fc3f9c72',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r1_5ffb21_5fpos_2605',['CAN_F9R1_FB21_Pos',['../group___peripheral___registers___bits___definition.html#gaedf1cb9ca8fd641443fbddc3b66dd953',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r1_5ffb22_2606',['CAN_F9R1_FB22',['../group___peripheral___registers___bits___definition.html#ga5c72a8d17db1de69086f19579b169c04',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r1_5ffb22_5fmsk_2607',['CAN_F9R1_FB22_Msk',['../group___peripheral___registers___bits___definition.html#ga55a508f12177632ba51a7ddc551ed9e2',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r1_5ffb22_5fpos_2608',['CAN_F9R1_FB22_Pos',['../group___peripheral___registers___bits___definition.html#gad975dfcf3d01716533fb54d8b61787c2',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r1_5ffb23_2609',['CAN_F9R1_FB23',['../group___peripheral___registers___bits___definition.html#ga4bb3ba674ec6c82ed108f6c0bfb2f854',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r1_5ffb23_5fmsk_2610',['CAN_F9R1_FB23_Msk',['../group___peripheral___registers___bits___definition.html#ga65ef341230d8345ce5e8176674f9f745',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r1_5ffb23_5fpos_2611',['CAN_F9R1_FB23_Pos',['../group___peripheral___registers___bits___definition.html#gad49102a5c0f38207584062f8303da2f5',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r1_5ffb24_2612',['CAN_F9R1_FB24',['../group___peripheral___registers___bits___definition.html#gaba13bd7fa1e4c2eaef3de31d933cbc10',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r1_5ffb24_5fmsk_2613',['CAN_F9R1_FB24_Msk',['../group___peripheral___registers___bits___definition.html#ga309068d091fa9bd5abd28c709efb96c8',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r1_5ffb24_5fpos_2614',['CAN_F9R1_FB24_Pos',['../group___peripheral___registers___bits___definition.html#gac621c869012858627036bd298ced7e8f',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r1_5ffb25_2615',['CAN_F9R1_FB25',['../group___peripheral___registers___bits___definition.html#gaa72247fe16d8f777c26726063fa43536',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r1_5ffb25_5fmsk_2616',['CAN_F9R1_FB25_Msk',['../group___peripheral___registers___bits___definition.html#gac97a1bd116fc0f32a29c4c3006d0330d',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r1_5ffb25_5fpos_2617',['CAN_F9R1_FB25_Pos',['../group___peripheral___registers___bits___definition.html#ga4cb66980120bd88fc4a472a87ea672e4',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r1_5ffb26_2618',['CAN_F9R1_FB26',['../group___peripheral___registers___bits___definition.html#ga32d7c1678449ff8f4e4b6f548ba85be4',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r1_5ffb26_5fmsk_2619',['CAN_F9R1_FB26_Msk',['../group___peripheral___registers___bits___definition.html#ga9ed19ac97bbe1e8d109a31af97ac183c',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r1_5ffb26_5fpos_2620',['CAN_F9R1_FB26_Pos',['../group___peripheral___registers___bits___definition.html#ga7f2aaac573ee7915936b4c68ab36fc5a',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r1_5ffb27_2621',['CAN_F9R1_FB27',['../group___peripheral___registers___bits___definition.html#ga678d4a0a39b379db5c2e0285782c686f',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r1_5ffb27_5fmsk_2622',['CAN_F9R1_FB27_Msk',['../group___peripheral___registers___bits___definition.html#ga3bfa05da1393f001376725caac1a5cb1',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r1_5ffb27_5fpos_2623',['CAN_F9R1_FB27_Pos',['../group___peripheral___registers___bits___definition.html#ga00c420c0a498d9f93ae7b78d10c90171',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r1_5ffb28_2624',['CAN_F9R1_FB28',['../group___peripheral___registers___bits___definition.html#ga6033aa5f4d140dc48ddb4a777583163c',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r1_5ffb28_5fmsk_2625',['CAN_F9R1_FB28_Msk',['../group___peripheral___registers___bits___definition.html#gaab301858f2e91edd141441ebf4be606b',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r1_5ffb28_5fpos_2626',['CAN_F9R1_FB28_Pos',['../group___peripheral___registers___bits___definition.html#ga0e5d9b745f7bd053a3843faf405b7eb1',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r1_5ffb29_2627',['CAN_F9R1_FB29',['../group___peripheral___registers___bits___definition.html#ga9fda159c684d7361094da1883473b544',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r1_5ffb29_5fmsk_2628',['CAN_F9R1_FB29_Msk',['../group___peripheral___registers___bits___definition.html#gac23f3b612ef426adf60238083766f4a8',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r1_5ffb29_5fpos_2629',['CAN_F9R1_FB29_Pos',['../group___peripheral___registers___bits___definition.html#gaa8fc29302b5a2404550b37a1e62c0f11',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r1_5ffb2_5fmsk_2630',['CAN_F9R1_FB2_Msk',['../group___peripheral___registers___bits___definition.html#gac66033af8f1d5f936090a464ef6af680',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r1_5ffb2_5fpos_2631',['CAN_F9R1_FB2_Pos',['../group___peripheral___registers___bits___definition.html#gacdac08de057f74084b0df1bdd49ffaa4',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r1_5ffb3_2632',['CAN_F9R1_FB3',['../group___peripheral___registers___bits___definition.html#ga807e831fafa69e9df65618de855ea186',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r1_5ffb30_2633',['CAN_F9R1_FB30',['../group___peripheral___registers___bits___definition.html#ga83cf4080564c51a0123b97840576c0ab',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r1_5ffb30_5fmsk_2634',['CAN_F9R1_FB30_Msk',['../group___peripheral___registers___bits___definition.html#ga0799e2743ca085ddc2d3557c81d4fb5a',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r1_5ffb30_5fpos_2635',['CAN_F9R1_FB30_Pos',['../group___peripheral___registers___bits___definition.html#gaec4d21090abcdafb53a216c6507cbf57',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r1_5ffb31_2636',['CAN_F9R1_FB31',['../group___peripheral___registers___bits___definition.html#ga127c155bc5c5236f04cfdcf96ff66cc5',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r1_5ffb31_5fmsk_2637',['CAN_F9R1_FB31_Msk',['../group___peripheral___registers___bits___definition.html#gac69d0815a7cd9bf18de74375fea92676',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r1_5ffb31_5fpos_2638',['CAN_F9R1_FB31_Pos',['../group___peripheral___registers___bits___definition.html#ga5c781d400959fec8e3f8636b97c6227c',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r1_5ffb3_5fmsk_2639',['CAN_F9R1_FB3_Msk',['../group___peripheral___registers___bits___definition.html#ga4bfd9933c0a4fb97ece209b9fcdfa794',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r1_5ffb3_5fpos_2640',['CAN_F9R1_FB3_Pos',['../group___peripheral___registers___bits___definition.html#ga693575c5b64ad798658952694e636204',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r1_5ffb4_2641',['CAN_F9R1_FB4',['../group___peripheral___registers___bits___definition.html#gaddce646e28626a508b2f98c4f35148b3',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r1_5ffb4_5fmsk_2642',['CAN_F9R1_FB4_Msk',['../group___peripheral___registers___bits___definition.html#ga362251d468d76c64459afc82f84acd06',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r1_5ffb4_5fpos_2643',['CAN_F9R1_FB4_Pos',['../group___peripheral___registers___bits___definition.html#ga726f4f35552287c718dce9b5c46baba1',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r1_5ffb5_2644',['CAN_F9R1_FB5',['../group___peripheral___registers___bits___definition.html#ga9ea72662e0243714ace5c0b48e7912f6',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r1_5ffb5_5fmsk_2645',['CAN_F9R1_FB5_Msk',['../group___peripheral___registers___bits___definition.html#ga9af391a698294bbcfd73e13d7bc3d45f',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r1_5ffb5_5fpos_2646',['CAN_F9R1_FB5_Pos',['../group___peripheral___registers___bits___definition.html#ga6064e11830367708fa478a64d6134471',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r1_5ffb6_2647',['CAN_F9R1_FB6',['../group___peripheral___registers___bits___definition.html#ga6b08ddbc0bed91c6a1933e6485ded5e2',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r1_5ffb6_5fmsk_2648',['CAN_F9R1_FB6_Msk',['../group___peripheral___registers___bits___definition.html#gadf73980f9d3a6a660ab4b0742b849827',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r1_5ffb6_5fpos_2649',['CAN_F9R1_FB6_Pos',['../group___peripheral___registers___bits___definition.html#gaa48d9cd13e58139129678537b2a46a54',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r1_5ffb7_2650',['CAN_F9R1_FB7',['../group___peripheral___registers___bits___definition.html#gae21fd9c8c790d4bc229c7ccb6d99dd36',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r1_5ffb7_5fmsk_2651',['CAN_F9R1_FB7_Msk',['../group___peripheral___registers___bits___definition.html#ga93cc25aaf5401c7a3e16cb4609ee0e07',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r1_5ffb7_5fpos_2652',['CAN_F9R1_FB7_Pos',['../group___peripheral___registers___bits___definition.html#ga7c12d5c48b26fa65b51d8978f372d235',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r1_5ffb8_2653',['CAN_F9R1_FB8',['../group___peripheral___registers___bits___definition.html#gadf1a8f02576caccfddc12f2ead734762',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r1_5ffb8_5fmsk_2654',['CAN_F9R1_FB8_Msk',['../group___peripheral___registers___bits___definition.html#gaba01d797a4d055fe0a1af549c3fb4734',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r1_5ffb8_5fpos_2655',['CAN_F9R1_FB8_Pos',['../group___peripheral___registers___bits___definition.html#ga8fce8e9c5098084f4b4e9fffe064627c',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r1_5ffb9_2656',['CAN_F9R1_FB9',['../group___peripheral___registers___bits___definition.html#ga80a2594aaa275fd88225927e7115085b',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r1_5ffb9_5fmsk_2657',['CAN_F9R1_FB9_Msk',['../group___peripheral___registers___bits___definition.html#gac2e7a7ac6a91de762e00f6ccbde5c982',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r1_5ffb9_5fpos_2658',['CAN_F9R1_FB9_Pos',['../group___peripheral___registers___bits___definition.html#ga4f9d0da640c988023228da572b39189f',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r2_5ffb0_2659',['CAN_F9R2_FB0',['../group___peripheral___registers___bits___definition.html#gaa1209cec0d1199b7f74bb2e2b1cca424',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r2_5ffb0_5fmsk_2660',['CAN_F9R2_FB0_Msk',['../group___peripheral___registers___bits___definition.html#ga47309fd6134f2abe4e3b1b496093d9be',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r2_5ffb0_5fpos_2661',['CAN_F9R2_FB0_Pos',['../group___peripheral___registers___bits___definition.html#ga71fb77883884a56d1b3e9d2029007d02',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r2_5ffb1_2662',['CAN_F9R2_FB1',['../group___peripheral___registers___bits___definition.html#ga9fd983be0f74b7f183261f21cd2f6910',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r2_5ffb10_2663',['CAN_F9R2_FB10',['../group___peripheral___registers___bits___definition.html#ga5adc0ffeba391461d887f5d176a9b5bd',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r2_5ffb10_5fmsk_2664',['CAN_F9R2_FB10_Msk',['../group___peripheral___registers___bits___definition.html#gaf0f169b5d13d9d6d69d89d99c8451ebd',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r2_5ffb10_5fpos_2665',['CAN_F9R2_FB10_Pos',['../group___peripheral___registers___bits___definition.html#ga91dd86a4bf1da1e33c7b56503eebbd52',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r2_5ffb11_2666',['CAN_F9R2_FB11',['../group___peripheral___registers___bits___definition.html#ga989f1dea5a35e78b08649ac699955563',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r2_5ffb11_5fmsk_2667',['CAN_F9R2_FB11_Msk',['../group___peripheral___registers___bits___definition.html#ga5b87e7eba6f9fbe4a1e390599703e4ea',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r2_5ffb11_5fpos_2668',['CAN_F9R2_FB11_Pos',['../group___peripheral___registers___bits___definition.html#gae624263208ca55d8690f216d3a4dfb78',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r2_5ffb12_2669',['CAN_F9R2_FB12',['../group___peripheral___registers___bits___definition.html#ga0b71e1b7db02ef8c5853534921b33aee',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r2_5ffb12_5fmsk_2670',['CAN_F9R2_FB12_Msk',['../group___peripheral___registers___bits___definition.html#ga9b961aa158542f370fd755e37e3ebbf7',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r2_5ffb12_5fpos_2671',['CAN_F9R2_FB12_Pos',['../group___peripheral___registers___bits___definition.html#gad6860cb0d3b72432d7e35b0ade6a3d05',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r2_5ffb13_2672',['CAN_F9R2_FB13',['../group___peripheral___registers___bits___definition.html#ga48cff2713910823bbf9c8aeb399d6695',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r2_5ffb13_5fmsk_2673',['CAN_F9R2_FB13_Msk',['../group___peripheral___registers___bits___definition.html#ga01e88250b1d9d44f23df2ddc46397574',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r2_5ffb13_5fpos_2674',['CAN_F9R2_FB13_Pos',['../group___peripheral___registers___bits___definition.html#ga5031b931df96b65727ccbb5298e678c1',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r2_5ffb14_2675',['CAN_F9R2_FB14',['../group___peripheral___registers___bits___definition.html#gab9e0057c4eb0f7238d2ec98ae0702ff3',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r2_5ffb14_5fmsk_2676',['CAN_F9R2_FB14_Msk',['../group___peripheral___registers___bits___definition.html#gaa2659b21a47fe2b7475163ef583622c7',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r2_5ffb14_5fpos_2677',['CAN_F9R2_FB14_Pos',['../group___peripheral___registers___bits___definition.html#ga88f67bd4804724913a1ace948970d584',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r2_5ffb15_2678',['CAN_F9R2_FB15',['../group___peripheral___registers___bits___definition.html#gacc16f71c9ee3bc56be17f7488c1df807',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r2_5ffb15_5fmsk_2679',['CAN_F9R2_FB15_Msk',['../group___peripheral___registers___bits___definition.html#ga034e40bc2fcebd32d4d77b2b38c68dda',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r2_5ffb15_5fpos_2680',['CAN_F9R2_FB15_Pos',['../group___peripheral___registers___bits___definition.html#ga69a42974dfe7527cbb7e2db8d402393b',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r2_5ffb16_2681',['CAN_F9R2_FB16',['../group___peripheral___registers___bits___definition.html#ga3909a33262113171b7d4dc11fcf8c3b1',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r2_5ffb16_5fmsk_2682',['CAN_F9R2_FB16_Msk',['../group___peripheral___registers___bits___definition.html#gacae78b5a3198b22b6590676496caa801',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r2_5ffb16_5fpos_2683',['CAN_F9R2_FB16_Pos',['../group___peripheral___registers___bits___definition.html#ga3f2ba5f0426b80b58ec6842414929185',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r2_5ffb17_2684',['CAN_F9R2_FB17',['../group___peripheral___registers___bits___definition.html#ga8cead3f8d10075aa34c9446859356e2d',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r2_5ffb17_5fmsk_2685',['CAN_F9R2_FB17_Msk',['../group___peripheral___registers___bits___definition.html#ga30db50cc21514e923c0bf91374491e91',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r2_5ffb17_5fpos_2686',['CAN_F9R2_FB17_Pos',['../group___peripheral___registers___bits___definition.html#ga5e3fde8ece69886d20cd8e258f981645',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r2_5ffb18_2687',['CAN_F9R2_FB18',['../group___peripheral___registers___bits___definition.html#gaf7730d43a2cf07a1568ed738a4f69692',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r2_5ffb18_5fmsk_2688',['CAN_F9R2_FB18_Msk',['../group___peripheral___registers___bits___definition.html#gac07c3cc02fa2a02058063f3fed95f97c',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r2_5ffb18_5fpos_2689',['CAN_F9R2_FB18_Pos',['../group___peripheral___registers___bits___definition.html#ga17263ecd2c5f80d8c32b697f375bff23',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r2_5ffb19_2690',['CAN_F9R2_FB19',['../group___peripheral___registers___bits___definition.html#ga6b2f5ba8403cbd679694cf9665e2690f',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r2_5ffb19_5fmsk_2691',['CAN_F9R2_FB19_Msk',['../group___peripheral___registers___bits___definition.html#ga280fd7273494894b41cf8b3e05a94423',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r2_5ffb19_5fpos_2692',['CAN_F9R2_FB19_Pos',['../group___peripheral___registers___bits___definition.html#ga19083a2e70e921dcb5e560c236c19b97',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r2_5ffb1_5fmsk_2693',['CAN_F9R2_FB1_Msk',['../group___peripheral___registers___bits___definition.html#gadfe55444ba47900acdea02a8e64db98b',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r2_5ffb1_5fpos_2694',['CAN_F9R2_FB1_Pos',['../group___peripheral___registers___bits___definition.html#gaa1b8c8d47bf8d4009b79c69e629106d8',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r2_5ffb2_2695',['CAN_F9R2_FB2',['../group___peripheral___registers___bits___definition.html#ga2e363da951c1191e733a8bc603cda3f5',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r2_5ffb20_2696',['CAN_F9R2_FB20',['../group___peripheral___registers___bits___definition.html#gaca5a17ed59696ed0572b80767c4bef81',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r2_5ffb20_5fmsk_2697',['CAN_F9R2_FB20_Msk',['../group___peripheral___registers___bits___definition.html#ga5ebf7e69a5cbb23be0d72df90d938455',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r2_5ffb20_5fpos_2698',['CAN_F9R2_FB20_Pos',['../group___peripheral___registers___bits___definition.html#gafcd8dc4d422b78b03a7190665e89fc7d',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r2_5ffb21_2699',['CAN_F9R2_FB21',['../group___peripheral___registers___bits___definition.html#gac318672024cefb98843d473cbb2d46b2',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r2_5ffb21_5fmsk_2700',['CAN_F9R2_FB21_Msk',['../group___peripheral___registers___bits___definition.html#ga29e80a00a8a175f05ccec5b2465f707f',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r2_5ffb21_5fpos_2701',['CAN_F9R2_FB21_Pos',['../group___peripheral___registers___bits___definition.html#ga7ee45801f88c81aa88d1dcb0cb13da8d',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r2_5ffb22_2702',['CAN_F9R2_FB22',['../group___peripheral___registers___bits___definition.html#ga3523d55c8cf0a308fea4837b00f89abb',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r2_5ffb22_5fmsk_2703',['CAN_F9R2_FB22_Msk',['../group___peripheral___registers___bits___definition.html#gaae2e762f3d91189614712c5f708c13ec',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r2_5ffb22_5fpos_2704',['CAN_F9R2_FB22_Pos',['../group___peripheral___registers___bits___definition.html#ga0a828c3ecaa65b06ed7262618009f645',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r2_5ffb23_2705',['CAN_F9R2_FB23',['../group___peripheral___registers___bits___definition.html#ga21d8d812323030dd39f417318c36b8dc',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r2_5ffb23_5fmsk_2706',['CAN_F9R2_FB23_Msk',['../group___peripheral___registers___bits___definition.html#ga6411880c098bbbe9e746ae660f1d3643',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r2_5ffb23_5fpos_2707',['CAN_F9R2_FB23_Pos',['../group___peripheral___registers___bits___definition.html#gac77e06fc859440775bed41060185f84d',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r2_5ffb24_2708',['CAN_F9R2_FB24',['../group___peripheral___registers___bits___definition.html#ga065bba6dde8a5b81b42c2618204bf0be',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r2_5ffb24_5fmsk_2709',['CAN_F9R2_FB24_Msk',['../group___peripheral___registers___bits___definition.html#ga9112971db909b1bf0bd272c687ca44ba',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r2_5ffb24_5fpos_2710',['CAN_F9R2_FB24_Pos',['../group___peripheral___registers___bits___definition.html#ga5e3da3cb77f9bab0b9688ee8ac1ead87',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r2_5ffb25_2711',['CAN_F9R2_FB25',['../group___peripheral___registers___bits___definition.html#gade5290535026c192f7e94a4cb98e48b4',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r2_5ffb25_5fmsk_2712',['CAN_F9R2_FB25_Msk',['../group___peripheral___registers___bits___definition.html#ga0a276cb2e015ee7b075eec7a16686ac3',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r2_5ffb25_5fpos_2713',['CAN_F9R2_FB25_Pos',['../group___peripheral___registers___bits___definition.html#ga784ec53e7bab49da60d9ede528c85b17',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r2_5ffb26_2714',['CAN_F9R2_FB26',['../group___peripheral___registers___bits___definition.html#gaac7e7544d60c3084da344ee20ab6a760',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r2_5ffb26_5fmsk_2715',['CAN_F9R2_FB26_Msk',['../group___peripheral___registers___bits___definition.html#ga664cbbe2443064efe7fb3129550c226b',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r2_5ffb26_5fpos_2716',['CAN_F9R2_FB26_Pos',['../group___peripheral___registers___bits___definition.html#ga4802401202cdadbd984547f05b09fd1b',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r2_5ffb27_2717',['CAN_F9R2_FB27',['../group___peripheral___registers___bits___definition.html#gae965845f1e45d1f45831be60829e63bc',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r2_5ffb27_5fmsk_2718',['CAN_F9R2_FB27_Msk',['../group___peripheral___registers___bits___definition.html#ga21473aad3bbd0a024b0e714c9bbf4e47',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r2_5ffb27_5fpos_2719',['CAN_F9R2_FB27_Pos',['../group___peripheral___registers___bits___definition.html#ga8f56af8f8de74632465471450552f8d5',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r2_5ffb28_2720',['CAN_F9R2_FB28',['../group___peripheral___registers___bits___definition.html#ga63bbecf009bf6bd61dc9e8fe0603da73',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r2_5ffb28_5fmsk_2721',['CAN_F9R2_FB28_Msk',['../group___peripheral___registers___bits___definition.html#ga23124d9ac50f080e32aebae3449ee1a0',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r2_5ffb28_5fpos_2722',['CAN_F9R2_FB28_Pos',['../group___peripheral___registers___bits___definition.html#ga9d4d14753760fee8b7edf9c281f43bfa',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r2_5ffb29_2723',['CAN_F9R2_FB29',['../group___peripheral___registers___bits___definition.html#ga834cf606ef4b69b0c459b8cb9e836a9b',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r2_5ffb29_5fmsk_2724',['CAN_F9R2_FB29_Msk',['../group___peripheral___registers___bits___definition.html#ga5c149f89a9b7f6a847fc01fe55304dd2',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r2_5ffb29_5fpos_2725',['CAN_F9R2_FB29_Pos',['../group___peripheral___registers___bits___definition.html#gac9834ba7e7b11eff8cca5d8ad9845f03',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r2_5ffb2_5fmsk_2726',['CAN_F9R2_FB2_Msk',['../group___peripheral___registers___bits___definition.html#ga5e3aeaa699aed8591a458dbdb8fd3358',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r2_5ffb2_5fpos_2727',['CAN_F9R2_FB2_Pos',['../group___peripheral___registers___bits___definition.html#ga36e5b680c042a6052bfd32e8ae58b221',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r2_5ffb3_2728',['CAN_F9R2_FB3',['../group___peripheral___registers___bits___definition.html#gabab5a59d405ae1684853988e95ab9844',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r2_5ffb30_2729',['CAN_F9R2_FB30',['../group___peripheral___registers___bits___definition.html#ga9c833e07b7a842ba7425291f628c9a11',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r2_5ffb30_5fmsk_2730',['CAN_F9R2_FB30_Msk',['../group___peripheral___registers___bits___definition.html#ga76d278d95612c8049d4ade5a1a30fabe',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r2_5ffb30_5fpos_2731',['CAN_F9R2_FB30_Pos',['../group___peripheral___registers___bits___definition.html#ga1765e9fda5089f19109be26e678e6e2d',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r2_5ffb31_2732',['CAN_F9R2_FB31',['../group___peripheral___registers___bits___definition.html#ga18ef7c7bae75406a267e6a333c549a9f',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r2_5ffb31_5fmsk_2733',['CAN_F9R2_FB31_Msk',['../group___peripheral___registers___bits___definition.html#ga3863b24c5580c3f1dcf4dcfccb08796f',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r2_5ffb31_5fpos_2734',['CAN_F9R2_FB31_Pos',['../group___peripheral___registers___bits___definition.html#ga0e51a4af2c6e972bfd49080723c0ac48',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r2_5ffb3_5fmsk_2735',['CAN_F9R2_FB3_Msk',['../group___peripheral___registers___bits___definition.html#gac9bf0ad567bc6a89528616adb3d30cc0',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r2_5ffb3_5fpos_2736',['CAN_F9R2_FB3_Pos',['../group___peripheral___registers___bits___definition.html#ga2c3e1cc66212316557b21298d3852b22',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r2_5ffb4_2737',['CAN_F9R2_FB4',['../group___peripheral___registers___bits___definition.html#ga4b5b46878001f43618c726b3429e4b50',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r2_5ffb4_5fmsk_2738',['CAN_F9R2_FB4_Msk',['../group___peripheral___registers___bits___definition.html#ga5010d303de1ed187fcf3d663cc5b7b3a',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r2_5ffb4_5fpos_2739',['CAN_F9R2_FB4_Pos',['../group___peripheral___registers___bits___definition.html#gadc1f6b4960d803c1e388f0f6a7525736',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r2_5ffb5_2740',['CAN_F9R2_FB5',['../group___peripheral___registers___bits___definition.html#ga582895a48cfeb8d7ecf6c9757ba0aa39',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r2_5ffb5_5fmsk_2741',['CAN_F9R2_FB5_Msk',['../group___peripheral___registers___bits___definition.html#ga596e424fe2e4186174d148aeef611074',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r2_5ffb5_5fpos_2742',['CAN_F9R2_FB5_Pos',['../group___peripheral___registers___bits___definition.html#ga9555447cbcc79096f5ae9e132455e2c6',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r2_5ffb6_2743',['CAN_F9R2_FB6',['../group___peripheral___registers___bits___definition.html#gafe18a44ac1a9c4cf2a6e94bb946af17f',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r2_5ffb6_5fmsk_2744',['CAN_F9R2_FB6_Msk',['../group___peripheral___registers___bits___definition.html#ga652ee4940983c9766b517598ad270e1f',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r2_5ffb6_5fpos_2745',['CAN_F9R2_FB6_Pos',['../group___peripheral___registers___bits___definition.html#ga0961df6b41382621852dc673c9101f39',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r2_5ffb7_2746',['CAN_F9R2_FB7',['../group___peripheral___registers___bits___definition.html#gae497ffa0ef246a52e57a394fa57e616d',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r2_5ffb7_5fmsk_2747',['CAN_F9R2_FB7_Msk',['../group___peripheral___registers___bits___definition.html#gaed416d6141752c65110daae0c617859a',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r2_5ffb7_5fpos_2748',['CAN_F9R2_FB7_Pos',['../group___peripheral___registers___bits___definition.html#ga2f7b07d1129f4ea3727306744500577a',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r2_5ffb8_2749',['CAN_F9R2_FB8',['../group___peripheral___registers___bits___definition.html#ga4eedc431183ceae7240d11afc05bacfa',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r2_5ffb8_5fmsk_2750',['CAN_F9R2_FB8_Msk',['../group___peripheral___registers___bits___definition.html#gad301a470b47c85751c573fc3579d91a9',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r2_5ffb8_5fpos_2751',['CAN_F9R2_FB8_Pos',['../group___peripheral___registers___bits___definition.html#gaff37f998935141f0cb7203a5b74baeea',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r2_5ffb9_2752',['CAN_F9R2_FB9',['../group___peripheral___registers___bits___definition.html#ga71d1294050a77f52ecd4b00568cd7477',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r2_5ffb9_5fmsk_2753',['CAN_F9R2_FB9_Msk',['../group___peripheral___registers___bits___definition.html#gaa912a018c3cc0adcbeacd61b6e5871a6',1,'stm32f407xx_matlab.h']]], - ['can_5ff9r2_5ffb9_5fpos_2754',['CAN_F9R2_FB9_Pos',['../group___peripheral___registers___bits___definition.html#ga232ef1a0d6455d0f6afe6ae0f7c5a911',1,'stm32f407xx_matlab.h']]], - ['can_5ffa1r_5ffact_2755',['CAN_FA1R_FACT',['../group___peripheral___registers___bits___definition.html#gaa571445875b08a9514e1d1b410a93ebd',1,'stm32f407xx_matlab.h']]], - ['can_5ffa1r_5ffact0_2756',['CAN_FA1R_FACT0',['../group___peripheral___registers___bits___definition.html#gab3ec1e2f9b9ccf2b4869cdf7c7328e60',1,'stm32f407xx_matlab.h']]], - ['can_5ffa1r_5ffact0_5fmsk_2757',['CAN_FA1R_FACT0_Msk',['../group___peripheral___registers___bits___definition.html#gabc33c5308d541004ba2961a7d0527278',1,'stm32f407xx_matlab.h']]], - ['can_5ffa1r_5ffact0_5fpos_2758',['CAN_FA1R_FACT0_Pos',['../group___peripheral___registers___bits___definition.html#ga4be3d2c02fe8f070f95f234191482b86',1,'stm32f407xx_matlab.h']]], - ['can_5ffa1r_5ffact1_2759',['CAN_FA1R_FACT1',['../group___peripheral___registers___bits___definition.html#ga2457026460aecb52dba7ea17237b4dbe',1,'stm32f407xx_matlab.h']]], - ['can_5ffa1r_5ffact10_2760',['CAN_FA1R_FACT10',['../group___peripheral___registers___bits___definition.html#ga19696d8b702b33eafe7f18aa0c6c1955',1,'stm32f407xx_matlab.h']]], - ['can_5ffa1r_5ffact10_5fmsk_2761',['CAN_FA1R_FACT10_Msk',['../group___peripheral___registers___bits___definition.html#gafff61cabd030366925d3f3608cd81ec4',1,'stm32f407xx_matlab.h']]], - ['can_5ffa1r_5ffact10_5fpos_2762',['CAN_FA1R_FACT10_Pos',['../group___peripheral___registers___bits___definition.html#ga095e0af1331f6dbf70921399cb9d5930',1,'stm32f407xx_matlab.h']]], - ['can_5ffa1r_5ffact11_2763',['CAN_FA1R_FACT11',['../group___peripheral___registers___bits___definition.html#ga89e5e3ccd4250ad2360b91ef51248a66',1,'stm32f407xx_matlab.h']]], - ['can_5ffa1r_5ffact11_5fmsk_2764',['CAN_FA1R_FACT11_Msk',['../group___peripheral___registers___bits___definition.html#gad043d708a8b891182f6f36217bba8a70',1,'stm32f407xx_matlab.h']]], - ['can_5ffa1r_5ffact11_5fpos_2765',['CAN_FA1R_FACT11_Pos',['../group___peripheral___registers___bits___definition.html#gabd79b5d1d4a66c46c60190ff3e356419',1,'stm32f407xx_matlab.h']]], - ['can_5ffa1r_5ffact12_2766',['CAN_FA1R_FACT12',['../group___peripheral___registers___bits___definition.html#gae78ec392640f05b20a7c6877983588ae',1,'stm32f407xx_matlab.h']]], - ['can_5ffa1r_5ffact12_5fmsk_2767',['CAN_FA1R_FACT12_Msk',['../group___peripheral___registers___bits___definition.html#gad7de851ce57bd07d4913bd409dee3f51',1,'stm32f407xx_matlab.h']]], - ['can_5ffa1r_5ffact12_5fpos_2768',['CAN_FA1R_FACT12_Pos',['../group___peripheral___registers___bits___definition.html#ga8ec82f6225d96fddd6fdb40033aa54d8',1,'stm32f407xx_matlab.h']]], - ['can_5ffa1r_5ffact13_2769',['CAN_FA1R_FACT13',['../group___peripheral___registers___bits___definition.html#gaa722eeef87f8a3f58ebfcb531645cc05',1,'stm32f407xx_matlab.h']]], - ['can_5ffa1r_5ffact13_5fmsk_2770',['CAN_FA1R_FACT13_Msk',['../group___peripheral___registers___bits___definition.html#ga5fc2cc6acea1e2a86083f9f0d5ce05c0',1,'stm32f407xx_matlab.h']]], - ['can_5ffa1r_5ffact13_5fpos_2771',['CAN_FA1R_FACT13_Pos',['../group___peripheral___registers___bits___definition.html#ga6056bd9c2a6de9289b06bbcd0eab4599',1,'stm32f407xx_matlab.h']]], - ['can_5ffa1r_5ffact14_2772',['CAN_FA1R_FACT14',['../group___peripheral___registers___bits___definition.html#gae2de45b22180cee8e9b3fef000869af3',1,'stm32f407xx_matlab.h']]], - ['can_5ffa1r_5ffact14_5fmsk_2773',['CAN_FA1R_FACT14_Msk',['../group___peripheral___registers___bits___definition.html#ga5aad7b1d23bd498ecd99b4adcb239560',1,'stm32f407xx_matlab.h']]], - ['can_5ffa1r_5ffact14_5fpos_2774',['CAN_FA1R_FACT14_Pos',['../group___peripheral___registers___bits___definition.html#ga8afb5078389340fd934c7f18978f45ce',1,'stm32f407xx_matlab.h']]], - ['can_5ffa1r_5ffact15_2775',['CAN_FA1R_FACT15',['../group___peripheral___registers___bits___definition.html#gab9e8c965500f24cb92a72038e9db3a03',1,'stm32f407xx_matlab.h']]], - ['can_5ffa1r_5ffact15_5fmsk_2776',['CAN_FA1R_FACT15_Msk',['../group___peripheral___registers___bits___definition.html#ga2d0e0b9363ac2965048f42ce3abc9518',1,'stm32f407xx_matlab.h']]], - ['can_5ffa1r_5ffact15_5fpos_2777',['CAN_FA1R_FACT15_Pos',['../group___peripheral___registers___bits___definition.html#ga83dd3c9202d4e42a35c2b5ccb4eee21b',1,'stm32f407xx_matlab.h']]], - ['can_5ffa1r_5ffact16_2778',['CAN_FA1R_FACT16',['../group___peripheral___registers___bits___definition.html#gae4054fdf1fced195e59509a2282fd023',1,'stm32f407xx_matlab.h']]], - ['can_5ffa1r_5ffact16_5fmsk_2779',['CAN_FA1R_FACT16_Msk',['../group___peripheral___registers___bits___definition.html#ga2b832148df149f3f89b168bf1da68449',1,'stm32f407xx_matlab.h']]], - ['can_5ffa1r_5ffact16_5fpos_2780',['CAN_FA1R_FACT16_Pos',['../group___peripheral___registers___bits___definition.html#ga0dd1b09262007ca3c8753891838f2291',1,'stm32f407xx_matlab.h']]], - ['can_5ffa1r_5ffact17_2781',['CAN_FA1R_FACT17',['../group___peripheral___registers___bits___definition.html#ga3a0970d03bb791397495af0762f54d65',1,'stm32f407xx_matlab.h']]], - ['can_5ffa1r_5ffact17_5fmsk_2782',['CAN_FA1R_FACT17_Msk',['../group___peripheral___registers___bits___definition.html#gaec1081e22c20c398d0a24cf2dba852ba',1,'stm32f407xx_matlab.h']]], - ['can_5ffa1r_5ffact17_5fpos_2783',['CAN_FA1R_FACT17_Pos',['../group___peripheral___registers___bits___definition.html#ga061545e7d6c13e4699c81dc71e7ac59d',1,'stm32f407xx_matlab.h']]], - ['can_5ffa1r_5ffact18_2784',['CAN_FA1R_FACT18',['../group___peripheral___registers___bits___definition.html#ga98ba61a8ef9d4e5cea606148281e432d',1,'stm32f407xx_matlab.h']]], - ['can_5ffa1r_5ffact18_5fmsk_2785',['CAN_FA1R_FACT18_Msk',['../group___peripheral___registers___bits___definition.html#ga0844889fa76d91d278d5694d916a04ca',1,'stm32f407xx_matlab.h']]], - ['can_5ffa1r_5ffact18_5fpos_2786',['CAN_FA1R_FACT18_Pos',['../group___peripheral___registers___bits___definition.html#gaccded4c9f678c1e12ecd3f296eaa6f6b',1,'stm32f407xx_matlab.h']]], - ['can_5ffa1r_5ffact19_2787',['CAN_FA1R_FACT19',['../group___peripheral___registers___bits___definition.html#ga87064c634cec6fc2ee70fecbb04b92c2',1,'stm32f407xx_matlab.h']]], - ['can_5ffa1r_5ffact19_5fmsk_2788',['CAN_FA1R_FACT19_Msk',['../group___peripheral___registers___bits___definition.html#ga74353cfdb58079f47563079de3fd778b',1,'stm32f407xx_matlab.h']]], - ['can_5ffa1r_5ffact19_5fpos_2789',['CAN_FA1R_FACT19_Pos',['../group___peripheral___registers___bits___definition.html#ga707b4f7a3fd6e7ed30c17c5cd1933ef3',1,'stm32f407xx_matlab.h']]], - ['can_5ffa1r_5ffact1_5fmsk_2790',['CAN_FA1R_FACT1_Msk',['../group___peripheral___registers___bits___definition.html#ga10ee3a44fa9dc10a77c9a0668a19ddab',1,'stm32f407xx_matlab.h']]], - ['can_5ffa1r_5ffact1_5fpos_2791',['CAN_FA1R_FACT1_Pos',['../group___peripheral___registers___bits___definition.html#gabd6506d842c27928a8647942fbdb0602',1,'stm32f407xx_matlab.h']]], - ['can_5ffa1r_5ffact2_2792',['CAN_FA1R_FACT2',['../group___peripheral___registers___bits___definition.html#ga66354c26d0252cc86729365b315a69ee',1,'stm32f407xx_matlab.h']]], - ['can_5ffa1r_5ffact20_2793',['CAN_FA1R_FACT20',['../group___peripheral___registers___bits___definition.html#gaa0222f2ac5c4d4b9e6382d4dd8286bb2',1,'stm32f407xx_matlab.h']]], - ['can_5ffa1r_5ffact20_5fmsk_2794',['CAN_FA1R_FACT20_Msk',['../group___peripheral___registers___bits___definition.html#ga093d17300bad7b8fa43bd6d264b07217',1,'stm32f407xx_matlab.h']]], - ['can_5ffa1r_5ffact20_5fpos_2795',['CAN_FA1R_FACT20_Pos',['../group___peripheral___registers___bits___definition.html#ga0a3d2f351f0a92a5604b01e36a921de2',1,'stm32f407xx_matlab.h']]], - ['can_5ffa1r_5ffact21_2796',['CAN_FA1R_FACT21',['../group___peripheral___registers___bits___definition.html#ga22534866322499e9d05513f0d41754fe',1,'stm32f407xx_matlab.h']]], - ['can_5ffa1r_5ffact21_5fmsk_2797',['CAN_FA1R_FACT21_Msk',['../group___peripheral___registers___bits___definition.html#ga4bcf854bcce93e28d97db435631b81d8',1,'stm32f407xx_matlab.h']]], - ['can_5ffa1r_5ffact21_5fpos_2798',['CAN_FA1R_FACT21_Pos',['../group___peripheral___registers___bits___definition.html#gae280cc92b21856b1da77deef88ae0aea',1,'stm32f407xx_matlab.h']]], - ['can_5ffa1r_5ffact22_2799',['CAN_FA1R_FACT22',['../group___peripheral___registers___bits___definition.html#gad9febd35acb8257833bf9dbbe18b063b',1,'stm32f407xx_matlab.h']]], - ['can_5ffa1r_5ffact22_5fmsk_2800',['CAN_FA1R_FACT22_Msk',['../group___peripheral___registers___bits___definition.html#ga1090ef53e33de146fb08fdee8e8874f9',1,'stm32f407xx_matlab.h']]], - ['can_5ffa1r_5ffact22_5fpos_2801',['CAN_FA1R_FACT22_Pos',['../group___peripheral___registers___bits___definition.html#gae195ba574d695a543786b5a60e2535d3',1,'stm32f407xx_matlab.h']]], - ['can_5ffa1r_5ffact23_2802',['CAN_FA1R_FACT23',['../group___peripheral___registers___bits___definition.html#ga12e95e773be98669c171971d3be8cc8b',1,'stm32f407xx_matlab.h']]], - ['can_5ffa1r_5ffact23_5fmsk_2803',['CAN_FA1R_FACT23_Msk',['../group___peripheral___registers___bits___definition.html#ga64eea4ed2c7c6a0c0c1a1b2e4acfd32f',1,'stm32f407xx_matlab.h']]], - ['can_5ffa1r_5ffact23_5fpos_2804',['CAN_FA1R_FACT23_Pos',['../group___peripheral___registers___bits___definition.html#ga36f892196608ea5f8567c9027e5f8f36',1,'stm32f407xx_matlab.h']]], - ['can_5ffa1r_5ffact24_2805',['CAN_FA1R_FACT24',['../group___peripheral___registers___bits___definition.html#ga63dd04052a79614027b3efe30ea1724a',1,'stm32f407xx_matlab.h']]], - ['can_5ffa1r_5ffact24_5fmsk_2806',['CAN_FA1R_FACT24_Msk',['../group___peripheral___registers___bits___definition.html#ga57f3f41e8a31cd07be66cbd05eabfbe4',1,'stm32f407xx_matlab.h']]], - ['can_5ffa1r_5ffact24_5fpos_2807',['CAN_FA1R_FACT24_Pos',['../group___peripheral___registers___bits___definition.html#ga311ef25d716f12e324d3dccbe2f8ec66',1,'stm32f407xx_matlab.h']]], - ['can_5ffa1r_5ffact25_2808',['CAN_FA1R_FACT25',['../group___peripheral___registers___bits___definition.html#ga994fbfb885e73b4221b64f8bcb19631e',1,'stm32f407xx_matlab.h']]], - ['can_5ffa1r_5ffact25_5fmsk_2809',['CAN_FA1R_FACT25_Msk',['../group___peripheral___registers___bits___definition.html#ga0d5955b25bf2b59795d8864719ff0bf0',1,'stm32f407xx_matlab.h']]], - ['can_5ffa1r_5ffact25_5fpos_2810',['CAN_FA1R_FACT25_Pos',['../group___peripheral___registers___bits___definition.html#ga5dfb5fd56f8ed22e24ee02ebbf37d58c',1,'stm32f407xx_matlab.h']]], - ['can_5ffa1r_5ffact26_2811',['CAN_FA1R_FACT26',['../group___peripheral___registers___bits___definition.html#gaf64c2c798a0c3bbe2745bf603e034a89',1,'stm32f407xx_matlab.h']]], - ['can_5ffa1r_5ffact26_5fmsk_2812',['CAN_FA1R_FACT26_Msk',['../group___peripheral___registers___bits___definition.html#gac30095caad0d9f62fc1aa0ba0ddd70c7',1,'stm32f407xx_matlab.h']]], - ['can_5ffa1r_5ffact26_5fpos_2813',['CAN_FA1R_FACT26_Pos',['../group___peripheral___registers___bits___definition.html#ga01ddadbe0437498108088593d769776e',1,'stm32f407xx_matlab.h']]], - ['can_5ffa1r_5ffact27_2814',['CAN_FA1R_FACT27',['../group___peripheral___registers___bits___definition.html#gaf72e900b51c3c380a81832d0314643c2',1,'stm32f407xx_matlab.h']]], - ['can_5ffa1r_5ffact27_5fmsk_2815',['CAN_FA1R_FACT27_Msk',['../group___peripheral___registers___bits___definition.html#gae4c4ecc7e23c652a42b36df4494bc0bf',1,'stm32f407xx_matlab.h']]], - ['can_5ffa1r_5ffact27_5fpos_2816',['CAN_FA1R_FACT27_Pos',['../group___peripheral___registers___bits___definition.html#ga20dee91cf99643da8f3cbcabefe188dc',1,'stm32f407xx_matlab.h']]], - ['can_5ffa1r_5ffact2_5fmsk_2817',['CAN_FA1R_FACT2_Msk',['../group___peripheral___registers___bits___definition.html#gaafc57ac18afd7bd0eb14e84dbc265a83',1,'stm32f407xx_matlab.h']]], - ['can_5ffa1r_5ffact2_5fpos_2818',['CAN_FA1R_FACT2_Pos',['../group___peripheral___registers___bits___definition.html#gaac70ad8a114259387ba6eb4bf21a2c13',1,'stm32f407xx_matlab.h']]], - ['can_5ffa1r_5ffact3_2819',['CAN_FA1R_FACT3',['../group___peripheral___registers___bits___definition.html#ga087dc5f2bdfe084eb98d2a0d06a29f1d',1,'stm32f407xx_matlab.h']]], - ['can_5ffa1r_5ffact3_5fmsk_2820',['CAN_FA1R_FACT3_Msk',['../group___peripheral___registers___bits___definition.html#ga4b9b6a83d65b39753f8208f45d0d72ce',1,'stm32f407xx_matlab.h']]], - ['can_5ffa1r_5ffact3_5fpos_2821',['CAN_FA1R_FACT3_Pos',['../group___peripheral___registers___bits___definition.html#gaa93067be654983f42daf67ab9da3fbc3',1,'stm32f407xx_matlab.h']]], - ['can_5ffa1r_5ffact4_2822',['CAN_FA1R_FACT4',['../group___peripheral___registers___bits___definition.html#ga6c46367b7e5ea831e34ba4cf824a63da',1,'stm32f407xx_matlab.h']]], - ['can_5ffa1r_5ffact4_5fmsk_2823',['CAN_FA1R_FACT4_Msk',['../group___peripheral___registers___bits___definition.html#ga562dc354461029230ead72878c01ba30',1,'stm32f407xx_matlab.h']]], - ['can_5ffa1r_5ffact4_5fpos_2824',['CAN_FA1R_FACT4_Pos',['../group___peripheral___registers___bits___definition.html#gafd3f42141b00002a6db3db68ecd9909d',1,'stm32f407xx_matlab.h']]], - ['can_5ffa1r_5ffact5_2825',['CAN_FA1R_FACT5',['../group___peripheral___registers___bits___definition.html#ga548238c7babf34116fdb44b4575e2664',1,'stm32f407xx_matlab.h']]], - ['can_5ffa1r_5ffact5_5fmsk_2826',['CAN_FA1R_FACT5_Msk',['../group___peripheral___registers___bits___definition.html#gabe67ef97c9d6b04fcad49eccad2ce8a1',1,'stm32f407xx_matlab.h']]], - ['can_5ffa1r_5ffact5_5fpos_2827',['CAN_FA1R_FACT5_Pos',['../group___peripheral___registers___bits___definition.html#gaf840e6f2d239bf5fc59c6f3454c2d122',1,'stm32f407xx_matlab.h']]], - ['can_5ffa1r_5ffact6_2828',['CAN_FA1R_FACT6',['../group___peripheral___registers___bits___definition.html#gae403370a70f9ea2b6f9b449cafa6a91c',1,'stm32f407xx_matlab.h']]], - ['can_5ffa1r_5ffact6_5fmsk_2829',['CAN_FA1R_FACT6_Msk',['../group___peripheral___registers___bits___definition.html#gab13ad536db58592d5b4f2beb9c4f0469',1,'stm32f407xx_matlab.h']]], - ['can_5ffa1r_5ffact6_5fpos_2830',['CAN_FA1R_FACT6_Pos',['../group___peripheral___registers___bits___definition.html#ga390f38386d4c2a6940d7dfe88bc4ab70',1,'stm32f407xx_matlab.h']]], - ['can_5ffa1r_5ffact7_2831',['CAN_FA1R_FACT7',['../group___peripheral___registers___bits___definition.html#ga33e9f4334cf3bf9e7e30d5edf278a02b',1,'stm32f407xx_matlab.h']]], - ['can_5ffa1r_5ffact7_5fmsk_2832',['CAN_FA1R_FACT7_Msk',['../group___peripheral___registers___bits___definition.html#ga32a9fa687af9f4bc3800be29ee32a3e6',1,'stm32f407xx_matlab.h']]], - ['can_5ffa1r_5ffact7_5fpos_2833',['CAN_FA1R_FACT7_Pos',['../group___peripheral___registers___bits___definition.html#gade2b7e97d515badec6d07154c8fdec2e',1,'stm32f407xx_matlab.h']]], - ['can_5ffa1r_5ffact8_2834',['CAN_FA1R_FACT8',['../group___peripheral___registers___bits___definition.html#ga0ccbdd2932828bfa1d68777cb595f12e',1,'stm32f407xx_matlab.h']]], - ['can_5ffa1r_5ffact8_5fmsk_2835',['CAN_FA1R_FACT8_Msk',['../group___peripheral___registers___bits___definition.html#ga9addaf5198f1b165bb8a1c5abe8c9a1f',1,'stm32f407xx_matlab.h']]], - ['can_5ffa1r_5ffact8_5fpos_2836',['CAN_FA1R_FACT8_Pos',['../group___peripheral___registers___bits___definition.html#gac34978a6e1dbc7ff9a62d577d0473308',1,'stm32f407xx_matlab.h']]], - ['can_5ffa1r_5ffact9_2837',['CAN_FA1R_FACT9',['../group___peripheral___registers___bits___definition.html#gaf8e4011791e551feeae33c47ef2b6a6a',1,'stm32f407xx_matlab.h']]], - ['can_5ffa1r_5ffact9_5fmsk_2838',['CAN_FA1R_FACT9_Msk',['../group___peripheral___registers___bits___definition.html#ga9cb920b1dd24719e2fe959bc9fa27b2c',1,'stm32f407xx_matlab.h']]], - ['can_5ffa1r_5ffact9_5fpos_2839',['CAN_FA1R_FACT9_Pos',['../group___peripheral___registers___bits___definition.html#ga6bd9a79b3e73c5343df683cb08e213e1',1,'stm32f407xx_matlab.h']]], - ['can_5ffa1r_5ffact_5fmsk_2840',['CAN_FA1R_FACT_Msk',['../group___peripheral___registers___bits___definition.html#ga2f05941c6d7ad0294283a20dc4307a56',1,'stm32f407xx_matlab.h']]], - ['can_5ffa1r_5ffact_5fpos_2841',['CAN_FA1R_FACT_Pos',['../group___peripheral___registers___bits___definition.html#ga21e8eff485fa16ae0d289eacce72bd56',1,'stm32f407xx_matlab.h']]], - ['can_5fffa1r_5fffa_2842',['CAN_FFA1R_FFA',['../group___peripheral___registers___bits___definition.html#ga16fa4bf13579d29b57f7602489d043fe',1,'stm32f407xx_matlab.h']]], - ['can_5fffa1r_5fffa0_2843',['CAN_FFA1R_FFA0',['../group___peripheral___registers___bits___definition.html#ga4b1a0f95bac4fed1a801da0cdbf2a833',1,'stm32f407xx_matlab.h']]], - ['can_5fffa1r_5fffa0_5fmsk_2844',['CAN_FFA1R_FFA0_Msk',['../group___peripheral___registers___bits___definition.html#ga63a732f91a0c26a9e29151486e2af798',1,'stm32f407xx_matlab.h']]], - ['can_5fffa1r_5fffa0_5fpos_2845',['CAN_FFA1R_FFA0_Pos',['../group___peripheral___registers___bits___definition.html#ga8e673e4b99624b2b674c1a0cb814af7d',1,'stm32f407xx_matlab.h']]], - ['can_5fffa1r_5fffa1_2846',['CAN_FFA1R_FFA1',['../group___peripheral___registers___bits___definition.html#gaba35e135e17431de861e57b550421386',1,'stm32f407xx_matlab.h']]], - ['can_5fffa1r_5fffa10_2847',['CAN_FFA1R_FFA10',['../group___peripheral___registers___bits___definition.html#ga8ac0384eab9b0cfdb491a960279fc438',1,'stm32f407xx_matlab.h']]], - ['can_5fffa1r_5fffa10_5fmsk_2848',['CAN_FFA1R_FFA10_Msk',['../group___peripheral___registers___bits___definition.html#ga7ac746965c32524f17be780be809bf29',1,'stm32f407xx_matlab.h']]], - ['can_5fffa1r_5fffa10_5fpos_2849',['CAN_FFA1R_FFA10_Pos',['../group___peripheral___registers___bits___definition.html#gabf1221d604b06bcee9432d1438ddd2f1',1,'stm32f407xx_matlab.h']]], - ['can_5fffa1r_5fffa11_2850',['CAN_FFA1R_FFA11',['../group___peripheral___registers___bits___definition.html#gaacd7e79ab503ec5143b5848edac71817',1,'stm32f407xx_matlab.h']]], - ['can_5fffa1r_5fffa11_5fmsk_2851',['CAN_FFA1R_FFA11_Msk',['../group___peripheral___registers___bits___definition.html#gab5fec989f32c99595a73b0910dc92787',1,'stm32f407xx_matlab.h']]], - ['can_5fffa1r_5fffa11_5fpos_2852',['CAN_FFA1R_FFA11_Pos',['../group___peripheral___registers___bits___definition.html#ga4435daea27c23de8ac235d2dc6ce988d',1,'stm32f407xx_matlab.h']]], - ['can_5fffa1r_5fffa12_2853',['CAN_FFA1R_FFA12',['../group___peripheral___registers___bits___definition.html#ga7873f1526050f5e666c22fb6a7e68b65',1,'stm32f407xx_matlab.h']]], - ['can_5fffa1r_5fffa12_5fmsk_2854',['CAN_FFA1R_FFA12_Msk',['../group___peripheral___registers___bits___definition.html#ga0e3859f0d8f9b1a52beaa72de195222b',1,'stm32f407xx_matlab.h']]], - ['can_5fffa1r_5fffa12_5fpos_2855',['CAN_FFA1R_FFA12_Pos',['../group___peripheral___registers___bits___definition.html#ga088625981d2bbc9e281ad21fb592022d',1,'stm32f407xx_matlab.h']]], - ['can_5fffa1r_5fffa13_2856',['CAN_FFA1R_FFA13',['../group___peripheral___registers___bits___definition.html#gac74339b69a2e6f67df9b6e136089c0ee',1,'stm32f407xx_matlab.h']]], - ['can_5fffa1r_5fffa13_5fmsk_2857',['CAN_FFA1R_FFA13_Msk',['../group___peripheral___registers___bits___definition.html#ga2ff3bf3a563646cf44a6dacfa1652cb0',1,'stm32f407xx_matlab.h']]], - ['can_5fffa1r_5fffa13_5fpos_2858',['CAN_FFA1R_FFA13_Pos',['../group___peripheral___registers___bits___definition.html#ga89646cfa2e98d87000f27e4bd22e0d48',1,'stm32f407xx_matlab.h']]], - ['can_5fffa1r_5fffa14_2859',['CAN_FFA1R_FFA14',['../group___peripheral___registers___bits___definition.html#ga6bdc473bfe275c940734d2c1775d982d',1,'stm32f407xx_matlab.h']]], - ['can_5fffa1r_5fffa14_5fmsk_2860',['CAN_FFA1R_FFA14_Msk',['../group___peripheral___registers___bits___definition.html#ga10da524219356b7c7aa0fff90ef718f1',1,'stm32f407xx_matlab.h']]], - ['can_5fffa1r_5fffa14_5fpos_2861',['CAN_FFA1R_FFA14_Pos',['../group___peripheral___registers___bits___definition.html#gaaf8560a004719b166cfaf281a67f79e1',1,'stm32f407xx_matlab.h']]], - ['can_5fffa1r_5fffa15_2862',['CAN_FFA1R_FFA15',['../group___peripheral___registers___bits___definition.html#ga8c72b1a17bc4a9c7ec3251af645e290d',1,'stm32f407xx_matlab.h']]], - ['can_5fffa1r_5fffa15_5fmsk_2863',['CAN_FFA1R_FFA15_Msk',['../group___peripheral___registers___bits___definition.html#gaef1dfb17246f207f68f459a0f7f440df',1,'stm32f407xx_matlab.h']]], - ['can_5fffa1r_5fffa15_5fpos_2864',['CAN_FFA1R_FFA15_Pos',['../group___peripheral___registers___bits___definition.html#gae41306fbd5429b13073a556e9c851470',1,'stm32f407xx_matlab.h']]], - ['can_5fffa1r_5fffa16_2865',['CAN_FFA1R_FFA16',['../group___peripheral___registers___bits___definition.html#gadac411834c4a2118354f7b160c292dd6',1,'stm32f407xx_matlab.h']]], - ['can_5fffa1r_5fffa16_5fmsk_2866',['CAN_FFA1R_FFA16_Msk',['../group___peripheral___registers___bits___definition.html#ga0f03a68e7428cc6c56b0f755246ecff4',1,'stm32f407xx_matlab.h']]], - ['can_5fffa1r_5fffa16_5fpos_2867',['CAN_FFA1R_FFA16_Pos',['../group___peripheral___registers___bits___definition.html#ga799996bdb9bc84e5bcd03e7d75f3ec4e',1,'stm32f407xx_matlab.h']]], - ['can_5fffa1r_5fffa17_2868',['CAN_FFA1R_FFA17',['../group___peripheral___registers___bits___definition.html#gaf73b3c3d378246929f1092416546aa45',1,'stm32f407xx_matlab.h']]], - ['can_5fffa1r_5fffa17_5fmsk_2869',['CAN_FFA1R_FFA17_Msk',['../group___peripheral___registers___bits___definition.html#ga9eccf63346520ce0fc6d72774b62957d',1,'stm32f407xx_matlab.h']]], - ['can_5fffa1r_5fffa17_5fpos_2870',['CAN_FFA1R_FFA17_Pos',['../group___peripheral___registers___bits___definition.html#gaa772ef7c7e8e47f6c54d342f83a6f4ab',1,'stm32f407xx_matlab.h']]], - ['can_5fffa1r_5fffa18_2871',['CAN_FFA1R_FFA18',['../group___peripheral___registers___bits___definition.html#gadc2bf72b9f9c57ddcaf09449a208a4ef',1,'stm32f407xx_matlab.h']]], - ['can_5fffa1r_5fffa18_5fmsk_2872',['CAN_FFA1R_FFA18_Msk',['../group___peripheral___registers___bits___definition.html#gad328f6b0426811376fb96edd92ee17dd',1,'stm32f407xx_matlab.h']]], - ['can_5fffa1r_5fffa18_5fpos_2873',['CAN_FFA1R_FFA18_Pos',['../group___peripheral___registers___bits___definition.html#ga89199c68d5354b179d13f125beb8866b',1,'stm32f407xx_matlab.h']]], - ['can_5fffa1r_5fffa19_2874',['CAN_FFA1R_FFA19',['../group___peripheral___registers___bits___definition.html#ga7a2371494a1ab03e90ff471b4e88d4eb',1,'stm32f407xx_matlab.h']]], - ['can_5fffa1r_5fffa19_5fmsk_2875',['CAN_FFA1R_FFA19_Msk',['../group___peripheral___registers___bits___definition.html#gaffc95b44aaf8c77fb00666241311d78b',1,'stm32f407xx_matlab.h']]], - ['can_5fffa1r_5fffa19_5fpos_2876',['CAN_FFA1R_FFA19_Pos',['../group___peripheral___registers___bits___definition.html#ga0d1c21deb9827442f5607348e34abc98',1,'stm32f407xx_matlab.h']]], - ['can_5fffa1r_5fffa1_5fmsk_2877',['CAN_FFA1R_FFA1_Msk',['../group___peripheral___registers___bits___definition.html#ga692f0c606853b771a99e052cd0fe0995',1,'stm32f407xx_matlab.h']]], - ['can_5fffa1r_5fffa1_5fpos_2878',['CAN_FFA1R_FFA1_Pos',['../group___peripheral___registers___bits___definition.html#gafce5ceec640174f6e6c06aafc980bb82',1,'stm32f407xx_matlab.h']]], - ['can_5fffa1r_5fffa2_2879',['CAN_FFA1R_FFA2',['../group___peripheral___registers___bits___definition.html#ga5b64393197f5cd0bd6e4853828a98065',1,'stm32f407xx_matlab.h']]], - ['can_5fffa1r_5fffa20_2880',['CAN_FFA1R_FFA20',['../group___peripheral___registers___bits___definition.html#ga7359bb245f5bc6f9298bdae577c7f2d1',1,'stm32f407xx_matlab.h']]], - ['can_5fffa1r_5fffa20_5fmsk_2881',['CAN_FFA1R_FFA20_Msk',['../group___peripheral___registers___bits___definition.html#ga87cf0758a707ef8bae3f14ca07009487',1,'stm32f407xx_matlab.h']]], - ['can_5fffa1r_5fffa20_5fpos_2882',['CAN_FFA1R_FFA20_Pos',['../group___peripheral___registers___bits___definition.html#ga077f389aa603e8dc048bc6af4cbec654',1,'stm32f407xx_matlab.h']]], - ['can_5fffa1r_5fffa21_2883',['CAN_FFA1R_FFA21',['../group___peripheral___registers___bits___definition.html#ga4390bdfd6fb22feb6b64de18b45304d8',1,'stm32f407xx_matlab.h']]], - ['can_5fffa1r_5fffa21_5fmsk_2884',['CAN_FFA1R_FFA21_Msk',['../group___peripheral___registers___bits___definition.html#ga49398f11989a0fac67eea74c169add65',1,'stm32f407xx_matlab.h']]], - ['can_5fffa1r_5fffa21_5fpos_2885',['CAN_FFA1R_FFA21_Pos',['../group___peripheral___registers___bits___definition.html#ga6b4ab4a10e2a0cb2bb32bee0c1d1fe8d',1,'stm32f407xx_matlab.h']]], - ['can_5fffa1r_5fffa22_2886',['CAN_FFA1R_FFA22',['../group___peripheral___registers___bits___definition.html#ga029cfaf7e13f5214dd3e056b0984b1d8',1,'stm32f407xx_matlab.h']]], - ['can_5fffa1r_5fffa22_5fmsk_2887',['CAN_FFA1R_FFA22_Msk',['../group___peripheral___registers___bits___definition.html#gab501571f610235c7a89d5ed6148ee4bb',1,'stm32f407xx_matlab.h']]], - ['can_5fffa1r_5fffa22_5fpos_2888',['CAN_FFA1R_FFA22_Pos',['../group___peripheral___registers___bits___definition.html#ga08da105ae70ea87f80128a8451fb14d8',1,'stm32f407xx_matlab.h']]], - ['can_5fffa1r_5fffa23_2889',['CAN_FFA1R_FFA23',['../group___peripheral___registers___bits___definition.html#gad969df81e8f4d8902ddf9ac76c7ff9d2',1,'stm32f407xx_matlab.h']]], - ['can_5fffa1r_5fffa23_5fmsk_2890',['CAN_FFA1R_FFA23_Msk',['../group___peripheral___registers___bits___definition.html#ga1258ce7b88510c0942cca2ec7443c749',1,'stm32f407xx_matlab.h']]], - ['can_5fffa1r_5fffa23_5fpos_2891',['CAN_FFA1R_FFA23_Pos',['../group___peripheral___registers___bits___definition.html#gabcc71274e0234226241674e65a697913',1,'stm32f407xx_matlab.h']]], - ['can_5fffa1r_5fffa24_2892',['CAN_FFA1R_FFA24',['../group___peripheral___registers___bits___definition.html#ga4d1adf29e37676017c67204623a45985',1,'stm32f407xx_matlab.h']]], - ['can_5fffa1r_5fffa24_5fmsk_2893',['CAN_FFA1R_FFA24_Msk',['../group___peripheral___registers___bits___definition.html#ga5fe02633e558b53290fc5645ac903318',1,'stm32f407xx_matlab.h']]], - ['can_5fffa1r_5fffa24_5fpos_2894',['CAN_FFA1R_FFA24_Pos',['../group___peripheral___registers___bits___definition.html#gaabae42ffc06637b9ac6424b2019cef2a',1,'stm32f407xx_matlab.h']]], - ['can_5fffa1r_5fffa25_2895',['CAN_FFA1R_FFA25',['../group___peripheral___registers___bits___definition.html#ga40553faf034d88e215c71d40c08f774e',1,'stm32f407xx_matlab.h']]], - ['can_5fffa1r_5fffa25_5fmsk_2896',['CAN_FFA1R_FFA25_Msk',['../group___peripheral___registers___bits___definition.html#gaf586e3c813baaa9026b78e158c90df0c',1,'stm32f407xx_matlab.h']]], - ['can_5fffa1r_5fffa25_5fpos_2897',['CAN_FFA1R_FFA25_Pos',['../group___peripheral___registers___bits___definition.html#gafcf4053a355ef612cbf6a56415cf8583',1,'stm32f407xx_matlab.h']]], - ['can_5fffa1r_5fffa26_2898',['CAN_FFA1R_FFA26',['../group___peripheral___registers___bits___definition.html#ga1d347ff7528138f59d223adf7c838440',1,'stm32f407xx_matlab.h']]], - ['can_5fffa1r_5fffa26_5fmsk_2899',['CAN_FFA1R_FFA26_Msk',['../group___peripheral___registers___bits___definition.html#gac224810fe7b45a273faa3d655bc64d44',1,'stm32f407xx_matlab.h']]], - ['can_5fffa1r_5fffa26_5fpos_2900',['CAN_FFA1R_FFA26_Pos',['../group___peripheral___registers___bits___definition.html#ga24094060ed59ce5c405fbb2f4212694a',1,'stm32f407xx_matlab.h']]], - ['can_5fffa1r_5fffa27_2901',['CAN_FFA1R_FFA27',['../group___peripheral___registers___bits___definition.html#ga4ace5c7e4d87bebdc36d66de6cef7442',1,'stm32f407xx_matlab.h']]], - ['can_5fffa1r_5fffa27_5fmsk_2902',['CAN_FFA1R_FFA27_Msk',['../group___peripheral___registers___bits___definition.html#gae312771a3ea200b9df91e30ddc1392d2',1,'stm32f407xx_matlab.h']]], - ['can_5fffa1r_5fffa27_5fpos_2903',['CAN_FFA1R_FFA27_Pos',['../group___peripheral___registers___bits___definition.html#ga7cf95c6d995ed5e1dded3e5d55020cbf',1,'stm32f407xx_matlab.h']]], - ['can_5fffa1r_5fffa2_5fmsk_2904',['CAN_FFA1R_FFA2_Msk',['../group___peripheral___registers___bits___definition.html#ga197d8ba6187ed4b6842505ae99104992',1,'stm32f407xx_matlab.h']]], - ['can_5fffa1r_5fffa2_5fpos_2905',['CAN_FFA1R_FFA2_Pos',['../group___peripheral___registers___bits___definition.html#gaa7a54c1f4d9f576917d36df988c7cce0',1,'stm32f407xx_matlab.h']]], - ['can_5fffa1r_5fffa3_2906',['CAN_FFA1R_FFA3',['../group___peripheral___registers___bits___definition.html#ga111ce1e4500e2c0f543128dddbe941e9',1,'stm32f407xx_matlab.h']]], - ['can_5fffa1r_5fffa3_5fmsk_2907',['CAN_FFA1R_FFA3_Msk',['../group___peripheral___registers___bits___definition.html#gae6c1a5ee723cd899b098e277386d86a4',1,'stm32f407xx_matlab.h']]], - ['can_5fffa1r_5fffa3_5fpos_2908',['CAN_FFA1R_FFA3_Pos',['../group___peripheral___registers___bits___definition.html#ga57037066dc96ae3ac826b462ab6916ac',1,'stm32f407xx_matlab.h']]], - ['can_5fffa1r_5fffa4_2909',['CAN_FFA1R_FFA4',['../group___peripheral___registers___bits___definition.html#ga8a824c777e7fea25f580bc313ed2ece6',1,'stm32f407xx_matlab.h']]], - ['can_5fffa1r_5fffa4_5fmsk_2910',['CAN_FFA1R_FFA4_Msk',['../group___peripheral___registers___bits___definition.html#ga9d03c010394020f6172d2fceba9e02ea',1,'stm32f407xx_matlab.h']]], - ['can_5fffa1r_5fffa4_5fpos_2911',['CAN_FFA1R_FFA4_Pos',['../group___peripheral___registers___bits___definition.html#ga69b604f0eea6a02bb71611b830ff32c2',1,'stm32f407xx_matlab.h']]], - ['can_5fffa1r_5fffa5_2912',['CAN_FFA1R_FFA5',['../group___peripheral___registers___bits___definition.html#gabd571c9c746225e9b856ce3a46c3bb2f',1,'stm32f407xx_matlab.h']]], - ['can_5fffa1r_5fffa5_5fmsk_2913',['CAN_FFA1R_FFA5_Msk',['../group___peripheral___registers___bits___definition.html#ga51918688a8985d110c995bf441a4f763',1,'stm32f407xx_matlab.h']]], - ['can_5fffa1r_5fffa5_5fpos_2914',['CAN_FFA1R_FFA5_Pos',['../group___peripheral___registers___bits___definition.html#gacacfe37b33ceac03e2abad22e7bbce28',1,'stm32f407xx_matlab.h']]], - ['can_5fffa1r_5fffa6_2915',['CAN_FFA1R_FFA6',['../group___peripheral___registers___bits___definition.html#gab2afec157fe9684f1fa4b4401500f035',1,'stm32f407xx_matlab.h']]], - ['can_5fffa1r_5fffa6_5fmsk_2916',['CAN_FFA1R_FFA6_Msk',['../group___peripheral___registers___bits___definition.html#ga01b319af3e2f1b59d544501192e24b68',1,'stm32f407xx_matlab.h']]], - ['can_5fffa1r_5fffa6_5fpos_2917',['CAN_FFA1R_FFA6_Pos',['../group___peripheral___registers___bits___definition.html#ga165fe8139c6eb2b3971def9579d1d497',1,'stm32f407xx_matlab.h']]], - ['can_5fffa1r_5fffa7_2918',['CAN_FFA1R_FFA7',['../group___peripheral___registers___bits___definition.html#ga2d70e150cfd4866ea6b0a264ad45f51b',1,'stm32f407xx_matlab.h']]], - ['can_5fffa1r_5fffa7_5fmsk_2919',['CAN_FFA1R_FFA7_Msk',['../group___peripheral___registers___bits___definition.html#ga62ff14edc65346f9e08e9f259a7fd45a',1,'stm32f407xx_matlab.h']]], - ['can_5fffa1r_5fffa7_5fpos_2920',['CAN_FFA1R_FFA7_Pos',['../group___peripheral___registers___bits___definition.html#gab1f1bf154b1ffb5f5e1f7bb5d8b0a300',1,'stm32f407xx_matlab.h']]], - ['can_5fffa1r_5fffa8_2921',['CAN_FFA1R_FFA8',['../group___peripheral___registers___bits___definition.html#gafa802583aa70aadeb46366ff98eccaf1',1,'stm32f407xx_matlab.h']]], - ['can_5fffa1r_5fffa8_5fmsk_2922',['CAN_FFA1R_FFA8_Msk',['../group___peripheral___registers___bits___definition.html#ga141132dbc9c5d5a0a125c8aae363445b',1,'stm32f407xx_matlab.h']]], - ['can_5fffa1r_5fffa8_5fpos_2923',['CAN_FFA1R_FFA8_Pos',['../group___peripheral___registers___bits___definition.html#ga9092a75173fa128b0d1fb7616df2cd07',1,'stm32f407xx_matlab.h']]], - ['can_5fffa1r_5fffa9_2924',['CAN_FFA1R_FFA9',['../group___peripheral___registers___bits___definition.html#ga6ee7da4c7e42fa7576d965c4bf94c089',1,'stm32f407xx_matlab.h']]], - ['can_5fffa1r_5fffa9_5fmsk_2925',['CAN_FFA1R_FFA9_Msk',['../group___peripheral___registers___bits___definition.html#ga3270aaea7647ea2c5ccbaf747ceffb5b',1,'stm32f407xx_matlab.h']]], - ['can_5fffa1r_5fffa9_5fpos_2926',['CAN_FFA1R_FFA9_Pos',['../group___peripheral___registers___bits___definition.html#gaa26f182a322fb252ccb2c4e573677ad7',1,'stm32f407xx_matlab.h']]], - ['can_5fffa1r_5fffa_5fmsk_2927',['CAN_FFA1R_FFA_Msk',['../group___peripheral___registers___bits___definition.html#ga9d6813f166c5bc78b7ceabcaf544202e',1,'stm32f407xx_matlab.h']]], - ['can_5fffa1r_5fffa_5fpos_2928',['CAN_FFA1R_FFA_Pos',['../group___peripheral___registers___bits___definition.html#gac8a13781d7e62a0c62344a9e3d32c31b',1,'stm32f407xx_matlab.h']]], - ['can_5ffifomailbox_5ftypedef_2929',['CAN_FIFOMailBox_TypeDef',['../struct_c_a_n___f_i_f_o_mail_box___type_def.html',1,'']]], - ['can_5ffilterregister_5ftypedef_2930',['CAN_FilterRegister_TypeDef',['../struct_c_a_n___filter_register___type_def.html',1,'']]], - ['can_5ffm1r_5ffbm_2931',['CAN_FM1R_FBM',['../group___peripheral___registers___bits___definition.html#ga481099e17a895e92cfbcfca617d52860',1,'stm32f407xx_matlab.h']]], - ['can_5ffm1r_5ffbm0_2932',['CAN_FM1R_FBM0',['../group___peripheral___registers___bits___definition.html#ga2d95ff05ed6ef9a38e9af9c0d3db3687',1,'stm32f407xx_matlab.h']]], - ['can_5ffm1r_5ffbm0_5fmsk_2933',['CAN_FM1R_FBM0_Msk',['../group___peripheral___registers___bits___definition.html#ga19e1fd75a24ae366d58b0a18e15f38bf',1,'stm32f407xx_matlab.h']]], - ['can_5ffm1r_5ffbm0_5fpos_2934',['CAN_FM1R_FBM0_Pos',['../group___peripheral___registers___bits___definition.html#gab47e86b4f2e3c77569cfe84fbcb8806b',1,'stm32f407xx_matlab.h']]], - ['can_5ffm1r_5ffbm1_2935',['CAN_FM1R_FBM1',['../group___peripheral___registers___bits___definition.html#gac2839d73344a7601aa22b5ed3fc0e5d1',1,'stm32f407xx_matlab.h']]], - ['can_5ffm1r_5ffbm10_2936',['CAN_FM1R_FBM10',['../group___peripheral___registers___bits___definition.html#ga0a98c6bde07c570463b6c0e32c0f6805',1,'stm32f407xx_matlab.h']]], - ['can_5ffm1r_5ffbm10_5fmsk_2937',['CAN_FM1R_FBM10_Msk',['../group___peripheral___registers___bits___definition.html#gaeb10a1a029fdb320217c7443225df7f8',1,'stm32f407xx_matlab.h']]], - ['can_5ffm1r_5ffbm10_5fpos_2938',['CAN_FM1R_FBM10_Pos',['../group___peripheral___registers___bits___definition.html#gab4c4d40f98e3c5e6116b323184afca0a',1,'stm32f407xx_matlab.h']]], - ['can_5ffm1r_5ffbm11_2939',['CAN_FM1R_FBM11',['../group___peripheral___registers___bits___definition.html#gab88796333c19954176ef77208cae4964',1,'stm32f407xx_matlab.h']]], - ['can_5ffm1r_5ffbm11_5fmsk_2940',['CAN_FM1R_FBM11_Msk',['../group___peripheral___registers___bits___definition.html#gaaa8a7616c4e1d6b08a96a629877107ad',1,'stm32f407xx_matlab.h']]], - ['can_5ffm1r_5ffbm11_5fpos_2941',['CAN_FM1R_FBM11_Pos',['../group___peripheral___registers___bits___definition.html#ga8310bf4c9b121dad00152f0d9e0aaf3d',1,'stm32f407xx_matlab.h']]], - ['can_5ffm1r_5ffbm12_2942',['CAN_FM1R_FBM12',['../group___peripheral___registers___bits___definition.html#ga858eaac0a8e23c03e13e5c1736bf9842',1,'stm32f407xx_matlab.h']]], - ['can_5ffm1r_5ffbm12_5fmsk_2943',['CAN_FM1R_FBM12_Msk',['../group___peripheral___registers___bits___definition.html#gae8b7c4c9581b2f876fe0cdf0bba3edaf',1,'stm32f407xx_matlab.h']]], - ['can_5ffm1r_5ffbm12_5fpos_2944',['CAN_FM1R_FBM12_Pos',['../group___peripheral___registers___bits___definition.html#ga0c1c28f5a8c8f6e7c1203c3268307e7d',1,'stm32f407xx_matlab.h']]], - ['can_5ffm1r_5ffbm13_2945',['CAN_FM1R_FBM13',['../group___peripheral___registers___bits___definition.html#gaf03b553802edd3ae23b70e97228b6dcc',1,'stm32f407xx_matlab.h']]], - ['can_5ffm1r_5ffbm13_5fmsk_2946',['CAN_FM1R_FBM13_Msk',['../group___peripheral___registers___bits___definition.html#ga13e0f2dc1023e882b4f2392c68444858',1,'stm32f407xx_matlab.h']]], - ['can_5ffm1r_5ffbm13_5fpos_2947',['CAN_FM1R_FBM13_Pos',['../group___peripheral___registers___bits___definition.html#ga510dd73a783e59a7d85c00d8190c89db',1,'stm32f407xx_matlab.h']]], - ['can_5ffm1r_5ffbm14_2948',['CAN_FM1R_FBM14',['../group___peripheral___registers___bits___definition.html#gae348cc5bec6eecd8a188c3e90a9618d1',1,'stm32f407xx_matlab.h']]], - ['can_5ffm1r_5ffbm14_5fmsk_2949',['CAN_FM1R_FBM14_Msk',['../group___peripheral___registers___bits___definition.html#ga0bc6cdb01d2d74ae091d20b682ceb0e3',1,'stm32f407xx_matlab.h']]], - ['can_5ffm1r_5ffbm14_5fpos_2950',['CAN_FM1R_FBM14_Pos',['../group___peripheral___registers___bits___definition.html#ga6b3286a1f53a442b35a01c37ea2f1f08',1,'stm32f407xx_matlab.h']]], - ['can_5ffm1r_5ffbm15_2951',['CAN_FM1R_FBM15',['../group___peripheral___registers___bits___definition.html#ga815c710d287cec5c46a901d01e4cac76',1,'stm32f407xx_matlab.h']]], - ['can_5ffm1r_5ffbm15_5fmsk_2952',['CAN_FM1R_FBM15_Msk',['../group___peripheral___registers___bits___definition.html#ga6d59e547e543eeddb35d6d003b18458c',1,'stm32f407xx_matlab.h']]], - ['can_5ffm1r_5ffbm15_5fpos_2953',['CAN_FM1R_FBM15_Pos',['../group___peripheral___registers___bits___definition.html#gafa1a315f40ac71ced3066bf3edd9b459',1,'stm32f407xx_matlab.h']]], - ['can_5ffm1r_5ffbm16_2954',['CAN_FM1R_FBM16',['../group___peripheral___registers___bits___definition.html#ga6500fcdf1baf5d5019364ad155e30bf0',1,'stm32f407xx_matlab.h']]], - ['can_5ffm1r_5ffbm16_5fmsk_2955',['CAN_FM1R_FBM16_Msk',['../group___peripheral___registers___bits___definition.html#gafd51db2c7330341bf43bb888e63a61f5',1,'stm32f407xx_matlab.h']]], - ['can_5ffm1r_5ffbm16_5fpos_2956',['CAN_FM1R_FBM16_Pos',['../group___peripheral___registers___bits___definition.html#ga7a18fbe03eb8d83dc877be06ecdc7810',1,'stm32f407xx_matlab.h']]], - ['can_5ffm1r_5ffbm17_2957',['CAN_FM1R_FBM17',['../group___peripheral___registers___bits___definition.html#ga698a1a5cf309ba539973ad61a08ed531',1,'stm32f407xx_matlab.h']]], - ['can_5ffm1r_5ffbm17_5fmsk_2958',['CAN_FM1R_FBM17_Msk',['../group___peripheral___registers___bits___definition.html#ga54acc06d013985e059388599e2df40b7',1,'stm32f407xx_matlab.h']]], - ['can_5ffm1r_5ffbm17_5fpos_2959',['CAN_FM1R_FBM17_Pos',['../group___peripheral___registers___bits___definition.html#gaf5b340bc770061dc909bbf5761db8352',1,'stm32f407xx_matlab.h']]], - ['can_5ffm1r_5ffbm18_2960',['CAN_FM1R_FBM18',['../group___peripheral___registers___bits___definition.html#gaa47585a76a3ddf465abad7176e993ca1',1,'stm32f407xx_matlab.h']]], - ['can_5ffm1r_5ffbm18_5fmsk_2961',['CAN_FM1R_FBM18_Msk',['../group___peripheral___registers___bits___definition.html#ga7251ea74eaf728ad4538cd5a6ac34eaa',1,'stm32f407xx_matlab.h']]], - ['can_5ffm1r_5ffbm18_5fpos_2962',['CAN_FM1R_FBM18_Pos',['../group___peripheral___registers___bits___definition.html#gaa7c2e03e37aa98be8846eb3582a59515',1,'stm32f407xx_matlab.h']]], - ['can_5ffm1r_5ffbm19_2963',['CAN_FM1R_FBM19',['../group___peripheral___registers___bits___definition.html#ga70c9e6ce3b2e262912480c533cb94c30',1,'stm32f407xx_matlab.h']]], - ['can_5ffm1r_5ffbm19_5fmsk_2964',['CAN_FM1R_FBM19_Msk',['../group___peripheral___registers___bits___definition.html#ga185b29bf8e41d61399645ccab8efdf07',1,'stm32f407xx_matlab.h']]], - ['can_5ffm1r_5ffbm19_5fpos_2965',['CAN_FM1R_FBM19_Pos',['../group___peripheral___registers___bits___definition.html#ga728ea8bee75db988971d2f69cef3aa9a',1,'stm32f407xx_matlab.h']]], - ['can_5ffm1r_5ffbm1_5fmsk_2966',['CAN_FM1R_FBM1_Msk',['../group___peripheral___registers___bits___definition.html#gad57540467b1e1e98c24df335d72b6715',1,'stm32f407xx_matlab.h']]], - ['can_5ffm1r_5ffbm1_5fpos_2967',['CAN_FM1R_FBM1_Pos',['../group___peripheral___registers___bits___definition.html#ga56b3a50f8a5df07e09f78d165ae0ebb0',1,'stm32f407xx_matlab.h']]], - ['can_5ffm1r_5ffbm2_2968',['CAN_FM1R_FBM2',['../group___peripheral___registers___bits___definition.html#ga7ba7963ac4eb5b936c444258c13f8940',1,'stm32f407xx_matlab.h']]], - ['can_5ffm1r_5ffbm20_2969',['CAN_FM1R_FBM20',['../group___peripheral___registers___bits___definition.html#ga4af2f860f3d7c3bf3509daf366143baf',1,'stm32f407xx_matlab.h']]], - ['can_5ffm1r_5ffbm20_5fmsk_2970',['CAN_FM1R_FBM20_Msk',['../group___peripheral___registers___bits___definition.html#ga3557afecc8db6dab2c8ab6a19a76b245',1,'stm32f407xx_matlab.h']]], - ['can_5ffm1r_5ffbm20_5fpos_2971',['CAN_FM1R_FBM20_Pos',['../group___peripheral___registers___bits___definition.html#gae918f1bdbe01f6350fe05cad4d2c07fc',1,'stm32f407xx_matlab.h']]], - ['can_5ffm1r_5ffbm21_2972',['CAN_FM1R_FBM21',['../group___peripheral___registers___bits___definition.html#ga9bfdcf62b11bffb9afbee7f6258f089b',1,'stm32f407xx_matlab.h']]], - ['can_5ffm1r_5ffbm21_5fmsk_2973',['CAN_FM1R_FBM21_Msk',['../group___peripheral___registers___bits___definition.html#ga4c4575301b441f99be4fecfbdc0c06a5',1,'stm32f407xx_matlab.h']]], - ['can_5ffm1r_5ffbm21_5fpos_2974',['CAN_FM1R_FBM21_Pos',['../group___peripheral___registers___bits___definition.html#ga7890f90e73ef96b5497aeca708dd950a',1,'stm32f407xx_matlab.h']]], - ['can_5ffm1r_5ffbm22_2975',['CAN_FM1R_FBM22',['../group___peripheral___registers___bits___definition.html#ga67e71ecc049fe1c882be5e03aaecdc01',1,'stm32f407xx_matlab.h']]], - ['can_5ffm1r_5ffbm22_5fmsk_2976',['CAN_FM1R_FBM22_Msk',['../group___peripheral___registers___bits___definition.html#gaad10cf074d53c11a4700ad7983e2ba34',1,'stm32f407xx_matlab.h']]], - ['can_5ffm1r_5ffbm22_5fpos_2977',['CAN_FM1R_FBM22_Pos',['../group___peripheral___registers___bits___definition.html#ga5e18237e288612926c6e8855345b2d47',1,'stm32f407xx_matlab.h']]], - ['can_5ffm1r_5ffbm23_2978',['CAN_FM1R_FBM23',['../group___peripheral___registers___bits___definition.html#ga70ac1d53ad6dbc162272b92aa704eff4',1,'stm32f407xx_matlab.h']]], - ['can_5ffm1r_5ffbm23_5fmsk_2979',['CAN_FM1R_FBM23_Msk',['../group___peripheral___registers___bits___definition.html#ga3d600617dc97adc1e75a2abcf1909d3b',1,'stm32f407xx_matlab.h']]], - ['can_5ffm1r_5ffbm23_5fpos_2980',['CAN_FM1R_FBM23_Pos',['../group___peripheral___registers___bits___definition.html#ga1ced626c3b41a506cd8cd737c03fe787',1,'stm32f407xx_matlab.h']]], - ['can_5ffm1r_5ffbm24_2981',['CAN_FM1R_FBM24',['../group___peripheral___registers___bits___definition.html#ga2befceefa1b4600adb96b1150a738dcf',1,'stm32f407xx_matlab.h']]], - ['can_5ffm1r_5ffbm24_5fmsk_2982',['CAN_FM1R_FBM24_Msk',['../group___peripheral___registers___bits___definition.html#ga7d68bf08a503f10fa7c9728ddafa8ed7',1,'stm32f407xx_matlab.h']]], - ['can_5ffm1r_5ffbm24_5fpos_2983',['CAN_FM1R_FBM24_Pos',['../group___peripheral___registers___bits___definition.html#gaea93cbe9b69f821ed9475b0585c15637',1,'stm32f407xx_matlab.h']]], - ['can_5ffm1r_5ffbm25_2984',['CAN_FM1R_FBM25',['../group___peripheral___registers___bits___definition.html#gaf8302ff02a952e32bd6cb5d8ce17ef94',1,'stm32f407xx_matlab.h']]], - ['can_5ffm1r_5ffbm25_5fmsk_2985',['CAN_FM1R_FBM25_Msk',['../group___peripheral___registers___bits___definition.html#gae4f8c432102ad6270ae8c8faa92599e7',1,'stm32f407xx_matlab.h']]], - ['can_5ffm1r_5ffbm25_5fpos_2986',['CAN_FM1R_FBM25_Pos',['../group___peripheral___registers___bits___definition.html#ga0cf69597e272b2e3db7bb54b60609553',1,'stm32f407xx_matlab.h']]], - ['can_5ffm1r_5ffbm26_2987',['CAN_FM1R_FBM26',['../group___peripheral___registers___bits___definition.html#ga1ea4af83b76361928669dc1de5681bd5',1,'stm32f407xx_matlab.h']]], - ['can_5ffm1r_5ffbm26_5fmsk_2988',['CAN_FM1R_FBM26_Msk',['../group___peripheral___registers___bits___definition.html#ga83528f848c64886be406a292c49f6b55',1,'stm32f407xx_matlab.h']]], - ['can_5ffm1r_5ffbm26_5fpos_2989',['CAN_FM1R_FBM26_Pos',['../group___peripheral___registers___bits___definition.html#ga20c45ed77383fe5ccf21614fe569ab6e',1,'stm32f407xx_matlab.h']]], - ['can_5ffm1r_5ffbm27_2990',['CAN_FM1R_FBM27',['../group___peripheral___registers___bits___definition.html#ga40ca208f170b85611874b2f832623aa8',1,'stm32f407xx_matlab.h']]], - ['can_5ffm1r_5ffbm27_5fmsk_2991',['CAN_FM1R_FBM27_Msk',['../group___peripheral___registers___bits___definition.html#gaf50cb4ff71b1cf38397efdff320e80cb',1,'stm32f407xx_matlab.h']]], - ['can_5ffm1r_5ffbm27_5fpos_2992',['CAN_FM1R_FBM27_Pos',['../group___peripheral___registers___bits___definition.html#ga9dbac6ff3f18e5f1104e326dc24302bf',1,'stm32f407xx_matlab.h']]], - ['can_5ffm1r_5ffbm2_5fmsk_2993',['CAN_FM1R_FBM2_Msk',['../group___peripheral___registers___bits___definition.html#gab036323d5ff180c94cb011bda0e93738',1,'stm32f407xx_matlab.h']]], - ['can_5ffm1r_5ffbm2_5fpos_2994',['CAN_FM1R_FBM2_Pos',['../group___peripheral___registers___bits___definition.html#ga9893bef42453161269747598ec908d49',1,'stm32f407xx_matlab.h']]], - ['can_5ffm1r_5ffbm3_2995',['CAN_FM1R_FBM3',['../group___peripheral___registers___bits___definition.html#ga2d129b27c2af41ae39e606e802a53386',1,'stm32f407xx_matlab.h']]], - ['can_5ffm1r_5ffbm3_5fmsk_2996',['CAN_FM1R_FBM3_Msk',['../group___peripheral___registers___bits___definition.html#ga8514f94421b8d4665c84a5e09ea814b6',1,'stm32f407xx_matlab.h']]], - ['can_5ffm1r_5ffbm3_5fpos_2997',['CAN_FM1R_FBM3_Pos',['../group___peripheral___registers___bits___definition.html#ga612d9e0e776abfcdbc2b24a964d6ab6e',1,'stm32f407xx_matlab.h']]], - ['can_5ffm1r_5ffbm4_2998',['CAN_FM1R_FBM4',['../group___peripheral___registers___bits___definition.html#gaf0c94e5f4dcceea510fc72b86128aff3',1,'stm32f407xx_matlab.h']]], - ['can_5ffm1r_5ffbm4_5fmsk_2999',['CAN_FM1R_FBM4_Msk',['../group___peripheral___registers___bits___definition.html#ga3bca8d2dab6ca215db7dfe45702c9c88',1,'stm32f407xx_matlab.h']]], - ['can_5ffm1r_5ffbm4_5fpos_3000',['CAN_FM1R_FBM4_Pos',['../group___peripheral___registers___bits___definition.html#gacb58de50d9b0a1508617d885f052d7a6',1,'stm32f407xx_matlab.h']]], - ['can_5ffm1r_5ffbm5_3001',['CAN_FM1R_FBM5',['../group___peripheral___registers___bits___definition.html#ga2d7fb7c366544a1ef7a85481d3e6325d',1,'stm32f407xx_matlab.h']]], - ['can_5ffm1r_5ffbm5_5fmsk_3002',['CAN_FM1R_FBM5_Msk',['../group___peripheral___registers___bits___definition.html#gad8534298a873d6eeba40f67ccd8e44dc',1,'stm32f407xx_matlab.h']]], - ['can_5ffm1r_5ffbm5_5fpos_3003',['CAN_FM1R_FBM5_Pos',['../group___peripheral___registers___bits___definition.html#ga3b8f80f23a5ab8f322c9b4b441a8d768',1,'stm32f407xx_matlab.h']]], - ['can_5ffm1r_5ffbm6_3004',['CAN_FM1R_FBM6',['../group___peripheral___registers___bits___definition.html#ga3ff70e74447679a0d1cde1aa69ea2db1',1,'stm32f407xx_matlab.h']]], - ['can_5ffm1r_5ffbm6_5fmsk_3005',['CAN_FM1R_FBM6_Msk',['../group___peripheral___registers___bits___definition.html#ga6e635abf1f1fda09814600ac218b25a5',1,'stm32f407xx_matlab.h']]], - ['can_5ffm1r_5ffbm6_5fpos_3006',['CAN_FM1R_FBM6_Pos',['../group___peripheral___registers___bits___definition.html#gad4a556397deec72a65aec5ec5600e16f',1,'stm32f407xx_matlab.h']]], - ['can_5ffm1r_5ffbm7_3007',['CAN_FM1R_FBM7',['../group___peripheral___registers___bits___definition.html#ga657fc12fd334bc626b2eb53fb03457b0',1,'stm32f407xx_matlab.h']]], - ['can_5ffm1r_5ffbm7_5fmsk_3008',['CAN_FM1R_FBM7_Msk',['../group___peripheral___registers___bits___definition.html#ga0e697f5e347652a49756219c13e6cc89',1,'stm32f407xx_matlab.h']]], - ['can_5ffm1r_5ffbm7_5fpos_3009',['CAN_FM1R_FBM7_Pos',['../group___peripheral___registers___bits___definition.html#gaf2d58da6b63e9ebe66d43e438f0df884',1,'stm32f407xx_matlab.h']]], - ['can_5ffm1r_5ffbm8_3010',['CAN_FM1R_FBM8',['../group___peripheral___registers___bits___definition.html#gab6bc390ed9a658014fd09fd1073e3037',1,'stm32f407xx_matlab.h']]], - ['can_5ffm1r_5ffbm8_5fmsk_3011',['CAN_FM1R_FBM8_Msk',['../group___peripheral___registers___bits___definition.html#ga1b3e86a2ff5df79cb0d1fc1d09da5309',1,'stm32f407xx_matlab.h']]], - ['can_5ffm1r_5ffbm8_5fpos_3012',['CAN_FM1R_FBM8_Pos',['../group___peripheral___registers___bits___definition.html#ga30b41b013fad0569137363aa33b5fd8e',1,'stm32f407xx_matlab.h']]], - ['can_5ffm1r_5ffbm9_3013',['CAN_FM1R_FBM9',['../group___peripheral___registers___bits___definition.html#ga375758246b99234dda725b7c64daff32',1,'stm32f407xx_matlab.h']]], - ['can_5ffm1r_5ffbm9_5fmsk_3014',['CAN_FM1R_FBM9_Msk',['../group___peripheral___registers___bits___definition.html#gac9787e28f4d47535624b593b042e7aef',1,'stm32f407xx_matlab.h']]], - ['can_5ffm1r_5ffbm9_5fpos_3015',['CAN_FM1R_FBM9_Pos',['../group___peripheral___registers___bits___definition.html#gae891964bdca74710cfb7a1587b9c75a2',1,'stm32f407xx_matlab.h']]], - ['can_5ffm1r_5ffbm_5fmsk_3016',['CAN_FM1R_FBM_Msk',['../group___peripheral___registers___bits___definition.html#ga97376a7949c1758c1f294cc9a85cbe8c',1,'stm32f407xx_matlab.h']]], - ['can_5ffm1r_5ffbm_5fpos_3017',['CAN_FM1R_FBM_Pos',['../group___peripheral___registers___bits___definition.html#gaa97dffd3da7f8927e2168a6dce9d8312',1,'stm32f407xx_matlab.h']]], - ['can_5ffmr_5fcan2sb_3018',['CAN_FMR_CAN2SB',['../group___peripheral___registers___bits___definition.html#ga3753c67c075a4508104d112ef9047f21',1,'stm32f407xx_matlab.h']]], - ['can_5ffmr_5fcan2sb_5fmsk_3019',['CAN_FMR_CAN2SB_Msk',['../group___peripheral___registers___bits___definition.html#ga92c82386fd3904c98b94f78cfb9570d2',1,'stm32f407xx_matlab.h']]], - ['can_5ffmr_5fcan2sb_5fpos_3020',['CAN_FMR_CAN2SB_Pos',['../group___peripheral___registers___bits___definition.html#gaaaea537f2e7bfc1d90c43a60d12145b7',1,'stm32f407xx_matlab.h']]], - ['can_5ffmr_5ffinit_3021',['CAN_FMR_FINIT',['../group___peripheral___registers___bits___definition.html#ga5eb5b835ee11a78bd391b9d1049f2549',1,'stm32f407xx_matlab.h']]], - ['can_5ffmr_5ffinit_5fmsk_3022',['CAN_FMR_FINIT_Msk',['../group___peripheral___registers___bits___definition.html#ga99a8549f1c1784779e00b257c216102d',1,'stm32f407xx_matlab.h']]], - ['can_5ffmr_5ffinit_5fpos_3023',['CAN_FMR_FINIT_Pos',['../group___peripheral___registers___bits___definition.html#ga8d07843af8269762b43ed1bef5fc29b3',1,'stm32f407xx_matlab.h']]], - ['can_5ffs1r_5ffsc_3024',['CAN_FS1R_FSC',['../group___peripheral___registers___bits___definition.html#gab41471f35878bcdff72d9cd05acf4714',1,'stm32f407xx_matlab.h']]], - ['can_5ffs1r_5ffsc0_3025',['CAN_FS1R_FSC0',['../group___peripheral___registers___bits___definition.html#gaab5ea9e0ed17df35894fff7828c89cad',1,'stm32f407xx_matlab.h']]], - ['can_5ffs1r_5ffsc0_5fmsk_3026',['CAN_FS1R_FSC0_Msk',['../group___peripheral___registers___bits___definition.html#ga521e7ed67be2a02528c2dd393abf8980',1,'stm32f407xx_matlab.h']]], - ['can_5ffs1r_5ffsc0_5fpos_3027',['CAN_FS1R_FSC0_Pos',['../group___peripheral___registers___bits___definition.html#ga975c66c5f2d56c2ba83d022200c37958',1,'stm32f407xx_matlab.h']]], - ['can_5ffs1r_5ffsc1_3028',['CAN_FS1R_FSC1',['../group___peripheral___registers___bits___definition.html#ga83304e93d2e75c1cd8bfe7c2ec30c1c8',1,'stm32f407xx_matlab.h']]], - ['can_5ffs1r_5ffsc10_3029',['CAN_FS1R_FSC10',['../group___peripheral___registers___bits___definition.html#ga93162a66091ffd4829ed8265f53fe977',1,'stm32f407xx_matlab.h']]], - ['can_5ffs1r_5ffsc10_5fmsk_3030',['CAN_FS1R_FSC10_Msk',['../group___peripheral___registers___bits___definition.html#gae4915e6d23184afe98e5669b2575bfad',1,'stm32f407xx_matlab.h']]], - ['can_5ffs1r_5ffsc10_5fpos_3031',['CAN_FS1R_FSC10_Pos',['../group___peripheral___registers___bits___definition.html#gaaba757c59e5d37c1acdbed8af1ab90b4',1,'stm32f407xx_matlab.h']]], - ['can_5ffs1r_5ffsc11_3032',['CAN_FS1R_FSC11',['../group___peripheral___registers___bits___definition.html#gaf2e0bf399ea9175123c95c7010ef527d',1,'stm32f407xx_matlab.h']]], - ['can_5ffs1r_5ffsc11_5fmsk_3033',['CAN_FS1R_FSC11_Msk',['../group___peripheral___registers___bits___definition.html#ga17d1cabb7f95d9e773867888654ea3b0',1,'stm32f407xx_matlab.h']]], - ['can_5ffs1r_5ffsc11_5fpos_3034',['CAN_FS1R_FSC11_Pos',['../group___peripheral___registers___bits___definition.html#gac2dd37596f667cdfd2771f05b413633e',1,'stm32f407xx_matlab.h']]], - ['can_5ffs1r_5ffsc12_3035',['CAN_FS1R_FSC12',['../group___peripheral___registers___bits___definition.html#ga89ea9e9c914052e2aecab16d57f2569d',1,'stm32f407xx_matlab.h']]], - ['can_5ffs1r_5ffsc12_5fmsk_3036',['CAN_FS1R_FSC12_Msk',['../group___peripheral___registers___bits___definition.html#gad12de017f6c66c2b893b34d99c36c031',1,'stm32f407xx_matlab.h']]], - ['can_5ffs1r_5ffsc12_5fpos_3037',['CAN_FS1R_FSC12_Pos',['../group___peripheral___registers___bits___definition.html#ga84011d0e3b79daa5ce4c9a076e774bca',1,'stm32f407xx_matlab.h']]], - ['can_5ffs1r_5ffsc13_3038',['CAN_FS1R_FSC13',['../group___peripheral___registers___bits___definition.html#gaf2df1f2a554fc014529da34620739bc4',1,'stm32f407xx_matlab.h']]], - ['can_5ffs1r_5ffsc13_5fmsk_3039',['CAN_FS1R_FSC13_Msk',['../group___peripheral___registers___bits___definition.html#ga325adfc64e83297e5feb842002f09142',1,'stm32f407xx_matlab.h']]], - ['can_5ffs1r_5ffsc13_5fpos_3040',['CAN_FS1R_FSC13_Pos',['../group___peripheral___registers___bits___definition.html#ga1e5c2f04599975dff25a01253f0ed0db',1,'stm32f407xx_matlab.h']]], - ['can_5ffs1r_5ffsc14_3041',['CAN_FS1R_FSC14',['../group___peripheral___registers___bits___definition.html#ga361a4228de4644d1d6a810f4d074eb5f',1,'stm32f407xx_matlab.h']]], - ['can_5ffs1r_5ffsc14_5fmsk_3042',['CAN_FS1R_FSC14_Msk',['../group___peripheral___registers___bits___definition.html#ga34624026fcafcbee1b6c88d7e7756aae',1,'stm32f407xx_matlab.h']]], - ['can_5ffs1r_5ffsc14_5fpos_3043',['CAN_FS1R_FSC14_Pos',['../group___peripheral___registers___bits___definition.html#ga711edd554bca297c3257d40b351c20c3',1,'stm32f407xx_matlab.h']]], - ['can_5ffs1r_5ffsc15_3044',['CAN_FS1R_FSC15',['../group___peripheral___registers___bits___definition.html#gaa5ff2e59c16311405dc891f956c7ec96',1,'stm32f407xx_matlab.h']]], - ['can_5ffs1r_5ffsc15_5fmsk_3045',['CAN_FS1R_FSC15_Msk',['../group___peripheral___registers___bits___definition.html#ga49834a4dc96f2cb8f792bd39d032abb4',1,'stm32f407xx_matlab.h']]], - ['can_5ffs1r_5ffsc15_5fpos_3046',['CAN_FS1R_FSC15_Pos',['../group___peripheral___registers___bits___definition.html#gaf3333c522cd42beec23bccc79a2ae1ba',1,'stm32f407xx_matlab.h']]], - ['can_5ffs1r_5ffsc16_3047',['CAN_FS1R_FSC16',['../group___peripheral___registers___bits___definition.html#gad0996ddbc1dcd487c052a0ae81ab852e',1,'stm32f407xx_matlab.h']]], - ['can_5ffs1r_5ffsc16_5fmsk_3048',['CAN_FS1R_FSC16_Msk',['../group___peripheral___registers___bits___definition.html#ga1eb533d142b86083e8b163adc30999a7',1,'stm32f407xx_matlab.h']]], - ['can_5ffs1r_5ffsc16_5fpos_3049',['CAN_FS1R_FSC16_Pos',['../group___peripheral___registers___bits___definition.html#ga94d84c5617fa0b58145211fc852fa55a',1,'stm32f407xx_matlab.h']]], - ['can_5ffs1r_5ffsc17_3050',['CAN_FS1R_FSC17',['../group___peripheral___registers___bits___definition.html#ga65482dccb8701bf35d1397aadc1e7dde',1,'stm32f407xx_matlab.h']]], - ['can_5ffs1r_5ffsc17_5fmsk_3051',['CAN_FS1R_FSC17_Msk',['../group___peripheral___registers___bits___definition.html#ga7d4c2ff7be6ee9b3e31108c9877aef03',1,'stm32f407xx_matlab.h']]], - ['can_5ffs1r_5ffsc17_5fpos_3052',['CAN_FS1R_FSC17_Pos',['../group___peripheral___registers___bits___definition.html#ga08ac31ff1870b11302f9e3b27d69789c',1,'stm32f407xx_matlab.h']]], - ['can_5ffs1r_5ffsc18_3053',['CAN_FS1R_FSC18',['../group___peripheral___registers___bits___definition.html#gaf2657192999f8d7f7fdd5c5ef14d884f',1,'stm32f407xx_matlab.h']]], - ['can_5ffs1r_5ffsc18_5fmsk_3054',['CAN_FS1R_FSC18_Msk',['../group___peripheral___registers___bits___definition.html#gad8d890a441fc7b0a75e36caf1cbd7f2d',1,'stm32f407xx_matlab.h']]], - ['can_5ffs1r_5ffsc18_5fpos_3055',['CAN_FS1R_FSC18_Pos',['../group___peripheral___registers___bits___definition.html#ga0e256893bf2da548fa31dacc67b8833b',1,'stm32f407xx_matlab.h']]], - ['can_5ffs1r_5ffsc19_3056',['CAN_FS1R_FSC19',['../group___peripheral___registers___bits___definition.html#gafd584a3a9b6d6ae964c0484decb86a93',1,'stm32f407xx_matlab.h']]], - ['can_5ffs1r_5ffsc19_5fmsk_3057',['CAN_FS1R_FSC19_Msk',['../group___peripheral___registers___bits___definition.html#ga562629687ae7a0c506aa310709b5451e',1,'stm32f407xx_matlab.h']]], - ['can_5ffs1r_5ffsc19_5fpos_3058',['CAN_FS1R_FSC19_Pos',['../group___peripheral___registers___bits___definition.html#ga691b7c4f52419323104f755201811d0b',1,'stm32f407xx_matlab.h']]], - ['can_5ffs1r_5ffsc1_5fmsk_3059',['CAN_FS1R_FSC1_Msk',['../group___peripheral___registers___bits___definition.html#ga1084aab8cb7c0fa2ebb1d54c8b1e5aec',1,'stm32f407xx_matlab.h']]], - ['can_5ffs1r_5ffsc1_5fpos_3060',['CAN_FS1R_FSC1_Pos',['../group___peripheral___registers___bits___definition.html#ga642ead0693a426283dce755b276cc60b',1,'stm32f407xx_matlab.h']]], - ['can_5ffs1r_5ffsc2_3061',['CAN_FS1R_FSC2',['../group___peripheral___registers___bits___definition.html#ga0ba1fa61fcf851188a6f16323dda1358',1,'stm32f407xx_matlab.h']]], - ['can_5ffs1r_5ffsc20_3062',['CAN_FS1R_FSC20',['../group___peripheral___registers___bits___definition.html#gae5a5e1f0f1a66d607984d02b96b7fa2a',1,'stm32f407xx_matlab.h']]], - ['can_5ffs1r_5ffsc20_5fmsk_3063',['CAN_FS1R_FSC20_Msk',['../group___peripheral___registers___bits___definition.html#gad0fce6ba0c9c134b3f634c8495b1e9a2',1,'stm32f407xx_matlab.h']]], - ['can_5ffs1r_5ffsc20_5fpos_3064',['CAN_FS1R_FSC20_Pos',['../group___peripheral___registers___bits___definition.html#gab0c2995214cad61a44cfbe386fafe5ff',1,'stm32f407xx_matlab.h']]], - ['can_5ffs1r_5ffsc21_3065',['CAN_FS1R_FSC21',['../group___peripheral___registers___bits___definition.html#gafa1d6dbc3fc5025a9e7416cc4b40cb7d',1,'stm32f407xx_matlab.h']]], - ['can_5ffs1r_5ffsc21_5fmsk_3066',['CAN_FS1R_FSC21_Msk',['../group___peripheral___registers___bits___definition.html#ga733db908c55117942e05d21f1ed80d7e',1,'stm32f407xx_matlab.h']]], - ['can_5ffs1r_5ffsc21_5fpos_3067',['CAN_FS1R_FSC21_Pos',['../group___peripheral___registers___bits___definition.html#ga6ea9c1362c0aa5d3d03f5df6b92ba9d4',1,'stm32f407xx_matlab.h']]], - ['can_5ffs1r_5ffsc22_3068',['CAN_FS1R_FSC22',['../group___peripheral___registers___bits___definition.html#ga586c662a1dd2458cd1644e597c8da86d',1,'stm32f407xx_matlab.h']]], - ['can_5ffs1r_5ffsc22_5fmsk_3069',['CAN_FS1R_FSC22_Msk',['../group___peripheral___registers___bits___definition.html#gaabe5f4c3cd58ca9f4749942e3e6e04ee',1,'stm32f407xx_matlab.h']]], - ['can_5ffs1r_5ffsc22_5fpos_3070',['CAN_FS1R_FSC22_Pos',['../group___peripheral___registers___bits___definition.html#gaf2f345b172c571948a3357dd94b72adf',1,'stm32f407xx_matlab.h']]], - ['can_5ffs1r_5ffsc23_3071',['CAN_FS1R_FSC23',['../group___peripheral___registers___bits___definition.html#ga941b39874446041b446c3102646a49b8',1,'stm32f407xx_matlab.h']]], - ['can_5ffs1r_5ffsc23_5fmsk_3072',['CAN_FS1R_FSC23_Msk',['../group___peripheral___registers___bits___definition.html#ga7f8a8529c7e6e9b2d9bcd4512888365a',1,'stm32f407xx_matlab.h']]], - ['can_5ffs1r_5ffsc23_5fpos_3073',['CAN_FS1R_FSC23_Pos',['../group___peripheral___registers___bits___definition.html#ga152bf04e1b1d963bfed4425d41dd27c8',1,'stm32f407xx_matlab.h']]], - ['can_5ffs1r_5ffsc24_3074',['CAN_FS1R_FSC24',['../group___peripheral___registers___bits___definition.html#ga702728de40ecf0afc5bc8f05ee243ece',1,'stm32f407xx_matlab.h']]], - ['can_5ffs1r_5ffsc24_5fmsk_3075',['CAN_FS1R_FSC24_Msk',['../group___peripheral___registers___bits___definition.html#ga68e6bfdc20abbec37b36857af02f466d',1,'stm32f407xx_matlab.h']]], - ['can_5ffs1r_5ffsc24_5fpos_3076',['CAN_FS1R_FSC24_Pos',['../group___peripheral___registers___bits___definition.html#ga51ea9d18bbbe2db9eed4a8e58e59e957',1,'stm32f407xx_matlab.h']]], - ['can_5ffs1r_5ffsc25_3077',['CAN_FS1R_FSC25',['../group___peripheral___registers___bits___definition.html#ga1bd08e49dcb537e967ef7e8a7b30e9d0',1,'stm32f407xx_matlab.h']]], - ['can_5ffs1r_5ffsc25_5fmsk_3078',['CAN_FS1R_FSC25_Msk',['../group___peripheral___registers___bits___definition.html#ga2211e33f4ca75397983086826a688656',1,'stm32f407xx_matlab.h']]], - ['can_5ffs1r_5ffsc25_5fpos_3079',['CAN_FS1R_FSC25_Pos',['../group___peripheral___registers___bits___definition.html#ga5f0bdcc4ed01c8beabedfc4b16a146f6',1,'stm32f407xx_matlab.h']]], - ['can_5ffs1r_5ffsc26_3080',['CAN_FS1R_FSC26',['../group___peripheral___registers___bits___definition.html#gac642623c62041b1be7ce3af929c4f924',1,'stm32f407xx_matlab.h']]], - ['can_5ffs1r_5ffsc26_5fmsk_3081',['CAN_FS1R_FSC26_Msk',['../group___peripheral___registers___bits___definition.html#ga4d55d2d1459b5de35264036663bc430b',1,'stm32f407xx_matlab.h']]], - ['can_5ffs1r_5ffsc26_5fpos_3082',['CAN_FS1R_FSC26_Pos',['../group___peripheral___registers___bits___definition.html#gab61794b3ead79416791289685a95db4d',1,'stm32f407xx_matlab.h']]], - ['can_5ffs1r_5ffsc27_3083',['CAN_FS1R_FSC27',['../group___peripheral___registers___bits___definition.html#ga9e86579ebc64eda3a65fd8d40e15af57',1,'stm32f407xx_matlab.h']]], - ['can_5ffs1r_5ffsc27_5fmsk_3084',['CAN_FS1R_FSC27_Msk',['../group___peripheral___registers___bits___definition.html#ga3c2c04e71ea402536a26c54e6f23116d',1,'stm32f407xx_matlab.h']]], - ['can_5ffs1r_5ffsc27_5fpos_3085',['CAN_FS1R_FSC27_Pos',['../group___peripheral___registers___bits___definition.html#ga3d7b516bf7cf68e60c3feb66b1c3588e',1,'stm32f407xx_matlab.h']]], - ['can_5ffs1r_5ffsc2_5fmsk_3086',['CAN_FS1R_FSC2_Msk',['../group___peripheral___registers___bits___definition.html#gab5c2bf5abff8b81f574f616837e91391',1,'stm32f407xx_matlab.h']]], - ['can_5ffs1r_5ffsc2_5fpos_3087',['CAN_FS1R_FSC2_Pos',['../group___peripheral___registers___bits___definition.html#ga7026c45f4a48271ab35dd5e090c4568c',1,'stm32f407xx_matlab.h']]], - ['can_5ffs1r_5ffsc3_3088',['CAN_FS1R_FSC3',['../group___peripheral___registers___bits___definition.html#gaf2175f52f4308c088458f9e54a1f1354',1,'stm32f407xx_matlab.h']]], - ['can_5ffs1r_5ffsc3_5fmsk_3089',['CAN_FS1R_FSC3_Msk',['../group___peripheral___registers___bits___definition.html#ga8783da3e87efcfa99529dc7f6d3e9b8e',1,'stm32f407xx_matlab.h']]], - ['can_5ffs1r_5ffsc3_5fpos_3090',['CAN_FS1R_FSC3_Pos',['../group___peripheral___registers___bits___definition.html#ga4262b5fb400ad83240758a8e0033bb98',1,'stm32f407xx_matlab.h']]], - ['can_5ffs1r_5ffsc4_3091',['CAN_FS1R_FSC4',['../group___peripheral___registers___bits___definition.html#ga791ac090d6a8f2c79cd72f9072aef30f',1,'stm32f407xx_matlab.h']]], - ['can_5ffs1r_5ffsc4_5fmsk_3092',['CAN_FS1R_FSC4_Msk',['../group___peripheral___registers___bits___definition.html#ga31ca51fc93d252a1a57a65ebf4163c46',1,'stm32f407xx_matlab.h']]], - ['can_5ffs1r_5ffsc4_5fpos_3093',['CAN_FS1R_FSC4_Pos',['../group___peripheral___registers___bits___definition.html#gaba967abdc8c83c0d6e4590c691c16c1c',1,'stm32f407xx_matlab.h']]], - ['can_5ffs1r_5ffsc5_3094',['CAN_FS1R_FSC5',['../group___peripheral___registers___bits___definition.html#gadb4ef2030ec70a4635ca4ac38cca76cb',1,'stm32f407xx_matlab.h']]], - ['can_5ffs1r_5ffsc5_5fmsk_3095',['CAN_FS1R_FSC5_Msk',['../group___peripheral___registers___bits___definition.html#ga9f3efc361a57e98dc7fd35b9ad6db3f3',1,'stm32f407xx_matlab.h']]], - ['can_5ffs1r_5ffsc5_5fpos_3096',['CAN_FS1R_FSC5_Pos',['../group___peripheral___registers___bits___definition.html#ga13a409ade293eec6d218a684042312d3',1,'stm32f407xx_matlab.h']]], - ['can_5ffs1r_5ffsc6_3097',['CAN_FS1R_FSC6',['../group___peripheral___registers___bits___definition.html#gaf015be41f803007b9d0b2f3371e3621b',1,'stm32f407xx_matlab.h']]], - ['can_5ffs1r_5ffsc6_5fmsk_3098',['CAN_FS1R_FSC6_Msk',['../group___peripheral___registers___bits___definition.html#ga2a42808ce8e7e8c94c7a1748bc42b256',1,'stm32f407xx_matlab.h']]], - ['can_5ffs1r_5ffsc6_5fpos_3099',['CAN_FS1R_FSC6_Pos',['../group___peripheral___registers___bits___definition.html#gae8cf40d32e952d3fddc0cdc49ef695b5',1,'stm32f407xx_matlab.h']]], - ['can_5ffs1r_5ffsc7_3100',['CAN_FS1R_FSC7',['../group___peripheral___registers___bits___definition.html#ga206d175417e2c787b44b0734708a5c9a',1,'stm32f407xx_matlab.h']]], - ['can_5ffs1r_5ffsc7_5fmsk_3101',['CAN_FS1R_FSC7_Msk',['../group___peripheral___registers___bits___definition.html#ga68d4a45e6f9068e4c7ed2af48eeb9e16',1,'stm32f407xx_matlab.h']]], - ['can_5ffs1r_5ffsc7_5fpos_3102',['CAN_FS1R_FSC7_Pos',['../group___peripheral___registers___bits___definition.html#ga8936fed15d6db3d7d1079851f2cf3679',1,'stm32f407xx_matlab.h']]], - ['can_5ffs1r_5ffsc8_3103',['CAN_FS1R_FSC8',['../group___peripheral___registers___bits___definition.html#ga7209f008874dadf147cb5357ee46c226',1,'stm32f407xx_matlab.h']]], - ['can_5ffs1r_5ffsc8_5fmsk_3104',['CAN_FS1R_FSC8_Msk',['../group___peripheral___registers___bits___definition.html#gab90fee6d415260e5eb61df78ff0bbc3d',1,'stm32f407xx_matlab.h']]], - ['can_5ffs1r_5ffsc8_5fpos_3105',['CAN_FS1R_FSC8_Pos',['../group___peripheral___registers___bits___definition.html#gaed8e8f6dee42172cd578e1abab937b8b',1,'stm32f407xx_matlab.h']]], - ['can_5ffs1r_5ffsc9_3106',['CAN_FS1R_FSC9',['../group___peripheral___registers___bits___definition.html#ga58b4d8fa56d898ad6bf66ba8a4e098eb',1,'stm32f407xx_matlab.h']]], - ['can_5ffs1r_5ffsc9_5fmsk_3107',['CAN_FS1R_FSC9_Msk',['../group___peripheral___registers___bits___definition.html#ga5fb2cac86c92bee0c7d29a1ee401aaa0',1,'stm32f407xx_matlab.h']]], - ['can_5ffs1r_5ffsc9_5fpos_3108',['CAN_FS1R_FSC9_Pos',['../group___peripheral___registers___bits___definition.html#ga4d172244d6448c45cb6be5d36474a4e1',1,'stm32f407xx_matlab.h']]], - ['can_5ffs1r_5ffsc_5fmsk_3109',['CAN_FS1R_FSC_Msk',['../group___peripheral___registers___bits___definition.html#ga2f5fd354abb81f726d16ba3df34d75d2',1,'stm32f407xx_matlab.h']]], - ['can_5ffs1r_5ffsc_5fpos_3110',['CAN_FS1R_FSC_Pos',['../group___peripheral___registers___bits___definition.html#gada2ff6f825375b0d42b92e7446a4e39c',1,'stm32f407xx_matlab.h']]], - ['can_5fier_5fbofie_3111',['CAN_IER_BOFIE',['../group___peripheral___registers___bits___definition.html#ga7d953fd5b625af04f95f5414259769ef',1,'stm32f407xx_matlab.h']]], - ['can_5fier_5fbofie_5fmsk_3112',['CAN_IER_BOFIE_Msk',['../group___peripheral___registers___bits___definition.html#ga748f02d794157dc9684f6c15096d4e75',1,'stm32f407xx_matlab.h']]], - ['can_5fier_5fbofie_5fpos_3113',['CAN_IER_BOFIE_Pos',['../group___peripheral___registers___bits___definition.html#gafa110152ba07d311efc4c513a0e39eb4',1,'stm32f407xx_matlab.h']]], - ['can_5fier_5fepvie_3114',['CAN_IER_EPVIE',['../group___peripheral___registers___bits___definition.html#ga9e3307992cabee858287305a64e5031b',1,'stm32f407xx_matlab.h']]], - ['can_5fier_5fepvie_5fmsk_3115',['CAN_IER_EPVIE_Msk',['../group___peripheral___registers___bits___definition.html#gababf833052c2a6ffbd6ce2aa5960a61b',1,'stm32f407xx_matlab.h']]], - ['can_5fier_5fepvie_5fpos_3116',['CAN_IER_EPVIE_Pos',['../group___peripheral___registers___bits___definition.html#gad9f52eb0782253e0623c7bdd27823743',1,'stm32f407xx_matlab.h']]], - ['can_5fier_5ferrie_3117',['CAN_IER_ERRIE',['../group___peripheral___registers___bits___definition.html#ga962968c3ee1f70c714a5b12442369d9a',1,'stm32f407xx_matlab.h']]], - ['can_5fier_5ferrie_5fmsk_3118',['CAN_IER_ERRIE_Msk',['../group___peripheral___registers___bits___definition.html#ga3df7133242e3ff1636bb946649faa8d0',1,'stm32f407xx_matlab.h']]], - ['can_5fier_5ferrie_5fpos_3119',['CAN_IER_ERRIE_Pos',['../group___peripheral___registers___bits___definition.html#gaf5a98a5d7ea27cfd207b83364fb3b8e2',1,'stm32f407xx_matlab.h']]], - ['can_5fier_5fewgie_3120',['CAN_IER_EWGIE',['../group___peripheral___registers___bits___definition.html#gaa80103eca53d74a2b047f761336918e3',1,'stm32f407xx_matlab.h']]], - ['can_5fier_5fewgie_5fmsk_3121',['CAN_IER_EWGIE_Msk',['../group___peripheral___registers___bits___definition.html#gac15046ca7a384201773a9dfeb03deabc',1,'stm32f407xx_matlab.h']]], - ['can_5fier_5fewgie_5fpos_3122',['CAN_IER_EWGIE_Pos',['../group___peripheral___registers___bits___definition.html#ga5ed2cabb36a1f1b250a8d344896b1c9c',1,'CAN_IER_EWGIE_Pos: stm32f407xx_matlab.h'],['../group___peripheral___registers___bits___definition.html#ga5ed2cabb36a1f1b250a8d344896b1c9c',1,'CAN_IER_EWGIE_Pos: stm32f407xx_matlab.h']]], - ['can_5fier_5fffie0_3123',['CAN_IER_FFIE0',['../group___peripheral___registers___bits___definition.html#gaf926ae29d98a8b72ef48f001fda07fc3',1,'stm32f407xx_matlab.h']]], - ['can_5fier_5fffie0_5fmsk_3124',['CAN_IER_FFIE0_Msk',['../group___peripheral___registers___bits___definition.html#ga8885a2f34117d17dfb78fb78fb18b7a7',1,'stm32f407xx_matlab.h']]], - ['can_5fier_5fffie0_5fpos_3125',['CAN_IER_FFIE0_Pos',['../group___peripheral___registers___bits___definition.html#ga411ce03315531b3f90698b7e9224b93a',1,'stm32f407xx_matlab.h']]], - ['can_5fier_5fffie1_3126',['CAN_IER_FFIE1',['../group___peripheral___registers___bits___definition.html#gaf5a7e9d13e8d96bef2ac1972520b1c4f',1,'stm32f407xx_matlab.h']]], - ['can_5fier_5fffie1_5fmsk_3127',['CAN_IER_FFIE1_Msk',['../group___peripheral___registers___bits___definition.html#ga20cba05b98222a9ce8bf5b5804c78ead',1,'stm32f407xx_matlab.h']]], - ['can_5fier_5fffie1_5fpos_3128',['CAN_IER_FFIE1_Pos',['../group___peripheral___registers___bits___definition.html#gae0c5e16c335ad2459a1726d123b8f720',1,'stm32f407xx_matlab.h']]], - ['can_5fier_5ffmpie0_3129',['CAN_IER_FMPIE0',['../group___peripheral___registers___bits___definition.html#ga59eecd1bb7d1d0e17422a26ae89cf39d',1,'stm32f407xx_matlab.h']]], - ['can_5fier_5ffmpie0_5fmsk_3130',['CAN_IER_FMPIE0_Msk',['../group___peripheral___registers___bits___definition.html#ga6885c5945dc4db64d46aa83bd8367e83',1,'stm32f407xx_matlab.h']]], - ['can_5fier_5ffmpie0_5fpos_3131',['CAN_IER_FMPIE0_Pos',['../group___peripheral___registers___bits___definition.html#ga3325defd7e318b63baa1f78b50394280',1,'stm32f407xx_matlab.h']]], - ['can_5fier_5ffmpie1_3132',['CAN_IER_FMPIE1',['../group___peripheral___registers___bits___definition.html#ga4b8492d1b8ce13fead7869a0e4ef39ed',1,'stm32f407xx_matlab.h']]], - ['can_5fier_5ffmpie1_5fmsk_3133',['CAN_IER_FMPIE1_Msk',['../group___peripheral___registers___bits___definition.html#gac66a68cb8bc52e699f9d83673515c3b9',1,'stm32f407xx_matlab.h']]], - ['can_5fier_5ffmpie1_5fpos_3134',['CAN_IER_FMPIE1_Pos',['../group___peripheral___registers___bits___definition.html#ga8b904e14bd25a2d2e155364c2ebb5c7e',1,'stm32f407xx_matlab.h']]], - ['can_5fier_5ffovie0_3135',['CAN_IER_FOVIE0',['../group___peripheral___registers___bits___definition.html#ga0c423699fdcd2ddddb3046a368505679',1,'stm32f407xx_matlab.h']]], - ['can_5fier_5ffovie0_5fmsk_3136',['CAN_IER_FOVIE0_Msk',['../group___peripheral___registers___bits___definition.html#ga7859520258dfc8c61eca8da04ff180f9',1,'stm32f407xx_matlab.h']]], - ['can_5fier_5ffovie0_5fpos_3137',['CAN_IER_FOVIE0_Pos',['../group___peripheral___registers___bits___definition.html#gab7cded06b69c3ab261928a1b48ece5f9',1,'stm32f407xx_matlab.h']]], - ['can_5fier_5ffovie1_3138',['CAN_IER_FOVIE1',['../group___peripheral___registers___bits___definition.html#ga3734d9bf5cd08ff219b2d8c2f8300dbf',1,'stm32f407xx_matlab.h']]], - ['can_5fier_5ffovie1_5fmsk_3139',['CAN_IER_FOVIE1_Msk',['../group___peripheral___registers___bits___definition.html#ga0256723529d4c2adf64c0f5b6da56e7a',1,'stm32f407xx_matlab.h']]], - ['can_5fier_5ffovie1_5fpos_3140',['CAN_IER_FOVIE1_Pos',['../group___peripheral___registers___bits___definition.html#ga210db948ed64aa24bc8176041966f934',1,'stm32f407xx_matlab.h']]], - ['can_5fier_5flecie_3141',['CAN_IER_LECIE',['../group___peripheral___registers___bits___definition.html#ga81514ecf1b6596e9930906779c4bdf39',1,'stm32f407xx_matlab.h']]], - ['can_5fier_5flecie_5fmsk_3142',['CAN_IER_LECIE_Msk',['../group___peripheral___registers___bits___definition.html#ga386f61a3f7ef21600969ef0c936e255c',1,'stm32f407xx_matlab.h']]], - ['can_5fier_5flecie_5fpos_3143',['CAN_IER_LECIE_Pos',['../group___peripheral___registers___bits___definition.html#ga4ccd7e2e333c2dae013674b5bac0ecbc',1,'stm32f407xx_matlab.h']]], - ['can_5fier_5fslkie_3144',['CAN_IER_SLKIE',['../group___peripheral___registers___bits___definition.html#ga82389b79f21410f5d5f6bef38d192812',1,'stm32f407xx_matlab.h']]], - ['can_5fier_5fslkie_5fmsk_3145',['CAN_IER_SLKIE_Msk',['../group___peripheral___registers___bits___definition.html#gaf34b93be0df4cfdaad8dbb99f4fa1bc7',1,'stm32f407xx_matlab.h']]], - ['can_5fier_5fslkie_5fpos_3146',['CAN_IER_SLKIE_Pos',['../group___peripheral___registers___bits___definition.html#gafa7b49f18204d00911b39f940b63e0f3',1,'stm32f407xx_matlab.h']]], - ['can_5fier_5ftmeie_3147',['CAN_IER_TMEIE',['../group___peripheral___registers___bits___definition.html#gafe027af7acd051f5a52db78608a36e26',1,'stm32f407xx_matlab.h']]], - ['can_5fier_5ftmeie_5fmsk_3148',['CAN_IER_TMEIE_Msk',['../group___peripheral___registers___bits___definition.html#gac38696874c8fbbd05b6413ac11746d6b',1,'stm32f407xx_matlab.h']]], - ['can_5fier_5ftmeie_5fpos_3149',['CAN_IER_TMEIE_Pos',['../group___peripheral___registers___bits___definition.html#gaea8fc846d9892de7b30d31bdf6b54edb',1,'stm32f407xx_matlab.h']]], - ['can_5fier_5fwkuie_3150',['CAN_IER_WKUIE',['../group___peripheral___registers___bits___definition.html#ga37f3438e80288c1791de27042df9838e',1,'stm32f407xx_matlab.h']]], - ['can_5fier_5fwkuie_5fmsk_3151',['CAN_IER_WKUIE_Msk',['../group___peripheral___registers___bits___definition.html#ga181d122c65769851c2cc82f4bd764d80',1,'stm32f407xx_matlab.h']]], - ['can_5fier_5fwkuie_5fpos_3152',['CAN_IER_WKUIE_Pos',['../group___peripheral___registers___bits___definition.html#gaf233f7c7c686ed81c4bc295143eb3a4b',1,'stm32f407xx_matlab.h']]], - ['can_5fmcr_5fabom_3153',['CAN_MCR_ABOM',['../group___peripheral___registers___bits___definition.html#gad7aff5c0a3ead7f937849ab66eba7490',1,'stm32f407xx_matlab.h']]], - ['can_5fmcr_5fabom_5fmsk_3154',['CAN_MCR_ABOM_Msk',['../group___peripheral___registers___bits___definition.html#gaeb5d923de1437f1c441b540c74c6ebd9',1,'stm32f407xx_matlab.h']]], - ['can_5fmcr_5fabom_5fpos_3155',['CAN_MCR_ABOM_Pos',['../group___peripheral___registers___bits___definition.html#ga1cc28c00c9766a53c2ba8c0d42feba92',1,'stm32f407xx_matlab.h']]], - ['can_5fmcr_5fawum_3156',['CAN_MCR_AWUM',['../group___peripheral___registers___bits___definition.html#gaa2745f1a565c3f2ec5b16612d1fd66e0',1,'stm32f407xx_matlab.h']]], - ['can_5fmcr_5fawum_5fmsk_3157',['CAN_MCR_AWUM_Msk',['../group___peripheral___registers___bits___definition.html#ga5a62120fa01d4bb366f02555ddd6a0d4',1,'stm32f407xx_matlab.h']]], - ['can_5fmcr_5fawum_5fpos_3158',['CAN_MCR_AWUM_Pos',['../group___peripheral___registers___bits___definition.html#ga191178a51ef5243b2ecf547aeb1d5eb9',1,'stm32f407xx_matlab.h']]], - ['can_5fmcr_5fdbf_3159',['CAN_MCR_DBF',['../group___peripheral___registers___bits___definition.html#gaf74445921cdd9df3e44b6b9ba8f67491',1,'stm32f407xx_matlab.h']]], - ['can_5fmcr_5fdbf_5fmsk_3160',['CAN_MCR_DBF_Msk',['../group___peripheral___registers___bits___definition.html#ga7284f1c36b5a1422050a8204ff673557',1,'stm32f407xx_matlab.h']]], - ['can_5fmcr_5fdbf_5fpos_3161',['CAN_MCR_DBF_Pos',['../group___peripheral___registers___bits___definition.html#gaa32526e641ef7eed19b3b8db98befbd4',1,'stm32f407xx_matlab.h']]], - ['can_5fmcr_5finrq_3162',['CAN_MCR_INRQ',['../group___peripheral___registers___bits___definition.html#ga0cf12be5661908dbe38aa14cd4c3a356',1,'stm32f407xx_matlab.h']]], - ['can_5fmcr_5finrq_5fmsk_3163',['CAN_MCR_INRQ_Msk',['../group___peripheral___registers___bits___definition.html#gaf7afc4335014982a4cfac31de0cdbebc',1,'stm32f407xx_matlab.h']]], - ['can_5fmcr_5finrq_5fpos_3164',['CAN_MCR_INRQ_Pos',['../group___peripheral___registers___bits___definition.html#ga5bcdd01eb82046959b22b3d254073c22',1,'stm32f407xx_matlab.h']]], - ['can_5fmcr_5fnart_3165',['CAN_MCR_NART',['../group___peripheral___registers___bits___definition.html#ga2774f04e286942d36a5b6135c8028049',1,'stm32f407xx_matlab.h']]], - ['can_5fmcr_5fnart_5fmsk_3166',['CAN_MCR_NART_Msk',['../group___peripheral___registers___bits___definition.html#ga4f03d5006b20e144bec0f3739345bc60',1,'stm32f407xx_matlab.h']]], - ['can_5fmcr_5fnart_5fpos_3167',['CAN_MCR_NART_Pos',['../group___peripheral___registers___bits___definition.html#gaa15d8c6ceddacbfdcfe732d9bcb0cd50',1,'stm32f407xx_matlab.h']]], - ['can_5fmcr_5freset_3168',['CAN_MCR_RESET',['../group___peripheral___registers___bits___definition.html#ga410fdbad37a9dbda508b8c437277e79f',1,'stm32f407xx_matlab.h']]], - ['can_5fmcr_5freset_5fmsk_3169',['CAN_MCR_RESET_Msk',['../group___peripheral___registers___bits___definition.html#gafa6c92ebbf496383e92f30301169b1b7',1,'stm32f407xx_matlab.h']]], - ['can_5fmcr_5freset_5fpos_3170',['CAN_MCR_RESET_Pos',['../group___peripheral___registers___bits___definition.html#ga21598a34f72464c29fccedd71b51d519',1,'stm32f407xx_matlab.h']]], - ['can_5fmcr_5frflm_3171',['CAN_MCR_RFLM',['../group___peripheral___registers___bits___definition.html#ga501125ff257a7d02c35a0d6dcbaa2ba8',1,'stm32f407xx_matlab.h']]], - ['can_5fmcr_5frflm_5fmsk_3172',['CAN_MCR_RFLM_Msk',['../group___peripheral___registers___bits___definition.html#ga5ff5789ccbdf18976ec76ab44cd798e0',1,'stm32f407xx_matlab.h']]], - ['can_5fmcr_5frflm_5fpos_3173',['CAN_MCR_RFLM_Pos',['../group___peripheral___registers___bits___definition.html#gaf728107056b7bc1dbab277967ad255bc',1,'stm32f407xx_matlab.h']]], - ['can_5fmcr_5fsleep_3174',['CAN_MCR_SLEEP',['../group___peripheral___registers___bits___definition.html#gadf9602dfb2f95b481b6e642b95991176',1,'stm32f407xx_matlab.h']]], - ['can_5fmcr_5fsleep_5fmsk_3175',['CAN_MCR_SLEEP_Msk',['../group___peripheral___registers___bits___definition.html#gac4181676e5d50d29f09805be441efc9b',1,'stm32f407xx_matlab.h']]], - ['can_5fmcr_5fsleep_5fpos_3176',['CAN_MCR_SLEEP_Pos',['../group___peripheral___registers___bits___definition.html#ga60009c948dbdf525fb2fc932d988c245',1,'stm32f407xx_matlab.h']]], - ['can_5fmcr_5fttcm_3177',['CAN_MCR_TTCM',['../group___peripheral___registers___bits___definition.html#ga32b2eda9cad8a969c5d2349bd1d853bb',1,'stm32f407xx_matlab.h']]], - ['can_5fmcr_5fttcm_5fmsk_3178',['CAN_MCR_TTCM_Msk',['../group___peripheral___registers___bits___definition.html#ga2a53a37c946b05dbafc5b7392d5163a3',1,'stm32f407xx_matlab.h']]], - ['can_5fmcr_5fttcm_5fpos_3179',['CAN_MCR_TTCM_Pos',['../group___peripheral___registers___bits___definition.html#ga16b15e96f1e4a0203c3974949c2e54a2',1,'stm32f407xx_matlab.h']]], - ['can_5fmcr_5ftxfp_3180',['CAN_MCR_TXFP',['../group___peripheral___registers___bits___definition.html#ga35e7e66f9cd8cb6efa6a80367d2294a9',1,'stm32f407xx_matlab.h']]], - ['can_5fmcr_5ftxfp_5fmsk_3181',['CAN_MCR_TXFP_Msk',['../group___peripheral___registers___bits___definition.html#gacc1c0efc56b72fa75b6e25d773ada7d2',1,'stm32f407xx_matlab.h']]], - ['can_5fmcr_5ftxfp_5fpos_3182',['CAN_MCR_TXFP_Pos',['../group___peripheral___registers___bits___definition.html#ga80233affcdda60458e98647fe1416f85',1,'stm32f407xx_matlab.h']]], - ['can_5fmsr_5ferri_3183',['CAN_MSR_ERRI',['../group___peripheral___registers___bits___definition.html#ga9c424768e9e963402f37cb95ae87a1ae',1,'stm32f407xx_matlab.h']]], - ['can_5fmsr_5ferri_5fmsk_3184',['CAN_MSR_ERRI_Msk',['../group___peripheral___registers___bits___definition.html#ga8a189bb7f091383b4cbc858f14cf1dbc',1,'stm32f407xx_matlab.h']]], - ['can_5fmsr_5ferri_5fpos_3185',['CAN_MSR_ERRI_Pos',['../group___peripheral___registers___bits___definition.html#ga1ff8b9d234d0cd377443d4cc21ccd663',1,'stm32f407xx_matlab.h']]], - ['can_5fmsr_5finak_3186',['CAN_MSR_INAK',['../group___peripheral___registers___bits___definition.html#ga2871cee90ebecb760bab16e9c039b682',1,'stm32f407xx_matlab.h']]], - ['can_5fmsr_5finak_5fmsk_3187',['CAN_MSR_INAK_Msk',['../group___peripheral___registers___bits___definition.html#gac65998a2ace7015bb67d9a4a64e4fba5',1,'stm32f407xx_matlab.h']]], - ['can_5fmsr_5finak_5fpos_3188',['CAN_MSR_INAK_Pos',['../group___peripheral___registers___bits___definition.html#gaf2a392cb8353ef23ff078a068ad8cdf9',1,'stm32f407xx_matlab.h']]], - ['can_5fmsr_5frx_3189',['CAN_MSR_RX',['../group___peripheral___registers___bits___definition.html#ga6564a1d2f23f246053188a454264eb4b',1,'stm32f407xx_matlab.h']]], - ['can_5fmsr_5frx_5fmsk_3190',['CAN_MSR_RX_Msk',['../group___peripheral___registers___bits___definition.html#ga453cbc8d18bbadf9be9ec9b7987f1dc4',1,'stm32f407xx_matlab.h']]], - ['can_5fmsr_5frx_5fpos_3191',['CAN_MSR_RX_Pos',['../group___peripheral___registers___bits___definition.html#gaef4c2abade47710dcb184a0f406eaf85',1,'stm32f407xx_matlab.h']]], - ['can_5fmsr_5frxm_3192',['CAN_MSR_RXM',['../group___peripheral___registers___bits___definition.html#ga67f8e1140b0304930d5b4f2a041a7884',1,'stm32f407xx_matlab.h']]], - ['can_5fmsr_5frxm_5fmsk_3193',['CAN_MSR_RXM_Msk',['../group___peripheral___registers___bits___definition.html#ga8eec1fe9e0ab8545330e597a28d9035d',1,'stm32f407xx_matlab.h']]], - ['can_5fmsr_5frxm_5fpos_3194',['CAN_MSR_RXM_Pos',['../group___peripheral___registers___bits___definition.html#ga9e954c04ec46d198ac7e9b88f46e9a93',1,'stm32f407xx_matlab.h']]], - ['can_5fmsr_5fsamp_3195',['CAN_MSR_SAMP',['../group___peripheral___registers___bits___definition.html#gaf68038824bb78c4a5c4dee1730848f69',1,'stm32f407xx_matlab.h']]], - ['can_5fmsr_5fsamp_5fmsk_3196',['CAN_MSR_SAMP_Msk',['../group___peripheral___registers___bits___definition.html#ga092ef8e336f9e5bf5121d0a5c28606cb',1,'stm32f407xx_matlab.h']]], - ['can_5fmsr_5fsamp_5fpos_3197',['CAN_MSR_SAMP_Pos',['../group___peripheral___registers___bits___definition.html#gab7ede877266831078649ab791547ba3e',1,'stm32f407xx_matlab.h']]], - ['can_5fmsr_5fslak_3198',['CAN_MSR_SLAK',['../group___peripheral___registers___bits___definition.html#gaf1611badb362f0fd9047af965509f074',1,'stm32f407xx_matlab.h']]], - ['can_5fmsr_5fslak_5fmsk_3199',['CAN_MSR_SLAK_Msk',['../group___peripheral___registers___bits___definition.html#ga81eeee3e575f4bd0cf494ad946b11a90',1,'stm32f407xx_matlab.h']]], - ['can_5fmsr_5fslak_5fpos_3200',['CAN_MSR_SLAK_Pos',['../group___peripheral___registers___bits___definition.html#gac27c0590f11b2b5fb894a60a9700567c',1,'stm32f407xx_matlab.h']]], - ['can_5fmsr_5fslaki_3201',['CAN_MSR_SLAKI',['../group___peripheral___registers___bits___definition.html#ga47ab62ae123c791de27ad05dde5bee91',1,'stm32f407xx_matlab.h']]], - ['can_5fmsr_5fslaki_5fmsk_3202',['CAN_MSR_SLAKI_Msk',['../group___peripheral___registers___bits___definition.html#ga5373a083dae43a5491e9bc91d9478dd5',1,'stm32f407xx_matlab.h']]], - ['can_5fmsr_5fslaki_5fpos_3203',['CAN_MSR_SLAKI_Pos',['../group___peripheral___registers___bits___definition.html#ga5030b442fd7a20eb18897625d8d68078',1,'stm32f407xx_matlab.h']]], - ['can_5fmsr_5ftxm_3204',['CAN_MSR_TXM',['../group___peripheral___registers___bits___definition.html#ga651580d35b658e90ea831cb13b8a8988',1,'stm32f407xx_matlab.h']]], - ['can_5fmsr_5ftxm_5fmsk_3205',['CAN_MSR_TXM_Msk',['../group___peripheral___registers___bits___definition.html#ga9ef1d9966b0022bbbeef87229714ec59',1,'stm32f407xx_matlab.h']]], - ['can_5fmsr_5ftxm_5fpos_3206',['CAN_MSR_TXM_Pos',['../group___peripheral___registers___bits___definition.html#gad3d01c4e4a870b78aca2a679d1936095',1,'stm32f407xx_matlab.h']]], - ['can_5fmsr_5fwkui_3207',['CAN_MSR_WKUI',['../group___peripheral___registers___bits___definition.html#ga0f4c753b96d21c5001b39ad5b08519fc',1,'stm32f407xx_matlab.h']]], - ['can_5fmsr_5fwkui_5fmsk_3208',['CAN_MSR_WKUI_Msk',['../group___peripheral___registers___bits___definition.html#gaad3ddd5d76a1f1e9af5926464efff245',1,'stm32f407xx_matlab.h']]], - ['can_5fmsr_5fwkui_5fpos_3209',['CAN_MSR_WKUI_Pos',['../group___peripheral___registers___bits___definition.html#ga953a3a5616c5bff5392ff196772915d7',1,'stm32f407xx_matlab.h']]], - ['can_5frdh0r_5fdata4_3210',['CAN_RDH0R_DATA4',['../group___peripheral___registers___bits___definition.html#ga4dc7309c31cda93d05bb1fe1c923646c',1,'stm32f407xx_matlab.h']]], - ['can_5frdh0r_5fdata4_5fmsk_3211',['CAN_RDH0R_DATA4_Msk',['../group___peripheral___registers___bits___definition.html#ga043ce7187baa93bc909445ec56a283b1',1,'stm32f407xx_matlab.h']]], - ['can_5frdh0r_5fdata4_5fpos_3212',['CAN_RDH0R_DATA4_Pos',['../group___peripheral___registers___bits___definition.html#ga3cb8238c1f77ff904290afdc572b31bc',1,'stm32f407xx_matlab.h']]], - ['can_5frdh0r_5fdata5_3213',['CAN_RDH0R_DATA5',['../group___peripheral___registers___bits___definition.html#ga577eba5ab3a66283f5c0837e91f1776a',1,'stm32f407xx_matlab.h']]], - ['can_5frdh0r_5fdata5_5fmsk_3214',['CAN_RDH0R_DATA5_Msk',['../group___peripheral___registers___bits___definition.html#ga1a76bc6ca34c282e8d5e6d80de4d2ae6',1,'stm32f407xx_matlab.h']]], - ['can_5frdh0r_5fdata5_5fpos_3215',['CAN_RDH0R_DATA5_Pos',['../group___peripheral___registers___bits___definition.html#gafeef959f9d8913e402c9a08f964da52f',1,'stm32f407xx_matlab.h']]], - ['can_5frdh0r_5fdata6_3216',['CAN_RDH0R_DATA6',['../group___peripheral___registers___bits___definition.html#ga27a0bd49dc24e59b776ad5a00aabb97b',1,'stm32f407xx_matlab.h']]], - ['can_5frdh0r_5fdata6_5fmsk_3217',['CAN_RDH0R_DATA6_Msk',['../group___peripheral___registers___bits___definition.html#ga5ea6c132f074602725c9d14d4a66826c',1,'stm32f407xx_matlab.h']]], - ['can_5frdh0r_5fdata6_5fpos_3218',['CAN_RDH0R_DATA6_Pos',['../group___peripheral___registers___bits___definition.html#ga0e54ca30453b2103004ca2b87da2e052',1,'stm32f407xx_matlab.h']]], - ['can_5frdh0r_5fdata7_3219',['CAN_RDH0R_DATA7',['../group___peripheral___registers___bits___definition.html#ga243b8a3632812b2f8c7b447ed635ce5f',1,'stm32f407xx_matlab.h']]], - ['can_5frdh0r_5fdata7_5fmsk_3220',['CAN_RDH0R_DATA7_Msk',['../group___peripheral___registers___bits___definition.html#ga167fa92520367130afbb5e929ff8b542',1,'stm32f407xx_matlab.h']]], - ['can_5frdh0r_5fdata7_5fpos_3221',['CAN_RDH0R_DATA7_Pos',['../group___peripheral___registers___bits___definition.html#ga676e501253a8d78d74a13f9dbc87d222',1,'stm32f407xx_matlab.h']]], - ['can_5frdh1r_5fdata4_3222',['CAN_RDH1R_DATA4',['../group___peripheral___registers___bits___definition.html#gafc2a55c1b5195cf043ef33e79d736255',1,'stm32f407xx_matlab.h']]], - ['can_5frdh1r_5fdata4_5fmsk_3223',['CAN_RDH1R_DATA4_Msk',['../group___peripheral___registers___bits___definition.html#ga0e0ca00fb558f95f4f692d5f7b90d157',1,'stm32f407xx_matlab.h']]], - ['can_5frdh1r_5fdata4_5fpos_3224',['CAN_RDH1R_DATA4_Pos',['../group___peripheral___registers___bits___definition.html#ga48e5ea8ab1e1cf135a10b2dbc69932f2',1,'stm32f407xx_matlab.h']]], - ['can_5frdh1r_5fdata5_3225',['CAN_RDH1R_DATA5',['../group___peripheral___registers___bits___definition.html#ga81d25a1ea5ad28e7db4a2adbb8a651ad',1,'stm32f407xx_matlab.h']]], - ['can_5frdh1r_5fdata5_5fmsk_3226',['CAN_RDH1R_DATA5_Msk',['../group___peripheral___registers___bits___definition.html#ga247617fd1c2c8daa148b3ed059f0603a',1,'stm32f407xx_matlab.h']]], - ['can_5frdh1r_5fdata5_5fpos_3227',['CAN_RDH1R_DATA5_Pos',['../group___peripheral___registers___bits___definition.html#gaacb82a6a71a2687b303c54a5c3aca105',1,'stm32f407xx_matlab.h']]], - ['can_5frdh1r_5fdata6_3228',['CAN_RDH1R_DATA6',['../group___peripheral___registers___bits___definition.html#ga39212ea40388510bde1931f7b3a064ae',1,'stm32f407xx_matlab.h']]], - ['can_5frdh1r_5fdata6_5fmsk_3229',['CAN_RDH1R_DATA6_Msk',['../group___peripheral___registers___bits___definition.html#ga5eeec37fc704ce7cf1c9ef92f6d87635',1,'stm32f407xx_matlab.h']]], - ['can_5frdh1r_5fdata6_5fpos_3230',['CAN_RDH1R_DATA6_Pos',['../group___peripheral___registers___bits___definition.html#gaab2ec9fa28c3b6f72ed102d5d255e875',1,'stm32f407xx_matlab.h']]], - ['can_5frdh1r_5fdata7_3231',['CAN_RDH1R_DATA7',['../group___peripheral___registers___bits___definition.html#gafdfbb90b5ef2ac1e7f23a5f15c0287eb',1,'stm32f407xx_matlab.h']]], - ['can_5frdh1r_5fdata7_5fmsk_3232',['CAN_RDH1R_DATA7_Msk',['../group___peripheral___registers___bits___definition.html#gad9e7a5ddb046143d3ca7c85ddb9c94c0',1,'stm32f407xx_matlab.h']]], - ['can_5frdh1r_5fdata7_5fpos_3233',['CAN_RDH1R_DATA7_Pos',['../group___peripheral___registers___bits___definition.html#ga021f76c67a2d07b56c4e10cd56cc416a',1,'stm32f407xx_matlab.h']]], - ['can_5frdl0r_5fdata0_3234',['CAN_RDL0R_DATA0',['../group___peripheral___registers___bits___definition.html#ga44313106efc3a5a65633168a2ad1928d',1,'stm32f407xx_matlab.h']]], - ['can_5frdl0r_5fdata0_5fmsk_3235',['CAN_RDL0R_DATA0_Msk',['../group___peripheral___registers___bits___definition.html#ga15f91b45288700ef7858e998d598ea21',1,'stm32f407xx_matlab.h']]], - ['can_5frdl0r_5fdata0_5fpos_3236',['CAN_RDL0R_DATA0_Pos',['../group___peripheral___registers___bits___definition.html#gadd7172931b3e1d8cf3daba5edfdd42c4',1,'stm32f407xx_matlab.h']]], - ['can_5frdl0r_5fdata1_3237',['CAN_RDL0R_DATA1',['../group___peripheral___registers___bits___definition.html#ga73d4025ce501af78db93761e8b8c3b9e',1,'stm32f407xx_matlab.h']]], - ['can_5frdl0r_5fdata1_5fmsk_3238',['CAN_RDL0R_DATA1_Msk',['../group___peripheral___registers___bits___definition.html#ga86f144804d9b849f9bf589f9d0d53b4c',1,'stm32f407xx_matlab.h']]], - ['can_5frdl0r_5fdata1_5fpos_3239',['CAN_RDL0R_DATA1_Pos',['../group___peripheral___registers___bits___definition.html#gab942d411c058da0f504d49adabdf7f11',1,'stm32f407xx_matlab.h']]], - ['can_5frdl0r_5fdata2_3240',['CAN_RDL0R_DATA2',['../group___peripheral___registers___bits___definition.html#ga52b3c31ad72881e11a4d3cae073a0df8',1,'stm32f407xx_matlab.h']]], - ['can_5frdl0r_5fdata2_5fmsk_3241',['CAN_RDL0R_DATA2_Msk',['../group___peripheral___registers___bits___definition.html#ga75e00e47c6f9bab7a6602af43e7d9d4d',1,'stm32f407xx_matlab.h']]], - ['can_5frdl0r_5fdata2_5fpos_3242',['CAN_RDL0R_DATA2_Pos',['../group___peripheral___registers___bits___definition.html#gafe0336c208a9884936f3527688c349de',1,'stm32f407xx_matlab.h']]], - ['can_5frdl0r_5fdata3_3243',['CAN_RDL0R_DATA3',['../group___peripheral___registers___bits___definition.html#gad637a53ae780998f95f2bb570d5cd05a',1,'stm32f407xx_matlab.h']]], - ['can_5frdl0r_5fdata3_5fmsk_3244',['CAN_RDL0R_DATA3_Msk',['../group___peripheral___registers___bits___definition.html#gaa0b46bd6794046d7c70d8db43a5c5524',1,'stm32f407xx_matlab.h']]], - ['can_5frdl0r_5fdata3_5fpos_3245',['CAN_RDL0R_DATA3_Pos',['../group___peripheral___registers___bits___definition.html#ga839a3d98930a4ab823b30dc7ac805e9a',1,'stm32f407xx_matlab.h']]], - ['can_5frdl1r_5fdata0_3246',['CAN_RDL1R_DATA0',['../group___peripheral___registers___bits___definition.html#ga1e399fed282a5aac0b25b059fcf04020',1,'stm32f407xx_matlab.h']]], - ['can_5frdl1r_5fdata0_5fmsk_3247',['CAN_RDL1R_DATA0_Msk',['../group___peripheral___registers___bits___definition.html#ga3d11f01bf6ac61f279f5227e5cfa87ac',1,'stm32f407xx_matlab.h']]], - ['can_5frdl1r_5fdata0_5fpos_3248',['CAN_RDL1R_DATA0_Pos',['../group___peripheral___registers___bits___definition.html#gaa5c0ebcd26923922b646df3064f4d5ad',1,'stm32f407xx_matlab.h']]], - ['can_5frdl1r_5fdata1_3249',['CAN_RDL1R_DATA1',['../group___peripheral___registers___bits___definition.html#ga27ec34e08f87e8836f32bbfed52e860a',1,'stm32f407xx_matlab.h']]], - ['can_5frdl1r_5fdata1_5fmsk_3250',['CAN_RDL1R_DATA1_Msk',['../group___peripheral___registers___bits___definition.html#ga2754a3d3971d890a60306c923f4c027d',1,'stm32f407xx_matlab.h']]], - ['can_5frdl1r_5fdata1_5fpos_3251',['CAN_RDL1R_DATA1_Pos',['../group___peripheral___registers___bits___definition.html#gac291bf56ea60efcd3123d4c89fcc00fb',1,'stm32f407xx_matlab.h']]], - ['can_5frdl1r_5fdata2_3252',['CAN_RDL1R_DATA2',['../group___peripheral___registers___bits___definition.html#gaea34eded40932d364743969643a598c4',1,'stm32f407xx_matlab.h']]], - ['can_5frdl1r_5fdata2_5fmsk_3253',['CAN_RDL1R_DATA2_Msk',['../group___peripheral___registers___bits___definition.html#gae5ea71525f58798512e56b01db47f6d5',1,'stm32f407xx_matlab.h']]], - ['can_5frdl1r_5fdata2_5fpos_3254',['CAN_RDL1R_DATA2_Pos',['../group___peripheral___registers___bits___definition.html#ga38f1bee2b3aac2261c4f9c5aa92550bc',1,'stm32f407xx_matlab.h']]], - ['can_5frdl1r_5fdata3_3255',['CAN_RDL1R_DATA3',['../group___peripheral___registers___bits___definition.html#ga80bfe3e724b28e8d2a5b7ac4393212cf',1,'stm32f407xx_matlab.h']]], - ['can_5frdl1r_5fdata3_5fmsk_3256',['CAN_RDL1R_DATA3_Msk',['../group___peripheral___registers___bits___definition.html#ga02684a0300f1d9e9c803b5afefb193fc',1,'stm32f407xx_matlab.h']]], - ['can_5frdl1r_5fdata3_5fpos_3257',['CAN_RDL1R_DATA3_Pos',['../group___peripheral___registers___bits___definition.html#ga7f201d587103efa2fc6da443415d7127',1,'stm32f407xx_matlab.h']]], - ['can_5frdt0r_5fdlc_3258',['CAN_RDT0R_DLC',['../group___peripheral___registers___bits___definition.html#ga17ca0af4afd89e6a1c43ffd1430359b7',1,'stm32f407xx_matlab.h']]], - ['can_5frdt0r_5fdlc_5fmsk_3259',['CAN_RDT0R_DLC_Msk',['../group___peripheral___registers___bits___definition.html#gace43bd7d7388fd3cf4c33142d62ef541',1,'stm32f407xx_matlab.h']]], - ['can_5frdt0r_5fdlc_5fpos_3260',['CAN_RDT0R_DLC_Pos',['../group___peripheral___registers___bits___definition.html#gabcb714f10d7dba636a67e79c0473dbf9',1,'stm32f407xx_matlab.h']]], - ['can_5frdt0r_5ffmi_3261',['CAN_RDT0R_FMI',['../group___peripheral___registers___bits___definition.html#ga5081739b6e21e033b95e68af9331a6d1',1,'stm32f407xx_matlab.h']]], - ['can_5frdt0r_5ffmi_5fmsk_3262',['CAN_RDT0R_FMI_Msk',['../group___peripheral___registers___bits___definition.html#ga9bafb8a31e8370f9d068a1acfe30e222',1,'stm32f407xx_matlab.h']]], - ['can_5frdt0r_5ffmi_5fpos_3263',['CAN_RDT0R_FMI_Pos',['../group___peripheral___registers___bits___definition.html#ga6076b1e14b5a81a0a25e4e8973a28477',1,'stm32f407xx_matlab.h']]], - ['can_5frdt0r_5ftime_3264',['CAN_RDT0R_TIME',['../group___peripheral___registers___bits___definition.html#gae20b7a72690033591eeda7a511ac4a2e',1,'stm32f407xx_matlab.h']]], - ['can_5frdt0r_5ftime_5fmsk_3265',['CAN_RDT0R_TIME_Msk',['../group___peripheral___registers___bits___definition.html#gafcf8581ecb0c6b9bf464155b93f1003a',1,'stm32f407xx_matlab.h']]], - ['can_5frdt0r_5ftime_5fpos_3266',['CAN_RDT0R_TIME_Pos',['../group___peripheral___registers___bits___definition.html#ga44d89e7d66e3f4c953cbaeb271a30ada',1,'stm32f407xx_matlab.h']]], - ['can_5frdt1r_5fdlc_3267',['CAN_RDT1R_DLC',['../group___peripheral___registers___bits___definition.html#ga964b0fa7c70a24a74165c57b3486aae8',1,'stm32f407xx_matlab.h']]], - ['can_5frdt1r_5fdlc_5fmsk_3268',['CAN_RDT1R_DLC_Msk',['../group___peripheral___registers___bits___definition.html#gaa33d633807f57ecc34d45c20e704a330',1,'stm32f407xx_matlab.h']]], - ['can_5frdt1r_5fdlc_5fpos_3269',['CAN_RDT1R_DLC_Pos',['../group___peripheral___registers___bits___definition.html#gab2e0b7a55b05caab1a213c35742696a6',1,'stm32f407xx_matlab.h']]], - ['can_5frdt1r_5ffmi_3270',['CAN_RDT1R_FMI',['../group___peripheral___registers___bits___definition.html#gaf7f72aec91130a20e3a855e78eabb48b',1,'stm32f407xx_matlab.h']]], - ['can_5frdt1r_5ffmi_5fmsk_3271',['CAN_RDT1R_FMI_Msk',['../group___peripheral___registers___bits___definition.html#ga41ca9a71d5f237de7e4d758b2b5850b5',1,'stm32f407xx_matlab.h']]], - ['can_5frdt1r_5ffmi_5fpos_3272',['CAN_RDT1R_FMI_Pos',['../group___peripheral___registers___bits___definition.html#ga683fd9390aff2459ef66760d02f7f654',1,'stm32f407xx_matlab.h']]], - ['can_5frdt1r_5ftime_3273',['CAN_RDT1R_TIME',['../group___peripheral___registers___bits___definition.html#gac112cba5a4cd0b541c1150263132c68a',1,'stm32f407xx_matlab.h']]], - ['can_5frdt1r_5ftime_5fmsk_3274',['CAN_RDT1R_TIME_Msk',['../group___peripheral___registers___bits___definition.html#ga22e450deb1ed7a778b47b4cebad44f42',1,'stm32f407xx_matlab.h']]], - ['can_5frdt1r_5ftime_5fpos_3275',['CAN_RDT1R_TIME_Pos',['../group___peripheral___registers___bits___definition.html#ga4a2fdfc1f548be70a30752803fea6a27',1,'stm32f407xx_matlab.h']]], - ['can_5frf0r_5ffmp0_3276',['CAN_RF0R_FMP0',['../group___peripheral___registers___bits___definition.html#ga9e23f3d7947e58531524d77b5c4741cc',1,'stm32f407xx_matlab.h']]], - ['can_5frf0r_5ffmp0_5fmsk_3277',['CAN_RF0R_FMP0_Msk',['../group___peripheral___registers___bits___definition.html#gad74fc3f4e266805779daf7f69194bd97',1,'stm32f407xx_matlab.h']]], - ['can_5frf0r_5ffmp0_5fpos_3278',['CAN_RF0R_FMP0_Pos',['../group___peripheral___registers___bits___definition.html#gab868d2c9f9b9e52d7d3b3e8227b8e862',1,'stm32f407xx_matlab.h']]], - ['can_5frf0r_5ffovr0_3279',['CAN_RF0R_FOVR0',['../group___peripheral___registers___bits___definition.html#ga2a3d15b3abab8199c16e26a3dffdc8b8',1,'stm32f407xx_matlab.h']]], - ['can_5frf0r_5ffovr0_5fmsk_3280',['CAN_RF0R_FOVR0_Msk',['../group___peripheral___registers___bits___definition.html#gaa0699f23293ca0bc417c7c1a343f53ba',1,'stm32f407xx_matlab.h']]], - ['can_5frf0r_5ffovr0_5fpos_3281',['CAN_RF0R_FOVR0_Pos',['../group___peripheral___registers___bits___definition.html#gae0aad54077e9896ec6f7599d126e54e1',1,'stm32f407xx_matlab.h']]], - ['can_5frf0r_5ffull0_3282',['CAN_RF0R_FULL0',['../group___peripheral___registers___bits___definition.html#gae934674f6e22a758e430f32cfc386d70',1,'stm32f407xx_matlab.h']]], - ['can_5frf0r_5ffull0_5fmsk_3283',['CAN_RF0R_FULL0_Msk',['../group___peripheral___registers___bits___definition.html#ga27305e8a2d6f381b6d0ff05d6d0c74ba',1,'stm32f407xx_matlab.h']]], - ['can_5frf0r_5ffull0_5fpos_3284',['CAN_RF0R_FULL0_Pos',['../group___peripheral___registers___bits___definition.html#gaab168d7bfdd89ac5e7654804ff6c16d3',1,'stm32f407xx_matlab.h']]], - ['can_5frf0r_5frfom0_3285',['CAN_RF0R_RFOM0',['../group___peripheral___registers___bits___definition.html#ga74d2db4b9b7d52712e47557dcc61964d',1,'stm32f407xx_matlab.h']]], - ['can_5frf0r_5frfom0_5fmsk_3286',['CAN_RF0R_RFOM0_Msk',['../group___peripheral___registers___bits___definition.html#gae3c768b2f6a6c8b8b434991528110467',1,'stm32f407xx_matlab.h']]], - ['can_5frf0r_5frfom0_5fpos_3287',['CAN_RF0R_RFOM0_Pos',['../group___peripheral___registers___bits___definition.html#gae75e432559ee49ae55397f529f199ad0',1,'stm32f407xx_matlab.h']]], - ['can_5frf1r_5ffmp1_3288',['CAN_RF1R_FMP1',['../group___peripheral___registers___bits___definition.html#ga8f9254d05043df6f21bf96234a03f72f',1,'stm32f407xx_matlab.h']]], - ['can_5frf1r_5ffmp1_5fmsk_3289',['CAN_RF1R_FMP1_Msk',['../group___peripheral___registers___bits___definition.html#ga2b08002573d35c943f136ab6c667f363',1,'stm32f407xx_matlab.h']]], - ['can_5frf1r_5ffmp1_5fpos_3290',['CAN_RF1R_FMP1_Pos',['../group___peripheral___registers___bits___definition.html#ga00fcf8bdc5087d5ff6d55c5206b346f3',1,'stm32f407xx_matlab.h']]], - ['can_5frf1r_5ffovr1_3291',['CAN_RF1R_FOVR1',['../group___peripheral___registers___bits___definition.html#gab5eeaabd4db3825bc53d860aca8d7590',1,'stm32f407xx_matlab.h']]], - ['can_5frf1r_5ffovr1_5fmsk_3292',['CAN_RF1R_FOVR1_Msk',['../group___peripheral___registers___bits___definition.html#gacee8c5b572eb85447912dcbc62aac97c',1,'stm32f407xx_matlab.h']]], - ['can_5frf1r_5ffovr1_5fpos_3293',['CAN_RF1R_FOVR1_Pos',['../group___peripheral___registers___bits___definition.html#ga9faad05fc13813a198405bb5f064fb05',1,'stm32f407xx_matlab.h']]], - ['can_5frf1r_5ffull1_3294',['CAN_RF1R_FULL1',['../group___peripheral___registers___bits___definition.html#gabdaa12fe4d14254cc4a6a4de749a7d0a',1,'stm32f407xx_matlab.h']]], - ['can_5frf1r_5ffull1_5fmsk_3295',['CAN_RF1R_FULL1_Msk',['../group___peripheral___registers___bits___definition.html#gae0ac244ab1c525913bfcc3d03b9ab06f',1,'stm32f407xx_matlab.h']]], - ['can_5frf1r_5ffull1_5fpos_3296',['CAN_RF1R_FULL1_Pos',['../group___peripheral___registers___bits___definition.html#gadc6bab0544e01fcd1bcf0487139f729e',1,'stm32f407xx_matlab.h']]], - ['can_5frf1r_5frfom1_3297',['CAN_RF1R_RFOM1',['../group___peripheral___registers___bits___definition.html#ga6930f860de4a90e3344e63fbc209b9ab',1,'stm32f407xx_matlab.h']]], - ['can_5frf1r_5frfom1_5fmsk_3298',['CAN_RF1R_RFOM1_Msk',['../group___peripheral___registers___bits___definition.html#gaec98a01deaf5464a0ba9052a028bf483',1,'stm32f407xx_matlab.h']]], - ['can_5frf1r_5frfom1_5fpos_3299',['CAN_RF1R_RFOM1_Pos',['../group___peripheral___registers___bits___definition.html#gaa2e95cc6d93830acc8669871fff26939',1,'stm32f407xx_matlab.h']]], - ['can_5fri0r_5fexid_3300',['CAN_RI0R_EXID',['../group___peripheral___registers___bits___definition.html#ga4d81487e8b340810e3193cd8f1386240',1,'stm32f407xx_matlab.h']]], - ['can_5fri0r_5fexid_5fmsk_3301',['CAN_RI0R_EXID_Msk',['../group___peripheral___registers___bits___definition.html#gacf95ca68eadd026273958ef22678dc37',1,'stm32f407xx_matlab.h']]], - ['can_5fri0r_5fexid_5fpos_3302',['CAN_RI0R_EXID_Pos',['../group___peripheral___registers___bits___definition.html#ga782a6732674fa4ee7b2581709d2a45b7',1,'stm32f407xx_matlab.h']]], - ['can_5fri0r_5fide_3303',['CAN_RI0R_IDE',['../group___peripheral___registers___bits___definition.html#ga688074182caafff289c921548bc9afca',1,'stm32f407xx_matlab.h']]], - ['can_5fri0r_5fide_5fmsk_3304',['CAN_RI0R_IDE_Msk',['../group___peripheral___registers___bits___definition.html#ga80f4b044d79d1e751d54a604b637c26c',1,'stm32f407xx_matlab.h']]], - ['can_5fri0r_5fide_5fpos_3305',['CAN_RI0R_IDE_Pos',['../group___peripheral___registers___bits___definition.html#gad1f9c6a0d27ac2f4c05fa3d0f6aab88b',1,'stm32f407xx_matlab.h']]], - ['can_5fri0r_5frtr_3306',['CAN_RI0R_RTR',['../group___peripheral___registers___bits___definition.html#ga41f4780b822a42834bf1927eb92b4fba',1,'stm32f407xx_matlab.h']]], - ['can_5fri0r_5frtr_5fmsk_3307',['CAN_RI0R_RTR_Msk',['../group___peripheral___registers___bits___definition.html#ga833387b84a95443455bffb4a6390b7b9',1,'stm32f407xx_matlab.h']]], - ['can_5fri0r_5frtr_5fpos_3308',['CAN_RI0R_RTR_Pos',['../group___peripheral___registers___bits___definition.html#ga1534235598ebdacd295d6e248ca1732f',1,'stm32f407xx_matlab.h']]], - ['can_5fri0r_5fstid_3309',['CAN_RI0R_STID',['../group___peripheral___registers___bits___definition.html#ga101aa355c83b8c7d068f02b7dcc5b98f',1,'stm32f407xx_matlab.h']]], - ['can_5fri0r_5fstid_5fmsk_3310',['CAN_RI0R_STID_Msk',['../group___peripheral___registers___bits___definition.html#ga02a63ecf925c0930d317bdbf439e9486',1,'stm32f407xx_matlab.h']]], - ['can_5fri0r_5fstid_5fpos_3311',['CAN_RI0R_STID_Pos',['../group___peripheral___registers___bits___definition.html#gac72774c622ac99f08cc1f7e2814be168',1,'stm32f407xx_matlab.h']]], - ['can_5fri1r_5fexid_3312',['CAN_RI1R_EXID',['../group___peripheral___registers___bits___definition.html#ga2ca45b282f2582c91450d4e1204121cf',1,'stm32f407xx_matlab.h']]], - ['can_5fri1r_5fexid_5fmsk_3313',['CAN_RI1R_EXID_Msk',['../group___peripheral___registers___bits___definition.html#ga1f8b1261a02cdc318caab37e7cff0f5f',1,'stm32f407xx_matlab.h']]], - ['can_5fri1r_5fexid_5fpos_3314',['CAN_RI1R_EXID_Pos',['../group___peripheral___registers___bits___definition.html#gafd36dce59fa984a072c332c0fae7a29a',1,'stm32f407xx_matlab.h']]], - ['can_5fri1r_5fide_3315',['CAN_RI1R_IDE',['../group___peripheral___registers___bits___definition.html#ga8dcedeb4250767a66a4d60c67e367cf8',1,'stm32f407xx_matlab.h']]], - ['can_5fri1r_5fide_5fmsk_3316',['CAN_RI1R_IDE_Msk',['../group___peripheral___registers___bits___definition.html#ga68b6e874a467bca60ef46e3ffb30f098',1,'stm32f407xx_matlab.h']]], - ['can_5fri1r_5fide_5fpos_3317',['CAN_RI1R_IDE_Pos',['../group___peripheral___registers___bits___definition.html#ga0367ce97761605b4cdc45b529f791417',1,'stm32f407xx_matlab.h']]], - ['can_5fri1r_5frtr_3318',['CAN_RI1R_RTR',['../group___peripheral___registers___bits___definition.html#gafbd0ecd9579a339bffb95ea3b7c9f1e8',1,'stm32f407xx_matlab.h']]], - ['can_5fri1r_5frtr_5fmsk_3319',['CAN_RI1R_RTR_Msk',['../group___peripheral___registers___bits___definition.html#ga2e9658541637a4332c1ccf67b34a8fb9',1,'stm32f407xx_matlab.h']]], - ['can_5fri1r_5frtr_5fpos_3320',['CAN_RI1R_RTR_Pos',['../group___peripheral___registers___bits___definition.html#ga726ed3ef9d26e53ea346a23731e0e967',1,'stm32f407xx_matlab.h']]], - ['can_5fri1r_5fstid_3321',['CAN_RI1R_STID',['../group___peripheral___registers___bits___definition.html#ga7f3c3aab0f24533821188d14901b3980',1,'stm32f407xx_matlab.h']]], - ['can_5fri1r_5fstid_5fmsk_3322',['CAN_RI1R_STID_Msk',['../group___peripheral___registers___bits___definition.html#ga27b4d8511b43ff7f56e18c15c6b260e0',1,'stm32f407xx_matlab.h']]], - ['can_5fri1r_5fstid_5fpos_3323',['CAN_RI1R_STID_Pos',['../group___peripheral___registers___bits___definition.html#ga7488f084446b0c0907a5f4851f48d38c',1,'stm32f407xx_matlab.h']]], - ['can_5ftdh0r_5fdata4_3324',['CAN_TDH0R_DATA4',['../group___peripheral___registers___bits___definition.html#ga0114ae75b33f978ca7825f7bcd836982',1,'stm32f407xx_matlab.h']]], - ['can_5ftdh0r_5fdata4_5fmsk_3325',['CAN_TDH0R_DATA4_Msk',['../group___peripheral___registers___bits___definition.html#ga2389e6393c4c90eac09ecadd67e77203',1,'stm32f407xx_matlab.h']]], - ['can_5ftdh0r_5fdata4_5fpos_3326',['CAN_TDH0R_DATA4_Pos',['../group___peripheral___registers___bits___definition.html#ga67239c62f07e5a4d0f348f9595d4fb0e',1,'stm32f407xx_matlab.h']]], - ['can_5ftdh0r_5fdata5_3327',['CAN_TDH0R_DATA5',['../group___peripheral___registers___bits___definition.html#gaf5b6a0742ac1bcd5ef0408cb0f92ef75',1,'stm32f407xx_matlab.h']]], - ['can_5ftdh0r_5fdata5_5fmsk_3328',['CAN_TDH0R_DATA5_Msk',['../group___peripheral___registers___bits___definition.html#gadeaa64cd95a54957ee402f9edbd62411',1,'stm32f407xx_matlab.h']]], - ['can_5ftdh0r_5fdata5_5fpos_3329',['CAN_TDH0R_DATA5_Pos',['../group___peripheral___registers___bits___definition.html#gac19fa11ce4c6d4c00690d453a3b42354',1,'stm32f407xx_matlab.h']]], - ['can_5ftdh0r_5fdata6_3330',['CAN_TDH0R_DATA6',['../group___peripheral___registers___bits___definition.html#gac8ea7090da55c7cc9993235efa1c4a02',1,'stm32f407xx_matlab.h']]], - ['can_5ftdh0r_5fdata6_5fmsk_3331',['CAN_TDH0R_DATA6_Msk',['../group___peripheral___registers___bits___definition.html#ga80deb2e84b16aa300ba4b6dad03ced70',1,'stm32f407xx_matlab.h']]], - ['can_5ftdh0r_5fdata6_5fpos_3332',['CAN_TDH0R_DATA6_Pos',['../group___peripheral___registers___bits___definition.html#ga19b1609d2ed4f6b59e9b175e022123b5',1,'stm32f407xx_matlab.h']]], - ['can_5ftdh0r_5fdata7_3333',['CAN_TDH0R_DATA7',['../group___peripheral___registers___bits___definition.html#ga6021a4045fbfd71817bf9aec6cbc731c',1,'stm32f407xx_matlab.h']]], - ['can_5ftdh0r_5fdata7_5fmsk_3334',['CAN_TDH0R_DATA7_Msk',['../group___peripheral___registers___bits___definition.html#gad14d21df0b2b694450b769b900c1161e',1,'stm32f407xx_matlab.h']]], - ['can_5ftdh0r_5fdata7_5fpos_3335',['CAN_TDH0R_DATA7_Pos',['../group___peripheral___registers___bits___definition.html#gaed76c2a3e8d2946eeed952bb2ff20e94',1,'stm32f407xx_matlab.h']]], - ['can_5ftdh1r_5fdata4_3336',['CAN_TDH1R_DATA4',['../group___peripheral___registers___bits___definition.html#ga41c3f19eea0d63211f643833da984c90',1,'stm32f407xx_matlab.h']]], - ['can_5ftdh1r_5fdata4_5fmsk_3337',['CAN_TDH1R_DATA4_Msk',['../group___peripheral___registers___bits___definition.html#ga44d94c7419786e7bba7ec0a1b35395cb',1,'stm32f407xx_matlab.h']]], - ['can_5ftdh1r_5fdata4_5fpos_3338',['CAN_TDH1R_DATA4_Pos',['../group___peripheral___registers___bits___definition.html#ga4acd3f2aaf9f8a62bc486733feb4fba8',1,'stm32f407xx_matlab.h']]], - ['can_5ftdh1r_5fdata5_3339',['CAN_TDH1R_DATA5',['../group___peripheral___registers___bits___definition.html#ga35cbe73d2ce87b6aaf19510818610d16',1,'stm32f407xx_matlab.h']]], - ['can_5ftdh1r_5fdata5_5fmsk_3340',['CAN_TDH1R_DATA5_Msk',['../group___peripheral___registers___bits___definition.html#gaa946d8a10e5f952a5c4eda78228042af',1,'stm32f407xx_matlab.h']]], - ['can_5ftdh1r_5fdata5_5fpos_3341',['CAN_TDH1R_DATA5_Pos',['../group___peripheral___registers___bits___definition.html#ga7f2050d91710f0b977d984e164067f9f',1,'stm32f407xx_matlab.h']]], - ['can_5ftdh1r_5fdata6_3342',['CAN_TDH1R_DATA6',['../group___peripheral___registers___bits___definition.html#ga1b731ca095cbad8e56ba4147c14d7128',1,'stm32f407xx_matlab.h']]], - ['can_5ftdh1r_5fdata6_5fmsk_3343',['CAN_TDH1R_DATA6_Msk',['../group___peripheral___registers___bits___definition.html#gaff0a58abbdfa5e21213dbc2f82935250',1,'stm32f407xx_matlab.h']]], - ['can_5ftdh1r_5fdata6_5fpos_3344',['CAN_TDH1R_DATA6_Pos',['../group___peripheral___registers___bits___definition.html#ga8f3a0e5d886a7db9accd6e2d1316174f',1,'stm32f407xx_matlab.h']]], - ['can_5ftdh1r_5fdata7_3345',['CAN_TDH1R_DATA7',['../group___peripheral___registers___bits___definition.html#gaec56ce4aba46e836d44e2c034a9ed817',1,'stm32f407xx_matlab.h']]], - ['can_5ftdh1r_5fdata7_5fmsk_3346',['CAN_TDH1R_DATA7_Msk',['../group___peripheral___registers___bits___definition.html#ga625d5b8e464b8dfc789e4191f55444cf',1,'stm32f407xx_matlab.h']]], - ['can_5ftdh1r_5fdata7_5fpos_3347',['CAN_TDH1R_DATA7_Pos',['../group___peripheral___registers___bits___definition.html#gae01db20e595c85191c3abd91a1f74717',1,'stm32f407xx_matlab.h']]], - ['can_5ftdh2r_5fdata4_3348',['CAN_TDH2R_DATA4',['../group___peripheral___registers___bits___definition.html#ga23a93a13da2f302ecd2f0c462065428d',1,'stm32f407xx_matlab.h']]], - ['can_5ftdh2r_5fdata4_5fmsk_3349',['CAN_TDH2R_DATA4_Msk',['../group___peripheral___registers___bits___definition.html#gae061c8ed2699c7a7be546e5825946c60',1,'stm32f407xx_matlab.h']]], - ['can_5ftdh2r_5fdata4_5fpos_3350',['CAN_TDH2R_DATA4_Pos',['../group___peripheral___registers___bits___definition.html#ga61800b82cf4fd9229d91e7f9e3ac7158',1,'stm32f407xx_matlab.h']]], - ['can_5ftdh2r_5fdata5_3351',['CAN_TDH2R_DATA5',['../group___peripheral___registers___bits___definition.html#gab9f372328c8d1e4fe2503d45aed50fb6',1,'stm32f407xx_matlab.h']]], - ['can_5ftdh2r_5fdata5_5fmsk_3352',['CAN_TDH2R_DATA5_Msk',['../group___peripheral___registers___bits___definition.html#gaf5ace2c6eb67c621bf571e285b76b007',1,'stm32f407xx_matlab.h']]], - ['can_5ftdh2r_5fdata5_5fpos_3353',['CAN_TDH2R_DATA5_Pos',['../group___peripheral___registers___bits___definition.html#gabd401f60132154e0d004d262ba48e862',1,'stm32f407xx_matlab.h']]], - ['can_5ftdh2r_5fdata6_3354',['CAN_TDH2R_DATA6',['../group___peripheral___registers___bits___definition.html#gae96248bcf102a3c6f39f72cdcf8e4fe5',1,'stm32f407xx_matlab.h']]], - ['can_5ftdh2r_5fdata6_5fmsk_3355',['CAN_TDH2R_DATA6_Msk',['../group___peripheral___registers___bits___definition.html#ga621fec630f1758b3f11a2e52e62fa970',1,'stm32f407xx_matlab.h']]], - ['can_5ftdh2r_5fdata6_5fpos_3356',['CAN_TDH2R_DATA6_Pos',['../group___peripheral___registers___bits___definition.html#gaf512e0c618635a2b56048d1712930843',1,'stm32f407xx_matlab.h']]], - ['can_5ftdh2r_5fdata7_3357',['CAN_TDH2R_DATA7',['../group___peripheral___registers___bits___definition.html#ga895341b943e4b01938857b84a0b0dbda',1,'stm32f407xx_matlab.h']]], - ['can_5ftdh2r_5fdata7_5fmsk_3358',['CAN_TDH2R_DATA7_Msk',['../group___peripheral___registers___bits___definition.html#gaee62fccda69811932555a125bce78606',1,'stm32f407xx_matlab.h']]], - ['can_5ftdh2r_5fdata7_5fpos_3359',['CAN_TDH2R_DATA7_Pos',['../group___peripheral___registers___bits___definition.html#ga57346e5378ab4dbab77f4f84d5a1e780',1,'stm32f407xx_matlab.h']]], - ['can_5ftdl0r_5fdata0_3360',['CAN_TDL0R_DATA0',['../group___peripheral___registers___bits___definition.html#gadec3350607b41410ddb6e00a71a4384e',1,'stm32f407xx_matlab.h']]], - ['can_5ftdl0r_5fdata0_5fmsk_3361',['CAN_TDL0R_DATA0_Msk',['../group___peripheral___registers___bits___definition.html#ga21c0f147ab22439d7677e400651302c4',1,'stm32f407xx_matlab.h']]], - ['can_5ftdl0r_5fdata0_5fpos_3362',['CAN_TDL0R_DATA0_Pos',['../group___peripheral___registers___bits___definition.html#gae2dfd1e20e5283d40302140066d527d3',1,'stm32f407xx_matlab.h']]], - ['can_5ftdl0r_5fdata1_3363',['CAN_TDL0R_DATA1',['../group___peripheral___registers___bits___definition.html#ga1cd20d218027e7432178c67414475830',1,'stm32f407xx_matlab.h']]], - ['can_5ftdl0r_5fdata1_5fmsk_3364',['CAN_TDL0R_DATA1_Msk',['../group___peripheral___registers___bits___definition.html#gae03b879d3e573023038e211ea211ae9f',1,'stm32f407xx_matlab.h']]], - ['can_5ftdl0r_5fdata1_5fpos_3365',['CAN_TDL0R_DATA1_Pos',['../group___peripheral___registers___bits___definition.html#ga1ebdc896d4816e5d5eee1c1700c7fb25',1,'stm32f407xx_matlab.h']]], - ['can_5ftdl0r_5fdata2_3366',['CAN_TDL0R_DATA2',['../group___peripheral___registers___bits___definition.html#gaa04384f0a7c5026c91a33a005c755d68',1,'stm32f407xx_matlab.h']]], - ['can_5ftdl0r_5fdata2_5fmsk_3367',['CAN_TDL0R_DATA2_Msk',['../group___peripheral___registers___bits___definition.html#gadcc788dc5db08c074c7026e60d3af7cb',1,'stm32f407xx_matlab.h']]], - ['can_5ftdl0r_5fdata2_5fpos_3368',['CAN_TDL0R_DATA2_Pos',['../group___peripheral___registers___bits___definition.html#gad46a5808e83c8ce1c6c2da8c3ee2898d',1,'stm32f407xx_matlab.h']]], - ['can_5ftdl0r_5fdata3_3369',['CAN_TDL0R_DATA3',['../group___peripheral___registers___bits___definition.html#ga283a1bfa52851ea4ee45f45817985752',1,'stm32f407xx_matlab.h']]], - ['can_5ftdl0r_5fdata3_5fmsk_3370',['CAN_TDL0R_DATA3_Msk',['../group___peripheral___registers___bits___definition.html#ga782c6f20d550a56c15fe265a75105255',1,'stm32f407xx_matlab.h']]], - ['can_5ftdl0r_5fdata3_5fpos_3371',['CAN_TDL0R_DATA3_Pos',['../group___peripheral___registers___bits___definition.html#ga66d8189fd904326f4be09972047fda59',1,'stm32f407xx_matlab.h']]], - ['can_5ftdl1r_5fdata0_3372',['CAN_TDL1R_DATA0',['../group___peripheral___registers___bits___definition.html#ga21abc05257bcdfa47fc824b4d806a105',1,'stm32f407xx_matlab.h']]], - ['can_5ftdl1r_5fdata0_5fmsk_3373',['CAN_TDL1R_DATA0_Msk',['../group___peripheral___registers___bits___definition.html#ga16520ea88ace96a458b0818d3e4d5cf2',1,'stm32f407xx_matlab.h']]], - ['can_5ftdl1r_5fdata0_5fpos_3374',['CAN_TDL1R_DATA0_Pos',['../group___peripheral___registers___bits___definition.html#ga4a9794992e11c29ba12088b41a9215cd',1,'stm32f407xx_matlab.h']]], - ['can_5ftdl1r_5fdata1_3375',['CAN_TDL1R_DATA1',['../group___peripheral___registers___bits___definition.html#ga0bf459dee1be706b38141722be67e4ab',1,'stm32f407xx_matlab.h']]], - ['can_5ftdl1r_5fdata1_5fmsk_3376',['CAN_TDL1R_DATA1_Msk',['../group___peripheral___registers___bits___definition.html#ga22d121d05d7faac3231ab8b0cc3fd4e2',1,'stm32f407xx_matlab.h']]], - ['can_5ftdl1r_5fdata1_5fpos_3377',['CAN_TDL1R_DATA1_Pos',['../group___peripheral___registers___bits___definition.html#ga15870798808b9bf8e3b389d99f8205bd',1,'stm32f407xx_matlab.h']]], - ['can_5ftdl1r_5fdata2_3378',['CAN_TDL1R_DATA2',['../group___peripheral___registers___bits___definition.html#gaeb92a65c225432fab0daa30808d5065c',1,'stm32f407xx_matlab.h']]], - ['can_5ftdl1r_5fdata2_5fmsk_3379',['CAN_TDL1R_DATA2_Msk',['../group___peripheral___registers___bits___definition.html#ga06359cf64606bd479a4a5e074c5e70ac',1,'stm32f407xx_matlab.h']]], - ['can_5ftdl1r_5fdata2_5fpos_3380',['CAN_TDL1R_DATA2_Pos',['../group___peripheral___registers___bits___definition.html#ga822b0dd09688ddb0241506b3657d3e76',1,'stm32f407xx_matlab.h']]], - ['can_5ftdl1r_5fdata3_3381',['CAN_TDL1R_DATA3',['../group___peripheral___registers___bits___definition.html#ga482506faa59360c6a48aa9bc55a024c4',1,'stm32f407xx_matlab.h']]], - ['can_5ftdl1r_5fdata3_5fmsk_3382',['CAN_TDL1R_DATA3_Msk',['../group___peripheral___registers___bits___definition.html#ga17d98be9066ebe1cf701052043be89bc',1,'stm32f407xx_matlab.h']]], - ['can_5ftdl1r_5fdata3_5fpos_3383',['CAN_TDL1R_DATA3_Pos',['../group___peripheral___registers___bits___definition.html#ga26002007d5645d59e1de29fecb91c906',1,'stm32f407xx_matlab.h']]], - ['can_5ftdl2r_5fdata0_3384',['CAN_TDL2R_DATA0',['../group___peripheral___registers___bits___definition.html#ga7a9852d0f6058c19f0e678228ea14a21',1,'stm32f407xx_matlab.h']]], - ['can_5ftdl2r_5fdata0_5fmsk_3385',['CAN_TDL2R_DATA0_Msk',['../group___peripheral___registers___bits___definition.html#gad9d44c13085429bc76007fa3aff31964',1,'stm32f407xx_matlab.h']]], - ['can_5ftdl2r_5fdata0_5fpos_3386',['CAN_TDL2R_DATA0_Pos',['../group___peripheral___registers___bits___definition.html#ga3e9d0286857aaf4744cae03ce9379b74',1,'stm32f407xx_matlab.h']]], - ['can_5ftdl2r_5fdata1_3387',['CAN_TDL2R_DATA1',['../group___peripheral___registers___bits___definition.html#gad5be1bcda68f562be669184b30727be1',1,'stm32f407xx_matlab.h']]], - ['can_5ftdl2r_5fdata1_5fmsk_3388',['CAN_TDL2R_DATA1_Msk',['../group___peripheral___registers___bits___definition.html#gac9e6c39a9c27791be19e6cde5f8c45c7',1,'stm32f407xx_matlab.h']]], - ['can_5ftdl2r_5fdata1_5fpos_3389',['CAN_TDL2R_DATA1_Pos',['../group___peripheral___registers___bits___definition.html#ga58e2da210f0a94f67e20d4c6179034c6',1,'stm32f407xx_matlab.h']]], - ['can_5ftdl2r_5fdata2_3390',['CAN_TDL2R_DATA2',['../group___peripheral___registers___bits___definition.html#ga62cd5e7f3e98fe5b247998d39ebdd6fb',1,'stm32f407xx_matlab.h']]], - ['can_5ftdl2r_5fdata2_5fmsk_3391',['CAN_TDL2R_DATA2_Msk',['../group___peripheral___registers___bits___definition.html#ga4dae494d814d7c4c5785066ffc203f11',1,'stm32f407xx_matlab.h']]], - ['can_5ftdl2r_5fdata2_5fpos_3392',['CAN_TDL2R_DATA2_Pos',['../group___peripheral___registers___bits___definition.html#ga0d7a1f37d86fae4a8efd1beb1322a4de',1,'stm32f407xx_matlab.h']]], - ['can_5ftdl2r_5fdata3_3393',['CAN_TDL2R_DATA3',['../group___peripheral___registers___bits___definition.html#ga3d76ed3982f13fb34a54d62f0caa3fa2',1,'stm32f407xx_matlab.h']]], - ['can_5ftdl2r_5fdata3_5fmsk_3394',['CAN_TDL2R_DATA3_Msk',['../group___peripheral___registers___bits___definition.html#ga9551d67aa378b224e317e4f298ccd195',1,'stm32f407xx_matlab.h']]], - ['can_5ftdl2r_5fdata3_5fpos_3395',['CAN_TDL2R_DATA3_Pos',['../group___peripheral___registers___bits___definition.html#ga7b77eb2ec1d44ecd49eae21f5d238a32',1,'stm32f407xx_matlab.h']]], - ['can_5ftdt0r_5fdlc_3396',['CAN_TDT0R_DLC',['../group___peripheral___registers___bits___definition.html#gacf812eaee11f12863773b3f8e95ae6e2',1,'stm32f407xx_matlab.h']]], - ['can_5ftdt0r_5fdlc_5fmsk_3397',['CAN_TDT0R_DLC_Msk',['../group___peripheral___registers___bits___definition.html#ga06a3a47edaaf175482a18feccbce3a61',1,'stm32f407xx_matlab.h']]], - ['can_5ftdt0r_5fdlc_5fpos_3398',['CAN_TDT0R_DLC_Pos',['../group___peripheral___registers___bits___definition.html#ga4ba7824b92498610f685f712c1075702',1,'stm32f407xx_matlab.h']]], - ['can_5ftdt0r_5ftgt_3399',['CAN_TDT0R_TGT',['../group___peripheral___registers___bits___definition.html#gad2d329960b527a62fab099a084bfa906',1,'stm32f407xx_matlab.h']]], - ['can_5ftdt0r_5ftgt_5fmsk_3400',['CAN_TDT0R_TGT_Msk',['../group___peripheral___registers___bits___definition.html#ga394785c0a3d16b48d7bbcc524d2821a3',1,'stm32f407xx_matlab.h']]], - ['can_5ftdt0r_5ftgt_5fpos_3401',['CAN_TDT0R_TGT_Pos',['../group___peripheral___registers___bits___definition.html#gac770efaeca5e93c9dbde1fa508ab79aa',1,'stm32f407xx_matlab.h']]], - ['can_5ftdt0r_5ftime_3402',['CAN_TDT0R_TIME',['../group___peripheral___registers___bits___definition.html#ga104ba91151bf88edd44593b1690b879a',1,'stm32f407xx_matlab.h']]], - ['can_5ftdt0r_5ftime_5fmsk_3403',['CAN_TDT0R_TIME_Msk',['../group___peripheral___registers___bits___definition.html#ga544adf091e79aa36d9d7a6e47bafcb41',1,'stm32f407xx_matlab.h']]], - ['can_5ftdt0r_5ftime_5fpos_3404',['CAN_TDT0R_TIME_Pos',['../group___peripheral___registers___bits___definition.html#ga5ffd9f8d93bb7f96dfc8f2b202986ec5',1,'stm32f407xx_matlab.h']]], - ['can_5ftdt1r_5fdlc_3405',['CAN_TDT1R_DLC',['../group___peripheral___registers___bits___definition.html#ga68ef8b6cb43a80d29c5fc318a67acd3b',1,'stm32f407xx_matlab.h']]], - ['can_5ftdt1r_5fdlc_5fmsk_3406',['CAN_TDT1R_DLC_Msk',['../group___peripheral___registers___bits___definition.html#ga78cb2a08e7abfd8105acee53c2fe6957',1,'stm32f407xx_matlab.h']]], - ['can_5ftdt1r_5fdlc_5fpos_3407',['CAN_TDT1R_DLC_Pos',['../group___peripheral___registers___bits___definition.html#ga5b088fcd5a224ff04b87ca90fe4ad93a',1,'stm32f407xx_matlab.h']]], - ['can_5ftdt1r_5ftgt_3408',['CAN_TDT1R_TGT',['../group___peripheral___registers___bits___definition.html#ga35757787e6481553885fdf4fd2738c4b',1,'stm32f407xx_matlab.h']]], - ['can_5ftdt1r_5ftgt_5fmsk_3409',['CAN_TDT1R_TGT_Msk',['../group___peripheral___registers___bits___definition.html#ga36274682f7c568c18db742816468f08d',1,'stm32f407xx_matlab.h']]], - ['can_5ftdt1r_5ftgt_5fpos_3410',['CAN_TDT1R_TGT_Pos',['../group___peripheral___registers___bits___definition.html#gaf17aa4d8323302bc493c93d38be34b60',1,'stm32f407xx_matlab.h']]], - ['can_5ftdt1r_5ftime_3411',['CAN_TDT1R_TIME',['../group___peripheral___registers___bits___definition.html#gad28ac334a59a6679c362611d65666910',1,'stm32f407xx_matlab.h']]], - ['can_5ftdt1r_5ftime_5fmsk_3412',['CAN_TDT1R_TIME_Msk',['../group___peripheral___registers___bits___definition.html#ga96a341aceed7cefa4f144685b047b5aa',1,'stm32f407xx_matlab.h']]], - ['can_5ftdt1r_5ftime_5fpos_3413',['CAN_TDT1R_TIME_Pos',['../group___peripheral___registers___bits___definition.html#ga37df5b75c3aedc37c37f308d32b178b6',1,'stm32f407xx_matlab.h']]], - ['can_5ftdt2r_5fdlc_3414',['CAN_TDT2R_DLC',['../group___peripheral___registers___bits___definition.html#ga52898eb9fa3bcf0b8086220971af49f5',1,'stm32f407xx_matlab.h']]], - ['can_5ftdt2r_5fdlc_5fmsk_3415',['CAN_TDT2R_DLC_Msk',['../group___peripheral___registers___bits___definition.html#ga63e75710f89ae715962fd2e2c5465edb',1,'stm32f407xx_matlab.h']]], - ['can_5ftdt2r_5fdlc_5fpos_3416',['CAN_TDT2R_DLC_Pos',['../group___peripheral___registers___bits___definition.html#ga45143135ab0f9c01d85cca11d7949b26',1,'stm32f407xx_matlab.h']]], - ['can_5ftdt2r_5ftgt_3417',['CAN_TDT2R_TGT',['../group___peripheral___registers___bits___definition.html#ga4c51b43d309b56e8a64724ef1517033e',1,'stm32f407xx_matlab.h']]], - ['can_5ftdt2r_5ftgt_5fmsk_3418',['CAN_TDT2R_TGT_Msk',['../group___peripheral___registers___bits___definition.html#ga01d388232664bf958d0396c19e39c815',1,'stm32f407xx_matlab.h']]], - ['can_5ftdt2r_5ftgt_5fpos_3419',['CAN_TDT2R_TGT_Pos',['../group___peripheral___registers___bits___definition.html#gaa9e5a3e9a2526007920e8a255b7e1c3a',1,'stm32f407xx_matlab.h']]], - ['can_5ftdt2r_5ftime_3420',['CAN_TDT2R_TIME',['../group___peripheral___registers___bits___definition.html#ga508aea584f7c81700b485916a13431fa',1,'stm32f407xx_matlab.h']]], - ['can_5ftdt2r_5ftime_5fmsk_3421',['CAN_TDT2R_TIME_Msk',['../group___peripheral___registers___bits___definition.html#ga9585327a9b756069b9a3ee0727e35f19',1,'stm32f407xx_matlab.h']]], - ['can_5ftdt2r_5ftime_5fpos_3422',['CAN_TDT2R_TIME_Pos',['../group___peripheral___registers___bits___definition.html#gaceba646b9f79f648862f0ec8cf1e6a85',1,'stm32f407xx_matlab.h']]], - ['can_5fti0r_5fexid_3423',['CAN_TI0R_EXID',['../group___peripheral___registers___bits___definition.html#ga894df6ad0d2976fe643dcb77052672f5',1,'stm32f407xx_matlab.h']]], - ['can_5fti0r_5fexid_5fmsk_3424',['CAN_TI0R_EXID_Msk',['../group___peripheral___registers___bits___definition.html#ga2138165e39efac11d31381e1d7c72bfa',1,'stm32f407xx_matlab.h']]], - ['can_5fti0r_5fexid_5fpos_3425',['CAN_TI0R_EXID_Pos',['../group___peripheral___registers___bits___definition.html#gae4e738c64e396face3bbc9c5011e6b0e',1,'stm32f407xx_matlab.h']]], - ['can_5fti0r_5fide_3426',['CAN_TI0R_IDE',['../group___peripheral___registers___bits___definition.html#ga06f761a877f8ad39f878284f69119c0b',1,'stm32f407xx_matlab.h']]], - ['can_5fti0r_5fide_5fmsk_3427',['CAN_TI0R_IDE_Msk',['../group___peripheral___registers___bits___definition.html#ga080d97de6d25618d06b2d0a453c692b6',1,'stm32f407xx_matlab.h']]], - ['can_5fti0r_5fide_5fpos_3428',['CAN_TI0R_IDE_Pos',['../group___peripheral___registers___bits___definition.html#ga10b3ea5dc6c4d2f6d3925debfc2ba267',1,'stm32f407xx_matlab.h']]], - ['can_5fti0r_5frtr_3429',['CAN_TI0R_RTR',['../group___peripheral___registers___bits___definition.html#gad5556f2ceb5b71b8afa76a18a31cbb6a',1,'stm32f407xx_matlab.h']]], - ['can_5fti0r_5frtr_5fmsk_3430',['CAN_TI0R_RTR_Msk',['../group___peripheral___registers___bits___definition.html#gab713759c47fadc25119dd265c413f771',1,'stm32f407xx_matlab.h']]], - ['can_5fti0r_5frtr_5fpos_3431',['CAN_TI0R_RTR_Pos',['../group___peripheral___registers___bits___definition.html#ga98b5217c83959ca007cb09ba59f1c182',1,'stm32f407xx_matlab.h']]], - ['can_5fti0r_5fstid_3432',['CAN_TI0R_STID',['../group___peripheral___registers___bits___definition.html#ga4d3b5882e1f9f76f5cfebffb5bc2f717',1,'stm32f407xx_matlab.h']]], - ['can_5fti0r_5fstid_5fmsk_3433',['CAN_TI0R_STID_Msk',['../group___peripheral___registers___bits___definition.html#gad4b180d9e1ecf00b104d18670496a8db',1,'stm32f407xx_matlab.h']]], - ['can_5fti0r_5fstid_5fpos_3434',['CAN_TI0R_STID_Pos',['../group___peripheral___registers___bits___definition.html#gab9e827ddbaa36f5651329cc61375221f',1,'stm32f407xx_matlab.h']]], - ['can_5fti0r_5ftxrq_3435',['CAN_TI0R_TXRQ',['../group___peripheral___registers___bits___definition.html#ga7b79cbb7ebb7f3419aa6ac04bd76899a',1,'stm32f407xx_matlab.h']]], - ['can_5fti0r_5ftxrq_5fmsk_3436',['CAN_TI0R_TXRQ_Msk',['../group___peripheral___registers___bits___definition.html#ga53cf2d76df5b85e7363ca6fb45e71c4a',1,'stm32f407xx_matlab.h']]], - ['can_5fti0r_5ftxrq_5fpos_3437',['CAN_TI0R_TXRQ_Pos',['../group___peripheral___registers___bits___definition.html#ga255ce6dd558937c9b33efa43d01b7029',1,'stm32f407xx_matlab.h']]], - ['can_5fti1r_5fexid_3438',['CAN_TI1R_EXID',['../group___peripheral___registers___bits___definition.html#ga6c660943fa3c70c4974c2dacd3e4ca2e',1,'stm32f407xx_matlab.h']]], - ['can_5fti1r_5fexid_5fmsk_3439',['CAN_TI1R_EXID_Msk',['../group___peripheral___registers___bits___definition.html#ga8ba8b24afd72b47c403129c09a6f295f',1,'stm32f407xx_matlab.h']]], - ['can_5fti1r_5fexid_5fpos_3440',['CAN_TI1R_EXID_Pos',['../group___peripheral___registers___bits___definition.html#gab927997e1cb30013ce0c58a974a1ea55',1,'stm32f407xx_matlab.h']]], - ['can_5fti1r_5fide_3441',['CAN_TI1R_IDE',['../group___peripheral___registers___bits___definition.html#ga8f338f3e295b7b512ed865b3f9a8d6de',1,'stm32f407xx_matlab.h']]], - ['can_5fti1r_5fide_5fmsk_3442',['CAN_TI1R_IDE_Msk',['../group___peripheral___registers___bits___definition.html#ga20f905ac8ef34db338cd9b9e94ea7216',1,'stm32f407xx_matlab.h']]], - ['can_5fti1r_5fide_5fpos_3443',['CAN_TI1R_IDE_Pos',['../group___peripheral___registers___bits___definition.html#ga176b1ffea4ad6af7a07044e30d9a210e',1,'stm32f407xx_matlab.h']]], - ['can_5fti1r_5frtr_3444',['CAN_TI1R_RTR',['../group___peripheral___registers___bits___definition.html#ga476cde56b1a2a13cde8477d5178ba34b',1,'stm32f407xx_matlab.h']]], - ['can_5fti1r_5frtr_5fmsk_3445',['CAN_TI1R_RTR_Msk',['../group___peripheral___registers___bits___definition.html#ga2f27bd0f65fe4d7afe69a92c28bef94e',1,'stm32f407xx_matlab.h']]], - ['can_5fti1r_5frtr_5fpos_3446',['CAN_TI1R_RTR_Pos',['../group___peripheral___registers___bits___definition.html#ga35a4cc56a2487c645c3b318bfba5e8ca',1,'stm32f407xx_matlab.h']]], - ['can_5fti1r_5fstid_3447',['CAN_TI1R_STID',['../group___peripheral___registers___bits___definition.html#ga842071768c2f8f5eae11a764a77dd0dd',1,'stm32f407xx_matlab.h']]], - ['can_5fti1r_5fstid_5fmsk_3448',['CAN_TI1R_STID_Msk',['../group___peripheral___registers___bits___definition.html#ga2fb9bb620f8051f9059d78eb2fd09cd9',1,'stm32f407xx_matlab.h']]], - ['can_5fti1r_5fstid_5fpos_3449',['CAN_TI1R_STID_Pos',['../group___peripheral___registers___bits___definition.html#ga2a5e1691eb28536f2773609a195e4cbf',1,'stm32f407xx_matlab.h']]], - ['can_5fti1r_5ftxrq_3450',['CAN_TI1R_TXRQ',['../group___peripheral___registers___bits___definition.html#ga0adf4a08415673753fafedf463f93bee',1,'stm32f407xx_matlab.h']]], - ['can_5fti1r_5ftxrq_5fmsk_3451',['CAN_TI1R_TXRQ_Msk',['../group___peripheral___registers___bits___definition.html#ga89f8f9283cb55ff6427db96afb6ad799',1,'stm32f407xx_matlab.h']]], - ['can_5fti1r_5ftxrq_5fpos_3452',['CAN_TI1R_TXRQ_Pos',['../group___peripheral___registers___bits___definition.html#gaab1e199d262fd92f1702125a8e8f5b49',1,'stm32f407xx_matlab.h']]], - ['can_5fti2r_5fexid_3453',['CAN_TI2R_EXID',['../group___peripheral___registers___bits___definition.html#gae62678bd1dc39aae5a153e9c9b3c3f3b',1,'stm32f407xx_matlab.h']]], - ['can_5fti2r_5fexid_5fmsk_3454',['CAN_TI2R_EXID_Msk',['../group___peripheral___registers___bits___definition.html#gade10da0694545f61f922cc3679f719d1',1,'stm32f407xx_matlab.h']]], - ['can_5fti2r_5fexid_5fpos_3455',['CAN_TI2R_EXID_Pos',['../group___peripheral___registers___bits___definition.html#gafd2af643048de0df22426f9066d19223',1,'stm32f407xx_matlab.h']]], - ['can_5fti2r_5fide_3456',['CAN_TI2R_IDE',['../group___peripheral___registers___bits___definition.html#gac1d888a2225c77452f73bf66fb0e1b78',1,'stm32f407xx_matlab.h']]], - ['can_5fti2r_5fide_5fmsk_3457',['CAN_TI2R_IDE_Msk',['../group___peripheral___registers___bits___definition.html#gab5048adf1f603ea5d5170f3f9bcb92b4',1,'stm32f407xx_matlab.h']]], - ['can_5fti2r_5fide_5fpos_3458',['CAN_TI2R_IDE_Pos',['../group___peripheral___registers___bits___definition.html#gade77331f4ecfa76912b1a1b439583b61',1,'stm32f407xx_matlab.h']]], - ['can_5fti2r_5frtr_3459',['CAN_TI2R_RTR',['../group___peripheral___registers___bits___definition.html#ga980cfab3daebb05da35b6166a051385d',1,'stm32f407xx_matlab.h']]], - ['can_5fti2r_5frtr_5fmsk_3460',['CAN_TI2R_RTR_Msk',['../group___peripheral___registers___bits___definition.html#gafe417e434f32c25426c52b68fb763c9f',1,'stm32f407xx_matlab.h']]], - ['can_5fti2r_5frtr_5fpos_3461',['CAN_TI2R_RTR_Pos',['../group___peripheral___registers___bits___definition.html#ga7ac8d95e007f7ca50f787eac4e08aa1e',1,'stm32f407xx_matlab.h']]], - ['can_5fti2r_5fstid_3462',['CAN_TI2R_STID',['../group___peripheral___registers___bits___definition.html#ga41c8bd734dd29caa40d34ced3981443a',1,'stm32f407xx_matlab.h']]], - ['can_5fti2r_5fstid_5fmsk_3463',['CAN_TI2R_STID_Msk',['../group___peripheral___registers___bits___definition.html#ga78165cdc898ec9184cf14df3d1940a46',1,'stm32f407xx_matlab.h']]], - ['can_5fti2r_5fstid_5fpos_3464',['CAN_TI2R_STID_Pos',['../group___peripheral___registers___bits___definition.html#ga2fa5a1ec336dd0151f1027aa25379708',1,'stm32f407xx_matlab.h']]], - ['can_5fti2r_5ftxrq_3465',['CAN_TI2R_TXRQ',['../group___peripheral___registers___bits___definition.html#gab4edd8438a684e353c497f80cb37365f',1,'stm32f407xx_matlab.h']]], - ['can_5fti2r_5ftxrq_5fmsk_3466',['CAN_TI2R_TXRQ_Msk',['../group___peripheral___registers___bits___definition.html#ga76f8681c59cc25db5a1089ecfc20a2ce',1,'stm32f407xx_matlab.h']]], - ['can_5fti2r_5ftxrq_5fpos_3467',['CAN_TI2R_TXRQ_Pos',['../group___peripheral___registers___bits___definition.html#ga5fa18e2cbbb88117b1b6272c0c1ffea4',1,'stm32f407xx_matlab.h']]], - ['can_5ftsr_5fabrq0_3468',['CAN_TSR_ABRQ0',['../group___peripheral___registers___bits___definition.html#gafdac6b87a303b0d0ec9b0d94a54ae31f',1,'stm32f407xx_matlab.h']]], - ['can_5ftsr_5fabrq0_5fmsk_3469',['CAN_TSR_ABRQ0_Msk',['../group___peripheral___registers___bits___definition.html#gaa78f950ccfd5a5a906c03de00a311047',1,'stm32f407xx_matlab.h']]], - ['can_5ftsr_5fabrq0_5fpos_3470',['CAN_TSR_ABRQ0_Pos',['../group___peripheral___registers___bits___definition.html#ga56679e8aea1650e19f2baf79b35be24f',1,'stm32f407xx_matlab.h']]], - ['can_5ftsr_5fabrq1_3471',['CAN_TSR_ABRQ1',['../group___peripheral___registers___bits___definition.html#ga4c44a4e585b3ab1c37a6c2c28c90d6cd',1,'stm32f407xx_matlab.h']]], - ['can_5ftsr_5fabrq1_5fmsk_3472',['CAN_TSR_ABRQ1_Msk',['../group___peripheral___registers___bits___definition.html#gadca8d9c91c9b53a361a07cea552fe847',1,'stm32f407xx_matlab.h']]], - ['can_5ftsr_5fabrq1_5fpos_3473',['CAN_TSR_ABRQ1_Pos',['../group___peripheral___registers___bits___definition.html#ga2254de573340c2b341cecb12bb6ead4e',1,'stm32f407xx_matlab.h']]], - ['can_5ftsr_5fabrq2_3474',['CAN_TSR_ABRQ2',['../group___peripheral___registers___bits___definition.html#ga2a3b7e4be7cebb35ad66cb85b82901bb',1,'stm32f407xx_matlab.h']]], - ['can_5ftsr_5fabrq2_5fmsk_3475',['CAN_TSR_ABRQ2_Msk',['../group___peripheral___registers___bits___definition.html#gafba8518081068f7375284a1e07873417',1,'stm32f407xx_matlab.h']]], - ['can_5ftsr_5fabrq2_5fpos_3476',['CAN_TSR_ABRQ2_Pos',['../group___peripheral___registers___bits___definition.html#ga5ad0f8e1da30d1f2b0c6713ae0cc2793',1,'stm32f407xx_matlab.h']]], - ['can_5ftsr_5falst0_3477',['CAN_TSR_ALST0',['../group___peripheral___registers___bits___definition.html#ga9b94ea5001d70a26ec32d9dc6ff76e47',1,'stm32f407xx_matlab.h']]], - ['can_5ftsr_5falst0_5fmsk_3478',['CAN_TSR_ALST0_Msk',['../group___peripheral___registers___bits___definition.html#ga9d2ee6ceab2eab0f30a108d406855c7e',1,'stm32f407xx_matlab.h']]], - ['can_5ftsr_5falst0_5fpos_3479',['CAN_TSR_ALST0_Pos',['../group___peripheral___registers___bits___definition.html#ga91b96c96a75628fa3b50f792e68b2b27',1,'stm32f407xx_matlab.h']]], - ['can_5ftsr_5falst1_3480',['CAN_TSR_ALST1',['../group___peripheral___registers___bits___definition.html#ga7a34d996177f23148c9b4cd6b0a80529',1,'stm32f407xx_matlab.h']]], - ['can_5ftsr_5falst1_5fmsk_3481',['CAN_TSR_ALST1_Msk',['../group___peripheral___registers___bits___definition.html#ga9ffcef1919cf06d2874bff8879d69c23',1,'stm32f407xx_matlab.h']]], - ['can_5ftsr_5falst1_5fpos_3482',['CAN_TSR_ALST1_Pos',['../group___peripheral___registers___bits___definition.html#gad3647d7d831be09723b38baaf9011fe0',1,'stm32f407xx_matlab.h']]], - ['can_5ftsr_5falst2_3483',['CAN_TSR_ALST2',['../group___peripheral___registers___bits___definition.html#ga75db1172038ebd72db1ed2fedc6108ff',1,'stm32f407xx_matlab.h']]], - ['can_5ftsr_5falst2_5fmsk_3484',['CAN_TSR_ALST2_Msk',['../group___peripheral___registers___bits___definition.html#gac5a24da79f81578dafc2126d5f731d4a',1,'stm32f407xx_matlab.h']]], - ['can_5ftsr_5falst2_5fpos_3485',['CAN_TSR_ALST2_Pos',['../group___peripheral___registers___bits___definition.html#ga435fe7e72dd93d43d2a3f1bd89a89c44',1,'stm32f407xx_matlab.h']]], - ['can_5ftsr_5fcode_3486',['CAN_TSR_CODE',['../group___peripheral___registers___bits___definition.html#gac00145ea43822f362f3d473bba62fa13',1,'stm32f407xx_matlab.h']]], - ['can_5ftsr_5fcode_5fmsk_3487',['CAN_TSR_CODE_Msk',['../group___peripheral___registers___bits___definition.html#ga13f9f007576f8a12578052bdbd224681',1,'stm32f407xx_matlab.h']]], - ['can_5ftsr_5fcode_5fpos_3488',['CAN_TSR_CODE_Pos',['../group___peripheral___registers___bits___definition.html#gaca63bcf7a21cf13d7fcd42d49ee2a59f',1,'stm32f407xx_matlab.h']]], - ['can_5ftsr_5flow_3489',['CAN_TSR_LOW',['../group___peripheral___registers___bits___definition.html#ga96c6453caa447cc4a9961d6ee5dea74e',1,'stm32f407xx_matlab.h']]], - ['can_5ftsr_5flow0_3490',['CAN_TSR_LOW0',['../group___peripheral___registers___bits___definition.html#ga79ff582efea1d7be2d1de7a1fd1a2b65',1,'stm32f407xx_matlab.h']]], - ['can_5ftsr_5flow0_5fmsk_3491',['CAN_TSR_LOW0_Msk',['../group___peripheral___registers___bits___definition.html#ga0ae04ec8ef32d4f5aa583628114cb54e',1,'stm32f407xx_matlab.h']]], - ['can_5ftsr_5flow0_5fpos_3492',['CAN_TSR_LOW0_Pos',['../group___peripheral___registers___bits___definition.html#gaca4490d8d7d5ccfdf3200cf4be7d6641',1,'stm32f407xx_matlab.h']]], - ['can_5ftsr_5flow1_3493',['CAN_TSR_LOW1',['../group___peripheral___registers___bits___definition.html#gac1e550c2e6a5f8425322f9943fd7c7ed',1,'stm32f407xx_matlab.h']]], - ['can_5ftsr_5flow1_5fmsk_3494',['CAN_TSR_LOW1_Msk',['../group___peripheral___registers___bits___definition.html#ga4b5f0c70b09a3395c07d6b2287210b7d',1,'stm32f407xx_matlab.h']]], - ['can_5ftsr_5flow1_5fpos_3495',['CAN_TSR_LOW1_Pos',['../group___peripheral___registers___bits___definition.html#ga6cb85fb2c45304df1a329b7d2320c511',1,'stm32f407xx_matlab.h']]], - ['can_5ftsr_5flow2_3496',['CAN_TSR_LOW2',['../group___peripheral___registers___bits___definition.html#gadd1db2c2ce76b732fdb71df65fb8124f',1,'stm32f407xx_matlab.h']]], - ['can_5ftsr_5flow2_5fmsk_3497',['CAN_TSR_LOW2_Msk',['../group___peripheral___registers___bits___definition.html#ga987f19b94125300653186bb50bb43ca6',1,'stm32f407xx_matlab.h']]], - ['can_5ftsr_5flow2_5fpos_3498',['CAN_TSR_LOW2_Pos',['../group___peripheral___registers___bits___definition.html#gaa822557268b20255c2be98727a357202',1,'stm32f407xx_matlab.h']]], - ['can_5ftsr_5flow_5fmsk_3499',['CAN_TSR_LOW_Msk',['../group___peripheral___registers___bits___definition.html#gacd34530d99bc8ff61a5e6ce04caf7d67',1,'stm32f407xx_matlab.h']]], - ['can_5ftsr_5flow_5fpos_3500',['CAN_TSR_LOW_Pos',['../group___peripheral___registers___bits___definition.html#ga702291f34c1368501b753d7af3d553fe',1,'stm32f407xx_matlab.h']]], - ['can_5ftsr_5frqcp0_3501',['CAN_TSR_RQCP0',['../group___peripheral___registers___bits___definition.html#ga4a4809b8908618df57e6393cc7fe0f52',1,'stm32f407xx_matlab.h']]], - ['can_5ftsr_5frqcp0_5fmsk_3502',['CAN_TSR_RQCP0_Msk',['../group___peripheral___registers___bits___definition.html#ga2d71df41ef791745448cbd0aaaad6e38',1,'stm32f407xx_matlab.h']]], - ['can_5ftsr_5frqcp0_5fpos_3503',['CAN_TSR_RQCP0_Pos',['../group___peripheral___registers___bits___definition.html#gab31d05fd93767905fa9bde4b5d6143d4',1,'stm32f407xx_matlab.h']]], - ['can_5ftsr_5frqcp1_3504',['CAN_TSR_RQCP1',['../group___peripheral___registers___bits___definition.html#gabd3118dec59c3a45d2f262b090699538',1,'stm32f407xx_matlab.h']]], - ['can_5ftsr_5frqcp1_5fmsk_3505',['CAN_TSR_RQCP1_Msk',['../group___peripheral___registers___bits___definition.html#ga27fdee112d3e6e2b5f6bad6c9d95cb2b',1,'stm32f407xx_matlab.h']]], - ['can_5ftsr_5frqcp1_5fpos_3506',['CAN_TSR_RQCP1_Pos',['../group___peripheral___registers___bits___definition.html#gabd31c6bc75f595b504cc521280752259',1,'stm32f407xx_matlab.h']]], - ['can_5ftsr_5frqcp2_3507',['CAN_TSR_RQCP2',['../group___peripheral___registers___bits___definition.html#ga3cf9e83cec96164f1dadf4e43411ebf0',1,'stm32f407xx_matlab.h']]], - ['can_5ftsr_5frqcp2_5fmsk_3508',['CAN_TSR_RQCP2_Msk',['../group___peripheral___registers___bits___definition.html#ga8137af39f29d789c1794527149da1e70',1,'stm32f407xx_matlab.h']]], - ['can_5ftsr_5frqcp2_5fpos_3509',['CAN_TSR_RQCP2_Pos',['../group___peripheral___registers___bits___definition.html#gac32ff69b06375749e0a00c17c010f1fe',1,'stm32f407xx_matlab.h']]], - ['can_5ftsr_5fterr0_3510',['CAN_TSR_TERR0',['../group___peripheral___registers___bits___definition.html#ga805d2dab5b1d4618492b1cf2a3f5e1e0',1,'stm32f407xx_matlab.h']]], - ['can_5ftsr_5fterr0_5fmsk_3511',['CAN_TSR_TERR0_Msk',['../group___peripheral___registers___bits___definition.html#ga58999cde45dd10f2f351be5cc8ec1a8b',1,'stm32f407xx_matlab.h']]], - ['can_5ftsr_5fterr0_5fpos_3512',['CAN_TSR_TERR0_Pos',['../group___peripheral___registers___bits___definition.html#ga52966440e5d87a89726c19d62645a27c',1,'stm32f407xx_matlab.h']]], - ['can_5ftsr_5fterr1_3513',['CAN_TSR_TERR1',['../group___peripheral___registers___bits___definition.html#ga9b01eca562bdb60e5416840fca47fff6',1,'stm32f407xx_matlab.h']]], - ['can_5ftsr_5fterr1_5fmsk_3514',['CAN_TSR_TERR1_Msk',['../group___peripheral___registers___bits___definition.html#ga5cd5d4653c34defa63b29c42292358dd',1,'stm32f407xx_matlab.h']]], - ['can_5ftsr_5fterr1_5fpos_3515',['CAN_TSR_TERR1_Pos',['../group___peripheral___registers___bits___definition.html#ga0c91415cb60af76367c9c03ddb9d1791',1,'stm32f407xx_matlab.h']]], - ['can_5ftsr_5fterr2_3516',['CAN_TSR_TERR2',['../group___peripheral___registers___bits___definition.html#ga26a85626eb26bf99413ba80c676d0af8',1,'stm32f407xx_matlab.h']]], - ['can_5ftsr_5fterr2_5fmsk_3517',['CAN_TSR_TERR2_Msk',['../group___peripheral___registers___bits___definition.html#gabd1cf1551625e3972c4942983a394acc',1,'stm32f407xx_matlab.h']]], - ['can_5ftsr_5fterr2_5fpos_3518',['CAN_TSR_TERR2_Pos',['../group___peripheral___registers___bits___definition.html#ga99b204977a683ed30b391720352e3260',1,'stm32f407xx_matlab.h']]], - ['can_5ftsr_5ftme_3519',['CAN_TSR_TME',['../group___peripheral___registers___bits___definition.html#ga61ab11e97b42c5210109516e30af9b05',1,'stm32f407xx_matlab.h']]], - ['can_5ftsr_5ftme0_3520',['CAN_TSR_TME0',['../group___peripheral___registers___bits___definition.html#gad7500e491fe82e67ed5d40759e8a50f0',1,'stm32f407xx_matlab.h']]], - ['can_5ftsr_5ftme0_5fmsk_3521',['CAN_TSR_TME0_Msk',['../group___peripheral___registers___bits___definition.html#ga440056199033e966155a795be606acdc',1,'stm32f407xx_matlab.h']]], - ['can_5ftsr_5ftme0_5fpos_3522',['CAN_TSR_TME0_Pos',['../group___peripheral___registers___bits___definition.html#ga37b566e4628d2f032e393c1b86748f2c',1,'stm32f407xx_matlab.h']]], - ['can_5ftsr_5ftme1_3523',['CAN_TSR_TME1',['../group___peripheral___registers___bits___definition.html#ga5ba2b51def4b1683fd050e43045306ea',1,'stm32f407xx_matlab.h']]], - ['can_5ftsr_5ftme1_5fmsk_3524',['CAN_TSR_TME1_Msk',['../group___peripheral___registers___bits___definition.html#ga39fa95bef47ce6b3631b924d25556454',1,'stm32f407xx_matlab.h']]], - ['can_5ftsr_5ftme1_5fpos_3525',['CAN_TSR_TME1_Pos',['../group___peripheral___registers___bits___definition.html#gad799e75ed3dad61e73e34781df0f87f2',1,'stm32f407xx_matlab.h']]], - ['can_5ftsr_5ftme2_3526',['CAN_TSR_TME2',['../group___peripheral___registers___bits___definition.html#gaf6523fac51d3aed2e36de4c2f07c2a21',1,'stm32f407xx_matlab.h']]], - ['can_5ftsr_5ftme2_5fmsk_3527',['CAN_TSR_TME2_Msk',['../group___peripheral___registers___bits___definition.html#ga4977ccde238489d3291b2fe91434c713',1,'stm32f407xx_matlab.h']]], - ['can_5ftsr_5ftme2_5fpos_3528',['CAN_TSR_TME2_Pos',['../group___peripheral___registers___bits___definition.html#ga1884d523a48ffedf27bb137b34ac6c78',1,'stm32f407xx_matlab.h']]], - ['can_5ftsr_5ftme_5fmsk_3529',['CAN_TSR_TME_Msk',['../group___peripheral___registers___bits___definition.html#ga635aef2e8090ae256c1251a3a1736965',1,'stm32f407xx_matlab.h']]], - ['can_5ftsr_5ftme_5fpos_3530',['CAN_TSR_TME_Pos',['../group___peripheral___registers___bits___definition.html#ga4348cbdeed004189582a35db2ff12d74',1,'stm32f407xx_matlab.h']]], - ['can_5ftsr_5ftxok0_3531',['CAN_TSR_TXOK0',['../group___peripheral___registers___bits___definition.html#gaacedb237b31d29aef7f38475e9a6b297',1,'stm32f407xx_matlab.h']]], - ['can_5ftsr_5ftxok0_5fmsk_3532',['CAN_TSR_TXOK0_Msk',['../group___peripheral___registers___bits___definition.html#ga13bd0e217ec398f9ac7c605b03eaa566',1,'stm32f407xx_matlab.h']]], - ['can_5ftsr_5ftxok0_5fpos_3533',['CAN_TSR_TXOK0_Pos',['../group___peripheral___registers___bits___definition.html#ga83553d6d8a8baa6d29b9df2e97689281',1,'stm32f407xx_matlab.h']]], - ['can_5ftsr_5ftxok1_3534',['CAN_TSR_TXOK1',['../group___peripheral___registers___bits___definition.html#gaea918e510c5471b1ac797350b7950151',1,'stm32f407xx_matlab.h']]], - ['can_5ftsr_5ftxok1_5fmsk_3535',['CAN_TSR_TXOK1_Msk',['../group___peripheral___registers___bits___definition.html#ga5d08d43b83ebfa8f93c1ac842ccb1e31',1,'stm32f407xx_matlab.h']]], - ['can_5ftsr_5ftxok1_5fpos_3536',['CAN_TSR_TXOK1_Pos',['../group___peripheral___registers___bits___definition.html#gaabf7c2bb1371409780b6aa677d30505d',1,'stm32f407xx_matlab.h']]], - ['can_5ftsr_5ftxok2_3537',['CAN_TSR_TXOK2',['../group___peripheral___registers___bits___definition.html#ga782c591bb204d751b470dd53a37d240e',1,'stm32f407xx_matlab.h']]], - ['can_5ftsr_5ftxok2_5fmsk_3538',['CAN_TSR_TXOK2_Msk',['../group___peripheral___registers___bits___definition.html#gab26c50058879d92619cbc4bef2e9d492',1,'stm32f407xx_matlab.h']]], - ['can_5ftsr_5ftxok2_5fpos_3539',['CAN_TSR_TXOK2_Pos',['../group___peripheral___registers___bits___definition.html#ga5c1c09375222011c0dba1bdb1cf56fd2',1,'stm32f407xx_matlab.h']]], - ['can_5ftxmailbox_5ftypedef_3540',['CAN_TxMailBox_TypeDef',['../struct_c_a_n___tx_mail_box___type_def.html',1,'']]], - ['can_5ftypedef_3541',['CAN_TypeDef',['../struct_c_a_n___type_def.html',1,'']]], - ['cc_5fpwm_5fch1_5fsimulation_3542',['CC_PWM_Ch1_Simulation',['../group___t_i_m___s_i_m_u_l_a_t_o_r.html#ga609dd2da1a15ffb80256e85942ed2671',1,'CC_PWM_Ch1_Simulation(TIM_TypeDef *TIMx, struct TIM_Sim *TIMS): stm32f4xx_matlab_tim.c'],['../group___t_i_m___s_i_m_u_l_a_t_o_r.html#ga609dd2da1a15ffb80256e85942ed2671',1,'CC_PWM_Ch1_Simulation(TIM_TypeDef *TIMx, struct TIM_Sim *TIMS): stm32f4xx_matlab_tim.c']]], - ['cc_5fpwm_5fch2_5fsimulation_3543',['CC_PWM_Ch2_Simulation',['../group___t_i_m___s_i_m_u_l_a_t_o_r.html#gaef90da33b410dcd77d9cdb58363d729c',1,'CC_PWM_Ch2_Simulation(TIM_TypeDef *TIMx, struct TIM_Sim *TIMS): stm32f4xx_matlab_tim.c'],['../group___t_i_m___s_i_m_u_l_a_t_o_r.html#gaef90da33b410dcd77d9cdb58363d729c',1,'CC_PWM_Ch2_Simulation(TIM_TypeDef *TIMx, struct TIM_Sim *TIMS): stm32f4xx_matlab_tim.c']]], - ['cc_5fpwm_5fch3_5fsimulation_3544',['CC_PWM_Ch3_Simulation',['../group___t_i_m___s_i_m_u_l_a_t_o_r.html#ga99db7a05808ca9b5aa12df01745ed2ef',1,'CC_PWM_Ch3_Simulation(TIM_TypeDef *TIMx, struct TIM_Sim *TIMS): stm32f4xx_matlab_tim.c'],['../group___t_i_m___s_i_m_u_l_a_t_o_r.html#ga99db7a05808ca9b5aa12df01745ed2ef',1,'CC_PWM_Ch3_Simulation(TIM_TypeDef *TIMx, struct TIM_Sim *TIMS): stm32f4xx_matlab_tim.c']]], - ['cc_5fpwm_5fch4_5fsimulation_3545',['CC_PWM_Ch4_Simulation',['../group___t_i_m___s_i_m_u_l_a_t_o_r.html#gad51e3fbb47f5768c33876ad803fbef20',1,'CC_PWM_Ch4_Simulation(TIM_TypeDef *TIMx, struct TIM_Sim *TIMS): stm32f4xx_matlab_tim.c'],['../group___t_i_m___s_i_m_u_l_a_t_o_r.html#gad51e3fbb47f5768c33876ad803fbef20',1,'CC_PWM_Ch4_Simulation(TIM_TypeDef *TIMx, struct TIM_Sim *TIMS): stm32f4xx_matlab_tim.c']]], - ['ccer_3546',['CCER',['../group___c_m_s_i_s___device.html#ga098110becfef10e1fd1b6a4f874da496',1,'TIM_TypeDef']]], - ['ccmdataram_5fbase_3547',['CCMDATARAM_BASE',['../group___c_m_s_i_s___device.html#gacd6db2394f2b493a873059464d5b0e18',1,'_memory::CCMDATARAM_BASE'],['../group___peripheral__memory__map.html#gabea1f1810ebeac402164b42ab54bcdf9',1,'CCMDATARAM_BASE: stm32f407xx_matlab.h']]], - ['ccmdataram_5fbase_5fshift_3548',['CCMDATARAM_BASE_SHIFT',['../group___peripheral__memory__map.html#ga2d06a3566d8983055baf9e883e0198ef',1,'stm32f407xx_matlab.h']]], - ['ccmdataram_5fend_3549',['CCMDATARAM_END',['../group___peripheral__memory__map.html#ga9fbe263946209e6f09faf93512bd2f9a',1,'stm32f407xx_matlab.h']]], - ['ccmdataram_5fend_5fshift_3550',['CCMDATARAM_END_SHIFT',['../group___peripheral__memory__map.html#ga86d258a24d1cef85ee0333fcaf6398a8',1,'stm32f407xx_matlab.h']]], - ['ccmdataram_5fsize_3551',['CCMDATARAM_SIZE',['../group___peripheral__memory__map.html#ga71542ecbf91e5a2e4e7657ebf4743bb0',1,'stm32f407xx_matlab.h']]], - ['ccmr1_3552',['CCMR1',['../group___c_m_s_i_s___device.html#gadb72f64492a75e780dd2294075c70fed',1,'TIM_TypeDef']]], - ['ccmr2_3553',['CCMR2',['../group___c_m_s_i_s___device.html#ga091452256c9a16c33d891f4d32b395bf',1,'TIM_TypeDef']]], - ['ccr_3554',['CCR',['../group___c_m_s_i_s__core___debug_functions.html#gad68b5c1f2d9845ef4247cf2d9b041336',1,'SCB_Type::CCR'],['../group___c_m_s_i_s___device.html#ga5e1322e27c40bf91d172f9673f205c97',1,'ADC_Common_TypeDef::CCR'],['../group___c_m_s_i_s___device.html#ga5e1322e27c40bf91d172f9673f205c97',1,'I2C_TypeDef::CCR']]], - ['ccr1_3555',['CCR1',['../group___c_m_s_i_s___device.html#gadab1e24ef769bbcb3e3769feae192ffb',1,'TIM_TypeDef']]], - ['ccr2_3556',['CCR2',['../group___c_m_s_i_s___device.html#gab90aa584f07eeeac364a67f5e05faa93',1,'TIM_TypeDef']]], - ['ccr3_3557',['CCR3',['../group___c_m_s_i_s___device.html#ga27a478cc47a3dff478555ccb985b06a2',1,'TIM_TypeDef']]], - ['ccr4_3558',['CCR4',['../group___c_m_s_i_s___device.html#ga85fdb75569bd7ea26fa48544786535be',1,'TIM_TypeDef']]], - ['cdr_3559',['CDR',['../group___c_m_s_i_s___device.html#ga760f86a1a18dffffda54fc15a977979f',1,'ADC_Common_TypeDef']]], - ['cfgr_3560',['CFGR',['../group___c_m_s_i_s___device.html#ga26f1e746ccbf9c9f67e7c60e61085ec1',1,'RCC_TypeDef']]], - ['cfr_3561',['CFR',['../group___c_m_s_i_s___device.html#gac011ddcfe531f8e16787ea851c1f3667',1,'WWDG_TypeDef']]], - ['cfsr_3562',['CFSR',['../group___c_m_s_i_s__core___debug_functions.html#ga0f9e27357254e6e953a94f95bda040b1',1,'SCB_Type']]], - ['channels_3563',['Channels',['../struct_t_i_m___sim.html#a41f21d0d1bfe0fb45e3f643ece9cdcee',1,'TIM_Sim']]], - ['channels_5fsim_3564',['Channels_Sim',['../struct_channels___sim.html',1,'']]], - ['channels_5fsimulation_3565',['Channels_Simulation',['../group___t_i_m___s_i_m_u_l_a_t_o_r.html#ga63dc3b53fe4b165b4c70e4d600258d50',1,'Channels_Simulation(TIM_TypeDef *TIMx, struct TIM_Sim *TIMS): stm32f4xx_matlab_tim.c'],['../group___t_i_m___s_i_m_u_l_a_t_o_r.html#ga63dc3b53fe4b165b4c70e4d600258d50',1,'Channels_Simulation(TIM_TypeDef *TIMx, struct TIM_Sim *TIMS): stm32f4xx_matlab_tim.c']]], - ['check_5foc1_5fgpio_5foutput_3566',['Check_OC1_GPIO_Output',['../group___t_i_m___s_i_m_u_l_a_t_o_r.html#ga819ef3dc9ad489178802ed1dcb0e6b41',1,'stm32f4xx_matlab_tim.h']]], - ['check_5foc2_5fgpio_5foutput_3567',['Check_OC2_GPIO_Output',['../group___t_i_m___s_i_m_u_l_a_t_o_r.html#gab05cf435dbdfc0a827fc6cf093d27694',1,'stm32f4xx_matlab_tim.h']]], - ['check_5foc3_5fgpio_5foutput_3568',['Check_OC3_GPIO_Output',['../group___t_i_m___s_i_m_u_l_a_t_o_r.html#ga1303da0a61cb89d0952378d46b1be2a3',1,'stm32f4xx_matlab_tim.h']]], - ['check_5foc4_5fgpio_5foutput_3569',['Check_OC4_GPIO_Output',['../group___t_i_m___s_i_m_u_l_a_t_o_r.html#gadd3fec5a120bcd59e8396435da2cb639',1,'stm32f4xx_matlab_tim.h']]], - ['check_5focx_5fgpio_5foutput_3570',['Check_OCx_GPIO_Output',['../group___t_i_m___s_i_m_u_l_a_t_o_r.html#ga332e5c16b48c0bc5a7c1f978442ef49f',1,'stm32f4xx_matlab_tim.h']]], - ['cid_3571',['CID',['../group___c_m_s_i_s___device.html#ga6eefd74b3acdc3c1a88b833fcf5e8d81',1,'USB_OTG_GlobalTypeDef']]], - ['cid0_3572',['CID0',['../group___c_m_s_i_s__core___debug_functions.html#ga26bbad5d9e0f1d302611d52373aef839',1,'ITM_Type']]], - ['cid1_3573',['CID1',['../group___c_m_s_i_s__core___debug_functions.html#ga4e60a608afd6433ecd943d95e417b80b',1,'ITM_Type']]], - ['cid2_3574',['CID2',['../group___c_m_s_i_s__core___debug_functions.html#gad98950702e55d1851e91b22de07b11aa',1,'ITM_Type']]], - ['cid3_3575',['CID3',['../group___c_m_s_i_s__core___debug_functions.html#gab9af64f413bf6f67e2a8044481292f67',1,'ITM_Type']]], - ['cir_3576',['CIR',['../group___c_m_s_i_s___device.html#ga907d8154c80b7e385478943f90b17a3b',1,'RCC_TypeDef']]], - ['claimclr_3577',['CLAIMCLR',['../group___c_m_s_i_s__core___debug_functions.html#ga1f74caab7b0a7afa848c63ce8ebc6a6f',1,'TPI_Type']]], - ['claimset_3578',['CLAIMSET',['../group___c_m_s_i_s__core___debug_functions.html#ga974d17c9a0b0b1b894e9707d158b0fbe',1,'TPI_Type']]], - ['clear_5fbit_3579',['CLEAR_BIT',['../group___exported__macro.html#ga133aae6fc0d41bffab39ab223a7001de',1,'stm32f4xx.h']]], - ['clear_5fflag_5fif_5fits_5fexpected_3580',['Clear_Flag_If_Its_Expected',['../group___r_c_c___s_i_m_u_l_a_t_o_r.html#ga5dc1d225a53e67cc732ca9069ffb1f0d',1,'stm32f4xx_matlab_rcc.h']]], - ['clear_5freg_3581',['CLEAR_REG',['../group___exported__macro.html#ga1378fbdda39f40b85420df55f41460ef',1,'stm32f4xx.h']]], - ['clkcr_3582',['CLKCR',['../group___c_m_s_i_s___device.html#gaa94197378e20fc739d269be49d9c5d40',1,'SDIO_TypeDef']]], - ['cmd_3583',['CMD',['../group___c_m_s_i_s___device.html#gadcf812cbe5147d300507d59d4a55935d',1,'SDIO_TypeDef']]], - ['cmpcr_3584',['CMPCR',['../group___c_m_s_i_s___device.html#ga08ddbac546fa9928256654d31255c8c3',1,'SYSCFG_TypeDef']]], - ['cmsis_3585',['CMSIS',['../group___c_m_s_i_s.html',1,'']]], - ['cmsis_20global_20defines_3586',['CMSIS Global Defines',['../group___c_m_s_i_s__glob__defs.html',1,'']]], - ['cmsis_5fdevice_3587',['CMSIS_Device',['../group___c_m_s_i_s___device.html',1,'']]], - ['cnt_3588',['CNT',['../group___c_m_s_i_s___device.html#ga6095a27d764d06750fc0d642e08f8b2a',1,'TIM_TypeDef']]], - ['comp0_3589',['COMP0',['../group___c_m_s_i_s__core___debug_functions.html#ga5d0c69187f8abc99ecbde49431cf0050',1,'DWT_Type']]], - ['comp1_3590',['COMP1',['../group___c_m_s_i_s__core___debug_functions.html#gaf9126caaf63b99d6df5d1e040c96e2ab',1,'DWT_Type']]], - ['comp2_3591',['COMP2',['../group___c_m_s_i_s__core___debug_functions.html#gaeeb1e36001c60a167399683280d6ec39',1,'DWT_Type']]], - ['comp3_3592',['COMP3',['../group___c_m_s_i_s__core___debug_functions.html#ga20b0b62a3576ee88db4a7c065cd988ac',1,'DWT_Type']]], - ['configuration_5fsection_5ffor_5fcmsis_3593',['Configuration_section_for_CMSIS',['../group___configuration__section__for___c_m_s_i_s.html',1,'']]], - ['control_20block_20scb_3594',['System Control Block (SCB)',['../group___c_m_s_i_s___s_c_b.html',1,'']]], - ['control_20registers_3595',['Status and Control Registers',['../group___c_m_s_i_s___c_o_r_e.html',1,'']]], - ['control_5ffpca_5fmsk_3596',['CONTROL_FPCA_Msk',['../group___c_m_s_i_s___c_o_r_e.html#gad20bb0212b2e1864f24af38d93587c79',1,'core_cm4_matlab.h']]], - ['control_5ffpca_5fpos_3597',['CONTROL_FPCA_Pos',['../group___c_m_s_i_s___c_o_r_e.html#gac7018b59b07134c5363b33eb94918a58',1,'core_cm4_matlab.h']]], - ['control_5fnpriv_5fmsk_3598',['CONTROL_nPRIV_Msk',['../group___c_m_s_i_s___c_o_r_e.html#gaef3b20d77acb213338f89ce5e7bc36b0',1,'core_cm4_matlab.h']]], - ['control_5fnpriv_5fpos_3599',['CONTROL_nPRIV_Pos',['../group___c_m_s_i_s___c_o_r_e.html#ga51b95bc03ec0d815b459bde0b14a5908',1,'core_cm4_matlab.h']]], - ['control_5fspsel_5fmsk_3600',['CONTROL_SPSEL_Msk',['../group___c_m_s_i_s___c_o_r_e.html#ga70b29840969b06909da21369b0b05b53',1,'core_cm4_matlab.h']]], - ['control_5fspsel_5fpos_3601',['CONTROL_SPSEL_Pos',['../group___c_m_s_i_s___c_o_r_e.html#ga07eafc53e609895342c6a530e9d01310',1,'core_cm4_matlab.h']]], - ['control_5ftype_3602',['CONTROL_Type',['../union_c_o_n_t_r_o_l___type.html',1,'']]], - ['controller_20nvic_3603',['Nested Vectored Interrupt Controller (NVIC)',['../group___c_m_s_i_s___n_v_i_c.html',1,'']]], - ['controls_20not_20in_20scb_20scnscb_3604',['System Controls not in SCB (SCnSCB)',['../group___c_m_s_i_s___s_cn_s_c_b.html',1,'']]], - ['core_20debug_20registers_20coredebug_3605',['Core Debug Registers (CoreDebug)',['../group___c_m_s_i_s___core_debug.html',1,'']]], - ['core_20definitions_3606',['Core Definitions',['../group___c_m_s_i_s__core__base.html',1,'']]], - ['core_20register_20bit_20field_20macros_3607',['Core register bit field macros',['../group___c_m_s_i_s__core__bitfield.html',1,'']]], - ['core_5fcm4_5fmatlab_2eh_3608',['core_cm4_matlab.h',['../core__cm4__matlab_8h.html',1,'']]], - ['coredebug_3609',['Core Debug Registers (CoreDebug)',['../group___c_m_s_i_s___core_debug.html',1,'']]], - ['coredebug_5fbase_3610',['CoreDebug_BASE',['../group___c_m_s_i_s__core__base.html#ga680604dbcda9e9b31a1639fcffe5230b',1,'core_cm4_matlab.h']]], - ['coredebug_5fbase_5fshift_3611',['CoreDebug_BASE_SHIFT',['../group___c_m_s_i_s__core__base.html#ga3b760f7bd0c5082d2d0db746f778c329',1,'core_cm4_matlab.h']]], - ['coredebug_5fdcrsr_5fregsel_5fmsk_3612',['CoreDebug_DCRSR_REGSEL_Msk',['../group___c_m_s_i_s___core_debug.html#ga17cafbd72b55030219ce5609baa7c01d',1,'core_cm4_matlab.h']]], - ['coredebug_5fdcrsr_5fregsel_5fpos_3613',['CoreDebug_DCRSR_REGSEL_Pos',['../group___c_m_s_i_s___core_debug.html#ga52182c8a9f63a52470244c0bc2064f7b',1,'core_cm4_matlab.h']]], - ['coredebug_5fdcrsr_5fregwnr_5fmsk_3614',['CoreDebug_DCRSR_REGWnR_Msk',['../group___c_m_s_i_s___core_debug.html#ga1eef4992d8f84bc6c0dffed1c87f90a5',1,'core_cm4_matlab.h']]], - ['coredebug_5fdcrsr_5fregwnr_5fpos_3615',['CoreDebug_DCRSR_REGWnR_Pos',['../group___c_m_s_i_s___core_debug.html#ga51e75942fc0614bc9bb2c0e96fcdda9a',1,'core_cm4_matlab.h']]], - ['coredebug_5fdemcr_5fmon_5fen_5fmsk_3616',['CoreDebug_DEMCR_MON_EN_Msk',['../group___c_m_s_i_s___core_debug.html#gac2b46b9b65bf8d23027f255fc9641977',1,'core_cm4_matlab.h']]], - ['coredebug_5fdemcr_5fmon_5fen_5fpos_3617',['CoreDebug_DEMCR_MON_EN_Pos',['../group___c_m_s_i_s___core_debug.html#ga802829678f6871863ae9ecf60a10425c',1,'core_cm4_matlab.h']]], - ['coredebug_5fdemcr_5fmon_5fpend_5fmsk_3618',['CoreDebug_DEMCR_MON_PEND_Msk',['../group___c_m_s_i_s___core_debug.html#ga68ec55930269fab78e733dcfa32392f8',1,'core_cm4_matlab.h']]], - ['coredebug_5fdemcr_5fmon_5fpend_5fpos_3619',['CoreDebug_DEMCR_MON_PEND_Pos',['../group___c_m_s_i_s___core_debug.html#ga1e2f706a59e0d8131279af1c7e152f8d',1,'core_cm4_matlab.h']]], - ['coredebug_5fdemcr_5fmon_5freq_5fmsk_3620',['CoreDebug_DEMCR_MON_REQ_Msk',['../group___c_m_s_i_s___core_debug.html#gae6384cbe8045051186d13ef9cdeace95',1,'core_cm4_matlab.h']]], - ['coredebug_5fdemcr_5fmon_5freq_5fpos_3621',['CoreDebug_DEMCR_MON_REQ_Pos',['../group___c_m_s_i_s___core_debug.html#ga341020a3b7450416d72544eaf8e57a64',1,'core_cm4_matlab.h']]], - ['coredebug_5fdemcr_5fmon_5fstep_5fmsk_3622',['CoreDebug_DEMCR_MON_STEP_Msk',['../group___c_m_s_i_s___core_debug.html#ga2ded814556de96fc369de7ae9a7ceb98',1,'core_cm4_matlab.h']]], - ['coredebug_5fdemcr_5fmon_5fstep_5fpos_3623',['CoreDebug_DEMCR_MON_STEP_Pos',['../group___c_m_s_i_s___core_debug.html#ga9ae10710684e14a1a534e785ef390e1b',1,'core_cm4_matlab.h']]], - ['coredebug_5fdemcr_5ftrcena_5fmsk_3624',['CoreDebug_DEMCR_TRCENA_Msk',['../group___c_m_s_i_s___core_debug.html#ga5e99652c1df93b441257389f49407834',1,'core_cm4_matlab.h']]], - ['coredebug_5fdemcr_5ftrcena_5fpos_3625',['CoreDebug_DEMCR_TRCENA_Pos',['../group___c_m_s_i_s___core_debug.html#ga6ff2102b98f86540224819a1b767ba39',1,'core_cm4_matlab.h']]], - ['coredebug_5fdemcr_5fvc_5fbuserr_5fmsk_3626',['CoreDebug_DEMCR_VC_BUSERR_Msk',['../group___c_m_s_i_s___core_debug.html#ga9d29546aefe3ca8662a7fe48dd4a5b2b',1,'core_cm4_matlab.h']]], - ['coredebug_5fdemcr_5fvc_5fbuserr_5fpos_3627',['CoreDebug_DEMCR_VC_BUSERR_Pos',['../group___c_m_s_i_s___core_debug.html#gab8e3d8f0f9590a51bbf10f6da3ad6933',1,'core_cm4_matlab.h']]], - ['coredebug_5fdemcr_5fvc_5fchkerr_5fmsk_3628',['CoreDebug_DEMCR_VC_CHKERR_Msk',['../group___c_m_s_i_s___core_debug.html#ga2f98b461d19746ab2febfddebb73da6f',1,'core_cm4_matlab.h']]], - ['coredebug_5fdemcr_5fvc_5fchkerr_5fpos_3629',['CoreDebug_DEMCR_VC_CHKERR_Pos',['../group___c_m_s_i_s___core_debug.html#ga10fc7c53bca904c128bc8e1a03072d50',1,'core_cm4_matlab.h']]], - ['coredebug_5fdemcr_5fvc_5fcorereset_5fmsk_3630',['CoreDebug_DEMCR_VC_CORERESET_Msk',['../group___c_m_s_i_s___core_debug.html#ga906476e53c1e1487c30f3a1181df9e30',1,'core_cm4_matlab.h']]], - ['coredebug_5fdemcr_5fvc_5fcorereset_5fpos_3631',['CoreDebug_DEMCR_VC_CORERESET_Pos',['../group___c_m_s_i_s___core_debug.html#ga9fcf09666f7063a7303117aa32a85d5a',1,'core_cm4_matlab.h']]], - ['coredebug_5fdemcr_5fvc_5fharderr_5fmsk_3632',['CoreDebug_DEMCR_VC_HARDERR_Msk',['../group___c_m_s_i_s___core_debug.html#ga803fc98c5bb85f10f0347b23794847d1',1,'core_cm4_matlab.h']]], - ['coredebug_5fdemcr_5fvc_5fharderr_5fpos_3633',['CoreDebug_DEMCR_VC_HARDERR_Pos',['../group___c_m_s_i_s___core_debug.html#gaed9f42053031a9a30cd8054623304c0a',1,'core_cm4_matlab.h']]], - ['coredebug_5fdemcr_5fvc_5finterr_5fmsk_3634',['CoreDebug_DEMCR_VC_INTERR_Msk',['../group___c_m_s_i_s___core_debug.html#gad6815d8e3df302d2f0ff2c2c734ed29a',1,'core_cm4_matlab.h']]], - ['coredebug_5fdemcr_5fvc_5finterr_5fpos_3635',['CoreDebug_DEMCR_VC_INTERR_Pos',['../group___c_m_s_i_s___core_debug.html#ga22079a6e436f23b90308be97e19cf07e',1,'core_cm4_matlab.h']]], - ['coredebug_5fdemcr_5fvc_5fmmerr_5fmsk_3636',['CoreDebug_DEMCR_VC_MMERR_Msk',['../group___c_m_s_i_s___core_debug.html#gad420a9b60620584faaca6289e83d3a87',1,'core_cm4_matlab.h']]], - ['coredebug_5fdemcr_5fvc_5fmmerr_5fpos_3637',['CoreDebug_DEMCR_VC_MMERR_Pos',['../group___c_m_s_i_s___core_debug.html#ga444454f7c7748e76cd76c3809c887c41',1,'core_cm4_matlab.h']]], - ['coredebug_5fdemcr_5fvc_5fnocperr_5fmsk_3638',['CoreDebug_DEMCR_VC_NOCPERR_Msk',['../group___c_m_s_i_s___core_debug.html#ga03ee58b1b02fdbf21612809034562f1c',1,'core_cm4_matlab.h']]], - ['coredebug_5fdemcr_5fvc_5fnocperr_5fpos_3639',['CoreDebug_DEMCR_VC_NOCPERR_Pos',['../group___c_m_s_i_s___core_debug.html#gac9d13eb2add61f610d5ced1f7ad2adf8',1,'core_cm4_matlab.h']]], - ['coredebug_5fdemcr_5fvc_5fstaterr_5fmsk_3640',['CoreDebug_DEMCR_VC_STATERR_Msk',['../group___c_m_s_i_s___core_debug.html#gaa38b947d77672c48bba1280c0a642e19',1,'core_cm4_matlab.h']]], - ['coredebug_5fdemcr_5fvc_5fstaterr_5fpos_3641',['CoreDebug_DEMCR_VC_STATERR_Pos',['../group___c_m_s_i_s___core_debug.html#ga16f0d3d2ce1e1e8cd762d938ac56c4ac',1,'core_cm4_matlab.h']]], - ['coredebug_5fdhcsr_5fc_5fdebugen_5fmsk_3642',['CoreDebug_DHCSR_C_DEBUGEN_Msk',['../group___c_m_s_i_s___core_debug.html#gab815c741a4fc2a61988cd2fb7594210b',1,'core_cm4_matlab.h']]], - ['coredebug_5fdhcsr_5fc_5fdebugen_5fpos_3643',['CoreDebug_DHCSR_C_DEBUGEN_Pos',['../group___c_m_s_i_s___core_debug.html#gab557abb5b172b74d2cf44efb9d824e4e',1,'core_cm4_matlab.h']]], - ['coredebug_5fdhcsr_5fc_5fhalt_5fmsk_3644',['CoreDebug_DHCSR_C_HALT_Msk',['../group___c_m_s_i_s___core_debug.html#ga1d905a3aa594eb2e8bb78bcc4da05b3f',1,'core_cm4_matlab.h']]], - ['coredebug_5fdhcsr_5fc_5fhalt_5fpos_3645',['CoreDebug_DHCSR_C_HALT_Pos',['../group___c_m_s_i_s___core_debug.html#gaddf1d43f8857e4efc3dc4e6b15509692',1,'core_cm4_matlab.h']]], - ['coredebug_5fdhcsr_5fc_5fmaskints_5fmsk_3646',['CoreDebug_DHCSR_C_MASKINTS_Msk',['../group___c_m_s_i_s___core_debug.html#ga77fe1ef3c4a729c1c82fb62a94a51c31',1,'core_cm4_matlab.h']]], - ['coredebug_5fdhcsr_5fc_5fmaskints_5fpos_3647',['CoreDebug_DHCSR_C_MASKINTS_Pos',['../group___c_m_s_i_s___core_debug.html#ga0d2907400eb948a4ea3886ca083ec8e3',1,'core_cm4_matlab.h']]], - ['coredebug_5fdhcsr_5fc_5fsnapstall_5fmsk_3648',['CoreDebug_DHCSR_C_SNAPSTALL_Msk',['../group___c_m_s_i_s___core_debug.html#ga53aa99b2e39a67622f3b9973e079c2b4',1,'core_cm4_matlab.h']]], - ['coredebug_5fdhcsr_5fc_5fsnapstall_5fpos_3649',['CoreDebug_DHCSR_C_SNAPSTALL_Pos',['../group___c_m_s_i_s___core_debug.html#ga85747214e2656df6b05ec72e4d22bd6d',1,'core_cm4_matlab.h']]], - ['coredebug_5fdhcsr_5fc_5fstep_5fmsk_3650',['CoreDebug_DHCSR_C_STEP_Msk',['../group___c_m_s_i_s___core_debug.html#gae6bda72fbd32cc5734ff3542170dc00d',1,'core_cm4_matlab.h']]], - ['coredebug_5fdhcsr_5fc_5fstep_5fpos_3651',['CoreDebug_DHCSR_C_STEP_Pos',['../group___c_m_s_i_s___core_debug.html#gae1fc39e80de54c0339cbb1b298a9f0f9',1,'core_cm4_matlab.h']]], - ['coredebug_5fdhcsr_5fdbgkey_5fmsk_3652',['CoreDebug_DHCSR_DBGKEY_Msk',['../group___c_m_s_i_s___core_debug.html#ga1ce997cee15edaafe4aed77751816ffc',1,'core_cm4_matlab.h']]], - ['coredebug_5fdhcsr_5fdbgkey_5fpos_3653',['CoreDebug_DHCSR_DBGKEY_Pos',['../group___c_m_s_i_s___core_debug.html#gac91280edd0ce932665cf75a23d11d842',1,'core_cm4_matlab.h']]], - ['coredebug_5fdhcsr_5fs_5fhalt_5fmsk_3654',['CoreDebug_DHCSR_S_HALT_Msk',['../group___c_m_s_i_s___core_debug.html#ga9f881ade3151a73bc5b02b73fe6473ca',1,'core_cm4_matlab.h']]], - ['coredebug_5fdhcsr_5fs_5fhalt_5fpos_3655',['CoreDebug_DHCSR_S_HALT_Pos',['../group___c_m_s_i_s___core_debug.html#ga760a9a0d7f39951dc3f07d01f1f64772',1,'core_cm4_matlab.h']]], - ['coredebug_5fdhcsr_5fs_5flockup_5fmsk_3656',['CoreDebug_DHCSR_S_LOCKUP_Msk',['../group___c_m_s_i_s___core_debug.html#ga7b67e4506d7f464ef5dafd6219739756',1,'core_cm4_matlab.h']]], - ['coredebug_5fdhcsr_5fs_5flockup_5fpos_3657',['CoreDebug_DHCSR_S_LOCKUP_Pos',['../group___c_m_s_i_s___core_debug.html#ga2900dd56a988a4ed27ad664d5642807e',1,'core_cm4_matlab.h']]], - ['coredebug_5fdhcsr_5fs_5fregrdy_5fmsk_3658',['CoreDebug_DHCSR_S_REGRDY_Msk',['../group___c_m_s_i_s___core_debug.html#gac4cd6f3178de48f473d8903e8c847c07',1,'core_cm4_matlab.h']]], - ['coredebug_5fdhcsr_5fs_5fregrdy_5fpos_3659',['CoreDebug_DHCSR_S_REGRDY_Pos',['../group___c_m_s_i_s___core_debug.html#ga20a71871ca8768019c51168c70c3f41d',1,'core_cm4_matlab.h']]], - ['coredebug_5fdhcsr_5fs_5freset_5fst_5fmsk_3660',['CoreDebug_DHCSR_S_RESET_ST_Msk',['../group___c_m_s_i_s___core_debug.html#gac474394bcceb31a8e09566c90b3f8922',1,'core_cm4_matlab.h']]], - ['coredebug_5fdhcsr_5fs_5freset_5fst_5fpos_3661',['CoreDebug_DHCSR_S_RESET_ST_Pos',['../group___c_m_s_i_s___core_debug.html#ga6f934c5427ea057394268e541fa97753',1,'core_cm4_matlab.h']]], - ['coredebug_5fdhcsr_5fs_5fretire_5fst_5fmsk_3662',['CoreDebug_DHCSR_S_RETIRE_ST_Msk',['../group___c_m_s_i_s___core_debug.html#ga89dceb5325f6bcb36a0473d65fbfcfa6',1,'core_cm4_matlab.h']]], - ['coredebug_5fdhcsr_5fs_5fretire_5fst_5fpos_3663',['CoreDebug_DHCSR_S_RETIRE_ST_Pos',['../group___c_m_s_i_s___core_debug.html#ga2328118f8b3574c871a53605eb17e730',1,'core_cm4_matlab.h']]], - ['coredebug_5fdhcsr_5fs_5fsleep_5fmsk_3664',['CoreDebug_DHCSR_S_SLEEP_Msk',['../group___c_m_s_i_s___core_debug.html#ga98d51538e645c2c1a422279cd85a0a25',1,'core_cm4_matlab.h']]], - ['coredebug_5fdhcsr_5fs_5fsleep_5fpos_3665',['CoreDebug_DHCSR_S_SLEEP_Pos',['../group___c_m_s_i_s___core_debug.html#ga349ccea33accc705595624c2d334fbcb',1,'core_cm4_matlab.h']]], - ['coredebug_5ftype_3666',['CoreDebug_Type',['../struct_core_debug___type.html',1,'']]], - ['cortex_5fperiph_5fbase_3667',['CORTEX_PERIPH_BASE',['../group___c_m_s_i_s__core___debug_functions.html#ga33c7ca027b61cba4b327fcad1c1cb7aa',1,'_cortex_memory']]], - ['cpacr_3668',['CPACR',['../group___c_m_s_i_s__core___debug_functions.html#gab8e9dd6ca5f31244ea352ed0c19155d8',1,'SCB_Type']]], - ['cpicnt_3669',['CPICNT',['../group___c_m_s_i_s__core___debug_functions.html#ga29ca657c77928334be08a2e6555be950',1,'DWT_Type']]], - ['cpuid_3670',['CPUID',['../group___c_m_s_i_s__core___debug_functions.html#gadbf8292503748ba6421a523bdee6819d',1,'SCB_Type']]], - ['cr_3671',['CR',['../group___c_m_s_i_s___device.html#gab40c89c59391aaa9d9a8ec011dd0907a',1,'CRC_TypeDef::CR'],['../group___c_m_s_i_s___device.html#gab40c89c59391aaa9d9a8ec011dd0907a',1,'DAC_TypeDef::CR'],['../group___c_m_s_i_s___device.html#gab40c89c59391aaa9d9a8ec011dd0907a',1,'DBGMCU_TypeDef::CR'],['../group___c_m_s_i_s___device.html#gab40c89c59391aaa9d9a8ec011dd0907a',1,'DCMI_TypeDef::CR'],['../group___c_m_s_i_s___device.html#gab40c89c59391aaa9d9a8ec011dd0907a',1,'DMA_Stream_TypeDef::CR'],['../group___c_m_s_i_s___device.html#gab40c89c59391aaa9d9a8ec011dd0907a',1,'FLASH_TypeDef::CR'],['../group___c_m_s_i_s___device.html#gab40c89c59391aaa9d9a8ec011dd0907a',1,'PWR_TypeDef::CR'],['../group___c_m_s_i_s___device.html#gab40c89c59391aaa9d9a8ec011dd0907a',1,'RCC_TypeDef::CR'],['../group___c_m_s_i_s___device.html#gab40c89c59391aaa9d9a8ec011dd0907a',1,'RTC_TypeDef::CR'],['../group___c_m_s_i_s___device.html#gab40c89c59391aaa9d9a8ec011dd0907a',1,'WWDG_TypeDef::CR'],['../group___c_m_s_i_s___device.html#gab40c89c59391aaa9d9a8ec011dd0907a',1,'RNG_TypeDef::CR']]], - ['cr1_3672',['CR1',['../group___c_m_s_i_s___device.html#gab0ec7102960640751d44e92ddac994f0',1,'ADC_TypeDef::CR1'],['../group___c_m_s_i_s___device.html#gab0ec7102960640751d44e92ddac994f0',1,'I2C_TypeDef::CR1'],['../group___c_m_s_i_s___device.html#gab0ec7102960640751d44e92ddac994f0',1,'SPI_TypeDef::CR1'],['../group___c_m_s_i_s___device.html#gab0ec7102960640751d44e92ddac994f0',1,'TIM_TypeDef::CR1'],['../group___c_m_s_i_s___device.html#gab0ec7102960640751d44e92ddac994f0',1,'USART_TypeDef::CR1']]], - ['cr2_3673',['CR2',['../group___c_m_s_i_s___device.html#gafdfa307571967afb1d97943e982b6586',1,'ADC_TypeDef::CR2'],['../group___c_m_s_i_s___device.html#gafdfa307571967afb1d97943e982b6586',1,'I2C_TypeDef::CR2'],['../group___c_m_s_i_s___device.html#gafdfa307571967afb1d97943e982b6586',1,'SPI_TypeDef::CR2'],['../group___c_m_s_i_s___device.html#gafdfa307571967afb1d97943e982b6586',1,'TIM_TypeDef::CR2'],['../group___c_m_s_i_s___device.html#gafdfa307571967afb1d97943e982b6586',1,'USART_TypeDef::CR2']]], - ['cr3_3674',['CR3',['../group___c_m_s_i_s___device.html#gadd5b8e29a64c55dcd65ca4201118e9d1',1,'USART_TypeDef']]], - ['crc_3675',['crc',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga0be4a4f92234a92301b5dea4ef762a83',1,'stm32f4xx_periph_registers.c']]], - ['crc_3676',['CRC',['../group___peripheral__declaration.html#ga4381bb54c2dbc34500521165aa7b89b1',1,'stm32f407xx_matlab.h']]], - ['crc_5fbase_3677',['CRC_BASE',['../group___peripheral__memory__map.html#ga656a447589e785594cbf2f45c835ad7e',1,'stm32f407xx_matlab.h']]], - ['crc_5fcr_5freset_3678',['CRC_CR_RESET',['../group___peripheral___registers___bits___definition.html#ga7d57481fb891a0964b40f721354c56d7',1,'stm32f407xx_matlab.h']]], - ['crc_5fcr_5freset_5fmsk_3679',['CRC_CR_RESET_Msk',['../group___peripheral___registers___bits___definition.html#ga04d46dadb6b31660c4ef0af2b00053f5',1,'stm32f407xx_matlab.h']]], - ['crc_5fcr_5freset_5fpos_3680',['CRC_CR_RESET_Pos',['../group___peripheral___registers___bits___definition.html#ga7a12ab5306d6320069e08e63cd9a56f1',1,'stm32f407xx_matlab.h']]], - ['crc_5fdr_5fdr_3681',['CRC_DR_DR',['../group___peripheral___registers___bits___definition.html#ga2bf4701d3b15924e657942ce3caa4105',1,'stm32f407xx_matlab.h']]], - ['crc_5fdr_5fdr_5fmsk_3682',['CRC_DR_DR_Msk',['../group___peripheral___registers___bits___definition.html#gadd43c14689d281daa4e9a32bf8ec89e1',1,'stm32f407xx_matlab.h']]], - ['crc_5fdr_5fdr_5fpos_3683',['CRC_DR_DR_Pos',['../group___peripheral___registers___bits___definition.html#ga3deebcf1cf5fae1957476154502b1fb5',1,'stm32f407xx_matlab.h']]], - ['crc_5fidr_5fidr_3684',['CRC_IDR_IDR',['../group___peripheral___registers___bits___definition.html#gae9a0feb3cf1d8c5871e663ca4a174cc0',1,'stm32f407xx_matlab.h']]], - ['crc_5fidr_5fidr_5fmsk_3685',['CRC_IDR_IDR_Msk',['../group___peripheral___registers___bits___definition.html#ga306789258d5416a44e545aa2ad6b2f7a',1,'stm32f407xx_matlab.h']]], - ['crc_5fidr_5fidr_5fpos_3686',['CRC_IDR_IDR_Pos',['../group___peripheral___registers___bits___definition.html#gab63759809b1cd1cfdf46d92becc60f85',1,'stm32f407xx_matlab.h']]], - ['crc_5ftypedef_3687',['CRC_TypeDef',['../struct_c_r_c___type_def.html',1,'']]], - ['crcpr_3688',['CRCPR',['../group___c_m_s_i_s___device.html#gace450027b4b33f921dd8edd3425a717c',1,'SPI_TypeDef']]], - ['create_5fsuspended_3689',['CREATE_SUSPENDED',['../group___w_r_a_p_p_e_r___c_o_n_f.html#ga98a12c757c95bd7c8ae75999092af30f',1,'mcu_wrapper_conf.h']]], - ['cspsr_3690',['CSPSR',['../group___c_m_s_i_s__core___debug_functions.html#gabf4a378b17278d98d2a5f9315fce7a5e',1,'TPI_Type']]], - ['csr_3691',['CSR',['../group___c_m_s_i_s___device.html#ga876dd0a8546697065f406b7543e27af2',1,'ADC_Common_TypeDef::CSR'],['../group___c_m_s_i_s___device.html#ga876dd0a8546697065f406b7543e27af2',1,'PWR_TypeDef::CSR'],['../group___c_m_s_i_s___device.html#ga876dd0a8546697065f406b7543e27af2',1,'RCC_TypeDef::CSR']]], - ['ctrl_3692',['CTRL',['../group___c_m_s_i_s__core___debug_functions.html#gac81efc171e9852a36caeb47122bfec5b',1,'SysTick_Type::CTRL'],['../group___c_m_s_i_s__core___debug_functions.html#gac81efc171e9852a36caeb47122bfec5b',1,'DWT_Type::CTRL']]], - ['cwsizer_3693',['CWSIZER',['../group___c_m_s_i_s___device.html#gaa3ccc5d081bbee3c61ae9aa5e0c83af9',1,'DCMI_TypeDef']]], - ['cwstrtr_3694',['CWSTRTR',['../group___c_m_s_i_s___device.html#ga919b70dd8762e44263a02dfbafc7b8ce',1,'DCMI_TypeDef']]], - ['cyccnt_3695',['CYCCNT',['../group___c_m_s_i_s__core___debug_functions.html#ga14822f5ad3426799332ac537d9293f3c',1,'DWT_Type']]] + ['call_5firqhandller_0',['call_IRQHandller',['../group___t_i_m___s_i_m_u_l_a_t_o_r.html#gaa2b3ab4507a894ffa6e4487d42054e67',1,'call_IRQHandller(TIM_TypeDef *TIMx): stm32f4xx_matlab_tim.c'],['../group___t_i_m___s_i_m_u_l_a_t_o_r.html#gaa2b3ab4507a894ffa6e4487d42054e67',1,'call_IRQHandller(TIM_TypeDef *TIMx): stm32f4xx_matlab_tim.c']]], + ['can1_1',['can1',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga047c365ed69ab08e79c499adcedff87b',1,'stm32f4xx_periph_registers.c']]], + ['can2_2',['can2',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#gae4b5c771c41468ea4ffa1af4de9ce39e',1,'stm32f4xx_periph_registers.c']]], + ['cc_5fpwm_5fch1_5fsimulation_3',['CC_PWM_Ch1_Simulation',['../group___t_i_m___s_i_m_u_l_a_t_o_r.html#ga609dd2da1a15ffb80256e85942ed2671',1,'CC_PWM_Ch1_Simulation(TIM_TypeDef *TIMx, struct TIM_Sim *TIMS): stm32f4xx_matlab_tim.c'],['../group___t_i_m___s_i_m_u_l_a_t_o_r.html#ga609dd2da1a15ffb80256e85942ed2671',1,'CC_PWM_Ch1_Simulation(TIM_TypeDef *TIMx, struct TIM_Sim *TIMS): stm32f4xx_matlab_tim.c']]], + ['cc_5fpwm_5fch2_5fsimulation_4',['CC_PWM_Ch2_Simulation',['../group___t_i_m___s_i_m_u_l_a_t_o_r.html#gaef90da33b410dcd77d9cdb58363d729c',1,'CC_PWM_Ch2_Simulation(TIM_TypeDef *TIMx, struct TIM_Sim *TIMS): stm32f4xx_matlab_tim.c'],['../group___t_i_m___s_i_m_u_l_a_t_o_r.html#gaef90da33b410dcd77d9cdb58363d729c',1,'CC_PWM_Ch2_Simulation(TIM_TypeDef *TIMx, struct TIM_Sim *TIMS): stm32f4xx_matlab_tim.c']]], + ['cc_5fpwm_5fch3_5fsimulation_5',['CC_PWM_Ch3_Simulation',['../group___t_i_m___s_i_m_u_l_a_t_o_r.html#ga99db7a05808ca9b5aa12df01745ed2ef',1,'CC_PWM_Ch3_Simulation(TIM_TypeDef *TIMx, struct TIM_Sim *TIMS): stm32f4xx_matlab_tim.c'],['../group___t_i_m___s_i_m_u_l_a_t_o_r.html#ga99db7a05808ca9b5aa12df01745ed2ef',1,'CC_PWM_Ch3_Simulation(TIM_TypeDef *TIMx, struct TIM_Sim *TIMS): stm32f4xx_matlab_tim.c']]], + ['cc_5fpwm_5fch4_5fsimulation_6',['CC_PWM_Ch4_Simulation',['../group___t_i_m___s_i_m_u_l_a_t_o_r.html#gad51e3fbb47f5768c33876ad803fbef20',1,'CC_PWM_Ch4_Simulation(TIM_TypeDef *TIMx, struct TIM_Sim *TIMS): stm32f4xx_matlab_tim.c'],['../group___t_i_m___s_i_m_u_l_a_t_o_r.html#gad51e3fbb47f5768c33876ad803fbef20',1,'CC_PWM_Ch4_Simulation(TIM_TypeDef *TIMx, struct TIM_Sim *TIMS): stm32f4xx_matlab_tim.c']]], + ['ccmdataram_5fbase_7',['CCMDATARAM_BASE',['../struct__memory.html#acd6db2394f2b493a873059464d5b0e18',1,'_memory::CCMDATARAM_BASE'],['../group___peripheral__memory__map.html#gabea1f1810ebeac402164b42ab54bcdf9',1,'CCMDATARAM_BASE: stm32f407xx_matlab_memory.h']]], + ['ccmdataram_5fbase_5fshift_8',['CCMDATARAM_BASE_SHIFT',['../group___peripheral__memory__map.html#ga2d06a3566d8983055baf9e883e0198ef',1,'stm32f407xx_matlab_memory.h']]], + ['ccmdataram_5fend_9',['CCMDATARAM_END',['../group___peripheral__memory__map.html#ga9fbe263946209e6f09faf93512bd2f9a',1,'stm32f407xx_matlab_memory.h']]], + ['ccmdataram_5fend_5fshift_10',['CCMDATARAM_END_SHIFT',['../group___peripheral__memory__map.html#ga86d258a24d1cef85ee0333fcaf6398a8',1,'stm32f407xx_matlab_memory.h']]], + ['ccmdataram_5fsize_11',['CCMDATARAM_SIZE',['../group___peripheral__memory__map.html#ga71542ecbf91e5a2e4e7657ebf4743bb0',1,'stm32f407xx_matlab_memory.h']]], + ['channels_12',['Channels',['../struct_t_i_m___sim.html#a41f21d0d1bfe0fb45e3f643ece9cdcee',1,'TIM_Sim']]], + ['channels_5fsim_13',['Channels_Sim',['../struct_channels___sim.html',1,'']]], + ['channels_5fsimulation_14',['Channels_Simulation',['../group___t_i_m___s_i_m_u_l_a_t_o_r.html#ga63dc3b53fe4b165b4c70e4d600258d50',1,'Channels_Simulation(TIM_TypeDef *TIMx, struct TIM_Sim *TIMS): stm32f4xx_matlab_tim.c'],['../group___t_i_m___s_i_m_u_l_a_t_o_r.html#ga63dc3b53fe4b165b4c70e4d600258d50',1,'Channels_Simulation(TIM_TypeDef *TIMx, struct TIM_Sim *TIMS): stm32f4xx_matlab_tim.c']]], + ['check_5foc1_5fgpio_5foutput_15',['Check_OC1_GPIO_Output',['../group___t_i_m___s_i_m_u_l_a_t_o_r.html#ga819ef3dc9ad489178802ed1dcb0e6b41',1,'stm32f4xx_matlab_tim.h']]], + ['check_5foc2_5fgpio_5foutput_16',['Check_OC2_GPIO_Output',['../group___t_i_m___s_i_m_u_l_a_t_o_r.html#gab05cf435dbdfc0a827fc6cf093d27694',1,'stm32f4xx_matlab_tim.h']]], + ['check_5foc3_5fgpio_5foutput_17',['Check_OC3_GPIO_Output',['../group___t_i_m___s_i_m_u_l_a_t_o_r.html#ga1303da0a61cb89d0952378d46b1be2a3',1,'stm32f4xx_matlab_tim.h']]], + ['check_5foc4_5fgpio_5foutput_18',['Check_OC4_GPIO_Output',['../group___t_i_m___s_i_m_u_l_a_t_o_r.html#gadd3fec5a120bcd59e8396435da2cb639',1,'stm32f4xx_matlab_tim.h']]], + ['check_5focx_5fgpio_5foutput_19',['Check_OCx_GPIO_Output',['../group___t_i_m___s_i_m_u_l_a_t_o_r.html#ga332e5c16b48c0bc5a7c1f978442ef49f',1,'stm32f4xx_matlab_tim.h']]], + ['clear_5fflag_5fif_5fits_5fexpected_20',['Clear_Flag_If_Its_Expected',['../group___r_c_c___s_i_m_u_l_a_t_o_r.html#ga5dc1d225a53e67cc732ca9069ffb1f0d',1,'stm32f4xx_matlab_rcc.h']]], + ['configuration_21',['Configuration',['../group___s_i_m_u_l_a_t_o_r___c_o_n_f.html',1,'Simulator Configuration'],['../group___w_r_a_p_p_e_r___c_o_n_f.html',1,'Wrapper Configuration']]], + ['core_20definitions_22',['Core Definitions',['../group___c_m_s_i_s__core__base.html',1,'']]], + ['coredebug_5fbase_23',['CoreDebug_BASE',['../group___c_m_s_i_s__core__base.html#ga680604dbcda9e9b31a1639fcffe5230b',1,'stm32f407xx_matlab_memory.h']]], + ['coredebug_5fbase_5fshift_24',['CoreDebug_BASE_SHIFT',['../group___c_m_s_i_s__core__base.html#ga3b760f7bd0c5082d2d0db746f778c329',1,'stm32f407xx_matlab_memory.h']]], + ['cortex_5fperiph_5fbase_25',['CORTEX_PERIPH_BASE',['../struct__cortex__memory.html#a33c7ca027b61cba4b327fcad1c1cb7aa',1,'_cortex_memory']]], + ['crc_26',['crc',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga0be4a4f92234a92301b5dea4ef762a83',1,'stm32f4xx_periph_registers.c']]], + ['create_5fsuspended_27',['CREATE_SUSPENDED',['../group___w_r_a_p_p_e_r___c_o_n_f.html#ga98a12c757c95bd7c8ae75999092af30f',1,'mcu_wrapper_conf.h']]] ]; diff --git a/DOCS/html/search/all_4.js b/DOCS/html/search/all_4.js index 972d9d9..9d2b8a1 100644 --- a/DOCS/html/search/all_4.js +++ b/DOCS/html/search/all_4.js @@ -1,976 +1,39 @@ var searchData= [ ['dac_0',['dac',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#gad8051cafe91bba5f5a52af50cd3a11da',1,'stm32f4xx_periph_registers.c']]], - ['dac_1',['DAC',['../group___peripheral__declaration.html#ga4aa2a4ab86ce00c23035e5cee2e7fc7e',1,'stm32f407xx_matlab.h']]], - ['dac1_2',['dac1',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#gac2a5eec34721432ce7d7dec940c4a105',1,'stm32f4xx_periph_registers.c']]], - ['dac1_3',['DAC1',['../group___peripheral__declaration.html#gaffb5ff8779fa698f3c7165a617d56e4f',1,'stm32f407xx_matlab.h']]], - ['dac_5fbase_4',['DAC_BASE',['../group___peripheral__memory__map.html#gad18d0b914c7f68cecbee1a2d23a67d38',1,'stm32f407xx_matlab.h']]], - ['dac_5fchannel2_5fsupport_5',['DAC_CHANNEL2_SUPPORT',['../group___peripheral___registers___bits___definition.html#ga88aaf7e89ddcd648227fd514315c9838',1,'stm32f407xx_matlab.h']]], - ['dac_5fcr_5fboff1_6',['DAC_CR_BOFF1',['../group___peripheral___registers___bits___definition.html#ga0b1e2b83ae1ab889cb1e34a99746c9d8',1,'stm32f407xx_matlab.h']]], - ['dac_5fcr_5fboff1_5fmsk_7',['DAC_CR_BOFF1_Msk',['../group___peripheral___registers___bits___definition.html#gad4cba0a69210b9ccb8566cfb83196e6f',1,'stm32f407xx_matlab.h']]], - ['dac_5fcr_5fboff1_5fpos_8',['DAC_CR_BOFF1_Pos',['../group___peripheral___registers___bits___definition.html#ga9f43af44fba93c50bf4765608ec6d902',1,'stm32f407xx_matlab.h']]], - ['dac_5fcr_5fboff2_9',['DAC_CR_BOFF2',['../group___peripheral___registers___bits___definition.html#gadd6f660a5f15262beca06b9098a559e9',1,'stm32f407xx_matlab.h']]], - ['dac_5fcr_5fboff2_5fmsk_10',['DAC_CR_BOFF2_Msk',['../group___peripheral___registers___bits___definition.html#ga088fea2fa6ece1301af6818b836469f3',1,'stm32f407xx_matlab.h']]], - ['dac_5fcr_5fboff2_5fpos_11',['DAC_CR_BOFF2_Pos',['../group___peripheral___registers___bits___definition.html#gabb3eb9eaa48220ba7cac6204c4637b75',1,'stm32f407xx_matlab.h']]], - ['dac_5fcr_5fdmaen1_12',['DAC_CR_DMAEN1',['../group___peripheral___registers___bits___definition.html#ga995c19d8c8de9ee09057ec6151154e17',1,'stm32f407xx_matlab.h']]], - ['dac_5fcr_5fdmaen1_5fmsk_13',['DAC_CR_DMAEN1_Msk',['../group___peripheral___registers___bits___definition.html#ga6509ff097fb987e9f1c592d6d5869356',1,'stm32f407xx_matlab.h']]], - ['dac_5fcr_5fdmaen1_5fpos_14',['DAC_CR_DMAEN1_Pos',['../group___peripheral___registers___bits___definition.html#gac1caf9621895f2a99c4b33a0908247b6',1,'stm32f407xx_matlab.h']]], - ['dac_5fcr_5fdmaen2_15',['DAC_CR_DMAEN2',['../group___peripheral___registers___bits___definition.html#ga6f905c2ac89f976df6c4beffdde58b53',1,'stm32f407xx_matlab.h']]], - ['dac_5fcr_5fdmaen2_5fmsk_16',['DAC_CR_DMAEN2_Msk',['../group___peripheral___registers___bits___definition.html#gaa85027944d9eddc64c42ee2ed98611f4',1,'stm32f407xx_matlab.h']]], - ['dac_5fcr_5fdmaen2_5fpos_17',['DAC_CR_DMAEN2_Pos',['../group___peripheral___registers___bits___definition.html#ga264e3d328584463c5164a7cca726cabb',1,'stm32f407xx_matlab.h']]], - ['dac_5fcr_5fdmaudrie1_18',['DAC_CR_DMAUDRIE1',['../group___peripheral___registers___bits___definition.html#gacbb0585e1053abf18cd129ad76a66bea',1,'stm32f407xx_matlab.h']]], - ['dac_5fcr_5fdmaudrie1_5fmsk_19',['DAC_CR_DMAUDRIE1_Msk',['../group___peripheral___registers___bits___definition.html#ga8ad8aa68545055eac63ab43cc5d3da91',1,'stm32f407xx_matlab.h']]], - ['dac_5fcr_5fdmaudrie1_5fpos_20',['DAC_CR_DMAUDRIE1_Pos',['../group___peripheral___registers___bits___definition.html#ga8a11a25b89aa18648594cb72bf3918bf',1,'stm32f407xx_matlab.h']]], - ['dac_5fcr_5fdmaudrie2_21',['DAC_CR_DMAUDRIE2',['../group___peripheral___registers___bits___definition.html#ga803e3bae78ced744b93aa76615303e15',1,'stm32f407xx_matlab.h']]], - ['dac_5fcr_5fdmaudrie2_5fmsk_22',['DAC_CR_DMAUDRIE2_Msk',['../group___peripheral___registers___bits___definition.html#ga239ab4f68c1a74d0e9423bbf6c98c5da',1,'stm32f407xx_matlab.h']]], - ['dac_5fcr_5fdmaudrie2_5fpos_23',['DAC_CR_DMAUDRIE2_Pos',['../group___peripheral___registers___bits___definition.html#gad6bf1e308092f2ef72387eb0fc5a8412',1,'stm32f407xx_matlab.h']]], - ['dac_5fcr_5fen1_24',['DAC_CR_EN1',['../group___peripheral___registers___bits___definition.html#gabd8cedbb3dda03d56ac0ba92d2d9cefd',1,'stm32f407xx_matlab.h']]], - ['dac_5fcr_5fen1_5fmsk_25',['DAC_CR_EN1_Msk',['../group___peripheral___registers___bits___definition.html#gaa4462abe77801be4a752c73aa2ff9a70',1,'stm32f407xx_matlab.h']]], - ['dac_5fcr_5fen1_5fpos_26',['DAC_CR_EN1_Pos',['../group___peripheral___registers___bits___definition.html#ga7663eb8440e12383fc88241acbfc99cf',1,'stm32f407xx_matlab.h']]], - ['dac_5fcr_5fen2_27',['DAC_CR_EN2',['../group___peripheral___registers___bits___definition.html#gaa65db2420e02fc6813842f57134d898f',1,'stm32f407xx_matlab.h']]], - ['dac_5fcr_5fen2_5fmsk_28',['DAC_CR_EN2_Msk',['../group___peripheral___registers___bits___definition.html#ga84b276403310ffa2407b8c57996456e7',1,'stm32f407xx_matlab.h']]], - ['dac_5fcr_5fen2_5fpos_29',['DAC_CR_EN2_Pos',['../group___peripheral___registers___bits___definition.html#gaf2dbea8c55239069a24139f398785af4',1,'stm32f407xx_matlab.h']]], - ['dac_5fcr_5fmamp1_30',['DAC_CR_MAMP1',['../group___peripheral___registers___bits___definition.html#ga3bcf611b2f0b975513325895bf16e085',1,'stm32f407xx_matlab.h']]], - ['dac_5fcr_5fmamp1_5f0_31',['DAC_CR_MAMP1_0',['../group___peripheral___registers___bits___definition.html#ga4225dcce22b440fcd3a8ad96c5f2baec',1,'stm32f407xx_matlab.h']]], - ['dac_5fcr_5fmamp1_5f1_32',['DAC_CR_MAMP1_1',['../group___peripheral___registers___bits___definition.html#ga6cc15817842cb7992d449c448684f68d',1,'stm32f407xx_matlab.h']]], - ['dac_5fcr_5fmamp1_5f2_33',['DAC_CR_MAMP1_2',['../group___peripheral___registers___bits___definition.html#ga0fefef1d798a2685b03e44bd9fdac06b',1,'stm32f407xx_matlab.h']]], - ['dac_5fcr_5fmamp1_5f3_34',['DAC_CR_MAMP1_3',['../group___peripheral___registers___bits___definition.html#gafdc83b4feb742c632ba66f55d102432b',1,'stm32f407xx_matlab.h']]], - ['dac_5fcr_5fmamp1_5fmsk_35',['DAC_CR_MAMP1_Msk',['../group___peripheral___registers___bits___definition.html#ga7f4fc31ff760aaa38ad85da8c4f1918a',1,'stm32f407xx_matlab.h']]], - ['dac_5fcr_5fmamp1_5fpos_36',['DAC_CR_MAMP1_Pos',['../group___peripheral___registers___bits___definition.html#ga018b4d24c02a803f2efb996745f49015',1,'stm32f407xx_matlab.h']]], - ['dac_5fcr_5fmamp2_37',['DAC_CR_MAMP2',['../group___peripheral___registers___bits___definition.html#ga7cf03fe2359cb0f11c33f793c2e92bdd',1,'stm32f407xx_matlab.h']]], - ['dac_5fcr_5fmamp2_5f0_38',['DAC_CR_MAMP2_0',['../group___peripheral___registers___bits___definition.html#gae8d952192721dbdcea8d707d43096454',1,'stm32f407xx_matlab.h']]], - ['dac_5fcr_5fmamp2_5f1_39',['DAC_CR_MAMP2_1',['../group___peripheral___registers___bits___definition.html#ga860032e8196838cd36a655c1749139d6',1,'stm32f407xx_matlab.h']]], - ['dac_5fcr_5fmamp2_5f2_40',['DAC_CR_MAMP2_2',['../group___peripheral___registers___bits___definition.html#ga2147ffa3282e9ff22475e5d6040f269e',1,'stm32f407xx_matlab.h']]], - ['dac_5fcr_5fmamp2_5f3_41',['DAC_CR_MAMP2_3',['../group___peripheral___registers___bits___definition.html#gaa0fe77a2029873111cbe723a5cba9c57',1,'stm32f407xx_matlab.h']]], - ['dac_5fcr_5fmamp2_5fmsk_42',['DAC_CR_MAMP2_Msk',['../group___peripheral___registers___bits___definition.html#gace1bce6cad4004ab884396a1d73a1725',1,'stm32f407xx_matlab.h']]], - ['dac_5fcr_5fmamp2_5fpos_43',['DAC_CR_MAMP2_Pos',['../group___peripheral___registers___bits___definition.html#ga7cccefc999aeab6622afaf662c7c8c50',1,'stm32f407xx_matlab.h']]], - ['dac_5fcr_5ften1_44',['DAC_CR_TEN1',['../group___peripheral___registers___bits___definition.html#ga998aa4fd791ea2f4626df6ddc8fc7109',1,'stm32f407xx_matlab.h']]], - ['dac_5fcr_5ften1_5fmsk_45',['DAC_CR_TEN1_Msk',['../group___peripheral___registers___bits___definition.html#ga1be7eb4a830047b463d611c2c813f437',1,'stm32f407xx_matlab.h']]], - ['dac_5fcr_5ften1_5fpos_46',['DAC_CR_TEN1_Pos',['../group___peripheral___registers___bits___definition.html#ga6ef4ab719505604c7a41e31c27fd05dd',1,'stm32f407xx_matlab.h']]], - ['dac_5fcr_5ften2_47',['DAC_CR_TEN2',['../group___peripheral___registers___bits___definition.html#gab8fc527f6ddb787123da09d2085b772f',1,'stm32f407xx_matlab.h']]], - ['dac_5fcr_5ften2_5fmsk_48',['DAC_CR_TEN2_Msk',['../group___peripheral___registers___bits___definition.html#gac16d129b7793ddcfef47bd642478d1df',1,'stm32f407xx_matlab.h']]], - ['dac_5fcr_5ften2_5fpos_49',['DAC_CR_TEN2_Pos',['../group___peripheral___registers___bits___definition.html#gaa2ef8fa2150330a16a2b19f17caa051e',1,'stm32f407xx_matlab.h']]], - ['dac_5fcr_5ftsel1_50',['DAC_CR_TSEL1',['../group___peripheral___registers___bits___definition.html#gaf951c1a57a1a19e356df57d908f09c6c',1,'stm32f407xx_matlab.h']]], - ['dac_5fcr_5ftsel1_5f0_51',['DAC_CR_TSEL1_0',['../group___peripheral___registers___bits___definition.html#ga8dfa13ec123c583136e24b7890add45b',1,'stm32f407xx_matlab.h']]], - ['dac_5fcr_5ftsel1_5f1_52',['DAC_CR_TSEL1_1',['../group___peripheral___registers___bits___definition.html#ga265e32c4fc43310acdf3ebea01376766',1,'stm32f407xx_matlab.h']]], - ['dac_5fcr_5ftsel1_5f2_53',['DAC_CR_TSEL1_2',['../group___peripheral___registers___bits___definition.html#gaa625d7638422e90a616ac93edd4bf408',1,'stm32f407xx_matlab.h']]], - ['dac_5fcr_5ftsel1_5fmsk_54',['DAC_CR_TSEL1_Msk',['../group___peripheral___registers___bits___definition.html#ga0ca56925c2b1f9c7662c850146bec7bd',1,'stm32f407xx_matlab.h']]], - ['dac_5fcr_5ftsel1_5fpos_55',['DAC_CR_TSEL1_Pos',['../group___peripheral___registers___bits___definition.html#gadc5baf43a193c631ad3c05eb24b97a7b',1,'stm32f407xx_matlab.h']]], - ['dac_5fcr_5ftsel2_56',['DAC_CR_TSEL2',['../group___peripheral___registers___bits___definition.html#ga73b4d0ccff78f7c3862903e7b0e66302',1,'stm32f407xx_matlab.h']]], - ['dac_5fcr_5ftsel2_5f0_57',['DAC_CR_TSEL2_0',['../group___peripheral___registers___bits___definition.html#ga9753b87f31e7106ecf77b2f01a99b237',1,'stm32f407xx_matlab.h']]], - ['dac_5fcr_5ftsel2_5f1_58',['DAC_CR_TSEL2_1',['../group___peripheral___registers___bits___definition.html#gac79323a6c81bfa5c8239b23cd3db737a',1,'stm32f407xx_matlab.h']]], - ['dac_5fcr_5ftsel2_5f2_59',['DAC_CR_TSEL2_2',['../group___peripheral___registers___bits___definition.html#ga9ad3da8a9c5fe9566d8ffe38916caaff',1,'stm32f407xx_matlab.h']]], - ['dac_5fcr_5ftsel2_5fmsk_60',['DAC_CR_TSEL2_Msk',['../group___peripheral___registers___bits___definition.html#ga0c9339a1dc175b09378d1168ab514333',1,'stm32f407xx_matlab.h']]], - ['dac_5fcr_5ftsel2_5fpos_61',['DAC_CR_TSEL2_Pos',['../group___peripheral___registers___bits___definition.html#ga80a933188591c4fbcad260c256105277',1,'stm32f407xx_matlab.h']]], - ['dac_5fcr_5fwave1_62',['DAC_CR_WAVE1',['../group___peripheral___registers___bits___definition.html#ga90491f31219d07175629eecdcdc9271e',1,'stm32f407xx_matlab.h']]], - ['dac_5fcr_5fwave1_5f0_63',['DAC_CR_WAVE1_0',['../group___peripheral___registers___bits___definition.html#ga0871e6466e3a7378103c431832ae525a',1,'stm32f407xx_matlab.h']]], - ['dac_5fcr_5fwave1_5f1_64',['DAC_CR_WAVE1_1',['../group___peripheral___registers___bits___definition.html#ga48e167ae02d2ad5bc9fd30c2f8ea5b37',1,'stm32f407xx_matlab.h']]], - ['dac_5fcr_5fwave1_5fmsk_65',['DAC_CR_WAVE1_Msk',['../group___peripheral___registers___bits___definition.html#ga8d85e9d75f265088a37b911f573e7dd3',1,'stm32f407xx_matlab.h']]], - ['dac_5fcr_5fwave1_5fpos_66',['DAC_CR_WAVE1_Pos',['../group___peripheral___registers___bits___definition.html#ga16a0202d6e3295400dc21b2088d333e1',1,'stm32f407xx_matlab.h']]], - ['dac_5fcr_5fwave2_67',['DAC_CR_WAVE2',['../group___peripheral___registers___bits___definition.html#gacf24e48cf288db4a4643057dd09e3a7b',1,'stm32f407xx_matlab.h']]], - ['dac_5fcr_5fwave2_5f0_68',['DAC_CR_WAVE2_0',['../group___peripheral___registers___bits___definition.html#ga55d97d8bcbfdd72d5aeb9e9fbc0d592d',1,'stm32f407xx_matlab.h']]], - ['dac_5fcr_5fwave2_5f1_69',['DAC_CR_WAVE2_1',['../group___peripheral___registers___bits___definition.html#ga4798bf254010b442b4ac4288c2f1b65f',1,'stm32f407xx_matlab.h']]], - ['dac_5fcr_5fwave2_5fmsk_70',['DAC_CR_WAVE2_Msk',['../group___peripheral___registers___bits___definition.html#ga0420dd10713d50b05ab6c477ab502893',1,'stm32f407xx_matlab.h']]], - ['dac_5fcr_5fwave2_5fpos_71',['DAC_CR_WAVE2_Pos',['../group___peripheral___registers___bits___definition.html#ga7795c9de47dc6747045ee7e2e6fb8ba9',1,'stm32f407xx_matlab.h']]], - ['dac_5fdhr12l1_5fdacc1dhr_72',['DAC_DHR12L1_DACC1DHR',['../group___peripheral___registers___bits___definition.html#ga0d34667f8f4b753689c8c936c28471c5',1,'stm32f407xx_matlab.h']]], - ['dac_5fdhr12l1_5fdacc1dhr_5fmsk_73',['DAC_DHR12L1_DACC1DHR_Msk',['../group___peripheral___registers___bits___definition.html#ga065dab2c8181ab7e3ff6cb43a86400c4',1,'stm32f407xx_matlab.h']]], - ['dac_5fdhr12l1_5fdacc1dhr_5fpos_74',['DAC_DHR12L1_DACC1DHR_Pos',['../group___peripheral___registers___bits___definition.html#gac1dcdc73fc338b3548cddcf84fb0c951',1,'stm32f407xx_matlab.h']]], - ['dac_5fdhr12l2_5fdacc2dhr_75',['DAC_DHR12L2_DACC2DHR',['../group___peripheral___registers___bits___definition.html#ga0f66bd794202221e1a55547673b7abab',1,'stm32f407xx_matlab.h']]], - ['dac_5fdhr12l2_5fdacc2dhr_5fmsk_76',['DAC_DHR12L2_DACC2DHR_Msk',['../group___peripheral___registers___bits___definition.html#ga40a67db51971c777b7ee75c4da5bc8e8',1,'stm32f407xx_matlab.h']]], - ['dac_5fdhr12l2_5fdacc2dhr_5fpos_77',['DAC_DHR12L2_DACC2DHR_Pos',['../group___peripheral___registers___bits___definition.html#ga8fe559f6278c4abd3b5db6277e82925b',1,'stm32f407xx_matlab.h']]], - ['dac_5fdhr12ld_5fdacc1dhr_78',['DAC_DHR12LD_DACC1DHR',['../group___peripheral___registers___bits___definition.html#ga203db656bfef6fedee17b99fb77b1bdd',1,'stm32f407xx_matlab.h']]], - ['dac_5fdhr12ld_5fdacc1dhr_5fmsk_79',['DAC_DHR12LD_DACC1DHR_Msk',['../group___peripheral___registers___bits___definition.html#gabbf9e7bb591e9c954f648ce36f5f9f90',1,'stm32f407xx_matlab.h']]], - ['dac_5fdhr12ld_5fdacc1dhr_5fpos_80',['DAC_DHR12LD_DACC1DHR_Pos',['../group___peripheral___registers___bits___definition.html#gaa367fe7ed3f9b2d5114dcc46ccab7468',1,'stm32f407xx_matlab.h']]], - ['dac_5fdhr12ld_5fdacc2dhr_81',['DAC_DHR12LD_DACC2DHR',['../group___peripheral___registers___bits___definition.html#ga8421d613b182aab8d6c58592bcda6c17',1,'stm32f407xx_matlab.h']]], - ['dac_5fdhr12ld_5fdacc2dhr_5fmsk_82',['DAC_DHR12LD_DACC2DHR_Msk',['../group___peripheral___registers___bits___definition.html#ga0c6a0375af61a42378851c55436f0e23',1,'stm32f407xx_matlab.h']]], - ['dac_5fdhr12ld_5fdacc2dhr_5fpos_83',['DAC_DHR12LD_DACC2DHR_Pos',['../group___peripheral___registers___bits___definition.html#gade1db665f01f9d179045057d0e857da0',1,'stm32f407xx_matlab.h']]], - ['dac_5fdhr12r1_5fdacc1dhr_84',['DAC_DHR12R1_DACC1DHR',['../group___peripheral___registers___bits___definition.html#ga5295b5cb7f5d71ed2e8a310deb00013d',1,'stm32f407xx_matlab.h']]], - ['dac_5fdhr12r1_5fdacc1dhr_5fmsk_85',['DAC_DHR12R1_DACC1DHR_Msk',['../group___peripheral___registers___bits___definition.html#ga203fee3fe672b7468231c91ce8a55e4b',1,'stm32f407xx_matlab.h']]], - ['dac_5fdhr12r1_5fdacc1dhr_5fpos_86',['DAC_DHR12R1_DACC1DHR_Pos',['../group___peripheral___registers___bits___definition.html#gab3250ec13530e0e363f0ab92c149774f',1,'stm32f407xx_matlab.h']]], - ['dac_5fdhr12r2_5fdacc2dhr_87',['DAC_DHR12R2_DACC2DHR',['../group___peripheral___registers___bits___definition.html#ga7506e369b37d55826042b540b10e44c7',1,'stm32f407xx_matlab.h']]], - ['dac_5fdhr12r2_5fdacc2dhr_5fmsk_88',['DAC_DHR12R2_DACC2DHR_Msk',['../group___peripheral___registers___bits___definition.html#gad3cf4f31c9248dc74d00b813c1f2b2e0',1,'stm32f407xx_matlab.h']]], - ['dac_5fdhr12r2_5fdacc2dhr_5fpos_89',['DAC_DHR12R2_DACC2DHR_Pos',['../group___peripheral___registers___bits___definition.html#gadd13752ec5bc912023c608426e47908e',1,'stm32f407xx_matlab.h']]], - ['dac_5fdhr12rd_5fdacc1dhr_90',['DAC_DHR12RD_DACC1DHR',['../group___peripheral___registers___bits___definition.html#gaca45719f3d365c9495bdcf6364ae59f8',1,'stm32f407xx_matlab.h']]], - ['dac_5fdhr12rd_5fdacc1dhr_5fmsk_91',['DAC_DHR12RD_DACC1DHR_Msk',['../group___peripheral___registers___bits___definition.html#ga7cf050c1d3f7c651b461b463c8ae659e',1,'stm32f407xx_matlab.h']]], - ['dac_5fdhr12rd_5fdacc1dhr_5fpos_92',['DAC_DHR12RD_DACC1DHR_Pos',['../group___peripheral___registers___bits___definition.html#ga6d1a7b56cdc34694e1aa032be202e79d',1,'stm32f407xx_matlab.h']]], - ['dac_5fdhr12rd_5fdacc2dhr_93',['DAC_DHR12RD_DACC2DHR',['../group___peripheral___registers___bits___definition.html#ga3edd68db1697af93027e05f6b764c540',1,'stm32f407xx_matlab.h']]], - ['dac_5fdhr12rd_5fdacc2dhr_5fmsk_94',['DAC_DHR12RD_DACC2DHR_Msk',['../group___peripheral___registers___bits___definition.html#gaa0ae28d5d855fd8fe53de3d5fc2ee437',1,'stm32f407xx_matlab.h']]], - ['dac_5fdhr12rd_5fdacc2dhr_5fpos_95',['DAC_DHR12RD_DACC2DHR_Pos',['../group___peripheral___registers___bits___definition.html#gae522220c8b02ab4bcf82f122a45997d3',1,'stm32f407xx_matlab.h']]], - ['dac_5fdhr8r1_5fdacc1dhr_96',['DAC_DHR8R1_DACC1DHR',['../group___peripheral___registers___bits___definition.html#gae1fc9f022fe4a08f67c51646177b26cb',1,'stm32f407xx_matlab.h']]], - ['dac_5fdhr8r1_5fdacc1dhr_5fmsk_97',['DAC_DHR8R1_DACC1DHR_Msk',['../group___peripheral___registers___bits___definition.html#gacde0062be02bb512e2bdc5ee84b4f17f',1,'stm32f407xx_matlab.h']]], - ['dac_5fdhr8r1_5fdacc1dhr_5fpos_98',['DAC_DHR8R1_DACC1DHR_Pos',['../group___peripheral___registers___bits___definition.html#ga6b874c02d121c755a1d4523f2e39134e',1,'stm32f407xx_matlab.h']]], - ['dac_5fdhr8r2_5fdacc2dhr_99',['DAC_DHR8R2_DACC2DHR',['../group___peripheral___registers___bits___definition.html#ga7da94dc053e6637efb9ccb57b7ae481c',1,'stm32f407xx_matlab.h']]], - ['dac_5fdhr8r2_5fdacc2dhr_5fmsk_100',['DAC_DHR8R2_DACC2DHR_Msk',['../group___peripheral___registers___bits___definition.html#gabf3e9e86edc54f83e02d2a0d3f486658',1,'stm32f407xx_matlab.h']]], - ['dac_5fdhr8r2_5fdacc2dhr_5fpos_101',['DAC_DHR8R2_DACC2DHR_Pos',['../group___peripheral___registers___bits___definition.html#ga4a8082de99f7eef453237a409763718b',1,'stm32f407xx_matlab.h']]], - ['dac_5fdhr8rd_5fdacc1dhr_102',['DAC_DHR8RD_DACC1DHR',['../group___peripheral___registers___bits___definition.html#ga9aee01ad181fa5b541864ed62907d70d',1,'stm32f407xx_matlab.h']]], - ['dac_5fdhr8rd_5fdacc1dhr_5fmsk_103',['DAC_DHR8RD_DACC1DHR_Msk',['../group___peripheral___registers___bits___definition.html#gae1b85c14a79ef230c7771336ab683678',1,'stm32f407xx_matlab.h']]], - ['dac_5fdhr8rd_5fdacc1dhr_5fpos_104',['DAC_DHR8RD_DACC1DHR_Pos',['../group___peripheral___registers___bits___definition.html#gac004fb7fdc93225fb835b27e39229a57',1,'stm32f407xx_matlab.h']]], - ['dac_5fdhr8rd_5fdacc2dhr_105',['DAC_DHR8RD_DACC2DHR',['../group___peripheral___registers___bits___definition.html#gae31631eaac76ebecb059918c351ef3c9',1,'stm32f407xx_matlab.h']]], - ['dac_5fdhr8rd_5fdacc2dhr_5fmsk_106',['DAC_DHR8RD_DACC2DHR_Msk',['../group___peripheral___registers___bits___definition.html#ga3520456f0013e51d3d2c3694d86488b6',1,'stm32f407xx_matlab.h']]], - ['dac_5fdhr8rd_5fdacc2dhr_5fpos_107',['DAC_DHR8RD_DACC2DHR_Pos',['../group___peripheral___registers___bits___definition.html#gabf849d0278349997f891d987def91224',1,'stm32f407xx_matlab.h']]], - ['dac_5fdor1_5fdacc1dor_108',['DAC_DOR1_DACC1DOR',['../group___peripheral___registers___bits___definition.html#ga5b4192938e039dc25a7df8fcc5f3932a',1,'stm32f407xx_matlab.h']]], - ['dac_5fdor1_5fdacc1dor_5fmsk_109',['DAC_DOR1_DACC1DOR_Msk',['../group___peripheral___registers___bits___definition.html#gae11b4b811ab6ba4e981ee60318f7d1a4',1,'stm32f407xx_matlab.h']]], - ['dac_5fdor1_5fdacc1dor_5fpos_110',['DAC_DOR1_DACC1DOR_Pos',['../group___peripheral___registers___bits___definition.html#gaacef98a0af264fa6b23a187e74d7c82d',1,'stm32f407xx_matlab.h']]], - ['dac_5fdor2_5fdacc2dor_111',['DAC_DOR2_DACC2DOR',['../group___peripheral___registers___bits___definition.html#gacaaa39c1e82279918918b072fd56db04',1,'stm32f407xx_matlab.h']]], - ['dac_5fdor2_5fdacc2dor_5fmsk_112',['DAC_DOR2_DACC2DOR_Msk',['../group___peripheral___registers___bits___definition.html#ga4a6d4d4b3b48221d195a3acb51ad6fbe',1,'stm32f407xx_matlab.h']]], - ['dac_5fdor2_5fdacc2dor_5fpos_113',['DAC_DOR2_DACC2DOR_Pos',['../group___peripheral___registers___bits___definition.html#ga17aa70d42a524b2dd911326fa65630f1',1,'stm32f407xx_matlab.h']]], - ['dac_5fsr_5fdmaudr1_114',['DAC_SR_DMAUDR1',['../group___peripheral___registers___bits___definition.html#ga7d2048d6b521fb0946dc8c4e577a49c0',1,'stm32f407xx_matlab.h']]], - ['dac_5fsr_5fdmaudr1_5fmsk_115',['DAC_SR_DMAUDR1_Msk',['../group___peripheral___registers___bits___definition.html#ga75ded00bd7866ed6e38c52beb4854d64',1,'stm32f407xx_matlab.h']]], - ['dac_5fsr_5fdmaudr1_5fpos_116',['DAC_SR_DMAUDR1_Pos',['../group___peripheral___registers___bits___definition.html#gadeeefee596334ca7c00e9dfa12cfdd83',1,'stm32f407xx_matlab.h']]], - ['dac_5fsr_5fdmaudr2_117',['DAC_SR_DMAUDR2',['../group___peripheral___registers___bits___definition.html#gaf16e48ab85d9261c5b599c56b14aea5d',1,'stm32f407xx_matlab.h']]], - ['dac_5fsr_5fdmaudr2_5fmsk_118',['DAC_SR_DMAUDR2_Msk',['../group___peripheral___registers___bits___definition.html#gaccadc59668f44b530b866ebcce6f0c74',1,'stm32f407xx_matlab.h']]], - ['dac_5fsr_5fdmaudr2_5fpos_119',['DAC_SR_DMAUDR2_Pos',['../group___peripheral___registers___bits___definition.html#gaa918fd0130e9edc2b4a21ff4ba17aa5e',1,'stm32f407xx_matlab.h']]], - ['dac_5fswtrigr_5fswtrig1_120',['DAC_SWTRIGR_SWTRIG1',['../group___peripheral___registers___bits___definition.html#ga970ef02dffaceb35ff1dd7aceb67acdd',1,'stm32f407xx_matlab.h']]], - ['dac_5fswtrigr_5fswtrig1_5fmsk_121',['DAC_SWTRIGR_SWTRIG1_Msk',['../group___peripheral___registers___bits___definition.html#ga819696c72cca7dd861aa7a3d9081e425',1,'stm32f407xx_matlab.h']]], - ['dac_5fswtrigr_5fswtrig1_5fpos_122',['DAC_SWTRIGR_SWTRIG1_Pos',['../group___peripheral___registers___bits___definition.html#ga32d8b5dafe7a5f4963e5f12656e48ee1',1,'stm32f407xx_matlab.h']]], - ['dac_5fswtrigr_5fswtrig2_123',['DAC_SWTRIGR_SWTRIG2',['../group___peripheral___registers___bits___definition.html#gaf0e53585b505d21f5c457476bd5a18f8',1,'stm32f407xx_matlab.h']]], - ['dac_5fswtrigr_5fswtrig2_5fmsk_124',['DAC_SWTRIGR_SWTRIG2_Msk',['../group___peripheral___registers___bits___definition.html#ga107859f1c6bd2dc30bf632941121bb05',1,'stm32f407xx_matlab.h']]], - ['dac_5fswtrigr_5fswtrig2_5fpos_125',['DAC_SWTRIGR_SWTRIG2_Pos',['../group___peripheral___registers___bits___definition.html#gadb85dac71ddd76ce877fad49a47634b5',1,'stm32f407xx_matlab.h']]], - ['dac_5ftypedef_126',['DAC_TypeDef',['../struct_d_a_c___type_def.html',1,'']]], - ['daint_127',['DAINT',['../group___c_m_s_i_s___device.html#ga4e15c273373694f64b3f70226cb3ac35',1,'USB_OTG_DeviceTypeDef']]], - ['daintmsk_128',['DAINTMSK',['../group___c_m_s_i_s___device.html#ga2c8f65655aa14ec9ba63c9d0655223ec',1,'USB_OTG_DeviceTypeDef']]], - ['data_20watchpoint_20and_20trace_20dwt_129',['Data Watchpoint and Trace (DWT)',['../group___c_m_s_i_s___d_w_t.html',1,'']]], - ['dbgmcu_130',['DBGMCU',['../group___peripheral__declaration.html#ga92ec6d9ec2251fda7d4ce09748cd74b4',1,'stm32f407xx_matlab.h']]], - ['dbgmcu_131',['dbgmcu',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#gacecf2f30be3d1243af9c27921727cb3d',1,'stm32f4xx_periph_registers.c']]], - ['dbgmcu_5fapb1_5ffz_5fdbg_5fcan1_5fstop_132',['DBGMCU_APB1_FZ_DBG_CAN1_STOP',['../group___peripheral___registers___bits___definition.html#ga1b404dcea4857bccabbb03d6cce6be8c',1,'stm32f407xx_matlab.h']]], - ['dbgmcu_5fapb1_5ffz_5fdbg_5fcan1_5fstop_5fmsk_133',['DBGMCU_APB1_FZ_DBG_CAN1_STOP_Msk',['../group___peripheral___registers___bits___definition.html#ga72cf0d5d23a0ac36f3c4c5515082221d',1,'stm32f407xx_matlab.h']]], - ['dbgmcu_5fapb1_5ffz_5fdbg_5fcan1_5fstop_5fpos_134',['DBGMCU_APB1_FZ_DBG_CAN1_STOP_Pos',['../group___peripheral___registers___bits___definition.html#gaf44a606db87b49504fc17760eba9290d',1,'stm32f407xx_matlab.h']]], - ['dbgmcu_5fapb1_5ffz_5fdbg_5fcan2_5fstop_135',['DBGMCU_APB1_FZ_DBG_CAN2_STOP',['../group___peripheral___registers___bits___definition.html#gaadc3889d6b84d143c98ecbfd873a9a1a',1,'stm32f407xx_matlab.h']]], - ['dbgmcu_5fapb1_5ffz_5fdbg_5fcan2_5fstop_5fmsk_136',['DBGMCU_APB1_FZ_DBG_CAN2_STOP_Msk',['../group___peripheral___registers___bits___definition.html#gaf6c0ae534d156b18cd9254ab942f88ff',1,'stm32f407xx_matlab.h']]], - ['dbgmcu_5fapb1_5ffz_5fdbg_5fcan2_5fstop_5fpos_137',['DBGMCU_APB1_FZ_DBG_CAN2_STOP_Pos',['../group___peripheral___registers___bits___definition.html#gac38ce10efced0708fe63650e0f855c3d',1,'stm32f407xx_matlab.h']]], - ['dbgmcu_5fapb1_5ffz_5fdbg_5fi2c1_5fsmbus_5ftimeout_138',['DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT',['../group___peripheral___registers___bits___definition.html#gae83fb5d62c6e6fa1c2fd06084528404e',1,'stm32f407xx_matlab.h']]], - ['dbgmcu_5fapb1_5ffz_5fdbg_5fi2c1_5fsmbus_5ftimeout_5fmsk_139',['DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk',['../group___peripheral___registers___bits___definition.html#ga202de646d5890eec98b04ad2be808604',1,'stm32f407xx_matlab.h']]], - ['dbgmcu_5fapb1_5ffz_5fdbg_5fi2c1_5fsmbus_5ftimeout_5fpos_140',['DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos',['../group___peripheral___registers___bits___definition.html#ga303e9dea0617bb3f03a8cc825005d6ce',1,'stm32f407xx_matlab.h']]], - ['dbgmcu_5fapb1_5ffz_5fdbg_5fi2c2_5fsmbus_5ftimeout_141',['DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT',['../group___peripheral___registers___bits___definition.html#ga8f6320aba695f6c3f97608e478533e96',1,'stm32f407xx_matlab.h']]], - ['dbgmcu_5fapb1_5ffz_5fdbg_5fi2c2_5fsmbus_5ftimeout_5fmsk_142',['DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk',['../group___peripheral___registers___bits___definition.html#gae03e6603b8d1af65a2b5c026c8379908',1,'stm32f407xx_matlab.h']]], - ['dbgmcu_5fapb1_5ffz_5fdbg_5fi2c2_5fsmbus_5ftimeout_5fpos_143',['DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos',['../group___peripheral___registers___bits___definition.html#gabc66781299067fbbec7d1be708314c17',1,'stm32f407xx_matlab.h']]], - ['dbgmcu_5fapb1_5ffz_5fdbg_5fi2c3_5fsmbus_5ftimeout_144',['DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT',['../group___peripheral___registers___bits___definition.html#ga7f7e5c708387aa1ddae35b892811b4e9',1,'stm32f407xx_matlab.h']]], - ['dbgmcu_5fapb1_5ffz_5fdbg_5fi2c3_5fsmbus_5ftimeout_5fmsk_145',['DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk',['../group___peripheral___registers___bits___definition.html#ga0ebb7cd7e57d8d9888025cfbdea082b4',1,'stm32f407xx_matlab.h']]], - ['dbgmcu_5fapb1_5ffz_5fdbg_5fi2c3_5fsmbus_5ftimeout_5fpos_146',['DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos',['../group___peripheral___registers___bits___definition.html#ga0c17ca25c071d846eeecdc761f590bf0',1,'stm32f407xx_matlab.h']]], - ['dbgmcu_5fapb1_5ffz_5fdbg_5fiwdeg_5fstop_147',['DBGMCU_APB1_FZ_DBG_IWDEG_STOP',['../group___peripheral___registers___bits___definition.html#gabe48f858edb831fbcb8769421df7d8e9',1,'stm32f407xx_matlab.h']]], - ['dbgmcu_5fapb1_5ffz_5fdbg_5fiwdg_5fstop_148',['DBGMCU_APB1_FZ_DBG_IWDG_STOP',['../group___peripheral___registers___bits___definition.html#gada8989cb96dd5d6dbdaaf16e1f127c6a',1,'stm32f407xx_matlab.h']]], - ['dbgmcu_5fapb1_5ffz_5fdbg_5fiwdg_5fstop_5fmsk_149',['DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk',['../group___peripheral___registers___bits___definition.html#ga9a7937e3a29764f7e80895b8fbe81baa',1,'stm32f407xx_matlab.h']]], - ['dbgmcu_5fapb1_5ffz_5fdbg_5fiwdg_5fstop_5fpos_150',['DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos',['../group___peripheral___registers___bits___definition.html#ga3bb0a55a4b7c9c3deeb61568b9c7e85c',1,'stm32f407xx_matlab.h']]], - ['dbgmcu_5fapb1_5ffz_5fdbg_5frtc_5fstop_151',['DBGMCU_APB1_FZ_DBG_RTC_STOP',['../group___peripheral___registers___bits___definition.html#ga1e20246d389229ff46006b405bb56b1d',1,'stm32f407xx_matlab.h']]], - ['dbgmcu_5fapb1_5ffz_5fdbg_5frtc_5fstop_5fmsk_152',['DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk',['../group___peripheral___registers___bits___definition.html#gaf7fefeace05cb28675d23037f7b3966a',1,'stm32f407xx_matlab.h']]], - ['dbgmcu_5fapb1_5ffz_5fdbg_5frtc_5fstop_5fpos_153',['DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos',['../group___peripheral___registers___bits___definition.html#ga004684cb88ffb723509a9ca4193e78ec',1,'stm32f407xx_matlab.h']]], - ['dbgmcu_5fapb1_5ffz_5fdbg_5ftim12_5fstop_154',['DBGMCU_APB1_FZ_DBG_TIM12_STOP',['../group___peripheral___registers___bits___definition.html#ga7ca0e04ad8c94e5b7fe29d8b9c20ebff',1,'stm32f407xx_matlab.h']]], - ['dbgmcu_5fapb1_5ffz_5fdbg_5ftim12_5fstop_5fmsk_155',['DBGMCU_APB1_FZ_DBG_TIM12_STOP_Msk',['../group___peripheral___registers___bits___definition.html#gadfcabcb2e0efbe9e76b3eae58b30943b',1,'stm32f407xx_matlab.h']]], - ['dbgmcu_5fapb1_5ffz_5fdbg_5ftim12_5fstop_5fpos_156',['DBGMCU_APB1_FZ_DBG_TIM12_STOP_Pos',['../group___peripheral___registers___bits___definition.html#ga9db1b0c37f083a12d94bbf6beeb4516e',1,'stm32f407xx_matlab.h']]], - ['dbgmcu_5fapb1_5ffz_5fdbg_5ftim13_5fstop_157',['DBGMCU_APB1_FZ_DBG_TIM13_STOP',['../group___peripheral___registers___bits___definition.html#ga68ef63b3c086ede54396596798553299',1,'stm32f407xx_matlab.h']]], - ['dbgmcu_5fapb1_5ffz_5fdbg_5ftim13_5fstop_5fmsk_158',['DBGMCU_APB1_FZ_DBG_TIM13_STOP_Msk',['../group___peripheral___registers___bits___definition.html#ga8e25332c23efcacd48317de37e337af6',1,'stm32f407xx_matlab.h']]], - ['dbgmcu_5fapb1_5ffz_5fdbg_5ftim13_5fstop_5fpos_159',['DBGMCU_APB1_FZ_DBG_TIM13_STOP_Pos',['../group___peripheral___registers___bits___definition.html#gab27cca037c1de40bf8855316c266abd2',1,'stm32f407xx_matlab.h']]], - ['dbgmcu_5fapb1_5ffz_5fdbg_5ftim14_5fstop_160',['DBGMCU_APB1_FZ_DBG_TIM14_STOP',['../group___peripheral___registers___bits___definition.html#gafd3acb3e632c74e326da7016073c7871',1,'stm32f407xx_matlab.h']]], - ['dbgmcu_5fapb1_5ffz_5fdbg_5ftim14_5fstop_5fmsk_161',['DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk',['../group___peripheral___registers___bits___definition.html#gaeec836ee0ced45ad06aa4b025f13987e',1,'stm32f407xx_matlab.h']]], - ['dbgmcu_5fapb1_5ffz_5fdbg_5ftim14_5fstop_5fpos_162',['DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos',['../group___peripheral___registers___bits___definition.html#gaf940f736a0f2e4531d141e53257e4e6d',1,'stm32f407xx_matlab.h']]], - ['dbgmcu_5fapb1_5ffz_5fdbg_5ftim2_5fstop_163',['DBGMCU_APB1_FZ_DBG_TIM2_STOP',['../group___peripheral___registers___bits___definition.html#gaae3c5b87084934a18748f5ec168f5aef',1,'stm32f407xx_matlab.h']]], - ['dbgmcu_5fapb1_5ffz_5fdbg_5ftim2_5fstop_5fmsk_164',['DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk',['../group___peripheral___registers___bits___definition.html#gaf96a2b1fb00169f78d3c8fb050ca35be',1,'stm32f407xx_matlab.h']]], - ['dbgmcu_5fapb1_5ffz_5fdbg_5ftim2_5fstop_5fpos_165',['DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos',['../group___peripheral___registers___bits___definition.html#gad1de6489ecedec59891894a54458bef2',1,'stm32f407xx_matlab.h']]], - ['dbgmcu_5fapb1_5ffz_5fdbg_5ftim3_5fstop_166',['DBGMCU_APB1_FZ_DBG_TIM3_STOP',['../group___peripheral___registers___bits___definition.html#ga2fea6834f4ef9fc6b403cd079a001cec',1,'stm32f407xx_matlab.h']]], - ['dbgmcu_5fapb1_5ffz_5fdbg_5ftim3_5fstop_5fmsk_167',['DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk',['../group___peripheral___registers___bits___definition.html#gaab210ab764b68711904243c0d11631b8',1,'stm32f407xx_matlab.h']]], - ['dbgmcu_5fapb1_5ffz_5fdbg_5ftim3_5fstop_5fpos_168',['DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos',['../group___peripheral___registers___bits___definition.html#ga3bd5fd9c34fd75ddb5c77d526f8f53a1',1,'stm32f407xx_matlab.h']]], - ['dbgmcu_5fapb1_5ffz_5fdbg_5ftim4_5fstop_169',['DBGMCU_APB1_FZ_DBG_TIM4_STOP',['../group___peripheral___registers___bits___definition.html#ga7ac65bf9342bb8acbcb25938e93abc45',1,'stm32f407xx_matlab.h']]], - ['dbgmcu_5fapb1_5ffz_5fdbg_5ftim4_5fstop_5fmsk_170',['DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk',['../group___peripheral___registers___bits___definition.html#gaa7dfb56349db84ef1ef5753e13cf2f48',1,'stm32f407xx_matlab.h']]], - ['dbgmcu_5fapb1_5ffz_5fdbg_5ftim4_5fstop_5fpos_171',['DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos',['../group___peripheral___registers___bits___definition.html#gaeef66d67708ae915fbbc2ee76aeaef3e',1,'stm32f407xx_matlab.h']]], - ['dbgmcu_5fapb1_5ffz_5fdbg_5ftim5_5fstop_172',['DBGMCU_APB1_FZ_DBG_TIM5_STOP',['../group___peripheral___registers___bits___definition.html#ga42d29d40515d36ce6ed7e5d34ed17dcf',1,'stm32f407xx_matlab.h']]], - ['dbgmcu_5fapb1_5ffz_5fdbg_5ftim5_5fstop_5fmsk_173',['DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk',['../group___peripheral___registers___bits___definition.html#gac4e288f717db03126942d03a1a6fafd8',1,'stm32f407xx_matlab.h']]], - ['dbgmcu_5fapb1_5ffz_5fdbg_5ftim5_5fstop_5fpos_174',['DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos',['../group___peripheral___registers___bits___definition.html#ga5218cc7d400bfb220c42a80b3a2a0603',1,'stm32f407xx_matlab.h']]], - ['dbgmcu_5fapb1_5ffz_5fdbg_5ftim6_5fstop_175',['DBGMCU_APB1_FZ_DBG_TIM6_STOP',['../group___peripheral___registers___bits___definition.html#gadea6a1e90739bcf1d0723a0566c66de7',1,'stm32f407xx_matlab.h']]], - ['dbgmcu_5fapb1_5ffz_5fdbg_5ftim6_5fstop_5fmsk_176',['DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk',['../group___peripheral___registers___bits___definition.html#gae3215a197f13b82287892283886326d1',1,'stm32f407xx_matlab.h']]], - ['dbgmcu_5fapb1_5ffz_5fdbg_5ftim6_5fstop_5fpos_177',['DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos',['../group___peripheral___registers___bits___definition.html#gaf603706e632bf2df878b8ba6fc0c4736',1,'stm32f407xx_matlab.h']]], - ['dbgmcu_5fapb1_5ffz_5fdbg_5ftim7_5fstop_178',['DBGMCU_APB1_FZ_DBG_TIM7_STOP',['../group___peripheral___registers___bits___definition.html#gafdade78c3d28a668f9826d0b72e5844b',1,'stm32f407xx_matlab.h']]], - ['dbgmcu_5fapb1_5ffz_5fdbg_5ftim7_5fstop_5fmsk_179',['DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk',['../group___peripheral___registers___bits___definition.html#ga29df0ea459e1900942f3e26141e0f9dd',1,'stm32f407xx_matlab.h']]], - ['dbgmcu_5fapb1_5ffz_5fdbg_5ftim7_5fstop_5fpos_180',['DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos',['../group___peripheral___registers___bits___definition.html#gab8568c72922b902663a7ade0e9d6cb88',1,'stm32f407xx_matlab.h']]], - ['dbgmcu_5fapb1_5ffz_5fdbg_5fwwdg_5fstop_181',['DBGMCU_APB1_FZ_DBG_WWDG_STOP',['../group___peripheral___registers___bits___definition.html#ga8a49d5e849185d09ee6c7594512ffe88',1,'stm32f407xx_matlab.h']]], - ['dbgmcu_5fapb1_5ffz_5fdbg_5fwwdg_5fstop_5fmsk_182',['DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk',['../group___peripheral___registers___bits___definition.html#ga0f24695b718a52f4a91297ee3c512db4',1,'stm32f407xx_matlab.h']]], - ['dbgmcu_5fapb1_5ffz_5fdbg_5fwwdg_5fstop_5fpos_183',['DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos',['../group___peripheral___registers___bits___definition.html#gaaad459d6930c29babb7672cd26d0ea9b',1,'stm32f407xx_matlab.h']]], - ['dbgmcu_5fapb2_5ffz_5fdbg_5ftim10_5fstop_184',['DBGMCU_APB2_FZ_DBG_TIM10_STOP',['../group___peripheral___registers___bits___definition.html#ga24d4bbf803a65e8202b0019ed0ce0ebb',1,'stm32f407xx_matlab.h']]], - ['dbgmcu_5fapb2_5ffz_5fdbg_5ftim10_5fstop_5fmsk_185',['DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk',['../group___peripheral___registers___bits___definition.html#ga9390f2c13a5b525bd1e7bbd6501c7a67',1,'stm32f407xx_matlab.h']]], - ['dbgmcu_5fapb2_5ffz_5fdbg_5ftim10_5fstop_5fpos_186',['DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos',['../group___peripheral___registers___bits___definition.html#ga2eb21a02384033248b1e45030a314598',1,'stm32f407xx_matlab.h']]], - ['dbgmcu_5fapb2_5ffz_5fdbg_5ftim11_5fstop_187',['DBGMCU_APB2_FZ_DBG_TIM11_STOP',['../group___peripheral___registers___bits___definition.html#ga354671c942db40e69820fd783ef955b4',1,'stm32f407xx_matlab.h']]], - ['dbgmcu_5fapb2_5ffz_5fdbg_5ftim11_5fstop_5fmsk_188',['DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk',['../group___peripheral___registers___bits___definition.html#gaea914b4c8a46cb0be4909dfd4e3199d6',1,'stm32f407xx_matlab.h']]], - ['dbgmcu_5fapb2_5ffz_5fdbg_5ftim11_5fstop_5fpos_189',['DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos',['../group___peripheral___registers___bits___definition.html#ga0dd5b307e8d9992857942180b6f7358f',1,'stm32f407xx_matlab.h']]], - ['dbgmcu_5fapb2_5ffz_5fdbg_5ftim1_5fstop_190',['DBGMCU_APB2_FZ_DBG_TIM1_STOP',['../group___peripheral___registers___bits___definition.html#ga3eb7be194b6ffb258b9e9f5ed08a931e',1,'stm32f407xx_matlab.h']]], - ['dbgmcu_5fapb2_5ffz_5fdbg_5ftim1_5fstop_5fmsk_191',['DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk',['../group___peripheral___registers___bits___definition.html#ga74cb9644d7d1eaf1a71254121f926169',1,'stm32f407xx_matlab.h']]], - ['dbgmcu_5fapb2_5ffz_5fdbg_5ftim1_5fstop_5fpos_192',['DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos',['../group___peripheral___registers___bits___definition.html#ga2b30844d430324cfe63e4932275a6978',1,'stm32f407xx_matlab.h']]], - ['dbgmcu_5fapb2_5ffz_5fdbg_5ftim8_5fstop_193',['DBGMCU_APB2_FZ_DBG_TIM8_STOP',['../group___peripheral___registers___bits___definition.html#ga37128bf689254919b07f64ee41cad1cf',1,'stm32f407xx_matlab.h']]], - ['dbgmcu_5fapb2_5ffz_5fdbg_5ftim8_5fstop_5fmsk_194',['DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk',['../group___peripheral___registers___bits___definition.html#ga98002708ee350ecf61a72911df9850b5',1,'stm32f407xx_matlab.h']]], - ['dbgmcu_5fapb2_5ffz_5fdbg_5ftim8_5fstop_5fpos_195',['DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos',['../group___peripheral___registers___bits___definition.html#gac84a0fb177332acd69c944aa00e90340',1,'stm32f407xx_matlab.h']]], - ['dbgmcu_5fapb2_5ffz_5fdbg_5ftim9_5fstop_196',['DBGMCU_APB2_FZ_DBG_TIM9_STOP',['../group___peripheral___registers___bits___definition.html#gaf12c17533a1e3262ee11f760e44f5127',1,'stm32f407xx_matlab.h']]], - ['dbgmcu_5fapb2_5ffz_5fdbg_5ftim9_5fstop_5fmsk_197',['DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk',['../group___peripheral___registers___bits___definition.html#ga983432f2957617c4215fe406dd932080',1,'stm32f407xx_matlab.h']]], - ['dbgmcu_5fapb2_5ffz_5fdbg_5ftim9_5fstop_5fpos_198',['DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos',['../group___peripheral___registers___bits___definition.html#gaa6fc3b8c8d5cbb8695e7cec3153bbe65',1,'stm32f407xx_matlab.h']]], - ['dbgmcu_5fbase_199',['DBGMCU_BASE',['../group___peripheral__memory__map.html#ga4adaf4fd82ccc3a538f1f27a70cdbbef',1,'stm32f407xx_matlab.h']]], - ['dbgmcu_5fcr_5fdbg_5fsleep_200',['DBGMCU_CR_DBG_SLEEP',['../group___peripheral___registers___bits___definition.html#ga037c80fe1d7308cee68245715ef6cd9a',1,'stm32f407xx_matlab.h']]], - ['dbgmcu_5fcr_5fdbg_5fsleep_5fmsk_201',['DBGMCU_CR_DBG_SLEEP_Msk',['../group___peripheral___registers___bits___definition.html#ga127e0531bc305bb460fd2417106bee61',1,'stm32f407xx_matlab.h']]], - ['dbgmcu_5fcr_5fdbg_5fsleep_5fpos_202',['DBGMCU_CR_DBG_SLEEP_Pos',['../group___peripheral___registers___bits___definition.html#ga3b996a2be01fbeeaa868603c7bca6044',1,'stm32f407xx_matlab.h']]], - ['dbgmcu_5fcr_5fdbg_5fstandby_203',['DBGMCU_CR_DBG_STANDBY',['../group___peripheral___registers___bits___definition.html#ga107a9396d63c892a8e614897c9d0b132',1,'stm32f407xx_matlab.h']]], - ['dbgmcu_5fcr_5fdbg_5fstandby_5fmsk_204',['DBGMCU_CR_DBG_STANDBY_Msk',['../group___peripheral___registers___bits___definition.html#ga52e9a797b04f9577456af2499f5bd9ff',1,'stm32f407xx_matlab.h']]], - ['dbgmcu_5fcr_5fdbg_5fstandby_5fpos_205',['DBGMCU_CR_DBG_STANDBY_Pos',['../group___peripheral___registers___bits___definition.html#ga74521b2e06cd16f46ea5987d82f9ff19',1,'stm32f407xx_matlab.h']]], - ['dbgmcu_5fcr_5fdbg_5fstop_206',['DBGMCU_CR_DBG_STOP',['../group___peripheral___registers___bits___definition.html#gaf511f21a8de5b0b66c862915eee8bf75',1,'stm32f407xx_matlab.h']]], - ['dbgmcu_5fcr_5fdbg_5fstop_5fmsk_207',['DBGMCU_CR_DBG_STOP_Msk',['../group___peripheral___registers___bits___definition.html#ga71cd122085cdadba462f9e251ac35349',1,'stm32f407xx_matlab.h']]], - ['dbgmcu_5fcr_5fdbg_5fstop_5fpos_208',['DBGMCU_CR_DBG_STOP_Pos',['../group___peripheral___registers___bits___definition.html#ga998b25ffd43297001c2f20ebb04fbcc9',1,'stm32f407xx_matlab.h']]], - ['dbgmcu_5fcr_5ftrace_5fioen_209',['DBGMCU_CR_TRACE_IOEN',['../group___peripheral___registers___bits___definition.html#ga9034b6eb9d4dceadffc6a1d1959056c9',1,'stm32f407xx_matlab.h']]], - ['dbgmcu_5fcr_5ftrace_5fioen_5fmsk_210',['DBGMCU_CR_TRACE_IOEN_Msk',['../group___peripheral___registers___bits___definition.html#ga18007dc2c11d41a5dc449e37cb8c0c56',1,'stm32f407xx_matlab.h']]], - ['dbgmcu_5fcr_5ftrace_5fioen_5fpos_211',['DBGMCU_CR_TRACE_IOEN_Pos',['../group___peripheral___registers___bits___definition.html#ga2be1af4b18b8c9ce4001dd363e6626e7',1,'stm32f407xx_matlab.h']]], - ['dbgmcu_5fcr_5ftrace_5fmode_212',['DBGMCU_CR_TRACE_MODE',['../group___peripheral___registers___bits___definition.html#gaa1395189e10bdbc37bce9ea480e22d10',1,'stm32f407xx_matlab.h']]], - ['dbgmcu_5fcr_5ftrace_5fmode_5f0_213',['DBGMCU_CR_TRACE_MODE_0',['../group___peripheral___registers___bits___definition.html#ga2d41a4027853783633d929a43f8d6d85',1,'stm32f407xx_matlab.h']]], - ['dbgmcu_5fcr_5ftrace_5fmode_5f1_214',['DBGMCU_CR_TRACE_MODE_1',['../group___peripheral___registers___bits___definition.html#ga7ba3a830051b53d43d850768242c503e',1,'stm32f407xx_matlab.h']]], - ['dbgmcu_5fcr_5ftrace_5fmode_5fmsk_215',['DBGMCU_CR_TRACE_MODE_Msk',['../group___peripheral___registers___bits___definition.html#gad641a08b344645d47a0789ffa25d7079',1,'stm32f407xx_matlab.h']]], - ['dbgmcu_5fcr_5ftrace_5fmode_5fpos_216',['DBGMCU_CR_TRACE_MODE_Pos',['../group___peripheral___registers___bits___definition.html#ga20dddffa934315ca4a5902cbf45f4d93',1,'stm32f407xx_matlab.h']]], - ['dbgmcu_5fidcode_5fdev_5fid_217',['DBGMCU_IDCODE_DEV_ID',['../group___peripheral___registers___bits___definition.html#gafd961fcddc40341a817a9ec85b7c80ac',1,'stm32f407xx_matlab.h']]], - ['dbgmcu_5fidcode_5fdev_5fid_5fmsk_218',['DBGMCU_IDCODE_DEV_ID_Msk',['../group___peripheral___registers___bits___definition.html#gabf18661126fecb64b8c7d7d4e590fb33',1,'stm32f407xx_matlab.h']]], - ['dbgmcu_5fidcode_5fdev_5fid_5fpos_219',['DBGMCU_IDCODE_DEV_ID_Pos',['../group___peripheral___registers___bits___definition.html#gad05a229877e557798dfbabe7188d7a54',1,'stm32f407xx_matlab.h']]], - ['dbgmcu_5fidcode_5frev_5fid_220',['DBGMCU_IDCODE_REV_ID',['../group___peripheral___registers___bits___definition.html#ga887eb26364a8693355024ca203323165',1,'stm32f407xx_matlab.h']]], - ['dbgmcu_5fidcode_5frev_5fid_5fmsk_221',['DBGMCU_IDCODE_REV_ID_Msk',['../group___peripheral___registers___bits___definition.html#ga0d92c620aed9b19c7e8d9d12f743b258',1,'stm32f407xx_matlab.h']]], - ['dbgmcu_5fidcode_5frev_5fid_5fpos_222',['DBGMCU_IDCODE_REV_ID_Pos',['../group___peripheral___registers___bits___definition.html#ga6e98f7579d16c36cbf6a09b04f2ee170',1,'stm32f407xx_matlab.h']]], - ['dbgmcu_5ftypedef_223',['DBGMCU_TypeDef',['../struct_d_b_g_m_c_u___type_def.html',1,'']]], - ['dcfg_224',['DCFG',['../group___c_m_s_i_s___device.html#ga9a163a0d5cfce7238b38067a1a53b324',1,'USB_OTG_DeviceTypeDef']]], - ['dcmi_225',['DCMI',['../group___peripheral__declaration.html#ga049d9f61cb078d642e68f3c22bb6d90c',1,'stm32f407xx_matlab.h']]], - ['dcmi_226',['dcmi',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga7acb73c38792037a032e8a1a05247546',1,'stm32f4xx_periph_registers.c']]], - ['dcmi_5fbase_227',['DCMI_BASE',['../group___peripheral__memory__map.html#ga55b794507e021135486de57129a2505c',1,'stm32f407xx_matlab.h']]], - ['dcmi_5fcr_5fcapture_228',['DCMI_CR_CAPTURE',['../group___peripheral___registers___bits___definition.html#ga7f8b54f16f7e17b3da807b6dae1d649e',1,'stm32f407xx_matlab.h']]], - ['dcmi_5fcr_5fcapture_5fmsk_229',['DCMI_CR_CAPTURE_Msk',['../group___peripheral___registers___bits___definition.html#ga15f2c325d001c3d3d5a1939106584fb3',1,'stm32f407xx_matlab.h']]], - ['dcmi_5fcr_5fcapture_5fpos_230',['DCMI_CR_CAPTURE_Pos',['../group___peripheral___registers___bits___definition.html#gafa3a454c9236fd257a8bfb17071637dc',1,'stm32f407xx_matlab.h']]], - ['dcmi_5fcr_5fcm_231',['DCMI_CR_CM',['../group___peripheral___registers___bits___definition.html#ga47bacab13c750dc0ecc9aaf935d1f435',1,'stm32f407xx_matlab.h']]], - ['dcmi_5fcr_5fcm_5fmsk_232',['DCMI_CR_CM_Msk',['../group___peripheral___registers___bits___definition.html#gaa9213d50a3270e1e2df73b73a97300b0',1,'stm32f407xx_matlab.h']]], - ['dcmi_5fcr_5fcm_5fpos_233',['DCMI_CR_CM_Pos',['../group___peripheral___registers___bits___definition.html#gade41604d334508afeb14b82e21f421be',1,'stm32f407xx_matlab.h']]], - ['dcmi_5fcr_5fcre_234',['DCMI_CR_CRE',['../group___peripheral___registers___bits___definition.html#ga79e4190a772dc07958573a110106db69',1,'stm32f407xx_matlab.h']]], - ['dcmi_5fcr_5fcre_5fmsk_235',['DCMI_CR_CRE_Msk',['../group___peripheral___registers___bits___definition.html#ga3810273d9f0eeae0f5b8e3d3b5a14b3a',1,'stm32f407xx_matlab.h']]], - ['dcmi_5fcr_5fcre_5fpos_236',['DCMI_CR_CRE_Pos',['../group___peripheral___registers___bits___definition.html#ga57ff97d20c4f41748dda19d71f7da8d9',1,'stm32f407xx_matlab.h']]], - ['dcmi_5fcr_5fcrop_237',['DCMI_CR_CROP',['../group___peripheral___registers___bits___definition.html#ga5bb929e7d3b4ea62e80ba66c7bc5c216',1,'stm32f407xx_matlab.h']]], - ['dcmi_5fcr_5fcrop_5fmsk_238',['DCMI_CR_CROP_Msk',['../group___peripheral___registers___bits___definition.html#ga45cccbefdbcefa8f1b4effbd30e4fd57',1,'stm32f407xx_matlab.h']]], - ['dcmi_5fcr_5fcrop_5fpos_239',['DCMI_CR_CROP_Pos',['../group___peripheral___registers___bits___definition.html#ga6cd43899ca78a773ae0132b07b795b73',1,'stm32f407xx_matlab.h']]], - ['dcmi_5fcr_5fedm_5f0_240',['DCMI_CR_EDM_0',['../group___peripheral___registers___bits___definition.html#ga9efa61252be662ff473d14156f09d32c',1,'stm32f407xx_matlab.h']]], - ['dcmi_5fcr_5fedm_5f1_241',['DCMI_CR_EDM_1',['../group___peripheral___registers___bits___definition.html#ga884b51a3e5bf0d615944f46b1751a97c',1,'stm32f407xx_matlab.h']]], - ['dcmi_5fcr_5fenable_242',['DCMI_CR_ENABLE',['../group___peripheral___registers___bits___definition.html#ga1fa2461ca2f0629c2ddd77fea94bbd06',1,'stm32f407xx_matlab.h']]], - ['dcmi_5fcr_5fenable_5fmsk_243',['DCMI_CR_ENABLE_Msk',['../group___peripheral___registers___bits___definition.html#ga38f1b2217a7ae182f5cb6739fd28c0cc',1,'stm32f407xx_matlab.h']]], - ['dcmi_5fcr_5fenable_5fpos_244',['DCMI_CR_ENABLE_Pos',['../group___peripheral___registers___bits___definition.html#gaef22c09278ab657cc3af24dcbff864be',1,'stm32f407xx_matlab.h']]], - ['dcmi_5fcr_5fess_245',['DCMI_CR_ESS',['../group___peripheral___registers___bits___definition.html#ga46851e2b6011a84ecdfc5218a855ad78',1,'stm32f407xx_matlab.h']]], - ['dcmi_5fcr_5fess_5fmsk_246',['DCMI_CR_ESS_Msk',['../group___peripheral___registers___bits___definition.html#gafd4f4d68488cc78decac4e7fe8838655',1,'stm32f407xx_matlab.h']]], - ['dcmi_5fcr_5fess_5fpos_247',['DCMI_CR_ESS_Pos',['../group___peripheral___registers___bits___definition.html#ga02f02e4a058fb7854a3e9c5f79cb6fb3',1,'stm32f407xx_matlab.h']]], - ['dcmi_5fcr_5ffcrc_5f0_248',['DCMI_CR_FCRC_0',['../group___peripheral___registers___bits___definition.html#ga13263970b396f75e00278ff7b78b313d',1,'stm32f407xx_matlab.h']]], - ['dcmi_5fcr_5ffcrc_5f1_249',['DCMI_CR_FCRC_1',['../group___peripheral___registers___bits___definition.html#ga1658bed43e7d0c3579151498104d5747',1,'stm32f407xx_matlab.h']]], - ['dcmi_5fcr_5fhspol_250',['DCMI_CR_HSPOL',['../group___peripheral___registers___bits___definition.html#gac2042d3da2719b7c9c6708e0566e46c5',1,'stm32f407xx_matlab.h']]], - ['dcmi_5fcr_5fhspol_5fmsk_251',['DCMI_CR_HSPOL_Msk',['../group___peripheral___registers___bits___definition.html#ga0c027a03833f80bfddbf2205d092769e',1,'stm32f407xx_matlab.h']]], - ['dcmi_5fcr_5fhspol_5fpos_252',['DCMI_CR_HSPOL_Pos',['../group___peripheral___registers___bits___definition.html#ga0fd28eb0687c6a1704733a53c08dd797',1,'stm32f407xx_matlab.h']]], - ['dcmi_5fcr_5fjpeg_253',['DCMI_CR_JPEG',['../group___peripheral___registers___bits___definition.html#gafd10a1f9c5a588f468e550bb56051b03',1,'stm32f407xx_matlab.h']]], - ['dcmi_5fcr_5fjpeg_5fmsk_254',['DCMI_CR_JPEG_Msk',['../group___peripheral___registers___bits___definition.html#gaef4bc80edc936ebf381a4c2149a9aa9c',1,'stm32f407xx_matlab.h']]], - ['dcmi_5fcr_5fjpeg_5fpos_255',['DCMI_CR_JPEG_Pos',['../group___peripheral___registers___bits___definition.html#gab93600cf87f62ab21c0270966eb49853',1,'stm32f407xx_matlab.h']]], - ['dcmi_5fcr_5fpckpol_256',['DCMI_CR_PCKPOL',['../group___peripheral___registers___bits___definition.html#ga00769f93cbcc2693c8fd42f0e8aa31ad',1,'stm32f407xx_matlab.h']]], - ['dcmi_5fcr_5fpckpol_5fmsk_257',['DCMI_CR_PCKPOL_Msk',['../group___peripheral___registers___bits___definition.html#ga09ec8d81a49c61ae9fd02cc5de658f8c',1,'stm32f407xx_matlab.h']]], - ['dcmi_5fcr_5fpckpol_5fpos_258',['DCMI_CR_PCKPOL_Pos',['../group___peripheral___registers___bits___definition.html#ga3929ea65cd626b5f7d472af5d21f4c1b',1,'stm32f407xx_matlab.h']]], - ['dcmi_5fcr_5fvspol_259',['DCMI_CR_VSPOL',['../group___peripheral___registers___bits___definition.html#ga497c7c4bf6fcc842ffc45eedc876ffdb',1,'stm32f407xx_matlab.h']]], - ['dcmi_5fcr_5fvspol_5fmsk_260',['DCMI_CR_VSPOL_Msk',['../group___peripheral___registers___bits___definition.html#gab3ac7d448956eaddaa8f416598662089',1,'stm32f407xx_matlab.h']]], - ['dcmi_5fcr_5fvspol_5fpos_261',['DCMI_CR_VSPOL_Pos',['../group___peripheral___registers___bits___definition.html#ga2c2656a42de18085bf84a731e82df2a7',1,'stm32f407xx_matlab.h']]], - ['dcmi_5fcwsize_5fcapcnt_262',['DCMI_CWSIZE_CAPCNT',['../group___peripheral___registers___bits___definition.html#ga6c31745cc8efc121ae47c30cc42b384f',1,'stm32f407xx_matlab.h']]], - ['dcmi_5fcwsize_5fcapcnt_5fmsk_263',['DCMI_CWSIZE_CAPCNT_Msk',['../group___peripheral___registers___bits___definition.html#gad530930a69892f9cd7ad4ff52a92b133',1,'stm32f407xx_matlab.h']]], - ['dcmi_5fcwsize_5fcapcnt_5fpos_264',['DCMI_CWSIZE_CAPCNT_Pos',['../group___peripheral___registers___bits___definition.html#ga909bd8775d484d961f2e95e832ccda6d',1,'stm32f407xx_matlab.h']]], - ['dcmi_5fcwsize_5fvline_265',['DCMI_CWSIZE_VLINE',['../group___peripheral___registers___bits___definition.html#ga11c87e423cc974fce1a8a50213e47af8',1,'stm32f407xx_matlab.h']]], - ['dcmi_5fcwsize_5fvline_5fmsk_266',['DCMI_CWSIZE_VLINE_Msk',['../group___peripheral___registers___bits___definition.html#ga628637bf9713da908eca5a53e0f42d4b',1,'stm32f407xx_matlab.h']]], - ['dcmi_5fcwsize_5fvline_5fpos_267',['DCMI_CWSIZE_VLINE_Pos',['../group___peripheral___registers___bits___definition.html#gab47763252d37347f698b9f1d6b459448',1,'stm32f407xx_matlab.h']]], - ['dcmi_5fcwstrt_5fhoffcnt_268',['DCMI_CWSTRT_HOFFCNT',['../group___peripheral___registers___bits___definition.html#gae099a5f83a683df21addd2efd2d9400a',1,'stm32f407xx_matlab.h']]], - ['dcmi_5fcwstrt_5fhoffcnt_5fmsk_269',['DCMI_CWSTRT_HOFFCNT_Msk',['../group___peripheral___registers___bits___definition.html#gaf0fae460ad5a360aada91b734fa3ba57',1,'stm32f407xx_matlab.h']]], - ['dcmi_5fcwstrt_5fhoffcnt_5fpos_270',['DCMI_CWSTRT_HOFFCNT_Pos',['../group___peripheral___registers___bits___definition.html#gad9a493eb26260002c069a0a548cf3fd2',1,'stm32f407xx_matlab.h']]], - ['dcmi_5fcwstrt_5fvst_271',['DCMI_CWSTRT_VST',['../group___peripheral___registers___bits___definition.html#gaf1f7a07e86f5331bd024197bf986f7fb',1,'stm32f407xx_matlab.h']]], - ['dcmi_5fcwstrt_5fvst_5fmsk_272',['DCMI_CWSTRT_VST_Msk',['../group___peripheral___registers___bits___definition.html#gaa1652ad176cc9fbdcec26e5ee24e1f90',1,'stm32f407xx_matlab.h']]], - ['dcmi_5fcwstrt_5fvst_5fpos_273',['DCMI_CWSTRT_VST_Pos',['../group___peripheral___registers___bits___definition.html#gaa4f2d38ccf4538602e4b0fd463d978ae',1,'stm32f407xx_matlab.h']]], - ['dcmi_5fdr_5fbyte0_274',['DCMI_DR_BYTE0',['../group___peripheral___registers___bits___definition.html#gac0910a5a593672f96d201adc561a04b9',1,'stm32f407xx_matlab.h']]], - ['dcmi_5fdr_5fbyte0_5fmsk_275',['DCMI_DR_BYTE0_Msk',['../group___peripheral___registers___bits___definition.html#ga07c270f5e6d112768db06c11b2cc6e56',1,'stm32f407xx_matlab.h']]], - ['dcmi_5fdr_5fbyte0_5fpos_276',['DCMI_DR_BYTE0_Pos',['../group___peripheral___registers___bits___definition.html#gac71db8315705b6ed05cf43460426e159',1,'stm32f407xx_matlab.h']]], - ['dcmi_5fdr_5fbyte1_277',['DCMI_DR_BYTE1',['../group___peripheral___registers___bits___definition.html#gab01aefc5cd095660ac49a2b7b9180c82',1,'stm32f407xx_matlab.h']]], - ['dcmi_5fdr_5fbyte1_5fmsk_278',['DCMI_DR_BYTE1_Msk',['../group___peripheral___registers___bits___definition.html#gab17364d3900caed76aecc643774c54bc',1,'stm32f407xx_matlab.h']]], - ['dcmi_5fdr_5fbyte1_5fpos_279',['DCMI_DR_BYTE1_Pos',['../group___peripheral___registers___bits___definition.html#gad5763f364e81aa40dd960d40ba88fa6a',1,'stm32f407xx_matlab.h']]], - ['dcmi_5fdr_5fbyte2_280',['DCMI_DR_BYTE2',['../group___peripheral___registers___bits___definition.html#gab1bfbeeca97efa76992487f3c22d6aff',1,'stm32f407xx_matlab.h']]], - ['dcmi_5fdr_5fbyte2_5fmsk_281',['DCMI_DR_BYTE2_Msk',['../group___peripheral___registers___bits___definition.html#ga8ee34bf9dabcdca52c0cbf44f25d9c5a',1,'stm32f407xx_matlab.h']]], - ['dcmi_5fdr_5fbyte2_5fpos_282',['DCMI_DR_BYTE2_Pos',['../group___peripheral___registers___bits___definition.html#gafbc045a35af6103ab0f7fc88ff6ba02d',1,'stm32f407xx_matlab.h']]], - ['dcmi_5fdr_5fbyte3_283',['DCMI_DR_BYTE3',['../group___peripheral___registers___bits___definition.html#gaaa63e80a5e9f30b03e3b01b0c597a5cf',1,'stm32f407xx_matlab.h']]], - ['dcmi_5fdr_5fbyte3_5fmsk_284',['DCMI_DR_BYTE3_Msk',['../group___peripheral___registers___bits___definition.html#gaa294b6ac2643ebf5c1492257ad79f45d',1,'stm32f407xx_matlab.h']]], - ['dcmi_5fdr_5fbyte3_5fpos_285',['DCMI_DR_BYTE3_Pos',['../group___peripheral___registers___bits___definition.html#ga2bc8e1dc5f89d3476b28267f4b84a8ce',1,'stm32f407xx_matlab.h']]], - ['dcmi_5fescr_5ffec_286',['DCMI_ESCR_FEC',['../group___peripheral___registers___bits___definition.html#gab398e0b4ccde3ef98da25a420ad0d47d',1,'stm32f407xx_matlab.h']]], - ['dcmi_5fescr_5ffec_5fmsk_287',['DCMI_ESCR_FEC_Msk',['../group___peripheral___registers___bits___definition.html#ga79ae393fc1fb2182bdf482cc4a1f5ff3',1,'stm32f407xx_matlab.h']]], - ['dcmi_5fescr_5ffec_5fpos_288',['DCMI_ESCR_FEC_Pos',['../group___peripheral___registers___bits___definition.html#gac8fa0ea70437313587a37aa718f1b2be',1,'stm32f407xx_matlab.h']]], - ['dcmi_5fescr_5ffsc_289',['DCMI_ESCR_FSC',['../group___peripheral___registers___bits___definition.html#ga822e9340b78048f18504488c6af07b17',1,'stm32f407xx_matlab.h']]], - ['dcmi_5fescr_5ffsc_5fmsk_290',['DCMI_ESCR_FSC_Msk',['../group___peripheral___registers___bits___definition.html#ga3ce58bb8ea8ca57dc51016be5eadb2d6',1,'stm32f407xx_matlab.h']]], - ['dcmi_5fescr_5ffsc_5fpos_291',['DCMI_ESCR_FSC_Pos',['../group___peripheral___registers___bits___definition.html#ga606ebaec78811eb133a2adef912d16ee',1,'stm32f407xx_matlab.h']]], - ['dcmi_5fescr_5flec_292',['DCMI_ESCR_LEC',['../group___peripheral___registers___bits___definition.html#ga174d7f3b7ae442fa4fa8a95bc551d7fe',1,'stm32f407xx_matlab.h']]], - ['dcmi_5fescr_5flec_5fmsk_293',['DCMI_ESCR_LEC_Msk',['../group___peripheral___registers___bits___definition.html#gab48737db683e9eb6c654fb009eccd7be',1,'stm32f407xx_matlab.h']]], - ['dcmi_5fescr_5flec_5fpos_294',['DCMI_ESCR_LEC_Pos',['../group___peripheral___registers___bits___definition.html#ga7ae8266875df6979d97b6f2ef0bf9dfd',1,'stm32f407xx_matlab.h']]], - ['dcmi_5fescr_5flsc_295',['DCMI_ESCR_LSC',['../group___peripheral___registers___bits___definition.html#ga2f673b3dfe4d73c36ec941780cc91ce5',1,'stm32f407xx_matlab.h']]], - ['dcmi_5fescr_5flsc_5fmsk_296',['DCMI_ESCR_LSC_Msk',['../group___peripheral___registers___bits___definition.html#ga70700ed96c539f193ff3dde57c41e414',1,'stm32f407xx_matlab.h']]], - ['dcmi_5fescr_5flsc_5fpos_297',['DCMI_ESCR_LSC_Pos',['../group___peripheral___registers___bits___definition.html#gaa2a19d08646392458bfc5b1db2fcd401',1,'stm32f407xx_matlab.h']]], - ['dcmi_5fesur_5ffeu_298',['DCMI_ESUR_FEU',['../group___peripheral___registers___bits___definition.html#ga71824df64b1b6626e66e5a83d4663a6e',1,'stm32f407xx_matlab.h']]], - ['dcmi_5fesur_5ffeu_5fmsk_299',['DCMI_ESUR_FEU_Msk',['../group___peripheral___registers___bits___definition.html#gad9324fdd6bc3877df9bc3bdc2adecb6c',1,'stm32f407xx_matlab.h']]], - ['dcmi_5fesur_5ffeu_5fpos_300',['DCMI_ESUR_FEU_Pos',['../group___peripheral___registers___bits___definition.html#gadc1a3b6739ae97c70421d9e43fc190c7',1,'stm32f407xx_matlab.h']]], - ['dcmi_5fesur_5ffsu_301',['DCMI_ESUR_FSU',['../group___peripheral___registers___bits___definition.html#ga07da26e3445ad620bf9f79853f521985',1,'stm32f407xx_matlab.h']]], - ['dcmi_5fesur_5ffsu_5fmsk_302',['DCMI_ESUR_FSU_Msk',['../group___peripheral___registers___bits___definition.html#ga036205fd064f7ac796af221a5c01d719',1,'stm32f407xx_matlab.h']]], - ['dcmi_5fesur_5ffsu_5fpos_303',['DCMI_ESUR_FSU_Pos',['../group___peripheral___registers___bits___definition.html#gab8ab290d57eea4b8ee06ab5d5be8260c',1,'stm32f407xx_matlab.h']]], - ['dcmi_5fesur_5fleu_304',['DCMI_ESUR_LEU',['../group___peripheral___registers___bits___definition.html#ga65e5d6c1fa10262d9deb97e557fd294c',1,'stm32f407xx_matlab.h']]], - ['dcmi_5fesur_5fleu_5fmsk_305',['DCMI_ESUR_LEU_Msk',['../group___peripheral___registers___bits___definition.html#gaa57fa1027141af3c9cbca28d364bfff6',1,'stm32f407xx_matlab.h']]], - ['dcmi_5fesur_5fleu_5fpos_306',['DCMI_ESUR_LEU_Pos',['../group___peripheral___registers___bits___definition.html#ga67c976e3d9e4b572622087768cd82438',1,'stm32f407xx_matlab.h']]], - ['dcmi_5fesur_5flsu_307',['DCMI_ESUR_LSU',['../group___peripheral___registers___bits___definition.html#gaef06107788d6ef1164cca2eec17ccd82',1,'stm32f407xx_matlab.h']]], - ['dcmi_5fesur_5flsu_5fmsk_308',['DCMI_ESUR_LSU_Msk',['../group___peripheral___registers___bits___definition.html#ga28f623ee4d63d33aa7ffba98e4eb56d2',1,'stm32f407xx_matlab.h']]], - ['dcmi_5fesur_5flsu_5fpos_309',['DCMI_ESUR_LSU_Pos',['../group___peripheral___registers___bits___definition.html#gad05dbef1970d3d226f390de22b5f9e36',1,'stm32f407xx_matlab.h']]], - ['dcmi_5ficr_5ferr_5fisc_310',['DCMI_ICR_ERR_ISC',['../group___peripheral___registers___bits___definition.html#ga8da69cdd9d4f4c280279fa05fdf235bc',1,'stm32f407xx_matlab.h']]], - ['dcmi_5ficr_5ferr_5fisc_5fmsk_311',['DCMI_ICR_ERR_ISC_Msk',['../group___peripheral___registers___bits___definition.html#gab819f4eb028d0bce638a7fc5aac68e1e',1,'stm32f407xx_matlab.h']]], - ['dcmi_5ficr_5ferr_5fisc_5fpos_312',['DCMI_ICR_ERR_ISC_Pos',['../group___peripheral___registers___bits___definition.html#gaef56d07e9430cebe51d917c96a46bd4a',1,'stm32f407xx_matlab.h']]], - ['dcmi_5ficr_5fframe_5fisc_313',['DCMI_ICR_FRAME_ISC',['../group___peripheral___registers___bits___definition.html#ga7ce2decf4166be0a5376ea2810403030',1,'stm32f407xx_matlab.h']]], - ['dcmi_5ficr_5fframe_5fisc_5fmsk_314',['DCMI_ICR_FRAME_ISC_Msk',['../group___peripheral___registers___bits___definition.html#ga6bc8bd2a6b5de3b723915ab6fbfc9603',1,'stm32f407xx_matlab.h']]], - ['dcmi_5ficr_5fframe_5fisc_5fpos_315',['DCMI_ICR_FRAME_ISC_Pos',['../group___peripheral___registers___bits___definition.html#gaa522718b7f9eeec5df1dc941c4caa092',1,'stm32f407xx_matlab.h']]], - ['dcmi_5ficr_5fline_5fisc_316',['DCMI_ICR_LINE_ISC',['../group___peripheral___registers___bits___definition.html#gae64182a042ceb8275c54819458b1ca9c',1,'stm32f407xx_matlab.h']]], - ['dcmi_5ficr_5fline_5fisc_5fmsk_317',['DCMI_ICR_LINE_ISC_Msk',['../group___peripheral___registers___bits___definition.html#gafdca5913b4eae2aeb02469e77434d557',1,'stm32f407xx_matlab.h']]], - ['dcmi_5ficr_5fline_5fisc_5fpos_318',['DCMI_ICR_LINE_ISC_Pos',['../group___peripheral___registers___bits___definition.html#ga166cd5d629e51a08b20b7fd3ceb8739a',1,'stm32f407xx_matlab.h']]], - ['dcmi_5ficr_5fovf_5fisc_319',['DCMI_ICR_OVF_ISC',['../group___peripheral___registers___bits___definition.html#ga0318fb46a8594834640d08a9ae06f79e',1,'stm32f407xx_matlab.h']]], - ['dcmi_5ficr_5fovr_5fisc_320',['DCMI_ICR_OVR_ISC',['../group___peripheral___registers___bits___definition.html#gaf9d9f8083bf587a6e6d6f5470fb29a88',1,'stm32f407xx_matlab.h']]], - ['dcmi_5ficr_5fovr_5fisc_5fmsk_321',['DCMI_ICR_OVR_ISC_Msk',['../group___peripheral___registers___bits___definition.html#ga63ef3349d85e073e5a212e523ad1ac50',1,'stm32f407xx_matlab.h']]], - ['dcmi_5ficr_5fovr_5fisc_5fpos_322',['DCMI_ICR_OVR_ISC_Pos',['../group___peripheral___registers___bits___definition.html#ga03be33d65b8a9c6c9c2ed69ba286f387',1,'stm32f407xx_matlab.h']]], - ['dcmi_5ficr_5fvsync_5fisc_323',['DCMI_ICR_VSYNC_ISC',['../group___peripheral___registers___bits___definition.html#gaedd101bdda4f13c30d7af5a85156a047',1,'stm32f407xx_matlab.h']]], - ['dcmi_5ficr_5fvsync_5fisc_5fmsk_324',['DCMI_ICR_VSYNC_ISC_Msk',['../group___peripheral___registers___bits___definition.html#ga5f7f889d6c3a2e1f6300618333b54b78',1,'stm32f407xx_matlab.h']]], - ['dcmi_5ficr_5fvsync_5fisc_5fpos_325',['DCMI_ICR_VSYNC_ISC_Pos',['../group___peripheral___registers___bits___definition.html#gad0087c275317c3692ea9ba74b5792f2a',1,'stm32f407xx_matlab.h']]], - ['dcmi_5fier_5ferr_5fie_326',['DCMI_IER_ERR_IE',['../group___peripheral___registers___bits___definition.html#gacc9d64d6edc4e8ff9452db0065c12831',1,'stm32f407xx_matlab.h']]], - ['dcmi_5fier_5ferr_5fie_5fmsk_327',['DCMI_IER_ERR_IE_Msk',['../group___peripheral___registers___bits___definition.html#ga3fdbc46256c696cc52602dbb3c275090',1,'stm32f407xx_matlab.h']]], - ['dcmi_5fier_5ferr_5fie_5fpos_328',['DCMI_IER_ERR_IE_Pos',['../group___peripheral___registers___bits___definition.html#ga71ba0a7a3bdbddd9117d28170b69f043',1,'stm32f407xx_matlab.h']]], - ['dcmi_5fier_5fframe_5fie_329',['DCMI_IER_FRAME_IE',['../group___peripheral___registers___bits___definition.html#ga78d30c219bf7b5ebe0f8ee74cbdae61d',1,'stm32f407xx_matlab.h']]], - ['dcmi_5fier_5fframe_5fie_5fmsk_330',['DCMI_IER_FRAME_IE_Msk',['../group___peripheral___registers___bits___definition.html#ga3f620e3f5ac8a334cda95e761e7e410b',1,'stm32f407xx_matlab.h']]], - ['dcmi_5fier_5fframe_5fie_5fpos_331',['DCMI_IER_FRAME_IE_Pos',['../group___peripheral___registers___bits___definition.html#ga8bd2b1d1f6d0b24c0871bd617f0fcca8',1,'stm32f407xx_matlab.h']]], - ['dcmi_5fier_5fline_5fie_332',['DCMI_IER_LINE_IE',['../group___peripheral___registers___bits___definition.html#ga4a06c700c5e779551834862a2d14612e',1,'stm32f407xx_matlab.h']]], - ['dcmi_5fier_5fline_5fie_5fmsk_333',['DCMI_IER_LINE_IE_Msk',['../group___peripheral___registers___bits___definition.html#ga61b024ef7c45524af9a733769c453ee4',1,'stm32f407xx_matlab.h']]], - ['dcmi_5fier_5fline_5fie_5fpos_334',['DCMI_IER_LINE_IE_Pos',['../group___peripheral___registers___bits___definition.html#ga8afd81592f141ee1f028a7e65f4418d1',1,'stm32f407xx_matlab.h']]], - ['dcmi_5fier_5fovf_5fie_335',['DCMI_IER_OVF_IE',['../group___peripheral___registers___bits___definition.html#ga4f313352a86f6b09726e63f89e161187',1,'stm32f407xx_matlab.h']]], - ['dcmi_5fier_5fovr_5fie_336',['DCMI_IER_OVR_IE',['../group___peripheral___registers___bits___definition.html#ga3526fa00f78f05a35551294374134d81',1,'stm32f407xx_matlab.h']]], - ['dcmi_5fier_5fovr_5fie_5fmsk_337',['DCMI_IER_OVR_IE_Msk',['../group___peripheral___registers___bits___definition.html#ga0b10a920924f2a6b2fbc3a29e1dfab62',1,'stm32f407xx_matlab.h']]], - ['dcmi_5fier_5fovr_5fie_5fpos_338',['DCMI_IER_OVR_IE_Pos',['../group___peripheral___registers___bits___definition.html#ga4e618e53a00804740c96a6a87fe4eb5d',1,'stm32f407xx_matlab.h']]], - ['dcmi_5fier_5fvsync_5fie_339',['DCMI_IER_VSYNC_IE',['../group___peripheral___registers___bits___definition.html#gad2f335c69d18e49ffb5314e85ac1f4fc',1,'stm32f407xx_matlab.h']]], - ['dcmi_5fier_5fvsync_5fie_5fmsk_340',['DCMI_IER_VSYNC_IE_Msk',['../group___peripheral___registers___bits___definition.html#gae8df43e41d5ffd5f74e8ab0e892a5eb9',1,'stm32f407xx_matlab.h']]], - ['dcmi_5fier_5fvsync_5fie_5fpos_341',['DCMI_IER_VSYNC_IE_Pos',['../group___peripheral___registers___bits___definition.html#ga8e02ca273e7458bbdb7e204666748b19',1,'stm32f407xx_matlab.h']]], - ['dcmi_5firqn_342',['DCMI_IRQn',['../group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8ace3c0fc2c4d05a7c02e3c987da5bc8e8',1,'stm32f407xx_matlab.h']]], - ['dcmi_5fmis_5ferr_5fmis_343',['DCMI_MIS_ERR_MIS',['../group___peripheral___registers___bits___definition.html#ga46deae49ce6acb93a2c9827b7de125ed',1,'stm32f407xx_matlab.h']]], - ['dcmi_5fmis_5ferr_5fmis_5fmsk_344',['DCMI_MIS_ERR_MIS_Msk',['../group___peripheral___registers___bits___definition.html#gae49e11fcd9d6e779c0f03fb206ba50dd',1,'stm32f407xx_matlab.h']]], - ['dcmi_5fmis_5ferr_5fmis_5fpos_345',['DCMI_MIS_ERR_MIS_Pos',['../group___peripheral___registers___bits___definition.html#ga794cffd7108134514729d69dc29e3adc',1,'stm32f407xx_matlab.h']]], - ['dcmi_5fmis_5fframe_5fmis_346',['DCMI_MIS_FRAME_MIS',['../group___peripheral___registers___bits___definition.html#ga941155c6f476426df918e806a0f32e4e',1,'stm32f407xx_matlab.h']]], - ['dcmi_5fmis_5fframe_5fmis_5fmsk_347',['DCMI_MIS_FRAME_MIS_Msk',['../group___peripheral___registers___bits___definition.html#ga1bccb72ae32d9e1af338767329728ecf',1,'stm32f407xx_matlab.h']]], - ['dcmi_5fmis_5fframe_5fmis_5fpos_348',['DCMI_MIS_FRAME_MIS_Pos',['../group___peripheral___registers___bits___definition.html#gaf50f1645c609ecf4c86539214559b13a',1,'stm32f407xx_matlab.h']]], - ['dcmi_5fmis_5fline_5fmis_349',['DCMI_MIS_LINE_MIS',['../group___peripheral___registers___bits___definition.html#ga340adf786e70c8b9ebc2deef9aa30ced',1,'stm32f407xx_matlab.h']]], - ['dcmi_5fmis_5fline_5fmis_5fmsk_350',['DCMI_MIS_LINE_MIS_Msk',['../group___peripheral___registers___bits___definition.html#ga06dbeaf099a326aa55f1ea65dd821af4',1,'stm32f407xx_matlab.h']]], - ['dcmi_5fmis_5fline_5fmis_5fpos_351',['DCMI_MIS_LINE_MIS_Pos',['../group___peripheral___registers___bits___definition.html#ga88e5fa975bd3ac9ba03ef27f9647c916',1,'stm32f407xx_matlab.h']]], - ['dcmi_5fmis_5fovr_5fmis_352',['DCMI_MIS_OVR_MIS',['../group___peripheral___registers___bits___definition.html#ga2bf479b833da567f2ee940d570a54517',1,'stm32f407xx_matlab.h']]], - ['dcmi_5fmis_5fovr_5fmis_5fmsk_353',['DCMI_MIS_OVR_MIS_Msk',['../group___peripheral___registers___bits___definition.html#ga56960bc01ad1ed046aab7db0fc2d0a5e',1,'stm32f407xx_matlab.h']]], - ['dcmi_5fmis_5fovr_5fmis_5fpos_354',['DCMI_MIS_OVR_MIS_Pos',['../group___peripheral___registers___bits___definition.html#gac62263a4027c8db50c73af02ce4c61f1',1,'stm32f407xx_matlab.h']]], - ['dcmi_5fmis_5fvsync_5fmis_355',['DCMI_MIS_VSYNC_MIS',['../group___peripheral___registers___bits___definition.html#ga8559771f71aa7c77eec58339c628f26a',1,'stm32f407xx_matlab.h']]], - ['dcmi_5fmis_5fvsync_5fmis_5fmsk_356',['DCMI_MIS_VSYNC_MIS_Msk',['../group___peripheral___registers___bits___definition.html#gaf4ff5663b22aac5464b75cb3514f262e',1,'stm32f407xx_matlab.h']]], - ['dcmi_5fmis_5fvsync_5fmis_5fpos_357',['DCMI_MIS_VSYNC_MIS_Pos',['../group___peripheral___registers___bits___definition.html#gad6e09a3ece4317ea262cd9f5e0e5a2a7',1,'stm32f407xx_matlab.h']]], - ['dcmi_5fmisr_5ferr_5fmis_358',['DCMI_MISR_ERR_MIS',['../group___peripheral___registers___bits___definition.html#ga117dd3b10b1c7a03016fce867a6a8281',1,'stm32f407xx_matlab.h']]], - ['dcmi_5fmisr_5fframe_5fmis_359',['DCMI_MISR_FRAME_MIS',['../group___peripheral___registers___bits___definition.html#ga73b7d7359389df61668089920ed5b28e',1,'stm32f407xx_matlab.h']]], - ['dcmi_5fmisr_5fline_5fmis_360',['DCMI_MISR_LINE_MIS',['../group___peripheral___registers___bits___definition.html#ga77aad6389ea95913c34b2ba3a14cfdca',1,'stm32f407xx_matlab.h']]], - ['dcmi_5fmisr_5fovf_5fmis_361',['DCMI_MISR_OVF_MIS',['../group___peripheral___registers___bits___definition.html#gaacaced5931c5790bdf6fc9ede4591496',1,'stm32f407xx_matlab.h']]], - ['dcmi_5fmisr_5fvsync_5fmis_362',['DCMI_MISR_VSYNC_MIS',['../group___peripheral___registers___bits___definition.html#ga1a02749de4576d3631cf35dbb4e4bf5c',1,'stm32f407xx_matlab.h']]], - ['dcmi_5fris_5ferr_5fris_363',['DCMI_RIS_ERR_RIS',['../group___peripheral___registers___bits___definition.html#ga60312c64ac11224348e6817b16b38ace',1,'stm32f407xx_matlab.h']]], - ['dcmi_5fris_5ferr_5fris_5fmsk_364',['DCMI_RIS_ERR_RIS_Msk',['../group___peripheral___registers___bits___definition.html#ga92f212d4ebfc932e28a9a190f96e1861',1,'stm32f407xx_matlab.h']]], - ['dcmi_5fris_5ferr_5fris_5fpos_365',['DCMI_RIS_ERR_RIS_Pos',['../group___peripheral___registers___bits___definition.html#gae917e074e286a7a44b7d192d540eb367',1,'stm32f407xx_matlab.h']]], - ['dcmi_5fris_5fframe_5fris_366',['DCMI_RIS_FRAME_RIS',['../group___peripheral___registers___bits___definition.html#ga188d7dafa72efe56f8363ffee4b0662b',1,'stm32f407xx_matlab.h']]], - ['dcmi_5fris_5fframe_5fris_5fmsk_367',['DCMI_RIS_FRAME_RIS_Msk',['../group___peripheral___registers___bits___definition.html#ga28f7059f0838e9089197abd09dbb1773',1,'stm32f407xx_matlab.h']]], - ['dcmi_5fris_5fframe_5fris_5fpos_368',['DCMI_RIS_FRAME_RIS_Pos',['../group___peripheral___registers___bits___definition.html#ga4dd9257e83488a0c5a4f22d1b687227e',1,'stm32f407xx_matlab.h']]], - ['dcmi_5fris_5fline_5fris_369',['DCMI_RIS_LINE_RIS',['../group___peripheral___registers___bits___definition.html#ga7df083b857fd655d11a90a7a1ee94d66',1,'stm32f407xx_matlab.h']]], - ['dcmi_5fris_5fline_5fris_5fmsk_370',['DCMI_RIS_LINE_RIS_Msk',['../group___peripheral___registers___bits___definition.html#ga143c2c95deb861fb392953a15b99c174',1,'stm32f407xx_matlab.h']]], - ['dcmi_5fris_5fline_5fris_5fpos_371',['DCMI_RIS_LINE_RIS_Pos',['../group___peripheral___registers___bits___definition.html#gab6c35d6c01b791049b926e626703a043',1,'stm32f407xx_matlab.h']]], - ['dcmi_5fris_5fovr_5fris_372',['DCMI_RIS_OVR_RIS',['../group___peripheral___registers___bits___definition.html#gaaeb2e93438e3aa6b72a2f897c3ed86bc',1,'stm32f407xx_matlab.h']]], - ['dcmi_5fris_5fovr_5fris_5fmsk_373',['DCMI_RIS_OVR_RIS_Msk',['../group___peripheral___registers___bits___definition.html#ga8bf3ee23039b601106d1d91e9acced53',1,'stm32f407xx_matlab.h']]], - ['dcmi_5fris_5fovr_5fris_5fpos_374',['DCMI_RIS_OVR_RIS_Pos',['../group___peripheral___registers___bits___definition.html#gace86e6047cb5cae4000378626d291678',1,'stm32f407xx_matlab.h']]], - ['dcmi_5fris_5fvsync_5fris_375',['DCMI_RIS_VSYNC_RIS',['../group___peripheral___registers___bits___definition.html#ga57777e4dfeb6df63ffc1eee8e1fd51e9',1,'stm32f407xx_matlab.h']]], - ['dcmi_5fris_5fvsync_5fris_5fmsk_376',['DCMI_RIS_VSYNC_RIS_Msk',['../group___peripheral___registers___bits___definition.html#gaaf2902c19b9063c83d8e269f83428a6d',1,'stm32f407xx_matlab.h']]], - ['dcmi_5fris_5fvsync_5fris_5fpos_377',['DCMI_RIS_VSYNC_RIS_Pos',['../group___peripheral___registers___bits___definition.html#ga2b953f571921dbaecbf126b7768ce9e0',1,'stm32f407xx_matlab.h']]], - ['dcmi_5frisr_5ferr_5fris_378',['DCMI_RISR_ERR_RIS',['../group___peripheral___registers___bits___definition.html#gaf03ca1f0e5e1a7868c07c8237d7e33a3',1,'stm32f407xx_matlab.h']]], - ['dcmi_5frisr_5fframe_5fris_379',['DCMI_RISR_FRAME_RIS',['../group___peripheral___registers___bits___definition.html#ga99308f49b63dd49db671a2a26d0d07fa',1,'stm32f407xx_matlab.h']]], - ['dcmi_5frisr_5fline_5fris_380',['DCMI_RISR_LINE_RIS',['../group___peripheral___registers___bits___definition.html#gaf06b386a61d97e046a7f0546478b91b8',1,'stm32f407xx_matlab.h']]], - ['dcmi_5frisr_5fovf_5fris_381',['DCMI_RISR_OVF_RIS',['../group___peripheral___registers___bits___definition.html#ga510c3f423fdddf8a41b6b69d55b6c66d',1,'stm32f407xx_matlab.h']]], - ['dcmi_5frisr_5fovr_5fris_382',['DCMI_RISR_OVR_RIS',['../group___peripheral___registers___bits___definition.html#gae893218ce7d16540e5af7c3afb03bc98',1,'stm32f407xx_matlab.h']]], - ['dcmi_5frisr_5fvsync_5fris_383',['DCMI_RISR_VSYNC_RIS',['../group___peripheral___registers___bits___definition.html#ga08625c101d8419ca58cc7032f4a936ec',1,'stm32f407xx_matlab.h']]], - ['dcmi_5fsr_5ffne_384',['DCMI_SR_FNE',['../group___peripheral___registers___bits___definition.html#ga990aaedf052bc3b9ebd115f06aa43ab2',1,'stm32f407xx_matlab.h']]], - ['dcmi_5fsr_5ffne_5fmsk_385',['DCMI_SR_FNE_Msk',['../group___peripheral___registers___bits___definition.html#gad19357d2286c9647ce0fce32c8b0578c',1,'stm32f407xx_matlab.h']]], - ['dcmi_5fsr_5ffne_5fpos_386',['DCMI_SR_FNE_Pos',['../group___peripheral___registers___bits___definition.html#ga4425f4dfb86dbb4249d27b92b90caafe',1,'stm32f407xx_matlab.h']]], - ['dcmi_5fsr_5fhsync_387',['DCMI_SR_HSYNC',['../group___peripheral___registers___bits___definition.html#gafb10174e5a89c32d6413ecf77e6610a0',1,'stm32f407xx_matlab.h']]], - ['dcmi_5fsr_5fhsync_5fmsk_388',['DCMI_SR_HSYNC_Msk',['../group___peripheral___registers___bits___definition.html#ga52a8a170e5bc418b043e712c65852121',1,'stm32f407xx_matlab.h']]], - ['dcmi_5fsr_5fhsync_5fpos_389',['DCMI_SR_HSYNC_Pos',['../group___peripheral___registers___bits___definition.html#gaa5e7fd85cd8977bbd867cacd10016b9a',1,'stm32f407xx_matlab.h']]], - ['dcmi_5fsr_5fvsync_390',['DCMI_SR_VSYNC',['../group___peripheral___registers___bits___definition.html#ga9608c2fdd5feb3c8c022545f8d7e6adf',1,'stm32f407xx_matlab.h']]], - ['dcmi_5fsr_5fvsync_5fmsk_391',['DCMI_SR_VSYNC_Msk',['../group___peripheral___registers___bits___definition.html#gae563614237e37f375f3a0cea5d01d272',1,'stm32f407xx_matlab.h']]], - ['dcmi_5fsr_5fvsync_5fpos_392',['DCMI_SR_VSYNC_Pos',['../group___peripheral___registers___bits___definition.html#ga8518f9299351064b5d42d297d3337e9a',1,'stm32f407xx_matlab.h']]], - ['dcmi_5ftypedef_393',['DCMI_TypeDef',['../struct_d_c_m_i___type_def.html',1,'']]], - ['dcount_394',['DCOUNT',['../group___c_m_s_i_s___device.html#ga1c267db01a753d0b8a77afcaff6f9e13',1,'SDIO_TypeDef']]], - ['dcr_395',['DCR',['../group___c_m_s_i_s___device.html#gaf6225cb8f4938f98204d11afaffd41c9',1,'TIM_TypeDef']]], - ['dcrdr_396',['DCRDR',['../group___c_m_s_i_s__core___debug_functions.html#gad1dbd0dd98b6d9327f70545e0081ddbf',1,'CoreDebug_Type']]], - ['dcrsr_397',['DCRSR',['../group___c_m_s_i_s__core___debug_functions.html#gab74a9ec90ad18e4f7a20362d362b754a',1,'CoreDebug_Type']]], - ['dctl_398',['DCTL',['../group___c_m_s_i_s___device.html#gadc1bdc4e76749ccda09c92e885b164ad',1,'USB_OTG_DeviceTypeDef']]], - ['dctrl_399',['DCTRL',['../group___c_m_s_i_s___device.html#ga96a3d1a050982fccc23c2e6dbe0de068',1,'SDIO_TypeDef']]], - ['deachint_400',['DEACHINT',['../group___c_m_s_i_s___device.html#gae85e8a65a72f52a9daf3d2b66b77c2e2',1,'USB_OTG_DeviceTypeDef']]], - ['deachmsk_401',['DEACHMSK',['../group___c_m_s_i_s___device.html#ga0234d794aba7ddae31f3da3c02c8a673',1,'USB_OTG_DeviceTypeDef']]], - ['debug_20registers_20coredebug_402',['Core Debug Registers (CoreDebug)',['../group___c_m_s_i_s___core_debug.html',1,'']]], - ['debug_5fmcu_403',['DEBUG_MCU',['../stm32f4xx__matlab__conf_8c.html#a85a080726cb1ade56443b458fc49404b',1,'DEBUG_MCU: stm32f4xx_matlab_conf.c'],['../group___peripheral__memory__map.html#ga85a080726cb1ade56443b458fc49404b',1,'DEBUG_MCU: stm32f407xx_matlab.h']]], - ['debugmonitor_5firqn_404',['DebugMonitor_IRQn',['../group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a8e033fcef7aed98a31c60a7de206722c',1,'stm32f407xx_matlab.h']]], - ['defines_405',['CMSIS Global Defines',['../group___c_m_s_i_s__glob__defs.html',1,'']]], - ['defines_20and_20type_20definitions_406',['Defines and Type Definitions',['../group___c_m_s_i_s__core__register.html',1,'']]], - ['definitions_407',['Definitions',['../group___c_m_s_i_s__core__base.html',1,'Core Definitions'],['../group___c_m_s_i_s__core__register.html',1,'Defines and Type Definitions']]], - ['deinitialize_5fmcu_408',['deInitialize_MCU',['../group___m_a_i_n___s_i_m_u_l_a_t_o_r.html#gad7d9ddf99be97748bc7417425271d85e',1,'deInitialize_MCU(void): stm32f4xx_matlab_conf.c'],['../group___m_a_i_n___s_i_m_u_l_a_t_o_r.html#gad7d9ddf99be97748bc7417425271d85e',1,'deInitialize_MCU(void): stm32f4xx_matlab_conf.c']]], - ['deinitialize_5fperiph_5fsim_409',['deInitialize_Periph_Sim',['../group___m_a_i_n___s_i_m_u_l_a_t_o_r.html#gaff389f4df35953d82d9d30ae161a8cf9',1,'deInitialize_Periph_Sim(void): stm32f4xx_matlab_conf.c'],['../group___m_a_i_n___s_i_m_u_l_a_t_o_r.html#gaff389f4df35953d82d9d30ae161a8cf9',1,'deInitialize_Periph_Sim(void): stm32f4xx_matlab_conf.c']]], - ['dekstop_5fcycles_5ffor_5fmcu_5fapp_410',['DEKSTOP_CYCLES_FOR_MCU_APP',['../group___w_r_a_p_p_e_r___c_o_n_f.html#gafc876c6cc8fa4255636740b201ac1d66',1,'mcu_wrapper_conf.h']]], - ['delete_411',['delete',['../mexing_8m.html#a079ba1759372ad0dafb30bfb334998cc',1,'mexing.m']]], - ['demcr_412',['DEMCR',['../group___c_m_s_i_s__core___debug_functions.html#gaa99de5f8c609f10c25ed51f57b2edd74',1,'CoreDebug_Type']]], - ['device_5fincluded_413',['Device_Included',['../group___device___included.html',1,'']]], - ['devid_414',['DEVID',['../group___c_m_s_i_s__core___debug_functions.html#gaaed316dacef669454fa035e04ee90eca',1,'TPI_Type']]], - ['devtype_415',['DEVTYPE',['../group___c_m_s_i_s__core___debug_functions.html#ga81f643aff0e4bed2638a618e2b1fd3bb',1,'TPI_Type']]], - ['dfr_416',['DFR',['../group___c_m_s_i_s__core___debug_functions.html#gae2b3d4530d1b0c05593b634dc46348bd',1,'SCB_Type']]], - ['dfsr_417',['DFSR',['../group___c_m_s_i_s__core___debug_functions.html#ga3b590075aa07880ce686d5cfb4e61c5c',1,'SCB_Type']]], - ['dhcsr_418',['DHCSR',['../group___c_m_s_i_s__core___debug_functions.html#ga94ca828091a9226ab6684fbf30e52909',1,'CoreDebug_Type']]], - ['dhr12l1_419',['DHR12L1',['../group___c_m_s_i_s___device.html#gae9028b8bcb5118b7073165fb50fcd559',1,'DAC_TypeDef']]], - ['dhr12l2_420',['DHR12L2',['../group___c_m_s_i_s___device.html#ga2e45f9c9d67e384187b25334ba0a3e3d',1,'DAC_TypeDef']]], - ['dhr12ld_421',['DHR12LD',['../group___c_m_s_i_s___device.html#gacc269320aff0a6482730224a4b641a59',1,'DAC_TypeDef']]], - ['dhr12r1_422',['DHR12R1',['../group___c_m_s_i_s___device.html#gac2bb55b037b800a25852736afdd7a258',1,'DAC_TypeDef']]], - ['dhr12r2_423',['DHR12R2',['../group___c_m_s_i_s___device.html#ga804c7e15dbb587c7ea25511f6a7809f7',1,'DAC_TypeDef']]], - ['dhr12rd_424',['DHR12RD',['../group___c_m_s_i_s___device.html#ga1590b77e57f17e75193da259da72095e',1,'DAC_TypeDef']]], - ['dhr8r1_425',['DHR8R1',['../group___c_m_s_i_s___device.html#gad0a200e12acad17a5c7d2059159ea7e1',1,'DAC_TypeDef']]], - ['dhr8r2_426',['DHR8R2',['../group___c_m_s_i_s___device.html#ga4c435f0e34ace4421241cd5c3ae87fc2',1,'DAC_TypeDef']]], - ['dhr8rd_427',['DHR8RD',['../group___c_m_s_i_s___device.html#ga9590269cba8412f1be96b0ddb846ef44',1,'DAC_TypeDef']]], - ['diepctl_428',['DIEPCTL',['../group___c_m_s_i_s___device.html#ga840b32fa57faa544c3000ae1d08564c7',1,'USB_OTG_INEndpointTypeDef']]], - ['diepdma_429',['DIEPDMA',['../group___c_m_s_i_s___device.html#ga05fcc63652e936e715223e4423069959',1,'USB_OTG_INEndpointTypeDef']]], - ['diepempmsk_430',['DIEPEMPMSK',['../group___c_m_s_i_s___device.html#ga99c6c50a3e3235c81b98a428ebd33d4c',1,'USB_OTG_DeviceTypeDef']]], - ['diepint_431',['DIEPINT',['../group___c_m_s_i_s___device.html#ga65f69561c1cefe00ce608b7a3c2d8af5',1,'USB_OTG_INEndpointTypeDef']]], - ['diepmsk_432',['DIEPMSK',['../group___c_m_s_i_s___device.html#ga48647281e48d96a96f701cf5ae3f4f63',1,'USB_OTG_DeviceTypeDef']]], - ['dieptsiz_433',['DIEPTSIZ',['../group___c_m_s_i_s___device.html#ga19cf1f1798a062c2a19afe9224e3f938',1,'USB_OTG_INEndpointTypeDef']]], - ['dieptxf_434',['DIEPTXF',['../group___c_m_s_i_s___device.html#ga2b783e516da93a95c56adf3e52dcbe62',1,'USB_OTG_GlobalTypeDef']]], - ['dieptxf0_5fhnptxfsiz_435',['DIEPTXF0_HNPTXFSIZ',['../group___c_m_s_i_s___device.html#ga93412b352267d3faf0bd2dbac590b69e',1,'USB_OTG_GlobalTypeDef']]], - ['dier_436',['DIER',['../group___c_m_s_i_s___device.html#ga07fccbd85b91e6dca03ce333c1457fcb',1,'TIM_TypeDef']]], - ['dinep1msk_437',['DINEP1MSK',['../group___c_m_s_i_s___device.html#gab62b876c61e11199cf5c37aa944a5fed',1,'USB_OTG_DeviceTypeDef']]], - ['disable_438',['DISABLE',['../group___exported__types.html#ggac9a7e9a35d2513ec15c3b537aaa4fba1ad3a9df141be0ccf10389b640f492b26d',1,'stm32f4xx.h']]], - ['disc_5fstates_5fwidth_439',['DISC_STATES_WIDTH',['../group___w_r_a_p_p_e_r___c_o_n_f.html#gaaed909ba8fd0e4f7a3c2533836dae5d9',1,'mcu_wrapper_conf.h']]], - ['dlen_440',['DLEN',['../group___c_m_s_i_s___device.html#ga612edc78d2fa6288392f8ea32c36f7fb',1,'SDIO_TypeDef']]], - ['dma1_441',['DMA1',['../group___peripheral__declaration.html#gacc16d2a5937f7585320a98f7f6b578f9',1,'stm32f407xx_matlab.h']]], - ['dma1_442',['dma1',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#gad75f4f486cddcbba8bd891fdffea63ff',1,'stm32f4xx_periph_registers.c']]], - ['dma1_5fbase_443',['DMA1_BASE',['../group___peripheral__memory__map.html#gab2d8a917a0e4ea99a22ac6ebf279bc72',1,'stm32f407xx_matlab.h']]], - ['dma1_5fstream0_444',['DMA1_Stream0',['../group___peripheral__declaration.html#ga61247dd5d594289c404dd8774202dfd8',1,'stm32f407xx_matlab.h']]], - ['dma1_5fstream0_445',['dma1_stream0',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga327e8fb8c3fdda29762971a665beb6eb',1,'stm32f4xx_periph_registers.c']]], - ['dma1_5fstream0_5fbase_446',['DMA1_Stream0_BASE',['../group___peripheral__memory__map.html#ga0d3c52aa35dcc68f78b704dfde57ba95',1,'stm32f407xx_matlab.h']]], - ['dma1_5fstream0_5firqn_447',['DMA1_Stream0_IRQn',['../group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a9ee33e72512c4cfb301b216f4fb9d68c',1,'stm32f407xx_matlab.h']]], - ['dma1_5fstream1_448',['DMA1_Stream1',['../group___peripheral__declaration.html#gaf7d82f110f19982d483eebc465d222b2',1,'stm32f407xx_matlab.h']]], - ['dma1_5fstream1_449',['dma1_stream1',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga9696aa3317c6d4e58bd31545db1a3791',1,'stm32f4xx_periph_registers.c']]], - ['dma1_5fstream1_5fbase_450',['DMA1_Stream1_BASE',['../group___peripheral__memory__map.html#ga5b4152cef577e37eccc9311d8bdbf3c2',1,'stm32f407xx_matlab.h']]], - ['dma1_5fstream1_5firqn_451',['DMA1_Stream1_IRQn',['../group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8aa45ca2c955060e2c2a7cbbe1d6753285',1,'stm32f407xx_matlab.h']]], - ['dma1_5fstream2_452',['dma1_stream2',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#gaf1e2d204d4c7f13213bc4cdece346a9f',1,'stm32f4xx_periph_registers.c']]], - ['dma1_5fstream2_453',['DMA1_Stream2',['../group___peripheral__declaration.html#gad0e2140b8eeec3594035f1a7bf2a7250',1,'stm32f407xx_matlab.h']]], - ['dma1_5fstream2_5fbase_454',['DMA1_Stream2_BASE',['../group___peripheral__memory__map.html#ga48a551ee91d3f07dd74347fdb35c703d',1,'stm32f407xx_matlab.h']]], - ['dma1_5fstream2_5firqn_455',['DMA1_Stream2_IRQn',['../group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a0d9ec75e4478e70235b705d5a6b3efd8',1,'stm32f407xx_matlab.h']]], - ['dma1_5fstream3_456',['dma1_stream3',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga67575d2b3cf487db91535889ed5802c4',1,'stm32f4xx_periph_registers.c']]], - ['dma1_5fstream3_457',['DMA1_Stream3',['../group___peripheral__declaration.html#ga96ac1af7a92469fe86a9fbdec091f25d',1,'stm32f407xx_matlab.h']]], - ['dma1_5fstream3_5fbase_458',['DMA1_Stream3_BASE',['../group___peripheral__memory__map.html#gac51deb54ff7cfe1290dfcf517ae67127',1,'stm32f407xx_matlab.h']]], - ['dma1_5fstream3_5firqn_459',['DMA1_Stream3_IRQn',['../group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8af77770e080206a7558decf09344fb2e2',1,'stm32f407xx_matlab.h']]], - ['dma1_5fstream4_460',['dma1_stream4',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga0da31a3af45097d4b4a136c5d74d6000',1,'stm32f4xx_periph_registers.c']]], - ['dma1_5fstream4_461',['DMA1_Stream4',['../group___peripheral__declaration.html#ga87df45f4b82e0b3a8c1b17f1a77aecdb',1,'stm32f407xx_matlab.h']]], - ['dma1_5fstream4_5fbase_462',['DMA1_Stream4_BASE',['../group___peripheral__memory__map.html#ga757a3c0d866c0fe68c6176156065a26b',1,'stm32f407xx_matlab.h']]], - ['dma1_5fstream4_5firqn_463',['DMA1_Stream4_IRQn',['../group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8aee2aaf365c6c297a63cee41ecae2301a',1,'stm32f407xx_matlab.h']]], - ['dma1_5fstream5_464',['dma1_stream5',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga160109a05c1a572c5911c1a0633e2cb1',1,'stm32f4xx_periph_registers.c']]], - ['dma1_5fstream5_465',['DMA1_Stream5',['../group___peripheral__declaration.html#gac3abc20f80e25c19b02104ad34eae652',1,'stm32f407xx_matlab.h']]], - ['dma1_5fstream5_5fbase_466',['DMA1_Stream5_BASE',['../group___peripheral__memory__map.html#ga0ded7bed8969fe2e2d616e7f90eb7654',1,'stm32f407xx_matlab.h']]], - ['dma1_5fstream5_5firqn_467',['DMA1_Stream5_IRQn',['../group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8ac92efa72399fe58fa615d8bf8fd64a4e',1,'stm32f407xx_matlab.h']]], - ['dma1_5fstream6_468',['DMA1_Stream6',['../group___peripheral__declaration.html#gac95127480470900755953f1cfe68567d',1,'stm32f407xx_matlab.h']]], - ['dma1_5fstream6_469',['dma1_stream6',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga52167e4b4ae32ee99aca493b07ec2cf0',1,'stm32f4xx_periph_registers.c']]], - ['dma1_5fstream6_5fbase_470',['DMA1_Stream6_BASE',['../group___peripheral__memory__map.html#ga58998ddc40adb6361704d6c9dad08125',1,'stm32f407xx_matlab.h']]], - ['dma1_5fstream6_5firqn_471',['DMA1_Stream6_IRQn',['../group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8aef5e2b68f62f6f1781fab894f0b8f486',1,'stm32f407xx_matlab.h']]], - ['dma1_5fstream7_472',['DMA1_Stream7',['../group___peripheral__declaration.html#ga8ecdeaf43d0f4207dab1fdb4d7bf8d26',1,'stm32f407xx_matlab.h']]], - ['dma1_5fstream7_473',['dma1_stream7',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#gaeb5a72f1dde2596da84347544d59f3ea',1,'stm32f4xx_periph_registers.c']]], - ['dma1_5fstream7_5fbase_474',['DMA1_Stream7_BASE',['../group___peripheral__memory__map.html#ga82186dd6d3f60995d428b34c041919d7',1,'stm32f407xx_matlab.h']]], - ['dma1_5fstream7_5firqn_475',['DMA1_Stream7_IRQn',['../group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8aedaa9c14e7e5fa9c0dcbb0c2455546e8',1,'stm32f407xx_matlab.h']]], - ['dma2_476',['DMA2',['../group___peripheral__declaration.html#ga506520140eec1708bc7570c49bdf972d',1,'stm32f407xx_matlab.h']]], - ['dma2_477',['dma2',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga797194bf8715329824161a98d1b2a236',1,'stm32f4xx_periph_registers.c']]], - ['dma2_5fbase_478',['DMA2_BASE',['../group___peripheral__memory__map.html#gab72a9ae145053ee13d1d491fb5c1df64',1,'stm32f407xx_matlab.h']]], - ['dma2_5fstream0_479',['DMA2_Stream0',['../group___peripheral__declaration.html#ga3a2efe5fd7a7a79be3b08a1670bbd016',1,'stm32f407xx_matlab.h']]], - ['dma2_5fstream0_480',['dma2_stream0',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#gaeff8718ce310afab98873eccba9ff245',1,'stm32f4xx_periph_registers.c']]], - ['dma2_5fstream0_5fbase_481',['DMA2_Stream0_BASE',['../group___peripheral__memory__map.html#gac4c67b24726ba6b94d03adb351bcec4d',1,'stm32f407xx_matlab.h']]], - ['dma2_5fstream0_5firqn_482',['DMA2_Stream0_IRQn',['../group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a1e5055722630fd4b12aff421964c2ebb',1,'stm32f407xx_matlab.h']]], - ['dma2_5fstream1_483',['dma2_stream1',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga0fb8b4583868b79144561ef45c93637a',1,'stm32f4xx_periph_registers.c']]], - ['dma2_5fstream1_484',['DMA2_Stream1',['../group___peripheral__declaration.html#gae96f15d34d3c41c16fce69bc2878151a',1,'stm32f407xx_matlab.h']]], - ['dma2_5fstream1_5fbase_485',['DMA2_Stream1_BASE',['../group___peripheral__memory__map.html#ga35512bdc3f5e9df4557c2fbe7935d0b1',1,'stm32f407xx_matlab.h']]], - ['dma2_5fstream1_5firqn_486',['DMA2_Stream1_IRQn',['../group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a98abb3f02c1feb3831706bc1b82307cb',1,'stm32f407xx_matlab.h']]], - ['dma2_5fstream2_487',['DMA2_Stream2',['../group___peripheral__declaration.html#ga71bb410664b861ff0520f08976e24ee1',1,'stm32f407xx_matlab.h']]], - ['dma2_5fstream2_488',['dma2_stream2',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga33cbc3fc9b89c29e722fc4e4973d6058',1,'stm32f4xx_periph_registers.c']]], - ['dma2_5fstream2_5fbase_489',['DMA2_Stream2_BASE',['../group___peripheral__memory__map.html#gaed33a06f08188466f2ede06160984e9a',1,'stm32f407xx_matlab.h']]], - ['dma2_5fstream2_5firqn_490',['DMA2_Stream2_IRQn',['../group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8abf5e189f3ac7aad9f65e65ea5a0f3b36',1,'stm32f407xx_matlab.h']]], - ['dma2_5fstream3_491',['dma2_stream3',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#gadcd0980342e18d51ce08021a0d1abfdd',1,'stm32f4xx_periph_registers.c']]], - ['dma2_5fstream3_492',['DMA2_Stream3',['../group___peripheral__declaration.html#gaa6ead6a5ca6b8df70b5505aaeec6fd2e',1,'stm32f407xx_matlab.h']]], - ['dma2_5fstream3_5fbase_493',['DMA2_Stream3_BASE',['../group___peripheral__memory__map.html#gaf3a9480e08c6ae94f4482e0cdaebdd17',1,'stm32f407xx_matlab.h']]], - ['dma2_5fstream3_5firqn_494',['DMA2_Stream3_IRQn',['../group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a3ff8f3439f509e6e985eb960e63e1be4',1,'stm32f407xx_matlab.h']]], - ['dma2_5fstream4_495',['DMA2_Stream4',['../group___peripheral__declaration.html#gae32674772021620800275dd3b6d62c2f',1,'stm32f407xx_matlab.h']]], - ['dma2_5fstream4_496',['dma2_stream4',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga14e0e20b296df9eea835441023807c15',1,'stm32f4xx_periph_registers.c']]], - ['dma2_5fstream4_5fbase_497',['DMA2_Stream4_BASE',['../group___peripheral__memory__map.html#gad1e67740e6301233473f64638145dd1f',1,'stm32f407xx_matlab.h']]], - ['dma2_5fstream4_5firqn_498',['DMA2_Stream4_IRQn',['../group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8ae54eb8b30273b38a0576f75aba24eec0',1,'stm32f407xx_matlab.h']]], - ['dma2_5fstream5_499',['dma2_stream5',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga8fc00e6429450f48f22fddb4040d1e2d',1,'stm32f4xx_periph_registers.c']]], - ['dma2_5fstream5_500',['DMA2_Stream5',['../group___peripheral__declaration.html#gac40f58718761251875b5a897287efd83',1,'stm32f407xx_matlab.h']]], - ['dma2_5fstream5_5fbase_501',['DMA2_Stream5_BASE',['../group___peripheral__memory__map.html#gaed1460fdc407b6decfbffccb0260d0af',1,'stm32f407xx_matlab.h']]], - ['dma2_5fstream5_5firqn_502',['DMA2_Stream5_IRQn',['../group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a933d4686213973abc01845a3da1c8a03',1,'stm32f407xx_matlab.h']]], - ['dma2_5fstream6_503',['dma2_stream6',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga8d4903dcdae5a8f4c0b7b2678b2cf5b4',1,'stm32f4xx_periph_registers.c']]], - ['dma2_5fstream6_504',['DMA2_Stream6',['../group___peripheral__declaration.html#ga11a00b283e0911cd427e277e5a314ccc',1,'stm32f407xx_matlab.h']]], - ['dma2_5fstream6_5fbase_505',['DMA2_Stream6_BASE',['../group___peripheral__memory__map.html#ga5e81174c96fd204fa7c82c815e85c8e6',1,'stm32f407xx_matlab.h']]], - ['dma2_5fstream6_5firqn_506',['DMA2_Stream6_IRQn',['../group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a21570761ad0b5ed751adc831691b7800',1,'stm32f407xx_matlab.h']]], - ['dma2_5fstream7_507',['dma2_stream7',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga19770af0d338f06fbb1ffa09150909b4',1,'stm32f4xx_periph_registers.c']]], - ['dma2_5fstream7_508',['DMA2_Stream7',['../group___peripheral__declaration.html#gacc135dbca0eca67d5aa0abc555f053ce',1,'stm32f407xx_matlab.h']]], - ['dma2_5fstream7_5fbase_509',['DMA2_Stream7_BASE',['../group___peripheral__memory__map.html#gaa9faa708ad2440d24eb1064cba9bb06d',1,'stm32f407xx_matlab.h']]], - ['dma2_5fstream7_5firqn_510',['DMA2_Stream7_IRQn',['../group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a3d4cc0cd9b4d71e7ee002c4f8c1f8a77',1,'stm32f407xx_matlab.h']]], - ['dma_5fhifcr_5fcdmeif4_511',['DMA_HIFCR_CDMEIF4',['../group___peripheral___registers___bits___definition.html#ga0d70d58a4423ac8973c30ddbc7404b44',1,'stm32f407xx_matlab.h']]], - ['dma_5fhifcr_5fcdmeif4_5fmsk_512',['DMA_HIFCR_CDMEIF4_Msk',['../group___peripheral___registers___bits___definition.html#ga3c5757329dbf0633cbe2ff33591b7f2d',1,'stm32f407xx_matlab.h']]], - ['dma_5fhifcr_5fcdmeif4_5fpos_513',['DMA_HIFCR_CDMEIF4_Pos',['../group___peripheral___registers___bits___definition.html#ga465e500de4458c78f26aa483d8f61ee7',1,'stm32f407xx_matlab.h']]], - ['dma_5fhifcr_5fcdmeif5_514',['DMA_HIFCR_CDMEIF5',['../group___peripheral___registers___bits___definition.html#ga15b404d9e1601cf3627cbf0163b50221',1,'stm32f407xx_matlab.h']]], - ['dma_5fhifcr_5fcdmeif5_5fmsk_515',['DMA_HIFCR_CDMEIF5_Msk',['../group___peripheral___registers___bits___definition.html#ga3b99d7b4f3c6346ccafa79d425ee6873',1,'stm32f407xx_matlab.h']]], - ['dma_5fhifcr_5fcdmeif5_5fpos_516',['DMA_HIFCR_CDMEIF5_Pos',['../group___peripheral___registers___bits___definition.html#ga1f259d0788bd3ae21521c574d0d1a00b',1,'stm32f407xx_matlab.h']]], - ['dma_5fhifcr_5fcdmeif6_517',['DMA_HIFCR_CDMEIF6',['../group___peripheral___registers___bits___definition.html#ga7f73fa93a4e01fbf279e920eca139807',1,'stm32f407xx_matlab.h']]], - ['dma_5fhifcr_5fcdmeif6_5fmsk_518',['DMA_HIFCR_CDMEIF6_Msk',['../group___peripheral___registers___bits___definition.html#ga798be301c7de50d3015965037a8ec2bd',1,'stm32f407xx_matlab.h']]], - ['dma_5fhifcr_5fcdmeif6_5fpos_519',['DMA_HIFCR_CDMEIF6_Pos',['../group___peripheral___registers___bits___definition.html#ga2a658f3e303a31be475cb1ea9957dc2e',1,'stm32f407xx_matlab.h']]], - ['dma_5fhifcr_5fcdmeif7_520',['DMA_HIFCR_CDMEIF7',['../group___peripheral___registers___bits___definition.html#gad70bf852fd8c24d79fcc104c950a589f',1,'stm32f407xx_matlab.h']]], - ['dma_5fhifcr_5fcdmeif7_5fmsk_521',['DMA_HIFCR_CDMEIF7_Msk',['../group___peripheral___registers___bits___definition.html#gabb5c753438fac42cee45e0e9a34fab6c',1,'stm32f407xx_matlab.h']]], - ['dma_5fhifcr_5fcdmeif7_5fpos_522',['DMA_HIFCR_CDMEIF7_Pos',['../group___peripheral___registers___bits___definition.html#ga6f4cf4a690ee458370ce8482e3a9b1b9',1,'stm32f407xx_matlab.h']]], - ['dma_5fhifcr_5fcfeif4_523',['DMA_HIFCR_CFEIF4',['../group___peripheral___registers___bits___definition.html#ga1e5ea118900178d4fa2d19656c1b48ff',1,'stm32f407xx_matlab.h']]], - ['dma_5fhifcr_5fcfeif4_5fmsk_524',['DMA_HIFCR_CFEIF4_Msk',['../group___peripheral___registers___bits___definition.html#gadd6d4a4e8764fa0406a1c9dd1bc4535f',1,'stm32f407xx_matlab.h']]], - ['dma_5fhifcr_5fcfeif4_5fpos_525',['DMA_HIFCR_CFEIF4_Pos',['../group___peripheral___registers___bits___definition.html#ga348534b63d5c5d29a3fdd8b080866566',1,'stm32f407xx_matlab.h']]], - ['dma_5fhifcr_5fcfeif5_526',['DMA_HIFCR_CFEIF5',['../group___peripheral___registers___bits___definition.html#ga9a4e90af967fa0a76c842384264e0e52',1,'stm32f407xx_matlab.h']]], - ['dma_5fhifcr_5fcfeif5_5fmsk_527',['DMA_HIFCR_CFEIF5_Msk',['../group___peripheral___registers___bits___definition.html#gab48755800a0d03cf51f6c69848c6e1ce',1,'stm32f407xx_matlab.h']]], - ['dma_5fhifcr_5fcfeif5_5fpos_528',['DMA_HIFCR_CFEIF5_Pos',['../group___peripheral___registers___bits___definition.html#ga60dbe00935c13e0ef57c08970f711a6a',1,'stm32f407xx_matlab.h']]], - ['dma_5fhifcr_5fcfeif6_529',['DMA_HIFCR_CFEIF6',['../group___peripheral___registers___bits___definition.html#ga39a0a7f42498f71dedae8140483b7ced',1,'stm32f407xx_matlab.h']]], - ['dma_5fhifcr_5fcfeif6_5fmsk_530',['DMA_HIFCR_CFEIF6_Msk',['../group___peripheral___registers___bits___definition.html#gaf4bb45a54e669718435808019bd2b9fb',1,'stm32f407xx_matlab.h']]], - ['dma_5fhifcr_5fcfeif6_5fpos_531',['DMA_HIFCR_CFEIF6_Pos',['../group___peripheral___registers___bits___definition.html#ga1cbdd122358aad1b832dcc0a7a4405af',1,'stm32f407xx_matlab.h']]], - ['dma_5fhifcr_5fcfeif7_532',['DMA_HIFCR_CFEIF7',['../group___peripheral___registers___bits___definition.html#ga50332abe2e7b5a4f9cffd65d9a29382a',1,'stm32f407xx_matlab.h']]], - ['dma_5fhifcr_5fcfeif7_5fmsk_533',['DMA_HIFCR_CFEIF7_Msk',['../group___peripheral___registers___bits___definition.html#ga962da3b48acc29b53beae6ae483f5331',1,'stm32f407xx_matlab.h']]], - ['dma_5fhifcr_5fcfeif7_5fpos_534',['DMA_HIFCR_CFEIF7_Pos',['../group___peripheral___registers___bits___definition.html#ga913da2290fb4ba8484a69b34e71840c7',1,'stm32f407xx_matlab.h']]], - ['dma_5fhifcr_5fchtif4_535',['DMA_HIFCR_CHTIF4',['../group___peripheral___registers___bits___definition.html#gaf8f0afa9a6526f7f4413766417a56be8',1,'stm32f407xx_matlab.h']]], - ['dma_5fhifcr_5fchtif4_5fmsk_536',['DMA_HIFCR_CHTIF4_Msk',['../group___peripheral___registers___bits___definition.html#gafa1aa9781098072d161c20890c3d1918',1,'stm32f407xx_matlab.h']]], - ['dma_5fhifcr_5fchtif4_5fpos_537',['DMA_HIFCR_CHTIF4_Pos',['../group___peripheral___registers___bits___definition.html#ga3415c8fd19bcb513fc96363d287784a4',1,'stm32f407xx_matlab.h']]], - ['dma_5fhifcr_5fchtif5_538',['DMA_HIFCR_CHTIF5',['../group___peripheral___registers___bits___definition.html#ga2cef7eeccd11737c1ebf5735284046cc',1,'stm32f407xx_matlab.h']]], - ['dma_5fhifcr_5fchtif5_5fmsk_539',['DMA_HIFCR_CHTIF5_Msk',['../group___peripheral___registers___bits___definition.html#gaa1ff3abfbb813d2e7c030d9b16786d00',1,'stm32f407xx_matlab.h']]], - ['dma_5fhifcr_5fchtif5_5fpos_540',['DMA_HIFCR_CHTIF5_Pos',['../group___peripheral___registers___bits___definition.html#ga3f5d41d4856f8ff464ce01e96e9f6e3f',1,'stm32f407xx_matlab.h']]], - ['dma_5fhifcr_5fchtif6_541',['DMA_HIFCR_CHTIF6',['../group___peripheral___registers___bits___definition.html#gaed7cbbbc0602d00e101e3f57aa3b696a',1,'stm32f407xx_matlab.h']]], - ['dma_5fhifcr_5fchtif6_5fmsk_542',['DMA_HIFCR_CHTIF6_Msk',['../group___peripheral___registers___bits___definition.html#ga6464e076a7b905e1b4a73e367fb4488e',1,'stm32f407xx_matlab.h']]], - ['dma_5fhifcr_5fchtif6_5fpos_543',['DMA_HIFCR_CHTIF6_Pos',['../group___peripheral___registers___bits___definition.html#gae4768327967dc957b842d2433d2cc5c2',1,'stm32f407xx_matlab.h']]], - ['dma_5fhifcr_5fchtif7_544',['DMA_HIFCR_CHTIF7',['../group___peripheral___registers___bits___definition.html#ga95e9989cbd70b18d833bb4cfcb8afce9',1,'stm32f407xx_matlab.h']]], - ['dma_5fhifcr_5fchtif7_5fmsk_545',['DMA_HIFCR_CHTIF7_Msk',['../group___peripheral___registers___bits___definition.html#ga256a0e76673c186a39f9f717af2e2287',1,'stm32f407xx_matlab.h']]], - ['dma_5fhifcr_5fchtif7_5fpos_546',['DMA_HIFCR_CHTIF7_Pos',['../group___peripheral___registers___bits___definition.html#gade6f40f4c574d22ec8527d8c27e78b58',1,'stm32f407xx_matlab.h']]], - ['dma_5fhifcr_5fctcif4_547',['DMA_HIFCR_CTCIF4',['../group___peripheral___registers___bits___definition.html#ga42e529507a40f0dc4c16da7cc6d659db',1,'stm32f407xx_matlab.h']]], - ['dma_5fhifcr_5fctcif4_5fmsk_548',['DMA_HIFCR_CTCIF4_Msk',['../group___peripheral___registers___bits___definition.html#gae02d30716d6c3e975c13073ae65f69e5',1,'stm32f407xx_matlab.h']]], - ['dma_5fhifcr_5fctcif4_5fpos_549',['DMA_HIFCR_CTCIF4_Pos',['../group___peripheral___registers___bits___definition.html#gaeaf0336605023f5db079294ebe4ea822',1,'stm32f407xx_matlab.h']]], - ['dma_5fhifcr_5fctcif5_550',['DMA_HIFCR_CTCIF5',['../group___peripheral___registers___bits___definition.html#gaa55d19705147a6ee16effe9ec1012a72',1,'stm32f407xx_matlab.h']]], - ['dma_5fhifcr_5fctcif5_5fmsk_551',['DMA_HIFCR_CTCIF5_Msk',['../group___peripheral___registers___bits___definition.html#ga0bec2f8ae9244ef971aed8aa9253f7fe',1,'stm32f407xx_matlab.h']]], - ['dma_5fhifcr_5fctcif5_5fpos_552',['DMA_HIFCR_CTCIF5_Pos',['../group___peripheral___registers___bits___definition.html#ga9e2ab5fecba1f2673c14bc21e9052dc9',1,'stm32f407xx_matlab.h']]], - ['dma_5fhifcr_5fctcif6_553',['DMA_HIFCR_CTCIF6',['../group___peripheral___registers___bits___definition.html#gacd88be16962491e41e586f5109014bc6',1,'stm32f407xx_matlab.h']]], - ['dma_5fhifcr_5fctcif6_5fmsk_554',['DMA_HIFCR_CTCIF6_Msk',['../group___peripheral___registers___bits___definition.html#ga8367ef52cfc4bb3dd4e1bbf8c01fc189',1,'stm32f407xx_matlab.h']]], - ['dma_5fhifcr_5fctcif6_5fpos_555',['DMA_HIFCR_CTCIF6_Pos',['../group___peripheral___registers___bits___definition.html#ga194f6a4be6fd796e114fb77ea2f15220',1,'stm32f407xx_matlab.h']]], - ['dma_5fhifcr_5fctcif7_556',['DMA_HIFCR_CTCIF7',['../group___peripheral___registers___bits___definition.html#gadf8056629f4948fb236b4339e213cc69',1,'stm32f407xx_matlab.h']]], - ['dma_5fhifcr_5fctcif7_5fmsk_557',['DMA_HIFCR_CTCIF7_Msk',['../group___peripheral___registers___bits___definition.html#gade1f557e9a94cd3841f22f0955ab2a43',1,'stm32f407xx_matlab.h']]], - ['dma_5fhifcr_5fctcif7_5fpos_558',['DMA_HIFCR_CTCIF7_Pos',['../group___peripheral___registers___bits___definition.html#ga42d3e6cfd2eef1e3d12e677af584447e',1,'stm32f407xx_matlab.h']]], - ['dma_5fhifcr_5fcteif4_559',['DMA_HIFCR_CTEIF4',['../group___peripheral___registers___bits___definition.html#ga9e05ff4fc6bace9cc6c0f0d4ec7b3314',1,'stm32f407xx_matlab.h']]], - ['dma_5fhifcr_5fcteif4_5fmsk_560',['DMA_HIFCR_CTEIF4_Msk',['../group___peripheral___registers___bits___definition.html#ga5aa004e3db2fb6845a6678bd30d9a604',1,'stm32f407xx_matlab.h']]], - ['dma_5fhifcr_5fcteif4_5fpos_561',['DMA_HIFCR_CTEIF4_Pos',['../group___peripheral___registers___bits___definition.html#ga9d1ac1b86e7505eceef920910bd930e2',1,'stm32f407xx_matlab.h']]], - ['dma_5fhifcr_5fcteif5_562',['DMA_HIFCR_CTEIF5',['../group___peripheral___registers___bits___definition.html#ga33394fe20a3567c8baaeb15ad9aab586',1,'stm32f407xx_matlab.h']]], - ['dma_5fhifcr_5fcteif5_5fmsk_563',['DMA_HIFCR_CTEIF5_Msk',['../group___peripheral___registers___bits___definition.html#gaca104c26dd5e9190434023a88d0dc4ac',1,'stm32f407xx_matlab.h']]], - ['dma_5fhifcr_5fcteif5_5fpos_564',['DMA_HIFCR_CTEIF5_Pos',['../group___peripheral___registers___bits___definition.html#ga42493eb990d42aa17c178842ecef08bd',1,'stm32f407xx_matlab.h']]], - ['dma_5fhifcr_5fcteif6_565',['DMA_HIFCR_CTEIF6',['../group___peripheral___registers___bits___definition.html#ga69e01e2f6a5cd1c800321e4121f8e788',1,'stm32f407xx_matlab.h']]], - ['dma_5fhifcr_5fcteif6_5fmsk_566',['DMA_HIFCR_CTEIF6_Msk',['../group___peripheral___registers___bits___definition.html#ga4328c04dd38fc2360b7333d6e22d8f73',1,'stm32f407xx_matlab.h']]], - ['dma_5fhifcr_5fcteif6_5fpos_567',['DMA_HIFCR_CTEIF6_Pos',['../group___peripheral___registers___bits___definition.html#ga8e0f6b1fd4902396d59d0d9865bd329e',1,'stm32f407xx_matlab.h']]], - ['dma_5fhifcr_5fcteif7_568',['DMA_HIFCR_CTEIF7',['../group___peripheral___registers___bits___definition.html#ga84ab215e0b217547745beefb65dfefdf',1,'stm32f407xx_matlab.h']]], - ['dma_5fhifcr_5fcteif7_5fmsk_569',['DMA_HIFCR_CTEIF7_Msk',['../group___peripheral___registers___bits___definition.html#ga08c1daec30b9644c55db577867afe491',1,'stm32f407xx_matlab.h']]], - ['dma_5fhifcr_5fcteif7_5fpos_570',['DMA_HIFCR_CTEIF7_Pos',['../group___peripheral___registers___bits___definition.html#gafae9da1fff2402f645b428368a4aea14',1,'stm32f407xx_matlab.h']]], - ['dma_5fhisr_5fdmeif4_571',['DMA_HISR_DMEIF4',['../group___peripheral___registers___bits___definition.html#gaf716f1bc12ea70f49802d84fb77646e8',1,'stm32f407xx_matlab.h']]], - ['dma_5fhisr_5fdmeif4_5fmsk_572',['DMA_HISR_DMEIF4_Msk',['../group___peripheral___registers___bits___definition.html#gae3bcb3c175f9e00b37de22d0d5cc041d',1,'stm32f407xx_matlab.h']]], - ['dma_5fhisr_5fdmeif4_5fpos_573',['DMA_HISR_DMEIF4_Pos',['../group___peripheral___registers___bits___definition.html#ga88c83f6ccfd101de6926df1d9112fb4a',1,'stm32f407xx_matlab.h']]], - ['dma_5fhisr_5fdmeif5_574',['DMA_HISR_DMEIF5',['../group___peripheral___registers___bits___definition.html#gac5ee964eee9c88fa28d32ce3ea6478f2',1,'stm32f407xx_matlab.h']]], - ['dma_5fhisr_5fdmeif5_5fmsk_575',['DMA_HISR_DMEIF5_Msk',['../group___peripheral___registers___bits___definition.html#gae170cce8a55fc679cc5a50b1b947969d',1,'stm32f407xx_matlab.h']]], - ['dma_5fhisr_5fdmeif5_5fpos_576',['DMA_HISR_DMEIF5_Pos',['../group___peripheral___registers___bits___definition.html#ga327eb55ab7770ef13a50436627bc5edf',1,'stm32f407xx_matlab.h']]], - ['dma_5fhisr_5fdmeif6_577',['DMA_HISR_DMEIF6',['../group___peripheral___registers___bits___definition.html#gab7b58e7ba316d3fc296f4433b3e62c38',1,'stm32f407xx_matlab.h']]], - ['dma_5fhisr_5fdmeif6_5fmsk_578',['DMA_HISR_DMEIF6_Msk',['../group___peripheral___registers___bits___definition.html#ga903b58a651a1aaf08e3058d9aefb2e76',1,'stm32f407xx_matlab.h']]], - ['dma_5fhisr_5fdmeif6_5fpos_579',['DMA_HISR_DMEIF6_Pos',['../group___peripheral___registers___bits___definition.html#gaf94b5e23736cdcfd2980ed8339ea346c',1,'stm32f407xx_matlab.h']]], - ['dma_5fhisr_5fdmeif7_580',['DMA_HISR_DMEIF7',['../group___peripheral___registers___bits___definition.html#ga3bb23848f8a022a47ab4abd5aa9b7d39',1,'stm32f407xx_matlab.h']]], - ['dma_5fhisr_5fdmeif7_5fmsk_581',['DMA_HISR_DMEIF7_Msk',['../group___peripheral___registers___bits___definition.html#ga6c027560b6bf31fb7926439500c32d6c',1,'stm32f407xx_matlab.h']]], - ['dma_5fhisr_5fdmeif7_5fpos_582',['DMA_HISR_DMEIF7_Pos',['../group___peripheral___registers___bits___definition.html#ga9e3c0b6526917df4addd70f13f7b9417',1,'stm32f407xx_matlab.h']]], - ['dma_5fhisr_5ffeif4_583',['DMA_HISR_FEIF4',['../group___peripheral___registers___bits___definition.html#gacab90057201b1da9774308ff3fb6cfa1',1,'stm32f407xx_matlab.h']]], - ['dma_5fhisr_5ffeif4_5fmsk_584',['DMA_HISR_FEIF4_Msk',['../group___peripheral___registers___bits___definition.html#ga2dd4eb12e7b05343a0bddd0dd413ba4c',1,'stm32f407xx_matlab.h']]], - ['dma_5fhisr_5ffeif4_5fpos_585',['DMA_HISR_FEIF4_Pos',['../group___peripheral___registers___bits___definition.html#ga7d7e45dd9031bcf619e6ca233a56a2db',1,'stm32f407xx_matlab.h']]], - ['dma_5fhisr_5ffeif5_586',['DMA_HISR_FEIF5',['../group___peripheral___registers___bits___definition.html#ga0d62494b31bb830433ddd683f4872519',1,'stm32f407xx_matlab.h']]], - ['dma_5fhisr_5ffeif5_5fmsk_587',['DMA_HISR_FEIF5_Msk',['../group___peripheral___registers___bits___definition.html#ga0bc4fff852e4fcf19079f79234caf9ae',1,'stm32f407xx_matlab.h']]], - ['dma_5fhisr_5ffeif5_5fpos_588',['DMA_HISR_FEIF5_Pos',['../group___peripheral___registers___bits___definition.html#ga24d536ac56c423089622de3d22968843',1,'stm32f407xx_matlab.h']]], - ['dma_5fhisr_5ffeif6_589',['DMA_HISR_FEIF6',['../group___peripheral___registers___bits___definition.html#gafb297f94bde8d1aea580683d466ca8ca',1,'stm32f407xx_matlab.h']]], - ['dma_5fhisr_5ffeif6_5fmsk_590',['DMA_HISR_FEIF6_Msk',['../group___peripheral___registers___bits___definition.html#gaa1736288bfd961d56e8571bdc91bd65b',1,'stm32f407xx_matlab.h']]], - ['dma_5fhisr_5ffeif6_5fpos_591',['DMA_HISR_FEIF6_Pos',['../group___peripheral___registers___bits___definition.html#gaa5e631133a8a3dbcdad903d73cccb160',1,'stm32f407xx_matlab.h']]], - ['dma_5fhisr_5ffeif7_592',['DMA_HISR_FEIF7',['../group___peripheral___registers___bits___definition.html#gadea53385fca360f16c4474db1cf18bc1',1,'stm32f407xx_matlab.h']]], - ['dma_5fhisr_5ffeif7_5fmsk_593',['DMA_HISR_FEIF7_Msk',['../group___peripheral___registers___bits___definition.html#ga4fe1e3a74167419160edbbc759ca3789',1,'stm32f407xx_matlab.h']]], - ['dma_5fhisr_5ffeif7_5fpos_594',['DMA_HISR_FEIF7_Pos',['../group___peripheral___registers___bits___definition.html#ga419c7042fb7439840a04e5fd445731d2',1,'stm32f407xx_matlab.h']]], - ['dma_5fhisr_5fhtif4_595',['DMA_HISR_HTIF4',['../group___peripheral___registers___bits___definition.html#gadba8d24329c676d70560eda0b8c1e5b0',1,'stm32f407xx_matlab.h']]], - ['dma_5fhisr_5fhtif4_5fmsk_596',['DMA_HISR_HTIF4_Msk',['../group___peripheral___registers___bits___definition.html#ga6117628ef3e354f4e6ce4ac3656bcd70',1,'stm32f407xx_matlab.h']]], - ['dma_5fhisr_5fhtif4_5fpos_597',['DMA_HISR_HTIF4_Pos',['../group___peripheral___registers___bits___definition.html#gaf39dc71e13779a10a6855de4801528a2',1,'stm32f407xx_matlab.h']]], - ['dma_5fhisr_5fhtif5_598',['DMA_HISR_HTIF5',['../group___peripheral___registers___bits___definition.html#ga8617bf8160d1027879ffd354e04908d9',1,'stm32f407xx_matlab.h']]], - ['dma_5fhisr_5fhtif5_5fmsk_599',['DMA_HISR_HTIF5_Msk',['../group___peripheral___registers___bits___definition.html#gad021f5ec7b128f0493f3f0989ad154ce',1,'stm32f407xx_matlab.h']]], - ['dma_5fhisr_5fhtif5_5fpos_600',['DMA_HISR_HTIF5_Pos',['../group___peripheral___registers___bits___definition.html#ga922891bcfc085c0d080ce473b8515655',1,'stm32f407xx_matlab.h']]], - ['dma_5fhisr_5fhtif6_601',['DMA_HISR_HTIF6',['../group___peripheral___registers___bits___definition.html#ga0d39c14138e9ff216c203b288137144b',1,'stm32f407xx_matlab.h']]], - ['dma_5fhisr_5fhtif6_5fmsk_602',['DMA_HISR_HTIF6_Msk',['../group___peripheral___registers___bits___definition.html#ga722b24166ff10769a7f325a6bda26272',1,'stm32f407xx_matlab.h']]], - ['dma_5fhisr_5fhtif6_5fpos_603',['DMA_HISR_HTIF6_Pos',['../group___peripheral___registers___bits___definition.html#ga27460df561ea71167eb046d7993a3763',1,'stm32f407xx_matlab.h']]], - ['dma_5fhisr_5fhtif7_604',['DMA_HISR_HTIF7',['../group___peripheral___registers___bits___definition.html#gaf535d1a3209d2e2e0e616e2d7501525d',1,'stm32f407xx_matlab.h']]], - ['dma_5fhisr_5fhtif7_5fmsk_605',['DMA_HISR_HTIF7_Msk',['../group___peripheral___registers___bits___definition.html#ga32a223400ca195866f036f2a3cdf2029',1,'stm32f407xx_matlab.h']]], - ['dma_5fhisr_5fhtif7_5fpos_606',['DMA_HISR_HTIF7_Pos',['../group___peripheral___registers___bits___definition.html#ga2d1b08aa592736655c679f9f57275ecd',1,'stm32f407xx_matlab.h']]], - ['dma_5fhisr_5ftcif4_607',['DMA_HISR_TCIF4',['../group___peripheral___registers___bits___definition.html#gafcce25c245499f9e62cb757e1871d973',1,'stm32f407xx_matlab.h']]], - ['dma_5fhisr_5ftcif4_5fmsk_608',['DMA_HISR_TCIF4_Msk',['../group___peripheral___registers___bits___definition.html#ga0436cbb07d44b1049a8c9ff1e5438c48',1,'stm32f407xx_matlab.h']]], - ['dma_5fhisr_5ftcif4_5fpos_609',['DMA_HISR_TCIF4_Pos',['../group___peripheral___registers___bits___definition.html#ga98b35dac75c8a374912b8e99af926c97',1,'stm32f407xx_matlab.h']]], - ['dma_5fhisr_5ftcif5_610',['DMA_HISR_TCIF5',['../group___peripheral___registers___bits___definition.html#ga64f15eaf1dd30450d1d35ee517507321',1,'stm32f407xx_matlab.h']]], - ['dma_5fhisr_5ftcif5_5fmsk_611',['DMA_HISR_TCIF5_Msk',['../group___peripheral___registers___bits___definition.html#ga57c25c3b163cfb7c292d5ebce785a2b7',1,'stm32f407xx_matlab.h']]], - ['dma_5fhisr_5ftcif5_5fpos_612',['DMA_HISR_TCIF5_Pos',['../group___peripheral___registers___bits___definition.html#gad9ec95df27557b62d73eb337ef879433',1,'stm32f407xx_matlab.h']]], - ['dma_5fhisr_5ftcif6_613',['DMA_HISR_TCIF6',['../group___peripheral___registers___bits___definition.html#gad29468aa609150e241d9ae62c477cf45',1,'stm32f407xx_matlab.h']]], - ['dma_5fhisr_5ftcif6_5fmsk_614',['DMA_HISR_TCIF6_Msk',['../group___peripheral___registers___bits___definition.html#ga8504bd4d44054ecc0974a59578f6f6ce',1,'stm32f407xx_matlab.h']]], - ['dma_5fhisr_5ftcif6_5fpos_615',['DMA_HISR_TCIF6_Pos',['../group___peripheral___registers___bits___definition.html#ga9d6ca1e8f590dcd64fae7d0aab508111',1,'stm32f407xx_matlab.h']]], - ['dma_5fhisr_5ftcif7_616',['DMA_HISR_TCIF7',['../group___peripheral___registers___bits___definition.html#gad20a0a5e103def436d4e329fc0888482',1,'stm32f407xx_matlab.h']]], - ['dma_5fhisr_5ftcif7_5fmsk_617',['DMA_HISR_TCIF7_Msk',['../group___peripheral___registers___bits___definition.html#ga7cecdf83cc7589761412e00b3d71e657',1,'stm32f407xx_matlab.h']]], - ['dma_5fhisr_5ftcif7_5fpos_618',['DMA_HISR_TCIF7_Pos',['../group___peripheral___registers___bits___definition.html#ga6de32d4d0c47fc9ee420f6f94e02f275',1,'stm32f407xx_matlab.h']]], - ['dma_5fhisr_5fteif4_619',['DMA_HISR_TEIF4',['../group___peripheral___registers___bits___definition.html#ga9005d4b958193fbd701c879eede467c1',1,'stm32f407xx_matlab.h']]], - ['dma_5fhisr_5fteif4_5fmsk_620',['DMA_HISR_TEIF4_Msk',['../group___peripheral___registers___bits___definition.html#gac851827ca11788591231f3d29f4ecc1c',1,'stm32f407xx_matlab.h']]], - ['dma_5fhisr_5fteif4_5fpos_621',['DMA_HISR_TEIF4_Pos',['../group___peripheral___registers___bits___definition.html#ga792ee749e2d12f4aa0cf3daca6b35057',1,'stm32f407xx_matlab.h']]], - ['dma_5fhisr_5fteif5_622',['DMA_HISR_TEIF5',['../group___peripheral___registers___bits___definition.html#gaf16fb0e5d87f704c89824f961bfb7637',1,'stm32f407xx_matlab.h']]], - ['dma_5fhisr_5fteif5_5fmsk_623',['DMA_HISR_TEIF5_Msk',['../group___peripheral___registers___bits___definition.html#ga706c81ee1877cd6f10dd96fd1668d0f8',1,'stm32f407xx_matlab.h']]], - ['dma_5fhisr_5fteif5_5fpos_624',['DMA_HISR_TEIF5_Pos',['../group___peripheral___registers___bits___definition.html#gaa6e505b2a29cc145b957dd8ea1c9c63f',1,'stm32f407xx_matlab.h']]], - ['dma_5fhisr_5fteif6_625',['DMA_HISR_TEIF6',['../group___peripheral___registers___bits___definition.html#ga1a7ec01955fb504a5aa4f9f16a9ac52c',1,'stm32f407xx_matlab.h']]], - ['dma_5fhisr_5fteif6_5fmsk_626',['DMA_HISR_TEIF6_Msk',['../group___peripheral___registers___bits___definition.html#gac6d3a65ce374edd183b14be4f40356e2',1,'stm32f407xx_matlab.h']]], - ['dma_5fhisr_5fteif6_5fpos_627',['DMA_HISR_TEIF6_Pos',['../group___peripheral___registers___bits___definition.html#ga83a1443bc4b15ef4c44d26611688b2d4',1,'stm32f407xx_matlab.h']]], - ['dma_5fhisr_5fteif7_628',['DMA_HISR_TEIF7',['../group___peripheral___registers___bits___definition.html#ga960f094539b5afc7f9d5e45b7909afe6',1,'stm32f407xx_matlab.h']]], - ['dma_5fhisr_5fteif7_5fmsk_629',['DMA_HISR_TEIF7_Msk',['../group___peripheral___registers___bits___definition.html#ga2754f465bbced1dec2e45bbb8fc9a3c4',1,'stm32f407xx_matlab.h']]], - ['dma_5fhisr_5fteif7_5fpos_630',['DMA_HISR_TEIF7_Pos',['../group___peripheral___registers___bits___definition.html#gac9f7912fe43718644df70d92495a2fe8',1,'stm32f407xx_matlab.h']]], - ['dma_5flifcr_5fcdmeif0_631',['DMA_LIFCR_CDMEIF0',['../group___peripheral___registers___bits___definition.html#gafe80a122bf0537e8c95877ccf2b7b6d9',1,'stm32f407xx_matlab.h']]], - ['dma_5flifcr_5fcdmeif0_5fmsk_632',['DMA_LIFCR_CDMEIF0_Msk',['../group___peripheral___registers___bits___definition.html#gaad09384dd4e933d5ae8490599f09b60f',1,'stm32f407xx_matlab.h']]], - ['dma_5flifcr_5fcdmeif0_5fpos_633',['DMA_LIFCR_CDMEIF0_Pos',['../group___peripheral___registers___bits___definition.html#ga9328d47385259284470fe88126f161c1',1,'stm32f407xx_matlab.h']]], - ['dma_5flifcr_5fcdmeif1_634',['DMA_LIFCR_CDMEIF1',['../group___peripheral___registers___bits___definition.html#ga9a5aea54a390886f7de82e87e6dfc936',1,'stm32f407xx_matlab.h']]], - ['dma_5flifcr_5fcdmeif1_5fmsk_635',['DMA_LIFCR_CDMEIF1_Msk',['../group___peripheral___registers___bits___definition.html#ga4d5941929a8582fdaf1e413063b56728',1,'stm32f407xx_matlab.h']]], - ['dma_5flifcr_5fcdmeif1_5fpos_636',['DMA_LIFCR_CDMEIF1_Pos',['../group___peripheral___registers___bits___definition.html#gaf7f3844824818f2a180921ec71e10165',1,'stm32f407xx_matlab.h']]], - ['dma_5flifcr_5fcdmeif2_637',['DMA_LIFCR_CDMEIF2',['../group___peripheral___registers___bits___definition.html#ga7680fc5f5e6c0032044f1d8ab7766de8',1,'stm32f407xx_matlab.h']]], - ['dma_5flifcr_5fcdmeif2_5fmsk_638',['DMA_LIFCR_CDMEIF2_Msk',['../group___peripheral___registers___bits___definition.html#gacac8f0e26e7170255fb9d9fd31b1ccbe',1,'stm32f407xx_matlab.h']]], - ['dma_5flifcr_5fcdmeif2_5fpos_639',['DMA_LIFCR_CDMEIF2_Pos',['../group___peripheral___registers___bits___definition.html#gaefc5081ac74c4a7cd7b9294d8be92251',1,'stm32f407xx_matlab.h']]], - ['dma_5flifcr_5fcdmeif3_640',['DMA_LIFCR_CDMEIF3',['../group___peripheral___registers___bits___definition.html#gabea10cdf2d3b0773b4e6b7fc9422f361',1,'stm32f407xx_matlab.h']]], - ['dma_5flifcr_5fcdmeif3_5fmsk_641',['DMA_LIFCR_CDMEIF3_Msk',['../group___peripheral___registers___bits___definition.html#ga87881333fb961788c6b31d08a9705cc5',1,'stm32f407xx_matlab.h']]], - ['dma_5flifcr_5fcdmeif3_5fpos_642',['DMA_LIFCR_CDMEIF3_Pos',['../group___peripheral___registers___bits___definition.html#gae5766d430a30ebb01d926b73c4838ee7',1,'stm32f407xx_matlab.h']]], - ['dma_5flifcr_5fcfeif0_643',['DMA_LIFCR_CFEIF0',['../group___peripheral___registers___bits___definition.html#gadf6b8892189f3779f7fecf529ed87c74',1,'stm32f407xx_matlab.h']]], - ['dma_5flifcr_5fcfeif0_5fmsk_644',['DMA_LIFCR_CFEIF0_Msk',['../group___peripheral___registers___bits___definition.html#gac5e3b1026a57f00f382879e844835e95',1,'stm32f407xx_matlab.h']]], - ['dma_5flifcr_5fcfeif0_5fpos_645',['DMA_LIFCR_CFEIF0_Pos',['../group___peripheral___registers___bits___definition.html#ga89140d2a2a82950d5cbd470e264fb525',1,'stm32f407xx_matlab.h']]], - ['dma_5flifcr_5fcfeif1_646',['DMA_LIFCR_CFEIF1',['../group___peripheral___registers___bits___definition.html#ga96cea0049553ab806bbc956f52528c37',1,'stm32f407xx_matlab.h']]], - ['dma_5flifcr_5fcfeif1_5fmsk_647',['DMA_LIFCR_CFEIF1_Msk',['../group___peripheral___registers___bits___definition.html#ga0809a566feea19caa99820c0beb7593a',1,'stm32f407xx_matlab.h']]], - ['dma_5flifcr_5fcfeif1_5fpos_648',['DMA_LIFCR_CFEIF1_Pos',['../group___peripheral___registers___bits___definition.html#ga7449839b8ccb071b0297c04b3f308374',1,'stm32f407xx_matlab.h']]], - ['dma_5flifcr_5fcfeif2_649',['DMA_LIFCR_CFEIF2',['../group___peripheral___registers___bits___definition.html#gae0f58173c721a4cee3f3885b352fa2a3',1,'stm32f407xx_matlab.h']]], - ['dma_5flifcr_5fcfeif2_5fmsk_650',['DMA_LIFCR_CFEIF2_Msk',['../group___peripheral___registers___bits___definition.html#ga117212472340bb8a793f05a4dcb98f03',1,'stm32f407xx_matlab.h']]], - ['dma_5flifcr_5fcfeif2_5fpos_651',['DMA_LIFCR_CFEIF2_Pos',['../group___peripheral___registers___bits___definition.html#ga5cf455eeb40c690897a63399e06b980a',1,'stm32f407xx_matlab.h']]], - ['dma_5flifcr_5fcfeif3_652',['DMA_LIFCR_CFEIF3',['../group___peripheral___registers___bits___definition.html#gad9432964145dc55af9186aea425e9963',1,'stm32f407xx_matlab.h']]], - ['dma_5flifcr_5fcfeif3_5fmsk_653',['DMA_LIFCR_CFEIF3_Msk',['../group___peripheral___registers___bits___definition.html#ga1733762b49e7da8c32a4d27044966872',1,'stm32f407xx_matlab.h']]], - ['dma_5flifcr_5fcfeif3_5fpos_654',['DMA_LIFCR_CFEIF3_Pos',['../group___peripheral___registers___bits___definition.html#ga6ce98c26903f04095ebeb872ab8599e2',1,'stm32f407xx_matlab.h']]], - ['dma_5flifcr_5fchtif0_655',['DMA_LIFCR_CHTIF0',['../group___peripheral___registers___bits___definition.html#ga44f83ba08feb98240a553403d977b8d1',1,'stm32f407xx_matlab.h']]], - ['dma_5flifcr_5fchtif0_5fmsk_656',['DMA_LIFCR_CHTIF0_Msk',['../group___peripheral___registers___bits___definition.html#gaca0f3b2beb4ae475024f013bfbe7813e',1,'stm32f407xx_matlab.h']]], - ['dma_5flifcr_5fchtif0_5fpos_657',['DMA_LIFCR_CHTIF0_Pos',['../group___peripheral___registers___bits___definition.html#gae4745b0ea4d34ffb750b377de2865dee',1,'stm32f407xx_matlab.h']]], - ['dma_5flifcr_5fchtif1_658',['DMA_LIFCR_CHTIF1',['../group___peripheral___registers___bits___definition.html#gad2f38b0c141a9afb3943276dacdcb969',1,'stm32f407xx_matlab.h']]], - ['dma_5flifcr_5fchtif1_5fmsk_659',['DMA_LIFCR_CHTIF1_Msk',['../group___peripheral___registers___bits___definition.html#ga4c3edca2d07701c0b50a844454593d54',1,'stm32f407xx_matlab.h']]], - ['dma_5flifcr_5fchtif1_5fpos_660',['DMA_LIFCR_CHTIF1_Pos',['../group___peripheral___registers___bits___definition.html#ga2cceed053af9c55ee130b9cac3dfa40f',1,'stm32f407xx_matlab.h']]], - ['dma_5flifcr_5fchtif2_661',['DMA_LIFCR_CHTIF2',['../group___peripheral___registers___bits___definition.html#gae19254e8ad726a73c6edc01bc7cf2cfa',1,'stm32f407xx_matlab.h']]], - ['dma_5flifcr_5fchtif2_5fmsk_662',['DMA_LIFCR_CHTIF2_Msk',['../group___peripheral___registers___bits___definition.html#gac756f07e62c4b7f720924d67b42b9af7',1,'stm32f407xx_matlab.h']]], - ['dma_5flifcr_5fchtif2_5fpos_663',['DMA_LIFCR_CHTIF2_Pos',['../group___peripheral___registers___bits___definition.html#ga54fe74158bbf9ebfc8905b256c16b1aa',1,'stm32f407xx_matlab.h']]], - ['dma_5flifcr_5fchtif3_664',['DMA_LIFCR_CHTIF3',['../group___peripheral___registers___bits___definition.html#ga0ed3ab4e5d7975f985eb25dc65f99be3',1,'stm32f407xx_matlab.h']]], - ['dma_5flifcr_5fchtif3_5fmsk_665',['DMA_LIFCR_CHTIF3_Msk',['../group___peripheral___registers___bits___definition.html#ga36f893f7c820962403289cc0f05e58bd',1,'stm32f407xx_matlab.h']]], - ['dma_5flifcr_5fchtif3_5fpos_666',['DMA_LIFCR_CHTIF3_Pos',['../group___peripheral___registers___bits___definition.html#ga879918dd49c563c83d9b0baf39f608c8',1,'stm32f407xx_matlab.h']]], - ['dma_5flifcr_5fctcif0_667',['DMA_LIFCR_CTCIF0',['../group___peripheral___registers___bits___definition.html#gab7a0b2cc41c63504195714614e59dc8e',1,'stm32f407xx_matlab.h']]], - ['dma_5flifcr_5fctcif0_5fmsk_668',['DMA_LIFCR_CTCIF0_Msk',['../group___peripheral___registers___bits___definition.html#ga5a99e08422f2f1ab8858824e873f0a5d',1,'stm32f407xx_matlab.h']]], - ['dma_5flifcr_5fctcif0_5fpos_669',['DMA_LIFCR_CTCIF0_Pos',['../group___peripheral___registers___bits___definition.html#gafee1c266c0c7d8ae75506988c24f197a',1,'stm32f407xx_matlab.h']]], - ['dma_5flifcr_5fctcif1_670',['DMA_LIFCR_CTCIF1',['../group___peripheral___registers___bits___definition.html#ga7494c54901b8f5bcb4894d20b8cfafed',1,'stm32f407xx_matlab.h']]], - ['dma_5flifcr_5fctcif1_5fmsk_671',['DMA_LIFCR_CTCIF1_Msk',['../group___peripheral___registers___bits___definition.html#ga81fc3bbc2471af2fc722698c394b5595',1,'stm32f407xx_matlab.h']]], - ['dma_5flifcr_5fctcif1_5fpos_672',['DMA_LIFCR_CTCIF1_Pos',['../group___peripheral___registers___bits___definition.html#gab2be6c298222759f49d71995f225a9c8',1,'stm32f407xx_matlab.h']]], - ['dma_5flifcr_5fctcif2_673',['DMA_LIFCR_CTCIF2',['../group___peripheral___registers___bits___definition.html#ga52d6df2b5ab2b43da273a702fe139b59',1,'stm32f407xx_matlab.h']]], - ['dma_5flifcr_5fctcif2_5fmsk_674',['DMA_LIFCR_CTCIF2_Msk',['../group___peripheral___registers___bits___definition.html#ga19e090383d9196956fa52d732415263d',1,'stm32f407xx_matlab.h']]], - ['dma_5flifcr_5fctcif2_5fpos_675',['DMA_LIFCR_CTCIF2_Pos',['../group___peripheral___registers___bits___definition.html#ga80de3a47390cdc24fdbb7a1c101d52df',1,'stm32f407xx_matlab.h']]], - ['dma_5flifcr_5fctcif3_676',['DMA_LIFCR_CTCIF3',['../group___peripheral___registers___bits___definition.html#ga5210736d34dc24eb9507975921233137',1,'stm32f407xx_matlab.h']]], - ['dma_5flifcr_5fctcif3_5fmsk_677',['DMA_LIFCR_CTCIF3_Msk',['../group___peripheral___registers___bits___definition.html#ga9ae2b6bed517a5d5f1f39e8fdd5ff18a',1,'stm32f407xx_matlab.h']]], - ['dma_5flifcr_5fctcif3_5fpos_678',['DMA_LIFCR_CTCIF3_Pos',['../group___peripheral___registers___bits___definition.html#ga2297c4815dff938a02b0af13da8c42cd',1,'stm32f407xx_matlab.h']]], - ['dma_5flifcr_5fcteif0_679',['DMA_LIFCR_CTEIF0',['../group___peripheral___registers___bits___definition.html#ga5824a64683ce2039260c952d989bf420',1,'stm32f407xx_matlab.h']]], - ['dma_5flifcr_5fcteif0_5fmsk_680',['DMA_LIFCR_CTEIF0_Msk',['../group___peripheral___registers___bits___definition.html#ga1e2bd6764a2c823750659f82e6ab82e4',1,'stm32f407xx_matlab.h']]], - ['dma_5flifcr_5fcteif0_5fpos_681',['DMA_LIFCR_CTEIF0_Pos',['../group___peripheral___registers___bits___definition.html#gac20301e14197382e7e5f532fe6d3c21f',1,'stm32f407xx_matlab.h']]], - ['dma_5flifcr_5fcteif1_682',['DMA_LIFCR_CTEIF1',['../group___peripheral___registers___bits___definition.html#gaf6d8adf52567aee2969492db65d448d4',1,'stm32f407xx_matlab.h']]], - ['dma_5flifcr_5fcteif1_5fmsk_683',['DMA_LIFCR_CTEIF1_Msk',['../group___peripheral___registers___bits___definition.html#gaf08b5acf028d011d3ccf519066f4e58e',1,'stm32f407xx_matlab.h']]], - ['dma_5flifcr_5fcteif1_5fpos_684',['DMA_LIFCR_CTEIF1_Pos',['../group___peripheral___registers___bits___definition.html#ga4e5563a90f78b2aa62d4cc65fd2ea2e8',1,'stm32f407xx_matlab.h']]], - ['dma_5flifcr_5fcteif2_685',['DMA_LIFCR_CTEIF2',['../group___peripheral___registers___bits___definition.html#gaa9d761752657a3d268da5434a04c6c6a',1,'stm32f407xx_matlab.h']]], - ['dma_5flifcr_5fcteif2_5fmsk_686',['DMA_LIFCR_CTEIF2_Msk',['../group___peripheral___registers___bits___definition.html#ga27d209fe8a4bec205b32f36435895a3a',1,'stm32f407xx_matlab.h']]], - ['dma_5flifcr_5fcteif2_5fpos_687',['DMA_LIFCR_CTEIF2_Pos',['../group___peripheral___registers___bits___definition.html#ga8e4b3f5d3bbfba08a7716e8e14c7c7b2',1,'stm32f407xx_matlab.h']]], - ['dma_5flifcr_5fcteif3_688',['DMA_LIFCR_CTEIF3',['../group___peripheral___registers___bits___definition.html#ga0a51c601387d1ae49333d5ace8ae86ee',1,'stm32f407xx_matlab.h']]], - ['dma_5flifcr_5fcteif3_5fmsk_689',['DMA_LIFCR_CTEIF3_Msk',['../group___peripheral___registers___bits___definition.html#gafeab970135917ddac9a49e5c5d246188',1,'stm32f407xx_matlab.h']]], - ['dma_5flifcr_5fcteif3_5fpos_690',['DMA_LIFCR_CTEIF3_Pos',['../group___peripheral___registers___bits___definition.html#ga200a4cd37d937325c0f891cd99b879a5',1,'stm32f407xx_matlab.h']]], - ['dma_5flisr_5fdmeif0_691',['DMA_LISR_DMEIF0',['../group___peripheral___registers___bits___definition.html#ga72de97ebc9d063dceb38bada91c44878',1,'stm32f407xx_matlab.h']]], - ['dma_5flisr_5fdmeif0_5fmsk_692',['DMA_LISR_DMEIF0_Msk',['../group___peripheral___registers___bits___definition.html#ga66347e1824698903c1533784c2413f84',1,'stm32f407xx_matlab.h']]], - ['dma_5flisr_5fdmeif0_5fpos_693',['DMA_LISR_DMEIF0_Pos',['../group___peripheral___registers___bits___definition.html#ga143abdc2acba3fb3ff2e3bc76f8cbf9d',1,'stm32f407xx_matlab.h']]], - ['dma_5flisr_5fdmeif1_694',['DMA_LISR_DMEIF1',['../group___peripheral___registers___bits___definition.html#gaa4903814bfc12dd6193416374fbddf8c',1,'stm32f407xx_matlab.h']]], - ['dma_5flisr_5fdmeif1_5fmsk_695',['DMA_LISR_DMEIF1_Msk',['../group___peripheral___registers___bits___definition.html#ga71ddcdc61bbf235161b59b2fa356fa3b',1,'stm32f407xx_matlab.h']]], - ['dma_5flisr_5fdmeif1_5fpos_696',['DMA_LISR_DMEIF1_Pos',['../group___peripheral___registers___bits___definition.html#ga863200d27b1112aa53312c17b3130fb9',1,'stm32f407xx_matlab.h']]], - ['dma_5flisr_5fdmeif2_697',['DMA_LISR_DMEIF2',['../group___peripheral___registers___bits___definition.html#gabc7edcd7404f0dcf19a724dfad22026a',1,'stm32f407xx_matlab.h']]], - ['dma_5flisr_5fdmeif2_5fmsk_698',['DMA_LISR_DMEIF2_Msk',['../group___peripheral___registers___bits___definition.html#ga6f7a3d352057475b51e9627d497bf8d5',1,'stm32f407xx_matlab.h']]], - ['dma_5flisr_5fdmeif2_5fpos_699',['DMA_LISR_DMEIF2_Pos',['../group___peripheral___registers___bits___definition.html#gad852ffba4cb1b34e1cc77ba3f5075c03',1,'stm32f407xx_matlab.h']]], - ['dma_5flisr_5fdmeif3_700',['DMA_LISR_DMEIF3',['../group___peripheral___registers___bits___definition.html#ga01fd1397b41221f5bdf6f107cb92e196',1,'stm32f407xx_matlab.h']]], - ['dma_5flisr_5fdmeif3_5fmsk_701',['DMA_LISR_DMEIF3_Msk',['../group___peripheral___registers___bits___definition.html#gad4331e1ec530a0dc0cbee400d5950b3a',1,'stm32f407xx_matlab.h']]], - ['dma_5flisr_5fdmeif3_5fpos_702',['DMA_LISR_DMEIF3_Pos',['../group___peripheral___registers___bits___definition.html#ga9f039fe3193408bc81d812149996ea9f',1,'stm32f407xx_matlab.h']]], - ['dma_5flisr_5ffeif0_703',['DMA_LISR_FEIF0',['../group___peripheral___registers___bits___definition.html#ga79bcc3f8e773206a66aba95c6f889d6f',1,'stm32f407xx_matlab.h']]], - ['dma_5flisr_5ffeif0_5fmsk_704',['DMA_LISR_FEIF0_Msk',['../group___peripheral___registers___bits___definition.html#gac4ecaf3690c72bee4bd08746779615dd',1,'stm32f407xx_matlab.h']]], - ['dma_5flisr_5ffeif0_5fpos_705',['DMA_LISR_FEIF0_Pos',['../group___peripheral___registers___bits___definition.html#gaf0b4469def09a256f7ce049de364650a',1,'stm32f407xx_matlab.h']]], - ['dma_5flisr_5ffeif1_706',['DMA_LISR_FEIF1',['../group___peripheral___registers___bits___definition.html#gafbc4fecde60c09e12f10113a156bb922',1,'stm32f407xx_matlab.h']]], - ['dma_5flisr_5ffeif1_5fmsk_707',['DMA_LISR_FEIF1_Msk',['../group___peripheral___registers___bits___definition.html#gaa932a51d97ae0952a1cf37b876ac9cbc',1,'stm32f407xx_matlab.h']]], - ['dma_5flisr_5ffeif1_5fpos_708',['DMA_LISR_FEIF1_Pos',['../group___peripheral___registers___bits___definition.html#ga4f8b90ddc0ba4459e396755e1fcc156f',1,'stm32f407xx_matlab.h']]], - ['dma_5flisr_5ffeif2_709',['DMA_LISR_FEIF2',['../group___peripheral___registers___bits___definition.html#ga99c42b194213872753460ef9b7745213',1,'stm32f407xx_matlab.h']]], - ['dma_5flisr_5ffeif2_5fmsk_710',['DMA_LISR_FEIF2_Msk',['../group___peripheral___registers___bits___definition.html#ga2d4c97aa0bf50b5ff36e271bde6b2285',1,'stm32f407xx_matlab.h']]], - ['dma_5flisr_5ffeif2_5fpos_711',['DMA_LISR_FEIF2_Pos',['../group___peripheral___registers___bits___definition.html#ga53433f2c39d945b72231cff33c0b6ccb',1,'stm32f407xx_matlab.h']]], - ['dma_5flisr_5ffeif3_712',['DMA_LISR_FEIF3',['../group___peripheral___registers___bits___definition.html#ga5367443a1378eef82aed62ca22763952',1,'stm32f407xx_matlab.h']]], - ['dma_5flisr_5ffeif3_5fmsk_713',['DMA_LISR_FEIF3_Msk',['../group___peripheral___registers___bits___definition.html#ga46bd312d438cb54d4b68b189cf120fd1',1,'stm32f407xx_matlab.h']]], - ['dma_5flisr_5ffeif3_5fpos_714',['DMA_LISR_FEIF3_Pos',['../group___peripheral___registers___bits___definition.html#gace4ae0196dace02aceafe1fe77b6e6d7',1,'stm32f407xx_matlab.h']]], - ['dma_5flisr_5fhtif0_715',['DMA_LISR_HTIF0',['../group___peripheral___registers___bits___definition.html#ga6181727d13abbc46283ff22ce359e3b9',1,'stm32f407xx_matlab.h']]], - ['dma_5flisr_5fhtif0_5fmsk_716',['DMA_LISR_HTIF0_Msk',['../group___peripheral___registers___bits___definition.html#ga8c5a05c426a6fc95eee5f6b387139293',1,'stm32f407xx_matlab.h']]], - ['dma_5flisr_5fhtif0_5fpos_717',['DMA_LISR_HTIF0_Pos',['../group___peripheral___registers___bits___definition.html#ga3e84488e6b41b533d99b63e3a08008da',1,'stm32f407xx_matlab.h']]], - ['dma_5flisr_5fhtif1_718',['DMA_LISR_HTIF1',['../group___peripheral___registers___bits___definition.html#ga04304a9f8891e325247c0aaa4c9fac72',1,'stm32f407xx_matlab.h']]], - ['dma_5flisr_5fhtif1_5fmsk_719',['DMA_LISR_HTIF1_Msk',['../group___peripheral___registers___bits___definition.html#ga3c9343cd010bd919a13bf32f9a8d998f',1,'stm32f407xx_matlab.h']]], - ['dma_5flisr_5fhtif1_5fpos_720',['DMA_LISR_HTIF1_Pos',['../group___peripheral___registers___bits___definition.html#ga00c7637307de891e63bc8ca8cb7750f4',1,'stm32f407xx_matlab.h']]], - ['dma_5flisr_5fhtif2_721',['DMA_LISR_HTIF2',['../group___peripheral___registers___bits___definition.html#ga6ca25185d14a1f0c208ec8ceadc787a6',1,'stm32f407xx_matlab.h']]], - ['dma_5flisr_5fhtif2_5fmsk_722',['DMA_LISR_HTIF2_Msk',['../group___peripheral___registers___bits___definition.html#ga83c87fe2679a6130003dd72b363e9c53',1,'stm32f407xx_matlab.h']]], - ['dma_5flisr_5fhtif2_5fpos_723',['DMA_LISR_HTIF2_Pos',['../group___peripheral___registers___bits___definition.html#ga2700c5fdeaa7186a38c920f5ec85ea49',1,'stm32f407xx_matlab.h']]], - ['dma_5flisr_5fhtif3_724',['DMA_LISR_HTIF3',['../group___peripheral___registers___bits___definition.html#gaa10c891ee2ec333b7f87eea5886d574f',1,'stm32f407xx_matlab.h']]], - ['dma_5flisr_5fhtif3_5fmsk_725',['DMA_LISR_HTIF3_Msk',['../group___peripheral___registers___bits___definition.html#ga202e6ae73e145494851e4c40f5c2eb2e',1,'stm32f407xx_matlab.h']]], - ['dma_5flisr_5fhtif3_5fpos_726',['DMA_LISR_HTIF3_Pos',['../group___peripheral___registers___bits___definition.html#gabc365b9d116f7bf0fb0bdb4a36b025f0',1,'stm32f407xx_matlab.h']]], - ['dma_5flisr_5ftcif0_727',['DMA_LISR_TCIF0',['../group___peripheral___registers___bits___definition.html#gadbc3f7e52c0688bed4b71fa37666901d',1,'stm32f407xx_matlab.h']]], - ['dma_5flisr_5ftcif0_5fmsk_728',['DMA_LISR_TCIF0_Msk',['../group___peripheral___registers___bits___definition.html#gae0a6dc2ab51b3f572bf7dba9ee25354b',1,'stm32f407xx_matlab.h']]], - ['dma_5flisr_5ftcif0_5fpos_729',['DMA_LISR_TCIF0_Pos',['../group___peripheral___registers___bits___definition.html#ga7ca6a950eb06d3526feab88473965afe',1,'stm32f407xx_matlab.h']]], - ['dma_5flisr_5ftcif1_730',['DMA_LISR_TCIF1',['../group___peripheral___registers___bits___definition.html#gae02aec39ded937b3ce816d3df4520d9b',1,'stm32f407xx_matlab.h']]], - ['dma_5flisr_5ftcif1_5fmsk_731',['DMA_LISR_TCIF1_Msk',['../group___peripheral___registers___bits___definition.html#ga338a63d76a175d0ef90bd5469232cc69',1,'stm32f407xx_matlab.h']]], - ['dma_5flisr_5ftcif1_5fpos_732',['DMA_LISR_TCIF1_Pos',['../group___peripheral___registers___bits___definition.html#ga03abe37d6a707015bd502285aa4ab71c',1,'stm32f407xx_matlab.h']]], - ['dma_5flisr_5ftcif2_733',['DMA_LISR_TCIF2',['../group___peripheral___registers___bits___definition.html#gaf21350cce8c4cb5d7c6fcf5edc930cf8',1,'stm32f407xx_matlab.h']]], - ['dma_5flisr_5ftcif2_5fmsk_734',['DMA_LISR_TCIF2_Msk',['../group___peripheral___registers___bits___definition.html#gae271580139c8f7d241532d0c833afe06',1,'stm32f407xx_matlab.h']]], - ['dma_5flisr_5ftcif2_5fpos_735',['DMA_LISR_TCIF2_Pos',['../group___peripheral___registers___bits___definition.html#ga7d0716b2ad4127572e8b69fb92652f19',1,'stm32f407xx_matlab.h']]], - ['dma_5flisr_5ftcif3_736',['DMA_LISR_TCIF3',['../group___peripheral___registers___bits___definition.html#ga44e5bf8adbb2646d325cba8d5dd670d8',1,'stm32f407xx_matlab.h']]], - ['dma_5flisr_5ftcif3_5fmsk_737',['DMA_LISR_TCIF3_Msk',['../group___peripheral___registers___bits___definition.html#ga9fcbb22f764dbcd84f9f7679ba140fd8',1,'stm32f407xx_matlab.h']]], - ['dma_5flisr_5ftcif3_5fpos_738',['DMA_LISR_TCIF3_Pos',['../group___peripheral___registers___bits___definition.html#ga1917ec61d4f0b063c4d63c94d00f104c',1,'stm32f407xx_matlab.h']]], - ['dma_5flisr_5fteif0_739',['DMA_LISR_TEIF0',['../group___peripheral___registers___bits___definition.html#gad43cdafa5acfcd683b7a2ee8976dd8ba',1,'stm32f407xx_matlab.h']]], - ['dma_5flisr_5fteif0_5fmsk_740',['DMA_LISR_TEIF0_Msk',['../group___peripheral___registers___bits___definition.html#ga8213385927a3d6b07c3e035b331fead4',1,'stm32f407xx_matlab.h']]], - ['dma_5flisr_5fteif0_5fpos_741',['DMA_LISR_TEIF0_Pos',['../group___peripheral___registers___bits___definition.html#gae0ce7d8c40ff5bece107011e99d86e16',1,'stm32f407xx_matlab.h']]], - ['dma_5flisr_5fteif1_742',['DMA_LISR_TEIF1',['../group___peripheral___registers___bits___definition.html#ga0cd826db0b9ea5544d1a93beb90f8972',1,'stm32f407xx_matlab.h']]], - ['dma_5flisr_5fteif1_5fmsk_743',['DMA_LISR_TEIF1_Msk',['../group___peripheral___registers___bits___definition.html#ga014420a4087c5f7fa521536fed95a57b',1,'stm32f407xx_matlab.h']]], - ['dma_5flisr_5fteif1_5fpos_744',['DMA_LISR_TEIF1_Pos',['../group___peripheral___registers___bits___definition.html#ga81e7b142424b2a4901007ea232482931',1,'stm32f407xx_matlab.h']]], - ['dma_5flisr_5fteif2_745',['DMA_LISR_TEIF2',['../group___peripheral___registers___bits___definition.html#ga74d540802cadde42bdd6debae5d8ab89',1,'stm32f407xx_matlab.h']]], - ['dma_5flisr_5fteif2_5fmsk_746',['DMA_LISR_TEIF2_Msk',['../group___peripheral___registers___bits___definition.html#ga64f9f609e2612044dd911f853c401ce9',1,'stm32f407xx_matlab.h']]], - ['dma_5flisr_5fteif2_5fpos_747',['DMA_LISR_TEIF2_Pos',['../group___peripheral___registers___bits___definition.html#gac01bf79870cef24f0875200fba8ab778',1,'stm32f407xx_matlab.h']]], - ['dma_5flisr_5fteif3_748',['DMA_LISR_TEIF3',['../group___peripheral___registers___bits___definition.html#ga5dfaba3a5db7cdcbddf9ee5974b44c2f',1,'stm32f407xx_matlab.h']]], - ['dma_5flisr_5fteif3_5fmsk_749',['DMA_LISR_TEIF3_Msk',['../group___peripheral___registers___bits___definition.html#ga770b6645dff14ef5d2950aff2995ec72',1,'stm32f407xx_matlab.h']]], - ['dma_5flisr_5fteif3_5fpos_750',['DMA_LISR_TEIF3_Pos',['../group___peripheral___registers___bits___definition.html#ga3eb3514f45c12c124807ea04b5e5206d',1,'stm32f407xx_matlab.h']]], - ['dma_5fstream_5ftypedef_751',['DMA_Stream_TypeDef',['../struct_d_m_a___stream___type_def.html',1,'']]], - ['dma_5fsxcr_5fack_752',['DMA_SxCR_ACK',['../group___peripheral___registers___bits___definition.html#ga4f597f58faf86d2b78ad931079f57305',1,'stm32f407xx_matlab.h']]], - ['dma_5fsxcr_5fack_5fmsk_753',['DMA_SxCR_ACK_Msk',['../group___peripheral___registers___bits___definition.html#gae03b6c12b1fc9d635ce6abac4b15006e',1,'stm32f407xx_matlab.h']]], - ['dma_5fsxcr_5fack_5fpos_754',['DMA_SxCR_ACK_Pos',['../group___peripheral___registers___bits___definition.html#gad4c9d3fe3ecd436e1e33bf246a8a1d81',1,'stm32f407xx_matlab.h']]], - ['dma_5fsxcr_5fchsel_755',['DMA_SxCR_CHSEL',['../group___peripheral___registers___bits___definition.html#gadf353426d72702c7801416ba36d53dc6',1,'stm32f407xx_matlab.h']]], - ['dma_5fsxcr_5fchsel_5f0_756',['DMA_SxCR_CHSEL_0',['../group___peripheral___registers___bits___definition.html#ga17d34dad5c7bdb97fdcadaebfed80d90',1,'stm32f407xx_matlab.h']]], - ['dma_5fsxcr_5fchsel_5f1_757',['DMA_SxCR_CHSEL_1',['../group___peripheral___registers___bits___definition.html#gafa59d7ef4d7e0895f18ca4ef1210edae',1,'stm32f407xx_matlab.h']]], - ['dma_5fsxcr_5fchsel_5f2_758',['DMA_SxCR_CHSEL_2',['../group___peripheral___registers___bits___definition.html#gae001e60d3fd84c18bb5e2f96b695af38',1,'stm32f407xx_matlab.h']]], - ['dma_5fsxcr_5fchsel_5fmsk_759',['DMA_SxCR_CHSEL_Msk',['../group___peripheral___registers___bits___definition.html#ga27c7e607fbf7db7b5515bacbb9070346',1,'stm32f407xx_matlab.h']]], - ['dma_5fsxcr_5fchsel_5fpos_760',['DMA_SxCR_CHSEL_Pos',['../group___peripheral___registers___bits___definition.html#ga79fe8c72b18021aec9a18b68b9df324c',1,'stm32f407xx_matlab.h']]], - ['dma_5fsxcr_5fcirc_761',['DMA_SxCR_CIRC',['../group___peripheral___registers___bits___definition.html#gadc248dbc519cc580621cdadcdd8741fb',1,'stm32f407xx_matlab.h']]], - ['dma_5fsxcr_5fcirc_5fmsk_762',['DMA_SxCR_CIRC_Msk',['../group___peripheral___registers___bits___definition.html#ga873f1581fb2b88c20d6621143a5751ac',1,'stm32f407xx_matlab.h']]], - ['dma_5fsxcr_5fcirc_5fpos_763',['DMA_SxCR_CIRC_Pos',['../group___peripheral___registers___bits___definition.html#ga34774d3e38a7f910c9eb723208457a83',1,'stm32f407xx_matlab.h']]], - ['dma_5fsxcr_5fct_764',['DMA_SxCR_CT',['../group___peripheral___registers___bits___definition.html#gadd36c677ee53f56dc408cd549e64cf7d',1,'stm32f407xx_matlab.h']]], - ['dma_5fsxcr_5fct_5fmsk_765',['DMA_SxCR_CT_Msk',['../group___peripheral___registers___bits___definition.html#gaa3ef149321f19c6fdda5eea2d622b78e',1,'stm32f407xx_matlab.h']]], - ['dma_5fsxcr_5fct_5fpos_766',['DMA_SxCR_CT_Pos',['../group___peripheral___registers___bits___definition.html#ga5ae631c89765d8c92dde7eece6b28c58',1,'stm32f407xx_matlab.h']]], - ['dma_5fsxcr_5fdbm_767',['DMA_SxCR_DBM',['../group___peripheral___registers___bits___definition.html#ga53a1cde736b2afc5a394a67849f0c497',1,'stm32f407xx_matlab.h']]], - ['dma_5fsxcr_5fdbm_5fmsk_768',['DMA_SxCR_DBM_Msk',['../group___peripheral___registers___bits___definition.html#ga460b7d274a9e54d2ddabddc9832425b4',1,'stm32f407xx_matlab.h']]], - ['dma_5fsxcr_5fdbm_5fpos_769',['DMA_SxCR_DBM_Pos',['../group___peripheral___registers___bits___definition.html#ga9d74a7510babe49319a47e4fccaceba7',1,'stm32f407xx_matlab.h']]], - ['dma_5fsxcr_5fdir_770',['DMA_SxCR_DIR',['../group___peripheral___registers___bits___definition.html#ga16bc78076551c42cbdc084e9d0006bd4',1,'stm32f407xx_matlab.h']]], - ['dma_5fsxcr_5fdir_5f0_771',['DMA_SxCR_DIR_0',['../group___peripheral___registers___bits___definition.html#gadca9547536f3d2f76577275964b4875e',1,'stm32f407xx_matlab.h']]], - ['dma_5fsxcr_5fdir_5f1_772',['DMA_SxCR_DIR_1',['../group___peripheral___registers___bits___definition.html#gac52c8d6ecad03bfe531867fa7457f2ae',1,'stm32f407xx_matlab.h']]], - ['dma_5fsxcr_5fdir_5fmsk_773',['DMA_SxCR_DIR_Msk',['../group___peripheral___registers___bits___definition.html#gab6c4f77554490fc06ecbd63e0e81a696',1,'stm32f407xx_matlab.h']]], - ['dma_5fsxcr_5fdir_5fpos_774',['DMA_SxCR_DIR_Pos',['../group___peripheral___registers___bits___definition.html#ga8302200753a3788a5b45462513a84b6b',1,'stm32f407xx_matlab.h']]], - ['dma_5fsxcr_5fdmeie_775',['DMA_SxCR_DMEIE',['../group___peripheral___registers___bits___definition.html#gacaecc56f94a9af756d077cf7df1b6c41',1,'stm32f407xx_matlab.h']]], - ['dma_5fsxcr_5fdmeie_5fmsk_776',['DMA_SxCR_DMEIE_Msk',['../group___peripheral___registers___bits___definition.html#ga640f196b45fc4e81ac468cbc3503148b',1,'stm32f407xx_matlab.h']]], - ['dma_5fsxcr_5fdmeie_5fpos_777',['DMA_SxCR_DMEIE_Pos',['../group___peripheral___registers___bits___definition.html#ga90d77b99e19ffb0ce8533726db577011',1,'stm32f407xx_matlab.h']]], - ['dma_5fsxcr_5fen_778',['DMA_SxCR_EN',['../group___peripheral___registers___bits___definition.html#gaabf69fe92e9a44167535365b0fe4ea9e',1,'stm32f407xx_matlab.h']]], - ['dma_5fsxcr_5fen_5fmsk_779',['DMA_SxCR_EN_Msk',['../group___peripheral___registers___bits___definition.html#ga038999913cf4b5608f4b06bde0f5b6f1',1,'stm32f407xx_matlab.h']]], - ['dma_5fsxcr_5fen_5fpos_780',['DMA_SxCR_EN_Pos',['../group___peripheral___registers___bits___definition.html#ga0ae3e4666ee54b89bca73e5ce40032a8',1,'stm32f407xx_matlab.h']]], - ['dma_5fsxcr_5fhtie_781',['DMA_SxCR_HTIE',['../group___peripheral___registers___bits___definition.html#ga13a7fe097608bc5031d42ba69effed20',1,'stm32f407xx_matlab.h']]], - ['dma_5fsxcr_5fhtie_5fmsk_782',['DMA_SxCR_HTIE_Msk',['../group___peripheral___registers___bits___definition.html#ga1b2b5b47a0da93f112effd85edf7e27b',1,'stm32f407xx_matlab.h']]], - ['dma_5fsxcr_5fhtie_5fpos_783',['DMA_SxCR_HTIE_Pos',['../group___peripheral___registers___bits___definition.html#ga7ed0223ba349ffb6e55d16415be0a92e',1,'stm32f407xx_matlab.h']]], - ['dma_5fsxcr_5fmburst_784',['DMA_SxCR_MBURST',['../group___peripheral___registers___bits___definition.html#ga5c1174bff38faf5d87b71521bce8f84f',1,'stm32f407xx_matlab.h']]], - ['dma_5fsxcr_5fmburst_5f0_785',['DMA_SxCR_MBURST_0',['../group___peripheral___registers___bits___definition.html#ga1e3931a8f14ffe008b8717e1b3232fca',1,'stm32f407xx_matlab.h']]], - ['dma_5fsxcr_5fmburst_5f1_786',['DMA_SxCR_MBURST_1',['../group___peripheral___registers___bits___definition.html#gaf28eac7212392083bbf1b3d475022b74',1,'stm32f407xx_matlab.h']]], - ['dma_5fsxcr_5fmburst_5fmsk_787',['DMA_SxCR_MBURST_Msk',['../group___peripheral___registers___bits___definition.html#gaa451942408f8a368a57eb9c45e43e7c8',1,'stm32f407xx_matlab.h']]], - ['dma_5fsxcr_5fmburst_5fpos_788',['DMA_SxCR_MBURST_Pos',['../group___peripheral___registers___bits___definition.html#gaf9bf6407dc86ae23902425ed20d90421',1,'stm32f407xx_matlab.h']]], - ['dma_5fsxcr_5fminc_789',['DMA_SxCR_MINC',['../group___peripheral___registers___bits___definition.html#ga771a295832a584a3777ede523a691719',1,'stm32f407xx_matlab.h']]], - ['dma_5fsxcr_5fminc_5fmsk_790',['DMA_SxCR_MINC_Msk',['../group___peripheral___registers___bits___definition.html#ga3b9b94c796c25b6dac673c711f74eb48',1,'stm32f407xx_matlab.h']]], - ['dma_5fsxcr_5fminc_5fpos_791',['DMA_SxCR_MINC_Pos',['../group___peripheral___registers___bits___definition.html#ga11d90925c956a5196f58cf3fc89aa56f',1,'stm32f407xx_matlab.h']]], - ['dma_5fsxcr_5fmsize_792',['DMA_SxCR_MSIZE',['../group___peripheral___registers___bits___definition.html#gae9a98cb706a722d726d8ec6e9fe4a773',1,'stm32f407xx_matlab.h']]], - ['dma_5fsxcr_5fmsize_5f0_793',['DMA_SxCR_MSIZE_0',['../group___peripheral___registers___bits___definition.html#ga39adb60b3394b61366691b45b8c2b80f',1,'stm32f407xx_matlab.h']]], - ['dma_5fsxcr_5fmsize_5f1_794',['DMA_SxCR_MSIZE_1',['../group___peripheral___registers___bits___definition.html#gaa5c2ef08ab52de52b4e1fd785f60e263',1,'stm32f407xx_matlab.h']]], - ['dma_5fsxcr_5fmsize_5fmsk_795',['DMA_SxCR_MSIZE_Msk',['../group___peripheral___registers___bits___definition.html#ga769dd95d6aa84f0bc0080891094cd5bd',1,'stm32f407xx_matlab.h']]], - ['dma_5fsxcr_5fmsize_5fpos_796',['DMA_SxCR_MSIZE_Pos',['../group___peripheral___registers___bits___definition.html#ga55693651f2994a1c09f7b47455638a6a',1,'stm32f407xx_matlab.h']]], - ['dma_5fsxcr_5fpburst_797',['DMA_SxCR_PBURST',['../group___peripheral___registers___bits___definition.html#ga502380abb155eb3b37a2ca9359e2da2e',1,'stm32f407xx_matlab.h']]], - ['dma_5fsxcr_5fpburst_5f0_798',['DMA_SxCR_PBURST_0',['../group___peripheral___registers___bits___definition.html#gadf0eee1ad1788868a194f95107057a16',1,'stm32f407xx_matlab.h']]], - ['dma_5fsxcr_5fpburst_5f1_799',['DMA_SxCR_PBURST_1',['../group___peripheral___registers___bits___definition.html#ga061207b2c654a0dd62e40187c9557eda',1,'stm32f407xx_matlab.h']]], - ['dma_5fsxcr_5fpburst_5fmsk_800',['DMA_SxCR_PBURST_Msk',['../group___peripheral___registers___bits___definition.html#ga0522a557e1c258b7973e76da59cb7bbb',1,'stm32f407xx_matlab.h']]], - ['dma_5fsxcr_5fpburst_5fpos_801',['DMA_SxCR_PBURST_Pos',['../group___peripheral___registers___bits___definition.html#ga596bbd1719434d9b94dc57641788484e',1,'stm32f407xx_matlab.h']]], - ['dma_5fsxcr_5fpfctrl_802',['DMA_SxCR_PFCTRL',['../group___peripheral___registers___bits___definition.html#ga11f412d256043bec3e01ceef7f2099f2',1,'stm32f407xx_matlab.h']]], - ['dma_5fsxcr_5fpfctrl_5fmsk_803',['DMA_SxCR_PFCTRL_Msk',['../group___peripheral___registers___bits___definition.html#gab67e3396d4689bc81191afda92e1864c',1,'stm32f407xx_matlab.h']]], - ['dma_5fsxcr_5fpfctrl_5fpos_804',['DMA_SxCR_PFCTRL_Pos',['../group___peripheral___registers___bits___definition.html#gac9b6e1601b8fe4d4315dabeb21d87871',1,'stm32f407xx_matlab.h']]], - ['dma_5fsxcr_5fpinc_805',['DMA_SxCR_PINC',['../group___peripheral___registers___bits___definition.html#ga29c5d5c559dd14646fdc170e74f1f03b',1,'stm32f407xx_matlab.h']]], - ['dma_5fsxcr_5fpinc_5fmsk_806',['DMA_SxCR_PINC_Msk',['../group___peripheral___registers___bits___definition.html#ga0829e862db027069781244f9820113ab',1,'stm32f407xx_matlab.h']]], - ['dma_5fsxcr_5fpinc_5fpos_807',['DMA_SxCR_PINC_Pos',['../group___peripheral___registers___bits___definition.html#ga6f2a2143daf87c92d37da6503762f7c5',1,'stm32f407xx_matlab.h']]], - ['dma_5fsxcr_5fpincos_808',['DMA_SxCR_PINCOS',['../group___peripheral___registers___bits___definition.html#gaeb929908d2e7fdef2136c20c93377c70',1,'stm32f407xx_matlab.h']]], - ['dma_5fsxcr_5fpincos_5fmsk_809',['DMA_SxCR_PINCOS_Msk',['../group___peripheral___registers___bits___definition.html#ga78df7ff746fecc4afaa5e980f11de4d6',1,'stm32f407xx_matlab.h']]], - ['dma_5fsxcr_5fpincos_5fpos_810',['DMA_SxCR_PINCOS_Pos',['../group___peripheral___registers___bits___definition.html#ga5e2c688c88288e3f899e47c4d11ca4fa',1,'stm32f407xx_matlab.h']]], - ['dma_5fsxcr_5fpl_811',['DMA_SxCR_PL',['../group___peripheral___registers___bits___definition.html#ga14c115d71a4e3b3c4da360108288154c',1,'stm32f407xx_matlab.h']]], - ['dma_5fsxcr_5fpl_5f0_812',['DMA_SxCR_PL_0',['../group___peripheral___registers___bits___definition.html#ga41b1b2f7bd6f0af932ff0fb7df9336b6',1,'stm32f407xx_matlab.h']]], - ['dma_5fsxcr_5fpl_5f1_813',['DMA_SxCR_PL_1',['../group___peripheral___registers___bits___definition.html#ga81817adc8c0ee54dea0f67a1a9e8eb77',1,'stm32f407xx_matlab.h']]], - ['dma_5fsxcr_5fpl_5fmsk_814',['DMA_SxCR_PL_Msk',['../group___peripheral___registers___bits___definition.html#ga3dc66d05a0b6c646926e155f584c2164',1,'stm32f407xx_matlab.h']]], - ['dma_5fsxcr_5fpl_5fpos_815',['DMA_SxCR_PL_Pos',['../group___peripheral___registers___bits___definition.html#gaf0df2c0e1e3fa3614d74ee91cefa8173',1,'stm32f407xx_matlab.h']]], - ['dma_5fsxcr_5fpsize_816',['DMA_SxCR_PSIZE',['../group___peripheral___registers___bits___definition.html#gaea0808f979c27b7b68d79ad511e95ea0',1,'stm32f407xx_matlab.h']]], - ['dma_5fsxcr_5fpsize_5f0_817',['DMA_SxCR_PSIZE_0',['../group___peripheral___registers___bits___definition.html#gab05cf3e3f7c9edae5c70d59b3b75b14f',1,'stm32f407xx_matlab.h']]], - ['dma_5fsxcr_5fpsize_5f1_818',['DMA_SxCR_PSIZE_1',['../group___peripheral___registers___bits___definition.html#ga8f376d0900380a3045cbeadd6a037302',1,'stm32f407xx_matlab.h']]], - ['dma_5fsxcr_5fpsize_5fmsk_819',['DMA_SxCR_PSIZE_Msk',['../group___peripheral___registers___bits___definition.html#ga1ddb21769dcff3c41c4bb61e66d8459a',1,'stm32f407xx_matlab.h']]], - ['dma_5fsxcr_5fpsize_5fpos_820',['DMA_SxCR_PSIZE_Pos',['../group___peripheral___registers___bits___definition.html#ga56479851c087f5fe7ea9656862ad35e1',1,'stm32f407xx_matlab.h']]], - ['dma_5fsxcr_5ftcie_821',['DMA_SxCR_TCIE',['../group___peripheral___registers___bits___definition.html#ga6ae47cc2cd2e985d29cb6b0bb65da1d7',1,'stm32f407xx_matlab.h']]], - ['dma_5fsxcr_5ftcie_5fmsk_822',['DMA_SxCR_TCIE_Msk',['../group___peripheral___registers___bits___definition.html#ga86e6592b451e33103e1d6d119046a5e3',1,'stm32f407xx_matlab.h']]], - ['dma_5fsxcr_5ftcie_5fpos_823',['DMA_SxCR_TCIE_Pos',['../group___peripheral___registers___bits___definition.html#ga04d5934cc3988e035dcb1bf40f6e755a',1,'stm32f407xx_matlab.h']]], - ['dma_5fsxcr_5fteie_824',['DMA_SxCR_TEIE',['../group___peripheral___registers___bits___definition.html#gaeee99c36ba3ea56cdb4f73a0b01fb602',1,'stm32f407xx_matlab.h']]], - ['dma_5fsxcr_5fteie_5fmsk_825',['DMA_SxCR_TEIE_Msk',['../group___peripheral___registers___bits___definition.html#ga7e7331240fc8545d3dba92568b243039',1,'stm32f407xx_matlab.h']]], - ['dma_5fsxcr_5fteie_5fpos_826',['DMA_SxCR_TEIE_Pos',['../group___peripheral___registers___bits___definition.html#ga3416da006a6a698c8f95f91e0b9b4b5f',1,'stm32f407xx_matlab.h']]], - ['dma_5fsxfcr_5fdmdis_827',['DMA_SxFCR_DMDIS',['../group___peripheral___registers___bits___definition.html#ga89406bb954742665691c0ac2f8d95ec9',1,'stm32f407xx_matlab.h']]], - ['dma_5fsxfcr_5fdmdis_5fmsk_828',['DMA_SxFCR_DMDIS_Msk',['../group___peripheral___registers___bits___definition.html#gadedd400be2f182737e484d52be6b80c1',1,'stm32f407xx_matlab.h']]], - ['dma_5fsxfcr_5fdmdis_5fpos_829',['DMA_SxFCR_DMDIS_Pos',['../group___peripheral___registers___bits___definition.html#ga562b4b1bcd309931c42bfe7793044e91',1,'stm32f407xx_matlab.h']]], - ['dma_5fsxfcr_5ffeie_830',['DMA_SxFCR_FEIE',['../group___peripheral___registers___bits___definition.html#gaba9ca2264bc381abe0f4183729ab1fb1',1,'stm32f407xx_matlab.h']]], - ['dma_5fsxfcr_5ffeie_5fmsk_831',['DMA_SxFCR_FEIE_Msk',['../group___peripheral___registers___bits___definition.html#gadff36ebec91293d8106a40bbf580be00',1,'stm32f407xx_matlab.h']]], - ['dma_5fsxfcr_5ffeie_5fpos_832',['DMA_SxFCR_FEIE_Pos',['../group___peripheral___registers___bits___definition.html#ga10b0f3097f54eff7dd2d43bb1c31f736',1,'stm32f407xx_matlab.h']]], - ['dma_5fsxfcr_5ffs_833',['DMA_SxFCR_FS',['../group___peripheral___registers___bits___definition.html#ga56094479dc9b173b00ccfb199d8a2853',1,'stm32f407xx_matlab.h']]], - ['dma_5fsxfcr_5ffs_5f0_834',['DMA_SxFCR_FS_0',['../group___peripheral___registers___bits___definition.html#gaccf0cb1a99fb8265535b15fc6a428060',1,'stm32f407xx_matlab.h']]], - ['dma_5fsxfcr_5ffs_5f1_835',['DMA_SxFCR_FS_1',['../group___peripheral___registers___bits___definition.html#ga6b5dd8e40fe393762866522caa0ab842',1,'stm32f407xx_matlab.h']]], - ['dma_5fsxfcr_5ffs_5f2_836',['DMA_SxFCR_FS_2',['../group___peripheral___registers___bits___definition.html#ga51558a53d17a6deeed3937c15787361c',1,'stm32f407xx_matlab.h']]], - ['dma_5fsxfcr_5ffs_5fmsk_837',['DMA_SxFCR_FS_Msk',['../group___peripheral___registers___bits___definition.html#ga46ecd57c9b56be53a38263c02d25c50f',1,'stm32f407xx_matlab.h']]], - ['dma_5fsxfcr_5ffs_5fpos_838',['DMA_SxFCR_FS_Pos',['../group___peripheral___registers___bits___definition.html#ga6719968db5f4e50b30015434339db896',1,'stm32f407xx_matlab.h']]], - ['dma_5fsxfcr_5ffth_839',['DMA_SxFCR_FTH',['../group___peripheral___registers___bits___definition.html#ga44c16978164026a81f5b07280e800e7f',1,'stm32f407xx_matlab.h']]], - ['dma_5fsxfcr_5ffth_5f0_840',['DMA_SxFCR_FTH_0',['../group___peripheral___registers___bits___definition.html#ga63716e11d34bca95927671055aa63fe8',1,'stm32f407xx_matlab.h']]], - ['dma_5fsxfcr_5ffth_5f1_841',['DMA_SxFCR_FTH_1',['../group___peripheral___registers___bits___definition.html#gae3d780fc1222a183071c73e62a0524a1',1,'stm32f407xx_matlab.h']]], - ['dma_5fsxfcr_5ffth_5fmsk_842',['DMA_SxFCR_FTH_Msk',['../group___peripheral___registers___bits___definition.html#ga5e436952c24ada5a0c553043092285e7',1,'stm32f407xx_matlab.h']]], - ['dma_5fsxfcr_5ffth_5fpos_843',['DMA_SxFCR_FTH_Pos',['../group___peripheral___registers___bits___definition.html#gae6876e8621d30962774d2b72dbc720ec',1,'stm32f407xx_matlab.h']]], - ['dma_5fsxm0ar_5fm0a_844',['DMA_SxM0AR_M0A',['../group___peripheral___registers___bits___definition.html#gaad87688b73616d4ff9503421a820f1cf',1,'stm32f407xx_matlab.h']]], - ['dma_5fsxm0ar_5fm0a_5fmsk_845',['DMA_SxM0AR_M0A_Msk',['../group___peripheral___registers___bits___definition.html#ga9675f5a5f6306fe441e0ee395b055d36',1,'stm32f407xx_matlab.h']]], - ['dma_5fsxm0ar_5fm0a_5fpos_846',['DMA_SxM0AR_M0A_Pos',['../group___peripheral___registers___bits___definition.html#gade05cbad452eb0b6e0a2627ff70c0145',1,'stm32f407xx_matlab.h']]], - ['dma_5fsxm1ar_5fm1a_847',['DMA_SxM1AR_M1A',['../group___peripheral___registers___bits___definition.html#gae057bfb6e5d7b553b668a050fcdb152d',1,'stm32f407xx_matlab.h']]], - ['dma_5fsxm1ar_5fm1a_5fmsk_848',['DMA_SxM1AR_M1A_Msk',['../group___peripheral___registers___bits___definition.html#ga73d1e5bcfadadcb890897b907225cd73',1,'stm32f407xx_matlab.h']]], - ['dma_5fsxm1ar_5fm1a_5fpos_849',['DMA_SxM1AR_M1A_Pos',['../group___peripheral___registers___bits___definition.html#gaa61888c070a3873c9fb8ee1486772e3a',1,'stm32f407xx_matlab.h']]], - ['dma_5fsxndt_850',['DMA_SxNDT',['../group___peripheral___registers___bits___definition.html#ga62e0e1a1121885de705e618855ba83b0',1,'stm32f407xx_matlab.h']]], - ['dma_5fsxndt_5f0_851',['DMA_SxNDT_0',['../group___peripheral___registers___bits___definition.html#ga9ae52f0e22e621d60861143ca6027852',1,'stm32f407xx_matlab.h']]], - ['dma_5fsxndt_5f1_852',['DMA_SxNDT_1',['../group___peripheral___registers___bits___definition.html#ga4c4223f0a871ccfee403988befa42d94',1,'stm32f407xx_matlab.h']]], - ['dma_5fsxndt_5f10_853',['DMA_SxNDT_10',['../group___peripheral___registers___bits___definition.html#ga64a0c2548db60b344bbbda72b53089ca',1,'stm32f407xx_matlab.h']]], - ['dma_5fsxndt_5f11_854',['DMA_SxNDT_11',['../group___peripheral___registers___bits___definition.html#ga6e37fe0da3a0c2e6ac94f999c8455187',1,'stm32f407xx_matlab.h']]], - ['dma_5fsxndt_5f12_855',['DMA_SxNDT_12',['../group___peripheral___registers___bits___definition.html#gaa27c8ece8e904ef16ea45be9f7733103',1,'stm32f407xx_matlab.h']]], - ['dma_5fsxndt_5f13_856',['DMA_SxNDT_13',['../group___peripheral___registers___bits___definition.html#ga8f320a375482fe097d3f1579925013bb',1,'stm32f407xx_matlab.h']]], - ['dma_5fsxndt_5f14_857',['DMA_SxNDT_14',['../group___peripheral___registers___bits___definition.html#ga8882d292259d683b075bf6c4e009b3ae',1,'stm32f407xx_matlab.h']]], - ['dma_5fsxndt_5f15_858',['DMA_SxNDT_15',['../group___peripheral___registers___bits___definition.html#ga386a1a2048a470bed80654cd548dea65',1,'stm32f407xx_matlab.h']]], - ['dma_5fsxndt_5f2_859',['DMA_SxNDT_2',['../group___peripheral___registers___bits___definition.html#ga4766cc41262f7b530351ecc5939fc222',1,'stm32f407xx_matlab.h']]], - ['dma_5fsxndt_5f3_860',['DMA_SxNDT_3',['../group___peripheral___registers___bits___definition.html#gaaa43d96546fce4a436e4478a99ac0394',1,'stm32f407xx_matlab.h']]], - ['dma_5fsxndt_5f4_861',['DMA_SxNDT_4',['../group___peripheral___registers___bits___definition.html#ga81412c27b9d192be6c8c251b3a750e3c',1,'stm32f407xx_matlab.h']]], - ['dma_5fsxndt_5f5_862',['DMA_SxNDT_5',['../group___peripheral___registers___bits___definition.html#gaeff6beaa117fca4b6d1bbd87de34f674',1,'stm32f407xx_matlab.h']]], - ['dma_5fsxndt_5f6_863',['DMA_SxNDT_6',['../group___peripheral___registers___bits___definition.html#ga7533a77655a960f82d08edfd2f4bf7ee',1,'stm32f407xx_matlab.h']]], - ['dma_5fsxndt_5f7_864',['DMA_SxNDT_7',['../group___peripheral___registers___bits___definition.html#ga4b2791b19fcf8586ffd28204bab2f2b4',1,'stm32f407xx_matlab.h']]], - ['dma_5fsxndt_5f8_865',['DMA_SxNDT_8',['../group___peripheral___registers___bits___definition.html#gaa6d77fc0aa9e027fc906f70f8e6a4aca',1,'stm32f407xx_matlab.h']]], - ['dma_5fsxndt_5f9_866',['DMA_SxNDT_9',['../group___peripheral___registers___bits___definition.html#ga4b4f096ed9b7f778e5b6beec36ca9698',1,'stm32f407xx_matlab.h']]], - ['dma_5fsxndt_5fmsk_867',['DMA_SxNDT_Msk',['../group___peripheral___registers___bits___definition.html#gad9525ced3fadc78d4d5bb8234d226a52',1,'stm32f407xx_matlab.h']]], - ['dma_5fsxndt_5fpos_868',['DMA_SxNDT_Pos',['../group___peripheral___registers___bits___definition.html#gaba02a9fd02f498e258e93837b511cdd1',1,'stm32f407xx_matlab.h']]], - ['dma_5fsxpar_5fpa_869',['DMA_SxPAR_PA',['../group___peripheral___registers___bits___definition.html#ga05ea0d30f566ad469a7794e088b93ecf',1,'stm32f407xx_matlab.h']]], - ['dma_5fsxpar_5fpa_5fmsk_870',['DMA_SxPAR_PA_Msk',['../group___peripheral___registers___bits___definition.html#ga19727ba46d26c121b0133381ceb4b521',1,'stm32f407xx_matlab.h']]], - ['dma_5fsxpar_5fpa_5fpos_871',['DMA_SxPAR_PA_Pos',['../group___peripheral___registers___bits___definition.html#ga323024ac58e46cdcb78e207f1749775c',1,'stm32f407xx_matlab.h']]], - ['dma_5ftypedef_872',['DMA_TypeDef',['../struct_d_m_a___type_def.html',1,'']]], - ['dmabmr_873',['DMABMR',['../group___c_m_s_i_s___device.html#gad1e11eb1200e64e0563e3576bf258194',1,'ETH_TypeDef']]], - ['dmachrbar_874',['DMACHRBAR',['../group___c_m_s_i_s___device.html#gacf3f7ecbf774d8d505655ac7f24761fc',1,'ETH_TypeDef']]], - ['dmachrdr_875',['DMACHRDR',['../group___c_m_s_i_s___device.html#ga9c49de2e699886d6604fd2b3d376a0e9',1,'ETH_TypeDef']]], - ['dmachtbar_876',['DMACHTBAR',['../group___c_m_s_i_s___device.html#ga900f9f888342fbdd8ee07e3ee1d4b73c',1,'ETH_TypeDef']]], - ['dmachtdr_877',['DMACHTDR',['../group___c_m_s_i_s___device.html#gab5bb348210fdd9a5538eb57abc5a5673',1,'ETH_TypeDef']]], - ['dmaier_878',['DMAIER',['../group___c_m_s_i_s___device.html#gadd56f3652fd065c6797411e80477a064',1,'ETH_TypeDef']]], - ['dmamfbocr_879',['DMAMFBOCR',['../group___c_m_s_i_s___device.html#ga12eba1fc5d54aa50fdda201f7f9a84a3',1,'ETH_TypeDef']]], - ['dmaomr_880',['DMAOMR',['../group___c_m_s_i_s___device.html#gaa15b972f30ee47f5df0d3ebc8866509d',1,'ETH_TypeDef']]], - ['dmar_881',['DMAR',['../group___c_m_s_i_s___device.html#gab9087f2f31dd5edf59de6a59ae4e67ae',1,'TIM_TypeDef']]], - ['dmardlar_882',['DMARDLAR',['../group___c_m_s_i_s___device.html#ga581ce491c035ce46db723260377c2032',1,'ETH_TypeDef']]], - ['dmarpdr_883',['DMARPDR',['../group___c_m_s_i_s___device.html#gaad6309afe126da26921191697d7e5c43',1,'ETH_TypeDef']]], - ['dmarswtr_884',['DMARSWTR',['../group___c_m_s_i_s___device.html#gac6fe9e194ed9d08bf6bd28ceb80ac4b0',1,'ETH_TypeDef']]], - ['dmasr_885',['DMASR',['../group___c_m_s_i_s___device.html#ga9e7c3d04e4dcf975939eeaac246b25d0',1,'ETH_TypeDef']]], - ['dmatdlar_886',['DMATDLAR',['../group___c_m_s_i_s___device.html#ga7dba9527df73350f35683140d73a5f8d',1,'ETH_TypeDef']]], - ['dmatpdr_887',['DMATPDR',['../group___c_m_s_i_s___device.html#gacf0114902a52b7ffcc343e06484b3623',1,'ETH_TypeDef']]], - ['doepctl_888',['DOEPCTL',['../group___c_m_s_i_s___device.html#ga905a2b4ece4882eb67c710e0db10e960',1,'USB_OTG_OUTEndpointTypeDef']]], - ['doepdma_889',['DOEPDMA',['../group___c_m_s_i_s___device.html#ga78a4f036f29e552acad6a442fbb69420',1,'USB_OTG_OUTEndpointTypeDef']]], - ['doepint_890',['DOEPINT',['../group___c_m_s_i_s___device.html#gaffd2c6f534c8f2c252f3a93d0cd04ea2',1,'USB_OTG_OUTEndpointTypeDef']]], - ['doepmsk_891',['DOEPMSK',['../group___c_m_s_i_s___device.html#ga11dbd3f7a82b3f3b91621321d3018e0a',1,'USB_OTG_DeviceTypeDef']]], - ['doeptsiz_892',['DOEPTSIZ',['../group___c_m_s_i_s___device.html#ga35b668314acbac2580b98caf8b9c5c10',1,'USB_OTG_OUTEndpointTypeDef']]], - ['dor1_893',['DOR1',['../group___c_m_s_i_s___device.html#gaa710505be03a41981c35bacc7ce20746',1,'DAC_TypeDef']]], - ['dor2_894',['DOR2',['../group___c_m_s_i_s___device.html#gaba9fb810b0cf6cbc1280c5c63be2418b',1,'DAC_TypeDef']]], - ['doutep1msk_895',['DOUTEP1MSK',['../group___c_m_s_i_s___device.html#ga196e86fc15ba228188d47468349de69b',1,'USB_OTG_DeviceTypeDef']]], - ['dr_896',['DR',['../group___c_m_s_i_s___device.html#ga3df0d8dfcd1ec958659ffe21eb64fa94',1,'ADC_TypeDef::DR'],['../group___c_m_s_i_s___device.html#ga3df0d8dfcd1ec958659ffe21eb64fa94',1,'CRC_TypeDef::DR'],['../group___c_m_s_i_s___device.html#ga3df0d8dfcd1ec958659ffe21eb64fa94',1,'DCMI_TypeDef::DR'],['../group___c_m_s_i_s___device.html#ga3df0d8dfcd1ec958659ffe21eb64fa94',1,'I2C_TypeDef::DR'],['../group___c_m_s_i_s___device.html#ga3df0d8dfcd1ec958659ffe21eb64fa94',1,'RTC_TypeDef::DR'],['../group___c_m_s_i_s___device.html#ga3df0d8dfcd1ec958659ffe21eb64fa94',1,'SPI_TypeDef::DR'],['../group___c_m_s_i_s___device.html#ga3df0d8dfcd1ec958659ffe21eb64fa94',1,'USART_TypeDef::DR'],['../group___c_m_s_i_s___device.html#ga3df0d8dfcd1ec958659ffe21eb64fa94',1,'RNG_TypeDef::DR']]], - ['dsts_897',['DSTS',['../group___c_m_s_i_s___device.html#ga8371acd36203fa875cdea3f29b94d1fb',1,'USB_OTG_DeviceTypeDef']]], - ['dthrctl_898',['DTHRCTL',['../group___c_m_s_i_s___device.html#gac5d3a4bffd921da5d69f9a601263b573',1,'USB_OTG_DeviceTypeDef']]], - ['dtimer_899',['DTIMER',['../group___c_m_s_i_s___device.html#ga1dd219eaeee8d9def822da843028bd02',1,'SDIO_TypeDef']]], - ['dtxfsts_900',['DTXFSTS',['../group___c_m_s_i_s___device.html#ga44135a03aa87fb60abd479a09f71343d',1,'USB_OTG_INEndpointTypeDef']]], - ['dvbusdis_901',['DVBUSDIS',['../group___c_m_s_i_s___device.html#gaef96b3719a70e62cb004b1e292b7a348',1,'USB_OTG_DeviceTypeDef']]], - ['dvbuspulse_902',['DVBUSPULSE',['../group___c_m_s_i_s___device.html#gacc968fd160f83749ad4176ad8cb36fe0',1,'USB_OTG_DeviceTypeDef']]], - ['dwt_903',['DWT',['../group___c_m_s_i_s___d_w_t.html',1,'Data Watchpoint and Trace (DWT)'],['../group___c_m_s_i_s__core__base.html#gabbe5a060185e1d5afa3f85b14e10a6ce',1,'DWT: core_cm4_matlab.h']]], - ['dwt_5fbase_904',['DWT_BASE',['../group___c_m_s_i_s__core__base.html#gafdab534f961bf8935eb456cb7700dcd2',1,'core_cm4_matlab.h']]], - ['dwt_5fbase_5fshift_905',['DWT_BASE_SHIFT',['../group___c_m_s_i_s__core__base.html#gaecf34cb76daeb0ed1854efbc8c1bacf7',1,'core_cm4_matlab.h']]], - ['dwt_5fcpicnt_5fcpicnt_5fmsk_906',['DWT_CPICNT_CPICNT_Msk',['../group___c_m_s_i_s___d_w_t.html#ga76f39e7bca3fa86a4dbf7b8f6adb7217',1,'core_cm4_matlab.h']]], - ['dwt_5fcpicnt_5fcpicnt_5fpos_907',['DWT_CPICNT_CPICNT_Pos',['../group___c_m_s_i_s___d_w_t.html#ga80e9ad8f6a9e2344af8a3cf989bebe3d',1,'core_cm4_matlab.h']]], - ['dwt_5fctrl_5fcpievtena_5fmsk_908',['DWT_CTRL_CPIEVTENA_Msk',['../group___c_m_s_i_s___d_w_t.html#ga189089c30aade60b983df17ad2412f6f',1,'core_cm4_matlab.h']]], - ['dwt_5fctrl_5fcpievtena_5fpos_909',['DWT_CTRL_CPIEVTENA_Pos',['../group___c_m_s_i_s___d_w_t.html#ga9fff0b71fb0be1499f5180c6bce1fc8f',1,'core_cm4_matlab.h']]], - ['dwt_5fctrl_5fcyccntena_5fmsk_910',['DWT_CTRL_CYCCNTENA_Msk',['../group___c_m_s_i_s___d_w_t.html#ga4a9d209dc2a81ea6bfa0ea21331769d3',1,'core_cm4_matlab.h']]], - ['dwt_5fctrl_5fcyccntena_5fpos_911',['DWT_CTRL_CYCCNTENA_Pos',['../group___c_m_s_i_s___d_w_t.html#gaa4509f5f8514a7200be61691f0e01f10',1,'core_cm4_matlab.h']]], - ['dwt_5fctrl_5fcycevtena_5fmsk_912',['DWT_CTRL_CYCEVTENA_Msk',['../group___c_m_s_i_s___d_w_t.html#ga40554bd81460e39abf08810f45fac1a2',1,'core_cm4_matlab.h']]], - ['dwt_5fctrl_5fcycevtena_5fpos_913',['DWT_CTRL_CYCEVTENA_Pos',['../group___c_m_s_i_s___d_w_t.html#ga0cb0640aaeb18a626d7823570d5c3cb6',1,'core_cm4_matlab.h']]], - ['dwt_5fctrl_5fcyctap_5fmsk_914',['DWT_CTRL_CYCTAP_Msk',['../group___c_m_s_i_s___d_w_t.html#ga6c12e2868b8989a69445646698b8c331',1,'core_cm4_matlab.h']]], - ['dwt_5fctrl_5fcyctap_5fpos_915',['DWT_CTRL_CYCTAP_Pos',['../group___c_m_s_i_s___d_w_t.html#gaf70b80936c7db60bf84fb6dadb8a3559',1,'core_cm4_matlab.h']]], - ['dwt_5fctrl_5fexcevtena_5fmsk_916',['DWT_CTRL_EXCEVTENA_Msk',['../group___c_m_s_i_s___d_w_t.html#gab7ee0def33423b5859ca4030dff63b58',1,'core_cm4_matlab.h']]], - ['dwt_5fctrl_5fexcevtena_5fpos_917',['DWT_CTRL_EXCEVTENA_Pos',['../group___c_m_s_i_s___d_w_t.html#gaf4e73f548ae3e945ef8b1d9ff1281544',1,'core_cm4_matlab.h']]], - ['dwt_5fctrl_5fexctrcena_5fmsk_918',['DWT_CTRL_EXCTRCENA_Msk',['../group___c_m_s_i_s___d_w_t.html#gaf4fbb509ab3cbb768f16484c660a24c3',1,'core_cm4_matlab.h']]], - ['dwt_5fctrl_5fexctrcena_5fpos_919',['DWT_CTRL_EXCTRCENA_Pos',['../group___c_m_s_i_s___d_w_t.html#ga05f13b547a9a1e63e003ee0bc6446d0d',1,'core_cm4_matlab.h']]], - ['dwt_5fctrl_5ffoldevtena_5fmsk_920',['DWT_CTRL_FOLDEVTENA_Msk',['../group___c_m_s_i_s___d_w_t.html#ga717e679d775562ae09185a3776b1582f',1,'core_cm4_matlab.h']]], - ['dwt_5fctrl_5ffoldevtena_5fpos_921',['DWT_CTRL_FOLDEVTENA_Pos',['../group___c_m_s_i_s___d_w_t.html#ga5602b0707f446ce78d88ff2a3a82bfff',1,'core_cm4_matlab.h']]], - ['dwt_5fctrl_5flsuevtena_5fmsk_922',['DWT_CTRL_LSUEVTENA_Msk',['../group___c_m_s_i_s___d_w_t.html#gac47427f455fbc29d4b6f8a479169f2b2',1,'core_cm4_matlab.h']]], - ['dwt_5fctrl_5flsuevtena_5fpos_923',['DWT_CTRL_LSUEVTENA_Pos',['../group___c_m_s_i_s___d_w_t.html#gaea5d1ee72188dc1d57b54c60a9f5233e',1,'core_cm4_matlab.h']]], - ['dwt_5fctrl_5fnocyccnt_5fmsk_924',['DWT_CTRL_NOCYCCNT_Msk',['../group___c_m_s_i_s___d_w_t.html#gaf40c8d7a4fd978034c137e90f714c143',1,'core_cm4_matlab.h']]], - ['dwt_5fctrl_5fnocyccnt_5fpos_925',['DWT_CTRL_NOCYCCNT_Pos',['../group___c_m_s_i_s___d_w_t.html#ga337f6167d960f57f12aa382ffecce522',1,'core_cm4_matlab.h']]], - ['dwt_5fctrl_5fnoexttrig_5fmsk_926',['DWT_CTRL_NOEXTTRIG_Msk',['../group___c_m_s_i_s___d_w_t.html#gacc7d15edf7a27147c422099ab475953e',1,'core_cm4_matlab.h']]], - ['dwt_5fctrl_5fnoexttrig_5fpos_927',['DWT_CTRL_NOEXTTRIG_Pos',['../group___c_m_s_i_s___d_w_t.html#gad997b9026715d5609b5a3b144eca42d0',1,'core_cm4_matlab.h']]], - ['dwt_5fctrl_5fnoprfcnt_5fmsk_928',['DWT_CTRL_NOPRFCNT_Msk',['../group___c_m_s_i_s___d_w_t.html#gafd8448d7db4bc51f27f202e6e1f27823',1,'core_cm4_matlab.h']]], - ['dwt_5fctrl_5fnoprfcnt_5fpos_929',['DWT_CTRL_NOPRFCNT_Pos',['../group___c_m_s_i_s___d_w_t.html#gad52a0e5be84363ab166cc17beca0d048',1,'core_cm4_matlab.h']]], - ['dwt_5fctrl_5fnotrcpkt_5fmsk_930',['DWT_CTRL_NOTRCPKT_Msk',['../group___c_m_s_i_s___d_w_t.html#ga04d8bb0a065ca38e2e5f13a97e1f7073',1,'core_cm4_matlab.h']]], - ['dwt_5fctrl_5fnotrcpkt_5fpos_931',['DWT_CTRL_NOTRCPKT_Pos',['../group___c_m_s_i_s___d_w_t.html#gaa82840323a2628e7f4a2b09b74fa73fd',1,'core_cm4_matlab.h']]], - ['dwt_5fctrl_5fnumcomp_5fmsk_932',['DWT_CTRL_NUMCOMP_Msk',['../group___c_m_s_i_s___d_w_t.html#gaa3d37d68c2ba73f2026265584c2815e7',1,'core_cm4_matlab.h']]], - ['dwt_5fctrl_5fnumcomp_5fpos_933',['DWT_CTRL_NUMCOMP_Pos',['../group___c_m_s_i_s___d_w_t.html#gaac44b9b7d5391a7ffef129b7f6c84cd7',1,'core_cm4_matlab.h']]], - ['dwt_5fctrl_5fpcsamplena_5fmsk_934',['DWT_CTRL_PCSAMPLENA_Msk',['../group___c_m_s_i_s___d_w_t.html#gafdcf1c86f43fbeaf2780ce797c9ef3d6',1,'core_cm4_matlab.h']]], - ['dwt_5fctrl_5fpcsamplena_5fpos_935',['DWT_CTRL_PCSAMPLENA_Pos',['../group___c_m_s_i_s___d_w_t.html#ga1e14afc7790fcb424fcf619e192554c9',1,'core_cm4_matlab.h']]], - ['dwt_5fctrl_5fpostinit_5fmsk_936',['DWT_CTRL_POSTINIT_Msk',['../group___c_m_s_i_s___d_w_t.html#gab8cbbee1e1d94d09f9a1f86379a08ee8',1,'core_cm4_matlab.h']]], - ['dwt_5fctrl_5fpostinit_5fpos_937',['DWT_CTRL_POSTINIT_Pos',['../group___c_m_s_i_s___d_w_t.html#ga2868c0b28eb13be930afb819f55f6f25',1,'core_cm4_matlab.h']]], - ['dwt_5fctrl_5fpostpreset_5fmsk_938',['DWT_CTRL_POSTPRESET_Msk',['../group___c_m_s_i_s___d_w_t.html#ga11d9e1e2a758fdd2657aa68ce61b9c9d',1,'core_cm4_matlab.h']]], - ['dwt_5fctrl_5fpostpreset_5fpos_939',['DWT_CTRL_POSTPRESET_Pos',['../group___c_m_s_i_s___d_w_t.html#ga129bc152febfddd67a0c20c6814cba69',1,'core_cm4_matlab.h']]], - ['dwt_5fctrl_5fsleepevtena_5fmsk_940',['DWT_CTRL_SLEEPEVTENA_Msk',['../group___c_m_s_i_s___d_w_t.html#ga2f431b3734fb840daf5b361034856da9',1,'core_cm4_matlab.h']]], - ['dwt_5fctrl_5fsleepevtena_5fpos_941',['DWT_CTRL_SLEEPEVTENA_Pos',['../group___c_m_s_i_s___d_w_t.html#ga9c6d62d121164013a8e3ee372f17f3e5',1,'core_cm4_matlab.h']]], - ['dwt_5fctrl_5fsynctap_5fmsk_942',['DWT_CTRL_SYNCTAP_Msk',['../group___c_m_s_i_s___d_w_t.html#gaf1e6c3729d56ecadeb6eeff4d225968c',1,'core_cm4_matlab.h']]], - ['dwt_5fctrl_5fsynctap_5fpos_943',['DWT_CTRL_SYNCTAP_Pos',['../group___c_m_s_i_s___d_w_t.html#ga678ef08786edcbef964479217efb9284',1,'core_cm4_matlab.h']]], - ['dwt_5fexccnt_5fexccnt_5fmsk_944',['DWT_EXCCNT_EXCCNT_Msk',['../group___c_m_s_i_s___d_w_t.html#ga057fa604a107b58a198bbbadb47e69c9',1,'core_cm4_matlab.h']]], - ['dwt_5fexccnt_5fexccnt_5fpos_945',['DWT_EXCCNT_EXCCNT_Pos',['../group___c_m_s_i_s___d_w_t.html#ga031c693654030d4cba398b45d2925b1d',1,'core_cm4_matlab.h']]], - ['dwt_5ffoldcnt_5ffoldcnt_5fmsk_946',['DWT_FOLDCNT_FOLDCNT_Msk',['../group___c_m_s_i_s___d_w_t.html#ga9cb73d0342d38b14e41027d3c5c02647',1,'core_cm4_matlab.h']]], - ['dwt_5ffoldcnt_5ffoldcnt_5fpos_947',['DWT_FOLDCNT_FOLDCNT_Pos',['../group___c_m_s_i_s___d_w_t.html#ga7f8af5ac12d178ba31a516f6ed141455',1,'core_cm4_matlab.h']]], - ['dwt_5ffunction_5fcycmatch_5fmsk_948',['DWT_FUNCTION_CYCMATCH_Msk',['../group___c_m_s_i_s___d_w_t.html#ga8e2ed09bdd33a8f7f7ce0444f5f3bb25',1,'core_cm4_matlab.h']]], - ['dwt_5ffunction_5fcycmatch_5fpos_949',['DWT_FUNCTION_CYCMATCH_Pos',['../group___c_m_s_i_s___d_w_t.html#ga4b65d79ca37ae8010b4a726312413efd',1,'core_cm4_matlab.h']]], - ['dwt_5ffunction_5fdatavaddr0_5fmsk_950',['DWT_FUNCTION_DATAVADDR0_Msk',['../group___c_m_s_i_s___d_w_t.html#gafc5efbe8f9b51e04aecd00c8a4eb50fb',1,'core_cm4_matlab.h']]], - ['dwt_5ffunction_5fdatavaddr0_5fpos_951',['DWT_FUNCTION_DATAVADDR0_Pos',['../group___c_m_s_i_s___d_w_t.html#ga9854cd8bf16f7dce0fb196a8029b018e',1,'core_cm4_matlab.h']]], - ['dwt_5ffunction_5fdatavaddr1_5fmsk_952',['DWT_FUNCTION_DATAVADDR1_Msk',['../group___c_m_s_i_s___d_w_t.html#gafdbf5a8c367befe8661a4f6945c83445',1,'core_cm4_matlab.h']]], - ['dwt_5ffunction_5fdatavaddr1_5fpos_953',['DWT_FUNCTION_DATAVADDR1_Pos',['../group___c_m_s_i_s___d_w_t.html#ga8b75e8ab3ffd5ea2fa762d028dc30e8c',1,'core_cm4_matlab.h']]], - ['dwt_5ffunction_5fdatavmatch_5fmsk_954',['DWT_FUNCTION_DATAVMATCH_Msk',['../group___c_m_s_i_s___d_w_t.html#ga32af1f1c0fcd2d8d9afd1ad79cd9970e',1,'core_cm4_matlab.h']]], - ['dwt_5ffunction_5fdatavmatch_5fpos_955',['DWT_FUNCTION_DATAVMATCH_Pos',['../group___c_m_s_i_s___d_w_t.html#ga106f3672cd4be7c7c846e20497ebe5a6',1,'core_cm4_matlab.h']]], - ['dwt_5ffunction_5fdatavsize_5fmsk_956',['DWT_FUNCTION_DATAVSIZE_Msk',['../group___c_m_s_i_s___d_w_t.html#gaab42cbc1e6084c44d5de70971613ea76',1,'core_cm4_matlab.h']]], - ['dwt_5ffunction_5fdatavsize_5fpos_957',['DWT_FUNCTION_DATAVSIZE_Pos',['../group___c_m_s_i_s___d_w_t.html#ga0517a186d4d448aa6416440f40fe7a4d',1,'core_cm4_matlab.h']]], - ['dwt_5ffunction_5femitrange_5fmsk_958',['DWT_FUNCTION_EMITRANGE_Msk',['../group___c_m_s_i_s___d_w_t.html#gad46dd5aba29f2e28d4d3f50b1d291f41',1,'core_cm4_matlab.h']]], - ['dwt_5ffunction_5femitrange_5fpos_959',['DWT_FUNCTION_EMITRANGE_Pos',['../group___c_m_s_i_s___d_w_t.html#ga41d5b332216baa8d29561260a1b85659',1,'core_cm4_matlab.h']]], - ['dwt_5ffunction_5ffunction_5fmsk_960',['DWT_FUNCTION_FUNCTION_Msk',['../group___c_m_s_i_s___d_w_t.html#ga3b2cda708755ecf5f921d08b25d774d1',1,'core_cm4_matlab.h']]], - ['dwt_5ffunction_5ffunction_5fpos_961',['DWT_FUNCTION_FUNCTION_Pos',['../group___c_m_s_i_s___d_w_t.html#ga5797b556edde2bbaa4d33dcdb1a891bb',1,'core_cm4_matlab.h']]], - ['dwt_5ffunction_5flnk1ena_5fmsk_962',['DWT_FUNCTION_LNK1ENA_Msk',['../group___c_m_s_i_s___d_w_t.html#ga64bd419260c3337cacf93607d1ad27ac',1,'core_cm4_matlab.h']]], - ['dwt_5ffunction_5flnk1ena_5fpos_963',['DWT_FUNCTION_LNK1ENA_Pos',['../group___c_m_s_i_s___d_w_t.html#ga89d7c48858b4d4de96cdadfac91856a1',1,'core_cm4_matlab.h']]], - ['dwt_5ffunction_5fmatched_5fmsk_964',['DWT_FUNCTION_MATCHED_Msk',['../group___c_m_s_i_s___d_w_t.html#gac8b1a655947490280709037808eec8ac',1,'core_cm4_matlab.h']]], - ['dwt_5ffunction_5fmatched_5fpos_965',['DWT_FUNCTION_MATCHED_Pos',['../group___c_m_s_i_s___d_w_t.html#ga22c5787493f74a6bacf6ffb103a190ba',1,'core_cm4_matlab.h']]], - ['dwt_5flsucnt_5flsucnt_5fmsk_966',['DWT_LSUCNT_LSUCNT_Msk',['../group___c_m_s_i_s___d_w_t.html#ga2186d7fc9317e20bad61336ee2925615',1,'core_cm4_matlab.h']]], - ['dwt_5flsucnt_5flsucnt_5fpos_967',['DWT_LSUCNT_LSUCNT_Pos',['../group___c_m_s_i_s___d_w_t.html#gab9394c7911b0b4312a096dad91d53a3d',1,'core_cm4_matlab.h']]], - ['dwt_5fmask_5fmask_5fmsk_968',['DWT_MASK_MASK_Msk',['../group___c_m_s_i_s___d_w_t.html#gadd798deb0f1312feab4fb05dcddc229b',1,'core_cm4_matlab.h']]], - ['dwt_5fmask_5fmask_5fpos_969',['DWT_MASK_MASK_Pos',['../group___c_m_s_i_s___d_w_t.html#gaf798ae34e2b9280ea64f4d9920cd2e7d',1,'core_cm4_matlab.h']]], - ['dwt_5fsleepcnt_5fsleepcnt_5fmsk_970',['DWT_SLEEPCNT_SLEEPCNT_Msk',['../group___c_m_s_i_s___d_w_t.html#ga1e340751d71413fef400a0a1d76cc828',1,'core_cm4_matlab.h']]], - ['dwt_5fsleepcnt_5fsleepcnt_5fpos_971',['DWT_SLEEPCNT_SLEEPCNT_Pos',['../group___c_m_s_i_s___d_w_t.html#ga0371a84a7996dc5852c56afb2676ba1c',1,'core_cm4_matlab.h']]], - ['dwt_5ftype_972',['DWT_Type',['../struct_d_w_t___type.html',1,'']]] + ['dac1_1',['dac1',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#gac2a5eec34721432ce7d7dec940c4a105',1,'stm32f4xx_periph_registers.c']]], + ['dbgmcu_2',['dbgmcu',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#gacecf2f30be3d1243af9c27921727cb3d',1,'stm32f4xx_periph_registers.c']]], + ['dbgmcu_5fbase_3',['DBGMCU_BASE',['../group___peripheral__memory__map.html#ga4adaf4fd82ccc3a538f1f27a70cdbbef',1,'stm32f407xx_matlab_memory.h']]], + ['dcmi_4',['dcmi',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga7acb73c38792037a032e8a1a05247546',1,'stm32f4xx_periph_registers.c']]], + ['debug_5fmcu_5',['DEBUG_MCU',['../stm32f4xx__matlab__conf_8c.html#a85a080726cb1ade56443b458fc49404b',1,'stm32f4xx_matlab_conf.c']]], + ['debug_5fmcu_5fbase_6',['DEBUG_MCU_BASE',['../struct__memory.html#a3b7f188430e83671b314657c1033f0e4',1,'_memory']]], + ['debug_5fmcu_5fsize_7',['DEBUG_MCU_SIZE',['../group___peripheral__memory__map.html#ga378fbcdeb200dba6b14c9ac7b02471f3',1,'stm32f407xx_matlab_memory.h']]], + ['debugging_8',['Periphs Variables for Debugging',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html',1,'']]], + ['definitions_9',['Core Definitions',['../group___c_m_s_i_s__core__base.html',1,'']]], + ['deinitialize_5fmcu_10',['deInitialize_MCU',['../stm32f4xx__matlab__conf_8c.html#ad7d9ddf99be97748bc7417425271d85e',1,'deInitialize_MCU(void): stm32f4xx_matlab_conf.c'],['../stm32f4xx__matlab__conf_8h.html#ad7d9ddf99be97748bc7417425271d85e',1,'deInitialize_MCU(void): stm32f4xx_matlab_conf.c']]], + ['deinitialize_5fperiph_5fsim_11',['deInitialize_Periph_Sim',['../stm32f4xx__matlab__conf_8c.html#aff389f4df35953d82d9d30ae161a8cf9',1,'deInitialize_Periph_Sim(void): stm32f4xx_matlab_conf.c'],['../stm32f4xx__matlab__conf_8h.html#aff389f4df35953d82d9d30ae161a8cf9',1,'deInitialize_Periph_Sim(void): stm32f4xx_matlab_conf.c']]], + ['dekstop_5fcycles_5ffor_5fmcu_5fapp_12',['DEKSTOP_CYCLES_FOR_MCU_APP',['../group___w_r_a_p_p_e_r___c_o_n_f.html#gafc876c6cc8fa4255636740b201ac1d66',1,'mcu_wrapper_conf.h']]], + ['delete_13',['delete',['../mexing_8m.html#a079ba1759372ad0dafb30bfb334998cc',1,'mexing.m']]], + ['disc_5fstates_5fwidth_14',['DISC_STATES_WIDTH',['../group___w_r_a_p_p_e_r___c_o_n_f.html#gaaed909ba8fd0e4f7a3c2533836dae5d9',1,'mcu_wrapper_conf.h']]], + ['dma1_15',['dma1',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#gad75f4f486cddcbba8bd891fdffea63ff',1,'stm32f4xx_periph_registers.c']]], + ['dma1_5fstream0_16',['dma1_stream0',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga327e8fb8c3fdda29762971a665beb6eb',1,'stm32f4xx_periph_registers.c']]], + ['dma1_5fstream1_17',['dma1_stream1',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga9696aa3317c6d4e58bd31545db1a3791',1,'stm32f4xx_periph_registers.c']]], + ['dma1_5fstream2_18',['dma1_stream2',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#gaf1e2d204d4c7f13213bc4cdece346a9f',1,'stm32f4xx_periph_registers.c']]], + ['dma1_5fstream3_19',['dma1_stream3',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga67575d2b3cf487db91535889ed5802c4',1,'stm32f4xx_periph_registers.c']]], + ['dma1_5fstream4_20',['dma1_stream4',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga0da31a3af45097d4b4a136c5d74d6000',1,'stm32f4xx_periph_registers.c']]], + ['dma1_5fstream5_21',['dma1_stream5',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga160109a05c1a572c5911c1a0633e2cb1',1,'stm32f4xx_periph_registers.c']]], + ['dma1_5fstream6_22',['dma1_stream6',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga52167e4b4ae32ee99aca493b07ec2cf0',1,'stm32f4xx_periph_registers.c']]], + ['dma1_5fstream7_23',['dma1_stream7',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#gaeb5a72f1dde2596da84347544d59f3ea',1,'stm32f4xx_periph_registers.c']]], + ['dma2_24',['dma2',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga797194bf8715329824161a98d1b2a236',1,'stm32f4xx_periph_registers.c']]], + ['dma2_5fstream0_25',['dma2_stream0',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#gaeff8718ce310afab98873eccba9ff245',1,'stm32f4xx_periph_registers.c']]], + ['dma2_5fstream1_26',['dma2_stream1',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga0fb8b4583868b79144561ef45c93637a',1,'stm32f4xx_periph_registers.c']]], + ['dma2_5fstream2_27',['dma2_stream2',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga33cbc3fc9b89c29e722fc4e4973d6058',1,'stm32f4xx_periph_registers.c']]], + ['dma2_5fstream3_28',['dma2_stream3',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#gadcd0980342e18d51ce08021a0d1abfdd',1,'stm32f4xx_periph_registers.c']]], + ['dma2_5fstream4_29',['dma2_stream4',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga14e0e20b296df9eea835441023807c15',1,'stm32f4xx_periph_registers.c']]], + ['dma2_5fstream5_30',['dma2_stream5',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga8fc00e6429450f48f22fddb4040d1e2d',1,'stm32f4xx_periph_registers.c']]], + ['dma2_5fstream6_31',['dma2_stream6',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga8d4903dcdae5a8f4c0b7b2678b2cf5b4',1,'stm32f4xx_periph_registers.c']]], + ['dma2_5fstream7_32',['dma2_stream7',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga19770af0d338f06fbb1ffa09150909b4',1,'stm32f4xx_periph_registers.c']]], + ['dwt_33',['DWT',['../group___c_m_s_i_s__core__base.html#gabbe5a060185e1d5afa3f85b14e10a6ce',1,'stm32f407xx_matlab_memory.h']]], + ['dwt_5fbase_34',['DWT_BASE',['../group___c_m_s_i_s__core__base.html#gafdab534f961bf8935eb456cb7700dcd2',1,'stm32f407xx_matlab_memory.h']]], + ['dwt_5fbase_5fshift_35',['DWT_BASE_SHIFT',['../group___c_m_s_i_s__core__base.html#gaecf34cb76daeb0ed1854efbc8c1bacf7',1,'stm32f407xx_matlab_memory.h']]] ]; diff --git a/DOCS/html/search/all_5.js b/DOCS/html/search/all_5.js index c8f95ab..6ec3de2 100644 --- a/DOCS/html/search/all_5.js +++ b/DOCS/html/search/all_5.js @@ -1,1328 +1,6 @@ var searchData= [ - ['eccr2_0',['ECCR2',['../group___c_m_s_i_s___device.html#ga05a47a1664adc7a3db3fa3e83fe883b4',1,'FSMC_Bank2_3_TypeDef']]], - ['eccr3_1',['ECCR3',['../group___c_m_s_i_s___device.html#ga6062be7dc144c07e01c303cb49d69ce2',1,'FSMC_Bank2_3_TypeDef']]], - ['egr_2',['EGR',['../group___c_m_s_i_s___device.html#ga196ebdaac12b21e90320c6175da78ef6',1,'TIM_TypeDef']]], - ['emr_3',['EMR',['../group___c_m_s_i_s___device.html#ga6034c7458d8e6030f6dacecf0f1a3a89',1,'EXTI_TypeDef']]], - ['emulator_4',['MATLAB STM32 EMULATOR',['../md__f_1_2_work_2_projects_2_m_a_t_l_a_b_2matlab__stm__emulate_2_r_e_a_d_m_e.html',1,'']]], - ['enable_5',['ENABLE',['../group___exported__types.html#ggac9a7e9a35d2513ec15c3b537aaa4fba1a7d46875fa3ebd2c34d2756950eda83bf',1,'stm32f4xx.h']]], - ['error_6',['ERROR',['../group___exported__types.html#gga8333b96c67f83cba354b3407fcbb6ee8a2fd6f336d08340583bd620a7f5694c90',1,'stm32f4xx.h']]], - ['errorstatus_7',['ErrorStatus',['../group___exported__types.html#ga8333b96c67f83cba354b3407fcbb6ee8',1,'stm32f4xx.h']]], - ['escr_8',['ESCR',['../group___c_m_s_i_s___device.html#ga9cc4ec74be864c929261e0810f2fd7f0',1,'DCMI_TypeDef']]], - ['esr_9',['ESR',['../group___c_m_s_i_s___device.html#ga2b39f943954e0e7d177b511d9074a0b7',1,'CAN_TypeDef']]], - ['esur_10',['ESUR',['../group___c_m_s_i_s___device.html#gaf751d49ef824c1636c78822ecae066f4',1,'DCMI_TypeDef']]], - ['eth_11',['eth',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga8b57579963e46439e92cb241151cec09',1,'stm32f4xx_periph_registers.c']]], - ['eth_12',['ETH',['../group___peripheral__declaration.html#ga3a3f60de4318afbd0b3318e7a416aadc',1,'stm32f407xx_matlab.h']]], - ['eth_5fbase_13',['ETH_BASE',['../group___peripheral__memory__map.html#gad965a7b1106ece575ed3da10c45c65cc',1,'stm32f407xx_matlab.h']]], - ['eth_5fdma_5fbase_14',['ETH_DMA_BASE',['../group___peripheral__memory__map.html#gace2114e1b37c1ba88d60f3e831b67e93',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmabmr_5faab_15',['ETH_DMABMR_AAB',['../group___peripheral___registers___bits___definition.html#gacec4fa12c34dc8fcacc2271f09ed0cbd',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmabmr_5faab_5fmsk_16',['ETH_DMABMR_AAB_Msk',['../group___peripheral___registers___bits___definition.html#ga5f5eca1e6932299715114700f0015d2e',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmabmr_5faab_5fpos_17',['ETH_DMABMR_AAB_Pos',['../group___peripheral___registers___bits___definition.html#ga7e542f89aee68bd91d90d7546db209de',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmabmr_5fda_18',['ETH_DMABMR_DA',['../group___peripheral___registers___bits___definition.html#gafd126734c36f2db46c51e73cef07afce',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmabmr_5fda_5fmsk_19',['ETH_DMABMR_DA_Msk',['../group___peripheral___registers___bits___definition.html#ga7bd68646897581a06cbee2dacbdd0c14',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmabmr_5fda_5fpos_20',['ETH_DMABMR_DA_Pos',['../group___peripheral___registers___bits___definition.html#gabad048a02b9fbed0c5824a6a632d0daf',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmabmr_5fdsl_21',['ETH_DMABMR_DSL',['../group___peripheral___registers___bits___definition.html#gab1931fd959cb78283ab0cf0bd9804387',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmabmr_5fdsl_5fmsk_22',['ETH_DMABMR_DSL_Msk',['../group___peripheral___registers___bits___definition.html#ga4c0974106bccb288a14a4f5b055f2a88',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmabmr_5fdsl_5fpos_23',['ETH_DMABMR_DSL_Pos',['../group___peripheral___registers___bits___definition.html#gaff399b83a19a6a62457cd0877bea35b7',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmabmr_5fede_24',['ETH_DMABMR_EDE',['../group___peripheral___registers___bits___definition.html#gaf04f1ef51af153093743c190d25ea21b',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmabmr_5fede_5fmsk_25',['ETH_DMABMR_EDE_Msk',['../group___peripheral___registers___bits___definition.html#ga18544872c7f55ac2011ff1fe2ab6d353',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmabmr_5fede_5fpos_26',['ETH_DMABMR_EDE_Pos',['../group___peripheral___registers___bits___definition.html#ga772af3cfca1669d65c2eb16413483032',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmabmr_5ffb_27',['ETH_DMABMR_FB',['../group___peripheral___registers___bits___definition.html#ga717f163fe72c7e1c999123160dde4143',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmabmr_5ffb_5fmsk_28',['ETH_DMABMR_FB_Msk',['../group___peripheral___registers___bits___definition.html#ga062f6878427a5d9cbb00432cc046ca7d',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmabmr_5ffb_5fpos_29',['ETH_DMABMR_FB_Pos',['../group___peripheral___registers___bits___definition.html#ga8c8d22bcd14946c499d9a638e7aedc25',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmabmr_5ffpm_30',['ETH_DMABMR_FPM',['../group___peripheral___registers___bits___definition.html#gafcb4414b6567f8b131712e0dc5c62beb',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmabmr_5ffpm_5fmsk_31',['ETH_DMABMR_FPM_Msk',['../group___peripheral___registers___bits___definition.html#ga2fdb196d2e2aba0246e12581b915f783',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmabmr_5ffpm_5fpos_32',['ETH_DMABMR_FPM_Pos',['../group___peripheral___registers___bits___definition.html#ga4fabf93610f531f3f2f1f4a601fe2498',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmabmr_5fmb_33',['ETH_DMABMR_MB',['../group___peripheral___registers___bits___definition.html#ga02d5b9592d4cb586352b11bc6ed179ff',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmabmr_5fmb_5fmsk_34',['ETH_DMABMR_MB_Msk',['../group___peripheral___registers___bits___definition.html#gafccc7781fcfe97b198cd1dc91959e0e9',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmabmr_5fmb_5fpos_35',['ETH_DMABMR_MB_Pos',['../group___peripheral___registers___bits___definition.html#ga6754f2bead2bd9b49eeba732d109220e',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmabmr_5fpbl_36',['ETH_DMABMR_PBL',['../group___peripheral___registers___bits___definition.html#ga0e3daa2867b6d01e8eda765e77648599',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmabmr_5fpbl_5f16beat_37',['ETH_DMABMR_PBL_16Beat',['../group___peripheral___registers___bits___definition.html#ga6351d1d02e94053527b8e18f393b1e82',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmabmr_5fpbl_5f1beat_38',['ETH_DMABMR_PBL_1Beat',['../group___peripheral___registers___bits___definition.html#gaefeb5f1c9376d0a0bc956aba567c7cb9',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmabmr_5fpbl_5f2beat_39',['ETH_DMABMR_PBL_2Beat',['../group___peripheral___registers___bits___definition.html#ga3a034f8cf671cba686e882172ad93949',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmabmr_5fpbl_5f32beat_40',['ETH_DMABMR_PBL_32Beat',['../group___peripheral___registers___bits___definition.html#ga82d8ee65c1583f4ec9092bc45563d720',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmabmr_5fpbl_5f4beat_41',['ETH_DMABMR_PBL_4Beat',['../group___peripheral___registers___bits___definition.html#ga55ff9b7cebc3489fcaab886a065d372c',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmabmr_5fpbl_5f4xpbl_5f128beat_42',['ETH_DMABMR_PBL_4xPBL_128Beat',['../group___peripheral___registers___bits___definition.html#ga4c90887a852a858c630ac388bec0b392',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmabmr_5fpbl_5f4xpbl_5f16beat_43',['ETH_DMABMR_PBL_4xPBL_16Beat',['../group___peripheral___registers___bits___definition.html#gae5c68f3a0a692fbd81bac47bfe2340bb',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmabmr_5fpbl_5f4xpbl_5f32beat_44',['ETH_DMABMR_PBL_4xPBL_32Beat',['../group___peripheral___registers___bits___definition.html#ga21298fccc783e5c6d65b9d64960b4ca2',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmabmr_5fpbl_5f4xpbl_5f4beat_45',['ETH_DMABMR_PBL_4xPBL_4Beat',['../group___peripheral___registers___bits___definition.html#ga89566024f4f6772d59592f5bacc7828d',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmabmr_5fpbl_5f4xpbl_5f64beat_46',['ETH_DMABMR_PBL_4xPBL_64Beat',['../group___peripheral___registers___bits___definition.html#ga40a789fc58356a8084c5f1eeba366de2',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmabmr_5fpbl_5f4xpbl_5f8beat_47',['ETH_DMABMR_PBL_4xPBL_8Beat',['../group___peripheral___registers___bits___definition.html#ga33acf850c7d6f97899f69d76d87a3dd6',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmabmr_5fpbl_5f8beat_48',['ETH_DMABMR_PBL_8Beat',['../group___peripheral___registers___bits___definition.html#gae920200ec813649824a20b434c1eecb5',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmabmr_5fpbl_5fmsk_49',['ETH_DMABMR_PBL_Msk',['../group___peripheral___registers___bits___definition.html#ga640bcbad2f68125c7593018245c80db6',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmabmr_5fpbl_5fpos_50',['ETH_DMABMR_PBL_Pos',['../group___peripheral___registers___bits___definition.html#ga4b37497a07a1d574524931c0d35f62a1',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmabmr_5frdp_51',['ETH_DMABMR_RDP',['../group___peripheral___registers___bits___definition.html#ga4f8be5fad8f704e418e3d799d4c6d3d1',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmabmr_5frdp_5f16beat_52',['ETH_DMABMR_RDP_16Beat',['../group___peripheral___registers___bits___definition.html#ga2ed1d26d7d55828eadcea86f774c5dd3',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmabmr_5frdp_5f1beat_53',['ETH_DMABMR_RDP_1Beat',['../group___peripheral___registers___bits___definition.html#gac56caa9d3b3a4300bd1aa0405131d7b9',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmabmr_5frdp_5f2beat_54',['ETH_DMABMR_RDP_2Beat',['../group___peripheral___registers___bits___definition.html#gaaf9bcd9870547bd6f454db6667ccdecb',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmabmr_5frdp_5f32beat_55',['ETH_DMABMR_RDP_32Beat',['../group___peripheral___registers___bits___definition.html#ga3636f50cc2841e5a945f7e908420cbd5',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmabmr_5frdp_5f4beat_56',['ETH_DMABMR_RDP_4Beat',['../group___peripheral___registers___bits___definition.html#gaf514499cdf6581fdcff5eaad5e6ab12f',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmabmr_5frdp_5f4xpbl_5f128beat_57',['ETH_DMABMR_RDP_4xPBL_128Beat',['../group___peripheral___registers___bits___definition.html#ga5ea2c20d00d2428c5f6a8fe4d7ebb392',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmabmr_5frdp_5f4xpbl_5f16beat_58',['ETH_DMABMR_RDP_4xPBL_16Beat',['../group___peripheral___registers___bits___definition.html#ga3ebf97fad14c750a087ed09210e42a1b',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmabmr_5frdp_5f4xpbl_5f32beat_59',['ETH_DMABMR_RDP_4xPBL_32Beat',['../group___peripheral___registers___bits___definition.html#gaf5e2d5606e920b57f303f032b0bad32b',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmabmr_5frdp_5f4xpbl_5f4beat_60',['ETH_DMABMR_RDP_4xPBL_4Beat',['../group___peripheral___registers___bits___definition.html#ga2a8ea3f877aaa74f8ea2d1a788ae3180',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmabmr_5frdp_5f4xpbl_5f64beat_61',['ETH_DMABMR_RDP_4xPBL_64Beat',['../group___peripheral___registers___bits___definition.html#gad1eab5835a2d15d943d5a8fbed274478',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmabmr_5frdp_5f4xpbl_5f8beat_62',['ETH_DMABMR_RDP_4xPBL_8Beat',['../group___peripheral___registers___bits___definition.html#ga7f0258c404d957601ae069a77c82d39b',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmabmr_5frdp_5f8beat_63',['ETH_DMABMR_RDP_8Beat',['../group___peripheral___registers___bits___definition.html#gad5b0089dafe1c8c2410127e93ea40681',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmabmr_5frdp_5fmsk_64',['ETH_DMABMR_RDP_Msk',['../group___peripheral___registers___bits___definition.html#ga45be619f0c8fa338658381e077b36fbb',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmabmr_5frdp_5fpos_65',['ETH_DMABMR_RDP_Pos',['../group___peripheral___registers___bits___definition.html#ga9e6b2716719f507d7cb5e7d140ac6fb9',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmabmr_5frtpr_66',['ETH_DMABMR_RTPR',['../group___peripheral___registers___bits___definition.html#gae06b7c29931b088e66f13b055aaddcd6',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmabmr_5frtpr_5f1_5f1_67',['ETH_DMABMR_RTPR_1_1',['../group___peripheral___registers___bits___definition.html#ga478e7d5ec02db7237be51fa5b83b9e25',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmabmr_5frtpr_5f2_5f1_68',['ETH_DMABMR_RTPR_2_1',['../group___peripheral___registers___bits___definition.html#ga1d9e5dda525076cc163bdc29f18e4055',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmabmr_5frtpr_5f3_5f1_69',['ETH_DMABMR_RTPR_3_1',['../group___peripheral___registers___bits___definition.html#gaf9e4fd353c5a9ecee3feb428eb54ce2b',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmabmr_5frtpr_5f4_5f1_70',['ETH_DMABMR_RTPR_4_1',['../group___peripheral___registers___bits___definition.html#gaad6d57a1f21bc958fa0cfab0cfed02b1',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmabmr_5frtpr_5fmsk_71',['ETH_DMABMR_RTPR_Msk',['../group___peripheral___registers___bits___definition.html#gac84d16b246ae40bcd90ef3a5a000bc59',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmabmr_5frtpr_5fpos_72',['ETH_DMABMR_RTPR_Pos',['../group___peripheral___registers___bits___definition.html#ga7e0752bf3c2a9ad5f6c2539dcf50a849',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmabmr_5fsr_73',['ETH_DMABMR_SR',['../group___peripheral___registers___bits___definition.html#ga2e8dfe321aeaecaa87e290f4d6e710dc',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmabmr_5fsr_5fmsk_74',['ETH_DMABMR_SR_Msk',['../group___peripheral___registers___bits___definition.html#gadf0350e3541f1c466e6544db265e36a4',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmabmr_5fsr_5fpos_75',['ETH_DMABMR_SR_Pos',['../group___peripheral___registers___bits___definition.html#gacef0ceff9d1440c18e92a28da757a8df',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmabmr_5fusp_76',['ETH_DMABMR_USP',['../group___peripheral___registers___bits___definition.html#ga91e71c4054613222a8610bde0b191d00',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmabmr_5fusp_5fmsk_77',['ETH_DMABMR_USP_Msk',['../group___peripheral___registers___bits___definition.html#ga9f99d342b5c91127b4ab8a4b34ab19f8',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmabmr_5fusp_5fpos_78',['ETH_DMABMR_USP_Pos',['../group___peripheral___registers___bits___definition.html#gae9c6b22e49c424a0c8380a6ac0b1716a',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmachrbar_5fhrbap_79',['ETH_DMACHRBAR_HRBAP',['../group___peripheral___registers___bits___definition.html#ga1cf1a9ed443f3498b67c658d26468212',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmachrbar_5fhrbap_5fmsk_80',['ETH_DMACHRBAR_HRBAP_Msk',['../group___peripheral___registers___bits___definition.html#ga6260b879f63938dfecd17e8d98f0a6dc',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmachrbar_5fhrbap_5fpos_81',['ETH_DMACHRBAR_HRBAP_Pos',['../group___peripheral___registers___bits___definition.html#ga7efa5638b78f19fc5df0386817347add',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmachrdr_5fhrdap_82',['ETH_DMACHRDR_HRDAP',['../group___peripheral___registers___bits___definition.html#gacb91f0f377b2bb0bfffe7df0ad46c7d3',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmachrdr_5fhrdap_5fmsk_83',['ETH_DMACHRDR_HRDAP_Msk',['../group___peripheral___registers___bits___definition.html#ga385d61115e00ef2711fb128ba0bc58a8',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmachrdr_5fhrdap_5fpos_84',['ETH_DMACHRDR_HRDAP_Pos',['../group___peripheral___registers___bits___definition.html#ga28f70ba69e471a3c4142c22529f41057',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmachtbar_5fhtbap_85',['ETH_DMACHTBAR_HTBAP',['../group___peripheral___registers___bits___definition.html#gad3524cdddc8525fe50c6754029011e12',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmachtbar_5fhtbap_5fmsk_86',['ETH_DMACHTBAR_HTBAP_Msk',['../group___peripheral___registers___bits___definition.html#gaacc327724f91b8ddb36f526ec8d78dfa',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmachtbar_5fhtbap_5fpos_87',['ETH_DMACHTBAR_HTBAP_Pos',['../group___peripheral___registers___bits___definition.html#gac708faf2f587cf1d4b48a9d9d864dad8',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmachtdr_5fhtdap_88',['ETH_DMACHTDR_HTDAP',['../group___peripheral___registers___bits___definition.html#gae013d158ee1e13f61069722eff4d52ac',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmachtdr_5fhtdap_5fmsk_89',['ETH_DMACHTDR_HTDAP_Msk',['../group___peripheral___registers___bits___definition.html#ga9e0d1eda1d389b3f99bbe46f26a25959',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmachtdr_5fhtdap_5fpos_90',['ETH_DMACHTDR_HTDAP_Pos',['../group___peripheral___registers___bits___definition.html#gac66c32e504b7893aab68fb675b30686f',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmaier_5faise_91',['ETH_DMAIER_AISE',['../group___peripheral___registers___bits___definition.html#ga7ae9340fa928abb4664efbb5c8478756',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmaier_5faise_5fmsk_92',['ETH_DMAIER_AISE_Msk',['../group___peripheral___registers___bits___definition.html#gabde04568b44b661a4ae2938663c0af68',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmaier_5faise_5fpos_93',['ETH_DMAIER_AISE_Pos',['../group___peripheral___registers___bits___definition.html#gaea77db4415f16fb34552c4f2e4672ec2',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmaier_5ferie_94',['ETH_DMAIER_ERIE',['../group___peripheral___registers___bits___definition.html#ga4fe43c4432e0505a5509424665692807',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmaier_5ferie_5fmsk_95',['ETH_DMAIER_ERIE_Msk',['../group___peripheral___registers___bits___definition.html#gac2fbc6e64e1d5c1bf78ada2bf0bef741',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmaier_5ferie_5fpos_96',['ETH_DMAIER_ERIE_Pos',['../group___peripheral___registers___bits___definition.html#gabf996fdcd5fe7a43c250aee861d96cf8',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmaier_5fetie_97',['ETH_DMAIER_ETIE',['../group___peripheral___registers___bits___definition.html#ga5b1c57b5102ca78372420b45a707b43e',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmaier_5fetie_5fmsk_98',['ETH_DMAIER_ETIE_Msk',['../group___peripheral___registers___bits___definition.html#gac753c8cb27122c6d9bb32ab8cfc2ae64',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmaier_5fetie_5fpos_99',['ETH_DMAIER_ETIE_Pos',['../group___peripheral___registers___bits___definition.html#ga369f3ea6bca9aebeceaf6b6d4d51b485',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmaier_5ffbeie_100',['ETH_DMAIER_FBEIE',['../group___peripheral___registers___bits___definition.html#ga92e94d1d37660b7cca9306ac020b4110',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmaier_5ffbeie_5fmsk_101',['ETH_DMAIER_FBEIE_Msk',['../group___peripheral___registers___bits___definition.html#gab1d818d82852308c7dc3884e4ab6bd0d',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmaier_5ffbeie_5fpos_102',['ETH_DMAIER_FBEIE_Pos',['../group___peripheral___registers___bits___definition.html#ga0e17cb26491d68d522f4aec00288a171',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmaier_5fnise_103',['ETH_DMAIER_NISE',['../group___peripheral___registers___bits___definition.html#ga3c12b833cb206d8bafa7d60faebea805',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmaier_5fnise_5fmsk_104',['ETH_DMAIER_NISE_Msk',['../group___peripheral___registers___bits___definition.html#ga1c8386338d800b390b1a94a7bf353b0b',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmaier_5fnise_5fpos_105',['ETH_DMAIER_NISE_Pos',['../group___peripheral___registers___bits___definition.html#ga6c2bf9775f1b2daae49c199875633b31',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmaier_5frbuie_106',['ETH_DMAIER_RBUIE',['../group___peripheral___registers___bits___definition.html#ga0c349d0b4aa329d39fcfd10d59de7b26',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmaier_5frbuie_5fmsk_107',['ETH_DMAIER_RBUIE_Msk',['../group___peripheral___registers___bits___definition.html#gada6ce4050a22be8bf8ecd9f32a62cb51',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmaier_5frbuie_5fpos_108',['ETH_DMAIER_RBUIE_Pos',['../group___peripheral___registers___bits___definition.html#gac599bb486eff43714e2340c066df6d22',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmaier_5frie_109',['ETH_DMAIER_RIE',['../group___peripheral___registers___bits___definition.html#ga4bce67fd8ee3363c1ab95b9f5324f745',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmaier_5frie_5fmsk_110',['ETH_DMAIER_RIE_Msk',['../group___peripheral___registers___bits___definition.html#gab5bd8f0165aaa498cdafe884dd1343d9',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmaier_5frie_5fpos_111',['ETH_DMAIER_RIE_Pos',['../group___peripheral___registers___bits___definition.html#gaba03ad718ced9224bb8b34762994818e',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmaier_5froie_112',['ETH_DMAIER_ROIE',['../group___peripheral___registers___bits___definition.html#gab3cdf8611ab9a0a7f4fc0e0090a33ba6',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmaier_5froie_5fmsk_113',['ETH_DMAIER_ROIE_Msk',['../group___peripheral___registers___bits___definition.html#gaf567f33d5a3d85984e52c65705f2c334',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmaier_5froie_5fpos_114',['ETH_DMAIER_ROIE_Pos',['../group___peripheral___registers___bits___definition.html#ga2e9037ad879e5483c5c2bb1989a09b89',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmaier_5frpsie_115',['ETH_DMAIER_RPSIE',['../group___peripheral___registers___bits___definition.html#gafcfba49acf14e8a0194e1fef8b1837f7',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmaier_5frpsie_5fmsk_116',['ETH_DMAIER_RPSIE_Msk',['../group___peripheral___registers___bits___definition.html#ga97d3ac01bc13ea08b25b59e5e200aaf4',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmaier_5frpsie_5fpos_117',['ETH_DMAIER_RPSIE_Pos',['../group___peripheral___registers___bits___definition.html#ga83ecac2aa610bfebcf7ae2d63d8afbb2',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmaier_5frwtie_118',['ETH_DMAIER_RWTIE',['../group___peripheral___registers___bits___definition.html#gaa28e115ada97b2e6d793f9d542f93e35',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmaier_5frwtie_5fmsk_119',['ETH_DMAIER_RWTIE_Msk',['../group___peripheral___registers___bits___definition.html#ga6a773793e51e25028b71f7bc22127a84',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmaier_5frwtie_5fpos_120',['ETH_DMAIER_RWTIE_Pos',['../group___peripheral___registers___bits___definition.html#ga89d02c397b29b9a25d117baef252c11d',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmaier_5ftbuie_121',['ETH_DMAIER_TBUIE',['../group___peripheral___registers___bits___definition.html#ga37fc5c9c473407d77a379d7032147b59',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmaier_5ftbuie_5fmsk_122',['ETH_DMAIER_TBUIE_Msk',['../group___peripheral___registers___bits___definition.html#ga38bf7b752b9e72761ab2bd11400e7730',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmaier_5ftbuie_5fpos_123',['ETH_DMAIER_TBUIE_Pos',['../group___peripheral___registers___bits___definition.html#ga436fa7c9599495a1a1a55eb40ec00d63',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmaier_5ftie_124',['ETH_DMAIER_TIE',['../group___peripheral___registers___bits___definition.html#ga1a19f069ddf349de788130cefdbc4149',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmaier_5ftie_5fmsk_125',['ETH_DMAIER_TIE_Msk',['../group___peripheral___registers___bits___definition.html#ga6a48f7292330cdb3c61e4e499357eb8b',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmaier_5ftie_5fpos_126',['ETH_DMAIER_TIE_Pos',['../group___peripheral___registers___bits___definition.html#gab7498e400e393f90604c092ce9bd5e74',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmaier_5ftjtie_127',['ETH_DMAIER_TJTIE',['../group___peripheral___registers___bits___definition.html#ga7a9cd48115f0b32941ee3087e9c60ec9',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmaier_5ftjtie_5fmsk_128',['ETH_DMAIER_TJTIE_Msk',['../group___peripheral___registers___bits___definition.html#gaf14e7f30233722f892e6af1d6428f7b8',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmaier_5ftjtie_5fpos_129',['ETH_DMAIER_TJTIE_Pos',['../group___peripheral___registers___bits___definition.html#gad439769a7926aaf62c3053133fe87beb',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmaier_5ftpsie_130',['ETH_DMAIER_TPSIE',['../group___peripheral___registers___bits___definition.html#ga3d4b2c3e0d50326adf0e8b3955aa9972',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmaier_5ftpsie_5fmsk_131',['ETH_DMAIER_TPSIE_Msk',['../group___peripheral___registers___bits___definition.html#gaa8db6095575b73d506673d78d355fdcb',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmaier_5ftpsie_5fpos_132',['ETH_DMAIER_TPSIE_Pos',['../group___peripheral___registers___bits___definition.html#ga08ab269c60b0052ee58983d0fd7ceff0',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmaier_5ftuie_133',['ETH_DMAIER_TUIE',['../group___peripheral___registers___bits___definition.html#ga91a59aa3adff595051bdda2da948ec71',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmaier_5ftuie_5fmsk_134',['ETH_DMAIER_TUIE_Msk',['../group___peripheral___registers___bits___definition.html#ga3479e12a504721ace0d9c1f2e9deae52',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmaier_5ftuie_5fpos_135',['ETH_DMAIER_TUIE_Pos',['../group___peripheral___registers___bits___definition.html#gafe6b97c4e2981f246308d884fb2acd78',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmamfbocr_5fmfa_136',['ETH_DMAMFBOCR_MFA',['../group___peripheral___registers___bits___definition.html#ga9595307f4b9d38f6e0991fa54c4bae8f',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmamfbocr_5fmfa_5fmsk_137',['ETH_DMAMFBOCR_MFA_Msk',['../group___peripheral___registers___bits___definition.html#ga265274e3d4f38a6e39a08b112fef1b63',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmamfbocr_5fmfa_5fpos_138',['ETH_DMAMFBOCR_MFA_Pos',['../group___peripheral___registers___bits___definition.html#gadf9e76a42bbf3d3b6de19402dc3c9cfa',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmamfbocr_5fmfc_139',['ETH_DMAMFBOCR_MFC',['../group___peripheral___registers___bits___definition.html#ga81aa193a52d5b3757a008b84eb0c6182',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmamfbocr_5fmfc_5fmsk_140',['ETH_DMAMFBOCR_MFC_Msk',['../group___peripheral___registers___bits___definition.html#gac16af00ecd2def9c483943a7b60bb6ff',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmamfbocr_5fmfc_5fpos_141',['ETH_DMAMFBOCR_MFC_Pos',['../group___peripheral___registers___bits___definition.html#gac9fd0920c44a894d3e2984214df300b3',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmamfbocr_5fofoc_142',['ETH_DMAMFBOCR_OFOC',['../group___peripheral___registers___bits___definition.html#ga3793f0a194ff3a19a1559824a821fe61',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmamfbocr_5fofoc_5fmsk_143',['ETH_DMAMFBOCR_OFOC_Msk',['../group___peripheral___registers___bits___definition.html#gaff5db91b32eee3facb9523b1e8c7f836',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmamfbocr_5fofoc_5fpos_144',['ETH_DMAMFBOCR_OFOC_Pos',['../group___peripheral___registers___bits___definition.html#ga8b868e9111c52d02c0df2319e41e40b2',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmamfbocr_5fomfc_145',['ETH_DMAMFBOCR_OMFC',['../group___peripheral___registers___bits___definition.html#ga9ffc962868d2b5ed265e7bffd6881aab',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmamfbocr_5fomfc_5fmsk_146',['ETH_DMAMFBOCR_OMFC_Msk',['../group___peripheral___registers___bits___definition.html#ga948b0af4c7ca43ee7b22e4db7318c6fd',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmamfbocr_5fomfc_5fpos_147',['ETH_DMAMFBOCR_OMFC_Pos',['../group___peripheral___registers___bits___definition.html#ga0d8683626bc1e997264dc41e58d7b1e9',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmaomr_5fdfrf_148',['ETH_DMAOMR_DFRF',['../group___peripheral___registers___bits___definition.html#ga61cfaa51bb7973e7e3c4fd6d549c88b2',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmaomr_5fdfrf_5fmsk_149',['ETH_DMAOMR_DFRF_Msk',['../group___peripheral___registers___bits___definition.html#ga58b42f95e34f9fd0fd26a720830cef43',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmaomr_5fdfrf_5fpos_150',['ETH_DMAOMR_DFRF_Pos',['../group___peripheral___registers___bits___definition.html#gab2b6e2a9d1a9466c95e92fe1a095158f',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmaomr_5fdtcefd_151',['ETH_DMAOMR_DTCEFD',['../group___peripheral___registers___bits___definition.html#gade93bfc37c0b1fc371b2fa1278ee7dfd',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmaomr_5fdtcefd_5fmsk_152',['ETH_DMAOMR_DTCEFD_Msk',['../group___peripheral___registers___bits___definition.html#ga57a12e235193d9a8db8d635b59287bdc',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmaomr_5fdtcefd_5fpos_153',['ETH_DMAOMR_DTCEFD_Pos',['../group___peripheral___registers___bits___definition.html#ga60ee4d9125ea52f825f501b8fb3a5023',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmaomr_5ffef_154',['ETH_DMAOMR_FEF',['../group___peripheral___registers___bits___definition.html#ga9ff2d7be55ac4e29a18d8490012d8d8f',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmaomr_5ffef_5fmsk_155',['ETH_DMAOMR_FEF_Msk',['../group___peripheral___registers___bits___definition.html#ga46da3dc9006268330b091ea369040c7e',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmaomr_5ffef_5fpos_156',['ETH_DMAOMR_FEF_Pos',['../group___peripheral___registers___bits___definition.html#ga4562507352bcedf8243532c8f3509cd1',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmaomr_5fftf_157',['ETH_DMAOMR_FTF',['../group___peripheral___registers___bits___definition.html#ga6ba6031456a00e99638005b7af823a49',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmaomr_5fftf_5fmsk_158',['ETH_DMAOMR_FTF_Msk',['../group___peripheral___registers___bits___definition.html#ga2ef2167aa40e49e8f8d49b0283a8f832',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmaomr_5fftf_5fpos_159',['ETH_DMAOMR_FTF_Pos',['../group___peripheral___registers___bits___definition.html#gae8d8c2e989f7e596b73202f7c41361c7',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmaomr_5ffugf_160',['ETH_DMAOMR_FUGF',['../group___peripheral___registers___bits___definition.html#gad7fb0b48ffa17fb3c37e730e63790b95',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmaomr_5ffugf_5fmsk_161',['ETH_DMAOMR_FUGF_Msk',['../group___peripheral___registers___bits___definition.html#gafb00925901abe34858a008f599a3949d',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmaomr_5ffugf_5fpos_162',['ETH_DMAOMR_FUGF_Pos',['../group___peripheral___registers___bits___definition.html#gad86ef8a3fdd31501c9ad670c6e0ee358',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmaomr_5fosf_163',['ETH_DMAOMR_OSF',['../group___peripheral___registers___bits___definition.html#ga6a9e1270eefa558420deba526b7cd2c2',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmaomr_5fosf_5fmsk_164',['ETH_DMAOMR_OSF_Msk',['../group___peripheral___registers___bits___definition.html#ga3643718f1c533d40fd4f9868544cdb66',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmaomr_5fosf_5fpos_165',['ETH_DMAOMR_OSF_Pos',['../group___peripheral___registers___bits___definition.html#gae0704646af78b6cf53b47640835429ae',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmaomr_5frsf_166',['ETH_DMAOMR_RSF',['../group___peripheral___registers___bits___definition.html#ga7132ff722841d431f9c6d3fc7e0c8912',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmaomr_5frsf_5fmsk_167',['ETH_DMAOMR_RSF_Msk',['../group___peripheral___registers___bits___definition.html#gac86b0ef8cd7b378ad33471bf63fabf28',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmaomr_5frsf_5fpos_168',['ETH_DMAOMR_RSF_Pos',['../group___peripheral___registers___bits___definition.html#gac568f4c7cfdae0a997fae6d41b397772',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmaomr_5frtc_169',['ETH_DMAOMR_RTC',['../group___peripheral___registers___bits___definition.html#ga00653932f863ff8c73752e4dea63283d',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmaomr_5frtc_5f128bytes_170',['ETH_DMAOMR_RTC_128Bytes',['../group___peripheral___registers___bits___definition.html#gab7099f07f7c61fdc118cebe38db796e9',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmaomr_5frtc_5f32bytes_171',['ETH_DMAOMR_RTC_32Bytes',['../group___peripheral___registers___bits___definition.html#ga6f4f5e1950abb65d6ed23e30994b7a26',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmaomr_5frtc_5f64bytes_172',['ETH_DMAOMR_RTC_64Bytes',['../group___peripheral___registers___bits___definition.html#ga29ec3c609bf796437bb50879be53974e',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmaomr_5frtc_5f96bytes_173',['ETH_DMAOMR_RTC_96Bytes',['../group___peripheral___registers___bits___definition.html#gaf73706fb0cf9a03909a55e3bcd19c75c',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmaomr_5frtc_5fmsk_174',['ETH_DMAOMR_RTC_Msk',['../group___peripheral___registers___bits___definition.html#ga6a10ffb355ad5a39fcee6c591a74c4f1',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmaomr_5frtc_5fpos_175',['ETH_DMAOMR_RTC_Pos',['../group___peripheral___registers___bits___definition.html#ga67e6a96f920fd6dbe951e83bab2fcbc8',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmaomr_5fsr_176',['ETH_DMAOMR_SR',['../group___peripheral___registers___bits___definition.html#gaf08aaa0c916bb56d2e4e71fdf0f034da',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmaomr_5fsr_5fmsk_177',['ETH_DMAOMR_SR_Msk',['../group___peripheral___registers___bits___definition.html#ga16eb92e4f7b229407dcf6e7e836f3504',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmaomr_5fsr_5fpos_178',['ETH_DMAOMR_SR_Pos',['../group___peripheral___registers___bits___definition.html#gaac945eacab78cad8b2f6149ad6ab3570',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmaomr_5fst_179',['ETH_DMAOMR_ST',['../group___peripheral___registers___bits___definition.html#ga5f15d70215b151c4c151b7b8475939ce',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmaomr_5fst_5fmsk_180',['ETH_DMAOMR_ST_Msk',['../group___peripheral___registers___bits___definition.html#gabd2cf0246f5b06eac0b6534c9802ac29',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmaomr_5fst_5fpos_181',['ETH_DMAOMR_ST_Pos',['../group___peripheral___registers___bits___definition.html#ga9e013ae0230f9b0c4f9598bb38c93b1e',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmaomr_5ftsf_182',['ETH_DMAOMR_TSF',['../group___peripheral___registers___bits___definition.html#ga600b35b875335358746524e5f6760613',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmaomr_5ftsf_5fmsk_183',['ETH_DMAOMR_TSF_Msk',['../group___peripheral___registers___bits___definition.html#ga627c0721df614ee7895be0c8603965ab',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmaomr_5ftsf_5fpos_184',['ETH_DMAOMR_TSF_Pos',['../group___peripheral___registers___bits___definition.html#ga3c6ccd5e3a792ff5bb20751121db1ad4',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmaomr_5fttc_185',['ETH_DMAOMR_TTC',['../group___peripheral___registers___bits___definition.html#ga8af2f55493df254efed28cad7fb72651',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmaomr_5fttc_5f128bytes_186',['ETH_DMAOMR_TTC_128Bytes',['../group___peripheral___registers___bits___definition.html#ga0a0af7e5f2074a30e33e4845b1c72155',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmaomr_5fttc_5f16bytes_187',['ETH_DMAOMR_TTC_16Bytes',['../group___peripheral___registers___bits___definition.html#ga6c21df36ca8ecb3c2d016cd4c683aded',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmaomr_5fttc_5f192bytes_188',['ETH_DMAOMR_TTC_192Bytes',['../group___peripheral___registers___bits___definition.html#ga4a29aa54f61418b0086bef0d8c9a4868',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmaomr_5fttc_5f24bytes_189',['ETH_DMAOMR_TTC_24Bytes',['../group___peripheral___registers___bits___definition.html#gac2e990a61fd2ca6d1f5d9e0fddfc1a76',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmaomr_5fttc_5f256bytes_190',['ETH_DMAOMR_TTC_256Bytes',['../group___peripheral___registers___bits___definition.html#gae9d703eb56388097660839c0dbb2dcf4',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmaomr_5fttc_5f32bytes_191',['ETH_DMAOMR_TTC_32Bytes',['../group___peripheral___registers___bits___definition.html#ga3e74522b40a38dbc62dca1cc87f7b13f',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmaomr_5fttc_5f40bytes_192',['ETH_DMAOMR_TTC_40Bytes',['../group___peripheral___registers___bits___definition.html#gac6c6cd2f59e4f784ef22ca7873bcafe6',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmaomr_5fttc_5f64bytes_193',['ETH_DMAOMR_TTC_64Bytes',['../group___peripheral___registers___bits___definition.html#gaca0372554b5b8c2b816071ced929b30f',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmaomr_5fttc_5fmsk_194',['ETH_DMAOMR_TTC_Msk',['../group___peripheral___registers___bits___definition.html#gab3c316b48c8c3a4e683b6e56cefa844d',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmaomr_5fttc_5fpos_195',['ETH_DMAOMR_TTC_Pos',['../group___peripheral___registers___bits___definition.html#ga9b3ede16f6855eec35690336a66089e3',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmardlar_5fsrl_196',['ETH_DMARDLAR_SRL',['../group___peripheral___registers___bits___definition.html#ga34e60ae1c7b80cf199c372b5e701b46e',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmardlar_5fsrl_5fmsk_197',['ETH_DMARDLAR_SRL_Msk',['../group___peripheral___registers___bits___definition.html#gab5cc8aee0138d0f2bfaf2c684376949f',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmardlar_5fsrl_5fpos_198',['ETH_DMARDLAR_SRL_Pos',['../group___peripheral___registers___bits___definition.html#ga3b8637d2710b95d2994fb20e620c6ee5',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmarpdr_5frpd_199',['ETH_DMARPDR_RPD',['../group___peripheral___registers___bits___definition.html#ga83f1c5a5628c6e7dcd853e511eac49e8',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmarpdr_5frpd_5fmsk_200',['ETH_DMARPDR_RPD_Msk',['../group___peripheral___registers___bits___definition.html#ga56d192c68de928fdbb181eb063145446',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmarpdr_5frpd_5fpos_201',['ETH_DMARPDR_RPD_Pos',['../group___peripheral___registers___bits___definition.html#ga05a0babc0d1d7b6a2ff358a8ff819fb5',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmasr_5fais_202',['ETH_DMASR_AIS',['../group___peripheral___registers___bits___definition.html#ga1cb15b33a997bec75b9c8750231ee411',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmasr_5fais_5fmsk_203',['ETH_DMASR_AIS_Msk',['../group___peripheral___registers___bits___definition.html#gaa257027c6436c5549724db8df50284db',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmasr_5fais_5fpos_204',['ETH_DMASR_AIS_Pos',['../group___peripheral___registers___bits___definition.html#gaf97acf90b407e4b509779b5af53d230b',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmasr_5febs_205',['ETH_DMASR_EBS',['../group___peripheral___registers___bits___definition.html#ga098b5395babfd8474a75a5a2034c94f2',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmasr_5febs_5fdatatransftx_206',['ETH_DMASR_EBS_DataTransfTx',['../group___peripheral___registers___bits___definition.html#gacd56804ed872078d962ef5f01dc295e1',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmasr_5febs_5fdatatransftx_5fmsk_207',['ETH_DMASR_EBS_DataTransfTx_Msk',['../group___peripheral___registers___bits___definition.html#gabb5f3f939bfb190ddd5837ecb203a7db',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmasr_5febs_5fdatatransftx_5fpos_208',['ETH_DMASR_EBS_DataTransfTx_Pos',['../group___peripheral___registers___bits___definition.html#gad72b89b7da590a72f8e9061c96111dbf',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmasr_5febs_5fdescaccess_209',['ETH_DMASR_EBS_DescAccess',['../group___peripheral___registers___bits___definition.html#ga42e1dfda0e23a1ae10c0c05c405e5c73',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmasr_5febs_5fdescaccess_5fmsk_210',['ETH_DMASR_EBS_DescAccess_Msk',['../group___peripheral___registers___bits___definition.html#ga2d01e1b20f21d635fd0e195148b12609',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmasr_5febs_5fdescaccess_5fpos_211',['ETH_DMASR_EBS_DescAccess_Pos',['../group___peripheral___registers___bits___definition.html#ga357bae318615787a3891c3c493b916d7',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmasr_5febs_5fmsk_212',['ETH_DMASR_EBS_Msk',['../group___peripheral___registers___bits___definition.html#gabf72d998538d5fcb41440f203e916edc',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmasr_5febs_5fpos_213',['ETH_DMASR_EBS_Pos',['../group___peripheral___registers___bits___definition.html#gad430939a2de7c270ecb359c5d1a32670',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmasr_5febs_5freadtransf_214',['ETH_DMASR_EBS_ReadTransf',['../group___peripheral___registers___bits___definition.html#ga315c68184fd0f0e510539dc8cd986393',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmasr_5febs_5freadtransf_5fmsk_215',['ETH_DMASR_EBS_ReadTransf_Msk',['../group___peripheral___registers___bits___definition.html#ga9ba2f75d57b076dd6fd741eb85569ea0',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmasr_5febs_5freadtransf_5fpos_216',['ETH_DMASR_EBS_ReadTransf_Pos',['../group___peripheral___registers___bits___definition.html#ga3ec84cb6fb224f4511dd259a9947c6b3',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmasr_5fers_217',['ETH_DMASR_ERS',['../group___peripheral___registers___bits___definition.html#ga899d94d62f011fc56aa5814e528055f7',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmasr_5fers_5fmsk_218',['ETH_DMASR_ERS_Msk',['../group___peripheral___registers___bits___definition.html#gab1038a467b90b609a7b709b179334c33',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmasr_5fers_5fpos_219',['ETH_DMASR_ERS_Pos',['../group___peripheral___registers___bits___definition.html#ga08262d444227cc81a46fa9e3b1dff314',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmasr_5fets_220',['ETH_DMASR_ETS',['../group___peripheral___registers___bits___definition.html#gacb828d827c627f704a53dc486cec821c',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmasr_5fets_5fmsk_221',['ETH_DMASR_ETS_Msk',['../group___peripheral___registers___bits___definition.html#ga86649ab55b955dee747af1266d117270',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmasr_5fets_5fpos_222',['ETH_DMASR_ETS_Pos',['../group___peripheral___registers___bits___definition.html#gacea84ae95fd863044bfb89895ce0edc6',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmasr_5ffbes_223',['ETH_DMASR_FBES',['../group___peripheral___registers___bits___definition.html#gab28c0a99d8d2ff948096d06b6dfdab9c',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmasr_5ffbes_5fmsk_224',['ETH_DMASR_FBES_Msk',['../group___peripheral___registers___bits___definition.html#ga616a1ac8f4d7a70430585b6461fc0ce3',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmasr_5ffbes_5fpos_225',['ETH_DMASR_FBES_Pos',['../group___peripheral___registers___bits___definition.html#ga491afda68d7906be911a8be5e16966ae',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmasr_5fmmcs_226',['ETH_DMASR_MMCS',['../group___peripheral___registers___bits___definition.html#ga2d6207fe0c8383456188e9bb1e2fb9fe',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmasr_5fmmcs_5fmsk_227',['ETH_DMASR_MMCS_Msk',['../group___peripheral___registers___bits___definition.html#ga5366f0a075f3c6821b4bade162bfc151',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmasr_5fmmcs_5fpos_228',['ETH_DMASR_MMCS_Pos',['../group___peripheral___registers___bits___definition.html#gadb58a6756ac7507049b458b398a3d6c4',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmasr_5fnis_229',['ETH_DMASR_NIS',['../group___peripheral___registers___bits___definition.html#gad8585a6af3197e49831882373410d94c',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmasr_5fnis_5fmsk_230',['ETH_DMASR_NIS_Msk',['../group___peripheral___registers___bits___definition.html#ga8a4beec3bd9093993f5b2434b1b1e09d',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmasr_5fnis_5fpos_231',['ETH_DMASR_NIS_Pos',['../group___peripheral___registers___bits___definition.html#ga3c5b7e682ca590e3a6069be7111c04eb',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmasr_5fpmts_232',['ETH_DMASR_PMTS',['../group___peripheral___registers___bits___definition.html#ga4792ff5cd86cdea1edf34ea90448b34a',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmasr_5fpmts_5fmsk_233',['ETH_DMASR_PMTS_Msk',['../group___peripheral___registers___bits___definition.html#ga92bdb1d530baa75204516d6c8045f1dc',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmasr_5fpmts_5fpos_234',['ETH_DMASR_PMTS_Pos',['../group___peripheral___registers___bits___definition.html#gaf9532f43143213e838dd0ab5a24caf78',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmasr_5frbus_235',['ETH_DMASR_RBUS',['../group___peripheral___registers___bits___definition.html#ga5569311c70d6ededf186d9a8af19d884',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmasr_5frbus_5fmsk_236',['ETH_DMASR_RBUS_Msk',['../group___peripheral___registers___bits___definition.html#ga03519d5ceec7c307530cd4d84ab77a86',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmasr_5frbus_5fpos_237',['ETH_DMASR_RBUS_Pos',['../group___peripheral___registers___bits___definition.html#gaafcf0fea72f556ad86e10f1f4261fdfe',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmasr_5fros_238',['ETH_DMASR_ROS',['../group___peripheral___registers___bits___definition.html#ga0c2f1e3cb729230b1099026b6a53b867',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmasr_5fros_5fmsk_239',['ETH_DMASR_ROS_Msk',['../group___peripheral___registers___bits___definition.html#ga89c38680c790e1e1717c0a0c76c4f9ef',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmasr_5fros_5fpos_240',['ETH_DMASR_ROS_Pos',['../group___peripheral___registers___bits___definition.html#ga73b5f22a117c3ef116e9506999b5a3a0',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmasr_5frps_241',['ETH_DMASR_RPS',['../group___peripheral___registers___bits___definition.html#gae773175991a44530bcd26057a7b3819e',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmasr_5frps_5fclosing_242',['ETH_DMASR_RPS_Closing',['../group___peripheral___registers___bits___definition.html#ga0976a4ba0b8dcbe42fdef38a8589fda8',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmasr_5frps_5fclosing_5fmsk_243',['ETH_DMASR_RPS_Closing_Msk',['../group___peripheral___registers___bits___definition.html#ga89428a8eb321c17f0d6319d5f8409d6e',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmasr_5frps_5fclosing_5fpos_244',['ETH_DMASR_RPS_Closing_Pos',['../group___peripheral___registers___bits___definition.html#ga3d0d9e0f3ccb8bb117dc2b6b01094ff2',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmasr_5frps_5ffetching_245',['ETH_DMASR_RPS_Fetching',['../group___peripheral___registers___bits___definition.html#ga92a04f8a6f4c047967d38e4fd3f4bbb9',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmasr_5frps_5ffetching_5fmsk_246',['ETH_DMASR_RPS_Fetching_Msk',['../group___peripheral___registers___bits___definition.html#ga6ebd16304081748a0fc85659ca005b74',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmasr_5frps_5ffetching_5fpos_247',['ETH_DMASR_RPS_Fetching_Pos',['../group___peripheral___registers___bits___definition.html#ga4a722459468b128af26661078a2e6dd3',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmasr_5frps_5fmsk_248',['ETH_DMASR_RPS_Msk',['../group___peripheral___registers___bits___definition.html#gade55bf5c8f6788537f16f5c535fca9df',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmasr_5frps_5fpos_249',['ETH_DMASR_RPS_Pos',['../group___peripheral___registers___bits___definition.html#gaeb7b51984ea407e0d049606fcc59b665',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmasr_5frps_5fqueuing_250',['ETH_DMASR_RPS_Queuing',['../group___peripheral___registers___bits___definition.html#gae6aaf0193e4f15e2937cb18586567e43',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmasr_5frps_5fqueuing_5fmsk_251',['ETH_DMASR_RPS_Queuing_Msk',['../group___peripheral___registers___bits___definition.html#ga276f57d8860566be667d03e6f38f9840',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmasr_5frps_5fqueuing_5fpos_252',['ETH_DMASR_RPS_Queuing_Pos',['../group___peripheral___registers___bits___definition.html#ga38c80ba33689333b6f1a08318ebb31b2',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmasr_5frps_5fstopped_253',['ETH_DMASR_RPS_Stopped',['../group___peripheral___registers___bits___definition.html#ga6a2dfc943902722a1bce1d0a24125e45',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmasr_5frps_5fsuspended_254',['ETH_DMASR_RPS_Suspended',['../group___peripheral___registers___bits___definition.html#gad5e1406af058b582a7f60f8415edde15',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmasr_5frps_5fsuspended_5fmsk_255',['ETH_DMASR_RPS_Suspended_Msk',['../group___peripheral___registers___bits___definition.html#gaf1fb0ba5f7b3373caf68328175250e96',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmasr_5frps_5fsuspended_5fpos_256',['ETH_DMASR_RPS_Suspended_Pos',['../group___peripheral___registers___bits___definition.html#ga465fd4ba545bbfa3ba642e65102787de',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmasr_5frps_5fwaiting_257',['ETH_DMASR_RPS_Waiting',['../group___peripheral___registers___bits___definition.html#ga5440bd06e487e3ca5d64afebc8b48bac',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmasr_5frps_5fwaiting_5fmsk_258',['ETH_DMASR_RPS_Waiting_Msk',['../group___peripheral___registers___bits___definition.html#ga02f12914ed1c79ed445e5dbbb0e085aa',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmasr_5frps_5fwaiting_5fpos_259',['ETH_DMASR_RPS_Waiting_Pos',['../group___peripheral___registers___bits___definition.html#ga69b95466c40968273837da5388e29d26',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmasr_5frpss_260',['ETH_DMASR_RPSS',['../group___peripheral___registers___bits___definition.html#ga70de31c814e36b7bb2b752e7b62bf840',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmasr_5frpss_5fmsk_261',['ETH_DMASR_RPSS_Msk',['../group___peripheral___registers___bits___definition.html#gad2630d1d889e82544e5f3eaaa0c73efb',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmasr_5frpss_5fpos_262',['ETH_DMASR_RPSS_Pos',['../group___peripheral___registers___bits___definition.html#ga67f272abdf029d7a2f9d8f111df46102',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmasr_5frs_263',['ETH_DMASR_RS',['../group___peripheral___registers___bits___definition.html#ga40f33df77007eab0110e1ffef365a2df',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmasr_5frs_5fmsk_264',['ETH_DMASR_RS_Msk',['../group___peripheral___registers___bits___definition.html#gad460f6aaea486c070dec64bbe36e7fa8',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmasr_5frs_5fpos_265',['ETH_DMASR_RS_Pos',['../group___peripheral___registers___bits___definition.html#ga6121b0165acc877d7927a4c4c4cde2d0',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmasr_5frwts_266',['ETH_DMASR_RWTS',['../group___peripheral___registers___bits___definition.html#ga3ce8d0c087f96b2b5c3e1db45cd1ecf5',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmasr_5frwts_5fmsk_267',['ETH_DMASR_RWTS_Msk',['../group___peripheral___registers___bits___definition.html#ga1a3f72a3dc3b046d2771cdcbf514b175',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmasr_5frwts_5fpos_268',['ETH_DMASR_RWTS_Pos',['../group___peripheral___registers___bits___definition.html#ga54e86ee5eaafdcced3a4d545fa49525a',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmasr_5ftbus_269',['ETH_DMASR_TBUS',['../group___peripheral___registers___bits___definition.html#ga26668ea80a2d794d72c0a441aa73d0d7',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmasr_5ftbus_5fmsk_270',['ETH_DMASR_TBUS_Msk',['../group___peripheral___registers___bits___definition.html#gaca6dd2813fb9e0bdf4bccedba156e4c7',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmasr_5ftbus_5fpos_271',['ETH_DMASR_TBUS_Pos',['../group___peripheral___registers___bits___definition.html#gadae620d299f7887143c10c6b67953637',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmasr_5ftjts_272',['ETH_DMASR_TJTS',['../group___peripheral___registers___bits___definition.html#ga8c543637a7e9669b8bdb12265b5ff448',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmasr_5ftjts_5fmsk_273',['ETH_DMASR_TJTS_Msk',['../group___peripheral___registers___bits___definition.html#ga43884645887bb7d31bf18e4e5709d7dc',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmasr_5ftjts_5fpos_274',['ETH_DMASR_TJTS_Pos',['../group___peripheral___registers___bits___definition.html#ga1736d46500149b490b990061e0e6504a',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmasr_5ftps_275',['ETH_DMASR_TPS',['../group___peripheral___registers___bits___definition.html#ga806073adcecb9139b1c1d7ed35a4f37c',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmasr_5ftps_5fclosing_276',['ETH_DMASR_TPS_Closing',['../group___peripheral___registers___bits___definition.html#gaf6e95d2a805ec4d8e50de467825c86e0',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmasr_5ftps_5fclosing_5fmsk_277',['ETH_DMASR_TPS_Closing_Msk',['../group___peripheral___registers___bits___definition.html#ga367081b68077417f3556e514f5ca1771',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmasr_5ftps_5fclosing_5fpos_278',['ETH_DMASR_TPS_Closing_Pos',['../group___peripheral___registers___bits___definition.html#ga98d18b94cc18a69e4522d1d4b4249a8e',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmasr_5ftps_5ffetching_279',['ETH_DMASR_TPS_Fetching',['../group___peripheral___registers___bits___definition.html#gadd9af883f17d4bbbdde6866ecf67afe2',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmasr_5ftps_5ffetching_5fmsk_280',['ETH_DMASR_TPS_Fetching_Msk',['../group___peripheral___registers___bits___definition.html#ga81cc65263215ebdbae36ff6f983e5611',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmasr_5ftps_5ffetching_5fpos_281',['ETH_DMASR_TPS_Fetching_Pos',['../group___peripheral___registers___bits___definition.html#ga85ca0bb143abb15cf11a7edd9d5ca974',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmasr_5ftps_5fmsk_282',['ETH_DMASR_TPS_Msk',['../group___peripheral___registers___bits___definition.html#ga706f64bbf5b12368955bc3d0fdba6a39',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmasr_5ftps_5fpos_283',['ETH_DMASR_TPS_Pos',['../group___peripheral___registers___bits___definition.html#gae9c98699ea2df54364b5232ff3d1cd30',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmasr_5ftps_5freading_284',['ETH_DMASR_TPS_Reading',['../group___peripheral___registers___bits___definition.html#ga72af54920faf4b54e760c3784dccaf65',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmasr_5ftps_5freading_5fmsk_285',['ETH_DMASR_TPS_Reading_Msk',['../group___peripheral___registers___bits___definition.html#ga76229b644063a64e1939b3c9e75c2539',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmasr_5ftps_5freading_5fpos_286',['ETH_DMASR_TPS_Reading_Pos',['../group___peripheral___registers___bits___definition.html#gae1f8f06d72c8a90d32f78cd39ba9abee',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmasr_5ftps_5fstopped_287',['ETH_DMASR_TPS_Stopped',['../group___peripheral___registers___bits___definition.html#ga0c0d4830c8196127e9b26178b23b6f3e',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmasr_5ftps_5fsuspended_288',['ETH_DMASR_TPS_Suspended',['../group___peripheral___registers___bits___definition.html#ga80b3558db79b5903dd3966ceed7bb1e8',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmasr_5ftps_5fsuspended_5fmsk_289',['ETH_DMASR_TPS_Suspended_Msk',['../group___peripheral___registers___bits___definition.html#gabebe05fb2f636f75f5cd2da28d465d8d',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmasr_5ftps_5fsuspended_5fpos_290',['ETH_DMASR_TPS_Suspended_Pos',['../group___peripheral___registers___bits___definition.html#gac1d5230313ea8ab7b2990fac846a769b',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmasr_5ftps_5fwaiting_291',['ETH_DMASR_TPS_Waiting',['../group___peripheral___registers___bits___definition.html#ga351ab7003c342ab1b43f9fd158fdc00d',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmasr_5ftps_5fwaiting_5fmsk_292',['ETH_DMASR_TPS_Waiting_Msk',['../group___peripheral___registers___bits___definition.html#ga372a83db64b04814ac01ef9b072bdb09',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmasr_5ftps_5fwaiting_5fpos_293',['ETH_DMASR_TPS_Waiting_Pos',['../group___peripheral___registers___bits___definition.html#ga73cefac3fbaeed6be54b48bd24de4b8b',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmasr_5ftpss_294',['ETH_DMASR_TPSS',['../group___peripheral___registers___bits___definition.html#gad48c871e98a7794ce6cd8294baee114a',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmasr_5ftpss_5fmsk_295',['ETH_DMASR_TPSS_Msk',['../group___peripheral___registers___bits___definition.html#ga531f361a12151e7c1335f9133526edb5',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmasr_5ftpss_5fpos_296',['ETH_DMASR_TPSS_Pos',['../group___peripheral___registers___bits___definition.html#ga98138bcfbccf33bbfe3e5556ebf5d394',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmasr_5fts_297',['ETH_DMASR_TS',['../group___peripheral___registers___bits___definition.html#ga9aa47191609cba66df647cb7e8e10974',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmasr_5fts_5fmsk_298',['ETH_DMASR_TS_Msk',['../group___peripheral___registers___bits___definition.html#gabfe8fdf02110a1d44c6f28f1d641d92f',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmasr_5fts_5fpos_299',['ETH_DMASR_TS_Pos',['../group___peripheral___registers___bits___definition.html#gab853a917a2d74fa41e630058426b301d',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmasr_5ftsts_300',['ETH_DMASR_TSTS',['../group___peripheral___registers___bits___definition.html#gac55027d33ea49f5498f5c9a0dab629d7',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmasr_5ftsts_5fmsk_301',['ETH_DMASR_TSTS_Msk',['../group___peripheral___registers___bits___definition.html#ga72e40eb362f28f7ea04d874e73e70072',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmasr_5ftsts_5fpos_302',['ETH_DMASR_TSTS_Pos',['../group___peripheral___registers___bits___definition.html#ga3f397466df0a01f13dbc1487726a6fbc',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmasr_5ftus_303',['ETH_DMASR_TUS',['../group___peripheral___registers___bits___definition.html#gaf2597865c464586829cec4f8d26fb1f1',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmasr_5ftus_5fmsk_304',['ETH_DMASR_TUS_Msk',['../group___peripheral___registers___bits___definition.html#gab3a7203a5fb55c1d6a69e6daab2e961b',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmasr_5ftus_5fpos_305',['ETH_DMASR_TUS_Pos',['../group___peripheral___registers___bits___definition.html#gaea24133f548e4e4cfc21d0074a61a2e6',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmatdlar_5fstl_306',['ETH_DMATDLAR_STL',['../group___peripheral___registers___bits___definition.html#ga8f9f12964bc4e019afface14df2dc87c',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmatdlar_5fstl_5fmsk_307',['ETH_DMATDLAR_STL_Msk',['../group___peripheral___registers___bits___definition.html#ga001a009e3ed3f0fa5c8b8d99839d4f16',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmatdlar_5fstl_5fpos_308',['ETH_DMATDLAR_STL_Pos',['../group___peripheral___registers___bits___definition.html#gae6a7932a4408e67d5c10d5a2d18f9385',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmatpdr_5ftpd_309',['ETH_DMATPDR_TPD',['../group___peripheral___registers___bits___definition.html#gaef2d9dbefaa6940adf6422092fae2da6',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmatpdr_5ftpd_5fmsk_310',['ETH_DMATPDR_TPD_Msk',['../group___peripheral___registers___bits___definition.html#ga04187d48766f865c479d26d2c6225fa9',1,'stm32f407xx_matlab.h']]], - ['eth_5fdmatpdr_5ftpd_5fpos_311',['ETH_DMATPDR_TPD_Pos',['../group___peripheral___registers___bits___definition.html#ga37cc58720fbe96f7130a00e32023189f',1,'stm32f407xx_matlab.h']]], - ['eth_5firqn_312',['ETH_IRQn',['../group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8ad71328dd95461b7c55b568cf25966f6a',1,'stm32f407xx_matlab.h']]], - ['eth_5fmac_5fbase_313',['ETH_MAC_BASE',['../group___peripheral__memory__map.html#ga3cf7005808feb61bff1fee01e50a711a',1,'stm32f407xx_matlab.h']]], - ['eth_5fmaca0hr_5fmaca0h_314',['ETH_MACA0HR_MACA0H',['../group___peripheral___registers___bits___definition.html#ga142dbcbb7da81e8549dde3c239ed8251',1,'stm32f407xx_matlab.h']]], - ['eth_5fmaca0hr_5fmaca0h_5fmsk_315',['ETH_MACA0HR_MACA0H_Msk',['../group___peripheral___registers___bits___definition.html#ga867c6c9c8a1a2c5559f99673debe33a3',1,'stm32f407xx_matlab.h']]], - ['eth_5fmaca0hr_5fmaca0h_5fpos_316',['ETH_MACA0HR_MACA0H_Pos',['../group___peripheral___registers___bits___definition.html#ga21bb827892ec43224afef17af302e1a3',1,'stm32f407xx_matlab.h']]], - ['eth_5fmaca0lr_5fmaca0l_317',['ETH_MACA0LR_MACA0L',['../group___peripheral___registers___bits___definition.html#gaf3ed9dbd9711ee9c19f40c73d8f33be3',1,'stm32f407xx_matlab.h']]], - ['eth_5fmaca0lr_5fmaca0l_5fmsk_318',['ETH_MACA0LR_MACA0L_Msk',['../group___peripheral___registers___bits___definition.html#ga994262dc8bd5b38a213503e3d2e6c398',1,'stm32f407xx_matlab.h']]], - ['eth_5fmaca0lr_5fmaca0l_5fpos_319',['ETH_MACA0LR_MACA0L_Pos',['../group___peripheral___registers___bits___definition.html#ga72f33ca841069471da9ca73b46d40ac5',1,'stm32f407xx_matlab.h']]], - ['eth_5fmaca1hr_5fae_320',['ETH_MACA1HR_AE',['../group___peripheral___registers___bits___definition.html#ga9f88c5ead1109f1e0abac07bcb2e44ea',1,'stm32f407xx_matlab.h']]], - ['eth_5fmaca1hr_5fae_5fmsk_321',['ETH_MACA1HR_AE_Msk',['../group___peripheral___registers___bits___definition.html#ga5ab67262fcf71a730f150aed61e3e173',1,'stm32f407xx_matlab.h']]], - ['eth_5fmaca1hr_5fae_5fpos_322',['ETH_MACA1HR_AE_Pos',['../group___peripheral___registers___bits___definition.html#ga2f3217cb3886e3c977a676a06b912eb2',1,'stm32f407xx_matlab.h']]], - ['eth_5fmaca1hr_5fmaca1h_323',['ETH_MACA1HR_MACA1H',['../group___peripheral___registers___bits___definition.html#gaddd4d059d3d4734c2528ef12cadbd769',1,'stm32f407xx_matlab.h']]], - ['eth_5fmaca1hr_5fmaca1h_5fmsk_324',['ETH_MACA1HR_MACA1H_Msk',['../group___peripheral___registers___bits___definition.html#ga859884136a9b5a2924fa61ecb29d28d7',1,'stm32f407xx_matlab.h']]], - ['eth_5fmaca1hr_5fmaca1h_5fpos_325',['ETH_MACA1HR_MACA1H_Pos',['../group___peripheral___registers___bits___definition.html#gaf00494291a47151e9c4ea357746f757d',1,'stm32f407xx_matlab.h']]], - ['eth_5fmaca1hr_5fmbc_326',['ETH_MACA1HR_MBC',['../group___peripheral___registers___bits___definition.html#ga7bf2fe1242cce62c3fe1cc49ce513b6a',1,'stm32f407xx_matlab.h']]], - ['eth_5fmaca1hr_5fmbc_5fhbits15_5f8_327',['ETH_MACA1HR_MBC_HBits15_8',['../group___peripheral___registers___bits___definition.html#gaf3e731440906539ecb1c52a84df889c5',1,'stm32f407xx_matlab.h']]], - ['eth_5fmaca1hr_5fmbc_5fhbits7_5f0_328',['ETH_MACA1HR_MBC_HBits7_0',['../group___peripheral___registers___bits___definition.html#gac8ebf87cc6584613fea5a49a382b2d67',1,'stm32f407xx_matlab.h']]], - ['eth_5fmaca1hr_5fmbc_5flbits15_5f8_329',['ETH_MACA1HR_MBC_LBits15_8',['../group___peripheral___registers___bits___definition.html#gab3520a54e7e68617539b51885b7bb918',1,'stm32f407xx_matlab.h']]], - ['eth_5fmaca1hr_5fmbc_5flbits23_5f16_330',['ETH_MACA1HR_MBC_LBits23_16',['../group___peripheral___registers___bits___definition.html#ga6d3767ea17fd333409e63262ab5f6878',1,'stm32f407xx_matlab.h']]], - ['eth_5fmaca1hr_5fmbc_5flbits31_5f24_331',['ETH_MACA1HR_MBC_LBits31_24',['../group___peripheral___registers___bits___definition.html#ga7fa211fa742d34dd8e8d2ca2ea5e865a',1,'stm32f407xx_matlab.h']]], - ['eth_5fmaca1hr_5fmbc_5flbits7_5f0_332',['ETH_MACA1HR_MBC_LBits7_0',['../group___peripheral___registers___bits___definition.html#ga3894de2dc133fd5e03e4d4817852adfd',1,'stm32f407xx_matlab.h']]], - ['eth_5fmaca1hr_5fmbc_5fmsk_333',['ETH_MACA1HR_MBC_Msk',['../group___peripheral___registers___bits___definition.html#gaf98e44dbd971404c80536dab4459e295',1,'stm32f407xx_matlab.h']]], - ['eth_5fmaca1hr_5fmbc_5fpos_334',['ETH_MACA1HR_MBC_Pos',['../group___peripheral___registers___bits___definition.html#ga6c4a2a38360a644181c889a97a058791',1,'stm32f407xx_matlab.h']]], - ['eth_5fmaca1hr_5fsa_335',['ETH_MACA1HR_SA',['../group___peripheral___registers___bits___definition.html#gac3840a96465b73115d34360abf3704c5',1,'stm32f407xx_matlab.h']]], - ['eth_5fmaca1hr_5fsa_5fmsk_336',['ETH_MACA1HR_SA_Msk',['../group___peripheral___registers___bits___definition.html#gac076f91767de8a428972303da56427d5',1,'stm32f407xx_matlab.h']]], - ['eth_5fmaca1hr_5fsa_5fpos_337',['ETH_MACA1HR_SA_Pos',['../group___peripheral___registers___bits___definition.html#gaecdc77542da8b8c62da99702324479e1',1,'stm32f407xx_matlab.h']]], - ['eth_5fmaca1lr_5fmaca1l_338',['ETH_MACA1LR_MACA1L',['../group___peripheral___registers___bits___definition.html#gacce742aa0eabc2a8b23ba4f79f18409a',1,'stm32f407xx_matlab.h']]], - ['eth_5fmaca1lr_5fmaca1l_5fmsk_339',['ETH_MACA1LR_MACA1L_Msk',['../group___peripheral___registers___bits___definition.html#ga93090bfada32ec17c3385ab72ec89ebb',1,'stm32f407xx_matlab.h']]], - ['eth_5fmaca1lr_5fmaca1l_5fpos_340',['ETH_MACA1LR_MACA1L_Pos',['../group___peripheral___registers___bits___definition.html#gaa29c12e370323d466187775345ab9d1e',1,'stm32f407xx_matlab.h']]], - ['eth_5fmaca2hr_5fae_341',['ETH_MACA2HR_AE',['../group___peripheral___registers___bits___definition.html#ga5713abb4f70f5514d2d44c44ea17254e',1,'stm32f407xx_matlab.h']]], - ['eth_5fmaca2hr_5fae_5fmsk_342',['ETH_MACA2HR_AE_Msk',['../group___peripheral___registers___bits___definition.html#ga8cdb03f087e227851c3ad964da076672',1,'stm32f407xx_matlab.h']]], - ['eth_5fmaca2hr_5fae_5fpos_343',['ETH_MACA2HR_AE_Pos',['../group___peripheral___registers___bits___definition.html#ga153e9d30ef5f5fd7e8107e36e4a15757',1,'stm32f407xx_matlab.h']]], - ['eth_5fmaca2hr_5fmaca2h_344',['ETH_MACA2HR_MACA2H',['../group___peripheral___registers___bits___definition.html#ga5c73a460038c40e28b27fe0cfcd17cef',1,'stm32f407xx_matlab.h']]], - ['eth_5fmaca2hr_5fmaca2h_5fmsk_345',['ETH_MACA2HR_MACA2H_Msk',['../group___peripheral___registers___bits___definition.html#ga8a378228b4b6bd086aa8931bb2b81326',1,'stm32f407xx_matlab.h']]], - ['eth_5fmaca2hr_5fmaca2h_5fpos_346',['ETH_MACA2HR_MACA2H_Pos',['../group___peripheral___registers___bits___definition.html#ga0a9cabfc6b16557ae778be5010419be9',1,'stm32f407xx_matlab.h']]], - ['eth_5fmaca2hr_5fmbc_347',['ETH_MACA2HR_MBC',['../group___peripheral___registers___bits___definition.html#ga270c0bb939fd71e02a8d221caada1071',1,'stm32f407xx_matlab.h']]], - ['eth_5fmaca2hr_5fmbc_5fhbits15_5f8_348',['ETH_MACA2HR_MBC_HBits15_8',['../group___peripheral___registers___bits___definition.html#ga656070d9cc36501e927908e2f3903332',1,'stm32f407xx_matlab.h']]], - ['eth_5fmaca2hr_5fmbc_5fhbits7_5f0_349',['ETH_MACA2HR_MBC_HBits7_0',['../group___peripheral___registers___bits___definition.html#ga322aa03bccdcb0b2e85119629e95be57',1,'stm32f407xx_matlab.h']]], - ['eth_5fmaca2hr_5fmbc_5flbits15_5f8_350',['ETH_MACA2HR_MBC_LBits15_8',['../group___peripheral___registers___bits___definition.html#ga394acdc62df68dadb1190d4f83f6dbaa',1,'stm32f407xx_matlab.h']]], - ['eth_5fmaca2hr_5fmbc_5flbits23_5f16_351',['ETH_MACA2HR_MBC_LBits23_16',['../group___peripheral___registers___bits___definition.html#ga8cc71bd0499aaa5a76247a6bd6e5e79a',1,'stm32f407xx_matlab.h']]], - ['eth_5fmaca2hr_5fmbc_5flbits31_5f24_352',['ETH_MACA2HR_MBC_LBits31_24',['../group___peripheral___registers___bits___definition.html#ga9519b002d1e0c04b1d5989bf410d24cb',1,'stm32f407xx_matlab.h']]], - ['eth_5fmaca2hr_5fmbc_5flbits7_5f0_353',['ETH_MACA2HR_MBC_LBits7_0',['../group___peripheral___registers___bits___definition.html#gaa87b47b25381694fdcc397cc63ea8810',1,'stm32f407xx_matlab.h']]], - ['eth_5fmaca2hr_5fmbc_5fmsk_354',['ETH_MACA2HR_MBC_Msk',['../group___peripheral___registers___bits___definition.html#gab90f57ac02ce2cf7223f3b0bfd0e7891',1,'stm32f407xx_matlab.h']]], - ['eth_5fmaca2hr_5fmbc_5fpos_355',['ETH_MACA2HR_MBC_Pos',['../group___peripheral___registers___bits___definition.html#ga9b46e39d1c8da3b5d032e57f2fe9c395',1,'stm32f407xx_matlab.h']]], - ['eth_5fmaca2hr_5fsa_356',['ETH_MACA2HR_SA',['../group___peripheral___registers___bits___definition.html#ga8c3f0a2b08321c5441a87b385bfe0c41',1,'stm32f407xx_matlab.h']]], - ['eth_5fmaca2hr_5fsa_5fmsk_357',['ETH_MACA2HR_SA_Msk',['../group___peripheral___registers___bits___definition.html#gade8dbf6a5ba0db18a839b799b9ae951a',1,'stm32f407xx_matlab.h']]], - ['eth_5fmaca2hr_5fsa_5fpos_358',['ETH_MACA2HR_SA_Pos',['../group___peripheral___registers___bits___definition.html#ga303b2c351db0593d5283e7f324cb725c',1,'stm32f407xx_matlab.h']]], - ['eth_5fmaca2lr_5fmaca2l_359',['ETH_MACA2LR_MACA2L',['../group___peripheral___registers___bits___definition.html#ga757e0ceef1c6d529f28c7875ff3e88e7',1,'stm32f407xx_matlab.h']]], - ['eth_5fmaca2lr_5fmaca2l_5fmsk_360',['ETH_MACA2LR_MACA2L_Msk',['../group___peripheral___registers___bits___definition.html#ga41296fc9e2a6a59d5f7c16e94bc17736',1,'stm32f407xx_matlab.h']]], - ['eth_5fmaca2lr_5fmaca2l_5fpos_361',['ETH_MACA2LR_MACA2L_Pos',['../group___peripheral___registers___bits___definition.html#ga84d72f061c5bd14552d066fefc0bf13c',1,'stm32f407xx_matlab.h']]], - ['eth_5fmaca3hr_5fae_362',['ETH_MACA3HR_AE',['../group___peripheral___registers___bits___definition.html#gaf3bb6d5c1237b2c573f22876a62dcaa9',1,'stm32f407xx_matlab.h']]], - ['eth_5fmaca3hr_5fae_5fmsk_363',['ETH_MACA3HR_AE_Msk',['../group___peripheral___registers___bits___definition.html#ga5c36200e79d56aba3c56dc24c475406a',1,'stm32f407xx_matlab.h']]], - ['eth_5fmaca3hr_5fae_5fpos_364',['ETH_MACA3HR_AE_Pos',['../group___peripheral___registers___bits___definition.html#ga19974f597cc028a35be1daec4a1ba531',1,'stm32f407xx_matlab.h']]], - ['eth_5fmaca3hr_5fmaca3h_365',['ETH_MACA3HR_MACA3H',['../group___peripheral___registers___bits___definition.html#ga0b5d9faa67c4cc6d1c42ec26ad99d57b',1,'stm32f407xx_matlab.h']]], - ['eth_5fmaca3hr_5fmaca3h_5fmsk_366',['ETH_MACA3HR_MACA3H_Msk',['../group___peripheral___registers___bits___definition.html#ga2a4c3dd7eb1ea655eb87161f5268de85',1,'stm32f407xx_matlab.h']]], - ['eth_5fmaca3hr_5fmaca3h_5fpos_367',['ETH_MACA3HR_MACA3H_Pos',['../group___peripheral___registers___bits___definition.html#ga8c868df20fcf4144cff7cdaecec1c892',1,'stm32f407xx_matlab.h']]], - ['eth_5fmaca3hr_5fmbc_368',['ETH_MACA3HR_MBC',['../group___peripheral___registers___bits___definition.html#ga64ec855ed04aea21b400ae947b54a353',1,'stm32f407xx_matlab.h']]], - ['eth_5fmaca3hr_5fmbc_5fhbits15_5f8_369',['ETH_MACA3HR_MBC_HBits15_8',['../group___peripheral___registers___bits___definition.html#ga019fe5bc7d94ee1ee4a605e06e777bb5',1,'stm32f407xx_matlab.h']]], - ['eth_5fmaca3hr_5fmbc_5fhbits7_5f0_370',['ETH_MACA3HR_MBC_HBits7_0',['../group___peripheral___registers___bits___definition.html#ga33587cdbe844563e853e3815b63c7c47',1,'stm32f407xx_matlab.h']]], - ['eth_5fmaca3hr_5fmbc_5flbits15_5f8_371',['ETH_MACA3HR_MBC_LBits15_8',['../group___peripheral___registers___bits___definition.html#ga4744ba01934291f07b1b132b82cb1bd4',1,'stm32f407xx_matlab.h']]], - ['eth_5fmaca3hr_5fmbc_5flbits23_5f16_372',['ETH_MACA3HR_MBC_LBits23_16',['../group___peripheral___registers___bits___definition.html#ga6b47f3fddf3dcd39b3af7785c1e5cced',1,'stm32f407xx_matlab.h']]], - ['eth_5fmaca3hr_5fmbc_5flbits31_5f24_373',['ETH_MACA3HR_MBC_LBits31_24',['../group___peripheral___registers___bits___definition.html#gae147613a45eb3d13b84b66158217bb89',1,'stm32f407xx_matlab.h']]], - ['eth_5fmaca3hr_5fmbc_5flbits7_5f0_374',['ETH_MACA3HR_MBC_LBits7_0',['../group___peripheral___registers___bits___definition.html#ga60f2f1ab81a02837ed96e5f92fe96181',1,'stm32f407xx_matlab.h']]], - ['eth_5fmaca3hr_5fmbc_5fmsk_375',['ETH_MACA3HR_MBC_Msk',['../group___peripheral___registers___bits___definition.html#ga0c9fa25a21daaf9673e50a75db9f4193',1,'stm32f407xx_matlab.h']]], - ['eth_5fmaca3hr_5fmbc_5fpos_376',['ETH_MACA3HR_MBC_Pos',['../group___peripheral___registers___bits___definition.html#gadedd5cb92d6134fd4110664083f943f9',1,'stm32f407xx_matlab.h']]], - ['eth_5fmaca3hr_5fsa_377',['ETH_MACA3HR_SA',['../group___peripheral___registers___bits___definition.html#ga54c41346fd61170b413812a19fcac8db',1,'stm32f407xx_matlab.h']]], - ['eth_5fmaca3hr_5fsa_5fmsk_378',['ETH_MACA3HR_SA_Msk',['../group___peripheral___registers___bits___definition.html#ga3b3ed7c73e177513e879d96e42f8fd5b',1,'stm32f407xx_matlab.h']]], - ['eth_5fmaca3hr_5fsa_5fpos_379',['ETH_MACA3HR_SA_Pos',['../group___peripheral___registers___bits___definition.html#ga988fe5da295995ba022cb1a379673ad7',1,'stm32f407xx_matlab.h']]], - ['eth_5fmaca3lr_5fmaca3l_380',['ETH_MACA3LR_MACA3L',['../group___peripheral___registers___bits___definition.html#gaa08b4ccde1b7251ba6317e744b09a95f',1,'stm32f407xx_matlab.h']]], - ['eth_5fmaca3lr_5fmaca3l_5fmsk_381',['ETH_MACA3LR_MACA3L_Msk',['../group___peripheral___registers___bits___definition.html#gada2b7497b892a22692e464256513c9e4',1,'stm32f407xx_matlab.h']]], - ['eth_5fmaca3lr_5fmaca3l_5fpos_382',['ETH_MACA3LR_MACA3L_Pos',['../group___peripheral___registers___bits___definition.html#gaec6beeb51e6198352c03b91615109947',1,'stm32f407xx_matlab.h']]], - ['eth_5fmaccr_5fapcs_383',['ETH_MACCR_APCS',['../group___peripheral___registers___bits___definition.html#ga0b5d2fe7260609d8186a7005f925dc28',1,'stm32f407xx_matlab.h']]], - ['eth_5fmaccr_5fapcs_5fmsk_384',['ETH_MACCR_APCS_Msk',['../group___peripheral___registers___bits___definition.html#ga64b76db821d5aacb94dd0ad98b9343b1',1,'stm32f407xx_matlab.h']]], - ['eth_5fmaccr_5fapcs_5fpos_385',['ETH_MACCR_APCS_Pos',['../group___peripheral___registers___bits___definition.html#gadf11af5805335ea5bf4a581746770169',1,'stm32f407xx_matlab.h']]], - ['eth_5fmaccr_5fbl_386',['ETH_MACCR_BL',['../group___peripheral___registers___bits___definition.html#gaa0fab432a0d01c8c1786b3d48489c0f9',1,'stm32f407xx_matlab.h']]], - ['eth_5fmaccr_5fbl_5f1_387',['ETH_MACCR_BL_1',['../group___peripheral___registers___bits___definition.html#gacf4db303c5f5822875770938f7cfb7c5',1,'stm32f407xx_matlab.h']]], - ['eth_5fmaccr_5fbl_5f10_388',['ETH_MACCR_BL_10',['../group___peripheral___registers___bits___definition.html#ga9bc0bcf13d6a51de76a67299ba40561f',1,'stm32f407xx_matlab.h']]], - ['eth_5fmaccr_5fbl_5f4_389',['ETH_MACCR_BL_4',['../group___peripheral___registers___bits___definition.html#ga6d5f35dc63a68792a4abfaf9d11a2feb',1,'stm32f407xx_matlab.h']]], - ['eth_5fmaccr_5fbl_5f8_390',['ETH_MACCR_BL_8',['../group___peripheral___registers___bits___definition.html#ga135a78ac267e35d598ed17aa776a1505',1,'stm32f407xx_matlab.h']]], - ['eth_5fmaccr_5fbl_5fmsk_391',['ETH_MACCR_BL_Msk',['../group___peripheral___registers___bits___definition.html#ga1ec3ac5f3f2541425180e8a899d3501f',1,'stm32f407xx_matlab.h']]], - ['eth_5fmaccr_5fbl_5fpos_392',['ETH_MACCR_BL_Pos',['../group___peripheral___registers___bits___definition.html#ga14f95db9a825ce4e8f6cd28c5451bad3',1,'stm32f407xx_matlab.h']]], - ['eth_5fmaccr_5fcsd_393',['ETH_MACCR_CSD',['../group___peripheral___registers___bits___definition.html#gad298d344663cc1213716b5981c61682c',1,'stm32f407xx_matlab.h']]], - ['eth_5fmaccr_5fcsd_5fmsk_394',['ETH_MACCR_CSD_Msk',['../group___peripheral___registers___bits___definition.html#gad18e8d3284ce4ec318027d9f3d8ca491',1,'stm32f407xx_matlab.h']]], - ['eth_5fmaccr_5fcsd_5fpos_395',['ETH_MACCR_CSD_Pos',['../group___peripheral___registers___bits___definition.html#ga588e9336435c218354a75fc12f8bf612',1,'stm32f407xx_matlab.h']]], - ['eth_5fmaccr_5fdc_396',['ETH_MACCR_DC',['../group___peripheral___registers___bits___definition.html#ga90347f47e9623d4714e0631b1afbccc9',1,'stm32f407xx_matlab.h']]], - ['eth_5fmaccr_5fdc_5fmsk_397',['ETH_MACCR_DC_Msk',['../group___peripheral___registers___bits___definition.html#ga725e7bba118c5f2780295c555a3ba916',1,'stm32f407xx_matlab.h']]], - ['eth_5fmaccr_5fdc_5fpos_398',['ETH_MACCR_DC_Pos',['../group___peripheral___registers___bits___definition.html#gacec9ce3aee181fbc67675464bace4292',1,'stm32f407xx_matlab.h']]], - ['eth_5fmaccr_5fdm_399',['ETH_MACCR_DM',['../group___peripheral___registers___bits___definition.html#ga83e463b0497de6801773acd7984722b2',1,'stm32f407xx_matlab.h']]], - ['eth_5fmaccr_5fdm_5fmsk_400',['ETH_MACCR_DM_Msk',['../group___peripheral___registers___bits___definition.html#ga36a3d885827efdd8dff930201dfee8cb',1,'stm32f407xx_matlab.h']]], - ['eth_5fmaccr_5fdm_5fpos_401',['ETH_MACCR_DM_Pos',['../group___peripheral___registers___bits___definition.html#gaf3fb4a84c106fe35457d37c5b64c3329',1,'stm32f407xx_matlab.h']]], - ['eth_5fmaccr_5ffes_402',['ETH_MACCR_FES',['../group___peripheral___registers___bits___definition.html#gafaa2d12a706f5c166e1ed620ec53177c',1,'stm32f407xx_matlab.h']]], - ['eth_5fmaccr_5ffes_5fmsk_403',['ETH_MACCR_FES_Msk',['../group___peripheral___registers___bits___definition.html#ga9f5dd4cb0742fd13187a8c200bb1f041',1,'stm32f407xx_matlab.h']]], - ['eth_5fmaccr_5ffes_5fpos_404',['ETH_MACCR_FES_Pos',['../group___peripheral___registers___bits___definition.html#ga6147083b9250f2eb3364b02195fe737c',1,'stm32f407xx_matlab.h']]], - ['eth_5fmaccr_5fifg_405',['ETH_MACCR_IFG',['../group___peripheral___registers___bits___definition.html#ga989c71f66d1361519d2b0586f30b148f',1,'stm32f407xx_matlab.h']]], - ['eth_5fmaccr_5fifg_5f40bit_406',['ETH_MACCR_IFG_40Bit',['../group___peripheral___registers___bits___definition.html#ga1bc414a4c1360538a9ccbea64009d581',1,'stm32f407xx_matlab.h']]], - ['eth_5fmaccr_5fifg_5f48bit_407',['ETH_MACCR_IFG_48Bit',['../group___peripheral___registers___bits___definition.html#ga8984fcb3cf6fb85c26878d9341324d77',1,'stm32f407xx_matlab.h']]], - ['eth_5fmaccr_5fifg_5f56bit_408',['ETH_MACCR_IFG_56Bit',['../group___peripheral___registers___bits___definition.html#gaebea1ff24623d7ba11f9eea98cd5466b',1,'stm32f407xx_matlab.h']]], - ['eth_5fmaccr_5fifg_5f64bit_409',['ETH_MACCR_IFG_64Bit',['../group___peripheral___registers___bits___definition.html#ga75c191358878ffd90ad6a6af336b935b',1,'stm32f407xx_matlab.h']]], - ['eth_5fmaccr_5fifg_5f72bit_410',['ETH_MACCR_IFG_72Bit',['../group___peripheral___registers___bits___definition.html#gab2e77bc6fa5effe78706bfda4a51d1e2',1,'stm32f407xx_matlab.h']]], - ['eth_5fmaccr_5fifg_5f80bit_411',['ETH_MACCR_IFG_80Bit',['../group___peripheral___registers___bits___definition.html#ga56adc3166c71f29d2d30efc6ed3a4369',1,'stm32f407xx_matlab.h']]], - ['eth_5fmaccr_5fifg_5f88bit_412',['ETH_MACCR_IFG_88Bit',['../group___peripheral___registers___bits___definition.html#gacf0f2ad0cd583f00dd2739cbb3dbdeea',1,'stm32f407xx_matlab.h']]], - ['eth_5fmaccr_5fifg_5f96bit_413',['ETH_MACCR_IFG_96Bit',['../group___peripheral___registers___bits___definition.html#ga004e9dab4a5e1ed4f165facca6fd80aa',1,'stm32f407xx_matlab.h']]], - ['eth_5fmaccr_5fifg_5fmsk_414',['ETH_MACCR_IFG_Msk',['../group___peripheral___registers___bits___definition.html#ga0081ebdecc02644f5a0a5304478e2f9c',1,'stm32f407xx_matlab.h']]], - ['eth_5fmaccr_5fifg_5fpos_415',['ETH_MACCR_IFG_Pos',['../group___peripheral___registers___bits___definition.html#ga6ef65cca0d90f5944aefd63db1505323',1,'stm32f407xx_matlab.h']]], - ['eth_5fmaccr_5fipco_416',['ETH_MACCR_IPCO',['../group___peripheral___registers___bits___definition.html#gadbd6f6975a04c0ded0e1a9e98035e802',1,'stm32f407xx_matlab.h']]], - ['eth_5fmaccr_5fipco_5fmsk_417',['ETH_MACCR_IPCO_Msk',['../group___peripheral___registers___bits___definition.html#ga8366318e6b656e2f84664b29cf67d4f5',1,'stm32f407xx_matlab.h']]], - ['eth_5fmaccr_5fipco_5fpos_418',['ETH_MACCR_IPCO_Pos',['../group___peripheral___registers___bits___definition.html#ga2debc54904a0cd2e8075c18b06b04607',1,'stm32f407xx_matlab.h']]], - ['eth_5fmaccr_5fjd_419',['ETH_MACCR_JD',['../group___peripheral___registers___bits___definition.html#ga1ef1243e257142caa99c086b07fa5d42',1,'stm32f407xx_matlab.h']]], - ['eth_5fmaccr_5fjd_5fmsk_420',['ETH_MACCR_JD_Msk',['../group___peripheral___registers___bits___definition.html#gab36b8e9295e605680052d61f262843fc',1,'stm32f407xx_matlab.h']]], - ['eth_5fmaccr_5fjd_5fpos_421',['ETH_MACCR_JD_Pos',['../group___peripheral___registers___bits___definition.html#ga96003f027aa496dc4345472db3b60f10',1,'stm32f407xx_matlab.h']]], - ['eth_5fmaccr_5flm_422',['ETH_MACCR_LM',['../group___peripheral___registers___bits___definition.html#ga38ad823b7d50c85fc620a9a93d250d54',1,'stm32f407xx_matlab.h']]], - ['eth_5fmaccr_5flm_5fmsk_423',['ETH_MACCR_LM_Msk',['../group___peripheral___registers___bits___definition.html#gaf8a68cc960648c12120c8b374bdd8716',1,'stm32f407xx_matlab.h']]], - ['eth_5fmaccr_5flm_5fpos_424',['ETH_MACCR_LM_Pos',['../group___peripheral___registers___bits___definition.html#ga59f9e595778a163299e230ac6fe01b07',1,'stm32f407xx_matlab.h']]], - ['eth_5fmaccr_5frd_425',['ETH_MACCR_RD',['../group___peripheral___registers___bits___definition.html#gad2771077782e2dcac94367e54353696e',1,'stm32f407xx_matlab.h']]], - ['eth_5fmaccr_5frd_5fmsk_426',['ETH_MACCR_RD_Msk',['../group___peripheral___registers___bits___definition.html#gab35d6a69246d8b8e0df616af385338d8',1,'stm32f407xx_matlab.h']]], - ['eth_5fmaccr_5frd_5fpos_427',['ETH_MACCR_RD_Pos',['../group___peripheral___registers___bits___definition.html#gab08db3705923934f19f57878b6aee621',1,'stm32f407xx_matlab.h']]], - ['eth_5fmaccr_5fre_428',['ETH_MACCR_RE',['../group___peripheral___registers___bits___definition.html#ga77984e7a5202bdc300bccc9cc90fad3e',1,'stm32f407xx_matlab.h']]], - ['eth_5fmaccr_5fre_5fmsk_429',['ETH_MACCR_RE_Msk',['../group___peripheral___registers___bits___definition.html#ga074212b9bb2b4d5991e91277fdd6b18a',1,'stm32f407xx_matlab.h']]], - ['eth_5fmaccr_5fre_5fpos_430',['ETH_MACCR_RE_Pos',['../group___peripheral___registers___bits___definition.html#gac8c13b3b7d19a9a11df6ae71c01de129',1,'stm32f407xx_matlab.h']]], - ['eth_5fmaccr_5frod_431',['ETH_MACCR_ROD',['../group___peripheral___registers___bits___definition.html#ga13f0065edda127d3f1fb6e88ca6f465b',1,'stm32f407xx_matlab.h']]], - ['eth_5fmaccr_5frod_5fmsk_432',['ETH_MACCR_ROD_Msk',['../group___peripheral___registers___bits___definition.html#ga7217c59c6e0a4c0fa327e7f5b40a435b',1,'stm32f407xx_matlab.h']]], - ['eth_5fmaccr_5frod_5fpos_433',['ETH_MACCR_ROD_Pos',['../group___peripheral___registers___bits___definition.html#ga4bbbcddaca5d36eea8da9241ece9bc03',1,'stm32f407xx_matlab.h']]], - ['eth_5fmaccr_5fte_434',['ETH_MACCR_TE',['../group___peripheral___registers___bits___definition.html#ga87c3818396ef51cad8be1f4c68fff164',1,'stm32f407xx_matlab.h']]], - ['eth_5fmaccr_5fte_5fmsk_435',['ETH_MACCR_TE_Msk',['../group___peripheral___registers___bits___definition.html#gaddcad0319763dc5cdb282dda26a50634',1,'stm32f407xx_matlab.h']]], - ['eth_5fmaccr_5fte_5fpos_436',['ETH_MACCR_TE_Pos',['../group___peripheral___registers___bits___definition.html#gad47f85fd08360f1244faff9cd913029c',1,'stm32f407xx_matlab.h']]], - ['eth_5fmaccr_5fwd_437',['ETH_MACCR_WD',['../group___peripheral___registers___bits___definition.html#ga6b90fbae827b1368b83cd9b0d9c64cc8',1,'stm32f407xx_matlab.h']]], - ['eth_5fmaccr_5fwd_5fmsk_438',['ETH_MACCR_WD_Msk',['../group___peripheral___registers___bits___definition.html#ga6dbb23089a2b3d19fd5deb5009a527f3',1,'stm32f407xx_matlab.h']]], - ['eth_5fmaccr_5fwd_5fpos_439',['ETH_MACCR_WD_Pos',['../group___peripheral___registers___bits___definition.html#gae59108fa4b2f56d375f7b7b2e7d50e30',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacdbgr_5fmmrpea_440',['ETH_MACDBGR_MMRPEA',['../group___peripheral___registers___bits___definition.html#ga2ea39162c87ae99fc775d7c685f4cad9',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacdbgr_5fmmrpea_5fmsk_441',['ETH_MACDBGR_MMRPEA_Msk',['../group___peripheral___registers___bits___definition.html#ga8e61368122a669649e18e073d92b9523',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacdbgr_5fmmrpea_5fpos_442',['ETH_MACDBGR_MMRPEA_Pos',['../group___peripheral___registers___bits___definition.html#ga30e18ad6efe686ce4182e2f381b136d9',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacdbgr_5fmmtea_443',['ETH_MACDBGR_MMTEA',['../group___peripheral___registers___bits___definition.html#ga351f61d0b865bf9eef1c322a63470b9b',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacdbgr_5fmmtea_5fmsk_444',['ETH_MACDBGR_MMTEA_Msk',['../group___peripheral___registers___bits___definition.html#gaaacb0318306838dab51594d9c70f1317',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacdbgr_5fmmtea_5fpos_445',['ETH_MACDBGR_MMTEA_Pos',['../group___peripheral___registers___bits___definition.html#ga255b74ece40f98dd5d09daadbaaf35a5',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacdbgr_5fmsfrwcs_446',['ETH_MACDBGR_MSFRWCS',['../group___peripheral___registers___bits___definition.html#gaf075cce7b6d8d49b2371c84b978d68c0',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacdbgr_5fmsfrwcs_5f0_447',['ETH_MACDBGR_MSFRWCS_0',['../group___peripheral___registers___bits___definition.html#ga0fb3798487f2a257d688ac435a608341',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacdbgr_5fmsfrwcs_5f1_448',['ETH_MACDBGR_MSFRWCS_1',['../group___peripheral___registers___bits___definition.html#ga4c641484d2e209feeb8767877a275ded',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacdbgr_5fmsfrwcs_5fmsk_449',['ETH_MACDBGR_MSFRWCS_Msk',['../group___peripheral___registers___bits___definition.html#ga52fd76b8f90767f087ec1c667025c8c3',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacdbgr_5fmsfrwcs_5fpos_450',['ETH_MACDBGR_MSFRWCS_Pos',['../group___peripheral___registers___bits___definition.html#ga667ffe9105a73ce0bde2927cf8f3d460',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacdbgr_5fmtfcs_451',['ETH_MACDBGR_MTFCS',['../group___peripheral___registers___bits___definition.html#gaede9295547f715df2272833f1245482a',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacdbgr_5fmtfcs_5fgeneratingpcf_452',['ETH_MACDBGR_MTFCS_GENERATINGPCF',['../group___peripheral___registers___bits___definition.html#gad6e711aa626786701cf5a7be94022d51',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacdbgr_5fmtfcs_5fgeneratingpcf_5fmsk_453',['ETH_MACDBGR_MTFCS_GENERATINGPCF_Msk',['../group___peripheral___registers___bits___definition.html#gad83c11088ad9488ad95df4164d87a6aa',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacdbgr_5fmtfcs_5fgeneratingpcf_5fpos_454',['ETH_MACDBGR_MTFCS_GENERATINGPCF_Pos',['../group___peripheral___registers___bits___definition.html#ga2557c4eac2221f1faab94f9b8cfe00e8',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacdbgr_5fmtfcs_5fidle_455',['ETH_MACDBGR_MTFCS_IDLE',['../group___peripheral___registers___bits___definition.html#gac046bac41daecef700eab3b0b56cffc8',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacdbgr_5fmtfcs_5fmsk_456',['ETH_MACDBGR_MTFCS_Msk',['../group___peripheral___registers___bits___definition.html#gaba7a88ee0e14eac0b53172fb50eb25d5',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacdbgr_5fmtfcs_5fpos_457',['ETH_MACDBGR_MTFCS_Pos',['../group___peripheral___registers___bits___definition.html#gae311faf908813d5e2431be06b785778a',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacdbgr_5fmtfcs_5ftransferring_458',['ETH_MACDBGR_MTFCS_TRANSFERRING',['../group___peripheral___registers___bits___definition.html#ga864ba1fd49a4814383f949cafe684e03',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacdbgr_5fmtfcs_5ftransferring_5fmsk_459',['ETH_MACDBGR_MTFCS_TRANSFERRING_Msk',['../group___peripheral___registers___bits___definition.html#ga256a9d6a729fb24273de7934fda3382a',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacdbgr_5fmtfcs_5ftransferring_5fpos_460',['ETH_MACDBGR_MTFCS_TRANSFERRING_Pos',['../group___peripheral___registers___bits___definition.html#gaacab9c8c877f4eb62417bc729bf9a06f',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacdbgr_5fmtfcs_5fwaiting_461',['ETH_MACDBGR_MTFCS_WAITING',['../group___peripheral___registers___bits___definition.html#ga8b7c3b89c04bd5e78f21fbc80531d93d',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacdbgr_5fmtfcs_5fwaiting_5fmsk_462',['ETH_MACDBGR_MTFCS_WAITING_Msk',['../group___peripheral___registers___bits___definition.html#ga5c76dec4e7bed65b011abe14d172b63b',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacdbgr_5fmtfcs_5fwaiting_5fpos_463',['ETH_MACDBGR_MTFCS_WAITING_Pos',['../group___peripheral___registers___bits___definition.html#ga924c2a45180a5d6a97c57af4472bc6da',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacdbgr_5fmtp_464',['ETH_MACDBGR_MTP',['../group___peripheral___registers___bits___definition.html#ga03abbf9c3ee0c6531fd85e0e83596ca8',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacdbgr_5fmtp_5fmsk_465',['ETH_MACDBGR_MTP_Msk',['../group___peripheral___registers___bits___definition.html#ga680e2f1a81947b367c26cc628bc10259',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacdbgr_5fmtp_5fpos_466',['ETH_MACDBGR_MTP_Pos',['../group___peripheral___registers___bits___definition.html#gad0e5a13ab003041865e72fe3b22a018c',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacdbgr_5frffl_467',['ETH_MACDBGR_RFFL',['../group___peripheral___registers___bits___definition.html#gaeaada3f1e16d6196492ee883729b1bc5',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacdbgr_5frffl_5fabovefct_468',['ETH_MACDBGR_RFFL_ABOVEFCT',['../group___peripheral___registers___bits___definition.html#ga6641e0e8ac06b83bae463bc922f21d11',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacdbgr_5frffl_5fabovefct_5fmsk_469',['ETH_MACDBGR_RFFL_ABOVEFCT_Msk',['../group___peripheral___registers___bits___definition.html#ga10c2064f3b400195c7af25036b061a7a',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacdbgr_5frffl_5fabovefct_5fpos_470',['ETH_MACDBGR_RFFL_ABOVEFCT_Pos',['../group___peripheral___registers___bits___definition.html#gadd0c643a902e127cc756b7fd2f1addc7',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacdbgr_5frffl_5fbelowfct_471',['ETH_MACDBGR_RFFL_BELOWFCT',['../group___peripheral___registers___bits___definition.html#ga2ddf7ce69f167379613a4c7cdcc1e793',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacdbgr_5frffl_5fbelowfct_5fmsk_472',['ETH_MACDBGR_RFFL_BELOWFCT_Msk',['../group___peripheral___registers___bits___definition.html#ga19cdea0cde9945c403c6c06813c9bf62',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacdbgr_5frffl_5fbelowfct_5fpos_473',['ETH_MACDBGR_RFFL_BELOWFCT_Pos',['../group___peripheral___registers___bits___definition.html#ga248a8dded9a74fcbffc47420902925cf',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacdbgr_5frffl_5fempty_474',['ETH_MACDBGR_RFFL_EMPTY',['../group___peripheral___registers___bits___definition.html#gab858b8daec5ad2e262c045e2c356c8da',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacdbgr_5frffl_5ffull_475',['ETH_MACDBGR_RFFL_FULL',['../group___peripheral___registers___bits___definition.html#gafe77114eff677d5aa1a9e9fdff1dd012',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacdbgr_5frffl_5ffull_5fmsk_476',['ETH_MACDBGR_RFFL_FULL_Msk',['../group___peripheral___registers___bits___definition.html#gaf21ee74d35ebd3ab19866e990b939cf7',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacdbgr_5frffl_5ffull_5fpos_477',['ETH_MACDBGR_RFFL_FULL_Pos',['../group___peripheral___registers___bits___definition.html#gaf89706d23f364ef3b84d865245142e81',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacdbgr_5frffl_5fmsk_478',['ETH_MACDBGR_RFFL_Msk',['../group___peripheral___registers___bits___definition.html#ga677c8cbf5dde19bafe80d61eeec6acdf',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacdbgr_5frffl_5fpos_479',['ETH_MACDBGR_RFFL_Pos',['../group___peripheral___registers___bits___definition.html#ga662cdc10d98ff6adaf37c06708632e18',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacdbgr_5frfrcs_480',['ETH_MACDBGR_RFRCS',['../group___peripheral___registers___bits___definition.html#ga71dcc3ae1256f5d497268d17da32365f',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacdbgr_5frfrcs_5fdatareading_481',['ETH_MACDBGR_RFRCS_DATAREADING',['../group___peripheral___registers___bits___definition.html#gaa876e6249677eb886802d0de921586a9',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacdbgr_5frfrcs_5fdatareading_5fmsk_482',['ETH_MACDBGR_RFRCS_DATAREADING_Msk',['../group___peripheral___registers___bits___definition.html#ga7b84a8a7e5d71118ae3cec94160a1e95',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacdbgr_5frfrcs_5fdatareading_5fpos_483',['ETH_MACDBGR_RFRCS_DATAREADING_Pos',['../group___peripheral___registers___bits___definition.html#gac0cf3fc9bd396cc8f571f20d977c36bd',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacdbgr_5frfrcs_5fflushing_484',['ETH_MACDBGR_RFRCS_FLUSHING',['../group___peripheral___registers___bits___definition.html#ga7c6dcca9f806cc4c605e87ff6688002f',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacdbgr_5frfrcs_5fflushing_5fmsk_485',['ETH_MACDBGR_RFRCS_FLUSHING_Msk',['../group___peripheral___registers___bits___definition.html#ga0dabbd91b31f2da515b27e58d3e4b382',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacdbgr_5frfrcs_5fflushing_5fpos_486',['ETH_MACDBGR_RFRCS_FLUSHING_Pos',['../group___peripheral___registers___bits___definition.html#ga7ad0c45c41812a126604ca20edd26ea1',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacdbgr_5frfrcs_5fidle_487',['ETH_MACDBGR_RFRCS_IDLE',['../group___peripheral___registers___bits___definition.html#ga02670bb4130b5700cd7c8a1b83fc5ea7',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacdbgr_5frfrcs_5fmsk_488',['ETH_MACDBGR_RFRCS_Msk',['../group___peripheral___registers___bits___definition.html#gad5bb3df9b84ce49d0cd478ad7c3c7853',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacdbgr_5frfrcs_5fpos_489',['ETH_MACDBGR_RFRCS_Pos',['../group___peripheral___registers___bits___definition.html#gae559873efaadb3aeee1a88c9d57532f2',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacdbgr_5frfrcs_5fstatusreading_490',['ETH_MACDBGR_RFRCS_STATUSREADING',['../group___peripheral___registers___bits___definition.html#gae60cfc823422bbec5008b06da236861e',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacdbgr_5frfrcs_5fstatusreading_5fmsk_491',['ETH_MACDBGR_RFRCS_STATUSREADING_Msk',['../group___peripheral___registers___bits___definition.html#gae2441dce4a78077110e952be1e34afef',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacdbgr_5frfrcs_5fstatusreading_5fpos_492',['ETH_MACDBGR_RFRCS_STATUSREADING_Pos',['../group___peripheral___registers___bits___definition.html#ga2a03f0782ae649ffa10bf09cf6544c21',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacdbgr_5frfwra_493',['ETH_MACDBGR_RFWRA',['../group___peripheral___registers___bits___definition.html#ga80fdd819a347bb13cbd5575fc15d914a',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacdbgr_5frfwra_5fmsk_494',['ETH_MACDBGR_RFWRA_Msk',['../group___peripheral___registers___bits___definition.html#ga65529949f0603e73f75fa2a35890b5a3',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacdbgr_5frfwra_5fpos_495',['ETH_MACDBGR_RFWRA_Pos',['../group___peripheral___registers___bits___definition.html#ga8dd87eed0c5d5ae993d654abb251b63c',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacdbgr_5ftff_496',['ETH_MACDBGR_TFF',['../group___peripheral___registers___bits___definition.html#ga94103a8c53ce5eab030b42165dd6916b',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacdbgr_5ftff_5fmsk_497',['ETH_MACDBGR_TFF_Msk',['../group___peripheral___registers___bits___definition.html#gaf5af5bce543dc0df3a800a2db110bbdc',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacdbgr_5ftff_5fpos_498',['ETH_MACDBGR_TFF_Pos',['../group___peripheral___registers___bits___definition.html#ga27fd32b963677065b181f32e16e04b7b',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacdbgr_5ftfne_499',['ETH_MACDBGR_TFNE',['../group___peripheral___registers___bits___definition.html#gad9dff0698db41111c7c99cb5973003d4',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacdbgr_5ftfne_5fmsk_500',['ETH_MACDBGR_TFNE_Msk',['../group___peripheral___registers___bits___definition.html#ga176073c87c07e195f0b2ca7868b3cde5',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacdbgr_5ftfne_5fpos_501',['ETH_MACDBGR_TFNE_Pos',['../group___peripheral___registers___bits___definition.html#ga67c688152c050956889165352ff65a16',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacdbgr_5ftfrs_502',['ETH_MACDBGR_TFRS',['../group___peripheral___registers___bits___definition.html#ga112165ea108b32a86b135583c29a2386',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacdbgr_5ftfrs_5fidle_503',['ETH_MACDBGR_TFRS_IDLE',['../group___peripheral___registers___bits___definition.html#ga48bc21a580c771ed4ac9b797c0b41d25',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacdbgr_5ftfrs_5fmsk_504',['ETH_MACDBGR_TFRS_Msk',['../group___peripheral___registers___bits___definition.html#ga97cc364a7442339bcbed0ffde5486ef0',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacdbgr_5ftfrs_5fpos_505',['ETH_MACDBGR_TFRS_Pos',['../group___peripheral___registers___bits___definition.html#ga7473c49e7a89cbb1b0e3c9cf67980284',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacdbgr_5ftfrs_5fread_506',['ETH_MACDBGR_TFRS_READ',['../group___peripheral___registers___bits___definition.html#ga520c63ccb534f4fd8740e7ceb254373d',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacdbgr_5ftfrs_5fread_5fmsk_507',['ETH_MACDBGR_TFRS_READ_Msk',['../group___peripheral___registers___bits___definition.html#ga21675a956d16a5aeac36b390b2bceb72',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacdbgr_5ftfrs_5fread_5fpos_508',['ETH_MACDBGR_TFRS_READ_Pos',['../group___peripheral___registers___bits___definition.html#gad9d9294176f211cb62aef1e622cf8052',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacdbgr_5ftfrs_5fwaiting_509',['ETH_MACDBGR_TFRS_WAITING',['../group___peripheral___registers___bits___definition.html#ga4b223d1c05a8e1503daa10e0f27f514d',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacdbgr_5ftfrs_5fwaiting_5fmsk_510',['ETH_MACDBGR_TFRS_WAITING_Msk',['../group___peripheral___registers___bits___definition.html#ga745c2d38c8863ffb583471feb51c5a91',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacdbgr_5ftfrs_5fwaiting_5fpos_511',['ETH_MACDBGR_TFRS_WAITING_Pos',['../group___peripheral___registers___bits___definition.html#ga4b3f3b4224569efda1658e0d8f0468bd',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacdbgr_5ftfrs_5fwriting_512',['ETH_MACDBGR_TFRS_WRITING',['../group___peripheral___registers___bits___definition.html#ga4902aaee652f847dd0494a87189fb275',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacdbgr_5ftfrs_5fwriting_5fmsk_513',['ETH_MACDBGR_TFRS_WRITING_Msk',['../group___peripheral___registers___bits___definition.html#ga6fd97c33d20badcf4ec3cbafda38ddb3',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacdbgr_5ftfrs_5fwriting_5fpos_514',['ETH_MACDBGR_TFRS_WRITING_Pos',['../group___peripheral___registers___bits___definition.html#gaa14782f524bd2b25ed567532e80f4fcf',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacdbgr_5ftfwa_515',['ETH_MACDBGR_TFWA',['../group___peripheral___registers___bits___definition.html#gaae53b57022944c49021787f52ed30117',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacdbgr_5ftfwa_5fmsk_516',['ETH_MACDBGR_TFWA_Msk',['../group___peripheral___registers___bits___definition.html#ga0b4ce9eaa80ad0cf60a5921737520507',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacdbgr_5ftfwa_5fpos_517',['ETH_MACDBGR_TFWA_Pos',['../group___peripheral___registers___bits___definition.html#ga1b16b33e92d14f1a2b12b8a86700fcf6',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacfcr_5ffcbbpa_518',['ETH_MACFCR_FCBBPA',['../group___peripheral___registers___bits___definition.html#ga7dccd98a15d90caf17bcaa6ae13d60a3',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacfcr_5ffcbbpa_5fmsk_519',['ETH_MACFCR_FCBBPA_Msk',['../group___peripheral___registers___bits___definition.html#gabceb72e4e65bfaa290be58922efdb336',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacfcr_5ffcbbpa_5fpos_520',['ETH_MACFCR_FCBBPA_Pos',['../group___peripheral___registers___bits___definition.html#gae98c96a63ef61268f22ba4abec8d811a',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacfcr_5fplt_521',['ETH_MACFCR_PLT',['../group___peripheral___registers___bits___definition.html#gaa299b14f248991ea740c352c2e2ec1e5',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacfcr_5fplt_5fminus144_522',['ETH_MACFCR_PLT_Minus144',['../group___peripheral___registers___bits___definition.html#ga2d71124fba7219f43938d8cc25ba4fad',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacfcr_5fplt_5fminus144_5fmsk_523',['ETH_MACFCR_PLT_Minus144_Msk',['../group___peripheral___registers___bits___definition.html#gad9574c5ecc97413442222dbfcda0b50c',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacfcr_5fplt_5fminus144_5fpos_524',['ETH_MACFCR_PLT_Minus144_Pos',['../group___peripheral___registers___bits___definition.html#gae9824db95c539fb9d35eb4f0c70c78f0',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacfcr_5fplt_5fminus256_525',['ETH_MACFCR_PLT_Minus256',['../group___peripheral___registers___bits___definition.html#gaf55b57c1a06e060afd934e7883a6ebca',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacfcr_5fplt_5fminus256_5fmsk_526',['ETH_MACFCR_PLT_Minus256_Msk',['../group___peripheral___registers___bits___definition.html#ga74132d764aff9d748dcf05fb9b0216ec',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacfcr_5fplt_5fminus256_5fpos_527',['ETH_MACFCR_PLT_Minus256_Pos',['../group___peripheral___registers___bits___definition.html#ga94bf0a9fd09b9e9354a2bf9360bdcd52',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacfcr_5fplt_5fminus28_528',['ETH_MACFCR_PLT_Minus28',['../group___peripheral___registers___bits___definition.html#ga006139afdeadd79e8ead0233a202b3aa',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacfcr_5fplt_5fminus28_5fmsk_529',['ETH_MACFCR_PLT_Minus28_Msk',['../group___peripheral___registers___bits___definition.html#ga43d3c34bc307b8592c4576e2e1f62a78',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacfcr_5fplt_5fminus28_5fpos_530',['ETH_MACFCR_PLT_Minus28_Pos',['../group___peripheral___registers___bits___definition.html#gad0a1efb0a76dd9c1cb2b0cb4534e40d3',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacfcr_5fplt_5fminus4_531',['ETH_MACFCR_PLT_Minus4',['../group___peripheral___registers___bits___definition.html#ga23d3e1992eec79fe65413ab67d3a3850',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacfcr_5fplt_5fmsk_532',['ETH_MACFCR_PLT_Msk',['../group___peripheral___registers___bits___definition.html#gaebd5b76da52c58fd104576b7d2ff7edb',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacfcr_5fplt_5fpos_533',['ETH_MACFCR_PLT_Pos',['../group___peripheral___registers___bits___definition.html#ga0e9b2183e3ab25eaa732bc9cff1c1179',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacfcr_5fpt_534',['ETH_MACFCR_PT',['../group___peripheral___registers___bits___definition.html#ga2b3bc8574eee69d1bf01d5ab91644bbc',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacfcr_5fpt_5fmsk_535',['ETH_MACFCR_PT_Msk',['../group___peripheral___registers___bits___definition.html#ga8ccbe0fdabaaf7f572a77e70af27b949',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacfcr_5fpt_5fpos_536',['ETH_MACFCR_PT_Pos',['../group___peripheral___registers___bits___definition.html#ga5ae35995a0ce92670739ba359d77affc',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacfcr_5frfce_537',['ETH_MACFCR_RFCE',['../group___peripheral___registers___bits___definition.html#gaf2eec52cb081cdba237e1195fe8c324b',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacfcr_5frfce_5fmsk_538',['ETH_MACFCR_RFCE_Msk',['../group___peripheral___registers___bits___definition.html#ga433c5ff49f74755a37c1311ddc075093',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacfcr_5frfce_5fpos_539',['ETH_MACFCR_RFCE_Pos',['../group___peripheral___registers___bits___definition.html#ga0612f97275b019ca840796bdd79d11e2',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacfcr_5ftfce_540',['ETH_MACFCR_TFCE',['../group___peripheral___registers___bits___definition.html#gaa5cd88b7b637bef7a8022270ee02c64a',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacfcr_5ftfce_5fmsk_541',['ETH_MACFCR_TFCE_Msk',['../group___peripheral___registers___bits___definition.html#ga4b5da2d9c9ac891b2d281bf28683ca8d',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacfcr_5ftfce_5fpos_542',['ETH_MACFCR_TFCE_Pos',['../group___peripheral___registers___bits___definition.html#ga89cab918808d77c19851211503d77e13',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacfcr_5fupfd_543',['ETH_MACFCR_UPFD',['../group___peripheral___registers___bits___definition.html#ga50539e6dcdc828a70c91ab0cb0c1c27c',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacfcr_5fupfd_5fmsk_544',['ETH_MACFCR_UPFD_Msk',['../group___peripheral___registers___bits___definition.html#ga80f30740b5201a4a56e2b1a6db8fe48e',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacfcr_5fupfd_5fpos_545',['ETH_MACFCR_UPFD_Pos',['../group___peripheral___registers___bits___definition.html#ga7ff0b3e85c3bf432dd589bdab6e76cde',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacfcr_5fzqpd_546',['ETH_MACFCR_ZQPD',['../group___peripheral___registers___bits___definition.html#gaf34f51c72bc9733694ca11993cc384e1',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacfcr_5fzqpd_5fmsk_547',['ETH_MACFCR_ZQPD_Msk',['../group___peripheral___registers___bits___definition.html#ga2e17d8c6daf50d922b16cff17da9eea6',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacfcr_5fzqpd_5fpos_548',['ETH_MACFCR_ZQPD_Pos',['../group___peripheral___registers___bits___definition.html#gab33dfecfb2d574506516b81d6098bd9f',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacffr_5fbfd_549',['ETH_MACFFR_BFD',['../group___peripheral___registers___bits___definition.html#ga8fea3f3e6b264e362a84675e09f33cbd',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacffr_5fbfd_5fmsk_550',['ETH_MACFFR_BFD_Msk',['../group___peripheral___registers___bits___definition.html#gacb4108d0862a690e04665be0fc04412d',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacffr_5fbfd_5fpos_551',['ETH_MACFFR_BFD_Pos',['../group___peripheral___registers___bits___definition.html#gaac8a275e8b823431da6aa47d36271ce5',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacffr_5fdaif_552',['ETH_MACFFR_DAIF',['../group___peripheral___registers___bits___definition.html#ga7f50c885917d6df63e6250a530a9ce0c',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacffr_5fdaif_5fmsk_553',['ETH_MACFFR_DAIF_Msk',['../group___peripheral___registers___bits___definition.html#ga3c15d55d7f391f42bd8751d76da28480',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacffr_5fdaif_5fpos_554',['ETH_MACFFR_DAIF_Pos',['../group___peripheral___registers___bits___definition.html#gab5a60d5a987a14e474d8782af855e6f5',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacffr_5fhm_555',['ETH_MACFFR_HM',['../group___peripheral___registers___bits___definition.html#gaaab1e7a61949844d578d7580b9d2c143',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacffr_5fhm_5fmsk_556',['ETH_MACFFR_HM_Msk',['../group___peripheral___registers___bits___definition.html#gab3c33afcbb8d2ae59624915dc1bd2620',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacffr_5fhm_5fpos_557',['ETH_MACFFR_HM_Pos',['../group___peripheral___registers___bits___definition.html#ga0cdf71d283afa6f77ce261fe5e197b92',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacffr_5fhpf_558',['ETH_MACFFR_HPF',['../group___peripheral___registers___bits___definition.html#ga8b902b5561e392e47ce5d66275902e29',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacffr_5fhpf_5fmsk_559',['ETH_MACFFR_HPF_Msk',['../group___peripheral___registers___bits___definition.html#ga7cb1611ef661179353862262e5685c53',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacffr_5fhpf_5fpos_560',['ETH_MACFFR_HPF_Pos',['../group___peripheral___registers___bits___definition.html#ga3f40208cefa46427f9038e48add7d195',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacffr_5fhu_561',['ETH_MACFFR_HU',['../group___peripheral___registers___bits___definition.html#ga6d925e8aa55a6b07772f86abce601529',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacffr_5fhu_5fmsk_562',['ETH_MACFFR_HU_Msk',['../group___peripheral___registers___bits___definition.html#ga9d738065b86ca7845927a39e9b06846a',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacffr_5fhu_5fpos_563',['ETH_MACFFR_HU_Pos',['../group___peripheral___registers___bits___definition.html#ga4087aca0085083cb8f5ce7a5842f42dc',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacffr_5fpam_564',['ETH_MACFFR_PAM',['../group___peripheral___registers___bits___definition.html#gaafaa7da9e50e9ecf39bdc614c01bc22e',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacffr_5fpam_5fmsk_565',['ETH_MACFFR_PAM_Msk',['../group___peripheral___registers___bits___definition.html#ga118b021e83c7e4ba113c17eca935e538',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacffr_5fpam_5fpos_566',['ETH_MACFFR_PAM_Pos',['../group___peripheral___registers___bits___definition.html#gaa2a5d3a1ce969272150c55c2a0f66143',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacffr_5fpcf_567',['ETH_MACFFR_PCF',['../group___peripheral___registers___bits___definition.html#ga25724ed070e5948cb5541d890d2af603',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacffr_5fpcf_5fblockall_568',['ETH_MACFFR_PCF_BlockAll',['../group___peripheral___registers___bits___definition.html#ga9bcec681af42037508574944fe68d6ff',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacffr_5fpcf_5fblockall_5fmsk_569',['ETH_MACFFR_PCF_BlockAll_Msk',['../group___peripheral___registers___bits___definition.html#ga5382075fb7e487b0c2a1a97f0c1d0276',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacffr_5fpcf_5fblockall_5fpos_570',['ETH_MACFFR_PCF_BlockAll_Pos',['../group___peripheral___registers___bits___definition.html#gafae24adcc21beedcf4d3668b07d9211d',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacffr_5fpcf_5fforwardall_571',['ETH_MACFFR_PCF_ForwardAll',['../group___peripheral___registers___bits___definition.html#gaf694466716e26c52452e21ce2a76f2fe',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacffr_5fpcf_5fforwardall_5fmsk_572',['ETH_MACFFR_PCF_ForwardAll_Msk',['../group___peripheral___registers___bits___definition.html#ga600b088ad4e2326651b1b8d066a85a0c',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacffr_5fpcf_5fforwardall_5fpos_573',['ETH_MACFFR_PCF_ForwardAll_Pos',['../group___peripheral___registers___bits___definition.html#ga9495c05d01a26d63e6c87461d5440410',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacffr_5fpcf_5fforwardpassedaddrfilter_574',['ETH_MACFFR_PCF_ForwardPassedAddrFilter',['../group___peripheral___registers___bits___definition.html#gaa3e83e62d864be50e58455719d6df217',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacffr_5fpcf_5fforwardpassedaddrfilter_5fmsk_575',['ETH_MACFFR_PCF_ForwardPassedAddrFilter_Msk',['../group___peripheral___registers___bits___definition.html#ga85f6303d1d492b59bb26034343e3a4df',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacffr_5fpcf_5fforwardpassedaddrfilter_5fpos_576',['ETH_MACFFR_PCF_ForwardPassedAddrFilter_Pos',['../group___peripheral___registers___bits___definition.html#gae90264da6a4c411fc2de7ed84c21de1b',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacffr_5fpcf_5fmsk_577',['ETH_MACFFR_PCF_Msk',['../group___peripheral___registers___bits___definition.html#ga066564941ff14e4ee4110870be454835',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacffr_5fpcf_5fpos_578',['ETH_MACFFR_PCF_Pos',['../group___peripheral___registers___bits___definition.html#gaf59b0fd52b7f31dd5fa99ed3e0db1f24',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacffr_5fpm_579',['ETH_MACFFR_PM',['../group___peripheral___registers___bits___definition.html#ga168f5e4a3eb11474c65396d75c07e086',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacffr_5fpm_5fmsk_580',['ETH_MACFFR_PM_Msk',['../group___peripheral___registers___bits___definition.html#ga46fc57cc116b06aab750055588f841de',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacffr_5fpm_5fpos_581',['ETH_MACFFR_PM_Pos',['../group___peripheral___registers___bits___definition.html#gab3bf7fe779fc85379362777f881c8a2c',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacffr_5fra_582',['ETH_MACFFR_RA',['../group___peripheral___registers___bits___definition.html#ga7970ce2fd938029f0a58cf668a82a0fb',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacffr_5fra_5fmsk_583',['ETH_MACFFR_RA_Msk',['../group___peripheral___registers___bits___definition.html#ga9a98d8a880edf71d2b6fbf245adcbe4b',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacffr_5fra_5fpos_584',['ETH_MACFFR_RA_Pos',['../group___peripheral___registers___bits___definition.html#gaaaefa92c0f1afda53c779ae046f1bc8e',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacffr_5fsaf_585',['ETH_MACFFR_SAF',['../group___peripheral___registers___bits___definition.html#ga1e710eda13cca42c8da46d5d37f34552',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacffr_5fsaf_5fmsk_586',['ETH_MACFFR_SAF_Msk',['../group___peripheral___registers___bits___definition.html#ga3aad930295c276453e51c416902b52cc',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacffr_5fsaf_5fpos_587',['ETH_MACFFR_SAF_Pos',['../group___peripheral___registers___bits___definition.html#gafa74c10f8950aa00a4ecab37d9fecac9',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacffr_5fsaif_588',['ETH_MACFFR_SAIF',['../group___peripheral___registers___bits___definition.html#gaaa351de2818df9599ce6b3378ca31f87',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacffr_5fsaif_5fmsk_589',['ETH_MACFFR_SAIF_Msk',['../group___peripheral___registers___bits___definition.html#gabfa7482e8b8e0d949875ed2e94f3b5f7',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacffr_5fsaif_5fpos_590',['ETH_MACFFR_SAIF_Pos',['../group___peripheral___registers___bits___definition.html#ga848f235f8e37e0293fc51aaa8b8b642e',1,'stm32f407xx_matlab.h']]], - ['eth_5fmachthr_5fhth_591',['ETH_MACHTHR_HTH',['../group___peripheral___registers___bits___definition.html#gaee61bc9033449996ae9f8f701b3bae23',1,'stm32f407xx_matlab.h']]], - ['eth_5fmachthr_5fhth_5fmsk_592',['ETH_MACHTHR_HTH_Msk',['../group___peripheral___registers___bits___definition.html#ga18191f472ac5fce293cc159e03ecf323',1,'stm32f407xx_matlab.h']]], - ['eth_5fmachthr_5fhth_5fpos_593',['ETH_MACHTHR_HTH_Pos',['../group___peripheral___registers___bits___definition.html#gaef7a817f06b2aafafe6ff3210a3c41af',1,'stm32f407xx_matlab.h']]], - ['eth_5fmachtlr_5fhtl_594',['ETH_MACHTLR_HTL',['../group___peripheral___registers___bits___definition.html#gac90cb3090f29ee9e5e7d935e8a3f2340',1,'stm32f407xx_matlab.h']]], - ['eth_5fmachtlr_5fhtl_5fmsk_595',['ETH_MACHTLR_HTL_Msk',['../group___peripheral___registers___bits___definition.html#ga263c1c48202e6c9c8ce639ef13a8ed85',1,'stm32f407xx_matlab.h']]], - ['eth_5fmachtlr_5fhtl_5fpos_596',['ETH_MACHTLR_HTL_Pos',['../group___peripheral___registers___bits___definition.html#ga1d7f015b0b97de99d91eee7ab01e5d5f',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacimr_5fpmtim_597',['ETH_MACIMR_PMTIM',['../group___peripheral___registers___bits___definition.html#gaf2cdb4ba6c97aba3e82e8192ebddcb5f',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacimr_5fpmtim_5fmsk_598',['ETH_MACIMR_PMTIM_Msk',['../group___peripheral___registers___bits___definition.html#ga5de068ed7fd3905c55b6e2cca8324e25',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacimr_5fpmtim_5fpos_599',['ETH_MACIMR_PMTIM_Pos',['../group___peripheral___registers___bits___definition.html#gadd408f2d5725c50c92eeedadc12b5b0e',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacimr_5ftstim_600',['ETH_MACIMR_TSTIM',['../group___peripheral___registers___bits___definition.html#ga8f17c13903c30bc301c7897b93a16a24',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacimr_5ftstim_5fmsk_601',['ETH_MACIMR_TSTIM_Msk',['../group___peripheral___registers___bits___definition.html#ga2092019773b2c66261249da4c9eced6b',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacimr_5ftstim_5fpos_602',['ETH_MACIMR_TSTIM_Pos',['../group___peripheral___registers___bits___definition.html#gaaff7e97a761e2557458f09c24e91d507',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacmiiar_5fcr_603',['ETH_MACMIIAR_CR',['../group___peripheral___registers___bits___definition.html#ga0747e464ca8bb685ee34d28eb2677c40',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacmiiar_5fcr_5fdiv102_604',['ETH_MACMIIAR_CR_Div102',['../group___peripheral___registers___bits___definition.html#ga372d485677cd2e3a995dab470abe66b8',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacmiiar_5fcr_5fdiv102_5fmsk_605',['ETH_MACMIIAR_CR_Div102_Msk',['../group___peripheral___registers___bits___definition.html#ga56cbb5a10b42335d5355aab44552c33e',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacmiiar_5fcr_5fdiv102_5fpos_606',['ETH_MACMIIAR_CR_Div102_Pos',['../group___peripheral___registers___bits___definition.html#gab8b402724d0798147654bb6a1193146e',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacmiiar_5fcr_5fdiv16_607',['ETH_MACMIIAR_CR_Div16',['../group___peripheral___registers___bits___definition.html#ga49474ccdc05637adbc870989373c6535',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacmiiar_5fcr_5fdiv16_5fmsk_608',['ETH_MACMIIAR_CR_Div16_Msk',['../group___peripheral___registers___bits___definition.html#ga9eab0313c19320fe59b933c3bd355b15',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacmiiar_5fcr_5fdiv16_5fpos_609',['ETH_MACMIIAR_CR_Div16_Pos',['../group___peripheral___registers___bits___definition.html#gad97d20a7f5815f99bcb920d3be101deb',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacmiiar_5fcr_5fdiv26_610',['ETH_MACMIIAR_CR_Div26',['../group___peripheral___registers___bits___definition.html#ga69a9da5dbeb77d96a729afc82d4f246d',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacmiiar_5fcr_5fdiv26_5fmsk_611',['ETH_MACMIIAR_CR_Div26_Msk',['../group___peripheral___registers___bits___definition.html#ga9a42460a599738bc6fe1acfa835e61c1',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacmiiar_5fcr_5fdiv26_5fpos_612',['ETH_MACMIIAR_CR_Div26_Pos',['../group___peripheral___registers___bits___definition.html#ga1425435b4fac9a8f965e73d490d9144a',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacmiiar_5fcr_5fdiv42_613',['ETH_MACMIIAR_CR_Div42',['../group___peripheral___registers___bits___definition.html#ga1fc1c108e8e7faa35839b3f72b5570d7',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacmiiar_5fcr_5fdiv62_614',['ETH_MACMIIAR_CR_Div62',['../group___peripheral___registers___bits___definition.html#ga0002142eea07988f854915782bd691c9',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacmiiar_5fcr_5fdiv62_5fmsk_615',['ETH_MACMIIAR_CR_Div62_Msk',['../group___peripheral___registers___bits___definition.html#ga04311c7087462f41231e89b064c61015',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacmiiar_5fcr_5fdiv62_5fpos_616',['ETH_MACMIIAR_CR_Div62_Pos',['../group___peripheral___registers___bits___definition.html#gad42d271e9f8b028f4b77f9c6214f4b41',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacmiiar_5fcr_5fmsk_617',['ETH_MACMIIAR_CR_Msk',['../group___peripheral___registers___bits___definition.html#ga2c7f3d710de7056d937f76f6f8329b83',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacmiiar_5fcr_5fpos_618',['ETH_MACMIIAR_CR_Pos',['../group___peripheral___registers___bits___definition.html#ga9498fb73edbb94c29ed6ccd963deef4e',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacmiiar_5fmb_619',['ETH_MACMIIAR_MB',['../group___peripheral___registers___bits___definition.html#ga4e3bd36fdbb97a3ec5b541997bf952aa',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacmiiar_5fmb_5fmsk_620',['ETH_MACMIIAR_MB_Msk',['../group___peripheral___registers___bits___definition.html#ga0973869be6711854cdbd8922973cad1f',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacmiiar_5fmb_5fpos_621',['ETH_MACMIIAR_MB_Pos',['../group___peripheral___registers___bits___definition.html#ga0bb3ef8fa6db10f02a9c54bc8d321fdd',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacmiiar_5fmr_622',['ETH_MACMIIAR_MR',['../group___peripheral___registers___bits___definition.html#gaa2ab5db007b55dca29e98ba3b31f7e66',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacmiiar_5fmr_5fmsk_623',['ETH_MACMIIAR_MR_Msk',['../group___peripheral___registers___bits___definition.html#gacfed7f5d1d0cb6f84b6442a3afc24496',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacmiiar_5fmr_5fpos_624',['ETH_MACMIIAR_MR_Pos',['../group___peripheral___registers___bits___definition.html#ga50e38f04aa760a4f72b6d012cfb34f71',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacmiiar_5fmw_625',['ETH_MACMIIAR_MW',['../group___peripheral___registers___bits___definition.html#gaffdb940b35822107a5959cdd1ab06482',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacmiiar_5fmw_5fmsk_626',['ETH_MACMIIAR_MW_Msk',['../group___peripheral___registers___bits___definition.html#ga6a13e637f5ae98bda497300e3f65f859',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacmiiar_5fmw_5fpos_627',['ETH_MACMIIAR_MW_Pos',['../group___peripheral___registers___bits___definition.html#gad0697f8d40c21c9b0c3ad91652ab0be4',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacmiiar_5fpa_628',['ETH_MACMIIAR_PA',['../group___peripheral___registers___bits___definition.html#ga712f44a77db4edfaf961e469153e34a4',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacmiiar_5fpa_5fmsk_629',['ETH_MACMIIAR_PA_Msk',['../group___peripheral___registers___bits___definition.html#ga036280a2fcae9747caca79a59f15dbc7',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacmiiar_5fpa_5fpos_630',['ETH_MACMIIAR_PA_Pos',['../group___peripheral___registers___bits___definition.html#gacf67cfdb4230e5d14ee041303582b91d',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacmiidr_5fmd_631',['ETH_MACMIIDR_MD',['../group___peripheral___registers___bits___definition.html#ga0c1226bcd1fc955b69191cd84c1ffe6e',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacmiidr_5fmd_5fmsk_632',['ETH_MACMIIDR_MD_Msk',['../group___peripheral___registers___bits___definition.html#ga553476638dac48c385faf4fcfef738a5',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacmiidr_5fmd_5fpos_633',['ETH_MACMIIDR_MD_Pos',['../group___peripheral___registers___bits___definition.html#ga0ce09ce27fe279dba841d64e3da3824a',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacpmtcsr_5fgu_634',['ETH_MACPMTCSR_GU',['../group___peripheral___registers___bits___definition.html#ga3c2d01faf67db27fb0b2cfeaf94242b4',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacpmtcsr_5fgu_5fmsk_635',['ETH_MACPMTCSR_GU_Msk',['../group___peripheral___registers___bits___definition.html#ga2f845ccfd867098d3ec25775040a5c8f',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacpmtcsr_5fgu_5fpos_636',['ETH_MACPMTCSR_GU_Pos',['../group___peripheral___registers___bits___definition.html#ga7877c7a6a9ed93454098e79a9a2a6281',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacpmtcsr_5fmpe_637',['ETH_MACPMTCSR_MPE',['../group___peripheral___registers___bits___definition.html#ga81540e67436a755a7692b32a33871f63',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacpmtcsr_5fmpe_5fmsk_638',['ETH_MACPMTCSR_MPE_Msk',['../group___peripheral___registers___bits___definition.html#ga71fdad55986e5e2b672ea1de7feb542c',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacpmtcsr_5fmpe_5fpos_639',['ETH_MACPMTCSR_MPE_Pos',['../group___peripheral___registers___bits___definition.html#gab2df8ebbf70fa09790c85774e1f5e8e0',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacpmtcsr_5fmpr_640',['ETH_MACPMTCSR_MPR',['../group___peripheral___registers___bits___definition.html#gab855f00737fb7f828752e1353c3a1031',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacpmtcsr_5fmpr_5fmsk_641',['ETH_MACPMTCSR_MPR_Msk',['../group___peripheral___registers___bits___definition.html#gae312b7c783a541e4dc026eef480398dd',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacpmtcsr_5fmpr_5fpos_642',['ETH_MACPMTCSR_MPR_Pos',['../group___peripheral___registers___bits___definition.html#gadf1514e6ea9fdddbbb6ce396bee1855a',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacpmtcsr_5fpd_643',['ETH_MACPMTCSR_PD',['../group___peripheral___registers___bits___definition.html#gab454be372dc141b6e515c4389cd18a12',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacpmtcsr_5fpd_5fmsk_644',['ETH_MACPMTCSR_PD_Msk',['../group___peripheral___registers___bits___definition.html#gaeaa6826d4d3fd55295dadbc3c3c73873',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacpmtcsr_5fpd_5fpos_645',['ETH_MACPMTCSR_PD_Pos',['../group___peripheral___registers___bits___definition.html#ga0e7bfb3f7e9212baa158705c26c44498',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacpmtcsr_5fwfe_646',['ETH_MACPMTCSR_WFE',['../group___peripheral___registers___bits___definition.html#ga998f1f5665f94008e39dfabb489faf8e',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacpmtcsr_5fwfe_5fmsk_647',['ETH_MACPMTCSR_WFE_Msk',['../group___peripheral___registers___bits___definition.html#ga4898617eb625181689fb6fbeace04705',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacpmtcsr_5fwfe_5fpos_648',['ETH_MACPMTCSR_WFE_Pos',['../group___peripheral___registers___bits___definition.html#ga23adb9148c3a9603d070458e5744df8a',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacpmtcsr_5fwffrpr_649',['ETH_MACPMTCSR_WFFRPR',['../group___peripheral___registers___bits___definition.html#gaeaa7046c581aa1b663c819352930cdd8',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacpmtcsr_5fwffrpr_5fmsk_650',['ETH_MACPMTCSR_WFFRPR_Msk',['../group___peripheral___registers___bits___definition.html#ga6fae91e3c9a395769622d32cff6427b3',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacpmtcsr_5fwffrpr_5fpos_651',['ETH_MACPMTCSR_WFFRPR_Pos',['../group___peripheral___registers___bits___definition.html#gabb526c7632b5374dce52fa2beb80a038',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacpmtcsr_5fwfr_652',['ETH_MACPMTCSR_WFR',['../group___peripheral___registers___bits___definition.html#ga597abfcc1408cb51980fa7a594a6cf30',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacpmtcsr_5fwfr_5fmsk_653',['ETH_MACPMTCSR_WFR_Msk',['../group___peripheral___registers___bits___definition.html#ga832d4cc3d0951c965e6f515125842bc4',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacpmtcsr_5fwfr_5fpos_654',['ETH_MACPMTCSR_WFR_Pos',['../group___peripheral___registers___bits___definition.html#gadfbe013f1b1f93c7274e072c837709b1',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacrwuffr_5fd_655',['ETH_MACRWUFFR_D',['../group___peripheral___registers___bits___definition.html#gaae49a607f4dc4ba71c695b3aa2fc0968',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacrwuffr_5fd_5fmsk_656',['ETH_MACRWUFFR_D_Msk',['../group___peripheral___registers___bits___definition.html#gad54a741a972e56cb46f569b953895bc5',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacrwuffr_5fd_5fpos_657',['ETH_MACRWUFFR_D_Pos',['../group___peripheral___registers___bits___definition.html#ga25fbbd599df79ba574b9915e17c91990',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacsr_5fmmcs_658',['ETH_MACSR_MMCS',['../group___peripheral___registers___bits___definition.html#ga764dd9b736867f6c5b590c7ca49017c2',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacsr_5fmmcs_5fmsk_659',['ETH_MACSR_MMCS_Msk',['../group___peripheral___registers___bits___definition.html#ga0e9a4734bc3540aa6d658c928a15634c',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacsr_5fmmcs_5fpos_660',['ETH_MACSR_MMCS_Pos',['../group___peripheral___registers___bits___definition.html#ga6836cf875c27333b0358be060c931c9e',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacsr_5fmmcts_661',['ETH_MACSR_MMCTS',['../group___peripheral___registers___bits___definition.html#ga0f628abfb1f1076cd89ac76a373d48d6',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacsr_5fmmcts_5fmsk_662',['ETH_MACSR_MMCTS_Msk',['../group___peripheral___registers___bits___definition.html#gabce1cd290247069cb65dd4d96d0fb638',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacsr_5fmmcts_5fpos_663',['ETH_MACSR_MMCTS_Pos',['../group___peripheral___registers___bits___definition.html#gaf8b2cfde92f9bb04b084ea2af687689d',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacsr_5fmmmcrs_664',['ETH_MACSR_MMMCRS',['../group___peripheral___registers___bits___definition.html#gaf9faeaa8069b56260ffc8ed2daa06fcd',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacsr_5fmmmcrs_5fmsk_665',['ETH_MACSR_MMMCRS_Msk',['../group___peripheral___registers___bits___definition.html#ga06bed909940fa2ea61c81f38c0209262',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacsr_5fmmmcrs_5fpos_666',['ETH_MACSR_MMMCRS_Pos',['../group___peripheral___registers___bits___definition.html#ga3e33ef451e773236892e9635f0aa7498',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacsr_5fpmts_667',['ETH_MACSR_PMTS',['../group___peripheral___registers___bits___definition.html#gaee99dd08ad3581436f53b7f22452dcb9',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacsr_5fpmts_5fmsk_668',['ETH_MACSR_PMTS_Msk',['../group___peripheral___registers___bits___definition.html#ga279ac5f84e4f33e20f11d5bdbcf21cc2',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacsr_5fpmts_5fpos_669',['ETH_MACSR_PMTS_Pos',['../group___peripheral___registers___bits___definition.html#ga7c4e8dc8e8dad60de5b659a72ca7fe74',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacsr_5ftsts_670',['ETH_MACSR_TSTS',['../group___peripheral___registers___bits___definition.html#gac5e4af1a52a19f5b2d8f3ce74dd5c85e',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacsr_5ftsts_5fmsk_671',['ETH_MACSR_TSTS_Msk',['../group___peripheral___registers___bits___definition.html#gaa7a53b96de3d0f7dc394e745bafcc899',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacsr_5ftsts_5fpos_672',['ETH_MACSR_TSTS_Pos',['../group___peripheral___registers___bits___definition.html#ga812de501f25e360962652a2a17b65e52',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacvlantr_5fvlantc_673',['ETH_MACVLANTR_VLANTC',['../group___peripheral___registers___bits___definition.html#gabd45480752cd22efecf0d7465bf49500',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacvlantr_5fvlantc_5fmsk_674',['ETH_MACVLANTR_VLANTC_Msk',['../group___peripheral___registers___bits___definition.html#ga74a0075909956532506d7a507c059ea7',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacvlantr_5fvlantc_5fpos_675',['ETH_MACVLANTR_VLANTC_Pos',['../group___peripheral___registers___bits___definition.html#ga425510877d0af2d2dca1daba3d77e4d9',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacvlantr_5fvlanti_676',['ETH_MACVLANTR_VLANTI',['../group___peripheral___registers___bits___definition.html#ga50874dc921fd523d84621a337aebc53d',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacvlantr_5fvlanti_5fmsk_677',['ETH_MACVLANTR_VLANTI_Msk',['../group___peripheral___registers___bits___definition.html#ga2d9e35eaf745fa9f80be9a7a722031a7',1,'stm32f407xx_matlab.h']]], - ['eth_5fmacvlantr_5fvlanti_5fpos_678',['ETH_MACVLANTR_VLANTI_Pos',['../group___peripheral___registers___bits___definition.html#gac2584a4fa262f72e82d506a3c49c00ef',1,'stm32f407xx_matlab.h']]], - ['eth_5fmmc_5fbase_679',['ETH_MMC_BASE',['../group___peripheral__memory__map.html#ga4946f2b3b03f7998343ac1778fbcf725',1,'stm32f407xx_matlab.h']]], - ['eth_5fmmccr_5fcr_680',['ETH_MMCCR_CR',['../group___peripheral___registers___bits___definition.html#ga7cb520c80fc0b2f00304bb7f8f7c5d4e',1,'stm32f407xx_matlab.h']]], - ['eth_5fmmccr_5fcr_5fmsk_681',['ETH_MMCCR_CR_Msk',['../group___peripheral___registers___bits___definition.html#ga36dc300b94cd6c761f4fb2105c306203',1,'stm32f407xx_matlab.h']]], - ['eth_5fmmccr_5fcr_5fpos_682',['ETH_MMCCR_CR_Pos',['../group___peripheral___registers___bits___definition.html#ga43cace7bf67560967d43822c7f2fa730',1,'stm32f407xx_matlab.h']]], - ['eth_5fmmccr_5fcsr_683',['ETH_MMCCR_CSR',['../group___peripheral___registers___bits___definition.html#ga948b685211ced94ef5d4b8d2c94df78a',1,'stm32f407xx_matlab.h']]], - ['eth_5fmmccr_5fcsr_5fmsk_684',['ETH_MMCCR_CSR_Msk',['../group___peripheral___registers___bits___definition.html#ga9f27d8db71e31940104b534eb8e10ca5',1,'stm32f407xx_matlab.h']]], - ['eth_5fmmccr_5fcsr_5fpos_685',['ETH_MMCCR_CSR_Pos',['../group___peripheral___registers___bits___definition.html#gad5f177ef83413fc7f8b139d2e61a195b',1,'stm32f407xx_matlab.h']]], - ['eth_5fmmccr_5fmcf_686',['ETH_MMCCR_MCF',['../group___peripheral___registers___bits___definition.html#ga17ab5fbe6c5189b3f98095f9adb1eeeb',1,'stm32f407xx_matlab.h']]], - ['eth_5fmmccr_5fmcf_5fmsk_687',['ETH_MMCCR_MCF_Msk',['../group___peripheral___registers___bits___definition.html#ga2e4246e3804f51c0f04a91e42ee6f6b1',1,'stm32f407xx_matlab.h']]], - ['eth_5fmmccr_5fmcf_5fpos_688',['ETH_MMCCR_MCF_Pos',['../group___peripheral___registers___bits___definition.html#ga1e66af70554c0813685e282d1bb9c4d5',1,'stm32f407xx_matlab.h']]], - ['eth_5fmmccr_5fmcfhp_689',['ETH_MMCCR_MCFHP',['../group___peripheral___registers___bits___definition.html#ga0eb309947d400951235c17953254fbf8',1,'stm32f407xx_matlab.h']]], - ['eth_5fmmccr_5fmcfhp_5fmsk_690',['ETH_MMCCR_MCFHP_Msk',['../group___peripheral___registers___bits___definition.html#ga7ed0579e3320b27f2fbc0c55159d7552',1,'stm32f407xx_matlab.h']]], - ['eth_5fmmccr_5fmcfhp_5fpos_691',['ETH_MMCCR_MCFHP_Pos',['../group___peripheral___registers___bits___definition.html#ga54d376c32875a39afa0492c2506b4e45',1,'stm32f407xx_matlab.h']]], - ['eth_5fmmccr_5fmcp_692',['ETH_MMCCR_MCP',['../group___peripheral___registers___bits___definition.html#ga2a6eeda6ffcafe7d8ba531ccaa3abf90',1,'stm32f407xx_matlab.h']]], - ['eth_5fmmccr_5fmcp_5fmsk_693',['ETH_MMCCR_MCP_Msk',['../group___peripheral___registers___bits___definition.html#gaf04f6b5deb3a53b8b506162772765171',1,'stm32f407xx_matlab.h']]], - ['eth_5fmmccr_5fmcp_5fpos_694',['ETH_MMCCR_MCP_Pos',['../group___peripheral___registers___bits___definition.html#ga17d60ddf79fe7ab501bcf68012f7b7ec',1,'stm32f407xx_matlab.h']]], - ['eth_5fmmccr_5fror_695',['ETH_MMCCR_ROR',['../group___peripheral___registers___bits___definition.html#ga243ae6b3acbbd295be6f76a84657a48d',1,'stm32f407xx_matlab.h']]], - ['eth_5fmmccr_5fror_5fmsk_696',['ETH_MMCCR_ROR_Msk',['../group___peripheral___registers___bits___definition.html#gaeb19c7101d5986ae5582acf37c2fa730',1,'stm32f407xx_matlab.h']]], - ['eth_5fmmccr_5fror_5fpos_697',['ETH_MMCCR_ROR_Pos',['../group___peripheral___registers___bits___definition.html#ga0ba16f3d8066423ef675d53633c3bf7f',1,'stm32f407xx_matlab.h']]], - ['eth_5fmmcrfaecr_5frfaec_698',['ETH_MMCRFAECR_RFAEC',['../group___peripheral___registers___bits___definition.html#gac52a70effea67d543da0842e323d2123',1,'stm32f407xx_matlab.h']]], - ['eth_5fmmcrfaecr_5frfaec_5fmsk_699',['ETH_MMCRFAECR_RFAEC_Msk',['../group___peripheral___registers___bits___definition.html#ga88b5da27b7870336e6dc92e75fbaf7bc',1,'stm32f407xx_matlab.h']]], - ['eth_5fmmcrfaecr_5frfaec_5fpos_700',['ETH_MMCRFAECR_RFAEC_Pos',['../group___peripheral___registers___bits___definition.html#ga9e4a1a9a81806b92f26c999479b882f7',1,'stm32f407xx_matlab.h']]], - ['eth_5fmmcrfcecr_5frfcec_701',['ETH_MMCRFCECR_RFCEC',['../group___peripheral___registers___bits___definition.html#ga8ed4e2c7449a522ecbc811252ba1f12b',1,'stm32f407xx_matlab.h']]], - ['eth_5fmmcrfcecr_5frfcec_5fmsk_702',['ETH_MMCRFCECR_RFCEC_Msk',['../group___peripheral___registers___bits___definition.html#gacfc0fdeab6719a464423e984ee5d3f96',1,'stm32f407xx_matlab.h']]], - ['eth_5fmmcrfcecr_5frfcec_5fpos_703',['ETH_MMCRFCECR_RFCEC_Pos',['../group___peripheral___registers___bits___definition.html#ga1deb0536d536852ede5d1ae0e6710164',1,'stm32f407xx_matlab.h']]], - ['eth_5fmmcrgufcr_5frgufc_704',['ETH_MMCRGUFCR_RGUFC',['../group___peripheral___registers___bits___definition.html#ga2dd42857738b46f748bc6a9109ab0f9e',1,'stm32f407xx_matlab.h']]], - ['eth_5fmmcrgufcr_5frgufc_5fmsk_705',['ETH_MMCRGUFCR_RGUFC_Msk',['../group___peripheral___registers___bits___definition.html#ga3587339b8bbd30eeff94ee495a7fdbe5',1,'stm32f407xx_matlab.h']]], - ['eth_5fmmcrgufcr_5frgufc_5fpos_706',['ETH_MMCRGUFCR_RGUFC_Pos',['../group___peripheral___registers___bits___definition.html#ga1cc3de8b52de82433d96f3621af5e9d6',1,'stm32f407xx_matlab.h']]], - ['eth_5fmmcrimr_5frfaem_707',['ETH_MMCRIMR_RFAEM',['../group___peripheral___registers___bits___definition.html#ga3c763ea4da19192ab30828971579400c',1,'stm32f407xx_matlab.h']]], - ['eth_5fmmcrimr_5frfaem_5fmsk_708',['ETH_MMCRIMR_RFAEM_Msk',['../group___peripheral___registers___bits___definition.html#gae5a6a3b036b82adac210651815b69cb0',1,'stm32f407xx_matlab.h']]], - ['eth_5fmmcrimr_5frfaem_5fpos_709',['ETH_MMCRIMR_RFAEM_Pos',['../group___peripheral___registers___bits___definition.html#ga60b9afd54fab9bfc9df42907c63bd685',1,'stm32f407xx_matlab.h']]], - ['eth_5fmmcrimr_5frfcem_710',['ETH_MMCRIMR_RFCEM',['../group___peripheral___registers___bits___definition.html#gad3eb72a19c5a4bd34a9ec2c624bd8a8c',1,'stm32f407xx_matlab.h']]], - ['eth_5fmmcrimr_5frfcem_5fmsk_711',['ETH_MMCRIMR_RFCEM_Msk',['../group___peripheral___registers___bits___definition.html#ga89a2ad8a6b0429d309799de95538e83f',1,'stm32f407xx_matlab.h']]], - ['eth_5fmmcrimr_5frfcem_5fpos_712',['ETH_MMCRIMR_RFCEM_Pos',['../group___peripheral___registers___bits___definition.html#ga50fbd3537b29ce431a76f1606791183d',1,'stm32f407xx_matlab.h']]], - ['eth_5fmmcrimr_5frgufm_713',['ETH_MMCRIMR_RGUFM',['../group___peripheral___registers___bits___definition.html#ga873a3b1c0a7756647be8455ea6bea8df',1,'stm32f407xx_matlab.h']]], - ['eth_5fmmcrimr_5frgufm_5fmsk_714',['ETH_MMCRIMR_RGUFM_Msk',['../group___peripheral___registers___bits___definition.html#ga470c1e9e33a19b7da3110acd5e0d9254',1,'stm32f407xx_matlab.h']]], - ['eth_5fmmcrimr_5frgufm_5fpos_715',['ETH_MMCRIMR_RGUFM_Pos',['../group___peripheral___registers___bits___definition.html#ga828d9869b1337d57b50a82873a8c8702',1,'stm32f407xx_matlab.h']]], - ['eth_5fmmcrir_5frfaes_716',['ETH_MMCRIR_RFAES',['../group___peripheral___registers___bits___definition.html#ga7d3859ff0eb6fff48fb98919fe72da15',1,'stm32f407xx_matlab.h']]], - ['eth_5fmmcrir_5frfaes_5fmsk_717',['ETH_MMCRIR_RFAES_Msk',['../group___peripheral___registers___bits___definition.html#ga9456fe951f40d50ade33d8a0221d1a6c',1,'stm32f407xx_matlab.h']]], - ['eth_5fmmcrir_5frfaes_5fpos_718',['ETH_MMCRIR_RFAES_Pos',['../group___peripheral___registers___bits___definition.html#gabea46fc5d1c9b634047e5b6a56171d58',1,'stm32f407xx_matlab.h']]], - ['eth_5fmmcrir_5frfces_719',['ETH_MMCRIR_RFCES',['../group___peripheral___registers___bits___definition.html#gac74e35d76820f3c2b0eb743f26023792',1,'stm32f407xx_matlab.h']]], - ['eth_5fmmcrir_5frfces_5fmsk_720',['ETH_MMCRIR_RFCES_Msk',['../group___peripheral___registers___bits___definition.html#ga707393c1886b72fdfed379967212a36c',1,'stm32f407xx_matlab.h']]], - ['eth_5fmmcrir_5frfces_5fpos_721',['ETH_MMCRIR_RFCES_Pos',['../group___peripheral___registers___bits___definition.html#ga8d23ef057bd9e8cdb9ed25bffca057b6',1,'stm32f407xx_matlab.h']]], - ['eth_5fmmcrir_5frgufs_722',['ETH_MMCRIR_RGUFS',['../group___peripheral___registers___bits___definition.html#gaa4b78bde6602ca062513389b8bf43e17',1,'stm32f407xx_matlab.h']]], - ['eth_5fmmcrir_5frgufs_5fmsk_723',['ETH_MMCRIR_RGUFS_Msk',['../group___peripheral___registers___bits___definition.html#gaf9dc1a19f41c18602c71bd10a99d70b8',1,'stm32f407xx_matlab.h']]], - ['eth_5fmmcrir_5frgufs_5fpos_724',['ETH_MMCRIR_RGUFS_Pos',['../group___peripheral___registers___bits___definition.html#gaa86865c319fd4a4bdc7f612169251a25',1,'stm32f407xx_matlab.h']]], - ['eth_5fmmctgfcr_5ftgfc_725',['ETH_MMCTGFCR_TGFC',['../group___peripheral___registers___bits___definition.html#ga68b659b400b12fd5c539e24bc115dff2',1,'stm32f407xx_matlab.h']]], - ['eth_5fmmctgfcr_5ftgfc_5fmsk_726',['ETH_MMCTGFCR_TGFC_Msk',['../group___peripheral___registers___bits___definition.html#ga5fdcd7783b8ea9e2c46c8b7d89a39a47',1,'stm32f407xx_matlab.h']]], - ['eth_5fmmctgfcr_5ftgfc_5fpos_727',['ETH_MMCTGFCR_TGFC_Pos',['../group___peripheral___registers___bits___definition.html#ga7cd5d71ebd3cafd488e7eba99fcfaa3c',1,'stm32f407xx_matlab.h']]], - ['eth_5fmmctgfmsccr_5ftgfmscc_728',['ETH_MMCTGFMSCCR_TGFMSCC',['../group___peripheral___registers___bits___definition.html#gad4a8b771ec947fe2b944108f72e64fbf',1,'stm32f407xx_matlab.h']]], - ['eth_5fmmctgfmsccr_5ftgfmscc_5fmsk_729',['ETH_MMCTGFMSCCR_TGFMSCC_Msk',['../group___peripheral___registers___bits___definition.html#gaedefca665609c9e6646ee60e8e91a0f9',1,'stm32f407xx_matlab.h']]], - ['eth_5fmmctgfmsccr_5ftgfmscc_5fpos_730',['ETH_MMCTGFMSCCR_TGFMSCC_Pos',['../group___peripheral___registers___bits___definition.html#gaf3b542ab35eb425c4878c828b365771d',1,'stm32f407xx_matlab.h']]], - ['eth_5fmmctgfsccr_5ftgfscc_731',['ETH_MMCTGFSCCR_TGFSCC',['../group___peripheral___registers___bits___definition.html#ga784008b2facbc9cab1982e0382057d1c',1,'stm32f407xx_matlab.h']]], - ['eth_5fmmctgfsccr_5ftgfscc_5fmsk_732',['ETH_MMCTGFSCCR_TGFSCC_Msk',['../group___peripheral___registers___bits___definition.html#gac88648ccd808f151b1fc5c72083e4583',1,'stm32f407xx_matlab.h']]], - ['eth_5fmmctgfsccr_5ftgfscc_5fpos_733',['ETH_MMCTGFSCCR_TGFSCC_Pos',['../group___peripheral___registers___bits___definition.html#gaf0a86aabaf7c4a86f0609e67dfc2de72',1,'stm32f407xx_matlab.h']]], - ['eth_5fmmctimr_5ftgfm_734',['ETH_MMCTIMR_TGFM',['../group___peripheral___registers___bits___definition.html#gae67e69315d2e64d3f4c9b7e65aacf8be',1,'stm32f407xx_matlab.h']]], - ['eth_5fmmctimr_5ftgfm_5fmsk_735',['ETH_MMCTIMR_TGFM_Msk',['../group___peripheral___registers___bits___definition.html#ga65ecd1dd64ba1588e1d83d9896f9e1f0',1,'stm32f407xx_matlab.h']]], - ['eth_5fmmctimr_5ftgfm_5fpos_736',['ETH_MMCTIMR_TGFM_Pos',['../group___peripheral___registers___bits___definition.html#gaa1600c79485a47fa57888479428b8b72',1,'stm32f407xx_matlab.h']]], - ['eth_5fmmctimr_5ftgfmscm_737',['ETH_MMCTIMR_TGFMSCM',['../group___peripheral___registers___bits___definition.html#ga20b6f12c07d34bcc014eaa31c6719486',1,'stm32f407xx_matlab.h']]], - ['eth_5fmmctimr_5ftgfmscm_5fmsk_738',['ETH_MMCTIMR_TGFMSCM_Msk',['../group___peripheral___registers___bits___definition.html#gaba449564725083891a9fc504321614cf',1,'stm32f407xx_matlab.h']]], - ['eth_5fmmctimr_5ftgfmscm_5fpos_739',['ETH_MMCTIMR_TGFMSCM_Pos',['../group___peripheral___registers___bits___definition.html#ga383cc44ef2b8c2cb5cc9a7393a40ea6a',1,'stm32f407xx_matlab.h']]], - ['eth_5fmmctimr_5ftgfscm_740',['ETH_MMCTIMR_TGFSCM',['../group___peripheral___registers___bits___definition.html#ga2f41666a525c61be9c88f3d54632ce34',1,'stm32f407xx_matlab.h']]], - ['eth_5fmmctimr_5ftgfscm_5fmsk_741',['ETH_MMCTIMR_TGFSCM_Msk',['../group___peripheral___registers___bits___definition.html#gaec67763632bc2229fca4167c7db268ce',1,'stm32f407xx_matlab.h']]], - ['eth_5fmmctimr_5ftgfscm_5fpos_742',['ETH_MMCTIMR_TGFSCM_Pos',['../group___peripheral___registers___bits___definition.html#gafcd2ae936752f3c3f6e303ecdbd6ce77',1,'stm32f407xx_matlab.h']]], - ['eth_5fmmctir_5ftgfmscs_743',['ETH_MMCTIR_TGFMSCS',['../group___peripheral___registers___bits___definition.html#ga796d834a29d0fc6fdc1908ba6db487c3',1,'stm32f407xx_matlab.h']]], - ['eth_5fmmctir_5ftgfmscs_5fmsk_744',['ETH_MMCTIR_TGFMSCS_Msk',['../group___peripheral___registers___bits___definition.html#gabd5834302f75346a6ce686d331b66cf2',1,'stm32f407xx_matlab.h']]], - ['eth_5fmmctir_5ftgfmscs_5fpos_745',['ETH_MMCTIR_TGFMSCS_Pos',['../group___peripheral___registers___bits___definition.html#gac4524f1174601c98399967db0321779f',1,'stm32f407xx_matlab.h']]], - ['eth_5fmmctir_5ftgfs_746',['ETH_MMCTIR_TGFS',['../group___peripheral___registers___bits___definition.html#gab5d5dcc69902946befc317ea5719a34c',1,'stm32f407xx_matlab.h']]], - ['eth_5fmmctir_5ftgfs_5fmsk_747',['ETH_MMCTIR_TGFS_Msk',['../group___peripheral___registers___bits___definition.html#ga5361ed811dd1673f55cc0ca20096022a',1,'stm32f407xx_matlab.h']]], - ['eth_5fmmctir_5ftgfs_5fpos_748',['ETH_MMCTIR_TGFS_Pos',['../group___peripheral___registers___bits___definition.html#ga04a0d740674b1ef700a33c222fcedef6',1,'stm32f407xx_matlab.h']]], - ['eth_5fmmctir_5ftgfscs_749',['ETH_MMCTIR_TGFSCS',['../group___peripheral___registers___bits___definition.html#gabe8e920b9e135d3e3ba61e0db758ff19',1,'stm32f407xx_matlab.h']]], - ['eth_5fmmctir_5ftgfscs_5fmsk_750',['ETH_MMCTIR_TGFSCS_Msk',['../group___peripheral___registers___bits___definition.html#ga1c0fa21e33672cbf0d9e4404aa236663',1,'stm32f407xx_matlab.h']]], - ['eth_5fmmctir_5ftgfscs_5fpos_751',['ETH_MMCTIR_TGFSCS_Pos',['../group___peripheral___registers___bits___definition.html#gae7ac440ef59fd4dae474a77cff93b992',1,'stm32f407xx_matlab.h']]], - ['eth_5fptp_5fbase_752',['ETH_PTP_BASE',['../group___peripheral__memory__map.html#gaa0f60b922aeb7275c785cbaa8f94ecf0',1,'stm32f407xx_matlab.h']]], - ['eth_5fptpssir_5fstssi_753',['ETH_PTPSSIR_STSSI',['../group___peripheral___registers___bits___definition.html#gab51d59cd679f65a179fe5e271b63a22c',1,'stm32f407xx_matlab.h']]], - ['eth_5fptpssir_5fstssi_5fmsk_754',['ETH_PTPSSIR_STSSI_Msk',['../group___peripheral___registers___bits___definition.html#ga0fef6f1da60d4682780fd1ef4cf3435f',1,'stm32f407xx_matlab.h']]], - ['eth_5fptpssir_5fstssi_5fpos_755',['ETH_PTPSSIR_STSSI_Pos',['../group___peripheral___registers___bits___definition.html#gac3855f0e2e250856a890efb4a29b68c6',1,'stm32f407xx_matlab.h']]], - ['eth_5fptptsar_5ftsa_756',['ETH_PTPTSAR_TSA',['../group___peripheral___registers___bits___definition.html#gab944b9f1ceff57bb31beb689a19537c4',1,'stm32f407xx_matlab.h']]], - ['eth_5fptptsar_5ftsa_5fmsk_757',['ETH_PTPTSAR_TSA_Msk',['../group___peripheral___registers___bits___definition.html#ga3f67b7a220cf80fec5ea4c9cd642fef3',1,'stm32f407xx_matlab.h']]], - ['eth_5fptptsar_5ftsa_5fpos_758',['ETH_PTPTSAR_TSA_Pos',['../group___peripheral___registers___bits___definition.html#ga142199a59a370ae94ef43febe1f0e27b',1,'stm32f407xx_matlab.h']]], - ['eth_5fptptscr_5ftsaru_759',['ETH_PTPTSCR_TSARU',['../group___peripheral___registers___bits___definition.html#ga19406b465c944a3e465a8077cbfbf39e',1,'stm32f407xx_matlab.h']]], - ['eth_5fptptscr_5ftsaru_5fmsk_760',['ETH_PTPTSCR_TSARU_Msk',['../group___peripheral___registers___bits___definition.html#gae38f60d94f4dd3d08f4ef813911adf79',1,'stm32f407xx_matlab.h']]], - ['eth_5fptptscr_5ftsaru_5fpos_761',['ETH_PTPTSCR_TSARU_Pos',['../group___peripheral___registers___bits___definition.html#ga764ac2859fe42ac27c1c462c9889e1f1',1,'stm32f407xx_matlab.h']]], - ['eth_5fptptscr_5ftscnt_762',['ETH_PTPTSCR_TSCNT',['../group___peripheral___registers___bits___definition.html#gaf9d47a61f30e11b514ef0840f3a0fb91',1,'stm32f407xx_matlab.h']]], - ['eth_5fptptscr_5ftscnt_5fmsk_763',['ETH_PTPTSCR_TSCNT_Msk',['../group___peripheral___registers___bits___definition.html#gae6eb6cba0cbd040d7d39085c0056a7fc',1,'stm32f407xx_matlab.h']]], - ['eth_5fptptscr_5ftscnt_5fpos_764',['ETH_PTPTSCR_TSCNT_Pos',['../group___peripheral___registers___bits___definition.html#ga8dee0d9d9d59df164911cfedd38f832e',1,'stm32f407xx_matlab.h']]], - ['eth_5fptptscr_5ftse_765',['ETH_PTPTSCR_TSE',['../group___peripheral___registers___bits___definition.html#ga9c1129b1d368bdef0c5c07d9acf8edd7',1,'stm32f407xx_matlab.h']]], - ['eth_5fptptscr_5ftse_5fmsk_766',['ETH_PTPTSCR_TSE_Msk',['../group___peripheral___registers___bits___definition.html#gaa354e48ec338c1aeb40ec642b98b49e5',1,'stm32f407xx_matlab.h']]], - ['eth_5fptptscr_5ftse_5fpos_767',['ETH_PTPTSCR_TSE_Pos',['../group___peripheral___registers___bits___definition.html#ga228aab4066179e8e0a8bb44d5a2205aa',1,'stm32f407xx_matlab.h']]], - ['eth_5fptptscr_5ftsfcu_768',['ETH_PTPTSCR_TSFCU',['../group___peripheral___registers___bits___definition.html#ga9e58e22d5668ebf118f67df5eb13e834',1,'stm32f407xx_matlab.h']]], - ['eth_5fptptscr_5ftsfcu_5fmsk_769',['ETH_PTPTSCR_TSFCU_Msk',['../group___peripheral___registers___bits___definition.html#ga29d78884eed541cedaf8b46b6914899d',1,'stm32f407xx_matlab.h']]], - ['eth_5fptptscr_5ftsfcu_5fpos_770',['ETH_PTPTSCR_TSFCU_Pos',['../group___peripheral___registers___bits___definition.html#ga428f2c4ef53f655e679732f632c6f490',1,'stm32f407xx_matlab.h']]], - ['eth_5fptptscr_5ftsite_771',['ETH_PTPTSCR_TSITE',['../group___peripheral___registers___bits___definition.html#ga44670d6793da45549fb7ea38c3523783',1,'stm32f407xx_matlab.h']]], - ['eth_5fptptscr_5ftsite_5fmsk_772',['ETH_PTPTSCR_TSITE_Msk',['../group___peripheral___registers___bits___definition.html#ga3731fcd0a402ff13734764182b29c99a',1,'stm32f407xx_matlab.h']]], - ['eth_5fptptscr_5ftsite_5fpos_773',['ETH_PTPTSCR_TSITE_Pos',['../group___peripheral___registers___bits___definition.html#gad9464fe8bfc44323aee790eb0768f6ab',1,'stm32f407xx_matlab.h']]], - ['eth_5fptptscr_5ftspffmae_774',['ETH_PTPTSCR_TSPFFMAE',['../group___peripheral___registers___bits___definition.html#ga5e755bd16b5f77c0e04690acf9f422a2',1,'stm32f407xx_matlab.h']]], - ['eth_5fptptscr_5ftspffmae_5fmsk_775',['ETH_PTPTSCR_TSPFFMAE_Msk',['../group___peripheral___registers___bits___definition.html#ga07ddca2b8b3a89a0e844b12b45c0a7a1',1,'stm32f407xx_matlab.h']]], - ['eth_5fptptscr_5ftspffmae_5fpos_776',['ETH_PTPTSCR_TSPFFMAE_Pos',['../group___peripheral___registers___bits___definition.html#ga8547e484fdbe7554b28c4dbbfda55984',1,'stm32f407xx_matlab.h']]], - ['eth_5fptptscr_5ftsptppsv2e_777',['ETH_PTPTSCR_TSPTPPSV2E',['../group___peripheral___registers___bits___definition.html#gaf06151b1fa7d4437bb664964de1ee12a',1,'stm32f407xx_matlab.h']]], - ['eth_5fptptscr_5ftsptppsv2e_5fmsk_778',['ETH_PTPTSCR_TSPTPPSV2E_Msk',['../group___peripheral___registers___bits___definition.html#gadbc463e7a55bfd585e2f87095164ed42',1,'stm32f407xx_matlab.h']]], - ['eth_5fptptscr_5ftsptppsv2e_5fpos_779',['ETH_PTPTSCR_TSPTPPSV2E_Pos',['../group___peripheral___registers___bits___definition.html#gae466858afa76b1a56f3da3221352ae5e',1,'stm32f407xx_matlab.h']]], - ['eth_5fptptscr_5ftssarfe_780',['ETH_PTPTSCR_TSSARFE',['../group___peripheral___registers___bits___definition.html#ga553bc2c98222a09ce2a60fb0c098763e',1,'stm32f407xx_matlab.h']]], - ['eth_5fptptscr_5ftssarfe_5fmsk_781',['ETH_PTPTSCR_TSSARFE_Msk',['../group___peripheral___registers___bits___definition.html#gaa6e14c1d9f9e1b4882f0c4380f18a4a8',1,'stm32f407xx_matlab.h']]], - ['eth_5fptptscr_5ftssarfe_5fpos_782',['ETH_PTPTSCR_TSSARFE_Pos',['../group___peripheral___registers___bits___definition.html#gaf5eaf028640c2b06b2debb0f1b16124b',1,'stm32f407xx_matlab.h']]], - ['eth_5fptptscr_5ftsseme_783',['ETH_PTPTSCR_TSSEME',['../group___peripheral___registers___bits___definition.html#ga6cc8829467d2678bd11d90ec20049cbd',1,'stm32f407xx_matlab.h']]], - ['eth_5fptptscr_5ftsseme_5fmsk_784',['ETH_PTPTSCR_TSSEME_Msk',['../group___peripheral___registers___bits___definition.html#gad299e7a85e91581bee8f41d8badd1210',1,'stm32f407xx_matlab.h']]], - ['eth_5fptptscr_5ftsseme_5fpos_785',['ETH_PTPTSCR_TSSEME_Pos',['../group___peripheral___registers___bits___definition.html#ga18e9717d99801dd4c06219ef74516ab9',1,'stm32f407xx_matlab.h']]], - ['eth_5fptptscr_5ftssipv4fe_786',['ETH_PTPTSCR_TSSIPV4FE',['../group___peripheral___registers___bits___definition.html#ga5e1ed6b41f9d8c686c294846b4a2fde0',1,'stm32f407xx_matlab.h']]], - ['eth_5fptptscr_5ftssipv4fe_5fmsk_787',['ETH_PTPTSCR_TSSIPV4FE_Msk',['../group___peripheral___registers___bits___definition.html#ga7584fce8033ccf0a76c1d0571b1a42f7',1,'stm32f407xx_matlab.h']]], - ['eth_5fptptscr_5ftssipv4fe_5fpos_788',['ETH_PTPTSCR_TSSIPV4FE_Pos',['../group___peripheral___registers___bits___definition.html#ga52099e8ee00c7b8d08568e768af469d8',1,'stm32f407xx_matlab.h']]], - ['eth_5fptptscr_5ftssipv6fe_789',['ETH_PTPTSCR_TSSIPV6FE',['../group___peripheral___registers___bits___definition.html#gadc3f015ae5624edbc57fd6482c9096b6',1,'stm32f407xx_matlab.h']]], - ['eth_5fptptscr_5ftssipv6fe_5fmsk_790',['ETH_PTPTSCR_TSSIPV6FE_Msk',['../group___peripheral___registers___bits___definition.html#ga5a1e31f374562426154d02d8e694d0cd',1,'stm32f407xx_matlab.h']]], - ['eth_5fptptscr_5ftssipv6fe_5fpos_791',['ETH_PTPTSCR_TSSIPV6FE_Pos',['../group___peripheral___registers___bits___definition.html#ga9861508d171c1c049ef136ab4c90f4ff',1,'stm32f407xx_matlab.h']]], - ['eth_5fptptscr_5ftssmrme_792',['ETH_PTPTSCR_TSSMRME',['../group___peripheral___registers___bits___definition.html#gabfd289fdf804f8ab2240abd611fd36ee',1,'stm32f407xx_matlab.h']]], - ['eth_5fptptscr_5ftssmrme_5fmsk_793',['ETH_PTPTSCR_TSSMRME_Msk',['../group___peripheral___registers___bits___definition.html#ga2ea5dd63a69ace6876b589be79c520bc',1,'stm32f407xx_matlab.h']]], - ['eth_5fptptscr_5ftssmrme_5fpos_794',['ETH_PTPTSCR_TSSMRME_Pos',['../group___peripheral___registers___bits___definition.html#ga9c64bd7449eae554c810dceb920c8f85',1,'stm32f407xx_matlab.h']]], - ['eth_5fptptscr_5ftssptpoefe_795',['ETH_PTPTSCR_TSSPTPOEFE',['../group___peripheral___registers___bits___definition.html#ga615bc0bc378392c6a508bb9e28826b72',1,'stm32f407xx_matlab.h']]], - ['eth_5fptptscr_5ftssptpoefe_5fmsk_796',['ETH_PTPTSCR_TSSPTPOEFE_Msk',['../group___peripheral___registers___bits___definition.html#ga3b84221fe479a965fcc665a05e0d2190',1,'stm32f407xx_matlab.h']]], - ['eth_5fptptscr_5ftssptpoefe_5fpos_797',['ETH_PTPTSCR_TSSPTPOEFE_Pos',['../group___peripheral___registers___bits___definition.html#ga34a9bf48d463d0bd45d5c133654c6319',1,'stm32f407xx_matlab.h']]], - ['eth_5fptptscr_5ftsssr_798',['ETH_PTPTSCR_TSSSR',['../group___peripheral___registers___bits___definition.html#gad653b859283fac4ed67f027d8af17dec',1,'stm32f407xx_matlab.h']]], - ['eth_5fptptscr_5ftsssr_5fmsk_799',['ETH_PTPTSCR_TSSSR_Msk',['../group___peripheral___registers___bits___definition.html#ga0770634e7a6a880384072a2974859d6e',1,'stm32f407xx_matlab.h']]], - ['eth_5fptptscr_5ftsssr_5fpos_800',['ETH_PTPTSCR_TSSSR_Pos',['../group___peripheral___registers___bits___definition.html#ga7efbf85f1370fa44e7655bd0c4c6f830',1,'stm32f407xx_matlab.h']]], - ['eth_5fptptscr_5ftssti_801',['ETH_PTPTSCR_TSSTI',['../group___peripheral___registers___bits___definition.html#gad484f7a6e6df6b3f2131d3bfb3dba856',1,'stm32f407xx_matlab.h']]], - ['eth_5fptptscr_5ftssti_5fmsk_802',['ETH_PTPTSCR_TSSTI_Msk',['../group___peripheral___registers___bits___definition.html#ga88c53dbf12851d2e912b3748de382452',1,'stm32f407xx_matlab.h']]], - ['eth_5fptptscr_5ftssti_5fpos_803',['ETH_PTPTSCR_TSSTI_Pos',['../group___peripheral___registers___bits___definition.html#ga6405b2ac005034ee0ea0642f19efad4b',1,'stm32f407xx_matlab.h']]], - ['eth_5fptptscr_5ftsstu_804',['ETH_PTPTSCR_TSSTU',['../group___peripheral___registers___bits___definition.html#ga589a3a200c3f68543f556432cdb98075',1,'stm32f407xx_matlab.h']]], - ['eth_5fptptscr_5ftsstu_5fmsk_805',['ETH_PTPTSCR_TSSTU_Msk',['../group___peripheral___registers___bits___definition.html#ga8573e45d80d88e5c90149584b3692421',1,'stm32f407xx_matlab.h']]], - ['eth_5fptptscr_5ftsstu_5fpos_806',['ETH_PTPTSCR_TSSTU_Pos',['../group___peripheral___registers___bits___definition.html#ga145b98f9a8b88b60ea10329203fbb745',1,'stm32f407xx_matlab.h']]], - ['eth_5fptptshr_5fsts_807',['ETH_PTPTSHR_STS',['../group___peripheral___registers___bits___definition.html#gad4e066e9342e4f16955c1506d64b26d5',1,'stm32f407xx_matlab.h']]], - ['eth_5fptptshr_5fsts_5fmsk_808',['ETH_PTPTSHR_STS_Msk',['../group___peripheral___registers___bits___definition.html#gac54fba4639ea8278ac2679ecf5693f11',1,'stm32f407xx_matlab.h']]], - ['eth_5fptptshr_5fsts_5fpos_809',['ETH_PTPTSHR_STS_Pos',['../group___peripheral___registers___bits___definition.html#ga0e50177b2fb9ba8ac977b0dec45787fc',1,'stm32f407xx_matlab.h']]], - ['eth_5fptptshur_5ftsus_810',['ETH_PTPTSHUR_TSUS',['../group___peripheral___registers___bits___definition.html#ga790cfc8e9a003b703e25d158e3490066',1,'stm32f407xx_matlab.h']]], - ['eth_5fptptshur_5ftsus_5fmsk_811',['ETH_PTPTSHUR_TSUS_Msk',['../group___peripheral___registers___bits___definition.html#ga5b1af8c724a3bb0fbbc8d796581df651',1,'stm32f407xx_matlab.h']]], - ['eth_5fptptshur_5ftsus_5fpos_812',['ETH_PTPTSHUR_TSUS_Pos',['../group___peripheral___registers___bits___definition.html#ga9d89a6613925b5dd9ec20932d66fdb44',1,'stm32f407xx_matlab.h']]], - ['eth_5fptptslr_5fstpns_813',['ETH_PTPTSLR_STPNS',['../group___peripheral___registers___bits___definition.html#ga5db7e66364e5d2022b53561fc6fcbfc6',1,'stm32f407xx_matlab.h']]], - ['eth_5fptptslr_5fstpns_5fmsk_814',['ETH_PTPTSLR_STPNS_Msk',['../group___peripheral___registers___bits___definition.html#ga57b0d4d7480472e548d2745b71c73884',1,'stm32f407xx_matlab.h']]], - ['eth_5fptptslr_5fstpns_5fpos_815',['ETH_PTPTSLR_STPNS_Pos',['../group___peripheral___registers___bits___definition.html#gac7678974b934e9b460c8f2525a2f0ead',1,'stm32f407xx_matlab.h']]], - ['eth_5fptptslr_5fstss_816',['ETH_PTPTSLR_STSS',['../group___peripheral___registers___bits___definition.html#ga56d984d62fb4bfdc0677734863135ade',1,'stm32f407xx_matlab.h']]], - ['eth_5fptptslr_5fstss_5fmsk_817',['ETH_PTPTSLR_STSS_Msk',['../group___peripheral___registers___bits___definition.html#ga5ea6ac5920c1f09cda85a6efe885d159',1,'stm32f407xx_matlab.h']]], - ['eth_5fptptslr_5fstss_5fpos_818',['ETH_PTPTSLR_STSS_Pos',['../group___peripheral___registers___bits___definition.html#gaa00f00cc105d644a374cd3ec55f191d6',1,'stm32f407xx_matlab.h']]], - ['eth_5fptptslur_5ftsupns_819',['ETH_PTPTSLUR_TSUPNS',['../group___peripheral___registers___bits___definition.html#gae03c675fcd71d14198665cb8c5956086',1,'stm32f407xx_matlab.h']]], - ['eth_5fptptslur_5ftsupns_5fmsk_820',['ETH_PTPTSLUR_TSUPNS_Msk',['../group___peripheral___registers___bits___definition.html#ga79eba1ff6e2e10261b485928bdaf9826',1,'stm32f407xx_matlab.h']]], - ['eth_5fptptslur_5ftsupns_5fpos_821',['ETH_PTPTSLUR_TSUPNS_Pos',['../group___peripheral___registers___bits___definition.html#gaf93e24b10684dff6d8a03817019e807c',1,'stm32f407xx_matlab.h']]], - ['eth_5fptptslur_5ftsuss_822',['ETH_PTPTSLUR_TSUSS',['../group___peripheral___registers___bits___definition.html#ga17fdf1f11b40e68b24a27eb2c60f50b1',1,'stm32f407xx_matlab.h']]], - ['eth_5fptptslur_5ftsuss_5fmsk_823',['ETH_PTPTSLUR_TSUSS_Msk',['../group___peripheral___registers___bits___definition.html#ga40c328002f73284b6216df8d8390a040',1,'stm32f407xx_matlab.h']]], - ['eth_5fptptslur_5ftsuss_5fpos_824',['ETH_PTPTSLUR_TSUSS_Pos',['../group___peripheral___registers___bits___definition.html#ga5f59fc90e2a93ca826f9a221a0543254',1,'stm32f407xx_matlab.h']]], - ['eth_5fptptssr_5ftsso_825',['ETH_PTPTSSR_TSSO',['../group___peripheral___registers___bits___definition.html#gaa245035f820779346591bee91d96b473',1,'stm32f407xx_matlab.h']]], - ['eth_5fptptssr_5ftsso_5fmsk_826',['ETH_PTPTSSR_TSSO_Msk',['../group___peripheral___registers___bits___definition.html#ga838b3f40f55f1ec42e054e2bc13af891',1,'stm32f407xx_matlab.h']]], - ['eth_5fptptssr_5ftsso_5fpos_827',['ETH_PTPTSSR_TSSO_Pos',['../group___peripheral___registers___bits___definition.html#gaf46c9260e7e81f588ddc44c647ea9275',1,'stm32f407xx_matlab.h']]], - ['eth_5fptptssr_5ftsttr_828',['ETH_PTPTSSR_TSTTR',['../group___peripheral___registers___bits___definition.html#ga491e96ebf2d049900f049cead51f320a',1,'stm32f407xx_matlab.h']]], - ['eth_5fptptssr_5ftsttr_5fmsk_829',['ETH_PTPTSSR_TSTTR_Msk',['../group___peripheral___registers___bits___definition.html#ga6231f5b648b131af03c3eac1c3a01182',1,'stm32f407xx_matlab.h']]], - ['eth_5fptptssr_5ftsttr_5fpos_830',['ETH_PTPTSSR_TSTTR_Pos',['../group___peripheral___registers___bits___definition.html#ga0a68e0dabcaf5d552e664091d33bf4a0',1,'stm32f407xx_matlab.h']]], - ['eth_5fptptthr_5fttsh_831',['ETH_PTPTTHR_TTSH',['../group___peripheral___registers___bits___definition.html#ga21db9a6b88a17aef32ccce70f017329e',1,'stm32f407xx_matlab.h']]], - ['eth_5fptptthr_5fttsh_5fmsk_832',['ETH_PTPTTHR_TTSH_Msk',['../group___peripheral___registers___bits___definition.html#ga80aac932c3b5b9dc4cffb160f27431af',1,'stm32f407xx_matlab.h']]], - ['eth_5fptptthr_5fttsh_5fpos_833',['ETH_PTPTTHR_TTSH_Pos',['../group___peripheral___registers___bits___definition.html#ga3a1209cf78ca23936fc172c225bcd13d',1,'stm32f407xx_matlab.h']]], - ['eth_5fptpttlr_5fttsl_834',['ETH_PTPTTLR_TTSL',['../group___peripheral___registers___bits___definition.html#ga61e7a9592215e36a8db010374f57d210',1,'stm32f407xx_matlab.h']]], - ['eth_5fptpttlr_5fttsl_5fmsk_835',['ETH_PTPTTLR_TTSL_Msk',['../group___peripheral___registers___bits___definition.html#ga7606deb781bd37b7ee59b6adcf9bc58f',1,'stm32f407xx_matlab.h']]], - ['eth_5fptpttlr_5fttsl_5fpos_836',['ETH_PTPTTLR_TTSL_Pos',['../group___peripheral___registers___bits___definition.html#gafccab56e7239c4fc0c2c260ce3da9567',1,'stm32f407xx_matlab.h']]], - ['eth_5ftypedef_837',['ETH_TypeDef',['../struct_e_t_h___type_def.html',1,'']]], - ['eth_5fwkup_5firqn_838',['ETH_WKUP_IRQn',['../group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a0485578005e12c2e2c0fb253a844ec6f',1,'stm32f407xx_matlab.h']]], - ['exc_5freturn_5fhandler_839',['EXC_RETURN_HANDLER',['../group___c_m_s_i_s___core___n_v_i_c_functions.html#gaa6fa2b10f756385433e08522d9e4632f',1,'core_cm4_matlab.h']]], - ['exc_5freturn_5fhandler_5ffpu_840',['EXC_RETURN_HANDLER_FPU',['../group___c_m_s_i_s___core___n_v_i_c_functions.html#ga3aa6648e1c3c09fbab1f543b9dcffc3a',1,'core_cm4_matlab.h']]], - ['exc_5freturn_5fthread_5fmsp_841',['EXC_RETURN_THREAD_MSP',['../group___c_m_s_i_s___core___n_v_i_c_functions.html#gaea4703101b5e679f695e231f7ee72331',1,'core_cm4_matlab.h']]], - ['exc_5freturn_5fthread_5fmsp_5ffpu_842',['EXC_RETURN_THREAD_MSP_FPU',['../group___c_m_s_i_s___core___n_v_i_c_functions.html#gaad4cb3b34fd4264ccfae1fbbc75a3431',1,'core_cm4_matlab.h']]], - ['exc_5freturn_5fthread_5fpsp_843',['EXC_RETURN_THREAD_PSP',['../group___c_m_s_i_s___core___n_v_i_c_functions.html#ga9998daf0fbdf31dbc8f81cd604b58175',1,'core_cm4_matlab.h']]], - ['exc_5freturn_5fthread_5fpsp_5ffpu_844',['EXC_RETURN_THREAD_PSP_FPU',['../group___c_m_s_i_s___core___n_v_i_c_functions.html#gadd2299e1d3a79c90b610c6b6f4cadb95',1,'core_cm4_matlab.h']]], - ['exccnt_845',['EXCCNT',['../group___c_m_s_i_s__core___debug_functions.html#gafe0bbc124e53ad450abc72bfb56bd74f',1,'DWT_Type']]], - ['exported_5fconstants_846',['Exported_constants',['../group___exported__constants.html',1,'']]], - ['exported_5fmacro_847',['Exported_macro',['../group___exported__macro.html',1,'']]], - ['exported_5fmacros_848',['Exported_macros',['../group___exported__macros.html',1,'']]], - ['exported_5ftypes_849',['Exported_types',['../group___exported__types.html',1,'']]], - ['exti_850',['EXTI',['../group___peripheral__declaration.html#ga9189e770cd9b63dadd36683eb9843cac',1,'stm32f407xx_matlab.h']]], - ['exti_851',['exti',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga5db1038489ccf5ec54a585b08226b84d',1,'stm32f4xx_periph_registers.c']]], - ['exti0_5firqn_852',['EXTI0_IRQn',['../group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8ab6aa6f87d26bbc6cf99b067b8d75c2f7',1,'stm32f407xx_matlab.h']]], - ['exti15_5f10_5firqn_853',['EXTI15_10_IRQn',['../group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a9fb0ad0c850234d1983fafdb17378e2f',1,'stm32f407xx_matlab.h']]], - ['exti1_5firqn_854',['EXTI1_IRQn',['../group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8ae4badcdecdb94eb10129c4c0577c5e19',1,'stm32f407xx_matlab.h']]], - ['exti2_5firqn_855',['EXTI2_IRQn',['../group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a082cb3f7839069a0715fd76c7eacbbc9',1,'stm32f407xx_matlab.h']]], - ['exti3_5firqn_856',['EXTI3_IRQn',['../group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8add889c84ba5de466ced209069e05d602',1,'stm32f407xx_matlab.h']]], - ['exti4_5firqn_857',['EXTI4_IRQn',['../group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8ab70a40106ca4486770df5d2072d9ac0e',1,'stm32f407xx_matlab.h']]], - ['exti9_5f5_5firqn_858',['EXTI9_5_IRQn',['../group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8aa3aa50e0353871985facf62d055faa52',1,'stm32f407xx_matlab.h']]], - ['exti_5fbase_859',['EXTI_BASE',['../group___peripheral__memory__map.html#ga87371508b3bcdcd98cd1ec629be29061',1,'stm32f407xx_matlab.h']]], - ['exti_5femr_5fem0_860',['EXTI_EMR_EM0',['../group___peripheral___registers___bits___definition.html#gaf972d7547ed83843150667c301a9d348',1,'stm32f407xx_matlab.h']]], - ['exti_5femr_5fem1_861',['EXTI_EMR_EM1',['../group___peripheral___registers___bits___definition.html#ga07843e6ff5b4ddd02bcf6c66a08cac93',1,'stm32f407xx_matlab.h']]], - ['exti_5femr_5fem10_862',['EXTI_EMR_EM10',['../group___peripheral___registers___bits___definition.html#gad548185c3c99b69f3eaec50067999112',1,'stm32f407xx_matlab.h']]], - ['exti_5femr_5fem11_863',['EXTI_EMR_EM11',['../group___peripheral___registers___bits___definition.html#gad5d0782c45b8b0951c8bbb5e7037a52b',1,'stm32f407xx_matlab.h']]], - ['exti_5femr_5fem12_864',['EXTI_EMR_EM12',['../group___peripheral___registers___bits___definition.html#gaef9eaec30663289e66b9d9b40682910f',1,'stm32f407xx_matlab.h']]], - ['exti_5femr_5fem13_865',['EXTI_EMR_EM13',['../group___peripheral___registers___bits___definition.html#gad2fc88afc4ba8231f4368527cc983d50',1,'stm32f407xx_matlab.h']]], - ['exti_5femr_5fem14_866',['EXTI_EMR_EM14',['../group___peripheral___registers___bits___definition.html#gaaf3c10c55ef88bb255f899d0d0939c98',1,'stm32f407xx_matlab.h']]], - ['exti_5femr_5fem15_867',['EXTI_EMR_EM15',['../group___peripheral___registers___bits___definition.html#gaa3690bd10db8f6505368f84d1d360d83',1,'stm32f407xx_matlab.h']]], - ['exti_5femr_5fem16_868',['EXTI_EMR_EM16',['../group___peripheral___registers___bits___definition.html#gaadea424b2e5e1e8733e5f8ba76b16c6c',1,'stm32f407xx_matlab.h']]], - ['exti_5femr_5fem17_869',['EXTI_EMR_EM17',['../group___peripheral___registers___bits___definition.html#ga0f640eaa67ff0f9e3e849fdc65f7f34e',1,'stm32f407xx_matlab.h']]], - ['exti_5femr_5fem18_870',['EXTI_EMR_EM18',['../group___peripheral___registers___bits___definition.html#ga7162c4422ad98bec692f15dda4e011eb',1,'stm32f407xx_matlab.h']]], - ['exti_5femr_5fem19_871',['EXTI_EMR_EM19',['../group___peripheral___registers___bits___definition.html#ga96076632bf23a1dfb53cfada4008d7b3',1,'stm32f407xx_matlab.h']]], - ['exti_5femr_5fem2_872',['EXTI_EMR_EM2',['../group___peripheral___registers___bits___definition.html#ga703c31569533b3b6d76f99da69b4d168',1,'stm32f407xx_matlab.h']]], - ['exti_5femr_5fem20_873',['EXTI_EMR_EM20',['../group___peripheral___registers___bits___definition.html#ga2a88ab99418d93b7277f19736c14c6c2',1,'stm32f407xx_matlab.h']]], - ['exti_5femr_5fem21_874',['EXTI_EMR_EM21',['../group___peripheral___registers___bits___definition.html#gaf17512ecb4d8572e8b73ab1a427fd500',1,'stm32f407xx_matlab.h']]], - ['exti_5femr_5fem22_875',['EXTI_EMR_EM22',['../group___peripheral___registers___bits___definition.html#ga31b9e9ec368a547f58ab7f6359c58bdf',1,'stm32f407xx_matlab.h']]], - ['exti_5femr_5fem3_876',['EXTI_EMR_EM3',['../group___peripheral___registers___bits___definition.html#ga6f2bd51b6a0981492a29436ef2b53344',1,'stm32f407xx_matlab.h']]], - ['exti_5femr_5fem4_877',['EXTI_EMR_EM4',['../group___peripheral___registers___bits___definition.html#ga7a3f176db76b4eb2cc1400f76afc967a',1,'stm32f407xx_matlab.h']]], - ['exti_5femr_5fem5_878',['EXTI_EMR_EM5',['../group___peripheral___registers___bits___definition.html#gacc0210d29dceb5682d01786b6fcf47fe',1,'stm32f407xx_matlab.h']]], - ['exti_5femr_5fem6_879',['EXTI_EMR_EM6',['../group___peripheral___registers___bits___definition.html#ga1c05702eec349cbbcce9b7bc825e2fd8',1,'stm32f407xx_matlab.h']]], - ['exti_5femr_5fem7_880',['EXTI_EMR_EM7',['../group___peripheral___registers___bits___definition.html#gaf04b9ef7548fb0564beae69739bdea72',1,'stm32f407xx_matlab.h']]], - ['exti_5femr_5fem8_881',['EXTI_EMR_EM8',['../group___peripheral___registers___bits___definition.html#ga7af57b60f4623e5a65011519dd707991',1,'stm32f407xx_matlab.h']]], - ['exti_5femr_5fem9_882',['EXTI_EMR_EM9',['../group___peripheral___registers___bits___definition.html#ga3757f0da147b7bb49719cb69096b5bc7',1,'stm32f407xx_matlab.h']]], - ['exti_5femr_5fmr0_883',['EXTI_EMR_MR0',['../group___peripheral___registers___bits___definition.html#ga515c0dc6d2472e06a89e4bb19725e8f3',1,'stm32f407xx_matlab.h']]], - ['exti_5femr_5fmr0_5fmsk_884',['EXTI_EMR_MR0_Msk',['../group___peripheral___registers___bits___definition.html#ga016c23b6c1164758878753e14201fdbc',1,'stm32f407xx_matlab.h']]], - ['exti_5femr_5fmr0_5fpos_885',['EXTI_EMR_MR0_Pos',['../group___peripheral___registers___bits___definition.html#gaf10ad3eba24a4fadc9e58e9b81c17494',1,'stm32f407xx_matlab.h']]], - ['exti_5femr_5fmr1_886',['EXTI_EMR_MR1',['../group___peripheral___registers___bits___definition.html#ga6d88e7c10e5985fa425ea7ab4fe4c3e5',1,'stm32f407xx_matlab.h']]], - ['exti_5femr_5fmr10_887',['EXTI_EMR_MR10',['../group___peripheral___registers___bits___definition.html#gaf342d34ed1b8e4aa916bf49e30c2a234',1,'stm32f407xx_matlab.h']]], - ['exti_5femr_5fmr10_5fmsk_888',['EXTI_EMR_MR10_Msk',['../group___peripheral___registers___bits___definition.html#ga3ef7af204b6807cb09f10a11f774889e',1,'stm32f407xx_matlab.h']]], - ['exti_5femr_5fmr10_5fpos_889',['EXTI_EMR_MR10_Pos',['../group___peripheral___registers___bits___definition.html#gaead96297678ea28e56765731de3f8511',1,'stm32f407xx_matlab.h']]], - ['exti_5femr_5fmr11_890',['EXTI_EMR_MR11',['../group___peripheral___registers___bits___definition.html#ga9ec516af1de770c82c3c9c458cbc0172',1,'stm32f407xx_matlab.h']]], - ['exti_5femr_5fmr11_5fmsk_891',['EXTI_EMR_MR11_Msk',['../group___peripheral___registers___bits___definition.html#gabb1a0c32eb56c845232f07d6e1498633',1,'stm32f407xx_matlab.h']]], - ['exti_5femr_5fmr11_5fpos_892',['EXTI_EMR_MR11_Pos',['../group___peripheral___registers___bits___definition.html#ga744443e18392efb9d31ceeabc2ba9786',1,'stm32f407xx_matlab.h']]], - ['exti_5femr_5fmr12_893',['EXTI_EMR_MR12',['../group___peripheral___registers___bits___definition.html#ga15732553e5b0de9f58180a0b024d4cad',1,'stm32f407xx_matlab.h']]], - ['exti_5femr_5fmr12_5fmsk_894',['EXTI_EMR_MR12_Msk',['../group___peripheral___registers___bits___definition.html#ga988ba6ff638ee9d2bc8a2dec8ef8ea32',1,'stm32f407xx_matlab.h']]], - ['exti_5femr_5fmr12_5fpos_895',['EXTI_EMR_MR12_Pos',['../group___peripheral___registers___bits___definition.html#gacdf200c3d4abdc44356ff3bfc66c136e',1,'stm32f407xx_matlab.h']]], - ['exti_5femr_5fmr13_896',['EXTI_EMR_MR13',['../group___peripheral___registers___bits___definition.html#ga9fd2ec6472e46869956acb28f5e1b55f',1,'stm32f407xx_matlab.h']]], - ['exti_5femr_5fmr13_5fmsk_897',['EXTI_EMR_MR13_Msk',['../group___peripheral___registers___bits___definition.html#ga06991d09dc3fd7373da2375b7e196452',1,'stm32f407xx_matlab.h']]], - ['exti_5femr_5fmr13_5fpos_898',['EXTI_EMR_MR13_Pos',['../group___peripheral___registers___bits___definition.html#gaacf17cbe9663809770d498fe8d28a6e5',1,'stm32f407xx_matlab.h']]], - ['exti_5femr_5fmr14_899',['EXTI_EMR_MR14',['../group___peripheral___registers___bits___definition.html#gaecf5890ea71eea034ec1cd9e96284f89',1,'stm32f407xx_matlab.h']]], - ['exti_5femr_5fmr14_5fmsk_900',['EXTI_EMR_MR14_Msk',['../group___peripheral___registers___bits___definition.html#ga56cd35406916f89cc00f5c4c153f7f3b',1,'stm32f407xx_matlab.h']]], - ['exti_5femr_5fmr14_5fpos_901',['EXTI_EMR_MR14_Pos',['../group___peripheral___registers___bits___definition.html#gae0dd6f7d71f00964f930cba3e7fc9d14',1,'stm32f407xx_matlab.h']]], - ['exti_5femr_5fmr15_902',['EXTI_EMR_MR15',['../group___peripheral___registers___bits___definition.html#ga7a7bacc32351a36aefcd5614abc76ae3',1,'stm32f407xx_matlab.h']]], - ['exti_5femr_5fmr15_5fmsk_903',['EXTI_EMR_MR15_Msk',['../group___peripheral___registers___bits___definition.html#gaaa1778406979e6566a10b085f1146a28',1,'stm32f407xx_matlab.h']]], - ['exti_5femr_5fmr15_5fpos_904',['EXTI_EMR_MR15_Pos',['../group___peripheral___registers___bits___definition.html#ga4ee0004caa46c2946bb05305cd93baa1',1,'stm32f407xx_matlab.h']]], - ['exti_5femr_5fmr16_905',['EXTI_EMR_MR16',['../group___peripheral___registers___bits___definition.html#ga34b1a6934265da759bc061f73d5d1374',1,'stm32f407xx_matlab.h']]], - ['exti_5femr_5fmr16_5fmsk_906',['EXTI_EMR_MR16_Msk',['../group___peripheral___registers___bits___definition.html#ga3cb43eaaa268ddc9d407c5edcfb05ff4',1,'stm32f407xx_matlab.h']]], - ['exti_5femr_5fmr16_5fpos_907',['EXTI_EMR_MR16_Pos',['../group___peripheral___registers___bits___definition.html#ga112b3657ea27bac2cfe0676dfa893157',1,'stm32f407xx_matlab.h']]], - ['exti_5femr_5fmr17_908',['EXTI_EMR_MR17',['../group___peripheral___registers___bits___definition.html#ga6a30aa20cf475eecf7e15171e83035e4',1,'stm32f407xx_matlab.h']]], - ['exti_5femr_5fmr17_5fmsk_909',['EXTI_EMR_MR17_Msk',['../group___peripheral___registers___bits___definition.html#ga889175528233c464f6c0a5f8a901a06d',1,'stm32f407xx_matlab.h']]], - ['exti_5femr_5fmr17_5fpos_910',['EXTI_EMR_MR17_Pos',['../group___peripheral___registers___bits___definition.html#gad853ef0d4af0ed5b68581464a067e1ab',1,'stm32f407xx_matlab.h']]], - ['exti_5femr_5fmr18_911',['EXTI_EMR_MR18',['../group___peripheral___registers___bits___definition.html#ga25eee729b57b4c78a0613c184fc539e5',1,'stm32f407xx_matlab.h']]], - ['exti_5femr_5fmr18_5fmsk_912',['EXTI_EMR_MR18_Msk',['../group___peripheral___registers___bits___definition.html#ga3e6e89686fa4e8fe58365b684331f398',1,'stm32f407xx_matlab.h']]], - ['exti_5femr_5fmr18_5fpos_913',['EXTI_EMR_MR18_Pos',['../group___peripheral___registers___bits___definition.html#ga7edb364e6ab767686e3c40b177489f00',1,'stm32f407xx_matlab.h']]], - ['exti_5femr_5fmr19_914',['EXTI_EMR_MR19',['../group___peripheral___registers___bits___definition.html#gaaeababa85e5ebe6aa93d011d83fd7994',1,'stm32f407xx_matlab.h']]], - ['exti_5femr_5fmr19_5fmsk_915',['EXTI_EMR_MR19_Msk',['../group___peripheral___registers___bits___definition.html#ga514f26dc55f8e37ec8ac8bef9dfcadd4',1,'stm32f407xx_matlab.h']]], - ['exti_5femr_5fmr19_5fpos_916',['EXTI_EMR_MR19_Pos',['../group___peripheral___registers___bits___definition.html#ga8990f832c2588cb200a51d52c5dc8c8a',1,'stm32f407xx_matlab.h']]], - ['exti_5femr_5fmr1_5fmsk_917',['EXTI_EMR_MR1_Msk',['../group___peripheral___registers___bits___definition.html#gaa419f81a443fd7eac16ac340c971dc63',1,'stm32f407xx_matlab.h']]], - ['exti_5femr_5fmr1_5fpos_918',['EXTI_EMR_MR1_Pos',['../group___peripheral___registers___bits___definition.html#gab2891b4a57f827defecd2ebb2cac457b',1,'stm32f407xx_matlab.h']]], - ['exti_5femr_5fmr2_919',['EXTI_EMR_MR2',['../group___peripheral___registers___bits___definition.html#ga460d5d4c0b53bcc04d5804e1204ded21',1,'stm32f407xx_matlab.h']]], - ['exti_5femr_5fmr20_920',['EXTI_EMR_MR20',['../group___peripheral___registers___bits___definition.html#ga047743f042d00f058dd8cf199c92fbfa',1,'stm32f407xx_matlab.h']]], - ['exti_5femr_5fmr20_5fmsk_921',['EXTI_EMR_MR20_Msk',['../group___peripheral___registers___bits___definition.html#gae190c58438ea386748cb39b06fc2d62c',1,'stm32f407xx_matlab.h']]], - ['exti_5femr_5fmr20_5fpos_922',['EXTI_EMR_MR20_Pos',['../group___peripheral___registers___bits___definition.html#gaa67b8f9a15a25b5d2bc93d72082652bd',1,'stm32f407xx_matlab.h']]], - ['exti_5femr_5fmr21_923',['EXTI_EMR_MR21',['../group___peripheral___registers___bits___definition.html#ga935956e41524c1f96d208f63a699377a',1,'stm32f407xx_matlab.h']]], - ['exti_5femr_5fmr21_5fmsk_924',['EXTI_EMR_MR21_Msk',['../group___peripheral___registers___bits___definition.html#ga525d06c52556b824cbf29d85a8925532',1,'stm32f407xx_matlab.h']]], - ['exti_5femr_5fmr21_5fpos_925',['EXTI_EMR_MR21_Pos',['../group___peripheral___registers___bits___definition.html#ga75a62823a85e5c8543646c7c6b273e2f',1,'stm32f407xx_matlab.h']]], - ['exti_5femr_5fmr22_926',['EXTI_EMR_MR22',['../group___peripheral___registers___bits___definition.html#ga8fbc202d80be3899d867a0b74abad813',1,'stm32f407xx_matlab.h']]], - ['exti_5femr_5fmr22_5fmsk_927',['EXTI_EMR_MR22_Msk',['../group___peripheral___registers___bits___definition.html#ga79c121c40bb976f66094ced0a851419a',1,'stm32f407xx_matlab.h']]], - ['exti_5femr_5fmr22_5fpos_928',['EXTI_EMR_MR22_Pos',['../group___peripheral___registers___bits___definition.html#gae52ca7f79c4b6092d6e2b781f0355bd8',1,'stm32f407xx_matlab.h']]], - ['exti_5femr_5fmr2_5fmsk_929',['EXTI_EMR_MR2_Msk',['../group___peripheral___registers___bits___definition.html#ga546cba14a3e8a8172d5652e670ac9ed3',1,'stm32f407xx_matlab.h']]], - ['exti_5femr_5fmr2_5fpos_930',['EXTI_EMR_MR2_Pos',['../group___peripheral___registers___bits___definition.html#ga09e8782d37f1f13cc30d86c2c3a02576',1,'stm32f407xx_matlab.h']]], - ['exti_5femr_5fmr3_931',['EXTI_EMR_MR3',['../group___peripheral___registers___bits___definition.html#ga73944983ce5a6bde9dc172b4f483898c',1,'stm32f407xx_matlab.h']]], - ['exti_5femr_5fmr3_5fmsk_932',['EXTI_EMR_MR3_Msk',['../group___peripheral___registers___bits___definition.html#ga14290334e49a34a93a3ce229bd5ecf74',1,'stm32f407xx_matlab.h']]], - ['exti_5femr_5fmr3_5fpos_933',['EXTI_EMR_MR3_Pos',['../group___peripheral___registers___bits___definition.html#gaeac760511bc46050ceb4ece479ead54b',1,'stm32f407xx_matlab.h']]], - ['exti_5femr_5fmr4_934',['EXTI_EMR_MR4',['../group___peripheral___registers___bits___definition.html#gab80f809ead83e747677a31c80c6aae03',1,'stm32f407xx_matlab.h']]], - ['exti_5femr_5fmr4_5fmsk_935',['EXTI_EMR_MR4_Msk',['../group___peripheral___registers___bits___definition.html#ga478ee1f30cf0d4ef71d512507fcb9cb7',1,'stm32f407xx_matlab.h']]], - ['exti_5femr_5fmr4_5fpos_936',['EXTI_EMR_MR4_Pos',['../group___peripheral___registers___bits___definition.html#ga4a337713821f1ea29a953eee7a2a6d2f',1,'stm32f407xx_matlab.h']]], - ['exti_5femr_5fmr5_937',['EXTI_EMR_MR5',['../group___peripheral___registers___bits___definition.html#ga65976f75b703f740dea3562ba3b8db59',1,'stm32f407xx_matlab.h']]], - ['exti_5femr_5fmr5_5fmsk_938',['EXTI_EMR_MR5_Msk',['../group___peripheral___registers___bits___definition.html#ga3e60a767b0307626c3cd4cbd01d10304',1,'stm32f407xx_matlab.h']]], - ['exti_5femr_5fmr5_5fpos_939',['EXTI_EMR_MR5_Pos',['../group___peripheral___registers___bits___definition.html#ga79e7760224986ab31fc06f5d84aa3b7f',1,'stm32f407xx_matlab.h']]], - ['exti_5femr_5fmr6_940',['EXTI_EMR_MR6',['../group___peripheral___registers___bits___definition.html#gaea480bd932cd1fa0904f5eb1caee9a12',1,'stm32f407xx_matlab.h']]], - ['exti_5femr_5fmr6_5fmsk_941',['EXTI_EMR_MR6_Msk',['../group___peripheral___registers___bits___definition.html#ga9ca40f93d86d921adecd19479b7ab5c6',1,'stm32f407xx_matlab.h']]], - ['exti_5femr_5fmr6_5fpos_942',['EXTI_EMR_MR6_Pos',['../group___peripheral___registers___bits___definition.html#gaf3210ae740c584799c07b1e7995e4252',1,'stm32f407xx_matlab.h']]], - ['exti_5femr_5fmr7_943',['EXTI_EMR_MR7',['../group___peripheral___registers___bits___definition.html#gadbb27ff8664928994ef96f87052d14be',1,'stm32f407xx_matlab.h']]], - ['exti_5femr_5fmr7_5fmsk_944',['EXTI_EMR_MR7_Msk',['../group___peripheral___registers___bits___definition.html#gace6755a5d4b361648f0b2c76a0b32282',1,'stm32f407xx_matlab.h']]], - ['exti_5femr_5fmr7_5fpos_945',['EXTI_EMR_MR7_Pos',['../group___peripheral___registers___bits___definition.html#gafafbf203c2dae41123f2eaf6565bb2f4',1,'stm32f407xx_matlab.h']]], - ['exti_5femr_5fmr8_946',['EXTI_EMR_MR8',['../group___peripheral___registers___bits___definition.html#ga4ed4b371da871ffd0cc12ee00147282f',1,'stm32f407xx_matlab.h']]], - ['exti_5femr_5fmr8_5fmsk_947',['EXTI_EMR_MR8_Msk',['../group___peripheral___registers___bits___definition.html#ga00700896523030015c081b6caa3b72b5',1,'stm32f407xx_matlab.h']]], - ['exti_5femr_5fmr8_5fpos_948',['EXTI_EMR_MR8_Pos',['../group___peripheral___registers___bits___definition.html#gae3349563ae0947ec6c441fe912fb0ede',1,'stm32f407xx_matlab.h']]], - ['exti_5femr_5fmr9_949',['EXTI_EMR_MR9',['../group___peripheral___registers___bits___definition.html#ga109af342179fff1fccfdde582834867a',1,'stm32f407xx_matlab.h']]], - ['exti_5femr_5fmr9_5fmsk_950',['EXTI_EMR_MR9_Msk',['../group___peripheral___registers___bits___definition.html#ga47c54d6a078dcc8b9aec22e327785fdd',1,'stm32f407xx_matlab.h']]], - ['exti_5femr_5fmr9_5fpos_951',['EXTI_EMR_MR9_Pos',['../group___peripheral___registers___bits___definition.html#gac42d64759efd55a329c207a31c7e3033',1,'stm32f407xx_matlab.h']]], - ['exti_5fftsr_5ftr0_952',['EXTI_FTSR_TR0',['../group___peripheral___registers___bits___definition.html#gacfb6fa5ae3fcaf08aec6d86c3bfefa4c',1,'stm32f407xx_matlab.h']]], - ['exti_5fftsr_5ftr0_5fmsk_953',['EXTI_FTSR_TR0_Msk',['../group___peripheral___registers___bits___definition.html#ga6fd5afa140faff4e562142dc289387cc',1,'stm32f407xx_matlab.h']]], - ['exti_5fftsr_5ftr0_5fpos_954',['EXTI_FTSR_TR0_Pos',['../group___peripheral___registers___bits___definition.html#ga0a92993932aa377be10ff0376f600b9f',1,'stm32f407xx_matlab.h']]], - ['exti_5fftsr_5ftr1_955',['EXTI_FTSR_TR1',['../group___peripheral___registers___bits___definition.html#gac287be3bd3bad84aed48603dbe8bd4ed',1,'stm32f407xx_matlab.h']]], - ['exti_5fftsr_5ftr10_956',['EXTI_FTSR_TR10',['../group___peripheral___registers___bits___definition.html#gac9a2b80699a213f0d2b03658f21ad643',1,'stm32f407xx_matlab.h']]], - ['exti_5fftsr_5ftr10_5fmsk_957',['EXTI_FTSR_TR10_Msk',['../group___peripheral___registers___bits___definition.html#ga8e6991a6c2f7e8fd99992d7623a31093',1,'stm32f407xx_matlab.h']]], - ['exti_5fftsr_5ftr10_5fpos_958',['EXTI_FTSR_TR10_Pos',['../group___peripheral___registers___bits___definition.html#ga0592581c7bd1ea908087aa319528fdae',1,'stm32f407xx_matlab.h']]], - ['exti_5fftsr_5ftr11_959',['EXTI_FTSR_TR11',['../group___peripheral___registers___bits___definition.html#ga6c74d4d520406a14c517784cdd5fc6ef',1,'stm32f407xx_matlab.h']]], - ['exti_5fftsr_5ftr11_5fmsk_960',['EXTI_FTSR_TR11_Msk',['../group___peripheral___registers___bits___definition.html#gac985e7db4d6a853c4411544878fd0551',1,'stm32f407xx_matlab.h']]], - ['exti_5fftsr_5ftr11_5fpos_961',['EXTI_FTSR_TR11_Pos',['../group___peripheral___registers___bits___definition.html#ga32ce99e8292f13831e1c8eaa79dc3554',1,'stm32f407xx_matlab.h']]], - ['exti_5fftsr_5ftr12_962',['EXTI_FTSR_TR12',['../group___peripheral___registers___bits___definition.html#ga3992511ec1785bdf107873b139d74245',1,'stm32f407xx_matlab.h']]], - ['exti_5fftsr_5ftr12_5fmsk_963',['EXTI_FTSR_TR12_Msk',['../group___peripheral___registers___bits___definition.html#ga3f1c99fa4436d7a5fad4632366db4462',1,'stm32f407xx_matlab.h']]], - ['exti_5fftsr_5ftr12_5fpos_964',['EXTI_FTSR_TR12_Pos',['../group___peripheral___registers___bits___definition.html#ga49f1f39d43c981697a040fc94abbbfc1',1,'stm32f407xx_matlab.h']]], - ['exti_5fftsr_5ftr13_965',['EXTI_FTSR_TR13',['../group___peripheral___registers___bits___definition.html#ga0714519a1edcba4695f92f1bba70e825',1,'stm32f407xx_matlab.h']]], - ['exti_5fftsr_5ftr13_5fmsk_966',['EXTI_FTSR_TR13_Msk',['../group___peripheral___registers___bits___definition.html#ga89275d329ff466aee9a8b226376eb9b7',1,'stm32f407xx_matlab.h']]], - ['exti_5fftsr_5ftr13_5fpos_967',['EXTI_FTSR_TR13_Pos',['../group___peripheral___registers___bits___definition.html#gabd86158859c108fbe911aff6498eb15b',1,'stm32f407xx_matlab.h']]], - ['exti_5fftsr_5ftr14_968',['EXTI_FTSR_TR14',['../group___peripheral___registers___bits___definition.html#ga5b92577e64a95ef2069f1a56176d35ff',1,'stm32f407xx_matlab.h']]], - ['exti_5fftsr_5ftr14_5fmsk_969',['EXTI_FTSR_TR14_Msk',['../group___peripheral___registers___bits___definition.html#ga4e2e56c2bfea3a94e5bc8905b5008dd0',1,'stm32f407xx_matlab.h']]], - ['exti_5fftsr_5ftr14_5fpos_970',['EXTI_FTSR_TR14_Pos',['../group___peripheral___registers___bits___definition.html#gaffd9b96b99f65602a7d5285d62b8c0ac',1,'stm32f407xx_matlab.h']]], - ['exti_5fftsr_5ftr15_971',['EXTI_FTSR_TR15',['../group___peripheral___registers___bits___definition.html#ga2a6cc515f13ffe1a3620d06fa08addc7',1,'stm32f407xx_matlab.h']]], - ['exti_5fftsr_5ftr15_5fmsk_972',['EXTI_FTSR_TR15_Msk',['../group___peripheral___registers___bits___definition.html#ga7b78c01259464833376dbc4755fefc21',1,'stm32f407xx_matlab.h']]], - ['exti_5fftsr_5ftr15_5fpos_973',['EXTI_FTSR_TR15_Pos',['../group___peripheral___registers___bits___definition.html#gaa5a3ca20b1ac9fdf5794fe609a3fe333',1,'stm32f407xx_matlab.h']]], - ['exti_5fftsr_5ftr16_974',['EXTI_FTSR_TR16',['../group___peripheral___registers___bits___definition.html#gaa1b4b850094ccc48790a1e4616ceebd2',1,'stm32f407xx_matlab.h']]], - ['exti_5fftsr_5ftr16_5fmsk_975',['EXTI_FTSR_TR16_Msk',['../group___peripheral___registers___bits___definition.html#gad43c9167b3d4af750254db5efaf97aa4',1,'stm32f407xx_matlab.h']]], - ['exti_5fftsr_5ftr16_5fpos_976',['EXTI_FTSR_TR16_Pos',['../group___peripheral___registers___bits___definition.html#ga5b123b9f8f09d0d1fcb29f846279ce21',1,'stm32f407xx_matlab.h']]], - ['exti_5fftsr_5ftr17_977',['EXTI_FTSR_TR17',['../group___peripheral___registers___bits___definition.html#ga009e618c9563b3a8dcaec493006115c7',1,'stm32f407xx_matlab.h']]], - ['exti_5fftsr_5ftr17_5fmsk_978',['EXTI_FTSR_TR17_Msk',['../group___peripheral___registers___bits___definition.html#ga3170e25ad439045d2372d1e052cea88c',1,'stm32f407xx_matlab.h']]], - ['exti_5fftsr_5ftr17_5fpos_979',['EXTI_FTSR_TR17_Pos',['../group___peripheral___registers___bits___definition.html#gacf5a7f78ce681c3f1b7afbaf3471d1f4',1,'stm32f407xx_matlab.h']]], - ['exti_5fftsr_5ftr18_980',['EXTI_FTSR_TR18',['../group___peripheral___registers___bits___definition.html#ga405285cdc474ee20085b17ef1f61517e',1,'stm32f407xx_matlab.h']]], - ['exti_5fftsr_5ftr18_5fmsk_981',['EXTI_FTSR_TR18_Msk',['../group___peripheral___registers___bits___definition.html#gac793e138d33f0b8106662bb5783b0eaf',1,'stm32f407xx_matlab.h']]], - ['exti_5fftsr_5ftr18_5fpos_982',['EXTI_FTSR_TR18_Pos',['../group___peripheral___registers___bits___definition.html#ga52a49bf16fd86f2e5f0c0cd439be375f',1,'stm32f407xx_matlab.h']]], - ['exti_5fftsr_5ftr19_983',['EXTI_FTSR_TR19',['../group___peripheral___registers___bits___definition.html#ga1277527e2fa727fdec2dcc7a300ea1af',1,'stm32f407xx_matlab.h']]], - ['exti_5fftsr_5ftr19_5fmsk_984',['EXTI_FTSR_TR19_Msk',['../group___peripheral___registers___bits___definition.html#gaa1a59ec9892e009f734e6c7703af85c4',1,'stm32f407xx_matlab.h']]], - ['exti_5fftsr_5ftr19_5fpos_985',['EXTI_FTSR_TR19_Pos',['../group___peripheral___registers___bits___definition.html#gaf317413191ad372394192996edebfcb3',1,'stm32f407xx_matlab.h']]], - ['exti_5fftsr_5ftr1_5fmsk_986',['EXTI_FTSR_TR1_Msk',['../group___peripheral___registers___bits___definition.html#ga01090491a062f3b8b4a80b0b66690ce8',1,'stm32f407xx_matlab.h']]], - ['exti_5fftsr_5ftr1_5fpos_987',['EXTI_FTSR_TR1_Pos',['../group___peripheral___registers___bits___definition.html#gadf26d85ea048d7c483094a9eebaa7aba',1,'stm32f407xx_matlab.h']]], - ['exti_5fftsr_5ftr2_988',['EXTI_FTSR_TR2',['../group___peripheral___registers___bits___definition.html#ga9c4503803cbe1933cd35519cfc809041',1,'stm32f407xx_matlab.h']]], - ['exti_5fftsr_5ftr20_989',['EXTI_FTSR_TR20',['../group___peripheral___registers___bits___definition.html#gae185289c161b407cdcd5ca185aca5477',1,'stm32f407xx_matlab.h']]], - ['exti_5fftsr_5ftr20_5fmsk_990',['EXTI_FTSR_TR20_Msk',['../group___peripheral___registers___bits___definition.html#ga0f627753cee5eab2cc5111bc5698fd36',1,'stm32f407xx_matlab.h']]], - ['exti_5fftsr_5ftr20_5fpos_991',['EXTI_FTSR_TR20_Pos',['../group___peripheral___registers___bits___definition.html#ga159e0d936264a23e36e44430355412c3',1,'stm32f407xx_matlab.h']]], - ['exti_5fftsr_5ftr21_992',['EXTI_FTSR_TR21',['../group___peripheral___registers___bits___definition.html#ga04957f9a7aa38bc50d6ac9340697a826',1,'stm32f407xx_matlab.h']]], - ['exti_5fftsr_5ftr21_5fmsk_993',['EXTI_FTSR_TR21_Msk',['../group___peripheral___registers___bits___definition.html#ga3bb39db3d5a47c3e7baf4240b5738064',1,'stm32f407xx_matlab.h']]], - ['exti_5fftsr_5ftr21_5fpos_994',['EXTI_FTSR_TR21_Pos',['../group___peripheral___registers___bits___definition.html#ga53324986eef8e0f233b9d7c7650f88f8',1,'stm32f407xx_matlab.h']]], - ['exti_5fftsr_5ftr22_995',['EXTI_FTSR_TR22',['../group___peripheral___registers___bits___definition.html#gaa7931f3a5864584bc80de7ab3455517e',1,'stm32f407xx_matlab.h']]], - ['exti_5fftsr_5ftr22_5fmsk_996',['EXTI_FTSR_TR22_Msk',['../group___peripheral___registers___bits___definition.html#gaf39fdb81f4c5e0e4a566369b17b1a88a',1,'stm32f407xx_matlab.h']]], - ['exti_5fftsr_5ftr22_5fpos_997',['EXTI_FTSR_TR22_Pos',['../group___peripheral___registers___bits___definition.html#gabf272ea16ee6c30f486255e71179f34d',1,'stm32f407xx_matlab.h']]], - ['exti_5fftsr_5ftr2_5fmsk_998',['EXTI_FTSR_TR2_Msk',['../group___peripheral___registers___bits___definition.html#ga71bfd75475e3d65a3bee0a4ccd41e0e3',1,'stm32f407xx_matlab.h']]], - ['exti_5fftsr_5ftr2_5fpos_999',['EXTI_FTSR_TR2_Pos',['../group___peripheral___registers___bits___definition.html#ga425e560479e3bcf114aca570bd170079',1,'stm32f407xx_matlab.h']]], - ['exti_5fftsr_5ftr3_1000',['EXTI_FTSR_TR3',['../group___peripheral___registers___bits___definition.html#ga23593d2b8a9ec0147bab28765af30e1f',1,'stm32f407xx_matlab.h']]], - ['exti_5fftsr_5ftr3_5fmsk_1001',['EXTI_FTSR_TR3_Msk',['../group___peripheral___registers___bits___definition.html#ga71b35fe3af253035fe6c7a8702ef8e5e',1,'stm32f407xx_matlab.h']]], - ['exti_5fftsr_5ftr3_5fpos_1002',['EXTI_FTSR_TR3_Pos',['../group___peripheral___registers___bits___definition.html#gaaf7f91925c2ac9c267480ed6b9fc1a04',1,'stm32f407xx_matlab.h']]], - ['exti_5fftsr_5ftr4_1003',['EXTI_FTSR_TR4',['../group___peripheral___registers___bits___definition.html#gaa77211bfa8f4d77cf373296954dad6b2',1,'stm32f407xx_matlab.h']]], - ['exti_5fftsr_5ftr4_5fmsk_1004',['EXTI_FTSR_TR4_Msk',['../group___peripheral___registers___bits___definition.html#gabecb16c1706cb6cad8ec0a8e06ac2475',1,'stm32f407xx_matlab.h']]], - ['exti_5fftsr_5ftr4_5fpos_1005',['EXTI_FTSR_TR4_Pos',['../group___peripheral___registers___bits___definition.html#gaa295a76e5ee487856be1dde365373f5d',1,'stm32f407xx_matlab.h']]], - ['exti_5fftsr_5ftr5_1006',['EXTI_FTSR_TR5',['../group___peripheral___registers___bits___definition.html#ga903f9b080c5971dd5d7935e5b87886e2',1,'stm32f407xx_matlab.h']]], - ['exti_5fftsr_5ftr5_5fmsk_1007',['EXTI_FTSR_TR5_Msk',['../group___peripheral___registers___bits___definition.html#gafeffba32b6b0854a232493dc2e2634d4',1,'stm32f407xx_matlab.h']]], - ['exti_5fftsr_5ftr5_5fpos_1008',['EXTI_FTSR_TR5_Pos',['../group___peripheral___registers___bits___definition.html#ga8f3affd9eee854acf6d5e1d820421532',1,'stm32f407xx_matlab.h']]], - ['exti_5fftsr_5ftr6_1009',['EXTI_FTSR_TR6',['../group___peripheral___registers___bits___definition.html#gae8527cce22f69e02a08ed67a67f8e5ca',1,'stm32f407xx_matlab.h']]], - ['exti_5fftsr_5ftr6_5fmsk_1010',['EXTI_FTSR_TR6_Msk',['../group___peripheral___registers___bits___definition.html#gaa6590e0e011792337a19831a0ea2df2c',1,'stm32f407xx_matlab.h']]], - ['exti_5fftsr_5ftr6_5fpos_1011',['EXTI_FTSR_TR6_Pos',['../group___peripheral___registers___bits___definition.html#gac5995bc6ec7301b6623c8014fd9db711',1,'stm32f407xx_matlab.h']]], - ['exti_5fftsr_5ftr7_1012',['EXTI_FTSR_TR7',['../group___peripheral___registers___bits___definition.html#gaf408315e497b902922a9bf40a4c6f567',1,'stm32f407xx_matlab.h']]], - ['exti_5fftsr_5ftr7_5fmsk_1013',['EXTI_FTSR_TR7_Msk',['../group___peripheral___registers___bits___definition.html#ga0d1347ed594a5d5bb5e0a69f31cbfb20',1,'stm32f407xx_matlab.h']]], - ['exti_5fftsr_5ftr7_5fpos_1014',['EXTI_FTSR_TR7_Pos',['../group___peripheral___registers___bits___definition.html#gaf100b4a2a76bcfdc3f7d0da8d39cc8b1',1,'stm32f407xx_matlab.h']]], - ['exti_5fftsr_5ftr8_1015',['EXTI_FTSR_TR8',['../group___peripheral___registers___bits___definition.html#ga00f1bded4d121e21116627b8e80784fc',1,'stm32f407xx_matlab.h']]], - ['exti_5fftsr_5ftr8_5fmsk_1016',['EXTI_FTSR_TR8_Msk',['../group___peripheral___registers___bits___definition.html#gaf0b6b9ab34a5724cebedd0ccbf1ad65e',1,'stm32f407xx_matlab.h']]], - ['exti_5fftsr_5ftr8_5fpos_1017',['EXTI_FTSR_TR8_Pos',['../group___peripheral___registers___bits___definition.html#gadb1e5c22b9a7b2b53fbcc3d50a7ac80a',1,'stm32f407xx_matlab.h']]], - ['exti_5fftsr_5ftr9_1018',['EXTI_FTSR_TR9',['../group___peripheral___registers___bits___definition.html#ga89f0c4de2b6acb75302d206b697f83ef',1,'stm32f407xx_matlab.h']]], - ['exti_5fftsr_5ftr9_5fmsk_1019',['EXTI_FTSR_TR9_Msk',['../group___peripheral___registers___bits___definition.html#ga898047db88343aeac8c05f39c4bc63e0',1,'stm32f407xx_matlab.h']]], - ['exti_5fftsr_5ftr9_5fpos_1020',['EXTI_FTSR_TR9_Pos',['../group___peripheral___registers___bits___definition.html#ga165ac2e2e46e32debc7efd99e258e608',1,'stm32f407xx_matlab.h']]], - ['exti_5fimr_5fim_1021',['EXTI_IMR_IM',['../group___peripheral___registers___bits___definition.html#gae4f23236f2d0bb9ed886556064714c50',1,'stm32f407xx_matlab.h']]], - ['exti_5fimr_5fim0_1022',['EXTI_IMR_IM0',['../group___peripheral___registers___bits___definition.html#gae43e6abdba2e7d7b7eaa07b268f288b3',1,'stm32f407xx_matlab.h']]], - ['exti_5fimr_5fim1_1023',['EXTI_IMR_IM1',['../group___peripheral___registers___bits___definition.html#ga1498c6a9cb8eb9842b83a2e91b3c290d',1,'stm32f407xx_matlab.h']]], - ['exti_5fimr_5fim10_1024',['EXTI_IMR_IM10',['../group___peripheral___registers___bits___definition.html#ga6e31c6dd167542dc8660c7dd6f31e0e9',1,'stm32f407xx_matlab.h']]], - ['exti_5fimr_5fim11_1025',['EXTI_IMR_IM11',['../group___peripheral___registers___bits___definition.html#ga5441a9f074c104d67a7629467724f3a0',1,'stm32f407xx_matlab.h']]], - ['exti_5fimr_5fim12_1026',['EXTI_IMR_IM12',['../group___peripheral___registers___bits___definition.html#gab736b78d54e4ae9b5f1ee0bebbda1e4d',1,'stm32f407xx_matlab.h']]], - ['exti_5fimr_5fim13_1027',['EXTI_IMR_IM13',['../group___peripheral___registers___bits___definition.html#ga1b835eee91599273c334d6bed80bdaca',1,'stm32f407xx_matlab.h']]], - ['exti_5fimr_5fim14_1028',['EXTI_IMR_IM14',['../group___peripheral___registers___bits___definition.html#ga933e1e28d08958b9800cbfbea953b9e6',1,'stm32f407xx_matlab.h']]], - ['exti_5fimr_5fim15_1029',['EXTI_IMR_IM15',['../group___peripheral___registers___bits___definition.html#ga16ac63565a42896a10eb5b56d45df7f1',1,'stm32f407xx_matlab.h']]], - ['exti_5fimr_5fim16_1030',['EXTI_IMR_IM16',['../group___peripheral___registers___bits___definition.html#ga33e28d73aacdcc55491fe44c2e840398',1,'stm32f407xx_matlab.h']]], - ['exti_5fimr_5fim17_1031',['EXTI_IMR_IM17',['../group___peripheral___registers___bits___definition.html#ga0db46755679e595721057e90574b1434',1,'stm32f407xx_matlab.h']]], - ['exti_5fimr_5fim18_1032',['EXTI_IMR_IM18',['../group___peripheral___registers___bits___definition.html#ga0f0a2063e564c44ba51733e0fcf25745',1,'stm32f407xx_matlab.h']]], - ['exti_5fimr_5fim19_1033',['EXTI_IMR_IM19',['../group___peripheral___registers___bits___definition.html#ga8cc8bc70fd30f54311218abe6c52c21c',1,'stm32f407xx_matlab.h']]], - ['exti_5fimr_5fim2_1034',['EXTI_IMR_IM2',['../group___peripheral___registers___bits___definition.html#ga10013221a5de01374bb63623ca68d5a5',1,'stm32f407xx_matlab.h']]], - ['exti_5fimr_5fim20_1035',['EXTI_IMR_IM20',['../group___peripheral___registers___bits___definition.html#ga8ec4f917392fcd3b64bfae4d17fe1808',1,'stm32f407xx_matlab.h']]], - ['exti_5fimr_5fim21_1036',['EXTI_IMR_IM21',['../group___peripheral___registers___bits___definition.html#ga9539fd6427a262f7cdbd42cd68a10eca',1,'stm32f407xx_matlab.h']]], - ['exti_5fimr_5fim22_1037',['EXTI_IMR_IM22',['../group___peripheral___registers___bits___definition.html#gab05cb948001efcf6d1cf4968160f3aa5',1,'stm32f407xx_matlab.h']]], - ['exti_5fimr_5fim3_1038',['EXTI_IMR_IM3',['../group___peripheral___registers___bits___definition.html#ga7a7e8e899926ae962ae34dc9d143fd09',1,'stm32f407xx_matlab.h']]], - ['exti_5fimr_5fim4_1039',['EXTI_IMR_IM4',['../group___peripheral___registers___bits___definition.html#gadad3c244ed0a107b5c4f96470a914348',1,'stm32f407xx_matlab.h']]], - ['exti_5fimr_5fim5_1040',['EXTI_IMR_IM5',['../group___peripheral___registers___bits___definition.html#ga91070bca3731cbe48e7bc97de97631a5',1,'stm32f407xx_matlab.h']]], - ['exti_5fimr_5fim6_1041',['EXTI_IMR_IM6',['../group___peripheral___registers___bits___definition.html#ga2ab55682980062f57cdb981aa649fbf3',1,'stm32f407xx_matlab.h']]], - ['exti_5fimr_5fim7_1042',['EXTI_IMR_IM7',['../group___peripheral___registers___bits___definition.html#gabd6ee214b24d450efe0c52d0b1dae0f4',1,'stm32f407xx_matlab.h']]], - ['exti_5fimr_5fim8_1043',['EXTI_IMR_IM8',['../group___peripheral___registers___bits___definition.html#gacc41defd6bd026adde49d44ad1e8a5c4',1,'stm32f407xx_matlab.h']]], - ['exti_5fimr_5fim9_1044',['EXTI_IMR_IM9',['../group___peripheral___registers___bits___definition.html#ga0a43b1d5d7f5dabbc44b03bdab7a6c3e',1,'stm32f407xx_matlab.h']]], - ['exti_5fimr_5fim_5fmsk_1045',['EXTI_IMR_IM_Msk',['../group___peripheral___registers___bits___definition.html#ga06eeb49b799d40a72140618195e6a55d',1,'stm32f407xx_matlab.h']]], - ['exti_5fimr_5fim_5fpos_1046',['EXTI_IMR_IM_Pos',['../group___peripheral___registers___bits___definition.html#ga1fe01103a449e5f81a25c733a3c1a03c',1,'stm32f407xx_matlab.h']]], - ['exti_5fimr_5fmr0_1047',['EXTI_IMR_MR0',['../group___peripheral___registers___bits___definition.html#gad03b2ba6cde99065627fccabd54ac097',1,'stm32f407xx_matlab.h']]], - ['exti_5fimr_5fmr0_5fmsk_1048',['EXTI_IMR_MR0_Msk',['../group___peripheral___registers___bits___definition.html#gaaf1117a400c80d740d3dbb7fbea0f8ce',1,'stm32f407xx_matlab.h']]], - ['exti_5fimr_5fmr0_5fpos_1049',['EXTI_IMR_MR0_Pos',['../group___peripheral___registers___bits___definition.html#ga4702ca255bab973cffa5dd240594a7a3',1,'stm32f407xx_matlab.h']]], - ['exti_5fimr_5fmr1_1050',['EXTI_IMR_MR1',['../group___peripheral___registers___bits___definition.html#gaaaf3f9a86c620149893db38c83f8ba58',1,'stm32f407xx_matlab.h']]], - ['exti_5fimr_5fmr10_1051',['EXTI_IMR_MR10',['../group___peripheral___registers___bits___definition.html#ga5fd7db9a1ce82c152ca7bc6fddf31366',1,'stm32f407xx_matlab.h']]], - ['exti_5fimr_5fmr10_5fmsk_1052',['EXTI_IMR_MR10_Msk',['../group___peripheral___registers___bits___definition.html#ga530c1c2659363a1edaba4af52c7e6a7d',1,'stm32f407xx_matlab.h']]], - ['exti_5fimr_5fmr10_5fpos_1053',['EXTI_IMR_MR10_Pos',['../group___peripheral___registers___bits___definition.html#ga0f8a8f8245716f96dde7049e27435f9a',1,'stm32f407xx_matlab.h']]], - ['exti_5fimr_5fmr11_1054',['EXTI_IMR_MR11',['../group___peripheral___registers___bits___definition.html#ga68cfe8fe938fcb0fc6925bf493ccfaa7',1,'stm32f407xx_matlab.h']]], - ['exti_5fimr_5fmr11_5fmsk_1055',['EXTI_IMR_MR11_Msk',['../group___peripheral___registers___bits___definition.html#ga25a00372781fec24bbabb7d2aeca82bd',1,'stm32f407xx_matlab.h']]], - ['exti_5fimr_5fmr11_5fpos_1056',['EXTI_IMR_MR11_Pos',['../group___peripheral___registers___bits___definition.html#ga29cc04d8d5116420b5b63c2f7c6b98e3',1,'stm32f407xx_matlab.h']]], - ['exti_5fimr_5fmr12_1057',['EXTI_IMR_MR12',['../group___peripheral___registers___bits___definition.html#gad21caf923d2083fb106852493667c16e',1,'stm32f407xx_matlab.h']]], - ['exti_5fimr_5fmr12_5fmsk_1058',['EXTI_IMR_MR12_Msk',['../group___peripheral___registers___bits___definition.html#ga7c26fd0b40d6d66aec7cc5fff86f6720',1,'stm32f407xx_matlab.h']]], - ['exti_5fimr_5fmr12_5fpos_1059',['EXTI_IMR_MR12_Pos',['../group___peripheral___registers___bits___definition.html#gaddd5fe4e39d5ff13ad5d3a051ffd2b73',1,'stm32f407xx_matlab.h']]], - ['exti_5fimr_5fmr13_1060',['EXTI_IMR_MR13',['../group___peripheral___registers___bits___definition.html#ga5e1938a063c48d7d6504cb32f7965c0e',1,'stm32f407xx_matlab.h']]], - ['exti_5fimr_5fmr13_5fmsk_1061',['EXTI_IMR_MR13_Msk',['../group___peripheral___registers___bits___definition.html#gadf4095ebf9c75696a62d7bead70cc5cc',1,'stm32f407xx_matlab.h']]], - ['exti_5fimr_5fmr13_5fpos_1062',['EXTI_IMR_MR13_Pos',['../group___peripheral___registers___bits___definition.html#ga3658584854eb1f7c9ad43934e5cb9f2a',1,'stm32f407xx_matlab.h']]], - ['exti_5fimr_5fmr14_1063',['EXTI_IMR_MR14',['../group___peripheral___registers___bits___definition.html#gab8827cee06670f256bc8f6301bea9cab',1,'stm32f407xx_matlab.h']]], - ['exti_5fimr_5fmr14_5fmsk_1064',['EXTI_IMR_MR14_Msk',['../group___peripheral___registers___bits___definition.html#ga052609a42da3b6c6895f006e50c12ab6',1,'stm32f407xx_matlab.h']]], - ['exti_5fimr_5fmr14_5fpos_1065',['EXTI_IMR_MR14_Pos',['../group___peripheral___registers___bits___definition.html#ga05cb292831097d4790e00b89987cf5bb',1,'stm32f407xx_matlab.h']]], - ['exti_5fimr_5fmr15_1066',['EXTI_IMR_MR15',['../group___peripheral___registers___bits___definition.html#ga88d9990be7f8f9e530a9f930a365fa44',1,'stm32f407xx_matlab.h']]], - ['exti_5fimr_5fmr15_5fmsk_1067',['EXTI_IMR_MR15_Msk',['../group___peripheral___registers___bits___definition.html#ga27011a5c7488ed0273c821804ef6a27b',1,'stm32f407xx_matlab.h']]], - ['exti_5fimr_5fmr15_5fpos_1068',['EXTI_IMR_MR15_Pos',['../group___peripheral___registers___bits___definition.html#ga84e87a9c94dd2cdf7ea1851c2af7727b',1,'stm32f407xx_matlab.h']]], - ['exti_5fimr_5fmr16_1069',['EXTI_IMR_MR16',['../group___peripheral___registers___bits___definition.html#ga7419f78ed9044bdd237b452ef49e1b7f',1,'stm32f407xx_matlab.h']]], - ['exti_5fimr_5fmr16_5fmsk_1070',['EXTI_IMR_MR16_Msk',['../group___peripheral___registers___bits___definition.html#ga155179198c3735dd1e35baf733f1542e',1,'stm32f407xx_matlab.h']]], - ['exti_5fimr_5fmr16_5fpos_1071',['EXTI_IMR_MR16_Pos',['../group___peripheral___registers___bits___definition.html#ga6fc8dc837cd6326f1fb7fae42e56ef74',1,'stm32f407xx_matlab.h']]], - ['exti_5fimr_5fmr17_1072',['EXTI_IMR_MR17',['../group___peripheral___registers___bits___definition.html#ga4489fa85d1552b8f40faed93483a5d35',1,'stm32f407xx_matlab.h']]], - ['exti_5fimr_5fmr17_5fmsk_1073',['EXTI_IMR_MR17_Msk',['../group___peripheral___registers___bits___definition.html#gad6eb3bf08d4a51133e62dd719f2e48b8',1,'stm32f407xx_matlab.h']]], - ['exti_5fimr_5fmr17_5fpos_1074',['EXTI_IMR_MR17_Pos',['../group___peripheral___registers___bits___definition.html#gabbc90bbbbc4137c8af29df2fc0162ae5',1,'stm32f407xx_matlab.h']]], - ['exti_5fimr_5fmr18_1075',['EXTI_IMR_MR18',['../group___peripheral___registers___bits___definition.html#ga05e16f2cda40cca58a45458cc44d510f',1,'stm32f407xx_matlab.h']]], - ['exti_5fimr_5fmr18_5fmsk_1076',['EXTI_IMR_MR18_Msk',['../group___peripheral___registers___bits___definition.html#ga52a2709f4f9d2ccb8d63c36958517b26',1,'stm32f407xx_matlab.h']]], - ['exti_5fimr_5fmr18_5fpos_1077',['EXTI_IMR_MR18_Pos',['../group___peripheral___registers___bits___definition.html#ga9084142db0eac80226038ced74846aa8',1,'stm32f407xx_matlab.h']]], - ['exti_5fimr_5fmr19_1078',['EXTI_IMR_MR19',['../group___peripheral___registers___bits___definition.html#gad47f7a023cbba165dfb95845d3c8c55c',1,'stm32f407xx_matlab.h']]], - ['exti_5fimr_5fmr19_5fmsk_1079',['EXTI_IMR_MR19_Msk',['../group___peripheral___registers___bits___definition.html#gab55fbb64891a3120b3d5c53984abe6ca',1,'stm32f407xx_matlab.h']]], - ['exti_5fimr_5fmr19_5fpos_1080',['EXTI_IMR_MR19_Pos',['../group___peripheral___registers___bits___definition.html#ga92d1beae3a87cd1515fd1104bb2e0ac5',1,'stm32f407xx_matlab.h']]], - ['exti_5fimr_5fmr1_5fmsk_1081',['EXTI_IMR_MR1_Msk',['../group___peripheral___registers___bits___definition.html#gacadc6566dd71406d2d516785c4b776bd',1,'stm32f407xx_matlab.h']]], - ['exti_5fimr_5fmr1_5fpos_1082',['EXTI_IMR_MR1_Pos',['../group___peripheral___registers___bits___definition.html#ga27eb2217e842fa69573590793a1e6b38',1,'stm32f407xx_matlab.h']]], - ['exti_5fimr_5fmr2_1083',['EXTI_IMR_MR2',['../group___peripheral___registers___bits___definition.html#ga71604d1c29973c5e2bf69c8e94e89f67',1,'stm32f407xx_matlab.h']]], - ['exti_5fimr_5fmr20_1084',['EXTI_IMR_MR20',['../group___peripheral___registers___bits___definition.html#ga4aee679baf5820e1666b60e48a64cafa',1,'stm32f407xx_matlab.h']]], - ['exti_5fimr_5fmr20_5fmsk_1085',['EXTI_IMR_MR20_Msk',['../group___peripheral___registers___bits___definition.html#ga8e9bb3e1445d27d46816b0be57cbfbbd',1,'stm32f407xx_matlab.h']]], - ['exti_5fimr_5fmr20_5fpos_1086',['EXTI_IMR_MR20_Pos',['../group___peripheral___registers___bits___definition.html#gae8a252b7afd91a453cd613fca4792aed',1,'stm32f407xx_matlab.h']]], - ['exti_5fimr_5fmr21_1087',['EXTI_IMR_MR21',['../group___peripheral___registers___bits___definition.html#ga3cc7e64c45d273ca7396ac1e0ce38c36',1,'stm32f407xx_matlab.h']]], - ['exti_5fimr_5fmr21_5fmsk_1088',['EXTI_IMR_MR21_Msk',['../group___peripheral___registers___bits___definition.html#gae66e025fa607e21af5498613c7ec7ebf',1,'stm32f407xx_matlab.h']]], - ['exti_5fimr_5fmr21_5fpos_1089',['EXTI_IMR_MR21_Pos',['../group___peripheral___registers___bits___definition.html#ga777cbe130041b394e728de96fac11175',1,'stm32f407xx_matlab.h']]], - ['exti_5fimr_5fmr22_1090',['EXTI_IMR_MR22',['../group___peripheral___registers___bits___definition.html#ga2aec84941d816be18a1607b6ee25acb1',1,'stm32f407xx_matlab.h']]], - ['exti_5fimr_5fmr22_5fmsk_1091',['EXTI_IMR_MR22_Msk',['../group___peripheral___registers___bits___definition.html#ga20c62ffabf9a216bc5d682fc0f1ad5f6',1,'stm32f407xx_matlab.h']]], - ['exti_5fimr_5fmr22_5fpos_1092',['EXTI_IMR_MR22_Pos',['../group___peripheral___registers___bits___definition.html#ga83efcf05bd49c293779334f366a3e342',1,'stm32f407xx_matlab.h']]], - ['exti_5fimr_5fmr2_5fmsk_1093',['EXTI_IMR_MR2_Msk',['../group___peripheral___registers___bits___definition.html#ga183b9b9663a6aeec66f0238abbbf282f',1,'stm32f407xx_matlab.h']]], - ['exti_5fimr_5fmr2_5fpos_1094',['EXTI_IMR_MR2_Pos',['../group___peripheral___registers___bits___definition.html#ga58855e17d769f246e7422b3f875c85a2',1,'stm32f407xx_matlab.h']]], - ['exti_5fimr_5fmr3_1095',['EXTI_IMR_MR3',['../group___peripheral___registers___bits___definition.html#ga5edd42f9b2129c18cfa3c3598dcd1134',1,'stm32f407xx_matlab.h']]], - ['exti_5fimr_5fmr3_5fmsk_1096',['EXTI_IMR_MR3_Msk',['../group___peripheral___registers___bits___definition.html#ga9f6badc25c27d6185c0e560454384a90',1,'stm32f407xx_matlab.h']]], - ['exti_5fimr_5fmr3_5fpos_1097',['EXTI_IMR_MR3_Pos',['../group___peripheral___registers___bits___definition.html#gad0b0d4c04570bfe939843d7cb5bf15f6',1,'stm32f407xx_matlab.h']]], - ['exti_5fimr_5fmr4_1098',['EXTI_IMR_MR4',['../group___peripheral___registers___bits___definition.html#ga23e920ad334439cd2ad4d683054914e3',1,'stm32f407xx_matlab.h']]], - ['exti_5fimr_5fmr4_5fmsk_1099',['EXTI_IMR_MR4_Msk',['../group___peripheral___registers___bits___definition.html#ga64dbc3def48abe258dd1e1ecce481086',1,'stm32f407xx_matlab.h']]], - ['exti_5fimr_5fmr4_5fpos_1100',['EXTI_IMR_MR4_Pos',['../group___peripheral___registers___bits___definition.html#gae18a7ef85db4597309170659c7ff1e6c',1,'stm32f407xx_matlab.h']]], - ['exti_5fimr_5fmr5_1101',['EXTI_IMR_MR5',['../group___peripheral___registers___bits___definition.html#ga7cd3c5a2e4c4cb9b81e8965fcbf1c3a5',1,'stm32f407xx_matlab.h']]], - ['exti_5fimr_5fmr5_5fmsk_1102',['EXTI_IMR_MR5_Msk',['../group___peripheral___registers___bits___definition.html#ga18ca0d16b43ed78d36f52dd5ab0c21c2',1,'stm32f407xx_matlab.h']]], - ['exti_5fimr_5fmr5_5fpos_1103',['EXTI_IMR_MR5_Pos',['../group___peripheral___registers___bits___definition.html#ga01f6ecdcfdf234180e99e7d9c02affc7',1,'stm32f407xx_matlab.h']]], - ['exti_5fimr_5fmr6_1104',['EXTI_IMR_MR6',['../group___peripheral___registers___bits___definition.html#ga5533c8ec796e3bbc9dc4474376056e06',1,'stm32f407xx_matlab.h']]], - ['exti_5fimr_5fmr6_5fmsk_1105',['EXTI_IMR_MR6_Msk',['../group___peripheral___registers___bits___definition.html#ga6dcc5b70b0a599e944d99f53ac071e1a',1,'stm32f407xx_matlab.h']]], - ['exti_5fimr_5fmr6_5fpos_1106',['EXTI_IMR_MR6_Pos',['../group___peripheral___registers___bits___definition.html#gabc6874ec52a6b876dd48842a28d219ba',1,'stm32f407xx_matlab.h']]], - ['exti_5fimr_5fmr7_1107',['EXTI_IMR_MR7',['../group___peripheral___registers___bits___definition.html#gab620165d3fea1c564fcf1016805a1a8e',1,'stm32f407xx_matlab.h']]], - ['exti_5fimr_5fmr7_5fmsk_1108',['EXTI_IMR_MR7_Msk',['../group___peripheral___registers___bits___definition.html#gae41e117f93d5e426758ee40bd7d45755',1,'stm32f407xx_matlab.h']]], - ['exti_5fimr_5fmr7_5fpos_1109',['EXTI_IMR_MR7_Pos',['../group___peripheral___registers___bits___definition.html#gad1b52dd9408a254ec3ba436ede0e42fa',1,'stm32f407xx_matlab.h']]], - ['exti_5fimr_5fmr8_1110',['EXTI_IMR_MR8',['../group___peripheral___registers___bits___definition.html#ga88e8b274e4398fdcb1c68da2b6320d5b',1,'stm32f407xx_matlab.h']]], - ['exti_5fimr_5fmr8_5fmsk_1111',['EXTI_IMR_MR8_Msk',['../group___peripheral___registers___bits___definition.html#ga02a618dd052d47d30cadf578ee58e416',1,'stm32f407xx_matlab.h']]], - ['exti_5fimr_5fmr8_5fpos_1112',['EXTI_IMR_MR8_Pos',['../group___peripheral___registers___bits___definition.html#gad1ad8042623ea52664eb00b43e35dcb7',1,'stm32f407xx_matlab.h']]], - ['exti_5fimr_5fmr9_1113',['EXTI_IMR_MR9',['../group___peripheral___registers___bits___definition.html#gaf4d177dcf33bb9a34f8590ec509746e8',1,'stm32f407xx_matlab.h']]], - ['exti_5fimr_5fmr9_5fmsk_1114',['EXTI_IMR_MR9_Msk',['../group___peripheral___registers___bits___definition.html#ga7433c8c28acd006d4a71e803f6d95de3',1,'stm32f407xx_matlab.h']]], - ['exti_5fimr_5fmr9_5fpos_1115',['EXTI_IMR_MR9_Pos',['../group___peripheral___registers___bits___definition.html#ga8b9b5e7500420b3ce5a2b711ed73fa50',1,'stm32f407xx_matlab.h']]], - ['exti_5fpr_5fpr0_1116',['EXTI_PR_PR0',['../group___peripheral___registers___bits___definition.html#ga6da1c8a465606de1f90a74d369fbf25a',1,'stm32f407xx_matlab.h']]], - ['exti_5fpr_5fpr0_5fmsk_1117',['EXTI_PR_PR0_Msk',['../group___peripheral___registers___bits___definition.html#ga6e52c51a9d888231a788288e42bb8596',1,'stm32f407xx_matlab.h']]], - ['exti_5fpr_5fpr0_5fpos_1118',['EXTI_PR_PR0_Pos',['../group___peripheral___registers___bits___definition.html#gad67b1832b8c6ebd37c07d774bf7b79c8',1,'stm32f407xx_matlab.h']]], - ['exti_5fpr_5fpr1_1119',['EXTI_PR_PR1',['../group___peripheral___registers___bits___definition.html#ga4b9b5f97edeccf442998a65b19e77f25',1,'stm32f407xx_matlab.h']]], - ['exti_5fpr_5fpr10_1120',['EXTI_PR_PR10',['../group___peripheral___registers___bits___definition.html#ga1ef8e9c691b95763007ed228e98fa108',1,'stm32f407xx_matlab.h']]], - ['exti_5fpr_5fpr10_5fmsk_1121',['EXTI_PR_PR10_Msk',['../group___peripheral___registers___bits___definition.html#ga19900075592fba3fc4a6641c5a44a4b4',1,'stm32f407xx_matlab.h']]], - ['exti_5fpr_5fpr10_5fpos_1122',['EXTI_PR_PR10_Pos',['../group___peripheral___registers___bits___definition.html#ga3f38ede7f65d599654716b9c70119997',1,'stm32f407xx_matlab.h']]], - ['exti_5fpr_5fpr11_1123',['EXTI_PR_PR11',['../group___peripheral___registers___bits___definition.html#ga144f1a41abb7b87a1619c15ba5fb548b',1,'stm32f407xx_matlab.h']]], - ['exti_5fpr_5fpr11_5fmsk_1124',['EXTI_PR_PR11_Msk',['../group___peripheral___registers___bits___definition.html#ga80e7dba5b45bb3fa090607a33ea4b4b7',1,'stm32f407xx_matlab.h']]], - ['exti_5fpr_5fpr11_5fpos_1125',['EXTI_PR_PR11_Pos',['../group___peripheral___registers___bits___definition.html#gaf0b7515b407f5831dc120540379ab0ee',1,'stm32f407xx_matlab.h']]], - ['exti_5fpr_5fpr12_1126',['EXTI_PR_PR12',['../group___peripheral___registers___bits___definition.html#gae1a68025056b8c84bb13635af5e2a07c',1,'stm32f407xx_matlab.h']]], - ['exti_5fpr_5fpr12_5fmsk_1127',['EXTI_PR_PR12_Msk',['../group___peripheral___registers___bits___definition.html#ga0a607029be3ca6159090afbf66b84d88',1,'stm32f407xx_matlab.h']]], - ['exti_5fpr_5fpr12_5fpos_1128',['EXTI_PR_PR12_Pos',['../group___peripheral___registers___bits___definition.html#gabe319cbf2bf25f1854993b7e9a88c02e',1,'stm32f407xx_matlab.h']]], - ['exti_5fpr_5fpr13_1129',['EXTI_PR_PR13',['../group___peripheral___registers___bits___definition.html#ga3471c79d5b19813785387504a1a5f0c4',1,'stm32f407xx_matlab.h']]], - ['exti_5fpr_5fpr13_5fmsk_1130',['EXTI_PR_PR13_Msk',['../group___peripheral___registers___bits___definition.html#ga46b3cd3e008be5d766a085378dbde61e',1,'stm32f407xx_matlab.h']]], - ['exti_5fpr_5fpr13_5fpos_1131',['EXTI_PR_PR13_Pos',['../group___peripheral___registers___bits___definition.html#gaa74c6b6143b3874744573c9ab8f30f65',1,'stm32f407xx_matlab.h']]], - ['exti_5fpr_5fpr14_1132',['EXTI_PR_PR14',['../group___peripheral___registers___bits___definition.html#gae5396ec2dbbee9d7585224fa12273598',1,'stm32f407xx_matlab.h']]], - ['exti_5fpr_5fpr14_5fmsk_1133',['EXTI_PR_PR14_Msk',['../group___peripheral___registers___bits___definition.html#ga845983f32b8eccfafede2ece6a9371a1',1,'stm32f407xx_matlab.h']]], - ['exti_5fpr_5fpr14_5fpos_1134',['EXTI_PR_PR14_Pos',['../group___peripheral___registers___bits___definition.html#gada52a67e5e44c06a2e40c3d4c721b345',1,'stm32f407xx_matlab.h']]], - ['exti_5fpr_5fpr15_1135',['EXTI_PR_PR15',['../group___peripheral___registers___bits___definition.html#ga149f9d9d6c1aab867734b59db1117c41',1,'stm32f407xx_matlab.h']]], - ['exti_5fpr_5fpr15_5fmsk_1136',['EXTI_PR_PR15_Msk',['../group___peripheral___registers___bits___definition.html#gac665a7df31dbb829ee5e8c92b35d1e94',1,'stm32f407xx_matlab.h']]], - ['exti_5fpr_5fpr15_5fpos_1137',['EXTI_PR_PR15_Pos',['../group___peripheral___registers___bits___definition.html#ga9d396fd4e0a34ebb0d44d2eb53daa753',1,'stm32f407xx_matlab.h']]], - ['exti_5fpr_5fpr16_1138',['EXTI_PR_PR16',['../group___peripheral___registers___bits___definition.html#gaa47e5b07d5a407198e09f05262f18bba',1,'stm32f407xx_matlab.h']]], - ['exti_5fpr_5fpr16_5fmsk_1139',['EXTI_PR_PR16_Msk',['../group___peripheral___registers___bits___definition.html#ga1577079526c7f1959e2e0c6c3dd8a4e4',1,'stm32f407xx_matlab.h']]], - ['exti_5fpr_5fpr16_5fpos_1140',['EXTI_PR_PR16_Pos',['../group___peripheral___registers___bits___definition.html#ga71810ea68a9e4297e245dacdfe77855a',1,'stm32f407xx_matlab.h']]], - ['exti_5fpr_5fpr17_1141',['EXTI_PR_PR17',['../group___peripheral___registers___bits___definition.html#gadbc7d82eb61e2adf0a955ef0cc97690f',1,'stm32f407xx_matlab.h']]], - ['exti_5fpr_5fpr17_5fmsk_1142',['EXTI_PR_PR17_Msk',['../group___peripheral___registers___bits___definition.html#ga60b0021b076cb2e50a546abdc74ff497',1,'stm32f407xx_matlab.h']]], - ['exti_5fpr_5fpr17_5fpos_1143',['EXTI_PR_PR17_Pos',['../group___peripheral___registers___bits___definition.html#ga6c42d3340997c553862f81db64944af9',1,'stm32f407xx_matlab.h']]], - ['exti_5fpr_5fpr18_1144',['EXTI_PR_PR18',['../group___peripheral___registers___bits___definition.html#ga541810a93fbf4cdd9b39f2717f37240d',1,'stm32f407xx_matlab.h']]], - ['exti_5fpr_5fpr18_5fmsk_1145',['EXTI_PR_PR18_Msk',['../group___peripheral___registers___bits___definition.html#ga09184330e3d3e7839d58dec6b07c284a',1,'stm32f407xx_matlab.h']]], - ['exti_5fpr_5fpr18_5fpos_1146',['EXTI_PR_PR18_Pos',['../group___peripheral___registers___bits___definition.html#ga65cfa57b6c19a9a31eb05adfbb24399a',1,'stm32f407xx_matlab.h']]], - ['exti_5fpr_5fpr19_1147',['EXTI_PR_PR19',['../group___peripheral___registers___bits___definition.html#ga41e43af631a30492e09e5fd5c50f47f5',1,'stm32f407xx_matlab.h']]], - ['exti_5fpr_5fpr19_5fmsk_1148',['EXTI_PR_PR19_Msk',['../group___peripheral___registers___bits___definition.html#gae2b3167c29bb083e4c0e025846069a78',1,'stm32f407xx_matlab.h']]], - ['exti_5fpr_5fpr19_5fpos_1149',['EXTI_PR_PR19_Pos',['../group___peripheral___registers___bits___definition.html#ga9a38e5f6a0896bb0c6c2f3e32a5d51f8',1,'stm32f407xx_matlab.h']]], - ['exti_5fpr_5fpr1_5fmsk_1150',['EXTI_PR_PR1_Msk',['../group___peripheral___registers___bits___definition.html#gaa0ea95730ba8514076cc76945a01d850',1,'stm32f407xx_matlab.h']]], - ['exti_5fpr_5fpr1_5fpos_1151',['EXTI_PR_PR1_Pos',['../group___peripheral___registers___bits___definition.html#gac7adebcc32984cb835d47179d34206eb',1,'stm32f407xx_matlab.h']]], - ['exti_5fpr_5fpr2_1152',['EXTI_PR_PR2',['../group___peripheral___registers___bits___definition.html#ga085d2105381752a0aadc9be5a93ea665',1,'stm32f407xx_matlab.h']]], - ['exti_5fpr_5fpr20_1153',['EXTI_PR_PR20',['../group___peripheral___registers___bits___definition.html#ga39358e6261a245eba447dfc1a1842e32',1,'stm32f407xx_matlab.h']]], - ['exti_5fpr_5fpr20_5fmsk_1154',['EXTI_PR_PR20_Msk',['../group___peripheral___registers___bits___definition.html#gac02bf4106a2d978a81fc825c808eace4',1,'stm32f407xx_matlab.h']]], - ['exti_5fpr_5fpr20_5fpos_1155',['EXTI_PR_PR20_Pos',['../group___peripheral___registers___bits___definition.html#gac3d5ef04e855f2eb705305eba6cf00b9',1,'stm32f407xx_matlab.h']]], - ['exti_5fpr_5fpr21_1156',['EXTI_PR_PR21',['../group___peripheral___registers___bits___definition.html#gac14b609a68b5c4cb4a20fb24e34954df',1,'stm32f407xx_matlab.h']]], - ['exti_5fpr_5fpr21_5fmsk_1157',['EXTI_PR_PR21_Msk',['../group___peripheral___registers___bits___definition.html#gabe3b7c51abb06113eb6b53ca2c963fba',1,'stm32f407xx_matlab.h']]], - ['exti_5fpr_5fpr21_5fpos_1158',['EXTI_PR_PR21_Pos',['../group___peripheral___registers___bits___definition.html#gad693094b03aec71eeca641ef0739d950',1,'stm32f407xx_matlab.h']]], - ['exti_5fpr_5fpr22_1159',['EXTI_PR_PR22',['../group___peripheral___registers___bits___definition.html#ga8199f21c468deeb2685865c26770ac07',1,'stm32f407xx_matlab.h']]], - ['exti_5fpr_5fpr22_5fmsk_1160',['EXTI_PR_PR22_Msk',['../group___peripheral___registers___bits___definition.html#gaa13b7a89ed2d6deef9017757d311e52a',1,'stm32f407xx_matlab.h']]], - ['exti_5fpr_5fpr22_5fpos_1161',['EXTI_PR_PR22_Pos',['../group___peripheral___registers___bits___definition.html#ga9d26bbce3e69e8c80b67e81db99cc2ff',1,'stm32f407xx_matlab.h']]], - ['exti_5fpr_5fpr2_5fmsk_1162',['EXTI_PR_PR2_Msk',['../group___peripheral___registers___bits___definition.html#gaa105697635cbab9ccf5f96efc9feec0d',1,'stm32f407xx_matlab.h']]], - ['exti_5fpr_5fpr2_5fpos_1163',['EXTI_PR_PR2_Pos',['../group___peripheral___registers___bits___definition.html#gaefa65f5976eeb883b977b391e3fbb690',1,'stm32f407xx_matlab.h']]], - ['exti_5fpr_5fpr3_1164',['EXTI_PR_PR3',['../group___peripheral___registers___bits___definition.html#ga064dab3e0d5689b92125713100555ce0',1,'stm32f407xx_matlab.h']]], - ['exti_5fpr_5fpr3_5fmsk_1165',['EXTI_PR_PR3_Msk',['../group___peripheral___registers___bits___definition.html#gacbe8a3ee648b4cf47f51e435b8644cee',1,'stm32f407xx_matlab.h']]], - ['exti_5fpr_5fpr3_5fpos_1166',['EXTI_PR_PR3_Pos',['../group___peripheral___registers___bits___definition.html#gad56d3f9d10fd4c75bf4ba756e3778ea0',1,'stm32f407xx_matlab.h']]], - ['exti_5fpr_5fpr4_1167',['EXTI_PR_PR4',['../group___peripheral___registers___bits___definition.html#ga14f73b3693b3353a006d360cb8fd2ddc',1,'stm32f407xx_matlab.h']]], - ['exti_5fpr_5fpr4_5fmsk_1168',['EXTI_PR_PR4_Msk',['../group___peripheral___registers___bits___definition.html#ga9465307df267001826deb47a946dab61',1,'stm32f407xx_matlab.h']]], - ['exti_5fpr_5fpr4_5fpos_1169',['EXTI_PR_PR4_Pos',['../group___peripheral___registers___bits___definition.html#ga58443521d982443a49db3fb2c273f5e4',1,'stm32f407xx_matlab.h']]], - ['exti_5fpr_5fpr5_1170',['EXTI_PR_PR5',['../group___peripheral___registers___bits___definition.html#ga319e167fa6e112061997d9a8d79f02f8',1,'stm32f407xx_matlab.h']]], - ['exti_5fpr_5fpr5_5fmsk_1171',['EXTI_PR_PR5_Msk',['../group___peripheral___registers___bits___definition.html#ga7b096f7d09eed26b05531f8b0dbe239c',1,'stm32f407xx_matlab.h']]], - ['exti_5fpr_5fpr5_5fpos_1172',['EXTI_PR_PR5_Pos',['../group___peripheral___registers___bits___definition.html#gab011cd54f79dd8093ed093c53f9a69f5',1,'stm32f407xx_matlab.h']]], - ['exti_5fpr_5fpr6_1173',['EXTI_PR_PR6',['../group___peripheral___registers___bits___definition.html#gaf6f47cd1f602692258985784ed5e8e76',1,'stm32f407xx_matlab.h']]], - ['exti_5fpr_5fpr6_5fmsk_1174',['EXTI_PR_PR6_Msk',['../group___peripheral___registers___bits___definition.html#gae216f090307338513e0c48b792ff4380',1,'stm32f407xx_matlab.h']]], - ['exti_5fpr_5fpr6_5fpos_1175',['EXTI_PR_PR6_Pos',['../group___peripheral___registers___bits___definition.html#ga348bfafc8c5751e74b93c27f2ddce116',1,'stm32f407xx_matlab.h']]], - ['exti_5fpr_5fpr7_1176',['EXTI_PR_PR7',['../group___peripheral___registers___bits___definition.html#gaa17ea7e3fb89e98fd6a232f453fcff9e',1,'stm32f407xx_matlab.h']]], - ['exti_5fpr_5fpr7_5fmsk_1177',['EXTI_PR_PR7_Msk',['../group___peripheral___registers___bits___definition.html#ga81bf1c350de28d01e9d252a2a7907a1c',1,'stm32f407xx_matlab.h']]], - ['exti_5fpr_5fpr7_5fpos_1178',['EXTI_PR_PR7_Pos',['../group___peripheral___registers___bits___definition.html#ga41fd7463743a65921d47e3e888e22fbf',1,'stm32f407xx_matlab.h']]], - ['exti_5fpr_5fpr8_1179',['EXTI_PR_PR8',['../group___peripheral___registers___bits___definition.html#gaa82e0dcb4961a32a9b7ebdf30493156d',1,'stm32f407xx_matlab.h']]], - ['exti_5fpr_5fpr8_5fmsk_1180',['EXTI_PR_PR8_Msk',['../group___peripheral___registers___bits___definition.html#gabf15f6df00912ea82ed99154c1824543',1,'stm32f407xx_matlab.h']]], - ['exti_5fpr_5fpr8_5fpos_1181',['EXTI_PR_PR8_Pos',['../group___peripheral___registers___bits___definition.html#ga06e264ce486fde316beef4d01b07377d',1,'stm32f407xx_matlab.h']]], - ['exti_5fpr_5fpr9_1182',['EXTI_PR_PR9',['../group___peripheral___registers___bits___definition.html#ga2fcc64f03d79af531febc077f45c48eb',1,'stm32f407xx_matlab.h']]], - ['exti_5fpr_5fpr9_5fmsk_1183',['EXTI_PR_PR9_Msk',['../group___peripheral___registers___bits___definition.html#gaf5c48dd0cba2bfc3f1cbae965d145019',1,'stm32f407xx_matlab.h']]], - ['exti_5fpr_5fpr9_5fpos_1184',['EXTI_PR_PR9_Pos',['../group___peripheral___registers___bits___definition.html#ga74df770efeeac2a51b21229994b265e8',1,'stm32f407xx_matlab.h']]], - ['exti_5frtsr_5ftr0_1185',['EXTI_RTSR_TR0',['../group___peripheral___registers___bits___definition.html#gadb1823a87cd797a6066681a3256cecc6',1,'stm32f407xx_matlab.h']]], - ['exti_5frtsr_5ftr0_5fmsk_1186',['EXTI_RTSR_TR0_Msk',['../group___peripheral___registers___bits___definition.html#ga2b3f74a67ed2871290e5cee5ec27e487',1,'stm32f407xx_matlab.h']]], - ['exti_5frtsr_5ftr0_5fpos_1187',['EXTI_RTSR_TR0_Pos',['../group___peripheral___registers___bits___definition.html#gaa359160d5aba50c4aff40330fd99d426',1,'stm32f407xx_matlab.h']]], - ['exti_5frtsr_5ftr1_1188',['EXTI_RTSR_TR1',['../group___peripheral___registers___bits___definition.html#ga1c42cc3763c52d1061b32219fc441566',1,'stm32f407xx_matlab.h']]], - ['exti_5frtsr_5ftr10_1189',['EXTI_RTSR_TR10',['../group___peripheral___registers___bits___definition.html#gaa29df7ddbd067889992eb60ecddce0e4',1,'stm32f407xx_matlab.h']]], - ['exti_5frtsr_5ftr10_5fmsk_1190',['EXTI_RTSR_TR10_Msk',['../group___peripheral___registers___bits___definition.html#ga12717df4fef207dd689f240bbb23cedf',1,'stm32f407xx_matlab.h']]], - ['exti_5frtsr_5ftr10_5fpos_1191',['EXTI_RTSR_TR10_Pos',['../group___peripheral___registers___bits___definition.html#gaf19c55236009d4d88273be1fe6d17b69',1,'stm32f407xx_matlab.h']]], - ['exti_5frtsr_5ftr11_1192',['EXTI_RTSR_TR11',['../group___peripheral___registers___bits___definition.html#ga8cf7a92cdb61b3f8cf6eec9513317ab7',1,'stm32f407xx_matlab.h']]], - ['exti_5frtsr_5ftr11_5fmsk_1193',['EXTI_RTSR_TR11_Msk',['../group___peripheral___registers___bits___definition.html#ga36a3f679be0d89926b127c4b293111e2',1,'stm32f407xx_matlab.h']]], - ['exti_5frtsr_5ftr11_5fpos_1194',['EXTI_RTSR_TR11_Pos',['../group___peripheral___registers___bits___definition.html#ga7f11477d08556852c4cf210f75d11920',1,'stm32f407xx_matlab.h']]], - ['exti_5frtsr_5ftr12_1195',['EXTI_RTSR_TR12',['../group___peripheral___registers___bits___definition.html#ga0423be12bfb13f34eec9656d6d274e04',1,'stm32f407xx_matlab.h']]], - ['exti_5frtsr_5ftr12_5fmsk_1196',['EXTI_RTSR_TR12_Msk',['../group___peripheral___registers___bits___definition.html#gab4507125ae8a435b97fe643f73e6492e',1,'stm32f407xx_matlab.h']]], - ['exti_5frtsr_5ftr12_5fpos_1197',['EXTI_RTSR_TR12_Pos',['../group___peripheral___registers___bits___definition.html#gaf8b0314682ff50f85bd8d5570fb6935a',1,'stm32f407xx_matlab.h']]], - ['exti_5frtsr_5ftr13_1198',['EXTI_RTSR_TR13',['../group___peripheral___registers___bits___definition.html#ga5d5ef451fd76dc0fa9c76d7c520d8f12',1,'stm32f407xx_matlab.h']]], - ['exti_5frtsr_5ftr13_5fmsk_1199',['EXTI_RTSR_TR13_Msk',['../group___peripheral___registers___bits___definition.html#ga799f99b4edc9604b38ab1f12e0cf9cae',1,'stm32f407xx_matlab.h']]], - ['exti_5frtsr_5ftr13_5fpos_1200',['EXTI_RTSR_TR13_Pos',['../group___peripheral___registers___bits___definition.html#ga20176d8fa4181b22a833e1598e96b153',1,'stm32f407xx_matlab.h']]], - ['exti_5frtsr_5ftr14_1201',['EXTI_RTSR_TR14',['../group___peripheral___registers___bits___definition.html#ga95b0d883fa0fbc49105bda5596463cda',1,'stm32f407xx_matlab.h']]], - ['exti_5frtsr_5ftr14_5fmsk_1202',['EXTI_RTSR_TR14_Msk',['../group___peripheral___registers___bits___definition.html#ga42533490cce0d8d3ff55a2d6ad8c24ee',1,'stm32f407xx_matlab.h']]], - ['exti_5frtsr_5ftr14_5fpos_1203',['EXTI_RTSR_TR14_Pos',['../group___peripheral___registers___bits___definition.html#ga2e76cfdc7657907d423ba90dcac7bc90',1,'stm32f407xx_matlab.h']]], - ['exti_5frtsr_5ftr15_1204',['EXTI_RTSR_TR15',['../group___peripheral___registers___bits___definition.html#ga4fe54b09102a18676829c0bafb0aead2',1,'stm32f407xx_matlab.h']]], - ['exti_5frtsr_5ftr15_5fmsk_1205',['EXTI_RTSR_TR15_Msk',['../group___peripheral___registers___bits___definition.html#ga3ffbcdf64f7de2427560316706ddc8c1',1,'stm32f407xx_matlab.h']]], - ['exti_5frtsr_5ftr15_5fpos_1206',['EXTI_RTSR_TR15_Pos',['../group___peripheral___registers___bits___definition.html#gaa62a698b0b47384cd72f49ebb9f17f4c',1,'stm32f407xx_matlab.h']]], - ['exti_5frtsr_5ftr16_1207',['EXTI_RTSR_TR16',['../group___peripheral___registers___bits___definition.html#gae8e4fb52990f0fa3fb9bed5b74f1a589',1,'stm32f407xx_matlab.h']]], - ['exti_5frtsr_5ftr16_5fmsk_1208',['EXTI_RTSR_TR16_Msk',['../group___peripheral___registers___bits___definition.html#gad883a3a53902664492c684a6dd435d33',1,'stm32f407xx_matlab.h']]], - ['exti_5frtsr_5ftr16_5fpos_1209',['EXTI_RTSR_TR16_Pos',['../group___peripheral___registers___bits___definition.html#ga5c280314b145321c6a62ce2764d1fd59',1,'stm32f407xx_matlab.h']]], - ['exti_5frtsr_5ftr17_1210',['EXTI_RTSR_TR17',['../group___peripheral___registers___bits___definition.html#gad0a8fcb63516a4ed0d91b556f696f806',1,'stm32f407xx_matlab.h']]], - ['exti_5frtsr_5ftr17_5fmsk_1211',['EXTI_RTSR_TR17_Msk',['../group___peripheral___registers___bits___definition.html#ga42283a804716a4de1910afd032b87681',1,'stm32f407xx_matlab.h']]], - ['exti_5frtsr_5ftr17_5fpos_1212',['EXTI_RTSR_TR17_Pos',['../group___peripheral___registers___bits___definition.html#ga47fa1d5d96ea124413c3b81b9c10f75f',1,'stm32f407xx_matlab.h']]], - ['exti_5frtsr_5ftr18_1213',['EXTI_RTSR_TR18',['../group___peripheral___registers___bits___definition.html#gaca4223b8c4bc8726ac96ec64837f7b62',1,'stm32f407xx_matlab.h']]], - ['exti_5frtsr_5ftr18_5fmsk_1214',['EXTI_RTSR_TR18_Msk',['../group___peripheral___registers___bits___definition.html#ga708076360f04650ae4bfdd6695caa617',1,'stm32f407xx_matlab.h']]], - ['exti_5frtsr_5ftr18_5fpos_1215',['EXTI_RTSR_TR18_Pos',['../group___peripheral___registers___bits___definition.html#ga49afa76eab5b3a7d5e5640fced73047c',1,'stm32f407xx_matlab.h']]], - ['exti_5frtsr_5ftr19_1216',['EXTI_RTSR_TR19',['../group___peripheral___registers___bits___definition.html#ga40a722b0c36e832f619b2136f1510b3e',1,'stm32f407xx_matlab.h']]], - ['exti_5frtsr_5ftr19_5fmsk_1217',['EXTI_RTSR_TR19_Msk',['../group___peripheral___registers___bits___definition.html#gaab40d59af38c6adbe9621b8ab68dbdbe',1,'stm32f407xx_matlab.h']]], - ['exti_5frtsr_5ftr19_5fpos_1218',['EXTI_RTSR_TR19_Pos',['../group___peripheral___registers___bits___definition.html#gaef9bfa9cb8df10ec1e3c2dd50235231c',1,'stm32f407xx_matlab.h']]], - ['exti_5frtsr_5ftr1_5fmsk_1219',['EXTI_RTSR_TR1_Msk',['../group___peripheral___registers___bits___definition.html#ga57ba4871b93492e5e8c846f2833f9da1',1,'stm32f407xx_matlab.h']]], - ['exti_5frtsr_5ftr1_5fpos_1220',['EXTI_RTSR_TR1_Pos',['../group___peripheral___registers___bits___definition.html#ga099233be3061fa5c0e44cbf3e20b6394',1,'stm32f407xx_matlab.h']]], - ['exti_5frtsr_5ftr2_1221',['EXTI_RTSR_TR2',['../group___peripheral___registers___bits___definition.html#ga1c073b519f09b130e4ab4039823e290c',1,'stm32f407xx_matlab.h']]], - ['exti_5frtsr_5ftr20_1222',['EXTI_RTSR_TR20',['../group___peripheral___registers___bits___definition.html#ga076319b89121213ea97b4767182b17bd',1,'stm32f407xx_matlab.h']]], - ['exti_5frtsr_5ftr20_5fmsk_1223',['EXTI_RTSR_TR20_Msk',['../group___peripheral___registers___bits___definition.html#gaf3497416ddbe940f3f87bdbe94dcb423',1,'stm32f407xx_matlab.h']]], - ['exti_5frtsr_5ftr20_5fpos_1224',['EXTI_RTSR_TR20_Pos',['../group___peripheral___registers___bits___definition.html#ga825c9ea20abb9a733bc90b94440fbc63',1,'stm32f407xx_matlab.h']]], - ['exti_5frtsr_5ftr21_1225',['EXTI_RTSR_TR21',['../group___peripheral___registers___bits___definition.html#ga5b1fd6472c3739cb5d21ba25bb6f745d',1,'stm32f407xx_matlab.h']]], - ['exti_5frtsr_5ftr21_5fmsk_1226',['EXTI_RTSR_TR21_Msk',['../group___peripheral___registers___bits___definition.html#ga0acfd045c5ef66801c4f70a7a529a210',1,'stm32f407xx_matlab.h']]], - ['exti_5frtsr_5ftr21_5fpos_1227',['EXTI_RTSR_TR21_Pos',['../group___peripheral___registers___bits___definition.html#ga6a92f33d68f20f61d92563404305ba35',1,'stm32f407xx_matlab.h']]], - ['exti_5frtsr_5ftr22_1228',['EXTI_RTSR_TR22',['../group___peripheral___registers___bits___definition.html#gaca577c5c1742e043ed5e0a2ffcc88f82',1,'stm32f407xx_matlab.h']]], - ['exti_5frtsr_5ftr22_5fmsk_1229',['EXTI_RTSR_TR22_Msk',['../group___peripheral___registers___bits___definition.html#gadcf74a99ed3d1bc23d06f4e6d634b46f',1,'stm32f407xx_matlab.h']]], - ['exti_5frtsr_5ftr22_5fpos_1230',['EXTI_RTSR_TR22_Pos',['../group___peripheral___registers___bits___definition.html#gad9b6c8e3b151388284c11fad135c06f3',1,'stm32f407xx_matlab.h']]], - ['exti_5frtsr_5ftr2_5fmsk_1231',['EXTI_RTSR_TR2_Msk',['../group___peripheral___registers___bits___definition.html#gadbecd9a805326155030f357bc2d70046',1,'stm32f407xx_matlab.h']]], - ['exti_5frtsr_5ftr2_5fpos_1232',['EXTI_RTSR_TR2_Pos',['../group___peripheral___registers___bits___definition.html#ga22b2187bec09d19b2b79382c25ff3b4b',1,'stm32f407xx_matlab.h']]], - ['exti_5frtsr_5ftr3_1233',['EXTI_RTSR_TR3',['../group___peripheral___registers___bits___definition.html#ga090f295579a774c215585a55e5066b11',1,'stm32f407xx_matlab.h']]], - ['exti_5frtsr_5ftr3_5fmsk_1234',['EXTI_RTSR_TR3_Msk',['../group___peripheral___registers___bits___definition.html#ga560d856b177ddb7b90e101caf3ce66be',1,'stm32f407xx_matlab.h']]], - ['exti_5frtsr_5ftr3_5fpos_1235',['EXTI_RTSR_TR3_Pos',['../group___peripheral___registers___bits___definition.html#gaeae95954e4c5e25f225d3cad0e2b2362',1,'stm32f407xx_matlab.h']]], - ['exti_5frtsr_5ftr4_1236',['EXTI_RTSR_TR4',['../group___peripheral___registers___bits___definition.html#gabce4722e99e3f44d40bfb6afb63444cc',1,'stm32f407xx_matlab.h']]], - ['exti_5frtsr_5ftr4_5fmsk_1237',['EXTI_RTSR_TR4_Msk',['../group___peripheral___registers___bits___definition.html#ga795eff3140a1d0c0e1fcfc03b2fa5860',1,'stm32f407xx_matlab.h']]], - ['exti_5frtsr_5ftr4_5fpos_1238',['EXTI_RTSR_TR4_Pos',['../group___peripheral___registers___bits___definition.html#gaa95865d62fde25381efad4f0c38cd8bd',1,'stm32f407xx_matlab.h']]], - ['exti_5frtsr_5ftr5_1239',['EXTI_RTSR_TR5',['../group___peripheral___registers___bits___definition.html#gac57b970ebc88f7bb015119ece9dd32de',1,'stm32f407xx_matlab.h']]], - ['exti_5frtsr_5ftr5_5fmsk_1240',['EXTI_RTSR_TR5_Msk',['../group___peripheral___registers___bits___definition.html#ga65a7c4c35c85b3e922e1df8447dd8e6d',1,'stm32f407xx_matlab.h']]], - ['exti_5frtsr_5ftr5_5fpos_1241',['EXTI_RTSR_TR5_Pos',['../group___peripheral___registers___bits___definition.html#ga29eade4e6218042bad165fd8cb162662',1,'stm32f407xx_matlab.h']]], - ['exti_5frtsr_5ftr6_1242',['EXTI_RTSR_TR6',['../group___peripheral___registers___bits___definition.html#gaccc2212ce653d34cf48446ae0a68bed6',1,'stm32f407xx_matlab.h']]], - ['exti_5frtsr_5ftr6_5fmsk_1243',['EXTI_RTSR_TR6_Msk',['../group___peripheral___registers___bits___definition.html#ga85d1a629b7cde96375b82803c46cfcb4',1,'stm32f407xx_matlab.h']]], - ['exti_5frtsr_5ftr6_5fpos_1244',['EXTI_RTSR_TR6_Pos',['../group___peripheral___registers___bits___definition.html#ga7a5fd949f067c605127932367ba4dad5',1,'stm32f407xx_matlab.h']]], - ['exti_5frtsr_5ftr7_1245',['EXTI_RTSR_TR7',['../group___peripheral___registers___bits___definition.html#gad380a0bc59524f4a0846a0b91d3c65c1',1,'stm32f407xx_matlab.h']]], - ['exti_5frtsr_5ftr7_5fmsk_1246',['EXTI_RTSR_TR7_Msk',['../group___peripheral___registers___bits___definition.html#gadbc9d6a9f75fdff045e4806edad97b47',1,'stm32f407xx_matlab.h']]], - ['exti_5frtsr_5ftr7_5fpos_1247',['EXTI_RTSR_TR7_Pos',['../group___peripheral___registers___bits___definition.html#ga79f320ed539b225c1e4f50e3cfb43100',1,'stm32f407xx_matlab.h']]], - ['exti_5frtsr_5ftr8_1248',['EXTI_RTSR_TR8',['../group___peripheral___registers___bits___definition.html#ga26cd6a5115b0bbe113f39545bff1ee39',1,'stm32f407xx_matlab.h']]], - ['exti_5frtsr_5ftr8_5fmsk_1249',['EXTI_RTSR_TR8_Msk',['../group___peripheral___registers___bits___definition.html#ga16c3b77b33079caf74151ade9fbc3b82',1,'stm32f407xx_matlab.h']]], - ['exti_5frtsr_5ftr8_5fpos_1250',['EXTI_RTSR_TR8_Pos',['../group___peripheral___registers___bits___definition.html#ga1f9bcf9229eced0f5101842fd9585e40',1,'stm32f407xx_matlab.h']]], - ['exti_5frtsr_5ftr9_1251',['EXTI_RTSR_TR9',['../group___peripheral___registers___bits___definition.html#ga3127246b2db3571b00c6af2453941d17',1,'stm32f407xx_matlab.h']]], - ['exti_5frtsr_5ftr9_5fmsk_1252',['EXTI_RTSR_TR9_Msk',['../group___peripheral___registers___bits___definition.html#ga394b28a010f7937178112dd11c7edf7b',1,'stm32f407xx_matlab.h']]], - ['exti_5frtsr_5ftr9_5fpos_1253',['EXTI_RTSR_TR9_Pos',['../group___peripheral___registers___bits___definition.html#ga3f3c856ba7076de4742cea9494d2d97b',1,'stm32f407xx_matlab.h']]], - ['exti_5fswier_5fswier0_1254',['EXTI_SWIER_SWIER0',['../group___peripheral___registers___bits___definition.html#gaa6df16d2e8010a2897888a4acf19cee3',1,'stm32f407xx_matlab.h']]], - ['exti_5fswier_5fswier0_5fmsk_1255',['EXTI_SWIER_SWIER0_Msk',['../group___peripheral___registers___bits___definition.html#gaded47468bc0aade2a8c36333d64a3fc7',1,'stm32f407xx_matlab.h']]], - ['exti_5fswier_5fswier0_5fpos_1256',['EXTI_SWIER_SWIER0_Pos',['../group___peripheral___registers___bits___definition.html#ga47cfabfaaaf3453afad037f2b4ee959d',1,'stm32f407xx_matlab.h']]], - ['exti_5fswier_5fswier1_1257',['EXTI_SWIER_SWIER1',['../group___peripheral___registers___bits___definition.html#gaeb0c3fa5a03204d743ae92ff925421ae',1,'stm32f407xx_matlab.h']]], - ['exti_5fswier_5fswier10_1258',['EXTI_SWIER_SWIER10',['../group___peripheral___registers___bits___definition.html#gae9d8691936b6cd80ff8e18c0bfe271d7',1,'stm32f407xx_matlab.h']]], - ['exti_5fswier_5fswier10_5fmsk_1259',['EXTI_SWIER_SWIER10_Msk',['../group___peripheral___registers___bits___definition.html#ga64deb2466771c956d1e912ea09166925',1,'stm32f407xx_matlab.h']]], - ['exti_5fswier_5fswier10_5fpos_1260',['EXTI_SWIER_SWIER10_Pos',['../group___peripheral___registers___bits___definition.html#gaea5b7316b4b5dde162c9acd4e1d1a441',1,'stm32f407xx_matlab.h']]], - ['exti_5fswier_5fswier11_1261',['EXTI_SWIER_SWIER11',['../group___peripheral___registers___bits___definition.html#ga7ab9fea9935608ec8ee7fb1e1ae049e7',1,'stm32f407xx_matlab.h']]], - ['exti_5fswier_5fswier11_5fmsk_1262',['EXTI_SWIER_SWIER11_Msk',['../group___peripheral___registers___bits___definition.html#gaace4933cca50b04988d34d48c7b659c3',1,'stm32f407xx_matlab.h']]], - ['exti_5fswier_5fswier11_5fpos_1263',['EXTI_SWIER_SWIER11_Pos',['../group___peripheral___registers___bits___definition.html#ga37276792859bdf50b5bc358b78d4fbbd',1,'stm32f407xx_matlab.h']]], - ['exti_5fswier_5fswier12_1264',['EXTI_SWIER_SWIER12',['../group___peripheral___registers___bits___definition.html#ga5d67869db50c848f57633ebf00566539',1,'stm32f407xx_matlab.h']]], - ['exti_5fswier_5fswier12_5fmsk_1265',['EXTI_SWIER_SWIER12_Msk',['../group___peripheral___registers___bits___definition.html#ga7d4daf940040b81b93f70afed1ec62e1',1,'stm32f407xx_matlab.h']]], - ['exti_5fswier_5fswier12_5fpos_1266',['EXTI_SWIER_SWIER12_Pos',['../group___peripheral___registers___bits___definition.html#gab28ccd43920facdbbb974c9e37c40961',1,'stm32f407xx_matlab.h']]], - ['exti_5fswier_5fswier13_1267',['EXTI_SWIER_SWIER13',['../group___peripheral___registers___bits___definition.html#ga930a1d03fe3c32bd65a336ccee418826',1,'stm32f407xx_matlab.h']]], - ['exti_5fswier_5fswier13_5fmsk_1268',['EXTI_SWIER_SWIER13_Msk',['../group___peripheral___registers___bits___definition.html#gafa747f781753f3db0d1731ce24ad4ddd',1,'stm32f407xx_matlab.h']]], - ['exti_5fswier_5fswier13_5fpos_1269',['EXTI_SWIER_SWIER13_Pos',['../group___peripheral___registers___bits___definition.html#ga73603dbe0418523c2c83957265e7e65d',1,'stm32f407xx_matlab.h']]], - ['exti_5fswier_5fswier14_1270',['EXTI_SWIER_SWIER14',['../group___peripheral___registers___bits___definition.html#gad5d645db667cd63d1a9b91963c543a4b',1,'stm32f407xx_matlab.h']]], - ['exti_5fswier_5fswier14_5fmsk_1271',['EXTI_SWIER_SWIER14_Msk',['../group___peripheral___registers___bits___definition.html#ga405d264956ba9e06788545e2ad87413e',1,'stm32f407xx_matlab.h']]], - ['exti_5fswier_5fswier14_5fpos_1272',['EXTI_SWIER_SWIER14_Pos',['../group___peripheral___registers___bits___definition.html#ga4295bced15121047e453c21f0b32c4de',1,'stm32f407xx_matlab.h']]], - ['exti_5fswier_5fswier15_1273',['EXTI_SWIER_SWIER15',['../group___peripheral___registers___bits___definition.html#ga0b9e64d5a1779371fa4678713ab18e08',1,'stm32f407xx_matlab.h']]], - ['exti_5fswier_5fswier15_5fmsk_1274',['EXTI_SWIER_SWIER15_Msk',['../group___peripheral___registers___bits___definition.html#ga677582734fb712a69ae2d6fb3a3329b6',1,'stm32f407xx_matlab.h']]], - ['exti_5fswier_5fswier15_5fpos_1275',['EXTI_SWIER_SWIER15_Pos',['../group___peripheral___registers___bits___definition.html#gafe3550ed355b125e7e32503596d47d3b',1,'stm32f407xx_matlab.h']]], - ['exti_5fswier_5fswier16_1276',['EXTI_SWIER_SWIER16',['../group___peripheral___registers___bits___definition.html#ga55b528743b11f4ab93ae97ee2e639b5b',1,'stm32f407xx_matlab.h']]], - ['exti_5fswier_5fswier16_5fmsk_1277',['EXTI_SWIER_SWIER16_Msk',['../group___peripheral___registers___bits___definition.html#ga0c201ce487fab3e1b835a718ee9f11bf',1,'stm32f407xx_matlab.h']]], - ['exti_5fswier_5fswier16_5fpos_1278',['EXTI_SWIER_SWIER16_Pos',['../group___peripheral___registers___bits___definition.html#gabb2a375858bd09f73db412291d9672c5',1,'stm32f407xx_matlab.h']]], - ['exti_5fswier_5fswier17_1279',['EXTI_SWIER_SWIER17',['../group___peripheral___registers___bits___definition.html#ga0da944251419887af3a87c86080fb455',1,'stm32f407xx_matlab.h']]], - ['exti_5fswier_5fswier17_5fmsk_1280',['EXTI_SWIER_SWIER17_Msk',['../group___peripheral___registers___bits___definition.html#ga46bf902143efb4e89c7e20de1ed4f108',1,'stm32f407xx_matlab.h']]], - ['exti_5fswier_5fswier17_5fpos_1281',['EXTI_SWIER_SWIER17_Pos',['../group___peripheral___registers___bits___definition.html#ga9a0e994273bfe6b3bdf630b68c673ce7',1,'stm32f407xx_matlab.h']]], - ['exti_5fswier_5fswier18_1282',['EXTI_SWIER_SWIER18',['../group___peripheral___registers___bits___definition.html#gab07aefbb7a8a18c9338b49d3b10ff068',1,'stm32f407xx_matlab.h']]], - ['exti_5fswier_5fswier18_5fmsk_1283',['EXTI_SWIER_SWIER18_Msk',['../group___peripheral___registers___bits___definition.html#ga9db116e94a090f461d8551591f829002',1,'stm32f407xx_matlab.h']]], - ['exti_5fswier_5fswier18_5fpos_1284',['EXTI_SWIER_SWIER18_Pos',['../group___peripheral___registers___bits___definition.html#gabf33aa36748aefb6e66d4c2094a94518',1,'stm32f407xx_matlab.h']]], - ['exti_5fswier_5fswier19_1285',['EXTI_SWIER_SWIER19',['../group___peripheral___registers___bits___definition.html#gaab7c48ac5522385cdb1d7882985f909b',1,'stm32f407xx_matlab.h']]], - ['exti_5fswier_5fswier19_5fmsk_1286',['EXTI_SWIER_SWIER19_Msk',['../group___peripheral___registers___bits___definition.html#ga5fddcdc43381e5daa122589d1a769c41',1,'stm32f407xx_matlab.h']]], - ['exti_5fswier_5fswier19_5fpos_1287',['EXTI_SWIER_SWIER19_Pos',['../group___peripheral___registers___bits___definition.html#gab87df3a3d69a14c70b19e1d69c00a7c6',1,'stm32f407xx_matlab.h']]], - ['exti_5fswier_5fswier1_5fmsk_1288',['EXTI_SWIER_SWIER1_Msk',['../group___peripheral___registers___bits___definition.html#ga43b28416d9efdd9464c175f594ff0490',1,'stm32f407xx_matlab.h']]], - ['exti_5fswier_5fswier1_5fpos_1289',['EXTI_SWIER_SWIER1_Pos',['../group___peripheral___registers___bits___definition.html#gadf7afd1d1f63c7a76bae06e5c5d86e96',1,'stm32f407xx_matlab.h']]], - ['exti_5fswier_5fswier2_1290',['EXTI_SWIER_SWIER2',['../group___peripheral___registers___bits___definition.html#ga6bea1dbaf71e830dd357135524166f4c',1,'stm32f407xx_matlab.h']]], - ['exti_5fswier_5fswier20_1291',['EXTI_SWIER_SWIER20',['../group___peripheral___registers___bits___definition.html#gaac71bf967ecd31eaa57ba4064877a75b',1,'stm32f407xx_matlab.h']]], - ['exti_5fswier_5fswier20_5fmsk_1292',['EXTI_SWIER_SWIER20_Msk',['../group___peripheral___registers___bits___definition.html#gaed39df1c85fd5856af03e80a5f42e445',1,'stm32f407xx_matlab.h']]], - ['exti_5fswier_5fswier20_5fpos_1293',['EXTI_SWIER_SWIER20_Pos',['../group___peripheral___registers___bits___definition.html#gac2a016281fe0bb15bc0ca4ba9b11f97f',1,'stm32f407xx_matlab.h']]], - ['exti_5fswier_5fswier21_1294',['EXTI_SWIER_SWIER21',['../group___peripheral___registers___bits___definition.html#ga23b409de4bca55f1f16cd309e58e88e6',1,'stm32f407xx_matlab.h']]], - ['exti_5fswier_5fswier21_5fmsk_1295',['EXTI_SWIER_SWIER21_Msk',['../group___peripheral___registers___bits___definition.html#gab53e7b09746e33f833ad4143bfeb4977',1,'stm32f407xx_matlab.h']]], - ['exti_5fswier_5fswier21_5fpos_1296',['EXTI_SWIER_SWIER21_Pos',['../group___peripheral___registers___bits___definition.html#ga34163f6b2b814470372c81f5591efc8a',1,'stm32f407xx_matlab.h']]], - ['exti_5fswier_5fswier22_1297',['EXTI_SWIER_SWIER22',['../group___peripheral___registers___bits___definition.html#gad6bd7759b8d48c722f05ea3d2e64fc02',1,'stm32f407xx_matlab.h']]], - ['exti_5fswier_5fswier22_5fmsk_1298',['EXTI_SWIER_SWIER22_Msk',['../group___peripheral___registers___bits___definition.html#gaf58cca6423fc2497df3e6a9ff5942ff3',1,'stm32f407xx_matlab.h']]], - ['exti_5fswier_5fswier22_5fpos_1299',['EXTI_SWIER_SWIER22_Pos',['../group___peripheral___registers___bits___definition.html#gaaedc6a73eb5e640541c1b13a822a315a',1,'stm32f407xx_matlab.h']]], - ['exti_5fswier_5fswier2_5fmsk_1300',['EXTI_SWIER_SWIER2_Msk',['../group___peripheral___registers___bits___definition.html#ga701fc135a83a7a43ca6a977fa51087e1',1,'stm32f407xx_matlab.h']]], - ['exti_5fswier_5fswier2_5fpos_1301',['EXTI_SWIER_SWIER2_Pos',['../group___peripheral___registers___bits___definition.html#ga6bc778d2738c9f6b76c560c98c0995c6',1,'stm32f407xx_matlab.h']]], - ['exti_5fswier_5fswier3_1302',['EXTI_SWIER_SWIER3',['../group___peripheral___registers___bits___definition.html#ga37395ac6729647ab5ee1fa4ca086c08a',1,'stm32f407xx_matlab.h']]], - ['exti_5fswier_5fswier3_5fmsk_1303',['EXTI_SWIER_SWIER3_Msk',['../group___peripheral___registers___bits___definition.html#gaf1adab50a513d2ffc1c7ec8c245bb4ce',1,'stm32f407xx_matlab.h']]], - ['exti_5fswier_5fswier3_5fpos_1304',['EXTI_SWIER_SWIER3_Pos',['../group___peripheral___registers___bits___definition.html#gaaadaa259d663aebd65a50639e1907e5c',1,'stm32f407xx_matlab.h']]], - ['exti_5fswier_5fswier4_1305',['EXTI_SWIER_SWIER4',['../group___peripheral___registers___bits___definition.html#gab051808f7a1ed9aaf43a3df90fc6a575',1,'stm32f407xx_matlab.h']]], - ['exti_5fswier_5fswier4_5fmsk_1306',['EXTI_SWIER_SWIER4_Msk',['../group___peripheral___registers___bits___definition.html#ga0cb85edd29e2bbdbb0ec3021c8f80e72',1,'stm32f407xx_matlab.h']]], - ['exti_5fswier_5fswier4_5fpos_1307',['EXTI_SWIER_SWIER4_Pos',['../group___peripheral___registers___bits___definition.html#ga93c17eacb283557123595fb08107d9f5',1,'stm32f407xx_matlab.h']]], - ['exti_5fswier_5fswier5_1308',['EXTI_SWIER_SWIER5',['../group___peripheral___registers___bits___definition.html#gaa5b4ace22acacac13ce106b2063a3977',1,'stm32f407xx_matlab.h']]], - ['exti_5fswier_5fswier5_5fmsk_1309',['EXTI_SWIER_SWIER5_Msk',['../group___peripheral___registers___bits___definition.html#gab9bb6ac1da4531f229770893e8803226',1,'stm32f407xx_matlab.h']]], - ['exti_5fswier_5fswier5_5fpos_1310',['EXTI_SWIER_SWIER5_Pos',['../group___peripheral___registers___bits___definition.html#ga626a1b735d1a60ffd3490c307dce91e5',1,'stm32f407xx_matlab.h']]], - ['exti_5fswier_5fswier6_1311',['EXTI_SWIER_SWIER6',['../group___peripheral___registers___bits___definition.html#gad8ad0142288597993852e4cf350f61ed',1,'stm32f407xx_matlab.h']]], - ['exti_5fswier_5fswier6_5fmsk_1312',['EXTI_SWIER_SWIER6_Msk',['../group___peripheral___registers___bits___definition.html#ga820d4fc8485a8c681dd9deddccf85c64',1,'stm32f407xx_matlab.h']]], - ['exti_5fswier_5fswier6_5fpos_1313',['EXTI_SWIER_SWIER6_Pos',['../group___peripheral___registers___bits___definition.html#gaac5de035fe3b407ebd937d15b85bb8a6',1,'stm32f407xx_matlab.h']]], - ['exti_5fswier_5fswier7_1314',['EXTI_SWIER_SWIER7',['../group___peripheral___registers___bits___definition.html#gabdf8eab3e32cc03ca71f519a9111e28f',1,'stm32f407xx_matlab.h']]], - ['exti_5fswier_5fswier7_5fmsk_1315',['EXTI_SWIER_SWIER7_Msk',['../group___peripheral___registers___bits___definition.html#gac444748417965f0a263e4a3f99c81c22',1,'stm32f407xx_matlab.h']]], - ['exti_5fswier_5fswier7_5fpos_1316',['EXTI_SWIER_SWIER7_Pos',['../group___peripheral___registers___bits___definition.html#ga0d9dd65850bb89ff5205240324494035',1,'stm32f407xx_matlab.h']]], - ['exti_5fswier_5fswier8_1317',['EXTI_SWIER_SWIER8',['../group___peripheral___registers___bits___definition.html#ga5e83a373926804449d500b115e9090ce',1,'stm32f407xx_matlab.h']]], - ['exti_5fswier_5fswier8_5fmsk_1318',['EXTI_SWIER_SWIER8_Msk',['../group___peripheral___registers___bits___definition.html#ga584d2b8877c26e45231b2194baba055a',1,'stm32f407xx_matlab.h']]], - ['exti_5fswier_5fswier8_5fpos_1319',['EXTI_SWIER_SWIER8_Pos',['../group___peripheral___registers___bits___definition.html#ga606f473204836b050515446b252877c5',1,'stm32f407xx_matlab.h']]], - ['exti_5fswier_5fswier9_1320',['EXTI_SWIER_SWIER9',['../group___peripheral___registers___bits___definition.html#gab102aa929ffe463ffe9f2db651704a61',1,'stm32f407xx_matlab.h']]], - ['exti_5fswier_5fswier9_5fmsk_1321',['EXTI_SWIER_SWIER9_Msk',['../group___peripheral___registers___bits___definition.html#ga2b275083074cfd7a32fc9af85b56509b',1,'stm32f407xx_matlab.h']]], - ['exti_5fswier_5fswier9_5fpos_1322',['EXTI_SWIER_SWIER9_Pos',['../group___peripheral___registers___bits___definition.html#ga1d7f6e0def3861e207f4affc4f9755d4',1,'stm32f407xx_matlab.h']]], - ['exti_5ftypedef_1323',['EXTI_TypeDef',['../struct_e_x_t_i___type_def.html',1,'']]], - ['exticr_1324',['EXTICR',['../group___c_m_s_i_s___device.html#ga52f7bf8003ba69d66a4e86dea6eeab65',1,'SYSCFG_TypeDef']]] + ['emulator_0',['MATLAB STM32 EMULATOR',['../index.html',1,'']]], + ['eth_1',['eth',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga8b57579963e46439e92cb241151cec09',1,'stm32f4xx_periph_registers.c']]], + ['exti_2',['exti',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga5db1038489ccf5ec54a585b08226b84d',1,'stm32f4xx_periph_registers.c']]] ]; diff --git a/DOCS/html/search/all_6.js b/DOCS/html/search/all_6.js index c849c64..0d79bd4 100644 --- a/DOCS/html/search/all_6.js +++ b/DOCS/html/search/all_6.js @@ -1,1335 +1,27 @@ var searchData= [ - ['fa1r_0',['FA1R',['../group___c_m_s_i_s___device.html#gaaf76271f4ab0b3deb3ceb6e2ac0d62d0',1,'CAN_TypeDef']]], - ['fcr_1',['FCR',['../group___c_m_s_i_s___device.html#ga5d5cc7f32884945503dd29f8f6cbb415',1,'DMA_Stream_TypeDef']]], - ['ffa1r_2',['FFA1R',['../group___c_m_s_i_s___device.html#gaf1405e594e39e5b34f9499f680157a25',1,'CAN_TypeDef']]], - ['ffcr_3',['FFCR',['../group___c_m_s_i_s__core___debug_functions.html#gafe3ca1410c32188d26be24c4ee9e180c',1,'TPI_Type']]], - ['ffsr_4',['FFSR',['../group___c_m_s_i_s__core___debug_functions.html#ga2a049b49e9da6772d38166397ce8fc70',1,'TPI_Type']]], - ['field_20macros_5',['Core register bit field macros',['../group___c_m_s_i_s__core__bitfield.html',1,'']]], - ['fifo_6',['FIFO',['../group___c_m_s_i_s___device.html#ga68bef1da5fd164cf0f884b4209670dc8',1,'SDIO_TypeDef']]], - ['fifo0_7',['FIFO0',['../group___c_m_s_i_s__core___debug_functions.html#gace73d78eff029b698e11cd5cf3efaf94',1,'TPI_Type']]], - ['fifo1_8',['FIFO1',['../group___c_m_s_i_s__core___debug_functions.html#gabad7737b3d46cc6d4813d37171d29745',1,'TPI_Type']]], - ['fifocnt_9',['FIFOCNT',['../group___c_m_s_i_s___device.html#ga003c4c00f70bd77298fc66a449822651',1,'SDIO_TypeDef']]], - ['flagstatus_10',['FlagStatus',['../group___exported__types.html#ga89136caac2e14c55151f527ac02daaff',1,'stm32f4xx.h']]], - ['flash_11',['FLASH',['../group___peripheral__declaration.html#ga844ea28ba1e0a5a0e497f16b61ea306b',1,'stm32f407xx_matlab.h']]], - ['flash_5facr_5fbyte0_5faddress_12',['FLASH_ACR_BYTE0_ADDRESS',['../group___peripheral___registers___bits___definition.html#ga277876cbec14426a7a70ed6b3ead6d49',1,'stm32f407xx_matlab.h']]], - ['flash_5facr_5fbyte0_5faddress_5fmsk_13',['FLASH_ACR_BYTE0_ADDRESS_Msk',['../group___peripheral___registers___bits___definition.html#ga8e53f8ca7c06552c5383884a01908a58',1,'stm32f407xx_matlab.h']]], - ['flash_5facr_5fbyte0_5faddress_5fpos_14',['FLASH_ACR_BYTE0_ADDRESS_Pos',['../group___peripheral___registers___bits___definition.html#gaa35bb342e6db09c1515b40635275212b',1,'stm32f407xx_matlab.h']]], - ['flash_5facr_5fbyte2_5faddress_15',['FLASH_ACR_BYTE2_ADDRESS',['../group___peripheral___registers___bits___definition.html#gac7c5712edb158a725d8647c6af19544e',1,'stm32f407xx_matlab.h']]], - ['flash_5facr_5fbyte2_5faddress_5fmsk_16',['FLASH_ACR_BYTE2_ADDRESS_Msk',['../group___peripheral___registers___bits___definition.html#ga5bb60f05f974d5fa62cea9de4dc907d1',1,'stm32f407xx_matlab.h']]], - ['flash_5facr_5fbyte2_5faddress_5fpos_17',['FLASH_ACR_BYTE2_ADDRESS_Pos',['../group___peripheral___registers___bits___definition.html#ga5c66a942588ae72bc8f5d54bea5e3bf2',1,'stm32f407xx_matlab.h']]], - ['flash_5facr_5fdcen_18',['FLASH_ACR_DCEN',['../group___peripheral___registers___bits___definition.html#ga5a9a5cc3aa05dc62264addab1008c896',1,'stm32f407xx_matlab.h']]], - ['flash_5facr_5fdcen_5fmsk_19',['FLASH_ACR_DCEN_Msk',['../group___peripheral___registers___bits___definition.html#gac4d8386ca0c38a2a5546714a068e63d5',1,'stm32f407xx_matlab.h']]], - ['flash_5facr_5fdcen_5fpos_20',['FLASH_ACR_DCEN_Pos',['../group___peripheral___registers___bits___definition.html#ga168563c4043c04251fc1524f6780a18e',1,'stm32f407xx_matlab.h']]], - ['flash_5facr_5fdcrst_21',['FLASH_ACR_DCRST',['../group___peripheral___registers___bits___definition.html#gac53d7c85551a9829014d6027d67ce6c7',1,'stm32f407xx_matlab.h']]], - ['flash_5facr_5fdcrst_5fmsk_22',['FLASH_ACR_DCRST_Msk',['../group___peripheral___registers___bits___definition.html#gab292276bf617270acde9e91828cbaede',1,'stm32f407xx_matlab.h']]], - ['flash_5facr_5fdcrst_5fpos_23',['FLASH_ACR_DCRST_Pos',['../group___peripheral___registers___bits___definition.html#gab97b6c3668fe60543b9d5a4f14e18f06',1,'stm32f407xx_matlab.h']]], - ['flash_5facr_5ficen_24',['FLASH_ACR_ICEN',['../group___peripheral___registers___bits___definition.html#ga51d8b1dd2c46942d377c579a38dce711',1,'stm32f407xx_matlab.h']]], - ['flash_5facr_5ficen_5fmsk_25',['FLASH_ACR_ICEN_Msk',['../group___peripheral___registers___bits___definition.html#ga95b43999203bce2ccdea6eba1f9925b9',1,'stm32f407xx_matlab.h']]], - ['flash_5facr_5ficen_5fpos_26',['FLASH_ACR_ICEN_Pos',['../group___peripheral___registers___bits___definition.html#gaf2045375967b3774ee2a00f3f3de10ad',1,'stm32f407xx_matlab.h']]], - ['flash_5facr_5ficrst_27',['FLASH_ACR_ICRST',['../group___peripheral___registers___bits___definition.html#ga923ff88475799eea9285f77f5383ced5',1,'stm32f407xx_matlab.h']]], - ['flash_5facr_5ficrst_5fmsk_28',['FLASH_ACR_ICRST_Msk',['../group___peripheral___registers___bits___definition.html#ga009d7ec202f2ec4e6322d6051731dcea',1,'stm32f407xx_matlab.h']]], - ['flash_5facr_5ficrst_5fpos_29',['FLASH_ACR_ICRST_Pos',['../group___peripheral___registers___bits___definition.html#ga5a8676f7e028638743d0097921be11e5',1,'stm32f407xx_matlab.h']]], - ['flash_5facr_5flatency_30',['FLASH_ACR_LATENCY',['../group___peripheral___registers___bits___definition.html#gaef5e44cbb084160a6004ca9951ec7318',1,'stm32f407xx_matlab.h']]], - ['flash_5facr_5flatency_5f0ws_31',['FLASH_ACR_LATENCY_0WS',['../group___peripheral___registers___bits___definition.html#ga936324709ea40109331b76849da2c8b2',1,'stm32f407xx_matlab.h']]], - ['flash_5facr_5flatency_5f1ws_32',['FLASH_ACR_LATENCY_1WS',['../group___peripheral___registers___bits___definition.html#gaec66af244e6afb5bbf9816d7c76e1621',1,'stm32f407xx_matlab.h']]], - ['flash_5facr_5flatency_5f2ws_33',['FLASH_ACR_LATENCY_2WS',['../group___peripheral___registers___bits___definition.html#gad9b09ca8db6df455d0b8f810f8521257',1,'stm32f407xx_matlab.h']]], - ['flash_5facr_5flatency_5f3ws_34',['FLASH_ACR_LATENCY_3WS',['../group___peripheral___registers___bits___definition.html#ga3437dcee177845a407919d3b2d9bd063',1,'stm32f407xx_matlab.h']]], - ['flash_5facr_5flatency_5f4ws_35',['FLASH_ACR_LATENCY_4WS',['../group___peripheral___registers___bits___definition.html#gad3594f2a9e12213efe75cd7df646e1ad',1,'stm32f407xx_matlab.h']]], - ['flash_5facr_5flatency_5f5ws_36',['FLASH_ACR_LATENCY_5WS',['../group___peripheral___registers___bits___definition.html#ga67e55ca49f028a701d0c81420a6e2918',1,'stm32f407xx_matlab.h']]], - ['flash_5facr_5flatency_5f6ws_37',['FLASH_ACR_LATENCY_6WS',['../group___peripheral___registers___bits___definition.html#ga3019ff197b4fd698e9625c9abb67f4be',1,'stm32f407xx_matlab.h']]], - ['flash_5facr_5flatency_5f7ws_38',['FLASH_ACR_LATENCY_7WS',['../group___peripheral___registers___bits___definition.html#gaa164c6e6fdfcae274a84dc87ca87b95e',1,'stm32f407xx_matlab.h']]], - ['flash_5facr_5flatency_5fmsk_39',['FLASH_ACR_LATENCY_Msk',['../group___peripheral___registers___bits___definition.html#gabdcd07c55bf5197e31d5ad9ab61747a3',1,'stm32f407xx_matlab.h']]], - ['flash_5facr_5flatency_5fpos_40',['FLASH_ACR_LATENCY_Pos',['../group___peripheral___registers___bits___definition.html#gacd27f57311268ed1ad0ddb1a207ce9a4',1,'stm32f407xx_matlab.h']]], - ['flash_5facr_5fprften_41',['FLASH_ACR_PRFTEN',['../group___peripheral___registers___bits___definition.html#ga082e7e91fffee86db39676396d01a8e0',1,'stm32f407xx_matlab.h']]], - ['flash_5facr_5fprften_5fmsk_42',['FLASH_ACR_PRFTEN_Msk',['../group___peripheral___registers___bits___definition.html#ga727504c465ce30a499631159bc419179',1,'stm32f407xx_matlab.h']]], - ['flash_5facr_5fprften_5fpos_43',['FLASH_ACR_PRFTEN_Pos',['../group___peripheral___registers___bits___definition.html#gaaf1b922e6400999bfabcde78d1c6f59b',1,'stm32f407xx_matlab.h']]], - ['flash_5fbase_44',['FLASH_BASE',['../group___c_m_s_i_s___device.html#ga84303738f0e64d5303c027932c055d87',1,'_memory::FLASH_BASE'],['../group___peripheral__memory__map.html#ga23a9099a5f8fc9c6e253c0eecb2be8db',1,'FLASH_BASE: stm32f407xx_matlab.h']]], - ['flash_5fbase_5fshift_45',['FLASH_BASE_SHIFT',['../group___peripheral__memory__map.html#ga4a1f7e664b3e091fee94976b33bbf7b9',1,'stm32f407xx_matlab.h']]], - ['flash_5fcr_5feopie_46',['FLASH_CR_EOPIE',['../group___peripheral___registers___bits___definition.html#gab9e69856f654ec430a42791a34799db0',1,'stm32f407xx_matlab.h']]], - ['flash_5fcr_5feopie_5fmsk_47',['FLASH_CR_EOPIE_Msk',['../group___peripheral___registers___bits___definition.html#gab0866e1ddcbf0e7a895ca9a4794db4bd',1,'stm32f407xx_matlab.h']]], - ['flash_5fcr_5feopie_5fpos_48',['FLASH_CR_EOPIE_Pos',['../group___peripheral___registers___bits___definition.html#ga4e162a7fa45cb85ba0df0942a2519478',1,'stm32f407xx_matlab.h']]], - ['flash_5fcr_5ferrie_49',['FLASH_CR_ERRIE',['../group___peripheral___registers___bits___definition.html#ga930897cecdaa9dbef8c640b84acbd8c2',1,'stm32f407xx_matlab.h']]], - ['flash_5fcr_5ferrie_5fmsk_50',['FLASH_CR_ERRIE_Msk',['../group___peripheral___registers___bits___definition.html#gac9f1e535996ab89de1ca07a32a11e526',1,'stm32f407xx_matlab.h']]], - ['flash_5fcr_5ferrie_5fpos_51',['FLASH_CR_ERRIE_Pos',['../group___peripheral___registers___bits___definition.html#gab075c4eeff509cfe0f34040c29edfb05',1,'stm32f407xx_matlab.h']]], - ['flash_5fcr_5flock_52',['FLASH_CR_LOCK',['../group___peripheral___registers___bits___definition.html#gab25f1fa4127fa015361b61a6f3180784',1,'stm32f407xx_matlab.h']]], - ['flash_5fcr_5flock_5fmsk_53',['FLASH_CR_LOCK_Msk',['../group___peripheral___registers___bits___definition.html#ga7954a2bc4dd25495e8c164454817a966',1,'stm32f407xx_matlab.h']]], - ['flash_5fcr_5flock_5fpos_54',['FLASH_CR_LOCK_Pos',['../group___peripheral___registers___bits___definition.html#gaa74509adc6db3db66803966b25423cae',1,'stm32f407xx_matlab.h']]], - ['flash_5fcr_5fmer_55',['FLASH_CR_MER',['../group___peripheral___registers___bits___definition.html#ga4a287aa5a625125301306a02fb69c53a',1,'stm32f407xx_matlab.h']]], - ['flash_5fcr_5fmer_5fmsk_56',['FLASH_CR_MER_Msk',['../group___peripheral___registers___bits___definition.html#ga3f1b8b67a6173c11f950347f09e63888',1,'stm32f407xx_matlab.h']]], - ['flash_5fcr_5fmer_5fpos_57',['FLASH_CR_MER_Pos',['../group___peripheral___registers___bits___definition.html#ga0627fa13f9e31a0250d6917e4d2ecbc1',1,'stm32f407xx_matlab.h']]], - ['flash_5fcr_5fpg_58',['FLASH_CR_PG',['../group___peripheral___registers___bits___definition.html#ga47754b39bd7a7c79c251d6376f97f661',1,'stm32f407xx_matlab.h']]], - ['flash_5fcr_5fpg_5fmsk_59',['FLASH_CR_PG_Msk',['../group___peripheral___registers___bits___definition.html#ga8bc468bdb6b58e9db0f91752dea96b1a',1,'stm32f407xx_matlab.h']]], - ['flash_5fcr_5fpg_5fpos_60',['FLASH_CR_PG_Pos',['../group___peripheral___registers___bits___definition.html#ga0a5addaa1ee5049b0c99023d91dd4a70',1,'stm32f407xx_matlab.h']]], - ['flash_5fcr_5fpsize_61',['FLASH_CR_PSIZE',['../group___peripheral___registers___bits___definition.html#ga948ebea4921be9f981292b6e6733b00f',1,'stm32f407xx_matlab.h']]], - ['flash_5fcr_5fpsize_5f0_62',['FLASH_CR_PSIZE_0',['../group___peripheral___registers___bits___definition.html#gaadbc673f47f1ed33ca4144e9eee91ad6',1,'stm32f407xx_matlab.h']]], - ['flash_5fcr_5fpsize_5f1_63',['FLASH_CR_PSIZE_1',['../group___peripheral___registers___bits___definition.html#ga196dca8b265486bf05782e6bbe81d854',1,'stm32f407xx_matlab.h']]], - ['flash_5fcr_5fpsize_5fmsk_64',['FLASH_CR_PSIZE_Msk',['../group___peripheral___registers___bits___definition.html#ga4f6b8486e155b78a7617fe046bade831',1,'stm32f407xx_matlab.h']]], - ['flash_5fcr_5fpsize_5fpos_65',['FLASH_CR_PSIZE_Pos',['../group___peripheral___registers___bits___definition.html#ga0242af989594850be999d37750caa5c5',1,'stm32f407xx_matlab.h']]], - ['flash_5fcr_5fser_66',['FLASH_CR_SER',['../group___peripheral___registers___bits___definition.html#gae0e561d67b381c4bd8714cd6a9c15f56',1,'stm32f407xx_matlab.h']]], - ['flash_5fcr_5fser_5fmsk_67',['FLASH_CR_SER_Msk',['../group___peripheral___registers___bits___definition.html#ga6479f79813e55ff738208840dd3abfeb',1,'stm32f407xx_matlab.h']]], - ['flash_5fcr_5fser_5fpos_68',['FLASH_CR_SER_Pos',['../group___peripheral___registers___bits___definition.html#ga9b8aa46dd6b3ec7eac3981210966235e',1,'stm32f407xx_matlab.h']]], - ['flash_5fcr_5fsnb_69',['FLASH_CR_SNB',['../group___peripheral___registers___bits___definition.html#ga4375b021000bd1acdecab7f72240f57d',1,'stm32f407xx_matlab.h']]], - ['flash_5fcr_5fsnb_5f0_70',['FLASH_CR_SNB_0',['../group___peripheral___registers___bits___definition.html#ga9937f2386c7127f9855f68e2ec121448',1,'stm32f407xx_matlab.h']]], - ['flash_5fcr_5fsnb_5f1_71',['FLASH_CR_SNB_1',['../group___peripheral___registers___bits___definition.html#gaa70c4abfe231ffeab3f34a97c171427b',1,'stm32f407xx_matlab.h']]], - ['flash_5fcr_5fsnb_5f2_72',['FLASH_CR_SNB_2',['../group___peripheral___registers___bits___definition.html#ga23c44361d3aaf062fc6b288b1d44b988',1,'stm32f407xx_matlab.h']]], - ['flash_5fcr_5fsnb_5f3_73',['FLASH_CR_SNB_3',['../group___peripheral___registers___bits___definition.html#ga417708b5b7aabfe219fb671f2955af31',1,'stm32f407xx_matlab.h']]], - ['flash_5fcr_5fsnb_5f4_74',['FLASH_CR_SNB_4',['../group___peripheral___registers___bits___definition.html#ga734972442e2704a86bfb69c5707b33a1',1,'stm32f407xx_matlab.h']]], - ['flash_5fcr_5fsnb_5fmsk_75',['FLASH_CR_SNB_Msk',['../group___peripheral___registers___bits___definition.html#ga67d162f1700e851ee1f94a541f761c7d',1,'stm32f407xx_matlab.h']]], - ['flash_5fcr_5fsnb_5fpos_76',['FLASH_CR_SNB_Pos',['../group___peripheral___registers___bits___definition.html#gab657376caa866d7aebcb539c12d943bb',1,'stm32f407xx_matlab.h']]], - ['flash_5fcr_5fstrt_77',['FLASH_CR_STRT',['../group___peripheral___registers___bits___definition.html#gafe4dd28134f93f52b1d4ec5b36a99864',1,'stm32f407xx_matlab.h']]], - ['flash_5fcr_5fstrt_5fmsk_78',['FLASH_CR_STRT_Msk',['../group___peripheral___registers___bits___definition.html#ga1ce773f84ec7782c408a8d9cef09f496',1,'stm32f407xx_matlab.h']]], - ['flash_5fcr_5fstrt_5fpos_79',['FLASH_CR_STRT_Pos',['../group___peripheral___registers___bits___definition.html#ga7925df36a4d15838d8cb457f671e7532',1,'stm32f407xx_matlab.h']]], - ['flash_5fend_80',['FLASH_END',['../group___peripheral__memory__map.html#ga8be554f354e5aa65370f6db63d4f3ee4',1,'stm32f407xx_matlab.h']]], - ['flash_5fend_5fshift_81',['FLASH_END_SHIFT',['../group___peripheral__memory__map.html#ga77155e7666b070a9653f0a43d11f2004',1,'stm32f407xx_matlab.h']]], - ['flash_5firqn_82',['FLASH_IRQn',['../group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a91b73963ce243a1d031576d49e137fab',1,'stm32f407xx_matlab.h']]], - ['flash_5foptcr1_5fnwrp_83',['FLASH_OPTCR1_nWRP',['../group___peripheral___registers___bits___definition.html#ga166b108d44b55fef7da25bb1a9696d4a',1,'stm32f407xx_matlab.h']]], - ['flash_5foptcr1_5fnwrp_5f0_84',['FLASH_OPTCR1_nWRP_0',['../group___peripheral___registers___bits___definition.html#gab8704f7d9b4f2ed666a36fd524200393',1,'stm32f407xx_matlab.h']]], - ['flash_5foptcr1_5fnwrp_5f1_85',['FLASH_OPTCR1_nWRP_1',['../group___peripheral___registers___bits___definition.html#ga5dbe2ea161a6b8f8f9410097b56e7f37',1,'stm32f407xx_matlab.h']]], - ['flash_5foptcr1_5fnwrp_5f10_86',['FLASH_OPTCR1_nWRP_10',['../group___peripheral___registers___bits___definition.html#gaaf08f9db2b0ca30861faac54b6df672e',1,'stm32f407xx_matlab.h']]], - ['flash_5foptcr1_5fnwrp_5f11_87',['FLASH_OPTCR1_nWRP_11',['../group___peripheral___registers___bits___definition.html#ga244656eb3ca465d38aba14e92f8c5870',1,'stm32f407xx_matlab.h']]], - ['flash_5foptcr1_5fnwrp_5f2_88',['FLASH_OPTCR1_nWRP_2',['../group___peripheral___registers___bits___definition.html#ga95055e7aee08960157182164896ab53e',1,'stm32f407xx_matlab.h']]], - ['flash_5foptcr1_5fnwrp_5f3_89',['FLASH_OPTCR1_nWRP_3',['../group___peripheral___registers___bits___definition.html#ga215ec5e70d6f8e9bcfc23e808720b7b5',1,'stm32f407xx_matlab.h']]], - ['flash_5foptcr1_5fnwrp_5f4_90',['FLASH_OPTCR1_nWRP_4',['../group___peripheral___registers___bits___definition.html#ga552186f19bc88ebbceb4b20fd17fa15c',1,'stm32f407xx_matlab.h']]], - ['flash_5foptcr1_5fnwrp_5f5_91',['FLASH_OPTCR1_nWRP_5',['../group___peripheral___registers___bits___definition.html#gaa4370733a7b56759492f1af72272d086',1,'stm32f407xx_matlab.h']]], - ['flash_5foptcr1_5fnwrp_5f6_92',['FLASH_OPTCR1_nWRP_6',['../group___peripheral___registers___bits___definition.html#gaeecb61b8efdc36c40fce01e4cd1d5907',1,'stm32f407xx_matlab.h']]], - ['flash_5foptcr1_5fnwrp_5f7_93',['FLASH_OPTCR1_nWRP_7',['../group___peripheral___registers___bits___definition.html#ga7e3446bcd7be06c230bc6cbceadae5cf',1,'stm32f407xx_matlab.h']]], - ['flash_5foptcr1_5fnwrp_5f8_94',['FLASH_OPTCR1_nWRP_8',['../group___peripheral___registers___bits___definition.html#ga97aac6b31d856505401e3bef486df10f',1,'stm32f407xx_matlab.h']]], - ['flash_5foptcr1_5fnwrp_5f9_95',['FLASH_OPTCR1_nWRP_9',['../group___peripheral___registers___bits___definition.html#ga0ab067bd8ab9645c93e6acf3b839dd8d',1,'stm32f407xx_matlab.h']]], - ['flash_5foptcr1_5fnwrp_5fmsk_96',['FLASH_OPTCR1_nWRP_Msk',['../group___peripheral___registers___bits___definition.html#ga584b3c849783bc64b9fde5f4f15090b6',1,'stm32f407xx_matlab.h']]], - ['flash_5foptcr1_5fnwrp_5fpos_97',['FLASH_OPTCR1_nWRP_Pos',['../group___peripheral___registers___bits___definition.html#ga5258f37e33f2705635abfcfa1e7caf8b',1,'stm32f407xx_matlab.h']]], - ['flash_5foptcr_5fbor_5flev_98',['FLASH_OPTCR_BOR_LEV',['../group___peripheral___registers___bits___definition.html#ga62cadc42caa03753ab8733da2b957ead',1,'stm32f407xx_matlab.h']]], - ['flash_5foptcr_5fbor_5flev_5f0_99',['FLASH_OPTCR_BOR_LEV_0',['../group___peripheral___registers___bits___definition.html#gaf842eaac29efd86925c9431a8eb99b27',1,'stm32f407xx_matlab.h']]], - ['flash_5foptcr_5fbor_5flev_5f1_100',['FLASH_OPTCR_BOR_LEV_1',['../group___peripheral___registers___bits___definition.html#ga2971824f63351f09ad3db521d6a5b212',1,'stm32f407xx_matlab.h']]], - ['flash_5foptcr_5fbor_5flev_5fmsk_101',['FLASH_OPTCR_BOR_LEV_Msk',['../group___peripheral___registers___bits___definition.html#ga0bbb4145b4e60c9aba5a41b52ca7de42',1,'stm32f407xx_matlab.h']]], - ['flash_5foptcr_5fbor_5flev_5fpos_102',['FLASH_OPTCR_BOR_LEV_Pos',['../group___peripheral___registers___bits___definition.html#ga664b8edfc20be3140e72411130fd9c2c',1,'stm32f407xx_matlab.h']]], - ['flash_5foptcr_5fnrst_5fstdby_103',['FLASH_OPTCR_nRST_STDBY',['../group___peripheral___registers___bits___definition.html#ga82102d640fe1d3e6e9f9c6a3e0adb56f',1,'stm32f407xx_matlab.h']]], - ['flash_5foptcr_5fnrst_5fstdby_5fmsk_104',['FLASH_OPTCR_nRST_STDBY_Msk',['../group___peripheral___registers___bits___definition.html#ga02c3e4e48e88b93407109e671e8aaf0e',1,'stm32f407xx_matlab.h']]], - ['flash_5foptcr_5fnrst_5fstdby_5fpos_105',['FLASH_OPTCR_nRST_STDBY_Pos',['../group___peripheral___registers___bits___definition.html#ga1240d379a33450a4a5fd676f13cd4db2',1,'stm32f407xx_matlab.h']]], - ['flash_5foptcr_5fnrst_5fstop_106',['FLASH_OPTCR_nRST_STOP',['../group___peripheral___registers___bits___definition.html#ga12b1ec98e521815433b3eec1e4136fd2',1,'stm32f407xx_matlab.h']]], - ['flash_5foptcr_5fnrst_5fstop_5fmsk_107',['FLASH_OPTCR_nRST_STOP_Msk',['../group___peripheral___registers___bits___definition.html#ga203b0fae4100b7cb942d38ab22459793',1,'stm32f407xx_matlab.h']]], - ['flash_5foptcr_5fnrst_5fstop_5fpos_108',['FLASH_OPTCR_nRST_STOP_Pos',['../group___peripheral___registers___bits___definition.html#ga0df94d9b6c39215d53adeb12124ffe2a',1,'stm32f407xx_matlab.h']]], - ['flash_5foptcr_5fnwrp_109',['FLASH_OPTCR_nWRP',['../group___peripheral___registers___bits___definition.html#ga2c2bbd885cff2e6c16662a014f3125e1',1,'stm32f407xx_matlab.h']]], - ['flash_5foptcr_5fnwrp_5f0_110',['FLASH_OPTCR_nWRP_0',['../group___peripheral___registers___bits___definition.html#ga823e5c42b89e152a8394c3fa6c8811ca',1,'stm32f407xx_matlab.h']]], - ['flash_5foptcr_5fnwrp_5f1_111',['FLASH_OPTCR_nWRP_1',['../group___peripheral___registers___bits___definition.html#ga4d0ef7c876b297706a26dda017441f9c',1,'stm32f407xx_matlab.h']]], - ['flash_5foptcr_5fnwrp_5f10_112',['FLASH_OPTCR_nWRP_10',['../group___peripheral___registers___bits___definition.html#ga38f22bae03f31d60f0c6aded7cd29ead',1,'stm32f407xx_matlab.h']]], - ['flash_5foptcr_5fnwrp_5f11_113',['FLASH_OPTCR_nWRP_11',['../group___peripheral___registers___bits___definition.html#gac11ce7f6df6922142fc54fb8d376e239',1,'stm32f407xx_matlab.h']]], - ['flash_5foptcr_5fnwrp_5f2_114',['FLASH_OPTCR_nWRP_2',['../group___peripheral___registers___bits___definition.html#ga96c5b96918f1871febfb31a026028522',1,'stm32f407xx_matlab.h']]], - ['flash_5foptcr_5fnwrp_5f3_115',['FLASH_OPTCR_nWRP_3',['../group___peripheral___registers___bits___definition.html#gabb0fa51cc0e95dcc79b74f451898f634',1,'stm32f407xx_matlab.h']]], - ['flash_5foptcr_5fnwrp_5f4_116',['FLASH_OPTCR_nWRP_4',['../group___peripheral___registers___bits___definition.html#gad936542dd4c587babd790e92783d90fb',1,'stm32f407xx_matlab.h']]], - ['flash_5foptcr_5fnwrp_5f5_117',['FLASH_OPTCR_nWRP_5',['../group___peripheral___registers___bits___definition.html#gae20268ac71dad90ee983642bb328e8ca',1,'stm32f407xx_matlab.h']]], - ['flash_5foptcr_5fnwrp_5f6_118',['FLASH_OPTCR_nWRP_6',['../group___peripheral___registers___bits___definition.html#ga947616eac2be3f26ae1a3d748e70cac8',1,'stm32f407xx_matlab.h']]], - ['flash_5foptcr_5fnwrp_5f7_119',['FLASH_OPTCR_nWRP_7',['../group___peripheral___registers___bits___definition.html#gaa4d248e42a97e1c852cbea42b25598e1',1,'stm32f407xx_matlab.h']]], - ['flash_5foptcr_5fnwrp_5f8_120',['FLASH_OPTCR_nWRP_8',['../group___peripheral___registers___bits___definition.html#gadb38a3c5a67d67160a33d1762ed0f51f',1,'stm32f407xx_matlab.h']]], - ['flash_5foptcr_5fnwrp_5f9_121',['FLASH_OPTCR_nWRP_9',['../group___peripheral___registers___bits___definition.html#ga5e186dbacd1587760b167b9ae4166c5c',1,'stm32f407xx_matlab.h']]], - ['flash_5foptcr_5fnwrp_5fmsk_122',['FLASH_OPTCR_nWRP_Msk',['../group___peripheral___registers___bits___definition.html#gae33aa677769879cad328db0ee92829df',1,'stm32f407xx_matlab.h']]], - ['flash_5foptcr_5fnwrp_5fpos_123',['FLASH_OPTCR_nWRP_Pos',['../group___peripheral___registers___bits___definition.html#gabb898dd74f16687db438fac87e762e40',1,'stm32f407xx_matlab.h']]], - ['flash_5foptcr_5foptlock_124',['FLASH_OPTCR_OPTLOCK',['../group___peripheral___registers___bits___definition.html#ga4c1da080e341fca41ce7f7d661cc4904',1,'stm32f407xx_matlab.h']]], - ['flash_5foptcr_5foptlock_5fmsk_125',['FLASH_OPTCR_OPTLOCK_Msk',['../group___peripheral___registers___bits___definition.html#gac4fb506626a51c8b29c864573f6c2835',1,'stm32f407xx_matlab.h']]], - ['flash_5foptcr_5foptlock_5fpos_126',['FLASH_OPTCR_OPTLOCK_Pos',['../group___peripheral___registers___bits___definition.html#gaaf12a3ac81fbc65a12d83ed398b6ef28',1,'stm32f407xx_matlab.h']]], - ['flash_5foptcr_5foptstrt_127',['FLASH_OPTCR_OPTSTRT',['../group___peripheral___registers___bits___definition.html#ga0858d561d4790c86b64a60204a09a3b5',1,'stm32f407xx_matlab.h']]], - ['flash_5foptcr_5foptstrt_5fmsk_128',['FLASH_OPTCR_OPTSTRT_Msk',['../group___peripheral___registers___bits___definition.html#gaf93699ed3b5dc9bb83833f2bf1610b11',1,'stm32f407xx_matlab.h']]], - ['flash_5foptcr_5foptstrt_5fpos_129',['FLASH_OPTCR_OPTSTRT_Pos',['../group___peripheral___registers___bits___definition.html#ga83a4a90f9f76098cdca63d9931bc79d7',1,'stm32f407xx_matlab.h']]], - ['flash_5foptcr_5frdp_130',['FLASH_OPTCR_RDP',['../group___peripheral___registers___bits___definition.html#gaa180c5732c34b271618aa58695c8ff5a',1,'stm32f407xx_matlab.h']]], - ['flash_5foptcr_5frdp_5f0_131',['FLASH_OPTCR_RDP_0',['../group___peripheral___registers___bits___definition.html#gafd79ca0fb8dd121074f40b83b2313d12',1,'stm32f407xx_matlab.h']]], - ['flash_5foptcr_5frdp_5f1_132',['FLASH_OPTCR_RDP_1',['../group___peripheral___registers___bits___definition.html#ga935fe4b6ea955b3dc26110f19e894e60',1,'stm32f407xx_matlab.h']]], - ['flash_5foptcr_5frdp_5f2_133',['FLASH_OPTCR_RDP_2',['../group___peripheral___registers___bits___definition.html#ga02ba844244e374fe8105a7cad59ad523',1,'stm32f407xx_matlab.h']]], - ['flash_5foptcr_5frdp_5f3_134',['FLASH_OPTCR_RDP_3',['../group___peripheral___registers___bits___definition.html#ga844d4d62b7de476c90dd5f971f5e9041',1,'stm32f407xx_matlab.h']]], - ['flash_5foptcr_5frdp_5f4_135',['FLASH_OPTCR_RDP_4',['../group___peripheral___registers___bits___definition.html#ga73bffe5ebb8d12020ebf3f2875f4a709',1,'stm32f407xx_matlab.h']]], - ['flash_5foptcr_5frdp_5f5_136',['FLASH_OPTCR_RDP_5',['../group___peripheral___registers___bits___definition.html#ga67fef54b7b6c44afcc50e4f20ba461fd',1,'stm32f407xx_matlab.h']]], - ['flash_5foptcr_5frdp_5f6_137',['FLASH_OPTCR_RDP_6',['../group___peripheral___registers___bits___definition.html#ga18946cdea0f463f1e5386f42986f7e67',1,'stm32f407xx_matlab.h']]], - ['flash_5foptcr_5frdp_5f7_138',['FLASH_OPTCR_RDP_7',['../group___peripheral___registers___bits___definition.html#gad00a8584a84d18d76e147e4873740b4d',1,'stm32f407xx_matlab.h']]], - ['flash_5foptcr_5frdp_5fmsk_139',['FLASH_OPTCR_RDP_Msk',['../group___peripheral___registers___bits___definition.html#ga3bc4c590daea652ce57f3a44a6a67d84',1,'stm32f407xx_matlab.h']]], - ['flash_5foptcr_5frdp_5fpos_140',['FLASH_OPTCR_RDP_Pos',['../group___peripheral___registers___bits___definition.html#ga2e06896e31b4fbbbffaa2865c16a607e',1,'stm32f407xx_matlab.h']]], - ['flash_5foptcr_5fwdg_5fsw_141',['FLASH_OPTCR_WDG_SW',['../group___peripheral___registers___bits___definition.html#gaf38cbe85e3a2c30dbe6ccb3b3e636504',1,'stm32f407xx_matlab.h']]], - ['flash_5foptcr_5fwdg_5fsw_5fmsk_142',['FLASH_OPTCR_WDG_SW_Msk',['../group___peripheral___registers___bits___definition.html#ga5a820fdb171a46fddcc020aa769a7b87',1,'stm32f407xx_matlab.h']]], - ['flash_5foptcr_5fwdg_5fsw_5fpos_143',['FLASH_OPTCR_WDG_SW_Pos',['../group___peripheral___registers___bits___definition.html#ga135a90817c765ba7f80a463cd48b8dd2',1,'stm32f407xx_matlab.h']]], - ['flash_5fotp_5fbase_144',['FLASH_OTP_BASE',['../group___c_m_s_i_s___device.html#gace5daae0e2da2f05a6b63f3f68109284',1,'_memory::FLASH_OTP_BASE'],['../group___peripheral__memory__map.html#ga91d296a67aec0da8f31c368cbc0eea94',1,'FLASH_OTP_BASE: stm32f407xx_matlab.h']]], - ['flash_5fotp_5fbase_5fshift_145',['FLASH_OTP_BASE_SHIFT',['../group___peripheral__memory__map.html#ga1ea2ceeb2a729bb1072d98cf7c3ceb6e',1,'stm32f407xx_matlab.h']]], - ['flash_5fotp_5fend_146',['FLASH_OTP_END',['../group___peripheral__memory__map.html#ga5bec9c5a91e312fca36f256f508ceee1',1,'stm32f407xx_matlab.h']]], - ['flash_5fotp_5fend_5fshift_147',['FLASH_OTP_END_SHIFT',['../group___peripheral__memory__map.html#ga46ebe9214ddc2503af753a11fd5ccb80',1,'stm32f407xx_matlab.h']]], - ['flash_5fotp_5fsize_148',['FLASH_OTP_SIZE',['../group___peripheral__memory__map.html#gacb3e2951c91f038686e0cbcd4321814b',1,'stm32f407xx_matlab.h']]], - ['flash_5fr_149',['flash_r',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga9005724fdcdcbb61e849a94a8068d0a5',1,'stm32f4xx_periph_registers.c']]], - ['flash_5fr_5fbase_150',['FLASH_R_BASE',['../group___peripheral__memory__map.html#ga8e21f4845015730c5731763169ec0e9b',1,'stm32f407xx_matlab.h']]], - ['flash_5fscale1_5flatency1_5ffreq_151',['FLASH_SCALE1_LATENCY1_FREQ',['../group___exported__macros.html#ga980965268c210a75ca5bb1e6b59b4052',1,'stm32f407xx_matlab.h']]], - ['flash_5fscale1_5flatency2_5ffreq_152',['FLASH_SCALE1_LATENCY2_FREQ',['../group___exported__macros.html#ga53673600707f291baa71c30919f8da98',1,'stm32f407xx_matlab.h']]], - ['flash_5fscale1_5flatency3_5ffreq_153',['FLASH_SCALE1_LATENCY3_FREQ',['../group___exported__macros.html#ga547cb8d59cf6a2a73a0f76331e4492df',1,'stm32f407xx_matlab.h']]], - ['flash_5fscale1_5flatency4_5ffreq_154',['FLASH_SCALE1_LATENCY4_FREQ',['../group___exported__macros.html#ga600fe88d1dfa0faef16947e24f52e84e',1,'stm32f407xx_matlab.h']]], - ['flash_5fscale1_5flatency5_5ffreq_155',['FLASH_SCALE1_LATENCY5_FREQ',['../group___exported__macros.html#gaf576f3543b7909cf6c889e05829d37a0',1,'stm32f407xx_matlab.h']]], - ['flash_5fscale2_5flatency1_5ffreq_156',['FLASH_SCALE2_LATENCY1_FREQ',['../group___exported__macros.html#ga19ba80e0c72cd041274f831901f302f9',1,'stm32f407xx_matlab.h']]], - ['flash_5fscale2_5flatency2_5ffreq_157',['FLASH_SCALE2_LATENCY2_FREQ',['../group___exported__macros.html#ga98847021d5de23ea0458b490c74e6299',1,'stm32f407xx_matlab.h']]], - ['flash_5fscale2_5flatency3_5ffreq_158',['FLASH_SCALE2_LATENCY3_FREQ',['../group___exported__macros.html#ga6956d1ea5f9484a43213022ebff8cf03',1,'stm32f407xx_matlab.h']]], - ['flash_5fscale2_5flatency4_5ffreq_159',['FLASH_SCALE2_LATENCY4_FREQ',['../group___exported__macros.html#ga8fc5a396df42d76fb41f377e71513ecb',1,'stm32f407xx_matlab.h']]], - ['flash_5fsize_160',['FLASH_SIZE',['../group___peripheral__memory__map.html#gae69620948dea1b76e0ab7843ab719db7',1,'stm32f407xx_matlab.h']]], - ['flash_5fsr_5fbsy_161',['FLASH_SR_BSY',['../group___peripheral___registers___bits___definition.html#ga4b86181a96fd2f1cc3828e9d8d83d368',1,'stm32f407xx_matlab.h']]], - ['flash_5fsr_5fbsy_5fmsk_162',['FLASH_SR_BSY_Msk',['../group___peripheral___registers___bits___definition.html#ga3564806c8fbd6e0b6ddde539c3e37045',1,'stm32f407xx_matlab.h']]], - ['flash_5fsr_5fbsy_5fpos_163',['FLASH_SR_BSY_Pos',['../group___peripheral___registers___bits___definition.html#ga1fff488dcd0ba14694a05d8c061441e0',1,'stm32f407xx_matlab.h']]], - ['flash_5fsr_5feop_164',['FLASH_SR_EOP',['../group___peripheral___registers___bits___definition.html#gae1301c6b487cfefa247c54a576a0c12b',1,'stm32f407xx_matlab.h']]], - ['flash_5fsr_5feop_5fmsk_165',['FLASH_SR_EOP_Msk',['../group___peripheral___registers___bits___definition.html#ga386f68b5d2c3622b29811577932360ed',1,'stm32f407xx_matlab.h']]], - ['flash_5fsr_5feop_5fpos_166',['FLASH_SR_EOP_Pos',['../group___peripheral___registers___bits___definition.html#ga2013e875c4c210b820e502feea6c9fb1',1,'stm32f407xx_matlab.h']]], - ['flash_5fsr_5fpgaerr_167',['FLASH_SR_PGAERR',['../group___peripheral___registers___bits___definition.html#gac98c2458e114e7f419f3222673878ce0',1,'stm32f407xx_matlab.h']]], - ['flash_5fsr_5fpgaerr_5fmsk_168',['FLASH_SR_PGAERR_Msk',['../group___peripheral___registers___bits___definition.html#ga433ad5d791f6ffcb202165a0131d00de',1,'stm32f407xx_matlab.h']]], - ['flash_5fsr_5fpgaerr_5fpos_169',['FLASH_SR_PGAERR_Pos',['../group___peripheral___registers___bits___definition.html#ga1e91ef00a66f31c28b41f990b0a5b57f',1,'stm32f407xx_matlab.h']]], - ['flash_5fsr_5fpgperr_170',['FLASH_SR_PGPERR',['../group___peripheral___registers___bits___definition.html#ga7fd2704724528be959f82089f67e3869',1,'stm32f407xx_matlab.h']]], - ['flash_5fsr_5fpgperr_5fmsk_171',['FLASH_SR_PGPERR_Msk',['../group___peripheral___registers___bits___definition.html#ga6caf6ab98ec1dd59205297dcf582c945',1,'stm32f407xx_matlab.h']]], - ['flash_5fsr_5fpgperr_5fpos_172',['FLASH_SR_PGPERR_Pos',['../group___peripheral___registers___bits___definition.html#gac07140ebffc87a7d5c0e006e9753bc12',1,'stm32f407xx_matlab.h']]], - ['flash_5fsr_5fpgserr_173',['FLASH_SR_PGSERR',['../group___peripheral___registers___bits___definition.html#ga5d76ad3629a288bee0136b8b34f274f4',1,'stm32f407xx_matlab.h']]], - ['flash_5fsr_5fpgserr_5fmsk_174',['FLASH_SR_PGSERR_Msk',['../group___peripheral___registers___bits___definition.html#gaf315476e1c4d69765908a72e0d1946be',1,'stm32f407xx_matlab.h']]], - ['flash_5fsr_5fpgserr_5fpos_175',['FLASH_SR_PGSERR_Pos',['../group___peripheral___registers___bits___definition.html#gaa714dc154587b83701170e6795646f36',1,'stm32f407xx_matlab.h']]], - ['flash_5fsr_5fsop_176',['FLASH_SR_SOP',['../group___peripheral___registers___bits___definition.html#gab779aa8b88258e15c183041744a846ff',1,'stm32f407xx_matlab.h']]], - ['flash_5fsr_5fsop_5fmsk_177',['FLASH_SR_SOP_Msk',['../group___peripheral___registers___bits___definition.html#gadd0272b01aaf5f6f7d69cd5906f3d755',1,'stm32f407xx_matlab.h']]], - ['flash_5fsr_5fsop_5fpos_178',['FLASH_SR_SOP_Pos',['../group___peripheral___registers___bits___definition.html#ga4af97243ceb7ddfa34b7c3882c41b306',1,'stm32f407xx_matlab.h']]], - ['flash_5fsr_5fwrperr_179',['FLASH_SR_WRPERR',['../group___peripheral___registers___bits___definition.html#gabf6f52f59b01530928d747cf32bd4d01',1,'stm32f407xx_matlab.h']]], - ['flash_5fsr_5fwrperr_5fmsk_180',['FLASH_SR_WRPERR_Msk',['../group___peripheral___registers___bits___definition.html#ga65a2ec1cfe4fece014bacf2c1332e659',1,'stm32f407xx_matlab.h']]], - ['flash_5fsr_5fwrperr_5fpos_181',['FLASH_SR_WRPERR_Pos',['../group___peripheral___registers___bits___definition.html#gace591108151f52fd0f18273c00403b80',1,'stm32f407xx_matlab.h']]], - ['flash_5ftypedef_182',['FLASH_TypeDef',['../struct_f_l_a_s_h___type_def.html',1,'']]], - ['flashsize_5fbase_183',['FLASHSIZE_BASE',['../group___peripheral__memory__map.html#ga776d985f2d4d40b588ef6ca9d573af78',1,'stm32f407xx_matlab.h']]], - ['floating_20point_20unit_20fpu_184',['Floating Point Unit (FPU)',['../group___c_m_s_i_s___f_p_u.html',1,'']]], - ['fm1r_185',['FM1R',['../group___c_m_s_i_s___device.html#gaaa6f4cf1f16aaa6d17ec6c410db76acf',1,'CAN_TypeDef']]], - ['fmc_5firqhandler_186',['FMC_IRQHandler',['../group___exported__macros.html#ga3dec035cce31cf17473f915dade1ca25',1,'stm32f407xx_matlab.h']]], - ['fmc_5firqn_187',['FMC_IRQn',['../group___exported__macros.html#ga1452f42f926ec3886d3688352472f960',1,'stm32f407xx_matlab.h']]], - ['fmcu_5fstop_188',['fMCU_Stop',['../struct_s_i_m_____m_c_u_handle_type_def.html#ad81f091fd8c1ad2908a5dd5967f3322e',1,'SIM__MCUHandleTypeDef']]], - ['fmr_189',['FMR',['../group___c_m_s_i_s___device.html#ga1cb734df34f6520a7204c4c70634ebba',1,'CAN_TypeDef']]], - ['foldcnt_190',['FOLDCNT',['../group___c_m_s_i_s__core___debug_functions.html#ga6324c1fbf6c94f1eaf742d09ad678216',1,'DWT_Type']]], - ['fpca_191',['FPCA',['../group___c_m_s_i_s__core___debug_functions.html#ga2518558c090f60161ba4e718a54ee468',1,'CONTROL_Type::FPCA'],['../group___c_m_s_i_s__core___debug_functions.html#ga2518558c090f60161ba4e718a54ee468',1,'CONTROL_Type::@3::FPCA']]], - ['fpcar_192',['FPCAR',['../group___c_m_s_i_s__core___debug_functions.html#ga4fa83b560b046f9cec201c68fbe33507',1,'FPU_Type']]], - ['fpccr_193',['FPCCR',['../group___c_m_s_i_s__core___debug_functions.html#ga242040bad11980d6250848a44cc967e3',1,'FPU_Type']]], - ['fpdscr_194',['FPDSCR',['../group___c_m_s_i_s__core___debug_functions.html#ga05a8c9a999e6ca4ff19f30c93ec50217',1,'FPU_Type']]], - ['fpu_195',['FPU',['../group___c_m_s_i_s___f_p_u.html',1,'Floating Point Unit (FPU)'],['../group___c_m_s_i_s__core__base.html#gabc7c93f2594e85ece1e1a24f10591428',1,'FPU: core_cm4_matlab.h']]], - ['fpu_20functions_196',['FPU Functions',['../group___c_m_s_i_s___core___fpu_functions.html',1,'']]], - ['fpu_5fbase_197',['FPU_BASE',['../group___c_m_s_i_s__core__base.html#ga4dcad4027118c098c07bcd575f1fbb28',1,'core_cm4_matlab.h']]], - ['fpu_5ffpcar_5faddress_5fmsk_198',['FPU_FPCAR_ADDRESS_Msk',['../group___c_m_s_i_s___f_p_u.html#ga517d89370c81325c5387b9c3085ac554',1,'core_cm4_matlab.h']]], - ['fpu_5ffpcar_5faddress_5fpos_199',['FPU_FPCAR_ADDRESS_Pos',['../group___c_m_s_i_s___f_p_u.html#gaf45377b7e45be8517ddbcf2028b80ae7',1,'core_cm4_matlab.h']]], - ['fpu_5ffpccr_5faspen_5fmsk_200',['FPU_FPCCR_ASPEN_Msk',['../group___c_m_s_i_s___f_p_u.html#ga309886ff6bbd25cb13c061c6683c6c0c',1,'core_cm4_matlab.h']]], - ['fpu_5ffpccr_5faspen_5fpos_201',['FPU_FPCCR_ASPEN_Pos',['../group___c_m_s_i_s___f_p_u.html#ga4228a923ddf665f868e56b4b9e9bff7b',1,'core_cm4_matlab.h']]], - ['fpu_5ffpccr_5fbfrdy_5fmsk_202',['FPU_FPCCR_BFRDY_Msk',['../group___c_m_s_i_s___f_p_u.html#gad349eb1323d8399d54a04c0bfd520cb2',1,'core_cm4_matlab.h']]], - ['fpu_5ffpccr_5fbfrdy_5fpos_203',['FPU_FPCCR_BFRDY_Pos',['../group___c_m_s_i_s___f_p_u.html#ga6d633920f92c3ce4133d769701619b17',1,'core_cm4_matlab.h']]], - ['fpu_5ffpccr_5fhfrdy_5fmsk_204',['FPU_FPCCR_HFRDY_Msk',['../group___c_m_s_i_s___f_p_u.html#gaf4beaa279abff34828344bd594fff8a1',1,'core_cm4_matlab.h']]], - ['fpu_5ffpccr_5fhfrdy_5fpos_205',['FPU_FPCCR_HFRDY_Pos',['../group___c_m_s_i_s___f_p_u.html#gab12733991487acc2da41ca300fe36fb6',1,'core_cm4_matlab.h']]], - ['fpu_5ffpccr_5flspact_5fmsk_206',['FPU_FPCCR_LSPACT_Msk',['../group___c_m_s_i_s___f_p_u.html#ga86e7c2fa52ba65c3b535dfa33f2586eb',1,'core_cm4_matlab.h']]], - ['fpu_5ffpccr_5flspact_5fpos_207',['FPU_FPCCR_LSPACT_Pos',['../group___c_m_s_i_s___f_p_u.html#ga803bf3f6d15b04deaad0801bee5b35ed',1,'core_cm4_matlab.h']]], - ['fpu_5ffpccr_5flspen_5fmsk_208',['FPU_FPCCR_LSPEN_Msk',['../group___c_m_s_i_s___f_p_u.html#gaf4ab19de45df6522dd882bc116f938e9',1,'core_cm4_matlab.h']]], - ['fpu_5ffpccr_5flspen_5fpos_209',['FPU_FPCCR_LSPEN_Pos',['../group___c_m_s_i_s___f_p_u.html#gac7d70e051fe759ad8fed83bf5b5aebc1',1,'core_cm4_matlab.h']]], - ['fpu_5ffpccr_5fmmrdy_5fmsk_210',['FPU_FPCCR_MMRDY_Msk',['../group___c_m_s_i_s___f_p_u.html#gadedfaec9fdd07261573e823a4dcfb5c4',1,'core_cm4_matlab.h']]], - ['fpu_5ffpccr_5fmmrdy_5fpos_211',['FPU_FPCCR_MMRDY_Pos',['../group___c_m_s_i_s___f_p_u.html#gaccdb481211629f9440431439231187f1',1,'core_cm4_matlab.h']]], - ['fpu_5ffpccr_5fmonrdy_5fmsk_212',['FPU_FPCCR_MONRDY_Msk',['../group___c_m_s_i_s___f_p_u.html#ga42067729a887081cf56b8fe1029be7a1',1,'core_cm4_matlab.h']]], - ['fpu_5ffpccr_5fmonrdy_5fpos_213',['FPU_FPCCR_MONRDY_Pos',['../group___c_m_s_i_s___f_p_u.html#gae0a4effc79209d821ded517c2be326ba',1,'core_cm4_matlab.h']]], - ['fpu_5ffpccr_5fthread_5fmsk_214',['FPU_FPCCR_THREAD_Msk',['../group___c_m_s_i_s___f_p_u.html#ga8d18cd88336d63d4b1810383aa8da700',1,'core_cm4_matlab.h']]], - ['fpu_5ffpccr_5fthread_5fpos_215',['FPU_FPCCR_THREAD_Pos',['../group___c_m_s_i_s___f_p_u.html#ga0937d64c42374200af44b22e5b49fd26',1,'core_cm4_matlab.h']]], - ['fpu_5ffpccr_5fuser_5fmsk_216',['FPU_FPCCR_USER_Msk',['../group___c_m_s_i_s___f_p_u.html#ga2eb70427eeaa7344196219cf5a8620a4',1,'core_cm4_matlab.h']]], - ['fpu_5ffpccr_5fuser_5fpos_217',['FPU_FPCCR_USER_Pos',['../group___c_m_s_i_s___f_p_u.html#gaea663104375ce6be15470e3db294c92d',1,'core_cm4_matlab.h']]], - ['fpu_5ffpdscr_5fahp_5fmsk_218',['FPU_FPDSCR_AHP_Msk',['../group___c_m_s_i_s___f_p_u.html#gab2789cebebda5fda8c4e9d87e24f32be',1,'core_cm4_matlab.h']]], - ['fpu_5ffpdscr_5fahp_5fpos_219',['FPU_FPDSCR_AHP_Pos',['../group___c_m_s_i_s___f_p_u.html#ga138f54bc002629ab3e4de814c58abb29',1,'core_cm4_matlab.h']]], - ['fpu_5ffpdscr_5fdn_5fmsk_220',['FPU_FPDSCR_DN_Msk',['../group___c_m_s_i_s___f_p_u.html#ga40c2d4a297ca2ceffe174703a4ad17f6',1,'core_cm4_matlab.h']]], - ['fpu_5ffpdscr_5fdn_5fpos_221',['FPU_FPDSCR_DN_Pos',['../group___c_m_s_i_s___f_p_u.html#ga41776b80fa450ef2ea6d3fee89aa35f2',1,'core_cm4_matlab.h']]], - ['fpu_5ffpdscr_5ffz_5fmsk_222',['FPU_FPDSCR_FZ_Msk',['../group___c_m_s_i_s___f_p_u.html#gaae7d901442d4af97c6d22939cffc8ad9',1,'core_cm4_matlab.h']]], - ['fpu_5ffpdscr_5ffz_5fpos_223',['FPU_FPDSCR_FZ_Pos',['../group___c_m_s_i_s___f_p_u.html#gab3c2fc96e312ba47b902d5f80d9b8575',1,'core_cm4_matlab.h']]], - ['fpu_5ffpdscr_5frmode_5fmsk_224',['FPU_FPDSCR_RMode_Msk',['../group___c_m_s_i_s___f_p_u.html#ga449beb50211f8e97df6b2640c82c4741',1,'core_cm4_matlab.h']]], - ['fpu_5ffpdscr_5frmode_5fpos_225',['FPU_FPDSCR_RMode_Pos',['../group___c_m_s_i_s___f_p_u.html#ga7aeedf36be8f170dd3e276028e8e29ed',1,'core_cm4_matlab.h']]], - ['fpu_5firqn_226',['FPU_IRQn',['../group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8aa6b8ff01b016a798c6e639728c179e4f',1,'stm32f407xx_matlab.h']]], - ['fpu_5fmvfr0_5fa_5fsimd_5fregisters_5fmsk_227',['FPU_MVFR0_A_SIMD_registers_Msk',['../group___c_m_s_i_s___f_p_u.html#ga118f13f9562805356e92b5ad52573021',1,'core_cm4_matlab.h']]], - ['fpu_5fmvfr0_5fa_5fsimd_5fregisters_5fpos_228',['FPU_MVFR0_A_SIMD_registers_Pos',['../group___c_m_s_i_s___f_p_u.html#gaa1de44af3e3162c8c176a57564611618',1,'core_cm4_matlab.h']]], - ['fpu_5fmvfr0_5fdivide_5fmsk_229',['FPU_MVFR0_Divide_Msk',['../group___c_m_s_i_s___f_p_u.html#gaeb7370768c6cdf06f8a15c86c6102ed2',1,'core_cm4_matlab.h']]], - ['fpu_5fmvfr0_5fdivide_5fpos_230',['FPU_MVFR0_Divide_Pos',['../group___c_m_s_i_s___f_p_u.html#ga167be203091e6cc7d00ad40ca48c4396',1,'core_cm4_matlab.h']]], - ['fpu_5fmvfr0_5fdouble_5fprecision_5fmsk_231',['FPU_MVFR0_Double_precision_Msk',['../group___c_m_s_i_s___f_p_u.html#ga3f2c8c6c759ffe70f548a165602ea901',1,'core_cm4_matlab.h']]], - ['fpu_5fmvfr0_5fdouble_5fprecision_5fpos_232',['FPU_MVFR0_Double_precision_Pos',['../group___c_m_s_i_s___f_p_u.html#ga461e26147be0c39402a78cb6249e8f84',1,'core_cm4_matlab.h']]], - ['fpu_5fmvfr0_5ffp_5fexcep_5ftrapping_5fmsk_233',['FPU_MVFR0_FP_excep_trapping_Msk',['../group___c_m_s_i_s___f_p_u.html#ga29bbddd679e821e050699fda23e6c85e',1,'core_cm4_matlab.h']]], - ['fpu_5fmvfr0_5ffp_5fexcep_5ftrapping_5fpos_234',['FPU_MVFR0_FP_excep_trapping_Pos',['../group___c_m_s_i_s___f_p_u.html#ga5c0715c41c4470f8bb0b6dcd34707f1c',1,'core_cm4_matlab.h']]], - ['fpu_5fmvfr0_5ffp_5frounding_5fmodes_5fmsk_235',['FPU_MVFR0_FP_rounding_modes_Msk',['../group___c_m_s_i_s___f_p_u.html#gae6dc9339ac72227d5d54360bb9fbef1b',1,'core_cm4_matlab.h']]], - ['fpu_5fmvfr0_5ffp_5frounding_5fmodes_5fpos_236',['FPU_MVFR0_FP_rounding_modes_Pos',['../group___c_m_s_i_s___f_p_u.html#ga1ebcc9076f08013f0ea814540df03e82',1,'core_cm4_matlab.h']]], - ['fpu_5fmvfr0_5fshort_5fvectors_5fmsk_237',['FPU_MVFR0_Short_vectors_Msk',['../group___c_m_s_i_s___f_p_u.html#gabf261a72023fdfc64f32c6b21d55c5b9',1,'core_cm4_matlab.h']]], - ['fpu_5fmvfr0_5fshort_5fvectors_5fpos_238',['FPU_MVFR0_Short_vectors_Pos',['../group___c_m_s_i_s___f_p_u.html#gabbf83a918536ebf10889cee71a0404c7',1,'core_cm4_matlab.h']]], - ['fpu_5fmvfr0_5fsingle_5fprecision_5fmsk_239',['FPU_MVFR0_Single_precision_Msk',['../group___c_m_s_i_s___f_p_u.html#ga95008f205c9d25e4ffebdbdc50d5ae44',1,'core_cm4_matlab.h']]], - ['fpu_5fmvfr0_5fsingle_5fprecision_5fpos_240',['FPU_MVFR0_Single_precision_Pos',['../group___c_m_s_i_s___f_p_u.html#ga1b4e9fe31992b1495c7a158747d42571',1,'core_cm4_matlab.h']]], - ['fpu_5fmvfr0_5fsquare_5froot_5fmsk_241',['FPU_MVFR0_Square_root_Msk',['../group___c_m_s_i_s___f_p_u.html#ga3ec0bfec1640bdaf9dff027f275b446d',1,'core_cm4_matlab.h']]], - ['fpu_5fmvfr0_5fsquare_5froot_5fpos_242',['FPU_MVFR0_Square_root_Pos',['../group___c_m_s_i_s___f_p_u.html#ga176c85453ba03257bf263adec05f7344',1,'core_cm4_matlab.h']]], - ['fpu_5fmvfr1_5fd_5fnan_5fmode_5fmsk_243',['FPU_MVFR1_D_NaN_mode_Msk',['../group___c_m_s_i_s___f_p_u.html#gad6af7c4632dba5a417307d456fe9b8a7',1,'core_cm4_matlab.h']]], - ['fpu_5fmvfr1_5fd_5fnan_5fmode_5fpos_244',['FPU_MVFR1_D_NaN_mode_Pos',['../group___c_m_s_i_s___f_p_u.html#gae34d7ce42e50e2f1ea3e654fd3ba690a',1,'core_cm4_matlab.h']]], - ['fpu_5fmvfr1_5ffp_5ffused_5fmac_5fmsk_245',['FPU_MVFR1_FP_fused_MAC_Msk',['../group___c_m_s_i_s___f_p_u.html#gaf5129ab18948ff573a1ab29f0be47bc2',1,'core_cm4_matlab.h']]], - ['fpu_5fmvfr1_5ffp_5ffused_5fmac_5fpos_246',['FPU_MVFR1_FP_fused_MAC_Pos',['../group___c_m_s_i_s___f_p_u.html#ga68c53771f02f4c73122a7b40796549cc',1,'core_cm4_matlab.h']]], - ['fpu_5fmvfr1_5ffp_5fhpfp_5fmsk_247',['FPU_MVFR1_FP_HPFP_Msk',['../group___c_m_s_i_s___f_p_u.html#gafe29dd327ed3b723b3f01759568e116d',1,'core_cm4_matlab.h']]], - ['fpu_5fmvfr1_5ffp_5fhpfp_5fpos_248',['FPU_MVFR1_FP_HPFP_Pos',['../group___c_m_s_i_s___f_p_u.html#ga02ceac0abcbdc8670633056bec005bfd',1,'core_cm4_matlab.h']]], - ['fpu_5fmvfr1_5fftz_5fmode_5fmsk_249',['FPU_MVFR1_FtZ_mode_Msk',['../group___c_m_s_i_s___f_p_u.html#gac566bde39a7afcceffbb21d830c269c1',1,'core_cm4_matlab.h']]], - ['fpu_5fmvfr1_5fftz_5fmode_5fpos_250',['FPU_MVFR1_FtZ_mode_Pos',['../group___c_m_s_i_s___f_p_u.html#ga7faa5bfa85036f8511793234cbbc2409',1,'core_cm4_matlab.h']]], - ['fpu_5ftype_251',['FPU_Type',['../struct_f_p_u___type.html',1,'']]], - ['fr1_252',['FR1',['../group___c_m_s_i_s___device.html#ga92036953ac673803fe001d843fea508b',1,'CAN_FilterRegister_TypeDef']]], - ['fr2_253',['FR2',['../group___c_m_s_i_s___device.html#ga7f7d80b45b7574463d7030fc8a464582',1,'CAN_FilterRegister_TypeDef']]], - ['fs1r_254',['FS1R',['../group___c_m_s_i_s___device.html#gaae0256ae42106ee7f87fc7e5bdb779d4',1,'CAN_TypeDef']]], - ['fscr_255',['FSCR',['../group___c_m_s_i_s__core___debug_functions.html#ga36370b2b0879b7b497f6dd854ba02873',1,'TPI_Type']]], - ['fsmc_5fbank1_256',['FSMC_Bank1',['../group___peripheral__declaration.html#ga2a759bad07fe730c99f9e1490e646220',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbank1_5fr_257',['fsmc_bank1_r',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#gabc182d46d8d7866f89db2e17f7d67496',1,'stm32f4xx_periph_registers.c']]], - ['fsmc_5fbank1_5fr_5fbase_258',['FSMC_Bank1_R_BASE',['../group___peripheral__memory__map.html#gad196fe6f5e4041b201d14f43508c06d2',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbank1_5ftypedef_259',['FSMC_Bank1_TypeDef',['../struct_f_s_m_c___bank1___type_def.html',1,'']]], - ['fsmc_5fbank1e_260',['FSMC_Bank1E',['../group___peripheral__declaration.html#ga422986101f42a8811ae89ac69deb2759',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbank1e_5fr_261',['fsmc_bank1e_r',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#gac5d854d8ad94b3865847d64044c9bec8',1,'stm32f4xx_periph_registers.c']]], - ['fsmc_5fbank1e_5fr_5fbase_262',['FSMC_Bank1E_R_BASE',['../group___peripheral__memory__map.html#gaea182589c84aee30b7f735474d8774e2',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbank1e_5ftypedef_263',['FSMC_Bank1E_TypeDef',['../struct_f_s_m_c___bank1_e___type_def.html',1,'']]], - ['fsmc_5fbank2_5f3_264',['FSMC_Bank2_3',['../group___peripheral__declaration.html#ga37d7365ac249959b103d7b91d74e776d',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbank2_5f3_5fr_265',['fsmc_bank2_3_r',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga337be35abe408bd089d87060903b944f',1,'stm32f4xx_periph_registers.c']]], - ['fsmc_5fbank2_5f3_5fr_5fbase_266',['FSMC_Bank2_3_R_BASE',['../group___peripheral__memory__map.html#ga851707a200f63e03c336073706fdce1d',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbank2_5f3_5ftypedef_267',['FSMC_Bank2_3_TypeDef',['../struct_f_s_m_c___bank2__3___type_def.html',1,'']]], - ['fsmc_5fbank4_268',['FSMC_Bank4',['../group___peripheral__declaration.html#ga5aa00e4ac522693c6a21bc23ef5a96df',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbank4_5fr_269',['fsmc_bank4_r',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga86a7b6923c554282c949627ccaaee51b',1,'stm32f4xx_periph_registers.c']]], - ['fsmc_5fbank4_5fr_5fbase_270',['FSMC_Bank4_R_BASE',['../group___peripheral__memory__map.html#gaf9e5417133160b0bdd0498d982acec19',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbank4_5ftypedef_271',['FSMC_Bank4_TypeDef',['../struct_f_s_m_c___bank4___type_def.html',1,'']]], - ['fsmc_5fbcr1_5fasyncwait_272',['FSMC_BCR1_ASYNCWAIT',['../group___peripheral___registers___bits___definition.html#gaf5673d96c0fb27c7faed335e05ad41c1',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr1_5fasyncwait_5fmsk_273',['FSMC_BCR1_ASYNCWAIT_Msk',['../group___peripheral___registers___bits___definition.html#gaf2587d2fc09a87653afa500cc77ce010',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr1_5fasyncwait_5fpos_274',['FSMC_BCR1_ASYNCWAIT_Pos',['../group___peripheral___registers___bits___definition.html#ga49520648ee432b57ad212494763df6f0',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr1_5fbursten_275',['FSMC_BCR1_BURSTEN',['../group___peripheral___registers___bits___definition.html#ga94857a0177ae12f1172da65d8708ae97',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr1_5fbursten_5fmsk_276',['FSMC_BCR1_BURSTEN_Msk',['../group___peripheral___registers___bits___definition.html#ga093941fc5df6f3d174d23a4863be87c3',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr1_5fbursten_5fpos_277',['FSMC_BCR1_BURSTEN_Pos',['../group___peripheral___registers___bits___definition.html#gabd79d1d9b9be97259d21184a38b79e78',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr1_5fcburstrw_278',['FSMC_BCR1_CBURSTRW',['../group___peripheral___registers___bits___definition.html#ga015672f5aa2132a55e316f5b7a577174',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr1_5fcburstrw_5fmsk_279',['FSMC_BCR1_CBURSTRW_Msk',['../group___peripheral___registers___bits___definition.html#ga56ae50002811cf51dce4cb26da2a18bb',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr1_5fcburstrw_5fpos_280',['FSMC_BCR1_CBURSTRW_Pos',['../group___peripheral___registers___bits___definition.html#ga92b8ede1953ab41ab13d6a6d62953ffa',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr1_5fcpsize_281',['FSMC_BCR1_CPSIZE',['../group___peripheral___registers___bits___definition.html#ga192791b6dc4c25e4992b07f098006a4e',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr1_5fcpsize_5f0_282',['FSMC_BCR1_CPSIZE_0',['../group___peripheral___registers___bits___definition.html#ga90f6d13b70b5cadaf0325336ffa204c2',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr1_5fcpsize_5f1_283',['FSMC_BCR1_CPSIZE_1',['../group___peripheral___registers___bits___definition.html#ga23f9cde76aa0df2b76bec396614542d2',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr1_5fcpsize_5f2_284',['FSMC_BCR1_CPSIZE_2',['../group___peripheral___registers___bits___definition.html#ga6b7e96850fe4f75e4ad878696ef94356',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr1_5fcpsize_5fmsk_285',['FSMC_BCR1_CPSIZE_Msk',['../group___peripheral___registers___bits___definition.html#ga10293af49314e88488ceb0d3e0faa53a',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr1_5fcpsize_5fpos_286',['FSMC_BCR1_CPSIZE_Pos',['../group___peripheral___registers___bits___definition.html#ga150c6b16ddf3ab16470062b3aa651c42',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr1_5fextmod_287',['FSMC_BCR1_EXTMOD',['../group___peripheral___registers___bits___definition.html#ga7936ff74a1cfba880a9b5bc943dc8661',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr1_5fextmod_5fmsk_288',['FSMC_BCR1_EXTMOD_Msk',['../group___peripheral___registers___bits___definition.html#ga59c8fad26fdda8528641ccde63012333',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr1_5fextmod_5fpos_289',['FSMC_BCR1_EXTMOD_Pos',['../group___peripheral___registers___bits___definition.html#ga8b6b842527b6be91baf209d302c0dcb2',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr1_5ffaccen_290',['FSMC_BCR1_FACCEN',['../group___peripheral___registers___bits___definition.html#ga14aaca2a8bccab73c7726cf73ee9be16',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr1_5ffaccen_5fmsk_291',['FSMC_BCR1_FACCEN_Msk',['../group___peripheral___registers___bits___definition.html#ga5822754c7aa0947d0b6623d884438f0e',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr1_5ffaccen_5fpos_292',['FSMC_BCR1_FACCEN_Pos',['../group___peripheral___registers___bits___definition.html#ga955890b4486255e510806f000bb44f43',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr1_5fmbken_293',['FSMC_BCR1_MBKEN',['../group___peripheral___registers___bits___definition.html#gad154cab86ce34cebfe1f76e5c2f78e61',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr1_5fmbken_5fmsk_294',['FSMC_BCR1_MBKEN_Msk',['../group___peripheral___registers___bits___definition.html#ga1fb54a74314811fa88d317a79004527c',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr1_5fmbken_5fpos_295',['FSMC_BCR1_MBKEN_Pos',['../group___peripheral___registers___bits___definition.html#gabdb4fdc15ea8091df00881c342b88eda',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr1_5fmtyp_296',['FSMC_BCR1_MTYP',['../group___peripheral___registers___bits___definition.html#ga9bab7a47703902d187502ac765ebb05d',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr1_5fmtyp_5f0_297',['FSMC_BCR1_MTYP_0',['../group___peripheral___registers___bits___definition.html#ga29b921567bd5a422c51f9a0f426ac3f6',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr1_5fmtyp_5f1_298',['FSMC_BCR1_MTYP_1',['../group___peripheral___registers___bits___definition.html#ga3fe2fd14b3c0d88aecfb9cf5b44995a0',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr1_5fmtyp_5fmsk_299',['FSMC_BCR1_MTYP_Msk',['../group___peripheral___registers___bits___definition.html#ga76cf34bfdd2f5d9a7959fee17050319f',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr1_5fmtyp_5fpos_300',['FSMC_BCR1_MTYP_Pos',['../group___peripheral___registers___bits___definition.html#gacf7fa08d310f1b3d957f0600375b3c87',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr1_5fmuxen_301',['FSMC_BCR1_MUXEN',['../group___peripheral___registers___bits___definition.html#ga28dd9f93d8687cdc08745df9fcc38e89',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr1_5fmuxen_5fmsk_302',['FSMC_BCR1_MUXEN_Msk',['../group___peripheral___registers___bits___definition.html#ga1346d0cf99bad4d9863fd777d1930d6c',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr1_5fmuxen_5fpos_303',['FSMC_BCR1_MUXEN_Pos',['../group___peripheral___registers___bits___definition.html#ga13b709c2443de9ab40dadc6830f31158',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr1_5fmwid_304',['FSMC_BCR1_MWID',['../group___peripheral___registers___bits___definition.html#gaa12297787a0580fedbd5244f0caa0a76',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr1_5fmwid_5f0_305',['FSMC_BCR1_MWID_0',['../group___peripheral___registers___bits___definition.html#ga1a6fe3b4b28a31c4bbf26a838695fd0c',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr1_5fmwid_5f1_306',['FSMC_BCR1_MWID_1',['../group___peripheral___registers___bits___definition.html#ga65592a6a20efa6aed5b59fe1eba508d8',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr1_5fmwid_5fmsk_307',['FSMC_BCR1_MWID_Msk',['../group___peripheral___registers___bits___definition.html#ga5e42eb74853897be5a39fe4e8549d166',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr1_5fmwid_5fpos_308',['FSMC_BCR1_MWID_Pos',['../group___peripheral___registers___bits___definition.html#ga5ec03e929628fb56d95403641ec23ac0',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr1_5fwaitcfg_309',['FSMC_BCR1_WAITCFG',['../group___peripheral___registers___bits___definition.html#ga141a337e3f1479e79d62b567ba685bcf',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr1_5fwaitcfg_5fmsk_310',['FSMC_BCR1_WAITCFG_Msk',['../group___peripheral___registers___bits___definition.html#gacccfccbca149c2df3ec50918bcb5822e',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr1_5fwaitcfg_5fpos_311',['FSMC_BCR1_WAITCFG_Pos',['../group___peripheral___registers___bits___definition.html#gaa37e744f19838aaaaa33e3184d68904e',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr1_5fwaiten_312',['FSMC_BCR1_WAITEN',['../group___peripheral___registers___bits___definition.html#gabe4611a02a4fa635b66d5b5e52328fc5',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr1_5fwaiten_5fmsk_313',['FSMC_BCR1_WAITEN_Msk',['../group___peripheral___registers___bits___definition.html#ga423ede6efc2a21e6a832faf9154df8a0',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr1_5fwaiten_5fpos_314',['FSMC_BCR1_WAITEN_Pos',['../group___peripheral___registers___bits___definition.html#ga0a3407dc3470cd1ced7fd05ffb11159b',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr1_5fwaitpol_315',['FSMC_BCR1_WAITPOL',['../group___peripheral___registers___bits___definition.html#ga57dbc565fbc7d8ec20fda7ef0da30df4',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr1_5fwaitpol_5fmsk_316',['FSMC_BCR1_WAITPOL_Msk',['../group___peripheral___registers___bits___definition.html#ga66ec261e040de2455880252747ec2954',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr1_5fwaitpol_5fpos_317',['FSMC_BCR1_WAITPOL_Pos',['../group___peripheral___registers___bits___definition.html#gaa688dcd0dc2b3c072f353941a5cb8c63',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr1_5fwrapmod_318',['FSMC_BCR1_WRAPMOD',['../group___peripheral___registers___bits___definition.html#gad215e95feee8339393bd93a2bcea11f1',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr1_5fwrapmod_5fmsk_319',['FSMC_BCR1_WRAPMOD_Msk',['../group___peripheral___registers___bits___definition.html#gae07f435df040041ae6b196ebc57e5038',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr1_5fwrapmod_5fpos_320',['FSMC_BCR1_WRAPMOD_Pos',['../group___peripheral___registers___bits___definition.html#ga81d2d47d639ff73b641182d78e5388cc',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr1_5fwren_321',['FSMC_BCR1_WREN',['../group___peripheral___registers___bits___definition.html#gaa7349a91da7ba38277a068f4e8eea314',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr1_5fwren_5fmsk_322',['FSMC_BCR1_WREN_Msk',['../group___peripheral___registers___bits___definition.html#ga1d6049a6f86dcc5df8daaaa481e6927d',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr1_5fwren_5fpos_323',['FSMC_BCR1_WREN_Pos',['../group___peripheral___registers___bits___definition.html#gaa816e36a3fdd330c2f0ce4e4cceabf43',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr2_5fasyncwait_324',['FSMC_BCR2_ASYNCWAIT',['../group___peripheral___registers___bits___definition.html#gad45d1b552ba61ccbb1dc4ebfc556285a',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr2_5fasyncwait_5fmsk_325',['FSMC_BCR2_ASYNCWAIT_Msk',['../group___peripheral___registers___bits___definition.html#ga5afee4a8591dcaaa4161fbb6ca509c68',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr2_5fasyncwait_5fpos_326',['FSMC_BCR2_ASYNCWAIT_Pos',['../group___peripheral___registers___bits___definition.html#gaca3661a377838f2fcd8d13def99b2bfe',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr2_5fbursten_327',['FSMC_BCR2_BURSTEN',['../group___peripheral___registers___bits___definition.html#ga0d8202b9b40d3912a6294fe2a0e28ebf',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr2_5fbursten_5fmsk_328',['FSMC_BCR2_BURSTEN_Msk',['../group___peripheral___registers___bits___definition.html#ga04ef7898a3300a0e437e98e0f3e266e3',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr2_5fbursten_5fpos_329',['FSMC_BCR2_BURSTEN_Pos',['../group___peripheral___registers___bits___definition.html#ga061b10b005a1fddca182f8df1a520fbd',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr2_5fcburstrw_330',['FSMC_BCR2_CBURSTRW',['../group___peripheral___registers___bits___definition.html#gae64b1874f1ab83a1d0224cb66e504dff',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr2_5fcburstrw_5fmsk_331',['FSMC_BCR2_CBURSTRW_Msk',['../group___peripheral___registers___bits___definition.html#ga354accac428f799c4156a56f43d81c5e',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr2_5fcburstrw_5fpos_332',['FSMC_BCR2_CBURSTRW_Pos',['../group___peripheral___registers___bits___definition.html#gaf4234ff44107642d57fc60bb1b4986d5',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr2_5fcpsize_333',['FSMC_BCR2_CPSIZE',['../group___peripheral___registers___bits___definition.html#ga4546f80f34121d6700fbb8389f69854a',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr2_5fcpsize_5f0_334',['FSMC_BCR2_CPSIZE_0',['../group___peripheral___registers___bits___definition.html#ga4bd12d2e7ea6f99a6fb5c2519d3f7a48',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr2_5fcpsize_5f1_335',['FSMC_BCR2_CPSIZE_1',['../group___peripheral___registers___bits___definition.html#ga2db6a0901e5f500c9c907a8fa2304c4d',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr2_5fcpsize_5f2_336',['FSMC_BCR2_CPSIZE_2',['../group___peripheral___registers___bits___definition.html#ga983f7ba781deff462208b000d0749d42',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr2_5fcpsize_5fmsk_337',['FSMC_BCR2_CPSIZE_Msk',['../group___peripheral___registers___bits___definition.html#ga379d9cd3ddb5ad5c73a6aaecd6a39842',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr2_5fcpsize_5fpos_338',['FSMC_BCR2_CPSIZE_Pos',['../group___peripheral___registers___bits___definition.html#ga29b50188ab8dd06a8dcea1db253c43d3',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr2_5fextmod_339',['FSMC_BCR2_EXTMOD',['../group___peripheral___registers___bits___definition.html#ga76d3e5d899ba2399d3318da577d58ac6',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr2_5fextmod_5fmsk_340',['FSMC_BCR2_EXTMOD_Msk',['../group___peripheral___registers___bits___definition.html#gab0d624c95c3930043d2561545ecfd5a5',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr2_5fextmod_5fpos_341',['FSMC_BCR2_EXTMOD_Pos',['../group___peripheral___registers___bits___definition.html#ga7799a975be4610d90af7d63aff4eb8f6',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr2_5ffaccen_342',['FSMC_BCR2_FACCEN',['../group___peripheral___registers___bits___definition.html#ga7a4e1ad30533ab54b45987cab30d51a0',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr2_5ffaccen_5fmsk_343',['FSMC_BCR2_FACCEN_Msk',['../group___peripheral___registers___bits___definition.html#ga182a7aed98f38419b4d55f4e746ddb78',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr2_5ffaccen_5fpos_344',['FSMC_BCR2_FACCEN_Pos',['../group___peripheral___registers___bits___definition.html#ga5111c287808eaefab515193e2bfe738e',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr2_5fmbken_345',['FSMC_BCR2_MBKEN',['../group___peripheral___registers___bits___definition.html#gad9c99df3c6cebc68f6695ad7bc13f717',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr2_5fmbken_5fmsk_346',['FSMC_BCR2_MBKEN_Msk',['../group___peripheral___registers___bits___definition.html#gaa6ef33bf632e3d9fbe345050be4f322a',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr2_5fmbken_5fpos_347',['FSMC_BCR2_MBKEN_Pos',['../group___peripheral___registers___bits___definition.html#ga8ad7fd4c0644328d6b50f1af802ec2f8',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr2_5fmtyp_348',['FSMC_BCR2_MTYP',['../group___peripheral___registers___bits___definition.html#gabdf82247710aaeff72fb37113bff3daf',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr2_5fmtyp_5f0_349',['FSMC_BCR2_MTYP_0',['../group___peripheral___registers___bits___definition.html#gac595e1e3045aad0b379367f47bf10a84',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr2_5fmtyp_5f1_350',['FSMC_BCR2_MTYP_1',['../group___peripheral___registers___bits___definition.html#ga8b9e5b00171ea739ba67a627a2484f47',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr2_5fmtyp_5fmsk_351',['FSMC_BCR2_MTYP_Msk',['../group___peripheral___registers___bits___definition.html#ga166ddafe3e417b6bb11f233e4e2dedf3',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr2_5fmtyp_5fpos_352',['FSMC_BCR2_MTYP_Pos',['../group___peripheral___registers___bits___definition.html#ga7789cdcc69a54e451f419b3d5266edac',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr2_5fmuxen_353',['FSMC_BCR2_MUXEN',['../group___peripheral___registers___bits___definition.html#ga9f65c4348ab55c12695730bde8be8986',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr2_5fmuxen_5fmsk_354',['FSMC_BCR2_MUXEN_Msk',['../group___peripheral___registers___bits___definition.html#ga4bf9eb6b6bdd6af3179dddcaabca890a',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr2_5fmuxen_5fpos_355',['FSMC_BCR2_MUXEN_Pos',['../group___peripheral___registers___bits___definition.html#ga6ac9fba61cf9cc72921d4f428738826c',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr2_5fmwid_356',['FSMC_BCR2_MWID',['../group___peripheral___registers___bits___definition.html#ga4099746e30f71a98ea71d1048a5d028a',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr2_5fmwid_5f0_357',['FSMC_BCR2_MWID_0',['../group___peripheral___registers___bits___definition.html#ga8501d3ce728f6a074061294a9e5a54cf',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr2_5fmwid_5f1_358',['FSMC_BCR2_MWID_1',['../group___peripheral___registers___bits___definition.html#ga74276c5828d545cf4b2db2d568c60627',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr2_5fmwid_5fmsk_359',['FSMC_BCR2_MWID_Msk',['../group___peripheral___registers___bits___definition.html#ga8a1f1c8878a8d8a6680537bf0c5ae926',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr2_5fmwid_5fpos_360',['FSMC_BCR2_MWID_Pos',['../group___peripheral___registers___bits___definition.html#gae5a899fbf4b3ed1a7fa6ee26cea383b4',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr2_5fwaitcfg_361',['FSMC_BCR2_WAITCFG',['../group___peripheral___registers___bits___definition.html#ga5141640b4dcb78a524740b681819f9f1',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr2_5fwaitcfg_5fmsk_362',['FSMC_BCR2_WAITCFG_Msk',['../group___peripheral___registers___bits___definition.html#ga0200789ac85e6c5e1e481c3df1446e18',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr2_5fwaitcfg_5fpos_363',['FSMC_BCR2_WAITCFG_Pos',['../group___peripheral___registers___bits___definition.html#ga7e9aee1a917ef0b27eb9b5734f853670',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr2_5fwaiten_364',['FSMC_BCR2_WAITEN',['../group___peripheral___registers___bits___definition.html#gad015d2aa1c58b48681f35a4f92eaf7f7',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr2_5fwaiten_5fmsk_365',['FSMC_BCR2_WAITEN_Msk',['../group___peripheral___registers___bits___definition.html#gac8c82d9bdf8bfef070bc96dcfe7e3d8d',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr2_5fwaiten_5fpos_366',['FSMC_BCR2_WAITEN_Pos',['../group___peripheral___registers___bits___definition.html#ga8f4660e60da72244831d66378c76b627',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr2_5fwaitpol_367',['FSMC_BCR2_WAITPOL',['../group___peripheral___registers___bits___definition.html#gaa0f59e7aa2664f9c767ce22bec369698',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr2_5fwaitpol_5fmsk_368',['FSMC_BCR2_WAITPOL_Msk',['../group___peripheral___registers___bits___definition.html#ga363eda93ed7acbb8f0d18a3a291730c7',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr2_5fwaitpol_5fpos_369',['FSMC_BCR2_WAITPOL_Pos',['../group___peripheral___registers___bits___definition.html#gaf39e91bdf996e863420c7e8fc1e5590e',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr2_5fwrapmod_370',['FSMC_BCR2_WRAPMOD',['../group___peripheral___registers___bits___definition.html#ga9e93e4e902a636d4d75a1fd7e884afea',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr2_5fwrapmod_5fmsk_371',['FSMC_BCR2_WRAPMOD_Msk',['../group___peripheral___registers___bits___definition.html#ga3424ec4e7bd6b62133ca3427cc80293c',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr2_5fwrapmod_5fpos_372',['FSMC_BCR2_WRAPMOD_Pos',['../group___peripheral___registers___bits___definition.html#ga789e78a6f20dfc6d81c80f6f1c6c52a6',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr2_5fwren_373',['FSMC_BCR2_WREN',['../group___peripheral___registers___bits___definition.html#gad446f2fcb7909b80a8c1731141be5186',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr2_5fwren_5fmsk_374',['FSMC_BCR2_WREN_Msk',['../group___peripheral___registers___bits___definition.html#ga33a8ad888dead565af3852d70b3ad6b9',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr2_5fwren_5fpos_375',['FSMC_BCR2_WREN_Pos',['../group___peripheral___registers___bits___definition.html#ga1c00df8248fceccd441d5d4b73b86622',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr3_5fasyncwait_376',['FSMC_BCR3_ASYNCWAIT',['../group___peripheral___registers___bits___definition.html#ga9e16fb6b68a8adb7722871ccdd2d9a44',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr3_5fasyncwait_5fmsk_377',['FSMC_BCR3_ASYNCWAIT_Msk',['../group___peripheral___registers___bits___definition.html#ga84c1483478667f1f1121b1b53aaf5bbc',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr3_5fasyncwait_5fpos_378',['FSMC_BCR3_ASYNCWAIT_Pos',['../group___peripheral___registers___bits___definition.html#ga7bf971e9566cc6a9e6638e0bca989f6c',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr3_5fbursten_379',['FSMC_BCR3_BURSTEN',['../group___peripheral___registers___bits___definition.html#gad9badf60f5caa010e041d66d40af596a',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr3_5fbursten_5fmsk_380',['FSMC_BCR3_BURSTEN_Msk',['../group___peripheral___registers___bits___definition.html#ga633d9f36439fa9f12c12c2a46152624b',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr3_5fbursten_5fpos_381',['FSMC_BCR3_BURSTEN_Pos',['../group___peripheral___registers___bits___definition.html#ga334b4a9ae7115924ece63694dcb6ee37',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr3_5fcburstrw_382',['FSMC_BCR3_CBURSTRW',['../group___peripheral___registers___bits___definition.html#ga70c6da37696af84767f82efd0df3a7da',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr3_5fcburstrw_5fmsk_383',['FSMC_BCR3_CBURSTRW_Msk',['../group___peripheral___registers___bits___definition.html#gad14301188370a35a883fbd2c29fbfab7',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr3_5fcburstrw_5fpos_384',['FSMC_BCR3_CBURSTRW_Pos',['../group___peripheral___registers___bits___definition.html#ga07716de72f0cdc426b9c6989d680e05e',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr3_5fcpsize_385',['FSMC_BCR3_CPSIZE',['../group___peripheral___registers___bits___definition.html#ga49e7953ee4991f90a96c3b6a72315731',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr3_5fcpsize_5f0_386',['FSMC_BCR3_CPSIZE_0',['../group___peripheral___registers___bits___definition.html#gadbe607c14de8dfcce9919fecba70f4b4',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr3_5fcpsize_5f1_387',['FSMC_BCR3_CPSIZE_1',['../group___peripheral___registers___bits___definition.html#ga6790c025341fd005cee64fb8a4a231d8',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr3_5fcpsize_5f2_388',['FSMC_BCR3_CPSIZE_2',['../group___peripheral___registers___bits___definition.html#gad77d43cb841e9374c76e93ea443630ad',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr3_5fcpsize_5fmsk_389',['FSMC_BCR3_CPSIZE_Msk',['../group___peripheral___registers___bits___definition.html#ga31e584400d48bf2a9f09b16d93e9aab4',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr3_5fcpsize_5fpos_390',['FSMC_BCR3_CPSIZE_Pos',['../group___peripheral___registers___bits___definition.html#gaecac8e30310435e28ad6456946b63ceb',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr3_5fextmod_391',['FSMC_BCR3_EXTMOD',['../group___peripheral___registers___bits___definition.html#ga6ab23550b17dca7ede57f8b5ef05f2e7',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr3_5fextmod_5fmsk_392',['FSMC_BCR3_EXTMOD_Msk',['../group___peripheral___registers___bits___definition.html#ga5f660417a9ec23815a2d362dea91b1e3',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr3_5fextmod_5fpos_393',['FSMC_BCR3_EXTMOD_Pos',['../group___peripheral___registers___bits___definition.html#gac15a809e2405d3853528319668a81ef7',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr3_5ffaccen_394',['FSMC_BCR3_FACCEN',['../group___peripheral___registers___bits___definition.html#ga380c39b95426ac9a18c70e3f56016c81',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr3_5ffaccen_5fmsk_395',['FSMC_BCR3_FACCEN_Msk',['../group___peripheral___registers___bits___definition.html#ga38db506ff5f00d90249a3a8521df490b',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr3_5ffaccen_5fpos_396',['FSMC_BCR3_FACCEN_Pos',['../group___peripheral___registers___bits___definition.html#ga70b916af09f1553cb63363b748b1f027',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr3_5fmbken_397',['FSMC_BCR3_MBKEN',['../group___peripheral___registers___bits___definition.html#ga0d7810ad338086a1ec9b15f339ed6f4d',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr3_5fmbken_5fmsk_398',['FSMC_BCR3_MBKEN_Msk',['../group___peripheral___registers___bits___definition.html#ga969d8a0800e499c8cfaae30766673baf',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr3_5fmbken_5fpos_399',['FSMC_BCR3_MBKEN_Pos',['../group___peripheral___registers___bits___definition.html#ga5eb6d03fe467aad546d992b73194cb27',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr3_5fmtyp_400',['FSMC_BCR3_MTYP',['../group___peripheral___registers___bits___definition.html#ga319fb6069b651eb947b4d0ba3c9f6196',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr3_5fmtyp_5f0_401',['FSMC_BCR3_MTYP_0',['../group___peripheral___registers___bits___definition.html#gaf33b80510e653dd32de2ae1ec1a1dfb5',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr3_5fmtyp_5f1_402',['FSMC_BCR3_MTYP_1',['../group___peripheral___registers___bits___definition.html#ga2a038553e3a30df4b6e331cad504069b',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr3_5fmtyp_5fmsk_403',['FSMC_BCR3_MTYP_Msk',['../group___peripheral___registers___bits___definition.html#ga988d00e68c4a63b1fc0b575bd9297db2',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr3_5fmtyp_5fpos_404',['FSMC_BCR3_MTYP_Pos',['../group___peripheral___registers___bits___definition.html#gab67e61d2783a793ef984e897897212fa',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr3_5fmuxen_405',['FSMC_BCR3_MUXEN',['../group___peripheral___registers___bits___definition.html#gadaae648c8591e7650cba828910638d3d',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr3_5fmuxen_5fmsk_406',['FSMC_BCR3_MUXEN_Msk',['../group___peripheral___registers___bits___definition.html#gade598d66e7b6ff96d1cc42e78566291b',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr3_5fmuxen_5fpos_407',['FSMC_BCR3_MUXEN_Pos',['../group___peripheral___registers___bits___definition.html#ga257d8fa0925c2a6e4ca3c71724a1c727',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr3_5fmwid_408',['FSMC_BCR3_MWID',['../group___peripheral___registers___bits___definition.html#ga51097cfe8d4263a30d292e7e9dc73cd2',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr3_5fmwid_5f0_409',['FSMC_BCR3_MWID_0',['../group___peripheral___registers___bits___definition.html#ga373b764c1a4104300eb587aa4510c1f1',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr3_5fmwid_5f1_410',['FSMC_BCR3_MWID_1',['../group___peripheral___registers___bits___definition.html#ga43c7292c185269cc11d986f3ae0ceb24',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr3_5fmwid_5fmsk_411',['FSMC_BCR3_MWID_Msk',['../group___peripheral___registers___bits___definition.html#ga6cd430671ae5969640d73b758ffdf612',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr3_5fmwid_5fpos_412',['FSMC_BCR3_MWID_Pos',['../group___peripheral___registers___bits___definition.html#ga17b5f1b6b3101230c49e90176f430673',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr3_5fwaitcfg_413',['FSMC_BCR3_WAITCFG',['../group___peripheral___registers___bits___definition.html#gab845515c37adae28d0e1452596cca7ea',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr3_5fwaitcfg_5fmsk_414',['FSMC_BCR3_WAITCFG_Msk',['../group___peripheral___registers___bits___definition.html#ga86ce7ee19c1952a2cd3a7dd07988d404',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr3_5fwaitcfg_5fpos_415',['FSMC_BCR3_WAITCFG_Pos',['../group___peripheral___registers___bits___definition.html#ga6429581833534bce92d223e08c93eb32',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr3_5fwaiten_416',['FSMC_BCR3_WAITEN',['../group___peripheral___registers___bits___definition.html#ga9665b36b791862c464f07ad49dea315c',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr3_5fwaiten_5fmsk_417',['FSMC_BCR3_WAITEN_Msk',['../group___peripheral___registers___bits___definition.html#ga955ff9500147df62bd5e71fd46ab399c',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr3_5fwaiten_5fpos_418',['FSMC_BCR3_WAITEN_Pos',['../group___peripheral___registers___bits___definition.html#gaabb86a849ca798041db570103d48155c',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr3_5fwaitpol_419',['FSMC_BCR3_WAITPOL',['../group___peripheral___registers___bits___definition.html#gabbca3d0aa315f3e9bc6bacf244bdb747',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr3_5fwaitpol_5fmsk_420',['FSMC_BCR3_WAITPOL_Msk',['../group___peripheral___registers___bits___definition.html#ga76308f3761147bead10be8690363ba75',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr3_5fwaitpol_5fpos_421',['FSMC_BCR3_WAITPOL_Pos',['../group___peripheral___registers___bits___definition.html#gaa8ca3bf2ec7e7869de4f702e2781df26',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr3_5fwrapmod_422',['FSMC_BCR3_WRAPMOD',['../group___peripheral___registers___bits___definition.html#ga44fc6e205695d39b63c0f5b18c3cd214',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr3_5fwrapmod_5fmsk_423',['FSMC_BCR3_WRAPMOD_Msk',['../group___peripheral___registers___bits___definition.html#gae03d16e63e73b02834d26f33cc91dc64',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr3_5fwrapmod_5fpos_424',['FSMC_BCR3_WRAPMOD_Pos',['../group___peripheral___registers___bits___definition.html#gad89219171643f908db3cfa28eee4d5e9',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr3_5fwren_425',['FSMC_BCR3_WREN',['../group___peripheral___registers___bits___definition.html#ga22c9b0145aa62cafd915a4c7da1931b5',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr3_5fwren_5fmsk_426',['FSMC_BCR3_WREN_Msk',['../group___peripheral___registers___bits___definition.html#gafe425cfa93902161f696ee0d9b26e9c5',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr3_5fwren_5fpos_427',['FSMC_BCR3_WREN_Pos',['../group___peripheral___registers___bits___definition.html#ga704d37df498bac515b6ec4c5e4f94462',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr4_5fasyncwait_428',['FSMC_BCR4_ASYNCWAIT',['../group___peripheral___registers___bits___definition.html#ga158eeaca2258bc25beae918d01e01dd8',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr4_5fasyncwait_5fmsk_429',['FSMC_BCR4_ASYNCWAIT_Msk',['../group___peripheral___registers___bits___definition.html#ga486c5a22b57dba36a2010257c92514ca',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr4_5fasyncwait_5fpos_430',['FSMC_BCR4_ASYNCWAIT_Pos',['../group___peripheral___registers___bits___definition.html#gafdb1dd068a4d2b956aef4fb973342e53',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr4_5fbursten_431',['FSMC_BCR4_BURSTEN',['../group___peripheral___registers___bits___definition.html#ga2c6ffdcee5dc3de1402bd8b644d6ecf4',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr4_5fbursten_5fmsk_432',['FSMC_BCR4_BURSTEN_Msk',['../group___peripheral___registers___bits___definition.html#ga0adae69dfd0ea81a4e50501b4e71dcf1',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr4_5fbursten_5fpos_433',['FSMC_BCR4_BURSTEN_Pos',['../group___peripheral___registers___bits___definition.html#ga61065b18069c91ca4a92acba5d8e2815',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr4_5fcburstrw_434',['FSMC_BCR4_CBURSTRW',['../group___peripheral___registers___bits___definition.html#ga19293300b8230e38afa1c16c526b3f29',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr4_5fcburstrw_5fmsk_435',['FSMC_BCR4_CBURSTRW_Msk',['../group___peripheral___registers___bits___definition.html#ga0e8b3d5023ae64207d965b9d26816b72',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr4_5fcburstrw_5fpos_436',['FSMC_BCR4_CBURSTRW_Pos',['../group___peripheral___registers___bits___definition.html#gad81ccd2059e86d3108e3c71e5075f936',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr4_5fcpsize_437',['FSMC_BCR4_CPSIZE',['../group___peripheral___registers___bits___definition.html#gad40c68c7a7806c531d78af3ba712f0cd',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr4_5fcpsize_5f0_438',['FSMC_BCR4_CPSIZE_0',['../group___peripheral___registers___bits___definition.html#ga801fee8ca2fcd5c881f95fa7eb319160',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr4_5fcpsize_5f1_439',['FSMC_BCR4_CPSIZE_1',['../group___peripheral___registers___bits___definition.html#ga7615f0150d36affdecdb05bdff084020',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr4_5fcpsize_5f2_440',['FSMC_BCR4_CPSIZE_2',['../group___peripheral___registers___bits___definition.html#ga59bdb0695f948fa7369451fc38380c12',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr4_5fcpsize_5fmsk_441',['FSMC_BCR4_CPSIZE_Msk',['../group___peripheral___registers___bits___definition.html#ga3a79495e98a82e6895d4b51c66b9af59',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr4_5fcpsize_5fpos_442',['FSMC_BCR4_CPSIZE_Pos',['../group___peripheral___registers___bits___definition.html#ga6efaac5bbbd151e85dbb22176550eb75',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr4_5fextmod_443',['FSMC_BCR4_EXTMOD',['../group___peripheral___registers___bits___definition.html#ga6794966a05855913923294f5c2ab69ed',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr4_5fextmod_5fmsk_444',['FSMC_BCR4_EXTMOD_Msk',['../group___peripheral___registers___bits___definition.html#gaf8d523e6b38ea3647b831b65a596faca',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr4_5fextmod_5fpos_445',['FSMC_BCR4_EXTMOD_Pos',['../group___peripheral___registers___bits___definition.html#ga63db0c5c207a432ae87a5881b163f000',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr4_5ffaccen_446',['FSMC_BCR4_FACCEN',['../group___peripheral___registers___bits___definition.html#gabf769d7958a8c610ccca912600e61f30',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr4_5ffaccen_5fmsk_447',['FSMC_BCR4_FACCEN_Msk',['../group___peripheral___registers___bits___definition.html#ga887e51078b00ac24b3ac8a5ff1d2290c',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr4_5ffaccen_5fpos_448',['FSMC_BCR4_FACCEN_Pos',['../group___peripheral___registers___bits___definition.html#ga576f29ec9b1d7afa35bcecd8b974d8af',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr4_5fmbken_449',['FSMC_BCR4_MBKEN',['../group___peripheral___registers___bits___definition.html#ga9a1ea2c2967cda7ef1597c4fb1a9dd9a',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr4_5fmbken_5fmsk_450',['FSMC_BCR4_MBKEN_Msk',['../group___peripheral___registers___bits___definition.html#ga8b3f9e5b69de79c42b203113832b8767',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr4_5fmbken_5fpos_451',['FSMC_BCR4_MBKEN_Pos',['../group___peripheral___registers___bits___definition.html#gae79298022ec557019f4b238bc0a1c93e',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr4_5fmtyp_452',['FSMC_BCR4_MTYP',['../group___peripheral___registers___bits___definition.html#ga1f9bf2c236b772e76174aff4388a1b6f',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr4_5fmtyp_5f0_453',['FSMC_BCR4_MTYP_0',['../group___peripheral___registers___bits___definition.html#ga66d358ec27a34fe13131d852b950643e',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr4_5fmtyp_5f1_454',['FSMC_BCR4_MTYP_1',['../group___peripheral___registers___bits___definition.html#gaac5abffefdc124215182346aba701183',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr4_5fmtyp_5fmsk_455',['FSMC_BCR4_MTYP_Msk',['../group___peripheral___registers___bits___definition.html#ga4f4900e19f018d5deee5bbbd8605ccc9',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr4_5fmtyp_5fpos_456',['FSMC_BCR4_MTYP_Pos',['../group___peripheral___registers___bits___definition.html#ga96c0fdb70786e0c784a5a4c002ca41db',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr4_5fmuxen_457',['FSMC_BCR4_MUXEN',['../group___peripheral___registers___bits___definition.html#ga92d644d34b59762d0b48f7784d3aed4b',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr4_5fmuxen_5fmsk_458',['FSMC_BCR4_MUXEN_Msk',['../group___peripheral___registers___bits___definition.html#ga1556380a7357a40ef14a0e064adb39ef',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr4_5fmuxen_5fpos_459',['FSMC_BCR4_MUXEN_Pos',['../group___peripheral___registers___bits___definition.html#ga241a30edf0f4403c5154c249277443a8',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr4_5fmwid_460',['FSMC_BCR4_MWID',['../group___peripheral___registers___bits___definition.html#ga5c4ce32ca454c42344cfe73f71abd274',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr4_5fmwid_5f0_461',['FSMC_BCR4_MWID_0',['../group___peripheral___registers___bits___definition.html#ga1c8f397cfb1f07421abeaf3060f7a329',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr4_5fmwid_5f1_462',['FSMC_BCR4_MWID_1',['../group___peripheral___registers___bits___definition.html#gaf5cd3a31190eb0cea8a72b55d8369970',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr4_5fmwid_5fmsk_463',['FSMC_BCR4_MWID_Msk',['../group___peripheral___registers___bits___definition.html#gaad01b905b7a139494a1577694bb6401f',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr4_5fmwid_5fpos_464',['FSMC_BCR4_MWID_Pos',['../group___peripheral___registers___bits___definition.html#gab06a48e2793af3cce3d0a32ee5622339',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr4_5fwaitcfg_465',['FSMC_BCR4_WAITCFG',['../group___peripheral___registers___bits___definition.html#ga11c35ab0ee9ee23a5352218b4b84a258',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr4_5fwaitcfg_5fmsk_466',['FSMC_BCR4_WAITCFG_Msk',['../group___peripheral___registers___bits___definition.html#ga6fe8c8ee1b76354cdd74bb024e2b036d',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr4_5fwaitcfg_5fpos_467',['FSMC_BCR4_WAITCFG_Pos',['../group___peripheral___registers___bits___definition.html#ga23b0e2f296dd78ec57b8f166cc59bf6b',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr4_5fwaiten_468',['FSMC_BCR4_WAITEN',['../group___peripheral___registers___bits___definition.html#ga458727d27c2bc7cede05f6537bfc1bd8',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr4_5fwaiten_5fmsk_469',['FSMC_BCR4_WAITEN_Msk',['../group___peripheral___registers___bits___definition.html#ga55ba3588b86b81122eb8da69f0593741',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr4_5fwaiten_5fpos_470',['FSMC_BCR4_WAITEN_Pos',['../group___peripheral___registers___bits___definition.html#gab597ed53b04db4a4f13b57a727b5624c',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr4_5fwaitpol_471',['FSMC_BCR4_WAITPOL',['../group___peripheral___registers___bits___definition.html#ga485976f8857949064d060374031cad3d',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr4_5fwaitpol_5fmsk_472',['FSMC_BCR4_WAITPOL_Msk',['../group___peripheral___registers___bits___definition.html#gaf12e7172887f85904c50033b9d8b78fd',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr4_5fwaitpol_5fpos_473',['FSMC_BCR4_WAITPOL_Pos',['../group___peripheral___registers___bits___definition.html#ga0716fa00c0b7d9e694f1e4faa3b463af',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr4_5fwrapmod_474',['FSMC_BCR4_WRAPMOD',['../group___peripheral___registers___bits___definition.html#gaa35333cfffc35c7948ee0aa0e5672c3c',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr4_5fwrapmod_5fmsk_475',['FSMC_BCR4_WRAPMOD_Msk',['../group___peripheral___registers___bits___definition.html#gad6f39d62a63c9708594f0d9819d3ad2a',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr4_5fwrapmod_5fpos_476',['FSMC_BCR4_WRAPMOD_Pos',['../group___peripheral___registers___bits___definition.html#ga6a74bbc78956ddc94627b5b987b05169',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr4_5fwren_477',['FSMC_BCR4_WREN',['../group___peripheral___registers___bits___definition.html#gadf2eef4eb8e6bb99cace5145b6ad09ee',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr4_5fwren_5fmsk_478',['FSMC_BCR4_WREN_Msk',['../group___peripheral___registers___bits___definition.html#gad3879a08367749ad58d7f17708998f28',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbcr4_5fwren_5fpos_479',['FSMC_BCR4_WREN_Pos',['../group___peripheral___registers___bits___definition.html#gaee04969322aa460220249296cbecbc07',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr1_5faccmod_480',['FSMC_BTR1_ACCMOD',['../group___peripheral___registers___bits___definition.html#ga027548b6b5971a2c56558932c956fa4c',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr1_5faccmod_5f0_481',['FSMC_BTR1_ACCMOD_0',['../group___peripheral___registers___bits___definition.html#gaf77aa4936dc4f35d1b426d147c643c80',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr1_5faccmod_5f1_482',['FSMC_BTR1_ACCMOD_1',['../group___peripheral___registers___bits___definition.html#ga7b336cf3ae23cfda19895927b63af558',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr1_5faccmod_5fmsk_483',['FSMC_BTR1_ACCMOD_Msk',['../group___peripheral___registers___bits___definition.html#ga97f35ab9565eeb82324ab5015237cdbd',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr1_5faccmod_5fpos_484',['FSMC_BTR1_ACCMOD_Pos',['../group___peripheral___registers___bits___definition.html#gabfe73fd49dee3d6123e7be78f49e8dce',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr1_5faddhld_485',['FSMC_BTR1_ADDHLD',['../group___peripheral___registers___bits___definition.html#gadc4a3860c48a62ff0290622e1937072d',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr1_5faddhld_5f0_486',['FSMC_BTR1_ADDHLD_0',['../group___peripheral___registers___bits___definition.html#ga222a16d5a1a8deebaf39a96d94d3c3f0',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr1_5faddhld_5f1_487',['FSMC_BTR1_ADDHLD_1',['../group___peripheral___registers___bits___definition.html#ga5ad1f9164644c4ff4c6ae5a655478abc',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr1_5faddhld_5f2_488',['FSMC_BTR1_ADDHLD_2',['../group___peripheral___registers___bits___definition.html#ga3f9d68df0fd84b77342a565e9faad929',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr1_5faddhld_5f3_489',['FSMC_BTR1_ADDHLD_3',['../group___peripheral___registers___bits___definition.html#ga6e88e45163e76f529b5a94937526f45c',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr1_5faddhld_5fmsk_490',['FSMC_BTR1_ADDHLD_Msk',['../group___peripheral___registers___bits___definition.html#ga1d1abafea7ca6c3eecc720b4e9e15b3e',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr1_5faddhld_5fpos_491',['FSMC_BTR1_ADDHLD_Pos',['../group___peripheral___registers___bits___definition.html#gab8d311b7f571c7f1b55638b62da5a5a1',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr1_5faddset_492',['FSMC_BTR1_ADDSET',['../group___peripheral___registers___bits___definition.html#gab457e5d3a33d80db3ad070b1cf57669a',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr1_5faddset_5f0_493',['FSMC_BTR1_ADDSET_0',['../group___peripheral___registers___bits___definition.html#gae29ca17c63df62cc12c06e6cfa3429e3',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr1_5faddset_5f1_494',['FSMC_BTR1_ADDSET_1',['../group___peripheral___registers___bits___definition.html#gaefb98ce348ba665f122e44ddc0390b45',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr1_5faddset_5f2_495',['FSMC_BTR1_ADDSET_2',['../group___peripheral___registers___bits___definition.html#gaa5e5c5b00c91aca1cc266622d3f30bf0',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr1_5faddset_5f3_496',['FSMC_BTR1_ADDSET_3',['../group___peripheral___registers___bits___definition.html#ga2f0105afe671cd62730cf879072c80f3',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr1_5faddset_5fmsk_497',['FSMC_BTR1_ADDSET_Msk',['../group___peripheral___registers___bits___definition.html#ga2b91cf869f5ab06c40ad7620ae59ffa8',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr1_5faddset_5fpos_498',['FSMC_BTR1_ADDSET_Pos',['../group___peripheral___registers___bits___definition.html#gad2b6109a964212ec400829faa37e113a',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr1_5fbusturn_499',['FSMC_BTR1_BUSTURN',['../group___peripheral___registers___bits___definition.html#ga7ec9346bbaf845f1dffe33c4a625c0ac',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr1_5fbusturn_5f0_500',['FSMC_BTR1_BUSTURN_0',['../group___peripheral___registers___bits___definition.html#ga6c1578a85c4f2cef9e034c7b5da6d454',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr1_5fbusturn_5f1_501',['FSMC_BTR1_BUSTURN_1',['../group___peripheral___registers___bits___definition.html#gaf873cbfe4827496215eb08bb33ae4784',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr1_5fbusturn_5f2_502',['FSMC_BTR1_BUSTURN_2',['../group___peripheral___registers___bits___definition.html#gad768d3ff0a5159e552663c9489b977f6',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr1_5fbusturn_5f3_503',['FSMC_BTR1_BUSTURN_3',['../group___peripheral___registers___bits___definition.html#gaf3ecfd25fb64efb3745ee96b2877a017',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr1_5fbusturn_5fmsk_504',['FSMC_BTR1_BUSTURN_Msk',['../group___peripheral___registers___bits___definition.html#gaedd0e3c6b2b476a6e6c0578a2bdf3d5d',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr1_5fbusturn_5fpos_505',['FSMC_BTR1_BUSTURN_Pos',['../group___peripheral___registers___bits___definition.html#ga164a173346248449423d03e8d1d40a31',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr1_5fclkdiv_506',['FSMC_BTR1_CLKDIV',['../group___peripheral___registers___bits___definition.html#gac7c4dbd43df84559e30a9c332b265ad5',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr1_5fclkdiv_5f0_507',['FSMC_BTR1_CLKDIV_0',['../group___peripheral___registers___bits___definition.html#gabe9c9e09de00afad666ace28c608032f',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr1_5fclkdiv_5f1_508',['FSMC_BTR1_CLKDIV_1',['../group___peripheral___registers___bits___definition.html#gafffebd7a0cf6e6d80b65804c2c50ce62',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr1_5fclkdiv_5f2_509',['FSMC_BTR1_CLKDIV_2',['../group___peripheral___registers___bits___definition.html#ga43afa754305cc1a7ff3075cdd4309990',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr1_5fclkdiv_5f3_510',['FSMC_BTR1_CLKDIV_3',['../group___peripheral___registers___bits___definition.html#ga68a146aec5d723a84945ae6da6c0692f',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr1_5fclkdiv_5fmsk_511',['FSMC_BTR1_CLKDIV_Msk',['../group___peripheral___registers___bits___definition.html#ga7c720b329720574b2c8d30c072f78716',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr1_5fclkdiv_5fpos_512',['FSMC_BTR1_CLKDIV_Pos',['../group___peripheral___registers___bits___definition.html#ga514bdebcbaf4a3e4d0ede4fef6bb0dd7',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr1_5fdatast_513',['FSMC_BTR1_DATAST',['../group___peripheral___registers___bits___definition.html#gae39175370a991b500962fd084230e389',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr1_5fdatast_5f0_514',['FSMC_BTR1_DATAST_0',['../group___peripheral___registers___bits___definition.html#ga4488a428f33d96263a00a30af42b849b',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr1_5fdatast_5f1_515',['FSMC_BTR1_DATAST_1',['../group___peripheral___registers___bits___definition.html#gad53bd6a1decfafdb420a37453b3b5545',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr1_5fdatast_5f2_516',['FSMC_BTR1_DATAST_2',['../group___peripheral___registers___bits___definition.html#gacce8f6cf5a9ba24943b3e762bde00aee',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr1_5fdatast_5f3_517',['FSMC_BTR1_DATAST_3',['../group___peripheral___registers___bits___definition.html#ga99638cc2cbe0dead029c201e5f30c3a8',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr1_5fdatast_5f4_518',['FSMC_BTR1_DATAST_4',['../group___peripheral___registers___bits___definition.html#ga46c64dd27460218f4398f84f8a1eb050',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr1_5fdatast_5f5_519',['FSMC_BTR1_DATAST_5',['../group___peripheral___registers___bits___definition.html#ga1d19491b3e729c6aac0fea41cc62b695',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr1_5fdatast_5f6_520',['FSMC_BTR1_DATAST_6',['../group___peripheral___registers___bits___definition.html#ga50c28cb325d28369d1a9ef764c63887b',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr1_5fdatast_5f7_521',['FSMC_BTR1_DATAST_7',['../group___peripheral___registers___bits___definition.html#ga7f54453aa732f52cbb5a1562d2eddd23',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr1_5fdatast_5fmsk_522',['FSMC_BTR1_DATAST_Msk',['../group___peripheral___registers___bits___definition.html#gae0a503b09190898423d53534300bf397',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr1_5fdatast_5fpos_523',['FSMC_BTR1_DATAST_Pos',['../group___peripheral___registers___bits___definition.html#ga5c6cf527aad7fcdb2e57ef4483cd4e91',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr1_5fdatlat_524',['FSMC_BTR1_DATLAT',['../group___peripheral___registers___bits___definition.html#ga4ef6dcccdb11a1b094966be0c019124b',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr1_5fdatlat_5f0_525',['FSMC_BTR1_DATLAT_0',['../group___peripheral___registers___bits___definition.html#gae2d832593697ba108d99a97e4fdfd159',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr1_5fdatlat_5f1_526',['FSMC_BTR1_DATLAT_1',['../group___peripheral___registers___bits___definition.html#ga2a7e4efc546c1c9d16c750a4542e1c55',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr1_5fdatlat_5f2_527',['FSMC_BTR1_DATLAT_2',['../group___peripheral___registers___bits___definition.html#ga22e7d41e0f94ab896c6eea199eb0aef1',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr1_5fdatlat_5f3_528',['FSMC_BTR1_DATLAT_3',['../group___peripheral___registers___bits___definition.html#ga8b42f22fc488e0ed0d06832118773123',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr1_5fdatlat_5fmsk_529',['FSMC_BTR1_DATLAT_Msk',['../group___peripheral___registers___bits___definition.html#ga19c7f2d933e94d7f60c22027558f2a23',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr1_5fdatlat_5fpos_530',['FSMC_BTR1_DATLAT_Pos',['../group___peripheral___registers___bits___definition.html#ga1bc0aee3036c6ddba4a1e66b92b0913c',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr2_5faccmod_531',['FSMC_BTR2_ACCMOD',['../group___peripheral___registers___bits___definition.html#ga07b93600977cde6e31a9464f87606043',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr2_5faccmod_5f0_532',['FSMC_BTR2_ACCMOD_0',['../group___peripheral___registers___bits___definition.html#ga9383d89d5e557a166f6b8290892b89b3',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr2_5faccmod_5f1_533',['FSMC_BTR2_ACCMOD_1',['../group___peripheral___registers___bits___definition.html#gad200e1dc2d1835e3dc0fa8f0483eb2c0',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr2_5faccmod_5fmsk_534',['FSMC_BTR2_ACCMOD_Msk',['../group___peripheral___registers___bits___definition.html#gad11258e9138b98bf6387167f0a2645f9',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr2_5faccmod_5fpos_535',['FSMC_BTR2_ACCMOD_Pos',['../group___peripheral___registers___bits___definition.html#gad9cba11e01cd8e90b1e56a3d52c44025',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr2_5faddhld_536',['FSMC_BTR2_ADDHLD',['../group___peripheral___registers___bits___definition.html#gac37c974d0260ba1dbd1acaf6fceb425c',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr2_5faddhld_5f0_537',['FSMC_BTR2_ADDHLD_0',['../group___peripheral___registers___bits___definition.html#gabbf56fc3a549d1e68d56e1587123bd27',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr2_5faddhld_5f1_538',['FSMC_BTR2_ADDHLD_1',['../group___peripheral___registers___bits___definition.html#ga0b7d19f02444ce8b3286d44258c6caef',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr2_5faddhld_5f2_539',['FSMC_BTR2_ADDHLD_2',['../group___peripheral___registers___bits___definition.html#ga7e9433e15e301d5d3f0dd6b73c9db2f7',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr2_5faddhld_5f3_540',['FSMC_BTR2_ADDHLD_3',['../group___peripheral___registers___bits___definition.html#gacc538e46145ed4947194f3ad63e211b7',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr2_5faddhld_5fmsk_541',['FSMC_BTR2_ADDHLD_Msk',['../group___peripheral___registers___bits___definition.html#gabe23e10bb28cb59dced9d9db5a4106db',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr2_5faddhld_5fpos_542',['FSMC_BTR2_ADDHLD_Pos',['../group___peripheral___registers___bits___definition.html#ga2be5c64e803c9fe4378275e2acd1b095',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr2_5faddset_543',['FSMC_BTR2_ADDSET',['../group___peripheral___registers___bits___definition.html#ga23697810b99730ddf52834a5066c1ba5',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr2_5faddset_5f0_544',['FSMC_BTR2_ADDSET_0',['../group___peripheral___registers___bits___definition.html#ga827398dc098f2d08bb77a04b2e7d6ba3',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr2_5faddset_5f1_545',['FSMC_BTR2_ADDSET_1',['../group___peripheral___registers___bits___definition.html#ga1b40f47f2db0db78de6fe2df58b5d591',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr2_5faddset_5f2_546',['FSMC_BTR2_ADDSET_2',['../group___peripheral___registers___bits___definition.html#ga558185a28aeedbb098890348a041a74d',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr2_5faddset_5f3_547',['FSMC_BTR2_ADDSET_3',['../group___peripheral___registers___bits___definition.html#gadbd4d42459a990825b61962d9118cd7b',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr2_5faddset_5fmsk_548',['FSMC_BTR2_ADDSET_Msk',['../group___peripheral___registers___bits___definition.html#ga903bf76eee82e88b1cefc9d1ed1aa4c7',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr2_5faddset_5fpos_549',['FSMC_BTR2_ADDSET_Pos',['../group___peripheral___registers___bits___definition.html#ga58b9a54aabd6cc507c6ab1b5fb134727',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr2_5fbusturn_550',['FSMC_BTR2_BUSTURN',['../group___peripheral___registers___bits___definition.html#ga5ae7c94522af51d2f96a0fa715dfa9b0',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr2_5fbusturn_5f0_551',['FSMC_BTR2_BUSTURN_0',['../group___peripheral___registers___bits___definition.html#ga2617a99e5eab8b31ff168557f93852a3',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr2_5fbusturn_5f1_552',['FSMC_BTR2_BUSTURN_1',['../group___peripheral___registers___bits___definition.html#ga83871fa5cde9d72ec840d29d43aa2e57',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr2_5fbusturn_5f2_553',['FSMC_BTR2_BUSTURN_2',['../group___peripheral___registers___bits___definition.html#gacada2902f8612df1e5ac6e224bcf8d3c',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr2_5fbusturn_5f3_554',['FSMC_BTR2_BUSTURN_3',['../group___peripheral___registers___bits___definition.html#ga66ad543195f36fdb3efdf7550381f982',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr2_5fbusturn_5fmsk_555',['FSMC_BTR2_BUSTURN_Msk',['../group___peripheral___registers___bits___definition.html#ga92af3fcfa317680d6fc598faa951d8e9',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr2_5fbusturn_5fpos_556',['FSMC_BTR2_BUSTURN_Pos',['../group___peripheral___registers___bits___definition.html#gae4f38b835e2730a7d9e817474b4a304c',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr2_5fclkdiv_557',['FSMC_BTR2_CLKDIV',['../group___peripheral___registers___bits___definition.html#ga37fdb25c494cf314cb680f84c5e0a503',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr2_5fclkdiv_5f0_558',['FSMC_BTR2_CLKDIV_0',['../group___peripheral___registers___bits___definition.html#ga1ac8729c8ac330f6ade93a6a15a4ba70',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr2_5fclkdiv_5f1_559',['FSMC_BTR2_CLKDIV_1',['../group___peripheral___registers___bits___definition.html#ga31920e8bf2d83ad3c2849f8e942bb6e4',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr2_5fclkdiv_5f2_560',['FSMC_BTR2_CLKDIV_2',['../group___peripheral___registers___bits___definition.html#gaf5ba3172687049c687e3a38ec08d6c5a',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr2_5fclkdiv_5f3_561',['FSMC_BTR2_CLKDIV_3',['../group___peripheral___registers___bits___definition.html#ga453c2a90dc3340596c9d34672cede6a0',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr2_5fclkdiv_5fmsk_562',['FSMC_BTR2_CLKDIV_Msk',['../group___peripheral___registers___bits___definition.html#gafe9c74d5bceaaa34ce11040cff130c7c',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr2_5fclkdiv_5fpos_563',['FSMC_BTR2_CLKDIV_Pos',['../group___peripheral___registers___bits___definition.html#ga3f1719a782602f2ad5737abd57bc866a',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr2_5fdatast_564',['FSMC_BTR2_DATAST',['../group___peripheral___registers___bits___definition.html#gabe1d3fe096ea53ea073b78bd6ddbff58',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr2_5fdatast_5f0_565',['FSMC_BTR2_DATAST_0',['../group___peripheral___registers___bits___definition.html#gaa066dab45a22ebd3a7102b92dcd251bd',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr2_5fdatast_5f1_566',['FSMC_BTR2_DATAST_1',['../group___peripheral___registers___bits___definition.html#ga68c15ca5fdd13efb5499f0e86bd5bc88',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr2_5fdatast_5f2_567',['FSMC_BTR2_DATAST_2',['../group___peripheral___registers___bits___definition.html#ga36cfe553d431ca6976f0d36c73045836',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr2_5fdatast_5f3_568',['FSMC_BTR2_DATAST_3',['../group___peripheral___registers___bits___definition.html#ga874499b29d2b72a75265f16a2d8ed834',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr2_5fdatast_5f4_569',['FSMC_BTR2_DATAST_4',['../group___peripheral___registers___bits___definition.html#ga4856fb97d7d04d612f24d7267e6c9b76',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr2_5fdatast_5f5_570',['FSMC_BTR2_DATAST_5',['../group___peripheral___registers___bits___definition.html#gacb50ada649984a8bde5535cc3163344c',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr2_5fdatast_5f6_571',['FSMC_BTR2_DATAST_6',['../group___peripheral___registers___bits___definition.html#gaac4784549001168b5ab21a93852100d0',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr2_5fdatast_5f7_572',['FSMC_BTR2_DATAST_7',['../group___peripheral___registers___bits___definition.html#ga4bdd6994cb33a10447cbce5c563746da',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr2_5fdatast_5fmsk_573',['FSMC_BTR2_DATAST_Msk',['../group___peripheral___registers___bits___definition.html#ga35f2c0de6b8e42c44f1006a29507ce07',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr2_5fdatast_5fpos_574',['FSMC_BTR2_DATAST_Pos',['../group___peripheral___registers___bits___definition.html#ga2b6e90fc9b165365c147924675deb339',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr2_5fdatlat_575',['FSMC_BTR2_DATLAT',['../group___peripheral___registers___bits___definition.html#gae3247db1653b31df0c34ab7898400bb5',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr2_5fdatlat_5f0_576',['FSMC_BTR2_DATLAT_0',['../group___peripheral___registers___bits___definition.html#ga0510047c932d2833f6cbe0a4a5d7b9b5',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr2_5fdatlat_5f1_577',['FSMC_BTR2_DATLAT_1',['../group___peripheral___registers___bits___definition.html#ga4e1852b706b3c719c0eab8ef863b39e0',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr2_5fdatlat_5f2_578',['FSMC_BTR2_DATLAT_2',['../group___peripheral___registers___bits___definition.html#ga7ace24f50d1c51c978af55d47c13c0e9',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr2_5fdatlat_5f3_579',['FSMC_BTR2_DATLAT_3',['../group___peripheral___registers___bits___definition.html#ga99389b63c4dee3c54aa1de36a4119add',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr2_5fdatlat_5fmsk_580',['FSMC_BTR2_DATLAT_Msk',['../group___peripheral___registers___bits___definition.html#ga3518166716c8654e8c0ad881bf0d2c66',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr2_5fdatlat_5fpos_581',['FSMC_BTR2_DATLAT_Pos',['../group___peripheral___registers___bits___definition.html#ga3766782905697c6b350ed00bc873baa9',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr3_5faccmod_582',['FSMC_BTR3_ACCMOD',['../group___peripheral___registers___bits___definition.html#ga56c8f213e437ceed2140f2c16a0416cd',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr3_5faccmod_5f0_583',['FSMC_BTR3_ACCMOD_0',['../group___peripheral___registers___bits___definition.html#ga4d50e71940995d42c5f9fadcb7cd61f2',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr3_5faccmod_5f1_584',['FSMC_BTR3_ACCMOD_1',['../group___peripheral___registers___bits___definition.html#gac8bbfd5e08b73d1c5de53ee0ff0ddb9a',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr3_5faccmod_5fmsk_585',['FSMC_BTR3_ACCMOD_Msk',['../group___peripheral___registers___bits___definition.html#ga02766e5c7ca9549655ea80d68267062e',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr3_5faccmod_5fpos_586',['FSMC_BTR3_ACCMOD_Pos',['../group___peripheral___registers___bits___definition.html#ga61e6d33a30b831902487e19a9d79bed0',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr3_5faddhld_587',['FSMC_BTR3_ADDHLD',['../group___peripheral___registers___bits___definition.html#ga7833ee760b2400e6fb483b1d83cbdff3',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr3_5faddhld_5f0_588',['FSMC_BTR3_ADDHLD_0',['../group___peripheral___registers___bits___definition.html#gad417ccae1c4018d0ff5c76c942aeb2ca',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr3_5faddhld_5f1_589',['FSMC_BTR3_ADDHLD_1',['../group___peripheral___registers___bits___definition.html#ga60d0ae6af13ef088367cef06c7f207d3',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr3_5faddhld_5f2_590',['FSMC_BTR3_ADDHLD_2',['../group___peripheral___registers___bits___definition.html#gac029aaed48e2a3e2eedf767fe0ce0b92',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr3_5faddhld_5f3_591',['FSMC_BTR3_ADDHLD_3',['../group___peripheral___registers___bits___definition.html#ga5b6aab5907bc42e140ca5a4d60fcd64c',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr3_5faddhld_5fmsk_592',['FSMC_BTR3_ADDHLD_Msk',['../group___peripheral___registers___bits___definition.html#ga2bf5884c4cc7c453908e3ac5272244b7',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr3_5faddhld_5fpos_593',['FSMC_BTR3_ADDHLD_Pos',['../group___peripheral___registers___bits___definition.html#gac4fb45db8d202b537ad7ca41ed70f459',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr3_5faddset_594',['FSMC_BTR3_ADDSET',['../group___peripheral___registers___bits___definition.html#gaf3e55daf436a25fadae7384611aa0f89',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr3_5faddset_5f0_595',['FSMC_BTR3_ADDSET_0',['../group___peripheral___registers___bits___definition.html#gab6a21211dd7a3445e944af0fe1a4b600',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr3_5faddset_5f1_596',['FSMC_BTR3_ADDSET_1',['../group___peripheral___registers___bits___definition.html#ga51c23d36fa8e7e38048d94830bf0f74f',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr3_5faddset_5f2_597',['FSMC_BTR3_ADDSET_2',['../group___peripheral___registers___bits___definition.html#ga93be4171cb7d0b66d8d4d12e61b07b88',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr3_5faddset_5f3_598',['FSMC_BTR3_ADDSET_3',['../group___peripheral___registers___bits___definition.html#gab01cf0b1c88857669d10fee8d7ba4d85',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr3_5faddset_5fmsk_599',['FSMC_BTR3_ADDSET_Msk',['../group___peripheral___registers___bits___definition.html#ga6a2fd577c6b176ec1d1ed35f4230ea74',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr3_5faddset_5fpos_600',['FSMC_BTR3_ADDSET_Pos',['../group___peripheral___registers___bits___definition.html#ga3f6c91220bbb34e5cb90903df17cfd63',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr3_5fbusturn_601',['FSMC_BTR3_BUSTURN',['../group___peripheral___registers___bits___definition.html#gae8a3ad9f940c6942682d8d97b1eb0ca4',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr3_5fbusturn_5f0_602',['FSMC_BTR3_BUSTURN_0',['../group___peripheral___registers___bits___definition.html#ga739f2db66e52626aa9a5ee02c11d7a34',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr3_5fbusturn_5f1_603',['FSMC_BTR3_BUSTURN_1',['../group___peripheral___registers___bits___definition.html#ga7e4c4102ea6e6cf2082e78168edfc18e',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr3_5fbusturn_5f2_604',['FSMC_BTR3_BUSTURN_2',['../group___peripheral___registers___bits___definition.html#gad5eab2601ae3cd040bf44feb3e70c459',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr3_5fbusturn_5f3_605',['FSMC_BTR3_BUSTURN_3',['../group___peripheral___registers___bits___definition.html#gacf61e23804e0fa3ca45f851ca98de371',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr3_5fbusturn_5fmsk_606',['FSMC_BTR3_BUSTURN_Msk',['../group___peripheral___registers___bits___definition.html#ga3a87c9110d709faefbf2d08ee49ca874',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr3_5fbusturn_5fpos_607',['FSMC_BTR3_BUSTURN_Pos',['../group___peripheral___registers___bits___definition.html#ga2b7b831c25c61676309f80788ec1a9e9',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr3_5fclkdiv_608',['FSMC_BTR3_CLKDIV',['../group___peripheral___registers___bits___definition.html#ga47a8d8e279c50995143ecf4124580703',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr3_5fclkdiv_5f0_609',['FSMC_BTR3_CLKDIV_0',['../group___peripheral___registers___bits___definition.html#gadd9c93b0ee64856981394a63d6a3a964',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr3_5fclkdiv_5f1_610',['FSMC_BTR3_CLKDIV_1',['../group___peripheral___registers___bits___definition.html#ga98fa7611b4ae197ab25cdf1cae9f8ee1',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr3_5fclkdiv_5f2_611',['FSMC_BTR3_CLKDIV_2',['../group___peripheral___registers___bits___definition.html#gaf806c044b2a3d1417acc79907dcaef4b',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr3_5fclkdiv_5f3_612',['FSMC_BTR3_CLKDIV_3',['../group___peripheral___registers___bits___definition.html#gaa9bf0683d046f9bcfb0d55a065ae69ab',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr3_5fclkdiv_5fmsk_613',['FSMC_BTR3_CLKDIV_Msk',['../group___peripheral___registers___bits___definition.html#ga050d3fd57381342b9c5d1153623e5d64',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr3_5fclkdiv_5fpos_614',['FSMC_BTR3_CLKDIV_Pos',['../group___peripheral___registers___bits___definition.html#gada052eafe7f4ee032f364b82040350a9',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr3_5fdatast_615',['FSMC_BTR3_DATAST',['../group___peripheral___registers___bits___definition.html#ga1e9ac671a510ee06e86c41d7876ffe10',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr3_5fdatast_5f0_616',['FSMC_BTR3_DATAST_0',['../group___peripheral___registers___bits___definition.html#ga65fe87d29c1a4ee0b08014ed8e0423e1',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr3_5fdatast_5f1_617',['FSMC_BTR3_DATAST_1',['../group___peripheral___registers___bits___definition.html#gad33e3df5c80255cb5e11ba427e9c224f',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr3_5fdatast_5f2_618',['FSMC_BTR3_DATAST_2',['../group___peripheral___registers___bits___definition.html#ga4a31f070e41c6785ebc606d4f25d103a',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr3_5fdatast_5f3_619',['FSMC_BTR3_DATAST_3',['../group___peripheral___registers___bits___definition.html#gad220fbd264261a37eac09d4f6c0b79a2',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr3_5fdatast_5f4_620',['FSMC_BTR3_DATAST_4',['../group___peripheral___registers___bits___definition.html#gab78ca925e07c24a308b1e603ed42aae1',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr3_5fdatast_5f5_621',['FSMC_BTR3_DATAST_5',['../group___peripheral___registers___bits___definition.html#ga3b61775591ffb8faef03a13435fd98b8',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr3_5fdatast_5f6_622',['FSMC_BTR3_DATAST_6',['../group___peripheral___registers___bits___definition.html#ga2d58607a3de993f0f7227a14b81ab56c',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr3_5fdatast_5f7_623',['FSMC_BTR3_DATAST_7',['../group___peripheral___registers___bits___definition.html#ga10dc7226824fa6ad00380417b3ba095d',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr3_5fdatast_5fmsk_624',['FSMC_BTR3_DATAST_Msk',['../group___peripheral___registers___bits___definition.html#gaf38dfdbab53cbef7b90eb2503114f121',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr3_5fdatast_5fpos_625',['FSMC_BTR3_DATAST_Pos',['../group___peripheral___registers___bits___definition.html#ga524942cc9d0eaf2095a6598db32db389',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr3_5fdatlat_626',['FSMC_BTR3_DATLAT',['../group___peripheral___registers___bits___definition.html#gaa88a80458ddd56b0dfa7cf3599b986dd',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr3_5fdatlat_5f0_627',['FSMC_BTR3_DATLAT_0',['../group___peripheral___registers___bits___definition.html#ga655083fdb0e563b9a4d6ea589194ba02',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr3_5fdatlat_5f1_628',['FSMC_BTR3_DATLAT_1',['../group___peripheral___registers___bits___definition.html#ga486280713c8f07d7033bce4e74825130',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr3_5fdatlat_5f2_629',['FSMC_BTR3_DATLAT_2',['../group___peripheral___registers___bits___definition.html#ga8314e30c84dccd983de04fdeeb57c360',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr3_5fdatlat_5f3_630',['FSMC_BTR3_DATLAT_3',['../group___peripheral___registers___bits___definition.html#gac7e7da5269a2dac164c9d1d01da2bc28',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr3_5fdatlat_5fmsk_631',['FSMC_BTR3_DATLAT_Msk',['../group___peripheral___registers___bits___definition.html#ga8e8b7682eb997746f807814f4d41ca6b',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr3_5fdatlat_5fpos_632',['FSMC_BTR3_DATLAT_Pos',['../group___peripheral___registers___bits___definition.html#ga949454e87f17316a0253839e17ebacc6',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr4_5faccmod_633',['FSMC_BTR4_ACCMOD',['../group___peripheral___registers___bits___definition.html#gabbf731d99007936586f9e15f17c3c771',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr4_5faccmod_5f0_634',['FSMC_BTR4_ACCMOD_0',['../group___peripheral___registers___bits___definition.html#ga8e69759ab89b16573bafd2f6ded95bfb',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr4_5faccmod_5f1_635',['FSMC_BTR4_ACCMOD_1',['../group___peripheral___registers___bits___definition.html#ga3e486b11f6af0f566f8843a5c95c6a6c',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr4_5faccmod_5fmsk_636',['FSMC_BTR4_ACCMOD_Msk',['../group___peripheral___registers___bits___definition.html#ga37535c8d3cc7d4388312e6640d513f6a',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr4_5faccmod_5fpos_637',['FSMC_BTR4_ACCMOD_Pos',['../group___peripheral___registers___bits___definition.html#ga88757eb5c47614f56b9fb13646b437e8',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr4_5faddhld_638',['FSMC_BTR4_ADDHLD',['../group___peripheral___registers___bits___definition.html#ga1e52ae9a5d59507bdf9f4f9da19444ed',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr4_5faddhld_5f0_639',['FSMC_BTR4_ADDHLD_0',['../group___peripheral___registers___bits___definition.html#gadf6200f13c3eed1e9646750897a987a2',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr4_5faddhld_5f1_640',['FSMC_BTR4_ADDHLD_1',['../group___peripheral___registers___bits___definition.html#ga0803bc2ad60138e0eef53a53ca5bf537',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr4_5faddhld_5f2_641',['FSMC_BTR4_ADDHLD_2',['../group___peripheral___registers___bits___definition.html#ga893711250b9d3ea2e5e48ca53d1e0147',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr4_5faddhld_5f3_642',['FSMC_BTR4_ADDHLD_3',['../group___peripheral___registers___bits___definition.html#ga75c73d4bb0ddcac383ca610a604d95b3',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr4_5faddhld_5fmsk_643',['FSMC_BTR4_ADDHLD_Msk',['../group___peripheral___registers___bits___definition.html#gaaabb5da557aa89d3f786f2bae2fb3bf0',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr4_5faddhld_5fpos_644',['FSMC_BTR4_ADDHLD_Pos',['../group___peripheral___registers___bits___definition.html#gab3d440dee3fe200e9aaeaa5ca74c7cda',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr4_5faddset_645',['FSMC_BTR4_ADDSET',['../group___peripheral___registers___bits___definition.html#gab44cc2146b4cf6bc8f43292512fd8cf8',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr4_5faddset_5f0_646',['FSMC_BTR4_ADDSET_0',['../group___peripheral___registers___bits___definition.html#gaa0ee1ab3716b0ab1a4e7b51234af7c63',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr4_5faddset_5f1_647',['FSMC_BTR4_ADDSET_1',['../group___peripheral___registers___bits___definition.html#gacd427c001c5b17a3e083c81f6b228a50',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr4_5faddset_5f2_648',['FSMC_BTR4_ADDSET_2',['../group___peripheral___registers___bits___definition.html#gae722fdaa69bfb7622aa80c82e3772949',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr4_5faddset_5f3_649',['FSMC_BTR4_ADDSET_3',['../group___peripheral___registers___bits___definition.html#ga0f8ab4a1c7fe6e7dc2b093add88c274e',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr4_5faddset_5fmsk_650',['FSMC_BTR4_ADDSET_Msk',['../group___peripheral___registers___bits___definition.html#ga6ffb05b35bc25ca9f5f8629e241482c2',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr4_5faddset_5fpos_651',['FSMC_BTR4_ADDSET_Pos',['../group___peripheral___registers___bits___definition.html#gabeff2f8b714d12899beab5530219676b',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr4_5fbusturn_652',['FSMC_BTR4_BUSTURN',['../group___peripheral___registers___bits___definition.html#ga207a9eedfc1b244c393be3c34ea60a15',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr4_5fbusturn_5f0_653',['FSMC_BTR4_BUSTURN_0',['../group___peripheral___registers___bits___definition.html#ga4dec1fa50fca6639be7179d445aacfe4',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr4_5fbusturn_5f1_654',['FSMC_BTR4_BUSTURN_1',['../group___peripheral___registers___bits___definition.html#gab1db211382068251dc5cfe44a175e639',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr4_5fbusturn_5f2_655',['FSMC_BTR4_BUSTURN_2',['../group___peripheral___registers___bits___definition.html#gaa5391a8c2a1e8cd6abb81fa5b2836464',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr4_5fbusturn_5f3_656',['FSMC_BTR4_BUSTURN_3',['../group___peripheral___registers___bits___definition.html#gadbfd74790a1e25339151de440e3a93e5',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr4_5fbusturn_5fmsk_657',['FSMC_BTR4_BUSTURN_Msk',['../group___peripheral___registers___bits___definition.html#gaa72c6ff1ec6f4fb7dee9a109ddc9835f',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr4_5fbusturn_5fpos_658',['FSMC_BTR4_BUSTURN_Pos',['../group___peripheral___registers___bits___definition.html#ga98966c488a394376e2b3bff182317cf6',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr4_5fclkdiv_659',['FSMC_BTR4_CLKDIV',['../group___peripheral___registers___bits___definition.html#ga7ac39964e3792653e454538407b11504',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr4_5fclkdiv_5f0_660',['FSMC_BTR4_CLKDIV_0',['../group___peripheral___registers___bits___definition.html#gaacee394c98ac568fe1d6df61c887ed53',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr4_5fclkdiv_5f1_661',['FSMC_BTR4_CLKDIV_1',['../group___peripheral___registers___bits___definition.html#ga9c7cd1d1a4954d494bd107400925f86f',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr4_5fclkdiv_5f2_662',['FSMC_BTR4_CLKDIV_2',['../group___peripheral___registers___bits___definition.html#ga93b0ab3235ffacca24e6b285460c5dd3',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr4_5fclkdiv_5f3_663',['FSMC_BTR4_CLKDIV_3',['../group___peripheral___registers___bits___definition.html#ga931463443390c5a706303e87a538d1ce',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr4_5fclkdiv_5fmsk_664',['FSMC_BTR4_CLKDIV_Msk',['../group___peripheral___registers___bits___definition.html#ga20d19a8021d7c397928886a751546a0f',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr4_5fclkdiv_5fpos_665',['FSMC_BTR4_CLKDIV_Pos',['../group___peripheral___registers___bits___definition.html#ga97a0c80d8b160a03fb4276150054be56',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr4_5fdatast_666',['FSMC_BTR4_DATAST',['../group___peripheral___registers___bits___definition.html#ga2c28625ee031527a29f7cb7db1bb97cf',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr4_5fdatast_5f0_667',['FSMC_BTR4_DATAST_0',['../group___peripheral___registers___bits___definition.html#gabdb0212604c6c58c9524adc7931e2897',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr4_5fdatast_5f1_668',['FSMC_BTR4_DATAST_1',['../group___peripheral___registers___bits___definition.html#ga2353d753ca5532703b4f822b7d2a7382',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr4_5fdatast_5f2_669',['FSMC_BTR4_DATAST_2',['../group___peripheral___registers___bits___definition.html#ga8d82a6f3fcf69d6b96968118db7b8216',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr4_5fdatast_5f3_670',['FSMC_BTR4_DATAST_3',['../group___peripheral___registers___bits___definition.html#ga3e0860f92bb204c4b5902d3e34b8b30a',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr4_5fdatast_5f4_671',['FSMC_BTR4_DATAST_4',['../group___peripheral___registers___bits___definition.html#ga7d6f871ca941d2beed194d2fc5190183',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr4_5fdatast_5f5_672',['FSMC_BTR4_DATAST_5',['../group___peripheral___registers___bits___definition.html#gaa798a7170769793b25d5cc37e9eff679',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr4_5fdatast_5f6_673',['FSMC_BTR4_DATAST_6',['../group___peripheral___registers___bits___definition.html#gac4c89f39ac5a74bdd3fc406da173fe79',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr4_5fdatast_5f7_674',['FSMC_BTR4_DATAST_7',['../group___peripheral___registers___bits___definition.html#ga633b76f7fce6507cf044dcb3d82a0d8d',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr4_5fdatast_5fmsk_675',['FSMC_BTR4_DATAST_Msk',['../group___peripheral___registers___bits___definition.html#gab99647a6ac8c924ad739bc5cc7244c01',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr4_5fdatast_5fpos_676',['FSMC_BTR4_DATAST_Pos',['../group___peripheral___registers___bits___definition.html#ga66d0e68db7568649671e7b0338acb688',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr4_5fdatlat_677',['FSMC_BTR4_DATLAT',['../group___peripheral___registers___bits___definition.html#gaa53cb7c299e794915d3aba803374adca',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr4_5fdatlat_5f0_678',['FSMC_BTR4_DATLAT_0',['../group___peripheral___registers___bits___definition.html#gad2315f17d1cd7dd9da1b0ee2f7e4ea29',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr4_5fdatlat_5f1_679',['FSMC_BTR4_DATLAT_1',['../group___peripheral___registers___bits___definition.html#ga808a7d758e6ca75c573d08ee92228745',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr4_5fdatlat_5f2_680',['FSMC_BTR4_DATLAT_2',['../group___peripheral___registers___bits___definition.html#gac376a62779292d64bfac24d572b743e9',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr4_5fdatlat_5f3_681',['FSMC_BTR4_DATLAT_3',['../group___peripheral___registers___bits___definition.html#gadfc558894dcb263451dbac13f48fffe1',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr4_5fdatlat_5fmsk_682',['FSMC_BTR4_DATLAT_Msk',['../group___peripheral___registers___bits___definition.html#ga737ae8e9d7fbf9906256a03e24d498aa',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbtr4_5fdatlat_5fpos_683',['FSMC_BTR4_DATLAT_Pos',['../group___peripheral___registers___bits___definition.html#gaa90d3bce2e4d950c80022117b564cb2c',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbwtr1_5faccmod_684',['FSMC_BWTR1_ACCMOD',['../group___peripheral___registers___bits___definition.html#gaa676b8e4f48602c27ea8edab61ce5db0',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbwtr1_5faccmod_5f0_685',['FSMC_BWTR1_ACCMOD_0',['../group___peripheral___registers___bits___definition.html#gae87cae14e6bb4403b420fc9e4084d6e2',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbwtr1_5faccmod_5f1_686',['FSMC_BWTR1_ACCMOD_1',['../group___peripheral___registers___bits___definition.html#gac0cddde5db2e0bb09f1c8938afd6ac98',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbwtr1_5faccmod_5fmsk_687',['FSMC_BWTR1_ACCMOD_Msk',['../group___peripheral___registers___bits___definition.html#gaeb84768b1b7f99be132fd7fabf109710',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbwtr1_5faccmod_5fpos_688',['FSMC_BWTR1_ACCMOD_Pos',['../group___peripheral___registers___bits___definition.html#ga1339ee30e40045b01377267cdcdf2e42',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbwtr1_5faddhld_689',['FSMC_BWTR1_ADDHLD',['../group___peripheral___registers___bits___definition.html#gafa3d8ff62f87ab6aeb5170dd67de15cf',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbwtr1_5faddhld_5f0_690',['FSMC_BWTR1_ADDHLD_0',['../group___peripheral___registers___bits___definition.html#ga1e24880c23375636d7504d42077a400a',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbwtr1_5faddhld_5f1_691',['FSMC_BWTR1_ADDHLD_1',['../group___peripheral___registers___bits___definition.html#gafb90dec93198b1d3077feb5fe508f004',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbwtr1_5faddhld_5f2_692',['FSMC_BWTR1_ADDHLD_2',['../group___peripheral___registers___bits___definition.html#ga26ef7d6cd5ec547a349462e4f31963b6',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbwtr1_5faddhld_5f3_693',['FSMC_BWTR1_ADDHLD_3',['../group___peripheral___registers___bits___definition.html#gac4a961ecd844e14a90d1b2f6c5d59196',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbwtr1_5faddhld_5fmsk_694',['FSMC_BWTR1_ADDHLD_Msk',['../group___peripheral___registers___bits___definition.html#ga4772c530938b9f655bb0a807b9cd0f9d',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbwtr1_5faddhld_5fpos_695',['FSMC_BWTR1_ADDHLD_Pos',['../group___peripheral___registers___bits___definition.html#gaa6e3be36c874835e8d5b50c546a6e5ce',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbwtr1_5faddset_696',['FSMC_BWTR1_ADDSET',['../group___peripheral___registers___bits___definition.html#ga4aa5ee153cb4bf79f0d4ae2c47f365c4',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbwtr1_5faddset_5f0_697',['FSMC_BWTR1_ADDSET_0',['../group___peripheral___registers___bits___definition.html#gaacb80aeedb6d0d9cb09e7b4d3ff8b541',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbwtr1_5faddset_5f1_698',['FSMC_BWTR1_ADDSET_1',['../group___peripheral___registers___bits___definition.html#ga20dbbdff1e2f1d57727dabbc4b03c840',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbwtr1_5faddset_5f2_699',['FSMC_BWTR1_ADDSET_2',['../group___peripheral___registers___bits___definition.html#ga411f0d164c26dda8132ff22856757470',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbwtr1_5faddset_5f3_700',['FSMC_BWTR1_ADDSET_3',['../group___peripheral___registers___bits___definition.html#ga3e2bc67999e8d2b63771fa223ffa8e4d',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbwtr1_5faddset_5fmsk_701',['FSMC_BWTR1_ADDSET_Msk',['../group___peripheral___registers___bits___definition.html#ga513a9612a5c7c61086b2f85d83e2653f',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbwtr1_5faddset_5fpos_702',['FSMC_BWTR1_ADDSET_Pos',['../group___peripheral___registers___bits___definition.html#ga52ddd50ef2636a8e0bb45957d72b6a49',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbwtr1_5fbusturn_703',['FSMC_BWTR1_BUSTURN',['../group___peripheral___registers___bits___definition.html#ga01289633ae20e7face5cb85cc031b532',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbwtr1_5fbusturn_5f0_704',['FSMC_BWTR1_BUSTURN_0',['../group___peripheral___registers___bits___definition.html#ga98fad3a30bdcb37dadcf7a443798e202',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbwtr1_5fbusturn_5f1_705',['FSMC_BWTR1_BUSTURN_1',['../group___peripheral___registers___bits___definition.html#ga8c0dc053a9639673abb045e1d50756fa',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbwtr1_5fbusturn_5f2_706',['FSMC_BWTR1_BUSTURN_2',['../group___peripheral___registers___bits___definition.html#gafafcc625222c5be36a617572881d6704',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbwtr1_5fbusturn_5f3_707',['FSMC_BWTR1_BUSTURN_3',['../group___peripheral___registers___bits___definition.html#gafd830ff4d12444139479977ee13c730b',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbwtr1_5fbusturn_5fmsk_708',['FSMC_BWTR1_BUSTURN_Msk',['../group___peripheral___registers___bits___definition.html#ga60c9f9abbf9f8110e9d7d5b729932af0',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbwtr1_5fbusturn_5fpos_709',['FSMC_BWTR1_BUSTURN_Pos',['../group___peripheral___registers___bits___definition.html#gade809e856484f40f6e54001fd88c7c80',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbwtr1_5fdatast_710',['FSMC_BWTR1_DATAST',['../group___peripheral___registers___bits___definition.html#gaee2641a6f415d03df324667662bd3dcf',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbwtr1_5fdatast_5f0_711',['FSMC_BWTR1_DATAST_0',['../group___peripheral___registers___bits___definition.html#ga162800452847dd98d27a4078370518b2',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbwtr1_5fdatast_5f1_712',['FSMC_BWTR1_DATAST_1',['../group___peripheral___registers___bits___definition.html#ga16476bfbbcb9726c1fbc593d3568a514',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbwtr1_5fdatast_5f2_713',['FSMC_BWTR1_DATAST_2',['../group___peripheral___registers___bits___definition.html#ga623de376d9f5189d73068d0865a5049e',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbwtr1_5fdatast_5f3_714',['FSMC_BWTR1_DATAST_3',['../group___peripheral___registers___bits___definition.html#gade0627f53e3df25fdaa973db6159bd70',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbwtr1_5fdatast_5f4_715',['FSMC_BWTR1_DATAST_4',['../group___peripheral___registers___bits___definition.html#ga39b5d7ddf6673ff23684c147c192f61b',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbwtr1_5fdatast_5f5_716',['FSMC_BWTR1_DATAST_5',['../group___peripheral___registers___bits___definition.html#ga211042c480c7d87941b584a591f7d0ab',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbwtr1_5fdatast_5f6_717',['FSMC_BWTR1_DATAST_6',['../group___peripheral___registers___bits___definition.html#ga62232d4ec2bbbf375cfa555f947345fa',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbwtr1_5fdatast_5f7_718',['FSMC_BWTR1_DATAST_7',['../group___peripheral___registers___bits___definition.html#ga7768908f2843432c6e4a4eb8e5153539',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbwtr1_5fdatast_5fmsk_719',['FSMC_BWTR1_DATAST_Msk',['../group___peripheral___registers___bits___definition.html#ga3de71f2a794f4e7a5e3135c715f644cc',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbwtr1_5fdatast_5fpos_720',['FSMC_BWTR1_DATAST_Pos',['../group___peripheral___registers___bits___definition.html#ga816436841706a81e91cc1627906c7e64',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbwtr2_5faccmod_721',['FSMC_BWTR2_ACCMOD',['../group___peripheral___registers___bits___definition.html#ga320be3e2e266dc25bd02e10787b2ba0d',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbwtr2_5faccmod_5f0_722',['FSMC_BWTR2_ACCMOD_0',['../group___peripheral___registers___bits___definition.html#gaabe5419d99a7ad4d4eb761c82077d958',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbwtr2_5faccmod_5f1_723',['FSMC_BWTR2_ACCMOD_1',['../group___peripheral___registers___bits___definition.html#gab6cdd284ad94abfef0f24fcb813b4558',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbwtr2_5faccmod_5fmsk_724',['FSMC_BWTR2_ACCMOD_Msk',['../group___peripheral___registers___bits___definition.html#ga2cebbf681a61a82429105f62eff22230',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbwtr2_5faccmod_5fpos_725',['FSMC_BWTR2_ACCMOD_Pos',['../group___peripheral___registers___bits___definition.html#gab50bf8884bd5bfd9845932225b058333',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbwtr2_5faddhld_726',['FSMC_BWTR2_ADDHLD',['../group___peripheral___registers___bits___definition.html#gae879db1879650f99b1c75635884bda17',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbwtr2_5faddhld_5f0_727',['FSMC_BWTR2_ADDHLD_0',['../group___peripheral___registers___bits___definition.html#gaf5826c5d5c544cd59210c071358fb8e9',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbwtr2_5faddhld_5f1_728',['FSMC_BWTR2_ADDHLD_1',['../group___peripheral___registers___bits___definition.html#ga258acf47f7706a1cd0b0a914e63cbe17',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbwtr2_5faddhld_5f2_729',['FSMC_BWTR2_ADDHLD_2',['../group___peripheral___registers___bits___definition.html#ga39f1a9ccc80d1218935936539a000b84',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbwtr2_5faddhld_5f3_730',['FSMC_BWTR2_ADDHLD_3',['../group___peripheral___registers___bits___definition.html#ga81de376a21fc25a7e1c31db341dfcd3f',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbwtr2_5faddhld_5fmsk_731',['FSMC_BWTR2_ADDHLD_Msk',['../group___peripheral___registers___bits___definition.html#ga5a432338fb1c54a6d09a5646556dc1a0',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbwtr2_5faddhld_5fpos_732',['FSMC_BWTR2_ADDHLD_Pos',['../group___peripheral___registers___bits___definition.html#ga71f8b02d43d99e0de2b34cc269d85d60',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbwtr2_5faddset_733',['FSMC_BWTR2_ADDSET',['../group___peripheral___registers___bits___definition.html#ga7b6553bd9ad305aa42341e08b1736260',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbwtr2_5faddset_5f0_734',['FSMC_BWTR2_ADDSET_0',['../group___peripheral___registers___bits___definition.html#ga593fe1987e8c6052cdb992e629f1d059',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbwtr2_5faddset_5f1_735',['FSMC_BWTR2_ADDSET_1',['../group___peripheral___registers___bits___definition.html#ga6dc23a2314a44b6ad9f293716f0c8a11',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbwtr2_5faddset_5f2_736',['FSMC_BWTR2_ADDSET_2',['../group___peripheral___registers___bits___definition.html#ga1e9c799b36f45cad86a3f98d262baa6d',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbwtr2_5faddset_5f3_737',['FSMC_BWTR2_ADDSET_3',['../group___peripheral___registers___bits___definition.html#ga95abc246eb528275d894346c0665e930',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbwtr2_5faddset_5fmsk_738',['FSMC_BWTR2_ADDSET_Msk',['../group___peripheral___registers___bits___definition.html#ga124ca65a19ddd2bf11faba48c98f3e84',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbwtr2_5faddset_5fpos_739',['FSMC_BWTR2_ADDSET_Pos',['../group___peripheral___registers___bits___definition.html#gadf19233630fc32a605d2a4898cb93a7b',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbwtr2_5fbusturn_740',['FSMC_BWTR2_BUSTURN',['../group___peripheral___registers___bits___definition.html#ga46c9ba35109d12ff41e5d40f16911546',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbwtr2_5fbusturn_5f0_741',['FSMC_BWTR2_BUSTURN_0',['../group___peripheral___registers___bits___definition.html#gad2e0a32552e1d57efa9ecacb5121a685',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbwtr2_5fbusturn_5f1_742',['FSMC_BWTR2_BUSTURN_1',['../group___peripheral___registers___bits___definition.html#gaec6ea37fe04083cee9202e3b814095cd',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbwtr2_5fbusturn_5f2_743',['FSMC_BWTR2_BUSTURN_2',['../group___peripheral___registers___bits___definition.html#gaff765b875a7e16a849d6019e1af147f0',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbwtr2_5fbusturn_5f3_744',['FSMC_BWTR2_BUSTURN_3',['../group___peripheral___registers___bits___definition.html#ga6a0684d050236cdf6c0a1b6e99c523fd',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbwtr2_5fbusturn_5fmsk_745',['FSMC_BWTR2_BUSTURN_Msk',['../group___peripheral___registers___bits___definition.html#ga02edb530ab2bf59ff2d2c1339177dc5b',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbwtr2_5fbusturn_5fpos_746',['FSMC_BWTR2_BUSTURN_Pos',['../group___peripheral___registers___bits___definition.html#gaf50bc4030068335c54e73016b0e72d37',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbwtr2_5fdatast_747',['FSMC_BWTR2_DATAST',['../group___peripheral___registers___bits___definition.html#gab280652524006fbb3820597112136f14',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbwtr2_5fdatast_5f0_748',['FSMC_BWTR2_DATAST_0',['../group___peripheral___registers___bits___definition.html#ga78a0f0466162848135313296ebf44890',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbwtr2_5fdatast_5f1_749',['FSMC_BWTR2_DATAST_1',['../group___peripheral___registers___bits___definition.html#ga51e43e17e99141c9009c779cc359323a',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbwtr2_5fdatast_5f2_750',['FSMC_BWTR2_DATAST_2',['../group___peripheral___registers___bits___definition.html#ga1f8791c2a33f740f905d45e3754e3353',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbwtr2_5fdatast_5f3_751',['FSMC_BWTR2_DATAST_3',['../group___peripheral___registers___bits___definition.html#ga8a2a5797dd14b5b89581c5fb08872fae',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbwtr2_5fdatast_5f4_752',['FSMC_BWTR2_DATAST_4',['../group___peripheral___registers___bits___definition.html#ga59727cc45244014c0837b63b79787ef8',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbwtr2_5fdatast_5f5_753',['FSMC_BWTR2_DATAST_5',['../group___peripheral___registers___bits___definition.html#gad7bb34356cc805ef2354194307e4119c',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbwtr2_5fdatast_5f6_754',['FSMC_BWTR2_DATAST_6',['../group___peripheral___registers___bits___definition.html#ga348a18f1a4b0c5463a8692a9f12464a9',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbwtr2_5fdatast_5f7_755',['FSMC_BWTR2_DATAST_7',['../group___peripheral___registers___bits___definition.html#ga6497892b70d765d6f54b43351140d9c8',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbwtr2_5fdatast_5fmsk_756',['FSMC_BWTR2_DATAST_Msk',['../group___peripheral___registers___bits___definition.html#ga1a8e67d5ff1e02c745ce4db92a251e7f',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbwtr2_5fdatast_5fpos_757',['FSMC_BWTR2_DATAST_Pos',['../group___peripheral___registers___bits___definition.html#ga4f1969ba212c34f57a767b158e6f80ed',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbwtr3_5faccmod_758',['FSMC_BWTR3_ACCMOD',['../group___peripheral___registers___bits___definition.html#gaa32a792c0c93d854a90bfbc36fa1329b',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbwtr3_5faccmod_5f0_759',['FSMC_BWTR3_ACCMOD_0',['../group___peripheral___registers___bits___definition.html#ga64d4e414ea73b47e07364e1a121af6a4',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbwtr3_5faccmod_5f1_760',['FSMC_BWTR3_ACCMOD_1',['../group___peripheral___registers___bits___definition.html#gada733b2bda718299345fd0191b25b49f',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbwtr3_5faccmod_5fmsk_761',['FSMC_BWTR3_ACCMOD_Msk',['../group___peripheral___registers___bits___definition.html#gafcc2c37152b55b3c8c5e178778567261',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbwtr3_5faccmod_5fpos_762',['FSMC_BWTR3_ACCMOD_Pos',['../group___peripheral___registers___bits___definition.html#gacad6fb10201c4c9c3e022b8551143f1f',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbwtr3_5faddhld_763',['FSMC_BWTR3_ADDHLD',['../group___peripheral___registers___bits___definition.html#gae3d031a0d71677932a68639ba88bd13e',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbwtr3_5faddhld_5f0_764',['FSMC_BWTR3_ADDHLD_0',['../group___peripheral___registers___bits___definition.html#ga5b3948c407a5a4be6a21cccad0a8d12d',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbwtr3_5faddhld_5f1_765',['FSMC_BWTR3_ADDHLD_1',['../group___peripheral___registers___bits___definition.html#gaea21d05228f7771c6306726af5da5a4a',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbwtr3_5faddhld_5f2_766',['FSMC_BWTR3_ADDHLD_2',['../group___peripheral___registers___bits___definition.html#gaa574b3a1efe581d195789dcc8bba01f8',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbwtr3_5faddhld_5f3_767',['FSMC_BWTR3_ADDHLD_3',['../group___peripheral___registers___bits___definition.html#gaae8216cf865785468af58dbce0002a7c',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbwtr3_5faddhld_5fmsk_768',['FSMC_BWTR3_ADDHLD_Msk',['../group___peripheral___registers___bits___definition.html#ga1025758662868a34da456a8f3c9600dd',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbwtr3_5faddhld_5fpos_769',['FSMC_BWTR3_ADDHLD_Pos',['../group___peripheral___registers___bits___definition.html#gae752c10ea876415cf0b54aca8c7d77e7',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbwtr3_5faddset_770',['FSMC_BWTR3_ADDSET',['../group___peripheral___registers___bits___definition.html#ga455ba53d0f18173b0694d71757a084ff',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbwtr3_5faddset_5f0_771',['FSMC_BWTR3_ADDSET_0',['../group___peripheral___registers___bits___definition.html#ga9dddd5ba924b56867c9cb39484ef498d',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbwtr3_5faddset_5f1_772',['FSMC_BWTR3_ADDSET_1',['../group___peripheral___registers___bits___definition.html#gacd242d768da1f9ab4304e91e5dabb5a9',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbwtr3_5faddset_5f2_773',['FSMC_BWTR3_ADDSET_2',['../group___peripheral___registers___bits___definition.html#gaef99967dc66814cf5d732365c40daebb',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbwtr3_5faddset_5f3_774',['FSMC_BWTR3_ADDSET_3',['../group___peripheral___registers___bits___definition.html#ga471ebb2d47fb951340df6ba22b40a788',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbwtr3_5faddset_5fmsk_775',['FSMC_BWTR3_ADDSET_Msk',['../group___peripheral___registers___bits___definition.html#gafcc45a7e8a398c8932cd545fb3ed10a6',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbwtr3_5faddset_5fpos_776',['FSMC_BWTR3_ADDSET_Pos',['../group___peripheral___registers___bits___definition.html#ga7e8110634778086f551394937f738ff9',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbwtr3_5fbusturn_777',['FSMC_BWTR3_BUSTURN',['../group___peripheral___registers___bits___definition.html#ga333004366913e1c938f2efb57c259c39',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbwtr3_5fbusturn_5f0_778',['FSMC_BWTR3_BUSTURN_0',['../group___peripheral___registers___bits___definition.html#ga966a4bb7d0878efc320d50457c26749d',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbwtr3_5fbusturn_5f1_779',['FSMC_BWTR3_BUSTURN_1',['../group___peripheral___registers___bits___definition.html#ga44b560ff9aaa44e2f4a18ac548c8d65e',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbwtr3_5fbusturn_5f2_780',['FSMC_BWTR3_BUSTURN_2',['../group___peripheral___registers___bits___definition.html#ga89448c3668da87fe261d575166325f3d',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbwtr3_5fbusturn_5f3_781',['FSMC_BWTR3_BUSTURN_3',['../group___peripheral___registers___bits___definition.html#ga86e615ef161c836eb338cc410f474cf6',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbwtr3_5fbusturn_5fmsk_782',['FSMC_BWTR3_BUSTURN_Msk',['../group___peripheral___registers___bits___definition.html#ga4922c75c6b3c2baf134ad5119a97a098',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbwtr3_5fbusturn_5fpos_783',['FSMC_BWTR3_BUSTURN_Pos',['../group___peripheral___registers___bits___definition.html#ga5b60d7fbc787a9d6df78fbc5fea4c206',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbwtr3_5fdatast_784',['FSMC_BWTR3_DATAST',['../group___peripheral___registers___bits___definition.html#gae93d9fee8a67491918526019b439a00f',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbwtr3_5fdatast_5f0_785',['FSMC_BWTR3_DATAST_0',['../group___peripheral___registers___bits___definition.html#gaf1ec40c6360faeb133cb224a6789bb51',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbwtr3_5fdatast_5f1_786',['FSMC_BWTR3_DATAST_1',['../group___peripheral___registers___bits___definition.html#gacaf23316e44d731620f0cbde29ae9a93',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbwtr3_5fdatast_5f2_787',['FSMC_BWTR3_DATAST_2',['../group___peripheral___registers___bits___definition.html#ga31686e755ef0f98078d96c08891cf8f4',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbwtr3_5fdatast_5f3_788',['FSMC_BWTR3_DATAST_3',['../group___peripheral___registers___bits___definition.html#ga5a291f74abf021a7fe66ce8afd714c39',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbwtr3_5fdatast_5f4_789',['FSMC_BWTR3_DATAST_4',['../group___peripheral___registers___bits___definition.html#gacd5b6e11c52314eb07772d72353002fa',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbwtr3_5fdatast_5f5_790',['FSMC_BWTR3_DATAST_5',['../group___peripheral___registers___bits___definition.html#ga590322c15eb3fb579edec41fd4a86ea5',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbwtr3_5fdatast_5f6_791',['FSMC_BWTR3_DATAST_6',['../group___peripheral___registers___bits___definition.html#ga3aec6604821cd38fafbceeaf81556d63',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbwtr3_5fdatast_5f7_792',['FSMC_BWTR3_DATAST_7',['../group___peripheral___registers___bits___definition.html#ga79e7035f0bb60e6082f699ee98d2ffc2',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbwtr3_5fdatast_5fmsk_793',['FSMC_BWTR3_DATAST_Msk',['../group___peripheral___registers___bits___definition.html#ga51d5ed2f485b7b92825e4677e11e095a',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbwtr3_5fdatast_5fpos_794',['FSMC_BWTR3_DATAST_Pos',['../group___peripheral___registers___bits___definition.html#gadfc2a85d6970397944903ed17252a68d',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbwtr4_5faccmod_795',['FSMC_BWTR4_ACCMOD',['../group___peripheral___registers___bits___definition.html#ga1d13f46a945d5daf6ec339781d3926a9',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbwtr4_5faccmod_5f0_796',['FSMC_BWTR4_ACCMOD_0',['../group___peripheral___registers___bits___definition.html#ga5e30f51c68b4ac4f9efee2cd5a45943c',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbwtr4_5faccmod_5f1_797',['FSMC_BWTR4_ACCMOD_1',['../group___peripheral___registers___bits___definition.html#gaf7ba26fb09f035addbe1e4c3b0d093c9',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbwtr4_5faccmod_5fmsk_798',['FSMC_BWTR4_ACCMOD_Msk',['../group___peripheral___registers___bits___definition.html#gab9daae3a3b8aaafa7afc2069debd8d14',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbwtr4_5faccmod_5fpos_799',['FSMC_BWTR4_ACCMOD_Pos',['../group___peripheral___registers___bits___definition.html#ga8fc1deea073ae82799fcda8073bdeccb',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbwtr4_5faddhld_800',['FSMC_BWTR4_ADDHLD',['../group___peripheral___registers___bits___definition.html#gaafe1198e70d843c883260d354b7ce7b5',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbwtr4_5faddhld_5f0_801',['FSMC_BWTR4_ADDHLD_0',['../group___peripheral___registers___bits___definition.html#gac62786f538820baa3f0f8edb17ef1b74',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbwtr4_5faddhld_5f1_802',['FSMC_BWTR4_ADDHLD_1',['../group___peripheral___registers___bits___definition.html#gaa69aa2d9cafe8f952721c88083c8a94e',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbwtr4_5faddhld_5f2_803',['FSMC_BWTR4_ADDHLD_2',['../group___peripheral___registers___bits___definition.html#ga4c6d991498c385991b461832fb093399',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbwtr4_5faddhld_5f3_804',['FSMC_BWTR4_ADDHLD_3',['../group___peripheral___registers___bits___definition.html#gac744bdeb5b9ae048b1fa1a07ce9ce9d1',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbwtr4_5faddhld_5fmsk_805',['FSMC_BWTR4_ADDHLD_Msk',['../group___peripheral___registers___bits___definition.html#gab7cf1485c80e4326e49ab8dc889e5537',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbwtr4_5faddhld_5fpos_806',['FSMC_BWTR4_ADDHLD_Pos',['../group___peripheral___registers___bits___definition.html#gac40aa70101334a56d6ce4cb52d9a64bc',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbwtr4_5faddset_807',['FSMC_BWTR4_ADDSET',['../group___peripheral___registers___bits___definition.html#gaa8c3c14faf87768beced4e297edc7bfd',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbwtr4_5faddset_5f0_808',['FSMC_BWTR4_ADDSET_0',['../group___peripheral___registers___bits___definition.html#ga65ba73495f6192e409cc00f3e26e27e0',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbwtr4_5faddset_5f1_809',['FSMC_BWTR4_ADDSET_1',['../group___peripheral___registers___bits___definition.html#ga3cc9fa3c1ceae0724f5005bb1e101775',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbwtr4_5faddset_5f2_810',['FSMC_BWTR4_ADDSET_2',['../group___peripheral___registers___bits___definition.html#gad2007941f4869504bfef23edbcc18bfa',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbwtr4_5faddset_5f3_811',['FSMC_BWTR4_ADDSET_3',['../group___peripheral___registers___bits___definition.html#gabcde23639f64241d95b02f5b950ef3cc',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbwtr4_5faddset_5fmsk_812',['FSMC_BWTR4_ADDSET_Msk',['../group___peripheral___registers___bits___definition.html#gaac9acf4808b842bc735479c137aceb01',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbwtr4_5faddset_5fpos_813',['FSMC_BWTR4_ADDSET_Pos',['../group___peripheral___registers___bits___definition.html#ga46344b3ec4032b5a520833b6ba553b8f',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbwtr4_5fbusturn_814',['FSMC_BWTR4_BUSTURN',['../group___peripheral___registers___bits___definition.html#ga2251ad4a30e8fd743b5ee0cf1f64b479',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbwtr4_5fbusturn_5f0_815',['FSMC_BWTR4_BUSTURN_0',['../group___peripheral___registers___bits___definition.html#gacc959ee76e0bf42eca48b4cc8ddb5bf6',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbwtr4_5fbusturn_5f1_816',['FSMC_BWTR4_BUSTURN_1',['../group___peripheral___registers___bits___definition.html#ga1e77325faba8acb512b97a5bfac186df',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbwtr4_5fbusturn_5f2_817',['FSMC_BWTR4_BUSTURN_2',['../group___peripheral___registers___bits___definition.html#gabc92938093fc0c4da4b3e82b0ac0f440',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbwtr4_5fbusturn_5f3_818',['FSMC_BWTR4_BUSTURN_3',['../group___peripheral___registers___bits___definition.html#ga1c239a600bcaa8addc11ef97c5c6248c',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbwtr4_5fbusturn_5fmsk_819',['FSMC_BWTR4_BUSTURN_Msk',['../group___peripheral___registers___bits___definition.html#ga152a5383e408f7ec2e000fcf40f335df',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbwtr4_5fbusturn_5fpos_820',['FSMC_BWTR4_BUSTURN_Pos',['../group___peripheral___registers___bits___definition.html#gae5ff326880c026bb2a70e39e7ce48074',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbwtr4_5fdatast_821',['FSMC_BWTR4_DATAST',['../group___peripheral___registers___bits___definition.html#ga6656c89aac87fc226c0e80f8f753abeb',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbwtr4_5fdatast_5f0_822',['FSMC_BWTR4_DATAST_0',['../group___peripheral___registers___bits___definition.html#ga5636aaec144530e1c46e819b62c95f09',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbwtr4_5fdatast_5f1_823',['FSMC_BWTR4_DATAST_1',['../group___peripheral___registers___bits___definition.html#ga19eb9fccff444a00caf75b9d20a143ed',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbwtr4_5fdatast_5f2_824',['FSMC_BWTR4_DATAST_2',['../group___peripheral___registers___bits___definition.html#gaa40f9fa60ddb69fdcdcdface743f2c26',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbwtr4_5fdatast_5f3_825',['FSMC_BWTR4_DATAST_3',['../group___peripheral___registers___bits___definition.html#gafa173c5ff9a7d316cd67897f8e36dbf5',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbwtr4_5fdatast_5f4_826',['FSMC_BWTR4_DATAST_4',['../group___peripheral___registers___bits___definition.html#ga7c8dde48be5fa0ea0e920d72e7b43ad0',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbwtr4_5fdatast_5f5_827',['FSMC_BWTR4_DATAST_5',['../group___peripheral___registers___bits___definition.html#ga2ff7e92fad8d55c205ee1225868c54a4',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbwtr4_5fdatast_5f6_828',['FSMC_BWTR4_DATAST_6',['../group___peripheral___registers___bits___definition.html#ga2dbfd952e906c67ec6bb813d220638f9',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbwtr4_5fdatast_5f7_829',['FSMC_BWTR4_DATAST_7',['../group___peripheral___registers___bits___definition.html#ga67a7e379e49efcdb4a42ed45eb20c620',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbwtr4_5fdatast_5fmsk_830',['FSMC_BWTR4_DATAST_Msk',['../group___peripheral___registers___bits___definition.html#gae370408fcf34c2db09d389102c249b1e',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fbwtr4_5fdatast_5fpos_831',['FSMC_BWTR4_DATAST_Pos',['../group___peripheral___registers___bits___definition.html#gab82ad4f36968e5609b1adc15bc1d0dd5',1,'stm32f407xx_matlab.h']]], - ['fsmc_5feccr2_5fecc2_832',['FSMC_ECCR2_ECC2',['../group___peripheral___registers___bits___definition.html#ga43da355ad2eb7d974488a02921b1b2ba',1,'stm32f407xx_matlab.h']]], - ['fsmc_5feccr2_5fecc2_5fmsk_833',['FSMC_ECCR2_ECC2_Msk',['../group___peripheral___registers___bits___definition.html#ga263cd31cea7c03124b24b94bec2ba751',1,'stm32f407xx_matlab.h']]], - ['fsmc_5feccr2_5fecc2_5fpos_834',['FSMC_ECCR2_ECC2_Pos',['../group___peripheral___registers___bits___definition.html#ga29ff399335d0f733c9c1476a5231bd92',1,'stm32f407xx_matlab.h']]], - ['fsmc_5feccr3_5fecc3_835',['FSMC_ECCR3_ECC3',['../group___peripheral___registers___bits___definition.html#ga798b288a17d84edc99ff1f5f81cf70be',1,'stm32f407xx_matlab.h']]], - ['fsmc_5feccr3_5fecc3_5fmsk_836',['FSMC_ECCR3_ECC3_Msk',['../group___peripheral___registers___bits___definition.html#gaf8f7ec32f0cb28be8c241bf487fdc8c3',1,'stm32f407xx_matlab.h']]], - ['fsmc_5feccr3_5fecc3_5fpos_837',['FSMC_ECCR3_ECC3_Pos',['../group___peripheral___registers___bits___definition.html#gad671bdabc43e3a5cdebc69d006e7227f',1,'stm32f407xx_matlab.h']]], - ['fsmc_5firqn_838',['FSMC_IRQn',['../group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a70450df88125476d5771f2ff3f562536',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpatt2_5fatthiz2_839',['FSMC_PATT2_ATTHIZ2',['../group___peripheral___registers___bits___definition.html#gae2726cd505612675158551fd9eed763f',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpatt2_5fatthiz2_5f0_840',['FSMC_PATT2_ATTHIZ2_0',['../group___peripheral___registers___bits___definition.html#gae1ff9b8faa8372116ca931826d18a9c7',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpatt2_5fatthiz2_5f1_841',['FSMC_PATT2_ATTHIZ2_1',['../group___peripheral___registers___bits___definition.html#gaac4081b55783073164985488c9d4d6b8',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpatt2_5fatthiz2_5f2_842',['FSMC_PATT2_ATTHIZ2_2',['../group___peripheral___registers___bits___definition.html#gaa3cc10b4217452bae11c69ed9f6f1844',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpatt2_5fatthiz2_5f3_843',['FSMC_PATT2_ATTHIZ2_3',['../group___peripheral___registers___bits___definition.html#ga93e2929a1bcde578f374bbebaa9482d1',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpatt2_5fatthiz2_5f4_844',['FSMC_PATT2_ATTHIZ2_4',['../group___peripheral___registers___bits___definition.html#gac536419b5ef258fa3f9140387e2f134f',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpatt2_5fatthiz2_5f5_845',['FSMC_PATT2_ATTHIZ2_5',['../group___peripheral___registers___bits___definition.html#ga5deab3153671ff06832dd651372f9ca7',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpatt2_5fatthiz2_5f6_846',['FSMC_PATT2_ATTHIZ2_6',['../group___peripheral___registers___bits___definition.html#ga047723a357976aca5bdf6575327986d2',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpatt2_5fatthiz2_5f7_847',['FSMC_PATT2_ATTHIZ2_7',['../group___peripheral___registers___bits___definition.html#ga859a5af02e12a11e7548085e9e186547',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpatt2_5fatthiz2_5fmsk_848',['FSMC_PATT2_ATTHIZ2_Msk',['../group___peripheral___registers___bits___definition.html#ga68a00587d76421282a4c27b05ab794e4',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpatt2_5fatthiz2_5fpos_849',['FSMC_PATT2_ATTHIZ2_Pos',['../group___peripheral___registers___bits___definition.html#ga5a79c090eb6e9372f579f1912d266a51',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpatt2_5fatthold2_850',['FSMC_PATT2_ATTHOLD2',['../group___peripheral___registers___bits___definition.html#gad007c3c6fbef432a5e6bb08bd6e0b1ce',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpatt2_5fatthold2_5f0_851',['FSMC_PATT2_ATTHOLD2_0',['../group___peripheral___registers___bits___definition.html#ga5b5e19eb38592e84b9c0f3f57df51892',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpatt2_5fatthold2_5f1_852',['FSMC_PATT2_ATTHOLD2_1',['../group___peripheral___registers___bits___definition.html#ga13dface112bf1300689a4f00ba31abac',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpatt2_5fatthold2_5f2_853',['FSMC_PATT2_ATTHOLD2_2',['../group___peripheral___registers___bits___definition.html#gaea0e1b34ac27f20c85db0f96eaeff994',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpatt2_5fatthold2_5f3_854',['FSMC_PATT2_ATTHOLD2_3',['../group___peripheral___registers___bits___definition.html#ga1582860673c5e72f9441095d5af7b8ad',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpatt2_5fatthold2_5f4_855',['FSMC_PATT2_ATTHOLD2_4',['../group___peripheral___registers___bits___definition.html#gacdd679f3b80617291639cafcdd8f77d1',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpatt2_5fatthold2_5f5_856',['FSMC_PATT2_ATTHOLD2_5',['../group___peripheral___registers___bits___definition.html#ga34e89cd935ec26279bc9876d9dd07b07',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpatt2_5fatthold2_5f6_857',['FSMC_PATT2_ATTHOLD2_6',['../group___peripheral___registers___bits___definition.html#ga12c42d6d5746ef8d763d36b04f6e4644',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpatt2_5fatthold2_5f7_858',['FSMC_PATT2_ATTHOLD2_7',['../group___peripheral___registers___bits___definition.html#ga93558ba1372a3709316b4734160b3874',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpatt2_5fatthold2_5fmsk_859',['FSMC_PATT2_ATTHOLD2_Msk',['../group___peripheral___registers___bits___definition.html#ga836b8150e0ee69c3acc4e1330ad8c9f2',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpatt2_5fatthold2_5fpos_860',['FSMC_PATT2_ATTHOLD2_Pos',['../group___peripheral___registers___bits___definition.html#ga82a9f758e7aac1ee2529a904e5ae7e62',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpatt2_5fattset2_861',['FSMC_PATT2_ATTSET2',['../group___peripheral___registers___bits___definition.html#gaab6cd1418de73ee3b214be589912e45f',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpatt2_5fattset2_5f0_862',['FSMC_PATT2_ATTSET2_0',['../group___peripheral___registers___bits___definition.html#gaab4718770edfb1b9b96df7410a58f79b',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpatt2_5fattset2_5f1_863',['FSMC_PATT2_ATTSET2_1',['../group___peripheral___registers___bits___definition.html#ga4cde8c8360b22a3fb63615b4274653c9',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpatt2_5fattset2_5f2_864',['FSMC_PATT2_ATTSET2_2',['../group___peripheral___registers___bits___definition.html#gae80034b8760da9dd1faaf7e326b6002a',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpatt2_5fattset2_5f3_865',['FSMC_PATT2_ATTSET2_3',['../group___peripheral___registers___bits___definition.html#ga11924ff951b3e939d2d20807901a82bf',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpatt2_5fattset2_5f4_866',['FSMC_PATT2_ATTSET2_4',['../group___peripheral___registers___bits___definition.html#gad1b81efbb998d5e86685075396fd83b0',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpatt2_5fattset2_5f5_867',['FSMC_PATT2_ATTSET2_5',['../group___peripheral___registers___bits___definition.html#ga3e89896b03049ad636484b44c7ecd670',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpatt2_5fattset2_5f6_868',['FSMC_PATT2_ATTSET2_6',['../group___peripheral___registers___bits___definition.html#gac751391f5acb1f3229ca65a3424d316d',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpatt2_5fattset2_5f7_869',['FSMC_PATT2_ATTSET2_7',['../group___peripheral___registers___bits___definition.html#gabb0f3115642332e5aef5cfa1b6b719d8',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpatt2_5fattset2_5fmsk_870',['FSMC_PATT2_ATTSET2_Msk',['../group___peripheral___registers___bits___definition.html#gabc4ae266a174a451c7eff4c6e82a08d6',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpatt2_5fattset2_5fpos_871',['FSMC_PATT2_ATTSET2_Pos',['../group___peripheral___registers___bits___definition.html#gabc7a654ded670713a8926626faad19db',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpatt2_5fattwait2_872',['FSMC_PATT2_ATTWAIT2',['../group___peripheral___registers___bits___definition.html#ga6fda97184969b04e909ac97d31da48e6',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpatt2_5fattwait2_5f0_873',['FSMC_PATT2_ATTWAIT2_0',['../group___peripheral___registers___bits___definition.html#gaf43a2874230fbe9b87f9495a736b9363',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpatt2_5fattwait2_5f1_874',['FSMC_PATT2_ATTWAIT2_1',['../group___peripheral___registers___bits___definition.html#gaad30fbb45343ced8deb9bbc062dba46b',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpatt2_5fattwait2_5f2_875',['FSMC_PATT2_ATTWAIT2_2',['../group___peripheral___registers___bits___definition.html#gae78c7794f66cd2063464ab2e6ef2bd07',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpatt2_5fattwait2_5f3_876',['FSMC_PATT2_ATTWAIT2_3',['../group___peripheral___registers___bits___definition.html#ga82c2de9009c75560a342122937b25853',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpatt2_5fattwait2_5f4_877',['FSMC_PATT2_ATTWAIT2_4',['../group___peripheral___registers___bits___definition.html#gae80b6a2fc197435f6b50b4ba035fb5fe',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpatt2_5fattwait2_5f5_878',['FSMC_PATT2_ATTWAIT2_5',['../group___peripheral___registers___bits___definition.html#gac924773c5fcbee73186600247618d10b',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpatt2_5fattwait2_5f6_879',['FSMC_PATT2_ATTWAIT2_6',['../group___peripheral___registers___bits___definition.html#ga70b22c0b9a32e473f0eb56952ba58d95',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpatt2_5fattwait2_5f7_880',['FSMC_PATT2_ATTWAIT2_7',['../group___peripheral___registers___bits___definition.html#ga2ade8feb15ddcef159ccf3ff55fb0c24',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpatt2_5fattwait2_5fmsk_881',['FSMC_PATT2_ATTWAIT2_Msk',['../group___peripheral___registers___bits___definition.html#ga91b82eb626e2249b2365749e2ddd5b82',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpatt2_5fattwait2_5fpos_882',['FSMC_PATT2_ATTWAIT2_Pos',['../group___peripheral___registers___bits___definition.html#gae092c85efe222aa5d2788335544ab0f1',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpatt3_5fatthiz3_883',['FSMC_PATT3_ATTHIZ3',['../group___peripheral___registers___bits___definition.html#gaea9d34b131aa7db353eef060ca37788c',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpatt3_5fatthiz3_5f0_884',['FSMC_PATT3_ATTHIZ3_0',['../group___peripheral___registers___bits___definition.html#ga5bc6736af23f6f033568e0085cd19964',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpatt3_5fatthiz3_5f1_885',['FSMC_PATT3_ATTHIZ3_1',['../group___peripheral___registers___bits___definition.html#ga41270d0ae8670f39b886b49e47e8195b',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpatt3_5fatthiz3_5f2_886',['FSMC_PATT3_ATTHIZ3_2',['../group___peripheral___registers___bits___definition.html#ga988ec453492aafacf205895c5398caf2',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpatt3_5fatthiz3_5f3_887',['FSMC_PATT3_ATTHIZ3_3',['../group___peripheral___registers___bits___definition.html#ga48885375147c060687bbccc6a234ce39',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpatt3_5fatthiz3_5f4_888',['FSMC_PATT3_ATTHIZ3_4',['../group___peripheral___registers___bits___definition.html#ga5ea193881223470d7b6a6ca3e3474a84',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpatt3_5fatthiz3_5f5_889',['FSMC_PATT3_ATTHIZ3_5',['../group___peripheral___registers___bits___definition.html#ga7ab1f4cb68cfb8717d2b29e3a84987b1',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpatt3_5fatthiz3_5f6_890',['FSMC_PATT3_ATTHIZ3_6',['../group___peripheral___registers___bits___definition.html#ga44fd348b342ec248b821123f3310f475',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpatt3_5fatthiz3_5f7_891',['FSMC_PATT3_ATTHIZ3_7',['../group___peripheral___registers___bits___definition.html#ga0ff1a3acc9bbab229000d48845ea1863',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpatt3_5fatthiz3_5fmsk_892',['FSMC_PATT3_ATTHIZ3_Msk',['../group___peripheral___registers___bits___definition.html#gafbbd7b49755e0e7052d77f774d72ca18',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpatt3_5fatthiz3_5fpos_893',['FSMC_PATT3_ATTHIZ3_Pos',['../group___peripheral___registers___bits___definition.html#gaaae5fdcc70300b0e9c7b69d31c9173b5',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpatt3_5fatthold3_894',['FSMC_PATT3_ATTHOLD3',['../group___peripheral___registers___bits___definition.html#gab3a2e634d0f5e3c9716c0910e1efda60',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpatt3_5fatthold3_5f0_895',['FSMC_PATT3_ATTHOLD3_0',['../group___peripheral___registers___bits___definition.html#gad34a9f1b84d670c4132c56fa30ca26f0',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpatt3_5fatthold3_5f1_896',['FSMC_PATT3_ATTHOLD3_1',['../group___peripheral___registers___bits___definition.html#ga5b2ed392d654694fc330c6721bed5728',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpatt3_5fatthold3_5f2_897',['FSMC_PATT3_ATTHOLD3_2',['../group___peripheral___registers___bits___definition.html#ga679d3ea50788981dac810ec62bc372f0',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpatt3_5fatthold3_5f3_898',['FSMC_PATT3_ATTHOLD3_3',['../group___peripheral___registers___bits___definition.html#ga75d74cf52f238826e87d3a3c27b52acc',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpatt3_5fatthold3_5f4_899',['FSMC_PATT3_ATTHOLD3_4',['../group___peripheral___registers___bits___definition.html#gaa8d656d40279e1655a6682dcc2762e92',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpatt3_5fatthold3_5f5_900',['FSMC_PATT3_ATTHOLD3_5',['../group___peripheral___registers___bits___definition.html#gafee75f2fcf37e20e983732f258f85371',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpatt3_5fatthold3_5f6_901',['FSMC_PATT3_ATTHOLD3_6',['../group___peripheral___registers___bits___definition.html#ga777b93e1e3c802ede605644d3ff3bba7',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpatt3_5fatthold3_5f7_902',['FSMC_PATT3_ATTHOLD3_7',['../group___peripheral___registers___bits___definition.html#ga39acada8d54a7a14d3838d042397bd74',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpatt3_5fatthold3_5fmsk_903',['FSMC_PATT3_ATTHOLD3_Msk',['../group___peripheral___registers___bits___definition.html#ga9cd55c17fa5ff544f7d19482034dd6de',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpatt3_5fatthold3_5fpos_904',['FSMC_PATT3_ATTHOLD3_Pos',['../group___peripheral___registers___bits___definition.html#ga05923158d59d724b0beec495f7ea9fcf',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpatt3_5fattset3_905',['FSMC_PATT3_ATTSET3',['../group___peripheral___registers___bits___definition.html#gae0487c57e948411f16c3a35927e60dd5',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpatt3_5fattset3_5f0_906',['FSMC_PATT3_ATTSET3_0',['../group___peripheral___registers___bits___definition.html#ga0e68a5b1bb5996422eac084d586359d4',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpatt3_5fattset3_5f1_907',['FSMC_PATT3_ATTSET3_1',['../group___peripheral___registers___bits___definition.html#ga2d8bd09ad36ab8cae67f87cb930ea428',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpatt3_5fattset3_5f2_908',['FSMC_PATT3_ATTSET3_2',['../group___peripheral___registers___bits___definition.html#ga29b9389601899ce2731c612ad05d9a96',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpatt3_5fattset3_5f3_909',['FSMC_PATT3_ATTSET3_3',['../group___peripheral___registers___bits___definition.html#ga97893656a7b65ec5420382de0b264a11',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpatt3_5fattset3_5f4_910',['FSMC_PATT3_ATTSET3_4',['../group___peripheral___registers___bits___definition.html#ga9a6993a1cc304b9300bdc365c2827d43',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpatt3_5fattset3_5f5_911',['FSMC_PATT3_ATTSET3_5',['../group___peripheral___registers___bits___definition.html#ga8cf65f61ce823183c3866607cab6bd09',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpatt3_5fattset3_5f6_912',['FSMC_PATT3_ATTSET3_6',['../group___peripheral___registers___bits___definition.html#gab2d5a3dd16094a6279766692694aa16b',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpatt3_5fattset3_5f7_913',['FSMC_PATT3_ATTSET3_7',['../group___peripheral___registers___bits___definition.html#ga7668853b7956cdb13fd73ed10faf4526',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpatt3_5fattset3_5fmsk_914',['FSMC_PATT3_ATTSET3_Msk',['../group___peripheral___registers___bits___definition.html#ga7ea2296ea7aafbc8aadd589669dfb638',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpatt3_5fattset3_5fpos_915',['FSMC_PATT3_ATTSET3_Pos',['../group___peripheral___registers___bits___definition.html#ga5ec2d77c99acc018d13e3f95ef8072b4',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpatt3_5fattwait3_916',['FSMC_PATT3_ATTWAIT3',['../group___peripheral___registers___bits___definition.html#gad8aaf4c77a663cab07ac6c365a271599',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpatt3_5fattwait3_5f0_917',['FSMC_PATT3_ATTWAIT3_0',['../group___peripheral___registers___bits___definition.html#gac5c5500a07e7885de5c372c55f147836',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpatt3_5fattwait3_5f1_918',['FSMC_PATT3_ATTWAIT3_1',['../group___peripheral___registers___bits___definition.html#gaddddbd0a403b2aeefcfdb28a7da56bf0',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpatt3_5fattwait3_5f2_919',['FSMC_PATT3_ATTWAIT3_2',['../group___peripheral___registers___bits___definition.html#gac34cbe7e282e1074e6c4b9645e48db2f',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpatt3_5fattwait3_5f3_920',['FSMC_PATT3_ATTWAIT3_3',['../group___peripheral___registers___bits___definition.html#ga771f2a5acde98a9760eb8a1338f416a3',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpatt3_5fattwait3_5f4_921',['FSMC_PATT3_ATTWAIT3_4',['../group___peripheral___registers___bits___definition.html#ga1bcc944836a379b2b878d5129ff94ddb',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpatt3_5fattwait3_5f5_922',['FSMC_PATT3_ATTWAIT3_5',['../group___peripheral___registers___bits___definition.html#gacf722482193ca6a1bf90f17af567e019',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpatt3_5fattwait3_5f6_923',['FSMC_PATT3_ATTWAIT3_6',['../group___peripheral___registers___bits___definition.html#gac2cc3ce135f309f7574f0c3d1a0ffe88',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpatt3_5fattwait3_5f7_924',['FSMC_PATT3_ATTWAIT3_7',['../group___peripheral___registers___bits___definition.html#gaa66342cc1db5dcad99153b5a2f22140e',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpatt3_5fattwait3_5fmsk_925',['FSMC_PATT3_ATTWAIT3_Msk',['../group___peripheral___registers___bits___definition.html#ga93f4da8f79e8595a22f0089aa1a3085b',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpatt3_5fattwait3_5fpos_926',['FSMC_PATT3_ATTWAIT3_Pos',['../group___peripheral___registers___bits___definition.html#gac9a5135aee8bd8f89325962d2598aaae',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpatt4_5fatthiz4_927',['FSMC_PATT4_ATTHIZ4',['../group___peripheral___registers___bits___definition.html#ga35948e4e9e5ce9d674e9e70ca2aeafe3',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpatt4_5fatthiz4_5f0_928',['FSMC_PATT4_ATTHIZ4_0',['../group___peripheral___registers___bits___definition.html#ga5b746d7b655f6379af4dd4d5ba842492',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpatt4_5fatthiz4_5f1_929',['FSMC_PATT4_ATTHIZ4_1',['../group___peripheral___registers___bits___definition.html#gac2dd87929111fc0c888dd7c311f8eba3',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpatt4_5fatthiz4_5f2_930',['FSMC_PATT4_ATTHIZ4_2',['../group___peripheral___registers___bits___definition.html#ga353c0709e22a06998f05b908a597f525',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpatt4_5fatthiz4_5f3_931',['FSMC_PATT4_ATTHIZ4_3',['../group___peripheral___registers___bits___definition.html#gaa777a5d42ac1e36044d7b18ffdd61a21',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpatt4_5fatthiz4_5f4_932',['FSMC_PATT4_ATTHIZ4_4',['../group___peripheral___registers___bits___definition.html#ga65c1778d08bfe2a40961f6acf023b9d4',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpatt4_5fatthiz4_5f5_933',['FSMC_PATT4_ATTHIZ4_5',['../group___peripheral___registers___bits___definition.html#gaadb7001986c9a4c28052b46657ad7a7e',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpatt4_5fatthiz4_5f6_934',['FSMC_PATT4_ATTHIZ4_6',['../group___peripheral___registers___bits___definition.html#gaa11a8d896354bd1c6645ac096db8e065',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpatt4_5fatthiz4_5f7_935',['FSMC_PATT4_ATTHIZ4_7',['../group___peripheral___registers___bits___definition.html#ga1a054f48705ec3fef0686c576f414f29',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpatt4_5fatthiz4_5fmsk_936',['FSMC_PATT4_ATTHIZ4_Msk',['../group___peripheral___registers___bits___definition.html#gac10548dc39d989f970e3397287096126',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpatt4_5fatthiz4_5fpos_937',['FSMC_PATT4_ATTHIZ4_Pos',['../group___peripheral___registers___bits___definition.html#gaa7e76eb10b9d92b8d3d88d4d026679fb',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpatt4_5fatthold4_938',['FSMC_PATT4_ATTHOLD4',['../group___peripheral___registers___bits___definition.html#ga0bf06c395d55c775b4fbe202bac517a6',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpatt4_5fatthold4_5f0_939',['FSMC_PATT4_ATTHOLD4_0',['../group___peripheral___registers___bits___definition.html#gad5c97b102bd1f2b61dcfb793c0d61d66',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpatt4_5fatthold4_5f1_940',['FSMC_PATT4_ATTHOLD4_1',['../group___peripheral___registers___bits___definition.html#ga738c8d87ebcdff68725a54ff7f39675d',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpatt4_5fatthold4_5f2_941',['FSMC_PATT4_ATTHOLD4_2',['../group___peripheral___registers___bits___definition.html#ga6d9610198e4710ca394e3aeb32aa229f',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpatt4_5fatthold4_5f3_942',['FSMC_PATT4_ATTHOLD4_3',['../group___peripheral___registers___bits___definition.html#gadd14059e9f658f37b3a1f18786395717',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpatt4_5fatthold4_5f4_943',['FSMC_PATT4_ATTHOLD4_4',['../group___peripheral___registers___bits___definition.html#ga7a39fa40e2d4990097e31b47ad85283a',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpatt4_5fatthold4_5f5_944',['FSMC_PATT4_ATTHOLD4_5',['../group___peripheral___registers___bits___definition.html#ga239e412f20305d58416f10a79e253a87',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpatt4_5fatthold4_5f6_945',['FSMC_PATT4_ATTHOLD4_6',['../group___peripheral___registers___bits___definition.html#gaff1aac62acdf71077ee4a9e8e9e6d2d6',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpatt4_5fatthold4_5f7_946',['FSMC_PATT4_ATTHOLD4_7',['../group___peripheral___registers___bits___definition.html#ga836fd2ad42b0c9f6d0eb651589d04123',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpatt4_5fatthold4_5fmsk_947',['FSMC_PATT4_ATTHOLD4_Msk',['../group___peripheral___registers___bits___definition.html#ga0108d421a275b527d8cb978b6d9685ce',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpatt4_5fatthold4_5fpos_948',['FSMC_PATT4_ATTHOLD4_Pos',['../group___peripheral___registers___bits___definition.html#ga443220812626d4a02edc701390f33a3d',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpatt4_5fattset4_949',['FSMC_PATT4_ATTSET4',['../group___peripheral___registers___bits___definition.html#ga7f4d8fb0d47b4a3fddf55c2532dd3159',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpatt4_5fattset4_5f0_950',['FSMC_PATT4_ATTSET4_0',['../group___peripheral___registers___bits___definition.html#ga1dac8bcf03610eb2d43b557f4d81532a',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpatt4_5fattset4_5f1_951',['FSMC_PATT4_ATTSET4_1',['../group___peripheral___registers___bits___definition.html#gaac2576c2a95871cbf9babd0778372571',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpatt4_5fattset4_5f2_952',['FSMC_PATT4_ATTSET4_2',['../group___peripheral___registers___bits___definition.html#ga88e760bbe9714ac07f381de3af0abc36',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpatt4_5fattset4_5f3_953',['FSMC_PATT4_ATTSET4_3',['../group___peripheral___registers___bits___definition.html#ga4b472fd4848733a921998f0305b5bc02',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpatt4_5fattset4_5f4_954',['FSMC_PATT4_ATTSET4_4',['../group___peripheral___registers___bits___definition.html#gae7d0c69190a0d78fedc875c3dc6b9037',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpatt4_5fattset4_5f5_955',['FSMC_PATT4_ATTSET4_5',['../group___peripheral___registers___bits___definition.html#ga168c6f16be9721a5ea0e31230bd1939b',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpatt4_5fattset4_5f6_956',['FSMC_PATT4_ATTSET4_6',['../group___peripheral___registers___bits___definition.html#ga72fe744c036b2acc4fff8733ac48b0ae',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpatt4_5fattset4_5f7_957',['FSMC_PATT4_ATTSET4_7',['../group___peripheral___registers___bits___definition.html#ga4529b17de7cb4eeeff25496620978adc',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpatt4_5fattset4_5fmsk_958',['FSMC_PATT4_ATTSET4_Msk',['../group___peripheral___registers___bits___definition.html#gac8ee09881a3a83d040c49e7ec91e16f8',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpatt4_5fattset4_5fpos_959',['FSMC_PATT4_ATTSET4_Pos',['../group___peripheral___registers___bits___definition.html#ga02c498b211356b2ff396a8f793ae1f88',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpatt4_5fattwait4_960',['FSMC_PATT4_ATTWAIT4',['../group___peripheral___registers___bits___definition.html#ga01edeaedc31867997a188fa89cab2ec0',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpatt4_5fattwait4_5f0_961',['FSMC_PATT4_ATTWAIT4_0',['../group___peripheral___registers___bits___definition.html#ga5da7db34cd23f3126f224a0b845a66a8',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpatt4_5fattwait4_5f1_962',['FSMC_PATT4_ATTWAIT4_1',['../group___peripheral___registers___bits___definition.html#ga14644aa2ed55afe2094015d74843a994',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpatt4_5fattwait4_5f2_963',['FSMC_PATT4_ATTWAIT4_2',['../group___peripheral___registers___bits___definition.html#gaf1023d5ae8fab70e7fdfbaff4ed46657',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpatt4_5fattwait4_5f3_964',['FSMC_PATT4_ATTWAIT4_3',['../group___peripheral___registers___bits___definition.html#ga906c9684ffcd8f0f9222cbfd0e21885a',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpatt4_5fattwait4_5f4_965',['FSMC_PATT4_ATTWAIT4_4',['../group___peripheral___registers___bits___definition.html#gae8d341a7448f645a2f849e591515f020',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpatt4_5fattwait4_5f5_966',['FSMC_PATT4_ATTWAIT4_5',['../group___peripheral___registers___bits___definition.html#gaf278272c5fdaa8fa7c84e1c095690632',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpatt4_5fattwait4_5f6_967',['FSMC_PATT4_ATTWAIT4_6',['../group___peripheral___registers___bits___definition.html#ga3126347e126717a761af0b6e44b9d72d',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpatt4_5fattwait4_5f7_968',['FSMC_PATT4_ATTWAIT4_7',['../group___peripheral___registers___bits___definition.html#ga34afb78710ca450ac7065f0bc263075c',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpatt4_5fattwait4_5fmsk_969',['FSMC_PATT4_ATTWAIT4_Msk',['../group___peripheral___registers___bits___definition.html#gab9b0b756ec9357585c52037f88e87c00',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpatt4_5fattwait4_5fpos_970',['FSMC_PATT4_ATTWAIT4_Pos',['../group___peripheral___registers___bits___definition.html#ga11a97fde0b98868526b7ea722e3185d3',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpcr2_5feccen_971',['FSMC_PCR2_ECCEN',['../group___peripheral___registers___bits___definition.html#gafa528d578aec8bc0f77a2550d4e48438',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpcr2_5feccen_5fmsk_972',['FSMC_PCR2_ECCEN_Msk',['../group___peripheral___registers___bits___definition.html#ga050ab1ee23d46eb34ed79f22bde35200',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpcr2_5feccen_5fpos_973',['FSMC_PCR2_ECCEN_Pos',['../group___peripheral___registers___bits___definition.html#ga7ca16b5cf800c2fb594a8a06fa0ea883',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpcr2_5feccps_974',['FSMC_PCR2_ECCPS',['../group___peripheral___registers___bits___definition.html#gaf2adbc7b4149193452b69bc55a968cd1',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpcr2_5feccps_5f0_975',['FSMC_PCR2_ECCPS_0',['../group___peripheral___registers___bits___definition.html#gae0e06e76b0dd7cc1f6b765b4c3ecfacb',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpcr2_5feccps_5f1_976',['FSMC_PCR2_ECCPS_1',['../group___peripheral___registers___bits___definition.html#ga8b947299d05921085b531f12db860f41',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpcr2_5feccps_5f2_977',['FSMC_PCR2_ECCPS_2',['../group___peripheral___registers___bits___definition.html#ga199db72eae8707aba0b22ff18bd8bcd0',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpcr2_5feccps_5fmsk_978',['FSMC_PCR2_ECCPS_Msk',['../group___peripheral___registers___bits___definition.html#ga481ae62d08b68ae47e76399a3db6f343',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpcr2_5feccps_5fpos_979',['FSMC_PCR2_ECCPS_Pos',['../group___peripheral___registers___bits___definition.html#ga252ebef1000455631c4839f64fe943c2',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpcr2_5fpbken_980',['FSMC_PCR2_PBKEN',['../group___peripheral___registers___bits___definition.html#ga2a2bfd8de14f8c726439ba8f494b38a1',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpcr2_5fpbken_5fmsk_981',['FSMC_PCR2_PBKEN_Msk',['../group___peripheral___registers___bits___definition.html#ga23ca7d9404f38c74f54c617779417247',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpcr2_5fpbken_5fpos_982',['FSMC_PCR2_PBKEN_Pos',['../group___peripheral___registers___bits___definition.html#gaa44a48baf82f718ea68a8f49f41a7197',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpcr2_5fptyp_983',['FSMC_PCR2_PTYP',['../group___peripheral___registers___bits___definition.html#ga175ab8f61bbc0bb5692fb62691db1ce3',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpcr2_5fptyp_5fmsk_984',['FSMC_PCR2_PTYP_Msk',['../group___peripheral___registers___bits___definition.html#gafcf702c34178ab9c91c1e5e31c5b6b8f',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpcr2_5fptyp_5fpos_985',['FSMC_PCR2_PTYP_Pos',['../group___peripheral___registers___bits___definition.html#ga56ca1be84472397c7e7c0e72e45f69c9',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpcr2_5fpwaiten_986',['FSMC_PCR2_PWAITEN',['../group___peripheral___registers___bits___definition.html#ga26f3ae80c9bbede6929c20004804476d',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpcr2_5fpwaiten_5fmsk_987',['FSMC_PCR2_PWAITEN_Msk',['../group___peripheral___registers___bits___definition.html#ga427ff4cc50d76345ee3d8885f7f09863',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpcr2_5fpwaiten_5fpos_988',['FSMC_PCR2_PWAITEN_Pos',['../group___peripheral___registers___bits___definition.html#gaaa09c72741deafe6d443fd0f25299480',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpcr2_5fpwid_989',['FSMC_PCR2_PWID',['../group___peripheral___registers___bits___definition.html#ga656155275dc1c2f690687d07717e017a',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpcr2_5fpwid_5f0_990',['FSMC_PCR2_PWID_0',['../group___peripheral___registers___bits___definition.html#gae36f67be67a473c318fa937246c6de17',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpcr2_5fpwid_5f1_991',['FSMC_PCR2_PWID_1',['../group___peripheral___registers___bits___definition.html#ga6180d3899a37f7e518b1e4b8bf935baa',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpcr2_5fpwid_5fmsk_992',['FSMC_PCR2_PWID_Msk',['../group___peripheral___registers___bits___definition.html#gaeaeb0bbbb281a4cc378e1ac5c0af401b',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpcr2_5fpwid_5fpos_993',['FSMC_PCR2_PWID_Pos',['../group___peripheral___registers___bits___definition.html#ga786bd3b30640e57e85ccd8faeb812c73',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpcr2_5ftar_994',['FSMC_PCR2_TAR',['../group___peripheral___registers___bits___definition.html#gaa6513b62e23afdbadc4b25697378a0f2',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpcr2_5ftar_5f0_995',['FSMC_PCR2_TAR_0',['../group___peripheral___registers___bits___definition.html#gacd7e456c24f5978e8cb1078c633f0d23',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpcr2_5ftar_5f1_996',['FSMC_PCR2_TAR_1',['../group___peripheral___registers___bits___definition.html#ga8f0b2191750ab21af10f009e1a97ca13',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpcr2_5ftar_5f2_997',['FSMC_PCR2_TAR_2',['../group___peripheral___registers___bits___definition.html#ga3de27b9eb559156b7ed87407206b7a17',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpcr2_5ftar_5f3_998',['FSMC_PCR2_TAR_3',['../group___peripheral___registers___bits___definition.html#ga1c70f852bb8809e8ea4800a7dd616266',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpcr2_5ftar_5fmsk_999',['FSMC_PCR2_TAR_Msk',['../group___peripheral___registers___bits___definition.html#gabb912af6630ca178d706e72bfeafe4e5',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpcr2_5ftar_5fpos_1000',['FSMC_PCR2_TAR_Pos',['../group___peripheral___registers___bits___definition.html#ga0c4fe782dd038165f42f57ebac4721bf',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpcr2_5ftclr_1001',['FSMC_PCR2_TCLR',['../group___peripheral___registers___bits___definition.html#gaa4f2c6c5ed8cd459a0822c35ea9e6800',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpcr2_5ftclr_5f0_1002',['FSMC_PCR2_TCLR_0',['../group___peripheral___registers___bits___definition.html#ga1edc7eec1b5a76a851175e5a7caa6c5c',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpcr2_5ftclr_5f1_1003',['FSMC_PCR2_TCLR_1',['../group___peripheral___registers___bits___definition.html#gaf8baae9949bd0f294a698721da24808f',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpcr2_5ftclr_5f2_1004',['FSMC_PCR2_TCLR_2',['../group___peripheral___registers___bits___definition.html#ga01ba36d067efffcfe5ecea3af1411675',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpcr2_5ftclr_5f3_1005',['FSMC_PCR2_TCLR_3',['../group___peripheral___registers___bits___definition.html#ga4999b81ed8783cca5f3b25500183ff9a',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpcr2_5ftclr_5fmsk_1006',['FSMC_PCR2_TCLR_Msk',['../group___peripheral___registers___bits___definition.html#ga0f526b241c14b7292561799c4e824e76',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpcr2_5ftclr_5fpos_1007',['FSMC_PCR2_TCLR_Pos',['../group___peripheral___registers___bits___definition.html#ga6c24b437e7873367aa3db5fe3f9526e5',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpcr3_5feccen_1008',['FSMC_PCR3_ECCEN',['../group___peripheral___registers___bits___definition.html#ga723c4c8c3b97cd1ce18c3b5c888e5b4e',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpcr3_5feccen_5fmsk_1009',['FSMC_PCR3_ECCEN_Msk',['../group___peripheral___registers___bits___definition.html#ga62b7f1f808fa00fda792439b9c0f10df',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpcr3_5feccen_5fpos_1010',['FSMC_PCR3_ECCEN_Pos',['../group___peripheral___registers___bits___definition.html#gaf427fbfd20e6142aa46d625037c67fbe',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpcr3_5feccps_1011',['FSMC_PCR3_ECCPS',['../group___peripheral___registers___bits___definition.html#gaf8d92853ca6f97f72682c2f53f686998',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpcr3_5feccps_5f0_1012',['FSMC_PCR3_ECCPS_0',['../group___peripheral___registers___bits___definition.html#ga506daa911151e1b9de3ed2b5030d1a5a',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpcr3_5feccps_5f1_1013',['FSMC_PCR3_ECCPS_1',['../group___peripheral___registers___bits___definition.html#ga6403c557bd93b5297fa7fbbf8dc49cc9',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpcr3_5feccps_5f2_1014',['FSMC_PCR3_ECCPS_2',['../group___peripheral___registers___bits___definition.html#gaf041e921fb9af07e9c709d79bbfaec89',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpcr3_5feccps_5fmsk_1015',['FSMC_PCR3_ECCPS_Msk',['../group___peripheral___registers___bits___definition.html#gae5c4fa241bbfe5cce0debcb6ad2052ce',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpcr3_5feccps_5fpos_1016',['FSMC_PCR3_ECCPS_Pos',['../group___peripheral___registers___bits___definition.html#ga102ae2695e494e32ba3a88386da61aaf',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpcr3_5fpbken_1017',['FSMC_PCR3_PBKEN',['../group___peripheral___registers___bits___definition.html#gaac1334587ebb2f313078aab2c2f76cf7',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpcr3_5fpbken_5fmsk_1018',['FSMC_PCR3_PBKEN_Msk',['../group___peripheral___registers___bits___definition.html#gad82453ed7e868ba250086608f62fc27c',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpcr3_5fpbken_5fpos_1019',['FSMC_PCR3_PBKEN_Pos',['../group___peripheral___registers___bits___definition.html#ga9ca0936c38ad7fe990f148f58bb1adff',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpcr3_5fptyp_1020',['FSMC_PCR3_PTYP',['../group___peripheral___registers___bits___definition.html#gade562589d0572ba223d2f6df265fe5b8',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpcr3_5fptyp_5fmsk_1021',['FSMC_PCR3_PTYP_Msk',['../group___peripheral___registers___bits___definition.html#ga698eaa08d2ec1dedfceb558efe404a83',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpcr3_5fptyp_5fpos_1022',['FSMC_PCR3_PTYP_Pos',['../group___peripheral___registers___bits___definition.html#ga63ea560efa8bf6aabab0f0e552844ca6',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpcr3_5fpwaiten_1023',['FSMC_PCR3_PWAITEN',['../group___peripheral___registers___bits___definition.html#gaae3f15324eb8692ddf3f294f358b1d8c',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpcr3_5fpwaiten_5fmsk_1024',['FSMC_PCR3_PWAITEN_Msk',['../group___peripheral___registers___bits___definition.html#ga2a95cabc9c10687663e8d26706a5a012',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpcr3_5fpwaiten_5fpos_1025',['FSMC_PCR3_PWAITEN_Pos',['../group___peripheral___registers___bits___definition.html#ga349eaf51ed38a2cde231d53a0701c961',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpcr3_5fpwid_1026',['FSMC_PCR3_PWID',['../group___peripheral___registers___bits___definition.html#gac6f9b4e4449f105aa9bd3630f0466b9f',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpcr3_5fpwid_5f0_1027',['FSMC_PCR3_PWID_0',['../group___peripheral___registers___bits___definition.html#gae07191f4d5e3c3ec38b271b30cd1ee07',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpcr3_5fpwid_5f1_1028',['FSMC_PCR3_PWID_1',['../group___peripheral___registers___bits___definition.html#gaa8819a742324c0523f3dc6b8959bcdd5',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpcr3_5fpwid_5fmsk_1029',['FSMC_PCR3_PWID_Msk',['../group___peripheral___registers___bits___definition.html#ga292dbafb10a606fcee46e2ed5a6465fc',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpcr3_5fpwid_5fpos_1030',['FSMC_PCR3_PWID_Pos',['../group___peripheral___registers___bits___definition.html#ga1002927e92f1e32f4430eee6387493c5',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpcr3_5ftar_1031',['FSMC_PCR3_TAR',['../group___peripheral___registers___bits___definition.html#ga199c4b0e690f0da0de46e372183da642',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpcr3_5ftar_5f0_1032',['FSMC_PCR3_TAR_0',['../group___peripheral___registers___bits___definition.html#gada0f17bcc683a5a6249348a63004e225',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpcr3_5ftar_5f1_1033',['FSMC_PCR3_TAR_1',['../group___peripheral___registers___bits___definition.html#gad4afb373f6f1cb1bedd653d8ea1dca78',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpcr3_5ftar_5f2_1034',['FSMC_PCR3_TAR_2',['../group___peripheral___registers___bits___definition.html#ga597698c6059f70f61310456e83353738',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpcr3_5ftar_5f3_1035',['FSMC_PCR3_TAR_3',['../group___peripheral___registers___bits___definition.html#ga4bd7aaf7ffcad9f4477ac4f2927a0912',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpcr3_5ftar_5fmsk_1036',['FSMC_PCR3_TAR_Msk',['../group___peripheral___registers___bits___definition.html#gaba49396ea8498e090556ab597f1a4964',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpcr3_5ftar_5fpos_1037',['FSMC_PCR3_TAR_Pos',['../group___peripheral___registers___bits___definition.html#gaa2a4166c7fb1ca933148a90ded54588c',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpcr3_5ftclr_1038',['FSMC_PCR3_TCLR',['../group___peripheral___registers___bits___definition.html#ga478e4371d8baf2a0b2675b3113edb071',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpcr3_5ftclr_5f0_1039',['FSMC_PCR3_TCLR_0',['../group___peripheral___registers___bits___definition.html#gadedb0d10b5b53656dc152b9264faffbd',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpcr3_5ftclr_5f1_1040',['FSMC_PCR3_TCLR_1',['../group___peripheral___registers___bits___definition.html#gab5536285f03b1732aed999d20c0e25aa',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpcr3_5ftclr_5f2_1041',['FSMC_PCR3_TCLR_2',['../group___peripheral___registers___bits___definition.html#gae7d40ba9c0f0da58948ee2cc546b634c',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpcr3_5ftclr_5f3_1042',['FSMC_PCR3_TCLR_3',['../group___peripheral___registers___bits___definition.html#ga63f96a640afa85d7521b05458f590a19',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpcr3_5ftclr_5fmsk_1043',['FSMC_PCR3_TCLR_Msk',['../group___peripheral___registers___bits___definition.html#gabf9f398e720fdb04a1c5cdecc91cd857',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpcr3_5ftclr_5fpos_1044',['FSMC_PCR3_TCLR_Pos',['../group___peripheral___registers___bits___definition.html#ga7d8b78bf2fb85e57fcd42e1dbbd7d0cb',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpcr4_5feccen_1045',['FSMC_PCR4_ECCEN',['../group___peripheral___registers___bits___definition.html#ga646509f8bebb0d662c730ed4cabe741f',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpcr4_5feccen_5fmsk_1046',['FSMC_PCR4_ECCEN_Msk',['../group___peripheral___registers___bits___definition.html#ga6bee93c8682a87840c8b437c174eb13b',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpcr4_5feccen_5fpos_1047',['FSMC_PCR4_ECCEN_Pos',['../group___peripheral___registers___bits___definition.html#ga424cf5e2f1981675d26adf2196f885fb',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpcr4_5feccps_1048',['FSMC_PCR4_ECCPS',['../group___peripheral___registers___bits___definition.html#ga2308baba97f307b8beb6239702471038',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpcr4_5feccps_5f0_1049',['FSMC_PCR4_ECCPS_0',['../group___peripheral___registers___bits___definition.html#ga76514698225c0734c1e9be46b6dbd298',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpcr4_5feccps_5f1_1050',['FSMC_PCR4_ECCPS_1',['../group___peripheral___registers___bits___definition.html#ga1c43076003bbf01f95765125e19ab94d',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpcr4_5feccps_5f2_1051',['FSMC_PCR4_ECCPS_2',['../group___peripheral___registers___bits___definition.html#gac4ba96304e6618d4eb7672cdc3bd8f01',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpcr4_5feccps_5fmsk_1052',['FSMC_PCR4_ECCPS_Msk',['../group___peripheral___registers___bits___definition.html#ga07b5adc339bceccfa581082c73978949',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpcr4_5feccps_5fpos_1053',['FSMC_PCR4_ECCPS_Pos',['../group___peripheral___registers___bits___definition.html#ga2d07f92979ed4e7985b86118ccf71d9d',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpcr4_5fpbken_1054',['FSMC_PCR4_PBKEN',['../group___peripheral___registers___bits___definition.html#ga2f4a72bae5da27f8da23c13a54fe9622',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpcr4_5fpbken_5fmsk_1055',['FSMC_PCR4_PBKEN_Msk',['../group___peripheral___registers___bits___definition.html#ga36baaaa99b92a8eb95f34e111e7b1129',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpcr4_5fpbken_5fpos_1056',['FSMC_PCR4_PBKEN_Pos',['../group___peripheral___registers___bits___definition.html#ga33cf4873210ab762fd32b654eb055e4a',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpcr4_5fptyp_1057',['FSMC_PCR4_PTYP',['../group___peripheral___registers___bits___definition.html#gabe2d6f4e9bdef35436d521ebbdca5e40',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpcr4_5fptyp_5fmsk_1058',['FSMC_PCR4_PTYP_Msk',['../group___peripheral___registers___bits___definition.html#gad3a1ef73cc660cb04c99fc409bfc75b7',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpcr4_5fptyp_5fpos_1059',['FSMC_PCR4_PTYP_Pos',['../group___peripheral___registers___bits___definition.html#ga02a9e81721d3a6940da19547e32f5542',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpcr4_5fpwaiten_1060',['FSMC_PCR4_PWAITEN',['../group___peripheral___registers___bits___definition.html#gab07ce7c785eb296a615b2c50415de21b',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpcr4_5fpwaiten_5fmsk_1061',['FSMC_PCR4_PWAITEN_Msk',['../group___peripheral___registers___bits___definition.html#ga8766498d3b50a9c490695d777713d492',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpcr4_5fpwaiten_5fpos_1062',['FSMC_PCR4_PWAITEN_Pos',['../group___peripheral___registers___bits___definition.html#gaaf0bbe752661c9c0cad5f84f067d4714',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpcr4_5fpwid_1063',['FSMC_PCR4_PWID',['../group___peripheral___registers___bits___definition.html#ga9486b2b7346570ecc5715f1d551c168a',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpcr4_5fpwid_5f0_1064',['FSMC_PCR4_PWID_0',['../group___peripheral___registers___bits___definition.html#ga0995cb320e6293ea435df275ce67359f',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpcr4_5fpwid_5f1_1065',['FSMC_PCR4_PWID_1',['../group___peripheral___registers___bits___definition.html#ga8b6be32b3844a299a2c92089e81e27e9',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpcr4_5fpwid_5fmsk_1066',['FSMC_PCR4_PWID_Msk',['../group___peripheral___registers___bits___definition.html#ga487f41300b79f8833d468b64195315f9',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpcr4_5fpwid_5fpos_1067',['FSMC_PCR4_PWID_Pos',['../group___peripheral___registers___bits___definition.html#gabea06d1f6a4648fefdc3939c115d6459',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpcr4_5ftar_1068',['FSMC_PCR4_TAR',['../group___peripheral___registers___bits___definition.html#ga0c583f305906f19b15ce3dc177fa21bd',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpcr4_5ftar_5f0_1069',['FSMC_PCR4_TAR_0',['../group___peripheral___registers___bits___definition.html#ga62fe4ede4c658b788596e8ea6f325c9f',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpcr4_5ftar_5f1_1070',['FSMC_PCR4_TAR_1',['../group___peripheral___registers___bits___definition.html#ga2a9958cbf815ac97c3500a46aaf573f5',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpcr4_5ftar_5f2_1071',['FSMC_PCR4_TAR_2',['../group___peripheral___registers___bits___definition.html#ga669e16ecd48c92f65bd66f2da63fe53f',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpcr4_5ftar_5f3_1072',['FSMC_PCR4_TAR_3',['../group___peripheral___registers___bits___definition.html#gad298ef64d36721696517ed0d4ac12d32',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpcr4_5ftar_5fmsk_1073',['FSMC_PCR4_TAR_Msk',['../group___peripheral___registers___bits___definition.html#ga77f6431c476681f6a4e72f807eba2e41',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpcr4_5ftar_5fpos_1074',['FSMC_PCR4_TAR_Pos',['../group___peripheral___registers___bits___definition.html#gaf67899acb4972b2feffc057c69460dc2',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpcr4_5ftclr_1075',['FSMC_PCR4_TCLR',['../group___peripheral___registers___bits___definition.html#ga7c7164974019263cacbc7dda2fc14126',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpcr4_5ftclr_5f0_1076',['FSMC_PCR4_TCLR_0',['../group___peripheral___registers___bits___definition.html#ga0dd78ad0c755190a69b37ebac75a11dd',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpcr4_5ftclr_5f1_1077',['FSMC_PCR4_TCLR_1',['../group___peripheral___registers___bits___definition.html#gaf0ea2e2287999d3c7d6583aab492514d',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpcr4_5ftclr_5f2_1078',['FSMC_PCR4_TCLR_2',['../group___peripheral___registers___bits___definition.html#ga34dd56ee892fc187e105e4d820ce3b9a',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpcr4_5ftclr_5f3_1079',['FSMC_PCR4_TCLR_3',['../group___peripheral___registers___bits___definition.html#ga0eb8dc60a469cfa96b3b3b7fad25ac92',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpcr4_5ftclr_5fmsk_1080',['FSMC_PCR4_TCLR_Msk',['../group___peripheral___registers___bits___definition.html#gae9971f1f3806a65aee5a5993f687c582',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpcr4_5ftclr_5fpos_1081',['FSMC_PCR4_TCLR_Pos',['../group___peripheral___registers___bits___definition.html#ga2db09770ae63805a9a06c0382b66c640',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpio4_5fiohiz4_1082',['FSMC_PIO4_IOHIZ4',['../group___peripheral___registers___bits___definition.html#ga4cce93379430df64fd697ad772bc477d',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpio4_5fiohiz4_5f0_1083',['FSMC_PIO4_IOHIZ4_0',['../group___peripheral___registers___bits___definition.html#gaaf3b5c59e3eb4e259ddb722b1e536e5c',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpio4_5fiohiz4_5f1_1084',['FSMC_PIO4_IOHIZ4_1',['../group___peripheral___registers___bits___definition.html#ga3e8c66264d4ec7b69de613cb528cfee2',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpio4_5fiohiz4_5f2_1085',['FSMC_PIO4_IOHIZ4_2',['../group___peripheral___registers___bits___definition.html#gab943b8acd274a8892e691ffab36a6a21',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpio4_5fiohiz4_5f3_1086',['FSMC_PIO4_IOHIZ4_3',['../group___peripheral___registers___bits___definition.html#ga4184c40fd57a850605ac12c73553b6ba',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpio4_5fiohiz4_5f4_1087',['FSMC_PIO4_IOHIZ4_4',['../group___peripheral___registers___bits___definition.html#ga9f966bdf26f7fa0f52076438219df7ee',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpio4_5fiohiz4_5f5_1088',['FSMC_PIO4_IOHIZ4_5',['../group___peripheral___registers___bits___definition.html#ga9ba68883e73a331543a2990a76d1e91a',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpio4_5fiohiz4_5f6_1089',['FSMC_PIO4_IOHIZ4_6',['../group___peripheral___registers___bits___definition.html#ga8b2c084a1dfbf7fb7bd922faa48bad8a',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpio4_5fiohiz4_5f7_1090',['FSMC_PIO4_IOHIZ4_7',['../group___peripheral___registers___bits___definition.html#gabc8aef29e6eaecd3ff2c13bae143b8b4',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpio4_5fiohiz4_5fmsk_1091',['FSMC_PIO4_IOHIZ4_Msk',['../group___peripheral___registers___bits___definition.html#ga0b36d517941428d62268b10e8058abf4',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpio4_5fiohiz4_5fpos_1092',['FSMC_PIO4_IOHIZ4_Pos',['../group___peripheral___registers___bits___definition.html#gaeaac653ebed9641460a4275d30047630',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpio4_5fiohold4_1093',['FSMC_PIO4_IOHOLD4',['../group___peripheral___registers___bits___definition.html#gab55064df0d9fab8a072da6baa7b85878',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpio4_5fiohold4_5f0_1094',['FSMC_PIO4_IOHOLD4_0',['../group___peripheral___registers___bits___definition.html#gadc1a288b385fcf83bfa95da479d387a4',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpio4_5fiohold4_5f1_1095',['FSMC_PIO4_IOHOLD4_1',['../group___peripheral___registers___bits___definition.html#ga402d7221ee27ce71d1b8bb18539d8307',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpio4_5fiohold4_5f2_1096',['FSMC_PIO4_IOHOLD4_2',['../group___peripheral___registers___bits___definition.html#ga274c5b835ec95c97c4f1c6ebbf72a096',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpio4_5fiohold4_5f3_1097',['FSMC_PIO4_IOHOLD4_3',['../group___peripheral___registers___bits___definition.html#ga519b9b4ae5b136769278eb98eb10c3a6',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpio4_5fiohold4_5f4_1098',['FSMC_PIO4_IOHOLD4_4',['../group___peripheral___registers___bits___definition.html#gab2d013be2823d9ea9b81f8f76331c11d',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpio4_5fiohold4_5f5_1099',['FSMC_PIO4_IOHOLD4_5',['../group___peripheral___registers___bits___definition.html#ga5a14c965f1ff993e0976aaefe638e2f6',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpio4_5fiohold4_5f6_1100',['FSMC_PIO4_IOHOLD4_6',['../group___peripheral___registers___bits___definition.html#ga49411f21445032ad8eaca19e89d204bc',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpio4_5fiohold4_5f7_1101',['FSMC_PIO4_IOHOLD4_7',['../group___peripheral___registers___bits___definition.html#ga323dcc3be986d57d14b794cca0038953',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpio4_5fiohold4_5fmsk_1102',['FSMC_PIO4_IOHOLD4_Msk',['../group___peripheral___registers___bits___definition.html#ga6cfbf79cf550a6d25af660a9b78ae382',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpio4_5fiohold4_5fpos_1103',['FSMC_PIO4_IOHOLD4_Pos',['../group___peripheral___registers___bits___definition.html#ga162d7f97cc7753670f748753357fafd2',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpio4_5fioset4_1104',['FSMC_PIO4_IOSET4',['../group___peripheral___registers___bits___definition.html#gaf14b77f09f496a1325b5384eef54dd4a',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpio4_5fioset4_5f0_1105',['FSMC_PIO4_IOSET4_0',['../group___peripheral___registers___bits___definition.html#ga29c07a816f3065ae0c9287b6e3e0e967',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpio4_5fioset4_5f1_1106',['FSMC_PIO4_IOSET4_1',['../group___peripheral___registers___bits___definition.html#gac31898a52e172935f354819c50d3ef8d',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpio4_5fioset4_5f2_1107',['FSMC_PIO4_IOSET4_2',['../group___peripheral___registers___bits___definition.html#gaf35797347825725faef495c676269927',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpio4_5fioset4_5f3_1108',['FSMC_PIO4_IOSET4_3',['../group___peripheral___registers___bits___definition.html#gae45109e3dcc3c3a15efd13eddffdd8c9',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpio4_5fioset4_5f4_1109',['FSMC_PIO4_IOSET4_4',['../group___peripheral___registers___bits___definition.html#ga349e3a58f832fbc9de16955521355c29',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpio4_5fioset4_5f5_1110',['FSMC_PIO4_IOSET4_5',['../group___peripheral___registers___bits___definition.html#gaf3304545838a6e20742b0203e0cb023a',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpio4_5fioset4_5f6_1111',['FSMC_PIO4_IOSET4_6',['../group___peripheral___registers___bits___definition.html#ga800ab779078734ca86eedb6c9e77bc57',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpio4_5fioset4_5f7_1112',['FSMC_PIO4_IOSET4_7',['../group___peripheral___registers___bits___definition.html#ga7e29b066726c486c6503d417d18904b1',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpio4_5fioset4_5fmsk_1113',['FSMC_PIO4_IOSET4_Msk',['../group___peripheral___registers___bits___definition.html#ga3358c18b8b82cd13305ec60101187b5c',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpio4_5fioset4_5fpos_1114',['FSMC_PIO4_IOSET4_Pos',['../group___peripheral___registers___bits___definition.html#ga9972446feb353b113f1c31cf6be894e5',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpio4_5fiowait4_1115',['FSMC_PIO4_IOWAIT4',['../group___peripheral___registers___bits___definition.html#ga035a0645caab3851714123302dd0af1c',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpio4_5fiowait4_5f0_1116',['FSMC_PIO4_IOWAIT4_0',['../group___peripheral___registers___bits___definition.html#gafb868a5bf3d33997c782f296440cabf7',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpio4_5fiowait4_5f1_1117',['FSMC_PIO4_IOWAIT4_1',['../group___peripheral___registers___bits___definition.html#gaaa48c96fedf31c6ab444828d60e471da',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpio4_5fiowait4_5f2_1118',['FSMC_PIO4_IOWAIT4_2',['../group___peripheral___registers___bits___definition.html#ga342e42235a123ea11544b1a230b07a75',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpio4_5fiowait4_5f3_1119',['FSMC_PIO4_IOWAIT4_3',['../group___peripheral___registers___bits___definition.html#ga9c012d7c41f51516580766d6ac36d82f',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpio4_5fiowait4_5f4_1120',['FSMC_PIO4_IOWAIT4_4',['../group___peripheral___registers___bits___definition.html#ga5331b528505a31a2b39deca7a5ddba02',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpio4_5fiowait4_5f5_1121',['FSMC_PIO4_IOWAIT4_5',['../group___peripheral___registers___bits___definition.html#gaabbfbc377efde5170ac484795a0a4215',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpio4_5fiowait4_5f6_1122',['FSMC_PIO4_IOWAIT4_6',['../group___peripheral___registers___bits___definition.html#ga0be64ff24a6ccb7eef471ad2ad0e283b',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpio4_5fiowait4_5f7_1123',['FSMC_PIO4_IOWAIT4_7',['../group___peripheral___registers___bits___definition.html#ga3e3fc1b8cfa57116c0521cafd7e733cc',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpio4_5fiowait4_5fmsk_1124',['FSMC_PIO4_IOWAIT4_Msk',['../group___peripheral___registers___bits___definition.html#gaa4594c1e3df3d2345bf1207cab2de430',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpio4_5fiowait4_5fpos_1125',['FSMC_PIO4_IOWAIT4_Pos',['../group___peripheral___registers___bits___definition.html#ga7003102b5d51a06d74a8176ca1299099',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpmem2_5fmemhiz2_1126',['FSMC_PMEM2_MEMHIZ2',['../group___peripheral___registers___bits___definition.html#ga8a7783e155a688bf79e68ebf570421c4',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpmem2_5fmemhiz2_5f0_1127',['FSMC_PMEM2_MEMHIZ2_0',['../group___peripheral___registers___bits___definition.html#ga8bb51ecefa94c1ab3b91c7a14705b8c8',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpmem2_5fmemhiz2_5f1_1128',['FSMC_PMEM2_MEMHIZ2_1',['../group___peripheral___registers___bits___definition.html#ga4c0d8bf861d9918763b7391d4ad287b0',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpmem2_5fmemhiz2_5f2_1129',['FSMC_PMEM2_MEMHIZ2_2',['../group___peripheral___registers___bits___definition.html#gaebd6a4457fa0ac4f1b98fdc58bef9999',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpmem2_5fmemhiz2_5f3_1130',['FSMC_PMEM2_MEMHIZ2_3',['../group___peripheral___registers___bits___definition.html#gaded9a6b1b516fa2595988c84c5465f9b',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpmem2_5fmemhiz2_5f4_1131',['FSMC_PMEM2_MEMHIZ2_4',['../group___peripheral___registers___bits___definition.html#gad9b1831fb25422c7a126a7d029223394',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpmem2_5fmemhiz2_5f5_1132',['FSMC_PMEM2_MEMHIZ2_5',['../group___peripheral___registers___bits___definition.html#gae828a4dde56e15f78ab156feeb329af9',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpmem2_5fmemhiz2_5f6_1133',['FSMC_PMEM2_MEMHIZ2_6',['../group___peripheral___registers___bits___definition.html#gacf5464a2e8aeec6eb06c58283168ef97',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpmem2_5fmemhiz2_5f7_1134',['FSMC_PMEM2_MEMHIZ2_7',['../group___peripheral___registers___bits___definition.html#ga3c5ca1880a516478e1b8f1142066c004',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpmem2_5fmemhiz2_5fmsk_1135',['FSMC_PMEM2_MEMHIZ2_Msk',['../group___peripheral___registers___bits___definition.html#gab6155f1c3280ce295a8c90bb5e3dfba9',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpmem2_5fmemhiz2_5fpos_1136',['FSMC_PMEM2_MEMHIZ2_Pos',['../group___peripheral___registers___bits___definition.html#ga1964483dae67a5aff01ddd046583acb7',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpmem2_5fmemhold2_1137',['FSMC_PMEM2_MEMHOLD2',['../group___peripheral___registers___bits___definition.html#gaad2c79ef9df8b619e93c15b506f4fd7d',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpmem2_5fmemhold2_5f0_1138',['FSMC_PMEM2_MEMHOLD2_0',['../group___peripheral___registers___bits___definition.html#gadd16a720c69fcac1f6b798cf6f9bbb7e',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpmem2_5fmemhold2_5f1_1139',['FSMC_PMEM2_MEMHOLD2_1',['../group___peripheral___registers___bits___definition.html#ga4630e2bdb842914d0f7b53d4ed610122',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpmem2_5fmemhold2_5f2_1140',['FSMC_PMEM2_MEMHOLD2_2',['../group___peripheral___registers___bits___definition.html#gacf699fd414971d0c52159c21652f5e58',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpmem2_5fmemhold2_5f3_1141',['FSMC_PMEM2_MEMHOLD2_3',['../group___peripheral___registers___bits___definition.html#gad3e1f50389b82f8737a12ef6d1683c4f',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpmem2_5fmemhold2_5f4_1142',['FSMC_PMEM2_MEMHOLD2_4',['../group___peripheral___registers___bits___definition.html#ga00c7b1a8cbcbcbcc0495ebd7c877ca9e',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpmem2_5fmemhold2_5f5_1143',['FSMC_PMEM2_MEMHOLD2_5',['../group___peripheral___registers___bits___definition.html#ga9cd7c5637824522c2bd0f2cd165ca218',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpmem2_5fmemhold2_5f6_1144',['FSMC_PMEM2_MEMHOLD2_6',['../group___peripheral___registers___bits___definition.html#ga52ee3806d174025ab98d6c9148f17ae2',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpmem2_5fmemhold2_5f7_1145',['FSMC_PMEM2_MEMHOLD2_7',['../group___peripheral___registers___bits___definition.html#gad1afae5788b827aebc3df92c74754b38',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpmem2_5fmemhold2_5fmsk_1146',['FSMC_PMEM2_MEMHOLD2_Msk',['../group___peripheral___registers___bits___definition.html#ga5f1e5661bbb15ad918a6e2f7d09fcfe6',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpmem2_5fmemhold2_5fpos_1147',['FSMC_PMEM2_MEMHOLD2_Pos',['../group___peripheral___registers___bits___definition.html#ga7e62ae5b193c0df1b570af7489ad9e78',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpmem2_5fmemset2_1148',['FSMC_PMEM2_MEMSET2',['../group___peripheral___registers___bits___definition.html#ga50a34195ddb7ab7aebc2acac39b27536',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpmem2_5fmemset2_5f0_1149',['FSMC_PMEM2_MEMSET2_0',['../group___peripheral___registers___bits___definition.html#ga529858550113070878ce680da0a6bf7d',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpmem2_5fmemset2_5f1_1150',['FSMC_PMEM2_MEMSET2_1',['../group___peripheral___registers___bits___definition.html#ga28517c1f5aeded21b3f0326247b0bbe1',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpmem2_5fmemset2_5f2_1151',['FSMC_PMEM2_MEMSET2_2',['../group___peripheral___registers___bits___definition.html#ga1f59339df091ad8a00d75c32b335b711',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpmem2_5fmemset2_5f3_1152',['FSMC_PMEM2_MEMSET2_3',['../group___peripheral___registers___bits___definition.html#ga7715c089272c9709e8f94590b46be609',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpmem2_5fmemset2_5f4_1153',['FSMC_PMEM2_MEMSET2_4',['../group___peripheral___registers___bits___definition.html#ga31a0e44106c1ec87375054be15b1cb84',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpmem2_5fmemset2_5f5_1154',['FSMC_PMEM2_MEMSET2_5',['../group___peripheral___registers___bits___definition.html#ga221edf50060c5dad91de3c0b877fdbfc',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpmem2_5fmemset2_5f6_1155',['FSMC_PMEM2_MEMSET2_6',['../group___peripheral___registers___bits___definition.html#ga5dc6beefe3ea22a84dbc44fd30843778',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpmem2_5fmemset2_5f7_1156',['FSMC_PMEM2_MEMSET2_7',['../group___peripheral___registers___bits___definition.html#gae14181cbd85100c2b3b104525c42ee6c',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpmem2_5fmemset2_5fmsk_1157',['FSMC_PMEM2_MEMSET2_Msk',['../group___peripheral___registers___bits___definition.html#ga1b57a52f74837d3aa9b7731a1a33159b',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpmem2_5fmemset2_5fpos_1158',['FSMC_PMEM2_MEMSET2_Pos',['../group___peripheral___registers___bits___definition.html#ga57fea4182c63e845dfaaeffe67d7dcf8',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpmem2_5fmemwait2_1159',['FSMC_PMEM2_MEMWAIT2',['../group___peripheral___registers___bits___definition.html#ga7affee760cfe5d04a58bda9cd7fc5f72',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpmem2_5fmemwait2_5f0_1160',['FSMC_PMEM2_MEMWAIT2_0',['../group___peripheral___registers___bits___definition.html#ga7ee1c7f3347678dff204e6ac8c6eaf4f',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpmem2_5fmemwait2_5f1_1161',['FSMC_PMEM2_MEMWAIT2_1',['../group___peripheral___registers___bits___definition.html#ga56de464fa3f895e75f0ec2ff3f9e1e1e',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpmem2_5fmemwait2_5f2_1162',['FSMC_PMEM2_MEMWAIT2_2',['../group___peripheral___registers___bits___definition.html#ga922a823292054746923fb13b8f4c1b5c',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpmem2_5fmemwait2_5f3_1163',['FSMC_PMEM2_MEMWAIT2_3',['../group___peripheral___registers___bits___definition.html#ga44f9c0141f457b0ef0ff42c1645d7337',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpmem2_5fmemwait2_5f4_1164',['FSMC_PMEM2_MEMWAIT2_4',['../group___peripheral___registers___bits___definition.html#ga8d15645ffe422f3e35cc03efd93361cb',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpmem2_5fmemwait2_5f5_1165',['FSMC_PMEM2_MEMWAIT2_5',['../group___peripheral___registers___bits___definition.html#ga640d5866b22b11924b7e4c9bfc608624',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpmem2_5fmemwait2_5f6_1166',['FSMC_PMEM2_MEMWAIT2_6',['../group___peripheral___registers___bits___definition.html#ga51d69f501306eae03db719cb52065b3c',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpmem2_5fmemwait2_5f7_1167',['FSMC_PMEM2_MEMWAIT2_7',['../group___peripheral___registers___bits___definition.html#ga127b0e01d15f1007cfa67247a99da26f',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpmem2_5fmemwait2_5fmsk_1168',['FSMC_PMEM2_MEMWAIT2_Msk',['../group___peripheral___registers___bits___definition.html#ga90343ef2f0e0433265e721aeba552f3f',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpmem2_5fmemwait2_5fpos_1169',['FSMC_PMEM2_MEMWAIT2_Pos',['../group___peripheral___registers___bits___definition.html#ga0072f7fa82f3fb4ca184511738fc4d30',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpmem3_5fmemhiz3_1170',['FSMC_PMEM3_MEMHIZ3',['../group___peripheral___registers___bits___definition.html#ga3a77d54c66589f233792d30fc83e7f12',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpmem3_5fmemhiz3_5f0_1171',['FSMC_PMEM3_MEMHIZ3_0',['../group___peripheral___registers___bits___definition.html#ga2d8453ab8a7488ff13c681154bfd293c',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpmem3_5fmemhiz3_5f1_1172',['FSMC_PMEM3_MEMHIZ3_1',['../group___peripheral___registers___bits___definition.html#gaf023951ad4fd31a691cc26fc3c27ec46',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpmem3_5fmemhiz3_5f2_1173',['FSMC_PMEM3_MEMHIZ3_2',['../group___peripheral___registers___bits___definition.html#gaaf8d790834161e0224c878cd8eab190e',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpmem3_5fmemhiz3_5f3_1174',['FSMC_PMEM3_MEMHIZ3_3',['../group___peripheral___registers___bits___definition.html#ga26daeb039123824e2de5fdd64cb3a1ff',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpmem3_5fmemhiz3_5f4_1175',['FSMC_PMEM3_MEMHIZ3_4',['../group___peripheral___registers___bits___definition.html#gafd06d96e44933ce665b2af8c2a4098e4',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpmem3_5fmemhiz3_5f5_1176',['FSMC_PMEM3_MEMHIZ3_5',['../group___peripheral___registers___bits___definition.html#gaef1254b2e2251da2b30aa297d1d0a1f8',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpmem3_5fmemhiz3_5f6_1177',['FSMC_PMEM3_MEMHIZ3_6',['../group___peripheral___registers___bits___definition.html#gaf33c72c5ab0747d587a801835cf1a897',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpmem3_5fmemhiz3_5f7_1178',['FSMC_PMEM3_MEMHIZ3_7',['../group___peripheral___registers___bits___definition.html#gaa7304d0d28edd32a70be474e656fbf8e',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpmem3_5fmemhiz3_5fmsk_1179',['FSMC_PMEM3_MEMHIZ3_Msk',['../group___peripheral___registers___bits___definition.html#ga0dfe7b65ecc252eca58b04156dbd4c32',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpmem3_5fmemhiz3_5fpos_1180',['FSMC_PMEM3_MEMHIZ3_Pos',['../group___peripheral___registers___bits___definition.html#ga14b9bedec189a62c563088a91e1a4a0e',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpmem3_5fmemhold3_1181',['FSMC_PMEM3_MEMHOLD3',['../group___peripheral___registers___bits___definition.html#gac8ef1e0f4db1e2792b0939f9058a149b',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpmem3_5fmemhold3_5f0_1182',['FSMC_PMEM3_MEMHOLD3_0',['../group___peripheral___registers___bits___definition.html#gaa1abd4698bb45c784b23b8d431eb90f1',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpmem3_5fmemhold3_5f1_1183',['FSMC_PMEM3_MEMHOLD3_1',['../group___peripheral___registers___bits___definition.html#ga0a93e71d784bdb1cd115805feac42d6b',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpmem3_5fmemhold3_5f2_1184',['FSMC_PMEM3_MEMHOLD3_2',['../group___peripheral___registers___bits___definition.html#ga20a5443b5236e71b8dfe0620abffbd68',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpmem3_5fmemhold3_5f3_1185',['FSMC_PMEM3_MEMHOLD3_3',['../group___peripheral___registers___bits___definition.html#ga3b330eabb266b26cf6aa93b12bfe7b38',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpmem3_5fmemhold3_5f4_1186',['FSMC_PMEM3_MEMHOLD3_4',['../group___peripheral___registers___bits___definition.html#gac6d1864268bb87124d127d92e8db54dc',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpmem3_5fmemhold3_5f5_1187',['FSMC_PMEM3_MEMHOLD3_5',['../group___peripheral___registers___bits___definition.html#ga8968569a91c0b5d6c456074ddfc98aa3',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpmem3_5fmemhold3_5f6_1188',['FSMC_PMEM3_MEMHOLD3_6',['../group___peripheral___registers___bits___definition.html#gaf40967f9e19b41e2692b7fe1177b8629',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpmem3_5fmemhold3_5f7_1189',['FSMC_PMEM3_MEMHOLD3_7',['../group___peripheral___registers___bits___definition.html#gaf0da29e1e300e47aebb0bd47bf5f0563',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpmem3_5fmemhold3_5fmsk_1190',['FSMC_PMEM3_MEMHOLD3_Msk',['../group___peripheral___registers___bits___definition.html#ga1dba6050327dc9b2282e64e8236e6725',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpmem3_5fmemhold3_5fpos_1191',['FSMC_PMEM3_MEMHOLD3_Pos',['../group___peripheral___registers___bits___definition.html#ga6130db15261d3342f1f6882fabccb590',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpmem3_5fmemset3_1192',['FSMC_PMEM3_MEMSET3',['../group___peripheral___registers___bits___definition.html#gaf69ac574f9be3c11ada1e2dc4c3abe4f',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpmem3_5fmemset3_5f0_1193',['FSMC_PMEM3_MEMSET3_0',['../group___peripheral___registers___bits___definition.html#gaee68bc7ff3e4cf11c2ca826541858c6a',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpmem3_5fmemset3_5f1_1194',['FSMC_PMEM3_MEMSET3_1',['../group___peripheral___registers___bits___definition.html#gafa10132605ec4a4be1ab48ee6b36080e',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpmem3_5fmemset3_5f2_1195',['FSMC_PMEM3_MEMSET3_2',['../group___peripheral___registers___bits___definition.html#gacd867b06de7c7a49244b6a35570d2cd2',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpmem3_5fmemset3_5f3_1196',['FSMC_PMEM3_MEMSET3_3',['../group___peripheral___registers___bits___definition.html#ga292a8826723614aa2504a376f4a2e5d5',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpmem3_5fmemset3_5f4_1197',['FSMC_PMEM3_MEMSET3_4',['../group___peripheral___registers___bits___definition.html#ga98703fee6465ba580b052ef76f2c63f2',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpmem3_5fmemset3_5f5_1198',['FSMC_PMEM3_MEMSET3_5',['../group___peripheral___registers___bits___definition.html#gaaea28a64fc9a7e0df35826b4ec372361',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpmem3_5fmemset3_5f6_1199',['FSMC_PMEM3_MEMSET3_6',['../group___peripheral___registers___bits___definition.html#gaea51bbe866574be10bdc1d2d16bb9810',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpmem3_5fmemset3_5f7_1200',['FSMC_PMEM3_MEMSET3_7',['../group___peripheral___registers___bits___definition.html#ga702eeb8c3930ea564af728cc3bb9044b',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpmem3_5fmemset3_5fmsk_1201',['FSMC_PMEM3_MEMSET3_Msk',['../group___peripheral___registers___bits___definition.html#gaaa58775ce9ebda0e97d4bf481c7bd53e',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpmem3_5fmemset3_5fpos_1202',['FSMC_PMEM3_MEMSET3_Pos',['../group___peripheral___registers___bits___definition.html#ga2db6b5656145efa4ae5c03d5932a5abf',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpmem3_5fmemwait3_1203',['FSMC_PMEM3_MEMWAIT3',['../group___peripheral___registers___bits___definition.html#ga4243cb8b53a10143621872c0d0ed318b',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpmem3_5fmemwait3_5f0_1204',['FSMC_PMEM3_MEMWAIT3_0',['../group___peripheral___registers___bits___definition.html#ga30d8aad77f584d1c380b6d04d4984ac5',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpmem3_5fmemwait3_5f1_1205',['FSMC_PMEM3_MEMWAIT3_1',['../group___peripheral___registers___bits___definition.html#gaacf4638838e3cf2dfa076ef795596967',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpmem3_5fmemwait3_5f2_1206',['FSMC_PMEM3_MEMWAIT3_2',['../group___peripheral___registers___bits___definition.html#gaa1c65a1027062f3fff04dfdd24c33e64',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpmem3_5fmemwait3_5f3_1207',['FSMC_PMEM3_MEMWAIT3_3',['../group___peripheral___registers___bits___definition.html#gae23146168ddc8e06defd6e75390dde1d',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpmem3_5fmemwait3_5f4_1208',['FSMC_PMEM3_MEMWAIT3_4',['../group___peripheral___registers___bits___definition.html#ga79640d63c03f94bd4f38859c46bad820',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpmem3_5fmemwait3_5f5_1209',['FSMC_PMEM3_MEMWAIT3_5',['../group___peripheral___registers___bits___definition.html#ga8d36841fa1730bbbc825278cffd623f3',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpmem3_5fmemwait3_5f6_1210',['FSMC_PMEM3_MEMWAIT3_6',['../group___peripheral___registers___bits___definition.html#ga2bd34f98ee23b7a58ac63cd195c00d70',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpmem3_5fmemwait3_5f7_1211',['FSMC_PMEM3_MEMWAIT3_7',['../group___peripheral___registers___bits___definition.html#ga0f485579592b7fdf2e480523ee220418',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpmem3_5fmemwait3_5fmsk_1212',['FSMC_PMEM3_MEMWAIT3_Msk',['../group___peripheral___registers___bits___definition.html#ga57e03075040da97e636158721615ca93',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpmem3_5fmemwait3_5fpos_1213',['FSMC_PMEM3_MEMWAIT3_Pos',['../group___peripheral___registers___bits___definition.html#ga1fae8d256e50724a047b115add6b6f8c',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpmem4_5fmemhiz4_1214',['FSMC_PMEM4_MEMHIZ4',['../group___peripheral___registers___bits___definition.html#ga6b194500112e61e5dd41ded843bb08c6',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpmem4_5fmemhiz4_5f0_1215',['FSMC_PMEM4_MEMHIZ4_0',['../group___peripheral___registers___bits___definition.html#ga9298e847d13d24cbe87a3c477af9f02c',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpmem4_5fmemhiz4_5f1_1216',['FSMC_PMEM4_MEMHIZ4_1',['../group___peripheral___registers___bits___definition.html#ga591eb0822bbb91c4ba12f80d35424c4c',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpmem4_5fmemhiz4_5f2_1217',['FSMC_PMEM4_MEMHIZ4_2',['../group___peripheral___registers___bits___definition.html#ga6db858408154b3694bb1fdc995f7e069',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpmem4_5fmemhiz4_5f3_1218',['FSMC_PMEM4_MEMHIZ4_3',['../group___peripheral___registers___bits___definition.html#ga0e38ef7ec628928bea867de00af9b206',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpmem4_5fmemhiz4_5f4_1219',['FSMC_PMEM4_MEMHIZ4_4',['../group___peripheral___registers___bits___definition.html#ga81a86c24f41bd5363793953df972d941',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpmem4_5fmemhiz4_5f5_1220',['FSMC_PMEM4_MEMHIZ4_5',['../group___peripheral___registers___bits___definition.html#ga08a6ec2df1aa20cfcfacaed7e60417a0',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpmem4_5fmemhiz4_5f6_1221',['FSMC_PMEM4_MEMHIZ4_6',['../group___peripheral___registers___bits___definition.html#ga443fff9e0a661cce0d3fe96886eceb0b',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpmem4_5fmemhiz4_5f7_1222',['FSMC_PMEM4_MEMHIZ4_7',['../group___peripheral___registers___bits___definition.html#ga90cf92af2475f9f7cadbb9553225260d',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpmem4_5fmemhiz4_5fmsk_1223',['FSMC_PMEM4_MEMHIZ4_Msk',['../group___peripheral___registers___bits___definition.html#gaa99cb02c3b57623c92d17f68b44f84a4',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpmem4_5fmemhiz4_5fpos_1224',['FSMC_PMEM4_MEMHIZ4_Pos',['../group___peripheral___registers___bits___definition.html#gab27dd74b58a232a823408c58277b19ef',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpmem4_5fmemhold4_1225',['FSMC_PMEM4_MEMHOLD4',['../group___peripheral___registers___bits___definition.html#ga5028f0c2a642b7faedf602f0b2c0d64c',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpmem4_5fmemhold4_5f0_1226',['FSMC_PMEM4_MEMHOLD4_0',['../group___peripheral___registers___bits___definition.html#gaf07eef15a372886fda3182f49e2e912e',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpmem4_5fmemhold4_5f1_1227',['FSMC_PMEM4_MEMHOLD4_1',['../group___peripheral___registers___bits___definition.html#gaa05a691ca81b6fe6df07adb1c5142597',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpmem4_5fmemhold4_5f2_1228',['FSMC_PMEM4_MEMHOLD4_2',['../group___peripheral___registers___bits___definition.html#gaafd4f50c33f4ec69e878983fb6065c73',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpmem4_5fmemhold4_5f3_1229',['FSMC_PMEM4_MEMHOLD4_3',['../group___peripheral___registers___bits___definition.html#gac3cf67d6699d41fc042aed2be6d6aef0',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpmem4_5fmemhold4_5f4_1230',['FSMC_PMEM4_MEMHOLD4_4',['../group___peripheral___registers___bits___definition.html#ga963acb8aef1a1e3f7f369421a3f9bfd9',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpmem4_5fmemhold4_5f5_1231',['FSMC_PMEM4_MEMHOLD4_5',['../group___peripheral___registers___bits___definition.html#gac3ca8c6eb5fde2be7d38bde8aedb5522',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpmem4_5fmemhold4_5f6_1232',['FSMC_PMEM4_MEMHOLD4_6',['../group___peripheral___registers___bits___definition.html#gae0352f9aa02c4037d690b516d7385d27',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpmem4_5fmemhold4_5f7_1233',['FSMC_PMEM4_MEMHOLD4_7',['../group___peripheral___registers___bits___definition.html#ga880aa86c933687f7565b7ab79776923e',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpmem4_5fmemhold4_5fmsk_1234',['FSMC_PMEM4_MEMHOLD4_Msk',['../group___peripheral___registers___bits___definition.html#gaf0cf6a3b9e83d5785668a232f179922b',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpmem4_5fmemhold4_5fpos_1235',['FSMC_PMEM4_MEMHOLD4_Pos',['../group___peripheral___registers___bits___definition.html#gaa288ec797541c772dfd1ce78ef63335e',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpmem4_5fmemset4_1236',['FSMC_PMEM4_MEMSET4',['../group___peripheral___registers___bits___definition.html#ga3b5cb5385ce2cef772ee4493c25617aa',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpmem4_5fmemset4_5f0_1237',['FSMC_PMEM4_MEMSET4_0',['../group___peripheral___registers___bits___definition.html#ga6df1a1190522593b71da113c7ea8cfab',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpmem4_5fmemset4_5f1_1238',['FSMC_PMEM4_MEMSET4_1',['../group___peripheral___registers___bits___definition.html#ga6fa76a9c077f40e973df8fe6903c69c4',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpmem4_5fmemset4_5f2_1239',['FSMC_PMEM4_MEMSET4_2',['../group___peripheral___registers___bits___definition.html#ga03ddc1ecb61313593976bf70aec06e9f',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpmem4_5fmemset4_5f3_1240',['FSMC_PMEM4_MEMSET4_3',['../group___peripheral___registers___bits___definition.html#ga4280253a6049c7739c6b70a6d7940998',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpmem4_5fmemset4_5f4_1241',['FSMC_PMEM4_MEMSET4_4',['../group___peripheral___registers___bits___definition.html#ga153d7b557dc40b797f93bf5593808279',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpmem4_5fmemset4_5f5_1242',['FSMC_PMEM4_MEMSET4_5',['../group___peripheral___registers___bits___definition.html#gabc8fc6eadc2e952227c121b6d6114834',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpmem4_5fmemset4_5f6_1243',['FSMC_PMEM4_MEMSET4_6',['../group___peripheral___registers___bits___definition.html#gaecce633b6da6db82000f1d39dc23bb3b',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpmem4_5fmemset4_5f7_1244',['FSMC_PMEM4_MEMSET4_7',['../group___peripheral___registers___bits___definition.html#ga04c68698ff6f47551244ae5a26893059',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpmem4_5fmemset4_5fmsk_1245',['FSMC_PMEM4_MEMSET4_Msk',['../group___peripheral___registers___bits___definition.html#gaa6506768173e0734a59f62d527f3f0a4',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpmem4_5fmemset4_5fpos_1246',['FSMC_PMEM4_MEMSET4_Pos',['../group___peripheral___registers___bits___definition.html#gaeec8eeb3ff3a51842b4bc3a0f01315c0',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpmem4_5fmemwait4_1247',['FSMC_PMEM4_MEMWAIT4',['../group___peripheral___registers___bits___definition.html#ga9673f81abf15ad70d09520db9ddfc58d',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpmem4_5fmemwait4_5f0_1248',['FSMC_PMEM4_MEMWAIT4_0',['../group___peripheral___registers___bits___definition.html#ga9c88b294c963e5be76da4bf3048af411',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpmem4_5fmemwait4_5f1_1249',['FSMC_PMEM4_MEMWAIT4_1',['../group___peripheral___registers___bits___definition.html#ga24d45891fa0a503d81f68f62f5fd18e5',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpmem4_5fmemwait4_5f2_1250',['FSMC_PMEM4_MEMWAIT4_2',['../group___peripheral___registers___bits___definition.html#gaf1fa35a7722b6339a7cef85b5be2280d',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpmem4_5fmemwait4_5f3_1251',['FSMC_PMEM4_MEMWAIT4_3',['../group___peripheral___registers___bits___definition.html#ga929f7f1066e3f2d69c72126615d06cb0',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpmem4_5fmemwait4_5f4_1252',['FSMC_PMEM4_MEMWAIT4_4',['../group___peripheral___registers___bits___definition.html#ga5282e3d9205f778b67ef00c27beb2918',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpmem4_5fmemwait4_5f5_1253',['FSMC_PMEM4_MEMWAIT4_5',['../group___peripheral___registers___bits___definition.html#ga1eed44a0b89a9f14b08c4ab2578ca5cc',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpmem4_5fmemwait4_5f6_1254',['FSMC_PMEM4_MEMWAIT4_6',['../group___peripheral___registers___bits___definition.html#gab2429913d3b7993dfda75413f0a72bf4',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpmem4_5fmemwait4_5f7_1255',['FSMC_PMEM4_MEMWAIT4_7',['../group___peripheral___registers___bits___definition.html#ga247eb296ad16d1c7f2ebea0ca85619f9',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpmem4_5fmemwait4_5fmsk_1256',['FSMC_PMEM4_MEMWAIT4_Msk',['../group___peripheral___registers___bits___definition.html#gaeb6d7917d078c6ccdc62cd80e9578513',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fpmem4_5fmemwait4_5fpos_1257',['FSMC_PMEM4_MEMWAIT4_Pos',['../group___peripheral___registers___bits___definition.html#ga265881544d02839df4b2a9b03be04358',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fr_5fbase_1258',['FSMC_R_BASE',['../group___c_m_s_i_s___device.html#gaeb17f07e5976d0674b1afe60cffc79d4',1,'_memory::FSMC_R_BASE'],['../group___peripheral__memory__map.html#gaddf0e199dccba83272b20c9fb4d3aaed',1,'FSMC_R_BASE: stm32f407xx_matlab.h']]], - ['fsmc_5fr_5fbase_5fshift_1259',['FSMC_R_BASE_SHIFT',['../group___peripheral__memory__map.html#gae359dc044d8a99c9634a01abdbab704b',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fr_5fsize_1260',['FSMC_R_SIZE',['../group___peripheral__memory__map.html#ga36147b9ef36c5be4745a45162cd85be4',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fsr2_5ffempt_1261',['FSMC_SR2_FEMPT',['../group___peripheral___registers___bits___definition.html#ga6ae2e544a4a515303f49815cdbd5ebbb',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fsr2_5ffempt_5fmsk_1262',['FSMC_SR2_FEMPT_Msk',['../group___peripheral___registers___bits___definition.html#gaaa95bc00b8c686ad2b0078d28b0f4830',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fsr2_5ffempt_5fpos_1263',['FSMC_SR2_FEMPT_Pos',['../group___peripheral___registers___bits___definition.html#ga39d0ccd9fb1c6c802201f0d5b2497892',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fsr2_5fifen_1264',['FSMC_SR2_IFEN',['../group___peripheral___registers___bits___definition.html#ga755c088c58b27f79108675f56ea9d196',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fsr2_5fifen_5fmsk_1265',['FSMC_SR2_IFEN_Msk',['../group___peripheral___registers___bits___definition.html#ga5b3607ef98ac617609731f96d63a6d8c',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fsr2_5fifen_5fpos_1266',['FSMC_SR2_IFEN_Pos',['../group___peripheral___registers___bits___definition.html#ga19ce3774c409a6824a03414035807696',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fsr2_5fifs_1267',['FSMC_SR2_IFS',['../group___peripheral___registers___bits___definition.html#gad6492ad6afe175283d07de38978936dc',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fsr2_5fifs_5fmsk_1268',['FSMC_SR2_IFS_Msk',['../group___peripheral___registers___bits___definition.html#ga892a452cb80f67fc2c5f4a0ff775ff5b',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fsr2_5fifs_5fpos_1269',['FSMC_SR2_IFS_Pos',['../group___peripheral___registers___bits___definition.html#ga45cd1c374a43ee088640e33e95dc5688',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fsr2_5filen_1270',['FSMC_SR2_ILEN',['../group___peripheral___registers___bits___definition.html#ga1e9df0edd35d0ad6a35ff3a3b045b47c',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fsr2_5filen_5fmsk_1271',['FSMC_SR2_ILEN_Msk',['../group___peripheral___registers___bits___definition.html#gae59b87df9b2b879f3c6228b44f8e67ec',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fsr2_5filen_5fpos_1272',['FSMC_SR2_ILEN_Pos',['../group___peripheral___registers___bits___definition.html#gada9faf7f03a84292d12b91b59ecc6e8e',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fsr2_5fils_1273',['FSMC_SR2_ILS',['../group___peripheral___registers___bits___definition.html#ga664d6e1440c12e76dfa34f716af85ed1',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fsr2_5fils_5fmsk_1274',['FSMC_SR2_ILS_Msk',['../group___peripheral___registers___bits___definition.html#ga88ea643e2a899e222e2c9166f0b47af9',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fsr2_5fils_5fpos_1275',['FSMC_SR2_ILS_Pos',['../group___peripheral___registers___bits___definition.html#ga640c5b0f263676b6d0e5934916f6613d',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fsr2_5firen_1276',['FSMC_SR2_IREN',['../group___peripheral___registers___bits___definition.html#ga3216bd665a118239e6ef0b58ec5e8a8e',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fsr2_5firen_5fmsk_1277',['FSMC_SR2_IREN_Msk',['../group___peripheral___registers___bits___definition.html#ga99bc457a07a274821c92d025bee142b2',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fsr2_5firen_5fpos_1278',['FSMC_SR2_IREN_Pos',['../group___peripheral___registers___bits___definition.html#ga64ac90a6d11f1b83eaaba0bbe76225a6',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fsr2_5firs_1279',['FSMC_SR2_IRS',['../group___peripheral___registers___bits___definition.html#ga19f1b90b2da89b68aa754d0a89d60de9',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fsr2_5firs_5fmsk_1280',['FSMC_SR2_IRS_Msk',['../group___peripheral___registers___bits___definition.html#gad134a6cdb6d9df958be6f45ea4f952a7',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fsr2_5firs_5fpos_1281',['FSMC_SR2_IRS_Pos',['../group___peripheral___registers___bits___definition.html#ga06ebb4b8d85407f96dcbdf67f4a99cb9',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fsr3_5ffempt_1282',['FSMC_SR3_FEMPT',['../group___peripheral___registers___bits___definition.html#ga230562cf231dc79cd9354933b39ae7de',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fsr3_5ffempt_5fmsk_1283',['FSMC_SR3_FEMPT_Msk',['../group___peripheral___registers___bits___definition.html#ga6436500aea203033a62f7ddcbad814a3',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fsr3_5ffempt_5fpos_1284',['FSMC_SR3_FEMPT_Pos',['../group___peripheral___registers___bits___definition.html#ga76a834622c16170caf9cb2e1fb14c452',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fsr3_5fifen_1285',['FSMC_SR3_IFEN',['../group___peripheral___registers___bits___definition.html#gaa7355e5368013759dbfabfec8b609ca8',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fsr3_5fifen_5fmsk_1286',['FSMC_SR3_IFEN_Msk',['../group___peripheral___registers___bits___definition.html#ga65588f7ae2e908af340e5ff1bfb18671',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fsr3_5fifen_5fpos_1287',['FSMC_SR3_IFEN_Pos',['../group___peripheral___registers___bits___definition.html#ga2c78f3e87e892640e79917b97a58ae0d',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fsr3_5fifs_1288',['FSMC_SR3_IFS',['../group___peripheral___registers___bits___definition.html#gafadff6b6f9e6430ada2f56bc9921dd7d',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fsr3_5fifs_5fmsk_1289',['FSMC_SR3_IFS_Msk',['../group___peripheral___registers___bits___definition.html#ga6a6b22553c9ad5a974bb1e8288932a54',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fsr3_5fifs_5fpos_1290',['FSMC_SR3_IFS_Pos',['../group___peripheral___registers___bits___definition.html#ga6149a6b31cbb1e18378e183cdbfa7cb6',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fsr3_5filen_1291',['FSMC_SR3_ILEN',['../group___peripheral___registers___bits___definition.html#ga86ac8f1f9f99c81a26fb54b597b57f12',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fsr3_5filen_5fmsk_1292',['FSMC_SR3_ILEN_Msk',['../group___peripheral___registers___bits___definition.html#gafec67196217e783676f157212cfc7976',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fsr3_5filen_5fpos_1293',['FSMC_SR3_ILEN_Pos',['../group___peripheral___registers___bits___definition.html#gac2b3bd94d6eddc0cdd3911ad580fa541',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fsr3_5fils_1294',['FSMC_SR3_ILS',['../group___peripheral___registers___bits___definition.html#ga9803b4ab5b8cce213a80abc11c751d21',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fsr3_5fils_5fmsk_1295',['FSMC_SR3_ILS_Msk',['../group___peripheral___registers___bits___definition.html#ga90c83ca70c1030e39babd809c181301b',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fsr3_5fils_5fpos_1296',['FSMC_SR3_ILS_Pos',['../group___peripheral___registers___bits___definition.html#gad9d20d9eb15db67e6195c83c6bfeba1a',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fsr3_5firen_1297',['FSMC_SR3_IREN',['../group___peripheral___registers___bits___definition.html#ga12baad15533ecbc57db95ea4939bc782',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fsr3_5firen_5fmsk_1298',['FSMC_SR3_IREN_Msk',['../group___peripheral___registers___bits___definition.html#ga1b1cab2aa1407a79d66c5c85029ea815',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fsr3_5firen_5fpos_1299',['FSMC_SR3_IREN_Pos',['../group___peripheral___registers___bits___definition.html#ga02bbc52ce42d56880369709c4f256dd3',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fsr3_5firs_1300',['FSMC_SR3_IRS',['../group___peripheral___registers___bits___definition.html#gad929e4a8c1fdb49ee6f690121336afea',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fsr3_5firs_5fmsk_1301',['FSMC_SR3_IRS_Msk',['../group___peripheral___registers___bits___definition.html#ga38a4f74813da2200db8d8f7254742593',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fsr3_5firs_5fpos_1302',['FSMC_SR3_IRS_Pos',['../group___peripheral___registers___bits___definition.html#ga88805716c1271a441d94a540f00d941b',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fsr4_5ffempt_1303',['FSMC_SR4_FEMPT',['../group___peripheral___registers___bits___definition.html#gaae7081cdf26e75bccfac1b6a29c04124',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fsr4_5ffempt_5fmsk_1304',['FSMC_SR4_FEMPT_Msk',['../group___peripheral___registers___bits___definition.html#gad85d7dabbc8635c7fbcf55e18c1b38c7',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fsr4_5ffempt_5fpos_1305',['FSMC_SR4_FEMPT_Pos',['../group___peripheral___registers___bits___definition.html#ga2927e164634b8377d7f5de607ffa8aae',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fsr4_5fifen_1306',['FSMC_SR4_IFEN',['../group___peripheral___registers___bits___definition.html#gaf97394e42be634cb441204f6bfffb504',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fsr4_5fifen_5fmsk_1307',['FSMC_SR4_IFEN_Msk',['../group___peripheral___registers___bits___definition.html#gaf050b0a4e3500f081929ef8893f3a01c',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fsr4_5fifen_5fpos_1308',['FSMC_SR4_IFEN_Pos',['../group___peripheral___registers___bits___definition.html#ga72c86dadfbc92cb71ada1b69afaf0422',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fsr4_5fifs_1309',['FSMC_SR4_IFS',['../group___peripheral___registers___bits___definition.html#gaf1e7d71b32a0b70d772fbdc85f7053fc',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fsr4_5fifs_5fmsk_1310',['FSMC_SR4_IFS_Msk',['../group___peripheral___registers___bits___definition.html#ga38930113868c959a3661b7296be4f3b4',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fsr4_5fifs_5fpos_1311',['FSMC_SR4_IFS_Pos',['../group___peripheral___registers___bits___definition.html#gaaba60426f9ebd437c2fe600929f17b9b',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fsr4_5filen_1312',['FSMC_SR4_ILEN',['../group___peripheral___registers___bits___definition.html#gac9b8d7c7b68723a4ef01843d547d95bc',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fsr4_5filen_5fmsk_1313',['FSMC_SR4_ILEN_Msk',['../group___peripheral___registers___bits___definition.html#ga7d2d4242df3e464630c5723bf8ce62f9',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fsr4_5filen_5fpos_1314',['FSMC_SR4_ILEN_Pos',['../group___peripheral___registers___bits___definition.html#gadb2544b2d75f937bc0ff66eaa824c8fa',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fsr4_5fils_1315',['FSMC_SR4_ILS',['../group___peripheral___registers___bits___definition.html#ga0e19feccd1553911d08be673c4af72ad',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fsr4_5fils_5fmsk_1316',['FSMC_SR4_ILS_Msk',['../group___peripheral___registers___bits___definition.html#gac9f640a57868933823d67ed24baae3cd',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fsr4_5fils_5fpos_1317',['FSMC_SR4_ILS_Pos',['../group___peripheral___registers___bits___definition.html#ga35d76d1ef37af831006e517f4c495b39',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fsr4_5firen_1318',['FSMC_SR4_IREN',['../group___peripheral___registers___bits___definition.html#ga6f5f17d22e07bb6674cbd68740b9708a',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fsr4_5firen_5fmsk_1319',['FSMC_SR4_IREN_Msk',['../group___peripheral___registers___bits___definition.html#ga7026294e98de80663d4530e07ae1777c',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fsr4_5firen_5fpos_1320',['FSMC_SR4_IREN_Pos',['../group___peripheral___registers___bits___definition.html#ga7345c2e21921244fde94badae4cb6084',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fsr4_5firs_1321',['FSMC_SR4_IRS',['../group___peripheral___registers___bits___definition.html#ga163f7143d51b516af0d46b142222957f',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fsr4_5firs_5fmsk_1322',['FSMC_SR4_IRS_Msk',['../group___peripheral___registers___bits___definition.html#ga359dc66df56e053e76cf0c8d8b1228f3',1,'stm32f407xx_matlab.h']]], - ['fsmc_5fsr4_5firs_5fpos_1323',['FSMC_SR4_IRS_Pos',['../group___peripheral___registers___bits___definition.html#ga8fd0b4be91d7fa754929c96bb772e40d',1,'stm32f407xx_matlab.h']]], - ['ftsr_1324',['FTSR',['../group___c_m_s_i_s___device.html#gaa0f7c828c46ae6f6bc9f66f11720bbe6',1,'EXTI_TypeDef']]], - ['function0_1325',['FUNCTION0',['../group___c_m_s_i_s__core___debug_functions.html#gad3c69d206a52a85165eb7bd8077b0608',1,'DWT_Type']]], - ['function1_1326',['FUNCTION1',['../group___c_m_s_i_s__core___debug_functions.html#gae8f02e32e101c4cc61115d271fa12ffb',1,'DWT_Type']]], - ['function2_1327',['FUNCTION2',['../group___c_m_s_i_s__core___debug_functions.html#ga8ba3cc103077080ae3c0fc41e87d1197',1,'DWT_Type']]], - ['function3_1328',['FUNCTION3',['../group___c_m_s_i_s__core___debug_functions.html#gafbfaba1d10558329868c6c55f91f82df',1,'DWT_Type']]], - ['functionalstate_1329',['FunctionalState',['../group___exported__types.html#gac9a7e9a35d2513ec15c3b537aaa4fba1',1,'stm32f4xx.h']]], - ['functions_1330',['Functions',['../group___c_m_s_i_s___core___fpu_functions.html',1,'FPU Functions'],['../group___c_m_s_i_s__core___debug_functions.html',1,'ITM Functions'],['../group___c_m_s_i_s___core___n_v_i_c_functions.html',1,'NVIC Functions'],['../group___c_m_s_i_s___core___sys_tick_functions.html',1,'SysTick Functions']]], - ['functions_20and_20instructions_20reference_1331',['Functions and Instructions Reference',['../group___c_m_s_i_s___core___function_interface.html',1,'']]] + ['flash_5fbase_0',['FLASH_BASE',['../struct__memory.html#a84303738f0e64d5303c027932c055d87',1,'_memory::FLASH_BASE'],['../group___peripheral__memory__map.html#ga23a9099a5f8fc9c6e253c0eecb2be8db',1,'FLASH_BASE: stm32f407xx_matlab_memory.h']]], + ['flash_5fbase_5fshift_1',['FLASH_BASE_SHIFT',['../group___peripheral__memory__map.html#ga4a1f7e664b3e091fee94976b33bbf7b9',1,'stm32f407xx_matlab_memory.h']]], + ['flash_5fend_2',['FLASH_END',['../group___peripheral__memory__map.html#ga8be554f354e5aa65370f6db63d4f3ee4',1,'stm32f407xx_matlab_memory.h']]], + ['flash_5fend_5fshift_3',['FLASH_END_SHIFT',['../group___peripheral__memory__map.html#ga77155e7666b070a9653f0a43d11f2004',1,'stm32f407xx_matlab_memory.h']]], + ['flash_5fotp_5fbase_4',['FLASH_OTP_BASE',['../struct__memory.html#ace5daae0e2da2f05a6b63f3f68109284',1,'_memory::FLASH_OTP_BASE'],['../group___peripheral__memory__map.html#ga91d296a67aec0da8f31c368cbc0eea94',1,'FLASH_OTP_BASE: stm32f407xx_matlab_memory.h']]], + ['flash_5fotp_5fbase_5fshift_5',['FLASH_OTP_BASE_SHIFT',['../group___peripheral__memory__map.html#ga1ea2ceeb2a729bb1072d98cf7c3ceb6e',1,'stm32f407xx_matlab_memory.h']]], + ['flash_5fotp_5fend_6',['FLASH_OTP_END',['../group___peripheral__memory__map.html#ga5bec9c5a91e312fca36f256f508ceee1',1,'stm32f407xx_matlab_memory.h']]], + ['flash_5fotp_5fend_5fshift_7',['FLASH_OTP_END_SHIFT',['../group___peripheral__memory__map.html#ga46ebe9214ddc2503af753a11fd5ccb80',1,'stm32f407xx_matlab_memory.h']]], + ['flash_5fotp_5fsize_8',['FLASH_OTP_SIZE',['../group___peripheral__memory__map.html#gacb3e2951c91f038686e0cbcd4321814b',1,'stm32f407xx_matlab_memory.h']]], + ['flash_5fr_9',['flash_r',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga9005724fdcdcbb61e849a94a8068d0a5',1,'stm32f4xx_periph_registers.c']]], + ['flash_5fsize_10',['FLASH_SIZE',['../group___peripheral__memory__map.html#gae69620948dea1b76e0ab7843ab719db7',1,'stm32f407xx_matlab_memory.h']]], + ['fmcu_5fstop_11',['fMCU_Stop',['../struct_s_i_m_____m_c_u_handle_type_def.html#ad81f091fd8c1ad2908a5dd5967f3322e',1,'SIM__MCUHandleTypeDef']]], + ['for_20debugging_12',['Periphs Variables for Debugging',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html',1,'']]], + ['fpu_13',['FPU',['../group___c_m_s_i_s__core__base.html#gabc7c93f2594e85ece1e1a24f10591428',1,'stm32f407xx_matlab_memory.h']]], + ['fpu_5fbase_14',['FPU_BASE',['../group___c_m_s_i_s__core__base.html#ga4dcad4027118c098c07bcd575f1fbb28',1,'stm32f407xx_matlab_memory.h']]], + ['fsmc_5fbank1_5fr_15',['fsmc_bank1_r',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#gabc182d46d8d7866f89db2e17f7d67496',1,'stm32f4xx_periph_registers.c']]], + ['fsmc_5fbank1e_5fr_16',['fsmc_bank1e_r',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#gac5d854d8ad94b3865847d64044c9bec8',1,'stm32f4xx_periph_registers.c']]], + ['fsmc_5fbank2_5f3_5fr_17',['fsmc_bank2_3_r',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga337be35abe408bd089d87060903b944f',1,'stm32f4xx_periph_registers.c']]], + ['fsmc_5fbank4_5fr_18',['fsmc_bank4_r',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga86a7b6923c554282c949627ccaaee51b',1,'stm32f4xx_periph_registers.c']]], + ['fsmc_5fr_5fbase_19',['FSMC_R_BASE',['../struct__memory.html#aeb17f07e5976d0674b1afe60cffc79d4',1,'_memory::FSMC_R_BASE'],['../group___peripheral__memory__map.html#gaddf0e199dccba83272b20c9fb4d3aaed',1,'FSMC_R_BASE: stm32f407xx_matlab_memory.h']]], + ['fsmc_5fr_5fbase_5fshift_20',['FSMC_R_BASE_SHIFT',['../group___peripheral__memory__map.html#gae359dc044d8a99c9634a01abdbab704b',1,'stm32f407xx_matlab_memory.h']]], + ['fsmc_5fr_5fsize_21',['FSMC_R_SIZE',['../group___peripheral__memory__map.html#ga36147b9ef36c5be4745a45162cd85be4',1,'stm32f407xx_matlab_memory.h']]], + ['function_20funtions_22',['S-Function funtions',['../group___w_r_a_p_p_e_r___s_f_u_n_c.html',1,'']]], + ['funtions_23',['S-Function funtions',['../group___w_r_a_p_p_e_r___s_f_u_n_c.html',1,'']]] ]; diff --git a/DOCS/html/search/all_7.js b/DOCS/html/search/all_7.js index 59fbabf..0c9fccb 100644 --- a/DOCS/html/search/all_7.js +++ b/DOCS/html/search/all_7.js @@ -1,1075 +1,15 @@ var searchData= [ - ['gahbcfg_0',['GAHBCFG',['../group___c_m_s_i_s___device.html#gac38ac55e4148686564478e95f345b833',1,'USB_OTG_GlobalTypeDef']]], - ['gccfg_1',['GCCFG',['../group___c_m_s_i_s___device.html#gaef85efc005db9a8e37d95644e92e9032',1,'USB_OTG_GlobalTypeDef']]], - ['ge_2',['GE',['../group___c_m_s_i_s__core___debug_functions.html#gaa91800ec6e90e457c7a1acd1f2e17099',1,'APSR_Type::GE'],['../group___c_m_s_i_s__core___debug_functions.html#gaa91800ec6e90e457c7a1acd1f2e17099',1,'APSR_Type::@0::GE'],['../group___c_m_s_i_s__core___debug_functions.html#gaa91800ec6e90e457c7a1acd1f2e17099',1,'xPSR_Type::GE'],['../group___c_m_s_i_s__core___debug_functions.html#gaa91800ec6e90e457c7a1acd1f2e17099',1,'xPSR_Type::@2::GE']]], - ['getcompilerconfigurations_3',['getCompilerConfigurations',['../mexing_8m.html#a8c4063b39743b0fdb6cbd8100456a07d',1,'mexing.m']]], - ['gintmsk_4',['GINTMSK',['../group___c_m_s_i_s___device.html#ga69d9432b4272331bffb34e196b57cbdf',1,'USB_OTG_GlobalTypeDef']]], - ['gintsts_5',['GINTSTS',['../group___c_m_s_i_s___device.html#ga9980c4a55080745a11528f8c7ffa1c66',1,'USB_OTG_GlobalTypeDef']]], - ['global_20defines_6',['CMSIS Global Defines',['../group___c_m_s_i_s__glob__defs.html',1,'']]], - ['gotgctl_7',['GOTGCTL',['../group___c_m_s_i_s___device.html#ga4f006a75f87074f02a532fbeb215bd24',1,'USB_OTG_GlobalTypeDef']]], - ['gotgint_8',['GOTGINT',['../group___c_m_s_i_s___device.html#gaef613e58417a7201da95b89b85931da9',1,'USB_OTG_GlobalTypeDef']]], - ['gpio_5fafrh_5fafrh0_9',['GPIO_AFRH_AFRH0',['../group___peripheral___registers___bits___definition.html#gadc5bb516e3b29af807cf4772787dfd0d',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrh_5fafrh0_5f0_10',['GPIO_AFRH_AFRH0_0',['../group___peripheral___registers___bits___definition.html#ga696d2e7fbb6ae2b172f64f9edd5af9b0',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrh_5fafrh0_5f1_11',['GPIO_AFRH_AFRH0_1',['../group___peripheral___registers___bits___definition.html#ga21e5f36c2bf8a8977d72621d93876b0b',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrh_5fafrh0_5f2_12',['GPIO_AFRH_AFRH0_2',['../group___peripheral___registers___bits___definition.html#ga40d8eb06b294389ac37efc69291182ec',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrh_5fafrh0_5f3_13',['GPIO_AFRH_AFRH0_3',['../group___peripheral___registers___bits___definition.html#gaa177428d840116200ec8e3645cfffbc7',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrh_5fafrh1_14',['GPIO_AFRH_AFRH1',['../group___peripheral___registers___bits___definition.html#ga75ca2458aef597ebfcd1eb6b83035acd',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrh_5fafrh1_5f0_15',['GPIO_AFRH_AFRH1_0',['../group___peripheral___registers___bits___definition.html#ga5050213115941df4d89f1803ff3dce18',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrh_5fafrh1_5f1_16',['GPIO_AFRH_AFRH1_1',['../group___peripheral___registers___bits___definition.html#ga413c97129e63fb91bdf0ac8220d9db00',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrh_5fafrh1_5f2_17',['GPIO_AFRH_AFRH1_2',['../group___peripheral___registers___bits___definition.html#ga5b89ccc6c477c0cd8ff857285df07d84',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrh_5fafrh1_5f3_18',['GPIO_AFRH_AFRH1_3',['../group___peripheral___registers___bits___definition.html#gad0ead68cbb1f4aadad0789e8d2bd32e4',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrh_5fafrh2_19',['GPIO_AFRH_AFRH2',['../group___peripheral___registers___bits___definition.html#ga4dc39c907cd02befde4b7681b2fa070b',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrh_5fafrh2_5f0_20',['GPIO_AFRH_AFRH2_0',['../group___peripheral___registers___bits___definition.html#ga3bc474910f7c3867c687e3d642dc7f86',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrh_5fafrh2_5f1_21',['GPIO_AFRH_AFRH2_1',['../group___peripheral___registers___bits___definition.html#ga6284f87ff50100a6c3e2cb496be1388a',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrh_5fafrh2_5f2_22',['GPIO_AFRH_AFRH2_2',['../group___peripheral___registers___bits___definition.html#gaa444f8755f374e202cb437a9f202f635',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrh_5fafrh2_5f3_23',['GPIO_AFRH_AFRH2_3',['../group___peripheral___registers___bits___definition.html#ga02b23ce670e6b5a0e87f28d1baa673a2',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrh_5fafrh3_24',['GPIO_AFRH_AFRH3',['../group___peripheral___registers___bits___definition.html#ga7043cbf3ca044ba36d59a8844c50552b',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrh_5fafrh3_5f0_25',['GPIO_AFRH_AFRH3_0',['../group___peripheral___registers___bits___definition.html#ga5a0bca51b2c5a8635202590ed61842ab',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrh_5fafrh3_5f1_26',['GPIO_AFRH_AFRH3_1',['../group___peripheral___registers___bits___definition.html#gace0ca814ed3617d6f520ded8bc05cf3e',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrh_5fafrh3_5f2_27',['GPIO_AFRH_AFRH3_2',['../group___peripheral___registers___bits___definition.html#ga9e22f1d39a67e130c29ba1d30d8b0740',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrh_5fafrh3_5f3_28',['GPIO_AFRH_AFRH3_3',['../group___peripheral___registers___bits___definition.html#ga22d6db61365e1172a8e5d895cbc16f59',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrh_5fafrh4_29',['GPIO_AFRH_AFRH4',['../group___peripheral___registers___bits___definition.html#gadae24d162b9e5a99064a81ba6a8d01d8',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrh_5fafrh4_5f0_30',['GPIO_AFRH_AFRH4_0',['../group___peripheral___registers___bits___definition.html#gaee18ebc3ee54fcf4b049c722aaabd664',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrh_5fafrh4_5f1_31',['GPIO_AFRH_AFRH4_1',['../group___peripheral___registers___bits___definition.html#gabd4ef3f6843069e21c3474025f9ad452',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrh_5fafrh4_5f2_32',['GPIO_AFRH_AFRH4_2',['../group___peripheral___registers___bits___definition.html#ga23d973c410f46a567dd05719fc60e8b9',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrh_5fafrh4_5f3_33',['GPIO_AFRH_AFRH4_3',['../group___peripheral___registers___bits___definition.html#gaef19c9e546b1d7130244a824a129a86d',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrh_5fafrh5_34',['GPIO_AFRH_AFRH5',['../group___peripheral___registers___bits___definition.html#ga33b1d2c7b5ed5804798660a3e86214c4',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrh_5fafrh5_5f0_35',['GPIO_AFRH_AFRH5_0',['../group___peripheral___registers___bits___definition.html#gaaccf0f28c6792dcea352d16295a3370e',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrh_5fafrh5_5f1_36',['GPIO_AFRH_AFRH5_1',['../group___peripheral___registers___bits___definition.html#gadb8de41b0dd5fdb53556acbd27eaffef',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrh_5fafrh5_5f2_37',['GPIO_AFRH_AFRH5_2',['../group___peripheral___registers___bits___definition.html#ga17d3ee9f02ed784d1f9eafd306c7770b',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrh_5fafrh5_5f3_38',['GPIO_AFRH_AFRH5_3',['../group___peripheral___registers___bits___definition.html#gaaca724f908dbf5ae10fe4721c4bb9a63',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrh_5fafrh6_39',['GPIO_AFRH_AFRH6',['../group___peripheral___registers___bits___definition.html#ga56c388b4718d2257b4af362bec67a74a',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrh_5fafrh6_5f0_40',['GPIO_AFRH_AFRH6_0',['../group___peripheral___registers___bits___definition.html#ga67bfcdbe201c0d10d6c604a7a77ef2c0',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrh_5fafrh6_5f1_41',['GPIO_AFRH_AFRH6_1',['../group___peripheral___registers___bits___definition.html#ga3c262cd0c09affb4b7a8d7fe40cb8737',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrh_5fafrh6_5f2_42',['GPIO_AFRH_AFRH6_2',['../group___peripheral___registers___bits___definition.html#ga37c5f9c67bf086d5d2adf5e894476103',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrh_5fafrh6_5f3_43',['GPIO_AFRH_AFRH6_3',['../group___peripheral___registers___bits___definition.html#ga69f0639cf752be23c3d72c7218a1e179',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrh_5fafrh7_44',['GPIO_AFRH_AFRH7',['../group___peripheral___registers___bits___definition.html#ga770397420d63cb6e8317ae401e6b2977',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrh_5fafrh7_5f0_45',['GPIO_AFRH_AFRH7_0',['../group___peripheral___registers___bits___definition.html#gae5323b47a92dc55d60b67a8d36049b07',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrh_5fafrh7_5f1_46',['GPIO_AFRH_AFRH7_1',['../group___peripheral___registers___bits___definition.html#ga133a9bf6920bdf13fbeda9e02c88bab4',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrh_5fafrh7_5f2_47',['GPIO_AFRH_AFRH7_2',['../group___peripheral___registers___bits___definition.html#gaa20fc99964f4f634664e4498869d1ec4',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrh_5fafrh7_5f3_48',['GPIO_AFRH_AFRH7_3',['../group___peripheral___registers___bits___definition.html#ga3a6c924c6c54448656df6acfa66b9aae',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrh_5fafsel10_49',['GPIO_AFRH_AFSEL10',['../group___peripheral___registers___bits___definition.html#ga9c41926ac3fc6ec0fb8def28275bbe30',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrh_5fafsel10_5f0_50',['GPIO_AFRH_AFSEL10_0',['../group___peripheral___registers___bits___definition.html#ga6d9771de8ec013027f8f26d799e7a3fe',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrh_5fafsel10_5f1_51',['GPIO_AFRH_AFSEL10_1',['../group___peripheral___registers___bits___definition.html#gad8f7170c263301f7b7c55dcdf1acb832',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrh_5fafsel10_5f2_52',['GPIO_AFRH_AFSEL10_2',['../group___peripheral___registers___bits___definition.html#gaf0b280a9f8a751dcb4a27cf2e9a73598',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrh_5fafsel10_5f3_53',['GPIO_AFRH_AFSEL10_3',['../group___peripheral___registers___bits___definition.html#gacc1431b847bccbc8841d8ab9a6aa36e5',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrh_5fafsel10_5fmsk_54',['GPIO_AFRH_AFSEL10_Msk',['../group___peripheral___registers___bits___definition.html#ga33b875b9713ed4640e400fcf126cf105',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrh_5fafsel10_5fpos_55',['GPIO_AFRH_AFSEL10_Pos',['../group___peripheral___registers___bits___definition.html#ga334f2ca0e5684d230cb7788969997f07',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrh_5fafsel11_56',['GPIO_AFRH_AFSEL11',['../group___peripheral___registers___bits___definition.html#ga47a97a35b9f12ef795aa1ebb3d85c3aa',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrh_5fafsel11_5f0_57',['GPIO_AFRH_AFSEL11_0',['../group___peripheral___registers___bits___definition.html#ga711beadb293e4ef285bb813b2e9feb6d',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrh_5fafsel11_5f1_58',['GPIO_AFRH_AFSEL11_1',['../group___peripheral___registers___bits___definition.html#ga8ad64e530b4cf96c745f69ac97d23195',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrh_5fafsel11_5f2_59',['GPIO_AFRH_AFSEL11_2',['../group___peripheral___registers___bits___definition.html#ga3ffb839fbc0a35b148f17363553f6647',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrh_5fafsel11_5f3_60',['GPIO_AFRH_AFSEL11_3',['../group___peripheral___registers___bits___definition.html#ga570aa5e92e75568945191853f0196321',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrh_5fafsel11_5fmsk_61',['GPIO_AFRH_AFSEL11_Msk',['../group___peripheral___registers___bits___definition.html#ga76888c8d8080e47339e0fd2e69ab42d8',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrh_5fafsel11_5fpos_62',['GPIO_AFRH_AFSEL11_Pos',['../group___peripheral___registers___bits___definition.html#ga9f655e646b26d49e38053d9ee9cc064b',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrh_5fafsel12_63',['GPIO_AFRH_AFSEL12',['../group___peripheral___registers___bits___definition.html#ga0c12c0939e7fcc354e37d55b74afb351',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrh_5fafsel12_5f0_64',['GPIO_AFRH_AFSEL12_0',['../group___peripheral___registers___bits___definition.html#gaffe1b4dcd4e796a2e145df206f35d6ea',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrh_5fafsel12_5f1_65',['GPIO_AFRH_AFSEL12_1',['../group___peripheral___registers___bits___definition.html#gaac5933c2c73fec3d2f3c41d32fb64bfa',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrh_5fafsel12_5f2_66',['GPIO_AFRH_AFSEL12_2',['../group___peripheral___registers___bits___definition.html#ga3ed0f0c148e3c52bf041ab53af1d88bf',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrh_5fafsel12_5f3_67',['GPIO_AFRH_AFSEL12_3',['../group___peripheral___registers___bits___definition.html#gacbd6cfac7c23742a6e1fe120adfe3183',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrh_5fafsel12_5fmsk_68',['GPIO_AFRH_AFSEL12_Msk',['../group___peripheral___registers___bits___definition.html#gae162137694aa110fb89b9afeea1c648f',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrh_5fafsel12_5fpos_69',['GPIO_AFRH_AFSEL12_Pos',['../group___peripheral___registers___bits___definition.html#ga0dce1ce501e0b3b5e5e4b4961f7afda3',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrh_5fafsel13_70',['GPIO_AFRH_AFSEL13',['../group___peripheral___registers___bits___definition.html#ga60e9a3a49cdad6cd65d377fb675185da',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrh_5fafsel13_5f0_71',['GPIO_AFRH_AFSEL13_0',['../group___peripheral___registers___bits___definition.html#gab74ce92f856d5f687b069166f211ecaf',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrh_5fafsel13_5f1_72',['GPIO_AFRH_AFSEL13_1',['../group___peripheral___registers___bits___definition.html#ga1d2985f042e79fb320b402a6e1c425f7',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrh_5fafsel13_5f2_73',['GPIO_AFRH_AFSEL13_2',['../group___peripheral___registers___bits___definition.html#ga59cb8d2b8ca336c6c169c0e1a07cb2eb',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrh_5fafsel13_5f3_74',['GPIO_AFRH_AFSEL13_3',['../group___peripheral___registers___bits___definition.html#gac2ff66c2036fd651e7ae366db237b76c',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrh_5fafsel13_5fmsk_75',['GPIO_AFRH_AFSEL13_Msk',['../group___peripheral___registers___bits___definition.html#gacc533ac377beb113777896f0deb0ef91',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrh_5fafsel13_5fpos_76',['GPIO_AFRH_AFSEL13_Pos',['../group___peripheral___registers___bits___definition.html#ga65b195db19c1ca62ef95eed10c649180',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrh_5fafsel14_77',['GPIO_AFRH_AFSEL14',['../group___peripheral___registers___bits___definition.html#gae3d930c6c5ffa92e461a0190be4bff78',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrh_5fafsel14_5f0_78',['GPIO_AFRH_AFSEL14_0',['../group___peripheral___registers___bits___definition.html#gacf5b6ebd9c3a8039b46748dcbd3eda99',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrh_5fafsel14_5f1_79',['GPIO_AFRH_AFSEL14_1',['../group___peripheral___registers___bits___definition.html#ga21985995f6f22d63ba1170ee629bcf02',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrh_5fafsel14_5f2_80',['GPIO_AFRH_AFSEL14_2',['../group___peripheral___registers___bits___definition.html#ga0c98e75f198a3d84038029711c3f299f',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrh_5fafsel14_5f3_81',['GPIO_AFRH_AFSEL14_3',['../group___peripheral___registers___bits___definition.html#ga41d1c1c7ac6886975bca9cc8ef57c73d',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrh_5fafsel14_5fmsk_82',['GPIO_AFRH_AFSEL14_Msk',['../group___peripheral___registers___bits___definition.html#gae997df2b0bb50f310e7fd17df043e8e8',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrh_5fafsel14_5fpos_83',['GPIO_AFRH_AFSEL14_Pos',['../group___peripheral___registers___bits___definition.html#ga7fcd5b907f7ca9538dffe1aeb00d7942',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrh_5fafsel15_84',['GPIO_AFRH_AFSEL15',['../group___peripheral___registers___bits___definition.html#ga46417b0da710ef512ac4ceb95b3ab44a',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrh_5fafsel15_5f0_85',['GPIO_AFRH_AFSEL15_0',['../group___peripheral___registers___bits___definition.html#ga841bd65d5afd409fd7f2bf5f1e859348',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrh_5fafsel15_5f1_86',['GPIO_AFRH_AFSEL15_1',['../group___peripheral___registers___bits___definition.html#ga233f1ae0a856a18e7b706093c80a6274',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrh_5fafsel15_5f2_87',['GPIO_AFRH_AFSEL15_2',['../group___peripheral___registers___bits___definition.html#gadaae51ed82039c62ec075b42a192c861',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrh_5fafsel15_5f3_88',['GPIO_AFRH_AFSEL15_3',['../group___peripheral___registers___bits___definition.html#ga8699f7ff5369b8c20eaa32cfecbe7daf',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrh_5fafsel15_5fmsk_89',['GPIO_AFRH_AFSEL15_Msk',['../group___peripheral___registers___bits___definition.html#gaf94ca202e9ee8d766a5ee7794dba95b6',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrh_5fafsel15_5fpos_90',['GPIO_AFRH_AFSEL15_Pos',['../group___peripheral___registers___bits___definition.html#ga0a0ed32e0f197da7ea8856a58cebdb46',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrh_5fafsel8_91',['GPIO_AFRH_AFSEL8',['../group___peripheral___registers___bits___definition.html#ga6ed3881740613378329271150088f1b2',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrh_5fafsel8_5f0_92',['GPIO_AFRH_AFSEL8_0',['../group___peripheral___registers___bits___definition.html#ga72cc5ca956395dbb409019f45601727d',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrh_5fafsel8_5f1_93',['GPIO_AFRH_AFSEL8_1',['../group___peripheral___registers___bits___definition.html#ga23cb04d03ed3fc80a827dd4fcd092e92',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrh_5fafsel8_5f2_94',['GPIO_AFRH_AFSEL8_2',['../group___peripheral___registers___bits___definition.html#gaf0d2ccbadd52c0de148593218c735ed3',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrh_5fafsel8_5f3_95',['GPIO_AFRH_AFSEL8_3',['../group___peripheral___registers___bits___definition.html#gabd9fc9adc13e5e90df54b8885522f98e',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrh_5fafsel8_5fmsk_96',['GPIO_AFRH_AFSEL8_Msk',['../group___peripheral___registers___bits___definition.html#ga5be819e7ca1f69e2d5f6d63aaee056c2',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrh_5fafsel8_5fpos_97',['GPIO_AFRH_AFSEL8_Pos',['../group___peripheral___registers___bits___definition.html#ga2cdfdbcb5332d98e0202f4f86480736f',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrh_5fafsel9_98',['GPIO_AFRH_AFSEL9',['../group___peripheral___registers___bits___definition.html#gacff5a20b7c9f10be43364ff422bb40ef',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrh_5fafsel9_5f0_99',['GPIO_AFRH_AFSEL9_0',['../group___peripheral___registers___bits___definition.html#ga44f61f3cb607268196179fa0a28b051e',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrh_5fafsel9_5f1_100',['GPIO_AFRH_AFSEL9_1',['../group___peripheral___registers___bits___definition.html#ga6093967302f540000072f05d3e64bf6f',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrh_5fafsel9_5f2_101',['GPIO_AFRH_AFSEL9_2',['../group___peripheral___registers___bits___definition.html#gaa7d91556fe4f170bbd818e6d88f5bc56',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrh_5fafsel9_5f3_102',['GPIO_AFRH_AFSEL9_3',['../group___peripheral___registers___bits___definition.html#gab68b3750a95f3627dea9867fb5cf4689',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrh_5fafsel9_5fmsk_103',['GPIO_AFRH_AFSEL9_Msk',['../group___peripheral___registers___bits___definition.html#gafb779906c49372a9c0d7c8eaf7face71',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrh_5fafsel9_5fpos_104',['GPIO_AFRH_AFSEL9_Pos',['../group___peripheral___registers___bits___definition.html#gae9aeed0c87696c3a98e7e4fc3dc6dc80',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrl_5fafrl0_105',['GPIO_AFRL_AFRL0',['../group___peripheral___registers___bits___definition.html#gaf4af89daf61c25562733d281e9acde3d',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrl_5fafrl0_5f0_106',['GPIO_AFRL_AFRL0_0',['../group___peripheral___registers___bits___definition.html#gac3f152d808e8aa43362b108b1160c128',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrl_5fafrl0_5f1_107',['GPIO_AFRL_AFRL0_1',['../group___peripheral___registers___bits___definition.html#gabd77c2da1b416d80c239a024c8e4ef61',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrl_5fafrl0_5f2_108',['GPIO_AFRL_AFRL0_2',['../group___peripheral___registers___bits___definition.html#ga693446d17258b95fafb2685a5fe868ab',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrl_5fafrl0_5f3_109',['GPIO_AFRL_AFRL0_3',['../group___peripheral___registers___bits___definition.html#gac17d2fbadcaab82ce79836839278642c',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrl_5fafrl1_110',['GPIO_AFRL_AFRL1',['../group___peripheral___registers___bits___definition.html#ga122cbed720d27776f0cfa6dab1fbc84c',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrl_5fafrl1_5f0_111',['GPIO_AFRL_AFRL1_0',['../group___peripheral___registers___bits___definition.html#ga9f2f94b9a8f50f296dd0a20b110b2e93',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrl_5fafrl1_5f1_112',['GPIO_AFRL_AFRL1_1',['../group___peripheral___registers___bits___definition.html#gaf34ee437f14787a7bc240b13469f8d02',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrl_5fafrl1_5f2_113',['GPIO_AFRL_AFRL1_2',['../group___peripheral___registers___bits___definition.html#ga3b9d92f139b6f523c8ece0582caa9205',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrl_5fafrl1_5f3_114',['GPIO_AFRL_AFRL1_3',['../group___peripheral___registers___bits___definition.html#ga385ae9713490b8a47c63fb3f1d92eecf',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrl_5fafrl2_115',['GPIO_AFRL_AFRL2',['../group___peripheral___registers___bits___definition.html#gafda8ce333741832561e1e3e76abcee7a',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrl_5fafrl2_5f0_116',['GPIO_AFRL_AFRL2_0',['../group___peripheral___registers___bits___definition.html#ga3ae4ecfdc6739da7658d5618f949b4f0',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrl_5fafrl2_5f1_117',['GPIO_AFRL_AFRL2_1',['../group___peripheral___registers___bits___definition.html#gae6105e47f03d5c714f52753c721848e2',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrl_5fafrl2_5f2_118',['GPIO_AFRL_AFRL2_2',['../group___peripheral___registers___bits___definition.html#ga2d392ca99cf444404f329d5419febb1d',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrl_5fafrl2_5f3_119',['GPIO_AFRL_AFRL2_3',['../group___peripheral___registers___bits___definition.html#ga08baef06281ebf48156f43cd6727bd7f',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrl_5fafrl3_120',['GPIO_AFRL_AFRL3',['../group___peripheral___registers___bits___definition.html#gaee969704e28b7b0159838a8aec5f1e65',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrl_5fafrl3_5f0_121',['GPIO_AFRL_AFRL3_0',['../group___peripheral___registers___bits___definition.html#ga95865001c230cb9d6794a1a8faa53464',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrl_5fafrl3_5f1_122',['GPIO_AFRL_AFRL3_1',['../group___peripheral___registers___bits___definition.html#ga8669f979e8cde27c80e8b33fb5cc4f96',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrl_5fafrl3_5f2_123',['GPIO_AFRL_AFRL3_2',['../group___peripheral___registers___bits___definition.html#ga6c4a49fa8bb4a4e2cd8613be0fe8a4e3',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrl_5fafrl3_5f3_124',['GPIO_AFRL_AFRL3_3',['../group___peripheral___registers___bits___definition.html#ga14278231a30cffd346762047a69f4cc2',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrl_5fafrl4_125',['GPIO_AFRL_AFRL4',['../group___peripheral___registers___bits___definition.html#gac862d4f115fd881871356418943a4446',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrl_5fafrl4_5f0_126',['GPIO_AFRL_AFRL4_0',['../group___peripheral___registers___bits___definition.html#ga2138d6628f63ceff1b9340fe143e4309',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrl_5fafrl4_5f1_127',['GPIO_AFRL_AFRL4_1',['../group___peripheral___registers___bits___definition.html#gaa691f7acdc66a2d79e128264a7bd1a63',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrl_5fafrl4_5f2_128',['GPIO_AFRL_AFRL4_2',['../group___peripheral___registers___bits___definition.html#ga6b2c314441cd3d4841bdb1e3d5de9db5',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrl_5fafrl4_5f3_129',['GPIO_AFRL_AFRL4_3',['../group___peripheral___registers___bits___definition.html#gacab260848c23e7b1ea2777f0e4a40fc1',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrl_5fafrl5_130',['GPIO_AFRL_AFRL5',['../group___peripheral___registers___bits___definition.html#ga481f4065077c16365632e6a647cdcb4e',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrl_5fafrl5_5f0_131',['GPIO_AFRL_AFRL5_0',['../group___peripheral___registers___bits___definition.html#gabe45d3ec4c0a71d968112e7a65b5510d',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrl_5fafrl5_5f1_132',['GPIO_AFRL_AFRL5_1',['../group___peripheral___registers___bits___definition.html#ga6372195804d3e61723030fb0d9a2268f',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrl_5fafrl5_5f2_133',['GPIO_AFRL_AFRL5_2',['../group___peripheral___registers___bits___definition.html#gaf383c494976eda7fad4006b937a6f359',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrl_5fafrl5_5f3_134',['GPIO_AFRL_AFRL5_3',['../group___peripheral___registers___bits___definition.html#ga01dfdf9aa650eb4d3c06c6f7a4e79e44',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrl_5fafrl6_135',['GPIO_AFRL_AFRL6',['../group___peripheral___registers___bits___definition.html#gac87a55d05f6d16cbfbce6e04a2c6888e',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrl_5fafrl6_5f0_136',['GPIO_AFRL_AFRL6_0',['../group___peripheral___registers___bits___definition.html#gaa94adf1532fc4188a926ba7d366cc13e',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrl_5fafrl6_5f1_137',['GPIO_AFRL_AFRL6_1',['../group___peripheral___registers___bits___definition.html#ga1f5289d6b05cf1ed7959b89dfb4e64a0',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrl_5fafrl6_5f2_138',['GPIO_AFRL_AFRL6_2',['../group___peripheral___registers___bits___definition.html#gaaf8dff68b61d57bf6cbe6f22d76c5629',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrl_5fafrl6_5f3_139',['GPIO_AFRL_AFRL6_3',['../group___peripheral___registers___bits___definition.html#gaf05b72714d2577958fa5c2b5e871d223',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrl_5fafrl7_140',['GPIO_AFRL_AFRL7',['../group___peripheral___registers___bits___definition.html#ga97a41237468859702de7ea91dad62ed8',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrl_5fafrl7_5f0_141',['GPIO_AFRL_AFRL7_0',['../group___peripheral___registers___bits___definition.html#ga292b5b0e56572245d5c5d72fcdada9fa',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrl_5fafrl7_5f1_142',['GPIO_AFRL_AFRL7_1',['../group___peripheral___registers___bits___definition.html#ga6d5348d823ed82075ed48b74a36c9db2',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrl_5fafrl7_5f2_143',['GPIO_AFRL_AFRL7_2',['../group___peripheral___registers___bits___definition.html#gaf28527531ac7958b1de74f0883a53334',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrl_5fafrl7_5f3_144',['GPIO_AFRL_AFRL7_3',['../group___peripheral___registers___bits___definition.html#ga1adb4a490f9b5c323dba6e591f4131f6',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrl_5fafsel0_145',['GPIO_AFRL_AFSEL0',['../group___peripheral___registers___bits___definition.html#ga7ec251e186471ae09aeb3cb0aa788594',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrl_5fafsel0_5f0_146',['GPIO_AFRL_AFSEL0_0',['../group___peripheral___registers___bits___definition.html#ga3d64770b98ab6db5eee36068d6e0c45a',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrl_5fafsel0_5f1_147',['GPIO_AFRL_AFSEL0_1',['../group___peripheral___registers___bits___definition.html#gaabf16f4a3f9458d9576accc1695bed4a',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrl_5fafsel0_5f2_148',['GPIO_AFRL_AFSEL0_2',['../group___peripheral___registers___bits___definition.html#gab872e44f9df01f18e4f78cee45d5cf43',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrl_5fafsel0_5f3_149',['GPIO_AFRL_AFSEL0_3',['../group___peripheral___registers___bits___definition.html#ga5a83a0eb943535ea970419f7bb87fa52',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrl_5fafsel0_5fmsk_150',['GPIO_AFRL_AFSEL0_Msk',['../group___peripheral___registers___bits___definition.html#ga214860438ba3256833543e2f5018922f',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrl_5fafsel0_5fpos_151',['GPIO_AFRL_AFSEL0_Pos',['../group___peripheral___registers___bits___definition.html#gac06dd36e2c8c90fe9502bad271b2ee60',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrl_5fafsel1_152',['GPIO_AFRL_AFSEL1',['../group___peripheral___registers___bits___definition.html#ga9fbd174222a013c9a0e222fdd0888de2',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrl_5fafsel1_5f0_153',['GPIO_AFRL_AFSEL1_0',['../group___peripheral___registers___bits___definition.html#gae6834a1a64ce4c42bd71cdb0bc685f06',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrl_5fafsel1_5f1_154',['GPIO_AFRL_AFSEL1_1',['../group___peripheral___registers___bits___definition.html#gac4f1e8fe3cf48f2dcdd6cd96c88b5754',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrl_5fafsel1_5f2_155',['GPIO_AFRL_AFSEL1_2',['../group___peripheral___registers___bits___definition.html#gac38c620ad920142f38db8ef78674df56',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrl_5fafsel1_5f3_156',['GPIO_AFRL_AFSEL1_3',['../group___peripheral___registers___bits___definition.html#ga4ee3c6fd5280247ff5cb1e4c139ab85d',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrl_5fafsel1_5fmsk_157',['GPIO_AFRL_AFSEL1_Msk',['../group___peripheral___registers___bits___definition.html#ga5aac45598b88539da585e098fc93d68b',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrl_5fafsel1_5fpos_158',['GPIO_AFRL_AFSEL1_Pos',['../group___peripheral___registers___bits___definition.html#ga313ba8093d5a511430908d9adc90dc6a',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrl_5fafsel2_159',['GPIO_AFRL_AFSEL2',['../group___peripheral___registers___bits___definition.html#gaa9bc63205b8a09bd2ae7fb066058f3da',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrl_5fafsel2_5f0_160',['GPIO_AFRL_AFSEL2_0',['../group___peripheral___registers___bits___definition.html#ga566eef02569b14ba89745698e4c7f4cb',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrl_5fafsel2_5f1_161',['GPIO_AFRL_AFSEL2_1',['../group___peripheral___registers___bits___definition.html#ga99704f0bd6543a391b934faae9f86c0e',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrl_5fafsel2_5f2_162',['GPIO_AFRL_AFSEL2_2',['../group___peripheral___registers___bits___definition.html#ga8e90655a95edd288bda4552137310e7c',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrl_5fafsel2_5f3_163',['GPIO_AFRL_AFSEL2_3',['../group___peripheral___registers___bits___definition.html#ga2a2b8fe31b1620d99caaa0d5b00214fc',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrl_5fafsel2_5fmsk_164',['GPIO_AFRL_AFSEL2_Msk',['../group___peripheral___registers___bits___definition.html#ga729f1e6b663a55ce7f5cfbe1c71489a4',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrl_5fafsel2_5fpos_165',['GPIO_AFRL_AFSEL2_Pos',['../group___peripheral___registers___bits___definition.html#gae132b28ab4f67a9e90e7d15302aad49b',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrl_5fafsel3_166',['GPIO_AFRL_AFSEL3',['../group___peripheral___registers___bits___definition.html#gae0fb36c07eac3809b6a5baaee74ee426',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrl_5fafsel3_5f0_167',['GPIO_AFRL_AFSEL3_0',['../group___peripheral___registers___bits___definition.html#gaf0eb39bec095e2b4661141b20c1bd80d',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrl_5fafsel3_5f1_168',['GPIO_AFRL_AFSEL3_1',['../group___peripheral___registers___bits___definition.html#ga97101a6c182091257d9a86f38bbf8015',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrl_5fafsel3_5f2_169',['GPIO_AFRL_AFSEL3_2',['../group___peripheral___registers___bits___definition.html#gaf97dd08bfd9439ae9a8be2aae31572ab',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrl_5fafsel3_5f3_170',['GPIO_AFRL_AFSEL3_3',['../group___peripheral___registers___bits___definition.html#ga640b17198ae3a4dca834c93941bb459e',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrl_5fafsel3_5fmsk_171',['GPIO_AFRL_AFSEL3_Msk',['../group___peripheral___registers___bits___definition.html#gaf34ee7b30defbcad60d167a279a8c17d',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrl_5fafsel3_5fpos_172',['GPIO_AFRL_AFSEL3_Pos',['../group___peripheral___registers___bits___definition.html#ga0d9325a035cc3d6962d660d3f54a8df4',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrl_5fafsel4_173',['GPIO_AFRL_AFSEL4',['../group___peripheral___registers___bits___definition.html#ga728e20cadadaa3c5aa1c42c25356a9f4',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrl_5fafsel4_5f0_174',['GPIO_AFRL_AFSEL4_0',['../group___peripheral___registers___bits___definition.html#ga958dcb0150574251c77490397469d443',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrl_5fafsel4_5f1_175',['GPIO_AFRL_AFSEL4_1',['../group___peripheral___registers___bits___definition.html#ga89f30587f699e9b28347b41b1752d846',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrl_5fafsel4_5f2_176',['GPIO_AFRL_AFSEL4_2',['../group___peripheral___registers___bits___definition.html#gafeb379dcb35516d7744e8a7467aa9ddf',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrl_5fafsel4_5f3_177',['GPIO_AFRL_AFSEL4_3',['../group___peripheral___registers___bits___definition.html#ga3c7a684490eaf01f5e1bd29f89bebfb8',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrl_5fafsel4_5fmsk_178',['GPIO_AFRL_AFSEL4_Msk',['../group___peripheral___registers___bits___definition.html#ga47cfab1b5c3a37414bc4a6ac2cbd746a',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrl_5fafsel4_5fpos_179',['GPIO_AFRL_AFSEL4_Pos',['../group___peripheral___registers___bits___definition.html#ga723fbe4b28093f1837001110d8d44d36',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrl_5fafsel5_180',['GPIO_AFRL_AFSEL5',['../group___peripheral___registers___bits___definition.html#gad158052aa17b4bf12f9ad20b6e0c6d0c',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrl_5fafsel5_5f0_181',['GPIO_AFRL_AFSEL5_0',['../group___peripheral___registers___bits___definition.html#ga4fba4a0c264295148200fdbea3645efb',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrl_5fafsel5_5f1_182',['GPIO_AFRL_AFSEL5_1',['../group___peripheral___registers___bits___definition.html#gaf532421a6d6665eb9dd82752aa71bda6',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrl_5fafsel5_5f2_183',['GPIO_AFRL_AFSEL5_2',['../group___peripheral___registers___bits___definition.html#ga600caf3a081a223a0c9bbd22c1d65fd7',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrl_5fafsel5_5f3_184',['GPIO_AFRL_AFSEL5_3',['../group___peripheral___registers___bits___definition.html#ga3cf281224f66730f522948ce2f16a9dc',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrl_5fafsel5_5fmsk_185',['GPIO_AFRL_AFSEL5_Msk',['../group___peripheral___registers___bits___definition.html#gaf514d5f0c3456e2f7fc6d82f2b392051',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrl_5fafsel5_5fpos_186',['GPIO_AFRL_AFSEL5_Pos',['../group___peripheral___registers___bits___definition.html#gaf35270d71f53047d2a14d1047478c0ba',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrl_5fafsel6_187',['GPIO_AFRL_AFSEL6',['../group___peripheral___registers___bits___definition.html#ga893c83ab521d1bf15e71b20309d71503',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrl_5fafsel6_5f0_188',['GPIO_AFRL_AFSEL6_0',['../group___peripheral___registers___bits___definition.html#gae4eb2b4e77d1338ae80e889bb7f98159',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrl_5fafsel6_5f1_189',['GPIO_AFRL_AFSEL6_1',['../group___peripheral___registers___bits___definition.html#ga87ae4b89cf40e01fc3d0c1cca38db1de',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrl_5fafsel6_5f2_190',['GPIO_AFRL_AFSEL6_2',['../group___peripheral___registers___bits___definition.html#gace077c57cb72736ef5dca98052403b72',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrl_5fafsel6_5f3_191',['GPIO_AFRL_AFSEL6_3',['../group___peripheral___registers___bits___definition.html#ga0b1fee857fd7d1b412ed64b1c6572280',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrl_5fafsel6_5fmsk_192',['GPIO_AFRL_AFSEL6_Msk',['../group___peripheral___registers___bits___definition.html#gafb4e272e9b14944740fbe643542f0ade',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrl_5fafsel6_5fpos_193',['GPIO_AFRL_AFSEL6_Pos',['../group___peripheral___registers___bits___definition.html#gad9943c5aeeb649ab6bf33fde0d844803',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrl_5fafsel7_194',['GPIO_AFRL_AFSEL7',['../group___peripheral___registers___bits___definition.html#ga0128026ab2c8ed18da456aaf82827e11',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrl_5fafsel7_5f0_195',['GPIO_AFRL_AFSEL7_0',['../group___peripheral___registers___bits___definition.html#ga35641566dd5e2c3483d8ac494ff9e50d',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrl_5fafsel7_5f1_196',['GPIO_AFRL_AFSEL7_1',['../group___peripheral___registers___bits___definition.html#ga6a155fcc736492a694dac6b25c803f85',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrl_5fafsel7_5f2_197',['GPIO_AFRL_AFSEL7_2',['../group___peripheral___registers___bits___definition.html#ga31a4fdc80b155797db598779ae7a242f',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrl_5fafsel7_5f3_198',['GPIO_AFRL_AFSEL7_3',['../group___peripheral___registers___bits___definition.html#gac11328845c720331b1d6a12003b3f4d3',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrl_5fafsel7_5fmsk_199',['GPIO_AFRL_AFSEL7_Msk',['../group___peripheral___registers___bits___definition.html#gab3248acbb1bea59926db7edb98a245b0',1,'stm32f407xx_matlab.h']]], - ['gpio_5fafrl_5fafsel7_5fpos_200',['GPIO_AFRL_AFSEL7_Pos',['../group___peripheral___registers___bits___definition.html#ga2836c1149e06b2497f1f53518f1151f2',1,'stm32f407xx_matlab.h']]], - ['gpio_5fbrr_5fbr0_201',['GPIO_BRR_BR0',['../group___peripheral___registers___bits___definition.html#gad8acd11feb4223a7ca438effb3d926fc',1,'stm32f407xx_matlab.h']]], - ['gpio_5fbrr_5fbr0_5fmsk_202',['GPIO_BRR_BR0_Msk',['../group___peripheral___registers___bits___definition.html#gab8094099cbec15df24976405da11376f',1,'stm32f407xx_matlab.h']]], - ['gpio_5fbrr_5fbr0_5fpos_203',['GPIO_BRR_BR0_Pos',['../group___peripheral___registers___bits___definition.html#gaa4adfe8c79c3cf7e0fb7e8714ae15adf',1,'stm32f407xx_matlab.h']]], - ['gpio_5fbrr_5fbr1_204',['GPIO_BRR_BR1',['../group___peripheral___registers___bits___definition.html#ga68f94e96c502467ad528983494cb6645',1,'stm32f407xx_matlab.h']]], - ['gpio_5fbrr_5fbr10_205',['GPIO_BRR_BR10',['../group___peripheral___registers___bits___definition.html#ga8fe20398333e9f7e5c247e0bcfcd1d31',1,'stm32f407xx_matlab.h']]], - ['gpio_5fbrr_5fbr10_5fmsk_206',['GPIO_BRR_BR10_Msk',['../group___peripheral___registers___bits___definition.html#ga079add3e90617726dd8748c74abaf023',1,'stm32f407xx_matlab.h']]], - ['gpio_5fbrr_5fbr10_5fpos_207',['GPIO_BRR_BR10_Pos',['../group___peripheral___registers___bits___definition.html#ga08c89c18c00e1747d1392245f4fdeb19',1,'stm32f407xx_matlab.h']]], - ['gpio_5fbrr_5fbr11_208',['GPIO_BRR_BR11',['../group___peripheral___registers___bits___definition.html#gac65c4bf495800254168edce220f12294',1,'stm32f407xx_matlab.h']]], - ['gpio_5fbrr_5fbr11_5fmsk_209',['GPIO_BRR_BR11_Msk',['../group___peripheral___registers___bits___definition.html#gaad2be9a16fb6670ebb3492795bf6866a',1,'stm32f407xx_matlab.h']]], - ['gpio_5fbrr_5fbr11_5fpos_210',['GPIO_BRR_BR11_Pos',['../group___peripheral___registers___bits___definition.html#ga3a92027f04f25fd1b7ec7ad660052b42',1,'stm32f407xx_matlab.h']]], - ['gpio_5fbrr_5fbr12_211',['GPIO_BRR_BR12',['../group___peripheral___registers___bits___definition.html#ga443c4943581f7590d706b183fb47250e',1,'stm32f407xx_matlab.h']]], - ['gpio_5fbrr_5fbr12_5fmsk_212',['GPIO_BRR_BR12_Msk',['../group___peripheral___registers___bits___definition.html#gaed3507b082d551500536f8c0c3929dca',1,'stm32f407xx_matlab.h']]], - ['gpio_5fbrr_5fbr12_5fpos_213',['GPIO_BRR_BR12_Pos',['../group___peripheral___registers___bits___definition.html#ga372754b6a71cbf3d09b959b2eef5fa7f',1,'stm32f407xx_matlab.h']]], - ['gpio_5fbrr_5fbr13_214',['GPIO_BRR_BR13',['../group___peripheral___registers___bits___definition.html#ga41f1e586a459fe54089921daed6b99cc',1,'stm32f407xx_matlab.h']]], - ['gpio_5fbrr_5fbr13_5fmsk_215',['GPIO_BRR_BR13_Msk',['../group___peripheral___registers___bits___definition.html#ga53217d2a5609f35d6b029a5e1eaf2e5f',1,'stm32f407xx_matlab.h']]], - ['gpio_5fbrr_5fbr13_5fpos_216',['GPIO_BRR_BR13_Pos',['../group___peripheral___registers___bits___definition.html#ga2dd4f25b9a855fb50ddc394a2384ccf2',1,'stm32f407xx_matlab.h']]], - ['gpio_5fbrr_5fbr14_217',['GPIO_BRR_BR14',['../group___peripheral___registers___bits___definition.html#ga4a77aa07922b7541f1e1c936a6651713',1,'stm32f407xx_matlab.h']]], - ['gpio_5fbrr_5fbr14_5fmsk_218',['GPIO_BRR_BR14_Msk',['../group___peripheral___registers___bits___definition.html#ga239abb28695da394a23f119ddd5aa724',1,'stm32f407xx_matlab.h']]], - ['gpio_5fbrr_5fbr14_5fpos_219',['GPIO_BRR_BR14_Pos',['../group___peripheral___registers___bits___definition.html#ga10e2ac4dac68a55a7c574736a2964312',1,'stm32f407xx_matlab.h']]], - ['gpio_5fbrr_5fbr15_220',['GPIO_BRR_BR15',['../group___peripheral___registers___bits___definition.html#gab2ab1e0d0902e871836ae13d70c566df',1,'stm32f407xx_matlab.h']]], - ['gpio_5fbrr_5fbr15_5fmsk_221',['GPIO_BRR_BR15_Msk',['../group___peripheral___registers___bits___definition.html#ga032413396d570a1f3041385e84ab009e',1,'stm32f407xx_matlab.h']]], - ['gpio_5fbrr_5fbr15_5fpos_222',['GPIO_BRR_BR15_Pos',['../group___peripheral___registers___bits___definition.html#ga7d13b2c8e758203e32008267734f961f',1,'stm32f407xx_matlab.h']]], - ['gpio_5fbrr_5fbr1_5fmsk_223',['GPIO_BRR_BR1_Msk',['../group___peripheral___registers___bits___definition.html#gad742debac1d7e18afd61fda41eda1454',1,'stm32f407xx_matlab.h']]], - ['gpio_5fbrr_5fbr1_5fpos_224',['GPIO_BRR_BR1_Pos',['../group___peripheral___registers___bits___definition.html#ga483e475a913145601000fc57ef63afcd',1,'stm32f407xx_matlab.h']]], - ['gpio_5fbrr_5fbr2_225',['GPIO_BRR_BR2',['../group___peripheral___registers___bits___definition.html#gaeebe4dddede0f14e00885b70c09bbd09',1,'stm32f407xx_matlab.h']]], - ['gpio_5fbrr_5fbr2_5fmsk_226',['GPIO_BRR_BR2_Msk',['../group___peripheral___registers___bits___definition.html#ga91d9b343fe4038316557b5665ad90895',1,'stm32f407xx_matlab.h']]], - ['gpio_5fbrr_5fbr2_5fpos_227',['GPIO_BRR_BR2_Pos',['../group___peripheral___registers___bits___definition.html#gadb13164bb973d1a4591ca626903e66b7',1,'stm32f407xx_matlab.h']]], - ['gpio_5fbrr_5fbr3_228',['GPIO_BRR_BR3',['../group___peripheral___registers___bits___definition.html#ga95b3047fcdfe9269f5a94b6412ec6a3c',1,'stm32f407xx_matlab.h']]], - ['gpio_5fbrr_5fbr3_5fmsk_229',['GPIO_BRR_BR3_Msk',['../group___peripheral___registers___bits___definition.html#ga59b86cdd805087a6aa27886a1c8f3f64',1,'stm32f407xx_matlab.h']]], - ['gpio_5fbrr_5fbr3_5fpos_230',['GPIO_BRR_BR3_Pos',['../group___peripheral___registers___bits___definition.html#gac814288cc968b01d3e7ee1b6d340a8dd',1,'stm32f407xx_matlab.h']]], - ['gpio_5fbrr_5fbr4_231',['GPIO_BRR_BR4',['../group___peripheral___registers___bits___definition.html#ga8fc7d79f0103f892f8c3a87d8038525a',1,'stm32f407xx_matlab.h']]], - ['gpio_5fbrr_5fbr4_5fmsk_232',['GPIO_BRR_BR4_Msk',['../group___peripheral___registers___bits___definition.html#ga84709afb9f2b311db9916987f5b62803',1,'stm32f407xx_matlab.h']]], - ['gpio_5fbrr_5fbr4_5fpos_233',['GPIO_BRR_BR4_Pos',['../group___peripheral___registers___bits___definition.html#gac9f7fabe9e3187ac070c2ed6e4ae7725',1,'stm32f407xx_matlab.h']]], - ['gpio_5fbrr_5fbr5_234',['GPIO_BRR_BR5',['../group___peripheral___registers___bits___definition.html#ga6cc7663eaa1496185041af93b4ff808b',1,'stm32f407xx_matlab.h']]], - ['gpio_5fbrr_5fbr5_5fmsk_235',['GPIO_BRR_BR5_Msk',['../group___peripheral___registers___bits___definition.html#ga50fd21ca329283e8f79675f8195d6a7e',1,'stm32f407xx_matlab.h']]], - ['gpio_5fbrr_5fbr5_5fpos_236',['GPIO_BRR_BR5_Pos',['../group___peripheral___registers___bits___definition.html#ga6b24f01f67db366ff6adf86f5f940669',1,'stm32f407xx_matlab.h']]], - ['gpio_5fbrr_5fbr6_237',['GPIO_BRR_BR6',['../group___peripheral___registers___bits___definition.html#gafa84d5cb9d0a0a945389ad0fef07eb2a',1,'stm32f407xx_matlab.h']]], - ['gpio_5fbrr_5fbr6_5fmsk_238',['GPIO_BRR_BR6_Msk',['../group___peripheral___registers___bits___definition.html#gae29f8525d511f39db8b6ac9efbae9ecc',1,'stm32f407xx_matlab.h']]], - ['gpio_5fbrr_5fbr6_5fpos_239',['GPIO_BRR_BR6_Pos',['../group___peripheral___registers___bits___definition.html#ga22e8aaa7e05c2f824d6fc1ae83f04913',1,'stm32f407xx_matlab.h']]], - ['gpio_5fbrr_5fbr7_240',['GPIO_BRR_BR7',['../group___peripheral___registers___bits___definition.html#ga5110afe1f5bda4fde7983b447ce162c4',1,'stm32f407xx_matlab.h']]], - ['gpio_5fbrr_5fbr7_5fmsk_241',['GPIO_BRR_BR7_Msk',['../group___peripheral___registers___bits___definition.html#gae40c636136e51fffad265559938cb9f0',1,'stm32f407xx_matlab.h']]], - ['gpio_5fbrr_5fbr7_5fpos_242',['GPIO_BRR_BR7_Pos',['../group___peripheral___registers___bits___definition.html#ga321d9cc2bc9fd4601694780ac4fcc7f6',1,'stm32f407xx_matlab.h']]], - ['gpio_5fbrr_5fbr8_243',['GPIO_BRR_BR8',['../group___peripheral___registers___bits___definition.html#gae1560a3457fcec47c6f1871cf225557e',1,'stm32f407xx_matlab.h']]], - ['gpio_5fbrr_5fbr8_5fmsk_244',['GPIO_BRR_BR8_Msk',['../group___peripheral___registers___bits___definition.html#gab9cd1191844e03a1aa271bd08e608e77',1,'stm32f407xx_matlab.h']]], - ['gpio_5fbrr_5fbr8_5fpos_245',['GPIO_BRR_BR8_Pos',['../group___peripheral___registers___bits___definition.html#gaf45a746e5bb2a1c132093a2844d22683',1,'stm32f407xx_matlab.h']]], - ['gpio_5fbrr_5fbr9_246',['GPIO_BRR_BR9',['../group___peripheral___registers___bits___definition.html#ga248ac798aa8fdd42573fa6ff4762ba58',1,'stm32f407xx_matlab.h']]], - ['gpio_5fbrr_5fbr9_5fmsk_247',['GPIO_BRR_BR9_Msk',['../group___peripheral___registers___bits___definition.html#ga0621db455e4164529a8e632bb413055d',1,'stm32f407xx_matlab.h']]], - ['gpio_5fbrr_5fbr9_5fpos_248',['GPIO_BRR_BR9_Pos',['../group___peripheral___registers___bits___definition.html#ga84ae3878f9088d349453430a79e26810',1,'stm32f407xx_matlab.h']]], - ['gpio_5fbsrr_5fbr0_249',['GPIO_BSRR_BR0',['../group___peripheral___registers___bits___definition.html#ga44316fb208a551d63550ab435a65faaf',1,'stm32f407xx_matlab.h']]], - ['gpio_5fbsrr_5fbr0_5fmsk_250',['GPIO_BSRR_BR0_Msk',['../group___peripheral___registers___bits___definition.html#gac6ca69cbc7e23bf313dda10288ce21f5',1,'stm32f407xx_matlab.h']]], - ['gpio_5fbsrr_5fbr0_5fpos_251',['GPIO_BSRR_BR0_Pos',['../group___peripheral___registers___bits___definition.html#ga9b9e4440bb44a4ab919e9a0171af788b',1,'stm32f407xx_matlab.h']]], - ['gpio_5fbsrr_5fbr1_252',['GPIO_BSRR_BR1',['../group___peripheral___registers___bits___definition.html#ga855ce6a1019d453bd1fbe9f61b5531b8',1,'stm32f407xx_matlab.h']]], - ['gpio_5fbsrr_5fbr10_253',['GPIO_BSRR_BR10',['../group___peripheral___registers___bits___definition.html#ga98581ac23be9f4fa003686d2ea523a81',1,'stm32f407xx_matlab.h']]], - ['gpio_5fbsrr_5fbr10_5fmsk_254',['GPIO_BSRR_BR10_Msk',['../group___peripheral___registers___bits___definition.html#gae3f93f6e94ae0d842e5b0cda9ba6a1cd',1,'stm32f407xx_matlab.h']]], - ['gpio_5fbsrr_5fbr10_5fpos_255',['GPIO_BSRR_BR10_Pos',['../group___peripheral___registers___bits___definition.html#ga968f494c3928ba28bfa7c87da5f2cbaa',1,'stm32f407xx_matlab.h']]], - ['gpio_5fbsrr_5fbr11_256',['GPIO_BSRR_BR11',['../group___peripheral___registers___bits___definition.html#gacedacd6c3e840a8172269cac3dbb550b',1,'stm32f407xx_matlab.h']]], - ['gpio_5fbsrr_5fbr11_5fmsk_257',['GPIO_BSRR_BR11_Msk',['../group___peripheral___registers___bits___definition.html#ga9f483f67fbc5614c010aa147e9ce6b3f',1,'stm32f407xx_matlab.h']]], - ['gpio_5fbsrr_5fbr11_5fpos_258',['GPIO_BSRR_BR11_Pos',['../group___peripheral___registers___bits___definition.html#ga8b421b338b145649e8937806472a59c6',1,'stm32f407xx_matlab.h']]], - ['gpio_5fbsrr_5fbr12_259',['GPIO_BSRR_BR12',['../group___peripheral___registers___bits___definition.html#ga4622e78de418b59cd4199928801b6958',1,'stm32f407xx_matlab.h']]], - ['gpio_5fbsrr_5fbr12_5fmsk_260',['GPIO_BSRR_BR12_Msk',['../group___peripheral___registers___bits___definition.html#gaa10f5ee9aeb2eefb25fd195e472c0de8',1,'stm32f407xx_matlab.h']]], - ['gpio_5fbsrr_5fbr12_5fpos_261',['GPIO_BSRR_BR12_Pos',['../group___peripheral___registers___bits___definition.html#ga79f141572b1c065dcabbc7ddfe4092f2',1,'stm32f407xx_matlab.h']]], - ['gpio_5fbsrr_5fbr13_262',['GPIO_BSRR_BR13',['../group___peripheral___registers___bits___definition.html#ga292c1d0172620e0454ccc36f91f0c6ea',1,'stm32f407xx_matlab.h']]], - ['gpio_5fbsrr_5fbr13_5fmsk_263',['GPIO_BSRR_BR13_Msk',['../group___peripheral___registers___bits___definition.html#ga7d000805bb6f4ad68ec73159df771422',1,'stm32f407xx_matlab.h']]], - ['gpio_5fbsrr_5fbr13_5fpos_264',['GPIO_BSRR_BR13_Pos',['../group___peripheral___registers___bits___definition.html#ga53a07a77a4bb0457b13abfee48ed3e39',1,'stm32f407xx_matlab.h']]], - ['gpio_5fbsrr_5fbr14_265',['GPIO_BSRR_BR14',['../group___peripheral___registers___bits___definition.html#ga32477ac5ab4f5c7257ca332bb691b7cf',1,'stm32f407xx_matlab.h']]], - ['gpio_5fbsrr_5fbr14_5fmsk_266',['GPIO_BSRR_BR14_Msk',['../group___peripheral___registers___bits___definition.html#ga1ad1816ec382b6ef6e952cef1408933f',1,'stm32f407xx_matlab.h']]], - ['gpio_5fbsrr_5fbr14_5fpos_267',['GPIO_BSRR_BR14_Pos',['../group___peripheral___registers___bits___definition.html#ga1e6b3f0c1a866cd39319f28cacbb768e',1,'stm32f407xx_matlab.h']]], - ['gpio_5fbsrr_5fbr15_268',['GPIO_BSRR_BR15',['../group___peripheral___registers___bits___definition.html#ga3c6d612adeaae9b26d0ea4af74ffe1cd',1,'stm32f407xx_matlab.h']]], - ['gpio_5fbsrr_5fbr15_5fmsk_269',['GPIO_BSRR_BR15_Msk',['../group___peripheral___registers___bits___definition.html#gaf8c00dff452eea9a285e36a81c5abd79',1,'stm32f407xx_matlab.h']]], - ['gpio_5fbsrr_5fbr15_5fpos_270',['GPIO_BSRR_BR15_Pos',['../group___peripheral___registers___bits___definition.html#ga30d885f9a72889c6f1070b6da4d4d782',1,'stm32f407xx_matlab.h']]], - ['gpio_5fbsrr_5fbr1_5fmsk_271',['GPIO_BSRR_BR1_Msk',['../group___peripheral___registers___bits___definition.html#gac9890be2a151b0b31119eba03b36b9df',1,'stm32f407xx_matlab.h']]], - ['gpio_5fbsrr_5fbr1_5fpos_272',['GPIO_BSRR_BR1_Pos',['../group___peripheral___registers___bits___definition.html#ga075d239db694cea8f30c70534ddf7be9',1,'stm32f407xx_matlab.h']]], - ['gpio_5fbsrr_5fbr2_273',['GPIO_BSRR_BR2',['../group___peripheral___registers___bits___definition.html#ga7ac2103861a8ab0c8c8fed5e3bf7db0a',1,'stm32f407xx_matlab.h']]], - ['gpio_5fbsrr_5fbr2_5fmsk_274',['GPIO_BSRR_BR2_Msk',['../group___peripheral___registers___bits___definition.html#gaca8d1db9b985749bcdcc4f83d80e25b1',1,'stm32f407xx_matlab.h']]], - ['gpio_5fbsrr_5fbr2_5fpos_275',['GPIO_BSRR_BR2_Pos',['../group___peripheral___registers___bits___definition.html#ga2c5825e38ef02071bf0d888ab636d241',1,'stm32f407xx_matlab.h']]], - ['gpio_5fbsrr_5fbr3_276',['GPIO_BSRR_BR3',['../group___peripheral___registers___bits___definition.html#gaf256a26094e33026f7f575f04d0e05c9',1,'stm32f407xx_matlab.h']]], - ['gpio_5fbsrr_5fbr3_5fmsk_277',['GPIO_BSRR_BR3_Msk',['../group___peripheral___registers___bits___definition.html#gad7045c8361aeed94f72ed591c604d1f1',1,'stm32f407xx_matlab.h']]], - ['gpio_5fbsrr_5fbr3_5fpos_278',['GPIO_BSRR_BR3_Pos',['../group___peripheral___registers___bits___definition.html#ga1ef6b53609ca5d188a6916d8574d6030',1,'stm32f407xx_matlab.h']]], - ['gpio_5fbsrr_5fbr4_279',['GPIO_BSRR_BR4',['../group___peripheral___registers___bits___definition.html#gac84f66118397bb661ad9edfdd50432f0',1,'stm32f407xx_matlab.h']]], - ['gpio_5fbsrr_5fbr4_5fmsk_280',['GPIO_BSRR_BR4_Msk',['../group___peripheral___registers___bits___definition.html#ga94341de3b04731a0df5c530c572dad7f',1,'stm32f407xx_matlab.h']]], - ['gpio_5fbsrr_5fbr4_5fpos_281',['GPIO_BSRR_BR4_Pos',['../group___peripheral___registers___bits___definition.html#ga71bbd49dad3b3dcd6ecb60b0fb1fa8eb',1,'stm32f407xx_matlab.h']]], - ['gpio_5fbsrr_5fbr5_282',['GPIO_BSRR_BR5',['../group___peripheral___registers___bits___definition.html#ga09a777f006ef68641e80110f20117a8d',1,'stm32f407xx_matlab.h']]], - ['gpio_5fbsrr_5fbr5_5fmsk_283',['GPIO_BSRR_BR5_Msk',['../group___peripheral___registers___bits___definition.html#ga4d366ba8f09d9211e25c5e76b56a91af',1,'stm32f407xx_matlab.h']]], - ['gpio_5fbsrr_5fbr5_5fpos_284',['GPIO_BSRR_BR5_Pos',['../group___peripheral___registers___bits___definition.html#gaa565b7acd495e70be1b68204ef2910db',1,'stm32f407xx_matlab.h']]], - ['gpio_5fbsrr_5fbr6_285',['GPIO_BSRR_BR6',['../group___peripheral___registers___bits___definition.html#ga8695c8bfcc32bda2806805339db1e8ce',1,'stm32f407xx_matlab.h']]], - ['gpio_5fbsrr_5fbr6_5fmsk_286',['GPIO_BSRR_BR6_Msk',['../group___peripheral___registers___bits___definition.html#ga354a942cded8f779316613b5a73b71ad',1,'stm32f407xx_matlab.h']]], - ['gpio_5fbsrr_5fbr6_5fpos_287',['GPIO_BSRR_BR6_Pos',['../group___peripheral___registers___bits___definition.html#gafce8dd4c2ed3764a234fc40ad192ae03',1,'stm32f407xx_matlab.h']]], - ['gpio_5fbsrr_5fbr7_288',['GPIO_BSRR_BR7',['../group___peripheral___registers___bits___definition.html#gaba577e8f2650976f219ad7ad93244f8a',1,'stm32f407xx_matlab.h']]], - ['gpio_5fbsrr_5fbr7_5fmsk_289',['GPIO_BSRR_BR7_Msk',['../group___peripheral___registers___bits___definition.html#ga6b90d1d54ad1a0def096663cfe9cbd74',1,'stm32f407xx_matlab.h']]], - ['gpio_5fbsrr_5fbr7_5fpos_290',['GPIO_BSRR_BR7_Pos',['../group___peripheral___registers___bits___definition.html#ga34e114c3d131dbb2abc05837b9c20fff',1,'stm32f407xx_matlab.h']]], - ['gpio_5fbsrr_5fbr8_291',['GPIO_BSRR_BR8',['../group___peripheral___registers___bits___definition.html#gaaedbc146cc7659d51bc5f472d3a405ee',1,'stm32f407xx_matlab.h']]], - ['gpio_5fbsrr_5fbr8_5fmsk_292',['GPIO_BSRR_BR8_Msk',['../group___peripheral___registers___bits___definition.html#ga5460b708647c1a9f742c0ff0d5bcb17b',1,'stm32f407xx_matlab.h']]], - ['gpio_5fbsrr_5fbr8_5fpos_293',['GPIO_BSRR_BR8_Pos',['../group___peripheral___registers___bits___definition.html#gadebc6e8a656a3adbff46f398b5bcb3d4',1,'stm32f407xx_matlab.h']]], - ['gpio_5fbsrr_5fbr9_294',['GPIO_BSRR_BR9',['../group___peripheral___registers___bits___definition.html#gaa3e0c779115c59cb98e021ede5605df3',1,'stm32f407xx_matlab.h']]], - ['gpio_5fbsrr_5fbr9_5fmsk_295',['GPIO_BSRR_BR9_Msk',['../group___peripheral___registers___bits___definition.html#ga4aa6d3943ec6a8d96dd855f436ab8e19',1,'stm32f407xx_matlab.h']]], - ['gpio_5fbsrr_5fbr9_5fpos_296',['GPIO_BSRR_BR9_Pos',['../group___peripheral___registers___bits___definition.html#ga13d98b977fc86581e566299bd363176d',1,'stm32f407xx_matlab.h']]], - ['gpio_5fbsrr_5fbr_5f0_297',['GPIO_BSRR_BR_0',['../group___peripheral___registers___bits___definition.html#ga831554de814ae2941c7f527ed6b0a742',1,'stm32f407xx_matlab.h']]], - ['gpio_5fbsrr_5fbr_5f1_298',['GPIO_BSRR_BR_1',['../group___peripheral___registers___bits___definition.html#ga6cf488fcb38fc660f7e3d1820a12ae07',1,'stm32f407xx_matlab.h']]], - ['gpio_5fbsrr_5fbr_5f10_299',['GPIO_BSRR_BR_10',['../group___peripheral___registers___bits___definition.html#ga7c14a1c84cc91ff1d21b6802cda7d7ef',1,'stm32f407xx_matlab.h']]], - ['gpio_5fbsrr_5fbr_5f11_300',['GPIO_BSRR_BR_11',['../group___peripheral___registers___bits___definition.html#ga498185a76dcc2305113c5d168c2844d9',1,'stm32f407xx_matlab.h']]], - ['gpio_5fbsrr_5fbr_5f12_301',['GPIO_BSRR_BR_12',['../group___peripheral___registers___bits___definition.html#ga222460b26eaba7d333bb4d4ae9426aff',1,'stm32f407xx_matlab.h']]], - ['gpio_5fbsrr_5fbr_5f13_302',['GPIO_BSRR_BR_13',['../group___peripheral___registers___bits___definition.html#gaca2dc3bd09745f8de6c6788fb1d106af',1,'stm32f407xx_matlab.h']]], - ['gpio_5fbsrr_5fbr_5f14_303',['GPIO_BSRR_BR_14',['../group___peripheral___registers___bits___definition.html#ga67c96f72bdd15516e22097a3a3dad5f1',1,'stm32f407xx_matlab.h']]], - ['gpio_5fbsrr_5fbr_5f15_304',['GPIO_BSRR_BR_15',['../group___peripheral___registers___bits___definition.html#ga6eaa59f6afa3fcebaf2a27c31ae38544',1,'stm32f407xx_matlab.h']]], - ['gpio_5fbsrr_5fbr_5f2_305',['GPIO_BSRR_BR_2',['../group___peripheral___registers___bits___definition.html#ga7fe0f9386b50b899fdf1f9008c54f893',1,'stm32f407xx_matlab.h']]], - ['gpio_5fbsrr_5fbr_5f3_306',['GPIO_BSRR_BR_3',['../group___peripheral___registers___bits___definition.html#ga42b377f0c5f564fb39480afe43ee8796',1,'stm32f407xx_matlab.h']]], - ['gpio_5fbsrr_5fbr_5f4_307',['GPIO_BSRR_BR_4',['../group___peripheral___registers___bits___definition.html#gab723c0327da5fb41fe366416b7d61d88',1,'stm32f407xx_matlab.h']]], - ['gpio_5fbsrr_5fbr_5f5_308',['GPIO_BSRR_BR_5',['../group___peripheral___registers___bits___definition.html#ga0d6d8644953029e183eda4404fe9bd27',1,'stm32f407xx_matlab.h']]], - ['gpio_5fbsrr_5fbr_5f6_309',['GPIO_BSRR_BR_6',['../group___peripheral___registers___bits___definition.html#ga59e4a03667e8a750fd2e775edc44ecbe',1,'stm32f407xx_matlab.h']]], - ['gpio_5fbsrr_5fbr_5f7_310',['GPIO_BSRR_BR_7',['../group___peripheral___registers___bits___definition.html#gafca85d377fe820e5099d870342d634a8',1,'stm32f407xx_matlab.h']]], - ['gpio_5fbsrr_5fbr_5f8_311',['GPIO_BSRR_BR_8',['../group___peripheral___registers___bits___definition.html#gab02c6e6e879085fd8912facf86d822cd',1,'stm32f407xx_matlab.h']]], - ['gpio_5fbsrr_5fbr_5f9_312',['GPIO_BSRR_BR_9',['../group___peripheral___registers___bits___definition.html#ga47ff03b3d52a7f40ae15cc167b34cc58',1,'stm32f407xx_matlab.h']]], - ['gpio_5fbsrr_5fbs0_313',['GPIO_BSRR_BS0',['../group___peripheral___registers___bits___definition.html#ga4bdfbe2a618de42c420de923b2f8507d',1,'stm32f407xx_matlab.h']]], - ['gpio_5fbsrr_5fbs0_5fmsk_314',['GPIO_BSRR_BS0_Msk',['../group___peripheral___registers___bits___definition.html#ga758aadb3c036759a162542216f98fcbc',1,'stm32f407xx_matlab.h']]], - ['gpio_5fbsrr_5fbs0_5fpos_315',['GPIO_BSRR_BS0_Pos',['../group___peripheral___registers___bits___definition.html#ga409d8650af1aa0e1958cc1ed2f96acda',1,'stm32f407xx_matlab.h']]], - ['gpio_5fbsrr_5fbs1_316',['GPIO_BSRR_BS1',['../group___peripheral___registers___bits___definition.html#ga316604d9223fee0c0591b58bd42b5f51',1,'stm32f407xx_matlab.h']]], - ['gpio_5fbsrr_5fbs10_317',['GPIO_BSRR_BS10',['../group___peripheral___registers___bits___definition.html#gadbe42933da56edaa62f89d6fb5093b32',1,'stm32f407xx_matlab.h']]], - ['gpio_5fbsrr_5fbs10_5fmsk_318',['GPIO_BSRR_BS10_Msk',['../group___peripheral___registers___bits___definition.html#ga2a8f9979581623c5ee8a3b16be563cd1',1,'stm32f407xx_matlab.h']]], - ['gpio_5fbsrr_5fbs10_5fpos_319',['GPIO_BSRR_BS10_Pos',['../group___peripheral___registers___bits___definition.html#gaf85195c9fb5642687151366b0f363441',1,'stm32f407xx_matlab.h']]], - ['gpio_5fbsrr_5fbs11_320',['GPIO_BSRR_BS11',['../group___peripheral___registers___bits___definition.html#ga71b06aba868da67827335c823cde772c',1,'stm32f407xx_matlab.h']]], - ['gpio_5fbsrr_5fbs11_5fmsk_321',['GPIO_BSRR_BS11_Msk',['../group___peripheral___registers___bits___definition.html#ga5d224601eb9ec2476451efe136693769',1,'stm32f407xx_matlab.h']]], - ['gpio_5fbsrr_5fbs11_5fpos_322',['GPIO_BSRR_BS11_Pos',['../group___peripheral___registers___bits___definition.html#ga7f79cf6b45de75813ed9d2af64f0d91b',1,'stm32f407xx_matlab.h']]], - ['gpio_5fbsrr_5fbs12_323',['GPIO_BSRR_BS12',['../group___peripheral___registers___bits___definition.html#ga34dec3bc91096fccb3339f2d6d181846',1,'stm32f407xx_matlab.h']]], - ['gpio_5fbsrr_5fbs12_5fmsk_324',['GPIO_BSRR_BS12_Msk',['../group___peripheral___registers___bits___definition.html#ga8cc01661d2dec2e9dd4b02528e271393',1,'stm32f407xx_matlab.h']]], - ['gpio_5fbsrr_5fbs12_5fpos_325',['GPIO_BSRR_BS12_Pos',['../group___peripheral___registers___bits___definition.html#ga4302c8e25dd2711d37262b73865f3c19',1,'stm32f407xx_matlab.h']]], - ['gpio_5fbsrr_5fbs13_326',['GPIO_BSRR_BS13',['../group___peripheral___registers___bits___definition.html#ga1ea853befe5a2a238f0e0fe5d6c41b9c',1,'stm32f407xx_matlab.h']]], - ['gpio_5fbsrr_5fbs13_5fmsk_327',['GPIO_BSRR_BS13_Msk',['../group___peripheral___registers___bits___definition.html#gaed57c94725261a35387ef04c9675cdbe',1,'stm32f407xx_matlab.h']]], - ['gpio_5fbsrr_5fbs13_5fpos_328',['GPIO_BSRR_BS13_Pos',['../group___peripheral___registers___bits___definition.html#ga5fe11d923932261f904c089da78e7ebc',1,'stm32f407xx_matlab.h']]], - ['gpio_5fbsrr_5fbs14_329',['GPIO_BSRR_BS14',['../group___peripheral___registers___bits___definition.html#ga24e32d8f8af43a171ed1a4c7eb202d17',1,'stm32f407xx_matlab.h']]], - ['gpio_5fbsrr_5fbs14_5fmsk_330',['GPIO_BSRR_BS14_Msk',['../group___peripheral___registers___bits___definition.html#gaeaaedec226989e8048f5cbde2de6c1c5',1,'stm32f407xx_matlab.h']]], - ['gpio_5fbsrr_5fbs14_5fpos_331',['GPIO_BSRR_BS14_Pos',['../group___peripheral___registers___bits___definition.html#ga7c86de2a9b2e7394040a65bf114131bc',1,'stm32f407xx_matlab.h']]], - ['gpio_5fbsrr_5fbs15_332',['GPIO_BSRR_BS15',['../group___peripheral___registers___bits___definition.html#gad8427fb5c9074e51fbf27480a6a65a80',1,'stm32f407xx_matlab.h']]], - ['gpio_5fbsrr_5fbs15_5fmsk_333',['GPIO_BSRR_BS15_Msk',['../group___peripheral___registers___bits___definition.html#gab40b26153e5c50ae45ebc6deb06cc0fb',1,'stm32f407xx_matlab.h']]], - ['gpio_5fbsrr_5fbs15_5fpos_334',['GPIO_BSRR_BS15_Pos',['../group___peripheral___registers___bits___definition.html#gae93dccdbf7e8ef41da1b847975cf0eac',1,'stm32f407xx_matlab.h']]], - ['gpio_5fbsrr_5fbs1_5fmsk_335',['GPIO_BSRR_BS1_Msk',['../group___peripheral___registers___bits___definition.html#ga875bc62855425da548fa2f68d3be0f49',1,'stm32f407xx_matlab.h']]], - ['gpio_5fbsrr_5fbs1_5fpos_336',['GPIO_BSRR_BS1_Pos',['../group___peripheral___registers___bits___definition.html#ga7457f610b20ffdd73c97d90724ed4d4e',1,'stm32f407xx_matlab.h']]], - ['gpio_5fbsrr_5fbs2_337',['GPIO_BSRR_BS2',['../group___peripheral___registers___bits___definition.html#gacc89617a25217236b94eec1fd93891cb',1,'stm32f407xx_matlab.h']]], - ['gpio_5fbsrr_5fbs2_5fmsk_338',['GPIO_BSRR_BS2_Msk',['../group___peripheral___registers___bits___definition.html#gaf0d718587115b4b07190c9ade21789ac',1,'stm32f407xx_matlab.h']]], - ['gpio_5fbsrr_5fbs2_5fpos_339',['GPIO_BSRR_BS2_Pos',['../group___peripheral___registers___bits___definition.html#ga3af1acce0c96a515284b6f8bd12b8436',1,'stm32f407xx_matlab.h']]], - ['gpio_5fbsrr_5fbs3_340',['GPIO_BSRR_BS3',['../group___peripheral___registers___bits___definition.html#ga79e5ac9ace2d797ecfcc3d633c7ca52f',1,'stm32f407xx_matlab.h']]], - ['gpio_5fbsrr_5fbs3_5fmsk_341',['GPIO_BSRR_BS3_Msk',['../group___peripheral___registers___bits___definition.html#gab8d8114b4db83d01096d0337750d3099',1,'stm32f407xx_matlab.h']]], - ['gpio_5fbsrr_5fbs3_5fpos_342',['GPIO_BSRR_BS3_Pos',['../group___peripheral___registers___bits___definition.html#gac0837604e1baac4b8b86fc3e660b17ad',1,'stm32f407xx_matlab.h']]], - ['gpio_5fbsrr_5fbs4_343',['GPIO_BSRR_BS4',['../group___peripheral___registers___bits___definition.html#ga692f3966c5260fd55f3bb09829f69e75',1,'stm32f407xx_matlab.h']]], - ['gpio_5fbsrr_5fbs4_5fmsk_344',['GPIO_BSRR_BS4_Msk',['../group___peripheral___registers___bits___definition.html#ga0331d270ba3fe6bad1f3353ed09194bf',1,'stm32f407xx_matlab.h']]], - ['gpio_5fbsrr_5fbs4_5fpos_345',['GPIO_BSRR_BS4_Pos',['../group___peripheral___registers___bits___definition.html#gae421b6676ce8b2865cbb6e15fc45d495',1,'stm32f407xx_matlab.h']]], - ['gpio_5fbsrr_5fbs5_346',['GPIO_BSRR_BS5',['../group___peripheral___registers___bits___definition.html#ga5ea824455e136eee60ec17f42dabab0b',1,'stm32f407xx_matlab.h']]], - ['gpio_5fbsrr_5fbs5_5fmsk_347',['GPIO_BSRR_BS5_Msk',['../group___peripheral___registers___bits___definition.html#ga502f44e296cddc2c4099ab7e7e9b11d8',1,'stm32f407xx_matlab.h']]], - ['gpio_5fbsrr_5fbs5_5fpos_348',['GPIO_BSRR_BS5_Pos',['../group___peripheral___registers___bits___definition.html#gad686100d76807920229b49d233cbd96d',1,'stm32f407xx_matlab.h']]], - ['gpio_5fbsrr_5fbs6_349',['GPIO_BSRR_BS6',['../group___peripheral___registers___bits___definition.html#ga69b3333e39824fde00bc36b181de3929',1,'stm32f407xx_matlab.h']]], - ['gpio_5fbsrr_5fbs6_5fmsk_350',['GPIO_BSRR_BS6_Msk',['../group___peripheral___registers___bits___definition.html#gab8d6a22635cfd41987e341af34b87a63',1,'stm32f407xx_matlab.h']]], - ['gpio_5fbsrr_5fbs6_5fpos_351',['GPIO_BSRR_BS6_Pos',['../group___peripheral___registers___bits___definition.html#ga91f4268de41bba2e411879d3fa900af7',1,'stm32f407xx_matlab.h']]], - ['gpio_5fbsrr_5fbs7_352',['GPIO_BSRR_BS7',['../group___peripheral___registers___bits___definition.html#gaf9836771d1c021b9b7350fd3c3d544b0',1,'stm32f407xx_matlab.h']]], - ['gpio_5fbsrr_5fbs7_5fmsk_353',['GPIO_BSRR_BS7_Msk',['../group___peripheral___registers___bits___definition.html#ga635b08b445669748e8fadbcb0d2481e6',1,'stm32f407xx_matlab.h']]], - ['gpio_5fbsrr_5fbs7_5fpos_354',['GPIO_BSRR_BS7_Pos',['../group___peripheral___registers___bits___definition.html#ga6d1dd4ddac06be768bb7727bcb657081',1,'stm32f407xx_matlab.h']]], - ['gpio_5fbsrr_5fbs8_355',['GPIO_BSRR_BS8',['../group___peripheral___registers___bits___definition.html#ga2c295b6482aa91ef51198e570166f60f',1,'stm32f407xx_matlab.h']]], - ['gpio_5fbsrr_5fbs8_5fmsk_356',['GPIO_BSRR_BS8_Msk',['../group___peripheral___registers___bits___definition.html#ga765d016146d30e6112499598959a948a',1,'stm32f407xx_matlab.h']]], - ['gpio_5fbsrr_5fbs8_5fpos_357',['GPIO_BSRR_BS8_Pos',['../group___peripheral___registers___bits___definition.html#ga595b5fd07dcafd23fd6ed6e23cb43b5a',1,'stm32f407xx_matlab.h']]], - ['gpio_5fbsrr_5fbs9_358',['GPIO_BSRR_BS9',['../group___peripheral___registers___bits___definition.html#ga49258fbb201ec8e332b248bbd0370b07',1,'stm32f407xx_matlab.h']]], - ['gpio_5fbsrr_5fbs9_5fmsk_359',['GPIO_BSRR_BS9_Msk',['../group___peripheral___registers___bits___definition.html#ga5e1f12d75678bb5d295b8f77d5db15a0',1,'stm32f407xx_matlab.h']]], - ['gpio_5fbsrr_5fbs9_5fpos_360',['GPIO_BSRR_BS9_Pos',['../group___peripheral___registers___bits___definition.html#gab415c303400428fa585419e57aa2513d',1,'stm32f407xx_matlab.h']]], - ['gpio_5fbsrr_5fbs_5f0_361',['GPIO_BSRR_BS_0',['../group___peripheral___registers___bits___definition.html#ga4b69748fd2f5e2890e784bc0970b31d5',1,'stm32f407xx_matlab.h']]], - ['gpio_5fbsrr_5fbs_5f1_362',['GPIO_BSRR_BS_1',['../group___peripheral___registers___bits___definition.html#gaa887cd170c757a2954ae8384908d030a',1,'stm32f407xx_matlab.h']]], - ['gpio_5fbsrr_5fbs_5f10_363',['GPIO_BSRR_BS_10',['../group___peripheral___registers___bits___definition.html#gaa58e335b962fc81af70d19dbd09d9137',1,'stm32f407xx_matlab.h']]], - ['gpio_5fbsrr_5fbs_5f11_364',['GPIO_BSRR_BS_11',['../group___peripheral___registers___bits___definition.html#ga5744153a68c73330e2ebe9a9a0ef8036',1,'stm32f407xx_matlab.h']]], - ['gpio_5fbsrr_5fbs_5f12_365',['GPIO_BSRR_BS_12',['../group___peripheral___registers___bits___definition.html#ga78652a72a05249db1d343735d1764208',1,'stm32f407xx_matlab.h']]], - ['gpio_5fbsrr_5fbs_5f13_366',['GPIO_BSRR_BS_13',['../group___peripheral___registers___bits___definition.html#ga6367e64393bc954efa6fdce80e94f1be',1,'stm32f407xx_matlab.h']]], - ['gpio_5fbsrr_5fbs_5f14_367',['GPIO_BSRR_BS_14',['../group___peripheral___registers___bits___definition.html#gaa8c5c56ab4bc16dd7341203c73899e41',1,'stm32f407xx_matlab.h']]], - ['gpio_5fbsrr_5fbs_5f15_368',['GPIO_BSRR_BS_15',['../group___peripheral___registers___bits___definition.html#ga66c0c77c304415bdccf47a0f08b58e4d',1,'stm32f407xx_matlab.h']]], - ['gpio_5fbsrr_5fbs_5f2_369',['GPIO_BSRR_BS_2',['../group___peripheral___registers___bits___definition.html#gaa59c6fcfc63587ebe3cbf640cc74776a',1,'stm32f407xx_matlab.h']]], - ['gpio_5fbsrr_5fbs_5f3_370',['GPIO_BSRR_BS_3',['../group___peripheral___registers___bits___definition.html#gac41aaeaf32b8837f8f6e29e09ed92152',1,'stm32f407xx_matlab.h']]], - ['gpio_5fbsrr_5fbs_5f4_371',['GPIO_BSRR_BS_4',['../group___peripheral___registers___bits___definition.html#ga002773af2697ddca1bac26831cfbf231',1,'stm32f407xx_matlab.h']]], - ['gpio_5fbsrr_5fbs_5f5_372',['GPIO_BSRR_BS_5',['../group___peripheral___registers___bits___definition.html#gaf9f2671eae81f28d0054b62ca5e2f763',1,'stm32f407xx_matlab.h']]], - ['gpio_5fbsrr_5fbs_5f6_373',['GPIO_BSRR_BS_6',['../group___peripheral___registers___bits___definition.html#ga5dab92d27518649b3807aa4c8ef376b6',1,'stm32f407xx_matlab.h']]], - ['gpio_5fbsrr_5fbs_5f7_374',['GPIO_BSRR_BS_7',['../group___peripheral___registers___bits___definition.html#gaac4945b022950bdb9570e744279a0dd6',1,'stm32f407xx_matlab.h']]], - ['gpio_5fbsrr_5fbs_5f8_375',['GPIO_BSRR_BS_8',['../group___peripheral___registers___bits___definition.html#ga648026b2f11d992bb0e3383644be4eb9',1,'stm32f407xx_matlab.h']]], - ['gpio_5fbsrr_5fbs_5f9_376',['GPIO_BSRR_BS_9',['../group___peripheral___registers___bits___definition.html#ga9db2ccea6361f65c6bf156aa57cd4b88',1,'stm32f407xx_matlab.h']]], - ['gpio_5fidr_5fid0_377',['GPIO_IDR_ID0',['../group___peripheral___registers___bits___definition.html#ga64aa379a4bcfe84ae33383d689373096',1,'stm32f407xx_matlab.h']]], - ['gpio_5fidr_5fid0_5fmsk_378',['GPIO_IDR_ID0_Msk',['../group___peripheral___registers___bits___definition.html#ga8fe6424f42570902856737fb45f7d321',1,'stm32f407xx_matlab.h']]], - ['gpio_5fidr_5fid0_5fpos_379',['GPIO_IDR_ID0_Pos',['../group___peripheral___registers___bits___definition.html#ga1069cfa20fb4680057c8f9b91826ebe1',1,'stm32f407xx_matlab.h']]], - ['gpio_5fidr_5fid1_380',['GPIO_IDR_ID1',['../group___peripheral___registers___bits___definition.html#ga2e44bbc1d39579b027765f259dc897ea',1,'stm32f407xx_matlab.h']]], - ['gpio_5fidr_5fid10_381',['GPIO_IDR_ID10',['../group___peripheral___registers___bits___definition.html#ga6cd53d2742d0ace30b835bd0f44f5ebf',1,'stm32f407xx_matlab.h']]], - ['gpio_5fidr_5fid10_5fmsk_382',['GPIO_IDR_ID10_Msk',['../group___peripheral___registers___bits___definition.html#gaa33d3d411ebb4a1009e148df02d2ac54',1,'stm32f407xx_matlab.h']]], - ['gpio_5fidr_5fid10_5fpos_383',['GPIO_IDR_ID10_Pos',['../group___peripheral___registers___bits___definition.html#gaf6842601dbe73734e8058a6858fa7078',1,'stm32f407xx_matlab.h']]], - ['gpio_5fidr_5fid11_384',['GPIO_IDR_ID11',['../group___peripheral___registers___bits___definition.html#gade5e087b267f95733cc4328522b7890d',1,'stm32f407xx_matlab.h']]], - ['gpio_5fidr_5fid11_5fmsk_385',['GPIO_IDR_ID11_Msk',['../group___peripheral___registers___bits___definition.html#gad068577edb9af03083fcd0f4de0f8758',1,'stm32f407xx_matlab.h']]], - ['gpio_5fidr_5fid11_5fpos_386',['GPIO_IDR_ID11_Pos',['../group___peripheral___registers___bits___definition.html#ga117cc21fe4de69983c2444c7f8587687',1,'stm32f407xx_matlab.h']]], - ['gpio_5fidr_5fid12_387',['GPIO_IDR_ID12',['../group___peripheral___registers___bits___definition.html#ga33564d1679db8201389f806595d000d9',1,'stm32f407xx_matlab.h']]], - ['gpio_5fidr_5fid12_5fmsk_388',['GPIO_IDR_ID12_Msk',['../group___peripheral___registers___bits___definition.html#ga04a2965de2040e7c131ca5ab24a6724c',1,'stm32f407xx_matlab.h']]], - ['gpio_5fidr_5fid12_5fpos_389',['GPIO_IDR_ID12_Pos',['../group___peripheral___registers___bits___definition.html#ga1bc8d6bc8dd7654ccb18d936a3efe79f',1,'stm32f407xx_matlab.h']]], - ['gpio_5fidr_5fid13_390',['GPIO_IDR_ID13',['../group___peripheral___registers___bits___definition.html#ga82e0ce0fca46443e3cbaf887a3a35713',1,'stm32f407xx_matlab.h']]], - ['gpio_5fidr_5fid13_5fmsk_391',['GPIO_IDR_ID13_Msk',['../group___peripheral___registers___bits___definition.html#ga38255de273b95c94e29c1bdaa637579e',1,'stm32f407xx_matlab.h']]], - ['gpio_5fidr_5fid13_5fpos_392',['GPIO_IDR_ID13_Pos',['../group___peripheral___registers___bits___definition.html#gada649f077b81777a8ba7ae97160e9fe4',1,'stm32f407xx_matlab.h']]], - ['gpio_5fidr_5fid14_393',['GPIO_IDR_ID14',['../group___peripheral___registers___bits___definition.html#gac716fc8a3853431b69697ea5ee0aa8d2',1,'stm32f407xx_matlab.h']]], - ['gpio_5fidr_5fid14_5fmsk_394',['GPIO_IDR_ID14_Msk',['../group___peripheral___registers___bits___definition.html#gacba67a5c308fb3b335dcd8979625b1b3',1,'stm32f407xx_matlab.h']]], - ['gpio_5fidr_5fid14_5fpos_395',['GPIO_IDR_ID14_Pos',['../group___peripheral___registers___bits___definition.html#ga0921a37817bff3c30f5e4c019b6a4084',1,'stm32f407xx_matlab.h']]], - ['gpio_5fidr_5fid15_396',['GPIO_IDR_ID15',['../group___peripheral___registers___bits___definition.html#gae72c80e97c41b8143cf299c078459ea4',1,'stm32f407xx_matlab.h']]], - ['gpio_5fidr_5fid15_5fmsk_397',['GPIO_IDR_ID15_Msk',['../group___peripheral___registers___bits___definition.html#ga18c156b5eb9356ecd1ba66c96864d5a5',1,'stm32f407xx_matlab.h']]], - ['gpio_5fidr_5fid15_5fpos_398',['GPIO_IDR_ID15_Pos',['../group___peripheral___registers___bits___definition.html#ga631021cf3bab4864fdc505ceee8a6c4f',1,'stm32f407xx_matlab.h']]], - ['gpio_5fidr_5fid1_5fmsk_399',['GPIO_IDR_ID1_Msk',['../group___peripheral___registers___bits___definition.html#ga00dbb77370754ad461600ed3cf418dba',1,'stm32f407xx_matlab.h']]], - ['gpio_5fidr_5fid1_5fpos_400',['GPIO_IDR_ID1_Pos',['../group___peripheral___registers___bits___definition.html#ga38320698cffb50138c8438a860030cb9',1,'stm32f407xx_matlab.h']]], - ['gpio_5fidr_5fid2_401',['GPIO_IDR_ID2',['../group___peripheral___registers___bits___definition.html#gaf2b06b287f35a0b048d8f5fbe4a06a9c',1,'stm32f407xx_matlab.h']]], - ['gpio_5fidr_5fid2_5fmsk_402',['GPIO_IDR_ID2_Msk',['../group___peripheral___registers___bits___definition.html#ga1b48dad5247c404dda274ab5e5fde340',1,'stm32f407xx_matlab.h']]], - ['gpio_5fidr_5fid2_5fpos_403',['GPIO_IDR_ID2_Pos',['../group___peripheral___registers___bits___definition.html#ga1720532896734b3e5ffaccd76834fdef',1,'stm32f407xx_matlab.h']]], - ['gpio_5fidr_5fid3_404',['GPIO_IDR_ID3',['../group___peripheral___registers___bits___definition.html#gac0c3adefa4cafaf0455139b4e80b70eb',1,'stm32f407xx_matlab.h']]], - ['gpio_5fidr_5fid3_5fmsk_405',['GPIO_IDR_ID3_Msk',['../group___peripheral___registers___bits___definition.html#ga2ca640e7db8f27244ae9515a58910ae3',1,'stm32f407xx_matlab.h']]], - ['gpio_5fidr_5fid3_5fpos_406',['GPIO_IDR_ID3_Pos',['../group___peripheral___registers___bits___definition.html#gac9ea4291861a56bb8901653b2c148ccd',1,'stm32f407xx_matlab.h']]], - ['gpio_5fidr_5fid4_407',['GPIO_IDR_ID4',['../group___peripheral___registers___bits___definition.html#ga7454dab87916ca6076b287a21c2e4cd7',1,'stm32f407xx_matlab.h']]], - ['gpio_5fidr_5fid4_5fmsk_408',['GPIO_IDR_ID4_Msk',['../group___peripheral___registers___bits___definition.html#gaa1d6c2b8346744bc456ea65d4365c207',1,'stm32f407xx_matlab.h']]], - ['gpio_5fidr_5fid4_5fpos_409',['GPIO_IDR_ID4_Pos',['../group___peripheral___registers___bits___definition.html#ga3acb4b4ccaae63ec98c19fbe056c74ae',1,'stm32f407xx_matlab.h']]], - ['gpio_5fidr_5fid5_410',['GPIO_IDR_ID5',['../group___peripheral___registers___bits___definition.html#ga2cbfa2ff564030d912ce8f327850a3bf',1,'stm32f407xx_matlab.h']]], - ['gpio_5fidr_5fid5_5fmsk_411',['GPIO_IDR_ID5_Msk',['../group___peripheral___registers___bits___definition.html#ga8b44907427286bcb72189dbef6fc0148',1,'stm32f407xx_matlab.h']]], - ['gpio_5fidr_5fid5_5fpos_412',['GPIO_IDR_ID5_Pos',['../group___peripheral___registers___bits___definition.html#ga4f45f4603706510827aa92d39fd4bb45',1,'stm32f407xx_matlab.h']]], - ['gpio_5fidr_5fid6_413',['GPIO_IDR_ID6',['../group___peripheral___registers___bits___definition.html#gac933b9235cae5f9fccbd2fc41f9a2dc4',1,'stm32f407xx_matlab.h']]], - ['gpio_5fidr_5fid6_5fmsk_414',['GPIO_IDR_ID6_Msk',['../group___peripheral___registers___bits___definition.html#gafb18ccf8bb22161f83ad929a18d4c4aa',1,'stm32f407xx_matlab.h']]], - ['gpio_5fidr_5fid6_5fpos_415',['GPIO_IDR_ID6_Pos',['../group___peripheral___registers___bits___definition.html#gafbd6ccece5d47d40c929af5cf9973203',1,'stm32f407xx_matlab.h']]], - ['gpio_5fidr_5fid7_416',['GPIO_IDR_ID7',['../group___peripheral___registers___bits___definition.html#ga09ce75fcb48ac0db30f99ba312e8538a',1,'stm32f407xx_matlab.h']]], - ['gpio_5fidr_5fid7_5fmsk_417',['GPIO_IDR_ID7_Msk',['../group___peripheral___registers___bits___definition.html#ga45c9835db5c12b661eae0c5a0a69af5a',1,'stm32f407xx_matlab.h']]], - ['gpio_5fidr_5fid7_5fpos_418',['GPIO_IDR_ID7_Pos',['../group___peripheral___registers___bits___definition.html#ga23669c60b1baa1d95dac788cff2a0eb8',1,'stm32f407xx_matlab.h']]], - ['gpio_5fidr_5fid8_419',['GPIO_IDR_ID8',['../group___peripheral___registers___bits___definition.html#gaa193633720d142ceca6c6b27c4e87f02',1,'stm32f407xx_matlab.h']]], - ['gpio_5fidr_5fid8_5fmsk_420',['GPIO_IDR_ID8_Msk',['../group___peripheral___registers___bits___definition.html#ga08a268c98dea54059f48bbda7edd8e74',1,'stm32f407xx_matlab.h']]], - ['gpio_5fidr_5fid8_5fpos_421',['GPIO_IDR_ID8_Pos',['../group___peripheral___registers___bits___definition.html#gaaba7afe6abb55e6a80fb0ace5d46c883',1,'stm32f407xx_matlab.h']]], - ['gpio_5fidr_5fid9_422',['GPIO_IDR_ID9',['../group___peripheral___registers___bits___definition.html#ga888325b6581f9ae181f3e4fe904b0c44',1,'stm32f407xx_matlab.h']]], - ['gpio_5fidr_5fid9_5fmsk_423',['GPIO_IDR_ID9_Msk',['../group___peripheral___registers___bits___definition.html#ga4dad9a902a8200c53d60ba02de858315',1,'stm32f407xx_matlab.h']]], - ['gpio_5fidr_5fid9_5fpos_424',['GPIO_IDR_ID9_Pos',['../group___peripheral___registers___bits___definition.html#gad46ff99f2017c2a5eeab2fdeebfb1012',1,'stm32f407xx_matlab.h']]], - ['gpio_5fidr_5fidr_5f0_425',['GPIO_IDR_IDR_0',['../group___peripheral___registers___bits___definition.html#ga7691154d734ec08089eb3dc28a369726',1,'stm32f407xx_matlab.h']]], - ['gpio_5fidr_5fidr_5f1_426',['GPIO_IDR_IDR_1',['../group___peripheral___registers___bits___definition.html#gad4b3e9ceaa683b7cbc89f2507ef0f110',1,'stm32f407xx_matlab.h']]], - ['gpio_5fidr_5fidr_5f10_427',['GPIO_IDR_IDR_10',['../group___peripheral___registers___bits___definition.html#gaff38e1078878bdd79375295e7ab829b5',1,'stm32f407xx_matlab.h']]], - ['gpio_5fidr_5fidr_5f11_428',['GPIO_IDR_IDR_11',['../group___peripheral___registers___bits___definition.html#ga84c3f48e386abf1f6d97e4fb86cbaa7c',1,'stm32f407xx_matlab.h']]], - ['gpio_5fidr_5fidr_5f12_429',['GPIO_IDR_IDR_12',['../group___peripheral___registers___bits___definition.html#gaec151d78711f0274d3ab5b239884e645',1,'stm32f407xx_matlab.h']]], - ['gpio_5fidr_5fidr_5f13_430',['GPIO_IDR_IDR_13',['../group___peripheral___registers___bits___definition.html#ga6771a14a3c52f397295737e509633b05',1,'stm32f407xx_matlab.h']]], - ['gpio_5fidr_5fidr_5f14_431',['GPIO_IDR_IDR_14',['../group___peripheral___registers___bits___definition.html#gae0b8882f4473b5d65266792ed631f0bb',1,'stm32f407xx_matlab.h']]], - ['gpio_5fidr_5fidr_5f15_432',['GPIO_IDR_IDR_15',['../group___peripheral___registers___bits___definition.html#ga5fa9b2bca3451f0be4560333692fb5a4',1,'stm32f407xx_matlab.h']]], - ['gpio_5fidr_5fidr_5f2_433',['GPIO_IDR_IDR_2',['../group___peripheral___registers___bits___definition.html#gaf32691b8213a6b9c7ddb164bcc66af7f',1,'stm32f407xx_matlab.h']]], - ['gpio_5fidr_5fidr_5f3_434',['GPIO_IDR_IDR_3',['../group___peripheral___registers___bits___definition.html#ga172dc9a76f772c8e386ac0162e0a52fa',1,'stm32f407xx_matlab.h']]], - ['gpio_5fidr_5fidr_5f4_435',['GPIO_IDR_IDR_4',['../group___peripheral___registers___bits___definition.html#ga5aded5247a4fa0834a311679c593fcd7',1,'stm32f407xx_matlab.h']]], - ['gpio_5fidr_5fidr_5f5_436',['GPIO_IDR_IDR_5',['../group___peripheral___registers___bits___definition.html#ga4e7bf44f34ab51218a24b6b9467e9166',1,'stm32f407xx_matlab.h']]], - ['gpio_5fidr_5fidr_5f6_437',['GPIO_IDR_IDR_6',['../group___peripheral___registers___bits___definition.html#ga6aa5a3c8353ab0ce15d6500baf902e8b',1,'stm32f407xx_matlab.h']]], - ['gpio_5fidr_5fidr_5f7_438',['GPIO_IDR_IDR_7',['../group___peripheral___registers___bits___definition.html#gaeccc9232d1758570c7dd9d8733d9f5b6',1,'stm32f407xx_matlab.h']]], - ['gpio_5fidr_5fidr_5f8_439',['GPIO_IDR_IDR_8',['../group___peripheral___registers___bits___definition.html#ga2b5f3c629daa6d4dd3ace095a127f9e1',1,'stm32f407xx_matlab.h']]], - ['gpio_5fidr_5fidr_5f9_440',['GPIO_IDR_IDR_9',['../group___peripheral___registers___bits___definition.html#gacd452f85fa151363ffbf1d263185ef0d',1,'stm32f407xx_matlab.h']]], - ['gpio_5flckr_5flck0_441',['GPIO_LCKR_LCK0',['../group___peripheral___registers___bits___definition.html#gaf6ae6b6d787a6af758bfde54b6ae934f',1,'stm32f407xx_matlab.h']]], - ['gpio_5flckr_5flck0_5fmsk_442',['GPIO_LCKR_LCK0_Msk',['../group___peripheral___registers___bits___definition.html#ga8b01ced29f1324ec2711a784f35504dd',1,'stm32f407xx_matlab.h']]], - ['gpio_5flckr_5flck0_5fpos_443',['GPIO_LCKR_LCK0_Pos',['../group___peripheral___registers___bits___definition.html#ga9a97048a23afc262b30fc9d0a4cb65bc',1,'stm32f407xx_matlab.h']]], - ['gpio_5flckr_5flck1_444',['GPIO_LCKR_LCK1',['../group___peripheral___registers___bits___definition.html#ga627d088ded79e6da761eaa880582372a',1,'stm32f407xx_matlab.h']]], - ['gpio_5flckr_5flck10_445',['GPIO_LCKR_LCK10',['../group___peripheral___registers___bits___definition.html#gaae055f5848967c7929f47e848b2ed812',1,'stm32f407xx_matlab.h']]], - ['gpio_5flckr_5flck10_5fmsk_446',['GPIO_LCKR_LCK10_Msk',['../group___peripheral___registers___bits___definition.html#ga1373c9d71b76f466fd817823e64e7aae',1,'stm32f407xx_matlab.h']]], - ['gpio_5flckr_5flck10_5fpos_447',['GPIO_LCKR_LCK10_Pos',['../group___peripheral___registers___bits___definition.html#ga8eeb57953118508685e74055da9d6348',1,'stm32f407xx_matlab.h']]], - ['gpio_5flckr_5flck11_448',['GPIO_LCKR_LCK11',['../group___peripheral___registers___bits___definition.html#ga4de971426a1248621733a9b78ef552ab',1,'stm32f407xx_matlab.h']]], - ['gpio_5flckr_5flck11_5fmsk_449',['GPIO_LCKR_LCK11_Msk',['../group___peripheral___registers___bits___definition.html#ga1aea84ab5cf33a4b62cdb3af4a819bde',1,'stm32f407xx_matlab.h']]], - ['gpio_5flckr_5flck11_5fpos_450',['GPIO_LCKR_LCK11_Pos',['../group___peripheral___registers___bits___definition.html#ga4a19305a39f7bd02815a39c998c34216',1,'stm32f407xx_matlab.h']]], - ['gpio_5flckr_5flck12_451',['GPIO_LCKR_LCK12',['../group___peripheral___registers___bits___definition.html#ga38e8685790aea3fb09194683d1f58508',1,'stm32f407xx_matlab.h']]], - ['gpio_5flckr_5flck12_5fmsk_452',['GPIO_LCKR_LCK12_Msk',['../group___peripheral___registers___bits___definition.html#gaf21271b45020769396b2980a02a4c309',1,'stm32f407xx_matlab.h']]], - ['gpio_5flckr_5flck12_5fpos_453',['GPIO_LCKR_LCK12_Pos',['../group___peripheral___registers___bits___definition.html#ga81e8901ea395cd0a1b56c4118670fa0e',1,'stm32f407xx_matlab.h']]], - ['gpio_5flckr_5flck13_454',['GPIO_LCKR_LCK13',['../group___peripheral___registers___bits___definition.html#gae0279fa554731160a9115c21d95312a5',1,'stm32f407xx_matlab.h']]], - ['gpio_5flckr_5flck13_5fmsk_455',['GPIO_LCKR_LCK13_Msk',['../group___peripheral___registers___bits___definition.html#ga64171a6f566fed1f9ea7418d6a00871c',1,'stm32f407xx_matlab.h']]], - ['gpio_5flckr_5flck13_5fpos_456',['GPIO_LCKR_LCK13_Pos',['../group___peripheral___registers___bits___definition.html#ga5dd0ccab863e23880863f0d431fdee11',1,'stm32f407xx_matlab.h']]], - ['gpio_5flckr_5flck14_457',['GPIO_LCKR_LCK14',['../group___peripheral___registers___bits___definition.html#ga8bf290cecb54b6b68ac42a544b87dcee',1,'stm32f407xx_matlab.h']]], - ['gpio_5flckr_5flck14_5fmsk_458',['GPIO_LCKR_LCK14_Msk',['../group___peripheral___registers___bits___definition.html#gac42b591ea761bd0ee23287ff8d508714',1,'stm32f407xx_matlab.h']]], - ['gpio_5flckr_5flck14_5fpos_459',['GPIO_LCKR_LCK14_Pos',['../group___peripheral___registers___bits___definition.html#ga5686e00f4e40771a31eb18d88e1ca1e9',1,'stm32f407xx_matlab.h']]], - ['gpio_5flckr_5flck15_460',['GPIO_LCKR_LCK15',['../group___peripheral___registers___bits___definition.html#ga47c3114c8cd603d8aee022d0b426bf04',1,'stm32f407xx_matlab.h']]], - ['gpio_5flckr_5flck15_5fmsk_461',['GPIO_LCKR_LCK15_Msk',['../group___peripheral___registers___bits___definition.html#ga3841ea86b5a8200485ab90c2c6511cec',1,'stm32f407xx_matlab.h']]], - ['gpio_5flckr_5flck15_5fpos_462',['GPIO_LCKR_LCK15_Pos',['../group___peripheral___registers___bits___definition.html#ga5ba6d99e256f344ea2d8a4ba9278a0e3',1,'stm32f407xx_matlab.h']]], - ['gpio_5flckr_5flck1_5fmsk_463',['GPIO_LCKR_LCK1_Msk',['../group___peripheral___registers___bits___definition.html#ga4780ec15743062227ad0808efb16d633',1,'stm32f407xx_matlab.h']]], - ['gpio_5flckr_5flck1_5fpos_464',['GPIO_LCKR_LCK1_Pos',['../group___peripheral___registers___bits___definition.html#ga94100a3d7d43a5b8718aea76e31279a7',1,'stm32f407xx_matlab.h']]], - ['gpio_5flckr_5flck2_465',['GPIO_LCKR_LCK2',['../group___peripheral___registers___bits___definition.html#gac5a17a7348d45dbe2b2ea41a0908d7de',1,'stm32f407xx_matlab.h']]], - ['gpio_5flckr_5flck2_5fmsk_466',['GPIO_LCKR_LCK2_Msk',['../group___peripheral___registers___bits___definition.html#gabc8315e9687b2a21a55a2abe39d42fdf',1,'stm32f407xx_matlab.h']]], - ['gpio_5flckr_5flck2_5fpos_467',['GPIO_LCKR_LCK2_Pos',['../group___peripheral___registers___bits___definition.html#ga96d48b0834c3898e74309980020f88a3',1,'stm32f407xx_matlab.h']]], - ['gpio_5flckr_5flck3_468',['GPIO_LCKR_LCK3',['../group___peripheral___registers___bits___definition.html#ga1597c1b50d32ed0229c38811656ba402',1,'stm32f407xx_matlab.h']]], - ['gpio_5flckr_5flck3_5fmsk_469',['GPIO_LCKR_LCK3_Msk',['../group___peripheral___registers___bits___definition.html#ga7f2a02d88e51b603d4b80078ccf691e0',1,'stm32f407xx_matlab.h']]], - ['gpio_5flckr_5flck3_5fpos_470',['GPIO_LCKR_LCK3_Pos',['../group___peripheral___registers___bits___definition.html#ga348f1d0358ea70f6a7dc2a00a1c519bf',1,'stm32f407xx_matlab.h']]], - ['gpio_5flckr_5flck4_471',['GPIO_LCKR_LCK4',['../group___peripheral___registers___bits___definition.html#ga723577475747d2405d86b1ab28767cb5',1,'stm32f407xx_matlab.h']]], - ['gpio_5flckr_5flck4_5fmsk_472',['GPIO_LCKR_LCK4_Msk',['../group___peripheral___registers___bits___definition.html#gac6c6dff29eb48ca0a5f6da2bc0bf3639',1,'stm32f407xx_matlab.h']]], - ['gpio_5flckr_5flck4_5fpos_473',['GPIO_LCKR_LCK4_Pos',['../group___peripheral___registers___bits___definition.html#ga9fd29e0757ed2bc8e3935d17960b68df',1,'stm32f407xx_matlab.h']]], - ['gpio_5flckr_5flck5_474',['GPIO_LCKR_LCK5',['../group___peripheral___registers___bits___definition.html#ga7c2446bfe50cbd04617496c30eda6c18',1,'stm32f407xx_matlab.h']]], - ['gpio_5flckr_5flck5_5fmsk_475',['GPIO_LCKR_LCK5_Msk',['../group___peripheral___registers___bits___definition.html#gacc6ac7aca22480f300049102d2b1c4be',1,'stm32f407xx_matlab.h']]], - ['gpio_5flckr_5flck5_5fpos_476',['GPIO_LCKR_LCK5_Pos',['../group___peripheral___registers___bits___definition.html#ga07f73a37145ff6709a20081d329900c2',1,'stm32f407xx_matlab.h']]], - ['gpio_5flckr_5flck6_477',['GPIO_LCKR_LCK6',['../group___peripheral___registers___bits___definition.html#ga606249f4cc3ac14cf8133b76f3c7edd7',1,'stm32f407xx_matlab.h']]], - ['gpio_5flckr_5flck6_5fmsk_478',['GPIO_LCKR_LCK6_Msk',['../group___peripheral___registers___bits___definition.html#ga083a590c26723e38ae5d7fd77e23809c',1,'stm32f407xx_matlab.h']]], - ['gpio_5flckr_5flck6_5fpos_479',['GPIO_LCKR_LCK6_Pos',['../group___peripheral___registers___bits___definition.html#ga456193c04a296b05ad87aa0f8e51c144',1,'stm32f407xx_matlab.h']]], - ['gpio_5flckr_5flck7_480',['GPIO_LCKR_LCK7',['../group___peripheral___registers___bits___definition.html#gaf998da536594af780718084cee0d22a4',1,'stm32f407xx_matlab.h']]], - ['gpio_5flckr_5flck7_5fmsk_481',['GPIO_LCKR_LCK7_Msk',['../group___peripheral___registers___bits___definition.html#ga5b322ee1833e0c7d369127406b5ea90e',1,'stm32f407xx_matlab.h']]], - ['gpio_5flckr_5flck7_5fpos_482',['GPIO_LCKR_LCK7_Pos',['../group___peripheral___registers___bits___definition.html#gaf9c741b163a1b1e23b05432f866544f4',1,'stm32f407xx_matlab.h']]], - ['gpio_5flckr_5flck8_483',['GPIO_LCKR_LCK8',['../group___peripheral___registers___bits___definition.html#gab00a81afcf4d92f6f5644724803b7404',1,'stm32f407xx_matlab.h']]], - ['gpio_5flckr_5flck8_5fmsk_484',['GPIO_LCKR_LCK8_Msk',['../group___peripheral___registers___bits___definition.html#gaa0e44a9155de4980cdb0f8c4d3afc43e',1,'stm32f407xx_matlab.h']]], - ['gpio_5flckr_5flck8_5fpos_485',['GPIO_LCKR_LCK8_Pos',['../group___peripheral___registers___bits___definition.html#gae9a02f2ef3023a1c82f04391fcb79859',1,'stm32f407xx_matlab.h']]], - ['gpio_5flckr_5flck9_486',['GPIO_LCKR_LCK9',['../group___peripheral___registers___bits___definition.html#gab9aa0442c88bc17eaf07c55dd84910ea',1,'stm32f407xx_matlab.h']]], - ['gpio_5flckr_5flck9_5fmsk_487',['GPIO_LCKR_LCK9_Msk',['../group___peripheral___registers___bits___definition.html#ga551c1ad8749c8ddb6785c06c1461338f',1,'stm32f407xx_matlab.h']]], - ['gpio_5flckr_5flck9_5fpos_488',['GPIO_LCKR_LCK9_Pos',['../group___peripheral___registers___bits___definition.html#ga821f9dc79420f84e79fe2697addf1d42',1,'stm32f407xx_matlab.h']]], - ['gpio_5flckr_5flckk_489',['GPIO_LCKR_LCKK',['../group___peripheral___registers___bits___definition.html#gafa2a83bf31ef76ee3857c7cb0a90c4d9',1,'stm32f407xx_matlab.h']]], - ['gpio_5flckr_5flckk_5fmsk_490',['GPIO_LCKR_LCKK_Msk',['../group___peripheral___registers___bits___definition.html#ga9312bf35ddbae593f8e94b3ea7dce9b5',1,'stm32f407xx_matlab.h']]], - ['gpio_5flckr_5flckk_5fpos_491',['GPIO_LCKR_LCKK_Pos',['../group___peripheral___registers___bits___definition.html#ga40eb2db1c2df544774f41995d029565d',1,'stm32f407xx_matlab.h']]], - ['gpio_5fmoder_5fmode0_492',['GPIO_MODER_MODE0',['../group___peripheral___registers___bits___definition.html#gabad45500839e6f801c64ee9474e4da33',1,'stm32f407xx_matlab.h']]], - ['gpio_5fmoder_5fmode0_5f0_493',['GPIO_MODER_MODE0_0',['../group___peripheral___registers___bits___definition.html#gac21859652224406f970f4c99d5198d16',1,'stm32f407xx_matlab.h']]], - ['gpio_5fmoder_5fmode0_5f1_494',['GPIO_MODER_MODE0_1',['../group___peripheral___registers___bits___definition.html#gae7a47a04b8e25a1de3250bd4921eeddc',1,'stm32f407xx_matlab.h']]], - ['gpio_5fmoder_5fmode0_5fmsk_495',['GPIO_MODER_MODE0_Msk',['../group___peripheral___registers___bits___definition.html#ga9cff105dfdd73e5a1705a3a52bfe4953',1,'stm32f407xx_matlab.h']]], - ['gpio_5fmoder_5fmode0_5fpos_496',['GPIO_MODER_MODE0_Pos',['../group___peripheral___registers___bits___definition.html#ga6f3903d8ae31585af4d8e0a4a980a53f',1,'stm32f407xx_matlab.h']]], - ['gpio_5fmoder_5fmode1_497',['GPIO_MODER_MODE1',['../group___peripheral___registers___bits___definition.html#ga76d7c80c5afbf9bf5aada55d91d59ecb',1,'stm32f407xx_matlab.h']]], - ['gpio_5fmoder_5fmode10_498',['GPIO_MODER_MODE10',['../group___peripheral___registers___bits___definition.html#ga10461308203bd8e510c3205e6a499c20',1,'stm32f407xx_matlab.h']]], - ['gpio_5fmoder_5fmode10_5f0_499',['GPIO_MODER_MODE10_0',['../group___peripheral___registers___bits___definition.html#ga7aa2a41e913180598b59b20ffafc4a47',1,'stm32f407xx_matlab.h']]], - ['gpio_5fmoder_5fmode10_5f1_500',['GPIO_MODER_MODE10_1',['../group___peripheral___registers___bits___definition.html#gad59d8ec1da352c55b9cb65b751f193e1',1,'stm32f407xx_matlab.h']]], - ['gpio_5fmoder_5fmode10_5fmsk_501',['GPIO_MODER_MODE10_Msk',['../group___peripheral___registers___bits___definition.html#gadc0dafc52e2eb8562733153c8658e8f4',1,'stm32f407xx_matlab.h']]], - ['gpio_5fmoder_5fmode10_5fpos_502',['GPIO_MODER_MODE10_Pos',['../group___peripheral___registers___bits___definition.html#ga034f78f504f81a1ed9a3d457792f4197',1,'stm32f407xx_matlab.h']]], - ['gpio_5fmoder_5fmode11_503',['GPIO_MODER_MODE11',['../group___peripheral___registers___bits___definition.html#gad4d968b108aa28b20cd40a7746004d2c',1,'stm32f407xx_matlab.h']]], - ['gpio_5fmoder_5fmode11_5f0_504',['GPIO_MODER_MODE11_0',['../group___peripheral___registers___bits___definition.html#gadeb4ecb54a0dc7f304007367e112725d',1,'stm32f407xx_matlab.h']]], - ['gpio_5fmoder_5fmode11_5f1_505',['GPIO_MODER_MODE11_1',['../group___peripheral___registers___bits___definition.html#ga7a7b954225f0a664d602cba0ed1e03d4',1,'stm32f407xx_matlab.h']]], - ['gpio_5fmoder_5fmode11_5fmsk_506',['GPIO_MODER_MODE11_Msk',['../group___peripheral___registers___bits___definition.html#ga313382ddc024a2cde3a1a3bb6ff1fc4d',1,'stm32f407xx_matlab.h']]], - ['gpio_5fmoder_5fmode11_5fpos_507',['GPIO_MODER_MODE11_Pos',['../group___peripheral___registers___bits___definition.html#gaf3c361d8935e5c043775a1dbf77b4530',1,'stm32f407xx_matlab.h']]], - ['gpio_5fmoder_5fmode12_508',['GPIO_MODER_MODE12',['../group___peripheral___registers___bits___definition.html#gac09cecc889ead7bc7a079d4889da0578',1,'stm32f407xx_matlab.h']]], - ['gpio_5fmoder_5fmode12_5f0_509',['GPIO_MODER_MODE12_0',['../group___peripheral___registers___bits___definition.html#ga4dc7e3ea6e86a627d7697dafbb7feab6',1,'stm32f407xx_matlab.h']]], - ['gpio_5fmoder_5fmode12_5f1_510',['GPIO_MODER_MODE12_1',['../group___peripheral___registers___bits___definition.html#ga9a2313be3f7d3fb0f2203456beaa4efe',1,'stm32f407xx_matlab.h']]], - ['gpio_5fmoder_5fmode12_5fmsk_511',['GPIO_MODER_MODE12_Msk',['../group___peripheral___registers___bits___definition.html#ga2bab0d5ff031fcff49dedb0c36073008',1,'stm32f407xx_matlab.h']]], - ['gpio_5fmoder_5fmode12_5fpos_512',['GPIO_MODER_MODE12_Pos',['../group___peripheral___registers___bits___definition.html#ga8967fa759f57e187e4b87b9723a12e05',1,'stm32f407xx_matlab.h']]], - ['gpio_5fmoder_5fmode13_513',['GPIO_MODER_MODE13',['../group___peripheral___registers___bits___definition.html#gaf38e8e70d58b97d462d45e6e116115be',1,'stm32f407xx_matlab.h']]], - ['gpio_5fmoder_5fmode13_5f0_514',['GPIO_MODER_MODE13_0',['../group___peripheral___registers___bits___definition.html#ga575519f151a9dda7c8e24d7c9e625b0f',1,'stm32f407xx_matlab.h']]], - ['gpio_5fmoder_5fmode13_5f1_515',['GPIO_MODER_MODE13_1',['../group___peripheral___registers___bits___definition.html#gad93a355f773bc67b68b0a665c5a15136',1,'stm32f407xx_matlab.h']]], - ['gpio_5fmoder_5fmode13_5fmsk_516',['GPIO_MODER_MODE13_Msk',['../group___peripheral___registers___bits___definition.html#ga02c48c21d983bab6115b056239d84217',1,'stm32f407xx_matlab.h']]], - ['gpio_5fmoder_5fmode13_5fpos_517',['GPIO_MODER_MODE13_Pos',['../group___peripheral___registers___bits___definition.html#gac4895814d5aa1829b1abfbd2d4df8b66',1,'stm32f407xx_matlab.h']]], - ['gpio_5fmoder_5fmode14_518',['GPIO_MODER_MODE14',['../group___peripheral___registers___bits___definition.html#ga1e67512a90147ccad6991e5b16821811',1,'stm32f407xx_matlab.h']]], - ['gpio_5fmoder_5fmode14_5f0_519',['GPIO_MODER_MODE14_0',['../group___peripheral___registers___bits___definition.html#gaaa664199b48953065ec3b16e7de90d9b',1,'stm32f407xx_matlab.h']]], - ['gpio_5fmoder_5fmode14_5f1_520',['GPIO_MODER_MODE14_1',['../group___peripheral___registers___bits___definition.html#ga1e8638837bc4e6d69cd7635296a51730',1,'stm32f407xx_matlab.h']]], - ['gpio_5fmoder_5fmode14_5fmsk_521',['GPIO_MODER_MODE14_Msk',['../group___peripheral___registers___bits___definition.html#ga8ee9ecd8c12612d429efa6b2694b8a25',1,'stm32f407xx_matlab.h']]], - ['gpio_5fmoder_5fmode14_5fpos_522',['GPIO_MODER_MODE14_Pos',['../group___peripheral___registers___bits___definition.html#gab23c1a3d555305265fe00c4a2f25d705',1,'stm32f407xx_matlab.h']]], - ['gpio_5fmoder_5fmode15_523',['GPIO_MODER_MODE15',['../group___peripheral___registers___bits___definition.html#ga8027405e42e74b5065861c067e0b9f77',1,'stm32f407xx_matlab.h']]], - ['gpio_5fmoder_5fmode15_5f0_524',['GPIO_MODER_MODE15_0',['../group___peripheral___registers___bits___definition.html#gace9ec013afbf2e01286ca61726e92332',1,'stm32f407xx_matlab.h']]], - ['gpio_5fmoder_5fmode15_5f1_525',['GPIO_MODER_MODE15_1',['../group___peripheral___registers___bits___definition.html#gaf7055ea8ec31fe604f1b5f04e2b194c4',1,'stm32f407xx_matlab.h']]], - ['gpio_5fmoder_5fmode15_5fmsk_526',['GPIO_MODER_MODE15_Msk',['../group___peripheral___registers___bits___definition.html#gacbdbb728d5db2fb68bbedd6e4374827b',1,'stm32f407xx_matlab.h']]], - ['gpio_5fmoder_5fmode15_5fpos_527',['GPIO_MODER_MODE15_Pos',['../group___peripheral___registers___bits___definition.html#ga040b83bff88d237d447bfe658913f2e7',1,'stm32f407xx_matlab.h']]], - ['gpio_5fmoder_5fmode1_5f0_528',['GPIO_MODER_MODE1_0',['../group___peripheral___registers___bits___definition.html#gabdd2690fbea56b2d7dd8af222370cc95',1,'stm32f407xx_matlab.h']]], - ['gpio_5fmoder_5fmode1_5f1_529',['GPIO_MODER_MODE1_1',['../group___peripheral___registers___bits___definition.html#ga1a240f6f0b335fe9595019531b4607b9',1,'stm32f407xx_matlab.h']]], - ['gpio_5fmoder_5fmode1_5fmsk_530',['GPIO_MODER_MODE1_Msk',['../group___peripheral___registers___bits___definition.html#ga30d7601c96266dc29ab8d67804154b3f',1,'stm32f407xx_matlab.h']]], - ['gpio_5fmoder_5fmode1_5fpos_531',['GPIO_MODER_MODE1_Pos',['../group___peripheral___registers___bits___definition.html#gadcd114563c35dd9bc117884af80acda8',1,'stm32f407xx_matlab.h']]], - ['gpio_5fmoder_5fmode2_532',['GPIO_MODER_MODE2',['../group___peripheral___registers___bits___definition.html#ga90970df916fe323664322ecbe516993d',1,'stm32f407xx_matlab.h']]], - ['gpio_5fmoder_5fmode2_5f0_533',['GPIO_MODER_MODE2_0',['../group___peripheral___registers___bits___definition.html#ga66a90c798fa54047f30b83f3eec1821b',1,'stm32f407xx_matlab.h']]], - ['gpio_5fmoder_5fmode2_5f1_534',['GPIO_MODER_MODE2_1',['../group___peripheral___registers___bits___definition.html#gaae88847b33d3c78142f99e5d1753451e',1,'stm32f407xx_matlab.h']]], - ['gpio_5fmoder_5fmode2_5fmsk_535',['GPIO_MODER_MODE2_Msk',['../group___peripheral___registers___bits___definition.html#ga7a188e7809bffb5a963302debcc602bf',1,'stm32f407xx_matlab.h']]], - ['gpio_5fmoder_5fmode2_5fpos_536',['GPIO_MODER_MODE2_Pos',['../group___peripheral___registers___bits___definition.html#gaf6405d97990f322ac711f5d50d69c41f',1,'stm32f407xx_matlab.h']]], - ['gpio_5fmoder_5fmode3_537',['GPIO_MODER_MODE3',['../group___peripheral___registers___bits___definition.html#ga9062e2f2d10271c05e5f963be522db96',1,'stm32f407xx_matlab.h']]], - ['gpio_5fmoder_5fmode3_5f0_538',['GPIO_MODER_MODE3_0',['../group___peripheral___registers___bits___definition.html#ga908f28256ab03cf88ed6e2fce3a2a70d',1,'stm32f407xx_matlab.h']]], - ['gpio_5fmoder_5fmode3_5f1_539',['GPIO_MODER_MODE3_1',['../group___peripheral___registers___bits___definition.html#ga99db34fd563915c2fc4eb16ef2505c98',1,'stm32f407xx_matlab.h']]], - ['gpio_5fmoder_5fmode3_5fmsk_540',['GPIO_MODER_MODE3_Msk',['../group___peripheral___registers___bits___definition.html#gad4eaea23a16c4fb39e27d295ce0e5b94',1,'stm32f407xx_matlab.h']]], - ['gpio_5fmoder_5fmode3_5fpos_541',['GPIO_MODER_MODE3_Pos',['../group___peripheral___registers___bits___definition.html#gaf3d6572d265c72f92e2005c141202422',1,'stm32f407xx_matlab.h']]], - ['gpio_5fmoder_5fmode4_542',['GPIO_MODER_MODE4',['../group___peripheral___registers___bits___definition.html#gae11faa17747d422f5d88ced879e09bb6',1,'stm32f407xx_matlab.h']]], - ['gpio_5fmoder_5fmode4_5f0_543',['GPIO_MODER_MODE4_0',['../group___peripheral___registers___bits___definition.html#ga2336f60fe03642339cbfd4e994812875',1,'stm32f407xx_matlab.h']]], - ['gpio_5fmoder_5fmode4_5f1_544',['GPIO_MODER_MODE4_1',['../group___peripheral___registers___bits___definition.html#gae946375c36dfb3b3669864ee62002e62',1,'stm32f407xx_matlab.h']]], - ['gpio_5fmoder_5fmode4_5fmsk_545',['GPIO_MODER_MODE4_Msk',['../group___peripheral___registers___bits___definition.html#gac9b416b464e6bcd73aa11bf0ef734b47',1,'stm32f407xx_matlab.h']]], - ['gpio_5fmoder_5fmode4_5fpos_546',['GPIO_MODER_MODE4_Pos',['../group___peripheral___registers___bits___definition.html#gab14bbd003834724332b11c3a33eba1a6',1,'stm32f407xx_matlab.h']]], - ['gpio_5fmoder_5fmode5_547',['GPIO_MODER_MODE5',['../group___peripheral___registers___bits___definition.html#ga1b40ba8ed0964516f512bb55a7783425',1,'stm32f407xx_matlab.h']]], - ['gpio_5fmoder_5fmode5_5f0_548',['GPIO_MODER_MODE5_0',['../group___peripheral___registers___bits___definition.html#gae9fbe729f8b1780ef0a6a24ce46a5dc9',1,'stm32f407xx_matlab.h']]], - ['gpio_5fmoder_5fmode5_5f1_549',['GPIO_MODER_MODE5_1',['../group___peripheral___registers___bits___definition.html#ga85fd33570c7059e94708cb99a1d88e55',1,'stm32f407xx_matlab.h']]], - ['gpio_5fmoder_5fmode5_5fmsk_550',['GPIO_MODER_MODE5_Msk',['../group___peripheral___registers___bits___definition.html#ga5ecdacbc580acb1d0045366bab0605a3',1,'stm32f407xx_matlab.h']]], - ['gpio_5fmoder_5fmode5_5fpos_551',['GPIO_MODER_MODE5_Pos',['../group___peripheral___registers___bits___definition.html#gaf3db08d5515fb6203ea8c2cf83d5ccd9',1,'stm32f407xx_matlab.h']]], - ['gpio_5fmoder_5fmode6_552',['GPIO_MODER_MODE6',['../group___peripheral___registers___bits___definition.html#gad09b263a1b49cc5db86e5e6fe5d0d59c',1,'stm32f407xx_matlab.h']]], - ['gpio_5fmoder_5fmode6_5f0_553',['GPIO_MODER_MODE6_0',['../group___peripheral___registers___bits___definition.html#gac9fe86e9e52f1ba692d5ea66c2e43678',1,'stm32f407xx_matlab.h']]], - ['gpio_5fmoder_5fmode6_5f1_554',['GPIO_MODER_MODE6_1',['../group___peripheral___registers___bits___definition.html#ga7ef7f24d9e982418baef863fbe1ffe5f',1,'stm32f407xx_matlab.h']]], - ['gpio_5fmoder_5fmode6_5fmsk_555',['GPIO_MODER_MODE6_Msk',['../group___peripheral___registers___bits___definition.html#ga923f7562b497aa9e864872e6314aec8b',1,'stm32f407xx_matlab.h']]], - ['gpio_5fmoder_5fmode6_5fpos_556',['GPIO_MODER_MODE6_Pos',['../group___peripheral___registers___bits___definition.html#ga1605f3cdb581e59663fd9fb0bab17d74',1,'stm32f407xx_matlab.h']]], - ['gpio_5fmoder_5fmode7_557',['GPIO_MODER_MODE7',['../group___peripheral___registers___bits___definition.html#gafff70c209574ca7023aa0a853a341e2b',1,'stm32f407xx_matlab.h']]], - ['gpio_5fmoder_5fmode7_5f0_558',['GPIO_MODER_MODE7_0',['../group___peripheral___registers___bits___definition.html#gac77ebcfb844a2b8893641ee9de058178',1,'stm32f407xx_matlab.h']]], - ['gpio_5fmoder_5fmode7_5f1_559',['GPIO_MODER_MODE7_1',['../group___peripheral___registers___bits___definition.html#ga1f64e364157865520082d72aa98ab0ee',1,'stm32f407xx_matlab.h']]], - ['gpio_5fmoder_5fmode7_5fmsk_560',['GPIO_MODER_MODE7_Msk',['../group___peripheral___registers___bits___definition.html#ga395417bce21078a26c0930132c9853ee',1,'stm32f407xx_matlab.h']]], - ['gpio_5fmoder_5fmode7_5fpos_561',['GPIO_MODER_MODE7_Pos',['../group___peripheral___registers___bits___definition.html#gabd7bb459725ad9a92adb58341f64c5db',1,'stm32f407xx_matlab.h']]], - ['gpio_5fmoder_5fmode8_562',['GPIO_MODER_MODE8',['../group___peripheral___registers___bits___definition.html#ga1d7027e90da284883872b827f78fbc26',1,'stm32f407xx_matlab.h']]], - ['gpio_5fmoder_5fmode8_5f0_563',['GPIO_MODER_MODE8_0',['../group___peripheral___registers___bits___definition.html#gaac1715680209944bc7593cedf31f491b',1,'stm32f407xx_matlab.h']]], - ['gpio_5fmoder_5fmode8_5f1_564',['GPIO_MODER_MODE8_1',['../group___peripheral___registers___bits___definition.html#ga3197ca6a90d936e5a564d377bd4126fd',1,'stm32f407xx_matlab.h']]], - ['gpio_5fmoder_5fmode8_5fmsk_565',['GPIO_MODER_MODE8_Msk',['../group___peripheral___registers___bits___definition.html#gabe7b281c031a88069e827a6ac710e0c5',1,'stm32f407xx_matlab.h']]], - ['gpio_5fmoder_5fmode8_5fpos_566',['GPIO_MODER_MODE8_Pos',['../group___peripheral___registers___bits___definition.html#ga962ec8cd96b449ed7cc142b491db4e0c',1,'stm32f407xx_matlab.h']]], - ['gpio_5fmoder_5fmode9_567',['GPIO_MODER_MODE9',['../group___peripheral___registers___bits___definition.html#gaf81e4a6121d0fe0ee5bc3fbe0f245572',1,'stm32f407xx_matlab.h']]], - ['gpio_5fmoder_5fmode9_5f0_568',['GPIO_MODER_MODE9_0',['../group___peripheral___registers___bits___definition.html#ga659899030e816750c2e4ecbf4250cc91',1,'stm32f407xx_matlab.h']]], - ['gpio_5fmoder_5fmode9_5f1_569',['GPIO_MODER_MODE9_1',['../group___peripheral___registers___bits___definition.html#ga15a408c473d172282468a1fccad482bb',1,'stm32f407xx_matlab.h']]], - ['gpio_5fmoder_5fmode9_5fmsk_570',['GPIO_MODER_MODE9_Msk',['../group___peripheral___registers___bits___definition.html#ga0acba3f02fb730df350c2d938792fd74',1,'stm32f407xx_matlab.h']]], - ['gpio_5fmoder_5fmode9_5fpos_571',['GPIO_MODER_MODE9_Pos',['../group___peripheral___registers___bits___definition.html#ga1093b1b58d8a8b51f204fc78239cbbb0',1,'stm32f407xx_matlab.h']]], - ['gpio_5fmoder_5fmoder0_572',['GPIO_MODER_MODER0',['../group___peripheral___registers___bits___definition.html#ga7b64d47643f8d3c08c2be0722ff23b93',1,'stm32f407xx_matlab.h']]], - ['gpio_5fmoder_5fmoder0_5f0_573',['GPIO_MODER_MODER0_0',['../group___peripheral___registers___bits___definition.html#ga9547fc54057db093f9ee4b846fcc4723',1,'stm32f407xx_matlab.h']]], - ['gpio_5fmoder_5fmoder0_5f1_574',['GPIO_MODER_MODER0_1',['../group___peripheral___registers___bits___definition.html#ga9e77a3bc750fe2ea8e06da301c65d6ef',1,'stm32f407xx_matlab.h']]], - ['gpio_5fmoder_5fmoder0_5fmsk_575',['GPIO_MODER_MODER0_Msk',['../group___peripheral___registers___bits___definition.html#ga44c7a73f891cc60cb11c8dc122fde9bd',1,'stm32f407xx_matlab.h']]], - ['gpio_5fmoder_5fmoder0_5fpos_576',['GPIO_MODER_MODER0_Pos',['../group___peripheral___registers___bits___definition.html#ga2244aa753f0340359098d15944602258',1,'stm32f407xx_matlab.h']]], - ['gpio_5fmoder_5fmoder1_577',['GPIO_MODER_MODER1',['../group___peripheral___registers___bits___definition.html#ga2e0597b084c911728ee92b5fc4a2ae5a',1,'stm32f407xx_matlab.h']]], - ['gpio_5fmoder_5fmoder10_578',['GPIO_MODER_MODER10',['../group___peripheral___registers___bits___definition.html#gaacbdb241d7bebde85d7d0b42c2f35563',1,'stm32f407xx_matlab.h']]], - ['gpio_5fmoder_5fmoder10_5f0_579',['GPIO_MODER_MODER10_0',['../group___peripheral___registers___bits___definition.html#ga6f4d2b18e57e7b2f600e4f5d9b17bd95',1,'stm32f407xx_matlab.h']]], - ['gpio_5fmoder_5fmoder10_5f1_580',['GPIO_MODER_MODER10_1',['../group___peripheral___registers___bits___definition.html#ga9dcae08e0f7afc002658a4ef4a764dc4',1,'stm32f407xx_matlab.h']]], - ['gpio_5fmoder_5fmoder10_5fmsk_581',['GPIO_MODER_MODER10_Msk',['../group___peripheral___registers___bits___definition.html#ga9af602f158627d6d61a2fcf7149a6178',1,'stm32f407xx_matlab.h']]], - ['gpio_5fmoder_5fmoder10_5fpos_582',['GPIO_MODER_MODER10_Pos',['../group___peripheral___registers___bits___definition.html#gacf36ddfa8971a143e722ca9897d6a554',1,'stm32f407xx_matlab.h']]], - ['gpio_5fmoder_5fmoder11_583',['GPIO_MODER_MODER11',['../group___peripheral___registers___bits___definition.html#gaf18bc295f7195fc050221287c4564474',1,'stm32f407xx_matlab.h']]], - ['gpio_5fmoder_5fmoder11_5f0_584',['GPIO_MODER_MODER11_0',['../group___peripheral___registers___bits___definition.html#gaf4082cd576f50cd2687e45557b70d458',1,'stm32f407xx_matlab.h']]], - ['gpio_5fmoder_5fmoder11_5f1_585',['GPIO_MODER_MODER11_1',['../group___peripheral___registers___bits___definition.html#ga1b2f611ae75f3441bad03866550f6263',1,'stm32f407xx_matlab.h']]], - ['gpio_5fmoder_5fmoder11_5fmsk_586',['GPIO_MODER_MODER11_Msk',['../group___peripheral___registers___bits___definition.html#ga82a8fa719e9f98d2a7b4fd00ad41927d',1,'stm32f407xx_matlab.h']]], - ['gpio_5fmoder_5fmoder11_5fpos_587',['GPIO_MODER_MODER11_Pos',['../group___peripheral___registers___bits___definition.html#gac60a554e688d63d15bce7240549d2ccb',1,'stm32f407xx_matlab.h']]], - ['gpio_5fmoder_5fmoder12_588',['GPIO_MODER_MODER12',['../group___peripheral___registers___bits___definition.html#ga63101c5c410b55b668ec190422dc3597',1,'stm32f407xx_matlab.h']]], - ['gpio_5fmoder_5fmoder12_5f0_589',['GPIO_MODER_MODER12_0',['../group___peripheral___registers___bits___definition.html#gaa89cd8ed328ed0116cbf51810fcd8788',1,'stm32f407xx_matlab.h']]], - ['gpio_5fmoder_5fmoder12_5f1_590',['GPIO_MODER_MODER12_1',['../group___peripheral___registers___bits___definition.html#ga74f91bdd676e477e4c19d30d3ea5c4c8',1,'stm32f407xx_matlab.h']]], - ['gpio_5fmoder_5fmoder12_5fmsk_591',['GPIO_MODER_MODER12_Msk',['../group___peripheral___registers___bits___definition.html#gabd6d6390219a23c8420cc152901ca9bd',1,'stm32f407xx_matlab.h']]], - ['gpio_5fmoder_5fmoder12_5fpos_592',['GPIO_MODER_MODER12_Pos',['../group___peripheral___registers___bits___definition.html#gaec7b868a25af299e046b49b017c1114f',1,'stm32f407xx_matlab.h']]], - ['gpio_5fmoder_5fmoder13_593',['GPIO_MODER_MODER13',['../group___peripheral___registers___bits___definition.html#ga353af246bef5dca5aadfe6fe3fd695c3',1,'stm32f407xx_matlab.h']]], - ['gpio_5fmoder_5fmoder13_5f0_594',['GPIO_MODER_MODER13_0',['../group___peripheral___registers___bits___definition.html#gabc01e2e6cf45e8ec27d3a66ff36c2cfa',1,'stm32f407xx_matlab.h']]], - ['gpio_5fmoder_5fmoder13_5f1_595',['GPIO_MODER_MODER13_1',['../group___peripheral___registers___bits___definition.html#ga71a30088f5475ae8774404ae7d41872e',1,'stm32f407xx_matlab.h']]], - ['gpio_5fmoder_5fmoder13_5fmsk_596',['GPIO_MODER_MODER13_Msk',['../group___peripheral___registers___bits___definition.html#ga3ae7344fb7e360c013ae484a7b3ce06e',1,'stm32f407xx_matlab.h']]], - ['gpio_5fmoder_5fmoder13_5fpos_597',['GPIO_MODER_MODER13_Pos',['../group___peripheral___registers___bits___definition.html#ga1e91d26a428aa90b419bf51324491246',1,'stm32f407xx_matlab.h']]], - ['gpio_5fmoder_5fmoder14_598',['GPIO_MODER_MODER14',['../group___peripheral___registers___bits___definition.html#ga18a722f9682045c1d2460fedf32b02b1',1,'stm32f407xx_matlab.h']]], - ['gpio_5fmoder_5fmoder14_5f0_599',['GPIO_MODER_MODER14_0',['../group___peripheral___registers___bits___definition.html#gad295063c22bd981239bc1b26f2e7f9c0',1,'stm32f407xx_matlab.h']]], - ['gpio_5fmoder_5fmoder14_5f1_600',['GPIO_MODER_MODER14_1',['../group___peripheral___registers___bits___definition.html#ga0ff3a914796db9625d86996b6f6f5288',1,'stm32f407xx_matlab.h']]], - ['gpio_5fmoder_5fmoder14_5fmsk_601',['GPIO_MODER_MODER14_Msk',['../group___peripheral___registers___bits___definition.html#ga1fd4d1526a36e0838bc8c9bab621aba0',1,'stm32f407xx_matlab.h']]], - ['gpio_5fmoder_5fmoder14_5fpos_602',['GPIO_MODER_MODER14_Pos',['../group___peripheral___registers___bits___definition.html#gac67c9470dc741033d3254a4041e3d320',1,'stm32f407xx_matlab.h']]], - ['gpio_5fmoder_5fmoder15_603',['GPIO_MODER_MODER15',['../group___peripheral___registers___bits___definition.html#gaefc40e6fae78c1c5c857346793f9d4c8',1,'stm32f407xx_matlab.h']]], - ['gpio_5fmoder_5fmoder15_5f0_604',['GPIO_MODER_MODER15_0',['../group___peripheral___registers___bits___definition.html#ga6c4b7f270eb99d851b84b9917fe49564',1,'stm32f407xx_matlab.h']]], - ['gpio_5fmoder_5fmoder15_5f1_605',['GPIO_MODER_MODER15_1',['../group___peripheral___registers___bits___definition.html#ga9297c041f5f74aec73e6f4dd89ad819c',1,'stm32f407xx_matlab.h']]], - ['gpio_5fmoder_5fmoder15_5fmsk_606',['GPIO_MODER_MODER15_Msk',['../group___peripheral___registers___bits___definition.html#ga97ba0885b9dda0bec8202305bf9cf0ad',1,'stm32f407xx_matlab.h']]], - ['gpio_5fmoder_5fmoder15_5fpos_607',['GPIO_MODER_MODER15_Pos',['../group___peripheral___registers___bits___definition.html#gac8c4f0c2ee0dbf7761c9acf9f4d9fa8b',1,'stm32f407xx_matlab.h']]], - ['gpio_5fmoder_5fmoder1_5f0_608',['GPIO_MODER_MODER1_0',['../group___peripheral___registers___bits___definition.html#ga5d85123ad7c77e052b542f2df47a1371',1,'stm32f407xx_matlab.h']]], - ['gpio_5fmoder_5fmoder1_5f1_609',['GPIO_MODER_MODER1_1',['../group___peripheral___registers___bits___definition.html#gad9f16759689b9ac61d9c68842ac49746',1,'stm32f407xx_matlab.h']]], - ['gpio_5fmoder_5fmoder1_5fmsk_610',['GPIO_MODER_MODER1_Msk',['../group___peripheral___registers___bits___definition.html#ga3b96dc64bbedb58b5a6fdcc3c97eab1d',1,'stm32f407xx_matlab.h']]], - ['gpio_5fmoder_5fmoder1_5fpos_611',['GPIO_MODER_MODER1_Pos',['../group___peripheral___registers___bits___definition.html#gae1030dee3583ca3e42adbdfe515ff542',1,'stm32f407xx_matlab.h']]], - ['gpio_5fmoder_5fmoder2_612',['GPIO_MODER_MODER2',['../group___peripheral___registers___bits___definition.html#ga06865341707bb4dd9671ce464d99ab2c',1,'stm32f407xx_matlab.h']]], - ['gpio_5fmoder_5fmoder2_5f0_613',['GPIO_MODER_MODER2_0',['../group___peripheral___registers___bits___definition.html#ga06e9f9713b7a822784cd2c0fa79dcff0',1,'stm32f407xx_matlab.h']]], - ['gpio_5fmoder_5fmoder2_5f1_614',['GPIO_MODER_MODER2_1',['../group___peripheral___registers___bits___definition.html#ga97f7959265384b2621288c8340990665',1,'stm32f407xx_matlab.h']]], - ['gpio_5fmoder_5fmoder2_5fmsk_615',['GPIO_MODER_MODER2_Msk',['../group___peripheral___registers___bits___definition.html#gaf6c01a65d00f6b648984e34f71ce0b83',1,'stm32f407xx_matlab.h']]], - ['gpio_5fmoder_5fmoder2_5fpos_616',['GPIO_MODER_MODER2_Pos',['../group___peripheral___registers___bits___definition.html#ga945f52c8af561a1c9a3358b0e8605ffc',1,'stm32f407xx_matlab.h']]], - ['gpio_5fmoder_5fmoder3_617',['GPIO_MODER_MODER3',['../group___peripheral___registers___bits___definition.html#gae06c9d07a091fb64ab53d0c899a9dda5',1,'stm32f407xx_matlab.h']]], - ['gpio_5fmoder_5fmoder3_5f0_618',['GPIO_MODER_MODER3_0',['../group___peripheral___registers___bits___definition.html#ga4aeeac804c07e25aeff31bebf3a639f6',1,'stm32f407xx_matlab.h']]], - ['gpio_5fmoder_5fmoder3_5f1_619',['GPIO_MODER_MODER3_1',['../group___peripheral___registers___bits___definition.html#gafc09e4958f306ddcb6107942504b45e0',1,'stm32f407xx_matlab.h']]], - ['gpio_5fmoder_5fmoder3_5fmsk_620',['GPIO_MODER_MODER3_Msk',['../group___peripheral___registers___bits___definition.html#ga053851b8f1df3d358a7b07fe8f720a25',1,'stm32f407xx_matlab.h']]], - ['gpio_5fmoder_5fmoder3_5fpos_621',['GPIO_MODER_MODER3_Pos',['../group___peripheral___registers___bits___definition.html#ga0df2c02569d6b84757d70cd5ab99d262',1,'stm32f407xx_matlab.h']]], - ['gpio_5fmoder_5fmoder4_622',['GPIO_MODER_MODER4',['../group___peripheral___registers___bits___definition.html#ga52cf9361d90c863c107cdeb859bd8b41',1,'stm32f407xx_matlab.h']]], - ['gpio_5fmoder_5fmoder4_5f0_623',['GPIO_MODER_MODER4_0',['../group___peripheral___registers___bits___definition.html#ga67276f1aa615d1af388fef7232483795',1,'stm32f407xx_matlab.h']]], - ['gpio_5fmoder_5fmoder4_5f1_624',['GPIO_MODER_MODER4_1',['../group___peripheral___registers___bits___definition.html#ga5203150980865199911d58af22f49567',1,'stm32f407xx_matlab.h']]], - ['gpio_5fmoder_5fmoder4_5fmsk_625',['GPIO_MODER_MODER4_Msk',['../group___peripheral___registers___bits___definition.html#ga0678135cc7fb1e00fe0de880d822fde5',1,'stm32f407xx_matlab.h']]], - ['gpio_5fmoder_5fmoder4_5fpos_626',['GPIO_MODER_MODER4_Pos',['../group___peripheral___registers___bits___definition.html#ga7866ff150289c04d52c808607dabbf9e',1,'stm32f407xx_matlab.h']]], - ['gpio_5fmoder_5fmoder5_627',['GPIO_MODER_MODER5',['../group___peripheral___registers___bits___definition.html#gae94ab55c126ff24572bbff0da5a3f360',1,'stm32f407xx_matlab.h']]], - ['gpio_5fmoder_5fmoder5_5f0_628',['GPIO_MODER_MODER5_0',['../group___peripheral___registers___bits___definition.html#ga62665be9bddb711eedf99c85e37bb5ad',1,'stm32f407xx_matlab.h']]], - ['gpio_5fmoder_5fmoder5_5f1_629',['GPIO_MODER_MODER5_1',['../group___peripheral___registers___bits___definition.html#ga5096355e22b25bd4e6324399d5764630',1,'stm32f407xx_matlab.h']]], - ['gpio_5fmoder_5fmoder5_5fmsk_630',['GPIO_MODER_MODER5_Msk',['../group___peripheral___registers___bits___definition.html#ga9f1827fce38f560f895e4486f1aacaac',1,'stm32f407xx_matlab.h']]], - ['gpio_5fmoder_5fmoder5_5fpos_631',['GPIO_MODER_MODER5_Pos',['../group___peripheral___registers___bits___definition.html#ga84f88cbf25e1defb5f9b99c95797f7ab',1,'stm32f407xx_matlab.h']]], - ['gpio_5fmoder_5fmoder6_632',['GPIO_MODER_MODER6',['../group___peripheral___registers___bits___definition.html#ga97a85a1bb88cf8f730e0de38cb664282',1,'stm32f407xx_matlab.h']]], - ['gpio_5fmoder_5fmoder6_5f0_633',['GPIO_MODER_MODER6_0',['../group___peripheral___registers___bits___definition.html#gaf45f41af21a000ab66da5b99b998deb3',1,'stm32f407xx_matlab.h']]], - ['gpio_5fmoder_5fmoder6_5f1_634',['GPIO_MODER_MODER6_1',['../group___peripheral___registers___bits___definition.html#ga41dfd1f39fe849fe3707ebf2ac0d8371',1,'stm32f407xx_matlab.h']]], - ['gpio_5fmoder_5fmoder6_5fmsk_635',['GPIO_MODER_MODER6_Msk',['../group___peripheral___registers___bits___definition.html#ga83a6d2a5dbd3f6f8447e0082c0e8d6ab',1,'stm32f407xx_matlab.h']]], - ['gpio_5fmoder_5fmoder6_5fpos_636',['GPIO_MODER_MODER6_Pos',['../group___peripheral___registers___bits___definition.html#ga81c3fdecd37cce14983b42d28fc46d27',1,'stm32f407xx_matlab.h']]], - ['gpio_5fmoder_5fmoder7_637',['GPIO_MODER_MODER7',['../group___peripheral___registers___bits___definition.html#ga22dc08ecc39bceba020d8e5949b658e0',1,'stm32f407xx_matlab.h']]], - ['gpio_5fmoder_5fmoder7_5f0_638',['GPIO_MODER_MODER7_0',['../group___peripheral___registers___bits___definition.html#ga585ab6cb29e3763ab8c1e997c55f2b43',1,'stm32f407xx_matlab.h']]], - ['gpio_5fmoder_5fmoder7_5f1_639',['GPIO_MODER_MODER7_1',['../group___peripheral___registers___bits___definition.html#ga2b5cca014fc55f64cdbbb42ea0515e05',1,'stm32f407xx_matlab.h']]], - ['gpio_5fmoder_5fmoder7_5fmsk_640',['GPIO_MODER_MODER7_Msk',['../group___peripheral___registers___bits___definition.html#gae685da5b1c5c085e69be64ecf0b65ec5',1,'stm32f407xx_matlab.h']]], - ['gpio_5fmoder_5fmoder7_5fpos_641',['GPIO_MODER_MODER7_Pos',['../group___peripheral___registers___bits___definition.html#gaf586709481b1450208dae7d9e53b9057',1,'stm32f407xx_matlab.h']]], - ['gpio_5fmoder_5fmoder8_642',['GPIO_MODER_MODER8',['../group___peripheral___registers___bits___definition.html#gac41f2174ef4444c685ea92da1258c678',1,'stm32f407xx_matlab.h']]], - ['gpio_5fmoder_5fmoder8_5f0_643',['GPIO_MODER_MODER8_0',['../group___peripheral___registers___bits___definition.html#ga2cdb8e55aa223af568ae12d316a22f8d',1,'stm32f407xx_matlab.h']]], - ['gpio_5fmoder_5fmoder8_5f1_644',['GPIO_MODER_MODER8_1',['../group___peripheral___registers___bits___definition.html#ga0729411ccd74a91cdd0f23adada25782',1,'stm32f407xx_matlab.h']]], - ['gpio_5fmoder_5fmoder8_5fmsk_645',['GPIO_MODER_MODER8_Msk',['../group___peripheral___registers___bits___definition.html#gaaddfeb2d4f139bd00fdcd2ce538f2087',1,'stm32f407xx_matlab.h']]], - ['gpio_5fmoder_5fmoder8_5fpos_646',['GPIO_MODER_MODER8_Pos',['../group___peripheral___registers___bits___definition.html#ga80e5f1f7c986ee7f31178901cab442ab',1,'stm32f407xx_matlab.h']]], - ['gpio_5fmoder_5fmoder9_647',['GPIO_MODER_MODER9',['../group___peripheral___registers___bits___definition.html#ga5d4ed9018bf72565bab1d08c476fed20',1,'stm32f407xx_matlab.h']]], - ['gpio_5fmoder_5fmoder9_5f0_648',['GPIO_MODER_MODER9_0',['../group___peripheral___registers___bits___definition.html#gaea7c7ec787b1ee1ae7e0b4da216eb418',1,'stm32f407xx_matlab.h']]], - ['gpio_5fmoder_5fmoder9_5f1_649',['GPIO_MODER_MODER9_1',['../group___peripheral___registers___bits___definition.html#gaa5cd33689071b7af70ece64a371645df',1,'stm32f407xx_matlab.h']]], - ['gpio_5fmoder_5fmoder9_5fmsk_650',['GPIO_MODER_MODER9_Msk',['../group___peripheral___registers___bits___definition.html#gafdcb7c58d623c51ababeb5917430132b',1,'stm32f407xx_matlab.h']]], - ['gpio_5fmoder_5fmoder9_5fpos_651',['GPIO_MODER_MODER9_Pos',['../group___peripheral___registers___bits___definition.html#gaf310164aef074cbdda2af5b0af223139',1,'stm32f407xx_matlab.h']]], - ['gpio_5fodr_5fod0_652',['GPIO_ODR_OD0',['../group___peripheral___registers___bits___definition.html#ga7e7937b0a505e771361804a211c7656f',1,'stm32f407xx_matlab.h']]], - ['gpio_5fodr_5fod0_5fmsk_653',['GPIO_ODR_OD0_Msk',['../group___peripheral___registers___bits___definition.html#ga5c08637123e42a30fbf4e9e49feb650f',1,'stm32f407xx_matlab.h']]], - ['gpio_5fodr_5fod0_5fpos_654',['GPIO_ODR_OD0_Pos',['../group___peripheral___registers___bits___definition.html#gade6bff88e55b2428269c90ebde121d31',1,'stm32f407xx_matlab.h']]], - ['gpio_5fodr_5fod1_655',['GPIO_ODR_OD1',['../group___peripheral___registers___bits___definition.html#ga104dff849ee2c6a0b58777a336912583',1,'stm32f407xx_matlab.h']]], - ['gpio_5fodr_5fod10_656',['GPIO_ODR_OD10',['../group___peripheral___registers___bits___definition.html#gac5c6ba137db2753434a1253e111ff6a2',1,'stm32f407xx_matlab.h']]], - ['gpio_5fodr_5fod10_5fmsk_657',['GPIO_ODR_OD10_Msk',['../group___peripheral___registers___bits___definition.html#gad5e3aca353a76254fd8d02debede2fae',1,'stm32f407xx_matlab.h']]], - ['gpio_5fodr_5fod10_5fpos_658',['GPIO_ODR_OD10_Pos',['../group___peripheral___registers___bits___definition.html#gaa47f67a9087ba57c2144a8a19d597bf5',1,'stm32f407xx_matlab.h']]], - ['gpio_5fodr_5fod11_659',['GPIO_ODR_OD11',['../group___peripheral___registers___bits___definition.html#ga5e7e487eb914e276c92534eab7b1efdc',1,'stm32f407xx_matlab.h']]], - ['gpio_5fodr_5fod11_5fmsk_660',['GPIO_ODR_OD11_Msk',['../group___peripheral___registers___bits___definition.html#ga5432eff2238e4c6adf1f5c5cda9a797d',1,'stm32f407xx_matlab.h']]], - ['gpio_5fodr_5fod11_5fpos_661',['GPIO_ODR_OD11_Pos',['../group___peripheral___registers___bits___definition.html#gaf4f6824376eb5f7f0185580a780d5ecf',1,'stm32f407xx_matlab.h']]], - ['gpio_5fodr_5fod12_662',['GPIO_ODR_OD12',['../group___peripheral___registers___bits___definition.html#gac42a77f0ced79d51a5952d929a7e0528',1,'stm32f407xx_matlab.h']]], - ['gpio_5fodr_5fod12_5fmsk_663',['GPIO_ODR_OD12_Msk',['../group___peripheral___registers___bits___definition.html#gae85ad24a6fcfac506e330e0f896b1e23',1,'stm32f407xx_matlab.h']]], - ['gpio_5fodr_5fod12_5fpos_664',['GPIO_ODR_OD12_Pos',['../group___peripheral___registers___bits___definition.html#ga0a3eca32e4b8eca5b984c371fc118c44',1,'stm32f407xx_matlab.h']]], - ['gpio_5fodr_5fod13_665',['GPIO_ODR_OD13',['../group___peripheral___registers___bits___definition.html#ga582584ba2995b3b9993728b02a98f2c1',1,'stm32f407xx_matlab.h']]], - ['gpio_5fodr_5fod13_5fmsk_666',['GPIO_ODR_OD13_Msk',['../group___peripheral___registers___bits___definition.html#ga93481785eb62b6669b8aceb1907b8e13',1,'stm32f407xx_matlab.h']]], - ['gpio_5fodr_5fod13_5fpos_667',['GPIO_ODR_OD13_Pos',['../group___peripheral___registers___bits___definition.html#ga29598cda6568737ee82992f76d07c45c',1,'stm32f407xx_matlab.h']]], - ['gpio_5fodr_5fod14_668',['GPIO_ODR_OD14',['../group___peripheral___registers___bits___definition.html#ga6c2ec83ded91512630244d2d1e1c300b',1,'stm32f407xx_matlab.h']]], - ['gpio_5fodr_5fod14_5fmsk_669',['GPIO_ODR_OD14_Msk',['../group___peripheral___registers___bits___definition.html#gaf028b3836cb425dab56d38dd1df17062',1,'stm32f407xx_matlab.h']]], - ['gpio_5fodr_5fod14_5fpos_670',['GPIO_ODR_OD14_Pos',['../group___peripheral___registers___bits___definition.html#gafd02d3bb351676e31027d8bad0c8eb70',1,'stm32f407xx_matlab.h']]], - ['gpio_5fodr_5fod15_671',['GPIO_ODR_OD15',['../group___peripheral___registers___bits___definition.html#ga7e411f3d6f91e5218dc9ca1b6739f053',1,'stm32f407xx_matlab.h']]], - ['gpio_5fodr_5fod15_5fmsk_672',['GPIO_ODR_OD15_Msk',['../group___peripheral___registers___bits___definition.html#ga26a07f39cf1e55d17f56df37cd875288',1,'stm32f407xx_matlab.h']]], - ['gpio_5fodr_5fod15_5fpos_673',['GPIO_ODR_OD15_Pos',['../group___peripheral___registers___bits___definition.html#gaa3bac5a39dda0f70c8fb9de38450eb21',1,'stm32f407xx_matlab.h']]], - ['gpio_5fodr_5fod1_5fmsk_674',['GPIO_ODR_OD1_Msk',['../group___peripheral___registers___bits___definition.html#ga284902fc92059f740dc599945071d767',1,'stm32f407xx_matlab.h']]], - ['gpio_5fodr_5fod1_5fpos_675',['GPIO_ODR_OD1_Pos',['../group___peripheral___registers___bits___definition.html#ga60dfdab58aa53c6790eb545f50f92722',1,'stm32f407xx_matlab.h']]], - ['gpio_5fodr_5fod2_676',['GPIO_ODR_OD2',['../group___peripheral___registers___bits___definition.html#gaff3ff4b6fa52aac52991053b26d8dd80',1,'stm32f407xx_matlab.h']]], - ['gpio_5fodr_5fod2_5fmsk_677',['GPIO_ODR_OD2_Msk',['../group___peripheral___registers___bits___definition.html#ga7b7c3794b7948875eea27a4b09bac063',1,'stm32f407xx_matlab.h']]], - ['gpio_5fodr_5fod2_5fpos_678',['GPIO_ODR_OD2_Pos',['../group___peripheral___registers___bits___definition.html#ga9ea388b190f9040a9657d9b395471596',1,'stm32f407xx_matlab.h']]], - ['gpio_5fodr_5fod3_679',['GPIO_ODR_OD3',['../group___peripheral___registers___bits___definition.html#gaba5790d50582befba7f91037df94b159',1,'stm32f407xx_matlab.h']]], - ['gpio_5fodr_5fod3_5fmsk_680',['GPIO_ODR_OD3_Msk',['../group___peripheral___registers___bits___definition.html#ga6b3312000af1016c233b04590b8c054c',1,'stm32f407xx_matlab.h']]], - ['gpio_5fodr_5fod3_5fpos_681',['GPIO_ODR_OD3_Pos',['../group___peripheral___registers___bits___definition.html#ga3a4ae35ae856330bc937251fd9ccf01c',1,'stm32f407xx_matlab.h']]], - ['gpio_5fodr_5fod4_682',['GPIO_ODR_OD4',['../group___peripheral___registers___bits___definition.html#gacd275e221a79cf7a3ac0c98ee15af3c5',1,'stm32f407xx_matlab.h']]], - ['gpio_5fodr_5fod4_5fmsk_683',['GPIO_ODR_OD4_Msk',['../group___peripheral___registers___bits___definition.html#gab27b415dc46e3832b021eb0d697f1b13',1,'stm32f407xx_matlab.h']]], - ['gpio_5fodr_5fod4_5fpos_684',['GPIO_ODR_OD4_Pos',['../group___peripheral___registers___bits___definition.html#ga91e0a70767add938306339ea3f3c8df5',1,'stm32f407xx_matlab.h']]], - ['gpio_5fodr_5fod5_685',['GPIO_ODR_OD5',['../group___peripheral___registers___bits___definition.html#ga4046ad484b858f3c49eb0449f45e3af5',1,'stm32f407xx_matlab.h']]], - ['gpio_5fodr_5fod5_5fmsk_686',['GPIO_ODR_OD5_Msk',['../group___peripheral___registers___bits___definition.html#ga530c4cdcbeb559b2f990a237b4765631',1,'stm32f407xx_matlab.h']]], - ['gpio_5fodr_5fod5_5fpos_687',['GPIO_ODR_OD5_Pos',['../group___peripheral___registers___bits___definition.html#gada7f2c3690272b52bde0c22223d39dff',1,'stm32f407xx_matlab.h']]], - ['gpio_5fodr_5fod6_688',['GPIO_ODR_OD6',['../group___peripheral___registers___bits___definition.html#ga34550e0c5098cf24a2ab86e2ecc67c14',1,'stm32f407xx_matlab.h']]], - ['gpio_5fodr_5fod6_5fmsk_689',['GPIO_ODR_OD6_Msk',['../group___peripheral___registers___bits___definition.html#ga965661d93777219b16fee1d210831622',1,'stm32f407xx_matlab.h']]], - ['gpio_5fodr_5fod6_5fpos_690',['GPIO_ODR_OD6_Pos',['../group___peripheral___registers___bits___definition.html#gaeaffa5b5eec9c90b552ebef5fc13828a',1,'stm32f407xx_matlab.h']]], - ['gpio_5fodr_5fod7_691',['GPIO_ODR_OD7',['../group___peripheral___registers___bits___definition.html#gaba7559603648f95b76d128f0a637675c',1,'stm32f407xx_matlab.h']]], - ['gpio_5fodr_5fod7_5fmsk_692',['GPIO_ODR_OD7_Msk',['../group___peripheral___registers___bits___definition.html#gad697f4e743a67aad8ad37560a176ed25',1,'stm32f407xx_matlab.h']]], - ['gpio_5fodr_5fod7_5fpos_693',['GPIO_ODR_OD7_Pos',['../group___peripheral___registers___bits___definition.html#ga34bf70d7723a8e809a7ec2baba5583b1',1,'stm32f407xx_matlab.h']]], - ['gpio_5fodr_5fod8_694',['GPIO_ODR_OD8',['../group___peripheral___registers___bits___definition.html#ga60a61ea7de95ccdcb674e8b972969a1f',1,'stm32f407xx_matlab.h']]], - ['gpio_5fodr_5fod8_5fmsk_695',['GPIO_ODR_OD8_Msk',['../group___peripheral___registers___bits___definition.html#gacad5442c3f20d25fdb0b24d78d1eab5b',1,'stm32f407xx_matlab.h']]], - ['gpio_5fodr_5fod8_5fpos_696',['GPIO_ODR_OD8_Pos',['../group___peripheral___registers___bits___definition.html#gad52cedd015ac8e511f7f2cdda0e6c4ca',1,'stm32f407xx_matlab.h']]], - ['gpio_5fodr_5fod9_697',['GPIO_ODR_OD9',['../group___peripheral___registers___bits___definition.html#gaa3bfdb1e3526890736b0c1238adda99c',1,'stm32f407xx_matlab.h']]], - ['gpio_5fodr_5fod9_5fmsk_698',['GPIO_ODR_OD9_Msk',['../group___peripheral___registers___bits___definition.html#ga871215a04902f7abbc8e4753aa523d87',1,'stm32f407xx_matlab.h']]], - ['gpio_5fodr_5fod9_5fpos_699',['GPIO_ODR_OD9_Pos',['../group___peripheral___registers___bits___definition.html#ga41b713787d20ffacdc2c2b4f6fe05e4e',1,'stm32f407xx_matlab.h']]], - ['gpio_5fodr_5fodr_5f0_700',['GPIO_ODR_ODR_0',['../group___peripheral___registers___bits___definition.html#ga42386f40895bc86ff49eefe80708bbc6',1,'stm32f407xx_matlab.h']]], - ['gpio_5fodr_5fodr_5f1_701',['GPIO_ODR_ODR_1',['../group___peripheral___registers___bits___definition.html#ga7680b11616859cd0f462703224511fb2',1,'stm32f407xx_matlab.h']]], - ['gpio_5fodr_5fodr_5f10_702',['GPIO_ODR_ODR_10',['../group___peripheral___registers___bits___definition.html#ga5e2817e62685ec81d3ca6674d8e75187',1,'stm32f407xx_matlab.h']]], - ['gpio_5fodr_5fodr_5f11_703',['GPIO_ODR_ODR_11',['../group___peripheral___registers___bits___definition.html#ga6022058342e528d097d2d352ccb3210c',1,'stm32f407xx_matlab.h']]], - ['gpio_5fodr_5fodr_5f12_704',['GPIO_ODR_ODR_12',['../group___peripheral___registers___bits___definition.html#ga6df2c7bfa97e4536c3c112fa6dc00992',1,'stm32f407xx_matlab.h']]], - ['gpio_5fodr_5fodr_5f13_705',['GPIO_ODR_ODR_13',['../group___peripheral___registers___bits___definition.html#gab7a51e706f1931e6ac3ddd117242da23',1,'stm32f407xx_matlab.h']]], - ['gpio_5fodr_5fodr_5f14_706',['GPIO_ODR_ODR_14',['../group___peripheral___registers___bits___definition.html#ga090cea405c38fd8c48f77e561deaaa07',1,'stm32f407xx_matlab.h']]], - ['gpio_5fodr_5fodr_5f15_707',['GPIO_ODR_ODR_15',['../group___peripheral___registers___bits___definition.html#ga527b7d78707f17edfe826be72aa59fdc',1,'stm32f407xx_matlab.h']]], - ['gpio_5fodr_5fodr_5f2_708',['GPIO_ODR_ODR_2',['../group___peripheral___registers___bits___definition.html#gae93b86fd4c1bfcfafc42bf820c17c019',1,'stm32f407xx_matlab.h']]], - ['gpio_5fodr_5fodr_5f3_709',['GPIO_ODR_ODR_3',['../group___peripheral___registers___bits___definition.html#ga3fffcd41fa6347ce4b61e6abbae55c7a',1,'stm32f407xx_matlab.h']]], - ['gpio_5fodr_5fodr_5f4_710',['GPIO_ODR_ODR_4',['../group___peripheral___registers___bits___definition.html#gac9b5f55a1f9dda2285576a276d0fb0e2',1,'stm32f407xx_matlab.h']]], - ['gpio_5fodr_5fodr_5f5_711',['GPIO_ODR_ODR_5',['../group___peripheral___registers___bits___definition.html#ga6723e4adf0b6b333f74e15e00a60a4db',1,'stm32f407xx_matlab.h']]], - ['gpio_5fodr_5fodr_5f6_712',['GPIO_ODR_ODR_6',['../group___peripheral___registers___bits___definition.html#ga202234d8f40086f6343e30597b52c838',1,'stm32f407xx_matlab.h']]], - ['gpio_5fodr_5fodr_5f7_713',['GPIO_ODR_ODR_7',['../group___peripheral___registers___bits___definition.html#ga3c713b846aa56d5a31b2e4525d705679',1,'stm32f407xx_matlab.h']]], - ['gpio_5fodr_5fodr_5f8_714',['GPIO_ODR_ODR_8',['../group___peripheral___registers___bits___definition.html#gaabe9c0b33000bbfe71f107cce0af0eb2',1,'stm32f407xx_matlab.h']]], - ['gpio_5fodr_5fodr_5f9_715',['GPIO_ODR_ODR_9',['../group___peripheral___registers___bits___definition.html#ga25f53481a7575ebb0eb5477950673188',1,'stm32f407xx_matlab.h']]], - ['gpio_5fospeeder_5fospeedr0_716',['GPIO_OSPEEDER_OSPEEDR0',['../group___peripheral___registers___bits___definition.html#ga86a137cc8e566a0da86e2fd4778938a6',1,'stm32f407xx_matlab.h']]], - ['gpio_5fospeeder_5fospeedr0_5f0_717',['GPIO_OSPEEDER_OSPEEDR0_0',['../group___peripheral___registers___bits___definition.html#ga95ff622f2b5941ce7202fe97a6e8c730',1,'stm32f407xx_matlab.h']]], - ['gpio_5fospeeder_5fospeedr0_5f1_718',['GPIO_OSPEEDER_OSPEEDR0_1',['../group___peripheral___registers___bits___definition.html#ga5a8e561180cdfcb7440a017d2aa10f59',1,'stm32f407xx_matlab.h']]], - ['gpio_5fospeeder_5fospeedr1_719',['GPIO_OSPEEDER_OSPEEDR1',['../group___peripheral___registers___bits___definition.html#ga9aca2c7cf73dd7a08fee8ae9a675c1d5',1,'stm32f407xx_matlab.h']]], - ['gpio_5fospeeder_5fospeedr10_720',['GPIO_OSPEEDER_OSPEEDR10',['../group___peripheral___registers___bits___definition.html#ga7f368a4fe9f84a2a1f75127cd92de706',1,'stm32f407xx_matlab.h']]], - ['gpio_5fospeeder_5fospeedr10_5f0_721',['GPIO_OSPEEDER_OSPEEDR10_0',['../group___peripheral___registers___bits___definition.html#gad24e2db3605c0510221a5d6cc18de45d',1,'stm32f407xx_matlab.h']]], - ['gpio_5fospeeder_5fospeedr10_5f1_722',['GPIO_OSPEEDER_OSPEEDR10_1',['../group___peripheral___registers___bits___definition.html#gac0b5fe166b79464e9419092b50a216e8',1,'stm32f407xx_matlab.h']]], - ['gpio_5fospeeder_5fospeedr11_723',['GPIO_OSPEEDER_OSPEEDR11',['../group___peripheral___registers___bits___definition.html#ga6f6fbff92ca95c7b4b49b773993af08f',1,'stm32f407xx_matlab.h']]], - ['gpio_5fospeeder_5fospeedr11_5f0_724',['GPIO_OSPEEDER_OSPEEDR11_0',['../group___peripheral___registers___bits___definition.html#ga7413457e1249fedd60208f6d1fe66fec',1,'stm32f407xx_matlab.h']]], - ['gpio_5fospeeder_5fospeedr11_5f1_725',['GPIO_OSPEEDER_OSPEEDR11_1',['../group___peripheral___registers___bits___definition.html#gad5a0177db55f86818a42240bf188c0bc',1,'stm32f407xx_matlab.h']]], - ['gpio_5fospeeder_5fospeedr12_726',['GPIO_OSPEEDER_OSPEEDR12',['../group___peripheral___registers___bits___definition.html#gac9928dcdc592ee959941c97aed702a99',1,'stm32f407xx_matlab.h']]], - ['gpio_5fospeeder_5fospeedr12_5f0_727',['GPIO_OSPEEDER_OSPEEDR12_0',['../group___peripheral___registers___bits___definition.html#ga68d9034e325bf95773f70a9cc94598af',1,'stm32f407xx_matlab.h']]], - ['gpio_5fospeeder_5fospeedr12_5f1_728',['GPIO_OSPEEDER_OSPEEDR12_1',['../group___peripheral___registers___bits___definition.html#ga225f0a354cd3c2391ed922b08dbc0cae',1,'stm32f407xx_matlab.h']]], - ['gpio_5fospeeder_5fospeedr13_729',['GPIO_OSPEEDER_OSPEEDR13',['../group___peripheral___registers___bits___definition.html#ga09d3845b5e708a7636cddf01c5a30468',1,'stm32f407xx_matlab.h']]], - ['gpio_5fospeeder_5fospeedr13_5f0_730',['GPIO_OSPEEDER_OSPEEDR13_0',['../group___peripheral___registers___bits___definition.html#ga93ce0e08aefefa639657d0ca1a169557',1,'stm32f407xx_matlab.h']]], - ['gpio_5fospeeder_5fospeedr13_5f1_731',['GPIO_OSPEEDER_OSPEEDR13_1',['../group___peripheral___registers___bits___definition.html#ga2fee18398176eeceef1a6a0229d81029',1,'stm32f407xx_matlab.h']]], - ['gpio_5fospeeder_5fospeedr14_732',['GPIO_OSPEEDER_OSPEEDR14',['../group___peripheral___registers___bits___definition.html#gae956b8918d07e914a3f9861de501623f',1,'stm32f407xx_matlab.h']]], - ['gpio_5fospeeder_5fospeedr14_5f0_733',['GPIO_OSPEEDER_OSPEEDR14_0',['../group___peripheral___registers___bits___definition.html#gafcec6386ada8c016b4696b853a6d1ff1',1,'stm32f407xx_matlab.h']]], - ['gpio_5fospeeder_5fospeedr14_5f1_734',['GPIO_OSPEEDER_OSPEEDR14_1',['../group___peripheral___registers___bits___definition.html#gae8fb23e47faf2dd2b69a22e36c4ea56d',1,'stm32f407xx_matlab.h']]], - ['gpio_5fospeeder_5fospeedr15_735',['GPIO_OSPEEDER_OSPEEDR15',['../group___peripheral___registers___bits___definition.html#ga9b405fe1beed00abecfb3d83b9f94b65',1,'stm32f407xx_matlab.h']]], - ['gpio_5fospeeder_5fospeedr15_5f0_736',['GPIO_OSPEEDER_OSPEEDR15_0',['../group___peripheral___registers___bits___definition.html#ga782862d03460b05a56d3287c971aabc8',1,'stm32f407xx_matlab.h']]], - ['gpio_5fospeeder_5fospeedr15_5f1_737',['GPIO_OSPEEDER_OSPEEDR15_1',['../group___peripheral___registers___bits___definition.html#ga929ae0a4ff8f30c45042715a73ab1ad7',1,'stm32f407xx_matlab.h']]], - ['gpio_5fospeeder_5fospeedr1_5f0_738',['GPIO_OSPEEDER_OSPEEDR1_0',['../group___peripheral___registers___bits___definition.html#ga5dd10c0d3419e2d2fda1af77fbc28156',1,'stm32f407xx_matlab.h']]], - ['gpio_5fospeeder_5fospeedr1_5f1_739',['GPIO_OSPEEDER_OSPEEDR1_1',['../group___peripheral___registers___bits___definition.html#ga4ebe740312db53a7d49ff7f78436bcb6',1,'stm32f407xx_matlab.h']]], - ['gpio_5fospeeder_5fospeedr2_740',['GPIO_OSPEEDER_OSPEEDR2',['../group___peripheral___registers___bits___definition.html#ga9f3dd6eabaf2dee10a45718bf9214bff',1,'stm32f407xx_matlab.h']]], - ['gpio_5fospeeder_5fospeedr2_5f0_741',['GPIO_OSPEEDER_OSPEEDR2_0',['../group___peripheral___registers___bits___definition.html#ga285b9f4328a29f624945f8fc57daab0e',1,'stm32f407xx_matlab.h']]], - ['gpio_5fospeeder_5fospeedr2_5f1_742',['GPIO_OSPEEDER_OSPEEDR2_1',['../group___peripheral___registers___bits___definition.html#gaeb41ac1ecdc620a7888e9714f36611c2',1,'stm32f407xx_matlab.h']]], - ['gpio_5fospeeder_5fospeedr3_743',['GPIO_OSPEEDER_OSPEEDR3',['../group___peripheral___registers___bits___definition.html#ga3bd77104c298e2cc79608954ed8a81e6',1,'stm32f407xx_matlab.h']]], - ['gpio_5fospeeder_5fospeedr3_5f0_744',['GPIO_OSPEEDER_OSPEEDR3_0',['../group___peripheral___registers___bits___definition.html#ga86ad8f39a6399526c2a06f5e481b7edd',1,'stm32f407xx_matlab.h']]], - ['gpio_5fospeeder_5fospeedr3_5f1_745',['GPIO_OSPEEDER_OSPEEDR3_1',['../group___peripheral___registers___bits___definition.html#ga4cbbc6c634d9f64d2959bfce25e475e3',1,'stm32f407xx_matlab.h']]], - ['gpio_5fospeeder_5fospeedr4_746',['GPIO_OSPEEDER_OSPEEDR4',['../group___peripheral___registers___bits___definition.html#gae993f7764c1e10e2f5022cba2a081f97',1,'stm32f407xx_matlab.h']]], - ['gpio_5fospeeder_5fospeedr4_5f0_747',['GPIO_OSPEEDER_OSPEEDR4_0',['../group___peripheral___registers___bits___definition.html#ga1e6579b81f162ca8d4b8ee6690b258e9',1,'stm32f407xx_matlab.h']]], - ['gpio_5fospeeder_5fospeedr4_5f1_748',['GPIO_OSPEEDER_OSPEEDR4_1',['../group___peripheral___registers___bits___definition.html#ga56650b0113cbb5ed50903e684abfdabc',1,'stm32f407xx_matlab.h']]], - ['gpio_5fospeeder_5fospeedr5_749',['GPIO_OSPEEDER_OSPEEDR5',['../group___peripheral___registers___bits___definition.html#gaa6e84a83dd64be450a33a67c9ba44add',1,'stm32f407xx_matlab.h']]], - ['gpio_5fospeeder_5fospeedr5_5f0_750',['GPIO_OSPEEDER_OSPEEDR5_0',['../group___peripheral___registers___bits___definition.html#ga0ee63c65224da433a0f588bdd579c88d',1,'stm32f407xx_matlab.h']]], - ['gpio_5fospeeder_5fospeedr5_5f1_751',['GPIO_OSPEEDER_OSPEEDR5_1',['../group___peripheral___registers___bits___definition.html#ga9feeadb829cbfbcc7f5ff5aa614e35de',1,'stm32f407xx_matlab.h']]], - ['gpio_5fospeeder_5fospeedr6_752',['GPIO_OSPEEDER_OSPEEDR6',['../group___peripheral___registers___bits___definition.html#gaa153220faa507b53170bd49dcffcfc76',1,'stm32f407xx_matlab.h']]], - ['gpio_5fospeeder_5fospeedr6_5f0_753',['GPIO_OSPEEDER_OSPEEDR6_0',['../group___peripheral___registers___bits___definition.html#ga314fae4f204824abf26545482246eb46',1,'stm32f407xx_matlab.h']]], - ['gpio_5fospeeder_5fospeedr6_5f1_754',['GPIO_OSPEEDER_OSPEEDR6_1',['../group___peripheral___registers___bits___definition.html#gad5502c629c3894c58a5e3e5e4398f92b',1,'stm32f407xx_matlab.h']]], - ['gpio_5fospeeder_5fospeedr7_755',['GPIO_OSPEEDER_OSPEEDR7',['../group___peripheral___registers___bits___definition.html#ga187b9c0a07272ef24ff4e579c2c724a9',1,'stm32f407xx_matlab.h']]], - ['gpio_5fospeeder_5fospeedr7_5f0_756',['GPIO_OSPEEDER_OSPEEDR7_0',['../group___peripheral___registers___bits___definition.html#gaa351c9cc66134dd2077fe4936e10068e',1,'stm32f407xx_matlab.h']]], - ['gpio_5fospeeder_5fospeedr7_5f1_757',['GPIO_OSPEEDER_OSPEEDR7_1',['../group___peripheral___registers___bits___definition.html#ga5824b9a56d3ab570c90c02e959f8e8a3',1,'stm32f407xx_matlab.h']]], - ['gpio_5fospeeder_5fospeedr8_758',['GPIO_OSPEEDER_OSPEEDR8',['../group___peripheral___registers___bits___definition.html#ga57fdec64829712f410b7099168d03335',1,'stm32f407xx_matlab.h']]], - ['gpio_5fospeeder_5fospeedr8_5f0_759',['GPIO_OSPEEDER_OSPEEDR8_0',['../group___peripheral___registers___bits___definition.html#ga00e257135823303b40c2dfe2054c72e6',1,'stm32f407xx_matlab.h']]], - ['gpio_5fospeeder_5fospeedr8_5f1_760',['GPIO_OSPEEDER_OSPEEDR8_1',['../group___peripheral___registers___bits___definition.html#gab026b036652fcab5dbec7fcccd8ec117',1,'stm32f407xx_matlab.h']]], - ['gpio_5fospeeder_5fospeedr9_761',['GPIO_OSPEEDER_OSPEEDR9',['../group___peripheral___registers___bits___definition.html#gaf2974e9de8b939e683976d3244f946c5',1,'stm32f407xx_matlab.h']]], - ['gpio_5fospeeder_5fospeedr9_5f0_762',['GPIO_OSPEEDER_OSPEEDR9_0',['../group___peripheral___registers___bits___definition.html#ga922dc2241064ba91a32163b52dc979a1',1,'stm32f407xx_matlab.h']]], - ['gpio_5fospeeder_5fospeedr9_5f1_763',['GPIO_OSPEEDER_OSPEEDR9_1',['../group___peripheral___registers___bits___definition.html#ga8958bf41efda58bc0c216496c3523a95',1,'stm32f407xx_matlab.h']]], - ['gpio_5fospeedr_5fospeed0_764',['GPIO_OSPEEDR_OSPEED0',['../group___peripheral___registers___bits___definition.html#ga25d567c6d24df0adb6402498fd5eb582',1,'stm32f407xx_matlab.h']]], - ['gpio_5fospeedr_5fospeed0_5f0_765',['GPIO_OSPEEDR_OSPEED0_0',['../group___peripheral___registers___bits___definition.html#gae999b23bc1e7f750599e3919db67bba7',1,'stm32f407xx_matlab.h']]], - ['gpio_5fospeedr_5fospeed0_5f1_766',['GPIO_OSPEEDR_OSPEED0_1',['../group___peripheral___registers___bits___definition.html#gaa211d91a2e8fa199d4d1c64e20c2283c',1,'stm32f407xx_matlab.h']]], - ['gpio_5fospeedr_5fospeed0_5fmsk_767',['GPIO_OSPEEDR_OSPEED0_Msk',['../group___peripheral___registers___bits___definition.html#gab411afa3d01185fcac7de1834855b03b',1,'stm32f407xx_matlab.h']]], - ['gpio_5fospeedr_5fospeed0_5fpos_768',['GPIO_OSPEEDR_OSPEED0_Pos',['../group___peripheral___registers___bits___definition.html#ga129f816361ac723f130c2757ab606de2',1,'stm32f407xx_matlab.h']]], - ['gpio_5fospeedr_5fospeed1_769',['GPIO_OSPEEDR_OSPEED1',['../group___peripheral___registers___bits___definition.html#gab8996628496af3a04fb060e7be6b4af6',1,'stm32f407xx_matlab.h']]], - ['gpio_5fospeedr_5fospeed10_770',['GPIO_OSPEEDR_OSPEED10',['../group___peripheral___registers___bits___definition.html#gaa0d96748028e1d2c05fb5a12d6ec6148',1,'stm32f407xx_matlab.h']]], - ['gpio_5fospeedr_5fospeed10_5f0_771',['GPIO_OSPEEDR_OSPEED10_0',['../group___peripheral___registers___bits___definition.html#gae4af74162b730df90c198dd5375c93db',1,'stm32f407xx_matlab.h']]], - ['gpio_5fospeedr_5fospeed10_5f1_772',['GPIO_OSPEEDR_OSPEED10_1',['../group___peripheral___registers___bits___definition.html#gac42c58e1c4f708bb1702b980d7335481',1,'stm32f407xx_matlab.h']]], - ['gpio_5fospeedr_5fospeed10_5fmsk_773',['GPIO_OSPEEDR_OSPEED10_Msk',['../group___peripheral___registers___bits___definition.html#ga7aa2187e9c9634216889077d878c85ae',1,'stm32f407xx_matlab.h']]], - ['gpio_5fospeedr_5fospeed10_5fpos_774',['GPIO_OSPEEDR_OSPEED10_Pos',['../group___peripheral___registers___bits___definition.html#ga4fbf963f1c171fe8902f5b81b6e45e6e',1,'stm32f407xx_matlab.h']]], - ['gpio_5fospeedr_5fospeed11_775',['GPIO_OSPEEDR_OSPEED11',['../group___peripheral___registers___bits___definition.html#gae71fee4a9fee0076207522f7b05d3e7b',1,'stm32f407xx_matlab.h']]], - ['gpio_5fospeedr_5fospeed11_5f0_776',['GPIO_OSPEEDR_OSPEED11_0',['../group___peripheral___registers___bits___definition.html#gaac1765e06791c8f44a8ab2771ce6e3e0',1,'stm32f407xx_matlab.h']]], - ['gpio_5fospeedr_5fospeed11_5f1_777',['GPIO_OSPEEDR_OSPEED11_1',['../group___peripheral___registers___bits___definition.html#gad48d309936025096bfc6cb30fa37464c',1,'stm32f407xx_matlab.h']]], - ['gpio_5fospeedr_5fospeed11_5fmsk_778',['GPIO_OSPEEDR_OSPEED11_Msk',['../group___peripheral___registers___bits___definition.html#gaffc4df43b3ca66616ef75c75d828031f',1,'stm32f407xx_matlab.h']]], - ['gpio_5fospeedr_5fospeed11_5fpos_779',['GPIO_OSPEEDR_OSPEED11_Pos',['../group___peripheral___registers___bits___definition.html#gab897b530b59c6f2f54305fb9db56fa9d',1,'stm32f407xx_matlab.h']]], - ['gpio_5fospeedr_5fospeed12_780',['GPIO_OSPEEDR_OSPEED12',['../group___peripheral___registers___bits___definition.html#ga91c0b6ceee5147b85871df78f1b7ae38',1,'stm32f407xx_matlab.h']]], - ['gpio_5fospeedr_5fospeed12_5f0_781',['GPIO_OSPEEDR_OSPEED12_0',['../group___peripheral___registers___bits___definition.html#ga227ef84ae7d0d0ed7f2e01c26804ad0b',1,'stm32f407xx_matlab.h']]], - ['gpio_5fospeedr_5fospeed12_5f1_782',['GPIO_OSPEEDR_OSPEED12_1',['../group___peripheral___registers___bits___definition.html#ga42e694529900596202d4cdd7ba188427',1,'stm32f407xx_matlab.h']]], - ['gpio_5fospeedr_5fospeed12_5fmsk_783',['GPIO_OSPEEDR_OSPEED12_Msk',['../group___peripheral___registers___bits___definition.html#ga941e03858f17e677f54ee229faacdeaa',1,'stm32f407xx_matlab.h']]], - ['gpio_5fospeedr_5fospeed12_5fpos_784',['GPIO_OSPEEDR_OSPEED12_Pos',['../group___peripheral___registers___bits___definition.html#ga7326dbd78a260f065b3df743fbea3054',1,'stm32f407xx_matlab.h']]], - ['gpio_5fospeedr_5fospeed13_785',['GPIO_OSPEEDR_OSPEED13',['../group___peripheral___registers___bits___definition.html#gabec7c4b2c0464c31b94d819b458294bc',1,'stm32f407xx_matlab.h']]], - ['gpio_5fospeedr_5fospeed13_5f0_786',['GPIO_OSPEEDR_OSPEED13_0',['../group___peripheral___registers___bits___definition.html#ga27d214e42ae822601fe8469c5310337d',1,'stm32f407xx_matlab.h']]], - ['gpio_5fospeedr_5fospeed13_5f1_787',['GPIO_OSPEEDR_OSPEED13_1',['../group___peripheral___registers___bits___definition.html#gad2ce26af8af11b3592c5e70fddf24a1a',1,'stm32f407xx_matlab.h']]], - ['gpio_5fospeedr_5fospeed13_5fmsk_788',['GPIO_OSPEEDR_OSPEED13_Msk',['../group___peripheral___registers___bits___definition.html#ga087816fdc310c1d74fa885b608c620c9',1,'stm32f407xx_matlab.h']]], - ['gpio_5fospeedr_5fospeed13_5fpos_789',['GPIO_OSPEEDR_OSPEED13_Pos',['../group___peripheral___registers___bits___definition.html#ga8362c7b2a216297bbf58ea02b3df434d',1,'stm32f407xx_matlab.h']]], - ['gpio_5fospeedr_5fospeed14_790',['GPIO_OSPEEDR_OSPEED14',['../group___peripheral___registers___bits___definition.html#gaa27efa359dedf4559a0cae3b4ccbb866',1,'stm32f407xx_matlab.h']]], - ['gpio_5fospeedr_5fospeed14_5f0_791',['GPIO_OSPEEDR_OSPEED14_0',['../group___peripheral___registers___bits___definition.html#gaf32f167e31bfe8d231d99369cad3a932',1,'stm32f407xx_matlab.h']]], - ['gpio_5fospeedr_5fospeed14_5f1_792',['GPIO_OSPEEDR_OSPEED14_1',['../group___peripheral___registers___bits___definition.html#ga2e7a469a29270897c6a7f44e94fca1f2',1,'stm32f407xx_matlab.h']]], - ['gpio_5fospeedr_5fospeed14_5fmsk_793',['GPIO_OSPEEDR_OSPEED14_Msk',['../group___peripheral___registers___bits___definition.html#ga8fb875fe73210c3a4e1c269e030a357b',1,'stm32f407xx_matlab.h']]], - ['gpio_5fospeedr_5fospeed14_5fpos_794',['GPIO_OSPEEDR_OSPEED14_Pos',['../group___peripheral___registers___bits___definition.html#ga542445998ee4d4e0a1ecc80f96415769',1,'stm32f407xx_matlab.h']]], - ['gpio_5fospeedr_5fospeed15_795',['GPIO_OSPEEDR_OSPEED15',['../group___peripheral___registers___bits___definition.html#ga62066038e31f29b2d96a9c9756b47007',1,'stm32f407xx_matlab.h']]], - ['gpio_5fospeedr_5fospeed15_5f0_796',['GPIO_OSPEEDR_OSPEED15_0',['../group___peripheral___registers___bits___definition.html#gaf4114c96c51d3cee45535ff5265b47b2',1,'stm32f407xx_matlab.h']]], - ['gpio_5fospeedr_5fospeed15_5f1_797',['GPIO_OSPEEDR_OSPEED15_1',['../group___peripheral___registers___bits___definition.html#ga01afd6d3720d359e6b8c76d03e6c5eb9',1,'stm32f407xx_matlab.h']]], - ['gpio_5fospeedr_5fospeed15_5fmsk_798',['GPIO_OSPEEDR_OSPEED15_Msk',['../group___peripheral___registers___bits___definition.html#ga45c126130830699c993c2d790c31f5e6',1,'stm32f407xx_matlab.h']]], - ['gpio_5fospeedr_5fospeed15_5fpos_799',['GPIO_OSPEEDR_OSPEED15_Pos',['../group___peripheral___registers___bits___definition.html#ga0e98a82b548dbb52cb0d16d6c9b68da9',1,'stm32f407xx_matlab.h']]], - ['gpio_5fospeedr_5fospeed1_5f0_800',['GPIO_OSPEEDR_OSPEED1_0',['../group___peripheral___registers___bits___definition.html#ga08097ab565c4771df00762e15e93642c',1,'stm32f407xx_matlab.h']]], - ['gpio_5fospeedr_5fospeed1_5f1_801',['GPIO_OSPEEDR_OSPEED1_1',['../group___peripheral___registers___bits___definition.html#ga0cb2eaafcac4ea42ea17c030512fd59d',1,'stm32f407xx_matlab.h']]], - ['gpio_5fospeedr_5fospeed1_5fmsk_802',['GPIO_OSPEEDR_OSPEED1_Msk',['../group___peripheral___registers___bits___definition.html#ga788188c5bf4669f2b316aa0c6b723e9e',1,'stm32f407xx_matlab.h']]], - ['gpio_5fospeedr_5fospeed1_5fpos_803',['GPIO_OSPEEDR_OSPEED1_Pos',['../group___peripheral___registers___bits___definition.html#ga8253e839d2f456baf264cc3639876b25',1,'stm32f407xx_matlab.h']]], - ['gpio_5fospeedr_5fospeed2_804',['GPIO_OSPEEDR_OSPEED2',['../group___peripheral___registers___bits___definition.html#ga00c3e1150ff05598e93fdee8dd68936e',1,'stm32f407xx_matlab.h']]], - ['gpio_5fospeedr_5fospeed2_5f0_805',['GPIO_OSPEEDR_OSPEED2_0',['../group___peripheral___registers___bits___definition.html#ga8e96818c186656af3af439dcfa16528b',1,'stm32f407xx_matlab.h']]], - ['gpio_5fospeedr_5fospeed2_5f1_806',['GPIO_OSPEEDR_OSPEED2_1',['../group___peripheral___registers___bits___definition.html#ga2548db9b2371c3502f92f75566344141',1,'stm32f407xx_matlab.h']]], - ['gpio_5fospeedr_5fospeed2_5fmsk_807',['GPIO_OSPEEDR_OSPEED2_Msk',['../group___peripheral___registers___bits___definition.html#ga5a287b69df598692ea5425ac903ee934',1,'stm32f407xx_matlab.h']]], - ['gpio_5fospeedr_5fospeed2_5fpos_808',['GPIO_OSPEEDR_OSPEED2_Pos',['../group___peripheral___registers___bits___definition.html#gafcc5a8e431eddf53ff110e3cabcf84a9',1,'stm32f407xx_matlab.h']]], - ['gpio_5fospeedr_5fospeed3_809',['GPIO_OSPEEDR_OSPEED3',['../group___peripheral___registers___bits___definition.html#ga70a77f985b46c258894f35dd089b0d20',1,'stm32f407xx_matlab.h']]], - ['gpio_5fospeedr_5fospeed3_5f0_810',['GPIO_OSPEEDR_OSPEED3_0',['../group___peripheral___registers___bits___definition.html#gaa2d54448afbd578a80e745bf88141f15',1,'stm32f407xx_matlab.h']]], - ['gpio_5fospeedr_5fospeed3_5f1_811',['GPIO_OSPEEDR_OSPEED3_1',['../group___peripheral___registers___bits___definition.html#gaa7445a434c85d73f0343f07e4b1abd2e',1,'stm32f407xx_matlab.h']]], - ['gpio_5fospeedr_5fospeed3_5fmsk_812',['GPIO_OSPEEDR_OSPEED3_Msk',['../group___peripheral___registers___bits___definition.html#ga1932d5de59094f3b77d1c38c3363e022',1,'stm32f407xx_matlab.h']]], - ['gpio_5fospeedr_5fospeed3_5fpos_813',['GPIO_OSPEEDR_OSPEED3_Pos',['../group___peripheral___registers___bits___definition.html#ga2b5205a128da01cee0bf8911e6deeba3',1,'stm32f407xx_matlab.h']]], - ['gpio_5fospeedr_5fospeed4_814',['GPIO_OSPEEDR_OSPEED4',['../group___peripheral___registers___bits___definition.html#ga44b7462b3a8eac83a6190a9d4ed94733',1,'stm32f407xx_matlab.h']]], - ['gpio_5fospeedr_5fospeed4_5f0_815',['GPIO_OSPEEDR_OSPEED4_0',['../group___peripheral___registers___bits___definition.html#ga7bc92d4bc48eb29f15eeda3b4f2b7729',1,'stm32f407xx_matlab.h']]], - ['gpio_5fospeedr_5fospeed4_5f1_816',['GPIO_OSPEEDR_OSPEED4_1',['../group___peripheral___registers___bits___definition.html#gaa1074b9afc9555d005eed1283990ee2e',1,'stm32f407xx_matlab.h']]], - ['gpio_5fospeedr_5fospeed4_5fmsk_817',['GPIO_OSPEEDR_OSPEED4_Msk',['../group___peripheral___registers___bits___definition.html#ga91182962d406df7459584b8cb9646e9e',1,'stm32f407xx_matlab.h']]], - ['gpio_5fospeedr_5fospeed4_5fpos_818',['GPIO_OSPEEDR_OSPEED4_Pos',['../group___peripheral___registers___bits___definition.html#ga8965c0a99fbe9052bf008a4da714b84b',1,'stm32f407xx_matlab.h']]], - ['gpio_5fospeedr_5fospeed5_819',['GPIO_OSPEEDR_OSPEED5',['../group___peripheral___registers___bits___definition.html#ga39a76e505a04bac8df5b801bc759d9cf',1,'stm32f407xx_matlab.h']]], - ['gpio_5fospeedr_5fospeed5_5f0_820',['GPIO_OSPEEDR_OSPEED5_0',['../group___peripheral___registers___bits___definition.html#ga51db6938ff53112b1546ea2955c6bec8',1,'stm32f407xx_matlab.h']]], - ['gpio_5fospeedr_5fospeed5_5f1_821',['GPIO_OSPEEDR_OSPEED5_1',['../group___peripheral___registers___bits___definition.html#ga33507bcb6d4a5f11748cd0f81483e900',1,'stm32f407xx_matlab.h']]], - ['gpio_5fospeedr_5fospeed5_5fmsk_822',['GPIO_OSPEEDR_OSPEED5_Msk',['../group___peripheral___registers___bits___definition.html#ga9fe5071dcf994ca5836756cd44c7df76',1,'stm32f407xx_matlab.h']]], - ['gpio_5fospeedr_5fospeed5_5fpos_823',['GPIO_OSPEEDR_OSPEED5_Pos',['../group___peripheral___registers___bits___definition.html#ga3dbca74e2ddaa85108e7326cd681c345',1,'stm32f407xx_matlab.h']]], - ['gpio_5fospeedr_5fospeed6_824',['GPIO_OSPEEDR_OSPEED6',['../group___peripheral___registers___bits___definition.html#ga220c76017b851a0861252cdc19e5ad8e',1,'stm32f407xx_matlab.h']]], - ['gpio_5fospeedr_5fospeed6_5f0_825',['GPIO_OSPEEDR_OSPEED6_0',['../group___peripheral___registers___bits___definition.html#gab28c483d24d4f8aefdf89578af2a66a5',1,'stm32f407xx_matlab.h']]], - ['gpio_5fospeedr_5fospeed6_5f1_826',['GPIO_OSPEEDR_OSPEED6_1',['../group___peripheral___registers___bits___definition.html#gaa2d7d80ccb16466efc06dc08334539fe',1,'stm32f407xx_matlab.h']]], - ['gpio_5fospeedr_5fospeed6_5fmsk_827',['GPIO_OSPEEDR_OSPEED6_Msk',['../group___peripheral___registers___bits___definition.html#ga1f07ebb84c0aa6967ca9057d75f3d5cc',1,'stm32f407xx_matlab.h']]], - ['gpio_5fospeedr_5fospeed6_5fpos_828',['GPIO_OSPEEDR_OSPEED6_Pos',['../group___peripheral___registers___bits___definition.html#gaa2559ea5b8212d7799d95c5a67593826',1,'stm32f407xx_matlab.h']]], - ['gpio_5fospeedr_5fospeed7_829',['GPIO_OSPEEDR_OSPEED7',['../group___peripheral___registers___bits___definition.html#gada868726c50880ee3f5e3cf35bf7be07',1,'stm32f407xx_matlab.h']]], - ['gpio_5fospeedr_5fospeed7_5f0_830',['GPIO_OSPEEDR_OSPEED7_0',['../group___peripheral___registers___bits___definition.html#ga241f032a5afcf9fbaf7a03ca6756dae3',1,'stm32f407xx_matlab.h']]], - ['gpio_5fospeedr_5fospeed7_5f1_831',['GPIO_OSPEEDR_OSPEED7_1',['../group___peripheral___registers___bits___definition.html#ga55510fcf6f51a1badbd0507b0174ca82',1,'stm32f407xx_matlab.h']]], - ['gpio_5fospeedr_5fospeed7_5fmsk_832',['GPIO_OSPEEDR_OSPEED7_Msk',['../group___peripheral___registers___bits___definition.html#gab238b715009a8081e4299a04464f8fba',1,'stm32f407xx_matlab.h']]], - ['gpio_5fospeedr_5fospeed7_5fpos_833',['GPIO_OSPEEDR_OSPEED7_Pos',['../group___peripheral___registers___bits___definition.html#ga0e1d68c48b823f2ddcbc19f9472b71e0',1,'stm32f407xx_matlab.h']]], - ['gpio_5fospeedr_5fospeed8_834',['GPIO_OSPEEDR_OSPEED8',['../group___peripheral___registers___bits___definition.html#ga48fc91b25c5e9b44cb2c5281e430b530',1,'stm32f407xx_matlab.h']]], - ['gpio_5fospeedr_5fospeed8_5f0_835',['GPIO_OSPEEDR_OSPEED8_0',['../group___peripheral___registers___bits___definition.html#gaf9cc347eada649f592544fe46a60d61f',1,'stm32f407xx_matlab.h']]], - ['gpio_5fospeedr_5fospeed8_5f1_836',['GPIO_OSPEEDR_OSPEED8_1',['../group___peripheral___registers___bits___definition.html#ga001e0393d3563dce9de7822581d99f74',1,'stm32f407xx_matlab.h']]], - ['gpio_5fospeedr_5fospeed8_5fmsk_837',['GPIO_OSPEEDR_OSPEED8_Msk',['../group___peripheral___registers___bits___definition.html#ga1b220cadf1c6f35a7a5ee9141b353361',1,'stm32f407xx_matlab.h']]], - ['gpio_5fospeedr_5fospeed8_5fpos_838',['GPIO_OSPEEDR_OSPEED8_Pos',['../group___peripheral___registers___bits___definition.html#ga752447edb6283f5ab3639ea160311702',1,'stm32f407xx_matlab.h']]], - ['gpio_5fospeedr_5fospeed9_839',['GPIO_OSPEEDR_OSPEED9',['../group___peripheral___registers___bits___definition.html#gaa18d29dd7797e82889241af2394d9bac',1,'stm32f407xx_matlab.h']]], - ['gpio_5fospeedr_5fospeed9_5f0_840',['GPIO_OSPEEDR_OSPEED9_0',['../group___peripheral___registers___bits___definition.html#ga79c3d503027ce61ba59f5362579c8c75',1,'stm32f407xx_matlab.h']]], - ['gpio_5fospeedr_5fospeed9_5f1_841',['GPIO_OSPEEDR_OSPEED9_1',['../group___peripheral___registers___bits___definition.html#ga8cf1f4b8620e0003ea2ee281c4d1a86e',1,'stm32f407xx_matlab.h']]], - ['gpio_5fospeedr_5fospeed9_5fmsk_842',['GPIO_OSPEEDR_OSPEED9_Msk',['../group___peripheral___registers___bits___definition.html#gaaaf713561b3fe73574b8566e54dbb7da',1,'stm32f407xx_matlab.h']]], - ['gpio_5fospeedr_5fospeed9_5fpos_843',['GPIO_OSPEEDR_OSPEED9_Pos',['../group___peripheral___registers___bits___definition.html#ga05c5c757f8ec338edbbf08bf5d8d68c5',1,'stm32f407xx_matlab.h']]], - ['gpio_5fotyper_5fot0_844',['GPIO_OTYPER_OT0',['../group___peripheral___registers___bits___definition.html#ga2aebd85688999595239036bd63eac4a3',1,'stm32f407xx_matlab.h']]], - ['gpio_5fotyper_5fot0_5fmsk_845',['GPIO_OTYPER_OT0_Msk',['../group___peripheral___registers___bits___definition.html#ga1dbf22f662367e7f4033c6ef85f69162',1,'stm32f407xx_matlab.h']]], - ['gpio_5fotyper_5fot0_5fpos_846',['GPIO_OTYPER_OT0_Pos',['../group___peripheral___registers___bits___definition.html#ga1d59a7c3218b146d61516cabb81588d1',1,'stm32f407xx_matlab.h']]], - ['gpio_5fotyper_5fot1_847',['GPIO_OTYPER_OT1',['../group___peripheral___registers___bits___definition.html#ga3c2e6db60417e319c9a8de701ab4d93d',1,'stm32f407xx_matlab.h']]], - ['gpio_5fotyper_5fot10_848',['GPIO_OTYPER_OT10',['../group___peripheral___registers___bits___definition.html#ga6bc9516ce236e7d3429066b16a7dfa9a',1,'stm32f407xx_matlab.h']]], - ['gpio_5fotyper_5fot10_5fmsk_849',['GPIO_OTYPER_OT10_Msk',['../group___peripheral___registers___bits___definition.html#ga108993b457894e46ee48421cf847d6b6',1,'stm32f407xx_matlab.h']]], - ['gpio_5fotyper_5fot10_5fpos_850',['GPIO_OTYPER_OT10_Pos',['../group___peripheral___registers___bits___definition.html#ga8ae2d866e0737d3b40919d877a321dbe',1,'stm32f407xx_matlab.h']]], - ['gpio_5fotyper_5fot11_851',['GPIO_OTYPER_OT11',['../group___peripheral___registers___bits___definition.html#ga9d842d0b79b54cd990a819197a0ecc6f',1,'stm32f407xx_matlab.h']]], - ['gpio_5fotyper_5fot11_5fmsk_852',['GPIO_OTYPER_OT11_Msk',['../group___peripheral___registers___bits___definition.html#ga0f833cf9e36cd48b282a838ee5d4d269',1,'stm32f407xx_matlab.h']]], - ['gpio_5fotyper_5fot11_5fpos_853',['GPIO_OTYPER_OT11_Pos',['../group___peripheral___registers___bits___definition.html#ga72764b8f1eaca4407ddce7f3313d045d',1,'stm32f407xx_matlab.h']]], - ['gpio_5fotyper_5fot12_854',['GPIO_OTYPER_OT12',['../group___peripheral___registers___bits___definition.html#ga6ab821f1edc7c879a34e51d85be89927',1,'stm32f407xx_matlab.h']]], - ['gpio_5fotyper_5fot12_5fmsk_855',['GPIO_OTYPER_OT12_Msk',['../group___peripheral___registers___bits___definition.html#gac138e0a10703e6da87ff724a9e8314e6',1,'stm32f407xx_matlab.h']]], - ['gpio_5fotyper_5fot12_5fpos_856',['GPIO_OTYPER_OT12_Pos',['../group___peripheral___registers___bits___definition.html#ga9cbdcf0cf8146de12cb5ff36c6cbdc35',1,'stm32f407xx_matlab.h']]], - ['gpio_5fotyper_5fot13_857',['GPIO_OTYPER_OT13',['../group___peripheral___registers___bits___definition.html#ga84f78f6726211e6183ec7fcd3a40d2a8',1,'stm32f407xx_matlab.h']]], - ['gpio_5fotyper_5fot13_5fmsk_858',['GPIO_OTYPER_OT13_Msk',['../group___peripheral___registers___bits___definition.html#gacc65a535136ed14fbaba9d5557d766a9',1,'stm32f407xx_matlab.h']]], - ['gpio_5fotyper_5fot13_5fpos_859',['GPIO_OTYPER_OT13_Pos',['../group___peripheral___registers___bits___definition.html#ga25fc93b49714517d14b95c51496f4dde',1,'stm32f407xx_matlab.h']]], - ['gpio_5fotyper_5fot14_860',['GPIO_OTYPER_OT14',['../group___peripheral___registers___bits___definition.html#ga1323319e1db0678046b6f77c45bfee8b',1,'stm32f407xx_matlab.h']]], - ['gpio_5fotyper_5fot14_5fmsk_861',['GPIO_OTYPER_OT14_Msk',['../group___peripheral___registers___bits___definition.html#gaf7a50883c2c1f5f71ffed16b182b4690',1,'stm32f407xx_matlab.h']]], - ['gpio_5fotyper_5fot14_5fpos_862',['GPIO_OTYPER_OT14_Pos',['../group___peripheral___registers___bits___definition.html#gaed656d73e74d6e4dc451d61cdd4529f9',1,'stm32f407xx_matlab.h']]], - ['gpio_5fotyper_5fot15_863',['GPIO_OTYPER_OT15',['../group___peripheral___registers___bits___definition.html#ga2c309a7ab680e01fcb7d001ea0a98c70',1,'stm32f407xx_matlab.h']]], - ['gpio_5fotyper_5fot15_5fmsk_864',['GPIO_OTYPER_OT15_Msk',['../group___peripheral___registers___bits___definition.html#gafe5d4eaffe4617f72cc460127fc20cf5',1,'stm32f407xx_matlab.h']]], - ['gpio_5fotyper_5fot15_5fpos_865',['GPIO_OTYPER_OT15_Pos',['../group___peripheral___registers___bits___definition.html#ga5efa1dc79a92b77579d2fd7fe2612c1b',1,'stm32f407xx_matlab.h']]], - ['gpio_5fotyper_5fot1_5fmsk_866',['GPIO_OTYPER_OT1_Msk',['../group___peripheral___registers___bits___definition.html#ga2d6d2752a99a69a1ed6fde751477f65e',1,'stm32f407xx_matlab.h']]], - ['gpio_5fotyper_5fot1_5fpos_867',['GPIO_OTYPER_OT1_Pos',['../group___peripheral___registers___bits___definition.html#ga592defc7541ea5c2463d0a5c9566a337',1,'stm32f407xx_matlab.h']]], - ['gpio_5fotyper_5fot2_868',['GPIO_OTYPER_OT2',['../group___peripheral___registers___bits___definition.html#ga5478c1782217eec4b8d09fcc930a55c1',1,'stm32f407xx_matlab.h']]], - ['gpio_5fotyper_5fot2_5fmsk_869',['GPIO_OTYPER_OT2_Msk',['../group___peripheral___registers___bits___definition.html#ga90c1021a385b3e3ad84b5c3f55dcd2bd',1,'stm32f407xx_matlab.h']]], - ['gpio_5fotyper_5fot2_5fpos_870',['GPIO_OTYPER_OT2_Pos',['../group___peripheral___registers___bits___definition.html#gac3a3f4f3a5a9a13e74861ada55fe8373',1,'stm32f407xx_matlab.h']]], - ['gpio_5fotyper_5fot3_871',['GPIO_OTYPER_OT3',['../group___peripheral___registers___bits___definition.html#ga52cbd557435c2173e390b534cc6a893b',1,'stm32f407xx_matlab.h']]], - ['gpio_5fotyper_5fot3_5fmsk_872',['GPIO_OTYPER_OT3_Msk',['../group___peripheral___registers___bits___definition.html#gac467eaf271fc0abc674a0f1657b754b9',1,'stm32f407xx_matlab.h']]], - ['gpio_5fotyper_5fot3_5fpos_873',['GPIO_OTYPER_OT3_Pos',['../group___peripheral___registers___bits___definition.html#gad678ac2b9b55a718f1e81237ee4a5b30',1,'stm32f407xx_matlab.h']]], - ['gpio_5fotyper_5fot4_874',['GPIO_OTYPER_OT4',['../group___peripheral___registers___bits___definition.html#gaedd72ae7a6ef61cb01d7b31e7ac3f02f',1,'stm32f407xx_matlab.h']]], - ['gpio_5fotyper_5fot4_5fmsk_875',['GPIO_OTYPER_OT4_Msk',['../group___peripheral___registers___bits___definition.html#gab826bfea8ea3e5500900e31d24603a3f',1,'stm32f407xx_matlab.h']]], - ['gpio_5fotyper_5fot4_5fpos_876',['GPIO_OTYPER_OT4_Pos',['../group___peripheral___registers___bits___definition.html#gaa9104ccbb9f57282217df7a4af2fa149',1,'stm32f407xx_matlab.h']]], - ['gpio_5fotyper_5fot5_877',['GPIO_OTYPER_OT5',['../group___peripheral___registers___bits___definition.html#gabfa602db904a1c4ac0bfe2f57e044f03',1,'stm32f407xx_matlab.h']]], - ['gpio_5fotyper_5fot5_5fmsk_878',['GPIO_OTYPER_OT5_Msk',['../group___peripheral___registers___bits___definition.html#gaa41f6d81f21b5d4c984d318c3d5ea5fc',1,'stm32f407xx_matlab.h']]], - ['gpio_5fotyper_5fot5_5fpos_879',['GPIO_OTYPER_OT5_Pos',['../group___peripheral___registers___bits___definition.html#gaffcd8be7000a751ac97b432e6f8febcd',1,'stm32f407xx_matlab.h']]], - ['gpio_5fotyper_5fot6_880',['GPIO_OTYPER_OT6',['../group___peripheral___registers___bits___definition.html#ga872f2008be45e90a2663c31f5e3858ee',1,'stm32f407xx_matlab.h']]], - ['gpio_5fotyper_5fot6_5fmsk_881',['GPIO_OTYPER_OT6_Msk',['../group___peripheral___registers___bits___definition.html#gaf04845f8e00f58279129c9d7cbc40340',1,'stm32f407xx_matlab.h']]], - ['gpio_5fotyper_5fot6_5fpos_882',['GPIO_OTYPER_OT6_Pos',['../group___peripheral___registers___bits___definition.html#ga5673f4acd1ca97723538455ce2ad8fa5',1,'stm32f407xx_matlab.h']]], - ['gpio_5fotyper_5fot7_883',['GPIO_OTYPER_OT7',['../group___peripheral___registers___bits___definition.html#gaac22a8999bf349459af4bd58fe319d03',1,'stm32f407xx_matlab.h']]], - ['gpio_5fotyper_5fot7_5fmsk_884',['GPIO_OTYPER_OT7_Msk',['../group___peripheral___registers___bits___definition.html#ga1c4371991d169bbce9043ef03eebc3e7',1,'stm32f407xx_matlab.h']]], - ['gpio_5fotyper_5fot7_5fpos_885',['GPIO_OTYPER_OT7_Pos',['../group___peripheral___registers___bits___definition.html#ga5567f31bc7165b0a55e42a392306faf5',1,'stm32f407xx_matlab.h']]], - ['gpio_5fotyper_5fot8_886',['GPIO_OTYPER_OT8',['../group___peripheral___registers___bits___definition.html#ga1b89d7c4cc8986895b4e4cbc8455f912',1,'stm32f407xx_matlab.h']]], - ['gpio_5fotyper_5fot8_5fmsk_887',['GPIO_OTYPER_OT8_Msk',['../group___peripheral___registers___bits___definition.html#ga88986ea0ef6829d98ea063355ed574bd',1,'stm32f407xx_matlab.h']]], - ['gpio_5fotyper_5fot8_5fpos_888',['GPIO_OTYPER_OT8_Pos',['../group___peripheral___registers___bits___definition.html#ga2df4811f95aae5d25c63d1e6645914e4',1,'stm32f407xx_matlab.h']]], - ['gpio_5fotyper_5fot9_889',['GPIO_OTYPER_OT9',['../group___peripheral___registers___bits___definition.html#gae53d4f666ee3410123ab941ee29fc886',1,'stm32f407xx_matlab.h']]], - ['gpio_5fotyper_5fot9_5fmsk_890',['GPIO_OTYPER_OT9_Msk',['../group___peripheral___registers___bits___definition.html#ga23374263ed146dfa55de5e09a9984520',1,'stm32f407xx_matlab.h']]], - ['gpio_5fotyper_5fot9_5fpos_891',['GPIO_OTYPER_OT9_Pos',['../group___peripheral___registers___bits___definition.html#ga9a517c02253d8081d006ba12b939ddb7',1,'stm32f407xx_matlab.h']]], - ['gpio_5fotyper_5fot_5f0_892',['GPIO_OTYPER_OT_0',['../group___peripheral___registers___bits___definition.html#gaf2f02eab04f88423789f532370680305',1,'stm32f407xx_matlab.h']]], - ['gpio_5fotyper_5fot_5f1_893',['GPIO_OTYPER_OT_1',['../group___peripheral___registers___bits___definition.html#ga8a842ad8f83c21f019f2e1e08f104a7f',1,'stm32f407xx_matlab.h']]], - ['gpio_5fotyper_5fot_5f10_894',['GPIO_OTYPER_OT_10',['../group___peripheral___registers___bits___definition.html#gadc1ef9cbe4226f9616c64bb641b44b3b',1,'stm32f407xx_matlab.h']]], - ['gpio_5fotyper_5fot_5f11_895',['GPIO_OTYPER_OT_11',['../group___peripheral___registers___bits___definition.html#gafd4fc33a12439fdf4ada19c04227dea7',1,'stm32f407xx_matlab.h']]], - ['gpio_5fotyper_5fot_5f12_896',['GPIO_OTYPER_OT_12',['../group___peripheral___registers___bits___definition.html#ga24e978fcc3d4e87bed919511e1226f0c',1,'stm32f407xx_matlab.h']]], - ['gpio_5fotyper_5fot_5f13_897',['GPIO_OTYPER_OT_13',['../group___peripheral___registers___bits___definition.html#ga7c5d7751cfdfaf58782f01692d8c88e8',1,'stm32f407xx_matlab.h']]], - ['gpio_5fotyper_5fot_5f14_898',['GPIO_OTYPER_OT_14',['../group___peripheral___registers___bits___definition.html#ga6c26938a0e8c03d90a966fc33f186e50',1,'stm32f407xx_matlab.h']]], - ['gpio_5fotyper_5fot_5f15_899',['GPIO_OTYPER_OT_15',['../group___peripheral___registers___bits___definition.html#ga51f153263d58a45fc2ef0734fc3f73eb',1,'stm32f407xx_matlab.h']]], - ['gpio_5fotyper_5fot_5f2_900',['GPIO_OTYPER_OT_2',['../group___peripheral___registers___bits___definition.html#ga3d3a246b6320fc51b39123249e1e6817',1,'stm32f407xx_matlab.h']]], - ['gpio_5fotyper_5fot_5f3_901',['GPIO_OTYPER_OT_3',['../group___peripheral___registers___bits___definition.html#gaef881bb4fa6b2dd9cecd4ee1385b6361',1,'stm32f407xx_matlab.h']]], - ['gpio_5fotyper_5fot_5f4_902',['GPIO_OTYPER_OT_4',['../group___peripheral___registers___bits___definition.html#ga8c3cc7a0b2c9b99212879cc8d7455258',1,'stm32f407xx_matlab.h']]], - ['gpio_5fotyper_5fot_5f5_903',['GPIO_OTYPER_OT_5',['../group___peripheral___registers___bits___definition.html#gaaa0dd76857b25ae35a785cee97c8403d',1,'stm32f407xx_matlab.h']]], - ['gpio_5fotyper_5fot_5f6_904',['GPIO_OTYPER_OT_6',['../group___peripheral___registers___bits___definition.html#ga1dbea639fd4ffe59a706a11fb1ee104b',1,'stm32f407xx_matlab.h']]], - ['gpio_5fotyper_5fot_5f7_905',['GPIO_OTYPER_OT_7',['../group___peripheral___registers___bits___definition.html#gaaacead96dc3377342af4aa18adf6453e',1,'stm32f407xx_matlab.h']]], - ['gpio_5fotyper_5fot_5f8_906',['GPIO_OTYPER_OT_8',['../group___peripheral___registers___bits___definition.html#ga5a1f64fdf2ab84c634c0fa8cb060a65f',1,'stm32f407xx_matlab.h']]], - ['gpio_5fotyper_5fot_5f9_907',['GPIO_OTYPER_OT_9',['../group___peripheral___registers___bits___definition.html#gaa5c7deea3d764bb3999578030e3158aa',1,'stm32f407xx_matlab.h']]], - ['gpio_5fpupdr_5fpupd0_908',['GPIO_PUPDR_PUPD0',['../group___peripheral___registers___bits___definition.html#ga757af1d9f0ba5f4ed76320b6932e3741',1,'stm32f407xx_matlab.h']]], - ['gpio_5fpupdr_5fpupd0_5f0_909',['GPIO_PUPDR_PUPD0_0',['../group___peripheral___registers___bits___definition.html#ga7ecb6eae6b933d78446834bf320cc235',1,'stm32f407xx_matlab.h']]], - ['gpio_5fpupdr_5fpupd0_5f1_910',['GPIO_PUPDR_PUPD0_1',['../group___peripheral___registers___bits___definition.html#ga9d8177954b7806374d1cbba3bbbfe034',1,'stm32f407xx_matlab.h']]], - ['gpio_5fpupdr_5fpupd0_5fmsk_911',['GPIO_PUPDR_PUPD0_Msk',['../group___peripheral___registers___bits___definition.html#gaa0be0e927e30b38360486e4d57854c20',1,'stm32f407xx_matlab.h']]], - ['gpio_5fpupdr_5fpupd0_5fpos_912',['GPIO_PUPDR_PUPD0_Pos',['../group___peripheral___registers___bits___definition.html#gada27513a02562dc3e44c361eb96d8d60',1,'stm32f407xx_matlab.h']]], - ['gpio_5fpupdr_5fpupd1_913',['GPIO_PUPDR_PUPD1',['../group___peripheral___registers___bits___definition.html#ga8da0bf95f1973c18a4a4b7c0aa3d1404',1,'stm32f407xx_matlab.h']]], - ['gpio_5fpupdr_5fpupd10_914',['GPIO_PUPDR_PUPD10',['../group___peripheral___registers___bits___definition.html#ga53f1c72b27ac3f18d6e8c7b366416ba6',1,'stm32f407xx_matlab.h']]], - ['gpio_5fpupdr_5fpupd10_5f0_915',['GPIO_PUPDR_PUPD10_0',['../group___peripheral___registers___bits___definition.html#ga71dc18b0db03b06216a30e15bb08c81f',1,'stm32f407xx_matlab.h']]], - ['gpio_5fpupdr_5fpupd10_5f1_916',['GPIO_PUPDR_PUPD10_1',['../group___peripheral___registers___bits___definition.html#ga955fdb4da04d3702e3566d5068d9fd0a',1,'stm32f407xx_matlab.h']]], - ['gpio_5fpupdr_5fpupd10_5fmsk_917',['GPIO_PUPDR_PUPD10_Msk',['../group___peripheral___registers___bits___definition.html#ga94f8b1bfa375b95aa586d4e657d810c1',1,'stm32f407xx_matlab.h']]], - ['gpio_5fpupdr_5fpupd10_5fpos_918',['GPIO_PUPDR_PUPD10_Pos',['../group___peripheral___registers___bits___definition.html#ga19ff590a0540fab5751f0f0b36ea3ac8',1,'stm32f407xx_matlab.h']]], - ['gpio_5fpupdr_5fpupd11_919',['GPIO_PUPDR_PUPD11',['../group___peripheral___registers___bits___definition.html#ga85596aa60b034d0de6ecb98f94a8d036',1,'stm32f407xx_matlab.h']]], - ['gpio_5fpupdr_5fpupd11_5f0_920',['GPIO_PUPDR_PUPD11_0',['../group___peripheral___registers___bits___definition.html#ga5acc6eda43958a03426815a0db4a494b',1,'stm32f407xx_matlab.h']]], - ['gpio_5fpupdr_5fpupd11_5f1_921',['GPIO_PUPDR_PUPD11_1',['../group___peripheral___registers___bits___definition.html#ga2666e7ba5f50abf8502ba8e0f0f57430',1,'stm32f407xx_matlab.h']]], - ['gpio_5fpupdr_5fpupd11_5fmsk_922',['GPIO_PUPDR_PUPD11_Msk',['../group___peripheral___registers___bits___definition.html#gabd0f388b7d8039e4b3d8dd573bc8f429',1,'stm32f407xx_matlab.h']]], - ['gpio_5fpupdr_5fpupd11_5fpos_923',['GPIO_PUPDR_PUPD11_Pos',['../group___peripheral___registers___bits___definition.html#gab55094695264b5c3342f623dec206815',1,'stm32f407xx_matlab.h']]], - ['gpio_5fpupdr_5fpupd12_924',['GPIO_PUPDR_PUPD12',['../group___peripheral___registers___bits___definition.html#ga834911368392a16ff6b7e051a7e7ae9c',1,'stm32f407xx_matlab.h']]], - ['gpio_5fpupdr_5fpupd12_5f0_925',['GPIO_PUPDR_PUPD12_0',['../group___peripheral___registers___bits___definition.html#gabac3dea5943de3917f93772936539e74',1,'stm32f407xx_matlab.h']]], - ['gpio_5fpupdr_5fpupd12_5f1_926',['GPIO_PUPDR_PUPD12_1',['../group___peripheral___registers___bits___definition.html#ga90f8b6c555a779ed1bef06e7ab1a0600',1,'stm32f407xx_matlab.h']]], - ['gpio_5fpupdr_5fpupd12_5fmsk_927',['GPIO_PUPDR_PUPD12_Msk',['../group___peripheral___registers___bits___definition.html#ga30a14d0a21b413ff9c5ff1efdec903bc',1,'stm32f407xx_matlab.h']]], - ['gpio_5fpupdr_5fpupd12_5fpos_928',['GPIO_PUPDR_PUPD12_Pos',['../group___peripheral___registers___bits___definition.html#gaa2f7ab8ad7a8ac91e877e24f8119a783',1,'stm32f407xx_matlab.h']]], - ['gpio_5fpupdr_5fpupd13_929',['GPIO_PUPDR_PUPD13',['../group___peripheral___registers___bits___definition.html#ga746478979825dcad6323b002906581b9',1,'stm32f407xx_matlab.h']]], - ['gpio_5fpupdr_5fpupd13_5f0_930',['GPIO_PUPDR_PUPD13_0',['../group___peripheral___registers___bits___definition.html#gab4f37903148418084e6059041ac2d3c8',1,'stm32f407xx_matlab.h']]], - ['gpio_5fpupdr_5fpupd13_5f1_931',['GPIO_PUPDR_PUPD13_1',['../group___peripheral___registers___bits___definition.html#gaf4dd950825a4c5bb9e89e44f4398f050',1,'stm32f407xx_matlab.h']]], - ['gpio_5fpupdr_5fpupd13_5fmsk_932',['GPIO_PUPDR_PUPD13_Msk',['../group___peripheral___registers___bits___definition.html#gadebe9101a2f2de81d563e9e982c186cd',1,'stm32f407xx_matlab.h']]], - ['gpio_5fpupdr_5fpupd13_5fpos_933',['GPIO_PUPDR_PUPD13_Pos',['../group___peripheral___registers___bits___definition.html#gadb87a27f5193bc33e7b553faa006086b',1,'stm32f407xx_matlab.h']]], - ['gpio_5fpupdr_5fpupd14_934',['GPIO_PUPDR_PUPD14',['../group___peripheral___registers___bits___definition.html#ga398c010d45105e8e37b1995430a52a94',1,'stm32f407xx_matlab.h']]], - ['gpio_5fpupdr_5fpupd14_5f0_935',['GPIO_PUPDR_PUPD14_0',['../group___peripheral___registers___bits___definition.html#ga2312d606bfcd3b62e9885d7d7b316b39',1,'stm32f407xx_matlab.h']]], - ['gpio_5fpupdr_5fpupd14_5f1_936',['GPIO_PUPDR_PUPD14_1',['../group___peripheral___registers___bits___definition.html#ga88f904affe99bf7a5045c1c3704d1146',1,'stm32f407xx_matlab.h']]], - ['gpio_5fpupdr_5fpupd14_5fmsk_937',['GPIO_PUPDR_PUPD14_Msk',['../group___peripheral___registers___bits___definition.html#gaf7e0dc8ebc4e7c81e65265cae3b23aa4',1,'stm32f407xx_matlab.h']]], - ['gpio_5fpupdr_5fpupd14_5fpos_938',['GPIO_PUPDR_PUPD14_Pos',['../group___peripheral___registers___bits___definition.html#ga4405ac26d78b02793fc695d410bd7b88',1,'stm32f407xx_matlab.h']]], - ['gpio_5fpupdr_5fpupd15_939',['GPIO_PUPDR_PUPD15',['../group___peripheral___registers___bits___definition.html#gacd5cdc50a6f6ee671aa1ac39c9048241',1,'stm32f407xx_matlab.h']]], - ['gpio_5fpupdr_5fpupd15_5f0_940',['GPIO_PUPDR_PUPD15_0',['../group___peripheral___registers___bits___definition.html#ga39538a30aef08d4bbf9ce88ee22d1b46',1,'stm32f407xx_matlab.h']]], - ['gpio_5fpupdr_5fpupd15_5f1_941',['GPIO_PUPDR_PUPD15_1',['../group___peripheral___registers___bits___definition.html#ga24352127803f5fbe718ff22e7a1062b4',1,'stm32f407xx_matlab.h']]], - ['gpio_5fpupdr_5fpupd15_5fmsk_942',['GPIO_PUPDR_PUPD15_Msk',['../group___peripheral___registers___bits___definition.html#gae63e9b1d8c9e5f92cbb3f8ad67304f67',1,'stm32f407xx_matlab.h']]], - ['gpio_5fpupdr_5fpupd15_5fpos_943',['GPIO_PUPDR_PUPD15_Pos',['../group___peripheral___registers___bits___definition.html#ga9596e5ba318ea6eb9d0de839e5125f7e',1,'stm32f407xx_matlab.h']]], - ['gpio_5fpupdr_5fpupd1_5f0_944',['GPIO_PUPDR_PUPD1_0',['../group___peripheral___registers___bits___definition.html#gaf6512d7fee2b400279ebd0843a5e481c',1,'stm32f407xx_matlab.h']]], - ['gpio_5fpupdr_5fpupd1_5f1_945',['GPIO_PUPDR_PUPD1_1',['../group___peripheral___registers___bits___definition.html#gadb010cc75a60effd883969c35611f5c8',1,'stm32f407xx_matlab.h']]], - ['gpio_5fpupdr_5fpupd1_5fmsk_946',['GPIO_PUPDR_PUPD1_Msk',['../group___peripheral___registers___bits___definition.html#gac529eb9b34ed26a9fb436c230cbad882',1,'stm32f407xx_matlab.h']]], - ['gpio_5fpupdr_5fpupd1_5fpos_947',['GPIO_PUPDR_PUPD1_Pos',['../group___peripheral___registers___bits___definition.html#ga2dc73dd62120c9617e25ccbf4b038991',1,'stm32f407xx_matlab.h']]], - ['gpio_5fpupdr_5fpupd2_948',['GPIO_PUPDR_PUPD2',['../group___peripheral___registers___bits___definition.html#ga0e8cc32256e605234ec8bfba9ebbe2d2',1,'stm32f407xx_matlab.h']]], - ['gpio_5fpupdr_5fpupd2_5f0_949',['GPIO_PUPDR_PUPD2_0',['../group___peripheral___registers___bits___definition.html#ga044bf572e114a7746127135a3f38caef',1,'stm32f407xx_matlab.h']]], - ['gpio_5fpupdr_5fpupd2_5f1_950',['GPIO_PUPDR_PUPD2_1',['../group___peripheral___registers___bits___definition.html#ga06efd822240e0026cb83e661b88a9e3c',1,'stm32f407xx_matlab.h']]], - ['gpio_5fpupdr_5fpupd2_5fmsk_951',['GPIO_PUPDR_PUPD2_Msk',['../group___peripheral___registers___bits___definition.html#gaa71a5ea0b0b124a1af187ef2160b412a',1,'stm32f407xx_matlab.h']]], - ['gpio_5fpupdr_5fpupd2_5fpos_952',['GPIO_PUPDR_PUPD2_Pos',['../group___peripheral___registers___bits___definition.html#ga586d58e70155a838a7607fa1d209e367',1,'stm32f407xx_matlab.h']]], - ['gpio_5fpupdr_5fpupd3_953',['GPIO_PUPDR_PUPD3',['../group___peripheral___registers___bits___definition.html#ga0c6217b6d33bf54771323d7f55e6fa9c',1,'stm32f407xx_matlab.h']]], - ['gpio_5fpupdr_5fpupd3_5f0_954',['GPIO_PUPDR_PUPD3_0',['../group___peripheral___registers___bits___definition.html#ga1f885f83700f6710d75e8a23135e4449',1,'stm32f407xx_matlab.h']]], - ['gpio_5fpupdr_5fpupd3_5f1_955',['GPIO_PUPDR_PUPD3_1',['../group___peripheral___registers___bits___definition.html#ga713dc2ffd7e76239f05399299043538a',1,'stm32f407xx_matlab.h']]], - ['gpio_5fpupdr_5fpupd3_5fmsk_956',['GPIO_PUPDR_PUPD3_Msk',['../group___peripheral___registers___bits___definition.html#ga4fbaf3b066dac1e0986a5b68ce30b0d3',1,'stm32f407xx_matlab.h']]], - ['gpio_5fpupdr_5fpupd3_5fpos_957',['GPIO_PUPDR_PUPD3_Pos',['../group___peripheral___registers___bits___definition.html#ga16874909048265725250c4d8b3d1fe16',1,'stm32f407xx_matlab.h']]], - ['gpio_5fpupdr_5fpupd4_958',['GPIO_PUPDR_PUPD4',['../group___peripheral___registers___bits___definition.html#gaf02aa5885737e111d98770d67b858d8e',1,'stm32f407xx_matlab.h']]], - ['gpio_5fpupdr_5fpupd4_5f0_959',['GPIO_PUPDR_PUPD4_0',['../group___peripheral___registers___bits___definition.html#gaa25af0133be08cc46bd64d19913f090c',1,'stm32f407xx_matlab.h']]], - ['gpio_5fpupdr_5fpupd4_5f1_960',['GPIO_PUPDR_PUPD4_1',['../group___peripheral___registers___bits___definition.html#gac699c89b1b15ad635a1a1109cbe2963e',1,'stm32f407xx_matlab.h']]], - ['gpio_5fpupdr_5fpupd4_5fmsk_961',['GPIO_PUPDR_PUPD4_Msk',['../group___peripheral___registers___bits___definition.html#ga1f0de7c586465d6dfb0e50d1194271cf',1,'stm32f407xx_matlab.h']]], - ['gpio_5fpupdr_5fpupd4_5fpos_962',['GPIO_PUPDR_PUPD4_Pos',['../group___peripheral___registers___bits___definition.html#gaffa6624f76681ba96183f8ea998da581',1,'stm32f407xx_matlab.h']]], - ['gpio_5fpupdr_5fpupd5_963',['GPIO_PUPDR_PUPD5',['../group___peripheral___registers___bits___definition.html#gabe54b8696e32251e874a821819d7c94d',1,'stm32f407xx_matlab.h']]], - ['gpio_5fpupdr_5fpupd5_5f0_964',['GPIO_PUPDR_PUPD5_0',['../group___peripheral___registers___bits___definition.html#ga31e7a8da20fb184d4bca472726c98058',1,'stm32f407xx_matlab.h']]], - ['gpio_5fpupdr_5fpupd5_5f1_965',['GPIO_PUPDR_PUPD5_1',['../group___peripheral___registers___bits___definition.html#ga0c3f4ba96ad50d3d5230fa8fb89f637d',1,'stm32f407xx_matlab.h']]], - ['gpio_5fpupdr_5fpupd5_5fmsk_966',['GPIO_PUPDR_PUPD5_Msk',['../group___peripheral___registers___bits___definition.html#ga2dca8d52990a63a4185d8185d3100222',1,'stm32f407xx_matlab.h']]], - ['gpio_5fpupdr_5fpupd5_5fpos_967',['GPIO_PUPDR_PUPD5_Pos',['../group___peripheral___registers___bits___definition.html#ga17c1aea5321b3308171bc9b813fccf02',1,'stm32f407xx_matlab.h']]], - ['gpio_5fpupdr_5fpupd6_968',['GPIO_PUPDR_PUPD6',['../group___peripheral___registers___bits___definition.html#gaa52d8b944af9bb59f52c2fd46559abdb',1,'stm32f407xx_matlab.h']]], - ['gpio_5fpupdr_5fpupd6_5f0_969',['GPIO_PUPDR_PUPD6_0',['../group___peripheral___registers___bits___definition.html#ga6aa2ea03e1632d3dfe812911bfd97f0b',1,'stm32f407xx_matlab.h']]], - ['gpio_5fpupdr_5fpupd6_5f1_970',['GPIO_PUPDR_PUPD6_1',['../group___peripheral___registers___bits___definition.html#ga3b5d490177e16ae30cd5264012feaa87',1,'stm32f407xx_matlab.h']]], - ['gpio_5fpupdr_5fpupd6_5fmsk_971',['GPIO_PUPDR_PUPD6_Msk',['../group___peripheral___registers___bits___definition.html#ga841c8e128f84ac7451f431d24a222072',1,'stm32f407xx_matlab.h']]], - ['gpio_5fpupdr_5fpupd6_5fpos_972',['GPIO_PUPDR_PUPD6_Pos',['../group___peripheral___registers___bits___definition.html#gac5cfdcc6b1779a517c19516429c6666b',1,'stm32f407xx_matlab.h']]], - ['gpio_5fpupdr_5fpupd7_973',['GPIO_PUPDR_PUPD7',['../group___peripheral___registers___bits___definition.html#ga18557333a95ca1a26bcd1d7f9fe207be',1,'stm32f407xx_matlab.h']]], - ['gpio_5fpupdr_5fpupd7_5f0_974',['GPIO_PUPDR_PUPD7_0',['../group___peripheral___registers___bits___definition.html#gae2954be6ab54a7d922b2d0f9e5d173f4',1,'stm32f407xx_matlab.h']]], - ['gpio_5fpupdr_5fpupd7_5f1_975',['GPIO_PUPDR_PUPD7_1',['../group___peripheral___registers___bits___definition.html#gabb959dd401c4890303c5c7fd962bcc08',1,'stm32f407xx_matlab.h']]], - ['gpio_5fpupdr_5fpupd7_5fmsk_976',['GPIO_PUPDR_PUPD7_Msk',['../group___peripheral___registers___bits___definition.html#ga268436f429d673b3b39ea443656997ad',1,'stm32f407xx_matlab.h']]], - ['gpio_5fpupdr_5fpupd7_5fpos_977',['GPIO_PUPDR_PUPD7_Pos',['../group___peripheral___registers___bits___definition.html#ga3de6729553a81ba44a7d1b93378d9536',1,'stm32f407xx_matlab.h']]], - ['gpio_5fpupdr_5fpupd8_978',['GPIO_PUPDR_PUPD8',['../group___peripheral___registers___bits___definition.html#ga0e71b61abf42a76033e458460793f940',1,'stm32f407xx_matlab.h']]], - ['gpio_5fpupdr_5fpupd8_5f0_979',['GPIO_PUPDR_PUPD8_0',['../group___peripheral___registers___bits___definition.html#ga430de706497b304d9821b50b3a51ac49',1,'stm32f407xx_matlab.h']]], - ['gpio_5fpupdr_5fpupd8_5f1_980',['GPIO_PUPDR_PUPD8_1',['../group___peripheral___registers___bits___definition.html#gae9a687c70a3cd5ef5ccef3a13e431b89',1,'stm32f407xx_matlab.h']]], - ['gpio_5fpupdr_5fpupd8_5fmsk_981',['GPIO_PUPDR_PUPD8_Msk',['../group___peripheral___registers___bits___definition.html#ga750db53344fb2cc3fb432ff0d7faa85c',1,'stm32f407xx_matlab.h']]], - ['gpio_5fpupdr_5fpupd8_5fpos_982',['GPIO_PUPDR_PUPD8_Pos',['../group___peripheral___registers___bits___definition.html#ga55b1f4d9f5e3bedd3c6af387409e5eba',1,'stm32f407xx_matlab.h']]], - ['gpio_5fpupdr_5fpupd9_983',['GPIO_PUPDR_PUPD9',['../group___peripheral___registers___bits___definition.html#ga5c7ece6fe1df8b61fd7f11f6751693a9',1,'stm32f407xx_matlab.h']]], - ['gpio_5fpupdr_5fpupd9_5f0_984',['GPIO_PUPDR_PUPD9_0',['../group___peripheral___registers___bits___definition.html#ga5b6a86ea34af6c236caa23893d34e6d2',1,'stm32f407xx_matlab.h']]], - ['gpio_5fpupdr_5fpupd9_5f1_985',['GPIO_PUPDR_PUPD9_1',['../group___peripheral___registers___bits___definition.html#ga07fb1faf433996b633d49c8307ce9bb2',1,'stm32f407xx_matlab.h']]], - ['gpio_5fpupdr_5fpupd9_5fmsk_986',['GPIO_PUPDR_PUPD9_Msk',['../group___peripheral___registers___bits___definition.html#gae60c0e898107eed9a832cc445d00e8f8',1,'stm32f407xx_matlab.h']]], - ['gpio_5fpupdr_5fpupd9_5fpos_987',['GPIO_PUPDR_PUPD9_Pos',['../group___peripheral___registers___bits___definition.html#gab0e83ee550967747ec5a38f064031b3e',1,'stm32f407xx_matlab.h']]], - ['gpio_5fpupdr_5fpupdr0_988',['GPIO_PUPDR_PUPDR0',['../group___peripheral___registers___bits___definition.html#ga04d9e85c6ccb1c915142139b2fd40277',1,'stm32f407xx_matlab.h']]], - ['gpio_5fpupdr_5fpupdr0_5f0_989',['GPIO_PUPDR_PUPDR0_0',['../group___peripheral___registers___bits___definition.html#ga90ce7d30e6ae0b2faca4a6861ecc4cc6',1,'stm32f407xx_matlab.h']]], - ['gpio_5fpupdr_5fpupdr0_5f1_990',['GPIO_PUPDR_PUPDR0_1',['../group___peripheral___registers___bits___definition.html#gafce37884b3fefd13f415d3d0e86cba54',1,'stm32f407xx_matlab.h']]], - ['gpio_5fpupdr_5fpupdr1_991',['GPIO_PUPDR_PUPDR1',['../group___peripheral___registers___bits___definition.html#ga2fc992293f3aea2c0bfb5a04524a0f29',1,'stm32f407xx_matlab.h']]], - ['gpio_5fpupdr_5fpupdr10_992',['GPIO_PUPDR_PUPDR10',['../group___peripheral___registers___bits___definition.html#gac3ea3497ce2e90ac0e709e7a99088b09',1,'stm32f407xx_matlab.h']]], - ['gpio_5fpupdr_5fpupdr10_5f0_993',['GPIO_PUPDR_PUPDR10_0',['../group___peripheral___registers___bits___definition.html#ga67fd34cdbc389ee49f5a9bf1271d7dd9',1,'stm32f407xx_matlab.h']]], - ['gpio_5fpupdr_5fpupdr10_5f1_994',['GPIO_PUPDR_PUPDR10_1',['../group___peripheral___registers___bits___definition.html#ga08ac8e25da27d1b6c97647fd18b3a335',1,'stm32f407xx_matlab.h']]], - ['gpio_5fpupdr_5fpupdr11_995',['GPIO_PUPDR_PUPDR11',['../group___peripheral___registers___bits___definition.html#gaaa93fd3e658c07a9daf9c8016fb4cf46',1,'stm32f407xx_matlab.h']]], - ['gpio_5fpupdr_5fpupdr11_5f0_996',['GPIO_PUPDR_PUPDR11_0',['../group___peripheral___registers___bits___definition.html#ga18b3ea6ccb52b072cb19d6677b610831',1,'stm32f407xx_matlab.h']]], - ['gpio_5fpupdr_5fpupdr11_5f1_997',['GPIO_PUPDR_PUPDR11_1',['../group___peripheral___registers___bits___definition.html#ga78a3508e309b9acfa99c3a4301dfb0d8',1,'stm32f407xx_matlab.h']]], - ['gpio_5fpupdr_5fpupdr12_998',['GPIO_PUPDR_PUPDR12',['../group___peripheral___registers___bits___definition.html#ga9ae4262e6f46de65ce93149a20e0d006',1,'stm32f407xx_matlab.h']]], - ['gpio_5fpupdr_5fpupdr12_5f0_999',['GPIO_PUPDR_PUPDR12_0',['../group___peripheral___registers___bits___definition.html#ga9a0cd6d85037a7ae0d19806a7dc428a0',1,'stm32f407xx_matlab.h']]], - ['gpio_5fpupdr_5fpupdr12_5f1_1000',['GPIO_PUPDR_PUPDR12_1',['../group___peripheral___registers___bits___definition.html#ga460b8f9029d8703782110e118fd6ccdb',1,'stm32f407xx_matlab.h']]], - ['gpio_5fpupdr_5fpupdr13_1001',['GPIO_PUPDR_PUPDR13',['../group___peripheral___registers___bits___definition.html#gaa63ee70f61bc9df40d9b38af69f93a7e',1,'stm32f407xx_matlab.h']]], - ['gpio_5fpupdr_5fpupdr13_5f0_1002',['GPIO_PUPDR_PUPDR13_0',['../group___peripheral___registers___bits___definition.html#gae29eccc9daf15c787ebfc26af3fb3194',1,'stm32f407xx_matlab.h']]], - ['gpio_5fpupdr_5fpupdr13_5f1_1003',['GPIO_PUPDR_PUPDR13_1',['../group___peripheral___registers___bits___definition.html#ga80eddbf0106ccf71413851269315125d',1,'stm32f407xx_matlab.h']]], - ['gpio_5fpupdr_5fpupdr14_1004',['GPIO_PUPDR_PUPDR14',['../group___peripheral___registers___bits___definition.html#ga62f533a38f324be7e3e68f5c0f2b3570',1,'stm32f407xx_matlab.h']]], - ['gpio_5fpupdr_5fpupdr14_5f0_1005',['GPIO_PUPDR_PUPDR14_0',['../group___peripheral___registers___bits___definition.html#gad8521ddc4fa71b57540b61ec7803e77f',1,'stm32f407xx_matlab.h']]], - ['gpio_5fpupdr_5fpupdr14_5f1_1006',['GPIO_PUPDR_PUPDR14_1',['../group___peripheral___registers___bits___definition.html#gac5bcc6307af9a6e5f578dfcb4fda49b3',1,'stm32f407xx_matlab.h']]], - ['gpio_5fpupdr_5fpupdr15_1007',['GPIO_PUPDR_PUPDR15',['../group___peripheral___registers___bits___definition.html#gac266bda493b96f1200bc0f7ae05a7475',1,'stm32f407xx_matlab.h']]], - ['gpio_5fpupdr_5fpupdr15_5f0_1008',['GPIO_PUPDR_PUPDR15_0',['../group___peripheral___registers___bits___definition.html#ga0b6f6a720852e3791433148aab8b722c',1,'stm32f407xx_matlab.h']]], - ['gpio_5fpupdr_5fpupdr15_5f1_1009',['GPIO_PUPDR_PUPDR15_1',['../group___peripheral___registers___bits___definition.html#ga0d827196cbbdebdf82554c8c04a1db6f',1,'stm32f407xx_matlab.h']]], - ['gpio_5fpupdr_5fpupdr1_5f0_1010',['GPIO_PUPDR_PUPDR1_0',['../group___peripheral___registers___bits___definition.html#gaf102b1b4f826fdc1febfeaf42a7d8a7f',1,'stm32f407xx_matlab.h']]], - ['gpio_5fpupdr_5fpupdr1_5f1_1011',['GPIO_PUPDR_PUPDR1_1',['../group___peripheral___registers___bits___definition.html#ga33e13010f729b9a9555c1af45ee42bf7',1,'stm32f407xx_matlab.h']]], - ['gpio_5fpupdr_5fpupdr2_1012',['GPIO_PUPDR_PUPDR2',['../group___peripheral___registers___bits___definition.html#ga719f6a7905af1965aeb1d22053819ea4',1,'stm32f407xx_matlab.h']]], - ['gpio_5fpupdr_5fpupdr2_5f0_1013',['GPIO_PUPDR_PUPDR2_0',['../group___peripheral___registers___bits___definition.html#gae53f1f88362bc9d12367842b2c41ac5f',1,'stm32f407xx_matlab.h']]], - ['gpio_5fpupdr_5fpupdr2_5f1_1014',['GPIO_PUPDR_PUPDR2_1',['../group___peripheral___registers___bits___definition.html#gad00c76742cc343b8be0aef2b7a552b21',1,'stm32f407xx_matlab.h']]], - ['gpio_5fpupdr_5fpupdr3_1015',['GPIO_PUPDR_PUPDR3',['../group___peripheral___registers___bits___definition.html#gaaae9d69d2db60b442144cc0f7427455d',1,'stm32f407xx_matlab.h']]], - ['gpio_5fpupdr_5fpupdr3_5f0_1016',['GPIO_PUPDR_PUPDR3_0',['../group___peripheral___registers___bits___definition.html#ga1fa0a8d6a6bfc0dd9d6cd2cf26a736a9',1,'stm32f407xx_matlab.h']]], - ['gpio_5fpupdr_5fpupdr3_5f1_1017',['GPIO_PUPDR_PUPDR3_1',['../group___peripheral___registers___bits___definition.html#ga9bd409075d0271cfcf5f2a382f55af83',1,'stm32f407xx_matlab.h']]], - ['gpio_5fpupdr_5fpupdr4_1018',['GPIO_PUPDR_PUPDR4',['../group___peripheral___registers___bits___definition.html#ga46b83340a77ca8575458294e095a1b3e',1,'stm32f407xx_matlab.h']]], - ['gpio_5fpupdr_5fpupdr4_5f0_1019',['GPIO_PUPDR_PUPDR4_0',['../group___peripheral___registers___bits___definition.html#gaaaa42ab206386a753e8d57b76761d787',1,'stm32f407xx_matlab.h']]], - ['gpio_5fpupdr_5fpupdr4_5f1_1020',['GPIO_PUPDR_PUPDR4_1',['../group___peripheral___registers___bits___definition.html#gaa7c19b72c8d4ebff81d9e7a6bb292d9e',1,'stm32f407xx_matlab.h']]], - ['gpio_5fpupdr_5fpupdr5_1021',['GPIO_PUPDR_PUPDR5',['../group___peripheral___registers___bits___definition.html#ga184f05795320c61aac7d5f99875aaaf3',1,'stm32f407xx_matlab.h']]], - ['gpio_5fpupdr_5fpupdr5_5f0_1022',['GPIO_PUPDR_PUPDR5_0',['../group___peripheral___registers___bits___definition.html#ga407f836cfe9440c0a9346bae50593324',1,'stm32f407xx_matlab.h']]], - ['gpio_5fpupdr_5fpupdr5_5f1_1023',['GPIO_PUPDR_PUPDR5_1',['../group___peripheral___registers___bits___definition.html#ga6e969eee59eb13d03cecb10296f3cba3',1,'stm32f407xx_matlab.h']]], - ['gpio_5fpupdr_5fpupdr6_1024',['GPIO_PUPDR_PUPDR6',['../group___peripheral___registers___bits___definition.html#ga867aff49673e9c790a7c07ffc94c9426',1,'stm32f407xx_matlab.h']]], - ['gpio_5fpupdr_5fpupdr6_5f0_1025',['GPIO_PUPDR_PUPDR6_0',['../group___peripheral___registers___bits___definition.html#gaa74c5941b0d588bfd8334c97dd16871e',1,'stm32f407xx_matlab.h']]], - ['gpio_5fpupdr_5fpupdr6_5f1_1026',['GPIO_PUPDR_PUPDR6_1',['../group___peripheral___registers___bits___definition.html#ga84fe57689233ae16b9b38b3db0f8b31b',1,'stm32f407xx_matlab.h']]], - ['gpio_5fpupdr_5fpupdr7_1027',['GPIO_PUPDR_PUPDR7',['../group___peripheral___registers___bits___definition.html#gaa747a73c564fc74b1b7cf597b4df2e2f',1,'stm32f407xx_matlab.h']]], - ['gpio_5fpupdr_5fpupdr7_5f0_1028',['GPIO_PUPDR_PUPDR7_0',['../group___peripheral___registers___bits___definition.html#ga7b75312f187bed2ef764a0f244b8cd1b',1,'stm32f407xx_matlab.h']]], - ['gpio_5fpupdr_5fpupdr7_5f1_1029',['GPIO_PUPDR_PUPDR7_1',['../group___peripheral___registers___bits___definition.html#ga284ea60cb769d74a000af43ddebfdbeb',1,'stm32f407xx_matlab.h']]], - ['gpio_5fpupdr_5fpupdr8_1030',['GPIO_PUPDR_PUPDR8',['../group___peripheral___registers___bits___definition.html#ga1c9d14950ed3985ab81c13047ac0df81',1,'stm32f407xx_matlab.h']]], - ['gpio_5fpupdr_5fpupdr8_5f0_1031',['GPIO_PUPDR_PUPDR8_0',['../group___peripheral___registers___bits___definition.html#ga76b3b97a4a27a8bb2e942c0f95f7af31',1,'stm32f407xx_matlab.h']]], - ['gpio_5fpupdr_5fpupdr8_5f1_1032',['GPIO_PUPDR_PUPDR8_1',['../group___peripheral___registers___bits___definition.html#gab9963e91e82f1059ec170793cbf32986',1,'stm32f407xx_matlab.h']]], - ['gpio_5fpupdr_5fpupdr9_1033',['GPIO_PUPDR_PUPDR9',['../group___peripheral___registers___bits___definition.html#ga35b41b7cab641de2538e1e1d21562bc8',1,'stm32f407xx_matlab.h']]], - ['gpio_5fpupdr_5fpupdr9_5f0_1034',['GPIO_PUPDR_PUPDR9_0',['../group___peripheral___registers___bits___definition.html#ga45a4501a9b4ff20e5404a97031e02537',1,'stm32f407xx_matlab.h']]], - ['gpio_5fpupdr_5fpupdr9_5f1_1035',['GPIO_PUPDR_PUPDR9_1',['../group___peripheral___registers___bits___definition.html#gaef8b9bad1bc1bb219f6b51bb12c48e67',1,'stm32f407xx_matlab.h']]], - ['gpio_5fsimulator_1036',['GPIO_SIMULATOR',['../group___g_p_i_o___s_i_m_u_l_a_t_o_r.html',1,'']]], - ['gpio_5fto_5fsfunc_1037',['GPIO_to_SFUNC',['../group___g_p_i_o___s_i_m_u_l_a_t_o_r.html#ga487177c90297da30ee8ec0dca0ce3067',1,'GPIO_to_SFUNC(real_T *disc): stm32f4xx_matlab_gpio.c'],['../group___g_p_i_o___s_i_m_u_l_a_t_o_r.html#ga487177c90297da30ee8ec0dca0ce3067',1,'GPIO_to_SFUNC(real_T *in): stm32f4xx_matlab_gpio.c']]], - ['gpio_5ftypedef_1038',['GPIO_TypeDef',['../struct_g_p_i_o___type_def.html',1,'']]], - ['gpioa_1039',['gpioa',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#gafe2a610b007523788505f398360469f5',1,'stm32f4xx_periph_registers.c']]], - ['gpioa_1040',['GPIOA',['../group___peripheral__declaration.html#gac485358099728ddae050db37924dd6b7',1,'stm32f407xx_matlab.h']]], - ['gpioa_5fbase_1041',['GPIOA_BASE',['../group___peripheral__memory__map.html#gad7723846cc5db8e43a44d78cf21f6efa',1,'stm32f407xx_matlab.h']]], - ['gpiob_1042',['gpiob',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#gade602c9d7c12472827a033d5b2e8aa23',1,'stm32f4xx_periph_registers.c']]], - ['gpiob_1043',['GPIOB',['../group___peripheral__declaration.html#ga68b66ac73be4c836db878a42e1fea3cd',1,'stm32f407xx_matlab.h']]], - ['gpiob_5fbase_1044',['GPIOB_BASE',['../group___peripheral__memory__map.html#gac944a89eb789000ece920c0f89cb6a68',1,'stm32f407xx_matlab.h']]], - ['gpioc_1045',['gpioc',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga2dab7cbce8521c60951c6342c19bb501',1,'stm32f4xx_periph_registers.c']]], - ['gpioc_1046',['GPIOC',['../group___peripheral__declaration.html#ga2dca03332d620196ba943bc2346eaa08',1,'stm32f407xx_matlab.h']]], - ['gpioc_5fbase_1047',['GPIOC_BASE',['../group___peripheral__memory__map.html#ga26f267dc35338eef219544c51f1e6b3f',1,'stm32f407xx_matlab.h']]], - ['gpiod_1048',['gpiod',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#gad48004dee1cfc09b9c68d896ea43be11',1,'stm32f4xx_periph_registers.c']]], - ['gpiod_1049',['GPIOD',['../group___peripheral__declaration.html#ga7580b1a929ea9df59725ba9c18eba6ac',1,'stm32f407xx_matlab.h']]], - ['gpiod_5fbase_1050',['GPIOD_BASE',['../group___peripheral__memory__map.html#ga1a93ab27129f04064089616910c296ec',1,'stm32f407xx_matlab.h']]], - ['gpioe_1051',['GPIOE',['../group___peripheral__declaration.html#gae04bdb5e8acc47cab1d0532e6b0d0763',1,'stm32f407xx_matlab.h']]], - ['gpioe_1052',['gpioe',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga179dea27e5a083e03fc241f28043becf',1,'stm32f4xx_periph_registers.c']]], - ['gpioe_5fbase_1053',['GPIOE_BASE',['../group___peripheral__memory__map.html#gab487b1983d936c4fee3e9e88b95aad9d',1,'stm32f407xx_matlab.h']]], - ['gpiof_1054',['gpiof',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga655c6a3fda1e8cc9126d4a2070d7e462',1,'stm32f4xx_periph_registers.c']]], - ['gpiof_1055',['GPIOF',['../group___peripheral__declaration.html#ga43c3022dede7c9db7a58d3c3409dbc8d',1,'stm32f407xx_matlab.h']]], - ['gpiof_5fbase_1056',['GPIOF_BASE',['../group___peripheral__memory__map.html#ga7f9a3f4223a1a784af464a114978d26e',1,'stm32f407xx_matlab.h']]], - ['gpiog_1057',['GPIOG',['../group___peripheral__declaration.html#ga02a2a23a32f9b02166a8c64012842414',1,'stm32f407xx_matlab.h']]], - ['gpiog_1058',['gpiog',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#gaed4e2f21f491ff70becdc5a582a2ad67',1,'stm32f4xx_periph_registers.c']]], - ['gpiog_5fbase_1059',['GPIOG_BASE',['../group___peripheral__memory__map.html#ga5d8ca4020f2e8c00bde974e8e7c13cfe',1,'stm32f407xx_matlab.h']]], - ['gpioh_1060',['GPIOH',['../group___peripheral__declaration.html#gadeacbb43ae86c879945afe98c679b285',1,'stm32f407xx_matlab.h']]], - ['gpioh_1061',['gpioh',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga9d4756994de85ee04d0086406c01c00b',1,'stm32f4xx_periph_registers.c']]], - ['gpioh_5fbase_1062',['GPIOH_BASE',['../group___peripheral__memory__map.html#gaee4716389f3a1c727495375b76645608',1,'stm32f407xx_matlab.h']]], - ['gpioi_1063',['GPIOI',['../group___peripheral__declaration.html#gad15f13545ecdbbabfccf43d5997e5ade',1,'stm32f407xx_matlab.h']]], - ['gpioi_1064',['gpioi',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga4fa8522689e49acbf45dc4e5a49d19ef',1,'stm32f4xx_periph_registers.c']]], - ['gpioi_5fbase_1065',['GPIOI_BASE',['../group___peripheral__memory__map.html#ga50acf918c2e1c4597d5ccfe25eb3ad3d',1,'stm32f407xx_matlab.h']]], - ['grstctl_1066',['GRSTCTL',['../group___c_m_s_i_s___device.html#gaecf297022669fda29294f6fe9818ebbd',1,'USB_OTG_GlobalTypeDef']]], - ['grxfsiz_1067',['GRXFSIZ',['../group___c_m_s_i_s___device.html#ga1140b76ff103608f66c26ad0a3d595d0',1,'USB_OTG_GlobalTypeDef']]], - ['grxstsp_1068',['GRXSTSP',['../group___c_m_s_i_s___device.html#ga026f1fea708d42ed74b0bd8a488bc55e',1,'USB_OTG_GlobalTypeDef']]], - ['grxstsr_1069',['GRXSTSR',['../group___c_m_s_i_s___device.html#ga9925d279a01c6e9713426315e2e44c87',1,'USB_OTG_GlobalTypeDef']]], - ['gtpr_1070',['GTPR',['../group___c_m_s_i_s___device.html#ga5dd0cb6c861eaf26470f56f451c1edbf',1,'USART_TypeDef']]], - ['gusbcfg_1071',['GUSBCFG',['../group___c_m_s_i_s___device.html#ga0633538b8b7a6f1372d38938851bba87',1,'USB_OTG_GlobalTypeDef']]] + ['getcompilerconfigurations_0',['getCompilerConfigurations',['../mexing_8m.html#a8c4063b39743b0fdb6cbd8100456a07d',1,'mexing.m']]], + ['gpio_20simulator_1',['GPIO Simulator',['../group___g_p_i_o___s_i_m_u_l_a_t_o_r.html',1,'']]], + ['gpio_5fto_5fsfunc_2',['GPIO_to_SFUNC',['../group___g_p_i_o___s_i_m_u_l_a_t_o_r.html#ga487177c90297da30ee8ec0dca0ce3067',1,'GPIO_to_SFUNC(real_T *out_buff): stm32f4xx_matlab_gpio.c'],['../group___g_p_i_o___s_i_m_u_l_a_t_o_r.html#ga487177c90297da30ee8ec0dca0ce3067',1,'GPIO_to_SFUNC(real_T *in): stm32f4xx_matlab_gpio.c']]], + ['gpioa_3',['gpioa',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#gafe2a610b007523788505f398360469f5',1,'stm32f4xx_periph_registers.c']]], + ['gpiob_4',['gpiob',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#gade602c9d7c12472827a033d5b2e8aa23',1,'stm32f4xx_periph_registers.c']]], + ['gpioc_5',['gpioc',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga2dab7cbce8521c60951c6342c19bb501',1,'stm32f4xx_periph_registers.c']]], + ['gpiod_6',['gpiod',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#gad48004dee1cfc09b9c68d896ea43be11',1,'stm32f4xx_periph_registers.c']]], + ['gpioe_7',['gpioe',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga179dea27e5a083e03fc241f28043becf',1,'stm32f4xx_periph_registers.c']]], + ['gpiof_8',['gpiof',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga655c6a3fda1e8cc9126d4a2070d7e462',1,'stm32f4xx_periph_registers.c']]], + ['gpiog_9',['gpiog',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#gaed4e2f21f491ff70becdc5a582a2ad67',1,'stm32f4xx_periph_registers.c']]], + ['gpioh_10',['gpioh',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga9d4756994de85ee04d0086406c01c00b',1,'stm32f4xx_periph_registers.c']]], + ['gpioi_11',['gpioi',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga4fa8522689e49acbf45dc4e5a49d19ef',1,'stm32f4xx_periph_registers.c']]] ]; diff --git a/DOCS/html/search/all_8.js b/DOCS/html/search/all_8.js index 4ae55e8..1225959 100644 --- a/DOCS/html/search/all_8.js +++ b/DOCS/html/search/all_8.js @@ -1,27 +1,7 @@ var searchData= [ - ['haint_0',['HAINT',['../group___c_m_s_i_s___device.html#ga9fb9e43255829e50b9e5416d58ae11be',1,'USB_OTG_HostTypeDef']]], - ['haintmsk_1',['HAINTMSK',['../group___c_m_s_i_s___device.html#ga4d431ac4a59cbb89ed82a6c6cf9dfc39',1,'USB_OTG_HostTypeDef']]], - ['handle_2',['HANDLE',['../group___m_c_u___w_r_a_p_p_e_r.html#gaa8c0374618b33785ccb02f74bcfebc46',1,'mcu_wrapper_conf.h']]], - ['hardware_5fconstant_5fdefinition_3',['Hardware_Constant_Definition',['../group___hardware___constant___definition.html',1,'']]], - ['hash_5frng_5firqn_4',['HASH_RNG_IRQn',['../group___peripheral__interrupt__number__definition.html#ga70479d84b2227bd03eca17d75ced09c1',1,'stm32f407xx_matlab.h']]], - ['hcchar_5',['HCCHAR',['../group___c_m_s_i_s___device.html#gac1d0619a44758dcaeeda5c0b9c22f784',1,'USB_OTG_HostChannelTypeDef']]], - ['hcdma_6',['HCDMA',['../group___c_m_s_i_s___device.html#gaf294702e1d54fe06b43e7a3b4033dc2e',1,'USB_OTG_HostChannelTypeDef']]], - ['hcfg_7',['HCFG',['../group___c_m_s_i_s___device.html#gaa15bc4ab9217b295560dbda2235c745a',1,'USB_OTG_HostTypeDef']]], - ['hcint_8',['HCINT',['../group___c_m_s_i_s___device.html#ga830a2b58d0eb53a7ec8f9816103e3bc1',1,'USB_OTG_HostChannelTypeDef']]], - ['hcintmsk_9',['HCINTMSK',['../group___c_m_s_i_s___device.html#gae69520f078c84fb1d33cd7551ff23342',1,'USB_OTG_HostChannelTypeDef']]], - ['hclk_5fvalue_10',['HCLK_Value',['../group___r_c_c___s_i_m_u_l_a_t_o_r.html#ga28d73042ad2f34965a12d5dca1c72c7d',1,'stm32f4xx_matlab_rcc.h']]], - ['hcsplt_11',['HCSPLT',['../group___c_m_s_i_s___device.html#gad715951248900b9a7c8c9ddb688bb3a0',1,'USB_OTG_HostChannelTypeDef']]], - ['hctsiz_12',['HCTSIZ',['../group___c_m_s_i_s___device.html#gadde42c516172a887c570545d965200cf',1,'USB_OTG_HostChannelTypeDef']]], - ['hfir_13',['HFIR',['../group___c_m_s_i_s___device.html#ga0a6f11662e44ad485cc869f49e5aa9c9',1,'USB_OTG_HostTypeDef']]], - ['hfnum_14',['HFNUM',['../group___c_m_s_i_s___device.html#ga6a141fc0dab9ee8930465a2da604420f',1,'USB_OTG_HostTypeDef']]], - ['hfsr_15',['HFSR',['../group___c_m_s_i_s__core___debug_functions.html#gab974e7ceb2e52a3fbcaa84e06e52922d',1,'SCB_Type']]], - ['hifcr_16',['HIFCR',['../group___c_m_s_i_s___device.html#gac55c27aeea4107813c1e7da3fcf46961',1,'DMA_TypeDef']]], - ['hisr_17',['HISR',['../group___c_m_s_i_s___device.html#ga6fe40f7ac1a18c2726b328b5ec02b262',1,'DMA_TypeDef']]], - ['hmcu_18',['hmcu',['../mcu__wrapper_8c.html#a7bd77e7f9825a3661f357e430246bfe8',1,'hmcu: mcu_wrapper.c'],['../mcu__wrapper__conf_8h.html#a7bd77e7f9825a3661f357e430246bfe8',1,'hmcu: mcu_wrapper.c']]], - ['hmcuthread_19',['hMCUThread',['../struct_s_i_m_____m_c_u_handle_type_def.html#af2b1efce882c9bc0926c715c16773afb',1,'SIM__MCUHandleTypeDef']]], - ['hnptxsts_20',['HNPTXSTS',['../group___c_m_s_i_s___device.html#ga6ff3c8a6647ae7e5dfcd2ccfbfed4948',1,'USB_OTG_GlobalTypeDef']]], - ['hptxfsiz_21',['HPTXFSIZ',['../group___c_m_s_i_s___device.html#ga928fd38284165374eb5aa85ed8d4e6cb',1,'USB_OTG_GlobalTypeDef']]], - ['hptxsts_22',['HPTXSTS',['../group___c_m_s_i_s___device.html#ga3903a00940c32a9f09889e08881e7a6a',1,'USB_OTG_HostTypeDef']]], - ['htr_23',['HTR',['../group___c_m_s_i_s___device.html#ga24c3512abcc90ef75cf3e9145e5dbe9b',1,'ADC_TypeDef']]] + ['handle_0',['HANDLE',['../group___m_c_u___w_r_a_p_p_e_r.html#gaa8c0374618b33785ccb02f74bcfebc46',1,'mcu_wrapper_conf.h']]], + ['hclk_5fvalue_1',['HCLK_Value',['../group___r_c_c___s_i_m_u_l_a_t_o_r.html#ga28d73042ad2f34965a12d5dca1c72c7d',1,'stm32f4xx_matlab_rcc.h']]], + ['hmcu_2',['hmcu',['../group___w_r_a_p_p_e_r___c_o_n_f.html#ga7bd77e7f9825a3661f357e430246bfe8',1,'hmcu: mcu_wrapper.c'],['../group___m_c_u___w_r_a_p_p_e_r.html#ga7bd77e7f9825a3661f357e430246bfe8',1,'hmcu: mcu_wrapper.c']]], + ['hmcuthread_3',['hMCUThread',['../struct_s_i_m_____m_c_u_handle_type_def.html#af2b1efce882c9bc0926c715c16773afb',1,'SIM__MCUHandleTypeDef']]] ]; diff --git a/DOCS/html/search/all_9.js b/DOCS/html/search/all_9.js index b03ace9..b40d62f 100644 --- a/DOCS/html/search/all_9.js +++ b/DOCS/html/search/all_9.js @@ -1,424 +1,17 @@ var searchData= [ ['i2c1_0',['i2c1',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga71aad08961ac03edca6186fa9bc61b8e',1,'stm32f4xx_periph_registers.c']]], - ['i2c1_1',['I2C1',['../group___peripheral__declaration.html#gab45d257574da6fe1f091cc45b7eda6cc',1,'stm32f407xx_matlab.h']]], - ['i2c1_5fbase_2',['I2C1_BASE',['../group___peripheral__memory__map.html#gacd72dbffb1738ca87c838545c4eb85a3',1,'stm32f407xx_matlab.h']]], - ['i2c1_5fer_5firqn_3',['I2C1_ER_IRQn',['../group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a2ec363869f4488782dc10a60abce3b34',1,'stm32f407xx_matlab.h']]], - ['i2c1_5fev_5firqn_4',['I2C1_EV_IRQn',['../group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a9852dbbe8c014e716ce7e03a7b809751',1,'stm32f407xx_matlab.h']]], - ['i2c2_5',['I2C2',['../group___peripheral__declaration.html#gafa60ac20c1921ef1002083bb3e1f5d16',1,'stm32f407xx_matlab.h']]], - ['i2c2_6',['i2c2',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#gaf4f631faa01cf5bb61ddc01eeb90d522',1,'stm32f4xx_periph_registers.c']]], - ['i2c2_5fbase_7',['I2C2_BASE',['../group___peripheral__memory__map.html#ga04bda70f25c795fb79f163b633ad4a5d',1,'stm32f407xx_matlab.h']]], - ['i2c2_5fer_5firqn_8',['I2C2_ER_IRQn',['../group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a60c35f2d48d512bd6818bc9fef7053d7',1,'stm32f407xx_matlab.h']]], - ['i2c2_5fev_5firqn_9',['I2C2_EV_IRQn',['../group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a3020193786527c47d2e4d8c92ceee804',1,'stm32f407xx_matlab.h']]], - ['i2c3_10',['i2c3',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#gac651c52b4ae02ee475e7babe47132f15',1,'stm32f4xx_periph_registers.c']]], - ['i2c3_11',['I2C3',['../group___peripheral__declaration.html#ga1489b37ed2bca9d9c659119590583bda',1,'stm32f407xx_matlab.h']]], - ['i2c3_5fbase_12',['I2C3_BASE',['../group___peripheral__memory__map.html#ga4e8b9198748235a1729e1e8f8f24983b',1,'stm32f407xx_matlab.h']]], - ['i2c3_5fer_5firqn_13',['I2C3_ER_IRQn',['../group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a6e954232d164a6942ebc7a6bd6f7736e',1,'stm32f407xx_matlab.h']]], - ['i2c3_5fev_5firqn_14',['I2C3_EV_IRQn',['../group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a8326db2d570cb865ffa1d49fa29d562a',1,'stm32f407xx_matlab.h']]], - ['i2c_5fccr_5fccr_15',['I2C_CCR_CCR',['../group___peripheral___registers___bits___definition.html#ga5c8cb2bd83dd7dbdcf6ca4bbf4a841de',1,'stm32f407xx_matlab.h']]], - ['i2c_5fccr_5fccr_5fmsk_16',['I2C_CCR_CCR_Msk',['../group___peripheral___registers___bits___definition.html#gaf3f68b672f4ff2fa9a6ba3e79e9e302b',1,'stm32f407xx_matlab.h']]], - ['i2c_5fccr_5fccr_5fpos_17',['I2C_CCR_CCR_Pos',['../group___peripheral___registers___bits___definition.html#ga908f5b1edffdedba90f8bbb141eedb8a',1,'stm32f407xx_matlab.h']]], - ['i2c_5fccr_5fduty_18',['I2C_CCR_DUTY',['../group___peripheral___registers___bits___definition.html#ga851c8a6b598d54c1a805b1632a4078e5',1,'stm32f407xx_matlab.h']]], - ['i2c_5fccr_5fduty_5fmsk_19',['I2C_CCR_DUTY_Msk',['../group___peripheral___registers___bits___definition.html#ga7e91ff511dab94ae774aaa9c3052fbc6',1,'stm32f407xx_matlab.h']]], - ['i2c_5fccr_5fduty_5fpos_20',['I2C_CCR_DUTY_Pos',['../group___peripheral___registers___bits___definition.html#ga152abc0c5a01abf887e702cbc9fe4f49',1,'stm32f407xx_matlab.h']]], - ['i2c_5fccr_5ffs_21',['I2C_CCR_FS',['../group___peripheral___registers___bits___definition.html#gaea64e5d7eba609ac9a84964bc0bc2def',1,'stm32f407xx_matlab.h']]], - ['i2c_5fccr_5ffs_5fmsk_22',['I2C_CCR_FS_Msk',['../group___peripheral___registers___bits___definition.html#ga1823d70e520da08c5b40320ed2f8331e',1,'stm32f407xx_matlab.h']]], - ['i2c_5fccr_5ffs_5fpos_23',['I2C_CCR_FS_Pos',['../group___peripheral___registers___bits___definition.html#ga017a81aea2e87d24a49e078079d72313',1,'stm32f407xx_matlab.h']]], - ['i2c_5fcr1_5fack_24',['I2C_CR1_ACK',['../group___peripheral___registers___bits___definition.html#gaf933b105259a4bc46a957576adb8d96d',1,'stm32f407xx_matlab.h']]], - ['i2c_5fcr1_5fack_5fmsk_25',['I2C_CR1_ACK_Msk',['../group___peripheral___registers___bits___definition.html#ga901752f0d8d57314c1bf5841b4d15927',1,'stm32f407xx_matlab.h']]], - ['i2c_5fcr1_5fack_5fpos_26',['I2C_CR1_ACK_Pos',['../group___peripheral___registers___bits___definition.html#gac4d488ef9214c8e156aa5789193b1af2',1,'stm32f407xx_matlab.h']]], - ['i2c_5fcr1_5falert_27',['I2C_CR1_ALERT',['../group___peripheral___registers___bits___definition.html#ga56729ccf93c5d9f5b5b05002e3a2323c',1,'stm32f407xx_matlab.h']]], - ['i2c_5fcr1_5falert_5fmsk_28',['I2C_CR1_ALERT_Msk',['../group___peripheral___registers___bits___definition.html#ga2c1f4432707ef457508aa265173d3ce6',1,'stm32f407xx_matlab.h']]], - ['i2c_5fcr1_5falert_5fpos_29',['I2C_CR1_ALERT_Pos',['../group___peripheral___registers___bits___definition.html#ga2cbad0729b1263ee12efe299c460c7a9',1,'stm32f407xx_matlab.h']]], - ['i2c_5fcr1_5fenarp_30',['I2C_CR1_ENARP',['../group___peripheral___registers___bits___definition.html#ga4598185d9092edfbf943464bcbb342ac',1,'stm32f407xx_matlab.h']]], - ['i2c_5fcr1_5fenarp_5fmsk_31',['I2C_CR1_ENARP_Msk',['../group___peripheral___registers___bits___definition.html#ga608ec88f391d4617d8d196acf88ae4c3',1,'stm32f407xx_matlab.h']]], - ['i2c_5fcr1_5fenarp_5fpos_32',['I2C_CR1_ENARP_Pos',['../group___peripheral___registers___bits___definition.html#ga183847901bff6ed293ac42cedcd0a00f',1,'stm32f407xx_matlab.h']]], - ['i2c_5fcr1_5fengc_33',['I2C_CR1_ENGC',['../group___peripheral___registers___bits___definition.html#ga1d8c219193b11f8507d7b85831d14912',1,'stm32f407xx_matlab.h']]], - ['i2c_5fcr1_5fengc_5fmsk_34',['I2C_CR1_ENGC_Msk',['../group___peripheral___registers___bits___definition.html#ga7eff07d7a774d45f0c0b853be70b1a06',1,'stm32f407xx_matlab.h']]], - ['i2c_5fcr1_5fengc_5fpos_35',['I2C_CR1_ENGC_Pos',['../group___peripheral___registers___bits___definition.html#ga54ffd903ba1ddb087e7166a83b30d145',1,'stm32f407xx_matlab.h']]], - ['i2c_5fcr1_5fenpec_36',['I2C_CR1_ENPEC',['../group___peripheral___registers___bits___definition.html#ga40d2eb849f9d55e6298035b61e84ca42',1,'stm32f407xx_matlab.h']]], - ['i2c_5fcr1_5fenpec_5fmsk_37',['I2C_CR1_ENPEC_Msk',['../group___peripheral___registers___bits___definition.html#ga047dbff196b5cc2e0ca679cf09daad7d',1,'stm32f407xx_matlab.h']]], - ['i2c_5fcr1_5fenpec_5fpos_38',['I2C_CR1_ENPEC_Pos',['../group___peripheral___registers___bits___definition.html#gad6320b277f4eb5ad80869cf46509ab63',1,'stm32f407xx_matlab.h']]], - ['i2c_5fcr1_5fnostretch_39',['I2C_CR1_NOSTRETCH',['../group___peripheral___registers___bits___definition.html#ga197aaca79f64e832af3a0a0864c2a08c',1,'stm32f407xx_matlab.h']]], - ['i2c_5fcr1_5fnostretch_5fmsk_40',['I2C_CR1_NOSTRETCH_Msk',['../group___peripheral___registers___bits___definition.html#ga1e4eb2525f0444cc6320f96cc6c01804',1,'stm32f407xx_matlab.h']]], - ['i2c_5fcr1_5fnostretch_5fpos_41',['I2C_CR1_NOSTRETCH_Pos',['../group___peripheral___registers___bits___definition.html#ga57955bf36ff5f4cd6a753e01817bf3b2',1,'stm32f407xx_matlab.h']]], - ['i2c_5fcr1_5fpe_42',['I2C_CR1_PE',['../group___peripheral___registers___bits___definition.html#ga953b0d38414808db79da116842ed3262',1,'stm32f407xx_matlab.h']]], - ['i2c_5fcr1_5fpe_5fmsk_43',['I2C_CR1_PE_Msk',['../group___peripheral___registers___bits___definition.html#ga641d1563a97f92a4c5e20dcdd0756986',1,'stm32f407xx_matlab.h']]], - ['i2c_5fcr1_5fpe_5fpos_44',['I2C_CR1_PE_Pos',['../group___peripheral___registers___bits___definition.html#ga7954738eae12426137b23733f12c7c14',1,'stm32f407xx_matlab.h']]], - ['i2c_5fcr1_5fpec_45',['I2C_CR1_PEC',['../group___peripheral___registers___bits___definition.html#gab4d0119253d93a106b5ca704e5020c12',1,'stm32f407xx_matlab.h']]], - ['i2c_5fcr1_5fpec_5fmsk_46',['I2C_CR1_PEC_Msk',['../group___peripheral___registers___bits___definition.html#gad603ba46a4c90d87755bc21032343a8e',1,'stm32f407xx_matlab.h']]], - ['i2c_5fcr1_5fpec_5fpos_47',['I2C_CR1_PEC_Pos',['../group___peripheral___registers___bits___definition.html#gae27ac08c854b421c8bbef0f91cb02e77',1,'stm32f407xx_matlab.h']]], - ['i2c_5fcr1_5fpos_48',['I2C_CR1_POS',['../group___peripheral___registers___bits___definition.html#ga34721958229a5983f2e95dfeaa8e55c3',1,'stm32f407xx_matlab.h']]], - ['i2c_5fcr1_5fpos_5fmsk_49',['I2C_CR1_POS_Msk',['../group___peripheral___registers___bits___definition.html#ga44cbb4dfe0bace0e0f63516352cdd686',1,'stm32f407xx_matlab.h']]], - ['i2c_5fcr1_5fpos_5fpos_50',['I2C_CR1_POS_Pos',['../group___peripheral___registers___bits___definition.html#ga1c8ebf2be75a57d79c3963cbb73299e5',1,'stm32f407xx_matlab.h']]], - ['i2c_5fcr1_5fsmbtype_51',['I2C_CR1_SMBTYPE',['../group___peripheral___registers___bits___definition.html#ga001198ff898802888edf58f56d5371c9',1,'stm32f407xx_matlab.h']]], - ['i2c_5fcr1_5fsmbtype_5fmsk_52',['I2C_CR1_SMBTYPE_Msk',['../group___peripheral___registers___bits___definition.html#ga67a812813bce3b9996dec37eff310945',1,'stm32f407xx_matlab.h']]], - ['i2c_5fcr1_5fsmbtype_5fpos_53',['I2C_CR1_SMBTYPE_Pos',['../group___peripheral___registers___bits___definition.html#gaf03323d716d67da6242e4da7431cd1ea',1,'stm32f407xx_matlab.h']]], - ['i2c_5fcr1_5fsmbus_54',['I2C_CR1_SMBUS',['../group___peripheral___registers___bits___definition.html#ga4cfee7b020a49bd037fa7cf27c796abc',1,'stm32f407xx_matlab.h']]], - ['i2c_5fcr1_5fsmbus_5fmsk_55',['I2C_CR1_SMBUS_Msk',['../group___peripheral___registers___bits___definition.html#gadf62afbb725efae2aa5a18c7841cfc51',1,'stm32f407xx_matlab.h']]], - ['i2c_5fcr1_5fsmbus_5fpos_56',['I2C_CR1_SMBUS_Pos',['../group___peripheral___registers___bits___definition.html#gae26dbc9f9c06eb552db052b0603430c0',1,'stm32f407xx_matlab.h']]], - ['i2c_5fcr1_5fstart_57',['I2C_CR1_START',['../group___peripheral___registers___bits___definition.html#ga2ca7f18dd5bc1130dbefae4ff8736143',1,'stm32f407xx_matlab.h']]], - ['i2c_5fcr1_5fstart_5fmsk_58',['I2C_CR1_START_Msk',['../group___peripheral___registers___bits___definition.html#ga20183fa72a3acfb6eb7cd333569af62b',1,'stm32f407xx_matlab.h']]], - ['i2c_5fcr1_5fstart_5fpos_59',['I2C_CR1_START_Pos',['../group___peripheral___registers___bits___definition.html#ga26478428c37301f88c8fe5a27ab7cff0',1,'stm32f407xx_matlab.h']]], - ['i2c_5fcr1_5fstop_60',['I2C_CR1_STOP',['../group___peripheral___registers___bits___definition.html#gace70293f3dfa24d448b600fc58e45223',1,'stm32f407xx_matlab.h']]], - ['i2c_5fcr1_5fstop_5fmsk_61',['I2C_CR1_STOP_Msk',['../group___peripheral___registers___bits___definition.html#gac560445dddd085e2ec78b6c38d290893',1,'stm32f407xx_matlab.h']]], - ['i2c_5fcr1_5fstop_5fpos_62',['I2C_CR1_STOP_Pos',['../group___peripheral___registers___bits___definition.html#ga1acc4153373e71ad85766145727d751f',1,'stm32f407xx_matlab.h']]], - ['i2c_5fcr1_5fswrst_63',['I2C_CR1_SWRST',['../group___peripheral___registers___bits___definition.html#ga8dc661ef13da02e5bcb943f2003d576d',1,'stm32f407xx_matlab.h']]], - ['i2c_5fcr1_5fswrst_5fmsk_64',['I2C_CR1_SWRST_Msk',['../group___peripheral___registers___bits___definition.html#ga87f58f075ab791157d5a7f73d61ea4a0',1,'stm32f407xx_matlab.h']]], - ['i2c_5fcr1_5fswrst_5fpos_65',['I2C_CR1_SWRST_Pos',['../group___peripheral___registers___bits___definition.html#ga5f26e1407449ae64fade6b92a5e85bc9',1,'stm32f407xx_matlab.h']]], - ['i2c_5fcr2_5fdmaen_66',['I2C_CR2_DMAEN',['../group___peripheral___registers___bits___definition.html#gadb81d5c91486b873bd0bf279a4ffcf69',1,'stm32f407xx_matlab.h']]], - ['i2c_5fcr2_5fdmaen_5fmsk_67',['I2C_CR2_DMAEN_Msk',['../group___peripheral___registers___bits___definition.html#ga2987290a42860b8700c2dcfb8eaef399',1,'stm32f407xx_matlab.h']]], - ['i2c_5fcr2_5fdmaen_5fpos_68',['I2C_CR2_DMAEN_Pos',['../group___peripheral___registers___bits___definition.html#ga69b0d5b0217bd628743324b8393bc74a',1,'stm32f407xx_matlab.h']]], - ['i2c_5fcr2_5ffreq_69',['I2C_CR2_FREQ',['../group___peripheral___registers___bits___definition.html#ga293fbe15ed5fd1fc95915bd6437859e7',1,'stm32f407xx_matlab.h']]], - ['i2c_5fcr2_5ffreq_5f0_70',['I2C_CR2_FREQ_0',['../group___peripheral___registers___bits___definition.html#ga09d944f5260f40a0eb714d41859e0d23',1,'stm32f407xx_matlab.h']]], - ['i2c_5fcr2_5ffreq_5f1_71',['I2C_CR2_FREQ_1',['../group___peripheral___registers___bits___definition.html#ga25ab0ef2a7795e3326900b277479d89c',1,'stm32f407xx_matlab.h']]], - ['i2c_5fcr2_5ffreq_5f2_72',['I2C_CR2_FREQ_2',['../group___peripheral___registers___bits___definition.html#ga657af5a02534cc900cbddc260319d845',1,'stm32f407xx_matlab.h']]], - ['i2c_5fcr2_5ffreq_5f3_73',['I2C_CR2_FREQ_3',['../group___peripheral___registers___bits___definition.html#ga655214f8327fd1322998c9d8bffe308d',1,'stm32f407xx_matlab.h']]], - ['i2c_5fcr2_5ffreq_5f4_74',['I2C_CR2_FREQ_4',['../group___peripheral___registers___bits___definition.html#ga3382a7262743bc824985af7339449386',1,'stm32f407xx_matlab.h']]], - ['i2c_5fcr2_5ffreq_5f5_75',['I2C_CR2_FREQ_5',['../group___peripheral___registers___bits___definition.html#gad3b1a2b777fcf158c9e4264485682a20',1,'stm32f407xx_matlab.h']]], - ['i2c_5fcr2_5ffreq_5fmsk_76',['I2C_CR2_FREQ_Msk',['../group___peripheral___registers___bits___definition.html#ga409296c2e8ff17ef7633266fad88d5ea',1,'stm32f407xx_matlab.h']]], - ['i2c_5fcr2_5ffreq_5fpos_77',['I2C_CR2_FREQ_Pos',['../group___peripheral___registers___bits___definition.html#gae37aa57192c71b1b734815130eeee8cd',1,'stm32f407xx_matlab.h']]], - ['i2c_5fcr2_5fitbufen_78',['I2C_CR2_ITBUFEN',['../group___peripheral___registers___bits___definition.html#ga2efbe5d96ed0ce447a45a62e8317a68a',1,'stm32f407xx_matlab.h']]], - ['i2c_5fcr2_5fitbufen_5fmsk_79',['I2C_CR2_ITBUFEN_Msk',['../group___peripheral___registers___bits___definition.html#ga765fa0272f4a94eed64fba9b3cdac713',1,'stm32f407xx_matlab.h']]], - ['i2c_5fcr2_5fitbufen_5fpos_80',['I2C_CR2_ITBUFEN_Pos',['../group___peripheral___registers___bits___definition.html#ga1cf0976d8a817ec970a78137e6bac452',1,'stm32f407xx_matlab.h']]], - ['i2c_5fcr2_5fiterren_81',['I2C_CR2_ITERREN',['../group___peripheral___registers___bits___definition.html#ga6f14ae48e4609c2b3645211234cba974',1,'stm32f407xx_matlab.h']]], - ['i2c_5fcr2_5fiterren_5fmsk_82',['I2C_CR2_ITERREN_Msk',['../group___peripheral___registers___bits___definition.html#ga3cbb0dde5e57765d211af8595a728029',1,'stm32f407xx_matlab.h']]], - ['i2c_5fcr2_5fiterren_5fpos_83',['I2C_CR2_ITERREN_Pos',['../group___peripheral___registers___bits___definition.html#ga1d664ebaabc46a45c4453e17e5132056',1,'stm32f407xx_matlab.h']]], - ['i2c_5fcr2_5fitevten_84',['I2C_CR2_ITEVTEN',['../group___peripheral___registers___bits___definition.html#ga3b1ebaf8173090ec469b055b98e585d2',1,'stm32f407xx_matlab.h']]], - ['i2c_5fcr2_5fitevten_5fmsk_85',['I2C_CR2_ITEVTEN_Msk',['../group___peripheral___registers___bits___definition.html#gac4a4a92cd2663c4e4e690fe5f66a1706',1,'stm32f407xx_matlab.h']]], - ['i2c_5fcr2_5fitevten_5fpos_86',['I2C_CR2_ITEVTEN_Pos',['../group___peripheral___registers___bits___definition.html#gae6b73580546ba348cd434416f7729d65',1,'stm32f407xx_matlab.h']]], - ['i2c_5fcr2_5flast_87',['I2C_CR2_LAST',['../group___peripheral___registers___bits___definition.html#ga6a0955008cbabbb6b726ba0b4f8da609',1,'stm32f407xx_matlab.h']]], - ['i2c_5fcr2_5flast_5fmsk_88',['I2C_CR2_LAST_Msk',['../group___peripheral___registers___bits___definition.html#ga2c9c22f3c0a1abb70e0255c765b30382',1,'stm32f407xx_matlab.h']]], - ['i2c_5fcr2_5flast_5fpos_89',['I2C_CR2_LAST_Pos',['../group___peripheral___registers___bits___definition.html#ga0c908f15a0b4c9e603d17b066fc85b7b',1,'stm32f407xx_matlab.h']]], - ['i2c_5fdr_5fdr_90',['I2C_DR_DR',['../group___peripheral___registers___bits___definition.html#gac43021a4a7f79672d27c36a469b301d5',1,'stm32f407xx_matlab.h']]], - ['i2c_5fdr_5fdr_5fmsk_91',['I2C_DR_DR_Msk',['../group___peripheral___registers___bits___definition.html#ga2b487d8e08e84b2ef59c6de0e92316b1',1,'stm32f407xx_matlab.h']]], - ['i2c_5fdr_5fdr_5fpos_92',['I2C_DR_DR_Pos',['../group___peripheral___registers___bits___definition.html#ga8168b87f1d876a0cdbafff9f3dd922f5',1,'stm32f407xx_matlab.h']]], - ['i2c_5foar1_5fadd0_93',['I2C_OAR1_ADD0',['../group___peripheral___registers___bits___definition.html#ga8b7c20c81f79d17921718412b8fca6d7',1,'stm32f407xx_matlab.h']]], - ['i2c_5foar1_5fadd0_5fmsk_94',['I2C_OAR1_ADD0_Msk',['../group___peripheral___registers___bits___definition.html#ga315ebd53e115b321f02d945a5a485356',1,'stm32f407xx_matlab.h']]], - ['i2c_5foar1_5fadd0_5fpos_95',['I2C_OAR1_ADD0_Pos',['../group___peripheral___registers___bits___definition.html#ga5025971b93434d9d6c1b47ba93cc4249',1,'stm32f407xx_matlab.h']]], - ['i2c_5foar1_5fadd1_96',['I2C_OAR1_ADD1',['../group___peripheral___registers___bits___definition.html#ga499a61f0013c5c6fe38b848901f58769',1,'stm32f407xx_matlab.h']]], - ['i2c_5foar1_5fadd1_5f7_97',['I2C_OAR1_ADD1_7',['../group___peripheral___registers___bits___definition.html#ga8250616a993a5f2bb04cd0f116005864',1,'stm32f407xx_matlab.h']]], - ['i2c_5foar1_5fadd1_5fmsk_98',['I2C_OAR1_ADD1_Msk',['../group___peripheral___registers___bits___definition.html#gaedbc5009a53817d14a5b61b81abe47eb',1,'stm32f407xx_matlab.h']]], - ['i2c_5foar1_5fadd1_5fpos_99',['I2C_OAR1_ADD1_Pos',['../group___peripheral___registers___bits___definition.html#ga53aaf5c99387556eb05205972a9fd765',1,'stm32f407xx_matlab.h']]], - ['i2c_5foar1_5fadd2_100',['I2C_OAR1_ADD2',['../group___peripheral___registers___bits___definition.html#gab44a263e36a7f34d922ff124aebd99c3',1,'stm32f407xx_matlab.h']]], - ['i2c_5foar1_5fadd2_5fmsk_101',['I2C_OAR1_ADD2_Msk',['../group___peripheral___registers___bits___definition.html#ga74d6b1ee8556d79db1f804871576381e',1,'stm32f407xx_matlab.h']]], - ['i2c_5foar1_5fadd2_5fpos_102',['I2C_OAR1_ADD2_Pos',['../group___peripheral___registers___bits___definition.html#gac1601f93351d29fd314910972bd4a997',1,'stm32f407xx_matlab.h']]], - ['i2c_5foar1_5fadd3_103',['I2C_OAR1_ADD3',['../group___peripheral___registers___bits___definition.html#ga9584dca3b1b414a63cf7ba75e557155b',1,'stm32f407xx_matlab.h']]], - ['i2c_5foar1_5fadd3_5fmsk_104',['I2C_OAR1_ADD3_Msk',['../group___peripheral___registers___bits___definition.html#ga3bd895166f6d0f2b1fe5bdb245495e7c',1,'stm32f407xx_matlab.h']]], - ['i2c_5foar1_5fadd3_5fpos_105',['I2C_OAR1_ADD3_Pos',['../group___peripheral___registers___bits___definition.html#ga04c1306ea26d1fde330540af98f2ebaf',1,'stm32f407xx_matlab.h']]], - ['i2c_5foar1_5fadd4_106',['I2C_OAR1_ADD4',['../group___peripheral___registers___bits___definition.html#ga110b915b907f4bf29ff03da1f077bd97',1,'stm32f407xx_matlab.h']]], - ['i2c_5foar1_5fadd4_5fmsk_107',['I2C_OAR1_ADD4_Msk',['../group___peripheral___registers___bits___definition.html#ga3261bcc4b1d94f2800cc78d26ef6a638',1,'stm32f407xx_matlab.h']]], - ['i2c_5foar1_5fadd4_5fpos_108',['I2C_OAR1_ADD4_Pos',['../group___peripheral___registers___bits___definition.html#ga91ebb7dae5c13a499109a9f0089387b2',1,'stm32f407xx_matlab.h']]], - ['i2c_5foar1_5fadd5_109',['I2C_OAR1_ADD5',['../group___peripheral___registers___bits___definition.html#ga0856dee2657cf0a04d79084da86988ca',1,'stm32f407xx_matlab.h']]], - ['i2c_5foar1_5fadd5_5fmsk_110',['I2C_OAR1_ADD5_Msk',['../group___peripheral___registers___bits___definition.html#ga078a30f84550430baa5ea4ce4b424afd',1,'stm32f407xx_matlab.h']]], - ['i2c_5foar1_5fadd5_5fpos_111',['I2C_OAR1_ADD5_Pos',['../group___peripheral___registers___bits___definition.html#ga863a732cfab0b27034149a5d95c1c978',1,'stm32f407xx_matlab.h']]], - ['i2c_5foar1_5fadd6_112',['I2C_OAR1_ADD6',['../group___peripheral___registers___bits___definition.html#ga5507af6154f60125dadc4654f57776ca',1,'stm32f407xx_matlab.h']]], - ['i2c_5foar1_5fadd6_5fmsk_113',['I2C_OAR1_ADD6_Msk',['../group___peripheral___registers___bits___definition.html#ga708c99b9b7c44311be6a91fa01e2603d',1,'stm32f407xx_matlab.h']]], - ['i2c_5foar1_5fadd6_5fpos_114',['I2C_OAR1_ADD6_Pos',['../group___peripheral___registers___bits___definition.html#gadeef10580199e2315af15107d03374b6',1,'stm32f407xx_matlab.h']]], - ['i2c_5foar1_5fadd7_115',['I2C_OAR1_ADD7',['../group___peripheral___registers___bits___definition.html#gaca710515f0aac5abdac02a630e09097c',1,'stm32f407xx_matlab.h']]], - ['i2c_5foar1_5fadd7_5fmsk_116',['I2C_OAR1_ADD7_Msk',['../group___peripheral___registers___bits___definition.html#ga6c9645decd676803bd6a1cb9e5cca0f8',1,'stm32f407xx_matlab.h']]], - ['i2c_5foar1_5fadd7_5fpos_117',['I2C_OAR1_ADD7_Pos',['../group___peripheral___registers___bits___definition.html#gaff51a9d14ec34d35f911c1c4d474db02',1,'stm32f407xx_matlab.h']]], - ['i2c_5foar1_5fadd8_118',['I2C_OAR1_ADD8',['../group___peripheral___registers___bits___definition.html#gab945eba8b842a253cc64cce722537264',1,'stm32f407xx_matlab.h']]], - ['i2c_5foar1_5fadd8_5f9_119',['I2C_OAR1_ADD8_9',['../group___peripheral___registers___bits___definition.html#gab8141dcd63a8429a64d488cc78ef3ec1',1,'stm32f407xx_matlab.h']]], - ['i2c_5foar1_5fadd8_5fmsk_120',['I2C_OAR1_ADD8_Msk',['../group___peripheral___registers___bits___definition.html#ga484398bbd79662011f8fb6467c127d65',1,'stm32f407xx_matlab.h']]], - ['i2c_5foar1_5fadd8_5fpos_121',['I2C_OAR1_ADD8_Pos',['../group___peripheral___registers___bits___definition.html#ga15f7918fdb3af6d0c8ade393fb8c8357',1,'stm32f407xx_matlab.h']]], - ['i2c_5foar1_5fadd9_122',['I2C_OAR1_ADD9',['../group___peripheral___registers___bits___definition.html#ga10cf2dfc6b1ed55413be06acca413430',1,'stm32f407xx_matlab.h']]], - ['i2c_5foar1_5fadd9_5fmsk_123',['I2C_OAR1_ADD9_Msk',['../group___peripheral___registers___bits___definition.html#gaaf1cdf0196ac2b11475fbf7078a852a2',1,'stm32f407xx_matlab.h']]], - ['i2c_5foar1_5fadd9_5fpos_124',['I2C_OAR1_ADD9_Pos',['../group___peripheral___registers___bits___definition.html#gad9208eb446047890ea90e2f87f57a8e0',1,'stm32f407xx_matlab.h']]], - ['i2c_5foar1_5faddmode_125',['I2C_OAR1_ADDMODE',['../group___peripheral___registers___bits___definition.html#ga7d8df80cd27313c896e887aae81fa639',1,'stm32f407xx_matlab.h']]], - ['i2c_5foar1_5faddmode_5fmsk_126',['I2C_OAR1_ADDMODE_Msk',['../group___peripheral___registers___bits___definition.html#ga465856ef24302471bd5562be5f4d8418',1,'stm32f407xx_matlab.h']]], - ['i2c_5foar1_5faddmode_5fpos_127',['I2C_OAR1_ADDMODE_Pos',['../group___peripheral___registers___bits___definition.html#ga0a9d87efeab027259266521e849cd0f6',1,'stm32f407xx_matlab.h']]], - ['i2c_5foar2_5fadd2_128',['I2C_OAR2_ADD2',['../group___peripheral___registers___bits___definition.html#gadd3d8fd1de1f16d051efb52dd3d657c4',1,'stm32f407xx_matlab.h']]], - ['i2c_5foar2_5fadd2_5fmsk_129',['I2C_OAR2_ADD2_Msk',['../group___peripheral___registers___bits___definition.html#ga18d179042a15bdc94dd4477b990082c5',1,'stm32f407xx_matlab.h']]], - ['i2c_5foar2_5fadd2_5fpos_130',['I2C_OAR2_ADD2_Pos',['../group___peripheral___registers___bits___definition.html#ga809d88f42d6572f85dd75ab2bb92b243',1,'stm32f407xx_matlab.h']]], - ['i2c_5foar2_5fendual_131',['I2C_OAR2_ENDUAL',['../group___peripheral___registers___bits___definition.html#gab83ed1ee64439cb2734a708445f37e94',1,'stm32f407xx_matlab.h']]], - ['i2c_5foar2_5fendual_5fmsk_132',['I2C_OAR2_ENDUAL_Msk',['../group___peripheral___registers___bits___definition.html#ga28fa608f2cec586e6bdb98ae510022d9',1,'stm32f407xx_matlab.h']]], - ['i2c_5foar2_5fendual_5fpos_133',['I2C_OAR2_ENDUAL_Pos',['../group___peripheral___registers___bits___definition.html#gabd1b7689ba1197bb496f7b0042e59ac9',1,'stm32f407xx_matlab.h']]], - ['i2c_5fsr1_5fadd10_134',['I2C_SR1_ADD10',['../group___peripheral___registers___bits___definition.html#ga6faaa55a1e48aa7c1f2b69669901445d',1,'stm32f407xx_matlab.h']]], - ['i2c_5fsr1_5fadd10_5fmsk_135',['I2C_SR1_ADD10_Msk',['../group___peripheral___registers___bits___definition.html#gabc01a4be991adeeffbdf18b5767ea30b',1,'stm32f407xx_matlab.h']]], - ['i2c_5fsr1_5fadd10_5fpos_136',['I2C_SR1_ADD10_Pos',['../group___peripheral___registers___bits___definition.html#ga57e3e98939884a675f561bd0133c73f7',1,'stm32f407xx_matlab.h']]], - ['i2c_5fsr1_5faddr_137',['I2C_SR1_ADDR',['../group___peripheral___registers___bits___definition.html#ga3db361a4d9dd84b187085a11d933b45d',1,'stm32f407xx_matlab.h']]], - ['i2c_5fsr1_5faddr_5fmsk_138',['I2C_SR1_ADDR_Msk',['../group___peripheral___registers___bits___definition.html#ga387882c1ac38b5af80a88ac6c5c8961f',1,'stm32f407xx_matlab.h']]], - ['i2c_5fsr1_5faddr_5fpos_139',['I2C_SR1_ADDR_Pos',['../group___peripheral___registers___bits___definition.html#ga4662fc1d4534a406d3e4e417dcaa29c1',1,'stm32f407xx_matlab.h']]], - ['i2c_5fsr1_5faf_140',['I2C_SR1_AF',['../group___peripheral___registers___bits___definition.html#ga62aa2496d4b3955214a16a7bd998fd88',1,'stm32f407xx_matlab.h']]], - ['i2c_5fsr1_5faf_5fmsk_141',['I2C_SR1_AF_Msk',['../group___peripheral___registers___bits___definition.html#gae64af2b76c8fc655547f07d0eda3c8d6',1,'stm32f407xx_matlab.h']]], - ['i2c_5fsr1_5faf_5fpos_142',['I2C_SR1_AF_Pos',['../group___peripheral___registers___bits___definition.html#gafb0a33028b96b10708bd881b21c17dae',1,'stm32f407xx_matlab.h']]], - ['i2c_5fsr1_5farlo_143',['I2C_SR1_ARLO',['../group___peripheral___registers___bits___definition.html#gacbc52f6ec6172c71d8b026a22c2f69d2',1,'stm32f407xx_matlab.h']]], - ['i2c_5fsr1_5farlo_5fmsk_144',['I2C_SR1_ARLO_Msk',['../group___peripheral___registers___bits___definition.html#ga7859c854cc27fefc075eb3a6d67410da',1,'stm32f407xx_matlab.h']]], - ['i2c_5fsr1_5farlo_5fpos_145',['I2C_SR1_ARLO_Pos',['../group___peripheral___registers___bits___definition.html#gafab03fd640b6661848addb3cd9d38519',1,'stm32f407xx_matlab.h']]], - ['i2c_5fsr1_5fberr_146',['I2C_SR1_BERR',['../group___peripheral___registers___bits___definition.html#ga1d12990c90ab0757dcfea150ea50b227',1,'stm32f407xx_matlab.h']]], - ['i2c_5fsr1_5fberr_5fmsk_147',['I2C_SR1_BERR_Msk',['../group___peripheral___registers___bits___definition.html#ga591f9c02dd6c1b393f295ddd9be5f28d',1,'stm32f407xx_matlab.h']]], - ['i2c_5fsr1_5fberr_5fpos_148',['I2C_SR1_BERR_Pos',['../group___peripheral___registers___bits___definition.html#ga0a1c615024c02d5ea5bcb3717ff6863d',1,'stm32f407xx_matlab.h']]], - ['i2c_5fsr1_5fbtf_149',['I2C_SR1_BTF',['../group___peripheral___registers___bits___definition.html#gafb279f85d78cfe5abd3eeb0b40a65ab1',1,'stm32f407xx_matlab.h']]], - ['i2c_5fsr1_5fbtf_5fmsk_150',['I2C_SR1_BTF_Msk',['../group___peripheral___registers___bits___definition.html#ga9da3a67ef386eb3c7fc5be2016a1f0b1',1,'stm32f407xx_matlab.h']]], - ['i2c_5fsr1_5fbtf_5fpos_151',['I2C_SR1_BTF_Pos',['../group___peripheral___registers___bits___definition.html#ga3c662220a2fc8d437b929ac360b7b6d3',1,'stm32f407xx_matlab.h']]], - ['i2c_5fsr1_5fovr_152',['I2C_SR1_OVR',['../group___peripheral___registers___bits___definition.html#gad42d2435d2e64bf710c701c9b17adfb4',1,'stm32f407xx_matlab.h']]], - ['i2c_5fsr1_5fovr_5fmsk_153',['I2C_SR1_OVR_Msk',['../group___peripheral___registers___bits___definition.html#gaeca6c423a2a9d7495c35517b3cc9a9b8',1,'stm32f407xx_matlab.h']]], - ['i2c_5fsr1_5fovr_5fpos_154',['I2C_SR1_OVR_Pos',['../group___peripheral___registers___bits___definition.html#ga628a0e0ea5fa7dd31b68d2bac80b8b20',1,'stm32f407xx_matlab.h']]], - ['i2c_5fsr1_5fpecerr_155',['I2C_SR1_PECERR',['../group___peripheral___registers___bits___definition.html#ga4b2976279024e832e53ad12796a7bb71',1,'stm32f407xx_matlab.h']]], - ['i2c_5fsr1_5fpecerr_5fmsk_156',['I2C_SR1_PECERR_Msk',['../group___peripheral___registers___bits___definition.html#gaafd640f94fa388e27d4747c5eb8fc938',1,'stm32f407xx_matlab.h']]], - ['i2c_5fsr1_5fpecerr_5fpos_157',['I2C_SR1_PECERR_Pos',['../group___peripheral___registers___bits___definition.html#ga1f1e78360bc478a00ca5c8176dcd0b22',1,'stm32f407xx_matlab.h']]], - ['i2c_5fsr1_5frxne_158',['I2C_SR1_RXNE',['../group___peripheral___registers___bits___definition.html#gaf6ebe33c992611bc2e25bbb01c1441a5',1,'stm32f407xx_matlab.h']]], - ['i2c_5fsr1_5frxne_5fmsk_159',['I2C_SR1_RXNE_Msk',['../group___peripheral___registers___bits___definition.html#gacf56d0f5cc9b333a2d287baf96e1ca62',1,'stm32f407xx_matlab.h']]], - ['i2c_5fsr1_5frxne_5fpos_160',['I2C_SR1_RXNE_Pos',['../group___peripheral___registers___bits___definition.html#ga380b3695a5b03ae70e411ba048a04e49',1,'stm32f407xx_matlab.h']]], - ['i2c_5fsr1_5fsb_161',['I2C_SR1_SB',['../group___peripheral___registers___bits___definition.html#ga6935c920da59d755d0cf834548a70ec4',1,'stm32f407xx_matlab.h']]], - ['i2c_5fsr1_5fsb_5fmsk_162',['I2C_SR1_SB_Msk',['../group___peripheral___registers___bits___definition.html#gab9d2227f20b51eda4af2fb9e9dd4f6df',1,'stm32f407xx_matlab.h']]], - ['i2c_5fsr1_5fsb_5fpos_163',['I2C_SR1_SB_Pos',['../group___peripheral___registers___bits___definition.html#ga67ed7d8c3e9dc642c2c70c834aeec6ea',1,'stm32f407xx_matlab.h']]], - ['i2c_5fsr1_5fsmbalert_164',['I2C_SR1_SMBALERT',['../group___peripheral___registers___bits___definition.html#ga8df36c38deb8791d0ac3cb5881298c1c',1,'stm32f407xx_matlab.h']]], - ['i2c_5fsr1_5fsmbalert_5fmsk_165',['I2C_SR1_SMBALERT_Msk',['../group___peripheral___registers___bits___definition.html#ga617464b325a3649c9a36ad80386558b6',1,'stm32f407xx_matlab.h']]], - ['i2c_5fsr1_5fsmbalert_5fpos_166',['I2C_SR1_SMBALERT_Pos',['../group___peripheral___registers___bits___definition.html#gad0c047e24fefb89f3928b37b7695aa55',1,'stm32f407xx_matlab.h']]], - ['i2c_5fsr1_5fstopf_167',['I2C_SR1_STOPF',['../group___peripheral___registers___bits___definition.html#gaafcea4cdbe2f6da31566c897fa893a7c',1,'stm32f407xx_matlab.h']]], - ['i2c_5fsr1_5fstopf_5fmsk_168',['I2C_SR1_STOPF_Msk',['../group___peripheral___registers___bits___definition.html#gad1679ebac13f8ad5aad54acd446f70e4',1,'stm32f407xx_matlab.h']]], - ['i2c_5fsr1_5fstopf_5fpos_169',['I2C_SR1_STOPF_Pos',['../group___peripheral___registers___bits___definition.html#ga508dc538aee33bf854cfbe3b7f4a7ba9',1,'stm32f407xx_matlab.h']]], - ['i2c_5fsr1_5ftimeout_170',['I2C_SR1_TIMEOUT',['../group___peripheral___registers___bits___definition.html#gaef3a1e4921d7c509d1b639c67882c4c9',1,'stm32f407xx_matlab.h']]], - ['i2c_5fsr1_5ftimeout_5fmsk_171',['I2C_SR1_TIMEOUT_Msk',['../group___peripheral___registers___bits___definition.html#ga7c0209188a2791eddad0c143ac7f9416',1,'stm32f407xx_matlab.h']]], - ['i2c_5fsr1_5ftimeout_5fpos_172',['I2C_SR1_TIMEOUT_Pos',['../group___peripheral___registers___bits___definition.html#ga80a7d5a7ab0b5eb4bbbcf59d64e9e58e',1,'stm32f407xx_matlab.h']]], - ['i2c_5fsr1_5ftxe_173',['I2C_SR1_TXE',['../group___peripheral___registers___bits___definition.html#gafdc4da49c163910203255e384591b6f7',1,'stm32f407xx_matlab.h']]], - ['i2c_5fsr1_5ftxe_5fmsk_174',['I2C_SR1_TXE_Msk',['../group___peripheral___registers___bits___definition.html#ga835a04e1e2c43a4462b9b5cd04b2b4ea',1,'stm32f407xx_matlab.h']]], - ['i2c_5fsr1_5ftxe_5fpos_175',['I2C_SR1_TXE_Pos',['../group___peripheral___registers___bits___definition.html#gabdceff8db6df40c017f96a5e606ea884',1,'stm32f407xx_matlab.h']]], - ['i2c_5fsr2_5fbusy_176',['I2C_SR2_BUSY',['../group___peripheral___registers___bits___definition.html#ga3b1e75a82da73ae2873cff1cd27c3179',1,'stm32f407xx_matlab.h']]], - ['i2c_5fsr2_5fbusy_5fmsk_177',['I2C_SR2_BUSY_Msk',['../group___peripheral___registers___bits___definition.html#ga43693f4a5b2f232a145eee42f26a1110',1,'stm32f407xx_matlab.h']]], - ['i2c_5fsr2_5fbusy_5fpos_178',['I2C_SR2_BUSY_Pos',['../group___peripheral___registers___bits___definition.html#gaa9b4a60a8e919cfe14e222976859b1cd',1,'stm32f407xx_matlab.h']]], - ['i2c_5fsr2_5fdualf_179',['I2C_SR2_DUALF',['../group___peripheral___registers___bits___definition.html#ga79a6a21835e06d9bc48009f4269b7798',1,'stm32f407xx_matlab.h']]], - ['i2c_5fsr2_5fdualf_5fmsk_180',['I2C_SR2_DUALF_Msk',['../group___peripheral___registers___bits___definition.html#ga338ddbff50ca2b01dacc4b8e93014f30',1,'stm32f407xx_matlab.h']]], - ['i2c_5fsr2_5fdualf_5fpos_181',['I2C_SR2_DUALF_Pos',['../group___peripheral___registers___bits___definition.html#ga546ae463133d2c719996689e24e61e1f',1,'stm32f407xx_matlab.h']]], - ['i2c_5fsr2_5fgencall_182',['I2C_SR2_GENCALL',['../group___peripheral___registers___bits___definition.html#gaf3aeb79cbe04f7ec1e3c2615921c4fab',1,'stm32f407xx_matlab.h']]], - ['i2c_5fsr2_5fgencall_5fmsk_183',['I2C_SR2_GENCALL_Msk',['../group___peripheral___registers___bits___definition.html#gada42e3c3d8e62bfab1117a382def5383',1,'stm32f407xx_matlab.h']]], - ['i2c_5fsr2_5fgencall_5fpos_184',['I2C_SR2_GENCALL_Pos',['../group___peripheral___registers___bits___definition.html#ga26e3032167b56ec310c7b81945dc76a4',1,'stm32f407xx_matlab.h']]], - ['i2c_5fsr2_5fmsl_185',['I2C_SR2_MSL',['../group___peripheral___registers___bits___definition.html#ga75cc361adf0e72e33d6771ebfa17b52d',1,'stm32f407xx_matlab.h']]], - ['i2c_5fsr2_5fmsl_5fmsk_186',['I2C_SR2_MSL_Msk',['../group___peripheral___registers___bits___definition.html#gad723df35fcda84431aefaace405b62b2',1,'stm32f407xx_matlab.h']]], - ['i2c_5fsr2_5fmsl_5fpos_187',['I2C_SR2_MSL_Pos',['../group___peripheral___registers___bits___definition.html#gada5253dbcd3c7d67d0fad31d938f4b5b',1,'stm32f407xx_matlab.h']]], - ['i2c_5fsr2_5fpec_188',['I2C_SR2_PEC',['../group___peripheral___registers___bits___definition.html#ga4a4fd5d9c9e2593be920d19a5f6ae732',1,'stm32f407xx_matlab.h']]], - ['i2c_5fsr2_5fpec_5fmsk_189',['I2C_SR2_PEC_Msk',['../group___peripheral___registers___bits___definition.html#ga5a9dceb742f98aa0f27e5ae8dc427a88',1,'stm32f407xx_matlab.h']]], - ['i2c_5fsr2_5fpec_5fpos_190',['I2C_SR2_PEC_Pos',['../group___peripheral___registers___bits___definition.html#ga332f5e12ed830e7d99b241549220a3c0',1,'stm32f407xx_matlab.h']]], - ['i2c_5fsr2_5fsmbdefault_191',['I2C_SR2_SMBDEFAULT',['../group___peripheral___registers___bits___definition.html#gafcf50334903013177a8c6f4e36b8d6fe',1,'stm32f407xx_matlab.h']]], - ['i2c_5fsr2_5fsmbdefault_5fmsk_192',['I2C_SR2_SMBDEFAULT_Msk',['../group___peripheral___registers___bits___definition.html#gaa390034d42a7873287b68e9ae3935a26',1,'stm32f407xx_matlab.h']]], - ['i2c_5fsr2_5fsmbdefault_5fpos_193',['I2C_SR2_SMBDEFAULT_Pos',['../group___peripheral___registers___bits___definition.html#gaf4be26fe6702a976b50628c3df1b352c',1,'stm32f407xx_matlab.h']]], - ['i2c_5fsr2_5fsmbhost_194',['I2C_SR2_SMBHOST',['../group___peripheral___registers___bits___definition.html#gaa07cf3e404f9f57e98d1ba3793079c80',1,'stm32f407xx_matlab.h']]], - ['i2c_5fsr2_5fsmbhost_5fmsk_195',['I2C_SR2_SMBHOST_Msk',['../group___peripheral___registers___bits___definition.html#ga6bd5daae1a83a7a62584be9f601ec52d',1,'stm32f407xx_matlab.h']]], - ['i2c_5fsr2_5fsmbhost_5fpos_196',['I2C_SR2_SMBHOST_Pos',['../group___peripheral___registers___bits___definition.html#gab3da82932b239f193ac2f57f87c3b1f0',1,'stm32f407xx_matlab.h']]], - ['i2c_5fsr2_5ftra_197',['I2C_SR2_TRA',['../group___peripheral___registers___bits___definition.html#ga288b20416b42a79e591aa80d9a690fca',1,'stm32f407xx_matlab.h']]], - ['i2c_5fsr2_5ftra_5fmsk_198',['I2C_SR2_TRA_Msk',['../group___peripheral___registers___bits___definition.html#ga260f5bfa56cd55a6e25ae1585fc1381e',1,'stm32f407xx_matlab.h']]], - ['i2c_5fsr2_5ftra_5fpos_199',['I2C_SR2_TRA_Pos',['../group___peripheral___registers___bits___definition.html#ga91e4b3f7e5bff2ea65eefeadbc0a2e2a',1,'stm32f407xx_matlab.h']]], - ['i2c_5ftrise_5ftrise_200',['I2C_TRISE_TRISE',['../group___peripheral___registers___bits___definition.html#gaff77a39aba630647af62dc7f1a5dc218',1,'stm32f407xx_matlab.h']]], - ['i2c_5ftrise_5ftrise_5fmsk_201',['I2C_TRISE_TRISE_Msk',['../group___peripheral___registers___bits___definition.html#ga8a3152b3f16c453126cc1cef41b765fe',1,'stm32f407xx_matlab.h']]], - ['i2c_5ftrise_5ftrise_5fpos_202',['I2C_TRISE_TRISE_Pos',['../group___peripheral___registers___bits___definition.html#gafb08ecb9599f81e5112a25142cb0e98f',1,'stm32f407xx_matlab.h']]], - ['i2c_5ftypedef_203',['I2C_TypeDef',['../struct_i2_c___type_def.html',1,'']]], - ['i2s2ext_204',['i2s2ext',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga06974a33ee50f86662415a0c4af114a8',1,'stm32f4xx_periph_registers.c']]], - ['i2s2ext_205',['I2S2ext',['../group___peripheral__declaration.html#ga9efe6de71871a01dd38abcb229f30c02',1,'stm32f407xx_matlab.h']]], - ['i2s2ext_5fbase_206',['I2S2ext_BASE',['../group___peripheral__memory__map.html#gaa5f7b241ed5b756decd835300c9e7bc9',1,'stm32f407xx_matlab.h']]], - ['i2s3ext_207',['I2S3ext',['../group___peripheral__declaration.html#ga15b3a03302ed53911099c5216da0b1cf',1,'stm32f407xx_matlab.h']]], - ['i2s3ext_208',['i2s3ext',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#gadc6636f1a31d3d480e01c46ffa6edddf',1,'stm32f4xx_periph_registers.c']]], - ['i2s3ext_5fbase_209',['I2S3ext_BASE',['../group___peripheral__memory__map.html#ga89b61d6e6b09e94f3fccb7bef34e0263',1,'stm32f407xx_matlab.h']]], - ['i2scfgr_210',['I2SCFGR',['../group___c_m_s_i_s___device.html#gaa0c41c8883cb0812d6aaf956c393584b',1,'SPI_TypeDef']]], - ['i2spr_211',['I2SPR',['../group___c_m_s_i_s___device.html#gab9be89a916ee5904381e10da10e5e8e9',1,'SPI_TypeDef']]], - ['iabr_212',['IABR',['../group___c_m_s_i_s__core___debug_functions.html#gad74aec367b7c2af1128d02d6bec57645',1,'NVIC_Type']]], - ['icer_213',['ICER',['../group___c_m_s_i_s__core___debug_functions.html#ga580236ad654b5446de777acbc55b68bc',1,'NVIC_Type']]], - ['ici_5fit_5f1_214',['ICI_IT_1',['../group___c_m_s_i_s__core___debug_functions.html#gabedfacab5e6f9c329bfa0051cb88a9d3',1,'xPSR_Type::ICI_IT_1'],['../group___c_m_s_i_s__core___debug_functions.html#gabedfacab5e6f9c329bfa0051cb88a9d3',1,'xPSR_Type::@2::ICI_IT_1']]], - ['ici_5fit_5f2_215',['ICI_IT_2',['../group___c_m_s_i_s__core___debug_functions.html#gae1df616880ca701154eba05e747605df',1,'xPSR_Type::ICI_IT_2'],['../group___c_m_s_i_s__core___debug_functions.html#gae1df616880ca701154eba05e747605df',1,'xPSR_Type::@2::ICI_IT_2']]], - ['icpr_216',['ICPR',['../group___c_m_s_i_s__core___debug_functions.html#ga1bef4ff3b0b2626aba9f916808d6477e',1,'NVIC_Type']]], - ['icr_217',['ICR',['../group___c_m_s_i_s___device.html#ga0a8c8230846fd8ff154b9fde8dfa0399',1,'DCMI_TypeDef::ICR'],['../group___c_m_s_i_s___device.html#ga0a8c8230846fd8ff154b9fde8dfa0399',1,'SDIO_TypeDef::ICR']]], - ['icsr_218',['ICSR',['../group___c_m_s_i_s__core___debug_functions.html#gaced895d6aba03d72b0d865fcc5ce44ee',1,'SCB_Type']]], - ['ictr_219',['ICTR',['../group___c_m_s_i_s__core___debug_functions.html#gacf9b76331abd768af25a10b3625da4b4',1,'SCnSCB_Type']]], - ['idcode_220',['IDCODE',['../group___c_m_s_i_s___device.html#ga24df28d0e440321b21f6f07b3bb93dea',1,'DBGMCU_TypeDef']]], - ['idmcuthread_221',['idMCUThread',['../struct_s_i_m_____m_c_u_handle_type_def.html#a52fe34944579ff4b1b6d3e85fae96546',1,'SIM__MCUHandleTypeDef']]], - ['idr_222',['IDR',['../group___c_m_s_i_s___device.html#ga601d7b0ba761c987db359b2d7173b7e0',1,'CRC_TypeDef::IDR'],['../group___c_m_s_i_s___device.html#ga328d2fe9ef1d513c3a97d30f98f0047c',1,'GPIO_TypeDef::IDR']]], - ['ier_223',['IER',['../group___c_m_s_i_s___device.html#ga6566f8cfbd1d8aa7e8db046aa35e77db',1,'CAN_TypeDef::IER'],['../group___c_m_s_i_s___device.html#ga6566f8cfbd1d8aa7e8db046aa35e77db',1,'DCMI_TypeDef::IER']]], - ['imcr_224',['IMCR',['../group___c_m_s_i_s__core___debug_functions.html#gaf0446ee5dcb6082dc8bba9adcc8ec812',1,'ITM_Type']]], - ['imr_225',['IMR',['../group___c_m_s_i_s___device.html#gae845b86e973b4bf8a33c447c261633f6',1,'EXTI_TypeDef']]], - ['in_20scb_20scnscb_226',['System Controls not in SCB (SCnSCB)',['../group___c_m_s_i_s___s_cn_s_c_b.html',1,'']]], - ['in_5fport_5fnumb_227',['IN_PORT_NUMB',['../group___w_r_a_p_p_e_r___c_o_n_f.html#ga25be09b98d138ff8c740bece06e1bcc6',1,'mcu_wrapper_conf.h']]], - ['in_5fport_5fwidth_228',['IN_PORT_WIDTH',['../group___w_r_a_p_p_e_r___c_o_n_f.html#gac41471250c3d92da182a969e378addfc',1,'mcu_wrapper_conf.h']]], - ['init_5ftim_5fsim_229',['Init_TIM_SIM',['../group___m_a_i_n___s_i_m_u_l_a_t_o_r.html#ga617bc2e624bea041e844a0ac0c6a50f9',1,'Init_TIM_SIM(void): stm32f4xx_matlab_conf.c'],['../group___m_a_i_n___s_i_m_u_l_a_t_o_r.html#ga617bc2e624bea041e844a0ac0c6a50f9',1,'Init_TIM_SIM(void): stm32f4xx_matlab_conf.c']]], - ['initialize_5fperiph_5fsim_230',['Initialize_Periph_Sim',['../group___m_a_i_n___s_i_m_u_l_a_t_o_r.html#gab020a77f89d6c0ea99c7559cfa7e3ba0',1,'Initialize_Periph_Sim(void): stm32f4xx_matlab_conf.c'],['../group___m_a_i_n___s_i_m_u_l_a_t_o_r.html#gab020a77f89d6c0ea99c7559cfa7e3ba0',1,'Initialize_Periph_Sim(void): stm32f4xx_matlab_conf.c']]], - ['instructions_20reference_231',['Functions and Instructions Reference',['../group___c_m_s_i_s___core___function_interface.html',1,'']]], - ['instrumentation_20trace_20macrocell_20itm_232',['Instrumentation Trace Macrocell (ITM)',['../group___c_m_s_i_s___i_t_m.html',1,'']]], - ['int16_5fc_233',['INT16_C',['../stdint_8h.html#a838b261fec725cb0f5d5b6769d3521e7',1,'stdint.h']]], - ['int16_5fmax_234',['INT16_MAX',['../stdint_8h.html#ac58f2c111cc9989c86db2a7dc4fd84ca',1,'stdint.h']]], - ['int16_5fmin_235',['INT16_MIN',['../stdint_8h.html#ad4e9955955b27624963643eac448118a',1,'stdint.h']]], - ['int16_5ft_236',['int16_t',['../stdint_8h.html#aa5ad9bec438b7cf669efb1ca064e79f5',1,'stdint.h']]], - ['int32_5fc_237',['INT32_C',['../stdint_8h.html#ad78650fb7726f4e99205406569ef403d',1,'stdint.h']]], - ['int32_5fmax_238',['INT32_MAX',['../stdint_8h.html#a181807730d4a375f848ba139813ce04f',1,'stdint.h']]], - ['int32_5fmin_239',['INT32_MIN',['../stdint_8h.html#a688eb21a22db27c2b2bd5836943cdcbe',1,'stdint.h']]], - ['int32_5ft_240',['int32_t',['../stdint_8h.html#ab1967d8591af1a4e48c37fd2b0f184d0',1,'stdint.h']]], - ['int64_5fc_241',['INT64_C',['../stdint_8h.html#a93d102802b35d3b8abae9bbe7f0fed75',1,'stdint.h']]], - ['int64_5fmax_242',['INT64_MAX',['../stdint_8h.html#ad0d744f05898e32d01f73f8af3cd2071',1,'stdint.h']]], - ['int64_5fmin_243',['INT64_MIN',['../stdint_8h.html#ab21f12f372f67b8ff0aa3432336ede67',1,'stdint.h']]], - ['int64_5ft_244',['int64_t',['../stdint_8h.html#a0c9423d16eef222e84c3690e1254d4fc',1,'stdint.h']]], - ['int8_5fc_245',['INT8_C',['../stdint_8h.html#a1eaa7db37089dcdfb60227725c9c1585',1,'stdint.h']]], - ['int8_5fmax_246',['INT8_MAX',['../stdint_8h.html#aaf7f29f45f1a513b4748a4e5014ddf6a',1,'stdint.h']]], - ['int8_5fmin_247',['INT8_MIN',['../stdint_8h.html#aadcf2a81af243df333b31efa6461ab8e',1,'stdint.h']]], - ['int8_5ft_248',['int8_t',['../stdint_8h.html#aef44329758059c91c76d334e8fc09700',1,'stdint.h']]], - ['int_5ffast16_5fmax_249',['INT_FAST16_MAX',['../stdint_8h.html#a2fd35d0ea091e04caec504ff0042cf00',1,'stdint.h']]], - ['int_5ffast16_5fmin_250',['INT_FAST16_MIN',['../stdint_8h.html#a169460a4e2a79138723d68d99372d958',1,'stdint.h']]], - ['int_5ffast16_5ft_251',['int_fast16_t',['../stdint_8h.html#a89a76a94f66a28fb25fa1548b05297bf',1,'stdint.h']]], - ['int_5ffast32_5fmax_252',['INT_FAST32_MAX',['../stdint_8h.html#ac96fa0f41b19e89f109e4f9913ca6635',1,'stdint.h']]], - ['int_5ffast32_5fmin_253',['INT_FAST32_MIN',['../stdint_8h.html#ad93df1652ed0635513d5efe4f1219926',1,'stdint.h']]], - ['int_5ffast32_5ft_254',['int_fast32_t',['../stdint_8h.html#ae884dda22bf64c7e974894a6d3b67929',1,'stdint.h']]], - ['int_5ffast64_5fmax_255',['INT_FAST64_MAX',['../stdint_8h.html#a13c95cf9c209d8daacb36cbf0d5ba275',1,'stdint.h']]], - ['int_5ffast64_5fmin_256',['INT_FAST64_MIN',['../stdint_8h.html#a50f0fdcb00ea2500cec0f3d6d45c36f3',1,'stdint.h']]], - ['int_5ffast64_5ft_257',['int_fast64_t',['../stdint_8h.html#a1ea692df2dbaf0e6fd4d04e505b56dd9',1,'stdint.h']]], - ['int_5ffast8_5fmax_258',['INT_FAST8_MAX',['../stdint_8h.html#acbcdb3bee0f5f904da5df8de69a80ca3',1,'stdint.h']]], - ['int_5ffast8_5fmin_259',['INT_FAST8_MIN',['../stdint_8h.html#aad8fb982cb19143efd5ee9a1a7a89390',1,'stdint.h']]], - ['int_5ffast8_5ft_260',['int_fast8_t',['../stdint_8h.html#a3ea64e25c86718ee706162b247d8c424',1,'stdint.h']]], - ['int_5fleast16_5fmax_261',['INT_LEAST16_MAX',['../stdint_8h.html#a7eb2a8e2a1c65d6c9ad0f86154890baa',1,'stdint.h']]], - ['int_5fleast16_5fmin_262',['INT_LEAST16_MIN',['../stdint_8h.html#a1f91bfd5820c2f27af3d260fc75813e1',1,'stdint.h']]], - ['int_5fleast16_5ft_263',['int_least16_t',['../stdint_8h.html#ad05f554db4d3cb2fe5ca66f316bc9452',1,'stdint.h']]], - ['int_5fleast32_5fmax_264',['INT_LEAST32_MAX',['../stdint_8h.html#a5618711a0a54f722190a3a1219e278c2',1,'stdint.h']]], - ['int_5fleast32_5fmin_265',['INT_LEAST32_MIN',['../stdint_8h.html#a2360a536116dd734820a6b5b3d560ce7',1,'stdint.h']]], - ['int_5fleast32_5ft_266',['int_least32_t',['../stdint_8h.html#a1ef09861eb7bed037170ba0025f664bf',1,'stdint.h']]], - ['int_5fleast64_5fmax_267',['INT_LEAST64_MAX',['../stdint_8h.html#a35d0f98a2e507fd1be779d49da92724e',1,'stdint.h']]], - ['int_5fleast64_5fmin_268',['INT_LEAST64_MIN',['../stdint_8h.html#ac12b4f6966b57ad82feb683b284b4060',1,'stdint.h']]], - ['int_5fleast64_5ft_269',['int_least64_t',['../stdint_8h.html#aa84e4a614844da82f79a3ef8ba848c89',1,'stdint.h']]], - ['int_5fleast8_5fmax_270',['INT_LEAST8_MAX',['../stdint_8h.html#aa05109908fb2770f632d2b646b9f85bf',1,'stdint.h']]], - ['int_5fleast8_5fmin_271',['INT_LEAST8_MIN',['../stdint_8h.html#a3e986cad833f63f420962ff60eda87e5',1,'stdint.h']]], - ['int_5fleast8_5ft_272',['int_least8_t',['../stdint_8h.html#ae04fa5ea5ad475bfe428842a986fbf28',1,'stdint.h']]], - ['interface_20tpi_273',['Trace Port Interface (TPI)',['../group___c_m_s_i_s___t_p_i.html',1,'']]], - ['interrupt_20controller_20nvic_274',['Nested Vectored Interrupt Controller (NVIC)',['../group___c_m_s_i_s___n_v_i_c.html',1,'']]], - ['intmax_5fc_275',['INTMAX_C',['../stdint_8h.html#a846429736de0233f6ecddedb21424ddd',1,'stdint.h']]], - ['intmax_5fmax_276',['INTMAX_MAX',['../stdint_8h.html#a022b9b0a3564d786244a4631847c37a3',1,'stdint.h']]], - ['intmax_5fmin_277',['INTMAX_MIN',['../stdint_8h.html#a2b0a3edfc672154f606dc3ad26277b61',1,'stdint.h']]], - ['intmax_5ft_278',['intmax_t',['../stdint_8h.html#ad5fc31e4f9356d76775e1e619d2e0286',1,'stdint.h']]], - ['intptr_5fmax_279',['INTPTR_MAX',['../stdint_8h.html#a9e5742f2bae4a5283431a3c03499e3a9',1,'stdint.h']]], - ['intptr_5fmin_280',['INTPTR_MIN',['../stdint_8h.html#a2aaa6d3aa1d7d1e0e326955aa24db752',1,'stdint.h']]], - ['intptr_5ft_281',['intptr_t',['../stdint_8h.html#aaadb3b51e475a79bc209cfbdb4d6e579',1,'stdint.h']]], - ['ip_282',['IP',['../group___c_m_s_i_s__core___debug_functions.html#ga4fda947a8fd3237a89d43b7d5a1057cb',1,'NVIC_Type']]], - ['ipsr_5fisr_5fmsk_283',['IPSR_ISR_Msk',['../group___c_m_s_i_s___c_o_r_e.html#gaf013a4579a64d1f21f56ea9f1b33ab56',1,'core_cm4_matlab.h']]], - ['ipsr_5fisr_5fpos_284',['IPSR_ISR_Pos',['../group___c_m_s_i_s___c_o_r_e.html#ga0e34027584d02c43811ae908a5ca9adf',1,'core_cm4_matlab.h']]], - ['ipsr_5ftype_285',['IPSR_Type',['../union_i_p_s_r___type.html',1,'']]], - ['irqn_5ftype_286',['IRQn_Type',['../group___peripheral__interrupt__number__definition.html#ga7e1129cd8a196f4284d41db3e82ad5c8',1,'stm32f407xx_matlab.h']]], - ['irr_287',['IRR',['../group___c_m_s_i_s__core___debug_functions.html#gae300b6ee4d883ceec8f3572fc0fc3d69',1,'ITM_Type']]], - ['is_5fadc_5fall_5finstance_288',['IS_ADC_ALL_INSTANCE',['../group___exported__macros.html#ga2204b62b378bcf08b3b9006c184c7c23',1,'stm32f407xx_matlab.h']]], - ['is_5fadc_5fcommon_5finstance_289',['IS_ADC_COMMON_INSTANCE',['../group___exported__macros.html#gad8a5831c786b6b265531b890a194cbe2',1,'stm32f407xx_matlab.h']]], - ['is_5fadc_5fmultimode_5fmaster_5finstance_290',['IS_ADC_MULTIMODE_MASTER_INSTANCE',['../group___exported__macros.html#ga26b4e299ac54d09082645a70f889c143',1,'stm32f407xx_matlab.h']]], - ['is_5fcan_5fall_5finstance_291',['IS_CAN_ALL_INSTANCE',['../group___exported__macros.html#ga974dd363bcb2a5f48ec032509fd4ece3',1,'stm32f407xx_matlab.h']]], - ['is_5fcrc_5fall_5finstance_292',['IS_CRC_ALL_INSTANCE',['../group___exported__macros.html#gaa514941a7f02f65eb27450c05e4e8dd1',1,'stm32f407xx_matlab.h']]], - ['is_5fdac_5fall_5finstance_293',['IS_DAC_ALL_INSTANCE',['../group___exported__macros.html#ga94426b97cc5f1644d67f291cbcdba6d8',1,'stm32f407xx_matlab.h']]], - ['is_5fdcmi_5fall_5finstance_294',['IS_DCMI_ALL_INSTANCE',['../group___exported__macros.html#gaca27f42a2f7dd5715c74884bd9af310d',1,'stm32f407xx_matlab.h']]], - ['is_5fdma_5fstream_5fall_5finstance_295',['IS_DMA_STREAM_ALL_INSTANCE',['../group___exported__macros.html#gafd60def465da605e33644e28072aee9c',1,'stm32f407xx_matlab.h']]], - ['is_5ffunctional_5fstate_296',['IS_FUNCTIONAL_STATE',['../group___exported__types.html#gaffaf7c3f537d7a3370b1bbdda67a2bf6',1,'stm32f4xx.h']]], - ['is_5fgpio_5fall_5finstance_297',['IS_GPIO_ALL_INSTANCE',['../group___exported__macros.html#ga783626dd2431afebea836a102e318957',1,'stm32f407xx_matlab.h']]], - ['is_5fhcd_5fall_5finstance_298',['IS_HCD_ALL_INSTANCE',['../group___exported__macros.html#ga6696ebd1aea007a19e831517f3e1f497',1,'stm32f407xx_matlab.h']]], - ['is_5fi2c_5fall_5finstance_299',['IS_I2C_ALL_INSTANCE',['../group___exported__macros.html#gacdf0149a4e8c41a6814c13613c38a6b2',1,'stm32f407xx_matlab.h']]], - ['is_5fi2s_5fall_5finstance_300',['IS_I2S_ALL_INSTANCE',['../group___exported__macros.html#ga0b35685911e3c7a38ee89e5cdc5a82fa',1,'stm32f407xx_matlab.h']]], - ['is_5fi2s_5fall_5finstance_5fext_301',['IS_I2S_ALL_INSTANCE_EXT',['../group___exported__macros.html#ga839b019f23ec240da66dd50a21ab5025',1,'stm32f407xx_matlab.h']]], - ['is_5fi2s_5fext_5fall_5finstance_302',['IS_I2S_EXT_ALL_INSTANCE',['../group___exported__macros.html#ga2f0d621c72fe4e5039562472460e29ab',1,'stm32f407xx_matlab.h']]], - ['is_5firda_5finstance_303',['IS_IRDA_INSTANCE',['../group___exported__macros.html#ga98ae6698dc54d8441fce553a65bf5429',1,'stm32f407xx_matlab.h']]], - ['is_5fiwdg_5fall_5finstance_304',['IS_IWDG_ALL_INSTANCE',['../group___exported__macros.html#gad9ec4c52f0572ee67d043e006f1d5e39',1,'stm32f407xx_matlab.h']]], - ['is_5fpcd_5fall_5finstance_305',['IS_PCD_ALL_INSTANCE',['../group___exported__macros.html#gadaf663c55446f04fa69ee912b8890b32',1,'stm32f407xx_matlab.h']]], - ['is_5frng_5fall_5finstance_306',['IS_RNG_ALL_INSTANCE',['../group___exported__macros.html#ga7369db258c1b8931b427262d0673751f',1,'stm32f407xx_matlab.h']]], - ['is_5frtc_5fall_5finstance_307',['IS_RTC_ALL_INSTANCE',['../group___exported__macros.html#gab4230e8bd4d88adc4250f041d67375ce',1,'stm32f407xx_matlab.h']]], - ['is_5fsdio_5fall_5finstance_308',['IS_SDIO_ALL_INSTANCE',['../group___exported__macros.html#ga73932cb2c83be6be1884d3cba2fc0063',1,'stm32f407xx_matlab.h']]], - ['is_5fsmartcard_5finstance_309',['IS_SMARTCARD_INSTANCE',['../group___exported__macros.html#gab2734c105403831749ccb34eeb058988',1,'stm32f407xx_matlab.h']]], - ['is_5fsmbus_5fall_5finstance_310',['IS_SMBUS_ALL_INSTANCE',['../group___exported__macros.html#ga85b79d63f4643c0de9a7519290a0eceb',1,'stm32f407xx_matlab.h']]], - ['is_5fspi_5fall_5finstance_311',['IS_SPI_ALL_INSTANCE',['../group___exported__macros.html#ga59c7619a86c03df3ebeb4bd8aaef982c',1,'stm32f407xx_matlab.h']]], - ['is_5ftim_5f32b_5fcounter_5finstance_312',['IS_TIM_32B_COUNTER_INSTANCE',['../group___exported__macros.html#gac41867bf288927ff8ff10a85e67a591b',1,'stm32f407xx_matlab.h']]], - ['is_5ftim_5fadvanced_5finstance_313',['IS_TIM_ADVANCED_INSTANCE',['../group___exported__macros.html#ga7e85353dbe9dc9d80ad06f0b935c12e1',1,'stm32f407xx_matlab.h']]], - ['is_5ftim_5fbreak_5finstance_314',['IS_TIM_BREAK_INSTANCE',['../group___exported__macros.html#ga68b8d9ca22720c9034753c604d83500d',1,'stm32f407xx_matlab.h']]], - ['is_5ftim_5fcc1_5finstance_315',['IS_TIM_CC1_INSTANCE',['../group___exported__macros.html#ga0c02efc77b1bfb640d7f6593f58ad464',1,'stm32f407xx_matlab.h']]], - ['is_5ftim_5fcc2_5finstance_316',['IS_TIM_CC2_INSTANCE',['../group___exported__macros.html#ga6ef84d278cf917c7e420b94687b39c7c',1,'stm32f407xx_matlab.h']]], - ['is_5ftim_5fcc3_5finstance_317',['IS_TIM_CC3_INSTANCE',['../group___exported__macros.html#ga0c37cb8f925fd43622cce7a4c00fd95e',1,'stm32f407xx_matlab.h']]], - ['is_5ftim_5fcc4_5finstance_318',['IS_TIM_CC4_INSTANCE',['../group___exported__macros.html#gae72b7182a73d81c33196265b31091c07',1,'stm32f407xx_matlab.h']]], - ['is_5ftim_5fccdma_5finstance_319',['IS_TIM_CCDMA_INSTANCE',['../group___exported__macros.html#ga8111ef18a809cd882ef327399fdbfc8f',1,'stm32f407xx_matlab.h']]], - ['is_5ftim_5fccx_5finstance_320',['IS_TIM_CCX_INSTANCE',['../group___exported__macros.html#ga6517a51ea79512a42bc53c718a77f18e',1,'stm32f407xx_matlab.h']]], - ['is_5ftim_5fccxn_5finstance_321',['IS_TIM_CCXN_INSTANCE',['../group___exported__macros.html#ga7181cfd1649c4e65e24b7c863e94a54f',1,'stm32f407xx_matlab.h']]], - ['is_5ftim_5fclock_5fdivision_5finstance_322',['IS_TIM_CLOCK_DIVISION_INSTANCE',['../group___exported__macros.html#gac54b9f42e8ab07c41abe7d96d13d698a',1,'stm32f407xx_matlab.h']]], - ['is_5ftim_5fclocksource_5fetrmode1_5finstance_323',['IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE',['../group___exported__macros.html#ga0ca20886f56bf7611ad511433b9caade',1,'stm32f407xx_matlab.h']]], - ['is_5ftim_5fclocksource_5fetrmode2_5finstance_324',['IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE',['../group___exported__macros.html#ga7beb8f84094e6a1567d10177cc4fdae9',1,'stm32f407xx_matlab.h']]], - ['is_5ftim_5fclocksource_5fitrx_5finstance_325',['IS_TIM_CLOCKSOURCE_ITRX_INSTANCE',['../group___exported__macros.html#ga57882c3c75fddf0ccf0c6ecf99b3d3df',1,'stm32f407xx_matlab.h']]], - ['is_5ftim_5fclocksource_5ftix_5finstance_326',['IS_TIM_CLOCKSOURCE_TIX_INSTANCE',['../group___exported__macros.html#gacbd23fd1f9f73dc249b16c89131a671c',1,'stm32f407xx_matlab.h']]], - ['is_5ftim_5fcommutation_5fevent_5finstance_327',['IS_TIM_COMMUTATION_EVENT_INSTANCE',['../group___exported__macros.html#ga5f61206c3c8b20784f9d237dce300afd',1,'stm32f407xx_matlab.h']]], - ['is_5ftim_5fcounter_5fmode_5fselect_5finstance_328',['IS_TIM_COUNTER_MODE_SELECT_INSTANCE',['../group___exported__macros.html#gaac0e3e7e7a18fd8eb81734b2baf9e3be',1,'stm32f407xx_matlab.h']]], - ['is_5ftim_5fdma_5fcc_5finstance_329',['IS_TIM_DMA_CC_INSTANCE',['../group___exported__macros.html#gad80a186286ce3daa92249a8d52111aaf',1,'stm32f407xx_matlab.h']]], - ['is_5ftim_5fdma_5finstance_330',['IS_TIM_DMA_INSTANCE',['../group___exported__macros.html#gad51d77b3bcc12a3a5c308d727b561371',1,'stm32f407xx_matlab.h']]], - ['is_5ftim_5fdmaburst_5finstance_331',['IS_TIM_DMABURST_INSTANCE',['../group___exported__macros.html#ga1ed43d4e9823446a1b9d43afc452f42e',1,'stm32f407xx_matlab.h']]], - ['is_5ftim_5fencoder_5finterface_5finstance_332',['IS_TIM_ENCODER_INTERFACE_INSTANCE',['../group___exported__macros.html#gacb14170c4996e004849647d8cb626402',1,'stm32f407xx_matlab.h']]], - ['is_5ftim_5fetr_5finstance_333',['IS_TIM_ETR_INSTANCE',['../group___exported__macros.html#gac71942c3817f1a893ef84fefe69496b7',1,'stm32f407xx_matlab.h']]], - ['is_5ftim_5fhall_5fsensor_5finterface_5finstance_334',['IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE',['../group___exported__macros.html#ga979ea18ba0931f5ed15cc2f3ac84794b',1,'stm32f407xx_matlab.h']]], - ['is_5ftim_5finstance_335',['IS_TIM_INSTANCE',['../group___exported__macros.html#gaba506eb03409b21388d7c5a6401a4f98',1,'stm32f407xx_matlab.h']]], - ['is_5ftim_5fmaster_5finstance_336',['IS_TIM_MASTER_INSTANCE',['../group___exported__macros.html#ga98104b1522d066b0c20205ca179d0eba',1,'stm32f407xx_matlab.h']]], - ['is_5ftim_5focxref_5fclear_5finstance_337',['IS_TIM_OCXREF_CLEAR_INSTANCE',['../group___exported__macros.html#ga7bf2abf939c55a4c8284c184735accdc',1,'stm32f407xx_matlab.h']]], - ['is_5ftim_5fremap_5finstance_338',['IS_TIM_REMAP_INSTANCE',['../group___exported__macros.html#ga6bb03cf116b07bfe1bd527f8ab61a7f9',1,'stm32f407xx_matlab.h']]], - ['is_5ftim_5frepetition_5fcounter_5finstance_339',['IS_TIM_REPETITION_COUNTER_INSTANCE',['../group___exported__macros.html#ga3b470612fd4c4e29fb985247056b1e07',1,'stm32f407xx_matlab.h']]], - ['is_5ftim_5fslave_5finstance_340',['IS_TIM_SLAVE_INSTANCE',['../group___exported__macros.html#ga3ba7d4187dba8dfb4ffd610312e8af14',1,'stm32f407xx_matlab.h']]], - ['is_5ftim_5fxor_5finstance_341',['IS_TIM_XOR_INSTANCE',['../group___exported__macros.html#ga6e06388143bb7bb111c78a3686dd753a',1,'stm32f407xx_matlab.h']]], - ['is_5fuart_5fhalfduplex_5finstance_342',['IS_UART_HALFDUPLEX_INSTANCE',['../group___exported__macros.html#ga69c4aa0c561c4c39c621710fbbb0cb7b',1,'stm32f407xx_matlab.h']]], - ['is_5fuart_5fhwflow_5finstance_343',['IS_UART_HWFLOW_INSTANCE',['../group___exported__macros.html#gaf9a11d0720f3efa780126414a4ac50ad',1,'stm32f407xx_matlab.h']]], - ['is_5fuart_5finstance_344',['IS_UART_INSTANCE',['../group___exported__macros.html#ga14e4b19f7c750110f6c27cf26347ba45',1,'stm32f407xx_matlab.h']]], - ['is_5fuart_5flin_5finstance_345',['IS_UART_LIN_INSTANCE',['../group___exported__macros.html#gaf7905bb5a02acf0e92ddf40bdd8dcdc0',1,'stm32f407xx_matlab.h']]], - ['is_5fusart_5finstance_346',['IS_USART_INSTANCE',['../group___exported__macros.html#gafbce654f84a7c994817453695ac91cbe',1,'stm32f407xx_matlab.h']]], - ['is_5fwwdg_5fall_5finstance_347',['IS_WWDG_ALL_INSTANCE',['../group___exported__macros.html#gac2a8aaec233e19987232455643a04d6f',1,'stm32f407xx_matlab.h']]], - ['isar_348',['ISAR',['../group___c_m_s_i_s__core___debug_functions.html#gaf2950df748750d535d5d65ac1c209563',1,'SCB_Type']]], - ['iser_349',['ISER',['../group___c_m_s_i_s__core___debug_functions.html#ga543747b83b9b1fab6545e8d36ae8b75b',1,'NVIC_Type']]], - ['ispr_350',['ISPR',['../group___c_m_s_i_s__core___debug_functions.html#gaf8330682adf1f1335bc02929acff3a3f',1,'NVIC_Type']]], - ['isr_351',['ISR',['../group___c_m_s_i_s__core___debug_functions.html#gad502ba7dbb2aab5f87c782b28f02622d',1,'IPSR_Type::ISR'],['../group___c_m_s_i_s__core___debug_functions.html#gad502ba7dbb2aab5f87c782b28f02622d',1,'IPSR_Type::@1::ISR'],['../group___c_m_s_i_s__core___debug_functions.html#gad502ba7dbb2aab5f87c782b28f02622d',1,'xPSR_Type::ISR'],['../group___c_m_s_i_s__core___debug_functions.html#gad502ba7dbb2aab5f87c782b28f02622d',1,'xPSR_Type::@2::ISR'],['../group___c_m_s_i_s___device.html#gab3c49a96815fcbee63d95e1e74f20e75',1,'RTC_TypeDef::ISR']]], - ['itatbctr0_352',['ITATBCTR0',['../group___c_m_s_i_s__core___debug_functions.html#ga9954c088735caa505adc113f6c64d812',1,'TPI_Type']]], - ['itatbctr2_353',['ITATBCTR2',['../group___c_m_s_i_s__core___debug_functions.html#ga97fb8816ad001f4910de095aa17d9db5',1,'TPI_Type']]], - ['itctrl_354',['ITCTRL',['../group___c_m_s_i_s__core___debug_functions.html#gae6b7f224b1c19c636148f991cc8db611',1,'TPI_Type']]], - ['itm_355',['ITM',['../group___c_m_s_i_s___i_t_m.html',1,'Instrumentation Trace Macrocell (ITM)'],['../group___c_m_s_i_s__core__base.html#gabae7cdf882def602cb787bb039ff6a43',1,'ITM: core_cm4_matlab.h']]], - ['itm_20functions_356',['ITM Functions',['../group___c_m_s_i_s__core___debug_functions.html',1,'']]], - ['itm_5fbase_357',['ITM_BASE',['../group___c_m_s_i_s__core__base.html#gadd76251e412a195ec0a8f47227a8359e',1,'core_cm4_matlab.h']]], - ['itm_5fbase_5fshift_358',['ITM_BASE_SHIFT',['../group___c_m_s_i_s__core__base.html#ga13157bf906d2f9c99e0942ce1e79f8d4',1,'core_cm4_matlab.h']]], - ['itm_5fcheckchar_359',['ITM_CheckChar',['../group___c_m_s_i_s__core___debug_functions.html#gae61ce9ca5917735325cd93b0fb21dd29',1,'core_cm4_matlab.h']]], - ['itm_5fimcr_5fintegration_5fmsk_360',['ITM_IMCR_INTEGRATION_Msk',['../group___c_m_s_i_s___i_t_m.html#ga8838bd3dd04c1a6be97cd946364a3fd2',1,'core_cm4_matlab.h']]], - ['itm_5fimcr_5fintegration_5fpos_361',['ITM_IMCR_INTEGRATION_Pos',['../group___c_m_s_i_s___i_t_m.html#ga08de02bf32caf48aaa29f7c68ff5d755',1,'core_cm4_matlab.h']]], - ['itm_5firr_5fatreadym_5fmsk_362',['ITM_IRR_ATREADYM_Msk',['../group___c_m_s_i_s___i_t_m.html#ga3dbc3e15f5bde2669cd8121a1fe419b9',1,'core_cm4_matlab.h']]], - ['itm_5firr_5fatreadym_5fpos_363',['ITM_IRR_ATREADYM_Pos',['../group___c_m_s_i_s___i_t_m.html#ga259edfd1d2e877a62e06d7a240df97f4',1,'core_cm4_matlab.h']]], - ['itm_5fiwr_5fatvalidm_5fmsk_364',['ITM_IWR_ATVALIDM_Msk',['../group___c_m_s_i_s___i_t_m.html#ga67b969f8f04ed15886727788f0e2ffd7',1,'core_cm4_matlab.h']]], - ['itm_5fiwr_5fatvalidm_5fpos_365',['ITM_IWR_ATVALIDM_Pos',['../group___c_m_s_i_s___i_t_m.html#ga04d3f842ad48f6a9127b4cecc963e1d7',1,'core_cm4_matlab.h']]], - ['itm_5flsr_5faccess_5fmsk_366',['ITM_LSR_Access_Msk',['../group___c_m_s_i_s___i_t_m.html#gac8ae69f11c0311da226c0c8ec40b3d37',1,'core_cm4_matlab.h']]], - ['itm_5flsr_5faccess_5fpos_367',['ITM_LSR_Access_Pos',['../group___c_m_s_i_s___i_t_m.html#ga144a49e12b83ad9809fdd2769094fdc0',1,'core_cm4_matlab.h']]], - ['itm_5flsr_5fbyteacc_5fmsk_368',['ITM_LSR_ByteAcc_Msk',['../group___c_m_s_i_s___i_t_m.html#ga91f492b2891bb8b7eac5b58de7b220f4',1,'core_cm4_matlab.h']]], - ['itm_5flsr_5fbyteacc_5fpos_369',['ITM_LSR_ByteAcc_Pos',['../group___c_m_s_i_s___i_t_m.html#gabfae3e570edc8759597311ed6dfb478e',1,'core_cm4_matlab.h']]], - ['itm_5flsr_5fpresent_5fmsk_370',['ITM_LSR_Present_Msk',['../group___c_m_s_i_s___i_t_m.html#gaa5bc2a7f5f1d69ff819531f5508bb017',1,'core_cm4_matlab.h']]], - ['itm_5flsr_5fpresent_5fpos_371',['ITM_LSR_Present_Pos',['../group___c_m_s_i_s___i_t_m.html#gaf5740689cf14564d3f3fd91299b6c88d',1,'core_cm4_matlab.h']]], - ['itm_5freceivechar_372',['ITM_ReceiveChar',['../group___c_m_s_i_s__core___debug_functions.html#gac3ee2c30a1ac4ed34c8a866a17decd53',1,'core_cm4_matlab.h']]], - ['itm_5frxbuffer_373',['ITM_RxBuffer',['../group___c_m_s_i_s__core___debug_functions.html#ga12e68e55a7badc271b948d6c7230b2a8',1,'core_cm4_matlab.h']]], - ['itm_5frxbuffer_5fempty_374',['ITM_RXBUFFER_EMPTY',['../group___c_m_s_i_s__core___debug_functions.html#gaa822cb398ee022b59e9e6c5d7bbb228a',1,'core_cm4_matlab.h']]], - ['itm_5fsendchar_375',['ITM_SendChar',['../group___c_m_s_i_s__core___debug_functions.html#gac90a497bd64286b84552c2c553d3419e',1,'core_cm4_matlab.h']]], - ['itm_5ftcr_5fbusy_5fmsk_376',['ITM_TCR_BUSY_Msk',['../group___c_m_s_i_s___i_t_m.html#ga43ad7cf33de12f2ef3a412d4f354c60f',1,'core_cm4_matlab.h']]], - ['itm_5ftcr_5fbusy_5fpos_377',['ITM_TCR_BUSY_Pos',['../group___c_m_s_i_s___i_t_m.html#ga9174ad4a36052c377cef4e6aba2ed484',1,'core_cm4_matlab.h']]], - ['itm_5ftcr_5fdwtena_5fmsk_378',['ITM_TCR_DWTENA_Msk',['../group___c_m_s_i_s___i_t_m.html#ga98ea1c596d43d3633a202f9ee746cf70',1,'core_cm4_matlab.h']]], - ['itm_5ftcr_5fdwtena_5fpos_379',['ITM_TCR_DWTENA_Pos',['../group___c_m_s_i_s___i_t_m.html#ga30e83ebb33aa766070fe3d1f27ae820e',1,'core_cm4_matlab.h']]], - ['itm_5ftcr_5fgtsfreq_5fmsk_380',['ITM_TCR_GTSFREQ_Msk',['../group___c_m_s_i_s___i_t_m.html#gade862cf009827f7f6748fc44c541b067',1,'core_cm4_matlab.h']]], - ['itm_5ftcr_5fgtsfreq_5fpos_381',['ITM_TCR_GTSFREQ_Pos',['../group___c_m_s_i_s___i_t_m.html#ga96c7c7cbc0d98426c408090b41f583f1',1,'core_cm4_matlab.h']]], - ['itm_5ftcr_5fitmena_5fmsk_382',['ITM_TCR_ITMENA_Msk',['../group___c_m_s_i_s___i_t_m.html#ga7dd53e3bff24ac09d94e61cb595cb2d9',1,'core_cm4_matlab.h']]], - ['itm_5ftcr_5fitmena_5fpos_383',['ITM_TCR_ITMENA_Pos',['../group___c_m_s_i_s___i_t_m.html#ga3286b86004bce7ffe17ee269f87f8d9d',1,'core_cm4_matlab.h']]], - ['itm_5ftcr_5fswoena_5fmsk_384',['ITM_TCR_SWOENA_Msk',['../group___c_m_s_i_s___i_t_m.html#ga97476cb65bab16a328b35f81fd02010a',1,'core_cm4_matlab.h']]], - ['itm_5ftcr_5fswoena_5fpos_385',['ITM_TCR_SWOENA_Pos',['../group___c_m_s_i_s___i_t_m.html#ga7a380f0c8078f6560051406583ecd6a5',1,'core_cm4_matlab.h']]], - ['itm_5ftcr_5fsyncena_5fmsk_386',['ITM_TCR_SYNCENA_Msk',['../group___c_m_s_i_s___i_t_m.html#gac89b74a78701c25b442105d7fe2bbefb',1,'core_cm4_matlab.h']]], - ['itm_5ftcr_5fsyncena_5fpos_387',['ITM_TCR_SYNCENA_Pos',['../group___c_m_s_i_s___i_t_m.html#gaa93a1147a39fc63980d299231252a30e',1,'core_cm4_matlab.h']]], - ['itm_5ftcr_5ftracebusid_5fmsk_388',['ITM_TCR_TraceBusID_Msk',['../group___c_m_s_i_s___i_t_m.html#ga60c20bd9649d1da5a2be8e656ba19a60',1,'core_cm4_matlab.h']]], - ['itm_5ftcr_5ftracebusid_5fpos_389',['ITM_TCR_TraceBusID_Pos',['../group___c_m_s_i_s___i_t_m.html#gaca0281de867f33114aac0636f7ce65d3',1,'core_cm4_matlab.h']]], - ['itm_5ftcr_5ftsena_5fmsk_390',['ITM_TCR_TSENA_Msk',['../group___c_m_s_i_s___i_t_m.html#ga436b2e8fa24328f48f2da31c00fc9e65',1,'core_cm4_matlab.h']]], - ['itm_5ftcr_5ftsena_5fpos_391',['ITM_TCR_TSENA_Pos',['../group___c_m_s_i_s___i_t_m.html#ga5aa381845f810114ab519b90753922a1',1,'core_cm4_matlab.h']]], - ['itm_5ftcr_5ftsprescale_5fmsk_392',['ITM_TCR_TSPrescale_Msk',['../group___c_m_s_i_s___i_t_m.html#ga7a723f71bfb0204c264d8dbe8cc7ae52',1,'core_cm4_matlab.h']]], - ['itm_5ftcr_5ftsprescale_5fpos_393',['ITM_TCR_TSPrescale_Pos',['../group___c_m_s_i_s___i_t_m.html#gad7bc9ee1732032c6e0de035f0978e473',1,'core_cm4_matlab.h']]], - ['itm_5ftpr_5fprivmask_5fmsk_394',['ITM_TPR_PRIVMASK_Msk',['../group___c_m_s_i_s___i_t_m.html#ga168e089d882df325a387aab3a802a46b',1,'core_cm4_matlab.h']]], - ['itm_5ftpr_5fprivmask_5fpos_395',['ITM_TPR_PRIVMASK_Pos',['../group___c_m_s_i_s___i_t_m.html#ga7abe5e590d1611599df87a1884a352e8',1,'core_cm4_matlab.h']]], - ['itm_5ftype_396',['ITM_Type',['../struct_i_t_m___type.html',1,'']]], - ['itstatus_397',['ITStatus',['../group___exported__types.html#ga39d4411201fb731279ad5a409b2b80d7',1,'stm32f4xx.h']]], - ['iwdg_398',['IWDG',['../group___peripheral__declaration.html#gad16b79dd94ee85d261d08a8ee94187e7',1,'stm32f407xx_matlab.h']]], - ['iwdg_399',['iwdg',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#gaa40a4f8558a3a1b0ed98bad7ea997a8b',1,'stm32f4xx_periph_registers.c']]], - ['iwdg_5fbase_400',['IWDG_BASE',['../group___peripheral__memory__map.html#ga8543ee4997296af5536b007cd4748f55',1,'stm32f407xx_matlab.h']]], - ['iwdg_5fkr_5fkey_401',['IWDG_KR_KEY',['../group___peripheral___registers___bits___definition.html#ga957f7d5f8a0ec1a6956a7f05cfbd97c2',1,'stm32f407xx_matlab.h']]], - ['iwdg_5fkr_5fkey_5fmsk_402',['IWDG_KR_KEY_Msk',['../group___peripheral___registers___bits___definition.html#ga4ccb19a688f8e5b1c41626d3718db07e',1,'stm32f407xx_matlab.h']]], - ['iwdg_5fkr_5fkey_5fpos_403',['IWDG_KR_KEY_Pos',['../group___peripheral___registers___bits___definition.html#ga6a5d1982414442435695ce911fc91b3c',1,'stm32f407xx_matlab.h']]], - ['iwdg_5fpr_5fpr_404',['IWDG_PR_PR',['../group___peripheral___registers___bits___definition.html#ga4de39c5672f17d326fceb5adc9adc090',1,'stm32f407xx_matlab.h']]], - ['iwdg_5fpr_5fpr_5f0_405',['IWDG_PR_PR_0',['../group___peripheral___registers___bits___definition.html#ga9b727e7882603df1684cbf230520ca76',1,'stm32f407xx_matlab.h']]], - ['iwdg_5fpr_5fpr_5f1_406',['IWDG_PR_PR_1',['../group___peripheral___registers___bits___definition.html#gafba2551b90c68d95c736a116224b473e',1,'stm32f407xx_matlab.h']]], - ['iwdg_5fpr_5fpr_5f2_407',['IWDG_PR_PR_2',['../group___peripheral___registers___bits___definition.html#ga55a1d7fde4e3e724a8644652ba9bb2b9',1,'stm32f407xx_matlab.h']]], - ['iwdg_5fpr_5fpr_5fmsk_408',['IWDG_PR_PR_Msk',['../group___peripheral___registers___bits___definition.html#ga75390b0bbc7eb3073a88536fe7f1c5ff',1,'stm32f407xx_matlab.h']]], - ['iwdg_5fpr_5fpr_5fpos_409',['IWDG_PR_PR_Pos',['../group___peripheral___registers___bits___definition.html#ga25d9c482d27bbc46b08d321c79d058e7',1,'stm32f407xx_matlab.h']]], - ['iwdg_5frlr_5frl_410',['IWDG_RLR_RL',['../group___peripheral___registers___bits___definition.html#ga87024bbb19f26def4c4c1510b22d3033',1,'stm32f407xx_matlab.h']]], - ['iwdg_5frlr_5frl_5fmsk_411',['IWDG_RLR_RL_Msk',['../group___peripheral___registers___bits___definition.html#ga797562ce090da2d4b6576ba3ec62ad12',1,'stm32f407xx_matlab.h']]], - ['iwdg_5frlr_5frl_5fpos_412',['IWDG_RLR_RL_Pos',['../group___peripheral___registers___bits___definition.html#ga57519650f213ae6a72cf9983d64b8618',1,'stm32f407xx_matlab.h']]], - ['iwdg_5fsr_5fpvu_413',['IWDG_SR_PVU',['../group___peripheral___registers___bits___definition.html#ga269bd5618ba773d32275b93be004c554',1,'stm32f407xx_matlab.h']]], - ['iwdg_5fsr_5fpvu_5fmsk_414',['IWDG_SR_PVU_Msk',['../group___peripheral___registers___bits___definition.html#ga7e966837f97df9cde2383682f0234a96',1,'stm32f407xx_matlab.h']]], - ['iwdg_5fsr_5fpvu_5fpos_415',['IWDG_SR_PVU_Pos',['../group___peripheral___registers___bits___definition.html#ga8174d249dcd092b42f36a09e5e04def1',1,'stm32f407xx_matlab.h']]], - ['iwdg_5fsr_5frvu_416',['IWDG_SR_RVU',['../group___peripheral___registers___bits___definition.html#gadffb8339e556a3b10120b15f0dacc232',1,'stm32f407xx_matlab.h']]], - ['iwdg_5fsr_5frvu_5fmsk_417',['IWDG_SR_RVU_Msk',['../group___peripheral___registers___bits___definition.html#gab984dca55296c6bc7aef24d356909c28',1,'stm32f407xx_matlab.h']]], - ['iwdg_5fsr_5frvu_5fpos_418',['IWDG_SR_RVU_Pos',['../group___peripheral___registers___bits___definition.html#ga4aeb9bcef7e84f6760608f5fcd052fec',1,'stm32f407xx_matlab.h']]], - ['iwdg_5ftypedef_419',['IWDG_TypeDef',['../struct_i_w_d_g___type_def.html',1,'']]], - ['iwr_420',['IWR',['../group___c_m_s_i_s__core___debug_functions.html#ga68e56eb5e16d2aa293b0bec5c99e50fe',1,'ITM_Type']]] + ['i2c2_1',['i2c2',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#gaf4f631faa01cf5bb61ddc01eeb90d522',1,'stm32f4xx_periph_registers.c']]], + ['i2c3_2',['i2c3',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#gac651c52b4ae02ee475e7babe47132f15',1,'stm32f4xx_periph_registers.c']]], + ['i2s2ext_3',['i2s2ext',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga06974a33ee50f86662415a0c4af114a8',1,'stm32f4xx_periph_registers.c']]], + ['i2s3ext_4',['i2s3ext',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#gadc6636f1a31d3d480e01c46ffa6edddf',1,'stm32f4xx_periph_registers.c']]], + ['idmcuthread_5',['idMCUThread',['../struct_s_i_m_____m_c_u_handle_type_def.html#a52fe34944579ff4b1b6d3e85fae96546',1,'SIM__MCUHandleTypeDef']]], + ['in_5fport_5fnumb_6',['IN_PORT_NUMB',['../group___w_r_a_p_p_e_r___c_o_n_f.html#ga25be09b98d138ff8c740bece06e1bcc6',1,'mcu_wrapper_conf.h']]], + ['in_5fport_5fwidth_7',['IN_PORT_WIDTH',['../group___w_r_a_p_p_e_r___c_o_n_f.html#gac41471250c3d92da182a969e378addfc',1,'mcu_wrapper_conf.h']]], + ['init_5ftim_5fsim_8',['Init_TIM_SIM',['../stm32f4xx__matlab__conf_8c.html#a617bc2e624bea041e844a0ac0c6a50f9',1,'Init_TIM_SIM(void): stm32f4xx_matlab_conf.c'],['../stm32f4xx__matlab__conf_8h.html#a617bc2e624bea041e844a0ac0c6a50f9',1,'Init_TIM_SIM(void): stm32f4xx_matlab_conf.c']]], + ['initialize_5fperiph_5fsim_9',['Initialize_Periph_Sim',['../group___m_a_i_n___s_i_m_u_l_a_t_o_r.html#gab020a77f89d6c0ea99c7559cfa7e3ba0',1,'Initialize_Periph_Sim(void): stm32f4xx_matlab_conf.c'],['../group___m_a_i_n___s_i_m_u_l_a_t_o_r.html#gab020a77f89d6c0ea99c7559cfa7e3ba0',1,'Initialize_Periph_Sim(void): stm32f4xx_matlab_conf.c']]], + ['itm_10',['ITM',['../group___c_m_s_i_s__core__base.html#gabae7cdf882def602cb787bb039ff6a43',1,'stm32f407xx_matlab_memory.h']]], + ['itm_5fbase_11',['ITM_BASE',['../group___c_m_s_i_s__core__base.html#gadd76251e412a195ec0a8f47227a8359e',1,'stm32f407xx_matlab_memory.h']]], + ['itm_5fbase_5fshift_12',['ITM_BASE_SHIFT',['../group___c_m_s_i_s__core__base.html#ga13157bf906d2f9c99e0942ce1e79f8d4',1,'stm32f407xx_matlab_memory.h']]], + ['iwdg_13',['iwdg',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#gaa40a4f8558a3a1b0ed98bad7ea997a8b',1,'stm32f4xx_periph_registers.c']]] ]; diff --git a/DOCS/html/search/all_a.js b/DOCS/html/search/all_a.js index c8da0b8..08e7aec 100644 --- a/DOCS/html/search/all_a.js +++ b/DOCS/html/search/all_a.js @@ -1,12 +1,32 @@ var searchData= [ - ['jdr1_0',['JDR1',['../group___c_m_s_i_s___device.html#ga22fa21352be442bd02f9c26a1013d598',1,'ADC_TypeDef']]], - ['jdr2_1',['JDR2',['../group___c_m_s_i_s___device.html#gae9156af81694b7a85923348be45a2167',1,'ADC_TypeDef']]], - ['jdr3_2',['JDR3',['../group___c_m_s_i_s___device.html#ga3a54028253a75a470fccf841178cba46',1,'ADC_TypeDef']]], - ['jdr4_3',['JDR4',['../group___c_m_s_i_s___device.html#ga9274ceea3b2c6d5c1903d0a7abad91a1',1,'ADC_TypeDef']]], - ['jofr1_4',['JOFR1',['../group___c_m_s_i_s___device.html#ga427dda1678f254bd98b1f321d7194a3b',1,'ADC_TypeDef']]], - ['jofr2_5',['JOFR2',['../group___c_m_s_i_s___device.html#ga11e65074b9f06b48c17cdfa5bea9f125',1,'ADC_TypeDef']]], - ['jofr3_6',['JOFR3',['../group___c_m_s_i_s___device.html#ga613f6b76d20c1a513976b920ecd7f4f8',1,'ADC_TypeDef']]], - ['jofr4_7',['JOFR4',['../group___c_m_s_i_s___device.html#ga2fd59854223e38158b4138ee8e913ab3',1,'ADC_TypeDef']]], - ['jsqr_8',['JSQR',['../group___c_m_s_i_s___device.html#ga75e0cc079831adcc051df456737d3ae4',1,'ADC_TypeDef']]] + ['main_0',['main',['../mcu__wrapper_8c.html#a840291bc02cba5474a4cb46a9b9566fe',1,'mcu_wrapper.c']]], + ['map_1',['Peripheral Memory Map',['../group___peripheral__memory__map.html',1,'']]], + ['matlab_2',['ЭмулÑтор STM Ð´Ð»Ñ MATLAB',['../index.html#ÑмулÑтор-stm-длÑ-matlab',1,'']]], + ['matlab_20stm32_20emulator_3',['MATLAB STM32 EMULATOR',['../index.html',1,'']]], + ['mcu_20wrapper_4',['MCU Wrapper',['../group___m_c_u___w_r_a_p_p_e_r.html',1,'']]], + ['mcu_2ec_5',['MCU.c',['../_m_c_u_8c.html',1,'']]], + ['mcu_5fapp_5fthread_6',['MCU_App_Thread',['../mcu__wrapper_8c.html#a1ea76a95b9b28061fb34ece9f6f0a85f',1,'mcu_wrapper.c']]], + ['mcu_5fcortex_5fmem_7',['MCU_CORTEX_MEM',['../group___c_m_s_i_s__core__base.html#ga47e1165d2b04b61b504f52b9f4782708',1,'MCU_CORTEX_MEM: stm32f4xx_matlab_conf.c'],['../group___c_m_s_i_s__core__base.html#ga47e1165d2b04b61b504f52b9f4782708',1,'MCU_CORTEX_MEM: stm32f4xx_matlab_conf.c']]], + ['mcu_5fcortexmemorytypedef_8',['MCU_CortexMemoryTypeDef',['../group___c_m_s_i_s__core__base.html#ga2283564fd240ac8b420f104dc381ce94',1,'stm32f407xx_matlab_memory.h']]], + ['mcu_5fmem_9',['MCU_MEM',['../group___peripheral__memory__map.html#gaf157a51d290d1383d493a6a2fe0241fc',1,'MCU_MEM: stm32f4xx_matlab_conf.c'],['../group___peripheral__memory__map.html#gaf157a51d290d1383d493a6a2fe0241fc',1,'MCU_MEM: stm32f4xx_matlab_conf.c']]], + ['mcu_5fmem_5fend_10',['MCU_MEM_END',['../group___peripheral__memory__map.html#ga4ddc1e9172ba6fe724328595a3fadcf2',1,'stm32f407xx_matlab_memory.h']]], + ['mcu_5fmemorytypedef_11',['MCU_MemoryTypeDef',['../group___peripheral__memory__map.html#ga304d35aeeebef1445af976d8a5248d57',1,'stm32f407xx_matlab_memory.h']]], + ['mcu_5fperiph_5fsimulation_12',['MCU_Periph_Simulation',['../group___m_c_u___w_r_a_p_p_e_r.html#gaccdef5b45f3d1646f248304e02b00e54',1,'MCU_Periph_Simulation(void): mcu_wrapper.c'],['../group___m_c_u___w_r_a_p_p_e_r.html#gaccdef5b45f3d1646f248304e02b00e54',1,'MCU_Periph_Simulation(void): mcu_wrapper.c']]], + ['mcu_5freadinputs_13',['MCU_readInputs',['../group___m_c_u___w_r_a_p_p_e_r.html#ga15045e0feba8ddf08e20958fd1e36cd5',1,'MCU_readInputs(SimStruct *S): mcu_wrapper.c'],['../group___m_c_u___w_r_a_p_p_e_r.html#ga15045e0feba8ddf08e20958fd1e36cd5',1,'MCU_readInputs(SimStruct *S): mcu_wrapper.c']]], + ['mcu_5fstep_5fsimulation_14',['MCU_Step_Simulation',['../group___m_c_u___w_r_a_p_p_e_r.html#gad3c4ea41584d0367dfbfb697f5e57456',1,'MCU_Step_Simulation(SimStruct *S, time_T time): mcu_wrapper.c'],['../group___m_c_u___w_r_a_p_p_e_r.html#gad3c4ea41584d0367dfbfb697f5e57456',1,'MCU_Step_Simulation(SimStruct *S, time_T time): mcu_wrapper.c']]], + ['mcu_5fwrapper_2ec_15',['mcu_wrapper.c',['../mcu__wrapper_8c.html',1,'']]], + ['mcu_5fwrapper_5fconf_2eh_16',['mcu_wrapper_conf.h',['../mcu__wrapper__conf_8h.html',1,'']]], + ['mcu_5fwriteoutputs_17',['MCU_writeOutputs',['../group___m_c_u___w_r_a_p_p_e_r.html#gad6b7bb9233d746d7709276f9ea1914c2',1,'MCU_writeOutputs(SimStruct *S): mcu_wrapper.c'],['../group___m_c_u___w_r_a_p_p_e_r.html#gad6b7bb9233d746d7709276f9ea1914c2',1,'MCU_writeOutputs(SimStruct *S): mcu_wrapper.c']]], + ['mdl_5fcheck_5fparameters_18',['MDL_CHECK_PARAMETERS',['../group___w_r_a_p_p_e_r___s_f_u_n_c.html#ga4936bd489281a5a9b9a2e081de0f003e',1,'MCU.c']]], + ['mdl_5fstart_19',['MDL_START',['../group___w_r_a_p_p_e_r___s_f_u_n_c.html#gac032abbf580c891fb0c11e63e9bc668a',1,'MCU.c']]], + ['mdl_5fupdate_20',['MDL_UPDATE',['../group___w_r_a_p_p_e_r___s_f_u_n_c.html#ga7556dbbf5cb7f9946d3e39bcda40c63b',1,'MCU.c']]], + ['mdlinitializesampletimes_21',['mdlInitializeSampleTimes',['../group___w_r_a_p_p_e_r___s_f_u_n_c.html#ga4308a5a20d9c7060391059b1dfce872e',1,'MCU.c']]], + ['mdlinitializesizes_22',['mdlInitializeSizes',['../group___w_r_a_p_p_e_r___s_f_u_n_c.html#gab500fc17ae5e95797926ac770d903b84',1,'MCU.c']]], + ['mdloutputs_23',['mdlOutputs',['../group___w_r_a_p_p_e_r___s_f_u_n_c.html#ga52f81157111c2436496e1a9630bdce5b',1,'MCU.c']]], + ['mdlstart_24',['mdlStart',['../group___w_r_a_p_p_e_r___s_f_u_n_c.html#ga0dd07daf338cf84d1aee4bb8b6771720',1,'MCU.c']]], + ['mdlterminate_25',['mdlTerminate',['../group___w_r_a_p_p_e_r___s_f_u_n_c.html#ga343acfd8b3b5308d6c94bbf40efbbac5',1,'MCU.c']]], + ['mdlupdate_26',['mdlUpdate',['../group___w_r_a_p_p_e_r___s_f_u_n_c.html#gad3d5b495abad2acd2ae68febd1d2c5ec',1,'MCU.c']]], + ['memory_20map_27',['Peripheral Memory Map',['../group___peripheral__memory__map.html',1,'']]], + ['mexing_2em_28',['mexing.m',['../mexing_8m.html',1,'']]] ]; diff --git a/DOCS/html/search/all_b.js b/DOCS/html/search/all_b.js index 156845b..17b84ea 100644 --- a/DOCS/html/search/all_b.js +++ b/DOCS/html/search/all_b.js @@ -1,5 +1,7 @@ var searchData= [ - ['keyr_0',['KEYR',['../group___c_m_s_i_s___device.html#ga84c491be6c66b1d5b6a2efd0740b3d0c',1,'FLASH_TypeDef']]], - ['kr_1',['KR',['../group___c_m_s_i_s___device.html#ga2f692354bde770f2a5e3e1b294ec064b',1,'IWDG_TypeDef']]] + ['native_5fwhile_0',['native_while',['../group___m_c_u___w_r_a_p_p_e_r.html#gabaad5b5eb9243ab531775be5eda6ee02',1,'mcu_wrapper_conf.h']]], + ['nparams_1',['NPARAMS',['../group___w_r_a_p_p_e_r___c_o_n_f.html#gae468832efa6adf5e9a96cabd8f878b47',1,'mcu_wrapper_conf.h']]], + ['nvic_2',['NVIC',['../group___c_m_s_i_s__core__base.html#gac8e97e8ce56ae9f57da1363a937f8a17',1,'stm32f407xx_matlab_memory.h']]], + ['nvic_5fbase_3',['NVIC_BASE',['../group___c_m_s_i_s__core__base.html#gaa0288691785a5f868238e0468b39523d',1,'stm32f407xx_matlab_memory.h']]] ]; diff --git a/DOCS/html/search/all_c.js b/DOCS/html/search/all_c.js index 6a9c2ec..40c0d8d 100644 --- a/DOCS/html/search/all_c.js +++ b/DOCS/html/search/all_c.js @@ -1,13 +1,18 @@ var searchData= [ - ['lar_0',['LAR',['../group___c_m_s_i_s__core___debug_functions.html#gacc9e51f871c357a9094105435b150d13',1,'ITM_Type']]], - ['lckr_1',['LCKR',['../group___c_m_s_i_s___device.html#ga2612a0f4b3fbdbb6293f6dc70105e190',1,'GPIO_TypeDef']]], - ['library_5fconfiguration_5fsection_2',['Library_configuration_section',['../group___library__configuration__section.html',1,'']]], - ['lifcr_3',['LIFCR',['../group___c_m_s_i_s___device.html#gac4f7bf4cb172024bfc940c00167cd04e',1,'DMA_TypeDef']]], - ['lisr_4',['LISR',['../group___c_m_s_i_s___device.html#ga5cdef358e9e95b570358e1f6a3a7f492',1,'DMA_TypeDef']]], - ['load_5',['LOAD',['../group___c_m_s_i_s__core___debug_functions.html#ga0c1333686137b7e25a46bd548a5b5bc3',1,'SysTick_Type']]], - ['lsi_5fstartup_5ftime_6',['LSI_STARTUP_TIME',['../group___hardware___constant___definition.html#gab9ea77371b070034ca2a56381a7e9de7',1,'stm32f407xx_matlab.h']]], - ['lsr_7',['LSR',['../group___c_m_s_i_s__core___debug_functions.html#ga7219432d03f6cd1d220f4fe10aef4880',1,'ITM_Type']]], - ['lsucnt_8',['LSUCNT',['../group___c_m_s_i_s__core___debug_functions.html#gae886261750c8c90d67a2f276d074e9c3',1,'DWT_Type']]], - ['ltr_9',['LTR',['../group___c_m_s_i_s___device.html#ga9f8712dfef7125c0bb39db11f2b7416b',1,'ADC_TypeDef']]] + ['oc1_5fgpiox_0',['OC1_GPIOx',['../struct_channels___sim.html#a48f9b22f7e44d1b56aa793c2344e06d1',1,'Channels_Sim']]], + ['oc1_5fpin_5fshift_1',['OC1_PIN_SHIFT',['../struct_channels___sim.html#a2d558fbd100d8052eb0e235ad9b1edfe',1,'Channels_Sim']]], + ['oc1ref_2',['OC1REF',['../struct_channels___sim.html#aae6762f43d55e99c3076c9f7e5cda5d9',1,'Channels_Sim']]], + ['oc2_5fgpiox_3',['OC2_GPIOx',['../struct_channels___sim.html#a095026a66ff13e090dae52ee17263f2d',1,'Channels_Sim']]], + ['oc2_5fpin_5fshift_4',['OC2_PIN_SHIFT',['../struct_channels___sim.html#ac2fdf8c4e985eee4ab2e6c82251c12cf',1,'Channels_Sim']]], + ['oc2ref_5',['OC2REF',['../struct_channels___sim.html#aa038da4ce5b26f3d86cda283a9cd749e',1,'Channels_Sim']]], + ['oc3_5fgpiox_6',['OC3_GPIOx',['../struct_channels___sim.html#a7d239c94641795d3caf5c28f8b7cc68d',1,'Channels_Sim']]], + ['oc3_5fpin_5fshift_7',['OC3_PIN_SHIFT',['../struct_channels___sim.html#ac15bcebfa2102716c5b6a4f80b2d51ab',1,'Channels_Sim']]], + ['oc3ref_8',['OC3REF',['../struct_channels___sim.html#abbea161f1b685a5d353d453fc9b56284',1,'Channels_Sim']]], + ['oc4_5fgpiox_9',['OC4_GPIOx',['../struct_channels___sim.html#a851558373b04d1a8a5dbb3c0da9279d8',1,'Channels_Sim']]], + ['oc4_5fpin_5fshift_10',['OC4_PIN_SHIFT',['../struct_channels___sim.html#aa87736409f5ca9986200fcb480920c5b',1,'Channels_Sim']]], + ['oc4ref_11',['OC4REF',['../struct_channels___sim.html#a1c6c166d70bfe9597717f6892da4f446',1,'Channels_Sim']]], + ['out_5fport_5fnumb_12',['OUT_PORT_NUMB',['../group___w_r_a_p_p_e_r___c_o_n_f.html#ga9fa483e805a6570c4793b1e0ff9719ac',1,'mcu_wrapper_conf.h']]], + ['out_5fport_5fwidth_13',['OUT_PORT_WIDTH',['../group___w_r_a_p_p_e_r___c_o_n_f.html#gac90b37686b0abfe29835c9632310897a',1,'mcu_wrapper_conf.h']]], + ['overflow_5fcheck_14',['Overflow_Check',['../group___t_i_m___s_i_m_u_l_a_t_o_r.html#ga05b798408f2179ae27731f231cf4b620',1,'Overflow_Check(TIM_TypeDef *TIMx, struct TIM_Sim *TIMS): stm32f4xx_matlab_tim.c'],['../group___t_i_m___s_i_m_u_l_a_t_o_r.html#ga05b798408f2179ae27731f231cf4b620',1,'Overflow_Check(TIM_TypeDef *TIMx, struct TIM_Sim *TIMS): stm32f4xx_matlab_tim.c']]] ]; diff --git a/DOCS/html/search/all_d.js b/DOCS/html/search/all_d.js index 0c16302..412949b 100644 --- a/DOCS/html/search/all_d.js +++ b/DOCS/html/search/all_d.js @@ -1,77 +1,14 @@ var searchData= [ - ['m0ar_0',['M0AR',['../group___c_m_s_i_s___device.html#ga63b4d166f4ab5024db6b493a7ab7b640',1,'DMA_Stream_TypeDef']]], - ['m1ar_1',['M1AR',['../group___c_m_s_i_s___device.html#gaee7782244ceb4791d9a3891804ac47ac',1,'DMA_Stream_TypeDef']]], - ['maca0hr_2',['MACA0HR',['../group___c_m_s_i_s___device.html#gab8b4520c137846f0a128146144514419',1,'ETH_TypeDef']]], - ['maca0lr_3',['MACA0LR',['../group___c_m_s_i_s___device.html#ga45e8169adb601f00e411b840f9fbb5af',1,'ETH_TypeDef']]], - ['maca1hr_4',['MACA1HR',['../group___c_m_s_i_s___device.html#ga3a6cc81e1024f9a93ec7653d32f12dcb',1,'ETH_TypeDef']]], - ['maca1lr_5',['MACA1LR',['../group___c_m_s_i_s___device.html#gaadfb486dd07e2fd02fb491733deffd9b',1,'ETH_TypeDef']]], - ['maca2hr_6',['MACA2HR',['../group___c_m_s_i_s___device.html#ga38f1ce04678d5141e115cfd6f7b803d1',1,'ETH_TypeDef']]], - ['maca2lr_7',['MACA2LR',['../group___c_m_s_i_s___device.html#ga423b12ab536a1c4fdb1ce63f645822a7',1,'ETH_TypeDef']]], - ['maca3hr_8',['MACA3HR',['../group___c_m_s_i_s___device.html#gad02ff09f7ce33f093ad04b84fee2bdec',1,'ETH_TypeDef']]], - ['maca3lr_9',['MACA3LR',['../group___c_m_s_i_s___device.html#ga2ba9f73c7fa756305d54a8f80872c6df',1,'ETH_TypeDef']]], - ['maccr_10',['MACCR',['../group___c_m_s_i_s___device.html#ga20acbcac1c35f66de94c9ff0e2ddc7b0',1,'ETH_TypeDef']]], - ['macdbgr_11',['MACDBGR',['../group___c_m_s_i_s___device.html#ga8f35b3865c1f5fce934c1d48b9a63442',1,'ETH_TypeDef']]], - ['macfcr_12',['MACFCR',['../group___c_m_s_i_s___device.html#ga12f62d3d3b9ee30c20c324b146e72795',1,'ETH_TypeDef']]], - ['macffr_13',['MACFFR',['../group___c_m_s_i_s___device.html#ga8ad4e3dbde1518ecde5d979c2a89a76a',1,'ETH_TypeDef']]], - ['machthr_14',['MACHTHR',['../group___c_m_s_i_s___device.html#ga121212bdb227106df681d24e5d896a4e',1,'ETH_TypeDef']]], - ['machtlr_15',['MACHTLR',['../group___c_m_s_i_s___device.html#ga1d34ab8e5c2041c00ba9526b3958099d',1,'ETH_TypeDef']]], - ['macimr_16',['MACIMR',['../group___c_m_s_i_s___device.html#gac42b829c02429cb9363563f7eb9d58ed',1,'ETH_TypeDef']]], - ['macmiiar_17',['MACMIIAR',['../group___c_m_s_i_s___device.html#ga9ea1e1c6615eb3bd70eb328dba65fc87',1,'ETH_TypeDef']]], - ['macmiidr_18',['MACMIIDR',['../group___c_m_s_i_s___device.html#ga87c7687c35332bf5ee86473043652146',1,'ETH_TypeDef']]], - ['macpmtcsr_19',['MACPMTCSR',['../group___c_m_s_i_s___device.html#gabbb2f4f89e7d8c3242365b4506e43217',1,'ETH_TypeDef']]], - ['macrocell_20itm_20',['Instrumentation Trace Macrocell (ITM)',['../group___c_m_s_i_s___i_t_m.html',1,'']]], - ['macros_21',['Core register bit field macros',['../group___c_m_s_i_s__core__bitfield.html',1,'']]], - ['macrwuffr_22',['MACRWUFFR',['../group___c_m_s_i_s___device.html#ga129dcc23d48588d5af7dd218b617933d',1,'ETH_TypeDef']]], - ['macsr_23',['MACSR',['../group___c_m_s_i_s___device.html#ga1173127526cca9128e409bc83c7729dc',1,'ETH_TypeDef']]], - ['macvlantr_24',['MACVLANTR',['../group___c_m_s_i_s___device.html#ga92ff1fe799bb33d13efbaa1195867781',1,'ETH_TypeDef']]], - ['main_25',['main',['../mcu__wrapper_8c.html#a840291bc02cba5474a4cb46a9b9566fe',1,'mcu_wrapper.c']]], - ['main_5fsimulator_26',['MAIN_SIMULATOR',['../group___m_a_i_n___s_i_m_u_l_a_t_o_r.html',1,'']]], - ['mask_27',['MASK',['../group___c_m_s_i_s___device.html#ga5c955643593b4aedbe9f84f054d26522',1,'SDIO_TypeDef']]], - ['mask0_28',['MASK0',['../group___c_m_s_i_s__core___debug_functions.html#ga84089e08ecf14b86f92c727a568ceac4',1,'DWT_Type']]], - ['mask1_29',['MASK1',['../group___c_m_s_i_s__core___debug_functions.html#ga6f663226a4f3409b0a73651b5a90b3af',1,'DWT_Type']]], - ['mask2_30',['MASK2',['../group___c_m_s_i_s__core___debug_functions.html#ga32213bf45fbe36e1823e69028f7edef2',1,'DWT_Type']]], - ['mask3_31',['MASK3',['../group___c_m_s_i_s__core___debug_functions.html#ga51e9ef8e2238e82f3b40aa2599397637',1,'DWT_Type']]], - ['matlab_32',['ЭмулÑтор STM Ð´Ð»Ñ MATLAB',['../md__f_1_2_work_2_projects_2_m_a_t_l_a_b_2matlab__stm__emulate_2_r_e_a_d_m_e.html#autotoc_md4',1,'']]], - ['matlab_20stm32_20emulator_33',['MATLAB STM32 EMULATOR',['../md__f_1_2_work_2_projects_2_m_a_t_l_a_b_2matlab__stm__emulate_2_r_e_a_d_m_e.html',1,'']]], - ['mcr_34',['MCR',['../group___c_m_s_i_s___device.html#ga27af4e9f888f0b7b1e8da7e002d98798',1,'CAN_TypeDef']]], - ['mcu_2ec_35',['MCU.c',['../_m_c_u_8c.html',1,'']]], - ['mcu_5fapp_5fthread_36',['MCU_App_Thread',['../mcu__wrapper_8c.html#a1ea76a95b9b28061fb34ece9f6f0a85f',1,'mcu_wrapper.c']]], - ['mcu_5fcortex_5fmem_37',['MCU_CORTEX_MEM',['../group___c_m_s_i_s__core__base.html#ga47e1165d2b04b61b504f52b9f4782708',1,'MCU_CORTEX_MEM: stm32f4xx_matlab_conf.c'],['../group___c_m_s_i_s__core__base.html#ga47e1165d2b04b61b504f52b9f4782708',1,'MCU_CORTEX_MEM: stm32f4xx_matlab_conf.c']]], - ['mcu_5fcortexmemorytypedef_38',['MCU_CortexMemoryTypeDef',['../group___c_m_s_i_s__core__base.html#ga2283564fd240ac8b420f104dc381ce94',1,'core_cm4_matlab.h']]], - ['mcu_5fmem_39',['MCU_MEM',['../group___peripheral__memory__map.html#gaf157a51d290d1383d493a6a2fe0241fc',1,'MCU_MEM: stm32f4xx_matlab_conf.c'],['../group___peripheral__memory__map.html#gaf157a51d290d1383d493a6a2fe0241fc',1,'MCU_MEM: stm32f4xx_matlab_conf.c']]], - ['mcu_5fmem_5fend_40',['MCU_MEM_END',['../group___peripheral__memory__map.html#ga4ddc1e9172ba6fe724328595a3fadcf2',1,'stm32f407xx_matlab.h']]], - ['mcu_5fmemorytypedef_41',['MCU_MemoryTypeDef',['../group___peripheral__memory__map.html#ga304d35aeeebef1445af976d8a5248d57',1,'stm32f407xx_matlab.h']]], - ['mcu_5fperiph_5fsimulation_42',['MCU_Periph_Simulation',['../mcu__wrapper_8c.html#accdef5b45f3d1646f248304e02b00e54',1,'MCU_Periph_Simulation(void): mcu_wrapper.c'],['../mcu__wrapper__conf_8h.html#accdef5b45f3d1646f248304e02b00e54',1,'MCU_Periph_Simulation(void): mcu_wrapper.c']]], - ['mcu_5freadinputs_43',['MCU_readInputs',['../mcu__wrapper_8c.html#a15045e0feba8ddf08e20958fd1e36cd5',1,'MCU_readInputs(SimStruct *S): mcu_wrapper.c'],['../mcu__wrapper__conf_8h.html#abc7d8087f585d1d627093e18df213512',1,'MCU_readInputs(real_T *in): mcu_wrapper_conf.h']]], - ['mcu_5fstep_5fsimulation_44',['MCU_Step_Simulation',['../mcu__wrapper_8c.html#ad3c4ea41584d0367dfbfb697f5e57456',1,'MCU_Step_Simulation(SimStruct *S, time_T time): mcu_wrapper.c'],['../mcu__wrapper__conf_8h.html#ad3c4ea41584d0367dfbfb697f5e57456',1,'MCU_Step_Simulation(SimStruct *S, time_T time): mcu_wrapper.c']]], - ['mcu_5fwrapper_45',['MCU_WRAPPER',['../group___m_c_u___w_r_a_p_p_e_r.html',1,'']]], - ['mcu_5fwrapper_2ec_46',['mcu_wrapper.c',['../mcu__wrapper_8c.html',1,'']]], - ['mcu_5fwrapper_5fconf_2eh_47',['mcu_wrapper_conf.h',['../mcu__wrapper__conf_8h.html',1,'']]], - ['mcu_5fwriteoutputs_48',['MCU_writeOutputs',['../mcu__wrapper_8c.html#ad6b7bb9233d746d7709276f9ea1914c2',1,'MCU_writeOutputs(SimStruct *S): mcu_wrapper.c'],['../mcu__wrapper__conf_8h.html#a823c4fab88e5ef9b283cee495b2524ad',1,'MCU_writeOutputs(real_T *disc): mcu_wrapper_conf.h']]], - ['mdl_5fcheck_5fparameters_49',['MDL_CHECK_PARAMETERS',['../_m_c_u_8c.html#a4936bd489281a5a9b9a2e081de0f003e',1,'MCU.c']]], - ['mdl_5fstart_50',['MDL_START',['../_m_c_u_8c.html#ac032abbf580c891fb0c11e63e9bc668a',1,'MCU.c']]], - ['mdl_5fupdate_51',['MDL_UPDATE',['../_m_c_u_8c.html#a7556dbbf5cb7f9946d3e39bcda40c63b',1,'MCU.c']]], - ['memorymanagement_5firqn_52',['MemoryManagement_IRQn',['../group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a33ff1cf7098de65d61b6354fee6cd5aa',1,'stm32f407xx_matlab.h']]], - ['memrmp_53',['MEMRMP',['../group___c_m_s_i_s___device.html#gab36c409d0a009e3ce5a89ac55d3ff194',1,'SYSCFG_TypeDef']]], - ['mexing_2em_54',['mexing.m',['../mexing_8m.html',1,'']]], - ['misr_55',['MISR',['../group___c_m_s_i_s___device.html#ga524e134cec519206cb41d0545e382978',1,'DCMI_TypeDef']]], - ['mmccr_56',['MMCCR',['../group___c_m_s_i_s___device.html#gad57490cb3a07132702f96d8b5d547c89',1,'ETH_TypeDef']]], - ['mmcrfaecr_57',['MMCRFAECR',['../group___c_m_s_i_s___device.html#ga65bb525a3f4d3ee131f9a7ed899d5eef',1,'ETH_TypeDef']]], - ['mmcrfcecr_58',['MMCRFCECR',['../group___c_m_s_i_s___device.html#gaff6eeec1afa983f153ff0786c8902d43',1,'ETH_TypeDef']]], - ['mmcrgufcr_59',['MMCRGUFCR',['../group___c_m_s_i_s___device.html#ga6ff264b60a3b40f40d136288e5ec5ba8',1,'ETH_TypeDef']]], - ['mmcrimr_60',['MMCRIMR',['../group___c_m_s_i_s___device.html#ga63872a3017c14a869c647123573dd002',1,'ETH_TypeDef']]], - ['mmcrir_61',['MMCRIR',['../group___c_m_s_i_s___device.html#gaea29ac183c979d0cb95ad3781fe9ed91',1,'ETH_TypeDef']]], - ['mmctgfcr_62',['MMCTGFCR',['../group___c_m_s_i_s___device.html#ga71d932b554a5548e5d85ed81e58c1ed0',1,'ETH_TypeDef']]], - ['mmctgfmsccr_63',['MMCTGFMSCCR',['../group___c_m_s_i_s___device.html#ga50c8425cf8d27268b3272ace0a224a94',1,'ETH_TypeDef']]], - ['mmctgfsccr_64',['MMCTGFSCCR',['../group___c_m_s_i_s___device.html#ga23970354d69354ab78165e76afd6c2f7',1,'ETH_TypeDef']]], - ['mmctimr_65',['MMCTIMR',['../group___c_m_s_i_s___device.html#ga18e294dd2625a93ebf2aab9f2b3c4911',1,'ETH_TypeDef']]], - ['mmctir_66',['MMCTIR',['../group___c_m_s_i_s___device.html#ga614e0b81fce7cf218a357f8a0a3de7b8',1,'ETH_TypeDef']]], - ['mmfar_67',['MMFAR',['../group___c_m_s_i_s__core___debug_functions.html#gae9d94d186615d57d38c9253cb842d244',1,'SCB_Type']]], - ['mmfr_68',['MMFR',['../group___c_m_s_i_s__core___debug_functions.html#gab6c914b579d22d7eb86d0e3d9a5fde71',1,'SCB_Type']]], - ['moder_69',['MODER',['../group___c_m_s_i_s___device.html#ga2b671a94c63a612f81e0e9de8152d01c',1,'GPIO_TypeDef']]], - ['modify_5freg_70',['MODIFY_REG',['../group___exported__macro.html#ga6553c99f510c3bab8cc0a91602053247',1,'stm32f4xx.h']]], - ['msr_71',['MSR',['../group___c_m_s_i_s___device.html#gacdd4c1b5466be103fb2bb2a225b1d3a9',1,'CAN_TypeDef']]], - ['mvfr0_72',['MVFR0',['../group___c_m_s_i_s__core___debug_functions.html#ga9b0103b438c8922eaea5624f71afbbc8',1,'FPU_Type']]], - ['mvfr1_73',['MVFR1',['../group___c_m_s_i_s__core___debug_functions.html#ga0a610dc4212de3ce1ad62e9afa76c728',1,'FPU_Type']]] + ['periph_5fbase_0',['PERIPH_BASE',['../struct__memory.html#a535f5001cfe9967fb7040cd5b081d944',1,'_memory::PERIPH_BASE'],['../group___peripheral__memory__map.html#ga9171f49478fa86d932f89e78e73b88b0',1,'PERIPH_BASE: stm32f407xx_matlab_memory.h']]], + ['periph_5fbase_5fshift_1',['PERIPH_BASE_SHIFT',['../group___peripheral__memory__map.html#ga1294c8e27eb23b591c5195504e4dfd23',1,'stm32f407xx_matlab_memory.h']]], + ['periph_5fbb_5fbase_2',['PERIPH_BB_BASE',['../struct__memory.html#a9fbcd0d73c2b2229b9f95743f280382c',1,'_memory::PERIPH_BB_BASE'],['../group___peripheral__memory__map.html#gaed7efc100877000845c236ccdc9e144a',1,'PERIPH_BB_BASE: stm32f407xx_matlab_memory.h']]], + ['periph_5fbb_5fbase_5fshift_3',['PERIPH_BB_BASE_SHIFT',['../group___peripheral__memory__map.html#ga33c4df718741b5cb60ca3fffe8969672',1,'stm32f407xx_matlab_memory.h']]], + ['periph_5fbb_5fsize_4',['PERIPH_BB_SIZE',['../group___peripheral__memory__map.html#ga16c53e8ec3bcf87a7d170220d774956c',1,'stm32f407xx_matlab_memory.h']]], + ['periph_5fsize_5',['PERIPH_SIZE',['../group___peripheral__memory__map.html#gaf91d23524f40a61d32fea568949043d0',1,'stm32f407xx_matlab_memory.h']]], + ['peripheral_20memory_20map_6',['Peripheral Memory Map',['../group___peripheral__memory__map.html',1,'']]], + ['periphs_20variables_20for_20debugging_7',['Periphs Variables for Debugging',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html',1,'']]], + ['port_5fnumb_8',['PORT_NUMB',['../group___w_r_a_p_p_e_r___c_o_n_f.html#gab59d8303ff443409a05cef11e3e7176e',1,'mcu_wrapper_conf.h']]], + ['port_5fwidth_9',['PORT_WIDTH',['../group___w_r_a_p_p_e_r___c_o_n_f.html#ga80d9b6ce1525c1148d94c021f0b8c83e',1,'mcu_wrapper_conf.h']]], + ['pwr_10',['pwr',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#gaba54a48e7552e8a1301cc87cdfcacfee',1,'stm32f4xx_periph_registers.c']]] ]; diff --git a/DOCS/html/search/all_e.js b/DOCS/html/search/all_e.js index f32e979..7169cf1 100644 --- a/DOCS/html/search/all_e.js +++ b/DOCS/html/search/all_e.js @@ -1,34 +1,10 @@ var searchData= [ - ['n_0',['N',['../group___c_m_s_i_s__core___debug_functions.html#gabae0610bc2a97bbf7f689e953e0b451f',1,'APSR_Type::N'],['../group___c_m_s_i_s__core___debug_functions.html#gabae0610bc2a97bbf7f689e953e0b451f',1,'APSR_Type::@0::N'],['../group___c_m_s_i_s__core___debug_functions.html#gabae0610bc2a97bbf7f689e953e0b451f',1,'xPSR_Type::N'],['../group___c_m_s_i_s__core___debug_functions.html#gabae0610bc2a97bbf7f689e953e0b451f',1,'xPSR_Type::@2::N']]], - ['native_5fwhile_1',['native_while',['../mcu__wrapper__conf_8h.html#abaad5b5eb9243ab531775be5eda6ee02',1,'mcu_wrapper_conf.h']]], - ['ndtr_2',['NDTR',['../group___c_m_s_i_s___device.html#gaf60258ad5a25addc1e8969665d0c1731',1,'DMA_Stream_TypeDef']]], - ['nested_20vectored_20interrupt_20controller_20nvic_3',['Nested Vectored Interrupt Controller (NVIC)',['../group___c_m_s_i_s___n_v_i_c.html',1,'']]], - ['nonmaskableint_5firqn_4',['NonMaskableInt_IRQn',['../group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8ade177d9c70c89e084093024b932a4e30',1,'stm32f407xx_matlab.h']]], - ['not_20in_20scb_20scnscb_5',['System Controls not in SCB (SCnSCB)',['../group___c_m_s_i_s___s_cn_s_c_b.html',1,'']]], - ['nparams_6',['NPARAMS',['../group___w_r_a_p_p_e_r___c_o_n_f.html#gae468832efa6adf5e9a96cabd8f878b47',1,'mcu_wrapper_conf.h']]], - ['npriv_7',['nPRIV',['../group___c_m_s_i_s__core___debug_functions.html#ga2a6e513e8a6bf4e58db169e312172332',1,'CONTROL_Type::nPRIV'],['../group___c_m_s_i_s__core___debug_functions.html#ga2a6e513e8a6bf4e58db169e312172332',1,'CONTROL_Type::@3::nPRIV']]], - ['nvic_8',['NVIC',['../group___c_m_s_i_s___n_v_i_c.html',1,'Nested Vectored Interrupt Controller (NVIC)'],['../group___c_m_s_i_s__core__base.html#gac8e97e8ce56ae9f57da1363a937f8a17',1,'NVIC: core_cm4_matlab.h']]], - ['nvic_20functions_9',['NVIC Functions',['../group___c_m_s_i_s___core___n_v_i_c_functions.html',1,'']]], - ['nvic_5fbase_10',['NVIC_BASE',['../group___c_m_s_i_s__core__base.html#gaa0288691785a5f868238e0468b39523d',1,'core_cm4_matlab.h']]], - ['nvic_5fclearpendingirq_11',['NVIC_ClearPendingIRQ',['../group___c_m_s_i_s___core___n_v_i_c_functions.html#ga590cf113000a079b1f0ea3dcd5b5316c',1,'core_cm4_matlab.h']]], - ['nvic_5fdecodepriority_12',['NVIC_DecodePriority',['../group___c_m_s_i_s___core___n_v_i_c_functions.html#ga3387607fd8a1a32cccd77d2ac672dd96',1,'core_cm4_matlab.h']]], - ['nvic_5fdisableirq_13',['NVIC_DisableIRQ',['../group___c_m_s_i_s___core___n_v_i_c_functions.html#ga73b4e251f59cab4e9a5e234aac02ae57',1,'core_cm4_matlab.h']]], - ['nvic_5fenableirq_14',['NVIC_EnableIRQ',['../group___c_m_s_i_s___core___n_v_i_c_functions.html#ga57b3064413dbc7459d9646020fdd8bef',1,'core_cm4_matlab.h']]], - ['nvic_5fencodepriority_15',['NVIC_EncodePriority',['../group___c_m_s_i_s___core___n_v_i_c_functions.html#gadb94ac5d892b376e4f3555ae0418ebac',1,'core_cm4_matlab.h']]], - ['nvic_5fgetactive_16',['NVIC_GetActive',['../group___c_m_s_i_s___core___n_v_i_c_functions.html#ga58ad3f352f832235ab3b192ff4745320',1,'core_cm4_matlab.h']]], - ['nvic_5fgetenableirq_17',['NVIC_GetEnableIRQ',['../group___c_m_s_i_s___core___n_v_i_c_functions.html#ga857de13232ec65dd15087eaa15bc4a69',1,'core_cm4_matlab.h']]], - ['nvic_5fgetpendingirq_18',['NVIC_GetPendingIRQ',['../group___c_m_s_i_s___core___n_v_i_c_functions.html#gac608957a239466e9e0cbc30aa64feb3b',1,'core_cm4_matlab.h']]], - ['nvic_5fgetpriority_19',['NVIC_GetPriority',['../group___c_m_s_i_s___core___n_v_i_c_functions.html#gaf59b9d0a791d2157abb319753953eceb',1,'core_cm4_matlab.h']]], - ['nvic_5fgetprioritygrouping_20',['NVIC_GetPriorityGrouping',['../group___c_m_s_i_s___core___n_v_i_c_functions.html#ga4eeb9214f2264fc23c34ad5de2d3fa11',1,'core_cm4_matlab.h']]], - ['nvic_5fgetvector_21',['NVIC_GetVector',['../group___c_m_s_i_s___core___n_v_i_c_functions.html#ga955eb1c33a3dcc62af11a8385e8c0fc8',1,'core_cm4_matlab.h']]], - ['nvic_5fsetpendingirq_22',['NVIC_SetPendingIRQ',['../group___c_m_s_i_s___core___n_v_i_c_functions.html#ga2b47e2e52cf5c48a5c3348636434b3ac',1,'core_cm4_matlab.h']]], - ['nvic_5fsetpriority_23',['NVIC_SetPriority',['../group___c_m_s_i_s___core___n_v_i_c_functions.html#gae0e9d0e2f7b6133828c71b57d4941c35',1,'core_cm4_matlab.h']]], - ['nvic_5fsetprioritygrouping_24',['NVIC_SetPriorityGrouping',['../group___c_m_s_i_s___core___n_v_i_c_functions.html#ga0e798d5aec68cdd8263db86a76df788f',1,'core_cm4_matlab.h']]], - ['nvic_5fsetvector_25',['NVIC_SetVector',['../group___c_m_s_i_s___core___n_v_i_c_functions.html#ga804af63bb4c4c317387897431814775d',1,'core_cm4_matlab.h']]], - ['nvic_5fstir_5fintid_5fmsk_26',['NVIC_STIR_INTID_Msk',['../group___c_m_s_i_s___n_v_i_c.html#gae4060c4dfcebb08871ca4244176ce752',1,'core_cm4_matlab.h']]], - ['nvic_5fstir_5fintid_5fpos_27',['NVIC_STIR_INTID_Pos',['../group___c_m_s_i_s___n_v_i_c.html#ga9eebe495e2e48d302211108837a2b3e8',1,'core_cm4_matlab.h']]], - ['nvic_5fsystemreset_28',['NVIC_SystemReset',['../group___c_m_s_i_s___core___n_v_i_c_functions.html#ga6aa0367d3642575610476bf0366f0c48',1,'core_cm4_matlab.h']]], - ['nvic_5ftype_29',['NVIC_Type',['../struct_n_v_i_c___type.html',1,'']]], - ['nvic_5fuser_5firq_5foffset_30',['NVIC_USER_IRQ_OFFSET',['../group___c_m_s_i_s___core___n_v_i_c_functions.html#ga8045d905a5ca57437d8e6f71ffcb6df5',1,'core_cm4_matlab.h']]] + ['rcc_0',['rcc',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga33f5f83bbcee4994fef4f29192860875',1,'stm32f4xx_periph_registers.c']]], + ['rcc_20simulator_1',['RCC Simulator',['../group___r_c_c___s_i_m_u_l_a_t_o_r.html',1,'']]], + ['readme_2emd_2',['README.md',['../_r_e_a_d_m_e_8md.html',1,'']]], + ['reload_3',['RELOAD',['../struct_t_i_m___sim.html#a1798863b8849972c8e0cf75abbbd116b',1,'TIM_Sim']]], + ['rng_4',['rng',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#gae5244ff1d33b8f1c69abb81fda62b538',1,'stm32f4xx_periph_registers.c']]], + ['rtc_5',['rtc',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga423742450422a8873970b076a7e25028',1,'stm32f4xx_periph_registers.c']]], + ['run_5fmex_2ebat_6',['run_mex.bat',['../run__mex_8bat.html',1,'']]] ]; diff --git a/DOCS/html/search/all_f.js b/DOCS/html/search/all_f.js index 3cc1287..8fd6ff1 100644 --- a/DOCS/html/search/all_f.js +++ b/DOCS/html/search/all_f.js @@ -1,33 +1,65 @@ var searchData= [ - ['oar1_0',['OAR1',['../group___c_m_s_i_s___device.html#ga08b4be0d626a00f26bc295b379b3bba6',1,'I2C_TypeDef']]], - ['oar2_1',['OAR2',['../group___c_m_s_i_s___device.html#gab5c57ffed0351fa064038939a6c0bbf6',1,'I2C_TypeDef']]], - ['oc1_5fgpiox_2',['OC1_GPIOx',['../struct_channels___sim.html#a48f9b22f7e44d1b56aa793c2344e06d1',1,'Channels_Sim']]], - ['oc1_5fpin_5fshift_3',['OC1_PIN_SHIFT',['../struct_channels___sim.html#a2d558fbd100d8052eb0e235ad9b1edfe',1,'Channels_Sim']]], - ['oc1ref_4',['OC1REF',['../struct_channels___sim.html#aae6762f43d55e99c3076c9f7e5cda5d9',1,'Channels_Sim']]], - ['oc2_5fgpiox_5',['OC2_GPIOx',['../struct_channels___sim.html#a095026a66ff13e090dae52ee17263f2d',1,'Channels_Sim']]], - ['oc2_5fpin_5fshift_6',['OC2_PIN_SHIFT',['../struct_channels___sim.html#ac2fdf8c4e985eee4ab2e6c82251c12cf',1,'Channels_Sim']]], - ['oc2ref_7',['OC2REF',['../struct_channels___sim.html#aa038da4ce5b26f3d86cda283a9cd749e',1,'Channels_Sim']]], - ['oc3_5fgpiox_8',['OC3_GPIOx',['../struct_channels___sim.html#a7d239c94641795d3caf5c28f8b7cc68d',1,'Channels_Sim']]], - ['oc3_5fpin_5fshift_9',['OC3_PIN_SHIFT',['../struct_channels___sim.html#ac15bcebfa2102716c5b6a4f80b2d51ab',1,'Channels_Sim']]], - ['oc3ref_10',['OC3REF',['../struct_channels___sim.html#abbea161f1b685a5d353d453fc9b56284',1,'Channels_Sim']]], - ['oc4_5fgpiox_11',['OC4_GPIOx',['../struct_channels___sim.html#a851558373b04d1a8a5dbb3c0da9279d8',1,'Channels_Sim']]], - ['oc4_5fpin_5fshift_12',['OC4_PIN_SHIFT',['../struct_channels___sim.html#aa87736409f5ca9986200fcb480920c5b',1,'Channels_Sim']]], - ['oc4ref_13',['OC4REF',['../struct_channels___sim.html#a1c6c166d70bfe9597717f6892da4f446',1,'Channels_Sim']]], - ['odr_14',['ODR',['../group___c_m_s_i_s___device.html#gabff7fffd2b5a718715a130006590c75c',1,'GPIO_TypeDef']]], - ['optcr_15',['OPTCR',['../group___c_m_s_i_s___device.html#gacfef9b6d7da4271943edc04d7dfdf595',1,'FLASH_TypeDef']]], - ['optcr1_16',['OPTCR1',['../group___c_m_s_i_s___device.html#ga1dddf235f246a1d4e7e5084cd51e2dd0',1,'FLASH_TypeDef']]], - ['optkeyr_17',['OPTKEYR',['../group___c_m_s_i_s___device.html#gafc4900646681dfe1ca43133d376c4423',1,'FLASH_TypeDef']]], - ['or_18',['OR',['../group___c_m_s_i_s___device.html#ga75ade4a9b3d40781fd80ce3e6589e98b',1,'TIM_TypeDef']]], - ['ospeedr_19',['OSPEEDR',['../group___c_m_s_i_s___device.html#ga328d16cc6213783ede54e4059ffd50a3',1,'GPIO_TypeDef']]], - ['otg_5ffs_5firqn_20',['OTG_FS_IRQn',['../group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8aa60a30b7ef03446a46fd72e084911f7e',1,'stm32f407xx_matlab.h']]], - ['otg_5ffs_5fwkup_5firqn_21',['OTG_FS_WKUP_IRQn',['../group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8aa612f35c4440359c35acbaa3c1458c5f',1,'stm32f407xx_matlab.h']]], - ['otg_5fhs_5fep1_5fin_5firqn_22',['OTG_HS_EP1_IN_IRQn',['../group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a1b040a7f76278a73cf5ea4c51f1be047',1,'stm32f407xx_matlab.h']]], - ['otg_5fhs_5fep1_5fout_5firqn_23',['OTG_HS_EP1_OUT_IRQn',['../group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a60b6cc4b6dbeca39e29a475d26c9e080',1,'stm32f407xx_matlab.h']]], - ['otg_5fhs_5firqn_24',['OTG_HS_IRQn',['../group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8aad2d5e47d27fe3a02f7059b20bb729c0',1,'stm32f407xx_matlab.h']]], - ['otg_5fhs_5fwkup_5firqn_25',['OTG_HS_WKUP_IRQn',['../group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a9e5c9d81dd3985a88094f8158c0f0267',1,'stm32f407xx_matlab.h']]], - ['otyper_26',['OTYPER',['../group___c_m_s_i_s___device.html#ga9543592bda60cb5261075594bdeedac9',1,'GPIO_TypeDef']]], - ['out_5fport_5fnumb_27',['OUT_PORT_NUMB',['../group___w_r_a_p_p_e_r___c_o_n_f.html#ga9fa483e805a6570c4793b1e0ff9719ac',1,'mcu_wrapper_conf.h']]], - ['out_5fport_5fwidth_28',['OUT_PORT_WIDTH',['../group___w_r_a_p_p_e_r___c_o_n_f.html#gac90b37686b0abfe29835c9632310897a',1,'mcu_wrapper_conf.h']]], - ['overflow_5fcheck_29',['Overflow_Check',['../group___t_i_m___s_i_m_u_l_a_t_o_r.html#ga05b798408f2179ae27731f231cf4b620',1,'Overflow_Check(TIM_TypeDef *TIMx, struct TIM_Sim *TIMS): stm32f4xx_matlab_tim.c'],['../group___t_i_m___s_i_m_u_l_a_t_o_r.html#ga05b798408f2179ae27731f231cf4b620',1,'Overflow_Check(TIM_TypeDef *TIMx, struct TIM_Sim *TIMS): stm32f4xx_matlab_tim.c']]] + ['s_20function_20funtions_0',['S-Function funtions',['../group___w_r_a_p_p_e_r___s_f_u_n_c.html',1,'']]], + ['s_5ffunction_5flevel_1',['S_FUNCTION_LEVEL',['../group___w_r_a_p_p_e_r___s_f_u_n_c.html#ga9a4ab27953070e39249f3fad28e93749',1,'MCU.c']]], + ['s_5ffunction_5fname_2',['S_FUNCTION_NAME',['../group___w_r_a_p_p_e_r___s_f_u_n_c.html#ga0f61df833e166c743295eebf43f0b142',1,'MCU.c']]], + ['scb_3',['SCB',['../group___c_m_s_i_s__core__base.html#gaaaf6477c2bde2f00f99e3c2fd1060b01',1,'stm32f407xx_matlab_memory.h']]], + ['scb_5fbase_4',['SCB_BASE',['../group___c_m_s_i_s__core__base.html#gad55a7ddb8d4b2398b0c1cfec76c0d9fd',1,'stm32f407xx_matlab_memory.h']]], + ['scnscb_5',['SCnSCB',['../group___c_m_s_i_s__core__base.html#ga9fe0cd2eef83a8adad94490d9ecca63f',1,'stm32f407xx_matlab_memory.h']]], + ['scs_5fbase_6',['SCS_BASE',['../group___c_m_s_i_s__core__base.html#ga3c14ed93192c8d9143322bbf77ebf770',1,'stm32f407xx_matlab_memory.h']]], + ['scs_5fbase_5fshift_7',['SCS_BASE_SHIFT',['../group___c_m_s_i_s__core__base.html#ga48d67e0906624018a8dc1ff5409f31ca',1,'stm32f407xx_matlab_memory.h']]], + ['sdio_8',['sdio',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga8b6edf2e7d9debf95d77d172c8c32cb7',1,'stm32f4xx_periph_registers.c']]], + ['set_5fflag_5fif_5fits_5fexpected_9',['Set_Flag_If_Its_Expected',['../group___r_c_c___s_i_m_u_l_a_t_o_r.html#gadf8f9d228ec9091df7d092a298f11b17',1,'stm32f4xx_matlab_rcc.h']]], + ['sfunc_5fto_5fgpio_10',['SFUNC_to_GPIO',['../group___g_p_i_o___s_i_m_u_l_a_t_o_r.html#ga368334de2e425bc656526d2f42671454',1,'SFUNC_to_GPIO(real_T *in): stm32f4xx_matlab_gpio.c'],['../group___g_p_i_o___s_i_m_u_l_a_t_o_r.html#ga368334de2e425bc656526d2f42671454',1,'SFUNC_to_GPIO(real_T *out_buff): stm32f4xx_matlab_gpio.c']]], + ['sim_5f_5fmcuhandletypedef_11',['SIM__MCUHandleTypeDef',['../struct_s_i_m_____m_c_u_handle_type_def.html',1,'']]], + ['sim_5fdeinitialize_5fsimulation_12',['SIM_deInitialize_Simulation',['../group___m_c_u___w_r_a_p_p_e_r.html#ga6f04b162923bada308d9668743425b92',1,'SIM_deInitialize_Simulation(void): mcu_wrapper.c'],['../group___m_c_u___w_r_a_p_p_e_r.html#ga6f04b162923bada308d9668743425b92',1,'SIM_deInitialize_Simulation(void): mcu_wrapper.c']]], + ['sim_5finitialize_5fsimulation_13',['SIM_Initialize_Simulation',['../group___m_c_u___w_r_a_p_p_e_r.html#ga54429d6d68b1d72ce16bab374e3ffa08',1,'SIM_Initialize_Simulation(void): mcu_wrapper.c'],['../group___m_c_u___w_r_a_p_p_e_r.html#ga54429d6d68b1d72ce16bab374e3ffa08',1,'SIM_Initialize_Simulation(void): mcu_wrapper.c']]], + ['sim_5fsample_5ftime_14',['SIM_Sample_Time',['../struct_s_i_m_____m_c_u_handle_type_def.html#ab19a05224f30fab089c5d5e18fdcca36',1,'SIM__MCUHandleTypeDef']]], + ['sim_5fwhile_15',['sim_while',['../group___m_c_u___w_r_a_p_p_e_r.html#ga1fef2893362ee1f5032b523ff8c7fd9d',1,'mcu_wrapper_conf.h']]], + ['sim_5fwriteoutput_16',['SIM_writeOutput',['../group___m_c_u___w_r_a_p_p_e_r.html#gad38bfad0ee1e186c0663565abb6bc71a',1,'mcu_wrapper_conf.h']]], + ['sim_5fwriteoutputs_17',['SIM_writeOutputs',['../mcu__wrapper_8c.html#a47b40a9825bcaeb3a1dfba8b27a0be3f',1,'mcu_wrapper.c']]], + ['simulate_5ftims_18',['Simulate_TIMs',['../group___t_i_m___s_i_m_u_l_a_t_o_r.html#ga3128cf64eeea541a8e25a72ce10da335',1,'Simulate_TIMs(void): stm32f4xx_matlab_tim.c'],['../group___t_i_m___s_i_m_u_l_a_t_o_r.html#ga3128cf64eeea541a8e25a72ce10da335',1,'Simulate_TIMs(void): stm32f4xx_matlab_tim.c']]], + ['simulation_19',['STM32 Simulation',['../group___s_t_m___s_i_m_u_l_a_t_i_o_n.html',1,'']]], + ['simulator_20',['Simulator',['../group___g_p_i_o___s_i_m_u_l_a_t_o_r.html',1,'GPIO Simulator'],['../group___r_c_c___s_i_m_u_l_a_t_o_r.html',1,'RCC Simulator'],['../group___m_a_i_n___s_i_m_u_l_a_t_o_r.html',1,'STM32 Simulator'],['../group___t_i_m___s_i_m_u_l_a_t_o_r.html',1,'TIM Simulator']]], + ['simulator_20configuration_21',['Simulator Configuration',['../group___s_i_m_u_l_a_t_o_r___c_o_n_f.html',1,'']]], + ['slave_5fchannels_22',['Slave_Channels',['../stm32f4xx__matlab__tim_8c.html#a66e48ba3c30d98536e05b7f5435e9828',1,'stm32f4xx_matlab_tim.c']]], + ['slave_5fmode_5fcheck_5fsource_23',['Slave_Mode_Check_Source',['../group___t_i_m___s_i_m_u_l_a_t_o_r.html#ga60fe7ff05dcbc30ca3c35aa08e87de21',1,'Slave_Mode_Check_Source(TIM_TypeDef *TIMx): stm32f4xx_matlab_tim.c'],['../group___t_i_m___s_i_m_u_l_a_t_o_r.html#ga60fe7ff05dcbc30ca3c35aa08e87de21',1,'Slave_Mode_Check_Source(TIM_TypeDef *TIMx): stm32f4xx_matlab_tim.c']]], + ['slavechannels_24',['SlaveChannels',['../struct_slave_channels.html',1,'']]], + ['spi1_25',['spi1',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga8cc3430b6591549759eb42cc2004a889',1,'stm32f4xx_periph_registers.c']]], + ['spi2_26',['spi2',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#gaafd9bde301b8cacea574ec4eea0e474f',1,'stm32f4xx_periph_registers.c']]], + ['spi3_27',['spi3',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga050e08b3b630957cd79c0e69968308bd',1,'stm32f4xx_periph_registers.c']]], + ['sram1_5fbase_28',['SRAM1_BASE',['../struct__memory.html#ac7c83f52956da4c75f4946348f7bfa1a',1,'_memory::SRAM1_BASE'],['../group___peripheral__memory__map.html#ga7d0fbfb8894012dbbb96754b95e562cd',1,'SRAM1_BASE: stm32f407xx_matlab_memory.h']]], + ['sram1_5fbase_5fshift_29',['SRAM1_BASE_SHIFT',['../group___peripheral__memory__map.html#gac53e3a39a0ebd3520aaa373ae44ff838',1,'stm32f407xx_matlab_memory.h']]], + ['sram1_5fbb_5fbase_30',['SRAM1_BB_BASE',['../struct__memory.html#ac88d0add27755615a9390fec8c64dafc',1,'_memory::SRAM1_BB_BASE'],['../group___peripheral__memory__map.html#gac4c4f61082e4b168f29d9cf97dc3ca5c',1,'SRAM1_BB_BASE: stm32f407xx_matlab_memory.h']]], + ['sram1_5fbb_5fbase_5fshift_31',['SRAM1_BB_BASE_SHIFT',['../group___peripheral__memory__map.html#ga9d4c99653d22992b3b4b1537ade15d21',1,'stm32f407xx_matlab_memory.h']]], + ['sram1_5fbb_5fsize_32',['SRAM1_BB_SIZE',['../group___peripheral__memory__map.html#ga4d759a2722aeeb47a81dd047d4e1790e',1,'stm32f407xx_matlab_memory.h']]], + ['sram1_5fsize_33',['SRAM1_SIZE',['../group___peripheral__memory__map.html#gacf1c7f7eb345f8e1b617fd1b16320111',1,'stm32f407xx_matlab_memory.h']]], + ['sram2_5fbase_34',['SRAM2_BASE',['../struct__memory.html#a57bfa1d7c82d97792cbb6c2d366dd48d',1,'_memory::SRAM2_BASE'],['../group___peripheral__memory__map.html#gadbb42a3d0a8a90a79d2146e4014241b1',1,'SRAM2_BASE: stm32f407xx_matlab_memory.h']]], + ['sram2_5fbase_5fshift_35',['SRAM2_BASE_SHIFT',['../group___peripheral__memory__map.html#gaff8892343768799209d59c2c33848222',1,'stm32f407xx_matlab_memory.h']]], + ['sram2_5fbb_5fbase_36',['SRAM2_BB_BASE',['../struct__memory.html#a5db33a541cebb596c2976d4fc409a611',1,'_memory::SRAM2_BB_BASE'],['../group___peripheral__memory__map.html#gac33cb6edadf184ab9860d77089503922',1,'SRAM2_BB_BASE: stm32f407xx_matlab_memory.h']]], + ['sram2_5fbb_5fbase_5fshift_37',['SRAM2_BB_BASE_SHIFT',['../group___peripheral__memory__map.html#ga1654496a485d04270e2208afa8e4fd5c',1,'stm32f407xx_matlab_memory.h']]], + ['sram2_5fbb_5fsize_38',['SRAM2_BB_SIZE',['../group___peripheral__memory__map.html#ga146845582d93b1fa90c52f43f704c178',1,'stm32f407xx_matlab_memory.h']]], + ['sram2_5fsize_39',['SRAM2_SIZE',['../group___peripheral__memory__map.html#gad89e757d25db6160b1aedeb58fcdac09',1,'stm32f407xx_matlab_memory.h']]], + ['status_40',['status',['../mexing_8m.html#ab1dc10c44c3fef32dbb7508037a5a3d6',1,'mexing.m']]], + ['stm_20длÑ_20matlab_41',['ЭмулÑтор STM Ð´Ð»Ñ MATLAB',['../index.html#ÑмулÑтор-stm-длÑ-matlab',1,'']]], + ['stm32_42',['ОпиÑание Ñтуктуры ÑмулÑтора (пример Ð´Ð»Ñ STM32)',['../index.html#опиÑание-Ñтуктуры-ÑмулÑтора-пример-длÑ-stm32',1,'']]], + ['stm32_20emulator_43',['MATLAB STM32 EMULATOR',['../index.html',1,'']]], + ['stm32_20simulation_44',['STM32 Simulation',['../group___s_t_m___s_i_m_u_l_a_t_i_o_n.html',1,'']]], + ['stm32_20simulator_45',['STM32 Simulator',['../group___m_a_i_n___s_i_m_u_l_a_t_o_r.html',1,'']]], + ['stm32f407xx_5fmatlab_5fmemory_2eh_46',['stm32f407xx_matlab_memory.h',['../stm32f407xx__matlab__memory_8h.html',1,'']]], + ['stm32f4xx_5fmatlab_5fconf_2ec_47',['stm32f4xx_matlab_conf.c',['../stm32f4xx__matlab__conf_8c.html',1,'']]], + ['stm32f4xx_5fmatlab_5fconf_2eh_48',['stm32f4xx_matlab_conf.h',['../stm32f4xx__matlab__conf_8h.html',1,'']]], + ['stm32f4xx_5fmatlab_5fgpio_2ec_49',['stm32f4xx_matlab_gpio.c',['../stm32f4xx__matlab__gpio_8c.html',1,'']]], + ['stm32f4xx_5fmatlab_5fgpio_2eh_50',['stm32f4xx_matlab_gpio.h',['../stm32f4xx__matlab__gpio_8h.html',1,'']]], + ['stm32f4xx_5fmatlab_5frcc_2ec_51',['stm32f4xx_matlab_rcc.c',['../stm32f4xx__matlab__rcc_8c.html',1,'']]], + ['stm32f4xx_5fmatlab_5frcc_2eh_52',['stm32f4xx_matlab_rcc.h',['../stm32f4xx__matlab__rcc_8h.html',1,'']]], + ['stm32f4xx_5fmatlab_5ftim_2ec_53',['stm32f4xx_matlab_tim.c',['../stm32f4xx__matlab__tim_8c.html',1,'']]], + ['stm32f4xx_5fmatlab_5ftim_2eh_54',['stm32f4xx_matlab_tim.h',['../stm32f4xx__matlab__tim_8h.html',1,'']]], + ['stm32f4xx_5fperiph_5fregisters_2ec_55',['stm32f4xx_periph_registers.c',['../stm32f4xx__periph__registers_8c.html',1,'']]], + ['syscfg_56',['syscfg',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga973efd19b15b8e1452258c3a02fda513',1,'stm32f4xx_periph_registers.c']]], + ['systemclock_57',['SystemClock',['../group___w_r_a_p_p_e_r___c_o_n_f.html#ga6a1676e08289f73141f9fa8419311385',1,'mcu_wrapper.c']]], + ['systemclock_5fstep_58',['SystemClock_step',['../group___w_r_a_p_p_e_r___c_o_n_f.html#gae50392991204ce9a89dd9aa8bf43634f',1,'mcu_wrapper.c']]], + ['systemclockdouble_59',['SystemClockDouble',['../group___w_r_a_p_p_e_r___c_o_n_f.html#gaf1cb3ba542e380d1f12d30579598c48c',1,'mcu_wrapper.c']]], + ['systick_60',['SysTick',['../group___c_m_s_i_s__core__base.html#gacd96c53beeaff8f603fcda425eb295de',1,'stm32f407xx_matlab_memory.h']]], + ['systick_5fbase_61',['SysTick_BASE',['../group___c_m_s_i_s__core__base.html#ga58effaac0b93006b756d33209e814646',1,'stm32f407xx_matlab_memory.h']]] ]; diff --git a/DOCS/html/search/classes_1.js b/DOCS/html/search/classes_1.js index cb9c22f..2e94eb7 100644 --- a/DOCS/html/search/classes_1.js +++ b/DOCS/html/search/classes_1.js @@ -1,6 +1,4 @@ var searchData= [ - ['adc_5fcommon_5ftypedef_0',['ADC_Common_TypeDef',['../struct_a_d_c___common___type_def.html',1,'']]], - ['adc_5ftypedef_1',['ADC_TypeDef',['../struct_a_d_c___type_def.html',1,'']]], - ['apsr_5ftype_2',['APSR_Type',['../union_a_p_s_r___type.html',1,'']]] + ['channels_5fsim_0',['Channels_Sim',['../struct_channels___sim.html',1,'']]] ]; diff --git a/DOCS/html/search/classes_2.js b/DOCS/html/search/classes_2.js index e45f3be..40d4fa1 100644 --- a/DOCS/html/search/classes_2.js +++ b/DOCS/html/search/classes_2.js @@ -1,11 +1,5 @@ var searchData= [ - ['can_5ffifomailbox_5ftypedef_0',['CAN_FIFOMailBox_TypeDef',['../struct_c_a_n___f_i_f_o_mail_box___type_def.html',1,'']]], - ['can_5ffilterregister_5ftypedef_1',['CAN_FilterRegister_TypeDef',['../struct_c_a_n___filter_register___type_def.html',1,'']]], - ['can_5ftxmailbox_5ftypedef_2',['CAN_TxMailBox_TypeDef',['../struct_c_a_n___tx_mail_box___type_def.html',1,'']]], - ['can_5ftypedef_3',['CAN_TypeDef',['../struct_c_a_n___type_def.html',1,'']]], - ['channels_5fsim_4',['Channels_Sim',['../struct_channels___sim.html',1,'']]], - ['control_5ftype_5',['CONTROL_Type',['../union_c_o_n_t_r_o_l___type.html',1,'']]], - ['coredebug_5ftype_6',['CoreDebug_Type',['../struct_core_debug___type.html',1,'']]], - ['crc_5ftypedef_7',['CRC_TypeDef',['../struct_c_r_c___type_def.html',1,'']]] + ['sim_5f_5fmcuhandletypedef_0',['SIM__MCUHandleTypeDef',['../struct_s_i_m_____m_c_u_handle_type_def.html',1,'']]], + ['slavechannels_1',['SlaveChannels',['../struct_slave_channels.html',1,'']]] ]; diff --git a/DOCS/html/search/classes_3.js b/DOCS/html/search/classes_3.js index d806272..ce2649c 100644 --- a/DOCS/html/search/classes_3.js +++ b/DOCS/html/search/classes_3.js @@ -1,9 +1,4 @@ var searchData= [ - ['dac_5ftypedef_0',['DAC_TypeDef',['../struct_d_a_c___type_def.html',1,'']]], - ['dbgmcu_5ftypedef_1',['DBGMCU_TypeDef',['../struct_d_b_g_m_c_u___type_def.html',1,'']]], - ['dcmi_5ftypedef_2',['DCMI_TypeDef',['../struct_d_c_m_i___type_def.html',1,'']]], - ['dma_5fstream_5ftypedef_3',['DMA_Stream_TypeDef',['../struct_d_m_a___stream___type_def.html',1,'']]], - ['dma_5ftypedef_4',['DMA_TypeDef',['../struct_d_m_a___type_def.html',1,'']]], - ['dwt_5ftype_5',['DWT_Type',['../struct_d_w_t___type.html',1,'']]] + ['tim_5fsim_0',['TIM_Sim',['../struct_t_i_m___sim.html',1,'']]] ]; diff --git a/DOCS/html/search/classes_4.js b/DOCS/html/search/classes_4.js deleted file mode 100644 index 92b2b61..0000000 --- a/DOCS/html/search/classes_4.js +++ /dev/null @@ -1,5 +0,0 @@ -var searchData= -[ - ['eth_5ftypedef_0',['ETH_TypeDef',['../struct_e_t_h___type_def.html',1,'']]], - ['exti_5ftypedef_1',['EXTI_TypeDef',['../struct_e_x_t_i___type_def.html',1,'']]] -]; diff --git a/DOCS/html/search/classes_5.js b/DOCS/html/search/classes_5.js deleted file mode 100644 index 3fe5c06..0000000 --- a/DOCS/html/search/classes_5.js +++ /dev/null @@ -1,9 +0,0 @@ -var searchData= -[ - ['flash_5ftypedef_0',['FLASH_TypeDef',['../struct_f_l_a_s_h___type_def.html',1,'']]], - ['fpu_5ftype_1',['FPU_Type',['../struct_f_p_u___type.html',1,'']]], - ['fsmc_5fbank1_5ftypedef_2',['FSMC_Bank1_TypeDef',['../struct_f_s_m_c___bank1___type_def.html',1,'']]], - ['fsmc_5fbank1e_5ftypedef_3',['FSMC_Bank1E_TypeDef',['../struct_f_s_m_c___bank1_e___type_def.html',1,'']]], - ['fsmc_5fbank2_5f3_5ftypedef_4',['FSMC_Bank2_3_TypeDef',['../struct_f_s_m_c___bank2__3___type_def.html',1,'']]], - ['fsmc_5fbank4_5ftypedef_5',['FSMC_Bank4_TypeDef',['../struct_f_s_m_c___bank4___type_def.html',1,'']]] -]; diff --git a/DOCS/html/search/classes_6.js b/DOCS/html/search/classes_6.js deleted file mode 100644 index e6eacea..0000000 --- a/DOCS/html/search/classes_6.js +++ /dev/null @@ -1,4 +0,0 @@ -var searchData= -[ - ['gpio_5ftypedef_0',['GPIO_TypeDef',['../struct_g_p_i_o___type_def.html',1,'']]] -]; diff --git a/DOCS/html/search/classes_7.js b/DOCS/html/search/classes_7.js deleted file mode 100644 index f136622..0000000 --- a/DOCS/html/search/classes_7.js +++ /dev/null @@ -1,7 +0,0 @@ -var searchData= -[ - ['i2c_5ftypedef_0',['I2C_TypeDef',['../struct_i2_c___type_def.html',1,'']]], - ['ipsr_5ftype_1',['IPSR_Type',['../union_i_p_s_r___type.html',1,'']]], - ['itm_5ftype_2',['ITM_Type',['../struct_i_t_m___type.html',1,'']]], - ['iwdg_5ftypedef_3',['IWDG_TypeDef',['../struct_i_w_d_g___type_def.html',1,'']]] -]; diff --git a/DOCS/html/search/classes_8.js b/DOCS/html/search/classes_8.js deleted file mode 100644 index 6a790a1..0000000 --- a/DOCS/html/search/classes_8.js +++ /dev/null @@ -1,4 +0,0 @@ -var searchData= -[ - ['nvic_5ftype_0',['NVIC_Type',['../struct_n_v_i_c___type.html',1,'']]] -]; diff --git a/DOCS/html/search/classes_9.js b/DOCS/html/search/classes_9.js deleted file mode 100644 index 1ba8e62..0000000 --- a/DOCS/html/search/classes_9.js +++ /dev/null @@ -1,4 +0,0 @@ -var searchData= -[ - ['pwr_5ftypedef_0',['PWR_TypeDef',['../struct_p_w_r___type_def.html',1,'']]] -]; diff --git a/DOCS/html/search/classes_a.js b/DOCS/html/search/classes_a.js deleted file mode 100644 index f859e0c..0000000 --- a/DOCS/html/search/classes_a.js +++ /dev/null @@ -1,6 +0,0 @@ -var searchData= -[ - ['rcc_5ftypedef_0',['RCC_TypeDef',['../struct_r_c_c___type_def.html',1,'']]], - ['rng_5ftypedef_1',['RNG_TypeDef',['../struct_r_n_g___type_def.html',1,'']]], - ['rtc_5ftypedef_2',['RTC_TypeDef',['../struct_r_t_c___type_def.html',1,'']]] -]; diff --git a/DOCS/html/search/classes_b.js b/DOCS/html/search/classes_b.js deleted file mode 100644 index da7257c..0000000 --- a/DOCS/html/search/classes_b.js +++ /dev/null @@ -1,11 +0,0 @@ -var searchData= -[ - ['scb_5ftype_0',['SCB_Type',['../struct_s_c_b___type.html',1,'']]], - ['scnscb_5ftype_1',['SCnSCB_Type',['../struct_s_cn_s_c_b___type.html',1,'']]], - ['sdio_5ftypedef_2',['SDIO_TypeDef',['../struct_s_d_i_o___type_def.html',1,'']]], - ['sim_5f_5fmcuhandletypedef_3',['SIM__MCUHandleTypeDef',['../struct_s_i_m_____m_c_u_handle_type_def.html',1,'']]], - ['slavechannels_4',['SlaveChannels',['../struct_slave_channels.html',1,'']]], - ['spi_5ftypedef_5',['SPI_TypeDef',['../struct_s_p_i___type_def.html',1,'']]], - ['syscfg_5ftypedef_6',['SYSCFG_TypeDef',['../struct_s_y_s_c_f_g___type_def.html',1,'']]], - ['systick_5ftype_7',['SysTick_Type',['../struct_sys_tick___type.html',1,'']]] -]; diff --git a/DOCS/html/search/classes_c.js b/DOCS/html/search/classes_c.js deleted file mode 100644 index 7a6a5d0..0000000 --- a/DOCS/html/search/classes_c.js +++ /dev/null @@ -1,6 +0,0 @@ -var searchData= -[ - ['tim_5fsim_0',['TIM_Sim',['../struct_t_i_m___sim.html',1,'']]], - ['tim_5ftypedef_1',['TIM_TypeDef',['../struct_t_i_m___type_def.html',1,'']]], - ['tpi_5ftype_2',['TPI_Type',['../struct_t_p_i___type.html',1,'']]] -]; diff --git a/DOCS/html/search/classes_d.js b/DOCS/html/search/classes_d.js deleted file mode 100644 index bd5885f..0000000 --- a/DOCS/html/search/classes_d.js +++ /dev/null @@ -1,10 +0,0 @@ -var searchData= -[ - ['usart_5ftypedef_0',['USART_TypeDef',['../struct_u_s_a_r_t___type_def.html',1,'']]], - ['usb_5fotg_5fdevicetypedef_1',['USB_OTG_DeviceTypeDef',['../struct_u_s_b___o_t_g___device_type_def.html',1,'']]], - ['usb_5fotg_5fglobaltypedef_2',['USB_OTG_GlobalTypeDef',['../struct_u_s_b___o_t_g___global_type_def.html',1,'']]], - ['usb_5fotg_5fhostchanneltypedef_3',['USB_OTG_HostChannelTypeDef',['../struct_u_s_b___o_t_g___host_channel_type_def.html',1,'']]], - ['usb_5fotg_5fhosttypedef_4',['USB_OTG_HostTypeDef',['../struct_u_s_b___o_t_g___host_type_def.html',1,'']]], - ['usb_5fotg_5finendpointtypedef_5',['USB_OTG_INEndpointTypeDef',['../struct_u_s_b___o_t_g___i_n_endpoint_type_def.html',1,'']]], - ['usb_5fotg_5foutendpointtypedef_6',['USB_OTG_OUTEndpointTypeDef',['../struct_u_s_b___o_t_g___o_u_t_endpoint_type_def.html',1,'']]] -]; diff --git a/DOCS/html/search/classes_e.js b/DOCS/html/search/classes_e.js deleted file mode 100644 index d649363..0000000 --- a/DOCS/html/search/classes_e.js +++ /dev/null @@ -1,4 +0,0 @@ -var searchData= -[ - ['wwdg_5ftypedef_0',['WWDG_TypeDef',['../struct_w_w_d_g___type_def.html',1,'']]] -]; diff --git a/DOCS/html/search/classes_f.js b/DOCS/html/search/classes_f.js deleted file mode 100644 index 56dbe40..0000000 --- a/DOCS/html/search/classes_f.js +++ /dev/null @@ -1,4 +0,0 @@ -var searchData= -[ - ['xpsr_5ftype_0',['xPSR_Type',['../unionx_p_s_r___type.html',1,'']]] -]; diff --git a/DOCS/html/search/defines_0.js b/DOCS/html/search/defines_0.js deleted file mode 100644 index 4df954d..0000000 --- a/DOCS/html/search/defines_0.js +++ /dev/null @@ -1,61 +0,0 @@ -var searchData= -[ - ['_5f_5faligned_0',['__ALIGNED',['../arm__defines_8h.html#aa65ef8f7a5e8b7a6ea6c1d48b4c78e55',1,'arm_defines.h']]], - ['_5f_5farmclib_5fversion_1',['__ARMCLIB_VERSION',['../stdint_8h.html#a069d06d08ec1fd2e3bef945d23718106',1,'stdint.h']]], - ['_5f_5fasm_2',['__ASM',['../arm__defines_8h.html#a1378040bcf22428955c6e3ce9c2053cd',1,'arm_defines.h']]], - ['_5f_5fbkpt_3',['__BKPT',['../arm__defines_8h.html#a15ea6bd3c507d3e81c3b3a1258e46397',1,'arm_defines.h']]], - ['_5f_5fclibns_4',['__CLIBNS',['../stdint_8h.html#a49324e794e54deaab7cb5dc166780120',1,'stdint.h']]], - ['_5f_5fclrex_5',['__CLREX',['../arm__defines_8h.html#a7f7b66103530fadcce226375af3c2c03',1,'arm_defines.h']]], - ['_5f_5fclz_6',['__CLZ',['../arm__defines_8h.html#ad435395be5d5f9eaacba4c5441e62796',1,'arm_defines.h']]], - ['_5f_5fdisable_5firq_7',['__disable_irq',['../arm__defines_8h.html#aff0484414d77b54006e638548b081d64',1,'arm_defines.h']]], - ['_5f_5fdmb_8',['__DMB',['../arm__defines_8h.html#a671101179b5943990785f36f8c1e2269',1,'arm_defines.h']]], - ['_5f_5fdsb_9',['__DSB',['../arm__defines_8h.html#a067d257a2b34565410acefb5afef2203',1,'arm_defines.h']]], - ['_5f_5fi_10',['__I',['../core__cm4__matlab_8h.html#af63697ed9952cc71e1225efe205f6cd3',1,'core_cm4_matlab.h']]], - ['_5f_5fim_11',['__IM',['../core__cm4__matlab_8h.html#a4cc1649793116d7c2d8afce7a4ffce43',1,'core_cm4_matlab.h']]], - ['_5f_5finline_12',['__INLINE',['../arm__defines_8h.html#ade2d8d7118f8ff49547f60aa0c3382bb',1,'arm_defines.h']]], - ['_5f_5finline_13',['__inline',['../arm__defines_8h.html#a96deb7ba5a74848afb710cc4ee6d2c08',1,'arm_defines.h']]], - ['_5f_5fint64_14',['__INT64',['../stdint_8h.html#a151a46d8d0c3ff2df4c26eb0c3494fb5',1,'stdint.h']]], - ['_5f_5fint64_5fc_15',['__INT64_C',['../stdint_8h.html#aba0b23b9278a0f12ef402626eeebfa13',1,'stdint.h']]], - ['_5f_5fint64_5fc_5fsuffix_5f_5f_16',['__INT64_C_SUFFIX__',['../stdint_8h.html#a33c4c9f9f182bf7e8a0e57fd5f68a8fc',1,'stdint.h']]], - ['_5f_5fio_17',['__IO',['../arm__defines_8h.html#aec43007d9998a0a0e01faede4133d6be',1,'__IO: arm_defines.h'],['../core__cm4__matlab_8h.html#aec43007d9998a0a0e01faede4133d6be',1,'__IO: core_cm4_matlab.h']]], - ['_5f_5fiom_18',['__IOM',['../core__cm4__matlab_8h.html#ab6caba5853a60a17e8e04499b52bf691',1,'core_cm4_matlab.h']]], - ['_5f_5fisb_19',['__ISB',['../arm__defines_8h.html#aad233022e850a009fc6f7602be1182f6',1,'arm_defines.h']]], - ['_5f_5fldrexb_20',['__LDREXB',['../arm__defines_8h.html#a8876672c1f185d3253fea6b06bdba771',1,'arm_defines.h']]], - ['_5f_5fldrexh_21',['__LDREXH',['../arm__defines_8h.html#aa7f6f01cf534bc8daccc421dc823fc6f',1,'arm_defines.h']]], - ['_5f_5fldrexw_22',['__LDREXW',['../arm__defines_8h.html#aa872ae25197f1dddc52835fdfed9a881',1,'arm_defines.h']]], - ['_5f_5flonglong_23',['__LONGLONG',['../stdint_8h.html#af6b8bce81cb81cef5df097a396496a69',1,'stdint.h']]], - ['_5f_5fno_5freturn_24',['__NO_RETURN',['../arm__defines_8h.html#a153a4a31b276a9758959580538720a51',1,'arm_defines.h']]], - ['_5f_5fnop_25',['__NOP',['../arm__defines_8h.html#a0b13f3617dd4af2cd2eb3a311073f717',1,'arm_defines.h']]], - ['_5f_5fo_26',['__O',['../core__cm4__matlab_8h.html#a7e25d9380f9ef903923964322e71f2f6',1,'core_cm4_matlab.h']]], - ['_5f_5fom_27',['__OM',['../core__cm4__matlab_8h.html#a0ea2009ed8fd9ef35b48708280fdb758',1,'core_cm4_matlab.h']]], - ['_5f_5fpacked_28',['__PACKED',['../arm__defines_8h.html#abe8996d3d985ee1529475443cc635bf1',1,'arm_defines.h']]], - ['_5f_5fpacked_5fstruct_29',['__PACKED_STRUCT',['../arm__defines_8h.html#a4dbb70fab85207c27b581ecb6532b314',1,'arm_defines.h']]], - ['_5f_5fpacked_5funion_30',['__PACKED_UNION',['../arm__defines_8h.html#a6fba34d08b0a526830b4231d2ea0b89a',1,'arm_defines.h']]], - ['_5f_5fpaste_31',['__PASTE',['../stdint_8h.html#ac3ae5768889bec57a63f08b6a6e5f58d',1,'stdint.h']]], - ['_5f_5fpaste2_32',['__PASTE2',['../stdint_8h.html#a9a494f36bdb6e7a465eecff7fc6c2a31',1,'stdint.h']]], - ['_5f_5frbit_33',['__RBIT',['../arm__defines_8h.html#a3a468db3bc52465a88269bfb34e675a7',1,'arm_defines.h']]], - ['_5f_5frestrict_34',['__RESTRICT',['../arm__defines_8h.html#a378ac21329d33f561f90265eef89f564',1,'arm_defines.h']]], - ['_5f_5frev_35',['__REV',['../arm__defines_8h.html#aca25a02e09983da5558f5242f2f635bc',1,'arm_defines.h']]], - ['_5f_5frev16_36',['__REV16',['../arm__defines_8h.html#ad35497777af37e7809271b5e6f9510ba',1,'arm_defines.h']]], - ['_5f_5frevsh_37',['__REVSH',['../arm__defines_8h.html#ae580812686119c9c5cf3c11a7519a404',1,'arm_defines.h']]], - ['_5f_5fror_38',['__ROR',['../arm__defines_8h.html#a27ffb10344b90805b21307493c319cb4',1,'arm_defines.h']]], - ['_5f_5fsev_39',['__SEV',['../arm__defines_8h.html#afa58e60fcd2176ad58f96947466ea1fa',1,'arm_defines.h']]], - ['_5f_5fssat_40',['__SSAT',['../arm__defines_8h.html#a3c013c2ed76ebc48c283c8bae17b9ab8',1,'arm_defines.h']]], - ['_5f_5fstatic_5fforceinline_41',['__STATIC_FORCEINLINE',['../arm__defines_8h.html#ab904513442afdf77d4f8c74f23cbb040',1,'arm_defines.h']]], - ['_5f_5fstatic_5finline_42',['__STATIC_INLINE',['../arm__defines_8h.html#aba87361bfad2ae52cfe2f40c1a1dbf9c',1,'arm_defines.h']]], - ['_5f_5fstdint_5fdecls_43',['__STDINT_DECLS',['../stdint_8h.html#a60a7be5011232f989fededd98181467b',1,'stdint.h']]], - ['_5f_5fstrexb_44',['__STREXB',['../arm__defines_8h.html#a503ba30a93e83963de38e5171fbbabce',1,'arm_defines.h']]], - ['_5f_5fstrexh_45',['__STREXH',['../arm__defines_8h.html#a63d19c6c7852ada9a1c1aab80e6294b1',1,'arm_defines.h']]], - ['_5f_5fstrexw_46',['__STREXW',['../arm__defines_8h.html#a0c3704e33e90ba0491cee56cfb553090',1,'arm_defines.h']]], - ['_5f_5fuint64_5fc_47',['__UINT64_C',['../stdint_8h.html#a3b5e01fc50cf47627f362b514e5ca9dd',1,'stdint.h']]], - ['_5f_5funaligned_5fuint16_5fread_48',['__UNALIGNED_UINT16_READ',['../arm__defines_8h.html#ab71b66e5ce403158d3dee62a59f9175f',1,'arm_defines.h']]], - ['_5f_5funaligned_5fuint16_5fwrite_49',['__UNALIGNED_UINT16_WRITE',['../arm__defines_8h.html#a5103fb373cae9837cc4a384be55dc87f',1,'arm_defines.h']]], - ['_5f_5funaligned_5fuint32_50',['__UNALIGNED_UINT32',['../arm__defines_8h.html#ac8a13aacd0453758fdfd01a57a2a6a3d',1,'arm_defines.h']]], - ['_5f_5funaligned_5fuint32_5fread_51',['__UNALIGNED_UINT32_READ',['../arm__defines_8h.html#a3b931f0b051b8c1a6377a3dcc7559b5e',1,'arm_defines.h']]], - ['_5f_5funaligned_5fuint32_5fwrite_52',['__UNALIGNED_UINT32_WRITE',['../arm__defines_8h.html#a203f593d140ed88b81bc189edc861110',1,'arm_defines.h']]], - ['_5f_5fusat_53',['__USAT',['../arm__defines_8h.html#ad0e4fa951d563740462d837bb6ddd7bb',1,'arm_defines.h']]], - ['_5f_5fused_54',['__USED',['../arm__defines_8h.html#a3e40e4c553fc11588f7a4c2a19e789e0',1,'arm_defines.h']]], - ['_5f_5fweak_55',['__WEAK',['../arm__defines_8h.html#ac607bf387b29162be6a9b77fc7999539',1,'arm_defines.h']]], - ['_5f_5fwfe_56',['__WFE',['../arm__defines_8h.html#af0330712223f4cfb6091e4ab84775f73',1,'arm_defines.h']]], - ['_5f_5fwfi_57',['__WFI',['../arm__defines_8h.html#ab28e2b328c4cf23c917ab18a23194f8e',1,'arm_defines.h']]] -]; diff --git a/DOCS/html/search/defines_1.js b/DOCS/html/search/defines_1.js deleted file mode 100644 index cad3432..0000000 --- a/DOCS/html/search/defines_1.js +++ /dev/null @@ -1,36 +0,0 @@ -var searchData= -[ - ['int16_5fc_0',['INT16_C',['../stdint_8h.html#a838b261fec725cb0f5d5b6769d3521e7',1,'stdint.h']]], - ['int16_5fmax_1',['INT16_MAX',['../stdint_8h.html#ac58f2c111cc9989c86db2a7dc4fd84ca',1,'stdint.h']]], - ['int16_5fmin_2',['INT16_MIN',['../stdint_8h.html#ad4e9955955b27624963643eac448118a',1,'stdint.h']]], - ['int32_5fc_3',['INT32_C',['../stdint_8h.html#ad78650fb7726f4e99205406569ef403d',1,'stdint.h']]], - ['int32_5fmax_4',['INT32_MAX',['../stdint_8h.html#a181807730d4a375f848ba139813ce04f',1,'stdint.h']]], - ['int32_5fmin_5',['INT32_MIN',['../stdint_8h.html#a688eb21a22db27c2b2bd5836943cdcbe',1,'stdint.h']]], - ['int64_5fc_6',['INT64_C',['../stdint_8h.html#a93d102802b35d3b8abae9bbe7f0fed75',1,'stdint.h']]], - ['int64_5fmax_7',['INT64_MAX',['../stdint_8h.html#ad0d744f05898e32d01f73f8af3cd2071',1,'stdint.h']]], - ['int64_5fmin_8',['INT64_MIN',['../stdint_8h.html#ab21f12f372f67b8ff0aa3432336ede67',1,'stdint.h']]], - ['int8_5fc_9',['INT8_C',['../stdint_8h.html#a1eaa7db37089dcdfb60227725c9c1585',1,'stdint.h']]], - ['int8_5fmax_10',['INT8_MAX',['../stdint_8h.html#aaf7f29f45f1a513b4748a4e5014ddf6a',1,'stdint.h']]], - ['int8_5fmin_11',['INT8_MIN',['../stdint_8h.html#aadcf2a81af243df333b31efa6461ab8e',1,'stdint.h']]], - ['int_5ffast16_5fmax_12',['INT_FAST16_MAX',['../stdint_8h.html#a2fd35d0ea091e04caec504ff0042cf00',1,'stdint.h']]], - ['int_5ffast16_5fmin_13',['INT_FAST16_MIN',['../stdint_8h.html#a169460a4e2a79138723d68d99372d958',1,'stdint.h']]], - ['int_5ffast32_5fmax_14',['INT_FAST32_MAX',['../stdint_8h.html#ac96fa0f41b19e89f109e4f9913ca6635',1,'stdint.h']]], - ['int_5ffast32_5fmin_15',['INT_FAST32_MIN',['../stdint_8h.html#ad93df1652ed0635513d5efe4f1219926',1,'stdint.h']]], - ['int_5ffast64_5fmax_16',['INT_FAST64_MAX',['../stdint_8h.html#a13c95cf9c209d8daacb36cbf0d5ba275',1,'stdint.h']]], - ['int_5ffast64_5fmin_17',['INT_FAST64_MIN',['../stdint_8h.html#a50f0fdcb00ea2500cec0f3d6d45c36f3',1,'stdint.h']]], - ['int_5ffast8_5fmax_18',['INT_FAST8_MAX',['../stdint_8h.html#acbcdb3bee0f5f904da5df8de69a80ca3',1,'stdint.h']]], - ['int_5ffast8_5fmin_19',['INT_FAST8_MIN',['../stdint_8h.html#aad8fb982cb19143efd5ee9a1a7a89390',1,'stdint.h']]], - ['int_5fleast16_5fmax_20',['INT_LEAST16_MAX',['../stdint_8h.html#a7eb2a8e2a1c65d6c9ad0f86154890baa',1,'stdint.h']]], - ['int_5fleast16_5fmin_21',['INT_LEAST16_MIN',['../stdint_8h.html#a1f91bfd5820c2f27af3d260fc75813e1',1,'stdint.h']]], - ['int_5fleast32_5fmax_22',['INT_LEAST32_MAX',['../stdint_8h.html#a5618711a0a54f722190a3a1219e278c2',1,'stdint.h']]], - ['int_5fleast32_5fmin_23',['INT_LEAST32_MIN',['../stdint_8h.html#a2360a536116dd734820a6b5b3d560ce7',1,'stdint.h']]], - ['int_5fleast64_5fmax_24',['INT_LEAST64_MAX',['../stdint_8h.html#a35d0f98a2e507fd1be779d49da92724e',1,'stdint.h']]], - ['int_5fleast64_5fmin_25',['INT_LEAST64_MIN',['../stdint_8h.html#ac12b4f6966b57ad82feb683b284b4060',1,'stdint.h']]], - ['int_5fleast8_5fmax_26',['INT_LEAST8_MAX',['../stdint_8h.html#aa05109908fb2770f632d2b646b9f85bf',1,'stdint.h']]], - ['int_5fleast8_5fmin_27',['INT_LEAST8_MIN',['../stdint_8h.html#a3e986cad833f63f420962ff60eda87e5',1,'stdint.h']]], - ['intmax_5fc_28',['INTMAX_C',['../stdint_8h.html#a846429736de0233f6ecddedb21424ddd',1,'stdint.h']]], - ['intmax_5fmax_29',['INTMAX_MAX',['../stdint_8h.html#a022b9b0a3564d786244a4631847c37a3',1,'stdint.h']]], - ['intmax_5fmin_30',['INTMAX_MIN',['../stdint_8h.html#a2b0a3edfc672154f606dc3ad26277b61',1,'stdint.h']]], - ['intptr_5fmax_31',['INTPTR_MAX',['../stdint_8h.html#a9e5742f2bae4a5283431a3c03499e3a9',1,'stdint.h']]], - ['intptr_5fmin_32',['INTPTR_MIN',['../stdint_8h.html#a2aaa6d3aa1d7d1e0e326955aa24db752',1,'stdint.h']]] -]; diff --git a/DOCS/html/search/defines_2.js b/DOCS/html/search/defines_2.js deleted file mode 100644 index bd4523f..0000000 --- a/DOCS/html/search/defines_2.js +++ /dev/null @@ -1,6 +0,0 @@ -var searchData= -[ - ['mdl_5fcheck_5fparameters_0',['MDL_CHECK_PARAMETERS',['../_m_c_u_8c.html#a4936bd489281a5a9b9a2e081de0f003e',1,'MCU.c']]], - ['mdl_5fstart_1',['MDL_START',['../_m_c_u_8c.html#ac032abbf580c891fb0c11e63e9bc668a',1,'MCU.c']]], - ['mdl_5fupdate_2',['MDL_UPDATE',['../_m_c_u_8c.html#a7556dbbf5cb7f9946d3e39bcda40c63b',1,'MCU.c']]] -]; diff --git a/DOCS/html/search/defines_3.js b/DOCS/html/search/defines_3.js deleted file mode 100644 index 984464c..0000000 --- a/DOCS/html/search/defines_3.js +++ /dev/null @@ -1,4 +0,0 @@ -var searchData= -[ - ['native_5fwhile_0',['native_while',['../mcu__wrapper__conf_8h.html#abaad5b5eb9243ab531775be5eda6ee02',1,'mcu_wrapper_conf.h']]] -]; diff --git a/DOCS/html/search/defines_4.js b/DOCS/html/search/defines_4.js deleted file mode 100644 index 164e3a6..0000000 --- a/DOCS/html/search/defines_4.js +++ /dev/null @@ -1,5 +0,0 @@ -var searchData= -[ - ['ptrdiff_5fmax_0',['PTRDIFF_MAX',['../stdint_8h.html#add2ef7bffac19cfdd1f4b5495409672f',1,'stdint.h']]], - ['ptrdiff_5fmin_1',['PTRDIFF_MIN',['../stdint_8h.html#ad9b88ba2fb858f98b50b38e49875d90e',1,'stdint.h']]] -]; diff --git a/DOCS/html/search/defines_5.js b/DOCS/html/search/defines_5.js deleted file mode 100644 index 9912362..0000000 --- a/DOCS/html/search/defines_5.js +++ /dev/null @@ -1,9 +0,0 @@ -var searchData= -[ - ['s_5ffunction_5flevel_0',['S_FUNCTION_LEVEL',['../_m_c_u_8c.html#a9a4ab27953070e39249f3fad28e93749',1,'MCU.c']]], - ['s_5ffunction_5fname_1',['S_FUNCTION_NAME',['../_m_c_u_8c.html#a0f61df833e166c743295eebf43f0b142',1,'MCU.c']]], - ['sig_5fatomic_5fmax_2',['SIG_ATOMIC_MAX',['../stdint_8h.html#a1f5fe9445d0ad0bee21bab1de4cc3e58',1,'stdint.h']]], - ['sig_5fatomic_5fmin_3',['SIG_ATOMIC_MIN',['../stdint_8h.html#a21e605b9ac3a03b6de93cdf5a69e129f',1,'stdint.h']]], - ['sim_5fwhile_4',['sim_while',['../mcu__wrapper__conf_8h.html#a1fef2893362ee1f5032b523ff8c7fd9d',1,'mcu_wrapper_conf.h']]], - ['size_5fmax_5',['SIZE_MAX',['../stdint_8h.html#a3c75bb398badb69c7577b21486f9963f',1,'stdint.h']]] -]; diff --git a/DOCS/html/search/defines_6.js b/DOCS/html/search/defines_6.js deleted file mode 100644 index bd49e5a..0000000 --- a/DOCS/html/search/defines_6.js +++ /dev/null @@ -1,22 +0,0 @@ -var searchData= -[ - ['uint16_5fc_0',['UINT16_C',['../stdint_8h.html#a1cb39a2cfaf899fd38730c7637807708',1,'stdint.h']]], - ['uint16_5fmax_1',['UINT16_MAX',['../stdint_8h.html#a3ea490c9b3617d4479bd80ef93cd5602',1,'stdint.h']]], - ['uint32_5fc_2',['UINT32_C',['../stdint_8h.html#a2451a7ede7ebd810357f1503e9898ea6',1,'stdint.h']]], - ['uint32_5fmax_3',['UINT32_MAX',['../stdint_8h.html#ab5eb23180f7cc12b7d6c04a8ec067fdd',1,'stdint.h']]], - ['uint64_5fc_4',['UINT64_C',['../stdint_8h.html#a134ae84400d184ed2570e3270d5472c2',1,'stdint.h']]], - ['uint64_5fmax_5',['UINT64_MAX',['../stdint_8h.html#a30654b4b67d97c42ca3f9b6052dda916',1,'stdint.h']]], - ['uint8_5fc_6',['UINT8_C',['../stdint_8h.html#acd2aa09844a8a245cf7fdbb808e215e5',1,'stdint.h']]], - ['uint8_5fmax_7',['UINT8_MAX',['../stdint_8h.html#aeb4e270a084ee26fe73e799861bd0252',1,'stdint.h']]], - ['uint_5ffast16_5fmax_8',['UINT_FAST16_MAX',['../stdint_8h.html#aed28ca63d9b222f6f1377358fe73a183',1,'stdint.h']]], - ['uint_5ffast32_5fmax_9',['UINT_FAST32_MAX',['../stdint_8h.html#ad51246a178143208b2db3315efd21c45',1,'stdint.h']]], - ['uint_5ffast64_5fmax_10',['UINT_FAST64_MAX',['../stdint_8h.html#aeb74410af7781bc84b5f64ae7a8f4a17',1,'stdint.h']]], - ['uint_5ffast8_5fmax_11',['UINT_FAST8_MAX',['../stdint_8h.html#a2c6f97ea2d76d0cf6260c84046cdb44e',1,'stdint.h']]], - ['uint_5fleast16_5fmax_12',['UINT_LEAST16_MAX',['../stdint_8h.html#a6ef6a1a518bbf516ca8b0180b11c358f',1,'stdint.h']]], - ['uint_5fleast32_5fmax_13',['UINT_LEAST32_MAX',['../stdint_8h.html#a70cad8bacc9a6db301e1cdc86cc8d571',1,'stdint.h']]], - ['uint_5fleast64_5fmax_14',['UINT_LEAST64_MAX',['../stdint_8h.html#aab530113fa96e280e49c3c138b0f917d',1,'stdint.h']]], - ['uint_5fleast8_5fmax_15',['UINT_LEAST8_MAX',['../stdint_8h.html#a2a80bde77ee1698d0f42f334adad4f2b',1,'stdint.h']]], - ['uintmax_5fc_16',['UINTMAX_C',['../stdint_8h.html#ad99c338b32fbeaa158cba21e532dfe5d',1,'stdint.h']]], - ['uintmax_5fmax_17',['UINTMAX_MAX',['../stdint_8h.html#aa54fd5210434219e9027bfa0f0e325c8',1,'stdint.h']]], - ['uintptr_5fmax_18',['UINTPTR_MAX',['../stdint_8h.html#ab2355300ea19395357e62d780f4dd073',1,'stdint.h']]] -]; diff --git a/DOCS/html/search/defines_7.js b/DOCS/html/search/defines_7.js deleted file mode 100644 index 2fe5fa5..0000000 --- a/DOCS/html/search/defines_7.js +++ /dev/null @@ -1,8 +0,0 @@ -var searchData= -[ - ['wchar_5fmax_0',['WCHAR_MAX',['../stdint_8h.html#a2a823f3ccf2306cfbaa34d8addf66010',1,'stdint.h']]], - ['wchar_5fmin_1',['WCHAR_MIN',['../stdint_8h.html#a051084d5ebcabf282d9ca9bb2b891a78',1,'stdint.h']]], - ['while_2',['while',['../mcu__wrapper__conf_8h.html#a866c2dad3e54488a018e859b3dc6feba',1,'mcu_wrapper_conf.h']]], - ['wint_5fmax_3',['WINT_MAX',['../stdint_8h.html#ad3f7b6bb8aa7d619017a91d3b2edc1ee',1,'stdint.h']]], - ['wint_5fmin_4',['WINT_MIN',['../stdint_8h.html#a5285bc55170ae1701e599decacc7f001',1,'stdint.h']]] -]; diff --git a/DOCS/html/search/enums_0.js b/DOCS/html/search/enums_0.js deleted file mode 100644 index dda0798..0000000 --- a/DOCS/html/search/enums_0.js +++ /dev/null @@ -1,4 +0,0 @@ -var searchData= -[ - ['errorstatus_0',['ErrorStatus',['../group___exported__types.html#ga8333b96c67f83cba354b3407fcbb6ee8',1,'stm32f4xx.h']]] -]; diff --git a/DOCS/html/search/enums_1.js b/DOCS/html/search/enums_1.js deleted file mode 100644 index e1be250..0000000 --- a/DOCS/html/search/enums_1.js +++ /dev/null @@ -1,5 +0,0 @@ -var searchData= -[ - ['flagstatus_0',['FlagStatus',['../group___exported__types.html#ga89136caac2e14c55151f527ac02daaff',1,'stm32f4xx.h']]], - ['functionalstate_1',['FunctionalState',['../group___exported__types.html#gac9a7e9a35d2513ec15c3b537aaa4fba1',1,'stm32f4xx.h']]] -]; diff --git a/DOCS/html/search/enums_2.js b/DOCS/html/search/enums_2.js deleted file mode 100644 index ac61304..0000000 --- a/DOCS/html/search/enums_2.js +++ /dev/null @@ -1,4 +0,0 @@ -var searchData= -[ - ['irqn_5ftype_0',['IRQn_Type',['../group___peripheral__interrupt__number__definition.html#ga7e1129cd8a196f4284d41db3e82ad5c8',1,'stm32f407xx_matlab.h']]] -]; diff --git a/DOCS/html/search/enumvalues_0.js b/DOCS/html/search/enumvalues_0.js deleted file mode 100644 index 17860e1..0000000 --- a/DOCS/html/search/enumvalues_0.js +++ /dev/null @@ -1,4 +0,0 @@ -var searchData= -[ - ['adc_5firqn_0',['ADC_IRQn',['../group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a4d69175258ae261dd545001e810421b3',1,'stm32f407xx_matlab.h']]] -]; diff --git a/DOCS/html/search/enumvalues_1.js b/DOCS/html/search/enumvalues_1.js deleted file mode 100644 index 669c690..0000000 --- a/DOCS/html/search/enumvalues_1.js +++ /dev/null @@ -1,4 +0,0 @@ -var searchData= -[ - ['busfault_5firqn_0',['BusFault_IRQn',['../group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a8693500eff174f16119e96234fee73af',1,'stm32f407xx_matlab.h']]] -]; diff --git a/DOCS/html/search/enumvalues_2.js b/DOCS/html/search/enumvalues_2.js deleted file mode 100644 index 37f161f..0000000 --- a/DOCS/html/search/enumvalues_2.js +++ /dev/null @@ -1,11 +0,0 @@ -var searchData= -[ - ['can1_5frx0_5firqn_0',['CAN1_RX0_IRQn',['../group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8ab6bf73ac43a9856b3f2759a59f3d25b5',1,'stm32f407xx_matlab.h']]], - ['can1_5frx1_5firqn_1',['CAN1_RX1_IRQn',['../group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8af71ef06c4f9ff0e1691c21ff3670acd4',1,'stm32f407xx_matlab.h']]], - ['can1_5fsce_5firqn_2',['CAN1_SCE_IRQn',['../group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a0f5f129d88a5606a378811e43039e274',1,'stm32f407xx_matlab.h']]], - ['can1_5ftx_5firqn_3',['CAN1_TX_IRQn',['../group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a9ceb5175f7c10cf436955173c2246877',1,'stm32f407xx_matlab.h']]], - ['can2_5frx0_5firqn_4',['CAN2_RX0_IRQn',['../group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a851fd2f2ab1418710e7da80e1bdf348a',1,'stm32f407xx_matlab.h']]], - ['can2_5frx1_5firqn_5',['CAN2_RX1_IRQn',['../group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8ab5023ff845be31a488ab63a0b8cf2b7a',1,'stm32f407xx_matlab.h']]], - ['can2_5fsce_5firqn_6',['CAN2_SCE_IRQn',['../group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a56c0b5758f26f31494e74aab9273f9fd',1,'stm32f407xx_matlab.h']]], - ['can2_5ftx_5firqn_7',['CAN2_TX_IRQn',['../group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8af6b8fbc990ac71c8425647bb684788a4',1,'stm32f407xx_matlab.h']]] -]; diff --git a/DOCS/html/search/enumvalues_3.js b/DOCS/html/search/enumvalues_3.js deleted file mode 100644 index 24eef60..0000000 --- a/DOCS/html/search/enumvalues_3.js +++ /dev/null @@ -1,22 +0,0 @@ -var searchData= -[ - ['dcmi_5firqn_0',['DCMI_IRQn',['../group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8ace3c0fc2c4d05a7c02e3c987da5bc8e8',1,'stm32f407xx_matlab.h']]], - ['debugmonitor_5firqn_1',['DebugMonitor_IRQn',['../group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a8e033fcef7aed98a31c60a7de206722c',1,'stm32f407xx_matlab.h']]], - ['disable_2',['DISABLE',['../group___exported__types.html#ggac9a7e9a35d2513ec15c3b537aaa4fba1ad3a9df141be0ccf10389b640f492b26d',1,'stm32f4xx.h']]], - ['dma1_5fstream0_5firqn_3',['DMA1_Stream0_IRQn',['../group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a9ee33e72512c4cfb301b216f4fb9d68c',1,'stm32f407xx_matlab.h']]], - ['dma1_5fstream1_5firqn_4',['DMA1_Stream1_IRQn',['../group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8aa45ca2c955060e2c2a7cbbe1d6753285',1,'stm32f407xx_matlab.h']]], - ['dma1_5fstream2_5firqn_5',['DMA1_Stream2_IRQn',['../group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a0d9ec75e4478e70235b705d5a6b3efd8',1,'stm32f407xx_matlab.h']]], - ['dma1_5fstream3_5firqn_6',['DMA1_Stream3_IRQn',['../group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8af77770e080206a7558decf09344fb2e2',1,'stm32f407xx_matlab.h']]], - ['dma1_5fstream4_5firqn_7',['DMA1_Stream4_IRQn',['../group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8aee2aaf365c6c297a63cee41ecae2301a',1,'stm32f407xx_matlab.h']]], - ['dma1_5fstream5_5firqn_8',['DMA1_Stream5_IRQn',['../group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8ac92efa72399fe58fa615d8bf8fd64a4e',1,'stm32f407xx_matlab.h']]], - ['dma1_5fstream6_5firqn_9',['DMA1_Stream6_IRQn',['../group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8aef5e2b68f62f6f1781fab894f0b8f486',1,'stm32f407xx_matlab.h']]], - ['dma1_5fstream7_5firqn_10',['DMA1_Stream7_IRQn',['../group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8aedaa9c14e7e5fa9c0dcbb0c2455546e8',1,'stm32f407xx_matlab.h']]], - ['dma2_5fstream0_5firqn_11',['DMA2_Stream0_IRQn',['../group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a1e5055722630fd4b12aff421964c2ebb',1,'stm32f407xx_matlab.h']]], - ['dma2_5fstream1_5firqn_12',['DMA2_Stream1_IRQn',['../group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a98abb3f02c1feb3831706bc1b82307cb',1,'stm32f407xx_matlab.h']]], - ['dma2_5fstream2_5firqn_13',['DMA2_Stream2_IRQn',['../group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8abf5e189f3ac7aad9f65e65ea5a0f3b36',1,'stm32f407xx_matlab.h']]], - ['dma2_5fstream3_5firqn_14',['DMA2_Stream3_IRQn',['../group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a3ff8f3439f509e6e985eb960e63e1be4',1,'stm32f407xx_matlab.h']]], - ['dma2_5fstream4_5firqn_15',['DMA2_Stream4_IRQn',['../group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8ae54eb8b30273b38a0576f75aba24eec0',1,'stm32f407xx_matlab.h']]], - ['dma2_5fstream5_5firqn_16',['DMA2_Stream5_IRQn',['../group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a933d4686213973abc01845a3da1c8a03',1,'stm32f407xx_matlab.h']]], - ['dma2_5fstream6_5firqn_17',['DMA2_Stream6_IRQn',['../group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a21570761ad0b5ed751adc831691b7800',1,'stm32f407xx_matlab.h']]], - ['dma2_5fstream7_5firqn_18',['DMA2_Stream7_IRQn',['../group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a3d4cc0cd9b4d71e7ee002c4f8c1f8a77',1,'stm32f407xx_matlab.h']]] -]; diff --git a/DOCS/html/search/enumvalues_4.js b/DOCS/html/search/enumvalues_4.js deleted file mode 100644 index 36e075c..0000000 --- a/DOCS/html/search/enumvalues_4.js +++ /dev/null @@ -1,14 +0,0 @@ -var searchData= -[ - ['enable_0',['ENABLE',['../group___exported__types.html#ggac9a7e9a35d2513ec15c3b537aaa4fba1a7d46875fa3ebd2c34d2756950eda83bf',1,'stm32f4xx.h']]], - ['error_1',['ERROR',['../group___exported__types.html#gga8333b96c67f83cba354b3407fcbb6ee8a2fd6f336d08340583bd620a7f5694c90',1,'stm32f4xx.h']]], - ['eth_5firqn_2',['ETH_IRQn',['../group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8ad71328dd95461b7c55b568cf25966f6a',1,'stm32f407xx_matlab.h']]], - ['eth_5fwkup_5firqn_3',['ETH_WKUP_IRQn',['../group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a0485578005e12c2e2c0fb253a844ec6f',1,'stm32f407xx_matlab.h']]], - ['exti0_5firqn_4',['EXTI0_IRQn',['../group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8ab6aa6f87d26bbc6cf99b067b8d75c2f7',1,'stm32f407xx_matlab.h']]], - ['exti15_5f10_5firqn_5',['EXTI15_10_IRQn',['../group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a9fb0ad0c850234d1983fafdb17378e2f',1,'stm32f407xx_matlab.h']]], - ['exti1_5firqn_6',['EXTI1_IRQn',['../group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8ae4badcdecdb94eb10129c4c0577c5e19',1,'stm32f407xx_matlab.h']]], - ['exti2_5firqn_7',['EXTI2_IRQn',['../group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a082cb3f7839069a0715fd76c7eacbbc9',1,'stm32f407xx_matlab.h']]], - ['exti3_5firqn_8',['EXTI3_IRQn',['../group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8add889c84ba5de466ced209069e05d602',1,'stm32f407xx_matlab.h']]], - ['exti4_5firqn_9',['EXTI4_IRQn',['../group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8ab70a40106ca4486770df5d2072d9ac0e',1,'stm32f407xx_matlab.h']]], - ['exti9_5f5_5firqn_10',['EXTI9_5_IRQn',['../group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8aa3aa50e0353871985facf62d055faa52',1,'stm32f407xx_matlab.h']]] -]; diff --git a/DOCS/html/search/enumvalues_5.js b/DOCS/html/search/enumvalues_5.js deleted file mode 100644 index c64df88..0000000 --- a/DOCS/html/search/enumvalues_5.js +++ /dev/null @@ -1,6 +0,0 @@ -var searchData= -[ - ['flash_5firqn_0',['FLASH_IRQn',['../group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a91b73963ce243a1d031576d49e137fab',1,'stm32f407xx_matlab.h']]], - ['fpu_5firqn_1',['FPU_IRQn',['../group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8aa6b8ff01b016a798c6e639728c179e4f',1,'stm32f407xx_matlab.h']]], - ['fsmc_5firqn_2',['FSMC_IRQn',['../group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a70450df88125476d5771f2ff3f562536',1,'stm32f407xx_matlab.h']]] -]; diff --git a/DOCS/html/search/enumvalues_6.js b/DOCS/html/search/enumvalues_6.js deleted file mode 100644 index d2229eb..0000000 --- a/DOCS/html/search/enumvalues_6.js +++ /dev/null @@ -1,9 +0,0 @@ -var searchData= -[ - ['i2c1_5fer_5firqn_0',['I2C1_ER_IRQn',['../group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a2ec363869f4488782dc10a60abce3b34',1,'stm32f407xx_matlab.h']]], - ['i2c1_5fev_5firqn_1',['I2C1_EV_IRQn',['../group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a9852dbbe8c014e716ce7e03a7b809751',1,'stm32f407xx_matlab.h']]], - ['i2c2_5fer_5firqn_2',['I2C2_ER_IRQn',['../group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a60c35f2d48d512bd6818bc9fef7053d7',1,'stm32f407xx_matlab.h']]], - ['i2c2_5fev_5firqn_3',['I2C2_EV_IRQn',['../group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a3020193786527c47d2e4d8c92ceee804',1,'stm32f407xx_matlab.h']]], - ['i2c3_5fer_5firqn_4',['I2C3_ER_IRQn',['../group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a6e954232d164a6942ebc7a6bd6f7736e',1,'stm32f407xx_matlab.h']]], - ['i2c3_5fev_5firqn_5',['I2C3_EV_IRQn',['../group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a8326db2d570cb865ffa1d49fa29d562a',1,'stm32f407xx_matlab.h']]] -]; diff --git a/DOCS/html/search/enumvalues_7.js b/DOCS/html/search/enumvalues_7.js deleted file mode 100644 index a75c398..0000000 --- a/DOCS/html/search/enumvalues_7.js +++ /dev/null @@ -1,4 +0,0 @@ -var searchData= -[ - ['memorymanagement_5firqn_0',['MemoryManagement_IRQn',['../group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a33ff1cf7098de65d61b6354fee6cd5aa',1,'stm32f407xx_matlab.h']]] -]; diff --git a/DOCS/html/search/enumvalues_8.js b/DOCS/html/search/enumvalues_8.js deleted file mode 100644 index d94653a..0000000 --- a/DOCS/html/search/enumvalues_8.js +++ /dev/null @@ -1,4 +0,0 @@ -var searchData= -[ - ['nonmaskableint_5firqn_0',['NonMaskableInt_IRQn',['../group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8ade177d9c70c89e084093024b932a4e30',1,'stm32f407xx_matlab.h']]] -]; diff --git a/DOCS/html/search/enumvalues_9.js b/DOCS/html/search/enumvalues_9.js deleted file mode 100644 index 3846f37..0000000 --- a/DOCS/html/search/enumvalues_9.js +++ /dev/null @@ -1,9 +0,0 @@ -var searchData= -[ - ['otg_5ffs_5firqn_0',['OTG_FS_IRQn',['../group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8aa60a30b7ef03446a46fd72e084911f7e',1,'stm32f407xx_matlab.h']]], - ['otg_5ffs_5fwkup_5firqn_1',['OTG_FS_WKUP_IRQn',['../group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8aa612f35c4440359c35acbaa3c1458c5f',1,'stm32f407xx_matlab.h']]], - ['otg_5fhs_5fep1_5fin_5firqn_2',['OTG_HS_EP1_IN_IRQn',['../group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a1b040a7f76278a73cf5ea4c51f1be047',1,'stm32f407xx_matlab.h']]], - ['otg_5fhs_5fep1_5fout_5firqn_3',['OTG_HS_EP1_OUT_IRQn',['../group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a60b6cc4b6dbeca39e29a475d26c9e080',1,'stm32f407xx_matlab.h']]], - ['otg_5fhs_5firqn_4',['OTG_HS_IRQn',['../group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8aad2d5e47d27fe3a02f7059b20bb729c0',1,'stm32f407xx_matlab.h']]], - ['otg_5fhs_5fwkup_5firqn_5',['OTG_HS_WKUP_IRQn',['../group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a9e5c9d81dd3985a88094f8158c0f0267',1,'stm32f407xx_matlab.h']]] -]; diff --git a/DOCS/html/search/enumvalues_a.js b/DOCS/html/search/enumvalues_a.js deleted file mode 100644 index 2ed2197..0000000 --- a/DOCS/html/search/enumvalues_a.js +++ /dev/null @@ -1,5 +0,0 @@ -var searchData= -[ - ['pendsv_5firqn_0',['PendSV_IRQn',['../group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a03c3cc89984928816d81793fc7bce4a2',1,'stm32f407xx_matlab.h']]], - ['pvd_5firqn_1',['PVD_IRQn',['../group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8ab0b51ffcc4dcf5661141b79c8e5bd924',1,'stm32f407xx_matlab.h']]] -]; diff --git a/DOCS/html/search/enumvalues_b.js b/DOCS/html/search/enumvalues_b.js deleted file mode 100644 index 2e736ee..0000000 --- a/DOCS/html/search/enumvalues_b.js +++ /dev/null @@ -1,8 +0,0 @@ -var searchData= -[ - ['rcc_5firqn_0',['RCC_IRQn',['../group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a5710b22392997bac63daa5c999730f77',1,'stm32f407xx_matlab.h']]], - ['reset_1',['RESET',['../group___exported__types.html#gga89136caac2e14c55151f527ac02daaffa589b7d94a3d91d145720e2fed0eb3a05',1,'stm32f4xx.h']]], - ['rng_5firqn_2',['RNG_IRQn',['../group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a90c4647e57cff99fac635c532802c4b5',1,'stm32f407xx_matlab.h']]], - ['rtc_5falarm_5firqn_3',['RTC_Alarm_IRQn',['../group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8afe09d6563a21a1540f658163a76a3b37',1,'stm32f407xx_matlab.h']]], - ['rtc_5fwkup_5firqn_4',['RTC_WKUP_IRQn',['../group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a173ccc3f31df1f7e43de2ddeab3d1777',1,'stm32f407xx_matlab.h']]] -]; diff --git a/DOCS/html/search/enumvalues_c.js b/DOCS/html/search/enumvalues_c.js deleted file mode 100644 index 5bd09e5..0000000 --- a/DOCS/html/search/enumvalues_c.js +++ /dev/null @@ -1,11 +0,0 @@ -var searchData= -[ - ['sdio_5firqn_0',['SDIO_IRQn',['../group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a16fe70a39348f3f27906dc268b5654e3',1,'stm32f407xx_matlab.h']]], - ['set_1',['SET',['../group___exported__types.html#gga89136caac2e14c55151f527ac02daaffab44c8101cc294c074709ec1b14211792',1,'stm32f4xx.h']]], - ['spi1_5firqn_2',['SPI1_IRQn',['../group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8aacdff1a9c42582ed663214cbe62c1174',1,'stm32f407xx_matlab.h']]], - ['spi2_5firqn_3',['SPI2_IRQn',['../group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a505fbd4ccf7c2a14c8b76dc9e58f7ede',1,'stm32f407xx_matlab.h']]], - ['spi3_5firqn_4',['SPI3_IRQn',['../group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a4e9331739fb76a2ca7781fede070ae44',1,'stm32f407xx_matlab.h']]], - ['success_5',['SUCCESS',['../group___exported__types.html#gga8333b96c67f83cba354b3407fcbb6ee8ac7f69f7c9e5aea9b8f54cf02870e2bf8',1,'stm32f4xx.h']]], - ['svcall_5firqn_6',['SVCall_IRQn',['../group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a4ce820b3cc6cf3a796b41aadc0cf1237',1,'stm32f407xx_matlab.h']]], - ['systick_5firqn_7',['SysTick_IRQn',['../group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a6dbff8f8543325f3474cbae2446776e7',1,'stm32f407xx_matlab.h']]] -]; diff --git a/DOCS/html/search/enumvalues_d.js b/DOCS/html/search/enumvalues_d.js deleted file mode 100644 index 0edf018..0000000 --- a/DOCS/html/search/enumvalues_d.js +++ /dev/null @@ -1,18 +0,0 @@ -var searchData= -[ - ['tamp_5fstamp_5firqn_0',['TAMP_STAMP_IRQn',['../group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8ac127cca7ae48bcf93924209f04e5e5a1',1,'stm32f407xx_matlab.h']]], - ['tim1_5fbrk_5ftim9_5firqn_1',['TIM1_BRK_TIM9_IRQn',['../group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8ab35b4ce63cfb11453f84a3695c6df368',1,'stm32f407xx_matlab.h']]], - ['tim1_5fcc_5firqn_2',['TIM1_CC_IRQn',['../group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8af312f0a21f600f9b286427e50c549ca9',1,'stm32f407xx_matlab.h']]], - ['tim1_5ftrg_5fcom_5ftim11_5firqn_3',['TIM1_TRG_COM_TIM11_IRQn',['../group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8ab1a744bdceb8eface6ff57dd036e608e',1,'stm32f407xx_matlab.h']]], - ['tim1_5fup_5ftim10_5firqn_4',['TIM1_UP_TIM10_IRQn',['../group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8aa3879e49013035601e17f83a51e0829f',1,'stm32f407xx_matlab.h']]], - ['tim2_5firqn_5',['TIM2_IRQn',['../group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a3a4e2095a926e4095d3c846eb1c98afa',1,'stm32f407xx_matlab.h']]], - ['tim3_5firqn_6',['TIM3_IRQn',['../group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a985574288f66e2a00e97387424a9a2d8',1,'stm32f407xx_matlab.h']]], - ['tim4_5firqn_7',['TIM4_IRQn',['../group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a368b899ca740b9ae0d75841f3abf68c4',1,'stm32f407xx_matlab.h']]], - ['tim5_5firqn_8',['TIM5_IRQn',['../group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8aed2eb3f4bb721d55fcc1003125956645',1,'stm32f407xx_matlab.h']]], - ['tim6_5fdac_5firqn_9',['TIM6_DAC_IRQn',['../group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a5f581e9aedfaccd9b1db9ec793804b45',1,'stm32f407xx_matlab.h']]], - ['tim7_5firqn_10',['TIM7_IRQn',['../group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a53cadc1e164ec85d0ea4cd143608e8e1',1,'stm32f407xx_matlab.h']]], - ['tim8_5fbrk_5ftim12_5firqn_11',['TIM8_BRK_TIM12_IRQn',['../group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a3e01328006d19f7d32354271b9f61dce',1,'stm32f407xx_matlab.h']]], - ['tim8_5fcc_5firqn_12',['TIM8_CC_IRQn',['../group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a637750639eff4e2b4aae80ed6f3cf67f',1,'stm32f407xx_matlab.h']]], - ['tim8_5ftrg_5fcom_5ftim14_5firqn_13',['TIM8_TRG_COM_TIM14_IRQn',['../group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8ae252b31c3a341acbe9a467e243137307',1,'stm32f407xx_matlab.h']]], - ['tim8_5fup_5ftim13_5firqn_14',['TIM8_UP_TIM13_IRQn',['../group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8aa8d8f67a98f24de6f0b36ad6b1f29a7d',1,'stm32f407xx_matlab.h']]] -]; diff --git a/DOCS/html/search/enumvalues_e.js b/DOCS/html/search/enumvalues_e.js deleted file mode 100644 index 701b3f3..0000000 --- a/DOCS/html/search/enumvalues_e.js +++ /dev/null @@ -1,10 +0,0 @@ -var searchData= -[ - ['uart4_5firqn_0',['UART4_IRQn',['../group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8aded5314b20c6e4e80cb6ab0668ffb8d5',1,'stm32f407xx_matlab.h']]], - ['uart5_5firqn_1',['UART5_IRQn',['../group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8ac55a11a64aae7432544d0ab0d4f7de09',1,'stm32f407xx_matlab.h']]], - ['usagefault_5firqn_2',['UsageFault_IRQn',['../group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a6895237c9443601ac832efa635dd8bbf',1,'stm32f407xx_matlab.h']]], - ['usart1_5firqn_3',['USART1_IRQn',['../group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8ad97cb163e1f678367e37c50d54d161ab',1,'stm32f407xx_matlab.h']]], - ['usart2_5firqn_4',['USART2_IRQn',['../group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a3f9c48714d0e5baaba6613343f0da68e',1,'stm32f407xx_matlab.h']]], - ['usart3_5firqn_5',['USART3_IRQn',['../group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8afb13802afc1f5fdf5c90e73ee99e5ff3',1,'stm32f407xx_matlab.h']]], - ['usart6_5firqn_6',['USART6_IRQn',['../group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8aa92bcb2bc3a87be869f05c5b07f04b8c',1,'stm32f407xx_matlab.h']]] -]; diff --git a/DOCS/html/search/enumvalues_f.js b/DOCS/html/search/enumvalues_f.js deleted file mode 100644 index 65aeda5..0000000 --- a/DOCS/html/search/enumvalues_f.js +++ /dev/null @@ -1,4 +0,0 @@ -var searchData= -[ - ['wwdg_5firqn_0',['WWDG_IRQn',['../group___peripheral__interrupt__number__definition.html#gga7e1129cd8a196f4284d41db3e82ad5c8a971089d7566ef902dfa0c80ac3a8fd52',1,'stm32f407xx_matlab.h']]] -]; diff --git a/DOCS/html/search/files_0.js b/DOCS/html/search/files_0.js index 916e2f9..67f9185 100644 --- a/DOCS/html/search/files_0.js +++ b/DOCS/html/search/files_0.js @@ -1,4 +1,7 @@ var searchData= [ - ['arm_5fdefines_2eh_0',['arm_defines.h',['../arm__defines_8h.html',1,'']]] + ['mcu_2ec_0',['MCU.c',['../_m_c_u_8c.html',1,'']]], + ['mcu_5fwrapper_2ec_1',['mcu_wrapper.c',['../mcu__wrapper_8c.html',1,'']]], + ['mcu_5fwrapper_5fconf_2eh_2',['mcu_wrapper_conf.h',['../mcu__wrapper__conf_8h.html',1,'']]], + ['mexing_2em_3',['mexing.m',['../mexing_8m.html',1,'']]] ]; diff --git a/DOCS/html/search/files_1.js b/DOCS/html/search/files_1.js index 42bde8e..6a28a2e 100644 --- a/DOCS/html/search/files_1.js +++ b/DOCS/html/search/files_1.js @@ -1,4 +1,5 @@ var searchData= [ - ['core_5fcm4_5fmatlab_2eh_0',['core_cm4_matlab.h',['../core__cm4__matlab_8h.html',1,'']]] + ['readme_2emd_0',['README.md',['../_r_e_a_d_m_e_8md.html',1,'']]], + ['run_5fmex_2ebat_1',['run_mex.bat',['../run__mex_8bat.html',1,'']]] ]; diff --git a/DOCS/html/search/files_2.js b/DOCS/html/search/files_2.js index 67f9185..d446b63 100644 --- a/DOCS/html/search/files_2.js +++ b/DOCS/html/search/files_2.js @@ -1,7 +1,13 @@ var searchData= [ - ['mcu_2ec_0',['MCU.c',['../_m_c_u_8c.html',1,'']]], - ['mcu_5fwrapper_2ec_1',['mcu_wrapper.c',['../mcu__wrapper_8c.html',1,'']]], - ['mcu_5fwrapper_5fconf_2eh_2',['mcu_wrapper_conf.h',['../mcu__wrapper__conf_8h.html',1,'']]], - ['mexing_2em_3',['mexing.m',['../mexing_8m.html',1,'']]] + ['stm32f407xx_5fmatlab_5fmemory_2eh_0',['stm32f407xx_matlab_memory.h',['../stm32f407xx__matlab__memory_8h.html',1,'']]], + ['stm32f4xx_5fmatlab_5fconf_2ec_1',['stm32f4xx_matlab_conf.c',['../stm32f4xx__matlab__conf_8c.html',1,'']]], + ['stm32f4xx_5fmatlab_5fconf_2eh_2',['stm32f4xx_matlab_conf.h',['../stm32f4xx__matlab__conf_8h.html',1,'']]], + ['stm32f4xx_5fmatlab_5fgpio_2ec_3',['stm32f4xx_matlab_gpio.c',['../stm32f4xx__matlab__gpio_8c.html',1,'']]], + ['stm32f4xx_5fmatlab_5fgpio_2eh_4',['stm32f4xx_matlab_gpio.h',['../stm32f4xx__matlab__gpio_8h.html',1,'']]], + ['stm32f4xx_5fmatlab_5frcc_2ec_5',['stm32f4xx_matlab_rcc.c',['../stm32f4xx__matlab__rcc_8c.html',1,'']]], + ['stm32f4xx_5fmatlab_5frcc_2eh_6',['stm32f4xx_matlab_rcc.h',['../stm32f4xx__matlab__rcc_8h.html',1,'']]], + ['stm32f4xx_5fmatlab_5ftim_2ec_7',['stm32f4xx_matlab_tim.c',['../stm32f4xx__matlab__tim_8c.html',1,'']]], + ['stm32f4xx_5fmatlab_5ftim_2eh_8',['stm32f4xx_matlab_tim.h',['../stm32f4xx__matlab__tim_8h.html',1,'']]], + ['stm32f4xx_5fperiph_5fregisters_2ec_9',['stm32f4xx_periph_registers.c',['../stm32f4xx__periph__registers_8c.html',1,'']]] ]; diff --git a/DOCS/html/search/files_3.js b/DOCS/html/search/files_3.js deleted file mode 100644 index 6a28a2e..0000000 --- a/DOCS/html/search/files_3.js +++ /dev/null @@ -1,5 +0,0 @@ -var searchData= -[ - ['readme_2emd_0',['README.md',['../_r_e_a_d_m_e_8md.html',1,'']]], - ['run_5fmex_2ebat_1',['run_mex.bat',['../run__mex_8bat.html',1,'']]] -]; diff --git a/DOCS/html/search/files_4.js b/DOCS/html/search/files_4.js deleted file mode 100644 index e910237..0000000 --- a/DOCS/html/search/files_4.js +++ /dev/null @@ -1,16 +0,0 @@ -var searchData= -[ - ['stdint_2eh_0',['stdint.h',['../stdint_8h.html',1,'']]], - ['stm32f407xx_5fmatlab_2eh_1',['stm32f407xx_matlab.h',['../stm32f407xx__matlab_8h.html',1,'']]], - ['stm32f4xx_2eh_2',['stm32f4xx.h',['../stm32f4xx_8h.html',1,'']]], - ['stm32f4xx_5fmatlab_5fconf_2ec_3',['stm32f4xx_matlab_conf.c',['../stm32f4xx__matlab__conf_8c.html',1,'']]], - ['stm32f4xx_5fmatlab_5fconf_2eh_4',['stm32f4xx_matlab_conf.h',['../stm32f4xx__matlab__conf_8h.html',1,'']]], - ['stm32f4xx_5fmatlab_5fgpio_2ec_5',['stm32f4xx_matlab_gpio.c',['../stm32f4xx__matlab__gpio_8c.html',1,'']]], - ['stm32f4xx_5fmatlab_5fgpio_2eh_6',['stm32f4xx_matlab_gpio.h',['../stm32f4xx__matlab__gpio_8h.html',1,'']]], - ['stm32f4xx_5fmatlab_5frcc_2ec_7',['stm32f4xx_matlab_rcc.c',['../stm32f4xx__matlab__rcc_8c.html',1,'']]], - ['stm32f4xx_5fmatlab_5frcc_2eh_8',['stm32f4xx_matlab_rcc.h',['../stm32f4xx__matlab__rcc_8h.html',1,'']]], - ['stm32f4xx_5fmatlab_5ftim_2ec_9',['stm32f4xx_matlab_tim.c',['../stm32f4xx__matlab__tim_8c.html',1,'']]], - ['stm32f4xx_5fmatlab_5ftim_2eh_10',['stm32f4xx_matlab_tim.h',['../stm32f4xx__matlab__tim_8h.html',1,'']]], - ['stm32f4xx_5fperiph_5fregisters_2ec_11',['stm32f4xx_periph_registers.c',['../stm32f4xx__periph__registers_8c.html',1,'']]], - ['system_5fstm32f4xx_2eh_12',['system_stm32f4xx.h',['../system__stm32f4xx_8h.html',1,'']]] -]; diff --git a/DOCS/html/search/functions_0.js b/DOCS/html/search/functions_0.js index a18a6d3..88e24ec 100644 --- a/DOCS/html/search/functions_0.js +++ b/DOCS/html/search/functions_0.js @@ -1,17 +1,9 @@ var searchData= [ - ['_5f_5fnvic_5fclearpendingirq_0',['__NVIC_ClearPendingIRQ',['../group___c_m_s_i_s___core___n_v_i_c_functions.html#ga562a86dbdf14827d0fee8fdafb04d191',1,'core_cm4_matlab.h']]], - ['_5f_5fnvic_5fdisableirq_1',['__NVIC_DisableIRQ',['../group___c_m_s_i_s___core___n_v_i_c_functions.html#gae016e4c1986312044ee768806537d52f',1,'core_cm4_matlab.h']]], - ['_5f_5fnvic_5fenableirq_2',['__NVIC_EnableIRQ',['../group___c_m_s_i_s___core___n_v_i_c_functions.html#ga71227e1376cde11eda03fcb62f1b33ea',1,'core_cm4_matlab.h']]], - ['_5f_5fnvic_5fgetactive_3',['__NVIC_GetActive',['../group___c_m_s_i_s___core___n_v_i_c_functions.html#gaa2837003c28c45abf193fe5e8d27f593',1,'core_cm4_matlab.h']]], - ['_5f_5fnvic_5fgetenableirq_4',['__NVIC_GetEnableIRQ',['../group___c_m_s_i_s___core___n_v_i_c_functions.html#gaaeb5e7cc0eaad4e2817272e7bf742083',1,'core_cm4_matlab.h']]], - ['_5f_5fnvic_5fgetpendingirq_5',['__NVIC_GetPendingIRQ',['../group___c_m_s_i_s___core___n_v_i_c_functions.html#ga5a92ca5fa801ad7adb92be7257ab9694',1,'core_cm4_matlab.h']]], - ['_5f_5fnvic_5fgetpriority_6',['__NVIC_GetPriority',['../group___c_m_s_i_s___core___n_v_i_c_functions.html#gaeb9dc99c8e7700668813144261b0bc73',1,'core_cm4_matlab.h']]], - ['_5f_5fnvic_5fgetprioritygrouping_7',['__NVIC_GetPriorityGrouping',['../group___c_m_s_i_s___core___n_v_i_c_functions.html#ga9b894af672df4373eb637f8288845c05',1,'core_cm4_matlab.h']]], - ['_5f_5fnvic_5fgetvector_8',['__NVIC_GetVector',['../group___c_m_s_i_s___core___n_v_i_c_functions.html#ga44b665d2afb708121d9b10c76ff00ee5',1,'core_cm4_matlab.h']]], - ['_5f_5fnvic_5fsetpendingirq_9',['__NVIC_SetPendingIRQ',['../group___c_m_s_i_s___core___n_v_i_c_functions.html#gaabefdd4b790b9a7308929938c0c1e1ad',1,'core_cm4_matlab.h']]], - ['_5f_5fnvic_5fsetpriority_10',['__NVIC_SetPriority',['../group___c_m_s_i_s___core___n_v_i_c_functions.html#ga505338e23563a9c074910fb14e7d45fd',1,'core_cm4_matlab.h']]], - ['_5f_5fnvic_5fsetprioritygrouping_11',['__NVIC_SetPriorityGrouping',['../group___c_m_s_i_s___core___n_v_i_c_functions.html#gafc94dcbaee03e4746ade1f5bb9aaa56d',1,'core_cm4_matlab.h']]], - ['_5f_5fnvic_5fsetvector_12',['__NVIC_SetVector',['../group___c_m_s_i_s___core___n_v_i_c_functions.html#ga0df355460bc1783d58f9d72ee4884208',1,'core_cm4_matlab.h']]], - ['_5f_5fnvic_5fsystemreset_13',['__NVIC_SystemReset',['../group___c_m_s_i_s___core___n_v_i_c_functions.html#ga0d9aa2d30fa54b41eb780c16e35b676c',1,'core_cm4_matlab.h']]] + ['call_5firqhandller_0',['call_IRQHandller',['../group___t_i_m___s_i_m_u_l_a_t_o_r.html#gaa2b3ab4507a894ffa6e4487d42054e67',1,'call_IRQHandller(TIM_TypeDef *TIMx): stm32f4xx_matlab_tim.c'],['../group___t_i_m___s_i_m_u_l_a_t_o_r.html#gaa2b3ab4507a894ffa6e4487d42054e67',1,'call_IRQHandller(TIM_TypeDef *TIMx): stm32f4xx_matlab_tim.c']]], + ['cc_5fpwm_5fch1_5fsimulation_1',['CC_PWM_Ch1_Simulation',['../group___t_i_m___s_i_m_u_l_a_t_o_r.html#ga609dd2da1a15ffb80256e85942ed2671',1,'CC_PWM_Ch1_Simulation(TIM_TypeDef *TIMx, struct TIM_Sim *TIMS): stm32f4xx_matlab_tim.c'],['../group___t_i_m___s_i_m_u_l_a_t_o_r.html#ga609dd2da1a15ffb80256e85942ed2671',1,'CC_PWM_Ch1_Simulation(TIM_TypeDef *TIMx, struct TIM_Sim *TIMS): stm32f4xx_matlab_tim.c']]], + ['cc_5fpwm_5fch2_5fsimulation_2',['CC_PWM_Ch2_Simulation',['../group___t_i_m___s_i_m_u_l_a_t_o_r.html#gaef90da33b410dcd77d9cdb58363d729c',1,'CC_PWM_Ch2_Simulation(TIM_TypeDef *TIMx, struct TIM_Sim *TIMS): stm32f4xx_matlab_tim.c'],['../group___t_i_m___s_i_m_u_l_a_t_o_r.html#gaef90da33b410dcd77d9cdb58363d729c',1,'CC_PWM_Ch2_Simulation(TIM_TypeDef *TIMx, struct TIM_Sim *TIMS): stm32f4xx_matlab_tim.c']]], + ['cc_5fpwm_5fch3_5fsimulation_3',['CC_PWM_Ch3_Simulation',['../group___t_i_m___s_i_m_u_l_a_t_o_r.html#ga99db7a05808ca9b5aa12df01745ed2ef',1,'CC_PWM_Ch3_Simulation(TIM_TypeDef *TIMx, struct TIM_Sim *TIMS): stm32f4xx_matlab_tim.c'],['../group___t_i_m___s_i_m_u_l_a_t_o_r.html#ga99db7a05808ca9b5aa12df01745ed2ef',1,'CC_PWM_Ch3_Simulation(TIM_TypeDef *TIMx, struct TIM_Sim *TIMS): stm32f4xx_matlab_tim.c']]], + ['cc_5fpwm_5fch4_5fsimulation_4',['CC_PWM_Ch4_Simulation',['../group___t_i_m___s_i_m_u_l_a_t_o_r.html#gad51e3fbb47f5768c33876ad803fbef20',1,'CC_PWM_Ch4_Simulation(TIM_TypeDef *TIMx, struct TIM_Sim *TIMS): stm32f4xx_matlab_tim.c'],['../group___t_i_m___s_i_m_u_l_a_t_o_r.html#gad51e3fbb47f5768c33876ad803fbef20',1,'CC_PWM_Ch4_Simulation(TIM_TypeDef *TIMx, struct TIM_Sim *TIMS): stm32f4xx_matlab_tim.c']]], + ['channels_5fsimulation_5',['Channels_Simulation',['../group___t_i_m___s_i_m_u_l_a_t_o_r.html#ga63dc3b53fe4b165b4c70e4d600258d50',1,'Channels_Simulation(TIM_TypeDef *TIMx, struct TIM_Sim *TIMS): stm32f4xx_matlab_tim.c'],['../group___t_i_m___s_i_m_u_l_a_t_o_r.html#ga63dc3b53fe4b165b4c70e4d600258d50',1,'Channels_Simulation(TIM_TypeDef *TIMx, struct TIM_Sim *TIMS): stm32f4xx_matlab_tim.c']]] ]; diff --git a/DOCS/html/search/functions_1.js b/DOCS/html/search/functions_1.js index 88e24ec..1f09303 100644 --- a/DOCS/html/search/functions_1.js +++ b/DOCS/html/search/functions_1.js @@ -1,9 +1,6 @@ var searchData= [ - ['call_5firqhandller_0',['call_IRQHandller',['../group___t_i_m___s_i_m_u_l_a_t_o_r.html#gaa2b3ab4507a894ffa6e4487d42054e67',1,'call_IRQHandller(TIM_TypeDef *TIMx): stm32f4xx_matlab_tim.c'],['../group___t_i_m___s_i_m_u_l_a_t_o_r.html#gaa2b3ab4507a894ffa6e4487d42054e67',1,'call_IRQHandller(TIM_TypeDef *TIMx): stm32f4xx_matlab_tim.c']]], - ['cc_5fpwm_5fch1_5fsimulation_1',['CC_PWM_Ch1_Simulation',['../group___t_i_m___s_i_m_u_l_a_t_o_r.html#ga609dd2da1a15ffb80256e85942ed2671',1,'CC_PWM_Ch1_Simulation(TIM_TypeDef *TIMx, struct TIM_Sim *TIMS): stm32f4xx_matlab_tim.c'],['../group___t_i_m___s_i_m_u_l_a_t_o_r.html#ga609dd2da1a15ffb80256e85942ed2671',1,'CC_PWM_Ch1_Simulation(TIM_TypeDef *TIMx, struct TIM_Sim *TIMS): stm32f4xx_matlab_tim.c']]], - ['cc_5fpwm_5fch2_5fsimulation_2',['CC_PWM_Ch2_Simulation',['../group___t_i_m___s_i_m_u_l_a_t_o_r.html#gaef90da33b410dcd77d9cdb58363d729c',1,'CC_PWM_Ch2_Simulation(TIM_TypeDef *TIMx, struct TIM_Sim *TIMS): stm32f4xx_matlab_tim.c'],['../group___t_i_m___s_i_m_u_l_a_t_o_r.html#gaef90da33b410dcd77d9cdb58363d729c',1,'CC_PWM_Ch2_Simulation(TIM_TypeDef *TIMx, struct TIM_Sim *TIMS): stm32f4xx_matlab_tim.c']]], - ['cc_5fpwm_5fch3_5fsimulation_3',['CC_PWM_Ch3_Simulation',['../group___t_i_m___s_i_m_u_l_a_t_o_r.html#ga99db7a05808ca9b5aa12df01745ed2ef',1,'CC_PWM_Ch3_Simulation(TIM_TypeDef *TIMx, struct TIM_Sim *TIMS): stm32f4xx_matlab_tim.c'],['../group___t_i_m___s_i_m_u_l_a_t_o_r.html#ga99db7a05808ca9b5aa12df01745ed2ef',1,'CC_PWM_Ch3_Simulation(TIM_TypeDef *TIMx, struct TIM_Sim *TIMS): stm32f4xx_matlab_tim.c']]], - ['cc_5fpwm_5fch4_5fsimulation_4',['CC_PWM_Ch4_Simulation',['../group___t_i_m___s_i_m_u_l_a_t_o_r.html#gad51e3fbb47f5768c33876ad803fbef20',1,'CC_PWM_Ch4_Simulation(TIM_TypeDef *TIMx, struct TIM_Sim *TIMS): stm32f4xx_matlab_tim.c'],['../group___t_i_m___s_i_m_u_l_a_t_o_r.html#gad51e3fbb47f5768c33876ad803fbef20',1,'CC_PWM_Ch4_Simulation(TIM_TypeDef *TIMx, struct TIM_Sim *TIMS): stm32f4xx_matlab_tim.c']]], - ['channels_5fsimulation_5',['Channels_Simulation',['../group___t_i_m___s_i_m_u_l_a_t_o_r.html#ga63dc3b53fe4b165b4c70e4d600258d50',1,'Channels_Simulation(TIM_TypeDef *TIMx, struct TIM_Sim *TIMS): stm32f4xx_matlab_tim.c'],['../group___t_i_m___s_i_m_u_l_a_t_o_r.html#ga63dc3b53fe4b165b4c70e4d600258d50',1,'Channels_Simulation(TIM_TypeDef *TIMx, struct TIM_Sim *TIMS): stm32f4xx_matlab_tim.c']]] + ['deinitialize_5fmcu_0',['deInitialize_MCU',['../stm32f4xx__matlab__conf_8c.html#ad7d9ddf99be97748bc7417425271d85e',1,'deInitialize_MCU(void): stm32f4xx_matlab_conf.c'],['../stm32f4xx__matlab__conf_8h.html#ad7d9ddf99be97748bc7417425271d85e',1,'deInitialize_MCU(void): stm32f4xx_matlab_conf.c']]], + ['deinitialize_5fperiph_5fsim_1',['deInitialize_Periph_Sim',['../stm32f4xx__matlab__conf_8c.html#aff389f4df35953d82d9d30ae161a8cf9',1,'deInitialize_Periph_Sim(void): stm32f4xx_matlab_conf.c'],['../stm32f4xx__matlab__conf_8h.html#aff389f4df35953d82d9d30ae161a8cf9',1,'deInitialize_Periph_Sim(void): stm32f4xx_matlab_conf.c']]], + ['delete_2',['delete',['../mexing_8m.html#a079ba1759372ad0dafb30bfb334998cc',1,'mexing.m']]] ]; diff --git a/DOCS/html/search/functions_2.js b/DOCS/html/search/functions_2.js index c2ee27a..2344d44 100644 --- a/DOCS/html/search/functions_2.js +++ b/DOCS/html/search/functions_2.js @@ -1,6 +1,5 @@ var searchData= [ - ['deinitialize_5fmcu_0',['deInitialize_MCU',['../group___m_a_i_n___s_i_m_u_l_a_t_o_r.html#gad7d9ddf99be97748bc7417425271d85e',1,'deInitialize_MCU(void): stm32f4xx_matlab_conf.c'],['../group___m_a_i_n___s_i_m_u_l_a_t_o_r.html#gad7d9ddf99be97748bc7417425271d85e',1,'deInitialize_MCU(void): stm32f4xx_matlab_conf.c']]], - ['deinitialize_5fperiph_5fsim_1',['deInitialize_Periph_Sim',['../group___m_a_i_n___s_i_m_u_l_a_t_o_r.html#gaff389f4df35953d82d9d30ae161a8cf9',1,'deInitialize_Periph_Sim(void): stm32f4xx_matlab_conf.c'],['../group___m_a_i_n___s_i_m_u_l_a_t_o_r.html#gaff389f4df35953d82d9d30ae161a8cf9',1,'deInitialize_Periph_Sim(void): stm32f4xx_matlab_conf.c']]], - ['delete_2',['delete',['../mexing_8m.html#a079ba1759372ad0dafb30bfb334998cc',1,'mexing.m']]] + ['getcompilerconfigurations_0',['getCompilerConfigurations',['../mexing_8m.html#a8c4063b39743b0fdb6cbd8100456a07d',1,'mexing.m']]], + ['gpio_5fto_5fsfunc_1',['GPIO_to_SFUNC',['../group___g_p_i_o___s_i_m_u_l_a_t_o_r.html#ga487177c90297da30ee8ec0dca0ce3067',1,'GPIO_to_SFUNC(real_T *out_buff): stm32f4xx_matlab_gpio.c'],['../group___g_p_i_o___s_i_m_u_l_a_t_o_r.html#ga487177c90297da30ee8ec0dca0ce3067',1,'GPIO_to_SFUNC(real_T *in): stm32f4xx_matlab_gpio.c']]] ]; diff --git a/DOCS/html/search/functions_3.js b/DOCS/html/search/functions_3.js index 1c06391..5c4eae1 100644 --- a/DOCS/html/search/functions_3.js +++ b/DOCS/html/search/functions_3.js @@ -1,5 +1,5 @@ var searchData= [ - ['getcompilerconfigurations_0',['getCompilerConfigurations',['../mexing_8m.html#a8c4063b39743b0fdb6cbd8100456a07d',1,'mexing.m']]], - ['gpio_5fto_5fsfunc_1',['GPIO_to_SFUNC',['../group___g_p_i_o___s_i_m_u_l_a_t_o_r.html#ga487177c90297da30ee8ec0dca0ce3067',1,'GPIO_to_SFUNC(real_T *disc): stm32f4xx_matlab_gpio.c'],['../group___g_p_i_o___s_i_m_u_l_a_t_o_r.html#ga487177c90297da30ee8ec0dca0ce3067',1,'GPIO_to_SFUNC(real_T *in): stm32f4xx_matlab_gpio.c']]] + ['init_5ftim_5fsim_0',['Init_TIM_SIM',['../stm32f4xx__matlab__conf_8c.html#a617bc2e624bea041e844a0ac0c6a50f9',1,'Init_TIM_SIM(void): stm32f4xx_matlab_conf.c'],['../stm32f4xx__matlab__conf_8h.html#a617bc2e624bea041e844a0ac0c6a50f9',1,'Init_TIM_SIM(void): stm32f4xx_matlab_conf.c']]], + ['initialize_5fperiph_5fsim_1',['Initialize_Periph_Sim',['../group___m_a_i_n___s_i_m_u_l_a_t_o_r.html#gab020a77f89d6c0ea99c7559cfa7e3ba0',1,'Initialize_Periph_Sim(void): stm32f4xx_matlab_conf.c'],['../group___m_a_i_n___s_i_m_u_l_a_t_o_r.html#gab020a77f89d6c0ea99c7559cfa7e3ba0',1,'Initialize_Periph_Sim(void): stm32f4xx_matlab_conf.c']]] ]; diff --git a/DOCS/html/search/functions_4.js b/DOCS/html/search/functions_4.js index 24c518d..dd80ce7 100644 --- a/DOCS/html/search/functions_4.js +++ b/DOCS/html/search/functions_4.js @@ -1,8 +1,15 @@ var searchData= [ - ['init_5ftim_5fsim_0',['Init_TIM_SIM',['../group___m_a_i_n___s_i_m_u_l_a_t_o_r.html#ga617bc2e624bea041e844a0ac0c6a50f9',1,'Init_TIM_SIM(void): stm32f4xx_matlab_conf.c'],['../group___m_a_i_n___s_i_m_u_l_a_t_o_r.html#ga617bc2e624bea041e844a0ac0c6a50f9',1,'Init_TIM_SIM(void): stm32f4xx_matlab_conf.c']]], - ['initialize_5fperiph_5fsim_1',['Initialize_Periph_Sim',['../group___m_a_i_n___s_i_m_u_l_a_t_o_r.html#gab020a77f89d6c0ea99c7559cfa7e3ba0',1,'Initialize_Periph_Sim(void): stm32f4xx_matlab_conf.c'],['../group___m_a_i_n___s_i_m_u_l_a_t_o_r.html#gab020a77f89d6c0ea99c7559cfa7e3ba0',1,'Initialize_Periph_Sim(void): stm32f4xx_matlab_conf.c']]], - ['itm_5fcheckchar_2',['ITM_CheckChar',['../group___c_m_s_i_s__core___debug_functions.html#gae61ce9ca5917735325cd93b0fb21dd29',1,'core_cm4_matlab.h']]], - ['itm_5freceivechar_3',['ITM_ReceiveChar',['../group___c_m_s_i_s__core___debug_functions.html#gac3ee2c30a1ac4ed34c8a866a17decd53',1,'core_cm4_matlab.h']]], - ['itm_5fsendchar_4',['ITM_SendChar',['../group___c_m_s_i_s__core___debug_functions.html#gac90a497bd64286b84552c2c553d3419e',1,'core_cm4_matlab.h']]] + ['main_0',['main',['../mcu__wrapper_8c.html#a840291bc02cba5474a4cb46a9b9566fe',1,'mcu_wrapper.c']]], + ['mcu_5fapp_5fthread_1',['MCU_App_Thread',['../mcu__wrapper_8c.html#a1ea76a95b9b28061fb34ece9f6f0a85f',1,'mcu_wrapper.c']]], + ['mcu_5fperiph_5fsimulation_2',['MCU_Periph_Simulation',['../group___m_c_u___w_r_a_p_p_e_r.html#gaccdef5b45f3d1646f248304e02b00e54',1,'MCU_Periph_Simulation(void): mcu_wrapper.c'],['../group___m_c_u___w_r_a_p_p_e_r.html#gaccdef5b45f3d1646f248304e02b00e54',1,'MCU_Periph_Simulation(void): mcu_wrapper.c']]], + ['mcu_5freadinputs_3',['MCU_readInputs',['../group___m_c_u___w_r_a_p_p_e_r.html#ga15045e0feba8ddf08e20958fd1e36cd5',1,'MCU_readInputs(SimStruct *S): mcu_wrapper.c'],['../group___m_c_u___w_r_a_p_p_e_r.html#ga15045e0feba8ddf08e20958fd1e36cd5',1,'MCU_readInputs(SimStruct *S): mcu_wrapper.c']]], + ['mcu_5fstep_5fsimulation_4',['MCU_Step_Simulation',['../group___m_c_u___w_r_a_p_p_e_r.html#gad3c4ea41584d0367dfbfb697f5e57456',1,'MCU_Step_Simulation(SimStruct *S, time_T time): mcu_wrapper.c'],['../group___m_c_u___w_r_a_p_p_e_r.html#gad3c4ea41584d0367dfbfb697f5e57456',1,'MCU_Step_Simulation(SimStruct *S, time_T time): mcu_wrapper.c']]], + ['mcu_5fwriteoutputs_5',['MCU_writeOutputs',['../group___m_c_u___w_r_a_p_p_e_r.html#gad6b7bb9233d746d7709276f9ea1914c2',1,'MCU_writeOutputs(SimStruct *S): mcu_wrapper.c'],['../group___m_c_u___w_r_a_p_p_e_r.html#gad6b7bb9233d746d7709276f9ea1914c2',1,'MCU_writeOutputs(SimStruct *S): mcu_wrapper.c']]], + ['mdlinitializesampletimes_6',['mdlInitializeSampleTimes',['../group___w_r_a_p_p_e_r___s_f_u_n_c.html#ga4308a5a20d9c7060391059b1dfce872e',1,'MCU.c']]], + ['mdlinitializesizes_7',['mdlInitializeSizes',['../group___w_r_a_p_p_e_r___s_f_u_n_c.html#gab500fc17ae5e95797926ac770d903b84',1,'MCU.c']]], + ['mdloutputs_8',['mdlOutputs',['../group___w_r_a_p_p_e_r___s_f_u_n_c.html#ga52f81157111c2436496e1a9630bdce5b',1,'MCU.c']]], + ['mdlstart_9',['mdlStart',['../group___w_r_a_p_p_e_r___s_f_u_n_c.html#ga0dd07daf338cf84d1aee4bb8b6771720',1,'MCU.c']]], + ['mdlterminate_10',['mdlTerminate',['../group___w_r_a_p_p_e_r___s_f_u_n_c.html#ga343acfd8b3b5308d6c94bbf40efbbac5',1,'MCU.c']]], + ['mdlupdate_11',['mdlUpdate',['../group___w_r_a_p_p_e_r___s_f_u_n_c.html#gad3d5b495abad2acd2ae68febd1d2c5ec',1,'MCU.c']]] ]; diff --git a/DOCS/html/search/functions_5.js b/DOCS/html/search/functions_5.js index 3708ab4..db7683e 100644 --- a/DOCS/html/search/functions_5.js +++ b/DOCS/html/search/functions_5.js @@ -1,9 +1,4 @@ var searchData= [ - ['main_0',['main',['../mcu__wrapper_8c.html#a840291bc02cba5474a4cb46a9b9566fe',1,'mcu_wrapper.c']]], - ['mcu_5fapp_5fthread_1',['MCU_App_Thread',['../mcu__wrapper_8c.html#a1ea76a95b9b28061fb34ece9f6f0a85f',1,'mcu_wrapper.c']]], - ['mcu_5fperiph_5fsimulation_2',['MCU_Periph_Simulation',['../mcu__wrapper_8c.html#accdef5b45f3d1646f248304e02b00e54',1,'MCU_Periph_Simulation(void): mcu_wrapper.c'],['../mcu__wrapper__conf_8h.html#accdef5b45f3d1646f248304e02b00e54',1,'MCU_Periph_Simulation(void): mcu_wrapper.c']]], - ['mcu_5freadinputs_3',['MCU_readInputs',['../mcu__wrapper_8c.html#a15045e0feba8ddf08e20958fd1e36cd5',1,'MCU_readInputs(SimStruct *S): mcu_wrapper.c'],['../mcu__wrapper__conf_8h.html#abc7d8087f585d1d627093e18df213512',1,'MCU_readInputs(real_T *in): mcu_wrapper_conf.h']]], - ['mcu_5fstep_5fsimulation_4',['MCU_Step_Simulation',['../mcu__wrapper_8c.html#ad3c4ea41584d0367dfbfb697f5e57456',1,'MCU_Step_Simulation(SimStruct *S, time_T time): mcu_wrapper.c'],['../mcu__wrapper__conf_8h.html#ad3c4ea41584d0367dfbfb697f5e57456',1,'MCU_Step_Simulation(SimStruct *S, time_T time): mcu_wrapper.c']]], - ['mcu_5fwriteoutputs_5',['MCU_writeOutputs',['../mcu__wrapper_8c.html#ad6b7bb9233d746d7709276f9ea1914c2',1,'MCU_writeOutputs(SimStruct *S): mcu_wrapper.c'],['../mcu__wrapper__conf_8h.html#a823c4fab88e5ef9b283cee495b2524ad',1,'MCU_writeOutputs(real_T *disc): mcu_wrapper_conf.h']]] + ['overflow_5fcheck_0',['Overflow_Check',['../group___t_i_m___s_i_m_u_l_a_t_o_r.html#ga05b798408f2179ae27731f231cf4b620',1,'Overflow_Check(TIM_TypeDef *TIMx, struct TIM_Sim *TIMS): stm32f4xx_matlab_tim.c'],['../group___t_i_m___s_i_m_u_l_a_t_o_r.html#ga05b798408f2179ae27731f231cf4b620',1,'Overflow_Check(TIM_TypeDef *TIMx, struct TIM_Sim *TIMS): stm32f4xx_matlab_tim.c']]] ]; diff --git a/DOCS/html/search/functions_6.js b/DOCS/html/search/functions_6.js index 93d3a80..5db2834 100644 --- a/DOCS/html/search/functions_6.js +++ b/DOCS/html/search/functions_6.js @@ -1,5 +1,10 @@ var searchData= [ - ['nvic_5fdecodepriority_0',['NVIC_DecodePriority',['../group___c_m_s_i_s___core___n_v_i_c_functions.html#ga3387607fd8a1a32cccd77d2ac672dd96',1,'core_cm4_matlab.h']]], - ['nvic_5fencodepriority_1',['NVIC_EncodePriority',['../group___c_m_s_i_s___core___n_v_i_c_functions.html#gadb94ac5d892b376e4f3555ae0418ebac',1,'core_cm4_matlab.h']]] + ['sfunc_5fto_5fgpio_0',['SFUNC_to_GPIO',['../group___g_p_i_o___s_i_m_u_l_a_t_o_r.html#ga368334de2e425bc656526d2f42671454',1,'SFUNC_to_GPIO(real_T *in): stm32f4xx_matlab_gpio.c'],['../group___g_p_i_o___s_i_m_u_l_a_t_o_r.html#ga368334de2e425bc656526d2f42671454',1,'SFUNC_to_GPIO(real_T *out_buff): stm32f4xx_matlab_gpio.c']]], + ['sim_5fdeinitialize_5fsimulation_1',['SIM_deInitialize_Simulation',['../group___m_c_u___w_r_a_p_p_e_r.html#ga6f04b162923bada308d9668743425b92',1,'SIM_deInitialize_Simulation(void): mcu_wrapper.c'],['../group___m_c_u___w_r_a_p_p_e_r.html#ga6f04b162923bada308d9668743425b92',1,'SIM_deInitialize_Simulation(void): mcu_wrapper.c']]], + ['sim_5finitialize_5fsimulation_2',['SIM_Initialize_Simulation',['../group___m_c_u___w_r_a_p_p_e_r.html#ga54429d6d68b1d72ce16bab374e3ffa08',1,'SIM_Initialize_Simulation(void): mcu_wrapper.c'],['../group___m_c_u___w_r_a_p_p_e_r.html#ga54429d6d68b1d72ce16bab374e3ffa08',1,'SIM_Initialize_Simulation(void): mcu_wrapper.c']]], + ['sim_5fwriteoutput_3',['SIM_writeOutput',['../group___m_c_u___w_r_a_p_p_e_r.html#gad38bfad0ee1e186c0663565abb6bc71a',1,'mcu_wrapper_conf.h']]], + ['sim_5fwriteoutputs_4',['SIM_writeOutputs',['../mcu__wrapper_8c.html#a47b40a9825bcaeb3a1dfba8b27a0be3f',1,'mcu_wrapper.c']]], + ['simulate_5ftims_5',['Simulate_TIMs',['../group___t_i_m___s_i_m_u_l_a_t_o_r.html#ga3128cf64eeea541a8e25a72ce10da335',1,'Simulate_TIMs(void): stm32f4xx_matlab_tim.c'],['../group___t_i_m___s_i_m_u_l_a_t_o_r.html#ga3128cf64eeea541a8e25a72ce10da335',1,'Simulate_TIMs(void): stm32f4xx_matlab_tim.c']]], + ['slave_5fmode_5fcheck_5fsource_6',['Slave_Mode_Check_Source',['../group___t_i_m___s_i_m_u_l_a_t_o_r.html#ga60fe7ff05dcbc30ca3c35aa08e87de21',1,'Slave_Mode_Check_Source(TIM_TypeDef *TIMx): stm32f4xx_matlab_tim.c'],['../group___t_i_m___s_i_m_u_l_a_t_o_r.html#ga60fe7ff05dcbc30ca3c35aa08e87de21',1,'Slave_Mode_Check_Source(TIM_TypeDef *TIMx): stm32f4xx_matlab_tim.c']]] ]; diff --git a/DOCS/html/search/functions_7.js b/DOCS/html/search/functions_7.js index db7683e..a9aecb7 100644 --- a/DOCS/html/search/functions_7.js +++ b/DOCS/html/search/functions_7.js @@ -1,4 +1,18 @@ var searchData= [ - ['overflow_5fcheck_0',['Overflow_Check',['../group___t_i_m___s_i_m_u_l_a_t_o_r.html#ga05b798408f2179ae27731f231cf4b620',1,'Overflow_Check(TIM_TypeDef *TIMx, struct TIM_Sim *TIMS): stm32f4xx_matlab_tim.c'],['../group___t_i_m___s_i_m_u_l_a_t_o_r.html#ga05b798408f2179ae27731f231cf4b620',1,'Overflow_Check(TIM_TypeDef *TIMx, struct TIM_Sim *TIMS): stm32f4xx_matlab_tim.c']]] + ['tim1_5fbrk_5ftim9_5firqhandler_0',['TIM1_BRK_TIM9_IRQHandler',['../stm32f4xx__matlab__tim_8c.html#a3b60f6118cdd3449f4ed29fde4704236',1,'stm32f4xx_matlab_tim.c']]], + ['tim1_5ftrg_5fcom_5ftim11_5firqhandler_1',['TIM1_TRG_COM_TIM11_IRQHandler',['../stm32f4xx__matlab__tim_8c.html#a098245bf4e2f8844b22692b034a266fb',1,'stm32f4xx_matlab_tim.c']]], + ['tim1_5fup_5ftim10_5firqhandler_2',['TIM1_UP_TIM10_IRQHandler',['../stm32f4xx__matlab__tim_8c.html#ad1fd361bc5ad89facee67c76d1ff8dc0',1,'stm32f4xx_matlab_tim.c']]], + ['tim2_5firqhandler_3',['TIM2_IRQHandler',['../stm32f4xx__matlab__tim_8c.html#a38ad4725462bdc5e86c4ead4f04b9fc2',1,'stm32f4xx_matlab_tim.c']]], + ['tim3_5firqhandler_4',['TIM3_IRQHandler',['../stm32f4xx__matlab__tim_8c.html#ac8e51d2183b5230cbd5481f8867adce9',1,'stm32f4xx_matlab_tim.c']]], + ['tim4_5firqhandler_5',['TIM4_IRQHandler',['../stm32f4xx__matlab__tim_8c.html#a7133f3f78767503641d307386e68bd28',1,'stm32f4xx_matlab_tim.c']]], + ['tim5_5firqhandler_6',['TIM5_IRQHandler',['../stm32f4xx__matlab__tim_8c.html#a5e66446caf21dd90191dc07a13ce2378',1,'stm32f4xx_matlab_tim.c']]], + ['tim6_5fdac_5firqhandler_7',['TIM6_DAC_IRQHandler',['../stm32f4xx__matlab__tim_8c.html#a0839a45f331c4c067939b9c4533bbf4d',1,'stm32f4xx_matlab_tim.c']]], + ['tim7_5firqhandler_8',['TIM7_IRQHandler',['../stm32f4xx__matlab__tim_8c.html#a98cff83252098363b2dbca9608df964e',1,'stm32f4xx_matlab_tim.c']]], + ['tim8_5fbrk_5ftim12_5firqhandler_9',['TIM8_BRK_TIM12_IRQHandler',['../stm32f4xx__matlab__tim_8c.html#a301e0d3520f05f672ce047976f75ff6a',1,'stm32f4xx_matlab_tim.c']]], + ['tim8_5ftrg_5fcom_5ftim14_5firqhandler_10',['TIM8_TRG_COM_TIM14_IRQHandler',['../stm32f4xx__matlab__tim_8c.html#a4c8359a023f7ede4a9d9f94ea6fb92da',1,'stm32f4xx_matlab_tim.c']]], + ['tim8_5fup_5ftim13_5firqhandler_11',['TIM8_UP_TIM13_IRQHandler',['../stm32f4xx__matlab__tim_8c.html#a7fb516f8826d882ac91cfc093884fcf5',1,'stm32f4xx_matlab_tim.c']]], + ['tim_5fsim_5fdeinit_12',['TIM_SIM_DEINIT',['../group___t_i_m___s_i_m_u_l_a_t_o_r.html#ga52ac5ac026ea57787d19cd1a8611abba',1,'TIM_SIM_DEINIT(void): stm32f4xx_matlab_tim.c'],['../group___t_i_m___s_i_m_u_l_a_t_o_r.html#ga52ac5ac026ea57787d19cd1a8611abba',1,'TIM_SIM_DEINIT(void): stm32f4xx_matlab_tim.c']]], + ['tim_5fsimulation_13',['TIM_Simulation',['../group___t_i_m___s_i_m_u_l_a_t_o_r.html#ga3fcb4dd48557c21fdd6c379ad16bd229',1,'TIM_Simulation(TIM_TypeDef *TIMx, struct TIM_Sim *TIMS): stm32f4xx_matlab_tim.c'],['../group___t_i_m___s_i_m_u_l_a_t_o_r.html#ga3fcb4dd48557c21fdd6c379ad16bd229',1,'TIM_Simulation(TIM_TypeDef *TIMx, struct TIM_Sim *TIMS): stm32f4xx_matlab_tim.c']]], + ['timx_5fcount_14',['TIMx_Count',['../group___t_i_m___s_i_m_u_l_a_t_o_r.html#ga55e7ce9aae452502d5104acbe8fa4237',1,'TIMx_Count(TIM_TypeDef *TIMx, struct TIM_Sim *TIMS): stm32f4xx_matlab_tim.c'],['../group___t_i_m___s_i_m_u_l_a_t_o_r.html#ga55e7ce9aae452502d5104acbe8fa4237',1,'TIMx_Count(TIM_TypeDef *TIMx, struct TIM_Sim *TIMS): stm32f4xx_matlab_tim.c']]] ]; diff --git a/DOCS/html/search/functions_8.js b/DOCS/html/search/functions_8.js index 35fe03b..5f5df45 100644 --- a/DOCS/html/search/functions_8.js +++ b/DOCS/html/search/functions_8.js @@ -1,13 +1,5 @@ var searchData= [ - ['scb_5fgetfputype_0',['SCB_GetFPUType',['../group___c_m_s_i_s___core___fpu_functions.html#ga6bcad99ce80a0e7e4ddc6f2379081756',1,'core_cm4_matlab.h']]], - ['sfunc_5fto_5fgpio_1',['SFUNC_to_GPIO',['../group___g_p_i_o___s_i_m_u_l_a_t_o_r.html#ga9bce93a37f6835a1824bec5f235c9ef5',1,'SFUNC_to_GPIO(real_T *in): stm32f4xx_matlab_gpio.c'],['../group___g_p_i_o___s_i_m_u_l_a_t_o_r.html#ga9bce93a37f6835a1824bec5f235c9ef5',1,'SFUNC_to_GPIO(real_T *disc): stm32f4xx_matlab_gpio.c']]], - ['sim_5fdeinitialize_5fsimulation_2',['SIM_deInitialize_Simulation',['../mcu__wrapper_8c.html#a6f04b162923bada308d9668743425b92',1,'SIM_deInitialize_Simulation(void): mcu_wrapper.c'],['../mcu__wrapper__conf_8h.html#a6f04b162923bada308d9668743425b92',1,'SIM_deInitialize_Simulation(void): mcu_wrapper.c']]], - ['sim_5finitialize_5fsimulation_3',['SIM_Initialize_Simulation',['../mcu__wrapper_8c.html#a54429d6d68b1d72ce16bab374e3ffa08',1,'SIM_Initialize_Simulation(void): mcu_wrapper.c'],['../mcu__wrapper__conf_8h.html#a54429d6d68b1d72ce16bab374e3ffa08',1,'SIM_Initialize_Simulation(void): mcu_wrapper.c']]], - ['sim_5fwriteoutput_4',['SIM_writeOutput',['../mcu__wrapper__conf_8h.html#ad38bfad0ee1e186c0663565abb6bc71a',1,'mcu_wrapper_conf.h']]], - ['sim_5fwriteoutputs_5',['SIM_writeOutputs',['../mcu__wrapper_8c.html#a47b40a9825bcaeb3a1dfba8b27a0be3f',1,'mcu_wrapper.c']]], - ['simulate_5ftims_6',['Simulate_TIMs',['../group___t_i_m___s_i_m_u_l_a_t_o_r.html#ga3128cf64eeea541a8e25a72ce10da335',1,'Simulate_TIMs(void): stm32f4xx_matlab_tim.c'],['../group___t_i_m___s_i_m_u_l_a_t_o_r.html#ga3128cf64eeea541a8e25a72ce10da335',1,'Simulate_TIMs(void): stm32f4xx_matlab_tim.c']]], - ['slave_5fmode_5fcheck_5fsource_7',['Slave_Mode_Check_Source',['../group___t_i_m___s_i_m_u_l_a_t_o_r.html#ga9689b1f2e04622487f039dfb74d8e0db',1,'Slave_Mode_Check_Source(TIM_TypeDef *TIMx, struct TIM_Sim *TIMS): stm32f4xx_matlab_tim.c'],['../group___t_i_m___s_i_m_u_l_a_t_o_r.html#ga9689b1f2e04622487f039dfb74d8e0db',1,'Slave_Mode_Check_Source(TIM_TypeDef *TIMx, struct TIM_Sim *TIMS): stm32f4xx_matlab_tim.c']]], - ['systemcoreclockupdate_8',['SystemCoreClockUpdate',['../group___s_t_m32_f4xx___system___exported___functions.html#gae0c36a9591fe6e9c45ecb21a794f0f0f',1,'system_stm32f4xx.h']]], - ['systeminit_9',['SystemInit',['../group___s_t_m32_f4xx___system___exported___functions.html#ga93f514700ccf00d08dbdcff7f1224eb2',1,'system_stm32f4xx.h']]] + ['write_5foc_5fto_5fgpio_0',['Write_OC_to_GPIO',['../group___t_i_m___s_i_m_u_l_a_t_o_r.html#ga28ab1124ab4cfbd21acb613cb0873d2d',1,'Write_OC_to_GPIO(TIM_TypeDef *TIMx, struct TIM_Sim *TIMS): stm32f4xx_matlab_tim.c'],['../group___t_i_m___s_i_m_u_l_a_t_o_r.html#ga28ab1124ab4cfbd21acb613cb0873d2d',1,'Write_OC_to_GPIO(TIM_TypeDef *TIMx, struct TIM_Sim *TIMS): stm32f4xx_matlab_tim.c']]], + ['write_5foc_5fto_5ftrgo_1',['Write_OC_to_TRGO',['../group___t_i_m___s_i_m_u_l_a_t_o_r.html#ga4ac3f9a63d2433519bd5137bab286080',1,'Write_OC_to_TRGO(TIM_TypeDef *TIMx, struct TIM_Sim *TIMS): stm32f4xx_matlab_tim.c'],['../group___t_i_m___s_i_m_u_l_a_t_o_r.html#ga4ac3f9a63d2433519bd5137bab286080',1,'Write_OC_to_TRGO(TIM_TypeDef *TIMx, struct TIM_Sim *TIMS): stm32f4xx_matlab_tim.c']]] ]; diff --git a/DOCS/html/search/functions_9.js b/DOCS/html/search/functions_9.js deleted file mode 100644 index a9aecb7..0000000 --- a/DOCS/html/search/functions_9.js +++ /dev/null @@ -1,18 +0,0 @@ -var searchData= -[ - ['tim1_5fbrk_5ftim9_5firqhandler_0',['TIM1_BRK_TIM9_IRQHandler',['../stm32f4xx__matlab__tim_8c.html#a3b60f6118cdd3449f4ed29fde4704236',1,'stm32f4xx_matlab_tim.c']]], - ['tim1_5ftrg_5fcom_5ftim11_5firqhandler_1',['TIM1_TRG_COM_TIM11_IRQHandler',['../stm32f4xx__matlab__tim_8c.html#a098245bf4e2f8844b22692b034a266fb',1,'stm32f4xx_matlab_tim.c']]], - ['tim1_5fup_5ftim10_5firqhandler_2',['TIM1_UP_TIM10_IRQHandler',['../stm32f4xx__matlab__tim_8c.html#ad1fd361bc5ad89facee67c76d1ff8dc0',1,'stm32f4xx_matlab_tim.c']]], - ['tim2_5firqhandler_3',['TIM2_IRQHandler',['../stm32f4xx__matlab__tim_8c.html#a38ad4725462bdc5e86c4ead4f04b9fc2',1,'stm32f4xx_matlab_tim.c']]], - ['tim3_5firqhandler_4',['TIM3_IRQHandler',['../stm32f4xx__matlab__tim_8c.html#ac8e51d2183b5230cbd5481f8867adce9',1,'stm32f4xx_matlab_tim.c']]], - ['tim4_5firqhandler_5',['TIM4_IRQHandler',['../stm32f4xx__matlab__tim_8c.html#a7133f3f78767503641d307386e68bd28',1,'stm32f4xx_matlab_tim.c']]], - ['tim5_5firqhandler_6',['TIM5_IRQHandler',['../stm32f4xx__matlab__tim_8c.html#a5e66446caf21dd90191dc07a13ce2378',1,'stm32f4xx_matlab_tim.c']]], - ['tim6_5fdac_5firqhandler_7',['TIM6_DAC_IRQHandler',['../stm32f4xx__matlab__tim_8c.html#a0839a45f331c4c067939b9c4533bbf4d',1,'stm32f4xx_matlab_tim.c']]], - ['tim7_5firqhandler_8',['TIM7_IRQHandler',['../stm32f4xx__matlab__tim_8c.html#a98cff83252098363b2dbca9608df964e',1,'stm32f4xx_matlab_tim.c']]], - ['tim8_5fbrk_5ftim12_5firqhandler_9',['TIM8_BRK_TIM12_IRQHandler',['../stm32f4xx__matlab__tim_8c.html#a301e0d3520f05f672ce047976f75ff6a',1,'stm32f4xx_matlab_tim.c']]], - ['tim8_5ftrg_5fcom_5ftim14_5firqhandler_10',['TIM8_TRG_COM_TIM14_IRQHandler',['../stm32f4xx__matlab__tim_8c.html#a4c8359a023f7ede4a9d9f94ea6fb92da',1,'stm32f4xx_matlab_tim.c']]], - ['tim8_5fup_5ftim13_5firqhandler_11',['TIM8_UP_TIM13_IRQHandler',['../stm32f4xx__matlab__tim_8c.html#a7fb516f8826d882ac91cfc093884fcf5',1,'stm32f4xx_matlab_tim.c']]], - ['tim_5fsim_5fdeinit_12',['TIM_SIM_DEINIT',['../group___t_i_m___s_i_m_u_l_a_t_o_r.html#ga52ac5ac026ea57787d19cd1a8611abba',1,'TIM_SIM_DEINIT(void): stm32f4xx_matlab_tim.c'],['../group___t_i_m___s_i_m_u_l_a_t_o_r.html#ga52ac5ac026ea57787d19cd1a8611abba',1,'TIM_SIM_DEINIT(void): stm32f4xx_matlab_tim.c']]], - ['tim_5fsimulation_13',['TIM_Simulation',['../group___t_i_m___s_i_m_u_l_a_t_o_r.html#ga3fcb4dd48557c21fdd6c379ad16bd229',1,'TIM_Simulation(TIM_TypeDef *TIMx, struct TIM_Sim *TIMS): stm32f4xx_matlab_tim.c'],['../group___t_i_m___s_i_m_u_l_a_t_o_r.html#ga3fcb4dd48557c21fdd6c379ad16bd229',1,'TIM_Simulation(TIM_TypeDef *TIMx, struct TIM_Sim *TIMS): stm32f4xx_matlab_tim.c']]], - ['timx_5fcount_14',['TIMx_Count',['../group___t_i_m___s_i_m_u_l_a_t_o_r.html#ga55e7ce9aae452502d5104acbe8fa4237',1,'TIMx_Count(TIM_TypeDef *TIMx, struct TIM_Sim *TIMS): stm32f4xx_matlab_tim.c'],['../group___t_i_m___s_i_m_u_l_a_t_o_r.html#ga55e7ce9aae452502d5104acbe8fa4237',1,'TIMx_Count(TIM_TypeDef *TIMx, struct TIM_Sim *TIMS): stm32f4xx_matlab_tim.c']]] -]; diff --git a/DOCS/html/search/functions_a.js b/DOCS/html/search/functions_a.js deleted file mode 100644 index 5f5df45..0000000 --- a/DOCS/html/search/functions_a.js +++ /dev/null @@ -1,5 +0,0 @@ -var searchData= -[ - ['write_5foc_5fto_5fgpio_0',['Write_OC_to_GPIO',['../group___t_i_m___s_i_m_u_l_a_t_o_r.html#ga28ab1124ab4cfbd21acb613cb0873d2d',1,'Write_OC_to_GPIO(TIM_TypeDef *TIMx, struct TIM_Sim *TIMS): stm32f4xx_matlab_tim.c'],['../group___t_i_m___s_i_m_u_l_a_t_o_r.html#ga28ab1124ab4cfbd21acb613cb0873d2d',1,'Write_OC_to_GPIO(TIM_TypeDef *TIMx, struct TIM_Sim *TIMS): stm32f4xx_matlab_tim.c']]], - ['write_5foc_5fto_5ftrgo_1',['Write_OC_to_TRGO',['../group___t_i_m___s_i_m_u_l_a_t_o_r.html#ga4ac3f9a63d2433519bd5137bab286080',1,'Write_OC_to_TRGO(TIM_TypeDef *TIMx, struct TIM_Sim *TIMS): stm32f4xx_matlab_tim.c'],['../group___t_i_m___s_i_m_u_l_a_t_o_r.html#ga4ac3f9a63d2433519bd5137bab286080',1,'Write_OC_to_TRGO(TIM_TypeDef *TIMx, struct TIM_Sim *TIMS): stm32f4xx_matlab_tim.c']]] -]; diff --git a/DOCS/html/search/groups_0.js b/DOCS/html/search/groups_0.js index 5118a9a..2f08e02 100644 --- a/DOCS/html/search/groups_0.js +++ b/DOCS/html/search/groups_0.js @@ -1,7 +1,5 @@ var searchData= [ - ['and_20control_20registers_0',['Status and Control Registers',['../group___c_m_s_i_s___c_o_r_e.html',1,'']]], - ['and_20instructions_20reference_1',['Functions and Instructions Reference',['../group___c_m_s_i_s___core___function_interface.html',1,'']]], - ['and_20trace_20dwt_2',['Data Watchpoint and Trace (DWT)',['../group___c_m_s_i_s___d_w_t.html',1,'']]], - ['and_20type_20definitions_3',['Defines and Type Definitions',['../group___c_m_s_i_s__core__register.html',1,'']]] + ['configuration_0',['Configuration',['../group___s_i_m_u_l_a_t_o_r___c_o_n_f.html',1,'Simulator Configuration'],['../group___w_r_a_p_p_e_r___c_o_n_f.html',1,'Wrapper Configuration']]], + ['core_20definitions_1',['Core Definitions',['../group___c_m_s_i_s__core__base.html',1,'']]] ]; diff --git a/DOCS/html/search/groups_1.js b/DOCS/html/search/groups_1.js index ac79163..1b5f948 100644 --- a/DOCS/html/search/groups_1.js +++ b/DOCS/html/search/groups_1.js @@ -1,5 +1,5 @@ var searchData= [ - ['bit_20field_20macros_0',['Core register bit field macros',['../group___c_m_s_i_s__core__bitfield.html',1,'']]], - ['block_20scb_1',['System Control Block (SCB)',['../group___c_m_s_i_s___s_c_b.html',1,'']]] + ['debugging_0',['Periphs Variables for Debugging',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html',1,'']]], + ['definitions_1',['Core Definitions',['../group___c_m_s_i_s__core__base.html',1,'']]] ]; diff --git a/DOCS/html/search/groups_10.js b/DOCS/html/search/groups_10.js deleted file mode 100644 index 259b8d7..0000000 --- a/DOCS/html/search/groups_10.js +++ /dev/null @@ -1,4 +0,0 @@ -var searchData= -[ - ['unit_20fpu_0',['Floating Point Unit (FPU)',['../group___c_m_s_i_s___f_p_u.html',1,'']]] -]; diff --git a/DOCS/html/search/groups_11.js b/DOCS/html/search/groups_11.js deleted file mode 100644 index a5f8f94..0000000 --- a/DOCS/html/search/groups_11.js +++ /dev/null @@ -1,4 +0,0 @@ -var searchData= -[ - ['vectored_20interrupt_20controller_20nvic_0',['Nested Vectored Interrupt Controller (NVIC)',['../group___c_m_s_i_s___n_v_i_c.html',1,'']]] -]; diff --git a/DOCS/html/search/groups_12.js b/DOCS/html/search/groups_12.js deleted file mode 100644 index e6159ac..0000000 --- a/DOCS/html/search/groups_12.js +++ /dev/null @@ -1,5 +0,0 @@ -var searchData= -[ - ['watchpoint_20and_20trace_20dwt_0',['Data Watchpoint and Trace (DWT)',['../group___c_m_s_i_s___d_w_t.html',1,'']]], - ['wrapper_5fconf_1',['WRAPPER_CONF',['../group___w_r_a_p_p_e_r___c_o_n_f.html',1,'']]] -]; diff --git a/DOCS/html/search/groups_2.js b/DOCS/html/search/groups_2.js index 91b7b5e..9f297a7 100644 --- a/DOCS/html/search/groups_2.js +++ b/DOCS/html/search/groups_2.js @@ -1,15 +1,6 @@ var searchData= [ - ['cmsis_0',['CMSIS',['../group___c_m_s_i_s.html',1,'']]], - ['cmsis_20global_20defines_1',['CMSIS Global Defines',['../group___c_m_s_i_s__glob__defs.html',1,'']]], - ['cmsis_5fdevice_2',['CMSIS_Device',['../group___c_m_s_i_s___device.html',1,'']]], - ['configuration_5fsection_5ffor_5fcmsis_3',['Configuration_section_for_CMSIS',['../group___configuration__section__for___c_m_s_i_s.html',1,'']]], - ['control_20block_20scb_4',['System Control Block (SCB)',['../group___c_m_s_i_s___s_c_b.html',1,'']]], - ['control_20registers_5',['Status and Control Registers',['../group___c_m_s_i_s___c_o_r_e.html',1,'']]], - ['controller_20nvic_6',['Nested Vectored Interrupt Controller (NVIC)',['../group___c_m_s_i_s___n_v_i_c.html',1,'']]], - ['controls_20not_20in_20scb_20scnscb_7',['System Controls not in SCB (SCnSCB)',['../group___c_m_s_i_s___s_cn_s_c_b.html',1,'']]], - ['core_20debug_20registers_20coredebug_8',['Core Debug Registers (CoreDebug)',['../group___c_m_s_i_s___core_debug.html',1,'']]], - ['core_20definitions_9',['Core Definitions',['../group___c_m_s_i_s__core__base.html',1,'']]], - ['core_20register_20bit_20field_20macros_10',['Core register bit field macros',['../group___c_m_s_i_s__core__bitfield.html',1,'']]], - ['coredebug_11',['Core Debug Registers (CoreDebug)',['../group___c_m_s_i_s___core_debug.html',1,'']]] + ['for_20debugging_0',['Periphs Variables for Debugging',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html',1,'']]], + ['function_20funtions_1',['S-Function funtions',['../group___w_r_a_p_p_e_r___s_f_u_n_c.html',1,'']]], + ['funtions_2',['S-Function funtions',['../group___w_r_a_p_p_e_r___s_f_u_n_c.html',1,'']]] ]; diff --git a/DOCS/html/search/groups_3.js b/DOCS/html/search/groups_3.js index f1fc986..d5a7ebf 100644 --- a/DOCS/html/search/groups_3.js +++ b/DOCS/html/search/groups_3.js @@ -1,10 +1,4 @@ var searchData= [ - ['data_20watchpoint_20and_20trace_20dwt_0',['Data Watchpoint and Trace (DWT)',['../group___c_m_s_i_s___d_w_t.html',1,'']]], - ['debug_20registers_20coredebug_1',['Core Debug Registers (CoreDebug)',['../group___c_m_s_i_s___core_debug.html',1,'']]], - ['defines_2',['CMSIS Global Defines',['../group___c_m_s_i_s__glob__defs.html',1,'']]], - ['defines_20and_20type_20definitions_3',['Defines and Type Definitions',['../group___c_m_s_i_s__core__register.html',1,'']]], - ['definitions_4',['Definitions',['../group___c_m_s_i_s__core__base.html',1,'Core Definitions'],['../group___c_m_s_i_s__core__register.html',1,'Defines and Type Definitions']]], - ['device_5fincluded_5',['Device_Included',['../group___device___included.html',1,'']]], - ['dwt_6',['Data Watchpoint and Trace (DWT)',['../group___c_m_s_i_s___d_w_t.html',1,'']]] + ['gpio_20simulator_0',['GPIO Simulator',['../group___g_p_i_o___s_i_m_u_l_a_t_o_r.html',1,'']]] ]; diff --git a/DOCS/html/search/groups_4.js b/DOCS/html/search/groups_4.js index e5f251b..01b8a74 100644 --- a/DOCS/html/search/groups_4.js +++ b/DOCS/html/search/groups_4.js @@ -1,7 +1,6 @@ var searchData= [ - ['exported_5fconstants_0',['Exported_constants',['../group___exported__constants.html',1,'']]], - ['exported_5fmacro_1',['Exported_macro',['../group___exported__macro.html',1,'']]], - ['exported_5fmacros_2',['Exported_macros',['../group___exported__macros.html',1,'']]], - ['exported_5ftypes_3',['Exported_types',['../group___exported__types.html',1,'']]] + ['map_0',['Peripheral Memory Map',['../group___peripheral__memory__map.html',1,'']]], + ['mcu_20wrapper_1',['MCU Wrapper',['../group___m_c_u___w_r_a_p_p_e_r.html',1,'']]], + ['memory_20map_2',['Peripheral Memory Map',['../group___peripheral__memory__map.html',1,'']]] ]; diff --git a/DOCS/html/search/groups_5.js b/DOCS/html/search/groups_5.js index 2676cfa..d824e5f 100644 --- a/DOCS/html/search/groups_5.js +++ b/DOCS/html/search/groups_5.js @@ -1,9 +1,5 @@ var searchData= [ - ['field_20macros_0',['Core register bit field macros',['../group___c_m_s_i_s__core__bitfield.html',1,'']]], - ['floating_20point_20unit_20fpu_1',['Floating Point Unit (FPU)',['../group___c_m_s_i_s___f_p_u.html',1,'']]], - ['fpu_2',['Floating Point Unit (FPU)',['../group___c_m_s_i_s___f_p_u.html',1,'']]], - ['fpu_20functions_3',['FPU Functions',['../group___c_m_s_i_s___core___fpu_functions.html',1,'']]], - ['functions_4',['Functions',['../group___c_m_s_i_s___core___fpu_functions.html',1,'FPU Functions'],['../group___c_m_s_i_s__core___debug_functions.html',1,'ITM Functions'],['../group___c_m_s_i_s___core___n_v_i_c_functions.html',1,'NVIC Functions'],['../group___c_m_s_i_s___core___sys_tick_functions.html',1,'SysTick Functions']]], - ['functions_20and_20instructions_20reference_5',['Functions and Instructions Reference',['../group___c_m_s_i_s___core___function_interface.html',1,'']]] + ['peripheral_20memory_20map_0',['Peripheral Memory Map',['../group___peripheral__memory__map.html',1,'']]], + ['periphs_20variables_20for_20debugging_1',['Periphs Variables for Debugging',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html',1,'']]] ]; diff --git a/DOCS/html/search/groups_6.js b/DOCS/html/search/groups_6.js index 814a1d1..218a879 100644 --- a/DOCS/html/search/groups_6.js +++ b/DOCS/html/search/groups_6.js @@ -1,5 +1,4 @@ var searchData= [ - ['global_20defines_0',['CMSIS Global Defines',['../group___c_m_s_i_s__glob__defs.html',1,'']]], - ['gpio_5fsimulator_1',['GPIO_SIMULATOR',['../group___g_p_i_o___s_i_m_u_l_a_t_o_r.html',1,'']]] + ['rcc_20simulator_0',['RCC Simulator',['../group___r_c_c___s_i_m_u_l_a_t_o_r.html',1,'']]] ]; diff --git a/DOCS/html/search/groups_7.js b/DOCS/html/search/groups_7.js index a7afd63..dd45eff 100644 --- a/DOCS/html/search/groups_7.js +++ b/DOCS/html/search/groups_7.js @@ -1,4 +1,9 @@ var searchData= [ - ['hardware_5fconstant_5fdefinition_0',['Hardware_Constant_Definition',['../group___hardware___constant___definition.html',1,'']]] + ['s_20function_20funtions_0',['S-Function funtions',['../group___w_r_a_p_p_e_r___s_f_u_n_c.html',1,'']]], + ['simulation_1',['STM32 Simulation',['../group___s_t_m___s_i_m_u_l_a_t_i_o_n.html',1,'']]], + ['simulator_2',['Simulator',['../group___g_p_i_o___s_i_m_u_l_a_t_o_r.html',1,'GPIO Simulator'],['../group___r_c_c___s_i_m_u_l_a_t_o_r.html',1,'RCC Simulator'],['../group___m_a_i_n___s_i_m_u_l_a_t_o_r.html',1,'STM32 Simulator'],['../group___t_i_m___s_i_m_u_l_a_t_o_r.html',1,'TIM Simulator']]], + ['simulator_20configuration_3',['Simulator Configuration',['../group___s_i_m_u_l_a_t_o_r___c_o_n_f.html',1,'']]], + ['stm32_20simulation_4',['STM32 Simulation',['../group___s_t_m___s_i_m_u_l_a_t_i_o_n.html',1,'']]], + ['stm32_20simulator_5',['STM32 Simulator',['../group___m_a_i_n___s_i_m_u_l_a_t_o_r.html',1,'']]] ]; diff --git a/DOCS/html/search/groups_8.js b/DOCS/html/search/groups_8.js index d37807b..38ed17f 100644 --- a/DOCS/html/search/groups_8.js +++ b/DOCS/html/search/groups_8.js @@ -1,10 +1,4 @@ var searchData= [ - ['in_20scb_20scnscb_0',['System Controls not in SCB (SCnSCB)',['../group___c_m_s_i_s___s_cn_s_c_b.html',1,'']]], - ['instructions_20reference_1',['Functions and Instructions Reference',['../group___c_m_s_i_s___core___function_interface.html',1,'']]], - ['instrumentation_20trace_20macrocell_20itm_2',['Instrumentation Trace Macrocell (ITM)',['../group___c_m_s_i_s___i_t_m.html',1,'']]], - ['interface_20tpi_3',['Trace Port Interface (TPI)',['../group___c_m_s_i_s___t_p_i.html',1,'']]], - ['interrupt_20controller_20nvic_4',['Nested Vectored Interrupt Controller (NVIC)',['../group___c_m_s_i_s___n_v_i_c.html',1,'']]], - ['itm_5',['Instrumentation Trace Macrocell (ITM)',['../group___c_m_s_i_s___i_t_m.html',1,'']]], - ['itm_20functions_6',['ITM Functions',['../group___c_m_s_i_s__core___debug_functions.html',1,'']]] + ['tim_20simulator_0',['TIM Simulator',['../group___t_i_m___s_i_m_u_l_a_t_o_r.html',1,'']]] ]; diff --git a/DOCS/html/search/groups_9.js b/DOCS/html/search/groups_9.js index e865188..c68f11c 100644 --- a/DOCS/html/search/groups_9.js +++ b/DOCS/html/search/groups_9.js @@ -1,4 +1,4 @@ var searchData= [ - ['library_5fconfiguration_5fsection_0',['Library_configuration_section',['../group___library__configuration__section.html',1,'']]] + ['variables_20for_20debugging_0',['Periphs Variables for Debugging',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html',1,'']]] ]; diff --git a/DOCS/html/search/groups_a.js b/DOCS/html/search/groups_a.js index 97f46fd..aa3c1e6 100644 --- a/DOCS/html/search/groups_a.js +++ b/DOCS/html/search/groups_a.js @@ -1,7 +1,5 @@ var searchData= [ - ['macrocell_20itm_0',['Instrumentation Trace Macrocell (ITM)',['../group___c_m_s_i_s___i_t_m.html',1,'']]], - ['macros_1',['Core register bit field macros',['../group___c_m_s_i_s__core__bitfield.html',1,'']]], - ['main_5fsimulator_2',['MAIN_SIMULATOR',['../group___m_a_i_n___s_i_m_u_l_a_t_o_r.html',1,'']]], - ['mcu_5fwrapper_3',['MCU_WRAPPER',['../group___m_c_u___w_r_a_p_p_e_r.html',1,'']]] + ['wrapper_0',['MCU Wrapper',['../group___m_c_u___w_r_a_p_p_e_r.html',1,'']]], + ['wrapper_20configuration_1',['Wrapper Configuration',['../group___w_r_a_p_p_e_r___c_o_n_f.html',1,'']]] ]; diff --git a/DOCS/html/search/groups_b.js b/DOCS/html/search/groups_b.js deleted file mode 100644 index 9ac90be..0000000 --- a/DOCS/html/search/groups_b.js +++ /dev/null @@ -1,7 +0,0 @@ -var searchData= -[ - ['nested_20vectored_20interrupt_20controller_20nvic_0',['Nested Vectored Interrupt Controller (NVIC)',['../group___c_m_s_i_s___n_v_i_c.html',1,'']]], - ['not_20in_20scb_20scnscb_1',['System Controls not in SCB (SCnSCB)',['../group___c_m_s_i_s___s_cn_s_c_b.html',1,'']]], - ['nvic_2',['Nested Vectored Interrupt Controller (NVIC)',['../group___c_m_s_i_s___n_v_i_c.html',1,'']]], - ['nvic_20functions_3',['NVIC Functions',['../group___c_m_s_i_s___core___n_v_i_c_functions.html',1,'']]] -]; diff --git a/DOCS/html/search/groups_c.js b/DOCS/html/search/groups_c.js deleted file mode 100644 index 18b8288..0000000 --- a/DOCS/html/search/groups_c.js +++ /dev/null @@ -1,11 +0,0 @@ -var searchData= -[ - ['periph_5fvars_5ffor_5fdebug_0',['PERIPH_VARS_FOR_DEBUG',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html',1,'']]], - ['peripheral_5fdeclaration_1',['Peripheral_declaration',['../group___peripheral__declaration.html',1,'']]], - ['peripheral_5finterrupt_5fnumber_5fdefinition_2',['Peripheral_interrupt_number_definition',['../group___peripheral__interrupt__number__definition.html',1,'']]], - ['peripheral_5fmemory_5fmap_3',['Peripheral_memory_map',['../group___peripheral__memory__map.html',1,'']]], - ['peripheral_5fregisters_5fbits_5fdefinition_4',['Peripheral_Registers_Bits_Definition',['../group___peripheral___registers___bits___definition.html',1,'']]], - ['peripheral_5fregisters_5fstructures_5',['Peripheral_registers_structures',['../group___peripheral__registers__structures.html',1,'']]], - ['point_20unit_20fpu_6',['Floating Point Unit (FPU)',['../group___c_m_s_i_s___f_p_u.html',1,'']]], - ['port_20interface_20tpi_7',['Trace Port Interface (TPI)',['../group___c_m_s_i_s___t_p_i.html',1,'']]] -]; diff --git a/DOCS/html/search/groups_d.js b/DOCS/html/search/groups_d.js deleted file mode 100644 index 7e8625f..0000000 --- a/DOCS/html/search/groups_d.js +++ /dev/null @@ -1,8 +0,0 @@ -var searchData= -[ - ['rcc_5fsimulator_0',['RCC_SIMULATOR',['../group___r_c_c___s_i_m_u_l_a_t_o_r.html',1,'']]], - ['reference_1',['Functions and Instructions Reference',['../group___c_m_s_i_s___core___function_interface.html',1,'']]], - ['register_20bit_20field_20macros_2',['Core register bit field macros',['../group___c_m_s_i_s__core__bitfield.html',1,'']]], - ['registers_3',['Status and Control Registers',['../group___c_m_s_i_s___c_o_r_e.html',1,'']]], - ['registers_20coredebug_4',['Core Debug Registers (CoreDebug)',['../group___c_m_s_i_s___core_debug.html',1,'']]] -]; diff --git a/DOCS/html/search/groups_e.js b/DOCS/html/search/groups_e.js deleted file mode 100644 index 48be8b4..0000000 --- a/DOCS/html/search/groups_e.js +++ /dev/null @@ -1,22 +0,0 @@ -var searchData= -[ - ['scb_0',['System Control Block (SCB)',['../group___c_m_s_i_s___s_c_b.html',1,'']]], - ['scb_20scnscb_1',['System Controls not in SCB (SCnSCB)',['../group___c_m_s_i_s___s_cn_s_c_b.html',1,'']]], - ['scnscb_2',['System Controls not in SCB (SCnSCB)',['../group___c_m_s_i_s___s_cn_s_c_b.html',1,'']]], - ['simulator_5fconf_3',['SIMULATOR_CONF',['../group___s_i_m_u_l_a_t_o_r___c_o_n_f.html',1,'']]], - ['status_20and_20control_20registers_4',['Status and Control Registers',['../group___c_m_s_i_s___c_o_r_e.html',1,'']]], - ['stm32f407xx_5',['Stm32f407xx',['../group__stm32f407xx.html',1,'']]], - ['stm32f4xx_6',['Stm32f4xx',['../group__stm32f4xx.html',1,'']]], - ['stm32f4xx_5fsystem_7',['Stm32f4xx_system',['../group__stm32f4xx__system.html',1,'']]], - ['stm32f4xx_5fsystem_5fexported_5fconstants_8',['STM32F4xx_System_Exported_Constants',['../group___s_t_m32_f4xx___system___exported___constants.html',1,'']]], - ['stm32f4xx_5fsystem_5fexported_5ffunctions_9',['STM32F4xx_System_Exported_Functions',['../group___s_t_m32_f4xx___system___exported___functions.html',1,'']]], - ['stm32f4xx_5fsystem_5fexported_5fmacros_10',['STM32F4xx_System_Exported_Macros',['../group___s_t_m32_f4xx___system___exported___macros.html',1,'']]], - ['stm32f4xx_5fsystem_5fexported_5ftypes_11',['STM32F4xx_System_Exported_types',['../group___s_t_m32_f4xx___system___exported__types.html',1,'']]], - ['stm32f4xx_5fsystem_5fincludes_12',['STM32F4xx_System_Includes',['../group___s_t_m32_f4xx___system___includes.html',1,'']]], - ['stm_5fsimulation_13',['STM_SIMULATION',['../group___s_t_m___s_i_m_u_l_a_t_i_o_n.html',1,'']]], - ['system_20control_20block_20scb_14',['System Control Block (SCB)',['../group___c_m_s_i_s___s_c_b.html',1,'']]], - ['system_20controls_20not_20in_20scb_20scnscb_15',['System Controls not in SCB (SCnSCB)',['../group___c_m_s_i_s___s_cn_s_c_b.html',1,'']]], - ['system_20tick_20timer_20systick_16',['System Tick Timer (SysTick)',['../group___c_m_s_i_s___sys_tick.html',1,'']]], - ['systick_17',['System Tick Timer (SysTick)',['../group___c_m_s_i_s___sys_tick.html',1,'']]], - ['systick_20functions_18',['SysTick Functions',['../group___c_m_s_i_s___core___sys_tick_functions.html',1,'']]] -]; diff --git a/DOCS/html/search/groups_f.js b/DOCS/html/search/groups_f.js deleted file mode 100644 index a47ef07..0000000 --- a/DOCS/html/search/groups_f.js +++ /dev/null @@ -1,11 +0,0 @@ -var searchData= -[ - ['tick_20timer_20systick_0',['System Tick Timer (SysTick)',['../group___c_m_s_i_s___sys_tick.html',1,'']]], - ['tim_5fsimulator_1',['TIM_SIMULATOR',['../group___t_i_m___s_i_m_u_l_a_t_o_r.html',1,'']]], - ['timer_20systick_2',['System Tick Timer (SysTick)',['../group___c_m_s_i_s___sys_tick.html',1,'']]], - ['tpi_3',['Trace Port Interface (TPI)',['../group___c_m_s_i_s___t_p_i.html',1,'']]], - ['trace_20dwt_4',['Data Watchpoint and Trace (DWT)',['../group___c_m_s_i_s___d_w_t.html',1,'']]], - ['trace_20macrocell_20itm_5',['Instrumentation Trace Macrocell (ITM)',['../group___c_m_s_i_s___i_t_m.html',1,'']]], - ['trace_20port_20interface_20tpi_6',['Trace Port Interface (TPI)',['../group___c_m_s_i_s___t_p_i.html',1,'']]], - ['type_20definitions_7',['Defines and Type Definitions',['../group___c_m_s_i_s__core__register.html',1,'']]] -]; diff --git a/DOCS/html/search/pages_0.js b/DOCS/html/search/pages_0.js index ea86c6c..f27fc99 100644 --- a/DOCS/html/search/pages_0.js +++ b/DOCS/html/search/pages_0.js @@ -1,4 +1,4 @@ var searchData= [ - ['emulator_0',['MATLAB STM32 EMULATOR',['../md__f_1_2_work_2_projects_2_m_a_t_l_a_b_2matlab__stm__emulate_2_r_e_a_d_m_e.html',1,'']]] + ['emulator_0',['MATLAB STM32 EMULATOR',['../index.html',1,'']]] ]; diff --git a/DOCS/html/search/pages_1.js b/DOCS/html/search/pages_1.js index 6e30f0e..ef5c708 100644 --- a/DOCS/html/search/pages_1.js +++ b/DOCS/html/search/pages_1.js @@ -1,4 +1,4 @@ var searchData= [ - ['matlab_20stm32_20emulator_0',['MATLAB STM32 EMULATOR',['../md__f_1_2_work_2_projects_2_m_a_t_l_a_b_2matlab__stm__emulate_2_r_e_a_d_m_e.html',1,'']]] + ['matlab_20stm32_20emulator_0',['MATLAB STM32 EMULATOR',['../index.html',1,'']]] ]; diff --git a/DOCS/html/search/pages_2.js b/DOCS/html/search/pages_2.js index 09b57dd..6eba325 100644 --- a/DOCS/html/search/pages_2.js +++ b/DOCS/html/search/pages_2.js @@ -1,4 +1,4 @@ var searchData= [ - ['stm32_20emulator_0',['MATLAB STM32 EMULATOR',['../md__f_1_2_work_2_projects_2_m_a_t_l_a_b_2matlab__stm__emulate_2_r_e_a_d_m_e.html',1,'']]] + ['stm32_20emulator_0',['MATLAB STM32 EMULATOR',['../index.html',1,'']]] ]; diff --git a/DOCS/html/search/searchdata.js b/DOCS/html/search/searchdata.js index 2d1e512..db9cebc 100644 --- a/DOCS/html/search/searchdata.js +++ b/DOCS/html/search/searchdata.js @@ -1,16 +1,13 @@ var indexSectionsWithContent = { - 0: "_abcdefghijklmnopqrstuvwxzдзикмопÑÑ", - 1: "_acdefginprstuwx", - 2: "acmrs", - 3: "_cdgimnostw", - 4: "_abcdefghijklmnopqrstuvwz", - 5: "himu", - 6: "efi", - 7: "abcdefimnoprstuw", - 8: "_imnpsuw", - 9: "abcdefghilmnprstuvw", - 10: "ems" + 0: "_abcdefghimnoprstuvwдзикмопÑÑ", + 1: "_cst", + 2: "mrs", + 3: "cdgimostw", + 4: "abcdefghimoprstuw", + 5: "hm", + 6: "cdfgmprstvw", + 7: "ems" }; var indexSectionNames = @@ -21,11 +18,8 @@ var indexSectionNames = 3: "functions", 4: "variables", 5: "typedefs", - 6: "enums", - 7: "enumvalues", - 8: "defines", - 9: "groups", - 10: "pages" + 6: "groups", + 7: "pages" }; var indexSectionLabels = @@ -36,10 +30,7 @@ var indexSectionLabels = 3: "Functions", 4: "Variables", 5: "Typedefs", - 6: "Enumerations", - 7: "Enumerator", - 8: "Macros", - 9: "Modules", - 10: "Pages" + 6: "Modules", + 7: "Pages" }; diff --git a/DOCS/html/search/typedefs_1.js b/DOCS/html/search/typedefs_1.js index 30d1ff8..8e27057 100644 --- a/DOCS/html/search/typedefs_1.js +++ b/DOCS/html/search/typedefs_1.js @@ -1,18 +1,5 @@ var searchData= [ - ['int16_5ft_0',['int16_t',['../stdint_8h.html#aa5ad9bec438b7cf669efb1ca064e79f5',1,'stdint.h']]], - ['int32_5ft_1',['int32_t',['../stdint_8h.html#ab1967d8591af1a4e48c37fd2b0f184d0',1,'stdint.h']]], - ['int64_5ft_2',['int64_t',['../stdint_8h.html#a0c9423d16eef222e84c3690e1254d4fc',1,'stdint.h']]], - ['int8_5ft_3',['int8_t',['../stdint_8h.html#aef44329758059c91c76d334e8fc09700',1,'stdint.h']]], - ['int_5ffast16_5ft_4',['int_fast16_t',['../stdint_8h.html#a89a76a94f66a28fb25fa1548b05297bf',1,'stdint.h']]], - ['int_5ffast32_5ft_5',['int_fast32_t',['../stdint_8h.html#ae884dda22bf64c7e974894a6d3b67929',1,'stdint.h']]], - ['int_5ffast64_5ft_6',['int_fast64_t',['../stdint_8h.html#a1ea692df2dbaf0e6fd4d04e505b56dd9',1,'stdint.h']]], - ['int_5ffast8_5ft_7',['int_fast8_t',['../stdint_8h.html#a3ea64e25c86718ee706162b247d8c424',1,'stdint.h']]], - ['int_5fleast16_5ft_8',['int_least16_t',['../stdint_8h.html#ad05f554db4d3cb2fe5ca66f316bc9452',1,'stdint.h']]], - ['int_5fleast32_5ft_9',['int_least32_t',['../stdint_8h.html#a1ef09861eb7bed037170ba0025f664bf',1,'stdint.h']]], - ['int_5fleast64_5ft_10',['int_least64_t',['../stdint_8h.html#aa84e4a614844da82f79a3ef8ba848c89',1,'stdint.h']]], - ['int_5fleast8_5ft_11',['int_least8_t',['../stdint_8h.html#ae04fa5ea5ad475bfe428842a986fbf28',1,'stdint.h']]], - ['intmax_5ft_12',['intmax_t',['../stdint_8h.html#ad5fc31e4f9356d76775e1e619d2e0286',1,'stdint.h']]], - ['intptr_5ft_13',['intptr_t',['../stdint_8h.html#aaadb3b51e475a79bc209cfbdb4d6e579',1,'stdint.h']]], - ['itstatus_14',['ITStatus',['../group___exported__types.html#ga39d4411201fb731279ad5a409b2b80d7',1,'stm32f4xx.h']]] + ['mcu_5fcortexmemorytypedef_0',['MCU_CortexMemoryTypeDef',['../group___c_m_s_i_s__core__base.html#ga2283564fd240ac8b420f104dc381ce94',1,'stm32f407xx_matlab_memory.h']]], + ['mcu_5fmemorytypedef_1',['MCU_MemoryTypeDef',['../group___peripheral__memory__map.html#ga304d35aeeebef1445af976d8a5248d57',1,'stm32f407xx_matlab_memory.h']]] ]; diff --git a/DOCS/html/search/typedefs_2.js b/DOCS/html/search/typedefs_2.js deleted file mode 100644 index 6fada79..0000000 --- a/DOCS/html/search/typedefs_2.js +++ /dev/null @@ -1,5 +0,0 @@ -var searchData= -[ - ['mcu_5fcortexmemorytypedef_0',['MCU_CortexMemoryTypeDef',['../group___c_m_s_i_s__core__base.html#ga2283564fd240ac8b420f104dc381ce94',1,'core_cm4_matlab.h']]], - ['mcu_5fmemorytypedef_1',['MCU_MemoryTypeDef',['../group___peripheral__memory__map.html#ga304d35aeeebef1445af976d8a5248d57',1,'stm32f407xx_matlab.h']]] -]; diff --git a/DOCS/html/search/typedefs_3.js b/DOCS/html/search/typedefs_3.js deleted file mode 100644 index eeb067f..0000000 --- a/DOCS/html/search/typedefs_3.js +++ /dev/null @@ -1,17 +0,0 @@ -var searchData= -[ - ['uint16_5ft_0',['uint16_t',['../stdint_8h.html#adf4d876453337156dde61095e1f20223',1,'stdint.h']]], - ['uint32_5ft_1',['uint32_t',['../stdint_8h.html#a435d1572bf3f880d55459d9805097f62',1,'stdint.h']]], - ['uint64_5ft_2',['uint64_t',['../stdint_8h.html#aeaec22c681a555c831cfc2337189a4da',1,'stdint.h']]], - ['uint8_5ft_3',['uint8_t',['../stdint_8h.html#aba7bc1797add20fe3efdf37ced1182c5',1,'stdint.h']]], - ['uint_5ffast16_5ft_4',['uint_fast16_t',['../stdint_8h.html#a226d967fb6d06433caf43f20dc876aae',1,'stdint.h']]], - ['uint_5ffast32_5ft_5',['uint_fast32_t',['../stdint_8h.html#a633264eb9df8f0520acccbbfb406f806',1,'stdint.h']]], - ['uint_5ffast64_5ft_6',['uint_fast64_t',['../stdint_8h.html#a231d03c9e26ec4bdeddf882b02354b40',1,'stdint.h']]], - ['uint_5ffast8_5ft_7',['uint_fast8_t',['../stdint_8h.html#ad0906fbe05a45fbdb000c58fe8929e70',1,'stdint.h']]], - ['uint_5fleast16_5ft_8',['uint_least16_t',['../stdint_8h.html#a1bae72af13d35bac8eb9424db7e27bf1',1,'stdint.h']]], - ['uint_5fleast32_5ft_9',['uint_least32_t',['../stdint_8h.html#a9a3e3b9785e918fb2c7d964efebd2130',1,'stdint.h']]], - ['uint_5fleast64_5ft_10',['uint_least64_t',['../stdint_8h.html#a3fd9527296a9f56a6bf1ea978fc2be3f',1,'stdint.h']]], - ['uint_5fleast8_5ft_11',['uint_least8_t',['../stdint_8h.html#ab0fdd2a9dc9606590ecccc0a5d8b5b7c',1,'stdint.h']]], - ['uintmax_5ft_12',['uintmax_t',['../stdint_8h.html#a3173cf7a59047054a5933f8e9aa56eae',1,'stdint.h']]], - ['uintptr_5ft_13',['uintptr_t',['../stdint_8h.html#a728e973c799f206f0151c8a3bd1e5699',1,'stdint.h']]] -]; diff --git a/DOCS/html/search/variables_0.js b/DOCS/html/search/variables_0.js index 7ff4ca1..b28c869 100644 --- a/DOCS/html/search/variables_0.js +++ b/DOCS/html/search/variables_0.js @@ -1,5 +1,8 @@ var searchData= [ - ['_5freserved0_0',['_reserved0',['../group___c_m_s_i_s__core___debug_functions.html#gac8a6a13838a897c8d0b8bc991bbaf7c1',1,'APSR_Type::_reserved0'],['../group___c_m_s_i_s__core___debug_functions.html#gac8a6a13838a897c8d0b8bc991bbaf7c1',1,'APSR_Type::@0::_reserved0'],['../group___c_m_s_i_s__core___debug_functions.html#gac8a6a13838a897c8d0b8bc991bbaf7c1',1,'IPSR_Type::_reserved0'],['../group___c_m_s_i_s__core___debug_functions.html#gac8a6a13838a897c8d0b8bc991bbaf7c1',1,'IPSR_Type::@1::_reserved0'],['../group___c_m_s_i_s__core___debug_functions.html#gac8a6a13838a897c8d0b8bc991bbaf7c1',1,'xPSR_Type::_reserved0'],['../group___c_m_s_i_s__core___debug_functions.html#gac8a6a13838a897c8d0b8bc991bbaf7c1',1,'xPSR_Type::@2::_reserved0'],['../group___c_m_s_i_s__core___debug_functions.html#gac8a6a13838a897c8d0b8bc991bbaf7c1',1,'CONTROL_Type::_reserved0'],['../group___c_m_s_i_s__core___debug_functions.html#gac8a6a13838a897c8d0b8bc991bbaf7c1',1,'CONTROL_Type::@3::_reserved0']]], - ['_5freserved1_1',['_reserved1',['../group___c_m_s_i_s__core___debug_functions.html#ga959a73d8faee56599b7e792a7c5a2d16',1,'APSR_Type::_reserved1'],['../group___c_m_s_i_s__core___debug_functions.html#ga959a73d8faee56599b7e792a7c5a2d16',1,'APSR_Type::@0::_reserved1'],['../group___c_m_s_i_s__core___debug_functions.html#ga959a73d8faee56599b7e792a7c5a2d16',1,'xPSR_Type::_reserved1'],['../group___c_m_s_i_s__core___debug_functions.html#ga959a73d8faee56599b7e792a7c5a2d16',1,'xPSR_Type::@2::_reserved1']]] + ['adc_0',['adc',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#gac69e5457edf5f5639c4532688de406ae',1,'stm32f4xx_periph_registers.c']]], + ['adc1_1',['adc1',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#gaf1cc5fa4068a793827866bc4be7e3799',1,'stm32f4xx_periph_registers.c']]], + ['adc123_5fcommon_2',['adc123_common',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#gad98be8090528df1e3edb79ec46438b0a',1,'stm32f4xx_periph_registers.c']]], + ['adc2_3',['adc2',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#gaa94271247e5f041f9097ef16d6450c68',1,'stm32f4xx_periph_registers.c']]], + ['adc3_4',['adc3',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga6f330240512375fb7e4e23ba73e4b612',1,'stm32f4xx_periph_registers.c']]] ]; diff --git a/DOCS/html/search/variables_1.js b/DOCS/html/search/variables_1.js index a4e1eb3..7f002ed 100644 --- a/DOCS/html/search/variables_1.js +++ b/DOCS/html/search/variables_1.js @@ -1,40 +1,5 @@ var searchData= [ - ['acpr_0',['ACPR',['../group___c_m_s_i_s__core___debug_functions.html#ga49a770cf0b7ec970f919f8ac22634fff',1,'TPI_Type']]], - ['acr_1',['ACR',['../group___c_m_s_i_s___device.html#ga9cb55206b29a8c16354747c556ab8bea',1,'FLASH_TypeDef']]], - ['actlr_2',['ACTLR',['../group___c_m_s_i_s__core___debug_functions.html#gafabed911b9f91f9df848999e1b5d6504',1,'SCnSCB_Type']]], - ['adc_3',['adc',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#gac69e5457edf5f5639c4532688de406ae',1,'stm32f4xx_periph_registers.c']]], - ['adc1_4',['adc1',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#gaf1cc5fa4068a793827866bc4be7e3799',1,'stm32f4xx_periph_registers.c']]], - ['adc123_5fcommon_5',['adc123_common',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#gad98be8090528df1e3edb79ec46438b0a',1,'stm32f4xx_periph_registers.c']]], - ['adc2_6',['adc2',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#gaa94271247e5f041f9097ef16d6450c68',1,'stm32f4xx_periph_registers.c']]], - ['adc3_7',['adc3',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga6f330240512375fb7e4e23ba73e4b612',1,'stm32f4xx_periph_registers.c']]], - ['adr_8',['ADR',['../group___c_m_s_i_s__core___debug_functions.html#ga72572af6d5dece4947453aeabd52575f',1,'SCB_Type']]], - ['afr_9',['AFR',['../group___c_m_s_i_s___device.html#gab67c1158c04450d19ad483dcd2192e43',1,'GPIO_TypeDef']]], - ['afsr_10',['AFSR',['../group___c_m_s_i_s__core___debug_functions.html#ga3ef0057e48fdef798f2ee12125a80d9f',1,'SCB_Type']]], - ['ahb1enr_11',['AHB1ENR',['../group___c_m_s_i_s___device.html#ga1e9c75b06c99d0611535f38c7b4aa845',1,'RCC_TypeDef']]], - ['ahb1lpenr_12',['AHB1LPENR',['../group___c_m_s_i_s___device.html#gaae70b1922167eb58d564cb82d39fd10b',1,'RCC_TypeDef']]], - ['ahb1rstr_13',['AHB1RSTR',['../group___c_m_s_i_s___device.html#ga46c20c598e9e12f919f0ea47ebcbc90f',1,'RCC_TypeDef']]], - ['ahb2enr_14',['AHB2ENR',['../group___c_m_s_i_s___device.html#ga5e92ed32c33c92e7ebf6919400ad535b',1,'RCC_TypeDef']]], - ['ahb2lpenr_15',['AHB2LPENR',['../group___c_m_s_i_s___device.html#ga2b30982547fae7d545d260312771b5c9',1,'RCC_TypeDef']]], - ['ahb2rstr_16',['AHB2RSTR',['../group___c_m_s_i_s___device.html#ga78a5aa9dd5694c48a7d8e66888a46450',1,'RCC_TypeDef']]], - ['ahb3enr_17',['AHB3ENR',['../group___c_m_s_i_s___device.html#gacdaa650fcd63730825479f6e8f70d4c0',1,'RCC_TypeDef']]], - ['ahb3lpenr_18',['AHB3LPENR',['../group___c_m_s_i_s___device.html#ga2ff82b9bf0231645108965aa0febd766',1,'RCC_TypeDef']]], - ['ahb3rstr_19',['AHB3RSTR',['../group___c_m_s_i_s___device.html#ga28560c5bfeb45326ea7f2019dba57bea',1,'RCC_TypeDef']]], - ['ahbpresctable_20',['AHBPrescTable',['../group___s_t_m32_f4xx___system___exported__types.html#ga6e1d9cd666f0eacbfde31e9932a93466',1,'system_stm32f4xx.h']]], - ['aircr_21',['AIRCR',['../group___c_m_s_i_s__core___debug_functions.html#ga9b6ccd9c0c0865f8facad77ea37240b0',1,'SCB_Type']]], - ['alrmar_22',['ALRMAR',['../group___c_m_s_i_s___device.html#gac005b1a5bc52634d5a34578cc9d2c3f6',1,'RTC_TypeDef']]], - ['alrmassr_23',['ALRMASSR',['../group___c_m_s_i_s___device.html#ga61282fa74cede526af85fd9d20513646',1,'RTC_TypeDef']]], - ['alrmbr_24',['ALRMBR',['../group___c_m_s_i_s___device.html#ga4e513deb9f58a138ad9f317cc5a3555d',1,'RTC_TypeDef']]], - ['alrmbssr_25',['ALRMBSSR',['../group___c_m_s_i_s___device.html#ga4ef7499da5d5beb1cfc81f7be057a7b2',1,'RTC_TypeDef']]], - ['apb1enr_26',['APB1ENR',['../group___c_m_s_i_s___device.html#gac88901e2eb35079b7b58a185e6bf554c',1,'RCC_TypeDef']]], - ['apb1fz_27',['APB1FZ',['../group___c_m_s_i_s___device.html#ga5eaefc557573ae7bdc632ef6b6d574b5',1,'DBGMCU_TypeDef']]], - ['apb1lpenr_28',['APB1LPENR',['../group___c_m_s_i_s___device.html#gad85a9951a7be79fe08ffc90f796f071b',1,'RCC_TypeDef']]], - ['apb1rstr_29',['APB1RSTR',['../group___c_m_s_i_s___device.html#ga7da5d372374bc59e9b9af750b01d6a78',1,'RCC_TypeDef']]], - ['apb2enr_30',['APB2ENR',['../group___c_m_s_i_s___device.html#gacc7bb47dddd2d94de124f74886d919be',1,'RCC_TypeDef']]], - ['apb2fz_31',['APB2FZ',['../group___c_m_s_i_s___device.html#ga4628a8c32f97ef93b15b2b503ef90c75',1,'DBGMCU_TypeDef']]], - ['apb2lpenr_32',['APB2LPENR',['../group___c_m_s_i_s___device.html#gaba51c57f9506e14a6f5983526c78943b',1,'RCC_TypeDef']]], - ['apb2rstr_33',['APB2RSTR',['../group___c_m_s_i_s___device.html#gab2c5389c9ff4ac188cd498b8f7170968',1,'RCC_TypeDef']]], - ['apbpresctable_34',['APBPrescTable',['../group___s_t_m32_f4xx___system___exported__types.html#ga5b4f8b768465842cf854a8f993b375e9',1,'system_stm32f4xx.h']]], - ['arg_35',['ARG',['../group___c_m_s_i_s___device.html#ga07d4e63efcbde252c667e64a8d818aa9',1,'SDIO_TypeDef']]], - ['arr_36',['ARR',['../group___c_m_s_i_s___device.html#gaf17f19bb4aeea3cc14fa73dfa7772cb8',1,'TIM_TypeDef']]] + ['bkpsram_5fbase_0',['BKPSRAM_BASE',['../struct__memory.html#ae20eaf17d134d9c2136072bca05f36c0',1,'_memory']]], + ['bkpsram_5fbb_5fbase_1',['BKPSRAM_BB_BASE',['../struct__memory.html#a90eb3fc2642288d3e7ca2416493bf8ae',1,'_memory']]] ]; diff --git a/DOCS/html/search/variables_10.js b/DOCS/html/search/variables_10.js index 9b4bb2d..0201c91 100644 --- a/DOCS/html/search/variables_10.js +++ b/DOCS/html/search/variables_10.js @@ -1,46 +1,4 @@ var searchData= [ - ['par_0',['PAR',['../group___c_m_s_i_s___device.html#gaef55be3d948c22dd32a97e8d4f8761fd',1,'DMA_Stream_TypeDef']]], - ['patt2_1',['PATT2',['../group___c_m_s_i_s___device.html#ga9c1bc909ec5ed32df45444488ea6668b',1,'FSMC_Bank2_3_TypeDef']]], - ['patt3_2',['PATT3',['../group___c_m_s_i_s___device.html#gaba03fea9c1bb2242d963e29f1b94d25e',1,'FSMC_Bank2_3_TypeDef']]], - ['patt4_3',['PATT4',['../group___c_m_s_i_s___device.html#ga955cad1aab7fb2d5b6e216cb29b5e7e2',1,'FSMC_Bank4_TypeDef']]], - ['pcr2_4',['PCR2',['../group___c_m_s_i_s___device.html#gab0cb1d704ee64c62ad5be55522a2683a',1,'FSMC_Bank2_3_TypeDef']]], - ['pcr3_5',['PCR3',['../group___c_m_s_i_s___device.html#ga73861fa74b83973fa1b5f92735c042ef',1,'FSMC_Bank2_3_TypeDef']]], - ['pcr4_6',['PCR4',['../group___c_m_s_i_s___device.html#ga2f02e7acfbd7e549ede84633215eb6a1',1,'FSMC_Bank4_TypeDef']]], - ['pcsr_7',['PCSR',['../group___c_m_s_i_s__core___debug_functions.html#ga72e52fffe9ac6af0ee15877e2d5dac41',1,'DWT_Type']]], - ['periph_5fbase_8',['PERIPH_BASE',['../group___c_m_s_i_s___device.html#ga535f5001cfe9967fb7040cd5b081d944',1,'_memory']]], - ['periph_5fbb_5fbase_9',['PERIPH_BB_BASE',['../group___c_m_s_i_s___device.html#ga9fbcd0d73c2b2229b9f95743f280382c',1,'_memory']]], - ['pfr_10',['PFR',['../group___c_m_s_i_s__core___debug_functions.html#ga602fa5eae6a772dbb09970d304e75690',1,'SCB_Type']]], - ['pid0_11',['PID0',['../group___c_m_s_i_s__core___debug_functions.html#ga6e3343cc3c4a8a5a6f14937882e9202a',1,'ITM_Type']]], - ['pid1_12',['PID1',['../group___c_m_s_i_s__core___debug_functions.html#gafa06959344f4991b00e6c545dd2fa30b',1,'ITM_Type']]], - ['pid2_13',['PID2',['../group___c_m_s_i_s__core___debug_functions.html#ga63db39f871596d28e69c283288ea2eba',1,'ITM_Type']]], - ['pid3_14',['PID3',['../group___c_m_s_i_s__core___debug_functions.html#gac2d006eed52ba550a309e5f61ed9c401',1,'ITM_Type']]], - ['pid4_15',['PID4',['../group___c_m_s_i_s__core___debug_functions.html#ga4c002e97cda2375d7421ad6415b6a02f',1,'ITM_Type']]], - ['pid5_16',['PID5',['../group___c_m_s_i_s__core___debug_functions.html#gac085b26f43fefeef9a4cf5c2af5e4a38',1,'ITM_Type']]], - ['pid6_17',['PID6',['../group___c_m_s_i_s__core___debug_functions.html#ga83ac5d00dee24cc7f805b5c147625593',1,'ITM_Type']]], - ['pid7_18',['PID7',['../group___c_m_s_i_s__core___debug_functions.html#gaf8aa73aeaf37bdf7dfd9f6c437ff2d2f',1,'ITM_Type']]], - ['pio4_19',['PIO4',['../group___c_m_s_i_s___device.html#gac53cd7a08093a4ae8f4de4bcff67a64f',1,'FSMC_Bank4_TypeDef']]], - ['pllcfgr_20',['PLLCFGR',['../group___c_m_s_i_s___device.html#gae6ff257862eba6b4b367feea786bf1fd',1,'RCC_TypeDef']]], - ['plli2scfgr_21',['PLLI2SCFGR',['../group___c_m_s_i_s___device.html#ga2d08d5f995ed77228eb56741184a1bb6',1,'RCC_TypeDef']]], - ['pmc_22',['PMC',['../group___c_m_s_i_s___device.html#ga2130abf1fefb63ce4c4b138fd8c9822a',1,'SYSCFG_TypeDef']]], - ['pmem2_23',['PMEM2',['../group___c_m_s_i_s___device.html#ga2e5a7a96de68a6612affa6df8c309c3d',1,'FSMC_Bank2_3_TypeDef']]], - ['pmem3_24',['PMEM3',['../group___c_m_s_i_s___device.html#gaba8981e4f06cfb3db7d9959242052f80',1,'FSMC_Bank2_3_TypeDef']]], - ['pmem4_25',['PMEM4',['../group___c_m_s_i_s___device.html#ga3f82cc749845fb0dd7dfa8121d96b663',1,'FSMC_Bank4_TypeDef']]], - ['port_26',['PORT',['../group___c_m_s_i_s__core___debug_functions.html#ga1f5da59fa27aae410806b7dbe9e499c6',1,'ITM_Type']]], - ['power_27',['POWER',['../group___c_m_s_i_s___device.html#ga65bff76f3af24c37708a1006d54720c7',1,'SDIO_TypeDef']]], - ['pr_28',['PR',['../group___c_m_s_i_s___device.html#gaf8d25514079514d38c104402f46470af',1,'EXTI_TypeDef::PR'],['../group___c_m_s_i_s___device.html#gaf8d25514079514d38c104402f46470af',1,'IWDG_TypeDef::PR']]], - ['prer_29',['PRER',['../group___c_m_s_i_s___device.html#gac9b4c6c5b29f3461ce3f875eea69f35b',1,'RTC_TypeDef']]], - ['psc_30',['PSC',['../group___c_m_s_i_s___device.html#ga9d4c753f09cbffdbe5c55008f0e8b180',1,'TIM_TypeDef']]], - ['ptpssir_31',['PTPSSIR',['../group___c_m_s_i_s___device.html#gaf34b7e8815984e272daa3f089014af4e',1,'ETH_TypeDef']]], - ['ptptsar_32',['PTPTSAR',['../group___c_m_s_i_s___device.html#ga8f47c0f21e22b98bbc2c9f3b6342fbb8',1,'ETH_TypeDef']]], - ['ptptscr_33',['PTPTSCR',['../group___c_m_s_i_s___device.html#gaa657aa42398bc8294976632d778b6db4',1,'ETH_TypeDef']]], - ['ptptshr_34',['PTPTSHR',['../group___c_m_s_i_s___device.html#ga1ebbda0d742e80ca3d53edfa3a95f627',1,'ETH_TypeDef']]], - ['ptptshur_35',['PTPTSHUR',['../group___c_m_s_i_s___device.html#gae8e4ef158db1de28bfd759e40677ba4c',1,'ETH_TypeDef']]], - ['ptptslr_36',['PTPTSLR',['../group___c_m_s_i_s___device.html#ga55c1058cd74dba0ed0cb8963684b9199',1,'ETH_TypeDef']]], - ['ptptslur_37',['PTPTSLUR',['../group___c_m_s_i_s___device.html#ga646bf44e807d10a09f980ace333d33ab',1,'ETH_TypeDef']]], - ['ptptssr_38',['PTPTSSR',['../group___c_m_s_i_s___device.html#gadca0624d09f2c72eee9807cea80a4d0c',1,'ETH_TypeDef']]], - ['ptptthr_39',['PTPTTHR',['../group___c_m_s_i_s___device.html#gaf90723c7aee9c32113a2667b0a5c69f1',1,'ETH_TypeDef']]], - ['ptpttlr_40',['PTPTTLR',['../group___c_m_s_i_s___device.html#ga28e7b0195ce457d20f585f6587fc1cb8',1,'ETH_TypeDef']]], - ['pupdr_41',['PUPDR',['../group___c_m_s_i_s___device.html#gabeed38529bd7b8de082e490e5d4f1727',1,'GPIO_TypeDef']]], - ['pwr_42',['pwr',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#gaba54a48e7552e8a1301cc87cdfcacfee',1,'stm32f4xx_periph_registers.c']]] + ['wwdg_0',['wwdg',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga8702a9a8de59f4e7f66b061c980a1c23',1,'stm32f4xx_periph_registers.c']]] ]; diff --git a/DOCS/html/search/variables_11.js b/DOCS/html/search/variables_11.js deleted file mode 100644 index f9523d9..0000000 --- a/DOCS/html/search/variables_11.js +++ /dev/null @@ -1,4 +0,0 @@ -var searchData= -[ - ['q_0',['Q',['../group___c_m_s_i_s__core___debug_functions.html#ga65f27ddc4f7e09c14ce7c5211b2e000a',1,'APSR_Type::Q'],['../group___c_m_s_i_s__core___debug_functions.html#ga65f27ddc4f7e09c14ce7c5211b2e000a',1,'APSR_Type::@0::Q'],['../group___c_m_s_i_s__core___debug_functions.html#ga65f27ddc4f7e09c14ce7c5211b2e000a',1,'xPSR_Type::Q'],['../group___c_m_s_i_s__core___debug_functions.html#ga65f27ddc4f7e09c14ce7c5211b2e000a',1,'xPSR_Type::@2::Q']]] -]; diff --git a/DOCS/html/search/variables_12.js b/DOCS/html/search/variables_12.js deleted file mode 100644 index 96d2d40..0000000 --- a/DOCS/html/search/variables_12.js +++ /dev/null @@ -1,46 +0,0 @@ -var searchData= -[ - ['rcc_0',['rcc',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga33f5f83bbcee4994fef4f29192860875',1,'stm32f4xx_periph_registers.c']]], - ['rcr_1',['RCR',['../group___c_m_s_i_s___device.html#gaa1b1b7107fcf35abe39d20f5dfc230ee',1,'TIM_TypeDef']]], - ['rdhr_2',['RDHR',['../group___c_m_s_i_s___device.html#ga7f11f42ba9d3bc5cd4a4f5ea0214608e',1,'CAN_FIFOMailBox_TypeDef']]], - ['rdlr_3',['RDLR',['../group___c_m_s_i_s___device.html#gae1c569688eedd49219cd505b9c22121b',1,'CAN_FIFOMailBox_TypeDef']]], - ['rdtr_4',['RDTR',['../group___c_m_s_i_s___device.html#ga9563d8a88d0db403b8357331bea83a2e',1,'CAN_FIFOMailBox_TypeDef']]], - ['reload_5',['RELOAD',['../struct_t_i_m___sim.html#a1798863b8849972c8e0cf75abbbd116b',1,'TIM_Sim']]], - ['reserved_6',['RESERVED',['../group___c_m_s_i_s___device.html#gafaf27b66c1edc60064db3fa6e693fb59',1,'SYSCFG_TypeDef']]], - ['reserved_7',['Reserved',['../group___c_m_s_i_s___device.html#gae930d94b6a3272fed7c42c1a02929924',1,'USB_OTG_HostChannelTypeDef']]], - ['reserved0_8',['RESERVED0',['../group___c_m_s_i_s__core___debug_functions.html#gafd37041a76931e7c95a4970aa0170ad0',1,'NVIC_Type::RESERVED0'],['../group___c_m_s_i_s__core___debug_functions.html#ga9361cfd01123913b78dd5d0dc8301bfd',1,'SCB_Type::RESERVED0'],['../group___c_m_s_i_s__core___debug_functions.html#ga37ff1c5ca91c4a545bde7f8a3301a563',1,'SCnSCB_Type::RESERVED0'],['../group___c_m_s_i_s__core___debug_functions.html#gaf3c010726422d9433474d4315fe1bbcd',1,'ITM_Type::RESERVED0'],['../group___c_m_s_i_s__core___debug_functions.html#ga37ff1c5ca91c4a545bde7f8a3301a563',1,'DWT_Type::RESERVED0'],['../group___c_m_s_i_s__core___debug_functions.html#gac9b95db444f893c84f01e49a91d22651',1,'TPI_Type::RESERVED0'],['../group___c_m_s_i_s__core___debug_functions.html#ga37ff1c5ca91c4a545bde7f8a3301a563',1,'FPU_Type::RESERVED0'],['../group___c_m_s_i_s___device.html#gaae28ab86a4ae57ed057ed1ea89a6d34b',1,'CAN_TypeDef::RESERVED0'],['../group___c_m_s_i_s___device.html#gaa7d2bd5481ee985778c410a7e5826b71',1,'CRC_TypeDef::RESERVED0'],['../group___c_m_s_i_s___device.html#ga8be676577db129a84a9a2689519a8502',1,'ETH_TypeDef::RESERVED0'],['../group___c_m_s_i_s___device.html#gaf86c61a5d38a4fc9cef942a12744486b',1,'FSMC_Bank2_3_TypeDef::RESERVED0'],['../group___c_m_s_i_s___device.html#gaf86c61a5d38a4fc9cef942a12744486b',1,'RCC_TypeDef::RESERVED0'],['../group___c_m_s_i_s___device.html#ga8be676577db129a84a9a2689519a8502',1,'SDIO_TypeDef::RESERVED0']]], - ['reserved04_9',['Reserved04',['../group___c_m_s_i_s___device.html#gacfe7efaa61db86840767dff6d73f8695',1,'USB_OTG_INEndpointTypeDef::Reserved04'],['../group___c_m_s_i_s___device.html#gacfe7efaa61db86840767dff6d73f8695',1,'USB_OTG_OUTEndpointTypeDef::Reserved04']]], - ['reserved0c_10',['Reserved0C',['../group___c_m_s_i_s___device.html#ga1bcc039378b4ed4ac1261a0a758c3d1d',1,'USB_OTG_DeviceTypeDef::Reserved0C'],['../group___c_m_s_i_s___device.html#ga1bcc039378b4ed4ac1261a0a758c3d1d',1,'USB_OTG_INEndpointTypeDef::Reserved0C'],['../group___c_m_s_i_s___device.html#ga1bcc039378b4ed4ac1261a0a758c3d1d',1,'USB_OTG_OUTEndpointTypeDef::Reserved0C']]], - ['reserved1_11',['RESERVED1',['../group___c_m_s_i_s__core___debug_functions.html#ga696e12d22e5f6693aeab2859440e5d58',1,'ITM_Type::RESERVED1'],['../group___c_m_s_i_s__core___debug_functions.html#ga22597a52981a247dfd72fc83fb1a54a3',1,'DWT_Type::RESERVED1'],['../group___c_m_s_i_s__core___debug_functions.html#gad6c93f857de1c48aa3a21aabb47e6c08',1,'TPI_Type::RESERVED1'],['../group___c_m_s_i_s___device.html#ga4bb07a7828fbd5fe86f6a5a3545c177d',1,'CAN_TypeDef::RESERVED1'],['../group___c_m_s_i_s___device.html#ga8249a3955aace28d92109b391311eb30',1,'CRC_TypeDef::RESERVED1'],['../group___c_m_s_i_s___device.html#gac4ac04e673b5b8320d53f7b0947db902',1,'ETH_TypeDef::RESERVED1'],['../group___c_m_s_i_s___device.html#gac4ac04e673b5b8320d53f7b0947db902',1,'FSMC_Bank2_3_TypeDef::RESERVED1'],['../group___c_m_s_i_s___device.html#ga28d88d9a08aab1adbebea61c42ef901e',1,'RCC_TypeDef::RESERVED1'],['../group___c_m_s_i_s___device.html#ga2d531df35272b1f3d787e5726ed5c52c',1,'SDIO_TypeDef::RESERVED1']]], - ['reserved10_12',['RESERVED10',['../group___c_m_s_i_s___device.html#ga57d552323802fb4dd0bac95a02e814f0',1,'ETH_TypeDef']]], - ['reserved18_13',['Reserved18',['../group___c_m_s_i_s___device.html#ga716e172ed03ae049eb501ad83207b4ed',1,'USB_OTG_INEndpointTypeDef::Reserved18'],['../group___c_m_s_i_s___device.html#ga78fbe0aab076cfbf9df51dd6f67eaf82',1,'USB_OTG_OUTEndpointTypeDef::Reserved18']]], - ['reserved2_14',['RESERVED2',['../group___c_m_s_i_s__core___debug_functions.html#gaf42026bc68849adde0d2972b717e2c63',1,'NVIC_Type::RESERVED2'],['../group___c_m_s_i_s__core___debug_functions.html#ga5d1c1ef815721bb6591f5ab016e2262b',1,'ITM_Type::RESERVED2'],['../group___c_m_s_i_s__core___debug_functions.html#gafc320edff930c9d2db6be3af044bff2a',1,'DWT_Type::RESERVED2'],['../group___c_m_s_i_s__core___debug_functions.html#gae33b1ff4c22f5f0743b1c76ebd6ceb7f',1,'TPI_Type::RESERVED2'],['../group___c_m_s_i_s___device.html#ga4c9b972a304c0e08ca27cbe57627c496',1,'CAN_TypeDef::RESERVED2'],['../group___c_m_s_i_s___device.html#ga1cf0d9299ef58b327f4e3d03da1c1aaf',1,'ETH_TypeDef::RESERVED2'],['../group___c_m_s_i_s___device.html#ga4c9b972a304c0e08ca27cbe57627c496',1,'FSMC_Bank2_3_TypeDef::RESERVED2'],['../group___c_m_s_i_s___device.html#ga4c9b972a304c0e08ca27cbe57627c496',1,'RCC_TypeDef::RESERVED2']]], - ['reserved20_15',['Reserved20',['../group___c_m_s_i_s___device.html#ga17d14644b0d28710722b1c2c0149e472',1,'USB_OTG_DeviceTypeDef']]], - ['reserved3_16',['RESERVED3',['../group___c_m_s_i_s__core___debug_functions.html#ga4a73c83f30b388bdeb158c9926d1f038',1,'NVIC_Type::RESERVED3'],['../group___c_m_s_i_s__core___debug_functions.html#ga8275b6f047f2640021fbef1f766e9d8f',1,'ITM_Type::RESERVED3'],['../group___c_m_s_i_s__core___debug_functions.html#gaf2f12e10edc6d605022706316e417534',1,'TPI_Type::RESERVED3'],['../group___c_m_s_i_s___device.html#gaf2b40c5e36a5e861490988275499e158',1,'CAN_TypeDef::RESERVED3'],['../group___c_m_s_i_s___device.html#gaf6446adf612691721c62fc68aff4fe39',1,'ETH_TypeDef::RESERVED3'],['../group___c_m_s_i_s___device.html#gaf2b40c5e36a5e861490988275499e158',1,'FSMC_Bank2_3_TypeDef::RESERVED3'],['../group___c_m_s_i_s___device.html#gab6f0f833dbe064708de75d95c68c32fd',1,'RCC_TypeDef::RESERVED3']]], - ['reserved30_17',['Reserved30',['../group___c_m_s_i_s___device.html#ga577856159d58c037352ee10609b2a99c',1,'USB_OTG_GlobalTypeDef']]], - ['reserved4_18',['RESERVED4',['../group___c_m_s_i_s__core___debug_functions.html#gacc89b6183e50c95d19287044abda0707',1,'NVIC_Type::RESERVED4'],['../group___c_m_s_i_s__core___debug_functions.html#gaab51ad96474c7f0bc4f8320a03dee762',1,'ITM_Type::RESERVED4'],['../group___c_m_s_i_s__core___debug_functions.html#ga85bb9b58f27f0189553adc1da97771e5',1,'TPI_Type::RESERVED4'],['../group___c_m_s_i_s___device.html#gac0018930ee9f18afda25b695b9a4ec16',1,'CAN_TypeDef::RESERVED4'],['../group___c_m_s_i_s___device.html#gabca175d3acfbc2a0806452fd57ea5fc4',1,'ETH_TypeDef::RESERVED4'],['../group___c_m_s_i_s___device.html#gac0018930ee9f18afda25b695b9a4ec16',1,'RCC_TypeDef::RESERVED4']]], - ['reserved40_19',['Reserved40',['../group___c_m_s_i_s___device.html#gaea9d4b7970a55a4c87d8482ba1ed1b8b',1,'USB_OTG_GlobalTypeDef::Reserved40'],['../group___c_m_s_i_s___device.html#ga9e0c029846e94bf08ac8edb35b30ecb2',1,'USB_OTG_DeviceTypeDef::Reserved40']]], - ['reserved40c_20',['Reserved40C',['../group___c_m_s_i_s___device.html#gaf66e42cdb83dc2eb156dfbbf42890f79',1,'USB_OTG_HostTypeDef']]], - ['reserved44_21',['Reserved44',['../group___c_m_s_i_s___device.html#ga8b1e044bd34b12074334270cfd18c931',1,'USB_OTG_DeviceTypeDef']]], - ['reserved5_22',['RESERVED5',['../group___c_m_s_i_s__core___debug_functions.html#ga91ec3c12a77345411c4f8caca5ef4e6c',1,'NVIC_Type::RESERVED5'],['../group___c_m_s_i_s__core___debug_functions.html#ga2b0ee1fd79c3162a6bf47581ed42b491',1,'ITM_Type::RESERVED5'],['../group___c_m_s_i_s__core___debug_functions.html#ga0be075c11181d8a44c3a019b8690e829',1,'TPI_Type::RESERVED5'],['../group___c_m_s_i_s___device.html#ga269f31b91d0f38a48061b76ecc346f55',1,'CAN_TypeDef::RESERVED5'],['../group___c_m_s_i_s___device.html#ga3c1a316c73bb5f0eae7fbe66177cbca6',1,'ETH_TypeDef::RESERVED5'],['../group___c_m_s_i_s___device.html#gac0eb05794aeee3b4ed69c8fe54c9be3b',1,'RCC_TypeDef::RESERVED5']]], - ['reserved6_23',['RESERVED6',['../group___c_m_s_i_s___device.html#ga7e9a9bba62d1d98e3058b29a892b3877',1,'ETH_TypeDef::RESERVED6'],['../group___c_m_s_i_s___device.html#ga10da398d74a1f88d5b42bd40718d9447',1,'RCC_TypeDef::RESERVED6']]], - ['reserved7_24',['RESERVED7',['../group___c_m_s_i_s__core___debug_functions.html#gaa0279d9a6b589b11dab6e3d22f87bac8',1,'TPI_Type::RESERVED7'],['../group___c_m_s_i_s___device.html#gab1b7eacec3f164ed04001e9c806f73f9',1,'ETH_TypeDef::RESERVED7'],['../group___c_m_s_i_s___device.html#ga6be3d40baea405ecaf6b38462357dac0',1,'RTC_TypeDef::RESERVED7']]], - ['reserved8_25',['RESERVED8',['../group___c_m_s_i_s___device.html#ga2e60bc2eefc18398fb2459d1b44453e5',1,'ETH_TypeDef']]], - ['reserved9_26',['Reserved9',['../group___c_m_s_i_s___device.html#ga5dc05e38e6d591cd88f820b7a0b3f727',1,'USB_OTG_DeviceTypeDef']]], - ['reserved9_27',['RESERVED9',['../group___c_m_s_i_s___device.html#gae62fffd7d8f9f69b15edacdea4ba27f2',1,'ETH_TypeDef']]], - ['resp1_28',['RESP1',['../group___c_m_s_i_s___device.html#ga7da778413f6db1f83ae25caed03382d4',1,'SDIO_TypeDef']]], - ['resp2_29',['RESP2',['../group___c_m_s_i_s___device.html#ga44614d7422faffd14af83884e76b2d3e',1,'SDIO_TypeDef']]], - ['resp3_30',['RESP3',['../group___c_m_s_i_s___device.html#ga270ee3c6e9f87e5851422ae0ef255fd4',1,'SDIO_TypeDef']]], - ['resp4_31',['RESP4',['../group___c_m_s_i_s___device.html#gaa74faef460a0c655439bcf20caac1653',1,'SDIO_TypeDef']]], - ['respcmd_32',['RESPCMD',['../group___c_m_s_i_s___device.html#ga195d1a8a6ae4f6072f4e4b62298051fe',1,'SDIO_TypeDef']]], - ['rf0r_33',['RF0R',['../group___c_m_s_i_s___device.html#gaccf4141cee239380d0ad4634ee21dbf6',1,'CAN_TypeDef']]], - ['rf1r_34',['RF1R',['../group___c_m_s_i_s___device.html#ga02b589bb589df4f39e549dca4d5abb08',1,'CAN_TypeDef']]], - ['rir_35',['RIR',['../group___c_m_s_i_s___device.html#ga0acc8eb90b17bef5b9e03c7ddaacfb0b',1,'CAN_FIFOMailBox_TypeDef']]], - ['risr_36',['RISR',['../group___c_m_s_i_s___device.html#gaa196fddf0ba7d6e3ce29bdb04eb38b94',1,'DCMI_TypeDef']]], - ['rlr_37',['RLR',['../group___c_m_s_i_s___device.html#ga7015e1046dbd3ea8783b33dc11a69e52',1,'IWDG_TypeDef']]], - ['rng_38',['rng',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#gae5244ff1d33b8f1c69abb81fda62b538',1,'stm32f4xx_periph_registers.c']]], - ['rserved1_39',['RSERVED1',['../group___c_m_s_i_s__core___debug_functions.html#ga1f2355d51336450dbe986c766006aa8a',1,'NVIC_Type']]], - ['rtc_40',['rtc',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga423742450422a8873970b076a7e25028',1,'stm32f4xx_periph_registers.c']]], - ['rtsr_41',['RTSR',['../group___c_m_s_i_s___device.html#ga0d952a17455687d6e9053730d028fa1d',1,'EXTI_TypeDef']]], - ['rxcrcr_42',['RXCRCR',['../group___c_m_s_i_s___device.html#ga2cf9dcd9008924334f20f0dc6b57042e',1,'SPI_TypeDef']]] -]; diff --git a/DOCS/html/search/variables_13.js b/DOCS/html/search/variables_13.js deleted file mode 100644 index 26ddfcc..0000000 --- a/DOCS/html/search/variables_13.js +++ /dev/null @@ -1,47 +0,0 @@ -var searchData= -[ - ['scr_0',['SCR',['../group___c_m_s_i_s__core___debug_functions.html#gacac65f229cb3fcb5369a0a9e0393b8c0',1,'SCB_Type']]], - ['sdio_1',['sdio',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga8b6edf2e7d9debf95d77d172c8c32cb7',1,'stm32f4xx_periph_registers.c']]], - ['sfifomailbox_2',['sFIFOMailBox',['../group___c_m_s_i_s___device.html#ga21b030b34e131f7ef6ea273416449fe4',1,'CAN_TypeDef']]], - ['sfilterregister_3',['sFilterRegister',['../group___c_m_s_i_s___device.html#ga31bd74513e6e599319702ad34113bf59',1,'CAN_TypeDef']]], - ['shcsr_4',['SHCSR',['../group___c_m_s_i_s__core___debug_functions.html#ga44ad5c292dbd77e72f310902375a8a06',1,'SCB_Type']]], - ['shiftr_5',['SHIFTR',['../group___c_m_s_i_s___device.html#ga2372c05a6c5508e0a9adada793f68b4f',1,'RTC_TypeDef']]], - ['shp_6',['SHP',['../group___c_m_s_i_s__core___debug_functions.html#ga293826a2c44f754e80af03d62f62f9e6',1,'SCB_Type']]], - ['sim_5fsample_5ftime_7',['SIM_Sample_Time',['../struct_s_i_m_____m_c_u_handle_type_def.html#ab19a05224f30fab089c5d5e18fdcca36',1,'SIM__MCUHandleTypeDef']]], - ['slave_5fchannels_8',['Slave_Channels',['../stm32f4xx__matlab__tim_8c.html#a66e48ba3c30d98536e05b7f5435e9828',1,'stm32f4xx_matlab_tim.c']]], - ['sleepcnt_9',['SLEEPCNT',['../group___c_m_s_i_s__core___debug_functions.html#gaafa1400cd3168b21652b86599ad3ed83',1,'DWT_Type']]], - ['smcr_10',['SMCR',['../group___c_m_s_i_s___device.html#ga2870732a4fc2ecd7bbecfbcbbf5528b7',1,'TIM_TypeDef']]], - ['smpr1_11',['SMPR1',['../group___c_m_s_i_s___device.html#gaf9d6c604e365c7d9d7601bf4ef373498',1,'ADC_TypeDef']]], - ['smpr2_12',['SMPR2',['../group___c_m_s_i_s___device.html#ga6ac83fae8377c7b7fcae50fa4211b0e8',1,'ADC_TypeDef']]], - ['spi1_13',['spi1',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga8cc3430b6591549759eb42cc2004a889',1,'stm32f4xx_periph_registers.c']]], - ['spi2_14',['spi2',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#gaafd9bde301b8cacea574ec4eea0e474f',1,'stm32f4xx_periph_registers.c']]], - ['spi3_15',['spi3',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga050e08b3b630957cd79c0e69968308bd',1,'stm32f4xx_periph_registers.c']]], - ['sppr_16',['SPPR',['../group___c_m_s_i_s__core___debug_functions.html#gae9673e1acb75a46ed9852fd7a557cb7d',1,'TPI_Type']]], - ['spsel_17',['SPSEL',['../group___c_m_s_i_s__core___debug_functions.html#gae185aac93686ffc78e998a9daf41415b',1,'CONTROL_Type::SPSEL'],['../group___c_m_s_i_s__core___debug_functions.html#gae185aac93686ffc78e998a9daf41415b',1,'CONTROL_Type::@3::SPSEL']]], - ['sqr1_18',['SQR1',['../group___c_m_s_i_s___device.html#ga3302e1bcfdfbbfeb58779d0761fb377c',1,'ADC_TypeDef']]], - ['sqr2_19',['SQR2',['../group___c_m_s_i_s___device.html#gaab440b0ad8631f5666dd32768a89cf60',1,'ADC_TypeDef']]], - ['sqr3_20',['SQR3',['../group___c_m_s_i_s___device.html#ga97e40d9928fa25a5628d6442f0aa6c0f',1,'ADC_TypeDef']]], - ['sr_21',['SR',['../group___c_m_s_i_s___device.html#ga081f4304e18753e5e8d0afd71ccca45e',1,'ADC_TypeDef::SR'],['../group___c_m_s_i_s___device.html#gaf6aca2bbd40c0fb6df7c3aebe224a360',1,'DAC_TypeDef::SR'],['../group___c_m_s_i_s___device.html#gaf6aca2bbd40c0fb6df7c3aebe224a360',1,'DCMI_TypeDef::SR'],['../group___c_m_s_i_s___device.html#gaf6aca2bbd40c0fb6df7c3aebe224a360',1,'FLASH_TypeDef::SR'],['../group___c_m_s_i_s___device.html#gaf6aca2bbd40c0fb6df7c3aebe224a360',1,'IWDG_TypeDef::SR'],['../group___c_m_s_i_s___device.html#gaf6aca2bbd40c0fb6df7c3aebe224a360',1,'SPI_TypeDef::SR'],['../group___c_m_s_i_s___device.html#gaf6aca2bbd40c0fb6df7c3aebe224a360',1,'TIM_TypeDef::SR'],['../group___c_m_s_i_s___device.html#gaf6aca2bbd40c0fb6df7c3aebe224a360',1,'USART_TypeDef::SR'],['../group___c_m_s_i_s___device.html#gaf6aca2bbd40c0fb6df7c3aebe224a360',1,'WWDG_TypeDef::SR'],['../group___c_m_s_i_s___device.html#gaf6aca2bbd40c0fb6df7c3aebe224a360',1,'RNG_TypeDef::SR']]], - ['sr1_22',['SR1',['../group___c_m_s_i_s___device.html#gacefca4fd83c4b7846ae6d3cfe7bb8df9',1,'I2C_TypeDef']]], - ['sr2_23',['SR2',['../group___c_m_s_i_s___device.html#ga89623ee198737b29dc0a803310605a83',1,'FSMC_Bank2_3_TypeDef::SR2'],['../group___c_m_s_i_s___device.html#ga89623ee198737b29dc0a803310605a83',1,'I2C_TypeDef::SR2']]], - ['sr3_24',['SR3',['../group___c_m_s_i_s___device.html#gaf30c34f7c606cb9416a413ec5fa36491',1,'FSMC_Bank2_3_TypeDef']]], - ['sr4_25',['SR4',['../group___c_m_s_i_s___device.html#ga8218d6e11dae5d4468c69303dec0b4fc',1,'FSMC_Bank4_TypeDef']]], - ['sram1_5fbase_26',['SRAM1_BASE',['../group___c_m_s_i_s___device.html#gac7c83f52956da4c75f4946348f7bfa1a',1,'_memory']]], - ['sram1_5fbb_5fbase_27',['SRAM1_BB_BASE',['../group___c_m_s_i_s___device.html#gac88d0add27755615a9390fec8c64dafc',1,'_memory']]], - ['sram2_5fbase_28',['SRAM2_BASE',['../group___c_m_s_i_s___device.html#ga57bfa1d7c82d97792cbb6c2d366dd48d',1,'_memory']]], - ['sram2_5fbb_5fbase_29',['SRAM2_BB_BASE',['../group___c_m_s_i_s___device.html#ga5db33a541cebb596c2976d4fc409a611',1,'_memory']]], - ['sscgr_30',['SSCGR',['../group___c_m_s_i_s___device.html#gaaef3da59eaf7c6dfdf9a12fd60ce58a8',1,'RCC_TypeDef']]], - ['sspsr_31',['SSPSR',['../group___c_m_s_i_s__core___debug_functions.html#ga1585b32a1ab860d0d77803475d08c7c6',1,'TPI_Type']]], - ['ssr_32',['SSR',['../group___c_m_s_i_s___device.html#ga8a868e5e76b52ced04c536be3dee08ec',1,'RTC_TypeDef']]], - ['sta_33',['STA',['../group___c_m_s_i_s___device.html#ga0633c88accff51e7cc9d1e9c3db950d9',1,'SDIO_TypeDef']]], - ['status_34',['status',['../mexing_8m.html#ab1dc10c44c3fef32dbb7508037a5a3d6',1,'mexing.m']]], - ['stir_35',['STIR',['../group___c_m_s_i_s__core___debug_functions.html#gada9cbba14ab1cc3fddd585f870932db8',1,'NVIC_Type']]], - ['stxmailbox_36',['sTxMailBox',['../group___c_m_s_i_s___device.html#gae37503ab1a7bbd29846f94cdadf0a9ef',1,'CAN_TypeDef']]], - ['swier_37',['SWIER',['../group___c_m_s_i_s___device.html#ga9eae93b6cc13d4d25e12f2224e2369c9',1,'EXTI_TypeDef']]], - ['swtrigr_38',['SWTRIGR',['../group___c_m_s_i_s___device.html#ga896bbb7153af0b67ad772360feaceeb4',1,'DAC_TypeDef']]], - ['syscfg_39',['syscfg',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga973efd19b15b8e1452258c3a02fda513',1,'stm32f4xx_periph_registers.c']]], - ['systemclock_40',['SystemClock',['../mcu__wrapper_8c.html#a6a1676e08289f73141f9fa8419311385',1,'mcu_wrapper.c']]], - ['systemclock_5fstep_41',['SystemClock_step',['../mcu__wrapper_8c.html#ae50392991204ce9a89dd9aa8bf43634f',1,'mcu_wrapper.c']]], - ['systemclockdouble_42',['SystemClockDouble',['../mcu__wrapper_8c.html#af1cb3ba542e380d1f12d30579598c48c',1,'mcu_wrapper.c']]], - ['systemcoreclock_43',['SystemCoreClock',['../group___s_t_m32_f4xx___system___exported__types.html#gaa3cd3e43291e81e795d642b79b6088e6',1,'system_stm32f4xx.h']]] -]; diff --git a/DOCS/html/search/variables_14.js b/DOCS/html/search/variables_14.js deleted file mode 100644 index 5fefadb..0000000 --- a/DOCS/html/search/variables_14.js +++ /dev/null @@ -1,50 +0,0 @@ -var searchData= -[ - ['t_0',['T',['../group___c_m_s_i_s__core___debug_functions.html#ga6e1cf12e53a20224f6f62c001d9be972',1,'xPSR_Type::T'],['../group___c_m_s_i_s__core___debug_functions.html#ga6e1cf12e53a20224f6f62c001d9be972',1,'xPSR_Type::@2::T']]], - ['tafcr_1',['TAFCR',['../group___c_m_s_i_s___device.html#ga14d03244a7fda1d94b51ae9ed144ca12',1,'RTC_TypeDef']]], - ['tcr_2',['TCR',['../group___c_m_s_i_s__core___debug_functions.html#ga4111c001c1e56fd3f51d27c5a63b04e6',1,'ITM_Type']]], - ['tdhr_3',['TDHR',['../group___c_m_s_i_s___device.html#ga90f7c1cf22683459c632d6040366eddf',1,'CAN_TxMailBox_TypeDef']]], - ['tdlr_4',['TDLR',['../group___c_m_s_i_s___device.html#gaded1359e1a32512910bff534d57ade68',1,'CAN_TxMailBox_TypeDef']]], - ['tdtr_5',['TDTR',['../group___c_m_s_i_s___device.html#gaed87bed042dd9523ce086119a3bab0ea',1,'CAN_TxMailBox_TypeDef']]], - ['ter_6',['TER',['../group___c_m_s_i_s__core___debug_functions.html#gaa6530efad3a727fb3cc8f509403b9948',1,'ITM_Type']]], - ['tim1_7',['tim1',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#gaedba2af9d3a451898c4116468f63e31c',1,'stm32f4xx_periph_registers.c']]], - ['tim10_8',['tim10',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga5fc888fc63ae5329a954de3db43caefd',1,'stm32f4xx_periph_registers.c']]], - ['tim11_9',['tim11',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga720638f02cb775a2bdd6b866847b106f',1,'stm32f4xx_periph_registers.c']]], - ['tim12_10',['tim12',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#gaf7e88c4f7e226298777e23ce86e0f68e',1,'stm32f4xx_periph_registers.c']]], - ['tim12s_11',['tim12s',['../group___m_a_i_n___s_i_m_u_l_a_t_o_r.html#gad582b36106c35060b40bddfca929350e',1,'stm32f4xx_matlab_conf.h']]], - ['tim13_12',['tim13',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga5b7e61840360c6a797a1d137d1937c91',1,'stm32f4xx_periph_registers.c']]], - ['tim14_13',['tim14',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga8ade2aee59ea8e56c5b2b9fdd81e4480',1,'stm32f4xx_periph_registers.c']]], - ['tim1_5ftrgo_14',['TIM1_TRGO',['../struct_slave_channels.html#a1bb1d8089ac5eff5af1df34649b50a94',1,'SlaveChannels']]], - ['tim1s_15',['tim1s',['../group___m_a_i_n___s_i_m_u_l_a_t_o_r.html#gab3aec69c8e446c577e391796728e4742',1,'stm32f4xx_matlab_conf.h']]], - ['tim2_16',['tim2',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#gaced1e82df483246f3faed614153db985',1,'stm32f4xx_periph_registers.c']]], - ['tim2_5ftrgo_17',['TIM2_TRGO',['../struct_slave_channels.html#a7b0ea9ba4357a49b11b9c1ef79252613',1,'SlaveChannels']]], - ['tim3_18',['tim3',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga8a9462732233ea58ea84b420b20866ee',1,'stm32f4xx_periph_registers.c']]], - ['tim3_5ftrgo_19',['TIM3_TRGO',['../struct_slave_channels.html#aab5be57f956df4be03effc282a0479e5',1,'SlaveChannels']]], - ['tim3s_20',['tim3s',['../group___m_a_i_n___s_i_m_u_l_a_t_o_r.html#gaefb416b7445ce7c77f15d96cd54cd2f5',1,'stm32f4xx_matlab_conf.h']]], - ['tim4_21',['tim4',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#gab15912b4a5af74002ab2c14632e0c538',1,'stm32f4xx_periph_registers.c']]], - ['tim4_5ftrgo_22',['TIM4_TRGO',['../struct_slave_channels.html#ab9bff03506a4f82f55b13a1065bccaa6',1,'SlaveChannels']]], - ['tim4s_23',['tim4s',['../group___m_a_i_n___s_i_m_u_l_a_t_o_r.html#gab42529334dbaea26f59721c40f7a7782',1,'stm32f4xx_matlab_conf.h']]], - ['tim5_24',['tim5',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga7f9bc8648d83bd2b1959b43b1f11b70e',1,'stm32f4xx_periph_registers.c']]], - ['tim5_5ftrgo_25',['TIM5_TRGO',['../struct_slave_channels.html#a9780a406b85390dddcc18d4c6e606462',1,'SlaveChannels']]], - ['tim6_26',['tim6',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#gac7a5702d9b22c89aa44e3f5161cd8c9d',1,'stm32f4xx_periph_registers.c']]], - ['tim6_5ftrgo_27',['TIM6_TRGO',['../struct_slave_channels.html#a2b1207a49068c13e3257396b4f369932',1,'SlaveChannels']]], - ['tim7_28',['tim7',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#gad32365c7344044f1d4b358b16faf768b',1,'stm32f4xx_periph_registers.c']]], - ['tim7_5ftrgo_29',['TIM7_TRGO',['../struct_slave_channels.html#a8a06a1b3f32a6abaf0a7ad38e27cf0e1',1,'SlaveChannels']]], - ['tim7s_30',['tim7s',['../group___m_a_i_n___s_i_m_u_l_a_t_o_r.html#gaf4ae2f8710078d4b2c0f07a4265ba66a',1,'stm32f4xx_matlab_conf.h']]], - ['tim8_31',['tim8',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga7cd2675665015ace1ee986d66c9cbfb2',1,'stm32f4xx_periph_registers.c']]], - ['tim8_5ftrgo_32',['TIM8_TRGO',['../struct_slave_channels.html#a591c0247b983b782f88fb92aea40f0c7',1,'SlaveChannels']]], - ['tim9_33',['tim9',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga3d6c0e6c095d01dac6c94c83c2e9e55f',1,'stm32f4xx_periph_registers.c']]], - ['tir_34',['TIR',['../group___c_m_s_i_s___device.html#ga6921aa1c578a7d17c6e0eb33a73b6630',1,'CAN_TxMailBox_TypeDef']]], - ['tpr_35',['TPR',['../group___c_m_s_i_s__core___debug_functions.html#gafe5e266862734ca1082ceddff7180688',1,'ITM_Type']]], - ['tr_36',['TR',['../group___c_m_s_i_s___device.html#ga63d179b7a36a715dce7203858d3be132',1,'RTC_TypeDef']]], - ['trigger_37',['TRIGGER',['../group___c_m_s_i_s__core___debug_functions.html#ga5590387d8f44b477fd69951a737b0d7e',1,'TPI_Type']]], - ['trise_38',['TRISE',['../group___c_m_s_i_s___device.html#ga5d5764c0ec44b661da957e6343f9e7b5',1,'I2C_TypeDef']]], - ['ts_39',['Ts',['../mexing_8m.html#ac910fa4e03fcc57ffc78b3693e910e1a',1,'mexing.m']]], - ['tsdr_40',['TSDR',['../group___c_m_s_i_s___device.html#gabeb6fb580a8fd128182aa9ba2738ac2c',1,'RTC_TypeDef']]], - ['tsr_41',['TSR',['../group___c_m_s_i_s___device.html#ga87e3001757a0cd493785f1f3337dd0e8',1,'CAN_TypeDef']]], - ['tsssr_42',['TSSSR',['../group___c_m_s_i_s___device.html#ga1d6c2bc4c067d6a64ef30d16a5925796',1,'RTC_TypeDef']]], - ['tstr_43',['TSTR',['../group___c_m_s_i_s___device.html#ga042059c8b4168681d6aecf30211dd7b8',1,'RTC_TypeDef']]], - ['tx_5fcnt_44',['tx_cnt',['../struct_t_i_m___sim.html#a369177ee20a3798f0d7b98cf7c549498',1,'TIM_Sim']]], - ['tx_5fstep_45',['tx_step',['../struct_t_i_m___sim.html#a838a96dee1a1980434ae35295f85141e',1,'TIM_Sim']]], - ['txcrcr_46',['TXCRCR',['../group___c_m_s_i_s___device.html#gab4e4328504fd66285df8264d410deefd',1,'SPI_TypeDef']]] -]; diff --git a/DOCS/html/search/variables_15.js b/DOCS/html/search/variables_15.js deleted file mode 100644 index d129bcb..0000000 --- a/DOCS/html/search/variables_15.js +++ /dev/null @@ -1,14 +0,0 @@ -var searchData= -[ - ['u16_0',['u16',['../group___c_m_s_i_s__core___debug_functions.html#gae93660eefe2482a8564fae9a1ca39739',1,'ITM_Type::u16'],['../group___c_m_s_i_s__core___debug_functions.html#gae93660eefe2482a8564fae9a1ca39739',1,'ITM_Type::@4::u16']]], - ['u32_1',['u32',['../group___c_m_s_i_s__core___debug_functions.html#gae89dd50f788f12863c681fba1a5b60d1',1,'ITM_Type::u32'],['../group___c_m_s_i_s__core___debug_functions.html#gae89dd50f788f12863c681fba1a5b60d1',1,'ITM_Type::@4::u32']]], - ['u8_2',['u8',['../group___c_m_s_i_s__core___debug_functions.html#ga4c0550e859d614c607bd4b575f05425c',1,'ITM_Type::u8'],['../group___c_m_s_i_s__core___debug_functions.html#ga4c0550e859d614c607bd4b575f05425c',1,'ITM_Type::@4::u8']]], - ['uart4_3',['uart4',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#gaeac987df31348c6546d30bf20d1202b1',1,'stm32f4xx_periph_registers.c']]], - ['uart5_4',['uart5',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga334a742f4e47d9275a7ca0b6a64f3b9b',1,'stm32f4xx_periph_registers.c']]], - ['usart1_5',['usart1',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga6008378d0a594dbb3373976f11998c07',1,'stm32f4xx_periph_registers.c']]], - ['usart2_6',['usart2',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga6704391eb1d9b549ec4a30bff051c840',1,'stm32f4xx_periph_registers.c']]], - ['usart3_7',['usart3',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga34a4f060994660316b3ccf64ef2ca061',1,'stm32f4xx_periph_registers.c']]], - ['usart6_8',['usart6',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#gac976d368ba60c6c4fb520f15ffc973ed',1,'stm32f4xx_periph_registers.c']]], - ['usb_5fotg_5ffs_5fperiph_9',['usb_otg_fs_periph',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#gab7326fc264f9026f7d5be1914a222257',1,'stm32f4xx_periph_registers.c']]], - ['usb_5fotg_5fhs_5fperiph_10',['usb_otg_hs_periph',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga4e565603c7406e27b1f5503de3a8c41b',1,'stm32f4xx_periph_registers.c']]] -]; diff --git a/DOCS/html/search/variables_16.js b/DOCS/html/search/variables_16.js deleted file mode 100644 index 6fb8392..0000000 --- a/DOCS/html/search/variables_16.js +++ /dev/null @@ -1,6 +0,0 @@ -var searchData= -[ - ['v_0',['V',['../group___c_m_s_i_s__core___debug_functions.html#gacd4a2b64faee91e4a9eef300667fa222',1,'APSR_Type::V'],['../group___c_m_s_i_s__core___debug_functions.html#gacd4a2b64faee91e4a9eef300667fa222',1,'APSR_Type::@0::V'],['../group___c_m_s_i_s__core___debug_functions.html#gacd4a2b64faee91e4a9eef300667fa222',1,'xPSR_Type::V'],['../group___c_m_s_i_s__core___debug_functions.html#gacd4a2b64faee91e4a9eef300667fa222',1,'xPSR_Type::@2::V']]], - ['val_1',['VAL',['../group___c_m_s_i_s__core___debug_functions.html#gae7a655a853654127f3dfb7fa32c3f457',1,'SysTick_Type']]], - ['vtor_2',['VTOR',['../group___c_m_s_i_s__core___debug_functions.html#gae457d2615e203c3d5904a43a1bc9df71',1,'SCB_Type']]] -]; diff --git a/DOCS/html/search/variables_17.js b/DOCS/html/search/variables_17.js deleted file mode 100644 index 494ba79..0000000 --- a/DOCS/html/search/variables_17.js +++ /dev/null @@ -1,7 +0,0 @@ -var searchData= -[ - ['w_0',['w',['../group___c_m_s_i_s__core___debug_functions.html#gad0fb62e7a08e70fc5e0a76b67809f84b',1,'APSR_Type::w'],['../group___c_m_s_i_s__core___debug_functions.html#gad0fb62e7a08e70fc5e0a76b67809f84b',1,'IPSR_Type::w'],['../group___c_m_s_i_s__core___debug_functions.html#gad0fb62e7a08e70fc5e0a76b67809f84b',1,'xPSR_Type::w'],['../group___c_m_s_i_s__core___debug_functions.html#gad0fb62e7a08e70fc5e0a76b67809f84b',1,'CONTROL_Type::w']]], - ['wpr_1',['WPR',['../group___c_m_s_i_s___device.html#ga6204786b050eb135fabb15784698e86e',1,'RTC_TypeDef']]], - ['wutr_2',['WUTR',['../group___c_m_s_i_s___device.html#gac5b3c8be61045a304d3076d4714d29f2',1,'RTC_TypeDef']]], - ['wwdg_3',['wwdg',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga8702a9a8de59f4e7f66b061c980a1c23',1,'stm32f4xx_periph_registers.c']]] -]; diff --git a/DOCS/html/search/variables_18.js b/DOCS/html/search/variables_18.js deleted file mode 100644 index da6bf00..0000000 --- a/DOCS/html/search/variables_18.js +++ /dev/null @@ -1,4 +0,0 @@ -var searchData= -[ - ['z_0',['Z',['../group___c_m_s_i_s__core___debug_functions.html#ga5ae954cbd9986cd64625d7fa00943c8e',1,'APSR_Type::Z'],['../group___c_m_s_i_s__core___debug_functions.html#ga5ae954cbd9986cd64625d7fa00943c8e',1,'APSR_Type::@0::Z'],['../group___c_m_s_i_s__core___debug_functions.html#ga5ae954cbd9986cd64625d7fa00943c8e',1,'xPSR_Type::Z'],['../group___c_m_s_i_s__core___debug_functions.html#ga5ae954cbd9986cd64625d7fa00943c8e',1,'xPSR_Type::@2::Z']]] -]; diff --git a/DOCS/html/search/variables_2.js b/DOCS/html/search/variables_2.js index 392e107..7d6761e 100644 --- a/DOCS/html/search/variables_2.js +++ b/DOCS/html/search/variables_2.js @@ -1,34 +1,9 @@ var searchData= [ - ['b_0',['b',['../group___c_m_s_i_s__core___debug_functions.html#ga84de5f534817cdbf8bd9064080effca2',1,'APSR_Type::b'],['../group___c_m_s_i_s__core___debug_functions.html#ga6e920e9d2e9a2738f8face0863888c0e',1,'IPSR_Type::b'],['../group___c_m_s_i_s__core___debug_functions.html#ga61873807b9abee3dfa090c036e580d2e',1,'xPSR_Type::b'],['../group___c_m_s_i_s__core___debug_functions.html#ga5d690aa9e65fccaa320e1b8613f502c9',1,'CONTROL_Type::b']]], - ['bdcr_1',['BDCR',['../group___c_m_s_i_s___device.html#ga0b9a3ced775287c8585a6a61af4b40e9',1,'RCC_TypeDef']]], - ['bdtr_2',['BDTR',['../group___c_m_s_i_s___device.html#ga476bae602205d6a49c7e71e2bda28c0a',1,'TIM_TypeDef']]], - ['bfar_3',['BFAR',['../group___c_m_s_i_s__core___debug_functions.html#ga3fde073744418e2fe476333cb4d55d0d',1,'SCB_Type']]], - ['bkp0r_4',['BKP0R',['../group___c_m_s_i_s___device.html#ga4808ec597e5a5fefd8a83a9127dd1aec',1,'RTC_TypeDef']]], - ['bkp10r_5',['BKP10R',['../group___c_m_s_i_s___device.html#gaade2881a3e408bfd106b27f78bbbcfc9',1,'RTC_TypeDef']]], - ['bkp11r_6',['BKP11R',['../group___c_m_s_i_s___device.html#gac66d5e2d3459cff89794c47dbc8f7228',1,'RTC_TypeDef']]], - ['bkp12r_7',['BKP12R',['../group___c_m_s_i_s___device.html#ga6f7eee5ae8a32c07f9c8fe14281bdaf3',1,'RTC_TypeDef']]], - ['bkp13r_8',['BKP13R',['../group___c_m_s_i_s___device.html#ga6ed4c3a0d4588a75078e9f8e376b4d06',1,'RTC_TypeDef']]], - ['bkp14r_9',['BKP14R',['../group___c_m_s_i_s___device.html#gac60f13e6619724747e61cfbff55b9fab',1,'RTC_TypeDef']]], - ['bkp15r_10',['BKP15R',['../group___c_m_s_i_s___device.html#gafafaddc3a983eb71332b7526d82191ad',1,'RTC_TypeDef']]], - ['bkp16r_11',['BKP16R',['../group___c_m_s_i_s___device.html#gad2f2eb2fb4b93e21515b10e920e719b6',1,'RTC_TypeDef']]], - ['bkp17r_12',['BKP17R',['../group___c_m_s_i_s___device.html#ga2842aa523df62f3508316eb3b2e08f4e',1,'RTC_TypeDef']]], - ['bkp18r_13',['BKP18R',['../group___c_m_s_i_s___device.html#ga640ccb2ccfb6316b88c070362dc29339',1,'RTC_TypeDef']]], - ['bkp19r_14',['BKP19R',['../group___c_m_s_i_s___device.html#ga4ec1dd54d976989b7c9e59fb14d974fb',1,'RTC_TypeDef']]], - ['bkp1r_15',['BKP1R',['../group___c_m_s_i_s___device.html#gaf85290529fb82acef7c9fcea3718346c',1,'RTC_TypeDef']]], - ['bkp2r_16',['BKP2R',['../group___c_m_s_i_s___device.html#gaaa251a80daa57ad0bd7db75cb3b9cdec',1,'RTC_TypeDef']]], - ['bkp3r_17',['BKP3R',['../group___c_m_s_i_s___device.html#ga0b1eeda834c3cfd4d2c67f242f7b2a1c',1,'RTC_TypeDef']]], - ['bkp4r_18',['BKP4R',['../group___c_m_s_i_s___device.html#gab13e106cc2eca92d1f4022df3bfdbcd7',1,'RTC_TypeDef']]], - ['bkp5r_19',['BKP5R',['../group___c_m_s_i_s___device.html#gab6bed862c0d0476ff4f89f7b9bf3e130',1,'RTC_TypeDef']]], - ['bkp6r_20',['BKP6R',['../group___c_m_s_i_s___device.html#ga1d854d2d7f0452f4c90035952b92d2ba',1,'RTC_TypeDef']]], - ['bkp7r_21',['BKP7R',['../group___c_m_s_i_s___device.html#ga2ca54ce1a8d2fa9d1ba6d5987ed5e2cf',1,'RTC_TypeDef']]], - ['bkp8r_22',['BKP8R',['../group___c_m_s_i_s___device.html#gac1085f6aae54b353c30871fe90c59851',1,'RTC_TypeDef']]], - ['bkp9r_23',['BKP9R',['../group___c_m_s_i_s___device.html#ga6c33564df6eaf97400e0457dde9b14ef',1,'RTC_TypeDef']]], - ['bkpsram_5fbase_24',['BKPSRAM_BASE',['../group___c_m_s_i_s___device.html#gae20eaf17d134d9c2136072bca05f36c0',1,'_memory']]], - ['bkpsram_5fbb_5fbase_25',['BKPSRAM_BB_BASE',['../group___c_m_s_i_s___device.html#ga90eb3fc2642288d3e7ca2416493bf8ae',1,'_memory']]], - ['brr_26',['BRR',['../group___c_m_s_i_s___device.html#ga092e59d908b2ca112e31047e942340cb',1,'USART_TypeDef']]], - ['bsrr_27',['BSRR',['../group___c_m_s_i_s___device.html#gac25dd6b9e3d55e17589195b461c5ec80',1,'GPIO_TypeDef']]], - ['btcr_28',['BTCR',['../group___c_m_s_i_s___device.html#ga80a6708b507f6eecbc10424fdb088b79',1,'FSMC_Bank1_TypeDef']]], - ['btr_29',['BTR',['../group___c_m_s_i_s___device.html#ga5c0fcd3e7b4c59ab1dd68f6bd8f74e07',1,'CAN_TypeDef']]], - ['bwtr_30',['BWTR',['../group___c_m_s_i_s___device.html#ga20f13b79c0f8670af319af0c5ebd5c91',1,'FSMC_Bank1E_TypeDef']]] + ['can1_0',['can1',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga047c365ed69ab08e79c499adcedff87b',1,'stm32f4xx_periph_registers.c']]], + ['can2_1',['can2',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#gae4b5c771c41468ea4ffa1af4de9ce39e',1,'stm32f4xx_periph_registers.c']]], + ['ccmdataram_5fbase_2',['CCMDATARAM_BASE',['../struct__memory.html#acd6db2394f2b493a873059464d5b0e18',1,'_memory']]], + ['channels_3',['Channels',['../struct_t_i_m___sim.html#a41f21d0d1bfe0fb45e3f643ece9cdcee',1,'TIM_Sim']]], + ['cortex_5fperiph_5fbase_4',['CORTEX_PERIPH_BASE',['../struct__cortex__memory.html#a33c7ca027b61cba4b327fcad1c1cb7aa',1,'_cortex_memory']]], + ['crc_5',['crc',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga0be4a4f92234a92301b5dea4ef762a83',1,'stm32f4xx_periph_registers.c']]] ]; diff --git a/DOCS/html/search/variables_3.js b/DOCS/html/search/variables_3.js index 20fe9b7..2303a91 100644 --- a/DOCS/html/search/variables_3.js +++ b/DOCS/html/search/variables_3.js @@ -1,55 +1,27 @@ var searchData= [ - ['c_0',['C',['../group___c_m_s_i_s__core___debug_functions.html#ga7a1caf92f32fe9ebd8d1fe89b06c7776',1,'APSR_Type::C'],['../group___c_m_s_i_s__core___debug_functions.html#ga7a1caf92f32fe9ebd8d1fe89b06c7776',1,'APSR_Type::@0::C'],['../group___c_m_s_i_s__core___debug_functions.html#ga7a1caf92f32fe9ebd8d1fe89b06c7776',1,'xPSR_Type::C'],['../group___c_m_s_i_s__core___debug_functions.html#ga7a1caf92f32fe9ebd8d1fe89b06c7776',1,'xPSR_Type::@2::C']]], - ['calib_1',['CALIB',['../group___c_m_s_i_s__core___debug_functions.html#gaedf0dff29a9cacdaa2fb7eec6b116a13',1,'SysTick_Type']]], - ['calibr_2',['CALIBR',['../group___c_m_s_i_s___device.html#gab97f3e9584dda705dc10a5f4c5f6e636',1,'RTC_TypeDef']]], - ['calr_3',['CALR',['../group___c_m_s_i_s___device.html#ga2ce7c3842792c506635bb87a21588b58',1,'RTC_TypeDef']]], - ['can1_4',['can1',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga047c365ed69ab08e79c499adcedff87b',1,'stm32f4xx_periph_registers.c']]], - ['can2_5',['can2',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#gae4b5c771c41468ea4ffa1af4de9ce39e',1,'stm32f4xx_periph_registers.c']]], - ['ccer_6',['CCER',['../group___c_m_s_i_s___device.html#ga098110becfef10e1fd1b6a4f874da496',1,'TIM_TypeDef']]], - ['ccmdataram_5fbase_7',['CCMDATARAM_BASE',['../group___c_m_s_i_s___device.html#gacd6db2394f2b493a873059464d5b0e18',1,'_memory']]], - ['ccmr1_8',['CCMR1',['../group___c_m_s_i_s___device.html#gadb72f64492a75e780dd2294075c70fed',1,'TIM_TypeDef']]], - ['ccmr2_9',['CCMR2',['../group___c_m_s_i_s___device.html#ga091452256c9a16c33d891f4d32b395bf',1,'TIM_TypeDef']]], - ['ccr_10',['CCR',['../group___c_m_s_i_s__core___debug_functions.html#gad68b5c1f2d9845ef4247cf2d9b041336',1,'SCB_Type::CCR'],['../group___c_m_s_i_s___device.html#ga5e1322e27c40bf91d172f9673f205c97',1,'ADC_Common_TypeDef::CCR'],['../group___c_m_s_i_s___device.html#ga5e1322e27c40bf91d172f9673f205c97',1,'I2C_TypeDef::CCR']]], - ['ccr1_11',['CCR1',['../group___c_m_s_i_s___device.html#gadab1e24ef769bbcb3e3769feae192ffb',1,'TIM_TypeDef']]], - ['ccr2_12',['CCR2',['../group___c_m_s_i_s___device.html#gab90aa584f07eeeac364a67f5e05faa93',1,'TIM_TypeDef']]], - ['ccr3_13',['CCR3',['../group___c_m_s_i_s___device.html#ga27a478cc47a3dff478555ccb985b06a2',1,'TIM_TypeDef']]], - ['ccr4_14',['CCR4',['../group___c_m_s_i_s___device.html#ga85fdb75569bd7ea26fa48544786535be',1,'TIM_TypeDef']]], - ['cdr_15',['CDR',['../group___c_m_s_i_s___device.html#ga760f86a1a18dffffda54fc15a977979f',1,'ADC_Common_TypeDef']]], - ['cfgr_16',['CFGR',['../group___c_m_s_i_s___device.html#ga26f1e746ccbf9c9f67e7c60e61085ec1',1,'RCC_TypeDef']]], - ['cfr_17',['CFR',['../group___c_m_s_i_s___device.html#gac011ddcfe531f8e16787ea851c1f3667',1,'WWDG_TypeDef']]], - ['cfsr_18',['CFSR',['../group___c_m_s_i_s__core___debug_functions.html#ga0f9e27357254e6e953a94f95bda040b1',1,'SCB_Type']]], - ['channels_19',['Channels',['../struct_t_i_m___sim.html#a41f21d0d1bfe0fb45e3f643ece9cdcee',1,'TIM_Sim']]], - ['cid_20',['CID',['../group___c_m_s_i_s___device.html#ga6eefd74b3acdc3c1a88b833fcf5e8d81',1,'USB_OTG_GlobalTypeDef']]], - ['cid0_21',['CID0',['../group___c_m_s_i_s__core___debug_functions.html#ga26bbad5d9e0f1d302611d52373aef839',1,'ITM_Type']]], - ['cid1_22',['CID1',['../group___c_m_s_i_s__core___debug_functions.html#ga4e60a608afd6433ecd943d95e417b80b',1,'ITM_Type']]], - ['cid2_23',['CID2',['../group___c_m_s_i_s__core___debug_functions.html#gad98950702e55d1851e91b22de07b11aa',1,'ITM_Type']]], - ['cid3_24',['CID3',['../group___c_m_s_i_s__core___debug_functions.html#gab9af64f413bf6f67e2a8044481292f67',1,'ITM_Type']]], - ['cir_25',['CIR',['../group___c_m_s_i_s___device.html#ga907d8154c80b7e385478943f90b17a3b',1,'RCC_TypeDef']]], - ['claimclr_26',['CLAIMCLR',['../group___c_m_s_i_s__core___debug_functions.html#ga1f74caab7b0a7afa848c63ce8ebc6a6f',1,'TPI_Type']]], - ['claimset_27',['CLAIMSET',['../group___c_m_s_i_s__core___debug_functions.html#ga974d17c9a0b0b1b894e9707d158b0fbe',1,'TPI_Type']]], - ['clkcr_28',['CLKCR',['../group___c_m_s_i_s___device.html#gaa94197378e20fc739d269be49d9c5d40',1,'SDIO_TypeDef']]], - ['cmd_29',['CMD',['../group___c_m_s_i_s___device.html#gadcf812cbe5147d300507d59d4a55935d',1,'SDIO_TypeDef']]], - ['cmpcr_30',['CMPCR',['../group___c_m_s_i_s___device.html#ga08ddbac546fa9928256654d31255c8c3',1,'SYSCFG_TypeDef']]], - ['cnt_31',['CNT',['../group___c_m_s_i_s___device.html#ga6095a27d764d06750fc0d642e08f8b2a',1,'TIM_TypeDef']]], - ['comp0_32',['COMP0',['../group___c_m_s_i_s__core___debug_functions.html#ga5d0c69187f8abc99ecbde49431cf0050',1,'DWT_Type']]], - ['comp1_33',['COMP1',['../group___c_m_s_i_s__core___debug_functions.html#gaf9126caaf63b99d6df5d1e040c96e2ab',1,'DWT_Type']]], - ['comp2_34',['COMP2',['../group___c_m_s_i_s__core___debug_functions.html#gaeeb1e36001c60a167399683280d6ec39',1,'DWT_Type']]], - ['comp3_35',['COMP3',['../group___c_m_s_i_s__core___debug_functions.html#ga20b0b62a3576ee88db4a7c065cd988ac',1,'DWT_Type']]], - ['cortex_5fperiph_5fbase_36',['CORTEX_PERIPH_BASE',['../group___c_m_s_i_s__core___debug_functions.html#ga33c7ca027b61cba4b327fcad1c1cb7aa',1,'_cortex_memory']]], - ['cpacr_37',['CPACR',['../group___c_m_s_i_s__core___debug_functions.html#gab8e9dd6ca5f31244ea352ed0c19155d8',1,'SCB_Type']]], - ['cpicnt_38',['CPICNT',['../group___c_m_s_i_s__core___debug_functions.html#ga29ca657c77928334be08a2e6555be950',1,'DWT_Type']]], - ['cpuid_39',['CPUID',['../group___c_m_s_i_s__core___debug_functions.html#gadbf8292503748ba6421a523bdee6819d',1,'SCB_Type']]], - ['cr_40',['CR',['../group___c_m_s_i_s___device.html#gab40c89c59391aaa9d9a8ec011dd0907a',1,'CRC_TypeDef::CR'],['../group___c_m_s_i_s___device.html#gab40c89c59391aaa9d9a8ec011dd0907a',1,'DAC_TypeDef::CR'],['../group___c_m_s_i_s___device.html#gab40c89c59391aaa9d9a8ec011dd0907a',1,'DBGMCU_TypeDef::CR'],['../group___c_m_s_i_s___device.html#gab40c89c59391aaa9d9a8ec011dd0907a',1,'DCMI_TypeDef::CR'],['../group___c_m_s_i_s___device.html#gab40c89c59391aaa9d9a8ec011dd0907a',1,'DMA_Stream_TypeDef::CR'],['../group___c_m_s_i_s___device.html#gab40c89c59391aaa9d9a8ec011dd0907a',1,'FLASH_TypeDef::CR'],['../group___c_m_s_i_s___device.html#gab40c89c59391aaa9d9a8ec011dd0907a',1,'PWR_TypeDef::CR'],['../group___c_m_s_i_s___device.html#gab40c89c59391aaa9d9a8ec011dd0907a',1,'RCC_TypeDef::CR'],['../group___c_m_s_i_s___device.html#gab40c89c59391aaa9d9a8ec011dd0907a',1,'RTC_TypeDef::CR'],['../group___c_m_s_i_s___device.html#gab40c89c59391aaa9d9a8ec011dd0907a',1,'WWDG_TypeDef::CR'],['../group___c_m_s_i_s___device.html#gab40c89c59391aaa9d9a8ec011dd0907a',1,'RNG_TypeDef::CR']]], - ['cr1_41',['CR1',['../group___c_m_s_i_s___device.html#gab0ec7102960640751d44e92ddac994f0',1,'ADC_TypeDef::CR1'],['../group___c_m_s_i_s___device.html#gab0ec7102960640751d44e92ddac994f0',1,'I2C_TypeDef::CR1'],['../group___c_m_s_i_s___device.html#gab0ec7102960640751d44e92ddac994f0',1,'SPI_TypeDef::CR1'],['../group___c_m_s_i_s___device.html#gab0ec7102960640751d44e92ddac994f0',1,'TIM_TypeDef::CR1'],['../group___c_m_s_i_s___device.html#gab0ec7102960640751d44e92ddac994f0',1,'USART_TypeDef::CR1']]], - ['cr2_42',['CR2',['../group___c_m_s_i_s___device.html#gafdfa307571967afb1d97943e982b6586',1,'ADC_TypeDef::CR2'],['../group___c_m_s_i_s___device.html#gafdfa307571967afb1d97943e982b6586',1,'I2C_TypeDef::CR2'],['../group___c_m_s_i_s___device.html#gafdfa307571967afb1d97943e982b6586',1,'SPI_TypeDef::CR2'],['../group___c_m_s_i_s___device.html#gafdfa307571967afb1d97943e982b6586',1,'TIM_TypeDef::CR2'],['../group___c_m_s_i_s___device.html#gafdfa307571967afb1d97943e982b6586',1,'USART_TypeDef::CR2']]], - ['cr3_43',['CR3',['../group___c_m_s_i_s___device.html#gadd5b8e29a64c55dcd65ca4201118e9d1',1,'USART_TypeDef']]], - ['crc_44',['crc',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga0be4a4f92234a92301b5dea4ef762a83',1,'stm32f4xx_periph_registers.c']]], - ['crcpr_45',['CRCPR',['../group___c_m_s_i_s___device.html#gace450027b4b33f921dd8edd3425a717c',1,'SPI_TypeDef']]], - ['cspsr_46',['CSPSR',['../group___c_m_s_i_s__core___debug_functions.html#gabf4a378b17278d98d2a5f9315fce7a5e',1,'TPI_Type']]], - ['csr_47',['CSR',['../group___c_m_s_i_s___device.html#ga876dd0a8546697065f406b7543e27af2',1,'ADC_Common_TypeDef::CSR'],['../group___c_m_s_i_s___device.html#ga876dd0a8546697065f406b7543e27af2',1,'PWR_TypeDef::CSR'],['../group___c_m_s_i_s___device.html#ga876dd0a8546697065f406b7543e27af2',1,'RCC_TypeDef::CSR']]], - ['ctrl_48',['CTRL',['../group___c_m_s_i_s__core___debug_functions.html#gac81efc171e9852a36caeb47122bfec5b',1,'SysTick_Type::CTRL'],['../group___c_m_s_i_s__core___debug_functions.html#gac81efc171e9852a36caeb47122bfec5b',1,'DWT_Type::CTRL']]], - ['cwsizer_49',['CWSIZER',['../group___c_m_s_i_s___device.html#gaa3ccc5d081bbee3c61ae9aa5e0c83af9',1,'DCMI_TypeDef']]], - ['cwstrtr_50',['CWSTRTR',['../group___c_m_s_i_s___device.html#ga919b70dd8762e44263a02dfbafc7b8ce',1,'DCMI_TypeDef']]], - ['cyccnt_51',['CYCCNT',['../group___c_m_s_i_s__core___debug_functions.html#ga14822f5ad3426799332ac537d9293f3c',1,'DWT_Type']]] + ['dac_0',['dac',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#gad8051cafe91bba5f5a52af50cd3a11da',1,'stm32f4xx_periph_registers.c']]], + ['dac1_1',['dac1',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#gac2a5eec34721432ce7d7dec940c4a105',1,'stm32f4xx_periph_registers.c']]], + ['dbgmcu_2',['dbgmcu',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#gacecf2f30be3d1243af9c27921727cb3d',1,'stm32f4xx_periph_registers.c']]], + ['dcmi_3',['dcmi',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga7acb73c38792037a032e8a1a05247546',1,'stm32f4xx_periph_registers.c']]], + ['debug_5fmcu_4',['DEBUG_MCU',['../stm32f4xx__matlab__conf_8c.html#a85a080726cb1ade56443b458fc49404b',1,'stm32f4xx_matlab_conf.c']]], + ['debug_5fmcu_5fbase_5',['DEBUG_MCU_BASE',['../struct__memory.html#a3b7f188430e83671b314657c1033f0e4',1,'_memory']]], + ['dma1_6',['dma1',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#gad75f4f486cddcbba8bd891fdffea63ff',1,'stm32f4xx_periph_registers.c']]], + ['dma1_5fstream0_7',['dma1_stream0',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga327e8fb8c3fdda29762971a665beb6eb',1,'stm32f4xx_periph_registers.c']]], + ['dma1_5fstream1_8',['dma1_stream1',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga9696aa3317c6d4e58bd31545db1a3791',1,'stm32f4xx_periph_registers.c']]], + ['dma1_5fstream2_9',['dma1_stream2',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#gaf1e2d204d4c7f13213bc4cdece346a9f',1,'stm32f4xx_periph_registers.c']]], + ['dma1_5fstream3_10',['dma1_stream3',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga67575d2b3cf487db91535889ed5802c4',1,'stm32f4xx_periph_registers.c']]], + ['dma1_5fstream4_11',['dma1_stream4',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga0da31a3af45097d4b4a136c5d74d6000',1,'stm32f4xx_periph_registers.c']]], + ['dma1_5fstream5_12',['dma1_stream5',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga160109a05c1a572c5911c1a0633e2cb1',1,'stm32f4xx_periph_registers.c']]], + ['dma1_5fstream6_13',['dma1_stream6',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga52167e4b4ae32ee99aca493b07ec2cf0',1,'stm32f4xx_periph_registers.c']]], + ['dma1_5fstream7_14',['dma1_stream7',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#gaeb5a72f1dde2596da84347544d59f3ea',1,'stm32f4xx_periph_registers.c']]], + ['dma2_15',['dma2',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga797194bf8715329824161a98d1b2a236',1,'stm32f4xx_periph_registers.c']]], + ['dma2_5fstream0_16',['dma2_stream0',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#gaeff8718ce310afab98873eccba9ff245',1,'stm32f4xx_periph_registers.c']]], + ['dma2_5fstream1_17',['dma2_stream1',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga0fb8b4583868b79144561ef45c93637a',1,'stm32f4xx_periph_registers.c']]], + ['dma2_5fstream2_18',['dma2_stream2',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga33cbc3fc9b89c29e722fc4e4973d6058',1,'stm32f4xx_periph_registers.c']]], + ['dma2_5fstream3_19',['dma2_stream3',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#gadcd0980342e18d51ce08021a0d1abfdd',1,'stm32f4xx_periph_registers.c']]], + ['dma2_5fstream4_20',['dma2_stream4',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga14e0e20b296df9eea835441023807c15',1,'stm32f4xx_periph_registers.c']]], + ['dma2_5fstream5_21',['dma2_stream5',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga8fc00e6429450f48f22fddb4040d1e2d',1,'stm32f4xx_periph_registers.c']]], + ['dma2_5fstream6_22',['dma2_stream6',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga8d4903dcdae5a8f4c0b7b2678b2cf5b4',1,'stm32f4xx_periph_registers.c']]], + ['dma2_5fstream7_23',['dma2_stream7',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga19770af0d338f06fbb1ffa09150909b4',1,'stm32f4xx_periph_registers.c']]] ]; diff --git a/DOCS/html/search/variables_4.js b/DOCS/html/search/variables_4.js index 599114e..f5ca2ba 100644 --- a/DOCS/html/search/variables_4.js +++ b/DOCS/html/search/variables_4.js @@ -1,93 +1,5 @@ var searchData= [ - ['dac_0',['dac',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#gad8051cafe91bba5f5a52af50cd3a11da',1,'stm32f4xx_periph_registers.c']]], - ['dac1_1',['dac1',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#gac2a5eec34721432ce7d7dec940c4a105',1,'stm32f4xx_periph_registers.c']]], - ['daint_2',['DAINT',['../group___c_m_s_i_s___device.html#ga4e15c273373694f64b3f70226cb3ac35',1,'USB_OTG_DeviceTypeDef']]], - ['daintmsk_3',['DAINTMSK',['../group___c_m_s_i_s___device.html#ga2c8f65655aa14ec9ba63c9d0655223ec',1,'USB_OTG_DeviceTypeDef']]], - ['dbgmcu_4',['dbgmcu',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#gacecf2f30be3d1243af9c27921727cb3d',1,'stm32f4xx_periph_registers.c']]], - ['dcfg_5',['DCFG',['../group___c_m_s_i_s___device.html#ga9a163a0d5cfce7238b38067a1a53b324',1,'USB_OTG_DeviceTypeDef']]], - ['dcmi_6',['dcmi',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga7acb73c38792037a032e8a1a05247546',1,'stm32f4xx_periph_registers.c']]], - ['dcount_7',['DCOUNT',['../group___c_m_s_i_s___device.html#ga1c267db01a753d0b8a77afcaff6f9e13',1,'SDIO_TypeDef']]], - ['dcr_8',['DCR',['../group___c_m_s_i_s___device.html#gaf6225cb8f4938f98204d11afaffd41c9',1,'TIM_TypeDef']]], - ['dcrdr_9',['DCRDR',['../group___c_m_s_i_s__core___debug_functions.html#gad1dbd0dd98b6d9327f70545e0081ddbf',1,'CoreDebug_Type']]], - ['dcrsr_10',['DCRSR',['../group___c_m_s_i_s__core___debug_functions.html#gab74a9ec90ad18e4f7a20362d362b754a',1,'CoreDebug_Type']]], - ['dctl_11',['DCTL',['../group___c_m_s_i_s___device.html#gadc1bdc4e76749ccda09c92e885b164ad',1,'USB_OTG_DeviceTypeDef']]], - ['dctrl_12',['DCTRL',['../group___c_m_s_i_s___device.html#ga96a3d1a050982fccc23c2e6dbe0de068',1,'SDIO_TypeDef']]], - ['deachint_13',['DEACHINT',['../group___c_m_s_i_s___device.html#gae85e8a65a72f52a9daf3d2b66b77c2e2',1,'USB_OTG_DeviceTypeDef']]], - ['deachmsk_14',['DEACHMSK',['../group___c_m_s_i_s___device.html#ga0234d794aba7ddae31f3da3c02c8a673',1,'USB_OTG_DeviceTypeDef']]], - ['debug_5fmcu_15',['DEBUG_MCU',['../stm32f4xx__matlab__conf_8c.html#a85a080726cb1ade56443b458fc49404b',1,'DEBUG_MCU: stm32f4xx_matlab_conf.c'],['../group___peripheral__memory__map.html#ga85a080726cb1ade56443b458fc49404b',1,'DEBUG_MCU: stm32f407xx_matlab.h']]], - ['demcr_16',['DEMCR',['../group___c_m_s_i_s__core___debug_functions.html#gaa99de5f8c609f10c25ed51f57b2edd74',1,'CoreDebug_Type']]], - ['devid_17',['DEVID',['../group___c_m_s_i_s__core___debug_functions.html#gaaed316dacef669454fa035e04ee90eca',1,'TPI_Type']]], - ['devtype_18',['DEVTYPE',['../group___c_m_s_i_s__core___debug_functions.html#ga81f643aff0e4bed2638a618e2b1fd3bb',1,'TPI_Type']]], - ['dfr_19',['DFR',['../group___c_m_s_i_s__core___debug_functions.html#gae2b3d4530d1b0c05593b634dc46348bd',1,'SCB_Type']]], - ['dfsr_20',['DFSR',['../group___c_m_s_i_s__core___debug_functions.html#ga3b590075aa07880ce686d5cfb4e61c5c',1,'SCB_Type']]], - ['dhcsr_21',['DHCSR',['../group___c_m_s_i_s__core___debug_functions.html#ga94ca828091a9226ab6684fbf30e52909',1,'CoreDebug_Type']]], - ['dhr12l1_22',['DHR12L1',['../group___c_m_s_i_s___device.html#gae9028b8bcb5118b7073165fb50fcd559',1,'DAC_TypeDef']]], - ['dhr12l2_23',['DHR12L2',['../group___c_m_s_i_s___device.html#ga2e45f9c9d67e384187b25334ba0a3e3d',1,'DAC_TypeDef']]], - ['dhr12ld_24',['DHR12LD',['../group___c_m_s_i_s___device.html#gacc269320aff0a6482730224a4b641a59',1,'DAC_TypeDef']]], - ['dhr12r1_25',['DHR12R1',['../group___c_m_s_i_s___device.html#gac2bb55b037b800a25852736afdd7a258',1,'DAC_TypeDef']]], - ['dhr12r2_26',['DHR12R2',['../group___c_m_s_i_s___device.html#ga804c7e15dbb587c7ea25511f6a7809f7',1,'DAC_TypeDef']]], - ['dhr12rd_27',['DHR12RD',['../group___c_m_s_i_s___device.html#ga1590b77e57f17e75193da259da72095e',1,'DAC_TypeDef']]], - ['dhr8r1_28',['DHR8R1',['../group___c_m_s_i_s___device.html#gad0a200e12acad17a5c7d2059159ea7e1',1,'DAC_TypeDef']]], - ['dhr8r2_29',['DHR8R2',['../group___c_m_s_i_s___device.html#ga4c435f0e34ace4421241cd5c3ae87fc2',1,'DAC_TypeDef']]], - ['dhr8rd_30',['DHR8RD',['../group___c_m_s_i_s___device.html#ga9590269cba8412f1be96b0ddb846ef44',1,'DAC_TypeDef']]], - ['diepctl_31',['DIEPCTL',['../group___c_m_s_i_s___device.html#ga840b32fa57faa544c3000ae1d08564c7',1,'USB_OTG_INEndpointTypeDef']]], - ['diepdma_32',['DIEPDMA',['../group___c_m_s_i_s___device.html#ga05fcc63652e936e715223e4423069959',1,'USB_OTG_INEndpointTypeDef']]], - ['diepempmsk_33',['DIEPEMPMSK',['../group___c_m_s_i_s___device.html#ga99c6c50a3e3235c81b98a428ebd33d4c',1,'USB_OTG_DeviceTypeDef']]], - ['diepint_34',['DIEPINT',['../group___c_m_s_i_s___device.html#ga65f69561c1cefe00ce608b7a3c2d8af5',1,'USB_OTG_INEndpointTypeDef']]], - ['diepmsk_35',['DIEPMSK',['../group___c_m_s_i_s___device.html#ga48647281e48d96a96f701cf5ae3f4f63',1,'USB_OTG_DeviceTypeDef']]], - ['dieptsiz_36',['DIEPTSIZ',['../group___c_m_s_i_s___device.html#ga19cf1f1798a062c2a19afe9224e3f938',1,'USB_OTG_INEndpointTypeDef']]], - ['dieptxf_37',['DIEPTXF',['../group___c_m_s_i_s___device.html#ga2b783e516da93a95c56adf3e52dcbe62',1,'USB_OTG_GlobalTypeDef']]], - ['dieptxf0_5fhnptxfsiz_38',['DIEPTXF0_HNPTXFSIZ',['../group___c_m_s_i_s___device.html#ga93412b352267d3faf0bd2dbac590b69e',1,'USB_OTG_GlobalTypeDef']]], - ['dier_39',['DIER',['../group___c_m_s_i_s___device.html#ga07fccbd85b91e6dca03ce333c1457fcb',1,'TIM_TypeDef']]], - ['dinep1msk_40',['DINEP1MSK',['../group___c_m_s_i_s___device.html#gab62b876c61e11199cf5c37aa944a5fed',1,'USB_OTG_DeviceTypeDef']]], - ['dlen_41',['DLEN',['../group___c_m_s_i_s___device.html#ga612edc78d2fa6288392f8ea32c36f7fb',1,'SDIO_TypeDef']]], - ['dma1_42',['dma1',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#gad75f4f486cddcbba8bd891fdffea63ff',1,'stm32f4xx_periph_registers.c']]], - ['dma1_5fstream0_43',['dma1_stream0',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga327e8fb8c3fdda29762971a665beb6eb',1,'stm32f4xx_periph_registers.c']]], - ['dma1_5fstream1_44',['dma1_stream1',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga9696aa3317c6d4e58bd31545db1a3791',1,'stm32f4xx_periph_registers.c']]], - ['dma1_5fstream2_45',['dma1_stream2',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#gaf1e2d204d4c7f13213bc4cdece346a9f',1,'stm32f4xx_periph_registers.c']]], - ['dma1_5fstream3_46',['dma1_stream3',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga67575d2b3cf487db91535889ed5802c4',1,'stm32f4xx_periph_registers.c']]], - ['dma1_5fstream4_47',['dma1_stream4',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga0da31a3af45097d4b4a136c5d74d6000',1,'stm32f4xx_periph_registers.c']]], - ['dma1_5fstream5_48',['dma1_stream5',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga160109a05c1a572c5911c1a0633e2cb1',1,'stm32f4xx_periph_registers.c']]], - ['dma1_5fstream6_49',['dma1_stream6',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga52167e4b4ae32ee99aca493b07ec2cf0',1,'stm32f4xx_periph_registers.c']]], - ['dma1_5fstream7_50',['dma1_stream7',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#gaeb5a72f1dde2596da84347544d59f3ea',1,'stm32f4xx_periph_registers.c']]], - ['dma2_51',['dma2',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga797194bf8715329824161a98d1b2a236',1,'stm32f4xx_periph_registers.c']]], - ['dma2_5fstream0_52',['dma2_stream0',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#gaeff8718ce310afab98873eccba9ff245',1,'stm32f4xx_periph_registers.c']]], - ['dma2_5fstream1_53',['dma2_stream1',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga0fb8b4583868b79144561ef45c93637a',1,'stm32f4xx_periph_registers.c']]], - ['dma2_5fstream2_54',['dma2_stream2',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga33cbc3fc9b89c29e722fc4e4973d6058',1,'stm32f4xx_periph_registers.c']]], - ['dma2_5fstream3_55',['dma2_stream3',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#gadcd0980342e18d51ce08021a0d1abfdd',1,'stm32f4xx_periph_registers.c']]], - ['dma2_5fstream4_56',['dma2_stream4',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga14e0e20b296df9eea835441023807c15',1,'stm32f4xx_periph_registers.c']]], - ['dma2_5fstream5_57',['dma2_stream5',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga8fc00e6429450f48f22fddb4040d1e2d',1,'stm32f4xx_periph_registers.c']]], - ['dma2_5fstream6_58',['dma2_stream6',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga8d4903dcdae5a8f4c0b7b2678b2cf5b4',1,'stm32f4xx_periph_registers.c']]], - ['dma2_5fstream7_59',['dma2_stream7',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga19770af0d338f06fbb1ffa09150909b4',1,'stm32f4xx_periph_registers.c']]], - ['dmabmr_60',['DMABMR',['../group___c_m_s_i_s___device.html#gad1e11eb1200e64e0563e3576bf258194',1,'ETH_TypeDef']]], - ['dmachrbar_61',['DMACHRBAR',['../group___c_m_s_i_s___device.html#gacf3f7ecbf774d8d505655ac7f24761fc',1,'ETH_TypeDef']]], - ['dmachrdr_62',['DMACHRDR',['../group___c_m_s_i_s___device.html#ga9c49de2e699886d6604fd2b3d376a0e9',1,'ETH_TypeDef']]], - ['dmachtbar_63',['DMACHTBAR',['../group___c_m_s_i_s___device.html#ga900f9f888342fbdd8ee07e3ee1d4b73c',1,'ETH_TypeDef']]], - ['dmachtdr_64',['DMACHTDR',['../group___c_m_s_i_s___device.html#gab5bb348210fdd9a5538eb57abc5a5673',1,'ETH_TypeDef']]], - ['dmaier_65',['DMAIER',['../group___c_m_s_i_s___device.html#gadd56f3652fd065c6797411e80477a064',1,'ETH_TypeDef']]], - ['dmamfbocr_66',['DMAMFBOCR',['../group___c_m_s_i_s___device.html#ga12eba1fc5d54aa50fdda201f7f9a84a3',1,'ETH_TypeDef']]], - ['dmaomr_67',['DMAOMR',['../group___c_m_s_i_s___device.html#gaa15b972f30ee47f5df0d3ebc8866509d',1,'ETH_TypeDef']]], - ['dmar_68',['DMAR',['../group___c_m_s_i_s___device.html#gab9087f2f31dd5edf59de6a59ae4e67ae',1,'TIM_TypeDef']]], - ['dmardlar_69',['DMARDLAR',['../group___c_m_s_i_s___device.html#ga581ce491c035ce46db723260377c2032',1,'ETH_TypeDef']]], - ['dmarpdr_70',['DMARPDR',['../group___c_m_s_i_s___device.html#gaad6309afe126da26921191697d7e5c43',1,'ETH_TypeDef']]], - ['dmarswtr_71',['DMARSWTR',['../group___c_m_s_i_s___device.html#gac6fe9e194ed9d08bf6bd28ceb80ac4b0',1,'ETH_TypeDef']]], - ['dmasr_72',['DMASR',['../group___c_m_s_i_s___device.html#ga9e7c3d04e4dcf975939eeaac246b25d0',1,'ETH_TypeDef']]], - ['dmatdlar_73',['DMATDLAR',['../group___c_m_s_i_s___device.html#ga7dba9527df73350f35683140d73a5f8d',1,'ETH_TypeDef']]], - ['dmatpdr_74',['DMATPDR',['../group___c_m_s_i_s___device.html#gacf0114902a52b7ffcc343e06484b3623',1,'ETH_TypeDef']]], - ['doepctl_75',['DOEPCTL',['../group___c_m_s_i_s___device.html#ga905a2b4ece4882eb67c710e0db10e960',1,'USB_OTG_OUTEndpointTypeDef']]], - ['doepdma_76',['DOEPDMA',['../group___c_m_s_i_s___device.html#ga78a4f036f29e552acad6a442fbb69420',1,'USB_OTG_OUTEndpointTypeDef']]], - ['doepint_77',['DOEPINT',['../group___c_m_s_i_s___device.html#gaffd2c6f534c8f2c252f3a93d0cd04ea2',1,'USB_OTG_OUTEndpointTypeDef']]], - ['doepmsk_78',['DOEPMSK',['../group___c_m_s_i_s___device.html#ga11dbd3f7a82b3f3b91621321d3018e0a',1,'USB_OTG_DeviceTypeDef']]], - ['doeptsiz_79',['DOEPTSIZ',['../group___c_m_s_i_s___device.html#ga35b668314acbac2580b98caf8b9c5c10',1,'USB_OTG_OUTEndpointTypeDef']]], - ['dor1_80',['DOR1',['../group___c_m_s_i_s___device.html#gaa710505be03a41981c35bacc7ce20746',1,'DAC_TypeDef']]], - ['dor2_81',['DOR2',['../group___c_m_s_i_s___device.html#gaba9fb810b0cf6cbc1280c5c63be2418b',1,'DAC_TypeDef']]], - ['doutep1msk_82',['DOUTEP1MSK',['../group___c_m_s_i_s___device.html#ga196e86fc15ba228188d47468349de69b',1,'USB_OTG_DeviceTypeDef']]], - ['dr_83',['DR',['../group___c_m_s_i_s___device.html#ga3df0d8dfcd1ec958659ffe21eb64fa94',1,'ADC_TypeDef::DR'],['../group___c_m_s_i_s___device.html#ga3df0d8dfcd1ec958659ffe21eb64fa94',1,'CRC_TypeDef::DR'],['../group___c_m_s_i_s___device.html#ga3df0d8dfcd1ec958659ffe21eb64fa94',1,'DCMI_TypeDef::DR'],['../group___c_m_s_i_s___device.html#ga3df0d8dfcd1ec958659ffe21eb64fa94',1,'I2C_TypeDef::DR'],['../group___c_m_s_i_s___device.html#ga3df0d8dfcd1ec958659ffe21eb64fa94',1,'RTC_TypeDef::DR'],['../group___c_m_s_i_s___device.html#ga3df0d8dfcd1ec958659ffe21eb64fa94',1,'SPI_TypeDef::DR'],['../group___c_m_s_i_s___device.html#ga3df0d8dfcd1ec958659ffe21eb64fa94',1,'USART_TypeDef::DR'],['../group___c_m_s_i_s___device.html#ga3df0d8dfcd1ec958659ffe21eb64fa94',1,'RNG_TypeDef::DR']]], - ['dsts_84',['DSTS',['../group___c_m_s_i_s___device.html#ga8371acd36203fa875cdea3f29b94d1fb',1,'USB_OTG_DeviceTypeDef']]], - ['dthrctl_85',['DTHRCTL',['../group___c_m_s_i_s___device.html#gac5d3a4bffd921da5d69f9a601263b573',1,'USB_OTG_DeviceTypeDef']]], - ['dtimer_86',['DTIMER',['../group___c_m_s_i_s___device.html#ga1dd219eaeee8d9def822da843028bd02',1,'SDIO_TypeDef']]], - ['dtxfsts_87',['DTXFSTS',['../group___c_m_s_i_s___device.html#ga44135a03aa87fb60abd479a09f71343d',1,'USB_OTG_INEndpointTypeDef']]], - ['dvbusdis_88',['DVBUSDIS',['../group___c_m_s_i_s___device.html#gaef96b3719a70e62cb004b1e292b7a348',1,'USB_OTG_DeviceTypeDef']]], - ['dvbuspulse_89',['DVBUSPULSE',['../group___c_m_s_i_s___device.html#gacc968fd160f83749ad4176ad8cb36fe0',1,'USB_OTG_DeviceTypeDef']]] + ['eth_0',['eth',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga8b57579963e46439e92cb241151cec09',1,'stm32f4xx_periph_registers.c']]], + ['exti_1',['exti',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga5db1038489ccf5ec54a585b08226b84d',1,'stm32f4xx_periph_registers.c']]] ]; diff --git a/DOCS/html/search/variables_5.js b/DOCS/html/search/variables_5.js index 33b2d4e..77e367f 100644 --- a/DOCS/html/search/variables_5.js +++ b/DOCS/html/search/variables_5.js @@ -1,14 +1,12 @@ var searchData= [ - ['eccr2_0',['ECCR2',['../group___c_m_s_i_s___device.html#ga05a47a1664adc7a3db3fa3e83fe883b4',1,'FSMC_Bank2_3_TypeDef']]], - ['eccr3_1',['ECCR3',['../group___c_m_s_i_s___device.html#ga6062be7dc144c07e01c303cb49d69ce2',1,'FSMC_Bank2_3_TypeDef']]], - ['egr_2',['EGR',['../group___c_m_s_i_s___device.html#ga196ebdaac12b21e90320c6175da78ef6',1,'TIM_TypeDef']]], - ['emr_3',['EMR',['../group___c_m_s_i_s___device.html#ga6034c7458d8e6030f6dacecf0f1a3a89',1,'EXTI_TypeDef']]], - ['escr_4',['ESCR',['../group___c_m_s_i_s___device.html#ga9cc4ec74be864c929261e0810f2fd7f0',1,'DCMI_TypeDef']]], - ['esr_5',['ESR',['../group___c_m_s_i_s___device.html#ga2b39f943954e0e7d177b511d9074a0b7',1,'CAN_TypeDef']]], - ['esur_6',['ESUR',['../group___c_m_s_i_s___device.html#gaf751d49ef824c1636c78822ecae066f4',1,'DCMI_TypeDef']]], - ['eth_7',['eth',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga8b57579963e46439e92cb241151cec09',1,'stm32f4xx_periph_registers.c']]], - ['exccnt_8',['EXCCNT',['../group___c_m_s_i_s__core___debug_functions.html#gafe0bbc124e53ad450abc72bfb56bd74f',1,'DWT_Type']]], - ['exti_9',['exti',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga5db1038489ccf5ec54a585b08226b84d',1,'stm32f4xx_periph_registers.c']]], - ['exticr_10',['EXTICR',['../group___c_m_s_i_s___device.html#ga52f7bf8003ba69d66a4e86dea6eeab65',1,'SYSCFG_TypeDef']]] + ['flash_5fbase_0',['FLASH_BASE',['../struct__memory.html#a84303738f0e64d5303c027932c055d87',1,'_memory']]], + ['flash_5fotp_5fbase_1',['FLASH_OTP_BASE',['../struct__memory.html#ace5daae0e2da2f05a6b63f3f68109284',1,'_memory']]], + ['flash_5fr_2',['flash_r',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga9005724fdcdcbb61e849a94a8068d0a5',1,'stm32f4xx_periph_registers.c']]], + ['fmcu_5fstop_3',['fMCU_Stop',['../struct_s_i_m_____m_c_u_handle_type_def.html#ad81f091fd8c1ad2908a5dd5967f3322e',1,'SIM__MCUHandleTypeDef']]], + ['fsmc_5fbank1_5fr_4',['fsmc_bank1_r',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#gabc182d46d8d7866f89db2e17f7d67496',1,'stm32f4xx_periph_registers.c']]], + ['fsmc_5fbank1e_5fr_5',['fsmc_bank1e_r',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#gac5d854d8ad94b3865847d64044c9bec8',1,'stm32f4xx_periph_registers.c']]], + ['fsmc_5fbank2_5f3_5fr_6',['fsmc_bank2_3_r',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga337be35abe408bd089d87060903b944f',1,'stm32f4xx_periph_registers.c']]], + ['fsmc_5fbank4_5fr_7',['fsmc_bank4_r',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga86a7b6923c554282c949627ccaaee51b',1,'stm32f4xx_periph_registers.c']]], + ['fsmc_5fr_5fbase_8',['FSMC_R_BASE',['../struct__memory.html#aeb17f07e5976d0674b1afe60cffc79d4',1,'_memory']]] ]; diff --git a/DOCS/html/search/variables_6.js b/DOCS/html/search/variables_6.js index cb4158d..585aca1 100644 --- a/DOCS/html/search/variables_6.js +++ b/DOCS/html/search/variables_6.js @@ -1,37 +1,12 @@ var searchData= [ - ['fa1r_0',['FA1R',['../group___c_m_s_i_s___device.html#gaaf76271f4ab0b3deb3ceb6e2ac0d62d0',1,'CAN_TypeDef']]], - ['fcr_1',['FCR',['../group___c_m_s_i_s___device.html#ga5d5cc7f32884945503dd29f8f6cbb415',1,'DMA_Stream_TypeDef']]], - ['ffa1r_2',['FFA1R',['../group___c_m_s_i_s___device.html#gaf1405e594e39e5b34f9499f680157a25',1,'CAN_TypeDef']]], - ['ffcr_3',['FFCR',['../group___c_m_s_i_s__core___debug_functions.html#gafe3ca1410c32188d26be24c4ee9e180c',1,'TPI_Type']]], - ['ffsr_4',['FFSR',['../group___c_m_s_i_s__core___debug_functions.html#ga2a049b49e9da6772d38166397ce8fc70',1,'TPI_Type']]], - ['fifo_5',['FIFO',['../group___c_m_s_i_s___device.html#ga68bef1da5fd164cf0f884b4209670dc8',1,'SDIO_TypeDef']]], - ['fifo0_6',['FIFO0',['../group___c_m_s_i_s__core___debug_functions.html#gace73d78eff029b698e11cd5cf3efaf94',1,'TPI_Type']]], - ['fifo1_7',['FIFO1',['../group___c_m_s_i_s__core___debug_functions.html#gabad7737b3d46cc6d4813d37171d29745',1,'TPI_Type']]], - ['fifocnt_8',['FIFOCNT',['../group___c_m_s_i_s___device.html#ga003c4c00f70bd77298fc66a449822651',1,'SDIO_TypeDef']]], - ['flash_5fbase_9',['FLASH_BASE',['../group___c_m_s_i_s___device.html#ga84303738f0e64d5303c027932c055d87',1,'_memory']]], - ['flash_5fotp_5fbase_10',['FLASH_OTP_BASE',['../group___c_m_s_i_s___device.html#gace5daae0e2da2f05a6b63f3f68109284',1,'_memory']]], - ['flash_5fr_11',['flash_r',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga9005724fdcdcbb61e849a94a8068d0a5',1,'stm32f4xx_periph_registers.c']]], - ['fm1r_12',['FM1R',['../group___c_m_s_i_s___device.html#gaaa6f4cf1f16aaa6d17ec6c410db76acf',1,'CAN_TypeDef']]], - ['fmcu_5fstop_13',['fMCU_Stop',['../struct_s_i_m_____m_c_u_handle_type_def.html#ad81f091fd8c1ad2908a5dd5967f3322e',1,'SIM__MCUHandleTypeDef']]], - ['fmr_14',['FMR',['../group___c_m_s_i_s___device.html#ga1cb734df34f6520a7204c4c70634ebba',1,'CAN_TypeDef']]], - ['foldcnt_15',['FOLDCNT',['../group___c_m_s_i_s__core___debug_functions.html#ga6324c1fbf6c94f1eaf742d09ad678216',1,'DWT_Type']]], - ['fpca_16',['FPCA',['../group___c_m_s_i_s__core___debug_functions.html#ga2518558c090f60161ba4e718a54ee468',1,'CONTROL_Type::FPCA'],['../group___c_m_s_i_s__core___debug_functions.html#ga2518558c090f60161ba4e718a54ee468',1,'CONTROL_Type::@3::FPCA']]], - ['fpcar_17',['FPCAR',['../group___c_m_s_i_s__core___debug_functions.html#ga4fa83b560b046f9cec201c68fbe33507',1,'FPU_Type']]], - ['fpccr_18',['FPCCR',['../group___c_m_s_i_s__core___debug_functions.html#ga242040bad11980d6250848a44cc967e3',1,'FPU_Type']]], - ['fpdscr_19',['FPDSCR',['../group___c_m_s_i_s__core___debug_functions.html#ga05a8c9a999e6ca4ff19f30c93ec50217',1,'FPU_Type']]], - ['fr1_20',['FR1',['../group___c_m_s_i_s___device.html#ga92036953ac673803fe001d843fea508b',1,'CAN_FilterRegister_TypeDef']]], - ['fr2_21',['FR2',['../group___c_m_s_i_s___device.html#ga7f7d80b45b7574463d7030fc8a464582',1,'CAN_FilterRegister_TypeDef']]], - ['fs1r_22',['FS1R',['../group___c_m_s_i_s___device.html#gaae0256ae42106ee7f87fc7e5bdb779d4',1,'CAN_TypeDef']]], - ['fscr_23',['FSCR',['../group___c_m_s_i_s__core___debug_functions.html#ga36370b2b0879b7b497f6dd854ba02873',1,'TPI_Type']]], - ['fsmc_5fbank1_5fr_24',['fsmc_bank1_r',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#gabc182d46d8d7866f89db2e17f7d67496',1,'stm32f4xx_periph_registers.c']]], - ['fsmc_5fbank1e_5fr_25',['fsmc_bank1e_r',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#gac5d854d8ad94b3865847d64044c9bec8',1,'stm32f4xx_periph_registers.c']]], - ['fsmc_5fbank2_5f3_5fr_26',['fsmc_bank2_3_r',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga337be35abe408bd089d87060903b944f',1,'stm32f4xx_periph_registers.c']]], - ['fsmc_5fbank4_5fr_27',['fsmc_bank4_r',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga86a7b6923c554282c949627ccaaee51b',1,'stm32f4xx_periph_registers.c']]], - ['fsmc_5fr_5fbase_28',['FSMC_R_BASE',['../group___c_m_s_i_s___device.html#gaeb17f07e5976d0674b1afe60cffc79d4',1,'_memory']]], - ['ftsr_29',['FTSR',['../group___c_m_s_i_s___device.html#gaa0f7c828c46ae6f6bc9f66f11720bbe6',1,'EXTI_TypeDef']]], - ['function0_30',['FUNCTION0',['../group___c_m_s_i_s__core___debug_functions.html#gad3c69d206a52a85165eb7bd8077b0608',1,'DWT_Type']]], - ['function1_31',['FUNCTION1',['../group___c_m_s_i_s__core___debug_functions.html#gae8f02e32e101c4cc61115d271fa12ffb',1,'DWT_Type']]], - ['function2_32',['FUNCTION2',['../group___c_m_s_i_s__core___debug_functions.html#ga8ba3cc103077080ae3c0fc41e87d1197',1,'DWT_Type']]], - ['function3_33',['FUNCTION3',['../group___c_m_s_i_s__core___debug_functions.html#gafbfaba1d10558329868c6c55f91f82df',1,'DWT_Type']]] + ['gpioa_0',['gpioa',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#gafe2a610b007523788505f398360469f5',1,'stm32f4xx_periph_registers.c']]], + ['gpiob_1',['gpiob',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#gade602c9d7c12472827a033d5b2e8aa23',1,'stm32f4xx_periph_registers.c']]], + ['gpioc_2',['gpioc',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga2dab7cbce8521c60951c6342c19bb501',1,'stm32f4xx_periph_registers.c']]], + ['gpiod_3',['gpiod',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#gad48004dee1cfc09b9c68d896ea43be11',1,'stm32f4xx_periph_registers.c']]], + ['gpioe_4',['gpioe',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga179dea27e5a083e03fc241f28043becf',1,'stm32f4xx_periph_registers.c']]], + ['gpiof_5',['gpiof',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga655c6a3fda1e8cc9126d4a2070d7e462',1,'stm32f4xx_periph_registers.c']]], + ['gpiog_6',['gpiog',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#gaed4e2f21f491ff70becdc5a582a2ad67',1,'stm32f4xx_periph_registers.c']]], + ['gpioh_7',['gpioh',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga9d4756994de85ee04d0086406c01c00b',1,'stm32f4xx_periph_registers.c']]], + ['gpioi_8',['gpioi',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga4fa8522689e49acbf45dc4e5a49d19ef',1,'stm32f4xx_periph_registers.c']]] ]; diff --git a/DOCS/html/search/variables_7.js b/DOCS/html/search/variables_7.js index 6f981fd..a076c8a 100644 --- a/DOCS/html/search/variables_7.js +++ b/DOCS/html/search/variables_7.js @@ -1,25 +1,5 @@ var searchData= [ - ['gahbcfg_0',['GAHBCFG',['../group___c_m_s_i_s___device.html#gac38ac55e4148686564478e95f345b833',1,'USB_OTG_GlobalTypeDef']]], - ['gccfg_1',['GCCFG',['../group___c_m_s_i_s___device.html#gaef85efc005db9a8e37d95644e92e9032',1,'USB_OTG_GlobalTypeDef']]], - ['ge_2',['GE',['../group___c_m_s_i_s__core___debug_functions.html#gaa91800ec6e90e457c7a1acd1f2e17099',1,'APSR_Type::GE'],['../group___c_m_s_i_s__core___debug_functions.html#gaa91800ec6e90e457c7a1acd1f2e17099',1,'APSR_Type::@0::GE'],['../group___c_m_s_i_s__core___debug_functions.html#gaa91800ec6e90e457c7a1acd1f2e17099',1,'xPSR_Type::GE'],['../group___c_m_s_i_s__core___debug_functions.html#gaa91800ec6e90e457c7a1acd1f2e17099',1,'xPSR_Type::@2::GE']]], - ['gintmsk_3',['GINTMSK',['../group___c_m_s_i_s___device.html#ga69d9432b4272331bffb34e196b57cbdf',1,'USB_OTG_GlobalTypeDef']]], - ['gintsts_4',['GINTSTS',['../group___c_m_s_i_s___device.html#ga9980c4a55080745a11528f8c7ffa1c66',1,'USB_OTG_GlobalTypeDef']]], - ['gotgctl_5',['GOTGCTL',['../group___c_m_s_i_s___device.html#ga4f006a75f87074f02a532fbeb215bd24',1,'USB_OTG_GlobalTypeDef']]], - ['gotgint_6',['GOTGINT',['../group___c_m_s_i_s___device.html#gaef613e58417a7201da95b89b85931da9',1,'USB_OTG_GlobalTypeDef']]], - ['gpioa_7',['gpioa',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#gafe2a610b007523788505f398360469f5',1,'stm32f4xx_periph_registers.c']]], - ['gpiob_8',['gpiob',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#gade602c9d7c12472827a033d5b2e8aa23',1,'stm32f4xx_periph_registers.c']]], - ['gpioc_9',['gpioc',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga2dab7cbce8521c60951c6342c19bb501',1,'stm32f4xx_periph_registers.c']]], - ['gpiod_10',['gpiod',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#gad48004dee1cfc09b9c68d896ea43be11',1,'stm32f4xx_periph_registers.c']]], - ['gpioe_11',['gpioe',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga179dea27e5a083e03fc241f28043becf',1,'stm32f4xx_periph_registers.c']]], - ['gpiof_12',['gpiof',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga655c6a3fda1e8cc9126d4a2070d7e462',1,'stm32f4xx_periph_registers.c']]], - ['gpiog_13',['gpiog',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#gaed4e2f21f491ff70becdc5a582a2ad67',1,'stm32f4xx_periph_registers.c']]], - ['gpioh_14',['gpioh',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga9d4756994de85ee04d0086406c01c00b',1,'stm32f4xx_periph_registers.c']]], - ['gpioi_15',['gpioi',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga4fa8522689e49acbf45dc4e5a49d19ef',1,'stm32f4xx_periph_registers.c']]], - ['grstctl_16',['GRSTCTL',['../group___c_m_s_i_s___device.html#gaecf297022669fda29294f6fe9818ebbd',1,'USB_OTG_GlobalTypeDef']]], - ['grxfsiz_17',['GRXFSIZ',['../group___c_m_s_i_s___device.html#ga1140b76ff103608f66c26ad0a3d595d0',1,'USB_OTG_GlobalTypeDef']]], - ['grxstsp_18',['GRXSTSP',['../group___c_m_s_i_s___device.html#ga026f1fea708d42ed74b0bd8a488bc55e',1,'USB_OTG_GlobalTypeDef']]], - ['grxstsr_19',['GRXSTSR',['../group___c_m_s_i_s___device.html#ga9925d279a01c6e9713426315e2e44c87',1,'USB_OTG_GlobalTypeDef']]], - ['gtpr_20',['GTPR',['../group___c_m_s_i_s___device.html#ga5dd0cb6c861eaf26470f56f451c1edbf',1,'USART_TypeDef']]], - ['gusbcfg_21',['GUSBCFG',['../group___c_m_s_i_s___device.html#ga0633538b8b7a6f1372d38938851bba87',1,'USB_OTG_GlobalTypeDef']]] + ['hmcu_0',['hmcu',['../group___w_r_a_p_p_e_r___c_o_n_f.html#ga7bd77e7f9825a3661f357e430246bfe8',1,'hmcu: mcu_wrapper.c'],['../group___m_c_u___w_r_a_p_p_e_r.html#ga7bd77e7f9825a3661f357e430246bfe8',1,'hmcu: mcu_wrapper.c']]], + ['hmcuthread_1',['hMCUThread',['../struct_s_i_m_____m_c_u_handle_type_def.html#af2b1efce882c9bc0926c715c16773afb',1,'SIM__MCUHandleTypeDef']]] ]; diff --git a/DOCS/html/search/variables_8.js b/DOCS/html/search/variables_8.js index 160d4b0..ac82a20 100644 --- a/DOCS/html/search/variables_8.js +++ b/DOCS/html/search/variables_8.js @@ -1,23 +1,10 @@ var searchData= [ - ['haint_0',['HAINT',['../group___c_m_s_i_s___device.html#ga9fb9e43255829e50b9e5416d58ae11be',1,'USB_OTG_HostTypeDef']]], - ['haintmsk_1',['HAINTMSK',['../group___c_m_s_i_s___device.html#ga4d431ac4a59cbb89ed82a6c6cf9dfc39',1,'USB_OTG_HostTypeDef']]], - ['hcchar_2',['HCCHAR',['../group___c_m_s_i_s___device.html#gac1d0619a44758dcaeeda5c0b9c22f784',1,'USB_OTG_HostChannelTypeDef']]], - ['hcdma_3',['HCDMA',['../group___c_m_s_i_s___device.html#gaf294702e1d54fe06b43e7a3b4033dc2e',1,'USB_OTG_HostChannelTypeDef']]], - ['hcfg_4',['HCFG',['../group___c_m_s_i_s___device.html#gaa15bc4ab9217b295560dbda2235c745a',1,'USB_OTG_HostTypeDef']]], - ['hcint_5',['HCINT',['../group___c_m_s_i_s___device.html#ga830a2b58d0eb53a7ec8f9816103e3bc1',1,'USB_OTG_HostChannelTypeDef']]], - ['hcintmsk_6',['HCINTMSK',['../group___c_m_s_i_s___device.html#gae69520f078c84fb1d33cd7551ff23342',1,'USB_OTG_HostChannelTypeDef']]], - ['hcsplt_7',['HCSPLT',['../group___c_m_s_i_s___device.html#gad715951248900b9a7c8c9ddb688bb3a0',1,'USB_OTG_HostChannelTypeDef']]], - ['hctsiz_8',['HCTSIZ',['../group___c_m_s_i_s___device.html#gadde42c516172a887c570545d965200cf',1,'USB_OTG_HostChannelTypeDef']]], - ['hfir_9',['HFIR',['../group___c_m_s_i_s___device.html#ga0a6f11662e44ad485cc869f49e5aa9c9',1,'USB_OTG_HostTypeDef']]], - ['hfnum_10',['HFNUM',['../group___c_m_s_i_s___device.html#ga6a141fc0dab9ee8930465a2da604420f',1,'USB_OTG_HostTypeDef']]], - ['hfsr_11',['HFSR',['../group___c_m_s_i_s__core___debug_functions.html#gab974e7ceb2e52a3fbcaa84e06e52922d',1,'SCB_Type']]], - ['hifcr_12',['HIFCR',['../group___c_m_s_i_s___device.html#gac55c27aeea4107813c1e7da3fcf46961',1,'DMA_TypeDef']]], - ['hisr_13',['HISR',['../group___c_m_s_i_s___device.html#ga6fe40f7ac1a18c2726b328b5ec02b262',1,'DMA_TypeDef']]], - ['hmcu_14',['hmcu',['../mcu__wrapper_8c.html#a7bd77e7f9825a3661f357e430246bfe8',1,'hmcu: mcu_wrapper.c'],['../mcu__wrapper__conf_8h.html#a7bd77e7f9825a3661f357e430246bfe8',1,'hmcu: mcu_wrapper.c']]], - ['hmcuthread_15',['hMCUThread',['../struct_s_i_m_____m_c_u_handle_type_def.html#af2b1efce882c9bc0926c715c16773afb',1,'SIM__MCUHandleTypeDef']]], - ['hnptxsts_16',['HNPTXSTS',['../group___c_m_s_i_s___device.html#ga6ff3c8a6647ae7e5dfcd2ccfbfed4948',1,'USB_OTG_GlobalTypeDef']]], - ['hptxfsiz_17',['HPTXFSIZ',['../group___c_m_s_i_s___device.html#ga928fd38284165374eb5aa85ed8d4e6cb',1,'USB_OTG_GlobalTypeDef']]], - ['hptxsts_18',['HPTXSTS',['../group___c_m_s_i_s___device.html#ga3903a00940c32a9f09889e08881e7a6a',1,'USB_OTG_HostTypeDef']]], - ['htr_19',['HTR',['../group___c_m_s_i_s___device.html#ga24c3512abcc90ef75cf3e9145e5dbe9b',1,'ADC_TypeDef']]] + ['i2c1_0',['i2c1',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga71aad08961ac03edca6186fa9bc61b8e',1,'stm32f4xx_periph_registers.c']]], + ['i2c2_1',['i2c2',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#gaf4f631faa01cf5bb61ddc01eeb90d522',1,'stm32f4xx_periph_registers.c']]], + ['i2c3_2',['i2c3',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#gac651c52b4ae02ee475e7babe47132f15',1,'stm32f4xx_periph_registers.c']]], + ['i2s2ext_3',['i2s2ext',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga06974a33ee50f86662415a0c4af114a8',1,'stm32f4xx_periph_registers.c']]], + ['i2s3ext_4',['i2s3ext',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#gadc6636f1a31d3d480e01c46ffa6edddf',1,'stm32f4xx_periph_registers.c']]], + ['idmcuthread_5',['idMCUThread',['../struct_s_i_m_____m_c_u_handle_type_def.html#a52fe34944579ff4b1b6d3e85fae96546',1,'SIM__MCUHandleTypeDef']]], + ['iwdg_6',['iwdg',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#gaa40a4f8558a3a1b0ed98bad7ea997a8b',1,'stm32f4xx_periph_registers.c']]] ]; diff --git a/DOCS/html/search/variables_9.js b/DOCS/html/search/variables_9.js index fad97a7..ad88c9e 100644 --- a/DOCS/html/search/variables_9.js +++ b/DOCS/html/search/variables_9.js @@ -1,36 +1,5 @@ var searchData= [ - ['i2c1_0',['i2c1',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga71aad08961ac03edca6186fa9bc61b8e',1,'stm32f4xx_periph_registers.c']]], - ['i2c2_1',['i2c2',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#gaf4f631faa01cf5bb61ddc01eeb90d522',1,'stm32f4xx_periph_registers.c']]], - ['i2c3_2',['i2c3',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#gac651c52b4ae02ee475e7babe47132f15',1,'stm32f4xx_periph_registers.c']]], - ['i2s2ext_3',['i2s2ext',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga06974a33ee50f86662415a0c4af114a8',1,'stm32f4xx_periph_registers.c']]], - ['i2s3ext_4',['i2s3ext',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#gadc6636f1a31d3d480e01c46ffa6edddf',1,'stm32f4xx_periph_registers.c']]], - ['i2scfgr_5',['I2SCFGR',['../group___c_m_s_i_s___device.html#gaa0c41c8883cb0812d6aaf956c393584b',1,'SPI_TypeDef']]], - ['i2spr_6',['I2SPR',['../group___c_m_s_i_s___device.html#gab9be89a916ee5904381e10da10e5e8e9',1,'SPI_TypeDef']]], - ['iabr_7',['IABR',['../group___c_m_s_i_s__core___debug_functions.html#gad74aec367b7c2af1128d02d6bec57645',1,'NVIC_Type']]], - ['icer_8',['ICER',['../group___c_m_s_i_s__core___debug_functions.html#ga580236ad654b5446de777acbc55b68bc',1,'NVIC_Type']]], - ['ici_5fit_5f1_9',['ICI_IT_1',['../group___c_m_s_i_s__core___debug_functions.html#gabedfacab5e6f9c329bfa0051cb88a9d3',1,'xPSR_Type::ICI_IT_1'],['../group___c_m_s_i_s__core___debug_functions.html#gabedfacab5e6f9c329bfa0051cb88a9d3',1,'xPSR_Type::@2::ICI_IT_1']]], - ['ici_5fit_5f2_10',['ICI_IT_2',['../group___c_m_s_i_s__core___debug_functions.html#gae1df616880ca701154eba05e747605df',1,'xPSR_Type::ICI_IT_2'],['../group___c_m_s_i_s__core___debug_functions.html#gae1df616880ca701154eba05e747605df',1,'xPSR_Type::@2::ICI_IT_2']]], - ['icpr_11',['ICPR',['../group___c_m_s_i_s__core___debug_functions.html#ga1bef4ff3b0b2626aba9f916808d6477e',1,'NVIC_Type']]], - ['icr_12',['ICR',['../group___c_m_s_i_s___device.html#ga0a8c8230846fd8ff154b9fde8dfa0399',1,'DCMI_TypeDef::ICR'],['../group___c_m_s_i_s___device.html#ga0a8c8230846fd8ff154b9fde8dfa0399',1,'SDIO_TypeDef::ICR']]], - ['icsr_13',['ICSR',['../group___c_m_s_i_s__core___debug_functions.html#gaced895d6aba03d72b0d865fcc5ce44ee',1,'SCB_Type']]], - ['ictr_14',['ICTR',['../group___c_m_s_i_s__core___debug_functions.html#gacf9b76331abd768af25a10b3625da4b4',1,'SCnSCB_Type']]], - ['idcode_15',['IDCODE',['../group___c_m_s_i_s___device.html#ga24df28d0e440321b21f6f07b3bb93dea',1,'DBGMCU_TypeDef']]], - ['idmcuthread_16',['idMCUThread',['../struct_s_i_m_____m_c_u_handle_type_def.html#a52fe34944579ff4b1b6d3e85fae96546',1,'SIM__MCUHandleTypeDef']]], - ['idr_17',['IDR',['../group___c_m_s_i_s___device.html#ga601d7b0ba761c987db359b2d7173b7e0',1,'CRC_TypeDef::IDR'],['../group___c_m_s_i_s___device.html#ga328d2fe9ef1d513c3a97d30f98f0047c',1,'GPIO_TypeDef::IDR']]], - ['ier_18',['IER',['../group___c_m_s_i_s___device.html#ga6566f8cfbd1d8aa7e8db046aa35e77db',1,'CAN_TypeDef::IER'],['../group___c_m_s_i_s___device.html#ga6566f8cfbd1d8aa7e8db046aa35e77db',1,'DCMI_TypeDef::IER']]], - ['imcr_19',['IMCR',['../group___c_m_s_i_s__core___debug_functions.html#gaf0446ee5dcb6082dc8bba9adcc8ec812',1,'ITM_Type']]], - ['imr_20',['IMR',['../group___c_m_s_i_s___device.html#gae845b86e973b4bf8a33c447c261633f6',1,'EXTI_TypeDef']]], - ['ip_21',['IP',['../group___c_m_s_i_s__core___debug_functions.html#ga4fda947a8fd3237a89d43b7d5a1057cb',1,'NVIC_Type']]], - ['irr_22',['IRR',['../group___c_m_s_i_s__core___debug_functions.html#gae300b6ee4d883ceec8f3572fc0fc3d69',1,'ITM_Type']]], - ['isar_23',['ISAR',['../group___c_m_s_i_s__core___debug_functions.html#gaf2950df748750d535d5d65ac1c209563',1,'SCB_Type']]], - ['iser_24',['ISER',['../group___c_m_s_i_s__core___debug_functions.html#ga543747b83b9b1fab6545e8d36ae8b75b',1,'NVIC_Type']]], - ['ispr_25',['ISPR',['../group___c_m_s_i_s__core___debug_functions.html#gaf8330682adf1f1335bc02929acff3a3f',1,'NVIC_Type']]], - ['isr_26',['ISR',['../group___c_m_s_i_s__core___debug_functions.html#gad502ba7dbb2aab5f87c782b28f02622d',1,'IPSR_Type::ISR'],['../group___c_m_s_i_s__core___debug_functions.html#gad502ba7dbb2aab5f87c782b28f02622d',1,'IPSR_Type::@1::ISR'],['../group___c_m_s_i_s__core___debug_functions.html#gad502ba7dbb2aab5f87c782b28f02622d',1,'xPSR_Type::ISR'],['../group___c_m_s_i_s__core___debug_functions.html#gad502ba7dbb2aab5f87c782b28f02622d',1,'xPSR_Type::@2::ISR'],['../group___c_m_s_i_s___device.html#gab3c49a96815fcbee63d95e1e74f20e75',1,'RTC_TypeDef::ISR']]], - ['itatbctr0_27',['ITATBCTR0',['../group___c_m_s_i_s__core___debug_functions.html#ga9954c088735caa505adc113f6c64d812',1,'TPI_Type']]], - ['itatbctr2_28',['ITATBCTR2',['../group___c_m_s_i_s__core___debug_functions.html#ga97fb8816ad001f4910de095aa17d9db5',1,'TPI_Type']]], - ['itctrl_29',['ITCTRL',['../group___c_m_s_i_s__core___debug_functions.html#gae6b7f224b1c19c636148f991cc8db611',1,'TPI_Type']]], - ['itm_5frxbuffer_30',['ITM_RxBuffer',['../group___c_m_s_i_s__core___debug_functions.html#ga12e68e55a7badc271b948d6c7230b2a8',1,'core_cm4_matlab.h']]], - ['iwdg_31',['iwdg',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#gaa40a4f8558a3a1b0ed98bad7ea997a8b',1,'stm32f4xx_periph_registers.c']]], - ['iwr_32',['IWR',['../group___c_m_s_i_s__core___debug_functions.html#ga68e56eb5e16d2aa293b0bec5c99e50fe',1,'ITM_Type']]] + ['mcu_5fcortex_5fmem_0',['MCU_CORTEX_MEM',['../group___c_m_s_i_s__core__base.html#ga47e1165d2b04b61b504f52b9f4782708',1,'MCU_CORTEX_MEM: stm32f4xx_matlab_conf.c'],['../group___c_m_s_i_s__core__base.html#ga47e1165d2b04b61b504f52b9f4782708',1,'MCU_CORTEX_MEM: stm32f4xx_matlab_conf.c']]], + ['mcu_5fmem_1',['MCU_MEM',['../group___peripheral__memory__map.html#gaf157a51d290d1383d493a6a2fe0241fc',1,'MCU_MEM: stm32f4xx_matlab_conf.c'],['../group___peripheral__memory__map.html#gaf157a51d290d1383d493a6a2fe0241fc',1,'MCU_MEM: stm32f4xx_matlab_conf.c']]] ]; diff --git a/DOCS/html/search/variables_a.js b/DOCS/html/search/variables_a.js index c8da0b8..c7cb1be 100644 --- a/DOCS/html/search/variables_a.js +++ b/DOCS/html/search/variables_a.js @@ -1,12 +1,15 @@ var searchData= [ - ['jdr1_0',['JDR1',['../group___c_m_s_i_s___device.html#ga22fa21352be442bd02f9c26a1013d598',1,'ADC_TypeDef']]], - ['jdr2_1',['JDR2',['../group___c_m_s_i_s___device.html#gae9156af81694b7a85923348be45a2167',1,'ADC_TypeDef']]], - ['jdr3_2',['JDR3',['../group___c_m_s_i_s___device.html#ga3a54028253a75a470fccf841178cba46',1,'ADC_TypeDef']]], - ['jdr4_3',['JDR4',['../group___c_m_s_i_s___device.html#ga9274ceea3b2c6d5c1903d0a7abad91a1',1,'ADC_TypeDef']]], - ['jofr1_4',['JOFR1',['../group___c_m_s_i_s___device.html#ga427dda1678f254bd98b1f321d7194a3b',1,'ADC_TypeDef']]], - ['jofr2_5',['JOFR2',['../group___c_m_s_i_s___device.html#ga11e65074b9f06b48c17cdfa5bea9f125',1,'ADC_TypeDef']]], - ['jofr3_6',['JOFR3',['../group___c_m_s_i_s___device.html#ga613f6b76d20c1a513976b920ecd7f4f8',1,'ADC_TypeDef']]], - ['jofr4_7',['JOFR4',['../group___c_m_s_i_s___device.html#ga2fd59854223e38158b4138ee8e913ab3',1,'ADC_TypeDef']]], - ['jsqr_8',['JSQR',['../group___c_m_s_i_s___device.html#ga75e0cc079831adcc051df456737d3ae4',1,'ADC_TypeDef']]] + ['oc1_5fgpiox_0',['OC1_GPIOx',['../struct_channels___sim.html#a48f9b22f7e44d1b56aa793c2344e06d1',1,'Channels_Sim']]], + ['oc1_5fpin_5fshift_1',['OC1_PIN_SHIFT',['../struct_channels___sim.html#a2d558fbd100d8052eb0e235ad9b1edfe',1,'Channels_Sim']]], + ['oc1ref_2',['OC1REF',['../struct_channels___sim.html#aae6762f43d55e99c3076c9f7e5cda5d9',1,'Channels_Sim']]], + ['oc2_5fgpiox_3',['OC2_GPIOx',['../struct_channels___sim.html#a095026a66ff13e090dae52ee17263f2d',1,'Channels_Sim']]], + ['oc2_5fpin_5fshift_4',['OC2_PIN_SHIFT',['../struct_channels___sim.html#ac2fdf8c4e985eee4ab2e6c82251c12cf',1,'Channels_Sim']]], + ['oc2ref_5',['OC2REF',['../struct_channels___sim.html#aa038da4ce5b26f3d86cda283a9cd749e',1,'Channels_Sim']]], + ['oc3_5fgpiox_6',['OC3_GPIOx',['../struct_channels___sim.html#a7d239c94641795d3caf5c28f8b7cc68d',1,'Channels_Sim']]], + ['oc3_5fpin_5fshift_7',['OC3_PIN_SHIFT',['../struct_channels___sim.html#ac15bcebfa2102716c5b6a4f80b2d51ab',1,'Channels_Sim']]], + ['oc3ref_8',['OC3REF',['../struct_channels___sim.html#abbea161f1b685a5d353d453fc9b56284',1,'Channels_Sim']]], + ['oc4_5fgpiox_9',['OC4_GPIOx',['../struct_channels___sim.html#a851558373b04d1a8a5dbb3c0da9279d8',1,'Channels_Sim']]], + ['oc4_5fpin_5fshift_10',['OC4_PIN_SHIFT',['../struct_channels___sim.html#aa87736409f5ca9986200fcb480920c5b',1,'Channels_Sim']]], + ['oc4ref_11',['OC4REF',['../struct_channels___sim.html#a1c6c166d70bfe9597717f6892da4f446',1,'Channels_Sim']]] ]; diff --git a/DOCS/html/search/variables_b.js b/DOCS/html/search/variables_b.js index 156845b..e1d0ad8 100644 --- a/DOCS/html/search/variables_b.js +++ b/DOCS/html/search/variables_b.js @@ -1,5 +1,6 @@ var searchData= [ - ['keyr_0',['KEYR',['../group___c_m_s_i_s___device.html#ga84c491be6c66b1d5b6a2efd0740b3d0c',1,'FLASH_TypeDef']]], - ['kr_1',['KR',['../group___c_m_s_i_s___device.html#ga2f692354bde770f2a5e3e1b294ec064b',1,'IWDG_TypeDef']]] + ['periph_5fbase_0',['PERIPH_BASE',['../struct__memory.html#a535f5001cfe9967fb7040cd5b081d944',1,'_memory']]], + ['periph_5fbb_5fbase_1',['PERIPH_BB_BASE',['../struct__memory.html#a9fbcd0d73c2b2229b9f95743f280382c',1,'_memory']]], + ['pwr_2',['pwr',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#gaba54a48e7552e8a1301cc87cdfcacfee',1,'stm32f4xx_periph_registers.c']]] ]; diff --git a/DOCS/html/search/variables_c.js b/DOCS/html/search/variables_c.js index 10073de..4e5abdc 100644 --- a/DOCS/html/search/variables_c.js +++ b/DOCS/html/search/variables_c.js @@ -1,11 +1,7 @@ var searchData= [ - ['lar_0',['LAR',['../group___c_m_s_i_s__core___debug_functions.html#gacc9e51f871c357a9094105435b150d13',1,'ITM_Type']]], - ['lckr_1',['LCKR',['../group___c_m_s_i_s___device.html#ga2612a0f4b3fbdbb6293f6dc70105e190',1,'GPIO_TypeDef']]], - ['lifcr_2',['LIFCR',['../group___c_m_s_i_s___device.html#gac4f7bf4cb172024bfc940c00167cd04e',1,'DMA_TypeDef']]], - ['lisr_3',['LISR',['../group___c_m_s_i_s___device.html#ga5cdef358e9e95b570358e1f6a3a7f492',1,'DMA_TypeDef']]], - ['load_4',['LOAD',['../group___c_m_s_i_s__core___debug_functions.html#ga0c1333686137b7e25a46bd548a5b5bc3',1,'SysTick_Type']]], - ['lsr_5',['LSR',['../group___c_m_s_i_s__core___debug_functions.html#ga7219432d03f6cd1d220f4fe10aef4880',1,'ITM_Type']]], - ['lsucnt_6',['LSUCNT',['../group___c_m_s_i_s__core___debug_functions.html#gae886261750c8c90d67a2f276d074e9c3',1,'DWT_Type']]], - ['ltr_7',['LTR',['../group___c_m_s_i_s___device.html#ga9f8712dfef7125c0bb39db11f2b7416b',1,'ADC_TypeDef']]] + ['rcc_0',['rcc',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga33f5f83bbcee4994fef4f29192860875',1,'stm32f4xx_periph_registers.c']]], + ['reload_1',['RELOAD',['../struct_t_i_m___sim.html#a1798863b8849972c8e0cf75abbbd116b',1,'TIM_Sim']]], + ['rng_2',['rng',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#gae5244ff1d33b8f1c69abb81fda62b538',1,'stm32f4xx_periph_registers.c']]], + ['rtc_3',['rtc',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga423742450422a8873970b076a7e25028',1,'stm32f4xx_periph_registers.c']]] ]; diff --git a/DOCS/html/search/variables_d.js b/DOCS/html/search/variables_d.js index fa86b09..74e3a6e 100644 --- a/DOCS/html/search/variables_d.js +++ b/DOCS/html/search/variables_d.js @@ -1,53 +1,18 @@ var searchData= [ - ['m0ar_0',['M0AR',['../group___c_m_s_i_s___device.html#ga63b4d166f4ab5024db6b493a7ab7b640',1,'DMA_Stream_TypeDef']]], - ['m1ar_1',['M1AR',['../group___c_m_s_i_s___device.html#gaee7782244ceb4791d9a3891804ac47ac',1,'DMA_Stream_TypeDef']]], - ['maca0hr_2',['MACA0HR',['../group___c_m_s_i_s___device.html#gab8b4520c137846f0a128146144514419',1,'ETH_TypeDef']]], - ['maca0lr_3',['MACA0LR',['../group___c_m_s_i_s___device.html#ga45e8169adb601f00e411b840f9fbb5af',1,'ETH_TypeDef']]], - ['maca1hr_4',['MACA1HR',['../group___c_m_s_i_s___device.html#ga3a6cc81e1024f9a93ec7653d32f12dcb',1,'ETH_TypeDef']]], - ['maca1lr_5',['MACA1LR',['../group___c_m_s_i_s___device.html#gaadfb486dd07e2fd02fb491733deffd9b',1,'ETH_TypeDef']]], - ['maca2hr_6',['MACA2HR',['../group___c_m_s_i_s___device.html#ga38f1ce04678d5141e115cfd6f7b803d1',1,'ETH_TypeDef']]], - ['maca2lr_7',['MACA2LR',['../group___c_m_s_i_s___device.html#ga423b12ab536a1c4fdb1ce63f645822a7',1,'ETH_TypeDef']]], - ['maca3hr_8',['MACA3HR',['../group___c_m_s_i_s___device.html#gad02ff09f7ce33f093ad04b84fee2bdec',1,'ETH_TypeDef']]], - ['maca3lr_9',['MACA3LR',['../group___c_m_s_i_s___device.html#ga2ba9f73c7fa756305d54a8f80872c6df',1,'ETH_TypeDef']]], - ['maccr_10',['MACCR',['../group___c_m_s_i_s___device.html#ga20acbcac1c35f66de94c9ff0e2ddc7b0',1,'ETH_TypeDef']]], - ['macdbgr_11',['MACDBGR',['../group___c_m_s_i_s___device.html#ga8f35b3865c1f5fce934c1d48b9a63442',1,'ETH_TypeDef']]], - ['macfcr_12',['MACFCR',['../group___c_m_s_i_s___device.html#ga12f62d3d3b9ee30c20c324b146e72795',1,'ETH_TypeDef']]], - ['macffr_13',['MACFFR',['../group___c_m_s_i_s___device.html#ga8ad4e3dbde1518ecde5d979c2a89a76a',1,'ETH_TypeDef']]], - ['machthr_14',['MACHTHR',['../group___c_m_s_i_s___device.html#ga121212bdb227106df681d24e5d896a4e',1,'ETH_TypeDef']]], - ['machtlr_15',['MACHTLR',['../group___c_m_s_i_s___device.html#ga1d34ab8e5c2041c00ba9526b3958099d',1,'ETH_TypeDef']]], - ['macimr_16',['MACIMR',['../group___c_m_s_i_s___device.html#gac42b829c02429cb9363563f7eb9d58ed',1,'ETH_TypeDef']]], - ['macmiiar_17',['MACMIIAR',['../group___c_m_s_i_s___device.html#ga9ea1e1c6615eb3bd70eb328dba65fc87',1,'ETH_TypeDef']]], - ['macmiidr_18',['MACMIIDR',['../group___c_m_s_i_s___device.html#ga87c7687c35332bf5ee86473043652146',1,'ETH_TypeDef']]], - ['macpmtcsr_19',['MACPMTCSR',['../group___c_m_s_i_s___device.html#gabbb2f4f89e7d8c3242365b4506e43217',1,'ETH_TypeDef']]], - ['macrwuffr_20',['MACRWUFFR',['../group___c_m_s_i_s___device.html#ga129dcc23d48588d5af7dd218b617933d',1,'ETH_TypeDef']]], - ['macsr_21',['MACSR',['../group___c_m_s_i_s___device.html#ga1173127526cca9128e409bc83c7729dc',1,'ETH_TypeDef']]], - ['macvlantr_22',['MACVLANTR',['../group___c_m_s_i_s___device.html#ga92ff1fe799bb33d13efbaa1195867781',1,'ETH_TypeDef']]], - ['mask_23',['MASK',['../group___c_m_s_i_s___device.html#ga5c955643593b4aedbe9f84f054d26522',1,'SDIO_TypeDef']]], - ['mask0_24',['MASK0',['../group___c_m_s_i_s__core___debug_functions.html#ga84089e08ecf14b86f92c727a568ceac4',1,'DWT_Type']]], - ['mask1_25',['MASK1',['../group___c_m_s_i_s__core___debug_functions.html#ga6f663226a4f3409b0a73651b5a90b3af',1,'DWT_Type']]], - ['mask2_26',['MASK2',['../group___c_m_s_i_s__core___debug_functions.html#ga32213bf45fbe36e1823e69028f7edef2',1,'DWT_Type']]], - ['mask3_27',['MASK3',['../group___c_m_s_i_s__core___debug_functions.html#ga51e9ef8e2238e82f3b40aa2599397637',1,'DWT_Type']]], - ['mcr_28',['MCR',['../group___c_m_s_i_s___device.html#ga27af4e9f888f0b7b1e8da7e002d98798',1,'CAN_TypeDef']]], - ['mcu_5fcortex_5fmem_29',['MCU_CORTEX_MEM',['../group___c_m_s_i_s__core__base.html#ga47e1165d2b04b61b504f52b9f4782708',1,'MCU_CORTEX_MEM: stm32f4xx_matlab_conf.c'],['../group___c_m_s_i_s__core__base.html#ga47e1165d2b04b61b504f52b9f4782708',1,'MCU_CORTEX_MEM: stm32f4xx_matlab_conf.c']]], - ['mcu_5fmem_30',['MCU_MEM',['../group___peripheral__memory__map.html#gaf157a51d290d1383d493a6a2fe0241fc',1,'MCU_MEM: stm32f4xx_matlab_conf.c'],['../group___peripheral__memory__map.html#gaf157a51d290d1383d493a6a2fe0241fc',1,'MCU_MEM: stm32f4xx_matlab_conf.c']]], - ['memrmp_31',['MEMRMP',['../group___c_m_s_i_s___device.html#gab36c409d0a009e3ce5a89ac55d3ff194',1,'SYSCFG_TypeDef']]], - ['misr_32',['MISR',['../group___c_m_s_i_s___device.html#ga524e134cec519206cb41d0545e382978',1,'DCMI_TypeDef']]], - ['mmccr_33',['MMCCR',['../group___c_m_s_i_s___device.html#gad57490cb3a07132702f96d8b5d547c89',1,'ETH_TypeDef']]], - ['mmcrfaecr_34',['MMCRFAECR',['../group___c_m_s_i_s___device.html#ga65bb525a3f4d3ee131f9a7ed899d5eef',1,'ETH_TypeDef']]], - ['mmcrfcecr_35',['MMCRFCECR',['../group___c_m_s_i_s___device.html#gaff6eeec1afa983f153ff0786c8902d43',1,'ETH_TypeDef']]], - ['mmcrgufcr_36',['MMCRGUFCR',['../group___c_m_s_i_s___device.html#ga6ff264b60a3b40f40d136288e5ec5ba8',1,'ETH_TypeDef']]], - ['mmcrimr_37',['MMCRIMR',['../group___c_m_s_i_s___device.html#ga63872a3017c14a869c647123573dd002',1,'ETH_TypeDef']]], - ['mmcrir_38',['MMCRIR',['../group___c_m_s_i_s___device.html#gaea29ac183c979d0cb95ad3781fe9ed91',1,'ETH_TypeDef']]], - ['mmctgfcr_39',['MMCTGFCR',['../group___c_m_s_i_s___device.html#ga71d932b554a5548e5d85ed81e58c1ed0',1,'ETH_TypeDef']]], - ['mmctgfmsccr_40',['MMCTGFMSCCR',['../group___c_m_s_i_s___device.html#ga50c8425cf8d27268b3272ace0a224a94',1,'ETH_TypeDef']]], - ['mmctgfsccr_41',['MMCTGFSCCR',['../group___c_m_s_i_s___device.html#ga23970354d69354ab78165e76afd6c2f7',1,'ETH_TypeDef']]], - ['mmctimr_42',['MMCTIMR',['../group___c_m_s_i_s___device.html#ga18e294dd2625a93ebf2aab9f2b3c4911',1,'ETH_TypeDef']]], - ['mmctir_43',['MMCTIR',['../group___c_m_s_i_s___device.html#ga614e0b81fce7cf218a357f8a0a3de7b8',1,'ETH_TypeDef']]], - ['mmfar_44',['MMFAR',['../group___c_m_s_i_s__core___debug_functions.html#gae9d94d186615d57d38c9253cb842d244',1,'SCB_Type']]], - ['mmfr_45',['MMFR',['../group___c_m_s_i_s__core___debug_functions.html#gab6c914b579d22d7eb86d0e3d9a5fde71',1,'SCB_Type']]], - ['moder_46',['MODER',['../group___c_m_s_i_s___device.html#ga2b671a94c63a612f81e0e9de8152d01c',1,'GPIO_TypeDef']]], - ['msr_47',['MSR',['../group___c_m_s_i_s___device.html#gacdd4c1b5466be103fb2bb2a225b1d3a9',1,'CAN_TypeDef']]], - ['mvfr0_48',['MVFR0',['../group___c_m_s_i_s__core___debug_functions.html#ga9b0103b438c8922eaea5624f71afbbc8',1,'FPU_Type']]], - ['mvfr1_49',['MVFR1',['../group___c_m_s_i_s__core___debug_functions.html#ga0a610dc4212de3ce1ad62e9afa76c728',1,'FPU_Type']]] + ['sdio_0',['sdio',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga8b6edf2e7d9debf95d77d172c8c32cb7',1,'stm32f4xx_periph_registers.c']]], + ['sim_5fsample_5ftime_1',['SIM_Sample_Time',['../struct_s_i_m_____m_c_u_handle_type_def.html#ab19a05224f30fab089c5d5e18fdcca36',1,'SIM__MCUHandleTypeDef']]], + ['slave_5fchannels_2',['Slave_Channels',['../stm32f4xx__matlab__tim_8c.html#a66e48ba3c30d98536e05b7f5435e9828',1,'stm32f4xx_matlab_tim.c']]], + ['spi1_3',['spi1',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga8cc3430b6591549759eb42cc2004a889',1,'stm32f4xx_periph_registers.c']]], + ['spi2_4',['spi2',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#gaafd9bde301b8cacea574ec4eea0e474f',1,'stm32f4xx_periph_registers.c']]], + ['spi3_5',['spi3',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga050e08b3b630957cd79c0e69968308bd',1,'stm32f4xx_periph_registers.c']]], + ['sram1_5fbase_6',['SRAM1_BASE',['../struct__memory.html#ac7c83f52956da4c75f4946348f7bfa1a',1,'_memory']]], + ['sram1_5fbb_5fbase_7',['SRAM1_BB_BASE',['../struct__memory.html#ac88d0add27755615a9390fec8c64dafc',1,'_memory']]], + ['sram2_5fbase_8',['SRAM2_BASE',['../struct__memory.html#a57bfa1d7c82d97792cbb6c2d366dd48d',1,'_memory']]], + ['sram2_5fbb_5fbase_9',['SRAM2_BB_BASE',['../struct__memory.html#a5db33a541cebb596c2976d4fc409a611',1,'_memory']]], + ['status_10',['status',['../mexing_8m.html#ab1dc10c44c3fef32dbb7508037a5a3d6',1,'mexing.m']]], + ['syscfg_11',['syscfg',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga973efd19b15b8e1452258c3a02fda513',1,'stm32f4xx_periph_registers.c']]], + ['systemclock_12',['SystemClock',['../group___w_r_a_p_p_e_r___c_o_n_f.html#ga6a1676e08289f73141f9fa8419311385',1,'mcu_wrapper.c']]], + ['systemclock_5fstep_13',['SystemClock_step',['../group___w_r_a_p_p_e_r___c_o_n_f.html#gae50392991204ce9a89dd9aa8bf43634f',1,'mcu_wrapper.c']]], + ['systemclockdouble_14',['SystemClockDouble',['../group___w_r_a_p_p_e_r___c_o_n_f.html#gaf1cb3ba542e380d1f12d30579598c48c',1,'mcu_wrapper.c']]] ]; diff --git a/DOCS/html/search/variables_e.js b/DOCS/html/search/variables_e.js index 2c83d18..db1bd5b 100644 --- a/DOCS/html/search/variables_e.js +++ b/DOCS/html/search/variables_e.js @@ -1,6 +1,33 @@ var searchData= [ - ['n_0',['N',['../group___c_m_s_i_s__core___debug_functions.html#gabae0610bc2a97bbf7f689e953e0b451f',1,'APSR_Type::N'],['../group___c_m_s_i_s__core___debug_functions.html#gabae0610bc2a97bbf7f689e953e0b451f',1,'APSR_Type::@0::N'],['../group___c_m_s_i_s__core___debug_functions.html#gabae0610bc2a97bbf7f689e953e0b451f',1,'xPSR_Type::N'],['../group___c_m_s_i_s__core___debug_functions.html#gabae0610bc2a97bbf7f689e953e0b451f',1,'xPSR_Type::@2::N']]], - ['ndtr_1',['NDTR',['../group___c_m_s_i_s___device.html#gaf60258ad5a25addc1e8969665d0c1731',1,'DMA_Stream_TypeDef']]], - ['npriv_2',['nPRIV',['../group___c_m_s_i_s__core___debug_functions.html#ga2a6e513e8a6bf4e58db169e312172332',1,'CONTROL_Type::nPRIV'],['../group___c_m_s_i_s__core___debug_functions.html#ga2a6e513e8a6bf4e58db169e312172332',1,'CONTROL_Type::@3::nPRIV']]] + ['tim1_0',['tim1',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#gaedba2af9d3a451898c4116468f63e31c',1,'stm32f4xx_periph_registers.c']]], + ['tim10_1',['tim10',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga5fc888fc63ae5329a954de3db43caefd',1,'stm32f4xx_periph_registers.c']]], + ['tim11_2',['tim11',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga720638f02cb775a2bdd6b866847b106f',1,'stm32f4xx_periph_registers.c']]], + ['tim12_3',['tim12',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#gaf7e88c4f7e226298777e23ce86e0f68e',1,'stm32f4xx_periph_registers.c']]], + ['tim12s_4',['tim12s',['../stm32f4xx__matlab__conf_8h.html#ad582b36106c35060b40bddfca929350e',1,'stm32f4xx_matlab_conf.h']]], + ['tim13_5',['tim13',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga5b7e61840360c6a797a1d137d1937c91',1,'stm32f4xx_periph_registers.c']]], + ['tim14_6',['tim14',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga8ade2aee59ea8e56c5b2b9fdd81e4480',1,'stm32f4xx_periph_registers.c']]], + ['tim1_5ftrgo_7',['TIM1_TRGO',['../struct_slave_channels.html#a1bb1d8089ac5eff5af1df34649b50a94',1,'SlaveChannels']]], + ['tim1s_8',['tim1s',['../stm32f4xx__matlab__conf_8h.html#ab3aec69c8e446c577e391796728e4742',1,'stm32f4xx_matlab_conf.h']]], + ['tim2_9',['tim2',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#gaced1e82df483246f3faed614153db985',1,'stm32f4xx_periph_registers.c']]], + ['tim2_5ftrgo_10',['TIM2_TRGO',['../struct_slave_channels.html#a7b0ea9ba4357a49b11b9c1ef79252613',1,'SlaveChannels']]], + ['tim3_11',['tim3',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga8a9462732233ea58ea84b420b20866ee',1,'stm32f4xx_periph_registers.c']]], + ['tim3_5ftrgo_12',['TIM3_TRGO',['../struct_slave_channels.html#aab5be57f956df4be03effc282a0479e5',1,'SlaveChannels']]], + ['tim3s_13',['tim3s',['../stm32f4xx__matlab__conf_8h.html#aefb416b7445ce7c77f15d96cd54cd2f5',1,'stm32f4xx_matlab_conf.h']]], + ['tim4_14',['tim4',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#gab15912b4a5af74002ab2c14632e0c538',1,'stm32f4xx_periph_registers.c']]], + ['tim4_5ftrgo_15',['TIM4_TRGO',['../struct_slave_channels.html#ab9bff03506a4f82f55b13a1065bccaa6',1,'SlaveChannels']]], + ['tim4s_16',['tim4s',['../stm32f4xx__matlab__conf_8h.html#ab42529334dbaea26f59721c40f7a7782',1,'stm32f4xx_matlab_conf.h']]], + ['tim5_17',['tim5',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga7f9bc8648d83bd2b1959b43b1f11b70e',1,'stm32f4xx_periph_registers.c']]], + ['tim5_5ftrgo_18',['TIM5_TRGO',['../struct_slave_channels.html#a9780a406b85390dddcc18d4c6e606462',1,'SlaveChannels']]], + ['tim6_19',['tim6',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#gac7a5702d9b22c89aa44e3f5161cd8c9d',1,'stm32f4xx_periph_registers.c']]], + ['tim6_5ftrgo_20',['TIM6_TRGO',['../struct_slave_channels.html#a2b1207a49068c13e3257396b4f369932',1,'SlaveChannels']]], + ['tim7_21',['tim7',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#gad32365c7344044f1d4b358b16faf768b',1,'stm32f4xx_periph_registers.c']]], + ['tim7_5ftrgo_22',['TIM7_TRGO',['../struct_slave_channels.html#a8a06a1b3f32a6abaf0a7ad38e27cf0e1',1,'SlaveChannels']]], + ['tim7s_23',['tim7s',['../stm32f4xx__matlab__conf_8h.html#af4ae2f8710078d4b2c0f07a4265ba66a',1,'stm32f4xx_matlab_conf.h']]], + ['tim8_24',['tim8',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga7cd2675665015ace1ee986d66c9cbfb2',1,'stm32f4xx_periph_registers.c']]], + ['tim8_5ftrgo_25',['TIM8_TRGO',['../struct_slave_channels.html#a591c0247b983b782f88fb92aea40f0c7',1,'SlaveChannels']]], + ['tim9_26',['tim9',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga3d6c0e6c095d01dac6c94c83c2e9e55f',1,'stm32f4xx_periph_registers.c']]], + ['ts_27',['Ts',['../mexing_8m.html#ac910fa4e03fcc57ffc78b3693e910e1a',1,'mexing.m']]], + ['tx_5fcnt_28',['tx_cnt',['../struct_t_i_m___sim.html#a369177ee20a3798f0d7b98cf7c549498',1,'TIM_Sim']]], + ['tx_5fstep_29',['tx_step',['../struct_t_i_m___sim.html#a838a96dee1a1980434ae35295f85141e',1,'TIM_Sim']]] ]; diff --git a/DOCS/html/search/variables_f.js b/DOCS/html/search/variables_f.js index 24f7268..332f267 100644 --- a/DOCS/html/search/variables_f.js +++ b/DOCS/html/search/variables_f.js @@ -1,24 +1,11 @@ var searchData= [ - ['oar1_0',['OAR1',['../group___c_m_s_i_s___device.html#ga08b4be0d626a00f26bc295b379b3bba6',1,'I2C_TypeDef']]], - ['oar2_1',['OAR2',['../group___c_m_s_i_s___device.html#gab5c57ffed0351fa064038939a6c0bbf6',1,'I2C_TypeDef']]], - ['oc1_5fgpiox_2',['OC1_GPIOx',['../struct_channels___sim.html#a48f9b22f7e44d1b56aa793c2344e06d1',1,'Channels_Sim']]], - ['oc1_5fpin_5fshift_3',['OC1_PIN_SHIFT',['../struct_channels___sim.html#a2d558fbd100d8052eb0e235ad9b1edfe',1,'Channels_Sim']]], - ['oc1ref_4',['OC1REF',['../struct_channels___sim.html#aae6762f43d55e99c3076c9f7e5cda5d9',1,'Channels_Sim']]], - ['oc2_5fgpiox_5',['OC2_GPIOx',['../struct_channels___sim.html#a095026a66ff13e090dae52ee17263f2d',1,'Channels_Sim']]], - ['oc2_5fpin_5fshift_6',['OC2_PIN_SHIFT',['../struct_channels___sim.html#ac2fdf8c4e985eee4ab2e6c82251c12cf',1,'Channels_Sim']]], - ['oc2ref_7',['OC2REF',['../struct_channels___sim.html#aa038da4ce5b26f3d86cda283a9cd749e',1,'Channels_Sim']]], - ['oc3_5fgpiox_8',['OC3_GPIOx',['../struct_channels___sim.html#a7d239c94641795d3caf5c28f8b7cc68d',1,'Channels_Sim']]], - ['oc3_5fpin_5fshift_9',['OC3_PIN_SHIFT',['../struct_channels___sim.html#ac15bcebfa2102716c5b6a4f80b2d51ab',1,'Channels_Sim']]], - ['oc3ref_10',['OC3REF',['../struct_channels___sim.html#abbea161f1b685a5d353d453fc9b56284',1,'Channels_Sim']]], - ['oc4_5fgpiox_11',['OC4_GPIOx',['../struct_channels___sim.html#a851558373b04d1a8a5dbb3c0da9279d8',1,'Channels_Sim']]], - ['oc4_5fpin_5fshift_12',['OC4_PIN_SHIFT',['../struct_channels___sim.html#aa87736409f5ca9986200fcb480920c5b',1,'Channels_Sim']]], - ['oc4ref_13',['OC4REF',['../struct_channels___sim.html#a1c6c166d70bfe9597717f6892da4f446',1,'Channels_Sim']]], - ['odr_14',['ODR',['../group___c_m_s_i_s___device.html#gabff7fffd2b5a718715a130006590c75c',1,'GPIO_TypeDef']]], - ['optcr_15',['OPTCR',['../group___c_m_s_i_s___device.html#gacfef9b6d7da4271943edc04d7dfdf595',1,'FLASH_TypeDef']]], - ['optcr1_16',['OPTCR1',['../group___c_m_s_i_s___device.html#ga1dddf235f246a1d4e7e5084cd51e2dd0',1,'FLASH_TypeDef']]], - ['optkeyr_17',['OPTKEYR',['../group___c_m_s_i_s___device.html#gafc4900646681dfe1ca43133d376c4423',1,'FLASH_TypeDef']]], - ['or_18',['OR',['../group___c_m_s_i_s___device.html#ga75ade4a9b3d40781fd80ce3e6589e98b',1,'TIM_TypeDef']]], - ['ospeedr_19',['OSPEEDR',['../group___c_m_s_i_s___device.html#ga328d16cc6213783ede54e4059ffd50a3',1,'GPIO_TypeDef']]], - ['otyper_20',['OTYPER',['../group___c_m_s_i_s___device.html#ga9543592bda60cb5261075594bdeedac9',1,'GPIO_TypeDef']]] + ['uart4_0',['uart4',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#gaeac987df31348c6546d30bf20d1202b1',1,'stm32f4xx_periph_registers.c']]], + ['uart5_1',['uart5',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga334a742f4e47d9275a7ca0b6a64f3b9b',1,'stm32f4xx_periph_registers.c']]], + ['usart1_2',['usart1',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga6008378d0a594dbb3373976f11998c07',1,'stm32f4xx_periph_registers.c']]], + ['usart2_3',['usart2',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga6704391eb1d9b549ec4a30bff051c840',1,'stm32f4xx_periph_registers.c']]], + ['usart3_4',['usart3',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga34a4f060994660316b3ccf64ef2ca061',1,'stm32f4xx_periph_registers.c']]], + ['usart6_5',['usart6',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#gac976d368ba60c6c4fb520f15ffc973ed',1,'stm32f4xx_periph_registers.c']]], + ['usb_5fotg_5ffs_5fperiph_6',['usb_otg_fs_periph',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#gab7326fc264f9026f7d5be1914a222257',1,'stm32f4xx_periph_registers.c']]], + ['usb_5fotg_5fhs_5fperiph_7',['usb_otg_hs_periph',['../group___p_e_r_i_p_h___v_a_r_s___f_o_r___d_e_b_u_g.html#ga4e565603c7406e27b1f5503de3a8c41b',1,'stm32f4xx_periph_registers.c']]] ]; diff --git a/DOCS/html/stdint_8h.html b/DOCS/html/stdint_8h.html deleted file mode 100644 index f2a0e03..0000000 --- a/DOCS/html/stdint_8h.html +++ /dev/null @@ -1,1749 +0,0 @@ - - - - - - - -STM MATLAB Simulator: F:/Work/Projects/MATLAB/matlab_stm_emulate/MCU_STM32F4xx_Matlab/Drivers/CMSIS/stdint.h File Reference - - - - - - - - - - - -
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    #define __ARMCLIB_VERSION   6190004
     
    #define __INT64   __int64
     
    #define __INT64_C_SUFFIX__   ll
     
    #define __PASTE2(x, y)   x ## y
     
    #define __PASTE(x, y)   __PASTE2(x, y)
     
    #define __INT64_C(x)   __ESCAPE__(__PASTE(x, __INT64_C_SUFFIX__))
     
    #define __UINT64_C(x)   __ESCAPE__(__PASTE(x ## u, __INT64_C_SUFFIX__))
     
    #define __LONGLONG   __int64
     
    #define __STDINT_DECLS
     
    #define __CLIBNS
     
    #define INT8_MIN   -128
     
    #define INT16_MIN   -32768
     
    #define INT32_MIN   (~0x7fffffff) /* -2147483648 is unsigned */
     
    #define INT64_MIN   __INT64_C(~0x7fffffffffffffff) /* -9223372036854775808 is unsigned */
     
    #define INT8_MAX   127
     
    #define INT16_MAX   32767
     
    #define INT32_MAX   2147483647
     
    #define INT64_MAX   __INT64_C(9223372036854775807)
     
    #define UINT8_MAX   255
     
    #define UINT16_MAX   65535
     
    #define UINT32_MAX   4294967295u
     
    #define UINT64_MAX   __UINT64_C(18446744073709551615)
     
    #define INT_LEAST8_MIN   -128
     
    #define INT_LEAST16_MIN   -32768
     
    #define INT_LEAST32_MIN   (~0x7fffffff)
     
    #define INT_LEAST64_MIN   __INT64_C(~0x7fffffffffffffff)
     
    #define INT_LEAST8_MAX   127
     
    #define INT_LEAST16_MAX   32767
     
    #define INT_LEAST32_MAX   2147483647
     
    #define INT_LEAST64_MAX   __INT64_C(9223372036854775807)
     
    #define UINT_LEAST8_MAX   255
     
    #define UINT_LEAST16_MAX   65535
     
    #define UINT_LEAST32_MAX   4294967295u
     
    #define UINT_LEAST64_MAX   __UINT64_C(18446744073709551615)
     
    #define INT_FAST8_MIN   (~0x7fffffff)
     
    #define INT_FAST16_MIN   (~0x7fffffff)
     
    #define INT_FAST32_MIN   (~0x7fffffff)
     
    #define INT_FAST64_MIN   __INT64_C(~0x7fffffffffffffff)
     
    #define INT_FAST8_MAX   2147483647
     
    #define INT_FAST16_MAX   2147483647
     
    #define INT_FAST32_MAX   2147483647
     
    #define INT_FAST64_MAX   __INT64_C(9223372036854775807)
     
    #define UINT_FAST8_MAX   4294967295u
     
    #define UINT_FAST16_MAX   4294967295u
     
    #define UINT_FAST32_MAX   4294967295u
     
    #define UINT_FAST64_MAX   __UINT64_C(18446744073709551615)
     
    #define INTPTR_MIN   INT32_MIN
     
    #define INTPTR_MAX   INT32_MAX
     
    #define UINTPTR_MAX   UINT32_MAX
     
    #define INTMAX_MIN   __ESCAPE__(~0x7fffffffffffffffll)
     
    #define INTMAX_MAX   __ESCAPE__(9223372036854775807ll)
     
    #define UINTMAX_MAX   __ESCAPE__(18446744073709551615ull)
     
    #define PTRDIFF_MIN   INT32_MIN
     
    #define PTRDIFF_MAX   INT32_MAX
     
    #define SIG_ATOMIC_MIN   (~0x7fffffff)
     
    #define SIG_ATOMIC_MAX   2147483647
     
    #define SIZE_MAX   UINT32_MAX
     
    #define WCHAR_MIN   0
     
    #define WCHAR_MAX   65535
     
    #define WINT_MIN   (~0x7fffffff)
     
    #define WINT_MAX   2147483647
     
    #define INT8_C(x)   (x)
     
    #define INT16_C(x)   (x)
     
    #define INT32_C(x)   (x)
     
    #define INT64_C(x)   __INT64_C(x)
     
    #define UINT8_C(x)   (x ## u)
     
    #define UINT16_C(x)   (x ## u)
     
    #define UINT32_C(x)   (x ## u)
     
    #define UINT64_C(x)   __UINT64_C(x)
     
    #define INTMAX_C(x)   __ESCAPE__(x ## ll)
     
    #define UINTMAX_C(x)   __ESCAPE__(x ## ull)
     
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    -Typedefs

    typedef signed char int8_t
     
    typedef signed short int int16_t
     
    typedef signed int int32_t
     
    typedef signed __INT64 int64_t
     
    typedef unsigned char uint8_t
     
    typedef unsigned short int uint16_t
     
    typedef unsigned int uint32_t
     
    typedef unsigned __INT64 uint64_t
     
    typedef signed char int_least8_t
     
    typedef signed short int int_least16_t
     
    typedef signed int int_least32_t
     
    typedef signed __INT64 int_least64_t
     
    typedef unsigned char uint_least8_t
     
    typedef unsigned short int uint_least16_t
     
    typedef unsigned int uint_least32_t
     
    typedef unsigned __INT64 uint_least64_t
     
    typedef signed int int_fast8_t
     
    typedef signed int int_fast16_t
     
    typedef signed int int_fast32_t
     
    typedef signed __INT64 int_fast64_t
     
    typedef unsigned int uint_fast8_t
     
    typedef unsigned int uint_fast16_t
     
    typedef unsigned int uint_fast32_t
     
    typedef unsigned __INT64 uint_fast64_t
     
    typedef signed int intptr_t
     
    typedef unsigned int uintptr_t
     
    typedef signed __LONGLONG intmax_t
     
    typedef unsigned __LONGLONG uintmax_t
     
    -

    Macro Definition Documentation

    - -

    ◆ __ARMCLIB_VERSION

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    #define __ARMCLIB_VERSION   6190004
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    ◆ __INT64

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    #define __INT64   __int64
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    ◆ __INT64_C_SUFFIX__

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    #define __INT64_C_SUFFIX__   ll
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    ◆ __PASTE2

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    #define __PASTE2( x,
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    ◆ __PASTE

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    #define __PASTE( x,
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    ◆ __INT64_C

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    #define __INT64_C( x)   __ESCAPE__(__PASTE(x, __INT64_C_SUFFIX__))
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    ◆ __UINT64_C

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    #define __UINT64_C( x)   __ESCAPE__(__PASTE(x ## u, __INT64_C_SUFFIX__))
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    ◆ __LONGLONG

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    #define __LONGLONG   __int64
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    ◆ __STDINT_DECLS

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    #define __STDINT_DECLS
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    ◆ __CLIBNS

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    #define __CLIBNS
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    ◆ INT8_MIN

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    ◆ INT16_MIN

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    ◆ INT32_MIN

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    #define INT32_MIN   (~0x7fffffff) /* -2147483648 is unsigned */
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    ◆ INT64_MIN

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    #define INT64_MIN   __INT64_C(~0x7fffffffffffffff) /* -9223372036854775808 is unsigned */
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    ◆ INT8_MAX

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    #define INT64_MAX   __INT64_C(9223372036854775807)
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    ◆ UINT8_MAX

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    ◆ UINT16_MAX

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    #define UINT32_MAX   4294967295u
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    ◆ UINT64_MAX

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    #define UINT64_MAX   __UINT64_C(18446744073709551615)
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    ◆ INT_LEAST8_MIN

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    #define INT_LEAST8_MIN   -128
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    #define INT_LEAST16_MIN   -32768
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    #define INT_LEAST32_MIN   (~0x7fffffff)
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    ◆ INT_LEAST64_MIN

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    #define INT_LEAST64_MIN   __INT64_C(~0x7fffffffffffffff)
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    ◆ INT_LEAST8_MAX

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    #define INT_LEAST8_MAX   127
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    ◆ INT_LEAST64_MAX

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    #define INT_LEAST64_MAX   __INT64_C(9223372036854775807)
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    ◆ UINT_LEAST8_MAX

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    #define UINT_LEAST32_MAX   4294967295u
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    ◆ UINT_LEAST64_MAX

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    #define UINT_LEAST64_MAX   __UINT64_C(18446744073709551615)
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    ◆ INT_FAST8_MIN

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    #define INT_FAST8_MIN   (~0x7fffffff)
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    ◆ INT_FAST16_MIN

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    #define INT_FAST16_MIN   (~0x7fffffff)
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    ◆ INT_FAST64_MIN

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    #define INT_FAST64_MIN   __INT64_C(~0x7fffffffffffffff)
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    ◆ INT_FAST16_MAX

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    #define INT_FAST16_MAX   2147483647
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    ◆ INT_FAST32_MAX

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    #define INT_FAST32_MAX   2147483647
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    ◆ INT_FAST64_MAX

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    #define INT_FAST64_MAX   __INT64_C(9223372036854775807)
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    ◆ UINT_FAST8_MAX

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    #define UINT_FAST8_MAX   4294967295u
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    ◆ UINT_FAST16_MAX

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    ◆ UINT_FAST64_MAX

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    #define UINT_FAST64_MAX   __UINT64_C(18446744073709551615)
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    ◆ INTPTR_MIN

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    ◆ UINTPTR_MAX

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    ◆ INTMAX_MIN

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    ◆ INTMAX_MAX

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    #define INTMAX_MAX   __ESCAPE__(9223372036854775807ll)
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    ◆ UINTMAX_MAX

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    #define UINTMAX_MAX   __ESCAPE__(18446744073709551615ull)
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    ◆ PTRDIFF_MIN

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    ◆ SIG_ATOMIC_MIN

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    #define SIG_ATOMIC_MIN   (~0x7fffffff)
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    ◆ SIG_ATOMIC_MAX

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    ◆ SIZE_MAX

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    #define SIZE_MAX   UINT32_MAX
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    ◆ WCHAR_MIN

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    #define WCHAR_MIN   0
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    ◆ WCHAR_MAX

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    #define WCHAR_MAX   65535
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    ◆ WINT_MIN

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    ◆ WINT_MAX

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    ◆ INT8_C

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    Typedef Documentation

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    ◆ int8_t

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    ◆ int_least64_t

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    ◆ uint_least8_t

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    ◆ uint_least16_t

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    ◆ uint_least64_t

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    ◆ int_fast8_t

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    ◆ int_fast16_t

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    ◆ int_fast64_t

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    ◆ uint_fast32_t

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    ◆ uint_fast64_t

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    ◆ intptr_t

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    ◆ intmax_t

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    ◆ uintmax_t

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    typedef unsigned __LONGLONG uintmax_t
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    -Generated by doxygen 1.10.0 -
    - - diff --git a/DOCS/html/stdint_8h__dep__incl.map b/DOCS/html/stdint_8h__dep__incl.map deleted file mode 100644 index 3931721..0000000 --- a/DOCS/html/stdint_8h__dep__incl.map +++ /dev/null @@ -1,7 +0,0 @@ - - - - - - - diff --git a/DOCS/html/stdint_8h__dep__incl.md5 b/DOCS/html/stdint_8h__dep__incl.md5 deleted file mode 100644 index d69a3a3..0000000 --- a/DOCS/html/stdint_8h__dep__incl.md5 +++ /dev/null @@ -1 +0,0 @@ -3d2f9d0f5fc9aa4c6ac88973690af231 \ No newline at end of file diff --git a/DOCS/html/stdint_8h__dep__incl.png b/DOCS/html/stdint_8h__dep__incl.png deleted file mode 100644 index ce791ce175fa9c4f0f6761553888ccab081d67a3..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 6475 zcmb`M2T&7hyT=14pn!l1NbiUuB7*dyfFRNo5QWgC3WO2}hpJc*M4I$oLX{>$0wEIN zGZZBS5~)c*1QI|J6p$SH#dE$g=icw$xp(I7&g{Fp^Ult@@3Zg!`91$lzGZF3b6n&& z007`IzhPo~*scQrEI>~7!!rP`lk@P%?rC9W0yy}!mv`4@0RX}PbCYZKzZKI&LcFUAkt3a%Sg$ znPkT40aNop-*=BPl6fk_saPj3Dx<_x2i(&tx;B&5JnfPWd;Q?fs4MLt%c+A2eeE#X ze9(Lc7C^B$@@rs!Y?5{y=o)r@>K1%XKQucpwpiqPZXOOZfm^0#w=DpE{J)n21SA#^B3}i{B8o7`g@qf+guWy{&We^KwWDdGCNP zV`m)LgURO`E{Y|nv#;nT6QiHbJp8p88r;M<>I+@;Yarc z>EBh)jA30NXFA&a(rfDHK5xBR0}oN>XTj!(g`Ba5P4(wl9jgmoTh(ff`4)oJavXrS^Q-d*Pdv z4L!2zBw2xplWo!hmnsD=s2w*>L1@V8w`T^97|rR1F1{1B467?LOB7H;)k{bq@Op6K zYQ`A{%*Ez!3n@E4DfrX{tLk-^yeVAkbtg0b0>Wk6f%-MiUOuu;PQSI}l>3`P8#{)v zb9|(W>s z{@t5xXqR$Z;wx`kVWy)I!?}J_tl=)7@i#T-&-VFK;ck``mH#e(QONiT~gPv zRUR+h@i!w(7ZTG%LcauX{J;PdAOGe9cytB~f>?Nh>T-9+pq6h=NKsj%lQ?^N|Fi?mhdGg!2Xqaz7XJ`27uOtv z8Er|BGcCx%MLG{{7RTOP5sPv~>8PIC5-JQ6$yegWec%pS;T>tP3t4u4Tc%5kHV2|N zCuykfV>;bV)%h+D-Y?DE1O4fcwJ_3wt7H0=K!~*tbNY-3eVN(^^R@zMd@W$Pb>uJ#0M!qO$yV)8 zgBPuXhe7UIs?fQG1PEJ5+dq_r${kzgY}) z7wg^EV9^d~I~^8u|Fv3C_?*{L)x7770udufB~#3SV| zK0>x67i{u)bEd)u$QXvNiCvf z%PD@WT3q#?*O%P7Ro$d3X~{`7$)z#hy0`Lli;kR5$meM*Sb`NSUgYP;hDT2QZ4}Op z4$S^GPU8t${F%JS%Fk~V?oqmg{Wk8a2Zny>6h2ZAig{0+EwwS zNyQ@NZVkNe#Z6hpNE+&MpH%q?l$z-LH%Sala#v_i(<=NUcx$W)xUm%JR*-ANp~NBE zc8w}Id`G4wBiW}beCcEys_A<9QNFfo5Zx|Q(JmTN!z%n?;gVB8(IbP9w$vX#-YB~zx=iO;xnx9J*!2@Y2={rP9R zG^%%-c&yY%@`}zJDP++k@r@rq447q+i=yk)Kqx1_m6}Uoa|JKX5t z(T9mf!DB#0%Bg|PnDrJ1}onwyQkYvxQWuZK|hZroi|R$z@BA&d+^}h znNB#GVX-g^G`o>A{=~`cxU=bNH>Iu@+M{2{IrMzKuvH#$i!}`FdYGF(MVlrU#DDW_ zYZlvhqOs={kOn{sHw@aW;3t7kTs@u?B_-u~i~2i z+sq#M-n6~WOhi3h3|JMBoqJAMHlp~viXeAylb!#HI{TC7+)V!m!Yvl_yuWew(Q4qX ziG*jLXyK>pmB~8PY{#~jWSyF{gcC0Rgahfx$N4Gk+^K1<$d`rES*?!>CiJCnA+l{x z$p~AzwnK|l;u!e4c~t%Y+!yA#i3lrPvfT(#0;ahVAm98+6$C7{c?%GoJ}mpvNI7WG zv5s_rNiBi2sH{^PLnI%6xvP5_$!odxU2BOPQw{%};2&P))U3}Wrd4%csTIHSwWo<- zg^>?!N6p<^2?XgJs}3b-Yxw0k5p{XDBWw0O+}Pf`J%6XZm!-|xTndd z_C(@qf_uX0&dI+^x-oJR6*U+3zLl3D;We|r;4MK2K*hu^_)FJ=v9a<@`f9TNj0jvz z%5Fq?O=mHwxf~t9%QXsNf>RiX%?-;t6Uj;g5=^JbS(K_ zQbTxRL|aVYz>u!&4UqO zr+Fl5Y(8HcJ*O3MaS~qw?ygcc+RS_Rz0s;AQLxQ|t{HctkmXc8?)CN6B(bc+?ne(OgpEc6Eac! ze(A$k-rFHRzn&XZk-PXI?SF?2M?vt*ukLu@wkA|Hd6#}VZO+55g9>1TK3u?PGPsHQ z_=}?0%R~B&=t{*L62;U^MqxSSYEngf5Z{d_5Vn6I9d~P?IO%B*#r7i>pBL=+!Sn*p zc&@Ey8OXLQ!U*VYM{nD`(BYNZjOveMjA-O?OZx~h5+fPxeE!>Hb=3zob1P?3az6S? zYJRCS)sKFo01OzRV67v1hN+qS!;DMXGd8`m1Q(2$Eiz;C2090+ua>AHq0w$g>V8;& z${ucpy~^YDJ^!`g{-TxxZvSj;P-hU%oQA}~qMow&YH1=hv`HIbgr_we&Uq8cW?hMV zZ{1=xAVZG1Lde|5Bn^TFbD>Npw-LVqp(9@)+SkY@=1wJg71gL%eS$1$+yc2G*0-jh zZxzV!k1+G?zz39u)UC`Ya~v=`OTkyY6sJR`H zKb$U3g`&R}J-L|x0Ss{fHX<~tDPp%~t6DtwNtqwMy&H2@Y8l*fJK7nRrV zntBXgO(FEje*9{?7@ZbJUVk-5?vqU3L*R`(JHq2+X!mRlG+mN|nhr-N49M`&(iELg z&@iLxzikpv5>`L@c$Do>c|}a zw^D`ZeSEX^%r|eLVK&*e+f-#2Xfi{^dZsLLgTsZJb@?jBv><7^yZ~ni39DIGAGxbj za3uQ>%GO4iR5!Uwq0-Lp!?W?TO-!1QXweZ7fU2lhTeZrmk?x)a*F|EcJT10AHIb&Y?jP9b8FC z{PFQSMV{1sz_Gtgc$R>5L!EpaP(VK;+C%r%_b1^2@$N&cj;SJ7+KlSrYpME zsZ0HYpl0o`ExSi*n(J^}cPU7>n?U&28d#1H7 z^6hwVE|Y1;q?yyht#Wv0pd2%2tORUL5UdD4sjD3l1n_@Tata_ThGxANu*r}y6&*gA zXFkYe7Kimu6dFWT4 z=hI_XJfrNEV#llD;K0nW+fFs@+{r?+{;T$)$n1XW`BP^MUGoMdze^=A@EmF? z6{7eTGU>f%za#EWZhB&Ivx9}|I<9C8g^pi@`V4wqa94ov4tpe7$s)kjQ{YC|Yurt= z7q8YXrMvJ_`c}XT>cr~BSqHdScNKk%s38TN_#e2$_`63}I)=fPrKfjTCA-!uqryeR z>vIF}d+oCR!B~H@RIQNjT78}ulc7Jw2RwbjM03T|EL`g~B<2;QL0lKxs>wtdbC9%I zE*V8?BIQ*z?Z44ypq3%|V%hmIzwC^rzb?WERSQpBaAg@epjFRq!5mTwo0zz*Bw~5e zO1?Xt1TW{QF{S>)rWj5GdFH+dc-jDflSeX(6zFG2bdHUu+0NfSY%EJ-HB&#w6KUnbmok?doi@_6h=~C- zX%3&dlqhx0v*TFs!|k=?)C>CLKy0}FAdjxB1U z9ct7;cTOq|VU44^bM+BHnLwYW@YZ#wh_B8K2&qoUp)JD(*gc*8i#94y(%Of#5oG^& z+JGhe!-xAr_Hy3i#Zr1^i%DfP=ahwl^EPj9SN8cFu|{s8j)F-UJI-=NmyH&{>)9K} zmh=g0VLL;L{7wxAJD3TtnX=*j^3$zNEl&3sDpr)0V!tyCkb-h2(990%d#sp8rJH2_ z!t0yQ;0MkUU}=l$gGAF+{_O#Y9C3Gj_~(V(JS2~*AUsc$&_QiVB6N>xGwJDeEXq3v ztMuaw3sa>sOvkYm$#buhCVewnX2YI{X$jCwK2@#ElUuAnNdJh8sVeH6JSc>*dCUA^ zrgN~>DNRyb(Wa4FkF+5AmMxW&t|0CGEzE0yI(|Q)-t^%JL(;+?t>;7=@>ib`yP)oN zyy@}HXIf6k(SF*4FhYBLedxAD`hKS8Ax?Q_mot>(c{8+u#Tkyh9CEHx5 zE+*LTgmaP8o;P}b#ES)^KU3MbAajEubC;W0p>q8+QV@C_87ee+b7fE8Ac)-w!#ifDR~a~)9F^I_|1{owK^4cH&dng zir@_?p39s$S#Nc{fEUsyO1-RsRe@ZS$Af!#4XloF27LsA1}wzEYnCoUt!j5Ttm7H2 z!Ah0$S{)^}Oo{Vn3XaZ0N~eIr7M~h2YfMaF%Usfi$4sd=U#@KDO!f2NGIGyih0qE4 zN~&RIjUGklKCHOMtWF+_CJ+#b7Tyv%i58ry^1u0sh+*F99lX#J!IdW+gkX3o;+@ce zz+4yE=6eLe)|fn~y7QVkUmKtQg+NejC;57g(#CtH^EJF@Ft*>x zGc{o9*!ZX*-@5RXhkdu2E(0f6SV$~?k>Ou%Kc6#T=gSjbrzsYIqMRa?NF?S${_)4* c&(>pKGGVrIC4U+x|LcbNb!(GmBlpMu0fcRoN&o-= diff --git a/DOCS/html/stdint_8h_source.html b/DOCS/html/stdint_8h_source.html deleted file mode 100644 index 2c199ba..0000000 --- a/DOCS/html/stdint_8h_source.html +++ /dev/null @@ -1,433 +0,0 @@ - - - - - - - -STM MATLAB Simulator: F:/Work/Projects/MATLAB/matlab_stm_emulate/MCU_STM32F4xx_Matlab/Drivers/CMSIS/stdint.h Source File - - - - - - - - - - - -
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    stdint.h
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    1/* Copyright (C) ARM Ltd., 1999,2014 */
    -
    2/* All rights reserved */
    -
    3
    -
    4/*
    -
    5 * RCS $Revision$
    -
    6 * Checkin $Date$
    -
    7 * Revising $Author: agrant $
    -
    8 */
    -
    9
    -
    10#ifndef __stdint_h
    -
    11#define __stdint_h
    -
    12#define __ARMCLIB_VERSION 6190004
    -
    13
    -
    14 #ifdef __INT64_TYPE__
    -
    15 /* armclang predefines '__INT64_TYPE__' and '__INT64_C_SUFFIX__' */
    -
    16 #define __INT64 __INT64_TYPE__
    -
    17 #else
    -
    18 /* armcc has builtin '__int64' which can be used in --strict mode */
    -
    19 #define __INT64 __int64
    -
    20 #define __INT64_C_SUFFIX__ ll
    -
    21 #endif
    -
    22 #define __PASTE2(x, y) x ## y
    -
    23 #define __PASTE(x, y) __PASTE2(x, y)
    -
    24 #define __INT64_C(x) __ESCAPE__(__PASTE(x, __INT64_C_SUFFIX__))
    -
    25 #define __UINT64_C(x) __ESCAPE__(__PASTE(x ## u, __INT64_C_SUFFIX__))
    -
    26 #if defined(__clang__) || (defined(__ARMCC_VERSION) && !defined(__STRICT_ANSI__))
    -
    27 /* armclang and non-strict armcc allow 'long long' in system headers */
    -
    28 #define __LONGLONG long long
    -
    29 #else
    -
    30 /* strict armcc has '__int64' */
    -
    31 #define __LONGLONG __int64
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    32 #endif
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    33
    -
    34 #ifndef __STDINT_DECLS
    -
    35 #define __STDINT_DECLS
    -
    36
    -
    37 #undef __CLIBNS
    -
    38
    -
    39 #ifdef __cplusplus
    -
    40 namespace std {
    -
    41 #define __CLIBNS std::
    -
    42 extern "C" {
    -
    43 #else
    -
    44 #define __CLIBNS
    -
    45 #endif /* __cplusplus */
    -
    46
    -
    47
    -
    48/*
    -
    49 * 'signed' is redundant below, except for 'signed char' and if
    -
    50 * the typedef is used to declare a bitfield.
    -
    51 */
    -
    52
    -
    53 /* 7.18.1.1 */
    -
    54
    -
    55 /* exact-width signed integer types */
    -
    56typedef signed char int8_t;
    -
    57typedef signed short int int16_t;
    -
    58typedef signed int int32_t;
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    59typedef signed __INT64 int64_t;
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    60
    -
    61 /* exact-width unsigned integer types */
    -
    62typedef unsigned char uint8_t;
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    63typedef unsigned short int uint16_t;
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    64typedef unsigned int uint32_t;
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    65typedef unsigned __INT64 uint64_t;
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    66
    -
    67 /* 7.18.1.2 */
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    68
    -
    69 /* smallest type of at least n bits */
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    70 /* minimum-width signed integer types */
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    71typedef signed char int_least8_t;
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    72typedef signed short int int_least16_t;
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    73typedef signed int int_least32_t;
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    74typedef signed __INT64 int_least64_t;
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    75
    -
    76 /* minimum-width unsigned integer types */
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    77typedef unsigned char uint_least8_t;
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    78typedef unsigned short int uint_least16_t;
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    79typedef unsigned int uint_least32_t;
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    80typedef unsigned __INT64 uint_least64_t;
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    81
    -
    82 /* 7.18.1.3 */
    -
    83
    -
    84 /* fastest minimum-width signed integer types */
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    85typedef signed int int_fast8_t;
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    86typedef signed int int_fast16_t;
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    87typedef signed int int_fast32_t;
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    88typedef signed __INT64 int_fast64_t;
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    89
    -
    90 /* fastest minimum-width unsigned integer types */
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    91typedef unsigned int uint_fast8_t;
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    92typedef unsigned int uint_fast16_t;
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    93typedef unsigned int uint_fast32_t;
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    94typedef unsigned __INT64 uint_fast64_t;
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    95
    -
    96 /* 7.18.1.4 integer types capable of holding object pointers */
    -
    97#if __sizeof_ptr == 8
    -
    98typedef signed __INT64 intptr_t;
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    99typedef unsigned __INT64 uintptr_t;
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    100#else
    -
    101typedef signed int intptr_t;
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    102typedef unsigned int uintptr_t;
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    103#endif
    -
    104
    -
    105 /* 7.18.1.5 greatest-width integer types */
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    106typedef signed __LONGLONG intmax_t;
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    107typedef unsigned __LONGLONG uintmax_t;
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    108
    -
    109
    -
    110#if !defined(__cplusplus) || defined(__USE_C99_ALL) || 201103L <= __cplusplus || defined(__STDC_LIMIT_MACROS)
    -
    111
    -
    112 /* 7.18.2.1 */
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    113
    -
    114 /* minimum values of exact-width signed integer types */
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    115#define INT8_MIN -128
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    116#define INT16_MIN -32768
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    117#define INT32_MIN (~0x7fffffff) /* -2147483648 is unsigned */
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    118#define INT64_MIN __INT64_C(~0x7fffffffffffffff) /* -9223372036854775808 is unsigned */
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    119
    -
    120 /* maximum values of exact-width signed integer types */
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    121#define INT8_MAX 127
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    122#define INT16_MAX 32767
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    123#define INT32_MAX 2147483647
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    124#define INT64_MAX __INT64_C(9223372036854775807)
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    125
    -
    126 /* maximum values of exact-width unsigned integer types */
    -
    127#define UINT8_MAX 255
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    128#define UINT16_MAX 65535
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    129#define UINT32_MAX 4294967295u
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    130#define UINT64_MAX __UINT64_C(18446744073709551615)
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    131
    -
    132 /* 7.18.2.2 */
    -
    133
    -
    134 /* minimum values of minimum-width signed integer types */
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    135#define INT_LEAST8_MIN -128
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    136#define INT_LEAST16_MIN -32768
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    137#define INT_LEAST32_MIN (~0x7fffffff)
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    138#define INT_LEAST64_MIN __INT64_C(~0x7fffffffffffffff)
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    139
    -
    140 /* maximum values of minimum-width signed integer types */
    -
    141#define INT_LEAST8_MAX 127
    -
    142#define INT_LEAST16_MAX 32767
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    143#define INT_LEAST32_MAX 2147483647
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    144#define INT_LEAST64_MAX __INT64_C(9223372036854775807)
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    145
    -
    146 /* maximum values of minimum-width unsigned integer types */
    -
    147#define UINT_LEAST8_MAX 255
    -
    148#define UINT_LEAST16_MAX 65535
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    149#define UINT_LEAST32_MAX 4294967295u
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    150#define UINT_LEAST64_MAX __UINT64_C(18446744073709551615)
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    151
    -
    152 /* 7.18.2.3 */
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    153
    -
    154 /* minimum values of fastest minimum-width signed integer types */
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    155#define INT_FAST8_MIN (~0x7fffffff)
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    156#define INT_FAST16_MIN (~0x7fffffff)
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    157#define INT_FAST32_MIN (~0x7fffffff)
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    158#define INT_FAST64_MIN __INT64_C(~0x7fffffffffffffff)
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    159
    -
    160 /* maximum values of fastest minimum-width signed integer types */
    -
    161#define INT_FAST8_MAX 2147483647
    -
    162#define INT_FAST16_MAX 2147483647
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    163#define INT_FAST32_MAX 2147483647
    -
    164#define INT_FAST64_MAX __INT64_C(9223372036854775807)
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    165
    -
    166 /* maximum values of fastest minimum-width unsigned integer types */
    -
    167#define UINT_FAST8_MAX 4294967295u
    -
    168#define UINT_FAST16_MAX 4294967295u
    -
    169#define UINT_FAST32_MAX 4294967295u
    -
    170#define UINT_FAST64_MAX __UINT64_C(18446744073709551615)
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    171
    -
    172 /* 7.18.2.4 */
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    173
    -
    174 /* minimum value of pointer-holding signed integer type */
    -
    175#if __sizeof_ptr == 8
    -
    176#define INTPTR_MIN INT64_MIN
    -
    177#else
    -
    178#define INTPTR_MIN INT32_MIN
    -
    179#endif
    -
    180
    -
    181 /* maximum value of pointer-holding signed integer type */
    -
    182#if __sizeof_ptr == 8
    -
    183#define INTPTR_MAX INT64_MAX
    -
    184#else
    -
    185#define INTPTR_MAX INT32_MAX
    -
    186#endif
    -
    187
    -
    188 /* maximum value of pointer-holding unsigned integer type */
    -
    189#if __sizeof_ptr == 8
    -
    190#define UINTPTR_MAX UINT64_MAX
    -
    191#else
    -
    192#define UINTPTR_MAX UINT32_MAX
    -
    193#endif
    -
    194
    -
    195 /* 7.18.2.5 */
    -
    196
    -
    197 /* minimum value of greatest-width signed integer type */
    -
    198#define INTMAX_MIN __ESCAPE__(~0x7fffffffffffffffll)
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    199
    -
    200 /* maximum value of greatest-width signed integer type */
    -
    201#define INTMAX_MAX __ESCAPE__(9223372036854775807ll)
    -
    202
    -
    203 /* maximum value of greatest-width unsigned integer type */
    -
    204#define UINTMAX_MAX __ESCAPE__(18446744073709551615ull)
    -
    205
    -
    206 /* 7.18.3 */
    -
    207
    -
    208 /* limits of ptrdiff_t */
    -
    209#if __sizeof_ptr == 8
    -
    210#define PTRDIFF_MIN INT64_MIN
    -
    211#define PTRDIFF_MAX INT64_MAX
    -
    212#else
    -
    213#define PTRDIFF_MIN INT32_MIN
    -
    214#define PTRDIFF_MAX INT32_MAX
    -
    215#endif
    -
    216
    -
    217 /* limits of sig_atomic_t */
    -
    218#define SIG_ATOMIC_MIN (~0x7fffffff)
    -
    219#define SIG_ATOMIC_MAX 2147483647
    -
    220
    -
    221 /* limit of size_t */
    -
    222#if __sizeof_ptr == 8
    -
    223#define SIZE_MAX UINT64_MAX
    -
    224#else
    -
    225#define SIZE_MAX UINT32_MAX
    -
    226#endif
    -
    227
    -
    228 /* limits of wchar_t */
    -
    229 /* NB we have to undef and redef because they're defined in both
    -
    230 * stdint.h and wchar.h */
    -
    231#undef WCHAR_MIN
    -
    232#undef WCHAR_MAX
    -
    233
    -
    234#if defined(__WCHAR32) || (defined(__ARM_SIZEOF_WCHAR_T) && __ARM_SIZEOF_WCHAR_T == 4)
    -
    235 #define WCHAR_MIN 0
    -
    236 #define WCHAR_MAX 0xffffffffU
    -
    237#else
    -
    238 #define WCHAR_MIN 0
    -
    239 #define WCHAR_MAX 65535
    -
    240#endif
    -
    241
    -
    242 /* limits of wint_t */
    -
    243#define WINT_MIN (~0x7fffffff)
    -
    244#define WINT_MAX 2147483647
    -
    245
    -
    246#endif /* __STDC_LIMIT_MACROS */
    -
    247
    -
    248#if !defined(__cplusplus) || defined(__USE_C99_ALL) || 201103L <= __cplusplus || defined(__STDC_CONSTANT_MACROS)
    -
    249
    -
    250 /* 7.18.4.1 macros for minimum-width integer constants */
    -
    251#define INT8_C(x) (x)
    -
    252#define INT16_C(x) (x)
    -
    253#define INT32_C(x) (x)
    -
    254#define INT64_C(x) __INT64_C(x)
    -
    255
    -
    256#define UINT8_C(x) (x ## u)
    -
    257#define UINT16_C(x) (x ## u)
    -
    258#define UINT32_C(x) (x ## u)
    -
    259#define UINT64_C(x) __UINT64_C(x)
    -
    260
    -
    261 /* 7.18.4.2 macros for greatest-width integer constants */
    -
    262#define INTMAX_C(x) __ESCAPE__(x ## ll)
    -
    263#define UINTMAX_C(x) __ESCAPE__(x ## ull)
    -
    264
    -
    265#endif /* __STDC_CONSTANT_MACROS */
    -
    266
    -
    267 #ifdef __cplusplus
    -
    268 } /* extern "C" */
    -
    269 } /* namespace std */
    -
    270 #endif /* __cplusplus */
    -
    271 #endif /* __STDINT_DECLS */
    -
    272
    -
    273 #ifdef __cplusplus
    -
    274 #ifndef __STDINT_NO_EXPORTS
    -
    275 using ::std::int8_t;
    -
    276 using ::std::int16_t;
    -
    277 using ::std::int32_t;
    -
    278 using ::std::int64_t;
    -
    279 using ::std::uint8_t;
    -
    280 using ::std::uint16_t;
    -
    281 using ::std::uint32_t;
    -
    282 using ::std::uint64_t;
    -
    283 using ::std::int_least8_t;
    -
    284 using ::std::int_least16_t;
    -
    285 using ::std::int_least32_t;
    -
    286 using ::std::int_least64_t;
    -
    287 using ::std::uint_least8_t;
    -
    288 using ::std::uint_least16_t;
    -
    289 using ::std::uint_least32_t;
    -
    290 using ::std::uint_least64_t;
    -
    291 using ::std::int_fast8_t;
    -
    292 using ::std::int_fast16_t;
    -
    293 using ::std::int_fast32_t;
    -
    294 using ::std::int_fast64_t;
    -
    295 using ::std::uint_fast8_t;
    -
    296 using ::std::uint_fast16_t;
    -
    297 using ::std::uint_fast32_t;
    -
    298 using ::std::uint_fast64_t;
    -
    299 using ::std::intptr_t;
    -
    300 using ::std::uintptr_t;
    -
    301 using ::std::intmax_t;
    -
    302 using ::std::uintmax_t;
    -
    303 #endif
    -
    304 #endif /* __cplusplus */
    -
    305
    -
    306#undef __INT64
    -
    307#undef __LONGLONG
    -
    308
    -
    309#endif /* __stdint_h */
    -
    310
    -
    311/* end of stdint.h */
    -
    int64_t
    signed __INT64 int64_t
    Definition stdint.h:59
    -
    __INT64
    #define __INT64
    Definition stdint.h:19
    -
    uint_least16_t
    unsigned short int uint_least16_t
    Definition stdint.h:78
    -
    int_fast64_t
    signed __INT64 int_fast64_t
    Definition stdint.h:88
    -
    int_least32_t
    signed int int_least32_t
    Definition stdint.h:73
    -
    uint_fast16_t
    unsigned int uint_fast16_t
    Definition stdint.h:92
    -
    uint_fast64_t
    unsigned __INT64 uint_fast64_t
    Definition stdint.h:94
    -
    uintmax_t
    unsigned __LONGLONG uintmax_t
    Definition stdint.h:107
    -
    int_fast8_t
    signed int int_fast8_t
    Definition stdint.h:85
    -
    uint_least64_t
    unsigned __INT64 uint_least64_t
    Definition stdint.h:80
    -
    uint32_t
    unsigned int uint32_t
    Definition stdint.h:64
    -
    uint_fast32_t
    unsigned int uint_fast32_t
    Definition stdint.h:93
    -
    uintptr_t
    unsigned int uintptr_t
    Definition stdint.h:102
    -
    int_fast16_t
    signed int int_fast16_t
    Definition stdint.h:86
    -
    uint_least32_t
    unsigned int uint_least32_t
    Definition stdint.h:79
    -
    int16_t
    signed short int int16_t
    Definition stdint.h:57
    -
    int_least64_t
    signed __INT64 int_least64_t
    Definition stdint.h:74
    -
    intptr_t
    signed int intptr_t
    Definition stdint.h:101
    -
    uint_least8_t
    unsigned char uint_least8_t
    Definition stdint.h:77
    -
    int32_t
    signed int int32_t
    Definition stdint.h:58
    -
    uint8_t
    unsigned char uint8_t
    Definition stdint.h:62
    -
    int_least16_t
    signed short int int_least16_t
    Definition stdint.h:72
    -
    uint_fast8_t
    unsigned int uint_fast8_t
    Definition stdint.h:91
    -
    intmax_t
    signed __LONGLONG intmax_t
    Definition stdint.h:106
    -
    uint16_t
    unsigned short int uint16_t
    Definition stdint.h:63
    -
    int_least8_t
    signed char int_least8_t
    Definition stdint.h:71
    -
    int_fast32_t
    signed int int_fast32_t
    Definition stdint.h:87
    -
    uint64_t
    unsigned __INT64 uint64_t
    Definition stdint.h:65
    -
    int8_t
    signed char int8_t
    Definition stdint.h:56
    -
    __LONGLONG
    #define __LONGLONG
    Definition stdint.h:31
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    -
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    #include "stdint.h"
    -#include "arm_defines.h"
    -#include "core_cm4_matlab.h"
    -#include "system_stm32f4xx.h"
    -
    - + Include dependency graph for stm32f407xx_matlab.h:
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    -Data Structures

    struct  ADC_TypeDef
     Analog to Digital Converter
    - More...
     
    struct  ADC_Common_TypeDef
     
    struct  CAN_TxMailBox_TypeDef
     Controller Area Network TxMailBox. More...
     
    struct  CAN_FIFOMailBox_TypeDef
     Controller Area Network FIFOMailBox. More...
     
    struct  CAN_FilterRegister_TypeDef
     Controller Area Network FilterRegister. More...
     
    struct  CAN_TypeDef
     Controller Area Network. More...
     
    struct  CRC_TypeDef
     CRC calculation unit. More...
     
    struct  DAC_TypeDef
     Digital to Analog Converter. More...
     
    struct  DBGMCU_TypeDef
     Debug MCU. More...
     
    struct  DCMI_TypeDef
     DCMI. More...
     
    struct  DMA_Stream_TypeDef
     DMA Controller. More...
     
    struct  DMA_TypeDef
     
    struct  ETH_TypeDef
     Ethernet MAC. More...
     
    struct  EXTI_TypeDef
     External Interrupt/Event Controller. More...
     
    struct  FLASH_TypeDef
     FLASH Registers. More...
     
    struct  FSMC_Bank1_TypeDef
     Flexible Static Memory Controller. More...
     
    struct  FSMC_Bank1E_TypeDef
     Flexible Static Memory Controller Bank1E. More...
     
    struct  FSMC_Bank2_3_TypeDef
     Flexible Static Memory Controller Bank2. More...
     
    struct  FSMC_Bank4_TypeDef
     Flexible Static Memory Controller Bank4. More...
     
    struct  GPIO_TypeDef
     General Purpose I/O. More...
     
    struct  SYSCFG_TypeDef
     System configuration controller. More...
     
    struct  I2C_TypeDef
     Inter-integrated Circuit Interface. More...
     
    struct  IWDG_TypeDef
     Independent WATCHDOG. More...
     
    struct  PWR_TypeDef
     Power Control. More...
     
    struct  RCC_TypeDef
     Reset and Clock Control. More...
     
    struct  RTC_TypeDef
     Real-Time Clock. More...
     
    struct  SDIO_TypeDef
     SD host Interface. More...
     
    struct  SPI_TypeDef
     Serial Peripheral Interface. More...
     
    struct  TIM_TypeDef
     TIM. More...
     
    struct  USART_TypeDef
     Universal Synchronous Asynchronous Receiver Transmitter. More...
     
    struct  WWDG_TypeDef
     Window WATCHDOG. More...
     
    struct  RNG_TypeDef
     RNG. More...
     
    struct  USB_OTG_GlobalTypeDef
     USB_OTG_Core_Registers. More...
     
    struct  USB_OTG_DeviceTypeDef
     USB_OTG_device_Registers. More...
     
    struct  USB_OTG_INEndpointTypeDef
     USB_OTG_IN_Endpoint-Specific_Register. More...
     
    struct  USB_OTG_OUTEndpointTypeDef
     USB_OTG_OUT_Endpoint-Specific_Registers. More...
     
    struct  USB_OTG_HostTypeDef
     USB_OTG_Host_Mode_Register_Structures. More...
     
    struct  USB_OTG_HostChannelTypeDef
     USB_OTG_Host_Channel_Specific_Registers. More...
     
    struct  _memory
     
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    -Macros

    #define __CM4_REV   0x0001U
     Configuration of the Cortex-M4 Processor and Core Peripherals.
     
    #define __MPU_PRESENT   1U
     
    #define __NVIC_PRIO_BITS   4U
     
    #define __Vendor_SysTickConfig   0U
     
    #define __FPU_PRESENT   1U
     
    #define HASH_RNG_IRQn   RNG_IRQn
     
    #define FLASH_BASE_SHIFT   0x08000000UL
     
    #define FLASH_END_SHIFT   0x080FFFFFUL
     
    #define CCMDATARAM_BASE_SHIFT   0x10000000UL
     
    #define CCMDATARAM_END_SHIFT   0x1000FFFFUL
     
    #define FLASH_OTP_BASE_SHIFT   0x1FFF7800UL
     
    #define FLASH_OTP_END_SHIFT   0x1FFF7A0FUL
     
    #define SRAM1_BASE_SHIFT   0x20000000UL
     
    #define SRAM2_BASE_SHIFT   0x2001C000UL
     
    #define SRAM1_BB_BASE_SHIFT   0x22000000UL
     
    #define SRAM2_BB_BASE_SHIFT   0x22380000UL
     
    #define PERIPH_BASE_SHIFT   0x40000000UL
     
    #define BKPSRAM_BASE_SHIFT   0x40024000UL
     
    #define PERIPH_BB_BASE_SHIFT   0x42000000UL
     
    #define BKPSRAM_BB_BASE_SHIFT   0x42480000UL
     
    #define FSMC_R_BASE_SHIFT   0xA0000000UL
     
    #define MCU_MEM_END   0xA0000FFFUL
     
    #define CCMDATARAM_SIZE   0x10000UL /* (64 KB) */
     
    #define SRAM1_SIZE   0x1C000UL /* (112 KB) */
     
    #define SRAM2_SIZE   0x4000UL /* (16 KB) */
     
    #define BKPSRAM_SIZE   0x1000UL /* (4 KB) */
     
    #define FLASH_SIZE   (CCMDATARAM_BASE_SHIFT - FLASH_BASE_SHIFT)
     
    #define FLASH_OTP_SIZE   (SRAM1_BASE_SHIFT - FLASH_OTP_BASE_SHIFT)
     
    #define SRAM1_BB_SIZE   (SRAM2_BB_BASE_SHIFT - SRAM1_BB_BASE_SHIFT)
     
    #define SRAM2_BB_SIZE   (PERIPH_BASE_SHIFT - SRAM2_BB_BASE_SHIFT)
     
    #define PERIPH_SIZE   (BKPSRAM_BASE_SHIFT - PERIPH_BASE_SHIFT)
     
    #define PERIPH_BB_SIZE   (BKPSRAM_BB_BASE_SHIFT - PERIPH_BB_BASE_SHIFT)
     
    #define FSMC_R_SIZE   (MCU_MEM_END - FSMC_R_BASE_SHIFT)
     
    #define FLASH_BASE   (MCU_MEM.CCMDATARAM_BASE)
     
    #define CCMDATARAM_BASE   (MCU_MEM.CCMDATARAM_BASE)
     
    #define SRAM1_BASE   (MCU_MEM.SRAM1_BASE)
     
    #define SRAM2_BASE   (MCU_MEM.SRAM2_BASE)
     
    #define PERIPH_BASE   (MCU_MEM.PERIPH_BASE)
     
    #define BKPSRAM_BASE   (MCU_MEM.BKPSRAM_BASE)
     
    #define FSMC_R_BASE   (MCU_MEM.FSMC_R_BASE)
     
    #define SRAM1_BB_BASE   (MCU_MEM.SRAM1_BB_BASE)
     
    #define SRAM2_BB_BASE   (MCU_MEM.SRAM2_BB_BASE)
     
    #define PERIPH_BB_BASE   (MCU_MEM.PERIPH_BB_BASE)
     
    #define BKPSRAM_BB_BASE   (MCU_MEM.BKPSRAM_BB_BASE)
     
    #define FLASH_END   (MCU_MEM.FLASH_END)
     
    #define FLASH_OTP_BASE   (MCU_MEM.FLASH_OTP_BASE)
     
    #define FLASH_OTP_END   (MCU_MEM.FLASH_OTP_END)
     
    #define CCMDATARAM_END   (MCU_MEM.CCMDATARAM_END)
     
    #define SRAM_BASE   SRAM1_BASE
     
    #define SRAM_BB_BASE   SRAM1_BB_BASE
     
    #define APB1PERIPH_BASE   PERIPH_BASE
     
    #define APB2PERIPH_BASE   (PERIPH_BASE + 0x00010000UL)
     
    #define AHB1PERIPH_BASE   (PERIPH_BASE + 0x00020000UL)
     
    #define AHB2PERIPH_BASE   (PERIPH_BASE + 0x10000000UL)
     
    #define TIM2_BASE   (APB1PERIPH_BASE + 0x0000UL)
     
    #define TIM3_BASE   (APB1PERIPH_BASE + 0x0400UL)
     
    #define TIM4_BASE   (APB1PERIPH_BASE + 0x0800UL)
     
    #define TIM5_BASE   (APB1PERIPH_BASE + 0x0C00UL)
     
    #define TIM6_BASE   (APB1PERIPH_BASE + 0x1000UL)
     
    #define TIM7_BASE   (APB1PERIPH_BASE + 0x1400UL)
     
    #define TIM12_BASE   (APB1PERIPH_BASE + 0x1800UL)
     
    #define TIM13_BASE   (APB1PERIPH_BASE + 0x1C00UL)
     
    #define TIM14_BASE   (APB1PERIPH_BASE + 0x2000UL)
     
    #define RTC_BASE   (APB1PERIPH_BASE + 0x2800UL)
     
    #define WWDG_BASE   (APB1PERIPH_BASE + 0x2C00UL)
     
    #define IWDG_BASE   (APB1PERIPH_BASE + 0x3000UL)
     
    #define I2S2ext_BASE   (APB1PERIPH_BASE + 0x3400UL)
     
    #define SPI2_BASE   (APB1PERIPH_BASE + 0x3800UL)
     
    #define SPI3_BASE   (APB1PERIPH_BASE + 0x3C00UL)
     
    #define I2S3ext_BASE   (APB1PERIPH_BASE + 0x4000UL)
     
    #define USART2_BASE   (APB1PERIPH_BASE + 0x4400UL)
     
    #define USART3_BASE   (APB1PERIPH_BASE + 0x4800UL)
     
    #define UART4_BASE   (APB1PERIPH_BASE + 0x4C00UL)
     
    #define UART5_BASE   (APB1PERIPH_BASE + 0x5000UL)
     
    #define I2C1_BASE   (APB1PERIPH_BASE + 0x5400UL)
     
    #define I2C2_BASE   (APB1PERIPH_BASE + 0x5800UL)
     
    #define I2C3_BASE   (APB1PERIPH_BASE + 0x5C00UL)
     
    #define CAN1_BASE   (APB1PERIPH_BASE + 0x6400UL)
     
    #define CAN2_BASE   (APB1PERIPH_BASE + 0x6800UL)
     
    #define PWR_BASE   (APB1PERIPH_BASE + 0x7000UL)
     
    #define DAC_BASE   (APB1PERIPH_BASE + 0x7400UL)
     
    #define TIM1_BASE   (APB2PERIPH_BASE + 0x0000UL)
     
    #define TIM8_BASE   (APB2PERIPH_BASE + 0x0400UL)
     
    #define USART1_BASE   (APB2PERIPH_BASE + 0x1000UL)
     
    #define USART6_BASE   (APB2PERIPH_BASE + 0x1400UL)
     
    #define ADC1_BASE   (APB2PERIPH_BASE + 0x2000UL)
     
    #define ADC2_BASE   (APB2PERIPH_BASE + 0x2100UL)
     
    #define ADC3_BASE   (APB2PERIPH_BASE + 0x2200UL)
     
    #define ADC123_COMMON_BASE   (APB2PERIPH_BASE + 0x2300UL)
     
    #define ADC_BASE   ADC123_COMMON_BASE
     
    #define SDIO_BASE   (APB2PERIPH_BASE + 0x2C00UL)
     
    #define SPI1_BASE   (APB2PERIPH_BASE + 0x3000UL)
     
    #define SYSCFG_BASE   (APB2PERIPH_BASE + 0x3800UL)
     
    #define EXTI_BASE   (APB2PERIPH_BASE + 0x3C00UL)
     
    #define TIM9_BASE   (APB2PERIPH_BASE + 0x4000UL)
     
    #define TIM10_BASE   (APB2PERIPH_BASE + 0x4400UL)
     
    #define TIM11_BASE   (APB2PERIPH_BASE + 0x4800UL)
     
    #define GPIOA_BASE   (AHB1PERIPH_BASE + 0x0000UL)
     
    #define GPIOB_BASE   (AHB1PERIPH_BASE + 0x0400UL)
     
    #define GPIOC_BASE   (AHB1PERIPH_BASE + 0x0800UL)
     
    #define GPIOD_BASE   (AHB1PERIPH_BASE + 0x0C00UL)
     
    #define GPIOE_BASE   (AHB1PERIPH_BASE + 0x1000UL)
     
    #define GPIOF_BASE   (AHB1PERIPH_BASE + 0x1400UL)
     
    #define GPIOG_BASE   (AHB1PERIPH_BASE + 0x1800UL)
     
    #define GPIOH_BASE   (AHB1PERIPH_BASE + 0x1C00UL)
     
    #define GPIOI_BASE   (AHB1PERIPH_BASE + 0x2000UL)
     
    #define CRC_BASE   (AHB1PERIPH_BASE + 0x3000UL)
     
    #define RCC_BASE   (AHB1PERIPH_BASE + 0x3800UL)
     
    #define FLASH_R_BASE   (AHB1PERIPH_BASE + 0x3C00UL)
     
    #define DMA1_BASE   (AHB1PERIPH_BASE + 0x6000UL)
     
    #define DMA1_Stream0_BASE   (DMA1_BASE + 0x010UL)
     
    #define DMA1_Stream1_BASE   (DMA1_BASE + 0x028UL)
     
    #define DMA1_Stream2_BASE   (DMA1_BASE + 0x040UL)
     
    #define DMA1_Stream3_BASE   (DMA1_BASE + 0x058UL)
     
    #define DMA1_Stream4_BASE   (DMA1_BASE + 0x070UL)
     
    #define DMA1_Stream5_BASE   (DMA1_BASE + 0x088UL)
     
    #define DMA1_Stream6_BASE   (DMA1_BASE + 0x0A0UL)
     
    #define DMA1_Stream7_BASE   (DMA1_BASE + 0x0B8UL)
     
    #define DMA2_BASE   (AHB1PERIPH_BASE + 0x6400UL)
     
    #define DMA2_Stream0_BASE   (DMA2_BASE + 0x010UL)
     
    #define DMA2_Stream1_BASE   (DMA2_BASE + 0x028UL)
     
    #define DMA2_Stream2_BASE   (DMA2_BASE + 0x040UL)
     
    #define DMA2_Stream3_BASE   (DMA2_BASE + 0x058UL)
     
    #define DMA2_Stream4_BASE   (DMA2_BASE + 0x070UL)
     
    #define DMA2_Stream5_BASE   (DMA2_BASE + 0x088UL)
     
    #define DMA2_Stream6_BASE   (DMA2_BASE + 0x0A0UL)
     
    #define DMA2_Stream7_BASE   (DMA2_BASE + 0x0B8UL)
     
    #define ETH_BASE   (AHB1PERIPH_BASE + 0x8000UL)
     
    #define ETH_MAC_BASE   (ETH_BASE)
     
    #define ETH_MMC_BASE   (ETH_BASE + 0x0100UL)
     
    #define ETH_PTP_BASE   (ETH_BASE + 0x0700UL)
     
    #define ETH_DMA_BASE   (ETH_BASE + 0x1000UL)
     
    #define DCMI_BASE   (AHB2PERIPH_BASE + 0x50000UL)
     
    #define RNG_BASE   (AHB2PERIPH_BASE + 0x60800UL)
     
    #define FSMC_Bank1_R_BASE   (FSMC_R_BASE + 0x0000UL)
     
    #define FSMC_Bank1E_R_BASE   (FSMC_R_BASE + 0x0104UL)
     
    #define FSMC_Bank2_3_R_BASE   (FSMC_R_BASE + 0x0060UL)
     
    #define FSMC_Bank4_R_BASE   (FSMC_R_BASE + 0x00A0UL)
     
    #define DBGMCU_BASE   (&DEBUG_MCU)
     
    #define USB_OTG_HS_PERIPH_BASE   0x40040000UL
     
    #define USB_OTG_FS_PERIPH_BASE   0x50000000UL
     
    #define USB_OTG_GLOBAL_BASE   0x000UL
     
    #define USB_OTG_DEVICE_BASE   0x800UL
     
    #define USB_OTG_IN_ENDPOINT_BASE   0x900UL
     
    #define USB_OTG_OUT_ENDPOINT_BASE   0xB00UL
     
    #define USB_OTG_EP_REG_SIZE   0x20UL
     
    #define USB_OTG_HOST_BASE   0x400UL
     
    #define USB_OTG_HOST_PORT_BASE   0x440UL
     
    #define USB_OTG_HOST_CHANNEL_BASE   0x500UL
     
    #define USB_OTG_HOST_CHANNEL_SIZE   0x20UL
     
    #define USB_OTG_PCGCCTL_BASE   0xE00UL
     
    #define USB_OTG_FIFO_BASE   0x1000UL
     
    #define USB_OTG_FIFO_SIZE   0x1000UL
     
    #define UID_BASE   0x1FFF7A10UL
     
    #define FLASHSIZE_BASE   0x1FFF7A22UL
     
    #define PACKAGE_BASE   0x1FFF7BF0UL
     
    #define TIM2   ((TIM_TypeDef *) TIM2_BASE)
     
    #define TIM3   ((TIM_TypeDef *) TIM3_BASE)
     
    #define TIM4   ((TIM_TypeDef *) TIM4_BASE)
     
    #define TIM5   ((TIM_TypeDef *) TIM5_BASE)
     
    #define TIM6   ((TIM_TypeDef *) TIM6_BASE)
     
    #define TIM7   ((TIM_TypeDef *) TIM7_BASE)
     
    #define TIM12   ((TIM_TypeDef *) TIM12_BASE)
     
    #define TIM13   ((TIM_TypeDef *) TIM13_BASE)
     
    #define TIM14   ((TIM_TypeDef *) TIM14_BASE)
     
    #define RTC   ((RTC_TypeDef *) RTC_BASE)
     
    #define WWDG   ((WWDG_TypeDef *) WWDG_BASE)
     
    #define IWDG   ((IWDG_TypeDef *) IWDG_BASE)
     
    #define I2S2ext   ((SPI_TypeDef *) I2S2ext_BASE)
     
    #define SPI2   ((SPI_TypeDef *) SPI2_BASE)
     
    #define SPI3   ((SPI_TypeDef *) SPI3_BASE)
     
    #define I2S3ext   ((SPI_TypeDef *) I2S3ext_BASE)
     
    #define USART2   ((USART_TypeDef *) USART2_BASE)
     
    #define USART3   ((USART_TypeDef *) USART3_BASE)
     
    #define UART4   ((USART_TypeDef *) UART4_BASE)
     
    #define UART5   ((USART_TypeDef *) UART5_BASE)
     
    #define I2C1   ((I2C_TypeDef *) I2C1_BASE)
     
    #define I2C2   ((I2C_TypeDef *) I2C2_BASE)
     
    #define I2C3   ((I2C_TypeDef *) I2C3_BASE)
     
    #define CAN1   ((CAN_TypeDef *) CAN1_BASE)
     
    #define CAN2   ((CAN_TypeDef *) CAN2_BASE)
     
    #define PWR   ((PWR_TypeDef *) PWR_BASE)
     
    #define DAC1   ((DAC_TypeDef *) DAC_BASE)
     
    #define DAC   ((DAC_TypeDef *) DAC_BASE) /* Kept for legacy purpose */
     
    #define TIM1   ((TIM_TypeDef *) TIM1_BASE)
     
    #define TIM8   ((TIM_TypeDef *) TIM8_BASE)
     
    #define USART1   ((USART_TypeDef *) USART1_BASE)
     
    #define USART6   ((USART_TypeDef *) USART6_BASE)
     
    #define ADC1   ((ADC_TypeDef *) ADC1_BASE)
     
    #define ADC2   ((ADC_TypeDef *) ADC2_BASE)
     
    #define ADC3   ((ADC_TypeDef *) ADC3_BASE)
     
    #define ADC123_COMMON   ((ADC_Common_TypeDef *) ADC123_COMMON_BASE)
     
    #define ADC   ADC123_COMMON
     
    #define SDIO   ((SDIO_TypeDef *) SDIO_BASE)
     
    #define SPI1   ((SPI_TypeDef *) SPI1_BASE)
     
    #define SYSCFG   ((SYSCFG_TypeDef *) SYSCFG_BASE)
     
    #define EXTI   ((EXTI_TypeDef *) EXTI_BASE)
     
    #define TIM9   ((TIM_TypeDef *) TIM9_BASE)
     
    #define TIM10   ((TIM_TypeDef *) TIM10_BASE)
     
    #define TIM11   ((TIM_TypeDef *) TIM11_BASE)
     
    #define GPIOA   ((GPIO_TypeDef *) GPIOA_BASE)
     
    #define GPIOB   ((GPIO_TypeDef *) GPIOB_BASE)
     
    #define GPIOC   ((GPIO_TypeDef *) GPIOC_BASE)
     
    #define GPIOD   ((GPIO_TypeDef *) GPIOD_BASE)
     
    #define GPIOE   ((GPIO_TypeDef *) GPIOE_BASE)
     
    #define GPIOF   ((GPIO_TypeDef *) GPIOF_BASE)
     
    #define GPIOG   ((GPIO_TypeDef *) GPIOG_BASE)
     
    #define GPIOH   ((GPIO_TypeDef *) GPIOH_BASE)
     
    #define GPIOI   ((GPIO_TypeDef *) GPIOI_BASE)
     
    #define CRC   ((CRC_TypeDef *) CRC_BASE)
     
    #define RCC   ((RCC_TypeDef *) RCC_BASE)
     
    #define FLASH   ((FLASH_TypeDef *) FLASH_R_BASE)
     
    #define DMA1   ((DMA_TypeDef *) DMA1_BASE)
     
    #define DMA1_Stream0   ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
     
    #define DMA1_Stream1   ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
     
    #define DMA1_Stream2   ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
     
    #define DMA1_Stream3   ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
     
    #define DMA1_Stream4   ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
     
    #define DMA1_Stream5   ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
     
    #define DMA1_Stream6   ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
     
    #define DMA1_Stream7   ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
     
    #define DMA2   ((DMA_TypeDef *) DMA2_BASE)
     
    #define DMA2_Stream0   ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
     
    #define DMA2_Stream1   ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
     
    #define DMA2_Stream2   ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
     
    #define DMA2_Stream3   ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
     
    #define DMA2_Stream4   ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
     
    #define DMA2_Stream5   ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
     
    #define DMA2_Stream6   ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
     
    #define DMA2_Stream7   ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
     
    #define ETH   ((ETH_TypeDef *) ETH_BASE)
     
    #define DCMI   ((DCMI_TypeDef *) DCMI_BASE)
     
    #define RNG   ((RNG_TypeDef *) RNG_BASE)
     
    #define FSMC_Bank1   ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE)
     
    #define FSMC_Bank1E   ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE)
     
    #define FSMC_Bank2_3   ((FSMC_Bank2_3_TypeDef *) FSMC_Bank2_3_R_BASE)
     
    #define FSMC_Bank4   ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE)
     
    #define DBGMCU   ((DBGMCU_TypeDef *) DBGMCU_BASE)
     
    #define USB_OTG_FS   ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
     
    #define USB_OTG_HS   ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE)
     
    #define LSI_STARTUP_TIME   40U
     
    #define ADC_MULTIMODE_SUPPORT
     
    #define ADC_SR_AWD_Pos   (0U)
     
    #define ADC_SR_AWD_Msk   (0x1UL << ADC_SR_AWD_Pos)
     
    #define ADC_SR_AWD   ADC_SR_AWD_Msk
     
    #define ADC_SR_EOC_Pos   (1U)
     
    #define ADC_SR_EOC_Msk   (0x1UL << ADC_SR_EOC_Pos)
     
    #define ADC_SR_EOC   ADC_SR_EOC_Msk
     
    #define ADC_SR_JEOC_Pos   (2U)
     
    #define ADC_SR_JEOC_Msk   (0x1UL << ADC_SR_JEOC_Pos)
     
    #define ADC_SR_JEOC   ADC_SR_JEOC_Msk
     
    #define ADC_SR_JSTRT_Pos   (3U)
     
    #define ADC_SR_JSTRT_Msk   (0x1UL << ADC_SR_JSTRT_Pos)
     
    #define ADC_SR_JSTRT   ADC_SR_JSTRT_Msk
     
    #define ADC_SR_STRT_Pos   (4U)
     
    #define ADC_SR_STRT_Msk   (0x1UL << ADC_SR_STRT_Pos)
     
    #define ADC_SR_STRT   ADC_SR_STRT_Msk
     
    #define ADC_SR_OVR_Pos   (5U)
     
    #define ADC_SR_OVR_Msk   (0x1UL << ADC_SR_OVR_Pos)
     
    #define ADC_SR_OVR   ADC_SR_OVR_Msk
     
    #define ADC_CR1_AWDCH_Pos   (0U)
     
    #define ADC_CR1_AWDCH_Msk   (0x1FUL << ADC_CR1_AWDCH_Pos)
     
    #define ADC_CR1_AWDCH   ADC_CR1_AWDCH_Msk
     
    #define ADC_CR1_AWDCH_0   (0x01UL << ADC_CR1_AWDCH_Pos)
     
    #define ADC_CR1_AWDCH_1   (0x02UL << ADC_CR1_AWDCH_Pos)
     
    #define ADC_CR1_AWDCH_2   (0x04UL << ADC_CR1_AWDCH_Pos)
     
    #define ADC_CR1_AWDCH_3   (0x08UL << ADC_CR1_AWDCH_Pos)
     
    #define ADC_CR1_AWDCH_4   (0x10UL << ADC_CR1_AWDCH_Pos)
     
    #define ADC_CR1_EOCIE_Pos   (5U)
     
    #define ADC_CR1_EOCIE_Msk   (0x1UL << ADC_CR1_EOCIE_Pos)
     
    #define ADC_CR1_EOCIE   ADC_CR1_EOCIE_Msk
     
    #define ADC_CR1_AWDIE_Pos   (6U)
     
    #define ADC_CR1_AWDIE_Msk   (0x1UL << ADC_CR1_AWDIE_Pos)
     
    #define ADC_CR1_AWDIE   ADC_CR1_AWDIE_Msk
     
    #define ADC_CR1_JEOCIE_Pos   (7U)
     
    #define ADC_CR1_JEOCIE_Msk   (0x1UL << ADC_CR1_JEOCIE_Pos)
     
    #define ADC_CR1_JEOCIE   ADC_CR1_JEOCIE_Msk
     
    #define ADC_CR1_SCAN_Pos   (8U)
     
    #define ADC_CR1_SCAN_Msk   (0x1UL << ADC_CR1_SCAN_Pos)
     
    #define ADC_CR1_SCAN   ADC_CR1_SCAN_Msk
     
    #define ADC_CR1_AWDSGL_Pos   (9U)
     
    #define ADC_CR1_AWDSGL_Msk   (0x1UL << ADC_CR1_AWDSGL_Pos)
     
    #define ADC_CR1_AWDSGL   ADC_CR1_AWDSGL_Msk
     
    #define ADC_CR1_JAUTO_Pos   (10U)
     
    #define ADC_CR1_JAUTO_Msk   (0x1UL << ADC_CR1_JAUTO_Pos)
     
    #define ADC_CR1_JAUTO   ADC_CR1_JAUTO_Msk
     
    #define ADC_CR1_DISCEN_Pos   (11U)
     
    #define ADC_CR1_DISCEN_Msk   (0x1UL << ADC_CR1_DISCEN_Pos)
     
    #define ADC_CR1_DISCEN   ADC_CR1_DISCEN_Msk
     
    #define ADC_CR1_JDISCEN_Pos   (12U)
     
    #define ADC_CR1_JDISCEN_Msk   (0x1UL << ADC_CR1_JDISCEN_Pos)
     
    #define ADC_CR1_JDISCEN   ADC_CR1_JDISCEN_Msk
     
    #define ADC_CR1_DISCNUM_Pos   (13U)
     
    #define ADC_CR1_DISCNUM_Msk   (0x7UL << ADC_CR1_DISCNUM_Pos)
     
    #define ADC_CR1_DISCNUM   ADC_CR1_DISCNUM_Msk
     
    #define ADC_CR1_DISCNUM_0   (0x1UL << ADC_CR1_DISCNUM_Pos)
     
    #define ADC_CR1_DISCNUM_1   (0x2UL << ADC_CR1_DISCNUM_Pos)
     
    #define ADC_CR1_DISCNUM_2   (0x4UL << ADC_CR1_DISCNUM_Pos)
     
    #define ADC_CR1_JAWDEN_Pos   (22U)
     
    #define ADC_CR1_JAWDEN_Msk   (0x1UL << ADC_CR1_JAWDEN_Pos)
     
    #define ADC_CR1_JAWDEN   ADC_CR1_JAWDEN_Msk
     
    #define ADC_CR1_AWDEN_Pos   (23U)
     
    #define ADC_CR1_AWDEN_Msk   (0x1UL << ADC_CR1_AWDEN_Pos)
     
    #define ADC_CR1_AWDEN   ADC_CR1_AWDEN_Msk
     
    #define ADC_CR1_RES_Pos   (24U)
     
    #define ADC_CR1_RES_Msk   (0x3UL << ADC_CR1_RES_Pos)
     
    #define ADC_CR1_RES   ADC_CR1_RES_Msk
     
    #define ADC_CR1_RES_0   (0x1UL << ADC_CR1_RES_Pos)
     
    #define ADC_CR1_RES_1   (0x2UL << ADC_CR1_RES_Pos)
     
    #define ADC_CR1_OVRIE_Pos   (26U)
     
    #define ADC_CR1_OVRIE_Msk   (0x1UL << ADC_CR1_OVRIE_Pos)
     
    #define ADC_CR1_OVRIE   ADC_CR1_OVRIE_Msk
     
    #define ADC_CR2_ADON_Pos   (0U)
     
    #define ADC_CR2_ADON_Msk   (0x1UL << ADC_CR2_ADON_Pos)
     
    #define ADC_CR2_ADON   ADC_CR2_ADON_Msk
     
    #define ADC_CR2_CONT_Pos   (1U)
     
    #define ADC_CR2_CONT_Msk   (0x1UL << ADC_CR2_CONT_Pos)
     
    #define ADC_CR2_CONT   ADC_CR2_CONT_Msk
     
    #define ADC_CR2_DMA_Pos   (8U)
     
    #define ADC_CR2_DMA_Msk   (0x1UL << ADC_CR2_DMA_Pos)
     
    #define ADC_CR2_DMA   ADC_CR2_DMA_Msk
     
    #define ADC_CR2_DDS_Pos   (9U)
     
    #define ADC_CR2_DDS_Msk   (0x1UL << ADC_CR2_DDS_Pos)
     
    #define ADC_CR2_DDS   ADC_CR2_DDS_Msk
     
    #define ADC_CR2_EOCS_Pos   (10U)
     
    #define ADC_CR2_EOCS_Msk   (0x1UL << ADC_CR2_EOCS_Pos)
     
    #define ADC_CR2_EOCS   ADC_CR2_EOCS_Msk
     
    #define ADC_CR2_ALIGN_Pos   (11U)
     
    #define ADC_CR2_ALIGN_Msk   (0x1UL << ADC_CR2_ALIGN_Pos)
     
    #define ADC_CR2_ALIGN   ADC_CR2_ALIGN_Msk
     
    #define ADC_CR2_JEXTSEL_Pos   (16U)
     
    #define ADC_CR2_JEXTSEL_Msk   (0xFUL << ADC_CR2_JEXTSEL_Pos)
     
    #define ADC_CR2_JEXTSEL   ADC_CR2_JEXTSEL_Msk
     
    #define ADC_CR2_JEXTSEL_0   (0x1UL << ADC_CR2_JEXTSEL_Pos)
     
    #define ADC_CR2_JEXTSEL_1   (0x2UL << ADC_CR2_JEXTSEL_Pos)
     
    #define ADC_CR2_JEXTSEL_2   (0x4UL << ADC_CR2_JEXTSEL_Pos)
     
    #define ADC_CR2_JEXTSEL_3   (0x8UL << ADC_CR2_JEXTSEL_Pos)
     
    #define ADC_CR2_JEXTEN_Pos   (20U)
     
    #define ADC_CR2_JEXTEN_Msk   (0x3UL << ADC_CR2_JEXTEN_Pos)
     
    #define ADC_CR2_JEXTEN   ADC_CR2_JEXTEN_Msk
     
    #define ADC_CR2_JEXTEN_0   (0x1UL << ADC_CR2_JEXTEN_Pos)
     
    #define ADC_CR2_JEXTEN_1   (0x2UL << ADC_CR2_JEXTEN_Pos)
     
    #define ADC_CR2_JSWSTART_Pos   (22U)
     
    #define ADC_CR2_JSWSTART_Msk   (0x1UL << ADC_CR2_JSWSTART_Pos)
     
    #define ADC_CR2_JSWSTART   ADC_CR2_JSWSTART_Msk
     
    #define ADC_CR2_EXTSEL_Pos   (24U)
     
    #define ADC_CR2_EXTSEL_Msk   (0xFUL << ADC_CR2_EXTSEL_Pos)
     
    #define ADC_CR2_EXTSEL   ADC_CR2_EXTSEL_Msk
     
    #define ADC_CR2_EXTSEL_0   (0x1UL << ADC_CR2_EXTSEL_Pos)
     
    #define ADC_CR2_EXTSEL_1   (0x2UL << ADC_CR2_EXTSEL_Pos)
     
    #define ADC_CR2_EXTSEL_2   (0x4UL << ADC_CR2_EXTSEL_Pos)
     
    #define ADC_CR2_EXTSEL_3   (0x8UL << ADC_CR2_EXTSEL_Pos)
     
    #define ADC_CR2_EXTEN_Pos   (28U)
     
    #define ADC_CR2_EXTEN_Msk   (0x3UL << ADC_CR2_EXTEN_Pos)
     
    #define ADC_CR2_EXTEN   ADC_CR2_EXTEN_Msk
     
    #define ADC_CR2_EXTEN_0   (0x1UL << ADC_CR2_EXTEN_Pos)
     
    #define ADC_CR2_EXTEN_1   (0x2UL << ADC_CR2_EXTEN_Pos)
     
    #define ADC_CR2_SWSTART_Pos   (30U)
     
    #define ADC_CR2_SWSTART_Msk   (0x1UL << ADC_CR2_SWSTART_Pos)
     
    #define ADC_CR2_SWSTART   ADC_CR2_SWSTART_Msk
     
    #define ADC_SMPR1_SMP10_Pos   (0U)
     
    #define ADC_SMPR1_SMP10_Msk   (0x7UL << ADC_SMPR1_SMP10_Pos)
     
    #define ADC_SMPR1_SMP10   ADC_SMPR1_SMP10_Msk
     
    #define ADC_SMPR1_SMP10_0   (0x1UL << ADC_SMPR1_SMP10_Pos)
     
    #define ADC_SMPR1_SMP10_1   (0x2UL << ADC_SMPR1_SMP10_Pos)
     
    #define ADC_SMPR1_SMP10_2   (0x4UL << ADC_SMPR1_SMP10_Pos)
     
    #define ADC_SMPR1_SMP11_Pos   (3U)
     
    #define ADC_SMPR1_SMP11_Msk   (0x7UL << ADC_SMPR1_SMP11_Pos)
     
    #define ADC_SMPR1_SMP11   ADC_SMPR1_SMP11_Msk
     
    #define ADC_SMPR1_SMP11_0   (0x1UL << ADC_SMPR1_SMP11_Pos)
     
    #define ADC_SMPR1_SMP11_1   (0x2UL << ADC_SMPR1_SMP11_Pos)
     
    #define ADC_SMPR1_SMP11_2   (0x4UL << ADC_SMPR1_SMP11_Pos)
     
    #define ADC_SMPR1_SMP12_Pos   (6U)
     
    #define ADC_SMPR1_SMP12_Msk   (0x7UL << ADC_SMPR1_SMP12_Pos)
     
    #define ADC_SMPR1_SMP12   ADC_SMPR1_SMP12_Msk
     
    #define ADC_SMPR1_SMP12_0   (0x1UL << ADC_SMPR1_SMP12_Pos)
     
    #define ADC_SMPR1_SMP12_1   (0x2UL << ADC_SMPR1_SMP12_Pos)
     
    #define ADC_SMPR1_SMP12_2   (0x4UL << ADC_SMPR1_SMP12_Pos)
     
    #define ADC_SMPR1_SMP13_Pos   (9U)
     
    #define ADC_SMPR1_SMP13_Msk   (0x7UL << ADC_SMPR1_SMP13_Pos)
     
    #define ADC_SMPR1_SMP13   ADC_SMPR1_SMP13_Msk
     
    #define ADC_SMPR1_SMP13_0   (0x1UL << ADC_SMPR1_SMP13_Pos)
     
    #define ADC_SMPR1_SMP13_1   (0x2UL << ADC_SMPR1_SMP13_Pos)
     
    #define ADC_SMPR1_SMP13_2   (0x4UL << ADC_SMPR1_SMP13_Pos)
     
    #define ADC_SMPR1_SMP14_Pos   (12U)
     
    #define ADC_SMPR1_SMP14_Msk   (0x7UL << ADC_SMPR1_SMP14_Pos)
     
    #define ADC_SMPR1_SMP14   ADC_SMPR1_SMP14_Msk
     
    #define ADC_SMPR1_SMP14_0   (0x1UL << ADC_SMPR1_SMP14_Pos)
     
    #define ADC_SMPR1_SMP14_1   (0x2UL << ADC_SMPR1_SMP14_Pos)
     
    #define ADC_SMPR1_SMP14_2   (0x4UL << ADC_SMPR1_SMP14_Pos)
     
    #define ADC_SMPR1_SMP15_Pos   (15U)
     
    #define ADC_SMPR1_SMP15_Msk   (0x7UL << ADC_SMPR1_SMP15_Pos)
     
    #define ADC_SMPR1_SMP15   ADC_SMPR1_SMP15_Msk
     
    #define ADC_SMPR1_SMP15_0   (0x1UL << ADC_SMPR1_SMP15_Pos)
     
    #define ADC_SMPR1_SMP15_1   (0x2UL << ADC_SMPR1_SMP15_Pos)
     
    #define ADC_SMPR1_SMP15_2   (0x4UL << ADC_SMPR1_SMP15_Pos)
     
    #define ADC_SMPR1_SMP16_Pos   (18U)
     
    #define ADC_SMPR1_SMP16_Msk   (0x7UL << ADC_SMPR1_SMP16_Pos)
     
    #define ADC_SMPR1_SMP16   ADC_SMPR1_SMP16_Msk
     
    #define ADC_SMPR1_SMP16_0   (0x1UL << ADC_SMPR1_SMP16_Pos)
     
    #define ADC_SMPR1_SMP16_1   (0x2UL << ADC_SMPR1_SMP16_Pos)
     
    #define ADC_SMPR1_SMP16_2   (0x4UL << ADC_SMPR1_SMP16_Pos)
     
    #define ADC_SMPR1_SMP17_Pos   (21U)
     
    #define ADC_SMPR1_SMP17_Msk   (0x7UL << ADC_SMPR1_SMP17_Pos)
     
    #define ADC_SMPR1_SMP17   ADC_SMPR1_SMP17_Msk
     
    #define ADC_SMPR1_SMP17_0   (0x1UL << ADC_SMPR1_SMP17_Pos)
     
    #define ADC_SMPR1_SMP17_1   (0x2UL << ADC_SMPR1_SMP17_Pos)
     
    #define ADC_SMPR1_SMP17_2   (0x4UL << ADC_SMPR1_SMP17_Pos)
     
    #define ADC_SMPR1_SMP18_Pos   (24U)
     
    #define ADC_SMPR1_SMP18_Msk   (0x7UL << ADC_SMPR1_SMP18_Pos)
     
    #define ADC_SMPR1_SMP18   ADC_SMPR1_SMP18_Msk
     
    #define ADC_SMPR1_SMP18_0   (0x1UL << ADC_SMPR1_SMP18_Pos)
     
    #define ADC_SMPR1_SMP18_1   (0x2UL << ADC_SMPR1_SMP18_Pos)
     
    #define ADC_SMPR1_SMP18_2   (0x4UL << ADC_SMPR1_SMP18_Pos)
     
    #define ADC_SMPR2_SMP0_Pos   (0U)
     
    #define ADC_SMPR2_SMP0_Msk   (0x7UL << ADC_SMPR2_SMP0_Pos)
     
    #define ADC_SMPR2_SMP0   ADC_SMPR2_SMP0_Msk
     
    #define ADC_SMPR2_SMP0_0   (0x1UL << ADC_SMPR2_SMP0_Pos)
     
    #define ADC_SMPR2_SMP0_1   (0x2UL << ADC_SMPR2_SMP0_Pos)
     
    #define ADC_SMPR2_SMP0_2   (0x4UL << ADC_SMPR2_SMP0_Pos)
     
    #define ADC_SMPR2_SMP1_Pos   (3U)
     
    #define ADC_SMPR2_SMP1_Msk   (0x7UL << ADC_SMPR2_SMP1_Pos)
     
    #define ADC_SMPR2_SMP1   ADC_SMPR2_SMP1_Msk
     
    #define ADC_SMPR2_SMP1_0   (0x1UL << ADC_SMPR2_SMP1_Pos)
     
    #define ADC_SMPR2_SMP1_1   (0x2UL << ADC_SMPR2_SMP1_Pos)
     
    #define ADC_SMPR2_SMP1_2   (0x4UL << ADC_SMPR2_SMP1_Pos)
     
    #define ADC_SMPR2_SMP2_Pos   (6U)
     
    #define ADC_SMPR2_SMP2_Msk   (0x7UL << ADC_SMPR2_SMP2_Pos)
     
    #define ADC_SMPR2_SMP2   ADC_SMPR2_SMP2_Msk
     
    #define ADC_SMPR2_SMP2_0   (0x1UL << ADC_SMPR2_SMP2_Pos)
     
    #define ADC_SMPR2_SMP2_1   (0x2UL << ADC_SMPR2_SMP2_Pos)
     
    #define ADC_SMPR2_SMP2_2   (0x4UL << ADC_SMPR2_SMP2_Pos)
     
    #define ADC_SMPR2_SMP3_Pos   (9U)
     
    #define ADC_SMPR2_SMP3_Msk   (0x7UL << ADC_SMPR2_SMP3_Pos)
     
    #define ADC_SMPR2_SMP3   ADC_SMPR2_SMP3_Msk
     
    #define ADC_SMPR2_SMP3_0   (0x1UL << ADC_SMPR2_SMP3_Pos)
     
    #define ADC_SMPR2_SMP3_1   (0x2UL << ADC_SMPR2_SMP3_Pos)
     
    #define ADC_SMPR2_SMP3_2   (0x4UL << ADC_SMPR2_SMP3_Pos)
     
    #define ADC_SMPR2_SMP4_Pos   (12U)
     
    #define ADC_SMPR2_SMP4_Msk   (0x7UL << ADC_SMPR2_SMP4_Pos)
     
    #define ADC_SMPR2_SMP4   ADC_SMPR2_SMP4_Msk
     
    #define ADC_SMPR2_SMP4_0   (0x1UL << ADC_SMPR2_SMP4_Pos)
     
    #define ADC_SMPR2_SMP4_1   (0x2UL << ADC_SMPR2_SMP4_Pos)
     
    #define ADC_SMPR2_SMP4_2   (0x4UL << ADC_SMPR2_SMP4_Pos)
     
    #define ADC_SMPR2_SMP5_Pos   (15U)
     
    #define ADC_SMPR2_SMP5_Msk   (0x7UL << ADC_SMPR2_SMP5_Pos)
     
    #define ADC_SMPR2_SMP5   ADC_SMPR2_SMP5_Msk
     
    #define ADC_SMPR2_SMP5_0   (0x1UL << ADC_SMPR2_SMP5_Pos)
     
    #define ADC_SMPR2_SMP5_1   (0x2UL << ADC_SMPR2_SMP5_Pos)
     
    #define ADC_SMPR2_SMP5_2   (0x4UL << ADC_SMPR2_SMP5_Pos)
     
    #define ADC_SMPR2_SMP6_Pos   (18U)
     
    #define ADC_SMPR2_SMP6_Msk   (0x7UL << ADC_SMPR2_SMP6_Pos)
     
    #define ADC_SMPR2_SMP6   ADC_SMPR2_SMP6_Msk
     
    #define ADC_SMPR2_SMP6_0   (0x1UL << ADC_SMPR2_SMP6_Pos)
     
    #define ADC_SMPR2_SMP6_1   (0x2UL << ADC_SMPR2_SMP6_Pos)
     
    #define ADC_SMPR2_SMP6_2   (0x4UL << ADC_SMPR2_SMP6_Pos)
     
    #define ADC_SMPR2_SMP7_Pos   (21U)
     
    #define ADC_SMPR2_SMP7_Msk   (0x7UL << ADC_SMPR2_SMP7_Pos)
     
    #define ADC_SMPR2_SMP7   ADC_SMPR2_SMP7_Msk
     
    #define ADC_SMPR2_SMP7_0   (0x1UL << ADC_SMPR2_SMP7_Pos)
     
    #define ADC_SMPR2_SMP7_1   (0x2UL << ADC_SMPR2_SMP7_Pos)
     
    #define ADC_SMPR2_SMP7_2   (0x4UL << ADC_SMPR2_SMP7_Pos)
     
    #define ADC_SMPR2_SMP8_Pos   (24U)
     
    #define ADC_SMPR2_SMP8_Msk   (0x7UL << ADC_SMPR2_SMP8_Pos)
     
    #define ADC_SMPR2_SMP8   ADC_SMPR2_SMP8_Msk
     
    #define ADC_SMPR2_SMP8_0   (0x1UL << ADC_SMPR2_SMP8_Pos)
     
    #define ADC_SMPR2_SMP8_1   (0x2UL << ADC_SMPR2_SMP8_Pos)
     
    #define ADC_SMPR2_SMP8_2   (0x4UL << ADC_SMPR2_SMP8_Pos)
     
    #define ADC_SMPR2_SMP9_Pos   (27U)
     
    #define ADC_SMPR2_SMP9_Msk   (0x7UL << ADC_SMPR2_SMP9_Pos)
     
    #define ADC_SMPR2_SMP9   ADC_SMPR2_SMP9_Msk
     
    #define ADC_SMPR2_SMP9_0   (0x1UL << ADC_SMPR2_SMP9_Pos)
     
    #define ADC_SMPR2_SMP9_1   (0x2UL << ADC_SMPR2_SMP9_Pos)
     
    #define ADC_SMPR2_SMP9_2   (0x4UL << ADC_SMPR2_SMP9_Pos)
     
    #define ADC_JOFR1_JOFFSET1_Pos   (0U)
     
    #define ADC_JOFR1_JOFFSET1_Msk   (0xFFFUL << ADC_JOFR1_JOFFSET1_Pos)
     
    #define ADC_JOFR1_JOFFSET1   ADC_JOFR1_JOFFSET1_Msk
     
    #define ADC_JOFR2_JOFFSET2_Pos   (0U)
     
    #define ADC_JOFR2_JOFFSET2_Msk   (0xFFFUL << ADC_JOFR2_JOFFSET2_Pos)
     
    #define ADC_JOFR2_JOFFSET2   ADC_JOFR2_JOFFSET2_Msk
     
    #define ADC_JOFR3_JOFFSET3_Pos   (0U)
     
    #define ADC_JOFR3_JOFFSET3_Msk   (0xFFFUL << ADC_JOFR3_JOFFSET3_Pos)
     
    #define ADC_JOFR3_JOFFSET3   ADC_JOFR3_JOFFSET3_Msk
     
    #define ADC_JOFR4_JOFFSET4_Pos   (0U)
     
    #define ADC_JOFR4_JOFFSET4_Msk   (0xFFFUL << ADC_JOFR4_JOFFSET4_Pos)
     
    #define ADC_JOFR4_JOFFSET4   ADC_JOFR4_JOFFSET4_Msk
     
    #define ADC_HTR_HT_Pos   (0U)
     
    #define ADC_HTR_HT_Msk   (0xFFFUL << ADC_HTR_HT_Pos)
     
    #define ADC_HTR_HT   ADC_HTR_HT_Msk
     
    #define ADC_LTR_LT_Pos   (0U)
     
    #define ADC_LTR_LT_Msk   (0xFFFUL << ADC_LTR_LT_Pos)
     
    #define ADC_LTR_LT   ADC_LTR_LT_Msk
     
    #define ADC_SQR1_SQ13_Pos   (0U)
     
    #define ADC_SQR1_SQ13_Msk   (0x1FUL << ADC_SQR1_SQ13_Pos)
     
    #define ADC_SQR1_SQ13   ADC_SQR1_SQ13_Msk
     
    #define ADC_SQR1_SQ13_0   (0x01UL << ADC_SQR1_SQ13_Pos)
     
    #define ADC_SQR1_SQ13_1   (0x02UL << ADC_SQR1_SQ13_Pos)
     
    #define ADC_SQR1_SQ13_2   (0x04UL << ADC_SQR1_SQ13_Pos)
     
    #define ADC_SQR1_SQ13_3   (0x08UL << ADC_SQR1_SQ13_Pos)
     
    #define ADC_SQR1_SQ13_4   (0x10UL << ADC_SQR1_SQ13_Pos)
     
    #define ADC_SQR1_SQ14_Pos   (5U)
     
    #define ADC_SQR1_SQ14_Msk   (0x1FUL << ADC_SQR1_SQ14_Pos)
     
    #define ADC_SQR1_SQ14   ADC_SQR1_SQ14_Msk
     
    #define ADC_SQR1_SQ14_0   (0x01UL << ADC_SQR1_SQ14_Pos)
     
    #define ADC_SQR1_SQ14_1   (0x02UL << ADC_SQR1_SQ14_Pos)
     
    #define ADC_SQR1_SQ14_2   (0x04UL << ADC_SQR1_SQ14_Pos)
     
    #define ADC_SQR1_SQ14_3   (0x08UL << ADC_SQR1_SQ14_Pos)
     
    #define ADC_SQR1_SQ14_4   (0x10UL << ADC_SQR1_SQ14_Pos)
     
    #define ADC_SQR1_SQ15_Pos   (10U)
     
    #define ADC_SQR1_SQ15_Msk   (0x1FUL << ADC_SQR1_SQ15_Pos)
     
    #define ADC_SQR1_SQ15   ADC_SQR1_SQ15_Msk
     
    #define ADC_SQR1_SQ15_0   (0x01UL << ADC_SQR1_SQ15_Pos)
     
    #define ADC_SQR1_SQ15_1   (0x02UL << ADC_SQR1_SQ15_Pos)
     
    #define ADC_SQR1_SQ15_2   (0x04UL << ADC_SQR1_SQ15_Pos)
     
    #define ADC_SQR1_SQ15_3   (0x08UL << ADC_SQR1_SQ15_Pos)
     
    #define ADC_SQR1_SQ15_4   (0x10UL << ADC_SQR1_SQ15_Pos)
     
    #define ADC_SQR1_SQ16_Pos   (15U)
     
    #define ADC_SQR1_SQ16_Msk   (0x1FUL << ADC_SQR1_SQ16_Pos)
     
    #define ADC_SQR1_SQ16   ADC_SQR1_SQ16_Msk
     
    #define ADC_SQR1_SQ16_0   (0x01UL << ADC_SQR1_SQ16_Pos)
     
    #define ADC_SQR1_SQ16_1   (0x02UL << ADC_SQR1_SQ16_Pos)
     
    #define ADC_SQR1_SQ16_2   (0x04UL << ADC_SQR1_SQ16_Pos)
     
    #define ADC_SQR1_SQ16_3   (0x08UL << ADC_SQR1_SQ16_Pos)
     
    #define ADC_SQR1_SQ16_4   (0x10UL << ADC_SQR1_SQ16_Pos)
     
    #define ADC_SQR1_L_Pos   (20U)
     
    #define ADC_SQR1_L_Msk   (0xFUL << ADC_SQR1_L_Pos)
     
    #define ADC_SQR1_L   ADC_SQR1_L_Msk
     
    #define ADC_SQR1_L_0   (0x1UL << ADC_SQR1_L_Pos)
     
    #define ADC_SQR1_L_1   (0x2UL << ADC_SQR1_L_Pos)
     
    #define ADC_SQR1_L_2   (0x4UL << ADC_SQR1_L_Pos)
     
    #define ADC_SQR1_L_3   (0x8UL << ADC_SQR1_L_Pos)
     
    #define ADC_SQR2_SQ7_Pos   (0U)
     
    #define ADC_SQR2_SQ7_Msk   (0x1FUL << ADC_SQR2_SQ7_Pos)
     
    #define ADC_SQR2_SQ7   ADC_SQR2_SQ7_Msk
     
    #define ADC_SQR2_SQ7_0   (0x01UL << ADC_SQR2_SQ7_Pos)
     
    #define ADC_SQR2_SQ7_1   (0x02UL << ADC_SQR2_SQ7_Pos)
     
    #define ADC_SQR2_SQ7_2   (0x04UL << ADC_SQR2_SQ7_Pos)
     
    #define ADC_SQR2_SQ7_3   (0x08UL << ADC_SQR2_SQ7_Pos)
     
    #define ADC_SQR2_SQ7_4   (0x10UL << ADC_SQR2_SQ7_Pos)
     
    #define ADC_SQR2_SQ8_Pos   (5U)
     
    #define ADC_SQR2_SQ8_Msk   (0x1FUL << ADC_SQR2_SQ8_Pos)
     
    #define ADC_SQR2_SQ8   ADC_SQR2_SQ8_Msk
     
    #define ADC_SQR2_SQ8_0   (0x01UL << ADC_SQR2_SQ8_Pos)
     
    #define ADC_SQR2_SQ8_1   (0x02UL << ADC_SQR2_SQ8_Pos)
     
    #define ADC_SQR2_SQ8_2   (0x04UL << ADC_SQR2_SQ8_Pos)
     
    #define ADC_SQR2_SQ8_3   (0x08UL << ADC_SQR2_SQ8_Pos)
     
    #define ADC_SQR2_SQ8_4   (0x10UL << ADC_SQR2_SQ8_Pos)
     
    #define ADC_SQR2_SQ9_Pos   (10U)
     
    #define ADC_SQR2_SQ9_Msk   (0x1FUL << ADC_SQR2_SQ9_Pos)
     
    #define ADC_SQR2_SQ9   ADC_SQR2_SQ9_Msk
     
    #define ADC_SQR2_SQ9_0   (0x01UL << ADC_SQR2_SQ9_Pos)
     
    #define ADC_SQR2_SQ9_1   (0x02UL << ADC_SQR2_SQ9_Pos)
     
    #define ADC_SQR2_SQ9_2   (0x04UL << ADC_SQR2_SQ9_Pos)
     
    #define ADC_SQR2_SQ9_3   (0x08UL << ADC_SQR2_SQ9_Pos)
     
    #define ADC_SQR2_SQ9_4   (0x10UL << ADC_SQR2_SQ9_Pos)
     
    #define ADC_SQR2_SQ10_Pos   (15U)
     
    #define ADC_SQR2_SQ10_Msk   (0x1FUL << ADC_SQR2_SQ10_Pos)
     
    #define ADC_SQR2_SQ10   ADC_SQR2_SQ10_Msk
     
    #define ADC_SQR2_SQ10_0   (0x01UL << ADC_SQR2_SQ10_Pos)
     
    #define ADC_SQR2_SQ10_1   (0x02UL << ADC_SQR2_SQ10_Pos)
     
    #define ADC_SQR2_SQ10_2   (0x04UL << ADC_SQR2_SQ10_Pos)
     
    #define ADC_SQR2_SQ10_3   (0x08UL << ADC_SQR2_SQ10_Pos)
     
    #define ADC_SQR2_SQ10_4   (0x10UL << ADC_SQR2_SQ10_Pos)
     
    #define ADC_SQR2_SQ11_Pos   (20U)
     
    #define ADC_SQR2_SQ11_Msk   (0x1FUL << ADC_SQR2_SQ11_Pos)
     
    #define ADC_SQR2_SQ11   ADC_SQR2_SQ11_Msk
     
    #define ADC_SQR2_SQ11_0   (0x01UL << ADC_SQR2_SQ11_Pos)
     
    #define ADC_SQR2_SQ11_1   (0x02UL << ADC_SQR2_SQ11_Pos)
     
    #define ADC_SQR2_SQ11_2   (0x04UL << ADC_SQR2_SQ11_Pos)
     
    #define ADC_SQR2_SQ11_3   (0x08UL << ADC_SQR2_SQ11_Pos)
     
    #define ADC_SQR2_SQ11_4   (0x10UL << ADC_SQR2_SQ11_Pos)
     
    #define ADC_SQR2_SQ12_Pos   (25U)
     
    #define ADC_SQR2_SQ12_Msk   (0x1FUL << ADC_SQR2_SQ12_Pos)
     
    #define ADC_SQR2_SQ12   ADC_SQR2_SQ12_Msk
     
    #define ADC_SQR2_SQ12_0   (0x01UL << ADC_SQR2_SQ12_Pos)
     
    #define ADC_SQR2_SQ12_1   (0x02UL << ADC_SQR2_SQ12_Pos)
     
    #define ADC_SQR2_SQ12_2   (0x04UL << ADC_SQR2_SQ12_Pos)
     
    #define ADC_SQR2_SQ12_3   (0x08UL << ADC_SQR2_SQ12_Pos)
     
    #define ADC_SQR2_SQ12_4   (0x10UL << ADC_SQR2_SQ12_Pos)
     
    #define ADC_SQR3_SQ1_Pos   (0U)
     
    #define ADC_SQR3_SQ1_Msk   (0x1FUL << ADC_SQR3_SQ1_Pos)
     
    #define ADC_SQR3_SQ1   ADC_SQR3_SQ1_Msk
     
    #define ADC_SQR3_SQ1_0   (0x01UL << ADC_SQR3_SQ1_Pos)
     
    #define ADC_SQR3_SQ1_1   (0x02UL << ADC_SQR3_SQ1_Pos)
     
    #define ADC_SQR3_SQ1_2   (0x04UL << ADC_SQR3_SQ1_Pos)
     
    #define ADC_SQR3_SQ1_3   (0x08UL << ADC_SQR3_SQ1_Pos)
     
    #define ADC_SQR3_SQ1_4   (0x10UL << ADC_SQR3_SQ1_Pos)
     
    #define ADC_SQR3_SQ2_Pos   (5U)
     
    #define ADC_SQR3_SQ2_Msk   (0x1FUL << ADC_SQR3_SQ2_Pos)
     
    #define ADC_SQR3_SQ2   ADC_SQR3_SQ2_Msk
     
    #define ADC_SQR3_SQ2_0   (0x01UL << ADC_SQR3_SQ2_Pos)
     
    #define ADC_SQR3_SQ2_1   (0x02UL << ADC_SQR3_SQ2_Pos)
     
    #define ADC_SQR3_SQ2_2   (0x04UL << ADC_SQR3_SQ2_Pos)
     
    #define ADC_SQR3_SQ2_3   (0x08UL << ADC_SQR3_SQ2_Pos)
     
    #define ADC_SQR3_SQ2_4   (0x10UL << ADC_SQR3_SQ2_Pos)
     
    #define ADC_SQR3_SQ3_Pos   (10U)
     
    #define ADC_SQR3_SQ3_Msk   (0x1FUL << ADC_SQR3_SQ3_Pos)
     
    #define ADC_SQR3_SQ3   ADC_SQR3_SQ3_Msk
     
    #define ADC_SQR3_SQ3_0   (0x01UL << ADC_SQR3_SQ3_Pos)
     
    #define ADC_SQR3_SQ3_1   (0x02UL << ADC_SQR3_SQ3_Pos)
     
    #define ADC_SQR3_SQ3_2   (0x04UL << ADC_SQR3_SQ3_Pos)
     
    #define ADC_SQR3_SQ3_3   (0x08UL << ADC_SQR3_SQ3_Pos)
     
    #define ADC_SQR3_SQ3_4   (0x10UL << ADC_SQR3_SQ3_Pos)
     
    #define ADC_SQR3_SQ4_Pos   (15U)
     
    #define ADC_SQR3_SQ4_Msk   (0x1FUL << ADC_SQR3_SQ4_Pos)
     
    #define ADC_SQR3_SQ4   ADC_SQR3_SQ4_Msk
     
    #define ADC_SQR3_SQ4_0   (0x01UL << ADC_SQR3_SQ4_Pos)
     
    #define ADC_SQR3_SQ4_1   (0x02UL << ADC_SQR3_SQ4_Pos)
     
    #define ADC_SQR3_SQ4_2   (0x04UL << ADC_SQR3_SQ4_Pos)
     
    #define ADC_SQR3_SQ4_3   (0x08UL << ADC_SQR3_SQ4_Pos)
     
    #define ADC_SQR3_SQ4_4   (0x10UL << ADC_SQR3_SQ4_Pos)
     
    #define ADC_SQR3_SQ5_Pos   (20U)
     
    #define ADC_SQR3_SQ5_Msk   (0x1FUL << ADC_SQR3_SQ5_Pos)
     
    #define ADC_SQR3_SQ5   ADC_SQR3_SQ5_Msk
     
    #define ADC_SQR3_SQ5_0   (0x01UL << ADC_SQR3_SQ5_Pos)
     
    #define ADC_SQR3_SQ5_1   (0x02UL << ADC_SQR3_SQ5_Pos)
     
    #define ADC_SQR3_SQ5_2   (0x04UL << ADC_SQR3_SQ5_Pos)
     
    #define ADC_SQR3_SQ5_3   (0x08UL << ADC_SQR3_SQ5_Pos)
     
    #define ADC_SQR3_SQ5_4   (0x10UL << ADC_SQR3_SQ5_Pos)
     
    #define ADC_SQR3_SQ6_Pos   (25U)
     
    #define ADC_SQR3_SQ6_Msk   (0x1FUL << ADC_SQR3_SQ6_Pos)
     
    #define ADC_SQR3_SQ6   ADC_SQR3_SQ6_Msk
     
    #define ADC_SQR3_SQ6_0   (0x01UL << ADC_SQR3_SQ6_Pos)
     
    #define ADC_SQR3_SQ6_1   (0x02UL << ADC_SQR3_SQ6_Pos)
     
    #define ADC_SQR3_SQ6_2   (0x04UL << ADC_SQR3_SQ6_Pos)
     
    #define ADC_SQR3_SQ6_3   (0x08UL << ADC_SQR3_SQ6_Pos)
     
    #define ADC_SQR3_SQ6_4   (0x10UL << ADC_SQR3_SQ6_Pos)
     
    #define ADC_JSQR_JSQ1_Pos   (0U)
     
    #define ADC_JSQR_JSQ1_Msk   (0x1FUL << ADC_JSQR_JSQ1_Pos)
     
    #define ADC_JSQR_JSQ1   ADC_JSQR_JSQ1_Msk
     
    #define ADC_JSQR_JSQ1_0   (0x01UL << ADC_JSQR_JSQ1_Pos)
     
    #define ADC_JSQR_JSQ1_1   (0x02UL << ADC_JSQR_JSQ1_Pos)
     
    #define ADC_JSQR_JSQ1_2   (0x04UL << ADC_JSQR_JSQ1_Pos)
     
    #define ADC_JSQR_JSQ1_3   (0x08UL << ADC_JSQR_JSQ1_Pos)
     
    #define ADC_JSQR_JSQ1_4   (0x10UL << ADC_JSQR_JSQ1_Pos)
     
    #define ADC_JSQR_JSQ2_Pos   (5U)
     
    #define ADC_JSQR_JSQ2_Msk   (0x1FUL << ADC_JSQR_JSQ2_Pos)
     
    #define ADC_JSQR_JSQ2   ADC_JSQR_JSQ2_Msk
     
    #define ADC_JSQR_JSQ2_0   (0x01UL << ADC_JSQR_JSQ2_Pos)
     
    #define ADC_JSQR_JSQ2_1   (0x02UL << ADC_JSQR_JSQ2_Pos)
     
    #define ADC_JSQR_JSQ2_2   (0x04UL << ADC_JSQR_JSQ2_Pos)
     
    #define ADC_JSQR_JSQ2_3   (0x08UL << ADC_JSQR_JSQ2_Pos)
     
    #define ADC_JSQR_JSQ2_4   (0x10UL << ADC_JSQR_JSQ2_Pos)
     
    #define ADC_JSQR_JSQ3_Pos   (10U)
     
    #define ADC_JSQR_JSQ3_Msk   (0x1FUL << ADC_JSQR_JSQ3_Pos)
     
    #define ADC_JSQR_JSQ3   ADC_JSQR_JSQ3_Msk
     
    #define ADC_JSQR_JSQ3_0   (0x01UL << ADC_JSQR_JSQ3_Pos)
     
    #define ADC_JSQR_JSQ3_1   (0x02UL << ADC_JSQR_JSQ3_Pos)
     
    #define ADC_JSQR_JSQ3_2   (0x04UL << ADC_JSQR_JSQ3_Pos)
     
    #define ADC_JSQR_JSQ3_3   (0x08UL << ADC_JSQR_JSQ3_Pos)
     
    #define ADC_JSQR_JSQ3_4   (0x10UL << ADC_JSQR_JSQ3_Pos)
     
    #define ADC_JSQR_JSQ4_Pos   (15U)
     
    #define ADC_JSQR_JSQ4_Msk   (0x1FUL << ADC_JSQR_JSQ4_Pos)
     
    #define ADC_JSQR_JSQ4   ADC_JSQR_JSQ4_Msk
     
    #define ADC_JSQR_JSQ4_0   (0x01UL << ADC_JSQR_JSQ4_Pos)
     
    #define ADC_JSQR_JSQ4_1   (0x02UL << ADC_JSQR_JSQ4_Pos)
     
    #define ADC_JSQR_JSQ4_2   (0x04UL << ADC_JSQR_JSQ4_Pos)
     
    #define ADC_JSQR_JSQ4_3   (0x08UL << ADC_JSQR_JSQ4_Pos)
     
    #define ADC_JSQR_JSQ4_4   (0x10UL << ADC_JSQR_JSQ4_Pos)
     
    #define ADC_JSQR_JL_Pos   (20U)
     
    #define ADC_JSQR_JL_Msk   (0x3UL << ADC_JSQR_JL_Pos)
     
    #define ADC_JSQR_JL   ADC_JSQR_JL_Msk
     
    #define ADC_JSQR_JL_0   (0x1UL << ADC_JSQR_JL_Pos)
     
    #define ADC_JSQR_JL_1   (0x2UL << ADC_JSQR_JL_Pos)
     
    #define ADC_JDR1_JDATA_Pos   (0U)
     
    #define ADC_JDR1_JDATA_Msk   (0xFFFFUL << ADC_JDR1_JDATA_Pos)
     
    #define ADC_JDR1_JDATA   ADC_JDR1_JDATA_Msk
     
    #define ADC_JDR2_JDATA_Pos   (0U)
     
    #define ADC_JDR2_JDATA_Msk   (0xFFFFUL << ADC_JDR2_JDATA_Pos)
     
    #define ADC_JDR2_JDATA   ADC_JDR2_JDATA_Msk
     
    #define ADC_JDR3_JDATA_Pos   (0U)
     
    #define ADC_JDR3_JDATA_Msk   (0xFFFFUL << ADC_JDR3_JDATA_Pos)
     
    #define ADC_JDR3_JDATA   ADC_JDR3_JDATA_Msk
     
    #define ADC_JDR4_JDATA_Pos   (0U)
     
    #define ADC_JDR4_JDATA_Msk   (0xFFFFUL << ADC_JDR4_JDATA_Pos)
     
    #define ADC_JDR4_JDATA   ADC_JDR4_JDATA_Msk
     
    #define ADC_DR_DATA_Pos   (0U)
     
    #define ADC_DR_DATA_Msk   (0xFFFFUL << ADC_DR_DATA_Pos)
     
    #define ADC_DR_DATA   ADC_DR_DATA_Msk
     
    #define ADC_DR_ADC2DATA_Pos   (16U)
     
    #define ADC_DR_ADC2DATA_Msk   (0xFFFFUL << ADC_DR_ADC2DATA_Pos)
     
    #define ADC_DR_ADC2DATA   ADC_DR_ADC2DATA_Msk
     
    #define ADC_CSR_AWD1_Pos   (0U)
     
    #define ADC_CSR_AWD1_Msk   (0x1UL << ADC_CSR_AWD1_Pos)
     
    #define ADC_CSR_AWD1   ADC_CSR_AWD1_Msk
     
    #define ADC_CSR_EOC1_Pos   (1U)
     
    #define ADC_CSR_EOC1_Msk   (0x1UL << ADC_CSR_EOC1_Pos)
     
    #define ADC_CSR_EOC1   ADC_CSR_EOC1_Msk
     
    #define ADC_CSR_JEOC1_Pos   (2U)
     
    #define ADC_CSR_JEOC1_Msk   (0x1UL << ADC_CSR_JEOC1_Pos)
     
    #define ADC_CSR_JEOC1   ADC_CSR_JEOC1_Msk
     
    #define ADC_CSR_JSTRT1_Pos   (3U)
     
    #define ADC_CSR_JSTRT1_Msk   (0x1UL << ADC_CSR_JSTRT1_Pos)
     
    #define ADC_CSR_JSTRT1   ADC_CSR_JSTRT1_Msk
     
    #define ADC_CSR_STRT1_Pos   (4U)
     
    #define ADC_CSR_STRT1_Msk   (0x1UL << ADC_CSR_STRT1_Pos)
     
    #define ADC_CSR_STRT1   ADC_CSR_STRT1_Msk
     
    #define ADC_CSR_OVR1_Pos   (5U)
     
    #define ADC_CSR_OVR1_Msk   (0x1UL << ADC_CSR_OVR1_Pos)
     
    #define ADC_CSR_OVR1   ADC_CSR_OVR1_Msk
     
    #define ADC_CSR_AWD2_Pos   (8U)
     
    #define ADC_CSR_AWD2_Msk   (0x1UL << ADC_CSR_AWD2_Pos)
     
    #define ADC_CSR_AWD2   ADC_CSR_AWD2_Msk
     
    #define ADC_CSR_EOC2_Pos   (9U)
     
    #define ADC_CSR_EOC2_Msk   (0x1UL << ADC_CSR_EOC2_Pos)
     
    #define ADC_CSR_EOC2   ADC_CSR_EOC2_Msk
     
    #define ADC_CSR_JEOC2_Pos   (10U)
     
    #define ADC_CSR_JEOC2_Msk   (0x1UL << ADC_CSR_JEOC2_Pos)
     
    #define ADC_CSR_JEOC2   ADC_CSR_JEOC2_Msk
     
    #define ADC_CSR_JSTRT2_Pos   (11U)
     
    #define ADC_CSR_JSTRT2_Msk   (0x1UL << ADC_CSR_JSTRT2_Pos)
     
    #define ADC_CSR_JSTRT2   ADC_CSR_JSTRT2_Msk
     
    #define ADC_CSR_STRT2_Pos   (12U)
     
    #define ADC_CSR_STRT2_Msk   (0x1UL << ADC_CSR_STRT2_Pos)
     
    #define ADC_CSR_STRT2   ADC_CSR_STRT2_Msk
     
    #define ADC_CSR_OVR2_Pos   (13U)
     
    #define ADC_CSR_OVR2_Msk   (0x1UL << ADC_CSR_OVR2_Pos)
     
    #define ADC_CSR_OVR2   ADC_CSR_OVR2_Msk
     
    #define ADC_CSR_AWD3_Pos   (16U)
     
    #define ADC_CSR_AWD3_Msk   (0x1UL << ADC_CSR_AWD3_Pos)
     
    #define ADC_CSR_AWD3   ADC_CSR_AWD3_Msk
     
    #define ADC_CSR_EOC3_Pos   (17U)
     
    #define ADC_CSR_EOC3_Msk   (0x1UL << ADC_CSR_EOC3_Pos)
     
    #define ADC_CSR_EOC3   ADC_CSR_EOC3_Msk
     
    #define ADC_CSR_JEOC3_Pos   (18U)
     
    #define ADC_CSR_JEOC3_Msk   (0x1UL << ADC_CSR_JEOC3_Pos)
     
    #define ADC_CSR_JEOC3   ADC_CSR_JEOC3_Msk
     
    #define ADC_CSR_JSTRT3_Pos   (19U)
     
    #define ADC_CSR_JSTRT3_Msk   (0x1UL << ADC_CSR_JSTRT3_Pos)
     
    #define ADC_CSR_JSTRT3   ADC_CSR_JSTRT3_Msk
     
    #define ADC_CSR_STRT3_Pos   (20U)
     
    #define ADC_CSR_STRT3_Msk   (0x1UL << ADC_CSR_STRT3_Pos)
     
    #define ADC_CSR_STRT3   ADC_CSR_STRT3_Msk
     
    #define ADC_CSR_OVR3_Pos   (21U)
     
    #define ADC_CSR_OVR3_Msk   (0x1UL << ADC_CSR_OVR3_Pos)
     
    #define ADC_CSR_OVR3   ADC_CSR_OVR3_Msk
     
    #define ADC_CSR_DOVR1   ADC_CSR_OVR1
     
    #define ADC_CSR_DOVR2   ADC_CSR_OVR2
     
    #define ADC_CSR_DOVR3   ADC_CSR_OVR3
     
    #define ADC_CCR_MULTI_Pos   (0U)
     
    #define ADC_CCR_MULTI_Msk   (0x1FUL << ADC_CCR_MULTI_Pos)
     
    #define ADC_CCR_MULTI   ADC_CCR_MULTI_Msk
     
    #define ADC_CCR_MULTI_0   (0x01UL << ADC_CCR_MULTI_Pos)
     
    #define ADC_CCR_MULTI_1   (0x02UL << ADC_CCR_MULTI_Pos)
     
    #define ADC_CCR_MULTI_2   (0x04UL << ADC_CCR_MULTI_Pos)
     
    #define ADC_CCR_MULTI_3   (0x08UL << ADC_CCR_MULTI_Pos)
     
    #define ADC_CCR_MULTI_4   (0x10UL << ADC_CCR_MULTI_Pos)
     
    #define ADC_CCR_DELAY_Pos   (8U)
     
    #define ADC_CCR_DELAY_Msk   (0xFUL << ADC_CCR_DELAY_Pos)
     
    #define ADC_CCR_DELAY   ADC_CCR_DELAY_Msk
     
    #define ADC_CCR_DELAY_0   (0x1UL << ADC_CCR_DELAY_Pos)
     
    #define ADC_CCR_DELAY_1   (0x2UL << ADC_CCR_DELAY_Pos)
     
    #define ADC_CCR_DELAY_2   (0x4UL << ADC_CCR_DELAY_Pos)
     
    #define ADC_CCR_DELAY_3   (0x8UL << ADC_CCR_DELAY_Pos)
     
    #define ADC_CCR_DDS_Pos   (13U)
     
    #define ADC_CCR_DDS_Msk   (0x1UL << ADC_CCR_DDS_Pos)
     
    #define ADC_CCR_DDS   ADC_CCR_DDS_Msk
     
    #define ADC_CCR_DMA_Pos   (14U)
     
    #define ADC_CCR_DMA_Msk   (0x3UL << ADC_CCR_DMA_Pos)
     
    #define ADC_CCR_DMA   ADC_CCR_DMA_Msk
     
    #define ADC_CCR_DMA_0   (0x1UL << ADC_CCR_DMA_Pos)
     
    #define ADC_CCR_DMA_1   (0x2UL << ADC_CCR_DMA_Pos)
     
    #define ADC_CCR_ADCPRE_Pos   (16U)
     
    #define ADC_CCR_ADCPRE_Msk   (0x3UL << ADC_CCR_ADCPRE_Pos)
     
    #define ADC_CCR_ADCPRE   ADC_CCR_ADCPRE_Msk
     
    #define ADC_CCR_ADCPRE_0   (0x1UL << ADC_CCR_ADCPRE_Pos)
     
    #define ADC_CCR_ADCPRE_1   (0x2UL << ADC_CCR_ADCPRE_Pos)
     
    #define ADC_CCR_VBATE_Pos   (22U)
     
    #define ADC_CCR_VBATE_Msk   (0x1UL << ADC_CCR_VBATE_Pos)
     
    #define ADC_CCR_VBATE   ADC_CCR_VBATE_Msk
     
    #define ADC_CCR_TSVREFE_Pos   (23U)
     
    #define ADC_CCR_TSVREFE_Msk   (0x1UL << ADC_CCR_TSVREFE_Pos)
     
    #define ADC_CCR_TSVREFE   ADC_CCR_TSVREFE_Msk
     
    #define ADC_CDR_DATA1_Pos   (0U)
     
    #define ADC_CDR_DATA1_Msk   (0xFFFFUL << ADC_CDR_DATA1_Pos)
     
    #define ADC_CDR_DATA1   ADC_CDR_DATA1_Msk
     
    #define ADC_CDR_DATA2_Pos   (16U)
     
    #define ADC_CDR_DATA2_Msk   (0xFFFFUL << ADC_CDR_DATA2_Pos)
     
    #define ADC_CDR_DATA2   ADC_CDR_DATA2_Msk
     
    #define ADC_CDR_RDATA_MST   ADC_CDR_DATA1
     
    #define ADC_CDR_RDATA_SLV   ADC_CDR_DATA2
     
    #define CAN_MCR_INRQ_Pos   (0U)
     
    #define CAN_MCR_INRQ_Msk   (0x1UL << CAN_MCR_INRQ_Pos)
     
    #define CAN_MCR_INRQ   CAN_MCR_INRQ_Msk
     
    #define CAN_MCR_SLEEP_Pos   (1U)
     
    #define CAN_MCR_SLEEP_Msk   (0x1UL << CAN_MCR_SLEEP_Pos)
     
    #define CAN_MCR_SLEEP   CAN_MCR_SLEEP_Msk
     
    #define CAN_MCR_TXFP_Pos   (2U)
     
    #define CAN_MCR_TXFP_Msk   (0x1UL << CAN_MCR_TXFP_Pos)
     
    #define CAN_MCR_TXFP   CAN_MCR_TXFP_Msk
     
    #define CAN_MCR_RFLM_Pos   (3U)
     
    #define CAN_MCR_RFLM_Msk   (0x1UL << CAN_MCR_RFLM_Pos)
     
    #define CAN_MCR_RFLM   CAN_MCR_RFLM_Msk
     
    #define CAN_MCR_NART_Pos   (4U)
     
    #define CAN_MCR_NART_Msk   (0x1UL << CAN_MCR_NART_Pos)
     
    #define CAN_MCR_NART   CAN_MCR_NART_Msk
     
    #define CAN_MCR_AWUM_Pos   (5U)
     
    #define CAN_MCR_AWUM_Msk   (0x1UL << CAN_MCR_AWUM_Pos)
     
    #define CAN_MCR_AWUM   CAN_MCR_AWUM_Msk
     
    #define CAN_MCR_ABOM_Pos   (6U)
     
    #define CAN_MCR_ABOM_Msk   (0x1UL << CAN_MCR_ABOM_Pos)
     
    #define CAN_MCR_ABOM   CAN_MCR_ABOM_Msk
     
    #define CAN_MCR_TTCM_Pos   (7U)
     
    #define CAN_MCR_TTCM_Msk   (0x1UL << CAN_MCR_TTCM_Pos)
     
    #define CAN_MCR_TTCM   CAN_MCR_TTCM_Msk
     
    #define CAN_MCR_RESET_Pos   (15U)
     
    #define CAN_MCR_RESET_Msk   (0x1UL << CAN_MCR_RESET_Pos)
     
    #define CAN_MCR_RESET   CAN_MCR_RESET_Msk
     
    #define CAN_MCR_DBF_Pos   (16U)
     
    #define CAN_MCR_DBF_Msk   (0x1UL << CAN_MCR_DBF_Pos)
     
    #define CAN_MCR_DBF   CAN_MCR_DBF_Msk
     
    #define CAN_MSR_INAK_Pos   (0U)
     
    #define CAN_MSR_INAK_Msk   (0x1UL << CAN_MSR_INAK_Pos)
     
    #define CAN_MSR_INAK   CAN_MSR_INAK_Msk
     
    #define CAN_MSR_SLAK_Pos   (1U)
     
    #define CAN_MSR_SLAK_Msk   (0x1UL << CAN_MSR_SLAK_Pos)
     
    #define CAN_MSR_SLAK   CAN_MSR_SLAK_Msk
     
    #define CAN_MSR_ERRI_Pos   (2U)
     
    #define CAN_MSR_ERRI_Msk   (0x1UL << CAN_MSR_ERRI_Pos)
     
    #define CAN_MSR_ERRI   CAN_MSR_ERRI_Msk
     
    #define CAN_MSR_WKUI_Pos   (3U)
     
    #define CAN_MSR_WKUI_Msk   (0x1UL << CAN_MSR_WKUI_Pos)
     
    #define CAN_MSR_WKUI   CAN_MSR_WKUI_Msk
     
    #define CAN_MSR_SLAKI_Pos   (4U)
     
    #define CAN_MSR_SLAKI_Msk   (0x1UL << CAN_MSR_SLAKI_Pos)
     
    #define CAN_MSR_SLAKI   CAN_MSR_SLAKI_Msk
     
    #define CAN_MSR_TXM_Pos   (8U)
     
    #define CAN_MSR_TXM_Msk   (0x1UL << CAN_MSR_TXM_Pos)
     
    #define CAN_MSR_TXM   CAN_MSR_TXM_Msk
     
    #define CAN_MSR_RXM_Pos   (9U)
     
    #define CAN_MSR_RXM_Msk   (0x1UL << CAN_MSR_RXM_Pos)
     
    #define CAN_MSR_RXM   CAN_MSR_RXM_Msk
     
    #define CAN_MSR_SAMP_Pos   (10U)
     
    #define CAN_MSR_SAMP_Msk   (0x1UL << CAN_MSR_SAMP_Pos)
     
    #define CAN_MSR_SAMP   CAN_MSR_SAMP_Msk
     
    #define CAN_MSR_RX_Pos   (11U)
     
    #define CAN_MSR_RX_Msk   (0x1UL << CAN_MSR_RX_Pos)
     
    #define CAN_MSR_RX   CAN_MSR_RX_Msk
     
    #define CAN_TSR_RQCP0_Pos   (0U)
     
    #define CAN_TSR_RQCP0_Msk   (0x1UL << CAN_TSR_RQCP0_Pos)
     
    #define CAN_TSR_RQCP0   CAN_TSR_RQCP0_Msk
     
    #define CAN_TSR_TXOK0_Pos   (1U)
     
    #define CAN_TSR_TXOK0_Msk   (0x1UL << CAN_TSR_TXOK0_Pos)
     
    #define CAN_TSR_TXOK0   CAN_TSR_TXOK0_Msk
     
    #define CAN_TSR_ALST0_Pos   (2U)
     
    #define CAN_TSR_ALST0_Msk   (0x1UL << CAN_TSR_ALST0_Pos)
     
    #define CAN_TSR_ALST0   CAN_TSR_ALST0_Msk
     
    #define CAN_TSR_TERR0_Pos   (3U)
     
    #define CAN_TSR_TERR0_Msk   (0x1UL << CAN_TSR_TERR0_Pos)
     
    #define CAN_TSR_TERR0   CAN_TSR_TERR0_Msk
     
    #define CAN_TSR_ABRQ0_Pos   (7U)
     
    #define CAN_TSR_ABRQ0_Msk   (0x1UL << CAN_TSR_ABRQ0_Pos)
     
    #define CAN_TSR_ABRQ0   CAN_TSR_ABRQ0_Msk
     
    #define CAN_TSR_RQCP1_Pos   (8U)
     
    #define CAN_TSR_RQCP1_Msk   (0x1UL << CAN_TSR_RQCP1_Pos)
     
    #define CAN_TSR_RQCP1   CAN_TSR_RQCP1_Msk
     
    #define CAN_TSR_TXOK1_Pos   (9U)
     
    #define CAN_TSR_TXOK1_Msk   (0x1UL << CAN_TSR_TXOK1_Pos)
     
    #define CAN_TSR_TXOK1   CAN_TSR_TXOK1_Msk
     
    #define CAN_TSR_ALST1_Pos   (10U)
     
    #define CAN_TSR_ALST1_Msk   (0x1UL << CAN_TSR_ALST1_Pos)
     
    #define CAN_TSR_ALST1   CAN_TSR_ALST1_Msk
     
    #define CAN_TSR_TERR1_Pos   (11U)
     
    #define CAN_TSR_TERR1_Msk   (0x1UL << CAN_TSR_TERR1_Pos)
     
    #define CAN_TSR_TERR1   CAN_TSR_TERR1_Msk
     
    #define CAN_TSR_ABRQ1_Pos   (15U)
     
    #define CAN_TSR_ABRQ1_Msk   (0x1UL << CAN_TSR_ABRQ1_Pos)
     
    #define CAN_TSR_ABRQ1   CAN_TSR_ABRQ1_Msk
     
    #define CAN_TSR_RQCP2_Pos   (16U)
     
    #define CAN_TSR_RQCP2_Msk   (0x1UL << CAN_TSR_RQCP2_Pos)
     
    #define CAN_TSR_RQCP2   CAN_TSR_RQCP2_Msk
     
    #define CAN_TSR_TXOK2_Pos   (17U)
     
    #define CAN_TSR_TXOK2_Msk   (0x1UL << CAN_TSR_TXOK2_Pos)
     
    #define CAN_TSR_TXOK2   CAN_TSR_TXOK2_Msk
     
    #define CAN_TSR_ALST2_Pos   (18U)
     
    #define CAN_TSR_ALST2_Msk   (0x1UL << CAN_TSR_ALST2_Pos)
     
    #define CAN_TSR_ALST2   CAN_TSR_ALST2_Msk
     
    #define CAN_TSR_TERR2_Pos   (19U)
     
    #define CAN_TSR_TERR2_Msk   (0x1UL << CAN_TSR_TERR2_Pos)
     
    #define CAN_TSR_TERR2   CAN_TSR_TERR2_Msk
     
    #define CAN_TSR_ABRQ2_Pos   (23U)
     
    #define CAN_TSR_ABRQ2_Msk   (0x1UL << CAN_TSR_ABRQ2_Pos)
     
    #define CAN_TSR_ABRQ2   CAN_TSR_ABRQ2_Msk
     
    #define CAN_TSR_CODE_Pos   (24U)
     
    #define CAN_TSR_CODE_Msk   (0x3UL << CAN_TSR_CODE_Pos)
     
    #define CAN_TSR_CODE   CAN_TSR_CODE_Msk
     
    #define CAN_TSR_TME_Pos   (26U)
     
    #define CAN_TSR_TME_Msk   (0x7UL << CAN_TSR_TME_Pos)
     
    #define CAN_TSR_TME   CAN_TSR_TME_Msk
     
    #define CAN_TSR_TME0_Pos   (26U)
     
    #define CAN_TSR_TME0_Msk   (0x1UL << CAN_TSR_TME0_Pos)
     
    #define CAN_TSR_TME0   CAN_TSR_TME0_Msk
     
    #define CAN_TSR_TME1_Pos   (27U)
     
    #define CAN_TSR_TME1_Msk   (0x1UL << CAN_TSR_TME1_Pos)
     
    #define CAN_TSR_TME1   CAN_TSR_TME1_Msk
     
    #define CAN_TSR_TME2_Pos   (28U)
     
    #define CAN_TSR_TME2_Msk   (0x1UL << CAN_TSR_TME2_Pos)
     
    #define CAN_TSR_TME2   CAN_TSR_TME2_Msk
     
    #define CAN_TSR_LOW_Pos   (29U)
     
    #define CAN_TSR_LOW_Msk   (0x7UL << CAN_TSR_LOW_Pos)
     
    #define CAN_TSR_LOW   CAN_TSR_LOW_Msk
     
    #define CAN_TSR_LOW0_Pos   (29U)
     
    #define CAN_TSR_LOW0_Msk   (0x1UL << CAN_TSR_LOW0_Pos)
     
    #define CAN_TSR_LOW0   CAN_TSR_LOW0_Msk
     
    #define CAN_TSR_LOW1_Pos   (30U)
     
    #define CAN_TSR_LOW1_Msk   (0x1UL << CAN_TSR_LOW1_Pos)
     
    #define CAN_TSR_LOW1   CAN_TSR_LOW1_Msk
     
    #define CAN_TSR_LOW2_Pos   (31U)
     
    #define CAN_TSR_LOW2_Msk   (0x1UL << CAN_TSR_LOW2_Pos)
     
    #define CAN_TSR_LOW2   CAN_TSR_LOW2_Msk
     
    #define CAN_RF0R_FMP0_Pos   (0U)
     
    #define CAN_RF0R_FMP0_Msk   (0x3UL << CAN_RF0R_FMP0_Pos)
     
    #define CAN_RF0R_FMP0   CAN_RF0R_FMP0_Msk
     
    #define CAN_RF0R_FULL0_Pos   (3U)
     
    #define CAN_RF0R_FULL0_Msk   (0x1UL << CAN_RF0R_FULL0_Pos)
     
    #define CAN_RF0R_FULL0   CAN_RF0R_FULL0_Msk
     
    #define CAN_RF0R_FOVR0_Pos   (4U)
     
    #define CAN_RF0R_FOVR0_Msk   (0x1UL << CAN_RF0R_FOVR0_Pos)
     
    #define CAN_RF0R_FOVR0   CAN_RF0R_FOVR0_Msk
     
    #define CAN_RF0R_RFOM0_Pos   (5U)
     
    #define CAN_RF0R_RFOM0_Msk   (0x1UL << CAN_RF0R_RFOM0_Pos)
     
    #define CAN_RF0R_RFOM0   CAN_RF0R_RFOM0_Msk
     
    #define CAN_RF1R_FMP1_Pos   (0U)
     
    #define CAN_RF1R_FMP1_Msk   (0x3UL << CAN_RF1R_FMP1_Pos)
     
    #define CAN_RF1R_FMP1   CAN_RF1R_FMP1_Msk
     
    #define CAN_RF1R_FULL1_Pos   (3U)
     
    #define CAN_RF1R_FULL1_Msk   (0x1UL << CAN_RF1R_FULL1_Pos)
     
    #define CAN_RF1R_FULL1   CAN_RF1R_FULL1_Msk
     
    #define CAN_RF1R_FOVR1_Pos   (4U)
     
    #define CAN_RF1R_FOVR1_Msk   (0x1UL << CAN_RF1R_FOVR1_Pos)
     
    #define CAN_RF1R_FOVR1   CAN_RF1R_FOVR1_Msk
     
    #define CAN_RF1R_RFOM1_Pos   (5U)
     
    #define CAN_RF1R_RFOM1_Msk   (0x1UL << CAN_RF1R_RFOM1_Pos)
     
    #define CAN_RF1R_RFOM1   CAN_RF1R_RFOM1_Msk
     
    #define CAN_IER_TMEIE_Pos   (0U)
     
    #define CAN_IER_TMEIE_Msk   (0x1UL << CAN_IER_TMEIE_Pos)
     
    #define CAN_IER_TMEIE   CAN_IER_TMEIE_Msk
     
    #define CAN_IER_FMPIE0_Pos   (1U)
     
    #define CAN_IER_FMPIE0_Msk   (0x1UL << CAN_IER_FMPIE0_Pos)
     
    #define CAN_IER_FMPIE0   CAN_IER_FMPIE0_Msk
     
    #define CAN_IER_FFIE0_Pos   (2U)
     
    #define CAN_IER_FFIE0_Msk   (0x1UL << CAN_IER_FFIE0_Pos)
     
    #define CAN_IER_FFIE0   CAN_IER_FFIE0_Msk
     
    #define CAN_IER_FOVIE0_Pos   (3U)
     
    #define CAN_IER_FOVIE0_Msk   (0x1UL << CAN_IER_FOVIE0_Pos)
     
    #define CAN_IER_FOVIE0   CAN_IER_FOVIE0_Msk
     
    #define CAN_IER_FMPIE1_Pos   (4U)
     
    #define CAN_IER_FMPIE1_Msk   (0x1UL << CAN_IER_FMPIE1_Pos)
     
    #define CAN_IER_FMPIE1   CAN_IER_FMPIE1_Msk
     
    #define CAN_IER_FFIE1_Pos   (5U)
     
    #define CAN_IER_FFIE1_Msk   (0x1UL << CAN_IER_FFIE1_Pos)
     
    #define CAN_IER_FFIE1   CAN_IER_FFIE1_Msk
     
    #define CAN_IER_FOVIE1_Pos   (6U)
     
    #define CAN_IER_FOVIE1_Msk   (0x1UL << CAN_IER_FOVIE1_Pos)
     
    #define CAN_IER_FOVIE1   CAN_IER_FOVIE1_Msk
     
    #define CAN_IER_EWGIE_Pos   (8U)
     
    #define CAN_IER_EWGIE_Msk   (0x1UL << CAN_IER_EWGIE_Pos)
     
    #define CAN_IER_EWGIE   CAN_IER_EWGIE_Msk
     
    #define CAN_IER_EPVIE_Pos   (9U)
     
    #define CAN_IER_EPVIE_Msk   (0x1UL << CAN_IER_EPVIE_Pos)
     
    #define CAN_IER_EPVIE   CAN_IER_EPVIE_Msk
     
    #define CAN_IER_BOFIE_Pos   (10U)
     
    #define CAN_IER_BOFIE_Msk   (0x1UL << CAN_IER_BOFIE_Pos)
     
    #define CAN_IER_BOFIE   CAN_IER_BOFIE_Msk
     
    #define CAN_IER_LECIE_Pos   (11U)
     
    #define CAN_IER_LECIE_Msk   (0x1UL << CAN_IER_LECIE_Pos)
     
    #define CAN_IER_LECIE   CAN_IER_LECIE_Msk
     
    #define CAN_IER_ERRIE_Pos   (15U)
     
    #define CAN_IER_ERRIE_Msk   (0x1UL << CAN_IER_ERRIE_Pos)
     
    #define CAN_IER_ERRIE   CAN_IER_ERRIE_Msk
     
    #define CAN_IER_WKUIE_Pos   (16U)
     
    #define CAN_IER_WKUIE_Msk   (0x1UL << CAN_IER_WKUIE_Pos)
     
    #define CAN_IER_WKUIE   CAN_IER_WKUIE_Msk
     
    #define CAN_IER_SLKIE_Pos   (17U)
     
    #define CAN_IER_SLKIE_Msk   (0x1UL << CAN_IER_SLKIE_Pos)
     
    #define CAN_IER_SLKIE   CAN_IER_SLKIE_Msk
     
    #define CAN_IER_EWGIE_Pos   (8U)
     
    #define CAN_ESR_EWGF_Pos   (0U)
     
    #define CAN_ESR_EWGF_Msk   (0x1UL << CAN_ESR_EWGF_Pos)
     
    #define CAN_ESR_EWGF   CAN_ESR_EWGF_Msk
     
    #define CAN_ESR_EPVF_Pos   (1U)
     
    #define CAN_ESR_EPVF_Msk   (0x1UL << CAN_ESR_EPVF_Pos)
     
    #define CAN_ESR_EPVF   CAN_ESR_EPVF_Msk
     
    #define CAN_ESR_BOFF_Pos   (2U)
     
    #define CAN_ESR_BOFF_Msk   (0x1UL << CAN_ESR_BOFF_Pos)
     
    #define CAN_ESR_BOFF   CAN_ESR_BOFF_Msk
     
    #define CAN_ESR_LEC_Pos   (4U)
     
    #define CAN_ESR_LEC_Msk   (0x7UL << CAN_ESR_LEC_Pos)
     
    #define CAN_ESR_LEC   CAN_ESR_LEC_Msk
     
    #define CAN_ESR_LEC_0   (0x1UL << CAN_ESR_LEC_Pos)
     
    #define CAN_ESR_LEC_1   (0x2UL << CAN_ESR_LEC_Pos)
     
    #define CAN_ESR_LEC_2   (0x4UL << CAN_ESR_LEC_Pos)
     
    #define CAN_ESR_TEC_Pos   (16U)
     
    #define CAN_ESR_TEC_Msk   (0xFFUL << CAN_ESR_TEC_Pos)
     
    #define CAN_ESR_TEC   CAN_ESR_TEC_Msk
     
    #define CAN_ESR_REC_Pos   (24U)
     
    #define CAN_ESR_REC_Msk   (0xFFUL << CAN_ESR_REC_Pos)
     
    #define CAN_ESR_REC   CAN_ESR_REC_Msk
     
    #define CAN_BTR_BRP_Pos   (0U)
     
    #define CAN_BTR_BRP_Msk   (0x3FFUL << CAN_BTR_BRP_Pos)
     
    #define CAN_BTR_BRP   CAN_BTR_BRP_Msk
     
    #define CAN_BTR_TS1_Pos   (16U)
     
    #define CAN_BTR_TS1_Msk   (0xFUL << CAN_BTR_TS1_Pos)
     
    #define CAN_BTR_TS1   CAN_BTR_TS1_Msk
     
    #define CAN_BTR_TS1_0   (0x1UL << CAN_BTR_TS1_Pos)
     
    #define CAN_BTR_TS1_1   (0x2UL << CAN_BTR_TS1_Pos)
     
    #define CAN_BTR_TS1_2   (0x4UL << CAN_BTR_TS1_Pos)
     
    #define CAN_BTR_TS1_3   (0x8UL << CAN_BTR_TS1_Pos)
     
    #define CAN_BTR_TS2_Pos   (20U)
     
    #define CAN_BTR_TS2_Msk   (0x7UL << CAN_BTR_TS2_Pos)
     
    #define CAN_BTR_TS2   CAN_BTR_TS2_Msk
     
    #define CAN_BTR_TS2_0   (0x1UL << CAN_BTR_TS2_Pos)
     
    #define CAN_BTR_TS2_1   (0x2UL << CAN_BTR_TS2_Pos)
     
    #define CAN_BTR_TS2_2   (0x4UL << CAN_BTR_TS2_Pos)
     
    #define CAN_BTR_SJW_Pos   (24U)
     
    #define CAN_BTR_SJW_Msk   (0x3UL << CAN_BTR_SJW_Pos)
     
    #define CAN_BTR_SJW   CAN_BTR_SJW_Msk
     
    #define CAN_BTR_SJW_0   (0x1UL << CAN_BTR_SJW_Pos)
     
    #define CAN_BTR_SJW_1   (0x2UL << CAN_BTR_SJW_Pos)
     
    #define CAN_BTR_LBKM_Pos   (30U)
     
    #define CAN_BTR_LBKM_Msk   (0x1UL << CAN_BTR_LBKM_Pos)
     
    #define CAN_BTR_LBKM   CAN_BTR_LBKM_Msk
     
    #define CAN_BTR_SILM_Pos   (31U)
     
    #define CAN_BTR_SILM_Msk   (0x1UL << CAN_BTR_SILM_Pos)
     
    #define CAN_BTR_SILM   CAN_BTR_SILM_Msk
     
    #define CAN_TI0R_TXRQ_Pos   (0U)
     
    #define CAN_TI0R_TXRQ_Msk   (0x1UL << CAN_TI0R_TXRQ_Pos)
     
    #define CAN_TI0R_TXRQ   CAN_TI0R_TXRQ_Msk
     
    #define CAN_TI0R_RTR_Pos   (1U)
     
    #define CAN_TI0R_RTR_Msk   (0x1UL << CAN_TI0R_RTR_Pos)
     
    #define CAN_TI0R_RTR   CAN_TI0R_RTR_Msk
     
    #define CAN_TI0R_IDE_Pos   (2U)
     
    #define CAN_TI0R_IDE_Msk   (0x1UL << CAN_TI0R_IDE_Pos)
     
    #define CAN_TI0R_IDE   CAN_TI0R_IDE_Msk
     
    #define CAN_TI0R_EXID_Pos   (3U)
     
    #define CAN_TI0R_EXID_Msk   (0x3FFFFUL << CAN_TI0R_EXID_Pos)
     
    #define CAN_TI0R_EXID   CAN_TI0R_EXID_Msk
     
    #define CAN_TI0R_STID_Pos   (21U)
     
    #define CAN_TI0R_STID_Msk   (0x7FFUL << CAN_TI0R_STID_Pos)
     
    #define CAN_TI0R_STID   CAN_TI0R_STID_Msk
     
    #define CAN_TDT0R_DLC_Pos   (0U)
     
    #define CAN_TDT0R_DLC_Msk   (0xFUL << CAN_TDT0R_DLC_Pos)
     
    #define CAN_TDT0R_DLC   CAN_TDT0R_DLC_Msk
     
    #define CAN_TDT0R_TGT_Pos   (8U)
     
    #define CAN_TDT0R_TGT_Msk   (0x1UL << CAN_TDT0R_TGT_Pos)
     
    #define CAN_TDT0R_TGT   CAN_TDT0R_TGT_Msk
     
    #define CAN_TDT0R_TIME_Pos   (16U)
     
    #define CAN_TDT0R_TIME_Msk   (0xFFFFUL << CAN_TDT0R_TIME_Pos)
     
    #define CAN_TDT0R_TIME   CAN_TDT0R_TIME_Msk
     
    #define CAN_TDL0R_DATA0_Pos   (0U)
     
    #define CAN_TDL0R_DATA0_Msk   (0xFFUL << CAN_TDL0R_DATA0_Pos)
     
    #define CAN_TDL0R_DATA0   CAN_TDL0R_DATA0_Msk
     
    #define CAN_TDL0R_DATA1_Pos   (8U)
     
    #define CAN_TDL0R_DATA1_Msk   (0xFFUL << CAN_TDL0R_DATA1_Pos)
     
    #define CAN_TDL0R_DATA1   CAN_TDL0R_DATA1_Msk
     
    #define CAN_TDL0R_DATA2_Pos   (16U)
     
    #define CAN_TDL0R_DATA2_Msk   (0xFFUL << CAN_TDL0R_DATA2_Pos)
     
    #define CAN_TDL0R_DATA2   CAN_TDL0R_DATA2_Msk
     
    #define CAN_TDL0R_DATA3_Pos   (24U)
     
    #define CAN_TDL0R_DATA3_Msk   (0xFFUL << CAN_TDL0R_DATA3_Pos)
     
    #define CAN_TDL0R_DATA3   CAN_TDL0R_DATA3_Msk
     
    #define CAN_TDH0R_DATA4_Pos   (0U)
     
    #define CAN_TDH0R_DATA4_Msk   (0xFFUL << CAN_TDH0R_DATA4_Pos)
     
    #define CAN_TDH0R_DATA4   CAN_TDH0R_DATA4_Msk
     
    #define CAN_TDH0R_DATA5_Pos   (8U)
     
    #define CAN_TDH0R_DATA5_Msk   (0xFFUL << CAN_TDH0R_DATA5_Pos)
     
    #define CAN_TDH0R_DATA5   CAN_TDH0R_DATA5_Msk
     
    #define CAN_TDH0R_DATA6_Pos   (16U)
     
    #define CAN_TDH0R_DATA6_Msk   (0xFFUL << CAN_TDH0R_DATA6_Pos)
     
    #define CAN_TDH0R_DATA6   CAN_TDH0R_DATA6_Msk
     
    #define CAN_TDH0R_DATA7_Pos   (24U)
     
    #define CAN_TDH0R_DATA7_Msk   (0xFFUL << CAN_TDH0R_DATA7_Pos)
     
    #define CAN_TDH0R_DATA7   CAN_TDH0R_DATA7_Msk
     
    #define CAN_TI1R_TXRQ_Pos   (0U)
     
    #define CAN_TI1R_TXRQ_Msk   (0x1UL << CAN_TI1R_TXRQ_Pos)
     
    #define CAN_TI1R_TXRQ   CAN_TI1R_TXRQ_Msk
     
    #define CAN_TI1R_RTR_Pos   (1U)
     
    #define CAN_TI1R_RTR_Msk   (0x1UL << CAN_TI1R_RTR_Pos)
     
    #define CAN_TI1R_RTR   CAN_TI1R_RTR_Msk
     
    #define CAN_TI1R_IDE_Pos   (2U)
     
    #define CAN_TI1R_IDE_Msk   (0x1UL << CAN_TI1R_IDE_Pos)
     
    #define CAN_TI1R_IDE   CAN_TI1R_IDE_Msk
     
    #define CAN_TI1R_EXID_Pos   (3U)
     
    #define CAN_TI1R_EXID_Msk   (0x3FFFFUL << CAN_TI1R_EXID_Pos)
     
    #define CAN_TI1R_EXID   CAN_TI1R_EXID_Msk
     
    #define CAN_TI1R_STID_Pos   (21U)
     
    #define CAN_TI1R_STID_Msk   (0x7FFUL << CAN_TI1R_STID_Pos)
     
    #define CAN_TI1R_STID   CAN_TI1R_STID_Msk
     
    #define CAN_TDT1R_DLC_Pos   (0U)
     
    #define CAN_TDT1R_DLC_Msk   (0xFUL << CAN_TDT1R_DLC_Pos)
     
    #define CAN_TDT1R_DLC   CAN_TDT1R_DLC_Msk
     
    #define CAN_TDT1R_TGT_Pos   (8U)
     
    #define CAN_TDT1R_TGT_Msk   (0x1UL << CAN_TDT1R_TGT_Pos)
     
    #define CAN_TDT1R_TGT   CAN_TDT1R_TGT_Msk
     
    #define CAN_TDT1R_TIME_Pos   (16U)
     
    #define CAN_TDT1R_TIME_Msk   (0xFFFFUL << CAN_TDT1R_TIME_Pos)
     
    #define CAN_TDT1R_TIME   CAN_TDT1R_TIME_Msk
     
    #define CAN_TDL1R_DATA0_Pos   (0U)
     
    #define CAN_TDL1R_DATA0_Msk   (0xFFUL << CAN_TDL1R_DATA0_Pos)
     
    #define CAN_TDL1R_DATA0   CAN_TDL1R_DATA0_Msk
     
    #define CAN_TDL1R_DATA1_Pos   (8U)
     
    #define CAN_TDL1R_DATA1_Msk   (0xFFUL << CAN_TDL1R_DATA1_Pos)
     
    #define CAN_TDL1R_DATA1   CAN_TDL1R_DATA1_Msk
     
    #define CAN_TDL1R_DATA2_Pos   (16U)
     
    #define CAN_TDL1R_DATA2_Msk   (0xFFUL << CAN_TDL1R_DATA2_Pos)
     
    #define CAN_TDL1R_DATA2   CAN_TDL1R_DATA2_Msk
     
    #define CAN_TDL1R_DATA3_Pos   (24U)
     
    #define CAN_TDL1R_DATA3_Msk   (0xFFUL << CAN_TDL1R_DATA3_Pos)
     
    #define CAN_TDL1R_DATA3   CAN_TDL1R_DATA3_Msk
     
    #define CAN_TDH1R_DATA4_Pos   (0U)
     
    #define CAN_TDH1R_DATA4_Msk   (0xFFUL << CAN_TDH1R_DATA4_Pos)
     
    #define CAN_TDH1R_DATA4   CAN_TDH1R_DATA4_Msk
     
    #define CAN_TDH1R_DATA5_Pos   (8U)
     
    #define CAN_TDH1R_DATA5_Msk   (0xFFUL << CAN_TDH1R_DATA5_Pos)
     
    #define CAN_TDH1R_DATA5   CAN_TDH1R_DATA5_Msk
     
    #define CAN_TDH1R_DATA6_Pos   (16U)
     
    #define CAN_TDH1R_DATA6_Msk   (0xFFUL << CAN_TDH1R_DATA6_Pos)
     
    #define CAN_TDH1R_DATA6   CAN_TDH1R_DATA6_Msk
     
    #define CAN_TDH1R_DATA7_Pos   (24U)
     
    #define CAN_TDH1R_DATA7_Msk   (0xFFUL << CAN_TDH1R_DATA7_Pos)
     
    #define CAN_TDH1R_DATA7   CAN_TDH1R_DATA7_Msk
     
    #define CAN_TI2R_TXRQ_Pos   (0U)
     
    #define CAN_TI2R_TXRQ_Msk   (0x1UL << CAN_TI2R_TXRQ_Pos)
     
    #define CAN_TI2R_TXRQ   CAN_TI2R_TXRQ_Msk
     
    #define CAN_TI2R_RTR_Pos   (1U)
     
    #define CAN_TI2R_RTR_Msk   (0x1UL << CAN_TI2R_RTR_Pos)
     
    #define CAN_TI2R_RTR   CAN_TI2R_RTR_Msk
     
    #define CAN_TI2R_IDE_Pos   (2U)
     
    #define CAN_TI2R_IDE_Msk   (0x1UL << CAN_TI2R_IDE_Pos)
     
    #define CAN_TI2R_IDE   CAN_TI2R_IDE_Msk
     
    #define CAN_TI2R_EXID_Pos   (3U)
     
    #define CAN_TI2R_EXID_Msk   (0x3FFFFUL << CAN_TI2R_EXID_Pos)
     
    #define CAN_TI2R_EXID   CAN_TI2R_EXID_Msk
     
    #define CAN_TI2R_STID_Pos   (21U)
     
    #define CAN_TI2R_STID_Msk   (0x7FFUL << CAN_TI2R_STID_Pos)
     
    #define CAN_TI2R_STID   CAN_TI2R_STID_Msk
     
    #define CAN_TDT2R_DLC_Pos   (0U)
     
    #define CAN_TDT2R_DLC_Msk   (0xFUL << CAN_TDT2R_DLC_Pos)
     
    #define CAN_TDT2R_DLC   CAN_TDT2R_DLC_Msk
     
    #define CAN_TDT2R_TGT_Pos   (8U)
     
    #define CAN_TDT2R_TGT_Msk   (0x1UL << CAN_TDT2R_TGT_Pos)
     
    #define CAN_TDT2R_TGT   CAN_TDT2R_TGT_Msk
     
    #define CAN_TDT2R_TIME_Pos   (16U)
     
    #define CAN_TDT2R_TIME_Msk   (0xFFFFUL << CAN_TDT2R_TIME_Pos)
     
    #define CAN_TDT2R_TIME   CAN_TDT2R_TIME_Msk
     
    #define CAN_TDL2R_DATA0_Pos   (0U)
     
    #define CAN_TDL2R_DATA0_Msk   (0xFFUL << CAN_TDL2R_DATA0_Pos)
     
    #define CAN_TDL2R_DATA0   CAN_TDL2R_DATA0_Msk
     
    #define CAN_TDL2R_DATA1_Pos   (8U)
     
    #define CAN_TDL2R_DATA1_Msk   (0xFFUL << CAN_TDL2R_DATA1_Pos)
     
    #define CAN_TDL2R_DATA1   CAN_TDL2R_DATA1_Msk
     
    #define CAN_TDL2R_DATA2_Pos   (16U)
     
    #define CAN_TDL2R_DATA2_Msk   (0xFFUL << CAN_TDL2R_DATA2_Pos)
     
    #define CAN_TDL2R_DATA2   CAN_TDL2R_DATA2_Msk
     
    #define CAN_TDL2R_DATA3_Pos   (24U)
     
    #define CAN_TDL2R_DATA3_Msk   (0xFFUL << CAN_TDL2R_DATA3_Pos)
     
    #define CAN_TDL2R_DATA3   CAN_TDL2R_DATA3_Msk
     
    #define CAN_TDH2R_DATA4_Pos   (0U)
     
    #define CAN_TDH2R_DATA4_Msk   (0xFFUL << CAN_TDH2R_DATA4_Pos)
     
    #define CAN_TDH2R_DATA4   CAN_TDH2R_DATA4_Msk
     
    #define CAN_TDH2R_DATA5_Pos   (8U)
     
    #define CAN_TDH2R_DATA5_Msk   (0xFFUL << CAN_TDH2R_DATA5_Pos)
     
    #define CAN_TDH2R_DATA5   CAN_TDH2R_DATA5_Msk
     
    #define CAN_TDH2R_DATA6_Pos   (16U)
     
    #define CAN_TDH2R_DATA6_Msk   (0xFFUL << CAN_TDH2R_DATA6_Pos)
     
    #define CAN_TDH2R_DATA6   CAN_TDH2R_DATA6_Msk
     
    #define CAN_TDH2R_DATA7_Pos   (24U)
     
    #define CAN_TDH2R_DATA7_Msk   (0xFFUL << CAN_TDH2R_DATA7_Pos)
     
    #define CAN_TDH2R_DATA7   CAN_TDH2R_DATA7_Msk
     
    #define CAN_RI0R_RTR_Pos   (1U)
     
    #define CAN_RI0R_RTR_Msk   (0x1UL << CAN_RI0R_RTR_Pos)
     
    #define CAN_RI0R_RTR   CAN_RI0R_RTR_Msk
     
    #define CAN_RI0R_IDE_Pos   (2U)
     
    #define CAN_RI0R_IDE_Msk   (0x1UL << CAN_RI0R_IDE_Pos)
     
    #define CAN_RI0R_IDE   CAN_RI0R_IDE_Msk
     
    #define CAN_RI0R_EXID_Pos   (3U)
     
    #define CAN_RI0R_EXID_Msk   (0x3FFFFUL << CAN_RI0R_EXID_Pos)
     
    #define CAN_RI0R_EXID   CAN_RI0R_EXID_Msk
     
    #define CAN_RI0R_STID_Pos   (21U)
     
    #define CAN_RI0R_STID_Msk   (0x7FFUL << CAN_RI0R_STID_Pos)
     
    #define CAN_RI0R_STID   CAN_RI0R_STID_Msk
     
    #define CAN_RDT0R_DLC_Pos   (0U)
     
    #define CAN_RDT0R_DLC_Msk   (0xFUL << CAN_RDT0R_DLC_Pos)
     
    #define CAN_RDT0R_DLC   CAN_RDT0R_DLC_Msk
     
    #define CAN_RDT0R_FMI_Pos   (8U)
     
    #define CAN_RDT0R_FMI_Msk   (0xFFUL << CAN_RDT0R_FMI_Pos)
     
    #define CAN_RDT0R_FMI   CAN_RDT0R_FMI_Msk
     
    #define CAN_RDT0R_TIME_Pos   (16U)
     
    #define CAN_RDT0R_TIME_Msk   (0xFFFFUL << CAN_RDT0R_TIME_Pos)
     
    #define CAN_RDT0R_TIME   CAN_RDT0R_TIME_Msk
     
    #define CAN_RDL0R_DATA0_Pos   (0U)
     
    #define CAN_RDL0R_DATA0_Msk   (0xFFUL << CAN_RDL0R_DATA0_Pos)
     
    #define CAN_RDL0R_DATA0   CAN_RDL0R_DATA0_Msk
     
    #define CAN_RDL0R_DATA1_Pos   (8U)
     
    #define CAN_RDL0R_DATA1_Msk   (0xFFUL << CAN_RDL0R_DATA1_Pos)
     
    #define CAN_RDL0R_DATA1   CAN_RDL0R_DATA1_Msk
     
    #define CAN_RDL0R_DATA2_Pos   (16U)
     
    #define CAN_RDL0R_DATA2_Msk   (0xFFUL << CAN_RDL0R_DATA2_Pos)
     
    #define CAN_RDL0R_DATA2   CAN_RDL0R_DATA2_Msk
     
    #define CAN_RDL0R_DATA3_Pos   (24U)
     
    #define CAN_RDL0R_DATA3_Msk   (0xFFUL << CAN_RDL0R_DATA3_Pos)
     
    #define CAN_RDL0R_DATA3   CAN_RDL0R_DATA3_Msk
     
    #define CAN_RDH0R_DATA4_Pos   (0U)
     
    #define CAN_RDH0R_DATA4_Msk   (0xFFUL << CAN_RDH0R_DATA4_Pos)
     
    #define CAN_RDH0R_DATA4   CAN_RDH0R_DATA4_Msk
     
    #define CAN_RDH0R_DATA5_Pos   (8U)
     
    #define CAN_RDH0R_DATA5_Msk   (0xFFUL << CAN_RDH0R_DATA5_Pos)
     
    #define CAN_RDH0R_DATA5   CAN_RDH0R_DATA5_Msk
     
    #define CAN_RDH0R_DATA6_Pos   (16U)
     
    #define CAN_RDH0R_DATA6_Msk   (0xFFUL << CAN_RDH0R_DATA6_Pos)
     
    #define CAN_RDH0R_DATA6   CAN_RDH0R_DATA6_Msk
     
    #define CAN_RDH0R_DATA7_Pos   (24U)
     
    #define CAN_RDH0R_DATA7_Msk   (0xFFUL << CAN_RDH0R_DATA7_Pos)
     
    #define CAN_RDH0R_DATA7   CAN_RDH0R_DATA7_Msk
     
    #define CAN_RI1R_RTR_Pos   (1U)
     
    #define CAN_RI1R_RTR_Msk   (0x1UL << CAN_RI1R_RTR_Pos)
     
    #define CAN_RI1R_RTR   CAN_RI1R_RTR_Msk
     
    #define CAN_RI1R_IDE_Pos   (2U)
     
    #define CAN_RI1R_IDE_Msk   (0x1UL << CAN_RI1R_IDE_Pos)
     
    #define CAN_RI1R_IDE   CAN_RI1R_IDE_Msk
     
    #define CAN_RI1R_EXID_Pos   (3U)
     
    #define CAN_RI1R_EXID_Msk   (0x3FFFFUL << CAN_RI1R_EXID_Pos)
     
    #define CAN_RI1R_EXID   CAN_RI1R_EXID_Msk
     
    #define CAN_RI1R_STID_Pos   (21U)
     
    #define CAN_RI1R_STID_Msk   (0x7FFUL << CAN_RI1R_STID_Pos)
     
    #define CAN_RI1R_STID   CAN_RI1R_STID_Msk
     
    #define CAN_RDT1R_DLC_Pos   (0U)
     
    #define CAN_RDT1R_DLC_Msk   (0xFUL << CAN_RDT1R_DLC_Pos)
     
    #define CAN_RDT1R_DLC   CAN_RDT1R_DLC_Msk
     
    #define CAN_RDT1R_FMI_Pos   (8U)
     
    #define CAN_RDT1R_FMI_Msk   (0xFFUL << CAN_RDT1R_FMI_Pos)
     
    #define CAN_RDT1R_FMI   CAN_RDT1R_FMI_Msk
     
    #define CAN_RDT1R_TIME_Pos   (16U)
     
    #define CAN_RDT1R_TIME_Msk   (0xFFFFUL << CAN_RDT1R_TIME_Pos)
     
    #define CAN_RDT1R_TIME   CAN_RDT1R_TIME_Msk
     
    #define CAN_RDL1R_DATA0_Pos   (0U)
     
    #define CAN_RDL1R_DATA0_Msk   (0xFFUL << CAN_RDL1R_DATA0_Pos)
     
    #define CAN_RDL1R_DATA0   CAN_RDL1R_DATA0_Msk
     
    #define CAN_RDL1R_DATA1_Pos   (8U)
     
    #define CAN_RDL1R_DATA1_Msk   (0xFFUL << CAN_RDL1R_DATA1_Pos)
     
    #define CAN_RDL1R_DATA1   CAN_RDL1R_DATA1_Msk
     
    #define CAN_RDL1R_DATA2_Pos   (16U)
     
    #define CAN_RDL1R_DATA2_Msk   (0xFFUL << CAN_RDL1R_DATA2_Pos)
     
    #define CAN_RDL1R_DATA2   CAN_RDL1R_DATA2_Msk
     
    #define CAN_RDL1R_DATA3_Pos   (24U)
     
    #define CAN_RDL1R_DATA3_Msk   (0xFFUL << CAN_RDL1R_DATA3_Pos)
     
    #define CAN_RDL1R_DATA3   CAN_RDL1R_DATA3_Msk
     
    #define CAN_RDH1R_DATA4_Pos   (0U)
     
    #define CAN_RDH1R_DATA4_Msk   (0xFFUL << CAN_RDH1R_DATA4_Pos)
     
    #define CAN_RDH1R_DATA4   CAN_RDH1R_DATA4_Msk
     
    #define CAN_RDH1R_DATA5_Pos   (8U)
     
    #define CAN_RDH1R_DATA5_Msk   (0xFFUL << CAN_RDH1R_DATA5_Pos)
     
    #define CAN_RDH1R_DATA5   CAN_RDH1R_DATA5_Msk
     
    #define CAN_RDH1R_DATA6_Pos   (16U)
     
    #define CAN_RDH1R_DATA6_Msk   (0xFFUL << CAN_RDH1R_DATA6_Pos)
     
    #define CAN_RDH1R_DATA6   CAN_RDH1R_DATA6_Msk
     
    #define CAN_RDH1R_DATA7_Pos   (24U)
     
    #define CAN_RDH1R_DATA7_Msk   (0xFFUL << CAN_RDH1R_DATA7_Pos)
     
    #define CAN_RDH1R_DATA7   CAN_RDH1R_DATA7_Msk
     
    #define CAN_FMR_FINIT_Pos   (0U)
     
    #define CAN_FMR_FINIT_Msk   (0x1UL << CAN_FMR_FINIT_Pos)
     
    #define CAN_FMR_FINIT   CAN_FMR_FINIT_Msk
     
    #define CAN_FMR_CAN2SB_Pos   (8U)
     
    #define CAN_FMR_CAN2SB_Msk   (0x3FUL << CAN_FMR_CAN2SB_Pos)
     
    #define CAN_FMR_CAN2SB   CAN_FMR_CAN2SB_Msk
     
    #define CAN_FM1R_FBM_Pos   (0U)
     
    #define CAN_FM1R_FBM_Msk   (0xFFFFFFFUL << CAN_FM1R_FBM_Pos)
     
    #define CAN_FM1R_FBM   CAN_FM1R_FBM_Msk
     
    #define CAN_FM1R_FBM0_Pos   (0U)
     
    #define CAN_FM1R_FBM0_Msk   (0x1UL << CAN_FM1R_FBM0_Pos)
     
    #define CAN_FM1R_FBM0   CAN_FM1R_FBM0_Msk
     
    #define CAN_FM1R_FBM1_Pos   (1U)
     
    #define CAN_FM1R_FBM1_Msk   (0x1UL << CAN_FM1R_FBM1_Pos)
     
    #define CAN_FM1R_FBM1   CAN_FM1R_FBM1_Msk
     
    #define CAN_FM1R_FBM2_Pos   (2U)
     
    #define CAN_FM1R_FBM2_Msk   (0x1UL << CAN_FM1R_FBM2_Pos)
     
    #define CAN_FM1R_FBM2   CAN_FM1R_FBM2_Msk
     
    #define CAN_FM1R_FBM3_Pos   (3U)
     
    #define CAN_FM1R_FBM3_Msk   (0x1UL << CAN_FM1R_FBM3_Pos)
     
    #define CAN_FM1R_FBM3   CAN_FM1R_FBM3_Msk
     
    #define CAN_FM1R_FBM4_Pos   (4U)
     
    #define CAN_FM1R_FBM4_Msk   (0x1UL << CAN_FM1R_FBM4_Pos)
     
    #define CAN_FM1R_FBM4   CAN_FM1R_FBM4_Msk
     
    #define CAN_FM1R_FBM5_Pos   (5U)
     
    #define CAN_FM1R_FBM5_Msk   (0x1UL << CAN_FM1R_FBM5_Pos)
     
    #define CAN_FM1R_FBM5   CAN_FM1R_FBM5_Msk
     
    #define CAN_FM1R_FBM6_Pos   (6U)
     
    #define CAN_FM1R_FBM6_Msk   (0x1UL << CAN_FM1R_FBM6_Pos)
     
    #define CAN_FM1R_FBM6   CAN_FM1R_FBM6_Msk
     
    #define CAN_FM1R_FBM7_Pos   (7U)
     
    #define CAN_FM1R_FBM7_Msk   (0x1UL << CAN_FM1R_FBM7_Pos)
     
    #define CAN_FM1R_FBM7   CAN_FM1R_FBM7_Msk
     
    #define CAN_FM1R_FBM8_Pos   (8U)
     
    #define CAN_FM1R_FBM8_Msk   (0x1UL << CAN_FM1R_FBM8_Pos)
     
    #define CAN_FM1R_FBM8   CAN_FM1R_FBM8_Msk
     
    #define CAN_FM1R_FBM9_Pos   (9U)
     
    #define CAN_FM1R_FBM9_Msk   (0x1UL << CAN_FM1R_FBM9_Pos)
     
    #define CAN_FM1R_FBM9   CAN_FM1R_FBM9_Msk
     
    #define CAN_FM1R_FBM10_Pos   (10U)
     
    #define CAN_FM1R_FBM10_Msk   (0x1UL << CAN_FM1R_FBM10_Pos)
     
    #define CAN_FM1R_FBM10   CAN_FM1R_FBM10_Msk
     
    #define CAN_FM1R_FBM11_Pos   (11U)
     
    #define CAN_FM1R_FBM11_Msk   (0x1UL << CAN_FM1R_FBM11_Pos)
     
    #define CAN_FM1R_FBM11   CAN_FM1R_FBM11_Msk
     
    #define CAN_FM1R_FBM12_Pos   (12U)
     
    #define CAN_FM1R_FBM12_Msk   (0x1UL << CAN_FM1R_FBM12_Pos)
     
    #define CAN_FM1R_FBM12   CAN_FM1R_FBM12_Msk
     
    #define CAN_FM1R_FBM13_Pos   (13U)
     
    #define CAN_FM1R_FBM13_Msk   (0x1UL << CAN_FM1R_FBM13_Pos)
     
    #define CAN_FM1R_FBM13   CAN_FM1R_FBM13_Msk
     
    #define CAN_FM1R_FBM14_Pos   (14U)
     
    #define CAN_FM1R_FBM14_Msk   (0x1UL << CAN_FM1R_FBM14_Pos)
     
    #define CAN_FM1R_FBM14   CAN_FM1R_FBM14_Msk
     
    #define CAN_FM1R_FBM15_Pos   (15U)
     
    #define CAN_FM1R_FBM15_Msk   (0x1UL << CAN_FM1R_FBM15_Pos)
     
    #define CAN_FM1R_FBM15   CAN_FM1R_FBM15_Msk
     
    #define CAN_FM1R_FBM16_Pos   (16U)
     
    #define CAN_FM1R_FBM16_Msk   (0x1UL << CAN_FM1R_FBM16_Pos)
     
    #define CAN_FM1R_FBM16   CAN_FM1R_FBM16_Msk
     
    #define CAN_FM1R_FBM17_Pos   (17U)
     
    #define CAN_FM1R_FBM17_Msk   (0x1UL << CAN_FM1R_FBM17_Pos)
     
    #define CAN_FM1R_FBM17   CAN_FM1R_FBM17_Msk
     
    #define CAN_FM1R_FBM18_Pos   (18U)
     
    #define CAN_FM1R_FBM18_Msk   (0x1UL << CAN_FM1R_FBM18_Pos)
     
    #define CAN_FM1R_FBM18   CAN_FM1R_FBM18_Msk
     
    #define CAN_FM1R_FBM19_Pos   (19U)
     
    #define CAN_FM1R_FBM19_Msk   (0x1UL << CAN_FM1R_FBM19_Pos)
     
    #define CAN_FM1R_FBM19   CAN_FM1R_FBM19_Msk
     
    #define CAN_FM1R_FBM20_Pos   (20U)
     
    #define CAN_FM1R_FBM20_Msk   (0x1UL << CAN_FM1R_FBM20_Pos)
     
    #define CAN_FM1R_FBM20   CAN_FM1R_FBM20_Msk
     
    #define CAN_FM1R_FBM21_Pos   (21U)
     
    #define CAN_FM1R_FBM21_Msk   (0x1UL << CAN_FM1R_FBM21_Pos)
     
    #define CAN_FM1R_FBM21   CAN_FM1R_FBM21_Msk
     
    #define CAN_FM1R_FBM22_Pos   (22U)
     
    #define CAN_FM1R_FBM22_Msk   (0x1UL << CAN_FM1R_FBM22_Pos)
     
    #define CAN_FM1R_FBM22   CAN_FM1R_FBM22_Msk
     
    #define CAN_FM1R_FBM23_Pos   (23U)
     
    #define CAN_FM1R_FBM23_Msk   (0x1UL << CAN_FM1R_FBM23_Pos)
     
    #define CAN_FM1R_FBM23   CAN_FM1R_FBM23_Msk
     
    #define CAN_FM1R_FBM24_Pos   (24U)
     
    #define CAN_FM1R_FBM24_Msk   (0x1UL << CAN_FM1R_FBM24_Pos)
     
    #define CAN_FM1R_FBM24   CAN_FM1R_FBM24_Msk
     
    #define CAN_FM1R_FBM25_Pos   (25U)
     
    #define CAN_FM1R_FBM25_Msk   (0x1UL << CAN_FM1R_FBM25_Pos)
     
    #define CAN_FM1R_FBM25   CAN_FM1R_FBM25_Msk
     
    #define CAN_FM1R_FBM26_Pos   (26U)
     
    #define CAN_FM1R_FBM26_Msk   (0x1UL << CAN_FM1R_FBM26_Pos)
     
    #define CAN_FM1R_FBM26   CAN_FM1R_FBM26_Msk
     
    #define CAN_FM1R_FBM27_Pos   (27U)
     
    #define CAN_FM1R_FBM27_Msk   (0x1UL << CAN_FM1R_FBM27_Pos)
     
    #define CAN_FM1R_FBM27   CAN_FM1R_FBM27_Msk
     
    #define CAN_FS1R_FSC_Pos   (0U)
     
    #define CAN_FS1R_FSC_Msk   (0xFFFFFFFUL << CAN_FS1R_FSC_Pos)
     
    #define CAN_FS1R_FSC   CAN_FS1R_FSC_Msk
     
    #define CAN_FS1R_FSC0_Pos   (0U)
     
    #define CAN_FS1R_FSC0_Msk   (0x1UL << CAN_FS1R_FSC0_Pos)
     
    #define CAN_FS1R_FSC0   CAN_FS1R_FSC0_Msk
     
    #define CAN_FS1R_FSC1_Pos   (1U)
     
    #define CAN_FS1R_FSC1_Msk   (0x1UL << CAN_FS1R_FSC1_Pos)
     
    #define CAN_FS1R_FSC1   CAN_FS1R_FSC1_Msk
     
    #define CAN_FS1R_FSC2_Pos   (2U)
     
    #define CAN_FS1R_FSC2_Msk   (0x1UL << CAN_FS1R_FSC2_Pos)
     
    #define CAN_FS1R_FSC2   CAN_FS1R_FSC2_Msk
     
    #define CAN_FS1R_FSC3_Pos   (3U)
     
    #define CAN_FS1R_FSC3_Msk   (0x1UL << CAN_FS1R_FSC3_Pos)
     
    #define CAN_FS1R_FSC3   CAN_FS1R_FSC3_Msk
     
    #define CAN_FS1R_FSC4_Pos   (4U)
     
    #define CAN_FS1R_FSC4_Msk   (0x1UL << CAN_FS1R_FSC4_Pos)
     
    #define CAN_FS1R_FSC4   CAN_FS1R_FSC4_Msk
     
    #define CAN_FS1R_FSC5_Pos   (5U)
     
    #define CAN_FS1R_FSC5_Msk   (0x1UL << CAN_FS1R_FSC5_Pos)
     
    #define CAN_FS1R_FSC5   CAN_FS1R_FSC5_Msk
     
    #define CAN_FS1R_FSC6_Pos   (6U)
     
    #define CAN_FS1R_FSC6_Msk   (0x1UL << CAN_FS1R_FSC6_Pos)
     
    #define CAN_FS1R_FSC6   CAN_FS1R_FSC6_Msk
     
    #define CAN_FS1R_FSC7_Pos   (7U)
     
    #define CAN_FS1R_FSC7_Msk   (0x1UL << CAN_FS1R_FSC7_Pos)
     
    #define CAN_FS1R_FSC7   CAN_FS1R_FSC7_Msk
     
    #define CAN_FS1R_FSC8_Pos   (8U)
     
    #define CAN_FS1R_FSC8_Msk   (0x1UL << CAN_FS1R_FSC8_Pos)
     
    #define CAN_FS1R_FSC8   CAN_FS1R_FSC8_Msk
     
    #define CAN_FS1R_FSC9_Pos   (9U)
     
    #define CAN_FS1R_FSC9_Msk   (0x1UL << CAN_FS1R_FSC9_Pos)
     
    #define CAN_FS1R_FSC9   CAN_FS1R_FSC9_Msk
     
    #define CAN_FS1R_FSC10_Pos   (10U)
     
    #define CAN_FS1R_FSC10_Msk   (0x1UL << CAN_FS1R_FSC10_Pos)
     
    #define CAN_FS1R_FSC10   CAN_FS1R_FSC10_Msk
     
    #define CAN_FS1R_FSC11_Pos   (11U)
     
    #define CAN_FS1R_FSC11_Msk   (0x1UL << CAN_FS1R_FSC11_Pos)
     
    #define CAN_FS1R_FSC11   CAN_FS1R_FSC11_Msk
     
    #define CAN_FS1R_FSC12_Pos   (12U)
     
    #define CAN_FS1R_FSC12_Msk   (0x1UL << CAN_FS1R_FSC12_Pos)
     
    #define CAN_FS1R_FSC12   CAN_FS1R_FSC12_Msk
     
    #define CAN_FS1R_FSC13_Pos   (13U)
     
    #define CAN_FS1R_FSC13_Msk   (0x1UL << CAN_FS1R_FSC13_Pos)
     
    #define CAN_FS1R_FSC13   CAN_FS1R_FSC13_Msk
     
    #define CAN_FS1R_FSC14_Pos   (14U)
     
    #define CAN_FS1R_FSC14_Msk   (0x1UL << CAN_FS1R_FSC14_Pos)
     
    #define CAN_FS1R_FSC14   CAN_FS1R_FSC14_Msk
     
    #define CAN_FS1R_FSC15_Pos   (15U)
     
    #define CAN_FS1R_FSC15_Msk   (0x1UL << CAN_FS1R_FSC15_Pos)
     
    #define CAN_FS1R_FSC15   CAN_FS1R_FSC15_Msk
     
    #define CAN_FS1R_FSC16_Pos   (16U)
     
    #define CAN_FS1R_FSC16_Msk   (0x1UL << CAN_FS1R_FSC16_Pos)
     
    #define CAN_FS1R_FSC16   CAN_FS1R_FSC16_Msk
     
    #define CAN_FS1R_FSC17_Pos   (17U)
     
    #define CAN_FS1R_FSC17_Msk   (0x1UL << CAN_FS1R_FSC17_Pos)
     
    #define CAN_FS1R_FSC17   CAN_FS1R_FSC17_Msk
     
    #define CAN_FS1R_FSC18_Pos   (18U)
     
    #define CAN_FS1R_FSC18_Msk   (0x1UL << CAN_FS1R_FSC18_Pos)
     
    #define CAN_FS1R_FSC18   CAN_FS1R_FSC18_Msk
     
    #define CAN_FS1R_FSC19_Pos   (19U)
     
    #define CAN_FS1R_FSC19_Msk   (0x1UL << CAN_FS1R_FSC19_Pos)
     
    #define CAN_FS1R_FSC19   CAN_FS1R_FSC19_Msk
     
    #define CAN_FS1R_FSC20_Pos   (20U)
     
    #define CAN_FS1R_FSC20_Msk   (0x1UL << CAN_FS1R_FSC20_Pos)
     
    #define CAN_FS1R_FSC20   CAN_FS1R_FSC20_Msk
     
    #define CAN_FS1R_FSC21_Pos   (21U)
     
    #define CAN_FS1R_FSC21_Msk   (0x1UL << CAN_FS1R_FSC21_Pos)
     
    #define CAN_FS1R_FSC21   CAN_FS1R_FSC21_Msk
     
    #define CAN_FS1R_FSC22_Pos   (22U)
     
    #define CAN_FS1R_FSC22_Msk   (0x1UL << CAN_FS1R_FSC22_Pos)
     
    #define CAN_FS1R_FSC22   CAN_FS1R_FSC22_Msk
     
    #define CAN_FS1R_FSC23_Pos   (23U)
     
    #define CAN_FS1R_FSC23_Msk   (0x1UL << CAN_FS1R_FSC23_Pos)
     
    #define CAN_FS1R_FSC23   CAN_FS1R_FSC23_Msk
     
    #define CAN_FS1R_FSC24_Pos   (24U)
     
    #define CAN_FS1R_FSC24_Msk   (0x1UL << CAN_FS1R_FSC24_Pos)
     
    #define CAN_FS1R_FSC24   CAN_FS1R_FSC24_Msk
     
    #define CAN_FS1R_FSC25_Pos   (25U)
     
    #define CAN_FS1R_FSC25_Msk   (0x1UL << CAN_FS1R_FSC25_Pos)
     
    #define CAN_FS1R_FSC25   CAN_FS1R_FSC25_Msk
     
    #define CAN_FS1R_FSC26_Pos   (26U)
     
    #define CAN_FS1R_FSC26_Msk   (0x1UL << CAN_FS1R_FSC26_Pos)
     
    #define CAN_FS1R_FSC26   CAN_FS1R_FSC26_Msk
     
    #define CAN_FS1R_FSC27_Pos   (27U)
     
    #define CAN_FS1R_FSC27_Msk   (0x1UL << CAN_FS1R_FSC27_Pos)
     
    #define CAN_FS1R_FSC27   CAN_FS1R_FSC27_Msk
     
    #define CAN_FFA1R_FFA_Pos   (0U)
     
    #define CAN_FFA1R_FFA_Msk   (0xFFFFFFFUL << CAN_FFA1R_FFA_Pos)
     
    #define CAN_FFA1R_FFA   CAN_FFA1R_FFA_Msk
     
    #define CAN_FFA1R_FFA0_Pos   (0U)
     
    #define CAN_FFA1R_FFA0_Msk   (0x1UL << CAN_FFA1R_FFA0_Pos)
     
    #define CAN_FFA1R_FFA0   CAN_FFA1R_FFA0_Msk
     
    #define CAN_FFA1R_FFA1_Pos   (1U)
     
    #define CAN_FFA1R_FFA1_Msk   (0x1UL << CAN_FFA1R_FFA1_Pos)
     
    #define CAN_FFA1R_FFA1   CAN_FFA1R_FFA1_Msk
     
    #define CAN_FFA1R_FFA2_Pos   (2U)
     
    #define CAN_FFA1R_FFA2_Msk   (0x1UL << CAN_FFA1R_FFA2_Pos)
     
    #define CAN_FFA1R_FFA2   CAN_FFA1R_FFA2_Msk
     
    #define CAN_FFA1R_FFA3_Pos   (3U)
     
    #define CAN_FFA1R_FFA3_Msk   (0x1UL << CAN_FFA1R_FFA3_Pos)
     
    #define CAN_FFA1R_FFA3   CAN_FFA1R_FFA3_Msk
     
    #define CAN_FFA1R_FFA4_Pos   (4U)
     
    #define CAN_FFA1R_FFA4_Msk   (0x1UL << CAN_FFA1R_FFA4_Pos)
     
    #define CAN_FFA1R_FFA4   CAN_FFA1R_FFA4_Msk
     
    #define CAN_FFA1R_FFA5_Pos   (5U)
     
    #define CAN_FFA1R_FFA5_Msk   (0x1UL << CAN_FFA1R_FFA5_Pos)
     
    #define CAN_FFA1R_FFA5   CAN_FFA1R_FFA5_Msk
     
    #define CAN_FFA1R_FFA6_Pos   (6U)
     
    #define CAN_FFA1R_FFA6_Msk   (0x1UL << CAN_FFA1R_FFA6_Pos)
     
    #define CAN_FFA1R_FFA6   CAN_FFA1R_FFA6_Msk
     
    #define CAN_FFA1R_FFA7_Pos   (7U)
     
    #define CAN_FFA1R_FFA7_Msk   (0x1UL << CAN_FFA1R_FFA7_Pos)
     
    #define CAN_FFA1R_FFA7   CAN_FFA1R_FFA7_Msk
     
    #define CAN_FFA1R_FFA8_Pos   (8U)
     
    #define CAN_FFA1R_FFA8_Msk   (0x1UL << CAN_FFA1R_FFA8_Pos)
     
    #define CAN_FFA1R_FFA8   CAN_FFA1R_FFA8_Msk
     
    #define CAN_FFA1R_FFA9_Pos   (9U)
     
    #define CAN_FFA1R_FFA9_Msk   (0x1UL << CAN_FFA1R_FFA9_Pos)
     
    #define CAN_FFA1R_FFA9   CAN_FFA1R_FFA9_Msk
     
    #define CAN_FFA1R_FFA10_Pos   (10U)
     
    #define CAN_FFA1R_FFA10_Msk   (0x1UL << CAN_FFA1R_FFA10_Pos)
     
    #define CAN_FFA1R_FFA10   CAN_FFA1R_FFA10_Msk
     
    #define CAN_FFA1R_FFA11_Pos   (11U)
     
    #define CAN_FFA1R_FFA11_Msk   (0x1UL << CAN_FFA1R_FFA11_Pos)
     
    #define CAN_FFA1R_FFA11   CAN_FFA1R_FFA11_Msk
     
    #define CAN_FFA1R_FFA12_Pos   (12U)
     
    #define CAN_FFA1R_FFA12_Msk   (0x1UL << CAN_FFA1R_FFA12_Pos)
     
    #define CAN_FFA1R_FFA12   CAN_FFA1R_FFA12_Msk
     
    #define CAN_FFA1R_FFA13_Pos   (13U)
     
    #define CAN_FFA1R_FFA13_Msk   (0x1UL << CAN_FFA1R_FFA13_Pos)
     
    #define CAN_FFA1R_FFA13   CAN_FFA1R_FFA13_Msk
     
    #define CAN_FFA1R_FFA14_Pos   (14U)
     
    #define CAN_FFA1R_FFA14_Msk   (0x1UL << CAN_FFA1R_FFA14_Pos)
     
    #define CAN_FFA1R_FFA14   CAN_FFA1R_FFA14_Msk
     
    #define CAN_FFA1R_FFA15_Pos   (15U)
     
    #define CAN_FFA1R_FFA15_Msk   (0x1UL << CAN_FFA1R_FFA15_Pos)
     
    #define CAN_FFA1R_FFA15   CAN_FFA1R_FFA15_Msk
     
    #define CAN_FFA1R_FFA16_Pos   (16U)
     
    #define CAN_FFA1R_FFA16_Msk   (0x1UL << CAN_FFA1R_FFA16_Pos)
     
    #define CAN_FFA1R_FFA16   CAN_FFA1R_FFA16_Msk
     
    #define CAN_FFA1R_FFA17_Pos   (17U)
     
    #define CAN_FFA1R_FFA17_Msk   (0x1UL << CAN_FFA1R_FFA17_Pos)
     
    #define CAN_FFA1R_FFA17   CAN_FFA1R_FFA17_Msk
     
    #define CAN_FFA1R_FFA18_Pos   (18U)
     
    #define CAN_FFA1R_FFA18_Msk   (0x1UL << CAN_FFA1R_FFA18_Pos)
     
    #define CAN_FFA1R_FFA18   CAN_FFA1R_FFA18_Msk
     
    #define CAN_FFA1R_FFA19_Pos   (19U)
     
    #define CAN_FFA1R_FFA19_Msk   (0x1UL << CAN_FFA1R_FFA19_Pos)
     
    #define CAN_FFA1R_FFA19   CAN_FFA1R_FFA19_Msk
     
    #define CAN_FFA1R_FFA20_Pos   (20U)
     
    #define CAN_FFA1R_FFA20_Msk   (0x1UL << CAN_FFA1R_FFA20_Pos)
     
    #define CAN_FFA1R_FFA20   CAN_FFA1R_FFA20_Msk
     
    #define CAN_FFA1R_FFA21_Pos   (21U)
     
    #define CAN_FFA1R_FFA21_Msk   (0x1UL << CAN_FFA1R_FFA21_Pos)
     
    #define CAN_FFA1R_FFA21   CAN_FFA1R_FFA21_Msk
     
    #define CAN_FFA1R_FFA22_Pos   (22U)
     
    #define CAN_FFA1R_FFA22_Msk   (0x1UL << CAN_FFA1R_FFA22_Pos)
     
    #define CAN_FFA1R_FFA22   CAN_FFA1R_FFA22_Msk
     
    #define CAN_FFA1R_FFA23_Pos   (23U)
     
    #define CAN_FFA1R_FFA23_Msk   (0x1UL << CAN_FFA1R_FFA23_Pos)
     
    #define CAN_FFA1R_FFA23   CAN_FFA1R_FFA23_Msk
     
    #define CAN_FFA1R_FFA24_Pos   (24U)
     
    #define CAN_FFA1R_FFA24_Msk   (0x1UL << CAN_FFA1R_FFA24_Pos)
     
    #define CAN_FFA1R_FFA24   CAN_FFA1R_FFA24_Msk
     
    #define CAN_FFA1R_FFA25_Pos   (25U)
     
    #define CAN_FFA1R_FFA25_Msk   (0x1UL << CAN_FFA1R_FFA25_Pos)
     
    #define CAN_FFA1R_FFA25   CAN_FFA1R_FFA25_Msk
     
    #define CAN_FFA1R_FFA26_Pos   (26U)
     
    #define CAN_FFA1R_FFA26_Msk   (0x1UL << CAN_FFA1R_FFA26_Pos)
     
    #define CAN_FFA1R_FFA26   CAN_FFA1R_FFA26_Msk
     
    #define CAN_FFA1R_FFA27_Pos   (27U)
     
    #define CAN_FFA1R_FFA27_Msk   (0x1UL << CAN_FFA1R_FFA27_Pos)
     
    #define CAN_FFA1R_FFA27   CAN_FFA1R_FFA27_Msk
     
    #define CAN_FA1R_FACT_Pos   (0U)
     
    #define CAN_FA1R_FACT_Msk   (0xFFFFFFFUL << CAN_FA1R_FACT_Pos)
     
    #define CAN_FA1R_FACT   CAN_FA1R_FACT_Msk
     
    #define CAN_FA1R_FACT0_Pos   (0U)
     
    #define CAN_FA1R_FACT0_Msk   (0x1UL << CAN_FA1R_FACT0_Pos)
     
    #define CAN_FA1R_FACT0   CAN_FA1R_FACT0_Msk
     
    #define CAN_FA1R_FACT1_Pos   (1U)
     
    #define CAN_FA1R_FACT1_Msk   (0x1UL << CAN_FA1R_FACT1_Pos)
     
    #define CAN_FA1R_FACT1   CAN_FA1R_FACT1_Msk
     
    #define CAN_FA1R_FACT2_Pos   (2U)
     
    #define CAN_FA1R_FACT2_Msk   (0x1UL << CAN_FA1R_FACT2_Pos)
     
    #define CAN_FA1R_FACT2   CAN_FA1R_FACT2_Msk
     
    #define CAN_FA1R_FACT3_Pos   (3U)
     
    #define CAN_FA1R_FACT3_Msk   (0x1UL << CAN_FA1R_FACT3_Pos)
     
    #define CAN_FA1R_FACT3   CAN_FA1R_FACT3_Msk
     
    #define CAN_FA1R_FACT4_Pos   (4U)
     
    #define CAN_FA1R_FACT4_Msk   (0x1UL << CAN_FA1R_FACT4_Pos)
     
    #define CAN_FA1R_FACT4   CAN_FA1R_FACT4_Msk
     
    #define CAN_FA1R_FACT5_Pos   (5U)
     
    #define CAN_FA1R_FACT5_Msk   (0x1UL << CAN_FA1R_FACT5_Pos)
     
    #define CAN_FA1R_FACT5   CAN_FA1R_FACT5_Msk
     
    #define CAN_FA1R_FACT6_Pos   (6U)
     
    #define CAN_FA1R_FACT6_Msk   (0x1UL << CAN_FA1R_FACT6_Pos)
     
    #define CAN_FA1R_FACT6   CAN_FA1R_FACT6_Msk
     
    #define CAN_FA1R_FACT7_Pos   (7U)
     
    #define CAN_FA1R_FACT7_Msk   (0x1UL << CAN_FA1R_FACT7_Pos)
     
    #define CAN_FA1R_FACT7   CAN_FA1R_FACT7_Msk
     
    #define CAN_FA1R_FACT8_Pos   (8U)
     
    #define CAN_FA1R_FACT8_Msk   (0x1UL << CAN_FA1R_FACT8_Pos)
     
    #define CAN_FA1R_FACT8   CAN_FA1R_FACT8_Msk
     
    #define CAN_FA1R_FACT9_Pos   (9U)
     
    #define CAN_FA1R_FACT9_Msk   (0x1UL << CAN_FA1R_FACT9_Pos)
     
    #define CAN_FA1R_FACT9   CAN_FA1R_FACT9_Msk
     
    #define CAN_FA1R_FACT10_Pos   (10U)
     
    #define CAN_FA1R_FACT10_Msk   (0x1UL << CAN_FA1R_FACT10_Pos)
     
    #define CAN_FA1R_FACT10   CAN_FA1R_FACT10_Msk
     
    #define CAN_FA1R_FACT11_Pos   (11U)
     
    #define CAN_FA1R_FACT11_Msk   (0x1UL << CAN_FA1R_FACT11_Pos)
     
    #define CAN_FA1R_FACT11   CAN_FA1R_FACT11_Msk
     
    #define CAN_FA1R_FACT12_Pos   (12U)
     
    #define CAN_FA1R_FACT12_Msk   (0x1UL << CAN_FA1R_FACT12_Pos)
     
    #define CAN_FA1R_FACT12   CAN_FA1R_FACT12_Msk
     
    #define CAN_FA1R_FACT13_Pos   (13U)
     
    #define CAN_FA1R_FACT13_Msk   (0x1UL << CAN_FA1R_FACT13_Pos)
     
    #define CAN_FA1R_FACT13   CAN_FA1R_FACT13_Msk
     
    #define CAN_FA1R_FACT14_Pos   (14U)
     
    #define CAN_FA1R_FACT14_Msk   (0x1UL << CAN_FA1R_FACT14_Pos)
     
    #define CAN_FA1R_FACT14   CAN_FA1R_FACT14_Msk
     
    #define CAN_FA1R_FACT15_Pos   (15U)
     
    #define CAN_FA1R_FACT15_Msk   (0x1UL << CAN_FA1R_FACT15_Pos)
     
    #define CAN_FA1R_FACT15   CAN_FA1R_FACT15_Msk
     
    #define CAN_FA1R_FACT16_Pos   (16U)
     
    #define CAN_FA1R_FACT16_Msk   (0x1UL << CAN_FA1R_FACT16_Pos)
     
    #define CAN_FA1R_FACT16   CAN_FA1R_FACT16_Msk
     
    #define CAN_FA1R_FACT17_Pos   (17U)
     
    #define CAN_FA1R_FACT17_Msk   (0x1UL << CAN_FA1R_FACT17_Pos)
     
    #define CAN_FA1R_FACT17   CAN_FA1R_FACT17_Msk
     
    #define CAN_FA1R_FACT18_Pos   (18U)
     
    #define CAN_FA1R_FACT18_Msk   (0x1UL << CAN_FA1R_FACT18_Pos)
     
    #define CAN_FA1R_FACT18   CAN_FA1R_FACT18_Msk
     
    #define CAN_FA1R_FACT19_Pos   (19U)
     
    #define CAN_FA1R_FACT19_Msk   (0x1UL << CAN_FA1R_FACT19_Pos)
     
    #define CAN_FA1R_FACT19   CAN_FA1R_FACT19_Msk
     
    #define CAN_FA1R_FACT20_Pos   (20U)
     
    #define CAN_FA1R_FACT20_Msk   (0x1UL << CAN_FA1R_FACT20_Pos)
     
    #define CAN_FA1R_FACT20   CAN_FA1R_FACT20_Msk
     
    #define CAN_FA1R_FACT21_Pos   (21U)
     
    #define CAN_FA1R_FACT21_Msk   (0x1UL << CAN_FA1R_FACT21_Pos)
     
    #define CAN_FA1R_FACT21   CAN_FA1R_FACT21_Msk
     
    #define CAN_FA1R_FACT22_Pos   (22U)
     
    #define CAN_FA1R_FACT22_Msk   (0x1UL << CAN_FA1R_FACT22_Pos)
     
    #define CAN_FA1R_FACT22   CAN_FA1R_FACT22_Msk
     
    #define CAN_FA1R_FACT23_Pos   (23U)
     
    #define CAN_FA1R_FACT23_Msk   (0x1UL << CAN_FA1R_FACT23_Pos)
     
    #define CAN_FA1R_FACT23   CAN_FA1R_FACT23_Msk
     
    #define CAN_FA1R_FACT24_Pos   (24U)
     
    #define CAN_FA1R_FACT24_Msk   (0x1UL << CAN_FA1R_FACT24_Pos)
     
    #define CAN_FA1R_FACT24   CAN_FA1R_FACT24_Msk
     
    #define CAN_FA1R_FACT25_Pos   (25U)
     
    #define CAN_FA1R_FACT25_Msk   (0x1UL << CAN_FA1R_FACT25_Pos)
     
    #define CAN_FA1R_FACT25   CAN_FA1R_FACT25_Msk
     
    #define CAN_FA1R_FACT26_Pos   (26U)
     
    #define CAN_FA1R_FACT26_Msk   (0x1UL << CAN_FA1R_FACT26_Pos)
     
    #define CAN_FA1R_FACT26   CAN_FA1R_FACT26_Msk
     
    #define CAN_FA1R_FACT27_Pos   (27U)
     
    #define CAN_FA1R_FACT27_Msk   (0x1UL << CAN_FA1R_FACT27_Pos)
     
    #define CAN_FA1R_FACT27   CAN_FA1R_FACT27_Msk
     
    #define CAN_F0R1_FB0_Pos   (0U)
     
    #define CAN_F0R1_FB0_Msk   (0x1UL << CAN_F0R1_FB0_Pos)
     
    #define CAN_F0R1_FB0   CAN_F0R1_FB0_Msk
     
    #define CAN_F0R1_FB1_Pos   (1U)
     
    #define CAN_F0R1_FB1_Msk   (0x1UL << CAN_F0R1_FB1_Pos)
     
    #define CAN_F0R1_FB1   CAN_F0R1_FB1_Msk
     
    #define CAN_F0R1_FB2_Pos   (2U)
     
    #define CAN_F0R1_FB2_Msk   (0x1UL << CAN_F0R1_FB2_Pos)
     
    #define CAN_F0R1_FB2   CAN_F0R1_FB2_Msk
     
    #define CAN_F0R1_FB3_Pos   (3U)
     
    #define CAN_F0R1_FB3_Msk   (0x1UL << CAN_F0R1_FB3_Pos)
     
    #define CAN_F0R1_FB3   CAN_F0R1_FB3_Msk
     
    #define CAN_F0R1_FB4_Pos   (4U)
     
    #define CAN_F0R1_FB4_Msk   (0x1UL << CAN_F0R1_FB4_Pos)
     
    #define CAN_F0R1_FB4   CAN_F0R1_FB4_Msk
     
    #define CAN_F0R1_FB5_Pos   (5U)
     
    #define CAN_F0R1_FB5_Msk   (0x1UL << CAN_F0R1_FB5_Pos)
     
    #define CAN_F0R1_FB5   CAN_F0R1_FB5_Msk
     
    #define CAN_F0R1_FB6_Pos   (6U)
     
    #define CAN_F0R1_FB6_Msk   (0x1UL << CAN_F0R1_FB6_Pos)
     
    #define CAN_F0R1_FB6   CAN_F0R1_FB6_Msk
     
    #define CAN_F0R1_FB7_Pos   (7U)
     
    #define CAN_F0R1_FB7_Msk   (0x1UL << CAN_F0R1_FB7_Pos)
     
    #define CAN_F0R1_FB7   CAN_F0R1_FB7_Msk
     
    #define CAN_F0R1_FB8_Pos   (8U)
     
    #define CAN_F0R1_FB8_Msk   (0x1UL << CAN_F0R1_FB8_Pos)
     
    #define CAN_F0R1_FB8   CAN_F0R1_FB8_Msk
     
    #define CAN_F0R1_FB9_Pos   (9U)
     
    #define CAN_F0R1_FB9_Msk   (0x1UL << CAN_F0R1_FB9_Pos)
     
    #define CAN_F0R1_FB9   CAN_F0R1_FB9_Msk
     
    #define CAN_F0R1_FB10_Pos   (10U)
     
    #define CAN_F0R1_FB10_Msk   (0x1UL << CAN_F0R1_FB10_Pos)
     
    #define CAN_F0R1_FB10   CAN_F0R1_FB10_Msk
     
    #define CAN_F0R1_FB11_Pos   (11U)
     
    #define CAN_F0R1_FB11_Msk   (0x1UL << CAN_F0R1_FB11_Pos)
     
    #define CAN_F0R1_FB11   CAN_F0R1_FB11_Msk
     
    #define CAN_F0R1_FB12_Pos   (12U)
     
    #define CAN_F0R1_FB12_Msk   (0x1UL << CAN_F0R1_FB12_Pos)
     
    #define CAN_F0R1_FB12   CAN_F0R1_FB12_Msk
     
    #define CAN_F0R1_FB13_Pos   (13U)
     
    #define CAN_F0R1_FB13_Msk   (0x1UL << CAN_F0R1_FB13_Pos)
     
    #define CAN_F0R1_FB13   CAN_F0R1_FB13_Msk
     
    #define CAN_F0R1_FB14_Pos   (14U)
     
    #define CAN_F0R1_FB14_Msk   (0x1UL << CAN_F0R1_FB14_Pos)
     
    #define CAN_F0R1_FB14   CAN_F0R1_FB14_Msk
     
    #define CAN_F0R1_FB15_Pos   (15U)
     
    #define CAN_F0R1_FB15_Msk   (0x1UL << CAN_F0R1_FB15_Pos)
     
    #define CAN_F0R1_FB15   CAN_F0R1_FB15_Msk
     
    #define CAN_F0R1_FB16_Pos   (16U)
     
    #define CAN_F0R1_FB16_Msk   (0x1UL << CAN_F0R1_FB16_Pos)
     
    #define CAN_F0R1_FB16   CAN_F0R1_FB16_Msk
     
    #define CAN_F0R1_FB17_Pos   (17U)
     
    #define CAN_F0R1_FB17_Msk   (0x1UL << CAN_F0R1_FB17_Pos)
     
    #define CAN_F0R1_FB17   CAN_F0R1_FB17_Msk
     
    #define CAN_F0R1_FB18_Pos   (18U)
     
    #define CAN_F0R1_FB18_Msk   (0x1UL << CAN_F0R1_FB18_Pos)
     
    #define CAN_F0R1_FB18   CAN_F0R1_FB18_Msk
     
    #define CAN_F0R1_FB19_Pos   (19U)
     
    #define CAN_F0R1_FB19_Msk   (0x1UL << CAN_F0R1_FB19_Pos)
     
    #define CAN_F0R1_FB19   CAN_F0R1_FB19_Msk
     
    #define CAN_F0R1_FB20_Pos   (20U)
     
    #define CAN_F0R1_FB20_Msk   (0x1UL << CAN_F0R1_FB20_Pos)
     
    #define CAN_F0R1_FB20   CAN_F0R1_FB20_Msk
     
    #define CAN_F0R1_FB21_Pos   (21U)
     
    #define CAN_F0R1_FB21_Msk   (0x1UL << CAN_F0R1_FB21_Pos)
     
    #define CAN_F0R1_FB21   CAN_F0R1_FB21_Msk
     
    #define CAN_F0R1_FB22_Pos   (22U)
     
    #define CAN_F0R1_FB22_Msk   (0x1UL << CAN_F0R1_FB22_Pos)
     
    #define CAN_F0R1_FB22   CAN_F0R1_FB22_Msk
     
    #define CAN_F0R1_FB23_Pos   (23U)
     
    #define CAN_F0R1_FB23_Msk   (0x1UL << CAN_F0R1_FB23_Pos)
     
    #define CAN_F0R1_FB23   CAN_F0R1_FB23_Msk
     
    #define CAN_F0R1_FB24_Pos   (24U)
     
    #define CAN_F0R1_FB24_Msk   (0x1UL << CAN_F0R1_FB24_Pos)
     
    #define CAN_F0R1_FB24   CAN_F0R1_FB24_Msk
     
    #define CAN_F0R1_FB25_Pos   (25U)
     
    #define CAN_F0R1_FB25_Msk   (0x1UL << CAN_F0R1_FB25_Pos)
     
    #define CAN_F0R1_FB25   CAN_F0R1_FB25_Msk
     
    #define CAN_F0R1_FB26_Pos   (26U)
     
    #define CAN_F0R1_FB26_Msk   (0x1UL << CAN_F0R1_FB26_Pos)
     
    #define CAN_F0R1_FB26   CAN_F0R1_FB26_Msk
     
    #define CAN_F0R1_FB27_Pos   (27U)
     
    #define CAN_F0R1_FB27_Msk   (0x1UL << CAN_F0R1_FB27_Pos)
     
    #define CAN_F0R1_FB27   CAN_F0R1_FB27_Msk
     
    #define CAN_F0R1_FB28_Pos   (28U)
     
    #define CAN_F0R1_FB28_Msk   (0x1UL << CAN_F0R1_FB28_Pos)
     
    #define CAN_F0R1_FB28   CAN_F0R1_FB28_Msk
     
    #define CAN_F0R1_FB29_Pos   (29U)
     
    #define CAN_F0R1_FB29_Msk   (0x1UL << CAN_F0R1_FB29_Pos)
     
    #define CAN_F0R1_FB29   CAN_F0R1_FB29_Msk
     
    #define CAN_F0R1_FB30_Pos   (30U)
     
    #define CAN_F0R1_FB30_Msk   (0x1UL << CAN_F0R1_FB30_Pos)
     
    #define CAN_F0R1_FB30   CAN_F0R1_FB30_Msk
     
    #define CAN_F0R1_FB31_Pos   (31U)
     
    #define CAN_F0R1_FB31_Msk   (0x1UL << CAN_F0R1_FB31_Pos)
     
    #define CAN_F0R1_FB31   CAN_F0R1_FB31_Msk
     
    #define CAN_F1R1_FB0_Pos   (0U)
     
    #define CAN_F1R1_FB0_Msk   (0x1UL << CAN_F1R1_FB0_Pos)
     
    #define CAN_F1R1_FB0   CAN_F1R1_FB0_Msk
     
    #define CAN_F1R1_FB1_Pos   (1U)
     
    #define CAN_F1R1_FB1_Msk   (0x1UL << CAN_F1R1_FB1_Pos)
     
    #define CAN_F1R1_FB1   CAN_F1R1_FB1_Msk
     
    #define CAN_F1R1_FB2_Pos   (2U)
     
    #define CAN_F1R1_FB2_Msk   (0x1UL << CAN_F1R1_FB2_Pos)
     
    #define CAN_F1R1_FB2   CAN_F1R1_FB2_Msk
     
    #define CAN_F1R1_FB3_Pos   (3U)
     
    #define CAN_F1R1_FB3_Msk   (0x1UL << CAN_F1R1_FB3_Pos)
     
    #define CAN_F1R1_FB3   CAN_F1R1_FB3_Msk
     
    #define CAN_F1R1_FB4_Pos   (4U)
     
    #define CAN_F1R1_FB4_Msk   (0x1UL << CAN_F1R1_FB4_Pos)
     
    #define CAN_F1R1_FB4   CAN_F1R1_FB4_Msk
     
    #define CAN_F1R1_FB5_Pos   (5U)
     
    #define CAN_F1R1_FB5_Msk   (0x1UL << CAN_F1R1_FB5_Pos)
     
    #define CAN_F1R1_FB5   CAN_F1R1_FB5_Msk
     
    #define CAN_F1R1_FB6_Pos   (6U)
     
    #define CAN_F1R1_FB6_Msk   (0x1UL << CAN_F1R1_FB6_Pos)
     
    #define CAN_F1R1_FB6   CAN_F1R1_FB6_Msk
     
    #define CAN_F1R1_FB7_Pos   (7U)
     
    #define CAN_F1R1_FB7_Msk   (0x1UL << CAN_F1R1_FB7_Pos)
     
    #define CAN_F1R1_FB7   CAN_F1R1_FB7_Msk
     
    #define CAN_F1R1_FB8_Pos   (8U)
     
    #define CAN_F1R1_FB8_Msk   (0x1UL << CAN_F1R1_FB8_Pos)
     
    #define CAN_F1R1_FB8   CAN_F1R1_FB8_Msk
     
    #define CAN_F1R1_FB9_Pos   (9U)
     
    #define CAN_F1R1_FB9_Msk   (0x1UL << CAN_F1R1_FB9_Pos)
     
    #define CAN_F1R1_FB9   CAN_F1R1_FB9_Msk
     
    #define CAN_F1R1_FB10_Pos   (10U)
     
    #define CAN_F1R1_FB10_Msk   (0x1UL << CAN_F1R1_FB10_Pos)
     
    #define CAN_F1R1_FB10   CAN_F1R1_FB10_Msk
     
    #define CAN_F1R1_FB11_Pos   (11U)
     
    #define CAN_F1R1_FB11_Msk   (0x1UL << CAN_F1R1_FB11_Pos)
     
    #define CAN_F1R1_FB11   CAN_F1R1_FB11_Msk
     
    #define CAN_F1R1_FB12_Pos   (12U)
     
    #define CAN_F1R1_FB12_Msk   (0x1UL << CAN_F1R1_FB12_Pos)
     
    #define CAN_F1R1_FB12   CAN_F1R1_FB12_Msk
     
    #define CAN_F1R1_FB13_Pos   (13U)
     
    #define CAN_F1R1_FB13_Msk   (0x1UL << CAN_F1R1_FB13_Pos)
     
    #define CAN_F1R1_FB13   CAN_F1R1_FB13_Msk
     
    #define CAN_F1R1_FB14_Pos   (14U)
     
    #define CAN_F1R1_FB14_Msk   (0x1UL << CAN_F1R1_FB14_Pos)
     
    #define CAN_F1R1_FB14   CAN_F1R1_FB14_Msk
     
    #define CAN_F1R1_FB15_Pos   (15U)
     
    #define CAN_F1R1_FB15_Msk   (0x1UL << CAN_F1R1_FB15_Pos)
     
    #define CAN_F1R1_FB15   CAN_F1R1_FB15_Msk
     
    #define CAN_F1R1_FB16_Pos   (16U)
     
    #define CAN_F1R1_FB16_Msk   (0x1UL << CAN_F1R1_FB16_Pos)
     
    #define CAN_F1R1_FB16   CAN_F1R1_FB16_Msk
     
    #define CAN_F1R1_FB17_Pos   (17U)
     
    #define CAN_F1R1_FB17_Msk   (0x1UL << CAN_F1R1_FB17_Pos)
     
    #define CAN_F1R1_FB17   CAN_F1R1_FB17_Msk
     
    #define CAN_F1R1_FB18_Pos   (18U)
     
    #define CAN_F1R1_FB18_Msk   (0x1UL << CAN_F1R1_FB18_Pos)
     
    #define CAN_F1R1_FB18   CAN_F1R1_FB18_Msk
     
    #define CAN_F1R1_FB19_Pos   (19U)
     
    #define CAN_F1R1_FB19_Msk   (0x1UL << CAN_F1R1_FB19_Pos)
     
    #define CAN_F1R1_FB19   CAN_F1R1_FB19_Msk
     
    #define CAN_F1R1_FB20_Pos   (20U)
     
    #define CAN_F1R1_FB20_Msk   (0x1UL << CAN_F1R1_FB20_Pos)
     
    #define CAN_F1R1_FB20   CAN_F1R1_FB20_Msk
     
    #define CAN_F1R1_FB21_Pos   (21U)
     
    #define CAN_F1R1_FB21_Msk   (0x1UL << CAN_F1R1_FB21_Pos)
     
    #define CAN_F1R1_FB21   CAN_F1R1_FB21_Msk
     
    #define CAN_F1R1_FB22_Pos   (22U)
     
    #define CAN_F1R1_FB22_Msk   (0x1UL << CAN_F1R1_FB22_Pos)
     
    #define CAN_F1R1_FB22   CAN_F1R1_FB22_Msk
     
    #define CAN_F1R1_FB23_Pos   (23U)
     
    #define CAN_F1R1_FB23_Msk   (0x1UL << CAN_F1R1_FB23_Pos)
     
    #define CAN_F1R1_FB23   CAN_F1R1_FB23_Msk
     
    #define CAN_F1R1_FB24_Pos   (24U)
     
    #define CAN_F1R1_FB24_Msk   (0x1UL << CAN_F1R1_FB24_Pos)
     
    #define CAN_F1R1_FB24   CAN_F1R1_FB24_Msk
     
    #define CAN_F1R1_FB25_Pos   (25U)
     
    #define CAN_F1R1_FB25_Msk   (0x1UL << CAN_F1R1_FB25_Pos)
     
    #define CAN_F1R1_FB25   CAN_F1R1_FB25_Msk
     
    #define CAN_F1R1_FB26_Pos   (26U)
     
    #define CAN_F1R1_FB26_Msk   (0x1UL << CAN_F1R1_FB26_Pos)
     
    #define CAN_F1R1_FB26   CAN_F1R1_FB26_Msk
     
    #define CAN_F1R1_FB27_Pos   (27U)
     
    #define CAN_F1R1_FB27_Msk   (0x1UL << CAN_F1R1_FB27_Pos)
     
    #define CAN_F1R1_FB27   CAN_F1R1_FB27_Msk
     
    #define CAN_F1R1_FB28_Pos   (28U)
     
    #define CAN_F1R1_FB28_Msk   (0x1UL << CAN_F1R1_FB28_Pos)
     
    #define CAN_F1R1_FB28   CAN_F1R1_FB28_Msk
     
    #define CAN_F1R1_FB29_Pos   (29U)
     
    #define CAN_F1R1_FB29_Msk   (0x1UL << CAN_F1R1_FB29_Pos)
     
    #define CAN_F1R1_FB29   CAN_F1R1_FB29_Msk
     
    #define CAN_F1R1_FB30_Pos   (30U)
     
    #define CAN_F1R1_FB30_Msk   (0x1UL << CAN_F1R1_FB30_Pos)
     
    #define CAN_F1R1_FB30   CAN_F1R1_FB30_Msk
     
    #define CAN_F1R1_FB31_Pos   (31U)
     
    #define CAN_F1R1_FB31_Msk   (0x1UL << CAN_F1R1_FB31_Pos)
     
    #define CAN_F1R1_FB31   CAN_F1R1_FB31_Msk
     
    #define CAN_F2R1_FB0_Pos   (0U)
     
    #define CAN_F2R1_FB0_Msk   (0x1UL << CAN_F2R1_FB0_Pos)
     
    #define CAN_F2R1_FB0   CAN_F2R1_FB0_Msk
     
    #define CAN_F2R1_FB1_Pos   (1U)
     
    #define CAN_F2R1_FB1_Msk   (0x1UL << CAN_F2R1_FB1_Pos)
     
    #define CAN_F2R1_FB1   CAN_F2R1_FB1_Msk
     
    #define CAN_F2R1_FB2_Pos   (2U)
     
    #define CAN_F2R1_FB2_Msk   (0x1UL << CAN_F2R1_FB2_Pos)
     
    #define CAN_F2R1_FB2   CAN_F2R1_FB2_Msk
     
    #define CAN_F2R1_FB3_Pos   (3U)
     
    #define CAN_F2R1_FB3_Msk   (0x1UL << CAN_F2R1_FB3_Pos)
     
    #define CAN_F2R1_FB3   CAN_F2R1_FB3_Msk
     
    #define CAN_F2R1_FB4_Pos   (4U)
     
    #define CAN_F2R1_FB4_Msk   (0x1UL << CAN_F2R1_FB4_Pos)
     
    #define CAN_F2R1_FB4   CAN_F2R1_FB4_Msk
     
    #define CAN_F2R1_FB5_Pos   (5U)
     
    #define CAN_F2R1_FB5_Msk   (0x1UL << CAN_F2R1_FB5_Pos)
     
    #define CAN_F2R1_FB5   CAN_F2R1_FB5_Msk
     
    #define CAN_F2R1_FB6_Pos   (6U)
     
    #define CAN_F2R1_FB6_Msk   (0x1UL << CAN_F2R1_FB6_Pos)
     
    #define CAN_F2R1_FB6   CAN_F2R1_FB6_Msk
     
    #define CAN_F2R1_FB7_Pos   (7U)
     
    #define CAN_F2R1_FB7_Msk   (0x1UL << CAN_F2R1_FB7_Pos)
     
    #define CAN_F2R1_FB7   CAN_F2R1_FB7_Msk
     
    #define CAN_F2R1_FB8_Pos   (8U)
     
    #define CAN_F2R1_FB8_Msk   (0x1UL << CAN_F2R1_FB8_Pos)
     
    #define CAN_F2R1_FB8   CAN_F2R1_FB8_Msk
     
    #define CAN_F2R1_FB9_Pos   (9U)
     
    #define CAN_F2R1_FB9_Msk   (0x1UL << CAN_F2R1_FB9_Pos)
     
    #define CAN_F2R1_FB9   CAN_F2R1_FB9_Msk
     
    #define CAN_F2R1_FB10_Pos   (10U)
     
    #define CAN_F2R1_FB10_Msk   (0x1UL << CAN_F2R1_FB10_Pos)
     
    #define CAN_F2R1_FB10   CAN_F2R1_FB10_Msk
     
    #define CAN_F2R1_FB11_Pos   (11U)
     
    #define CAN_F2R1_FB11_Msk   (0x1UL << CAN_F2R1_FB11_Pos)
     
    #define CAN_F2R1_FB11   CAN_F2R1_FB11_Msk
     
    #define CAN_F2R1_FB12_Pos   (12U)
     
    #define CAN_F2R1_FB12_Msk   (0x1UL << CAN_F2R1_FB12_Pos)
     
    #define CAN_F2R1_FB12   CAN_F2R1_FB12_Msk
     
    #define CAN_F2R1_FB13_Pos   (13U)
     
    #define CAN_F2R1_FB13_Msk   (0x1UL << CAN_F2R1_FB13_Pos)
     
    #define CAN_F2R1_FB13   CAN_F2R1_FB13_Msk
     
    #define CAN_F2R1_FB14_Pos   (14U)
     
    #define CAN_F2R1_FB14_Msk   (0x1UL << CAN_F2R1_FB14_Pos)
     
    #define CAN_F2R1_FB14   CAN_F2R1_FB14_Msk
     
    #define CAN_F2R1_FB15_Pos   (15U)
     
    #define CAN_F2R1_FB15_Msk   (0x1UL << CAN_F2R1_FB15_Pos)
     
    #define CAN_F2R1_FB15   CAN_F2R1_FB15_Msk
     
    #define CAN_F2R1_FB16_Pos   (16U)
     
    #define CAN_F2R1_FB16_Msk   (0x1UL << CAN_F2R1_FB16_Pos)
     
    #define CAN_F2R1_FB16   CAN_F2R1_FB16_Msk
     
    #define CAN_F2R1_FB17_Pos   (17U)
     
    #define CAN_F2R1_FB17_Msk   (0x1UL << CAN_F2R1_FB17_Pos)
     
    #define CAN_F2R1_FB17   CAN_F2R1_FB17_Msk
     
    #define CAN_F2R1_FB18_Pos   (18U)
     
    #define CAN_F2R1_FB18_Msk   (0x1UL << CAN_F2R1_FB18_Pos)
     
    #define CAN_F2R1_FB18   CAN_F2R1_FB18_Msk
     
    #define CAN_F2R1_FB19_Pos   (19U)
     
    #define CAN_F2R1_FB19_Msk   (0x1UL << CAN_F2R1_FB19_Pos)
     
    #define CAN_F2R1_FB19   CAN_F2R1_FB19_Msk
     
    #define CAN_F2R1_FB20_Pos   (20U)
     
    #define CAN_F2R1_FB20_Msk   (0x1UL << CAN_F2R1_FB20_Pos)
     
    #define CAN_F2R1_FB20   CAN_F2R1_FB20_Msk
     
    #define CAN_F2R1_FB21_Pos   (21U)
     
    #define CAN_F2R1_FB21_Msk   (0x1UL << CAN_F2R1_FB21_Pos)
     
    #define CAN_F2R1_FB21   CAN_F2R1_FB21_Msk
     
    #define CAN_F2R1_FB22_Pos   (22U)
     
    #define CAN_F2R1_FB22_Msk   (0x1UL << CAN_F2R1_FB22_Pos)
     
    #define CAN_F2R1_FB22   CAN_F2R1_FB22_Msk
     
    #define CAN_F2R1_FB23_Pos   (23U)
     
    #define CAN_F2R1_FB23_Msk   (0x1UL << CAN_F2R1_FB23_Pos)
     
    #define CAN_F2R1_FB23   CAN_F2R1_FB23_Msk
     
    #define CAN_F2R1_FB24_Pos   (24U)
     
    #define CAN_F2R1_FB24_Msk   (0x1UL << CAN_F2R1_FB24_Pos)
     
    #define CAN_F2R1_FB24   CAN_F2R1_FB24_Msk
     
    #define CAN_F2R1_FB25_Pos   (25U)
     
    #define CAN_F2R1_FB25_Msk   (0x1UL << CAN_F2R1_FB25_Pos)
     
    #define CAN_F2R1_FB25   CAN_F2R1_FB25_Msk
     
    #define CAN_F2R1_FB26_Pos   (26U)
     
    #define CAN_F2R1_FB26_Msk   (0x1UL << CAN_F2R1_FB26_Pos)
     
    #define CAN_F2R1_FB26   CAN_F2R1_FB26_Msk
     
    #define CAN_F2R1_FB27_Pos   (27U)
     
    #define CAN_F2R1_FB27_Msk   (0x1UL << CAN_F2R1_FB27_Pos)
     
    #define CAN_F2R1_FB27   CAN_F2R1_FB27_Msk
     
    #define CAN_F2R1_FB28_Pos   (28U)
     
    #define CAN_F2R1_FB28_Msk   (0x1UL << CAN_F2R1_FB28_Pos)
     
    #define CAN_F2R1_FB28   CAN_F2R1_FB28_Msk
     
    #define CAN_F2R1_FB29_Pos   (29U)
     
    #define CAN_F2R1_FB29_Msk   (0x1UL << CAN_F2R1_FB29_Pos)
     
    #define CAN_F2R1_FB29   CAN_F2R1_FB29_Msk
     
    #define CAN_F2R1_FB30_Pos   (30U)
     
    #define CAN_F2R1_FB30_Msk   (0x1UL << CAN_F2R1_FB30_Pos)
     
    #define CAN_F2R1_FB30   CAN_F2R1_FB30_Msk
     
    #define CAN_F2R1_FB31_Pos   (31U)
     
    #define CAN_F2R1_FB31_Msk   (0x1UL << CAN_F2R1_FB31_Pos)
     
    #define CAN_F2R1_FB31   CAN_F2R1_FB31_Msk
     
    #define CAN_F3R1_FB0_Pos   (0U)
     
    #define CAN_F3R1_FB0_Msk   (0x1UL << CAN_F3R1_FB0_Pos)
     
    #define CAN_F3R1_FB0   CAN_F3R1_FB0_Msk
     
    #define CAN_F3R1_FB1_Pos   (1U)
     
    #define CAN_F3R1_FB1_Msk   (0x1UL << CAN_F3R1_FB1_Pos)
     
    #define CAN_F3R1_FB1   CAN_F3R1_FB1_Msk
     
    #define CAN_F3R1_FB2_Pos   (2U)
     
    #define CAN_F3R1_FB2_Msk   (0x1UL << CAN_F3R1_FB2_Pos)
     
    #define CAN_F3R1_FB2   CAN_F3R1_FB2_Msk
     
    #define CAN_F3R1_FB3_Pos   (3U)
     
    #define CAN_F3R1_FB3_Msk   (0x1UL << CAN_F3R1_FB3_Pos)
     
    #define CAN_F3R1_FB3   CAN_F3R1_FB3_Msk
     
    #define CAN_F3R1_FB4_Pos   (4U)
     
    #define CAN_F3R1_FB4_Msk   (0x1UL << CAN_F3R1_FB4_Pos)
     
    #define CAN_F3R1_FB4   CAN_F3R1_FB4_Msk
     
    #define CAN_F3R1_FB5_Pos   (5U)
     
    #define CAN_F3R1_FB5_Msk   (0x1UL << CAN_F3R1_FB5_Pos)
     
    #define CAN_F3R1_FB5   CAN_F3R1_FB5_Msk
     
    #define CAN_F3R1_FB6_Pos   (6U)
     
    #define CAN_F3R1_FB6_Msk   (0x1UL << CAN_F3R1_FB6_Pos)
     
    #define CAN_F3R1_FB6   CAN_F3R1_FB6_Msk
     
    #define CAN_F3R1_FB7_Pos   (7U)
     
    #define CAN_F3R1_FB7_Msk   (0x1UL << CAN_F3R1_FB7_Pos)
     
    #define CAN_F3R1_FB7   CAN_F3R1_FB7_Msk
     
    #define CAN_F3R1_FB8_Pos   (8U)
     
    #define CAN_F3R1_FB8_Msk   (0x1UL << CAN_F3R1_FB8_Pos)
     
    #define CAN_F3R1_FB8   CAN_F3R1_FB8_Msk
     
    #define CAN_F3R1_FB9_Pos   (9U)
     
    #define CAN_F3R1_FB9_Msk   (0x1UL << CAN_F3R1_FB9_Pos)
     
    #define CAN_F3R1_FB9   CAN_F3R1_FB9_Msk
     
    #define CAN_F3R1_FB10_Pos   (10U)
     
    #define CAN_F3R1_FB10_Msk   (0x1UL << CAN_F3R1_FB10_Pos)
     
    #define CAN_F3R1_FB10   CAN_F3R1_FB10_Msk
     
    #define CAN_F3R1_FB11_Pos   (11U)
     
    #define CAN_F3R1_FB11_Msk   (0x1UL << CAN_F3R1_FB11_Pos)
     
    #define CAN_F3R1_FB11   CAN_F3R1_FB11_Msk
     
    #define CAN_F3R1_FB12_Pos   (12U)
     
    #define CAN_F3R1_FB12_Msk   (0x1UL << CAN_F3R1_FB12_Pos)
     
    #define CAN_F3R1_FB12   CAN_F3R1_FB12_Msk
     
    #define CAN_F3R1_FB13_Pos   (13U)
     
    #define CAN_F3R1_FB13_Msk   (0x1UL << CAN_F3R1_FB13_Pos)
     
    #define CAN_F3R1_FB13   CAN_F3R1_FB13_Msk
     
    #define CAN_F3R1_FB14_Pos   (14U)
     
    #define CAN_F3R1_FB14_Msk   (0x1UL << CAN_F3R1_FB14_Pos)
     
    #define CAN_F3R1_FB14   CAN_F3R1_FB14_Msk
     
    #define CAN_F3R1_FB15_Pos   (15U)
     
    #define CAN_F3R1_FB15_Msk   (0x1UL << CAN_F3R1_FB15_Pos)
     
    #define CAN_F3R1_FB15   CAN_F3R1_FB15_Msk
     
    #define CAN_F3R1_FB16_Pos   (16U)
     
    #define CAN_F3R1_FB16_Msk   (0x1UL << CAN_F3R1_FB16_Pos)
     
    #define CAN_F3R1_FB16   CAN_F3R1_FB16_Msk
     
    #define CAN_F3R1_FB17_Pos   (17U)
     
    #define CAN_F3R1_FB17_Msk   (0x1UL << CAN_F3R1_FB17_Pos)
     
    #define CAN_F3R1_FB17   CAN_F3R1_FB17_Msk
     
    #define CAN_F3R1_FB18_Pos   (18U)
     
    #define CAN_F3R1_FB18_Msk   (0x1UL << CAN_F3R1_FB18_Pos)
     
    #define CAN_F3R1_FB18   CAN_F3R1_FB18_Msk
     
    #define CAN_F3R1_FB19_Pos   (19U)
     
    #define CAN_F3R1_FB19_Msk   (0x1UL << CAN_F3R1_FB19_Pos)
     
    #define CAN_F3R1_FB19   CAN_F3R1_FB19_Msk
     
    #define CAN_F3R1_FB20_Pos   (20U)
     
    #define CAN_F3R1_FB20_Msk   (0x1UL << CAN_F3R1_FB20_Pos)
     
    #define CAN_F3R1_FB20   CAN_F3R1_FB20_Msk
     
    #define CAN_F3R1_FB21_Pos   (21U)
     
    #define CAN_F3R1_FB21_Msk   (0x1UL << CAN_F3R1_FB21_Pos)
     
    #define CAN_F3R1_FB21   CAN_F3R1_FB21_Msk
     
    #define CAN_F3R1_FB22_Pos   (22U)
     
    #define CAN_F3R1_FB22_Msk   (0x1UL << CAN_F3R1_FB22_Pos)
     
    #define CAN_F3R1_FB22   CAN_F3R1_FB22_Msk
     
    #define CAN_F3R1_FB23_Pos   (23U)
     
    #define CAN_F3R1_FB23_Msk   (0x1UL << CAN_F3R1_FB23_Pos)
     
    #define CAN_F3R1_FB23   CAN_F3R1_FB23_Msk
     
    #define CAN_F3R1_FB24_Pos   (24U)
     
    #define CAN_F3R1_FB24_Msk   (0x1UL << CAN_F3R1_FB24_Pos)
     
    #define CAN_F3R1_FB24   CAN_F3R1_FB24_Msk
     
    #define CAN_F3R1_FB25_Pos   (25U)
     
    #define CAN_F3R1_FB25_Msk   (0x1UL << CAN_F3R1_FB25_Pos)
     
    #define CAN_F3R1_FB25   CAN_F3R1_FB25_Msk
     
    #define CAN_F3R1_FB26_Pos   (26U)
     
    #define CAN_F3R1_FB26_Msk   (0x1UL << CAN_F3R1_FB26_Pos)
     
    #define CAN_F3R1_FB26   CAN_F3R1_FB26_Msk
     
    #define CAN_F3R1_FB27_Pos   (27U)
     
    #define CAN_F3R1_FB27_Msk   (0x1UL << CAN_F3R1_FB27_Pos)
     
    #define CAN_F3R1_FB27   CAN_F3R1_FB27_Msk
     
    #define CAN_F3R1_FB28_Pos   (28U)
     
    #define CAN_F3R1_FB28_Msk   (0x1UL << CAN_F3R1_FB28_Pos)
     
    #define CAN_F3R1_FB28   CAN_F3R1_FB28_Msk
     
    #define CAN_F3R1_FB29_Pos   (29U)
     
    #define CAN_F3R1_FB29_Msk   (0x1UL << CAN_F3R1_FB29_Pos)
     
    #define CAN_F3R1_FB29   CAN_F3R1_FB29_Msk
     
    #define CAN_F3R1_FB30_Pos   (30U)
     
    #define CAN_F3R1_FB30_Msk   (0x1UL << CAN_F3R1_FB30_Pos)
     
    #define CAN_F3R1_FB30   CAN_F3R1_FB30_Msk
     
    #define CAN_F3R1_FB31_Pos   (31U)
     
    #define CAN_F3R1_FB31_Msk   (0x1UL << CAN_F3R1_FB31_Pos)
     
    #define CAN_F3R1_FB31   CAN_F3R1_FB31_Msk
     
    #define CAN_F4R1_FB0_Pos   (0U)
     
    #define CAN_F4R1_FB0_Msk   (0x1UL << CAN_F4R1_FB0_Pos)
     
    #define CAN_F4R1_FB0   CAN_F4R1_FB0_Msk
     
    #define CAN_F4R1_FB1_Pos   (1U)
     
    #define CAN_F4R1_FB1_Msk   (0x1UL << CAN_F4R1_FB1_Pos)
     
    #define CAN_F4R1_FB1   CAN_F4R1_FB1_Msk
     
    #define CAN_F4R1_FB2_Pos   (2U)
     
    #define CAN_F4R1_FB2_Msk   (0x1UL << CAN_F4R1_FB2_Pos)
     
    #define CAN_F4R1_FB2   CAN_F4R1_FB2_Msk
     
    #define CAN_F4R1_FB3_Pos   (3U)
     
    #define CAN_F4R1_FB3_Msk   (0x1UL << CAN_F4R1_FB3_Pos)
     
    #define CAN_F4R1_FB3   CAN_F4R1_FB3_Msk
     
    #define CAN_F4R1_FB4_Pos   (4U)
     
    #define CAN_F4R1_FB4_Msk   (0x1UL << CAN_F4R1_FB4_Pos)
     
    #define CAN_F4R1_FB4   CAN_F4R1_FB4_Msk
     
    #define CAN_F4R1_FB5_Pos   (5U)
     
    #define CAN_F4R1_FB5_Msk   (0x1UL << CAN_F4R1_FB5_Pos)
     
    #define CAN_F4R1_FB5   CAN_F4R1_FB5_Msk
     
    #define CAN_F4R1_FB6_Pos   (6U)
     
    #define CAN_F4R1_FB6_Msk   (0x1UL << CAN_F4R1_FB6_Pos)
     
    #define CAN_F4R1_FB6   CAN_F4R1_FB6_Msk
     
    #define CAN_F4R1_FB7_Pos   (7U)
     
    #define CAN_F4R1_FB7_Msk   (0x1UL << CAN_F4R1_FB7_Pos)
     
    #define CAN_F4R1_FB7   CAN_F4R1_FB7_Msk
     
    #define CAN_F4R1_FB8_Pos   (8U)
     
    #define CAN_F4R1_FB8_Msk   (0x1UL << CAN_F4R1_FB8_Pos)
     
    #define CAN_F4R1_FB8   CAN_F4R1_FB8_Msk
     
    #define CAN_F4R1_FB9_Pos   (9U)
     
    #define CAN_F4R1_FB9_Msk   (0x1UL << CAN_F4R1_FB9_Pos)
     
    #define CAN_F4R1_FB9   CAN_F4R1_FB9_Msk
     
    #define CAN_F4R1_FB10_Pos   (10U)
     
    #define CAN_F4R1_FB10_Msk   (0x1UL << CAN_F4R1_FB10_Pos)
     
    #define CAN_F4R1_FB10   CAN_F4R1_FB10_Msk
     
    #define CAN_F4R1_FB11_Pos   (11U)
     
    #define CAN_F4R1_FB11_Msk   (0x1UL << CAN_F4R1_FB11_Pos)
     
    #define CAN_F4R1_FB11   CAN_F4R1_FB11_Msk
     
    #define CAN_F4R1_FB12_Pos   (12U)
     
    #define CAN_F4R1_FB12_Msk   (0x1UL << CAN_F4R1_FB12_Pos)
     
    #define CAN_F4R1_FB12   CAN_F4R1_FB12_Msk
     
    #define CAN_F4R1_FB13_Pos   (13U)
     
    #define CAN_F4R1_FB13_Msk   (0x1UL << CAN_F4R1_FB13_Pos)
     
    #define CAN_F4R1_FB13   CAN_F4R1_FB13_Msk
     
    #define CAN_F4R1_FB14_Pos   (14U)
     
    #define CAN_F4R1_FB14_Msk   (0x1UL << CAN_F4R1_FB14_Pos)
     
    #define CAN_F4R1_FB14   CAN_F4R1_FB14_Msk
     
    #define CAN_F4R1_FB15_Pos   (15U)
     
    #define CAN_F4R1_FB15_Msk   (0x1UL << CAN_F4R1_FB15_Pos)
     
    #define CAN_F4R1_FB15   CAN_F4R1_FB15_Msk
     
    #define CAN_F4R1_FB16_Pos   (16U)
     
    #define CAN_F4R1_FB16_Msk   (0x1UL << CAN_F4R1_FB16_Pos)
     
    #define CAN_F4R1_FB16   CAN_F4R1_FB16_Msk
     
    #define CAN_F4R1_FB17_Pos   (17U)
     
    #define CAN_F4R1_FB17_Msk   (0x1UL << CAN_F4R1_FB17_Pos)
     
    #define CAN_F4R1_FB17   CAN_F4R1_FB17_Msk
     
    #define CAN_F4R1_FB18_Pos   (18U)
     
    #define CAN_F4R1_FB18_Msk   (0x1UL << CAN_F4R1_FB18_Pos)
     
    #define CAN_F4R1_FB18   CAN_F4R1_FB18_Msk
     
    #define CAN_F4R1_FB19_Pos   (19U)
     
    #define CAN_F4R1_FB19_Msk   (0x1UL << CAN_F4R1_FB19_Pos)
     
    #define CAN_F4R1_FB19   CAN_F4R1_FB19_Msk
     
    #define CAN_F4R1_FB20_Pos   (20U)
     
    #define CAN_F4R1_FB20_Msk   (0x1UL << CAN_F4R1_FB20_Pos)
     
    #define CAN_F4R1_FB20   CAN_F4R1_FB20_Msk
     
    #define CAN_F4R1_FB21_Pos   (21U)
     
    #define CAN_F4R1_FB21_Msk   (0x1UL << CAN_F4R1_FB21_Pos)
     
    #define CAN_F4R1_FB21   CAN_F4R1_FB21_Msk
     
    #define CAN_F4R1_FB22_Pos   (22U)
     
    #define CAN_F4R1_FB22_Msk   (0x1UL << CAN_F4R1_FB22_Pos)
     
    #define CAN_F4R1_FB22   CAN_F4R1_FB22_Msk
     
    #define CAN_F4R1_FB23_Pos   (23U)
     
    #define CAN_F4R1_FB23_Msk   (0x1UL << CAN_F4R1_FB23_Pos)
     
    #define CAN_F4R1_FB23   CAN_F4R1_FB23_Msk
     
    #define CAN_F4R1_FB24_Pos   (24U)
     
    #define CAN_F4R1_FB24_Msk   (0x1UL << CAN_F4R1_FB24_Pos)
     
    #define CAN_F4R1_FB24   CAN_F4R1_FB24_Msk
     
    #define CAN_F4R1_FB25_Pos   (25U)
     
    #define CAN_F4R1_FB25_Msk   (0x1UL << CAN_F4R1_FB25_Pos)
     
    #define CAN_F4R1_FB25   CAN_F4R1_FB25_Msk
     
    #define CAN_F4R1_FB26_Pos   (26U)
     
    #define CAN_F4R1_FB26_Msk   (0x1UL << CAN_F4R1_FB26_Pos)
     
    #define CAN_F4R1_FB26   CAN_F4R1_FB26_Msk
     
    #define CAN_F4R1_FB27_Pos   (27U)
     
    #define CAN_F4R1_FB27_Msk   (0x1UL << CAN_F4R1_FB27_Pos)
     
    #define CAN_F4R1_FB27   CAN_F4R1_FB27_Msk
     
    #define CAN_F4R1_FB28_Pos   (28U)
     
    #define CAN_F4R1_FB28_Msk   (0x1UL << CAN_F4R1_FB28_Pos)
     
    #define CAN_F4R1_FB28   CAN_F4R1_FB28_Msk
     
    #define CAN_F4R1_FB29_Pos   (29U)
     
    #define CAN_F4R1_FB29_Msk   (0x1UL << CAN_F4R1_FB29_Pos)
     
    #define CAN_F4R1_FB29   CAN_F4R1_FB29_Msk
     
    #define CAN_F4R1_FB30_Pos   (30U)
     
    #define CAN_F4R1_FB30_Msk   (0x1UL << CAN_F4R1_FB30_Pos)
     
    #define CAN_F4R1_FB30   CAN_F4R1_FB30_Msk
     
    #define CAN_F4R1_FB31_Pos   (31U)
     
    #define CAN_F4R1_FB31_Msk   (0x1UL << CAN_F4R1_FB31_Pos)
     
    #define CAN_F4R1_FB31   CAN_F4R1_FB31_Msk
     
    #define CAN_F5R1_FB0_Pos   (0U)
     
    #define CAN_F5R1_FB0_Msk   (0x1UL << CAN_F5R1_FB0_Pos)
     
    #define CAN_F5R1_FB0   CAN_F5R1_FB0_Msk
     
    #define CAN_F5R1_FB1_Pos   (1U)
     
    #define CAN_F5R1_FB1_Msk   (0x1UL << CAN_F5R1_FB1_Pos)
     
    #define CAN_F5R1_FB1   CAN_F5R1_FB1_Msk
     
    #define CAN_F5R1_FB2_Pos   (2U)
     
    #define CAN_F5R1_FB2_Msk   (0x1UL << CAN_F5R1_FB2_Pos)
     
    #define CAN_F5R1_FB2   CAN_F5R1_FB2_Msk
     
    #define CAN_F5R1_FB3_Pos   (3U)
     
    #define CAN_F5R1_FB3_Msk   (0x1UL << CAN_F5R1_FB3_Pos)
     
    #define CAN_F5R1_FB3   CAN_F5R1_FB3_Msk
     
    #define CAN_F5R1_FB4_Pos   (4U)
     
    #define CAN_F5R1_FB4_Msk   (0x1UL << CAN_F5R1_FB4_Pos)
     
    #define CAN_F5R1_FB4   CAN_F5R1_FB4_Msk
     
    #define CAN_F5R1_FB5_Pos   (5U)
     
    #define CAN_F5R1_FB5_Msk   (0x1UL << CAN_F5R1_FB5_Pos)
     
    #define CAN_F5R1_FB5   CAN_F5R1_FB5_Msk
     
    #define CAN_F5R1_FB6_Pos   (6U)
     
    #define CAN_F5R1_FB6_Msk   (0x1UL << CAN_F5R1_FB6_Pos)
     
    #define CAN_F5R1_FB6   CAN_F5R1_FB6_Msk
     
    #define CAN_F5R1_FB7_Pos   (7U)
     
    #define CAN_F5R1_FB7_Msk   (0x1UL << CAN_F5R1_FB7_Pos)
     
    #define CAN_F5R1_FB7   CAN_F5R1_FB7_Msk
     
    #define CAN_F5R1_FB8_Pos   (8U)
     
    #define CAN_F5R1_FB8_Msk   (0x1UL << CAN_F5R1_FB8_Pos)
     
    #define CAN_F5R1_FB8   CAN_F5R1_FB8_Msk
     
    #define CAN_F5R1_FB9_Pos   (9U)
     
    #define CAN_F5R1_FB9_Msk   (0x1UL << CAN_F5R1_FB9_Pos)
     
    #define CAN_F5R1_FB9   CAN_F5R1_FB9_Msk
     
    #define CAN_F5R1_FB10_Pos   (10U)
     
    #define CAN_F5R1_FB10_Msk   (0x1UL << CAN_F5R1_FB10_Pos)
     
    #define CAN_F5R1_FB10   CAN_F5R1_FB10_Msk
     
    #define CAN_F5R1_FB11_Pos   (11U)
     
    #define CAN_F5R1_FB11_Msk   (0x1UL << CAN_F5R1_FB11_Pos)
     
    #define CAN_F5R1_FB11   CAN_F5R1_FB11_Msk
     
    #define CAN_F5R1_FB12_Pos   (12U)
     
    #define CAN_F5R1_FB12_Msk   (0x1UL << CAN_F5R1_FB12_Pos)
     
    #define CAN_F5R1_FB12   CAN_F5R1_FB12_Msk
     
    #define CAN_F5R1_FB13_Pos   (13U)
     
    #define CAN_F5R1_FB13_Msk   (0x1UL << CAN_F5R1_FB13_Pos)
     
    #define CAN_F5R1_FB13   CAN_F5R1_FB13_Msk
     
    #define CAN_F5R1_FB14_Pos   (14U)
     
    #define CAN_F5R1_FB14_Msk   (0x1UL << CAN_F5R1_FB14_Pos)
     
    #define CAN_F5R1_FB14   CAN_F5R1_FB14_Msk
     
    #define CAN_F5R1_FB15_Pos   (15U)
     
    #define CAN_F5R1_FB15_Msk   (0x1UL << CAN_F5R1_FB15_Pos)
     
    #define CAN_F5R1_FB15   CAN_F5R1_FB15_Msk
     
    #define CAN_F5R1_FB16_Pos   (16U)
     
    #define CAN_F5R1_FB16_Msk   (0x1UL << CAN_F5R1_FB16_Pos)
     
    #define CAN_F5R1_FB16   CAN_F5R1_FB16_Msk
     
    #define CAN_F5R1_FB17_Pos   (17U)
     
    #define CAN_F5R1_FB17_Msk   (0x1UL << CAN_F5R1_FB17_Pos)
     
    #define CAN_F5R1_FB17   CAN_F5R1_FB17_Msk
     
    #define CAN_F5R1_FB18_Pos   (18U)
     
    #define CAN_F5R1_FB18_Msk   (0x1UL << CAN_F5R1_FB18_Pos)
     
    #define CAN_F5R1_FB18   CAN_F5R1_FB18_Msk
     
    #define CAN_F5R1_FB19_Pos   (19U)
     
    #define CAN_F5R1_FB19_Msk   (0x1UL << CAN_F5R1_FB19_Pos)
     
    #define CAN_F5R1_FB19   CAN_F5R1_FB19_Msk
     
    #define CAN_F5R1_FB20_Pos   (20U)
     
    #define CAN_F5R1_FB20_Msk   (0x1UL << CAN_F5R1_FB20_Pos)
     
    #define CAN_F5R1_FB20   CAN_F5R1_FB20_Msk
     
    #define CAN_F5R1_FB21_Pos   (21U)
     
    #define CAN_F5R1_FB21_Msk   (0x1UL << CAN_F5R1_FB21_Pos)
     
    #define CAN_F5R1_FB21   CAN_F5R1_FB21_Msk
     
    #define CAN_F5R1_FB22_Pos   (22U)
     
    #define CAN_F5R1_FB22_Msk   (0x1UL << CAN_F5R1_FB22_Pos)
     
    #define CAN_F5R1_FB22   CAN_F5R1_FB22_Msk
     
    #define CAN_F5R1_FB23_Pos   (23U)
     
    #define CAN_F5R1_FB23_Msk   (0x1UL << CAN_F5R1_FB23_Pos)
     
    #define CAN_F5R1_FB23   CAN_F5R1_FB23_Msk
     
    #define CAN_F5R1_FB24_Pos   (24U)
     
    #define CAN_F5R1_FB24_Msk   (0x1UL << CAN_F5R1_FB24_Pos)
     
    #define CAN_F5R1_FB24   CAN_F5R1_FB24_Msk
     
    #define CAN_F5R1_FB25_Pos   (25U)
     
    #define CAN_F5R1_FB25_Msk   (0x1UL << CAN_F5R1_FB25_Pos)
     
    #define CAN_F5R1_FB25   CAN_F5R1_FB25_Msk
     
    #define CAN_F5R1_FB26_Pos   (26U)
     
    #define CAN_F5R1_FB26_Msk   (0x1UL << CAN_F5R1_FB26_Pos)
     
    #define CAN_F5R1_FB26   CAN_F5R1_FB26_Msk
     
    #define CAN_F5R1_FB27_Pos   (27U)
     
    #define CAN_F5R1_FB27_Msk   (0x1UL << CAN_F5R1_FB27_Pos)
     
    #define CAN_F5R1_FB27   CAN_F5R1_FB27_Msk
     
    #define CAN_F5R1_FB28_Pos   (28U)
     
    #define CAN_F5R1_FB28_Msk   (0x1UL << CAN_F5R1_FB28_Pos)
     
    #define CAN_F5R1_FB28   CAN_F5R1_FB28_Msk
     
    #define CAN_F5R1_FB29_Pos   (29U)
     
    #define CAN_F5R1_FB29_Msk   (0x1UL << CAN_F5R1_FB29_Pos)
     
    #define CAN_F5R1_FB29   CAN_F5R1_FB29_Msk
     
    #define CAN_F5R1_FB30_Pos   (30U)
     
    #define CAN_F5R1_FB30_Msk   (0x1UL << CAN_F5R1_FB30_Pos)
     
    #define CAN_F5R1_FB30   CAN_F5R1_FB30_Msk
     
    #define CAN_F5R1_FB31_Pos   (31U)
     
    #define CAN_F5R1_FB31_Msk   (0x1UL << CAN_F5R1_FB31_Pos)
     
    #define CAN_F5R1_FB31   CAN_F5R1_FB31_Msk
     
    #define CAN_F6R1_FB0_Pos   (0U)
     
    #define CAN_F6R1_FB0_Msk   (0x1UL << CAN_F6R1_FB0_Pos)
     
    #define CAN_F6R1_FB0   CAN_F6R1_FB0_Msk
     
    #define CAN_F6R1_FB1_Pos   (1U)
     
    #define CAN_F6R1_FB1_Msk   (0x1UL << CAN_F6R1_FB1_Pos)
     
    #define CAN_F6R1_FB1   CAN_F6R1_FB1_Msk
     
    #define CAN_F6R1_FB2_Pos   (2U)
     
    #define CAN_F6R1_FB2_Msk   (0x1UL << CAN_F6R1_FB2_Pos)
     
    #define CAN_F6R1_FB2   CAN_F6R1_FB2_Msk
     
    #define CAN_F6R1_FB3_Pos   (3U)
     
    #define CAN_F6R1_FB3_Msk   (0x1UL << CAN_F6R1_FB3_Pos)
     
    #define CAN_F6R1_FB3   CAN_F6R1_FB3_Msk
     
    #define CAN_F6R1_FB4_Pos   (4U)
     
    #define CAN_F6R1_FB4_Msk   (0x1UL << CAN_F6R1_FB4_Pos)
     
    #define CAN_F6R1_FB4   CAN_F6R1_FB4_Msk
     
    #define CAN_F6R1_FB5_Pos   (5U)
     
    #define CAN_F6R1_FB5_Msk   (0x1UL << CAN_F6R1_FB5_Pos)
     
    #define CAN_F6R1_FB5   CAN_F6R1_FB5_Msk
     
    #define CAN_F6R1_FB6_Pos   (6U)
     
    #define CAN_F6R1_FB6_Msk   (0x1UL << CAN_F6R1_FB6_Pos)
     
    #define CAN_F6R1_FB6   CAN_F6R1_FB6_Msk
     
    #define CAN_F6R1_FB7_Pos   (7U)
     
    #define CAN_F6R1_FB7_Msk   (0x1UL << CAN_F6R1_FB7_Pos)
     
    #define CAN_F6R1_FB7   CAN_F6R1_FB7_Msk
     
    #define CAN_F6R1_FB8_Pos   (8U)
     
    #define CAN_F6R1_FB8_Msk   (0x1UL << CAN_F6R1_FB8_Pos)
     
    #define CAN_F6R1_FB8   CAN_F6R1_FB8_Msk
     
    #define CAN_F6R1_FB9_Pos   (9U)
     
    #define CAN_F6R1_FB9_Msk   (0x1UL << CAN_F6R1_FB9_Pos)
     
    #define CAN_F6R1_FB9   CAN_F6R1_FB9_Msk
     
    #define CAN_F6R1_FB10_Pos   (10U)
     
    #define CAN_F6R1_FB10_Msk   (0x1UL << CAN_F6R1_FB10_Pos)
     
    #define CAN_F6R1_FB10   CAN_F6R1_FB10_Msk
     
    #define CAN_F6R1_FB11_Pos   (11U)
     
    #define CAN_F6R1_FB11_Msk   (0x1UL << CAN_F6R1_FB11_Pos)
     
    #define CAN_F6R1_FB11   CAN_F6R1_FB11_Msk
     
    #define CAN_F6R1_FB12_Pos   (12U)
     
    #define CAN_F6R1_FB12_Msk   (0x1UL << CAN_F6R1_FB12_Pos)
     
    #define CAN_F6R1_FB12   CAN_F6R1_FB12_Msk
     
    #define CAN_F6R1_FB13_Pos   (13U)
     
    #define CAN_F6R1_FB13_Msk   (0x1UL << CAN_F6R1_FB13_Pos)
     
    #define CAN_F6R1_FB13   CAN_F6R1_FB13_Msk
     
    #define CAN_F6R1_FB14_Pos   (14U)
     
    #define CAN_F6R1_FB14_Msk   (0x1UL << CAN_F6R1_FB14_Pos)
     
    #define CAN_F6R1_FB14   CAN_F6R1_FB14_Msk
     
    #define CAN_F6R1_FB15_Pos   (15U)
     
    #define CAN_F6R1_FB15_Msk   (0x1UL << CAN_F6R1_FB15_Pos)
     
    #define CAN_F6R1_FB15   CAN_F6R1_FB15_Msk
     
    #define CAN_F6R1_FB16_Pos   (16U)
     
    #define CAN_F6R1_FB16_Msk   (0x1UL << CAN_F6R1_FB16_Pos)
     
    #define CAN_F6R1_FB16   CAN_F6R1_FB16_Msk
     
    #define CAN_F6R1_FB17_Pos   (17U)
     
    #define CAN_F6R1_FB17_Msk   (0x1UL << CAN_F6R1_FB17_Pos)
     
    #define CAN_F6R1_FB17   CAN_F6R1_FB17_Msk
     
    #define CAN_F6R1_FB18_Pos   (18U)
     
    #define CAN_F6R1_FB18_Msk   (0x1UL << CAN_F6R1_FB18_Pos)
     
    #define CAN_F6R1_FB18   CAN_F6R1_FB18_Msk
     
    #define CAN_F6R1_FB19_Pos   (19U)
     
    #define CAN_F6R1_FB19_Msk   (0x1UL << CAN_F6R1_FB19_Pos)
     
    #define CAN_F6R1_FB19   CAN_F6R1_FB19_Msk
     
    #define CAN_F6R1_FB20_Pos   (20U)
     
    #define CAN_F6R1_FB20_Msk   (0x1UL << CAN_F6R1_FB20_Pos)
     
    #define CAN_F6R1_FB20   CAN_F6R1_FB20_Msk
     
    #define CAN_F6R1_FB21_Pos   (21U)
     
    #define CAN_F6R1_FB21_Msk   (0x1UL << CAN_F6R1_FB21_Pos)
     
    #define CAN_F6R1_FB21   CAN_F6R1_FB21_Msk
     
    #define CAN_F6R1_FB22_Pos   (22U)
     
    #define CAN_F6R1_FB22_Msk   (0x1UL << CAN_F6R1_FB22_Pos)
     
    #define CAN_F6R1_FB22   CAN_F6R1_FB22_Msk
     
    #define CAN_F6R1_FB23_Pos   (23U)
     
    #define CAN_F6R1_FB23_Msk   (0x1UL << CAN_F6R1_FB23_Pos)
     
    #define CAN_F6R1_FB23   CAN_F6R1_FB23_Msk
     
    #define CAN_F6R1_FB24_Pos   (24U)
     
    #define CAN_F6R1_FB24_Msk   (0x1UL << CAN_F6R1_FB24_Pos)
     
    #define CAN_F6R1_FB24   CAN_F6R1_FB24_Msk
     
    #define CAN_F6R1_FB25_Pos   (25U)
     
    #define CAN_F6R1_FB25_Msk   (0x1UL << CAN_F6R1_FB25_Pos)
     
    #define CAN_F6R1_FB25   CAN_F6R1_FB25_Msk
     
    #define CAN_F6R1_FB26_Pos   (26U)
     
    #define CAN_F6R1_FB26_Msk   (0x1UL << CAN_F6R1_FB26_Pos)
     
    #define CAN_F6R1_FB26   CAN_F6R1_FB26_Msk
     
    #define CAN_F6R1_FB27_Pos   (27U)
     
    #define CAN_F6R1_FB27_Msk   (0x1UL << CAN_F6R1_FB27_Pos)
     
    #define CAN_F6R1_FB27   CAN_F6R1_FB27_Msk
     
    #define CAN_F6R1_FB28_Pos   (28U)
     
    #define CAN_F6R1_FB28_Msk   (0x1UL << CAN_F6R1_FB28_Pos)
     
    #define CAN_F6R1_FB28   CAN_F6R1_FB28_Msk
     
    #define CAN_F6R1_FB29_Pos   (29U)
     
    #define CAN_F6R1_FB29_Msk   (0x1UL << CAN_F6R1_FB29_Pos)
     
    #define CAN_F6R1_FB29   CAN_F6R1_FB29_Msk
     
    #define CAN_F6R1_FB30_Pos   (30U)
     
    #define CAN_F6R1_FB30_Msk   (0x1UL << CAN_F6R1_FB30_Pos)
     
    #define CAN_F6R1_FB30   CAN_F6R1_FB30_Msk
     
    #define CAN_F6R1_FB31_Pos   (31U)
     
    #define CAN_F6R1_FB31_Msk   (0x1UL << CAN_F6R1_FB31_Pos)
     
    #define CAN_F6R1_FB31   CAN_F6R1_FB31_Msk
     
    #define CAN_F7R1_FB0_Pos   (0U)
     
    #define CAN_F7R1_FB0_Msk   (0x1UL << CAN_F7R1_FB0_Pos)
     
    #define CAN_F7R1_FB0   CAN_F7R1_FB0_Msk
     
    #define CAN_F7R1_FB1_Pos   (1U)
     
    #define CAN_F7R1_FB1_Msk   (0x1UL << CAN_F7R1_FB1_Pos)
     
    #define CAN_F7R1_FB1   CAN_F7R1_FB1_Msk
     
    #define CAN_F7R1_FB2_Pos   (2U)
     
    #define CAN_F7R1_FB2_Msk   (0x1UL << CAN_F7R1_FB2_Pos)
     
    #define CAN_F7R1_FB2   CAN_F7R1_FB2_Msk
     
    #define CAN_F7R1_FB3_Pos   (3U)
     
    #define CAN_F7R1_FB3_Msk   (0x1UL << CAN_F7R1_FB3_Pos)
     
    #define CAN_F7R1_FB3   CAN_F7R1_FB3_Msk
     
    #define CAN_F7R1_FB4_Pos   (4U)
     
    #define CAN_F7R1_FB4_Msk   (0x1UL << CAN_F7R1_FB4_Pos)
     
    #define CAN_F7R1_FB4   CAN_F7R1_FB4_Msk
     
    #define CAN_F7R1_FB5_Pos   (5U)
     
    #define CAN_F7R1_FB5_Msk   (0x1UL << CAN_F7R1_FB5_Pos)
     
    #define CAN_F7R1_FB5   CAN_F7R1_FB5_Msk
     
    #define CAN_F7R1_FB6_Pos   (6U)
     
    #define CAN_F7R1_FB6_Msk   (0x1UL << CAN_F7R1_FB6_Pos)
     
    #define CAN_F7R1_FB6   CAN_F7R1_FB6_Msk
     
    #define CAN_F7R1_FB7_Pos   (7U)
     
    #define CAN_F7R1_FB7_Msk   (0x1UL << CAN_F7R1_FB7_Pos)
     
    #define CAN_F7R1_FB7   CAN_F7R1_FB7_Msk
     
    #define CAN_F7R1_FB8_Pos   (8U)
     
    #define CAN_F7R1_FB8_Msk   (0x1UL << CAN_F7R1_FB8_Pos)
     
    #define CAN_F7R1_FB8   CAN_F7R1_FB8_Msk
     
    #define CAN_F7R1_FB9_Pos   (9U)
     
    #define CAN_F7R1_FB9_Msk   (0x1UL << CAN_F7R1_FB9_Pos)
     
    #define CAN_F7R1_FB9   CAN_F7R1_FB9_Msk
     
    #define CAN_F7R1_FB10_Pos   (10U)
     
    #define CAN_F7R1_FB10_Msk   (0x1UL << CAN_F7R1_FB10_Pos)
     
    #define CAN_F7R1_FB10   CAN_F7R1_FB10_Msk
     
    #define CAN_F7R1_FB11_Pos   (11U)
     
    #define CAN_F7R1_FB11_Msk   (0x1UL << CAN_F7R1_FB11_Pos)
     
    #define CAN_F7R1_FB11   CAN_F7R1_FB11_Msk
     
    #define CAN_F7R1_FB12_Pos   (12U)
     
    #define CAN_F7R1_FB12_Msk   (0x1UL << CAN_F7R1_FB12_Pos)
     
    #define CAN_F7R1_FB12   CAN_F7R1_FB12_Msk
     
    #define CAN_F7R1_FB13_Pos   (13U)
     
    #define CAN_F7R1_FB13_Msk   (0x1UL << CAN_F7R1_FB13_Pos)
     
    #define CAN_F7R1_FB13   CAN_F7R1_FB13_Msk
     
    #define CAN_F7R1_FB14_Pos   (14U)
     
    #define CAN_F7R1_FB14_Msk   (0x1UL << CAN_F7R1_FB14_Pos)
     
    #define CAN_F7R1_FB14   CAN_F7R1_FB14_Msk
     
    #define CAN_F7R1_FB15_Pos   (15U)
     
    #define CAN_F7R1_FB15_Msk   (0x1UL << CAN_F7R1_FB15_Pos)
     
    #define CAN_F7R1_FB15   CAN_F7R1_FB15_Msk
     
    #define CAN_F7R1_FB16_Pos   (16U)
     
    #define CAN_F7R1_FB16_Msk   (0x1UL << CAN_F7R1_FB16_Pos)
     
    #define CAN_F7R1_FB16   CAN_F7R1_FB16_Msk
     
    #define CAN_F7R1_FB17_Pos   (17U)
     
    #define CAN_F7R1_FB17_Msk   (0x1UL << CAN_F7R1_FB17_Pos)
     
    #define CAN_F7R1_FB17   CAN_F7R1_FB17_Msk
     
    #define CAN_F7R1_FB18_Pos   (18U)
     
    #define CAN_F7R1_FB18_Msk   (0x1UL << CAN_F7R1_FB18_Pos)
     
    #define CAN_F7R1_FB18   CAN_F7R1_FB18_Msk
     
    #define CAN_F7R1_FB19_Pos   (19U)
     
    #define CAN_F7R1_FB19_Msk   (0x1UL << CAN_F7R1_FB19_Pos)
     
    #define CAN_F7R1_FB19   CAN_F7R1_FB19_Msk
     
    #define CAN_F7R1_FB20_Pos   (20U)
     
    #define CAN_F7R1_FB20_Msk   (0x1UL << CAN_F7R1_FB20_Pos)
     
    #define CAN_F7R1_FB20   CAN_F7R1_FB20_Msk
     
    #define CAN_F7R1_FB21_Pos   (21U)
     
    #define CAN_F7R1_FB21_Msk   (0x1UL << CAN_F7R1_FB21_Pos)
     
    #define CAN_F7R1_FB21   CAN_F7R1_FB21_Msk
     
    #define CAN_F7R1_FB22_Pos   (22U)
     
    #define CAN_F7R1_FB22_Msk   (0x1UL << CAN_F7R1_FB22_Pos)
     
    #define CAN_F7R1_FB22   CAN_F7R1_FB22_Msk
     
    #define CAN_F7R1_FB23_Pos   (23U)
     
    #define CAN_F7R1_FB23_Msk   (0x1UL << CAN_F7R1_FB23_Pos)
     
    #define CAN_F7R1_FB23   CAN_F7R1_FB23_Msk
     
    #define CAN_F7R1_FB24_Pos   (24U)
     
    #define CAN_F7R1_FB24_Msk   (0x1UL << CAN_F7R1_FB24_Pos)
     
    #define CAN_F7R1_FB24   CAN_F7R1_FB24_Msk
     
    #define CAN_F7R1_FB25_Pos   (25U)
     
    #define CAN_F7R1_FB25_Msk   (0x1UL << CAN_F7R1_FB25_Pos)
     
    #define CAN_F7R1_FB25   CAN_F7R1_FB25_Msk
     
    #define CAN_F7R1_FB26_Pos   (26U)
     
    #define CAN_F7R1_FB26_Msk   (0x1UL << CAN_F7R1_FB26_Pos)
     
    #define CAN_F7R1_FB26   CAN_F7R1_FB26_Msk
     
    #define CAN_F7R1_FB27_Pos   (27U)
     
    #define CAN_F7R1_FB27_Msk   (0x1UL << CAN_F7R1_FB27_Pos)
     
    #define CAN_F7R1_FB27   CAN_F7R1_FB27_Msk
     
    #define CAN_F7R1_FB28_Pos   (28U)
     
    #define CAN_F7R1_FB28_Msk   (0x1UL << CAN_F7R1_FB28_Pos)
     
    #define CAN_F7R1_FB28   CAN_F7R1_FB28_Msk
     
    #define CAN_F7R1_FB29_Pos   (29U)
     
    #define CAN_F7R1_FB29_Msk   (0x1UL << CAN_F7R1_FB29_Pos)
     
    #define CAN_F7R1_FB29   CAN_F7R1_FB29_Msk
     
    #define CAN_F7R1_FB30_Pos   (30U)
     
    #define CAN_F7R1_FB30_Msk   (0x1UL << CAN_F7R1_FB30_Pos)
     
    #define CAN_F7R1_FB30   CAN_F7R1_FB30_Msk
     
    #define CAN_F7R1_FB31_Pos   (31U)
     
    #define CAN_F7R1_FB31_Msk   (0x1UL << CAN_F7R1_FB31_Pos)
     
    #define CAN_F7R1_FB31   CAN_F7R1_FB31_Msk
     
    #define CAN_F8R1_FB0_Pos   (0U)
     
    #define CAN_F8R1_FB0_Msk   (0x1UL << CAN_F8R1_FB0_Pos)
     
    #define CAN_F8R1_FB0   CAN_F8R1_FB0_Msk
     
    #define CAN_F8R1_FB1_Pos   (1U)
     
    #define CAN_F8R1_FB1_Msk   (0x1UL << CAN_F8R1_FB1_Pos)
     
    #define CAN_F8R1_FB1   CAN_F8R1_FB1_Msk
     
    #define CAN_F8R1_FB2_Pos   (2U)
     
    #define CAN_F8R1_FB2_Msk   (0x1UL << CAN_F8R1_FB2_Pos)
     
    #define CAN_F8R1_FB2   CAN_F8R1_FB2_Msk
     
    #define CAN_F8R1_FB3_Pos   (3U)
     
    #define CAN_F8R1_FB3_Msk   (0x1UL << CAN_F8R1_FB3_Pos)
     
    #define CAN_F8R1_FB3   CAN_F8R1_FB3_Msk
     
    #define CAN_F8R1_FB4_Pos   (4U)
     
    #define CAN_F8R1_FB4_Msk   (0x1UL << CAN_F8R1_FB4_Pos)
     
    #define CAN_F8R1_FB4   CAN_F8R1_FB4_Msk
     
    #define CAN_F8R1_FB5_Pos   (5U)
     
    #define CAN_F8R1_FB5_Msk   (0x1UL << CAN_F8R1_FB5_Pos)
     
    #define CAN_F8R1_FB5   CAN_F8R1_FB5_Msk
     
    #define CAN_F8R1_FB6_Pos   (6U)
     
    #define CAN_F8R1_FB6_Msk   (0x1UL << CAN_F8R1_FB6_Pos)
     
    #define CAN_F8R1_FB6   CAN_F8R1_FB6_Msk
     
    #define CAN_F8R1_FB7_Pos   (7U)
     
    #define CAN_F8R1_FB7_Msk   (0x1UL << CAN_F8R1_FB7_Pos)
     
    #define CAN_F8R1_FB7   CAN_F8R1_FB7_Msk
     
    #define CAN_F8R1_FB8_Pos   (8U)
     
    #define CAN_F8R1_FB8_Msk   (0x1UL << CAN_F8R1_FB8_Pos)
     
    #define CAN_F8R1_FB8   CAN_F8R1_FB8_Msk
     
    #define CAN_F8R1_FB9_Pos   (9U)
     
    #define CAN_F8R1_FB9_Msk   (0x1UL << CAN_F8R1_FB9_Pos)
     
    #define CAN_F8R1_FB9   CAN_F8R1_FB9_Msk
     
    #define CAN_F8R1_FB10_Pos   (10U)
     
    #define CAN_F8R1_FB10_Msk   (0x1UL << CAN_F8R1_FB10_Pos)
     
    #define CAN_F8R1_FB10   CAN_F8R1_FB10_Msk
     
    #define CAN_F8R1_FB11_Pos   (11U)
     
    #define CAN_F8R1_FB11_Msk   (0x1UL << CAN_F8R1_FB11_Pos)
     
    #define CAN_F8R1_FB11   CAN_F8R1_FB11_Msk
     
    #define CAN_F8R1_FB12_Pos   (12U)
     
    #define CAN_F8R1_FB12_Msk   (0x1UL << CAN_F8R1_FB12_Pos)
     
    #define CAN_F8R1_FB12   CAN_F8R1_FB12_Msk
     
    #define CAN_F8R1_FB13_Pos   (13U)
     
    #define CAN_F8R1_FB13_Msk   (0x1UL << CAN_F8R1_FB13_Pos)
     
    #define CAN_F8R1_FB13   CAN_F8R1_FB13_Msk
     
    #define CAN_F8R1_FB14_Pos   (14U)
     
    #define CAN_F8R1_FB14_Msk   (0x1UL << CAN_F8R1_FB14_Pos)
     
    #define CAN_F8R1_FB14   CAN_F8R1_FB14_Msk
     
    #define CAN_F8R1_FB15_Pos   (15U)
     
    #define CAN_F8R1_FB15_Msk   (0x1UL << CAN_F8R1_FB15_Pos)
     
    #define CAN_F8R1_FB15   CAN_F8R1_FB15_Msk
     
    #define CAN_F8R1_FB16_Pos   (16U)
     
    #define CAN_F8R1_FB16_Msk   (0x1UL << CAN_F8R1_FB16_Pos)
     
    #define CAN_F8R1_FB16   CAN_F8R1_FB16_Msk
     
    #define CAN_F8R1_FB17_Pos   (17U)
     
    #define CAN_F8R1_FB17_Msk   (0x1UL << CAN_F8R1_FB17_Pos)
     
    #define CAN_F8R1_FB17   CAN_F8R1_FB17_Msk
     
    #define CAN_F8R1_FB18_Pos   (18U)
     
    #define CAN_F8R1_FB18_Msk   (0x1UL << CAN_F8R1_FB18_Pos)
     
    #define CAN_F8R1_FB18   CAN_F8R1_FB18_Msk
     
    #define CAN_F8R1_FB19_Pos   (19U)
     
    #define CAN_F8R1_FB19_Msk   (0x1UL << CAN_F8R1_FB19_Pos)
     
    #define CAN_F8R1_FB19   CAN_F8R1_FB19_Msk
     
    #define CAN_F8R1_FB20_Pos   (20U)
     
    #define CAN_F8R1_FB20_Msk   (0x1UL << CAN_F8R1_FB20_Pos)
     
    #define CAN_F8R1_FB20   CAN_F8R1_FB20_Msk
     
    #define CAN_F8R1_FB21_Pos   (21U)
     
    #define CAN_F8R1_FB21_Msk   (0x1UL << CAN_F8R1_FB21_Pos)
     
    #define CAN_F8R1_FB21   CAN_F8R1_FB21_Msk
     
    #define CAN_F8R1_FB22_Pos   (22U)
     
    #define CAN_F8R1_FB22_Msk   (0x1UL << CAN_F8R1_FB22_Pos)
     
    #define CAN_F8R1_FB22   CAN_F8R1_FB22_Msk
     
    #define CAN_F8R1_FB23_Pos   (23U)
     
    #define CAN_F8R1_FB23_Msk   (0x1UL << CAN_F8R1_FB23_Pos)
     
    #define CAN_F8R1_FB23   CAN_F8R1_FB23_Msk
     
    #define CAN_F8R1_FB24_Pos   (24U)
     
    #define CAN_F8R1_FB24_Msk   (0x1UL << CAN_F8R1_FB24_Pos)
     
    #define CAN_F8R1_FB24   CAN_F8R1_FB24_Msk
     
    #define CAN_F8R1_FB25_Pos   (25U)
     
    #define CAN_F8R1_FB25_Msk   (0x1UL << CAN_F8R1_FB25_Pos)
     
    #define CAN_F8R1_FB25   CAN_F8R1_FB25_Msk
     
    #define CAN_F8R1_FB26_Pos   (26U)
     
    #define CAN_F8R1_FB26_Msk   (0x1UL << CAN_F8R1_FB26_Pos)
     
    #define CAN_F8R1_FB26   CAN_F8R1_FB26_Msk
     
    #define CAN_F8R1_FB27_Pos   (27U)
     
    #define CAN_F8R1_FB27_Msk   (0x1UL << CAN_F8R1_FB27_Pos)
     
    #define CAN_F8R1_FB27   CAN_F8R1_FB27_Msk
     
    #define CAN_F8R1_FB28_Pos   (28U)
     
    #define CAN_F8R1_FB28_Msk   (0x1UL << CAN_F8R1_FB28_Pos)
     
    #define CAN_F8R1_FB28   CAN_F8R1_FB28_Msk
     
    #define CAN_F8R1_FB29_Pos   (29U)
     
    #define CAN_F8R1_FB29_Msk   (0x1UL << CAN_F8R1_FB29_Pos)
     
    #define CAN_F8R1_FB29   CAN_F8R1_FB29_Msk
     
    #define CAN_F8R1_FB30_Pos   (30U)
     
    #define CAN_F8R1_FB30_Msk   (0x1UL << CAN_F8R1_FB30_Pos)
     
    #define CAN_F8R1_FB30   CAN_F8R1_FB30_Msk
     
    #define CAN_F8R1_FB31_Pos   (31U)
     
    #define CAN_F8R1_FB31_Msk   (0x1UL << CAN_F8R1_FB31_Pos)
     
    #define CAN_F8R1_FB31   CAN_F8R1_FB31_Msk
     
    #define CAN_F9R1_FB0_Pos   (0U)
     
    #define CAN_F9R1_FB0_Msk   (0x1UL << CAN_F9R1_FB0_Pos)
     
    #define CAN_F9R1_FB0   CAN_F9R1_FB0_Msk
     
    #define CAN_F9R1_FB1_Pos   (1U)
     
    #define CAN_F9R1_FB1_Msk   (0x1UL << CAN_F9R1_FB1_Pos)
     
    #define CAN_F9R1_FB1   CAN_F9R1_FB1_Msk
     
    #define CAN_F9R1_FB2_Pos   (2U)
     
    #define CAN_F9R1_FB2_Msk   (0x1UL << CAN_F9R1_FB2_Pos)
     
    #define CAN_F9R1_FB2   CAN_F9R1_FB2_Msk
     
    #define CAN_F9R1_FB3_Pos   (3U)
     
    #define CAN_F9R1_FB3_Msk   (0x1UL << CAN_F9R1_FB3_Pos)
     
    #define CAN_F9R1_FB3   CAN_F9R1_FB3_Msk
     
    #define CAN_F9R1_FB4_Pos   (4U)
     
    #define CAN_F9R1_FB4_Msk   (0x1UL << CAN_F9R1_FB4_Pos)
     
    #define CAN_F9R1_FB4   CAN_F9R1_FB4_Msk
     
    #define CAN_F9R1_FB5_Pos   (5U)
     
    #define CAN_F9R1_FB5_Msk   (0x1UL << CAN_F9R1_FB5_Pos)
     
    #define CAN_F9R1_FB5   CAN_F9R1_FB5_Msk
     
    #define CAN_F9R1_FB6_Pos   (6U)
     
    #define CAN_F9R1_FB6_Msk   (0x1UL << CAN_F9R1_FB6_Pos)
     
    #define CAN_F9R1_FB6   CAN_F9R1_FB6_Msk
     
    #define CAN_F9R1_FB7_Pos   (7U)
     
    #define CAN_F9R1_FB7_Msk   (0x1UL << CAN_F9R1_FB7_Pos)
     
    #define CAN_F9R1_FB7   CAN_F9R1_FB7_Msk
     
    #define CAN_F9R1_FB8_Pos   (8U)
     
    #define CAN_F9R1_FB8_Msk   (0x1UL << CAN_F9R1_FB8_Pos)
     
    #define CAN_F9R1_FB8   CAN_F9R1_FB8_Msk
     
    #define CAN_F9R1_FB9_Pos   (9U)
     
    #define CAN_F9R1_FB9_Msk   (0x1UL << CAN_F9R1_FB9_Pos)
     
    #define CAN_F9R1_FB9   CAN_F9R1_FB9_Msk
     
    #define CAN_F9R1_FB10_Pos   (10U)
     
    #define CAN_F9R1_FB10_Msk   (0x1UL << CAN_F9R1_FB10_Pos)
     
    #define CAN_F9R1_FB10   CAN_F9R1_FB10_Msk
     
    #define CAN_F9R1_FB11_Pos   (11U)
     
    #define CAN_F9R1_FB11_Msk   (0x1UL << CAN_F9R1_FB11_Pos)
     
    #define CAN_F9R1_FB11   CAN_F9R1_FB11_Msk
     
    #define CAN_F9R1_FB12_Pos   (12U)
     
    #define CAN_F9R1_FB12_Msk   (0x1UL << CAN_F9R1_FB12_Pos)
     
    #define CAN_F9R1_FB12   CAN_F9R1_FB12_Msk
     
    #define CAN_F9R1_FB13_Pos   (13U)
     
    #define CAN_F9R1_FB13_Msk   (0x1UL << CAN_F9R1_FB13_Pos)
     
    #define CAN_F9R1_FB13   CAN_F9R1_FB13_Msk
     
    #define CAN_F9R1_FB14_Pos   (14U)
     
    #define CAN_F9R1_FB14_Msk   (0x1UL << CAN_F9R1_FB14_Pos)
     
    #define CAN_F9R1_FB14   CAN_F9R1_FB14_Msk
     
    #define CAN_F9R1_FB15_Pos   (15U)
     
    #define CAN_F9R1_FB15_Msk   (0x1UL << CAN_F9R1_FB15_Pos)
     
    #define CAN_F9R1_FB15   CAN_F9R1_FB15_Msk
     
    #define CAN_F9R1_FB16_Pos   (16U)
     
    #define CAN_F9R1_FB16_Msk   (0x1UL << CAN_F9R1_FB16_Pos)
     
    #define CAN_F9R1_FB16   CAN_F9R1_FB16_Msk
     
    #define CAN_F9R1_FB17_Pos   (17U)
     
    #define CAN_F9R1_FB17_Msk   (0x1UL << CAN_F9R1_FB17_Pos)
     
    #define CAN_F9R1_FB17   CAN_F9R1_FB17_Msk
     
    #define CAN_F9R1_FB18_Pos   (18U)
     
    #define CAN_F9R1_FB18_Msk   (0x1UL << CAN_F9R1_FB18_Pos)
     
    #define CAN_F9R1_FB18   CAN_F9R1_FB18_Msk
     
    #define CAN_F9R1_FB19_Pos   (19U)
     
    #define CAN_F9R1_FB19_Msk   (0x1UL << CAN_F9R1_FB19_Pos)
     
    #define CAN_F9R1_FB19   CAN_F9R1_FB19_Msk
     
    #define CAN_F9R1_FB20_Pos   (20U)
     
    #define CAN_F9R1_FB20_Msk   (0x1UL << CAN_F9R1_FB20_Pos)
     
    #define CAN_F9R1_FB20   CAN_F9R1_FB20_Msk
     
    #define CAN_F9R1_FB21_Pos   (21U)
     
    #define CAN_F9R1_FB21_Msk   (0x1UL << CAN_F9R1_FB21_Pos)
     
    #define CAN_F9R1_FB21   CAN_F9R1_FB21_Msk
     
    #define CAN_F9R1_FB22_Pos   (22U)
     
    #define CAN_F9R1_FB22_Msk   (0x1UL << CAN_F9R1_FB22_Pos)
     
    #define CAN_F9R1_FB22   CAN_F9R1_FB22_Msk
     
    #define CAN_F9R1_FB23_Pos   (23U)
     
    #define CAN_F9R1_FB23_Msk   (0x1UL << CAN_F9R1_FB23_Pos)
     
    #define CAN_F9R1_FB23   CAN_F9R1_FB23_Msk
     
    #define CAN_F9R1_FB24_Pos   (24U)
     
    #define CAN_F9R1_FB24_Msk   (0x1UL << CAN_F9R1_FB24_Pos)
     
    #define CAN_F9R1_FB24   CAN_F9R1_FB24_Msk
     
    #define CAN_F9R1_FB25_Pos   (25U)
     
    #define CAN_F9R1_FB25_Msk   (0x1UL << CAN_F9R1_FB25_Pos)
     
    #define CAN_F9R1_FB25   CAN_F9R1_FB25_Msk
     
    #define CAN_F9R1_FB26_Pos   (26U)
     
    #define CAN_F9R1_FB26_Msk   (0x1UL << CAN_F9R1_FB26_Pos)
     
    #define CAN_F9R1_FB26   CAN_F9R1_FB26_Msk
     
    #define CAN_F9R1_FB27_Pos   (27U)
     
    #define CAN_F9R1_FB27_Msk   (0x1UL << CAN_F9R1_FB27_Pos)
     
    #define CAN_F9R1_FB27   CAN_F9R1_FB27_Msk
     
    #define CAN_F9R1_FB28_Pos   (28U)
     
    #define CAN_F9R1_FB28_Msk   (0x1UL << CAN_F9R1_FB28_Pos)
     
    #define CAN_F9R1_FB28   CAN_F9R1_FB28_Msk
     
    #define CAN_F9R1_FB29_Pos   (29U)
     
    #define CAN_F9R1_FB29_Msk   (0x1UL << CAN_F9R1_FB29_Pos)
     
    #define CAN_F9R1_FB29   CAN_F9R1_FB29_Msk
     
    #define CAN_F9R1_FB30_Pos   (30U)
     
    #define CAN_F9R1_FB30_Msk   (0x1UL << CAN_F9R1_FB30_Pos)
     
    #define CAN_F9R1_FB30   CAN_F9R1_FB30_Msk
     
    #define CAN_F9R1_FB31_Pos   (31U)
     
    #define CAN_F9R1_FB31_Msk   (0x1UL << CAN_F9R1_FB31_Pos)
     
    #define CAN_F9R1_FB31   CAN_F9R1_FB31_Msk
     
    #define CAN_F10R1_FB0_Pos   (0U)
     
    #define CAN_F10R1_FB0_Msk   (0x1UL << CAN_F10R1_FB0_Pos)
     
    #define CAN_F10R1_FB0   CAN_F10R1_FB0_Msk
     
    #define CAN_F10R1_FB1_Pos   (1U)
     
    #define CAN_F10R1_FB1_Msk   (0x1UL << CAN_F10R1_FB1_Pos)
     
    #define CAN_F10R1_FB1   CAN_F10R1_FB1_Msk
     
    #define CAN_F10R1_FB2_Pos   (2U)
     
    #define CAN_F10R1_FB2_Msk   (0x1UL << CAN_F10R1_FB2_Pos)
     
    #define CAN_F10R1_FB2   CAN_F10R1_FB2_Msk
     
    #define CAN_F10R1_FB3_Pos   (3U)
     
    #define CAN_F10R1_FB3_Msk   (0x1UL << CAN_F10R1_FB3_Pos)
     
    #define CAN_F10R1_FB3   CAN_F10R1_FB3_Msk
     
    #define CAN_F10R1_FB4_Pos   (4U)
     
    #define CAN_F10R1_FB4_Msk   (0x1UL << CAN_F10R1_FB4_Pos)
     
    #define CAN_F10R1_FB4   CAN_F10R1_FB4_Msk
     
    #define CAN_F10R1_FB5_Pos   (5U)
     
    #define CAN_F10R1_FB5_Msk   (0x1UL << CAN_F10R1_FB5_Pos)
     
    #define CAN_F10R1_FB5   CAN_F10R1_FB5_Msk
     
    #define CAN_F10R1_FB6_Pos   (6U)
     
    #define CAN_F10R1_FB6_Msk   (0x1UL << CAN_F10R1_FB6_Pos)
     
    #define CAN_F10R1_FB6   CAN_F10R1_FB6_Msk
     
    #define CAN_F10R1_FB7_Pos   (7U)
     
    #define CAN_F10R1_FB7_Msk   (0x1UL << CAN_F10R1_FB7_Pos)
     
    #define CAN_F10R1_FB7   CAN_F10R1_FB7_Msk
     
    #define CAN_F10R1_FB8_Pos   (8U)
     
    #define CAN_F10R1_FB8_Msk   (0x1UL << CAN_F10R1_FB8_Pos)
     
    #define CAN_F10R1_FB8   CAN_F10R1_FB8_Msk
     
    #define CAN_F10R1_FB9_Pos   (9U)
     
    #define CAN_F10R1_FB9_Msk   (0x1UL << CAN_F10R1_FB9_Pos)
     
    #define CAN_F10R1_FB9   CAN_F10R1_FB9_Msk
     
    #define CAN_F10R1_FB10_Pos   (10U)
     
    #define CAN_F10R1_FB10_Msk   (0x1UL << CAN_F10R1_FB10_Pos)
     
    #define CAN_F10R1_FB10   CAN_F10R1_FB10_Msk
     
    #define CAN_F10R1_FB11_Pos   (11U)
     
    #define CAN_F10R1_FB11_Msk   (0x1UL << CAN_F10R1_FB11_Pos)
     
    #define CAN_F10R1_FB11   CAN_F10R1_FB11_Msk
     
    #define CAN_F10R1_FB12_Pos   (12U)
     
    #define CAN_F10R1_FB12_Msk   (0x1UL << CAN_F10R1_FB12_Pos)
     
    #define CAN_F10R1_FB12   CAN_F10R1_FB12_Msk
     
    #define CAN_F10R1_FB13_Pos   (13U)
     
    #define CAN_F10R1_FB13_Msk   (0x1UL << CAN_F10R1_FB13_Pos)
     
    #define CAN_F10R1_FB13   CAN_F10R1_FB13_Msk
     
    #define CAN_F10R1_FB14_Pos   (14U)
     
    #define CAN_F10R1_FB14_Msk   (0x1UL << CAN_F10R1_FB14_Pos)
     
    #define CAN_F10R1_FB14   CAN_F10R1_FB14_Msk
     
    #define CAN_F10R1_FB15_Pos   (15U)
     
    #define CAN_F10R1_FB15_Msk   (0x1UL << CAN_F10R1_FB15_Pos)
     
    #define CAN_F10R1_FB15   CAN_F10R1_FB15_Msk
     
    #define CAN_F10R1_FB16_Pos   (16U)
     
    #define CAN_F10R1_FB16_Msk   (0x1UL << CAN_F10R1_FB16_Pos)
     
    #define CAN_F10R1_FB16   CAN_F10R1_FB16_Msk
     
    #define CAN_F10R1_FB17_Pos   (17U)
     
    #define CAN_F10R1_FB17_Msk   (0x1UL << CAN_F10R1_FB17_Pos)
     
    #define CAN_F10R1_FB17   CAN_F10R1_FB17_Msk
     
    #define CAN_F10R1_FB18_Pos   (18U)
     
    #define CAN_F10R1_FB18_Msk   (0x1UL << CAN_F10R1_FB18_Pos)
     
    #define CAN_F10R1_FB18   CAN_F10R1_FB18_Msk
     
    #define CAN_F10R1_FB19_Pos   (19U)
     
    #define CAN_F10R1_FB19_Msk   (0x1UL << CAN_F10R1_FB19_Pos)
     
    #define CAN_F10R1_FB19   CAN_F10R1_FB19_Msk
     
    #define CAN_F10R1_FB20_Pos   (20U)
     
    #define CAN_F10R1_FB20_Msk   (0x1UL << CAN_F10R1_FB20_Pos)
     
    #define CAN_F10R1_FB20   CAN_F10R1_FB20_Msk
     
    #define CAN_F10R1_FB21_Pos   (21U)
     
    #define CAN_F10R1_FB21_Msk   (0x1UL << CAN_F10R1_FB21_Pos)
     
    #define CAN_F10R1_FB21   CAN_F10R1_FB21_Msk
     
    #define CAN_F10R1_FB22_Pos   (22U)
     
    #define CAN_F10R1_FB22_Msk   (0x1UL << CAN_F10R1_FB22_Pos)
     
    #define CAN_F10R1_FB22   CAN_F10R1_FB22_Msk
     
    #define CAN_F10R1_FB23_Pos   (23U)
     
    #define CAN_F10R1_FB23_Msk   (0x1UL << CAN_F10R1_FB23_Pos)
     
    #define CAN_F10R1_FB23   CAN_F10R1_FB23_Msk
     
    #define CAN_F10R1_FB24_Pos   (24U)
     
    #define CAN_F10R1_FB24_Msk   (0x1UL << CAN_F10R1_FB24_Pos)
     
    #define CAN_F10R1_FB24   CAN_F10R1_FB24_Msk
     
    #define CAN_F10R1_FB25_Pos   (25U)
     
    #define CAN_F10R1_FB25_Msk   (0x1UL << CAN_F10R1_FB25_Pos)
     
    #define CAN_F10R1_FB25   CAN_F10R1_FB25_Msk
     
    #define CAN_F10R1_FB26_Pos   (26U)
     
    #define CAN_F10R1_FB26_Msk   (0x1UL << CAN_F10R1_FB26_Pos)
     
    #define CAN_F10R1_FB26   CAN_F10R1_FB26_Msk
     
    #define CAN_F10R1_FB27_Pos   (27U)
     
    #define CAN_F10R1_FB27_Msk   (0x1UL << CAN_F10R1_FB27_Pos)
     
    #define CAN_F10R1_FB27   CAN_F10R1_FB27_Msk
     
    #define CAN_F10R1_FB28_Pos   (28U)
     
    #define CAN_F10R1_FB28_Msk   (0x1UL << CAN_F10R1_FB28_Pos)
     
    #define CAN_F10R1_FB28   CAN_F10R1_FB28_Msk
     
    #define CAN_F10R1_FB29_Pos   (29U)
     
    #define CAN_F10R1_FB29_Msk   (0x1UL << CAN_F10R1_FB29_Pos)
     
    #define CAN_F10R1_FB29   CAN_F10R1_FB29_Msk
     
    #define CAN_F10R1_FB30_Pos   (30U)
     
    #define CAN_F10R1_FB30_Msk   (0x1UL << CAN_F10R1_FB30_Pos)
     
    #define CAN_F10R1_FB30   CAN_F10R1_FB30_Msk
     
    #define CAN_F10R1_FB31_Pos   (31U)
     
    #define CAN_F10R1_FB31_Msk   (0x1UL << CAN_F10R1_FB31_Pos)
     
    #define CAN_F10R1_FB31   CAN_F10R1_FB31_Msk
     
    #define CAN_F11R1_FB0_Pos   (0U)
     
    #define CAN_F11R1_FB0_Msk   (0x1UL << CAN_F11R1_FB0_Pos)
     
    #define CAN_F11R1_FB0   CAN_F11R1_FB0_Msk
     
    #define CAN_F11R1_FB1_Pos   (1U)
     
    #define CAN_F11R1_FB1_Msk   (0x1UL << CAN_F11R1_FB1_Pos)
     
    #define CAN_F11R1_FB1   CAN_F11R1_FB1_Msk
     
    #define CAN_F11R1_FB2_Pos   (2U)
     
    #define CAN_F11R1_FB2_Msk   (0x1UL << CAN_F11R1_FB2_Pos)
     
    #define CAN_F11R1_FB2   CAN_F11R1_FB2_Msk
     
    #define CAN_F11R1_FB3_Pos   (3U)
     
    #define CAN_F11R1_FB3_Msk   (0x1UL << CAN_F11R1_FB3_Pos)
     
    #define CAN_F11R1_FB3   CAN_F11R1_FB3_Msk
     
    #define CAN_F11R1_FB4_Pos   (4U)
     
    #define CAN_F11R1_FB4_Msk   (0x1UL << CAN_F11R1_FB4_Pos)
     
    #define CAN_F11R1_FB4   CAN_F11R1_FB4_Msk
     
    #define CAN_F11R1_FB5_Pos   (5U)
     
    #define CAN_F11R1_FB5_Msk   (0x1UL << CAN_F11R1_FB5_Pos)
     
    #define CAN_F11R1_FB5   CAN_F11R1_FB5_Msk
     
    #define CAN_F11R1_FB6_Pos   (6U)
     
    #define CAN_F11R1_FB6_Msk   (0x1UL << CAN_F11R1_FB6_Pos)
     
    #define CAN_F11R1_FB6   CAN_F11R1_FB6_Msk
     
    #define CAN_F11R1_FB7_Pos   (7U)
     
    #define CAN_F11R1_FB7_Msk   (0x1UL << CAN_F11R1_FB7_Pos)
     
    #define CAN_F11R1_FB7   CAN_F11R1_FB7_Msk
     
    #define CAN_F11R1_FB8_Pos   (8U)
     
    #define CAN_F11R1_FB8_Msk   (0x1UL << CAN_F11R1_FB8_Pos)
     
    #define CAN_F11R1_FB8   CAN_F11R1_FB8_Msk
     
    #define CAN_F11R1_FB9_Pos   (9U)
     
    #define CAN_F11R1_FB9_Msk   (0x1UL << CAN_F11R1_FB9_Pos)
     
    #define CAN_F11R1_FB9   CAN_F11R1_FB9_Msk
     
    #define CAN_F11R1_FB10_Pos   (10U)
     
    #define CAN_F11R1_FB10_Msk   (0x1UL << CAN_F11R1_FB10_Pos)
     
    #define CAN_F11R1_FB10   CAN_F11R1_FB10_Msk
     
    #define CAN_F11R1_FB11_Pos   (11U)
     
    #define CAN_F11R1_FB11_Msk   (0x1UL << CAN_F11R1_FB11_Pos)
     
    #define CAN_F11R1_FB11   CAN_F11R1_FB11_Msk
     
    #define CAN_F11R1_FB12_Pos   (12U)
     
    #define CAN_F11R1_FB12_Msk   (0x1UL << CAN_F11R1_FB12_Pos)
     
    #define CAN_F11R1_FB12   CAN_F11R1_FB12_Msk
     
    #define CAN_F11R1_FB13_Pos   (13U)
     
    #define CAN_F11R1_FB13_Msk   (0x1UL << CAN_F11R1_FB13_Pos)
     
    #define CAN_F11R1_FB13   CAN_F11R1_FB13_Msk
     
    #define CAN_F11R1_FB14_Pos   (14U)
     
    #define CAN_F11R1_FB14_Msk   (0x1UL << CAN_F11R1_FB14_Pos)
     
    #define CAN_F11R1_FB14   CAN_F11R1_FB14_Msk
     
    #define CAN_F11R1_FB15_Pos   (15U)
     
    #define CAN_F11R1_FB15_Msk   (0x1UL << CAN_F11R1_FB15_Pos)
     
    #define CAN_F11R1_FB15   CAN_F11R1_FB15_Msk
     
    #define CAN_F11R1_FB16_Pos   (16U)
     
    #define CAN_F11R1_FB16_Msk   (0x1UL << CAN_F11R1_FB16_Pos)
     
    #define CAN_F11R1_FB16   CAN_F11R1_FB16_Msk
     
    #define CAN_F11R1_FB17_Pos   (17U)
     
    #define CAN_F11R1_FB17_Msk   (0x1UL << CAN_F11R1_FB17_Pos)
     
    #define CAN_F11R1_FB17   CAN_F11R1_FB17_Msk
     
    #define CAN_F11R1_FB18_Pos   (18U)
     
    #define CAN_F11R1_FB18_Msk   (0x1UL << CAN_F11R1_FB18_Pos)
     
    #define CAN_F11R1_FB18   CAN_F11R1_FB18_Msk
     
    #define CAN_F11R1_FB19_Pos   (19U)
     
    #define CAN_F11R1_FB19_Msk   (0x1UL << CAN_F11R1_FB19_Pos)
     
    #define CAN_F11R1_FB19   CAN_F11R1_FB19_Msk
     
    #define CAN_F11R1_FB20_Pos   (20U)
     
    #define CAN_F11R1_FB20_Msk   (0x1UL << CAN_F11R1_FB20_Pos)
     
    #define CAN_F11R1_FB20   CAN_F11R1_FB20_Msk
     
    #define CAN_F11R1_FB21_Pos   (21U)
     
    #define CAN_F11R1_FB21_Msk   (0x1UL << CAN_F11R1_FB21_Pos)
     
    #define CAN_F11R1_FB21   CAN_F11R1_FB21_Msk
     
    #define CAN_F11R1_FB22_Pos   (22U)
     
    #define CAN_F11R1_FB22_Msk   (0x1UL << CAN_F11R1_FB22_Pos)
     
    #define CAN_F11R1_FB22   CAN_F11R1_FB22_Msk
     
    #define CAN_F11R1_FB23_Pos   (23U)
     
    #define CAN_F11R1_FB23_Msk   (0x1UL << CAN_F11R1_FB23_Pos)
     
    #define CAN_F11R1_FB23   CAN_F11R1_FB23_Msk
     
    #define CAN_F11R1_FB24_Pos   (24U)
     
    #define CAN_F11R1_FB24_Msk   (0x1UL << CAN_F11R1_FB24_Pos)
     
    #define CAN_F11R1_FB24   CAN_F11R1_FB24_Msk
     
    #define CAN_F11R1_FB25_Pos   (25U)
     
    #define CAN_F11R1_FB25_Msk   (0x1UL << CAN_F11R1_FB25_Pos)
     
    #define CAN_F11R1_FB25   CAN_F11R1_FB25_Msk
     
    #define CAN_F11R1_FB26_Pos   (26U)
     
    #define CAN_F11R1_FB26_Msk   (0x1UL << CAN_F11R1_FB26_Pos)
     
    #define CAN_F11R1_FB26   CAN_F11R1_FB26_Msk
     
    #define CAN_F11R1_FB27_Pos   (27U)
     
    #define CAN_F11R1_FB27_Msk   (0x1UL << CAN_F11R1_FB27_Pos)
     
    #define CAN_F11R1_FB27   CAN_F11R1_FB27_Msk
     
    #define CAN_F11R1_FB28_Pos   (28U)
     
    #define CAN_F11R1_FB28_Msk   (0x1UL << CAN_F11R1_FB28_Pos)
     
    #define CAN_F11R1_FB28   CAN_F11R1_FB28_Msk
     
    #define CAN_F11R1_FB29_Pos   (29U)
     
    #define CAN_F11R1_FB29_Msk   (0x1UL << CAN_F11R1_FB29_Pos)
     
    #define CAN_F11R1_FB29   CAN_F11R1_FB29_Msk
     
    #define CAN_F11R1_FB30_Pos   (30U)
     
    #define CAN_F11R1_FB30_Msk   (0x1UL << CAN_F11R1_FB30_Pos)
     
    #define CAN_F11R1_FB30   CAN_F11R1_FB30_Msk
     
    #define CAN_F11R1_FB31_Pos   (31U)
     
    #define CAN_F11R1_FB31_Msk   (0x1UL << CAN_F11R1_FB31_Pos)
     
    #define CAN_F11R1_FB31   CAN_F11R1_FB31_Msk
     
    #define CAN_F12R1_FB0_Pos   (0U)
     
    #define CAN_F12R1_FB0_Msk   (0x1UL << CAN_F12R1_FB0_Pos)
     
    #define CAN_F12R1_FB0   CAN_F12R1_FB0_Msk
     
    #define CAN_F12R1_FB1_Pos   (1U)
     
    #define CAN_F12R1_FB1_Msk   (0x1UL << CAN_F12R1_FB1_Pos)
     
    #define CAN_F12R1_FB1   CAN_F12R1_FB1_Msk
     
    #define CAN_F12R1_FB2_Pos   (2U)
     
    #define CAN_F12R1_FB2_Msk   (0x1UL << CAN_F12R1_FB2_Pos)
     
    #define CAN_F12R1_FB2   CAN_F12R1_FB2_Msk
     
    #define CAN_F12R1_FB3_Pos   (3U)
     
    #define CAN_F12R1_FB3_Msk   (0x1UL << CAN_F12R1_FB3_Pos)
     
    #define CAN_F12R1_FB3   CAN_F12R1_FB3_Msk
     
    #define CAN_F12R1_FB4_Pos   (4U)
     
    #define CAN_F12R1_FB4_Msk   (0x1UL << CAN_F12R1_FB4_Pos)
     
    #define CAN_F12R1_FB4   CAN_F12R1_FB4_Msk
     
    #define CAN_F12R1_FB5_Pos   (5U)
     
    #define CAN_F12R1_FB5_Msk   (0x1UL << CAN_F12R1_FB5_Pos)
     
    #define CAN_F12R1_FB5   CAN_F12R1_FB5_Msk
     
    #define CAN_F12R1_FB6_Pos   (6U)
     
    #define CAN_F12R1_FB6_Msk   (0x1UL << CAN_F12R1_FB6_Pos)
     
    #define CAN_F12R1_FB6   CAN_F12R1_FB6_Msk
     
    #define CAN_F12R1_FB7_Pos   (7U)
     
    #define CAN_F12R1_FB7_Msk   (0x1UL << CAN_F12R1_FB7_Pos)
     
    #define CAN_F12R1_FB7   CAN_F12R1_FB7_Msk
     
    #define CAN_F12R1_FB8_Pos   (8U)
     
    #define CAN_F12R1_FB8_Msk   (0x1UL << CAN_F12R1_FB8_Pos)
     
    #define CAN_F12R1_FB8   CAN_F12R1_FB8_Msk
     
    #define CAN_F12R1_FB9_Pos   (9U)
     
    #define CAN_F12R1_FB9_Msk   (0x1UL << CAN_F12R1_FB9_Pos)
     
    #define CAN_F12R1_FB9   CAN_F12R1_FB9_Msk
     
    #define CAN_F12R1_FB10_Pos   (10U)
     
    #define CAN_F12R1_FB10_Msk   (0x1UL << CAN_F12R1_FB10_Pos)
     
    #define CAN_F12R1_FB10   CAN_F12R1_FB10_Msk
     
    #define CAN_F12R1_FB11_Pos   (11U)
     
    #define CAN_F12R1_FB11_Msk   (0x1UL << CAN_F12R1_FB11_Pos)
     
    #define CAN_F12R1_FB11   CAN_F12R1_FB11_Msk
     
    #define CAN_F12R1_FB12_Pos   (12U)
     
    #define CAN_F12R1_FB12_Msk   (0x1UL << CAN_F12R1_FB12_Pos)
     
    #define CAN_F12R1_FB12   CAN_F12R1_FB12_Msk
     
    #define CAN_F12R1_FB13_Pos   (13U)
     
    #define CAN_F12R1_FB13_Msk   (0x1UL << CAN_F12R1_FB13_Pos)
     
    #define CAN_F12R1_FB13   CAN_F12R1_FB13_Msk
     
    #define CAN_F12R1_FB14_Pos   (14U)
     
    #define CAN_F12R1_FB14_Msk   (0x1UL << CAN_F12R1_FB14_Pos)
     
    #define CAN_F12R1_FB14   CAN_F12R1_FB14_Msk
     
    #define CAN_F12R1_FB15_Pos   (15U)
     
    #define CAN_F12R1_FB15_Msk   (0x1UL << CAN_F12R1_FB15_Pos)
     
    #define CAN_F12R1_FB15   CAN_F12R1_FB15_Msk
     
    #define CAN_F12R1_FB16_Pos   (16U)
     
    #define CAN_F12R1_FB16_Msk   (0x1UL << CAN_F12R1_FB16_Pos)
     
    #define CAN_F12R1_FB16   CAN_F12R1_FB16_Msk
     
    #define CAN_F12R1_FB17_Pos   (17U)
     
    #define CAN_F12R1_FB17_Msk   (0x1UL << CAN_F12R1_FB17_Pos)
     
    #define CAN_F12R1_FB17   CAN_F12R1_FB17_Msk
     
    #define CAN_F12R1_FB18_Pos   (18U)
     
    #define CAN_F12R1_FB18_Msk   (0x1UL << CAN_F12R1_FB18_Pos)
     
    #define CAN_F12R1_FB18   CAN_F12R1_FB18_Msk
     
    #define CAN_F12R1_FB19_Pos   (19U)
     
    #define CAN_F12R1_FB19_Msk   (0x1UL << CAN_F12R1_FB19_Pos)
     
    #define CAN_F12R1_FB19   CAN_F12R1_FB19_Msk
     
    #define CAN_F12R1_FB20_Pos   (20U)
     
    #define CAN_F12R1_FB20_Msk   (0x1UL << CAN_F12R1_FB20_Pos)
     
    #define CAN_F12R1_FB20   CAN_F12R1_FB20_Msk
     
    #define CAN_F12R1_FB21_Pos   (21U)
     
    #define CAN_F12R1_FB21_Msk   (0x1UL << CAN_F12R1_FB21_Pos)
     
    #define CAN_F12R1_FB21   CAN_F12R1_FB21_Msk
     
    #define CAN_F12R1_FB22_Pos   (22U)
     
    #define CAN_F12R1_FB22_Msk   (0x1UL << CAN_F12R1_FB22_Pos)
     
    #define CAN_F12R1_FB22   CAN_F12R1_FB22_Msk
     
    #define CAN_F12R1_FB23_Pos   (23U)
     
    #define CAN_F12R1_FB23_Msk   (0x1UL << CAN_F12R1_FB23_Pos)
     
    #define CAN_F12R1_FB23   CAN_F12R1_FB23_Msk
     
    #define CAN_F12R1_FB24_Pos   (24U)
     
    #define CAN_F12R1_FB24_Msk   (0x1UL << CAN_F12R1_FB24_Pos)
     
    #define CAN_F12R1_FB24   CAN_F12R1_FB24_Msk
     
    #define CAN_F12R1_FB25_Pos   (25U)
     
    #define CAN_F12R1_FB25_Msk   (0x1UL << CAN_F12R1_FB25_Pos)
     
    #define CAN_F12R1_FB25   CAN_F12R1_FB25_Msk
     
    #define CAN_F12R1_FB26_Pos   (26U)
     
    #define CAN_F12R1_FB26_Msk   (0x1UL << CAN_F12R1_FB26_Pos)
     
    #define CAN_F12R1_FB26   CAN_F12R1_FB26_Msk
     
    #define CAN_F12R1_FB27_Pos   (27U)
     
    #define CAN_F12R1_FB27_Msk   (0x1UL << CAN_F12R1_FB27_Pos)
     
    #define CAN_F12R1_FB27   CAN_F12R1_FB27_Msk
     
    #define CAN_F12R1_FB28_Pos   (28U)
     
    #define CAN_F12R1_FB28_Msk   (0x1UL << CAN_F12R1_FB28_Pos)
     
    #define CAN_F12R1_FB28   CAN_F12R1_FB28_Msk
     
    #define CAN_F12R1_FB29_Pos   (29U)
     
    #define CAN_F12R1_FB29_Msk   (0x1UL << CAN_F12R1_FB29_Pos)
     
    #define CAN_F12R1_FB29   CAN_F12R1_FB29_Msk
     
    #define CAN_F12R1_FB30_Pos   (30U)
     
    #define CAN_F12R1_FB30_Msk   (0x1UL << CAN_F12R1_FB30_Pos)
     
    #define CAN_F12R1_FB30   CAN_F12R1_FB30_Msk
     
    #define CAN_F12R1_FB31_Pos   (31U)
     
    #define CAN_F12R1_FB31_Msk   (0x1UL << CAN_F12R1_FB31_Pos)
     
    #define CAN_F12R1_FB31   CAN_F12R1_FB31_Msk
     
    #define CAN_F13R1_FB0_Pos   (0U)
     
    #define CAN_F13R1_FB0_Msk   (0x1UL << CAN_F13R1_FB0_Pos)
     
    #define CAN_F13R1_FB0   CAN_F13R1_FB0_Msk
     
    #define CAN_F13R1_FB1_Pos   (1U)
     
    #define CAN_F13R1_FB1_Msk   (0x1UL << CAN_F13R1_FB1_Pos)
     
    #define CAN_F13R1_FB1   CAN_F13R1_FB1_Msk
     
    #define CAN_F13R1_FB2_Pos   (2U)
     
    #define CAN_F13R1_FB2_Msk   (0x1UL << CAN_F13R1_FB2_Pos)
     
    #define CAN_F13R1_FB2   CAN_F13R1_FB2_Msk
     
    #define CAN_F13R1_FB3_Pos   (3U)
     
    #define CAN_F13R1_FB3_Msk   (0x1UL << CAN_F13R1_FB3_Pos)
     
    #define CAN_F13R1_FB3   CAN_F13R1_FB3_Msk
     
    #define CAN_F13R1_FB4_Pos   (4U)
     
    #define CAN_F13R1_FB4_Msk   (0x1UL << CAN_F13R1_FB4_Pos)
     
    #define CAN_F13R1_FB4   CAN_F13R1_FB4_Msk
     
    #define CAN_F13R1_FB5_Pos   (5U)
     
    #define CAN_F13R1_FB5_Msk   (0x1UL << CAN_F13R1_FB5_Pos)
     
    #define CAN_F13R1_FB5   CAN_F13R1_FB5_Msk
     
    #define CAN_F13R1_FB6_Pos   (6U)
     
    #define CAN_F13R1_FB6_Msk   (0x1UL << CAN_F13R1_FB6_Pos)
     
    #define CAN_F13R1_FB6   CAN_F13R1_FB6_Msk
     
    #define CAN_F13R1_FB7_Pos   (7U)
     
    #define CAN_F13R1_FB7_Msk   (0x1UL << CAN_F13R1_FB7_Pos)
     
    #define CAN_F13R1_FB7   CAN_F13R1_FB7_Msk
     
    #define CAN_F13R1_FB8_Pos   (8U)
     
    #define CAN_F13R1_FB8_Msk   (0x1UL << CAN_F13R1_FB8_Pos)
     
    #define CAN_F13R1_FB8   CAN_F13R1_FB8_Msk
     
    #define CAN_F13R1_FB9_Pos   (9U)
     
    #define CAN_F13R1_FB9_Msk   (0x1UL << CAN_F13R1_FB9_Pos)
     
    #define CAN_F13R1_FB9   CAN_F13R1_FB9_Msk
     
    #define CAN_F13R1_FB10_Pos   (10U)
     
    #define CAN_F13R1_FB10_Msk   (0x1UL << CAN_F13R1_FB10_Pos)
     
    #define CAN_F13R1_FB10   CAN_F13R1_FB10_Msk
     
    #define CAN_F13R1_FB11_Pos   (11U)
     
    #define CAN_F13R1_FB11_Msk   (0x1UL << CAN_F13R1_FB11_Pos)
     
    #define CAN_F13R1_FB11   CAN_F13R1_FB11_Msk
     
    #define CAN_F13R1_FB12_Pos   (12U)
     
    #define CAN_F13R1_FB12_Msk   (0x1UL << CAN_F13R1_FB12_Pos)
     
    #define CAN_F13R1_FB12   CAN_F13R1_FB12_Msk
     
    #define CAN_F13R1_FB13_Pos   (13U)
     
    #define CAN_F13R1_FB13_Msk   (0x1UL << CAN_F13R1_FB13_Pos)
     
    #define CAN_F13R1_FB13   CAN_F13R1_FB13_Msk
     
    #define CAN_F13R1_FB14_Pos   (14U)
     
    #define CAN_F13R1_FB14_Msk   (0x1UL << CAN_F13R1_FB14_Pos)
     
    #define CAN_F13R1_FB14   CAN_F13R1_FB14_Msk
     
    #define CAN_F13R1_FB15_Pos   (15U)
     
    #define CAN_F13R1_FB15_Msk   (0x1UL << CAN_F13R1_FB15_Pos)
     
    #define CAN_F13R1_FB15   CAN_F13R1_FB15_Msk
     
    #define CAN_F13R1_FB16_Pos   (16U)
     
    #define CAN_F13R1_FB16_Msk   (0x1UL << CAN_F13R1_FB16_Pos)
     
    #define CAN_F13R1_FB16   CAN_F13R1_FB16_Msk
     
    #define CAN_F13R1_FB17_Pos   (17U)
     
    #define CAN_F13R1_FB17_Msk   (0x1UL << CAN_F13R1_FB17_Pos)
     
    #define CAN_F13R1_FB17   CAN_F13R1_FB17_Msk
     
    #define CAN_F13R1_FB18_Pos   (18U)
     
    #define CAN_F13R1_FB18_Msk   (0x1UL << CAN_F13R1_FB18_Pos)
     
    #define CAN_F13R1_FB18   CAN_F13R1_FB18_Msk
     
    #define CAN_F13R1_FB19_Pos   (19U)
     
    #define CAN_F13R1_FB19_Msk   (0x1UL << CAN_F13R1_FB19_Pos)
     
    #define CAN_F13R1_FB19   CAN_F13R1_FB19_Msk
     
    #define CAN_F13R1_FB20_Pos   (20U)
     
    #define CAN_F13R1_FB20_Msk   (0x1UL << CAN_F13R1_FB20_Pos)
     
    #define CAN_F13R1_FB20   CAN_F13R1_FB20_Msk
     
    #define CAN_F13R1_FB21_Pos   (21U)
     
    #define CAN_F13R1_FB21_Msk   (0x1UL << CAN_F13R1_FB21_Pos)
     
    #define CAN_F13R1_FB21   CAN_F13R1_FB21_Msk
     
    #define CAN_F13R1_FB22_Pos   (22U)
     
    #define CAN_F13R1_FB22_Msk   (0x1UL << CAN_F13R1_FB22_Pos)
     
    #define CAN_F13R1_FB22   CAN_F13R1_FB22_Msk
     
    #define CAN_F13R1_FB23_Pos   (23U)
     
    #define CAN_F13R1_FB23_Msk   (0x1UL << CAN_F13R1_FB23_Pos)
     
    #define CAN_F13R1_FB23   CAN_F13R1_FB23_Msk
     
    #define CAN_F13R1_FB24_Pos   (24U)
     
    #define CAN_F13R1_FB24_Msk   (0x1UL << CAN_F13R1_FB24_Pos)
     
    #define CAN_F13R1_FB24   CAN_F13R1_FB24_Msk
     
    #define CAN_F13R1_FB25_Pos   (25U)
     
    #define CAN_F13R1_FB25_Msk   (0x1UL << CAN_F13R1_FB25_Pos)
     
    #define CAN_F13R1_FB25   CAN_F13R1_FB25_Msk
     
    #define CAN_F13R1_FB26_Pos   (26U)
     
    #define CAN_F13R1_FB26_Msk   (0x1UL << CAN_F13R1_FB26_Pos)
     
    #define CAN_F13R1_FB26   CAN_F13R1_FB26_Msk
     
    #define CAN_F13R1_FB27_Pos   (27U)
     
    #define CAN_F13R1_FB27_Msk   (0x1UL << CAN_F13R1_FB27_Pos)
     
    #define CAN_F13R1_FB27   CAN_F13R1_FB27_Msk
     
    #define CAN_F13R1_FB28_Pos   (28U)
     
    #define CAN_F13R1_FB28_Msk   (0x1UL << CAN_F13R1_FB28_Pos)
     
    #define CAN_F13R1_FB28   CAN_F13R1_FB28_Msk
     
    #define CAN_F13R1_FB29_Pos   (29U)
     
    #define CAN_F13R1_FB29_Msk   (0x1UL << CAN_F13R1_FB29_Pos)
     
    #define CAN_F13R1_FB29   CAN_F13R1_FB29_Msk
     
    #define CAN_F13R1_FB30_Pos   (30U)
     
    #define CAN_F13R1_FB30_Msk   (0x1UL << CAN_F13R1_FB30_Pos)
     
    #define CAN_F13R1_FB30   CAN_F13R1_FB30_Msk
     
    #define CAN_F13R1_FB31_Pos   (31U)
     
    #define CAN_F13R1_FB31_Msk   (0x1UL << CAN_F13R1_FB31_Pos)
     
    #define CAN_F13R1_FB31   CAN_F13R1_FB31_Msk
     
    #define CAN_F0R2_FB0_Pos   (0U)
     
    #define CAN_F0R2_FB0_Msk   (0x1UL << CAN_F0R2_FB0_Pos)
     
    #define CAN_F0R2_FB0   CAN_F0R2_FB0_Msk
     
    #define CAN_F0R2_FB1_Pos   (1U)
     
    #define CAN_F0R2_FB1_Msk   (0x1UL << CAN_F0R2_FB1_Pos)
     
    #define CAN_F0R2_FB1   CAN_F0R2_FB1_Msk
     
    #define CAN_F0R2_FB2_Pos   (2U)
     
    #define CAN_F0R2_FB2_Msk   (0x1UL << CAN_F0R2_FB2_Pos)
     
    #define CAN_F0R2_FB2   CAN_F0R2_FB2_Msk
     
    #define CAN_F0R2_FB3_Pos   (3U)
     
    #define CAN_F0R2_FB3_Msk   (0x1UL << CAN_F0R2_FB3_Pos)
     
    #define CAN_F0R2_FB3   CAN_F0R2_FB3_Msk
     
    #define CAN_F0R2_FB4_Pos   (4U)
     
    #define CAN_F0R2_FB4_Msk   (0x1UL << CAN_F0R2_FB4_Pos)
     
    #define CAN_F0R2_FB4   CAN_F0R2_FB4_Msk
     
    #define CAN_F0R2_FB5_Pos   (5U)
     
    #define CAN_F0R2_FB5_Msk   (0x1UL << CAN_F0R2_FB5_Pos)
     
    #define CAN_F0R2_FB5   CAN_F0R2_FB5_Msk
     
    #define CAN_F0R2_FB6_Pos   (6U)
     
    #define CAN_F0R2_FB6_Msk   (0x1UL << CAN_F0R2_FB6_Pos)
     
    #define CAN_F0R2_FB6   CAN_F0R2_FB6_Msk
     
    #define CAN_F0R2_FB7_Pos   (7U)
     
    #define CAN_F0R2_FB7_Msk   (0x1UL << CAN_F0R2_FB7_Pos)
     
    #define CAN_F0R2_FB7   CAN_F0R2_FB7_Msk
     
    #define CAN_F0R2_FB8_Pos   (8U)
     
    #define CAN_F0R2_FB8_Msk   (0x1UL << CAN_F0R2_FB8_Pos)
     
    #define CAN_F0R2_FB8   CAN_F0R2_FB8_Msk
     
    #define CAN_F0R2_FB9_Pos   (9U)
     
    #define CAN_F0R2_FB9_Msk   (0x1UL << CAN_F0R2_FB9_Pos)
     
    #define CAN_F0R2_FB9   CAN_F0R2_FB9_Msk
     
    #define CAN_F0R2_FB10_Pos   (10U)
     
    #define CAN_F0R2_FB10_Msk   (0x1UL << CAN_F0R2_FB10_Pos)
     
    #define CAN_F0R2_FB10   CAN_F0R2_FB10_Msk
     
    #define CAN_F0R2_FB11_Pos   (11U)
     
    #define CAN_F0R2_FB11_Msk   (0x1UL << CAN_F0R2_FB11_Pos)
     
    #define CAN_F0R2_FB11   CAN_F0R2_FB11_Msk
     
    #define CAN_F0R2_FB12_Pos   (12U)
     
    #define CAN_F0R2_FB12_Msk   (0x1UL << CAN_F0R2_FB12_Pos)
     
    #define CAN_F0R2_FB12   CAN_F0R2_FB12_Msk
     
    #define CAN_F0R2_FB13_Pos   (13U)
     
    #define CAN_F0R2_FB13_Msk   (0x1UL << CAN_F0R2_FB13_Pos)
     
    #define CAN_F0R2_FB13   CAN_F0R2_FB13_Msk
     
    #define CAN_F0R2_FB14_Pos   (14U)
     
    #define CAN_F0R2_FB14_Msk   (0x1UL << CAN_F0R2_FB14_Pos)
     
    #define CAN_F0R2_FB14   CAN_F0R2_FB14_Msk
     
    #define CAN_F0R2_FB15_Pos   (15U)
     
    #define CAN_F0R2_FB15_Msk   (0x1UL << CAN_F0R2_FB15_Pos)
     
    #define CAN_F0R2_FB15   CAN_F0R2_FB15_Msk
     
    #define CAN_F0R2_FB16_Pos   (16U)
     
    #define CAN_F0R2_FB16_Msk   (0x1UL << CAN_F0R2_FB16_Pos)
     
    #define CAN_F0R2_FB16   CAN_F0R2_FB16_Msk
     
    #define CAN_F0R2_FB17_Pos   (17U)
     
    #define CAN_F0R2_FB17_Msk   (0x1UL << CAN_F0R2_FB17_Pos)
     
    #define CAN_F0R2_FB17   CAN_F0R2_FB17_Msk
     
    #define CAN_F0R2_FB18_Pos   (18U)
     
    #define CAN_F0R2_FB18_Msk   (0x1UL << CAN_F0R2_FB18_Pos)
     
    #define CAN_F0R2_FB18   CAN_F0R2_FB18_Msk
     
    #define CAN_F0R2_FB19_Pos   (19U)
     
    #define CAN_F0R2_FB19_Msk   (0x1UL << CAN_F0R2_FB19_Pos)
     
    #define CAN_F0R2_FB19   CAN_F0R2_FB19_Msk
     
    #define CAN_F0R2_FB20_Pos   (20U)
     
    #define CAN_F0R2_FB20_Msk   (0x1UL << CAN_F0R2_FB20_Pos)
     
    #define CAN_F0R2_FB20   CAN_F0R2_FB20_Msk
     
    #define CAN_F0R2_FB21_Pos   (21U)
     
    #define CAN_F0R2_FB21_Msk   (0x1UL << CAN_F0R2_FB21_Pos)
     
    #define CAN_F0R2_FB21   CAN_F0R2_FB21_Msk
     
    #define CAN_F0R2_FB22_Pos   (22U)
     
    #define CAN_F0R2_FB22_Msk   (0x1UL << CAN_F0R2_FB22_Pos)
     
    #define CAN_F0R2_FB22   CAN_F0R2_FB22_Msk
     
    #define CAN_F0R2_FB23_Pos   (23U)
     
    #define CAN_F0R2_FB23_Msk   (0x1UL << CAN_F0R2_FB23_Pos)
     
    #define CAN_F0R2_FB23   CAN_F0R2_FB23_Msk
     
    #define CAN_F0R2_FB24_Pos   (24U)
     
    #define CAN_F0R2_FB24_Msk   (0x1UL << CAN_F0R2_FB24_Pos)
     
    #define CAN_F0R2_FB24   CAN_F0R2_FB24_Msk
     
    #define CAN_F0R2_FB25_Pos   (25U)
     
    #define CAN_F0R2_FB25_Msk   (0x1UL << CAN_F0R2_FB25_Pos)
     
    #define CAN_F0R2_FB25   CAN_F0R2_FB25_Msk
     
    #define CAN_F0R2_FB26_Pos   (26U)
     
    #define CAN_F0R2_FB26_Msk   (0x1UL << CAN_F0R2_FB26_Pos)
     
    #define CAN_F0R2_FB26   CAN_F0R2_FB26_Msk
     
    #define CAN_F0R2_FB27_Pos   (27U)
     
    #define CAN_F0R2_FB27_Msk   (0x1UL << CAN_F0R2_FB27_Pos)
     
    #define CAN_F0R2_FB27   CAN_F0R2_FB27_Msk
     
    #define CAN_F0R2_FB28_Pos   (28U)
     
    #define CAN_F0R2_FB28_Msk   (0x1UL << CAN_F0R2_FB28_Pos)
     
    #define CAN_F0R2_FB28   CAN_F0R2_FB28_Msk
     
    #define CAN_F0R2_FB29_Pos   (29U)
     
    #define CAN_F0R2_FB29_Msk   (0x1UL << CAN_F0R2_FB29_Pos)
     
    #define CAN_F0R2_FB29   CAN_F0R2_FB29_Msk
     
    #define CAN_F0R2_FB30_Pos   (30U)
     
    #define CAN_F0R2_FB30_Msk   (0x1UL << CAN_F0R2_FB30_Pos)
     
    #define CAN_F0R2_FB30   CAN_F0R2_FB30_Msk
     
    #define CAN_F0R2_FB31_Pos   (31U)
     
    #define CAN_F0R2_FB31_Msk   (0x1UL << CAN_F0R2_FB31_Pos)
     
    #define CAN_F0R2_FB31   CAN_F0R2_FB31_Msk
     
    #define CAN_F1R2_FB0_Pos   (0U)
     
    #define CAN_F1R2_FB0_Msk   (0x1UL << CAN_F1R2_FB0_Pos)
     
    #define CAN_F1R2_FB0   CAN_F1R2_FB0_Msk
     
    #define CAN_F1R2_FB1_Pos   (1U)
     
    #define CAN_F1R2_FB1_Msk   (0x1UL << CAN_F1R2_FB1_Pos)
     
    #define CAN_F1R2_FB1   CAN_F1R2_FB1_Msk
     
    #define CAN_F1R2_FB2_Pos   (2U)
     
    #define CAN_F1R2_FB2_Msk   (0x1UL << CAN_F1R2_FB2_Pos)
     
    #define CAN_F1R2_FB2   CAN_F1R2_FB2_Msk
     
    #define CAN_F1R2_FB3_Pos   (3U)
     
    #define CAN_F1R2_FB3_Msk   (0x1UL << CAN_F1R2_FB3_Pos)
     
    #define CAN_F1R2_FB3   CAN_F1R2_FB3_Msk
     
    #define CAN_F1R2_FB4_Pos   (4U)
     
    #define CAN_F1R2_FB4_Msk   (0x1UL << CAN_F1R2_FB4_Pos)
     
    #define CAN_F1R2_FB4   CAN_F1R2_FB4_Msk
     
    #define CAN_F1R2_FB5_Pos   (5U)
     
    #define CAN_F1R2_FB5_Msk   (0x1UL << CAN_F1R2_FB5_Pos)
     
    #define CAN_F1R2_FB5   CAN_F1R2_FB5_Msk
     
    #define CAN_F1R2_FB6_Pos   (6U)
     
    #define CAN_F1R2_FB6_Msk   (0x1UL << CAN_F1R2_FB6_Pos)
     
    #define CAN_F1R2_FB6   CAN_F1R2_FB6_Msk
     
    #define CAN_F1R2_FB7_Pos   (7U)
     
    #define CAN_F1R2_FB7_Msk   (0x1UL << CAN_F1R2_FB7_Pos)
     
    #define CAN_F1R2_FB7   CAN_F1R2_FB7_Msk
     
    #define CAN_F1R2_FB8_Pos   (8U)
     
    #define CAN_F1R2_FB8_Msk   (0x1UL << CAN_F1R2_FB8_Pos)
     
    #define CAN_F1R2_FB8   CAN_F1R2_FB8_Msk
     
    #define CAN_F1R2_FB9_Pos   (9U)
     
    #define CAN_F1R2_FB9_Msk   (0x1UL << CAN_F1R2_FB9_Pos)
     
    #define CAN_F1R2_FB9   CAN_F1R2_FB9_Msk
     
    #define CAN_F1R2_FB10_Pos   (10U)
     
    #define CAN_F1R2_FB10_Msk   (0x1UL << CAN_F1R2_FB10_Pos)
     
    #define CAN_F1R2_FB10   CAN_F1R2_FB10_Msk
     
    #define CAN_F1R2_FB11_Pos   (11U)
     
    #define CAN_F1R2_FB11_Msk   (0x1UL << CAN_F1R2_FB11_Pos)
     
    #define CAN_F1R2_FB11   CAN_F1R2_FB11_Msk
     
    #define CAN_F1R2_FB12_Pos   (12U)
     
    #define CAN_F1R2_FB12_Msk   (0x1UL << CAN_F1R2_FB12_Pos)
     
    #define CAN_F1R2_FB12   CAN_F1R2_FB12_Msk
     
    #define CAN_F1R2_FB13_Pos   (13U)
     
    #define CAN_F1R2_FB13_Msk   (0x1UL << CAN_F1R2_FB13_Pos)
     
    #define CAN_F1R2_FB13   CAN_F1R2_FB13_Msk
     
    #define CAN_F1R2_FB14_Pos   (14U)
     
    #define CAN_F1R2_FB14_Msk   (0x1UL << CAN_F1R2_FB14_Pos)
     
    #define CAN_F1R2_FB14   CAN_F1R2_FB14_Msk
     
    #define CAN_F1R2_FB15_Pos   (15U)
     
    #define CAN_F1R2_FB15_Msk   (0x1UL << CAN_F1R2_FB15_Pos)
     
    #define CAN_F1R2_FB15   CAN_F1R2_FB15_Msk
     
    #define CAN_F1R2_FB16_Pos   (16U)
     
    #define CAN_F1R2_FB16_Msk   (0x1UL << CAN_F1R2_FB16_Pos)
     
    #define CAN_F1R2_FB16   CAN_F1R2_FB16_Msk
     
    #define CAN_F1R2_FB17_Pos   (17U)
     
    #define CAN_F1R2_FB17_Msk   (0x1UL << CAN_F1R2_FB17_Pos)
     
    #define CAN_F1R2_FB17   CAN_F1R2_FB17_Msk
     
    #define CAN_F1R2_FB18_Pos   (18U)
     
    #define CAN_F1R2_FB18_Msk   (0x1UL << CAN_F1R2_FB18_Pos)
     
    #define CAN_F1R2_FB18   CAN_F1R2_FB18_Msk
     
    #define CAN_F1R2_FB19_Pos   (19U)
     
    #define CAN_F1R2_FB19_Msk   (0x1UL << CAN_F1R2_FB19_Pos)
     
    #define CAN_F1R2_FB19   CAN_F1R2_FB19_Msk
     
    #define CAN_F1R2_FB20_Pos   (20U)
     
    #define CAN_F1R2_FB20_Msk   (0x1UL << CAN_F1R2_FB20_Pos)
     
    #define CAN_F1R2_FB20   CAN_F1R2_FB20_Msk
     
    #define CAN_F1R2_FB21_Pos   (21U)
     
    #define CAN_F1R2_FB21_Msk   (0x1UL << CAN_F1R2_FB21_Pos)
     
    #define CAN_F1R2_FB21   CAN_F1R2_FB21_Msk
     
    #define CAN_F1R2_FB22_Pos   (22U)
     
    #define CAN_F1R2_FB22_Msk   (0x1UL << CAN_F1R2_FB22_Pos)
     
    #define CAN_F1R2_FB22   CAN_F1R2_FB22_Msk
     
    #define CAN_F1R2_FB23_Pos   (23U)
     
    #define CAN_F1R2_FB23_Msk   (0x1UL << CAN_F1R2_FB23_Pos)
     
    #define CAN_F1R2_FB23   CAN_F1R2_FB23_Msk
     
    #define CAN_F1R2_FB24_Pos   (24U)
     
    #define CAN_F1R2_FB24_Msk   (0x1UL << CAN_F1R2_FB24_Pos)
     
    #define CAN_F1R2_FB24   CAN_F1R2_FB24_Msk
     
    #define CAN_F1R2_FB25_Pos   (25U)
     
    #define CAN_F1R2_FB25_Msk   (0x1UL << CAN_F1R2_FB25_Pos)
     
    #define CAN_F1R2_FB25   CAN_F1R2_FB25_Msk
     
    #define CAN_F1R2_FB26_Pos   (26U)
     
    #define CAN_F1R2_FB26_Msk   (0x1UL << CAN_F1R2_FB26_Pos)
     
    #define CAN_F1R2_FB26   CAN_F1R2_FB26_Msk
     
    #define CAN_F1R2_FB27_Pos   (27U)
     
    #define CAN_F1R2_FB27_Msk   (0x1UL << CAN_F1R2_FB27_Pos)
     
    #define CAN_F1R2_FB27   CAN_F1R2_FB27_Msk
     
    #define CAN_F1R2_FB28_Pos   (28U)
     
    #define CAN_F1R2_FB28_Msk   (0x1UL << CAN_F1R2_FB28_Pos)
     
    #define CAN_F1R2_FB28   CAN_F1R2_FB28_Msk
     
    #define CAN_F1R2_FB29_Pos   (29U)
     
    #define CAN_F1R2_FB29_Msk   (0x1UL << CAN_F1R2_FB29_Pos)
     
    #define CAN_F1R2_FB29   CAN_F1R2_FB29_Msk
     
    #define CAN_F1R2_FB30_Pos   (30U)
     
    #define CAN_F1R2_FB30_Msk   (0x1UL << CAN_F1R2_FB30_Pos)
     
    #define CAN_F1R2_FB30   CAN_F1R2_FB30_Msk
     
    #define CAN_F1R2_FB31_Pos   (31U)
     
    #define CAN_F1R2_FB31_Msk   (0x1UL << CAN_F1R2_FB31_Pos)
     
    #define CAN_F1R2_FB31   CAN_F1R2_FB31_Msk
     
    #define CAN_F2R2_FB0_Pos   (0U)
     
    #define CAN_F2R2_FB0_Msk   (0x1UL << CAN_F2R2_FB0_Pos)
     
    #define CAN_F2R2_FB0   CAN_F2R2_FB0_Msk
     
    #define CAN_F2R2_FB1_Pos   (1U)
     
    #define CAN_F2R2_FB1_Msk   (0x1UL << CAN_F2R2_FB1_Pos)
     
    #define CAN_F2R2_FB1   CAN_F2R2_FB1_Msk
     
    #define CAN_F2R2_FB2_Pos   (2U)
     
    #define CAN_F2R2_FB2_Msk   (0x1UL << CAN_F2R2_FB2_Pos)
     
    #define CAN_F2R2_FB2   CAN_F2R2_FB2_Msk
     
    #define CAN_F2R2_FB3_Pos   (3U)
     
    #define CAN_F2R2_FB3_Msk   (0x1UL << CAN_F2R2_FB3_Pos)
     
    #define CAN_F2R2_FB3   CAN_F2R2_FB3_Msk
     
    #define CAN_F2R2_FB4_Pos   (4U)
     
    #define CAN_F2R2_FB4_Msk   (0x1UL << CAN_F2R2_FB4_Pos)
     
    #define CAN_F2R2_FB4   CAN_F2R2_FB4_Msk
     
    #define CAN_F2R2_FB5_Pos   (5U)
     
    #define CAN_F2R2_FB5_Msk   (0x1UL << CAN_F2R2_FB5_Pos)
     
    #define CAN_F2R2_FB5   CAN_F2R2_FB5_Msk
     
    #define CAN_F2R2_FB6_Pos   (6U)
     
    #define CAN_F2R2_FB6_Msk   (0x1UL << CAN_F2R2_FB6_Pos)
     
    #define CAN_F2R2_FB6   CAN_F2R2_FB6_Msk
     
    #define CAN_F2R2_FB7_Pos   (7U)
     
    #define CAN_F2R2_FB7_Msk   (0x1UL << CAN_F2R2_FB7_Pos)
     
    #define CAN_F2R2_FB7   CAN_F2R2_FB7_Msk
     
    #define CAN_F2R2_FB8_Pos   (8U)
     
    #define CAN_F2R2_FB8_Msk   (0x1UL << CAN_F2R2_FB8_Pos)
     
    #define CAN_F2R2_FB8   CAN_F2R2_FB8_Msk
     
    #define CAN_F2R2_FB9_Pos   (9U)
     
    #define CAN_F2R2_FB9_Msk   (0x1UL << CAN_F2R2_FB9_Pos)
     
    #define CAN_F2R2_FB9   CAN_F2R2_FB9_Msk
     
    #define CAN_F2R2_FB10_Pos   (10U)
     
    #define CAN_F2R2_FB10_Msk   (0x1UL << CAN_F2R2_FB10_Pos)
     
    #define CAN_F2R2_FB10   CAN_F2R2_FB10_Msk
     
    #define CAN_F2R2_FB11_Pos   (11U)
     
    #define CAN_F2R2_FB11_Msk   (0x1UL << CAN_F2R2_FB11_Pos)
     
    #define CAN_F2R2_FB11   CAN_F2R2_FB11_Msk
     
    #define CAN_F2R2_FB12_Pos   (12U)
     
    #define CAN_F2R2_FB12_Msk   (0x1UL << CAN_F2R2_FB12_Pos)
     
    #define CAN_F2R2_FB12   CAN_F2R2_FB12_Msk
     
    #define CAN_F2R2_FB13_Pos   (13U)
     
    #define CAN_F2R2_FB13_Msk   (0x1UL << CAN_F2R2_FB13_Pos)
     
    #define CAN_F2R2_FB13   CAN_F2R2_FB13_Msk
     
    #define CAN_F2R2_FB14_Pos   (14U)
     
    #define CAN_F2R2_FB14_Msk   (0x1UL << CAN_F2R2_FB14_Pos)
     
    #define CAN_F2R2_FB14   CAN_F2R2_FB14_Msk
     
    #define CAN_F2R2_FB15_Pos   (15U)
     
    #define CAN_F2R2_FB15_Msk   (0x1UL << CAN_F2R2_FB15_Pos)
     
    #define CAN_F2R2_FB15   CAN_F2R2_FB15_Msk
     
    #define CAN_F2R2_FB16_Pos   (16U)
     
    #define CAN_F2R2_FB16_Msk   (0x1UL << CAN_F2R2_FB16_Pos)
     
    #define CAN_F2R2_FB16   CAN_F2R2_FB16_Msk
     
    #define CAN_F2R2_FB17_Pos   (17U)
     
    #define CAN_F2R2_FB17_Msk   (0x1UL << CAN_F2R2_FB17_Pos)
     
    #define CAN_F2R2_FB17   CAN_F2R2_FB17_Msk
     
    #define CAN_F2R2_FB18_Pos   (18U)
     
    #define CAN_F2R2_FB18_Msk   (0x1UL << CAN_F2R2_FB18_Pos)
     
    #define CAN_F2R2_FB18   CAN_F2R2_FB18_Msk
     
    #define CAN_F2R2_FB19_Pos   (19U)
     
    #define CAN_F2R2_FB19_Msk   (0x1UL << CAN_F2R2_FB19_Pos)
     
    #define CAN_F2R2_FB19   CAN_F2R2_FB19_Msk
     
    #define CAN_F2R2_FB20_Pos   (20U)
     
    #define CAN_F2R2_FB20_Msk   (0x1UL << CAN_F2R2_FB20_Pos)
     
    #define CAN_F2R2_FB20   CAN_F2R2_FB20_Msk
     
    #define CAN_F2R2_FB21_Pos   (21U)
     
    #define CAN_F2R2_FB21_Msk   (0x1UL << CAN_F2R2_FB21_Pos)
     
    #define CAN_F2R2_FB21   CAN_F2R2_FB21_Msk
     
    #define CAN_F2R2_FB22_Pos   (22U)
     
    #define CAN_F2R2_FB22_Msk   (0x1UL << CAN_F2R2_FB22_Pos)
     
    #define CAN_F2R2_FB22   CAN_F2R2_FB22_Msk
     
    #define CAN_F2R2_FB23_Pos   (23U)
     
    #define CAN_F2R2_FB23_Msk   (0x1UL << CAN_F2R2_FB23_Pos)
     
    #define CAN_F2R2_FB23   CAN_F2R2_FB23_Msk
     
    #define CAN_F2R2_FB24_Pos   (24U)
     
    #define CAN_F2R2_FB24_Msk   (0x1UL << CAN_F2R2_FB24_Pos)
     
    #define CAN_F2R2_FB24   CAN_F2R2_FB24_Msk
     
    #define CAN_F2R2_FB25_Pos   (25U)
     
    #define CAN_F2R2_FB25_Msk   (0x1UL << CAN_F2R2_FB25_Pos)
     
    #define CAN_F2R2_FB25   CAN_F2R2_FB25_Msk
     
    #define CAN_F2R2_FB26_Pos   (26U)
     
    #define CAN_F2R2_FB26_Msk   (0x1UL << CAN_F2R2_FB26_Pos)
     
    #define CAN_F2R2_FB26   CAN_F2R2_FB26_Msk
     
    #define CAN_F2R2_FB27_Pos   (27U)
     
    #define CAN_F2R2_FB27_Msk   (0x1UL << CAN_F2R2_FB27_Pos)
     
    #define CAN_F2R2_FB27   CAN_F2R2_FB27_Msk
     
    #define CAN_F2R2_FB28_Pos   (28U)
     
    #define CAN_F2R2_FB28_Msk   (0x1UL << CAN_F2R2_FB28_Pos)
     
    #define CAN_F2R2_FB28   CAN_F2R2_FB28_Msk
     
    #define CAN_F2R2_FB29_Pos   (29U)
     
    #define CAN_F2R2_FB29_Msk   (0x1UL << CAN_F2R2_FB29_Pos)
     
    #define CAN_F2R2_FB29   CAN_F2R2_FB29_Msk
     
    #define CAN_F2R2_FB30_Pos   (30U)
     
    #define CAN_F2R2_FB30_Msk   (0x1UL << CAN_F2R2_FB30_Pos)
     
    #define CAN_F2R2_FB30   CAN_F2R2_FB30_Msk
     
    #define CAN_F2R2_FB31_Pos   (31U)
     
    #define CAN_F2R2_FB31_Msk   (0x1UL << CAN_F2R2_FB31_Pos)
     
    #define CAN_F2R2_FB31   CAN_F2R2_FB31_Msk
     
    #define CAN_F3R2_FB0_Pos   (0U)
     
    #define CAN_F3R2_FB0_Msk   (0x1UL << CAN_F3R2_FB0_Pos)
     
    #define CAN_F3R2_FB0   CAN_F3R2_FB0_Msk
     
    #define CAN_F3R2_FB1_Pos   (1U)
     
    #define CAN_F3R2_FB1_Msk   (0x1UL << CAN_F3R2_FB1_Pos)
     
    #define CAN_F3R2_FB1   CAN_F3R2_FB1_Msk
     
    #define CAN_F3R2_FB2_Pos   (2U)
     
    #define CAN_F3R2_FB2_Msk   (0x1UL << CAN_F3R2_FB2_Pos)
     
    #define CAN_F3R2_FB2   CAN_F3R2_FB2_Msk
     
    #define CAN_F3R2_FB3_Pos   (3U)
     
    #define CAN_F3R2_FB3_Msk   (0x1UL << CAN_F3R2_FB3_Pos)
     
    #define CAN_F3R2_FB3   CAN_F3R2_FB3_Msk
     
    #define CAN_F3R2_FB4_Pos   (4U)
     
    #define CAN_F3R2_FB4_Msk   (0x1UL << CAN_F3R2_FB4_Pos)
     
    #define CAN_F3R2_FB4   CAN_F3R2_FB4_Msk
     
    #define CAN_F3R2_FB5_Pos   (5U)
     
    #define CAN_F3R2_FB5_Msk   (0x1UL << CAN_F3R2_FB5_Pos)
     
    #define CAN_F3R2_FB5   CAN_F3R2_FB5_Msk
     
    #define CAN_F3R2_FB6_Pos   (6U)
     
    #define CAN_F3R2_FB6_Msk   (0x1UL << CAN_F3R2_FB6_Pos)
     
    #define CAN_F3R2_FB6   CAN_F3R2_FB6_Msk
     
    #define CAN_F3R2_FB7_Pos   (7U)
     
    #define CAN_F3R2_FB7_Msk   (0x1UL << CAN_F3R2_FB7_Pos)
     
    #define CAN_F3R2_FB7   CAN_F3R2_FB7_Msk
     
    #define CAN_F3R2_FB8_Pos   (8U)
     
    #define CAN_F3R2_FB8_Msk   (0x1UL << CAN_F3R2_FB8_Pos)
     
    #define CAN_F3R2_FB8   CAN_F3R2_FB8_Msk
     
    #define CAN_F3R2_FB9_Pos   (9U)
     
    #define CAN_F3R2_FB9_Msk   (0x1UL << CAN_F3R2_FB9_Pos)
     
    #define CAN_F3R2_FB9   CAN_F3R2_FB9_Msk
     
    #define CAN_F3R2_FB10_Pos   (10U)
     
    #define CAN_F3R2_FB10_Msk   (0x1UL << CAN_F3R2_FB10_Pos)
     
    #define CAN_F3R2_FB10   CAN_F3R2_FB10_Msk
     
    #define CAN_F3R2_FB11_Pos   (11U)
     
    #define CAN_F3R2_FB11_Msk   (0x1UL << CAN_F3R2_FB11_Pos)
     
    #define CAN_F3R2_FB11   CAN_F3R2_FB11_Msk
     
    #define CAN_F3R2_FB12_Pos   (12U)
     
    #define CAN_F3R2_FB12_Msk   (0x1UL << CAN_F3R2_FB12_Pos)
     
    #define CAN_F3R2_FB12   CAN_F3R2_FB12_Msk
     
    #define CAN_F3R2_FB13_Pos   (13U)
     
    #define CAN_F3R2_FB13_Msk   (0x1UL << CAN_F3R2_FB13_Pos)
     
    #define CAN_F3R2_FB13   CAN_F3R2_FB13_Msk
     
    #define CAN_F3R2_FB14_Pos   (14U)
     
    #define CAN_F3R2_FB14_Msk   (0x1UL << CAN_F3R2_FB14_Pos)
     
    #define CAN_F3R2_FB14   CAN_F3R2_FB14_Msk
     
    #define CAN_F3R2_FB15_Pos   (15U)
     
    #define CAN_F3R2_FB15_Msk   (0x1UL << CAN_F3R2_FB15_Pos)
     
    #define CAN_F3R2_FB15   CAN_F3R2_FB15_Msk
     
    #define CAN_F3R2_FB16_Pos   (16U)
     
    #define CAN_F3R2_FB16_Msk   (0x1UL << CAN_F3R2_FB16_Pos)
     
    #define CAN_F3R2_FB16   CAN_F3R2_FB16_Msk
     
    #define CAN_F3R2_FB17_Pos   (17U)
     
    #define CAN_F3R2_FB17_Msk   (0x1UL << CAN_F3R2_FB17_Pos)
     
    #define CAN_F3R2_FB17   CAN_F3R2_FB17_Msk
     
    #define CAN_F3R2_FB18_Pos   (18U)
     
    #define CAN_F3R2_FB18_Msk   (0x1UL << CAN_F3R2_FB18_Pos)
     
    #define CAN_F3R2_FB18   CAN_F3R2_FB18_Msk
     
    #define CAN_F3R2_FB19_Pos   (19U)
     
    #define CAN_F3R2_FB19_Msk   (0x1UL << CAN_F3R2_FB19_Pos)
     
    #define CAN_F3R2_FB19   CAN_F3R2_FB19_Msk
     
    #define CAN_F3R2_FB20_Pos   (20U)
     
    #define CAN_F3R2_FB20_Msk   (0x1UL << CAN_F3R2_FB20_Pos)
     
    #define CAN_F3R2_FB20   CAN_F3R2_FB20_Msk
     
    #define CAN_F3R2_FB21_Pos   (21U)
     
    #define CAN_F3R2_FB21_Msk   (0x1UL << CAN_F3R2_FB21_Pos)
     
    #define CAN_F3R2_FB21   CAN_F3R2_FB21_Msk
     
    #define CAN_F3R2_FB22_Pos   (22U)
     
    #define CAN_F3R2_FB22_Msk   (0x1UL << CAN_F3R2_FB22_Pos)
     
    #define CAN_F3R2_FB22   CAN_F3R2_FB22_Msk
     
    #define CAN_F3R2_FB23_Pos   (23U)
     
    #define CAN_F3R2_FB23_Msk   (0x1UL << CAN_F3R2_FB23_Pos)
     
    #define CAN_F3R2_FB23   CAN_F3R2_FB23_Msk
     
    #define CAN_F3R2_FB24_Pos   (24U)
     
    #define CAN_F3R2_FB24_Msk   (0x1UL << CAN_F3R2_FB24_Pos)
     
    #define CAN_F3R2_FB24   CAN_F3R2_FB24_Msk
     
    #define CAN_F3R2_FB25_Pos   (25U)
     
    #define CAN_F3R2_FB25_Msk   (0x1UL << CAN_F3R2_FB25_Pos)
     
    #define CAN_F3R2_FB25   CAN_F3R2_FB25_Msk
     
    #define CAN_F3R2_FB26_Pos   (26U)
     
    #define CAN_F3R2_FB26_Msk   (0x1UL << CAN_F3R2_FB26_Pos)
     
    #define CAN_F3R2_FB26   CAN_F3R2_FB26_Msk
     
    #define CAN_F3R2_FB27_Pos   (27U)
     
    #define CAN_F3R2_FB27_Msk   (0x1UL << CAN_F3R2_FB27_Pos)
     
    #define CAN_F3R2_FB27   CAN_F3R2_FB27_Msk
     
    #define CAN_F3R2_FB28_Pos   (28U)
     
    #define CAN_F3R2_FB28_Msk   (0x1UL << CAN_F3R2_FB28_Pos)
     
    #define CAN_F3R2_FB28   CAN_F3R2_FB28_Msk
     
    #define CAN_F3R2_FB29_Pos   (29U)
     
    #define CAN_F3R2_FB29_Msk   (0x1UL << CAN_F3R2_FB29_Pos)
     
    #define CAN_F3R2_FB29   CAN_F3R2_FB29_Msk
     
    #define CAN_F3R2_FB30_Pos   (30U)
     
    #define CAN_F3R2_FB30_Msk   (0x1UL << CAN_F3R2_FB30_Pos)
     
    #define CAN_F3R2_FB30   CAN_F3R2_FB30_Msk
     
    #define CAN_F3R2_FB31_Pos   (31U)
     
    #define CAN_F3R2_FB31_Msk   (0x1UL << CAN_F3R2_FB31_Pos)
     
    #define CAN_F3R2_FB31   CAN_F3R2_FB31_Msk
     
    #define CAN_F4R2_FB0_Pos   (0U)
     
    #define CAN_F4R2_FB0_Msk   (0x1UL << CAN_F4R2_FB0_Pos)
     
    #define CAN_F4R2_FB0   CAN_F4R2_FB0_Msk
     
    #define CAN_F4R2_FB1_Pos   (1U)
     
    #define CAN_F4R2_FB1_Msk   (0x1UL << CAN_F4R2_FB1_Pos)
     
    #define CAN_F4R2_FB1   CAN_F4R2_FB1_Msk
     
    #define CAN_F4R2_FB2_Pos   (2U)
     
    #define CAN_F4R2_FB2_Msk   (0x1UL << CAN_F4R2_FB2_Pos)
     
    #define CAN_F4R2_FB2   CAN_F4R2_FB2_Msk
     
    #define CAN_F4R2_FB3_Pos   (3U)
     
    #define CAN_F4R2_FB3_Msk   (0x1UL << CAN_F4R2_FB3_Pos)
     
    #define CAN_F4R2_FB3   CAN_F4R2_FB3_Msk
     
    #define CAN_F4R2_FB4_Pos   (4U)
     
    #define CAN_F4R2_FB4_Msk   (0x1UL << CAN_F4R2_FB4_Pos)
     
    #define CAN_F4R2_FB4   CAN_F4R2_FB4_Msk
     
    #define CAN_F4R2_FB5_Pos   (5U)
     
    #define CAN_F4R2_FB5_Msk   (0x1UL << CAN_F4R2_FB5_Pos)
     
    #define CAN_F4R2_FB5   CAN_F4R2_FB5_Msk
     
    #define CAN_F4R2_FB6_Pos   (6U)
     
    #define CAN_F4R2_FB6_Msk   (0x1UL << CAN_F4R2_FB6_Pos)
     
    #define CAN_F4R2_FB6   CAN_F4R2_FB6_Msk
     
    #define CAN_F4R2_FB7_Pos   (7U)
     
    #define CAN_F4R2_FB7_Msk   (0x1UL << CAN_F4R2_FB7_Pos)
     
    #define CAN_F4R2_FB7   CAN_F4R2_FB7_Msk
     
    #define CAN_F4R2_FB8_Pos   (8U)
     
    #define CAN_F4R2_FB8_Msk   (0x1UL << CAN_F4R2_FB8_Pos)
     
    #define CAN_F4R2_FB8   CAN_F4R2_FB8_Msk
     
    #define CAN_F4R2_FB9_Pos   (9U)
     
    #define CAN_F4R2_FB9_Msk   (0x1UL << CAN_F4R2_FB9_Pos)
     
    #define CAN_F4R2_FB9   CAN_F4R2_FB9_Msk
     
    #define CAN_F4R2_FB10_Pos   (10U)
     
    #define CAN_F4R2_FB10_Msk   (0x1UL << CAN_F4R2_FB10_Pos)
     
    #define CAN_F4R2_FB10   CAN_F4R2_FB10_Msk
     
    #define CAN_F4R2_FB11_Pos   (11U)
     
    #define CAN_F4R2_FB11_Msk   (0x1UL << CAN_F4R2_FB11_Pos)
     
    #define CAN_F4R2_FB11   CAN_F4R2_FB11_Msk
     
    #define CAN_F4R2_FB12_Pos   (12U)
     
    #define CAN_F4R2_FB12_Msk   (0x1UL << CAN_F4R2_FB12_Pos)
     
    #define CAN_F4R2_FB12   CAN_F4R2_FB12_Msk
     
    #define CAN_F4R2_FB13_Pos   (13U)
     
    #define CAN_F4R2_FB13_Msk   (0x1UL << CAN_F4R2_FB13_Pos)
     
    #define CAN_F4R2_FB13   CAN_F4R2_FB13_Msk
     
    #define CAN_F4R2_FB14_Pos   (14U)
     
    #define CAN_F4R2_FB14_Msk   (0x1UL << CAN_F4R2_FB14_Pos)
     
    #define CAN_F4R2_FB14   CAN_F4R2_FB14_Msk
     
    #define CAN_F4R2_FB15_Pos   (15U)
     
    #define CAN_F4R2_FB15_Msk   (0x1UL << CAN_F4R2_FB15_Pos)
     
    #define CAN_F4R2_FB15   CAN_F4R2_FB15_Msk
     
    #define CAN_F4R2_FB16_Pos   (16U)
     
    #define CAN_F4R2_FB16_Msk   (0x1UL << CAN_F4R2_FB16_Pos)
     
    #define CAN_F4R2_FB16   CAN_F4R2_FB16_Msk
     
    #define CAN_F4R2_FB17_Pos   (17U)
     
    #define CAN_F4R2_FB17_Msk   (0x1UL << CAN_F4R2_FB17_Pos)
     
    #define CAN_F4R2_FB17   CAN_F4R2_FB17_Msk
     
    #define CAN_F4R2_FB18_Pos   (18U)
     
    #define CAN_F4R2_FB18_Msk   (0x1UL << CAN_F4R2_FB18_Pos)
     
    #define CAN_F4R2_FB18   CAN_F4R2_FB18_Msk
     
    #define CAN_F4R2_FB19_Pos   (19U)
     
    #define CAN_F4R2_FB19_Msk   (0x1UL << CAN_F4R2_FB19_Pos)
     
    #define CAN_F4R2_FB19   CAN_F4R2_FB19_Msk
     
    #define CAN_F4R2_FB20_Pos   (20U)
     
    #define CAN_F4R2_FB20_Msk   (0x1UL << CAN_F4R2_FB20_Pos)
     
    #define CAN_F4R2_FB20   CAN_F4R2_FB20_Msk
     
    #define CAN_F4R2_FB21_Pos   (21U)
     
    #define CAN_F4R2_FB21_Msk   (0x1UL << CAN_F4R2_FB21_Pos)
     
    #define CAN_F4R2_FB21   CAN_F4R2_FB21_Msk
     
    #define CAN_F4R2_FB22_Pos   (22U)
     
    #define CAN_F4R2_FB22_Msk   (0x1UL << CAN_F4R2_FB22_Pos)
     
    #define CAN_F4R2_FB22   CAN_F4R2_FB22_Msk
     
    #define CAN_F4R2_FB23_Pos   (23U)
     
    #define CAN_F4R2_FB23_Msk   (0x1UL << CAN_F4R2_FB23_Pos)
     
    #define CAN_F4R2_FB23   CAN_F4R2_FB23_Msk
     
    #define CAN_F4R2_FB24_Pos   (24U)
     
    #define CAN_F4R2_FB24_Msk   (0x1UL << CAN_F4R2_FB24_Pos)
     
    #define CAN_F4R2_FB24   CAN_F4R2_FB24_Msk
     
    #define CAN_F4R2_FB25_Pos   (25U)
     
    #define CAN_F4R2_FB25_Msk   (0x1UL << CAN_F4R2_FB25_Pos)
     
    #define CAN_F4R2_FB25   CAN_F4R2_FB25_Msk
     
    #define CAN_F4R2_FB26_Pos   (26U)
     
    #define CAN_F4R2_FB26_Msk   (0x1UL << CAN_F4R2_FB26_Pos)
     
    #define CAN_F4R2_FB26   CAN_F4R2_FB26_Msk
     
    #define CAN_F4R2_FB27_Pos   (27U)
     
    #define CAN_F4R2_FB27_Msk   (0x1UL << CAN_F4R2_FB27_Pos)
     
    #define CAN_F4R2_FB27   CAN_F4R2_FB27_Msk
     
    #define CAN_F4R2_FB28_Pos   (28U)
     
    #define CAN_F4R2_FB28_Msk   (0x1UL << CAN_F4R2_FB28_Pos)
     
    #define CAN_F4R2_FB28   CAN_F4R2_FB28_Msk
     
    #define CAN_F4R2_FB29_Pos   (29U)
     
    #define CAN_F4R2_FB29_Msk   (0x1UL << CAN_F4R2_FB29_Pos)
     
    #define CAN_F4R2_FB29   CAN_F4R2_FB29_Msk
     
    #define CAN_F4R2_FB30_Pos   (30U)
     
    #define CAN_F4R2_FB30_Msk   (0x1UL << CAN_F4R2_FB30_Pos)
     
    #define CAN_F4R2_FB30   CAN_F4R2_FB30_Msk
     
    #define CAN_F4R2_FB31_Pos   (31U)
     
    #define CAN_F4R2_FB31_Msk   (0x1UL << CAN_F4R2_FB31_Pos)
     
    #define CAN_F4R2_FB31   CAN_F4R2_FB31_Msk
     
    #define CAN_F5R2_FB0_Pos   (0U)
     
    #define CAN_F5R2_FB0_Msk   (0x1UL << CAN_F5R2_FB0_Pos)
     
    #define CAN_F5R2_FB0   CAN_F5R2_FB0_Msk
     
    #define CAN_F5R2_FB1_Pos   (1U)
     
    #define CAN_F5R2_FB1_Msk   (0x1UL << CAN_F5R2_FB1_Pos)
     
    #define CAN_F5R2_FB1   CAN_F5R2_FB1_Msk
     
    #define CAN_F5R2_FB2_Pos   (2U)
     
    #define CAN_F5R2_FB2_Msk   (0x1UL << CAN_F5R2_FB2_Pos)
     
    #define CAN_F5R2_FB2   CAN_F5R2_FB2_Msk
     
    #define CAN_F5R2_FB3_Pos   (3U)
     
    #define CAN_F5R2_FB3_Msk   (0x1UL << CAN_F5R2_FB3_Pos)
     
    #define CAN_F5R2_FB3   CAN_F5R2_FB3_Msk
     
    #define CAN_F5R2_FB4_Pos   (4U)
     
    #define CAN_F5R2_FB4_Msk   (0x1UL << CAN_F5R2_FB4_Pos)
     
    #define CAN_F5R2_FB4   CAN_F5R2_FB4_Msk
     
    #define CAN_F5R2_FB5_Pos   (5U)
     
    #define CAN_F5R2_FB5_Msk   (0x1UL << CAN_F5R2_FB5_Pos)
     
    #define CAN_F5R2_FB5   CAN_F5R2_FB5_Msk
     
    #define CAN_F5R2_FB6_Pos   (6U)
     
    #define CAN_F5R2_FB6_Msk   (0x1UL << CAN_F5R2_FB6_Pos)
     
    #define CAN_F5R2_FB6   CAN_F5R2_FB6_Msk
     
    #define CAN_F5R2_FB7_Pos   (7U)
     
    #define CAN_F5R2_FB7_Msk   (0x1UL << CAN_F5R2_FB7_Pos)
     
    #define CAN_F5R2_FB7   CAN_F5R2_FB7_Msk
     
    #define CAN_F5R2_FB8_Pos   (8U)
     
    #define CAN_F5R2_FB8_Msk   (0x1UL << CAN_F5R2_FB8_Pos)
     
    #define CAN_F5R2_FB8   CAN_F5R2_FB8_Msk
     
    #define CAN_F5R2_FB9_Pos   (9U)
     
    #define CAN_F5R2_FB9_Msk   (0x1UL << CAN_F5R2_FB9_Pos)
     
    #define CAN_F5R2_FB9   CAN_F5R2_FB9_Msk
     
    #define CAN_F5R2_FB10_Pos   (10U)
     
    #define CAN_F5R2_FB10_Msk   (0x1UL << CAN_F5R2_FB10_Pos)
     
    #define CAN_F5R2_FB10   CAN_F5R2_FB10_Msk
     
    #define CAN_F5R2_FB11_Pos   (11U)
     
    #define CAN_F5R2_FB11_Msk   (0x1UL << CAN_F5R2_FB11_Pos)
     
    #define CAN_F5R2_FB11   CAN_F5R2_FB11_Msk
     
    #define CAN_F5R2_FB12_Pos   (12U)
     
    #define CAN_F5R2_FB12_Msk   (0x1UL << CAN_F5R2_FB12_Pos)
     
    #define CAN_F5R2_FB12   CAN_F5R2_FB12_Msk
     
    #define CAN_F5R2_FB13_Pos   (13U)
     
    #define CAN_F5R2_FB13_Msk   (0x1UL << CAN_F5R2_FB13_Pos)
     
    #define CAN_F5R2_FB13   CAN_F5R2_FB13_Msk
     
    #define CAN_F5R2_FB14_Pos   (14U)
     
    #define CAN_F5R2_FB14_Msk   (0x1UL << CAN_F5R2_FB14_Pos)
     
    #define CAN_F5R2_FB14   CAN_F5R2_FB14_Msk
     
    #define CAN_F5R2_FB15_Pos   (15U)
     
    #define CAN_F5R2_FB15_Msk   (0x1UL << CAN_F5R2_FB15_Pos)
     
    #define CAN_F5R2_FB15   CAN_F5R2_FB15_Msk
     
    #define CAN_F5R2_FB16_Pos   (16U)
     
    #define CAN_F5R2_FB16_Msk   (0x1UL << CAN_F5R2_FB16_Pos)
     
    #define CAN_F5R2_FB16   CAN_F5R2_FB16_Msk
     
    #define CAN_F5R2_FB17_Pos   (17U)
     
    #define CAN_F5R2_FB17_Msk   (0x1UL << CAN_F5R2_FB17_Pos)
     
    #define CAN_F5R2_FB17   CAN_F5R2_FB17_Msk
     
    #define CAN_F5R2_FB18_Pos   (18U)
     
    #define CAN_F5R2_FB18_Msk   (0x1UL << CAN_F5R2_FB18_Pos)
     
    #define CAN_F5R2_FB18   CAN_F5R2_FB18_Msk
     
    #define CAN_F5R2_FB19_Pos   (19U)
     
    #define CAN_F5R2_FB19_Msk   (0x1UL << CAN_F5R2_FB19_Pos)
     
    #define CAN_F5R2_FB19   CAN_F5R2_FB19_Msk
     
    #define CAN_F5R2_FB20_Pos   (20U)
     
    #define CAN_F5R2_FB20_Msk   (0x1UL << CAN_F5R2_FB20_Pos)
     
    #define CAN_F5R2_FB20   CAN_F5R2_FB20_Msk
     
    #define CAN_F5R2_FB21_Pos   (21U)
     
    #define CAN_F5R2_FB21_Msk   (0x1UL << CAN_F5R2_FB21_Pos)
     
    #define CAN_F5R2_FB21   CAN_F5R2_FB21_Msk
     
    #define CAN_F5R2_FB22_Pos   (22U)
     
    #define CAN_F5R2_FB22_Msk   (0x1UL << CAN_F5R2_FB22_Pos)
     
    #define CAN_F5R2_FB22   CAN_F5R2_FB22_Msk
     
    #define CAN_F5R2_FB23_Pos   (23U)
     
    #define CAN_F5R2_FB23_Msk   (0x1UL << CAN_F5R2_FB23_Pos)
     
    #define CAN_F5R2_FB23   CAN_F5R2_FB23_Msk
     
    #define CAN_F5R2_FB24_Pos   (24U)
     
    #define CAN_F5R2_FB24_Msk   (0x1UL << CAN_F5R2_FB24_Pos)
     
    #define CAN_F5R2_FB24   CAN_F5R2_FB24_Msk
     
    #define CAN_F5R2_FB25_Pos   (25U)
     
    #define CAN_F5R2_FB25_Msk   (0x1UL << CAN_F5R2_FB25_Pos)
     
    #define CAN_F5R2_FB25   CAN_F5R2_FB25_Msk
     
    #define CAN_F5R2_FB26_Pos   (26U)
     
    #define CAN_F5R2_FB26_Msk   (0x1UL << CAN_F5R2_FB26_Pos)
     
    #define CAN_F5R2_FB26   CAN_F5R2_FB26_Msk
     
    #define CAN_F5R2_FB27_Pos   (27U)
     
    #define CAN_F5R2_FB27_Msk   (0x1UL << CAN_F5R2_FB27_Pos)
     
    #define CAN_F5R2_FB27   CAN_F5R2_FB27_Msk
     
    #define CAN_F5R2_FB28_Pos   (28U)
     
    #define CAN_F5R2_FB28_Msk   (0x1UL << CAN_F5R2_FB28_Pos)
     
    #define CAN_F5R2_FB28   CAN_F5R2_FB28_Msk
     
    #define CAN_F5R2_FB29_Pos   (29U)
     
    #define CAN_F5R2_FB29_Msk   (0x1UL << CAN_F5R2_FB29_Pos)
     
    #define CAN_F5R2_FB29   CAN_F5R2_FB29_Msk
     
    #define CAN_F5R2_FB30_Pos   (30U)
     
    #define CAN_F5R2_FB30_Msk   (0x1UL << CAN_F5R2_FB30_Pos)
     
    #define CAN_F5R2_FB30   CAN_F5R2_FB30_Msk
     
    #define CAN_F5R2_FB31_Pos   (31U)
     
    #define CAN_F5R2_FB31_Msk   (0x1UL << CAN_F5R2_FB31_Pos)
     
    #define CAN_F5R2_FB31   CAN_F5R2_FB31_Msk
     
    #define CAN_F6R2_FB0_Pos   (0U)
     
    #define CAN_F6R2_FB0_Msk   (0x1UL << CAN_F6R2_FB0_Pos)
     
    #define CAN_F6R2_FB0   CAN_F6R2_FB0_Msk
     
    #define CAN_F6R2_FB1_Pos   (1U)
     
    #define CAN_F6R2_FB1_Msk   (0x1UL << CAN_F6R2_FB1_Pos)
     
    #define CAN_F6R2_FB1   CAN_F6R2_FB1_Msk
     
    #define CAN_F6R2_FB2_Pos   (2U)
     
    #define CAN_F6R2_FB2_Msk   (0x1UL << CAN_F6R2_FB2_Pos)
     
    #define CAN_F6R2_FB2   CAN_F6R2_FB2_Msk
     
    #define CAN_F6R2_FB3_Pos   (3U)
     
    #define CAN_F6R2_FB3_Msk   (0x1UL << CAN_F6R2_FB3_Pos)
     
    #define CAN_F6R2_FB3   CAN_F6R2_FB3_Msk
     
    #define CAN_F6R2_FB4_Pos   (4U)
     
    #define CAN_F6R2_FB4_Msk   (0x1UL << CAN_F6R2_FB4_Pos)
     
    #define CAN_F6R2_FB4   CAN_F6R2_FB4_Msk
     
    #define CAN_F6R2_FB5_Pos   (5U)
     
    #define CAN_F6R2_FB5_Msk   (0x1UL << CAN_F6R2_FB5_Pos)
     
    #define CAN_F6R2_FB5   CAN_F6R2_FB5_Msk
     
    #define CAN_F6R2_FB6_Pos   (6U)
     
    #define CAN_F6R2_FB6_Msk   (0x1UL << CAN_F6R2_FB6_Pos)
     
    #define CAN_F6R2_FB6   CAN_F6R2_FB6_Msk
     
    #define CAN_F6R2_FB7_Pos   (7U)
     
    #define CAN_F6R2_FB7_Msk   (0x1UL << CAN_F6R2_FB7_Pos)
     
    #define CAN_F6R2_FB7   CAN_F6R2_FB7_Msk
     
    #define CAN_F6R2_FB8_Pos   (8U)
     
    #define CAN_F6R2_FB8_Msk   (0x1UL << CAN_F6R2_FB8_Pos)
     
    #define CAN_F6R2_FB8   CAN_F6R2_FB8_Msk
     
    #define CAN_F6R2_FB9_Pos   (9U)
     
    #define CAN_F6R2_FB9_Msk   (0x1UL << CAN_F6R2_FB9_Pos)
     
    #define CAN_F6R2_FB9   CAN_F6R2_FB9_Msk
     
    #define CAN_F6R2_FB10_Pos   (10U)
     
    #define CAN_F6R2_FB10_Msk   (0x1UL << CAN_F6R2_FB10_Pos)
     
    #define CAN_F6R2_FB10   CAN_F6R2_FB10_Msk
     
    #define CAN_F6R2_FB11_Pos   (11U)
     
    #define CAN_F6R2_FB11_Msk   (0x1UL << CAN_F6R2_FB11_Pos)
     
    #define CAN_F6R2_FB11   CAN_F6R2_FB11_Msk
     
    #define CAN_F6R2_FB12_Pos   (12U)
     
    #define CAN_F6R2_FB12_Msk   (0x1UL << CAN_F6R2_FB12_Pos)
     
    #define CAN_F6R2_FB12   CAN_F6R2_FB12_Msk
     
    #define CAN_F6R2_FB13_Pos   (13U)
     
    #define CAN_F6R2_FB13_Msk   (0x1UL << CAN_F6R2_FB13_Pos)
     
    #define CAN_F6R2_FB13   CAN_F6R2_FB13_Msk
     
    #define CAN_F6R2_FB14_Pos   (14U)
     
    #define CAN_F6R2_FB14_Msk   (0x1UL << CAN_F6R2_FB14_Pos)
     
    #define CAN_F6R2_FB14   CAN_F6R2_FB14_Msk
     
    #define CAN_F6R2_FB15_Pos   (15U)
     
    #define CAN_F6R2_FB15_Msk   (0x1UL << CAN_F6R2_FB15_Pos)
     
    #define CAN_F6R2_FB15   CAN_F6R2_FB15_Msk
     
    #define CAN_F6R2_FB16_Pos   (16U)
     
    #define CAN_F6R2_FB16_Msk   (0x1UL << CAN_F6R2_FB16_Pos)
     
    #define CAN_F6R2_FB16   CAN_F6R2_FB16_Msk
     
    #define CAN_F6R2_FB17_Pos   (17U)
     
    #define CAN_F6R2_FB17_Msk   (0x1UL << CAN_F6R2_FB17_Pos)
     
    #define CAN_F6R2_FB17   CAN_F6R2_FB17_Msk
     
    #define CAN_F6R2_FB18_Pos   (18U)
     
    #define CAN_F6R2_FB18_Msk   (0x1UL << CAN_F6R2_FB18_Pos)
     
    #define CAN_F6R2_FB18   CAN_F6R2_FB18_Msk
     
    #define CAN_F6R2_FB19_Pos   (19U)
     
    #define CAN_F6R2_FB19_Msk   (0x1UL << CAN_F6R2_FB19_Pos)
     
    #define CAN_F6R2_FB19   CAN_F6R2_FB19_Msk
     
    #define CAN_F6R2_FB20_Pos   (20U)
     
    #define CAN_F6R2_FB20_Msk   (0x1UL << CAN_F6R2_FB20_Pos)
     
    #define CAN_F6R2_FB20   CAN_F6R2_FB20_Msk
     
    #define CAN_F6R2_FB21_Pos   (21U)
     
    #define CAN_F6R2_FB21_Msk   (0x1UL << CAN_F6R2_FB21_Pos)
     
    #define CAN_F6R2_FB21   CAN_F6R2_FB21_Msk
     
    #define CAN_F6R2_FB22_Pos   (22U)
     
    #define CAN_F6R2_FB22_Msk   (0x1UL << CAN_F6R2_FB22_Pos)
     
    #define CAN_F6R2_FB22   CAN_F6R2_FB22_Msk
     
    #define CAN_F6R2_FB23_Pos   (23U)
     
    #define CAN_F6R2_FB23_Msk   (0x1UL << CAN_F6R2_FB23_Pos)
     
    #define CAN_F6R2_FB23   CAN_F6R2_FB23_Msk
     
    #define CAN_F6R2_FB24_Pos   (24U)
     
    #define CAN_F6R2_FB24_Msk   (0x1UL << CAN_F6R2_FB24_Pos)
     
    #define CAN_F6R2_FB24   CAN_F6R2_FB24_Msk
     
    #define CAN_F6R2_FB25_Pos   (25U)
     
    #define CAN_F6R2_FB25_Msk   (0x1UL << CAN_F6R2_FB25_Pos)
     
    #define CAN_F6R2_FB25   CAN_F6R2_FB25_Msk
     
    #define CAN_F6R2_FB26_Pos   (26U)
     
    #define CAN_F6R2_FB26_Msk   (0x1UL << CAN_F6R2_FB26_Pos)
     
    #define CAN_F6R2_FB26   CAN_F6R2_FB26_Msk
     
    #define CAN_F6R2_FB27_Pos   (27U)
     
    #define CAN_F6R2_FB27_Msk   (0x1UL << CAN_F6R2_FB27_Pos)
     
    #define CAN_F6R2_FB27   CAN_F6R2_FB27_Msk
     
    #define CAN_F6R2_FB28_Pos   (28U)
     
    #define CAN_F6R2_FB28_Msk   (0x1UL << CAN_F6R2_FB28_Pos)
     
    #define CAN_F6R2_FB28   CAN_F6R2_FB28_Msk
     
    #define CAN_F6R2_FB29_Pos   (29U)
     
    #define CAN_F6R2_FB29_Msk   (0x1UL << CAN_F6R2_FB29_Pos)
     
    #define CAN_F6R2_FB29   CAN_F6R2_FB29_Msk
     
    #define CAN_F6R2_FB30_Pos   (30U)
     
    #define CAN_F6R2_FB30_Msk   (0x1UL << CAN_F6R2_FB30_Pos)
     
    #define CAN_F6R2_FB30   CAN_F6R2_FB30_Msk
     
    #define CAN_F6R2_FB31_Pos   (31U)
     
    #define CAN_F6R2_FB31_Msk   (0x1UL << CAN_F6R2_FB31_Pos)
     
    #define CAN_F6R2_FB31   CAN_F6R2_FB31_Msk
     
    #define CAN_F7R2_FB0_Pos   (0U)
     
    #define CAN_F7R2_FB0_Msk   (0x1UL << CAN_F7R2_FB0_Pos)
     
    #define CAN_F7R2_FB0   CAN_F7R2_FB0_Msk
     
    #define CAN_F7R2_FB1_Pos   (1U)
     
    #define CAN_F7R2_FB1_Msk   (0x1UL << CAN_F7R2_FB1_Pos)
     
    #define CAN_F7R2_FB1   CAN_F7R2_FB1_Msk
     
    #define CAN_F7R2_FB2_Pos   (2U)
     
    #define CAN_F7R2_FB2_Msk   (0x1UL << CAN_F7R2_FB2_Pos)
     
    #define CAN_F7R2_FB2   CAN_F7R2_FB2_Msk
     
    #define CAN_F7R2_FB3_Pos   (3U)
     
    #define CAN_F7R2_FB3_Msk   (0x1UL << CAN_F7R2_FB3_Pos)
     
    #define CAN_F7R2_FB3   CAN_F7R2_FB3_Msk
     
    #define CAN_F7R2_FB4_Pos   (4U)
     
    #define CAN_F7R2_FB4_Msk   (0x1UL << CAN_F7R2_FB4_Pos)
     
    #define CAN_F7R2_FB4   CAN_F7R2_FB4_Msk
     
    #define CAN_F7R2_FB5_Pos   (5U)
     
    #define CAN_F7R2_FB5_Msk   (0x1UL << CAN_F7R2_FB5_Pos)
     
    #define CAN_F7R2_FB5   CAN_F7R2_FB5_Msk
     
    #define CAN_F7R2_FB6_Pos   (6U)
     
    #define CAN_F7R2_FB6_Msk   (0x1UL << CAN_F7R2_FB6_Pos)
     
    #define CAN_F7R2_FB6   CAN_F7R2_FB6_Msk
     
    #define CAN_F7R2_FB7_Pos   (7U)
     
    #define CAN_F7R2_FB7_Msk   (0x1UL << CAN_F7R2_FB7_Pos)
     
    #define CAN_F7R2_FB7   CAN_F7R2_FB7_Msk
     
    #define CAN_F7R2_FB8_Pos   (8U)
     
    #define CAN_F7R2_FB8_Msk   (0x1UL << CAN_F7R2_FB8_Pos)
     
    #define CAN_F7R2_FB8   CAN_F7R2_FB8_Msk
     
    #define CAN_F7R2_FB9_Pos   (9U)
     
    #define CAN_F7R2_FB9_Msk   (0x1UL << CAN_F7R2_FB9_Pos)
     
    #define CAN_F7R2_FB9   CAN_F7R2_FB9_Msk
     
    #define CAN_F7R2_FB10_Pos   (10U)
     
    #define CAN_F7R2_FB10_Msk   (0x1UL << CAN_F7R2_FB10_Pos)
     
    #define CAN_F7R2_FB10   CAN_F7R2_FB10_Msk
     
    #define CAN_F7R2_FB11_Pos   (11U)
     
    #define CAN_F7R2_FB11_Msk   (0x1UL << CAN_F7R2_FB11_Pos)
     
    #define CAN_F7R2_FB11   CAN_F7R2_FB11_Msk
     
    #define CAN_F7R2_FB12_Pos   (12U)
     
    #define CAN_F7R2_FB12_Msk   (0x1UL << CAN_F7R2_FB12_Pos)
     
    #define CAN_F7R2_FB12   CAN_F7R2_FB12_Msk
     
    #define CAN_F7R2_FB13_Pos   (13U)
     
    #define CAN_F7R2_FB13_Msk   (0x1UL << CAN_F7R2_FB13_Pos)
     
    #define CAN_F7R2_FB13   CAN_F7R2_FB13_Msk
     
    #define CAN_F7R2_FB14_Pos   (14U)
     
    #define CAN_F7R2_FB14_Msk   (0x1UL << CAN_F7R2_FB14_Pos)
     
    #define CAN_F7R2_FB14   CAN_F7R2_FB14_Msk
     
    #define CAN_F7R2_FB15_Pos   (15U)
     
    #define CAN_F7R2_FB15_Msk   (0x1UL << CAN_F7R2_FB15_Pos)
     
    #define CAN_F7R2_FB15   CAN_F7R2_FB15_Msk
     
    #define CAN_F7R2_FB16_Pos   (16U)
     
    #define CAN_F7R2_FB16_Msk   (0x1UL << CAN_F7R2_FB16_Pos)
     
    #define CAN_F7R2_FB16   CAN_F7R2_FB16_Msk
     
    #define CAN_F7R2_FB17_Pos   (17U)
     
    #define CAN_F7R2_FB17_Msk   (0x1UL << CAN_F7R2_FB17_Pos)
     
    #define CAN_F7R2_FB17   CAN_F7R2_FB17_Msk
     
    #define CAN_F7R2_FB18_Pos   (18U)
     
    #define CAN_F7R2_FB18_Msk   (0x1UL << CAN_F7R2_FB18_Pos)
     
    #define CAN_F7R2_FB18   CAN_F7R2_FB18_Msk
     
    #define CAN_F7R2_FB19_Pos   (19U)
     
    #define CAN_F7R2_FB19_Msk   (0x1UL << CAN_F7R2_FB19_Pos)
     
    #define CAN_F7R2_FB19   CAN_F7R2_FB19_Msk
     
    #define CAN_F7R2_FB20_Pos   (20U)
     
    #define CAN_F7R2_FB20_Msk   (0x1UL << CAN_F7R2_FB20_Pos)
     
    #define CAN_F7R2_FB20   CAN_F7R2_FB20_Msk
     
    #define CAN_F7R2_FB21_Pos   (21U)
     
    #define CAN_F7R2_FB21_Msk   (0x1UL << CAN_F7R2_FB21_Pos)
     
    #define CAN_F7R2_FB21   CAN_F7R2_FB21_Msk
     
    #define CAN_F7R2_FB22_Pos   (22U)
     
    #define CAN_F7R2_FB22_Msk   (0x1UL << CAN_F7R2_FB22_Pos)
     
    #define CAN_F7R2_FB22   CAN_F7R2_FB22_Msk
     
    #define CAN_F7R2_FB23_Pos   (23U)
     
    #define CAN_F7R2_FB23_Msk   (0x1UL << CAN_F7R2_FB23_Pos)
     
    #define CAN_F7R2_FB23   CAN_F7R2_FB23_Msk
     
    #define CAN_F7R2_FB24_Pos   (24U)
     
    #define CAN_F7R2_FB24_Msk   (0x1UL << CAN_F7R2_FB24_Pos)
     
    #define CAN_F7R2_FB24   CAN_F7R2_FB24_Msk
     
    #define CAN_F7R2_FB25_Pos   (25U)
     
    #define CAN_F7R2_FB25_Msk   (0x1UL << CAN_F7R2_FB25_Pos)
     
    #define CAN_F7R2_FB25   CAN_F7R2_FB25_Msk
     
    #define CAN_F7R2_FB26_Pos   (26U)
     
    #define CAN_F7R2_FB26_Msk   (0x1UL << CAN_F7R2_FB26_Pos)
     
    #define CAN_F7R2_FB26   CAN_F7R2_FB26_Msk
     
    #define CAN_F7R2_FB27_Pos   (27U)
     
    #define CAN_F7R2_FB27_Msk   (0x1UL << CAN_F7R2_FB27_Pos)
     
    #define CAN_F7R2_FB27   CAN_F7R2_FB27_Msk
     
    #define CAN_F7R2_FB28_Pos   (28U)
     
    #define CAN_F7R2_FB28_Msk   (0x1UL << CAN_F7R2_FB28_Pos)
     
    #define CAN_F7R2_FB28   CAN_F7R2_FB28_Msk
     
    #define CAN_F7R2_FB29_Pos   (29U)
     
    #define CAN_F7R2_FB29_Msk   (0x1UL << CAN_F7R2_FB29_Pos)
     
    #define CAN_F7R2_FB29   CAN_F7R2_FB29_Msk
     
    #define CAN_F7R2_FB30_Pos   (30U)
     
    #define CAN_F7R2_FB30_Msk   (0x1UL << CAN_F7R2_FB30_Pos)
     
    #define CAN_F7R2_FB30   CAN_F7R2_FB30_Msk
     
    #define CAN_F7R2_FB31_Pos   (31U)
     
    #define CAN_F7R2_FB31_Msk   (0x1UL << CAN_F7R2_FB31_Pos)
     
    #define CAN_F7R2_FB31   CAN_F7R2_FB31_Msk
     
    #define CAN_F8R2_FB0_Pos   (0U)
     
    #define CAN_F8R2_FB0_Msk   (0x1UL << CAN_F8R2_FB0_Pos)
     
    #define CAN_F8R2_FB0   CAN_F8R2_FB0_Msk
     
    #define CAN_F8R2_FB1_Pos   (1U)
     
    #define CAN_F8R2_FB1_Msk   (0x1UL << CAN_F8R2_FB1_Pos)
     
    #define CAN_F8R2_FB1   CAN_F8R2_FB1_Msk
     
    #define CAN_F8R2_FB2_Pos   (2U)
     
    #define CAN_F8R2_FB2_Msk   (0x1UL << CAN_F8R2_FB2_Pos)
     
    #define CAN_F8R2_FB2   CAN_F8R2_FB2_Msk
     
    #define CAN_F8R2_FB3_Pos   (3U)
     
    #define CAN_F8R2_FB3_Msk   (0x1UL << CAN_F8R2_FB3_Pos)
     
    #define CAN_F8R2_FB3   CAN_F8R2_FB3_Msk
     
    #define CAN_F8R2_FB4_Pos   (4U)
     
    #define CAN_F8R2_FB4_Msk   (0x1UL << CAN_F8R2_FB4_Pos)
     
    #define CAN_F8R2_FB4   CAN_F8R2_FB4_Msk
     
    #define CAN_F8R2_FB5_Pos   (5U)
     
    #define CAN_F8R2_FB5_Msk   (0x1UL << CAN_F8R2_FB5_Pos)
     
    #define CAN_F8R2_FB5   CAN_F8R2_FB5_Msk
     
    #define CAN_F8R2_FB6_Pos   (6U)
     
    #define CAN_F8R2_FB6_Msk   (0x1UL << CAN_F8R2_FB6_Pos)
     
    #define CAN_F8R2_FB6   CAN_F8R2_FB6_Msk
     
    #define CAN_F8R2_FB7_Pos   (7U)
     
    #define CAN_F8R2_FB7_Msk   (0x1UL << CAN_F8R2_FB7_Pos)
     
    #define CAN_F8R2_FB7   CAN_F8R2_FB7_Msk
     
    #define CAN_F8R2_FB8_Pos   (8U)
     
    #define CAN_F8R2_FB8_Msk   (0x1UL << CAN_F8R2_FB8_Pos)
     
    #define CAN_F8R2_FB8   CAN_F8R2_FB8_Msk
     
    #define CAN_F8R2_FB9_Pos   (9U)
     
    #define CAN_F8R2_FB9_Msk   (0x1UL << CAN_F8R2_FB9_Pos)
     
    #define CAN_F8R2_FB9   CAN_F8R2_FB9_Msk
     
    #define CAN_F8R2_FB10_Pos   (10U)
     
    #define CAN_F8R2_FB10_Msk   (0x1UL << CAN_F8R2_FB10_Pos)
     
    #define CAN_F8R2_FB10   CAN_F8R2_FB10_Msk
     
    #define CAN_F8R2_FB11_Pos   (11U)
     
    #define CAN_F8R2_FB11_Msk   (0x1UL << CAN_F8R2_FB11_Pos)
     
    #define CAN_F8R2_FB11   CAN_F8R2_FB11_Msk
     
    #define CAN_F8R2_FB12_Pos   (12U)
     
    #define CAN_F8R2_FB12_Msk   (0x1UL << CAN_F8R2_FB12_Pos)
     
    #define CAN_F8R2_FB12   CAN_F8R2_FB12_Msk
     
    #define CAN_F8R2_FB13_Pos   (13U)
     
    #define CAN_F8R2_FB13_Msk   (0x1UL << CAN_F8R2_FB13_Pos)
     
    #define CAN_F8R2_FB13   CAN_F8R2_FB13_Msk
     
    #define CAN_F8R2_FB14_Pos   (14U)
     
    #define CAN_F8R2_FB14_Msk   (0x1UL << CAN_F8R2_FB14_Pos)
     
    #define CAN_F8R2_FB14   CAN_F8R2_FB14_Msk
     
    #define CAN_F8R2_FB15_Pos   (15U)
     
    #define CAN_F8R2_FB15_Msk   (0x1UL << CAN_F8R2_FB15_Pos)
     
    #define CAN_F8R2_FB15   CAN_F8R2_FB15_Msk
     
    #define CAN_F8R2_FB16_Pos   (16U)
     
    #define CAN_F8R2_FB16_Msk   (0x1UL << CAN_F8R2_FB16_Pos)
     
    #define CAN_F8R2_FB16   CAN_F8R2_FB16_Msk
     
    #define CAN_F8R2_FB17_Pos   (17U)
     
    #define CAN_F8R2_FB17_Msk   (0x1UL << CAN_F8R2_FB17_Pos)
     
    #define CAN_F8R2_FB17   CAN_F8R2_FB17_Msk
     
    #define CAN_F8R2_FB18_Pos   (18U)
     
    #define CAN_F8R2_FB18_Msk   (0x1UL << CAN_F8R2_FB18_Pos)
     
    #define CAN_F8R2_FB18   CAN_F8R2_FB18_Msk
     
    #define CAN_F8R2_FB19_Pos   (19U)
     
    #define CAN_F8R2_FB19_Msk   (0x1UL << CAN_F8R2_FB19_Pos)
     
    #define CAN_F8R2_FB19   CAN_F8R2_FB19_Msk
     
    #define CAN_F8R2_FB20_Pos   (20U)
     
    #define CAN_F8R2_FB20_Msk   (0x1UL << CAN_F8R2_FB20_Pos)
     
    #define CAN_F8R2_FB20   CAN_F8R2_FB20_Msk
     
    #define CAN_F8R2_FB21_Pos   (21U)
     
    #define CAN_F8R2_FB21_Msk   (0x1UL << CAN_F8R2_FB21_Pos)
     
    #define CAN_F8R2_FB21   CAN_F8R2_FB21_Msk
     
    #define CAN_F8R2_FB22_Pos   (22U)
     
    #define CAN_F8R2_FB22_Msk   (0x1UL << CAN_F8R2_FB22_Pos)
     
    #define CAN_F8R2_FB22   CAN_F8R2_FB22_Msk
     
    #define CAN_F8R2_FB23_Pos   (23U)
     
    #define CAN_F8R2_FB23_Msk   (0x1UL << CAN_F8R2_FB23_Pos)
     
    #define CAN_F8R2_FB23   CAN_F8R2_FB23_Msk
     
    #define CAN_F8R2_FB24_Pos   (24U)
     
    #define CAN_F8R2_FB24_Msk   (0x1UL << CAN_F8R2_FB24_Pos)
     
    #define CAN_F8R2_FB24   CAN_F8R2_FB24_Msk
     
    #define CAN_F8R2_FB25_Pos   (25U)
     
    #define CAN_F8R2_FB25_Msk   (0x1UL << CAN_F8R2_FB25_Pos)
     
    #define CAN_F8R2_FB25   CAN_F8R2_FB25_Msk
     
    #define CAN_F8R2_FB26_Pos   (26U)
     
    #define CAN_F8R2_FB26_Msk   (0x1UL << CAN_F8R2_FB26_Pos)
     
    #define CAN_F8R2_FB26   CAN_F8R2_FB26_Msk
     
    #define CAN_F8R2_FB27_Pos   (27U)
     
    #define CAN_F8R2_FB27_Msk   (0x1UL << CAN_F8R2_FB27_Pos)
     
    #define CAN_F8R2_FB27   CAN_F8R2_FB27_Msk
     
    #define CAN_F8R2_FB28_Pos   (28U)
     
    #define CAN_F8R2_FB28_Msk   (0x1UL << CAN_F8R2_FB28_Pos)
     
    #define CAN_F8R2_FB28   CAN_F8R2_FB28_Msk
     
    #define CAN_F8R2_FB29_Pos   (29U)
     
    #define CAN_F8R2_FB29_Msk   (0x1UL << CAN_F8R2_FB29_Pos)
     
    #define CAN_F8R2_FB29   CAN_F8R2_FB29_Msk
     
    #define CAN_F8R2_FB30_Pos   (30U)
     
    #define CAN_F8R2_FB30_Msk   (0x1UL << CAN_F8R2_FB30_Pos)
     
    #define CAN_F8R2_FB30   CAN_F8R2_FB30_Msk
     
    #define CAN_F8R2_FB31_Pos   (31U)
     
    #define CAN_F8R2_FB31_Msk   (0x1UL << CAN_F8R2_FB31_Pos)
     
    #define CAN_F8R2_FB31   CAN_F8R2_FB31_Msk
     
    #define CAN_F9R2_FB0_Pos   (0U)
     
    #define CAN_F9R2_FB0_Msk   (0x1UL << CAN_F9R2_FB0_Pos)
     
    #define CAN_F9R2_FB0   CAN_F9R2_FB0_Msk
     
    #define CAN_F9R2_FB1_Pos   (1U)
     
    #define CAN_F9R2_FB1_Msk   (0x1UL << CAN_F9R2_FB1_Pos)
     
    #define CAN_F9R2_FB1   CAN_F9R2_FB1_Msk
     
    #define CAN_F9R2_FB2_Pos   (2U)
     
    #define CAN_F9R2_FB2_Msk   (0x1UL << CAN_F9R2_FB2_Pos)
     
    #define CAN_F9R2_FB2   CAN_F9R2_FB2_Msk
     
    #define CAN_F9R2_FB3_Pos   (3U)
     
    #define CAN_F9R2_FB3_Msk   (0x1UL << CAN_F9R2_FB3_Pos)
     
    #define CAN_F9R2_FB3   CAN_F9R2_FB3_Msk
     
    #define CAN_F9R2_FB4_Pos   (4U)
     
    #define CAN_F9R2_FB4_Msk   (0x1UL << CAN_F9R2_FB4_Pos)
     
    #define CAN_F9R2_FB4   CAN_F9R2_FB4_Msk
     
    #define CAN_F9R2_FB5_Pos   (5U)
     
    #define CAN_F9R2_FB5_Msk   (0x1UL << CAN_F9R2_FB5_Pos)
     
    #define CAN_F9R2_FB5   CAN_F9R2_FB5_Msk
     
    #define CAN_F9R2_FB6_Pos   (6U)
     
    #define CAN_F9R2_FB6_Msk   (0x1UL << CAN_F9R2_FB6_Pos)
     
    #define CAN_F9R2_FB6   CAN_F9R2_FB6_Msk
     
    #define CAN_F9R2_FB7_Pos   (7U)
     
    #define CAN_F9R2_FB7_Msk   (0x1UL << CAN_F9R2_FB7_Pos)
     
    #define CAN_F9R2_FB7   CAN_F9R2_FB7_Msk
     
    #define CAN_F9R2_FB8_Pos   (8U)
     
    #define CAN_F9R2_FB8_Msk   (0x1UL << CAN_F9R2_FB8_Pos)
     
    #define CAN_F9R2_FB8   CAN_F9R2_FB8_Msk
     
    #define CAN_F9R2_FB9_Pos   (9U)
     
    #define CAN_F9R2_FB9_Msk   (0x1UL << CAN_F9R2_FB9_Pos)
     
    #define CAN_F9R2_FB9   CAN_F9R2_FB9_Msk
     
    #define CAN_F9R2_FB10_Pos   (10U)
     
    #define CAN_F9R2_FB10_Msk   (0x1UL << CAN_F9R2_FB10_Pos)
     
    #define CAN_F9R2_FB10   CAN_F9R2_FB10_Msk
     
    #define CAN_F9R2_FB11_Pos   (11U)
     
    #define CAN_F9R2_FB11_Msk   (0x1UL << CAN_F9R2_FB11_Pos)
     
    #define CAN_F9R2_FB11   CAN_F9R2_FB11_Msk
     
    #define CAN_F9R2_FB12_Pos   (12U)
     
    #define CAN_F9R2_FB12_Msk   (0x1UL << CAN_F9R2_FB12_Pos)
     
    #define CAN_F9R2_FB12   CAN_F9R2_FB12_Msk
     
    #define CAN_F9R2_FB13_Pos   (13U)
     
    #define CAN_F9R2_FB13_Msk   (0x1UL << CAN_F9R2_FB13_Pos)
     
    #define CAN_F9R2_FB13   CAN_F9R2_FB13_Msk
     
    #define CAN_F9R2_FB14_Pos   (14U)
     
    #define CAN_F9R2_FB14_Msk   (0x1UL << CAN_F9R2_FB14_Pos)
     
    #define CAN_F9R2_FB14   CAN_F9R2_FB14_Msk
     
    #define CAN_F9R2_FB15_Pos   (15U)
     
    #define CAN_F9R2_FB15_Msk   (0x1UL << CAN_F9R2_FB15_Pos)
     
    #define CAN_F9R2_FB15   CAN_F9R2_FB15_Msk
     
    #define CAN_F9R2_FB16_Pos   (16U)
     
    #define CAN_F9R2_FB16_Msk   (0x1UL << CAN_F9R2_FB16_Pos)
     
    #define CAN_F9R2_FB16   CAN_F9R2_FB16_Msk
     
    #define CAN_F9R2_FB17_Pos   (17U)
     
    #define CAN_F9R2_FB17_Msk   (0x1UL << CAN_F9R2_FB17_Pos)
     
    #define CAN_F9R2_FB17   CAN_F9R2_FB17_Msk
     
    #define CAN_F9R2_FB18_Pos   (18U)
     
    #define CAN_F9R2_FB18_Msk   (0x1UL << CAN_F9R2_FB18_Pos)
     
    #define CAN_F9R2_FB18   CAN_F9R2_FB18_Msk
     
    #define CAN_F9R2_FB19_Pos   (19U)
     
    #define CAN_F9R2_FB19_Msk   (0x1UL << CAN_F9R2_FB19_Pos)
     
    #define CAN_F9R2_FB19   CAN_F9R2_FB19_Msk
     
    #define CAN_F9R2_FB20_Pos   (20U)
     
    #define CAN_F9R2_FB20_Msk   (0x1UL << CAN_F9R2_FB20_Pos)
     
    #define CAN_F9R2_FB20   CAN_F9R2_FB20_Msk
     
    #define CAN_F9R2_FB21_Pos   (21U)
     
    #define CAN_F9R2_FB21_Msk   (0x1UL << CAN_F9R2_FB21_Pos)
     
    #define CAN_F9R2_FB21   CAN_F9R2_FB21_Msk
     
    #define CAN_F9R2_FB22_Pos   (22U)
     
    #define CAN_F9R2_FB22_Msk   (0x1UL << CAN_F9R2_FB22_Pos)
     
    #define CAN_F9R2_FB22   CAN_F9R2_FB22_Msk
     
    #define CAN_F9R2_FB23_Pos   (23U)
     
    #define CAN_F9R2_FB23_Msk   (0x1UL << CAN_F9R2_FB23_Pos)
     
    #define CAN_F9R2_FB23   CAN_F9R2_FB23_Msk
     
    #define CAN_F9R2_FB24_Pos   (24U)
     
    #define CAN_F9R2_FB24_Msk   (0x1UL << CAN_F9R2_FB24_Pos)
     
    #define CAN_F9R2_FB24   CAN_F9R2_FB24_Msk
     
    #define CAN_F9R2_FB25_Pos   (25U)
     
    #define CAN_F9R2_FB25_Msk   (0x1UL << CAN_F9R2_FB25_Pos)
     
    #define CAN_F9R2_FB25   CAN_F9R2_FB25_Msk
     
    #define CAN_F9R2_FB26_Pos   (26U)
     
    #define CAN_F9R2_FB26_Msk   (0x1UL << CAN_F9R2_FB26_Pos)
     
    #define CAN_F9R2_FB26   CAN_F9R2_FB26_Msk
     
    #define CAN_F9R2_FB27_Pos   (27U)
     
    #define CAN_F9R2_FB27_Msk   (0x1UL << CAN_F9R2_FB27_Pos)
     
    #define CAN_F9R2_FB27   CAN_F9R2_FB27_Msk
     
    #define CAN_F9R2_FB28_Pos   (28U)
     
    #define CAN_F9R2_FB28_Msk   (0x1UL << CAN_F9R2_FB28_Pos)
     
    #define CAN_F9R2_FB28   CAN_F9R2_FB28_Msk
     
    #define CAN_F9R2_FB29_Pos   (29U)
     
    #define CAN_F9R2_FB29_Msk   (0x1UL << CAN_F9R2_FB29_Pos)
     
    #define CAN_F9R2_FB29   CAN_F9R2_FB29_Msk
     
    #define CAN_F9R2_FB30_Pos   (30U)
     
    #define CAN_F9R2_FB30_Msk   (0x1UL << CAN_F9R2_FB30_Pos)
     
    #define CAN_F9R2_FB30   CAN_F9R2_FB30_Msk
     
    #define CAN_F9R2_FB31_Pos   (31U)
     
    #define CAN_F9R2_FB31_Msk   (0x1UL << CAN_F9R2_FB31_Pos)
     
    #define CAN_F9R2_FB31   CAN_F9R2_FB31_Msk
     
    #define CAN_F10R2_FB0_Pos   (0U)
     
    #define CAN_F10R2_FB0_Msk   (0x1UL << CAN_F10R2_FB0_Pos)
     
    #define CAN_F10R2_FB0   CAN_F10R2_FB0_Msk
     
    #define CAN_F10R2_FB1_Pos   (1U)
     
    #define CAN_F10R2_FB1_Msk   (0x1UL << CAN_F10R2_FB1_Pos)
     
    #define CAN_F10R2_FB1   CAN_F10R2_FB1_Msk
     
    #define CAN_F10R2_FB2_Pos   (2U)
     
    #define CAN_F10R2_FB2_Msk   (0x1UL << CAN_F10R2_FB2_Pos)
     
    #define CAN_F10R2_FB2   CAN_F10R2_FB2_Msk
     
    #define CAN_F10R2_FB3_Pos   (3U)
     
    #define CAN_F10R2_FB3_Msk   (0x1UL << CAN_F10R2_FB3_Pos)
     
    #define CAN_F10R2_FB3   CAN_F10R2_FB3_Msk
     
    #define CAN_F10R2_FB4_Pos   (4U)
     
    #define CAN_F10R2_FB4_Msk   (0x1UL << CAN_F10R2_FB4_Pos)
     
    #define CAN_F10R2_FB4   CAN_F10R2_FB4_Msk
     
    #define CAN_F10R2_FB5_Pos   (5U)
     
    #define CAN_F10R2_FB5_Msk   (0x1UL << CAN_F10R2_FB5_Pos)
     
    #define CAN_F10R2_FB5   CAN_F10R2_FB5_Msk
     
    #define CAN_F10R2_FB6_Pos   (6U)
     
    #define CAN_F10R2_FB6_Msk   (0x1UL << CAN_F10R2_FB6_Pos)
     
    #define CAN_F10R2_FB6   CAN_F10R2_FB6_Msk
     
    #define CAN_F10R2_FB7_Pos   (7U)
     
    #define CAN_F10R2_FB7_Msk   (0x1UL << CAN_F10R2_FB7_Pos)
     
    #define CAN_F10R2_FB7   CAN_F10R2_FB7_Msk
     
    #define CAN_F10R2_FB8_Pos   (8U)
     
    #define CAN_F10R2_FB8_Msk   (0x1UL << CAN_F10R2_FB8_Pos)
     
    #define CAN_F10R2_FB8   CAN_F10R2_FB8_Msk
     
    #define CAN_F10R2_FB9_Pos   (9U)
     
    #define CAN_F10R2_FB9_Msk   (0x1UL << CAN_F10R2_FB9_Pos)
     
    #define CAN_F10R2_FB9   CAN_F10R2_FB9_Msk
     
    #define CAN_F10R2_FB10_Pos   (10U)
     
    #define CAN_F10R2_FB10_Msk   (0x1UL << CAN_F10R2_FB10_Pos)
     
    #define CAN_F10R2_FB10   CAN_F10R2_FB10_Msk
     
    #define CAN_F10R2_FB11_Pos   (11U)
     
    #define CAN_F10R2_FB11_Msk   (0x1UL << CAN_F10R2_FB11_Pos)
     
    #define CAN_F10R2_FB11   CAN_F10R2_FB11_Msk
     
    #define CAN_F10R2_FB12_Pos   (12U)
     
    #define CAN_F10R2_FB12_Msk   (0x1UL << CAN_F10R2_FB12_Pos)
     
    #define CAN_F10R2_FB12   CAN_F10R2_FB12_Msk
     
    #define CAN_F10R2_FB13_Pos   (13U)
     
    #define CAN_F10R2_FB13_Msk   (0x1UL << CAN_F10R2_FB13_Pos)
     
    #define CAN_F10R2_FB13   CAN_F10R2_FB13_Msk
     
    #define CAN_F10R2_FB14_Pos   (14U)
     
    #define CAN_F10R2_FB14_Msk   (0x1UL << CAN_F10R2_FB14_Pos)
     
    #define CAN_F10R2_FB14   CAN_F10R2_FB14_Msk
     
    #define CAN_F10R2_FB15_Pos   (15U)
     
    #define CAN_F10R2_FB15_Msk   (0x1UL << CAN_F10R2_FB15_Pos)
     
    #define CAN_F10R2_FB15   CAN_F10R2_FB15_Msk
     
    #define CAN_F10R2_FB16_Pos   (16U)
     
    #define CAN_F10R2_FB16_Msk   (0x1UL << CAN_F10R2_FB16_Pos)
     
    #define CAN_F10R2_FB16   CAN_F10R2_FB16_Msk
     
    #define CAN_F10R2_FB17_Pos   (17U)
     
    #define CAN_F10R2_FB17_Msk   (0x1UL << CAN_F10R2_FB17_Pos)
     
    #define CAN_F10R2_FB17   CAN_F10R2_FB17_Msk
     
    #define CAN_F10R2_FB18_Pos   (18U)
     
    #define CAN_F10R2_FB18_Msk   (0x1UL << CAN_F10R2_FB18_Pos)
     
    #define CAN_F10R2_FB18   CAN_F10R2_FB18_Msk
     
    #define CAN_F10R2_FB19_Pos   (19U)
     
    #define CAN_F10R2_FB19_Msk   (0x1UL << CAN_F10R2_FB19_Pos)
     
    #define CAN_F10R2_FB19   CAN_F10R2_FB19_Msk
     
    #define CAN_F10R2_FB20_Pos   (20U)
     
    #define CAN_F10R2_FB20_Msk   (0x1UL << CAN_F10R2_FB20_Pos)
     
    #define CAN_F10R2_FB20   CAN_F10R2_FB20_Msk
     
    #define CAN_F10R2_FB21_Pos   (21U)
     
    #define CAN_F10R2_FB21_Msk   (0x1UL << CAN_F10R2_FB21_Pos)
     
    #define CAN_F10R2_FB21   CAN_F10R2_FB21_Msk
     
    #define CAN_F10R2_FB22_Pos   (22U)
     
    #define CAN_F10R2_FB22_Msk   (0x1UL << CAN_F10R2_FB22_Pos)
     
    #define CAN_F10R2_FB22   CAN_F10R2_FB22_Msk
     
    #define CAN_F10R2_FB23_Pos   (23U)
     
    #define CAN_F10R2_FB23_Msk   (0x1UL << CAN_F10R2_FB23_Pos)
     
    #define CAN_F10R2_FB23   CAN_F10R2_FB23_Msk
     
    #define CAN_F10R2_FB24_Pos   (24U)
     
    #define CAN_F10R2_FB24_Msk   (0x1UL << CAN_F10R2_FB24_Pos)
     
    #define CAN_F10R2_FB24   CAN_F10R2_FB24_Msk
     
    #define CAN_F10R2_FB25_Pos   (25U)
     
    #define CAN_F10R2_FB25_Msk   (0x1UL << CAN_F10R2_FB25_Pos)
     
    #define CAN_F10R2_FB25   CAN_F10R2_FB25_Msk
     
    #define CAN_F10R2_FB26_Pos   (26U)
     
    #define CAN_F10R2_FB26_Msk   (0x1UL << CAN_F10R2_FB26_Pos)
     
    #define CAN_F10R2_FB26   CAN_F10R2_FB26_Msk
     
    #define CAN_F10R2_FB27_Pos   (27U)
     
    #define CAN_F10R2_FB27_Msk   (0x1UL << CAN_F10R2_FB27_Pos)
     
    #define CAN_F10R2_FB27   CAN_F10R2_FB27_Msk
     
    #define CAN_F10R2_FB28_Pos   (28U)
     
    #define CAN_F10R2_FB28_Msk   (0x1UL << CAN_F10R2_FB28_Pos)
     
    #define CAN_F10R2_FB28   CAN_F10R2_FB28_Msk
     
    #define CAN_F10R2_FB29_Pos   (29U)
     
    #define CAN_F10R2_FB29_Msk   (0x1UL << CAN_F10R2_FB29_Pos)
     
    #define CAN_F10R2_FB29   CAN_F10R2_FB29_Msk
     
    #define CAN_F10R2_FB30_Pos   (30U)
     
    #define CAN_F10R2_FB30_Msk   (0x1UL << CAN_F10R2_FB30_Pos)
     
    #define CAN_F10R2_FB30   CAN_F10R2_FB30_Msk
     
    #define CAN_F10R2_FB31_Pos   (31U)
     
    #define CAN_F10R2_FB31_Msk   (0x1UL << CAN_F10R2_FB31_Pos)
     
    #define CAN_F10R2_FB31   CAN_F10R2_FB31_Msk
     
    #define CAN_F11R2_FB0_Pos   (0U)
     
    #define CAN_F11R2_FB0_Msk   (0x1UL << CAN_F11R2_FB0_Pos)
     
    #define CAN_F11R2_FB0   CAN_F11R2_FB0_Msk
     
    #define CAN_F11R2_FB1_Pos   (1U)
     
    #define CAN_F11R2_FB1_Msk   (0x1UL << CAN_F11R2_FB1_Pos)
     
    #define CAN_F11R2_FB1   CAN_F11R2_FB1_Msk
     
    #define CAN_F11R2_FB2_Pos   (2U)
     
    #define CAN_F11R2_FB2_Msk   (0x1UL << CAN_F11R2_FB2_Pos)
     
    #define CAN_F11R2_FB2   CAN_F11R2_FB2_Msk
     
    #define CAN_F11R2_FB3_Pos   (3U)
     
    #define CAN_F11R2_FB3_Msk   (0x1UL << CAN_F11R2_FB3_Pos)
     
    #define CAN_F11R2_FB3   CAN_F11R2_FB3_Msk
     
    #define CAN_F11R2_FB4_Pos   (4U)
     
    #define CAN_F11R2_FB4_Msk   (0x1UL << CAN_F11R2_FB4_Pos)
     
    #define CAN_F11R2_FB4   CAN_F11R2_FB4_Msk
     
    #define CAN_F11R2_FB5_Pos   (5U)
     
    #define CAN_F11R2_FB5_Msk   (0x1UL << CAN_F11R2_FB5_Pos)
     
    #define CAN_F11R2_FB5   CAN_F11R2_FB5_Msk
     
    #define CAN_F11R2_FB6_Pos   (6U)
     
    #define CAN_F11R2_FB6_Msk   (0x1UL << CAN_F11R2_FB6_Pos)
     
    #define CAN_F11R2_FB6   CAN_F11R2_FB6_Msk
     
    #define CAN_F11R2_FB7_Pos   (7U)
     
    #define CAN_F11R2_FB7_Msk   (0x1UL << CAN_F11R2_FB7_Pos)
     
    #define CAN_F11R2_FB7   CAN_F11R2_FB7_Msk
     
    #define CAN_F11R2_FB8_Pos   (8U)
     
    #define CAN_F11R2_FB8_Msk   (0x1UL << CAN_F11R2_FB8_Pos)
     
    #define CAN_F11R2_FB8   CAN_F11R2_FB8_Msk
     
    #define CAN_F11R2_FB9_Pos   (9U)
     
    #define CAN_F11R2_FB9_Msk   (0x1UL << CAN_F11R2_FB9_Pos)
     
    #define CAN_F11R2_FB9   CAN_F11R2_FB9_Msk
     
    #define CAN_F11R2_FB10_Pos   (10U)
     
    #define CAN_F11R2_FB10_Msk   (0x1UL << CAN_F11R2_FB10_Pos)
     
    #define CAN_F11R2_FB10   CAN_F11R2_FB10_Msk
     
    #define CAN_F11R2_FB11_Pos   (11U)
     
    #define CAN_F11R2_FB11_Msk   (0x1UL << CAN_F11R2_FB11_Pos)
     
    #define CAN_F11R2_FB11   CAN_F11R2_FB11_Msk
     
    #define CAN_F11R2_FB12_Pos   (12U)
     
    #define CAN_F11R2_FB12_Msk   (0x1UL << CAN_F11R2_FB12_Pos)
     
    #define CAN_F11R2_FB12   CAN_F11R2_FB12_Msk
     
    #define CAN_F11R2_FB13_Pos   (13U)
     
    #define CAN_F11R2_FB13_Msk   (0x1UL << CAN_F11R2_FB13_Pos)
     
    #define CAN_F11R2_FB13   CAN_F11R2_FB13_Msk
     
    #define CAN_F11R2_FB14_Pos   (14U)
     
    #define CAN_F11R2_FB14_Msk   (0x1UL << CAN_F11R2_FB14_Pos)
     
    #define CAN_F11R2_FB14   CAN_F11R2_FB14_Msk
     
    #define CAN_F11R2_FB15_Pos   (15U)
     
    #define CAN_F11R2_FB15_Msk   (0x1UL << CAN_F11R2_FB15_Pos)
     
    #define CAN_F11R2_FB15   CAN_F11R2_FB15_Msk
     
    #define CAN_F11R2_FB16_Pos   (16U)
     
    #define CAN_F11R2_FB16_Msk   (0x1UL << CAN_F11R2_FB16_Pos)
     
    #define CAN_F11R2_FB16   CAN_F11R2_FB16_Msk
     
    #define CAN_F11R2_FB17_Pos   (17U)
     
    #define CAN_F11R2_FB17_Msk   (0x1UL << CAN_F11R2_FB17_Pos)
     
    #define CAN_F11R2_FB17   CAN_F11R2_FB17_Msk
     
    #define CAN_F11R2_FB18_Pos   (18U)
     
    #define CAN_F11R2_FB18_Msk   (0x1UL << CAN_F11R2_FB18_Pos)
     
    #define CAN_F11R2_FB18   CAN_F11R2_FB18_Msk
     
    #define CAN_F11R2_FB19_Pos   (19U)
     
    #define CAN_F11R2_FB19_Msk   (0x1UL << CAN_F11R2_FB19_Pos)
     
    #define CAN_F11R2_FB19   CAN_F11R2_FB19_Msk
     
    #define CAN_F11R2_FB20_Pos   (20U)
     
    #define CAN_F11R2_FB20_Msk   (0x1UL << CAN_F11R2_FB20_Pos)
     
    #define CAN_F11R2_FB20   CAN_F11R2_FB20_Msk
     
    #define CAN_F11R2_FB21_Pos   (21U)
     
    #define CAN_F11R2_FB21_Msk   (0x1UL << CAN_F11R2_FB21_Pos)
     
    #define CAN_F11R2_FB21   CAN_F11R2_FB21_Msk
     
    #define CAN_F11R2_FB22_Pos   (22U)
     
    #define CAN_F11R2_FB22_Msk   (0x1UL << CAN_F11R2_FB22_Pos)
     
    #define CAN_F11R2_FB22   CAN_F11R2_FB22_Msk
     
    #define CAN_F11R2_FB23_Pos   (23U)
     
    #define CAN_F11R2_FB23_Msk   (0x1UL << CAN_F11R2_FB23_Pos)
     
    #define CAN_F11R2_FB23   CAN_F11R2_FB23_Msk
     
    #define CAN_F11R2_FB24_Pos   (24U)
     
    #define CAN_F11R2_FB24_Msk   (0x1UL << CAN_F11R2_FB24_Pos)
     
    #define CAN_F11R2_FB24   CAN_F11R2_FB24_Msk
     
    #define CAN_F11R2_FB25_Pos   (25U)
     
    #define CAN_F11R2_FB25_Msk   (0x1UL << CAN_F11R2_FB25_Pos)
     
    #define CAN_F11R2_FB25   CAN_F11R2_FB25_Msk
     
    #define CAN_F11R2_FB26_Pos   (26U)
     
    #define CAN_F11R2_FB26_Msk   (0x1UL << CAN_F11R2_FB26_Pos)
     
    #define CAN_F11R2_FB26   CAN_F11R2_FB26_Msk
     
    #define CAN_F11R2_FB27_Pos   (27U)
     
    #define CAN_F11R2_FB27_Msk   (0x1UL << CAN_F11R2_FB27_Pos)
     
    #define CAN_F11R2_FB27   CAN_F11R2_FB27_Msk
     
    #define CAN_F11R2_FB28_Pos   (28U)
     
    #define CAN_F11R2_FB28_Msk   (0x1UL << CAN_F11R2_FB28_Pos)
     
    #define CAN_F11R2_FB28   CAN_F11R2_FB28_Msk
     
    #define CAN_F11R2_FB29_Pos   (29U)
     
    #define CAN_F11R2_FB29_Msk   (0x1UL << CAN_F11R2_FB29_Pos)
     
    #define CAN_F11R2_FB29   CAN_F11R2_FB29_Msk
     
    #define CAN_F11R2_FB30_Pos   (30U)
     
    #define CAN_F11R2_FB30_Msk   (0x1UL << CAN_F11R2_FB30_Pos)
     
    #define CAN_F11R2_FB30   CAN_F11R2_FB30_Msk
     
    #define CAN_F11R2_FB31_Pos   (31U)
     
    #define CAN_F11R2_FB31_Msk   (0x1UL << CAN_F11R2_FB31_Pos)
     
    #define CAN_F11R2_FB31   CAN_F11R2_FB31_Msk
     
    #define CAN_F12R2_FB0_Pos   (0U)
     
    #define CAN_F12R2_FB0_Msk   (0x1UL << CAN_F12R2_FB0_Pos)
     
    #define CAN_F12R2_FB0   CAN_F12R2_FB0_Msk
     
    #define CAN_F12R2_FB1_Pos   (1U)
     
    #define CAN_F12R2_FB1_Msk   (0x1UL << CAN_F12R2_FB1_Pos)
     
    #define CAN_F12R2_FB1   CAN_F12R2_FB1_Msk
     
    #define CAN_F12R2_FB2_Pos   (2U)
     
    #define CAN_F12R2_FB2_Msk   (0x1UL << CAN_F12R2_FB2_Pos)
     
    #define CAN_F12R2_FB2   CAN_F12R2_FB2_Msk
     
    #define CAN_F12R2_FB3_Pos   (3U)
     
    #define CAN_F12R2_FB3_Msk   (0x1UL << CAN_F12R2_FB3_Pos)
     
    #define CAN_F12R2_FB3   CAN_F12R2_FB3_Msk
     
    #define CAN_F12R2_FB4_Pos   (4U)
     
    #define CAN_F12R2_FB4_Msk   (0x1UL << CAN_F12R2_FB4_Pos)
     
    #define CAN_F12R2_FB4   CAN_F12R2_FB4_Msk
     
    #define CAN_F12R2_FB5_Pos   (5U)
     
    #define CAN_F12R2_FB5_Msk   (0x1UL << CAN_F12R2_FB5_Pos)
     
    #define CAN_F12R2_FB5   CAN_F12R2_FB5_Msk
     
    #define CAN_F12R2_FB6_Pos   (6U)
     
    #define CAN_F12R2_FB6_Msk   (0x1UL << CAN_F12R2_FB6_Pos)
     
    #define CAN_F12R2_FB6   CAN_F12R2_FB6_Msk
     
    #define CAN_F12R2_FB7_Pos   (7U)
     
    #define CAN_F12R2_FB7_Msk   (0x1UL << CAN_F12R2_FB7_Pos)
     
    #define CAN_F12R2_FB7   CAN_F12R2_FB7_Msk
     
    #define CAN_F12R2_FB8_Pos   (8U)
     
    #define CAN_F12R2_FB8_Msk   (0x1UL << CAN_F12R2_FB8_Pos)
     
    #define CAN_F12R2_FB8   CAN_F12R2_FB8_Msk
     
    #define CAN_F12R2_FB9_Pos   (9U)
     
    #define CAN_F12R2_FB9_Msk   (0x1UL << CAN_F12R2_FB9_Pos)
     
    #define CAN_F12R2_FB9   CAN_F12R2_FB9_Msk
     
    #define CAN_F12R2_FB10_Pos   (10U)
     
    #define CAN_F12R2_FB10_Msk   (0x1UL << CAN_F12R2_FB10_Pos)
     
    #define CAN_F12R2_FB10   CAN_F12R2_FB10_Msk
     
    #define CAN_F12R2_FB11_Pos   (11U)
     
    #define CAN_F12R2_FB11_Msk   (0x1UL << CAN_F12R2_FB11_Pos)
     
    #define CAN_F12R2_FB11   CAN_F12R2_FB11_Msk
     
    #define CAN_F12R2_FB12_Pos   (12U)
     
    #define CAN_F12R2_FB12_Msk   (0x1UL << CAN_F12R2_FB12_Pos)
     
    #define CAN_F12R2_FB12   CAN_F12R2_FB12_Msk
     
    #define CAN_F12R2_FB13_Pos   (13U)
     
    #define CAN_F12R2_FB13_Msk   (0x1UL << CAN_F12R2_FB13_Pos)
     
    #define CAN_F12R2_FB13   CAN_F12R2_FB13_Msk
     
    #define CAN_F12R2_FB14_Pos   (14U)
     
    #define CAN_F12R2_FB14_Msk   (0x1UL << CAN_F12R2_FB14_Pos)
     
    #define CAN_F12R2_FB14   CAN_F12R2_FB14_Msk
     
    #define CAN_F12R2_FB15_Pos   (15U)
     
    #define CAN_F12R2_FB15_Msk   (0x1UL << CAN_F12R2_FB15_Pos)
     
    #define CAN_F12R2_FB15   CAN_F12R2_FB15_Msk
     
    #define CAN_F12R2_FB16_Pos   (16U)
     
    #define CAN_F12R2_FB16_Msk   (0x1UL << CAN_F12R2_FB16_Pos)
     
    #define CAN_F12R2_FB16   CAN_F12R2_FB16_Msk
     
    #define CAN_F12R2_FB17_Pos   (17U)
     
    #define CAN_F12R2_FB17_Msk   (0x1UL << CAN_F12R2_FB17_Pos)
     
    #define CAN_F12R2_FB17   CAN_F12R2_FB17_Msk
     
    #define CAN_F12R2_FB18_Pos   (18U)
     
    #define CAN_F12R2_FB18_Msk   (0x1UL << CAN_F12R2_FB18_Pos)
     
    #define CAN_F12R2_FB18   CAN_F12R2_FB18_Msk
     
    #define CAN_F12R2_FB19_Pos   (19U)
     
    #define CAN_F12R2_FB19_Msk   (0x1UL << CAN_F12R2_FB19_Pos)
     
    #define CAN_F12R2_FB19   CAN_F12R2_FB19_Msk
     
    #define CAN_F12R2_FB20_Pos   (20U)
     
    #define CAN_F12R2_FB20_Msk   (0x1UL << CAN_F12R2_FB20_Pos)
     
    #define CAN_F12R2_FB20   CAN_F12R2_FB20_Msk
     
    #define CAN_F12R2_FB21_Pos   (21U)
     
    #define CAN_F12R2_FB21_Msk   (0x1UL << CAN_F12R2_FB21_Pos)
     
    #define CAN_F12R2_FB21   CAN_F12R2_FB21_Msk
     
    #define CAN_F12R2_FB22_Pos   (22U)
     
    #define CAN_F12R2_FB22_Msk   (0x1UL << CAN_F12R2_FB22_Pos)
     
    #define CAN_F12R2_FB22   CAN_F12R2_FB22_Msk
     
    #define CAN_F12R2_FB23_Pos   (23U)
     
    #define CAN_F12R2_FB23_Msk   (0x1UL << CAN_F12R2_FB23_Pos)
     
    #define CAN_F12R2_FB23   CAN_F12R2_FB23_Msk
     
    #define CAN_F12R2_FB24_Pos   (24U)
     
    #define CAN_F12R2_FB24_Msk   (0x1UL << CAN_F12R2_FB24_Pos)
     
    #define CAN_F12R2_FB24   CAN_F12R2_FB24_Msk
     
    #define CAN_F12R2_FB25_Pos   (25U)
     
    #define CAN_F12R2_FB25_Msk   (0x1UL << CAN_F12R2_FB25_Pos)
     
    #define CAN_F12R2_FB25   CAN_F12R2_FB25_Msk
     
    #define CAN_F12R2_FB26_Pos   (26U)
     
    #define CAN_F12R2_FB26_Msk   (0x1UL << CAN_F12R2_FB26_Pos)
     
    #define CAN_F12R2_FB26   CAN_F12R2_FB26_Msk
     
    #define CAN_F12R2_FB27_Pos   (27U)
     
    #define CAN_F12R2_FB27_Msk   (0x1UL << CAN_F12R2_FB27_Pos)
     
    #define CAN_F12R2_FB27   CAN_F12R2_FB27_Msk
     
    #define CAN_F12R2_FB28_Pos   (28U)
     
    #define CAN_F12R2_FB28_Msk   (0x1UL << CAN_F12R2_FB28_Pos)
     
    #define CAN_F12R2_FB28   CAN_F12R2_FB28_Msk
     
    #define CAN_F12R2_FB29_Pos   (29U)
     
    #define CAN_F12R2_FB29_Msk   (0x1UL << CAN_F12R2_FB29_Pos)
     
    #define CAN_F12R2_FB29   CAN_F12R2_FB29_Msk
     
    #define CAN_F12R2_FB30_Pos   (30U)
     
    #define CAN_F12R2_FB30_Msk   (0x1UL << CAN_F12R2_FB30_Pos)
     
    #define CAN_F12R2_FB30   CAN_F12R2_FB30_Msk
     
    #define CAN_F12R2_FB31_Pos   (31U)
     
    #define CAN_F12R2_FB31_Msk   (0x1UL << CAN_F12R2_FB31_Pos)
     
    #define CAN_F12R2_FB31   CAN_F12R2_FB31_Msk
     
    #define CAN_F13R2_FB0_Pos   (0U)
     
    #define CAN_F13R2_FB0_Msk   (0x1UL << CAN_F13R2_FB0_Pos)
     
    #define CAN_F13R2_FB0   CAN_F13R2_FB0_Msk
     
    #define CAN_F13R2_FB1_Pos   (1U)
     
    #define CAN_F13R2_FB1_Msk   (0x1UL << CAN_F13R2_FB1_Pos)
     
    #define CAN_F13R2_FB1   CAN_F13R2_FB1_Msk
     
    #define CAN_F13R2_FB2_Pos   (2U)
     
    #define CAN_F13R2_FB2_Msk   (0x1UL << CAN_F13R2_FB2_Pos)
     
    #define CAN_F13R2_FB2   CAN_F13R2_FB2_Msk
     
    #define CAN_F13R2_FB3_Pos   (3U)
     
    #define CAN_F13R2_FB3_Msk   (0x1UL << CAN_F13R2_FB3_Pos)
     
    #define CAN_F13R2_FB3   CAN_F13R2_FB3_Msk
     
    #define CAN_F13R2_FB4_Pos   (4U)
     
    #define CAN_F13R2_FB4_Msk   (0x1UL << CAN_F13R2_FB4_Pos)
     
    #define CAN_F13R2_FB4   CAN_F13R2_FB4_Msk
     
    #define CAN_F13R2_FB5_Pos   (5U)
     
    #define CAN_F13R2_FB5_Msk   (0x1UL << CAN_F13R2_FB5_Pos)
     
    #define CAN_F13R2_FB5   CAN_F13R2_FB5_Msk
     
    #define CAN_F13R2_FB6_Pos   (6U)
     
    #define CAN_F13R2_FB6_Msk   (0x1UL << CAN_F13R2_FB6_Pos)
     
    #define CAN_F13R2_FB6   CAN_F13R2_FB6_Msk
     
    #define CAN_F13R2_FB7_Pos   (7U)
     
    #define CAN_F13R2_FB7_Msk   (0x1UL << CAN_F13R2_FB7_Pos)
     
    #define CAN_F13R2_FB7   CAN_F13R2_FB7_Msk
     
    #define CAN_F13R2_FB8_Pos   (8U)
     
    #define CAN_F13R2_FB8_Msk   (0x1UL << CAN_F13R2_FB8_Pos)
     
    #define CAN_F13R2_FB8   CAN_F13R2_FB8_Msk
     
    #define CAN_F13R2_FB9_Pos   (9U)
     
    #define CAN_F13R2_FB9_Msk   (0x1UL << CAN_F13R2_FB9_Pos)
     
    #define CAN_F13R2_FB9   CAN_F13R2_FB9_Msk
     
    #define CAN_F13R2_FB10_Pos   (10U)
     
    #define CAN_F13R2_FB10_Msk   (0x1UL << CAN_F13R2_FB10_Pos)
     
    #define CAN_F13R2_FB10   CAN_F13R2_FB10_Msk
     
    #define CAN_F13R2_FB11_Pos   (11U)
     
    #define CAN_F13R2_FB11_Msk   (0x1UL << CAN_F13R2_FB11_Pos)
     
    #define CAN_F13R2_FB11   CAN_F13R2_FB11_Msk
     
    #define CAN_F13R2_FB12_Pos   (12U)
     
    #define CAN_F13R2_FB12_Msk   (0x1UL << CAN_F13R2_FB12_Pos)
     
    #define CAN_F13R2_FB12   CAN_F13R2_FB12_Msk
     
    #define CAN_F13R2_FB13_Pos   (13U)
     
    #define CAN_F13R2_FB13_Msk   (0x1UL << CAN_F13R2_FB13_Pos)
     
    #define CAN_F13R2_FB13   CAN_F13R2_FB13_Msk
     
    #define CAN_F13R2_FB14_Pos   (14U)
     
    #define CAN_F13R2_FB14_Msk   (0x1UL << CAN_F13R2_FB14_Pos)
     
    #define CAN_F13R2_FB14   CAN_F13R2_FB14_Msk
     
    #define CAN_F13R2_FB15_Pos   (15U)
     
    #define CAN_F13R2_FB15_Msk   (0x1UL << CAN_F13R2_FB15_Pos)
     
    #define CAN_F13R2_FB15   CAN_F13R2_FB15_Msk
     
    #define CAN_F13R2_FB16_Pos   (16U)
     
    #define CAN_F13R2_FB16_Msk   (0x1UL << CAN_F13R2_FB16_Pos)
     
    #define CAN_F13R2_FB16   CAN_F13R2_FB16_Msk
     
    #define CAN_F13R2_FB17_Pos   (17U)
     
    #define CAN_F13R2_FB17_Msk   (0x1UL << CAN_F13R2_FB17_Pos)
     
    #define CAN_F13R2_FB17   CAN_F13R2_FB17_Msk
     
    #define CAN_F13R2_FB18_Pos   (18U)
     
    #define CAN_F13R2_FB18_Msk   (0x1UL << CAN_F13R2_FB18_Pos)
     
    #define CAN_F13R2_FB18   CAN_F13R2_FB18_Msk
     
    #define CAN_F13R2_FB19_Pos   (19U)
     
    #define CAN_F13R2_FB19_Msk   (0x1UL << CAN_F13R2_FB19_Pos)
     
    #define CAN_F13R2_FB19   CAN_F13R2_FB19_Msk
     
    #define CAN_F13R2_FB20_Pos   (20U)
     
    #define CAN_F13R2_FB20_Msk   (0x1UL << CAN_F13R2_FB20_Pos)
     
    #define CAN_F13R2_FB20   CAN_F13R2_FB20_Msk
     
    #define CAN_F13R2_FB21_Pos   (21U)
     
    #define CAN_F13R2_FB21_Msk   (0x1UL << CAN_F13R2_FB21_Pos)
     
    #define CAN_F13R2_FB21   CAN_F13R2_FB21_Msk
     
    #define CAN_F13R2_FB22_Pos   (22U)
     
    #define CAN_F13R2_FB22_Msk   (0x1UL << CAN_F13R2_FB22_Pos)
     
    #define CAN_F13R2_FB22   CAN_F13R2_FB22_Msk
     
    #define CAN_F13R2_FB23_Pos   (23U)
     
    #define CAN_F13R2_FB23_Msk   (0x1UL << CAN_F13R2_FB23_Pos)
     
    #define CAN_F13R2_FB23   CAN_F13R2_FB23_Msk
     
    #define CAN_F13R2_FB24_Pos   (24U)
     
    #define CAN_F13R2_FB24_Msk   (0x1UL << CAN_F13R2_FB24_Pos)
     
    #define CAN_F13R2_FB24   CAN_F13R2_FB24_Msk
     
    #define CAN_F13R2_FB25_Pos   (25U)
     
    #define CAN_F13R2_FB25_Msk   (0x1UL << CAN_F13R2_FB25_Pos)
     
    #define CAN_F13R2_FB25   CAN_F13R2_FB25_Msk
     
    #define CAN_F13R2_FB26_Pos   (26U)
     
    #define CAN_F13R2_FB26_Msk   (0x1UL << CAN_F13R2_FB26_Pos)
     
    #define CAN_F13R2_FB26   CAN_F13R2_FB26_Msk
     
    #define CAN_F13R2_FB27_Pos   (27U)
     
    #define CAN_F13R2_FB27_Msk   (0x1UL << CAN_F13R2_FB27_Pos)
     
    #define CAN_F13R2_FB27   CAN_F13R2_FB27_Msk
     
    #define CAN_F13R2_FB28_Pos   (28U)
     
    #define CAN_F13R2_FB28_Msk   (0x1UL << CAN_F13R2_FB28_Pos)
     
    #define CAN_F13R2_FB28   CAN_F13R2_FB28_Msk
     
    #define CAN_F13R2_FB29_Pos   (29U)
     
    #define CAN_F13R2_FB29_Msk   (0x1UL << CAN_F13R2_FB29_Pos)
     
    #define CAN_F13R2_FB29   CAN_F13R2_FB29_Msk
     
    #define CAN_F13R2_FB30_Pos   (30U)
     
    #define CAN_F13R2_FB30_Msk   (0x1UL << CAN_F13R2_FB30_Pos)
     
    #define CAN_F13R2_FB30   CAN_F13R2_FB30_Msk
     
    #define CAN_F13R2_FB31_Pos   (31U)
     
    #define CAN_F13R2_FB31_Msk   (0x1UL << CAN_F13R2_FB31_Pos)
     
    #define CAN_F13R2_FB31   CAN_F13R2_FB31_Msk
     
    #define CRC_DR_DR_Pos   (0U)
     
    #define CRC_DR_DR_Msk   (0xFFFFFFFFUL << CRC_DR_DR_Pos)
     
    #define CRC_DR_DR   CRC_DR_DR_Msk
     
    #define CRC_IDR_IDR_Pos   (0U)
     
    #define CRC_IDR_IDR_Msk   (0xFFUL << CRC_IDR_IDR_Pos)
     
    #define CRC_IDR_IDR   CRC_IDR_IDR_Msk
     
    #define CRC_CR_RESET_Pos   (0U)
     
    #define CRC_CR_RESET_Msk   (0x1UL << CRC_CR_RESET_Pos)
     
    #define CRC_CR_RESET   CRC_CR_RESET_Msk
     
    #define DAC_CHANNEL2_SUPPORT
     
    #define DAC_CR_EN1_Pos   (0U)
     
    #define DAC_CR_EN1_Msk   (0x1UL << DAC_CR_EN1_Pos)
     
    #define DAC_CR_EN1   DAC_CR_EN1_Msk
     
    #define DAC_CR_BOFF1_Pos   (1U)
     
    #define DAC_CR_BOFF1_Msk   (0x1UL << DAC_CR_BOFF1_Pos)
     
    #define DAC_CR_BOFF1   DAC_CR_BOFF1_Msk
     
    #define DAC_CR_TEN1_Pos   (2U)
     
    #define DAC_CR_TEN1_Msk   (0x1UL << DAC_CR_TEN1_Pos)
     
    #define DAC_CR_TEN1   DAC_CR_TEN1_Msk
     
    #define DAC_CR_TSEL1_Pos   (3U)
     
    #define DAC_CR_TSEL1_Msk   (0x7UL << DAC_CR_TSEL1_Pos)
     
    #define DAC_CR_TSEL1   DAC_CR_TSEL1_Msk
     
    #define DAC_CR_TSEL1_0   (0x1UL << DAC_CR_TSEL1_Pos)
     
    #define DAC_CR_TSEL1_1   (0x2UL << DAC_CR_TSEL1_Pos)
     
    #define DAC_CR_TSEL1_2   (0x4UL << DAC_CR_TSEL1_Pos)
     
    #define DAC_CR_WAVE1_Pos   (6U)
     
    #define DAC_CR_WAVE1_Msk   (0x3UL << DAC_CR_WAVE1_Pos)
     
    #define DAC_CR_WAVE1   DAC_CR_WAVE1_Msk
     
    #define DAC_CR_WAVE1_0   (0x1UL << DAC_CR_WAVE1_Pos)
     
    #define DAC_CR_WAVE1_1   (0x2UL << DAC_CR_WAVE1_Pos)
     
    #define DAC_CR_MAMP1_Pos   (8U)
     
    #define DAC_CR_MAMP1_Msk   (0xFUL << DAC_CR_MAMP1_Pos)
     
    #define DAC_CR_MAMP1   DAC_CR_MAMP1_Msk
     
    #define DAC_CR_MAMP1_0   (0x1UL << DAC_CR_MAMP1_Pos)
     
    #define DAC_CR_MAMP1_1   (0x2UL << DAC_CR_MAMP1_Pos)
     
    #define DAC_CR_MAMP1_2   (0x4UL << DAC_CR_MAMP1_Pos)
     
    #define DAC_CR_MAMP1_3   (0x8UL << DAC_CR_MAMP1_Pos)
     
    #define DAC_CR_DMAEN1_Pos   (12U)
     
    #define DAC_CR_DMAEN1_Msk   (0x1UL << DAC_CR_DMAEN1_Pos)
     
    #define DAC_CR_DMAEN1   DAC_CR_DMAEN1_Msk
     
    #define DAC_CR_DMAUDRIE1_Pos   (13U)
     
    #define DAC_CR_DMAUDRIE1_Msk   (0x1UL << DAC_CR_DMAUDRIE1_Pos)
     
    #define DAC_CR_DMAUDRIE1   DAC_CR_DMAUDRIE1_Msk
     
    #define DAC_CR_EN2_Pos   (16U)
     
    #define DAC_CR_EN2_Msk   (0x1UL << DAC_CR_EN2_Pos)
     
    #define DAC_CR_EN2   DAC_CR_EN2_Msk
     
    #define DAC_CR_BOFF2_Pos   (17U)
     
    #define DAC_CR_BOFF2_Msk   (0x1UL << DAC_CR_BOFF2_Pos)
     
    #define DAC_CR_BOFF2   DAC_CR_BOFF2_Msk
     
    #define DAC_CR_TEN2_Pos   (18U)
     
    #define DAC_CR_TEN2_Msk   (0x1UL << DAC_CR_TEN2_Pos)
     
    #define DAC_CR_TEN2   DAC_CR_TEN2_Msk
     
    #define DAC_CR_TSEL2_Pos   (19U)
     
    #define DAC_CR_TSEL2_Msk   (0x7UL << DAC_CR_TSEL2_Pos)
     
    #define DAC_CR_TSEL2   DAC_CR_TSEL2_Msk
     
    #define DAC_CR_TSEL2_0   (0x1UL << DAC_CR_TSEL2_Pos)
     
    #define DAC_CR_TSEL2_1   (0x2UL << DAC_CR_TSEL2_Pos)
     
    #define DAC_CR_TSEL2_2   (0x4UL << DAC_CR_TSEL2_Pos)
     
    #define DAC_CR_WAVE2_Pos   (22U)
     
    #define DAC_CR_WAVE2_Msk   (0x3UL << DAC_CR_WAVE2_Pos)
     
    #define DAC_CR_WAVE2   DAC_CR_WAVE2_Msk
     
    #define DAC_CR_WAVE2_0   (0x1UL << DAC_CR_WAVE2_Pos)
     
    #define DAC_CR_WAVE2_1   (0x2UL << DAC_CR_WAVE2_Pos)
     
    #define DAC_CR_MAMP2_Pos   (24U)
     
    #define DAC_CR_MAMP2_Msk   (0xFUL << DAC_CR_MAMP2_Pos)
     
    #define DAC_CR_MAMP2   DAC_CR_MAMP2_Msk
     
    #define DAC_CR_MAMP2_0   (0x1UL << DAC_CR_MAMP2_Pos)
     
    #define DAC_CR_MAMP2_1   (0x2UL << DAC_CR_MAMP2_Pos)
     
    #define DAC_CR_MAMP2_2   (0x4UL << DAC_CR_MAMP2_Pos)
     
    #define DAC_CR_MAMP2_3   (0x8UL << DAC_CR_MAMP2_Pos)
     
    #define DAC_CR_DMAEN2_Pos   (28U)
     
    #define DAC_CR_DMAEN2_Msk   (0x1UL << DAC_CR_DMAEN2_Pos)
     
    #define DAC_CR_DMAEN2   DAC_CR_DMAEN2_Msk
     
    #define DAC_CR_DMAUDRIE2_Pos   (29U)
     
    #define DAC_CR_DMAUDRIE2_Msk   (0x1UL << DAC_CR_DMAUDRIE2_Pos)
     
    #define DAC_CR_DMAUDRIE2   DAC_CR_DMAUDRIE2_Msk
     
    #define DAC_SWTRIGR_SWTRIG1_Pos   (0U)
     
    #define DAC_SWTRIGR_SWTRIG1_Msk   (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos)
     
    #define DAC_SWTRIGR_SWTRIG1   DAC_SWTRIGR_SWTRIG1_Msk
     
    #define DAC_SWTRIGR_SWTRIG2_Pos   (1U)
     
    #define DAC_SWTRIGR_SWTRIG2_Msk   (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos)
     
    #define DAC_SWTRIGR_SWTRIG2   DAC_SWTRIGR_SWTRIG2_Msk
     
    #define DAC_DHR12R1_DACC1DHR_Pos   (0U)
     
    #define DAC_DHR12R1_DACC1DHR_Msk   (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos)
     
    #define DAC_DHR12R1_DACC1DHR   DAC_DHR12R1_DACC1DHR_Msk
     
    #define DAC_DHR12L1_DACC1DHR_Pos   (4U)
     
    #define DAC_DHR12L1_DACC1DHR_Msk   (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos)
     
    #define DAC_DHR12L1_DACC1DHR   DAC_DHR12L1_DACC1DHR_Msk
     
    #define DAC_DHR8R1_DACC1DHR_Pos   (0U)
     
    #define DAC_DHR8R1_DACC1DHR_Msk   (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos)
     
    #define DAC_DHR8R1_DACC1DHR   DAC_DHR8R1_DACC1DHR_Msk
     
    #define DAC_DHR12R2_DACC2DHR_Pos   (0U)
     
    #define DAC_DHR12R2_DACC2DHR_Msk   (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos)
     
    #define DAC_DHR12R2_DACC2DHR   DAC_DHR12R2_DACC2DHR_Msk
     
    #define DAC_DHR12L2_DACC2DHR_Pos   (4U)
     
    #define DAC_DHR12L2_DACC2DHR_Msk   (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos)
     
    #define DAC_DHR12L2_DACC2DHR   DAC_DHR12L2_DACC2DHR_Msk
     
    #define DAC_DHR8R2_DACC2DHR_Pos   (0U)
     
    #define DAC_DHR8R2_DACC2DHR_Msk   (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos)
     
    #define DAC_DHR8R2_DACC2DHR   DAC_DHR8R2_DACC2DHR_Msk
     
    #define DAC_DHR12RD_DACC1DHR_Pos   (0U)
     
    #define DAC_DHR12RD_DACC1DHR_Msk   (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos)
     
    #define DAC_DHR12RD_DACC1DHR   DAC_DHR12RD_DACC1DHR_Msk
     
    #define DAC_DHR12RD_DACC2DHR_Pos   (16U)
     
    #define DAC_DHR12RD_DACC2DHR_Msk   (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos)
     
    #define DAC_DHR12RD_DACC2DHR   DAC_DHR12RD_DACC2DHR_Msk
     
    #define DAC_DHR12LD_DACC1DHR_Pos   (4U)
     
    #define DAC_DHR12LD_DACC1DHR_Msk   (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos)
     
    #define DAC_DHR12LD_DACC1DHR   DAC_DHR12LD_DACC1DHR_Msk
     
    #define DAC_DHR12LD_DACC2DHR_Pos   (20U)
     
    #define DAC_DHR12LD_DACC2DHR_Msk   (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos)
     
    #define DAC_DHR12LD_DACC2DHR   DAC_DHR12LD_DACC2DHR_Msk
     
    #define DAC_DHR8RD_DACC1DHR_Pos   (0U)
     
    #define DAC_DHR8RD_DACC1DHR_Msk   (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos)
     
    #define DAC_DHR8RD_DACC1DHR   DAC_DHR8RD_DACC1DHR_Msk
     
    #define DAC_DHR8RD_DACC2DHR_Pos   (8U)
     
    #define DAC_DHR8RD_DACC2DHR_Msk   (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos)
     
    #define DAC_DHR8RD_DACC2DHR   DAC_DHR8RD_DACC2DHR_Msk
     
    #define DAC_DOR1_DACC1DOR_Pos   (0U)
     
    #define DAC_DOR1_DACC1DOR_Msk   (0xFFFUL << DAC_DOR1_DACC1DOR_Pos)
     
    #define DAC_DOR1_DACC1DOR   DAC_DOR1_DACC1DOR_Msk
     
    #define DAC_DOR2_DACC2DOR_Pos   (0U)
     
    #define DAC_DOR2_DACC2DOR_Msk   (0xFFFUL << DAC_DOR2_DACC2DOR_Pos)
     
    #define DAC_DOR2_DACC2DOR   DAC_DOR2_DACC2DOR_Msk
     
    #define DAC_SR_DMAUDR1_Pos   (13U)
     
    #define DAC_SR_DMAUDR1_Msk   (0x1UL << DAC_SR_DMAUDR1_Pos)
     
    #define DAC_SR_DMAUDR1   DAC_SR_DMAUDR1_Msk
     
    #define DAC_SR_DMAUDR2_Pos   (29U)
     
    #define DAC_SR_DMAUDR2_Msk   (0x1UL << DAC_SR_DMAUDR2_Pos)
     
    #define DAC_SR_DMAUDR2   DAC_SR_DMAUDR2_Msk
     
    #define DCMI_CR_CAPTURE_Pos   (0U)
     
    #define DCMI_CR_CAPTURE_Msk   (0x1UL << DCMI_CR_CAPTURE_Pos)
     
    #define DCMI_CR_CAPTURE   DCMI_CR_CAPTURE_Msk
     
    #define DCMI_CR_CM_Pos   (1U)
     
    #define DCMI_CR_CM_Msk   (0x1UL << DCMI_CR_CM_Pos)
     
    #define DCMI_CR_CM   DCMI_CR_CM_Msk
     
    #define DCMI_CR_CROP_Pos   (2U)
     
    #define DCMI_CR_CROP_Msk   (0x1UL << DCMI_CR_CROP_Pos)
     
    #define DCMI_CR_CROP   DCMI_CR_CROP_Msk
     
    #define DCMI_CR_JPEG_Pos   (3U)
     
    #define DCMI_CR_JPEG_Msk   (0x1UL << DCMI_CR_JPEG_Pos)
     
    #define DCMI_CR_JPEG   DCMI_CR_JPEG_Msk
     
    #define DCMI_CR_ESS_Pos   (4U)
     
    #define DCMI_CR_ESS_Msk   (0x1UL << DCMI_CR_ESS_Pos)
     
    #define DCMI_CR_ESS   DCMI_CR_ESS_Msk
     
    #define DCMI_CR_PCKPOL_Pos   (5U)
     
    #define DCMI_CR_PCKPOL_Msk   (0x1UL << DCMI_CR_PCKPOL_Pos)
     
    #define DCMI_CR_PCKPOL   DCMI_CR_PCKPOL_Msk
     
    #define DCMI_CR_HSPOL_Pos   (6U)
     
    #define DCMI_CR_HSPOL_Msk   (0x1UL << DCMI_CR_HSPOL_Pos)
     
    #define DCMI_CR_HSPOL   DCMI_CR_HSPOL_Msk
     
    #define DCMI_CR_VSPOL_Pos   (7U)
     
    #define DCMI_CR_VSPOL_Msk   (0x1UL << DCMI_CR_VSPOL_Pos)
     
    #define DCMI_CR_VSPOL   DCMI_CR_VSPOL_Msk
     
    #define DCMI_CR_FCRC_0   0x00000100U
     
    #define DCMI_CR_FCRC_1   0x00000200U
     
    #define DCMI_CR_EDM_0   0x00000400U
     
    #define DCMI_CR_EDM_1   0x00000800U
     
    #define DCMI_CR_CRE_Pos   (12U)
     
    #define DCMI_CR_CRE_Msk   (0x1UL << DCMI_CR_CRE_Pos)
     
    #define DCMI_CR_CRE   DCMI_CR_CRE_Msk
     
    #define DCMI_CR_ENABLE_Pos   (14U)
     
    #define DCMI_CR_ENABLE_Msk   (0x1UL << DCMI_CR_ENABLE_Pos)
     
    #define DCMI_CR_ENABLE   DCMI_CR_ENABLE_Msk
     
    #define DCMI_SR_HSYNC_Pos   (0U)
     
    #define DCMI_SR_HSYNC_Msk   (0x1UL << DCMI_SR_HSYNC_Pos)
     
    #define DCMI_SR_HSYNC   DCMI_SR_HSYNC_Msk
     
    #define DCMI_SR_VSYNC_Pos   (1U)
     
    #define DCMI_SR_VSYNC_Msk   (0x1UL << DCMI_SR_VSYNC_Pos)
     
    #define DCMI_SR_VSYNC   DCMI_SR_VSYNC_Msk
     
    #define DCMI_SR_FNE_Pos   (2U)
     
    #define DCMI_SR_FNE_Msk   (0x1UL << DCMI_SR_FNE_Pos)
     
    #define DCMI_SR_FNE   DCMI_SR_FNE_Msk
     
    #define DCMI_RIS_FRAME_RIS_Pos   (0U)
     
    #define DCMI_RIS_FRAME_RIS_Msk   (0x1UL << DCMI_RIS_FRAME_RIS_Pos)
     
    #define DCMI_RIS_FRAME_RIS   DCMI_RIS_FRAME_RIS_Msk
     
    #define DCMI_RIS_OVR_RIS_Pos   (1U)
     
    #define DCMI_RIS_OVR_RIS_Msk   (0x1UL << DCMI_RIS_OVR_RIS_Pos)
     
    #define DCMI_RIS_OVR_RIS   DCMI_RIS_OVR_RIS_Msk
     
    #define DCMI_RIS_ERR_RIS_Pos   (2U)
     
    #define DCMI_RIS_ERR_RIS_Msk   (0x1UL << DCMI_RIS_ERR_RIS_Pos)
     
    #define DCMI_RIS_ERR_RIS   DCMI_RIS_ERR_RIS_Msk
     
    #define DCMI_RIS_VSYNC_RIS_Pos   (3U)
     
    #define DCMI_RIS_VSYNC_RIS_Msk   (0x1UL << DCMI_RIS_VSYNC_RIS_Pos)
     
    #define DCMI_RIS_VSYNC_RIS   DCMI_RIS_VSYNC_RIS_Msk
     
    #define DCMI_RIS_LINE_RIS_Pos   (4U)
     
    #define DCMI_RIS_LINE_RIS_Msk   (0x1UL << DCMI_RIS_LINE_RIS_Pos)
     
    #define DCMI_RIS_LINE_RIS   DCMI_RIS_LINE_RIS_Msk
     
    #define DCMI_RISR_FRAME_RIS   DCMI_RIS_FRAME_RIS
     
    #define DCMI_RISR_OVR_RIS   DCMI_RIS_OVR_RIS
     
    #define DCMI_RISR_ERR_RIS   DCMI_RIS_ERR_RIS
     
    #define DCMI_RISR_VSYNC_RIS   DCMI_RIS_VSYNC_RIS
     
    #define DCMI_RISR_LINE_RIS   DCMI_RIS_LINE_RIS
     
    #define DCMI_RISR_OVF_RIS   DCMI_RIS_OVR_RIS
     
    #define DCMI_IER_FRAME_IE_Pos   (0U)
     
    #define DCMI_IER_FRAME_IE_Msk   (0x1UL << DCMI_IER_FRAME_IE_Pos)
     
    #define DCMI_IER_FRAME_IE   DCMI_IER_FRAME_IE_Msk
     
    #define DCMI_IER_OVR_IE_Pos   (1U)
     
    #define DCMI_IER_OVR_IE_Msk   (0x1UL << DCMI_IER_OVR_IE_Pos)
     
    #define DCMI_IER_OVR_IE   DCMI_IER_OVR_IE_Msk
     
    #define DCMI_IER_ERR_IE_Pos   (2U)
     
    #define DCMI_IER_ERR_IE_Msk   (0x1UL << DCMI_IER_ERR_IE_Pos)
     
    #define DCMI_IER_ERR_IE   DCMI_IER_ERR_IE_Msk
     
    #define DCMI_IER_VSYNC_IE_Pos   (3U)
     
    #define DCMI_IER_VSYNC_IE_Msk   (0x1UL << DCMI_IER_VSYNC_IE_Pos)
     
    #define DCMI_IER_VSYNC_IE   DCMI_IER_VSYNC_IE_Msk
     
    #define DCMI_IER_LINE_IE_Pos   (4U)
     
    #define DCMI_IER_LINE_IE_Msk   (0x1UL << DCMI_IER_LINE_IE_Pos)
     
    #define DCMI_IER_LINE_IE   DCMI_IER_LINE_IE_Msk
     
    #define DCMI_IER_OVF_IE   DCMI_IER_OVR_IE
     
    #define DCMI_MIS_FRAME_MIS_Pos   (0U)
     
    #define DCMI_MIS_FRAME_MIS_Msk   (0x1UL << DCMI_MIS_FRAME_MIS_Pos)
     
    #define DCMI_MIS_FRAME_MIS   DCMI_MIS_FRAME_MIS_Msk
     
    #define DCMI_MIS_OVR_MIS_Pos   (1U)
     
    #define DCMI_MIS_OVR_MIS_Msk   (0x1UL << DCMI_MIS_OVR_MIS_Pos)
     
    #define DCMI_MIS_OVR_MIS   DCMI_MIS_OVR_MIS_Msk
     
    #define DCMI_MIS_ERR_MIS_Pos   (2U)
     
    #define DCMI_MIS_ERR_MIS_Msk   (0x1UL << DCMI_MIS_ERR_MIS_Pos)
     
    #define DCMI_MIS_ERR_MIS   DCMI_MIS_ERR_MIS_Msk
     
    #define DCMI_MIS_VSYNC_MIS_Pos   (3U)
     
    #define DCMI_MIS_VSYNC_MIS_Msk   (0x1UL << DCMI_MIS_VSYNC_MIS_Pos)
     
    #define DCMI_MIS_VSYNC_MIS   DCMI_MIS_VSYNC_MIS_Msk
     
    #define DCMI_MIS_LINE_MIS_Pos   (4U)
     
    #define DCMI_MIS_LINE_MIS_Msk   (0x1UL << DCMI_MIS_LINE_MIS_Pos)
     
    #define DCMI_MIS_LINE_MIS   DCMI_MIS_LINE_MIS_Msk
     
    #define DCMI_MISR_FRAME_MIS   DCMI_MIS_FRAME_MIS
     
    #define DCMI_MISR_OVF_MIS   DCMI_MIS_OVR_MIS
     
    #define DCMI_MISR_ERR_MIS   DCMI_MIS_ERR_MIS
     
    #define DCMI_MISR_VSYNC_MIS   DCMI_MIS_VSYNC_MIS
     
    #define DCMI_MISR_LINE_MIS   DCMI_MIS_LINE_MIS
     
    #define DCMI_ICR_FRAME_ISC_Pos   (0U)
     
    #define DCMI_ICR_FRAME_ISC_Msk   (0x1UL << DCMI_ICR_FRAME_ISC_Pos)
     
    #define DCMI_ICR_FRAME_ISC   DCMI_ICR_FRAME_ISC_Msk
     
    #define DCMI_ICR_OVR_ISC_Pos   (1U)
     
    #define DCMI_ICR_OVR_ISC_Msk   (0x1UL << DCMI_ICR_OVR_ISC_Pos)
     
    #define DCMI_ICR_OVR_ISC   DCMI_ICR_OVR_ISC_Msk
     
    #define DCMI_ICR_ERR_ISC_Pos   (2U)
     
    #define DCMI_ICR_ERR_ISC_Msk   (0x1UL << DCMI_ICR_ERR_ISC_Pos)
     
    #define DCMI_ICR_ERR_ISC   DCMI_ICR_ERR_ISC_Msk
     
    #define DCMI_ICR_VSYNC_ISC_Pos   (3U)
     
    #define DCMI_ICR_VSYNC_ISC_Msk   (0x1UL << DCMI_ICR_VSYNC_ISC_Pos)
     
    #define DCMI_ICR_VSYNC_ISC   DCMI_ICR_VSYNC_ISC_Msk
     
    #define DCMI_ICR_LINE_ISC_Pos   (4U)
     
    #define DCMI_ICR_LINE_ISC_Msk   (0x1UL << DCMI_ICR_LINE_ISC_Pos)
     
    #define DCMI_ICR_LINE_ISC   DCMI_ICR_LINE_ISC_Msk
     
    #define DCMI_ICR_OVF_ISC   DCMI_ICR_OVR_ISC
     
    #define DCMI_ESCR_FSC_Pos   (0U)
     
    #define DCMI_ESCR_FSC_Msk   (0xFFUL << DCMI_ESCR_FSC_Pos)
     
    #define DCMI_ESCR_FSC   DCMI_ESCR_FSC_Msk
     
    #define DCMI_ESCR_LSC_Pos   (8U)
     
    #define DCMI_ESCR_LSC_Msk   (0xFFUL << DCMI_ESCR_LSC_Pos)
     
    #define DCMI_ESCR_LSC   DCMI_ESCR_LSC_Msk
     
    #define DCMI_ESCR_LEC_Pos   (16U)
     
    #define DCMI_ESCR_LEC_Msk   (0xFFUL << DCMI_ESCR_LEC_Pos)
     
    #define DCMI_ESCR_LEC   DCMI_ESCR_LEC_Msk
     
    #define DCMI_ESCR_FEC_Pos   (24U)
     
    #define DCMI_ESCR_FEC_Msk   (0xFFUL << DCMI_ESCR_FEC_Pos)
     
    #define DCMI_ESCR_FEC   DCMI_ESCR_FEC_Msk
     
    #define DCMI_ESUR_FSU_Pos   (0U)
     
    #define DCMI_ESUR_FSU_Msk   (0xFFUL << DCMI_ESUR_FSU_Pos)
     
    #define DCMI_ESUR_FSU   DCMI_ESUR_FSU_Msk
     
    #define DCMI_ESUR_LSU_Pos   (8U)
     
    #define DCMI_ESUR_LSU_Msk   (0xFFUL << DCMI_ESUR_LSU_Pos)
     
    #define DCMI_ESUR_LSU   DCMI_ESUR_LSU_Msk
     
    #define DCMI_ESUR_LEU_Pos   (16U)
     
    #define DCMI_ESUR_LEU_Msk   (0xFFUL << DCMI_ESUR_LEU_Pos)
     
    #define DCMI_ESUR_LEU   DCMI_ESUR_LEU_Msk
     
    #define DCMI_ESUR_FEU_Pos   (24U)
     
    #define DCMI_ESUR_FEU_Msk   (0xFFUL << DCMI_ESUR_FEU_Pos)
     
    #define DCMI_ESUR_FEU   DCMI_ESUR_FEU_Msk
     
    #define DCMI_CWSTRT_HOFFCNT_Pos   (0U)
     
    #define DCMI_CWSTRT_HOFFCNT_Msk   (0x3FFFUL << DCMI_CWSTRT_HOFFCNT_Pos)
     
    #define DCMI_CWSTRT_HOFFCNT   DCMI_CWSTRT_HOFFCNT_Msk
     
    #define DCMI_CWSTRT_VST_Pos   (16U)
     
    #define DCMI_CWSTRT_VST_Msk   (0x1FFFUL << DCMI_CWSTRT_VST_Pos)
     
    #define DCMI_CWSTRT_VST   DCMI_CWSTRT_VST_Msk
     
    #define DCMI_CWSIZE_CAPCNT_Pos   (0U)
     
    #define DCMI_CWSIZE_CAPCNT_Msk   (0x3FFFUL << DCMI_CWSIZE_CAPCNT_Pos)
     
    #define DCMI_CWSIZE_CAPCNT   DCMI_CWSIZE_CAPCNT_Msk
     
    #define DCMI_CWSIZE_VLINE_Pos   (16U)
     
    #define DCMI_CWSIZE_VLINE_Msk   (0x3FFFUL << DCMI_CWSIZE_VLINE_Pos)
     
    #define DCMI_CWSIZE_VLINE   DCMI_CWSIZE_VLINE_Msk
     
    #define DCMI_DR_BYTE0_Pos   (0U)
     
    #define DCMI_DR_BYTE0_Msk   (0xFFUL << DCMI_DR_BYTE0_Pos)
     
    #define DCMI_DR_BYTE0   DCMI_DR_BYTE0_Msk
     
    #define DCMI_DR_BYTE1_Pos   (8U)
     
    #define DCMI_DR_BYTE1_Msk   (0xFFUL << DCMI_DR_BYTE1_Pos)
     
    #define DCMI_DR_BYTE1   DCMI_DR_BYTE1_Msk
     
    #define DCMI_DR_BYTE2_Pos   (16U)
     
    #define DCMI_DR_BYTE2_Msk   (0xFFUL << DCMI_DR_BYTE2_Pos)
     
    #define DCMI_DR_BYTE2   DCMI_DR_BYTE2_Msk
     
    #define DCMI_DR_BYTE3_Pos   (24U)
     
    #define DCMI_DR_BYTE3_Msk   (0xFFUL << DCMI_DR_BYTE3_Pos)
     
    #define DCMI_DR_BYTE3   DCMI_DR_BYTE3_Msk
     
    #define DMA_SxCR_CHSEL_Pos   (25U)
     
    #define DMA_SxCR_CHSEL_Msk   (0x7UL << DMA_SxCR_CHSEL_Pos)
     
    #define DMA_SxCR_CHSEL   DMA_SxCR_CHSEL_Msk
     
    #define DMA_SxCR_CHSEL_0   0x02000000U
     
    #define DMA_SxCR_CHSEL_1   0x04000000U
     
    #define DMA_SxCR_CHSEL_2   0x08000000U
     
    #define DMA_SxCR_MBURST_Pos   (23U)
     
    #define DMA_SxCR_MBURST_Msk   (0x3UL << DMA_SxCR_MBURST_Pos)
     
    #define DMA_SxCR_MBURST   DMA_SxCR_MBURST_Msk
     
    #define DMA_SxCR_MBURST_0   (0x1UL << DMA_SxCR_MBURST_Pos)
     
    #define DMA_SxCR_MBURST_1   (0x2UL << DMA_SxCR_MBURST_Pos)
     
    #define DMA_SxCR_PBURST_Pos   (21U)
     
    #define DMA_SxCR_PBURST_Msk   (0x3UL << DMA_SxCR_PBURST_Pos)
     
    #define DMA_SxCR_PBURST   DMA_SxCR_PBURST_Msk
     
    #define DMA_SxCR_PBURST_0   (0x1UL << DMA_SxCR_PBURST_Pos)
     
    #define DMA_SxCR_PBURST_1   (0x2UL << DMA_SxCR_PBURST_Pos)
     
    #define DMA_SxCR_CT_Pos   (19U)
     
    #define DMA_SxCR_CT_Msk   (0x1UL << DMA_SxCR_CT_Pos)
     
    #define DMA_SxCR_CT   DMA_SxCR_CT_Msk
     
    #define DMA_SxCR_DBM_Pos   (18U)
     
    #define DMA_SxCR_DBM_Msk   (0x1UL << DMA_SxCR_DBM_Pos)
     
    #define DMA_SxCR_DBM   DMA_SxCR_DBM_Msk
     
    #define DMA_SxCR_PL_Pos   (16U)
     
    #define DMA_SxCR_PL_Msk   (0x3UL << DMA_SxCR_PL_Pos)
     
    #define DMA_SxCR_PL   DMA_SxCR_PL_Msk
     
    #define DMA_SxCR_PL_0   (0x1UL << DMA_SxCR_PL_Pos)
     
    #define DMA_SxCR_PL_1   (0x2UL << DMA_SxCR_PL_Pos)
     
    #define DMA_SxCR_PINCOS_Pos   (15U)
     
    #define DMA_SxCR_PINCOS_Msk   (0x1UL << DMA_SxCR_PINCOS_Pos)
     
    #define DMA_SxCR_PINCOS   DMA_SxCR_PINCOS_Msk
     
    #define DMA_SxCR_MSIZE_Pos   (13U)
     
    #define DMA_SxCR_MSIZE_Msk   (0x3UL << DMA_SxCR_MSIZE_Pos)
     
    #define DMA_SxCR_MSIZE   DMA_SxCR_MSIZE_Msk
     
    #define DMA_SxCR_MSIZE_0   (0x1UL << DMA_SxCR_MSIZE_Pos)
     
    #define DMA_SxCR_MSIZE_1   (0x2UL << DMA_SxCR_MSIZE_Pos)
     
    #define DMA_SxCR_PSIZE_Pos   (11U)
     
    #define DMA_SxCR_PSIZE_Msk   (0x3UL << DMA_SxCR_PSIZE_Pos)
     
    #define DMA_SxCR_PSIZE   DMA_SxCR_PSIZE_Msk
     
    #define DMA_SxCR_PSIZE_0   (0x1UL << DMA_SxCR_PSIZE_Pos)
     
    #define DMA_SxCR_PSIZE_1   (0x2UL << DMA_SxCR_PSIZE_Pos)
     
    #define DMA_SxCR_MINC_Pos   (10U)
     
    #define DMA_SxCR_MINC_Msk   (0x1UL << DMA_SxCR_MINC_Pos)
     
    #define DMA_SxCR_MINC   DMA_SxCR_MINC_Msk
     
    #define DMA_SxCR_PINC_Pos   (9U)
     
    #define DMA_SxCR_PINC_Msk   (0x1UL << DMA_SxCR_PINC_Pos)
     
    #define DMA_SxCR_PINC   DMA_SxCR_PINC_Msk
     
    #define DMA_SxCR_CIRC_Pos   (8U)
     
    #define DMA_SxCR_CIRC_Msk   (0x1UL << DMA_SxCR_CIRC_Pos)
     
    #define DMA_SxCR_CIRC   DMA_SxCR_CIRC_Msk
     
    #define DMA_SxCR_DIR_Pos   (6U)
     
    #define DMA_SxCR_DIR_Msk   (0x3UL << DMA_SxCR_DIR_Pos)
     
    #define DMA_SxCR_DIR   DMA_SxCR_DIR_Msk
     
    #define DMA_SxCR_DIR_0   (0x1UL << DMA_SxCR_DIR_Pos)
     
    #define DMA_SxCR_DIR_1   (0x2UL << DMA_SxCR_DIR_Pos)
     
    #define DMA_SxCR_PFCTRL_Pos   (5U)
     
    #define DMA_SxCR_PFCTRL_Msk   (0x1UL << DMA_SxCR_PFCTRL_Pos)
     
    #define DMA_SxCR_PFCTRL   DMA_SxCR_PFCTRL_Msk
     
    #define DMA_SxCR_TCIE_Pos   (4U)
     
    #define DMA_SxCR_TCIE_Msk   (0x1UL << DMA_SxCR_TCIE_Pos)
     
    #define DMA_SxCR_TCIE   DMA_SxCR_TCIE_Msk
     
    #define DMA_SxCR_HTIE_Pos   (3U)
     
    #define DMA_SxCR_HTIE_Msk   (0x1UL << DMA_SxCR_HTIE_Pos)
     
    #define DMA_SxCR_HTIE   DMA_SxCR_HTIE_Msk
     
    #define DMA_SxCR_TEIE_Pos   (2U)
     
    #define DMA_SxCR_TEIE_Msk   (0x1UL << DMA_SxCR_TEIE_Pos)
     
    #define DMA_SxCR_TEIE   DMA_SxCR_TEIE_Msk
     
    #define DMA_SxCR_DMEIE_Pos   (1U)
     
    #define DMA_SxCR_DMEIE_Msk   (0x1UL << DMA_SxCR_DMEIE_Pos)
     
    #define DMA_SxCR_DMEIE   DMA_SxCR_DMEIE_Msk
     
    #define DMA_SxCR_EN_Pos   (0U)
     
    #define DMA_SxCR_EN_Msk   (0x1UL << DMA_SxCR_EN_Pos)
     
    #define DMA_SxCR_EN   DMA_SxCR_EN_Msk
     
    #define DMA_SxCR_ACK_Pos   (20U)
     
    #define DMA_SxCR_ACK_Msk   (0x1UL << DMA_SxCR_ACK_Pos)
     
    #define DMA_SxCR_ACK   DMA_SxCR_ACK_Msk
     
    #define DMA_SxNDT_Pos   (0U)
     
    #define DMA_SxNDT_Msk   (0xFFFFUL << DMA_SxNDT_Pos)
     
    #define DMA_SxNDT   DMA_SxNDT_Msk
     
    #define DMA_SxNDT_0   (0x0001UL << DMA_SxNDT_Pos)
     
    #define DMA_SxNDT_1   (0x0002UL << DMA_SxNDT_Pos)
     
    #define DMA_SxNDT_2   (0x0004UL << DMA_SxNDT_Pos)
     
    #define DMA_SxNDT_3   (0x0008UL << DMA_SxNDT_Pos)
     
    #define DMA_SxNDT_4   (0x0010UL << DMA_SxNDT_Pos)
     
    #define DMA_SxNDT_5   (0x0020UL << DMA_SxNDT_Pos)
     
    #define DMA_SxNDT_6   (0x0040UL << DMA_SxNDT_Pos)
     
    #define DMA_SxNDT_7   (0x0080UL << DMA_SxNDT_Pos)
     
    #define DMA_SxNDT_8   (0x0100UL << DMA_SxNDT_Pos)
     
    #define DMA_SxNDT_9   (0x0200UL << DMA_SxNDT_Pos)
     
    #define DMA_SxNDT_10   (0x0400UL << DMA_SxNDT_Pos)
     
    #define DMA_SxNDT_11   (0x0800UL << DMA_SxNDT_Pos)
     
    #define DMA_SxNDT_12   (0x1000UL << DMA_SxNDT_Pos)
     
    #define DMA_SxNDT_13   (0x2000UL << DMA_SxNDT_Pos)
     
    #define DMA_SxNDT_14   (0x4000UL << DMA_SxNDT_Pos)
     
    #define DMA_SxNDT_15   (0x8000UL << DMA_SxNDT_Pos)
     
    #define DMA_SxFCR_FEIE_Pos   (7U)
     
    #define DMA_SxFCR_FEIE_Msk   (0x1UL << DMA_SxFCR_FEIE_Pos)
     
    #define DMA_SxFCR_FEIE   DMA_SxFCR_FEIE_Msk
     
    #define DMA_SxFCR_FS_Pos   (3U)
     
    #define DMA_SxFCR_FS_Msk   (0x7UL << DMA_SxFCR_FS_Pos)
     
    #define DMA_SxFCR_FS   DMA_SxFCR_FS_Msk
     
    #define DMA_SxFCR_FS_0   (0x1UL << DMA_SxFCR_FS_Pos)
     
    #define DMA_SxFCR_FS_1   (0x2UL << DMA_SxFCR_FS_Pos)
     
    #define DMA_SxFCR_FS_2   (0x4UL << DMA_SxFCR_FS_Pos)
     
    #define DMA_SxFCR_DMDIS_Pos   (2U)
     
    #define DMA_SxFCR_DMDIS_Msk   (0x1UL << DMA_SxFCR_DMDIS_Pos)
     
    #define DMA_SxFCR_DMDIS   DMA_SxFCR_DMDIS_Msk
     
    #define DMA_SxFCR_FTH_Pos   (0U)
     
    #define DMA_SxFCR_FTH_Msk   (0x3UL << DMA_SxFCR_FTH_Pos)
     
    #define DMA_SxFCR_FTH   DMA_SxFCR_FTH_Msk
     
    #define DMA_SxFCR_FTH_0   (0x1UL << DMA_SxFCR_FTH_Pos)
     
    #define DMA_SxFCR_FTH_1   (0x2UL << DMA_SxFCR_FTH_Pos)
     
    #define DMA_LISR_TCIF3_Pos   (27U)
     
    #define DMA_LISR_TCIF3_Msk   (0x1UL << DMA_LISR_TCIF3_Pos)
     
    #define DMA_LISR_TCIF3   DMA_LISR_TCIF3_Msk
     
    #define DMA_LISR_HTIF3_Pos   (26U)
     
    #define DMA_LISR_HTIF3_Msk   (0x1UL << DMA_LISR_HTIF3_Pos)
     
    #define DMA_LISR_HTIF3   DMA_LISR_HTIF3_Msk
     
    #define DMA_LISR_TEIF3_Pos   (25U)
     
    #define DMA_LISR_TEIF3_Msk   (0x1UL << DMA_LISR_TEIF3_Pos)
     
    #define DMA_LISR_TEIF3   DMA_LISR_TEIF3_Msk
     
    #define DMA_LISR_DMEIF3_Pos   (24U)
     
    #define DMA_LISR_DMEIF3_Msk   (0x1UL << DMA_LISR_DMEIF3_Pos)
     
    #define DMA_LISR_DMEIF3   DMA_LISR_DMEIF3_Msk
     
    #define DMA_LISR_FEIF3_Pos   (22U)
     
    #define DMA_LISR_FEIF3_Msk   (0x1UL << DMA_LISR_FEIF3_Pos)
     
    #define DMA_LISR_FEIF3   DMA_LISR_FEIF3_Msk
     
    #define DMA_LISR_TCIF2_Pos   (21U)
     
    #define DMA_LISR_TCIF2_Msk   (0x1UL << DMA_LISR_TCIF2_Pos)
     
    #define DMA_LISR_TCIF2   DMA_LISR_TCIF2_Msk
     
    #define DMA_LISR_HTIF2_Pos   (20U)
     
    #define DMA_LISR_HTIF2_Msk   (0x1UL << DMA_LISR_HTIF2_Pos)
     
    #define DMA_LISR_HTIF2   DMA_LISR_HTIF2_Msk
     
    #define DMA_LISR_TEIF2_Pos   (19U)
     
    #define DMA_LISR_TEIF2_Msk   (0x1UL << DMA_LISR_TEIF2_Pos)
     
    #define DMA_LISR_TEIF2   DMA_LISR_TEIF2_Msk
     
    #define DMA_LISR_DMEIF2_Pos   (18U)
     
    #define DMA_LISR_DMEIF2_Msk   (0x1UL << DMA_LISR_DMEIF2_Pos)
     
    #define DMA_LISR_DMEIF2   DMA_LISR_DMEIF2_Msk
     
    #define DMA_LISR_FEIF2_Pos   (16U)
     
    #define DMA_LISR_FEIF2_Msk   (0x1UL << DMA_LISR_FEIF2_Pos)
     
    #define DMA_LISR_FEIF2   DMA_LISR_FEIF2_Msk
     
    #define DMA_LISR_TCIF1_Pos   (11U)
     
    #define DMA_LISR_TCIF1_Msk   (0x1UL << DMA_LISR_TCIF1_Pos)
     
    #define DMA_LISR_TCIF1   DMA_LISR_TCIF1_Msk
     
    #define DMA_LISR_HTIF1_Pos   (10U)
     
    #define DMA_LISR_HTIF1_Msk   (0x1UL << DMA_LISR_HTIF1_Pos)
     
    #define DMA_LISR_HTIF1   DMA_LISR_HTIF1_Msk
     
    #define DMA_LISR_TEIF1_Pos   (9U)
     
    #define DMA_LISR_TEIF1_Msk   (0x1UL << DMA_LISR_TEIF1_Pos)
     
    #define DMA_LISR_TEIF1   DMA_LISR_TEIF1_Msk
     
    #define DMA_LISR_DMEIF1_Pos   (8U)
     
    #define DMA_LISR_DMEIF1_Msk   (0x1UL << DMA_LISR_DMEIF1_Pos)
     
    #define DMA_LISR_DMEIF1   DMA_LISR_DMEIF1_Msk
     
    #define DMA_LISR_FEIF1_Pos   (6U)
     
    #define DMA_LISR_FEIF1_Msk   (0x1UL << DMA_LISR_FEIF1_Pos)
     
    #define DMA_LISR_FEIF1   DMA_LISR_FEIF1_Msk
     
    #define DMA_LISR_TCIF0_Pos   (5U)
     
    #define DMA_LISR_TCIF0_Msk   (0x1UL << DMA_LISR_TCIF0_Pos)
     
    #define DMA_LISR_TCIF0   DMA_LISR_TCIF0_Msk
     
    #define DMA_LISR_HTIF0_Pos   (4U)
     
    #define DMA_LISR_HTIF0_Msk   (0x1UL << DMA_LISR_HTIF0_Pos)
     
    #define DMA_LISR_HTIF0   DMA_LISR_HTIF0_Msk
     
    #define DMA_LISR_TEIF0_Pos   (3U)
     
    #define DMA_LISR_TEIF0_Msk   (0x1UL << DMA_LISR_TEIF0_Pos)
     
    #define DMA_LISR_TEIF0   DMA_LISR_TEIF0_Msk
     
    #define DMA_LISR_DMEIF0_Pos   (2U)
     
    #define DMA_LISR_DMEIF0_Msk   (0x1UL << DMA_LISR_DMEIF0_Pos)
     
    #define DMA_LISR_DMEIF0   DMA_LISR_DMEIF0_Msk
     
    #define DMA_LISR_FEIF0_Pos   (0U)
     
    #define DMA_LISR_FEIF0_Msk   (0x1UL << DMA_LISR_FEIF0_Pos)
     
    #define DMA_LISR_FEIF0   DMA_LISR_FEIF0_Msk
     
    #define DMA_HISR_TCIF7_Pos   (27U)
     
    #define DMA_HISR_TCIF7_Msk   (0x1UL << DMA_HISR_TCIF7_Pos)
     
    #define DMA_HISR_TCIF7   DMA_HISR_TCIF7_Msk
     
    #define DMA_HISR_HTIF7_Pos   (26U)
     
    #define DMA_HISR_HTIF7_Msk   (0x1UL << DMA_HISR_HTIF7_Pos)
     
    #define DMA_HISR_HTIF7   DMA_HISR_HTIF7_Msk
     
    #define DMA_HISR_TEIF7_Pos   (25U)
     
    #define DMA_HISR_TEIF7_Msk   (0x1UL << DMA_HISR_TEIF7_Pos)
     
    #define DMA_HISR_TEIF7   DMA_HISR_TEIF7_Msk
     
    #define DMA_HISR_DMEIF7_Pos   (24U)
     
    #define DMA_HISR_DMEIF7_Msk   (0x1UL << DMA_HISR_DMEIF7_Pos)
     
    #define DMA_HISR_DMEIF7   DMA_HISR_DMEIF7_Msk
     
    #define DMA_HISR_FEIF7_Pos   (22U)
     
    #define DMA_HISR_FEIF7_Msk   (0x1UL << DMA_HISR_FEIF7_Pos)
     
    #define DMA_HISR_FEIF7   DMA_HISR_FEIF7_Msk
     
    #define DMA_HISR_TCIF6_Pos   (21U)
     
    #define DMA_HISR_TCIF6_Msk   (0x1UL << DMA_HISR_TCIF6_Pos)
     
    #define DMA_HISR_TCIF6   DMA_HISR_TCIF6_Msk
     
    #define DMA_HISR_HTIF6_Pos   (20U)
     
    #define DMA_HISR_HTIF6_Msk   (0x1UL << DMA_HISR_HTIF6_Pos)
     
    #define DMA_HISR_HTIF6   DMA_HISR_HTIF6_Msk
     
    #define DMA_HISR_TEIF6_Pos   (19U)
     
    #define DMA_HISR_TEIF6_Msk   (0x1UL << DMA_HISR_TEIF6_Pos)
     
    #define DMA_HISR_TEIF6   DMA_HISR_TEIF6_Msk
     
    #define DMA_HISR_DMEIF6_Pos   (18U)
     
    #define DMA_HISR_DMEIF6_Msk   (0x1UL << DMA_HISR_DMEIF6_Pos)
     
    #define DMA_HISR_DMEIF6   DMA_HISR_DMEIF6_Msk
     
    #define DMA_HISR_FEIF6_Pos   (16U)
     
    #define DMA_HISR_FEIF6_Msk   (0x1UL << DMA_HISR_FEIF6_Pos)
     
    #define DMA_HISR_FEIF6   DMA_HISR_FEIF6_Msk
     
    #define DMA_HISR_TCIF5_Pos   (11U)
     
    #define DMA_HISR_TCIF5_Msk   (0x1UL << DMA_HISR_TCIF5_Pos)
     
    #define DMA_HISR_TCIF5   DMA_HISR_TCIF5_Msk
     
    #define DMA_HISR_HTIF5_Pos   (10U)
     
    #define DMA_HISR_HTIF5_Msk   (0x1UL << DMA_HISR_HTIF5_Pos)
     
    #define DMA_HISR_HTIF5   DMA_HISR_HTIF5_Msk
     
    #define DMA_HISR_TEIF5_Pos   (9U)
     
    #define DMA_HISR_TEIF5_Msk   (0x1UL << DMA_HISR_TEIF5_Pos)
     
    #define DMA_HISR_TEIF5   DMA_HISR_TEIF5_Msk
     
    #define DMA_HISR_DMEIF5_Pos   (8U)
     
    #define DMA_HISR_DMEIF5_Msk   (0x1UL << DMA_HISR_DMEIF5_Pos)
     
    #define DMA_HISR_DMEIF5   DMA_HISR_DMEIF5_Msk
     
    #define DMA_HISR_FEIF5_Pos   (6U)
     
    #define DMA_HISR_FEIF5_Msk   (0x1UL << DMA_HISR_FEIF5_Pos)
     
    #define DMA_HISR_FEIF5   DMA_HISR_FEIF5_Msk
     
    #define DMA_HISR_TCIF4_Pos   (5U)
     
    #define DMA_HISR_TCIF4_Msk   (0x1UL << DMA_HISR_TCIF4_Pos)
     
    #define DMA_HISR_TCIF4   DMA_HISR_TCIF4_Msk
     
    #define DMA_HISR_HTIF4_Pos   (4U)
     
    #define DMA_HISR_HTIF4_Msk   (0x1UL << DMA_HISR_HTIF4_Pos)
     
    #define DMA_HISR_HTIF4   DMA_HISR_HTIF4_Msk
     
    #define DMA_HISR_TEIF4_Pos   (3U)
     
    #define DMA_HISR_TEIF4_Msk   (0x1UL << DMA_HISR_TEIF4_Pos)
     
    #define DMA_HISR_TEIF4   DMA_HISR_TEIF4_Msk
     
    #define DMA_HISR_DMEIF4_Pos   (2U)
     
    #define DMA_HISR_DMEIF4_Msk   (0x1UL << DMA_HISR_DMEIF4_Pos)
     
    #define DMA_HISR_DMEIF4   DMA_HISR_DMEIF4_Msk
     
    #define DMA_HISR_FEIF4_Pos   (0U)
     
    #define DMA_HISR_FEIF4_Msk   (0x1UL << DMA_HISR_FEIF4_Pos)
     
    #define DMA_HISR_FEIF4   DMA_HISR_FEIF4_Msk
     
    #define DMA_LIFCR_CTCIF3_Pos   (27U)
     
    #define DMA_LIFCR_CTCIF3_Msk   (0x1UL << DMA_LIFCR_CTCIF3_Pos)
     
    #define DMA_LIFCR_CTCIF3   DMA_LIFCR_CTCIF3_Msk
     
    #define DMA_LIFCR_CHTIF3_Pos   (26U)
     
    #define DMA_LIFCR_CHTIF3_Msk   (0x1UL << DMA_LIFCR_CHTIF3_Pos)
     
    #define DMA_LIFCR_CHTIF3   DMA_LIFCR_CHTIF3_Msk
     
    #define DMA_LIFCR_CTEIF3_Pos   (25U)
     
    #define DMA_LIFCR_CTEIF3_Msk   (0x1UL << DMA_LIFCR_CTEIF3_Pos)
     
    #define DMA_LIFCR_CTEIF3   DMA_LIFCR_CTEIF3_Msk
     
    #define DMA_LIFCR_CDMEIF3_Pos   (24U)
     
    #define DMA_LIFCR_CDMEIF3_Msk   (0x1UL << DMA_LIFCR_CDMEIF3_Pos)
     
    #define DMA_LIFCR_CDMEIF3   DMA_LIFCR_CDMEIF3_Msk
     
    #define DMA_LIFCR_CFEIF3_Pos   (22U)
     
    #define DMA_LIFCR_CFEIF3_Msk   (0x1UL << DMA_LIFCR_CFEIF3_Pos)
     
    #define DMA_LIFCR_CFEIF3   DMA_LIFCR_CFEIF3_Msk
     
    #define DMA_LIFCR_CTCIF2_Pos   (21U)
     
    #define DMA_LIFCR_CTCIF2_Msk   (0x1UL << DMA_LIFCR_CTCIF2_Pos)
     
    #define DMA_LIFCR_CTCIF2   DMA_LIFCR_CTCIF2_Msk
     
    #define DMA_LIFCR_CHTIF2_Pos   (20U)
     
    #define DMA_LIFCR_CHTIF2_Msk   (0x1UL << DMA_LIFCR_CHTIF2_Pos)
     
    #define DMA_LIFCR_CHTIF2   DMA_LIFCR_CHTIF2_Msk
     
    #define DMA_LIFCR_CTEIF2_Pos   (19U)
     
    #define DMA_LIFCR_CTEIF2_Msk   (0x1UL << DMA_LIFCR_CTEIF2_Pos)
     
    #define DMA_LIFCR_CTEIF2   DMA_LIFCR_CTEIF2_Msk
     
    #define DMA_LIFCR_CDMEIF2_Pos   (18U)
     
    #define DMA_LIFCR_CDMEIF2_Msk   (0x1UL << DMA_LIFCR_CDMEIF2_Pos)
     
    #define DMA_LIFCR_CDMEIF2   DMA_LIFCR_CDMEIF2_Msk
     
    #define DMA_LIFCR_CFEIF2_Pos   (16U)
     
    #define DMA_LIFCR_CFEIF2_Msk   (0x1UL << DMA_LIFCR_CFEIF2_Pos)
     
    #define DMA_LIFCR_CFEIF2   DMA_LIFCR_CFEIF2_Msk
     
    #define DMA_LIFCR_CTCIF1_Pos   (11U)
     
    #define DMA_LIFCR_CTCIF1_Msk   (0x1UL << DMA_LIFCR_CTCIF1_Pos)
     
    #define DMA_LIFCR_CTCIF1   DMA_LIFCR_CTCIF1_Msk
     
    #define DMA_LIFCR_CHTIF1_Pos   (10U)
     
    #define DMA_LIFCR_CHTIF1_Msk   (0x1UL << DMA_LIFCR_CHTIF1_Pos)
     
    #define DMA_LIFCR_CHTIF1   DMA_LIFCR_CHTIF1_Msk
     
    #define DMA_LIFCR_CTEIF1_Pos   (9U)
     
    #define DMA_LIFCR_CTEIF1_Msk   (0x1UL << DMA_LIFCR_CTEIF1_Pos)
     
    #define DMA_LIFCR_CTEIF1   DMA_LIFCR_CTEIF1_Msk
     
    #define DMA_LIFCR_CDMEIF1_Pos   (8U)
     
    #define DMA_LIFCR_CDMEIF1_Msk   (0x1UL << DMA_LIFCR_CDMEIF1_Pos)
     
    #define DMA_LIFCR_CDMEIF1   DMA_LIFCR_CDMEIF1_Msk
     
    #define DMA_LIFCR_CFEIF1_Pos   (6U)
     
    #define DMA_LIFCR_CFEIF1_Msk   (0x1UL << DMA_LIFCR_CFEIF1_Pos)
     
    #define DMA_LIFCR_CFEIF1   DMA_LIFCR_CFEIF1_Msk
     
    #define DMA_LIFCR_CTCIF0_Pos   (5U)
     
    #define DMA_LIFCR_CTCIF0_Msk   (0x1UL << DMA_LIFCR_CTCIF0_Pos)
     
    #define DMA_LIFCR_CTCIF0   DMA_LIFCR_CTCIF0_Msk
     
    #define DMA_LIFCR_CHTIF0_Pos   (4U)
     
    #define DMA_LIFCR_CHTIF0_Msk   (0x1UL << DMA_LIFCR_CHTIF0_Pos)
     
    #define DMA_LIFCR_CHTIF0   DMA_LIFCR_CHTIF0_Msk
     
    #define DMA_LIFCR_CTEIF0_Pos   (3U)
     
    #define DMA_LIFCR_CTEIF0_Msk   (0x1UL << DMA_LIFCR_CTEIF0_Pos)
     
    #define DMA_LIFCR_CTEIF0   DMA_LIFCR_CTEIF0_Msk
     
    #define DMA_LIFCR_CDMEIF0_Pos   (2U)
     
    #define DMA_LIFCR_CDMEIF0_Msk   (0x1UL << DMA_LIFCR_CDMEIF0_Pos)
     
    #define DMA_LIFCR_CDMEIF0   DMA_LIFCR_CDMEIF0_Msk
     
    #define DMA_LIFCR_CFEIF0_Pos   (0U)
     
    #define DMA_LIFCR_CFEIF0_Msk   (0x1UL << DMA_LIFCR_CFEIF0_Pos)
     
    #define DMA_LIFCR_CFEIF0   DMA_LIFCR_CFEIF0_Msk
     
    #define DMA_HIFCR_CTCIF7_Pos   (27U)
     
    #define DMA_HIFCR_CTCIF7_Msk   (0x1UL << DMA_HIFCR_CTCIF7_Pos)
     
    #define DMA_HIFCR_CTCIF7   DMA_HIFCR_CTCIF7_Msk
     
    #define DMA_HIFCR_CHTIF7_Pos   (26U)
     
    #define DMA_HIFCR_CHTIF7_Msk   (0x1UL << DMA_HIFCR_CHTIF7_Pos)
     
    #define DMA_HIFCR_CHTIF7   DMA_HIFCR_CHTIF7_Msk
     
    #define DMA_HIFCR_CTEIF7_Pos   (25U)
     
    #define DMA_HIFCR_CTEIF7_Msk   (0x1UL << DMA_HIFCR_CTEIF7_Pos)
     
    #define DMA_HIFCR_CTEIF7   DMA_HIFCR_CTEIF7_Msk
     
    #define DMA_HIFCR_CDMEIF7_Pos   (24U)
     
    #define DMA_HIFCR_CDMEIF7_Msk   (0x1UL << DMA_HIFCR_CDMEIF7_Pos)
     
    #define DMA_HIFCR_CDMEIF7   DMA_HIFCR_CDMEIF7_Msk
     
    #define DMA_HIFCR_CFEIF7_Pos   (22U)
     
    #define DMA_HIFCR_CFEIF7_Msk   (0x1UL << DMA_HIFCR_CFEIF7_Pos)
     
    #define DMA_HIFCR_CFEIF7   DMA_HIFCR_CFEIF7_Msk
     
    #define DMA_HIFCR_CTCIF6_Pos   (21U)
     
    #define DMA_HIFCR_CTCIF6_Msk   (0x1UL << DMA_HIFCR_CTCIF6_Pos)
     
    #define DMA_HIFCR_CTCIF6   DMA_HIFCR_CTCIF6_Msk
     
    #define DMA_HIFCR_CHTIF6_Pos   (20U)
     
    #define DMA_HIFCR_CHTIF6_Msk   (0x1UL << DMA_HIFCR_CHTIF6_Pos)
     
    #define DMA_HIFCR_CHTIF6   DMA_HIFCR_CHTIF6_Msk
     
    #define DMA_HIFCR_CTEIF6_Pos   (19U)
     
    #define DMA_HIFCR_CTEIF6_Msk   (0x1UL << DMA_HIFCR_CTEIF6_Pos)
     
    #define DMA_HIFCR_CTEIF6   DMA_HIFCR_CTEIF6_Msk
     
    #define DMA_HIFCR_CDMEIF6_Pos   (18U)
     
    #define DMA_HIFCR_CDMEIF6_Msk   (0x1UL << DMA_HIFCR_CDMEIF6_Pos)
     
    #define DMA_HIFCR_CDMEIF6   DMA_HIFCR_CDMEIF6_Msk
     
    #define DMA_HIFCR_CFEIF6_Pos   (16U)
     
    #define DMA_HIFCR_CFEIF6_Msk   (0x1UL << DMA_HIFCR_CFEIF6_Pos)
     
    #define DMA_HIFCR_CFEIF6   DMA_HIFCR_CFEIF6_Msk
     
    #define DMA_HIFCR_CTCIF5_Pos   (11U)
     
    #define DMA_HIFCR_CTCIF5_Msk   (0x1UL << DMA_HIFCR_CTCIF5_Pos)
     
    #define DMA_HIFCR_CTCIF5   DMA_HIFCR_CTCIF5_Msk
     
    #define DMA_HIFCR_CHTIF5_Pos   (10U)
     
    #define DMA_HIFCR_CHTIF5_Msk   (0x1UL << DMA_HIFCR_CHTIF5_Pos)
     
    #define DMA_HIFCR_CHTIF5   DMA_HIFCR_CHTIF5_Msk
     
    #define DMA_HIFCR_CTEIF5_Pos   (9U)
     
    #define DMA_HIFCR_CTEIF5_Msk   (0x1UL << DMA_HIFCR_CTEIF5_Pos)
     
    #define DMA_HIFCR_CTEIF5   DMA_HIFCR_CTEIF5_Msk
     
    #define DMA_HIFCR_CDMEIF5_Pos   (8U)
     
    #define DMA_HIFCR_CDMEIF5_Msk   (0x1UL << DMA_HIFCR_CDMEIF5_Pos)
     
    #define DMA_HIFCR_CDMEIF5   DMA_HIFCR_CDMEIF5_Msk
     
    #define DMA_HIFCR_CFEIF5_Pos   (6U)
     
    #define DMA_HIFCR_CFEIF5_Msk   (0x1UL << DMA_HIFCR_CFEIF5_Pos)
     
    #define DMA_HIFCR_CFEIF5   DMA_HIFCR_CFEIF5_Msk
     
    #define DMA_HIFCR_CTCIF4_Pos   (5U)
     
    #define DMA_HIFCR_CTCIF4_Msk   (0x1UL << DMA_HIFCR_CTCIF4_Pos)
     
    #define DMA_HIFCR_CTCIF4   DMA_HIFCR_CTCIF4_Msk
     
    #define DMA_HIFCR_CHTIF4_Pos   (4U)
     
    #define DMA_HIFCR_CHTIF4_Msk   (0x1UL << DMA_HIFCR_CHTIF4_Pos)
     
    #define DMA_HIFCR_CHTIF4   DMA_HIFCR_CHTIF4_Msk
     
    #define DMA_HIFCR_CTEIF4_Pos   (3U)
     
    #define DMA_HIFCR_CTEIF4_Msk   (0x1UL << DMA_HIFCR_CTEIF4_Pos)
     
    #define DMA_HIFCR_CTEIF4   DMA_HIFCR_CTEIF4_Msk
     
    #define DMA_HIFCR_CDMEIF4_Pos   (2U)
     
    #define DMA_HIFCR_CDMEIF4_Msk   (0x1UL << DMA_HIFCR_CDMEIF4_Pos)
     
    #define DMA_HIFCR_CDMEIF4   DMA_HIFCR_CDMEIF4_Msk
     
    #define DMA_HIFCR_CFEIF4_Pos   (0U)
     
    #define DMA_HIFCR_CFEIF4_Msk   (0x1UL << DMA_HIFCR_CFEIF4_Pos)
     
    #define DMA_HIFCR_CFEIF4   DMA_HIFCR_CFEIF4_Msk
     
    #define DMA_SxPAR_PA_Pos   (0U)
     
    #define DMA_SxPAR_PA_Msk   (0xFFFFFFFFUL << DMA_SxPAR_PA_Pos)
     
    #define DMA_SxPAR_PA   DMA_SxPAR_PA_Msk
     
    #define DMA_SxM0AR_M0A_Pos   (0U)
     
    #define DMA_SxM0AR_M0A_Msk   (0xFFFFFFFFUL << DMA_SxM0AR_M0A_Pos)
     
    #define DMA_SxM0AR_M0A   DMA_SxM0AR_M0A_Msk
     
    #define DMA_SxM1AR_M1A_Pos   (0U)
     
    #define DMA_SxM1AR_M1A_Msk   (0xFFFFFFFFUL << DMA_SxM1AR_M1A_Pos)
     
    #define DMA_SxM1AR_M1A   DMA_SxM1AR_M1A_Msk
     
    #define EXTI_IMR_MR0_Pos   (0U)
     
    #define EXTI_IMR_MR0_Msk   (0x1UL << EXTI_IMR_MR0_Pos)
     
    #define EXTI_IMR_MR0   EXTI_IMR_MR0_Msk
     
    #define EXTI_IMR_MR1_Pos   (1U)
     
    #define EXTI_IMR_MR1_Msk   (0x1UL << EXTI_IMR_MR1_Pos)
     
    #define EXTI_IMR_MR1   EXTI_IMR_MR1_Msk
     
    #define EXTI_IMR_MR2_Pos   (2U)
     
    #define EXTI_IMR_MR2_Msk   (0x1UL << EXTI_IMR_MR2_Pos)
     
    #define EXTI_IMR_MR2   EXTI_IMR_MR2_Msk
     
    #define EXTI_IMR_MR3_Pos   (3U)
     
    #define EXTI_IMR_MR3_Msk   (0x1UL << EXTI_IMR_MR3_Pos)
     
    #define EXTI_IMR_MR3   EXTI_IMR_MR3_Msk
     
    #define EXTI_IMR_MR4_Pos   (4U)
     
    #define EXTI_IMR_MR4_Msk   (0x1UL << EXTI_IMR_MR4_Pos)
     
    #define EXTI_IMR_MR4   EXTI_IMR_MR4_Msk
     
    #define EXTI_IMR_MR5_Pos   (5U)
     
    #define EXTI_IMR_MR5_Msk   (0x1UL << EXTI_IMR_MR5_Pos)
     
    #define EXTI_IMR_MR5   EXTI_IMR_MR5_Msk
     
    #define EXTI_IMR_MR6_Pos   (6U)
     
    #define EXTI_IMR_MR6_Msk   (0x1UL << EXTI_IMR_MR6_Pos)
     
    #define EXTI_IMR_MR6   EXTI_IMR_MR6_Msk
     
    #define EXTI_IMR_MR7_Pos   (7U)
     
    #define EXTI_IMR_MR7_Msk   (0x1UL << EXTI_IMR_MR7_Pos)
     
    #define EXTI_IMR_MR7   EXTI_IMR_MR7_Msk
     
    #define EXTI_IMR_MR8_Pos   (8U)
     
    #define EXTI_IMR_MR8_Msk   (0x1UL << EXTI_IMR_MR8_Pos)
     
    #define EXTI_IMR_MR8   EXTI_IMR_MR8_Msk
     
    #define EXTI_IMR_MR9_Pos   (9U)
     
    #define EXTI_IMR_MR9_Msk   (0x1UL << EXTI_IMR_MR9_Pos)
     
    #define EXTI_IMR_MR9   EXTI_IMR_MR9_Msk
     
    #define EXTI_IMR_MR10_Pos   (10U)
     
    #define EXTI_IMR_MR10_Msk   (0x1UL << EXTI_IMR_MR10_Pos)
     
    #define EXTI_IMR_MR10   EXTI_IMR_MR10_Msk
     
    #define EXTI_IMR_MR11_Pos   (11U)
     
    #define EXTI_IMR_MR11_Msk   (0x1UL << EXTI_IMR_MR11_Pos)
     
    #define EXTI_IMR_MR11   EXTI_IMR_MR11_Msk
     
    #define EXTI_IMR_MR12_Pos   (12U)
     
    #define EXTI_IMR_MR12_Msk   (0x1UL << EXTI_IMR_MR12_Pos)
     
    #define EXTI_IMR_MR12   EXTI_IMR_MR12_Msk
     
    #define EXTI_IMR_MR13_Pos   (13U)
     
    #define EXTI_IMR_MR13_Msk   (0x1UL << EXTI_IMR_MR13_Pos)
     
    #define EXTI_IMR_MR13   EXTI_IMR_MR13_Msk
     
    #define EXTI_IMR_MR14_Pos   (14U)
     
    #define EXTI_IMR_MR14_Msk   (0x1UL << EXTI_IMR_MR14_Pos)
     
    #define EXTI_IMR_MR14   EXTI_IMR_MR14_Msk
     
    #define EXTI_IMR_MR15_Pos   (15U)
     
    #define EXTI_IMR_MR15_Msk   (0x1UL << EXTI_IMR_MR15_Pos)
     
    #define EXTI_IMR_MR15   EXTI_IMR_MR15_Msk
     
    #define EXTI_IMR_MR16_Pos   (16U)
     
    #define EXTI_IMR_MR16_Msk   (0x1UL << EXTI_IMR_MR16_Pos)
     
    #define EXTI_IMR_MR16   EXTI_IMR_MR16_Msk
     
    #define EXTI_IMR_MR17_Pos   (17U)
     
    #define EXTI_IMR_MR17_Msk   (0x1UL << EXTI_IMR_MR17_Pos)
     
    #define EXTI_IMR_MR17   EXTI_IMR_MR17_Msk
     
    #define EXTI_IMR_MR18_Pos   (18U)
     
    #define EXTI_IMR_MR18_Msk   (0x1UL << EXTI_IMR_MR18_Pos)
     
    #define EXTI_IMR_MR18   EXTI_IMR_MR18_Msk
     
    #define EXTI_IMR_MR19_Pos   (19U)
     
    #define EXTI_IMR_MR19_Msk   (0x1UL << EXTI_IMR_MR19_Pos)
     
    #define EXTI_IMR_MR19   EXTI_IMR_MR19_Msk
     
    #define EXTI_IMR_MR20_Pos   (20U)
     
    #define EXTI_IMR_MR20_Msk   (0x1UL << EXTI_IMR_MR20_Pos)
     
    #define EXTI_IMR_MR20   EXTI_IMR_MR20_Msk
     
    #define EXTI_IMR_MR21_Pos   (21U)
     
    #define EXTI_IMR_MR21_Msk   (0x1UL << EXTI_IMR_MR21_Pos)
     
    #define EXTI_IMR_MR21   EXTI_IMR_MR21_Msk
     
    #define EXTI_IMR_MR22_Pos   (22U)
     
    #define EXTI_IMR_MR22_Msk   (0x1UL << EXTI_IMR_MR22_Pos)
     
    #define EXTI_IMR_MR22   EXTI_IMR_MR22_Msk
     
    #define EXTI_IMR_IM0   EXTI_IMR_MR0
     
    #define EXTI_IMR_IM1   EXTI_IMR_MR1
     
    #define EXTI_IMR_IM2   EXTI_IMR_MR2
     
    #define EXTI_IMR_IM3   EXTI_IMR_MR3
     
    #define EXTI_IMR_IM4   EXTI_IMR_MR4
     
    #define EXTI_IMR_IM5   EXTI_IMR_MR5
     
    #define EXTI_IMR_IM6   EXTI_IMR_MR6
     
    #define EXTI_IMR_IM7   EXTI_IMR_MR7
     
    #define EXTI_IMR_IM8   EXTI_IMR_MR8
     
    #define EXTI_IMR_IM9   EXTI_IMR_MR9
     
    #define EXTI_IMR_IM10   EXTI_IMR_MR10
     
    #define EXTI_IMR_IM11   EXTI_IMR_MR11
     
    #define EXTI_IMR_IM12   EXTI_IMR_MR12
     
    #define EXTI_IMR_IM13   EXTI_IMR_MR13
     
    #define EXTI_IMR_IM14   EXTI_IMR_MR14
     
    #define EXTI_IMR_IM15   EXTI_IMR_MR15
     
    #define EXTI_IMR_IM16   EXTI_IMR_MR16
     
    #define EXTI_IMR_IM17   EXTI_IMR_MR17
     
    #define EXTI_IMR_IM18   EXTI_IMR_MR18
     
    #define EXTI_IMR_IM19   EXTI_IMR_MR19
     
    #define EXTI_IMR_IM20   EXTI_IMR_MR20
     
    #define EXTI_IMR_IM21   EXTI_IMR_MR21
     
    #define EXTI_IMR_IM22   EXTI_IMR_MR22
     
    #define EXTI_IMR_IM_Pos   (0U)
     
    #define EXTI_IMR_IM_Msk   (0x7FFFFFUL << EXTI_IMR_IM_Pos)
     
    #define EXTI_IMR_IM   EXTI_IMR_IM_Msk
     
    #define EXTI_EMR_MR0_Pos   (0U)
     
    #define EXTI_EMR_MR0_Msk   (0x1UL << EXTI_EMR_MR0_Pos)
     
    #define EXTI_EMR_MR0   EXTI_EMR_MR0_Msk
     
    #define EXTI_EMR_MR1_Pos   (1U)
     
    #define EXTI_EMR_MR1_Msk   (0x1UL << EXTI_EMR_MR1_Pos)
     
    #define EXTI_EMR_MR1   EXTI_EMR_MR1_Msk
     
    #define EXTI_EMR_MR2_Pos   (2U)
     
    #define EXTI_EMR_MR2_Msk   (0x1UL << EXTI_EMR_MR2_Pos)
     
    #define EXTI_EMR_MR2   EXTI_EMR_MR2_Msk
     
    #define EXTI_EMR_MR3_Pos   (3U)
     
    #define EXTI_EMR_MR3_Msk   (0x1UL << EXTI_EMR_MR3_Pos)
     
    #define EXTI_EMR_MR3   EXTI_EMR_MR3_Msk
     
    #define EXTI_EMR_MR4_Pos   (4U)
     
    #define EXTI_EMR_MR4_Msk   (0x1UL << EXTI_EMR_MR4_Pos)
     
    #define EXTI_EMR_MR4   EXTI_EMR_MR4_Msk
     
    #define EXTI_EMR_MR5_Pos   (5U)
     
    #define EXTI_EMR_MR5_Msk   (0x1UL << EXTI_EMR_MR5_Pos)
     
    #define EXTI_EMR_MR5   EXTI_EMR_MR5_Msk
     
    #define EXTI_EMR_MR6_Pos   (6U)
     
    #define EXTI_EMR_MR6_Msk   (0x1UL << EXTI_EMR_MR6_Pos)
     
    #define EXTI_EMR_MR6   EXTI_EMR_MR6_Msk
     
    #define EXTI_EMR_MR7_Pos   (7U)
     
    #define EXTI_EMR_MR7_Msk   (0x1UL << EXTI_EMR_MR7_Pos)
     
    #define EXTI_EMR_MR7   EXTI_EMR_MR7_Msk
     
    #define EXTI_EMR_MR8_Pos   (8U)
     
    #define EXTI_EMR_MR8_Msk   (0x1UL << EXTI_EMR_MR8_Pos)
     
    #define EXTI_EMR_MR8   EXTI_EMR_MR8_Msk
     
    #define EXTI_EMR_MR9_Pos   (9U)
     
    #define EXTI_EMR_MR9_Msk   (0x1UL << EXTI_EMR_MR9_Pos)
     
    #define EXTI_EMR_MR9   EXTI_EMR_MR9_Msk
     
    #define EXTI_EMR_MR10_Pos   (10U)
     
    #define EXTI_EMR_MR10_Msk   (0x1UL << EXTI_EMR_MR10_Pos)
     
    #define EXTI_EMR_MR10   EXTI_EMR_MR10_Msk
     
    #define EXTI_EMR_MR11_Pos   (11U)
     
    #define EXTI_EMR_MR11_Msk   (0x1UL << EXTI_EMR_MR11_Pos)
     
    #define EXTI_EMR_MR11   EXTI_EMR_MR11_Msk
     
    #define EXTI_EMR_MR12_Pos   (12U)
     
    #define EXTI_EMR_MR12_Msk   (0x1UL << EXTI_EMR_MR12_Pos)
     
    #define EXTI_EMR_MR12   EXTI_EMR_MR12_Msk
     
    #define EXTI_EMR_MR13_Pos   (13U)
     
    #define EXTI_EMR_MR13_Msk   (0x1UL << EXTI_EMR_MR13_Pos)
     
    #define EXTI_EMR_MR13   EXTI_EMR_MR13_Msk
     
    #define EXTI_EMR_MR14_Pos   (14U)
     
    #define EXTI_EMR_MR14_Msk   (0x1UL << EXTI_EMR_MR14_Pos)
     
    #define EXTI_EMR_MR14   EXTI_EMR_MR14_Msk
     
    #define EXTI_EMR_MR15_Pos   (15U)
     
    #define EXTI_EMR_MR15_Msk   (0x1UL << EXTI_EMR_MR15_Pos)
     
    #define EXTI_EMR_MR15   EXTI_EMR_MR15_Msk
     
    #define EXTI_EMR_MR16_Pos   (16U)
     
    #define EXTI_EMR_MR16_Msk   (0x1UL << EXTI_EMR_MR16_Pos)
     
    #define EXTI_EMR_MR16   EXTI_EMR_MR16_Msk
     
    #define EXTI_EMR_MR17_Pos   (17U)
     
    #define EXTI_EMR_MR17_Msk   (0x1UL << EXTI_EMR_MR17_Pos)
     
    #define EXTI_EMR_MR17   EXTI_EMR_MR17_Msk
     
    #define EXTI_EMR_MR18_Pos   (18U)
     
    #define EXTI_EMR_MR18_Msk   (0x1UL << EXTI_EMR_MR18_Pos)
     
    #define EXTI_EMR_MR18   EXTI_EMR_MR18_Msk
     
    #define EXTI_EMR_MR19_Pos   (19U)
     
    #define EXTI_EMR_MR19_Msk   (0x1UL << EXTI_EMR_MR19_Pos)
     
    #define EXTI_EMR_MR19   EXTI_EMR_MR19_Msk
     
    #define EXTI_EMR_MR20_Pos   (20U)
     
    #define EXTI_EMR_MR20_Msk   (0x1UL << EXTI_EMR_MR20_Pos)
     
    #define EXTI_EMR_MR20   EXTI_EMR_MR20_Msk
     
    #define EXTI_EMR_MR21_Pos   (21U)
     
    #define EXTI_EMR_MR21_Msk   (0x1UL << EXTI_EMR_MR21_Pos)
     
    #define EXTI_EMR_MR21   EXTI_EMR_MR21_Msk
     
    #define EXTI_EMR_MR22_Pos   (22U)
     
    #define EXTI_EMR_MR22_Msk   (0x1UL << EXTI_EMR_MR22_Pos)
     
    #define EXTI_EMR_MR22   EXTI_EMR_MR22_Msk
     
    #define EXTI_EMR_EM0   EXTI_EMR_MR0
     
    #define EXTI_EMR_EM1   EXTI_EMR_MR1
     
    #define EXTI_EMR_EM2   EXTI_EMR_MR2
     
    #define EXTI_EMR_EM3   EXTI_EMR_MR3
     
    #define EXTI_EMR_EM4   EXTI_EMR_MR4
     
    #define EXTI_EMR_EM5   EXTI_EMR_MR5
     
    #define EXTI_EMR_EM6   EXTI_EMR_MR6
     
    #define EXTI_EMR_EM7   EXTI_EMR_MR7
     
    #define EXTI_EMR_EM8   EXTI_EMR_MR8
     
    #define EXTI_EMR_EM9   EXTI_EMR_MR9
     
    #define EXTI_EMR_EM10   EXTI_EMR_MR10
     
    #define EXTI_EMR_EM11   EXTI_EMR_MR11
     
    #define EXTI_EMR_EM12   EXTI_EMR_MR12
     
    #define EXTI_EMR_EM13   EXTI_EMR_MR13
     
    #define EXTI_EMR_EM14   EXTI_EMR_MR14
     
    #define EXTI_EMR_EM15   EXTI_EMR_MR15
     
    #define EXTI_EMR_EM16   EXTI_EMR_MR16
     
    #define EXTI_EMR_EM17   EXTI_EMR_MR17
     
    #define EXTI_EMR_EM18   EXTI_EMR_MR18
     
    #define EXTI_EMR_EM19   EXTI_EMR_MR19
     
    #define EXTI_EMR_EM20   EXTI_EMR_MR20
     
    #define EXTI_EMR_EM21   EXTI_EMR_MR21
     
    #define EXTI_EMR_EM22   EXTI_EMR_MR22
     
    #define EXTI_RTSR_TR0_Pos   (0U)
     
    #define EXTI_RTSR_TR0_Msk   (0x1UL << EXTI_RTSR_TR0_Pos)
     
    #define EXTI_RTSR_TR0   EXTI_RTSR_TR0_Msk
     
    #define EXTI_RTSR_TR1_Pos   (1U)
     
    #define EXTI_RTSR_TR1_Msk   (0x1UL << EXTI_RTSR_TR1_Pos)
     
    #define EXTI_RTSR_TR1   EXTI_RTSR_TR1_Msk
     
    #define EXTI_RTSR_TR2_Pos   (2U)
     
    #define EXTI_RTSR_TR2_Msk   (0x1UL << EXTI_RTSR_TR2_Pos)
     
    #define EXTI_RTSR_TR2   EXTI_RTSR_TR2_Msk
     
    #define EXTI_RTSR_TR3_Pos   (3U)
     
    #define EXTI_RTSR_TR3_Msk   (0x1UL << EXTI_RTSR_TR3_Pos)
     
    #define EXTI_RTSR_TR3   EXTI_RTSR_TR3_Msk
     
    #define EXTI_RTSR_TR4_Pos   (4U)
     
    #define EXTI_RTSR_TR4_Msk   (0x1UL << EXTI_RTSR_TR4_Pos)
     
    #define EXTI_RTSR_TR4   EXTI_RTSR_TR4_Msk
     
    #define EXTI_RTSR_TR5_Pos   (5U)
     
    #define EXTI_RTSR_TR5_Msk   (0x1UL << EXTI_RTSR_TR5_Pos)
     
    #define EXTI_RTSR_TR5   EXTI_RTSR_TR5_Msk
     
    #define EXTI_RTSR_TR6_Pos   (6U)
     
    #define EXTI_RTSR_TR6_Msk   (0x1UL << EXTI_RTSR_TR6_Pos)
     
    #define EXTI_RTSR_TR6   EXTI_RTSR_TR6_Msk
     
    #define EXTI_RTSR_TR7_Pos   (7U)
     
    #define EXTI_RTSR_TR7_Msk   (0x1UL << EXTI_RTSR_TR7_Pos)
     
    #define EXTI_RTSR_TR7   EXTI_RTSR_TR7_Msk
     
    #define EXTI_RTSR_TR8_Pos   (8U)
     
    #define EXTI_RTSR_TR8_Msk   (0x1UL << EXTI_RTSR_TR8_Pos)
     
    #define EXTI_RTSR_TR8   EXTI_RTSR_TR8_Msk
     
    #define EXTI_RTSR_TR9_Pos   (9U)
     
    #define EXTI_RTSR_TR9_Msk   (0x1UL << EXTI_RTSR_TR9_Pos)
     
    #define EXTI_RTSR_TR9   EXTI_RTSR_TR9_Msk
     
    #define EXTI_RTSR_TR10_Pos   (10U)
     
    #define EXTI_RTSR_TR10_Msk   (0x1UL << EXTI_RTSR_TR10_Pos)
     
    #define EXTI_RTSR_TR10   EXTI_RTSR_TR10_Msk
     
    #define EXTI_RTSR_TR11_Pos   (11U)
     
    #define EXTI_RTSR_TR11_Msk   (0x1UL << EXTI_RTSR_TR11_Pos)
     
    #define EXTI_RTSR_TR11   EXTI_RTSR_TR11_Msk
     
    #define EXTI_RTSR_TR12_Pos   (12U)
     
    #define EXTI_RTSR_TR12_Msk   (0x1UL << EXTI_RTSR_TR12_Pos)
     
    #define EXTI_RTSR_TR12   EXTI_RTSR_TR12_Msk
     
    #define EXTI_RTSR_TR13_Pos   (13U)
     
    #define EXTI_RTSR_TR13_Msk   (0x1UL << EXTI_RTSR_TR13_Pos)
     
    #define EXTI_RTSR_TR13   EXTI_RTSR_TR13_Msk
     
    #define EXTI_RTSR_TR14_Pos   (14U)
     
    #define EXTI_RTSR_TR14_Msk   (0x1UL << EXTI_RTSR_TR14_Pos)
     
    #define EXTI_RTSR_TR14   EXTI_RTSR_TR14_Msk
     
    #define EXTI_RTSR_TR15_Pos   (15U)
     
    #define EXTI_RTSR_TR15_Msk   (0x1UL << EXTI_RTSR_TR15_Pos)
     
    #define EXTI_RTSR_TR15   EXTI_RTSR_TR15_Msk
     
    #define EXTI_RTSR_TR16_Pos   (16U)
     
    #define EXTI_RTSR_TR16_Msk   (0x1UL << EXTI_RTSR_TR16_Pos)
     
    #define EXTI_RTSR_TR16   EXTI_RTSR_TR16_Msk
     
    #define EXTI_RTSR_TR17_Pos   (17U)
     
    #define EXTI_RTSR_TR17_Msk   (0x1UL << EXTI_RTSR_TR17_Pos)
     
    #define EXTI_RTSR_TR17   EXTI_RTSR_TR17_Msk
     
    #define EXTI_RTSR_TR18_Pos   (18U)
     
    #define EXTI_RTSR_TR18_Msk   (0x1UL << EXTI_RTSR_TR18_Pos)
     
    #define EXTI_RTSR_TR18   EXTI_RTSR_TR18_Msk
     
    #define EXTI_RTSR_TR19_Pos   (19U)
     
    #define EXTI_RTSR_TR19_Msk   (0x1UL << EXTI_RTSR_TR19_Pos)
     
    #define EXTI_RTSR_TR19   EXTI_RTSR_TR19_Msk
     
    #define EXTI_RTSR_TR20_Pos   (20U)
     
    #define EXTI_RTSR_TR20_Msk   (0x1UL << EXTI_RTSR_TR20_Pos)
     
    #define EXTI_RTSR_TR20   EXTI_RTSR_TR20_Msk
     
    #define EXTI_RTSR_TR21_Pos   (21U)
     
    #define EXTI_RTSR_TR21_Msk   (0x1UL << EXTI_RTSR_TR21_Pos)
     
    #define EXTI_RTSR_TR21   EXTI_RTSR_TR21_Msk
     
    #define EXTI_RTSR_TR22_Pos   (22U)
     
    #define EXTI_RTSR_TR22_Msk   (0x1UL << EXTI_RTSR_TR22_Pos)
     
    #define EXTI_RTSR_TR22   EXTI_RTSR_TR22_Msk
     
    #define EXTI_FTSR_TR0_Pos   (0U)
     
    #define EXTI_FTSR_TR0_Msk   (0x1UL << EXTI_FTSR_TR0_Pos)
     
    #define EXTI_FTSR_TR0   EXTI_FTSR_TR0_Msk
     
    #define EXTI_FTSR_TR1_Pos   (1U)
     
    #define EXTI_FTSR_TR1_Msk   (0x1UL << EXTI_FTSR_TR1_Pos)
     
    #define EXTI_FTSR_TR1   EXTI_FTSR_TR1_Msk
     
    #define EXTI_FTSR_TR2_Pos   (2U)
     
    #define EXTI_FTSR_TR2_Msk   (0x1UL << EXTI_FTSR_TR2_Pos)
     
    #define EXTI_FTSR_TR2   EXTI_FTSR_TR2_Msk
     
    #define EXTI_FTSR_TR3_Pos   (3U)
     
    #define EXTI_FTSR_TR3_Msk   (0x1UL << EXTI_FTSR_TR3_Pos)
     
    #define EXTI_FTSR_TR3   EXTI_FTSR_TR3_Msk
     
    #define EXTI_FTSR_TR4_Pos   (4U)
     
    #define EXTI_FTSR_TR4_Msk   (0x1UL << EXTI_FTSR_TR4_Pos)
     
    #define EXTI_FTSR_TR4   EXTI_FTSR_TR4_Msk
     
    #define EXTI_FTSR_TR5_Pos   (5U)
     
    #define EXTI_FTSR_TR5_Msk   (0x1UL << EXTI_FTSR_TR5_Pos)
     
    #define EXTI_FTSR_TR5   EXTI_FTSR_TR5_Msk
     
    #define EXTI_FTSR_TR6_Pos   (6U)
     
    #define EXTI_FTSR_TR6_Msk   (0x1UL << EXTI_FTSR_TR6_Pos)
     
    #define EXTI_FTSR_TR6   EXTI_FTSR_TR6_Msk
     
    #define EXTI_FTSR_TR7_Pos   (7U)
     
    #define EXTI_FTSR_TR7_Msk   (0x1UL << EXTI_FTSR_TR7_Pos)
     
    #define EXTI_FTSR_TR7   EXTI_FTSR_TR7_Msk
     
    #define EXTI_FTSR_TR8_Pos   (8U)
     
    #define EXTI_FTSR_TR8_Msk   (0x1UL << EXTI_FTSR_TR8_Pos)
     
    #define EXTI_FTSR_TR8   EXTI_FTSR_TR8_Msk
     
    #define EXTI_FTSR_TR9_Pos   (9U)
     
    #define EXTI_FTSR_TR9_Msk   (0x1UL << EXTI_FTSR_TR9_Pos)
     
    #define EXTI_FTSR_TR9   EXTI_FTSR_TR9_Msk
     
    #define EXTI_FTSR_TR10_Pos   (10U)
     
    #define EXTI_FTSR_TR10_Msk   (0x1UL << EXTI_FTSR_TR10_Pos)
     
    #define EXTI_FTSR_TR10   EXTI_FTSR_TR10_Msk
     
    #define EXTI_FTSR_TR11_Pos   (11U)
     
    #define EXTI_FTSR_TR11_Msk   (0x1UL << EXTI_FTSR_TR11_Pos)
     
    #define EXTI_FTSR_TR11   EXTI_FTSR_TR11_Msk
     
    #define EXTI_FTSR_TR12_Pos   (12U)
     
    #define EXTI_FTSR_TR12_Msk   (0x1UL << EXTI_FTSR_TR12_Pos)
     
    #define EXTI_FTSR_TR12   EXTI_FTSR_TR12_Msk
     
    #define EXTI_FTSR_TR13_Pos   (13U)
     
    #define EXTI_FTSR_TR13_Msk   (0x1UL << EXTI_FTSR_TR13_Pos)
     
    #define EXTI_FTSR_TR13   EXTI_FTSR_TR13_Msk
     
    #define EXTI_FTSR_TR14_Pos   (14U)
     
    #define EXTI_FTSR_TR14_Msk   (0x1UL << EXTI_FTSR_TR14_Pos)
     
    #define EXTI_FTSR_TR14   EXTI_FTSR_TR14_Msk
     
    #define EXTI_FTSR_TR15_Pos   (15U)
     
    #define EXTI_FTSR_TR15_Msk   (0x1UL << EXTI_FTSR_TR15_Pos)
     
    #define EXTI_FTSR_TR15   EXTI_FTSR_TR15_Msk
     
    #define EXTI_FTSR_TR16_Pos   (16U)
     
    #define EXTI_FTSR_TR16_Msk   (0x1UL << EXTI_FTSR_TR16_Pos)
     
    #define EXTI_FTSR_TR16   EXTI_FTSR_TR16_Msk
     
    #define EXTI_FTSR_TR17_Pos   (17U)
     
    #define EXTI_FTSR_TR17_Msk   (0x1UL << EXTI_FTSR_TR17_Pos)
     
    #define EXTI_FTSR_TR17   EXTI_FTSR_TR17_Msk
     
    #define EXTI_FTSR_TR18_Pos   (18U)
     
    #define EXTI_FTSR_TR18_Msk   (0x1UL << EXTI_FTSR_TR18_Pos)
     
    #define EXTI_FTSR_TR18   EXTI_FTSR_TR18_Msk
     
    #define EXTI_FTSR_TR19_Pos   (19U)
     
    #define EXTI_FTSR_TR19_Msk   (0x1UL << EXTI_FTSR_TR19_Pos)
     
    #define EXTI_FTSR_TR19   EXTI_FTSR_TR19_Msk
     
    #define EXTI_FTSR_TR20_Pos   (20U)
     
    #define EXTI_FTSR_TR20_Msk   (0x1UL << EXTI_FTSR_TR20_Pos)
     
    #define EXTI_FTSR_TR20   EXTI_FTSR_TR20_Msk
     
    #define EXTI_FTSR_TR21_Pos   (21U)
     
    #define EXTI_FTSR_TR21_Msk   (0x1UL << EXTI_FTSR_TR21_Pos)
     
    #define EXTI_FTSR_TR21   EXTI_FTSR_TR21_Msk
     
    #define EXTI_FTSR_TR22_Pos   (22U)
     
    #define EXTI_FTSR_TR22_Msk   (0x1UL << EXTI_FTSR_TR22_Pos)
     
    #define EXTI_FTSR_TR22   EXTI_FTSR_TR22_Msk
     
    #define EXTI_SWIER_SWIER0_Pos   (0U)
     
    #define EXTI_SWIER_SWIER0_Msk   (0x1UL << EXTI_SWIER_SWIER0_Pos)
     
    #define EXTI_SWIER_SWIER0   EXTI_SWIER_SWIER0_Msk
     
    #define EXTI_SWIER_SWIER1_Pos   (1U)
     
    #define EXTI_SWIER_SWIER1_Msk   (0x1UL << EXTI_SWIER_SWIER1_Pos)
     
    #define EXTI_SWIER_SWIER1   EXTI_SWIER_SWIER1_Msk
     
    #define EXTI_SWIER_SWIER2_Pos   (2U)
     
    #define EXTI_SWIER_SWIER2_Msk   (0x1UL << EXTI_SWIER_SWIER2_Pos)
     
    #define EXTI_SWIER_SWIER2   EXTI_SWIER_SWIER2_Msk
     
    #define EXTI_SWIER_SWIER3_Pos   (3U)
     
    #define EXTI_SWIER_SWIER3_Msk   (0x1UL << EXTI_SWIER_SWIER3_Pos)
     
    #define EXTI_SWIER_SWIER3   EXTI_SWIER_SWIER3_Msk
     
    #define EXTI_SWIER_SWIER4_Pos   (4U)
     
    #define EXTI_SWIER_SWIER4_Msk   (0x1UL << EXTI_SWIER_SWIER4_Pos)
     
    #define EXTI_SWIER_SWIER4   EXTI_SWIER_SWIER4_Msk
     
    #define EXTI_SWIER_SWIER5_Pos   (5U)
     
    #define EXTI_SWIER_SWIER5_Msk   (0x1UL << EXTI_SWIER_SWIER5_Pos)
     
    #define EXTI_SWIER_SWIER5   EXTI_SWIER_SWIER5_Msk
     
    #define EXTI_SWIER_SWIER6_Pos   (6U)
     
    #define EXTI_SWIER_SWIER6_Msk   (0x1UL << EXTI_SWIER_SWIER6_Pos)
     
    #define EXTI_SWIER_SWIER6   EXTI_SWIER_SWIER6_Msk
     
    #define EXTI_SWIER_SWIER7_Pos   (7U)
     
    #define EXTI_SWIER_SWIER7_Msk   (0x1UL << EXTI_SWIER_SWIER7_Pos)
     
    #define EXTI_SWIER_SWIER7   EXTI_SWIER_SWIER7_Msk
     
    #define EXTI_SWIER_SWIER8_Pos   (8U)
     
    #define EXTI_SWIER_SWIER8_Msk   (0x1UL << EXTI_SWIER_SWIER8_Pos)
     
    #define EXTI_SWIER_SWIER8   EXTI_SWIER_SWIER8_Msk
     
    #define EXTI_SWIER_SWIER9_Pos   (9U)
     
    #define EXTI_SWIER_SWIER9_Msk   (0x1UL << EXTI_SWIER_SWIER9_Pos)
     
    #define EXTI_SWIER_SWIER9   EXTI_SWIER_SWIER9_Msk
     
    #define EXTI_SWIER_SWIER10_Pos   (10U)
     
    #define EXTI_SWIER_SWIER10_Msk   (0x1UL << EXTI_SWIER_SWIER10_Pos)
     
    #define EXTI_SWIER_SWIER10   EXTI_SWIER_SWIER10_Msk
     
    #define EXTI_SWIER_SWIER11_Pos   (11U)
     
    #define EXTI_SWIER_SWIER11_Msk   (0x1UL << EXTI_SWIER_SWIER11_Pos)
     
    #define EXTI_SWIER_SWIER11   EXTI_SWIER_SWIER11_Msk
     
    #define EXTI_SWIER_SWIER12_Pos   (12U)
     
    #define EXTI_SWIER_SWIER12_Msk   (0x1UL << EXTI_SWIER_SWIER12_Pos)
     
    #define EXTI_SWIER_SWIER12   EXTI_SWIER_SWIER12_Msk
     
    #define EXTI_SWIER_SWIER13_Pos   (13U)
     
    #define EXTI_SWIER_SWIER13_Msk   (0x1UL << EXTI_SWIER_SWIER13_Pos)
     
    #define EXTI_SWIER_SWIER13   EXTI_SWIER_SWIER13_Msk
     
    #define EXTI_SWIER_SWIER14_Pos   (14U)
     
    #define EXTI_SWIER_SWIER14_Msk   (0x1UL << EXTI_SWIER_SWIER14_Pos)
     
    #define EXTI_SWIER_SWIER14   EXTI_SWIER_SWIER14_Msk
     
    #define EXTI_SWIER_SWIER15_Pos   (15U)
     
    #define EXTI_SWIER_SWIER15_Msk   (0x1UL << EXTI_SWIER_SWIER15_Pos)
     
    #define EXTI_SWIER_SWIER15   EXTI_SWIER_SWIER15_Msk
     
    #define EXTI_SWIER_SWIER16_Pos   (16U)
     
    #define EXTI_SWIER_SWIER16_Msk   (0x1UL << EXTI_SWIER_SWIER16_Pos)
     
    #define EXTI_SWIER_SWIER16   EXTI_SWIER_SWIER16_Msk
     
    #define EXTI_SWIER_SWIER17_Pos   (17U)
     
    #define EXTI_SWIER_SWIER17_Msk   (0x1UL << EXTI_SWIER_SWIER17_Pos)
     
    #define EXTI_SWIER_SWIER17   EXTI_SWIER_SWIER17_Msk
     
    #define EXTI_SWIER_SWIER18_Pos   (18U)
     
    #define EXTI_SWIER_SWIER18_Msk   (0x1UL << EXTI_SWIER_SWIER18_Pos)
     
    #define EXTI_SWIER_SWIER18   EXTI_SWIER_SWIER18_Msk
     
    #define EXTI_SWIER_SWIER19_Pos   (19U)
     
    #define EXTI_SWIER_SWIER19_Msk   (0x1UL << EXTI_SWIER_SWIER19_Pos)
     
    #define EXTI_SWIER_SWIER19   EXTI_SWIER_SWIER19_Msk
     
    #define EXTI_SWIER_SWIER20_Pos   (20U)
     
    #define EXTI_SWIER_SWIER20_Msk   (0x1UL << EXTI_SWIER_SWIER20_Pos)
     
    #define EXTI_SWIER_SWIER20   EXTI_SWIER_SWIER20_Msk
     
    #define EXTI_SWIER_SWIER21_Pos   (21U)
     
    #define EXTI_SWIER_SWIER21_Msk   (0x1UL << EXTI_SWIER_SWIER21_Pos)
     
    #define EXTI_SWIER_SWIER21   EXTI_SWIER_SWIER21_Msk
     
    #define EXTI_SWIER_SWIER22_Pos   (22U)
     
    #define EXTI_SWIER_SWIER22_Msk   (0x1UL << EXTI_SWIER_SWIER22_Pos)
     
    #define EXTI_SWIER_SWIER22   EXTI_SWIER_SWIER22_Msk
     
    #define EXTI_PR_PR0_Pos   (0U)
     
    #define EXTI_PR_PR0_Msk   (0x1UL << EXTI_PR_PR0_Pos)
     
    #define EXTI_PR_PR0   EXTI_PR_PR0_Msk
     
    #define EXTI_PR_PR1_Pos   (1U)
     
    #define EXTI_PR_PR1_Msk   (0x1UL << EXTI_PR_PR1_Pos)
     
    #define EXTI_PR_PR1   EXTI_PR_PR1_Msk
     
    #define EXTI_PR_PR2_Pos   (2U)
     
    #define EXTI_PR_PR2_Msk   (0x1UL << EXTI_PR_PR2_Pos)
     
    #define EXTI_PR_PR2   EXTI_PR_PR2_Msk
     
    #define EXTI_PR_PR3_Pos   (3U)
     
    #define EXTI_PR_PR3_Msk   (0x1UL << EXTI_PR_PR3_Pos)
     
    #define EXTI_PR_PR3   EXTI_PR_PR3_Msk
     
    #define EXTI_PR_PR4_Pos   (4U)
     
    #define EXTI_PR_PR4_Msk   (0x1UL << EXTI_PR_PR4_Pos)
     
    #define EXTI_PR_PR4   EXTI_PR_PR4_Msk
     
    #define EXTI_PR_PR5_Pos   (5U)
     
    #define EXTI_PR_PR5_Msk   (0x1UL << EXTI_PR_PR5_Pos)
     
    #define EXTI_PR_PR5   EXTI_PR_PR5_Msk
     
    #define EXTI_PR_PR6_Pos   (6U)
     
    #define EXTI_PR_PR6_Msk   (0x1UL << EXTI_PR_PR6_Pos)
     
    #define EXTI_PR_PR6   EXTI_PR_PR6_Msk
     
    #define EXTI_PR_PR7_Pos   (7U)
     
    #define EXTI_PR_PR7_Msk   (0x1UL << EXTI_PR_PR7_Pos)
     
    #define EXTI_PR_PR7   EXTI_PR_PR7_Msk
     
    #define EXTI_PR_PR8_Pos   (8U)
     
    #define EXTI_PR_PR8_Msk   (0x1UL << EXTI_PR_PR8_Pos)
     
    #define EXTI_PR_PR8   EXTI_PR_PR8_Msk
     
    #define EXTI_PR_PR9_Pos   (9U)
     
    #define EXTI_PR_PR9_Msk   (0x1UL << EXTI_PR_PR9_Pos)
     
    #define EXTI_PR_PR9   EXTI_PR_PR9_Msk
     
    #define EXTI_PR_PR10_Pos   (10U)
     
    #define EXTI_PR_PR10_Msk   (0x1UL << EXTI_PR_PR10_Pos)
     
    #define EXTI_PR_PR10   EXTI_PR_PR10_Msk
     
    #define EXTI_PR_PR11_Pos   (11U)
     
    #define EXTI_PR_PR11_Msk   (0x1UL << EXTI_PR_PR11_Pos)
     
    #define EXTI_PR_PR11   EXTI_PR_PR11_Msk
     
    #define EXTI_PR_PR12_Pos   (12U)
     
    #define EXTI_PR_PR12_Msk   (0x1UL << EXTI_PR_PR12_Pos)
     
    #define EXTI_PR_PR12   EXTI_PR_PR12_Msk
     
    #define EXTI_PR_PR13_Pos   (13U)
     
    #define EXTI_PR_PR13_Msk   (0x1UL << EXTI_PR_PR13_Pos)
     
    #define EXTI_PR_PR13   EXTI_PR_PR13_Msk
     
    #define EXTI_PR_PR14_Pos   (14U)
     
    #define EXTI_PR_PR14_Msk   (0x1UL << EXTI_PR_PR14_Pos)
     
    #define EXTI_PR_PR14   EXTI_PR_PR14_Msk
     
    #define EXTI_PR_PR15_Pos   (15U)
     
    #define EXTI_PR_PR15_Msk   (0x1UL << EXTI_PR_PR15_Pos)
     
    #define EXTI_PR_PR15   EXTI_PR_PR15_Msk
     
    #define EXTI_PR_PR16_Pos   (16U)
     
    #define EXTI_PR_PR16_Msk   (0x1UL << EXTI_PR_PR16_Pos)
     
    #define EXTI_PR_PR16   EXTI_PR_PR16_Msk
     
    #define EXTI_PR_PR17_Pos   (17U)
     
    #define EXTI_PR_PR17_Msk   (0x1UL << EXTI_PR_PR17_Pos)
     
    #define EXTI_PR_PR17   EXTI_PR_PR17_Msk
     
    #define EXTI_PR_PR18_Pos   (18U)
     
    #define EXTI_PR_PR18_Msk   (0x1UL << EXTI_PR_PR18_Pos)
     
    #define EXTI_PR_PR18   EXTI_PR_PR18_Msk
     
    #define EXTI_PR_PR19_Pos   (19U)
     
    #define EXTI_PR_PR19_Msk   (0x1UL << EXTI_PR_PR19_Pos)
     
    #define EXTI_PR_PR19   EXTI_PR_PR19_Msk
     
    #define EXTI_PR_PR20_Pos   (20U)
     
    #define EXTI_PR_PR20_Msk   (0x1UL << EXTI_PR_PR20_Pos)
     
    #define EXTI_PR_PR20   EXTI_PR_PR20_Msk
     
    #define EXTI_PR_PR21_Pos   (21U)
     
    #define EXTI_PR_PR21_Msk   (0x1UL << EXTI_PR_PR21_Pos)
     
    #define EXTI_PR_PR21   EXTI_PR_PR21_Msk
     
    #define EXTI_PR_PR22_Pos   (22U)
     
    #define EXTI_PR_PR22_Msk   (0x1UL << EXTI_PR_PR22_Pos)
     
    #define EXTI_PR_PR22   EXTI_PR_PR22_Msk
     
    #define FLASH_ACR_LATENCY_Pos   (0U)
     
    #define FLASH_ACR_LATENCY_Msk   (0x7UL << FLASH_ACR_LATENCY_Pos)
     
    #define FLASH_ACR_LATENCY   FLASH_ACR_LATENCY_Msk
     
    #define FLASH_ACR_LATENCY_0WS   0x00000000U
     
    #define FLASH_ACR_LATENCY_1WS   0x00000001U
     
    #define FLASH_ACR_LATENCY_2WS   0x00000002U
     
    #define FLASH_ACR_LATENCY_3WS   0x00000003U
     
    #define FLASH_ACR_LATENCY_4WS   0x00000004U
     
    #define FLASH_ACR_LATENCY_5WS   0x00000005U
     
    #define FLASH_ACR_LATENCY_6WS   0x00000006U
     
    #define FLASH_ACR_LATENCY_7WS   0x00000007U
     
    #define FLASH_ACR_PRFTEN_Pos   (8U)
     
    #define FLASH_ACR_PRFTEN_Msk   (0x1UL << FLASH_ACR_PRFTEN_Pos)
     
    #define FLASH_ACR_PRFTEN   FLASH_ACR_PRFTEN_Msk
     
    #define FLASH_ACR_ICEN_Pos   (9U)
     
    #define FLASH_ACR_ICEN_Msk   (0x1UL << FLASH_ACR_ICEN_Pos)
     
    #define FLASH_ACR_ICEN   FLASH_ACR_ICEN_Msk
     
    #define FLASH_ACR_DCEN_Pos   (10U)
     
    #define FLASH_ACR_DCEN_Msk   (0x1UL << FLASH_ACR_DCEN_Pos)
     
    #define FLASH_ACR_DCEN   FLASH_ACR_DCEN_Msk
     
    #define FLASH_ACR_ICRST_Pos   (11U)
     
    #define FLASH_ACR_ICRST_Msk   (0x1UL << FLASH_ACR_ICRST_Pos)
     
    #define FLASH_ACR_ICRST   FLASH_ACR_ICRST_Msk
     
    #define FLASH_ACR_DCRST_Pos   (12U)
     
    #define FLASH_ACR_DCRST_Msk   (0x1UL << FLASH_ACR_DCRST_Pos)
     
    #define FLASH_ACR_DCRST   FLASH_ACR_DCRST_Msk
     
    #define FLASH_ACR_BYTE0_ADDRESS_Pos   (10U)
     
    #define FLASH_ACR_BYTE0_ADDRESS_Msk   (0x10008FUL << FLASH_ACR_BYTE0_ADDRESS_Pos)
     
    #define FLASH_ACR_BYTE0_ADDRESS   FLASH_ACR_BYTE0_ADDRESS_Msk
     
    #define FLASH_ACR_BYTE2_ADDRESS_Pos   (0U)
     
    #define FLASH_ACR_BYTE2_ADDRESS_Msk   (0x40023C03UL << FLASH_ACR_BYTE2_ADDRESS_Pos)
     
    #define FLASH_ACR_BYTE2_ADDRESS   FLASH_ACR_BYTE2_ADDRESS_Msk
     
    #define FLASH_SR_EOP_Pos   (0U)
     
    #define FLASH_SR_EOP_Msk   (0x1UL << FLASH_SR_EOP_Pos)
     
    #define FLASH_SR_EOP   FLASH_SR_EOP_Msk
     
    #define FLASH_SR_SOP_Pos   (1U)
     
    #define FLASH_SR_SOP_Msk   (0x1UL << FLASH_SR_SOP_Pos)
     
    #define FLASH_SR_SOP   FLASH_SR_SOP_Msk
     
    #define FLASH_SR_WRPERR_Pos   (4U)
     
    #define FLASH_SR_WRPERR_Msk   (0x1UL << FLASH_SR_WRPERR_Pos)
     
    #define FLASH_SR_WRPERR   FLASH_SR_WRPERR_Msk
     
    #define FLASH_SR_PGAERR_Pos   (5U)
     
    #define FLASH_SR_PGAERR_Msk   (0x1UL << FLASH_SR_PGAERR_Pos)
     
    #define FLASH_SR_PGAERR   FLASH_SR_PGAERR_Msk
     
    #define FLASH_SR_PGPERR_Pos   (6U)
     
    #define FLASH_SR_PGPERR_Msk   (0x1UL << FLASH_SR_PGPERR_Pos)
     
    #define FLASH_SR_PGPERR   FLASH_SR_PGPERR_Msk
     
    #define FLASH_SR_PGSERR_Pos   (7U)
     
    #define FLASH_SR_PGSERR_Msk   (0x1UL << FLASH_SR_PGSERR_Pos)
     
    #define FLASH_SR_PGSERR   FLASH_SR_PGSERR_Msk
     
    #define FLASH_SR_BSY_Pos   (16U)
     
    #define FLASH_SR_BSY_Msk   (0x1UL << FLASH_SR_BSY_Pos)
     
    #define FLASH_SR_BSY   FLASH_SR_BSY_Msk
     
    #define FLASH_CR_PG_Pos   (0U)
     
    #define FLASH_CR_PG_Msk   (0x1UL << FLASH_CR_PG_Pos)
     
    #define FLASH_CR_PG   FLASH_CR_PG_Msk
     
    #define FLASH_CR_SER_Pos   (1U)
     
    #define FLASH_CR_SER_Msk   (0x1UL << FLASH_CR_SER_Pos)
     
    #define FLASH_CR_SER   FLASH_CR_SER_Msk
     
    #define FLASH_CR_MER_Pos   (2U)
     
    #define FLASH_CR_MER_Msk   (0x1UL << FLASH_CR_MER_Pos)
     
    #define FLASH_CR_MER   FLASH_CR_MER_Msk
     
    #define FLASH_CR_SNB_Pos   (3U)
     
    #define FLASH_CR_SNB_Msk   (0x1FUL << FLASH_CR_SNB_Pos)
     
    #define FLASH_CR_SNB   FLASH_CR_SNB_Msk
     
    #define FLASH_CR_SNB_0   (0x01UL << FLASH_CR_SNB_Pos)
     
    #define FLASH_CR_SNB_1   (0x02UL << FLASH_CR_SNB_Pos)
     
    #define FLASH_CR_SNB_2   (0x04UL << FLASH_CR_SNB_Pos)
     
    #define FLASH_CR_SNB_3   (0x08UL << FLASH_CR_SNB_Pos)
     
    #define FLASH_CR_SNB_4   (0x10UL << FLASH_CR_SNB_Pos)
     
    #define FLASH_CR_PSIZE_Pos   (8U)
     
    #define FLASH_CR_PSIZE_Msk   (0x3UL << FLASH_CR_PSIZE_Pos)
     
    #define FLASH_CR_PSIZE   FLASH_CR_PSIZE_Msk
     
    #define FLASH_CR_PSIZE_0   (0x1UL << FLASH_CR_PSIZE_Pos)
     
    #define FLASH_CR_PSIZE_1   (0x2UL << FLASH_CR_PSIZE_Pos)
     
    #define FLASH_CR_STRT_Pos   (16U)
     
    #define FLASH_CR_STRT_Msk   (0x1UL << FLASH_CR_STRT_Pos)
     
    #define FLASH_CR_STRT   FLASH_CR_STRT_Msk
     
    #define FLASH_CR_EOPIE_Pos   (24U)
     
    #define FLASH_CR_EOPIE_Msk   (0x1UL << FLASH_CR_EOPIE_Pos)
     
    #define FLASH_CR_EOPIE   FLASH_CR_EOPIE_Msk
     
    #define FLASH_CR_ERRIE_Pos   (25U)
     
    #define FLASH_CR_ERRIE_Msk   (0x1UL << FLASH_CR_ERRIE_Pos)
     
    #define FLASH_CR_ERRIE   FLASH_CR_ERRIE_Msk
     
    #define FLASH_CR_LOCK_Pos   (31U)
     
    #define FLASH_CR_LOCK_Msk   (0x1UL << FLASH_CR_LOCK_Pos)
     
    #define FLASH_CR_LOCK   FLASH_CR_LOCK_Msk
     
    #define FLASH_OPTCR_OPTLOCK_Pos   (0U)
     
    #define FLASH_OPTCR_OPTLOCK_Msk   (0x1UL << FLASH_OPTCR_OPTLOCK_Pos)
     
    #define FLASH_OPTCR_OPTLOCK   FLASH_OPTCR_OPTLOCK_Msk
     
    #define FLASH_OPTCR_OPTSTRT_Pos   (1U)
     
    #define FLASH_OPTCR_OPTSTRT_Msk   (0x1UL << FLASH_OPTCR_OPTSTRT_Pos)
     
    #define FLASH_OPTCR_OPTSTRT   FLASH_OPTCR_OPTSTRT_Msk
     
    #define FLASH_OPTCR_BOR_LEV_0   0x00000004U
     
    #define FLASH_OPTCR_BOR_LEV_1   0x00000008U
     
    #define FLASH_OPTCR_BOR_LEV_Pos   (2U)
     
    #define FLASH_OPTCR_BOR_LEV_Msk   (0x3UL << FLASH_OPTCR_BOR_LEV_Pos)
     
    #define FLASH_OPTCR_BOR_LEV   FLASH_OPTCR_BOR_LEV_Msk
     
    #define FLASH_OPTCR_WDG_SW_Pos   (5U)
     
    #define FLASH_OPTCR_WDG_SW_Msk   (0x1UL << FLASH_OPTCR_WDG_SW_Pos)
     
    #define FLASH_OPTCR_WDG_SW   FLASH_OPTCR_WDG_SW_Msk
     
    #define FLASH_OPTCR_nRST_STOP_Pos   (6U)
     
    #define FLASH_OPTCR_nRST_STOP_Msk   (0x1UL << FLASH_OPTCR_nRST_STOP_Pos)
     
    #define FLASH_OPTCR_nRST_STOP   FLASH_OPTCR_nRST_STOP_Msk
     
    #define FLASH_OPTCR_nRST_STDBY_Pos   (7U)
     
    #define FLASH_OPTCR_nRST_STDBY_Msk   (0x1UL << FLASH_OPTCR_nRST_STDBY_Pos)
     
    #define FLASH_OPTCR_nRST_STDBY   FLASH_OPTCR_nRST_STDBY_Msk
     
    #define FLASH_OPTCR_RDP_Pos   (8U)
     
    #define FLASH_OPTCR_RDP_Msk   (0xFFUL << FLASH_OPTCR_RDP_Pos)
     
    #define FLASH_OPTCR_RDP   FLASH_OPTCR_RDP_Msk
     
    #define FLASH_OPTCR_RDP_0   (0x01UL << FLASH_OPTCR_RDP_Pos)
     
    #define FLASH_OPTCR_RDP_1   (0x02UL << FLASH_OPTCR_RDP_Pos)
     
    #define FLASH_OPTCR_RDP_2   (0x04UL << FLASH_OPTCR_RDP_Pos)
     
    #define FLASH_OPTCR_RDP_3   (0x08UL << FLASH_OPTCR_RDP_Pos)
     
    #define FLASH_OPTCR_RDP_4   (0x10UL << FLASH_OPTCR_RDP_Pos)
     
    #define FLASH_OPTCR_RDP_5   (0x20UL << FLASH_OPTCR_RDP_Pos)
     
    #define FLASH_OPTCR_RDP_6   (0x40UL << FLASH_OPTCR_RDP_Pos)
     
    #define FLASH_OPTCR_RDP_7   (0x80UL << FLASH_OPTCR_RDP_Pos)
     
    #define FLASH_OPTCR_nWRP_Pos   (16U)
     
    #define FLASH_OPTCR_nWRP_Msk   (0xFFFUL << FLASH_OPTCR_nWRP_Pos)
     
    #define FLASH_OPTCR_nWRP   FLASH_OPTCR_nWRP_Msk
     
    #define FLASH_OPTCR_nWRP_0   0x00010000U
     
    #define FLASH_OPTCR_nWRP_1   0x00020000U
     
    #define FLASH_OPTCR_nWRP_2   0x00040000U
     
    #define FLASH_OPTCR_nWRP_3   0x00080000U
     
    #define FLASH_OPTCR_nWRP_4   0x00100000U
     
    #define FLASH_OPTCR_nWRP_5   0x00200000U
     
    #define FLASH_OPTCR_nWRP_6   0x00400000U
     
    #define FLASH_OPTCR_nWRP_7   0x00800000U
     
    #define FLASH_OPTCR_nWRP_8   0x01000000U
     
    #define FLASH_OPTCR_nWRP_9   0x02000000U
     
    #define FLASH_OPTCR_nWRP_10   0x04000000U
     
    #define FLASH_OPTCR_nWRP_11   0x08000000U
     
    #define FLASH_OPTCR1_nWRP_Pos   (16U)
     
    #define FLASH_OPTCR1_nWRP_Msk   (0xFFFUL << FLASH_OPTCR1_nWRP_Pos)
     
    #define FLASH_OPTCR1_nWRP   FLASH_OPTCR1_nWRP_Msk
     
    #define FLASH_OPTCR1_nWRP_0   (0x001UL << FLASH_OPTCR1_nWRP_Pos)
     
    #define FLASH_OPTCR1_nWRP_1   (0x002UL << FLASH_OPTCR1_nWRP_Pos)
     
    #define FLASH_OPTCR1_nWRP_2   (0x004UL << FLASH_OPTCR1_nWRP_Pos)
     
    #define FLASH_OPTCR1_nWRP_3   (0x008UL << FLASH_OPTCR1_nWRP_Pos)
     
    #define FLASH_OPTCR1_nWRP_4   (0x010UL << FLASH_OPTCR1_nWRP_Pos)
     
    #define FLASH_OPTCR1_nWRP_5   (0x020UL << FLASH_OPTCR1_nWRP_Pos)
     
    #define FLASH_OPTCR1_nWRP_6   (0x040UL << FLASH_OPTCR1_nWRP_Pos)
     
    #define FLASH_OPTCR1_nWRP_7   (0x080UL << FLASH_OPTCR1_nWRP_Pos)
     
    #define FLASH_OPTCR1_nWRP_8   (0x100UL << FLASH_OPTCR1_nWRP_Pos)
     
    #define FLASH_OPTCR1_nWRP_9   (0x200UL << FLASH_OPTCR1_nWRP_Pos)
     
    #define FLASH_OPTCR1_nWRP_10   (0x400UL << FLASH_OPTCR1_nWRP_Pos)
     
    #define FLASH_OPTCR1_nWRP_11   (0x800UL << FLASH_OPTCR1_nWRP_Pos)
     
    #define FSMC_BCR1_MBKEN_Pos   (0U)
     
    #define FSMC_BCR1_MBKEN_Msk   (0x1UL << FSMC_BCR1_MBKEN_Pos)
     
    #define FSMC_BCR1_MBKEN   FSMC_BCR1_MBKEN_Msk
     
    #define FSMC_BCR1_MUXEN_Pos   (1U)
     
    #define FSMC_BCR1_MUXEN_Msk   (0x1UL << FSMC_BCR1_MUXEN_Pos)
     
    #define FSMC_BCR1_MUXEN   FSMC_BCR1_MUXEN_Msk
     
    #define FSMC_BCR1_MTYP_Pos   (2U)
     
    #define FSMC_BCR1_MTYP_Msk   (0x3UL << FSMC_BCR1_MTYP_Pos)
     
    #define FSMC_BCR1_MTYP   FSMC_BCR1_MTYP_Msk
     
    #define FSMC_BCR1_MTYP_0   (0x1UL << FSMC_BCR1_MTYP_Pos)
     
    #define FSMC_BCR1_MTYP_1   (0x2UL << FSMC_BCR1_MTYP_Pos)
     
    #define FSMC_BCR1_MWID_Pos   (4U)
     
    #define FSMC_BCR1_MWID_Msk   (0x3UL << FSMC_BCR1_MWID_Pos)
     
    #define FSMC_BCR1_MWID   FSMC_BCR1_MWID_Msk
     
    #define FSMC_BCR1_MWID_0   (0x1UL << FSMC_BCR1_MWID_Pos)
     
    #define FSMC_BCR1_MWID_1   (0x2UL << FSMC_BCR1_MWID_Pos)
     
    #define FSMC_BCR1_FACCEN_Pos   (6U)
     
    #define FSMC_BCR1_FACCEN_Msk   (0x1UL << FSMC_BCR1_FACCEN_Pos)
     
    #define FSMC_BCR1_FACCEN   FSMC_BCR1_FACCEN_Msk
     
    #define FSMC_BCR1_BURSTEN_Pos   (8U)
     
    #define FSMC_BCR1_BURSTEN_Msk   (0x1UL << FSMC_BCR1_BURSTEN_Pos)
     
    #define FSMC_BCR1_BURSTEN   FSMC_BCR1_BURSTEN_Msk
     
    #define FSMC_BCR1_WAITPOL_Pos   (9U)
     
    #define FSMC_BCR1_WAITPOL_Msk   (0x1UL << FSMC_BCR1_WAITPOL_Pos)
     
    #define FSMC_BCR1_WAITPOL   FSMC_BCR1_WAITPOL_Msk
     
    #define FSMC_BCR1_WRAPMOD_Pos   (10U)
     
    #define FSMC_BCR1_WRAPMOD_Msk   (0x1UL << FSMC_BCR1_WRAPMOD_Pos)
     
    #define FSMC_BCR1_WRAPMOD   FSMC_BCR1_WRAPMOD_Msk
     
    #define FSMC_BCR1_WAITCFG_Pos   (11U)
     
    #define FSMC_BCR1_WAITCFG_Msk   (0x1UL << FSMC_BCR1_WAITCFG_Pos)
     
    #define FSMC_BCR1_WAITCFG   FSMC_BCR1_WAITCFG_Msk
     
    #define FSMC_BCR1_WREN_Pos   (12U)
     
    #define FSMC_BCR1_WREN_Msk   (0x1UL << FSMC_BCR1_WREN_Pos)
     
    #define FSMC_BCR1_WREN   FSMC_BCR1_WREN_Msk
     
    #define FSMC_BCR1_WAITEN_Pos   (13U)
     
    #define FSMC_BCR1_WAITEN_Msk   (0x1UL << FSMC_BCR1_WAITEN_Pos)
     
    #define FSMC_BCR1_WAITEN   FSMC_BCR1_WAITEN_Msk
     
    #define FSMC_BCR1_EXTMOD_Pos   (14U)
     
    #define FSMC_BCR1_EXTMOD_Msk   (0x1UL << FSMC_BCR1_EXTMOD_Pos)
     
    #define FSMC_BCR1_EXTMOD   FSMC_BCR1_EXTMOD_Msk
     
    #define FSMC_BCR1_ASYNCWAIT_Pos   (15U)
     
    #define FSMC_BCR1_ASYNCWAIT_Msk   (0x1UL << FSMC_BCR1_ASYNCWAIT_Pos)
     
    #define FSMC_BCR1_ASYNCWAIT   FSMC_BCR1_ASYNCWAIT_Msk
     
    #define FSMC_BCR1_CPSIZE_Pos   (16U)
     
    #define FSMC_BCR1_CPSIZE_Msk   (0x7UL << FSMC_BCR1_CPSIZE_Pos)
     
    #define FSMC_BCR1_CPSIZE   FSMC_BCR1_CPSIZE_Msk
     
    #define FSMC_BCR1_CPSIZE_0   (0x1UL << FSMC_BCR1_CPSIZE_Pos)
     
    #define FSMC_BCR1_CPSIZE_1   (0x2UL << FSMC_BCR1_CPSIZE_Pos)
     
    #define FSMC_BCR1_CPSIZE_2   (0x4UL << FSMC_BCR1_CPSIZE_Pos)
     
    #define FSMC_BCR1_CBURSTRW_Pos   (19U)
     
    #define FSMC_BCR1_CBURSTRW_Msk   (0x1UL << FSMC_BCR1_CBURSTRW_Pos)
     
    #define FSMC_BCR1_CBURSTRW   FSMC_BCR1_CBURSTRW_Msk
     
    #define FSMC_BCR2_MBKEN_Pos   (0U)
     
    #define FSMC_BCR2_MBKEN_Msk   (0x1UL << FSMC_BCR2_MBKEN_Pos)
     
    #define FSMC_BCR2_MBKEN   FSMC_BCR2_MBKEN_Msk
     
    #define FSMC_BCR2_MUXEN_Pos   (1U)
     
    #define FSMC_BCR2_MUXEN_Msk   (0x1UL << FSMC_BCR2_MUXEN_Pos)
     
    #define FSMC_BCR2_MUXEN   FSMC_BCR2_MUXEN_Msk
     
    #define FSMC_BCR2_MTYP_Pos   (2U)
     
    #define FSMC_BCR2_MTYP_Msk   (0x3UL << FSMC_BCR2_MTYP_Pos)
     
    #define FSMC_BCR2_MTYP   FSMC_BCR2_MTYP_Msk
     
    #define FSMC_BCR2_MTYP_0   (0x1UL << FSMC_BCR2_MTYP_Pos)
     
    #define FSMC_BCR2_MTYP_1   (0x2UL << FSMC_BCR2_MTYP_Pos)
     
    #define FSMC_BCR2_MWID_Pos   (4U)
     
    #define FSMC_BCR2_MWID_Msk   (0x3UL << FSMC_BCR2_MWID_Pos)
     
    #define FSMC_BCR2_MWID   FSMC_BCR2_MWID_Msk
     
    #define FSMC_BCR2_MWID_0   (0x1UL << FSMC_BCR2_MWID_Pos)
     
    #define FSMC_BCR2_MWID_1   (0x2UL << FSMC_BCR2_MWID_Pos)
     
    #define FSMC_BCR2_FACCEN_Pos   (6U)
     
    #define FSMC_BCR2_FACCEN_Msk   (0x1UL << FSMC_BCR2_FACCEN_Pos)
     
    #define FSMC_BCR2_FACCEN   FSMC_BCR2_FACCEN_Msk
     
    #define FSMC_BCR2_BURSTEN_Pos   (8U)
     
    #define FSMC_BCR2_BURSTEN_Msk   (0x1UL << FSMC_BCR2_BURSTEN_Pos)
     
    #define FSMC_BCR2_BURSTEN   FSMC_BCR2_BURSTEN_Msk
     
    #define FSMC_BCR2_WAITPOL_Pos   (9U)
     
    #define FSMC_BCR2_WAITPOL_Msk   (0x1UL << FSMC_BCR2_WAITPOL_Pos)
     
    #define FSMC_BCR2_WAITPOL   FSMC_BCR2_WAITPOL_Msk
     
    #define FSMC_BCR2_WRAPMOD_Pos   (10U)
     
    #define FSMC_BCR2_WRAPMOD_Msk   (0x1UL << FSMC_BCR2_WRAPMOD_Pos)
     
    #define FSMC_BCR2_WRAPMOD   FSMC_BCR2_WRAPMOD_Msk
     
    #define FSMC_BCR2_WAITCFG_Pos   (11U)
     
    #define FSMC_BCR2_WAITCFG_Msk   (0x1UL << FSMC_BCR2_WAITCFG_Pos)
     
    #define FSMC_BCR2_WAITCFG   FSMC_BCR2_WAITCFG_Msk
     
    #define FSMC_BCR2_WREN_Pos   (12U)
     
    #define FSMC_BCR2_WREN_Msk   (0x1UL << FSMC_BCR2_WREN_Pos)
     
    #define FSMC_BCR2_WREN   FSMC_BCR2_WREN_Msk
     
    #define FSMC_BCR2_WAITEN_Pos   (13U)
     
    #define FSMC_BCR2_WAITEN_Msk   (0x1UL << FSMC_BCR2_WAITEN_Pos)
     
    #define FSMC_BCR2_WAITEN   FSMC_BCR2_WAITEN_Msk
     
    #define FSMC_BCR2_EXTMOD_Pos   (14U)
     
    #define FSMC_BCR2_EXTMOD_Msk   (0x1UL << FSMC_BCR2_EXTMOD_Pos)
     
    #define FSMC_BCR2_EXTMOD   FSMC_BCR2_EXTMOD_Msk
     
    #define FSMC_BCR2_ASYNCWAIT_Pos   (15U)
     
    #define FSMC_BCR2_ASYNCWAIT_Msk   (0x1UL << FSMC_BCR2_ASYNCWAIT_Pos)
     
    #define FSMC_BCR2_ASYNCWAIT   FSMC_BCR2_ASYNCWAIT_Msk
     
    #define FSMC_BCR2_CPSIZE_Pos   (16U)
     
    #define FSMC_BCR2_CPSIZE_Msk   (0x7UL << FSMC_BCR2_CPSIZE_Pos)
     
    #define FSMC_BCR2_CPSIZE   FSMC_BCR2_CPSIZE_Msk
     
    #define FSMC_BCR2_CPSIZE_0   (0x1UL << FSMC_BCR2_CPSIZE_Pos)
     
    #define FSMC_BCR2_CPSIZE_1   (0x2UL << FSMC_BCR2_CPSIZE_Pos)
     
    #define FSMC_BCR2_CPSIZE_2   (0x4UL << FSMC_BCR2_CPSIZE_Pos)
     
    #define FSMC_BCR2_CBURSTRW_Pos   (19U)
     
    #define FSMC_BCR2_CBURSTRW_Msk   (0x1UL << FSMC_BCR2_CBURSTRW_Pos)
     
    #define FSMC_BCR2_CBURSTRW   FSMC_BCR2_CBURSTRW_Msk
     
    #define FSMC_BCR3_MBKEN_Pos   (0U)
     
    #define FSMC_BCR3_MBKEN_Msk   (0x1UL << FSMC_BCR3_MBKEN_Pos)
     
    #define FSMC_BCR3_MBKEN   FSMC_BCR3_MBKEN_Msk
     
    #define FSMC_BCR3_MUXEN_Pos   (1U)
     
    #define FSMC_BCR3_MUXEN_Msk   (0x1UL << FSMC_BCR3_MUXEN_Pos)
     
    #define FSMC_BCR3_MUXEN   FSMC_BCR3_MUXEN_Msk
     
    #define FSMC_BCR3_MTYP_Pos   (2U)
     
    #define FSMC_BCR3_MTYP_Msk   (0x3UL << FSMC_BCR3_MTYP_Pos)
     
    #define FSMC_BCR3_MTYP   FSMC_BCR3_MTYP_Msk
     
    #define FSMC_BCR3_MTYP_0   (0x1UL << FSMC_BCR3_MTYP_Pos)
     
    #define FSMC_BCR3_MTYP_1   (0x2UL << FSMC_BCR3_MTYP_Pos)
     
    #define FSMC_BCR3_MWID_Pos   (4U)
     
    #define FSMC_BCR3_MWID_Msk   (0x3UL << FSMC_BCR3_MWID_Pos)
     
    #define FSMC_BCR3_MWID   FSMC_BCR3_MWID_Msk
     
    #define FSMC_BCR3_MWID_0   (0x1UL << FSMC_BCR3_MWID_Pos)
     
    #define FSMC_BCR3_MWID_1   (0x2UL << FSMC_BCR3_MWID_Pos)
     
    #define FSMC_BCR3_FACCEN_Pos   (6U)
     
    #define FSMC_BCR3_FACCEN_Msk   (0x1UL << FSMC_BCR3_FACCEN_Pos)
     
    #define FSMC_BCR3_FACCEN   FSMC_BCR3_FACCEN_Msk
     
    #define FSMC_BCR3_BURSTEN_Pos   (8U)
     
    #define FSMC_BCR3_BURSTEN_Msk   (0x1UL << FSMC_BCR3_BURSTEN_Pos)
     
    #define FSMC_BCR3_BURSTEN   FSMC_BCR3_BURSTEN_Msk
     
    #define FSMC_BCR3_WAITPOL_Pos   (9U)
     
    #define FSMC_BCR3_WAITPOL_Msk   (0x1UL << FSMC_BCR3_WAITPOL_Pos)
     
    #define FSMC_BCR3_WAITPOL   FSMC_BCR3_WAITPOL_Msk
     
    #define FSMC_BCR3_WRAPMOD_Pos   (10U)
     
    #define FSMC_BCR3_WRAPMOD_Msk   (0x1UL << FSMC_BCR3_WRAPMOD_Pos)
     
    #define FSMC_BCR3_WRAPMOD   FSMC_BCR3_WRAPMOD_Msk
     
    #define FSMC_BCR3_WAITCFG_Pos   (11U)
     
    #define FSMC_BCR3_WAITCFG_Msk   (0x1UL << FSMC_BCR3_WAITCFG_Pos)
     
    #define FSMC_BCR3_WAITCFG   FSMC_BCR3_WAITCFG_Msk
     
    #define FSMC_BCR3_WREN_Pos   (12U)
     
    #define FSMC_BCR3_WREN_Msk   (0x1UL << FSMC_BCR3_WREN_Pos)
     
    #define FSMC_BCR3_WREN   FSMC_BCR3_WREN_Msk
     
    #define FSMC_BCR3_WAITEN_Pos   (13U)
     
    #define FSMC_BCR3_WAITEN_Msk   (0x1UL << FSMC_BCR3_WAITEN_Pos)
     
    #define FSMC_BCR3_WAITEN   FSMC_BCR3_WAITEN_Msk
     
    #define FSMC_BCR3_EXTMOD_Pos   (14U)
     
    #define FSMC_BCR3_EXTMOD_Msk   (0x1UL << FSMC_BCR3_EXTMOD_Pos)
     
    #define FSMC_BCR3_EXTMOD   FSMC_BCR3_EXTMOD_Msk
     
    #define FSMC_BCR3_ASYNCWAIT_Pos   (15U)
     
    #define FSMC_BCR3_ASYNCWAIT_Msk   (0x1UL << FSMC_BCR3_ASYNCWAIT_Pos)
     
    #define FSMC_BCR3_ASYNCWAIT   FSMC_BCR3_ASYNCWAIT_Msk
     
    #define FSMC_BCR3_CPSIZE_Pos   (16U)
     
    #define FSMC_BCR3_CPSIZE_Msk   (0x7UL << FSMC_BCR3_CPSIZE_Pos)
     
    #define FSMC_BCR3_CPSIZE   FSMC_BCR3_CPSIZE_Msk
     
    #define FSMC_BCR3_CPSIZE_0   (0x1UL << FSMC_BCR3_CPSIZE_Pos)
     
    #define FSMC_BCR3_CPSIZE_1   (0x2UL << FSMC_BCR3_CPSIZE_Pos)
     
    #define FSMC_BCR3_CPSIZE_2   (0x4UL << FSMC_BCR3_CPSIZE_Pos)
     
    #define FSMC_BCR3_CBURSTRW_Pos   (19U)
     
    #define FSMC_BCR3_CBURSTRW_Msk   (0x1UL << FSMC_BCR3_CBURSTRW_Pos)
     
    #define FSMC_BCR3_CBURSTRW   FSMC_BCR3_CBURSTRW_Msk
     
    #define FSMC_BCR4_MBKEN_Pos   (0U)
     
    #define FSMC_BCR4_MBKEN_Msk   (0x1UL << FSMC_BCR4_MBKEN_Pos)
     
    #define FSMC_BCR4_MBKEN   FSMC_BCR4_MBKEN_Msk
     
    #define FSMC_BCR4_MUXEN_Pos   (1U)
     
    #define FSMC_BCR4_MUXEN_Msk   (0x1UL << FSMC_BCR4_MUXEN_Pos)
     
    #define FSMC_BCR4_MUXEN   FSMC_BCR4_MUXEN_Msk
     
    #define FSMC_BCR4_MTYP_Pos   (2U)
     
    #define FSMC_BCR4_MTYP_Msk   (0x3UL << FSMC_BCR4_MTYP_Pos)
     
    #define FSMC_BCR4_MTYP   FSMC_BCR4_MTYP_Msk
     
    #define FSMC_BCR4_MTYP_0   (0x1UL << FSMC_BCR4_MTYP_Pos)
     
    #define FSMC_BCR4_MTYP_1   (0x2UL << FSMC_BCR4_MTYP_Pos)
     
    #define FSMC_BCR4_MWID_Pos   (4U)
     
    #define FSMC_BCR4_MWID_Msk   (0x3UL << FSMC_BCR4_MWID_Pos)
     
    #define FSMC_BCR4_MWID   FSMC_BCR4_MWID_Msk
     
    #define FSMC_BCR4_MWID_0   (0x1UL << FSMC_BCR4_MWID_Pos)
     
    #define FSMC_BCR4_MWID_1   (0x2UL << FSMC_BCR4_MWID_Pos)
     
    #define FSMC_BCR4_FACCEN_Pos   (6U)
     
    #define FSMC_BCR4_FACCEN_Msk   (0x1UL << FSMC_BCR4_FACCEN_Pos)
     
    #define FSMC_BCR4_FACCEN   FSMC_BCR4_FACCEN_Msk
     
    #define FSMC_BCR4_BURSTEN_Pos   (8U)
     
    #define FSMC_BCR4_BURSTEN_Msk   (0x1UL << FSMC_BCR4_BURSTEN_Pos)
     
    #define FSMC_BCR4_BURSTEN   FSMC_BCR4_BURSTEN_Msk
     
    #define FSMC_BCR4_WAITPOL_Pos   (9U)
     
    #define FSMC_BCR4_WAITPOL_Msk   (0x1UL << FSMC_BCR4_WAITPOL_Pos)
     
    #define FSMC_BCR4_WAITPOL   FSMC_BCR4_WAITPOL_Msk
     
    #define FSMC_BCR4_WRAPMOD_Pos   (10U)
     
    #define FSMC_BCR4_WRAPMOD_Msk   (0x1UL << FSMC_BCR4_WRAPMOD_Pos)
     
    #define FSMC_BCR4_WRAPMOD   FSMC_BCR4_WRAPMOD_Msk
     
    #define FSMC_BCR4_WAITCFG_Pos   (11U)
     
    #define FSMC_BCR4_WAITCFG_Msk   (0x1UL << FSMC_BCR4_WAITCFG_Pos)
     
    #define FSMC_BCR4_WAITCFG   FSMC_BCR4_WAITCFG_Msk
     
    #define FSMC_BCR4_WREN_Pos   (12U)
     
    #define FSMC_BCR4_WREN_Msk   (0x1UL << FSMC_BCR4_WREN_Pos)
     
    #define FSMC_BCR4_WREN   FSMC_BCR4_WREN_Msk
     
    #define FSMC_BCR4_WAITEN_Pos   (13U)
     
    #define FSMC_BCR4_WAITEN_Msk   (0x1UL << FSMC_BCR4_WAITEN_Pos)
     
    #define FSMC_BCR4_WAITEN   FSMC_BCR4_WAITEN_Msk
     
    #define FSMC_BCR4_EXTMOD_Pos   (14U)
     
    #define FSMC_BCR4_EXTMOD_Msk   (0x1UL << FSMC_BCR4_EXTMOD_Pos)
     
    #define FSMC_BCR4_EXTMOD   FSMC_BCR4_EXTMOD_Msk
     
    #define FSMC_BCR4_ASYNCWAIT_Pos   (15U)
     
    #define FSMC_BCR4_ASYNCWAIT_Msk   (0x1UL << FSMC_BCR4_ASYNCWAIT_Pos)
     
    #define FSMC_BCR4_ASYNCWAIT   FSMC_BCR4_ASYNCWAIT_Msk
     
    #define FSMC_BCR4_CPSIZE_Pos   (16U)
     
    #define FSMC_BCR4_CPSIZE_Msk   (0x7UL << FSMC_BCR4_CPSIZE_Pos)
     
    #define FSMC_BCR4_CPSIZE   FSMC_BCR4_CPSIZE_Msk
     
    #define FSMC_BCR4_CPSIZE_0   (0x1UL << FSMC_BCR4_CPSIZE_Pos)
     
    #define FSMC_BCR4_CPSIZE_1   (0x2UL << FSMC_BCR4_CPSIZE_Pos)
     
    #define FSMC_BCR4_CPSIZE_2   (0x4UL << FSMC_BCR4_CPSIZE_Pos)
     
    #define FSMC_BCR4_CBURSTRW_Pos   (19U)
     
    #define FSMC_BCR4_CBURSTRW_Msk   (0x1UL << FSMC_BCR4_CBURSTRW_Pos)
     
    #define FSMC_BCR4_CBURSTRW   FSMC_BCR4_CBURSTRW_Msk
     
    #define FSMC_BTR1_ADDSET_Pos   (0U)
     
    #define FSMC_BTR1_ADDSET_Msk   (0xFUL << FSMC_BTR1_ADDSET_Pos)
     
    #define FSMC_BTR1_ADDSET   FSMC_BTR1_ADDSET_Msk
     
    #define FSMC_BTR1_ADDSET_0   (0x1UL << FSMC_BTR1_ADDSET_Pos)
     
    #define FSMC_BTR1_ADDSET_1   (0x2UL << FSMC_BTR1_ADDSET_Pos)
     
    #define FSMC_BTR1_ADDSET_2   (0x4UL << FSMC_BTR1_ADDSET_Pos)
     
    #define FSMC_BTR1_ADDSET_3   (0x8UL << FSMC_BTR1_ADDSET_Pos)
     
    #define FSMC_BTR1_ADDHLD_Pos   (4U)
     
    #define FSMC_BTR1_ADDHLD_Msk   (0xFUL << FSMC_BTR1_ADDHLD_Pos)
     
    #define FSMC_BTR1_ADDHLD   FSMC_BTR1_ADDHLD_Msk
     
    #define FSMC_BTR1_ADDHLD_0   (0x1UL << FSMC_BTR1_ADDHLD_Pos)
     
    #define FSMC_BTR1_ADDHLD_1   (0x2UL << FSMC_BTR1_ADDHLD_Pos)
     
    #define FSMC_BTR1_ADDHLD_2   (0x4UL << FSMC_BTR1_ADDHLD_Pos)
     
    #define FSMC_BTR1_ADDHLD_3   (0x8UL << FSMC_BTR1_ADDHLD_Pos)
     
    #define FSMC_BTR1_DATAST_Pos   (8U)
     
    #define FSMC_BTR1_DATAST_Msk   (0xFFUL << FSMC_BTR1_DATAST_Pos)
     
    #define FSMC_BTR1_DATAST   FSMC_BTR1_DATAST_Msk
     
    #define FSMC_BTR1_DATAST_0   (0x01UL << FSMC_BTR1_DATAST_Pos)
     
    #define FSMC_BTR1_DATAST_1   (0x02UL << FSMC_BTR1_DATAST_Pos)
     
    #define FSMC_BTR1_DATAST_2   (0x04UL << FSMC_BTR1_DATAST_Pos)
     
    #define FSMC_BTR1_DATAST_3   (0x08UL << FSMC_BTR1_DATAST_Pos)
     
    #define FSMC_BTR1_DATAST_4   (0x10UL << FSMC_BTR1_DATAST_Pos)
     
    #define FSMC_BTR1_DATAST_5   (0x20UL << FSMC_BTR1_DATAST_Pos)
     
    #define FSMC_BTR1_DATAST_6   (0x40UL << FSMC_BTR1_DATAST_Pos)
     
    #define FSMC_BTR1_DATAST_7   (0x80UL << FSMC_BTR1_DATAST_Pos)
     
    #define FSMC_BTR1_BUSTURN_Pos   (16U)
     
    #define FSMC_BTR1_BUSTURN_Msk   (0xFUL << FSMC_BTR1_BUSTURN_Pos)
     
    #define FSMC_BTR1_BUSTURN   FSMC_BTR1_BUSTURN_Msk
     
    #define FSMC_BTR1_BUSTURN_0   (0x1UL << FSMC_BTR1_BUSTURN_Pos)
     
    #define FSMC_BTR1_BUSTURN_1   (0x2UL << FSMC_BTR1_BUSTURN_Pos)
     
    #define FSMC_BTR1_BUSTURN_2   (0x4UL << FSMC_BTR1_BUSTURN_Pos)
     
    #define FSMC_BTR1_BUSTURN_3   (0x8UL << FSMC_BTR1_BUSTURN_Pos)
     
    #define FSMC_BTR1_CLKDIV_Pos   (20U)
     
    #define FSMC_BTR1_CLKDIV_Msk   (0xFUL << FSMC_BTR1_CLKDIV_Pos)
     
    #define FSMC_BTR1_CLKDIV   FSMC_BTR1_CLKDIV_Msk
     
    #define FSMC_BTR1_CLKDIV_0   (0x1UL << FSMC_BTR1_CLKDIV_Pos)
     
    #define FSMC_BTR1_CLKDIV_1   (0x2UL << FSMC_BTR1_CLKDIV_Pos)
     
    #define FSMC_BTR1_CLKDIV_2   (0x4UL << FSMC_BTR1_CLKDIV_Pos)
     
    #define FSMC_BTR1_CLKDIV_3   (0x8UL << FSMC_BTR1_CLKDIV_Pos)
     
    #define FSMC_BTR1_DATLAT_Pos   (24U)
     
    #define FSMC_BTR1_DATLAT_Msk   (0xFUL << FSMC_BTR1_DATLAT_Pos)
     
    #define FSMC_BTR1_DATLAT   FSMC_BTR1_DATLAT_Msk
     
    #define FSMC_BTR1_DATLAT_0   (0x1UL << FSMC_BTR1_DATLAT_Pos)
     
    #define FSMC_BTR1_DATLAT_1   (0x2UL << FSMC_BTR1_DATLAT_Pos)
     
    #define FSMC_BTR1_DATLAT_2   (0x4UL << FSMC_BTR1_DATLAT_Pos)
     
    #define FSMC_BTR1_DATLAT_3   (0x8UL << FSMC_BTR1_DATLAT_Pos)
     
    #define FSMC_BTR1_ACCMOD_Pos   (28U)
     
    #define FSMC_BTR1_ACCMOD_Msk   (0x3UL << FSMC_BTR1_ACCMOD_Pos)
     
    #define FSMC_BTR1_ACCMOD   FSMC_BTR1_ACCMOD_Msk
     
    #define FSMC_BTR1_ACCMOD_0   (0x1UL << FSMC_BTR1_ACCMOD_Pos)
     
    #define FSMC_BTR1_ACCMOD_1   (0x2UL << FSMC_BTR1_ACCMOD_Pos)
     
    #define FSMC_BTR2_ADDSET_Pos   (0U)
     
    #define FSMC_BTR2_ADDSET_Msk   (0xFUL << FSMC_BTR2_ADDSET_Pos)
     
    #define FSMC_BTR2_ADDSET   FSMC_BTR2_ADDSET_Msk
     
    #define FSMC_BTR2_ADDSET_0   (0x1UL << FSMC_BTR2_ADDSET_Pos)
     
    #define FSMC_BTR2_ADDSET_1   (0x2UL << FSMC_BTR2_ADDSET_Pos)
     
    #define FSMC_BTR2_ADDSET_2   (0x4UL << FSMC_BTR2_ADDSET_Pos)
     
    #define FSMC_BTR2_ADDSET_3   (0x8UL << FSMC_BTR2_ADDSET_Pos)
     
    #define FSMC_BTR2_ADDHLD_Pos   (4U)
     
    #define FSMC_BTR2_ADDHLD_Msk   (0xFUL << FSMC_BTR2_ADDHLD_Pos)
     
    #define FSMC_BTR2_ADDHLD   FSMC_BTR2_ADDHLD_Msk
     
    #define FSMC_BTR2_ADDHLD_0   (0x1UL << FSMC_BTR2_ADDHLD_Pos)
     
    #define FSMC_BTR2_ADDHLD_1   (0x2UL << FSMC_BTR2_ADDHLD_Pos)
     
    #define FSMC_BTR2_ADDHLD_2   (0x4UL << FSMC_BTR2_ADDHLD_Pos)
     
    #define FSMC_BTR2_ADDHLD_3   (0x8UL << FSMC_BTR2_ADDHLD_Pos)
     
    #define FSMC_BTR2_DATAST_Pos   (8U)
     
    #define FSMC_BTR2_DATAST_Msk   (0xFFUL << FSMC_BTR2_DATAST_Pos)
     
    #define FSMC_BTR2_DATAST   FSMC_BTR2_DATAST_Msk
     
    #define FSMC_BTR2_DATAST_0   (0x01UL << FSMC_BTR2_DATAST_Pos)
     
    #define FSMC_BTR2_DATAST_1   (0x02UL << FSMC_BTR2_DATAST_Pos)
     
    #define FSMC_BTR2_DATAST_2   (0x04UL << FSMC_BTR2_DATAST_Pos)
     
    #define FSMC_BTR2_DATAST_3   (0x08UL << FSMC_BTR2_DATAST_Pos)
     
    #define FSMC_BTR2_DATAST_4   (0x10UL << FSMC_BTR2_DATAST_Pos)
     
    #define FSMC_BTR2_DATAST_5   (0x20UL << FSMC_BTR2_DATAST_Pos)
     
    #define FSMC_BTR2_DATAST_6   (0x40UL << FSMC_BTR2_DATAST_Pos)
     
    #define FSMC_BTR2_DATAST_7   (0x80UL << FSMC_BTR2_DATAST_Pos)
     
    #define FSMC_BTR2_BUSTURN_Pos   (16U)
     
    #define FSMC_BTR2_BUSTURN_Msk   (0xFUL << FSMC_BTR2_BUSTURN_Pos)
     
    #define FSMC_BTR2_BUSTURN   FSMC_BTR2_BUSTURN_Msk
     
    #define FSMC_BTR2_BUSTURN_0   (0x1UL << FSMC_BTR2_BUSTURN_Pos)
     
    #define FSMC_BTR2_BUSTURN_1   (0x2UL << FSMC_BTR2_BUSTURN_Pos)
     
    #define FSMC_BTR2_BUSTURN_2   (0x4UL << FSMC_BTR2_BUSTURN_Pos)
     
    #define FSMC_BTR2_BUSTURN_3   (0x8UL << FSMC_BTR2_BUSTURN_Pos)
     
    #define FSMC_BTR2_CLKDIV_Pos   (20U)
     
    #define FSMC_BTR2_CLKDIV_Msk   (0xFUL << FSMC_BTR2_CLKDIV_Pos)
     
    #define FSMC_BTR2_CLKDIV   FSMC_BTR2_CLKDIV_Msk
     
    #define FSMC_BTR2_CLKDIV_0   (0x1UL << FSMC_BTR2_CLKDIV_Pos)
     
    #define FSMC_BTR2_CLKDIV_1   (0x2UL << FSMC_BTR2_CLKDIV_Pos)
     
    #define FSMC_BTR2_CLKDIV_2   (0x4UL << FSMC_BTR2_CLKDIV_Pos)
     
    #define FSMC_BTR2_CLKDIV_3   (0x8UL << FSMC_BTR2_CLKDIV_Pos)
     
    #define FSMC_BTR2_DATLAT_Pos   (24U)
     
    #define FSMC_BTR2_DATLAT_Msk   (0xFUL << FSMC_BTR2_DATLAT_Pos)
     
    #define FSMC_BTR2_DATLAT   FSMC_BTR2_DATLAT_Msk
     
    #define FSMC_BTR2_DATLAT_0   (0x1UL << FSMC_BTR2_DATLAT_Pos)
     
    #define FSMC_BTR2_DATLAT_1   (0x2UL << FSMC_BTR2_DATLAT_Pos)
     
    #define FSMC_BTR2_DATLAT_2   (0x4UL << FSMC_BTR2_DATLAT_Pos)
     
    #define FSMC_BTR2_DATLAT_3   (0x8UL << FSMC_BTR2_DATLAT_Pos)
     
    #define FSMC_BTR2_ACCMOD_Pos   (28U)
     
    #define FSMC_BTR2_ACCMOD_Msk   (0x3UL << FSMC_BTR2_ACCMOD_Pos)
     
    #define FSMC_BTR2_ACCMOD   FSMC_BTR2_ACCMOD_Msk
     
    #define FSMC_BTR2_ACCMOD_0   (0x1UL << FSMC_BTR2_ACCMOD_Pos)
     
    #define FSMC_BTR2_ACCMOD_1   (0x2UL << FSMC_BTR2_ACCMOD_Pos)
     
    #define FSMC_BTR3_ADDSET_Pos   (0U)
     
    #define FSMC_BTR3_ADDSET_Msk   (0xFUL << FSMC_BTR3_ADDSET_Pos)
     
    #define FSMC_BTR3_ADDSET   FSMC_BTR3_ADDSET_Msk
     
    #define FSMC_BTR3_ADDSET_0   (0x1UL << FSMC_BTR3_ADDSET_Pos)
     
    #define FSMC_BTR3_ADDSET_1   (0x2UL << FSMC_BTR3_ADDSET_Pos)
     
    #define FSMC_BTR3_ADDSET_2   (0x4UL << FSMC_BTR3_ADDSET_Pos)
     
    #define FSMC_BTR3_ADDSET_3   (0x8UL << FSMC_BTR3_ADDSET_Pos)
     
    #define FSMC_BTR3_ADDHLD_Pos   (4U)
     
    #define FSMC_BTR3_ADDHLD_Msk   (0xFUL << FSMC_BTR3_ADDHLD_Pos)
     
    #define FSMC_BTR3_ADDHLD   FSMC_BTR3_ADDHLD_Msk
     
    #define FSMC_BTR3_ADDHLD_0   (0x1UL << FSMC_BTR3_ADDHLD_Pos)
     
    #define FSMC_BTR3_ADDHLD_1   (0x2UL << FSMC_BTR3_ADDHLD_Pos)
     
    #define FSMC_BTR3_ADDHLD_2   (0x4UL << FSMC_BTR3_ADDHLD_Pos)
     
    #define FSMC_BTR3_ADDHLD_3   (0x8UL << FSMC_BTR3_ADDHLD_Pos)
     
    #define FSMC_BTR3_DATAST_Pos   (8U)
     
    #define FSMC_BTR3_DATAST_Msk   (0xFFUL << FSMC_BTR3_DATAST_Pos)
     
    #define FSMC_BTR3_DATAST   FSMC_BTR3_DATAST_Msk
     
    #define FSMC_BTR3_DATAST_0   (0x01UL << FSMC_BTR3_DATAST_Pos)
     
    #define FSMC_BTR3_DATAST_1   (0x02UL << FSMC_BTR3_DATAST_Pos)
     
    #define FSMC_BTR3_DATAST_2   (0x04UL << FSMC_BTR3_DATAST_Pos)
     
    #define FSMC_BTR3_DATAST_3   (0x08UL << FSMC_BTR3_DATAST_Pos)
     
    #define FSMC_BTR3_DATAST_4   (0x10UL << FSMC_BTR3_DATAST_Pos)
     
    #define FSMC_BTR3_DATAST_5   (0x20UL << FSMC_BTR3_DATAST_Pos)
     
    #define FSMC_BTR3_DATAST_6   (0x40UL << FSMC_BTR3_DATAST_Pos)
     
    #define FSMC_BTR3_DATAST_7   (0x80UL << FSMC_BTR3_DATAST_Pos)
     
    #define FSMC_BTR3_BUSTURN_Pos   (16U)
     
    #define FSMC_BTR3_BUSTURN_Msk   (0xFUL << FSMC_BTR3_BUSTURN_Pos)
     
    #define FSMC_BTR3_BUSTURN   FSMC_BTR3_BUSTURN_Msk
     
    #define FSMC_BTR3_BUSTURN_0   (0x1UL << FSMC_BTR3_BUSTURN_Pos)
     
    #define FSMC_BTR3_BUSTURN_1   (0x2UL << FSMC_BTR3_BUSTURN_Pos)
     
    #define FSMC_BTR3_BUSTURN_2   (0x4UL << FSMC_BTR3_BUSTURN_Pos)
     
    #define FSMC_BTR3_BUSTURN_3   (0x8UL << FSMC_BTR3_BUSTURN_Pos)
     
    #define FSMC_BTR3_CLKDIV_Pos   (20U)
     
    #define FSMC_BTR3_CLKDIV_Msk   (0xFUL << FSMC_BTR3_CLKDIV_Pos)
     
    #define FSMC_BTR3_CLKDIV   FSMC_BTR3_CLKDIV_Msk
     
    #define FSMC_BTR3_CLKDIV_0   (0x1UL << FSMC_BTR3_CLKDIV_Pos)
     
    #define FSMC_BTR3_CLKDIV_1   (0x2UL << FSMC_BTR3_CLKDIV_Pos)
     
    #define FSMC_BTR3_CLKDIV_2   (0x4UL << FSMC_BTR3_CLKDIV_Pos)
     
    #define FSMC_BTR3_CLKDIV_3   (0x8UL << FSMC_BTR3_CLKDIV_Pos)
     
    #define FSMC_BTR3_DATLAT_Pos   (24U)
     
    #define FSMC_BTR3_DATLAT_Msk   (0xFUL << FSMC_BTR3_DATLAT_Pos)
     
    #define FSMC_BTR3_DATLAT   FSMC_BTR3_DATLAT_Msk
     
    #define FSMC_BTR3_DATLAT_0   (0x1UL << FSMC_BTR3_DATLAT_Pos)
     
    #define FSMC_BTR3_DATLAT_1   (0x2UL << FSMC_BTR3_DATLAT_Pos)
     
    #define FSMC_BTR3_DATLAT_2   (0x4UL << FSMC_BTR3_DATLAT_Pos)
     
    #define FSMC_BTR3_DATLAT_3   (0x8UL << FSMC_BTR3_DATLAT_Pos)
     
    #define FSMC_BTR3_ACCMOD_Pos   (28U)
     
    #define FSMC_BTR3_ACCMOD_Msk   (0x3UL << FSMC_BTR3_ACCMOD_Pos)
     
    #define FSMC_BTR3_ACCMOD   FSMC_BTR3_ACCMOD_Msk
     
    #define FSMC_BTR3_ACCMOD_0   (0x1UL << FSMC_BTR3_ACCMOD_Pos)
     
    #define FSMC_BTR3_ACCMOD_1   (0x2UL << FSMC_BTR3_ACCMOD_Pos)
     
    #define FSMC_BTR4_ADDSET_Pos   (0U)
     
    #define FSMC_BTR4_ADDSET_Msk   (0xFUL << FSMC_BTR4_ADDSET_Pos)
     
    #define FSMC_BTR4_ADDSET   FSMC_BTR4_ADDSET_Msk
     
    #define FSMC_BTR4_ADDSET_0   (0x1UL << FSMC_BTR4_ADDSET_Pos)
     
    #define FSMC_BTR4_ADDSET_1   (0x2UL << FSMC_BTR4_ADDSET_Pos)
     
    #define FSMC_BTR4_ADDSET_2   (0x4UL << FSMC_BTR4_ADDSET_Pos)
     
    #define FSMC_BTR4_ADDSET_3   (0x8UL << FSMC_BTR4_ADDSET_Pos)
     
    #define FSMC_BTR4_ADDHLD_Pos   (4U)
     
    #define FSMC_BTR4_ADDHLD_Msk   (0xFUL << FSMC_BTR4_ADDHLD_Pos)
     
    #define FSMC_BTR4_ADDHLD   FSMC_BTR4_ADDHLD_Msk
     
    #define FSMC_BTR4_ADDHLD_0   (0x1UL << FSMC_BTR4_ADDHLD_Pos)
     
    #define FSMC_BTR4_ADDHLD_1   (0x2UL << FSMC_BTR4_ADDHLD_Pos)
     
    #define FSMC_BTR4_ADDHLD_2   (0x4UL << FSMC_BTR4_ADDHLD_Pos)
     
    #define FSMC_BTR4_ADDHLD_3   (0x8UL << FSMC_BTR4_ADDHLD_Pos)
     
    #define FSMC_BTR4_DATAST_Pos   (8U)
     
    #define FSMC_BTR4_DATAST_Msk   (0xFFUL << FSMC_BTR4_DATAST_Pos)
     
    #define FSMC_BTR4_DATAST   FSMC_BTR4_DATAST_Msk
     
    #define FSMC_BTR4_DATAST_0   (0x01UL << FSMC_BTR4_DATAST_Pos)
     
    #define FSMC_BTR4_DATAST_1   (0x02UL << FSMC_BTR4_DATAST_Pos)
     
    #define FSMC_BTR4_DATAST_2   (0x04UL << FSMC_BTR4_DATAST_Pos)
     
    #define FSMC_BTR4_DATAST_3   (0x08UL << FSMC_BTR4_DATAST_Pos)
     
    #define FSMC_BTR4_DATAST_4   (0x10UL << FSMC_BTR4_DATAST_Pos)
     
    #define FSMC_BTR4_DATAST_5   (0x20UL << FSMC_BTR4_DATAST_Pos)
     
    #define FSMC_BTR4_DATAST_6   (0x40UL << FSMC_BTR4_DATAST_Pos)
     
    #define FSMC_BTR4_DATAST_7   (0x80UL << FSMC_BTR4_DATAST_Pos)
     
    #define FSMC_BTR4_BUSTURN_Pos   (16U)
     
    #define FSMC_BTR4_BUSTURN_Msk   (0xFUL << FSMC_BTR4_BUSTURN_Pos)
     
    #define FSMC_BTR4_BUSTURN   FSMC_BTR4_BUSTURN_Msk
     
    #define FSMC_BTR4_BUSTURN_0   (0x1UL << FSMC_BTR4_BUSTURN_Pos)
     
    #define FSMC_BTR4_BUSTURN_1   (0x2UL << FSMC_BTR4_BUSTURN_Pos)
     
    #define FSMC_BTR4_BUSTURN_2   (0x4UL << FSMC_BTR4_BUSTURN_Pos)
     
    #define FSMC_BTR4_BUSTURN_3   (0x8UL << FSMC_BTR4_BUSTURN_Pos)
     
    #define FSMC_BTR4_CLKDIV_Pos   (20U)
     
    #define FSMC_BTR4_CLKDIV_Msk   (0xFUL << FSMC_BTR4_CLKDIV_Pos)
     
    #define FSMC_BTR4_CLKDIV   FSMC_BTR4_CLKDIV_Msk
     
    #define FSMC_BTR4_CLKDIV_0   (0x1UL << FSMC_BTR4_CLKDIV_Pos)
     
    #define FSMC_BTR4_CLKDIV_1   (0x2UL << FSMC_BTR4_CLKDIV_Pos)
     
    #define FSMC_BTR4_CLKDIV_2   (0x4UL << FSMC_BTR4_CLKDIV_Pos)
     
    #define FSMC_BTR4_CLKDIV_3   (0x8UL << FSMC_BTR4_CLKDIV_Pos)
     
    #define FSMC_BTR4_DATLAT_Pos   (24U)
     
    #define FSMC_BTR4_DATLAT_Msk   (0xFUL << FSMC_BTR4_DATLAT_Pos)
     
    #define FSMC_BTR4_DATLAT   FSMC_BTR4_DATLAT_Msk
     
    #define FSMC_BTR4_DATLAT_0   (0x1UL << FSMC_BTR4_DATLAT_Pos)
     
    #define FSMC_BTR4_DATLAT_1   (0x2UL << FSMC_BTR4_DATLAT_Pos)
     
    #define FSMC_BTR4_DATLAT_2   (0x4UL << FSMC_BTR4_DATLAT_Pos)
     
    #define FSMC_BTR4_DATLAT_3   (0x8UL << FSMC_BTR4_DATLAT_Pos)
     
    #define FSMC_BTR4_ACCMOD_Pos   (28U)
     
    #define FSMC_BTR4_ACCMOD_Msk   (0x3UL << FSMC_BTR4_ACCMOD_Pos)
     
    #define FSMC_BTR4_ACCMOD   FSMC_BTR4_ACCMOD_Msk
     
    #define FSMC_BTR4_ACCMOD_0   (0x1UL << FSMC_BTR4_ACCMOD_Pos)
     
    #define FSMC_BTR4_ACCMOD_1   (0x2UL << FSMC_BTR4_ACCMOD_Pos)
     
    #define FSMC_BWTR1_ADDSET_Pos   (0U)
     
    #define FSMC_BWTR1_ADDSET_Msk   (0xFUL << FSMC_BWTR1_ADDSET_Pos)
     
    #define FSMC_BWTR1_ADDSET   FSMC_BWTR1_ADDSET_Msk
     
    #define FSMC_BWTR1_ADDSET_0   (0x1UL << FSMC_BWTR1_ADDSET_Pos)
     
    #define FSMC_BWTR1_ADDSET_1   (0x2UL << FSMC_BWTR1_ADDSET_Pos)
     
    #define FSMC_BWTR1_ADDSET_2   (0x4UL << FSMC_BWTR1_ADDSET_Pos)
     
    #define FSMC_BWTR1_ADDSET_3   (0x8UL << FSMC_BWTR1_ADDSET_Pos)
     
    #define FSMC_BWTR1_ADDHLD_Pos   (4U)
     
    #define FSMC_BWTR1_ADDHLD_Msk   (0xFUL << FSMC_BWTR1_ADDHLD_Pos)
     
    #define FSMC_BWTR1_ADDHLD   FSMC_BWTR1_ADDHLD_Msk
     
    #define FSMC_BWTR1_ADDHLD_0   (0x1UL << FSMC_BWTR1_ADDHLD_Pos)
     
    #define FSMC_BWTR1_ADDHLD_1   (0x2UL << FSMC_BWTR1_ADDHLD_Pos)
     
    #define FSMC_BWTR1_ADDHLD_2   (0x4UL << FSMC_BWTR1_ADDHLD_Pos)
     
    #define FSMC_BWTR1_ADDHLD_3   (0x8UL << FSMC_BWTR1_ADDHLD_Pos)
     
    #define FSMC_BWTR1_DATAST_Pos   (8U)
     
    #define FSMC_BWTR1_DATAST_Msk   (0xFFUL << FSMC_BWTR1_DATAST_Pos)
     
    #define FSMC_BWTR1_DATAST   FSMC_BWTR1_DATAST_Msk
     
    #define FSMC_BWTR1_DATAST_0   (0x01UL << FSMC_BWTR1_DATAST_Pos)
     
    #define FSMC_BWTR1_DATAST_1   (0x02UL << FSMC_BWTR1_DATAST_Pos)
     
    #define FSMC_BWTR1_DATAST_2   (0x04UL << FSMC_BWTR1_DATAST_Pos)
     
    #define FSMC_BWTR1_DATAST_3   (0x08UL << FSMC_BWTR1_DATAST_Pos)
     
    #define FSMC_BWTR1_DATAST_4   (0x10UL << FSMC_BWTR1_DATAST_Pos)
     
    #define FSMC_BWTR1_DATAST_5   (0x20UL << FSMC_BWTR1_DATAST_Pos)
     
    #define FSMC_BWTR1_DATAST_6   (0x40UL << FSMC_BWTR1_DATAST_Pos)
     
    #define FSMC_BWTR1_DATAST_7   (0x80UL << FSMC_BWTR1_DATAST_Pos)
     
    #define FSMC_BWTR1_BUSTURN_Pos   (16U)
     
    #define FSMC_BWTR1_BUSTURN_Msk   (0xFUL << FSMC_BWTR1_BUSTURN_Pos)
     
    #define FSMC_BWTR1_BUSTURN   FSMC_BWTR1_BUSTURN_Msk
     
    #define FSMC_BWTR1_BUSTURN_0   (0x1UL << FSMC_BWTR1_BUSTURN_Pos)
     
    #define FSMC_BWTR1_BUSTURN_1   (0x2UL << FSMC_BWTR1_BUSTURN_Pos)
     
    #define FSMC_BWTR1_BUSTURN_2   (0x4UL << FSMC_BWTR1_BUSTURN_Pos)
     
    #define FSMC_BWTR1_BUSTURN_3   (0x8UL << FSMC_BWTR1_BUSTURN_Pos)
     
    #define FSMC_BWTR1_ACCMOD_Pos   (28U)
     
    #define FSMC_BWTR1_ACCMOD_Msk   (0x3UL << FSMC_BWTR1_ACCMOD_Pos)
     
    #define FSMC_BWTR1_ACCMOD   FSMC_BWTR1_ACCMOD_Msk
     
    #define FSMC_BWTR1_ACCMOD_0   (0x1UL << FSMC_BWTR1_ACCMOD_Pos)
     
    #define FSMC_BWTR1_ACCMOD_1   (0x2UL << FSMC_BWTR1_ACCMOD_Pos)
     
    #define FSMC_BWTR2_ADDSET_Pos   (0U)
     
    #define FSMC_BWTR2_ADDSET_Msk   (0xFUL << FSMC_BWTR2_ADDSET_Pos)
     
    #define FSMC_BWTR2_ADDSET   FSMC_BWTR2_ADDSET_Msk
     
    #define FSMC_BWTR2_ADDSET_0   (0x1UL << FSMC_BWTR2_ADDSET_Pos)
     
    #define FSMC_BWTR2_ADDSET_1   (0x2UL << FSMC_BWTR2_ADDSET_Pos)
     
    #define FSMC_BWTR2_ADDSET_2   (0x4UL << FSMC_BWTR2_ADDSET_Pos)
     
    #define FSMC_BWTR2_ADDSET_3   (0x8UL << FSMC_BWTR2_ADDSET_Pos)
     
    #define FSMC_BWTR2_ADDHLD_Pos   (4U)
     
    #define FSMC_BWTR2_ADDHLD_Msk   (0xFUL << FSMC_BWTR2_ADDHLD_Pos)
     
    #define FSMC_BWTR2_ADDHLD   FSMC_BWTR2_ADDHLD_Msk
     
    #define FSMC_BWTR2_ADDHLD_0   (0x1UL << FSMC_BWTR2_ADDHLD_Pos)
     
    #define FSMC_BWTR2_ADDHLD_1   (0x2UL << FSMC_BWTR2_ADDHLD_Pos)
     
    #define FSMC_BWTR2_ADDHLD_2   (0x4UL << FSMC_BWTR2_ADDHLD_Pos)
     
    #define FSMC_BWTR2_ADDHLD_3   (0x8UL << FSMC_BWTR2_ADDHLD_Pos)
     
    #define FSMC_BWTR2_DATAST_Pos   (8U)
     
    #define FSMC_BWTR2_DATAST_Msk   (0xFFUL << FSMC_BWTR2_DATAST_Pos)
     
    #define FSMC_BWTR2_DATAST   FSMC_BWTR2_DATAST_Msk
     
    #define FSMC_BWTR2_DATAST_0   (0x01UL << FSMC_BWTR2_DATAST_Pos)
     
    #define FSMC_BWTR2_DATAST_1   (0x02UL << FSMC_BWTR2_DATAST_Pos)
     
    #define FSMC_BWTR2_DATAST_2   (0x04UL << FSMC_BWTR2_DATAST_Pos)
     
    #define FSMC_BWTR2_DATAST_3   (0x08UL << FSMC_BWTR2_DATAST_Pos)
     
    #define FSMC_BWTR2_DATAST_4   (0x10UL << FSMC_BWTR2_DATAST_Pos)
     
    #define FSMC_BWTR2_DATAST_5   (0x20UL << FSMC_BWTR2_DATAST_Pos)
     
    #define FSMC_BWTR2_DATAST_6   (0x40UL << FSMC_BWTR2_DATAST_Pos)
     
    #define FSMC_BWTR2_DATAST_7   (0x80UL << FSMC_BWTR2_DATAST_Pos)
     
    #define FSMC_BWTR2_BUSTURN_Pos   (16U)
     
    #define FSMC_BWTR2_BUSTURN_Msk   (0xFUL << FSMC_BWTR2_BUSTURN_Pos)
     
    #define FSMC_BWTR2_BUSTURN   FSMC_BWTR2_BUSTURN_Msk
     
    #define FSMC_BWTR2_BUSTURN_0   (0x1UL << FSMC_BWTR2_BUSTURN_Pos)
     
    #define FSMC_BWTR2_BUSTURN_1   (0x2UL << FSMC_BWTR2_BUSTURN_Pos)
     
    #define FSMC_BWTR2_BUSTURN_2   (0x4UL << FSMC_BWTR2_BUSTURN_Pos)
     
    #define FSMC_BWTR2_BUSTURN_3   (0x8UL << FSMC_BWTR2_BUSTURN_Pos)
     
    #define FSMC_BWTR2_ACCMOD_Pos   (28U)
     
    #define FSMC_BWTR2_ACCMOD_Msk   (0x3UL << FSMC_BWTR2_ACCMOD_Pos)
     
    #define FSMC_BWTR2_ACCMOD   FSMC_BWTR2_ACCMOD_Msk
     
    #define FSMC_BWTR2_ACCMOD_0   (0x1UL << FSMC_BWTR2_ACCMOD_Pos)
     
    #define FSMC_BWTR2_ACCMOD_1   (0x2UL << FSMC_BWTR2_ACCMOD_Pos)
     
    #define FSMC_BWTR3_ADDSET_Pos   (0U)
     
    #define FSMC_BWTR3_ADDSET_Msk   (0xFUL << FSMC_BWTR3_ADDSET_Pos)
     
    #define FSMC_BWTR3_ADDSET   FSMC_BWTR3_ADDSET_Msk
     
    #define FSMC_BWTR3_ADDSET_0   (0x1UL << FSMC_BWTR3_ADDSET_Pos)
     
    #define FSMC_BWTR3_ADDSET_1   (0x2UL << FSMC_BWTR3_ADDSET_Pos)
     
    #define FSMC_BWTR3_ADDSET_2   (0x4UL << FSMC_BWTR3_ADDSET_Pos)
     
    #define FSMC_BWTR3_ADDSET_3   (0x8UL << FSMC_BWTR3_ADDSET_Pos)
     
    #define FSMC_BWTR3_ADDHLD_Pos   (4U)
     
    #define FSMC_BWTR3_ADDHLD_Msk   (0xFUL << FSMC_BWTR3_ADDHLD_Pos)
     
    #define FSMC_BWTR3_ADDHLD   FSMC_BWTR3_ADDHLD_Msk
     
    #define FSMC_BWTR3_ADDHLD_0   (0x1UL << FSMC_BWTR3_ADDHLD_Pos)
     
    #define FSMC_BWTR3_ADDHLD_1   (0x2UL << FSMC_BWTR3_ADDHLD_Pos)
     
    #define FSMC_BWTR3_ADDHLD_2   (0x4UL << FSMC_BWTR3_ADDHLD_Pos)
     
    #define FSMC_BWTR3_ADDHLD_3   (0x8UL << FSMC_BWTR3_ADDHLD_Pos)
     
    #define FSMC_BWTR3_DATAST_Pos   (8U)
     
    #define FSMC_BWTR3_DATAST_Msk   (0xFFUL << FSMC_BWTR3_DATAST_Pos)
     
    #define FSMC_BWTR3_DATAST   FSMC_BWTR3_DATAST_Msk
     
    #define FSMC_BWTR3_DATAST_0   (0x01UL << FSMC_BWTR3_DATAST_Pos)
     
    #define FSMC_BWTR3_DATAST_1   (0x02UL << FSMC_BWTR3_DATAST_Pos)
     
    #define FSMC_BWTR3_DATAST_2   (0x04UL << FSMC_BWTR3_DATAST_Pos)
     
    #define FSMC_BWTR3_DATAST_3   (0x08UL << FSMC_BWTR3_DATAST_Pos)
     
    #define FSMC_BWTR3_DATAST_4   (0x10UL << FSMC_BWTR3_DATAST_Pos)
     
    #define FSMC_BWTR3_DATAST_5   (0x20UL << FSMC_BWTR3_DATAST_Pos)
     
    #define FSMC_BWTR3_DATAST_6   (0x40UL << FSMC_BWTR3_DATAST_Pos)
     
    #define FSMC_BWTR3_DATAST_7   (0x80UL << FSMC_BWTR3_DATAST_Pos)
     
    #define FSMC_BWTR3_BUSTURN_Pos   (16U)
     
    #define FSMC_BWTR3_BUSTURN_Msk   (0xFUL << FSMC_BWTR3_BUSTURN_Pos)
     
    #define FSMC_BWTR3_BUSTURN   FSMC_BWTR3_BUSTURN_Msk
     
    #define FSMC_BWTR3_BUSTURN_0   (0x1UL << FSMC_BWTR3_BUSTURN_Pos)
     
    #define FSMC_BWTR3_BUSTURN_1   (0x2UL << FSMC_BWTR3_BUSTURN_Pos)
     
    #define FSMC_BWTR3_BUSTURN_2   (0x4UL << FSMC_BWTR3_BUSTURN_Pos)
     
    #define FSMC_BWTR3_BUSTURN_3   (0x8UL << FSMC_BWTR3_BUSTURN_Pos)
     
    #define FSMC_BWTR3_ACCMOD_Pos   (28U)
     
    #define FSMC_BWTR3_ACCMOD_Msk   (0x3UL << FSMC_BWTR3_ACCMOD_Pos)
     
    #define FSMC_BWTR3_ACCMOD   FSMC_BWTR3_ACCMOD_Msk
     
    #define FSMC_BWTR3_ACCMOD_0   (0x1UL << FSMC_BWTR3_ACCMOD_Pos)
     
    #define FSMC_BWTR3_ACCMOD_1   (0x2UL << FSMC_BWTR3_ACCMOD_Pos)
     
    #define FSMC_BWTR4_ADDSET_Pos   (0U)
     
    #define FSMC_BWTR4_ADDSET_Msk   (0xFUL << FSMC_BWTR4_ADDSET_Pos)
     
    #define FSMC_BWTR4_ADDSET   FSMC_BWTR4_ADDSET_Msk
     
    #define FSMC_BWTR4_ADDSET_0   (0x1UL << FSMC_BWTR4_ADDSET_Pos)
     
    #define FSMC_BWTR4_ADDSET_1   (0x2UL << FSMC_BWTR4_ADDSET_Pos)
     
    #define FSMC_BWTR4_ADDSET_2   (0x4UL << FSMC_BWTR4_ADDSET_Pos)
     
    #define FSMC_BWTR4_ADDSET_3   (0x8UL << FSMC_BWTR4_ADDSET_Pos)
     
    #define FSMC_BWTR4_ADDHLD_Pos   (4U)
     
    #define FSMC_BWTR4_ADDHLD_Msk   (0xFUL << FSMC_BWTR4_ADDHLD_Pos)
     
    #define FSMC_BWTR4_ADDHLD   FSMC_BWTR4_ADDHLD_Msk
     
    #define FSMC_BWTR4_ADDHLD_0   (0x1UL << FSMC_BWTR4_ADDHLD_Pos)
     
    #define FSMC_BWTR4_ADDHLD_1   (0x2UL << FSMC_BWTR4_ADDHLD_Pos)
     
    #define FSMC_BWTR4_ADDHLD_2   (0x4UL << FSMC_BWTR4_ADDHLD_Pos)
     
    #define FSMC_BWTR4_ADDHLD_3   (0x8UL << FSMC_BWTR4_ADDHLD_Pos)
     
    #define FSMC_BWTR4_DATAST_Pos   (8U)
     
    #define FSMC_BWTR4_DATAST_Msk   (0xFFUL << FSMC_BWTR4_DATAST_Pos)
     
    #define FSMC_BWTR4_DATAST   FSMC_BWTR4_DATAST_Msk
     
    #define FSMC_BWTR4_DATAST_0   0x00000100U
     
    #define FSMC_BWTR4_DATAST_1   0x00000200U
     
    #define FSMC_BWTR4_DATAST_2   0x00000400U
     
    #define FSMC_BWTR4_DATAST_3   0x00000800U
     
    #define FSMC_BWTR4_DATAST_4   0x00001000U
     
    #define FSMC_BWTR4_DATAST_5   0x00002000U
     
    #define FSMC_BWTR4_DATAST_6   0x00004000U
     
    #define FSMC_BWTR4_DATAST_7   0x00008000U
     
    #define FSMC_BWTR4_BUSTURN_Pos   (16U)
     
    #define FSMC_BWTR4_BUSTURN_Msk   (0xFUL << FSMC_BWTR4_BUSTURN_Pos)
     
    #define FSMC_BWTR4_BUSTURN   FSMC_BWTR4_BUSTURN_Msk
     
    #define FSMC_BWTR4_BUSTURN_0   (0x1UL << FSMC_BWTR4_BUSTURN_Pos)
     
    #define FSMC_BWTR4_BUSTURN_1   (0x2UL << FSMC_BWTR4_BUSTURN_Pos)
     
    #define FSMC_BWTR4_BUSTURN_2   (0x4UL << FSMC_BWTR4_BUSTURN_Pos)
     
    #define FSMC_BWTR4_BUSTURN_3   (0x8UL << FSMC_BWTR4_BUSTURN_Pos)
     
    #define FSMC_BWTR4_ACCMOD_Pos   (28U)
     
    #define FSMC_BWTR4_ACCMOD_Msk   (0x3UL << FSMC_BWTR4_ACCMOD_Pos)
     
    #define FSMC_BWTR4_ACCMOD   FSMC_BWTR4_ACCMOD_Msk
     
    #define FSMC_BWTR4_ACCMOD_0   (0x1UL << FSMC_BWTR4_ACCMOD_Pos)
     
    #define FSMC_BWTR4_ACCMOD_1   (0x2UL << FSMC_BWTR4_ACCMOD_Pos)
     
    #define FSMC_PCR2_PWAITEN_Pos   (1U)
     
    #define FSMC_PCR2_PWAITEN_Msk   (0x1UL << FSMC_PCR2_PWAITEN_Pos)
     
    #define FSMC_PCR2_PWAITEN   FSMC_PCR2_PWAITEN_Msk
     
    #define FSMC_PCR2_PBKEN_Pos   (2U)
     
    #define FSMC_PCR2_PBKEN_Msk   (0x1UL << FSMC_PCR2_PBKEN_Pos)
     
    #define FSMC_PCR2_PBKEN   FSMC_PCR2_PBKEN_Msk
     
    #define FSMC_PCR2_PTYP_Pos   (3U)
     
    #define FSMC_PCR2_PTYP_Msk   (0x1UL << FSMC_PCR2_PTYP_Pos)
     
    #define FSMC_PCR2_PTYP   FSMC_PCR2_PTYP_Msk
     
    #define FSMC_PCR2_PWID_Pos   (4U)
     
    #define FSMC_PCR2_PWID_Msk   (0x3UL << FSMC_PCR2_PWID_Pos)
     
    #define FSMC_PCR2_PWID   FSMC_PCR2_PWID_Msk
     
    #define FSMC_PCR2_PWID_0   (0x1UL << FSMC_PCR2_PWID_Pos)
     
    #define FSMC_PCR2_PWID_1   (0x2UL << FSMC_PCR2_PWID_Pos)
     
    #define FSMC_PCR2_ECCEN_Pos   (6U)
     
    #define FSMC_PCR2_ECCEN_Msk   (0x1UL << FSMC_PCR2_ECCEN_Pos)
     
    #define FSMC_PCR2_ECCEN   FSMC_PCR2_ECCEN_Msk
     
    #define FSMC_PCR2_TCLR_Pos   (9U)
     
    #define FSMC_PCR2_TCLR_Msk   (0xFUL << FSMC_PCR2_TCLR_Pos)
     
    #define FSMC_PCR2_TCLR   FSMC_PCR2_TCLR_Msk
     
    #define FSMC_PCR2_TCLR_0   (0x1UL << FSMC_PCR2_TCLR_Pos)
     
    #define FSMC_PCR2_TCLR_1   (0x2UL << FSMC_PCR2_TCLR_Pos)
     
    #define FSMC_PCR2_TCLR_2   (0x4UL << FSMC_PCR2_TCLR_Pos)
     
    #define FSMC_PCR2_TCLR_3   (0x8UL << FSMC_PCR2_TCLR_Pos)
     
    #define FSMC_PCR2_TAR_Pos   (13U)
     
    #define FSMC_PCR2_TAR_Msk   (0xFUL << FSMC_PCR2_TAR_Pos)
     
    #define FSMC_PCR2_TAR   FSMC_PCR2_TAR_Msk
     
    #define FSMC_PCR2_TAR_0   (0x1UL << FSMC_PCR2_TAR_Pos)
     
    #define FSMC_PCR2_TAR_1   (0x2UL << FSMC_PCR2_TAR_Pos)
     
    #define FSMC_PCR2_TAR_2   (0x4UL << FSMC_PCR2_TAR_Pos)
     
    #define FSMC_PCR2_TAR_3   (0x8UL << FSMC_PCR2_TAR_Pos)
     
    #define FSMC_PCR2_ECCPS_Pos   (17U)
     
    #define FSMC_PCR2_ECCPS_Msk   (0x7UL << FSMC_PCR2_ECCPS_Pos)
     
    #define FSMC_PCR2_ECCPS   FSMC_PCR2_ECCPS_Msk
     
    #define FSMC_PCR2_ECCPS_0   (0x1UL << FSMC_PCR2_ECCPS_Pos)
     
    #define FSMC_PCR2_ECCPS_1   (0x2UL << FSMC_PCR2_ECCPS_Pos)
     
    #define FSMC_PCR2_ECCPS_2   (0x4UL << FSMC_PCR2_ECCPS_Pos)
     
    #define FSMC_PCR3_PWAITEN_Pos   (1U)
     
    #define FSMC_PCR3_PWAITEN_Msk   (0x1UL << FSMC_PCR3_PWAITEN_Pos)
     
    #define FSMC_PCR3_PWAITEN   FSMC_PCR3_PWAITEN_Msk
     
    #define FSMC_PCR3_PBKEN_Pos   (2U)
     
    #define FSMC_PCR3_PBKEN_Msk   (0x1UL << FSMC_PCR3_PBKEN_Pos)
     
    #define FSMC_PCR3_PBKEN   FSMC_PCR3_PBKEN_Msk
     
    #define FSMC_PCR3_PTYP_Pos   (3U)
     
    #define FSMC_PCR3_PTYP_Msk   (0x1UL << FSMC_PCR3_PTYP_Pos)
     
    #define FSMC_PCR3_PTYP   FSMC_PCR3_PTYP_Msk
     
    #define FSMC_PCR3_PWID_Pos   (4U)
     
    #define FSMC_PCR3_PWID_Msk   (0x3UL << FSMC_PCR3_PWID_Pos)
     
    #define FSMC_PCR3_PWID   FSMC_PCR3_PWID_Msk
     
    #define FSMC_PCR3_PWID_0   (0x1UL << FSMC_PCR3_PWID_Pos)
     
    #define FSMC_PCR3_PWID_1   (0x2UL << FSMC_PCR3_PWID_Pos)
     
    #define FSMC_PCR3_ECCEN_Pos   (6U)
     
    #define FSMC_PCR3_ECCEN_Msk   (0x1UL << FSMC_PCR3_ECCEN_Pos)
     
    #define FSMC_PCR3_ECCEN   FSMC_PCR3_ECCEN_Msk
     
    #define FSMC_PCR3_TCLR_Pos   (9U)
     
    #define FSMC_PCR3_TCLR_Msk   (0xFUL << FSMC_PCR3_TCLR_Pos)
     
    #define FSMC_PCR3_TCLR   FSMC_PCR3_TCLR_Msk
     
    #define FSMC_PCR3_TCLR_0   (0x1UL << FSMC_PCR3_TCLR_Pos)
     
    #define FSMC_PCR3_TCLR_1   (0x2UL << FSMC_PCR3_TCLR_Pos)
     
    #define FSMC_PCR3_TCLR_2   (0x4UL << FSMC_PCR3_TCLR_Pos)
     
    #define FSMC_PCR3_TCLR_3   (0x8UL << FSMC_PCR3_TCLR_Pos)
     
    #define FSMC_PCR3_TAR_Pos   (13U)
     
    #define FSMC_PCR3_TAR_Msk   (0xFUL << FSMC_PCR3_TAR_Pos)
     
    #define FSMC_PCR3_TAR   FSMC_PCR3_TAR_Msk
     
    #define FSMC_PCR3_TAR_0   (0x1UL << FSMC_PCR3_TAR_Pos)
     
    #define FSMC_PCR3_TAR_1   (0x2UL << FSMC_PCR3_TAR_Pos)
     
    #define FSMC_PCR3_TAR_2   (0x4UL << FSMC_PCR3_TAR_Pos)
     
    #define FSMC_PCR3_TAR_3   (0x8UL << FSMC_PCR3_TAR_Pos)
     
    #define FSMC_PCR3_ECCPS_Pos   (17U)
     
    #define FSMC_PCR3_ECCPS_Msk   (0x7UL << FSMC_PCR3_ECCPS_Pos)
     
    #define FSMC_PCR3_ECCPS   FSMC_PCR3_ECCPS_Msk
     
    #define FSMC_PCR3_ECCPS_0   (0x1UL << FSMC_PCR3_ECCPS_Pos)
     
    #define FSMC_PCR3_ECCPS_1   (0x2UL << FSMC_PCR3_ECCPS_Pos)
     
    #define FSMC_PCR3_ECCPS_2   (0x4UL << FSMC_PCR3_ECCPS_Pos)
     
    #define FSMC_PCR4_PWAITEN_Pos   (1U)
     
    #define FSMC_PCR4_PWAITEN_Msk   (0x1UL << FSMC_PCR4_PWAITEN_Pos)
     
    #define FSMC_PCR4_PWAITEN   FSMC_PCR4_PWAITEN_Msk
     
    #define FSMC_PCR4_PBKEN_Pos   (2U)
     
    #define FSMC_PCR4_PBKEN_Msk   (0x1UL << FSMC_PCR4_PBKEN_Pos)
     
    #define FSMC_PCR4_PBKEN   FSMC_PCR4_PBKEN_Msk
     
    #define FSMC_PCR4_PTYP_Pos   (3U)
     
    #define FSMC_PCR4_PTYP_Msk   (0x1UL << FSMC_PCR4_PTYP_Pos)
     
    #define FSMC_PCR4_PTYP   FSMC_PCR4_PTYP_Msk
     
    #define FSMC_PCR4_PWID_Pos   (4U)
     
    #define FSMC_PCR4_PWID_Msk   (0x3UL << FSMC_PCR4_PWID_Pos)
     
    #define FSMC_PCR4_PWID   FSMC_PCR4_PWID_Msk
     
    #define FSMC_PCR4_PWID_0   (0x1UL << FSMC_PCR4_PWID_Pos)
     
    #define FSMC_PCR4_PWID_1   (0x2UL << FSMC_PCR4_PWID_Pos)
     
    #define FSMC_PCR4_ECCEN_Pos   (6U)
     
    #define FSMC_PCR4_ECCEN_Msk   (0x1UL << FSMC_PCR4_ECCEN_Pos)
     
    #define FSMC_PCR4_ECCEN   FSMC_PCR4_ECCEN_Msk
     
    #define FSMC_PCR4_TCLR_Pos   (9U)
     
    #define FSMC_PCR4_TCLR_Msk   (0xFUL << FSMC_PCR4_TCLR_Pos)
     
    #define FSMC_PCR4_TCLR   FSMC_PCR4_TCLR_Msk
     
    #define FSMC_PCR4_TCLR_0   (0x1UL << FSMC_PCR4_TCLR_Pos)
     
    #define FSMC_PCR4_TCLR_1   (0x2UL << FSMC_PCR4_TCLR_Pos)
     
    #define FSMC_PCR4_TCLR_2   (0x4UL << FSMC_PCR4_TCLR_Pos)
     
    #define FSMC_PCR4_TCLR_3   (0x8UL << FSMC_PCR4_TCLR_Pos)
     
    #define FSMC_PCR4_TAR_Pos   (13U)
     
    #define FSMC_PCR4_TAR_Msk   (0xFUL << FSMC_PCR4_TAR_Pos)
     
    #define FSMC_PCR4_TAR   FSMC_PCR4_TAR_Msk
     
    #define FSMC_PCR4_TAR_0   (0x1UL << FSMC_PCR4_TAR_Pos)
     
    #define FSMC_PCR4_TAR_1   (0x2UL << FSMC_PCR4_TAR_Pos)
     
    #define FSMC_PCR4_TAR_2   (0x4UL << FSMC_PCR4_TAR_Pos)
     
    #define FSMC_PCR4_TAR_3   (0x8UL << FSMC_PCR4_TAR_Pos)
     
    #define FSMC_PCR4_ECCPS_Pos   (17U)
     
    #define FSMC_PCR4_ECCPS_Msk   (0x7UL << FSMC_PCR4_ECCPS_Pos)
     
    #define FSMC_PCR4_ECCPS   FSMC_PCR4_ECCPS_Msk
     
    #define FSMC_PCR4_ECCPS_0   (0x1UL << FSMC_PCR4_ECCPS_Pos)
     
    #define FSMC_PCR4_ECCPS_1   (0x2UL << FSMC_PCR4_ECCPS_Pos)
     
    #define FSMC_PCR4_ECCPS_2   (0x4UL << FSMC_PCR4_ECCPS_Pos)
     
    #define FSMC_SR2_IRS_Pos   (0U)
     
    #define FSMC_SR2_IRS_Msk   (0x1UL << FSMC_SR2_IRS_Pos)
     
    #define FSMC_SR2_IRS   FSMC_SR2_IRS_Msk
     
    #define FSMC_SR2_ILS_Pos   (1U)
     
    #define FSMC_SR2_ILS_Msk   (0x1UL << FSMC_SR2_ILS_Pos)
     
    #define FSMC_SR2_ILS   FSMC_SR2_ILS_Msk
     
    #define FSMC_SR2_IFS_Pos   (2U)
     
    #define FSMC_SR2_IFS_Msk   (0x1UL << FSMC_SR2_IFS_Pos)
     
    #define FSMC_SR2_IFS   FSMC_SR2_IFS_Msk
     
    #define FSMC_SR2_IREN_Pos   (3U)
     
    #define FSMC_SR2_IREN_Msk   (0x1UL << FSMC_SR2_IREN_Pos)
     
    #define FSMC_SR2_IREN   FSMC_SR2_IREN_Msk
     
    #define FSMC_SR2_ILEN_Pos   (4U)
     
    #define FSMC_SR2_ILEN_Msk   (0x1UL << FSMC_SR2_ILEN_Pos)
     
    #define FSMC_SR2_ILEN   FSMC_SR2_ILEN_Msk
     
    #define FSMC_SR2_IFEN_Pos   (5U)
     
    #define FSMC_SR2_IFEN_Msk   (0x1UL << FSMC_SR2_IFEN_Pos)
     
    #define FSMC_SR2_IFEN   FSMC_SR2_IFEN_Msk
     
    #define FSMC_SR2_FEMPT_Pos   (6U)
     
    #define FSMC_SR2_FEMPT_Msk   (0x1UL << FSMC_SR2_FEMPT_Pos)
     
    #define FSMC_SR2_FEMPT   FSMC_SR2_FEMPT_Msk
     
    #define FSMC_SR3_IRS_Pos   (0U)
     
    #define FSMC_SR3_IRS_Msk   (0x1UL << FSMC_SR3_IRS_Pos)
     
    #define FSMC_SR3_IRS   FSMC_SR3_IRS_Msk
     
    #define FSMC_SR3_ILS_Pos   (1U)
     
    #define FSMC_SR3_ILS_Msk   (0x1UL << FSMC_SR3_ILS_Pos)
     
    #define FSMC_SR3_ILS   FSMC_SR3_ILS_Msk
     
    #define FSMC_SR3_IFS_Pos   (2U)
     
    #define FSMC_SR3_IFS_Msk   (0x1UL << FSMC_SR3_IFS_Pos)
     
    #define FSMC_SR3_IFS   FSMC_SR3_IFS_Msk
     
    #define FSMC_SR3_IREN_Pos   (3U)
     
    #define FSMC_SR3_IREN_Msk   (0x1UL << FSMC_SR3_IREN_Pos)
     
    #define FSMC_SR3_IREN   FSMC_SR3_IREN_Msk
     
    #define FSMC_SR3_ILEN_Pos   (4U)
     
    #define FSMC_SR3_ILEN_Msk   (0x1UL << FSMC_SR3_ILEN_Pos)
     
    #define FSMC_SR3_ILEN   FSMC_SR3_ILEN_Msk
     
    #define FSMC_SR3_IFEN_Pos   (5U)
     
    #define FSMC_SR3_IFEN_Msk   (0x1UL << FSMC_SR3_IFEN_Pos)
     
    #define FSMC_SR3_IFEN   FSMC_SR3_IFEN_Msk
     
    #define FSMC_SR3_FEMPT_Pos   (6U)
     
    #define FSMC_SR3_FEMPT_Msk   (0x1UL << FSMC_SR3_FEMPT_Pos)
     
    #define FSMC_SR3_FEMPT   FSMC_SR3_FEMPT_Msk
     
    #define FSMC_SR4_IRS_Pos   (0U)
     
    #define FSMC_SR4_IRS_Msk   (0x1UL << FSMC_SR4_IRS_Pos)
     
    #define FSMC_SR4_IRS   FSMC_SR4_IRS_Msk
     
    #define FSMC_SR4_ILS_Pos   (1U)
     
    #define FSMC_SR4_ILS_Msk   (0x1UL << FSMC_SR4_ILS_Pos)
     
    #define FSMC_SR4_ILS   FSMC_SR4_ILS_Msk
     
    #define FSMC_SR4_IFS_Pos   (2U)
     
    #define FSMC_SR4_IFS_Msk   (0x1UL << FSMC_SR4_IFS_Pos)
     
    #define FSMC_SR4_IFS   FSMC_SR4_IFS_Msk
     
    #define FSMC_SR4_IREN_Pos   (3U)
     
    #define FSMC_SR4_IREN_Msk   (0x1UL << FSMC_SR4_IREN_Pos)
     
    #define FSMC_SR4_IREN   FSMC_SR4_IREN_Msk
     
    #define FSMC_SR4_ILEN_Pos   (4U)
     
    #define FSMC_SR4_ILEN_Msk   (0x1UL << FSMC_SR4_ILEN_Pos)
     
    #define FSMC_SR4_ILEN   FSMC_SR4_ILEN_Msk
     
    #define FSMC_SR4_IFEN_Pos   (5U)
     
    #define FSMC_SR4_IFEN_Msk   (0x1UL << FSMC_SR4_IFEN_Pos)
     
    #define FSMC_SR4_IFEN   FSMC_SR4_IFEN_Msk
     
    #define FSMC_SR4_FEMPT_Pos   (6U)
     
    #define FSMC_SR4_FEMPT_Msk   (0x1UL << FSMC_SR4_FEMPT_Pos)
     
    #define FSMC_SR4_FEMPT   FSMC_SR4_FEMPT_Msk
     
    #define FSMC_PMEM2_MEMSET2_Pos   (0U)
     
    #define FSMC_PMEM2_MEMSET2_Msk   (0xFFUL << FSMC_PMEM2_MEMSET2_Pos)
     
    #define FSMC_PMEM2_MEMSET2   FSMC_PMEM2_MEMSET2_Msk
     
    #define FSMC_PMEM2_MEMSET2_0   (0x01UL << FSMC_PMEM2_MEMSET2_Pos)
     
    #define FSMC_PMEM2_MEMSET2_1   (0x02UL << FSMC_PMEM2_MEMSET2_Pos)
     
    #define FSMC_PMEM2_MEMSET2_2   (0x04UL << FSMC_PMEM2_MEMSET2_Pos)
     
    #define FSMC_PMEM2_MEMSET2_3   (0x08UL << FSMC_PMEM2_MEMSET2_Pos)
     
    #define FSMC_PMEM2_MEMSET2_4   (0x10UL << FSMC_PMEM2_MEMSET2_Pos)
     
    #define FSMC_PMEM2_MEMSET2_5   (0x20UL << FSMC_PMEM2_MEMSET2_Pos)
     
    #define FSMC_PMEM2_MEMSET2_6   (0x40UL << FSMC_PMEM2_MEMSET2_Pos)
     
    #define FSMC_PMEM2_MEMSET2_7   (0x80UL << FSMC_PMEM2_MEMSET2_Pos)
     
    #define FSMC_PMEM2_MEMWAIT2_Pos   (8U)
     
    #define FSMC_PMEM2_MEMWAIT2_Msk   (0xFFUL << FSMC_PMEM2_MEMWAIT2_Pos)
     
    #define FSMC_PMEM2_MEMWAIT2   FSMC_PMEM2_MEMWAIT2_Msk
     
    #define FSMC_PMEM2_MEMWAIT2_0   (0x01UL << FSMC_PMEM2_MEMWAIT2_Pos)
     
    #define FSMC_PMEM2_MEMWAIT2_1   (0x02UL << FSMC_PMEM2_MEMWAIT2_Pos)
     
    #define FSMC_PMEM2_MEMWAIT2_2   (0x04UL << FSMC_PMEM2_MEMWAIT2_Pos)
     
    #define FSMC_PMEM2_MEMWAIT2_3   (0x08UL << FSMC_PMEM2_MEMWAIT2_Pos)
     
    #define FSMC_PMEM2_MEMWAIT2_4   (0x10UL << FSMC_PMEM2_MEMWAIT2_Pos)
     
    #define FSMC_PMEM2_MEMWAIT2_5   (0x20UL << FSMC_PMEM2_MEMWAIT2_Pos)
     
    #define FSMC_PMEM2_MEMWAIT2_6   (0x40UL << FSMC_PMEM2_MEMWAIT2_Pos)
     
    #define FSMC_PMEM2_MEMWAIT2_7   (0x80UL << FSMC_PMEM2_MEMWAIT2_Pos)
     
    #define FSMC_PMEM2_MEMHOLD2_Pos   (16U)
     
    #define FSMC_PMEM2_MEMHOLD2_Msk   (0xFFUL << FSMC_PMEM2_MEMHOLD2_Pos)
     
    #define FSMC_PMEM2_MEMHOLD2   FSMC_PMEM2_MEMHOLD2_Msk
     
    #define FSMC_PMEM2_MEMHOLD2_0   (0x01UL << FSMC_PMEM2_MEMHOLD2_Pos)
     
    #define FSMC_PMEM2_MEMHOLD2_1   (0x02UL << FSMC_PMEM2_MEMHOLD2_Pos)
     
    #define FSMC_PMEM2_MEMHOLD2_2   (0x04UL << FSMC_PMEM2_MEMHOLD2_Pos)
     
    #define FSMC_PMEM2_MEMHOLD2_3   (0x08UL << FSMC_PMEM2_MEMHOLD2_Pos)
     
    #define FSMC_PMEM2_MEMHOLD2_4   (0x10UL << FSMC_PMEM2_MEMHOLD2_Pos)
     
    #define FSMC_PMEM2_MEMHOLD2_5   (0x20UL << FSMC_PMEM2_MEMHOLD2_Pos)
     
    #define FSMC_PMEM2_MEMHOLD2_6   (0x40UL << FSMC_PMEM2_MEMHOLD2_Pos)
     
    #define FSMC_PMEM2_MEMHOLD2_7   (0x80UL << FSMC_PMEM2_MEMHOLD2_Pos)
     
    #define FSMC_PMEM2_MEMHIZ2_Pos   (24U)
     
    #define FSMC_PMEM2_MEMHIZ2_Msk   (0xFFUL << FSMC_PMEM2_MEMHIZ2_Pos)
     
    #define FSMC_PMEM2_MEMHIZ2   FSMC_PMEM2_MEMHIZ2_Msk
     
    #define FSMC_PMEM2_MEMHIZ2_0   (0x01UL << FSMC_PMEM2_MEMHIZ2_Pos)
     
    #define FSMC_PMEM2_MEMHIZ2_1   (0x02UL << FSMC_PMEM2_MEMHIZ2_Pos)
     
    #define FSMC_PMEM2_MEMHIZ2_2   (0x04UL << FSMC_PMEM2_MEMHIZ2_Pos)
     
    #define FSMC_PMEM2_MEMHIZ2_3   (0x08UL << FSMC_PMEM2_MEMHIZ2_Pos)
     
    #define FSMC_PMEM2_MEMHIZ2_4   (0x10UL << FSMC_PMEM2_MEMHIZ2_Pos)
     
    #define FSMC_PMEM2_MEMHIZ2_5   (0x20UL << FSMC_PMEM2_MEMHIZ2_Pos)
     
    #define FSMC_PMEM2_MEMHIZ2_6   (0x40UL << FSMC_PMEM2_MEMHIZ2_Pos)
     
    #define FSMC_PMEM2_MEMHIZ2_7   (0x80UL << FSMC_PMEM2_MEMHIZ2_Pos)
     
    #define FSMC_PMEM3_MEMSET3_Pos   (0U)
     
    #define FSMC_PMEM3_MEMSET3_Msk   (0xFFUL << FSMC_PMEM3_MEMSET3_Pos)
     
    #define FSMC_PMEM3_MEMSET3   FSMC_PMEM3_MEMSET3_Msk
     
    #define FSMC_PMEM3_MEMSET3_0   (0x01UL << FSMC_PMEM3_MEMSET3_Pos)
     
    #define FSMC_PMEM3_MEMSET3_1   (0x02UL << FSMC_PMEM3_MEMSET3_Pos)
     
    #define FSMC_PMEM3_MEMSET3_2   (0x04UL << FSMC_PMEM3_MEMSET3_Pos)
     
    #define FSMC_PMEM3_MEMSET3_3   (0x08UL << FSMC_PMEM3_MEMSET3_Pos)
     
    #define FSMC_PMEM3_MEMSET3_4   (0x10UL << FSMC_PMEM3_MEMSET3_Pos)
     
    #define FSMC_PMEM3_MEMSET3_5   (0x20UL << FSMC_PMEM3_MEMSET3_Pos)
     
    #define FSMC_PMEM3_MEMSET3_6   (0x40UL << FSMC_PMEM3_MEMSET3_Pos)
     
    #define FSMC_PMEM3_MEMSET3_7   (0x80UL << FSMC_PMEM3_MEMSET3_Pos)
     
    #define FSMC_PMEM3_MEMWAIT3_Pos   (8U)
     
    #define FSMC_PMEM3_MEMWAIT3_Msk   (0xFFUL << FSMC_PMEM3_MEMWAIT3_Pos)
     
    #define FSMC_PMEM3_MEMWAIT3   FSMC_PMEM3_MEMWAIT3_Msk
     
    #define FSMC_PMEM3_MEMWAIT3_0   (0x01UL << FSMC_PMEM3_MEMWAIT3_Pos)
     
    #define FSMC_PMEM3_MEMWAIT3_1   (0x02UL << FSMC_PMEM3_MEMWAIT3_Pos)
     
    #define FSMC_PMEM3_MEMWAIT3_2   (0x04UL << FSMC_PMEM3_MEMWAIT3_Pos)
     
    #define FSMC_PMEM3_MEMWAIT3_3   (0x08UL << FSMC_PMEM3_MEMWAIT3_Pos)
     
    #define FSMC_PMEM3_MEMWAIT3_4   (0x10UL << FSMC_PMEM3_MEMWAIT3_Pos)
     
    #define FSMC_PMEM3_MEMWAIT3_5   (0x20UL << FSMC_PMEM3_MEMWAIT3_Pos)
     
    #define FSMC_PMEM3_MEMWAIT3_6   (0x40UL << FSMC_PMEM3_MEMWAIT3_Pos)
     
    #define FSMC_PMEM3_MEMWAIT3_7   (0x80UL << FSMC_PMEM3_MEMWAIT3_Pos)
     
    #define FSMC_PMEM3_MEMHOLD3_Pos   (16U)
     
    #define FSMC_PMEM3_MEMHOLD3_Msk   (0xFFUL << FSMC_PMEM3_MEMHOLD3_Pos)
     
    #define FSMC_PMEM3_MEMHOLD3   FSMC_PMEM3_MEMHOLD3_Msk
     
    #define FSMC_PMEM3_MEMHOLD3_0   (0x01UL << FSMC_PMEM3_MEMHOLD3_Pos)
     
    #define FSMC_PMEM3_MEMHOLD3_1   (0x02UL << FSMC_PMEM3_MEMHOLD3_Pos)
     
    #define FSMC_PMEM3_MEMHOLD3_2   (0x04UL << FSMC_PMEM3_MEMHOLD3_Pos)
     
    #define FSMC_PMEM3_MEMHOLD3_3   (0x08UL << FSMC_PMEM3_MEMHOLD3_Pos)
     
    #define FSMC_PMEM3_MEMHOLD3_4   (0x10UL << FSMC_PMEM3_MEMHOLD3_Pos)
     
    #define FSMC_PMEM3_MEMHOLD3_5   (0x20UL << FSMC_PMEM3_MEMHOLD3_Pos)
     
    #define FSMC_PMEM3_MEMHOLD3_6   (0x40UL << FSMC_PMEM3_MEMHOLD3_Pos)
     
    #define FSMC_PMEM3_MEMHOLD3_7   (0x80UL << FSMC_PMEM3_MEMHOLD3_Pos)
     
    #define FSMC_PMEM3_MEMHIZ3_Pos   (24U)
     
    #define FSMC_PMEM3_MEMHIZ3_Msk   (0xFFUL << FSMC_PMEM3_MEMHIZ3_Pos)
     
    #define FSMC_PMEM3_MEMHIZ3   FSMC_PMEM3_MEMHIZ3_Msk
     
    #define FSMC_PMEM3_MEMHIZ3_0   (0x01UL << FSMC_PMEM3_MEMHIZ3_Pos)
     
    #define FSMC_PMEM3_MEMHIZ3_1   (0x02UL << FSMC_PMEM3_MEMHIZ3_Pos)
     
    #define FSMC_PMEM3_MEMHIZ3_2   (0x04UL << FSMC_PMEM3_MEMHIZ3_Pos)
     
    #define FSMC_PMEM3_MEMHIZ3_3   (0x08UL << FSMC_PMEM3_MEMHIZ3_Pos)
     
    #define FSMC_PMEM3_MEMHIZ3_4   (0x10UL << FSMC_PMEM3_MEMHIZ3_Pos)
     
    #define FSMC_PMEM3_MEMHIZ3_5   (0x20UL << FSMC_PMEM3_MEMHIZ3_Pos)
     
    #define FSMC_PMEM3_MEMHIZ3_6   (0x40UL << FSMC_PMEM3_MEMHIZ3_Pos)
     
    #define FSMC_PMEM3_MEMHIZ3_7   (0x80UL << FSMC_PMEM3_MEMHIZ3_Pos)
     
    #define FSMC_PMEM4_MEMSET4_Pos   (0U)
     
    #define FSMC_PMEM4_MEMSET4_Msk   (0xFFUL << FSMC_PMEM4_MEMSET4_Pos)
     
    #define FSMC_PMEM4_MEMSET4   FSMC_PMEM4_MEMSET4_Msk
     
    #define FSMC_PMEM4_MEMSET4_0   (0x01UL << FSMC_PMEM4_MEMSET4_Pos)
     
    #define FSMC_PMEM4_MEMSET4_1   (0x02UL << FSMC_PMEM4_MEMSET4_Pos)
     
    #define FSMC_PMEM4_MEMSET4_2   (0x04UL << FSMC_PMEM4_MEMSET4_Pos)
     
    #define FSMC_PMEM4_MEMSET4_3   (0x08UL << FSMC_PMEM4_MEMSET4_Pos)
     
    #define FSMC_PMEM4_MEMSET4_4   (0x10UL << FSMC_PMEM4_MEMSET4_Pos)
     
    #define FSMC_PMEM4_MEMSET4_5   (0x20UL << FSMC_PMEM4_MEMSET4_Pos)
     
    #define FSMC_PMEM4_MEMSET4_6   (0x40UL << FSMC_PMEM4_MEMSET4_Pos)
     
    #define FSMC_PMEM4_MEMSET4_7   (0x80UL << FSMC_PMEM4_MEMSET4_Pos)
     
    #define FSMC_PMEM4_MEMWAIT4_Pos   (8U)
     
    #define FSMC_PMEM4_MEMWAIT4_Msk   (0xFFUL << FSMC_PMEM4_MEMWAIT4_Pos)
     
    #define FSMC_PMEM4_MEMWAIT4   FSMC_PMEM4_MEMWAIT4_Msk
     
    #define FSMC_PMEM4_MEMWAIT4_0   (0x01UL << FSMC_PMEM4_MEMWAIT4_Pos)
     
    #define FSMC_PMEM4_MEMWAIT4_1   (0x02UL << FSMC_PMEM4_MEMWAIT4_Pos)
     
    #define FSMC_PMEM4_MEMWAIT4_2   (0x04UL << FSMC_PMEM4_MEMWAIT4_Pos)
     
    #define FSMC_PMEM4_MEMWAIT4_3   (0x08UL << FSMC_PMEM4_MEMWAIT4_Pos)
     
    #define FSMC_PMEM4_MEMWAIT4_4   (0x10UL << FSMC_PMEM4_MEMWAIT4_Pos)
     
    #define FSMC_PMEM4_MEMWAIT4_5   (0x20UL << FSMC_PMEM4_MEMWAIT4_Pos)
     
    #define FSMC_PMEM4_MEMWAIT4_6   (0x40UL << FSMC_PMEM4_MEMWAIT4_Pos)
     
    #define FSMC_PMEM4_MEMWAIT4_7   (0x80UL << FSMC_PMEM4_MEMWAIT4_Pos)
     
    #define FSMC_PMEM4_MEMHOLD4_Pos   (16U)
     
    #define FSMC_PMEM4_MEMHOLD4_Msk   (0xFFUL << FSMC_PMEM4_MEMHOLD4_Pos)
     
    #define FSMC_PMEM4_MEMHOLD4   FSMC_PMEM4_MEMHOLD4_Msk
     
    #define FSMC_PMEM4_MEMHOLD4_0   (0x01UL << FSMC_PMEM4_MEMHOLD4_Pos)
     
    #define FSMC_PMEM4_MEMHOLD4_1   (0x02UL << FSMC_PMEM4_MEMHOLD4_Pos)
     
    #define FSMC_PMEM4_MEMHOLD4_2   (0x04UL << FSMC_PMEM4_MEMHOLD4_Pos)
     
    #define FSMC_PMEM4_MEMHOLD4_3   (0x08UL << FSMC_PMEM4_MEMHOLD4_Pos)
     
    #define FSMC_PMEM4_MEMHOLD4_4   (0x10UL << FSMC_PMEM4_MEMHOLD4_Pos)
     
    #define FSMC_PMEM4_MEMHOLD4_5   (0x20UL << FSMC_PMEM4_MEMHOLD4_Pos)
     
    #define FSMC_PMEM4_MEMHOLD4_6   (0x40UL << FSMC_PMEM4_MEMHOLD4_Pos)
     
    #define FSMC_PMEM4_MEMHOLD4_7   (0x80UL << FSMC_PMEM4_MEMHOLD4_Pos)
     
    #define FSMC_PMEM4_MEMHIZ4_Pos   (24U)
     
    #define FSMC_PMEM4_MEMHIZ4_Msk   (0xFFUL << FSMC_PMEM4_MEMHIZ4_Pos)
     
    #define FSMC_PMEM4_MEMHIZ4   FSMC_PMEM4_MEMHIZ4_Msk
     
    #define FSMC_PMEM4_MEMHIZ4_0   (0x01UL << FSMC_PMEM4_MEMHIZ4_Pos)
     
    #define FSMC_PMEM4_MEMHIZ4_1   (0x02UL << FSMC_PMEM4_MEMHIZ4_Pos)
     
    #define FSMC_PMEM4_MEMHIZ4_2   (0x04UL << FSMC_PMEM4_MEMHIZ4_Pos)
     
    #define FSMC_PMEM4_MEMHIZ4_3   (0x08UL << FSMC_PMEM4_MEMHIZ4_Pos)
     
    #define FSMC_PMEM4_MEMHIZ4_4   (0x10UL << FSMC_PMEM4_MEMHIZ4_Pos)
     
    #define FSMC_PMEM4_MEMHIZ4_5   (0x20UL << FSMC_PMEM4_MEMHIZ4_Pos)
     
    #define FSMC_PMEM4_MEMHIZ4_6   (0x40UL << FSMC_PMEM4_MEMHIZ4_Pos)
     
    #define FSMC_PMEM4_MEMHIZ4_7   (0x80UL << FSMC_PMEM4_MEMHIZ4_Pos)
     
    #define FSMC_PATT2_ATTSET2_Pos   (0U)
     
    #define FSMC_PATT2_ATTSET2_Msk   (0xFFUL << FSMC_PATT2_ATTSET2_Pos)
     
    #define FSMC_PATT2_ATTSET2   FSMC_PATT2_ATTSET2_Msk
     
    #define FSMC_PATT2_ATTSET2_0   (0x01UL << FSMC_PATT2_ATTSET2_Pos)
     
    #define FSMC_PATT2_ATTSET2_1   (0x02UL << FSMC_PATT2_ATTSET2_Pos)
     
    #define FSMC_PATT2_ATTSET2_2   (0x04UL << FSMC_PATT2_ATTSET2_Pos)
     
    #define FSMC_PATT2_ATTSET2_3   (0x08UL << FSMC_PATT2_ATTSET2_Pos)
     
    #define FSMC_PATT2_ATTSET2_4   (0x10UL << FSMC_PATT2_ATTSET2_Pos)
     
    #define FSMC_PATT2_ATTSET2_5   (0x20UL << FSMC_PATT2_ATTSET2_Pos)
     
    #define FSMC_PATT2_ATTSET2_6   (0x40UL << FSMC_PATT2_ATTSET2_Pos)
     
    #define FSMC_PATT2_ATTSET2_7   (0x80UL << FSMC_PATT2_ATTSET2_Pos)
     
    #define FSMC_PATT2_ATTWAIT2_Pos   (8U)
     
    #define FSMC_PATT2_ATTWAIT2_Msk   (0xFFUL << FSMC_PATT2_ATTWAIT2_Pos)
     
    #define FSMC_PATT2_ATTWAIT2   FSMC_PATT2_ATTWAIT2_Msk
     
    #define FSMC_PATT2_ATTWAIT2_0   (0x01UL << FSMC_PATT2_ATTWAIT2_Pos)
     
    #define FSMC_PATT2_ATTWAIT2_1   (0x02UL << FSMC_PATT2_ATTWAIT2_Pos)
     
    #define FSMC_PATT2_ATTWAIT2_2   (0x04UL << FSMC_PATT2_ATTWAIT2_Pos)
     
    #define FSMC_PATT2_ATTWAIT2_3   (0x08UL << FSMC_PATT2_ATTWAIT2_Pos)
     
    #define FSMC_PATT2_ATTWAIT2_4   (0x10UL << FSMC_PATT2_ATTWAIT2_Pos)
     
    #define FSMC_PATT2_ATTWAIT2_5   (0x20UL << FSMC_PATT2_ATTWAIT2_Pos)
     
    #define FSMC_PATT2_ATTWAIT2_6   (0x40UL << FSMC_PATT2_ATTWAIT2_Pos)
     
    #define FSMC_PATT2_ATTWAIT2_7   (0x80UL << FSMC_PATT2_ATTWAIT2_Pos)
     
    #define FSMC_PATT2_ATTHOLD2_Pos   (16U)
     
    #define FSMC_PATT2_ATTHOLD2_Msk   (0xFFUL << FSMC_PATT2_ATTHOLD2_Pos)
     
    #define FSMC_PATT2_ATTHOLD2   FSMC_PATT2_ATTHOLD2_Msk
     
    #define FSMC_PATT2_ATTHOLD2_0   (0x01UL << FSMC_PATT2_ATTHOLD2_Pos)
     
    #define FSMC_PATT2_ATTHOLD2_1   (0x02UL << FSMC_PATT2_ATTHOLD2_Pos)
     
    #define FSMC_PATT2_ATTHOLD2_2   (0x04UL << FSMC_PATT2_ATTHOLD2_Pos)
     
    #define FSMC_PATT2_ATTHOLD2_3   (0x08UL << FSMC_PATT2_ATTHOLD2_Pos)
     
    #define FSMC_PATT2_ATTHOLD2_4   (0x10UL << FSMC_PATT2_ATTHOLD2_Pos)
     
    #define FSMC_PATT2_ATTHOLD2_5   (0x20UL << FSMC_PATT2_ATTHOLD2_Pos)
     
    #define FSMC_PATT2_ATTHOLD2_6   (0x40UL << FSMC_PATT2_ATTHOLD2_Pos)
     
    #define FSMC_PATT2_ATTHOLD2_7   (0x80UL << FSMC_PATT2_ATTHOLD2_Pos)
     
    #define FSMC_PATT2_ATTHIZ2_Pos   (24U)
     
    #define FSMC_PATT2_ATTHIZ2_Msk   (0xFFUL << FSMC_PATT2_ATTHIZ2_Pos)
     
    #define FSMC_PATT2_ATTHIZ2   FSMC_PATT2_ATTHIZ2_Msk
     
    #define FSMC_PATT2_ATTHIZ2_0   (0x01UL << FSMC_PATT2_ATTHIZ2_Pos)
     
    #define FSMC_PATT2_ATTHIZ2_1   (0x02UL << FSMC_PATT2_ATTHIZ2_Pos)
     
    #define FSMC_PATT2_ATTHIZ2_2   (0x04UL << FSMC_PATT2_ATTHIZ2_Pos)
     
    #define FSMC_PATT2_ATTHIZ2_3   (0x08UL << FSMC_PATT2_ATTHIZ2_Pos)
     
    #define FSMC_PATT2_ATTHIZ2_4   (0x10UL << FSMC_PATT2_ATTHIZ2_Pos)
     
    #define FSMC_PATT2_ATTHIZ2_5   (0x20UL << FSMC_PATT2_ATTHIZ2_Pos)
     
    #define FSMC_PATT2_ATTHIZ2_6   (0x40UL << FSMC_PATT2_ATTHIZ2_Pos)
     
    #define FSMC_PATT2_ATTHIZ2_7   (0x80UL << FSMC_PATT2_ATTHIZ2_Pos)
     
    #define FSMC_PATT3_ATTSET3_Pos   (0U)
     
    #define FSMC_PATT3_ATTSET3_Msk   (0xFFUL << FSMC_PATT3_ATTSET3_Pos)
     
    #define FSMC_PATT3_ATTSET3   FSMC_PATT3_ATTSET3_Msk
     
    #define FSMC_PATT3_ATTSET3_0   (0x01UL << FSMC_PATT3_ATTSET3_Pos)
     
    #define FSMC_PATT3_ATTSET3_1   (0x02UL << FSMC_PATT3_ATTSET3_Pos)
     
    #define FSMC_PATT3_ATTSET3_2   (0x04UL << FSMC_PATT3_ATTSET3_Pos)
     
    #define FSMC_PATT3_ATTSET3_3   (0x08UL << FSMC_PATT3_ATTSET3_Pos)
     
    #define FSMC_PATT3_ATTSET3_4   (0x10UL << FSMC_PATT3_ATTSET3_Pos)
     
    #define FSMC_PATT3_ATTSET3_5   (0x20UL << FSMC_PATT3_ATTSET3_Pos)
     
    #define FSMC_PATT3_ATTSET3_6   (0x40UL << FSMC_PATT3_ATTSET3_Pos)
     
    #define FSMC_PATT3_ATTSET3_7   (0x80UL << FSMC_PATT3_ATTSET3_Pos)
     
    #define FSMC_PATT3_ATTWAIT3_Pos   (8U)
     
    #define FSMC_PATT3_ATTWAIT3_Msk   (0xFFUL << FSMC_PATT3_ATTWAIT3_Pos)
     
    #define FSMC_PATT3_ATTWAIT3   FSMC_PATT3_ATTWAIT3_Msk
     
    #define FSMC_PATT3_ATTWAIT3_0   (0x01UL << FSMC_PATT3_ATTWAIT3_Pos)
     
    #define FSMC_PATT3_ATTWAIT3_1   (0x02UL << FSMC_PATT3_ATTWAIT3_Pos)
     
    #define FSMC_PATT3_ATTWAIT3_2   (0x04UL << FSMC_PATT3_ATTWAIT3_Pos)
     
    #define FSMC_PATT3_ATTWAIT3_3   (0x08UL << FSMC_PATT3_ATTWAIT3_Pos)
     
    #define FSMC_PATT3_ATTWAIT3_4   (0x10UL << FSMC_PATT3_ATTWAIT3_Pos)
     
    #define FSMC_PATT3_ATTWAIT3_5   (0x20UL << FSMC_PATT3_ATTWAIT3_Pos)
     
    #define FSMC_PATT3_ATTWAIT3_6   (0x40UL << FSMC_PATT3_ATTWAIT3_Pos)
     
    #define FSMC_PATT3_ATTWAIT3_7   (0x80UL << FSMC_PATT3_ATTWAIT3_Pos)
     
    #define FSMC_PATT3_ATTHOLD3_Pos   (16U)
     
    #define FSMC_PATT3_ATTHOLD3_Msk   (0xFFUL << FSMC_PATT3_ATTHOLD3_Pos)
     
    #define FSMC_PATT3_ATTHOLD3   FSMC_PATT3_ATTHOLD3_Msk
     
    #define FSMC_PATT3_ATTHOLD3_0   (0x01UL << FSMC_PATT3_ATTHOLD3_Pos)
     
    #define FSMC_PATT3_ATTHOLD3_1   (0x02UL << FSMC_PATT3_ATTHOLD3_Pos)
     
    #define FSMC_PATT3_ATTHOLD3_2   (0x04UL << FSMC_PATT3_ATTHOLD3_Pos)
     
    #define FSMC_PATT3_ATTHOLD3_3   (0x08UL << FSMC_PATT3_ATTHOLD3_Pos)
     
    #define FSMC_PATT3_ATTHOLD3_4   (0x10UL << FSMC_PATT3_ATTHOLD3_Pos)
     
    #define FSMC_PATT3_ATTHOLD3_5   (0x20UL << FSMC_PATT3_ATTHOLD3_Pos)
     
    #define FSMC_PATT3_ATTHOLD3_6   (0x40UL << FSMC_PATT3_ATTHOLD3_Pos)
     
    #define FSMC_PATT3_ATTHOLD3_7   (0x80UL << FSMC_PATT3_ATTHOLD3_Pos)
     
    #define FSMC_PATT3_ATTHIZ3_Pos   (24U)
     
    #define FSMC_PATT3_ATTHIZ3_Msk   (0xFFUL << FSMC_PATT3_ATTHIZ3_Pos)
     
    #define FSMC_PATT3_ATTHIZ3   FSMC_PATT3_ATTHIZ3_Msk
     
    #define FSMC_PATT3_ATTHIZ3_0   (0x01UL << FSMC_PATT3_ATTHIZ3_Pos)
     
    #define FSMC_PATT3_ATTHIZ3_1   (0x02UL << FSMC_PATT3_ATTHIZ3_Pos)
     
    #define FSMC_PATT3_ATTHIZ3_2   (0x04UL << FSMC_PATT3_ATTHIZ3_Pos)
     
    #define FSMC_PATT3_ATTHIZ3_3   (0x08UL << FSMC_PATT3_ATTHIZ3_Pos)
     
    #define FSMC_PATT3_ATTHIZ3_4   (0x10UL << FSMC_PATT3_ATTHIZ3_Pos)
     
    #define FSMC_PATT3_ATTHIZ3_5   (0x20UL << FSMC_PATT3_ATTHIZ3_Pos)
     
    #define FSMC_PATT3_ATTHIZ3_6   (0x40UL << FSMC_PATT3_ATTHIZ3_Pos)
     
    #define FSMC_PATT3_ATTHIZ3_7   (0x80UL << FSMC_PATT3_ATTHIZ3_Pos)
     
    #define FSMC_PATT4_ATTSET4_Pos   (0U)
     
    #define FSMC_PATT4_ATTSET4_Msk   (0xFFUL << FSMC_PATT4_ATTSET4_Pos)
     
    #define FSMC_PATT4_ATTSET4   FSMC_PATT4_ATTSET4_Msk
     
    #define FSMC_PATT4_ATTSET4_0   (0x01UL << FSMC_PATT4_ATTSET4_Pos)
     
    #define FSMC_PATT4_ATTSET4_1   (0x02UL << FSMC_PATT4_ATTSET4_Pos)
     
    #define FSMC_PATT4_ATTSET4_2   (0x04UL << FSMC_PATT4_ATTSET4_Pos)
     
    #define FSMC_PATT4_ATTSET4_3   (0x08UL << FSMC_PATT4_ATTSET4_Pos)
     
    #define FSMC_PATT4_ATTSET4_4   (0x10UL << FSMC_PATT4_ATTSET4_Pos)
     
    #define FSMC_PATT4_ATTSET4_5   (0x20UL << FSMC_PATT4_ATTSET4_Pos)
     
    #define FSMC_PATT4_ATTSET4_6   (0x40UL << FSMC_PATT4_ATTSET4_Pos)
     
    #define FSMC_PATT4_ATTSET4_7   (0x80UL << FSMC_PATT4_ATTSET4_Pos)
     
    #define FSMC_PATT4_ATTWAIT4_Pos   (8U)
     
    #define FSMC_PATT4_ATTWAIT4_Msk   (0xFFUL << FSMC_PATT4_ATTWAIT4_Pos)
     
    #define FSMC_PATT4_ATTWAIT4   FSMC_PATT4_ATTWAIT4_Msk
     
    #define FSMC_PATT4_ATTWAIT4_0   (0x01UL << FSMC_PATT4_ATTWAIT4_Pos)
     
    #define FSMC_PATT4_ATTWAIT4_1   (0x02UL << FSMC_PATT4_ATTWAIT4_Pos)
     
    #define FSMC_PATT4_ATTWAIT4_2   (0x04UL << FSMC_PATT4_ATTWAIT4_Pos)
     
    #define FSMC_PATT4_ATTWAIT4_3   (0x08UL << FSMC_PATT4_ATTWAIT4_Pos)
     
    #define FSMC_PATT4_ATTWAIT4_4   (0x10UL << FSMC_PATT4_ATTWAIT4_Pos)
     
    #define FSMC_PATT4_ATTWAIT4_5   (0x20UL << FSMC_PATT4_ATTWAIT4_Pos)
     
    #define FSMC_PATT4_ATTWAIT4_6   (0x40UL << FSMC_PATT4_ATTWAIT4_Pos)
     
    #define FSMC_PATT4_ATTWAIT4_7   (0x80UL << FSMC_PATT4_ATTWAIT4_Pos)
     
    #define FSMC_PATT4_ATTHOLD4_Pos   (16U)
     
    #define FSMC_PATT4_ATTHOLD4_Msk   (0xFFUL << FSMC_PATT4_ATTHOLD4_Pos)
     
    #define FSMC_PATT4_ATTHOLD4   FSMC_PATT4_ATTHOLD4_Msk
     
    #define FSMC_PATT4_ATTHOLD4_0   (0x01UL << FSMC_PATT4_ATTHOLD4_Pos)
     
    #define FSMC_PATT4_ATTHOLD4_1   (0x02UL << FSMC_PATT4_ATTHOLD4_Pos)
     
    #define FSMC_PATT4_ATTHOLD4_2   (0x04UL << FSMC_PATT4_ATTHOLD4_Pos)
     
    #define FSMC_PATT4_ATTHOLD4_3   (0x08UL << FSMC_PATT4_ATTHOLD4_Pos)
     
    #define FSMC_PATT4_ATTHOLD4_4   (0x10UL << FSMC_PATT4_ATTHOLD4_Pos)
     
    #define FSMC_PATT4_ATTHOLD4_5   (0x20UL << FSMC_PATT4_ATTHOLD4_Pos)
     
    #define FSMC_PATT4_ATTHOLD4_6   (0x40UL << FSMC_PATT4_ATTHOLD4_Pos)
     
    #define FSMC_PATT4_ATTHOLD4_7   (0x80UL << FSMC_PATT4_ATTHOLD4_Pos)
     
    #define FSMC_PATT4_ATTHIZ4_Pos   (24U)
     
    #define FSMC_PATT4_ATTHIZ4_Msk   (0xFFUL << FSMC_PATT4_ATTHIZ4_Pos)
     
    #define FSMC_PATT4_ATTHIZ4   FSMC_PATT4_ATTHIZ4_Msk
     
    #define FSMC_PATT4_ATTHIZ4_0   (0x01UL << FSMC_PATT4_ATTHIZ4_Pos)
     
    #define FSMC_PATT4_ATTHIZ4_1   (0x02UL << FSMC_PATT4_ATTHIZ4_Pos)
     
    #define FSMC_PATT4_ATTHIZ4_2   (0x04UL << FSMC_PATT4_ATTHIZ4_Pos)
     
    #define FSMC_PATT4_ATTHIZ4_3   (0x08UL << FSMC_PATT4_ATTHIZ4_Pos)
     
    #define FSMC_PATT4_ATTHIZ4_4   (0x10UL << FSMC_PATT4_ATTHIZ4_Pos)
     
    #define FSMC_PATT4_ATTHIZ4_5   (0x20UL << FSMC_PATT4_ATTHIZ4_Pos)
     
    #define FSMC_PATT4_ATTHIZ4_6   (0x40UL << FSMC_PATT4_ATTHIZ4_Pos)
     
    #define FSMC_PATT4_ATTHIZ4_7   (0x80UL << FSMC_PATT4_ATTHIZ4_Pos)
     
    #define FSMC_PIO4_IOSET4_Pos   (0U)
     
    #define FSMC_PIO4_IOSET4_Msk   (0xFFUL << FSMC_PIO4_IOSET4_Pos)
     
    #define FSMC_PIO4_IOSET4   FSMC_PIO4_IOSET4_Msk
     
    #define FSMC_PIO4_IOSET4_0   (0x01UL << FSMC_PIO4_IOSET4_Pos)
     
    #define FSMC_PIO4_IOSET4_1   (0x02UL << FSMC_PIO4_IOSET4_Pos)
     
    #define FSMC_PIO4_IOSET4_2   (0x04UL << FSMC_PIO4_IOSET4_Pos)
     
    #define FSMC_PIO4_IOSET4_3   (0x08UL << FSMC_PIO4_IOSET4_Pos)
     
    #define FSMC_PIO4_IOSET4_4   (0x10UL << FSMC_PIO4_IOSET4_Pos)
     
    #define FSMC_PIO4_IOSET4_5   (0x20UL << FSMC_PIO4_IOSET4_Pos)
     
    #define FSMC_PIO4_IOSET4_6   (0x40UL << FSMC_PIO4_IOSET4_Pos)
     
    #define FSMC_PIO4_IOSET4_7   (0x80UL << FSMC_PIO4_IOSET4_Pos)
     
    #define FSMC_PIO4_IOWAIT4_Pos   (8U)
     
    #define FSMC_PIO4_IOWAIT4_Msk   (0xFFUL << FSMC_PIO4_IOWAIT4_Pos)
     
    #define FSMC_PIO4_IOWAIT4   FSMC_PIO4_IOWAIT4_Msk
     
    #define FSMC_PIO4_IOWAIT4_0   (0x01UL << FSMC_PIO4_IOWAIT4_Pos)
     
    #define FSMC_PIO4_IOWAIT4_1   (0x02UL << FSMC_PIO4_IOWAIT4_Pos)
     
    #define FSMC_PIO4_IOWAIT4_2   (0x04UL << FSMC_PIO4_IOWAIT4_Pos)
     
    #define FSMC_PIO4_IOWAIT4_3   (0x08UL << FSMC_PIO4_IOWAIT4_Pos)
     
    #define FSMC_PIO4_IOWAIT4_4   (0x10UL << FSMC_PIO4_IOWAIT4_Pos)
     
    #define FSMC_PIO4_IOWAIT4_5   (0x20UL << FSMC_PIO4_IOWAIT4_Pos)
     
    #define FSMC_PIO4_IOWAIT4_6   (0x40UL << FSMC_PIO4_IOWAIT4_Pos)
     
    #define FSMC_PIO4_IOWAIT4_7   (0x80UL << FSMC_PIO4_IOWAIT4_Pos)
     
    #define FSMC_PIO4_IOHOLD4_Pos   (16U)
     
    #define FSMC_PIO4_IOHOLD4_Msk   (0xFFUL << FSMC_PIO4_IOHOLD4_Pos)
     
    #define FSMC_PIO4_IOHOLD4   FSMC_PIO4_IOHOLD4_Msk
     
    #define FSMC_PIO4_IOHOLD4_0   (0x01UL << FSMC_PIO4_IOHOLD4_Pos)
     
    #define FSMC_PIO4_IOHOLD4_1   (0x02UL << FSMC_PIO4_IOHOLD4_Pos)
     
    #define FSMC_PIO4_IOHOLD4_2   (0x04UL << FSMC_PIO4_IOHOLD4_Pos)
     
    #define FSMC_PIO4_IOHOLD4_3   (0x08UL << FSMC_PIO4_IOHOLD4_Pos)
     
    #define FSMC_PIO4_IOHOLD4_4   (0x10UL << FSMC_PIO4_IOHOLD4_Pos)
     
    #define FSMC_PIO4_IOHOLD4_5   (0x20UL << FSMC_PIO4_IOHOLD4_Pos)
     
    #define FSMC_PIO4_IOHOLD4_6   (0x40UL << FSMC_PIO4_IOHOLD4_Pos)
     
    #define FSMC_PIO4_IOHOLD4_7   (0x80UL << FSMC_PIO4_IOHOLD4_Pos)
     
    #define FSMC_PIO4_IOHIZ4_Pos   (24U)
     
    #define FSMC_PIO4_IOHIZ4_Msk   (0xFFUL << FSMC_PIO4_IOHIZ4_Pos)
     
    #define FSMC_PIO4_IOHIZ4   FSMC_PIO4_IOHIZ4_Msk
     
    #define FSMC_PIO4_IOHIZ4_0   (0x01UL << FSMC_PIO4_IOHIZ4_Pos)
     
    #define FSMC_PIO4_IOHIZ4_1   (0x02UL << FSMC_PIO4_IOHIZ4_Pos)
     
    #define FSMC_PIO4_IOHIZ4_2   (0x04UL << FSMC_PIO4_IOHIZ4_Pos)
     
    #define FSMC_PIO4_IOHIZ4_3   (0x08UL << FSMC_PIO4_IOHIZ4_Pos)
     
    #define FSMC_PIO4_IOHIZ4_4   (0x10UL << FSMC_PIO4_IOHIZ4_Pos)
     
    #define FSMC_PIO4_IOHIZ4_5   (0x20UL << FSMC_PIO4_IOHIZ4_Pos)
     
    #define FSMC_PIO4_IOHIZ4_6   (0x40UL << FSMC_PIO4_IOHIZ4_Pos)
     
    #define FSMC_PIO4_IOHIZ4_7   (0x80UL << FSMC_PIO4_IOHIZ4_Pos)
     
    #define FSMC_ECCR2_ECC2_Pos   (0U)
     
    #define FSMC_ECCR2_ECC2_Msk   (0xFFFFFFFFUL << FSMC_ECCR2_ECC2_Pos)
     
    #define FSMC_ECCR2_ECC2   FSMC_ECCR2_ECC2_Msk
     
    #define FSMC_ECCR3_ECC3_Pos   (0U)
     
    #define FSMC_ECCR3_ECC3_Msk   (0xFFFFFFFFUL << FSMC_ECCR3_ECC3_Pos)
     
    #define FSMC_ECCR3_ECC3   FSMC_ECCR3_ECC3_Msk
     
    #define GPIO_MODER_MODER0_Pos   (0U)
     
    #define GPIO_MODER_MODER0_Msk   (0x3UL << GPIO_MODER_MODER0_Pos)
     
    #define GPIO_MODER_MODER0   GPIO_MODER_MODER0_Msk
     
    #define GPIO_MODER_MODER0_0   (0x1UL << GPIO_MODER_MODER0_Pos)
     
    #define GPIO_MODER_MODER0_1   (0x2UL << GPIO_MODER_MODER0_Pos)
     
    #define GPIO_MODER_MODER1_Pos   (2U)
     
    #define GPIO_MODER_MODER1_Msk   (0x3UL << GPIO_MODER_MODER1_Pos)
     
    #define GPIO_MODER_MODER1   GPIO_MODER_MODER1_Msk
     
    #define GPIO_MODER_MODER1_0   (0x1UL << GPIO_MODER_MODER1_Pos)
     
    #define GPIO_MODER_MODER1_1   (0x2UL << GPIO_MODER_MODER1_Pos)
     
    #define GPIO_MODER_MODER2_Pos   (4U)
     
    #define GPIO_MODER_MODER2_Msk   (0x3UL << GPIO_MODER_MODER2_Pos)
     
    #define GPIO_MODER_MODER2   GPIO_MODER_MODER2_Msk
     
    #define GPIO_MODER_MODER2_0   (0x1UL << GPIO_MODER_MODER2_Pos)
     
    #define GPIO_MODER_MODER2_1   (0x2UL << GPIO_MODER_MODER2_Pos)
     
    #define GPIO_MODER_MODER3_Pos   (6U)
     
    #define GPIO_MODER_MODER3_Msk   (0x3UL << GPIO_MODER_MODER3_Pos)
     
    #define GPIO_MODER_MODER3   GPIO_MODER_MODER3_Msk
     
    #define GPIO_MODER_MODER3_0   (0x1UL << GPIO_MODER_MODER3_Pos)
     
    #define GPIO_MODER_MODER3_1   (0x2UL << GPIO_MODER_MODER3_Pos)
     
    #define GPIO_MODER_MODER4_Pos   (8U)
     
    #define GPIO_MODER_MODER4_Msk   (0x3UL << GPIO_MODER_MODER4_Pos)
     
    #define GPIO_MODER_MODER4   GPIO_MODER_MODER4_Msk
     
    #define GPIO_MODER_MODER4_0   (0x1UL << GPIO_MODER_MODER4_Pos)
     
    #define GPIO_MODER_MODER4_1   (0x2UL << GPIO_MODER_MODER4_Pos)
     
    #define GPIO_MODER_MODER5_Pos   (10U)
     
    #define GPIO_MODER_MODER5_Msk   (0x3UL << GPIO_MODER_MODER5_Pos)
     
    #define GPIO_MODER_MODER5   GPIO_MODER_MODER5_Msk
     
    #define GPIO_MODER_MODER5_0   (0x1UL << GPIO_MODER_MODER5_Pos)
     
    #define GPIO_MODER_MODER5_1   (0x2UL << GPIO_MODER_MODER5_Pos)
     
    #define GPIO_MODER_MODER6_Pos   (12U)
     
    #define GPIO_MODER_MODER6_Msk   (0x3UL << GPIO_MODER_MODER6_Pos)
     
    #define GPIO_MODER_MODER6   GPIO_MODER_MODER6_Msk
     
    #define GPIO_MODER_MODER6_0   (0x1UL << GPIO_MODER_MODER6_Pos)
     
    #define GPIO_MODER_MODER6_1   (0x2UL << GPIO_MODER_MODER6_Pos)
     
    #define GPIO_MODER_MODER7_Pos   (14U)
     
    #define GPIO_MODER_MODER7_Msk   (0x3UL << GPIO_MODER_MODER7_Pos)
     
    #define GPIO_MODER_MODER7   GPIO_MODER_MODER7_Msk
     
    #define GPIO_MODER_MODER7_0   (0x1UL << GPIO_MODER_MODER7_Pos)
     
    #define GPIO_MODER_MODER7_1   (0x2UL << GPIO_MODER_MODER7_Pos)
     
    #define GPIO_MODER_MODER8_Pos   (16U)
     
    #define GPIO_MODER_MODER8_Msk   (0x3UL << GPIO_MODER_MODER8_Pos)
     
    #define GPIO_MODER_MODER8   GPIO_MODER_MODER8_Msk
     
    #define GPIO_MODER_MODER8_0   (0x1UL << GPIO_MODER_MODER8_Pos)
     
    #define GPIO_MODER_MODER8_1   (0x2UL << GPIO_MODER_MODER8_Pos)
     
    #define GPIO_MODER_MODER9_Pos   (18U)
     
    #define GPIO_MODER_MODER9_Msk   (0x3UL << GPIO_MODER_MODER9_Pos)
     
    #define GPIO_MODER_MODER9   GPIO_MODER_MODER9_Msk
     
    #define GPIO_MODER_MODER9_0   (0x1UL << GPIO_MODER_MODER9_Pos)
     
    #define GPIO_MODER_MODER9_1   (0x2UL << GPIO_MODER_MODER9_Pos)
     
    #define GPIO_MODER_MODER10_Pos   (20U)
     
    #define GPIO_MODER_MODER10_Msk   (0x3UL << GPIO_MODER_MODER10_Pos)
     
    #define GPIO_MODER_MODER10   GPIO_MODER_MODER10_Msk
     
    #define GPIO_MODER_MODER10_0   (0x1UL << GPIO_MODER_MODER10_Pos)
     
    #define GPIO_MODER_MODER10_1   (0x2UL << GPIO_MODER_MODER10_Pos)
     
    #define GPIO_MODER_MODER11_Pos   (22U)
     
    #define GPIO_MODER_MODER11_Msk   (0x3UL << GPIO_MODER_MODER11_Pos)
     
    #define GPIO_MODER_MODER11   GPIO_MODER_MODER11_Msk
     
    #define GPIO_MODER_MODER11_0   (0x1UL << GPIO_MODER_MODER11_Pos)
     
    #define GPIO_MODER_MODER11_1   (0x2UL << GPIO_MODER_MODER11_Pos)
     
    #define GPIO_MODER_MODER12_Pos   (24U)
     
    #define GPIO_MODER_MODER12_Msk   (0x3UL << GPIO_MODER_MODER12_Pos)
     
    #define GPIO_MODER_MODER12   GPIO_MODER_MODER12_Msk
     
    #define GPIO_MODER_MODER12_0   (0x1UL << GPIO_MODER_MODER12_Pos)
     
    #define GPIO_MODER_MODER12_1   (0x2UL << GPIO_MODER_MODER12_Pos)
     
    #define GPIO_MODER_MODER13_Pos   (26U)
     
    #define GPIO_MODER_MODER13_Msk   (0x3UL << GPIO_MODER_MODER13_Pos)
     
    #define GPIO_MODER_MODER13   GPIO_MODER_MODER13_Msk
     
    #define GPIO_MODER_MODER13_0   (0x1UL << GPIO_MODER_MODER13_Pos)
     
    #define GPIO_MODER_MODER13_1   (0x2UL << GPIO_MODER_MODER13_Pos)
     
    #define GPIO_MODER_MODER14_Pos   (28U)
     
    #define GPIO_MODER_MODER14_Msk   (0x3UL << GPIO_MODER_MODER14_Pos)
     
    #define GPIO_MODER_MODER14   GPIO_MODER_MODER14_Msk
     
    #define GPIO_MODER_MODER14_0   (0x1UL << GPIO_MODER_MODER14_Pos)
     
    #define GPIO_MODER_MODER14_1   (0x2UL << GPIO_MODER_MODER14_Pos)
     
    #define GPIO_MODER_MODER15_Pos   (30U)
     
    #define GPIO_MODER_MODER15_Msk   (0x3UL << GPIO_MODER_MODER15_Pos)
     
    #define GPIO_MODER_MODER15   GPIO_MODER_MODER15_Msk
     
    #define GPIO_MODER_MODER15_0   (0x1UL << GPIO_MODER_MODER15_Pos)
     
    #define GPIO_MODER_MODER15_1   (0x2UL << GPIO_MODER_MODER15_Pos)
     
    #define GPIO_MODER_MODE0_Pos   GPIO_MODER_MODER0_Pos
     
    #define GPIO_MODER_MODE0_Msk   GPIO_MODER_MODER0_Msk
     
    #define GPIO_MODER_MODE0   GPIO_MODER_MODER0
     
    #define GPIO_MODER_MODE0_0   GPIO_MODER_MODER0_0
     
    #define GPIO_MODER_MODE0_1   GPIO_MODER_MODER0_1
     
    #define GPIO_MODER_MODE1_Pos   GPIO_MODER_MODER1_Pos
     
    #define GPIO_MODER_MODE1_Msk   GPIO_MODER_MODER1_Msk
     
    #define GPIO_MODER_MODE1   GPIO_MODER_MODER1
     
    #define GPIO_MODER_MODE1_0   GPIO_MODER_MODER1_0
     
    #define GPIO_MODER_MODE1_1   GPIO_MODER_MODER1_1
     
    #define GPIO_MODER_MODE2_Pos   GPIO_MODER_MODER2_Pos
     
    #define GPIO_MODER_MODE2_Msk   GPIO_MODER_MODER2_Msk
     
    #define GPIO_MODER_MODE2   GPIO_MODER_MODER2
     
    #define GPIO_MODER_MODE2_0   GPIO_MODER_MODER2_0
     
    #define GPIO_MODER_MODE2_1   GPIO_MODER_MODER2_1
     
    #define GPIO_MODER_MODE3_Pos   GPIO_MODER_MODER3_Pos
     
    #define GPIO_MODER_MODE3_Msk   GPIO_MODER_MODER3_Msk
     
    #define GPIO_MODER_MODE3   GPIO_MODER_MODER3
     
    #define GPIO_MODER_MODE3_0   GPIO_MODER_MODER3_0
     
    #define GPIO_MODER_MODE3_1   GPIO_MODER_MODER3_1
     
    #define GPIO_MODER_MODE4_Pos   GPIO_MODER_MODER4_Pos
     
    #define GPIO_MODER_MODE4_Msk   GPIO_MODER_MODER4_Msk
     
    #define GPIO_MODER_MODE4   GPIO_MODER_MODER4
     
    #define GPIO_MODER_MODE4_0   GPIO_MODER_MODER4_0
     
    #define GPIO_MODER_MODE4_1   GPIO_MODER_MODER4_1
     
    #define GPIO_MODER_MODE5_Pos   GPIO_MODER_MODER5_Pos
     
    #define GPIO_MODER_MODE5_Msk   GPIO_MODER_MODER5_Msk
     
    #define GPIO_MODER_MODE5   GPIO_MODER_MODER5
     
    #define GPIO_MODER_MODE5_0   GPIO_MODER_MODER5_0
     
    #define GPIO_MODER_MODE5_1   GPIO_MODER_MODER5_1
     
    #define GPIO_MODER_MODE6_Pos   GPIO_MODER_MODER6_Pos
     
    #define GPIO_MODER_MODE6_Msk   GPIO_MODER_MODER6_Msk
     
    #define GPIO_MODER_MODE6   GPIO_MODER_MODER6
     
    #define GPIO_MODER_MODE6_0   GPIO_MODER_MODER6_0
     
    #define GPIO_MODER_MODE6_1   GPIO_MODER_MODER6_1
     
    #define GPIO_MODER_MODE7_Pos   GPIO_MODER_MODER7_Pos
     
    #define GPIO_MODER_MODE7_Msk   GPIO_MODER_MODER7_Msk
     
    #define GPIO_MODER_MODE7   GPIO_MODER_MODER7
     
    #define GPIO_MODER_MODE7_0   GPIO_MODER_MODER7_0
     
    #define GPIO_MODER_MODE7_1   GPIO_MODER_MODER7_1
     
    #define GPIO_MODER_MODE8_Pos   GPIO_MODER_MODER8_Pos
     
    #define GPIO_MODER_MODE8_Msk   GPIO_MODER_MODER8_Msk
     
    #define GPIO_MODER_MODE8   GPIO_MODER_MODER8
     
    #define GPIO_MODER_MODE8_0   GPIO_MODER_MODER8_0
     
    #define GPIO_MODER_MODE8_1   GPIO_MODER_MODER8_1
     
    #define GPIO_MODER_MODE9_Pos   GPIO_MODER_MODER9_Pos
     
    #define GPIO_MODER_MODE9_Msk   GPIO_MODER_MODER9_Msk
     
    #define GPIO_MODER_MODE9   GPIO_MODER_MODER9
     
    #define GPIO_MODER_MODE9_0   GPIO_MODER_MODER9_0
     
    #define GPIO_MODER_MODE9_1   GPIO_MODER_MODER9_1
     
    #define GPIO_MODER_MODE10_Pos   GPIO_MODER_MODER10_Pos
     
    #define GPIO_MODER_MODE10_Msk   GPIO_MODER_MODER10_Msk
     
    #define GPIO_MODER_MODE10   GPIO_MODER_MODER10
     
    #define GPIO_MODER_MODE10_0   GPIO_MODER_MODER10_0
     
    #define GPIO_MODER_MODE10_1   GPIO_MODER_MODER10_1
     
    #define GPIO_MODER_MODE11_Pos   GPIO_MODER_MODER11_Pos
     
    #define GPIO_MODER_MODE11_Msk   GPIO_MODER_MODER11_Msk
     
    #define GPIO_MODER_MODE11   GPIO_MODER_MODER11
     
    #define GPIO_MODER_MODE11_0   GPIO_MODER_MODER11_0
     
    #define GPIO_MODER_MODE11_1   GPIO_MODER_MODER11_1
     
    #define GPIO_MODER_MODE12_Pos   GPIO_MODER_MODER12_Pos
     
    #define GPIO_MODER_MODE12_Msk   GPIO_MODER_MODER12_Msk
     
    #define GPIO_MODER_MODE12   GPIO_MODER_MODER12
     
    #define GPIO_MODER_MODE12_0   GPIO_MODER_MODER12_0
     
    #define GPIO_MODER_MODE12_1   GPIO_MODER_MODER12_1
     
    #define GPIO_MODER_MODE13_Pos   GPIO_MODER_MODER13_Pos
     
    #define GPIO_MODER_MODE13_Msk   GPIO_MODER_MODER13_Msk
     
    #define GPIO_MODER_MODE13   GPIO_MODER_MODER13
     
    #define GPIO_MODER_MODE13_0   GPIO_MODER_MODER13_0
     
    #define GPIO_MODER_MODE13_1   GPIO_MODER_MODER13_1
     
    #define GPIO_MODER_MODE14_Pos   GPIO_MODER_MODER14_Pos
     
    #define GPIO_MODER_MODE14_Msk   GPIO_MODER_MODER14_Msk
     
    #define GPIO_MODER_MODE14   GPIO_MODER_MODER14
     
    #define GPIO_MODER_MODE14_0   GPIO_MODER_MODER14_0
     
    #define GPIO_MODER_MODE14_1   GPIO_MODER_MODER14_1
     
    #define GPIO_MODER_MODE15_Pos   GPIO_MODER_MODER15_Pos
     
    #define GPIO_MODER_MODE15_Msk   GPIO_MODER_MODER15_Msk
     
    #define GPIO_MODER_MODE15   GPIO_MODER_MODER15
     
    #define GPIO_MODER_MODE15_0   GPIO_MODER_MODER15_0
     
    #define GPIO_MODER_MODE15_1   GPIO_MODER_MODER15_1
     
    #define GPIO_OTYPER_OT0_Pos   (0U)
     
    #define GPIO_OTYPER_OT0_Msk   (0x1UL << GPIO_OTYPER_OT0_Pos)
     
    #define GPIO_OTYPER_OT0   GPIO_OTYPER_OT0_Msk
     
    #define GPIO_OTYPER_OT1_Pos   (1U)
     
    #define GPIO_OTYPER_OT1_Msk   (0x1UL << GPIO_OTYPER_OT1_Pos)
     
    #define GPIO_OTYPER_OT1   GPIO_OTYPER_OT1_Msk
     
    #define GPIO_OTYPER_OT2_Pos   (2U)
     
    #define GPIO_OTYPER_OT2_Msk   (0x1UL << GPIO_OTYPER_OT2_Pos)
     
    #define GPIO_OTYPER_OT2   GPIO_OTYPER_OT2_Msk
     
    #define GPIO_OTYPER_OT3_Pos   (3U)
     
    #define GPIO_OTYPER_OT3_Msk   (0x1UL << GPIO_OTYPER_OT3_Pos)
     
    #define GPIO_OTYPER_OT3   GPIO_OTYPER_OT3_Msk
     
    #define GPIO_OTYPER_OT4_Pos   (4U)
     
    #define GPIO_OTYPER_OT4_Msk   (0x1UL << GPIO_OTYPER_OT4_Pos)
     
    #define GPIO_OTYPER_OT4   GPIO_OTYPER_OT4_Msk
     
    #define GPIO_OTYPER_OT5_Pos   (5U)
     
    #define GPIO_OTYPER_OT5_Msk   (0x1UL << GPIO_OTYPER_OT5_Pos)
     
    #define GPIO_OTYPER_OT5   GPIO_OTYPER_OT5_Msk
     
    #define GPIO_OTYPER_OT6_Pos   (6U)
     
    #define GPIO_OTYPER_OT6_Msk   (0x1UL << GPIO_OTYPER_OT6_Pos)
     
    #define GPIO_OTYPER_OT6   GPIO_OTYPER_OT6_Msk
     
    #define GPIO_OTYPER_OT7_Pos   (7U)
     
    #define GPIO_OTYPER_OT7_Msk   (0x1UL << GPIO_OTYPER_OT7_Pos)
     
    #define GPIO_OTYPER_OT7   GPIO_OTYPER_OT7_Msk
     
    #define GPIO_OTYPER_OT8_Pos   (8U)
     
    #define GPIO_OTYPER_OT8_Msk   (0x1UL << GPIO_OTYPER_OT8_Pos)
     
    #define GPIO_OTYPER_OT8   GPIO_OTYPER_OT8_Msk
     
    #define GPIO_OTYPER_OT9_Pos   (9U)
     
    #define GPIO_OTYPER_OT9_Msk   (0x1UL << GPIO_OTYPER_OT9_Pos)
     
    #define GPIO_OTYPER_OT9   GPIO_OTYPER_OT9_Msk
     
    #define GPIO_OTYPER_OT10_Pos   (10U)
     
    #define GPIO_OTYPER_OT10_Msk   (0x1UL << GPIO_OTYPER_OT10_Pos)
     
    #define GPIO_OTYPER_OT10   GPIO_OTYPER_OT10_Msk
     
    #define GPIO_OTYPER_OT11_Pos   (11U)
     
    #define GPIO_OTYPER_OT11_Msk   (0x1UL << GPIO_OTYPER_OT11_Pos)
     
    #define GPIO_OTYPER_OT11   GPIO_OTYPER_OT11_Msk
     
    #define GPIO_OTYPER_OT12_Pos   (12U)
     
    #define GPIO_OTYPER_OT12_Msk   (0x1UL << GPIO_OTYPER_OT12_Pos)
     
    #define GPIO_OTYPER_OT12   GPIO_OTYPER_OT12_Msk
     
    #define GPIO_OTYPER_OT13_Pos   (13U)
     
    #define GPIO_OTYPER_OT13_Msk   (0x1UL << GPIO_OTYPER_OT13_Pos)
     
    #define GPIO_OTYPER_OT13   GPIO_OTYPER_OT13_Msk
     
    #define GPIO_OTYPER_OT14_Pos   (14U)
     
    #define GPIO_OTYPER_OT14_Msk   (0x1UL << GPIO_OTYPER_OT14_Pos)
     
    #define GPIO_OTYPER_OT14   GPIO_OTYPER_OT14_Msk
     
    #define GPIO_OTYPER_OT15_Pos   (15U)
     
    #define GPIO_OTYPER_OT15_Msk   (0x1UL << GPIO_OTYPER_OT15_Pos)
     
    #define GPIO_OTYPER_OT15   GPIO_OTYPER_OT15_Msk
     
    #define GPIO_OTYPER_OT_0   GPIO_OTYPER_OT0
     
    #define GPIO_OTYPER_OT_1   GPIO_OTYPER_OT1
     
    #define GPIO_OTYPER_OT_2   GPIO_OTYPER_OT2
     
    #define GPIO_OTYPER_OT_3   GPIO_OTYPER_OT3
     
    #define GPIO_OTYPER_OT_4   GPIO_OTYPER_OT4
     
    #define GPIO_OTYPER_OT_5   GPIO_OTYPER_OT5
     
    #define GPIO_OTYPER_OT_6   GPIO_OTYPER_OT6
     
    #define GPIO_OTYPER_OT_7   GPIO_OTYPER_OT7
     
    #define GPIO_OTYPER_OT_8   GPIO_OTYPER_OT8
     
    #define GPIO_OTYPER_OT_9   GPIO_OTYPER_OT9
     
    #define GPIO_OTYPER_OT_10   GPIO_OTYPER_OT10
     
    #define GPIO_OTYPER_OT_11   GPIO_OTYPER_OT11
     
    #define GPIO_OTYPER_OT_12   GPIO_OTYPER_OT12
     
    #define GPIO_OTYPER_OT_13   GPIO_OTYPER_OT13
     
    #define GPIO_OTYPER_OT_14   GPIO_OTYPER_OT14
     
    #define GPIO_OTYPER_OT_15   GPIO_OTYPER_OT15
     
    #define GPIO_OSPEEDR_OSPEED0_Pos   (0U)
     
    #define GPIO_OSPEEDR_OSPEED0_Msk   (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos)
     
    #define GPIO_OSPEEDR_OSPEED0   GPIO_OSPEEDR_OSPEED0_Msk
     
    #define GPIO_OSPEEDR_OSPEED0_0   (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos)
     
    #define GPIO_OSPEEDR_OSPEED0_1   (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos)
     
    #define GPIO_OSPEEDR_OSPEED1_Pos   (2U)
     
    #define GPIO_OSPEEDR_OSPEED1_Msk   (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos)
     
    #define GPIO_OSPEEDR_OSPEED1   GPIO_OSPEEDR_OSPEED1_Msk
     
    #define GPIO_OSPEEDR_OSPEED1_0   (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos)
     
    #define GPIO_OSPEEDR_OSPEED1_1   (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos)
     
    #define GPIO_OSPEEDR_OSPEED2_Pos   (4U)
     
    #define GPIO_OSPEEDR_OSPEED2_Msk   (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos)
     
    #define GPIO_OSPEEDR_OSPEED2   GPIO_OSPEEDR_OSPEED2_Msk
     
    #define GPIO_OSPEEDR_OSPEED2_0   (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos)
     
    #define GPIO_OSPEEDR_OSPEED2_1   (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos)
     
    #define GPIO_OSPEEDR_OSPEED3_Pos   (6U)
     
    #define GPIO_OSPEEDR_OSPEED3_Msk   (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos)
     
    #define GPIO_OSPEEDR_OSPEED3   GPIO_OSPEEDR_OSPEED3_Msk
     
    #define GPIO_OSPEEDR_OSPEED3_0   (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos)
     
    #define GPIO_OSPEEDR_OSPEED3_1   (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos)
     
    #define GPIO_OSPEEDR_OSPEED4_Pos   (8U)
     
    #define GPIO_OSPEEDR_OSPEED4_Msk   (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos)
     
    #define GPIO_OSPEEDR_OSPEED4   GPIO_OSPEEDR_OSPEED4_Msk
     
    #define GPIO_OSPEEDR_OSPEED4_0   (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos)
     
    #define GPIO_OSPEEDR_OSPEED4_1   (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos)
     
    #define GPIO_OSPEEDR_OSPEED5_Pos   (10U)
     
    #define GPIO_OSPEEDR_OSPEED5_Msk   (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos)
     
    #define GPIO_OSPEEDR_OSPEED5   GPIO_OSPEEDR_OSPEED5_Msk
     
    #define GPIO_OSPEEDR_OSPEED5_0   (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos)
     
    #define GPIO_OSPEEDR_OSPEED5_1   (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos)
     
    #define GPIO_OSPEEDR_OSPEED6_Pos   (12U)
     
    #define GPIO_OSPEEDR_OSPEED6_Msk   (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos)
     
    #define GPIO_OSPEEDR_OSPEED6   GPIO_OSPEEDR_OSPEED6_Msk
     
    #define GPIO_OSPEEDR_OSPEED6_0   (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos)
     
    #define GPIO_OSPEEDR_OSPEED6_1   (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos)
     
    #define GPIO_OSPEEDR_OSPEED7_Pos   (14U)
     
    #define GPIO_OSPEEDR_OSPEED7_Msk   (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos)
     
    #define GPIO_OSPEEDR_OSPEED7   GPIO_OSPEEDR_OSPEED7_Msk
     
    #define GPIO_OSPEEDR_OSPEED7_0   (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos)
     
    #define GPIO_OSPEEDR_OSPEED7_1   (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos)
     
    #define GPIO_OSPEEDR_OSPEED8_Pos   (16U)
     
    #define GPIO_OSPEEDR_OSPEED8_Msk   (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos)
     
    #define GPIO_OSPEEDR_OSPEED8   GPIO_OSPEEDR_OSPEED8_Msk
     
    #define GPIO_OSPEEDR_OSPEED8_0   (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos)
     
    #define GPIO_OSPEEDR_OSPEED8_1   (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos)
     
    #define GPIO_OSPEEDR_OSPEED9_Pos   (18U)
     
    #define GPIO_OSPEEDR_OSPEED9_Msk   (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos)
     
    #define GPIO_OSPEEDR_OSPEED9   GPIO_OSPEEDR_OSPEED9_Msk
     
    #define GPIO_OSPEEDR_OSPEED9_0   (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos)
     
    #define GPIO_OSPEEDR_OSPEED9_1   (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos)
     
    #define GPIO_OSPEEDR_OSPEED10_Pos   (20U)
     
    #define GPIO_OSPEEDR_OSPEED10_Msk   (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos)
     
    #define GPIO_OSPEEDR_OSPEED10   GPIO_OSPEEDR_OSPEED10_Msk
     
    #define GPIO_OSPEEDR_OSPEED10_0   (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos)
     
    #define GPIO_OSPEEDR_OSPEED10_1   (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos)
     
    #define GPIO_OSPEEDR_OSPEED11_Pos   (22U)
     
    #define GPIO_OSPEEDR_OSPEED11_Msk   (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos)
     
    #define GPIO_OSPEEDR_OSPEED11   GPIO_OSPEEDR_OSPEED11_Msk
     
    #define GPIO_OSPEEDR_OSPEED11_0   (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos)
     
    #define GPIO_OSPEEDR_OSPEED11_1   (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos)
     
    #define GPIO_OSPEEDR_OSPEED12_Pos   (24U)
     
    #define GPIO_OSPEEDR_OSPEED12_Msk   (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos)
     
    #define GPIO_OSPEEDR_OSPEED12   GPIO_OSPEEDR_OSPEED12_Msk
     
    #define GPIO_OSPEEDR_OSPEED12_0   (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos)
     
    #define GPIO_OSPEEDR_OSPEED12_1   (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos)
     
    #define GPIO_OSPEEDR_OSPEED13_Pos   (26U)
     
    #define GPIO_OSPEEDR_OSPEED13_Msk   (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos)
     
    #define GPIO_OSPEEDR_OSPEED13   GPIO_OSPEEDR_OSPEED13_Msk
     
    #define GPIO_OSPEEDR_OSPEED13_0   (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos)
     
    #define GPIO_OSPEEDR_OSPEED13_1   (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos)
     
    #define GPIO_OSPEEDR_OSPEED14_Pos   (28U)
     
    #define GPIO_OSPEEDR_OSPEED14_Msk   (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos)
     
    #define GPIO_OSPEEDR_OSPEED14   GPIO_OSPEEDR_OSPEED14_Msk
     
    #define GPIO_OSPEEDR_OSPEED14_0   (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos)
     
    #define GPIO_OSPEEDR_OSPEED14_1   (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos)
     
    #define GPIO_OSPEEDR_OSPEED15_Pos   (30U)
     
    #define GPIO_OSPEEDR_OSPEED15_Msk   (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos)
     
    #define GPIO_OSPEEDR_OSPEED15   GPIO_OSPEEDR_OSPEED15_Msk
     
    #define GPIO_OSPEEDR_OSPEED15_0   (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos)
     
    #define GPIO_OSPEEDR_OSPEED15_1   (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos)
     
    #define GPIO_OSPEEDER_OSPEEDR0   GPIO_OSPEEDR_OSPEED0
     
    #define GPIO_OSPEEDER_OSPEEDR0_0   GPIO_OSPEEDR_OSPEED0_0
     
    #define GPIO_OSPEEDER_OSPEEDR0_1   GPIO_OSPEEDR_OSPEED0_1
     
    #define GPIO_OSPEEDER_OSPEEDR1   GPIO_OSPEEDR_OSPEED1
     
    #define GPIO_OSPEEDER_OSPEEDR1_0   GPIO_OSPEEDR_OSPEED1_0
     
    #define GPIO_OSPEEDER_OSPEEDR1_1   GPIO_OSPEEDR_OSPEED1_1
     
    #define GPIO_OSPEEDER_OSPEEDR2   GPIO_OSPEEDR_OSPEED2
     
    #define GPIO_OSPEEDER_OSPEEDR2_0   GPIO_OSPEEDR_OSPEED2_0
     
    #define GPIO_OSPEEDER_OSPEEDR2_1   GPIO_OSPEEDR_OSPEED2_1
     
    #define GPIO_OSPEEDER_OSPEEDR3   GPIO_OSPEEDR_OSPEED3
     
    #define GPIO_OSPEEDER_OSPEEDR3_0   GPIO_OSPEEDR_OSPEED3_0
     
    #define GPIO_OSPEEDER_OSPEEDR3_1   GPIO_OSPEEDR_OSPEED3_1
     
    #define GPIO_OSPEEDER_OSPEEDR4   GPIO_OSPEEDR_OSPEED4
     
    #define GPIO_OSPEEDER_OSPEEDR4_0   GPIO_OSPEEDR_OSPEED4_0
     
    #define GPIO_OSPEEDER_OSPEEDR4_1   GPIO_OSPEEDR_OSPEED4_1
     
    #define GPIO_OSPEEDER_OSPEEDR5   GPIO_OSPEEDR_OSPEED5
     
    #define GPIO_OSPEEDER_OSPEEDR5_0   GPIO_OSPEEDR_OSPEED5_0
     
    #define GPIO_OSPEEDER_OSPEEDR5_1   GPIO_OSPEEDR_OSPEED5_1
     
    #define GPIO_OSPEEDER_OSPEEDR6   GPIO_OSPEEDR_OSPEED6
     
    #define GPIO_OSPEEDER_OSPEEDR6_0   GPIO_OSPEEDR_OSPEED6_0
     
    #define GPIO_OSPEEDER_OSPEEDR6_1   GPIO_OSPEEDR_OSPEED6_1
     
    #define GPIO_OSPEEDER_OSPEEDR7   GPIO_OSPEEDR_OSPEED7
     
    #define GPIO_OSPEEDER_OSPEEDR7_0   GPIO_OSPEEDR_OSPEED7_0
     
    #define GPIO_OSPEEDER_OSPEEDR7_1   GPIO_OSPEEDR_OSPEED7_1
     
    #define GPIO_OSPEEDER_OSPEEDR8   GPIO_OSPEEDR_OSPEED8
     
    #define GPIO_OSPEEDER_OSPEEDR8_0   GPIO_OSPEEDR_OSPEED8_0
     
    #define GPIO_OSPEEDER_OSPEEDR8_1   GPIO_OSPEEDR_OSPEED8_1
     
    #define GPIO_OSPEEDER_OSPEEDR9   GPIO_OSPEEDR_OSPEED9
     
    #define GPIO_OSPEEDER_OSPEEDR9_0   GPIO_OSPEEDR_OSPEED9_0
     
    #define GPIO_OSPEEDER_OSPEEDR9_1   GPIO_OSPEEDR_OSPEED9_1
     
    #define GPIO_OSPEEDER_OSPEEDR10   GPIO_OSPEEDR_OSPEED10
     
    #define GPIO_OSPEEDER_OSPEEDR10_0   GPIO_OSPEEDR_OSPEED10_0
     
    #define GPIO_OSPEEDER_OSPEEDR10_1   GPIO_OSPEEDR_OSPEED10_1
     
    #define GPIO_OSPEEDER_OSPEEDR11   GPIO_OSPEEDR_OSPEED11
     
    #define GPIO_OSPEEDER_OSPEEDR11_0   GPIO_OSPEEDR_OSPEED11_0
     
    #define GPIO_OSPEEDER_OSPEEDR11_1   GPIO_OSPEEDR_OSPEED11_1
     
    #define GPIO_OSPEEDER_OSPEEDR12   GPIO_OSPEEDR_OSPEED12
     
    #define GPIO_OSPEEDER_OSPEEDR12_0   GPIO_OSPEEDR_OSPEED12_0
     
    #define GPIO_OSPEEDER_OSPEEDR12_1   GPIO_OSPEEDR_OSPEED12_1
     
    #define GPIO_OSPEEDER_OSPEEDR13   GPIO_OSPEEDR_OSPEED13
     
    #define GPIO_OSPEEDER_OSPEEDR13_0   GPIO_OSPEEDR_OSPEED13_0
     
    #define GPIO_OSPEEDER_OSPEEDR13_1   GPIO_OSPEEDR_OSPEED13_1
     
    #define GPIO_OSPEEDER_OSPEEDR14   GPIO_OSPEEDR_OSPEED14
     
    #define GPIO_OSPEEDER_OSPEEDR14_0   GPIO_OSPEEDR_OSPEED14_0
     
    #define GPIO_OSPEEDER_OSPEEDR14_1   GPIO_OSPEEDR_OSPEED14_1
     
    #define GPIO_OSPEEDER_OSPEEDR15   GPIO_OSPEEDR_OSPEED15
     
    #define GPIO_OSPEEDER_OSPEEDR15_0   GPIO_OSPEEDR_OSPEED15_0
     
    #define GPIO_OSPEEDER_OSPEEDR15_1   GPIO_OSPEEDR_OSPEED15_1
     
    #define GPIO_PUPDR_PUPD0_Pos   (0U)
     
    #define GPIO_PUPDR_PUPD0_Msk   (0x3UL << GPIO_PUPDR_PUPD0_Pos)
     
    #define GPIO_PUPDR_PUPD0   GPIO_PUPDR_PUPD0_Msk
     
    #define GPIO_PUPDR_PUPD0_0   (0x1UL << GPIO_PUPDR_PUPD0_Pos)
     
    #define GPIO_PUPDR_PUPD0_1   (0x2UL << GPIO_PUPDR_PUPD0_Pos)
     
    #define GPIO_PUPDR_PUPD1_Pos   (2U)
     
    #define GPIO_PUPDR_PUPD1_Msk   (0x3UL << GPIO_PUPDR_PUPD1_Pos)
     
    #define GPIO_PUPDR_PUPD1   GPIO_PUPDR_PUPD1_Msk
     
    #define GPIO_PUPDR_PUPD1_0   (0x1UL << GPIO_PUPDR_PUPD1_Pos)
     
    #define GPIO_PUPDR_PUPD1_1   (0x2UL << GPIO_PUPDR_PUPD1_Pos)
     
    #define GPIO_PUPDR_PUPD2_Pos   (4U)
     
    #define GPIO_PUPDR_PUPD2_Msk   (0x3UL << GPIO_PUPDR_PUPD2_Pos)
     
    #define GPIO_PUPDR_PUPD2   GPIO_PUPDR_PUPD2_Msk
     
    #define GPIO_PUPDR_PUPD2_0   (0x1UL << GPIO_PUPDR_PUPD2_Pos)
     
    #define GPIO_PUPDR_PUPD2_1   (0x2UL << GPIO_PUPDR_PUPD2_Pos)
     
    #define GPIO_PUPDR_PUPD3_Pos   (6U)
     
    #define GPIO_PUPDR_PUPD3_Msk   (0x3UL << GPIO_PUPDR_PUPD3_Pos)
     
    #define GPIO_PUPDR_PUPD3   GPIO_PUPDR_PUPD3_Msk
     
    #define GPIO_PUPDR_PUPD3_0   (0x1UL << GPIO_PUPDR_PUPD3_Pos)
     
    #define GPIO_PUPDR_PUPD3_1   (0x2UL << GPIO_PUPDR_PUPD3_Pos)
     
    #define GPIO_PUPDR_PUPD4_Pos   (8U)
     
    #define GPIO_PUPDR_PUPD4_Msk   (0x3UL << GPIO_PUPDR_PUPD4_Pos)
     
    #define GPIO_PUPDR_PUPD4   GPIO_PUPDR_PUPD4_Msk
     
    #define GPIO_PUPDR_PUPD4_0   (0x1UL << GPIO_PUPDR_PUPD4_Pos)
     
    #define GPIO_PUPDR_PUPD4_1   (0x2UL << GPIO_PUPDR_PUPD4_Pos)
     
    #define GPIO_PUPDR_PUPD5_Pos   (10U)
     
    #define GPIO_PUPDR_PUPD5_Msk   (0x3UL << GPIO_PUPDR_PUPD5_Pos)
     
    #define GPIO_PUPDR_PUPD5   GPIO_PUPDR_PUPD5_Msk
     
    #define GPIO_PUPDR_PUPD5_0   (0x1UL << GPIO_PUPDR_PUPD5_Pos)
     
    #define GPIO_PUPDR_PUPD5_1   (0x2UL << GPIO_PUPDR_PUPD5_Pos)
     
    #define GPIO_PUPDR_PUPD6_Pos   (12U)
     
    #define GPIO_PUPDR_PUPD6_Msk   (0x3UL << GPIO_PUPDR_PUPD6_Pos)
     
    #define GPIO_PUPDR_PUPD6   GPIO_PUPDR_PUPD6_Msk
     
    #define GPIO_PUPDR_PUPD6_0   (0x1UL << GPIO_PUPDR_PUPD6_Pos)
     
    #define GPIO_PUPDR_PUPD6_1   (0x2UL << GPIO_PUPDR_PUPD6_Pos)
     
    #define GPIO_PUPDR_PUPD7_Pos   (14U)
     
    #define GPIO_PUPDR_PUPD7_Msk   (0x3UL << GPIO_PUPDR_PUPD7_Pos)
     
    #define GPIO_PUPDR_PUPD7   GPIO_PUPDR_PUPD7_Msk
     
    #define GPIO_PUPDR_PUPD7_0   (0x1UL << GPIO_PUPDR_PUPD7_Pos)
     
    #define GPIO_PUPDR_PUPD7_1   (0x2UL << GPIO_PUPDR_PUPD7_Pos)
     
    #define GPIO_PUPDR_PUPD8_Pos   (16U)
     
    #define GPIO_PUPDR_PUPD8_Msk   (0x3UL << GPIO_PUPDR_PUPD8_Pos)
     
    #define GPIO_PUPDR_PUPD8   GPIO_PUPDR_PUPD8_Msk
     
    #define GPIO_PUPDR_PUPD8_0   (0x1UL << GPIO_PUPDR_PUPD8_Pos)
     
    #define GPIO_PUPDR_PUPD8_1   (0x2UL << GPIO_PUPDR_PUPD8_Pos)
     
    #define GPIO_PUPDR_PUPD9_Pos   (18U)
     
    #define GPIO_PUPDR_PUPD9_Msk   (0x3UL << GPIO_PUPDR_PUPD9_Pos)
     
    #define GPIO_PUPDR_PUPD9   GPIO_PUPDR_PUPD9_Msk
     
    #define GPIO_PUPDR_PUPD9_0   (0x1UL << GPIO_PUPDR_PUPD9_Pos)
     
    #define GPIO_PUPDR_PUPD9_1   (0x2UL << GPIO_PUPDR_PUPD9_Pos)
     
    #define GPIO_PUPDR_PUPD10_Pos   (20U)
     
    #define GPIO_PUPDR_PUPD10_Msk   (0x3UL << GPIO_PUPDR_PUPD10_Pos)
     
    #define GPIO_PUPDR_PUPD10   GPIO_PUPDR_PUPD10_Msk
     
    #define GPIO_PUPDR_PUPD10_0   (0x1UL << GPIO_PUPDR_PUPD10_Pos)
     
    #define GPIO_PUPDR_PUPD10_1   (0x2UL << GPIO_PUPDR_PUPD10_Pos)
     
    #define GPIO_PUPDR_PUPD11_Pos   (22U)
     
    #define GPIO_PUPDR_PUPD11_Msk   (0x3UL << GPIO_PUPDR_PUPD11_Pos)
     
    #define GPIO_PUPDR_PUPD11   GPIO_PUPDR_PUPD11_Msk
     
    #define GPIO_PUPDR_PUPD11_0   (0x1UL << GPIO_PUPDR_PUPD11_Pos)
     
    #define GPIO_PUPDR_PUPD11_1   (0x2UL << GPIO_PUPDR_PUPD11_Pos)
     
    #define GPIO_PUPDR_PUPD12_Pos   (24U)
     
    #define GPIO_PUPDR_PUPD12_Msk   (0x3UL << GPIO_PUPDR_PUPD12_Pos)
     
    #define GPIO_PUPDR_PUPD12   GPIO_PUPDR_PUPD12_Msk
     
    #define GPIO_PUPDR_PUPD12_0   (0x1UL << GPIO_PUPDR_PUPD12_Pos)
     
    #define GPIO_PUPDR_PUPD12_1   (0x2UL << GPIO_PUPDR_PUPD12_Pos)
     
    #define GPIO_PUPDR_PUPD13_Pos   (26U)
     
    #define GPIO_PUPDR_PUPD13_Msk   (0x3UL << GPIO_PUPDR_PUPD13_Pos)
     
    #define GPIO_PUPDR_PUPD13   GPIO_PUPDR_PUPD13_Msk
     
    #define GPIO_PUPDR_PUPD13_0   (0x1UL << GPIO_PUPDR_PUPD13_Pos)
     
    #define GPIO_PUPDR_PUPD13_1   (0x2UL << GPIO_PUPDR_PUPD13_Pos)
     
    #define GPIO_PUPDR_PUPD14_Pos   (28U)
     
    #define GPIO_PUPDR_PUPD14_Msk   (0x3UL << GPIO_PUPDR_PUPD14_Pos)
     
    #define GPIO_PUPDR_PUPD14   GPIO_PUPDR_PUPD14_Msk
     
    #define GPIO_PUPDR_PUPD14_0   (0x1UL << GPIO_PUPDR_PUPD14_Pos)
     
    #define GPIO_PUPDR_PUPD14_1   (0x2UL << GPIO_PUPDR_PUPD14_Pos)
     
    #define GPIO_PUPDR_PUPD15_Pos   (30U)
     
    #define GPIO_PUPDR_PUPD15_Msk   (0x3UL << GPIO_PUPDR_PUPD15_Pos)
     
    #define GPIO_PUPDR_PUPD15   GPIO_PUPDR_PUPD15_Msk
     
    #define GPIO_PUPDR_PUPD15_0   (0x1UL << GPIO_PUPDR_PUPD15_Pos)
     
    #define GPIO_PUPDR_PUPD15_1   (0x2UL << GPIO_PUPDR_PUPD15_Pos)
     
    #define GPIO_PUPDR_PUPDR0   GPIO_PUPDR_PUPD0
     
    #define GPIO_PUPDR_PUPDR0_0   GPIO_PUPDR_PUPD0_0
     
    #define GPIO_PUPDR_PUPDR0_1   GPIO_PUPDR_PUPD0_1
     
    #define GPIO_PUPDR_PUPDR1   GPIO_PUPDR_PUPD1
     
    #define GPIO_PUPDR_PUPDR1_0   GPIO_PUPDR_PUPD1_0
     
    #define GPIO_PUPDR_PUPDR1_1   GPIO_PUPDR_PUPD1_1
     
    #define GPIO_PUPDR_PUPDR2   GPIO_PUPDR_PUPD2
     
    #define GPIO_PUPDR_PUPDR2_0   GPIO_PUPDR_PUPD2_0
     
    #define GPIO_PUPDR_PUPDR2_1   GPIO_PUPDR_PUPD2_1
     
    #define GPIO_PUPDR_PUPDR3   GPIO_PUPDR_PUPD3
     
    #define GPIO_PUPDR_PUPDR3_0   GPIO_PUPDR_PUPD3_0
     
    #define GPIO_PUPDR_PUPDR3_1   GPIO_PUPDR_PUPD3_1
     
    #define GPIO_PUPDR_PUPDR4   GPIO_PUPDR_PUPD4
     
    #define GPIO_PUPDR_PUPDR4_0   GPIO_PUPDR_PUPD4_0
     
    #define GPIO_PUPDR_PUPDR4_1   GPIO_PUPDR_PUPD4_1
     
    #define GPIO_PUPDR_PUPDR5   GPIO_PUPDR_PUPD5
     
    #define GPIO_PUPDR_PUPDR5_0   GPIO_PUPDR_PUPD5_0
     
    #define GPIO_PUPDR_PUPDR5_1   GPIO_PUPDR_PUPD5_1
     
    #define GPIO_PUPDR_PUPDR6   GPIO_PUPDR_PUPD6
     
    #define GPIO_PUPDR_PUPDR6_0   GPIO_PUPDR_PUPD6_0
     
    #define GPIO_PUPDR_PUPDR6_1   GPIO_PUPDR_PUPD6_1
     
    #define GPIO_PUPDR_PUPDR7   GPIO_PUPDR_PUPD7
     
    #define GPIO_PUPDR_PUPDR7_0   GPIO_PUPDR_PUPD7_0
     
    #define GPIO_PUPDR_PUPDR7_1   GPIO_PUPDR_PUPD7_1
     
    #define GPIO_PUPDR_PUPDR8   GPIO_PUPDR_PUPD8
     
    #define GPIO_PUPDR_PUPDR8_0   GPIO_PUPDR_PUPD8_0
     
    #define GPIO_PUPDR_PUPDR8_1   GPIO_PUPDR_PUPD8_1
     
    #define GPIO_PUPDR_PUPDR9   GPIO_PUPDR_PUPD9
     
    #define GPIO_PUPDR_PUPDR9_0   GPIO_PUPDR_PUPD9_0
     
    #define GPIO_PUPDR_PUPDR9_1   GPIO_PUPDR_PUPD9_1
     
    #define GPIO_PUPDR_PUPDR10   GPIO_PUPDR_PUPD10
     
    #define GPIO_PUPDR_PUPDR10_0   GPIO_PUPDR_PUPD10_0
     
    #define GPIO_PUPDR_PUPDR10_1   GPIO_PUPDR_PUPD10_1
     
    #define GPIO_PUPDR_PUPDR11   GPIO_PUPDR_PUPD11
     
    #define GPIO_PUPDR_PUPDR11_0   GPIO_PUPDR_PUPD11_0
     
    #define GPIO_PUPDR_PUPDR11_1   GPIO_PUPDR_PUPD11_1
     
    #define GPIO_PUPDR_PUPDR12   GPIO_PUPDR_PUPD12
     
    #define GPIO_PUPDR_PUPDR12_0   GPIO_PUPDR_PUPD12_0
     
    #define GPIO_PUPDR_PUPDR12_1   GPIO_PUPDR_PUPD12_1
     
    #define GPIO_PUPDR_PUPDR13   GPIO_PUPDR_PUPD13
     
    #define GPIO_PUPDR_PUPDR13_0   GPIO_PUPDR_PUPD13_0
     
    #define GPIO_PUPDR_PUPDR13_1   GPIO_PUPDR_PUPD13_1
     
    #define GPIO_PUPDR_PUPDR14   GPIO_PUPDR_PUPD14
     
    #define GPIO_PUPDR_PUPDR14_0   GPIO_PUPDR_PUPD14_0
     
    #define GPIO_PUPDR_PUPDR14_1   GPIO_PUPDR_PUPD14_1
     
    #define GPIO_PUPDR_PUPDR15   GPIO_PUPDR_PUPD15
     
    #define GPIO_PUPDR_PUPDR15_0   GPIO_PUPDR_PUPD15_0
     
    #define GPIO_PUPDR_PUPDR15_1   GPIO_PUPDR_PUPD15_1
     
    #define GPIO_IDR_ID0_Pos   (0U)
     
    #define GPIO_IDR_ID0_Msk   (0x1UL << GPIO_IDR_ID0_Pos)
     
    #define GPIO_IDR_ID0   GPIO_IDR_ID0_Msk
     
    #define GPIO_IDR_ID1_Pos   (1U)
     
    #define GPIO_IDR_ID1_Msk   (0x1UL << GPIO_IDR_ID1_Pos)
     
    #define GPIO_IDR_ID1   GPIO_IDR_ID1_Msk
     
    #define GPIO_IDR_ID2_Pos   (2U)
     
    #define GPIO_IDR_ID2_Msk   (0x1UL << GPIO_IDR_ID2_Pos)
     
    #define GPIO_IDR_ID2   GPIO_IDR_ID2_Msk
     
    #define GPIO_IDR_ID3_Pos   (3U)
     
    #define GPIO_IDR_ID3_Msk   (0x1UL << GPIO_IDR_ID3_Pos)
     
    #define GPIO_IDR_ID3   GPIO_IDR_ID3_Msk
     
    #define GPIO_IDR_ID4_Pos   (4U)
     
    #define GPIO_IDR_ID4_Msk   (0x1UL << GPIO_IDR_ID4_Pos)
     
    #define GPIO_IDR_ID4   GPIO_IDR_ID4_Msk
     
    #define GPIO_IDR_ID5_Pos   (5U)
     
    #define GPIO_IDR_ID5_Msk   (0x1UL << GPIO_IDR_ID5_Pos)
     
    #define GPIO_IDR_ID5   GPIO_IDR_ID5_Msk
     
    #define GPIO_IDR_ID6_Pos   (6U)
     
    #define GPIO_IDR_ID6_Msk   (0x1UL << GPIO_IDR_ID6_Pos)
     
    #define GPIO_IDR_ID6   GPIO_IDR_ID6_Msk
     
    #define GPIO_IDR_ID7_Pos   (7U)
     
    #define GPIO_IDR_ID7_Msk   (0x1UL << GPIO_IDR_ID7_Pos)
     
    #define GPIO_IDR_ID7   GPIO_IDR_ID7_Msk
     
    #define GPIO_IDR_ID8_Pos   (8U)
     
    #define GPIO_IDR_ID8_Msk   (0x1UL << GPIO_IDR_ID8_Pos)
     
    #define GPIO_IDR_ID8   GPIO_IDR_ID8_Msk
     
    #define GPIO_IDR_ID9_Pos   (9U)
     
    #define GPIO_IDR_ID9_Msk   (0x1UL << GPIO_IDR_ID9_Pos)
     
    #define GPIO_IDR_ID9   GPIO_IDR_ID9_Msk
     
    #define GPIO_IDR_ID10_Pos   (10U)
     
    #define GPIO_IDR_ID10_Msk   (0x1UL << GPIO_IDR_ID10_Pos)
     
    #define GPIO_IDR_ID10   GPIO_IDR_ID10_Msk
     
    #define GPIO_IDR_ID11_Pos   (11U)
     
    #define GPIO_IDR_ID11_Msk   (0x1UL << GPIO_IDR_ID11_Pos)
     
    #define GPIO_IDR_ID11   GPIO_IDR_ID11_Msk
     
    #define GPIO_IDR_ID12_Pos   (12U)
     
    #define GPIO_IDR_ID12_Msk   (0x1UL << GPIO_IDR_ID12_Pos)
     
    #define GPIO_IDR_ID12   GPIO_IDR_ID12_Msk
     
    #define GPIO_IDR_ID13_Pos   (13U)
     
    #define GPIO_IDR_ID13_Msk   (0x1UL << GPIO_IDR_ID13_Pos)
     
    #define GPIO_IDR_ID13   GPIO_IDR_ID13_Msk
     
    #define GPIO_IDR_ID14_Pos   (14U)
     
    #define GPIO_IDR_ID14_Msk   (0x1UL << GPIO_IDR_ID14_Pos)
     
    #define GPIO_IDR_ID14   GPIO_IDR_ID14_Msk
     
    #define GPIO_IDR_ID15_Pos   (15U)
     
    #define GPIO_IDR_ID15_Msk   (0x1UL << GPIO_IDR_ID15_Pos)
     
    #define GPIO_IDR_ID15   GPIO_IDR_ID15_Msk
     
    #define GPIO_IDR_IDR_0   GPIO_IDR_ID0
     
    #define GPIO_IDR_IDR_1   GPIO_IDR_ID1
     
    #define GPIO_IDR_IDR_2   GPIO_IDR_ID2
     
    #define GPIO_IDR_IDR_3   GPIO_IDR_ID3
     
    #define GPIO_IDR_IDR_4   GPIO_IDR_ID4
     
    #define GPIO_IDR_IDR_5   GPIO_IDR_ID5
     
    #define GPIO_IDR_IDR_6   GPIO_IDR_ID6
     
    #define GPIO_IDR_IDR_7   GPIO_IDR_ID7
     
    #define GPIO_IDR_IDR_8   GPIO_IDR_ID8
     
    #define GPIO_IDR_IDR_9   GPIO_IDR_ID9
     
    #define GPIO_IDR_IDR_10   GPIO_IDR_ID10
     
    #define GPIO_IDR_IDR_11   GPIO_IDR_ID11
     
    #define GPIO_IDR_IDR_12   GPIO_IDR_ID12
     
    #define GPIO_IDR_IDR_13   GPIO_IDR_ID13
     
    #define GPIO_IDR_IDR_14   GPIO_IDR_ID14
     
    #define GPIO_IDR_IDR_15   GPIO_IDR_ID15
     
    #define GPIO_ODR_OD0_Pos   (0U)
     
    #define GPIO_ODR_OD0_Msk   (0x1UL << GPIO_ODR_OD0_Pos)
     
    #define GPIO_ODR_OD0   GPIO_ODR_OD0_Msk
     
    #define GPIO_ODR_OD1_Pos   (1U)
     
    #define GPIO_ODR_OD1_Msk   (0x1UL << GPIO_ODR_OD1_Pos)
     
    #define GPIO_ODR_OD1   GPIO_ODR_OD1_Msk
     
    #define GPIO_ODR_OD2_Pos   (2U)
     
    #define GPIO_ODR_OD2_Msk   (0x1UL << GPIO_ODR_OD2_Pos)
     
    #define GPIO_ODR_OD2   GPIO_ODR_OD2_Msk
     
    #define GPIO_ODR_OD3_Pos   (3U)
     
    #define GPIO_ODR_OD3_Msk   (0x1UL << GPIO_ODR_OD3_Pos)
     
    #define GPIO_ODR_OD3   GPIO_ODR_OD3_Msk
     
    #define GPIO_ODR_OD4_Pos   (4U)
     
    #define GPIO_ODR_OD4_Msk   (0x1UL << GPIO_ODR_OD4_Pos)
     
    #define GPIO_ODR_OD4   GPIO_ODR_OD4_Msk
     
    #define GPIO_ODR_OD5_Pos   (5U)
     
    #define GPIO_ODR_OD5_Msk   (0x1UL << GPIO_ODR_OD5_Pos)
     
    #define GPIO_ODR_OD5   GPIO_ODR_OD5_Msk
     
    #define GPIO_ODR_OD6_Pos   (6U)
     
    #define GPIO_ODR_OD6_Msk   (0x1UL << GPIO_ODR_OD6_Pos)
     
    #define GPIO_ODR_OD6   GPIO_ODR_OD6_Msk
     
    #define GPIO_ODR_OD7_Pos   (7U)
     
    #define GPIO_ODR_OD7_Msk   (0x1UL << GPIO_ODR_OD7_Pos)
     
    #define GPIO_ODR_OD7   GPIO_ODR_OD7_Msk
     
    #define GPIO_ODR_OD8_Pos   (8U)
     
    #define GPIO_ODR_OD8_Msk   (0x1UL << GPIO_ODR_OD8_Pos)
     
    #define GPIO_ODR_OD8   GPIO_ODR_OD8_Msk
     
    #define GPIO_ODR_OD9_Pos   (9U)
     
    #define GPIO_ODR_OD9_Msk   (0x1UL << GPIO_ODR_OD9_Pos)
     
    #define GPIO_ODR_OD9   GPIO_ODR_OD9_Msk
     
    #define GPIO_ODR_OD10_Pos   (10U)
     
    #define GPIO_ODR_OD10_Msk   (0x1UL << GPIO_ODR_OD10_Pos)
     
    #define GPIO_ODR_OD10   GPIO_ODR_OD10_Msk
     
    #define GPIO_ODR_OD11_Pos   (11U)
     
    #define GPIO_ODR_OD11_Msk   (0x1UL << GPIO_ODR_OD11_Pos)
     
    #define GPIO_ODR_OD11   GPIO_ODR_OD11_Msk
     
    #define GPIO_ODR_OD12_Pos   (12U)
     
    #define GPIO_ODR_OD12_Msk   (0x1UL << GPIO_ODR_OD12_Pos)
     
    #define GPIO_ODR_OD12   GPIO_ODR_OD12_Msk
     
    #define GPIO_ODR_OD13_Pos   (13U)
     
    #define GPIO_ODR_OD13_Msk   (0x1UL << GPIO_ODR_OD13_Pos)
     
    #define GPIO_ODR_OD13   GPIO_ODR_OD13_Msk
     
    #define GPIO_ODR_OD14_Pos   (14U)
     
    #define GPIO_ODR_OD14_Msk   (0x1UL << GPIO_ODR_OD14_Pos)
     
    #define GPIO_ODR_OD14   GPIO_ODR_OD14_Msk
     
    #define GPIO_ODR_OD15_Pos   (15U)
     
    #define GPIO_ODR_OD15_Msk   (0x1UL << GPIO_ODR_OD15_Pos)
     
    #define GPIO_ODR_OD15   GPIO_ODR_OD15_Msk
     
    #define GPIO_ODR_ODR_0   GPIO_ODR_OD0
     
    #define GPIO_ODR_ODR_1   GPIO_ODR_OD1
     
    #define GPIO_ODR_ODR_2   GPIO_ODR_OD2
     
    #define GPIO_ODR_ODR_3   GPIO_ODR_OD3
     
    #define GPIO_ODR_ODR_4   GPIO_ODR_OD4
     
    #define GPIO_ODR_ODR_5   GPIO_ODR_OD5
     
    #define GPIO_ODR_ODR_6   GPIO_ODR_OD6
     
    #define GPIO_ODR_ODR_7   GPIO_ODR_OD7
     
    #define GPIO_ODR_ODR_8   GPIO_ODR_OD8
     
    #define GPIO_ODR_ODR_9   GPIO_ODR_OD9
     
    #define GPIO_ODR_ODR_10   GPIO_ODR_OD10
     
    #define GPIO_ODR_ODR_11   GPIO_ODR_OD11
     
    #define GPIO_ODR_ODR_12   GPIO_ODR_OD12
     
    #define GPIO_ODR_ODR_13   GPIO_ODR_OD13
     
    #define GPIO_ODR_ODR_14   GPIO_ODR_OD14
     
    #define GPIO_ODR_ODR_15   GPIO_ODR_OD15
     
    #define GPIO_BSRR_BS0_Pos   (0U)
     
    #define GPIO_BSRR_BS0_Msk   (0x1UL << GPIO_BSRR_BS0_Pos)
     
    #define GPIO_BSRR_BS0   GPIO_BSRR_BS0_Msk
     
    #define GPIO_BSRR_BS1_Pos   (1U)
     
    #define GPIO_BSRR_BS1_Msk   (0x1UL << GPIO_BSRR_BS1_Pos)
     
    #define GPIO_BSRR_BS1   GPIO_BSRR_BS1_Msk
     
    #define GPIO_BSRR_BS2_Pos   (2U)
     
    #define GPIO_BSRR_BS2_Msk   (0x1UL << GPIO_BSRR_BS2_Pos)
     
    #define GPIO_BSRR_BS2   GPIO_BSRR_BS2_Msk
     
    #define GPIO_BSRR_BS3_Pos   (3U)
     
    #define GPIO_BSRR_BS3_Msk   (0x1UL << GPIO_BSRR_BS3_Pos)
     
    #define GPIO_BSRR_BS3   GPIO_BSRR_BS3_Msk
     
    #define GPIO_BSRR_BS4_Pos   (4U)
     
    #define GPIO_BSRR_BS4_Msk   (0x1UL << GPIO_BSRR_BS4_Pos)
     
    #define GPIO_BSRR_BS4   GPIO_BSRR_BS4_Msk
     
    #define GPIO_BSRR_BS5_Pos   (5U)
     
    #define GPIO_BSRR_BS5_Msk   (0x1UL << GPIO_BSRR_BS5_Pos)
     
    #define GPIO_BSRR_BS5   GPIO_BSRR_BS5_Msk
     
    #define GPIO_BSRR_BS6_Pos   (6U)
     
    #define GPIO_BSRR_BS6_Msk   (0x1UL << GPIO_BSRR_BS6_Pos)
     
    #define GPIO_BSRR_BS6   GPIO_BSRR_BS6_Msk
     
    #define GPIO_BSRR_BS7_Pos   (7U)
     
    #define GPIO_BSRR_BS7_Msk   (0x1UL << GPIO_BSRR_BS7_Pos)
     
    #define GPIO_BSRR_BS7   GPIO_BSRR_BS7_Msk
     
    #define GPIO_BSRR_BS8_Pos   (8U)
     
    #define GPIO_BSRR_BS8_Msk   (0x1UL << GPIO_BSRR_BS8_Pos)
     
    #define GPIO_BSRR_BS8   GPIO_BSRR_BS8_Msk
     
    #define GPIO_BSRR_BS9_Pos   (9U)
     
    #define GPIO_BSRR_BS9_Msk   (0x1UL << GPIO_BSRR_BS9_Pos)
     
    #define GPIO_BSRR_BS9   GPIO_BSRR_BS9_Msk
     
    #define GPIO_BSRR_BS10_Pos   (10U)
     
    #define GPIO_BSRR_BS10_Msk   (0x1UL << GPIO_BSRR_BS10_Pos)
     
    #define GPIO_BSRR_BS10   GPIO_BSRR_BS10_Msk
     
    #define GPIO_BSRR_BS11_Pos   (11U)
     
    #define GPIO_BSRR_BS11_Msk   (0x1UL << GPIO_BSRR_BS11_Pos)
     
    #define GPIO_BSRR_BS11   GPIO_BSRR_BS11_Msk
     
    #define GPIO_BSRR_BS12_Pos   (12U)
     
    #define GPIO_BSRR_BS12_Msk   (0x1UL << GPIO_BSRR_BS12_Pos)
     
    #define GPIO_BSRR_BS12   GPIO_BSRR_BS12_Msk
     
    #define GPIO_BSRR_BS13_Pos   (13U)
     
    #define GPIO_BSRR_BS13_Msk   (0x1UL << GPIO_BSRR_BS13_Pos)
     
    #define GPIO_BSRR_BS13   GPIO_BSRR_BS13_Msk
     
    #define GPIO_BSRR_BS14_Pos   (14U)
     
    #define GPIO_BSRR_BS14_Msk   (0x1UL << GPIO_BSRR_BS14_Pos)
     
    #define GPIO_BSRR_BS14   GPIO_BSRR_BS14_Msk
     
    #define GPIO_BSRR_BS15_Pos   (15U)
     
    #define GPIO_BSRR_BS15_Msk   (0x1UL << GPIO_BSRR_BS15_Pos)
     
    #define GPIO_BSRR_BS15   GPIO_BSRR_BS15_Msk
     
    #define GPIO_BSRR_BR0_Pos   (16U)
     
    #define GPIO_BSRR_BR0_Msk   (0x1UL << GPIO_BSRR_BR0_Pos)
     
    #define GPIO_BSRR_BR0   GPIO_BSRR_BR0_Msk
     
    #define GPIO_BSRR_BR1_Pos   (17U)
     
    #define GPIO_BSRR_BR1_Msk   (0x1UL << GPIO_BSRR_BR1_Pos)
     
    #define GPIO_BSRR_BR1   GPIO_BSRR_BR1_Msk
     
    #define GPIO_BSRR_BR2_Pos   (18U)
     
    #define GPIO_BSRR_BR2_Msk   (0x1UL << GPIO_BSRR_BR2_Pos)
     
    #define GPIO_BSRR_BR2   GPIO_BSRR_BR2_Msk
     
    #define GPIO_BSRR_BR3_Pos   (19U)
     
    #define GPIO_BSRR_BR3_Msk   (0x1UL << GPIO_BSRR_BR3_Pos)
     
    #define GPIO_BSRR_BR3   GPIO_BSRR_BR3_Msk
     
    #define GPIO_BSRR_BR4_Pos   (20U)
     
    #define GPIO_BSRR_BR4_Msk   (0x1UL << GPIO_BSRR_BR4_Pos)
     
    #define GPIO_BSRR_BR4   GPIO_BSRR_BR4_Msk
     
    #define GPIO_BSRR_BR5_Pos   (21U)
     
    #define GPIO_BSRR_BR5_Msk   (0x1UL << GPIO_BSRR_BR5_Pos)
     
    #define GPIO_BSRR_BR5   GPIO_BSRR_BR5_Msk
     
    #define GPIO_BSRR_BR6_Pos   (22U)
     
    #define GPIO_BSRR_BR6_Msk   (0x1UL << GPIO_BSRR_BR6_Pos)
     
    #define GPIO_BSRR_BR6   GPIO_BSRR_BR6_Msk
     
    #define GPIO_BSRR_BR7_Pos   (23U)
     
    #define GPIO_BSRR_BR7_Msk   (0x1UL << GPIO_BSRR_BR7_Pos)
     
    #define GPIO_BSRR_BR7   GPIO_BSRR_BR7_Msk
     
    #define GPIO_BSRR_BR8_Pos   (24U)
     
    #define GPIO_BSRR_BR8_Msk   (0x1UL << GPIO_BSRR_BR8_Pos)
     
    #define GPIO_BSRR_BR8   GPIO_BSRR_BR8_Msk
     
    #define GPIO_BSRR_BR9_Pos   (25U)
     
    #define GPIO_BSRR_BR9_Msk   (0x1UL << GPIO_BSRR_BR9_Pos)
     
    #define GPIO_BSRR_BR9   GPIO_BSRR_BR9_Msk
     
    #define GPIO_BSRR_BR10_Pos   (26U)
     
    #define GPIO_BSRR_BR10_Msk   (0x1UL << GPIO_BSRR_BR10_Pos)
     
    #define GPIO_BSRR_BR10   GPIO_BSRR_BR10_Msk
     
    #define GPIO_BSRR_BR11_Pos   (27U)
     
    #define GPIO_BSRR_BR11_Msk   (0x1UL << GPIO_BSRR_BR11_Pos)
     
    #define GPIO_BSRR_BR11   GPIO_BSRR_BR11_Msk
     
    #define GPIO_BSRR_BR12_Pos   (28U)
     
    #define GPIO_BSRR_BR12_Msk   (0x1UL << GPIO_BSRR_BR12_Pos)
     
    #define GPIO_BSRR_BR12   GPIO_BSRR_BR12_Msk
     
    #define GPIO_BSRR_BR13_Pos   (29U)
     
    #define GPIO_BSRR_BR13_Msk   (0x1UL << GPIO_BSRR_BR13_Pos)
     
    #define GPIO_BSRR_BR13   GPIO_BSRR_BR13_Msk
     
    #define GPIO_BSRR_BR14_Pos   (30U)
     
    #define GPIO_BSRR_BR14_Msk   (0x1UL << GPIO_BSRR_BR14_Pos)
     
    #define GPIO_BSRR_BR14   GPIO_BSRR_BR14_Msk
     
    #define GPIO_BSRR_BR15_Pos   (31U)
     
    #define GPIO_BSRR_BR15_Msk   (0x1UL << GPIO_BSRR_BR15_Pos)
     
    #define GPIO_BSRR_BR15   GPIO_BSRR_BR15_Msk
     
    #define GPIO_BSRR_BS_0   GPIO_BSRR_BS0
     
    #define GPIO_BSRR_BS_1   GPIO_BSRR_BS1
     
    #define GPIO_BSRR_BS_2   GPIO_BSRR_BS2
     
    #define GPIO_BSRR_BS_3   GPIO_BSRR_BS3
     
    #define GPIO_BSRR_BS_4   GPIO_BSRR_BS4
     
    #define GPIO_BSRR_BS_5   GPIO_BSRR_BS5
     
    #define GPIO_BSRR_BS_6   GPIO_BSRR_BS6
     
    #define GPIO_BSRR_BS_7   GPIO_BSRR_BS7
     
    #define GPIO_BSRR_BS_8   GPIO_BSRR_BS8
     
    #define GPIO_BSRR_BS_9   GPIO_BSRR_BS9
     
    #define GPIO_BSRR_BS_10   GPIO_BSRR_BS10
     
    #define GPIO_BSRR_BS_11   GPIO_BSRR_BS11
     
    #define GPIO_BSRR_BS_12   GPIO_BSRR_BS12
     
    #define GPIO_BSRR_BS_13   GPIO_BSRR_BS13
     
    #define GPIO_BSRR_BS_14   GPIO_BSRR_BS14
     
    #define GPIO_BSRR_BS_15   GPIO_BSRR_BS15
     
    #define GPIO_BSRR_BR_0   GPIO_BSRR_BR0
     
    #define GPIO_BSRR_BR_1   GPIO_BSRR_BR1
     
    #define GPIO_BSRR_BR_2   GPIO_BSRR_BR2
     
    #define GPIO_BSRR_BR_3   GPIO_BSRR_BR3
     
    #define GPIO_BSRR_BR_4   GPIO_BSRR_BR4
     
    #define GPIO_BSRR_BR_5   GPIO_BSRR_BR5
     
    #define GPIO_BSRR_BR_6   GPIO_BSRR_BR6
     
    #define GPIO_BSRR_BR_7   GPIO_BSRR_BR7
     
    #define GPIO_BSRR_BR_8   GPIO_BSRR_BR8
     
    #define GPIO_BSRR_BR_9   GPIO_BSRR_BR9
     
    #define GPIO_BSRR_BR_10   GPIO_BSRR_BR10
     
    #define GPIO_BSRR_BR_11   GPIO_BSRR_BR11
     
    #define GPIO_BSRR_BR_12   GPIO_BSRR_BR12
     
    #define GPIO_BSRR_BR_13   GPIO_BSRR_BR13
     
    #define GPIO_BSRR_BR_14   GPIO_BSRR_BR14
     
    #define GPIO_BSRR_BR_15   GPIO_BSRR_BR15
     
    #define GPIO_BRR_BR0   GPIO_BSRR_BR0
     
    #define GPIO_BRR_BR0_Pos   GPIO_BSRR_BR0_Pos
     
    #define GPIO_BRR_BR0_Msk   GPIO_BSRR_BR0_Msk
     
    #define GPIO_BRR_BR1   GPIO_BSRR_BR1
     
    #define GPIO_BRR_BR1_Pos   GPIO_BSRR_BR1_Pos
     
    #define GPIO_BRR_BR1_Msk   GPIO_BSRR_BR1_Msk
     
    #define GPIO_BRR_BR2   GPIO_BSRR_BR2
     
    #define GPIO_BRR_BR2_Pos   GPIO_BSRR_BR2_Pos
     
    #define GPIO_BRR_BR2_Msk   GPIO_BSRR_BR2_Msk
     
    #define GPIO_BRR_BR3   GPIO_BSRR_BR3
     
    #define GPIO_BRR_BR3_Pos   GPIO_BSRR_BR3_Pos
     
    #define GPIO_BRR_BR3_Msk   GPIO_BSRR_BR3_Msk
     
    #define GPIO_BRR_BR4   GPIO_BSRR_BR4
     
    #define GPIO_BRR_BR4_Pos   GPIO_BSRR_BR4_Pos
     
    #define GPIO_BRR_BR4_Msk   GPIO_BSRR_BR4_Msk
     
    #define GPIO_BRR_BR5   GPIO_BSRR_BR5
     
    #define GPIO_BRR_BR5_Pos   GPIO_BSRR_BR5_Pos
     
    #define GPIO_BRR_BR5_Msk   GPIO_BSRR_BR5_Msk
     
    #define GPIO_BRR_BR6   GPIO_BSRR_BR6
     
    #define GPIO_BRR_BR6_Pos   GPIO_BSRR_BR6_Pos
     
    #define GPIO_BRR_BR6_Msk   GPIO_BSRR_BR6_Msk
     
    #define GPIO_BRR_BR7   GPIO_BSRR_BR7
     
    #define GPIO_BRR_BR7_Pos   GPIO_BSRR_BR7_Pos
     
    #define GPIO_BRR_BR7_Msk   GPIO_BSRR_BR7_Msk
     
    #define GPIO_BRR_BR8   GPIO_BSRR_BR8
     
    #define GPIO_BRR_BR8_Pos   GPIO_BSRR_BR8_Pos
     
    #define GPIO_BRR_BR8_Msk   GPIO_BSRR_BR8_Msk
     
    #define GPIO_BRR_BR9   GPIO_BSRR_BR9
     
    #define GPIO_BRR_BR9_Pos   GPIO_BSRR_BR9_Pos
     
    #define GPIO_BRR_BR9_Msk   GPIO_BSRR_BR9_Msk
     
    #define GPIO_BRR_BR10   GPIO_BSRR_BR10
     
    #define GPIO_BRR_BR10_Pos   GPIO_BSRR_BR10_Pos
     
    #define GPIO_BRR_BR10_Msk   GPIO_BSRR_BR10_Msk
     
    #define GPIO_BRR_BR11   GPIO_BSRR_BR11
     
    #define GPIO_BRR_BR11_Pos   GPIO_BSRR_BR11_Pos
     
    #define GPIO_BRR_BR11_Msk   GPIO_BSRR_BR11_Msk
     
    #define GPIO_BRR_BR12   GPIO_BSRR_BR12
     
    #define GPIO_BRR_BR12_Pos   GPIO_BSRR_BR12_Pos
     
    #define GPIO_BRR_BR12_Msk   GPIO_BSRR_BR12_Msk
     
    #define GPIO_BRR_BR13   GPIO_BSRR_BR13
     
    #define GPIO_BRR_BR13_Pos   GPIO_BSRR_BR13_Pos
     
    #define GPIO_BRR_BR13_Msk   GPIO_BSRR_BR13_Msk
     
    #define GPIO_BRR_BR14   GPIO_BSRR_BR14
     
    #define GPIO_BRR_BR14_Pos   GPIO_BSRR_BR14_Pos
     
    #define GPIO_BRR_BR14_Msk   GPIO_BSRR_BR14_Msk
     
    #define GPIO_BRR_BR15   GPIO_BSRR_BR15
     
    #define GPIO_BRR_BR15_Pos   GPIO_BSRR_BR15_Pos
     
    #define GPIO_BRR_BR15_Msk   GPIO_BSRR_BR15_Msk
     
    #define GPIO_LCKR_LCK0_Pos   (0U)
     
    #define GPIO_LCKR_LCK0_Msk   (0x1UL << GPIO_LCKR_LCK0_Pos)
     
    #define GPIO_LCKR_LCK0   GPIO_LCKR_LCK0_Msk
     
    #define GPIO_LCKR_LCK1_Pos   (1U)
     
    #define GPIO_LCKR_LCK1_Msk   (0x1UL << GPIO_LCKR_LCK1_Pos)
     
    #define GPIO_LCKR_LCK1   GPIO_LCKR_LCK1_Msk
     
    #define GPIO_LCKR_LCK2_Pos   (2U)
     
    #define GPIO_LCKR_LCK2_Msk   (0x1UL << GPIO_LCKR_LCK2_Pos)
     
    #define GPIO_LCKR_LCK2   GPIO_LCKR_LCK2_Msk
     
    #define GPIO_LCKR_LCK3_Pos   (3U)
     
    #define GPIO_LCKR_LCK3_Msk   (0x1UL << GPIO_LCKR_LCK3_Pos)
     
    #define GPIO_LCKR_LCK3   GPIO_LCKR_LCK3_Msk
     
    #define GPIO_LCKR_LCK4_Pos   (4U)
     
    #define GPIO_LCKR_LCK4_Msk   (0x1UL << GPIO_LCKR_LCK4_Pos)
     
    #define GPIO_LCKR_LCK4   GPIO_LCKR_LCK4_Msk
     
    #define GPIO_LCKR_LCK5_Pos   (5U)
     
    #define GPIO_LCKR_LCK5_Msk   (0x1UL << GPIO_LCKR_LCK5_Pos)
     
    #define GPIO_LCKR_LCK5   GPIO_LCKR_LCK5_Msk
     
    #define GPIO_LCKR_LCK6_Pos   (6U)
     
    #define GPIO_LCKR_LCK6_Msk   (0x1UL << GPIO_LCKR_LCK6_Pos)
     
    #define GPIO_LCKR_LCK6   GPIO_LCKR_LCK6_Msk
     
    #define GPIO_LCKR_LCK7_Pos   (7U)
     
    #define GPIO_LCKR_LCK7_Msk   (0x1UL << GPIO_LCKR_LCK7_Pos)
     
    #define GPIO_LCKR_LCK7   GPIO_LCKR_LCK7_Msk
     
    #define GPIO_LCKR_LCK8_Pos   (8U)
     
    #define GPIO_LCKR_LCK8_Msk   (0x1UL << GPIO_LCKR_LCK8_Pos)
     
    #define GPIO_LCKR_LCK8   GPIO_LCKR_LCK8_Msk
     
    #define GPIO_LCKR_LCK9_Pos   (9U)
     
    #define GPIO_LCKR_LCK9_Msk   (0x1UL << GPIO_LCKR_LCK9_Pos)
     
    #define GPIO_LCKR_LCK9   GPIO_LCKR_LCK9_Msk
     
    #define GPIO_LCKR_LCK10_Pos   (10U)
     
    #define GPIO_LCKR_LCK10_Msk   (0x1UL << GPIO_LCKR_LCK10_Pos)
     
    #define GPIO_LCKR_LCK10   GPIO_LCKR_LCK10_Msk
     
    #define GPIO_LCKR_LCK11_Pos   (11U)
     
    #define GPIO_LCKR_LCK11_Msk   (0x1UL << GPIO_LCKR_LCK11_Pos)
     
    #define GPIO_LCKR_LCK11   GPIO_LCKR_LCK11_Msk
     
    #define GPIO_LCKR_LCK12_Pos   (12U)
     
    #define GPIO_LCKR_LCK12_Msk   (0x1UL << GPIO_LCKR_LCK12_Pos)
     
    #define GPIO_LCKR_LCK12   GPIO_LCKR_LCK12_Msk
     
    #define GPIO_LCKR_LCK13_Pos   (13U)
     
    #define GPIO_LCKR_LCK13_Msk   (0x1UL << GPIO_LCKR_LCK13_Pos)
     
    #define GPIO_LCKR_LCK13   GPIO_LCKR_LCK13_Msk
     
    #define GPIO_LCKR_LCK14_Pos   (14U)
     
    #define GPIO_LCKR_LCK14_Msk   (0x1UL << GPIO_LCKR_LCK14_Pos)
     
    #define GPIO_LCKR_LCK14   GPIO_LCKR_LCK14_Msk
     
    #define GPIO_LCKR_LCK15_Pos   (15U)
     
    #define GPIO_LCKR_LCK15_Msk   (0x1UL << GPIO_LCKR_LCK15_Pos)
     
    #define GPIO_LCKR_LCK15   GPIO_LCKR_LCK15_Msk
     
    #define GPIO_LCKR_LCKK_Pos   (16U)
     
    #define GPIO_LCKR_LCKK_Msk   (0x1UL << GPIO_LCKR_LCKK_Pos)
     
    #define GPIO_LCKR_LCKK   GPIO_LCKR_LCKK_Msk
     
    #define GPIO_AFRL_AFSEL0_Pos   (0U)
     
    #define GPIO_AFRL_AFSEL0_Msk   (0xFUL << GPIO_AFRL_AFSEL0_Pos)
     
    #define GPIO_AFRL_AFSEL0   GPIO_AFRL_AFSEL0_Msk
     
    #define GPIO_AFRL_AFSEL0_0   (0x1UL << GPIO_AFRL_AFSEL0_Pos)
     
    #define GPIO_AFRL_AFSEL0_1   (0x2UL << GPIO_AFRL_AFSEL0_Pos)
     
    #define GPIO_AFRL_AFSEL0_2   (0x4UL << GPIO_AFRL_AFSEL0_Pos)
     
    #define GPIO_AFRL_AFSEL0_3   (0x8UL << GPIO_AFRL_AFSEL0_Pos)
     
    #define GPIO_AFRL_AFSEL1_Pos   (4U)
     
    #define GPIO_AFRL_AFSEL1_Msk   (0xFUL << GPIO_AFRL_AFSEL1_Pos)
     
    #define GPIO_AFRL_AFSEL1   GPIO_AFRL_AFSEL1_Msk
     
    #define GPIO_AFRL_AFSEL1_0   (0x1UL << GPIO_AFRL_AFSEL1_Pos)
     
    #define GPIO_AFRL_AFSEL1_1   (0x2UL << GPIO_AFRL_AFSEL1_Pos)
     
    #define GPIO_AFRL_AFSEL1_2   (0x4UL << GPIO_AFRL_AFSEL1_Pos)
     
    #define GPIO_AFRL_AFSEL1_3   (0x8UL << GPIO_AFRL_AFSEL1_Pos)
     
    #define GPIO_AFRL_AFSEL2_Pos   (8U)
     
    #define GPIO_AFRL_AFSEL2_Msk   (0xFUL << GPIO_AFRL_AFSEL2_Pos)
     
    #define GPIO_AFRL_AFSEL2   GPIO_AFRL_AFSEL2_Msk
     
    #define GPIO_AFRL_AFSEL2_0   (0x1UL << GPIO_AFRL_AFSEL2_Pos)
     
    #define GPIO_AFRL_AFSEL2_1   (0x2UL << GPIO_AFRL_AFSEL2_Pos)
     
    #define GPIO_AFRL_AFSEL2_2   (0x4UL << GPIO_AFRL_AFSEL2_Pos)
     
    #define GPIO_AFRL_AFSEL2_3   (0x8UL << GPIO_AFRL_AFSEL2_Pos)
     
    #define GPIO_AFRL_AFSEL3_Pos   (12U)
     
    #define GPIO_AFRL_AFSEL3_Msk   (0xFUL << GPIO_AFRL_AFSEL3_Pos)
     
    #define GPIO_AFRL_AFSEL3   GPIO_AFRL_AFSEL3_Msk
     
    #define GPIO_AFRL_AFSEL3_0   (0x1UL << GPIO_AFRL_AFSEL3_Pos)
     
    #define GPIO_AFRL_AFSEL3_1   (0x2UL << GPIO_AFRL_AFSEL3_Pos)
     
    #define GPIO_AFRL_AFSEL3_2   (0x4UL << GPIO_AFRL_AFSEL3_Pos)
     
    #define GPIO_AFRL_AFSEL3_3   (0x8UL << GPIO_AFRL_AFSEL3_Pos)
     
    #define GPIO_AFRL_AFSEL4_Pos   (16U)
     
    #define GPIO_AFRL_AFSEL4_Msk   (0xFUL << GPIO_AFRL_AFSEL4_Pos)
     
    #define GPIO_AFRL_AFSEL4   GPIO_AFRL_AFSEL4_Msk
     
    #define GPIO_AFRL_AFSEL4_0   (0x1UL << GPIO_AFRL_AFSEL4_Pos)
     
    #define GPIO_AFRL_AFSEL4_1   (0x2UL << GPIO_AFRL_AFSEL4_Pos)
     
    #define GPIO_AFRL_AFSEL4_2   (0x4UL << GPIO_AFRL_AFSEL4_Pos)
     
    #define GPIO_AFRL_AFSEL4_3   (0x8UL << GPIO_AFRL_AFSEL4_Pos)
     
    #define GPIO_AFRL_AFSEL5_Pos   (20U)
     
    #define GPIO_AFRL_AFSEL5_Msk   (0xFUL << GPIO_AFRL_AFSEL5_Pos)
     
    #define GPIO_AFRL_AFSEL5   GPIO_AFRL_AFSEL5_Msk
     
    #define GPIO_AFRL_AFSEL5_0   (0x1UL << GPIO_AFRL_AFSEL5_Pos)
     
    #define GPIO_AFRL_AFSEL5_1   (0x2UL << GPIO_AFRL_AFSEL5_Pos)
     
    #define GPIO_AFRL_AFSEL5_2   (0x4UL << GPIO_AFRL_AFSEL5_Pos)
     
    #define GPIO_AFRL_AFSEL5_3   (0x8UL << GPIO_AFRL_AFSEL5_Pos)
     
    #define GPIO_AFRL_AFSEL6_Pos   (24U)
     
    #define GPIO_AFRL_AFSEL6_Msk   (0xFUL << GPIO_AFRL_AFSEL6_Pos)
     
    #define GPIO_AFRL_AFSEL6   GPIO_AFRL_AFSEL6_Msk
     
    #define GPIO_AFRL_AFSEL6_0   (0x1UL << GPIO_AFRL_AFSEL6_Pos)
     
    #define GPIO_AFRL_AFSEL6_1   (0x2UL << GPIO_AFRL_AFSEL6_Pos)
     
    #define GPIO_AFRL_AFSEL6_2   (0x4UL << GPIO_AFRL_AFSEL6_Pos)
     
    #define GPIO_AFRL_AFSEL6_3   (0x8UL << GPIO_AFRL_AFSEL6_Pos)
     
    #define GPIO_AFRL_AFSEL7_Pos   (28U)
     
    #define GPIO_AFRL_AFSEL7_Msk   (0xFUL << GPIO_AFRL_AFSEL7_Pos)
     
    #define GPIO_AFRL_AFSEL7   GPIO_AFRL_AFSEL7_Msk
     
    #define GPIO_AFRL_AFSEL7_0   (0x1UL << GPIO_AFRL_AFSEL7_Pos)
     
    #define GPIO_AFRL_AFSEL7_1   (0x2UL << GPIO_AFRL_AFSEL7_Pos)
     
    #define GPIO_AFRL_AFSEL7_2   (0x4UL << GPIO_AFRL_AFSEL7_Pos)
     
    #define GPIO_AFRL_AFSEL7_3   (0x8UL << GPIO_AFRL_AFSEL7_Pos)
     
    #define GPIO_AFRL_AFRL0   GPIO_AFRL_AFSEL0
     
    #define GPIO_AFRL_AFRL0_0   GPIO_AFRL_AFSEL0_0
     
    #define GPIO_AFRL_AFRL0_1   GPIO_AFRL_AFSEL0_1
     
    #define GPIO_AFRL_AFRL0_2   GPIO_AFRL_AFSEL0_2
     
    #define GPIO_AFRL_AFRL0_3   GPIO_AFRL_AFSEL0_3
     
    #define GPIO_AFRL_AFRL1   GPIO_AFRL_AFSEL1
     
    #define GPIO_AFRL_AFRL1_0   GPIO_AFRL_AFSEL1_0
     
    #define GPIO_AFRL_AFRL1_1   GPIO_AFRL_AFSEL1_1
     
    #define GPIO_AFRL_AFRL1_2   GPIO_AFRL_AFSEL1_2
     
    #define GPIO_AFRL_AFRL1_3   GPIO_AFRL_AFSEL1_3
     
    #define GPIO_AFRL_AFRL2   GPIO_AFRL_AFSEL2
     
    #define GPIO_AFRL_AFRL2_0   GPIO_AFRL_AFSEL2_0
     
    #define GPIO_AFRL_AFRL2_1   GPIO_AFRL_AFSEL2_1
     
    #define GPIO_AFRL_AFRL2_2   GPIO_AFRL_AFSEL2_2
     
    #define GPIO_AFRL_AFRL2_3   GPIO_AFRL_AFSEL2_3
     
    #define GPIO_AFRL_AFRL3   GPIO_AFRL_AFSEL3
     
    #define GPIO_AFRL_AFRL3_0   GPIO_AFRL_AFSEL3_0
     
    #define GPIO_AFRL_AFRL3_1   GPIO_AFRL_AFSEL3_1
     
    #define GPIO_AFRL_AFRL3_2   GPIO_AFRL_AFSEL3_2
     
    #define GPIO_AFRL_AFRL3_3   GPIO_AFRL_AFSEL3_3
     
    #define GPIO_AFRL_AFRL4   GPIO_AFRL_AFSEL4
     
    #define GPIO_AFRL_AFRL4_0   GPIO_AFRL_AFSEL4_0
     
    #define GPIO_AFRL_AFRL4_1   GPIO_AFRL_AFSEL4_1
     
    #define GPIO_AFRL_AFRL4_2   GPIO_AFRL_AFSEL4_2
     
    #define GPIO_AFRL_AFRL4_3   GPIO_AFRL_AFSEL4_3
     
    #define GPIO_AFRL_AFRL5   GPIO_AFRL_AFSEL5
     
    #define GPIO_AFRL_AFRL5_0   GPIO_AFRL_AFSEL5_0
     
    #define GPIO_AFRL_AFRL5_1   GPIO_AFRL_AFSEL5_1
     
    #define GPIO_AFRL_AFRL5_2   GPIO_AFRL_AFSEL5_2
     
    #define GPIO_AFRL_AFRL5_3   GPIO_AFRL_AFSEL5_3
     
    #define GPIO_AFRL_AFRL6   GPIO_AFRL_AFSEL6
     
    #define GPIO_AFRL_AFRL6_0   GPIO_AFRL_AFSEL6_0
     
    #define GPIO_AFRL_AFRL6_1   GPIO_AFRL_AFSEL6_1
     
    #define GPIO_AFRL_AFRL6_2   GPIO_AFRL_AFSEL6_2
     
    #define GPIO_AFRL_AFRL6_3   GPIO_AFRL_AFSEL6_3
     
    #define GPIO_AFRL_AFRL7   GPIO_AFRL_AFSEL7
     
    #define GPIO_AFRL_AFRL7_0   GPIO_AFRL_AFSEL7_0
     
    #define GPIO_AFRL_AFRL7_1   GPIO_AFRL_AFSEL7_1
     
    #define GPIO_AFRL_AFRL7_2   GPIO_AFRL_AFSEL7_2
     
    #define GPIO_AFRL_AFRL7_3   GPIO_AFRL_AFSEL7_3
     
    #define GPIO_AFRH_AFSEL8_Pos   (0U)
     
    #define GPIO_AFRH_AFSEL8_Msk   (0xFUL << GPIO_AFRH_AFSEL8_Pos)
     
    #define GPIO_AFRH_AFSEL8   GPIO_AFRH_AFSEL8_Msk
     
    #define GPIO_AFRH_AFSEL8_0   (0x1UL << GPIO_AFRH_AFSEL8_Pos)
     
    #define GPIO_AFRH_AFSEL8_1   (0x2UL << GPIO_AFRH_AFSEL8_Pos)
     
    #define GPIO_AFRH_AFSEL8_2   (0x4UL << GPIO_AFRH_AFSEL8_Pos)
     
    #define GPIO_AFRH_AFSEL8_3   (0x8UL << GPIO_AFRH_AFSEL8_Pos)
     
    #define GPIO_AFRH_AFSEL9_Pos   (4U)
     
    #define GPIO_AFRH_AFSEL9_Msk   (0xFUL << GPIO_AFRH_AFSEL9_Pos)
     
    #define GPIO_AFRH_AFSEL9   GPIO_AFRH_AFSEL9_Msk
     
    #define GPIO_AFRH_AFSEL9_0   (0x1UL << GPIO_AFRH_AFSEL9_Pos)
     
    #define GPIO_AFRH_AFSEL9_1   (0x2UL << GPIO_AFRH_AFSEL9_Pos)
     
    #define GPIO_AFRH_AFSEL9_2   (0x4UL << GPIO_AFRH_AFSEL9_Pos)
     
    #define GPIO_AFRH_AFSEL9_3   (0x8UL << GPIO_AFRH_AFSEL9_Pos)
     
    #define GPIO_AFRH_AFSEL10_Pos   (8U)
     
    #define GPIO_AFRH_AFSEL10_Msk   (0xFUL << GPIO_AFRH_AFSEL10_Pos)
     
    #define GPIO_AFRH_AFSEL10   GPIO_AFRH_AFSEL10_Msk
     
    #define GPIO_AFRH_AFSEL10_0   (0x1UL << GPIO_AFRH_AFSEL10_Pos)
     
    #define GPIO_AFRH_AFSEL10_1   (0x2UL << GPIO_AFRH_AFSEL10_Pos)
     
    #define GPIO_AFRH_AFSEL10_2   (0x4UL << GPIO_AFRH_AFSEL10_Pos)
     
    #define GPIO_AFRH_AFSEL10_3   (0x8UL << GPIO_AFRH_AFSEL10_Pos)
     
    #define GPIO_AFRH_AFSEL11_Pos   (12U)
     
    #define GPIO_AFRH_AFSEL11_Msk   (0xFUL << GPIO_AFRH_AFSEL11_Pos)
     
    #define GPIO_AFRH_AFSEL11   GPIO_AFRH_AFSEL11_Msk
     
    #define GPIO_AFRH_AFSEL11_0   (0x1UL << GPIO_AFRH_AFSEL11_Pos)
     
    #define GPIO_AFRH_AFSEL11_1   (0x2UL << GPIO_AFRH_AFSEL11_Pos)
     
    #define GPIO_AFRH_AFSEL11_2   (0x4UL << GPIO_AFRH_AFSEL11_Pos)
     
    #define GPIO_AFRH_AFSEL11_3   (0x8UL << GPIO_AFRH_AFSEL11_Pos)
     
    #define GPIO_AFRH_AFSEL12_Pos   (16U)
     
    #define GPIO_AFRH_AFSEL12_Msk   (0xFUL << GPIO_AFRH_AFSEL12_Pos)
     
    #define GPIO_AFRH_AFSEL12   GPIO_AFRH_AFSEL12_Msk
     
    #define GPIO_AFRH_AFSEL12_0   (0x1UL << GPIO_AFRH_AFSEL12_Pos)
     
    #define GPIO_AFRH_AFSEL12_1   (0x2UL << GPIO_AFRH_AFSEL12_Pos)
     
    #define GPIO_AFRH_AFSEL12_2   (0x4UL << GPIO_AFRH_AFSEL12_Pos)
     
    #define GPIO_AFRH_AFSEL12_3   (0x8UL << GPIO_AFRH_AFSEL12_Pos)
     
    #define GPIO_AFRH_AFSEL13_Pos   (20U)
     
    #define GPIO_AFRH_AFSEL13_Msk   (0xFUL << GPIO_AFRH_AFSEL13_Pos)
     
    #define GPIO_AFRH_AFSEL13   GPIO_AFRH_AFSEL13_Msk
     
    #define GPIO_AFRH_AFSEL13_0   (0x1UL << GPIO_AFRH_AFSEL13_Pos)
     
    #define GPIO_AFRH_AFSEL13_1   (0x2UL << GPIO_AFRH_AFSEL13_Pos)
     
    #define GPIO_AFRH_AFSEL13_2   (0x4UL << GPIO_AFRH_AFSEL13_Pos)
     
    #define GPIO_AFRH_AFSEL13_3   (0x8UL << GPIO_AFRH_AFSEL13_Pos)
     
    #define GPIO_AFRH_AFSEL14_Pos   (24U)
     
    #define GPIO_AFRH_AFSEL14_Msk   (0xFUL << GPIO_AFRH_AFSEL14_Pos)
     
    #define GPIO_AFRH_AFSEL14   GPIO_AFRH_AFSEL14_Msk
     
    #define GPIO_AFRH_AFSEL14_0   (0x1UL << GPIO_AFRH_AFSEL14_Pos)
     
    #define GPIO_AFRH_AFSEL14_1   (0x2UL << GPIO_AFRH_AFSEL14_Pos)
     
    #define GPIO_AFRH_AFSEL14_2   (0x4UL << GPIO_AFRH_AFSEL14_Pos)
     
    #define GPIO_AFRH_AFSEL14_3   (0x8UL << GPIO_AFRH_AFSEL14_Pos)
     
    #define GPIO_AFRH_AFSEL15_Pos   (28U)
     
    #define GPIO_AFRH_AFSEL15_Msk   (0xFUL << GPIO_AFRH_AFSEL15_Pos)
     
    #define GPIO_AFRH_AFSEL15   GPIO_AFRH_AFSEL15_Msk
     
    #define GPIO_AFRH_AFSEL15_0   (0x1UL << GPIO_AFRH_AFSEL15_Pos)
     
    #define GPIO_AFRH_AFSEL15_1   (0x2UL << GPIO_AFRH_AFSEL15_Pos)
     
    #define GPIO_AFRH_AFSEL15_2   (0x4UL << GPIO_AFRH_AFSEL15_Pos)
     
    #define GPIO_AFRH_AFSEL15_3   (0x8UL << GPIO_AFRH_AFSEL15_Pos)
     
    #define GPIO_AFRH_AFRH0   GPIO_AFRH_AFSEL8
     
    #define GPIO_AFRH_AFRH0_0   GPIO_AFRH_AFSEL8_0
     
    #define GPIO_AFRH_AFRH0_1   GPIO_AFRH_AFSEL8_1
     
    #define GPIO_AFRH_AFRH0_2   GPIO_AFRH_AFSEL8_2
     
    #define GPIO_AFRH_AFRH0_3   GPIO_AFRH_AFSEL8_3
     
    #define GPIO_AFRH_AFRH1   GPIO_AFRH_AFSEL9
     
    #define GPIO_AFRH_AFRH1_0   GPIO_AFRH_AFSEL9_0
     
    #define GPIO_AFRH_AFRH1_1   GPIO_AFRH_AFSEL9_1
     
    #define GPIO_AFRH_AFRH1_2   GPIO_AFRH_AFSEL9_2
     
    #define GPIO_AFRH_AFRH1_3   GPIO_AFRH_AFSEL9_3
     
    #define GPIO_AFRH_AFRH2   GPIO_AFRH_AFSEL10
     
    #define GPIO_AFRH_AFRH2_0   GPIO_AFRH_AFSEL10_0
     
    #define GPIO_AFRH_AFRH2_1   GPIO_AFRH_AFSEL10_1
     
    #define GPIO_AFRH_AFRH2_2   GPIO_AFRH_AFSEL10_2
     
    #define GPIO_AFRH_AFRH2_3   GPIO_AFRH_AFSEL10_3
     
    #define GPIO_AFRH_AFRH3   GPIO_AFRH_AFSEL11
     
    #define GPIO_AFRH_AFRH3_0   GPIO_AFRH_AFSEL11_0
     
    #define GPIO_AFRH_AFRH3_1   GPIO_AFRH_AFSEL11_1
     
    #define GPIO_AFRH_AFRH3_2   GPIO_AFRH_AFSEL11_2
     
    #define GPIO_AFRH_AFRH3_3   GPIO_AFRH_AFSEL11_3
     
    #define GPIO_AFRH_AFRH4   GPIO_AFRH_AFSEL12
     
    #define GPIO_AFRH_AFRH4_0   GPIO_AFRH_AFSEL12_0
     
    #define GPIO_AFRH_AFRH4_1   GPIO_AFRH_AFSEL12_1
     
    #define GPIO_AFRH_AFRH4_2   GPIO_AFRH_AFSEL12_2
     
    #define GPIO_AFRH_AFRH4_3   GPIO_AFRH_AFSEL12_3
     
    #define GPIO_AFRH_AFRH5   GPIO_AFRH_AFSEL13
     
    #define GPIO_AFRH_AFRH5_0   GPIO_AFRH_AFSEL13_0
     
    #define GPIO_AFRH_AFRH5_1   GPIO_AFRH_AFSEL13_1
     
    #define GPIO_AFRH_AFRH5_2   GPIO_AFRH_AFSEL13_2
     
    #define GPIO_AFRH_AFRH5_3   GPIO_AFRH_AFSEL13_3
     
    #define GPIO_AFRH_AFRH6   GPIO_AFRH_AFSEL14
     
    #define GPIO_AFRH_AFRH6_0   GPIO_AFRH_AFSEL14_0
     
    #define GPIO_AFRH_AFRH6_1   GPIO_AFRH_AFSEL14_1
     
    #define GPIO_AFRH_AFRH6_2   GPIO_AFRH_AFSEL14_2
     
    #define GPIO_AFRH_AFRH6_3   GPIO_AFRH_AFSEL14_3
     
    #define GPIO_AFRH_AFRH7   GPIO_AFRH_AFSEL15
     
    #define GPIO_AFRH_AFRH7_0   GPIO_AFRH_AFSEL15_0
     
    #define GPIO_AFRH_AFRH7_1   GPIO_AFRH_AFSEL15_1
     
    #define GPIO_AFRH_AFRH7_2   GPIO_AFRH_AFSEL15_2
     
    #define GPIO_AFRH_AFRH7_3   GPIO_AFRH_AFSEL15_3
     
    #define I2C_CR1_PE_Pos   (0U)
     
    #define I2C_CR1_PE_Msk   (0x1UL << I2C_CR1_PE_Pos)
     
    #define I2C_CR1_PE   I2C_CR1_PE_Msk
     
    #define I2C_CR1_SMBUS_Pos   (1U)
     
    #define I2C_CR1_SMBUS_Msk   (0x1UL << I2C_CR1_SMBUS_Pos)
     
    #define I2C_CR1_SMBUS   I2C_CR1_SMBUS_Msk
     
    #define I2C_CR1_SMBTYPE_Pos   (3U)
     
    #define I2C_CR1_SMBTYPE_Msk   (0x1UL << I2C_CR1_SMBTYPE_Pos)
     
    #define I2C_CR1_SMBTYPE   I2C_CR1_SMBTYPE_Msk
     
    #define I2C_CR1_ENARP_Pos   (4U)
     
    #define I2C_CR1_ENARP_Msk   (0x1UL << I2C_CR1_ENARP_Pos)
     
    #define I2C_CR1_ENARP   I2C_CR1_ENARP_Msk
     
    #define I2C_CR1_ENPEC_Pos   (5U)
     
    #define I2C_CR1_ENPEC_Msk   (0x1UL << I2C_CR1_ENPEC_Pos)
     
    #define I2C_CR1_ENPEC   I2C_CR1_ENPEC_Msk
     
    #define I2C_CR1_ENGC_Pos   (6U)
     
    #define I2C_CR1_ENGC_Msk   (0x1UL << I2C_CR1_ENGC_Pos)
     
    #define I2C_CR1_ENGC   I2C_CR1_ENGC_Msk
     
    #define I2C_CR1_NOSTRETCH_Pos   (7U)
     
    #define I2C_CR1_NOSTRETCH_Msk   (0x1UL << I2C_CR1_NOSTRETCH_Pos)
     
    #define I2C_CR1_NOSTRETCH   I2C_CR1_NOSTRETCH_Msk
     
    #define I2C_CR1_START_Pos   (8U)
     
    #define I2C_CR1_START_Msk   (0x1UL << I2C_CR1_START_Pos)
     
    #define I2C_CR1_START   I2C_CR1_START_Msk
     
    #define I2C_CR1_STOP_Pos   (9U)
     
    #define I2C_CR1_STOP_Msk   (0x1UL << I2C_CR1_STOP_Pos)
     
    #define I2C_CR1_STOP   I2C_CR1_STOP_Msk
     
    #define I2C_CR1_ACK_Pos   (10U)
     
    #define I2C_CR1_ACK_Msk   (0x1UL << I2C_CR1_ACK_Pos)
     
    #define I2C_CR1_ACK   I2C_CR1_ACK_Msk
     
    #define I2C_CR1_POS_Pos   (11U)
     
    #define I2C_CR1_POS_Msk   (0x1UL << I2C_CR1_POS_Pos)
     
    #define I2C_CR1_POS   I2C_CR1_POS_Msk
     
    #define I2C_CR1_PEC_Pos   (12U)
     
    #define I2C_CR1_PEC_Msk   (0x1UL << I2C_CR1_PEC_Pos)
     
    #define I2C_CR1_PEC   I2C_CR1_PEC_Msk
     
    #define I2C_CR1_ALERT_Pos   (13U)
     
    #define I2C_CR1_ALERT_Msk   (0x1UL << I2C_CR1_ALERT_Pos)
     
    #define I2C_CR1_ALERT   I2C_CR1_ALERT_Msk
     
    #define I2C_CR1_SWRST_Pos   (15U)
     
    #define I2C_CR1_SWRST_Msk   (0x1UL << I2C_CR1_SWRST_Pos)
     
    #define I2C_CR1_SWRST   I2C_CR1_SWRST_Msk
     
    #define I2C_CR2_FREQ_Pos   (0U)
     
    #define I2C_CR2_FREQ_Msk   (0x3FUL << I2C_CR2_FREQ_Pos)
     
    #define I2C_CR2_FREQ   I2C_CR2_FREQ_Msk
     
    #define I2C_CR2_FREQ_0   (0x01UL << I2C_CR2_FREQ_Pos)
     
    #define I2C_CR2_FREQ_1   (0x02UL << I2C_CR2_FREQ_Pos)
     
    #define I2C_CR2_FREQ_2   (0x04UL << I2C_CR2_FREQ_Pos)
     
    #define I2C_CR2_FREQ_3   (0x08UL << I2C_CR2_FREQ_Pos)
     
    #define I2C_CR2_FREQ_4   (0x10UL << I2C_CR2_FREQ_Pos)
     
    #define I2C_CR2_FREQ_5   (0x20UL << I2C_CR2_FREQ_Pos)
     
    #define I2C_CR2_ITERREN_Pos   (8U)
     
    #define I2C_CR2_ITERREN_Msk   (0x1UL << I2C_CR2_ITERREN_Pos)
     
    #define I2C_CR2_ITERREN   I2C_CR2_ITERREN_Msk
     
    #define I2C_CR2_ITEVTEN_Pos   (9U)
     
    #define I2C_CR2_ITEVTEN_Msk   (0x1UL << I2C_CR2_ITEVTEN_Pos)
     
    #define I2C_CR2_ITEVTEN   I2C_CR2_ITEVTEN_Msk
     
    #define I2C_CR2_ITBUFEN_Pos   (10U)
     
    #define I2C_CR2_ITBUFEN_Msk   (0x1UL << I2C_CR2_ITBUFEN_Pos)
     
    #define I2C_CR2_ITBUFEN   I2C_CR2_ITBUFEN_Msk
     
    #define I2C_CR2_DMAEN_Pos   (11U)
     
    #define I2C_CR2_DMAEN_Msk   (0x1UL << I2C_CR2_DMAEN_Pos)
     
    #define I2C_CR2_DMAEN   I2C_CR2_DMAEN_Msk
     
    #define I2C_CR2_LAST_Pos   (12U)
     
    #define I2C_CR2_LAST_Msk   (0x1UL << I2C_CR2_LAST_Pos)
     
    #define I2C_CR2_LAST   I2C_CR2_LAST_Msk
     
    #define I2C_OAR1_ADD1_7   0x000000FEU
     
    #define I2C_OAR1_ADD8_9   0x00000300U
     
    #define I2C_OAR1_ADD0_Pos   (0U)
     
    #define I2C_OAR1_ADD0_Msk   (0x1UL << I2C_OAR1_ADD0_Pos)
     
    #define I2C_OAR1_ADD0   I2C_OAR1_ADD0_Msk
     
    #define I2C_OAR1_ADD1_Pos   (1U)
     
    #define I2C_OAR1_ADD1_Msk   (0x1UL << I2C_OAR1_ADD1_Pos)
     
    #define I2C_OAR1_ADD1   I2C_OAR1_ADD1_Msk
     
    #define I2C_OAR1_ADD2_Pos   (2U)
     
    #define I2C_OAR1_ADD2_Msk   (0x1UL << I2C_OAR1_ADD2_Pos)
     
    #define I2C_OAR1_ADD2   I2C_OAR1_ADD2_Msk
     
    #define I2C_OAR1_ADD3_Pos   (3U)
     
    #define I2C_OAR1_ADD3_Msk   (0x1UL << I2C_OAR1_ADD3_Pos)
     
    #define I2C_OAR1_ADD3   I2C_OAR1_ADD3_Msk
     
    #define I2C_OAR1_ADD4_Pos   (4U)
     
    #define I2C_OAR1_ADD4_Msk   (0x1UL << I2C_OAR1_ADD4_Pos)
     
    #define I2C_OAR1_ADD4   I2C_OAR1_ADD4_Msk
     
    #define I2C_OAR1_ADD5_Pos   (5U)
     
    #define I2C_OAR1_ADD5_Msk   (0x1UL << I2C_OAR1_ADD5_Pos)
     
    #define I2C_OAR1_ADD5   I2C_OAR1_ADD5_Msk
     
    #define I2C_OAR1_ADD6_Pos   (6U)
     
    #define I2C_OAR1_ADD6_Msk   (0x1UL << I2C_OAR1_ADD6_Pos)
     
    #define I2C_OAR1_ADD6   I2C_OAR1_ADD6_Msk
     
    #define I2C_OAR1_ADD7_Pos   (7U)
     
    #define I2C_OAR1_ADD7_Msk   (0x1UL << I2C_OAR1_ADD7_Pos)
     
    #define I2C_OAR1_ADD7   I2C_OAR1_ADD7_Msk
     
    #define I2C_OAR1_ADD8_Pos   (8U)
     
    #define I2C_OAR1_ADD8_Msk   (0x1UL << I2C_OAR1_ADD8_Pos)
     
    #define I2C_OAR1_ADD8   I2C_OAR1_ADD8_Msk
     
    #define I2C_OAR1_ADD9_Pos   (9U)
     
    #define I2C_OAR1_ADD9_Msk   (0x1UL << I2C_OAR1_ADD9_Pos)
     
    #define I2C_OAR1_ADD9   I2C_OAR1_ADD9_Msk
     
    #define I2C_OAR1_ADDMODE_Pos   (15U)
     
    #define I2C_OAR1_ADDMODE_Msk   (0x1UL << I2C_OAR1_ADDMODE_Pos)
     
    #define I2C_OAR1_ADDMODE   I2C_OAR1_ADDMODE_Msk
     
    #define I2C_OAR2_ENDUAL_Pos   (0U)
     
    #define I2C_OAR2_ENDUAL_Msk   (0x1UL << I2C_OAR2_ENDUAL_Pos)
     
    #define I2C_OAR2_ENDUAL   I2C_OAR2_ENDUAL_Msk
     
    #define I2C_OAR2_ADD2_Pos   (1U)
     
    #define I2C_OAR2_ADD2_Msk   (0x7FUL << I2C_OAR2_ADD2_Pos)
     
    #define I2C_OAR2_ADD2   I2C_OAR2_ADD2_Msk
     
    #define I2C_DR_DR_Pos   (0U)
     
    #define I2C_DR_DR_Msk   (0xFFUL << I2C_DR_DR_Pos)
     
    #define I2C_DR_DR   I2C_DR_DR_Msk
     
    #define I2C_SR1_SB_Pos   (0U)
     
    #define I2C_SR1_SB_Msk   (0x1UL << I2C_SR1_SB_Pos)
     
    #define I2C_SR1_SB   I2C_SR1_SB_Msk
     
    #define I2C_SR1_ADDR_Pos   (1U)
     
    #define I2C_SR1_ADDR_Msk   (0x1UL << I2C_SR1_ADDR_Pos)
     
    #define I2C_SR1_ADDR   I2C_SR1_ADDR_Msk
     
    #define I2C_SR1_BTF_Pos   (2U)
     
    #define I2C_SR1_BTF_Msk   (0x1UL << I2C_SR1_BTF_Pos)
     
    #define I2C_SR1_BTF   I2C_SR1_BTF_Msk
     
    #define I2C_SR1_ADD10_Pos   (3U)
     
    #define I2C_SR1_ADD10_Msk   (0x1UL << I2C_SR1_ADD10_Pos)
     
    #define I2C_SR1_ADD10   I2C_SR1_ADD10_Msk
     
    #define I2C_SR1_STOPF_Pos   (4U)
     
    #define I2C_SR1_STOPF_Msk   (0x1UL << I2C_SR1_STOPF_Pos)
     
    #define I2C_SR1_STOPF   I2C_SR1_STOPF_Msk
     
    #define I2C_SR1_RXNE_Pos   (6U)
     
    #define I2C_SR1_RXNE_Msk   (0x1UL << I2C_SR1_RXNE_Pos)
     
    #define I2C_SR1_RXNE   I2C_SR1_RXNE_Msk
     
    #define I2C_SR1_TXE_Pos   (7U)
     
    #define I2C_SR1_TXE_Msk   (0x1UL << I2C_SR1_TXE_Pos)
     
    #define I2C_SR1_TXE   I2C_SR1_TXE_Msk
     
    #define I2C_SR1_BERR_Pos   (8U)
     
    #define I2C_SR1_BERR_Msk   (0x1UL << I2C_SR1_BERR_Pos)
     
    #define I2C_SR1_BERR   I2C_SR1_BERR_Msk
     
    #define I2C_SR1_ARLO_Pos   (9U)
     
    #define I2C_SR1_ARLO_Msk   (0x1UL << I2C_SR1_ARLO_Pos)
     
    #define I2C_SR1_ARLO   I2C_SR1_ARLO_Msk
     
    #define I2C_SR1_AF_Pos   (10U)
     
    #define I2C_SR1_AF_Msk   (0x1UL << I2C_SR1_AF_Pos)
     
    #define I2C_SR1_AF   I2C_SR1_AF_Msk
     
    #define I2C_SR1_OVR_Pos   (11U)
     
    #define I2C_SR1_OVR_Msk   (0x1UL << I2C_SR1_OVR_Pos)
     
    #define I2C_SR1_OVR   I2C_SR1_OVR_Msk
     
    #define I2C_SR1_PECERR_Pos   (12U)
     
    #define I2C_SR1_PECERR_Msk   (0x1UL << I2C_SR1_PECERR_Pos)
     
    #define I2C_SR1_PECERR   I2C_SR1_PECERR_Msk
     
    #define I2C_SR1_TIMEOUT_Pos   (14U)
     
    #define I2C_SR1_TIMEOUT_Msk   (0x1UL << I2C_SR1_TIMEOUT_Pos)
     
    #define I2C_SR1_TIMEOUT   I2C_SR1_TIMEOUT_Msk
     
    #define I2C_SR1_SMBALERT_Pos   (15U)
     
    #define I2C_SR1_SMBALERT_Msk   (0x1UL << I2C_SR1_SMBALERT_Pos)
     
    #define I2C_SR1_SMBALERT   I2C_SR1_SMBALERT_Msk
     
    #define I2C_SR2_MSL_Pos   (0U)
     
    #define I2C_SR2_MSL_Msk   (0x1UL << I2C_SR2_MSL_Pos)
     
    #define I2C_SR2_MSL   I2C_SR2_MSL_Msk
     
    #define I2C_SR2_BUSY_Pos   (1U)
     
    #define I2C_SR2_BUSY_Msk   (0x1UL << I2C_SR2_BUSY_Pos)
     
    #define I2C_SR2_BUSY   I2C_SR2_BUSY_Msk
     
    #define I2C_SR2_TRA_Pos   (2U)
     
    #define I2C_SR2_TRA_Msk   (0x1UL << I2C_SR2_TRA_Pos)
     
    #define I2C_SR2_TRA   I2C_SR2_TRA_Msk
     
    #define I2C_SR2_GENCALL_Pos   (4U)
     
    #define I2C_SR2_GENCALL_Msk   (0x1UL << I2C_SR2_GENCALL_Pos)
     
    #define I2C_SR2_GENCALL   I2C_SR2_GENCALL_Msk
     
    #define I2C_SR2_SMBDEFAULT_Pos   (5U)
     
    #define I2C_SR2_SMBDEFAULT_Msk   (0x1UL << I2C_SR2_SMBDEFAULT_Pos)
     
    #define I2C_SR2_SMBDEFAULT   I2C_SR2_SMBDEFAULT_Msk
     
    #define I2C_SR2_SMBHOST_Pos   (6U)
     
    #define I2C_SR2_SMBHOST_Msk   (0x1UL << I2C_SR2_SMBHOST_Pos)
     
    #define I2C_SR2_SMBHOST   I2C_SR2_SMBHOST_Msk
     
    #define I2C_SR2_DUALF_Pos   (7U)
     
    #define I2C_SR2_DUALF_Msk   (0x1UL << I2C_SR2_DUALF_Pos)
     
    #define I2C_SR2_DUALF   I2C_SR2_DUALF_Msk
     
    #define I2C_SR2_PEC_Pos   (8U)
     
    #define I2C_SR2_PEC_Msk   (0xFFUL << I2C_SR2_PEC_Pos)
     
    #define I2C_SR2_PEC   I2C_SR2_PEC_Msk
     
    #define I2C_CCR_CCR_Pos   (0U)
     
    #define I2C_CCR_CCR_Msk   (0xFFFUL << I2C_CCR_CCR_Pos)
     
    #define I2C_CCR_CCR   I2C_CCR_CCR_Msk
     
    #define I2C_CCR_DUTY_Pos   (14U)
     
    #define I2C_CCR_DUTY_Msk   (0x1UL << I2C_CCR_DUTY_Pos)
     
    #define I2C_CCR_DUTY   I2C_CCR_DUTY_Msk
     
    #define I2C_CCR_FS_Pos   (15U)
     
    #define I2C_CCR_FS_Msk   (0x1UL << I2C_CCR_FS_Pos)
     
    #define I2C_CCR_FS   I2C_CCR_FS_Msk
     
    #define I2C_TRISE_TRISE_Pos   (0U)
     
    #define I2C_TRISE_TRISE_Msk   (0x3FUL << I2C_TRISE_TRISE_Pos)
     
    #define I2C_TRISE_TRISE   I2C_TRISE_TRISE_Msk
     
    #define IWDG_KR_KEY_Pos   (0U)
     
    #define IWDG_KR_KEY_Msk   (0xFFFFUL << IWDG_KR_KEY_Pos)
     
    #define IWDG_KR_KEY   IWDG_KR_KEY_Msk
     
    #define IWDG_PR_PR_Pos   (0U)
     
    #define IWDG_PR_PR_Msk   (0x7UL << IWDG_PR_PR_Pos)
     
    #define IWDG_PR_PR   IWDG_PR_PR_Msk
     
    #define IWDG_PR_PR_0   (0x1UL << IWDG_PR_PR_Pos)
     
    #define IWDG_PR_PR_1   (0x2UL << IWDG_PR_PR_Pos)
     
    #define IWDG_PR_PR_2   (0x4UL << IWDG_PR_PR_Pos)
     
    #define IWDG_RLR_RL_Pos   (0U)
     
    #define IWDG_RLR_RL_Msk   (0xFFFUL << IWDG_RLR_RL_Pos)
     
    #define IWDG_RLR_RL   IWDG_RLR_RL_Msk
     
    #define IWDG_SR_PVU_Pos   (0U)
     
    #define IWDG_SR_PVU_Msk   (0x1UL << IWDG_SR_PVU_Pos)
     
    #define IWDG_SR_PVU   IWDG_SR_PVU_Msk
     
    #define IWDG_SR_RVU_Pos   (1U)
     
    #define IWDG_SR_RVU_Msk   (0x1UL << IWDG_SR_RVU_Pos)
     
    #define IWDG_SR_RVU   IWDG_SR_RVU_Msk
     
    #define PWR_CR_LPDS_Pos   (0U)
     
    #define PWR_CR_LPDS_Msk   (0x1UL << PWR_CR_LPDS_Pos)
     
    #define PWR_CR_LPDS   PWR_CR_LPDS_Msk
     
    #define PWR_CR_PDDS_Pos   (1U)
     
    #define PWR_CR_PDDS_Msk   (0x1UL << PWR_CR_PDDS_Pos)
     
    #define PWR_CR_PDDS   PWR_CR_PDDS_Msk
     
    #define PWR_CR_CWUF_Pos   (2U)
     
    #define PWR_CR_CWUF_Msk   (0x1UL << PWR_CR_CWUF_Pos)
     
    #define PWR_CR_CWUF   PWR_CR_CWUF_Msk
     
    #define PWR_CR_CSBF_Pos   (3U)
     
    #define PWR_CR_CSBF_Msk   (0x1UL << PWR_CR_CSBF_Pos)
     
    #define PWR_CR_CSBF   PWR_CR_CSBF_Msk
     
    #define PWR_CR_PVDE_Pos   (4U)
     
    #define PWR_CR_PVDE_Msk   (0x1UL << PWR_CR_PVDE_Pos)
     
    #define PWR_CR_PVDE   PWR_CR_PVDE_Msk
     
    #define PWR_CR_PLS_Pos   (5U)
     
    #define PWR_CR_PLS_Msk   (0x7UL << PWR_CR_PLS_Pos)
     
    #define PWR_CR_PLS   PWR_CR_PLS_Msk
     
    #define PWR_CR_PLS_0   (0x1UL << PWR_CR_PLS_Pos)
     
    #define PWR_CR_PLS_1   (0x2UL << PWR_CR_PLS_Pos)
     
    #define PWR_CR_PLS_2   (0x4UL << PWR_CR_PLS_Pos)
     
    #define PWR_CR_PLS_LEV0   0x00000000U
     
    #define PWR_CR_PLS_LEV1   0x00000020U
     
    #define PWR_CR_PLS_LEV2   0x00000040U
     
    #define PWR_CR_PLS_LEV3   0x00000060U
     
    #define PWR_CR_PLS_LEV4   0x00000080U
     
    #define PWR_CR_PLS_LEV5   0x000000A0U
     
    #define PWR_CR_PLS_LEV6   0x000000C0U
     
    #define PWR_CR_PLS_LEV7   0x000000E0U
     
    #define PWR_CR_DBP_Pos   (8U)
     
    #define PWR_CR_DBP_Msk   (0x1UL << PWR_CR_DBP_Pos)
     
    #define PWR_CR_DBP   PWR_CR_DBP_Msk
     
    #define PWR_CR_FPDS_Pos   (9U)
     
    #define PWR_CR_FPDS_Msk   (0x1UL << PWR_CR_FPDS_Pos)
     
    #define PWR_CR_FPDS   PWR_CR_FPDS_Msk
     
    #define PWR_CR_VOS_Pos   (14U)
     
    #define PWR_CR_VOS_Msk   (0x1UL << PWR_CR_VOS_Pos)
     
    #define PWR_CR_VOS   PWR_CR_VOS_Msk
     
    #define PWR_CR_PMODE   PWR_CR_VOS
     
    #define PWR_CSR_WUF_Pos   (0U)
     
    #define PWR_CSR_WUF_Msk   (0x1UL << PWR_CSR_WUF_Pos)
     
    #define PWR_CSR_WUF   PWR_CSR_WUF_Msk
     
    #define PWR_CSR_SBF_Pos   (1U)
     
    #define PWR_CSR_SBF_Msk   (0x1UL << PWR_CSR_SBF_Pos)
     
    #define PWR_CSR_SBF   PWR_CSR_SBF_Msk
     
    #define PWR_CSR_PVDO_Pos   (2U)
     
    #define PWR_CSR_PVDO_Msk   (0x1UL << PWR_CSR_PVDO_Pos)
     
    #define PWR_CSR_PVDO   PWR_CSR_PVDO_Msk
     
    #define PWR_CSR_BRR_Pos   (3U)
     
    #define PWR_CSR_BRR_Msk   (0x1UL << PWR_CSR_BRR_Pos)
     
    #define PWR_CSR_BRR   PWR_CSR_BRR_Msk
     
    #define PWR_CSR_EWUP_Pos   (8U)
     
    #define PWR_CSR_EWUP_Msk   (0x1UL << PWR_CSR_EWUP_Pos)
     
    #define PWR_CSR_EWUP   PWR_CSR_EWUP_Msk
     
    #define PWR_CSR_BRE_Pos   (9U)
     
    #define PWR_CSR_BRE_Msk   (0x1UL << PWR_CSR_BRE_Pos)
     
    #define PWR_CSR_BRE   PWR_CSR_BRE_Msk
     
    #define PWR_CSR_VOSRDY_Pos   (14U)
     
    #define PWR_CSR_VOSRDY_Msk   (0x1UL << PWR_CSR_VOSRDY_Pos)
     
    #define PWR_CSR_VOSRDY   PWR_CSR_VOSRDY_Msk
     
    #define PWR_CSR_REGRDY   PWR_CSR_VOSRDY
     
    #define RCC_CR_HSION_Pos   (0U)
     
    #define RCC_CR_HSION_Msk   (0x1UL << RCC_CR_HSION_Pos)
     
    #define RCC_CR_HSION   RCC_CR_HSION_Msk
     
    #define RCC_CR_HSIRDY_Pos   (1U)
     
    #define RCC_CR_HSIRDY_Msk   (0x1UL << RCC_CR_HSIRDY_Pos)
     
    #define RCC_CR_HSIRDY   RCC_CR_HSIRDY_Msk
     
    #define RCC_CR_HSITRIM_Pos   (3U)
     
    #define RCC_CR_HSITRIM_Msk   (0x1FUL << RCC_CR_HSITRIM_Pos)
     
    #define RCC_CR_HSITRIM   RCC_CR_HSITRIM_Msk
     
    #define RCC_CR_HSITRIM_0   (0x01UL << RCC_CR_HSITRIM_Pos)
     
    #define RCC_CR_HSITRIM_1   (0x02UL << RCC_CR_HSITRIM_Pos)
     
    #define RCC_CR_HSITRIM_2   (0x04UL << RCC_CR_HSITRIM_Pos)
     
    #define RCC_CR_HSITRIM_3   (0x08UL << RCC_CR_HSITRIM_Pos)
     
    #define RCC_CR_HSITRIM_4   (0x10UL << RCC_CR_HSITRIM_Pos)
     
    #define RCC_CR_HSICAL_Pos   (8U)
     
    #define RCC_CR_HSICAL_Msk   (0xFFUL << RCC_CR_HSICAL_Pos)
     
    #define RCC_CR_HSICAL   RCC_CR_HSICAL_Msk
     
    #define RCC_CR_HSICAL_0   (0x01UL << RCC_CR_HSICAL_Pos)
     
    #define RCC_CR_HSICAL_1   (0x02UL << RCC_CR_HSICAL_Pos)
     
    #define RCC_CR_HSICAL_2   (0x04UL << RCC_CR_HSICAL_Pos)
     
    #define RCC_CR_HSICAL_3   (0x08UL << RCC_CR_HSICAL_Pos)
     
    #define RCC_CR_HSICAL_4   (0x10UL << RCC_CR_HSICAL_Pos)
     
    #define RCC_CR_HSICAL_5   (0x20UL << RCC_CR_HSICAL_Pos)
     
    #define RCC_CR_HSICAL_6   (0x40UL << RCC_CR_HSICAL_Pos)
     
    #define RCC_CR_HSICAL_7   (0x80UL << RCC_CR_HSICAL_Pos)
     
    #define RCC_CR_HSEON_Pos   (16U)
     
    #define RCC_CR_HSEON_Msk   (0x1UL << RCC_CR_HSEON_Pos)
     
    #define RCC_CR_HSEON   RCC_CR_HSEON_Msk
     
    #define RCC_CR_HSERDY_Pos   (17U)
     
    #define RCC_CR_HSERDY_Msk   (0x1UL << RCC_CR_HSERDY_Pos)
     
    #define RCC_CR_HSERDY   RCC_CR_HSERDY_Msk
     
    #define RCC_CR_HSEBYP_Pos   (18U)
     
    #define RCC_CR_HSEBYP_Msk   (0x1UL << RCC_CR_HSEBYP_Pos)
     
    #define RCC_CR_HSEBYP   RCC_CR_HSEBYP_Msk
     
    #define RCC_CR_CSSON_Pos   (19U)
     
    #define RCC_CR_CSSON_Msk   (0x1UL << RCC_CR_CSSON_Pos)
     
    #define RCC_CR_CSSON   RCC_CR_CSSON_Msk
     
    #define RCC_CR_PLLON_Pos   (24U)
     
    #define RCC_CR_PLLON_Msk   (0x1UL << RCC_CR_PLLON_Pos)
     
    #define RCC_CR_PLLON   RCC_CR_PLLON_Msk
     
    #define RCC_CR_PLLRDY_Pos   (25U)
     
    #define RCC_CR_PLLRDY_Msk   (0x1UL << RCC_CR_PLLRDY_Pos)
     
    #define RCC_CR_PLLRDY   RCC_CR_PLLRDY_Msk
     
    #define RCC_PLLI2S_SUPPORT
     
    #define RCC_CR_PLLI2SON_Pos   (26U)
     
    #define RCC_CR_PLLI2SON_Msk   (0x1UL << RCC_CR_PLLI2SON_Pos)
     
    #define RCC_CR_PLLI2SON   RCC_CR_PLLI2SON_Msk
     
    #define RCC_CR_PLLI2SRDY_Pos   (27U)
     
    #define RCC_CR_PLLI2SRDY_Msk   (0x1UL << RCC_CR_PLLI2SRDY_Pos)
     
    #define RCC_CR_PLLI2SRDY   RCC_CR_PLLI2SRDY_Msk
     
    #define RCC_PLLCFGR_PLLM_Pos   (0U)
     
    #define RCC_PLLCFGR_PLLM_Msk   (0x3FUL << RCC_PLLCFGR_PLLM_Pos)
     
    #define RCC_PLLCFGR_PLLM   RCC_PLLCFGR_PLLM_Msk
     
    #define RCC_PLLCFGR_PLLM_0   (0x01UL << RCC_PLLCFGR_PLLM_Pos)
     
    #define RCC_PLLCFGR_PLLM_1   (0x02UL << RCC_PLLCFGR_PLLM_Pos)
     
    #define RCC_PLLCFGR_PLLM_2   (0x04UL << RCC_PLLCFGR_PLLM_Pos)
     
    #define RCC_PLLCFGR_PLLM_3   (0x08UL << RCC_PLLCFGR_PLLM_Pos)
     
    #define RCC_PLLCFGR_PLLM_4   (0x10UL << RCC_PLLCFGR_PLLM_Pos)
     
    #define RCC_PLLCFGR_PLLM_5   (0x20UL << RCC_PLLCFGR_PLLM_Pos)
     
    #define RCC_PLLCFGR_PLLN_Pos   (6U)
     
    #define RCC_PLLCFGR_PLLN_Msk   (0x1FFUL << RCC_PLLCFGR_PLLN_Pos)
     
    #define RCC_PLLCFGR_PLLN   RCC_PLLCFGR_PLLN_Msk
     
    #define RCC_PLLCFGR_PLLN_0   (0x001UL << RCC_PLLCFGR_PLLN_Pos)
     
    #define RCC_PLLCFGR_PLLN_1   (0x002UL << RCC_PLLCFGR_PLLN_Pos)
     
    #define RCC_PLLCFGR_PLLN_2   (0x004UL << RCC_PLLCFGR_PLLN_Pos)
     
    #define RCC_PLLCFGR_PLLN_3   (0x008UL << RCC_PLLCFGR_PLLN_Pos)
     
    #define RCC_PLLCFGR_PLLN_4   (0x010UL << RCC_PLLCFGR_PLLN_Pos)
     
    #define RCC_PLLCFGR_PLLN_5   (0x020UL << RCC_PLLCFGR_PLLN_Pos)
     
    #define RCC_PLLCFGR_PLLN_6   (0x040UL << RCC_PLLCFGR_PLLN_Pos)
     
    #define RCC_PLLCFGR_PLLN_7   (0x080UL << RCC_PLLCFGR_PLLN_Pos)
     
    #define RCC_PLLCFGR_PLLN_8   (0x100UL << RCC_PLLCFGR_PLLN_Pos)
     
    #define RCC_PLLCFGR_PLLP_Pos   (16U)
     
    #define RCC_PLLCFGR_PLLP_Msk   (0x3UL << RCC_PLLCFGR_PLLP_Pos)
     
    #define RCC_PLLCFGR_PLLP   RCC_PLLCFGR_PLLP_Msk
     
    #define RCC_PLLCFGR_PLLP_0   (0x1UL << RCC_PLLCFGR_PLLP_Pos)
     
    #define RCC_PLLCFGR_PLLP_1   (0x2UL << RCC_PLLCFGR_PLLP_Pos)
     
    #define RCC_PLLCFGR_PLLSRC_Pos   (22U)
     
    #define RCC_PLLCFGR_PLLSRC_Msk   (0x1UL << RCC_PLLCFGR_PLLSRC_Pos)
     
    #define RCC_PLLCFGR_PLLSRC   RCC_PLLCFGR_PLLSRC_Msk
     
    #define RCC_PLLCFGR_PLLSRC_HSE_Pos   (22U)
     
    #define RCC_PLLCFGR_PLLSRC_HSE_Msk   (0x1UL << RCC_PLLCFGR_PLLSRC_HSE_Pos)
     
    #define RCC_PLLCFGR_PLLSRC_HSE   RCC_PLLCFGR_PLLSRC_HSE_Msk
     
    #define RCC_PLLCFGR_PLLSRC_HSI   0x00000000U
     
    #define RCC_PLLCFGR_PLLQ_Pos   (24U)
     
    #define RCC_PLLCFGR_PLLQ_Msk   (0xFUL << RCC_PLLCFGR_PLLQ_Pos)
     
    #define RCC_PLLCFGR_PLLQ   RCC_PLLCFGR_PLLQ_Msk
     
    #define RCC_PLLCFGR_PLLQ_0   (0x1UL << RCC_PLLCFGR_PLLQ_Pos)
     
    #define RCC_PLLCFGR_PLLQ_1   (0x2UL << RCC_PLLCFGR_PLLQ_Pos)
     
    #define RCC_PLLCFGR_PLLQ_2   (0x4UL << RCC_PLLCFGR_PLLQ_Pos)
     
    #define RCC_PLLCFGR_PLLQ_3   (0x8UL << RCC_PLLCFGR_PLLQ_Pos)
     
    #define RCC_CFGR_SW_Pos   (0U)
     
    #define RCC_CFGR_SW_Msk   (0x3UL << RCC_CFGR_SW_Pos)
     
    #define RCC_CFGR_SW   RCC_CFGR_SW_Msk
     
    #define RCC_CFGR_SW_0   (0x1UL << RCC_CFGR_SW_Pos)
     
    #define RCC_CFGR_SW_1   (0x2UL << RCC_CFGR_SW_Pos)
     
    #define RCC_CFGR_SW_HSI   0x00000000U
     
    #define RCC_CFGR_SW_HSE   0x00000001U
     
    #define RCC_CFGR_SW_PLL   0x00000002U
     
    #define RCC_CFGR_SWS_Pos   (2U)
     
    #define RCC_CFGR_SWS_Msk   (0x3UL << RCC_CFGR_SWS_Pos)
     
    #define RCC_CFGR_SWS   RCC_CFGR_SWS_Msk
     
    #define RCC_CFGR_SWS_0   (0x1UL << RCC_CFGR_SWS_Pos)
     
    #define RCC_CFGR_SWS_1   (0x2UL << RCC_CFGR_SWS_Pos)
     
    #define RCC_CFGR_SWS_HSI   0x00000000U
     
    #define RCC_CFGR_SWS_HSE   0x00000004U
     
    #define RCC_CFGR_SWS_PLL   0x00000008U
     
    #define RCC_CFGR_HPRE_Pos   (4U)
     
    #define RCC_CFGR_HPRE_Msk   (0xFUL << RCC_CFGR_HPRE_Pos)
     
    #define RCC_CFGR_HPRE   RCC_CFGR_HPRE_Msk
     
    #define RCC_CFGR_HPRE_0   (0x1UL << RCC_CFGR_HPRE_Pos)
     
    #define RCC_CFGR_HPRE_1   (0x2UL << RCC_CFGR_HPRE_Pos)
     
    #define RCC_CFGR_HPRE_2   (0x4UL << RCC_CFGR_HPRE_Pos)
     
    #define RCC_CFGR_HPRE_3   (0x8UL << RCC_CFGR_HPRE_Pos)
     
    #define RCC_CFGR_HPRE_DIV1   0x00000000U
     
    #define RCC_CFGR_HPRE_DIV2   0x00000080U
     
    #define RCC_CFGR_HPRE_DIV4   0x00000090U
     
    #define RCC_CFGR_HPRE_DIV8   0x000000A0U
     
    #define RCC_CFGR_HPRE_DIV16   0x000000B0U
     
    #define RCC_CFGR_HPRE_DIV64   0x000000C0U
     
    #define RCC_CFGR_HPRE_DIV128   0x000000D0U
     
    #define RCC_CFGR_HPRE_DIV256   0x000000E0U
     
    #define RCC_CFGR_HPRE_DIV512   0x000000F0U
     
    #define RCC_CFGR_PPRE1_Pos   (10U)
     
    #define RCC_CFGR_PPRE1_Msk   (0x7UL << RCC_CFGR_PPRE1_Pos)
     
    #define RCC_CFGR_PPRE1   RCC_CFGR_PPRE1_Msk
     
    #define RCC_CFGR_PPRE1_0   (0x1UL << RCC_CFGR_PPRE1_Pos)
     
    #define RCC_CFGR_PPRE1_1   (0x2UL << RCC_CFGR_PPRE1_Pos)
     
    #define RCC_CFGR_PPRE1_2   (0x4UL << RCC_CFGR_PPRE1_Pos)
     
    #define RCC_CFGR_PPRE1_DIV1   0x00000000U
     
    #define RCC_CFGR_PPRE1_DIV2   0x00001000U
     
    #define RCC_CFGR_PPRE1_DIV4   0x00001400U
     
    #define RCC_CFGR_PPRE1_DIV8   0x00001800U
     
    #define RCC_CFGR_PPRE1_DIV16   0x00001C00U
     
    #define RCC_CFGR_PPRE2_Pos   (13U)
     
    #define RCC_CFGR_PPRE2_Msk   (0x7UL << RCC_CFGR_PPRE2_Pos)
     
    #define RCC_CFGR_PPRE2   RCC_CFGR_PPRE2_Msk
     
    #define RCC_CFGR_PPRE2_0   (0x1UL << RCC_CFGR_PPRE2_Pos)
     
    #define RCC_CFGR_PPRE2_1   (0x2UL << RCC_CFGR_PPRE2_Pos)
     
    #define RCC_CFGR_PPRE2_2   (0x4UL << RCC_CFGR_PPRE2_Pos)
     
    #define RCC_CFGR_PPRE2_DIV1   0x00000000U
     
    #define RCC_CFGR_PPRE2_DIV2   0x00008000U
     
    #define RCC_CFGR_PPRE2_DIV4   0x0000A000U
     
    #define RCC_CFGR_PPRE2_DIV8   0x0000C000U
     
    #define RCC_CFGR_PPRE2_DIV16   0x0000E000U
     
    #define RCC_CFGR_RTCPRE_Pos   (16U)
     
    #define RCC_CFGR_RTCPRE_Msk   (0x1FUL << RCC_CFGR_RTCPRE_Pos)
     
    #define RCC_CFGR_RTCPRE   RCC_CFGR_RTCPRE_Msk
     
    #define RCC_CFGR_RTCPRE_0   (0x01UL << RCC_CFGR_RTCPRE_Pos)
     
    #define RCC_CFGR_RTCPRE_1   (0x02UL << RCC_CFGR_RTCPRE_Pos)
     
    #define RCC_CFGR_RTCPRE_2   (0x04UL << RCC_CFGR_RTCPRE_Pos)
     
    #define RCC_CFGR_RTCPRE_3   (0x08UL << RCC_CFGR_RTCPRE_Pos)
     
    #define RCC_CFGR_RTCPRE_4   (0x10UL << RCC_CFGR_RTCPRE_Pos)
     
    #define RCC_CFGR_MCO1_Pos   (21U)
     
    #define RCC_CFGR_MCO1_Msk   (0x3UL << RCC_CFGR_MCO1_Pos)
     
    #define RCC_CFGR_MCO1   RCC_CFGR_MCO1_Msk
     
    #define RCC_CFGR_MCO1_0   (0x1UL << RCC_CFGR_MCO1_Pos)
     
    #define RCC_CFGR_MCO1_1   (0x2UL << RCC_CFGR_MCO1_Pos)
     
    #define RCC_CFGR_I2SSRC_Pos   (23U)
     
    #define RCC_CFGR_I2SSRC_Msk   (0x1UL << RCC_CFGR_I2SSRC_Pos)
     
    #define RCC_CFGR_I2SSRC   RCC_CFGR_I2SSRC_Msk
     
    #define RCC_CFGR_MCO1PRE_Pos   (24U)
     
    #define RCC_CFGR_MCO1PRE_Msk   (0x7UL << RCC_CFGR_MCO1PRE_Pos)
     
    #define RCC_CFGR_MCO1PRE   RCC_CFGR_MCO1PRE_Msk
     
    #define RCC_CFGR_MCO1PRE_0   (0x1UL << RCC_CFGR_MCO1PRE_Pos)
     
    #define RCC_CFGR_MCO1PRE_1   (0x2UL << RCC_CFGR_MCO1PRE_Pos)
     
    #define RCC_CFGR_MCO1PRE_2   (0x4UL << RCC_CFGR_MCO1PRE_Pos)
     
    #define RCC_CFGR_MCO2PRE_Pos   (27U)
     
    #define RCC_CFGR_MCO2PRE_Msk   (0x7UL << RCC_CFGR_MCO2PRE_Pos)
     
    #define RCC_CFGR_MCO2PRE   RCC_CFGR_MCO2PRE_Msk
     
    #define RCC_CFGR_MCO2PRE_0   (0x1UL << RCC_CFGR_MCO2PRE_Pos)
     
    #define RCC_CFGR_MCO2PRE_1   (0x2UL << RCC_CFGR_MCO2PRE_Pos)
     
    #define RCC_CFGR_MCO2PRE_2   (0x4UL << RCC_CFGR_MCO2PRE_Pos)
     
    #define RCC_CFGR_MCO2_Pos   (30U)
     
    #define RCC_CFGR_MCO2_Msk   (0x3UL << RCC_CFGR_MCO2_Pos)
     
    #define RCC_CFGR_MCO2   RCC_CFGR_MCO2_Msk
     
    #define RCC_CFGR_MCO2_0   (0x1UL << RCC_CFGR_MCO2_Pos)
     
    #define RCC_CFGR_MCO2_1   (0x2UL << RCC_CFGR_MCO2_Pos)
     
    #define RCC_CIR_LSIRDYF_Pos   (0U)
     
    #define RCC_CIR_LSIRDYF_Msk   (0x1UL << RCC_CIR_LSIRDYF_Pos)
     
    #define RCC_CIR_LSIRDYF   RCC_CIR_LSIRDYF_Msk
     
    #define RCC_CIR_LSERDYF_Pos   (1U)
     
    #define RCC_CIR_LSERDYF_Msk   (0x1UL << RCC_CIR_LSERDYF_Pos)
     
    #define RCC_CIR_LSERDYF   RCC_CIR_LSERDYF_Msk
     
    #define RCC_CIR_HSIRDYF_Pos   (2U)
     
    #define RCC_CIR_HSIRDYF_Msk   (0x1UL << RCC_CIR_HSIRDYF_Pos)
     
    #define RCC_CIR_HSIRDYF   RCC_CIR_HSIRDYF_Msk
     
    #define RCC_CIR_HSERDYF_Pos   (3U)
     
    #define RCC_CIR_HSERDYF_Msk   (0x1UL << RCC_CIR_HSERDYF_Pos)
     
    #define RCC_CIR_HSERDYF   RCC_CIR_HSERDYF_Msk
     
    #define RCC_CIR_PLLRDYF_Pos   (4U)
     
    #define RCC_CIR_PLLRDYF_Msk   (0x1UL << RCC_CIR_PLLRDYF_Pos)
     
    #define RCC_CIR_PLLRDYF   RCC_CIR_PLLRDYF_Msk
     
    #define RCC_CIR_PLLI2SRDYF_Pos   (5U)
     
    #define RCC_CIR_PLLI2SRDYF_Msk   (0x1UL << RCC_CIR_PLLI2SRDYF_Pos)
     
    #define RCC_CIR_PLLI2SRDYF   RCC_CIR_PLLI2SRDYF_Msk
     
    #define RCC_CIR_CSSF_Pos   (7U)
     
    #define RCC_CIR_CSSF_Msk   (0x1UL << RCC_CIR_CSSF_Pos)
     
    #define RCC_CIR_CSSF   RCC_CIR_CSSF_Msk
     
    #define RCC_CIR_LSIRDYIE_Pos   (8U)
     
    #define RCC_CIR_LSIRDYIE_Msk   (0x1UL << RCC_CIR_LSIRDYIE_Pos)
     
    #define RCC_CIR_LSIRDYIE   RCC_CIR_LSIRDYIE_Msk
     
    #define RCC_CIR_LSERDYIE_Pos   (9U)
     
    #define RCC_CIR_LSERDYIE_Msk   (0x1UL << RCC_CIR_LSERDYIE_Pos)
     
    #define RCC_CIR_LSERDYIE   RCC_CIR_LSERDYIE_Msk
     
    #define RCC_CIR_HSIRDYIE_Pos   (10U)
     
    #define RCC_CIR_HSIRDYIE_Msk   (0x1UL << RCC_CIR_HSIRDYIE_Pos)
     
    #define RCC_CIR_HSIRDYIE   RCC_CIR_HSIRDYIE_Msk
     
    #define RCC_CIR_HSERDYIE_Pos   (11U)
     
    #define RCC_CIR_HSERDYIE_Msk   (0x1UL << RCC_CIR_HSERDYIE_Pos)
     
    #define RCC_CIR_HSERDYIE   RCC_CIR_HSERDYIE_Msk
     
    #define RCC_CIR_PLLRDYIE_Pos   (12U)
     
    #define RCC_CIR_PLLRDYIE_Msk   (0x1UL << RCC_CIR_PLLRDYIE_Pos)
     
    #define RCC_CIR_PLLRDYIE   RCC_CIR_PLLRDYIE_Msk
     
    #define RCC_CIR_PLLI2SRDYIE_Pos   (13U)
     
    #define RCC_CIR_PLLI2SRDYIE_Msk   (0x1UL << RCC_CIR_PLLI2SRDYIE_Pos)
     
    #define RCC_CIR_PLLI2SRDYIE   RCC_CIR_PLLI2SRDYIE_Msk
     
    #define RCC_CIR_LSIRDYC_Pos   (16U)
     
    #define RCC_CIR_LSIRDYC_Msk   (0x1UL << RCC_CIR_LSIRDYC_Pos)
     
    #define RCC_CIR_LSIRDYC   RCC_CIR_LSIRDYC_Msk
     
    #define RCC_CIR_LSERDYC_Pos   (17U)
     
    #define RCC_CIR_LSERDYC_Msk   (0x1UL << RCC_CIR_LSERDYC_Pos)
     
    #define RCC_CIR_LSERDYC   RCC_CIR_LSERDYC_Msk
     
    #define RCC_CIR_HSIRDYC_Pos   (18U)
     
    #define RCC_CIR_HSIRDYC_Msk   (0x1UL << RCC_CIR_HSIRDYC_Pos)
     
    #define RCC_CIR_HSIRDYC   RCC_CIR_HSIRDYC_Msk
     
    #define RCC_CIR_HSERDYC_Pos   (19U)
     
    #define RCC_CIR_HSERDYC_Msk   (0x1UL << RCC_CIR_HSERDYC_Pos)
     
    #define RCC_CIR_HSERDYC   RCC_CIR_HSERDYC_Msk
     
    #define RCC_CIR_PLLRDYC_Pos   (20U)
     
    #define RCC_CIR_PLLRDYC_Msk   (0x1UL << RCC_CIR_PLLRDYC_Pos)
     
    #define RCC_CIR_PLLRDYC   RCC_CIR_PLLRDYC_Msk
     
    #define RCC_CIR_PLLI2SRDYC_Pos   (21U)
     
    #define RCC_CIR_PLLI2SRDYC_Msk   (0x1UL << RCC_CIR_PLLI2SRDYC_Pos)
     
    #define RCC_CIR_PLLI2SRDYC   RCC_CIR_PLLI2SRDYC_Msk
     
    #define RCC_CIR_CSSC_Pos   (23U)
     
    #define RCC_CIR_CSSC_Msk   (0x1UL << RCC_CIR_CSSC_Pos)
     
    #define RCC_CIR_CSSC   RCC_CIR_CSSC_Msk
     
    #define RCC_AHB1RSTR_GPIOARST_Pos   (0U)
     
    #define RCC_AHB1RSTR_GPIOARST_Msk   (0x1UL << RCC_AHB1RSTR_GPIOARST_Pos)
     
    #define RCC_AHB1RSTR_GPIOARST   RCC_AHB1RSTR_GPIOARST_Msk
     
    #define RCC_AHB1RSTR_GPIOBRST_Pos   (1U)
     
    #define RCC_AHB1RSTR_GPIOBRST_Msk   (0x1UL << RCC_AHB1RSTR_GPIOBRST_Pos)
     
    #define RCC_AHB1RSTR_GPIOBRST   RCC_AHB1RSTR_GPIOBRST_Msk
     
    #define RCC_AHB1RSTR_GPIOCRST_Pos   (2U)
     
    #define RCC_AHB1RSTR_GPIOCRST_Msk   (0x1UL << RCC_AHB1RSTR_GPIOCRST_Pos)
     
    #define RCC_AHB1RSTR_GPIOCRST   RCC_AHB1RSTR_GPIOCRST_Msk
     
    #define RCC_AHB1RSTR_GPIODRST_Pos   (3U)
     
    #define RCC_AHB1RSTR_GPIODRST_Msk   (0x1UL << RCC_AHB1RSTR_GPIODRST_Pos)
     
    #define RCC_AHB1RSTR_GPIODRST   RCC_AHB1RSTR_GPIODRST_Msk
     
    #define RCC_AHB1RSTR_GPIOERST_Pos   (4U)
     
    #define RCC_AHB1RSTR_GPIOERST_Msk   (0x1UL << RCC_AHB1RSTR_GPIOERST_Pos)
     
    #define RCC_AHB1RSTR_GPIOERST   RCC_AHB1RSTR_GPIOERST_Msk
     
    #define RCC_AHB1RSTR_GPIOFRST_Pos   (5U)
     
    #define RCC_AHB1RSTR_GPIOFRST_Msk   (0x1UL << RCC_AHB1RSTR_GPIOFRST_Pos)
     
    #define RCC_AHB1RSTR_GPIOFRST   RCC_AHB1RSTR_GPIOFRST_Msk
     
    #define RCC_AHB1RSTR_GPIOGRST_Pos   (6U)
     
    #define RCC_AHB1RSTR_GPIOGRST_Msk   (0x1UL << RCC_AHB1RSTR_GPIOGRST_Pos)
     
    #define RCC_AHB1RSTR_GPIOGRST   RCC_AHB1RSTR_GPIOGRST_Msk
     
    #define RCC_AHB1RSTR_GPIOHRST_Pos   (7U)
     
    #define RCC_AHB1RSTR_GPIOHRST_Msk   (0x1UL << RCC_AHB1RSTR_GPIOHRST_Pos)
     
    #define RCC_AHB1RSTR_GPIOHRST   RCC_AHB1RSTR_GPIOHRST_Msk
     
    #define RCC_AHB1RSTR_GPIOIRST_Pos   (8U)
     
    #define RCC_AHB1RSTR_GPIOIRST_Msk   (0x1UL << RCC_AHB1RSTR_GPIOIRST_Pos)
     
    #define RCC_AHB1RSTR_GPIOIRST   RCC_AHB1RSTR_GPIOIRST_Msk
     
    #define RCC_AHB1RSTR_CRCRST_Pos   (12U)
     
    #define RCC_AHB1RSTR_CRCRST_Msk   (0x1UL << RCC_AHB1RSTR_CRCRST_Pos)
     
    #define RCC_AHB1RSTR_CRCRST   RCC_AHB1RSTR_CRCRST_Msk
     
    #define RCC_AHB1RSTR_DMA1RST_Pos   (21U)
     
    #define RCC_AHB1RSTR_DMA1RST_Msk   (0x1UL << RCC_AHB1RSTR_DMA1RST_Pos)
     
    #define RCC_AHB1RSTR_DMA1RST   RCC_AHB1RSTR_DMA1RST_Msk
     
    #define RCC_AHB1RSTR_DMA2RST_Pos   (22U)
     
    #define RCC_AHB1RSTR_DMA2RST_Msk   (0x1UL << RCC_AHB1RSTR_DMA2RST_Pos)
     
    #define RCC_AHB1RSTR_DMA2RST   RCC_AHB1RSTR_DMA2RST_Msk
     
    #define RCC_AHB1RSTR_ETHMACRST_Pos   (25U)
     
    #define RCC_AHB1RSTR_ETHMACRST_Msk   (0x1UL << RCC_AHB1RSTR_ETHMACRST_Pos)
     
    #define RCC_AHB1RSTR_ETHMACRST   RCC_AHB1RSTR_ETHMACRST_Msk
     
    #define RCC_AHB1RSTR_OTGHRST_Pos   (29U)
     
    #define RCC_AHB1RSTR_OTGHRST_Msk   (0x1UL << RCC_AHB1RSTR_OTGHRST_Pos)
     
    #define RCC_AHB1RSTR_OTGHRST   RCC_AHB1RSTR_OTGHRST_Msk
     
    #define RCC_AHB2RSTR_DCMIRST_Pos   (0U)
     
    #define RCC_AHB2RSTR_DCMIRST_Msk   (0x1UL << RCC_AHB2RSTR_DCMIRST_Pos)
     
    #define RCC_AHB2RSTR_DCMIRST   RCC_AHB2RSTR_DCMIRST_Msk
     
    #define RCC_AHB2RSTR_RNGRST_Pos   (6U)
     
    #define RCC_AHB2RSTR_RNGRST_Msk   (0x1UL << RCC_AHB2RSTR_RNGRST_Pos)
     
    #define RCC_AHB2RSTR_RNGRST   RCC_AHB2RSTR_RNGRST_Msk
     
    #define RCC_AHB2RSTR_OTGFSRST_Pos   (7U)
     
    #define RCC_AHB2RSTR_OTGFSRST_Msk   (0x1UL << RCC_AHB2RSTR_OTGFSRST_Pos)
     
    #define RCC_AHB2RSTR_OTGFSRST   RCC_AHB2RSTR_OTGFSRST_Msk
     
    #define RCC_AHB3RSTR_FSMCRST_Pos   (0U)
     
    #define RCC_AHB3RSTR_FSMCRST_Msk   (0x1UL << RCC_AHB3RSTR_FSMCRST_Pos)
     
    #define RCC_AHB3RSTR_FSMCRST   RCC_AHB3RSTR_FSMCRST_Msk
     
    #define RCC_APB1RSTR_TIM2RST_Pos   (0U)
     
    #define RCC_APB1RSTR_TIM2RST_Msk   (0x1UL << RCC_APB1RSTR_TIM2RST_Pos)
     
    #define RCC_APB1RSTR_TIM2RST   RCC_APB1RSTR_TIM2RST_Msk
     
    #define RCC_APB1RSTR_TIM3RST_Pos   (1U)
     
    #define RCC_APB1RSTR_TIM3RST_Msk   (0x1UL << RCC_APB1RSTR_TIM3RST_Pos)
     
    #define RCC_APB1RSTR_TIM3RST   RCC_APB1RSTR_TIM3RST_Msk
     
    #define RCC_APB1RSTR_TIM4RST_Pos   (2U)
     
    #define RCC_APB1RSTR_TIM4RST_Msk   (0x1UL << RCC_APB1RSTR_TIM4RST_Pos)
     
    #define RCC_APB1RSTR_TIM4RST   RCC_APB1RSTR_TIM4RST_Msk
     
    #define RCC_APB1RSTR_TIM5RST_Pos   (3U)
     
    #define RCC_APB1RSTR_TIM5RST_Msk   (0x1UL << RCC_APB1RSTR_TIM5RST_Pos)
     
    #define RCC_APB1RSTR_TIM5RST   RCC_APB1RSTR_TIM5RST_Msk
     
    #define RCC_APB1RSTR_TIM6RST_Pos   (4U)
     
    #define RCC_APB1RSTR_TIM6RST_Msk   (0x1UL << RCC_APB1RSTR_TIM6RST_Pos)
     
    #define RCC_APB1RSTR_TIM6RST   RCC_APB1RSTR_TIM6RST_Msk
     
    #define RCC_APB1RSTR_TIM7RST_Pos   (5U)
     
    #define RCC_APB1RSTR_TIM7RST_Msk   (0x1UL << RCC_APB1RSTR_TIM7RST_Pos)
     
    #define RCC_APB1RSTR_TIM7RST   RCC_APB1RSTR_TIM7RST_Msk
     
    #define RCC_APB1RSTR_TIM12RST_Pos   (6U)
     
    #define RCC_APB1RSTR_TIM12RST_Msk   (0x1UL << RCC_APB1RSTR_TIM12RST_Pos)
     
    #define RCC_APB1RSTR_TIM12RST   RCC_APB1RSTR_TIM12RST_Msk
     
    #define RCC_APB1RSTR_TIM13RST_Pos   (7U)
     
    #define RCC_APB1RSTR_TIM13RST_Msk   (0x1UL << RCC_APB1RSTR_TIM13RST_Pos)
     
    #define RCC_APB1RSTR_TIM13RST   RCC_APB1RSTR_TIM13RST_Msk
     
    #define RCC_APB1RSTR_TIM14RST_Pos   (8U)
     
    #define RCC_APB1RSTR_TIM14RST_Msk   (0x1UL << RCC_APB1RSTR_TIM14RST_Pos)
     
    #define RCC_APB1RSTR_TIM14RST   RCC_APB1RSTR_TIM14RST_Msk
     
    #define RCC_APB1RSTR_WWDGRST_Pos   (11U)
     
    #define RCC_APB1RSTR_WWDGRST_Msk   (0x1UL << RCC_APB1RSTR_WWDGRST_Pos)
     
    #define RCC_APB1RSTR_WWDGRST   RCC_APB1RSTR_WWDGRST_Msk
     
    #define RCC_APB1RSTR_SPI2RST_Pos   (14U)
     
    #define RCC_APB1RSTR_SPI2RST_Msk   (0x1UL << RCC_APB1RSTR_SPI2RST_Pos)
     
    #define RCC_APB1RSTR_SPI2RST   RCC_APB1RSTR_SPI2RST_Msk
     
    #define RCC_APB1RSTR_SPI3RST_Pos   (15U)
     
    #define RCC_APB1RSTR_SPI3RST_Msk   (0x1UL << RCC_APB1RSTR_SPI3RST_Pos)
     
    #define RCC_APB1RSTR_SPI3RST   RCC_APB1RSTR_SPI3RST_Msk
     
    #define RCC_APB1RSTR_USART2RST_Pos   (17U)
     
    #define RCC_APB1RSTR_USART2RST_Msk   (0x1UL << RCC_APB1RSTR_USART2RST_Pos)
     
    #define RCC_APB1RSTR_USART2RST   RCC_APB1RSTR_USART2RST_Msk
     
    #define RCC_APB1RSTR_USART3RST_Pos   (18U)
     
    #define RCC_APB1RSTR_USART3RST_Msk   (0x1UL << RCC_APB1RSTR_USART3RST_Pos)
     
    #define RCC_APB1RSTR_USART3RST   RCC_APB1RSTR_USART3RST_Msk
     
    #define RCC_APB1RSTR_UART4RST_Pos   (19U)
     
    #define RCC_APB1RSTR_UART4RST_Msk   (0x1UL << RCC_APB1RSTR_UART4RST_Pos)
     
    #define RCC_APB1RSTR_UART4RST   RCC_APB1RSTR_UART4RST_Msk
     
    #define RCC_APB1RSTR_UART5RST_Pos   (20U)
     
    #define RCC_APB1RSTR_UART5RST_Msk   (0x1UL << RCC_APB1RSTR_UART5RST_Pos)
     
    #define RCC_APB1RSTR_UART5RST   RCC_APB1RSTR_UART5RST_Msk
     
    #define RCC_APB1RSTR_I2C1RST_Pos   (21U)
     
    #define RCC_APB1RSTR_I2C1RST_Msk   (0x1UL << RCC_APB1RSTR_I2C1RST_Pos)
     
    #define RCC_APB1RSTR_I2C1RST   RCC_APB1RSTR_I2C1RST_Msk
     
    #define RCC_APB1RSTR_I2C2RST_Pos   (22U)
     
    #define RCC_APB1RSTR_I2C2RST_Msk   (0x1UL << RCC_APB1RSTR_I2C2RST_Pos)
     
    #define RCC_APB1RSTR_I2C2RST   RCC_APB1RSTR_I2C2RST_Msk
     
    #define RCC_APB1RSTR_I2C3RST_Pos   (23U)
     
    #define RCC_APB1RSTR_I2C3RST_Msk   (0x1UL << RCC_APB1RSTR_I2C3RST_Pos)
     
    #define RCC_APB1RSTR_I2C3RST   RCC_APB1RSTR_I2C3RST_Msk
     
    #define RCC_APB1RSTR_CAN1RST_Pos   (25U)
     
    #define RCC_APB1RSTR_CAN1RST_Msk   (0x1UL << RCC_APB1RSTR_CAN1RST_Pos)
     
    #define RCC_APB1RSTR_CAN1RST   RCC_APB1RSTR_CAN1RST_Msk
     
    #define RCC_APB1RSTR_CAN2RST_Pos   (26U)
     
    #define RCC_APB1RSTR_CAN2RST_Msk   (0x1UL << RCC_APB1RSTR_CAN2RST_Pos)
     
    #define RCC_APB1RSTR_CAN2RST   RCC_APB1RSTR_CAN2RST_Msk
     
    #define RCC_APB1RSTR_PWRRST_Pos   (28U)
     
    #define RCC_APB1RSTR_PWRRST_Msk   (0x1UL << RCC_APB1RSTR_PWRRST_Pos)
     
    #define RCC_APB1RSTR_PWRRST   RCC_APB1RSTR_PWRRST_Msk
     
    #define RCC_APB1RSTR_DACRST_Pos   (29U)
     
    #define RCC_APB1RSTR_DACRST_Msk   (0x1UL << RCC_APB1RSTR_DACRST_Pos)
     
    #define RCC_APB1RSTR_DACRST   RCC_APB1RSTR_DACRST_Msk
     
    #define RCC_APB2RSTR_TIM1RST_Pos   (0U)
     
    #define RCC_APB2RSTR_TIM1RST_Msk   (0x1UL << RCC_APB2RSTR_TIM1RST_Pos)
     
    #define RCC_APB2RSTR_TIM1RST   RCC_APB2RSTR_TIM1RST_Msk
     
    #define RCC_APB2RSTR_TIM8RST_Pos   (1U)
     
    #define RCC_APB2RSTR_TIM8RST_Msk   (0x1UL << RCC_APB2RSTR_TIM8RST_Pos)
     
    #define RCC_APB2RSTR_TIM8RST   RCC_APB2RSTR_TIM8RST_Msk
     
    #define RCC_APB2RSTR_USART1RST_Pos   (4U)
     
    #define RCC_APB2RSTR_USART1RST_Msk   (0x1UL << RCC_APB2RSTR_USART1RST_Pos)
     
    #define RCC_APB2RSTR_USART1RST   RCC_APB2RSTR_USART1RST_Msk
     
    #define RCC_APB2RSTR_USART6RST_Pos   (5U)
     
    #define RCC_APB2RSTR_USART6RST_Msk   (0x1UL << RCC_APB2RSTR_USART6RST_Pos)
     
    #define RCC_APB2RSTR_USART6RST   RCC_APB2RSTR_USART6RST_Msk
     
    #define RCC_APB2RSTR_ADCRST_Pos   (8U)
     
    #define RCC_APB2RSTR_ADCRST_Msk   (0x1UL << RCC_APB2RSTR_ADCRST_Pos)
     
    #define RCC_APB2RSTR_ADCRST   RCC_APB2RSTR_ADCRST_Msk
     
    #define RCC_APB2RSTR_SDIORST_Pos   (11U)
     
    #define RCC_APB2RSTR_SDIORST_Msk   (0x1UL << RCC_APB2RSTR_SDIORST_Pos)
     
    #define RCC_APB2RSTR_SDIORST   RCC_APB2RSTR_SDIORST_Msk
     
    #define RCC_APB2RSTR_SPI1RST_Pos   (12U)
     
    #define RCC_APB2RSTR_SPI1RST_Msk   (0x1UL << RCC_APB2RSTR_SPI1RST_Pos)
     
    #define RCC_APB2RSTR_SPI1RST   RCC_APB2RSTR_SPI1RST_Msk
     
    #define RCC_APB2RSTR_SYSCFGRST_Pos   (14U)
     
    #define RCC_APB2RSTR_SYSCFGRST_Msk   (0x1UL << RCC_APB2RSTR_SYSCFGRST_Pos)
     
    #define RCC_APB2RSTR_SYSCFGRST   RCC_APB2RSTR_SYSCFGRST_Msk
     
    #define RCC_APB2RSTR_TIM9RST_Pos   (16U)
     
    #define RCC_APB2RSTR_TIM9RST_Msk   (0x1UL << RCC_APB2RSTR_TIM9RST_Pos)
     
    #define RCC_APB2RSTR_TIM9RST   RCC_APB2RSTR_TIM9RST_Msk
     
    #define RCC_APB2RSTR_TIM10RST_Pos   (17U)
     
    #define RCC_APB2RSTR_TIM10RST_Msk   (0x1UL << RCC_APB2RSTR_TIM10RST_Pos)
     
    #define RCC_APB2RSTR_TIM10RST   RCC_APB2RSTR_TIM10RST_Msk
     
    #define RCC_APB2RSTR_TIM11RST_Pos   (18U)
     
    #define RCC_APB2RSTR_TIM11RST_Msk   (0x1UL << RCC_APB2RSTR_TIM11RST_Pos)
     
    #define RCC_APB2RSTR_TIM11RST   RCC_APB2RSTR_TIM11RST_Msk
     
    #define RCC_APB2RSTR_SPI1   RCC_APB2RSTR_SPI1RST
     
    #define RCC_AHB1ENR_GPIOAEN_Pos   (0U)
     
    #define RCC_AHB1ENR_GPIOAEN_Msk   (0x1UL << RCC_AHB1ENR_GPIOAEN_Pos)
     
    #define RCC_AHB1ENR_GPIOAEN   RCC_AHB1ENR_GPIOAEN_Msk
     
    #define RCC_AHB1ENR_GPIOBEN_Pos   (1U)
     
    #define RCC_AHB1ENR_GPIOBEN_Msk   (0x1UL << RCC_AHB1ENR_GPIOBEN_Pos)
     
    #define RCC_AHB1ENR_GPIOBEN   RCC_AHB1ENR_GPIOBEN_Msk
     
    #define RCC_AHB1ENR_GPIOCEN_Pos   (2U)
     
    #define RCC_AHB1ENR_GPIOCEN_Msk   (0x1UL << RCC_AHB1ENR_GPIOCEN_Pos)
     
    #define RCC_AHB1ENR_GPIOCEN   RCC_AHB1ENR_GPIOCEN_Msk
     
    #define RCC_AHB1ENR_GPIODEN_Pos   (3U)
     
    #define RCC_AHB1ENR_GPIODEN_Msk   (0x1UL << RCC_AHB1ENR_GPIODEN_Pos)
     
    #define RCC_AHB1ENR_GPIODEN   RCC_AHB1ENR_GPIODEN_Msk
     
    #define RCC_AHB1ENR_GPIOEEN_Pos   (4U)
     
    #define RCC_AHB1ENR_GPIOEEN_Msk   (0x1UL << RCC_AHB1ENR_GPIOEEN_Pos)
     
    #define RCC_AHB1ENR_GPIOEEN   RCC_AHB1ENR_GPIOEEN_Msk
     
    #define RCC_AHB1ENR_GPIOFEN_Pos   (5U)
     
    #define RCC_AHB1ENR_GPIOFEN_Msk   (0x1UL << RCC_AHB1ENR_GPIOFEN_Pos)
     
    #define RCC_AHB1ENR_GPIOFEN   RCC_AHB1ENR_GPIOFEN_Msk
     
    #define RCC_AHB1ENR_GPIOGEN_Pos   (6U)
     
    #define RCC_AHB1ENR_GPIOGEN_Msk   (0x1UL << RCC_AHB1ENR_GPIOGEN_Pos)
     
    #define RCC_AHB1ENR_GPIOGEN   RCC_AHB1ENR_GPIOGEN_Msk
     
    #define RCC_AHB1ENR_GPIOHEN_Pos   (7U)
     
    #define RCC_AHB1ENR_GPIOHEN_Msk   (0x1UL << RCC_AHB1ENR_GPIOHEN_Pos)
     
    #define RCC_AHB1ENR_GPIOHEN   RCC_AHB1ENR_GPIOHEN_Msk
     
    #define RCC_AHB1ENR_GPIOIEN_Pos   (8U)
     
    #define RCC_AHB1ENR_GPIOIEN_Msk   (0x1UL << RCC_AHB1ENR_GPIOIEN_Pos)
     
    #define RCC_AHB1ENR_GPIOIEN   RCC_AHB1ENR_GPIOIEN_Msk
     
    #define RCC_AHB1ENR_CRCEN_Pos   (12U)
     
    #define RCC_AHB1ENR_CRCEN_Msk   (0x1UL << RCC_AHB1ENR_CRCEN_Pos)
     
    #define RCC_AHB1ENR_CRCEN   RCC_AHB1ENR_CRCEN_Msk
     
    #define RCC_AHB1ENR_BKPSRAMEN_Pos   (18U)
     
    #define RCC_AHB1ENR_BKPSRAMEN_Msk   (0x1UL << RCC_AHB1ENR_BKPSRAMEN_Pos)
     
    #define RCC_AHB1ENR_BKPSRAMEN   RCC_AHB1ENR_BKPSRAMEN_Msk
     
    #define RCC_AHB1ENR_CCMDATARAMEN_Pos   (20U)
     
    #define RCC_AHB1ENR_CCMDATARAMEN_Msk   (0x1UL << RCC_AHB1ENR_CCMDATARAMEN_Pos)
     
    #define RCC_AHB1ENR_CCMDATARAMEN   RCC_AHB1ENR_CCMDATARAMEN_Msk
     
    #define RCC_AHB1ENR_DMA1EN_Pos   (21U)
     
    #define RCC_AHB1ENR_DMA1EN_Msk   (0x1UL << RCC_AHB1ENR_DMA1EN_Pos)
     
    #define RCC_AHB1ENR_DMA1EN   RCC_AHB1ENR_DMA1EN_Msk
     
    #define RCC_AHB1ENR_DMA2EN_Pos   (22U)
     
    #define RCC_AHB1ENR_DMA2EN_Msk   (0x1UL << RCC_AHB1ENR_DMA2EN_Pos)
     
    #define RCC_AHB1ENR_DMA2EN   RCC_AHB1ENR_DMA2EN_Msk
     
    #define RCC_AHB1ENR_ETHMACEN_Pos   (25U)
     
    #define RCC_AHB1ENR_ETHMACEN_Msk   (0x1UL << RCC_AHB1ENR_ETHMACEN_Pos)
     
    #define RCC_AHB1ENR_ETHMACEN   RCC_AHB1ENR_ETHMACEN_Msk
     
    #define RCC_AHB1ENR_ETHMACTXEN_Pos   (26U)
     
    #define RCC_AHB1ENR_ETHMACTXEN_Msk   (0x1UL << RCC_AHB1ENR_ETHMACTXEN_Pos)
     
    #define RCC_AHB1ENR_ETHMACTXEN   RCC_AHB1ENR_ETHMACTXEN_Msk
     
    #define RCC_AHB1ENR_ETHMACRXEN_Pos   (27U)
     
    #define RCC_AHB1ENR_ETHMACRXEN_Msk   (0x1UL << RCC_AHB1ENR_ETHMACRXEN_Pos)
     
    #define RCC_AHB1ENR_ETHMACRXEN   RCC_AHB1ENR_ETHMACRXEN_Msk
     
    #define RCC_AHB1ENR_ETHMACPTPEN_Pos   (28U)
     
    #define RCC_AHB1ENR_ETHMACPTPEN_Msk   (0x1UL << RCC_AHB1ENR_ETHMACPTPEN_Pos)
     
    #define RCC_AHB1ENR_ETHMACPTPEN   RCC_AHB1ENR_ETHMACPTPEN_Msk
     
    #define RCC_AHB1ENR_OTGHSEN_Pos   (29U)
     
    #define RCC_AHB1ENR_OTGHSEN_Msk   (0x1UL << RCC_AHB1ENR_OTGHSEN_Pos)
     
    #define RCC_AHB1ENR_OTGHSEN   RCC_AHB1ENR_OTGHSEN_Msk
     
    #define RCC_AHB1ENR_OTGHSULPIEN_Pos   (30U)
     
    #define RCC_AHB1ENR_OTGHSULPIEN_Msk   (0x1UL << RCC_AHB1ENR_OTGHSULPIEN_Pos)
     
    #define RCC_AHB1ENR_OTGHSULPIEN   RCC_AHB1ENR_OTGHSULPIEN_Msk
     
    #define RCC_AHB2_SUPPORT
     
    #define RCC_AHB2ENR_DCMIEN_Pos   (0U)
     
    #define RCC_AHB2ENR_DCMIEN_Msk   (0x1UL << RCC_AHB2ENR_DCMIEN_Pos)
     
    #define RCC_AHB2ENR_DCMIEN   RCC_AHB2ENR_DCMIEN_Msk
     
    #define RCC_AHB2ENR_RNGEN_Pos   (6U)
     
    #define RCC_AHB2ENR_RNGEN_Msk   (0x1UL << RCC_AHB2ENR_RNGEN_Pos)
     
    #define RCC_AHB2ENR_RNGEN   RCC_AHB2ENR_RNGEN_Msk
     
    #define RCC_AHB2ENR_OTGFSEN_Pos   (7U)
     
    #define RCC_AHB2ENR_OTGFSEN_Msk   (0x1UL << RCC_AHB2ENR_OTGFSEN_Pos)
     
    #define RCC_AHB2ENR_OTGFSEN   RCC_AHB2ENR_OTGFSEN_Msk
     
    #define RCC_AHB3_SUPPORT
     
    #define RCC_AHB3ENR_FSMCEN_Pos   (0U)
     
    #define RCC_AHB3ENR_FSMCEN_Msk   (0x1UL << RCC_AHB3ENR_FSMCEN_Pos)
     
    #define RCC_AHB3ENR_FSMCEN   RCC_AHB3ENR_FSMCEN_Msk
     
    #define RCC_APB1ENR_TIM2EN_Pos   (0U)
     
    #define RCC_APB1ENR_TIM2EN_Msk   (0x1UL << RCC_APB1ENR_TIM2EN_Pos)
     
    #define RCC_APB1ENR_TIM2EN   RCC_APB1ENR_TIM2EN_Msk
     
    #define RCC_APB1ENR_TIM3EN_Pos   (1U)
     
    #define RCC_APB1ENR_TIM3EN_Msk   (0x1UL << RCC_APB1ENR_TIM3EN_Pos)
     
    #define RCC_APB1ENR_TIM3EN   RCC_APB1ENR_TIM3EN_Msk
     
    #define RCC_APB1ENR_TIM4EN_Pos   (2U)
     
    #define RCC_APB1ENR_TIM4EN_Msk   (0x1UL << RCC_APB1ENR_TIM4EN_Pos)
     
    #define RCC_APB1ENR_TIM4EN   RCC_APB1ENR_TIM4EN_Msk
     
    #define RCC_APB1ENR_TIM5EN_Pos   (3U)
     
    #define RCC_APB1ENR_TIM5EN_Msk   (0x1UL << RCC_APB1ENR_TIM5EN_Pos)
     
    #define RCC_APB1ENR_TIM5EN   RCC_APB1ENR_TIM5EN_Msk
     
    #define RCC_APB1ENR_TIM6EN_Pos   (4U)
     
    #define RCC_APB1ENR_TIM6EN_Msk   (0x1UL << RCC_APB1ENR_TIM6EN_Pos)
     
    #define RCC_APB1ENR_TIM6EN   RCC_APB1ENR_TIM6EN_Msk
     
    #define RCC_APB1ENR_TIM7EN_Pos   (5U)
     
    #define RCC_APB1ENR_TIM7EN_Msk   (0x1UL << RCC_APB1ENR_TIM7EN_Pos)
     
    #define RCC_APB1ENR_TIM7EN   RCC_APB1ENR_TIM7EN_Msk
     
    #define RCC_APB1ENR_TIM12EN_Pos   (6U)
     
    #define RCC_APB1ENR_TIM12EN_Msk   (0x1UL << RCC_APB1ENR_TIM12EN_Pos)
     
    #define RCC_APB1ENR_TIM12EN   RCC_APB1ENR_TIM12EN_Msk
     
    #define RCC_APB1ENR_TIM13EN_Pos   (7U)
     
    #define RCC_APB1ENR_TIM13EN_Msk   (0x1UL << RCC_APB1ENR_TIM13EN_Pos)
     
    #define RCC_APB1ENR_TIM13EN   RCC_APB1ENR_TIM13EN_Msk
     
    #define RCC_APB1ENR_TIM14EN_Pos   (8U)
     
    #define RCC_APB1ENR_TIM14EN_Msk   (0x1UL << RCC_APB1ENR_TIM14EN_Pos)
     
    #define RCC_APB1ENR_TIM14EN   RCC_APB1ENR_TIM14EN_Msk
     
    #define RCC_APB1ENR_WWDGEN_Pos   (11U)
     
    #define RCC_APB1ENR_WWDGEN_Msk   (0x1UL << RCC_APB1ENR_WWDGEN_Pos)
     
    #define RCC_APB1ENR_WWDGEN   RCC_APB1ENR_WWDGEN_Msk
     
    #define RCC_APB1ENR_SPI2EN_Pos   (14U)
     
    #define RCC_APB1ENR_SPI2EN_Msk   (0x1UL << RCC_APB1ENR_SPI2EN_Pos)
     
    #define RCC_APB1ENR_SPI2EN   RCC_APB1ENR_SPI2EN_Msk
     
    #define RCC_APB1ENR_SPI3EN_Pos   (15U)
     
    #define RCC_APB1ENR_SPI3EN_Msk   (0x1UL << RCC_APB1ENR_SPI3EN_Pos)
     
    #define RCC_APB1ENR_SPI3EN   RCC_APB1ENR_SPI3EN_Msk
     
    #define RCC_APB1ENR_USART2EN_Pos   (17U)
     
    #define RCC_APB1ENR_USART2EN_Msk   (0x1UL << RCC_APB1ENR_USART2EN_Pos)
     
    #define RCC_APB1ENR_USART2EN   RCC_APB1ENR_USART2EN_Msk
     
    #define RCC_APB1ENR_USART3EN_Pos   (18U)
     
    #define RCC_APB1ENR_USART3EN_Msk   (0x1UL << RCC_APB1ENR_USART3EN_Pos)
     
    #define RCC_APB1ENR_USART3EN   RCC_APB1ENR_USART3EN_Msk
     
    #define RCC_APB1ENR_UART4EN_Pos   (19U)
     
    #define RCC_APB1ENR_UART4EN_Msk   (0x1UL << RCC_APB1ENR_UART4EN_Pos)
     
    #define RCC_APB1ENR_UART4EN   RCC_APB1ENR_UART4EN_Msk
     
    #define RCC_APB1ENR_UART5EN_Pos   (20U)
     
    #define RCC_APB1ENR_UART5EN_Msk   (0x1UL << RCC_APB1ENR_UART5EN_Pos)
     
    #define RCC_APB1ENR_UART5EN   RCC_APB1ENR_UART5EN_Msk
     
    #define RCC_APB1ENR_I2C1EN_Pos   (21U)
     
    #define RCC_APB1ENR_I2C1EN_Msk   (0x1UL << RCC_APB1ENR_I2C1EN_Pos)
     
    #define RCC_APB1ENR_I2C1EN   RCC_APB1ENR_I2C1EN_Msk
     
    #define RCC_APB1ENR_I2C2EN_Pos   (22U)
     
    #define RCC_APB1ENR_I2C2EN_Msk   (0x1UL << RCC_APB1ENR_I2C2EN_Pos)
     
    #define RCC_APB1ENR_I2C2EN   RCC_APB1ENR_I2C2EN_Msk
     
    #define RCC_APB1ENR_I2C3EN_Pos   (23U)
     
    #define RCC_APB1ENR_I2C3EN_Msk   (0x1UL << RCC_APB1ENR_I2C3EN_Pos)
     
    #define RCC_APB1ENR_I2C3EN   RCC_APB1ENR_I2C3EN_Msk
     
    #define RCC_APB1ENR_CAN1EN_Pos   (25U)
     
    #define RCC_APB1ENR_CAN1EN_Msk   (0x1UL << RCC_APB1ENR_CAN1EN_Pos)
     
    #define RCC_APB1ENR_CAN1EN   RCC_APB1ENR_CAN1EN_Msk
     
    #define RCC_APB1ENR_CAN2EN_Pos   (26U)
     
    #define RCC_APB1ENR_CAN2EN_Msk   (0x1UL << RCC_APB1ENR_CAN2EN_Pos)
     
    #define RCC_APB1ENR_CAN2EN   RCC_APB1ENR_CAN2EN_Msk
     
    #define RCC_APB1ENR_PWREN_Pos   (28U)
     
    #define RCC_APB1ENR_PWREN_Msk   (0x1UL << RCC_APB1ENR_PWREN_Pos)
     
    #define RCC_APB1ENR_PWREN   RCC_APB1ENR_PWREN_Msk
     
    #define RCC_APB1ENR_DACEN_Pos   (29U)
     
    #define RCC_APB1ENR_DACEN_Msk   (0x1UL << RCC_APB1ENR_DACEN_Pos)
     
    #define RCC_APB1ENR_DACEN   RCC_APB1ENR_DACEN_Msk
     
    #define RCC_APB2ENR_TIM1EN_Pos   (0U)
     
    #define RCC_APB2ENR_TIM1EN_Msk   (0x1UL << RCC_APB2ENR_TIM1EN_Pos)
     
    #define RCC_APB2ENR_TIM1EN   RCC_APB2ENR_TIM1EN_Msk
     
    #define RCC_APB2ENR_TIM8EN_Pos   (1U)
     
    #define RCC_APB2ENR_TIM8EN_Msk   (0x1UL << RCC_APB2ENR_TIM8EN_Pos)
     
    #define RCC_APB2ENR_TIM8EN   RCC_APB2ENR_TIM8EN_Msk
     
    #define RCC_APB2ENR_USART1EN_Pos   (4U)
     
    #define RCC_APB2ENR_USART1EN_Msk   (0x1UL << RCC_APB2ENR_USART1EN_Pos)
     
    #define RCC_APB2ENR_USART1EN   RCC_APB2ENR_USART1EN_Msk
     
    #define RCC_APB2ENR_USART6EN_Pos   (5U)
     
    #define RCC_APB2ENR_USART6EN_Msk   (0x1UL << RCC_APB2ENR_USART6EN_Pos)
     
    #define RCC_APB2ENR_USART6EN   RCC_APB2ENR_USART6EN_Msk
     
    #define RCC_APB2ENR_ADC1EN_Pos   (8U)
     
    #define RCC_APB2ENR_ADC1EN_Msk   (0x1UL << RCC_APB2ENR_ADC1EN_Pos)
     
    #define RCC_APB2ENR_ADC1EN   RCC_APB2ENR_ADC1EN_Msk
     
    #define RCC_APB2ENR_ADC2EN_Pos   (9U)
     
    #define RCC_APB2ENR_ADC2EN_Msk   (0x1UL << RCC_APB2ENR_ADC2EN_Pos)
     
    #define RCC_APB2ENR_ADC2EN   RCC_APB2ENR_ADC2EN_Msk
     
    #define RCC_APB2ENR_ADC3EN_Pos   (10U)
     
    #define RCC_APB2ENR_ADC3EN_Msk   (0x1UL << RCC_APB2ENR_ADC3EN_Pos)
     
    #define RCC_APB2ENR_ADC3EN   RCC_APB2ENR_ADC3EN_Msk
     
    #define RCC_APB2ENR_SDIOEN_Pos   (11U)
     
    #define RCC_APB2ENR_SDIOEN_Msk   (0x1UL << RCC_APB2ENR_SDIOEN_Pos)
     
    #define RCC_APB2ENR_SDIOEN   RCC_APB2ENR_SDIOEN_Msk
     
    #define RCC_APB2ENR_SPI1EN_Pos   (12U)
     
    #define RCC_APB2ENR_SPI1EN_Msk   (0x1UL << RCC_APB2ENR_SPI1EN_Pos)
     
    #define RCC_APB2ENR_SPI1EN   RCC_APB2ENR_SPI1EN_Msk
     
    #define RCC_APB2ENR_SYSCFGEN_Pos   (14U)
     
    #define RCC_APB2ENR_SYSCFGEN_Msk   (0x1UL << RCC_APB2ENR_SYSCFGEN_Pos)
     
    #define RCC_APB2ENR_SYSCFGEN   RCC_APB2ENR_SYSCFGEN_Msk
     
    #define RCC_APB2ENR_TIM9EN_Pos   (16U)
     
    #define RCC_APB2ENR_TIM9EN_Msk   (0x1UL << RCC_APB2ENR_TIM9EN_Pos)
     
    #define RCC_APB2ENR_TIM9EN   RCC_APB2ENR_TIM9EN_Msk
     
    #define RCC_APB2ENR_TIM10EN_Pos   (17U)
     
    #define RCC_APB2ENR_TIM10EN_Msk   (0x1UL << RCC_APB2ENR_TIM10EN_Pos)
     
    #define RCC_APB2ENR_TIM10EN   RCC_APB2ENR_TIM10EN_Msk
     
    #define RCC_APB2ENR_TIM11EN_Pos   (18U)
     
    #define RCC_APB2ENR_TIM11EN_Msk   (0x1UL << RCC_APB2ENR_TIM11EN_Pos)
     
    #define RCC_APB2ENR_TIM11EN   RCC_APB2ENR_TIM11EN_Msk
     
    #define RCC_AHB1LPENR_GPIOALPEN_Pos   (0U)
     
    #define RCC_AHB1LPENR_GPIOALPEN_Msk   (0x1UL << RCC_AHB1LPENR_GPIOALPEN_Pos)
     
    #define RCC_AHB1LPENR_GPIOALPEN   RCC_AHB1LPENR_GPIOALPEN_Msk
     
    #define RCC_AHB1LPENR_GPIOBLPEN_Pos   (1U)
     
    #define RCC_AHB1LPENR_GPIOBLPEN_Msk   (0x1UL << RCC_AHB1LPENR_GPIOBLPEN_Pos)
     
    #define RCC_AHB1LPENR_GPIOBLPEN   RCC_AHB1LPENR_GPIOBLPEN_Msk
     
    #define RCC_AHB1LPENR_GPIOCLPEN_Pos   (2U)
     
    #define RCC_AHB1LPENR_GPIOCLPEN_Msk   (0x1UL << RCC_AHB1LPENR_GPIOCLPEN_Pos)
     
    #define RCC_AHB1LPENR_GPIOCLPEN   RCC_AHB1LPENR_GPIOCLPEN_Msk
     
    #define RCC_AHB1LPENR_GPIODLPEN_Pos   (3U)
     
    #define RCC_AHB1LPENR_GPIODLPEN_Msk   (0x1UL << RCC_AHB1LPENR_GPIODLPEN_Pos)
     
    #define RCC_AHB1LPENR_GPIODLPEN   RCC_AHB1LPENR_GPIODLPEN_Msk
     
    #define RCC_AHB1LPENR_GPIOELPEN_Pos   (4U)
     
    #define RCC_AHB1LPENR_GPIOELPEN_Msk   (0x1UL << RCC_AHB1LPENR_GPIOELPEN_Pos)
     
    #define RCC_AHB1LPENR_GPIOELPEN   RCC_AHB1LPENR_GPIOELPEN_Msk
     
    #define RCC_AHB1LPENR_GPIOFLPEN_Pos   (5U)
     
    #define RCC_AHB1LPENR_GPIOFLPEN_Msk   (0x1UL << RCC_AHB1LPENR_GPIOFLPEN_Pos)
     
    #define RCC_AHB1LPENR_GPIOFLPEN   RCC_AHB1LPENR_GPIOFLPEN_Msk
     
    #define RCC_AHB1LPENR_GPIOGLPEN_Pos   (6U)
     
    #define RCC_AHB1LPENR_GPIOGLPEN_Msk   (0x1UL << RCC_AHB1LPENR_GPIOGLPEN_Pos)
     
    #define RCC_AHB1LPENR_GPIOGLPEN   RCC_AHB1LPENR_GPIOGLPEN_Msk
     
    #define RCC_AHB1LPENR_GPIOHLPEN_Pos   (7U)
     
    #define RCC_AHB1LPENR_GPIOHLPEN_Msk   (0x1UL << RCC_AHB1LPENR_GPIOHLPEN_Pos)
     
    #define RCC_AHB1LPENR_GPIOHLPEN   RCC_AHB1LPENR_GPIOHLPEN_Msk
     
    #define RCC_AHB1LPENR_GPIOILPEN_Pos   (8U)
     
    #define RCC_AHB1LPENR_GPIOILPEN_Msk   (0x1UL << RCC_AHB1LPENR_GPIOILPEN_Pos)
     
    #define RCC_AHB1LPENR_GPIOILPEN   RCC_AHB1LPENR_GPIOILPEN_Msk
     
    #define RCC_AHB1LPENR_CRCLPEN_Pos   (12U)
     
    #define RCC_AHB1LPENR_CRCLPEN_Msk   (0x1UL << RCC_AHB1LPENR_CRCLPEN_Pos)
     
    #define RCC_AHB1LPENR_CRCLPEN   RCC_AHB1LPENR_CRCLPEN_Msk
     
    #define RCC_AHB1LPENR_FLITFLPEN_Pos   (15U)
     
    #define RCC_AHB1LPENR_FLITFLPEN_Msk   (0x1UL << RCC_AHB1LPENR_FLITFLPEN_Pos)
     
    #define RCC_AHB1LPENR_FLITFLPEN   RCC_AHB1LPENR_FLITFLPEN_Msk
     
    #define RCC_AHB1LPENR_SRAM1LPEN_Pos   (16U)
     
    #define RCC_AHB1LPENR_SRAM1LPEN_Msk   (0x1UL << RCC_AHB1LPENR_SRAM1LPEN_Pos)
     
    #define RCC_AHB1LPENR_SRAM1LPEN   RCC_AHB1LPENR_SRAM1LPEN_Msk
     
    #define RCC_AHB1LPENR_SRAM2LPEN_Pos   (17U)
     
    #define RCC_AHB1LPENR_SRAM2LPEN_Msk   (0x1UL << RCC_AHB1LPENR_SRAM2LPEN_Pos)
     
    #define RCC_AHB1LPENR_SRAM2LPEN   RCC_AHB1LPENR_SRAM2LPEN_Msk
     
    #define RCC_AHB1LPENR_BKPSRAMLPEN_Pos   (18U)
     
    #define RCC_AHB1LPENR_BKPSRAMLPEN_Msk   (0x1UL << RCC_AHB1LPENR_BKPSRAMLPEN_Pos)
     
    #define RCC_AHB1LPENR_BKPSRAMLPEN   RCC_AHB1LPENR_BKPSRAMLPEN_Msk
     
    #define RCC_AHB1LPENR_DMA1LPEN_Pos   (21U)
     
    #define RCC_AHB1LPENR_DMA1LPEN_Msk   (0x1UL << RCC_AHB1LPENR_DMA1LPEN_Pos)
     
    #define RCC_AHB1LPENR_DMA1LPEN   RCC_AHB1LPENR_DMA1LPEN_Msk
     
    #define RCC_AHB1LPENR_DMA2LPEN_Pos   (22U)
     
    #define RCC_AHB1LPENR_DMA2LPEN_Msk   (0x1UL << RCC_AHB1LPENR_DMA2LPEN_Pos)
     
    #define RCC_AHB1LPENR_DMA2LPEN   RCC_AHB1LPENR_DMA2LPEN_Msk
     
    #define RCC_AHB1LPENR_ETHMACLPEN_Pos   (25U)
     
    #define RCC_AHB1LPENR_ETHMACLPEN_Msk   (0x1UL << RCC_AHB1LPENR_ETHMACLPEN_Pos)
     
    #define RCC_AHB1LPENR_ETHMACLPEN   RCC_AHB1LPENR_ETHMACLPEN_Msk
     
    #define RCC_AHB1LPENR_ETHMACTXLPEN_Pos   (26U)
     
    #define RCC_AHB1LPENR_ETHMACTXLPEN_Msk   (0x1UL << RCC_AHB1LPENR_ETHMACTXLPEN_Pos)
     
    #define RCC_AHB1LPENR_ETHMACTXLPEN   RCC_AHB1LPENR_ETHMACTXLPEN_Msk
     
    #define RCC_AHB1LPENR_ETHMACRXLPEN_Pos   (27U)
     
    #define RCC_AHB1LPENR_ETHMACRXLPEN_Msk   (0x1UL << RCC_AHB1LPENR_ETHMACRXLPEN_Pos)
     
    #define RCC_AHB1LPENR_ETHMACRXLPEN   RCC_AHB1LPENR_ETHMACRXLPEN_Msk
     
    #define RCC_AHB1LPENR_ETHMACPTPLPEN_Pos   (28U)
     
    #define RCC_AHB1LPENR_ETHMACPTPLPEN_Msk   (0x1UL << RCC_AHB1LPENR_ETHMACPTPLPEN_Pos)
     
    #define RCC_AHB1LPENR_ETHMACPTPLPEN   RCC_AHB1LPENR_ETHMACPTPLPEN_Msk
     
    #define RCC_AHB1LPENR_OTGHSLPEN_Pos   (29U)
     
    #define RCC_AHB1LPENR_OTGHSLPEN_Msk   (0x1UL << RCC_AHB1LPENR_OTGHSLPEN_Pos)
     
    #define RCC_AHB1LPENR_OTGHSLPEN   RCC_AHB1LPENR_OTGHSLPEN_Msk
     
    #define RCC_AHB1LPENR_OTGHSULPILPEN_Pos   (30U)
     
    #define RCC_AHB1LPENR_OTGHSULPILPEN_Msk   (0x1UL << RCC_AHB1LPENR_OTGHSULPILPEN_Pos)
     
    #define RCC_AHB1LPENR_OTGHSULPILPEN   RCC_AHB1LPENR_OTGHSULPILPEN_Msk
     
    #define RCC_AHB2LPENR_DCMILPEN_Pos   (0U)
     
    #define RCC_AHB2LPENR_DCMILPEN_Msk   (0x1UL << RCC_AHB2LPENR_DCMILPEN_Pos)
     
    #define RCC_AHB2LPENR_DCMILPEN   RCC_AHB2LPENR_DCMILPEN_Msk
     
    #define RCC_AHB2LPENR_RNGLPEN_Pos   (6U)
     
    #define RCC_AHB2LPENR_RNGLPEN_Msk   (0x1UL << RCC_AHB2LPENR_RNGLPEN_Pos)
     
    #define RCC_AHB2LPENR_RNGLPEN   RCC_AHB2LPENR_RNGLPEN_Msk
     
    #define RCC_AHB2LPENR_OTGFSLPEN_Pos   (7U)
     
    #define RCC_AHB2LPENR_OTGFSLPEN_Msk   (0x1UL << RCC_AHB2LPENR_OTGFSLPEN_Pos)
     
    #define RCC_AHB2LPENR_OTGFSLPEN   RCC_AHB2LPENR_OTGFSLPEN_Msk
     
    #define RCC_AHB3LPENR_FSMCLPEN_Pos   (0U)
     
    #define RCC_AHB3LPENR_FSMCLPEN_Msk   (0x1UL << RCC_AHB3LPENR_FSMCLPEN_Pos)
     
    #define RCC_AHB3LPENR_FSMCLPEN   RCC_AHB3LPENR_FSMCLPEN_Msk
     
    #define RCC_APB1LPENR_TIM2LPEN_Pos   (0U)
     
    #define RCC_APB1LPENR_TIM2LPEN_Msk   (0x1UL << RCC_APB1LPENR_TIM2LPEN_Pos)
     
    #define RCC_APB1LPENR_TIM2LPEN   RCC_APB1LPENR_TIM2LPEN_Msk
     
    #define RCC_APB1LPENR_TIM3LPEN_Pos   (1U)
     
    #define RCC_APB1LPENR_TIM3LPEN_Msk   (0x1UL << RCC_APB1LPENR_TIM3LPEN_Pos)
     
    #define RCC_APB1LPENR_TIM3LPEN   RCC_APB1LPENR_TIM3LPEN_Msk
     
    #define RCC_APB1LPENR_TIM4LPEN_Pos   (2U)
     
    #define RCC_APB1LPENR_TIM4LPEN_Msk   (0x1UL << RCC_APB1LPENR_TIM4LPEN_Pos)
     
    #define RCC_APB1LPENR_TIM4LPEN   RCC_APB1LPENR_TIM4LPEN_Msk
     
    #define RCC_APB1LPENR_TIM5LPEN_Pos   (3U)
     
    #define RCC_APB1LPENR_TIM5LPEN_Msk   (0x1UL << RCC_APB1LPENR_TIM5LPEN_Pos)
     
    #define RCC_APB1LPENR_TIM5LPEN   RCC_APB1LPENR_TIM5LPEN_Msk
     
    #define RCC_APB1LPENR_TIM6LPEN_Pos   (4U)
     
    #define RCC_APB1LPENR_TIM6LPEN_Msk   (0x1UL << RCC_APB1LPENR_TIM6LPEN_Pos)
     
    #define RCC_APB1LPENR_TIM6LPEN   RCC_APB1LPENR_TIM6LPEN_Msk
     
    #define RCC_APB1LPENR_TIM7LPEN_Pos   (5U)
     
    #define RCC_APB1LPENR_TIM7LPEN_Msk   (0x1UL << RCC_APB1LPENR_TIM7LPEN_Pos)
     
    #define RCC_APB1LPENR_TIM7LPEN   RCC_APB1LPENR_TIM7LPEN_Msk
     
    #define RCC_APB1LPENR_TIM12LPEN_Pos   (6U)
     
    #define RCC_APB1LPENR_TIM12LPEN_Msk   (0x1UL << RCC_APB1LPENR_TIM12LPEN_Pos)
     
    #define RCC_APB1LPENR_TIM12LPEN   RCC_APB1LPENR_TIM12LPEN_Msk
     
    #define RCC_APB1LPENR_TIM13LPEN_Pos   (7U)
     
    #define RCC_APB1LPENR_TIM13LPEN_Msk   (0x1UL << RCC_APB1LPENR_TIM13LPEN_Pos)
     
    #define RCC_APB1LPENR_TIM13LPEN   RCC_APB1LPENR_TIM13LPEN_Msk
     
    #define RCC_APB1LPENR_TIM14LPEN_Pos   (8U)
     
    #define RCC_APB1LPENR_TIM14LPEN_Msk   (0x1UL << RCC_APB1LPENR_TIM14LPEN_Pos)
     
    #define RCC_APB1LPENR_TIM14LPEN   RCC_APB1LPENR_TIM14LPEN_Msk
     
    #define RCC_APB1LPENR_WWDGLPEN_Pos   (11U)
     
    #define RCC_APB1LPENR_WWDGLPEN_Msk   (0x1UL << RCC_APB1LPENR_WWDGLPEN_Pos)
     
    #define RCC_APB1LPENR_WWDGLPEN   RCC_APB1LPENR_WWDGLPEN_Msk
     
    #define RCC_APB1LPENR_SPI2LPEN_Pos   (14U)
     
    #define RCC_APB1LPENR_SPI2LPEN_Msk   (0x1UL << RCC_APB1LPENR_SPI2LPEN_Pos)
     
    #define RCC_APB1LPENR_SPI2LPEN   RCC_APB1LPENR_SPI2LPEN_Msk
     
    #define RCC_APB1LPENR_SPI3LPEN_Pos   (15U)
     
    #define RCC_APB1LPENR_SPI3LPEN_Msk   (0x1UL << RCC_APB1LPENR_SPI3LPEN_Pos)
     
    #define RCC_APB1LPENR_SPI3LPEN   RCC_APB1LPENR_SPI3LPEN_Msk
     
    #define RCC_APB1LPENR_USART2LPEN_Pos   (17U)
     
    #define RCC_APB1LPENR_USART2LPEN_Msk   (0x1UL << RCC_APB1LPENR_USART2LPEN_Pos)
     
    #define RCC_APB1LPENR_USART2LPEN   RCC_APB1LPENR_USART2LPEN_Msk
     
    #define RCC_APB1LPENR_USART3LPEN_Pos   (18U)
     
    #define RCC_APB1LPENR_USART3LPEN_Msk   (0x1UL << RCC_APB1LPENR_USART3LPEN_Pos)
     
    #define RCC_APB1LPENR_USART3LPEN   RCC_APB1LPENR_USART3LPEN_Msk
     
    #define RCC_APB1LPENR_UART4LPEN_Pos   (19U)
     
    #define RCC_APB1LPENR_UART4LPEN_Msk   (0x1UL << RCC_APB1LPENR_UART4LPEN_Pos)
     
    #define RCC_APB1LPENR_UART4LPEN   RCC_APB1LPENR_UART4LPEN_Msk
     
    #define RCC_APB1LPENR_UART5LPEN_Pos   (20U)
     
    #define RCC_APB1LPENR_UART5LPEN_Msk   (0x1UL << RCC_APB1LPENR_UART5LPEN_Pos)
     
    #define RCC_APB1LPENR_UART5LPEN   RCC_APB1LPENR_UART5LPEN_Msk
     
    #define RCC_APB1LPENR_I2C1LPEN_Pos   (21U)
     
    #define RCC_APB1LPENR_I2C1LPEN_Msk   (0x1UL << RCC_APB1LPENR_I2C1LPEN_Pos)
     
    #define RCC_APB1LPENR_I2C1LPEN   RCC_APB1LPENR_I2C1LPEN_Msk
     
    #define RCC_APB1LPENR_I2C2LPEN_Pos   (22U)
     
    #define RCC_APB1LPENR_I2C2LPEN_Msk   (0x1UL << RCC_APB1LPENR_I2C2LPEN_Pos)
     
    #define RCC_APB1LPENR_I2C2LPEN   RCC_APB1LPENR_I2C2LPEN_Msk
     
    #define RCC_APB1LPENR_I2C3LPEN_Pos   (23U)
     
    #define RCC_APB1LPENR_I2C3LPEN_Msk   (0x1UL << RCC_APB1LPENR_I2C3LPEN_Pos)
     
    #define RCC_APB1LPENR_I2C3LPEN   RCC_APB1LPENR_I2C3LPEN_Msk
     
    #define RCC_APB1LPENR_CAN1LPEN_Pos   (25U)
     
    #define RCC_APB1LPENR_CAN1LPEN_Msk   (0x1UL << RCC_APB1LPENR_CAN1LPEN_Pos)
     
    #define RCC_APB1LPENR_CAN1LPEN   RCC_APB1LPENR_CAN1LPEN_Msk
     
    #define RCC_APB1LPENR_CAN2LPEN_Pos   (26U)
     
    #define RCC_APB1LPENR_CAN2LPEN_Msk   (0x1UL << RCC_APB1LPENR_CAN2LPEN_Pos)
     
    #define RCC_APB1LPENR_CAN2LPEN   RCC_APB1LPENR_CAN2LPEN_Msk
     
    #define RCC_APB1LPENR_PWRLPEN_Pos   (28U)
     
    #define RCC_APB1LPENR_PWRLPEN_Msk   (0x1UL << RCC_APB1LPENR_PWRLPEN_Pos)
     
    #define RCC_APB1LPENR_PWRLPEN   RCC_APB1LPENR_PWRLPEN_Msk
     
    #define RCC_APB1LPENR_DACLPEN_Pos   (29U)
     
    #define RCC_APB1LPENR_DACLPEN_Msk   (0x1UL << RCC_APB1LPENR_DACLPEN_Pos)
     
    #define RCC_APB1LPENR_DACLPEN   RCC_APB1LPENR_DACLPEN_Msk
     
    #define RCC_APB2LPENR_TIM1LPEN_Pos   (0U)
     
    #define RCC_APB2LPENR_TIM1LPEN_Msk   (0x1UL << RCC_APB2LPENR_TIM1LPEN_Pos)
     
    #define RCC_APB2LPENR_TIM1LPEN   RCC_APB2LPENR_TIM1LPEN_Msk
     
    #define RCC_APB2LPENR_TIM8LPEN_Pos   (1U)
     
    #define RCC_APB2LPENR_TIM8LPEN_Msk   (0x1UL << RCC_APB2LPENR_TIM8LPEN_Pos)
     
    #define RCC_APB2LPENR_TIM8LPEN   RCC_APB2LPENR_TIM8LPEN_Msk
     
    #define RCC_APB2LPENR_USART1LPEN_Pos   (4U)
     
    #define RCC_APB2LPENR_USART1LPEN_Msk   (0x1UL << RCC_APB2LPENR_USART1LPEN_Pos)
     
    #define RCC_APB2LPENR_USART1LPEN   RCC_APB2LPENR_USART1LPEN_Msk
     
    #define RCC_APB2LPENR_USART6LPEN_Pos   (5U)
     
    #define RCC_APB2LPENR_USART6LPEN_Msk   (0x1UL << RCC_APB2LPENR_USART6LPEN_Pos)
     
    #define RCC_APB2LPENR_USART6LPEN   RCC_APB2LPENR_USART6LPEN_Msk
     
    #define RCC_APB2LPENR_ADC1LPEN_Pos   (8U)
     
    #define RCC_APB2LPENR_ADC1LPEN_Msk   (0x1UL << RCC_APB2LPENR_ADC1LPEN_Pos)
     
    #define RCC_APB2LPENR_ADC1LPEN   RCC_APB2LPENR_ADC1LPEN_Msk
     
    #define RCC_APB2LPENR_ADC2LPEN_Pos   (9U)
     
    #define RCC_APB2LPENR_ADC2LPEN_Msk   (0x1UL << RCC_APB2LPENR_ADC2LPEN_Pos)
     
    #define RCC_APB2LPENR_ADC2LPEN   RCC_APB2LPENR_ADC2LPEN_Msk
     
    #define RCC_APB2LPENR_ADC3LPEN_Pos   (10U)
     
    #define RCC_APB2LPENR_ADC3LPEN_Msk   (0x1UL << RCC_APB2LPENR_ADC3LPEN_Pos)
     
    #define RCC_APB2LPENR_ADC3LPEN   RCC_APB2LPENR_ADC3LPEN_Msk
     
    #define RCC_APB2LPENR_SDIOLPEN_Pos   (11U)
     
    #define RCC_APB2LPENR_SDIOLPEN_Msk   (0x1UL << RCC_APB2LPENR_SDIOLPEN_Pos)
     
    #define RCC_APB2LPENR_SDIOLPEN   RCC_APB2LPENR_SDIOLPEN_Msk
     
    #define RCC_APB2LPENR_SPI1LPEN_Pos   (12U)
     
    #define RCC_APB2LPENR_SPI1LPEN_Msk   (0x1UL << RCC_APB2LPENR_SPI1LPEN_Pos)
     
    #define RCC_APB2LPENR_SPI1LPEN   RCC_APB2LPENR_SPI1LPEN_Msk
     
    #define RCC_APB2LPENR_SYSCFGLPEN_Pos   (14U)
     
    #define RCC_APB2LPENR_SYSCFGLPEN_Msk   (0x1UL << RCC_APB2LPENR_SYSCFGLPEN_Pos)
     
    #define RCC_APB2LPENR_SYSCFGLPEN   RCC_APB2LPENR_SYSCFGLPEN_Msk
     
    #define RCC_APB2LPENR_TIM9LPEN_Pos   (16U)
     
    #define RCC_APB2LPENR_TIM9LPEN_Msk   (0x1UL << RCC_APB2LPENR_TIM9LPEN_Pos)
     
    #define RCC_APB2LPENR_TIM9LPEN   RCC_APB2LPENR_TIM9LPEN_Msk
     
    #define RCC_APB2LPENR_TIM10LPEN_Pos   (17U)
     
    #define RCC_APB2LPENR_TIM10LPEN_Msk   (0x1UL << RCC_APB2LPENR_TIM10LPEN_Pos)
     
    #define RCC_APB2LPENR_TIM10LPEN   RCC_APB2LPENR_TIM10LPEN_Msk
     
    #define RCC_APB2LPENR_TIM11LPEN_Pos   (18U)
     
    #define RCC_APB2LPENR_TIM11LPEN_Msk   (0x1UL << RCC_APB2LPENR_TIM11LPEN_Pos)
     
    #define RCC_APB2LPENR_TIM11LPEN   RCC_APB2LPENR_TIM11LPEN_Msk
     
    #define RCC_BDCR_LSEON_Pos   (0U)
     
    #define RCC_BDCR_LSEON_Msk   (0x1UL << RCC_BDCR_LSEON_Pos)
     
    #define RCC_BDCR_LSEON   RCC_BDCR_LSEON_Msk
     
    #define RCC_BDCR_LSERDY_Pos   (1U)
     
    #define RCC_BDCR_LSERDY_Msk   (0x1UL << RCC_BDCR_LSERDY_Pos)
     
    #define RCC_BDCR_LSERDY   RCC_BDCR_LSERDY_Msk
     
    #define RCC_BDCR_LSEBYP_Pos   (2U)
     
    #define RCC_BDCR_LSEBYP_Msk   (0x1UL << RCC_BDCR_LSEBYP_Pos)
     
    #define RCC_BDCR_LSEBYP   RCC_BDCR_LSEBYP_Msk
     
    #define RCC_BDCR_RTCSEL_Pos   (8U)
     
    #define RCC_BDCR_RTCSEL_Msk   (0x3UL << RCC_BDCR_RTCSEL_Pos)
     
    #define RCC_BDCR_RTCSEL   RCC_BDCR_RTCSEL_Msk
     
    #define RCC_BDCR_RTCSEL_0   (0x1UL << RCC_BDCR_RTCSEL_Pos)
     
    #define RCC_BDCR_RTCSEL_1   (0x2UL << RCC_BDCR_RTCSEL_Pos)
     
    #define RCC_BDCR_RTCEN_Pos   (15U)
     
    #define RCC_BDCR_RTCEN_Msk   (0x1UL << RCC_BDCR_RTCEN_Pos)
     
    #define RCC_BDCR_RTCEN   RCC_BDCR_RTCEN_Msk
     
    #define RCC_BDCR_BDRST_Pos   (16U)
     
    #define RCC_BDCR_BDRST_Msk   (0x1UL << RCC_BDCR_BDRST_Pos)
     
    #define RCC_BDCR_BDRST   RCC_BDCR_BDRST_Msk
     
    #define RCC_CSR_LSION_Pos   (0U)
     
    #define RCC_CSR_LSION_Msk   (0x1UL << RCC_CSR_LSION_Pos)
     
    #define RCC_CSR_LSION   RCC_CSR_LSION_Msk
     
    #define RCC_CSR_LSIRDY_Pos   (1U)
     
    #define RCC_CSR_LSIRDY_Msk   (0x1UL << RCC_CSR_LSIRDY_Pos)
     
    #define RCC_CSR_LSIRDY   RCC_CSR_LSIRDY_Msk
     
    #define RCC_CSR_RMVF_Pos   (24U)
     
    #define RCC_CSR_RMVF_Msk   (0x1UL << RCC_CSR_RMVF_Pos)
     
    #define RCC_CSR_RMVF   RCC_CSR_RMVF_Msk
     
    #define RCC_CSR_BORRSTF_Pos   (25U)
     
    #define RCC_CSR_BORRSTF_Msk   (0x1UL << RCC_CSR_BORRSTF_Pos)
     
    #define RCC_CSR_BORRSTF   RCC_CSR_BORRSTF_Msk
     
    #define RCC_CSR_PINRSTF_Pos   (26U)
     
    #define RCC_CSR_PINRSTF_Msk   (0x1UL << RCC_CSR_PINRSTF_Pos)
     
    #define RCC_CSR_PINRSTF   RCC_CSR_PINRSTF_Msk
     
    #define RCC_CSR_PORRSTF_Pos   (27U)
     
    #define RCC_CSR_PORRSTF_Msk   (0x1UL << RCC_CSR_PORRSTF_Pos)
     
    #define RCC_CSR_PORRSTF   RCC_CSR_PORRSTF_Msk
     
    #define RCC_CSR_SFTRSTF_Pos   (28U)
     
    #define RCC_CSR_SFTRSTF_Msk   (0x1UL << RCC_CSR_SFTRSTF_Pos)
     
    #define RCC_CSR_SFTRSTF   RCC_CSR_SFTRSTF_Msk
     
    #define RCC_CSR_IWDGRSTF_Pos   (29U)
     
    #define RCC_CSR_IWDGRSTF_Msk   (0x1UL << RCC_CSR_IWDGRSTF_Pos)
     
    #define RCC_CSR_IWDGRSTF   RCC_CSR_IWDGRSTF_Msk
     
    #define RCC_CSR_WWDGRSTF_Pos   (30U)
     
    #define RCC_CSR_WWDGRSTF_Msk   (0x1UL << RCC_CSR_WWDGRSTF_Pos)
     
    #define RCC_CSR_WWDGRSTF   RCC_CSR_WWDGRSTF_Msk
     
    #define RCC_CSR_LPWRRSTF_Pos   (31U)
     
    #define RCC_CSR_LPWRRSTF_Msk   (0x1UL << RCC_CSR_LPWRRSTF_Pos)
     
    #define RCC_CSR_LPWRRSTF   RCC_CSR_LPWRRSTF_Msk
     
    #define RCC_CSR_PADRSTF   RCC_CSR_PINRSTF
     
    #define RCC_CSR_WDGRSTF   RCC_CSR_IWDGRSTF
     
    #define RCC_SSCGR_MODPER_Pos   (0U)
     
    #define RCC_SSCGR_MODPER_Msk   (0x1FFFUL << RCC_SSCGR_MODPER_Pos)
     
    #define RCC_SSCGR_MODPER   RCC_SSCGR_MODPER_Msk
     
    #define RCC_SSCGR_INCSTEP_Pos   (13U)
     
    #define RCC_SSCGR_INCSTEP_Msk   (0x7FFFUL << RCC_SSCGR_INCSTEP_Pos)
     
    #define RCC_SSCGR_INCSTEP   RCC_SSCGR_INCSTEP_Msk
     
    #define RCC_SSCGR_SPREADSEL_Pos   (30U)
     
    #define RCC_SSCGR_SPREADSEL_Msk   (0x1UL << RCC_SSCGR_SPREADSEL_Pos)
     
    #define RCC_SSCGR_SPREADSEL   RCC_SSCGR_SPREADSEL_Msk
     
    #define RCC_SSCGR_SSCGEN_Pos   (31U)
     
    #define RCC_SSCGR_SSCGEN_Msk   (0x1UL << RCC_SSCGR_SSCGEN_Pos)
     
    #define RCC_SSCGR_SSCGEN   RCC_SSCGR_SSCGEN_Msk
     
    #define RCC_PLLI2SCFGR_PLLI2SN_Pos   (6U)
     
    #define RCC_PLLI2SCFGR_PLLI2SN_Msk   (0x1FFUL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
     
    #define RCC_PLLI2SCFGR_PLLI2SN   RCC_PLLI2SCFGR_PLLI2SN_Msk
     
    #define RCC_PLLI2SCFGR_PLLI2SN_0   (0x001UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
     
    #define RCC_PLLI2SCFGR_PLLI2SN_1   (0x002UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
     
    #define RCC_PLLI2SCFGR_PLLI2SN_2   (0x004UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
     
    #define RCC_PLLI2SCFGR_PLLI2SN_3   (0x008UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
     
    #define RCC_PLLI2SCFGR_PLLI2SN_4   (0x010UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
     
    #define RCC_PLLI2SCFGR_PLLI2SN_5   (0x020UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
     
    #define RCC_PLLI2SCFGR_PLLI2SN_6   (0x040UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
     
    #define RCC_PLLI2SCFGR_PLLI2SN_7   (0x080UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
     
    #define RCC_PLLI2SCFGR_PLLI2SN_8   (0x100UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
     
    #define RCC_PLLI2SCFGR_PLLI2SR_Pos   (28U)
     
    #define RCC_PLLI2SCFGR_PLLI2SR_Msk   (0x7UL << RCC_PLLI2SCFGR_PLLI2SR_Pos)
     
    #define RCC_PLLI2SCFGR_PLLI2SR   RCC_PLLI2SCFGR_PLLI2SR_Msk
     
    #define RCC_PLLI2SCFGR_PLLI2SR_0   (0x1UL << RCC_PLLI2SCFGR_PLLI2SR_Pos)
     
    #define RCC_PLLI2SCFGR_PLLI2SR_1   (0x2UL << RCC_PLLI2SCFGR_PLLI2SR_Pos)
     
    #define RCC_PLLI2SCFGR_PLLI2SR_2   (0x4UL << RCC_PLLI2SCFGR_PLLI2SR_Pos)
     
    #define RNG_CR_RNGEN_Pos   (2U)
     
    #define RNG_CR_RNGEN_Msk   (0x1UL << RNG_CR_RNGEN_Pos)
     
    #define RNG_CR_RNGEN   RNG_CR_RNGEN_Msk
     
    #define RNG_CR_IE_Pos   (3U)
     
    #define RNG_CR_IE_Msk   (0x1UL << RNG_CR_IE_Pos)
     
    #define RNG_CR_IE   RNG_CR_IE_Msk
     
    #define RNG_SR_DRDY_Pos   (0U)
     
    #define RNG_SR_DRDY_Msk   (0x1UL << RNG_SR_DRDY_Pos)
     
    #define RNG_SR_DRDY   RNG_SR_DRDY_Msk
     
    #define RNG_SR_CECS_Pos   (1U)
     
    #define RNG_SR_CECS_Msk   (0x1UL << RNG_SR_CECS_Pos)
     
    #define RNG_SR_CECS   RNG_SR_CECS_Msk
     
    #define RNG_SR_SECS_Pos   (2U)
     
    #define RNG_SR_SECS_Msk   (0x1UL << RNG_SR_SECS_Pos)
     
    #define RNG_SR_SECS   RNG_SR_SECS_Msk
     
    #define RNG_SR_CEIS_Pos   (5U)
     
    #define RNG_SR_CEIS_Msk   (0x1UL << RNG_SR_CEIS_Pos)
     
    #define RNG_SR_CEIS   RNG_SR_CEIS_Msk
     
    #define RNG_SR_SEIS_Pos   (6U)
     
    #define RNG_SR_SEIS_Msk   (0x1UL << RNG_SR_SEIS_Pos)
     
    #define RNG_SR_SEIS   RNG_SR_SEIS_Msk
     
    #define RTC_TAMPER2_SUPPORT
     
    #define RTC_AF2_SUPPORT
     
    #define RTC_TR_PM_Pos   (22U)
     
    #define RTC_TR_PM_Msk   (0x1UL << RTC_TR_PM_Pos)
     
    #define RTC_TR_PM   RTC_TR_PM_Msk
     
    #define RTC_TR_HT_Pos   (20U)
     
    #define RTC_TR_HT_Msk   (0x3UL << RTC_TR_HT_Pos)
     
    #define RTC_TR_HT   RTC_TR_HT_Msk
     
    #define RTC_TR_HT_0   (0x1UL << RTC_TR_HT_Pos)
     
    #define RTC_TR_HT_1   (0x2UL << RTC_TR_HT_Pos)
     
    #define RTC_TR_HU_Pos   (16U)
     
    #define RTC_TR_HU_Msk   (0xFUL << RTC_TR_HU_Pos)
     
    #define RTC_TR_HU   RTC_TR_HU_Msk
     
    #define RTC_TR_HU_0   (0x1UL << RTC_TR_HU_Pos)
     
    #define RTC_TR_HU_1   (0x2UL << RTC_TR_HU_Pos)
     
    #define RTC_TR_HU_2   (0x4UL << RTC_TR_HU_Pos)
     
    #define RTC_TR_HU_3   (0x8UL << RTC_TR_HU_Pos)
     
    #define RTC_TR_MNT_Pos   (12U)
     
    #define RTC_TR_MNT_Msk   (0x7UL << RTC_TR_MNT_Pos)
     
    #define RTC_TR_MNT   RTC_TR_MNT_Msk
     
    #define RTC_TR_MNT_0   (0x1UL << RTC_TR_MNT_Pos)
     
    #define RTC_TR_MNT_1   (0x2UL << RTC_TR_MNT_Pos)
     
    #define RTC_TR_MNT_2   (0x4UL << RTC_TR_MNT_Pos)
     
    #define RTC_TR_MNU_Pos   (8U)
     
    #define RTC_TR_MNU_Msk   (0xFUL << RTC_TR_MNU_Pos)
     
    #define RTC_TR_MNU   RTC_TR_MNU_Msk
     
    #define RTC_TR_MNU_0   (0x1UL << RTC_TR_MNU_Pos)
     
    #define RTC_TR_MNU_1   (0x2UL << RTC_TR_MNU_Pos)
     
    #define RTC_TR_MNU_2   (0x4UL << RTC_TR_MNU_Pos)
     
    #define RTC_TR_MNU_3   (0x8UL << RTC_TR_MNU_Pos)
     
    #define RTC_TR_ST_Pos   (4U)
     
    #define RTC_TR_ST_Msk   (0x7UL << RTC_TR_ST_Pos)
     
    #define RTC_TR_ST   RTC_TR_ST_Msk
     
    #define RTC_TR_ST_0   (0x1UL << RTC_TR_ST_Pos)
     
    #define RTC_TR_ST_1   (0x2UL << RTC_TR_ST_Pos)
     
    #define RTC_TR_ST_2   (0x4UL << RTC_TR_ST_Pos)
     
    #define RTC_TR_SU_Pos   (0U)
     
    #define RTC_TR_SU_Msk   (0xFUL << RTC_TR_SU_Pos)
     
    #define RTC_TR_SU   RTC_TR_SU_Msk
     
    #define RTC_TR_SU_0   (0x1UL << RTC_TR_SU_Pos)
     
    #define RTC_TR_SU_1   (0x2UL << RTC_TR_SU_Pos)
     
    #define RTC_TR_SU_2   (0x4UL << RTC_TR_SU_Pos)
     
    #define RTC_TR_SU_3   (0x8UL << RTC_TR_SU_Pos)
     
    #define RTC_DR_YT_Pos   (20U)
     
    #define RTC_DR_YT_Msk   (0xFUL << RTC_DR_YT_Pos)
     
    #define RTC_DR_YT   RTC_DR_YT_Msk
     
    #define RTC_DR_YT_0   (0x1UL << RTC_DR_YT_Pos)
     
    #define RTC_DR_YT_1   (0x2UL << RTC_DR_YT_Pos)
     
    #define RTC_DR_YT_2   (0x4UL << RTC_DR_YT_Pos)
     
    #define RTC_DR_YT_3   (0x8UL << RTC_DR_YT_Pos)
     
    #define RTC_DR_YU_Pos   (16U)
     
    #define RTC_DR_YU_Msk   (0xFUL << RTC_DR_YU_Pos)
     
    #define RTC_DR_YU   RTC_DR_YU_Msk
     
    #define RTC_DR_YU_0   (0x1UL << RTC_DR_YU_Pos)
     
    #define RTC_DR_YU_1   (0x2UL << RTC_DR_YU_Pos)
     
    #define RTC_DR_YU_2   (0x4UL << RTC_DR_YU_Pos)
     
    #define RTC_DR_YU_3   (0x8UL << RTC_DR_YU_Pos)
     
    #define RTC_DR_WDU_Pos   (13U)
     
    #define RTC_DR_WDU_Msk   (0x7UL << RTC_DR_WDU_Pos)
     
    #define RTC_DR_WDU   RTC_DR_WDU_Msk
     
    #define RTC_DR_WDU_0   (0x1UL << RTC_DR_WDU_Pos)
     
    #define RTC_DR_WDU_1   (0x2UL << RTC_DR_WDU_Pos)
     
    #define RTC_DR_WDU_2   (0x4UL << RTC_DR_WDU_Pos)
     
    #define RTC_DR_MT_Pos   (12U)
     
    #define RTC_DR_MT_Msk   (0x1UL << RTC_DR_MT_Pos)
     
    #define RTC_DR_MT   RTC_DR_MT_Msk
     
    #define RTC_DR_MU_Pos   (8U)
     
    #define RTC_DR_MU_Msk   (0xFUL << RTC_DR_MU_Pos)
     
    #define RTC_DR_MU   RTC_DR_MU_Msk
     
    #define RTC_DR_MU_0   (0x1UL << RTC_DR_MU_Pos)
     
    #define RTC_DR_MU_1   (0x2UL << RTC_DR_MU_Pos)
     
    #define RTC_DR_MU_2   (0x4UL << RTC_DR_MU_Pos)
     
    #define RTC_DR_MU_3   (0x8UL << RTC_DR_MU_Pos)
     
    #define RTC_DR_DT_Pos   (4U)
     
    #define RTC_DR_DT_Msk   (0x3UL << RTC_DR_DT_Pos)
     
    #define RTC_DR_DT   RTC_DR_DT_Msk
     
    #define RTC_DR_DT_0   (0x1UL << RTC_DR_DT_Pos)
     
    #define RTC_DR_DT_1   (0x2UL << RTC_DR_DT_Pos)
     
    #define RTC_DR_DU_Pos   (0U)
     
    #define RTC_DR_DU_Msk   (0xFUL << RTC_DR_DU_Pos)
     
    #define RTC_DR_DU   RTC_DR_DU_Msk
     
    #define RTC_DR_DU_0   (0x1UL << RTC_DR_DU_Pos)
     
    #define RTC_DR_DU_1   (0x2UL << RTC_DR_DU_Pos)
     
    #define RTC_DR_DU_2   (0x4UL << RTC_DR_DU_Pos)
     
    #define RTC_DR_DU_3   (0x8UL << RTC_DR_DU_Pos)
     
    #define RTC_CR_COE_Pos   (23U)
     
    #define RTC_CR_COE_Msk   (0x1UL << RTC_CR_COE_Pos)
     
    #define RTC_CR_COE   RTC_CR_COE_Msk
     
    #define RTC_CR_OSEL_Pos   (21U)
     
    #define RTC_CR_OSEL_Msk   (0x3UL << RTC_CR_OSEL_Pos)
     
    #define RTC_CR_OSEL   RTC_CR_OSEL_Msk
     
    #define RTC_CR_OSEL_0   (0x1UL << RTC_CR_OSEL_Pos)
     
    #define RTC_CR_OSEL_1   (0x2UL << RTC_CR_OSEL_Pos)
     
    #define RTC_CR_POL_Pos   (20U)
     
    #define RTC_CR_POL_Msk   (0x1UL << RTC_CR_POL_Pos)
     
    #define RTC_CR_POL   RTC_CR_POL_Msk
     
    #define RTC_CR_COSEL_Pos   (19U)
     
    #define RTC_CR_COSEL_Msk   (0x1UL << RTC_CR_COSEL_Pos)
     
    #define RTC_CR_COSEL   RTC_CR_COSEL_Msk
     
    #define RTC_CR_BKP_Pos   (18U)
     
    #define RTC_CR_BKP_Msk   (0x1UL << RTC_CR_BKP_Pos)
     
    #define RTC_CR_BKP   RTC_CR_BKP_Msk
     
    #define RTC_CR_SUB1H_Pos   (17U)
     
    #define RTC_CR_SUB1H_Msk   (0x1UL << RTC_CR_SUB1H_Pos)
     
    #define RTC_CR_SUB1H   RTC_CR_SUB1H_Msk
     
    #define RTC_CR_ADD1H_Pos   (16U)
     
    #define RTC_CR_ADD1H_Msk   (0x1UL << RTC_CR_ADD1H_Pos)
     
    #define RTC_CR_ADD1H   RTC_CR_ADD1H_Msk
     
    #define RTC_CR_TSIE_Pos   (15U)
     
    #define RTC_CR_TSIE_Msk   (0x1UL << RTC_CR_TSIE_Pos)
     
    #define RTC_CR_TSIE   RTC_CR_TSIE_Msk
     
    #define RTC_CR_WUTIE_Pos   (14U)
     
    #define RTC_CR_WUTIE_Msk   (0x1UL << RTC_CR_WUTIE_Pos)
     
    #define RTC_CR_WUTIE   RTC_CR_WUTIE_Msk
     
    #define RTC_CR_ALRBIE_Pos   (13U)
     
    #define RTC_CR_ALRBIE_Msk   (0x1UL << RTC_CR_ALRBIE_Pos)
     
    #define RTC_CR_ALRBIE   RTC_CR_ALRBIE_Msk
     
    #define RTC_CR_ALRAIE_Pos   (12U)
     
    #define RTC_CR_ALRAIE_Msk   (0x1UL << RTC_CR_ALRAIE_Pos)
     
    #define RTC_CR_ALRAIE   RTC_CR_ALRAIE_Msk
     
    #define RTC_CR_TSE_Pos   (11U)
     
    #define RTC_CR_TSE_Msk   (0x1UL << RTC_CR_TSE_Pos)
     
    #define RTC_CR_TSE   RTC_CR_TSE_Msk
     
    #define RTC_CR_WUTE_Pos   (10U)
     
    #define RTC_CR_WUTE_Msk   (0x1UL << RTC_CR_WUTE_Pos)
     
    #define RTC_CR_WUTE   RTC_CR_WUTE_Msk
     
    #define RTC_CR_ALRBE_Pos   (9U)
     
    #define RTC_CR_ALRBE_Msk   (0x1UL << RTC_CR_ALRBE_Pos)
     
    #define RTC_CR_ALRBE   RTC_CR_ALRBE_Msk
     
    #define RTC_CR_ALRAE_Pos   (8U)
     
    #define RTC_CR_ALRAE_Msk   (0x1UL << RTC_CR_ALRAE_Pos)
     
    #define RTC_CR_ALRAE   RTC_CR_ALRAE_Msk
     
    #define RTC_CR_DCE_Pos   (7U)
     
    #define RTC_CR_DCE_Msk   (0x1UL << RTC_CR_DCE_Pos)
     
    #define RTC_CR_DCE   RTC_CR_DCE_Msk
     
    #define RTC_CR_FMT_Pos   (6U)
     
    #define RTC_CR_FMT_Msk   (0x1UL << RTC_CR_FMT_Pos)
     
    #define RTC_CR_FMT   RTC_CR_FMT_Msk
     
    #define RTC_CR_BYPSHAD_Pos   (5U)
     
    #define RTC_CR_BYPSHAD_Msk   (0x1UL << RTC_CR_BYPSHAD_Pos)
     
    #define RTC_CR_BYPSHAD   RTC_CR_BYPSHAD_Msk
     
    #define RTC_CR_REFCKON_Pos   (4U)
     
    #define RTC_CR_REFCKON_Msk   (0x1UL << RTC_CR_REFCKON_Pos)
     
    #define RTC_CR_REFCKON   RTC_CR_REFCKON_Msk
     
    #define RTC_CR_TSEDGE_Pos   (3U)
     
    #define RTC_CR_TSEDGE_Msk   (0x1UL << RTC_CR_TSEDGE_Pos)
     
    #define RTC_CR_TSEDGE   RTC_CR_TSEDGE_Msk
     
    #define RTC_CR_WUCKSEL_Pos   (0U)
     
    #define RTC_CR_WUCKSEL_Msk   (0x7UL << RTC_CR_WUCKSEL_Pos)
     
    #define RTC_CR_WUCKSEL   RTC_CR_WUCKSEL_Msk
     
    #define RTC_CR_WUCKSEL_0   (0x1UL << RTC_CR_WUCKSEL_Pos)
     
    #define RTC_CR_WUCKSEL_1   (0x2UL << RTC_CR_WUCKSEL_Pos)
     
    #define RTC_CR_WUCKSEL_2   (0x4UL << RTC_CR_WUCKSEL_Pos)
     
    #define RTC_CR_BCK   RTC_CR_BKP
     
    #define RTC_ISR_RECALPF_Pos   (16U)
     
    #define RTC_ISR_RECALPF_Msk   (0x1UL << RTC_ISR_RECALPF_Pos)
     
    #define RTC_ISR_RECALPF   RTC_ISR_RECALPF_Msk
     
    #define RTC_ISR_TAMP1F_Pos   (13U)
     
    #define RTC_ISR_TAMP1F_Msk   (0x1UL << RTC_ISR_TAMP1F_Pos)
     
    #define RTC_ISR_TAMP1F   RTC_ISR_TAMP1F_Msk
     
    #define RTC_ISR_TAMP2F_Pos   (14U)
     
    #define RTC_ISR_TAMP2F_Msk   (0x1UL << RTC_ISR_TAMP2F_Pos)
     
    #define RTC_ISR_TAMP2F   RTC_ISR_TAMP2F_Msk
     
    #define RTC_ISR_TSOVF_Pos   (12U)
     
    #define RTC_ISR_TSOVF_Msk   (0x1UL << RTC_ISR_TSOVF_Pos)
     
    #define RTC_ISR_TSOVF   RTC_ISR_TSOVF_Msk
     
    #define RTC_ISR_TSF_Pos   (11U)
     
    #define RTC_ISR_TSF_Msk   (0x1UL << RTC_ISR_TSF_Pos)
     
    #define RTC_ISR_TSF   RTC_ISR_TSF_Msk
     
    #define RTC_ISR_WUTF_Pos   (10U)
     
    #define RTC_ISR_WUTF_Msk   (0x1UL << RTC_ISR_WUTF_Pos)
     
    #define RTC_ISR_WUTF   RTC_ISR_WUTF_Msk
     
    #define RTC_ISR_ALRBF_Pos   (9U)
     
    #define RTC_ISR_ALRBF_Msk   (0x1UL << RTC_ISR_ALRBF_Pos)
     
    #define RTC_ISR_ALRBF   RTC_ISR_ALRBF_Msk
     
    #define RTC_ISR_ALRAF_Pos   (8U)
     
    #define RTC_ISR_ALRAF_Msk   (0x1UL << RTC_ISR_ALRAF_Pos)
     
    #define RTC_ISR_ALRAF   RTC_ISR_ALRAF_Msk
     
    #define RTC_ISR_INIT_Pos   (7U)
     
    #define RTC_ISR_INIT_Msk   (0x1UL << RTC_ISR_INIT_Pos)
     
    #define RTC_ISR_INIT   RTC_ISR_INIT_Msk
     
    #define RTC_ISR_INITF_Pos   (6U)
     
    #define RTC_ISR_INITF_Msk   (0x1UL << RTC_ISR_INITF_Pos)
     
    #define RTC_ISR_INITF   RTC_ISR_INITF_Msk
     
    #define RTC_ISR_RSF_Pos   (5U)
     
    #define RTC_ISR_RSF_Msk   (0x1UL << RTC_ISR_RSF_Pos)
     
    #define RTC_ISR_RSF   RTC_ISR_RSF_Msk
     
    #define RTC_ISR_INITS_Pos   (4U)
     
    #define RTC_ISR_INITS_Msk   (0x1UL << RTC_ISR_INITS_Pos)
     
    #define RTC_ISR_INITS   RTC_ISR_INITS_Msk
     
    #define RTC_ISR_SHPF_Pos   (3U)
     
    #define RTC_ISR_SHPF_Msk   (0x1UL << RTC_ISR_SHPF_Pos)
     
    #define RTC_ISR_SHPF   RTC_ISR_SHPF_Msk
     
    #define RTC_ISR_WUTWF_Pos   (2U)
     
    #define RTC_ISR_WUTWF_Msk   (0x1UL << RTC_ISR_WUTWF_Pos)
     
    #define RTC_ISR_WUTWF   RTC_ISR_WUTWF_Msk
     
    #define RTC_ISR_ALRBWF_Pos   (1U)
     
    #define RTC_ISR_ALRBWF_Msk   (0x1UL << RTC_ISR_ALRBWF_Pos)
     
    #define RTC_ISR_ALRBWF   RTC_ISR_ALRBWF_Msk
     
    #define RTC_ISR_ALRAWF_Pos   (0U)
     
    #define RTC_ISR_ALRAWF_Msk   (0x1UL << RTC_ISR_ALRAWF_Pos)
     
    #define RTC_ISR_ALRAWF   RTC_ISR_ALRAWF_Msk
     
    #define RTC_PRER_PREDIV_A_Pos   (16U)
     
    #define RTC_PRER_PREDIV_A_Msk   (0x7FUL << RTC_PRER_PREDIV_A_Pos)
     
    #define RTC_PRER_PREDIV_A   RTC_PRER_PREDIV_A_Msk
     
    #define RTC_PRER_PREDIV_S_Pos   (0U)
     
    #define RTC_PRER_PREDIV_S_Msk   (0x7FFFUL << RTC_PRER_PREDIV_S_Pos)
     
    #define RTC_PRER_PREDIV_S   RTC_PRER_PREDIV_S_Msk
     
    #define RTC_WUTR_WUT_Pos   (0U)
     
    #define RTC_WUTR_WUT_Msk   (0xFFFFUL << RTC_WUTR_WUT_Pos)
     
    #define RTC_WUTR_WUT   RTC_WUTR_WUT_Msk
     
    #define RTC_CALIBR_DCS_Pos   (7U)
     
    #define RTC_CALIBR_DCS_Msk   (0x1UL << RTC_CALIBR_DCS_Pos)
     
    #define RTC_CALIBR_DCS   RTC_CALIBR_DCS_Msk
     
    #define RTC_CALIBR_DC_Pos   (0U)
     
    #define RTC_CALIBR_DC_Msk   (0x1FUL << RTC_CALIBR_DC_Pos)
     
    #define RTC_CALIBR_DC   RTC_CALIBR_DC_Msk
     
    #define RTC_ALRMAR_MSK4_Pos   (31U)
     
    #define RTC_ALRMAR_MSK4_Msk   (0x1UL << RTC_ALRMAR_MSK4_Pos)
     
    #define RTC_ALRMAR_MSK4   RTC_ALRMAR_MSK4_Msk
     
    #define RTC_ALRMAR_WDSEL_Pos   (30U)
     
    #define RTC_ALRMAR_WDSEL_Msk   (0x1UL << RTC_ALRMAR_WDSEL_Pos)
     
    #define RTC_ALRMAR_WDSEL   RTC_ALRMAR_WDSEL_Msk
     
    #define RTC_ALRMAR_DT_Pos   (28U)
     
    #define RTC_ALRMAR_DT_Msk   (0x3UL << RTC_ALRMAR_DT_Pos)
     
    #define RTC_ALRMAR_DT   RTC_ALRMAR_DT_Msk
     
    #define RTC_ALRMAR_DT_0   (0x1UL << RTC_ALRMAR_DT_Pos)
     
    #define RTC_ALRMAR_DT_1   (0x2UL << RTC_ALRMAR_DT_Pos)
     
    #define RTC_ALRMAR_DU_Pos   (24U)
     
    #define RTC_ALRMAR_DU_Msk   (0xFUL << RTC_ALRMAR_DU_Pos)
     
    #define RTC_ALRMAR_DU   RTC_ALRMAR_DU_Msk
     
    #define RTC_ALRMAR_DU_0   (0x1UL << RTC_ALRMAR_DU_Pos)
     
    #define RTC_ALRMAR_DU_1   (0x2UL << RTC_ALRMAR_DU_Pos)
     
    #define RTC_ALRMAR_DU_2   (0x4UL << RTC_ALRMAR_DU_Pos)
     
    #define RTC_ALRMAR_DU_3   (0x8UL << RTC_ALRMAR_DU_Pos)
     
    #define RTC_ALRMAR_MSK3_Pos   (23U)
     
    #define RTC_ALRMAR_MSK3_Msk   (0x1UL << RTC_ALRMAR_MSK3_Pos)
     
    #define RTC_ALRMAR_MSK3   RTC_ALRMAR_MSK3_Msk
     
    #define RTC_ALRMAR_PM_Pos   (22U)
     
    #define RTC_ALRMAR_PM_Msk   (0x1UL << RTC_ALRMAR_PM_Pos)
     
    #define RTC_ALRMAR_PM   RTC_ALRMAR_PM_Msk
     
    #define RTC_ALRMAR_HT_Pos   (20U)
     
    #define RTC_ALRMAR_HT_Msk   (0x3UL << RTC_ALRMAR_HT_Pos)
     
    #define RTC_ALRMAR_HT   RTC_ALRMAR_HT_Msk
     
    #define RTC_ALRMAR_HT_0   (0x1UL << RTC_ALRMAR_HT_Pos)
     
    #define RTC_ALRMAR_HT_1   (0x2UL << RTC_ALRMAR_HT_Pos)
     
    #define RTC_ALRMAR_HU_Pos   (16U)
     
    #define RTC_ALRMAR_HU_Msk   (0xFUL << RTC_ALRMAR_HU_Pos)
     
    #define RTC_ALRMAR_HU   RTC_ALRMAR_HU_Msk
     
    #define RTC_ALRMAR_HU_0   (0x1UL << RTC_ALRMAR_HU_Pos)
     
    #define RTC_ALRMAR_HU_1   (0x2UL << RTC_ALRMAR_HU_Pos)
     
    #define RTC_ALRMAR_HU_2   (0x4UL << RTC_ALRMAR_HU_Pos)
     
    #define RTC_ALRMAR_HU_3   (0x8UL << RTC_ALRMAR_HU_Pos)
     
    #define RTC_ALRMAR_MSK2_Pos   (15U)
     
    #define RTC_ALRMAR_MSK2_Msk   (0x1UL << RTC_ALRMAR_MSK2_Pos)
     
    #define RTC_ALRMAR_MSK2   RTC_ALRMAR_MSK2_Msk
     
    #define RTC_ALRMAR_MNT_Pos   (12U)
     
    #define RTC_ALRMAR_MNT_Msk   (0x7UL << RTC_ALRMAR_MNT_Pos)
     
    #define RTC_ALRMAR_MNT   RTC_ALRMAR_MNT_Msk
     
    #define RTC_ALRMAR_MNT_0   (0x1UL << RTC_ALRMAR_MNT_Pos)
     
    #define RTC_ALRMAR_MNT_1   (0x2UL << RTC_ALRMAR_MNT_Pos)
     
    #define RTC_ALRMAR_MNT_2   (0x4UL << RTC_ALRMAR_MNT_Pos)
     
    #define RTC_ALRMAR_MNU_Pos   (8U)
     
    #define RTC_ALRMAR_MNU_Msk   (0xFUL << RTC_ALRMAR_MNU_Pos)
     
    #define RTC_ALRMAR_MNU   RTC_ALRMAR_MNU_Msk
     
    #define RTC_ALRMAR_MNU_0   (0x1UL << RTC_ALRMAR_MNU_Pos)
     
    #define RTC_ALRMAR_MNU_1   (0x2UL << RTC_ALRMAR_MNU_Pos)
     
    #define RTC_ALRMAR_MNU_2   (0x4UL << RTC_ALRMAR_MNU_Pos)
     
    #define RTC_ALRMAR_MNU_3   (0x8UL << RTC_ALRMAR_MNU_Pos)
     
    #define RTC_ALRMAR_MSK1_Pos   (7U)
     
    #define RTC_ALRMAR_MSK1_Msk   (0x1UL << RTC_ALRMAR_MSK1_Pos)
     
    #define RTC_ALRMAR_MSK1   RTC_ALRMAR_MSK1_Msk
     
    #define RTC_ALRMAR_ST_Pos   (4U)
     
    #define RTC_ALRMAR_ST_Msk   (0x7UL << RTC_ALRMAR_ST_Pos)
     
    #define RTC_ALRMAR_ST   RTC_ALRMAR_ST_Msk
     
    #define RTC_ALRMAR_ST_0   (0x1UL << RTC_ALRMAR_ST_Pos)
     
    #define RTC_ALRMAR_ST_1   (0x2UL << RTC_ALRMAR_ST_Pos)
     
    #define RTC_ALRMAR_ST_2   (0x4UL << RTC_ALRMAR_ST_Pos)
     
    #define RTC_ALRMAR_SU_Pos   (0U)
     
    #define RTC_ALRMAR_SU_Msk   (0xFUL << RTC_ALRMAR_SU_Pos)
     
    #define RTC_ALRMAR_SU   RTC_ALRMAR_SU_Msk
     
    #define RTC_ALRMAR_SU_0   (0x1UL << RTC_ALRMAR_SU_Pos)
     
    #define RTC_ALRMAR_SU_1   (0x2UL << RTC_ALRMAR_SU_Pos)
     
    #define RTC_ALRMAR_SU_2   (0x4UL << RTC_ALRMAR_SU_Pos)
     
    #define RTC_ALRMAR_SU_3   (0x8UL << RTC_ALRMAR_SU_Pos)
     
    #define RTC_ALRMBR_MSK4_Pos   (31U)
     
    #define RTC_ALRMBR_MSK4_Msk   (0x1UL << RTC_ALRMBR_MSK4_Pos)
     
    #define RTC_ALRMBR_MSK4   RTC_ALRMBR_MSK4_Msk
     
    #define RTC_ALRMBR_WDSEL_Pos   (30U)
     
    #define RTC_ALRMBR_WDSEL_Msk   (0x1UL << RTC_ALRMBR_WDSEL_Pos)
     
    #define RTC_ALRMBR_WDSEL   RTC_ALRMBR_WDSEL_Msk
     
    #define RTC_ALRMBR_DT_Pos   (28U)
     
    #define RTC_ALRMBR_DT_Msk   (0x3UL << RTC_ALRMBR_DT_Pos)
     
    #define RTC_ALRMBR_DT   RTC_ALRMBR_DT_Msk
     
    #define RTC_ALRMBR_DT_0   (0x1UL << RTC_ALRMBR_DT_Pos)
     
    #define RTC_ALRMBR_DT_1   (0x2UL << RTC_ALRMBR_DT_Pos)
     
    #define RTC_ALRMBR_DU_Pos   (24U)
     
    #define RTC_ALRMBR_DU_Msk   (0xFUL << RTC_ALRMBR_DU_Pos)
     
    #define RTC_ALRMBR_DU   RTC_ALRMBR_DU_Msk
     
    #define RTC_ALRMBR_DU_0   (0x1UL << RTC_ALRMBR_DU_Pos)
     
    #define RTC_ALRMBR_DU_1   (0x2UL << RTC_ALRMBR_DU_Pos)
     
    #define RTC_ALRMBR_DU_2   (0x4UL << RTC_ALRMBR_DU_Pos)
     
    #define RTC_ALRMBR_DU_3   (0x8UL << RTC_ALRMBR_DU_Pos)
     
    #define RTC_ALRMBR_MSK3_Pos   (23U)
     
    #define RTC_ALRMBR_MSK3_Msk   (0x1UL << RTC_ALRMBR_MSK3_Pos)
     
    #define RTC_ALRMBR_MSK3   RTC_ALRMBR_MSK3_Msk
     
    #define RTC_ALRMBR_PM_Pos   (22U)
     
    #define RTC_ALRMBR_PM_Msk   (0x1UL << RTC_ALRMBR_PM_Pos)
     
    #define RTC_ALRMBR_PM   RTC_ALRMBR_PM_Msk
     
    #define RTC_ALRMBR_HT_Pos   (20U)
     
    #define RTC_ALRMBR_HT_Msk   (0x3UL << RTC_ALRMBR_HT_Pos)
     
    #define RTC_ALRMBR_HT   RTC_ALRMBR_HT_Msk
     
    #define RTC_ALRMBR_HT_0   (0x1UL << RTC_ALRMBR_HT_Pos)
     
    #define RTC_ALRMBR_HT_1   (0x2UL << RTC_ALRMBR_HT_Pos)
     
    #define RTC_ALRMBR_HU_Pos   (16U)
     
    #define RTC_ALRMBR_HU_Msk   (0xFUL << RTC_ALRMBR_HU_Pos)
     
    #define RTC_ALRMBR_HU   RTC_ALRMBR_HU_Msk
     
    #define RTC_ALRMBR_HU_0   (0x1UL << RTC_ALRMBR_HU_Pos)
     
    #define RTC_ALRMBR_HU_1   (0x2UL << RTC_ALRMBR_HU_Pos)
     
    #define RTC_ALRMBR_HU_2   (0x4UL << RTC_ALRMBR_HU_Pos)
     
    #define RTC_ALRMBR_HU_3   (0x8UL << RTC_ALRMBR_HU_Pos)
     
    #define RTC_ALRMBR_MSK2_Pos   (15U)
     
    #define RTC_ALRMBR_MSK2_Msk   (0x1UL << RTC_ALRMBR_MSK2_Pos)
     
    #define RTC_ALRMBR_MSK2   RTC_ALRMBR_MSK2_Msk
     
    #define RTC_ALRMBR_MNT_Pos   (12U)
     
    #define RTC_ALRMBR_MNT_Msk   (0x7UL << RTC_ALRMBR_MNT_Pos)
     
    #define RTC_ALRMBR_MNT   RTC_ALRMBR_MNT_Msk
     
    #define RTC_ALRMBR_MNT_0   (0x1UL << RTC_ALRMBR_MNT_Pos)
     
    #define RTC_ALRMBR_MNT_1   (0x2UL << RTC_ALRMBR_MNT_Pos)
     
    #define RTC_ALRMBR_MNT_2   (0x4UL << RTC_ALRMBR_MNT_Pos)
     
    #define RTC_ALRMBR_MNU_Pos   (8U)
     
    #define RTC_ALRMBR_MNU_Msk   (0xFUL << RTC_ALRMBR_MNU_Pos)
     
    #define RTC_ALRMBR_MNU   RTC_ALRMBR_MNU_Msk
     
    #define RTC_ALRMBR_MNU_0   (0x1UL << RTC_ALRMBR_MNU_Pos)
     
    #define RTC_ALRMBR_MNU_1   (0x2UL << RTC_ALRMBR_MNU_Pos)
     
    #define RTC_ALRMBR_MNU_2   (0x4UL << RTC_ALRMBR_MNU_Pos)
     
    #define RTC_ALRMBR_MNU_3   (0x8UL << RTC_ALRMBR_MNU_Pos)
     
    #define RTC_ALRMBR_MSK1_Pos   (7U)
     
    #define RTC_ALRMBR_MSK1_Msk   (0x1UL << RTC_ALRMBR_MSK1_Pos)
     
    #define RTC_ALRMBR_MSK1   RTC_ALRMBR_MSK1_Msk
     
    #define RTC_ALRMBR_ST_Pos   (4U)
     
    #define RTC_ALRMBR_ST_Msk   (0x7UL << RTC_ALRMBR_ST_Pos)
     
    #define RTC_ALRMBR_ST   RTC_ALRMBR_ST_Msk
     
    #define RTC_ALRMBR_ST_0   (0x1UL << RTC_ALRMBR_ST_Pos)
     
    #define RTC_ALRMBR_ST_1   (0x2UL << RTC_ALRMBR_ST_Pos)
     
    #define RTC_ALRMBR_ST_2   (0x4UL << RTC_ALRMBR_ST_Pos)
     
    #define RTC_ALRMBR_SU_Pos   (0U)
     
    #define RTC_ALRMBR_SU_Msk   (0xFUL << RTC_ALRMBR_SU_Pos)
     
    #define RTC_ALRMBR_SU   RTC_ALRMBR_SU_Msk
     
    #define RTC_ALRMBR_SU_0   (0x1UL << RTC_ALRMBR_SU_Pos)
     
    #define RTC_ALRMBR_SU_1   (0x2UL << RTC_ALRMBR_SU_Pos)
     
    #define RTC_ALRMBR_SU_2   (0x4UL << RTC_ALRMBR_SU_Pos)
     
    #define RTC_ALRMBR_SU_3   (0x8UL << RTC_ALRMBR_SU_Pos)
     
    #define RTC_WPR_KEY_Pos   (0U)
     
    #define RTC_WPR_KEY_Msk   (0xFFUL << RTC_WPR_KEY_Pos)
     
    #define RTC_WPR_KEY   RTC_WPR_KEY_Msk
     
    #define RTC_SSR_SS_Pos   (0U)
     
    #define RTC_SSR_SS_Msk   (0xFFFFUL << RTC_SSR_SS_Pos)
     
    #define RTC_SSR_SS   RTC_SSR_SS_Msk
     
    #define RTC_SHIFTR_SUBFS_Pos   (0U)
     
    #define RTC_SHIFTR_SUBFS_Msk   (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos)
     
    #define RTC_SHIFTR_SUBFS   RTC_SHIFTR_SUBFS_Msk
     
    #define RTC_SHIFTR_ADD1S_Pos   (31U)
     
    #define RTC_SHIFTR_ADD1S_Msk   (0x1UL << RTC_SHIFTR_ADD1S_Pos)
     
    #define RTC_SHIFTR_ADD1S   RTC_SHIFTR_ADD1S_Msk
     
    #define RTC_TSTR_PM_Pos   (22U)
     
    #define RTC_TSTR_PM_Msk   (0x1UL << RTC_TSTR_PM_Pos)
     
    #define RTC_TSTR_PM   RTC_TSTR_PM_Msk
     
    #define RTC_TSTR_HT_Pos   (20U)
     
    #define RTC_TSTR_HT_Msk   (0x3UL << RTC_TSTR_HT_Pos)
     
    #define RTC_TSTR_HT   RTC_TSTR_HT_Msk
     
    #define RTC_TSTR_HT_0   (0x1UL << RTC_TSTR_HT_Pos)
     
    #define RTC_TSTR_HT_1   (0x2UL << RTC_TSTR_HT_Pos)
     
    #define RTC_TSTR_HU_Pos   (16U)
     
    #define RTC_TSTR_HU_Msk   (0xFUL << RTC_TSTR_HU_Pos)
     
    #define RTC_TSTR_HU   RTC_TSTR_HU_Msk
     
    #define RTC_TSTR_HU_0   (0x1UL << RTC_TSTR_HU_Pos)
     
    #define RTC_TSTR_HU_1   (0x2UL << RTC_TSTR_HU_Pos)
     
    #define RTC_TSTR_HU_2   (0x4UL << RTC_TSTR_HU_Pos)
     
    #define RTC_TSTR_HU_3   (0x8UL << RTC_TSTR_HU_Pos)
     
    #define RTC_TSTR_MNT_Pos   (12U)
     
    #define RTC_TSTR_MNT_Msk   (0x7UL << RTC_TSTR_MNT_Pos)
     
    #define RTC_TSTR_MNT   RTC_TSTR_MNT_Msk
     
    #define RTC_TSTR_MNT_0   (0x1UL << RTC_TSTR_MNT_Pos)
     
    #define RTC_TSTR_MNT_1   (0x2UL << RTC_TSTR_MNT_Pos)
     
    #define RTC_TSTR_MNT_2   (0x4UL << RTC_TSTR_MNT_Pos)
     
    #define RTC_TSTR_MNU_Pos   (8U)
     
    #define RTC_TSTR_MNU_Msk   (0xFUL << RTC_TSTR_MNU_Pos)
     
    #define RTC_TSTR_MNU   RTC_TSTR_MNU_Msk
     
    #define RTC_TSTR_MNU_0   (0x1UL << RTC_TSTR_MNU_Pos)
     
    #define RTC_TSTR_MNU_1   (0x2UL << RTC_TSTR_MNU_Pos)
     
    #define RTC_TSTR_MNU_2   (0x4UL << RTC_TSTR_MNU_Pos)
     
    #define RTC_TSTR_MNU_3   (0x8UL << RTC_TSTR_MNU_Pos)
     
    #define RTC_TSTR_ST_Pos   (4U)
     
    #define RTC_TSTR_ST_Msk   (0x7UL << RTC_TSTR_ST_Pos)
     
    #define RTC_TSTR_ST   RTC_TSTR_ST_Msk
     
    #define RTC_TSTR_ST_0   (0x1UL << RTC_TSTR_ST_Pos)
     
    #define RTC_TSTR_ST_1   (0x2UL << RTC_TSTR_ST_Pos)
     
    #define RTC_TSTR_ST_2   (0x4UL << RTC_TSTR_ST_Pos)
     
    #define RTC_TSTR_SU_Pos   (0U)
     
    #define RTC_TSTR_SU_Msk   (0xFUL << RTC_TSTR_SU_Pos)
     
    #define RTC_TSTR_SU   RTC_TSTR_SU_Msk
     
    #define RTC_TSTR_SU_0   (0x1UL << RTC_TSTR_SU_Pos)
     
    #define RTC_TSTR_SU_1   (0x2UL << RTC_TSTR_SU_Pos)
     
    #define RTC_TSTR_SU_2   (0x4UL << RTC_TSTR_SU_Pos)
     
    #define RTC_TSTR_SU_3   (0x8UL << RTC_TSTR_SU_Pos)
     
    #define RTC_TSDR_WDU_Pos   (13U)
     
    #define RTC_TSDR_WDU_Msk   (0x7UL << RTC_TSDR_WDU_Pos)
     
    #define RTC_TSDR_WDU   RTC_TSDR_WDU_Msk
     
    #define RTC_TSDR_WDU_0   (0x1UL << RTC_TSDR_WDU_Pos)
     
    #define RTC_TSDR_WDU_1   (0x2UL << RTC_TSDR_WDU_Pos)
     
    #define RTC_TSDR_WDU_2   (0x4UL << RTC_TSDR_WDU_Pos)
     
    #define RTC_TSDR_MT_Pos   (12U)
     
    #define RTC_TSDR_MT_Msk   (0x1UL << RTC_TSDR_MT_Pos)
     
    #define RTC_TSDR_MT   RTC_TSDR_MT_Msk
     
    #define RTC_TSDR_MU_Pos   (8U)
     
    #define RTC_TSDR_MU_Msk   (0xFUL << RTC_TSDR_MU_Pos)
     
    #define RTC_TSDR_MU   RTC_TSDR_MU_Msk
     
    #define RTC_TSDR_MU_0   (0x1UL << RTC_TSDR_MU_Pos)
     
    #define RTC_TSDR_MU_1   (0x2UL << RTC_TSDR_MU_Pos)
     
    #define RTC_TSDR_MU_2   (0x4UL << RTC_TSDR_MU_Pos)
     
    #define RTC_TSDR_MU_3   (0x8UL << RTC_TSDR_MU_Pos)
     
    #define RTC_TSDR_DT_Pos   (4U)
     
    #define RTC_TSDR_DT_Msk   (0x3UL << RTC_TSDR_DT_Pos)
     
    #define RTC_TSDR_DT   RTC_TSDR_DT_Msk
     
    #define RTC_TSDR_DT_0   (0x1UL << RTC_TSDR_DT_Pos)
     
    #define RTC_TSDR_DT_1   (0x2UL << RTC_TSDR_DT_Pos)
     
    #define RTC_TSDR_DU_Pos   (0U)
     
    #define RTC_TSDR_DU_Msk   (0xFUL << RTC_TSDR_DU_Pos)
     
    #define RTC_TSDR_DU   RTC_TSDR_DU_Msk
     
    #define RTC_TSDR_DU_0   (0x1UL << RTC_TSDR_DU_Pos)
     
    #define RTC_TSDR_DU_1   (0x2UL << RTC_TSDR_DU_Pos)
     
    #define RTC_TSDR_DU_2   (0x4UL << RTC_TSDR_DU_Pos)
     
    #define RTC_TSDR_DU_3   (0x8UL << RTC_TSDR_DU_Pos)
     
    #define RTC_TSSSR_SS_Pos   (0U)
     
    #define RTC_TSSSR_SS_Msk   (0xFFFFUL << RTC_TSSSR_SS_Pos)
     
    #define RTC_TSSSR_SS   RTC_TSSSR_SS_Msk
     
    #define RTC_CALR_CALP_Pos   (15U)
     
    #define RTC_CALR_CALP_Msk   (0x1UL << RTC_CALR_CALP_Pos)
     
    #define RTC_CALR_CALP   RTC_CALR_CALP_Msk
     
    #define RTC_CALR_CALW8_Pos   (14U)
     
    #define RTC_CALR_CALW8_Msk   (0x1UL << RTC_CALR_CALW8_Pos)
     
    #define RTC_CALR_CALW8   RTC_CALR_CALW8_Msk
     
    #define RTC_CALR_CALW16_Pos   (13U)
     
    #define RTC_CALR_CALW16_Msk   (0x1UL << RTC_CALR_CALW16_Pos)
     
    #define RTC_CALR_CALW16   RTC_CALR_CALW16_Msk
     
    #define RTC_CALR_CALM_Pos   (0U)
     
    #define RTC_CALR_CALM_Msk   (0x1FFUL << RTC_CALR_CALM_Pos)
     
    #define RTC_CALR_CALM   RTC_CALR_CALM_Msk
     
    #define RTC_CALR_CALM_0   (0x001UL << RTC_CALR_CALM_Pos)
     
    #define RTC_CALR_CALM_1   (0x002UL << RTC_CALR_CALM_Pos)
     
    #define RTC_CALR_CALM_2   (0x004UL << RTC_CALR_CALM_Pos)
     
    #define RTC_CALR_CALM_3   (0x008UL << RTC_CALR_CALM_Pos)
     
    #define RTC_CALR_CALM_4   (0x010UL << RTC_CALR_CALM_Pos)
     
    #define RTC_CALR_CALM_5   (0x020UL << RTC_CALR_CALM_Pos)
     
    #define RTC_CALR_CALM_6   (0x040UL << RTC_CALR_CALM_Pos)
     
    #define RTC_CALR_CALM_7   (0x080UL << RTC_CALR_CALM_Pos)
     
    #define RTC_CALR_CALM_8   (0x100UL << RTC_CALR_CALM_Pos)
     
    #define RTC_TAFCR_ALARMOUTTYPE_Pos   (18U)
     
    #define RTC_TAFCR_ALARMOUTTYPE_Msk   (0x1UL << RTC_TAFCR_ALARMOUTTYPE_Pos)
     
    #define RTC_TAFCR_ALARMOUTTYPE   RTC_TAFCR_ALARMOUTTYPE_Msk
     
    #define RTC_TAFCR_TSINSEL_Pos   (17U)
     
    #define RTC_TAFCR_TSINSEL_Msk   (0x1UL << RTC_TAFCR_TSINSEL_Pos)
     
    #define RTC_TAFCR_TSINSEL   RTC_TAFCR_TSINSEL_Msk
     
    #define RTC_TAFCR_TAMP1INSEL_Pos   (16U)
     
    #define RTC_TAFCR_TAMP1INSEL_Msk   (0x1UL << RTC_TAFCR_TAMP1INSEL_Pos)
     
    #define RTC_TAFCR_TAMP1INSEL   RTC_TAFCR_TAMP1INSEL_Msk
     
    #define RTC_TAFCR_TAMPPUDIS_Pos   (15U)
     
    #define RTC_TAFCR_TAMPPUDIS_Msk   (0x1UL << RTC_TAFCR_TAMPPUDIS_Pos)
     
    #define RTC_TAFCR_TAMPPUDIS   RTC_TAFCR_TAMPPUDIS_Msk
     
    #define RTC_TAFCR_TAMPPRCH_Pos   (13U)
     
    #define RTC_TAFCR_TAMPPRCH_Msk   (0x3UL << RTC_TAFCR_TAMPPRCH_Pos)
     
    #define RTC_TAFCR_TAMPPRCH   RTC_TAFCR_TAMPPRCH_Msk
     
    #define RTC_TAFCR_TAMPPRCH_0   (0x1UL << RTC_TAFCR_TAMPPRCH_Pos)
     
    #define RTC_TAFCR_TAMPPRCH_1   (0x2UL << RTC_TAFCR_TAMPPRCH_Pos)
     
    #define RTC_TAFCR_TAMPFLT_Pos   (11U)
     
    #define RTC_TAFCR_TAMPFLT_Msk   (0x3UL << RTC_TAFCR_TAMPFLT_Pos)
     
    #define RTC_TAFCR_TAMPFLT   RTC_TAFCR_TAMPFLT_Msk
     
    #define RTC_TAFCR_TAMPFLT_0   (0x1UL << RTC_TAFCR_TAMPFLT_Pos)
     
    #define RTC_TAFCR_TAMPFLT_1   (0x2UL << RTC_TAFCR_TAMPFLT_Pos)
     
    #define RTC_TAFCR_TAMPFREQ_Pos   (8U)
     
    #define RTC_TAFCR_TAMPFREQ_Msk   (0x7UL << RTC_TAFCR_TAMPFREQ_Pos)
     
    #define RTC_TAFCR_TAMPFREQ   RTC_TAFCR_TAMPFREQ_Msk
     
    #define RTC_TAFCR_TAMPFREQ_0   (0x1UL << RTC_TAFCR_TAMPFREQ_Pos)
     
    #define RTC_TAFCR_TAMPFREQ_1   (0x2UL << RTC_TAFCR_TAMPFREQ_Pos)
     
    #define RTC_TAFCR_TAMPFREQ_2   (0x4UL << RTC_TAFCR_TAMPFREQ_Pos)
     
    #define RTC_TAFCR_TAMPTS_Pos   (7U)
     
    #define RTC_TAFCR_TAMPTS_Msk   (0x1UL << RTC_TAFCR_TAMPTS_Pos)
     
    #define RTC_TAFCR_TAMPTS   RTC_TAFCR_TAMPTS_Msk
     
    #define RTC_TAFCR_TAMP2TRG_Pos   (4U)
     
    #define RTC_TAFCR_TAMP2TRG_Msk   (0x1UL << RTC_TAFCR_TAMP2TRG_Pos)
     
    #define RTC_TAFCR_TAMP2TRG   RTC_TAFCR_TAMP2TRG_Msk
     
    #define RTC_TAFCR_TAMP2E_Pos   (3U)
     
    #define RTC_TAFCR_TAMP2E_Msk   (0x1UL << RTC_TAFCR_TAMP2E_Pos)
     
    #define RTC_TAFCR_TAMP2E   RTC_TAFCR_TAMP2E_Msk
     
    #define RTC_TAFCR_TAMPIE_Pos   (2U)
     
    #define RTC_TAFCR_TAMPIE_Msk   (0x1UL << RTC_TAFCR_TAMPIE_Pos)
     
    #define RTC_TAFCR_TAMPIE   RTC_TAFCR_TAMPIE_Msk
     
    #define RTC_TAFCR_TAMP1TRG_Pos   (1U)
     
    #define RTC_TAFCR_TAMP1TRG_Msk   (0x1UL << RTC_TAFCR_TAMP1TRG_Pos)
     
    #define RTC_TAFCR_TAMP1TRG   RTC_TAFCR_TAMP1TRG_Msk
     
    #define RTC_TAFCR_TAMP1E_Pos   (0U)
     
    #define RTC_TAFCR_TAMP1E_Msk   (0x1UL << RTC_TAFCR_TAMP1E_Pos)
     
    #define RTC_TAFCR_TAMP1E   RTC_TAFCR_TAMP1E_Msk
     
    #define RTC_TAFCR_TAMPINSEL   RTC_TAFCR_TAMP1INSEL
     
    #define RTC_ALRMASSR_MASKSS_Pos   (24U)
     
    #define RTC_ALRMASSR_MASKSS_Msk   (0xFUL << RTC_ALRMASSR_MASKSS_Pos)
     
    #define RTC_ALRMASSR_MASKSS   RTC_ALRMASSR_MASKSS_Msk
     
    #define RTC_ALRMASSR_MASKSS_0   (0x1UL << RTC_ALRMASSR_MASKSS_Pos)
     
    #define RTC_ALRMASSR_MASKSS_1   (0x2UL << RTC_ALRMASSR_MASKSS_Pos)
     
    #define RTC_ALRMASSR_MASKSS_2   (0x4UL << RTC_ALRMASSR_MASKSS_Pos)
     
    #define RTC_ALRMASSR_MASKSS_3   (0x8UL << RTC_ALRMASSR_MASKSS_Pos)
     
    #define RTC_ALRMASSR_SS_Pos   (0U)
     
    #define RTC_ALRMASSR_SS_Msk   (0x7FFFUL << RTC_ALRMASSR_SS_Pos)
     
    #define RTC_ALRMASSR_SS   RTC_ALRMASSR_SS_Msk
     
    #define RTC_ALRMBSSR_MASKSS_Pos   (24U)
     
    #define RTC_ALRMBSSR_MASKSS_Msk   (0xFUL << RTC_ALRMBSSR_MASKSS_Pos)
     
    #define RTC_ALRMBSSR_MASKSS   RTC_ALRMBSSR_MASKSS_Msk
     
    #define RTC_ALRMBSSR_MASKSS_0   (0x1UL << RTC_ALRMBSSR_MASKSS_Pos)
     
    #define RTC_ALRMBSSR_MASKSS_1   (0x2UL << RTC_ALRMBSSR_MASKSS_Pos)
     
    #define RTC_ALRMBSSR_MASKSS_2   (0x4UL << RTC_ALRMBSSR_MASKSS_Pos)
     
    #define RTC_ALRMBSSR_MASKSS_3   (0x8UL << RTC_ALRMBSSR_MASKSS_Pos)
     
    #define RTC_ALRMBSSR_SS_Pos   (0U)
     
    #define RTC_ALRMBSSR_SS_Msk   (0x7FFFUL << RTC_ALRMBSSR_SS_Pos)
     
    #define RTC_ALRMBSSR_SS   RTC_ALRMBSSR_SS_Msk
     
    #define RTC_BKP0R_Pos   (0U)
     
    #define RTC_BKP0R_Msk   (0xFFFFFFFFUL << RTC_BKP0R_Pos)
     
    #define RTC_BKP0R   RTC_BKP0R_Msk
     
    #define RTC_BKP1R_Pos   (0U)
     
    #define RTC_BKP1R_Msk   (0xFFFFFFFFUL << RTC_BKP1R_Pos)
     
    #define RTC_BKP1R   RTC_BKP1R_Msk
     
    #define RTC_BKP2R_Pos   (0U)
     
    #define RTC_BKP2R_Msk   (0xFFFFFFFFUL << RTC_BKP2R_Pos)
     
    #define RTC_BKP2R   RTC_BKP2R_Msk
     
    #define RTC_BKP3R_Pos   (0U)
     
    #define RTC_BKP3R_Msk   (0xFFFFFFFFUL << RTC_BKP3R_Pos)
     
    #define RTC_BKP3R   RTC_BKP3R_Msk
     
    #define RTC_BKP4R_Pos   (0U)
     
    #define RTC_BKP4R_Msk   (0xFFFFFFFFUL << RTC_BKP4R_Pos)
     
    #define RTC_BKP4R   RTC_BKP4R_Msk
     
    #define RTC_BKP5R_Pos   (0U)
     
    #define RTC_BKP5R_Msk   (0xFFFFFFFFUL << RTC_BKP5R_Pos)
     
    #define RTC_BKP5R   RTC_BKP5R_Msk
     
    #define RTC_BKP6R_Pos   (0U)
     
    #define RTC_BKP6R_Msk   (0xFFFFFFFFUL << RTC_BKP6R_Pos)
     
    #define RTC_BKP6R   RTC_BKP6R_Msk
     
    #define RTC_BKP7R_Pos   (0U)
     
    #define RTC_BKP7R_Msk   (0xFFFFFFFFUL << RTC_BKP7R_Pos)
     
    #define RTC_BKP7R   RTC_BKP7R_Msk
     
    #define RTC_BKP8R_Pos   (0U)
     
    #define RTC_BKP8R_Msk   (0xFFFFFFFFUL << RTC_BKP8R_Pos)
     
    #define RTC_BKP8R   RTC_BKP8R_Msk
     
    #define RTC_BKP9R_Pos   (0U)
     
    #define RTC_BKP9R_Msk   (0xFFFFFFFFUL << RTC_BKP9R_Pos)
     
    #define RTC_BKP9R   RTC_BKP9R_Msk
     
    #define RTC_BKP10R_Pos   (0U)
     
    #define RTC_BKP10R_Msk   (0xFFFFFFFFUL << RTC_BKP10R_Pos)
     
    #define RTC_BKP10R   RTC_BKP10R_Msk
     
    #define RTC_BKP11R_Pos   (0U)
     
    #define RTC_BKP11R_Msk   (0xFFFFFFFFUL << RTC_BKP11R_Pos)
     
    #define RTC_BKP11R   RTC_BKP11R_Msk
     
    #define RTC_BKP12R_Pos   (0U)
     
    #define RTC_BKP12R_Msk   (0xFFFFFFFFUL << RTC_BKP12R_Pos)
     
    #define RTC_BKP12R   RTC_BKP12R_Msk
     
    #define RTC_BKP13R_Pos   (0U)
     
    #define RTC_BKP13R_Msk   (0xFFFFFFFFUL << RTC_BKP13R_Pos)
     
    #define RTC_BKP13R   RTC_BKP13R_Msk
     
    #define RTC_BKP14R_Pos   (0U)
     
    #define RTC_BKP14R_Msk   (0xFFFFFFFFUL << RTC_BKP14R_Pos)
     
    #define RTC_BKP14R   RTC_BKP14R_Msk
     
    #define RTC_BKP15R_Pos   (0U)
     
    #define RTC_BKP15R_Msk   (0xFFFFFFFFUL << RTC_BKP15R_Pos)
     
    #define RTC_BKP15R   RTC_BKP15R_Msk
     
    #define RTC_BKP16R_Pos   (0U)
     
    #define RTC_BKP16R_Msk   (0xFFFFFFFFUL << RTC_BKP16R_Pos)
     
    #define RTC_BKP16R   RTC_BKP16R_Msk
     
    #define RTC_BKP17R_Pos   (0U)
     
    #define RTC_BKP17R_Msk   (0xFFFFFFFFUL << RTC_BKP17R_Pos)
     
    #define RTC_BKP17R   RTC_BKP17R_Msk
     
    #define RTC_BKP18R_Pos   (0U)
     
    #define RTC_BKP18R_Msk   (0xFFFFFFFFUL << RTC_BKP18R_Pos)
     
    #define RTC_BKP18R   RTC_BKP18R_Msk
     
    #define RTC_BKP19R_Pos   (0U)
     
    #define RTC_BKP19R_Msk   (0xFFFFFFFFUL << RTC_BKP19R_Pos)
     
    #define RTC_BKP19R   RTC_BKP19R_Msk
     
    #define RTC_BKP_NUMBER   0x000000014U
     
    #define SDIO_POWER_PWRCTRL_Pos   (0U)
     
    #define SDIO_POWER_PWRCTRL_Msk   (0x3UL << SDIO_POWER_PWRCTRL_Pos)
     
    #define SDIO_POWER_PWRCTRL   SDIO_POWER_PWRCTRL_Msk
     
    #define SDIO_POWER_PWRCTRL_0   (0x1UL << SDIO_POWER_PWRCTRL_Pos)
     
    #define SDIO_POWER_PWRCTRL_1   (0x2UL << SDIO_POWER_PWRCTRL_Pos)
     
    #define SDIO_CLKCR_CLKDIV_Pos   (0U)
     
    #define SDIO_CLKCR_CLKDIV_Msk   (0xFFUL << SDIO_CLKCR_CLKDIV_Pos)
     
    #define SDIO_CLKCR_CLKDIV   SDIO_CLKCR_CLKDIV_Msk
     
    #define SDIO_CLKCR_CLKEN_Pos   (8U)
     
    #define SDIO_CLKCR_CLKEN_Msk   (0x1UL << SDIO_CLKCR_CLKEN_Pos)
     
    #define SDIO_CLKCR_CLKEN   SDIO_CLKCR_CLKEN_Msk
     
    #define SDIO_CLKCR_PWRSAV_Pos   (9U)
     
    #define SDIO_CLKCR_PWRSAV_Msk   (0x1UL << SDIO_CLKCR_PWRSAV_Pos)
     
    #define SDIO_CLKCR_PWRSAV   SDIO_CLKCR_PWRSAV_Msk
     
    #define SDIO_CLKCR_BYPASS_Pos   (10U)
     
    #define SDIO_CLKCR_BYPASS_Msk   (0x1UL << SDIO_CLKCR_BYPASS_Pos)
     
    #define SDIO_CLKCR_BYPASS   SDIO_CLKCR_BYPASS_Msk
     
    #define SDIO_CLKCR_WIDBUS_Pos   (11U)
     
    #define SDIO_CLKCR_WIDBUS_Msk   (0x3UL << SDIO_CLKCR_WIDBUS_Pos)
     
    #define SDIO_CLKCR_WIDBUS   SDIO_CLKCR_WIDBUS_Msk
     
    #define SDIO_CLKCR_WIDBUS_0   (0x1UL << SDIO_CLKCR_WIDBUS_Pos)
     
    #define SDIO_CLKCR_WIDBUS_1   (0x2UL << SDIO_CLKCR_WIDBUS_Pos)
     
    #define SDIO_CLKCR_NEGEDGE_Pos   (13U)
     
    #define SDIO_CLKCR_NEGEDGE_Msk   (0x1UL << SDIO_CLKCR_NEGEDGE_Pos)
     
    #define SDIO_CLKCR_NEGEDGE   SDIO_CLKCR_NEGEDGE_Msk
     
    #define SDIO_CLKCR_HWFC_EN_Pos   (14U)
     
    #define SDIO_CLKCR_HWFC_EN_Msk   (0x1UL << SDIO_CLKCR_HWFC_EN_Pos)
     
    #define SDIO_CLKCR_HWFC_EN   SDIO_CLKCR_HWFC_EN_Msk
     
    #define SDIO_ARG_CMDARG_Pos   (0U)
     
    #define SDIO_ARG_CMDARG_Msk   (0xFFFFFFFFUL << SDIO_ARG_CMDARG_Pos)
     
    #define SDIO_ARG_CMDARG   SDIO_ARG_CMDARG_Msk
     
    #define SDIO_CMD_CMDINDEX_Pos   (0U)
     
    #define SDIO_CMD_CMDINDEX_Msk   (0x3FUL << SDIO_CMD_CMDINDEX_Pos)
     
    #define SDIO_CMD_CMDINDEX   SDIO_CMD_CMDINDEX_Msk
     
    #define SDIO_CMD_WAITRESP_Pos   (6U)
     
    #define SDIO_CMD_WAITRESP_Msk   (0x3UL << SDIO_CMD_WAITRESP_Pos)
     
    #define SDIO_CMD_WAITRESP   SDIO_CMD_WAITRESP_Msk
     
    #define SDIO_CMD_WAITRESP_0   (0x1UL << SDIO_CMD_WAITRESP_Pos)
     
    #define SDIO_CMD_WAITRESP_1   (0x2UL << SDIO_CMD_WAITRESP_Pos)
     
    #define SDIO_CMD_WAITINT_Pos   (8U)
     
    #define SDIO_CMD_WAITINT_Msk   (0x1UL << SDIO_CMD_WAITINT_Pos)
     
    #define SDIO_CMD_WAITINT   SDIO_CMD_WAITINT_Msk
     
    #define SDIO_CMD_WAITPEND_Pos   (9U)
     
    #define SDIO_CMD_WAITPEND_Msk   (0x1UL << SDIO_CMD_WAITPEND_Pos)
     
    #define SDIO_CMD_WAITPEND   SDIO_CMD_WAITPEND_Msk
     
    #define SDIO_CMD_CPSMEN_Pos   (10U)
     
    #define SDIO_CMD_CPSMEN_Msk   (0x1UL << SDIO_CMD_CPSMEN_Pos)
     
    #define SDIO_CMD_CPSMEN   SDIO_CMD_CPSMEN_Msk
     
    #define SDIO_CMD_SDIOSUSPEND_Pos   (11U)
     
    #define SDIO_CMD_SDIOSUSPEND_Msk   (0x1UL << SDIO_CMD_SDIOSUSPEND_Pos)
     
    #define SDIO_CMD_SDIOSUSPEND   SDIO_CMD_SDIOSUSPEND_Msk
     
    #define SDIO_CMD_ENCMDCOMPL_Pos   (12U)
     
    #define SDIO_CMD_ENCMDCOMPL_Msk   (0x1UL << SDIO_CMD_ENCMDCOMPL_Pos)
     
    #define SDIO_CMD_ENCMDCOMPL   SDIO_CMD_ENCMDCOMPL_Msk
     
    #define SDIO_CMD_NIEN_Pos   (13U)
     
    #define SDIO_CMD_NIEN_Msk   (0x1UL << SDIO_CMD_NIEN_Pos)
     
    #define SDIO_CMD_NIEN   SDIO_CMD_NIEN_Msk
     
    #define SDIO_CMD_CEATACMD_Pos   (14U)
     
    #define SDIO_CMD_CEATACMD_Msk   (0x1UL << SDIO_CMD_CEATACMD_Pos)
     
    #define SDIO_CMD_CEATACMD   SDIO_CMD_CEATACMD_Msk
     
    #define SDIO_RESPCMD_RESPCMD_Pos   (0U)
     
    #define SDIO_RESPCMD_RESPCMD_Msk   (0x3FUL << SDIO_RESPCMD_RESPCMD_Pos)
     
    #define SDIO_RESPCMD_RESPCMD   SDIO_RESPCMD_RESPCMD_Msk
     
    #define SDIO_RESP0_CARDSTATUS0_Pos   (0U)
     
    #define SDIO_RESP0_CARDSTATUS0_Msk   (0xFFFFFFFFUL << SDIO_RESP0_CARDSTATUS0_Pos)
     
    #define SDIO_RESP0_CARDSTATUS0   SDIO_RESP0_CARDSTATUS0_Msk
     
    #define SDIO_RESP1_CARDSTATUS1_Pos   (0U)
     
    #define SDIO_RESP1_CARDSTATUS1_Msk   (0xFFFFFFFFUL << SDIO_RESP1_CARDSTATUS1_Pos)
     
    #define SDIO_RESP1_CARDSTATUS1   SDIO_RESP1_CARDSTATUS1_Msk
     
    #define SDIO_RESP2_CARDSTATUS2_Pos   (0U)
     
    #define SDIO_RESP2_CARDSTATUS2_Msk   (0xFFFFFFFFUL << SDIO_RESP2_CARDSTATUS2_Pos)
     
    #define SDIO_RESP2_CARDSTATUS2   SDIO_RESP2_CARDSTATUS2_Msk
     
    #define SDIO_RESP3_CARDSTATUS3_Pos   (0U)
     
    #define SDIO_RESP3_CARDSTATUS3_Msk   (0xFFFFFFFFUL << SDIO_RESP3_CARDSTATUS3_Pos)
     
    #define SDIO_RESP3_CARDSTATUS3   SDIO_RESP3_CARDSTATUS3_Msk
     
    #define SDIO_RESP4_CARDSTATUS4_Pos   (0U)
     
    #define SDIO_RESP4_CARDSTATUS4_Msk   (0xFFFFFFFFUL << SDIO_RESP4_CARDSTATUS4_Pos)
     
    #define SDIO_RESP4_CARDSTATUS4   SDIO_RESP4_CARDSTATUS4_Msk
     
    #define SDIO_DTIMER_DATATIME_Pos   (0U)
     
    #define SDIO_DTIMER_DATATIME_Msk   (0xFFFFFFFFUL << SDIO_DTIMER_DATATIME_Pos)
     
    #define SDIO_DTIMER_DATATIME   SDIO_DTIMER_DATATIME_Msk
     
    #define SDIO_DLEN_DATALENGTH_Pos   (0U)
     
    #define SDIO_DLEN_DATALENGTH_Msk   (0x1FFFFFFUL << SDIO_DLEN_DATALENGTH_Pos)
     
    #define SDIO_DLEN_DATALENGTH   SDIO_DLEN_DATALENGTH_Msk
     
    #define SDIO_DCTRL_DTEN_Pos   (0U)
     
    #define SDIO_DCTRL_DTEN_Msk   (0x1UL << SDIO_DCTRL_DTEN_Pos)
     
    #define SDIO_DCTRL_DTEN   SDIO_DCTRL_DTEN_Msk
     
    #define SDIO_DCTRL_DTDIR_Pos   (1U)
     
    #define SDIO_DCTRL_DTDIR_Msk   (0x1UL << SDIO_DCTRL_DTDIR_Pos)
     
    #define SDIO_DCTRL_DTDIR   SDIO_DCTRL_DTDIR_Msk
     
    #define SDIO_DCTRL_DTMODE_Pos   (2U)
     
    #define SDIO_DCTRL_DTMODE_Msk   (0x1UL << SDIO_DCTRL_DTMODE_Pos)
     
    #define SDIO_DCTRL_DTMODE   SDIO_DCTRL_DTMODE_Msk
     
    #define SDIO_DCTRL_DMAEN_Pos   (3U)
     
    #define SDIO_DCTRL_DMAEN_Msk   (0x1UL << SDIO_DCTRL_DMAEN_Pos)
     
    #define SDIO_DCTRL_DMAEN   SDIO_DCTRL_DMAEN_Msk
     
    #define SDIO_DCTRL_DBLOCKSIZE_Pos   (4U)
     
    #define SDIO_DCTRL_DBLOCKSIZE_Msk   (0xFUL << SDIO_DCTRL_DBLOCKSIZE_Pos)
     
    #define SDIO_DCTRL_DBLOCKSIZE   SDIO_DCTRL_DBLOCKSIZE_Msk
     
    #define SDIO_DCTRL_DBLOCKSIZE_0   (0x1UL << SDIO_DCTRL_DBLOCKSIZE_Pos)
     
    #define SDIO_DCTRL_DBLOCKSIZE_1   (0x2UL << SDIO_DCTRL_DBLOCKSIZE_Pos)
     
    #define SDIO_DCTRL_DBLOCKSIZE_2   (0x4UL << SDIO_DCTRL_DBLOCKSIZE_Pos)
     
    #define SDIO_DCTRL_DBLOCKSIZE_3   (0x8UL << SDIO_DCTRL_DBLOCKSIZE_Pos)
     
    #define SDIO_DCTRL_RWSTART_Pos   (8U)
     
    #define SDIO_DCTRL_RWSTART_Msk   (0x1UL << SDIO_DCTRL_RWSTART_Pos)
     
    #define SDIO_DCTRL_RWSTART   SDIO_DCTRL_RWSTART_Msk
     
    #define SDIO_DCTRL_RWSTOP_Pos   (9U)
     
    #define SDIO_DCTRL_RWSTOP_Msk   (0x1UL << SDIO_DCTRL_RWSTOP_Pos)
     
    #define SDIO_DCTRL_RWSTOP   SDIO_DCTRL_RWSTOP_Msk
     
    #define SDIO_DCTRL_RWMOD_Pos   (10U)
     
    #define SDIO_DCTRL_RWMOD_Msk   (0x1UL << SDIO_DCTRL_RWMOD_Pos)
     
    #define SDIO_DCTRL_RWMOD   SDIO_DCTRL_RWMOD_Msk
     
    #define SDIO_DCTRL_SDIOEN_Pos   (11U)
     
    #define SDIO_DCTRL_SDIOEN_Msk   (0x1UL << SDIO_DCTRL_SDIOEN_Pos)
     
    #define SDIO_DCTRL_SDIOEN   SDIO_DCTRL_SDIOEN_Msk
     
    #define SDIO_DCOUNT_DATACOUNT_Pos   (0U)
     
    #define SDIO_DCOUNT_DATACOUNT_Msk   (0x1FFFFFFUL << SDIO_DCOUNT_DATACOUNT_Pos)
     
    #define SDIO_DCOUNT_DATACOUNT   SDIO_DCOUNT_DATACOUNT_Msk
     
    #define SDIO_STA_CCRCFAIL_Pos   (0U)
     
    #define SDIO_STA_CCRCFAIL_Msk   (0x1UL << SDIO_STA_CCRCFAIL_Pos)
     
    #define SDIO_STA_CCRCFAIL   SDIO_STA_CCRCFAIL_Msk
     
    #define SDIO_STA_DCRCFAIL_Pos   (1U)
     
    #define SDIO_STA_DCRCFAIL_Msk   (0x1UL << SDIO_STA_DCRCFAIL_Pos)
     
    #define SDIO_STA_DCRCFAIL   SDIO_STA_DCRCFAIL_Msk
     
    #define SDIO_STA_CTIMEOUT_Pos   (2U)
     
    #define SDIO_STA_CTIMEOUT_Msk   (0x1UL << SDIO_STA_CTIMEOUT_Pos)
     
    #define SDIO_STA_CTIMEOUT   SDIO_STA_CTIMEOUT_Msk
     
    #define SDIO_STA_DTIMEOUT_Pos   (3U)
     
    #define SDIO_STA_DTIMEOUT_Msk   (0x1UL << SDIO_STA_DTIMEOUT_Pos)
     
    #define SDIO_STA_DTIMEOUT   SDIO_STA_DTIMEOUT_Msk
     
    #define SDIO_STA_TXUNDERR_Pos   (4U)
     
    #define SDIO_STA_TXUNDERR_Msk   (0x1UL << SDIO_STA_TXUNDERR_Pos)
     
    #define SDIO_STA_TXUNDERR   SDIO_STA_TXUNDERR_Msk
     
    #define SDIO_STA_RXOVERR_Pos   (5U)
     
    #define SDIO_STA_RXOVERR_Msk   (0x1UL << SDIO_STA_RXOVERR_Pos)
     
    #define SDIO_STA_RXOVERR   SDIO_STA_RXOVERR_Msk
     
    #define SDIO_STA_CMDREND_Pos   (6U)
     
    #define SDIO_STA_CMDREND_Msk   (0x1UL << SDIO_STA_CMDREND_Pos)
     
    #define SDIO_STA_CMDREND   SDIO_STA_CMDREND_Msk
     
    #define SDIO_STA_CMDSENT_Pos   (7U)
     
    #define SDIO_STA_CMDSENT_Msk   (0x1UL << SDIO_STA_CMDSENT_Pos)
     
    #define SDIO_STA_CMDSENT   SDIO_STA_CMDSENT_Msk
     
    #define SDIO_STA_DATAEND_Pos   (8U)
     
    #define SDIO_STA_DATAEND_Msk   (0x1UL << SDIO_STA_DATAEND_Pos)
     
    #define SDIO_STA_DATAEND   SDIO_STA_DATAEND_Msk
     
    #define SDIO_STA_STBITERR_Pos   (9U)
     
    #define SDIO_STA_STBITERR_Msk   (0x1UL << SDIO_STA_STBITERR_Pos)
     
    #define SDIO_STA_STBITERR   SDIO_STA_STBITERR_Msk
     
    #define SDIO_STA_DBCKEND_Pos   (10U)
     
    #define SDIO_STA_DBCKEND_Msk   (0x1UL << SDIO_STA_DBCKEND_Pos)
     
    #define SDIO_STA_DBCKEND   SDIO_STA_DBCKEND_Msk
     
    #define SDIO_STA_CMDACT_Pos   (11U)
     
    #define SDIO_STA_CMDACT_Msk   (0x1UL << SDIO_STA_CMDACT_Pos)
     
    #define SDIO_STA_CMDACT   SDIO_STA_CMDACT_Msk
     
    #define SDIO_STA_TXACT_Pos   (12U)
     
    #define SDIO_STA_TXACT_Msk   (0x1UL << SDIO_STA_TXACT_Pos)
     
    #define SDIO_STA_TXACT   SDIO_STA_TXACT_Msk
     
    #define SDIO_STA_RXACT_Pos   (13U)
     
    #define SDIO_STA_RXACT_Msk   (0x1UL << SDIO_STA_RXACT_Pos)
     
    #define SDIO_STA_RXACT   SDIO_STA_RXACT_Msk
     
    #define SDIO_STA_TXFIFOHE_Pos   (14U)
     
    #define SDIO_STA_TXFIFOHE_Msk   (0x1UL << SDIO_STA_TXFIFOHE_Pos)
     
    #define SDIO_STA_TXFIFOHE   SDIO_STA_TXFIFOHE_Msk
     
    #define SDIO_STA_RXFIFOHF_Pos   (15U)
     
    #define SDIO_STA_RXFIFOHF_Msk   (0x1UL << SDIO_STA_RXFIFOHF_Pos)
     
    #define SDIO_STA_RXFIFOHF   SDIO_STA_RXFIFOHF_Msk
     
    #define SDIO_STA_TXFIFOF_Pos   (16U)
     
    #define SDIO_STA_TXFIFOF_Msk   (0x1UL << SDIO_STA_TXFIFOF_Pos)
     
    #define SDIO_STA_TXFIFOF   SDIO_STA_TXFIFOF_Msk
     
    #define SDIO_STA_RXFIFOF_Pos   (17U)
     
    #define SDIO_STA_RXFIFOF_Msk   (0x1UL << SDIO_STA_RXFIFOF_Pos)
     
    #define SDIO_STA_RXFIFOF   SDIO_STA_RXFIFOF_Msk
     
    #define SDIO_STA_TXFIFOE_Pos   (18U)
     
    #define SDIO_STA_TXFIFOE_Msk   (0x1UL << SDIO_STA_TXFIFOE_Pos)
     
    #define SDIO_STA_TXFIFOE   SDIO_STA_TXFIFOE_Msk
     
    #define SDIO_STA_RXFIFOE_Pos   (19U)
     
    #define SDIO_STA_RXFIFOE_Msk   (0x1UL << SDIO_STA_RXFIFOE_Pos)
     
    #define SDIO_STA_RXFIFOE   SDIO_STA_RXFIFOE_Msk
     
    #define SDIO_STA_TXDAVL_Pos   (20U)
     
    #define SDIO_STA_TXDAVL_Msk   (0x1UL << SDIO_STA_TXDAVL_Pos)
     
    #define SDIO_STA_TXDAVL   SDIO_STA_TXDAVL_Msk
     
    #define SDIO_STA_RXDAVL_Pos   (21U)
     
    #define SDIO_STA_RXDAVL_Msk   (0x1UL << SDIO_STA_RXDAVL_Pos)
     
    #define SDIO_STA_RXDAVL   SDIO_STA_RXDAVL_Msk
     
    #define SDIO_STA_SDIOIT_Pos   (22U)
     
    #define SDIO_STA_SDIOIT_Msk   (0x1UL << SDIO_STA_SDIOIT_Pos)
     
    #define SDIO_STA_SDIOIT   SDIO_STA_SDIOIT_Msk
     
    #define SDIO_STA_CEATAEND_Pos   (23U)
     
    #define SDIO_STA_CEATAEND_Msk   (0x1UL << SDIO_STA_CEATAEND_Pos)
     
    #define SDIO_STA_CEATAEND   SDIO_STA_CEATAEND_Msk
     
    #define SDIO_ICR_CCRCFAILC_Pos   (0U)
     
    #define SDIO_ICR_CCRCFAILC_Msk   (0x1UL << SDIO_ICR_CCRCFAILC_Pos)
     
    #define SDIO_ICR_CCRCFAILC   SDIO_ICR_CCRCFAILC_Msk
     
    #define SDIO_ICR_DCRCFAILC_Pos   (1U)
     
    #define SDIO_ICR_DCRCFAILC_Msk   (0x1UL << SDIO_ICR_DCRCFAILC_Pos)
     
    #define SDIO_ICR_DCRCFAILC   SDIO_ICR_DCRCFAILC_Msk
     
    #define SDIO_ICR_CTIMEOUTC_Pos   (2U)
     
    #define SDIO_ICR_CTIMEOUTC_Msk   (0x1UL << SDIO_ICR_CTIMEOUTC_Pos)
     
    #define SDIO_ICR_CTIMEOUTC   SDIO_ICR_CTIMEOUTC_Msk
     
    #define SDIO_ICR_DTIMEOUTC_Pos   (3U)
     
    #define SDIO_ICR_DTIMEOUTC_Msk   (0x1UL << SDIO_ICR_DTIMEOUTC_Pos)
     
    #define SDIO_ICR_DTIMEOUTC   SDIO_ICR_DTIMEOUTC_Msk
     
    #define SDIO_ICR_TXUNDERRC_Pos   (4U)
     
    #define SDIO_ICR_TXUNDERRC_Msk   (0x1UL << SDIO_ICR_TXUNDERRC_Pos)
     
    #define SDIO_ICR_TXUNDERRC   SDIO_ICR_TXUNDERRC_Msk
     
    #define SDIO_ICR_RXOVERRC_Pos   (5U)
     
    #define SDIO_ICR_RXOVERRC_Msk   (0x1UL << SDIO_ICR_RXOVERRC_Pos)
     
    #define SDIO_ICR_RXOVERRC   SDIO_ICR_RXOVERRC_Msk
     
    #define SDIO_ICR_CMDRENDC_Pos   (6U)
     
    #define SDIO_ICR_CMDRENDC_Msk   (0x1UL << SDIO_ICR_CMDRENDC_Pos)
     
    #define SDIO_ICR_CMDRENDC   SDIO_ICR_CMDRENDC_Msk
     
    #define SDIO_ICR_CMDSENTC_Pos   (7U)
     
    #define SDIO_ICR_CMDSENTC_Msk   (0x1UL << SDIO_ICR_CMDSENTC_Pos)
     
    #define SDIO_ICR_CMDSENTC   SDIO_ICR_CMDSENTC_Msk
     
    #define SDIO_ICR_DATAENDC_Pos   (8U)
     
    #define SDIO_ICR_DATAENDC_Msk   (0x1UL << SDIO_ICR_DATAENDC_Pos)
     
    #define SDIO_ICR_DATAENDC   SDIO_ICR_DATAENDC_Msk
     
    #define SDIO_ICR_STBITERRC_Pos   (9U)
     
    #define SDIO_ICR_STBITERRC_Msk   (0x1UL << SDIO_ICR_STBITERRC_Pos)
     
    #define SDIO_ICR_STBITERRC   SDIO_ICR_STBITERRC_Msk
     
    #define SDIO_ICR_DBCKENDC_Pos   (10U)
     
    #define SDIO_ICR_DBCKENDC_Msk   (0x1UL << SDIO_ICR_DBCKENDC_Pos)
     
    #define SDIO_ICR_DBCKENDC   SDIO_ICR_DBCKENDC_Msk
     
    #define SDIO_ICR_SDIOITC_Pos   (22U)
     
    #define SDIO_ICR_SDIOITC_Msk   (0x1UL << SDIO_ICR_SDIOITC_Pos)
     
    #define SDIO_ICR_SDIOITC   SDIO_ICR_SDIOITC_Msk
     
    #define SDIO_ICR_CEATAENDC_Pos   (23U)
     
    #define SDIO_ICR_CEATAENDC_Msk   (0x1UL << SDIO_ICR_CEATAENDC_Pos)
     
    #define SDIO_ICR_CEATAENDC   SDIO_ICR_CEATAENDC_Msk
     
    #define SDIO_MASK_CCRCFAILIE_Pos   (0U)
     
    #define SDIO_MASK_CCRCFAILIE_Msk   (0x1UL << SDIO_MASK_CCRCFAILIE_Pos)
     
    #define SDIO_MASK_CCRCFAILIE   SDIO_MASK_CCRCFAILIE_Msk
     
    #define SDIO_MASK_DCRCFAILIE_Pos   (1U)
     
    #define SDIO_MASK_DCRCFAILIE_Msk   (0x1UL << SDIO_MASK_DCRCFAILIE_Pos)
     
    #define SDIO_MASK_DCRCFAILIE   SDIO_MASK_DCRCFAILIE_Msk
     
    #define SDIO_MASK_CTIMEOUTIE_Pos   (2U)
     
    #define SDIO_MASK_CTIMEOUTIE_Msk   (0x1UL << SDIO_MASK_CTIMEOUTIE_Pos)
     
    #define SDIO_MASK_CTIMEOUTIE   SDIO_MASK_CTIMEOUTIE_Msk
     
    #define SDIO_MASK_DTIMEOUTIE_Pos   (3U)
     
    #define SDIO_MASK_DTIMEOUTIE_Msk   (0x1UL << SDIO_MASK_DTIMEOUTIE_Pos)
     
    #define SDIO_MASK_DTIMEOUTIE   SDIO_MASK_DTIMEOUTIE_Msk
     
    #define SDIO_MASK_TXUNDERRIE_Pos   (4U)
     
    #define SDIO_MASK_TXUNDERRIE_Msk   (0x1UL << SDIO_MASK_TXUNDERRIE_Pos)
     
    #define SDIO_MASK_TXUNDERRIE   SDIO_MASK_TXUNDERRIE_Msk
     
    #define SDIO_MASK_RXOVERRIE_Pos   (5U)
     
    #define SDIO_MASK_RXOVERRIE_Msk   (0x1UL << SDIO_MASK_RXOVERRIE_Pos)
     
    #define SDIO_MASK_RXOVERRIE   SDIO_MASK_RXOVERRIE_Msk
     
    #define SDIO_MASK_CMDRENDIE_Pos   (6U)
     
    #define SDIO_MASK_CMDRENDIE_Msk   (0x1UL << SDIO_MASK_CMDRENDIE_Pos)
     
    #define SDIO_MASK_CMDRENDIE   SDIO_MASK_CMDRENDIE_Msk
     
    #define SDIO_MASK_CMDSENTIE_Pos   (7U)
     
    #define SDIO_MASK_CMDSENTIE_Msk   (0x1UL << SDIO_MASK_CMDSENTIE_Pos)
     
    #define SDIO_MASK_CMDSENTIE   SDIO_MASK_CMDSENTIE_Msk
     
    #define SDIO_MASK_DATAENDIE_Pos   (8U)
     
    #define SDIO_MASK_DATAENDIE_Msk   (0x1UL << SDIO_MASK_DATAENDIE_Pos)
     
    #define SDIO_MASK_DATAENDIE   SDIO_MASK_DATAENDIE_Msk
     
    #define SDIO_MASK_STBITERRIE_Pos   (9U)
     
    #define SDIO_MASK_STBITERRIE_Msk   (0x1UL << SDIO_MASK_STBITERRIE_Pos)
     
    #define SDIO_MASK_STBITERRIE   SDIO_MASK_STBITERRIE_Msk
     
    #define SDIO_MASK_DBCKENDIE_Pos   (10U)
     
    #define SDIO_MASK_DBCKENDIE_Msk   (0x1UL << SDIO_MASK_DBCKENDIE_Pos)
     
    #define SDIO_MASK_DBCKENDIE   SDIO_MASK_DBCKENDIE_Msk
     
    #define SDIO_MASK_CMDACTIE_Pos   (11U)
     
    #define SDIO_MASK_CMDACTIE_Msk   (0x1UL << SDIO_MASK_CMDACTIE_Pos)
     
    #define SDIO_MASK_CMDACTIE   SDIO_MASK_CMDACTIE_Msk
     
    #define SDIO_MASK_TXACTIE_Pos   (12U)
     
    #define SDIO_MASK_TXACTIE_Msk   (0x1UL << SDIO_MASK_TXACTIE_Pos)
     
    #define SDIO_MASK_TXACTIE   SDIO_MASK_TXACTIE_Msk
     
    #define SDIO_MASK_RXACTIE_Pos   (13U)
     
    #define SDIO_MASK_RXACTIE_Msk   (0x1UL << SDIO_MASK_RXACTIE_Pos)
     
    #define SDIO_MASK_RXACTIE   SDIO_MASK_RXACTIE_Msk
     
    #define SDIO_MASK_TXFIFOHEIE_Pos   (14U)
     
    #define SDIO_MASK_TXFIFOHEIE_Msk   (0x1UL << SDIO_MASK_TXFIFOHEIE_Pos)
     
    #define SDIO_MASK_TXFIFOHEIE   SDIO_MASK_TXFIFOHEIE_Msk
     
    #define SDIO_MASK_RXFIFOHFIE_Pos   (15U)
     
    #define SDIO_MASK_RXFIFOHFIE_Msk   (0x1UL << SDIO_MASK_RXFIFOHFIE_Pos)
     
    #define SDIO_MASK_RXFIFOHFIE   SDIO_MASK_RXFIFOHFIE_Msk
     
    #define SDIO_MASK_TXFIFOFIE_Pos   (16U)
     
    #define SDIO_MASK_TXFIFOFIE_Msk   (0x1UL << SDIO_MASK_TXFIFOFIE_Pos)
     
    #define SDIO_MASK_TXFIFOFIE   SDIO_MASK_TXFIFOFIE_Msk
     
    #define SDIO_MASK_RXFIFOFIE_Pos   (17U)
     
    #define SDIO_MASK_RXFIFOFIE_Msk   (0x1UL << SDIO_MASK_RXFIFOFIE_Pos)
     
    #define SDIO_MASK_RXFIFOFIE   SDIO_MASK_RXFIFOFIE_Msk
     
    #define SDIO_MASK_TXFIFOEIE_Pos   (18U)
     
    #define SDIO_MASK_TXFIFOEIE_Msk   (0x1UL << SDIO_MASK_TXFIFOEIE_Pos)
     
    #define SDIO_MASK_TXFIFOEIE   SDIO_MASK_TXFIFOEIE_Msk
     
    #define SDIO_MASK_RXFIFOEIE_Pos   (19U)
     
    #define SDIO_MASK_RXFIFOEIE_Msk   (0x1UL << SDIO_MASK_RXFIFOEIE_Pos)
     
    #define SDIO_MASK_RXFIFOEIE   SDIO_MASK_RXFIFOEIE_Msk
     
    #define SDIO_MASK_TXDAVLIE_Pos   (20U)
     
    #define SDIO_MASK_TXDAVLIE_Msk   (0x1UL << SDIO_MASK_TXDAVLIE_Pos)
     
    #define SDIO_MASK_TXDAVLIE   SDIO_MASK_TXDAVLIE_Msk
     
    #define SDIO_MASK_RXDAVLIE_Pos   (21U)
     
    #define SDIO_MASK_RXDAVLIE_Msk   (0x1UL << SDIO_MASK_RXDAVLIE_Pos)
     
    #define SDIO_MASK_RXDAVLIE   SDIO_MASK_RXDAVLIE_Msk
     
    #define SDIO_MASK_SDIOITIE_Pos   (22U)
     
    #define SDIO_MASK_SDIOITIE_Msk   (0x1UL << SDIO_MASK_SDIOITIE_Pos)
     
    #define SDIO_MASK_SDIOITIE   SDIO_MASK_SDIOITIE_Msk
     
    #define SDIO_MASK_CEATAENDIE_Pos   (23U)
     
    #define SDIO_MASK_CEATAENDIE_Msk   (0x1UL << SDIO_MASK_CEATAENDIE_Pos)
     
    #define SDIO_MASK_CEATAENDIE   SDIO_MASK_CEATAENDIE_Msk
     
    #define SDIO_FIFOCNT_FIFOCOUNT_Pos   (0U)
     
    #define SDIO_FIFOCNT_FIFOCOUNT_Msk   (0xFFFFFFUL << SDIO_FIFOCNT_FIFOCOUNT_Pos)
     
    #define SDIO_FIFOCNT_FIFOCOUNT   SDIO_FIFOCNT_FIFOCOUNT_Msk
     
    #define SDIO_FIFO_FIFODATA_Pos   (0U)
     
    #define SDIO_FIFO_FIFODATA_Msk   (0xFFFFFFFFUL << SDIO_FIFO_FIFODATA_Pos)
     
    #define SDIO_FIFO_FIFODATA   SDIO_FIFO_FIFODATA_Msk
     
    #define SPI_I2S_FULLDUPLEX_SUPPORT
     
    #define SPI_CR1_CPHA_Pos   (0U)
     
    #define SPI_CR1_CPHA_Msk   (0x1UL << SPI_CR1_CPHA_Pos)
     
    #define SPI_CR1_CPHA   SPI_CR1_CPHA_Msk
     
    #define SPI_CR1_CPOL_Pos   (1U)
     
    #define SPI_CR1_CPOL_Msk   (0x1UL << SPI_CR1_CPOL_Pos)
     
    #define SPI_CR1_CPOL   SPI_CR1_CPOL_Msk
     
    #define SPI_CR1_MSTR_Pos   (2U)
     
    #define SPI_CR1_MSTR_Msk   (0x1UL << SPI_CR1_MSTR_Pos)
     
    #define SPI_CR1_MSTR   SPI_CR1_MSTR_Msk
     
    #define SPI_CR1_BR_Pos   (3U)
     
    #define SPI_CR1_BR_Msk   (0x7UL << SPI_CR1_BR_Pos)
     
    #define SPI_CR1_BR   SPI_CR1_BR_Msk
     
    #define SPI_CR1_BR_0   (0x1UL << SPI_CR1_BR_Pos)
     
    #define SPI_CR1_BR_1   (0x2UL << SPI_CR1_BR_Pos)
     
    #define SPI_CR1_BR_2   (0x4UL << SPI_CR1_BR_Pos)
     
    #define SPI_CR1_SPE_Pos   (6U)
     
    #define SPI_CR1_SPE_Msk   (0x1UL << SPI_CR1_SPE_Pos)
     
    #define SPI_CR1_SPE   SPI_CR1_SPE_Msk
     
    #define SPI_CR1_LSBFIRST_Pos   (7U)
     
    #define SPI_CR1_LSBFIRST_Msk   (0x1UL << SPI_CR1_LSBFIRST_Pos)
     
    #define SPI_CR1_LSBFIRST   SPI_CR1_LSBFIRST_Msk
     
    #define SPI_CR1_SSI_Pos   (8U)
     
    #define SPI_CR1_SSI_Msk   (0x1UL << SPI_CR1_SSI_Pos)
     
    #define SPI_CR1_SSI   SPI_CR1_SSI_Msk
     
    #define SPI_CR1_SSM_Pos   (9U)
     
    #define SPI_CR1_SSM_Msk   (0x1UL << SPI_CR1_SSM_Pos)
     
    #define SPI_CR1_SSM   SPI_CR1_SSM_Msk
     
    #define SPI_CR1_RXONLY_Pos   (10U)
     
    #define SPI_CR1_RXONLY_Msk   (0x1UL << SPI_CR1_RXONLY_Pos)
     
    #define SPI_CR1_RXONLY   SPI_CR1_RXONLY_Msk
     
    #define SPI_CR1_DFF_Pos   (11U)
     
    #define SPI_CR1_DFF_Msk   (0x1UL << SPI_CR1_DFF_Pos)
     
    #define SPI_CR1_DFF   SPI_CR1_DFF_Msk
     
    #define SPI_CR1_CRCNEXT_Pos   (12U)
     
    #define SPI_CR1_CRCNEXT_Msk   (0x1UL << SPI_CR1_CRCNEXT_Pos)
     
    #define SPI_CR1_CRCNEXT   SPI_CR1_CRCNEXT_Msk
     
    #define SPI_CR1_CRCEN_Pos   (13U)
     
    #define SPI_CR1_CRCEN_Msk   (0x1UL << SPI_CR1_CRCEN_Pos)
     
    #define SPI_CR1_CRCEN   SPI_CR1_CRCEN_Msk
     
    #define SPI_CR1_BIDIOE_Pos   (14U)
     
    #define SPI_CR1_BIDIOE_Msk   (0x1UL << SPI_CR1_BIDIOE_Pos)
     
    #define SPI_CR1_BIDIOE   SPI_CR1_BIDIOE_Msk
     
    #define SPI_CR1_BIDIMODE_Pos   (15U)
     
    #define SPI_CR1_BIDIMODE_Msk   (0x1UL << SPI_CR1_BIDIMODE_Pos)
     
    #define SPI_CR1_BIDIMODE   SPI_CR1_BIDIMODE_Msk
     
    #define SPI_CR2_RXDMAEN_Pos   (0U)
     
    #define SPI_CR2_RXDMAEN_Msk   (0x1UL << SPI_CR2_RXDMAEN_Pos)
     
    #define SPI_CR2_RXDMAEN   SPI_CR2_RXDMAEN_Msk
     
    #define SPI_CR2_TXDMAEN_Pos   (1U)
     
    #define SPI_CR2_TXDMAEN_Msk   (0x1UL << SPI_CR2_TXDMAEN_Pos)
     
    #define SPI_CR2_TXDMAEN   SPI_CR2_TXDMAEN_Msk
     
    #define SPI_CR2_SSOE_Pos   (2U)
     
    #define SPI_CR2_SSOE_Msk   (0x1UL << SPI_CR2_SSOE_Pos)
     
    #define SPI_CR2_SSOE   SPI_CR2_SSOE_Msk
     
    #define SPI_CR2_FRF_Pos   (4U)
     
    #define SPI_CR2_FRF_Msk   (0x1UL << SPI_CR2_FRF_Pos)
     
    #define SPI_CR2_FRF   SPI_CR2_FRF_Msk
     
    #define SPI_CR2_ERRIE_Pos   (5U)
     
    #define SPI_CR2_ERRIE_Msk   (0x1UL << SPI_CR2_ERRIE_Pos)
     
    #define SPI_CR2_ERRIE   SPI_CR2_ERRIE_Msk
     
    #define SPI_CR2_RXNEIE_Pos   (6U)
     
    #define SPI_CR2_RXNEIE_Msk   (0x1UL << SPI_CR2_RXNEIE_Pos)
     
    #define SPI_CR2_RXNEIE   SPI_CR2_RXNEIE_Msk
     
    #define SPI_CR2_TXEIE_Pos   (7U)
     
    #define SPI_CR2_TXEIE_Msk   (0x1UL << SPI_CR2_TXEIE_Pos)
     
    #define SPI_CR2_TXEIE   SPI_CR2_TXEIE_Msk
     
    #define SPI_SR_RXNE_Pos   (0U)
     
    #define SPI_SR_RXNE_Msk   (0x1UL << SPI_SR_RXNE_Pos)
     
    #define SPI_SR_RXNE   SPI_SR_RXNE_Msk
     
    #define SPI_SR_TXE_Pos   (1U)
     
    #define SPI_SR_TXE_Msk   (0x1UL << SPI_SR_TXE_Pos)
     
    #define SPI_SR_TXE   SPI_SR_TXE_Msk
     
    #define SPI_SR_CHSIDE_Pos   (2U)
     
    #define SPI_SR_CHSIDE_Msk   (0x1UL << SPI_SR_CHSIDE_Pos)
     
    #define SPI_SR_CHSIDE   SPI_SR_CHSIDE_Msk
     
    #define SPI_SR_UDR_Pos   (3U)
     
    #define SPI_SR_UDR_Msk   (0x1UL << SPI_SR_UDR_Pos)
     
    #define SPI_SR_UDR   SPI_SR_UDR_Msk
     
    #define SPI_SR_CRCERR_Pos   (4U)
     
    #define SPI_SR_CRCERR_Msk   (0x1UL << SPI_SR_CRCERR_Pos)
     
    #define SPI_SR_CRCERR   SPI_SR_CRCERR_Msk
     
    #define SPI_SR_MODF_Pos   (5U)
     
    #define SPI_SR_MODF_Msk   (0x1UL << SPI_SR_MODF_Pos)
     
    #define SPI_SR_MODF   SPI_SR_MODF_Msk
     
    #define SPI_SR_OVR_Pos   (6U)
     
    #define SPI_SR_OVR_Msk   (0x1UL << SPI_SR_OVR_Pos)
     
    #define SPI_SR_OVR   SPI_SR_OVR_Msk
     
    #define SPI_SR_BSY_Pos   (7U)
     
    #define SPI_SR_BSY_Msk   (0x1UL << SPI_SR_BSY_Pos)
     
    #define SPI_SR_BSY   SPI_SR_BSY_Msk
     
    #define SPI_SR_FRE_Pos   (8U)
     
    #define SPI_SR_FRE_Msk   (0x1UL << SPI_SR_FRE_Pos)
     
    #define SPI_SR_FRE   SPI_SR_FRE_Msk
     
    #define SPI_DR_DR_Pos   (0U)
     
    #define SPI_DR_DR_Msk   (0xFFFFUL << SPI_DR_DR_Pos)
     
    #define SPI_DR_DR   SPI_DR_DR_Msk
     
    #define SPI_CRCPR_CRCPOLY_Pos   (0U)
     
    #define SPI_CRCPR_CRCPOLY_Msk   (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos)
     
    #define SPI_CRCPR_CRCPOLY   SPI_CRCPR_CRCPOLY_Msk
     
    #define SPI_RXCRCR_RXCRC_Pos   (0U)
     
    #define SPI_RXCRCR_RXCRC_Msk   (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos)
     
    #define SPI_RXCRCR_RXCRC   SPI_RXCRCR_RXCRC_Msk
     
    #define SPI_TXCRCR_TXCRC_Pos   (0U)
     
    #define SPI_TXCRCR_TXCRC_Msk   (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos)
     
    #define SPI_TXCRCR_TXCRC   SPI_TXCRCR_TXCRC_Msk
     
    #define SPI_I2SCFGR_CHLEN_Pos   (0U)
     
    #define SPI_I2SCFGR_CHLEN_Msk   (0x1UL << SPI_I2SCFGR_CHLEN_Pos)
     
    #define SPI_I2SCFGR_CHLEN   SPI_I2SCFGR_CHLEN_Msk
     
    #define SPI_I2SCFGR_DATLEN_Pos   (1U)
     
    #define SPI_I2SCFGR_DATLEN_Msk   (0x3UL << SPI_I2SCFGR_DATLEN_Pos)
     
    #define SPI_I2SCFGR_DATLEN   SPI_I2SCFGR_DATLEN_Msk
     
    #define SPI_I2SCFGR_DATLEN_0   (0x1UL << SPI_I2SCFGR_DATLEN_Pos)
     
    #define SPI_I2SCFGR_DATLEN_1   (0x2UL << SPI_I2SCFGR_DATLEN_Pos)
     
    #define SPI_I2SCFGR_CKPOL_Pos   (3U)
     
    #define SPI_I2SCFGR_CKPOL_Msk   (0x1UL << SPI_I2SCFGR_CKPOL_Pos)
     
    #define SPI_I2SCFGR_CKPOL   SPI_I2SCFGR_CKPOL_Msk
     
    #define SPI_I2SCFGR_I2SSTD_Pos   (4U)
     
    #define SPI_I2SCFGR_I2SSTD_Msk   (0x3UL << SPI_I2SCFGR_I2SSTD_Pos)
     
    #define SPI_I2SCFGR_I2SSTD   SPI_I2SCFGR_I2SSTD_Msk
     
    #define SPI_I2SCFGR_I2SSTD_0   (0x1UL << SPI_I2SCFGR_I2SSTD_Pos)
     
    #define SPI_I2SCFGR_I2SSTD_1   (0x2UL << SPI_I2SCFGR_I2SSTD_Pos)
     
    #define SPI_I2SCFGR_PCMSYNC_Pos   (7U)
     
    #define SPI_I2SCFGR_PCMSYNC_Msk   (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos)
     
    #define SPI_I2SCFGR_PCMSYNC   SPI_I2SCFGR_PCMSYNC_Msk
     
    #define SPI_I2SCFGR_I2SCFG_Pos   (8U)
     
    #define SPI_I2SCFGR_I2SCFG_Msk   (0x3UL << SPI_I2SCFGR_I2SCFG_Pos)
     
    #define SPI_I2SCFGR_I2SCFG   SPI_I2SCFGR_I2SCFG_Msk
     
    #define SPI_I2SCFGR_I2SCFG_0   (0x1UL << SPI_I2SCFGR_I2SCFG_Pos)
     
    #define SPI_I2SCFGR_I2SCFG_1   (0x2UL << SPI_I2SCFGR_I2SCFG_Pos)
     
    #define SPI_I2SCFGR_I2SE_Pos   (10U)
     
    #define SPI_I2SCFGR_I2SE_Msk   (0x1UL << SPI_I2SCFGR_I2SE_Pos)
     
    #define SPI_I2SCFGR_I2SE   SPI_I2SCFGR_I2SE_Msk
     
    #define SPI_I2SCFGR_I2SMOD_Pos   (11U)
     
    #define SPI_I2SCFGR_I2SMOD_Msk   (0x1UL << SPI_I2SCFGR_I2SMOD_Pos)
     
    #define SPI_I2SCFGR_I2SMOD   SPI_I2SCFGR_I2SMOD_Msk
     
    #define SPI_I2SPR_I2SDIV_Pos   (0U)
     
    #define SPI_I2SPR_I2SDIV_Msk   (0xFFUL << SPI_I2SPR_I2SDIV_Pos)
     
    #define SPI_I2SPR_I2SDIV   SPI_I2SPR_I2SDIV_Msk
     
    #define SPI_I2SPR_ODD_Pos   (8U)
     
    #define SPI_I2SPR_ODD_Msk   (0x1UL << SPI_I2SPR_ODD_Pos)
     
    #define SPI_I2SPR_ODD   SPI_I2SPR_ODD_Msk
     
    #define SPI_I2SPR_MCKOE_Pos   (9U)
     
    #define SPI_I2SPR_MCKOE_Msk   (0x1UL << SPI_I2SPR_MCKOE_Pos)
     
    #define SPI_I2SPR_MCKOE   SPI_I2SPR_MCKOE_Msk
     
    #define SYSCFG_MEMRMP_MEM_MODE_Pos   (0U)
     
    #define SYSCFG_MEMRMP_MEM_MODE_Msk   (0x3UL << SYSCFG_MEMRMP_MEM_MODE_Pos)
     
    #define SYSCFG_MEMRMP_MEM_MODE   SYSCFG_MEMRMP_MEM_MODE_Msk
     
    #define SYSCFG_MEMRMP_MEM_MODE_0   (0x1UL << SYSCFG_MEMRMP_MEM_MODE_Pos)
     
    #define SYSCFG_MEMRMP_MEM_MODE_1   (0x2UL << SYSCFG_MEMRMP_MEM_MODE_Pos)
     
    #define SYSCFG_PMC_MII_RMII_SEL_Pos   (23U)
     
    #define SYSCFG_PMC_MII_RMII_SEL_Msk   (0x1UL << SYSCFG_PMC_MII_RMII_SEL_Pos)
     
    #define SYSCFG_PMC_MII_RMII_SEL   SYSCFG_PMC_MII_RMII_SEL_Msk
     
    #define SYSCFG_PMC_MII_RMII   SYSCFG_PMC_MII_RMII_SEL
     
    #define SYSCFG_EXTICR1_EXTI0_Pos   (0U)
     
    #define SYSCFG_EXTICR1_EXTI0_Msk   (0xFUL << SYSCFG_EXTICR1_EXTI0_Pos)
     
    #define SYSCFG_EXTICR1_EXTI0   SYSCFG_EXTICR1_EXTI0_Msk
     
    #define SYSCFG_EXTICR1_EXTI1_Pos   (4U)
     
    #define SYSCFG_EXTICR1_EXTI1_Msk   (0xFUL << SYSCFG_EXTICR1_EXTI1_Pos)
     
    #define SYSCFG_EXTICR1_EXTI1   SYSCFG_EXTICR1_EXTI1_Msk
     
    #define SYSCFG_EXTICR1_EXTI2_Pos   (8U)
     
    #define SYSCFG_EXTICR1_EXTI2_Msk   (0xFUL << SYSCFG_EXTICR1_EXTI2_Pos)
     
    #define SYSCFG_EXTICR1_EXTI2   SYSCFG_EXTICR1_EXTI2_Msk
     
    #define SYSCFG_EXTICR1_EXTI3_Pos   (12U)
     
    #define SYSCFG_EXTICR1_EXTI3_Msk   (0xFUL << SYSCFG_EXTICR1_EXTI3_Pos)
     
    #define SYSCFG_EXTICR1_EXTI3   SYSCFG_EXTICR1_EXTI3_Msk
     
    #define SYSCFG_EXTICR1_EXTI0_PA   0x0000U
     EXTI0 configuration
    -
     
    #define SYSCFG_EXTICR1_EXTI0_PB   0x0001U
     
    #define SYSCFG_EXTICR1_EXTI0_PC   0x0002U
     
    #define SYSCFG_EXTICR1_EXTI0_PD   0x0003U
     
    #define SYSCFG_EXTICR1_EXTI0_PE   0x0004U
     
    #define SYSCFG_EXTICR1_EXTI0_PF   0x0005U
     
    #define SYSCFG_EXTICR1_EXTI0_PG   0x0006U
     
    #define SYSCFG_EXTICR1_EXTI0_PH   0x0007U
     
    #define SYSCFG_EXTICR1_EXTI0_PI   0x0008U
     
    #define SYSCFG_EXTICR1_EXTI1_PA   0x0000U
     EXTI1 configuration
    -
     
    #define SYSCFG_EXTICR1_EXTI1_PB   0x0010U
     
    #define SYSCFG_EXTICR1_EXTI1_PC   0x0020U
     
    #define SYSCFG_EXTICR1_EXTI1_PD   0x0030U
     
    #define SYSCFG_EXTICR1_EXTI1_PE   0x0040U
     
    #define SYSCFG_EXTICR1_EXTI1_PF   0x0050U
     
    #define SYSCFG_EXTICR1_EXTI1_PG   0x0060U
     
    #define SYSCFG_EXTICR1_EXTI1_PH   0x0070U
     
    #define SYSCFG_EXTICR1_EXTI1_PI   0x0080U
     
    #define SYSCFG_EXTICR1_EXTI2_PA   0x0000U
     EXTI2 configuration
    -
     
    #define SYSCFG_EXTICR1_EXTI2_PB   0x0100U
     
    #define SYSCFG_EXTICR1_EXTI2_PC   0x0200U
     
    #define SYSCFG_EXTICR1_EXTI2_PD   0x0300U
     
    #define SYSCFG_EXTICR1_EXTI2_PE   0x0400U
     
    #define SYSCFG_EXTICR1_EXTI2_PF   0x0500U
     
    #define SYSCFG_EXTICR1_EXTI2_PG   0x0600U
     
    #define SYSCFG_EXTICR1_EXTI2_PH   0x0700U
     
    #define SYSCFG_EXTICR1_EXTI2_PI   0x0800U
     
    #define SYSCFG_EXTICR1_EXTI3_PA   0x0000U
     EXTI3 configuration
    -
     
    #define SYSCFG_EXTICR1_EXTI3_PB   0x1000U
     
    #define SYSCFG_EXTICR1_EXTI3_PC   0x2000U
     
    #define SYSCFG_EXTICR1_EXTI3_PD   0x3000U
     
    #define SYSCFG_EXTICR1_EXTI3_PE   0x4000U
     
    #define SYSCFG_EXTICR1_EXTI3_PF   0x5000U
     
    #define SYSCFG_EXTICR1_EXTI3_PG   0x6000U
     
    #define SYSCFG_EXTICR1_EXTI3_PH   0x7000U
     
    #define SYSCFG_EXTICR1_EXTI3_PI   0x8000U
     
    #define SYSCFG_EXTICR2_EXTI4_Pos   (0U)
     
    #define SYSCFG_EXTICR2_EXTI4_Msk   (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos)
     
    #define SYSCFG_EXTICR2_EXTI4   SYSCFG_EXTICR2_EXTI4_Msk
     
    #define SYSCFG_EXTICR2_EXTI5_Pos   (4U)
     
    #define SYSCFG_EXTICR2_EXTI5_Msk   (0xFUL << SYSCFG_EXTICR2_EXTI5_Pos)
     
    #define SYSCFG_EXTICR2_EXTI5   SYSCFG_EXTICR2_EXTI5_Msk
     
    #define SYSCFG_EXTICR2_EXTI6_Pos   (8U)
     
    #define SYSCFG_EXTICR2_EXTI6_Msk   (0xFUL << SYSCFG_EXTICR2_EXTI6_Pos)
     
    #define SYSCFG_EXTICR2_EXTI6   SYSCFG_EXTICR2_EXTI6_Msk
     
    #define SYSCFG_EXTICR2_EXTI7_Pos   (12U)
     
    #define SYSCFG_EXTICR2_EXTI7_Msk   (0xFUL << SYSCFG_EXTICR2_EXTI7_Pos)
     
    #define SYSCFG_EXTICR2_EXTI7   SYSCFG_EXTICR2_EXTI7_Msk
     
    #define SYSCFG_EXTICR2_EXTI4_PA   0x0000U
     EXTI4 configuration
    -
     
    #define SYSCFG_EXTICR2_EXTI4_PB   0x0001U
     
    #define SYSCFG_EXTICR2_EXTI4_PC   0x0002U
     
    #define SYSCFG_EXTICR2_EXTI4_PD   0x0003U
     
    #define SYSCFG_EXTICR2_EXTI4_PE   0x0004U
     
    #define SYSCFG_EXTICR2_EXTI4_PF   0x0005U
     
    #define SYSCFG_EXTICR2_EXTI4_PG   0x0006U
     
    #define SYSCFG_EXTICR2_EXTI4_PH   0x0007U
     
    #define SYSCFG_EXTICR2_EXTI4_PI   0x0008U
     
    #define SYSCFG_EXTICR2_EXTI5_PA   0x0000U
     EXTI5 configuration
    -
     
    #define SYSCFG_EXTICR2_EXTI5_PB   0x0010U
     
    #define SYSCFG_EXTICR2_EXTI5_PC   0x0020U
     
    #define SYSCFG_EXTICR2_EXTI5_PD   0x0030U
     
    #define SYSCFG_EXTICR2_EXTI5_PE   0x0040U
     
    #define SYSCFG_EXTICR2_EXTI5_PF   0x0050U
     
    #define SYSCFG_EXTICR2_EXTI5_PG   0x0060U
     
    #define SYSCFG_EXTICR2_EXTI5_PH   0x0070U
     
    #define SYSCFG_EXTICR2_EXTI5_PI   0x0080U
     
    #define SYSCFG_EXTICR2_EXTI6_PA   0x0000U
     EXTI6 configuration
    -
     
    #define SYSCFG_EXTICR2_EXTI6_PB   0x0100U
     
    #define SYSCFG_EXTICR2_EXTI6_PC   0x0200U
     
    #define SYSCFG_EXTICR2_EXTI6_PD   0x0300U
     
    #define SYSCFG_EXTICR2_EXTI6_PE   0x0400U
     
    #define SYSCFG_EXTICR2_EXTI6_PF   0x0500U
     
    #define SYSCFG_EXTICR2_EXTI6_PG   0x0600U
     
    #define SYSCFG_EXTICR2_EXTI6_PH   0x0700U
     
    #define SYSCFG_EXTICR2_EXTI6_PI   0x0800U
     
    #define SYSCFG_EXTICR2_EXTI7_PA   0x0000U
     EXTI7 configuration
    -
     
    #define SYSCFG_EXTICR2_EXTI7_PB   0x1000U
     
    #define SYSCFG_EXTICR2_EXTI7_PC   0x2000U
     
    #define SYSCFG_EXTICR2_EXTI7_PD   0x3000U
     
    #define SYSCFG_EXTICR2_EXTI7_PE   0x4000U
     
    #define SYSCFG_EXTICR2_EXTI7_PF   0x5000U
     
    #define SYSCFG_EXTICR2_EXTI7_PG   0x6000U
     
    #define SYSCFG_EXTICR2_EXTI7_PH   0x7000U
     
    #define SYSCFG_EXTICR2_EXTI7_PI   0x8000U
     
    #define SYSCFG_EXTICR3_EXTI8_Pos   (0U)
     
    #define SYSCFG_EXTICR3_EXTI8_Msk   (0xFUL << SYSCFG_EXTICR3_EXTI8_Pos)
     
    #define SYSCFG_EXTICR3_EXTI8   SYSCFG_EXTICR3_EXTI8_Msk
     
    #define SYSCFG_EXTICR3_EXTI9_Pos   (4U)
     
    #define SYSCFG_EXTICR3_EXTI9_Msk   (0xFUL << SYSCFG_EXTICR3_EXTI9_Pos)
     
    #define SYSCFG_EXTICR3_EXTI9   SYSCFG_EXTICR3_EXTI9_Msk
     
    #define SYSCFG_EXTICR3_EXTI10_Pos   (8U)
     
    #define SYSCFG_EXTICR3_EXTI10_Msk   (0xFUL << SYSCFG_EXTICR3_EXTI10_Pos)
     
    #define SYSCFG_EXTICR3_EXTI10   SYSCFG_EXTICR3_EXTI10_Msk
     
    #define SYSCFG_EXTICR3_EXTI11_Pos   (12U)
     
    #define SYSCFG_EXTICR3_EXTI11_Msk   (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos)
     
    #define SYSCFG_EXTICR3_EXTI11   SYSCFG_EXTICR3_EXTI11_Msk
     
    #define SYSCFG_EXTICR3_EXTI8_PA   0x0000U
     EXTI8 configuration
    -
     
    #define SYSCFG_EXTICR3_EXTI8_PB   0x0001U
     
    #define SYSCFG_EXTICR3_EXTI8_PC   0x0002U
     
    #define SYSCFG_EXTICR3_EXTI8_PD   0x0003U
     
    #define SYSCFG_EXTICR3_EXTI8_PE   0x0004U
     
    #define SYSCFG_EXTICR3_EXTI8_PF   0x0005U
     
    #define SYSCFG_EXTICR3_EXTI8_PG   0x0006U
     
    #define SYSCFG_EXTICR3_EXTI8_PH   0x0007U
     
    #define SYSCFG_EXTICR3_EXTI8_PI   0x0008U
     
    #define SYSCFG_EXTICR3_EXTI9_PA   0x0000U
     EXTI9 configuration
    -
     
    #define SYSCFG_EXTICR3_EXTI9_PB   0x0010U
     
    #define SYSCFG_EXTICR3_EXTI9_PC   0x0020U
     
    #define SYSCFG_EXTICR3_EXTI9_PD   0x0030U
     
    #define SYSCFG_EXTICR3_EXTI9_PE   0x0040U
     
    #define SYSCFG_EXTICR3_EXTI9_PF   0x0050U
     
    #define SYSCFG_EXTICR3_EXTI9_PG   0x0060U
     
    #define SYSCFG_EXTICR3_EXTI9_PH   0x0070U
     
    #define SYSCFG_EXTICR3_EXTI9_PI   0x0080U
     
    #define SYSCFG_EXTICR3_EXTI10_PA   0x0000U
     EXTI10 configuration
    -
     
    #define SYSCFG_EXTICR3_EXTI10_PB   0x0100U
     
    #define SYSCFG_EXTICR3_EXTI10_PC   0x0200U
     
    #define SYSCFG_EXTICR3_EXTI10_PD   0x0300U
     
    #define SYSCFG_EXTICR3_EXTI10_PE   0x0400U
     
    #define SYSCFG_EXTICR3_EXTI10_PF   0x0500U
     
    #define SYSCFG_EXTICR3_EXTI10_PG   0x0600U
     
    #define SYSCFG_EXTICR3_EXTI10_PH   0x0700U
     
    #define SYSCFG_EXTICR3_EXTI10_PI   0x0800U
     
    #define SYSCFG_EXTICR3_EXTI11_PA   0x0000U
     EXTI11 configuration
    -
     
    #define SYSCFG_EXTICR3_EXTI11_PB   0x1000U
     
    #define SYSCFG_EXTICR3_EXTI11_PC   0x2000U
     
    #define SYSCFG_EXTICR3_EXTI11_PD   0x3000U
     
    #define SYSCFG_EXTICR3_EXTI11_PE   0x4000U
     
    #define SYSCFG_EXTICR3_EXTI11_PF   0x5000U
     
    #define SYSCFG_EXTICR3_EXTI11_PG   0x6000U
     
    #define SYSCFG_EXTICR3_EXTI11_PH   0x7000U
     
    #define SYSCFG_EXTICR3_EXTI11_PI   0x8000U
     
    #define SYSCFG_EXTICR4_EXTI12_Pos   (0U)
     
    #define SYSCFG_EXTICR4_EXTI12_Msk   (0xFUL << SYSCFG_EXTICR4_EXTI12_Pos)
     
    #define SYSCFG_EXTICR4_EXTI12   SYSCFG_EXTICR4_EXTI12_Msk
     
    #define SYSCFG_EXTICR4_EXTI13_Pos   (4U)
     
    #define SYSCFG_EXTICR4_EXTI13_Msk   (0xFUL << SYSCFG_EXTICR4_EXTI13_Pos)
     
    #define SYSCFG_EXTICR4_EXTI13   SYSCFG_EXTICR4_EXTI13_Msk
     
    #define SYSCFG_EXTICR4_EXTI14_Pos   (8U)
     
    #define SYSCFG_EXTICR4_EXTI14_Msk   (0xFUL << SYSCFG_EXTICR4_EXTI14_Pos)
     
    #define SYSCFG_EXTICR4_EXTI14   SYSCFG_EXTICR4_EXTI14_Msk
     
    #define SYSCFG_EXTICR4_EXTI15_Pos   (12U)
     
    #define SYSCFG_EXTICR4_EXTI15_Msk   (0xFUL << SYSCFG_EXTICR4_EXTI15_Pos)
     
    #define SYSCFG_EXTICR4_EXTI15   SYSCFG_EXTICR4_EXTI15_Msk
     
    #define SYSCFG_EXTICR4_EXTI12_PA   0x0000U
     EXTI12 configuration
    -
     
    #define SYSCFG_EXTICR4_EXTI12_PB   0x0001U
     
    #define SYSCFG_EXTICR4_EXTI12_PC   0x0002U
     
    #define SYSCFG_EXTICR4_EXTI12_PD   0x0003U
     
    #define SYSCFG_EXTICR4_EXTI12_PE   0x0004U
     
    #define SYSCFG_EXTICR4_EXTI12_PF   0x0005U
     
    #define SYSCFG_EXTICR4_EXTI12_PG   0x0006U
     
    #define SYSCFG_EXTICR4_EXTI12_PH   0x0007U
     
    #define SYSCFG_EXTICR4_EXTI13_PA   0x0000U
     EXTI13 configuration
    -
     
    #define SYSCFG_EXTICR4_EXTI13_PB   0x0010U
     
    #define SYSCFG_EXTICR4_EXTI13_PC   0x0020U
     
    #define SYSCFG_EXTICR4_EXTI13_PD   0x0030U
     
    #define SYSCFG_EXTICR4_EXTI13_PE   0x0040U
     
    #define SYSCFG_EXTICR4_EXTI13_PF   0x0050U
     
    #define SYSCFG_EXTICR4_EXTI13_PG   0x0060U
     
    #define SYSCFG_EXTICR4_EXTI13_PH   0x0070U
     
    #define SYSCFG_EXTICR4_EXTI14_PA   0x0000U
     EXTI14 configuration
    -
     
    #define SYSCFG_EXTICR4_EXTI14_PB   0x0100U
     
    #define SYSCFG_EXTICR4_EXTI14_PC   0x0200U
     
    #define SYSCFG_EXTICR4_EXTI14_PD   0x0300U
     
    #define SYSCFG_EXTICR4_EXTI14_PE   0x0400U
     
    #define SYSCFG_EXTICR4_EXTI14_PF   0x0500U
     
    #define SYSCFG_EXTICR4_EXTI14_PG   0x0600U
     
    #define SYSCFG_EXTICR4_EXTI14_PH   0x0700U
     
    #define SYSCFG_EXTICR4_EXTI15_PA   0x0000U
     EXTI15 configuration
    -
     
    #define SYSCFG_EXTICR4_EXTI15_PB   0x1000U
     
    #define SYSCFG_EXTICR4_EXTI15_PC   0x2000U
     
    #define SYSCFG_EXTICR4_EXTI15_PD   0x3000U
     
    #define SYSCFG_EXTICR4_EXTI15_PE   0x4000U
     
    #define SYSCFG_EXTICR4_EXTI15_PF   0x5000U
     
    #define SYSCFG_EXTICR4_EXTI15_PG   0x6000U
     
    #define SYSCFG_EXTICR4_EXTI15_PH   0x7000U
     
    #define SYSCFG_CMPCR_CMP_PD_Pos   (0U)
     
    #define SYSCFG_CMPCR_CMP_PD_Msk   (0x1UL << SYSCFG_CMPCR_CMP_PD_Pos)
     
    #define SYSCFG_CMPCR_CMP_PD   SYSCFG_CMPCR_CMP_PD_Msk
     
    #define SYSCFG_CMPCR_READY_Pos   (8U)
     
    #define SYSCFG_CMPCR_READY_Msk   (0x1UL << SYSCFG_CMPCR_READY_Pos)
     
    #define SYSCFG_CMPCR_READY   SYSCFG_CMPCR_READY_Msk
     
    #define TIM_CR1_CEN_Pos   (0U)
     
    #define TIM_CR1_CEN_Msk   (0x1UL << TIM_CR1_CEN_Pos)
     
    #define TIM_CR1_CEN   TIM_CR1_CEN_Msk
     
    #define TIM_CR1_UDIS_Pos   (1U)
     
    #define TIM_CR1_UDIS_Msk   (0x1UL << TIM_CR1_UDIS_Pos)
     
    #define TIM_CR1_UDIS   TIM_CR1_UDIS_Msk
     
    #define TIM_CR1_URS_Pos   (2U)
     
    #define TIM_CR1_URS_Msk   (0x1UL << TIM_CR1_URS_Pos)
     
    #define TIM_CR1_URS   TIM_CR1_URS_Msk
     
    #define TIM_CR1_OPM_Pos   (3U)
     
    #define TIM_CR1_OPM_Msk   (0x1UL << TIM_CR1_OPM_Pos)
     
    #define TIM_CR1_OPM   TIM_CR1_OPM_Msk
     
    #define TIM_CR1_DIR_Pos   (4U)
     
    #define TIM_CR1_DIR_Msk   (0x1UL << TIM_CR1_DIR_Pos)
     
    #define TIM_CR1_DIR   TIM_CR1_DIR_Msk
     
    #define TIM_CR1_CMS_Pos   (5U)
     
    #define TIM_CR1_CMS_Msk   (0x3UL << TIM_CR1_CMS_Pos)
     
    #define TIM_CR1_CMS   TIM_CR1_CMS_Msk
     
    #define TIM_CR1_CMS_0   (0x1UL << TIM_CR1_CMS_Pos)
     
    #define TIM_CR1_CMS_1   (0x2UL << TIM_CR1_CMS_Pos)
     
    #define TIM_CR1_ARPE_Pos   (7U)
     
    #define TIM_CR1_ARPE_Msk   (0x1UL << TIM_CR1_ARPE_Pos)
     
    #define TIM_CR1_ARPE   TIM_CR1_ARPE_Msk
     
    #define TIM_CR1_CKD_Pos   (8U)
     
    #define TIM_CR1_CKD_Msk   (0x3UL << TIM_CR1_CKD_Pos)
     
    #define TIM_CR1_CKD   TIM_CR1_CKD_Msk
     
    #define TIM_CR1_CKD_0   (0x1UL << TIM_CR1_CKD_Pos)
     
    #define TIM_CR1_CKD_1   (0x2UL << TIM_CR1_CKD_Pos)
     
    #define TIM_CR2_CCPC_Pos   (0U)
     
    #define TIM_CR2_CCPC_Msk   (0x1UL << TIM_CR2_CCPC_Pos)
     
    #define TIM_CR2_CCPC   TIM_CR2_CCPC_Msk
     
    #define TIM_CR2_CCUS_Pos   (2U)
     
    #define TIM_CR2_CCUS_Msk   (0x1UL << TIM_CR2_CCUS_Pos)
     
    #define TIM_CR2_CCUS   TIM_CR2_CCUS_Msk
     
    #define TIM_CR2_CCDS_Pos   (3U)
     
    #define TIM_CR2_CCDS_Msk   (0x1UL << TIM_CR2_CCDS_Pos)
     
    #define TIM_CR2_CCDS   TIM_CR2_CCDS_Msk
     
    #define TIM_CR2_MMS_Pos   (4U)
     
    #define TIM_CR2_MMS_Msk   (0x7UL << TIM_CR2_MMS_Pos)
     
    #define TIM_CR2_MMS   TIM_CR2_MMS_Msk
     
    #define TIM_CR2_MMS_0   (0x1UL << TIM_CR2_MMS_Pos)
     
    #define TIM_CR2_MMS_1   (0x2UL << TIM_CR2_MMS_Pos)
     
    #define TIM_CR2_MMS_2   (0x4UL << TIM_CR2_MMS_Pos)
     
    #define TIM_CR2_TI1S_Pos   (7U)
     
    #define TIM_CR2_TI1S_Msk   (0x1UL << TIM_CR2_TI1S_Pos)
     
    #define TIM_CR2_TI1S   TIM_CR2_TI1S_Msk
     
    #define TIM_CR2_OIS1_Pos   (8U)
     
    #define TIM_CR2_OIS1_Msk   (0x1UL << TIM_CR2_OIS1_Pos)
     
    #define TIM_CR2_OIS1   TIM_CR2_OIS1_Msk
     
    #define TIM_CR2_OIS1N_Pos   (9U)
     
    #define TIM_CR2_OIS1N_Msk   (0x1UL << TIM_CR2_OIS1N_Pos)
     
    #define TIM_CR2_OIS1N   TIM_CR2_OIS1N_Msk
     
    #define TIM_CR2_OIS2_Pos   (10U)
     
    #define TIM_CR2_OIS2_Msk   (0x1UL << TIM_CR2_OIS2_Pos)
     
    #define TIM_CR2_OIS2   TIM_CR2_OIS2_Msk
     
    #define TIM_CR2_OIS2N_Pos   (11U)
     
    #define TIM_CR2_OIS2N_Msk   (0x1UL << TIM_CR2_OIS2N_Pos)
     
    #define TIM_CR2_OIS2N   TIM_CR2_OIS2N_Msk
     
    #define TIM_CR2_OIS3_Pos   (12U)
     
    #define TIM_CR2_OIS3_Msk   (0x1UL << TIM_CR2_OIS3_Pos)
     
    #define TIM_CR2_OIS3   TIM_CR2_OIS3_Msk
     
    #define TIM_CR2_OIS3N_Pos   (13U)
     
    #define TIM_CR2_OIS3N_Msk   (0x1UL << TIM_CR2_OIS3N_Pos)
     
    #define TIM_CR2_OIS3N   TIM_CR2_OIS3N_Msk
     
    #define TIM_CR2_OIS4_Pos   (14U)
     
    #define TIM_CR2_OIS4_Msk   (0x1UL << TIM_CR2_OIS4_Pos)
     
    #define TIM_CR2_OIS4   TIM_CR2_OIS4_Msk
     
    #define TIM_SMCR_SMS_Pos   (0U)
     
    #define TIM_SMCR_SMS_Msk   (0x7UL << TIM_SMCR_SMS_Pos)
     
    #define TIM_SMCR_SMS   TIM_SMCR_SMS_Msk
     
    #define TIM_SMCR_SMS_0   (0x1UL << TIM_SMCR_SMS_Pos)
     
    #define TIM_SMCR_SMS_1   (0x2UL << TIM_SMCR_SMS_Pos)
     
    #define TIM_SMCR_SMS_2   (0x4UL << TIM_SMCR_SMS_Pos)
     
    #define TIM_SMCR_TS_Pos   (4U)
     
    #define TIM_SMCR_TS_Msk   (0x7UL << TIM_SMCR_TS_Pos)
     
    #define TIM_SMCR_TS   TIM_SMCR_TS_Msk
     
    #define TIM_SMCR_TS_0   (0x1UL << TIM_SMCR_TS_Pos)
     
    #define TIM_SMCR_TS_1   (0x2UL << TIM_SMCR_TS_Pos)
     
    #define TIM_SMCR_TS_2   (0x4UL << TIM_SMCR_TS_Pos)
     
    #define TIM_SMCR_MSM_Pos   (7U)
     
    #define TIM_SMCR_MSM_Msk   (0x1UL << TIM_SMCR_MSM_Pos)
     
    #define TIM_SMCR_MSM   TIM_SMCR_MSM_Msk
     
    #define TIM_SMCR_ETF_Pos   (8U)
     
    #define TIM_SMCR_ETF_Msk   (0xFUL << TIM_SMCR_ETF_Pos)
     
    #define TIM_SMCR_ETF   TIM_SMCR_ETF_Msk
     
    #define TIM_SMCR_ETF_0   (0x1UL << TIM_SMCR_ETF_Pos)
     
    #define TIM_SMCR_ETF_1   (0x2UL << TIM_SMCR_ETF_Pos)
     
    #define TIM_SMCR_ETF_2   (0x4UL << TIM_SMCR_ETF_Pos)
     
    #define TIM_SMCR_ETF_3   (0x8UL << TIM_SMCR_ETF_Pos)
     
    #define TIM_SMCR_ETPS_Pos   (12U)
     
    #define TIM_SMCR_ETPS_Msk   (0x3UL << TIM_SMCR_ETPS_Pos)
     
    #define TIM_SMCR_ETPS   TIM_SMCR_ETPS_Msk
     
    #define TIM_SMCR_ETPS_0   (0x1UL << TIM_SMCR_ETPS_Pos)
     
    #define TIM_SMCR_ETPS_1   (0x2UL << TIM_SMCR_ETPS_Pos)
     
    #define TIM_SMCR_ECE_Pos   (14U)
     
    #define TIM_SMCR_ECE_Msk   (0x1UL << TIM_SMCR_ECE_Pos)
     
    #define TIM_SMCR_ECE   TIM_SMCR_ECE_Msk
     
    #define TIM_SMCR_ETP_Pos   (15U)
     
    #define TIM_SMCR_ETP_Msk   (0x1UL << TIM_SMCR_ETP_Pos)
     
    #define TIM_SMCR_ETP   TIM_SMCR_ETP_Msk
     
    #define TIM_DIER_UIE_Pos   (0U)
     
    #define TIM_DIER_UIE_Msk   (0x1UL << TIM_DIER_UIE_Pos)
     
    #define TIM_DIER_UIE   TIM_DIER_UIE_Msk
     
    #define TIM_DIER_CC1IE_Pos   (1U)
     
    #define TIM_DIER_CC1IE_Msk   (0x1UL << TIM_DIER_CC1IE_Pos)
     
    #define TIM_DIER_CC1IE   TIM_DIER_CC1IE_Msk
     
    #define TIM_DIER_CC2IE_Pos   (2U)
     
    #define TIM_DIER_CC2IE_Msk   (0x1UL << TIM_DIER_CC2IE_Pos)
     
    #define TIM_DIER_CC2IE   TIM_DIER_CC2IE_Msk
     
    #define TIM_DIER_CC3IE_Pos   (3U)
     
    #define TIM_DIER_CC3IE_Msk   (0x1UL << TIM_DIER_CC3IE_Pos)
     
    #define TIM_DIER_CC3IE   TIM_DIER_CC3IE_Msk
     
    #define TIM_DIER_CC4IE_Pos   (4U)
     
    #define TIM_DIER_CC4IE_Msk   (0x1UL << TIM_DIER_CC4IE_Pos)
     
    #define TIM_DIER_CC4IE   TIM_DIER_CC4IE_Msk
     
    #define TIM_DIER_COMIE_Pos   (5U)
     
    #define TIM_DIER_COMIE_Msk   (0x1UL << TIM_DIER_COMIE_Pos)
     
    #define TIM_DIER_COMIE   TIM_DIER_COMIE_Msk
     
    #define TIM_DIER_TIE_Pos   (6U)
     
    #define TIM_DIER_TIE_Msk   (0x1UL << TIM_DIER_TIE_Pos)
     
    #define TIM_DIER_TIE   TIM_DIER_TIE_Msk
     
    #define TIM_DIER_BIE_Pos   (7U)
     
    #define TIM_DIER_BIE_Msk   (0x1UL << TIM_DIER_BIE_Pos)
     
    #define TIM_DIER_BIE   TIM_DIER_BIE_Msk
     
    #define TIM_DIER_UDE_Pos   (8U)
     
    #define TIM_DIER_UDE_Msk   (0x1UL << TIM_DIER_UDE_Pos)
     
    #define TIM_DIER_UDE   TIM_DIER_UDE_Msk
     
    #define TIM_DIER_CC1DE_Pos   (9U)
     
    #define TIM_DIER_CC1DE_Msk   (0x1UL << TIM_DIER_CC1DE_Pos)
     
    #define TIM_DIER_CC1DE   TIM_DIER_CC1DE_Msk
     
    #define TIM_DIER_CC2DE_Pos   (10U)
     
    #define TIM_DIER_CC2DE_Msk   (0x1UL << TIM_DIER_CC2DE_Pos)
     
    #define TIM_DIER_CC2DE   TIM_DIER_CC2DE_Msk
     
    #define TIM_DIER_CC3DE_Pos   (11U)
     
    #define TIM_DIER_CC3DE_Msk   (0x1UL << TIM_DIER_CC3DE_Pos)
     
    #define TIM_DIER_CC3DE   TIM_DIER_CC3DE_Msk
     
    #define TIM_DIER_CC4DE_Pos   (12U)
     
    #define TIM_DIER_CC4DE_Msk   (0x1UL << TIM_DIER_CC4DE_Pos)
     
    #define TIM_DIER_CC4DE   TIM_DIER_CC4DE_Msk
     
    #define TIM_DIER_COMDE_Pos   (13U)
     
    #define TIM_DIER_COMDE_Msk   (0x1UL << TIM_DIER_COMDE_Pos)
     
    #define TIM_DIER_COMDE   TIM_DIER_COMDE_Msk
     
    #define TIM_DIER_TDE_Pos   (14U)
     
    #define TIM_DIER_TDE_Msk   (0x1UL << TIM_DIER_TDE_Pos)
     
    #define TIM_DIER_TDE   TIM_DIER_TDE_Msk
     
    #define TIM_SR_UIF_Pos   (0U)
     
    #define TIM_SR_UIF_Msk   (0x1UL << TIM_SR_UIF_Pos)
     
    #define TIM_SR_UIF   TIM_SR_UIF_Msk
     
    #define TIM_SR_CC1IF_Pos   (1U)
     
    #define TIM_SR_CC1IF_Msk   (0x1UL << TIM_SR_CC1IF_Pos)
     
    #define TIM_SR_CC1IF   TIM_SR_CC1IF_Msk
     
    #define TIM_SR_CC2IF_Pos   (2U)
     
    #define TIM_SR_CC2IF_Msk   (0x1UL << TIM_SR_CC2IF_Pos)
     
    #define TIM_SR_CC2IF   TIM_SR_CC2IF_Msk
     
    #define TIM_SR_CC3IF_Pos   (3U)
     
    #define TIM_SR_CC3IF_Msk   (0x1UL << TIM_SR_CC3IF_Pos)
     
    #define TIM_SR_CC3IF   TIM_SR_CC3IF_Msk
     
    #define TIM_SR_CC4IF_Pos   (4U)
     
    #define TIM_SR_CC4IF_Msk   (0x1UL << TIM_SR_CC4IF_Pos)
     
    #define TIM_SR_CC4IF   TIM_SR_CC4IF_Msk
     
    #define TIM_SR_COMIF_Pos   (5U)
     
    #define TIM_SR_COMIF_Msk   (0x1UL << TIM_SR_COMIF_Pos)
     
    #define TIM_SR_COMIF   TIM_SR_COMIF_Msk
     
    #define TIM_SR_TIF_Pos   (6U)
     
    #define TIM_SR_TIF_Msk   (0x1UL << TIM_SR_TIF_Pos)
     
    #define TIM_SR_TIF   TIM_SR_TIF_Msk
     
    #define TIM_SR_BIF_Pos   (7U)
     
    #define TIM_SR_BIF_Msk   (0x1UL << TIM_SR_BIF_Pos)
     
    #define TIM_SR_BIF   TIM_SR_BIF_Msk
     
    #define TIM_SR_CC1OF_Pos   (9U)
     
    #define TIM_SR_CC1OF_Msk   (0x1UL << TIM_SR_CC1OF_Pos)
     
    #define TIM_SR_CC1OF   TIM_SR_CC1OF_Msk
     
    #define TIM_SR_CC2OF_Pos   (10U)
     
    #define TIM_SR_CC2OF_Msk   (0x1UL << TIM_SR_CC2OF_Pos)
     
    #define TIM_SR_CC2OF   TIM_SR_CC2OF_Msk
     
    #define TIM_SR_CC3OF_Pos   (11U)
     
    #define TIM_SR_CC3OF_Msk   (0x1UL << TIM_SR_CC3OF_Pos)
     
    #define TIM_SR_CC3OF   TIM_SR_CC3OF_Msk
     
    #define TIM_SR_CC4OF_Pos   (12U)
     
    #define TIM_SR_CC4OF_Msk   (0x1UL << TIM_SR_CC4OF_Pos)
     
    #define TIM_SR_CC4OF   TIM_SR_CC4OF_Msk
     
    #define TIM_EGR_UG_Pos   (0U)
     
    #define TIM_EGR_UG_Msk   (0x1UL << TIM_EGR_UG_Pos)
     
    #define TIM_EGR_UG   TIM_EGR_UG_Msk
     
    #define TIM_EGR_CC1G_Pos   (1U)
     
    #define TIM_EGR_CC1G_Msk   (0x1UL << TIM_EGR_CC1G_Pos)
     
    #define TIM_EGR_CC1G   TIM_EGR_CC1G_Msk
     
    #define TIM_EGR_CC2G_Pos   (2U)
     
    #define TIM_EGR_CC2G_Msk   (0x1UL << TIM_EGR_CC2G_Pos)
     
    #define TIM_EGR_CC2G   TIM_EGR_CC2G_Msk
     
    #define TIM_EGR_CC3G_Pos   (3U)
     
    #define TIM_EGR_CC3G_Msk   (0x1UL << TIM_EGR_CC3G_Pos)
     
    #define TIM_EGR_CC3G   TIM_EGR_CC3G_Msk
     
    #define TIM_EGR_CC4G_Pos   (4U)
     
    #define TIM_EGR_CC4G_Msk   (0x1UL << TIM_EGR_CC4G_Pos)
     
    #define TIM_EGR_CC4G   TIM_EGR_CC4G_Msk
     
    #define TIM_EGR_COMG_Pos   (5U)
     
    #define TIM_EGR_COMG_Msk   (0x1UL << TIM_EGR_COMG_Pos)
     
    #define TIM_EGR_COMG   TIM_EGR_COMG_Msk
     
    #define TIM_EGR_TG_Pos   (6U)
     
    #define TIM_EGR_TG_Msk   (0x1UL << TIM_EGR_TG_Pos)
     
    #define TIM_EGR_TG   TIM_EGR_TG_Msk
     
    #define TIM_EGR_BG_Pos   (7U)
     
    #define TIM_EGR_BG_Msk   (0x1UL << TIM_EGR_BG_Pos)
     
    #define TIM_EGR_BG   TIM_EGR_BG_Msk
     
    #define TIM_CCMR1_CC1S_Pos   (0U)
     
    #define TIM_CCMR1_CC1S_Msk   (0x3UL << TIM_CCMR1_CC1S_Pos)
     
    #define TIM_CCMR1_CC1S   TIM_CCMR1_CC1S_Msk
     
    #define TIM_CCMR1_CC1S_0   (0x1UL << TIM_CCMR1_CC1S_Pos)
     
    #define TIM_CCMR1_CC1S_1   (0x2UL << TIM_CCMR1_CC1S_Pos)
     
    #define TIM_CCMR1_OC1FE_Pos   (2U)
     
    #define TIM_CCMR1_OC1FE_Msk   (0x1UL << TIM_CCMR1_OC1FE_Pos)
     
    #define TIM_CCMR1_OC1FE   TIM_CCMR1_OC1FE_Msk
     
    #define TIM_CCMR1_OC1PE_Pos   (3U)
     
    #define TIM_CCMR1_OC1PE_Msk   (0x1UL << TIM_CCMR1_OC1PE_Pos)
     
    #define TIM_CCMR1_OC1PE   TIM_CCMR1_OC1PE_Msk
     
    #define TIM_CCMR1_OC1M_Pos   (4U)
     
    #define TIM_CCMR1_OC1M_Msk   (0x7UL << TIM_CCMR1_OC1M_Pos)
     
    #define TIM_CCMR1_OC1M   TIM_CCMR1_OC1M_Msk
     
    #define TIM_CCMR1_OC1M_0   (0x1UL << TIM_CCMR1_OC1M_Pos)
     
    #define TIM_CCMR1_OC1M_1   (0x2UL << TIM_CCMR1_OC1M_Pos)
     
    #define TIM_CCMR1_OC1M_2   (0x4UL << TIM_CCMR1_OC1M_Pos)
     
    #define TIM_CCMR1_OC1CE_Pos   (7U)
     
    #define TIM_CCMR1_OC1CE_Msk   (0x1UL << TIM_CCMR1_OC1CE_Pos)
     
    #define TIM_CCMR1_OC1CE   TIM_CCMR1_OC1CE_Msk
     
    #define TIM_CCMR1_CC2S_Pos   (8U)
     
    #define TIM_CCMR1_CC2S_Msk   (0x3UL << TIM_CCMR1_CC2S_Pos)
     
    #define TIM_CCMR1_CC2S   TIM_CCMR1_CC2S_Msk
     
    #define TIM_CCMR1_CC2S_0   (0x1UL << TIM_CCMR1_CC2S_Pos)
     
    #define TIM_CCMR1_CC2S_1   (0x2UL << TIM_CCMR1_CC2S_Pos)
     
    #define TIM_CCMR1_OC2FE_Pos   (10U)
     
    #define TIM_CCMR1_OC2FE_Msk   (0x1UL << TIM_CCMR1_OC2FE_Pos)
     
    #define TIM_CCMR1_OC2FE   TIM_CCMR1_OC2FE_Msk
     
    #define TIM_CCMR1_OC2PE_Pos   (11U)
     
    #define TIM_CCMR1_OC2PE_Msk   (0x1UL << TIM_CCMR1_OC2PE_Pos)
     
    #define TIM_CCMR1_OC2PE   TIM_CCMR1_OC2PE_Msk
     
    #define TIM_CCMR1_OC2M_Pos   (12U)
     
    #define TIM_CCMR1_OC2M_Msk   (0x7UL << TIM_CCMR1_OC2M_Pos)
     
    #define TIM_CCMR1_OC2M   TIM_CCMR1_OC2M_Msk
     
    #define TIM_CCMR1_OC2M_0   (0x1UL << TIM_CCMR1_OC2M_Pos)
     
    #define TIM_CCMR1_OC2M_1   (0x2UL << TIM_CCMR1_OC2M_Pos)
     
    #define TIM_CCMR1_OC2M_2   (0x4UL << TIM_CCMR1_OC2M_Pos)
     
    #define TIM_CCMR1_OC2CE_Pos   (15U)
     
    #define TIM_CCMR1_OC2CE_Msk   (0x1UL << TIM_CCMR1_OC2CE_Pos)
     
    #define TIM_CCMR1_OC2CE   TIM_CCMR1_OC2CE_Msk
     
    #define TIM_CCMR1_IC1PSC_Pos   (2U)
     
    #define TIM_CCMR1_IC1PSC_Msk   (0x3UL << TIM_CCMR1_IC1PSC_Pos)
     
    #define TIM_CCMR1_IC1PSC   TIM_CCMR1_IC1PSC_Msk
     
    #define TIM_CCMR1_IC1PSC_0   (0x1UL << TIM_CCMR1_IC1PSC_Pos)
     
    #define TIM_CCMR1_IC1PSC_1   (0x2UL << TIM_CCMR1_IC1PSC_Pos)
     
    #define TIM_CCMR1_IC1F_Pos   (4U)
     
    #define TIM_CCMR1_IC1F_Msk   (0xFUL << TIM_CCMR1_IC1F_Pos)
     
    #define TIM_CCMR1_IC1F   TIM_CCMR1_IC1F_Msk
     
    #define TIM_CCMR1_IC1F_0   (0x1UL << TIM_CCMR1_IC1F_Pos)
     
    #define TIM_CCMR1_IC1F_1   (0x2UL << TIM_CCMR1_IC1F_Pos)
     
    #define TIM_CCMR1_IC1F_2   (0x4UL << TIM_CCMR1_IC1F_Pos)
     
    #define TIM_CCMR1_IC1F_3   (0x8UL << TIM_CCMR1_IC1F_Pos)
     
    #define TIM_CCMR1_IC2PSC_Pos   (10U)
     
    #define TIM_CCMR1_IC2PSC_Msk   (0x3UL << TIM_CCMR1_IC2PSC_Pos)
     
    #define TIM_CCMR1_IC2PSC   TIM_CCMR1_IC2PSC_Msk
     
    #define TIM_CCMR1_IC2PSC_0   (0x1UL << TIM_CCMR1_IC2PSC_Pos)
     
    #define TIM_CCMR1_IC2PSC_1   (0x2UL << TIM_CCMR1_IC2PSC_Pos)
     
    #define TIM_CCMR1_IC2F_Pos   (12U)
     
    #define TIM_CCMR1_IC2F_Msk   (0xFUL << TIM_CCMR1_IC2F_Pos)
     
    #define TIM_CCMR1_IC2F   TIM_CCMR1_IC2F_Msk
     
    #define TIM_CCMR1_IC2F_0   (0x1UL << TIM_CCMR1_IC2F_Pos)
     
    #define TIM_CCMR1_IC2F_1   (0x2UL << TIM_CCMR1_IC2F_Pos)
     
    #define TIM_CCMR1_IC2F_2   (0x4UL << TIM_CCMR1_IC2F_Pos)
     
    #define TIM_CCMR1_IC2F_3   (0x8UL << TIM_CCMR1_IC2F_Pos)
     
    #define TIM_CCMR2_CC3S_Pos   (0U)
     
    #define TIM_CCMR2_CC3S_Msk   (0x3UL << TIM_CCMR2_CC3S_Pos)
     
    #define TIM_CCMR2_CC3S   TIM_CCMR2_CC3S_Msk
     
    #define TIM_CCMR2_CC3S_0   (0x1UL << TIM_CCMR2_CC3S_Pos)
     
    #define TIM_CCMR2_CC3S_1   (0x2UL << TIM_CCMR2_CC3S_Pos)
     
    #define TIM_CCMR2_OC3FE_Pos   (2U)
     
    #define TIM_CCMR2_OC3FE_Msk   (0x1UL << TIM_CCMR2_OC3FE_Pos)
     
    #define TIM_CCMR2_OC3FE   TIM_CCMR2_OC3FE_Msk
     
    #define TIM_CCMR2_OC3PE_Pos   (3U)
     
    #define TIM_CCMR2_OC3PE_Msk   (0x1UL << TIM_CCMR2_OC3PE_Pos)
     
    #define TIM_CCMR2_OC3PE   TIM_CCMR2_OC3PE_Msk
     
    #define TIM_CCMR2_OC3M_Pos   (4U)
     
    #define TIM_CCMR2_OC3M_Msk   (0x7UL << TIM_CCMR2_OC3M_Pos)
     
    #define TIM_CCMR2_OC3M   TIM_CCMR2_OC3M_Msk
     
    #define TIM_CCMR2_OC3M_0   (0x1UL << TIM_CCMR2_OC3M_Pos)
     
    #define TIM_CCMR2_OC3M_1   (0x2UL << TIM_CCMR2_OC3M_Pos)
     
    #define TIM_CCMR2_OC3M_2   (0x4UL << TIM_CCMR2_OC3M_Pos)
     
    #define TIM_CCMR2_OC3CE_Pos   (7U)
     
    #define TIM_CCMR2_OC3CE_Msk   (0x1UL << TIM_CCMR2_OC3CE_Pos)
     
    #define TIM_CCMR2_OC3CE   TIM_CCMR2_OC3CE_Msk
     
    #define TIM_CCMR2_CC4S_Pos   (8U)
     
    #define TIM_CCMR2_CC4S_Msk   (0x3UL << TIM_CCMR2_CC4S_Pos)
     
    #define TIM_CCMR2_CC4S   TIM_CCMR2_CC4S_Msk
     
    #define TIM_CCMR2_CC4S_0   (0x1UL << TIM_CCMR2_CC4S_Pos)
     
    #define TIM_CCMR2_CC4S_1   (0x2UL << TIM_CCMR2_CC4S_Pos)
     
    #define TIM_CCMR2_OC4FE_Pos   (10U)
     
    #define TIM_CCMR2_OC4FE_Msk   (0x1UL << TIM_CCMR2_OC4FE_Pos)
     
    #define TIM_CCMR2_OC4FE   TIM_CCMR2_OC4FE_Msk
     
    #define TIM_CCMR2_OC4PE_Pos   (11U)
     
    #define TIM_CCMR2_OC4PE_Msk   (0x1UL << TIM_CCMR2_OC4PE_Pos)
     
    #define TIM_CCMR2_OC4PE   TIM_CCMR2_OC4PE_Msk
     
    #define TIM_CCMR2_OC4M_Pos   (12U)
     
    #define TIM_CCMR2_OC4M_Msk   (0x7UL << TIM_CCMR2_OC4M_Pos)
     
    #define TIM_CCMR2_OC4M   TIM_CCMR2_OC4M_Msk
     
    #define TIM_CCMR2_OC4M_0   (0x1UL << TIM_CCMR2_OC4M_Pos)
     
    #define TIM_CCMR2_OC4M_1   (0x2UL << TIM_CCMR2_OC4M_Pos)
     
    #define TIM_CCMR2_OC4M_2   (0x4UL << TIM_CCMR2_OC4M_Pos)
     
    #define TIM_CCMR2_OC4CE_Pos   (15U)
     
    #define TIM_CCMR2_OC4CE_Msk   (0x1UL << TIM_CCMR2_OC4CE_Pos)
     
    #define TIM_CCMR2_OC4CE   TIM_CCMR2_OC4CE_Msk
     
    #define TIM_CCMR2_IC3PSC_Pos   (2U)
     
    #define TIM_CCMR2_IC3PSC_Msk   (0x3UL << TIM_CCMR2_IC3PSC_Pos)
     
    #define TIM_CCMR2_IC3PSC   TIM_CCMR2_IC3PSC_Msk
     
    #define TIM_CCMR2_IC3PSC_0   (0x1UL << TIM_CCMR2_IC3PSC_Pos)
     
    #define TIM_CCMR2_IC3PSC_1   (0x2UL << TIM_CCMR2_IC3PSC_Pos)
     
    #define TIM_CCMR2_IC3F_Pos   (4U)
     
    #define TIM_CCMR2_IC3F_Msk   (0xFUL << TIM_CCMR2_IC3F_Pos)
     
    #define TIM_CCMR2_IC3F   TIM_CCMR2_IC3F_Msk
     
    #define TIM_CCMR2_IC3F_0   (0x1UL << TIM_CCMR2_IC3F_Pos)
     
    #define TIM_CCMR2_IC3F_1   (0x2UL << TIM_CCMR2_IC3F_Pos)
     
    #define TIM_CCMR2_IC3F_2   (0x4UL << TIM_CCMR2_IC3F_Pos)
     
    #define TIM_CCMR2_IC3F_3   (0x8UL << TIM_CCMR2_IC3F_Pos)
     
    #define TIM_CCMR2_IC4PSC_Pos   (10U)
     
    #define TIM_CCMR2_IC4PSC_Msk   (0x3UL << TIM_CCMR2_IC4PSC_Pos)
     
    #define TIM_CCMR2_IC4PSC   TIM_CCMR2_IC4PSC_Msk
     
    #define TIM_CCMR2_IC4PSC_0   (0x1UL << TIM_CCMR2_IC4PSC_Pos)
     
    #define TIM_CCMR2_IC4PSC_1   (0x2UL << TIM_CCMR2_IC4PSC_Pos)
     
    #define TIM_CCMR2_IC4F_Pos   (12U)
     
    #define TIM_CCMR2_IC4F_Msk   (0xFUL << TIM_CCMR2_IC4F_Pos)
     
    #define TIM_CCMR2_IC4F   TIM_CCMR2_IC4F_Msk
     
    #define TIM_CCMR2_IC4F_0   (0x1UL << TIM_CCMR2_IC4F_Pos)
     
    #define TIM_CCMR2_IC4F_1   (0x2UL << TIM_CCMR2_IC4F_Pos)
     
    #define TIM_CCMR2_IC4F_2   (0x4UL << TIM_CCMR2_IC4F_Pos)
     
    #define TIM_CCMR2_IC4F_3   (0x8UL << TIM_CCMR2_IC4F_Pos)
     
    #define TIM_CCER_CC1E_Pos   (0U)
     
    #define TIM_CCER_CC1E_Msk   (0x1UL << TIM_CCER_CC1E_Pos)
     
    #define TIM_CCER_CC1E   TIM_CCER_CC1E_Msk
     
    #define TIM_CCER_CC1P_Pos   (1U)
     
    #define TIM_CCER_CC1P_Msk   (0x1UL << TIM_CCER_CC1P_Pos)
     
    #define TIM_CCER_CC1P   TIM_CCER_CC1P_Msk
     
    #define TIM_CCER_CC1NE_Pos   (2U)
     
    #define TIM_CCER_CC1NE_Msk   (0x1UL << TIM_CCER_CC1NE_Pos)
     
    #define TIM_CCER_CC1NE   TIM_CCER_CC1NE_Msk
     
    #define TIM_CCER_CC1NP_Pos   (3U)
     
    #define TIM_CCER_CC1NP_Msk   (0x1UL << TIM_CCER_CC1NP_Pos)
     
    #define TIM_CCER_CC1NP   TIM_CCER_CC1NP_Msk
     
    #define TIM_CCER_CC2E_Pos   (4U)
     
    #define TIM_CCER_CC2E_Msk   (0x1UL << TIM_CCER_CC2E_Pos)
     
    #define TIM_CCER_CC2E   TIM_CCER_CC2E_Msk
     
    #define TIM_CCER_CC2P_Pos   (5U)
     
    #define TIM_CCER_CC2P_Msk   (0x1UL << TIM_CCER_CC2P_Pos)
     
    #define TIM_CCER_CC2P   TIM_CCER_CC2P_Msk
     
    #define TIM_CCER_CC2NE_Pos   (6U)
     
    #define TIM_CCER_CC2NE_Msk   (0x1UL << TIM_CCER_CC2NE_Pos)
     
    #define TIM_CCER_CC2NE   TIM_CCER_CC2NE_Msk
     
    #define TIM_CCER_CC2NP_Pos   (7U)
     
    #define TIM_CCER_CC2NP_Msk   (0x1UL << TIM_CCER_CC2NP_Pos)
     
    #define TIM_CCER_CC2NP   TIM_CCER_CC2NP_Msk
     
    #define TIM_CCER_CC3E_Pos   (8U)
     
    #define TIM_CCER_CC3E_Msk   (0x1UL << TIM_CCER_CC3E_Pos)
     
    #define TIM_CCER_CC3E   TIM_CCER_CC3E_Msk
     
    #define TIM_CCER_CC3P_Pos   (9U)
     
    #define TIM_CCER_CC3P_Msk   (0x1UL << TIM_CCER_CC3P_Pos)
     
    #define TIM_CCER_CC3P   TIM_CCER_CC3P_Msk
     
    #define TIM_CCER_CC3NE_Pos   (10U)
     
    #define TIM_CCER_CC3NE_Msk   (0x1UL << TIM_CCER_CC3NE_Pos)
     
    #define TIM_CCER_CC3NE   TIM_CCER_CC3NE_Msk
     
    #define TIM_CCER_CC3NP_Pos   (11U)
     
    #define TIM_CCER_CC3NP_Msk   (0x1UL << TIM_CCER_CC3NP_Pos)
     
    #define TIM_CCER_CC3NP   TIM_CCER_CC3NP_Msk
     
    #define TIM_CCER_CC4E_Pos   (12U)
     
    #define TIM_CCER_CC4E_Msk   (0x1UL << TIM_CCER_CC4E_Pos)
     
    #define TIM_CCER_CC4E   TIM_CCER_CC4E_Msk
     
    #define TIM_CCER_CC4P_Pos   (13U)
     
    #define TIM_CCER_CC4P_Msk   (0x1UL << TIM_CCER_CC4P_Pos)
     
    #define TIM_CCER_CC4P   TIM_CCER_CC4P_Msk
     
    #define TIM_CCER_CC4NP_Pos   (15U)
     
    #define TIM_CCER_CC4NP_Msk   (0x1UL << TIM_CCER_CC4NP_Pos)
     
    #define TIM_CCER_CC4NP   TIM_CCER_CC4NP_Msk
     
    #define TIM_CNT_CNT_Pos   (0U)
     
    #define TIM_CNT_CNT_Msk   (0xFFFFFFFFUL << TIM_CNT_CNT_Pos)
     
    #define TIM_CNT_CNT   TIM_CNT_CNT_Msk
     
    #define TIM_PSC_PSC_Pos   (0U)
     
    #define TIM_PSC_PSC_Msk   (0xFFFFUL << TIM_PSC_PSC_Pos)
     
    #define TIM_PSC_PSC   TIM_PSC_PSC_Msk
     
    #define TIM_ARR_ARR_Pos   (0U)
     
    #define TIM_ARR_ARR_Msk   (0xFFFFFFFFUL << TIM_ARR_ARR_Pos)
     
    #define TIM_ARR_ARR   TIM_ARR_ARR_Msk
     
    #define TIM_RCR_REP_Pos   (0U)
     
    #define TIM_RCR_REP_Msk   (0xFFUL << TIM_RCR_REP_Pos)
     
    #define TIM_RCR_REP   TIM_RCR_REP_Msk
     
    #define TIM_CCR1_CCR1_Pos   (0U)
     
    #define TIM_CCR1_CCR1_Msk   (0xFFFFUL << TIM_CCR1_CCR1_Pos)
     
    #define TIM_CCR1_CCR1   TIM_CCR1_CCR1_Msk
     
    #define TIM_CCR2_CCR2_Pos   (0U)
     
    #define TIM_CCR2_CCR2_Msk   (0xFFFFUL << TIM_CCR2_CCR2_Pos)
     
    #define TIM_CCR2_CCR2   TIM_CCR2_CCR2_Msk
     
    #define TIM_CCR3_CCR3_Pos   (0U)
     
    #define TIM_CCR3_CCR3_Msk   (0xFFFFUL << TIM_CCR3_CCR3_Pos)
     
    #define TIM_CCR3_CCR3   TIM_CCR3_CCR3_Msk
     
    #define TIM_CCR4_CCR4_Pos   (0U)
     
    #define TIM_CCR4_CCR4_Msk   (0xFFFFUL << TIM_CCR4_CCR4_Pos)
     
    #define TIM_CCR4_CCR4   TIM_CCR4_CCR4_Msk
     
    #define TIM_BDTR_DTG_Pos   (0U)
     
    #define TIM_BDTR_DTG_Msk   (0xFFUL << TIM_BDTR_DTG_Pos)
     
    #define TIM_BDTR_DTG   TIM_BDTR_DTG_Msk
     
    #define TIM_BDTR_DTG_0   (0x01UL << TIM_BDTR_DTG_Pos)
     
    #define TIM_BDTR_DTG_1   (0x02UL << TIM_BDTR_DTG_Pos)
     
    #define TIM_BDTR_DTG_2   (0x04UL << TIM_BDTR_DTG_Pos)
     
    #define TIM_BDTR_DTG_3   (0x08UL << TIM_BDTR_DTG_Pos)
     
    #define TIM_BDTR_DTG_4   (0x10UL << TIM_BDTR_DTG_Pos)
     
    #define TIM_BDTR_DTG_5   (0x20UL << TIM_BDTR_DTG_Pos)
     
    #define TIM_BDTR_DTG_6   (0x40UL << TIM_BDTR_DTG_Pos)
     
    #define TIM_BDTR_DTG_7   (0x80UL << TIM_BDTR_DTG_Pos)
     
    #define TIM_BDTR_LOCK_Pos   (8U)
     
    #define TIM_BDTR_LOCK_Msk   (0x3UL << TIM_BDTR_LOCK_Pos)
     
    #define TIM_BDTR_LOCK   TIM_BDTR_LOCK_Msk
     
    #define TIM_BDTR_LOCK_0   (0x1UL << TIM_BDTR_LOCK_Pos)
     
    #define TIM_BDTR_LOCK_1   (0x2UL << TIM_BDTR_LOCK_Pos)
     
    #define TIM_BDTR_OSSI_Pos   (10U)
     
    #define TIM_BDTR_OSSI_Msk   (0x1UL << TIM_BDTR_OSSI_Pos)
     
    #define TIM_BDTR_OSSI   TIM_BDTR_OSSI_Msk
     
    #define TIM_BDTR_OSSR_Pos   (11U)
     
    #define TIM_BDTR_OSSR_Msk   (0x1UL << TIM_BDTR_OSSR_Pos)
     
    #define TIM_BDTR_OSSR   TIM_BDTR_OSSR_Msk
     
    #define TIM_BDTR_BKE_Pos   (12U)
     
    #define TIM_BDTR_BKE_Msk   (0x1UL << TIM_BDTR_BKE_Pos)
     
    #define TIM_BDTR_BKE   TIM_BDTR_BKE_Msk
     
    #define TIM_BDTR_BKP_Pos   (13U)
     
    #define TIM_BDTR_BKP_Msk   (0x1UL << TIM_BDTR_BKP_Pos)
     
    #define TIM_BDTR_BKP   TIM_BDTR_BKP_Msk
     
    #define TIM_BDTR_AOE_Pos   (14U)
     
    #define TIM_BDTR_AOE_Msk   (0x1UL << TIM_BDTR_AOE_Pos)
     
    #define TIM_BDTR_AOE   TIM_BDTR_AOE_Msk
     
    #define TIM_BDTR_MOE_Pos   (15U)
     
    #define TIM_BDTR_MOE_Msk   (0x1UL << TIM_BDTR_MOE_Pos)
     
    #define TIM_BDTR_MOE   TIM_BDTR_MOE_Msk
     
    #define TIM_DCR_DBA_Pos   (0U)
     
    #define TIM_DCR_DBA_Msk   (0x1FUL << TIM_DCR_DBA_Pos)
     
    #define TIM_DCR_DBA   TIM_DCR_DBA_Msk
     
    #define TIM_DCR_DBA_0   (0x01UL << TIM_DCR_DBA_Pos)
     
    #define TIM_DCR_DBA_1   (0x02UL << TIM_DCR_DBA_Pos)
     
    #define TIM_DCR_DBA_2   (0x04UL << TIM_DCR_DBA_Pos)
     
    #define TIM_DCR_DBA_3   (0x08UL << TIM_DCR_DBA_Pos)
     
    #define TIM_DCR_DBA_4   (0x10UL << TIM_DCR_DBA_Pos)
     
    #define TIM_DCR_DBL_Pos   (8U)
     
    #define TIM_DCR_DBL_Msk   (0x1FUL << TIM_DCR_DBL_Pos)
     
    #define TIM_DCR_DBL   TIM_DCR_DBL_Msk
     
    #define TIM_DCR_DBL_0   (0x01UL << TIM_DCR_DBL_Pos)
     
    #define TIM_DCR_DBL_1   (0x02UL << TIM_DCR_DBL_Pos)
     
    #define TIM_DCR_DBL_2   (0x04UL << TIM_DCR_DBL_Pos)
     
    #define TIM_DCR_DBL_3   (0x08UL << TIM_DCR_DBL_Pos)
     
    #define TIM_DCR_DBL_4   (0x10UL << TIM_DCR_DBL_Pos)
     
    #define TIM_DMAR_DMAB_Pos   (0U)
     
    #define TIM_DMAR_DMAB_Msk   (0xFFFFUL << TIM_DMAR_DMAB_Pos)
     
    #define TIM_DMAR_DMAB   TIM_DMAR_DMAB_Msk
     
    #define TIM_OR_TI1_RMP_Pos   (0U)
     
    #define TIM_OR_TI1_RMP_Msk   (0x3UL << TIM_OR_TI1_RMP_Pos)
     
    #define TIM_OR_TI1_RMP   TIM_OR_TI1_RMP_Msk
     
    #define TIM_OR_TI1_RMP_0   (0x1UL << TIM_OR_TI1_RMP_Pos)
     
    #define TIM_OR_TI1_RMP_1   (0x2UL << TIM_OR_TI1_RMP_Pos)
     
    #define TIM_OR_TI4_RMP_Pos   (6U)
     
    #define TIM_OR_TI4_RMP_Msk   (0x3UL << TIM_OR_TI4_RMP_Pos)
     
    #define TIM_OR_TI4_RMP   TIM_OR_TI4_RMP_Msk
     
    #define TIM_OR_TI4_RMP_0   (0x1UL << TIM_OR_TI4_RMP_Pos)
     
    #define TIM_OR_TI4_RMP_1   (0x2UL << TIM_OR_TI4_RMP_Pos)
     
    #define TIM_OR_ITR1_RMP_Pos   (10U)
     
    #define TIM_OR_ITR1_RMP_Msk   (0x3UL << TIM_OR_ITR1_RMP_Pos)
     
    #define TIM_OR_ITR1_RMP   TIM_OR_ITR1_RMP_Msk
     
    #define TIM_OR_ITR1_RMP_0   (0x1UL << TIM_OR_ITR1_RMP_Pos)
     
    #define TIM_OR_ITR1_RMP_1   (0x2UL << TIM_OR_ITR1_RMP_Pos)
     
    #define USART_SR_PE_Pos   (0U)
     
    #define USART_SR_PE_Msk   (0x1UL << USART_SR_PE_Pos)
     
    #define USART_SR_PE   USART_SR_PE_Msk
     
    #define USART_SR_FE_Pos   (1U)
     
    #define USART_SR_FE_Msk   (0x1UL << USART_SR_FE_Pos)
     
    #define USART_SR_FE   USART_SR_FE_Msk
     
    #define USART_SR_NE_Pos   (2U)
     
    #define USART_SR_NE_Msk   (0x1UL << USART_SR_NE_Pos)
     
    #define USART_SR_NE   USART_SR_NE_Msk
     
    #define USART_SR_ORE_Pos   (3U)
     
    #define USART_SR_ORE_Msk   (0x1UL << USART_SR_ORE_Pos)
     
    #define USART_SR_ORE   USART_SR_ORE_Msk
     
    #define USART_SR_IDLE_Pos   (4U)
     
    #define USART_SR_IDLE_Msk   (0x1UL << USART_SR_IDLE_Pos)
     
    #define USART_SR_IDLE   USART_SR_IDLE_Msk
     
    #define USART_SR_RXNE_Pos   (5U)
     
    #define USART_SR_RXNE_Msk   (0x1UL << USART_SR_RXNE_Pos)
     
    #define USART_SR_RXNE   USART_SR_RXNE_Msk
     
    #define USART_SR_TC_Pos   (6U)
     
    #define USART_SR_TC_Msk   (0x1UL << USART_SR_TC_Pos)
     
    #define USART_SR_TC   USART_SR_TC_Msk
     
    #define USART_SR_TXE_Pos   (7U)
     
    #define USART_SR_TXE_Msk   (0x1UL << USART_SR_TXE_Pos)
     
    #define USART_SR_TXE   USART_SR_TXE_Msk
     
    #define USART_SR_LBD_Pos   (8U)
     
    #define USART_SR_LBD_Msk   (0x1UL << USART_SR_LBD_Pos)
     
    #define USART_SR_LBD   USART_SR_LBD_Msk
     
    #define USART_SR_CTS_Pos   (9U)
     
    #define USART_SR_CTS_Msk   (0x1UL << USART_SR_CTS_Pos)
     
    #define USART_SR_CTS   USART_SR_CTS_Msk
     
    #define USART_DR_DR_Pos   (0U)
     
    #define USART_DR_DR_Msk   (0x1FFUL << USART_DR_DR_Pos)
     
    #define USART_DR_DR   USART_DR_DR_Msk
     
    #define USART_BRR_DIV_Fraction_Pos   (0U)
     
    #define USART_BRR_DIV_Fraction_Msk   (0xFUL << USART_BRR_DIV_Fraction_Pos)
     
    #define USART_BRR_DIV_Fraction   USART_BRR_DIV_Fraction_Msk
     
    #define USART_BRR_DIV_Mantissa_Pos   (4U)
     
    #define USART_BRR_DIV_Mantissa_Msk   (0xFFFUL << USART_BRR_DIV_Mantissa_Pos)
     
    #define USART_BRR_DIV_Mantissa   USART_BRR_DIV_Mantissa_Msk
     
    #define USART_CR1_SBK_Pos   (0U)
     
    #define USART_CR1_SBK_Msk   (0x1UL << USART_CR1_SBK_Pos)
     
    #define USART_CR1_SBK   USART_CR1_SBK_Msk
     
    #define USART_CR1_RWU_Pos   (1U)
     
    #define USART_CR1_RWU_Msk   (0x1UL << USART_CR1_RWU_Pos)
     
    #define USART_CR1_RWU   USART_CR1_RWU_Msk
     
    #define USART_CR1_RE_Pos   (2U)
     
    #define USART_CR1_RE_Msk   (0x1UL << USART_CR1_RE_Pos)
     
    #define USART_CR1_RE   USART_CR1_RE_Msk
     
    #define USART_CR1_TE_Pos   (3U)
     
    #define USART_CR1_TE_Msk   (0x1UL << USART_CR1_TE_Pos)
     
    #define USART_CR1_TE   USART_CR1_TE_Msk
     
    #define USART_CR1_IDLEIE_Pos   (4U)
     
    #define USART_CR1_IDLEIE_Msk   (0x1UL << USART_CR1_IDLEIE_Pos)
     
    #define USART_CR1_IDLEIE   USART_CR1_IDLEIE_Msk
     
    #define USART_CR1_RXNEIE_Pos   (5U)
     
    #define USART_CR1_RXNEIE_Msk   (0x1UL << USART_CR1_RXNEIE_Pos)
     
    #define USART_CR1_RXNEIE   USART_CR1_RXNEIE_Msk
     
    #define USART_CR1_TCIE_Pos   (6U)
     
    #define USART_CR1_TCIE_Msk   (0x1UL << USART_CR1_TCIE_Pos)
     
    #define USART_CR1_TCIE   USART_CR1_TCIE_Msk
     
    #define USART_CR1_TXEIE_Pos   (7U)
     
    #define USART_CR1_TXEIE_Msk   (0x1UL << USART_CR1_TXEIE_Pos)
     
    #define USART_CR1_TXEIE   USART_CR1_TXEIE_Msk
     
    #define USART_CR1_PEIE_Pos   (8U)
     
    #define USART_CR1_PEIE_Msk   (0x1UL << USART_CR1_PEIE_Pos)
     
    #define USART_CR1_PEIE   USART_CR1_PEIE_Msk
     
    #define USART_CR1_PS_Pos   (9U)
     
    #define USART_CR1_PS_Msk   (0x1UL << USART_CR1_PS_Pos)
     
    #define USART_CR1_PS   USART_CR1_PS_Msk
     
    #define USART_CR1_PCE_Pos   (10U)
     
    #define USART_CR1_PCE_Msk   (0x1UL << USART_CR1_PCE_Pos)
     
    #define USART_CR1_PCE   USART_CR1_PCE_Msk
     
    #define USART_CR1_WAKE_Pos   (11U)
     
    #define USART_CR1_WAKE_Msk   (0x1UL << USART_CR1_WAKE_Pos)
     
    #define USART_CR1_WAKE   USART_CR1_WAKE_Msk
     
    #define USART_CR1_M_Pos   (12U)
     
    #define USART_CR1_M_Msk   (0x1UL << USART_CR1_M_Pos)
     
    #define USART_CR1_M   USART_CR1_M_Msk
     
    #define USART_CR1_UE_Pos   (13U)
     
    #define USART_CR1_UE_Msk   (0x1UL << USART_CR1_UE_Pos)
     
    #define USART_CR1_UE   USART_CR1_UE_Msk
     
    #define USART_CR1_OVER8_Pos   (15U)
     
    #define USART_CR1_OVER8_Msk   (0x1UL << USART_CR1_OVER8_Pos)
     
    #define USART_CR1_OVER8   USART_CR1_OVER8_Msk
     
    #define USART_CR2_ADD_Pos   (0U)
     
    #define USART_CR2_ADD_Msk   (0xFUL << USART_CR2_ADD_Pos)
     
    #define USART_CR2_ADD   USART_CR2_ADD_Msk
     
    #define USART_CR2_LBDL_Pos   (5U)
     
    #define USART_CR2_LBDL_Msk   (0x1UL << USART_CR2_LBDL_Pos)
     
    #define USART_CR2_LBDL   USART_CR2_LBDL_Msk
     
    #define USART_CR2_LBDIE_Pos   (6U)
     
    #define USART_CR2_LBDIE_Msk   (0x1UL << USART_CR2_LBDIE_Pos)
     
    #define USART_CR2_LBDIE   USART_CR2_LBDIE_Msk
     
    #define USART_CR2_LBCL_Pos   (8U)
     
    #define USART_CR2_LBCL_Msk   (0x1UL << USART_CR2_LBCL_Pos)
     
    #define USART_CR2_LBCL   USART_CR2_LBCL_Msk
     
    #define USART_CR2_CPHA_Pos   (9U)
     
    #define USART_CR2_CPHA_Msk   (0x1UL << USART_CR2_CPHA_Pos)
     
    #define USART_CR2_CPHA   USART_CR2_CPHA_Msk
     
    #define USART_CR2_CPOL_Pos   (10U)
     
    #define USART_CR2_CPOL_Msk   (0x1UL << USART_CR2_CPOL_Pos)
     
    #define USART_CR2_CPOL   USART_CR2_CPOL_Msk
     
    #define USART_CR2_CLKEN_Pos   (11U)
     
    #define USART_CR2_CLKEN_Msk   (0x1UL << USART_CR2_CLKEN_Pos)
     
    #define USART_CR2_CLKEN   USART_CR2_CLKEN_Msk
     
    #define USART_CR2_STOP_Pos   (12U)
     
    #define USART_CR2_STOP_Msk   (0x3UL << USART_CR2_STOP_Pos)
     
    #define USART_CR2_STOP   USART_CR2_STOP_Msk
     
    #define USART_CR2_STOP_0   (0x1UL << USART_CR2_STOP_Pos)
     
    #define USART_CR2_STOP_1   (0x2UL << USART_CR2_STOP_Pos)
     
    #define USART_CR2_LINEN_Pos   (14U)
     
    #define USART_CR2_LINEN_Msk   (0x1UL << USART_CR2_LINEN_Pos)
     
    #define USART_CR2_LINEN   USART_CR2_LINEN_Msk
     
    #define USART_CR3_EIE_Pos   (0U)
     
    #define USART_CR3_EIE_Msk   (0x1UL << USART_CR3_EIE_Pos)
     
    #define USART_CR3_EIE   USART_CR3_EIE_Msk
     
    #define USART_CR3_IREN_Pos   (1U)
     
    #define USART_CR3_IREN_Msk   (0x1UL << USART_CR3_IREN_Pos)
     
    #define USART_CR3_IREN   USART_CR3_IREN_Msk
     
    #define USART_CR3_IRLP_Pos   (2U)
     
    #define USART_CR3_IRLP_Msk   (0x1UL << USART_CR3_IRLP_Pos)
     
    #define USART_CR3_IRLP   USART_CR3_IRLP_Msk
     
    #define USART_CR3_HDSEL_Pos   (3U)
     
    #define USART_CR3_HDSEL_Msk   (0x1UL << USART_CR3_HDSEL_Pos)
     
    #define USART_CR3_HDSEL   USART_CR3_HDSEL_Msk
     
    #define USART_CR3_NACK_Pos   (4U)
     
    #define USART_CR3_NACK_Msk   (0x1UL << USART_CR3_NACK_Pos)
     
    #define USART_CR3_NACK   USART_CR3_NACK_Msk
     
    #define USART_CR3_SCEN_Pos   (5U)
     
    #define USART_CR3_SCEN_Msk   (0x1UL << USART_CR3_SCEN_Pos)
     
    #define USART_CR3_SCEN   USART_CR3_SCEN_Msk
     
    #define USART_CR3_DMAR_Pos   (6U)
     
    #define USART_CR3_DMAR_Msk   (0x1UL << USART_CR3_DMAR_Pos)
     
    #define USART_CR3_DMAR   USART_CR3_DMAR_Msk
     
    #define USART_CR3_DMAT_Pos   (7U)
     
    #define USART_CR3_DMAT_Msk   (0x1UL << USART_CR3_DMAT_Pos)
     
    #define USART_CR3_DMAT   USART_CR3_DMAT_Msk
     
    #define USART_CR3_RTSE_Pos   (8U)
     
    #define USART_CR3_RTSE_Msk   (0x1UL << USART_CR3_RTSE_Pos)
     
    #define USART_CR3_RTSE   USART_CR3_RTSE_Msk
     
    #define USART_CR3_CTSE_Pos   (9U)
     
    #define USART_CR3_CTSE_Msk   (0x1UL << USART_CR3_CTSE_Pos)
     
    #define USART_CR3_CTSE   USART_CR3_CTSE_Msk
     
    #define USART_CR3_CTSIE_Pos   (10U)
     
    #define USART_CR3_CTSIE_Msk   (0x1UL << USART_CR3_CTSIE_Pos)
     
    #define USART_CR3_CTSIE   USART_CR3_CTSIE_Msk
     
    #define USART_CR3_ONEBIT_Pos   (11U)
     
    #define USART_CR3_ONEBIT_Msk   (0x1UL << USART_CR3_ONEBIT_Pos)
     
    #define USART_CR3_ONEBIT   USART_CR3_ONEBIT_Msk
     
    #define USART_GTPR_PSC_Pos   (0U)
     
    #define USART_GTPR_PSC_Msk   (0xFFUL << USART_GTPR_PSC_Pos)
     
    #define USART_GTPR_PSC   USART_GTPR_PSC_Msk
     
    #define USART_GTPR_PSC_0   (0x01UL << USART_GTPR_PSC_Pos)
     
    #define USART_GTPR_PSC_1   (0x02UL << USART_GTPR_PSC_Pos)
     
    #define USART_GTPR_PSC_2   (0x04UL << USART_GTPR_PSC_Pos)
     
    #define USART_GTPR_PSC_3   (0x08UL << USART_GTPR_PSC_Pos)
     
    #define USART_GTPR_PSC_4   (0x10UL << USART_GTPR_PSC_Pos)
     
    #define USART_GTPR_PSC_5   (0x20UL << USART_GTPR_PSC_Pos)
     
    #define USART_GTPR_PSC_6   (0x40UL << USART_GTPR_PSC_Pos)
     
    #define USART_GTPR_PSC_7   (0x80UL << USART_GTPR_PSC_Pos)
     
    #define USART_GTPR_GT_Pos   (8U)
     
    #define USART_GTPR_GT_Msk   (0xFFUL << USART_GTPR_GT_Pos)
     
    #define USART_GTPR_GT   USART_GTPR_GT_Msk
     
    #define WWDG_CR_T_Pos   (0U)
     
    #define WWDG_CR_T_Msk   (0x7FUL << WWDG_CR_T_Pos)
     
    #define WWDG_CR_T   WWDG_CR_T_Msk
     
    #define WWDG_CR_T_0   (0x01UL << WWDG_CR_T_Pos)
     
    #define WWDG_CR_T_1   (0x02UL << WWDG_CR_T_Pos)
     
    #define WWDG_CR_T_2   (0x04UL << WWDG_CR_T_Pos)
     
    #define WWDG_CR_T_3   (0x08UL << WWDG_CR_T_Pos)
     
    #define WWDG_CR_T_4   (0x10UL << WWDG_CR_T_Pos)
     
    #define WWDG_CR_T_5   (0x20UL << WWDG_CR_T_Pos)
     
    #define WWDG_CR_T_6   (0x40UL << WWDG_CR_T_Pos)
     
    #define WWDG_CR_T0   WWDG_CR_T_0
     
    #define WWDG_CR_T1   WWDG_CR_T_1
     
    #define WWDG_CR_T2   WWDG_CR_T_2
     
    #define WWDG_CR_T3   WWDG_CR_T_3
     
    #define WWDG_CR_T4   WWDG_CR_T_4
     
    #define WWDG_CR_T5   WWDG_CR_T_5
     
    #define WWDG_CR_T6   WWDG_CR_T_6
     
    #define WWDG_CR_WDGA_Pos   (7U)
     
    #define WWDG_CR_WDGA_Msk   (0x1UL << WWDG_CR_WDGA_Pos)
     
    #define WWDG_CR_WDGA   WWDG_CR_WDGA_Msk
     
    #define WWDG_CFR_W_Pos   (0U)
     
    #define WWDG_CFR_W_Msk   (0x7FUL << WWDG_CFR_W_Pos)
     
    #define WWDG_CFR_W   WWDG_CFR_W_Msk
     
    #define WWDG_CFR_W_0   (0x01UL << WWDG_CFR_W_Pos)
     
    #define WWDG_CFR_W_1   (0x02UL << WWDG_CFR_W_Pos)
     
    #define WWDG_CFR_W_2   (0x04UL << WWDG_CFR_W_Pos)
     
    #define WWDG_CFR_W_3   (0x08UL << WWDG_CFR_W_Pos)
     
    #define WWDG_CFR_W_4   (0x10UL << WWDG_CFR_W_Pos)
     
    #define WWDG_CFR_W_5   (0x20UL << WWDG_CFR_W_Pos)
     
    #define WWDG_CFR_W_6   (0x40UL << WWDG_CFR_W_Pos)
     
    #define WWDG_CFR_W0   WWDG_CFR_W_0
     
    #define WWDG_CFR_W1   WWDG_CFR_W_1
     
    #define WWDG_CFR_W2   WWDG_CFR_W_2
     
    #define WWDG_CFR_W3   WWDG_CFR_W_3
     
    #define WWDG_CFR_W4   WWDG_CFR_W_4
     
    #define WWDG_CFR_W5   WWDG_CFR_W_5
     
    #define WWDG_CFR_W6   WWDG_CFR_W_6
     
    #define WWDG_CFR_WDGTB_Pos   (7U)
     
    #define WWDG_CFR_WDGTB_Msk   (0x3UL << WWDG_CFR_WDGTB_Pos)
     
    #define WWDG_CFR_WDGTB   WWDG_CFR_WDGTB_Msk
     
    #define WWDG_CFR_WDGTB_0   (0x1UL << WWDG_CFR_WDGTB_Pos)
     
    #define WWDG_CFR_WDGTB_1   (0x2UL << WWDG_CFR_WDGTB_Pos)
     
    #define WWDG_CFR_WDGTB0   WWDG_CFR_WDGTB_0
     
    #define WWDG_CFR_WDGTB1   WWDG_CFR_WDGTB_1
     
    #define WWDG_CFR_EWI_Pos   (9U)
     
    #define WWDG_CFR_EWI_Msk   (0x1UL << WWDG_CFR_EWI_Pos)
     
    #define WWDG_CFR_EWI   WWDG_CFR_EWI_Msk
     
    #define WWDG_SR_EWIF_Pos   (0U)
     
    #define WWDG_SR_EWIF_Msk   (0x1UL << WWDG_SR_EWIF_Pos)
     
    #define WWDG_SR_EWIF   WWDG_SR_EWIF_Msk
     
    #define DBGMCU_IDCODE_DEV_ID_Pos   (0U)
     
    #define DBGMCU_IDCODE_DEV_ID_Msk   (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos)
     
    #define DBGMCU_IDCODE_DEV_ID   DBGMCU_IDCODE_DEV_ID_Msk
     
    #define DBGMCU_IDCODE_REV_ID_Pos   (16U)
     
    #define DBGMCU_IDCODE_REV_ID_Msk   (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos)
     
    #define DBGMCU_IDCODE_REV_ID   DBGMCU_IDCODE_REV_ID_Msk
     
    #define DBGMCU_CR_DBG_SLEEP_Pos   (0U)
     
    #define DBGMCU_CR_DBG_SLEEP_Msk   (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos)
     
    #define DBGMCU_CR_DBG_SLEEP   DBGMCU_CR_DBG_SLEEP_Msk
     
    #define DBGMCU_CR_DBG_STOP_Pos   (1U)
     
    #define DBGMCU_CR_DBG_STOP_Msk   (0x1UL << DBGMCU_CR_DBG_STOP_Pos)
     
    #define DBGMCU_CR_DBG_STOP   DBGMCU_CR_DBG_STOP_Msk
     
    #define DBGMCU_CR_DBG_STANDBY_Pos   (2U)
     
    #define DBGMCU_CR_DBG_STANDBY_Msk   (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos)
     
    #define DBGMCU_CR_DBG_STANDBY   DBGMCU_CR_DBG_STANDBY_Msk
     
    #define DBGMCU_CR_TRACE_IOEN_Pos   (5U)
     
    #define DBGMCU_CR_TRACE_IOEN_Msk   (0x1UL << DBGMCU_CR_TRACE_IOEN_Pos)
     
    #define DBGMCU_CR_TRACE_IOEN   DBGMCU_CR_TRACE_IOEN_Msk
     
    #define DBGMCU_CR_TRACE_MODE_Pos   (6U)
     
    #define DBGMCU_CR_TRACE_MODE_Msk   (0x3UL << DBGMCU_CR_TRACE_MODE_Pos)
     
    #define DBGMCU_CR_TRACE_MODE   DBGMCU_CR_TRACE_MODE_Msk
     
    #define DBGMCU_CR_TRACE_MODE_0   (0x1UL << DBGMCU_CR_TRACE_MODE_Pos)
     
    #define DBGMCU_CR_TRACE_MODE_1   (0x2UL << DBGMCU_CR_TRACE_MODE_Pos)
     
    #define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos   (0U)
     
    #define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk   (0x1UL << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos)
     
    #define DBGMCU_APB1_FZ_DBG_TIM2_STOP   DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk
     
    #define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos   (1U)
     
    #define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk   (0x1UL << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos)
     
    #define DBGMCU_APB1_FZ_DBG_TIM3_STOP   DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk
     
    #define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos   (2U)
     
    #define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk   (0x1UL << DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos)
     
    #define DBGMCU_APB1_FZ_DBG_TIM4_STOP   DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk
     
    #define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos   (3U)
     
    #define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk   (0x1UL << DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos)
     
    #define DBGMCU_APB1_FZ_DBG_TIM5_STOP   DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk
     
    #define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos   (4U)
     
    #define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk   (0x1UL << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos)
     
    #define DBGMCU_APB1_FZ_DBG_TIM6_STOP   DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk
     
    #define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos   (5U)
     
    #define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk   (0x1UL << DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos)
     
    #define DBGMCU_APB1_FZ_DBG_TIM7_STOP   DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk
     
    #define DBGMCU_APB1_FZ_DBG_TIM12_STOP_Pos   (6U)
     
    #define DBGMCU_APB1_FZ_DBG_TIM12_STOP_Msk   (0x1UL << DBGMCU_APB1_FZ_DBG_TIM12_STOP_Pos)
     
    #define DBGMCU_APB1_FZ_DBG_TIM12_STOP   DBGMCU_APB1_FZ_DBG_TIM12_STOP_Msk
     
    #define DBGMCU_APB1_FZ_DBG_TIM13_STOP_Pos   (7U)
     
    #define DBGMCU_APB1_FZ_DBG_TIM13_STOP_Msk   (0x1UL << DBGMCU_APB1_FZ_DBG_TIM13_STOP_Pos)
     
    #define DBGMCU_APB1_FZ_DBG_TIM13_STOP   DBGMCU_APB1_FZ_DBG_TIM13_STOP_Msk
     
    #define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos   (8U)
     
    #define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk   (0x1UL << DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos)
     
    #define DBGMCU_APB1_FZ_DBG_TIM14_STOP   DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk
     
    #define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos   (10U)
     
    #define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk   (0x1UL << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos)
     
    #define DBGMCU_APB1_FZ_DBG_RTC_STOP   DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk
     
    #define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos   (11U)
     
    #define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk   (0x1UL << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos)
     
    #define DBGMCU_APB1_FZ_DBG_WWDG_STOP   DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk
     
    #define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos   (12U)
     
    #define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk   (0x1UL << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos)
     
    #define DBGMCU_APB1_FZ_DBG_IWDG_STOP   DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk
     
    #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos   (21U)
     
    #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk   (0x1UL << DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos)
     
    #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT   DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk
     
    #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos   (22U)
     
    #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk   (0x1UL << DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos)
     
    #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT   DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk
     
    #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos   (23U)
     
    #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk   (0x1UL << DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos)
     
    #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT   DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk
     
    #define DBGMCU_APB1_FZ_DBG_CAN1_STOP_Pos   (25U)
     
    #define DBGMCU_APB1_FZ_DBG_CAN1_STOP_Msk   (0x1UL << DBGMCU_APB1_FZ_DBG_CAN1_STOP_Pos)
     
    #define DBGMCU_APB1_FZ_DBG_CAN1_STOP   DBGMCU_APB1_FZ_DBG_CAN1_STOP_Msk
     
    #define DBGMCU_APB1_FZ_DBG_CAN2_STOP_Pos   (26U)
     
    #define DBGMCU_APB1_FZ_DBG_CAN2_STOP_Msk   (0x1UL << DBGMCU_APB1_FZ_DBG_CAN2_STOP_Pos)
     
    #define DBGMCU_APB1_FZ_DBG_CAN2_STOP   DBGMCU_APB1_FZ_DBG_CAN2_STOP_Msk
     
    #define DBGMCU_APB1_FZ_DBG_IWDEG_STOP   DBGMCU_APB1_FZ_DBG_IWDG_STOP
     
    #define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos   (0U)
     
    #define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk   (0x1UL << DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos)
     
    #define DBGMCU_APB2_FZ_DBG_TIM1_STOP   DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk
     
    #define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos   (1U)
     
    #define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk   (0x1UL << DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos)
     
    #define DBGMCU_APB2_FZ_DBG_TIM8_STOP   DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk
     
    #define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos   (16U)
     
    #define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk   (0x1UL << DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos)
     
    #define DBGMCU_APB2_FZ_DBG_TIM9_STOP   DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk
     
    #define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos   (17U)
     
    #define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk   (0x1UL << DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos)
     
    #define DBGMCU_APB2_FZ_DBG_TIM10_STOP   DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk
     
    #define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos   (18U)
     
    #define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk   (0x1UL << DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos)
     
    #define DBGMCU_APB2_FZ_DBG_TIM11_STOP   DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk
     
    #define ETH_MACCR_WD_Pos   (23U)
     
    #define ETH_MACCR_WD_Msk   (0x1UL << ETH_MACCR_WD_Pos)
     
    #define ETH_MACCR_WD   ETH_MACCR_WD_Msk /* Watchdog disable */
     
    #define ETH_MACCR_JD_Pos   (22U)
     
    #define ETH_MACCR_JD_Msk   (0x1UL << ETH_MACCR_JD_Pos)
     
    #define ETH_MACCR_JD   ETH_MACCR_JD_Msk /* Jabber disable */
     
    #define ETH_MACCR_IFG_Pos   (17U)
     
    #define ETH_MACCR_IFG_Msk   (0x7UL << ETH_MACCR_IFG_Pos)
     
    #define ETH_MACCR_IFG   ETH_MACCR_IFG_Msk /* Inter-frame gap */
     
    #define ETH_MACCR_IFG_96Bit   0x00000000U /* Minimum IFG between frames during transmission is 96Bit */
     
    #define ETH_MACCR_IFG_88Bit   0x00020000U /* Minimum IFG between frames during transmission is 88Bit */
     
    #define ETH_MACCR_IFG_80Bit   0x00040000U /* Minimum IFG between frames during transmission is 80Bit */
     
    #define ETH_MACCR_IFG_72Bit   0x00060000U /* Minimum IFG between frames during transmission is 72Bit */
     
    #define ETH_MACCR_IFG_64Bit   0x00080000U /* Minimum IFG between frames during transmission is 64Bit */
     
    #define ETH_MACCR_IFG_56Bit   0x000A0000U /* Minimum IFG between frames during transmission is 56Bit */
     
    #define ETH_MACCR_IFG_48Bit   0x000C0000U /* Minimum IFG between frames during transmission is 48Bit */
     
    #define ETH_MACCR_IFG_40Bit   0x000E0000U /* Minimum IFG between frames during transmission is 40Bit */
     
    #define ETH_MACCR_CSD_Pos   (16U)
     
    #define ETH_MACCR_CSD_Msk   (0x1UL << ETH_MACCR_CSD_Pos)
     
    #define ETH_MACCR_CSD   ETH_MACCR_CSD_Msk /* Carrier sense disable (during transmission) */
     
    #define ETH_MACCR_FES_Pos   (14U)
     
    #define ETH_MACCR_FES_Msk   (0x1UL << ETH_MACCR_FES_Pos)
     
    #define ETH_MACCR_FES   ETH_MACCR_FES_Msk /* Fast ethernet speed */
     
    #define ETH_MACCR_ROD_Pos   (13U)
     
    #define ETH_MACCR_ROD_Msk   (0x1UL << ETH_MACCR_ROD_Pos)
     
    #define ETH_MACCR_ROD   ETH_MACCR_ROD_Msk /* Receive own disable */
     
    #define ETH_MACCR_LM_Pos   (12U)
     
    #define ETH_MACCR_LM_Msk   (0x1UL << ETH_MACCR_LM_Pos)
     
    #define ETH_MACCR_LM   ETH_MACCR_LM_Msk /* loopback mode */
     
    #define ETH_MACCR_DM_Pos   (11U)
     
    #define ETH_MACCR_DM_Msk   (0x1UL << ETH_MACCR_DM_Pos)
     
    #define ETH_MACCR_DM   ETH_MACCR_DM_Msk /* Duplex mode */
     
    #define ETH_MACCR_IPCO_Pos   (10U)
     
    #define ETH_MACCR_IPCO_Msk   (0x1UL << ETH_MACCR_IPCO_Pos)
     
    #define ETH_MACCR_IPCO   ETH_MACCR_IPCO_Msk /* IP Checksum offload */
     
    #define ETH_MACCR_RD_Pos   (9U)
     
    #define ETH_MACCR_RD_Msk   (0x1UL << ETH_MACCR_RD_Pos)
     
    #define ETH_MACCR_RD   ETH_MACCR_RD_Msk /* Retry disable */
     
    #define ETH_MACCR_APCS_Pos   (7U)
     
    #define ETH_MACCR_APCS_Msk   (0x1UL << ETH_MACCR_APCS_Pos)
     
    #define ETH_MACCR_APCS   ETH_MACCR_APCS_Msk /* Automatic Pad/CRC stripping */
     
    #define ETH_MACCR_BL_Pos   (5U)
     
    #define ETH_MACCR_BL_Msk   (0x3UL << ETH_MACCR_BL_Pos)
     
    #define ETH_MACCR_BL
     
    #define ETH_MACCR_BL_10   0x00000000U /* k = min (n, 10) */
     
    #define ETH_MACCR_BL_8   0x00000020U /* k = min (n, 8) */
     
    #define ETH_MACCR_BL_4   0x00000040U /* k = min (n, 4) */
     
    #define ETH_MACCR_BL_1   0x00000060U /* k = min (n, 1) */
     
    #define ETH_MACCR_DC_Pos   (4U)
     
    #define ETH_MACCR_DC_Msk   (0x1UL << ETH_MACCR_DC_Pos)
     
    #define ETH_MACCR_DC   ETH_MACCR_DC_Msk /* Defferal check */
     
    #define ETH_MACCR_TE_Pos   (3U)
     
    #define ETH_MACCR_TE_Msk   (0x1UL << ETH_MACCR_TE_Pos)
     
    #define ETH_MACCR_TE   ETH_MACCR_TE_Msk /* Transmitter enable */
     
    #define ETH_MACCR_RE_Pos   (2U)
     
    #define ETH_MACCR_RE_Msk   (0x1UL << ETH_MACCR_RE_Pos)
     
    #define ETH_MACCR_RE   ETH_MACCR_RE_Msk /* Receiver enable */
     
    #define ETH_MACFFR_RA_Pos   (31U)
     
    #define ETH_MACFFR_RA_Msk   (0x1UL << ETH_MACFFR_RA_Pos)
     
    #define ETH_MACFFR_RA   ETH_MACFFR_RA_Msk /* Receive all */
     
    #define ETH_MACFFR_HPF_Pos   (10U)
     
    #define ETH_MACFFR_HPF_Msk   (0x1UL << ETH_MACFFR_HPF_Pos)
     
    #define ETH_MACFFR_HPF   ETH_MACFFR_HPF_Msk /* Hash or perfect filter */
     
    #define ETH_MACFFR_SAF_Pos   (9U)
     
    #define ETH_MACFFR_SAF_Msk   (0x1UL << ETH_MACFFR_SAF_Pos)
     
    #define ETH_MACFFR_SAF   ETH_MACFFR_SAF_Msk /* Source address filter enable */
     
    #define ETH_MACFFR_SAIF_Pos   (8U)
     
    #define ETH_MACFFR_SAIF_Msk   (0x1UL << ETH_MACFFR_SAIF_Pos)
     
    #define ETH_MACFFR_SAIF   ETH_MACFFR_SAIF_Msk /* SA inverse filtering */
     
    #define ETH_MACFFR_PCF_Pos   (6U)
     
    #define ETH_MACFFR_PCF_Msk   (0x3UL << ETH_MACFFR_PCF_Pos)
     
    #define ETH_MACFFR_PCF   ETH_MACFFR_PCF_Msk /* Pass control frames: 3 cases */
     
    #define ETH_MACFFR_PCF_BlockAll_Pos   (6U)
     
    #define ETH_MACFFR_PCF_BlockAll_Msk   (0x1UL << ETH_MACFFR_PCF_BlockAll_Pos)
     
    #define ETH_MACFFR_PCF_BlockAll   ETH_MACFFR_PCF_BlockAll_Msk /* MAC filters all control frames from reaching the application */
     
    #define ETH_MACFFR_PCF_ForwardAll_Pos   (7U)
     
    #define ETH_MACFFR_PCF_ForwardAll_Msk   (0x1UL << ETH_MACFFR_PCF_ForwardAll_Pos)
     
    #define ETH_MACFFR_PCF_ForwardAll   ETH_MACFFR_PCF_ForwardAll_Msk /* MAC forwards all control frames to application even if they fail the Address Filter */
     
    #define ETH_MACFFR_PCF_ForwardPassedAddrFilter_Pos   (6U)
     
    #define ETH_MACFFR_PCF_ForwardPassedAddrFilter_Msk   (0x3UL << ETH_MACFFR_PCF_ForwardPassedAddrFilter_Pos)
     
    #define ETH_MACFFR_PCF_ForwardPassedAddrFilter   ETH_MACFFR_PCF_ForwardPassedAddrFilter_Msk /* MAC forwards control frames that pass the Address Filter. */
     
    #define ETH_MACFFR_BFD_Pos   (5U)
     
    #define ETH_MACFFR_BFD_Msk   (0x1UL << ETH_MACFFR_BFD_Pos)
     
    #define ETH_MACFFR_BFD   ETH_MACFFR_BFD_Msk /* Broadcast frame disable */
     
    #define ETH_MACFFR_PAM_Pos   (4U)
     
    #define ETH_MACFFR_PAM_Msk   (0x1UL << ETH_MACFFR_PAM_Pos)
     
    #define ETH_MACFFR_PAM   ETH_MACFFR_PAM_Msk /* Pass all mutlicast */
     
    #define ETH_MACFFR_DAIF_Pos   (3U)
     
    #define ETH_MACFFR_DAIF_Msk   (0x1UL << ETH_MACFFR_DAIF_Pos)
     
    #define ETH_MACFFR_DAIF   ETH_MACFFR_DAIF_Msk /* DA Inverse filtering */
     
    #define ETH_MACFFR_HM_Pos   (2U)
     
    #define ETH_MACFFR_HM_Msk   (0x1UL << ETH_MACFFR_HM_Pos)
     
    #define ETH_MACFFR_HM   ETH_MACFFR_HM_Msk /* Hash multicast */
     
    #define ETH_MACFFR_HU_Pos   (1U)
     
    #define ETH_MACFFR_HU_Msk   (0x1UL << ETH_MACFFR_HU_Pos)
     
    #define ETH_MACFFR_HU   ETH_MACFFR_HU_Msk /* Hash unicast */
     
    #define ETH_MACFFR_PM_Pos   (0U)
     
    #define ETH_MACFFR_PM_Msk   (0x1UL << ETH_MACFFR_PM_Pos)
     
    #define ETH_MACFFR_PM   ETH_MACFFR_PM_Msk /* Promiscuous mode */
     
    #define ETH_MACHTHR_HTH_Pos   (0U)
     
    #define ETH_MACHTHR_HTH_Msk   (0xFFFFFFFFUL << ETH_MACHTHR_HTH_Pos)
     
    #define ETH_MACHTHR_HTH   ETH_MACHTHR_HTH_Msk /* Hash table high */
     
    #define ETH_MACHTLR_HTL_Pos   (0U)
     
    #define ETH_MACHTLR_HTL_Msk   (0xFFFFFFFFUL << ETH_MACHTLR_HTL_Pos)
     
    #define ETH_MACHTLR_HTL   ETH_MACHTLR_HTL_Msk /* Hash table low */
     
    #define ETH_MACMIIAR_PA_Pos   (11U)
     
    #define ETH_MACMIIAR_PA_Msk   (0x1FUL << ETH_MACMIIAR_PA_Pos)
     
    #define ETH_MACMIIAR_PA   ETH_MACMIIAR_PA_Msk /* Physical layer address */
     
    #define ETH_MACMIIAR_MR_Pos   (6U)
     
    #define ETH_MACMIIAR_MR_Msk   (0x1FUL << ETH_MACMIIAR_MR_Pos)
     
    #define ETH_MACMIIAR_MR   ETH_MACMIIAR_MR_Msk /* MII register in the selected PHY */
     
    #define ETH_MACMIIAR_CR_Pos   (2U)
     
    #define ETH_MACMIIAR_CR_Msk   (0x7UL << ETH_MACMIIAR_CR_Pos)
     
    #define ETH_MACMIIAR_CR   ETH_MACMIIAR_CR_Msk /* CR clock range: 6 cases */
     
    #define ETH_MACMIIAR_CR_Div42   0x00000000U /* HCLK:60-100 MHz; MDC clock= HCLK/42 */
     
    #define ETH_MACMIIAR_CR_Div62_Pos   (2U)
     
    #define ETH_MACMIIAR_CR_Div62_Msk   (0x1UL << ETH_MACMIIAR_CR_Div62_Pos)
     
    #define ETH_MACMIIAR_CR_Div62   ETH_MACMIIAR_CR_Div62_Msk /* HCLK:100-150 MHz; MDC clock= HCLK/62 */
     
    #define ETH_MACMIIAR_CR_Div16_Pos   (3U)
     
    #define ETH_MACMIIAR_CR_Div16_Msk   (0x1UL << ETH_MACMIIAR_CR_Div16_Pos)
     
    #define ETH_MACMIIAR_CR_Div16   ETH_MACMIIAR_CR_Div16_Msk /* HCLK:20-35 MHz; MDC clock= HCLK/16 */
     
    #define ETH_MACMIIAR_CR_Div26_Pos   (2U)
     
    #define ETH_MACMIIAR_CR_Div26_Msk   (0x3UL << ETH_MACMIIAR_CR_Div26_Pos)
     
    #define ETH_MACMIIAR_CR_Div26   ETH_MACMIIAR_CR_Div26_Msk /* HCLK:35-60 MHz; MDC clock= HCLK/26 */
     
    #define ETH_MACMIIAR_CR_Div102_Pos   (4U)
     
    #define ETH_MACMIIAR_CR_Div102_Msk   (0x1UL << ETH_MACMIIAR_CR_Div102_Pos)
     
    #define ETH_MACMIIAR_CR_Div102   ETH_MACMIIAR_CR_Div102_Msk /* HCLK:150-168 MHz; MDC clock= HCLK/102 */
     
    #define ETH_MACMIIAR_MW_Pos   (1U)
     
    #define ETH_MACMIIAR_MW_Msk   (0x1UL << ETH_MACMIIAR_MW_Pos)
     
    #define ETH_MACMIIAR_MW   ETH_MACMIIAR_MW_Msk /* MII write */
     
    #define ETH_MACMIIAR_MB_Pos   (0U)
     
    #define ETH_MACMIIAR_MB_Msk   (0x1UL << ETH_MACMIIAR_MB_Pos)
     
    #define ETH_MACMIIAR_MB   ETH_MACMIIAR_MB_Msk /* MII busy */
     
    #define ETH_MACMIIDR_MD_Pos   (0U)
     
    #define ETH_MACMIIDR_MD_Msk   (0xFFFFUL << ETH_MACMIIDR_MD_Pos)
     
    #define ETH_MACMIIDR_MD   ETH_MACMIIDR_MD_Msk /* MII data: read/write data from/to PHY */
     
    #define ETH_MACFCR_PT_Pos   (16U)
     
    #define ETH_MACFCR_PT_Msk   (0xFFFFUL << ETH_MACFCR_PT_Pos)
     
    #define ETH_MACFCR_PT   ETH_MACFCR_PT_Msk /* Pause time */
     
    #define ETH_MACFCR_ZQPD_Pos   (7U)
     
    #define ETH_MACFCR_ZQPD_Msk   (0x1UL << ETH_MACFCR_ZQPD_Pos)
     
    #define ETH_MACFCR_ZQPD   ETH_MACFCR_ZQPD_Msk /* Zero-quanta pause disable */
     
    #define ETH_MACFCR_PLT_Pos   (4U)
     
    #define ETH_MACFCR_PLT_Msk   (0x3UL << ETH_MACFCR_PLT_Pos)
     
    #define ETH_MACFCR_PLT   ETH_MACFCR_PLT_Msk /* Pause low threshold: 4 cases */
     
    #define ETH_MACFCR_PLT_Minus4   0x00000000U /* Pause time minus 4 slot times */
     
    #define ETH_MACFCR_PLT_Minus28_Pos   (4U)
     
    #define ETH_MACFCR_PLT_Minus28_Msk   (0x1UL << ETH_MACFCR_PLT_Minus28_Pos)
     
    #define ETH_MACFCR_PLT_Minus28   ETH_MACFCR_PLT_Minus28_Msk /* Pause time minus 28 slot times */
     
    #define ETH_MACFCR_PLT_Minus144_Pos   (5U)
     
    #define ETH_MACFCR_PLT_Minus144_Msk   (0x1UL << ETH_MACFCR_PLT_Minus144_Pos)
     
    #define ETH_MACFCR_PLT_Minus144   ETH_MACFCR_PLT_Minus144_Msk /* Pause time minus 144 slot times */
     
    #define ETH_MACFCR_PLT_Minus256_Pos   (4U)
     
    #define ETH_MACFCR_PLT_Minus256_Msk   (0x3UL << ETH_MACFCR_PLT_Minus256_Pos)
     
    #define ETH_MACFCR_PLT_Minus256   ETH_MACFCR_PLT_Minus256_Msk /* Pause time minus 256 slot times */
     
    #define ETH_MACFCR_UPFD_Pos   (3U)
     
    #define ETH_MACFCR_UPFD_Msk   (0x1UL << ETH_MACFCR_UPFD_Pos)
     
    #define ETH_MACFCR_UPFD   ETH_MACFCR_UPFD_Msk /* Unicast pause frame detect */
     
    #define ETH_MACFCR_RFCE_Pos   (2U)
     
    #define ETH_MACFCR_RFCE_Msk   (0x1UL << ETH_MACFCR_RFCE_Pos)
     
    #define ETH_MACFCR_RFCE   ETH_MACFCR_RFCE_Msk /* Receive flow control enable */
     
    #define ETH_MACFCR_TFCE_Pos   (1U)
     
    #define ETH_MACFCR_TFCE_Msk   (0x1UL << ETH_MACFCR_TFCE_Pos)
     
    #define ETH_MACFCR_TFCE   ETH_MACFCR_TFCE_Msk /* Transmit flow control enable */
     
    #define ETH_MACFCR_FCBBPA_Pos   (0U)
     
    #define ETH_MACFCR_FCBBPA_Msk   (0x1UL << ETH_MACFCR_FCBBPA_Pos)
     
    #define ETH_MACFCR_FCBBPA   ETH_MACFCR_FCBBPA_Msk /* Flow control busy/backpressure activate */
     
    #define ETH_MACVLANTR_VLANTC_Pos   (16U)
     
    #define ETH_MACVLANTR_VLANTC_Msk   (0x1UL << ETH_MACVLANTR_VLANTC_Pos)
     
    #define ETH_MACVLANTR_VLANTC   ETH_MACVLANTR_VLANTC_Msk /* 12-bit VLAN tag comparison */
     
    #define ETH_MACVLANTR_VLANTI_Pos   (0U)
     
    #define ETH_MACVLANTR_VLANTI_Msk   (0xFFFFUL << ETH_MACVLANTR_VLANTI_Pos)
     
    #define ETH_MACVLANTR_VLANTI   ETH_MACVLANTR_VLANTI_Msk /* VLAN tag identifier (for receive frames) */
     
    #define ETH_MACRWUFFR_D_Pos   (0U)
     
    #define ETH_MACRWUFFR_D_Msk   (0xFFFFFFFFUL << ETH_MACRWUFFR_D_Pos)
     
    #define ETH_MACRWUFFR_D   ETH_MACRWUFFR_D_Msk /* Wake-up frame filter register data */
     
    #define ETH_MACPMTCSR_WFFRPR_Pos   (31U)
     
    #define ETH_MACPMTCSR_WFFRPR_Msk   (0x1UL << ETH_MACPMTCSR_WFFRPR_Pos)
     
    #define ETH_MACPMTCSR_WFFRPR   ETH_MACPMTCSR_WFFRPR_Msk /* Wake-Up Frame Filter Register Pointer Reset */
     
    #define ETH_MACPMTCSR_GU_Pos   (9U)
     
    #define ETH_MACPMTCSR_GU_Msk   (0x1UL << ETH_MACPMTCSR_GU_Pos)
     
    #define ETH_MACPMTCSR_GU   ETH_MACPMTCSR_GU_Msk /* Global Unicast */
     
    #define ETH_MACPMTCSR_WFR_Pos   (6U)
     
    #define ETH_MACPMTCSR_WFR_Msk   (0x1UL << ETH_MACPMTCSR_WFR_Pos)
     
    #define ETH_MACPMTCSR_WFR   ETH_MACPMTCSR_WFR_Msk /* Wake-Up Frame Received */
     
    #define ETH_MACPMTCSR_MPR_Pos   (5U)
     
    #define ETH_MACPMTCSR_MPR_Msk   (0x1UL << ETH_MACPMTCSR_MPR_Pos)
     
    #define ETH_MACPMTCSR_MPR   ETH_MACPMTCSR_MPR_Msk /* Magic Packet Received */
     
    #define ETH_MACPMTCSR_WFE_Pos   (2U)
     
    #define ETH_MACPMTCSR_WFE_Msk   (0x1UL << ETH_MACPMTCSR_WFE_Pos)
     
    #define ETH_MACPMTCSR_WFE   ETH_MACPMTCSR_WFE_Msk /* Wake-Up Frame Enable */
     
    #define ETH_MACPMTCSR_MPE_Pos   (1U)
     
    #define ETH_MACPMTCSR_MPE_Msk   (0x1UL << ETH_MACPMTCSR_MPE_Pos)
     
    #define ETH_MACPMTCSR_MPE   ETH_MACPMTCSR_MPE_Msk /* Magic Packet Enable */
     
    #define ETH_MACPMTCSR_PD_Pos   (0U)
     
    #define ETH_MACPMTCSR_PD_Msk   (0x1UL << ETH_MACPMTCSR_PD_Pos)
     
    #define ETH_MACPMTCSR_PD   ETH_MACPMTCSR_PD_Msk /* Power Down */
     
    #define ETH_MACDBGR_TFF_Pos   (25U)
     
    #define ETH_MACDBGR_TFF_Msk   (0x1UL << ETH_MACDBGR_TFF_Pos)
     
    #define ETH_MACDBGR_TFF   ETH_MACDBGR_TFF_Msk /* Tx FIFO full */
     
    #define ETH_MACDBGR_TFNE_Pos   (24U)
     
    #define ETH_MACDBGR_TFNE_Msk   (0x1UL << ETH_MACDBGR_TFNE_Pos)
     
    #define ETH_MACDBGR_TFNE   ETH_MACDBGR_TFNE_Msk /* Tx FIFO not empty */
     
    #define ETH_MACDBGR_TFWA_Pos   (22U)
     
    #define ETH_MACDBGR_TFWA_Msk   (0x1UL << ETH_MACDBGR_TFWA_Pos)
     
    #define ETH_MACDBGR_TFWA   ETH_MACDBGR_TFWA_Msk /* Tx FIFO write active */
     
    #define ETH_MACDBGR_TFRS_Pos   (20U)
     
    #define ETH_MACDBGR_TFRS_Msk   (0x3UL << ETH_MACDBGR_TFRS_Pos)
     
    #define ETH_MACDBGR_TFRS   ETH_MACDBGR_TFRS_Msk /* Tx FIFO read status mask */
     
    #define ETH_MACDBGR_TFRS_WRITING_Pos   (20U)
     
    #define ETH_MACDBGR_TFRS_WRITING_Msk   (0x3UL << ETH_MACDBGR_TFRS_WRITING_Pos)
     
    #define ETH_MACDBGR_TFRS_WRITING   ETH_MACDBGR_TFRS_WRITING_Msk /* Writing the received TxStatus or flushing the TxFIFO */
     
    #define ETH_MACDBGR_TFRS_WAITING_Pos   (21U)
     
    #define ETH_MACDBGR_TFRS_WAITING_Msk   (0x1UL << ETH_MACDBGR_TFRS_WAITING_Pos)
     
    #define ETH_MACDBGR_TFRS_WAITING   ETH_MACDBGR_TFRS_WAITING_Msk /* Waiting for TxStatus from MAC transmitter */
     
    #define ETH_MACDBGR_TFRS_READ_Pos   (20U)
     
    #define ETH_MACDBGR_TFRS_READ_Msk   (0x1UL << ETH_MACDBGR_TFRS_READ_Pos)
     
    #define ETH_MACDBGR_TFRS_READ   ETH_MACDBGR_TFRS_READ_Msk /* Read state (transferring data to the MAC transmitter) */
     
    #define ETH_MACDBGR_TFRS_IDLE   0x00000000U /* Idle state */
     
    #define ETH_MACDBGR_MTP_Pos   (19U)
     
    #define ETH_MACDBGR_MTP_Msk   (0x1UL << ETH_MACDBGR_MTP_Pos)
     
    #define ETH_MACDBGR_MTP   ETH_MACDBGR_MTP_Msk /* MAC transmitter in pause */
     
    #define ETH_MACDBGR_MTFCS_Pos   (17U)
     
    #define ETH_MACDBGR_MTFCS_Msk   (0x3UL << ETH_MACDBGR_MTFCS_Pos)
     
    #define ETH_MACDBGR_MTFCS   ETH_MACDBGR_MTFCS_Msk /* MAC transmit frame controller status mask */
     
    #define ETH_MACDBGR_MTFCS_TRANSFERRING_Pos   (17U)
     
    #define ETH_MACDBGR_MTFCS_TRANSFERRING_Msk   (0x3UL << ETH_MACDBGR_MTFCS_TRANSFERRING_Pos)
     
    #define ETH_MACDBGR_MTFCS_TRANSFERRING   ETH_MACDBGR_MTFCS_TRANSFERRING_Msk /* Transferring input frame for transmission */
     
    #define ETH_MACDBGR_MTFCS_GENERATINGPCF_Pos   (18U)
     
    #define ETH_MACDBGR_MTFCS_GENERATINGPCF_Msk   (0x1UL << ETH_MACDBGR_MTFCS_GENERATINGPCF_Pos)
     
    #define ETH_MACDBGR_MTFCS_GENERATINGPCF   ETH_MACDBGR_MTFCS_GENERATINGPCF_Msk /* Generating and transmitting a Pause control frame (in full duplex mode) */
     
    #define ETH_MACDBGR_MTFCS_WAITING_Pos   (17U)
     
    #define ETH_MACDBGR_MTFCS_WAITING_Msk   (0x1UL << ETH_MACDBGR_MTFCS_WAITING_Pos)
     
    #define ETH_MACDBGR_MTFCS_WAITING   ETH_MACDBGR_MTFCS_WAITING_Msk /* Waiting for Status of previous frame or IFG/backoff period to be over */
     
    #define ETH_MACDBGR_MTFCS_IDLE   0x00000000U /* Idle */
     
    #define ETH_MACDBGR_MMTEA_Pos   (16U)
     
    #define ETH_MACDBGR_MMTEA_Msk   (0x1UL << ETH_MACDBGR_MMTEA_Pos)
     
    #define ETH_MACDBGR_MMTEA   ETH_MACDBGR_MMTEA_Msk /* MAC MII transmit engine active */
     
    #define ETH_MACDBGR_RFFL_Pos   (8U)
     
    #define ETH_MACDBGR_RFFL_Msk   (0x3UL << ETH_MACDBGR_RFFL_Pos)
     
    #define ETH_MACDBGR_RFFL   ETH_MACDBGR_RFFL_Msk /* Rx FIFO fill level mask */
     
    #define ETH_MACDBGR_RFFL_FULL_Pos   (8U)
     
    #define ETH_MACDBGR_RFFL_FULL_Msk   (0x3UL << ETH_MACDBGR_RFFL_FULL_Pos)
     
    #define ETH_MACDBGR_RFFL_FULL   ETH_MACDBGR_RFFL_FULL_Msk /* RxFIFO full */
     
    #define ETH_MACDBGR_RFFL_ABOVEFCT_Pos   (9U)
     
    #define ETH_MACDBGR_RFFL_ABOVEFCT_Msk   (0x1UL << ETH_MACDBGR_RFFL_ABOVEFCT_Pos)
     
    #define ETH_MACDBGR_RFFL_ABOVEFCT   ETH_MACDBGR_RFFL_ABOVEFCT_Msk /* RxFIFO fill-level above flow-control activate threshold */
     
    #define ETH_MACDBGR_RFFL_BELOWFCT_Pos   (8U)
     
    #define ETH_MACDBGR_RFFL_BELOWFCT_Msk   (0x1UL << ETH_MACDBGR_RFFL_BELOWFCT_Pos)
     
    #define ETH_MACDBGR_RFFL_BELOWFCT   ETH_MACDBGR_RFFL_BELOWFCT_Msk /* RxFIFO fill-level below flow-control de-activate threshold */
     
    #define ETH_MACDBGR_RFFL_EMPTY   0x00000000U /* RxFIFO empty */
     
    #define ETH_MACDBGR_RFRCS_Pos   (5U)
     
    #define ETH_MACDBGR_RFRCS_Msk   (0x3UL << ETH_MACDBGR_RFRCS_Pos)
     
    #define ETH_MACDBGR_RFRCS   ETH_MACDBGR_RFRCS_Msk /* Rx FIFO read controller status mask */
     
    #define ETH_MACDBGR_RFRCS_FLUSHING_Pos   (5U)
     
    #define ETH_MACDBGR_RFRCS_FLUSHING_Msk   (0x3UL << ETH_MACDBGR_RFRCS_FLUSHING_Pos)
     
    #define ETH_MACDBGR_RFRCS_FLUSHING   ETH_MACDBGR_RFRCS_FLUSHING_Msk /* Flushing the frame data and status */
     
    #define ETH_MACDBGR_RFRCS_STATUSREADING_Pos   (6U)
     
    #define ETH_MACDBGR_RFRCS_STATUSREADING_Msk   (0x1UL << ETH_MACDBGR_RFRCS_STATUSREADING_Pos)
     
    #define ETH_MACDBGR_RFRCS_STATUSREADING   ETH_MACDBGR_RFRCS_STATUSREADING_Msk /* Reading frame status (or time-stamp) */
     
    #define ETH_MACDBGR_RFRCS_DATAREADING_Pos   (5U)
     
    #define ETH_MACDBGR_RFRCS_DATAREADING_Msk   (0x1UL << ETH_MACDBGR_RFRCS_DATAREADING_Pos)
     
    #define ETH_MACDBGR_RFRCS_DATAREADING   ETH_MACDBGR_RFRCS_DATAREADING_Msk /* Reading frame data */
     
    #define ETH_MACDBGR_RFRCS_IDLE   0x00000000U /* IDLE state */
     
    #define ETH_MACDBGR_RFWRA_Pos   (4U)
     
    #define ETH_MACDBGR_RFWRA_Msk   (0x1UL << ETH_MACDBGR_RFWRA_Pos)
     
    #define ETH_MACDBGR_RFWRA   ETH_MACDBGR_RFWRA_Msk /* Rx FIFO write controller active */
     
    #define ETH_MACDBGR_MSFRWCS_Pos   (1U)
     
    #define ETH_MACDBGR_MSFRWCS_Msk   (0x3UL << ETH_MACDBGR_MSFRWCS_Pos)
     
    #define ETH_MACDBGR_MSFRWCS   ETH_MACDBGR_MSFRWCS_Msk /* MAC small FIFO read / write controllers status mask */
     
    #define ETH_MACDBGR_MSFRWCS_1   (0x2UL << ETH_MACDBGR_MSFRWCS_Pos)
     
    #define ETH_MACDBGR_MSFRWCS_0   (0x1UL << ETH_MACDBGR_MSFRWCS_Pos)
     
    #define ETH_MACDBGR_MMRPEA_Pos   (0U)
     
    #define ETH_MACDBGR_MMRPEA_Msk   (0x1UL << ETH_MACDBGR_MMRPEA_Pos)
     
    #define ETH_MACDBGR_MMRPEA   ETH_MACDBGR_MMRPEA_Msk /* MAC MII receive protocol engine active */
     
    #define ETH_MACSR_TSTS_Pos   (9U)
     
    #define ETH_MACSR_TSTS_Msk   (0x1UL << ETH_MACSR_TSTS_Pos)
     
    #define ETH_MACSR_TSTS   ETH_MACSR_TSTS_Msk /* Time stamp trigger status */
     
    #define ETH_MACSR_MMCTS_Pos   (6U)
     
    #define ETH_MACSR_MMCTS_Msk   (0x1UL << ETH_MACSR_MMCTS_Pos)
     
    #define ETH_MACSR_MMCTS   ETH_MACSR_MMCTS_Msk /* MMC transmit status */
     
    #define ETH_MACSR_MMMCRS_Pos   (5U)
     
    #define ETH_MACSR_MMMCRS_Msk   (0x1UL << ETH_MACSR_MMMCRS_Pos)
     
    #define ETH_MACSR_MMMCRS   ETH_MACSR_MMMCRS_Msk /* MMC receive status */
     
    #define ETH_MACSR_MMCS_Pos   (4U)
     
    #define ETH_MACSR_MMCS_Msk   (0x1UL << ETH_MACSR_MMCS_Pos)
     
    #define ETH_MACSR_MMCS   ETH_MACSR_MMCS_Msk /* MMC status */
     
    #define ETH_MACSR_PMTS_Pos   (3U)
     
    #define ETH_MACSR_PMTS_Msk   (0x1UL << ETH_MACSR_PMTS_Pos)
     
    #define ETH_MACSR_PMTS   ETH_MACSR_PMTS_Msk /* PMT status */
     
    #define ETH_MACIMR_TSTIM_Pos   (9U)
     
    #define ETH_MACIMR_TSTIM_Msk   (0x1UL << ETH_MACIMR_TSTIM_Pos)
     
    #define ETH_MACIMR_TSTIM   ETH_MACIMR_TSTIM_Msk /* Time stamp trigger interrupt mask */
     
    #define ETH_MACIMR_PMTIM_Pos   (3U)
     
    #define ETH_MACIMR_PMTIM_Msk   (0x1UL << ETH_MACIMR_PMTIM_Pos)
     
    #define ETH_MACIMR_PMTIM   ETH_MACIMR_PMTIM_Msk /* PMT interrupt mask */
     
    #define ETH_MACA0HR_MACA0H_Pos   (0U)
     
    #define ETH_MACA0HR_MACA0H_Msk   (0xFFFFUL << ETH_MACA0HR_MACA0H_Pos)
     
    #define ETH_MACA0HR_MACA0H   ETH_MACA0HR_MACA0H_Msk /* MAC address0 high */
     
    #define ETH_MACA0LR_MACA0L_Pos   (0U)
     
    #define ETH_MACA0LR_MACA0L_Msk   (0xFFFFFFFFUL << ETH_MACA0LR_MACA0L_Pos)
     
    #define ETH_MACA0LR_MACA0L   ETH_MACA0LR_MACA0L_Msk /* MAC address0 low */
     
    #define ETH_MACA1HR_AE_Pos   (31U)
     
    #define ETH_MACA1HR_AE_Msk   (0x1UL << ETH_MACA1HR_AE_Pos)
     
    #define ETH_MACA1HR_AE   ETH_MACA1HR_AE_Msk /* Address enable */
     
    #define ETH_MACA1HR_SA_Pos   (30U)
     
    #define ETH_MACA1HR_SA_Msk   (0x1UL << ETH_MACA1HR_SA_Pos)
     
    #define ETH_MACA1HR_SA   ETH_MACA1HR_SA_Msk /* Source address */
     
    #define ETH_MACA1HR_MBC_Pos   (24U)
     
    #define ETH_MACA1HR_MBC_Msk   (0x3FUL << ETH_MACA1HR_MBC_Pos)
     
    #define ETH_MACA1HR_MBC   ETH_MACA1HR_MBC_Msk /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
     
    #define ETH_MACA1HR_MBC_HBits15_8   0x20000000U /* Mask MAC Address high reg bits [15:8] */
     
    #define ETH_MACA1HR_MBC_HBits7_0   0x10000000U /* Mask MAC Address high reg bits [7:0] */
     
    #define ETH_MACA1HR_MBC_LBits31_24   0x08000000U /* Mask MAC Address low reg bits [31:24] */
     
    #define ETH_MACA1HR_MBC_LBits23_16   0x04000000U /* Mask MAC Address low reg bits [23:16] */
     
    #define ETH_MACA1HR_MBC_LBits15_8   0x02000000U /* Mask MAC Address low reg bits [15:8] */
     
    #define ETH_MACA1HR_MBC_LBits7_0   0x01000000U /* Mask MAC Address low reg bits [7:0] */
     
    #define ETH_MACA1HR_MACA1H_Pos   (0U)
     
    #define ETH_MACA1HR_MACA1H_Msk   (0xFFFFUL << ETH_MACA1HR_MACA1H_Pos)
     
    #define ETH_MACA1HR_MACA1H   ETH_MACA1HR_MACA1H_Msk /* MAC address1 high */
     
    #define ETH_MACA1LR_MACA1L_Pos   (0U)
     
    #define ETH_MACA1LR_MACA1L_Msk   (0xFFFFFFFFUL << ETH_MACA1LR_MACA1L_Pos)
     
    #define ETH_MACA1LR_MACA1L   ETH_MACA1LR_MACA1L_Msk /* MAC address1 low */
     
    #define ETH_MACA2HR_AE_Pos   (31U)
     
    #define ETH_MACA2HR_AE_Msk   (0x1UL << ETH_MACA2HR_AE_Pos)
     
    #define ETH_MACA2HR_AE   ETH_MACA2HR_AE_Msk /* Address enable */
     
    #define ETH_MACA2HR_SA_Pos   (30U)
     
    #define ETH_MACA2HR_SA_Msk   (0x1UL << ETH_MACA2HR_SA_Pos)
     
    #define ETH_MACA2HR_SA   ETH_MACA2HR_SA_Msk /* Source address */
     
    #define ETH_MACA2HR_MBC_Pos   (24U)
     
    #define ETH_MACA2HR_MBC_Msk   (0x3FUL << ETH_MACA2HR_MBC_Pos)
     
    #define ETH_MACA2HR_MBC   ETH_MACA2HR_MBC_Msk /* Mask byte control */
     
    #define ETH_MACA2HR_MBC_HBits15_8   0x20000000U /* Mask MAC Address high reg bits [15:8] */
     
    #define ETH_MACA2HR_MBC_HBits7_0   0x10000000U /* Mask MAC Address high reg bits [7:0] */
     
    #define ETH_MACA2HR_MBC_LBits31_24   0x08000000U /* Mask MAC Address low reg bits [31:24] */
     
    #define ETH_MACA2HR_MBC_LBits23_16   0x04000000U /* Mask MAC Address low reg bits [23:16] */
     
    #define ETH_MACA2HR_MBC_LBits15_8   0x02000000U /* Mask MAC Address low reg bits [15:8] */
     
    #define ETH_MACA2HR_MBC_LBits7_0   0x01000000U /* Mask MAC Address low reg bits [70] */
     
    #define ETH_MACA2HR_MACA2H_Pos   (0U)
     
    #define ETH_MACA2HR_MACA2H_Msk   (0xFFFFUL << ETH_MACA2HR_MACA2H_Pos)
     
    #define ETH_MACA2HR_MACA2H   ETH_MACA2HR_MACA2H_Msk /* MAC address1 high */
     
    #define ETH_MACA2LR_MACA2L_Pos   (0U)
     
    #define ETH_MACA2LR_MACA2L_Msk   (0xFFFFFFFFUL << ETH_MACA2LR_MACA2L_Pos)
     
    #define ETH_MACA2LR_MACA2L   ETH_MACA2LR_MACA2L_Msk /* MAC address2 low */
     
    #define ETH_MACA3HR_AE_Pos   (31U)
     
    #define ETH_MACA3HR_AE_Msk   (0x1UL << ETH_MACA3HR_AE_Pos)
     
    #define ETH_MACA3HR_AE   ETH_MACA3HR_AE_Msk /* Address enable */
     
    #define ETH_MACA3HR_SA_Pos   (30U)
     
    #define ETH_MACA3HR_SA_Msk   (0x1UL << ETH_MACA3HR_SA_Pos)
     
    #define ETH_MACA3HR_SA   ETH_MACA3HR_SA_Msk /* Source address */
     
    #define ETH_MACA3HR_MBC_Pos   (24U)
     
    #define ETH_MACA3HR_MBC_Msk   (0x3FUL << ETH_MACA3HR_MBC_Pos)
     
    #define ETH_MACA3HR_MBC   ETH_MACA3HR_MBC_Msk /* Mask byte control */
     
    #define ETH_MACA3HR_MBC_HBits15_8   0x20000000U /* Mask MAC Address high reg bits [15:8] */
     
    #define ETH_MACA3HR_MBC_HBits7_0   0x10000000U /* Mask MAC Address high reg bits [7:0] */
     
    #define ETH_MACA3HR_MBC_LBits31_24   0x08000000U /* Mask MAC Address low reg bits [31:24] */
     
    #define ETH_MACA3HR_MBC_LBits23_16   0x04000000U /* Mask MAC Address low reg bits [23:16] */
     
    #define ETH_MACA3HR_MBC_LBits15_8   0x02000000U /* Mask MAC Address low reg bits [15:8] */
     
    #define ETH_MACA3HR_MBC_LBits7_0   0x01000000U /* Mask MAC Address low reg bits [70] */
     
    #define ETH_MACA3HR_MACA3H_Pos   (0U)
     
    #define ETH_MACA3HR_MACA3H_Msk   (0xFFFFUL << ETH_MACA3HR_MACA3H_Pos)
     
    #define ETH_MACA3HR_MACA3H   ETH_MACA3HR_MACA3H_Msk /* MAC address3 high */
     
    #define ETH_MACA3LR_MACA3L_Pos   (0U)
     
    #define ETH_MACA3LR_MACA3L_Msk   (0xFFFFFFFFUL << ETH_MACA3LR_MACA3L_Pos)
     
    #define ETH_MACA3LR_MACA3L   ETH_MACA3LR_MACA3L_Msk /* MAC address3 low */
     
    #define ETH_MMCCR_MCFHP_Pos   (5U)
     
    #define ETH_MMCCR_MCFHP_Msk   (0x1UL << ETH_MMCCR_MCFHP_Pos)
     
    #define ETH_MMCCR_MCFHP   ETH_MMCCR_MCFHP_Msk /* MMC counter Full-Half preset */
     
    #define ETH_MMCCR_MCP_Pos   (4U)
     
    #define ETH_MMCCR_MCP_Msk   (0x1UL << ETH_MMCCR_MCP_Pos)
     
    #define ETH_MMCCR_MCP   ETH_MMCCR_MCP_Msk /* MMC counter preset */
     
    #define ETH_MMCCR_MCF_Pos   (3U)
     
    #define ETH_MMCCR_MCF_Msk   (0x1UL << ETH_MMCCR_MCF_Pos)
     
    #define ETH_MMCCR_MCF   ETH_MMCCR_MCF_Msk /* MMC Counter Freeze */
     
    #define ETH_MMCCR_ROR_Pos   (2U)
     
    #define ETH_MMCCR_ROR_Msk   (0x1UL << ETH_MMCCR_ROR_Pos)
     
    #define ETH_MMCCR_ROR   ETH_MMCCR_ROR_Msk /* Reset on Read */
     
    #define ETH_MMCCR_CSR_Pos   (1U)
     
    #define ETH_MMCCR_CSR_Msk   (0x1UL << ETH_MMCCR_CSR_Pos)
     
    #define ETH_MMCCR_CSR   ETH_MMCCR_CSR_Msk /* Counter Stop Rollover */
     
    #define ETH_MMCCR_CR_Pos   (0U)
     
    #define ETH_MMCCR_CR_Msk   (0x1UL << ETH_MMCCR_CR_Pos)
     
    #define ETH_MMCCR_CR   ETH_MMCCR_CR_Msk /* Counters Reset */
     
    #define ETH_MMCRIR_RGUFS_Pos   (17U)
     
    #define ETH_MMCRIR_RGUFS_Msk   (0x1UL << ETH_MMCRIR_RGUFS_Pos)
     
    #define ETH_MMCRIR_RGUFS   ETH_MMCRIR_RGUFS_Msk /* Set when Rx good unicast frames counter reaches half the maximum value */
     
    #define ETH_MMCRIR_RFAES_Pos   (6U)
     
    #define ETH_MMCRIR_RFAES_Msk   (0x1UL << ETH_MMCRIR_RFAES_Pos)
     
    #define ETH_MMCRIR_RFAES   ETH_MMCRIR_RFAES_Msk /* Set when Rx alignment error counter reaches half the maximum value */
     
    #define ETH_MMCRIR_RFCES_Pos   (5U)
     
    #define ETH_MMCRIR_RFCES_Msk   (0x1UL << ETH_MMCRIR_RFCES_Pos)
     
    #define ETH_MMCRIR_RFCES   ETH_MMCRIR_RFCES_Msk /* Set when Rx crc error counter reaches half the maximum value */
     
    #define ETH_MMCTIR_TGFS_Pos   (21U)
     
    #define ETH_MMCTIR_TGFS_Msk   (0x1UL << ETH_MMCTIR_TGFS_Pos)
     
    #define ETH_MMCTIR_TGFS   ETH_MMCTIR_TGFS_Msk /* Set when Tx good frame count counter reaches half the maximum value */
     
    #define ETH_MMCTIR_TGFMSCS_Pos   (15U)
     
    #define ETH_MMCTIR_TGFMSCS_Msk   (0x1UL << ETH_MMCTIR_TGFMSCS_Pos)
     
    #define ETH_MMCTIR_TGFMSCS   ETH_MMCTIR_TGFMSCS_Msk /* Set when Tx good multi col counter reaches half the maximum value */
     
    #define ETH_MMCTIR_TGFSCS_Pos   (14U)
     
    #define ETH_MMCTIR_TGFSCS_Msk   (0x1UL << ETH_MMCTIR_TGFSCS_Pos)
     
    #define ETH_MMCTIR_TGFSCS   ETH_MMCTIR_TGFSCS_Msk /* Set when Tx good single col counter reaches half the maximum value */
     
    #define ETH_MMCRIMR_RGUFM_Pos   (17U)
     
    #define ETH_MMCRIMR_RGUFM_Msk   (0x1UL << ETH_MMCRIMR_RGUFM_Pos)
     
    #define ETH_MMCRIMR_RGUFM   ETH_MMCRIMR_RGUFM_Msk /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */
     
    #define ETH_MMCRIMR_RFAEM_Pos   (6U)
     
    #define ETH_MMCRIMR_RFAEM_Msk   (0x1UL << ETH_MMCRIMR_RFAEM_Pos)
     
    #define ETH_MMCRIMR_RFAEM   ETH_MMCRIMR_RFAEM_Msk /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */
     
    #define ETH_MMCRIMR_RFCEM_Pos   (5U)
     
    #define ETH_MMCRIMR_RFCEM_Msk   (0x1UL << ETH_MMCRIMR_RFCEM_Pos)
     
    #define ETH_MMCRIMR_RFCEM   ETH_MMCRIMR_RFCEM_Msk /* Mask the interrupt when Rx crc error counter reaches half the maximum value */
     
    #define ETH_MMCTIMR_TGFM_Pos   (21U)
     
    #define ETH_MMCTIMR_TGFM_Msk   (0x1UL << ETH_MMCTIMR_TGFM_Pos)
     
    #define ETH_MMCTIMR_TGFM   ETH_MMCTIMR_TGFM_Msk /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */
     
    #define ETH_MMCTIMR_TGFMSCM_Pos   (15U)
     
    #define ETH_MMCTIMR_TGFMSCM_Msk   (0x1UL << ETH_MMCTIMR_TGFMSCM_Pos)
     
    #define ETH_MMCTIMR_TGFMSCM   ETH_MMCTIMR_TGFMSCM_Msk /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */
     
    #define ETH_MMCTIMR_TGFSCM_Pos   (14U)
     
    #define ETH_MMCTIMR_TGFSCM_Msk   (0x1UL << ETH_MMCTIMR_TGFSCM_Pos)
     
    #define ETH_MMCTIMR_TGFSCM   ETH_MMCTIMR_TGFSCM_Msk /* Mask the interrupt when Tx good single col counter reaches half the maximum value */
     
    #define ETH_MMCTGFSCCR_TGFSCC_Pos   (0U)
     
    #define ETH_MMCTGFSCCR_TGFSCC_Msk   (0xFFFFFFFFUL << ETH_MMCTGFSCCR_TGFSCC_Pos)
     
    #define ETH_MMCTGFSCCR_TGFSCC   ETH_MMCTGFSCCR_TGFSCC_Msk /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */
     
    #define ETH_MMCTGFMSCCR_TGFMSCC_Pos   (0U)
     
    #define ETH_MMCTGFMSCCR_TGFMSCC_Msk   (0xFFFFFFFFUL << ETH_MMCTGFMSCCR_TGFMSCC_Pos)
     
    #define ETH_MMCTGFMSCCR_TGFMSCC   ETH_MMCTGFMSCCR_TGFMSCC_Msk /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */
     
    #define ETH_MMCTGFCR_TGFC_Pos   (0U)
     
    #define ETH_MMCTGFCR_TGFC_Msk   (0xFFFFFFFFUL << ETH_MMCTGFCR_TGFC_Pos)
     
    #define ETH_MMCTGFCR_TGFC   ETH_MMCTGFCR_TGFC_Msk /* Number of good frames transmitted. */
     
    #define ETH_MMCRFCECR_RFCEC_Pos   (0U)
     
    #define ETH_MMCRFCECR_RFCEC_Msk   (0xFFFFFFFFUL << ETH_MMCRFCECR_RFCEC_Pos)
     
    #define ETH_MMCRFCECR_RFCEC   ETH_MMCRFCECR_RFCEC_Msk /* Number of frames received with CRC error. */
     
    #define ETH_MMCRFAECR_RFAEC_Pos   (0U)
     
    #define ETH_MMCRFAECR_RFAEC_Msk   (0xFFFFFFFFUL << ETH_MMCRFAECR_RFAEC_Pos)
     
    #define ETH_MMCRFAECR_RFAEC   ETH_MMCRFAECR_RFAEC_Msk /* Number of frames received with alignment (dribble) error */
     
    #define ETH_MMCRGUFCR_RGUFC_Pos   (0U)
     
    #define ETH_MMCRGUFCR_RGUFC_Msk   (0xFFFFFFFFUL << ETH_MMCRGUFCR_RGUFC_Pos)
     
    #define ETH_MMCRGUFCR_RGUFC   ETH_MMCRGUFCR_RGUFC_Msk /* Number of good unicast frames received. */
     
    #define ETH_PTPTSCR_TSPFFMAE_Pos   (18U)
     
    #define ETH_PTPTSCR_TSPFFMAE_Msk   (0x1UL << ETH_PTPTSCR_TSPFFMAE_Pos)
     
    #define ETH_PTPTSCR_TSPFFMAE   ETH_PTPTSCR_TSPFFMAE_Msk /* Time stamp PTP frame filtering MAC address enable */
     
    #define ETH_PTPTSCR_TSCNT_Pos   (16U)
     
    #define ETH_PTPTSCR_TSCNT_Msk   (0x3UL << ETH_PTPTSCR_TSCNT_Pos)
     
    #define ETH_PTPTSCR_TSCNT   ETH_PTPTSCR_TSCNT_Msk /* Time stamp clock node type */
     
    #define ETH_PTPTSCR_TSSMRME_Pos   (15U)
     
    #define ETH_PTPTSCR_TSSMRME_Msk   (0x1UL << ETH_PTPTSCR_TSSMRME_Pos)
     
    #define ETH_PTPTSCR_TSSMRME   ETH_PTPTSCR_TSSMRME_Msk /* Time stamp snapshot for message relevant to master enable */
     
    #define ETH_PTPTSCR_TSSEME_Pos   (14U)
     
    #define ETH_PTPTSCR_TSSEME_Msk   (0x1UL << ETH_PTPTSCR_TSSEME_Pos)
     
    #define ETH_PTPTSCR_TSSEME   ETH_PTPTSCR_TSSEME_Msk /* Time stamp snapshot for event message enable */
     
    #define ETH_PTPTSCR_TSSIPV4FE_Pos   (13U)
     
    #define ETH_PTPTSCR_TSSIPV4FE_Msk   (0x1UL << ETH_PTPTSCR_TSSIPV4FE_Pos)
     
    #define ETH_PTPTSCR_TSSIPV4FE   ETH_PTPTSCR_TSSIPV4FE_Msk /* Time stamp snapshot for IPv4 frames enable */
     
    #define ETH_PTPTSCR_TSSIPV6FE_Pos   (12U)
     
    #define ETH_PTPTSCR_TSSIPV6FE_Msk   (0x1UL << ETH_PTPTSCR_TSSIPV6FE_Pos)
     
    #define ETH_PTPTSCR_TSSIPV6FE   ETH_PTPTSCR_TSSIPV6FE_Msk /* Time stamp snapshot for IPv6 frames enable */
     
    #define ETH_PTPTSCR_TSSPTPOEFE_Pos   (11U)
     
    #define ETH_PTPTSCR_TSSPTPOEFE_Msk   (0x1UL << ETH_PTPTSCR_TSSPTPOEFE_Pos)
     
    #define ETH_PTPTSCR_TSSPTPOEFE   ETH_PTPTSCR_TSSPTPOEFE_Msk /* Time stamp snapshot for PTP over ethernet frames enable */
     
    #define ETH_PTPTSCR_TSPTPPSV2E_Pos   (10U)
     
    #define ETH_PTPTSCR_TSPTPPSV2E_Msk   (0x1UL << ETH_PTPTSCR_TSPTPPSV2E_Pos)
     
    #define ETH_PTPTSCR_TSPTPPSV2E   ETH_PTPTSCR_TSPTPPSV2E_Msk /* Time stamp PTP packet snooping for version2 format enable */
     
    #define ETH_PTPTSCR_TSSSR_Pos   (9U)
     
    #define ETH_PTPTSCR_TSSSR_Msk   (0x1UL << ETH_PTPTSCR_TSSSR_Pos)
     
    #define ETH_PTPTSCR_TSSSR   ETH_PTPTSCR_TSSSR_Msk /* Time stamp Sub-seconds rollover */
     
    #define ETH_PTPTSCR_TSSARFE_Pos   (8U)
     
    #define ETH_PTPTSCR_TSSARFE_Msk   (0x1UL << ETH_PTPTSCR_TSSARFE_Pos)
     
    #define ETH_PTPTSCR_TSSARFE   ETH_PTPTSCR_TSSARFE_Msk /* Time stamp snapshot for all received frames enable */
     
    #define ETH_PTPTSCR_TSARU_Pos   (5U)
     
    #define ETH_PTPTSCR_TSARU_Msk   (0x1UL << ETH_PTPTSCR_TSARU_Pos)
     
    #define ETH_PTPTSCR_TSARU   ETH_PTPTSCR_TSARU_Msk /* Addend register update */
     
    #define ETH_PTPTSCR_TSITE_Pos   (4U)
     
    #define ETH_PTPTSCR_TSITE_Msk   (0x1UL << ETH_PTPTSCR_TSITE_Pos)
     
    #define ETH_PTPTSCR_TSITE   ETH_PTPTSCR_TSITE_Msk /* Time stamp interrupt trigger enable */
     
    #define ETH_PTPTSCR_TSSTU_Pos   (3U)
     
    #define ETH_PTPTSCR_TSSTU_Msk   (0x1UL << ETH_PTPTSCR_TSSTU_Pos)
     
    #define ETH_PTPTSCR_TSSTU   ETH_PTPTSCR_TSSTU_Msk /* Time stamp update */
     
    #define ETH_PTPTSCR_TSSTI_Pos   (2U)
     
    #define ETH_PTPTSCR_TSSTI_Msk   (0x1UL << ETH_PTPTSCR_TSSTI_Pos)
     
    #define ETH_PTPTSCR_TSSTI   ETH_PTPTSCR_TSSTI_Msk /* Time stamp initialize */
     
    #define ETH_PTPTSCR_TSFCU_Pos   (1U)
     
    #define ETH_PTPTSCR_TSFCU_Msk   (0x1UL << ETH_PTPTSCR_TSFCU_Pos)
     
    #define ETH_PTPTSCR_TSFCU   ETH_PTPTSCR_TSFCU_Msk /* Time stamp fine or coarse update */
     
    #define ETH_PTPTSCR_TSE_Pos   (0U)
     
    #define ETH_PTPTSCR_TSE_Msk   (0x1UL << ETH_PTPTSCR_TSE_Pos)
     
    #define ETH_PTPTSCR_TSE   ETH_PTPTSCR_TSE_Msk /* Time stamp enable */
     
    #define ETH_PTPSSIR_STSSI_Pos   (0U)
     
    #define ETH_PTPSSIR_STSSI_Msk   (0xFFUL << ETH_PTPSSIR_STSSI_Pos)
     
    #define ETH_PTPSSIR_STSSI   ETH_PTPSSIR_STSSI_Msk /* System time Sub-second increment value */
     
    #define ETH_PTPTSHR_STS_Pos   (0U)
     
    #define ETH_PTPTSHR_STS_Msk   (0xFFFFFFFFUL << ETH_PTPTSHR_STS_Pos)
     
    #define ETH_PTPTSHR_STS   ETH_PTPTSHR_STS_Msk /* System Time second */
     
    #define ETH_PTPTSLR_STPNS_Pos   (31U)
     
    #define ETH_PTPTSLR_STPNS_Msk   (0x1UL << ETH_PTPTSLR_STPNS_Pos)
     
    #define ETH_PTPTSLR_STPNS   ETH_PTPTSLR_STPNS_Msk /* System Time Positive or negative time */
     
    #define ETH_PTPTSLR_STSS_Pos   (0U)
     
    #define ETH_PTPTSLR_STSS_Msk   (0x7FFFFFFFUL << ETH_PTPTSLR_STSS_Pos)
     
    #define ETH_PTPTSLR_STSS   ETH_PTPTSLR_STSS_Msk /* System Time sub-seconds */
     
    #define ETH_PTPTSHUR_TSUS_Pos   (0U)
     
    #define ETH_PTPTSHUR_TSUS_Msk   (0xFFFFFFFFUL << ETH_PTPTSHUR_TSUS_Pos)
     
    #define ETH_PTPTSHUR_TSUS   ETH_PTPTSHUR_TSUS_Msk /* Time stamp update seconds */
     
    #define ETH_PTPTSLUR_TSUPNS_Pos   (31U)
     
    #define ETH_PTPTSLUR_TSUPNS_Msk   (0x1UL << ETH_PTPTSLUR_TSUPNS_Pos)
     
    #define ETH_PTPTSLUR_TSUPNS   ETH_PTPTSLUR_TSUPNS_Msk /* Time stamp update Positive or negative time */
     
    #define ETH_PTPTSLUR_TSUSS_Pos   (0U)
     
    #define ETH_PTPTSLUR_TSUSS_Msk   (0x7FFFFFFFUL << ETH_PTPTSLUR_TSUSS_Pos)
     
    #define ETH_PTPTSLUR_TSUSS   ETH_PTPTSLUR_TSUSS_Msk /* Time stamp update sub-seconds */
     
    #define ETH_PTPTSAR_TSA_Pos   (0U)
     
    #define ETH_PTPTSAR_TSA_Msk   (0xFFFFFFFFUL << ETH_PTPTSAR_TSA_Pos)
     
    #define ETH_PTPTSAR_TSA   ETH_PTPTSAR_TSA_Msk /* Time stamp addend */
     
    #define ETH_PTPTTHR_TTSH_Pos   (0U)
     
    #define ETH_PTPTTHR_TTSH_Msk   (0xFFFFFFFFUL << ETH_PTPTTHR_TTSH_Pos)
     
    #define ETH_PTPTTHR_TTSH   ETH_PTPTTHR_TTSH_Msk /* Target time stamp high */
     
    #define ETH_PTPTTLR_TTSL_Pos   (0U)
     
    #define ETH_PTPTTLR_TTSL_Msk   (0xFFFFFFFFUL << ETH_PTPTTLR_TTSL_Pos)
     
    #define ETH_PTPTTLR_TTSL   ETH_PTPTTLR_TTSL_Msk /* Target time stamp low */
     
    #define ETH_PTPTSSR_TSTTR_Pos   (5U)
     
    #define ETH_PTPTSSR_TSTTR_Msk   (0x1UL << ETH_PTPTSSR_TSTTR_Pos)
     
    #define ETH_PTPTSSR_TSTTR   ETH_PTPTSSR_TSTTR_Msk /* Time stamp target time reached */
     
    #define ETH_PTPTSSR_TSSO_Pos   (4U)
     
    #define ETH_PTPTSSR_TSSO_Msk   (0x1UL << ETH_PTPTSSR_TSSO_Pos)
     
    #define ETH_PTPTSSR_TSSO   ETH_PTPTSSR_TSSO_Msk /* Time stamp seconds overflow */
     
    #define ETH_DMABMR_MB_Pos   (26U)
     
    #define ETH_DMABMR_MB_Msk   (0x1UL << ETH_DMABMR_MB_Pos)
     
    #define ETH_DMABMR_MB   ETH_DMABMR_MB_Msk /* Mixed Burst */
     
    #define ETH_DMABMR_AAB_Pos   (25U)
     
    #define ETH_DMABMR_AAB_Msk   (0x1UL << ETH_DMABMR_AAB_Pos)
     
    #define ETH_DMABMR_AAB   ETH_DMABMR_AAB_Msk /* Address-Aligned beats */
     
    #define ETH_DMABMR_FPM_Pos   (24U)
     
    #define ETH_DMABMR_FPM_Msk   (0x1UL << ETH_DMABMR_FPM_Pos)
     
    #define ETH_DMABMR_FPM   ETH_DMABMR_FPM_Msk /* 4xPBL mode */
     
    #define ETH_DMABMR_USP_Pos   (23U)
     
    #define ETH_DMABMR_USP_Msk   (0x1UL << ETH_DMABMR_USP_Pos)
     
    #define ETH_DMABMR_USP   ETH_DMABMR_USP_Msk /* Use separate PBL */
     
    #define ETH_DMABMR_RDP_Pos   (17U)
     
    #define ETH_DMABMR_RDP_Msk   (0x3FUL << ETH_DMABMR_RDP_Pos)
     
    #define ETH_DMABMR_RDP   ETH_DMABMR_RDP_Msk /* RxDMA PBL */
     
    #define ETH_DMABMR_RDP_1Beat   0x00020000U /* maximum number of beats to be transferred in one RxDMA transaction is 1 */
     
    #define ETH_DMABMR_RDP_2Beat   0x00040000U /* maximum number of beats to be transferred in one RxDMA transaction is 2 */
     
    #define ETH_DMABMR_RDP_4Beat   0x00080000U /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
     
    #define ETH_DMABMR_RDP_8Beat   0x00100000U /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
     
    #define ETH_DMABMR_RDP_16Beat   0x00200000U /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
     
    #define ETH_DMABMR_RDP_32Beat   0x00400000U /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
     
    #define ETH_DMABMR_RDP_4xPBL_4Beat   0x01020000U /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
     
    #define ETH_DMABMR_RDP_4xPBL_8Beat   0x01040000U /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
     
    #define ETH_DMABMR_RDP_4xPBL_16Beat   0x01080000U /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
     
    #define ETH_DMABMR_RDP_4xPBL_32Beat   0x01100000U /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
     
    #define ETH_DMABMR_RDP_4xPBL_64Beat   0x01200000U /* maximum number of beats to be transferred in one RxDMA transaction is 64 */
     
    #define ETH_DMABMR_RDP_4xPBL_128Beat   0x01400000U /* maximum number of beats to be transferred in one RxDMA transaction is 128 */
     
    #define ETH_DMABMR_FB_Pos   (16U)
     
    #define ETH_DMABMR_FB_Msk   (0x1UL << ETH_DMABMR_FB_Pos)
     
    #define ETH_DMABMR_FB   ETH_DMABMR_FB_Msk /* Fixed Burst */
     
    #define ETH_DMABMR_RTPR_Pos   (14U)
     
    #define ETH_DMABMR_RTPR_Msk   (0x3UL << ETH_DMABMR_RTPR_Pos)
     
    #define ETH_DMABMR_RTPR   ETH_DMABMR_RTPR_Msk /* Rx Tx priority ratio */
     
    #define ETH_DMABMR_RTPR_1_1   0x00000000U /* Rx Tx priority ratio */
     
    #define ETH_DMABMR_RTPR_2_1   0x00004000U /* Rx Tx priority ratio */
     
    #define ETH_DMABMR_RTPR_3_1   0x00008000U /* Rx Tx priority ratio */
     
    #define ETH_DMABMR_RTPR_4_1   0x0000C000U /* Rx Tx priority ratio */
     
    #define ETH_DMABMR_PBL_Pos   (8U)
     
    #define ETH_DMABMR_PBL_Msk   (0x3FUL << ETH_DMABMR_PBL_Pos)
     
    #define ETH_DMABMR_PBL   ETH_DMABMR_PBL_Msk /* Programmable burst length */
     
    #define ETH_DMABMR_PBL_1Beat   0x00000100U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
     
    #define ETH_DMABMR_PBL_2Beat   0x00000200U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
     
    #define ETH_DMABMR_PBL_4Beat   0x00000400U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
     
    #define ETH_DMABMR_PBL_8Beat   0x00000800U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
     
    #define ETH_DMABMR_PBL_16Beat   0x00001000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
     
    #define ETH_DMABMR_PBL_32Beat   0x00002000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
     
    #define ETH_DMABMR_PBL_4xPBL_4Beat   0x01000100U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
     
    #define ETH_DMABMR_PBL_4xPBL_8Beat   0x01000200U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
     
    #define ETH_DMABMR_PBL_4xPBL_16Beat   0x01000400U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
     
    #define ETH_DMABMR_PBL_4xPBL_32Beat   0x01000800U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
     
    #define ETH_DMABMR_PBL_4xPBL_64Beat   0x01001000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
     
    #define ETH_DMABMR_PBL_4xPBL_128Beat   0x01002000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
     
    #define ETH_DMABMR_EDE_Pos   (7U)
     
    #define ETH_DMABMR_EDE_Msk   (0x1UL << ETH_DMABMR_EDE_Pos)
     
    #define ETH_DMABMR_EDE   ETH_DMABMR_EDE_Msk /* Enhanced Descriptor Enable */
     
    #define ETH_DMABMR_DSL_Pos   (2U)
     
    #define ETH_DMABMR_DSL_Msk   (0x1FUL << ETH_DMABMR_DSL_Pos)
     
    #define ETH_DMABMR_DSL   ETH_DMABMR_DSL_Msk /* Descriptor Skip Length */
     
    #define ETH_DMABMR_DA_Pos   (1U)
     
    #define ETH_DMABMR_DA_Msk   (0x1UL << ETH_DMABMR_DA_Pos)
     
    #define ETH_DMABMR_DA   ETH_DMABMR_DA_Msk /* DMA arbitration scheme */
     
    #define ETH_DMABMR_SR_Pos   (0U)
     
    #define ETH_DMABMR_SR_Msk   (0x1UL << ETH_DMABMR_SR_Pos)
     
    #define ETH_DMABMR_SR   ETH_DMABMR_SR_Msk /* Software reset */
     
    #define ETH_DMATPDR_TPD_Pos   (0U)
     
    #define ETH_DMATPDR_TPD_Msk   (0xFFFFFFFFUL << ETH_DMATPDR_TPD_Pos)
     
    #define ETH_DMATPDR_TPD   ETH_DMATPDR_TPD_Msk /* Transmit poll demand */
     
    #define ETH_DMARPDR_RPD_Pos   (0U)
     
    #define ETH_DMARPDR_RPD_Msk   (0xFFFFFFFFUL << ETH_DMARPDR_RPD_Pos)
     
    #define ETH_DMARPDR_RPD   ETH_DMARPDR_RPD_Msk /* Receive poll demand */
     
    #define ETH_DMARDLAR_SRL_Pos   (0U)
     
    #define ETH_DMARDLAR_SRL_Msk   (0xFFFFFFFFUL << ETH_DMARDLAR_SRL_Pos)
     
    #define ETH_DMARDLAR_SRL   ETH_DMARDLAR_SRL_Msk /* Start of receive list */
     
    #define ETH_DMATDLAR_STL_Pos   (0U)
     
    #define ETH_DMATDLAR_STL_Msk   (0xFFFFFFFFUL << ETH_DMATDLAR_STL_Pos)
     
    #define ETH_DMATDLAR_STL   ETH_DMATDLAR_STL_Msk /* Start of transmit list */
     
    #define ETH_DMASR_TSTS_Pos   (29U)
     
    #define ETH_DMASR_TSTS_Msk   (0x1UL << ETH_DMASR_TSTS_Pos)
     
    #define ETH_DMASR_TSTS   ETH_DMASR_TSTS_Msk /* Time-stamp trigger status */
     
    #define ETH_DMASR_PMTS_Pos   (28U)
     
    #define ETH_DMASR_PMTS_Msk   (0x1UL << ETH_DMASR_PMTS_Pos)
     
    #define ETH_DMASR_PMTS   ETH_DMASR_PMTS_Msk /* PMT status */
     
    #define ETH_DMASR_MMCS_Pos   (27U)
     
    #define ETH_DMASR_MMCS_Msk   (0x1UL << ETH_DMASR_MMCS_Pos)
     
    #define ETH_DMASR_MMCS   ETH_DMASR_MMCS_Msk /* MMC status */
     
    #define ETH_DMASR_EBS_Pos   (23U)
     
    #define ETH_DMASR_EBS_Msk   (0x7UL << ETH_DMASR_EBS_Pos)
     
    #define ETH_DMASR_EBS   ETH_DMASR_EBS_Msk /* Error bits status */
     
    #define ETH_DMASR_EBS_DescAccess_Pos   (25U)
     
    #define ETH_DMASR_EBS_DescAccess_Msk   (0x1UL << ETH_DMASR_EBS_DescAccess_Pos)
     
    #define ETH_DMASR_EBS_DescAccess   ETH_DMASR_EBS_DescAccess_Msk /* Error bits 0-data buffer, 1-desc. access */
     
    #define ETH_DMASR_EBS_ReadTransf_Pos   (24U)
     
    #define ETH_DMASR_EBS_ReadTransf_Msk   (0x1UL << ETH_DMASR_EBS_ReadTransf_Pos)
     
    #define ETH_DMASR_EBS_ReadTransf   ETH_DMASR_EBS_ReadTransf_Msk /* Error bits 0-write trnsf, 1-read transfr */
     
    #define ETH_DMASR_EBS_DataTransfTx_Pos   (23U)
     
    #define ETH_DMASR_EBS_DataTransfTx_Msk   (0x1UL << ETH_DMASR_EBS_DataTransfTx_Pos)
     
    #define ETH_DMASR_EBS_DataTransfTx   ETH_DMASR_EBS_DataTransfTx_Msk /* Error bits 0-Rx DMA, 1-Tx DMA */
     
    #define ETH_DMASR_TPS_Pos   (20U)
     
    #define ETH_DMASR_TPS_Msk   (0x7UL << ETH_DMASR_TPS_Pos)
     
    #define ETH_DMASR_TPS   ETH_DMASR_TPS_Msk /* Transmit process state */
     
    #define ETH_DMASR_TPS_Stopped   0x00000000U /* Stopped - Reset or Stop Tx Command issued */
     
    #define ETH_DMASR_TPS_Fetching_Pos   (20U)
     
    #define ETH_DMASR_TPS_Fetching_Msk   (0x1UL << ETH_DMASR_TPS_Fetching_Pos)
     
    #define ETH_DMASR_TPS_Fetching   ETH_DMASR_TPS_Fetching_Msk /* Running - fetching the Tx descriptor */
     
    #define ETH_DMASR_TPS_Waiting_Pos   (21U)
     
    #define ETH_DMASR_TPS_Waiting_Msk   (0x1UL << ETH_DMASR_TPS_Waiting_Pos)
     
    #define ETH_DMASR_TPS_Waiting   ETH_DMASR_TPS_Waiting_Msk /* Running - waiting for status */
     
    #define ETH_DMASR_TPS_Reading_Pos   (20U)
     
    #define ETH_DMASR_TPS_Reading_Msk   (0x3UL << ETH_DMASR_TPS_Reading_Pos)
     
    #define ETH_DMASR_TPS_Reading   ETH_DMASR_TPS_Reading_Msk /* Running - reading the data from host memory */
     
    #define ETH_DMASR_TPS_Suspended_Pos   (21U)
     
    #define ETH_DMASR_TPS_Suspended_Msk   (0x3UL << ETH_DMASR_TPS_Suspended_Pos)
     
    #define ETH_DMASR_TPS_Suspended   ETH_DMASR_TPS_Suspended_Msk /* Suspended - Tx Descriptor unavailable */
     
    #define ETH_DMASR_TPS_Closing_Pos   (20U)
     
    #define ETH_DMASR_TPS_Closing_Msk   (0x7UL << ETH_DMASR_TPS_Closing_Pos)
     
    #define ETH_DMASR_TPS_Closing   ETH_DMASR_TPS_Closing_Msk /* Running - closing Rx descriptor */
     
    #define ETH_DMASR_RPS_Pos   (17U)
     
    #define ETH_DMASR_RPS_Msk   (0x7UL << ETH_DMASR_RPS_Pos)
     
    #define ETH_DMASR_RPS   ETH_DMASR_RPS_Msk /* Receive process state */
     
    #define ETH_DMASR_RPS_Stopped   0x00000000U /* Stopped - Reset or Stop Rx Command issued */
     
    #define ETH_DMASR_RPS_Fetching_Pos   (17U)
     
    #define ETH_DMASR_RPS_Fetching_Msk   (0x1UL << ETH_DMASR_RPS_Fetching_Pos)
     
    #define ETH_DMASR_RPS_Fetching   ETH_DMASR_RPS_Fetching_Msk /* Running - fetching the Rx descriptor */
     
    #define ETH_DMASR_RPS_Waiting_Pos   (17U)
     
    #define ETH_DMASR_RPS_Waiting_Msk   (0x3UL << ETH_DMASR_RPS_Waiting_Pos)
     
    #define ETH_DMASR_RPS_Waiting   ETH_DMASR_RPS_Waiting_Msk /* Running - waiting for packet */
     
    #define ETH_DMASR_RPS_Suspended_Pos   (19U)
     
    #define ETH_DMASR_RPS_Suspended_Msk   (0x1UL << ETH_DMASR_RPS_Suspended_Pos)
     
    #define ETH_DMASR_RPS_Suspended   ETH_DMASR_RPS_Suspended_Msk /* Suspended - Rx Descriptor unavailable */
     
    #define ETH_DMASR_RPS_Closing_Pos   (17U)
     
    #define ETH_DMASR_RPS_Closing_Msk   (0x5UL << ETH_DMASR_RPS_Closing_Pos)
     
    #define ETH_DMASR_RPS_Closing   ETH_DMASR_RPS_Closing_Msk /* Running - closing descriptor */
     
    #define ETH_DMASR_RPS_Queuing_Pos   (17U)
     
    #define ETH_DMASR_RPS_Queuing_Msk   (0x7UL << ETH_DMASR_RPS_Queuing_Pos)
     
    #define ETH_DMASR_RPS_Queuing   ETH_DMASR_RPS_Queuing_Msk /* Running - queuing the receive frame into host memory */
     
    #define ETH_DMASR_NIS_Pos   (16U)
     
    #define ETH_DMASR_NIS_Msk   (0x1UL << ETH_DMASR_NIS_Pos)
     
    #define ETH_DMASR_NIS   ETH_DMASR_NIS_Msk /* Normal interrupt summary */
     
    #define ETH_DMASR_AIS_Pos   (15U)
     
    #define ETH_DMASR_AIS_Msk   (0x1UL << ETH_DMASR_AIS_Pos)
     
    #define ETH_DMASR_AIS   ETH_DMASR_AIS_Msk /* Abnormal interrupt summary */
     
    #define ETH_DMASR_ERS_Pos   (14U)
     
    #define ETH_DMASR_ERS_Msk   (0x1UL << ETH_DMASR_ERS_Pos)
     
    #define ETH_DMASR_ERS   ETH_DMASR_ERS_Msk /* Early receive status */
     
    #define ETH_DMASR_FBES_Pos   (13U)
     
    #define ETH_DMASR_FBES_Msk   (0x1UL << ETH_DMASR_FBES_Pos)
     
    #define ETH_DMASR_FBES   ETH_DMASR_FBES_Msk /* Fatal bus error status */
     
    #define ETH_DMASR_ETS_Pos   (10U)
     
    #define ETH_DMASR_ETS_Msk   (0x1UL << ETH_DMASR_ETS_Pos)
     
    #define ETH_DMASR_ETS   ETH_DMASR_ETS_Msk /* Early transmit status */
     
    #define ETH_DMASR_RWTS_Pos   (9U)
     
    #define ETH_DMASR_RWTS_Msk   (0x1UL << ETH_DMASR_RWTS_Pos)
     
    #define ETH_DMASR_RWTS   ETH_DMASR_RWTS_Msk /* Receive watchdog timeout status */
     
    #define ETH_DMASR_RPSS_Pos   (8U)
     
    #define ETH_DMASR_RPSS_Msk   (0x1UL << ETH_DMASR_RPSS_Pos)
     
    #define ETH_DMASR_RPSS   ETH_DMASR_RPSS_Msk /* Receive process stopped status */
     
    #define ETH_DMASR_RBUS_Pos   (7U)
     
    #define ETH_DMASR_RBUS_Msk   (0x1UL << ETH_DMASR_RBUS_Pos)
     
    #define ETH_DMASR_RBUS   ETH_DMASR_RBUS_Msk /* Receive buffer unavailable status */
     
    #define ETH_DMASR_RS_Pos   (6U)
     
    #define ETH_DMASR_RS_Msk   (0x1UL << ETH_DMASR_RS_Pos)
     
    #define ETH_DMASR_RS   ETH_DMASR_RS_Msk /* Receive status */
     
    #define ETH_DMASR_TUS_Pos   (5U)
     
    #define ETH_DMASR_TUS_Msk   (0x1UL << ETH_DMASR_TUS_Pos)
     
    #define ETH_DMASR_TUS   ETH_DMASR_TUS_Msk /* Transmit underflow status */
     
    #define ETH_DMASR_ROS_Pos   (4U)
     
    #define ETH_DMASR_ROS_Msk   (0x1UL << ETH_DMASR_ROS_Pos)
     
    #define ETH_DMASR_ROS   ETH_DMASR_ROS_Msk /* Receive overflow status */
     
    #define ETH_DMASR_TJTS_Pos   (3U)
     
    #define ETH_DMASR_TJTS_Msk   (0x1UL << ETH_DMASR_TJTS_Pos)
     
    #define ETH_DMASR_TJTS   ETH_DMASR_TJTS_Msk /* Transmit jabber timeout status */
     
    #define ETH_DMASR_TBUS_Pos   (2U)
     
    #define ETH_DMASR_TBUS_Msk   (0x1UL << ETH_DMASR_TBUS_Pos)
     
    #define ETH_DMASR_TBUS   ETH_DMASR_TBUS_Msk /* Transmit buffer unavailable status */
     
    #define ETH_DMASR_TPSS_Pos   (1U)
     
    #define ETH_DMASR_TPSS_Msk   (0x1UL << ETH_DMASR_TPSS_Pos)
     
    #define ETH_DMASR_TPSS   ETH_DMASR_TPSS_Msk /* Transmit process stopped status */
     
    #define ETH_DMASR_TS_Pos   (0U)
     
    #define ETH_DMASR_TS_Msk   (0x1UL << ETH_DMASR_TS_Pos)
     
    #define ETH_DMASR_TS   ETH_DMASR_TS_Msk /* Transmit status */
     
    #define ETH_DMAOMR_DTCEFD_Pos   (26U)
     
    #define ETH_DMAOMR_DTCEFD_Msk   (0x1UL << ETH_DMAOMR_DTCEFD_Pos)
     
    #define ETH_DMAOMR_DTCEFD   ETH_DMAOMR_DTCEFD_Msk /* Disable Dropping of TCP/IP checksum error frames */
     
    #define ETH_DMAOMR_RSF_Pos   (25U)
     
    #define ETH_DMAOMR_RSF_Msk   (0x1UL << ETH_DMAOMR_RSF_Pos)
     
    #define ETH_DMAOMR_RSF   ETH_DMAOMR_RSF_Msk /* Receive store and forward */
     
    #define ETH_DMAOMR_DFRF_Pos   (24U)
     
    #define ETH_DMAOMR_DFRF_Msk   (0x1UL << ETH_DMAOMR_DFRF_Pos)
     
    #define ETH_DMAOMR_DFRF   ETH_DMAOMR_DFRF_Msk /* Disable flushing of received frames */
     
    #define ETH_DMAOMR_TSF_Pos   (21U)
     
    #define ETH_DMAOMR_TSF_Msk   (0x1UL << ETH_DMAOMR_TSF_Pos)
     
    #define ETH_DMAOMR_TSF   ETH_DMAOMR_TSF_Msk /* Transmit store and forward */
     
    #define ETH_DMAOMR_FTF_Pos   (20U)
     
    #define ETH_DMAOMR_FTF_Msk   (0x1UL << ETH_DMAOMR_FTF_Pos)
     
    #define ETH_DMAOMR_FTF   ETH_DMAOMR_FTF_Msk /* Flush transmit FIFO */
     
    #define ETH_DMAOMR_TTC_Pos   (14U)
     
    #define ETH_DMAOMR_TTC_Msk   (0x7UL << ETH_DMAOMR_TTC_Pos)
     
    #define ETH_DMAOMR_TTC   ETH_DMAOMR_TTC_Msk /* Transmit threshold control */
     
    #define ETH_DMAOMR_TTC_64Bytes   0x00000000U /* threshold level of the MTL Transmit FIFO is 64 Bytes */
     
    #define ETH_DMAOMR_TTC_128Bytes   0x00004000U /* threshold level of the MTL Transmit FIFO is 128 Bytes */
     
    #define ETH_DMAOMR_TTC_192Bytes   0x00008000U /* threshold level of the MTL Transmit FIFO is 192 Bytes */
     
    #define ETH_DMAOMR_TTC_256Bytes   0x0000C000U /* threshold level of the MTL Transmit FIFO is 256 Bytes */
     
    #define ETH_DMAOMR_TTC_40Bytes   0x00010000U /* threshold level of the MTL Transmit FIFO is 40 Bytes */
     
    #define ETH_DMAOMR_TTC_32Bytes   0x00014000U /* threshold level of the MTL Transmit FIFO is 32 Bytes */
     
    #define ETH_DMAOMR_TTC_24Bytes   0x00018000U /* threshold level of the MTL Transmit FIFO is 24 Bytes */
     
    #define ETH_DMAOMR_TTC_16Bytes   0x0001C000U /* threshold level of the MTL Transmit FIFO is 16 Bytes */
     
    #define ETH_DMAOMR_ST_Pos   (13U)
     
    #define ETH_DMAOMR_ST_Msk   (0x1UL << ETH_DMAOMR_ST_Pos)
     
    #define ETH_DMAOMR_ST   ETH_DMAOMR_ST_Msk /* Start/stop transmission command */
     
    #define ETH_DMAOMR_FEF_Pos   (7U)
     
    #define ETH_DMAOMR_FEF_Msk   (0x1UL << ETH_DMAOMR_FEF_Pos)
     
    #define ETH_DMAOMR_FEF   ETH_DMAOMR_FEF_Msk /* Forward error frames */
     
    #define ETH_DMAOMR_FUGF_Pos   (6U)
     
    #define ETH_DMAOMR_FUGF_Msk   (0x1UL << ETH_DMAOMR_FUGF_Pos)
     
    #define ETH_DMAOMR_FUGF   ETH_DMAOMR_FUGF_Msk /* Forward undersized good frames */
     
    #define ETH_DMAOMR_RTC_Pos   (3U)
     
    #define ETH_DMAOMR_RTC_Msk   (0x3UL << ETH_DMAOMR_RTC_Pos)
     
    #define ETH_DMAOMR_RTC   ETH_DMAOMR_RTC_Msk /* receive threshold control */
     
    #define ETH_DMAOMR_RTC_64Bytes   0x00000000U /* threshold level of the MTL Receive FIFO is 64 Bytes */
     
    #define ETH_DMAOMR_RTC_32Bytes   0x00000008U /* threshold level of the MTL Receive FIFO is 32 Bytes */
     
    #define ETH_DMAOMR_RTC_96Bytes   0x00000010U /* threshold level of the MTL Receive FIFO is 96 Bytes */
     
    #define ETH_DMAOMR_RTC_128Bytes   0x00000018U /* threshold level of the MTL Receive FIFO is 128 Bytes */
     
    #define ETH_DMAOMR_OSF_Pos   (2U)
     
    #define ETH_DMAOMR_OSF_Msk   (0x1UL << ETH_DMAOMR_OSF_Pos)
     
    #define ETH_DMAOMR_OSF   ETH_DMAOMR_OSF_Msk /* operate on second frame */
     
    #define ETH_DMAOMR_SR_Pos   (1U)
     
    #define ETH_DMAOMR_SR_Msk   (0x1UL << ETH_DMAOMR_SR_Pos)
     
    #define ETH_DMAOMR_SR   ETH_DMAOMR_SR_Msk /* Start/stop receive */
     
    #define ETH_DMAIER_NISE_Pos   (16U)
     
    #define ETH_DMAIER_NISE_Msk   (0x1UL << ETH_DMAIER_NISE_Pos)
     
    #define ETH_DMAIER_NISE   ETH_DMAIER_NISE_Msk /* Normal interrupt summary enable */
     
    #define ETH_DMAIER_AISE_Pos   (15U)
     
    #define ETH_DMAIER_AISE_Msk   (0x1UL << ETH_DMAIER_AISE_Pos)
     
    #define ETH_DMAIER_AISE   ETH_DMAIER_AISE_Msk /* Abnormal interrupt summary enable */
     
    #define ETH_DMAIER_ERIE_Pos   (14U)
     
    #define ETH_DMAIER_ERIE_Msk   (0x1UL << ETH_DMAIER_ERIE_Pos)
     
    #define ETH_DMAIER_ERIE   ETH_DMAIER_ERIE_Msk /* Early receive interrupt enable */
     
    #define ETH_DMAIER_FBEIE_Pos   (13U)
     
    #define ETH_DMAIER_FBEIE_Msk   (0x1UL << ETH_DMAIER_FBEIE_Pos)
     
    #define ETH_DMAIER_FBEIE   ETH_DMAIER_FBEIE_Msk /* Fatal bus error interrupt enable */
     
    #define ETH_DMAIER_ETIE_Pos   (10U)
     
    #define ETH_DMAIER_ETIE_Msk   (0x1UL << ETH_DMAIER_ETIE_Pos)
     
    #define ETH_DMAIER_ETIE   ETH_DMAIER_ETIE_Msk /* Early transmit interrupt enable */
     
    #define ETH_DMAIER_RWTIE_Pos   (9U)
     
    #define ETH_DMAIER_RWTIE_Msk   (0x1UL << ETH_DMAIER_RWTIE_Pos)
     
    #define ETH_DMAIER_RWTIE   ETH_DMAIER_RWTIE_Msk /* Receive watchdog timeout interrupt enable */
     
    #define ETH_DMAIER_RPSIE_Pos   (8U)
     
    #define ETH_DMAIER_RPSIE_Msk   (0x1UL << ETH_DMAIER_RPSIE_Pos)
     
    #define ETH_DMAIER_RPSIE   ETH_DMAIER_RPSIE_Msk /* Receive process stopped interrupt enable */
     
    #define ETH_DMAIER_RBUIE_Pos   (7U)
     
    #define ETH_DMAIER_RBUIE_Msk   (0x1UL << ETH_DMAIER_RBUIE_Pos)
     
    #define ETH_DMAIER_RBUIE   ETH_DMAIER_RBUIE_Msk /* Receive buffer unavailable interrupt enable */
     
    #define ETH_DMAIER_RIE_Pos   (6U)
     
    #define ETH_DMAIER_RIE_Msk   (0x1UL << ETH_DMAIER_RIE_Pos)
     
    #define ETH_DMAIER_RIE   ETH_DMAIER_RIE_Msk /* Receive interrupt enable */
     
    #define ETH_DMAIER_TUIE_Pos   (5U)
     
    #define ETH_DMAIER_TUIE_Msk   (0x1UL << ETH_DMAIER_TUIE_Pos)
     
    #define ETH_DMAIER_TUIE   ETH_DMAIER_TUIE_Msk /* Transmit Underflow interrupt enable */
     
    #define ETH_DMAIER_ROIE_Pos   (4U)
     
    #define ETH_DMAIER_ROIE_Msk   (0x1UL << ETH_DMAIER_ROIE_Pos)
     
    #define ETH_DMAIER_ROIE   ETH_DMAIER_ROIE_Msk /* Receive Overflow interrupt enable */
     
    #define ETH_DMAIER_TJTIE_Pos   (3U)
     
    #define ETH_DMAIER_TJTIE_Msk   (0x1UL << ETH_DMAIER_TJTIE_Pos)
     
    #define ETH_DMAIER_TJTIE   ETH_DMAIER_TJTIE_Msk /* Transmit jabber timeout interrupt enable */
     
    #define ETH_DMAIER_TBUIE_Pos   (2U)
     
    #define ETH_DMAIER_TBUIE_Msk   (0x1UL << ETH_DMAIER_TBUIE_Pos)
     
    #define ETH_DMAIER_TBUIE   ETH_DMAIER_TBUIE_Msk /* Transmit buffer unavailable interrupt enable */
     
    #define ETH_DMAIER_TPSIE_Pos   (1U)
     
    #define ETH_DMAIER_TPSIE_Msk   (0x1UL << ETH_DMAIER_TPSIE_Pos)
     
    #define ETH_DMAIER_TPSIE   ETH_DMAIER_TPSIE_Msk /* Transmit process stopped interrupt enable */
     
    #define ETH_DMAIER_TIE_Pos   (0U)
     
    #define ETH_DMAIER_TIE_Msk   (0x1UL << ETH_DMAIER_TIE_Pos)
     
    #define ETH_DMAIER_TIE   ETH_DMAIER_TIE_Msk /* Transmit interrupt enable */
     
    #define ETH_DMAMFBOCR_OFOC_Pos   (28U)
     
    #define ETH_DMAMFBOCR_OFOC_Msk   (0x1UL << ETH_DMAMFBOCR_OFOC_Pos)
     
    #define ETH_DMAMFBOCR_OFOC   ETH_DMAMFBOCR_OFOC_Msk /* Overflow bit for FIFO overflow counter */
     
    #define ETH_DMAMFBOCR_MFA_Pos   (17U)
     
    #define ETH_DMAMFBOCR_MFA_Msk   (0x7FFUL << ETH_DMAMFBOCR_MFA_Pos)
     
    #define ETH_DMAMFBOCR_MFA   ETH_DMAMFBOCR_MFA_Msk /* Number of frames missed by the application */
     
    #define ETH_DMAMFBOCR_OMFC_Pos   (16U)
     
    #define ETH_DMAMFBOCR_OMFC_Msk   (0x1UL << ETH_DMAMFBOCR_OMFC_Pos)
     
    #define ETH_DMAMFBOCR_OMFC   ETH_DMAMFBOCR_OMFC_Msk /* Overflow bit for missed frame counter */
     
    #define ETH_DMAMFBOCR_MFC_Pos   (0U)
     
    #define ETH_DMAMFBOCR_MFC_Msk   (0xFFFFUL << ETH_DMAMFBOCR_MFC_Pos)
     
    #define ETH_DMAMFBOCR_MFC   ETH_DMAMFBOCR_MFC_Msk /* Number of frames missed by the controller */
     
    #define ETH_DMACHTDR_HTDAP_Pos   (0U)
     
    #define ETH_DMACHTDR_HTDAP_Msk   (0xFFFFFFFFUL << ETH_DMACHTDR_HTDAP_Pos)
     
    #define ETH_DMACHTDR_HTDAP   ETH_DMACHTDR_HTDAP_Msk /* Host transmit descriptor address pointer */
     
    #define ETH_DMACHRDR_HRDAP_Pos   (0U)
     
    #define ETH_DMACHRDR_HRDAP_Msk   (0xFFFFFFFFUL << ETH_DMACHRDR_HRDAP_Pos)
     
    #define ETH_DMACHRDR_HRDAP   ETH_DMACHRDR_HRDAP_Msk /* Host receive descriptor address pointer */
     
    #define ETH_DMACHTBAR_HTBAP_Pos   (0U)
     
    #define ETH_DMACHTBAR_HTBAP_Msk   (0xFFFFFFFFUL << ETH_DMACHTBAR_HTBAP_Pos)
     
    #define ETH_DMACHTBAR_HTBAP   ETH_DMACHTBAR_HTBAP_Msk /* Host transmit buffer address pointer */
     
    #define ETH_DMACHRBAR_HRBAP_Pos   (0U)
     
    #define ETH_DMACHRBAR_HRBAP_Msk   (0xFFFFFFFFUL << ETH_DMACHRBAR_HRBAP_Pos)
     
    #define ETH_DMACHRBAR_HRBAP   ETH_DMACHRBAR_HRBAP_Msk /* Host receive buffer address pointer */
     
    #define USB_OTG_GOTGCTL_SRQSCS_Pos   (0U)
     
    #define USB_OTG_GOTGCTL_SRQSCS_Msk   (0x1UL << USB_OTG_GOTGCTL_SRQSCS_Pos)
     
    #define USB_OTG_GOTGCTL_SRQSCS   USB_OTG_GOTGCTL_SRQSCS_Msk
     
    #define USB_OTG_GOTGCTL_SRQ_Pos   (1U)
     
    #define USB_OTG_GOTGCTL_SRQ_Msk   (0x1UL << USB_OTG_GOTGCTL_SRQ_Pos)
     
    #define USB_OTG_GOTGCTL_SRQ   USB_OTG_GOTGCTL_SRQ_Msk
     
    #define USB_OTG_GOTGCTL_HNGSCS_Pos   (8U)
     
    #define USB_OTG_GOTGCTL_HNGSCS_Msk   (0x1UL << USB_OTG_GOTGCTL_HNGSCS_Pos)
     
    #define USB_OTG_GOTGCTL_HNGSCS   USB_OTG_GOTGCTL_HNGSCS_Msk
     
    #define USB_OTG_GOTGCTL_HNPRQ_Pos   (9U)
     
    #define USB_OTG_GOTGCTL_HNPRQ_Msk   (0x1UL << USB_OTG_GOTGCTL_HNPRQ_Pos)
     
    #define USB_OTG_GOTGCTL_HNPRQ   USB_OTG_GOTGCTL_HNPRQ_Msk
     
    #define USB_OTG_GOTGCTL_HSHNPEN_Pos   (10U)
     
    #define USB_OTG_GOTGCTL_HSHNPEN_Msk   (0x1UL << USB_OTG_GOTGCTL_HSHNPEN_Pos)
     
    #define USB_OTG_GOTGCTL_HSHNPEN   USB_OTG_GOTGCTL_HSHNPEN_Msk
     
    #define USB_OTG_GOTGCTL_DHNPEN_Pos   (11U)
     
    #define USB_OTG_GOTGCTL_DHNPEN_Msk   (0x1UL << USB_OTG_GOTGCTL_DHNPEN_Pos)
     
    #define USB_OTG_GOTGCTL_DHNPEN   USB_OTG_GOTGCTL_DHNPEN_Msk
     
    #define USB_OTG_GOTGCTL_CIDSTS_Pos   (16U)
     
    #define USB_OTG_GOTGCTL_CIDSTS_Msk   (0x1UL << USB_OTG_GOTGCTL_CIDSTS_Pos)
     
    #define USB_OTG_GOTGCTL_CIDSTS   USB_OTG_GOTGCTL_CIDSTS_Msk
     
    #define USB_OTG_GOTGCTL_DBCT_Pos   (17U)
     
    #define USB_OTG_GOTGCTL_DBCT_Msk   (0x1UL << USB_OTG_GOTGCTL_DBCT_Pos)
     
    #define USB_OTG_GOTGCTL_DBCT   USB_OTG_GOTGCTL_DBCT_Msk
     
    #define USB_OTG_GOTGCTL_ASVLD_Pos   (18U)
     
    #define USB_OTG_GOTGCTL_ASVLD_Msk   (0x1UL << USB_OTG_GOTGCTL_ASVLD_Pos)
     
    #define USB_OTG_GOTGCTL_ASVLD   USB_OTG_GOTGCTL_ASVLD_Msk
     
    #define USB_OTG_GOTGCTL_BSVLD_Pos   (19U)
     
    #define USB_OTG_GOTGCTL_BSVLD_Msk   (0x1UL << USB_OTG_GOTGCTL_BSVLD_Pos)
     
    #define USB_OTG_GOTGCTL_BSVLD   USB_OTG_GOTGCTL_BSVLD_Msk
     
    #define USB_OTG_HCFG_FSLSPCS_Pos   (0U)
     
    #define USB_OTG_HCFG_FSLSPCS_Msk   (0x3UL << USB_OTG_HCFG_FSLSPCS_Pos)
     
    #define USB_OTG_HCFG_FSLSPCS   USB_OTG_HCFG_FSLSPCS_Msk
     
    #define USB_OTG_HCFG_FSLSPCS_0   (0x1UL << USB_OTG_HCFG_FSLSPCS_Pos)
     
    #define USB_OTG_HCFG_FSLSPCS_1   (0x2UL << USB_OTG_HCFG_FSLSPCS_Pos)
     
    #define USB_OTG_HCFG_FSLSS_Pos   (2U)
     
    #define USB_OTG_HCFG_FSLSS_Msk   (0x1UL << USB_OTG_HCFG_FSLSS_Pos)
     
    #define USB_OTG_HCFG_FSLSS   USB_OTG_HCFG_FSLSS_Msk
     
    #define USB_OTG_DCFG_DSPD_Pos   (0U)
     
    #define USB_OTG_DCFG_DSPD_Msk   (0x3UL << USB_OTG_DCFG_DSPD_Pos)
     
    #define USB_OTG_DCFG_DSPD   USB_OTG_DCFG_DSPD_Msk
     
    #define USB_OTG_DCFG_DSPD_0   (0x1UL << USB_OTG_DCFG_DSPD_Pos)
     
    #define USB_OTG_DCFG_DSPD_1   (0x2UL << USB_OTG_DCFG_DSPD_Pos)
     
    #define USB_OTG_DCFG_NZLSOHSK_Pos   (2U)
     
    #define USB_OTG_DCFG_NZLSOHSK_Msk   (0x1UL << USB_OTG_DCFG_NZLSOHSK_Pos)
     
    #define USB_OTG_DCFG_NZLSOHSK   USB_OTG_DCFG_NZLSOHSK_Msk
     
    #define USB_OTG_DCFG_DAD_Pos   (4U)
     
    #define USB_OTG_DCFG_DAD_Msk   (0x7FUL << USB_OTG_DCFG_DAD_Pos)
     
    #define USB_OTG_DCFG_DAD   USB_OTG_DCFG_DAD_Msk
     
    #define USB_OTG_DCFG_DAD_0   (0x01UL << USB_OTG_DCFG_DAD_Pos)
     
    #define USB_OTG_DCFG_DAD_1   (0x02UL << USB_OTG_DCFG_DAD_Pos)
     
    #define USB_OTG_DCFG_DAD_2   (0x04UL << USB_OTG_DCFG_DAD_Pos)
     
    #define USB_OTG_DCFG_DAD_3   (0x08UL << USB_OTG_DCFG_DAD_Pos)
     
    #define USB_OTG_DCFG_DAD_4   (0x10UL << USB_OTG_DCFG_DAD_Pos)
     
    #define USB_OTG_DCFG_DAD_5   (0x20UL << USB_OTG_DCFG_DAD_Pos)
     
    #define USB_OTG_DCFG_DAD_6   (0x40UL << USB_OTG_DCFG_DAD_Pos)
     
    #define USB_OTG_DCFG_PFIVL_Pos   (11U)
     
    #define USB_OTG_DCFG_PFIVL_Msk   (0x3UL << USB_OTG_DCFG_PFIVL_Pos)
     
    #define USB_OTG_DCFG_PFIVL   USB_OTG_DCFG_PFIVL_Msk
     
    #define USB_OTG_DCFG_PFIVL_0   (0x1UL << USB_OTG_DCFG_PFIVL_Pos)
     
    #define USB_OTG_DCFG_PFIVL_1   (0x2UL << USB_OTG_DCFG_PFIVL_Pos)
     
    #define USB_OTG_DCFG_XCVRDLY_Pos   (14U)
     
    #define USB_OTG_DCFG_XCVRDLY_Msk   (0x1UL << USB_OTG_DCFG_XCVRDLY_Pos)
     
    #define USB_OTG_DCFG_XCVRDLY   USB_OTG_DCFG_XCVRDLY_Msk
     
    #define USB_OTG_DCFG_ERRATIM_Pos   (15U)
     
    #define USB_OTG_DCFG_ERRATIM_Msk   (0x1UL << USB_OTG_DCFG_ERRATIM_Pos)
     
    #define USB_OTG_DCFG_ERRATIM   USB_OTG_DCFG_ERRATIM_Msk
     
    #define USB_OTG_DCFG_PERSCHIVL_Pos   (24U)
     
    #define USB_OTG_DCFG_PERSCHIVL_Msk   (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos)
     
    #define USB_OTG_DCFG_PERSCHIVL   USB_OTG_DCFG_PERSCHIVL_Msk
     
    #define USB_OTG_DCFG_PERSCHIVL_0   (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos)
     
    #define USB_OTG_DCFG_PERSCHIVL_1   (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos)
     
    #define USB_OTG_PCGCR_STPPCLK_Pos   (0U)
     
    #define USB_OTG_PCGCR_STPPCLK_Msk   (0x1UL << USB_OTG_PCGCR_STPPCLK_Pos)
     
    #define USB_OTG_PCGCR_STPPCLK   USB_OTG_PCGCR_STPPCLK_Msk
     
    #define USB_OTG_PCGCR_GATEHCLK_Pos   (1U)
     
    #define USB_OTG_PCGCR_GATEHCLK_Msk   (0x1UL << USB_OTG_PCGCR_GATEHCLK_Pos)
     
    #define USB_OTG_PCGCR_GATEHCLK   USB_OTG_PCGCR_GATEHCLK_Msk
     
    #define USB_OTG_PCGCR_PHYSUSP_Pos   (4U)
     
    #define USB_OTG_PCGCR_PHYSUSP_Msk   (0x1UL << USB_OTG_PCGCR_PHYSUSP_Pos)
     
    #define USB_OTG_PCGCR_PHYSUSP   USB_OTG_PCGCR_PHYSUSP_Msk
     
    #define USB_OTG_GOTGINT_SEDET_Pos   (2U)
     
    #define USB_OTG_GOTGINT_SEDET_Msk   (0x1UL << USB_OTG_GOTGINT_SEDET_Pos)
     
    #define USB_OTG_GOTGINT_SEDET   USB_OTG_GOTGINT_SEDET_Msk
     
    #define USB_OTG_GOTGINT_SRSSCHG_Pos   (8U)
     
    #define USB_OTG_GOTGINT_SRSSCHG_Msk   (0x1UL << USB_OTG_GOTGINT_SRSSCHG_Pos)
     
    #define USB_OTG_GOTGINT_SRSSCHG   USB_OTG_GOTGINT_SRSSCHG_Msk
     
    #define USB_OTG_GOTGINT_HNSSCHG_Pos   (9U)
     
    #define USB_OTG_GOTGINT_HNSSCHG_Msk   (0x1UL << USB_OTG_GOTGINT_HNSSCHG_Pos)
     
    #define USB_OTG_GOTGINT_HNSSCHG   USB_OTG_GOTGINT_HNSSCHG_Msk
     
    #define USB_OTG_GOTGINT_HNGDET_Pos   (17U)
     
    #define USB_OTG_GOTGINT_HNGDET_Msk   (0x1UL << USB_OTG_GOTGINT_HNGDET_Pos)
     
    #define USB_OTG_GOTGINT_HNGDET   USB_OTG_GOTGINT_HNGDET_Msk
     
    #define USB_OTG_GOTGINT_ADTOCHG_Pos   (18U)
     
    #define USB_OTG_GOTGINT_ADTOCHG_Msk   (0x1UL << USB_OTG_GOTGINT_ADTOCHG_Pos)
     
    #define USB_OTG_GOTGINT_ADTOCHG   USB_OTG_GOTGINT_ADTOCHG_Msk
     
    #define USB_OTG_GOTGINT_DBCDNE_Pos   (19U)
     
    #define USB_OTG_GOTGINT_DBCDNE_Msk   (0x1UL << USB_OTG_GOTGINT_DBCDNE_Pos)
     
    #define USB_OTG_GOTGINT_DBCDNE   USB_OTG_GOTGINT_DBCDNE_Msk
     
    #define USB_OTG_DCTL_RWUSIG_Pos   (0U)
     
    #define USB_OTG_DCTL_RWUSIG_Msk   (0x1UL << USB_OTG_DCTL_RWUSIG_Pos)
     
    #define USB_OTG_DCTL_RWUSIG   USB_OTG_DCTL_RWUSIG_Msk
     
    #define USB_OTG_DCTL_SDIS_Pos   (1U)
     
    #define USB_OTG_DCTL_SDIS_Msk   (0x1UL << USB_OTG_DCTL_SDIS_Pos)
     
    #define USB_OTG_DCTL_SDIS   USB_OTG_DCTL_SDIS_Msk
     
    #define USB_OTG_DCTL_GINSTS_Pos   (2U)
     
    #define USB_OTG_DCTL_GINSTS_Msk   (0x1UL << USB_OTG_DCTL_GINSTS_Pos)
     
    #define USB_OTG_DCTL_GINSTS   USB_OTG_DCTL_GINSTS_Msk
     
    #define USB_OTG_DCTL_GONSTS_Pos   (3U)
     
    #define USB_OTG_DCTL_GONSTS_Msk   (0x1UL << USB_OTG_DCTL_GONSTS_Pos)
     
    #define USB_OTG_DCTL_GONSTS   USB_OTG_DCTL_GONSTS_Msk
     
    #define USB_OTG_DCTL_TCTL_Pos   (4U)
     
    #define USB_OTG_DCTL_TCTL_Msk   (0x7UL << USB_OTG_DCTL_TCTL_Pos)
     
    #define USB_OTG_DCTL_TCTL   USB_OTG_DCTL_TCTL_Msk
     
    #define USB_OTG_DCTL_TCTL_0   (0x1UL << USB_OTG_DCTL_TCTL_Pos)
     
    #define USB_OTG_DCTL_TCTL_1   (0x2UL << USB_OTG_DCTL_TCTL_Pos)
     
    #define USB_OTG_DCTL_TCTL_2   (0x4UL << USB_OTG_DCTL_TCTL_Pos)
     
    #define USB_OTG_DCTL_SGINAK_Pos   (7U)
     
    #define USB_OTG_DCTL_SGINAK_Msk   (0x1UL << USB_OTG_DCTL_SGINAK_Pos)
     
    #define USB_OTG_DCTL_SGINAK   USB_OTG_DCTL_SGINAK_Msk
     
    #define USB_OTG_DCTL_CGINAK_Pos   (8U)
     
    #define USB_OTG_DCTL_CGINAK_Msk   (0x1UL << USB_OTG_DCTL_CGINAK_Pos)
     
    #define USB_OTG_DCTL_CGINAK   USB_OTG_DCTL_CGINAK_Msk
     
    #define USB_OTG_DCTL_SGONAK_Pos   (9U)
     
    #define USB_OTG_DCTL_SGONAK_Msk   (0x1UL << USB_OTG_DCTL_SGONAK_Pos)
     
    #define USB_OTG_DCTL_SGONAK   USB_OTG_DCTL_SGONAK_Msk
     
    #define USB_OTG_DCTL_CGONAK_Pos   (10U)
     
    #define USB_OTG_DCTL_CGONAK_Msk   (0x1UL << USB_OTG_DCTL_CGONAK_Pos)
     
    #define USB_OTG_DCTL_CGONAK   USB_OTG_DCTL_CGONAK_Msk
     
    #define USB_OTG_DCTL_POPRGDNE_Pos   (11U)
     
    #define USB_OTG_DCTL_POPRGDNE_Msk   (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos)
     
    #define USB_OTG_DCTL_POPRGDNE   USB_OTG_DCTL_POPRGDNE_Msk
     
    #define USB_OTG_HFIR_FRIVL_Pos   (0U)
     
    #define USB_OTG_HFIR_FRIVL_Msk   (0xFFFFUL << USB_OTG_HFIR_FRIVL_Pos)
     
    #define USB_OTG_HFIR_FRIVL   USB_OTG_HFIR_FRIVL_Msk
     
    #define USB_OTG_HFNUM_FRNUM_Pos   (0U)
     
    #define USB_OTG_HFNUM_FRNUM_Msk   (0xFFFFUL << USB_OTG_HFNUM_FRNUM_Pos)
     
    #define USB_OTG_HFNUM_FRNUM   USB_OTG_HFNUM_FRNUM_Msk
     
    #define USB_OTG_HFNUM_FTREM_Pos   (16U)
     
    #define USB_OTG_HFNUM_FTREM_Msk   (0xFFFFUL << USB_OTG_HFNUM_FTREM_Pos)
     
    #define USB_OTG_HFNUM_FTREM   USB_OTG_HFNUM_FTREM_Msk
     
    #define USB_OTG_DSTS_SUSPSTS_Pos   (0U)
     
    #define USB_OTG_DSTS_SUSPSTS_Msk   (0x1UL << USB_OTG_DSTS_SUSPSTS_Pos)
     
    #define USB_OTG_DSTS_SUSPSTS   USB_OTG_DSTS_SUSPSTS_Msk
     
    #define USB_OTG_DSTS_ENUMSPD_Pos   (1U)
     
    #define USB_OTG_DSTS_ENUMSPD_Msk   (0x3UL << USB_OTG_DSTS_ENUMSPD_Pos)
     
    #define USB_OTG_DSTS_ENUMSPD   USB_OTG_DSTS_ENUMSPD_Msk
     
    #define USB_OTG_DSTS_ENUMSPD_0   (0x1UL << USB_OTG_DSTS_ENUMSPD_Pos)
     
    #define USB_OTG_DSTS_ENUMSPD_1   (0x2UL << USB_OTG_DSTS_ENUMSPD_Pos)
     
    #define USB_OTG_DSTS_EERR_Pos   (3U)
     
    #define USB_OTG_DSTS_EERR_Msk   (0x1UL << USB_OTG_DSTS_EERR_Pos)
     
    #define USB_OTG_DSTS_EERR   USB_OTG_DSTS_EERR_Msk
     
    #define USB_OTG_DSTS_FNSOF_Pos   (8U)
     
    #define USB_OTG_DSTS_FNSOF_Msk   (0x3FFFUL << USB_OTG_DSTS_FNSOF_Pos)
     
    #define USB_OTG_DSTS_FNSOF   USB_OTG_DSTS_FNSOF_Msk
     
    #define USB_OTG_GAHBCFG_GINT_Pos   (0U)
     
    #define USB_OTG_GAHBCFG_GINT_Msk   (0x1UL << USB_OTG_GAHBCFG_GINT_Pos)
     
    #define USB_OTG_GAHBCFG_GINT   USB_OTG_GAHBCFG_GINT_Msk
     
    #define USB_OTG_GAHBCFG_HBSTLEN_Pos   (1U)
     
    #define USB_OTG_GAHBCFG_HBSTLEN_Msk   (0xFUL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
     
    #define USB_OTG_GAHBCFG_HBSTLEN   USB_OTG_GAHBCFG_HBSTLEN_Msk
     
    #define USB_OTG_GAHBCFG_HBSTLEN_0   (0x0UL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
     
    #define USB_OTG_GAHBCFG_HBSTLEN_1   (0x1UL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
     
    #define USB_OTG_GAHBCFG_HBSTLEN_2   (0x3UL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
     
    #define USB_OTG_GAHBCFG_HBSTLEN_3   (0x5UL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
     
    #define USB_OTG_GAHBCFG_HBSTLEN_4   (0x7UL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
     
    #define USB_OTG_GAHBCFG_DMAEN_Pos   (5U)
     
    #define USB_OTG_GAHBCFG_DMAEN_Msk   (0x1UL << USB_OTG_GAHBCFG_DMAEN_Pos)
     
    #define USB_OTG_GAHBCFG_DMAEN   USB_OTG_GAHBCFG_DMAEN_Msk
     
    #define USB_OTG_GAHBCFG_TXFELVL_Pos   (7U)
     
    #define USB_OTG_GAHBCFG_TXFELVL_Msk   (0x1UL << USB_OTG_GAHBCFG_TXFELVL_Pos)
     
    #define USB_OTG_GAHBCFG_TXFELVL   USB_OTG_GAHBCFG_TXFELVL_Msk
     
    #define USB_OTG_GAHBCFG_PTXFELVL_Pos   (8U)
     
    #define USB_OTG_GAHBCFG_PTXFELVL_Msk   (0x1UL << USB_OTG_GAHBCFG_PTXFELVL_Pos)
     
    #define USB_OTG_GAHBCFG_PTXFELVL   USB_OTG_GAHBCFG_PTXFELVL_Msk
     
    #define USB_OTG_GUSBCFG_TOCAL_Pos   (0U)
     
    #define USB_OTG_GUSBCFG_TOCAL_Msk   (0x7UL << USB_OTG_GUSBCFG_TOCAL_Pos)
     
    #define USB_OTG_GUSBCFG_TOCAL   USB_OTG_GUSBCFG_TOCAL_Msk
     
    #define USB_OTG_GUSBCFG_TOCAL_0   (0x1UL << USB_OTG_GUSBCFG_TOCAL_Pos)
     
    #define USB_OTG_GUSBCFG_TOCAL_1   (0x2UL << USB_OTG_GUSBCFG_TOCAL_Pos)
     
    #define USB_OTG_GUSBCFG_TOCAL_2   (0x4UL << USB_OTG_GUSBCFG_TOCAL_Pos)
     
    #define USB_OTG_GUSBCFG_PHYSEL_Pos   (6U)
     
    #define USB_OTG_GUSBCFG_PHYSEL_Msk   (0x1UL << USB_OTG_GUSBCFG_PHYSEL_Pos)
     
    #define USB_OTG_GUSBCFG_PHYSEL   USB_OTG_GUSBCFG_PHYSEL_Msk
     
    #define USB_OTG_GUSBCFG_SRPCAP_Pos   (8U)
     
    #define USB_OTG_GUSBCFG_SRPCAP_Msk   (0x1UL << USB_OTG_GUSBCFG_SRPCAP_Pos)
     
    #define USB_OTG_GUSBCFG_SRPCAP   USB_OTG_GUSBCFG_SRPCAP_Msk
     
    #define USB_OTG_GUSBCFG_HNPCAP_Pos   (9U)
     
    #define USB_OTG_GUSBCFG_HNPCAP_Msk   (0x1UL << USB_OTG_GUSBCFG_HNPCAP_Pos)
     
    #define USB_OTG_GUSBCFG_HNPCAP   USB_OTG_GUSBCFG_HNPCAP_Msk
     
    #define USB_OTG_GUSBCFG_TRDT_Pos   (10U)
     
    #define USB_OTG_GUSBCFG_TRDT_Msk   (0xFUL << USB_OTG_GUSBCFG_TRDT_Pos)
     
    #define USB_OTG_GUSBCFG_TRDT   USB_OTG_GUSBCFG_TRDT_Msk
     
    #define USB_OTG_GUSBCFG_TRDT_0   (0x1UL << USB_OTG_GUSBCFG_TRDT_Pos)
     
    #define USB_OTG_GUSBCFG_TRDT_1   (0x2UL << USB_OTG_GUSBCFG_TRDT_Pos)
     
    #define USB_OTG_GUSBCFG_TRDT_2   (0x4UL << USB_OTG_GUSBCFG_TRDT_Pos)
     
    #define USB_OTG_GUSBCFG_TRDT_3   (0x8UL << USB_OTG_GUSBCFG_TRDT_Pos)
     
    #define USB_OTG_GUSBCFG_PHYLPCS_Pos   (15U)
     
    #define USB_OTG_GUSBCFG_PHYLPCS_Msk   (0x1UL << USB_OTG_GUSBCFG_PHYLPCS_Pos)
     
    #define USB_OTG_GUSBCFG_PHYLPCS   USB_OTG_GUSBCFG_PHYLPCS_Msk
     
    #define USB_OTG_GUSBCFG_ULPIFSLS_Pos   (17U)
     
    #define USB_OTG_GUSBCFG_ULPIFSLS_Msk   (0x1UL << USB_OTG_GUSBCFG_ULPIFSLS_Pos)
     
    #define USB_OTG_GUSBCFG_ULPIFSLS   USB_OTG_GUSBCFG_ULPIFSLS_Msk
     
    #define USB_OTG_GUSBCFG_ULPIAR_Pos   (18U)
     
    #define USB_OTG_GUSBCFG_ULPIAR_Msk   (0x1UL << USB_OTG_GUSBCFG_ULPIAR_Pos)
     
    #define USB_OTG_GUSBCFG_ULPIAR   USB_OTG_GUSBCFG_ULPIAR_Msk
     
    #define USB_OTG_GUSBCFG_ULPICSM_Pos   (19U)
     
    #define USB_OTG_GUSBCFG_ULPICSM_Msk   (0x1UL << USB_OTG_GUSBCFG_ULPICSM_Pos)
     
    #define USB_OTG_GUSBCFG_ULPICSM   USB_OTG_GUSBCFG_ULPICSM_Msk
     
    #define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos   (20U)
     
    #define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk   (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos)
     
    #define USB_OTG_GUSBCFG_ULPIEVBUSD   USB_OTG_GUSBCFG_ULPIEVBUSD_Msk
     
    #define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos   (21U)
     
    #define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk   (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos)
     
    #define USB_OTG_GUSBCFG_ULPIEVBUSI   USB_OTG_GUSBCFG_ULPIEVBUSI_Msk
     
    #define USB_OTG_GUSBCFG_TSDPS_Pos   (22U)
     
    #define USB_OTG_GUSBCFG_TSDPS_Msk   (0x1UL << USB_OTG_GUSBCFG_TSDPS_Pos)
     
    #define USB_OTG_GUSBCFG_TSDPS   USB_OTG_GUSBCFG_TSDPS_Msk
     
    #define USB_OTG_GUSBCFG_PCCI_Pos   (23U)
     
    #define USB_OTG_GUSBCFG_PCCI_Msk   (0x1UL << USB_OTG_GUSBCFG_PCCI_Pos)
     
    #define USB_OTG_GUSBCFG_PCCI   USB_OTG_GUSBCFG_PCCI_Msk
     
    #define USB_OTG_GUSBCFG_PTCI_Pos   (24U)
     
    #define USB_OTG_GUSBCFG_PTCI_Msk   (0x1UL << USB_OTG_GUSBCFG_PTCI_Pos)
     
    #define USB_OTG_GUSBCFG_PTCI   USB_OTG_GUSBCFG_PTCI_Msk
     
    #define USB_OTG_GUSBCFG_ULPIIPD_Pos   (25U)
     
    #define USB_OTG_GUSBCFG_ULPIIPD_Msk   (0x1UL << USB_OTG_GUSBCFG_ULPIIPD_Pos)
     
    #define USB_OTG_GUSBCFG_ULPIIPD   USB_OTG_GUSBCFG_ULPIIPD_Msk
     
    #define USB_OTG_GUSBCFG_FHMOD_Pos   (29U)
     
    #define USB_OTG_GUSBCFG_FHMOD_Msk   (0x1UL << USB_OTG_GUSBCFG_FHMOD_Pos)
     
    #define USB_OTG_GUSBCFG_FHMOD   USB_OTG_GUSBCFG_FHMOD_Msk
     
    #define USB_OTG_GUSBCFG_FDMOD_Pos   (30U)
     
    #define USB_OTG_GUSBCFG_FDMOD_Msk   (0x1UL << USB_OTG_GUSBCFG_FDMOD_Pos)
     
    #define USB_OTG_GUSBCFG_FDMOD   USB_OTG_GUSBCFG_FDMOD_Msk
     
    #define USB_OTG_GUSBCFG_CTXPKT_Pos   (31U)
     
    #define USB_OTG_GUSBCFG_CTXPKT_Msk   (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos)
     
    #define USB_OTG_GUSBCFG_CTXPKT   USB_OTG_GUSBCFG_CTXPKT_Msk
     
    #define USB_OTG_GRSTCTL_CSRST_Pos   (0U)
     
    #define USB_OTG_GRSTCTL_CSRST_Msk   (0x1UL << USB_OTG_GRSTCTL_CSRST_Pos)
     
    #define USB_OTG_GRSTCTL_CSRST   USB_OTG_GRSTCTL_CSRST_Msk
     
    #define USB_OTG_GRSTCTL_HSRST_Pos   (1U)
     
    #define USB_OTG_GRSTCTL_HSRST_Msk   (0x1UL << USB_OTG_GRSTCTL_HSRST_Pos)
     
    #define USB_OTG_GRSTCTL_HSRST   USB_OTG_GRSTCTL_HSRST_Msk
     
    #define USB_OTG_GRSTCTL_FCRST_Pos   (2U)
     
    #define USB_OTG_GRSTCTL_FCRST_Msk   (0x1UL << USB_OTG_GRSTCTL_FCRST_Pos)
     
    #define USB_OTG_GRSTCTL_FCRST   USB_OTG_GRSTCTL_FCRST_Msk
     
    #define USB_OTG_GRSTCTL_RXFFLSH_Pos   (4U)
     
    #define USB_OTG_GRSTCTL_RXFFLSH_Msk   (0x1UL << USB_OTG_GRSTCTL_RXFFLSH_Pos)
     
    #define USB_OTG_GRSTCTL_RXFFLSH   USB_OTG_GRSTCTL_RXFFLSH_Msk
     
    #define USB_OTG_GRSTCTL_TXFFLSH_Pos   (5U)
     
    #define USB_OTG_GRSTCTL_TXFFLSH_Msk   (0x1UL << USB_OTG_GRSTCTL_TXFFLSH_Pos)
     
    #define USB_OTG_GRSTCTL_TXFFLSH   USB_OTG_GRSTCTL_TXFFLSH_Msk
     
    #define USB_OTG_GRSTCTL_TXFNUM_Pos   (6U)
     
    #define USB_OTG_GRSTCTL_TXFNUM_Msk   (0x1FUL << USB_OTG_GRSTCTL_TXFNUM_Pos)
     
    #define USB_OTG_GRSTCTL_TXFNUM   USB_OTG_GRSTCTL_TXFNUM_Msk
     
    #define USB_OTG_GRSTCTL_TXFNUM_0   (0x01UL << USB_OTG_GRSTCTL_TXFNUM_Pos)
     
    #define USB_OTG_GRSTCTL_TXFNUM_1   (0x02UL << USB_OTG_GRSTCTL_TXFNUM_Pos)
     
    #define USB_OTG_GRSTCTL_TXFNUM_2   (0x04UL << USB_OTG_GRSTCTL_TXFNUM_Pos)
     
    #define USB_OTG_GRSTCTL_TXFNUM_3   (0x08UL << USB_OTG_GRSTCTL_TXFNUM_Pos)
     
    #define USB_OTG_GRSTCTL_TXFNUM_4   (0x10UL << USB_OTG_GRSTCTL_TXFNUM_Pos)
     
    #define USB_OTG_GRSTCTL_DMAREQ_Pos   (30U)
     
    #define USB_OTG_GRSTCTL_DMAREQ_Msk   (0x1UL << USB_OTG_GRSTCTL_DMAREQ_Pos)
     
    #define USB_OTG_GRSTCTL_DMAREQ   USB_OTG_GRSTCTL_DMAREQ_Msk
     
    #define USB_OTG_GRSTCTL_AHBIDL_Pos   (31U)
     
    #define USB_OTG_GRSTCTL_AHBIDL_Msk   (0x1UL << USB_OTG_GRSTCTL_AHBIDL_Pos)
     
    #define USB_OTG_GRSTCTL_AHBIDL   USB_OTG_GRSTCTL_AHBIDL_Msk
     
    #define USB_OTG_DIEPMSK_XFRCM_Pos   (0U)
     
    #define USB_OTG_DIEPMSK_XFRCM_Msk   (0x1UL << USB_OTG_DIEPMSK_XFRCM_Pos)
     
    #define USB_OTG_DIEPMSK_XFRCM   USB_OTG_DIEPMSK_XFRCM_Msk
     
    #define USB_OTG_DIEPMSK_EPDM_Pos   (1U)
     
    #define USB_OTG_DIEPMSK_EPDM_Msk   (0x1UL << USB_OTG_DIEPMSK_EPDM_Pos)
     
    #define USB_OTG_DIEPMSK_EPDM   USB_OTG_DIEPMSK_EPDM_Msk
     
    #define USB_OTG_DIEPMSK_TOM_Pos   (3U)
     
    #define USB_OTG_DIEPMSK_TOM_Msk   (0x1UL << USB_OTG_DIEPMSK_TOM_Pos)
     
    #define USB_OTG_DIEPMSK_TOM   USB_OTG_DIEPMSK_TOM_Msk
     
    #define USB_OTG_DIEPMSK_ITTXFEMSK_Pos   (4U)
     
    #define USB_OTG_DIEPMSK_ITTXFEMSK_Msk   (0x1UL << USB_OTG_DIEPMSK_ITTXFEMSK_Pos)
     
    #define USB_OTG_DIEPMSK_ITTXFEMSK   USB_OTG_DIEPMSK_ITTXFEMSK_Msk
     
    #define USB_OTG_DIEPMSK_INEPNMM_Pos   (5U)
     
    #define USB_OTG_DIEPMSK_INEPNMM_Msk   (0x1UL << USB_OTG_DIEPMSK_INEPNMM_Pos)
     
    #define USB_OTG_DIEPMSK_INEPNMM   USB_OTG_DIEPMSK_INEPNMM_Msk
     
    #define USB_OTG_DIEPMSK_INEPNEM_Pos   (6U)
     
    #define USB_OTG_DIEPMSK_INEPNEM_Msk   (0x1UL << USB_OTG_DIEPMSK_INEPNEM_Pos)
     
    #define USB_OTG_DIEPMSK_INEPNEM   USB_OTG_DIEPMSK_INEPNEM_Msk
     
    #define USB_OTG_DIEPMSK_TXFURM_Pos   (8U)
     
    #define USB_OTG_DIEPMSK_TXFURM_Msk   (0x1UL << USB_OTG_DIEPMSK_TXFURM_Pos)
     
    #define USB_OTG_DIEPMSK_TXFURM   USB_OTG_DIEPMSK_TXFURM_Msk
     
    #define USB_OTG_DIEPMSK_BIM_Pos   (9U)
     
    #define USB_OTG_DIEPMSK_BIM_Msk   (0x1UL << USB_OTG_DIEPMSK_BIM_Pos)
     
    #define USB_OTG_DIEPMSK_BIM   USB_OTG_DIEPMSK_BIM_Msk
     
    #define USB_OTG_HPTXSTS_PTXFSAVL_Pos   (0U)
     
    #define USB_OTG_HPTXSTS_PTXFSAVL_Msk   (0xFFFFUL << USB_OTG_HPTXSTS_PTXFSAVL_Pos)
     
    #define USB_OTG_HPTXSTS_PTXFSAVL   USB_OTG_HPTXSTS_PTXFSAVL_Msk
     
    #define USB_OTG_HPTXSTS_PTXQSAV_Pos   (16U)
     
    #define USB_OTG_HPTXSTS_PTXQSAV_Msk   (0xFFUL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
     
    #define USB_OTG_HPTXSTS_PTXQSAV   USB_OTG_HPTXSTS_PTXQSAV_Msk
     
    #define USB_OTG_HPTXSTS_PTXQSAV_0   (0x01UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
     
    #define USB_OTG_HPTXSTS_PTXQSAV_1   (0x02UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
     
    #define USB_OTG_HPTXSTS_PTXQSAV_2   (0x04UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
     
    #define USB_OTG_HPTXSTS_PTXQSAV_3   (0x08UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
     
    #define USB_OTG_HPTXSTS_PTXQSAV_4   (0x10UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
     
    #define USB_OTG_HPTXSTS_PTXQSAV_5   (0x20UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
     
    #define USB_OTG_HPTXSTS_PTXQSAV_6   (0x40UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
     
    #define USB_OTG_HPTXSTS_PTXQSAV_7   (0x80UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
     
    #define USB_OTG_HPTXSTS_PTXQTOP_Pos   (24U)
     
    #define USB_OTG_HPTXSTS_PTXQTOP_Msk   (0xFFUL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
     
    #define USB_OTG_HPTXSTS_PTXQTOP   USB_OTG_HPTXSTS_PTXQTOP_Msk
     
    #define USB_OTG_HPTXSTS_PTXQTOP_0   (0x01UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
     
    #define USB_OTG_HPTXSTS_PTXQTOP_1   (0x02UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
     
    #define USB_OTG_HPTXSTS_PTXQTOP_2   (0x04UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
     
    #define USB_OTG_HPTXSTS_PTXQTOP_3   (0x08UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
     
    #define USB_OTG_HPTXSTS_PTXQTOP_4   (0x10UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
     
    #define USB_OTG_HPTXSTS_PTXQTOP_5   (0x20UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
     
    #define USB_OTG_HPTXSTS_PTXQTOP_6   (0x40UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
     
    #define USB_OTG_HPTXSTS_PTXQTOP_7   (0x80UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
     
    #define USB_OTG_HAINT_HAINT_Pos   (0U)
     
    #define USB_OTG_HAINT_HAINT_Msk   (0xFFFFUL << USB_OTG_HAINT_HAINT_Pos)
     
    #define USB_OTG_HAINT_HAINT   USB_OTG_HAINT_HAINT_Msk
     
    #define USB_OTG_DOEPMSK_XFRCM_Pos   (0U)
     
    #define USB_OTG_DOEPMSK_XFRCM_Msk   (0x1UL << USB_OTG_DOEPMSK_XFRCM_Pos)
     
    #define USB_OTG_DOEPMSK_XFRCM   USB_OTG_DOEPMSK_XFRCM_Msk
     
    #define USB_OTG_DOEPMSK_EPDM_Pos   (1U)
     
    #define USB_OTG_DOEPMSK_EPDM_Msk   (0x1UL << USB_OTG_DOEPMSK_EPDM_Pos)
     
    #define USB_OTG_DOEPMSK_EPDM   USB_OTG_DOEPMSK_EPDM_Msk
     
    #define USB_OTG_DOEPMSK_AHBERRM_Pos   (2U)
     
    #define USB_OTG_DOEPMSK_AHBERRM_Msk   (0x1UL << USB_OTG_DOEPMSK_AHBERRM_Pos)
     
    #define USB_OTG_DOEPMSK_AHBERRM   USB_OTG_DOEPMSK_AHBERRM_Msk
     
    #define USB_OTG_DOEPMSK_STUPM_Pos   (3U)
     
    #define USB_OTG_DOEPMSK_STUPM_Msk   (0x1UL << USB_OTG_DOEPMSK_STUPM_Pos)
     
    #define USB_OTG_DOEPMSK_STUPM   USB_OTG_DOEPMSK_STUPM_Msk
     
    #define USB_OTG_DOEPMSK_OTEPDM_Pos   (4U)
     
    #define USB_OTG_DOEPMSK_OTEPDM_Msk   (0x1UL << USB_OTG_DOEPMSK_OTEPDM_Pos)
     
    #define USB_OTG_DOEPMSK_OTEPDM   USB_OTG_DOEPMSK_OTEPDM_Msk
     
    #define USB_OTG_DOEPMSK_OTEPSPRM_Pos   (5U)
     
    #define USB_OTG_DOEPMSK_OTEPSPRM_Msk   (0x1UL << USB_OTG_DOEPMSK_OTEPSPRM_Pos)
     
    #define USB_OTG_DOEPMSK_OTEPSPRM   USB_OTG_DOEPMSK_OTEPSPRM_Msk
     
    #define USB_OTG_DOEPMSK_B2BSTUP_Pos   (6U)
     
    #define USB_OTG_DOEPMSK_B2BSTUP_Msk   (0x1UL << USB_OTG_DOEPMSK_B2BSTUP_Pos)
     
    #define USB_OTG_DOEPMSK_B2BSTUP   USB_OTG_DOEPMSK_B2BSTUP_Msk
     
    #define USB_OTG_DOEPMSK_OPEM_Pos   (8U)
     
    #define USB_OTG_DOEPMSK_OPEM_Msk   (0x1UL << USB_OTG_DOEPMSK_OPEM_Pos)
     
    #define USB_OTG_DOEPMSK_OPEM   USB_OTG_DOEPMSK_OPEM_Msk
     
    #define USB_OTG_DOEPMSK_BOIM_Pos   (9U)
     
    #define USB_OTG_DOEPMSK_BOIM_Msk   (0x1UL << USB_OTG_DOEPMSK_BOIM_Pos)
     
    #define USB_OTG_DOEPMSK_BOIM   USB_OTG_DOEPMSK_BOIM_Msk
     
    #define USB_OTG_DOEPMSK_BERRM_Pos   (12U)
     
    #define USB_OTG_DOEPMSK_BERRM_Msk   (0x1UL << USB_OTG_DOEPMSK_BERRM_Pos)
     
    #define USB_OTG_DOEPMSK_BERRM   USB_OTG_DOEPMSK_BERRM_Msk
     
    #define USB_OTG_DOEPMSK_NAKM_Pos   (13U)
     
    #define USB_OTG_DOEPMSK_NAKM_Msk   (0x1UL << USB_OTG_DOEPMSK_NAKM_Pos)
     
    #define USB_OTG_DOEPMSK_NAKM   USB_OTG_DOEPMSK_NAKM_Msk
     
    #define USB_OTG_DOEPMSK_NYETM_Pos   (14U)
     
    #define USB_OTG_DOEPMSK_NYETM_Msk   (0x1UL << USB_OTG_DOEPMSK_NYETM_Pos)
     
    #define USB_OTG_DOEPMSK_NYETM   USB_OTG_DOEPMSK_NYETM_Msk
     
    #define USB_OTG_GINTSTS_CMOD_Pos   (0U)
     
    #define USB_OTG_GINTSTS_CMOD_Msk   (0x1UL << USB_OTG_GINTSTS_CMOD_Pos)
     
    #define USB_OTG_GINTSTS_CMOD   USB_OTG_GINTSTS_CMOD_Msk
     
    #define USB_OTG_GINTSTS_MMIS_Pos   (1U)
     
    #define USB_OTG_GINTSTS_MMIS_Msk   (0x1UL << USB_OTG_GINTSTS_MMIS_Pos)
     
    #define USB_OTG_GINTSTS_MMIS   USB_OTG_GINTSTS_MMIS_Msk
     
    #define USB_OTG_GINTSTS_OTGINT_Pos   (2U)
     
    #define USB_OTG_GINTSTS_OTGINT_Msk   (0x1UL << USB_OTG_GINTSTS_OTGINT_Pos)
     
    #define USB_OTG_GINTSTS_OTGINT   USB_OTG_GINTSTS_OTGINT_Msk
     
    #define USB_OTG_GINTSTS_SOF_Pos   (3U)
     
    #define USB_OTG_GINTSTS_SOF_Msk   (0x1UL << USB_OTG_GINTSTS_SOF_Pos)
     
    #define USB_OTG_GINTSTS_SOF   USB_OTG_GINTSTS_SOF_Msk
     
    #define USB_OTG_GINTSTS_RXFLVL_Pos   (4U)
     
    #define USB_OTG_GINTSTS_RXFLVL_Msk   (0x1UL << USB_OTG_GINTSTS_RXFLVL_Pos)
     
    #define USB_OTG_GINTSTS_RXFLVL   USB_OTG_GINTSTS_RXFLVL_Msk
     
    #define USB_OTG_GINTSTS_NPTXFE_Pos   (5U)
     
    #define USB_OTG_GINTSTS_NPTXFE_Msk   (0x1UL << USB_OTG_GINTSTS_NPTXFE_Pos)
     
    #define USB_OTG_GINTSTS_NPTXFE   USB_OTG_GINTSTS_NPTXFE_Msk
     
    #define USB_OTG_GINTSTS_GINAKEFF_Pos   (6U)
     
    #define USB_OTG_GINTSTS_GINAKEFF_Msk   (0x1UL << USB_OTG_GINTSTS_GINAKEFF_Pos)
     
    #define USB_OTG_GINTSTS_GINAKEFF   USB_OTG_GINTSTS_GINAKEFF_Msk
     
    #define USB_OTG_GINTSTS_BOUTNAKEFF_Pos   (7U)
     
    #define USB_OTG_GINTSTS_BOUTNAKEFF_Msk   (0x1UL << USB_OTG_GINTSTS_BOUTNAKEFF_Pos)
     
    #define USB_OTG_GINTSTS_BOUTNAKEFF   USB_OTG_GINTSTS_BOUTNAKEFF_Msk
     
    #define USB_OTG_GINTSTS_ESUSP_Pos   (10U)
     
    #define USB_OTG_GINTSTS_ESUSP_Msk   (0x1UL << USB_OTG_GINTSTS_ESUSP_Pos)
     
    #define USB_OTG_GINTSTS_ESUSP   USB_OTG_GINTSTS_ESUSP_Msk
     
    #define USB_OTG_GINTSTS_USBSUSP_Pos   (11U)
     
    #define USB_OTG_GINTSTS_USBSUSP_Msk   (0x1UL << USB_OTG_GINTSTS_USBSUSP_Pos)
     
    #define USB_OTG_GINTSTS_USBSUSP   USB_OTG_GINTSTS_USBSUSP_Msk
     
    #define USB_OTG_GINTSTS_USBRST_Pos   (12U)
     
    #define USB_OTG_GINTSTS_USBRST_Msk   (0x1UL << USB_OTG_GINTSTS_USBRST_Pos)
     
    #define USB_OTG_GINTSTS_USBRST   USB_OTG_GINTSTS_USBRST_Msk
     
    #define USB_OTG_GINTSTS_ENUMDNE_Pos   (13U)
     
    #define USB_OTG_GINTSTS_ENUMDNE_Msk   (0x1UL << USB_OTG_GINTSTS_ENUMDNE_Pos)
     
    #define USB_OTG_GINTSTS_ENUMDNE   USB_OTG_GINTSTS_ENUMDNE_Msk
     
    #define USB_OTG_GINTSTS_ISOODRP_Pos   (14U)
     
    #define USB_OTG_GINTSTS_ISOODRP_Msk   (0x1UL << USB_OTG_GINTSTS_ISOODRP_Pos)
     
    #define USB_OTG_GINTSTS_ISOODRP   USB_OTG_GINTSTS_ISOODRP_Msk
     
    #define USB_OTG_GINTSTS_EOPF_Pos   (15U)
     
    #define USB_OTG_GINTSTS_EOPF_Msk   (0x1UL << USB_OTG_GINTSTS_EOPF_Pos)
     
    #define USB_OTG_GINTSTS_EOPF   USB_OTG_GINTSTS_EOPF_Msk
     
    #define USB_OTG_GINTSTS_IEPINT_Pos   (18U)
     
    #define USB_OTG_GINTSTS_IEPINT_Msk   (0x1UL << USB_OTG_GINTSTS_IEPINT_Pos)
     
    #define USB_OTG_GINTSTS_IEPINT   USB_OTG_GINTSTS_IEPINT_Msk
     
    #define USB_OTG_GINTSTS_OEPINT_Pos   (19U)
     
    #define USB_OTG_GINTSTS_OEPINT_Msk   (0x1UL << USB_OTG_GINTSTS_OEPINT_Pos)
     
    #define USB_OTG_GINTSTS_OEPINT   USB_OTG_GINTSTS_OEPINT_Msk
     
    #define USB_OTG_GINTSTS_IISOIXFR_Pos   (20U)
     
    #define USB_OTG_GINTSTS_IISOIXFR_Msk   (0x1UL << USB_OTG_GINTSTS_IISOIXFR_Pos)
     
    #define USB_OTG_GINTSTS_IISOIXFR   USB_OTG_GINTSTS_IISOIXFR_Msk
     
    #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos   (21U)
     
    #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk   (0x1UL << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos)
     
    #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT   USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk
     
    #define USB_OTG_GINTSTS_DATAFSUSP_Pos   (22U)
     
    #define USB_OTG_GINTSTS_DATAFSUSP_Msk   (0x1UL << USB_OTG_GINTSTS_DATAFSUSP_Pos)
     
    #define USB_OTG_GINTSTS_DATAFSUSP   USB_OTG_GINTSTS_DATAFSUSP_Msk
     
    #define USB_OTG_GINTSTS_HPRTINT_Pos   (24U)
     
    #define USB_OTG_GINTSTS_HPRTINT_Msk   (0x1UL << USB_OTG_GINTSTS_HPRTINT_Pos)
     
    #define USB_OTG_GINTSTS_HPRTINT   USB_OTG_GINTSTS_HPRTINT_Msk
     
    #define USB_OTG_GINTSTS_HCINT_Pos   (25U)
     
    #define USB_OTG_GINTSTS_HCINT_Msk   (0x1UL << USB_OTG_GINTSTS_HCINT_Pos)
     
    #define USB_OTG_GINTSTS_HCINT   USB_OTG_GINTSTS_HCINT_Msk
     
    #define USB_OTG_GINTSTS_PTXFE_Pos   (26U)
     
    #define USB_OTG_GINTSTS_PTXFE_Msk   (0x1UL << USB_OTG_GINTSTS_PTXFE_Pos)
     
    #define USB_OTG_GINTSTS_PTXFE   USB_OTG_GINTSTS_PTXFE_Msk
     
    #define USB_OTG_GINTSTS_CIDSCHG_Pos   (28U)
     
    #define USB_OTG_GINTSTS_CIDSCHG_Msk   (0x1UL << USB_OTG_GINTSTS_CIDSCHG_Pos)
     
    #define USB_OTG_GINTSTS_CIDSCHG   USB_OTG_GINTSTS_CIDSCHG_Msk
     
    #define USB_OTG_GINTSTS_DISCINT_Pos   (29U)
     
    #define USB_OTG_GINTSTS_DISCINT_Msk   (0x1UL << USB_OTG_GINTSTS_DISCINT_Pos)
     
    #define USB_OTG_GINTSTS_DISCINT   USB_OTG_GINTSTS_DISCINT_Msk
     
    #define USB_OTG_GINTSTS_SRQINT_Pos   (30U)
     
    #define USB_OTG_GINTSTS_SRQINT_Msk   (0x1UL << USB_OTG_GINTSTS_SRQINT_Pos)
     
    #define USB_OTG_GINTSTS_SRQINT   USB_OTG_GINTSTS_SRQINT_Msk
     
    #define USB_OTG_GINTSTS_WKUINT_Pos   (31U)
     
    #define USB_OTG_GINTSTS_WKUINT_Msk   (0x1UL << USB_OTG_GINTSTS_WKUINT_Pos)
     
    #define USB_OTG_GINTSTS_WKUINT   USB_OTG_GINTSTS_WKUINT_Msk
     
    #define USB_OTG_GINTMSK_MMISM_Pos   (1U)
     
    #define USB_OTG_GINTMSK_MMISM_Msk   (0x1UL << USB_OTG_GINTMSK_MMISM_Pos)
     
    #define USB_OTG_GINTMSK_MMISM   USB_OTG_GINTMSK_MMISM_Msk
     
    #define USB_OTG_GINTMSK_OTGINT_Pos   (2U)
     
    #define USB_OTG_GINTMSK_OTGINT_Msk   (0x1UL << USB_OTG_GINTMSK_OTGINT_Pos)
     
    #define USB_OTG_GINTMSK_OTGINT   USB_OTG_GINTMSK_OTGINT_Msk
     
    #define USB_OTG_GINTMSK_SOFM_Pos   (3U)
     
    #define USB_OTG_GINTMSK_SOFM_Msk   (0x1UL << USB_OTG_GINTMSK_SOFM_Pos)
     
    #define USB_OTG_GINTMSK_SOFM   USB_OTG_GINTMSK_SOFM_Msk
     
    #define USB_OTG_GINTMSK_RXFLVLM_Pos   (4U)
     
    #define USB_OTG_GINTMSK_RXFLVLM_Msk   (0x1UL << USB_OTG_GINTMSK_RXFLVLM_Pos)
     
    #define USB_OTG_GINTMSK_RXFLVLM   USB_OTG_GINTMSK_RXFLVLM_Msk
     
    #define USB_OTG_GINTMSK_NPTXFEM_Pos   (5U)
     
    #define USB_OTG_GINTMSK_NPTXFEM_Msk   (0x1UL << USB_OTG_GINTMSK_NPTXFEM_Pos)
     
    #define USB_OTG_GINTMSK_NPTXFEM   USB_OTG_GINTMSK_NPTXFEM_Msk
     
    #define USB_OTG_GINTMSK_GINAKEFFM_Pos   (6U)
     
    #define USB_OTG_GINTMSK_GINAKEFFM_Msk   (0x1UL << USB_OTG_GINTMSK_GINAKEFFM_Pos)
     
    #define USB_OTG_GINTMSK_GINAKEFFM   USB_OTG_GINTMSK_GINAKEFFM_Msk
     
    #define USB_OTG_GINTMSK_GONAKEFFM_Pos   (7U)
     
    #define USB_OTG_GINTMSK_GONAKEFFM_Msk   (0x1UL << USB_OTG_GINTMSK_GONAKEFFM_Pos)
     
    #define USB_OTG_GINTMSK_GONAKEFFM   USB_OTG_GINTMSK_GONAKEFFM_Msk
     
    #define USB_OTG_GINTMSK_ESUSPM_Pos   (10U)
     
    #define USB_OTG_GINTMSK_ESUSPM_Msk   (0x1UL << USB_OTG_GINTMSK_ESUSPM_Pos)
     
    #define USB_OTG_GINTMSK_ESUSPM   USB_OTG_GINTMSK_ESUSPM_Msk
     
    #define USB_OTG_GINTMSK_USBSUSPM_Pos   (11U)
     
    #define USB_OTG_GINTMSK_USBSUSPM_Msk   (0x1UL << USB_OTG_GINTMSK_USBSUSPM_Pos)
     
    #define USB_OTG_GINTMSK_USBSUSPM   USB_OTG_GINTMSK_USBSUSPM_Msk
     
    #define USB_OTG_GINTMSK_USBRST_Pos   (12U)
     
    #define USB_OTG_GINTMSK_USBRST_Msk   (0x1UL << USB_OTG_GINTMSK_USBRST_Pos)
     
    #define USB_OTG_GINTMSK_USBRST   USB_OTG_GINTMSK_USBRST_Msk
     
    #define USB_OTG_GINTMSK_ENUMDNEM_Pos   (13U)
     
    #define USB_OTG_GINTMSK_ENUMDNEM_Msk   (0x1UL << USB_OTG_GINTMSK_ENUMDNEM_Pos)
     
    #define USB_OTG_GINTMSK_ENUMDNEM   USB_OTG_GINTMSK_ENUMDNEM_Msk
     
    #define USB_OTG_GINTMSK_ISOODRPM_Pos   (14U)
     
    #define USB_OTG_GINTMSK_ISOODRPM_Msk   (0x1UL << USB_OTG_GINTMSK_ISOODRPM_Pos)
     
    #define USB_OTG_GINTMSK_ISOODRPM   USB_OTG_GINTMSK_ISOODRPM_Msk
     
    #define USB_OTG_GINTMSK_EOPFM_Pos   (15U)
     
    #define USB_OTG_GINTMSK_EOPFM_Msk   (0x1UL << USB_OTG_GINTMSK_EOPFM_Pos)
     
    #define USB_OTG_GINTMSK_EOPFM   USB_OTG_GINTMSK_EOPFM_Msk
     
    #define USB_OTG_GINTMSK_EPMISM_Pos   (17U)
     
    #define USB_OTG_GINTMSK_EPMISM_Msk   (0x1UL << USB_OTG_GINTMSK_EPMISM_Pos)
     
    #define USB_OTG_GINTMSK_EPMISM   USB_OTG_GINTMSK_EPMISM_Msk
     
    #define USB_OTG_GINTMSK_IEPINT_Pos   (18U)
     
    #define USB_OTG_GINTMSK_IEPINT_Msk   (0x1UL << USB_OTG_GINTMSK_IEPINT_Pos)
     
    #define USB_OTG_GINTMSK_IEPINT   USB_OTG_GINTMSK_IEPINT_Msk
     
    #define USB_OTG_GINTMSK_OEPINT_Pos   (19U)
     
    #define USB_OTG_GINTMSK_OEPINT_Msk   (0x1UL << USB_OTG_GINTMSK_OEPINT_Pos)
     
    #define USB_OTG_GINTMSK_OEPINT   USB_OTG_GINTMSK_OEPINT_Msk
     
    #define USB_OTG_GINTMSK_IISOIXFRM_Pos   (20U)
     
    #define USB_OTG_GINTMSK_IISOIXFRM_Msk   (0x1UL << USB_OTG_GINTMSK_IISOIXFRM_Pos)
     
    #define USB_OTG_GINTMSK_IISOIXFRM   USB_OTG_GINTMSK_IISOIXFRM_Msk
     
    #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos   (21U)
     
    #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk   (0x1UL << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos)
     
    #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM   USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk
     
    #define USB_OTG_GINTMSK_FSUSPM_Pos   (22U)
     
    #define USB_OTG_GINTMSK_FSUSPM_Msk   (0x1UL << USB_OTG_GINTMSK_FSUSPM_Pos)
     
    #define USB_OTG_GINTMSK_FSUSPM   USB_OTG_GINTMSK_FSUSPM_Msk
     
    #define USB_OTG_GINTMSK_PRTIM_Pos   (24U)
     
    #define USB_OTG_GINTMSK_PRTIM_Msk   (0x1UL << USB_OTG_GINTMSK_PRTIM_Pos)
     
    #define USB_OTG_GINTMSK_PRTIM   USB_OTG_GINTMSK_PRTIM_Msk
     
    #define USB_OTG_GINTMSK_HCIM_Pos   (25U)
     
    #define USB_OTG_GINTMSK_HCIM_Msk   (0x1UL << USB_OTG_GINTMSK_HCIM_Pos)
     
    #define USB_OTG_GINTMSK_HCIM   USB_OTG_GINTMSK_HCIM_Msk
     
    #define USB_OTG_GINTMSK_PTXFEM_Pos   (26U)
     
    #define USB_OTG_GINTMSK_PTXFEM_Msk   (0x1UL << USB_OTG_GINTMSK_PTXFEM_Pos)
     
    #define USB_OTG_GINTMSK_PTXFEM   USB_OTG_GINTMSK_PTXFEM_Msk
     
    #define USB_OTG_GINTMSK_CIDSCHGM_Pos   (28U)
     
    #define USB_OTG_GINTMSK_CIDSCHGM_Msk   (0x1UL << USB_OTG_GINTMSK_CIDSCHGM_Pos)
     
    #define USB_OTG_GINTMSK_CIDSCHGM   USB_OTG_GINTMSK_CIDSCHGM_Msk
     
    #define USB_OTG_GINTMSK_DISCINT_Pos   (29U)
     
    #define USB_OTG_GINTMSK_DISCINT_Msk   (0x1UL << USB_OTG_GINTMSK_DISCINT_Pos)
     
    #define USB_OTG_GINTMSK_DISCINT   USB_OTG_GINTMSK_DISCINT_Msk
     
    #define USB_OTG_GINTMSK_SRQIM_Pos   (30U)
     
    #define USB_OTG_GINTMSK_SRQIM_Msk   (0x1UL << USB_OTG_GINTMSK_SRQIM_Pos)
     
    #define USB_OTG_GINTMSK_SRQIM   USB_OTG_GINTMSK_SRQIM_Msk
     
    #define USB_OTG_GINTMSK_WUIM_Pos   (31U)
     
    #define USB_OTG_GINTMSK_WUIM_Msk   (0x1UL << USB_OTG_GINTMSK_WUIM_Pos)
     
    #define USB_OTG_GINTMSK_WUIM   USB_OTG_GINTMSK_WUIM_Msk
     
    #define USB_OTG_DAINT_IEPINT_Pos   (0U)
     
    #define USB_OTG_DAINT_IEPINT_Msk   (0xFFFFUL << USB_OTG_DAINT_IEPINT_Pos)
     
    #define USB_OTG_DAINT_IEPINT   USB_OTG_DAINT_IEPINT_Msk
     
    #define USB_OTG_DAINT_OEPINT_Pos   (16U)
     
    #define USB_OTG_DAINT_OEPINT_Msk   (0xFFFFUL << USB_OTG_DAINT_OEPINT_Pos)
     
    #define USB_OTG_DAINT_OEPINT   USB_OTG_DAINT_OEPINT_Msk
     
    #define USB_OTG_HAINTMSK_HAINTM_Pos   (0U)
     
    #define USB_OTG_HAINTMSK_HAINTM_Msk   (0xFFFFUL << USB_OTG_HAINTMSK_HAINTM_Pos)
     
    #define USB_OTG_HAINTMSK_HAINTM   USB_OTG_HAINTMSK_HAINTM_Msk
     
    #define USB_OTG_GRXSTSP_EPNUM_Pos   (0U)
     
    #define USB_OTG_GRXSTSP_EPNUM_Msk   (0xFUL << USB_OTG_GRXSTSP_EPNUM_Pos)
     
    #define USB_OTG_GRXSTSP_EPNUM   USB_OTG_GRXSTSP_EPNUM_Msk
     
    #define USB_OTG_GRXSTSP_BCNT_Pos   (4U)
     
    #define USB_OTG_GRXSTSP_BCNT_Msk   (0x7FFUL << USB_OTG_GRXSTSP_BCNT_Pos)
     
    #define USB_OTG_GRXSTSP_BCNT   USB_OTG_GRXSTSP_BCNT_Msk
     
    #define USB_OTG_GRXSTSP_DPID_Pos   (15U)
     
    #define USB_OTG_GRXSTSP_DPID_Msk   (0x3UL << USB_OTG_GRXSTSP_DPID_Pos)
     
    #define USB_OTG_GRXSTSP_DPID   USB_OTG_GRXSTSP_DPID_Msk
     
    #define USB_OTG_GRXSTSP_PKTSTS_Pos   (17U)
     
    #define USB_OTG_GRXSTSP_PKTSTS_Msk   (0xFUL << USB_OTG_GRXSTSP_PKTSTS_Pos)
     
    #define USB_OTG_GRXSTSP_PKTSTS   USB_OTG_GRXSTSP_PKTSTS_Msk
     
    #define USB_OTG_DAINTMSK_IEPM_Pos   (0U)
     
    #define USB_OTG_DAINTMSK_IEPM_Msk   (0xFFFFUL << USB_OTG_DAINTMSK_IEPM_Pos)
     
    #define USB_OTG_DAINTMSK_IEPM   USB_OTG_DAINTMSK_IEPM_Msk
     
    #define USB_OTG_DAINTMSK_OEPM_Pos   (16U)
     
    #define USB_OTG_DAINTMSK_OEPM_Msk   (0xFFFFUL << USB_OTG_DAINTMSK_OEPM_Pos)
     
    #define USB_OTG_DAINTMSK_OEPM   USB_OTG_DAINTMSK_OEPM_Msk
     
    #define USB_OTG_GRXFSIZ_RXFD_Pos   (0U)
     
    #define USB_OTG_GRXFSIZ_RXFD_Msk   (0xFFFFUL << USB_OTG_GRXFSIZ_RXFD_Pos)
     
    #define USB_OTG_GRXFSIZ_RXFD   USB_OTG_GRXFSIZ_RXFD_Msk
     
    #define USB_OTG_DVBUSDIS_VBUSDT_Pos   (0U)
     
    #define USB_OTG_DVBUSDIS_VBUSDT_Msk   (0xFFFFUL << USB_OTG_DVBUSDIS_VBUSDT_Pos)
     
    #define USB_OTG_DVBUSDIS_VBUSDT   USB_OTG_DVBUSDIS_VBUSDT_Msk
     
    #define USB_OTG_NPTXFSA_Pos   (0U)
     
    #define USB_OTG_NPTXFSA_Msk   (0xFFFFUL << USB_OTG_NPTXFSA_Pos)
     
    #define USB_OTG_NPTXFSA   USB_OTG_NPTXFSA_Msk
     
    #define USB_OTG_NPTXFD_Pos   (16U)
     
    #define USB_OTG_NPTXFD_Msk   (0xFFFFUL << USB_OTG_NPTXFD_Pos)
     
    #define USB_OTG_NPTXFD   USB_OTG_NPTXFD_Msk
     
    #define USB_OTG_TX0FSA_Pos   (0U)
     
    #define USB_OTG_TX0FSA_Msk   (0xFFFFUL << USB_OTG_TX0FSA_Pos)
     
    #define USB_OTG_TX0FSA   USB_OTG_TX0FSA_Msk
     
    #define USB_OTG_TX0FD_Pos   (16U)
     
    #define USB_OTG_TX0FD_Msk   (0xFFFFUL << USB_OTG_TX0FD_Pos)
     
    #define USB_OTG_TX0FD   USB_OTG_TX0FD_Msk
     
    #define USB_OTG_DVBUSPULSE_DVBUSP_Pos   (0U)
     
    #define USB_OTG_DVBUSPULSE_DVBUSP_Msk   (0xFFFUL << USB_OTG_DVBUSPULSE_DVBUSP_Pos)
     
    #define USB_OTG_DVBUSPULSE_DVBUSP   USB_OTG_DVBUSPULSE_DVBUSP_Msk
     
    #define USB_OTG_GNPTXSTS_NPTXFSAV_Pos   (0U)
     
    #define USB_OTG_GNPTXSTS_NPTXFSAV_Msk   (0xFFFFUL << USB_OTG_GNPTXSTS_NPTXFSAV_Pos)
     
    #define USB_OTG_GNPTXSTS_NPTXFSAV   USB_OTG_GNPTXSTS_NPTXFSAV_Msk
     
    #define USB_OTG_GNPTXSTS_NPTQXSAV_Pos   (16U)
     
    #define USB_OTG_GNPTXSTS_NPTQXSAV_Msk   (0xFFUL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
     
    #define USB_OTG_GNPTXSTS_NPTQXSAV   USB_OTG_GNPTXSTS_NPTQXSAV_Msk
     
    #define USB_OTG_GNPTXSTS_NPTQXSAV_0   (0x01UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
     
    #define USB_OTG_GNPTXSTS_NPTQXSAV_1   (0x02UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
     
    #define USB_OTG_GNPTXSTS_NPTQXSAV_2   (0x04UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
     
    #define USB_OTG_GNPTXSTS_NPTQXSAV_3   (0x08UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
     
    #define USB_OTG_GNPTXSTS_NPTQXSAV_4   (0x10UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
     
    #define USB_OTG_GNPTXSTS_NPTQXSAV_5   (0x20UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
     
    #define USB_OTG_GNPTXSTS_NPTQXSAV_6   (0x40UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
     
    #define USB_OTG_GNPTXSTS_NPTQXSAV_7   (0x80UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
     
    #define USB_OTG_GNPTXSTS_NPTXQTOP_Pos   (24U)
     
    #define USB_OTG_GNPTXSTS_NPTXQTOP_Msk   (0x7FUL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
     
    #define USB_OTG_GNPTXSTS_NPTXQTOP   USB_OTG_GNPTXSTS_NPTXQTOP_Msk
     
    #define USB_OTG_GNPTXSTS_NPTXQTOP_0   (0x01UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
     
    #define USB_OTG_GNPTXSTS_NPTXQTOP_1   (0x02UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
     
    #define USB_OTG_GNPTXSTS_NPTXQTOP_2   (0x04UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
     
    #define USB_OTG_GNPTXSTS_NPTXQTOP_3   (0x08UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
     
    #define USB_OTG_GNPTXSTS_NPTXQTOP_4   (0x10UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
     
    #define USB_OTG_GNPTXSTS_NPTXQTOP_5   (0x20UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
     
    #define USB_OTG_GNPTXSTS_NPTXQTOP_6   (0x40UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
     
    #define USB_OTG_DTHRCTL_NONISOTHREN_Pos   (0U)
     
    #define USB_OTG_DTHRCTL_NONISOTHREN_Msk   (0x1UL << USB_OTG_DTHRCTL_NONISOTHREN_Pos)
     
    #define USB_OTG_DTHRCTL_NONISOTHREN   USB_OTG_DTHRCTL_NONISOTHREN_Msk
     
    #define USB_OTG_DTHRCTL_ISOTHREN_Pos   (1U)
     
    #define USB_OTG_DTHRCTL_ISOTHREN_Msk   (0x1UL << USB_OTG_DTHRCTL_ISOTHREN_Pos)
     
    #define USB_OTG_DTHRCTL_ISOTHREN   USB_OTG_DTHRCTL_ISOTHREN_Msk
     
    #define USB_OTG_DTHRCTL_TXTHRLEN_Pos   (2U)
     
    #define USB_OTG_DTHRCTL_TXTHRLEN_Msk   (0x1FFUL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
     
    #define USB_OTG_DTHRCTL_TXTHRLEN   USB_OTG_DTHRCTL_TXTHRLEN_Msk
     
    #define USB_OTG_DTHRCTL_TXTHRLEN_0   (0x001UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
     
    #define USB_OTG_DTHRCTL_TXTHRLEN_1   (0x002UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
     
    #define USB_OTG_DTHRCTL_TXTHRLEN_2   (0x004UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
     
    #define USB_OTG_DTHRCTL_TXTHRLEN_3   (0x008UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
     
    #define USB_OTG_DTHRCTL_TXTHRLEN_4   (0x010UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
     
    #define USB_OTG_DTHRCTL_TXTHRLEN_5   (0x020UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
     
    #define USB_OTG_DTHRCTL_TXTHRLEN_6   (0x040UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
     
    #define USB_OTG_DTHRCTL_TXTHRLEN_7   (0x080UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
     
    #define USB_OTG_DTHRCTL_TXTHRLEN_8   (0x100UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
     
    #define USB_OTG_DTHRCTL_RXTHREN_Pos   (16U)
     
    #define USB_OTG_DTHRCTL_RXTHREN_Msk   (0x1UL << USB_OTG_DTHRCTL_RXTHREN_Pos)
     
    #define USB_OTG_DTHRCTL_RXTHREN   USB_OTG_DTHRCTL_RXTHREN_Msk
     
    #define USB_OTG_DTHRCTL_RXTHRLEN_Pos   (17U)
     
    #define USB_OTG_DTHRCTL_RXTHRLEN_Msk   (0x1FFUL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
     
    #define USB_OTG_DTHRCTL_RXTHRLEN   USB_OTG_DTHRCTL_RXTHRLEN_Msk
     
    #define USB_OTG_DTHRCTL_RXTHRLEN_0   (0x001UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
     
    #define USB_OTG_DTHRCTL_RXTHRLEN_1   (0x002UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
     
    #define USB_OTG_DTHRCTL_RXTHRLEN_2   (0x004UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
     
    #define USB_OTG_DTHRCTL_RXTHRLEN_3   (0x008UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
     
    #define USB_OTG_DTHRCTL_RXTHRLEN_4   (0x010UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
     
    #define USB_OTG_DTHRCTL_RXTHRLEN_5   (0x020UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
     
    #define USB_OTG_DTHRCTL_RXTHRLEN_6   (0x040UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
     
    #define USB_OTG_DTHRCTL_RXTHRLEN_7   (0x080UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
     
    #define USB_OTG_DTHRCTL_RXTHRLEN_8   (0x100UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
     
    #define USB_OTG_DTHRCTL_ARPEN_Pos   (27U)
     
    #define USB_OTG_DTHRCTL_ARPEN_Msk   (0x1UL << USB_OTG_DTHRCTL_ARPEN_Pos)
     
    #define USB_OTG_DTHRCTL_ARPEN   USB_OTG_DTHRCTL_ARPEN_Msk
     
    #define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos   (0U)
     
    #define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk   (0xFFFFUL << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos)
     
    #define USB_OTG_DIEPEMPMSK_INEPTXFEM   USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk
     
    #define USB_OTG_DEACHINT_IEP1INT_Pos   (1U)
     
    #define USB_OTG_DEACHINT_IEP1INT_Msk   (0x1UL << USB_OTG_DEACHINT_IEP1INT_Pos)
     
    #define USB_OTG_DEACHINT_IEP1INT   USB_OTG_DEACHINT_IEP1INT_Msk
     
    #define USB_OTG_DEACHINT_OEP1INT_Pos   (17U)
     
    #define USB_OTG_DEACHINT_OEP1INT_Msk   (0x1UL << USB_OTG_DEACHINT_OEP1INT_Pos)
     
    #define USB_OTG_DEACHINT_OEP1INT   USB_OTG_DEACHINT_OEP1INT_Msk
     
    #define USB_OTG_GCCFG_PWRDWN_Pos   (16U)
     
    #define USB_OTG_GCCFG_PWRDWN_Msk   (0x1UL << USB_OTG_GCCFG_PWRDWN_Pos)
     
    #define USB_OTG_GCCFG_PWRDWN   USB_OTG_GCCFG_PWRDWN_Msk
     
    #define USB_OTG_GCCFG_I2CPADEN_Pos   (17U)
     
    #define USB_OTG_GCCFG_I2CPADEN_Msk   (0x1UL << USB_OTG_GCCFG_I2CPADEN_Pos)
     
    #define USB_OTG_GCCFG_I2CPADEN   USB_OTG_GCCFG_I2CPADEN_Msk
     
    #define USB_OTG_GCCFG_VBUSASEN_Pos   (18U)
     
    #define USB_OTG_GCCFG_VBUSASEN_Msk   (0x1UL << USB_OTG_GCCFG_VBUSASEN_Pos)
     
    #define USB_OTG_GCCFG_VBUSASEN   USB_OTG_GCCFG_VBUSASEN_Msk
     
    #define USB_OTG_GCCFG_VBUSBSEN_Pos   (19U)
     
    #define USB_OTG_GCCFG_VBUSBSEN_Msk   (0x1UL << USB_OTG_GCCFG_VBUSBSEN_Pos)
     
    #define USB_OTG_GCCFG_VBUSBSEN   USB_OTG_GCCFG_VBUSBSEN_Msk
     
    #define USB_OTG_GCCFG_SOFOUTEN_Pos   (20U)
     
    #define USB_OTG_GCCFG_SOFOUTEN_Msk   (0x1UL << USB_OTG_GCCFG_SOFOUTEN_Pos)
     
    #define USB_OTG_GCCFG_SOFOUTEN   USB_OTG_GCCFG_SOFOUTEN_Msk
     
    #define USB_OTG_GCCFG_NOVBUSSENS_Pos   (21U)
     
    #define USB_OTG_GCCFG_NOVBUSSENS_Msk   (0x1UL << USB_OTG_GCCFG_NOVBUSSENS_Pos)
     
    #define USB_OTG_GCCFG_NOVBUSSENS   USB_OTG_GCCFG_NOVBUSSENS_Msk
     
    #define USB_OTG_DEACHINTMSK_IEP1INTM_Pos   (1U)
     
    #define USB_OTG_DEACHINTMSK_IEP1INTM_Msk   (0x1UL << USB_OTG_DEACHINTMSK_IEP1INTM_Pos)
     
    #define USB_OTG_DEACHINTMSK_IEP1INTM   USB_OTG_DEACHINTMSK_IEP1INTM_Msk
     
    #define USB_OTG_DEACHINTMSK_OEP1INTM_Pos   (17U)
     
    #define USB_OTG_DEACHINTMSK_OEP1INTM_Msk   (0x1UL << USB_OTG_DEACHINTMSK_OEP1INTM_Pos)
     
    #define USB_OTG_DEACHINTMSK_OEP1INTM   USB_OTG_DEACHINTMSK_OEP1INTM_Msk
     
    #define USB_OTG_CID_PRODUCT_ID_Pos   (0U)
     
    #define USB_OTG_CID_PRODUCT_ID_Msk   (0xFFFFFFFFUL << USB_OTG_CID_PRODUCT_ID_Pos)
     
    #define USB_OTG_CID_PRODUCT_ID   USB_OTG_CID_PRODUCT_ID_Msk
     
    #define USB_OTG_DIEPEACHMSK1_XFRCM_Pos   (0U)
     
    #define USB_OTG_DIEPEACHMSK1_XFRCM_Msk   (0x1UL << USB_OTG_DIEPEACHMSK1_XFRCM_Pos)
     
    #define USB_OTG_DIEPEACHMSK1_XFRCM   USB_OTG_DIEPEACHMSK1_XFRCM_Msk
     
    #define USB_OTG_DIEPEACHMSK1_EPDM_Pos   (1U)
     
    #define USB_OTG_DIEPEACHMSK1_EPDM_Msk   (0x1UL << USB_OTG_DIEPEACHMSK1_EPDM_Pos)
     
    #define USB_OTG_DIEPEACHMSK1_EPDM   USB_OTG_DIEPEACHMSK1_EPDM_Msk
     
    #define USB_OTG_DIEPEACHMSK1_TOM_Pos   (3U)
     
    #define USB_OTG_DIEPEACHMSK1_TOM_Msk   (0x1UL << USB_OTG_DIEPEACHMSK1_TOM_Pos)
     
    #define USB_OTG_DIEPEACHMSK1_TOM   USB_OTG_DIEPEACHMSK1_TOM_Msk
     
    #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos   (4U)
     
    #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk   (0x1UL << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos)
     
    #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK   USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk
     
    #define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos   (5U)
     
    #define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk   (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos)
     
    #define USB_OTG_DIEPEACHMSK1_INEPNMM   USB_OTG_DIEPEACHMSK1_INEPNMM_Msk
     
    #define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos   (6U)
     
    #define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk   (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos)
     
    #define USB_OTG_DIEPEACHMSK1_INEPNEM   USB_OTG_DIEPEACHMSK1_INEPNEM_Msk
     
    #define USB_OTG_DIEPEACHMSK1_TXFURM_Pos   (8U)
     
    #define USB_OTG_DIEPEACHMSK1_TXFURM_Msk   (0x1UL << USB_OTG_DIEPEACHMSK1_TXFURM_Pos)
     
    #define USB_OTG_DIEPEACHMSK1_TXFURM   USB_OTG_DIEPEACHMSK1_TXFURM_Msk
     
    #define USB_OTG_DIEPEACHMSK1_BIM_Pos   (9U)
     
    #define USB_OTG_DIEPEACHMSK1_BIM_Msk   (0x1UL << USB_OTG_DIEPEACHMSK1_BIM_Pos)
     
    #define USB_OTG_DIEPEACHMSK1_BIM   USB_OTG_DIEPEACHMSK1_BIM_Msk
     
    #define USB_OTG_DIEPEACHMSK1_NAKM_Pos   (13U)
     
    #define USB_OTG_DIEPEACHMSK1_NAKM_Msk   (0x1UL << USB_OTG_DIEPEACHMSK1_NAKM_Pos)
     
    #define USB_OTG_DIEPEACHMSK1_NAKM   USB_OTG_DIEPEACHMSK1_NAKM_Msk
     
    #define USB_OTG_HPRT_PCSTS_Pos   (0U)
     
    #define USB_OTG_HPRT_PCSTS_Msk   (0x1UL << USB_OTG_HPRT_PCSTS_Pos)
     
    #define USB_OTG_HPRT_PCSTS   USB_OTG_HPRT_PCSTS_Msk
     
    #define USB_OTG_HPRT_PCDET_Pos   (1U)
     
    #define USB_OTG_HPRT_PCDET_Msk   (0x1UL << USB_OTG_HPRT_PCDET_Pos)
     
    #define USB_OTG_HPRT_PCDET   USB_OTG_HPRT_PCDET_Msk
     
    #define USB_OTG_HPRT_PENA_Pos   (2U)
     
    #define USB_OTG_HPRT_PENA_Msk   (0x1UL << USB_OTG_HPRT_PENA_Pos)
     
    #define USB_OTG_HPRT_PENA   USB_OTG_HPRT_PENA_Msk
     
    #define USB_OTG_HPRT_PENCHNG_Pos   (3U)
     
    #define USB_OTG_HPRT_PENCHNG_Msk   (0x1UL << USB_OTG_HPRT_PENCHNG_Pos)
     
    #define USB_OTG_HPRT_PENCHNG   USB_OTG_HPRT_PENCHNG_Msk
     
    #define USB_OTG_HPRT_POCA_Pos   (4U)
     
    #define USB_OTG_HPRT_POCA_Msk   (0x1UL << USB_OTG_HPRT_POCA_Pos)
     
    #define USB_OTG_HPRT_POCA   USB_OTG_HPRT_POCA_Msk
     
    #define USB_OTG_HPRT_POCCHNG_Pos   (5U)
     
    #define USB_OTG_HPRT_POCCHNG_Msk   (0x1UL << USB_OTG_HPRT_POCCHNG_Pos)
     
    #define USB_OTG_HPRT_POCCHNG   USB_OTG_HPRT_POCCHNG_Msk
     
    #define USB_OTG_HPRT_PRES_Pos   (6U)
     
    #define USB_OTG_HPRT_PRES_Msk   (0x1UL << USB_OTG_HPRT_PRES_Pos)
     
    #define USB_OTG_HPRT_PRES   USB_OTG_HPRT_PRES_Msk
     
    #define USB_OTG_HPRT_PSUSP_Pos   (7U)
     
    #define USB_OTG_HPRT_PSUSP_Msk   (0x1UL << USB_OTG_HPRT_PSUSP_Pos)
     
    #define USB_OTG_HPRT_PSUSP   USB_OTG_HPRT_PSUSP_Msk
     
    #define USB_OTG_HPRT_PRST_Pos   (8U)
     
    #define USB_OTG_HPRT_PRST_Msk   (0x1UL << USB_OTG_HPRT_PRST_Pos)
     
    #define USB_OTG_HPRT_PRST   USB_OTG_HPRT_PRST_Msk
     
    #define USB_OTG_HPRT_PLSTS_Pos   (10U)
     
    #define USB_OTG_HPRT_PLSTS_Msk   (0x3UL << USB_OTG_HPRT_PLSTS_Pos)
     
    #define USB_OTG_HPRT_PLSTS   USB_OTG_HPRT_PLSTS_Msk
     
    #define USB_OTG_HPRT_PLSTS_0   (0x1UL << USB_OTG_HPRT_PLSTS_Pos)
     
    #define USB_OTG_HPRT_PLSTS_1   (0x2UL << USB_OTG_HPRT_PLSTS_Pos)
     
    #define USB_OTG_HPRT_PPWR_Pos   (12U)
     
    #define USB_OTG_HPRT_PPWR_Msk   (0x1UL << USB_OTG_HPRT_PPWR_Pos)
     
    #define USB_OTG_HPRT_PPWR   USB_OTG_HPRT_PPWR_Msk
     
    #define USB_OTG_HPRT_PTCTL_Pos   (13U)
     
    #define USB_OTG_HPRT_PTCTL_Msk   (0xFUL << USB_OTG_HPRT_PTCTL_Pos)
     
    #define USB_OTG_HPRT_PTCTL   USB_OTG_HPRT_PTCTL_Msk
     
    #define USB_OTG_HPRT_PTCTL_0   (0x1UL << USB_OTG_HPRT_PTCTL_Pos)
     
    #define USB_OTG_HPRT_PTCTL_1   (0x2UL << USB_OTG_HPRT_PTCTL_Pos)
     
    #define USB_OTG_HPRT_PTCTL_2   (0x4UL << USB_OTG_HPRT_PTCTL_Pos)
     
    #define USB_OTG_HPRT_PTCTL_3   (0x8UL << USB_OTG_HPRT_PTCTL_Pos)
     
    #define USB_OTG_HPRT_PSPD_Pos   (17U)
     
    #define USB_OTG_HPRT_PSPD_Msk   (0x3UL << USB_OTG_HPRT_PSPD_Pos)
     
    #define USB_OTG_HPRT_PSPD   USB_OTG_HPRT_PSPD_Msk
     
    #define USB_OTG_HPRT_PSPD_0   (0x1UL << USB_OTG_HPRT_PSPD_Pos)
     
    #define USB_OTG_HPRT_PSPD_1   (0x2UL << USB_OTG_HPRT_PSPD_Pos)
     
    #define USB_OTG_DOEPEACHMSK1_XFRCM_Pos   (0U)
     
    #define USB_OTG_DOEPEACHMSK1_XFRCM_Msk   (0x1UL << USB_OTG_DOEPEACHMSK1_XFRCM_Pos)
     
    #define USB_OTG_DOEPEACHMSK1_XFRCM   USB_OTG_DOEPEACHMSK1_XFRCM_Msk
     
    #define USB_OTG_DOEPEACHMSK1_EPDM_Pos   (1U)
     
    #define USB_OTG_DOEPEACHMSK1_EPDM_Msk   (0x1UL << USB_OTG_DOEPEACHMSK1_EPDM_Pos)
     
    #define USB_OTG_DOEPEACHMSK1_EPDM   USB_OTG_DOEPEACHMSK1_EPDM_Msk
     
    #define USB_OTG_DOEPEACHMSK1_TOM_Pos   (3U)
     
    #define USB_OTG_DOEPEACHMSK1_TOM_Msk   (0x1UL << USB_OTG_DOEPEACHMSK1_TOM_Pos)
     
    #define USB_OTG_DOEPEACHMSK1_TOM   USB_OTG_DOEPEACHMSK1_TOM_Msk
     
    #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos   (4U)
     
    #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk   (0x1UL << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos)
     
    #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK   USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk
     
    #define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos   (5U)
     
    #define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk   (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos)
     
    #define USB_OTG_DOEPEACHMSK1_INEPNMM   USB_OTG_DOEPEACHMSK1_INEPNMM_Msk
     
    #define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos   (6U)
     
    #define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk   (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos)
     
    #define USB_OTG_DOEPEACHMSK1_INEPNEM   USB_OTG_DOEPEACHMSK1_INEPNEM_Msk
     
    #define USB_OTG_DOEPEACHMSK1_TXFURM_Pos   (8U)
     
    #define USB_OTG_DOEPEACHMSK1_TXFURM_Msk   (0x1UL << USB_OTG_DOEPEACHMSK1_TXFURM_Pos)
     
    #define USB_OTG_DOEPEACHMSK1_TXFURM   USB_OTG_DOEPEACHMSK1_TXFURM_Msk
     
    #define USB_OTG_DOEPEACHMSK1_BIM_Pos   (9U)
     
    #define USB_OTG_DOEPEACHMSK1_BIM_Msk   (0x1UL << USB_OTG_DOEPEACHMSK1_BIM_Pos)
     
    #define USB_OTG_DOEPEACHMSK1_BIM   USB_OTG_DOEPEACHMSK1_BIM_Msk
     
    #define USB_OTG_DOEPEACHMSK1_BERRM_Pos   (12U)
     
    #define USB_OTG_DOEPEACHMSK1_BERRM_Msk   (0x1UL << USB_OTG_DOEPEACHMSK1_BERRM_Pos)
     
    #define USB_OTG_DOEPEACHMSK1_BERRM   USB_OTG_DOEPEACHMSK1_BERRM_Msk
     
    #define USB_OTG_DOEPEACHMSK1_NAKM_Pos   (13U)
     
    #define USB_OTG_DOEPEACHMSK1_NAKM_Msk   (0x1UL << USB_OTG_DOEPEACHMSK1_NAKM_Pos)
     
    #define USB_OTG_DOEPEACHMSK1_NAKM   USB_OTG_DOEPEACHMSK1_NAKM_Msk
     
    #define USB_OTG_DOEPEACHMSK1_NYETM_Pos   (14U)
     
    #define USB_OTG_DOEPEACHMSK1_NYETM_Msk   (0x1UL << USB_OTG_DOEPEACHMSK1_NYETM_Pos)
     
    #define USB_OTG_DOEPEACHMSK1_NYETM   USB_OTG_DOEPEACHMSK1_NYETM_Msk
     
    #define USB_OTG_HPTXFSIZ_PTXSA_Pos   (0U)
     
    #define USB_OTG_HPTXFSIZ_PTXSA_Msk   (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXSA_Pos)
     
    #define USB_OTG_HPTXFSIZ_PTXSA   USB_OTG_HPTXFSIZ_PTXSA_Msk
     
    #define USB_OTG_HPTXFSIZ_PTXFD_Pos   (16U)
     
    #define USB_OTG_HPTXFSIZ_PTXFD_Msk   (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXFD_Pos)
     
    #define USB_OTG_HPTXFSIZ_PTXFD   USB_OTG_HPTXFSIZ_PTXFD_Msk
     
    #define USB_OTG_DIEPCTL_MPSIZ_Pos   (0U)
     
    #define USB_OTG_DIEPCTL_MPSIZ_Msk   (0x7FFUL << USB_OTG_DIEPCTL_MPSIZ_Pos)
     
    #define USB_OTG_DIEPCTL_MPSIZ   USB_OTG_DIEPCTL_MPSIZ_Msk
     
    #define USB_OTG_DIEPCTL_USBAEP_Pos   (15U)
     
    #define USB_OTG_DIEPCTL_USBAEP_Msk   (0x1UL << USB_OTG_DIEPCTL_USBAEP_Pos)
     
    #define USB_OTG_DIEPCTL_USBAEP   USB_OTG_DIEPCTL_USBAEP_Msk
     
    #define USB_OTG_DIEPCTL_EONUM_DPID_Pos   (16U)
     
    #define USB_OTG_DIEPCTL_EONUM_DPID_Msk   (0x1UL << USB_OTG_DIEPCTL_EONUM_DPID_Pos)
     
    #define USB_OTG_DIEPCTL_EONUM_DPID   USB_OTG_DIEPCTL_EONUM_DPID_Msk
     
    #define USB_OTG_DIEPCTL_NAKSTS_Pos   (17U)
     
    #define USB_OTG_DIEPCTL_NAKSTS_Msk   (0x1UL << USB_OTG_DIEPCTL_NAKSTS_Pos)
     
    #define USB_OTG_DIEPCTL_NAKSTS   USB_OTG_DIEPCTL_NAKSTS_Msk
     
    #define USB_OTG_DIEPCTL_EPTYP_Pos   (18U)
     
    #define USB_OTG_DIEPCTL_EPTYP_Msk   (0x3UL << USB_OTG_DIEPCTL_EPTYP_Pos)
     
    #define USB_OTG_DIEPCTL_EPTYP   USB_OTG_DIEPCTL_EPTYP_Msk
     
    #define USB_OTG_DIEPCTL_EPTYP_0   (0x1UL << USB_OTG_DIEPCTL_EPTYP_Pos)
     
    #define USB_OTG_DIEPCTL_EPTYP_1   (0x2UL << USB_OTG_DIEPCTL_EPTYP_Pos)
     
    #define USB_OTG_DIEPCTL_STALL_Pos   (21U)
     
    #define USB_OTG_DIEPCTL_STALL_Msk   (0x1UL << USB_OTG_DIEPCTL_STALL_Pos)
     
    #define USB_OTG_DIEPCTL_STALL   USB_OTG_DIEPCTL_STALL_Msk
     
    #define USB_OTG_DIEPCTL_TXFNUM_Pos   (22U)
     
    #define USB_OTG_DIEPCTL_TXFNUM_Msk   (0xFUL << USB_OTG_DIEPCTL_TXFNUM_Pos)
     
    #define USB_OTG_DIEPCTL_TXFNUM   USB_OTG_DIEPCTL_TXFNUM_Msk
     
    #define USB_OTG_DIEPCTL_TXFNUM_0   (0x1UL << USB_OTG_DIEPCTL_TXFNUM_Pos)
     
    #define USB_OTG_DIEPCTL_TXFNUM_1   (0x2UL << USB_OTG_DIEPCTL_TXFNUM_Pos)
     
    #define USB_OTG_DIEPCTL_TXFNUM_2   (0x4UL << USB_OTG_DIEPCTL_TXFNUM_Pos)
     
    #define USB_OTG_DIEPCTL_TXFNUM_3   (0x8UL << USB_OTG_DIEPCTL_TXFNUM_Pos)
     
    #define USB_OTG_DIEPCTL_CNAK_Pos   (26U)
     
    #define USB_OTG_DIEPCTL_CNAK_Msk   (0x1UL << USB_OTG_DIEPCTL_CNAK_Pos)
     
    #define USB_OTG_DIEPCTL_CNAK   USB_OTG_DIEPCTL_CNAK_Msk
     
    #define USB_OTG_DIEPCTL_SNAK_Pos   (27U)
     
    #define USB_OTG_DIEPCTL_SNAK_Msk   (0x1UL << USB_OTG_DIEPCTL_SNAK_Pos)
     
    #define USB_OTG_DIEPCTL_SNAK   USB_OTG_DIEPCTL_SNAK_Msk
     
    #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos   (28U)
     
    #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk   (0x1UL << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos)
     
    #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM   USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk
     
    #define USB_OTG_DIEPCTL_SODDFRM_Pos   (29U)
     
    #define USB_OTG_DIEPCTL_SODDFRM_Msk   (0x1UL << USB_OTG_DIEPCTL_SODDFRM_Pos)
     
    #define USB_OTG_DIEPCTL_SODDFRM   USB_OTG_DIEPCTL_SODDFRM_Msk
     
    #define USB_OTG_DIEPCTL_EPDIS_Pos   (30U)
     
    #define USB_OTG_DIEPCTL_EPDIS_Msk   (0x1UL << USB_OTG_DIEPCTL_EPDIS_Pos)
     
    #define USB_OTG_DIEPCTL_EPDIS   USB_OTG_DIEPCTL_EPDIS_Msk
     
    #define USB_OTG_DIEPCTL_EPENA_Pos   (31U)
     
    #define USB_OTG_DIEPCTL_EPENA_Msk   (0x1UL << USB_OTG_DIEPCTL_EPENA_Pos)
     
    #define USB_OTG_DIEPCTL_EPENA   USB_OTG_DIEPCTL_EPENA_Msk
     
    #define USB_OTG_HCCHAR_MPSIZ_Pos   (0U)
     
    #define USB_OTG_HCCHAR_MPSIZ_Msk   (0x7FFUL << USB_OTG_HCCHAR_MPSIZ_Pos)
     
    #define USB_OTG_HCCHAR_MPSIZ   USB_OTG_HCCHAR_MPSIZ_Msk
     
    #define USB_OTG_HCCHAR_EPNUM_Pos   (11U)
     
    #define USB_OTG_HCCHAR_EPNUM_Msk   (0xFUL << USB_OTG_HCCHAR_EPNUM_Pos)
     
    #define USB_OTG_HCCHAR_EPNUM   USB_OTG_HCCHAR_EPNUM_Msk
     
    #define USB_OTG_HCCHAR_EPNUM_0   (0x1UL << USB_OTG_HCCHAR_EPNUM_Pos)
     
    #define USB_OTG_HCCHAR_EPNUM_1   (0x2UL << USB_OTG_HCCHAR_EPNUM_Pos)
     
    #define USB_OTG_HCCHAR_EPNUM_2   (0x4UL << USB_OTG_HCCHAR_EPNUM_Pos)
     
    #define USB_OTG_HCCHAR_EPNUM_3   (0x8UL << USB_OTG_HCCHAR_EPNUM_Pos)
     
    #define USB_OTG_HCCHAR_EPDIR_Pos   (15U)
     
    #define USB_OTG_HCCHAR_EPDIR_Msk   (0x1UL << USB_OTG_HCCHAR_EPDIR_Pos)
     
    #define USB_OTG_HCCHAR_EPDIR   USB_OTG_HCCHAR_EPDIR_Msk
     
    #define USB_OTG_HCCHAR_LSDEV_Pos   (17U)
     
    #define USB_OTG_HCCHAR_LSDEV_Msk   (0x1UL << USB_OTG_HCCHAR_LSDEV_Pos)
     
    #define USB_OTG_HCCHAR_LSDEV   USB_OTG_HCCHAR_LSDEV_Msk
     
    #define USB_OTG_HCCHAR_EPTYP_Pos   (18U)
     
    #define USB_OTG_HCCHAR_EPTYP_Msk   (0x3UL << USB_OTG_HCCHAR_EPTYP_Pos)
     
    #define USB_OTG_HCCHAR_EPTYP   USB_OTG_HCCHAR_EPTYP_Msk
     
    #define USB_OTG_HCCHAR_EPTYP_0   (0x1UL << USB_OTG_HCCHAR_EPTYP_Pos)
     
    #define USB_OTG_HCCHAR_EPTYP_1   (0x2UL << USB_OTG_HCCHAR_EPTYP_Pos)
     
    #define USB_OTG_HCCHAR_MC_Pos   (20U)
     
    #define USB_OTG_HCCHAR_MC_Msk   (0x3UL << USB_OTG_HCCHAR_MC_Pos)
     
    #define USB_OTG_HCCHAR_MC   USB_OTG_HCCHAR_MC_Msk
     
    #define USB_OTG_HCCHAR_MC_0   (0x1UL << USB_OTG_HCCHAR_MC_Pos)
     
    #define USB_OTG_HCCHAR_MC_1   (0x2UL << USB_OTG_HCCHAR_MC_Pos)
     
    #define USB_OTG_HCCHAR_DAD_Pos   (22U)
     
    #define USB_OTG_HCCHAR_DAD_Msk   (0x7FUL << USB_OTG_HCCHAR_DAD_Pos)
     
    #define USB_OTG_HCCHAR_DAD   USB_OTG_HCCHAR_DAD_Msk
     
    #define USB_OTG_HCCHAR_DAD_0   (0x01UL << USB_OTG_HCCHAR_DAD_Pos)
     
    #define USB_OTG_HCCHAR_DAD_1   (0x02UL << USB_OTG_HCCHAR_DAD_Pos)
     
    #define USB_OTG_HCCHAR_DAD_2   (0x04UL << USB_OTG_HCCHAR_DAD_Pos)
     
    #define USB_OTG_HCCHAR_DAD_3   (0x08UL << USB_OTG_HCCHAR_DAD_Pos)
     
    #define USB_OTG_HCCHAR_DAD_4   (0x10UL << USB_OTG_HCCHAR_DAD_Pos)
     
    #define USB_OTG_HCCHAR_DAD_5   (0x20UL << USB_OTG_HCCHAR_DAD_Pos)
     
    #define USB_OTG_HCCHAR_DAD_6   (0x40UL << USB_OTG_HCCHAR_DAD_Pos)
     
    #define USB_OTG_HCCHAR_ODDFRM_Pos   (29U)
     
    #define USB_OTG_HCCHAR_ODDFRM_Msk   (0x1UL << USB_OTG_HCCHAR_ODDFRM_Pos)
     
    #define USB_OTG_HCCHAR_ODDFRM   USB_OTG_HCCHAR_ODDFRM_Msk
     
    #define USB_OTG_HCCHAR_CHDIS_Pos   (30U)
     
    #define USB_OTG_HCCHAR_CHDIS_Msk   (0x1UL << USB_OTG_HCCHAR_CHDIS_Pos)
     
    #define USB_OTG_HCCHAR_CHDIS   USB_OTG_HCCHAR_CHDIS_Msk
     
    #define USB_OTG_HCCHAR_CHENA_Pos   (31U)
     
    #define USB_OTG_HCCHAR_CHENA_Msk   (0x1UL << USB_OTG_HCCHAR_CHENA_Pos)
     
    #define USB_OTG_HCCHAR_CHENA   USB_OTG_HCCHAR_CHENA_Msk
     
    #define USB_OTG_HCSPLT_PRTADDR_Pos   (0U)
     
    #define USB_OTG_HCSPLT_PRTADDR_Msk   (0x7FUL << USB_OTG_HCSPLT_PRTADDR_Pos)
     
    #define USB_OTG_HCSPLT_PRTADDR   USB_OTG_HCSPLT_PRTADDR_Msk
     
    #define USB_OTG_HCSPLT_PRTADDR_0   (0x01UL << USB_OTG_HCSPLT_PRTADDR_Pos)
     
    #define USB_OTG_HCSPLT_PRTADDR_1   (0x02UL << USB_OTG_HCSPLT_PRTADDR_Pos)
     
    #define USB_OTG_HCSPLT_PRTADDR_2   (0x04UL << USB_OTG_HCSPLT_PRTADDR_Pos)
     
    #define USB_OTG_HCSPLT_PRTADDR_3   (0x08UL << USB_OTG_HCSPLT_PRTADDR_Pos)
     
    #define USB_OTG_HCSPLT_PRTADDR_4   (0x10UL << USB_OTG_HCSPLT_PRTADDR_Pos)
     
    #define USB_OTG_HCSPLT_PRTADDR_5   (0x20UL << USB_OTG_HCSPLT_PRTADDR_Pos)
     
    #define USB_OTG_HCSPLT_PRTADDR_6   (0x40UL << USB_OTG_HCSPLT_PRTADDR_Pos)
     
    #define USB_OTG_HCSPLT_HUBADDR_Pos   (7U)
     
    #define USB_OTG_HCSPLT_HUBADDR_Msk   (0x7FUL << USB_OTG_HCSPLT_HUBADDR_Pos)
     
    #define USB_OTG_HCSPLT_HUBADDR   USB_OTG_HCSPLT_HUBADDR_Msk
     
    #define USB_OTG_HCSPLT_HUBADDR_0   (0x01UL << USB_OTG_HCSPLT_HUBADDR_Pos)
     
    #define USB_OTG_HCSPLT_HUBADDR_1   (0x02UL << USB_OTG_HCSPLT_HUBADDR_Pos)
     
    #define USB_OTG_HCSPLT_HUBADDR_2   (0x04UL << USB_OTG_HCSPLT_HUBADDR_Pos)
     
    #define USB_OTG_HCSPLT_HUBADDR_3   (0x08UL << USB_OTG_HCSPLT_HUBADDR_Pos)
     
    #define USB_OTG_HCSPLT_HUBADDR_4   (0x10UL << USB_OTG_HCSPLT_HUBADDR_Pos)
     
    #define USB_OTG_HCSPLT_HUBADDR_5   (0x20UL << USB_OTG_HCSPLT_HUBADDR_Pos)
     
    #define USB_OTG_HCSPLT_HUBADDR_6   (0x40UL << USB_OTG_HCSPLT_HUBADDR_Pos)
     
    #define USB_OTG_HCSPLT_XACTPOS_Pos   (14U)
     
    #define USB_OTG_HCSPLT_XACTPOS_Msk   (0x3UL << USB_OTG_HCSPLT_XACTPOS_Pos)
     
    #define USB_OTG_HCSPLT_XACTPOS   USB_OTG_HCSPLT_XACTPOS_Msk
     
    #define USB_OTG_HCSPLT_XACTPOS_0   (0x1UL << USB_OTG_HCSPLT_XACTPOS_Pos)
     
    #define USB_OTG_HCSPLT_XACTPOS_1   (0x2UL << USB_OTG_HCSPLT_XACTPOS_Pos)
     
    #define USB_OTG_HCSPLT_COMPLSPLT_Pos   (16U)
     
    #define USB_OTG_HCSPLT_COMPLSPLT_Msk   (0x1UL << USB_OTG_HCSPLT_COMPLSPLT_Pos)
     
    #define USB_OTG_HCSPLT_COMPLSPLT   USB_OTG_HCSPLT_COMPLSPLT_Msk
     
    #define USB_OTG_HCSPLT_SPLITEN_Pos   (31U)
     
    #define USB_OTG_HCSPLT_SPLITEN_Msk   (0x1UL << USB_OTG_HCSPLT_SPLITEN_Pos)
     
    #define USB_OTG_HCSPLT_SPLITEN   USB_OTG_HCSPLT_SPLITEN_Msk
     
    #define USB_OTG_HCINT_XFRC_Pos   (0U)
     
    #define USB_OTG_HCINT_XFRC_Msk   (0x1UL << USB_OTG_HCINT_XFRC_Pos)
     
    #define USB_OTG_HCINT_XFRC   USB_OTG_HCINT_XFRC_Msk
     
    #define USB_OTG_HCINT_CHH_Pos   (1U)
     
    #define USB_OTG_HCINT_CHH_Msk   (0x1UL << USB_OTG_HCINT_CHH_Pos)
     
    #define USB_OTG_HCINT_CHH   USB_OTG_HCINT_CHH_Msk
     
    #define USB_OTG_HCINT_AHBERR_Pos   (2U)
     
    #define USB_OTG_HCINT_AHBERR_Msk   (0x1UL << USB_OTG_HCINT_AHBERR_Pos)
     
    #define USB_OTG_HCINT_AHBERR   USB_OTG_HCINT_AHBERR_Msk
     
    #define USB_OTG_HCINT_STALL_Pos   (3U)
     
    #define USB_OTG_HCINT_STALL_Msk   (0x1UL << USB_OTG_HCINT_STALL_Pos)
     
    #define USB_OTG_HCINT_STALL   USB_OTG_HCINT_STALL_Msk
     
    #define USB_OTG_HCINT_NAK_Pos   (4U)
     
    #define USB_OTG_HCINT_NAK_Msk   (0x1UL << USB_OTG_HCINT_NAK_Pos)
     
    #define USB_OTG_HCINT_NAK   USB_OTG_HCINT_NAK_Msk
     
    #define USB_OTG_HCINT_ACK_Pos   (5U)
     
    #define USB_OTG_HCINT_ACK_Msk   (0x1UL << USB_OTG_HCINT_ACK_Pos)
     
    #define USB_OTG_HCINT_ACK   USB_OTG_HCINT_ACK_Msk
     
    #define USB_OTG_HCINT_NYET_Pos   (6U)
     
    #define USB_OTG_HCINT_NYET_Msk   (0x1UL << USB_OTG_HCINT_NYET_Pos)
     
    #define USB_OTG_HCINT_NYET   USB_OTG_HCINT_NYET_Msk
     
    #define USB_OTG_HCINT_TXERR_Pos   (7U)
     
    #define USB_OTG_HCINT_TXERR_Msk   (0x1UL << USB_OTG_HCINT_TXERR_Pos)
     
    #define USB_OTG_HCINT_TXERR   USB_OTG_HCINT_TXERR_Msk
     
    #define USB_OTG_HCINT_BBERR_Pos   (8U)
     
    #define USB_OTG_HCINT_BBERR_Msk   (0x1UL << USB_OTG_HCINT_BBERR_Pos)
     
    #define USB_OTG_HCINT_BBERR   USB_OTG_HCINT_BBERR_Msk
     
    #define USB_OTG_HCINT_FRMOR_Pos   (9U)
     
    #define USB_OTG_HCINT_FRMOR_Msk   (0x1UL << USB_OTG_HCINT_FRMOR_Pos)
     
    #define USB_OTG_HCINT_FRMOR   USB_OTG_HCINT_FRMOR_Msk
     
    #define USB_OTG_HCINT_DTERR_Pos   (10U)
     
    #define USB_OTG_HCINT_DTERR_Msk   (0x1UL << USB_OTG_HCINT_DTERR_Pos)
     
    #define USB_OTG_HCINT_DTERR   USB_OTG_HCINT_DTERR_Msk
     
    #define USB_OTG_DIEPINT_XFRC_Pos   (0U)
     
    #define USB_OTG_DIEPINT_XFRC_Msk   (0x1UL << USB_OTG_DIEPINT_XFRC_Pos)
     
    #define USB_OTG_DIEPINT_XFRC   USB_OTG_DIEPINT_XFRC_Msk
     
    #define USB_OTG_DIEPINT_EPDISD_Pos   (1U)
     
    #define USB_OTG_DIEPINT_EPDISD_Msk   (0x1UL << USB_OTG_DIEPINT_EPDISD_Pos)
     
    #define USB_OTG_DIEPINT_EPDISD   USB_OTG_DIEPINT_EPDISD_Msk
     
    #define USB_OTG_DIEPINT_AHBERR_Pos   (2U)
     
    #define USB_OTG_DIEPINT_AHBERR_Msk   (0x1UL << USB_OTG_DIEPINT_AHBERR_Pos)
     
    #define USB_OTG_DIEPINT_AHBERR   USB_OTG_DIEPINT_AHBERR_Msk
     
    #define USB_OTG_DIEPINT_TOC_Pos   (3U)
     
    #define USB_OTG_DIEPINT_TOC_Msk   (0x1UL << USB_OTG_DIEPINT_TOC_Pos)
     
    #define USB_OTG_DIEPINT_TOC   USB_OTG_DIEPINT_TOC_Msk
     
    #define USB_OTG_DIEPINT_ITTXFE_Pos   (4U)
     
    #define USB_OTG_DIEPINT_ITTXFE_Msk   (0x1UL << USB_OTG_DIEPINT_ITTXFE_Pos)
     
    #define USB_OTG_DIEPINT_ITTXFE   USB_OTG_DIEPINT_ITTXFE_Msk
     
    #define USB_OTG_DIEPINT_INEPNM_Pos   (5U)
     
    #define USB_OTG_DIEPINT_INEPNM_Msk   (0x1UL << USB_OTG_DIEPINT_INEPNM_Pos)
     
    #define USB_OTG_DIEPINT_INEPNM   USB_OTG_DIEPINT_INEPNM_Msk
     
    #define USB_OTG_DIEPINT_INEPNE_Pos   (6U)
     
    #define USB_OTG_DIEPINT_INEPNE_Msk   (0x1UL << USB_OTG_DIEPINT_INEPNE_Pos)
     
    #define USB_OTG_DIEPINT_INEPNE   USB_OTG_DIEPINT_INEPNE_Msk
     
    #define USB_OTG_DIEPINT_TXFE_Pos   (7U)
     
    #define USB_OTG_DIEPINT_TXFE_Msk   (0x1UL << USB_OTG_DIEPINT_TXFE_Pos)
     
    #define USB_OTG_DIEPINT_TXFE   USB_OTG_DIEPINT_TXFE_Msk
     
    #define USB_OTG_DIEPINT_TXFIFOUDRN_Pos   (8U)
     
    #define USB_OTG_DIEPINT_TXFIFOUDRN_Msk   (0x1UL << USB_OTG_DIEPINT_TXFIFOUDRN_Pos)
     
    #define USB_OTG_DIEPINT_TXFIFOUDRN   USB_OTG_DIEPINT_TXFIFOUDRN_Msk
     
    #define USB_OTG_DIEPINT_BNA_Pos   (9U)
     
    #define USB_OTG_DIEPINT_BNA_Msk   (0x1UL << USB_OTG_DIEPINT_BNA_Pos)
     
    #define USB_OTG_DIEPINT_BNA   USB_OTG_DIEPINT_BNA_Msk
     
    #define USB_OTG_DIEPINT_PKTDRPSTS_Pos   (11U)
     
    #define USB_OTG_DIEPINT_PKTDRPSTS_Msk   (0x1UL << USB_OTG_DIEPINT_PKTDRPSTS_Pos)
     
    #define USB_OTG_DIEPINT_PKTDRPSTS   USB_OTG_DIEPINT_PKTDRPSTS_Msk
     
    #define USB_OTG_DIEPINT_BERR_Pos   (12U)
     
    #define USB_OTG_DIEPINT_BERR_Msk   (0x1UL << USB_OTG_DIEPINT_BERR_Pos)
     
    #define USB_OTG_DIEPINT_BERR   USB_OTG_DIEPINT_BERR_Msk
     
    #define USB_OTG_DIEPINT_NAK_Pos   (13U)
     
    #define USB_OTG_DIEPINT_NAK_Msk   (0x1UL << USB_OTG_DIEPINT_NAK_Pos)
     
    #define USB_OTG_DIEPINT_NAK   USB_OTG_DIEPINT_NAK_Msk
     
    #define USB_OTG_HCINTMSK_XFRCM_Pos   (0U)
     
    #define USB_OTG_HCINTMSK_XFRCM_Msk   (0x1UL << USB_OTG_HCINTMSK_XFRCM_Pos)
     
    #define USB_OTG_HCINTMSK_XFRCM   USB_OTG_HCINTMSK_XFRCM_Msk
     
    #define USB_OTG_HCINTMSK_CHHM_Pos   (1U)
     
    #define USB_OTG_HCINTMSK_CHHM_Msk   (0x1UL << USB_OTG_HCINTMSK_CHHM_Pos)
     
    #define USB_OTG_HCINTMSK_CHHM   USB_OTG_HCINTMSK_CHHM_Msk
     
    #define USB_OTG_HCINTMSK_AHBERR_Pos   (2U)
     
    #define USB_OTG_HCINTMSK_AHBERR_Msk   (0x1UL << USB_OTG_HCINTMSK_AHBERR_Pos)
     
    #define USB_OTG_HCINTMSK_AHBERR   USB_OTG_HCINTMSK_AHBERR_Msk
     
    #define USB_OTG_HCINTMSK_STALLM_Pos   (3U)
     
    #define USB_OTG_HCINTMSK_STALLM_Msk   (0x1UL << USB_OTG_HCINTMSK_STALLM_Pos)
     
    #define USB_OTG_HCINTMSK_STALLM   USB_OTG_HCINTMSK_STALLM_Msk
     
    #define USB_OTG_HCINTMSK_NAKM_Pos   (4U)
     
    #define USB_OTG_HCINTMSK_NAKM_Msk   (0x1UL << USB_OTG_HCINTMSK_NAKM_Pos)
     
    #define USB_OTG_HCINTMSK_NAKM   USB_OTG_HCINTMSK_NAKM_Msk
     
    #define USB_OTG_HCINTMSK_ACKM_Pos   (5U)
     
    #define USB_OTG_HCINTMSK_ACKM_Msk   (0x1UL << USB_OTG_HCINTMSK_ACKM_Pos)
     
    #define USB_OTG_HCINTMSK_ACKM   USB_OTG_HCINTMSK_ACKM_Msk
     
    #define USB_OTG_HCINTMSK_NYET_Pos   (6U)
     
    #define USB_OTG_HCINTMSK_NYET_Msk   (0x1UL << USB_OTG_HCINTMSK_NYET_Pos)
     
    #define USB_OTG_HCINTMSK_NYET   USB_OTG_HCINTMSK_NYET_Msk
     
    #define USB_OTG_HCINTMSK_TXERRM_Pos   (7U)
     
    #define USB_OTG_HCINTMSK_TXERRM_Msk   (0x1UL << USB_OTG_HCINTMSK_TXERRM_Pos)
     
    #define USB_OTG_HCINTMSK_TXERRM   USB_OTG_HCINTMSK_TXERRM_Msk
     
    #define USB_OTG_HCINTMSK_BBERRM_Pos   (8U)
     
    #define USB_OTG_HCINTMSK_BBERRM_Msk   (0x1UL << USB_OTG_HCINTMSK_BBERRM_Pos)
     
    #define USB_OTG_HCINTMSK_BBERRM   USB_OTG_HCINTMSK_BBERRM_Msk
     
    #define USB_OTG_HCINTMSK_FRMORM_Pos   (9U)
     
    #define USB_OTG_HCINTMSK_FRMORM_Msk   (0x1UL << USB_OTG_HCINTMSK_FRMORM_Pos)
     
    #define USB_OTG_HCINTMSK_FRMORM   USB_OTG_HCINTMSK_FRMORM_Msk
     
    #define USB_OTG_HCINTMSK_DTERRM_Pos   (10U)
     
    #define USB_OTG_HCINTMSK_DTERRM_Msk   (0x1UL << USB_OTG_HCINTMSK_DTERRM_Pos)
     
    #define USB_OTG_HCINTMSK_DTERRM   USB_OTG_HCINTMSK_DTERRM_Msk
     
    #define USB_OTG_DIEPTSIZ_XFRSIZ_Pos   (0U)
     
    #define USB_OTG_DIEPTSIZ_XFRSIZ_Msk   (0x7FFFFUL << USB_OTG_DIEPTSIZ_XFRSIZ_Pos)
     
    #define USB_OTG_DIEPTSIZ_XFRSIZ   USB_OTG_DIEPTSIZ_XFRSIZ_Msk
     
    #define USB_OTG_DIEPTSIZ_PKTCNT_Pos   (19U)
     
    #define USB_OTG_DIEPTSIZ_PKTCNT_Msk   (0x3FFUL << USB_OTG_DIEPTSIZ_PKTCNT_Pos)
     
    #define USB_OTG_DIEPTSIZ_PKTCNT   USB_OTG_DIEPTSIZ_PKTCNT_Msk
     
    #define USB_OTG_DIEPTSIZ_MULCNT_Pos   (29U)
     
    #define USB_OTG_DIEPTSIZ_MULCNT_Msk   (0x3UL << USB_OTG_DIEPTSIZ_MULCNT_Pos)
     
    #define USB_OTG_DIEPTSIZ_MULCNT   USB_OTG_DIEPTSIZ_MULCNT_Msk
     
    #define USB_OTG_HCTSIZ_XFRSIZ_Pos   (0U)
     
    #define USB_OTG_HCTSIZ_XFRSIZ_Msk   (0x7FFFFUL << USB_OTG_HCTSIZ_XFRSIZ_Pos)
     
    #define USB_OTG_HCTSIZ_XFRSIZ   USB_OTG_HCTSIZ_XFRSIZ_Msk
     
    #define USB_OTG_HCTSIZ_PKTCNT_Pos   (19U)
     
    #define USB_OTG_HCTSIZ_PKTCNT_Msk   (0x3FFUL << USB_OTG_HCTSIZ_PKTCNT_Pos)
     
    #define USB_OTG_HCTSIZ_PKTCNT   USB_OTG_HCTSIZ_PKTCNT_Msk
     
    #define USB_OTG_HCTSIZ_DOPING_Pos   (31U)
     
    #define USB_OTG_HCTSIZ_DOPING_Msk   (0x1UL << USB_OTG_HCTSIZ_DOPING_Pos)
     
    #define USB_OTG_HCTSIZ_DOPING   USB_OTG_HCTSIZ_DOPING_Msk
     
    #define USB_OTG_HCTSIZ_DPID_Pos   (29U)
     
    #define USB_OTG_HCTSIZ_DPID_Msk   (0x3UL << USB_OTG_HCTSIZ_DPID_Pos)
     
    #define USB_OTG_HCTSIZ_DPID   USB_OTG_HCTSIZ_DPID_Msk
     
    #define USB_OTG_HCTSIZ_DPID_0   (0x1UL << USB_OTG_HCTSIZ_DPID_Pos)
     
    #define USB_OTG_HCTSIZ_DPID_1   (0x2UL << USB_OTG_HCTSIZ_DPID_Pos)
     
    #define USB_OTG_DIEPDMA_DMAADDR_Pos   (0U)
     
    #define USB_OTG_DIEPDMA_DMAADDR_Msk   (0xFFFFFFFFUL << USB_OTG_DIEPDMA_DMAADDR_Pos)
     
    #define USB_OTG_DIEPDMA_DMAADDR   USB_OTG_DIEPDMA_DMAADDR_Msk
     
    #define USB_OTG_HCDMA_DMAADDR_Pos   (0U)
     
    #define USB_OTG_HCDMA_DMAADDR_Msk   (0xFFFFFFFFUL << USB_OTG_HCDMA_DMAADDR_Pos)
     
    #define USB_OTG_HCDMA_DMAADDR   USB_OTG_HCDMA_DMAADDR_Msk
     
    #define USB_OTG_DTXFSTS_INEPTFSAV_Pos   (0U)
     
    #define USB_OTG_DTXFSTS_INEPTFSAV_Msk   (0xFFFFUL << USB_OTG_DTXFSTS_INEPTFSAV_Pos)
     
    #define USB_OTG_DTXFSTS_INEPTFSAV   USB_OTG_DTXFSTS_INEPTFSAV_Msk
     
    #define USB_OTG_DIEPTXF_INEPTXSA_Pos   (0U)
     
    #define USB_OTG_DIEPTXF_INEPTXSA_Msk   (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXSA_Pos)
     
    #define USB_OTG_DIEPTXF_INEPTXSA   USB_OTG_DIEPTXF_INEPTXSA_Msk
     
    #define USB_OTG_DIEPTXF_INEPTXFD_Pos   (16U)
     
    #define USB_OTG_DIEPTXF_INEPTXFD_Msk   (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXFD_Pos)
     
    #define USB_OTG_DIEPTXF_INEPTXFD   USB_OTG_DIEPTXF_INEPTXFD_Msk
     
    #define USB_OTG_DOEPCTL_MPSIZ_Pos   (0U)
     
    #define USB_OTG_DOEPCTL_MPSIZ_Msk   (0x7FFUL << USB_OTG_DOEPCTL_MPSIZ_Pos)
     
    #define USB_OTG_DOEPCTL_MPSIZ   USB_OTG_DOEPCTL_MPSIZ_Msk /*!< Maximum packet size */
     
    #define USB_OTG_DOEPCTL_USBAEP_Pos   (15U)
     
    #define USB_OTG_DOEPCTL_USBAEP_Msk   (0x1UL << USB_OTG_DOEPCTL_USBAEP_Pos)
     
    #define USB_OTG_DOEPCTL_USBAEP   USB_OTG_DOEPCTL_USBAEP_Msk
     
    #define USB_OTG_DOEPCTL_NAKSTS_Pos   (17U)
     
    #define USB_OTG_DOEPCTL_NAKSTS_Msk   (0x1UL << USB_OTG_DOEPCTL_NAKSTS_Pos)
     
    #define USB_OTG_DOEPCTL_NAKSTS   USB_OTG_DOEPCTL_NAKSTS_Msk
     
    #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos   (28U)
     
    #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk   (0x1UL << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos)
     
    #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM   USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk
     
    #define USB_OTG_DOEPCTL_SODDFRM_Pos   (29U)
     
    #define USB_OTG_DOEPCTL_SODDFRM_Msk   (0x1UL << USB_OTG_DOEPCTL_SODDFRM_Pos)
     
    #define USB_OTG_DOEPCTL_SODDFRM   USB_OTG_DOEPCTL_SODDFRM_Msk
     
    #define USB_OTG_DOEPCTL_EPTYP_Pos   (18U)
     
    #define USB_OTG_DOEPCTL_EPTYP_Msk   (0x3UL << USB_OTG_DOEPCTL_EPTYP_Pos)
     
    #define USB_OTG_DOEPCTL_EPTYP   USB_OTG_DOEPCTL_EPTYP_Msk
     
    #define USB_OTG_DOEPCTL_EPTYP_0   (0x1UL << USB_OTG_DOEPCTL_EPTYP_Pos)
     
    #define USB_OTG_DOEPCTL_EPTYP_1   (0x2UL << USB_OTG_DOEPCTL_EPTYP_Pos)
     
    #define USB_OTG_DOEPCTL_SNPM_Pos   (20U)
     
    #define USB_OTG_DOEPCTL_SNPM_Msk   (0x1UL << USB_OTG_DOEPCTL_SNPM_Pos)
     
    #define USB_OTG_DOEPCTL_SNPM   USB_OTG_DOEPCTL_SNPM_Msk
     
    #define USB_OTG_DOEPCTL_STALL_Pos   (21U)
     
    #define USB_OTG_DOEPCTL_STALL_Msk   (0x1UL << USB_OTG_DOEPCTL_STALL_Pos)
     
    #define USB_OTG_DOEPCTL_STALL   USB_OTG_DOEPCTL_STALL_Msk
     
    #define USB_OTG_DOEPCTL_CNAK_Pos   (26U)
     
    #define USB_OTG_DOEPCTL_CNAK_Msk   (0x1UL << USB_OTG_DOEPCTL_CNAK_Pos)
     
    #define USB_OTG_DOEPCTL_CNAK   USB_OTG_DOEPCTL_CNAK_Msk
     
    #define USB_OTG_DOEPCTL_SNAK_Pos   (27U)
     
    #define USB_OTG_DOEPCTL_SNAK_Msk   (0x1UL << USB_OTG_DOEPCTL_SNAK_Pos)
     
    #define USB_OTG_DOEPCTL_SNAK   USB_OTG_DOEPCTL_SNAK_Msk
     
    #define USB_OTG_DOEPCTL_EPDIS_Pos   (30U)
     
    #define USB_OTG_DOEPCTL_EPDIS_Msk   (0x1UL << USB_OTG_DOEPCTL_EPDIS_Pos)
     
    #define USB_OTG_DOEPCTL_EPDIS   USB_OTG_DOEPCTL_EPDIS_Msk
     
    #define USB_OTG_DOEPCTL_EPENA_Pos   (31U)
     
    #define USB_OTG_DOEPCTL_EPENA_Msk   (0x1UL << USB_OTG_DOEPCTL_EPENA_Pos)
     
    #define USB_OTG_DOEPCTL_EPENA   USB_OTG_DOEPCTL_EPENA_Msk
     
    #define USB_OTG_DOEPINT_XFRC_Pos   (0U)
     
    #define USB_OTG_DOEPINT_XFRC_Msk   (0x1UL << USB_OTG_DOEPINT_XFRC_Pos)
     
    #define USB_OTG_DOEPINT_XFRC   USB_OTG_DOEPINT_XFRC_Msk
     
    #define USB_OTG_DOEPINT_EPDISD_Pos   (1U)
     
    #define USB_OTG_DOEPINT_EPDISD_Msk   (0x1UL << USB_OTG_DOEPINT_EPDISD_Pos)
     
    #define USB_OTG_DOEPINT_EPDISD   USB_OTG_DOEPINT_EPDISD_Msk
     
    #define USB_OTG_DOEPINT_AHBERR_Pos   (2U)
     
    #define USB_OTG_DOEPINT_AHBERR_Msk   (0x1UL << USB_OTG_DOEPINT_AHBERR_Pos)
     
    #define USB_OTG_DOEPINT_AHBERR   USB_OTG_DOEPINT_AHBERR_Msk
     
    #define USB_OTG_DOEPINT_STUP_Pos   (3U)
     
    #define USB_OTG_DOEPINT_STUP_Msk   (0x1UL << USB_OTG_DOEPINT_STUP_Pos)
     
    #define USB_OTG_DOEPINT_STUP   USB_OTG_DOEPINT_STUP_Msk
     
    #define USB_OTG_DOEPINT_OTEPDIS_Pos   (4U)
     
    #define USB_OTG_DOEPINT_OTEPDIS_Msk   (0x1UL << USB_OTG_DOEPINT_OTEPDIS_Pos)
     
    #define USB_OTG_DOEPINT_OTEPDIS   USB_OTG_DOEPINT_OTEPDIS_Msk
     
    #define USB_OTG_DOEPINT_OTEPSPR_Pos   (5U)
     
    #define USB_OTG_DOEPINT_OTEPSPR_Msk   (0x1UL << USB_OTG_DOEPINT_OTEPSPR_Pos)
     
    #define USB_OTG_DOEPINT_OTEPSPR   USB_OTG_DOEPINT_OTEPSPR_Msk
     
    #define USB_OTG_DOEPINT_B2BSTUP_Pos   (6U)
     
    #define USB_OTG_DOEPINT_B2BSTUP_Msk   (0x1UL << USB_OTG_DOEPINT_B2BSTUP_Pos)
     
    #define USB_OTG_DOEPINT_B2BSTUP   USB_OTG_DOEPINT_B2BSTUP_Msk
     
    #define USB_OTG_DOEPINT_OUTPKTERR_Pos   (8U)
     
    #define USB_OTG_DOEPINT_OUTPKTERR_Msk   (0x1UL << USB_OTG_DOEPINT_OUTPKTERR_Pos)
     
    #define USB_OTG_DOEPINT_OUTPKTERR   USB_OTG_DOEPINT_OUTPKTERR_Msk
     
    #define USB_OTG_DOEPINT_NAK_Pos   (13U)
     
    #define USB_OTG_DOEPINT_NAK_Msk   (0x1UL << USB_OTG_DOEPINT_NAK_Pos)
     
    #define USB_OTG_DOEPINT_NAK   USB_OTG_DOEPINT_NAK_Msk
     
    #define USB_OTG_DOEPINT_NYET_Pos   (14U)
     
    #define USB_OTG_DOEPINT_NYET_Msk   (0x1UL << USB_OTG_DOEPINT_NYET_Pos)
     
    #define USB_OTG_DOEPINT_NYET   USB_OTG_DOEPINT_NYET_Msk
     
    #define USB_OTG_DOEPINT_STPKTRX_Pos   (15U)
     
    #define USB_OTG_DOEPINT_STPKTRX_Msk   (0x1UL << USB_OTG_DOEPINT_STPKTRX_Pos)
     
    #define USB_OTG_DOEPINT_STPKTRX   USB_OTG_DOEPINT_STPKTRX_Msk
     
    #define USB_OTG_DOEPTSIZ_XFRSIZ_Pos   (0U)
     
    #define USB_OTG_DOEPTSIZ_XFRSIZ_Msk   (0x7FFFFUL << USB_OTG_DOEPTSIZ_XFRSIZ_Pos)
     
    #define USB_OTG_DOEPTSIZ_XFRSIZ   USB_OTG_DOEPTSIZ_XFRSIZ_Msk
     
    #define USB_OTG_DOEPTSIZ_PKTCNT_Pos   (19U)
     
    #define USB_OTG_DOEPTSIZ_PKTCNT_Msk   (0x3FFUL << USB_OTG_DOEPTSIZ_PKTCNT_Pos)
     
    #define USB_OTG_DOEPTSIZ_PKTCNT   USB_OTG_DOEPTSIZ_PKTCNT_Msk
     
    #define USB_OTG_DOEPTSIZ_STUPCNT_Pos   (29U)
     
    #define USB_OTG_DOEPTSIZ_STUPCNT_Msk   (0x3UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos)
     
    #define USB_OTG_DOEPTSIZ_STUPCNT   USB_OTG_DOEPTSIZ_STUPCNT_Msk
     
    #define USB_OTG_DOEPTSIZ_STUPCNT_0   (0x1UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos)
     
    #define USB_OTG_DOEPTSIZ_STUPCNT_1   (0x2UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos)
     
    #define USB_OTG_PCGCCTL_STOPCLK_Pos   (0U)
     
    #define USB_OTG_PCGCCTL_STOPCLK_Msk   (0x1UL << USB_OTG_PCGCCTL_STOPCLK_Pos)
     
    #define USB_OTG_PCGCCTL_STOPCLK   USB_OTG_PCGCCTL_STOPCLK_Msk
     
    #define USB_OTG_PCGCCTL_GATECLK_Pos   (1U)
     
    #define USB_OTG_PCGCCTL_GATECLK_Msk   (0x1UL << USB_OTG_PCGCCTL_GATECLK_Pos)
     
    #define USB_OTG_PCGCCTL_GATECLK   USB_OTG_PCGCCTL_GATECLK_Msk
     
    #define USB_OTG_PCGCCTL_PHYSUSP_Pos   (4U)
     
    #define USB_OTG_PCGCCTL_PHYSUSP_Msk   (0x1UL << USB_OTG_PCGCCTL_PHYSUSP_Pos)
     
    #define USB_OTG_PCGCCTL_PHYSUSP   USB_OTG_PCGCCTL_PHYSUSP_Msk
     
    #define USB_OTG_CHNUM_Pos   (0U)
     
    #define USB_OTG_CHNUM_Msk   (0xFUL << USB_OTG_CHNUM_Pos)
     
    #define USB_OTG_CHNUM   USB_OTG_CHNUM_Msk
     
    #define USB_OTG_CHNUM_0   (0x1UL << USB_OTG_CHNUM_Pos)
     
    #define USB_OTG_CHNUM_1   (0x2UL << USB_OTG_CHNUM_Pos)
     
    #define USB_OTG_CHNUM_2   (0x4UL << USB_OTG_CHNUM_Pos)
     
    #define USB_OTG_CHNUM_3   (0x8UL << USB_OTG_CHNUM_Pos)
     
    #define USB_OTG_BCNT_Pos   (4U)
     
    #define USB_OTG_BCNT_Msk   (0x7FFUL << USB_OTG_BCNT_Pos)
     
    #define USB_OTG_BCNT   USB_OTG_BCNT_Msk
     
    #define USB_OTG_DPID_Pos   (15U)
     
    #define USB_OTG_DPID_Msk   (0x3UL << USB_OTG_DPID_Pos)
     
    #define USB_OTG_DPID   USB_OTG_DPID_Msk
     
    #define USB_OTG_DPID_0   (0x1UL << USB_OTG_DPID_Pos)
     
    #define USB_OTG_DPID_1   (0x2UL << USB_OTG_DPID_Pos)
     
    #define USB_OTG_PKTSTS_Pos   (17U)
     
    #define USB_OTG_PKTSTS_Msk   (0xFUL << USB_OTG_PKTSTS_Pos)
     
    #define USB_OTG_PKTSTS   USB_OTG_PKTSTS_Msk
     
    #define USB_OTG_PKTSTS_0   (0x1UL << USB_OTG_PKTSTS_Pos)
     
    #define USB_OTG_PKTSTS_1   (0x2UL << USB_OTG_PKTSTS_Pos)
     
    #define USB_OTG_PKTSTS_2   (0x4UL << USB_OTG_PKTSTS_Pos)
     
    #define USB_OTG_PKTSTS_3   (0x8UL << USB_OTG_PKTSTS_Pos)
     
    #define USB_OTG_EPNUM_Pos   (0U)
     
    #define USB_OTG_EPNUM_Msk   (0xFUL << USB_OTG_EPNUM_Pos)
     
    #define USB_OTG_EPNUM   USB_OTG_EPNUM_Msk
     
    #define USB_OTG_EPNUM_0   (0x1UL << USB_OTG_EPNUM_Pos)
     
    #define USB_OTG_EPNUM_1   (0x2UL << USB_OTG_EPNUM_Pos)
     
    #define USB_OTG_EPNUM_2   (0x4UL << USB_OTG_EPNUM_Pos)
     
    #define USB_OTG_EPNUM_3   (0x8UL << USB_OTG_EPNUM_Pos)
     
    #define USB_OTG_FRMNUM_Pos   (21U)
     
    #define USB_OTG_FRMNUM_Msk   (0xFUL << USB_OTG_FRMNUM_Pos)
     
    #define USB_OTG_FRMNUM   USB_OTG_FRMNUM_Msk
     
    #define USB_OTG_FRMNUM_0   (0x1UL << USB_OTG_FRMNUM_Pos)
     
    #define USB_OTG_FRMNUM_1   (0x2UL << USB_OTG_FRMNUM_Pos)
     
    #define USB_OTG_FRMNUM_2   (0x4UL << USB_OTG_FRMNUM_Pos)
     
    #define USB_OTG_FRMNUM_3   (0x8UL << USB_OTG_FRMNUM_Pos)
     
    #define IS_ADC_ALL_INSTANCE(INSTANCE)
     
    #define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE)   ((INSTANCE) == ADC1)
     
    #define IS_ADC_COMMON_INSTANCE(INSTANCE)   ((INSTANCE) == ADC123_COMMON)
     
    #define IS_CAN_ALL_INSTANCE(INSTANCE)
     
    #define IS_CRC_ALL_INSTANCE(INSTANCE)   ((INSTANCE) == CRC)
     
    #define IS_DAC_ALL_INSTANCE(INSTANCE)   ((INSTANCE) == DAC1)
     
    #define IS_DCMI_ALL_INSTANCE(INSTANCE)   ((INSTANCE) == DCMI)
     
    #define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE)
     
    #define IS_GPIO_ALL_INSTANCE(INSTANCE)
     
    #define IS_I2C_ALL_INSTANCE(INSTANCE)
     
    #define IS_SMBUS_ALL_INSTANCE   IS_I2C_ALL_INSTANCE
     
    #define IS_I2S_ALL_INSTANCE(INSTANCE)
     
    #define IS_I2S_EXT_ALL_INSTANCE(INSTANCE)
     
    #define IS_I2S_ALL_INSTANCE_EXT   IS_I2S_EXT_ALL_INSTANCE
     
    #define IS_RNG_ALL_INSTANCE(INSTANCE)   ((INSTANCE) == RNG)
     
    #define IS_RTC_ALL_INSTANCE(INSTANCE)   ((INSTANCE) == RTC)
     
    #define IS_SPI_ALL_INSTANCE(INSTANCE)
     
    #define IS_TIM_INSTANCE(INSTANCE)
     
    #define IS_TIM_CC1_INSTANCE(INSTANCE)
     
    #define IS_TIM_CC2_INSTANCE(INSTANCE)
     
    #define IS_TIM_CC3_INSTANCE(INSTANCE)
     
    #define IS_TIM_CC4_INSTANCE(INSTANCE)
     
    #define IS_TIM_ADVANCED_INSTANCE(INSTANCE)
     
    #define IS_TIM_XOR_INSTANCE(INSTANCE)
     
    #define IS_TIM_DMA_INSTANCE(INSTANCE)
     
    #define IS_TIM_DMA_CC_INSTANCE(INSTANCE)
     
    #define IS_TIM_CCDMA_INSTANCE(INSTANCE)
     
    #define IS_TIM_DMABURST_INSTANCE(INSTANCE)
     
    #define IS_TIM_MASTER_INSTANCE(INSTANCE)
     
    #define IS_TIM_SLAVE_INSTANCE(INSTANCE)
     
    #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)
     
    #define IS_TIM_ETR_INSTANCE(INSTANCE)
     
    #define IS_TIM_REMAP_INSTANCE(INSTANCE)
     
    #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL)
     
    #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL)
     
    #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)
     
    #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)
     
    #define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE)
     
    #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)
     
    #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)
     
    #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)
     
    #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)
     
    #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)
     
    #define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)
     
    #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)
     
    #define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE)
     
    #define IS_TIM_BREAK_INSTANCE(INSTANCE)
     
    #define IS_USART_INSTANCE(INSTANCE)
     
    #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE)
     
    #define IS_UART_INSTANCE   IS_UART_HALFDUPLEX_INSTANCE
     
    #define IS_UART_HWFLOW_INSTANCE(INSTANCE)
     
    #define IS_UART_LIN_INSTANCE   IS_UART_HALFDUPLEX_INSTANCE
     
    #define IS_SMARTCARD_INSTANCE(INSTANCE)
     
    #define IS_IRDA_INSTANCE(INSTANCE)
     
    #define IS_PCD_ALL_INSTANCE(INSTANCE)
     
    #define IS_HCD_ALL_INSTANCE(INSTANCE)
     
    #define IS_SDIO_ALL_INSTANCE(INSTANCE)   ((INSTANCE) == SDIO)
     
    #define IS_IWDG_ALL_INSTANCE(INSTANCE)   ((INSTANCE) == IWDG)
     
    #define IS_WWDG_ALL_INSTANCE(INSTANCE)   ((INSTANCE) == WWDG)
     
    #define USB_OTG_FS_HOST_MAX_CHANNEL_NBR   8U
     
    #define USB_OTG_FS_MAX_IN_ENDPOINTS   4U /* Including EP0 */
     
    #define USB_OTG_FS_MAX_OUT_ENDPOINTS   4U /* Including EP0 */
     
    #define USB_OTG_FS_TOTAL_FIFO_SIZE   1280U /* in Bytes */
     
    #define RCC_PLLCFGR_RST_VALUE   0x24003010U
     
    #define RCC_PLLI2SCFGR_RST_VALUE   0x20003000U
     
    #define RCC_MAX_FREQUENCY   168000000U
     
    #define RCC_MAX_FREQUENCY_SCALE1   RCC_MAX_FREQUENCY
     
    #define RCC_MAX_FREQUENCY_SCALE2   144000000U
     
    #define RCC_PLLVCO_OUTPUT_MIN   100000000U
     
    #define RCC_PLLVCO_INPUT_MIN   950000U
     
    #define RCC_PLLVCO_INPUT_MAX   2100000U
     
    #define RCC_PLLVCO_OUTPUT_MAX   432000000U
     
    #define RCC_PLLN_MIN_VALUE   50U
     
    #define RCC_PLLN_MAX_VALUE   432U
     
    #define FLASH_SCALE1_LATENCY1_FREQ   30000000U
     
    #define FLASH_SCALE1_LATENCY2_FREQ   60000000U
     
    #define FLASH_SCALE1_LATENCY3_FREQ   90000000U
     
    #define FLASH_SCALE1_LATENCY4_FREQ   120000000U
     
    #define FLASH_SCALE1_LATENCY5_FREQ   150000000U
     
    #define FLASH_SCALE2_LATENCY1_FREQ   30000000U
     
    #define FLASH_SCALE2_LATENCY2_FREQ   60000000U
     
    #define FLASH_SCALE2_LATENCY3_FREQ   90000000U
     
    #define FLASH_SCALE2_LATENCY4_FREQ   12000000U
     
    #define USB_OTG_HS_HOST_MAX_CHANNEL_NBR   12U
     
    #define USB_OTG_HS_MAX_IN_ENDPOINTS   6U /* Including EP0 */
     
    #define USB_OTG_HS_MAX_OUT_ENDPOINTS   6U /* Including EP0 */
     
    #define USB_OTG_HS_TOTAL_FIFO_SIZE   4096U /* in Bytes */
     
    #define FMC_IRQn   FSMC_IRQn
     
    #define FMC_IRQHandler   FSMC_IRQHandler
     
    - - - -

    -Typedefs

    typedef struct _memory MCU_MemoryTypeDef
     
    - - - - -

    -Enumerations

    enum  IRQn_Type {
    -  NonMaskableInt_IRQn = -14 -, MemoryManagement_IRQn = -12 -, BusFault_IRQn = -11 -, UsageFault_IRQn = -10 -,
    -  SVCall_IRQn = -5 -, DebugMonitor_IRQn = -4 -, PendSV_IRQn = -2 -, SysTick_IRQn = -1 -,
    -  WWDG_IRQn = 0 -, PVD_IRQn = 1 -, TAMP_STAMP_IRQn = 2 -, RTC_WKUP_IRQn = 3 -,
    -  FLASH_IRQn = 4 -, RCC_IRQn = 5 -, EXTI0_IRQn = 6 -, EXTI1_IRQn = 7 -,
    -  EXTI2_IRQn = 8 -, EXTI3_IRQn = 9 -, EXTI4_IRQn = 10 -, DMA1_Stream0_IRQn = 11 -,
    -  DMA1_Stream1_IRQn = 12 -, DMA1_Stream2_IRQn = 13 -, DMA1_Stream3_IRQn = 14 -, DMA1_Stream4_IRQn = 15 -,
    -  DMA1_Stream5_IRQn = 16 -, DMA1_Stream6_IRQn = 17 -, ADC_IRQn = 18 -, CAN1_TX_IRQn = 19 -,
    -  CAN1_RX0_IRQn = 20 -, CAN1_RX1_IRQn = 21 -, CAN1_SCE_IRQn = 22 -, EXTI9_5_IRQn = 23 -,
    -  TIM1_BRK_TIM9_IRQn = 24 -, TIM1_UP_TIM10_IRQn = 25 -, TIM1_TRG_COM_TIM11_IRQn = 26 -, TIM1_CC_IRQn = 27 -,
    -  TIM2_IRQn = 28 -, TIM3_IRQn = 29 -, TIM4_IRQn = 30 -, I2C1_EV_IRQn = 31 -,
    -  I2C1_ER_IRQn = 32 -, I2C2_EV_IRQn = 33 -, I2C2_ER_IRQn = 34 -, SPI1_IRQn = 35 -,
    -  SPI2_IRQn = 36 -, USART1_IRQn = 37 -, USART2_IRQn = 38 -, USART3_IRQn = 39 -,
    -  EXTI15_10_IRQn = 40 -, RTC_Alarm_IRQn = 41 -, OTG_FS_WKUP_IRQn = 42 -, TIM8_BRK_TIM12_IRQn = 43 -,
    -  TIM8_UP_TIM13_IRQn = 44 -, TIM8_TRG_COM_TIM14_IRQn = 45 -, TIM8_CC_IRQn = 46 -, DMA1_Stream7_IRQn = 47 -,
    -  FSMC_IRQn = 48 -, SDIO_IRQn = 49 -, TIM5_IRQn = 50 -, SPI3_IRQn = 51 -,
    -  UART4_IRQn = 52 -, UART5_IRQn = 53 -, TIM6_DAC_IRQn = 54 -, TIM7_IRQn = 55 -,
    -  DMA2_Stream0_IRQn = 56 -, DMA2_Stream1_IRQn = 57 -, DMA2_Stream2_IRQn = 58 -, DMA2_Stream3_IRQn = 59 -,
    -  DMA2_Stream4_IRQn = 60 -, ETH_IRQn = 61 -, ETH_WKUP_IRQn = 62 -, CAN2_TX_IRQn = 63 -,
    -  CAN2_RX0_IRQn = 64 -, CAN2_RX1_IRQn = 65 -, CAN2_SCE_IRQn = 66 -, OTG_FS_IRQn = 67 -,
    -  DMA2_Stream5_IRQn = 68 -, DMA2_Stream6_IRQn = 69 -, DMA2_Stream7_IRQn = 70 -, USART6_IRQn = 71 -,
    -  I2C3_EV_IRQn = 72 -, I2C3_ER_IRQn = 73 -, OTG_HS_EP1_OUT_IRQn = 74 -, OTG_HS_EP1_IN_IRQn = 75 -,
    -  OTG_HS_WKUP_IRQn = 76 -, OTG_HS_IRQn = 77 -, DCMI_IRQn = 78 -, RNG_IRQn = 80 -,
    -  FPU_IRQn = 81 -
    - }
     STM32F4XX Interrupt Number Definition, according to the selected device in Library_configuration_section. More...
     
    - - - - - -

    -Variables

    MCU_MemoryTypeDef MCU_MEM
     
    DBGMCU_TypeDef DEBUG_MCU
     
    -
    - -
    -Generated by doxygen 1.10.0 -
    - - diff --git a/DOCS/html/stm32f407xx__matlab_8h__dep__incl.map b/DOCS/html/stm32f407xx__matlab_8h__dep__incl.map deleted file mode 100644 index 12be981..0000000 --- a/DOCS/html/stm32f407xx__matlab_8h__dep__incl.map +++ /dev/null @@ -1,5 +0,0 @@ - - - - - diff --git a/DOCS/html/stm32f407xx__matlab_8h__dep__incl.md5 b/DOCS/html/stm32f407xx__matlab_8h__dep__incl.md5 deleted file mode 100644 index 5b94ca5..0000000 --- a/DOCS/html/stm32f407xx__matlab_8h__dep__incl.md5 +++ /dev/null @@ -1 +0,0 @@ -9c2ef22dd24e4de9d7caf95640224044 \ No newline at end of file diff --git a/DOCS/html/stm32f407xx__matlab_8h__dep__incl.png b/DOCS/html/stm32f407xx__matlab_8h__dep__incl.png deleted file mode 100644 index b7227aa697a4e4c7633a29306995ed9b4e1a96d9..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 4501 zcmchbc{Cf!zrcfDw5ZZsYb zl5GtB(*oi>XEIcXwnt!Mym2BT&iRsoX!+oH)IQ&u@SICL^Bdn;kp5g?9@I3g-5QhFslSuFwh!P7dz- zNCJ%=935*H2VEL}2}p{XL9z{o)h)K!_q<1aaNwQp*G{l=tng?=2>s&c1AWv%eiSJ1d`_CI-xv2suxnwkS*cpL*&mAT?uhA7wK$ck zXHaF|16Hl}9#OGt#p;ljlSU0!*`BR8n*GvYMy4`K@Rkp*Y|} zsOO3M>d)g5Tk`%6Y4UHZzX-m*>CO2Lxk78Iw=FvvrYjscmvgZ-6bDJ$;|2 z1%_;6GG~Z$)?NhTI5>p$5i@i=3pwf6mJkf!O<89El9l)tgSXFe?s-uoK)pxOh0wS* z{?93G+{%%}zm3~&Ik)S! zdH0F+`;!SJe)i#v(_>e6rBsFO3NO~4Dt9dP>=+*EXhVl)CFto_jr0rL?w*cx??=%- zV0NtJLn-EQL}3J19j4T|@FHya{=~qg4m_z$#$xUCbJ-`l+tucz1%q|I%svtb33W=b z@?`txk699c0gB_Xz2iD+?TJu#I(Vm@1Xdl>E$kfbOfAVeJa|EF4vq`pe2@Bp3hq5k zGibj2GUe9}w4_Y^agww(m%jABy-NG9-mX;nBM55+4?jD^d4EuGdM#9iiZ5X`I-Eb! z_|AkKPE|{vTku{&4v1aRPSZ+{76Dy#!s4+%YqEf`jRD9 zf{QQupO3%BTW5%-qyp%esV>HoU(-mCKp*lH4jjk{aQ*rrU^o1SyNfeiO-_#KcGkW7 zT@0agKf-|>$u2F>*eb1E7vy0^BO3K|0}^!;T!wfEP#^~6Yi>OsVVuaxmY*#vnrzG> z^~2VnqxqY-LBhTh41qVIbi5WUcS9&U+QemkciF}09$8rjHXABa!oyik(X zOT>hW(1vvpuP%IAvfDhs!Ntgl{ld_Tp3(2~?GVi!*)JVet52Q`xO?uw+y0SQ4_6Qm zhi5P!0?W~>?2Zjk+Vm+$iv~Pwlp8+OnAwB^50~OqY~$GovB)yXWYb9_9e{jqG(zu- zJtF%eQ2@nH$C`ThKac&#)c|0B`<%xufY`;6LvuTP^1`}av6oFQ8XE3>u6p!)je_X) zuiu7>=Pn&I>39i!(R?|v0#fq~6Y=+V_;?FBk+c!MySQw)@!ik^gDT(TiuGqMmEJaS z)L@x?qDA9c486qt1<)T1Rhq3VNGJBAN$2TeO&_uoW|lYGXZkjdiuj&+YDkF~I=SlO zX(ERgf6fIW!den>Ev@Ps5+Z}Nx3FUML1=jlcPt$%LnLgBnMD_8T&J*_Wgfm9rz=Jh zAFl197CqGK4yQ^2H|>Auyua~!wT1FMuF#Ku9L;c`##>#gEK#dak{@WSIDuh5E7zUm|Bl#=D#t1T~0T2wbyW3nv1;iFgcUT%;-9YpS2OAe!- zKr@beiqU9tL0M@~VR`sWTmjKe&*Z+J-O+tG3Vf1J5ae!HF1%N8vb$%WUKPsq99AMb3)Y z>o61#q7memfJ&NPQ`ohMk5EVq^PJOPv~BgvkTozw?H%7g+I?pKa2S&uHyTkUvL6oF zU~Cp+T60GD-v4t6|K}V3|0OZnxGL}H;Lw7Mjoqph=>_np`?XxYdi$#lZIhETPh>yJ zap#+R&R+fOp2vk#vGr-$bwSyo+sdBBloF zz{I@o7Uf+%sjH7-2edN-jUQkL&~5MDdbJV|Xf{8p4~{S1x{wYs+`8EgNgv1suWwo2 z)6m~!DahQ1zah)?(o$`vk%BK9Wl*VLq;y!9k&fu-Si|S*cKVG7;_MsAAIDcIm;hzz zagGw&la>^SPp<^_U$k*=4#^i{&bK`1zxfMz8^1AUNdS!+sSGQQW>a6~Pw-az;Tzgg zqa|@n4Suio(w#wuva=|#KH89-DZi*DVVyhL0phw2tPU0byO5brdhMd zBM*^|EV1faqQ>CJ7(md85~1Xi*@0Yj`cy0uP?xMF4FK_il7CA582|&*VJv=IP@$@p zo}|hykAALDWj;^O7!Hv9iBSU^tYB8>vHMAXzT5wzdGrn>+DT`2P~^AAm&mI|;`4k9 zT9P>PQI*&geM}h&Ln+kQ@~JU|h=O~%%UIS3P_lJ{!Z6O>-7H+dj@Nva>JJJ0fA()F{l3Ejm&KmF>rhm9Cb~9b5{A zw+P{YN z_4QXH?;>t7Vg{(YQr1i*PBmKAw{m%&^Y6lOZFKo4~1~%=YKQOV00T2~(?B zAhRaHQJ<~-i9bx3z!*7D1vd>Z{ojPs^I%25e`;SgC_L3BOq?2Z_hBSk896}WUsUtt z;vAyp?DOlRPGTP7O&_|f-P6F^$Wb3j7RPJ%U87|<&TA)X8^7>6p^_>eKL;!=5dvfk z8EJE7mAZG+rjuiN#<1T%$UE^a^O92jvHBQY)Jp}T!nP{rp0pp1EtY5WmriU#r5&YE zjLdq>o9Rk&Znb6j?W2#XxKphH8+3n5Y$I!cUp<0$WOj|gBr{H1ib9zEqp6r|pArup zIZ7)U!4c&;(+d`H&vHL(BO z^cvOd(qJ|Leb)l*|KV)biG>~OlpLADpOBqqYx{WYoA3#8L*6Ol&0B6i1q zoJsgtqK=6DrYngo#@*t-Ss*r!Q9a6UB>rPUdmX1Hgm z_d;Ef{^6wEKJ~(_(du$+gx-Zq7?S@D=%#ja<{3()^Fg6H(exT0NzWO7j@jsgIX|H|&pEr%i`16fL}O#K1!}^uEv7vXW5oD?zkp#)j&R<()srbn02_eRxiu!i;CdFC2Qm zN#JD7E;ndh9N6m#vp1fi?Q(a0|K-8$K - - - - - - - - - - diff --git a/DOCS/html/stm32f407xx__matlab_8h__incl.md5 b/DOCS/html/stm32f407xx__matlab_8h__incl.md5 deleted file mode 100644 index 6c6e78c..0000000 --- a/DOCS/html/stm32f407xx__matlab_8h__incl.md5 +++ /dev/null @@ -1 +0,0 @@ -09b44ea2f6e8aeb173670f1d20af76da \ No newline at end of file diff --git a/DOCS/html/stm32f407xx__matlab_8h__incl.png b/DOCS/html/stm32f407xx__matlab_8h__incl.png deleted file mode 100644 index c4b2cfbb6df429314b262e42d0c376096334c60d..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 6768 zcmZ{J2UHVX*KX(th9XV6fQBkkq(~JBJya>urAw8FRB47D47?C}7oh@X{hy+(alUVUegb##&8F?cH48Tw)G+4_0rdWP)ap4?#l zAYSDEv-PRCkUa0**xL)Lk8JAlVgW1VmdrD=vi=R*k&J|w|MUVR+@lIXU7 zC9E9vq5>;nY;(KbdwES!d@P~@fj}-1&qqY~&;$=SIdiRTL=?baFiI%(_Ucs%go>J4 zR{#RSjmtw1qQTvwB@bdUu~t-6EZ=)OQQ7`Rwsti90O3$wUOWD`5IPfKz6 z`YiFS3C7|C|Ek;#aynW8Y2BgGeI}I3Q~&VEMFGN!DPHyU6`Ia)Mv8RWr*SmE!(45`dgmOJ_6m(W*4lfJ|4+jX|7ao~K@a?*5D zX3i^E($Ph~v*i_fxc{-SO@{*5x63Lf-r22^iMh1;0}afAq?x_&s>m+grPEclt-7i1 zGVxdl*^8cy=K{%sS37KTSC(dICnxHB#H6g4#D~G0P9aHN1Pu0rSX51&jsEDU2Xk(J1f+RzQb%Z<4U88wHhS!Rc}~~nHtSj zwzg)9o`0t>?cNysut)#g(CLIQXO}JpK(D%i4pq)zf}zPR_$_Ti6?VBq?X^8_E9v4zJFZ2XUxx1J7Tr zv=i#%*J7>rVQjCG#yY1Wd0JB-I!lKmZ&rAds=o+phmKz&C`Ff748Zz0{H#b8zBmWV zt_6x_-qWoYPR*fVYHVRmaAS zk2xYQtBpAM7_OftSmdCn9kaYYpNrO#7!hd(?9^l#or8b|6R#kr!s@ANNz|U~Ar>^$ zj}WpnkJd(AcTS}?{ytE^KKiv0_LvJ1F1{%e?{8Z_PcVIz#KC#kk#z?yu=UFKx6L-1 zEjRI`8Q-dJIp8ih;Sq?2Hpz{hS*q}LQq8&l?r7*E5sIQiKAKy)4=fXXS|owm*0cAeczXbUEwv7RD-fqdEB zm-CJkmnm-3V?#95lN@M*9NW8h?;c0?Bn=E`O@F4M>-heiP~UU4r>Dno8bw9N8u9Gk zWTNoU**ymmd>IXJ%Y$&{=30v=)H~!I*mpb!+s1UV{F`aWJDi-H@UTvnmEN6}k8A6i zb;1F}Vbe$aX|>dUL~HG4`ZP3B0<_*WS|yb}S@!lvMutW9h4d2EA36y!u?x{vy9{|< zB{{n6!`2W&u7GdWRfD>yC=4|v`?>#eJ!G(9DiNFtdvH%P39ypY<(G3 z>L`jpQWA6ViGyfX_}o!g@-*`^P^j0WWv8<_j$TD|~Fyq_|kCu3?2fAWf&FL0$ z>eOq!$vG(eYAmi}buX^^15bQLVXm&;Wy*SJWF!pb05j`K9pQmFYU@FFf**BBmvuwsH(ZiJufOp>Dj&T)L=C|1BDo7b;%RKVze$u#U=GR-OBS5a0* zPsM~4ZTu(M+*9(tTy+;sc5Ne0l)=Z=5Rf_?X!-Q31ZOV8vJeS1HFZ~qEer<=>qQ}w zb1j&yRDR9opBXe(%qn4CssQzU^>ny5C)>bJQ-Mui{-=DjtKs+0Nl(}67rq;U&)aQb z7H!8LH412S!p!Bjqypp325q|`tsQFA!cATYSVvjstQ@E(FP9$6B$-ILr~%{jOt9afvQys+l1$7I1ng z5a~D@TINx^L()v)5kwJT7`bgFqH7I((oz6SGVNs1cN>yYKt)Uj4jn>wIfVbtXpbSj zIL?9*yxS->Cu2@^O5~kB{e-u1Anb&{PQuT(-vgt}=w%=3MleVUD2$l+3=$H-Jr-lD z+(r(!%(so_o;v-0)i@hLwH63KvQbuCGXDM=-ED>7>Ey8*=gPgZ7SYu!Xq^#a)atoN zukZaCsg_71P9cE+Is}{>I)f(_74+R$)^ZqB{p#AV=_obWJ%`MPYj516^Uk}$6@y3~ zF4bi@F>cSm>__>+e}tlndi@YTh+ShNw`r#FbVP`WiT%K~8V(MHJ35hMR@T<|B@ORv zZEZ_;UPZ$HZ(`%Xss4SBjfjGSN>?AZx~hlXA)wCx_}^*YOZY#b0Ze(k_DhAmhV{j@ z8j%jhi+0oTR%<$RqFu~bk68kg-H*~#1#z{N3&~^Ue$zUD ze9#7}Z;;JjudonbG#b}Em>xx4BQ+4LhWct+n24GGbQ&2FtLP4*t;It9U6xl5KkZD+ z93wVK@ci%5HRX8~`;U9csF})^GZ@lRmMj$@G*(5?%e}wb>MRQ2%yd57!5AeW5wWl- z*1h-F^rMU7V?j&aO9-bU>c#(jQqxdP8ysJ}yApHU!iO)^9+xh36x~s2~p9@*vb_S9L>NnCR z*Sycm+(BiQsv_c4o2*J z-g`fQ1gt9C-sR>LsR*jYlDo#Jv(027_A$|T0aYB=I|-Sk0o^{363+V zy_$OG0}ku5g~^y-24~I5g;4_PsN0?>?e}&@=uVGu4Wn&D4gL_kyTJH(33S@==O1B zRhG}?lWUbM@fpkj7JvW{SjhiwowG;s)tHw*SgFkxrgi`7BU+jSWkQDq^pos|`6y<^lK`(H-V2KQMzuItI~}$hx$EaR6O6388v7ke=kH)9(6Zn zGuLs!1mFx1pkFX8xnJHwJAXeA37LwC?E%S&Roh;iZukZ)H`L_%khYnT&dE(ZPOg5z ziD&R^E?g5ZRf2)C(nNtcr-Z{s0R;up?%ew4cATM$ZoVaBk81_yB8+&4@?nZpGqM2y z`90=g?US7mqp6s<9(oIidhUjYQp#(I7Dft!N9$8Ne)cNN#4PPhc=Tf*_+w;3D(E)3 zN5D|w)Hl#FA*0Yc;{PlP9jK2bn%3B~`deR}`cXby zp9=x^sQ0gR- zU)o55GSePw_=zL1Oqg;TAiz@Q05EDvr_qOp=&a~T3) zlKQqvogv-VWNp=ayXA%lU2z(#^R5_WT6$y@{?`AJH+JC&%cYczNzpnLZ79oE{Vo$g z1!j9>HgWl^Z~vX|01kYh6bP*<S0=kMJodRlNe*Y83A%JKJ24P45|uAyH{+0d-a zaqPI6=p@}vyIq5UrpA9G==tCf?^k>w!UY$e7V-sgtyxXqE?Z7a-&35=y}BHN6;0W1LbLQ?ThUcK5l7vZW|&Iomh+qk?-wfdc;-F%AOiwQ> zL@L~I)FRXLS$GzidmcUm&weDp8*sna^G5~F+_JD6T5`pgZqXJ@?RmEP_U20VcNst>a`-kVZ3j3?ybyBA>Tf=Z^gk@qCKp(TK} zg%m+4JG?)9`v=A1?~P;P@n>ovF}Mi2mzfSQw5RI}<1LI)bRnA?Jv&P>FI3PrU#zVM z!M|}nLA5|ul~E2aj35X9Bf$b!jaz+}z5j~qsNi261NU#FIrw3@WB`1b z4`-xW^J82XSB&bSnC9$XH^5-YYtfQA#JDh7hiwPuWci{>t!pRx^s~dP6tpR6*^GMe zBo_Oqq;7tdONEf~87vEt+;?NocK^H~(9F_nrhS&vhr}#gjjk?KUO}LxUD*67(2V>w zFt{tDAsx1#b%)Z~Yr_!yILAs*JHYuVj)xPQ>WLS-Trq0%h6%!pVG4oh^v|%-=>vEru zs6pSI6xNt68IHN^K7JV>eUex(y~R3w^a11Pn062!u$}5ITxYJGwc94~c|$)3*!E${#2d5lW{j>(n{o)t(U-!99~jC z=w5IKb^C|d+Qrfge$JL_bH6yl{eSjezX_i0M8CN1LLH!XtYKAgQbpC6d7`)iTC&mA-`TyU z=w87Wj-_P6vJW%U)&WnjoBfC}Zv#tsi=XzB8e$L)(9e5wU1{GU*3B$zNm_+2c@~!v zwrpnPo2#``1`&uXK@5m9IfqM}RD9~NrF7u2L zs=Pb_BERIz`8n!l-4DC~&LpQB{J%dHCl=?BJZ~Jh%ZvxRWa+ABZd_%XM(O(0xJ^z9 zBRoFWdHi`y@?4sb-?dxG>$U_drzn5^7v$x=QzEHYc<{Fc8enRO(v?!rgdERRB;%jK zExkkg%~)c8dUX*zzdWWLD_}RrZcZ0hgf4jk9>6*Qeop39*25y_iK|0A;ZH0;5l*ur z0Hs(!gu{HGc}hKLQBAeBjaYy9uj!l=l7){gvs+Txlyr)Y$f#QcOXAjggZ{g3A!1&m zWJ39H3~iluFpfjSg2_t_GE7YQ*ee-)p^kJ$uh;O85MB#r13!P6IBD3KrZ3b0TJWCR z$4Vq3N?xxOe+g{9*UDAYrqF1(KiF(@(egeduR7t7xc{SYKqkQzfABCK3v7v+^jagB zoqu0-w4Ey=t7}j)2wa7WzXkO+%TB!2G)kx8!V8;7_4TXg4>H^p+Mc`iA_1SA@Kp|M z7_UEMVP(=Ha{g#Gc< zimTj1NuMuq&=sd623hAv5|fa~7nVd1Pk3eZsy#`~8@!P^jkRQm;|`CAczMap^W)%2 z-@!n-UPjOkcdZ&m&0t5e9>{t$UE}JOUY$KsF#60jMYO^^EAZ?AgPz42$?YvMgU_kRDUwX@B*5YNGLiXt-YEHgXH#sv52 zTuhwkV7&do!GSyJiDj1GGunYaJJZ5)a=50<^-B0U`)ca^x$zXUP!vu~W&CeV^*>6_ ze|_?yvLKO>*cKNqNX(p3@)9f=mLM=jb?a@qT77~YCZ!w%sGH%$>`J>DJivC>Cm$47G z!Y;h$3108Zs)Vrb@po#=St`oikmZ@(o|@=QhL`;NSmmRO+WNVUu`rw#ftg-Oxo{m` z`BsTy&`oGKkYa-l5VeXx25Ncc0eK13s}0op5;8YUv90si%AFT89s=8eXXdr>Jj47k zYa-YRO+Wsoa+F&|bD#Fb6~s0ruO5G^Vz$9At=ih_KfbUpa`)T$4a`GpRpDS zVWi(QT0m0+=?gyP!e2^2w|?2CyV(I22Wy3d&l0ImWyy?3(rq~Fgth<|WP%3A7p z=&WMeFHn)uD*V~+_#PpWoBb*zra`MQnKSm%<)z+9+^WP`x7)%+m*7q`8&1`t)@Kg{ znwi+q+ocyE8WF9rU+hHsf4%w~XrpdbJ*BA?$b=Orz94^TKjff>u=H~s-uq@K|L6H} z!<}!LMXT$YL-Xo75~%rqHI0hIFP?K}HRO&b{%PGbp6Q5bPpqpu|9GgWd3{Y#V0QlF zM5~ybQ_ZB4#`8xT-6>Dq#!x?w6Bvy&#Hk*-0>#>en&&GL`oH<+3wl27 zc(i++)0!V$k&7S5R7LlK)ed5#w_LKx(LV||4&QGd(rPe5Q$lVvG^_vZ2S%2}YYHIH zj!~spGDfu721Btuf$H?)S;;ji(<-bFU<*3zJc>Q+$6opCihM4aC#V!TiG1gVX44ZE z6RV+b<8^e+UP?_%lgc>!<9pRhGbrEpt$I)!C(i!QEtm5=h-vK4tA1~`W!x_$fSQsP KxctRy*#7~9#u2js diff --git a/DOCS/html/stm32f407xx__matlab_8h_source.html b/DOCS/html/stm32f407xx__matlab_8h_source.html deleted file mode 100644 index f329ca1..0000000 --- a/DOCS/html/stm32f407xx__matlab_8h_source.html +++ /dev/null @@ -1,15592 +0,0 @@ - - - - - - - -STM MATLAB Simulator: F:/Work/Projects/MATLAB/matlab_stm_emulate/MCU_STM32F4xx_Matlab/Drivers/CMSIS/stm32f407xx_matlab.h Source File - - - - - - - - - - - -
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    1/************************************************************************
    -
    2Данный файл ÑвлÑетÑÑ ÐºÐ¾Ð¿Ð¸ÐµÐ¹ stm32f407xx.h Ñ Ð½ÐµÐºÐ¾Ñ‚Ð¾Ñ€Ñ‹Ð¼Ð¸ изменениÑми:
    -
    3- добавлен кейловÑкий stdint.h (через "", вмеÑто <>) (~170)
    -
    4- добавлен cmsis_armcc_matlab.h Ñ Ð´ÐµÑ„Ð°Ð¹Ð½Ð°Ð¼Ð¸ из оригинального cmsis_armcc.h (~170)
    -
    5- добавлен core_cm4.h Ñ Ð´ÐµÑ„Ð°Ð¹Ð½Ð°Ð¼Ð¸ из оригинального core_cm4.h (~170)
    -
    6- добавлена Ñтруктура Ð¸Ð¼Ð¸Ñ‚Ð¸Ñ€ÑƒÑŽÑ‰Ð°Ñ Ð¿Ð°Ð¼ÑÑ‚ÑŒ МК (Ð´Ð»Ñ Ñ€Ð°Ð±Ð¾Ñ‚Ñ‹ дефайнов адреÑов региÑтров) (~950)
    -
    7 (надо допилить)
    -
    8Ðеобходимо допилить поддержку вÑех дефайнов, которые объÑвлÑÑŽÑ‚ÑÑ Ð²
    -
    9arm_acle.h, arm_compat.h, cmsis_armclang.h, cmsis_compiler.h, cmsis_version.h,
    -
    10core_cm4.h, mpu_armv7.h, stddef
    -
    11**************************************************************************/
    -
    44#ifndef __STM32F407xx_H
    -
    45#define __STM32F407xx_H
    -
    46
    -
    47#ifdef __cplusplus
    -
    48 extern "C" {
    -
    49#endif /* __cplusplus */
    -
    50
    -
    58#define __CM4_REV 0x0001U
    -
    59#define __MPU_PRESENT 1U
    -
    60#define __NVIC_PRIO_BITS 4U
    -
    61#define __Vendor_SysTickConfig 0U
    -
    62#define __FPU_PRESENT 1U
    -
    -
    76typedef enum
    -
    77{
    -
    78/****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
    -
    79 NonMaskableInt_IRQn = -14,
    -
    80 MemoryManagement_IRQn = -12,
    -
    81 BusFault_IRQn = -11,
    -
    82 UsageFault_IRQn = -10,
    -
    83 SVCall_IRQn = -5,
    -
    84 DebugMonitor_IRQn = -4,
    -
    85 PendSV_IRQn = -2,
    -
    86 SysTick_IRQn = -1,
    -
    87/****** STM32 specific Interrupt Numbers **********************************************************************/
    -
    88 WWDG_IRQn = 0,
    -
    89 PVD_IRQn = 1,
    -
    90 TAMP_STAMP_IRQn = 2,
    -
    91 RTC_WKUP_IRQn = 3,
    -
    92 FLASH_IRQn = 4,
    -
    93 RCC_IRQn = 5,
    -
    94 EXTI0_IRQn = 6,
    -
    95 EXTI1_IRQn = 7,
    -
    96 EXTI2_IRQn = 8,
    -
    97 EXTI3_IRQn = 9,
    -
    98 EXTI4_IRQn = 10,
    -
    99 DMA1_Stream0_IRQn = 11,
    -
    100 DMA1_Stream1_IRQn = 12,
    -
    101 DMA1_Stream2_IRQn = 13,
    -
    102 DMA1_Stream3_IRQn = 14,
    -
    103 DMA1_Stream4_IRQn = 15,
    -
    104 DMA1_Stream5_IRQn = 16,
    -
    105 DMA1_Stream6_IRQn = 17,
    -
    106 ADC_IRQn = 18,
    -
    107 CAN1_TX_IRQn = 19,
    -
    108 CAN1_RX0_IRQn = 20,
    -
    109 CAN1_RX1_IRQn = 21,
    -
    110 CAN1_SCE_IRQn = 22,
    -
    111 EXTI9_5_IRQn = 23,
    -
    112 TIM1_BRK_TIM9_IRQn = 24,
    -
    113 TIM1_UP_TIM10_IRQn = 25,
    -
    114 TIM1_TRG_COM_TIM11_IRQn = 26,
    -
    115 TIM1_CC_IRQn = 27,
    -
    116 TIM2_IRQn = 28,
    -
    117 TIM3_IRQn = 29,
    -
    118 TIM4_IRQn = 30,
    -
    119 I2C1_EV_IRQn = 31,
    -
    120 I2C1_ER_IRQn = 32,
    -
    121 I2C2_EV_IRQn = 33,
    -
    122 I2C2_ER_IRQn = 34,
    -
    123 SPI1_IRQn = 35,
    -
    124 SPI2_IRQn = 36,
    -
    125 USART1_IRQn = 37,
    -
    126 USART2_IRQn = 38,
    -
    127 USART3_IRQn = 39,
    -
    128 EXTI15_10_IRQn = 40,
    -
    129 RTC_Alarm_IRQn = 41,
    -
    130 OTG_FS_WKUP_IRQn = 42,
    -
    131 TIM8_BRK_TIM12_IRQn = 43,
    -
    132 TIM8_UP_TIM13_IRQn = 44,
    -
    133 TIM8_TRG_COM_TIM14_IRQn = 45,
    -
    134 TIM8_CC_IRQn = 46,
    -
    135 DMA1_Stream7_IRQn = 47,
    -
    136 FSMC_IRQn = 48,
    -
    137 SDIO_IRQn = 49,
    -
    138 TIM5_IRQn = 50,
    -
    139 SPI3_IRQn = 51,
    -
    140 UART4_IRQn = 52,
    -
    141 UART5_IRQn = 53,
    -
    142 TIM6_DAC_IRQn = 54,
    -
    143 TIM7_IRQn = 55,
    -
    144 DMA2_Stream0_IRQn = 56,
    -
    145 DMA2_Stream1_IRQn = 57,
    -
    146 DMA2_Stream2_IRQn = 58,
    -
    147 DMA2_Stream3_IRQn = 59,
    -
    148 DMA2_Stream4_IRQn = 60,
    -
    149 ETH_IRQn = 61,
    -
    150 ETH_WKUP_IRQn = 62,
    -
    151 CAN2_TX_IRQn = 63,
    -
    152 CAN2_RX0_IRQn = 64,
    -
    153 CAN2_RX1_IRQn = 65,
    -
    154 CAN2_SCE_IRQn = 66,
    -
    155 OTG_FS_IRQn = 67,
    -
    156 DMA2_Stream5_IRQn = 68,
    -
    157 DMA2_Stream6_IRQn = 69,
    -
    158 DMA2_Stream7_IRQn = 70,
    -
    159 USART6_IRQn = 71,
    -
    160 I2C3_EV_IRQn = 72,
    -
    161 I2C3_ER_IRQn = 73,
    -
    162 OTG_HS_EP1_OUT_IRQn = 74,
    -
    163 OTG_HS_EP1_IN_IRQn = 75,
    -
    164 OTG_HS_WKUP_IRQn = 76,
    -
    165 OTG_HS_IRQn = 77,
    -
    166 DCMI_IRQn = 78,
    -
    167 RNG_IRQn = 80,
    -
    168 FPU_IRQn = 81
    -
    169} IRQn_Type;
    -
    -
    170/* Legacy define */
    -
    171#define HASH_RNG_IRQn RNG_IRQn
    -
    172
    -
    177#include "stdint.h"
    -
    178#include "arm_defines.h"
    -
    179#include "core_cm4_matlab.h" /* Cortex-M4 processor and core peripherals */
    -
    180#include "system_stm32f4xx.h"
    -
    181
    - -
    213
    - -
    221
    -
    222
    - -
    234
    - -
    246
    -
    -
    251typedef struct
    -
    252{
    -
    253 __IO uint32_t FR1;
    -
    254 __IO uint32_t FR2;
    -
    255} CAN_FilterRegister_TypeDef;
    -
    -
    256
    - -
    286
    - -
    299
    - -
    321
    - -
    333
    - -
    352
    - -
    366
    - -
    374
    -
    -
    379typedef struct
    -
    380{
    -
    381 __IO uint32_t MACCR;
    -
    382 __IO uint32_t MACFFR;
    -
    383 __IO uint32_t MACHTHR;
    -
    384 __IO uint32_t MACHTLR;
    -
    385 __IO uint32_t MACMIIAR;
    -
    386 __IO uint32_t MACMIIDR;
    -
    387 __IO uint32_t MACFCR;
    -
    388 __IO uint32_t MACVLANTR; /* 8 */
    -
    389 uint32_t RESERVED0[2];
    -
    390 __IO uint32_t MACRWUFFR; /* 11 */
    -
    391 __IO uint32_t MACPMTCSR;
    -
    392 uint32_t RESERVED1;
    -
    393 __IO uint32_t MACDBGR;
    -
    394 __IO uint32_t MACSR; /* 15 */
    -
    395 __IO uint32_t MACIMR;
    -
    396 __IO uint32_t MACA0HR;
    -
    397 __IO uint32_t MACA0LR;
    -
    398 __IO uint32_t MACA1HR;
    -
    399 __IO uint32_t MACA1LR;
    -
    400 __IO uint32_t MACA2HR;
    -
    401 __IO uint32_t MACA2LR;
    -
    402 __IO uint32_t MACA3HR;
    -
    403 __IO uint32_t MACA3LR; /* 24 */
    -
    404 uint32_t RESERVED2[40];
    -
    405 __IO uint32_t MMCCR; /* 65 */
    -
    406 __IO uint32_t MMCRIR;
    -
    407 __IO uint32_t MMCTIR;
    -
    408 __IO uint32_t MMCRIMR;
    -
    409 __IO uint32_t MMCTIMR; /* 69 */
    -
    410 uint32_t RESERVED3[14];
    -
    411 __IO uint32_t MMCTGFSCCR; /* 84 */
    -
    412 __IO uint32_t MMCTGFMSCCR;
    -
    413 uint32_t RESERVED4[5];
    -
    414 __IO uint32_t MMCTGFCR;
    -
    415 uint32_t RESERVED5[10];
    -
    416 __IO uint32_t MMCRFCECR;
    -
    417 __IO uint32_t MMCRFAECR;
    -
    418 uint32_t RESERVED6[10];
    -
    419 __IO uint32_t MMCRGUFCR;
    -
    420 uint32_t RESERVED7[334];
    -
    421 __IO uint32_t PTPTSCR;
    -
    422 __IO uint32_t PTPSSIR;
    -
    423 __IO uint32_t PTPTSHR;
    -
    424 __IO uint32_t PTPTSLR;
    -
    425 __IO uint32_t PTPTSHUR;
    -
    426 __IO uint32_t PTPTSLUR;
    -
    427 __IO uint32_t PTPTSAR;
    -
    428 __IO uint32_t PTPTTHR;
    -
    429 __IO uint32_t PTPTTLR;
    -
    430 __IO uint32_t RESERVED8;
    -
    431 __IO uint32_t PTPTSSR;
    -
    432 uint32_t RESERVED9[565];
    -
    433 __IO uint32_t DMABMR;
    -
    434 __IO uint32_t DMATPDR;
    -
    435 __IO uint32_t DMARPDR;
    -
    436 __IO uint32_t DMARDLAR;
    -
    437 __IO uint32_t DMATDLAR;
    -
    438 __IO uint32_t DMASR;
    -
    439 __IO uint32_t DMAOMR;
    -
    440 __IO uint32_t DMAIER;
    -
    441 __IO uint32_t DMAMFBOCR;
    -
    442 __IO uint32_t DMARSWTR;
    -
    443 uint32_t RESERVED10[8];
    -
    444 __IO uint32_t DMACHTDR;
    -
    445 __IO uint32_t DMACHRDR;
    -
    446 __IO uint32_t DMACHTBAR;
    -
    447 __IO uint32_t DMACHRBAR;
    -
    448} ETH_TypeDef;
    -
    -
    449
    - -
    463
    - -
    478
    -
    479
    -
    480
    -
    -
    485typedef struct
    -
    486{
    -
    487 __IO uint32_t BTCR[8];
    -
    488} FSMC_Bank1_TypeDef;
    -
    -
    489
    -
    -
    494typedef struct
    -
    495{
    -
    496 __IO uint32_t BWTR[7];
    -
    497} FSMC_Bank1E_TypeDef;
    -
    -
    498
    - -
    520
    - -
    533
    - -
    550
    -
    -
    555typedef struct
    -
    556{
    -
    557 __IO uint32_t MEMRMP;
    -
    558 __IO uint32_t PMC;
    -
    559 __IO uint32_t EXTICR[4];
    -
    560 uint32_t RESERVED[2];
    -
    561 __IO uint32_t CMPCR;
    -
    562} SYSCFG_TypeDef;
    -
    -
    563
    - -
    580
    - -
    592
    -
    593
    -
    -
    598typedef struct
    -
    599{
    -
    600 __IO uint32_t CR;
    -
    601 __IO uint32_t CSR;
    -
    602} PWR_TypeDef;
    -
    -
    603
    - -
    641
    - -
    689
    - -
    717
    - -
    734
    -
    735
    - -
    764
    - -
    779
    -
    -
    784typedef struct
    -
    785{
    -
    786 __IO uint32_t CR;
    -
    787 __IO uint32_t CFR;
    -
    788 __IO uint32_t SR;
    -
    789} WWDG_TypeDef;
    -
    -
    790
    -
    -
    795typedef struct
    -
    796{
    -
    797 __IO uint32_t CR;
    -
    798 __IO uint32_t SR;
    -
    799 __IO uint32_t DR;
    -
    800} RNG_TypeDef;
    -
    -
    801
    - -
    826
    - -
    853
    - -
    868
    - -
    882
    - -
    896
    - -
    910
    -
    918#define FLASH_BASE_SHIFT 0x08000000UL
    -
    919#define FLASH_END_SHIFT 0x080FFFFFUL
    -
    920#define CCMDATARAM_BASE_SHIFT 0x10000000UL
    -
    921#define CCMDATARAM_END_SHIFT 0x1000FFFFUL
    -
    922#define FLASH_OTP_BASE_SHIFT 0x1FFF7800UL
    -
    923#define FLASH_OTP_END_SHIFT 0x1FFF7A0FUL
    -
    924#define SRAM1_BASE_SHIFT 0x20000000UL
    -
    925#define SRAM2_BASE_SHIFT 0x2001C000UL
    -
    926#define SRAM1_BB_BASE_SHIFT 0x22000000UL
    -
    927#define SRAM2_BB_BASE_SHIFT 0x22380000UL
    -
    928#define PERIPH_BASE_SHIFT 0x40000000UL
    -
    929#define BKPSRAM_BASE_SHIFT 0x40024000UL
    -
    930#define PERIPH_BB_BASE_SHIFT 0x42000000UL
    -
    931#define BKPSRAM_BB_BASE_SHIFT 0x42480000UL
    -
    932#define FSMC_R_BASE_SHIFT 0xA0000000UL
    -
    934#define MCU_MEM_END 0xA0000FFFUL
    -
    936#define CCMDATARAM_SIZE 0x10000UL /* (64 KB) */
    -
    937#define SRAM1_SIZE 0x1C000UL /* (112 KB) */
    -
    938#define SRAM2_SIZE 0x4000UL /* (16 KB) */
    -
    939#define BKPSRAM_SIZE 0x1000UL /* (4 KB) */
    -
    940
    -
    941#define FLASH_SIZE (CCMDATARAM_BASE_SHIFT - FLASH_BASE_SHIFT)
    -
    942//#define CCMDATARAM_SIZE (FLASH_OTP_BASE_SHIFT - CCMDATARAM_BASE_SHIFT)
    -
    943#define FLASH_OTP_SIZE (SRAM1_BASE_SHIFT - FLASH_OTP_BASE_SHIFT)
    -
    944//#define SRAM1_SIZE (SRAM2_BASE_SHIFT - SRAM1_BASE_SHIFT)
    -
    945//#define SRAM2_SIZE (SRAM1_BB_BASE_SHIFT - SRAM2_BASE_SHIFT)
    -
    946#define SRAM1_BB_SIZE (SRAM2_BB_BASE_SHIFT - SRAM1_BB_BASE_SHIFT)
    -
    947#define SRAM2_BB_SIZE (PERIPH_BASE_SHIFT - SRAM2_BB_BASE_SHIFT)
    -
    948#define PERIPH_SIZE (BKPSRAM_BASE_SHIFT - PERIPH_BASE_SHIFT)
    -
    949//#define BKPSRAM_SIZE (PERIPH_BB_BASE_SHIFT - BKPSRAM_BASE_SHIFT)
    -
    950#define PERIPH_BB_SIZE (BKPSRAM_BB_BASE_SHIFT - PERIPH_BB_BASE_SHIFT)
    -
    951//#define BKPSRAM_BB_SIZE (FSMC_R_BASE_SHIFT - BKPSRAM_BB_BASE_SHIFT)
    -
    952#define FSMC_R_SIZE (MCU_MEM_END - FSMC_R_BASE_SHIFT)
    -
    953
    -
    954
    - -
    972extern MCU_MemoryTypeDef MCU_MEM;
    -
    973DBGMCU_TypeDef DEBUG_MCU;
    -
    974
    -
    978#define FLASH_BASE (MCU_MEM.CCMDATARAM_BASE)
    -
    979#define CCMDATARAM_BASE (MCU_MEM.CCMDATARAM_BASE)
    -
    980#define SRAM1_BASE (MCU_MEM.SRAM1_BASE)
    -
    981#define SRAM2_BASE (MCU_MEM.SRAM2_BASE)
    -
    982#define PERIPH_BASE (MCU_MEM.PERIPH_BASE)
    -
    983#define BKPSRAM_BASE (MCU_MEM.BKPSRAM_BASE)
    -
    984#define FSMC_R_BASE (MCU_MEM.FSMC_R_BASE)
    -
    985#define SRAM1_BB_BASE (MCU_MEM.SRAM1_BB_BASE)
    -
    986#define SRAM2_BB_BASE (MCU_MEM.SRAM2_BB_BASE)
    -
    987#define PERIPH_BB_BASE (MCU_MEM.PERIPH_BB_BASE)
    -
    988#define BKPSRAM_BB_BASE (MCU_MEM.BKPSRAM_BB_BASE)
    -
    989#define FLASH_END (MCU_MEM.FLASH_END)
    -
    990#define FLASH_OTP_BASE (MCU_MEM.FLASH_OTP_BASE)
    -
    991#define FLASH_OTP_END (MCU_MEM.FLASH_OTP_END)
    -
    992#define CCMDATARAM_END (MCU_MEM.CCMDATARAM_END)
    -
    994 /* Legacy defines */
    -
    995#define SRAM_BASE SRAM1_BASE
    -
    996#define SRAM_BB_BASE SRAM1_BB_BASE
    -
    997
    -
    999#define APB1PERIPH_BASE PERIPH_BASE
    -
    1000#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL)
    -
    1001#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL)
    -
    1002#define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000UL)
    -
    1003
    -
    1005#define TIM2_BASE (APB1PERIPH_BASE + 0x0000UL)
    -
    1006#define TIM3_BASE (APB1PERIPH_BASE + 0x0400UL)
    -
    1007#define TIM4_BASE (APB1PERIPH_BASE + 0x0800UL)
    -
    1008#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00UL)
    -
    1009#define TIM6_BASE (APB1PERIPH_BASE + 0x1000UL)
    -
    1010#define TIM7_BASE (APB1PERIPH_BASE + 0x1400UL)
    -
    1011#define TIM12_BASE (APB1PERIPH_BASE + 0x1800UL)
    -
    1012#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00UL)
    -
    1013#define TIM14_BASE (APB1PERIPH_BASE + 0x2000UL)
    -
    1014#define RTC_BASE (APB1PERIPH_BASE + 0x2800UL)
    -
    1015#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00UL)
    -
    1016#define IWDG_BASE (APB1PERIPH_BASE + 0x3000UL)
    -
    1017#define I2S2ext_BASE (APB1PERIPH_BASE + 0x3400UL)
    -
    1018#define SPI2_BASE (APB1PERIPH_BASE + 0x3800UL)
    -
    1019#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00UL)
    -
    1020#define I2S3ext_BASE (APB1PERIPH_BASE + 0x4000UL)
    -
    1021#define USART2_BASE (APB1PERIPH_BASE + 0x4400UL)
    -
    1022#define USART3_BASE (APB1PERIPH_BASE + 0x4800UL)
    -
    1023#define UART4_BASE (APB1PERIPH_BASE + 0x4C00UL)
    -
    1024#define UART5_BASE (APB1PERIPH_BASE + 0x5000UL)
    -
    1025#define I2C1_BASE (APB1PERIPH_BASE + 0x5400UL)
    -
    1026#define I2C2_BASE (APB1PERIPH_BASE + 0x5800UL)
    -
    1027#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00UL)
    -
    1028#define CAN1_BASE (APB1PERIPH_BASE + 0x6400UL)
    -
    1029#define CAN2_BASE (APB1PERIPH_BASE + 0x6800UL)
    -
    1030#define PWR_BASE (APB1PERIPH_BASE + 0x7000UL)
    -
    1031#define DAC_BASE (APB1PERIPH_BASE + 0x7400UL)
    -
    1032
    -
    1034#define TIM1_BASE (APB2PERIPH_BASE + 0x0000UL)
    -
    1035#define TIM8_BASE (APB2PERIPH_BASE + 0x0400UL)
    -
    1036#define USART1_BASE (APB2PERIPH_BASE + 0x1000UL)
    -
    1037#define USART6_BASE (APB2PERIPH_BASE + 0x1400UL)
    -
    1038#define ADC1_BASE (APB2PERIPH_BASE + 0x2000UL)
    -
    1039#define ADC2_BASE (APB2PERIPH_BASE + 0x2100UL)
    -
    1040#define ADC3_BASE (APB2PERIPH_BASE + 0x2200UL)
    -
    1041#define ADC123_COMMON_BASE (APB2PERIPH_BASE + 0x2300UL)
    -
    1042/* Legacy define */
    -
    1043#define ADC_BASE ADC123_COMMON_BASE
    -
    1044#define SDIO_BASE (APB2PERIPH_BASE + 0x2C00UL)
    -
    1045#define SPI1_BASE (APB2PERIPH_BASE + 0x3000UL)
    -
    1046#define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800UL)
    -
    1047#define EXTI_BASE (APB2PERIPH_BASE + 0x3C00UL)
    -
    1048#define TIM9_BASE (APB2PERIPH_BASE + 0x4000UL)
    -
    1049#define TIM10_BASE (APB2PERIPH_BASE + 0x4400UL)
    -
    1050#define TIM11_BASE (APB2PERIPH_BASE + 0x4800UL)
    -
    1051
    -
    1053#define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000UL)
    -
    1054#define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400UL)
    -
    1055#define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800UL)
    -
    1056#define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00UL)
    -
    1057#define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000UL)
    -
    1058#define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400UL)
    -
    1059#define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800UL)
    -
    1060#define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00UL)
    -
    1061#define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000UL)
    -
    1062#define CRC_BASE (AHB1PERIPH_BASE + 0x3000UL)
    -
    1063#define RCC_BASE (AHB1PERIPH_BASE + 0x3800UL)
    -
    1064#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00UL)
    -
    1065#define DMA1_BASE (AHB1PERIPH_BASE + 0x6000UL)
    -
    1066#define DMA1_Stream0_BASE (DMA1_BASE + 0x010UL)
    -
    1067#define DMA1_Stream1_BASE (DMA1_BASE + 0x028UL)
    -
    1068#define DMA1_Stream2_BASE (DMA1_BASE + 0x040UL)
    -
    1069#define DMA1_Stream3_BASE (DMA1_BASE + 0x058UL)
    -
    1070#define DMA1_Stream4_BASE (DMA1_BASE + 0x070UL)
    -
    1071#define DMA1_Stream5_BASE (DMA1_BASE + 0x088UL)
    -
    1072#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0UL)
    -
    1073#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8UL)
    -
    1074#define DMA2_BASE (AHB1PERIPH_BASE + 0x6400UL)
    -
    1075#define DMA2_Stream0_BASE (DMA2_BASE + 0x010UL)
    -
    1076#define DMA2_Stream1_BASE (DMA2_BASE + 0x028UL)
    -
    1077#define DMA2_Stream2_BASE (DMA2_BASE + 0x040UL)
    -
    1078#define DMA2_Stream3_BASE (DMA2_BASE + 0x058UL)
    -
    1079#define DMA2_Stream4_BASE (DMA2_BASE + 0x070UL)
    -
    1080#define DMA2_Stream5_BASE (DMA2_BASE + 0x088UL)
    -
    1081#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0UL)
    -
    1082#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8UL)
    -
    1083#define ETH_BASE (AHB1PERIPH_BASE + 0x8000UL)
    -
    1084#define ETH_MAC_BASE (ETH_BASE)
    -
    1085#define ETH_MMC_BASE (ETH_BASE + 0x0100UL)
    -
    1086#define ETH_PTP_BASE (ETH_BASE + 0x0700UL)
    -
    1087#define ETH_DMA_BASE (ETH_BASE + 0x1000UL)
    -
    1088
    -
    1090#define DCMI_BASE (AHB2PERIPH_BASE + 0x50000UL)
    -
    1091#define RNG_BASE (AHB2PERIPH_BASE + 0x60800UL)
    -
    1092
    -
    1094#define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000UL)
    -
    1095#define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104UL)
    -
    1096#define FSMC_Bank2_3_R_BASE (FSMC_R_BASE + 0x0060UL)
    -
    1097#define FSMC_Bank4_R_BASE (FSMC_R_BASE + 0x00A0UL)
    -
    1098
    -
    1099
    -
    1101#define DBGMCU_BASE (&DEBUG_MCU)
    -
    1103#define USB_OTG_HS_PERIPH_BASE 0x40040000UL
    -
    1104#define USB_OTG_FS_PERIPH_BASE 0x50000000UL
    -
    1105
    -
    1106#define USB_OTG_GLOBAL_BASE 0x000UL
    -
    1107#define USB_OTG_DEVICE_BASE 0x800UL
    -
    1108#define USB_OTG_IN_ENDPOINT_BASE 0x900UL
    -
    1109#define USB_OTG_OUT_ENDPOINT_BASE 0xB00UL
    -
    1110#define USB_OTG_EP_REG_SIZE 0x20UL
    -
    1111#define USB_OTG_HOST_BASE 0x400UL
    -
    1112#define USB_OTG_HOST_PORT_BASE 0x440UL
    -
    1113#define USB_OTG_HOST_CHANNEL_BASE 0x500UL
    -
    1114#define USB_OTG_HOST_CHANNEL_SIZE 0x20UL
    -
    1115#define USB_OTG_PCGCCTL_BASE 0xE00UL
    -
    1116#define USB_OTG_FIFO_BASE 0x1000UL
    -
    1117#define USB_OTG_FIFO_SIZE 0x1000UL
    -
    1118
    -
    1119#define UID_BASE 0x1FFF7A10UL
    -
    1120#define FLASHSIZE_BASE 0x1FFF7A22UL
    -
    1121#define PACKAGE_BASE 0x1FFF7BF0UL
    -
    1129#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
    -
    1130#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
    -
    1131#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
    -
    1132#define TIM5 ((TIM_TypeDef *) TIM5_BASE)
    -
    1133#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
    -
    1134#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
    -
    1135#define TIM12 ((TIM_TypeDef *) TIM12_BASE)
    -
    1136#define TIM13 ((TIM_TypeDef *) TIM13_BASE)
    -
    1137#define TIM14 ((TIM_TypeDef *) TIM14_BASE)
    -
    1138#define RTC ((RTC_TypeDef *) RTC_BASE)
    -
    1139#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
    -
    1140#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
    -
    1141#define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE)
    -
    1142#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
    -
    1143#define SPI3 ((SPI_TypeDef *) SPI3_BASE)
    -
    1144#define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE)
    -
    1145#define USART2 ((USART_TypeDef *) USART2_BASE)
    -
    1146#define USART3 ((USART_TypeDef *) USART3_BASE)
    -
    1147#define UART4 ((USART_TypeDef *) UART4_BASE)
    -
    1148#define UART5 ((USART_TypeDef *) UART5_BASE)
    -
    1149#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
    -
    1150#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
    -
    1151#define I2C3 ((I2C_TypeDef *) I2C3_BASE)
    -
    1152#define CAN1 ((CAN_TypeDef *) CAN1_BASE)
    -
    1153#define CAN2 ((CAN_TypeDef *) CAN2_BASE)
    -
    1154#define PWR ((PWR_TypeDef *) PWR_BASE)
    -
    1155#define DAC1 ((DAC_TypeDef *) DAC_BASE)
    -
    1156#define DAC ((DAC_TypeDef *) DAC_BASE) /* Kept for legacy purpose */
    -
    1157#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
    -
    1158#define TIM8 ((TIM_TypeDef *) TIM8_BASE)
    -
    1159#define USART1 ((USART_TypeDef *) USART1_BASE)
    -
    1160#define USART6 ((USART_TypeDef *) USART6_BASE)
    -
    1161#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
    -
    1162#define ADC2 ((ADC_TypeDef *) ADC2_BASE)
    -
    1163#define ADC3 ((ADC_TypeDef *) ADC3_BASE)
    -
    1164#define ADC123_COMMON ((ADC_Common_TypeDef *) ADC123_COMMON_BASE)
    -
    1165 /* Legacy define */
    -
    1166#define ADC ADC123_COMMON
    -
    1167#define SDIO ((SDIO_TypeDef *) SDIO_BASE)
    -
    1168#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
    -
    1169#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
    -
    1170#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
    -
    1171#define TIM9 ((TIM_TypeDef *) TIM9_BASE)
    -
    1172#define TIM10 ((TIM_TypeDef *) TIM10_BASE)
    -
    1173#define TIM11 ((TIM_TypeDef *) TIM11_BASE)
    -
    1174#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
    -
    1175#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
    -
    1176#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
    -
    1177#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
    -
    1178#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
    -
    1179#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
    -
    1180#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
    -
    1181#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
    -
    1182#define GPIOI ((GPIO_TypeDef *) GPIOI_BASE)
    -
    1183#define CRC ((CRC_TypeDef *) CRC_BASE)
    -
    1184#define RCC ((RCC_TypeDef *) RCC_BASE)
    -
    1185#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
    -
    1186#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
    -
    1187#define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
    -
    1188#define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
    -
    1189#define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
    -
    1190#define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
    -
    1191#define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
    -
    1192#define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
    -
    1193#define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
    -
    1194#define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
    -
    1195#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
    -
    1196#define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
    -
    1197#define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
    -
    1198#define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
    -
    1199#define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
    -
    1200#define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
    -
    1201#define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
    -
    1202#define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
    -
    1203#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
    -
    1204#define ETH ((ETH_TypeDef *) ETH_BASE)
    -
    1205#define DCMI ((DCMI_TypeDef *) DCMI_BASE)
    -
    1206#define RNG ((RNG_TypeDef *) RNG_BASE)
    -
    1207#define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE)
    -
    1208#define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE)
    -
    1209#define FSMC_Bank2_3 ((FSMC_Bank2_3_TypeDef *) FSMC_Bank2_3_R_BASE)
    -
    1210#define FSMC_Bank4 ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE)
    -
    1211#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
    -
    1212#define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
    -
    1213#define USB_OTG_HS ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE)
    -
    1214
    -
    1226#define LSI_STARTUP_TIME 40U
    -
    1235/******************************************************************************/
    -
    1236/* Peripheral Registers_Bits_Definition */
    -
    1237/******************************************************************************/
    -
    1238
    -
    1239/******************************************************************************/
    -
    1240/* */
    -
    1241/* Analog to Digital Converter */
    -
    1242/* */
    -
    1243/******************************************************************************/
    -
    1244/*
    -
    1245 * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
    -
    1246 */
    -
    1247#define ADC_MULTIMODE_SUPPORT
    -
    1249/******************** Bit definition for ADC_SR register ********************/
    -
    1250#define ADC_SR_AWD_Pos (0U)
    -
    1251#define ADC_SR_AWD_Msk (0x1UL << ADC_SR_AWD_Pos)
    -
    1252#define ADC_SR_AWD ADC_SR_AWD_Msk
    -
    1253#define ADC_SR_EOC_Pos (1U)
    -
    1254#define ADC_SR_EOC_Msk (0x1UL << ADC_SR_EOC_Pos)
    -
    1255#define ADC_SR_EOC ADC_SR_EOC_Msk
    -
    1256#define ADC_SR_JEOC_Pos (2U)
    -
    1257#define ADC_SR_JEOC_Msk (0x1UL << ADC_SR_JEOC_Pos)
    -
    1258#define ADC_SR_JEOC ADC_SR_JEOC_Msk
    -
    1259#define ADC_SR_JSTRT_Pos (3U)
    -
    1260#define ADC_SR_JSTRT_Msk (0x1UL << ADC_SR_JSTRT_Pos)
    -
    1261#define ADC_SR_JSTRT ADC_SR_JSTRT_Msk
    -
    1262#define ADC_SR_STRT_Pos (4U)
    -
    1263#define ADC_SR_STRT_Msk (0x1UL << ADC_SR_STRT_Pos)
    -
    1264#define ADC_SR_STRT ADC_SR_STRT_Msk
    -
    1265#define ADC_SR_OVR_Pos (5U)
    -
    1266#define ADC_SR_OVR_Msk (0x1UL << ADC_SR_OVR_Pos)
    -
    1267#define ADC_SR_OVR ADC_SR_OVR_Msk
    -
    1269/******************* Bit definition for ADC_CR1 register ********************/
    -
    1270#define ADC_CR1_AWDCH_Pos (0U)
    -
    1271#define ADC_CR1_AWDCH_Msk (0x1FUL << ADC_CR1_AWDCH_Pos)
    -
    1272#define ADC_CR1_AWDCH ADC_CR1_AWDCH_Msk
    -
    1273#define ADC_CR1_AWDCH_0 (0x01UL << ADC_CR1_AWDCH_Pos)
    -
    1274#define ADC_CR1_AWDCH_1 (0x02UL << ADC_CR1_AWDCH_Pos)
    -
    1275#define ADC_CR1_AWDCH_2 (0x04UL << ADC_CR1_AWDCH_Pos)
    -
    1276#define ADC_CR1_AWDCH_3 (0x08UL << ADC_CR1_AWDCH_Pos)
    -
    1277#define ADC_CR1_AWDCH_4 (0x10UL << ADC_CR1_AWDCH_Pos)
    -
    1278#define ADC_CR1_EOCIE_Pos (5U)
    -
    1279#define ADC_CR1_EOCIE_Msk (0x1UL << ADC_CR1_EOCIE_Pos)
    -
    1280#define ADC_CR1_EOCIE ADC_CR1_EOCIE_Msk
    -
    1281#define ADC_CR1_AWDIE_Pos (6U)
    -
    1282#define ADC_CR1_AWDIE_Msk (0x1UL << ADC_CR1_AWDIE_Pos)
    -
    1283#define ADC_CR1_AWDIE ADC_CR1_AWDIE_Msk
    -
    1284#define ADC_CR1_JEOCIE_Pos (7U)
    -
    1285#define ADC_CR1_JEOCIE_Msk (0x1UL << ADC_CR1_JEOCIE_Pos)
    -
    1286#define ADC_CR1_JEOCIE ADC_CR1_JEOCIE_Msk
    -
    1287#define ADC_CR1_SCAN_Pos (8U)
    -
    1288#define ADC_CR1_SCAN_Msk (0x1UL << ADC_CR1_SCAN_Pos)
    -
    1289#define ADC_CR1_SCAN ADC_CR1_SCAN_Msk
    -
    1290#define ADC_CR1_AWDSGL_Pos (9U)
    -
    1291#define ADC_CR1_AWDSGL_Msk (0x1UL << ADC_CR1_AWDSGL_Pos)
    -
    1292#define ADC_CR1_AWDSGL ADC_CR1_AWDSGL_Msk
    -
    1293#define ADC_CR1_JAUTO_Pos (10U)
    -
    1294#define ADC_CR1_JAUTO_Msk (0x1UL << ADC_CR1_JAUTO_Pos)
    -
    1295#define ADC_CR1_JAUTO ADC_CR1_JAUTO_Msk
    -
    1296#define ADC_CR1_DISCEN_Pos (11U)
    -
    1297#define ADC_CR1_DISCEN_Msk (0x1UL << ADC_CR1_DISCEN_Pos)
    -
    1298#define ADC_CR1_DISCEN ADC_CR1_DISCEN_Msk
    -
    1299#define ADC_CR1_JDISCEN_Pos (12U)
    -
    1300#define ADC_CR1_JDISCEN_Msk (0x1UL << ADC_CR1_JDISCEN_Pos)
    -
    1301#define ADC_CR1_JDISCEN ADC_CR1_JDISCEN_Msk
    -
    1302#define ADC_CR1_DISCNUM_Pos (13U)
    -
    1303#define ADC_CR1_DISCNUM_Msk (0x7UL << ADC_CR1_DISCNUM_Pos)
    -
    1304#define ADC_CR1_DISCNUM ADC_CR1_DISCNUM_Msk
    -
    1305#define ADC_CR1_DISCNUM_0 (0x1UL << ADC_CR1_DISCNUM_Pos)
    -
    1306#define ADC_CR1_DISCNUM_1 (0x2UL << ADC_CR1_DISCNUM_Pos)
    -
    1307#define ADC_CR1_DISCNUM_2 (0x4UL << ADC_CR1_DISCNUM_Pos)
    -
    1308#define ADC_CR1_JAWDEN_Pos (22U)
    -
    1309#define ADC_CR1_JAWDEN_Msk (0x1UL << ADC_CR1_JAWDEN_Pos)
    -
    1310#define ADC_CR1_JAWDEN ADC_CR1_JAWDEN_Msk
    -
    1311#define ADC_CR1_AWDEN_Pos (23U)
    -
    1312#define ADC_CR1_AWDEN_Msk (0x1UL << ADC_CR1_AWDEN_Pos)
    -
    1313#define ADC_CR1_AWDEN ADC_CR1_AWDEN_Msk
    -
    1314#define ADC_CR1_RES_Pos (24U)
    -
    1315#define ADC_CR1_RES_Msk (0x3UL << ADC_CR1_RES_Pos)
    -
    1316#define ADC_CR1_RES ADC_CR1_RES_Msk
    -
    1317#define ADC_CR1_RES_0 (0x1UL << ADC_CR1_RES_Pos)
    -
    1318#define ADC_CR1_RES_1 (0x2UL << ADC_CR1_RES_Pos)
    -
    1319#define ADC_CR1_OVRIE_Pos (26U)
    -
    1320#define ADC_CR1_OVRIE_Msk (0x1UL << ADC_CR1_OVRIE_Pos)
    -
    1321#define ADC_CR1_OVRIE ADC_CR1_OVRIE_Msk
    -
    1323/******************* Bit definition for ADC_CR2 register ********************/
    -
    1324#define ADC_CR2_ADON_Pos (0U)
    -
    1325#define ADC_CR2_ADON_Msk (0x1UL << ADC_CR2_ADON_Pos)
    -
    1326#define ADC_CR2_ADON ADC_CR2_ADON_Msk
    -
    1327#define ADC_CR2_CONT_Pos (1U)
    -
    1328#define ADC_CR2_CONT_Msk (0x1UL << ADC_CR2_CONT_Pos)
    -
    1329#define ADC_CR2_CONT ADC_CR2_CONT_Msk
    -
    1330#define ADC_CR2_DMA_Pos (8U)
    -
    1331#define ADC_CR2_DMA_Msk (0x1UL << ADC_CR2_DMA_Pos)
    -
    1332#define ADC_CR2_DMA ADC_CR2_DMA_Msk
    -
    1333#define ADC_CR2_DDS_Pos (9U)
    -
    1334#define ADC_CR2_DDS_Msk (0x1UL << ADC_CR2_DDS_Pos)
    -
    1335#define ADC_CR2_DDS ADC_CR2_DDS_Msk
    -
    1336#define ADC_CR2_EOCS_Pos (10U)
    -
    1337#define ADC_CR2_EOCS_Msk (0x1UL << ADC_CR2_EOCS_Pos)
    -
    1338#define ADC_CR2_EOCS ADC_CR2_EOCS_Msk
    -
    1339#define ADC_CR2_ALIGN_Pos (11U)
    -
    1340#define ADC_CR2_ALIGN_Msk (0x1UL << ADC_CR2_ALIGN_Pos)
    -
    1341#define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk
    -
    1342#define ADC_CR2_JEXTSEL_Pos (16U)
    -
    1343#define ADC_CR2_JEXTSEL_Msk (0xFUL << ADC_CR2_JEXTSEL_Pos)
    -
    1344#define ADC_CR2_JEXTSEL ADC_CR2_JEXTSEL_Msk
    -
    1345#define ADC_CR2_JEXTSEL_0 (0x1UL << ADC_CR2_JEXTSEL_Pos)
    -
    1346#define ADC_CR2_JEXTSEL_1 (0x2UL << ADC_CR2_JEXTSEL_Pos)
    -
    1347#define ADC_CR2_JEXTSEL_2 (0x4UL << ADC_CR2_JEXTSEL_Pos)
    -
    1348#define ADC_CR2_JEXTSEL_3 (0x8UL << ADC_CR2_JEXTSEL_Pos)
    -
    1349#define ADC_CR2_JEXTEN_Pos (20U)
    -
    1350#define ADC_CR2_JEXTEN_Msk (0x3UL << ADC_CR2_JEXTEN_Pos)
    -
    1351#define ADC_CR2_JEXTEN ADC_CR2_JEXTEN_Msk
    -
    1352#define ADC_CR2_JEXTEN_0 (0x1UL << ADC_CR2_JEXTEN_Pos)
    -
    1353#define ADC_CR2_JEXTEN_1 (0x2UL << ADC_CR2_JEXTEN_Pos)
    -
    1354#define ADC_CR2_JSWSTART_Pos (22U)
    -
    1355#define ADC_CR2_JSWSTART_Msk (0x1UL << ADC_CR2_JSWSTART_Pos)
    -
    1356#define ADC_CR2_JSWSTART ADC_CR2_JSWSTART_Msk
    -
    1357#define ADC_CR2_EXTSEL_Pos (24U)
    -
    1358#define ADC_CR2_EXTSEL_Msk (0xFUL << ADC_CR2_EXTSEL_Pos)
    -
    1359#define ADC_CR2_EXTSEL ADC_CR2_EXTSEL_Msk
    -
    1360#define ADC_CR2_EXTSEL_0 (0x1UL << ADC_CR2_EXTSEL_Pos)
    -
    1361#define ADC_CR2_EXTSEL_1 (0x2UL << ADC_CR2_EXTSEL_Pos)
    -
    1362#define ADC_CR2_EXTSEL_2 (0x4UL << ADC_CR2_EXTSEL_Pos)
    -
    1363#define ADC_CR2_EXTSEL_3 (0x8UL << ADC_CR2_EXTSEL_Pos)
    -
    1364#define ADC_CR2_EXTEN_Pos (28U)
    -
    1365#define ADC_CR2_EXTEN_Msk (0x3UL << ADC_CR2_EXTEN_Pos)
    -
    1366#define ADC_CR2_EXTEN ADC_CR2_EXTEN_Msk
    -
    1367#define ADC_CR2_EXTEN_0 (0x1UL << ADC_CR2_EXTEN_Pos)
    -
    1368#define ADC_CR2_EXTEN_1 (0x2UL << ADC_CR2_EXTEN_Pos)
    -
    1369#define ADC_CR2_SWSTART_Pos (30U)
    -
    1370#define ADC_CR2_SWSTART_Msk (0x1UL << ADC_CR2_SWSTART_Pos)
    -
    1371#define ADC_CR2_SWSTART ADC_CR2_SWSTART_Msk
    -
    1373/****************** Bit definition for ADC_SMPR1 register *******************/
    -
    1374#define ADC_SMPR1_SMP10_Pos (0U)
    -
    1375#define ADC_SMPR1_SMP10_Msk (0x7UL << ADC_SMPR1_SMP10_Pos)
    -
    1376#define ADC_SMPR1_SMP10 ADC_SMPR1_SMP10_Msk
    -
    1377#define ADC_SMPR1_SMP10_0 (0x1UL << ADC_SMPR1_SMP10_Pos)
    -
    1378#define ADC_SMPR1_SMP10_1 (0x2UL << ADC_SMPR1_SMP10_Pos)
    -
    1379#define ADC_SMPR1_SMP10_2 (0x4UL << ADC_SMPR1_SMP10_Pos)
    -
    1380#define ADC_SMPR1_SMP11_Pos (3U)
    -
    1381#define ADC_SMPR1_SMP11_Msk (0x7UL << ADC_SMPR1_SMP11_Pos)
    -
    1382#define ADC_SMPR1_SMP11 ADC_SMPR1_SMP11_Msk
    -
    1383#define ADC_SMPR1_SMP11_0 (0x1UL << ADC_SMPR1_SMP11_Pos)
    -
    1384#define ADC_SMPR1_SMP11_1 (0x2UL << ADC_SMPR1_SMP11_Pos)
    -
    1385#define ADC_SMPR1_SMP11_2 (0x4UL << ADC_SMPR1_SMP11_Pos)
    -
    1386#define ADC_SMPR1_SMP12_Pos (6U)
    -
    1387#define ADC_SMPR1_SMP12_Msk (0x7UL << ADC_SMPR1_SMP12_Pos)
    -
    1388#define ADC_SMPR1_SMP12 ADC_SMPR1_SMP12_Msk
    -
    1389#define ADC_SMPR1_SMP12_0 (0x1UL << ADC_SMPR1_SMP12_Pos)
    -
    1390#define ADC_SMPR1_SMP12_1 (0x2UL << ADC_SMPR1_SMP12_Pos)
    -
    1391#define ADC_SMPR1_SMP12_2 (0x4UL << ADC_SMPR1_SMP12_Pos)
    -
    1392#define ADC_SMPR1_SMP13_Pos (9U)
    -
    1393#define ADC_SMPR1_SMP13_Msk (0x7UL << ADC_SMPR1_SMP13_Pos)
    -
    1394#define ADC_SMPR1_SMP13 ADC_SMPR1_SMP13_Msk
    -
    1395#define ADC_SMPR1_SMP13_0 (0x1UL << ADC_SMPR1_SMP13_Pos)
    -
    1396#define ADC_SMPR1_SMP13_1 (0x2UL << ADC_SMPR1_SMP13_Pos)
    -
    1397#define ADC_SMPR1_SMP13_2 (0x4UL << ADC_SMPR1_SMP13_Pos)
    -
    1398#define ADC_SMPR1_SMP14_Pos (12U)
    -
    1399#define ADC_SMPR1_SMP14_Msk (0x7UL << ADC_SMPR1_SMP14_Pos)
    -
    1400#define ADC_SMPR1_SMP14 ADC_SMPR1_SMP14_Msk
    -
    1401#define ADC_SMPR1_SMP14_0 (0x1UL << ADC_SMPR1_SMP14_Pos)
    -
    1402#define ADC_SMPR1_SMP14_1 (0x2UL << ADC_SMPR1_SMP14_Pos)
    -
    1403#define ADC_SMPR1_SMP14_2 (0x4UL << ADC_SMPR1_SMP14_Pos)
    -
    1404#define ADC_SMPR1_SMP15_Pos (15U)
    -
    1405#define ADC_SMPR1_SMP15_Msk (0x7UL << ADC_SMPR1_SMP15_Pos)
    -
    1406#define ADC_SMPR1_SMP15 ADC_SMPR1_SMP15_Msk
    -
    1407#define ADC_SMPR1_SMP15_0 (0x1UL << ADC_SMPR1_SMP15_Pos)
    -
    1408#define ADC_SMPR1_SMP15_1 (0x2UL << ADC_SMPR1_SMP15_Pos)
    -
    1409#define ADC_SMPR1_SMP15_2 (0x4UL << ADC_SMPR1_SMP15_Pos)
    -
    1410#define ADC_SMPR1_SMP16_Pos (18U)
    -
    1411#define ADC_SMPR1_SMP16_Msk (0x7UL << ADC_SMPR1_SMP16_Pos)
    -
    1412#define ADC_SMPR1_SMP16 ADC_SMPR1_SMP16_Msk
    -
    1413#define ADC_SMPR1_SMP16_0 (0x1UL << ADC_SMPR1_SMP16_Pos)
    -
    1414#define ADC_SMPR1_SMP16_1 (0x2UL << ADC_SMPR1_SMP16_Pos)
    -
    1415#define ADC_SMPR1_SMP16_2 (0x4UL << ADC_SMPR1_SMP16_Pos)
    -
    1416#define ADC_SMPR1_SMP17_Pos (21U)
    -
    1417#define ADC_SMPR1_SMP17_Msk (0x7UL << ADC_SMPR1_SMP17_Pos)
    -
    1418#define ADC_SMPR1_SMP17 ADC_SMPR1_SMP17_Msk
    -
    1419#define ADC_SMPR1_SMP17_0 (0x1UL << ADC_SMPR1_SMP17_Pos)
    -
    1420#define ADC_SMPR1_SMP17_1 (0x2UL << ADC_SMPR1_SMP17_Pos)
    -
    1421#define ADC_SMPR1_SMP17_2 (0x4UL << ADC_SMPR1_SMP17_Pos)
    -
    1422#define ADC_SMPR1_SMP18_Pos (24U)
    -
    1423#define ADC_SMPR1_SMP18_Msk (0x7UL << ADC_SMPR1_SMP18_Pos)
    -
    1424#define ADC_SMPR1_SMP18 ADC_SMPR1_SMP18_Msk
    -
    1425#define ADC_SMPR1_SMP18_0 (0x1UL << ADC_SMPR1_SMP18_Pos)
    -
    1426#define ADC_SMPR1_SMP18_1 (0x2UL << ADC_SMPR1_SMP18_Pos)
    -
    1427#define ADC_SMPR1_SMP18_2 (0x4UL << ADC_SMPR1_SMP18_Pos)
    -
    1429/****************** Bit definition for ADC_SMPR2 register *******************/
    -
    1430#define ADC_SMPR2_SMP0_Pos (0U)
    -
    1431#define ADC_SMPR2_SMP0_Msk (0x7UL << ADC_SMPR2_SMP0_Pos)
    -
    1432#define ADC_SMPR2_SMP0 ADC_SMPR2_SMP0_Msk
    -
    1433#define ADC_SMPR2_SMP0_0 (0x1UL << ADC_SMPR2_SMP0_Pos)
    -
    1434#define ADC_SMPR2_SMP0_1 (0x2UL << ADC_SMPR2_SMP0_Pos)
    -
    1435#define ADC_SMPR2_SMP0_2 (0x4UL << ADC_SMPR2_SMP0_Pos)
    -
    1436#define ADC_SMPR2_SMP1_Pos (3U)
    -
    1437#define ADC_SMPR2_SMP1_Msk (0x7UL << ADC_SMPR2_SMP1_Pos)
    -
    1438#define ADC_SMPR2_SMP1 ADC_SMPR2_SMP1_Msk
    -
    1439#define ADC_SMPR2_SMP1_0 (0x1UL << ADC_SMPR2_SMP1_Pos)
    -
    1440#define ADC_SMPR2_SMP1_1 (0x2UL << ADC_SMPR2_SMP1_Pos)
    -
    1441#define ADC_SMPR2_SMP1_2 (0x4UL << ADC_SMPR2_SMP1_Pos)
    -
    1442#define ADC_SMPR2_SMP2_Pos (6U)
    -
    1443#define ADC_SMPR2_SMP2_Msk (0x7UL << ADC_SMPR2_SMP2_Pos)
    -
    1444#define ADC_SMPR2_SMP2 ADC_SMPR2_SMP2_Msk
    -
    1445#define ADC_SMPR2_SMP2_0 (0x1UL << ADC_SMPR2_SMP2_Pos)
    -
    1446#define ADC_SMPR2_SMP2_1 (0x2UL << ADC_SMPR2_SMP2_Pos)
    -
    1447#define ADC_SMPR2_SMP2_2 (0x4UL << ADC_SMPR2_SMP2_Pos)
    -
    1448#define ADC_SMPR2_SMP3_Pos (9U)
    -
    1449#define ADC_SMPR2_SMP3_Msk (0x7UL << ADC_SMPR2_SMP3_Pos)
    -
    1450#define ADC_SMPR2_SMP3 ADC_SMPR2_SMP3_Msk
    -
    1451#define ADC_SMPR2_SMP3_0 (0x1UL << ADC_SMPR2_SMP3_Pos)
    -
    1452#define ADC_SMPR2_SMP3_1 (0x2UL << ADC_SMPR2_SMP3_Pos)
    -
    1453#define ADC_SMPR2_SMP3_2 (0x4UL << ADC_SMPR2_SMP3_Pos)
    -
    1454#define ADC_SMPR2_SMP4_Pos (12U)
    -
    1455#define ADC_SMPR2_SMP4_Msk (0x7UL << ADC_SMPR2_SMP4_Pos)
    -
    1456#define ADC_SMPR2_SMP4 ADC_SMPR2_SMP4_Msk
    -
    1457#define ADC_SMPR2_SMP4_0 (0x1UL << ADC_SMPR2_SMP4_Pos)
    -
    1458#define ADC_SMPR2_SMP4_1 (0x2UL << ADC_SMPR2_SMP4_Pos)
    -
    1459#define ADC_SMPR2_SMP4_2 (0x4UL << ADC_SMPR2_SMP4_Pos)
    -
    1460#define ADC_SMPR2_SMP5_Pos (15U)
    -
    1461#define ADC_SMPR2_SMP5_Msk (0x7UL << ADC_SMPR2_SMP5_Pos)
    -
    1462#define ADC_SMPR2_SMP5 ADC_SMPR2_SMP5_Msk
    -
    1463#define ADC_SMPR2_SMP5_0 (0x1UL << ADC_SMPR2_SMP5_Pos)
    -
    1464#define ADC_SMPR2_SMP5_1 (0x2UL << ADC_SMPR2_SMP5_Pos)
    -
    1465#define ADC_SMPR2_SMP5_2 (0x4UL << ADC_SMPR2_SMP5_Pos)
    -
    1466#define ADC_SMPR2_SMP6_Pos (18U)
    -
    1467#define ADC_SMPR2_SMP6_Msk (0x7UL << ADC_SMPR2_SMP6_Pos)
    -
    1468#define ADC_SMPR2_SMP6 ADC_SMPR2_SMP6_Msk
    -
    1469#define ADC_SMPR2_SMP6_0 (0x1UL << ADC_SMPR2_SMP6_Pos)
    -
    1470#define ADC_SMPR2_SMP6_1 (0x2UL << ADC_SMPR2_SMP6_Pos)
    -
    1471#define ADC_SMPR2_SMP6_2 (0x4UL << ADC_SMPR2_SMP6_Pos)
    -
    1472#define ADC_SMPR2_SMP7_Pos (21U)
    -
    1473#define ADC_SMPR2_SMP7_Msk (0x7UL << ADC_SMPR2_SMP7_Pos)
    -
    1474#define ADC_SMPR2_SMP7 ADC_SMPR2_SMP7_Msk
    -
    1475#define ADC_SMPR2_SMP7_0 (0x1UL << ADC_SMPR2_SMP7_Pos)
    -
    1476#define ADC_SMPR2_SMP7_1 (0x2UL << ADC_SMPR2_SMP7_Pos)
    -
    1477#define ADC_SMPR2_SMP7_2 (0x4UL << ADC_SMPR2_SMP7_Pos)
    -
    1478#define ADC_SMPR2_SMP8_Pos (24U)
    -
    1479#define ADC_SMPR2_SMP8_Msk (0x7UL << ADC_SMPR2_SMP8_Pos)
    -
    1480#define ADC_SMPR2_SMP8 ADC_SMPR2_SMP8_Msk
    -
    1481#define ADC_SMPR2_SMP8_0 (0x1UL << ADC_SMPR2_SMP8_Pos)
    -
    1482#define ADC_SMPR2_SMP8_1 (0x2UL << ADC_SMPR2_SMP8_Pos)
    -
    1483#define ADC_SMPR2_SMP8_2 (0x4UL << ADC_SMPR2_SMP8_Pos)
    -
    1484#define ADC_SMPR2_SMP9_Pos (27U)
    -
    1485#define ADC_SMPR2_SMP9_Msk (0x7UL << ADC_SMPR2_SMP9_Pos)
    -
    1486#define ADC_SMPR2_SMP9 ADC_SMPR2_SMP9_Msk
    -
    1487#define ADC_SMPR2_SMP9_0 (0x1UL << ADC_SMPR2_SMP9_Pos)
    -
    1488#define ADC_SMPR2_SMP9_1 (0x2UL << ADC_SMPR2_SMP9_Pos)
    -
    1489#define ADC_SMPR2_SMP9_2 (0x4UL << ADC_SMPR2_SMP9_Pos)
    -
    1491/****************** Bit definition for ADC_JOFR1 register *******************/
    -
    1492#define ADC_JOFR1_JOFFSET1_Pos (0U)
    -
    1493#define ADC_JOFR1_JOFFSET1_Msk (0xFFFUL << ADC_JOFR1_JOFFSET1_Pos)
    -
    1494#define ADC_JOFR1_JOFFSET1 ADC_JOFR1_JOFFSET1_Msk
    -
    1496/****************** Bit definition for ADC_JOFR2 register *******************/
    -
    1497#define ADC_JOFR2_JOFFSET2_Pos (0U)
    -
    1498#define ADC_JOFR2_JOFFSET2_Msk (0xFFFUL << ADC_JOFR2_JOFFSET2_Pos)
    -
    1499#define ADC_JOFR2_JOFFSET2 ADC_JOFR2_JOFFSET2_Msk
    -
    1501/****************** Bit definition for ADC_JOFR3 register *******************/
    -
    1502#define ADC_JOFR3_JOFFSET3_Pos (0U)
    -
    1503#define ADC_JOFR3_JOFFSET3_Msk (0xFFFUL << ADC_JOFR3_JOFFSET3_Pos)
    -
    1504#define ADC_JOFR3_JOFFSET3 ADC_JOFR3_JOFFSET3_Msk
    -
    1506/****************** Bit definition for ADC_JOFR4 register *******************/
    -
    1507#define ADC_JOFR4_JOFFSET4_Pos (0U)
    -
    1508#define ADC_JOFR4_JOFFSET4_Msk (0xFFFUL << ADC_JOFR4_JOFFSET4_Pos)
    -
    1509#define ADC_JOFR4_JOFFSET4 ADC_JOFR4_JOFFSET4_Msk
    -
    1511/******************* Bit definition for ADC_HTR register ********************/
    -
    1512#define ADC_HTR_HT_Pos (0U)
    -
    1513#define ADC_HTR_HT_Msk (0xFFFUL << ADC_HTR_HT_Pos)
    -
    1514#define ADC_HTR_HT ADC_HTR_HT_Msk
    -
    1516/******************* Bit definition for ADC_LTR register ********************/
    -
    1517#define ADC_LTR_LT_Pos (0U)
    -
    1518#define ADC_LTR_LT_Msk (0xFFFUL << ADC_LTR_LT_Pos)
    -
    1519#define ADC_LTR_LT ADC_LTR_LT_Msk
    -
    1521/******************* Bit definition for ADC_SQR1 register *******************/
    -
    1522#define ADC_SQR1_SQ13_Pos (0U)
    -
    1523#define ADC_SQR1_SQ13_Msk (0x1FUL << ADC_SQR1_SQ13_Pos)
    -
    1524#define ADC_SQR1_SQ13 ADC_SQR1_SQ13_Msk
    -
    1525#define ADC_SQR1_SQ13_0 (0x01UL << ADC_SQR1_SQ13_Pos)
    -
    1526#define ADC_SQR1_SQ13_1 (0x02UL << ADC_SQR1_SQ13_Pos)
    -
    1527#define ADC_SQR1_SQ13_2 (0x04UL << ADC_SQR1_SQ13_Pos)
    -
    1528#define ADC_SQR1_SQ13_3 (0x08UL << ADC_SQR1_SQ13_Pos)
    -
    1529#define ADC_SQR1_SQ13_4 (0x10UL << ADC_SQR1_SQ13_Pos)
    -
    1530#define ADC_SQR1_SQ14_Pos (5U)
    -
    1531#define ADC_SQR1_SQ14_Msk (0x1FUL << ADC_SQR1_SQ14_Pos)
    -
    1532#define ADC_SQR1_SQ14 ADC_SQR1_SQ14_Msk
    -
    1533#define ADC_SQR1_SQ14_0 (0x01UL << ADC_SQR1_SQ14_Pos)
    -
    1534#define ADC_SQR1_SQ14_1 (0x02UL << ADC_SQR1_SQ14_Pos)
    -
    1535#define ADC_SQR1_SQ14_2 (0x04UL << ADC_SQR1_SQ14_Pos)
    -
    1536#define ADC_SQR1_SQ14_3 (0x08UL << ADC_SQR1_SQ14_Pos)
    -
    1537#define ADC_SQR1_SQ14_4 (0x10UL << ADC_SQR1_SQ14_Pos)
    -
    1538#define ADC_SQR1_SQ15_Pos (10U)
    -
    1539#define ADC_SQR1_SQ15_Msk (0x1FUL << ADC_SQR1_SQ15_Pos)
    -
    1540#define ADC_SQR1_SQ15 ADC_SQR1_SQ15_Msk
    -
    1541#define ADC_SQR1_SQ15_0 (0x01UL << ADC_SQR1_SQ15_Pos)
    -
    1542#define ADC_SQR1_SQ15_1 (0x02UL << ADC_SQR1_SQ15_Pos)
    -
    1543#define ADC_SQR1_SQ15_2 (0x04UL << ADC_SQR1_SQ15_Pos)
    -
    1544#define ADC_SQR1_SQ15_3 (0x08UL << ADC_SQR1_SQ15_Pos)
    -
    1545#define ADC_SQR1_SQ15_4 (0x10UL << ADC_SQR1_SQ15_Pos)
    -
    1546#define ADC_SQR1_SQ16_Pos (15U)
    -
    1547#define ADC_SQR1_SQ16_Msk (0x1FUL << ADC_SQR1_SQ16_Pos)
    -
    1548#define ADC_SQR1_SQ16 ADC_SQR1_SQ16_Msk
    -
    1549#define ADC_SQR1_SQ16_0 (0x01UL << ADC_SQR1_SQ16_Pos)
    -
    1550#define ADC_SQR1_SQ16_1 (0x02UL << ADC_SQR1_SQ16_Pos)
    -
    1551#define ADC_SQR1_SQ16_2 (0x04UL << ADC_SQR1_SQ16_Pos)
    -
    1552#define ADC_SQR1_SQ16_3 (0x08UL << ADC_SQR1_SQ16_Pos)
    -
    1553#define ADC_SQR1_SQ16_4 (0x10UL << ADC_SQR1_SQ16_Pos)
    -
    1554#define ADC_SQR1_L_Pos (20U)
    -
    1555#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos)
    -
    1556#define ADC_SQR1_L ADC_SQR1_L_Msk
    -
    1557#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos)
    -
    1558#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos)
    -
    1559#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos)
    -
    1560#define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos)
    -
    1562/******************* Bit definition for ADC_SQR2 register *******************/
    -
    1563#define ADC_SQR2_SQ7_Pos (0U)
    -
    1564#define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos)
    -
    1565#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk
    -
    1566#define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos)
    -
    1567#define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos)
    -
    1568#define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos)
    -
    1569#define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos)
    -
    1570#define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos)
    -
    1571#define ADC_SQR2_SQ8_Pos (5U)
    -
    1572#define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos)
    -
    1573#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk
    -
    1574#define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos)
    -
    1575#define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos)
    -
    1576#define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos)
    -
    1577#define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos)
    -
    1578#define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos)
    -
    1579#define ADC_SQR2_SQ9_Pos (10U)
    -
    1580#define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos)
    -
    1581#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk
    -
    1582#define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos)
    -
    1583#define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos)
    -
    1584#define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos)
    -
    1585#define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos)
    -
    1586#define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos)
    -
    1587#define ADC_SQR2_SQ10_Pos (15U)
    -
    1588#define ADC_SQR2_SQ10_Msk (0x1FUL << ADC_SQR2_SQ10_Pos)
    -
    1589#define ADC_SQR2_SQ10 ADC_SQR2_SQ10_Msk
    -
    1590#define ADC_SQR2_SQ10_0 (0x01UL << ADC_SQR2_SQ10_Pos)
    -
    1591#define ADC_SQR2_SQ10_1 (0x02UL << ADC_SQR2_SQ10_Pos)
    -
    1592#define ADC_SQR2_SQ10_2 (0x04UL << ADC_SQR2_SQ10_Pos)
    -
    1593#define ADC_SQR2_SQ10_3 (0x08UL << ADC_SQR2_SQ10_Pos)
    -
    1594#define ADC_SQR2_SQ10_4 (0x10UL << ADC_SQR2_SQ10_Pos)
    -
    1595#define ADC_SQR2_SQ11_Pos (20U)
    -
    1596#define ADC_SQR2_SQ11_Msk (0x1FUL << ADC_SQR2_SQ11_Pos)
    -
    1597#define ADC_SQR2_SQ11 ADC_SQR2_SQ11_Msk
    -
    1598#define ADC_SQR2_SQ11_0 (0x01UL << ADC_SQR2_SQ11_Pos)
    -
    1599#define ADC_SQR2_SQ11_1 (0x02UL << ADC_SQR2_SQ11_Pos)
    -
    1600#define ADC_SQR2_SQ11_2 (0x04UL << ADC_SQR2_SQ11_Pos)
    -
    1601#define ADC_SQR2_SQ11_3 (0x08UL << ADC_SQR2_SQ11_Pos)
    -
    1602#define ADC_SQR2_SQ11_4 (0x10UL << ADC_SQR2_SQ11_Pos)
    -
    1603#define ADC_SQR2_SQ12_Pos (25U)
    -
    1604#define ADC_SQR2_SQ12_Msk (0x1FUL << ADC_SQR2_SQ12_Pos)
    -
    1605#define ADC_SQR2_SQ12 ADC_SQR2_SQ12_Msk
    -
    1606#define ADC_SQR2_SQ12_0 (0x01UL << ADC_SQR2_SQ12_Pos)
    -
    1607#define ADC_SQR2_SQ12_1 (0x02UL << ADC_SQR2_SQ12_Pos)
    -
    1608#define ADC_SQR2_SQ12_2 (0x04UL << ADC_SQR2_SQ12_Pos)
    -
    1609#define ADC_SQR2_SQ12_3 (0x08UL << ADC_SQR2_SQ12_Pos)
    -
    1610#define ADC_SQR2_SQ12_4 (0x10UL << ADC_SQR2_SQ12_Pos)
    -
    1612/******************* Bit definition for ADC_SQR3 register *******************/
    -
    1613#define ADC_SQR3_SQ1_Pos (0U)
    -
    1614#define ADC_SQR3_SQ1_Msk (0x1FUL << ADC_SQR3_SQ1_Pos)
    -
    1615#define ADC_SQR3_SQ1 ADC_SQR3_SQ1_Msk
    -
    1616#define ADC_SQR3_SQ1_0 (0x01UL << ADC_SQR3_SQ1_Pos)
    -
    1617#define ADC_SQR3_SQ1_1 (0x02UL << ADC_SQR3_SQ1_Pos)
    -
    1618#define ADC_SQR3_SQ1_2 (0x04UL << ADC_SQR3_SQ1_Pos)
    -
    1619#define ADC_SQR3_SQ1_3 (0x08UL << ADC_SQR3_SQ1_Pos)
    -
    1620#define ADC_SQR3_SQ1_4 (0x10UL << ADC_SQR3_SQ1_Pos)
    -
    1621#define ADC_SQR3_SQ2_Pos (5U)
    -
    1622#define ADC_SQR3_SQ2_Msk (0x1FUL << ADC_SQR3_SQ2_Pos)
    -
    1623#define ADC_SQR3_SQ2 ADC_SQR3_SQ2_Msk
    -
    1624#define ADC_SQR3_SQ2_0 (0x01UL << ADC_SQR3_SQ2_Pos)
    -
    1625#define ADC_SQR3_SQ2_1 (0x02UL << ADC_SQR3_SQ2_Pos)
    -
    1626#define ADC_SQR3_SQ2_2 (0x04UL << ADC_SQR3_SQ2_Pos)
    -
    1627#define ADC_SQR3_SQ2_3 (0x08UL << ADC_SQR3_SQ2_Pos)
    -
    1628#define ADC_SQR3_SQ2_4 (0x10UL << ADC_SQR3_SQ2_Pos)
    -
    1629#define ADC_SQR3_SQ3_Pos (10U)
    -
    1630#define ADC_SQR3_SQ3_Msk (0x1FUL << ADC_SQR3_SQ3_Pos)
    -
    1631#define ADC_SQR3_SQ3 ADC_SQR3_SQ3_Msk
    -
    1632#define ADC_SQR3_SQ3_0 (0x01UL << ADC_SQR3_SQ3_Pos)
    -
    1633#define ADC_SQR3_SQ3_1 (0x02UL << ADC_SQR3_SQ3_Pos)
    -
    1634#define ADC_SQR3_SQ3_2 (0x04UL << ADC_SQR3_SQ3_Pos)
    -
    1635#define ADC_SQR3_SQ3_3 (0x08UL << ADC_SQR3_SQ3_Pos)
    -
    1636#define ADC_SQR3_SQ3_4 (0x10UL << ADC_SQR3_SQ3_Pos)
    -
    1637#define ADC_SQR3_SQ4_Pos (15U)
    -
    1638#define ADC_SQR3_SQ4_Msk (0x1FUL << ADC_SQR3_SQ4_Pos)
    -
    1639#define ADC_SQR3_SQ4 ADC_SQR3_SQ4_Msk
    -
    1640#define ADC_SQR3_SQ4_0 (0x01UL << ADC_SQR3_SQ4_Pos)
    -
    1641#define ADC_SQR3_SQ4_1 (0x02UL << ADC_SQR3_SQ4_Pos)
    -
    1642#define ADC_SQR3_SQ4_2 (0x04UL << ADC_SQR3_SQ4_Pos)
    -
    1643#define ADC_SQR3_SQ4_3 (0x08UL << ADC_SQR3_SQ4_Pos)
    -
    1644#define ADC_SQR3_SQ4_4 (0x10UL << ADC_SQR3_SQ4_Pos)
    -
    1645#define ADC_SQR3_SQ5_Pos (20U)
    -
    1646#define ADC_SQR3_SQ5_Msk (0x1FUL << ADC_SQR3_SQ5_Pos)
    -
    1647#define ADC_SQR3_SQ5 ADC_SQR3_SQ5_Msk
    -
    1648#define ADC_SQR3_SQ5_0 (0x01UL << ADC_SQR3_SQ5_Pos)
    -
    1649#define ADC_SQR3_SQ5_1 (0x02UL << ADC_SQR3_SQ5_Pos)
    -
    1650#define ADC_SQR3_SQ5_2 (0x04UL << ADC_SQR3_SQ5_Pos)
    -
    1651#define ADC_SQR3_SQ5_3 (0x08UL << ADC_SQR3_SQ5_Pos)
    -
    1652#define ADC_SQR3_SQ5_4 (0x10UL << ADC_SQR3_SQ5_Pos)
    -
    1653#define ADC_SQR3_SQ6_Pos (25U)
    -
    1654#define ADC_SQR3_SQ6_Msk (0x1FUL << ADC_SQR3_SQ6_Pos)
    -
    1655#define ADC_SQR3_SQ6 ADC_SQR3_SQ6_Msk
    -
    1656#define ADC_SQR3_SQ6_0 (0x01UL << ADC_SQR3_SQ6_Pos)
    -
    1657#define ADC_SQR3_SQ6_1 (0x02UL << ADC_SQR3_SQ6_Pos)
    -
    1658#define ADC_SQR3_SQ6_2 (0x04UL << ADC_SQR3_SQ6_Pos)
    -
    1659#define ADC_SQR3_SQ6_3 (0x08UL << ADC_SQR3_SQ6_Pos)
    -
    1660#define ADC_SQR3_SQ6_4 (0x10UL << ADC_SQR3_SQ6_Pos)
    -
    1662/******************* Bit definition for ADC_JSQR register *******************/
    -
    1663#define ADC_JSQR_JSQ1_Pos (0U)
    -
    1664#define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos)
    -
    1665#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk
    -
    1666#define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos)
    -
    1667#define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos)
    -
    1668#define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos)
    -
    1669#define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos)
    -
    1670#define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos)
    -
    1671#define ADC_JSQR_JSQ2_Pos (5U)
    -
    1672#define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos)
    -
    1673#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk
    -
    1674#define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos)
    -
    1675#define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos)
    -
    1676#define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos)
    -
    1677#define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos)
    -
    1678#define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos)
    -
    1679#define ADC_JSQR_JSQ3_Pos (10U)
    -
    1680#define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos)
    -
    1681#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk
    -
    1682#define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos)
    -
    1683#define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos)
    -
    1684#define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos)
    -
    1685#define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos)
    -
    1686#define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos)
    -
    1687#define ADC_JSQR_JSQ4_Pos (15U)
    -
    1688#define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos)
    -
    1689#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk
    -
    1690#define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos)
    -
    1691#define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos)
    -
    1692#define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos)
    -
    1693#define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos)
    -
    1694#define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos)
    -
    1695#define ADC_JSQR_JL_Pos (20U)
    -
    1696#define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos)
    -
    1697#define ADC_JSQR_JL ADC_JSQR_JL_Msk
    -
    1698#define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos)
    -
    1699#define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos)
    -
    1701/******************* Bit definition for ADC_JDR1 register *******************/
    -
    1702#define ADC_JDR1_JDATA_Pos (0U)
    -
    1703#define ADC_JDR1_JDATA_Msk (0xFFFFUL << ADC_JDR1_JDATA_Pos)
    -
    1704#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk
    -
    1706/******************* Bit definition for ADC_JDR2 register *******************/
    -
    1707#define ADC_JDR2_JDATA_Pos (0U)
    -
    1708#define ADC_JDR2_JDATA_Msk (0xFFFFUL << ADC_JDR2_JDATA_Pos)
    -
    1709#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk
    -
    1711/******************* Bit definition for ADC_JDR3 register *******************/
    -
    1712#define ADC_JDR3_JDATA_Pos (0U)
    -
    1713#define ADC_JDR3_JDATA_Msk (0xFFFFUL << ADC_JDR3_JDATA_Pos)
    -
    1714#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk
    -
    1716/******************* Bit definition for ADC_JDR4 register *******************/
    -
    1717#define ADC_JDR4_JDATA_Pos (0U)
    -
    1718#define ADC_JDR4_JDATA_Msk (0xFFFFUL << ADC_JDR4_JDATA_Pos)
    -
    1719#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk
    -
    1721/******************** Bit definition for ADC_DR register ********************/
    -
    1722#define ADC_DR_DATA_Pos (0U)
    -
    1723#define ADC_DR_DATA_Msk (0xFFFFUL << ADC_DR_DATA_Pos)
    -
    1724#define ADC_DR_DATA ADC_DR_DATA_Msk
    -
    1725#define ADC_DR_ADC2DATA_Pos (16U)
    -
    1726#define ADC_DR_ADC2DATA_Msk (0xFFFFUL << ADC_DR_ADC2DATA_Pos)
    -
    1727#define ADC_DR_ADC2DATA ADC_DR_ADC2DATA_Msk
    -
    1729/******************* Bit definition for ADC_CSR register ********************/
    -
    1730#define ADC_CSR_AWD1_Pos (0U)
    -
    1731#define ADC_CSR_AWD1_Msk (0x1UL << ADC_CSR_AWD1_Pos)
    -
    1732#define ADC_CSR_AWD1 ADC_CSR_AWD1_Msk
    -
    1733#define ADC_CSR_EOC1_Pos (1U)
    -
    1734#define ADC_CSR_EOC1_Msk (0x1UL << ADC_CSR_EOC1_Pos)
    -
    1735#define ADC_CSR_EOC1 ADC_CSR_EOC1_Msk
    -
    1736#define ADC_CSR_JEOC1_Pos (2U)
    -
    1737#define ADC_CSR_JEOC1_Msk (0x1UL << ADC_CSR_JEOC1_Pos)
    -
    1738#define ADC_CSR_JEOC1 ADC_CSR_JEOC1_Msk
    -
    1739#define ADC_CSR_JSTRT1_Pos (3U)
    -
    1740#define ADC_CSR_JSTRT1_Msk (0x1UL << ADC_CSR_JSTRT1_Pos)
    -
    1741#define ADC_CSR_JSTRT1 ADC_CSR_JSTRT1_Msk
    -
    1742#define ADC_CSR_STRT1_Pos (4U)
    -
    1743#define ADC_CSR_STRT1_Msk (0x1UL << ADC_CSR_STRT1_Pos)
    -
    1744#define ADC_CSR_STRT1 ADC_CSR_STRT1_Msk
    -
    1745#define ADC_CSR_OVR1_Pos (5U)
    -
    1746#define ADC_CSR_OVR1_Msk (0x1UL << ADC_CSR_OVR1_Pos)
    -
    1747#define ADC_CSR_OVR1 ADC_CSR_OVR1_Msk
    -
    1748#define ADC_CSR_AWD2_Pos (8U)
    -
    1749#define ADC_CSR_AWD2_Msk (0x1UL << ADC_CSR_AWD2_Pos)
    -
    1750#define ADC_CSR_AWD2 ADC_CSR_AWD2_Msk
    -
    1751#define ADC_CSR_EOC2_Pos (9U)
    -
    1752#define ADC_CSR_EOC2_Msk (0x1UL << ADC_CSR_EOC2_Pos)
    -
    1753#define ADC_CSR_EOC2 ADC_CSR_EOC2_Msk
    -
    1754#define ADC_CSR_JEOC2_Pos (10U)
    -
    1755#define ADC_CSR_JEOC2_Msk (0x1UL << ADC_CSR_JEOC2_Pos)
    -
    1756#define ADC_CSR_JEOC2 ADC_CSR_JEOC2_Msk
    -
    1757#define ADC_CSR_JSTRT2_Pos (11U)
    -
    1758#define ADC_CSR_JSTRT2_Msk (0x1UL << ADC_CSR_JSTRT2_Pos)
    -
    1759#define ADC_CSR_JSTRT2 ADC_CSR_JSTRT2_Msk
    -
    1760#define ADC_CSR_STRT2_Pos (12U)
    -
    1761#define ADC_CSR_STRT2_Msk (0x1UL << ADC_CSR_STRT2_Pos)
    -
    1762#define ADC_CSR_STRT2 ADC_CSR_STRT2_Msk
    -
    1763#define ADC_CSR_OVR2_Pos (13U)
    -
    1764#define ADC_CSR_OVR2_Msk (0x1UL << ADC_CSR_OVR2_Pos)
    -
    1765#define ADC_CSR_OVR2 ADC_CSR_OVR2_Msk
    -
    1766#define ADC_CSR_AWD3_Pos (16U)
    -
    1767#define ADC_CSR_AWD3_Msk (0x1UL << ADC_CSR_AWD3_Pos)
    -
    1768#define ADC_CSR_AWD3 ADC_CSR_AWD3_Msk
    -
    1769#define ADC_CSR_EOC3_Pos (17U)
    -
    1770#define ADC_CSR_EOC3_Msk (0x1UL << ADC_CSR_EOC3_Pos)
    -
    1771#define ADC_CSR_EOC3 ADC_CSR_EOC3_Msk
    -
    1772#define ADC_CSR_JEOC3_Pos (18U)
    -
    1773#define ADC_CSR_JEOC3_Msk (0x1UL << ADC_CSR_JEOC3_Pos)
    -
    1774#define ADC_CSR_JEOC3 ADC_CSR_JEOC3_Msk
    -
    1775#define ADC_CSR_JSTRT3_Pos (19U)
    -
    1776#define ADC_CSR_JSTRT3_Msk (0x1UL << ADC_CSR_JSTRT3_Pos)
    -
    1777#define ADC_CSR_JSTRT3 ADC_CSR_JSTRT3_Msk
    -
    1778#define ADC_CSR_STRT3_Pos (20U)
    -
    1779#define ADC_CSR_STRT3_Msk (0x1UL << ADC_CSR_STRT3_Pos)
    -
    1780#define ADC_CSR_STRT3 ADC_CSR_STRT3_Msk
    -
    1781#define ADC_CSR_OVR3_Pos (21U)
    -
    1782#define ADC_CSR_OVR3_Msk (0x1UL << ADC_CSR_OVR3_Pos)
    -
    1783#define ADC_CSR_OVR3 ADC_CSR_OVR3_Msk
    -
    1785/* Legacy defines */
    -
    1786#define ADC_CSR_DOVR1 ADC_CSR_OVR1
    -
    1787#define ADC_CSR_DOVR2 ADC_CSR_OVR2
    -
    1788#define ADC_CSR_DOVR3 ADC_CSR_OVR3
    -
    1789
    -
    1790/******************* Bit definition for ADC_CCR register ********************/
    -
    1791#define ADC_CCR_MULTI_Pos (0U)
    -
    1792#define ADC_CCR_MULTI_Msk (0x1FUL << ADC_CCR_MULTI_Pos)
    -
    1793#define ADC_CCR_MULTI ADC_CCR_MULTI_Msk
    -
    1794#define ADC_CCR_MULTI_0 (0x01UL << ADC_CCR_MULTI_Pos)
    -
    1795#define ADC_CCR_MULTI_1 (0x02UL << ADC_CCR_MULTI_Pos)
    -
    1796#define ADC_CCR_MULTI_2 (0x04UL << ADC_CCR_MULTI_Pos)
    -
    1797#define ADC_CCR_MULTI_3 (0x08UL << ADC_CCR_MULTI_Pos)
    -
    1798#define ADC_CCR_MULTI_4 (0x10UL << ADC_CCR_MULTI_Pos)
    -
    1799#define ADC_CCR_DELAY_Pos (8U)
    -
    1800#define ADC_CCR_DELAY_Msk (0xFUL << ADC_CCR_DELAY_Pos)
    -
    1801#define ADC_CCR_DELAY ADC_CCR_DELAY_Msk
    -
    1802#define ADC_CCR_DELAY_0 (0x1UL << ADC_CCR_DELAY_Pos)
    -
    1803#define ADC_CCR_DELAY_1 (0x2UL << ADC_CCR_DELAY_Pos)
    -
    1804#define ADC_CCR_DELAY_2 (0x4UL << ADC_CCR_DELAY_Pos)
    -
    1805#define ADC_CCR_DELAY_3 (0x8UL << ADC_CCR_DELAY_Pos)
    -
    1806#define ADC_CCR_DDS_Pos (13U)
    -
    1807#define ADC_CCR_DDS_Msk (0x1UL << ADC_CCR_DDS_Pos)
    -
    1808#define ADC_CCR_DDS ADC_CCR_DDS_Msk
    -
    1809#define ADC_CCR_DMA_Pos (14U)
    -
    1810#define ADC_CCR_DMA_Msk (0x3UL << ADC_CCR_DMA_Pos)
    -
    1811#define ADC_CCR_DMA ADC_CCR_DMA_Msk
    -
    1812#define ADC_CCR_DMA_0 (0x1UL << ADC_CCR_DMA_Pos)
    -
    1813#define ADC_CCR_DMA_1 (0x2UL << ADC_CCR_DMA_Pos)
    -
    1814#define ADC_CCR_ADCPRE_Pos (16U)
    -
    1815#define ADC_CCR_ADCPRE_Msk (0x3UL << ADC_CCR_ADCPRE_Pos)
    -
    1816#define ADC_CCR_ADCPRE ADC_CCR_ADCPRE_Msk
    -
    1817#define ADC_CCR_ADCPRE_0 (0x1UL << ADC_CCR_ADCPRE_Pos)
    -
    1818#define ADC_CCR_ADCPRE_1 (0x2UL << ADC_CCR_ADCPRE_Pos)
    -
    1819#define ADC_CCR_VBATE_Pos (22U)
    -
    1820#define ADC_CCR_VBATE_Msk (0x1UL << ADC_CCR_VBATE_Pos)
    -
    1821#define ADC_CCR_VBATE ADC_CCR_VBATE_Msk
    -
    1822#define ADC_CCR_TSVREFE_Pos (23U)
    -
    1823#define ADC_CCR_TSVREFE_Msk (0x1UL << ADC_CCR_TSVREFE_Pos)
    -
    1824#define ADC_CCR_TSVREFE ADC_CCR_TSVREFE_Msk
    -
    1826/******************* Bit definition for ADC_CDR register ********************/
    -
    1827#define ADC_CDR_DATA1_Pos (0U)
    -
    1828#define ADC_CDR_DATA1_Msk (0xFFFFUL << ADC_CDR_DATA1_Pos)
    -
    1829#define ADC_CDR_DATA1 ADC_CDR_DATA1_Msk
    -
    1830#define ADC_CDR_DATA2_Pos (16U)
    -
    1831#define ADC_CDR_DATA2_Msk (0xFFFFUL << ADC_CDR_DATA2_Pos)
    -
    1832#define ADC_CDR_DATA2 ADC_CDR_DATA2_Msk
    -
    1834/* Legacy defines */
    -
    1835#define ADC_CDR_RDATA_MST ADC_CDR_DATA1
    -
    1836#define ADC_CDR_RDATA_SLV ADC_CDR_DATA2
    -
    1837
    -
    1838/******************************************************************************/
    -
    1839/* */
    -
    1840/* Controller Area Network */
    -
    1841/* */
    -
    1842/******************************************************************************/
    -
    1844/******************* Bit definition for CAN_MCR register ********************/
    -
    1845#define CAN_MCR_INRQ_Pos (0U)
    -
    1846#define CAN_MCR_INRQ_Msk (0x1UL << CAN_MCR_INRQ_Pos)
    -
    1847#define CAN_MCR_INRQ CAN_MCR_INRQ_Msk
    -
    1848#define CAN_MCR_SLEEP_Pos (1U)
    -
    1849#define CAN_MCR_SLEEP_Msk (0x1UL << CAN_MCR_SLEEP_Pos)
    -
    1850#define CAN_MCR_SLEEP CAN_MCR_SLEEP_Msk
    -
    1851#define CAN_MCR_TXFP_Pos (2U)
    -
    1852#define CAN_MCR_TXFP_Msk (0x1UL << CAN_MCR_TXFP_Pos)
    -
    1853#define CAN_MCR_TXFP CAN_MCR_TXFP_Msk
    -
    1854#define CAN_MCR_RFLM_Pos (3U)
    -
    1855#define CAN_MCR_RFLM_Msk (0x1UL << CAN_MCR_RFLM_Pos)
    -
    1856#define CAN_MCR_RFLM CAN_MCR_RFLM_Msk
    -
    1857#define CAN_MCR_NART_Pos (4U)
    -
    1858#define CAN_MCR_NART_Msk (0x1UL << CAN_MCR_NART_Pos)
    -
    1859#define CAN_MCR_NART CAN_MCR_NART_Msk
    -
    1860#define CAN_MCR_AWUM_Pos (5U)
    -
    1861#define CAN_MCR_AWUM_Msk (0x1UL << CAN_MCR_AWUM_Pos)
    -
    1862#define CAN_MCR_AWUM CAN_MCR_AWUM_Msk
    -
    1863#define CAN_MCR_ABOM_Pos (6U)
    -
    1864#define CAN_MCR_ABOM_Msk (0x1UL << CAN_MCR_ABOM_Pos)
    -
    1865#define CAN_MCR_ABOM CAN_MCR_ABOM_Msk
    -
    1866#define CAN_MCR_TTCM_Pos (7U)
    -
    1867#define CAN_MCR_TTCM_Msk (0x1UL << CAN_MCR_TTCM_Pos)
    -
    1868#define CAN_MCR_TTCM CAN_MCR_TTCM_Msk
    -
    1869#define CAN_MCR_RESET_Pos (15U)
    -
    1870#define CAN_MCR_RESET_Msk (0x1UL << CAN_MCR_RESET_Pos)
    -
    1871#define CAN_MCR_RESET CAN_MCR_RESET_Msk
    -
    1872#define CAN_MCR_DBF_Pos (16U)
    -
    1873#define CAN_MCR_DBF_Msk (0x1UL << CAN_MCR_DBF_Pos)
    -
    1874#define CAN_MCR_DBF CAN_MCR_DBF_Msk
    -
    1875/******************* Bit definition for CAN_MSR register ********************/
    -
    1876#define CAN_MSR_INAK_Pos (0U)
    -
    1877#define CAN_MSR_INAK_Msk (0x1UL << CAN_MSR_INAK_Pos)
    -
    1878#define CAN_MSR_INAK CAN_MSR_INAK_Msk
    -
    1879#define CAN_MSR_SLAK_Pos (1U)
    -
    1880#define CAN_MSR_SLAK_Msk (0x1UL << CAN_MSR_SLAK_Pos)
    -
    1881#define CAN_MSR_SLAK CAN_MSR_SLAK_Msk
    -
    1882#define CAN_MSR_ERRI_Pos (2U)
    -
    1883#define CAN_MSR_ERRI_Msk (0x1UL << CAN_MSR_ERRI_Pos)
    -
    1884#define CAN_MSR_ERRI CAN_MSR_ERRI_Msk
    -
    1885#define CAN_MSR_WKUI_Pos (3U)
    -
    1886#define CAN_MSR_WKUI_Msk (0x1UL << CAN_MSR_WKUI_Pos)
    -
    1887#define CAN_MSR_WKUI CAN_MSR_WKUI_Msk
    -
    1888#define CAN_MSR_SLAKI_Pos (4U)
    -
    1889#define CAN_MSR_SLAKI_Msk (0x1UL << CAN_MSR_SLAKI_Pos)
    -
    1890#define CAN_MSR_SLAKI CAN_MSR_SLAKI_Msk
    -
    1891#define CAN_MSR_TXM_Pos (8U)
    -
    1892#define CAN_MSR_TXM_Msk (0x1UL << CAN_MSR_TXM_Pos)
    -
    1893#define CAN_MSR_TXM CAN_MSR_TXM_Msk
    -
    1894#define CAN_MSR_RXM_Pos (9U)
    -
    1895#define CAN_MSR_RXM_Msk (0x1UL << CAN_MSR_RXM_Pos)
    -
    1896#define CAN_MSR_RXM CAN_MSR_RXM_Msk
    -
    1897#define CAN_MSR_SAMP_Pos (10U)
    -
    1898#define CAN_MSR_SAMP_Msk (0x1UL << CAN_MSR_SAMP_Pos)
    -
    1899#define CAN_MSR_SAMP CAN_MSR_SAMP_Msk
    -
    1900#define CAN_MSR_RX_Pos (11U)
    -
    1901#define CAN_MSR_RX_Msk (0x1UL << CAN_MSR_RX_Pos)
    -
    1902#define CAN_MSR_RX CAN_MSR_RX_Msk
    -
    1904/******************* Bit definition for CAN_TSR register ********************/
    -
    1905#define CAN_TSR_RQCP0_Pos (0U)
    -
    1906#define CAN_TSR_RQCP0_Msk (0x1UL << CAN_TSR_RQCP0_Pos)
    -
    1907#define CAN_TSR_RQCP0 CAN_TSR_RQCP0_Msk
    -
    1908#define CAN_TSR_TXOK0_Pos (1U)
    -
    1909#define CAN_TSR_TXOK0_Msk (0x1UL << CAN_TSR_TXOK0_Pos)
    -
    1910#define CAN_TSR_TXOK0 CAN_TSR_TXOK0_Msk
    -
    1911#define CAN_TSR_ALST0_Pos (2U)
    -
    1912#define CAN_TSR_ALST0_Msk (0x1UL << CAN_TSR_ALST0_Pos)
    -
    1913#define CAN_TSR_ALST0 CAN_TSR_ALST0_Msk
    -
    1914#define CAN_TSR_TERR0_Pos (3U)
    -
    1915#define CAN_TSR_TERR0_Msk (0x1UL << CAN_TSR_TERR0_Pos)
    -
    1916#define CAN_TSR_TERR0 CAN_TSR_TERR0_Msk
    -
    1917#define CAN_TSR_ABRQ0_Pos (7U)
    -
    1918#define CAN_TSR_ABRQ0_Msk (0x1UL << CAN_TSR_ABRQ0_Pos)
    -
    1919#define CAN_TSR_ABRQ0 CAN_TSR_ABRQ0_Msk
    -
    1920#define CAN_TSR_RQCP1_Pos (8U)
    -
    1921#define CAN_TSR_RQCP1_Msk (0x1UL << CAN_TSR_RQCP1_Pos)
    -
    1922#define CAN_TSR_RQCP1 CAN_TSR_RQCP1_Msk
    -
    1923#define CAN_TSR_TXOK1_Pos (9U)
    -
    1924#define CAN_TSR_TXOK1_Msk (0x1UL << CAN_TSR_TXOK1_Pos)
    -
    1925#define CAN_TSR_TXOK1 CAN_TSR_TXOK1_Msk
    -
    1926#define CAN_TSR_ALST1_Pos (10U)
    -
    1927#define CAN_TSR_ALST1_Msk (0x1UL << CAN_TSR_ALST1_Pos)
    -
    1928#define CAN_TSR_ALST1 CAN_TSR_ALST1_Msk
    -
    1929#define CAN_TSR_TERR1_Pos (11U)
    -
    1930#define CAN_TSR_TERR1_Msk (0x1UL << CAN_TSR_TERR1_Pos)
    -
    1931#define CAN_TSR_TERR1 CAN_TSR_TERR1_Msk
    -
    1932#define CAN_TSR_ABRQ1_Pos (15U)
    -
    1933#define CAN_TSR_ABRQ1_Msk (0x1UL << CAN_TSR_ABRQ1_Pos)
    -
    1934#define CAN_TSR_ABRQ1 CAN_TSR_ABRQ1_Msk
    -
    1935#define CAN_TSR_RQCP2_Pos (16U)
    -
    1936#define CAN_TSR_RQCP2_Msk (0x1UL << CAN_TSR_RQCP2_Pos)
    -
    1937#define CAN_TSR_RQCP2 CAN_TSR_RQCP2_Msk
    -
    1938#define CAN_TSR_TXOK2_Pos (17U)
    -
    1939#define CAN_TSR_TXOK2_Msk (0x1UL << CAN_TSR_TXOK2_Pos)
    -
    1940#define CAN_TSR_TXOK2 CAN_TSR_TXOK2_Msk
    -
    1941#define CAN_TSR_ALST2_Pos (18U)
    -
    1942#define CAN_TSR_ALST2_Msk (0x1UL << CAN_TSR_ALST2_Pos)
    -
    1943#define CAN_TSR_ALST2 CAN_TSR_ALST2_Msk
    -
    1944#define CAN_TSR_TERR2_Pos (19U)
    -
    1945#define CAN_TSR_TERR2_Msk (0x1UL << CAN_TSR_TERR2_Pos)
    -
    1946#define CAN_TSR_TERR2 CAN_TSR_TERR2_Msk
    -
    1947#define CAN_TSR_ABRQ2_Pos (23U)
    -
    1948#define CAN_TSR_ABRQ2_Msk (0x1UL << CAN_TSR_ABRQ2_Pos)
    -
    1949#define CAN_TSR_ABRQ2 CAN_TSR_ABRQ2_Msk
    -
    1950#define CAN_TSR_CODE_Pos (24U)
    -
    1951#define CAN_TSR_CODE_Msk (0x3UL << CAN_TSR_CODE_Pos)
    -
    1952#define CAN_TSR_CODE CAN_TSR_CODE_Msk
    -
    1954#define CAN_TSR_TME_Pos (26U)
    -
    1955#define CAN_TSR_TME_Msk (0x7UL << CAN_TSR_TME_Pos)
    -
    1956#define CAN_TSR_TME CAN_TSR_TME_Msk
    -
    1957#define CAN_TSR_TME0_Pos (26U)
    -
    1958#define CAN_TSR_TME0_Msk (0x1UL << CAN_TSR_TME0_Pos)
    -
    1959#define CAN_TSR_TME0 CAN_TSR_TME0_Msk
    -
    1960#define CAN_TSR_TME1_Pos (27U)
    -
    1961#define CAN_TSR_TME1_Msk (0x1UL << CAN_TSR_TME1_Pos)
    -
    1962#define CAN_TSR_TME1 CAN_TSR_TME1_Msk
    -
    1963#define CAN_TSR_TME2_Pos (28U)
    -
    1964#define CAN_TSR_TME2_Msk (0x1UL << CAN_TSR_TME2_Pos)
    -
    1965#define CAN_TSR_TME2 CAN_TSR_TME2_Msk
    -
    1967#define CAN_TSR_LOW_Pos (29U)
    -
    1968#define CAN_TSR_LOW_Msk (0x7UL << CAN_TSR_LOW_Pos)
    -
    1969#define CAN_TSR_LOW CAN_TSR_LOW_Msk
    -
    1970#define CAN_TSR_LOW0_Pos (29U)
    -
    1971#define CAN_TSR_LOW0_Msk (0x1UL << CAN_TSR_LOW0_Pos)
    -
    1972#define CAN_TSR_LOW0 CAN_TSR_LOW0_Msk
    -
    1973#define CAN_TSR_LOW1_Pos (30U)
    -
    1974#define CAN_TSR_LOW1_Msk (0x1UL << CAN_TSR_LOW1_Pos)
    -
    1975#define CAN_TSR_LOW1 CAN_TSR_LOW1_Msk
    -
    1976#define CAN_TSR_LOW2_Pos (31U)
    -
    1977#define CAN_TSR_LOW2_Msk (0x1UL << CAN_TSR_LOW2_Pos)
    -
    1978#define CAN_TSR_LOW2 CAN_TSR_LOW2_Msk
    -
    1980/******************* Bit definition for CAN_RF0R register *******************/
    -
    1981#define CAN_RF0R_FMP0_Pos (0U)
    -
    1982#define CAN_RF0R_FMP0_Msk (0x3UL << CAN_RF0R_FMP0_Pos)
    -
    1983#define CAN_RF0R_FMP0 CAN_RF0R_FMP0_Msk
    -
    1984#define CAN_RF0R_FULL0_Pos (3U)
    -
    1985#define CAN_RF0R_FULL0_Msk (0x1UL << CAN_RF0R_FULL0_Pos)
    -
    1986#define CAN_RF0R_FULL0 CAN_RF0R_FULL0_Msk
    -
    1987#define CAN_RF0R_FOVR0_Pos (4U)
    -
    1988#define CAN_RF0R_FOVR0_Msk (0x1UL << CAN_RF0R_FOVR0_Pos)
    -
    1989#define CAN_RF0R_FOVR0 CAN_RF0R_FOVR0_Msk
    -
    1990#define CAN_RF0R_RFOM0_Pos (5U)
    -
    1991#define CAN_RF0R_RFOM0_Msk (0x1UL << CAN_RF0R_RFOM0_Pos)
    -
    1992#define CAN_RF0R_RFOM0 CAN_RF0R_RFOM0_Msk
    -
    1994/******************* Bit definition for CAN_RF1R register *******************/
    -
    1995#define CAN_RF1R_FMP1_Pos (0U)
    -
    1996#define CAN_RF1R_FMP1_Msk (0x3UL << CAN_RF1R_FMP1_Pos)
    -
    1997#define CAN_RF1R_FMP1 CAN_RF1R_FMP1_Msk
    -
    1998#define CAN_RF1R_FULL1_Pos (3U)
    -
    1999#define CAN_RF1R_FULL1_Msk (0x1UL << CAN_RF1R_FULL1_Pos)
    -
    2000#define CAN_RF1R_FULL1 CAN_RF1R_FULL1_Msk
    -
    2001#define CAN_RF1R_FOVR1_Pos (4U)
    -
    2002#define CAN_RF1R_FOVR1_Msk (0x1UL << CAN_RF1R_FOVR1_Pos)
    -
    2003#define CAN_RF1R_FOVR1 CAN_RF1R_FOVR1_Msk
    -
    2004#define CAN_RF1R_RFOM1_Pos (5U)
    -
    2005#define CAN_RF1R_RFOM1_Msk (0x1UL << CAN_RF1R_RFOM1_Pos)
    -
    2006#define CAN_RF1R_RFOM1 CAN_RF1R_RFOM1_Msk
    -
    2008/******************** Bit definition for CAN_IER register *******************/
    -
    2009#define CAN_IER_TMEIE_Pos (0U)
    -
    2010#define CAN_IER_TMEIE_Msk (0x1UL << CAN_IER_TMEIE_Pos)
    -
    2011#define CAN_IER_TMEIE CAN_IER_TMEIE_Msk
    -
    2012#define CAN_IER_FMPIE0_Pos (1U)
    -
    2013#define CAN_IER_FMPIE0_Msk (0x1UL << CAN_IER_FMPIE0_Pos)
    -
    2014#define CAN_IER_FMPIE0 CAN_IER_FMPIE0_Msk
    -
    2015#define CAN_IER_FFIE0_Pos (2U)
    -
    2016#define CAN_IER_FFIE0_Msk (0x1UL << CAN_IER_FFIE0_Pos)
    -
    2017#define CAN_IER_FFIE0 CAN_IER_FFIE0_Msk
    -
    2018#define CAN_IER_FOVIE0_Pos (3U)
    -
    2019#define CAN_IER_FOVIE0_Msk (0x1UL << CAN_IER_FOVIE0_Pos)
    -
    2020#define CAN_IER_FOVIE0 CAN_IER_FOVIE0_Msk
    -
    2021#define CAN_IER_FMPIE1_Pos (4U)
    -
    2022#define CAN_IER_FMPIE1_Msk (0x1UL << CAN_IER_FMPIE1_Pos)
    -
    2023#define CAN_IER_FMPIE1 CAN_IER_FMPIE1_Msk
    -
    2024#define CAN_IER_FFIE1_Pos (5U)
    -
    2025#define CAN_IER_FFIE1_Msk (0x1UL << CAN_IER_FFIE1_Pos)
    -
    2026#define CAN_IER_FFIE1 CAN_IER_FFIE1_Msk
    -
    2027#define CAN_IER_FOVIE1_Pos (6U)
    -
    2028#define CAN_IER_FOVIE1_Msk (0x1UL << CAN_IER_FOVIE1_Pos)
    -
    2029#define CAN_IER_FOVIE1 CAN_IER_FOVIE1_Msk
    -
    2030#define CAN_IER_EWGIE_Pos (8U)
    -
    2031#define CAN_IER_EWGIE_Msk (0x1UL << CAN_IER_EWGIE_Pos)
    -
    2032#define CAN_IER_EWGIE CAN_IER_EWGIE_Msk
    -
    2033#define CAN_IER_EPVIE_Pos (9U)
    -
    2034#define CAN_IER_EPVIE_Msk (0x1UL << CAN_IER_EPVIE_Pos)
    -
    2035#define CAN_IER_EPVIE CAN_IER_EPVIE_Msk
    -
    2036#define CAN_IER_BOFIE_Pos (10U)
    -
    2037#define CAN_IER_BOFIE_Msk (0x1UL << CAN_IER_BOFIE_Pos)
    -
    2038#define CAN_IER_BOFIE CAN_IER_BOFIE_Msk
    -
    2039#define CAN_IER_LECIE_Pos (11U)
    -
    2040#define CAN_IER_LECIE_Msk (0x1UL << CAN_IER_LECIE_Pos)
    -
    2041#define CAN_IER_LECIE CAN_IER_LECIE_Msk
    -
    2042#define CAN_IER_ERRIE_Pos (15U)
    -
    2043#define CAN_IER_ERRIE_Msk (0x1UL << CAN_IER_ERRIE_Pos)
    -
    2044#define CAN_IER_ERRIE CAN_IER_ERRIE_Msk
    -
    2045#define CAN_IER_WKUIE_Pos (16U)
    -
    2046#define CAN_IER_WKUIE_Msk (0x1UL << CAN_IER_WKUIE_Pos)
    -
    2047#define CAN_IER_WKUIE CAN_IER_WKUIE_Msk
    -
    2048#define CAN_IER_SLKIE_Pos (17U)
    -
    2049#define CAN_IER_SLKIE_Msk (0x1UL << CAN_IER_SLKIE_Pos)
    -
    2050#define CAN_IER_SLKIE CAN_IER_SLKIE_Msk
    -
    2051#define CAN_IER_EWGIE_Pos (8U)
    -
    2052
    -
    2053/******************** Bit definition for CAN_ESR register *******************/
    -
    2054#define CAN_ESR_EWGF_Pos (0U)
    -
    2055#define CAN_ESR_EWGF_Msk (0x1UL << CAN_ESR_EWGF_Pos)
    -
    2056#define CAN_ESR_EWGF CAN_ESR_EWGF_Msk
    -
    2057#define CAN_ESR_EPVF_Pos (1U)
    -
    2058#define CAN_ESR_EPVF_Msk (0x1UL << CAN_ESR_EPVF_Pos)
    -
    2059#define CAN_ESR_EPVF CAN_ESR_EPVF_Msk
    -
    2060#define CAN_ESR_BOFF_Pos (2U)
    -
    2061#define CAN_ESR_BOFF_Msk (0x1UL << CAN_ESR_BOFF_Pos)
    -
    2062#define CAN_ESR_BOFF CAN_ESR_BOFF_Msk
    -
    2064#define CAN_ESR_LEC_Pos (4U)
    -
    2065#define CAN_ESR_LEC_Msk (0x7UL << CAN_ESR_LEC_Pos)
    -
    2066#define CAN_ESR_LEC CAN_ESR_LEC_Msk
    -
    2067#define CAN_ESR_LEC_0 (0x1UL << CAN_ESR_LEC_Pos)
    -
    2068#define CAN_ESR_LEC_1 (0x2UL << CAN_ESR_LEC_Pos)
    -
    2069#define CAN_ESR_LEC_2 (0x4UL << CAN_ESR_LEC_Pos)
    -
    2071#define CAN_ESR_TEC_Pos (16U)
    -
    2072#define CAN_ESR_TEC_Msk (0xFFUL << CAN_ESR_TEC_Pos)
    -
    2073#define CAN_ESR_TEC CAN_ESR_TEC_Msk
    -
    2074#define CAN_ESR_REC_Pos (24U)
    -
    2075#define CAN_ESR_REC_Msk (0xFFUL << CAN_ESR_REC_Pos)
    -
    2076#define CAN_ESR_REC CAN_ESR_REC_Msk
    -
    2078/******************* Bit definition for CAN_BTR register ********************/
    -
    2079#define CAN_BTR_BRP_Pos (0U)
    -
    2080#define CAN_BTR_BRP_Msk (0x3FFUL << CAN_BTR_BRP_Pos)
    -
    2081#define CAN_BTR_BRP CAN_BTR_BRP_Msk
    -
    2082#define CAN_BTR_TS1_Pos (16U)
    -
    2083#define CAN_BTR_TS1_Msk (0xFUL << CAN_BTR_TS1_Pos)
    -
    2084#define CAN_BTR_TS1 CAN_BTR_TS1_Msk
    -
    2085#define CAN_BTR_TS1_0 (0x1UL << CAN_BTR_TS1_Pos)
    -
    2086#define CAN_BTR_TS1_1 (0x2UL << CAN_BTR_TS1_Pos)
    -
    2087#define CAN_BTR_TS1_2 (0x4UL << CAN_BTR_TS1_Pos)
    -
    2088#define CAN_BTR_TS1_3 (0x8UL << CAN_BTR_TS1_Pos)
    -
    2089#define CAN_BTR_TS2_Pos (20U)
    -
    2090#define CAN_BTR_TS2_Msk (0x7UL << CAN_BTR_TS2_Pos)
    -
    2091#define CAN_BTR_TS2 CAN_BTR_TS2_Msk
    -
    2092#define CAN_BTR_TS2_0 (0x1UL << CAN_BTR_TS2_Pos)
    -
    2093#define CAN_BTR_TS2_1 (0x2UL << CAN_BTR_TS2_Pos)
    -
    2094#define CAN_BTR_TS2_2 (0x4UL << CAN_BTR_TS2_Pos)
    -
    2095#define CAN_BTR_SJW_Pos (24U)
    -
    2096#define CAN_BTR_SJW_Msk (0x3UL << CAN_BTR_SJW_Pos)
    -
    2097#define CAN_BTR_SJW CAN_BTR_SJW_Msk
    -
    2098#define CAN_BTR_SJW_0 (0x1UL << CAN_BTR_SJW_Pos)
    -
    2099#define CAN_BTR_SJW_1 (0x2UL << CAN_BTR_SJW_Pos)
    -
    2100#define CAN_BTR_LBKM_Pos (30U)
    -
    2101#define CAN_BTR_LBKM_Msk (0x1UL << CAN_BTR_LBKM_Pos)
    -
    2102#define CAN_BTR_LBKM CAN_BTR_LBKM_Msk
    -
    2103#define CAN_BTR_SILM_Pos (31U)
    -
    2104#define CAN_BTR_SILM_Msk (0x1UL << CAN_BTR_SILM_Pos)
    -
    2105#define CAN_BTR_SILM CAN_BTR_SILM_Msk
    -
    2109/****************** Bit definition for CAN_TI0R register ********************/
    -
    2110#define CAN_TI0R_TXRQ_Pos (0U)
    -
    2111#define CAN_TI0R_TXRQ_Msk (0x1UL << CAN_TI0R_TXRQ_Pos)
    -
    2112#define CAN_TI0R_TXRQ CAN_TI0R_TXRQ_Msk
    -
    2113#define CAN_TI0R_RTR_Pos (1U)
    -
    2114#define CAN_TI0R_RTR_Msk (0x1UL << CAN_TI0R_RTR_Pos)
    -
    2115#define CAN_TI0R_RTR CAN_TI0R_RTR_Msk
    -
    2116#define CAN_TI0R_IDE_Pos (2U)
    -
    2117#define CAN_TI0R_IDE_Msk (0x1UL << CAN_TI0R_IDE_Pos)
    -
    2118#define CAN_TI0R_IDE CAN_TI0R_IDE_Msk
    -
    2119#define CAN_TI0R_EXID_Pos (3U)
    -
    2120#define CAN_TI0R_EXID_Msk (0x3FFFFUL << CAN_TI0R_EXID_Pos)
    -
    2121#define CAN_TI0R_EXID CAN_TI0R_EXID_Msk
    -
    2122#define CAN_TI0R_STID_Pos (21U)
    -
    2123#define CAN_TI0R_STID_Msk (0x7FFUL << CAN_TI0R_STID_Pos)
    -
    2124#define CAN_TI0R_STID CAN_TI0R_STID_Msk
    -
    2126/****************** Bit definition for CAN_TDT0R register *******************/
    -
    2127#define CAN_TDT0R_DLC_Pos (0U)
    -
    2128#define CAN_TDT0R_DLC_Msk (0xFUL << CAN_TDT0R_DLC_Pos)
    -
    2129#define CAN_TDT0R_DLC CAN_TDT0R_DLC_Msk
    -
    2130#define CAN_TDT0R_TGT_Pos (8U)
    -
    2131#define CAN_TDT0R_TGT_Msk (0x1UL << CAN_TDT0R_TGT_Pos)
    -
    2132#define CAN_TDT0R_TGT CAN_TDT0R_TGT_Msk
    -
    2133#define CAN_TDT0R_TIME_Pos (16U)
    -
    2134#define CAN_TDT0R_TIME_Msk (0xFFFFUL << CAN_TDT0R_TIME_Pos)
    -
    2135#define CAN_TDT0R_TIME CAN_TDT0R_TIME_Msk
    -
    2137/****************** Bit definition for CAN_TDL0R register *******************/
    -
    2138#define CAN_TDL0R_DATA0_Pos (0U)
    -
    2139#define CAN_TDL0R_DATA0_Msk (0xFFUL << CAN_TDL0R_DATA0_Pos)
    -
    2140#define CAN_TDL0R_DATA0 CAN_TDL0R_DATA0_Msk
    -
    2141#define CAN_TDL0R_DATA1_Pos (8U)
    -
    2142#define CAN_TDL0R_DATA1_Msk (0xFFUL << CAN_TDL0R_DATA1_Pos)
    -
    2143#define CAN_TDL0R_DATA1 CAN_TDL0R_DATA1_Msk
    -
    2144#define CAN_TDL0R_DATA2_Pos (16U)
    -
    2145#define CAN_TDL0R_DATA2_Msk (0xFFUL << CAN_TDL0R_DATA2_Pos)
    -
    2146#define CAN_TDL0R_DATA2 CAN_TDL0R_DATA2_Msk
    -
    2147#define CAN_TDL0R_DATA3_Pos (24U)
    -
    2148#define CAN_TDL0R_DATA3_Msk (0xFFUL << CAN_TDL0R_DATA3_Pos)
    -
    2149#define CAN_TDL0R_DATA3 CAN_TDL0R_DATA3_Msk
    -
    2151/****************** Bit definition for CAN_TDH0R register *******************/
    -
    2152#define CAN_TDH0R_DATA4_Pos (0U)
    -
    2153#define CAN_TDH0R_DATA4_Msk (0xFFUL << CAN_TDH0R_DATA4_Pos)
    -
    2154#define CAN_TDH0R_DATA4 CAN_TDH0R_DATA4_Msk
    -
    2155#define CAN_TDH0R_DATA5_Pos (8U)
    -
    2156#define CAN_TDH0R_DATA5_Msk (0xFFUL << CAN_TDH0R_DATA5_Pos)
    -
    2157#define CAN_TDH0R_DATA5 CAN_TDH0R_DATA5_Msk
    -
    2158#define CAN_TDH0R_DATA6_Pos (16U)
    -
    2159#define CAN_TDH0R_DATA6_Msk (0xFFUL << CAN_TDH0R_DATA6_Pos)
    -
    2160#define CAN_TDH0R_DATA6 CAN_TDH0R_DATA6_Msk
    -
    2161#define CAN_TDH0R_DATA7_Pos (24U)
    -
    2162#define CAN_TDH0R_DATA7_Msk (0xFFUL << CAN_TDH0R_DATA7_Pos)
    -
    2163#define CAN_TDH0R_DATA7 CAN_TDH0R_DATA7_Msk
    -
    2165/******************* Bit definition for CAN_TI1R register *******************/
    -
    2166#define CAN_TI1R_TXRQ_Pos (0U)
    -
    2167#define CAN_TI1R_TXRQ_Msk (0x1UL << CAN_TI1R_TXRQ_Pos)
    -
    2168#define CAN_TI1R_TXRQ CAN_TI1R_TXRQ_Msk
    -
    2169#define CAN_TI1R_RTR_Pos (1U)
    -
    2170#define CAN_TI1R_RTR_Msk (0x1UL << CAN_TI1R_RTR_Pos)
    -
    2171#define CAN_TI1R_RTR CAN_TI1R_RTR_Msk
    -
    2172#define CAN_TI1R_IDE_Pos (2U)
    -
    2173#define CAN_TI1R_IDE_Msk (0x1UL << CAN_TI1R_IDE_Pos)
    -
    2174#define CAN_TI1R_IDE CAN_TI1R_IDE_Msk
    -
    2175#define CAN_TI1R_EXID_Pos (3U)
    -
    2176#define CAN_TI1R_EXID_Msk (0x3FFFFUL << CAN_TI1R_EXID_Pos)
    -
    2177#define CAN_TI1R_EXID CAN_TI1R_EXID_Msk
    -
    2178#define CAN_TI1R_STID_Pos (21U)
    -
    2179#define CAN_TI1R_STID_Msk (0x7FFUL << CAN_TI1R_STID_Pos)
    -
    2180#define CAN_TI1R_STID CAN_TI1R_STID_Msk
    -
    2182/******************* Bit definition for CAN_TDT1R register ******************/
    -
    2183#define CAN_TDT1R_DLC_Pos (0U)
    -
    2184#define CAN_TDT1R_DLC_Msk (0xFUL << CAN_TDT1R_DLC_Pos)
    -
    2185#define CAN_TDT1R_DLC CAN_TDT1R_DLC_Msk
    -
    2186#define CAN_TDT1R_TGT_Pos (8U)
    -
    2187#define CAN_TDT1R_TGT_Msk (0x1UL << CAN_TDT1R_TGT_Pos)
    -
    2188#define CAN_TDT1R_TGT CAN_TDT1R_TGT_Msk
    -
    2189#define CAN_TDT1R_TIME_Pos (16U)
    -
    2190#define CAN_TDT1R_TIME_Msk (0xFFFFUL << CAN_TDT1R_TIME_Pos)
    -
    2191#define CAN_TDT1R_TIME CAN_TDT1R_TIME_Msk
    -
    2193/******************* Bit definition for CAN_TDL1R register ******************/
    -
    2194#define CAN_TDL1R_DATA0_Pos (0U)
    -
    2195#define CAN_TDL1R_DATA0_Msk (0xFFUL << CAN_TDL1R_DATA0_Pos)
    -
    2196#define CAN_TDL1R_DATA0 CAN_TDL1R_DATA0_Msk
    -
    2197#define CAN_TDL1R_DATA1_Pos (8U)
    -
    2198#define CAN_TDL1R_DATA1_Msk (0xFFUL << CAN_TDL1R_DATA1_Pos)
    -
    2199#define CAN_TDL1R_DATA1 CAN_TDL1R_DATA1_Msk
    -
    2200#define CAN_TDL1R_DATA2_Pos (16U)
    -
    2201#define CAN_TDL1R_DATA2_Msk (0xFFUL << CAN_TDL1R_DATA2_Pos)
    -
    2202#define CAN_TDL1R_DATA2 CAN_TDL1R_DATA2_Msk
    -
    2203#define CAN_TDL1R_DATA3_Pos (24U)
    -
    2204#define CAN_TDL1R_DATA3_Msk (0xFFUL << CAN_TDL1R_DATA3_Pos)
    -
    2205#define CAN_TDL1R_DATA3 CAN_TDL1R_DATA3_Msk
    -
    2207/******************* Bit definition for CAN_TDH1R register ******************/
    -
    2208#define CAN_TDH1R_DATA4_Pos (0U)
    -
    2209#define CAN_TDH1R_DATA4_Msk (0xFFUL << CAN_TDH1R_DATA4_Pos)
    -
    2210#define CAN_TDH1R_DATA4 CAN_TDH1R_DATA4_Msk
    -
    2211#define CAN_TDH1R_DATA5_Pos (8U)
    -
    2212#define CAN_TDH1R_DATA5_Msk (0xFFUL << CAN_TDH1R_DATA5_Pos)
    -
    2213#define CAN_TDH1R_DATA5 CAN_TDH1R_DATA5_Msk
    -
    2214#define CAN_TDH1R_DATA6_Pos (16U)
    -
    2215#define CAN_TDH1R_DATA6_Msk (0xFFUL << CAN_TDH1R_DATA6_Pos)
    -
    2216#define CAN_TDH1R_DATA6 CAN_TDH1R_DATA6_Msk
    -
    2217#define CAN_TDH1R_DATA7_Pos (24U)
    -
    2218#define CAN_TDH1R_DATA7_Msk (0xFFUL << CAN_TDH1R_DATA7_Pos)
    -
    2219#define CAN_TDH1R_DATA7 CAN_TDH1R_DATA7_Msk
    -
    2221/******************* Bit definition for CAN_TI2R register *******************/
    -
    2222#define CAN_TI2R_TXRQ_Pos (0U)
    -
    2223#define CAN_TI2R_TXRQ_Msk (0x1UL << CAN_TI2R_TXRQ_Pos)
    -
    2224#define CAN_TI2R_TXRQ CAN_TI2R_TXRQ_Msk
    -
    2225#define CAN_TI2R_RTR_Pos (1U)
    -
    2226#define CAN_TI2R_RTR_Msk (0x1UL << CAN_TI2R_RTR_Pos)
    -
    2227#define CAN_TI2R_RTR CAN_TI2R_RTR_Msk
    -
    2228#define CAN_TI2R_IDE_Pos (2U)
    -
    2229#define CAN_TI2R_IDE_Msk (0x1UL << CAN_TI2R_IDE_Pos)
    -
    2230#define CAN_TI2R_IDE CAN_TI2R_IDE_Msk
    -
    2231#define CAN_TI2R_EXID_Pos (3U)
    -
    2232#define CAN_TI2R_EXID_Msk (0x3FFFFUL << CAN_TI2R_EXID_Pos)
    -
    2233#define CAN_TI2R_EXID CAN_TI2R_EXID_Msk
    -
    2234#define CAN_TI2R_STID_Pos (21U)
    -
    2235#define CAN_TI2R_STID_Msk (0x7FFUL << CAN_TI2R_STID_Pos)
    -
    2236#define CAN_TI2R_STID CAN_TI2R_STID_Msk
    -
    2238/******************* Bit definition for CAN_TDT2R register ******************/
    -
    2239#define CAN_TDT2R_DLC_Pos (0U)
    -
    2240#define CAN_TDT2R_DLC_Msk (0xFUL << CAN_TDT2R_DLC_Pos)
    -
    2241#define CAN_TDT2R_DLC CAN_TDT2R_DLC_Msk
    -
    2242#define CAN_TDT2R_TGT_Pos (8U)
    -
    2243#define CAN_TDT2R_TGT_Msk (0x1UL << CAN_TDT2R_TGT_Pos)
    -
    2244#define CAN_TDT2R_TGT CAN_TDT2R_TGT_Msk
    -
    2245#define CAN_TDT2R_TIME_Pos (16U)
    -
    2246#define CAN_TDT2R_TIME_Msk (0xFFFFUL << CAN_TDT2R_TIME_Pos)
    -
    2247#define CAN_TDT2R_TIME CAN_TDT2R_TIME_Msk
    -
    2249/******************* Bit definition for CAN_TDL2R register ******************/
    -
    2250#define CAN_TDL2R_DATA0_Pos (0U)
    -
    2251#define CAN_TDL2R_DATA0_Msk (0xFFUL << CAN_TDL2R_DATA0_Pos)
    -
    2252#define CAN_TDL2R_DATA0 CAN_TDL2R_DATA0_Msk
    -
    2253#define CAN_TDL2R_DATA1_Pos (8U)
    -
    2254#define CAN_TDL2R_DATA1_Msk (0xFFUL << CAN_TDL2R_DATA1_Pos)
    -
    2255#define CAN_TDL2R_DATA1 CAN_TDL2R_DATA1_Msk
    -
    2256#define CAN_TDL2R_DATA2_Pos (16U)
    -
    2257#define CAN_TDL2R_DATA2_Msk (0xFFUL << CAN_TDL2R_DATA2_Pos)
    -
    2258#define CAN_TDL2R_DATA2 CAN_TDL2R_DATA2_Msk
    -
    2259#define CAN_TDL2R_DATA3_Pos (24U)
    -
    2260#define CAN_TDL2R_DATA3_Msk (0xFFUL << CAN_TDL2R_DATA3_Pos)
    -
    2261#define CAN_TDL2R_DATA3 CAN_TDL2R_DATA3_Msk
    -
    2263/******************* Bit definition for CAN_TDH2R register ******************/
    -
    2264#define CAN_TDH2R_DATA4_Pos (0U)
    -
    2265#define CAN_TDH2R_DATA4_Msk (0xFFUL << CAN_TDH2R_DATA4_Pos)
    -
    2266#define CAN_TDH2R_DATA4 CAN_TDH2R_DATA4_Msk
    -
    2267#define CAN_TDH2R_DATA5_Pos (8U)
    -
    2268#define CAN_TDH2R_DATA5_Msk (0xFFUL << CAN_TDH2R_DATA5_Pos)
    -
    2269#define CAN_TDH2R_DATA5 CAN_TDH2R_DATA5_Msk
    -
    2270#define CAN_TDH2R_DATA6_Pos (16U)
    -
    2271#define CAN_TDH2R_DATA6_Msk (0xFFUL << CAN_TDH2R_DATA6_Pos)
    -
    2272#define CAN_TDH2R_DATA6 CAN_TDH2R_DATA6_Msk
    -
    2273#define CAN_TDH2R_DATA7_Pos (24U)
    -
    2274#define CAN_TDH2R_DATA7_Msk (0xFFUL << CAN_TDH2R_DATA7_Pos)
    -
    2275#define CAN_TDH2R_DATA7 CAN_TDH2R_DATA7_Msk
    -
    2277/******************* Bit definition for CAN_RI0R register *******************/
    -
    2278#define CAN_RI0R_RTR_Pos (1U)
    -
    2279#define CAN_RI0R_RTR_Msk (0x1UL << CAN_RI0R_RTR_Pos)
    -
    2280#define CAN_RI0R_RTR CAN_RI0R_RTR_Msk
    -
    2281#define CAN_RI0R_IDE_Pos (2U)
    -
    2282#define CAN_RI0R_IDE_Msk (0x1UL << CAN_RI0R_IDE_Pos)
    -
    2283#define CAN_RI0R_IDE CAN_RI0R_IDE_Msk
    -
    2284#define CAN_RI0R_EXID_Pos (3U)
    -
    2285#define CAN_RI0R_EXID_Msk (0x3FFFFUL << CAN_RI0R_EXID_Pos)
    -
    2286#define CAN_RI0R_EXID CAN_RI0R_EXID_Msk
    -
    2287#define CAN_RI0R_STID_Pos (21U)
    -
    2288#define CAN_RI0R_STID_Msk (0x7FFUL << CAN_RI0R_STID_Pos)
    -
    2289#define CAN_RI0R_STID CAN_RI0R_STID_Msk
    -
    2291/******************* Bit definition for CAN_RDT0R register ******************/
    -
    2292#define CAN_RDT0R_DLC_Pos (0U)
    -
    2293#define CAN_RDT0R_DLC_Msk (0xFUL << CAN_RDT0R_DLC_Pos)
    -
    2294#define CAN_RDT0R_DLC CAN_RDT0R_DLC_Msk
    -
    2295#define CAN_RDT0R_FMI_Pos (8U)
    -
    2296#define CAN_RDT0R_FMI_Msk (0xFFUL << CAN_RDT0R_FMI_Pos)
    -
    2297#define CAN_RDT0R_FMI CAN_RDT0R_FMI_Msk
    -
    2298#define CAN_RDT0R_TIME_Pos (16U)
    -
    2299#define CAN_RDT0R_TIME_Msk (0xFFFFUL << CAN_RDT0R_TIME_Pos)
    -
    2300#define CAN_RDT0R_TIME CAN_RDT0R_TIME_Msk
    -
    2302/******************* Bit definition for CAN_RDL0R register ******************/
    -
    2303#define CAN_RDL0R_DATA0_Pos (0U)
    -
    2304#define CAN_RDL0R_DATA0_Msk (0xFFUL << CAN_RDL0R_DATA0_Pos)
    -
    2305#define CAN_RDL0R_DATA0 CAN_RDL0R_DATA0_Msk
    -
    2306#define CAN_RDL0R_DATA1_Pos (8U)
    -
    2307#define CAN_RDL0R_DATA1_Msk (0xFFUL << CAN_RDL0R_DATA1_Pos)
    -
    2308#define CAN_RDL0R_DATA1 CAN_RDL0R_DATA1_Msk
    -
    2309#define CAN_RDL0R_DATA2_Pos (16U)
    -
    2310#define CAN_RDL0R_DATA2_Msk (0xFFUL << CAN_RDL0R_DATA2_Pos)
    -
    2311#define CAN_RDL0R_DATA2 CAN_RDL0R_DATA2_Msk
    -
    2312#define CAN_RDL0R_DATA3_Pos (24U)
    -
    2313#define CAN_RDL0R_DATA3_Msk (0xFFUL << CAN_RDL0R_DATA3_Pos)
    -
    2314#define CAN_RDL0R_DATA3 CAN_RDL0R_DATA3_Msk
    -
    2316/******************* Bit definition for CAN_RDH0R register ******************/
    -
    2317#define CAN_RDH0R_DATA4_Pos (0U)
    -
    2318#define CAN_RDH0R_DATA4_Msk (0xFFUL << CAN_RDH0R_DATA4_Pos)
    -
    2319#define CAN_RDH0R_DATA4 CAN_RDH0R_DATA4_Msk
    -
    2320#define CAN_RDH0R_DATA5_Pos (8U)
    -
    2321#define CAN_RDH0R_DATA5_Msk (0xFFUL << CAN_RDH0R_DATA5_Pos)
    -
    2322#define CAN_RDH0R_DATA5 CAN_RDH0R_DATA5_Msk
    -
    2323#define CAN_RDH0R_DATA6_Pos (16U)
    -
    2324#define CAN_RDH0R_DATA6_Msk (0xFFUL << CAN_RDH0R_DATA6_Pos)
    -
    2325#define CAN_RDH0R_DATA6 CAN_RDH0R_DATA6_Msk
    -
    2326#define CAN_RDH0R_DATA7_Pos (24U)
    -
    2327#define CAN_RDH0R_DATA7_Msk (0xFFUL << CAN_RDH0R_DATA7_Pos)
    -
    2328#define CAN_RDH0R_DATA7 CAN_RDH0R_DATA7_Msk
    -
    2330/******************* Bit definition for CAN_RI1R register *******************/
    -
    2331#define CAN_RI1R_RTR_Pos (1U)
    -
    2332#define CAN_RI1R_RTR_Msk (0x1UL << CAN_RI1R_RTR_Pos)
    -
    2333#define CAN_RI1R_RTR CAN_RI1R_RTR_Msk
    -
    2334#define CAN_RI1R_IDE_Pos (2U)
    -
    2335#define CAN_RI1R_IDE_Msk (0x1UL << CAN_RI1R_IDE_Pos)
    -
    2336#define CAN_RI1R_IDE CAN_RI1R_IDE_Msk
    -
    2337#define CAN_RI1R_EXID_Pos (3U)
    -
    2338#define CAN_RI1R_EXID_Msk (0x3FFFFUL << CAN_RI1R_EXID_Pos)
    -
    2339#define CAN_RI1R_EXID CAN_RI1R_EXID_Msk
    -
    2340#define CAN_RI1R_STID_Pos (21U)
    -
    2341#define CAN_RI1R_STID_Msk (0x7FFUL << CAN_RI1R_STID_Pos)
    -
    2342#define CAN_RI1R_STID CAN_RI1R_STID_Msk
    -
    2344/******************* Bit definition for CAN_RDT1R register ******************/
    -
    2345#define CAN_RDT1R_DLC_Pos (0U)
    -
    2346#define CAN_RDT1R_DLC_Msk (0xFUL << CAN_RDT1R_DLC_Pos)
    -
    2347#define CAN_RDT1R_DLC CAN_RDT1R_DLC_Msk
    -
    2348#define CAN_RDT1R_FMI_Pos (8U)
    -
    2349#define CAN_RDT1R_FMI_Msk (0xFFUL << CAN_RDT1R_FMI_Pos)
    -
    2350#define CAN_RDT1R_FMI CAN_RDT1R_FMI_Msk
    -
    2351#define CAN_RDT1R_TIME_Pos (16U)
    -
    2352#define CAN_RDT1R_TIME_Msk (0xFFFFUL << CAN_RDT1R_TIME_Pos)
    -
    2353#define CAN_RDT1R_TIME CAN_RDT1R_TIME_Msk
    -
    2355/******************* Bit definition for CAN_RDL1R register ******************/
    -
    2356#define CAN_RDL1R_DATA0_Pos (0U)
    -
    2357#define CAN_RDL1R_DATA0_Msk (0xFFUL << CAN_RDL1R_DATA0_Pos)
    -
    2358#define CAN_RDL1R_DATA0 CAN_RDL1R_DATA0_Msk
    -
    2359#define CAN_RDL1R_DATA1_Pos (8U)
    -
    2360#define CAN_RDL1R_DATA1_Msk (0xFFUL << CAN_RDL1R_DATA1_Pos)
    -
    2361#define CAN_RDL1R_DATA1 CAN_RDL1R_DATA1_Msk
    -
    2362#define CAN_RDL1R_DATA2_Pos (16U)
    -
    2363#define CAN_RDL1R_DATA2_Msk (0xFFUL << CAN_RDL1R_DATA2_Pos)
    -
    2364#define CAN_RDL1R_DATA2 CAN_RDL1R_DATA2_Msk
    -
    2365#define CAN_RDL1R_DATA3_Pos (24U)
    -
    2366#define CAN_RDL1R_DATA3_Msk (0xFFUL << CAN_RDL1R_DATA3_Pos)
    -
    2367#define CAN_RDL1R_DATA3 CAN_RDL1R_DATA3_Msk
    -
    2369/******************* Bit definition for CAN_RDH1R register ******************/
    -
    2370#define CAN_RDH1R_DATA4_Pos (0U)
    -
    2371#define CAN_RDH1R_DATA4_Msk (0xFFUL << CAN_RDH1R_DATA4_Pos)
    -
    2372#define CAN_RDH1R_DATA4 CAN_RDH1R_DATA4_Msk
    -
    2373#define CAN_RDH1R_DATA5_Pos (8U)
    -
    2374#define CAN_RDH1R_DATA5_Msk (0xFFUL << CAN_RDH1R_DATA5_Pos)
    -
    2375#define CAN_RDH1R_DATA5 CAN_RDH1R_DATA5_Msk
    -
    2376#define CAN_RDH1R_DATA6_Pos (16U)
    -
    2377#define CAN_RDH1R_DATA6_Msk (0xFFUL << CAN_RDH1R_DATA6_Pos)
    -
    2378#define CAN_RDH1R_DATA6 CAN_RDH1R_DATA6_Msk
    -
    2379#define CAN_RDH1R_DATA7_Pos (24U)
    -
    2380#define CAN_RDH1R_DATA7_Msk (0xFFUL << CAN_RDH1R_DATA7_Pos)
    -
    2381#define CAN_RDH1R_DATA7 CAN_RDH1R_DATA7_Msk
    -
    2384/******************* Bit definition for CAN_FMR register ********************/
    -
    2385#define CAN_FMR_FINIT_Pos (0U)
    -
    2386#define CAN_FMR_FINIT_Msk (0x1UL << CAN_FMR_FINIT_Pos)
    -
    2387#define CAN_FMR_FINIT CAN_FMR_FINIT_Msk
    -
    2388#define CAN_FMR_CAN2SB_Pos (8U)
    -
    2389#define CAN_FMR_CAN2SB_Msk (0x3FUL << CAN_FMR_CAN2SB_Pos)
    -
    2390#define CAN_FMR_CAN2SB CAN_FMR_CAN2SB_Msk
    -
    2392/******************* Bit definition for CAN_FM1R register *******************/
    -
    2393#define CAN_FM1R_FBM_Pos (0U)
    -
    2394#define CAN_FM1R_FBM_Msk (0xFFFFFFFUL << CAN_FM1R_FBM_Pos)
    -
    2395#define CAN_FM1R_FBM CAN_FM1R_FBM_Msk
    -
    2396#define CAN_FM1R_FBM0_Pos (0U)
    -
    2397#define CAN_FM1R_FBM0_Msk (0x1UL << CAN_FM1R_FBM0_Pos)
    -
    2398#define CAN_FM1R_FBM0 CAN_FM1R_FBM0_Msk
    -
    2399#define CAN_FM1R_FBM1_Pos (1U)
    -
    2400#define CAN_FM1R_FBM1_Msk (0x1UL << CAN_FM1R_FBM1_Pos)
    -
    2401#define CAN_FM1R_FBM1 CAN_FM1R_FBM1_Msk
    -
    2402#define CAN_FM1R_FBM2_Pos (2U)
    -
    2403#define CAN_FM1R_FBM2_Msk (0x1UL << CAN_FM1R_FBM2_Pos)
    -
    2404#define CAN_FM1R_FBM2 CAN_FM1R_FBM2_Msk
    -
    2405#define CAN_FM1R_FBM3_Pos (3U)
    -
    2406#define CAN_FM1R_FBM3_Msk (0x1UL << CAN_FM1R_FBM3_Pos)
    -
    2407#define CAN_FM1R_FBM3 CAN_FM1R_FBM3_Msk
    -
    2408#define CAN_FM1R_FBM4_Pos (4U)
    -
    2409#define CAN_FM1R_FBM4_Msk (0x1UL << CAN_FM1R_FBM4_Pos)
    -
    2410#define CAN_FM1R_FBM4 CAN_FM1R_FBM4_Msk
    -
    2411#define CAN_FM1R_FBM5_Pos (5U)
    -
    2412#define CAN_FM1R_FBM5_Msk (0x1UL << CAN_FM1R_FBM5_Pos)
    -
    2413#define CAN_FM1R_FBM5 CAN_FM1R_FBM5_Msk
    -
    2414#define CAN_FM1R_FBM6_Pos (6U)
    -
    2415#define CAN_FM1R_FBM6_Msk (0x1UL << CAN_FM1R_FBM6_Pos)
    -
    2416#define CAN_FM1R_FBM6 CAN_FM1R_FBM6_Msk
    -
    2417#define CAN_FM1R_FBM7_Pos (7U)
    -
    2418#define CAN_FM1R_FBM7_Msk (0x1UL << CAN_FM1R_FBM7_Pos)
    -
    2419#define CAN_FM1R_FBM7 CAN_FM1R_FBM7_Msk
    -
    2420#define CAN_FM1R_FBM8_Pos (8U)
    -
    2421#define CAN_FM1R_FBM8_Msk (0x1UL << CAN_FM1R_FBM8_Pos)
    -
    2422#define CAN_FM1R_FBM8 CAN_FM1R_FBM8_Msk
    -
    2423#define CAN_FM1R_FBM9_Pos (9U)
    -
    2424#define CAN_FM1R_FBM9_Msk (0x1UL << CAN_FM1R_FBM9_Pos)
    -
    2425#define CAN_FM1R_FBM9 CAN_FM1R_FBM9_Msk
    -
    2426#define CAN_FM1R_FBM10_Pos (10U)
    -
    2427#define CAN_FM1R_FBM10_Msk (0x1UL << CAN_FM1R_FBM10_Pos)
    -
    2428#define CAN_FM1R_FBM10 CAN_FM1R_FBM10_Msk
    -
    2429#define CAN_FM1R_FBM11_Pos (11U)
    -
    2430#define CAN_FM1R_FBM11_Msk (0x1UL << CAN_FM1R_FBM11_Pos)
    -
    2431#define CAN_FM1R_FBM11 CAN_FM1R_FBM11_Msk
    -
    2432#define CAN_FM1R_FBM12_Pos (12U)
    -
    2433#define CAN_FM1R_FBM12_Msk (0x1UL << CAN_FM1R_FBM12_Pos)
    -
    2434#define CAN_FM1R_FBM12 CAN_FM1R_FBM12_Msk
    -
    2435#define CAN_FM1R_FBM13_Pos (13U)
    -
    2436#define CAN_FM1R_FBM13_Msk (0x1UL << CAN_FM1R_FBM13_Pos)
    -
    2437#define CAN_FM1R_FBM13 CAN_FM1R_FBM13_Msk
    -
    2438#define CAN_FM1R_FBM14_Pos (14U)
    -
    2439#define CAN_FM1R_FBM14_Msk (0x1UL << CAN_FM1R_FBM14_Pos)
    -
    2440#define CAN_FM1R_FBM14 CAN_FM1R_FBM14_Msk
    -
    2441#define CAN_FM1R_FBM15_Pos (15U)
    -
    2442#define CAN_FM1R_FBM15_Msk (0x1UL << CAN_FM1R_FBM15_Pos)
    -
    2443#define CAN_FM1R_FBM15 CAN_FM1R_FBM15_Msk
    -
    2444#define CAN_FM1R_FBM16_Pos (16U)
    -
    2445#define CAN_FM1R_FBM16_Msk (0x1UL << CAN_FM1R_FBM16_Pos)
    -
    2446#define CAN_FM1R_FBM16 CAN_FM1R_FBM16_Msk
    -
    2447#define CAN_FM1R_FBM17_Pos (17U)
    -
    2448#define CAN_FM1R_FBM17_Msk (0x1UL << CAN_FM1R_FBM17_Pos)
    -
    2449#define CAN_FM1R_FBM17 CAN_FM1R_FBM17_Msk
    -
    2450#define CAN_FM1R_FBM18_Pos (18U)
    -
    2451#define CAN_FM1R_FBM18_Msk (0x1UL << CAN_FM1R_FBM18_Pos)
    -
    2452#define CAN_FM1R_FBM18 CAN_FM1R_FBM18_Msk
    -
    2453#define CAN_FM1R_FBM19_Pos (19U)
    -
    2454#define CAN_FM1R_FBM19_Msk (0x1UL << CAN_FM1R_FBM19_Pos)
    -
    2455#define CAN_FM1R_FBM19 CAN_FM1R_FBM19_Msk
    -
    2456#define CAN_FM1R_FBM20_Pos (20U)
    -
    2457#define CAN_FM1R_FBM20_Msk (0x1UL << CAN_FM1R_FBM20_Pos)
    -
    2458#define CAN_FM1R_FBM20 CAN_FM1R_FBM20_Msk
    -
    2459#define CAN_FM1R_FBM21_Pos (21U)
    -
    2460#define CAN_FM1R_FBM21_Msk (0x1UL << CAN_FM1R_FBM21_Pos)
    -
    2461#define CAN_FM1R_FBM21 CAN_FM1R_FBM21_Msk
    -
    2462#define CAN_FM1R_FBM22_Pos (22U)
    -
    2463#define CAN_FM1R_FBM22_Msk (0x1UL << CAN_FM1R_FBM22_Pos)
    -
    2464#define CAN_FM1R_FBM22 CAN_FM1R_FBM22_Msk
    -
    2465#define CAN_FM1R_FBM23_Pos (23U)
    -
    2466#define CAN_FM1R_FBM23_Msk (0x1UL << CAN_FM1R_FBM23_Pos)
    -
    2467#define CAN_FM1R_FBM23 CAN_FM1R_FBM23_Msk
    -
    2468#define CAN_FM1R_FBM24_Pos (24U)
    -
    2469#define CAN_FM1R_FBM24_Msk (0x1UL << CAN_FM1R_FBM24_Pos)
    -
    2470#define CAN_FM1R_FBM24 CAN_FM1R_FBM24_Msk
    -
    2471#define CAN_FM1R_FBM25_Pos (25U)
    -
    2472#define CAN_FM1R_FBM25_Msk (0x1UL << CAN_FM1R_FBM25_Pos)
    -
    2473#define CAN_FM1R_FBM25 CAN_FM1R_FBM25_Msk
    -
    2474#define CAN_FM1R_FBM26_Pos (26U)
    -
    2475#define CAN_FM1R_FBM26_Msk (0x1UL << CAN_FM1R_FBM26_Pos)
    -
    2476#define CAN_FM1R_FBM26 CAN_FM1R_FBM26_Msk
    -
    2477#define CAN_FM1R_FBM27_Pos (27U)
    -
    2478#define CAN_FM1R_FBM27_Msk (0x1UL << CAN_FM1R_FBM27_Pos)
    -
    2479#define CAN_FM1R_FBM27 CAN_FM1R_FBM27_Msk
    -
    2481/******************* Bit definition for CAN_FS1R register *******************/
    -
    2482#define CAN_FS1R_FSC_Pos (0U)
    -
    2483#define CAN_FS1R_FSC_Msk (0xFFFFFFFUL << CAN_FS1R_FSC_Pos)
    -
    2484#define CAN_FS1R_FSC CAN_FS1R_FSC_Msk
    -
    2485#define CAN_FS1R_FSC0_Pos (0U)
    -
    2486#define CAN_FS1R_FSC0_Msk (0x1UL << CAN_FS1R_FSC0_Pos)
    -
    2487#define CAN_FS1R_FSC0 CAN_FS1R_FSC0_Msk
    -
    2488#define CAN_FS1R_FSC1_Pos (1U)
    -
    2489#define CAN_FS1R_FSC1_Msk (0x1UL << CAN_FS1R_FSC1_Pos)
    -
    2490#define CAN_FS1R_FSC1 CAN_FS1R_FSC1_Msk
    -
    2491#define CAN_FS1R_FSC2_Pos (2U)
    -
    2492#define CAN_FS1R_FSC2_Msk (0x1UL << CAN_FS1R_FSC2_Pos)
    -
    2493#define CAN_FS1R_FSC2 CAN_FS1R_FSC2_Msk
    -
    2494#define CAN_FS1R_FSC3_Pos (3U)
    -
    2495#define CAN_FS1R_FSC3_Msk (0x1UL << CAN_FS1R_FSC3_Pos)
    -
    2496#define CAN_FS1R_FSC3 CAN_FS1R_FSC3_Msk
    -
    2497#define CAN_FS1R_FSC4_Pos (4U)
    -
    2498#define CAN_FS1R_FSC4_Msk (0x1UL << CAN_FS1R_FSC4_Pos)
    -
    2499#define CAN_FS1R_FSC4 CAN_FS1R_FSC4_Msk
    -
    2500#define CAN_FS1R_FSC5_Pos (5U)
    -
    2501#define CAN_FS1R_FSC5_Msk (0x1UL << CAN_FS1R_FSC5_Pos)
    -
    2502#define CAN_FS1R_FSC5 CAN_FS1R_FSC5_Msk
    -
    2503#define CAN_FS1R_FSC6_Pos (6U)
    -
    2504#define CAN_FS1R_FSC6_Msk (0x1UL << CAN_FS1R_FSC6_Pos)
    -
    2505#define CAN_FS1R_FSC6 CAN_FS1R_FSC6_Msk
    -
    2506#define CAN_FS1R_FSC7_Pos (7U)
    -
    2507#define CAN_FS1R_FSC7_Msk (0x1UL << CAN_FS1R_FSC7_Pos)
    -
    2508#define CAN_FS1R_FSC7 CAN_FS1R_FSC7_Msk
    -
    2509#define CAN_FS1R_FSC8_Pos (8U)
    -
    2510#define CAN_FS1R_FSC8_Msk (0x1UL << CAN_FS1R_FSC8_Pos)
    -
    2511#define CAN_FS1R_FSC8 CAN_FS1R_FSC8_Msk
    -
    2512#define CAN_FS1R_FSC9_Pos (9U)
    -
    2513#define CAN_FS1R_FSC9_Msk (0x1UL << CAN_FS1R_FSC9_Pos)
    -
    2514#define CAN_FS1R_FSC9 CAN_FS1R_FSC9_Msk
    -
    2515#define CAN_FS1R_FSC10_Pos (10U)
    -
    2516#define CAN_FS1R_FSC10_Msk (0x1UL << CAN_FS1R_FSC10_Pos)
    -
    2517#define CAN_FS1R_FSC10 CAN_FS1R_FSC10_Msk
    -
    2518#define CAN_FS1R_FSC11_Pos (11U)
    -
    2519#define CAN_FS1R_FSC11_Msk (0x1UL << CAN_FS1R_FSC11_Pos)
    -
    2520#define CAN_FS1R_FSC11 CAN_FS1R_FSC11_Msk
    -
    2521#define CAN_FS1R_FSC12_Pos (12U)
    -
    2522#define CAN_FS1R_FSC12_Msk (0x1UL << CAN_FS1R_FSC12_Pos)
    -
    2523#define CAN_FS1R_FSC12 CAN_FS1R_FSC12_Msk
    -
    2524#define CAN_FS1R_FSC13_Pos (13U)
    -
    2525#define CAN_FS1R_FSC13_Msk (0x1UL << CAN_FS1R_FSC13_Pos)
    -
    2526#define CAN_FS1R_FSC13 CAN_FS1R_FSC13_Msk
    -
    2527#define CAN_FS1R_FSC14_Pos (14U)
    -
    2528#define CAN_FS1R_FSC14_Msk (0x1UL << CAN_FS1R_FSC14_Pos)
    -
    2529#define CAN_FS1R_FSC14 CAN_FS1R_FSC14_Msk
    -
    2530#define CAN_FS1R_FSC15_Pos (15U)
    -
    2531#define CAN_FS1R_FSC15_Msk (0x1UL << CAN_FS1R_FSC15_Pos)
    -
    2532#define CAN_FS1R_FSC15 CAN_FS1R_FSC15_Msk
    -
    2533#define CAN_FS1R_FSC16_Pos (16U)
    -
    2534#define CAN_FS1R_FSC16_Msk (0x1UL << CAN_FS1R_FSC16_Pos)
    -
    2535#define CAN_FS1R_FSC16 CAN_FS1R_FSC16_Msk
    -
    2536#define CAN_FS1R_FSC17_Pos (17U)
    -
    2537#define CAN_FS1R_FSC17_Msk (0x1UL << CAN_FS1R_FSC17_Pos)
    -
    2538#define CAN_FS1R_FSC17 CAN_FS1R_FSC17_Msk
    -
    2539#define CAN_FS1R_FSC18_Pos (18U)
    -
    2540#define CAN_FS1R_FSC18_Msk (0x1UL << CAN_FS1R_FSC18_Pos)
    -
    2541#define CAN_FS1R_FSC18 CAN_FS1R_FSC18_Msk
    -
    2542#define CAN_FS1R_FSC19_Pos (19U)
    -
    2543#define CAN_FS1R_FSC19_Msk (0x1UL << CAN_FS1R_FSC19_Pos)
    -
    2544#define CAN_FS1R_FSC19 CAN_FS1R_FSC19_Msk
    -
    2545#define CAN_FS1R_FSC20_Pos (20U)
    -
    2546#define CAN_FS1R_FSC20_Msk (0x1UL << CAN_FS1R_FSC20_Pos)
    -
    2547#define CAN_FS1R_FSC20 CAN_FS1R_FSC20_Msk
    -
    2548#define CAN_FS1R_FSC21_Pos (21U)
    -
    2549#define CAN_FS1R_FSC21_Msk (0x1UL << CAN_FS1R_FSC21_Pos)
    -
    2550#define CAN_FS1R_FSC21 CAN_FS1R_FSC21_Msk
    -
    2551#define CAN_FS1R_FSC22_Pos (22U)
    -
    2552#define CAN_FS1R_FSC22_Msk (0x1UL << CAN_FS1R_FSC22_Pos)
    -
    2553#define CAN_FS1R_FSC22 CAN_FS1R_FSC22_Msk
    -
    2554#define CAN_FS1R_FSC23_Pos (23U)
    -
    2555#define CAN_FS1R_FSC23_Msk (0x1UL << CAN_FS1R_FSC23_Pos)
    -
    2556#define CAN_FS1R_FSC23 CAN_FS1R_FSC23_Msk
    -
    2557#define CAN_FS1R_FSC24_Pos (24U)
    -
    2558#define CAN_FS1R_FSC24_Msk (0x1UL << CAN_FS1R_FSC24_Pos)
    -
    2559#define CAN_FS1R_FSC24 CAN_FS1R_FSC24_Msk
    -
    2560#define CAN_FS1R_FSC25_Pos (25U)
    -
    2561#define CAN_FS1R_FSC25_Msk (0x1UL << CAN_FS1R_FSC25_Pos)
    -
    2562#define CAN_FS1R_FSC25 CAN_FS1R_FSC25_Msk
    -
    2563#define CAN_FS1R_FSC26_Pos (26U)
    -
    2564#define CAN_FS1R_FSC26_Msk (0x1UL << CAN_FS1R_FSC26_Pos)
    -
    2565#define CAN_FS1R_FSC26 CAN_FS1R_FSC26_Msk
    -
    2566#define CAN_FS1R_FSC27_Pos (27U)
    -
    2567#define CAN_FS1R_FSC27_Msk (0x1UL << CAN_FS1R_FSC27_Pos)
    -
    2568#define CAN_FS1R_FSC27 CAN_FS1R_FSC27_Msk
    -
    2570/****************** Bit definition for CAN_FFA1R register *******************/
    -
    2571#define CAN_FFA1R_FFA_Pos (0U)
    -
    2572#define CAN_FFA1R_FFA_Msk (0xFFFFFFFUL << CAN_FFA1R_FFA_Pos)
    -
    2573#define CAN_FFA1R_FFA CAN_FFA1R_FFA_Msk
    -
    2574#define CAN_FFA1R_FFA0_Pos (0U)
    -
    2575#define CAN_FFA1R_FFA0_Msk (0x1UL << CAN_FFA1R_FFA0_Pos)
    -
    2576#define CAN_FFA1R_FFA0 CAN_FFA1R_FFA0_Msk
    -
    2577#define CAN_FFA1R_FFA1_Pos (1U)
    -
    2578#define CAN_FFA1R_FFA1_Msk (0x1UL << CAN_FFA1R_FFA1_Pos)
    -
    2579#define CAN_FFA1R_FFA1 CAN_FFA1R_FFA1_Msk
    -
    2580#define CAN_FFA1R_FFA2_Pos (2U)
    -
    2581#define CAN_FFA1R_FFA2_Msk (0x1UL << CAN_FFA1R_FFA2_Pos)
    -
    2582#define CAN_FFA1R_FFA2 CAN_FFA1R_FFA2_Msk
    -
    2583#define CAN_FFA1R_FFA3_Pos (3U)
    -
    2584#define CAN_FFA1R_FFA3_Msk (0x1UL << CAN_FFA1R_FFA3_Pos)
    -
    2585#define CAN_FFA1R_FFA3 CAN_FFA1R_FFA3_Msk
    -
    2586#define CAN_FFA1R_FFA4_Pos (4U)
    -
    2587#define CAN_FFA1R_FFA4_Msk (0x1UL << CAN_FFA1R_FFA4_Pos)
    -
    2588#define CAN_FFA1R_FFA4 CAN_FFA1R_FFA4_Msk
    -
    2589#define CAN_FFA1R_FFA5_Pos (5U)
    -
    2590#define CAN_FFA1R_FFA5_Msk (0x1UL << CAN_FFA1R_FFA5_Pos)
    -
    2591#define CAN_FFA1R_FFA5 CAN_FFA1R_FFA5_Msk
    -
    2592#define CAN_FFA1R_FFA6_Pos (6U)
    -
    2593#define CAN_FFA1R_FFA6_Msk (0x1UL << CAN_FFA1R_FFA6_Pos)
    -
    2594#define CAN_FFA1R_FFA6 CAN_FFA1R_FFA6_Msk
    -
    2595#define CAN_FFA1R_FFA7_Pos (7U)
    -
    2596#define CAN_FFA1R_FFA7_Msk (0x1UL << CAN_FFA1R_FFA7_Pos)
    -
    2597#define CAN_FFA1R_FFA7 CAN_FFA1R_FFA7_Msk
    -
    2598#define CAN_FFA1R_FFA8_Pos (8U)
    -
    2599#define CAN_FFA1R_FFA8_Msk (0x1UL << CAN_FFA1R_FFA8_Pos)
    -
    2600#define CAN_FFA1R_FFA8 CAN_FFA1R_FFA8_Msk
    -
    2601#define CAN_FFA1R_FFA9_Pos (9U)
    -
    2602#define CAN_FFA1R_FFA9_Msk (0x1UL << CAN_FFA1R_FFA9_Pos)
    -
    2603#define CAN_FFA1R_FFA9 CAN_FFA1R_FFA9_Msk
    -
    2604#define CAN_FFA1R_FFA10_Pos (10U)
    -
    2605#define CAN_FFA1R_FFA10_Msk (0x1UL << CAN_FFA1R_FFA10_Pos)
    -
    2606#define CAN_FFA1R_FFA10 CAN_FFA1R_FFA10_Msk
    -
    2607#define CAN_FFA1R_FFA11_Pos (11U)
    -
    2608#define CAN_FFA1R_FFA11_Msk (0x1UL << CAN_FFA1R_FFA11_Pos)
    -
    2609#define CAN_FFA1R_FFA11 CAN_FFA1R_FFA11_Msk
    -
    2610#define CAN_FFA1R_FFA12_Pos (12U)
    -
    2611#define CAN_FFA1R_FFA12_Msk (0x1UL << CAN_FFA1R_FFA12_Pos)
    -
    2612#define CAN_FFA1R_FFA12 CAN_FFA1R_FFA12_Msk
    -
    2613#define CAN_FFA1R_FFA13_Pos (13U)
    -
    2614#define CAN_FFA1R_FFA13_Msk (0x1UL << CAN_FFA1R_FFA13_Pos)
    -
    2615#define CAN_FFA1R_FFA13 CAN_FFA1R_FFA13_Msk
    -
    2616#define CAN_FFA1R_FFA14_Pos (14U)
    -
    2617#define CAN_FFA1R_FFA14_Msk (0x1UL << CAN_FFA1R_FFA14_Pos)
    -
    2618#define CAN_FFA1R_FFA14 CAN_FFA1R_FFA14_Msk
    -
    2619#define CAN_FFA1R_FFA15_Pos (15U)
    -
    2620#define CAN_FFA1R_FFA15_Msk (0x1UL << CAN_FFA1R_FFA15_Pos)
    -
    2621#define CAN_FFA1R_FFA15 CAN_FFA1R_FFA15_Msk
    -
    2622#define CAN_FFA1R_FFA16_Pos (16U)
    -
    2623#define CAN_FFA1R_FFA16_Msk (0x1UL << CAN_FFA1R_FFA16_Pos)
    -
    2624#define CAN_FFA1R_FFA16 CAN_FFA1R_FFA16_Msk
    -
    2625#define CAN_FFA1R_FFA17_Pos (17U)
    -
    2626#define CAN_FFA1R_FFA17_Msk (0x1UL << CAN_FFA1R_FFA17_Pos)
    -
    2627#define CAN_FFA1R_FFA17 CAN_FFA1R_FFA17_Msk
    -
    2628#define CAN_FFA1R_FFA18_Pos (18U)
    -
    2629#define CAN_FFA1R_FFA18_Msk (0x1UL << CAN_FFA1R_FFA18_Pos)
    -
    2630#define CAN_FFA1R_FFA18 CAN_FFA1R_FFA18_Msk
    -
    2631#define CAN_FFA1R_FFA19_Pos (19U)
    -
    2632#define CAN_FFA1R_FFA19_Msk (0x1UL << CAN_FFA1R_FFA19_Pos)
    -
    2633#define CAN_FFA1R_FFA19 CAN_FFA1R_FFA19_Msk
    -
    2634#define CAN_FFA1R_FFA20_Pos (20U)
    -
    2635#define CAN_FFA1R_FFA20_Msk (0x1UL << CAN_FFA1R_FFA20_Pos)
    -
    2636#define CAN_FFA1R_FFA20 CAN_FFA1R_FFA20_Msk
    -
    2637#define CAN_FFA1R_FFA21_Pos (21U)
    -
    2638#define CAN_FFA1R_FFA21_Msk (0x1UL << CAN_FFA1R_FFA21_Pos)
    -
    2639#define CAN_FFA1R_FFA21 CAN_FFA1R_FFA21_Msk
    -
    2640#define CAN_FFA1R_FFA22_Pos (22U)
    -
    2641#define CAN_FFA1R_FFA22_Msk (0x1UL << CAN_FFA1R_FFA22_Pos)
    -
    2642#define CAN_FFA1R_FFA22 CAN_FFA1R_FFA22_Msk
    -
    2643#define CAN_FFA1R_FFA23_Pos (23U)
    -
    2644#define CAN_FFA1R_FFA23_Msk (0x1UL << CAN_FFA1R_FFA23_Pos)
    -
    2645#define CAN_FFA1R_FFA23 CAN_FFA1R_FFA23_Msk
    -
    2646#define CAN_FFA1R_FFA24_Pos (24U)
    -
    2647#define CAN_FFA1R_FFA24_Msk (0x1UL << CAN_FFA1R_FFA24_Pos)
    -
    2648#define CAN_FFA1R_FFA24 CAN_FFA1R_FFA24_Msk
    -
    2649#define CAN_FFA1R_FFA25_Pos (25U)
    -
    2650#define CAN_FFA1R_FFA25_Msk (0x1UL << CAN_FFA1R_FFA25_Pos)
    -
    2651#define CAN_FFA1R_FFA25 CAN_FFA1R_FFA25_Msk
    -
    2652#define CAN_FFA1R_FFA26_Pos (26U)
    -
    2653#define CAN_FFA1R_FFA26_Msk (0x1UL << CAN_FFA1R_FFA26_Pos)
    -
    2654#define CAN_FFA1R_FFA26 CAN_FFA1R_FFA26_Msk
    -
    2655#define CAN_FFA1R_FFA27_Pos (27U)
    -
    2656#define CAN_FFA1R_FFA27_Msk (0x1UL << CAN_FFA1R_FFA27_Pos)
    -
    2657#define CAN_FFA1R_FFA27 CAN_FFA1R_FFA27_Msk
    -
    2659/******************* Bit definition for CAN_FA1R register *******************/
    -
    2660#define CAN_FA1R_FACT_Pos (0U)
    -
    2661#define CAN_FA1R_FACT_Msk (0xFFFFFFFUL << CAN_FA1R_FACT_Pos)
    -
    2662#define CAN_FA1R_FACT CAN_FA1R_FACT_Msk
    -
    2663#define CAN_FA1R_FACT0_Pos (0U)
    -
    2664#define CAN_FA1R_FACT0_Msk (0x1UL << CAN_FA1R_FACT0_Pos)
    -
    2665#define CAN_FA1R_FACT0 CAN_FA1R_FACT0_Msk
    -
    2666#define CAN_FA1R_FACT1_Pos (1U)
    -
    2667#define CAN_FA1R_FACT1_Msk (0x1UL << CAN_FA1R_FACT1_Pos)
    -
    2668#define CAN_FA1R_FACT1 CAN_FA1R_FACT1_Msk
    -
    2669#define CAN_FA1R_FACT2_Pos (2U)
    -
    2670#define CAN_FA1R_FACT2_Msk (0x1UL << CAN_FA1R_FACT2_Pos)
    -
    2671#define CAN_FA1R_FACT2 CAN_FA1R_FACT2_Msk
    -
    2672#define CAN_FA1R_FACT3_Pos (3U)
    -
    2673#define CAN_FA1R_FACT3_Msk (0x1UL << CAN_FA1R_FACT3_Pos)
    -
    2674#define CAN_FA1R_FACT3 CAN_FA1R_FACT3_Msk
    -
    2675#define CAN_FA1R_FACT4_Pos (4U)
    -
    2676#define CAN_FA1R_FACT4_Msk (0x1UL << CAN_FA1R_FACT4_Pos)
    -
    2677#define CAN_FA1R_FACT4 CAN_FA1R_FACT4_Msk
    -
    2678#define CAN_FA1R_FACT5_Pos (5U)
    -
    2679#define CAN_FA1R_FACT5_Msk (0x1UL << CAN_FA1R_FACT5_Pos)
    -
    2680#define CAN_FA1R_FACT5 CAN_FA1R_FACT5_Msk
    -
    2681#define CAN_FA1R_FACT6_Pos (6U)
    -
    2682#define CAN_FA1R_FACT6_Msk (0x1UL << CAN_FA1R_FACT6_Pos)
    -
    2683#define CAN_FA1R_FACT6 CAN_FA1R_FACT6_Msk
    -
    2684#define CAN_FA1R_FACT7_Pos (7U)
    -
    2685#define CAN_FA1R_FACT7_Msk (0x1UL << CAN_FA1R_FACT7_Pos)
    -
    2686#define CAN_FA1R_FACT7 CAN_FA1R_FACT7_Msk
    -
    2687#define CAN_FA1R_FACT8_Pos (8U)
    -
    2688#define CAN_FA1R_FACT8_Msk (0x1UL << CAN_FA1R_FACT8_Pos)
    -
    2689#define CAN_FA1R_FACT8 CAN_FA1R_FACT8_Msk
    -
    2690#define CAN_FA1R_FACT9_Pos (9U)
    -
    2691#define CAN_FA1R_FACT9_Msk (0x1UL << CAN_FA1R_FACT9_Pos)
    -
    2692#define CAN_FA1R_FACT9 CAN_FA1R_FACT9_Msk
    -
    2693#define CAN_FA1R_FACT10_Pos (10U)
    -
    2694#define CAN_FA1R_FACT10_Msk (0x1UL << CAN_FA1R_FACT10_Pos)
    -
    2695#define CAN_FA1R_FACT10 CAN_FA1R_FACT10_Msk
    -
    2696#define CAN_FA1R_FACT11_Pos (11U)
    -
    2697#define CAN_FA1R_FACT11_Msk (0x1UL << CAN_FA1R_FACT11_Pos)
    -
    2698#define CAN_FA1R_FACT11 CAN_FA1R_FACT11_Msk
    -
    2699#define CAN_FA1R_FACT12_Pos (12U)
    -
    2700#define CAN_FA1R_FACT12_Msk (0x1UL << CAN_FA1R_FACT12_Pos)
    -
    2701#define CAN_FA1R_FACT12 CAN_FA1R_FACT12_Msk
    -
    2702#define CAN_FA1R_FACT13_Pos (13U)
    -
    2703#define CAN_FA1R_FACT13_Msk (0x1UL << CAN_FA1R_FACT13_Pos)
    -
    2704#define CAN_FA1R_FACT13 CAN_FA1R_FACT13_Msk
    -
    2705#define CAN_FA1R_FACT14_Pos (14U)
    -
    2706#define CAN_FA1R_FACT14_Msk (0x1UL << CAN_FA1R_FACT14_Pos)
    -
    2707#define CAN_FA1R_FACT14 CAN_FA1R_FACT14_Msk
    -
    2708#define CAN_FA1R_FACT15_Pos (15U)
    -
    2709#define CAN_FA1R_FACT15_Msk (0x1UL << CAN_FA1R_FACT15_Pos)
    -
    2710#define CAN_FA1R_FACT15 CAN_FA1R_FACT15_Msk
    -
    2711#define CAN_FA1R_FACT16_Pos (16U)
    -
    2712#define CAN_FA1R_FACT16_Msk (0x1UL << CAN_FA1R_FACT16_Pos)
    -
    2713#define CAN_FA1R_FACT16 CAN_FA1R_FACT16_Msk
    -
    2714#define CAN_FA1R_FACT17_Pos (17U)
    -
    2715#define CAN_FA1R_FACT17_Msk (0x1UL << CAN_FA1R_FACT17_Pos)
    -
    2716#define CAN_FA1R_FACT17 CAN_FA1R_FACT17_Msk
    -
    2717#define CAN_FA1R_FACT18_Pos (18U)
    -
    2718#define CAN_FA1R_FACT18_Msk (0x1UL << CAN_FA1R_FACT18_Pos)
    -
    2719#define CAN_FA1R_FACT18 CAN_FA1R_FACT18_Msk
    -
    2720#define CAN_FA1R_FACT19_Pos (19U)
    -
    2721#define CAN_FA1R_FACT19_Msk (0x1UL << CAN_FA1R_FACT19_Pos)
    -
    2722#define CAN_FA1R_FACT19 CAN_FA1R_FACT19_Msk
    -
    2723#define CAN_FA1R_FACT20_Pos (20U)
    -
    2724#define CAN_FA1R_FACT20_Msk (0x1UL << CAN_FA1R_FACT20_Pos)
    -
    2725#define CAN_FA1R_FACT20 CAN_FA1R_FACT20_Msk
    -
    2726#define CAN_FA1R_FACT21_Pos (21U)
    -
    2727#define CAN_FA1R_FACT21_Msk (0x1UL << CAN_FA1R_FACT21_Pos)
    -
    2728#define CAN_FA1R_FACT21 CAN_FA1R_FACT21_Msk
    -
    2729#define CAN_FA1R_FACT22_Pos (22U)
    -
    2730#define CAN_FA1R_FACT22_Msk (0x1UL << CAN_FA1R_FACT22_Pos)
    -
    2731#define CAN_FA1R_FACT22 CAN_FA1R_FACT22_Msk
    -
    2732#define CAN_FA1R_FACT23_Pos (23U)
    -
    2733#define CAN_FA1R_FACT23_Msk (0x1UL << CAN_FA1R_FACT23_Pos)
    -
    2734#define CAN_FA1R_FACT23 CAN_FA1R_FACT23_Msk
    -
    2735#define CAN_FA1R_FACT24_Pos (24U)
    -
    2736#define CAN_FA1R_FACT24_Msk (0x1UL << CAN_FA1R_FACT24_Pos)
    -
    2737#define CAN_FA1R_FACT24 CAN_FA1R_FACT24_Msk
    -
    2738#define CAN_FA1R_FACT25_Pos (25U)
    -
    2739#define CAN_FA1R_FACT25_Msk (0x1UL << CAN_FA1R_FACT25_Pos)
    -
    2740#define CAN_FA1R_FACT25 CAN_FA1R_FACT25_Msk
    -
    2741#define CAN_FA1R_FACT26_Pos (26U)
    -
    2742#define CAN_FA1R_FACT26_Msk (0x1UL << CAN_FA1R_FACT26_Pos)
    -
    2743#define CAN_FA1R_FACT26 CAN_FA1R_FACT26_Msk
    -
    2744#define CAN_FA1R_FACT27_Pos (27U)
    -
    2745#define CAN_FA1R_FACT27_Msk (0x1UL << CAN_FA1R_FACT27_Pos)
    -
    2746#define CAN_FA1R_FACT27 CAN_FA1R_FACT27_Msk
    -
    2749/******************* Bit definition for CAN_F0R1 register *******************/
    -
    2750#define CAN_F0R1_FB0_Pos (0U)
    -
    2751#define CAN_F0R1_FB0_Msk (0x1UL << CAN_F0R1_FB0_Pos)
    -
    2752#define CAN_F0R1_FB0 CAN_F0R1_FB0_Msk
    -
    2753#define CAN_F0R1_FB1_Pos (1U)
    -
    2754#define CAN_F0R1_FB1_Msk (0x1UL << CAN_F0R1_FB1_Pos)
    -
    2755#define CAN_F0R1_FB1 CAN_F0R1_FB1_Msk
    -
    2756#define CAN_F0R1_FB2_Pos (2U)
    -
    2757#define CAN_F0R1_FB2_Msk (0x1UL << CAN_F0R1_FB2_Pos)
    -
    2758#define CAN_F0R1_FB2 CAN_F0R1_FB2_Msk
    -
    2759#define CAN_F0R1_FB3_Pos (3U)
    -
    2760#define CAN_F0R1_FB3_Msk (0x1UL << CAN_F0R1_FB3_Pos)
    -
    2761#define CAN_F0R1_FB3 CAN_F0R1_FB3_Msk
    -
    2762#define CAN_F0R1_FB4_Pos (4U)
    -
    2763#define CAN_F0R1_FB4_Msk (0x1UL << CAN_F0R1_FB4_Pos)
    -
    2764#define CAN_F0R1_FB4 CAN_F0R1_FB4_Msk
    -
    2765#define CAN_F0R1_FB5_Pos (5U)
    -
    2766#define CAN_F0R1_FB5_Msk (0x1UL << CAN_F0R1_FB5_Pos)
    -
    2767#define CAN_F0R1_FB5 CAN_F0R1_FB5_Msk
    -
    2768#define CAN_F0R1_FB6_Pos (6U)
    -
    2769#define CAN_F0R1_FB6_Msk (0x1UL << CAN_F0R1_FB6_Pos)
    -
    2770#define CAN_F0R1_FB6 CAN_F0R1_FB6_Msk
    -
    2771#define CAN_F0R1_FB7_Pos (7U)
    -
    2772#define CAN_F0R1_FB7_Msk (0x1UL << CAN_F0R1_FB7_Pos)
    -
    2773#define CAN_F0R1_FB7 CAN_F0R1_FB7_Msk
    -
    2774#define CAN_F0R1_FB8_Pos (8U)
    -
    2775#define CAN_F0R1_FB8_Msk (0x1UL << CAN_F0R1_FB8_Pos)
    -
    2776#define CAN_F0R1_FB8 CAN_F0R1_FB8_Msk
    -
    2777#define CAN_F0R1_FB9_Pos (9U)
    -
    2778#define CAN_F0R1_FB9_Msk (0x1UL << CAN_F0R1_FB9_Pos)
    -
    2779#define CAN_F0R1_FB9 CAN_F0R1_FB9_Msk
    -
    2780#define CAN_F0R1_FB10_Pos (10U)
    -
    2781#define CAN_F0R1_FB10_Msk (0x1UL << CAN_F0R1_FB10_Pos)
    -
    2782#define CAN_F0R1_FB10 CAN_F0R1_FB10_Msk
    -
    2783#define CAN_F0R1_FB11_Pos (11U)
    -
    2784#define CAN_F0R1_FB11_Msk (0x1UL << CAN_F0R1_FB11_Pos)
    -
    2785#define CAN_F0R1_FB11 CAN_F0R1_FB11_Msk
    -
    2786#define CAN_F0R1_FB12_Pos (12U)
    -
    2787#define CAN_F0R1_FB12_Msk (0x1UL << CAN_F0R1_FB12_Pos)
    -
    2788#define CAN_F0R1_FB12 CAN_F0R1_FB12_Msk
    -
    2789#define CAN_F0R1_FB13_Pos (13U)
    -
    2790#define CAN_F0R1_FB13_Msk (0x1UL << CAN_F0R1_FB13_Pos)
    -
    2791#define CAN_F0R1_FB13 CAN_F0R1_FB13_Msk
    -
    2792#define CAN_F0R1_FB14_Pos (14U)
    -
    2793#define CAN_F0R1_FB14_Msk (0x1UL << CAN_F0R1_FB14_Pos)
    -
    2794#define CAN_F0R1_FB14 CAN_F0R1_FB14_Msk
    -
    2795#define CAN_F0R1_FB15_Pos (15U)
    -
    2796#define CAN_F0R1_FB15_Msk (0x1UL << CAN_F0R1_FB15_Pos)
    -
    2797#define CAN_F0R1_FB15 CAN_F0R1_FB15_Msk
    -
    2798#define CAN_F0R1_FB16_Pos (16U)
    -
    2799#define CAN_F0R1_FB16_Msk (0x1UL << CAN_F0R1_FB16_Pos)
    -
    2800#define CAN_F0R1_FB16 CAN_F0R1_FB16_Msk
    -
    2801#define CAN_F0R1_FB17_Pos (17U)
    -
    2802#define CAN_F0R1_FB17_Msk (0x1UL << CAN_F0R1_FB17_Pos)
    -
    2803#define CAN_F0R1_FB17 CAN_F0R1_FB17_Msk
    -
    2804#define CAN_F0R1_FB18_Pos (18U)
    -
    2805#define CAN_F0R1_FB18_Msk (0x1UL << CAN_F0R1_FB18_Pos)
    -
    2806#define CAN_F0R1_FB18 CAN_F0R1_FB18_Msk
    -
    2807#define CAN_F0R1_FB19_Pos (19U)
    -
    2808#define CAN_F0R1_FB19_Msk (0x1UL << CAN_F0R1_FB19_Pos)
    -
    2809#define CAN_F0R1_FB19 CAN_F0R1_FB19_Msk
    -
    2810#define CAN_F0R1_FB20_Pos (20U)
    -
    2811#define CAN_F0R1_FB20_Msk (0x1UL << CAN_F0R1_FB20_Pos)
    -
    2812#define CAN_F0R1_FB20 CAN_F0R1_FB20_Msk
    -
    2813#define CAN_F0R1_FB21_Pos (21U)
    -
    2814#define CAN_F0R1_FB21_Msk (0x1UL << CAN_F0R1_FB21_Pos)
    -
    2815#define CAN_F0R1_FB21 CAN_F0R1_FB21_Msk
    -
    2816#define CAN_F0R1_FB22_Pos (22U)
    -
    2817#define CAN_F0R1_FB22_Msk (0x1UL << CAN_F0R1_FB22_Pos)
    -
    2818#define CAN_F0R1_FB22 CAN_F0R1_FB22_Msk
    -
    2819#define CAN_F0R1_FB23_Pos (23U)
    -
    2820#define CAN_F0R1_FB23_Msk (0x1UL << CAN_F0R1_FB23_Pos)
    -
    2821#define CAN_F0R1_FB23 CAN_F0R1_FB23_Msk
    -
    2822#define CAN_F0R1_FB24_Pos (24U)
    -
    2823#define CAN_F0R1_FB24_Msk (0x1UL << CAN_F0R1_FB24_Pos)
    -
    2824#define CAN_F0R1_FB24 CAN_F0R1_FB24_Msk
    -
    2825#define CAN_F0R1_FB25_Pos (25U)
    -
    2826#define CAN_F0R1_FB25_Msk (0x1UL << CAN_F0R1_FB25_Pos)
    -
    2827#define CAN_F0R1_FB25 CAN_F0R1_FB25_Msk
    -
    2828#define CAN_F0R1_FB26_Pos (26U)
    -
    2829#define CAN_F0R1_FB26_Msk (0x1UL << CAN_F0R1_FB26_Pos)
    -
    2830#define CAN_F0R1_FB26 CAN_F0R1_FB26_Msk
    -
    2831#define CAN_F0R1_FB27_Pos (27U)
    -
    2832#define CAN_F0R1_FB27_Msk (0x1UL << CAN_F0R1_FB27_Pos)
    -
    2833#define CAN_F0R1_FB27 CAN_F0R1_FB27_Msk
    -
    2834#define CAN_F0R1_FB28_Pos (28U)
    -
    2835#define CAN_F0R1_FB28_Msk (0x1UL << CAN_F0R1_FB28_Pos)
    -
    2836#define CAN_F0R1_FB28 CAN_F0R1_FB28_Msk
    -
    2837#define CAN_F0R1_FB29_Pos (29U)
    -
    2838#define CAN_F0R1_FB29_Msk (0x1UL << CAN_F0R1_FB29_Pos)
    -
    2839#define CAN_F0R1_FB29 CAN_F0R1_FB29_Msk
    -
    2840#define CAN_F0R1_FB30_Pos (30U)
    -
    2841#define CAN_F0R1_FB30_Msk (0x1UL << CAN_F0R1_FB30_Pos)
    -
    2842#define CAN_F0R1_FB30 CAN_F0R1_FB30_Msk
    -
    2843#define CAN_F0R1_FB31_Pos (31U)
    -
    2844#define CAN_F0R1_FB31_Msk (0x1UL << CAN_F0R1_FB31_Pos)
    -
    2845#define CAN_F0R1_FB31 CAN_F0R1_FB31_Msk
    -
    2847/******************* Bit definition for CAN_F1R1 register *******************/
    -
    2848#define CAN_F1R1_FB0_Pos (0U)
    -
    2849#define CAN_F1R1_FB0_Msk (0x1UL << CAN_F1R1_FB0_Pos)
    -
    2850#define CAN_F1R1_FB0 CAN_F1R1_FB0_Msk
    -
    2851#define CAN_F1R1_FB1_Pos (1U)
    -
    2852#define CAN_F1R1_FB1_Msk (0x1UL << CAN_F1R1_FB1_Pos)
    -
    2853#define CAN_F1R1_FB1 CAN_F1R1_FB1_Msk
    -
    2854#define CAN_F1R1_FB2_Pos (2U)
    -
    2855#define CAN_F1R1_FB2_Msk (0x1UL << CAN_F1R1_FB2_Pos)
    -
    2856#define CAN_F1R1_FB2 CAN_F1R1_FB2_Msk
    -
    2857#define CAN_F1R1_FB3_Pos (3U)
    -
    2858#define CAN_F1R1_FB3_Msk (0x1UL << CAN_F1R1_FB3_Pos)
    -
    2859#define CAN_F1R1_FB3 CAN_F1R1_FB3_Msk
    -
    2860#define CAN_F1R1_FB4_Pos (4U)
    -
    2861#define CAN_F1R1_FB4_Msk (0x1UL << CAN_F1R1_FB4_Pos)
    -
    2862#define CAN_F1R1_FB4 CAN_F1R1_FB4_Msk
    -
    2863#define CAN_F1R1_FB5_Pos (5U)
    -
    2864#define CAN_F1R1_FB5_Msk (0x1UL << CAN_F1R1_FB5_Pos)
    -
    2865#define CAN_F1R1_FB5 CAN_F1R1_FB5_Msk
    -
    2866#define CAN_F1R1_FB6_Pos (6U)
    -
    2867#define CAN_F1R1_FB6_Msk (0x1UL << CAN_F1R1_FB6_Pos)
    -
    2868#define CAN_F1R1_FB6 CAN_F1R1_FB6_Msk
    -
    2869#define CAN_F1R1_FB7_Pos (7U)
    -
    2870#define CAN_F1R1_FB7_Msk (0x1UL << CAN_F1R1_FB7_Pos)
    -
    2871#define CAN_F1R1_FB7 CAN_F1R1_FB7_Msk
    -
    2872#define CAN_F1R1_FB8_Pos (8U)
    -
    2873#define CAN_F1R1_FB8_Msk (0x1UL << CAN_F1R1_FB8_Pos)
    -
    2874#define CAN_F1R1_FB8 CAN_F1R1_FB8_Msk
    -
    2875#define CAN_F1R1_FB9_Pos (9U)
    -
    2876#define CAN_F1R1_FB9_Msk (0x1UL << CAN_F1R1_FB9_Pos)
    -
    2877#define CAN_F1R1_FB9 CAN_F1R1_FB9_Msk
    -
    2878#define CAN_F1R1_FB10_Pos (10U)
    -
    2879#define CAN_F1R1_FB10_Msk (0x1UL << CAN_F1R1_FB10_Pos)
    -
    2880#define CAN_F1R1_FB10 CAN_F1R1_FB10_Msk
    -
    2881#define CAN_F1R1_FB11_Pos (11U)
    -
    2882#define CAN_F1R1_FB11_Msk (0x1UL << CAN_F1R1_FB11_Pos)
    -
    2883#define CAN_F1R1_FB11 CAN_F1R1_FB11_Msk
    -
    2884#define CAN_F1R1_FB12_Pos (12U)
    -
    2885#define CAN_F1R1_FB12_Msk (0x1UL << CAN_F1R1_FB12_Pos)
    -
    2886#define CAN_F1R1_FB12 CAN_F1R1_FB12_Msk
    -
    2887#define CAN_F1R1_FB13_Pos (13U)
    -
    2888#define CAN_F1R1_FB13_Msk (0x1UL << CAN_F1R1_FB13_Pos)
    -
    2889#define CAN_F1R1_FB13 CAN_F1R1_FB13_Msk
    -
    2890#define CAN_F1R1_FB14_Pos (14U)
    -
    2891#define CAN_F1R1_FB14_Msk (0x1UL << CAN_F1R1_FB14_Pos)
    -
    2892#define CAN_F1R1_FB14 CAN_F1R1_FB14_Msk
    -
    2893#define CAN_F1R1_FB15_Pos (15U)
    -
    2894#define CAN_F1R1_FB15_Msk (0x1UL << CAN_F1R1_FB15_Pos)
    -
    2895#define CAN_F1R1_FB15 CAN_F1R1_FB15_Msk
    -
    2896#define CAN_F1R1_FB16_Pos (16U)
    -
    2897#define CAN_F1R1_FB16_Msk (0x1UL << CAN_F1R1_FB16_Pos)
    -
    2898#define CAN_F1R1_FB16 CAN_F1R1_FB16_Msk
    -
    2899#define CAN_F1R1_FB17_Pos (17U)
    -
    2900#define CAN_F1R1_FB17_Msk (0x1UL << CAN_F1R1_FB17_Pos)
    -
    2901#define CAN_F1R1_FB17 CAN_F1R1_FB17_Msk
    -
    2902#define CAN_F1R1_FB18_Pos (18U)
    -
    2903#define CAN_F1R1_FB18_Msk (0x1UL << CAN_F1R1_FB18_Pos)
    -
    2904#define CAN_F1R1_FB18 CAN_F1R1_FB18_Msk
    -
    2905#define CAN_F1R1_FB19_Pos (19U)
    -
    2906#define CAN_F1R1_FB19_Msk (0x1UL << CAN_F1R1_FB19_Pos)
    -
    2907#define CAN_F1R1_FB19 CAN_F1R1_FB19_Msk
    -
    2908#define CAN_F1R1_FB20_Pos (20U)
    -
    2909#define CAN_F1R1_FB20_Msk (0x1UL << CAN_F1R1_FB20_Pos)
    -
    2910#define CAN_F1R1_FB20 CAN_F1R1_FB20_Msk
    -
    2911#define CAN_F1R1_FB21_Pos (21U)
    -
    2912#define CAN_F1R1_FB21_Msk (0x1UL << CAN_F1R1_FB21_Pos)
    -
    2913#define CAN_F1R1_FB21 CAN_F1R1_FB21_Msk
    -
    2914#define CAN_F1R1_FB22_Pos (22U)
    -
    2915#define CAN_F1R1_FB22_Msk (0x1UL << CAN_F1R1_FB22_Pos)
    -
    2916#define CAN_F1R1_FB22 CAN_F1R1_FB22_Msk
    -
    2917#define CAN_F1R1_FB23_Pos (23U)
    -
    2918#define CAN_F1R1_FB23_Msk (0x1UL << CAN_F1R1_FB23_Pos)
    -
    2919#define CAN_F1R1_FB23 CAN_F1R1_FB23_Msk
    -
    2920#define CAN_F1R1_FB24_Pos (24U)
    -
    2921#define CAN_F1R1_FB24_Msk (0x1UL << CAN_F1R1_FB24_Pos)
    -
    2922#define CAN_F1R1_FB24 CAN_F1R1_FB24_Msk
    -
    2923#define CAN_F1R1_FB25_Pos (25U)
    -
    2924#define CAN_F1R1_FB25_Msk (0x1UL << CAN_F1R1_FB25_Pos)
    -
    2925#define CAN_F1R1_FB25 CAN_F1R1_FB25_Msk
    -
    2926#define CAN_F1R1_FB26_Pos (26U)
    -
    2927#define CAN_F1R1_FB26_Msk (0x1UL << CAN_F1R1_FB26_Pos)
    -
    2928#define CAN_F1R1_FB26 CAN_F1R1_FB26_Msk
    -
    2929#define CAN_F1R1_FB27_Pos (27U)
    -
    2930#define CAN_F1R1_FB27_Msk (0x1UL << CAN_F1R1_FB27_Pos)
    -
    2931#define CAN_F1R1_FB27 CAN_F1R1_FB27_Msk
    -
    2932#define CAN_F1R1_FB28_Pos (28U)
    -
    2933#define CAN_F1R1_FB28_Msk (0x1UL << CAN_F1R1_FB28_Pos)
    -
    2934#define CAN_F1R1_FB28 CAN_F1R1_FB28_Msk
    -
    2935#define CAN_F1R1_FB29_Pos (29U)
    -
    2936#define CAN_F1R1_FB29_Msk (0x1UL << CAN_F1R1_FB29_Pos)
    -
    2937#define CAN_F1R1_FB29 CAN_F1R1_FB29_Msk
    -
    2938#define CAN_F1R1_FB30_Pos (30U)
    -
    2939#define CAN_F1R1_FB30_Msk (0x1UL << CAN_F1R1_FB30_Pos)
    -
    2940#define CAN_F1R1_FB30 CAN_F1R1_FB30_Msk
    -
    2941#define CAN_F1R1_FB31_Pos (31U)
    -
    2942#define CAN_F1R1_FB31_Msk (0x1UL << CAN_F1R1_FB31_Pos)
    -
    2943#define CAN_F1R1_FB31 CAN_F1R1_FB31_Msk
    -
    2945/******************* Bit definition for CAN_F2R1 register *******************/
    -
    2946#define CAN_F2R1_FB0_Pos (0U)
    -
    2947#define CAN_F2R1_FB0_Msk (0x1UL << CAN_F2R1_FB0_Pos)
    -
    2948#define CAN_F2R1_FB0 CAN_F2R1_FB0_Msk
    -
    2949#define CAN_F2R1_FB1_Pos (1U)
    -
    2950#define CAN_F2R1_FB1_Msk (0x1UL << CAN_F2R1_FB1_Pos)
    -
    2951#define CAN_F2R1_FB1 CAN_F2R1_FB1_Msk
    -
    2952#define CAN_F2R1_FB2_Pos (2U)
    -
    2953#define CAN_F2R1_FB2_Msk (0x1UL << CAN_F2R1_FB2_Pos)
    -
    2954#define CAN_F2R1_FB2 CAN_F2R1_FB2_Msk
    -
    2955#define CAN_F2R1_FB3_Pos (3U)
    -
    2956#define CAN_F2R1_FB3_Msk (0x1UL << CAN_F2R1_FB3_Pos)
    -
    2957#define CAN_F2R1_FB3 CAN_F2R1_FB3_Msk
    -
    2958#define CAN_F2R1_FB4_Pos (4U)
    -
    2959#define CAN_F2R1_FB4_Msk (0x1UL << CAN_F2R1_FB4_Pos)
    -
    2960#define CAN_F2R1_FB4 CAN_F2R1_FB4_Msk
    -
    2961#define CAN_F2R1_FB5_Pos (5U)
    -
    2962#define CAN_F2R1_FB5_Msk (0x1UL << CAN_F2R1_FB5_Pos)
    -
    2963#define CAN_F2R1_FB5 CAN_F2R1_FB5_Msk
    -
    2964#define CAN_F2R1_FB6_Pos (6U)
    -
    2965#define CAN_F2R1_FB6_Msk (0x1UL << CAN_F2R1_FB6_Pos)
    -
    2966#define CAN_F2R1_FB6 CAN_F2R1_FB6_Msk
    -
    2967#define CAN_F2R1_FB7_Pos (7U)
    -
    2968#define CAN_F2R1_FB7_Msk (0x1UL << CAN_F2R1_FB7_Pos)
    -
    2969#define CAN_F2R1_FB7 CAN_F2R1_FB7_Msk
    -
    2970#define CAN_F2R1_FB8_Pos (8U)
    -
    2971#define CAN_F2R1_FB8_Msk (0x1UL << CAN_F2R1_FB8_Pos)
    -
    2972#define CAN_F2R1_FB8 CAN_F2R1_FB8_Msk
    -
    2973#define CAN_F2R1_FB9_Pos (9U)
    -
    2974#define CAN_F2R1_FB9_Msk (0x1UL << CAN_F2R1_FB9_Pos)
    -
    2975#define CAN_F2R1_FB9 CAN_F2R1_FB9_Msk
    -
    2976#define CAN_F2R1_FB10_Pos (10U)
    -
    2977#define CAN_F2R1_FB10_Msk (0x1UL << CAN_F2R1_FB10_Pos)
    -
    2978#define CAN_F2R1_FB10 CAN_F2R1_FB10_Msk
    -
    2979#define CAN_F2R1_FB11_Pos (11U)
    -
    2980#define CAN_F2R1_FB11_Msk (0x1UL << CAN_F2R1_FB11_Pos)
    -
    2981#define CAN_F2R1_FB11 CAN_F2R1_FB11_Msk
    -
    2982#define CAN_F2R1_FB12_Pos (12U)
    -
    2983#define CAN_F2R1_FB12_Msk (0x1UL << CAN_F2R1_FB12_Pos)
    -
    2984#define CAN_F2R1_FB12 CAN_F2R1_FB12_Msk
    -
    2985#define CAN_F2R1_FB13_Pos (13U)
    -
    2986#define CAN_F2R1_FB13_Msk (0x1UL << CAN_F2R1_FB13_Pos)
    -
    2987#define CAN_F2R1_FB13 CAN_F2R1_FB13_Msk
    -
    2988#define CAN_F2R1_FB14_Pos (14U)
    -
    2989#define CAN_F2R1_FB14_Msk (0x1UL << CAN_F2R1_FB14_Pos)
    -
    2990#define CAN_F2R1_FB14 CAN_F2R1_FB14_Msk
    -
    2991#define CAN_F2R1_FB15_Pos (15U)
    -
    2992#define CAN_F2R1_FB15_Msk (0x1UL << CAN_F2R1_FB15_Pos)
    -
    2993#define CAN_F2R1_FB15 CAN_F2R1_FB15_Msk
    -
    2994#define CAN_F2R1_FB16_Pos (16U)
    -
    2995#define CAN_F2R1_FB16_Msk (0x1UL << CAN_F2R1_FB16_Pos)
    -
    2996#define CAN_F2R1_FB16 CAN_F2R1_FB16_Msk
    -
    2997#define CAN_F2R1_FB17_Pos (17U)
    -
    2998#define CAN_F2R1_FB17_Msk (0x1UL << CAN_F2R1_FB17_Pos)
    -
    2999#define CAN_F2R1_FB17 CAN_F2R1_FB17_Msk
    -
    3000#define CAN_F2R1_FB18_Pos (18U)
    -
    3001#define CAN_F2R1_FB18_Msk (0x1UL << CAN_F2R1_FB18_Pos)
    -
    3002#define CAN_F2R1_FB18 CAN_F2R1_FB18_Msk
    -
    3003#define CAN_F2R1_FB19_Pos (19U)
    -
    3004#define CAN_F2R1_FB19_Msk (0x1UL << CAN_F2R1_FB19_Pos)
    -
    3005#define CAN_F2R1_FB19 CAN_F2R1_FB19_Msk
    -
    3006#define CAN_F2R1_FB20_Pos (20U)
    -
    3007#define CAN_F2R1_FB20_Msk (0x1UL << CAN_F2R1_FB20_Pos)
    -
    3008#define CAN_F2R1_FB20 CAN_F2R1_FB20_Msk
    -
    3009#define CAN_F2R1_FB21_Pos (21U)
    -
    3010#define CAN_F2R1_FB21_Msk (0x1UL << CAN_F2R1_FB21_Pos)
    -
    3011#define CAN_F2R1_FB21 CAN_F2R1_FB21_Msk
    -
    3012#define CAN_F2R1_FB22_Pos (22U)
    -
    3013#define CAN_F2R1_FB22_Msk (0x1UL << CAN_F2R1_FB22_Pos)
    -
    3014#define CAN_F2R1_FB22 CAN_F2R1_FB22_Msk
    -
    3015#define CAN_F2R1_FB23_Pos (23U)
    -
    3016#define CAN_F2R1_FB23_Msk (0x1UL << CAN_F2R1_FB23_Pos)
    -
    3017#define CAN_F2R1_FB23 CAN_F2R1_FB23_Msk
    -
    3018#define CAN_F2R1_FB24_Pos (24U)
    -
    3019#define CAN_F2R1_FB24_Msk (0x1UL << CAN_F2R1_FB24_Pos)
    -
    3020#define CAN_F2R1_FB24 CAN_F2R1_FB24_Msk
    -
    3021#define CAN_F2R1_FB25_Pos (25U)
    -
    3022#define CAN_F2R1_FB25_Msk (0x1UL << CAN_F2R1_FB25_Pos)
    -
    3023#define CAN_F2R1_FB25 CAN_F2R1_FB25_Msk
    -
    3024#define CAN_F2R1_FB26_Pos (26U)
    -
    3025#define CAN_F2R1_FB26_Msk (0x1UL << CAN_F2R1_FB26_Pos)
    -
    3026#define CAN_F2R1_FB26 CAN_F2R1_FB26_Msk
    -
    3027#define CAN_F2R1_FB27_Pos (27U)
    -
    3028#define CAN_F2R1_FB27_Msk (0x1UL << CAN_F2R1_FB27_Pos)
    -
    3029#define CAN_F2R1_FB27 CAN_F2R1_FB27_Msk
    -
    3030#define CAN_F2R1_FB28_Pos (28U)
    -
    3031#define CAN_F2R1_FB28_Msk (0x1UL << CAN_F2R1_FB28_Pos)
    -
    3032#define CAN_F2R1_FB28 CAN_F2R1_FB28_Msk
    -
    3033#define CAN_F2R1_FB29_Pos (29U)
    -
    3034#define CAN_F2R1_FB29_Msk (0x1UL << CAN_F2R1_FB29_Pos)
    -
    3035#define CAN_F2R1_FB29 CAN_F2R1_FB29_Msk
    -
    3036#define CAN_F2R1_FB30_Pos (30U)
    -
    3037#define CAN_F2R1_FB30_Msk (0x1UL << CAN_F2R1_FB30_Pos)
    -
    3038#define CAN_F2R1_FB30 CAN_F2R1_FB30_Msk
    -
    3039#define CAN_F2R1_FB31_Pos (31U)
    -
    3040#define CAN_F2R1_FB31_Msk (0x1UL << CAN_F2R1_FB31_Pos)
    -
    3041#define CAN_F2R1_FB31 CAN_F2R1_FB31_Msk
    -
    3043/******************* Bit definition for CAN_F3R1 register *******************/
    -
    3044#define CAN_F3R1_FB0_Pos (0U)
    -
    3045#define CAN_F3R1_FB0_Msk (0x1UL << CAN_F3R1_FB0_Pos)
    -
    3046#define CAN_F3R1_FB0 CAN_F3R1_FB0_Msk
    -
    3047#define CAN_F3R1_FB1_Pos (1U)
    -
    3048#define CAN_F3R1_FB1_Msk (0x1UL << CAN_F3R1_FB1_Pos)
    -
    3049#define CAN_F3R1_FB1 CAN_F3R1_FB1_Msk
    -
    3050#define CAN_F3R1_FB2_Pos (2U)
    -
    3051#define CAN_F3R1_FB2_Msk (0x1UL << CAN_F3R1_FB2_Pos)
    -
    3052#define CAN_F3R1_FB2 CAN_F3R1_FB2_Msk
    -
    3053#define CAN_F3R1_FB3_Pos (3U)
    -
    3054#define CAN_F3R1_FB3_Msk (0x1UL << CAN_F3R1_FB3_Pos)
    -
    3055#define CAN_F3R1_FB3 CAN_F3R1_FB3_Msk
    -
    3056#define CAN_F3R1_FB4_Pos (4U)
    -
    3057#define CAN_F3R1_FB4_Msk (0x1UL << CAN_F3R1_FB4_Pos)
    -
    3058#define CAN_F3R1_FB4 CAN_F3R1_FB4_Msk
    -
    3059#define CAN_F3R1_FB5_Pos (5U)
    -
    3060#define CAN_F3R1_FB5_Msk (0x1UL << CAN_F3R1_FB5_Pos)
    -
    3061#define CAN_F3R1_FB5 CAN_F3R1_FB5_Msk
    -
    3062#define CAN_F3R1_FB6_Pos (6U)
    -
    3063#define CAN_F3R1_FB6_Msk (0x1UL << CAN_F3R1_FB6_Pos)
    -
    3064#define CAN_F3R1_FB6 CAN_F3R1_FB6_Msk
    -
    3065#define CAN_F3R1_FB7_Pos (7U)
    -
    3066#define CAN_F3R1_FB7_Msk (0x1UL << CAN_F3R1_FB7_Pos)
    -
    3067#define CAN_F3R1_FB7 CAN_F3R1_FB7_Msk
    -
    3068#define CAN_F3R1_FB8_Pos (8U)
    -
    3069#define CAN_F3R1_FB8_Msk (0x1UL << CAN_F3R1_FB8_Pos)
    -
    3070#define CAN_F3R1_FB8 CAN_F3R1_FB8_Msk
    -
    3071#define CAN_F3R1_FB9_Pos (9U)
    -
    3072#define CAN_F3R1_FB9_Msk (0x1UL << CAN_F3R1_FB9_Pos)
    -
    3073#define CAN_F3R1_FB9 CAN_F3R1_FB9_Msk
    -
    3074#define CAN_F3R1_FB10_Pos (10U)
    -
    3075#define CAN_F3R1_FB10_Msk (0x1UL << CAN_F3R1_FB10_Pos)
    -
    3076#define CAN_F3R1_FB10 CAN_F3R1_FB10_Msk
    -
    3077#define CAN_F3R1_FB11_Pos (11U)
    -
    3078#define CAN_F3R1_FB11_Msk (0x1UL << CAN_F3R1_FB11_Pos)
    -
    3079#define CAN_F3R1_FB11 CAN_F3R1_FB11_Msk
    -
    3080#define CAN_F3R1_FB12_Pos (12U)
    -
    3081#define CAN_F3R1_FB12_Msk (0x1UL << CAN_F3R1_FB12_Pos)
    -
    3082#define CAN_F3R1_FB12 CAN_F3R1_FB12_Msk
    -
    3083#define CAN_F3R1_FB13_Pos (13U)
    -
    3084#define CAN_F3R1_FB13_Msk (0x1UL << CAN_F3R1_FB13_Pos)
    -
    3085#define CAN_F3R1_FB13 CAN_F3R1_FB13_Msk
    -
    3086#define CAN_F3R1_FB14_Pos (14U)
    -
    3087#define CAN_F3R1_FB14_Msk (0x1UL << CAN_F3R1_FB14_Pos)
    -
    3088#define CAN_F3R1_FB14 CAN_F3R1_FB14_Msk
    -
    3089#define CAN_F3R1_FB15_Pos (15U)
    -
    3090#define CAN_F3R1_FB15_Msk (0x1UL << CAN_F3R1_FB15_Pos)
    -
    3091#define CAN_F3R1_FB15 CAN_F3R1_FB15_Msk
    -
    3092#define CAN_F3R1_FB16_Pos (16U)
    -
    3093#define CAN_F3R1_FB16_Msk (0x1UL << CAN_F3R1_FB16_Pos)
    -
    3094#define CAN_F3R1_FB16 CAN_F3R1_FB16_Msk
    -
    3095#define CAN_F3R1_FB17_Pos (17U)
    -
    3096#define CAN_F3R1_FB17_Msk (0x1UL << CAN_F3R1_FB17_Pos)
    -
    3097#define CAN_F3R1_FB17 CAN_F3R1_FB17_Msk
    -
    3098#define CAN_F3R1_FB18_Pos (18U)
    -
    3099#define CAN_F3R1_FB18_Msk (0x1UL << CAN_F3R1_FB18_Pos)
    -
    3100#define CAN_F3R1_FB18 CAN_F3R1_FB18_Msk
    -
    3101#define CAN_F3R1_FB19_Pos (19U)
    -
    3102#define CAN_F3R1_FB19_Msk (0x1UL << CAN_F3R1_FB19_Pos)
    -
    3103#define CAN_F3R1_FB19 CAN_F3R1_FB19_Msk
    -
    3104#define CAN_F3R1_FB20_Pos (20U)
    -
    3105#define CAN_F3R1_FB20_Msk (0x1UL << CAN_F3R1_FB20_Pos)
    -
    3106#define CAN_F3R1_FB20 CAN_F3R1_FB20_Msk
    -
    3107#define CAN_F3R1_FB21_Pos (21U)
    -
    3108#define CAN_F3R1_FB21_Msk (0x1UL << CAN_F3R1_FB21_Pos)
    -
    3109#define CAN_F3R1_FB21 CAN_F3R1_FB21_Msk
    -
    3110#define CAN_F3R1_FB22_Pos (22U)
    -
    3111#define CAN_F3R1_FB22_Msk (0x1UL << CAN_F3R1_FB22_Pos)
    -
    3112#define CAN_F3R1_FB22 CAN_F3R1_FB22_Msk
    -
    3113#define CAN_F3R1_FB23_Pos (23U)
    -
    3114#define CAN_F3R1_FB23_Msk (0x1UL << CAN_F3R1_FB23_Pos)
    -
    3115#define CAN_F3R1_FB23 CAN_F3R1_FB23_Msk
    -
    3116#define CAN_F3R1_FB24_Pos (24U)
    -
    3117#define CAN_F3R1_FB24_Msk (0x1UL << CAN_F3R1_FB24_Pos)
    -
    3118#define CAN_F3R1_FB24 CAN_F3R1_FB24_Msk
    -
    3119#define CAN_F3R1_FB25_Pos (25U)
    -
    3120#define CAN_F3R1_FB25_Msk (0x1UL << CAN_F3R1_FB25_Pos)
    -
    3121#define CAN_F3R1_FB25 CAN_F3R1_FB25_Msk
    -
    3122#define CAN_F3R1_FB26_Pos (26U)
    -
    3123#define CAN_F3R1_FB26_Msk (0x1UL << CAN_F3R1_FB26_Pos)
    -
    3124#define CAN_F3R1_FB26 CAN_F3R1_FB26_Msk
    -
    3125#define CAN_F3R1_FB27_Pos (27U)
    -
    3126#define CAN_F3R1_FB27_Msk (0x1UL << CAN_F3R1_FB27_Pos)
    -
    3127#define CAN_F3R1_FB27 CAN_F3R1_FB27_Msk
    -
    3128#define CAN_F3R1_FB28_Pos (28U)
    -
    3129#define CAN_F3R1_FB28_Msk (0x1UL << CAN_F3R1_FB28_Pos)
    -
    3130#define CAN_F3R1_FB28 CAN_F3R1_FB28_Msk
    -
    3131#define CAN_F3R1_FB29_Pos (29U)
    -
    3132#define CAN_F3R1_FB29_Msk (0x1UL << CAN_F3R1_FB29_Pos)
    -
    3133#define CAN_F3R1_FB29 CAN_F3R1_FB29_Msk
    -
    3134#define CAN_F3R1_FB30_Pos (30U)
    -
    3135#define CAN_F3R1_FB30_Msk (0x1UL << CAN_F3R1_FB30_Pos)
    -
    3136#define CAN_F3R1_FB30 CAN_F3R1_FB30_Msk
    -
    3137#define CAN_F3R1_FB31_Pos (31U)
    -
    3138#define CAN_F3R1_FB31_Msk (0x1UL << CAN_F3R1_FB31_Pos)
    -
    3139#define CAN_F3R1_FB31 CAN_F3R1_FB31_Msk
    -
    3141/******************* Bit definition for CAN_F4R1 register *******************/
    -
    3142#define CAN_F4R1_FB0_Pos (0U)
    -
    3143#define CAN_F4R1_FB0_Msk (0x1UL << CAN_F4R1_FB0_Pos)
    -
    3144#define CAN_F4R1_FB0 CAN_F4R1_FB0_Msk
    -
    3145#define CAN_F4R1_FB1_Pos (1U)
    -
    3146#define CAN_F4R1_FB1_Msk (0x1UL << CAN_F4R1_FB1_Pos)
    -
    3147#define CAN_F4R1_FB1 CAN_F4R1_FB1_Msk
    -
    3148#define CAN_F4R1_FB2_Pos (2U)
    -
    3149#define CAN_F4R1_FB2_Msk (0x1UL << CAN_F4R1_FB2_Pos)
    -
    3150#define CAN_F4R1_FB2 CAN_F4R1_FB2_Msk
    -
    3151#define CAN_F4R1_FB3_Pos (3U)
    -
    3152#define CAN_F4R1_FB3_Msk (0x1UL << CAN_F4R1_FB3_Pos)
    -
    3153#define CAN_F4R1_FB3 CAN_F4R1_FB3_Msk
    -
    3154#define CAN_F4R1_FB4_Pos (4U)
    -
    3155#define CAN_F4R1_FB4_Msk (0x1UL << CAN_F4R1_FB4_Pos)
    -
    3156#define CAN_F4R1_FB4 CAN_F4R1_FB4_Msk
    -
    3157#define CAN_F4R1_FB5_Pos (5U)
    -
    3158#define CAN_F4R1_FB5_Msk (0x1UL << CAN_F4R1_FB5_Pos)
    -
    3159#define CAN_F4R1_FB5 CAN_F4R1_FB5_Msk
    -
    3160#define CAN_F4R1_FB6_Pos (6U)
    -
    3161#define CAN_F4R1_FB6_Msk (0x1UL << CAN_F4R1_FB6_Pos)
    -
    3162#define CAN_F4R1_FB6 CAN_F4R1_FB6_Msk
    -
    3163#define CAN_F4R1_FB7_Pos (7U)
    -
    3164#define CAN_F4R1_FB7_Msk (0x1UL << CAN_F4R1_FB7_Pos)
    -
    3165#define CAN_F4R1_FB7 CAN_F4R1_FB7_Msk
    -
    3166#define CAN_F4R1_FB8_Pos (8U)
    -
    3167#define CAN_F4R1_FB8_Msk (0x1UL << CAN_F4R1_FB8_Pos)
    -
    3168#define CAN_F4R1_FB8 CAN_F4R1_FB8_Msk
    -
    3169#define CAN_F4R1_FB9_Pos (9U)
    -
    3170#define CAN_F4R1_FB9_Msk (0x1UL << CAN_F4R1_FB9_Pos)
    -
    3171#define CAN_F4R1_FB9 CAN_F4R1_FB9_Msk
    -
    3172#define CAN_F4R1_FB10_Pos (10U)
    -
    3173#define CAN_F4R1_FB10_Msk (0x1UL << CAN_F4R1_FB10_Pos)
    -
    3174#define CAN_F4R1_FB10 CAN_F4R1_FB10_Msk
    -
    3175#define CAN_F4R1_FB11_Pos (11U)
    -
    3176#define CAN_F4R1_FB11_Msk (0x1UL << CAN_F4R1_FB11_Pos)
    -
    3177#define CAN_F4R1_FB11 CAN_F4R1_FB11_Msk
    -
    3178#define CAN_F4R1_FB12_Pos (12U)
    -
    3179#define CAN_F4R1_FB12_Msk (0x1UL << CAN_F4R1_FB12_Pos)
    -
    3180#define CAN_F4R1_FB12 CAN_F4R1_FB12_Msk
    -
    3181#define CAN_F4R1_FB13_Pos (13U)
    -
    3182#define CAN_F4R1_FB13_Msk (0x1UL << CAN_F4R1_FB13_Pos)
    -
    3183#define CAN_F4R1_FB13 CAN_F4R1_FB13_Msk
    -
    3184#define CAN_F4R1_FB14_Pos (14U)
    -
    3185#define CAN_F4R1_FB14_Msk (0x1UL << CAN_F4R1_FB14_Pos)
    -
    3186#define CAN_F4R1_FB14 CAN_F4R1_FB14_Msk
    -
    3187#define CAN_F4R1_FB15_Pos (15U)
    -
    3188#define CAN_F4R1_FB15_Msk (0x1UL << CAN_F4R1_FB15_Pos)
    -
    3189#define CAN_F4R1_FB15 CAN_F4R1_FB15_Msk
    -
    3190#define CAN_F4R1_FB16_Pos (16U)
    -
    3191#define CAN_F4R1_FB16_Msk (0x1UL << CAN_F4R1_FB16_Pos)
    -
    3192#define CAN_F4R1_FB16 CAN_F4R1_FB16_Msk
    -
    3193#define CAN_F4R1_FB17_Pos (17U)
    -
    3194#define CAN_F4R1_FB17_Msk (0x1UL << CAN_F4R1_FB17_Pos)
    -
    3195#define CAN_F4R1_FB17 CAN_F4R1_FB17_Msk
    -
    3196#define CAN_F4R1_FB18_Pos (18U)
    -
    3197#define CAN_F4R1_FB18_Msk (0x1UL << CAN_F4R1_FB18_Pos)
    -
    3198#define CAN_F4R1_FB18 CAN_F4R1_FB18_Msk
    -
    3199#define CAN_F4R1_FB19_Pos (19U)
    -
    3200#define CAN_F4R1_FB19_Msk (0x1UL << CAN_F4R1_FB19_Pos)
    -
    3201#define CAN_F4R1_FB19 CAN_F4R1_FB19_Msk
    -
    3202#define CAN_F4R1_FB20_Pos (20U)
    -
    3203#define CAN_F4R1_FB20_Msk (0x1UL << CAN_F4R1_FB20_Pos)
    -
    3204#define CAN_F4R1_FB20 CAN_F4R1_FB20_Msk
    -
    3205#define CAN_F4R1_FB21_Pos (21U)
    -
    3206#define CAN_F4R1_FB21_Msk (0x1UL << CAN_F4R1_FB21_Pos)
    -
    3207#define CAN_F4R1_FB21 CAN_F4R1_FB21_Msk
    -
    3208#define CAN_F4R1_FB22_Pos (22U)
    -
    3209#define CAN_F4R1_FB22_Msk (0x1UL << CAN_F4R1_FB22_Pos)
    -
    3210#define CAN_F4R1_FB22 CAN_F4R1_FB22_Msk
    -
    3211#define CAN_F4R1_FB23_Pos (23U)
    -
    3212#define CAN_F4R1_FB23_Msk (0x1UL << CAN_F4R1_FB23_Pos)
    -
    3213#define CAN_F4R1_FB23 CAN_F4R1_FB23_Msk
    -
    3214#define CAN_F4R1_FB24_Pos (24U)
    -
    3215#define CAN_F4R1_FB24_Msk (0x1UL << CAN_F4R1_FB24_Pos)
    -
    3216#define CAN_F4R1_FB24 CAN_F4R1_FB24_Msk
    -
    3217#define CAN_F4R1_FB25_Pos (25U)
    -
    3218#define CAN_F4R1_FB25_Msk (0x1UL << CAN_F4R1_FB25_Pos)
    -
    3219#define CAN_F4R1_FB25 CAN_F4R1_FB25_Msk
    -
    3220#define CAN_F4R1_FB26_Pos (26U)
    -
    3221#define CAN_F4R1_FB26_Msk (0x1UL << CAN_F4R1_FB26_Pos)
    -
    3222#define CAN_F4R1_FB26 CAN_F4R1_FB26_Msk
    -
    3223#define CAN_F4R1_FB27_Pos (27U)
    -
    3224#define CAN_F4R1_FB27_Msk (0x1UL << CAN_F4R1_FB27_Pos)
    -
    3225#define CAN_F4R1_FB27 CAN_F4R1_FB27_Msk
    -
    3226#define CAN_F4R1_FB28_Pos (28U)
    -
    3227#define CAN_F4R1_FB28_Msk (0x1UL << CAN_F4R1_FB28_Pos)
    -
    3228#define CAN_F4R1_FB28 CAN_F4R1_FB28_Msk
    -
    3229#define CAN_F4R1_FB29_Pos (29U)
    -
    3230#define CAN_F4R1_FB29_Msk (0x1UL << CAN_F4R1_FB29_Pos)
    -
    3231#define CAN_F4R1_FB29 CAN_F4R1_FB29_Msk
    -
    3232#define CAN_F4R1_FB30_Pos (30U)
    -
    3233#define CAN_F4R1_FB30_Msk (0x1UL << CAN_F4R1_FB30_Pos)
    -
    3234#define CAN_F4R1_FB30 CAN_F4R1_FB30_Msk
    -
    3235#define CAN_F4R1_FB31_Pos (31U)
    -
    3236#define CAN_F4R1_FB31_Msk (0x1UL << CAN_F4R1_FB31_Pos)
    -
    3237#define CAN_F4R1_FB31 CAN_F4R1_FB31_Msk
    -
    3239/******************* Bit definition for CAN_F5R1 register *******************/
    -
    3240#define CAN_F5R1_FB0_Pos (0U)
    -
    3241#define CAN_F5R1_FB0_Msk (0x1UL << CAN_F5R1_FB0_Pos)
    -
    3242#define CAN_F5R1_FB0 CAN_F5R1_FB0_Msk
    -
    3243#define CAN_F5R1_FB1_Pos (1U)
    -
    3244#define CAN_F5R1_FB1_Msk (0x1UL << CAN_F5R1_FB1_Pos)
    -
    3245#define CAN_F5R1_FB1 CAN_F5R1_FB1_Msk
    -
    3246#define CAN_F5R1_FB2_Pos (2U)
    -
    3247#define CAN_F5R1_FB2_Msk (0x1UL << CAN_F5R1_FB2_Pos)
    -
    3248#define CAN_F5R1_FB2 CAN_F5R1_FB2_Msk
    -
    3249#define CAN_F5R1_FB3_Pos (3U)
    -
    3250#define CAN_F5R1_FB3_Msk (0x1UL << CAN_F5R1_FB3_Pos)
    -
    3251#define CAN_F5R1_FB3 CAN_F5R1_FB3_Msk
    -
    3252#define CAN_F5R1_FB4_Pos (4U)
    -
    3253#define CAN_F5R1_FB4_Msk (0x1UL << CAN_F5R1_FB4_Pos)
    -
    3254#define CAN_F5R1_FB4 CAN_F5R1_FB4_Msk
    -
    3255#define CAN_F5R1_FB5_Pos (5U)
    -
    3256#define CAN_F5R1_FB5_Msk (0x1UL << CAN_F5R1_FB5_Pos)
    -
    3257#define CAN_F5R1_FB5 CAN_F5R1_FB5_Msk
    -
    3258#define CAN_F5R1_FB6_Pos (6U)
    -
    3259#define CAN_F5R1_FB6_Msk (0x1UL << CAN_F5R1_FB6_Pos)
    -
    3260#define CAN_F5R1_FB6 CAN_F5R1_FB6_Msk
    -
    3261#define CAN_F5R1_FB7_Pos (7U)
    -
    3262#define CAN_F5R1_FB7_Msk (0x1UL << CAN_F5R1_FB7_Pos)
    -
    3263#define CAN_F5R1_FB7 CAN_F5R1_FB7_Msk
    -
    3264#define CAN_F5R1_FB8_Pos (8U)
    -
    3265#define CAN_F5R1_FB8_Msk (0x1UL << CAN_F5R1_FB8_Pos)
    -
    3266#define CAN_F5R1_FB8 CAN_F5R1_FB8_Msk
    -
    3267#define CAN_F5R1_FB9_Pos (9U)
    -
    3268#define CAN_F5R1_FB9_Msk (0x1UL << CAN_F5R1_FB9_Pos)
    -
    3269#define CAN_F5R1_FB9 CAN_F5R1_FB9_Msk
    -
    3270#define CAN_F5R1_FB10_Pos (10U)
    -
    3271#define CAN_F5R1_FB10_Msk (0x1UL << CAN_F5R1_FB10_Pos)
    -
    3272#define CAN_F5R1_FB10 CAN_F5R1_FB10_Msk
    -
    3273#define CAN_F5R1_FB11_Pos (11U)
    -
    3274#define CAN_F5R1_FB11_Msk (0x1UL << CAN_F5R1_FB11_Pos)
    -
    3275#define CAN_F5R1_FB11 CAN_F5R1_FB11_Msk
    -
    3276#define CAN_F5R1_FB12_Pos (12U)
    -
    3277#define CAN_F5R1_FB12_Msk (0x1UL << CAN_F5R1_FB12_Pos)
    -
    3278#define CAN_F5R1_FB12 CAN_F5R1_FB12_Msk
    -
    3279#define CAN_F5R1_FB13_Pos (13U)
    -
    3280#define CAN_F5R1_FB13_Msk (0x1UL << CAN_F5R1_FB13_Pos)
    -
    3281#define CAN_F5R1_FB13 CAN_F5R1_FB13_Msk
    -
    3282#define CAN_F5R1_FB14_Pos (14U)
    -
    3283#define CAN_F5R1_FB14_Msk (0x1UL << CAN_F5R1_FB14_Pos)
    -
    3284#define CAN_F5R1_FB14 CAN_F5R1_FB14_Msk
    -
    3285#define CAN_F5R1_FB15_Pos (15U)
    -
    3286#define CAN_F5R1_FB15_Msk (0x1UL << CAN_F5R1_FB15_Pos)
    -
    3287#define CAN_F5R1_FB15 CAN_F5R1_FB15_Msk
    -
    3288#define CAN_F5R1_FB16_Pos (16U)
    -
    3289#define CAN_F5R1_FB16_Msk (0x1UL << CAN_F5R1_FB16_Pos)
    -
    3290#define CAN_F5R1_FB16 CAN_F5R1_FB16_Msk
    -
    3291#define CAN_F5R1_FB17_Pos (17U)
    -
    3292#define CAN_F5R1_FB17_Msk (0x1UL << CAN_F5R1_FB17_Pos)
    -
    3293#define CAN_F5R1_FB17 CAN_F5R1_FB17_Msk
    -
    3294#define CAN_F5R1_FB18_Pos (18U)
    -
    3295#define CAN_F5R1_FB18_Msk (0x1UL << CAN_F5R1_FB18_Pos)
    -
    3296#define CAN_F5R1_FB18 CAN_F5R1_FB18_Msk
    -
    3297#define CAN_F5R1_FB19_Pos (19U)
    -
    3298#define CAN_F5R1_FB19_Msk (0x1UL << CAN_F5R1_FB19_Pos)
    -
    3299#define CAN_F5R1_FB19 CAN_F5R1_FB19_Msk
    -
    3300#define CAN_F5R1_FB20_Pos (20U)
    -
    3301#define CAN_F5R1_FB20_Msk (0x1UL << CAN_F5R1_FB20_Pos)
    -
    3302#define CAN_F5R1_FB20 CAN_F5R1_FB20_Msk
    -
    3303#define CAN_F5R1_FB21_Pos (21U)
    -
    3304#define CAN_F5R1_FB21_Msk (0x1UL << CAN_F5R1_FB21_Pos)
    -
    3305#define CAN_F5R1_FB21 CAN_F5R1_FB21_Msk
    -
    3306#define CAN_F5R1_FB22_Pos (22U)
    -
    3307#define CAN_F5R1_FB22_Msk (0x1UL << CAN_F5R1_FB22_Pos)
    -
    3308#define CAN_F5R1_FB22 CAN_F5R1_FB22_Msk
    -
    3309#define CAN_F5R1_FB23_Pos (23U)
    -
    3310#define CAN_F5R1_FB23_Msk (0x1UL << CAN_F5R1_FB23_Pos)
    -
    3311#define CAN_F5R1_FB23 CAN_F5R1_FB23_Msk
    -
    3312#define CAN_F5R1_FB24_Pos (24U)
    -
    3313#define CAN_F5R1_FB24_Msk (0x1UL << CAN_F5R1_FB24_Pos)
    -
    3314#define CAN_F5R1_FB24 CAN_F5R1_FB24_Msk
    -
    3315#define CAN_F5R1_FB25_Pos (25U)
    -
    3316#define CAN_F5R1_FB25_Msk (0x1UL << CAN_F5R1_FB25_Pos)
    -
    3317#define CAN_F5R1_FB25 CAN_F5R1_FB25_Msk
    -
    3318#define CAN_F5R1_FB26_Pos (26U)
    -
    3319#define CAN_F5R1_FB26_Msk (0x1UL << CAN_F5R1_FB26_Pos)
    -
    3320#define CAN_F5R1_FB26 CAN_F5R1_FB26_Msk
    -
    3321#define CAN_F5R1_FB27_Pos (27U)
    -
    3322#define CAN_F5R1_FB27_Msk (0x1UL << CAN_F5R1_FB27_Pos)
    -
    3323#define CAN_F5R1_FB27 CAN_F5R1_FB27_Msk
    -
    3324#define CAN_F5R1_FB28_Pos (28U)
    -
    3325#define CAN_F5R1_FB28_Msk (0x1UL << CAN_F5R1_FB28_Pos)
    -
    3326#define CAN_F5R1_FB28 CAN_F5R1_FB28_Msk
    -
    3327#define CAN_F5R1_FB29_Pos (29U)
    -
    3328#define CAN_F5R1_FB29_Msk (0x1UL << CAN_F5R1_FB29_Pos)
    -
    3329#define CAN_F5R1_FB29 CAN_F5R1_FB29_Msk
    -
    3330#define CAN_F5R1_FB30_Pos (30U)
    -
    3331#define CAN_F5R1_FB30_Msk (0x1UL << CAN_F5R1_FB30_Pos)
    -
    3332#define CAN_F5R1_FB30 CAN_F5R1_FB30_Msk
    -
    3333#define CAN_F5R1_FB31_Pos (31U)
    -
    3334#define CAN_F5R1_FB31_Msk (0x1UL << CAN_F5R1_FB31_Pos)
    -
    3335#define CAN_F5R1_FB31 CAN_F5R1_FB31_Msk
    -
    3337/******************* Bit definition for CAN_F6R1 register *******************/
    -
    3338#define CAN_F6R1_FB0_Pos (0U)
    -
    3339#define CAN_F6R1_FB0_Msk (0x1UL << CAN_F6R1_FB0_Pos)
    -
    3340#define CAN_F6R1_FB0 CAN_F6R1_FB0_Msk
    -
    3341#define CAN_F6R1_FB1_Pos (1U)
    -
    3342#define CAN_F6R1_FB1_Msk (0x1UL << CAN_F6R1_FB1_Pos)
    -
    3343#define CAN_F6R1_FB1 CAN_F6R1_FB1_Msk
    -
    3344#define CAN_F6R1_FB2_Pos (2U)
    -
    3345#define CAN_F6R1_FB2_Msk (0x1UL << CAN_F6R1_FB2_Pos)
    -
    3346#define CAN_F6R1_FB2 CAN_F6R1_FB2_Msk
    -
    3347#define CAN_F6R1_FB3_Pos (3U)
    -
    3348#define CAN_F6R1_FB3_Msk (0x1UL << CAN_F6R1_FB3_Pos)
    -
    3349#define CAN_F6R1_FB3 CAN_F6R1_FB3_Msk
    -
    3350#define CAN_F6R1_FB4_Pos (4U)
    -
    3351#define CAN_F6R1_FB4_Msk (0x1UL << CAN_F6R1_FB4_Pos)
    -
    3352#define CAN_F6R1_FB4 CAN_F6R1_FB4_Msk
    -
    3353#define CAN_F6R1_FB5_Pos (5U)
    -
    3354#define CAN_F6R1_FB5_Msk (0x1UL << CAN_F6R1_FB5_Pos)
    -
    3355#define CAN_F6R1_FB5 CAN_F6R1_FB5_Msk
    -
    3356#define CAN_F6R1_FB6_Pos (6U)
    -
    3357#define CAN_F6R1_FB6_Msk (0x1UL << CAN_F6R1_FB6_Pos)
    -
    3358#define CAN_F6R1_FB6 CAN_F6R1_FB6_Msk
    -
    3359#define CAN_F6R1_FB7_Pos (7U)
    -
    3360#define CAN_F6R1_FB7_Msk (0x1UL << CAN_F6R1_FB7_Pos)
    -
    3361#define CAN_F6R1_FB7 CAN_F6R1_FB7_Msk
    -
    3362#define CAN_F6R1_FB8_Pos (8U)
    -
    3363#define CAN_F6R1_FB8_Msk (0x1UL << CAN_F6R1_FB8_Pos)
    -
    3364#define CAN_F6R1_FB8 CAN_F6R1_FB8_Msk
    -
    3365#define CAN_F6R1_FB9_Pos (9U)
    -
    3366#define CAN_F6R1_FB9_Msk (0x1UL << CAN_F6R1_FB9_Pos)
    -
    3367#define CAN_F6R1_FB9 CAN_F6R1_FB9_Msk
    -
    3368#define CAN_F6R1_FB10_Pos (10U)
    -
    3369#define CAN_F6R1_FB10_Msk (0x1UL << CAN_F6R1_FB10_Pos)
    -
    3370#define CAN_F6R1_FB10 CAN_F6R1_FB10_Msk
    -
    3371#define CAN_F6R1_FB11_Pos (11U)
    -
    3372#define CAN_F6R1_FB11_Msk (0x1UL << CAN_F6R1_FB11_Pos)
    -
    3373#define CAN_F6R1_FB11 CAN_F6R1_FB11_Msk
    -
    3374#define CAN_F6R1_FB12_Pos (12U)
    -
    3375#define CAN_F6R1_FB12_Msk (0x1UL << CAN_F6R1_FB12_Pos)
    -
    3376#define CAN_F6R1_FB12 CAN_F6R1_FB12_Msk
    -
    3377#define CAN_F6R1_FB13_Pos (13U)
    -
    3378#define CAN_F6R1_FB13_Msk (0x1UL << CAN_F6R1_FB13_Pos)
    -
    3379#define CAN_F6R1_FB13 CAN_F6R1_FB13_Msk
    -
    3380#define CAN_F6R1_FB14_Pos (14U)
    -
    3381#define CAN_F6R1_FB14_Msk (0x1UL << CAN_F6R1_FB14_Pos)
    -
    3382#define CAN_F6R1_FB14 CAN_F6R1_FB14_Msk
    -
    3383#define CAN_F6R1_FB15_Pos (15U)
    -
    3384#define CAN_F6R1_FB15_Msk (0x1UL << CAN_F6R1_FB15_Pos)
    -
    3385#define CAN_F6R1_FB15 CAN_F6R1_FB15_Msk
    -
    3386#define CAN_F6R1_FB16_Pos (16U)
    -
    3387#define CAN_F6R1_FB16_Msk (0x1UL << CAN_F6R1_FB16_Pos)
    -
    3388#define CAN_F6R1_FB16 CAN_F6R1_FB16_Msk
    -
    3389#define CAN_F6R1_FB17_Pos (17U)
    -
    3390#define CAN_F6R1_FB17_Msk (0x1UL << CAN_F6R1_FB17_Pos)
    -
    3391#define CAN_F6R1_FB17 CAN_F6R1_FB17_Msk
    -
    3392#define CAN_F6R1_FB18_Pos (18U)
    -
    3393#define CAN_F6R1_FB18_Msk (0x1UL << CAN_F6R1_FB18_Pos)
    -
    3394#define CAN_F6R1_FB18 CAN_F6R1_FB18_Msk
    -
    3395#define CAN_F6R1_FB19_Pos (19U)
    -
    3396#define CAN_F6R1_FB19_Msk (0x1UL << CAN_F6R1_FB19_Pos)
    -
    3397#define CAN_F6R1_FB19 CAN_F6R1_FB19_Msk
    -
    3398#define CAN_F6R1_FB20_Pos (20U)
    -
    3399#define CAN_F6R1_FB20_Msk (0x1UL << CAN_F6R1_FB20_Pos)
    -
    3400#define CAN_F6R1_FB20 CAN_F6R1_FB20_Msk
    -
    3401#define CAN_F6R1_FB21_Pos (21U)
    -
    3402#define CAN_F6R1_FB21_Msk (0x1UL << CAN_F6R1_FB21_Pos)
    -
    3403#define CAN_F6R1_FB21 CAN_F6R1_FB21_Msk
    -
    3404#define CAN_F6R1_FB22_Pos (22U)
    -
    3405#define CAN_F6R1_FB22_Msk (0x1UL << CAN_F6R1_FB22_Pos)
    -
    3406#define CAN_F6R1_FB22 CAN_F6R1_FB22_Msk
    -
    3407#define CAN_F6R1_FB23_Pos (23U)
    -
    3408#define CAN_F6R1_FB23_Msk (0x1UL << CAN_F6R1_FB23_Pos)
    -
    3409#define CAN_F6R1_FB23 CAN_F6R1_FB23_Msk
    -
    3410#define CAN_F6R1_FB24_Pos (24U)
    -
    3411#define CAN_F6R1_FB24_Msk (0x1UL << CAN_F6R1_FB24_Pos)
    -
    3412#define CAN_F6R1_FB24 CAN_F6R1_FB24_Msk
    -
    3413#define CAN_F6R1_FB25_Pos (25U)
    -
    3414#define CAN_F6R1_FB25_Msk (0x1UL << CAN_F6R1_FB25_Pos)
    -
    3415#define CAN_F6R1_FB25 CAN_F6R1_FB25_Msk
    -
    3416#define CAN_F6R1_FB26_Pos (26U)
    -
    3417#define CAN_F6R1_FB26_Msk (0x1UL << CAN_F6R1_FB26_Pos)
    -
    3418#define CAN_F6R1_FB26 CAN_F6R1_FB26_Msk
    -
    3419#define CAN_F6R1_FB27_Pos (27U)
    -
    3420#define CAN_F6R1_FB27_Msk (0x1UL << CAN_F6R1_FB27_Pos)
    -
    3421#define CAN_F6R1_FB27 CAN_F6R1_FB27_Msk
    -
    3422#define CAN_F6R1_FB28_Pos (28U)
    -
    3423#define CAN_F6R1_FB28_Msk (0x1UL << CAN_F6R1_FB28_Pos)
    -
    3424#define CAN_F6R1_FB28 CAN_F6R1_FB28_Msk
    -
    3425#define CAN_F6R1_FB29_Pos (29U)
    -
    3426#define CAN_F6R1_FB29_Msk (0x1UL << CAN_F6R1_FB29_Pos)
    -
    3427#define CAN_F6R1_FB29 CAN_F6R1_FB29_Msk
    -
    3428#define CAN_F6R1_FB30_Pos (30U)
    -
    3429#define CAN_F6R1_FB30_Msk (0x1UL << CAN_F6R1_FB30_Pos)
    -
    3430#define CAN_F6R1_FB30 CAN_F6R1_FB30_Msk
    -
    3431#define CAN_F6R1_FB31_Pos (31U)
    -
    3432#define CAN_F6R1_FB31_Msk (0x1UL << CAN_F6R1_FB31_Pos)
    -
    3433#define CAN_F6R1_FB31 CAN_F6R1_FB31_Msk
    -
    3435/******************* Bit definition for CAN_F7R1 register *******************/
    -
    3436#define CAN_F7R1_FB0_Pos (0U)
    -
    3437#define CAN_F7R1_FB0_Msk (0x1UL << CAN_F7R1_FB0_Pos)
    -
    3438#define CAN_F7R1_FB0 CAN_F7R1_FB0_Msk
    -
    3439#define CAN_F7R1_FB1_Pos (1U)
    -
    3440#define CAN_F7R1_FB1_Msk (0x1UL << CAN_F7R1_FB1_Pos)
    -
    3441#define CAN_F7R1_FB1 CAN_F7R1_FB1_Msk
    -
    3442#define CAN_F7R1_FB2_Pos (2U)
    -
    3443#define CAN_F7R1_FB2_Msk (0x1UL << CAN_F7R1_FB2_Pos)
    -
    3444#define CAN_F7R1_FB2 CAN_F7R1_FB2_Msk
    -
    3445#define CAN_F7R1_FB3_Pos (3U)
    -
    3446#define CAN_F7R1_FB3_Msk (0x1UL << CAN_F7R1_FB3_Pos)
    -
    3447#define CAN_F7R1_FB3 CAN_F7R1_FB3_Msk
    -
    3448#define CAN_F7R1_FB4_Pos (4U)
    -
    3449#define CAN_F7R1_FB4_Msk (0x1UL << CAN_F7R1_FB4_Pos)
    -
    3450#define CAN_F7R1_FB4 CAN_F7R1_FB4_Msk
    -
    3451#define CAN_F7R1_FB5_Pos (5U)
    -
    3452#define CAN_F7R1_FB5_Msk (0x1UL << CAN_F7R1_FB5_Pos)
    -
    3453#define CAN_F7R1_FB5 CAN_F7R1_FB5_Msk
    -
    3454#define CAN_F7R1_FB6_Pos (6U)
    -
    3455#define CAN_F7R1_FB6_Msk (0x1UL << CAN_F7R1_FB6_Pos)
    -
    3456#define CAN_F7R1_FB6 CAN_F7R1_FB6_Msk
    -
    3457#define CAN_F7R1_FB7_Pos (7U)
    -
    3458#define CAN_F7R1_FB7_Msk (0x1UL << CAN_F7R1_FB7_Pos)
    -
    3459#define CAN_F7R1_FB7 CAN_F7R1_FB7_Msk
    -
    3460#define CAN_F7R1_FB8_Pos (8U)
    -
    3461#define CAN_F7R1_FB8_Msk (0x1UL << CAN_F7R1_FB8_Pos)
    -
    3462#define CAN_F7R1_FB8 CAN_F7R1_FB8_Msk
    -
    3463#define CAN_F7R1_FB9_Pos (9U)
    -
    3464#define CAN_F7R1_FB9_Msk (0x1UL << CAN_F7R1_FB9_Pos)
    -
    3465#define CAN_F7R1_FB9 CAN_F7R1_FB9_Msk
    -
    3466#define CAN_F7R1_FB10_Pos (10U)
    -
    3467#define CAN_F7R1_FB10_Msk (0x1UL << CAN_F7R1_FB10_Pos)
    -
    3468#define CAN_F7R1_FB10 CAN_F7R1_FB10_Msk
    -
    3469#define CAN_F7R1_FB11_Pos (11U)
    -
    3470#define CAN_F7R1_FB11_Msk (0x1UL << CAN_F7R1_FB11_Pos)
    -
    3471#define CAN_F7R1_FB11 CAN_F7R1_FB11_Msk
    -
    3472#define CAN_F7R1_FB12_Pos (12U)
    -
    3473#define CAN_F7R1_FB12_Msk (0x1UL << CAN_F7R1_FB12_Pos)
    -
    3474#define CAN_F7R1_FB12 CAN_F7R1_FB12_Msk
    -
    3475#define CAN_F7R1_FB13_Pos (13U)
    -
    3476#define CAN_F7R1_FB13_Msk (0x1UL << CAN_F7R1_FB13_Pos)
    -
    3477#define CAN_F7R1_FB13 CAN_F7R1_FB13_Msk
    -
    3478#define CAN_F7R1_FB14_Pos (14U)
    -
    3479#define CAN_F7R1_FB14_Msk (0x1UL << CAN_F7R1_FB14_Pos)
    -
    3480#define CAN_F7R1_FB14 CAN_F7R1_FB14_Msk
    -
    3481#define CAN_F7R1_FB15_Pos (15U)
    -
    3482#define CAN_F7R1_FB15_Msk (0x1UL << CAN_F7R1_FB15_Pos)
    -
    3483#define CAN_F7R1_FB15 CAN_F7R1_FB15_Msk
    -
    3484#define CAN_F7R1_FB16_Pos (16U)
    -
    3485#define CAN_F7R1_FB16_Msk (0x1UL << CAN_F7R1_FB16_Pos)
    -
    3486#define CAN_F7R1_FB16 CAN_F7R1_FB16_Msk
    -
    3487#define CAN_F7R1_FB17_Pos (17U)
    -
    3488#define CAN_F7R1_FB17_Msk (0x1UL << CAN_F7R1_FB17_Pos)
    -
    3489#define CAN_F7R1_FB17 CAN_F7R1_FB17_Msk
    -
    3490#define CAN_F7R1_FB18_Pos (18U)
    -
    3491#define CAN_F7R1_FB18_Msk (0x1UL << CAN_F7R1_FB18_Pos)
    -
    3492#define CAN_F7R1_FB18 CAN_F7R1_FB18_Msk
    -
    3493#define CAN_F7R1_FB19_Pos (19U)
    -
    3494#define CAN_F7R1_FB19_Msk (0x1UL << CAN_F7R1_FB19_Pos)
    -
    3495#define CAN_F7R1_FB19 CAN_F7R1_FB19_Msk
    -
    3496#define CAN_F7R1_FB20_Pos (20U)
    -
    3497#define CAN_F7R1_FB20_Msk (0x1UL << CAN_F7R1_FB20_Pos)
    -
    3498#define CAN_F7R1_FB20 CAN_F7R1_FB20_Msk
    -
    3499#define CAN_F7R1_FB21_Pos (21U)
    -
    3500#define CAN_F7R1_FB21_Msk (0x1UL << CAN_F7R1_FB21_Pos)
    -
    3501#define CAN_F7R1_FB21 CAN_F7R1_FB21_Msk
    -
    3502#define CAN_F7R1_FB22_Pos (22U)
    -
    3503#define CAN_F7R1_FB22_Msk (0x1UL << CAN_F7R1_FB22_Pos)
    -
    3504#define CAN_F7R1_FB22 CAN_F7R1_FB22_Msk
    -
    3505#define CAN_F7R1_FB23_Pos (23U)
    -
    3506#define CAN_F7R1_FB23_Msk (0x1UL << CAN_F7R1_FB23_Pos)
    -
    3507#define CAN_F7R1_FB23 CAN_F7R1_FB23_Msk
    -
    3508#define CAN_F7R1_FB24_Pos (24U)
    -
    3509#define CAN_F7R1_FB24_Msk (0x1UL << CAN_F7R1_FB24_Pos)
    -
    3510#define CAN_F7R1_FB24 CAN_F7R1_FB24_Msk
    -
    3511#define CAN_F7R1_FB25_Pos (25U)
    -
    3512#define CAN_F7R1_FB25_Msk (0x1UL << CAN_F7R1_FB25_Pos)
    -
    3513#define CAN_F7R1_FB25 CAN_F7R1_FB25_Msk
    -
    3514#define CAN_F7R1_FB26_Pos (26U)
    -
    3515#define CAN_F7R1_FB26_Msk (0x1UL << CAN_F7R1_FB26_Pos)
    -
    3516#define CAN_F7R1_FB26 CAN_F7R1_FB26_Msk
    -
    3517#define CAN_F7R1_FB27_Pos (27U)
    -
    3518#define CAN_F7R1_FB27_Msk (0x1UL << CAN_F7R1_FB27_Pos)
    -
    3519#define CAN_F7R1_FB27 CAN_F7R1_FB27_Msk
    -
    3520#define CAN_F7R1_FB28_Pos (28U)
    -
    3521#define CAN_F7R1_FB28_Msk (0x1UL << CAN_F7R1_FB28_Pos)
    -
    3522#define CAN_F7R1_FB28 CAN_F7R1_FB28_Msk
    -
    3523#define CAN_F7R1_FB29_Pos (29U)
    -
    3524#define CAN_F7R1_FB29_Msk (0x1UL << CAN_F7R1_FB29_Pos)
    -
    3525#define CAN_F7R1_FB29 CAN_F7R1_FB29_Msk
    -
    3526#define CAN_F7R1_FB30_Pos (30U)
    -
    3527#define CAN_F7R1_FB30_Msk (0x1UL << CAN_F7R1_FB30_Pos)
    -
    3528#define CAN_F7R1_FB30 CAN_F7R1_FB30_Msk
    -
    3529#define CAN_F7R1_FB31_Pos (31U)
    -
    3530#define CAN_F7R1_FB31_Msk (0x1UL << CAN_F7R1_FB31_Pos)
    -
    3531#define CAN_F7R1_FB31 CAN_F7R1_FB31_Msk
    -
    3533/******************* Bit definition for CAN_F8R1 register *******************/
    -
    3534#define CAN_F8R1_FB0_Pos (0U)
    -
    3535#define CAN_F8R1_FB0_Msk (0x1UL << CAN_F8R1_FB0_Pos)
    -
    3536#define CAN_F8R1_FB0 CAN_F8R1_FB0_Msk
    -
    3537#define CAN_F8R1_FB1_Pos (1U)
    -
    3538#define CAN_F8R1_FB1_Msk (0x1UL << CAN_F8R1_FB1_Pos)
    -
    3539#define CAN_F8R1_FB1 CAN_F8R1_FB1_Msk
    -
    3540#define CAN_F8R1_FB2_Pos (2U)
    -
    3541#define CAN_F8R1_FB2_Msk (0x1UL << CAN_F8R1_FB2_Pos)
    -
    3542#define CAN_F8R1_FB2 CAN_F8R1_FB2_Msk
    -
    3543#define CAN_F8R1_FB3_Pos (3U)
    -
    3544#define CAN_F8R1_FB3_Msk (0x1UL << CAN_F8R1_FB3_Pos)
    -
    3545#define CAN_F8R1_FB3 CAN_F8R1_FB3_Msk
    -
    3546#define CAN_F8R1_FB4_Pos (4U)
    -
    3547#define CAN_F8R1_FB4_Msk (0x1UL << CAN_F8R1_FB4_Pos)
    -
    3548#define CAN_F8R1_FB4 CAN_F8R1_FB4_Msk
    -
    3549#define CAN_F8R1_FB5_Pos (5U)
    -
    3550#define CAN_F8R1_FB5_Msk (0x1UL << CAN_F8R1_FB5_Pos)
    -
    3551#define CAN_F8R1_FB5 CAN_F8R1_FB5_Msk
    -
    3552#define CAN_F8R1_FB6_Pos (6U)
    -
    3553#define CAN_F8R1_FB6_Msk (0x1UL << CAN_F8R1_FB6_Pos)
    -
    3554#define CAN_F8R1_FB6 CAN_F8R1_FB6_Msk
    -
    3555#define CAN_F8R1_FB7_Pos (7U)
    -
    3556#define CAN_F8R1_FB7_Msk (0x1UL << CAN_F8R1_FB7_Pos)
    -
    3557#define CAN_F8R1_FB7 CAN_F8R1_FB7_Msk
    -
    3558#define CAN_F8R1_FB8_Pos (8U)
    -
    3559#define CAN_F8R1_FB8_Msk (0x1UL << CAN_F8R1_FB8_Pos)
    -
    3560#define CAN_F8R1_FB8 CAN_F8R1_FB8_Msk
    -
    3561#define CAN_F8R1_FB9_Pos (9U)
    -
    3562#define CAN_F8R1_FB9_Msk (0x1UL << CAN_F8R1_FB9_Pos)
    -
    3563#define CAN_F8R1_FB9 CAN_F8R1_FB9_Msk
    -
    3564#define CAN_F8R1_FB10_Pos (10U)
    -
    3565#define CAN_F8R1_FB10_Msk (0x1UL << CAN_F8R1_FB10_Pos)
    -
    3566#define CAN_F8R1_FB10 CAN_F8R1_FB10_Msk
    -
    3567#define CAN_F8R1_FB11_Pos (11U)
    -
    3568#define CAN_F8R1_FB11_Msk (0x1UL << CAN_F8R1_FB11_Pos)
    -
    3569#define CAN_F8R1_FB11 CAN_F8R1_FB11_Msk
    -
    3570#define CAN_F8R1_FB12_Pos (12U)
    -
    3571#define CAN_F8R1_FB12_Msk (0x1UL << CAN_F8R1_FB12_Pos)
    -
    3572#define CAN_F8R1_FB12 CAN_F8R1_FB12_Msk
    -
    3573#define CAN_F8R1_FB13_Pos (13U)
    -
    3574#define CAN_F8R1_FB13_Msk (0x1UL << CAN_F8R1_FB13_Pos)
    -
    3575#define CAN_F8R1_FB13 CAN_F8R1_FB13_Msk
    -
    3576#define CAN_F8R1_FB14_Pos (14U)
    -
    3577#define CAN_F8R1_FB14_Msk (0x1UL << CAN_F8R1_FB14_Pos)
    -
    3578#define CAN_F8R1_FB14 CAN_F8R1_FB14_Msk
    -
    3579#define CAN_F8R1_FB15_Pos (15U)
    -
    3580#define CAN_F8R1_FB15_Msk (0x1UL << CAN_F8R1_FB15_Pos)
    -
    3581#define CAN_F8R1_FB15 CAN_F8R1_FB15_Msk
    -
    3582#define CAN_F8R1_FB16_Pos (16U)
    -
    3583#define CAN_F8R1_FB16_Msk (0x1UL << CAN_F8R1_FB16_Pos)
    -
    3584#define CAN_F8R1_FB16 CAN_F8R1_FB16_Msk
    -
    3585#define CAN_F8R1_FB17_Pos (17U)
    -
    3586#define CAN_F8R1_FB17_Msk (0x1UL << CAN_F8R1_FB17_Pos)
    -
    3587#define CAN_F8R1_FB17 CAN_F8R1_FB17_Msk
    -
    3588#define CAN_F8R1_FB18_Pos (18U)
    -
    3589#define CAN_F8R1_FB18_Msk (0x1UL << CAN_F8R1_FB18_Pos)
    -
    3590#define CAN_F8R1_FB18 CAN_F8R1_FB18_Msk
    -
    3591#define CAN_F8R1_FB19_Pos (19U)
    -
    3592#define CAN_F8R1_FB19_Msk (0x1UL << CAN_F8R1_FB19_Pos)
    -
    3593#define CAN_F8R1_FB19 CAN_F8R1_FB19_Msk
    -
    3594#define CAN_F8R1_FB20_Pos (20U)
    -
    3595#define CAN_F8R1_FB20_Msk (0x1UL << CAN_F8R1_FB20_Pos)
    -
    3596#define CAN_F8R1_FB20 CAN_F8R1_FB20_Msk
    -
    3597#define CAN_F8R1_FB21_Pos (21U)
    -
    3598#define CAN_F8R1_FB21_Msk (0x1UL << CAN_F8R1_FB21_Pos)
    -
    3599#define CAN_F8R1_FB21 CAN_F8R1_FB21_Msk
    -
    3600#define CAN_F8R1_FB22_Pos (22U)
    -
    3601#define CAN_F8R1_FB22_Msk (0x1UL << CAN_F8R1_FB22_Pos)
    -
    3602#define CAN_F8R1_FB22 CAN_F8R1_FB22_Msk
    -
    3603#define CAN_F8R1_FB23_Pos (23U)
    -
    3604#define CAN_F8R1_FB23_Msk (0x1UL << CAN_F8R1_FB23_Pos)
    -
    3605#define CAN_F8R1_FB23 CAN_F8R1_FB23_Msk
    -
    3606#define CAN_F8R1_FB24_Pos (24U)
    -
    3607#define CAN_F8R1_FB24_Msk (0x1UL << CAN_F8R1_FB24_Pos)
    -
    3608#define CAN_F8R1_FB24 CAN_F8R1_FB24_Msk
    -
    3609#define CAN_F8R1_FB25_Pos (25U)
    -
    3610#define CAN_F8R1_FB25_Msk (0x1UL << CAN_F8R1_FB25_Pos)
    -
    3611#define CAN_F8R1_FB25 CAN_F8R1_FB25_Msk
    -
    3612#define CAN_F8R1_FB26_Pos (26U)
    -
    3613#define CAN_F8R1_FB26_Msk (0x1UL << CAN_F8R1_FB26_Pos)
    -
    3614#define CAN_F8R1_FB26 CAN_F8R1_FB26_Msk
    -
    3615#define CAN_F8R1_FB27_Pos (27U)
    -
    3616#define CAN_F8R1_FB27_Msk (0x1UL << CAN_F8R1_FB27_Pos)
    -
    3617#define CAN_F8R1_FB27 CAN_F8R1_FB27_Msk
    -
    3618#define CAN_F8R1_FB28_Pos (28U)
    -
    3619#define CAN_F8R1_FB28_Msk (0x1UL << CAN_F8R1_FB28_Pos)
    -
    3620#define CAN_F8R1_FB28 CAN_F8R1_FB28_Msk
    -
    3621#define CAN_F8R1_FB29_Pos (29U)
    -
    3622#define CAN_F8R1_FB29_Msk (0x1UL << CAN_F8R1_FB29_Pos)
    -
    3623#define CAN_F8R1_FB29 CAN_F8R1_FB29_Msk
    -
    3624#define CAN_F8R1_FB30_Pos (30U)
    -
    3625#define CAN_F8R1_FB30_Msk (0x1UL << CAN_F8R1_FB30_Pos)
    -
    3626#define CAN_F8R1_FB30 CAN_F8R1_FB30_Msk
    -
    3627#define CAN_F8R1_FB31_Pos (31U)
    -
    3628#define CAN_F8R1_FB31_Msk (0x1UL << CAN_F8R1_FB31_Pos)
    -
    3629#define CAN_F8R1_FB31 CAN_F8R1_FB31_Msk
    -
    3631/******************* Bit definition for CAN_F9R1 register *******************/
    -
    3632#define CAN_F9R1_FB0_Pos (0U)
    -
    3633#define CAN_F9R1_FB0_Msk (0x1UL << CAN_F9R1_FB0_Pos)
    -
    3634#define CAN_F9R1_FB0 CAN_F9R1_FB0_Msk
    -
    3635#define CAN_F9R1_FB1_Pos (1U)
    -
    3636#define CAN_F9R1_FB1_Msk (0x1UL << CAN_F9R1_FB1_Pos)
    -
    3637#define CAN_F9R1_FB1 CAN_F9R1_FB1_Msk
    -
    3638#define CAN_F9R1_FB2_Pos (2U)
    -
    3639#define CAN_F9R1_FB2_Msk (0x1UL << CAN_F9R1_FB2_Pos)
    -
    3640#define CAN_F9R1_FB2 CAN_F9R1_FB2_Msk
    -
    3641#define CAN_F9R1_FB3_Pos (3U)
    -
    3642#define CAN_F9R1_FB3_Msk (0x1UL << CAN_F9R1_FB3_Pos)
    -
    3643#define CAN_F9R1_FB3 CAN_F9R1_FB3_Msk
    -
    3644#define CAN_F9R1_FB4_Pos (4U)
    -
    3645#define CAN_F9R1_FB4_Msk (0x1UL << CAN_F9R1_FB4_Pos)
    -
    3646#define CAN_F9R1_FB4 CAN_F9R1_FB4_Msk
    -
    3647#define CAN_F9R1_FB5_Pos (5U)
    -
    3648#define CAN_F9R1_FB5_Msk (0x1UL << CAN_F9R1_FB5_Pos)
    -
    3649#define CAN_F9R1_FB5 CAN_F9R1_FB5_Msk
    -
    3650#define CAN_F9R1_FB6_Pos (6U)
    -
    3651#define CAN_F9R1_FB6_Msk (0x1UL << CAN_F9R1_FB6_Pos)
    -
    3652#define CAN_F9R1_FB6 CAN_F9R1_FB6_Msk
    -
    3653#define CAN_F9R1_FB7_Pos (7U)
    -
    3654#define CAN_F9R1_FB7_Msk (0x1UL << CAN_F9R1_FB7_Pos)
    -
    3655#define CAN_F9R1_FB7 CAN_F9R1_FB7_Msk
    -
    3656#define CAN_F9R1_FB8_Pos (8U)
    -
    3657#define CAN_F9R1_FB8_Msk (0x1UL << CAN_F9R1_FB8_Pos)
    -
    3658#define CAN_F9R1_FB8 CAN_F9R1_FB8_Msk
    -
    3659#define CAN_F9R1_FB9_Pos (9U)
    -
    3660#define CAN_F9R1_FB9_Msk (0x1UL << CAN_F9R1_FB9_Pos)
    -
    3661#define CAN_F9R1_FB9 CAN_F9R1_FB9_Msk
    -
    3662#define CAN_F9R1_FB10_Pos (10U)
    -
    3663#define CAN_F9R1_FB10_Msk (0x1UL << CAN_F9R1_FB10_Pos)
    -
    3664#define CAN_F9R1_FB10 CAN_F9R1_FB10_Msk
    -
    3665#define CAN_F9R1_FB11_Pos (11U)
    -
    3666#define CAN_F9R1_FB11_Msk (0x1UL << CAN_F9R1_FB11_Pos)
    -
    3667#define CAN_F9R1_FB11 CAN_F9R1_FB11_Msk
    -
    3668#define CAN_F9R1_FB12_Pos (12U)
    -
    3669#define CAN_F9R1_FB12_Msk (0x1UL << CAN_F9R1_FB12_Pos)
    -
    3670#define CAN_F9R1_FB12 CAN_F9R1_FB12_Msk
    -
    3671#define CAN_F9R1_FB13_Pos (13U)
    -
    3672#define CAN_F9R1_FB13_Msk (0x1UL << CAN_F9R1_FB13_Pos)
    -
    3673#define CAN_F9R1_FB13 CAN_F9R1_FB13_Msk
    -
    3674#define CAN_F9R1_FB14_Pos (14U)
    -
    3675#define CAN_F9R1_FB14_Msk (0x1UL << CAN_F9R1_FB14_Pos)
    -
    3676#define CAN_F9R1_FB14 CAN_F9R1_FB14_Msk
    -
    3677#define CAN_F9R1_FB15_Pos (15U)
    -
    3678#define CAN_F9R1_FB15_Msk (0x1UL << CAN_F9R1_FB15_Pos)
    -
    3679#define CAN_F9R1_FB15 CAN_F9R1_FB15_Msk
    -
    3680#define CAN_F9R1_FB16_Pos (16U)
    -
    3681#define CAN_F9R1_FB16_Msk (0x1UL << CAN_F9R1_FB16_Pos)
    -
    3682#define CAN_F9R1_FB16 CAN_F9R1_FB16_Msk
    -
    3683#define CAN_F9R1_FB17_Pos (17U)
    -
    3684#define CAN_F9R1_FB17_Msk (0x1UL << CAN_F9R1_FB17_Pos)
    -
    3685#define CAN_F9R1_FB17 CAN_F9R1_FB17_Msk
    -
    3686#define CAN_F9R1_FB18_Pos (18U)
    -
    3687#define CAN_F9R1_FB18_Msk (0x1UL << CAN_F9R1_FB18_Pos)
    -
    3688#define CAN_F9R1_FB18 CAN_F9R1_FB18_Msk
    -
    3689#define CAN_F9R1_FB19_Pos (19U)
    -
    3690#define CAN_F9R1_FB19_Msk (0x1UL << CAN_F9R1_FB19_Pos)
    -
    3691#define CAN_F9R1_FB19 CAN_F9R1_FB19_Msk
    -
    3692#define CAN_F9R1_FB20_Pos (20U)
    -
    3693#define CAN_F9R1_FB20_Msk (0x1UL << CAN_F9R1_FB20_Pos)
    -
    3694#define CAN_F9R1_FB20 CAN_F9R1_FB20_Msk
    -
    3695#define CAN_F9R1_FB21_Pos (21U)
    -
    3696#define CAN_F9R1_FB21_Msk (0x1UL << CAN_F9R1_FB21_Pos)
    -
    3697#define CAN_F9R1_FB21 CAN_F9R1_FB21_Msk
    -
    3698#define CAN_F9R1_FB22_Pos (22U)
    -
    3699#define CAN_F9R1_FB22_Msk (0x1UL << CAN_F9R1_FB22_Pos)
    -
    3700#define CAN_F9R1_FB22 CAN_F9R1_FB22_Msk
    -
    3701#define CAN_F9R1_FB23_Pos (23U)
    -
    3702#define CAN_F9R1_FB23_Msk (0x1UL << CAN_F9R1_FB23_Pos)
    -
    3703#define CAN_F9R1_FB23 CAN_F9R1_FB23_Msk
    -
    3704#define CAN_F9R1_FB24_Pos (24U)
    -
    3705#define CAN_F9R1_FB24_Msk (0x1UL << CAN_F9R1_FB24_Pos)
    -
    3706#define CAN_F9R1_FB24 CAN_F9R1_FB24_Msk
    -
    3707#define CAN_F9R1_FB25_Pos (25U)
    -
    3708#define CAN_F9R1_FB25_Msk (0x1UL << CAN_F9R1_FB25_Pos)
    -
    3709#define CAN_F9R1_FB25 CAN_F9R1_FB25_Msk
    -
    3710#define CAN_F9R1_FB26_Pos (26U)
    -
    3711#define CAN_F9R1_FB26_Msk (0x1UL << CAN_F9R1_FB26_Pos)
    -
    3712#define CAN_F9R1_FB26 CAN_F9R1_FB26_Msk
    -
    3713#define CAN_F9R1_FB27_Pos (27U)
    -
    3714#define CAN_F9R1_FB27_Msk (0x1UL << CAN_F9R1_FB27_Pos)
    -
    3715#define CAN_F9R1_FB27 CAN_F9R1_FB27_Msk
    -
    3716#define CAN_F9R1_FB28_Pos (28U)
    -
    3717#define CAN_F9R1_FB28_Msk (0x1UL << CAN_F9R1_FB28_Pos)
    -
    3718#define CAN_F9R1_FB28 CAN_F9R1_FB28_Msk
    -
    3719#define CAN_F9R1_FB29_Pos (29U)
    -
    3720#define CAN_F9R1_FB29_Msk (0x1UL << CAN_F9R1_FB29_Pos)
    -
    3721#define CAN_F9R1_FB29 CAN_F9R1_FB29_Msk
    -
    3722#define CAN_F9R1_FB30_Pos (30U)
    -
    3723#define CAN_F9R1_FB30_Msk (0x1UL << CAN_F9R1_FB30_Pos)
    -
    3724#define CAN_F9R1_FB30 CAN_F9R1_FB30_Msk
    -
    3725#define CAN_F9R1_FB31_Pos (31U)
    -
    3726#define CAN_F9R1_FB31_Msk (0x1UL << CAN_F9R1_FB31_Pos)
    -
    3727#define CAN_F9R1_FB31 CAN_F9R1_FB31_Msk
    -
    3729/******************* Bit definition for CAN_F10R1 register ******************/
    -
    3730#define CAN_F10R1_FB0_Pos (0U)
    -
    3731#define CAN_F10R1_FB0_Msk (0x1UL << CAN_F10R1_FB0_Pos)
    -
    3732#define CAN_F10R1_FB0 CAN_F10R1_FB0_Msk
    -
    3733#define CAN_F10R1_FB1_Pos (1U)
    -
    3734#define CAN_F10R1_FB1_Msk (0x1UL << CAN_F10R1_FB1_Pos)
    -
    3735#define CAN_F10R1_FB1 CAN_F10R1_FB1_Msk
    -
    3736#define CAN_F10R1_FB2_Pos (2U)
    -
    3737#define CAN_F10R1_FB2_Msk (0x1UL << CAN_F10R1_FB2_Pos)
    -
    3738#define CAN_F10R1_FB2 CAN_F10R1_FB2_Msk
    -
    3739#define CAN_F10R1_FB3_Pos (3U)
    -
    3740#define CAN_F10R1_FB3_Msk (0x1UL << CAN_F10R1_FB3_Pos)
    -
    3741#define CAN_F10R1_FB3 CAN_F10R1_FB3_Msk
    -
    3742#define CAN_F10R1_FB4_Pos (4U)
    -
    3743#define CAN_F10R1_FB4_Msk (0x1UL << CAN_F10R1_FB4_Pos)
    -
    3744#define CAN_F10R1_FB4 CAN_F10R1_FB4_Msk
    -
    3745#define CAN_F10R1_FB5_Pos (5U)
    -
    3746#define CAN_F10R1_FB5_Msk (0x1UL << CAN_F10R1_FB5_Pos)
    -
    3747#define CAN_F10R1_FB5 CAN_F10R1_FB5_Msk
    -
    3748#define CAN_F10R1_FB6_Pos (6U)
    -
    3749#define CAN_F10R1_FB6_Msk (0x1UL << CAN_F10R1_FB6_Pos)
    -
    3750#define CAN_F10R1_FB6 CAN_F10R1_FB6_Msk
    -
    3751#define CAN_F10R1_FB7_Pos (7U)
    -
    3752#define CAN_F10R1_FB7_Msk (0x1UL << CAN_F10R1_FB7_Pos)
    -
    3753#define CAN_F10R1_FB7 CAN_F10R1_FB7_Msk
    -
    3754#define CAN_F10R1_FB8_Pos (8U)
    -
    3755#define CAN_F10R1_FB8_Msk (0x1UL << CAN_F10R1_FB8_Pos)
    -
    3756#define CAN_F10R1_FB8 CAN_F10R1_FB8_Msk
    -
    3757#define CAN_F10R1_FB9_Pos (9U)
    -
    3758#define CAN_F10R1_FB9_Msk (0x1UL << CAN_F10R1_FB9_Pos)
    -
    3759#define CAN_F10R1_FB9 CAN_F10R1_FB9_Msk
    -
    3760#define CAN_F10R1_FB10_Pos (10U)
    -
    3761#define CAN_F10R1_FB10_Msk (0x1UL << CAN_F10R1_FB10_Pos)
    -
    3762#define CAN_F10R1_FB10 CAN_F10R1_FB10_Msk
    -
    3763#define CAN_F10R1_FB11_Pos (11U)
    -
    3764#define CAN_F10R1_FB11_Msk (0x1UL << CAN_F10R1_FB11_Pos)
    -
    3765#define CAN_F10R1_FB11 CAN_F10R1_FB11_Msk
    -
    3766#define CAN_F10R1_FB12_Pos (12U)
    -
    3767#define CAN_F10R1_FB12_Msk (0x1UL << CAN_F10R1_FB12_Pos)
    -
    3768#define CAN_F10R1_FB12 CAN_F10R1_FB12_Msk
    -
    3769#define CAN_F10R1_FB13_Pos (13U)
    -
    3770#define CAN_F10R1_FB13_Msk (0x1UL << CAN_F10R1_FB13_Pos)
    -
    3771#define CAN_F10R1_FB13 CAN_F10R1_FB13_Msk
    -
    3772#define CAN_F10R1_FB14_Pos (14U)
    -
    3773#define CAN_F10R1_FB14_Msk (0x1UL << CAN_F10R1_FB14_Pos)
    -
    3774#define CAN_F10R1_FB14 CAN_F10R1_FB14_Msk
    -
    3775#define CAN_F10R1_FB15_Pos (15U)
    -
    3776#define CAN_F10R1_FB15_Msk (0x1UL << CAN_F10R1_FB15_Pos)
    -
    3777#define CAN_F10R1_FB15 CAN_F10R1_FB15_Msk
    -
    3778#define CAN_F10R1_FB16_Pos (16U)
    -
    3779#define CAN_F10R1_FB16_Msk (0x1UL << CAN_F10R1_FB16_Pos)
    -
    3780#define CAN_F10R1_FB16 CAN_F10R1_FB16_Msk
    -
    3781#define CAN_F10R1_FB17_Pos (17U)
    -
    3782#define CAN_F10R1_FB17_Msk (0x1UL << CAN_F10R1_FB17_Pos)
    -
    3783#define CAN_F10R1_FB17 CAN_F10R1_FB17_Msk
    -
    3784#define CAN_F10R1_FB18_Pos (18U)
    -
    3785#define CAN_F10R1_FB18_Msk (0x1UL << CAN_F10R1_FB18_Pos)
    -
    3786#define CAN_F10R1_FB18 CAN_F10R1_FB18_Msk
    -
    3787#define CAN_F10R1_FB19_Pos (19U)
    -
    3788#define CAN_F10R1_FB19_Msk (0x1UL << CAN_F10R1_FB19_Pos)
    -
    3789#define CAN_F10R1_FB19 CAN_F10R1_FB19_Msk
    -
    3790#define CAN_F10R1_FB20_Pos (20U)
    -
    3791#define CAN_F10R1_FB20_Msk (0x1UL << CAN_F10R1_FB20_Pos)
    -
    3792#define CAN_F10R1_FB20 CAN_F10R1_FB20_Msk
    -
    3793#define CAN_F10R1_FB21_Pos (21U)
    -
    3794#define CAN_F10R1_FB21_Msk (0x1UL << CAN_F10R1_FB21_Pos)
    -
    3795#define CAN_F10R1_FB21 CAN_F10R1_FB21_Msk
    -
    3796#define CAN_F10R1_FB22_Pos (22U)
    -
    3797#define CAN_F10R1_FB22_Msk (0x1UL << CAN_F10R1_FB22_Pos)
    -
    3798#define CAN_F10R1_FB22 CAN_F10R1_FB22_Msk
    -
    3799#define CAN_F10R1_FB23_Pos (23U)
    -
    3800#define CAN_F10R1_FB23_Msk (0x1UL << CAN_F10R1_FB23_Pos)
    -
    3801#define CAN_F10R1_FB23 CAN_F10R1_FB23_Msk
    -
    3802#define CAN_F10R1_FB24_Pos (24U)
    -
    3803#define CAN_F10R1_FB24_Msk (0x1UL << CAN_F10R1_FB24_Pos)
    -
    3804#define CAN_F10R1_FB24 CAN_F10R1_FB24_Msk
    -
    3805#define CAN_F10R1_FB25_Pos (25U)
    -
    3806#define CAN_F10R1_FB25_Msk (0x1UL << CAN_F10R1_FB25_Pos)
    -
    3807#define CAN_F10R1_FB25 CAN_F10R1_FB25_Msk
    -
    3808#define CAN_F10R1_FB26_Pos (26U)
    -
    3809#define CAN_F10R1_FB26_Msk (0x1UL << CAN_F10R1_FB26_Pos)
    -
    3810#define CAN_F10R1_FB26 CAN_F10R1_FB26_Msk
    -
    3811#define CAN_F10R1_FB27_Pos (27U)
    -
    3812#define CAN_F10R1_FB27_Msk (0x1UL << CAN_F10R1_FB27_Pos)
    -
    3813#define CAN_F10R1_FB27 CAN_F10R1_FB27_Msk
    -
    3814#define CAN_F10R1_FB28_Pos (28U)
    -
    3815#define CAN_F10R1_FB28_Msk (0x1UL << CAN_F10R1_FB28_Pos)
    -
    3816#define CAN_F10R1_FB28 CAN_F10R1_FB28_Msk
    -
    3817#define CAN_F10R1_FB29_Pos (29U)
    -
    3818#define CAN_F10R1_FB29_Msk (0x1UL << CAN_F10R1_FB29_Pos)
    -
    3819#define CAN_F10R1_FB29 CAN_F10R1_FB29_Msk
    -
    3820#define CAN_F10R1_FB30_Pos (30U)
    -
    3821#define CAN_F10R1_FB30_Msk (0x1UL << CAN_F10R1_FB30_Pos)
    -
    3822#define CAN_F10R1_FB30 CAN_F10R1_FB30_Msk
    -
    3823#define CAN_F10R1_FB31_Pos (31U)
    -
    3824#define CAN_F10R1_FB31_Msk (0x1UL << CAN_F10R1_FB31_Pos)
    -
    3825#define CAN_F10R1_FB31 CAN_F10R1_FB31_Msk
    -
    3827/******************* Bit definition for CAN_F11R1 register ******************/
    -
    3828#define CAN_F11R1_FB0_Pos (0U)
    -
    3829#define CAN_F11R1_FB0_Msk (0x1UL << CAN_F11R1_FB0_Pos)
    -
    3830#define CAN_F11R1_FB0 CAN_F11R1_FB0_Msk
    -
    3831#define CAN_F11R1_FB1_Pos (1U)
    -
    3832#define CAN_F11R1_FB1_Msk (0x1UL << CAN_F11R1_FB1_Pos)
    -
    3833#define CAN_F11R1_FB1 CAN_F11R1_FB1_Msk
    -
    3834#define CAN_F11R1_FB2_Pos (2U)
    -
    3835#define CAN_F11R1_FB2_Msk (0x1UL << CAN_F11R1_FB2_Pos)
    -
    3836#define CAN_F11R1_FB2 CAN_F11R1_FB2_Msk
    -
    3837#define CAN_F11R1_FB3_Pos (3U)
    -
    3838#define CAN_F11R1_FB3_Msk (0x1UL << CAN_F11R1_FB3_Pos)
    -
    3839#define CAN_F11R1_FB3 CAN_F11R1_FB3_Msk
    -
    3840#define CAN_F11R1_FB4_Pos (4U)
    -
    3841#define CAN_F11R1_FB4_Msk (0x1UL << CAN_F11R1_FB4_Pos)
    -
    3842#define CAN_F11R1_FB4 CAN_F11R1_FB4_Msk
    -
    3843#define CAN_F11R1_FB5_Pos (5U)
    -
    3844#define CAN_F11R1_FB5_Msk (0x1UL << CAN_F11R1_FB5_Pos)
    -
    3845#define CAN_F11R1_FB5 CAN_F11R1_FB5_Msk
    -
    3846#define CAN_F11R1_FB6_Pos (6U)
    -
    3847#define CAN_F11R1_FB6_Msk (0x1UL << CAN_F11R1_FB6_Pos)
    -
    3848#define CAN_F11R1_FB6 CAN_F11R1_FB6_Msk
    -
    3849#define CAN_F11R1_FB7_Pos (7U)
    -
    3850#define CAN_F11R1_FB7_Msk (0x1UL << CAN_F11R1_FB7_Pos)
    -
    3851#define CAN_F11R1_FB7 CAN_F11R1_FB7_Msk
    -
    3852#define CAN_F11R1_FB8_Pos (8U)
    -
    3853#define CAN_F11R1_FB8_Msk (0x1UL << CAN_F11R1_FB8_Pos)
    -
    3854#define CAN_F11R1_FB8 CAN_F11R1_FB8_Msk
    -
    3855#define CAN_F11R1_FB9_Pos (9U)
    -
    3856#define CAN_F11R1_FB9_Msk (0x1UL << CAN_F11R1_FB9_Pos)
    -
    3857#define CAN_F11R1_FB9 CAN_F11R1_FB9_Msk
    -
    3858#define CAN_F11R1_FB10_Pos (10U)
    -
    3859#define CAN_F11R1_FB10_Msk (0x1UL << CAN_F11R1_FB10_Pos)
    -
    3860#define CAN_F11R1_FB10 CAN_F11R1_FB10_Msk
    -
    3861#define CAN_F11R1_FB11_Pos (11U)
    -
    3862#define CAN_F11R1_FB11_Msk (0x1UL << CAN_F11R1_FB11_Pos)
    -
    3863#define CAN_F11R1_FB11 CAN_F11R1_FB11_Msk
    -
    3864#define CAN_F11R1_FB12_Pos (12U)
    -
    3865#define CAN_F11R1_FB12_Msk (0x1UL << CAN_F11R1_FB12_Pos)
    -
    3866#define CAN_F11R1_FB12 CAN_F11R1_FB12_Msk
    -
    3867#define CAN_F11R1_FB13_Pos (13U)
    -
    3868#define CAN_F11R1_FB13_Msk (0x1UL << CAN_F11R1_FB13_Pos)
    -
    3869#define CAN_F11R1_FB13 CAN_F11R1_FB13_Msk
    -
    3870#define CAN_F11R1_FB14_Pos (14U)
    -
    3871#define CAN_F11R1_FB14_Msk (0x1UL << CAN_F11R1_FB14_Pos)
    -
    3872#define CAN_F11R1_FB14 CAN_F11R1_FB14_Msk
    -
    3873#define CAN_F11R1_FB15_Pos (15U)
    -
    3874#define CAN_F11R1_FB15_Msk (0x1UL << CAN_F11R1_FB15_Pos)
    -
    3875#define CAN_F11R1_FB15 CAN_F11R1_FB15_Msk
    -
    3876#define CAN_F11R1_FB16_Pos (16U)
    -
    3877#define CAN_F11R1_FB16_Msk (0x1UL << CAN_F11R1_FB16_Pos)
    -
    3878#define CAN_F11R1_FB16 CAN_F11R1_FB16_Msk
    -
    3879#define CAN_F11R1_FB17_Pos (17U)
    -
    3880#define CAN_F11R1_FB17_Msk (0x1UL << CAN_F11R1_FB17_Pos)
    -
    3881#define CAN_F11R1_FB17 CAN_F11R1_FB17_Msk
    -
    3882#define CAN_F11R1_FB18_Pos (18U)
    -
    3883#define CAN_F11R1_FB18_Msk (0x1UL << CAN_F11R1_FB18_Pos)
    -
    3884#define CAN_F11R1_FB18 CAN_F11R1_FB18_Msk
    -
    3885#define CAN_F11R1_FB19_Pos (19U)
    -
    3886#define CAN_F11R1_FB19_Msk (0x1UL << CAN_F11R1_FB19_Pos)
    -
    3887#define CAN_F11R1_FB19 CAN_F11R1_FB19_Msk
    -
    3888#define CAN_F11R1_FB20_Pos (20U)
    -
    3889#define CAN_F11R1_FB20_Msk (0x1UL << CAN_F11R1_FB20_Pos)
    -
    3890#define CAN_F11R1_FB20 CAN_F11R1_FB20_Msk
    -
    3891#define CAN_F11R1_FB21_Pos (21U)
    -
    3892#define CAN_F11R1_FB21_Msk (0x1UL << CAN_F11R1_FB21_Pos)
    -
    3893#define CAN_F11R1_FB21 CAN_F11R1_FB21_Msk
    -
    3894#define CAN_F11R1_FB22_Pos (22U)
    -
    3895#define CAN_F11R1_FB22_Msk (0x1UL << CAN_F11R1_FB22_Pos)
    -
    3896#define CAN_F11R1_FB22 CAN_F11R1_FB22_Msk
    -
    3897#define CAN_F11R1_FB23_Pos (23U)
    -
    3898#define CAN_F11R1_FB23_Msk (0x1UL << CAN_F11R1_FB23_Pos)
    -
    3899#define CAN_F11R1_FB23 CAN_F11R1_FB23_Msk
    -
    3900#define CAN_F11R1_FB24_Pos (24U)
    -
    3901#define CAN_F11R1_FB24_Msk (0x1UL << CAN_F11R1_FB24_Pos)
    -
    3902#define CAN_F11R1_FB24 CAN_F11R1_FB24_Msk
    -
    3903#define CAN_F11R1_FB25_Pos (25U)
    -
    3904#define CAN_F11R1_FB25_Msk (0x1UL << CAN_F11R1_FB25_Pos)
    -
    3905#define CAN_F11R1_FB25 CAN_F11R1_FB25_Msk
    -
    3906#define CAN_F11R1_FB26_Pos (26U)
    -
    3907#define CAN_F11R1_FB26_Msk (0x1UL << CAN_F11R1_FB26_Pos)
    -
    3908#define CAN_F11R1_FB26 CAN_F11R1_FB26_Msk
    -
    3909#define CAN_F11R1_FB27_Pos (27U)
    -
    3910#define CAN_F11R1_FB27_Msk (0x1UL << CAN_F11R1_FB27_Pos)
    -
    3911#define CAN_F11R1_FB27 CAN_F11R1_FB27_Msk
    -
    3912#define CAN_F11R1_FB28_Pos (28U)
    -
    3913#define CAN_F11R1_FB28_Msk (0x1UL << CAN_F11R1_FB28_Pos)
    -
    3914#define CAN_F11R1_FB28 CAN_F11R1_FB28_Msk
    -
    3915#define CAN_F11R1_FB29_Pos (29U)
    -
    3916#define CAN_F11R1_FB29_Msk (0x1UL << CAN_F11R1_FB29_Pos)
    -
    3917#define CAN_F11R1_FB29 CAN_F11R1_FB29_Msk
    -
    3918#define CAN_F11R1_FB30_Pos (30U)
    -
    3919#define CAN_F11R1_FB30_Msk (0x1UL << CAN_F11R1_FB30_Pos)
    -
    3920#define CAN_F11R1_FB30 CAN_F11R1_FB30_Msk
    -
    3921#define CAN_F11R1_FB31_Pos (31U)
    -
    3922#define CAN_F11R1_FB31_Msk (0x1UL << CAN_F11R1_FB31_Pos)
    -
    3923#define CAN_F11R1_FB31 CAN_F11R1_FB31_Msk
    -
    3925/******************* Bit definition for CAN_F12R1 register ******************/
    -
    3926#define CAN_F12R1_FB0_Pos (0U)
    -
    3927#define CAN_F12R1_FB0_Msk (0x1UL << CAN_F12R1_FB0_Pos)
    -
    3928#define CAN_F12R1_FB0 CAN_F12R1_FB0_Msk
    -
    3929#define CAN_F12R1_FB1_Pos (1U)
    -
    3930#define CAN_F12R1_FB1_Msk (0x1UL << CAN_F12R1_FB1_Pos)
    -
    3931#define CAN_F12R1_FB1 CAN_F12R1_FB1_Msk
    -
    3932#define CAN_F12R1_FB2_Pos (2U)
    -
    3933#define CAN_F12R1_FB2_Msk (0x1UL << CAN_F12R1_FB2_Pos)
    -
    3934#define CAN_F12R1_FB2 CAN_F12R1_FB2_Msk
    -
    3935#define CAN_F12R1_FB3_Pos (3U)
    -
    3936#define CAN_F12R1_FB3_Msk (0x1UL << CAN_F12R1_FB3_Pos)
    -
    3937#define CAN_F12R1_FB3 CAN_F12R1_FB3_Msk
    -
    3938#define CAN_F12R1_FB4_Pos (4U)
    -
    3939#define CAN_F12R1_FB4_Msk (0x1UL << CAN_F12R1_FB4_Pos)
    -
    3940#define CAN_F12R1_FB4 CAN_F12R1_FB4_Msk
    -
    3941#define CAN_F12R1_FB5_Pos (5U)
    -
    3942#define CAN_F12R1_FB5_Msk (0x1UL << CAN_F12R1_FB5_Pos)
    -
    3943#define CAN_F12R1_FB5 CAN_F12R1_FB5_Msk
    -
    3944#define CAN_F12R1_FB6_Pos (6U)
    -
    3945#define CAN_F12R1_FB6_Msk (0x1UL << CAN_F12R1_FB6_Pos)
    -
    3946#define CAN_F12R1_FB6 CAN_F12R1_FB6_Msk
    -
    3947#define CAN_F12R1_FB7_Pos (7U)
    -
    3948#define CAN_F12R1_FB7_Msk (0x1UL << CAN_F12R1_FB7_Pos)
    -
    3949#define CAN_F12R1_FB7 CAN_F12R1_FB7_Msk
    -
    3950#define CAN_F12R1_FB8_Pos (8U)
    -
    3951#define CAN_F12R1_FB8_Msk (0x1UL << CAN_F12R1_FB8_Pos)
    -
    3952#define CAN_F12R1_FB8 CAN_F12R1_FB8_Msk
    -
    3953#define CAN_F12R1_FB9_Pos (9U)
    -
    3954#define CAN_F12R1_FB9_Msk (0x1UL << CAN_F12R1_FB9_Pos)
    -
    3955#define CAN_F12R1_FB9 CAN_F12R1_FB9_Msk
    -
    3956#define CAN_F12R1_FB10_Pos (10U)
    -
    3957#define CAN_F12R1_FB10_Msk (0x1UL << CAN_F12R1_FB10_Pos)
    -
    3958#define CAN_F12R1_FB10 CAN_F12R1_FB10_Msk
    -
    3959#define CAN_F12R1_FB11_Pos (11U)
    -
    3960#define CAN_F12R1_FB11_Msk (0x1UL << CAN_F12R1_FB11_Pos)
    -
    3961#define CAN_F12R1_FB11 CAN_F12R1_FB11_Msk
    -
    3962#define CAN_F12R1_FB12_Pos (12U)
    -
    3963#define CAN_F12R1_FB12_Msk (0x1UL << CAN_F12R1_FB12_Pos)
    -
    3964#define CAN_F12R1_FB12 CAN_F12R1_FB12_Msk
    -
    3965#define CAN_F12R1_FB13_Pos (13U)
    -
    3966#define CAN_F12R1_FB13_Msk (0x1UL << CAN_F12R1_FB13_Pos)
    -
    3967#define CAN_F12R1_FB13 CAN_F12R1_FB13_Msk
    -
    3968#define CAN_F12R1_FB14_Pos (14U)
    -
    3969#define CAN_F12R1_FB14_Msk (0x1UL << CAN_F12R1_FB14_Pos)
    -
    3970#define CAN_F12R1_FB14 CAN_F12R1_FB14_Msk
    -
    3971#define CAN_F12R1_FB15_Pos (15U)
    -
    3972#define CAN_F12R1_FB15_Msk (0x1UL << CAN_F12R1_FB15_Pos)
    -
    3973#define CAN_F12R1_FB15 CAN_F12R1_FB15_Msk
    -
    3974#define CAN_F12R1_FB16_Pos (16U)
    -
    3975#define CAN_F12R1_FB16_Msk (0x1UL << CAN_F12R1_FB16_Pos)
    -
    3976#define CAN_F12R1_FB16 CAN_F12R1_FB16_Msk
    -
    3977#define CAN_F12R1_FB17_Pos (17U)
    -
    3978#define CAN_F12R1_FB17_Msk (0x1UL << CAN_F12R1_FB17_Pos)
    -
    3979#define CAN_F12R1_FB17 CAN_F12R1_FB17_Msk
    -
    3980#define CAN_F12R1_FB18_Pos (18U)
    -
    3981#define CAN_F12R1_FB18_Msk (0x1UL << CAN_F12R1_FB18_Pos)
    -
    3982#define CAN_F12R1_FB18 CAN_F12R1_FB18_Msk
    -
    3983#define CAN_F12R1_FB19_Pos (19U)
    -
    3984#define CAN_F12R1_FB19_Msk (0x1UL << CAN_F12R1_FB19_Pos)
    -
    3985#define CAN_F12R1_FB19 CAN_F12R1_FB19_Msk
    -
    3986#define CAN_F12R1_FB20_Pos (20U)
    -
    3987#define CAN_F12R1_FB20_Msk (0x1UL << CAN_F12R1_FB20_Pos)
    -
    3988#define CAN_F12R1_FB20 CAN_F12R1_FB20_Msk
    -
    3989#define CAN_F12R1_FB21_Pos (21U)
    -
    3990#define CAN_F12R1_FB21_Msk (0x1UL << CAN_F12R1_FB21_Pos)
    -
    3991#define CAN_F12R1_FB21 CAN_F12R1_FB21_Msk
    -
    3992#define CAN_F12R1_FB22_Pos (22U)
    -
    3993#define CAN_F12R1_FB22_Msk (0x1UL << CAN_F12R1_FB22_Pos)
    -
    3994#define CAN_F12R1_FB22 CAN_F12R1_FB22_Msk
    -
    3995#define CAN_F12R1_FB23_Pos (23U)
    -
    3996#define CAN_F12R1_FB23_Msk (0x1UL << CAN_F12R1_FB23_Pos)
    -
    3997#define CAN_F12R1_FB23 CAN_F12R1_FB23_Msk
    -
    3998#define CAN_F12R1_FB24_Pos (24U)
    -
    3999#define CAN_F12R1_FB24_Msk (0x1UL << CAN_F12R1_FB24_Pos)
    -
    4000#define CAN_F12R1_FB24 CAN_F12R1_FB24_Msk
    -
    4001#define CAN_F12R1_FB25_Pos (25U)
    -
    4002#define CAN_F12R1_FB25_Msk (0x1UL << CAN_F12R1_FB25_Pos)
    -
    4003#define CAN_F12R1_FB25 CAN_F12R1_FB25_Msk
    -
    4004#define CAN_F12R1_FB26_Pos (26U)
    -
    4005#define CAN_F12R1_FB26_Msk (0x1UL << CAN_F12R1_FB26_Pos)
    -
    4006#define CAN_F12R1_FB26 CAN_F12R1_FB26_Msk
    -
    4007#define CAN_F12R1_FB27_Pos (27U)
    -
    4008#define CAN_F12R1_FB27_Msk (0x1UL << CAN_F12R1_FB27_Pos)
    -
    4009#define CAN_F12R1_FB27 CAN_F12R1_FB27_Msk
    -
    4010#define CAN_F12R1_FB28_Pos (28U)
    -
    4011#define CAN_F12R1_FB28_Msk (0x1UL << CAN_F12R1_FB28_Pos)
    -
    4012#define CAN_F12R1_FB28 CAN_F12R1_FB28_Msk
    -
    4013#define CAN_F12R1_FB29_Pos (29U)
    -
    4014#define CAN_F12R1_FB29_Msk (0x1UL << CAN_F12R1_FB29_Pos)
    -
    4015#define CAN_F12R1_FB29 CAN_F12R1_FB29_Msk
    -
    4016#define CAN_F12R1_FB30_Pos (30U)
    -
    4017#define CAN_F12R1_FB30_Msk (0x1UL << CAN_F12R1_FB30_Pos)
    -
    4018#define CAN_F12R1_FB30 CAN_F12R1_FB30_Msk
    -
    4019#define CAN_F12R1_FB31_Pos (31U)
    -
    4020#define CAN_F12R1_FB31_Msk (0x1UL << CAN_F12R1_FB31_Pos)
    -
    4021#define CAN_F12R1_FB31 CAN_F12R1_FB31_Msk
    -
    4023/******************* Bit definition for CAN_F13R1 register ******************/
    -
    4024#define CAN_F13R1_FB0_Pos (0U)
    -
    4025#define CAN_F13R1_FB0_Msk (0x1UL << CAN_F13R1_FB0_Pos)
    -
    4026#define CAN_F13R1_FB0 CAN_F13R1_FB0_Msk
    -
    4027#define CAN_F13R1_FB1_Pos (1U)
    -
    4028#define CAN_F13R1_FB1_Msk (0x1UL << CAN_F13R1_FB1_Pos)
    -
    4029#define CAN_F13R1_FB1 CAN_F13R1_FB1_Msk
    -
    4030#define CAN_F13R1_FB2_Pos (2U)
    -
    4031#define CAN_F13R1_FB2_Msk (0x1UL << CAN_F13R1_FB2_Pos)
    -
    4032#define CAN_F13R1_FB2 CAN_F13R1_FB2_Msk
    -
    4033#define CAN_F13R1_FB3_Pos (3U)
    -
    4034#define CAN_F13R1_FB3_Msk (0x1UL << CAN_F13R1_FB3_Pos)
    -
    4035#define CAN_F13R1_FB3 CAN_F13R1_FB3_Msk
    -
    4036#define CAN_F13R1_FB4_Pos (4U)
    -
    4037#define CAN_F13R1_FB4_Msk (0x1UL << CAN_F13R1_FB4_Pos)
    -
    4038#define CAN_F13R1_FB4 CAN_F13R1_FB4_Msk
    -
    4039#define CAN_F13R1_FB5_Pos (5U)
    -
    4040#define CAN_F13R1_FB5_Msk (0x1UL << CAN_F13R1_FB5_Pos)
    -
    4041#define CAN_F13R1_FB5 CAN_F13R1_FB5_Msk
    -
    4042#define CAN_F13R1_FB6_Pos (6U)
    -
    4043#define CAN_F13R1_FB6_Msk (0x1UL << CAN_F13R1_FB6_Pos)
    -
    4044#define CAN_F13R1_FB6 CAN_F13R1_FB6_Msk
    -
    4045#define CAN_F13R1_FB7_Pos (7U)
    -
    4046#define CAN_F13R1_FB7_Msk (0x1UL << CAN_F13R1_FB7_Pos)
    -
    4047#define CAN_F13R1_FB7 CAN_F13R1_FB7_Msk
    -
    4048#define CAN_F13R1_FB8_Pos (8U)
    -
    4049#define CAN_F13R1_FB8_Msk (0x1UL << CAN_F13R1_FB8_Pos)
    -
    4050#define CAN_F13R1_FB8 CAN_F13R1_FB8_Msk
    -
    4051#define CAN_F13R1_FB9_Pos (9U)
    -
    4052#define CAN_F13R1_FB9_Msk (0x1UL << CAN_F13R1_FB9_Pos)
    -
    4053#define CAN_F13R1_FB9 CAN_F13R1_FB9_Msk
    -
    4054#define CAN_F13R1_FB10_Pos (10U)
    -
    4055#define CAN_F13R1_FB10_Msk (0x1UL << CAN_F13R1_FB10_Pos)
    -
    4056#define CAN_F13R1_FB10 CAN_F13R1_FB10_Msk
    -
    4057#define CAN_F13R1_FB11_Pos (11U)
    -
    4058#define CAN_F13R1_FB11_Msk (0x1UL << CAN_F13R1_FB11_Pos)
    -
    4059#define CAN_F13R1_FB11 CAN_F13R1_FB11_Msk
    -
    4060#define CAN_F13R1_FB12_Pos (12U)
    -
    4061#define CAN_F13R1_FB12_Msk (0x1UL << CAN_F13R1_FB12_Pos)
    -
    4062#define CAN_F13R1_FB12 CAN_F13R1_FB12_Msk
    -
    4063#define CAN_F13R1_FB13_Pos (13U)
    -
    4064#define CAN_F13R1_FB13_Msk (0x1UL << CAN_F13R1_FB13_Pos)
    -
    4065#define CAN_F13R1_FB13 CAN_F13R1_FB13_Msk
    -
    4066#define CAN_F13R1_FB14_Pos (14U)
    -
    4067#define CAN_F13R1_FB14_Msk (0x1UL << CAN_F13R1_FB14_Pos)
    -
    4068#define CAN_F13R1_FB14 CAN_F13R1_FB14_Msk
    -
    4069#define CAN_F13R1_FB15_Pos (15U)
    -
    4070#define CAN_F13R1_FB15_Msk (0x1UL << CAN_F13R1_FB15_Pos)
    -
    4071#define CAN_F13R1_FB15 CAN_F13R1_FB15_Msk
    -
    4072#define CAN_F13R1_FB16_Pos (16U)
    -
    4073#define CAN_F13R1_FB16_Msk (0x1UL << CAN_F13R1_FB16_Pos)
    -
    4074#define CAN_F13R1_FB16 CAN_F13R1_FB16_Msk
    -
    4075#define CAN_F13R1_FB17_Pos (17U)
    -
    4076#define CAN_F13R1_FB17_Msk (0x1UL << CAN_F13R1_FB17_Pos)
    -
    4077#define CAN_F13R1_FB17 CAN_F13R1_FB17_Msk
    -
    4078#define CAN_F13R1_FB18_Pos (18U)
    -
    4079#define CAN_F13R1_FB18_Msk (0x1UL << CAN_F13R1_FB18_Pos)
    -
    4080#define CAN_F13R1_FB18 CAN_F13R1_FB18_Msk
    -
    4081#define CAN_F13R1_FB19_Pos (19U)
    -
    4082#define CAN_F13R1_FB19_Msk (0x1UL << CAN_F13R1_FB19_Pos)
    -
    4083#define CAN_F13R1_FB19 CAN_F13R1_FB19_Msk
    -
    4084#define CAN_F13R1_FB20_Pos (20U)
    -
    4085#define CAN_F13R1_FB20_Msk (0x1UL << CAN_F13R1_FB20_Pos)
    -
    4086#define CAN_F13R1_FB20 CAN_F13R1_FB20_Msk
    -
    4087#define CAN_F13R1_FB21_Pos (21U)
    -
    4088#define CAN_F13R1_FB21_Msk (0x1UL << CAN_F13R1_FB21_Pos)
    -
    4089#define CAN_F13R1_FB21 CAN_F13R1_FB21_Msk
    -
    4090#define CAN_F13R1_FB22_Pos (22U)
    -
    4091#define CAN_F13R1_FB22_Msk (0x1UL << CAN_F13R1_FB22_Pos)
    -
    4092#define CAN_F13R1_FB22 CAN_F13R1_FB22_Msk
    -
    4093#define CAN_F13R1_FB23_Pos (23U)
    -
    4094#define CAN_F13R1_FB23_Msk (0x1UL << CAN_F13R1_FB23_Pos)
    -
    4095#define CAN_F13R1_FB23 CAN_F13R1_FB23_Msk
    -
    4096#define CAN_F13R1_FB24_Pos (24U)
    -
    4097#define CAN_F13R1_FB24_Msk (0x1UL << CAN_F13R1_FB24_Pos)
    -
    4098#define CAN_F13R1_FB24 CAN_F13R1_FB24_Msk
    -
    4099#define CAN_F13R1_FB25_Pos (25U)
    -
    4100#define CAN_F13R1_FB25_Msk (0x1UL << CAN_F13R1_FB25_Pos)
    -
    4101#define CAN_F13R1_FB25 CAN_F13R1_FB25_Msk
    -
    4102#define CAN_F13R1_FB26_Pos (26U)
    -
    4103#define CAN_F13R1_FB26_Msk (0x1UL << CAN_F13R1_FB26_Pos)
    -
    4104#define CAN_F13R1_FB26 CAN_F13R1_FB26_Msk
    -
    4105#define CAN_F13R1_FB27_Pos (27U)
    -
    4106#define CAN_F13R1_FB27_Msk (0x1UL << CAN_F13R1_FB27_Pos)
    -
    4107#define CAN_F13R1_FB27 CAN_F13R1_FB27_Msk
    -
    4108#define CAN_F13R1_FB28_Pos (28U)
    -
    4109#define CAN_F13R1_FB28_Msk (0x1UL << CAN_F13R1_FB28_Pos)
    -
    4110#define CAN_F13R1_FB28 CAN_F13R1_FB28_Msk
    -
    4111#define CAN_F13R1_FB29_Pos (29U)
    -
    4112#define CAN_F13R1_FB29_Msk (0x1UL << CAN_F13R1_FB29_Pos)
    -
    4113#define CAN_F13R1_FB29 CAN_F13R1_FB29_Msk
    -
    4114#define CAN_F13R1_FB30_Pos (30U)
    -
    4115#define CAN_F13R1_FB30_Msk (0x1UL << CAN_F13R1_FB30_Pos)
    -
    4116#define CAN_F13R1_FB30 CAN_F13R1_FB30_Msk
    -
    4117#define CAN_F13R1_FB31_Pos (31U)
    -
    4118#define CAN_F13R1_FB31_Msk (0x1UL << CAN_F13R1_FB31_Pos)
    -
    4119#define CAN_F13R1_FB31 CAN_F13R1_FB31_Msk
    -
    4121/******************* Bit definition for CAN_F0R2 register *******************/
    -
    4122#define CAN_F0R2_FB0_Pos (0U)
    -
    4123#define CAN_F0R2_FB0_Msk (0x1UL << CAN_F0R2_FB0_Pos)
    -
    4124#define CAN_F0R2_FB0 CAN_F0R2_FB0_Msk
    -
    4125#define CAN_F0R2_FB1_Pos (1U)
    -
    4126#define CAN_F0R2_FB1_Msk (0x1UL << CAN_F0R2_FB1_Pos)
    -
    4127#define CAN_F0R2_FB1 CAN_F0R2_FB1_Msk
    -
    4128#define CAN_F0R2_FB2_Pos (2U)
    -
    4129#define CAN_F0R2_FB2_Msk (0x1UL << CAN_F0R2_FB2_Pos)
    -
    4130#define CAN_F0R2_FB2 CAN_F0R2_FB2_Msk
    -
    4131#define CAN_F0R2_FB3_Pos (3U)
    -
    4132#define CAN_F0R2_FB3_Msk (0x1UL << CAN_F0R2_FB3_Pos)
    -
    4133#define CAN_F0R2_FB3 CAN_F0R2_FB3_Msk
    -
    4134#define CAN_F0R2_FB4_Pos (4U)
    -
    4135#define CAN_F0R2_FB4_Msk (0x1UL << CAN_F0R2_FB4_Pos)
    -
    4136#define CAN_F0R2_FB4 CAN_F0R2_FB4_Msk
    -
    4137#define CAN_F0R2_FB5_Pos (5U)
    -
    4138#define CAN_F0R2_FB5_Msk (0x1UL << CAN_F0R2_FB5_Pos)
    -
    4139#define CAN_F0R2_FB5 CAN_F0R2_FB5_Msk
    -
    4140#define CAN_F0R2_FB6_Pos (6U)
    -
    4141#define CAN_F0R2_FB6_Msk (0x1UL << CAN_F0R2_FB6_Pos)
    -
    4142#define CAN_F0R2_FB6 CAN_F0R2_FB6_Msk
    -
    4143#define CAN_F0R2_FB7_Pos (7U)
    -
    4144#define CAN_F0R2_FB7_Msk (0x1UL << CAN_F0R2_FB7_Pos)
    -
    4145#define CAN_F0R2_FB7 CAN_F0R2_FB7_Msk
    -
    4146#define CAN_F0R2_FB8_Pos (8U)
    -
    4147#define CAN_F0R2_FB8_Msk (0x1UL << CAN_F0R2_FB8_Pos)
    -
    4148#define CAN_F0R2_FB8 CAN_F0R2_FB8_Msk
    -
    4149#define CAN_F0R2_FB9_Pos (9U)
    -
    4150#define CAN_F0R2_FB9_Msk (0x1UL << CAN_F0R2_FB9_Pos)
    -
    4151#define CAN_F0R2_FB9 CAN_F0R2_FB9_Msk
    -
    4152#define CAN_F0R2_FB10_Pos (10U)
    -
    4153#define CAN_F0R2_FB10_Msk (0x1UL << CAN_F0R2_FB10_Pos)
    -
    4154#define CAN_F0R2_FB10 CAN_F0R2_FB10_Msk
    -
    4155#define CAN_F0R2_FB11_Pos (11U)
    -
    4156#define CAN_F0R2_FB11_Msk (0x1UL << CAN_F0R2_FB11_Pos)
    -
    4157#define CAN_F0R2_FB11 CAN_F0R2_FB11_Msk
    -
    4158#define CAN_F0R2_FB12_Pos (12U)
    -
    4159#define CAN_F0R2_FB12_Msk (0x1UL << CAN_F0R2_FB12_Pos)
    -
    4160#define CAN_F0R2_FB12 CAN_F0R2_FB12_Msk
    -
    4161#define CAN_F0R2_FB13_Pos (13U)
    -
    4162#define CAN_F0R2_FB13_Msk (0x1UL << CAN_F0R2_FB13_Pos)
    -
    4163#define CAN_F0R2_FB13 CAN_F0R2_FB13_Msk
    -
    4164#define CAN_F0R2_FB14_Pos (14U)
    -
    4165#define CAN_F0R2_FB14_Msk (0x1UL << CAN_F0R2_FB14_Pos)
    -
    4166#define CAN_F0R2_FB14 CAN_F0R2_FB14_Msk
    -
    4167#define CAN_F0R2_FB15_Pos (15U)
    -
    4168#define CAN_F0R2_FB15_Msk (0x1UL << CAN_F0R2_FB15_Pos)
    -
    4169#define CAN_F0R2_FB15 CAN_F0R2_FB15_Msk
    -
    4170#define CAN_F0R2_FB16_Pos (16U)
    -
    4171#define CAN_F0R2_FB16_Msk (0x1UL << CAN_F0R2_FB16_Pos)
    -
    4172#define CAN_F0R2_FB16 CAN_F0R2_FB16_Msk
    -
    4173#define CAN_F0R2_FB17_Pos (17U)
    -
    4174#define CAN_F0R2_FB17_Msk (0x1UL << CAN_F0R2_FB17_Pos)
    -
    4175#define CAN_F0R2_FB17 CAN_F0R2_FB17_Msk
    -
    4176#define CAN_F0R2_FB18_Pos (18U)
    -
    4177#define CAN_F0R2_FB18_Msk (0x1UL << CAN_F0R2_FB18_Pos)
    -
    4178#define CAN_F0R2_FB18 CAN_F0R2_FB18_Msk
    -
    4179#define CAN_F0R2_FB19_Pos (19U)
    -
    4180#define CAN_F0R2_FB19_Msk (0x1UL << CAN_F0R2_FB19_Pos)
    -
    4181#define CAN_F0R2_FB19 CAN_F0R2_FB19_Msk
    -
    4182#define CAN_F0R2_FB20_Pos (20U)
    -
    4183#define CAN_F0R2_FB20_Msk (0x1UL << CAN_F0R2_FB20_Pos)
    -
    4184#define CAN_F0R2_FB20 CAN_F0R2_FB20_Msk
    -
    4185#define CAN_F0R2_FB21_Pos (21U)
    -
    4186#define CAN_F0R2_FB21_Msk (0x1UL << CAN_F0R2_FB21_Pos)
    -
    4187#define CAN_F0R2_FB21 CAN_F0R2_FB21_Msk
    -
    4188#define CAN_F0R2_FB22_Pos (22U)
    -
    4189#define CAN_F0R2_FB22_Msk (0x1UL << CAN_F0R2_FB22_Pos)
    -
    4190#define CAN_F0R2_FB22 CAN_F0R2_FB22_Msk
    -
    4191#define CAN_F0R2_FB23_Pos (23U)
    -
    4192#define CAN_F0R2_FB23_Msk (0x1UL << CAN_F0R2_FB23_Pos)
    -
    4193#define CAN_F0R2_FB23 CAN_F0R2_FB23_Msk
    -
    4194#define CAN_F0R2_FB24_Pos (24U)
    -
    4195#define CAN_F0R2_FB24_Msk (0x1UL << CAN_F0R2_FB24_Pos)
    -
    4196#define CAN_F0R2_FB24 CAN_F0R2_FB24_Msk
    -
    4197#define CAN_F0R2_FB25_Pos (25U)
    -
    4198#define CAN_F0R2_FB25_Msk (0x1UL << CAN_F0R2_FB25_Pos)
    -
    4199#define CAN_F0R2_FB25 CAN_F0R2_FB25_Msk
    -
    4200#define CAN_F0R2_FB26_Pos (26U)
    -
    4201#define CAN_F0R2_FB26_Msk (0x1UL << CAN_F0R2_FB26_Pos)
    -
    4202#define CAN_F0R2_FB26 CAN_F0R2_FB26_Msk
    -
    4203#define CAN_F0R2_FB27_Pos (27U)
    -
    4204#define CAN_F0R2_FB27_Msk (0x1UL << CAN_F0R2_FB27_Pos)
    -
    4205#define CAN_F0R2_FB27 CAN_F0R2_FB27_Msk
    -
    4206#define CAN_F0R2_FB28_Pos (28U)
    -
    4207#define CAN_F0R2_FB28_Msk (0x1UL << CAN_F0R2_FB28_Pos)
    -
    4208#define CAN_F0R2_FB28 CAN_F0R2_FB28_Msk
    -
    4209#define CAN_F0R2_FB29_Pos (29U)
    -
    4210#define CAN_F0R2_FB29_Msk (0x1UL << CAN_F0R2_FB29_Pos)
    -
    4211#define CAN_F0R2_FB29 CAN_F0R2_FB29_Msk
    -
    4212#define CAN_F0R2_FB30_Pos (30U)
    -
    4213#define CAN_F0R2_FB30_Msk (0x1UL << CAN_F0R2_FB30_Pos)
    -
    4214#define CAN_F0R2_FB30 CAN_F0R2_FB30_Msk
    -
    4215#define CAN_F0R2_FB31_Pos (31U)
    -
    4216#define CAN_F0R2_FB31_Msk (0x1UL << CAN_F0R2_FB31_Pos)
    -
    4217#define CAN_F0R2_FB31 CAN_F0R2_FB31_Msk
    -
    4219/******************* Bit definition for CAN_F1R2 register *******************/
    -
    4220#define CAN_F1R2_FB0_Pos (0U)
    -
    4221#define CAN_F1R2_FB0_Msk (0x1UL << CAN_F1R2_FB0_Pos)
    -
    4222#define CAN_F1R2_FB0 CAN_F1R2_FB0_Msk
    -
    4223#define CAN_F1R2_FB1_Pos (1U)
    -
    4224#define CAN_F1R2_FB1_Msk (0x1UL << CAN_F1R2_FB1_Pos)
    -
    4225#define CAN_F1R2_FB1 CAN_F1R2_FB1_Msk
    -
    4226#define CAN_F1R2_FB2_Pos (2U)
    -
    4227#define CAN_F1R2_FB2_Msk (0x1UL << CAN_F1R2_FB2_Pos)
    -
    4228#define CAN_F1R2_FB2 CAN_F1R2_FB2_Msk
    -
    4229#define CAN_F1R2_FB3_Pos (3U)
    -
    4230#define CAN_F1R2_FB3_Msk (0x1UL << CAN_F1R2_FB3_Pos)
    -
    4231#define CAN_F1R2_FB3 CAN_F1R2_FB3_Msk
    -
    4232#define CAN_F1R2_FB4_Pos (4U)
    -
    4233#define CAN_F1R2_FB4_Msk (0x1UL << CAN_F1R2_FB4_Pos)
    -
    4234#define CAN_F1R2_FB4 CAN_F1R2_FB4_Msk
    -
    4235#define CAN_F1R2_FB5_Pos (5U)
    -
    4236#define CAN_F1R2_FB5_Msk (0x1UL << CAN_F1R2_FB5_Pos)
    -
    4237#define CAN_F1R2_FB5 CAN_F1R2_FB5_Msk
    -
    4238#define CAN_F1R2_FB6_Pos (6U)
    -
    4239#define CAN_F1R2_FB6_Msk (0x1UL << CAN_F1R2_FB6_Pos)
    -
    4240#define CAN_F1R2_FB6 CAN_F1R2_FB6_Msk
    -
    4241#define CAN_F1R2_FB7_Pos (7U)
    -
    4242#define CAN_F1R2_FB7_Msk (0x1UL << CAN_F1R2_FB7_Pos)
    -
    4243#define CAN_F1R2_FB7 CAN_F1R2_FB7_Msk
    -
    4244#define CAN_F1R2_FB8_Pos (8U)
    -
    4245#define CAN_F1R2_FB8_Msk (0x1UL << CAN_F1R2_FB8_Pos)
    -
    4246#define CAN_F1R2_FB8 CAN_F1R2_FB8_Msk
    -
    4247#define CAN_F1R2_FB9_Pos (9U)
    -
    4248#define CAN_F1R2_FB9_Msk (0x1UL << CAN_F1R2_FB9_Pos)
    -
    4249#define CAN_F1R2_FB9 CAN_F1R2_FB9_Msk
    -
    4250#define CAN_F1R2_FB10_Pos (10U)
    -
    4251#define CAN_F1R2_FB10_Msk (0x1UL << CAN_F1R2_FB10_Pos)
    -
    4252#define CAN_F1R2_FB10 CAN_F1R2_FB10_Msk
    -
    4253#define CAN_F1R2_FB11_Pos (11U)
    -
    4254#define CAN_F1R2_FB11_Msk (0x1UL << CAN_F1R2_FB11_Pos)
    -
    4255#define CAN_F1R2_FB11 CAN_F1R2_FB11_Msk
    -
    4256#define CAN_F1R2_FB12_Pos (12U)
    -
    4257#define CAN_F1R2_FB12_Msk (0x1UL << CAN_F1R2_FB12_Pos)
    -
    4258#define CAN_F1R2_FB12 CAN_F1R2_FB12_Msk
    -
    4259#define CAN_F1R2_FB13_Pos (13U)
    -
    4260#define CAN_F1R2_FB13_Msk (0x1UL << CAN_F1R2_FB13_Pos)
    -
    4261#define CAN_F1R2_FB13 CAN_F1R2_FB13_Msk
    -
    4262#define CAN_F1R2_FB14_Pos (14U)
    -
    4263#define CAN_F1R2_FB14_Msk (0x1UL << CAN_F1R2_FB14_Pos)
    -
    4264#define CAN_F1R2_FB14 CAN_F1R2_FB14_Msk
    -
    4265#define CAN_F1R2_FB15_Pos (15U)
    -
    4266#define CAN_F1R2_FB15_Msk (0x1UL << CAN_F1R2_FB15_Pos)
    -
    4267#define CAN_F1R2_FB15 CAN_F1R2_FB15_Msk
    -
    4268#define CAN_F1R2_FB16_Pos (16U)
    -
    4269#define CAN_F1R2_FB16_Msk (0x1UL << CAN_F1R2_FB16_Pos)
    -
    4270#define CAN_F1R2_FB16 CAN_F1R2_FB16_Msk
    -
    4271#define CAN_F1R2_FB17_Pos (17U)
    -
    4272#define CAN_F1R2_FB17_Msk (0x1UL << CAN_F1R2_FB17_Pos)
    -
    4273#define CAN_F1R2_FB17 CAN_F1R2_FB17_Msk
    -
    4274#define CAN_F1R2_FB18_Pos (18U)
    -
    4275#define CAN_F1R2_FB18_Msk (0x1UL << CAN_F1R2_FB18_Pos)
    -
    4276#define CAN_F1R2_FB18 CAN_F1R2_FB18_Msk
    -
    4277#define CAN_F1R2_FB19_Pos (19U)
    -
    4278#define CAN_F1R2_FB19_Msk (0x1UL << CAN_F1R2_FB19_Pos)
    -
    4279#define CAN_F1R2_FB19 CAN_F1R2_FB19_Msk
    -
    4280#define CAN_F1R2_FB20_Pos (20U)
    -
    4281#define CAN_F1R2_FB20_Msk (0x1UL << CAN_F1R2_FB20_Pos)
    -
    4282#define CAN_F1R2_FB20 CAN_F1R2_FB20_Msk
    -
    4283#define CAN_F1R2_FB21_Pos (21U)
    -
    4284#define CAN_F1R2_FB21_Msk (0x1UL << CAN_F1R2_FB21_Pos)
    -
    4285#define CAN_F1R2_FB21 CAN_F1R2_FB21_Msk
    -
    4286#define CAN_F1R2_FB22_Pos (22U)
    -
    4287#define CAN_F1R2_FB22_Msk (0x1UL << CAN_F1R2_FB22_Pos)
    -
    4288#define CAN_F1R2_FB22 CAN_F1R2_FB22_Msk
    -
    4289#define CAN_F1R2_FB23_Pos (23U)
    -
    4290#define CAN_F1R2_FB23_Msk (0x1UL << CAN_F1R2_FB23_Pos)
    -
    4291#define CAN_F1R2_FB23 CAN_F1R2_FB23_Msk
    -
    4292#define CAN_F1R2_FB24_Pos (24U)
    -
    4293#define CAN_F1R2_FB24_Msk (0x1UL << CAN_F1R2_FB24_Pos)
    -
    4294#define CAN_F1R2_FB24 CAN_F1R2_FB24_Msk
    -
    4295#define CAN_F1R2_FB25_Pos (25U)
    -
    4296#define CAN_F1R2_FB25_Msk (0x1UL << CAN_F1R2_FB25_Pos)
    -
    4297#define CAN_F1R2_FB25 CAN_F1R2_FB25_Msk
    -
    4298#define CAN_F1R2_FB26_Pos (26U)
    -
    4299#define CAN_F1R2_FB26_Msk (0x1UL << CAN_F1R2_FB26_Pos)
    -
    4300#define CAN_F1R2_FB26 CAN_F1R2_FB26_Msk
    -
    4301#define CAN_F1R2_FB27_Pos (27U)
    -
    4302#define CAN_F1R2_FB27_Msk (0x1UL << CAN_F1R2_FB27_Pos)
    -
    4303#define CAN_F1R2_FB27 CAN_F1R2_FB27_Msk
    -
    4304#define CAN_F1R2_FB28_Pos (28U)
    -
    4305#define CAN_F1R2_FB28_Msk (0x1UL << CAN_F1R2_FB28_Pos)
    -
    4306#define CAN_F1R2_FB28 CAN_F1R2_FB28_Msk
    -
    4307#define CAN_F1R2_FB29_Pos (29U)
    -
    4308#define CAN_F1R2_FB29_Msk (0x1UL << CAN_F1R2_FB29_Pos)
    -
    4309#define CAN_F1R2_FB29 CAN_F1R2_FB29_Msk
    -
    4310#define CAN_F1R2_FB30_Pos (30U)
    -
    4311#define CAN_F1R2_FB30_Msk (0x1UL << CAN_F1R2_FB30_Pos)
    -
    4312#define CAN_F1R2_FB30 CAN_F1R2_FB30_Msk
    -
    4313#define CAN_F1R2_FB31_Pos (31U)
    -
    4314#define CAN_F1R2_FB31_Msk (0x1UL << CAN_F1R2_FB31_Pos)
    -
    4315#define CAN_F1R2_FB31 CAN_F1R2_FB31_Msk
    -
    4317/******************* Bit definition for CAN_F2R2 register *******************/
    -
    4318#define CAN_F2R2_FB0_Pos (0U)
    -
    4319#define CAN_F2R2_FB0_Msk (0x1UL << CAN_F2R2_FB0_Pos)
    -
    4320#define CAN_F2R2_FB0 CAN_F2R2_FB0_Msk
    -
    4321#define CAN_F2R2_FB1_Pos (1U)
    -
    4322#define CAN_F2R2_FB1_Msk (0x1UL << CAN_F2R2_FB1_Pos)
    -
    4323#define CAN_F2R2_FB1 CAN_F2R2_FB1_Msk
    -
    4324#define CAN_F2R2_FB2_Pos (2U)
    -
    4325#define CAN_F2R2_FB2_Msk (0x1UL << CAN_F2R2_FB2_Pos)
    -
    4326#define CAN_F2R2_FB2 CAN_F2R2_FB2_Msk
    -
    4327#define CAN_F2R2_FB3_Pos (3U)
    -
    4328#define CAN_F2R2_FB3_Msk (0x1UL << CAN_F2R2_FB3_Pos)
    -
    4329#define CAN_F2R2_FB3 CAN_F2R2_FB3_Msk
    -
    4330#define CAN_F2R2_FB4_Pos (4U)
    -
    4331#define CAN_F2R2_FB4_Msk (0x1UL << CAN_F2R2_FB4_Pos)
    -
    4332#define CAN_F2R2_FB4 CAN_F2R2_FB4_Msk
    -
    4333#define CAN_F2R2_FB5_Pos (5U)
    -
    4334#define CAN_F2R2_FB5_Msk (0x1UL << CAN_F2R2_FB5_Pos)
    -
    4335#define CAN_F2R2_FB5 CAN_F2R2_FB5_Msk
    -
    4336#define CAN_F2R2_FB6_Pos (6U)
    -
    4337#define CAN_F2R2_FB6_Msk (0x1UL << CAN_F2R2_FB6_Pos)
    -
    4338#define CAN_F2R2_FB6 CAN_F2R2_FB6_Msk
    -
    4339#define CAN_F2R2_FB7_Pos (7U)
    -
    4340#define CAN_F2R2_FB7_Msk (0x1UL << CAN_F2R2_FB7_Pos)
    -
    4341#define CAN_F2R2_FB7 CAN_F2R2_FB7_Msk
    -
    4342#define CAN_F2R2_FB8_Pos (8U)
    -
    4343#define CAN_F2R2_FB8_Msk (0x1UL << CAN_F2R2_FB8_Pos)
    -
    4344#define CAN_F2R2_FB8 CAN_F2R2_FB8_Msk
    -
    4345#define CAN_F2R2_FB9_Pos (9U)
    -
    4346#define CAN_F2R2_FB9_Msk (0x1UL << CAN_F2R2_FB9_Pos)
    -
    4347#define CAN_F2R2_FB9 CAN_F2R2_FB9_Msk
    -
    4348#define CAN_F2R2_FB10_Pos (10U)
    -
    4349#define CAN_F2R2_FB10_Msk (0x1UL << CAN_F2R2_FB10_Pos)
    -
    4350#define CAN_F2R2_FB10 CAN_F2R2_FB10_Msk
    -
    4351#define CAN_F2R2_FB11_Pos (11U)
    -
    4352#define CAN_F2R2_FB11_Msk (0x1UL << CAN_F2R2_FB11_Pos)
    -
    4353#define CAN_F2R2_FB11 CAN_F2R2_FB11_Msk
    -
    4354#define CAN_F2R2_FB12_Pos (12U)
    -
    4355#define CAN_F2R2_FB12_Msk (0x1UL << CAN_F2R2_FB12_Pos)
    -
    4356#define CAN_F2R2_FB12 CAN_F2R2_FB12_Msk
    -
    4357#define CAN_F2R2_FB13_Pos (13U)
    -
    4358#define CAN_F2R2_FB13_Msk (0x1UL << CAN_F2R2_FB13_Pos)
    -
    4359#define CAN_F2R2_FB13 CAN_F2R2_FB13_Msk
    -
    4360#define CAN_F2R2_FB14_Pos (14U)
    -
    4361#define CAN_F2R2_FB14_Msk (0x1UL << CAN_F2R2_FB14_Pos)
    -
    4362#define CAN_F2R2_FB14 CAN_F2R2_FB14_Msk
    -
    4363#define CAN_F2R2_FB15_Pos (15U)
    -
    4364#define CAN_F2R2_FB15_Msk (0x1UL << CAN_F2R2_FB15_Pos)
    -
    4365#define CAN_F2R2_FB15 CAN_F2R2_FB15_Msk
    -
    4366#define CAN_F2R2_FB16_Pos (16U)
    -
    4367#define CAN_F2R2_FB16_Msk (0x1UL << CAN_F2R2_FB16_Pos)
    -
    4368#define CAN_F2R2_FB16 CAN_F2R2_FB16_Msk
    -
    4369#define CAN_F2R2_FB17_Pos (17U)
    -
    4370#define CAN_F2R2_FB17_Msk (0x1UL << CAN_F2R2_FB17_Pos)
    -
    4371#define CAN_F2R2_FB17 CAN_F2R2_FB17_Msk
    -
    4372#define CAN_F2R2_FB18_Pos (18U)
    -
    4373#define CAN_F2R2_FB18_Msk (0x1UL << CAN_F2R2_FB18_Pos)
    -
    4374#define CAN_F2R2_FB18 CAN_F2R2_FB18_Msk
    -
    4375#define CAN_F2R2_FB19_Pos (19U)
    -
    4376#define CAN_F2R2_FB19_Msk (0x1UL << CAN_F2R2_FB19_Pos)
    -
    4377#define CAN_F2R2_FB19 CAN_F2R2_FB19_Msk
    -
    4378#define CAN_F2R2_FB20_Pos (20U)
    -
    4379#define CAN_F2R2_FB20_Msk (0x1UL << CAN_F2R2_FB20_Pos)
    -
    4380#define CAN_F2R2_FB20 CAN_F2R2_FB20_Msk
    -
    4381#define CAN_F2R2_FB21_Pos (21U)
    -
    4382#define CAN_F2R2_FB21_Msk (0x1UL << CAN_F2R2_FB21_Pos)
    -
    4383#define CAN_F2R2_FB21 CAN_F2R2_FB21_Msk
    -
    4384#define CAN_F2R2_FB22_Pos (22U)
    -
    4385#define CAN_F2R2_FB22_Msk (0x1UL << CAN_F2R2_FB22_Pos)
    -
    4386#define CAN_F2R2_FB22 CAN_F2R2_FB22_Msk
    -
    4387#define CAN_F2R2_FB23_Pos (23U)
    -
    4388#define CAN_F2R2_FB23_Msk (0x1UL << CAN_F2R2_FB23_Pos)
    -
    4389#define CAN_F2R2_FB23 CAN_F2R2_FB23_Msk
    -
    4390#define CAN_F2R2_FB24_Pos (24U)
    -
    4391#define CAN_F2R2_FB24_Msk (0x1UL << CAN_F2R2_FB24_Pos)
    -
    4392#define CAN_F2R2_FB24 CAN_F2R2_FB24_Msk
    -
    4393#define CAN_F2R2_FB25_Pos (25U)
    -
    4394#define CAN_F2R2_FB25_Msk (0x1UL << CAN_F2R2_FB25_Pos)
    -
    4395#define CAN_F2R2_FB25 CAN_F2R2_FB25_Msk
    -
    4396#define CAN_F2R2_FB26_Pos (26U)
    -
    4397#define CAN_F2R2_FB26_Msk (0x1UL << CAN_F2R2_FB26_Pos)
    -
    4398#define CAN_F2R2_FB26 CAN_F2R2_FB26_Msk
    -
    4399#define CAN_F2R2_FB27_Pos (27U)
    -
    4400#define CAN_F2R2_FB27_Msk (0x1UL << CAN_F2R2_FB27_Pos)
    -
    4401#define CAN_F2R2_FB27 CAN_F2R2_FB27_Msk
    -
    4402#define CAN_F2R2_FB28_Pos (28U)
    -
    4403#define CAN_F2R2_FB28_Msk (0x1UL << CAN_F2R2_FB28_Pos)
    -
    4404#define CAN_F2R2_FB28 CAN_F2R2_FB28_Msk
    -
    4405#define CAN_F2R2_FB29_Pos (29U)
    -
    4406#define CAN_F2R2_FB29_Msk (0x1UL << CAN_F2R2_FB29_Pos)
    -
    4407#define CAN_F2R2_FB29 CAN_F2R2_FB29_Msk
    -
    4408#define CAN_F2R2_FB30_Pos (30U)
    -
    4409#define CAN_F2R2_FB30_Msk (0x1UL << CAN_F2R2_FB30_Pos)
    -
    4410#define CAN_F2R2_FB30 CAN_F2R2_FB30_Msk
    -
    4411#define CAN_F2R2_FB31_Pos (31U)
    -
    4412#define CAN_F2R2_FB31_Msk (0x1UL << CAN_F2R2_FB31_Pos)
    -
    4413#define CAN_F2R2_FB31 CAN_F2R2_FB31_Msk
    -
    4415/******************* Bit definition for CAN_F3R2 register *******************/
    -
    4416#define CAN_F3R2_FB0_Pos (0U)
    -
    4417#define CAN_F3R2_FB0_Msk (0x1UL << CAN_F3R2_FB0_Pos)
    -
    4418#define CAN_F3R2_FB0 CAN_F3R2_FB0_Msk
    -
    4419#define CAN_F3R2_FB1_Pos (1U)
    -
    4420#define CAN_F3R2_FB1_Msk (0x1UL << CAN_F3R2_FB1_Pos)
    -
    4421#define CAN_F3R2_FB1 CAN_F3R2_FB1_Msk
    -
    4422#define CAN_F3R2_FB2_Pos (2U)
    -
    4423#define CAN_F3R2_FB2_Msk (0x1UL << CAN_F3R2_FB2_Pos)
    -
    4424#define CAN_F3R2_FB2 CAN_F3R2_FB2_Msk
    -
    4425#define CAN_F3R2_FB3_Pos (3U)
    -
    4426#define CAN_F3R2_FB3_Msk (0x1UL << CAN_F3R2_FB3_Pos)
    -
    4427#define CAN_F3R2_FB3 CAN_F3R2_FB3_Msk
    -
    4428#define CAN_F3R2_FB4_Pos (4U)
    -
    4429#define CAN_F3R2_FB4_Msk (0x1UL << CAN_F3R2_FB4_Pos)
    -
    4430#define CAN_F3R2_FB4 CAN_F3R2_FB4_Msk
    -
    4431#define CAN_F3R2_FB5_Pos (5U)
    -
    4432#define CAN_F3R2_FB5_Msk (0x1UL << CAN_F3R2_FB5_Pos)
    -
    4433#define CAN_F3R2_FB5 CAN_F3R2_FB5_Msk
    -
    4434#define CAN_F3R2_FB6_Pos (6U)
    -
    4435#define CAN_F3R2_FB6_Msk (0x1UL << CAN_F3R2_FB6_Pos)
    -
    4436#define CAN_F3R2_FB6 CAN_F3R2_FB6_Msk
    -
    4437#define CAN_F3R2_FB7_Pos (7U)
    -
    4438#define CAN_F3R2_FB7_Msk (0x1UL << CAN_F3R2_FB7_Pos)
    -
    4439#define CAN_F3R2_FB7 CAN_F3R2_FB7_Msk
    -
    4440#define CAN_F3R2_FB8_Pos (8U)
    -
    4441#define CAN_F3R2_FB8_Msk (0x1UL << CAN_F3R2_FB8_Pos)
    -
    4442#define CAN_F3R2_FB8 CAN_F3R2_FB8_Msk
    -
    4443#define CAN_F3R2_FB9_Pos (9U)
    -
    4444#define CAN_F3R2_FB9_Msk (0x1UL << CAN_F3R2_FB9_Pos)
    -
    4445#define CAN_F3R2_FB9 CAN_F3R2_FB9_Msk
    -
    4446#define CAN_F3R2_FB10_Pos (10U)
    -
    4447#define CAN_F3R2_FB10_Msk (0x1UL << CAN_F3R2_FB10_Pos)
    -
    4448#define CAN_F3R2_FB10 CAN_F3R2_FB10_Msk
    -
    4449#define CAN_F3R2_FB11_Pos (11U)
    -
    4450#define CAN_F3R2_FB11_Msk (0x1UL << CAN_F3R2_FB11_Pos)
    -
    4451#define CAN_F3R2_FB11 CAN_F3R2_FB11_Msk
    -
    4452#define CAN_F3R2_FB12_Pos (12U)
    -
    4453#define CAN_F3R2_FB12_Msk (0x1UL << CAN_F3R2_FB12_Pos)
    -
    4454#define CAN_F3R2_FB12 CAN_F3R2_FB12_Msk
    -
    4455#define CAN_F3R2_FB13_Pos (13U)
    -
    4456#define CAN_F3R2_FB13_Msk (0x1UL << CAN_F3R2_FB13_Pos)
    -
    4457#define CAN_F3R2_FB13 CAN_F3R2_FB13_Msk
    -
    4458#define CAN_F3R2_FB14_Pos (14U)
    -
    4459#define CAN_F3R2_FB14_Msk (0x1UL << CAN_F3R2_FB14_Pos)
    -
    4460#define CAN_F3R2_FB14 CAN_F3R2_FB14_Msk
    -
    4461#define CAN_F3R2_FB15_Pos (15U)
    -
    4462#define CAN_F3R2_FB15_Msk (0x1UL << CAN_F3R2_FB15_Pos)
    -
    4463#define CAN_F3R2_FB15 CAN_F3R2_FB15_Msk
    -
    4464#define CAN_F3R2_FB16_Pos (16U)
    -
    4465#define CAN_F3R2_FB16_Msk (0x1UL << CAN_F3R2_FB16_Pos)
    -
    4466#define CAN_F3R2_FB16 CAN_F3R2_FB16_Msk
    -
    4467#define CAN_F3R2_FB17_Pos (17U)
    -
    4468#define CAN_F3R2_FB17_Msk (0x1UL << CAN_F3R2_FB17_Pos)
    -
    4469#define CAN_F3R2_FB17 CAN_F3R2_FB17_Msk
    -
    4470#define CAN_F3R2_FB18_Pos (18U)
    -
    4471#define CAN_F3R2_FB18_Msk (0x1UL << CAN_F3R2_FB18_Pos)
    -
    4472#define CAN_F3R2_FB18 CAN_F3R2_FB18_Msk
    -
    4473#define CAN_F3R2_FB19_Pos (19U)
    -
    4474#define CAN_F3R2_FB19_Msk (0x1UL << CAN_F3R2_FB19_Pos)
    -
    4475#define CAN_F3R2_FB19 CAN_F3R2_FB19_Msk
    -
    4476#define CAN_F3R2_FB20_Pos (20U)
    -
    4477#define CAN_F3R2_FB20_Msk (0x1UL << CAN_F3R2_FB20_Pos)
    -
    4478#define CAN_F3R2_FB20 CAN_F3R2_FB20_Msk
    -
    4479#define CAN_F3R2_FB21_Pos (21U)
    -
    4480#define CAN_F3R2_FB21_Msk (0x1UL << CAN_F3R2_FB21_Pos)
    -
    4481#define CAN_F3R2_FB21 CAN_F3R2_FB21_Msk
    -
    4482#define CAN_F3R2_FB22_Pos (22U)
    -
    4483#define CAN_F3R2_FB22_Msk (0x1UL << CAN_F3R2_FB22_Pos)
    -
    4484#define CAN_F3R2_FB22 CAN_F3R2_FB22_Msk
    -
    4485#define CAN_F3R2_FB23_Pos (23U)
    -
    4486#define CAN_F3R2_FB23_Msk (0x1UL << CAN_F3R2_FB23_Pos)
    -
    4487#define CAN_F3R2_FB23 CAN_F3R2_FB23_Msk
    -
    4488#define CAN_F3R2_FB24_Pos (24U)
    -
    4489#define CAN_F3R2_FB24_Msk (0x1UL << CAN_F3R2_FB24_Pos)
    -
    4490#define CAN_F3R2_FB24 CAN_F3R2_FB24_Msk
    -
    4491#define CAN_F3R2_FB25_Pos (25U)
    -
    4492#define CAN_F3R2_FB25_Msk (0x1UL << CAN_F3R2_FB25_Pos)
    -
    4493#define CAN_F3R2_FB25 CAN_F3R2_FB25_Msk
    -
    4494#define CAN_F3R2_FB26_Pos (26U)
    -
    4495#define CAN_F3R2_FB26_Msk (0x1UL << CAN_F3R2_FB26_Pos)
    -
    4496#define CAN_F3R2_FB26 CAN_F3R2_FB26_Msk
    -
    4497#define CAN_F3R2_FB27_Pos (27U)
    -
    4498#define CAN_F3R2_FB27_Msk (0x1UL << CAN_F3R2_FB27_Pos)
    -
    4499#define CAN_F3R2_FB27 CAN_F3R2_FB27_Msk
    -
    4500#define CAN_F3R2_FB28_Pos (28U)
    -
    4501#define CAN_F3R2_FB28_Msk (0x1UL << CAN_F3R2_FB28_Pos)
    -
    4502#define CAN_F3R2_FB28 CAN_F3R2_FB28_Msk
    -
    4503#define CAN_F3R2_FB29_Pos (29U)
    -
    4504#define CAN_F3R2_FB29_Msk (0x1UL << CAN_F3R2_FB29_Pos)
    -
    4505#define CAN_F3R2_FB29 CAN_F3R2_FB29_Msk
    -
    4506#define CAN_F3R2_FB30_Pos (30U)
    -
    4507#define CAN_F3R2_FB30_Msk (0x1UL << CAN_F3R2_FB30_Pos)
    -
    4508#define CAN_F3R2_FB30 CAN_F3R2_FB30_Msk
    -
    4509#define CAN_F3R2_FB31_Pos (31U)
    -
    4510#define CAN_F3R2_FB31_Msk (0x1UL << CAN_F3R2_FB31_Pos)
    -
    4511#define CAN_F3R2_FB31 CAN_F3R2_FB31_Msk
    -
    4513/******************* Bit definition for CAN_F4R2 register *******************/
    -
    4514#define CAN_F4R2_FB0_Pos (0U)
    -
    4515#define CAN_F4R2_FB0_Msk (0x1UL << CAN_F4R2_FB0_Pos)
    -
    4516#define CAN_F4R2_FB0 CAN_F4R2_FB0_Msk
    -
    4517#define CAN_F4R2_FB1_Pos (1U)
    -
    4518#define CAN_F4R2_FB1_Msk (0x1UL << CAN_F4R2_FB1_Pos)
    -
    4519#define CAN_F4R2_FB1 CAN_F4R2_FB1_Msk
    -
    4520#define CAN_F4R2_FB2_Pos (2U)
    -
    4521#define CAN_F4R2_FB2_Msk (0x1UL << CAN_F4R2_FB2_Pos)
    -
    4522#define CAN_F4R2_FB2 CAN_F4R2_FB2_Msk
    -
    4523#define CAN_F4R2_FB3_Pos (3U)
    -
    4524#define CAN_F4R2_FB3_Msk (0x1UL << CAN_F4R2_FB3_Pos)
    -
    4525#define CAN_F4R2_FB3 CAN_F4R2_FB3_Msk
    -
    4526#define CAN_F4R2_FB4_Pos (4U)
    -
    4527#define CAN_F4R2_FB4_Msk (0x1UL << CAN_F4R2_FB4_Pos)
    -
    4528#define CAN_F4R2_FB4 CAN_F4R2_FB4_Msk
    -
    4529#define CAN_F4R2_FB5_Pos (5U)
    -
    4530#define CAN_F4R2_FB5_Msk (0x1UL << CAN_F4R2_FB5_Pos)
    -
    4531#define CAN_F4R2_FB5 CAN_F4R2_FB5_Msk
    -
    4532#define CAN_F4R2_FB6_Pos (6U)
    -
    4533#define CAN_F4R2_FB6_Msk (0x1UL << CAN_F4R2_FB6_Pos)
    -
    4534#define CAN_F4R2_FB6 CAN_F4R2_FB6_Msk
    -
    4535#define CAN_F4R2_FB7_Pos (7U)
    -
    4536#define CAN_F4R2_FB7_Msk (0x1UL << CAN_F4R2_FB7_Pos)
    -
    4537#define CAN_F4R2_FB7 CAN_F4R2_FB7_Msk
    -
    4538#define CAN_F4R2_FB8_Pos (8U)
    -
    4539#define CAN_F4R2_FB8_Msk (0x1UL << CAN_F4R2_FB8_Pos)
    -
    4540#define CAN_F4R2_FB8 CAN_F4R2_FB8_Msk
    -
    4541#define CAN_F4R2_FB9_Pos (9U)
    -
    4542#define CAN_F4R2_FB9_Msk (0x1UL << CAN_F4R2_FB9_Pos)
    -
    4543#define CAN_F4R2_FB9 CAN_F4R2_FB9_Msk
    -
    4544#define CAN_F4R2_FB10_Pos (10U)
    -
    4545#define CAN_F4R2_FB10_Msk (0x1UL << CAN_F4R2_FB10_Pos)
    -
    4546#define CAN_F4R2_FB10 CAN_F4R2_FB10_Msk
    -
    4547#define CAN_F4R2_FB11_Pos (11U)
    -
    4548#define CAN_F4R2_FB11_Msk (0x1UL << CAN_F4R2_FB11_Pos)
    -
    4549#define CAN_F4R2_FB11 CAN_F4R2_FB11_Msk
    -
    4550#define CAN_F4R2_FB12_Pos (12U)
    -
    4551#define CAN_F4R2_FB12_Msk (0x1UL << CAN_F4R2_FB12_Pos)
    -
    4552#define CAN_F4R2_FB12 CAN_F4R2_FB12_Msk
    -
    4553#define CAN_F4R2_FB13_Pos (13U)
    -
    4554#define CAN_F4R2_FB13_Msk (0x1UL << CAN_F4R2_FB13_Pos)
    -
    4555#define CAN_F4R2_FB13 CAN_F4R2_FB13_Msk
    -
    4556#define CAN_F4R2_FB14_Pos (14U)
    -
    4557#define CAN_F4R2_FB14_Msk (0x1UL << CAN_F4R2_FB14_Pos)
    -
    4558#define CAN_F4R2_FB14 CAN_F4R2_FB14_Msk
    -
    4559#define CAN_F4R2_FB15_Pos (15U)
    -
    4560#define CAN_F4R2_FB15_Msk (0x1UL << CAN_F4R2_FB15_Pos)
    -
    4561#define CAN_F4R2_FB15 CAN_F4R2_FB15_Msk
    -
    4562#define CAN_F4R2_FB16_Pos (16U)
    -
    4563#define CAN_F4R2_FB16_Msk (0x1UL << CAN_F4R2_FB16_Pos)
    -
    4564#define CAN_F4R2_FB16 CAN_F4R2_FB16_Msk
    -
    4565#define CAN_F4R2_FB17_Pos (17U)
    -
    4566#define CAN_F4R2_FB17_Msk (0x1UL << CAN_F4R2_FB17_Pos)
    -
    4567#define CAN_F4R2_FB17 CAN_F4R2_FB17_Msk
    -
    4568#define CAN_F4R2_FB18_Pos (18U)
    -
    4569#define CAN_F4R2_FB18_Msk (0x1UL << CAN_F4R2_FB18_Pos)
    -
    4570#define CAN_F4R2_FB18 CAN_F4R2_FB18_Msk
    -
    4571#define CAN_F4R2_FB19_Pos (19U)
    -
    4572#define CAN_F4R2_FB19_Msk (0x1UL << CAN_F4R2_FB19_Pos)
    -
    4573#define CAN_F4R2_FB19 CAN_F4R2_FB19_Msk
    -
    4574#define CAN_F4R2_FB20_Pos (20U)
    -
    4575#define CAN_F4R2_FB20_Msk (0x1UL << CAN_F4R2_FB20_Pos)
    -
    4576#define CAN_F4R2_FB20 CAN_F4R2_FB20_Msk
    -
    4577#define CAN_F4R2_FB21_Pos (21U)
    -
    4578#define CAN_F4R2_FB21_Msk (0x1UL << CAN_F4R2_FB21_Pos)
    -
    4579#define CAN_F4R2_FB21 CAN_F4R2_FB21_Msk
    -
    4580#define CAN_F4R2_FB22_Pos (22U)
    -
    4581#define CAN_F4R2_FB22_Msk (0x1UL << CAN_F4R2_FB22_Pos)
    -
    4582#define CAN_F4R2_FB22 CAN_F4R2_FB22_Msk
    -
    4583#define CAN_F4R2_FB23_Pos (23U)
    -
    4584#define CAN_F4R2_FB23_Msk (0x1UL << CAN_F4R2_FB23_Pos)
    -
    4585#define CAN_F4R2_FB23 CAN_F4R2_FB23_Msk
    -
    4586#define CAN_F4R2_FB24_Pos (24U)
    -
    4587#define CAN_F4R2_FB24_Msk (0x1UL << CAN_F4R2_FB24_Pos)
    -
    4588#define CAN_F4R2_FB24 CAN_F4R2_FB24_Msk
    -
    4589#define CAN_F4R2_FB25_Pos (25U)
    -
    4590#define CAN_F4R2_FB25_Msk (0x1UL << CAN_F4R2_FB25_Pos)
    -
    4591#define CAN_F4R2_FB25 CAN_F4R2_FB25_Msk
    -
    4592#define CAN_F4R2_FB26_Pos (26U)
    -
    4593#define CAN_F4R2_FB26_Msk (0x1UL << CAN_F4R2_FB26_Pos)
    -
    4594#define CAN_F4R2_FB26 CAN_F4R2_FB26_Msk
    -
    4595#define CAN_F4R2_FB27_Pos (27U)
    -
    4596#define CAN_F4R2_FB27_Msk (0x1UL << CAN_F4R2_FB27_Pos)
    -
    4597#define CAN_F4R2_FB27 CAN_F4R2_FB27_Msk
    -
    4598#define CAN_F4R2_FB28_Pos (28U)
    -
    4599#define CAN_F4R2_FB28_Msk (0x1UL << CAN_F4R2_FB28_Pos)
    -
    4600#define CAN_F4R2_FB28 CAN_F4R2_FB28_Msk
    -
    4601#define CAN_F4R2_FB29_Pos (29U)
    -
    4602#define CAN_F4R2_FB29_Msk (0x1UL << CAN_F4R2_FB29_Pos)
    -
    4603#define CAN_F4R2_FB29 CAN_F4R2_FB29_Msk
    -
    4604#define CAN_F4R2_FB30_Pos (30U)
    -
    4605#define CAN_F4R2_FB30_Msk (0x1UL << CAN_F4R2_FB30_Pos)
    -
    4606#define CAN_F4R2_FB30 CAN_F4R2_FB30_Msk
    -
    4607#define CAN_F4R2_FB31_Pos (31U)
    -
    4608#define CAN_F4R2_FB31_Msk (0x1UL << CAN_F4R2_FB31_Pos)
    -
    4609#define CAN_F4R2_FB31 CAN_F4R2_FB31_Msk
    -
    4611/******************* Bit definition for CAN_F5R2 register *******************/
    -
    4612#define CAN_F5R2_FB0_Pos (0U)
    -
    4613#define CAN_F5R2_FB0_Msk (0x1UL << CAN_F5R2_FB0_Pos)
    -
    4614#define CAN_F5R2_FB0 CAN_F5R2_FB0_Msk
    -
    4615#define CAN_F5R2_FB1_Pos (1U)
    -
    4616#define CAN_F5R2_FB1_Msk (0x1UL << CAN_F5R2_FB1_Pos)
    -
    4617#define CAN_F5R2_FB1 CAN_F5R2_FB1_Msk
    -
    4618#define CAN_F5R2_FB2_Pos (2U)
    -
    4619#define CAN_F5R2_FB2_Msk (0x1UL << CAN_F5R2_FB2_Pos)
    -
    4620#define CAN_F5R2_FB2 CAN_F5R2_FB2_Msk
    -
    4621#define CAN_F5R2_FB3_Pos (3U)
    -
    4622#define CAN_F5R2_FB3_Msk (0x1UL << CAN_F5R2_FB3_Pos)
    -
    4623#define CAN_F5R2_FB3 CAN_F5R2_FB3_Msk
    -
    4624#define CAN_F5R2_FB4_Pos (4U)
    -
    4625#define CAN_F5R2_FB4_Msk (0x1UL << CAN_F5R2_FB4_Pos)
    -
    4626#define CAN_F5R2_FB4 CAN_F5R2_FB4_Msk
    -
    4627#define CAN_F5R2_FB5_Pos (5U)
    -
    4628#define CAN_F5R2_FB5_Msk (0x1UL << CAN_F5R2_FB5_Pos)
    -
    4629#define CAN_F5R2_FB5 CAN_F5R2_FB5_Msk
    -
    4630#define CAN_F5R2_FB6_Pos (6U)
    -
    4631#define CAN_F5R2_FB6_Msk (0x1UL << CAN_F5R2_FB6_Pos)
    -
    4632#define CAN_F5R2_FB6 CAN_F5R2_FB6_Msk
    -
    4633#define CAN_F5R2_FB7_Pos (7U)
    -
    4634#define CAN_F5R2_FB7_Msk (0x1UL << CAN_F5R2_FB7_Pos)
    -
    4635#define CAN_F5R2_FB7 CAN_F5R2_FB7_Msk
    -
    4636#define CAN_F5R2_FB8_Pos (8U)
    -
    4637#define CAN_F5R2_FB8_Msk (0x1UL << CAN_F5R2_FB8_Pos)
    -
    4638#define CAN_F5R2_FB8 CAN_F5R2_FB8_Msk
    -
    4639#define CAN_F5R2_FB9_Pos (9U)
    -
    4640#define CAN_F5R2_FB9_Msk (0x1UL << CAN_F5R2_FB9_Pos)
    -
    4641#define CAN_F5R2_FB9 CAN_F5R2_FB9_Msk
    -
    4642#define CAN_F5R2_FB10_Pos (10U)
    -
    4643#define CAN_F5R2_FB10_Msk (0x1UL << CAN_F5R2_FB10_Pos)
    -
    4644#define CAN_F5R2_FB10 CAN_F5R2_FB10_Msk
    -
    4645#define CAN_F5R2_FB11_Pos (11U)
    -
    4646#define CAN_F5R2_FB11_Msk (0x1UL << CAN_F5R2_FB11_Pos)
    -
    4647#define CAN_F5R2_FB11 CAN_F5R2_FB11_Msk
    -
    4648#define CAN_F5R2_FB12_Pos (12U)
    -
    4649#define CAN_F5R2_FB12_Msk (0x1UL << CAN_F5R2_FB12_Pos)
    -
    4650#define CAN_F5R2_FB12 CAN_F5R2_FB12_Msk
    -
    4651#define CAN_F5R2_FB13_Pos (13U)
    -
    4652#define CAN_F5R2_FB13_Msk (0x1UL << CAN_F5R2_FB13_Pos)
    -
    4653#define CAN_F5R2_FB13 CAN_F5R2_FB13_Msk
    -
    4654#define CAN_F5R2_FB14_Pos (14U)
    -
    4655#define CAN_F5R2_FB14_Msk (0x1UL << CAN_F5R2_FB14_Pos)
    -
    4656#define CAN_F5R2_FB14 CAN_F5R2_FB14_Msk
    -
    4657#define CAN_F5R2_FB15_Pos (15U)
    -
    4658#define CAN_F5R2_FB15_Msk (0x1UL << CAN_F5R2_FB15_Pos)
    -
    4659#define CAN_F5R2_FB15 CAN_F5R2_FB15_Msk
    -
    4660#define CAN_F5R2_FB16_Pos (16U)
    -
    4661#define CAN_F5R2_FB16_Msk (0x1UL << CAN_F5R2_FB16_Pos)
    -
    4662#define CAN_F5R2_FB16 CAN_F5R2_FB16_Msk
    -
    4663#define CAN_F5R2_FB17_Pos (17U)
    -
    4664#define CAN_F5R2_FB17_Msk (0x1UL << CAN_F5R2_FB17_Pos)
    -
    4665#define CAN_F5R2_FB17 CAN_F5R2_FB17_Msk
    -
    4666#define CAN_F5R2_FB18_Pos (18U)
    -
    4667#define CAN_F5R2_FB18_Msk (0x1UL << CAN_F5R2_FB18_Pos)
    -
    4668#define CAN_F5R2_FB18 CAN_F5R2_FB18_Msk
    -
    4669#define CAN_F5R2_FB19_Pos (19U)
    -
    4670#define CAN_F5R2_FB19_Msk (0x1UL << CAN_F5R2_FB19_Pos)
    -
    4671#define CAN_F5R2_FB19 CAN_F5R2_FB19_Msk
    -
    4672#define CAN_F5R2_FB20_Pos (20U)
    -
    4673#define CAN_F5R2_FB20_Msk (0x1UL << CAN_F5R2_FB20_Pos)
    -
    4674#define CAN_F5R2_FB20 CAN_F5R2_FB20_Msk
    -
    4675#define CAN_F5R2_FB21_Pos (21U)
    -
    4676#define CAN_F5R2_FB21_Msk (0x1UL << CAN_F5R2_FB21_Pos)
    -
    4677#define CAN_F5R2_FB21 CAN_F5R2_FB21_Msk
    -
    4678#define CAN_F5R2_FB22_Pos (22U)
    -
    4679#define CAN_F5R2_FB22_Msk (0x1UL << CAN_F5R2_FB22_Pos)
    -
    4680#define CAN_F5R2_FB22 CAN_F5R2_FB22_Msk
    -
    4681#define CAN_F5R2_FB23_Pos (23U)
    -
    4682#define CAN_F5R2_FB23_Msk (0x1UL << CAN_F5R2_FB23_Pos)
    -
    4683#define CAN_F5R2_FB23 CAN_F5R2_FB23_Msk
    -
    4684#define CAN_F5R2_FB24_Pos (24U)
    -
    4685#define CAN_F5R2_FB24_Msk (0x1UL << CAN_F5R2_FB24_Pos)
    -
    4686#define CAN_F5R2_FB24 CAN_F5R2_FB24_Msk
    -
    4687#define CAN_F5R2_FB25_Pos (25U)
    -
    4688#define CAN_F5R2_FB25_Msk (0x1UL << CAN_F5R2_FB25_Pos)
    -
    4689#define CAN_F5R2_FB25 CAN_F5R2_FB25_Msk
    -
    4690#define CAN_F5R2_FB26_Pos (26U)
    -
    4691#define CAN_F5R2_FB26_Msk (0x1UL << CAN_F5R2_FB26_Pos)
    -
    4692#define CAN_F5R2_FB26 CAN_F5R2_FB26_Msk
    -
    4693#define CAN_F5R2_FB27_Pos (27U)
    -
    4694#define CAN_F5R2_FB27_Msk (0x1UL << CAN_F5R2_FB27_Pos)
    -
    4695#define CAN_F5R2_FB27 CAN_F5R2_FB27_Msk
    -
    4696#define CAN_F5R2_FB28_Pos (28U)
    -
    4697#define CAN_F5R2_FB28_Msk (0x1UL << CAN_F5R2_FB28_Pos)
    -
    4698#define CAN_F5R2_FB28 CAN_F5R2_FB28_Msk
    -
    4699#define CAN_F5R2_FB29_Pos (29U)
    -
    4700#define CAN_F5R2_FB29_Msk (0x1UL << CAN_F5R2_FB29_Pos)
    -
    4701#define CAN_F5R2_FB29 CAN_F5R2_FB29_Msk
    -
    4702#define CAN_F5R2_FB30_Pos (30U)
    -
    4703#define CAN_F5R2_FB30_Msk (0x1UL << CAN_F5R2_FB30_Pos)
    -
    4704#define CAN_F5R2_FB30 CAN_F5R2_FB30_Msk
    -
    4705#define CAN_F5R2_FB31_Pos (31U)
    -
    4706#define CAN_F5R2_FB31_Msk (0x1UL << CAN_F5R2_FB31_Pos)
    -
    4707#define CAN_F5R2_FB31 CAN_F5R2_FB31_Msk
    -
    4709/******************* Bit definition for CAN_F6R2 register *******************/
    -
    4710#define CAN_F6R2_FB0_Pos (0U)
    -
    4711#define CAN_F6R2_FB0_Msk (0x1UL << CAN_F6R2_FB0_Pos)
    -
    4712#define CAN_F6R2_FB0 CAN_F6R2_FB0_Msk
    -
    4713#define CAN_F6R2_FB1_Pos (1U)
    -
    4714#define CAN_F6R2_FB1_Msk (0x1UL << CAN_F6R2_FB1_Pos)
    -
    4715#define CAN_F6R2_FB1 CAN_F6R2_FB1_Msk
    -
    4716#define CAN_F6R2_FB2_Pos (2U)
    -
    4717#define CAN_F6R2_FB2_Msk (0x1UL << CAN_F6R2_FB2_Pos)
    -
    4718#define CAN_F6R2_FB2 CAN_F6R2_FB2_Msk
    -
    4719#define CAN_F6R2_FB3_Pos (3U)
    -
    4720#define CAN_F6R2_FB3_Msk (0x1UL << CAN_F6R2_FB3_Pos)
    -
    4721#define CAN_F6R2_FB3 CAN_F6R2_FB3_Msk
    -
    4722#define CAN_F6R2_FB4_Pos (4U)
    -
    4723#define CAN_F6R2_FB4_Msk (0x1UL << CAN_F6R2_FB4_Pos)
    -
    4724#define CAN_F6R2_FB4 CAN_F6R2_FB4_Msk
    -
    4725#define CAN_F6R2_FB5_Pos (5U)
    -
    4726#define CAN_F6R2_FB5_Msk (0x1UL << CAN_F6R2_FB5_Pos)
    -
    4727#define CAN_F6R2_FB5 CAN_F6R2_FB5_Msk
    -
    4728#define CAN_F6R2_FB6_Pos (6U)
    -
    4729#define CAN_F6R2_FB6_Msk (0x1UL << CAN_F6R2_FB6_Pos)
    -
    4730#define CAN_F6R2_FB6 CAN_F6R2_FB6_Msk
    -
    4731#define CAN_F6R2_FB7_Pos (7U)
    -
    4732#define CAN_F6R2_FB7_Msk (0x1UL << CAN_F6R2_FB7_Pos)
    -
    4733#define CAN_F6R2_FB7 CAN_F6R2_FB7_Msk
    -
    4734#define CAN_F6R2_FB8_Pos (8U)
    -
    4735#define CAN_F6R2_FB8_Msk (0x1UL << CAN_F6R2_FB8_Pos)
    -
    4736#define CAN_F6R2_FB8 CAN_F6R2_FB8_Msk
    -
    4737#define CAN_F6R2_FB9_Pos (9U)
    -
    4738#define CAN_F6R2_FB9_Msk (0x1UL << CAN_F6R2_FB9_Pos)
    -
    4739#define CAN_F6R2_FB9 CAN_F6R2_FB9_Msk
    -
    4740#define CAN_F6R2_FB10_Pos (10U)
    -
    4741#define CAN_F6R2_FB10_Msk (0x1UL << CAN_F6R2_FB10_Pos)
    -
    4742#define CAN_F6R2_FB10 CAN_F6R2_FB10_Msk
    -
    4743#define CAN_F6R2_FB11_Pos (11U)
    -
    4744#define CAN_F6R2_FB11_Msk (0x1UL << CAN_F6R2_FB11_Pos)
    -
    4745#define CAN_F6R2_FB11 CAN_F6R2_FB11_Msk
    -
    4746#define CAN_F6R2_FB12_Pos (12U)
    -
    4747#define CAN_F6R2_FB12_Msk (0x1UL << CAN_F6R2_FB12_Pos)
    -
    4748#define CAN_F6R2_FB12 CAN_F6R2_FB12_Msk
    -
    4749#define CAN_F6R2_FB13_Pos (13U)
    -
    4750#define CAN_F6R2_FB13_Msk (0x1UL << CAN_F6R2_FB13_Pos)
    -
    4751#define CAN_F6R2_FB13 CAN_F6R2_FB13_Msk
    -
    4752#define CAN_F6R2_FB14_Pos (14U)
    -
    4753#define CAN_F6R2_FB14_Msk (0x1UL << CAN_F6R2_FB14_Pos)
    -
    4754#define CAN_F6R2_FB14 CAN_F6R2_FB14_Msk
    -
    4755#define CAN_F6R2_FB15_Pos (15U)
    -
    4756#define CAN_F6R2_FB15_Msk (0x1UL << CAN_F6R2_FB15_Pos)
    -
    4757#define CAN_F6R2_FB15 CAN_F6R2_FB15_Msk
    -
    4758#define CAN_F6R2_FB16_Pos (16U)
    -
    4759#define CAN_F6R2_FB16_Msk (0x1UL << CAN_F6R2_FB16_Pos)
    -
    4760#define CAN_F6R2_FB16 CAN_F6R2_FB16_Msk
    -
    4761#define CAN_F6R2_FB17_Pos (17U)
    -
    4762#define CAN_F6R2_FB17_Msk (0x1UL << CAN_F6R2_FB17_Pos)
    -
    4763#define CAN_F6R2_FB17 CAN_F6R2_FB17_Msk
    -
    4764#define CAN_F6R2_FB18_Pos (18U)
    -
    4765#define CAN_F6R2_FB18_Msk (0x1UL << CAN_F6R2_FB18_Pos)
    -
    4766#define CAN_F6R2_FB18 CAN_F6R2_FB18_Msk
    -
    4767#define CAN_F6R2_FB19_Pos (19U)
    -
    4768#define CAN_F6R2_FB19_Msk (0x1UL << CAN_F6R2_FB19_Pos)
    -
    4769#define CAN_F6R2_FB19 CAN_F6R2_FB19_Msk
    -
    4770#define CAN_F6R2_FB20_Pos (20U)
    -
    4771#define CAN_F6R2_FB20_Msk (0x1UL << CAN_F6R2_FB20_Pos)
    -
    4772#define CAN_F6R2_FB20 CAN_F6R2_FB20_Msk
    -
    4773#define CAN_F6R2_FB21_Pos (21U)
    -
    4774#define CAN_F6R2_FB21_Msk (0x1UL << CAN_F6R2_FB21_Pos)
    -
    4775#define CAN_F6R2_FB21 CAN_F6R2_FB21_Msk
    -
    4776#define CAN_F6R2_FB22_Pos (22U)
    -
    4777#define CAN_F6R2_FB22_Msk (0x1UL << CAN_F6R2_FB22_Pos)
    -
    4778#define CAN_F6R2_FB22 CAN_F6R2_FB22_Msk
    -
    4779#define CAN_F6R2_FB23_Pos (23U)
    -
    4780#define CAN_F6R2_FB23_Msk (0x1UL << CAN_F6R2_FB23_Pos)
    -
    4781#define CAN_F6R2_FB23 CAN_F6R2_FB23_Msk
    -
    4782#define CAN_F6R2_FB24_Pos (24U)
    -
    4783#define CAN_F6R2_FB24_Msk (0x1UL << CAN_F6R2_FB24_Pos)
    -
    4784#define CAN_F6R2_FB24 CAN_F6R2_FB24_Msk
    -
    4785#define CAN_F6R2_FB25_Pos (25U)
    -
    4786#define CAN_F6R2_FB25_Msk (0x1UL << CAN_F6R2_FB25_Pos)
    -
    4787#define CAN_F6R2_FB25 CAN_F6R2_FB25_Msk
    -
    4788#define CAN_F6R2_FB26_Pos (26U)
    -
    4789#define CAN_F6R2_FB26_Msk (0x1UL << CAN_F6R2_FB26_Pos)
    -
    4790#define CAN_F6R2_FB26 CAN_F6R2_FB26_Msk
    -
    4791#define CAN_F6R2_FB27_Pos (27U)
    -
    4792#define CAN_F6R2_FB27_Msk (0x1UL << CAN_F6R2_FB27_Pos)
    -
    4793#define CAN_F6R2_FB27 CAN_F6R2_FB27_Msk
    -
    4794#define CAN_F6R2_FB28_Pos (28U)
    -
    4795#define CAN_F6R2_FB28_Msk (0x1UL << CAN_F6R2_FB28_Pos)
    -
    4796#define CAN_F6R2_FB28 CAN_F6R2_FB28_Msk
    -
    4797#define CAN_F6R2_FB29_Pos (29U)
    -
    4798#define CAN_F6R2_FB29_Msk (0x1UL << CAN_F6R2_FB29_Pos)
    -
    4799#define CAN_F6R2_FB29 CAN_F6R2_FB29_Msk
    -
    4800#define CAN_F6R2_FB30_Pos (30U)
    -
    4801#define CAN_F6R2_FB30_Msk (0x1UL << CAN_F6R2_FB30_Pos)
    -
    4802#define CAN_F6R2_FB30 CAN_F6R2_FB30_Msk
    -
    4803#define CAN_F6R2_FB31_Pos (31U)
    -
    4804#define CAN_F6R2_FB31_Msk (0x1UL << CAN_F6R2_FB31_Pos)
    -
    4805#define CAN_F6R2_FB31 CAN_F6R2_FB31_Msk
    -
    4807/******************* Bit definition for CAN_F7R2 register *******************/
    -
    4808#define CAN_F7R2_FB0_Pos (0U)
    -
    4809#define CAN_F7R2_FB0_Msk (0x1UL << CAN_F7R2_FB0_Pos)
    -
    4810#define CAN_F7R2_FB0 CAN_F7R2_FB0_Msk
    -
    4811#define CAN_F7R2_FB1_Pos (1U)
    -
    4812#define CAN_F7R2_FB1_Msk (0x1UL << CAN_F7R2_FB1_Pos)
    -
    4813#define CAN_F7R2_FB1 CAN_F7R2_FB1_Msk
    -
    4814#define CAN_F7R2_FB2_Pos (2U)
    -
    4815#define CAN_F7R2_FB2_Msk (0x1UL << CAN_F7R2_FB2_Pos)
    -
    4816#define CAN_F7R2_FB2 CAN_F7R2_FB2_Msk
    -
    4817#define CAN_F7R2_FB3_Pos (3U)
    -
    4818#define CAN_F7R2_FB3_Msk (0x1UL << CAN_F7R2_FB3_Pos)
    -
    4819#define CAN_F7R2_FB3 CAN_F7R2_FB3_Msk
    -
    4820#define CAN_F7R2_FB4_Pos (4U)
    -
    4821#define CAN_F7R2_FB4_Msk (0x1UL << CAN_F7R2_FB4_Pos)
    -
    4822#define CAN_F7R2_FB4 CAN_F7R2_FB4_Msk
    -
    4823#define CAN_F7R2_FB5_Pos (5U)
    -
    4824#define CAN_F7R2_FB5_Msk (0x1UL << CAN_F7R2_FB5_Pos)
    -
    4825#define CAN_F7R2_FB5 CAN_F7R2_FB5_Msk
    -
    4826#define CAN_F7R2_FB6_Pos (6U)
    -
    4827#define CAN_F7R2_FB6_Msk (0x1UL << CAN_F7R2_FB6_Pos)
    -
    4828#define CAN_F7R2_FB6 CAN_F7R2_FB6_Msk
    -
    4829#define CAN_F7R2_FB7_Pos (7U)
    -
    4830#define CAN_F7R2_FB7_Msk (0x1UL << CAN_F7R2_FB7_Pos)
    -
    4831#define CAN_F7R2_FB7 CAN_F7R2_FB7_Msk
    -
    4832#define CAN_F7R2_FB8_Pos (8U)
    -
    4833#define CAN_F7R2_FB8_Msk (0x1UL << CAN_F7R2_FB8_Pos)
    -
    4834#define CAN_F7R2_FB8 CAN_F7R2_FB8_Msk
    -
    4835#define CAN_F7R2_FB9_Pos (9U)
    -
    4836#define CAN_F7R2_FB9_Msk (0x1UL << CAN_F7R2_FB9_Pos)
    -
    4837#define CAN_F7R2_FB9 CAN_F7R2_FB9_Msk
    -
    4838#define CAN_F7R2_FB10_Pos (10U)
    -
    4839#define CAN_F7R2_FB10_Msk (0x1UL << CAN_F7R2_FB10_Pos)
    -
    4840#define CAN_F7R2_FB10 CAN_F7R2_FB10_Msk
    -
    4841#define CAN_F7R2_FB11_Pos (11U)
    -
    4842#define CAN_F7R2_FB11_Msk (0x1UL << CAN_F7R2_FB11_Pos)
    -
    4843#define CAN_F7R2_FB11 CAN_F7R2_FB11_Msk
    -
    4844#define CAN_F7R2_FB12_Pos (12U)
    -
    4845#define CAN_F7R2_FB12_Msk (0x1UL << CAN_F7R2_FB12_Pos)
    -
    4846#define CAN_F7R2_FB12 CAN_F7R2_FB12_Msk
    -
    4847#define CAN_F7R2_FB13_Pos (13U)
    -
    4848#define CAN_F7R2_FB13_Msk (0x1UL << CAN_F7R2_FB13_Pos)
    -
    4849#define CAN_F7R2_FB13 CAN_F7R2_FB13_Msk
    -
    4850#define CAN_F7R2_FB14_Pos (14U)
    -
    4851#define CAN_F7R2_FB14_Msk (0x1UL << CAN_F7R2_FB14_Pos)
    -
    4852#define CAN_F7R2_FB14 CAN_F7R2_FB14_Msk
    -
    4853#define CAN_F7R2_FB15_Pos (15U)
    -
    4854#define CAN_F7R2_FB15_Msk (0x1UL << CAN_F7R2_FB15_Pos)
    -
    4855#define CAN_F7R2_FB15 CAN_F7R2_FB15_Msk
    -
    4856#define CAN_F7R2_FB16_Pos (16U)
    -
    4857#define CAN_F7R2_FB16_Msk (0x1UL << CAN_F7R2_FB16_Pos)
    -
    4858#define CAN_F7R2_FB16 CAN_F7R2_FB16_Msk
    -
    4859#define CAN_F7R2_FB17_Pos (17U)
    -
    4860#define CAN_F7R2_FB17_Msk (0x1UL << CAN_F7R2_FB17_Pos)
    -
    4861#define CAN_F7R2_FB17 CAN_F7R2_FB17_Msk
    -
    4862#define CAN_F7R2_FB18_Pos (18U)
    -
    4863#define CAN_F7R2_FB18_Msk (0x1UL << CAN_F7R2_FB18_Pos)
    -
    4864#define CAN_F7R2_FB18 CAN_F7R2_FB18_Msk
    -
    4865#define CAN_F7R2_FB19_Pos (19U)
    -
    4866#define CAN_F7R2_FB19_Msk (0x1UL << CAN_F7R2_FB19_Pos)
    -
    4867#define CAN_F7R2_FB19 CAN_F7R2_FB19_Msk
    -
    4868#define CAN_F7R2_FB20_Pos (20U)
    -
    4869#define CAN_F7R2_FB20_Msk (0x1UL << CAN_F7R2_FB20_Pos)
    -
    4870#define CAN_F7R2_FB20 CAN_F7R2_FB20_Msk
    -
    4871#define CAN_F7R2_FB21_Pos (21U)
    -
    4872#define CAN_F7R2_FB21_Msk (0x1UL << CAN_F7R2_FB21_Pos)
    -
    4873#define CAN_F7R2_FB21 CAN_F7R2_FB21_Msk
    -
    4874#define CAN_F7R2_FB22_Pos (22U)
    -
    4875#define CAN_F7R2_FB22_Msk (0x1UL << CAN_F7R2_FB22_Pos)
    -
    4876#define CAN_F7R2_FB22 CAN_F7R2_FB22_Msk
    -
    4877#define CAN_F7R2_FB23_Pos (23U)
    -
    4878#define CAN_F7R2_FB23_Msk (0x1UL << CAN_F7R2_FB23_Pos)
    -
    4879#define CAN_F7R2_FB23 CAN_F7R2_FB23_Msk
    -
    4880#define CAN_F7R2_FB24_Pos (24U)
    -
    4881#define CAN_F7R2_FB24_Msk (0x1UL << CAN_F7R2_FB24_Pos)
    -
    4882#define CAN_F7R2_FB24 CAN_F7R2_FB24_Msk
    -
    4883#define CAN_F7R2_FB25_Pos (25U)
    -
    4884#define CAN_F7R2_FB25_Msk (0x1UL << CAN_F7R2_FB25_Pos)
    -
    4885#define CAN_F7R2_FB25 CAN_F7R2_FB25_Msk
    -
    4886#define CAN_F7R2_FB26_Pos (26U)
    -
    4887#define CAN_F7R2_FB26_Msk (0x1UL << CAN_F7R2_FB26_Pos)
    -
    4888#define CAN_F7R2_FB26 CAN_F7R2_FB26_Msk
    -
    4889#define CAN_F7R2_FB27_Pos (27U)
    -
    4890#define CAN_F7R2_FB27_Msk (0x1UL << CAN_F7R2_FB27_Pos)
    -
    4891#define CAN_F7R2_FB27 CAN_F7R2_FB27_Msk
    -
    4892#define CAN_F7R2_FB28_Pos (28U)
    -
    4893#define CAN_F7R2_FB28_Msk (0x1UL << CAN_F7R2_FB28_Pos)
    -
    4894#define CAN_F7R2_FB28 CAN_F7R2_FB28_Msk
    -
    4895#define CAN_F7R2_FB29_Pos (29U)
    -
    4896#define CAN_F7R2_FB29_Msk (0x1UL << CAN_F7R2_FB29_Pos)
    -
    4897#define CAN_F7R2_FB29 CAN_F7R2_FB29_Msk
    -
    4898#define CAN_F7R2_FB30_Pos (30U)
    -
    4899#define CAN_F7R2_FB30_Msk (0x1UL << CAN_F7R2_FB30_Pos)
    -
    4900#define CAN_F7R2_FB30 CAN_F7R2_FB30_Msk
    -
    4901#define CAN_F7R2_FB31_Pos (31U)
    -
    4902#define CAN_F7R2_FB31_Msk (0x1UL << CAN_F7R2_FB31_Pos)
    -
    4903#define CAN_F7R2_FB31 CAN_F7R2_FB31_Msk
    -
    4905/******************* Bit definition for CAN_F8R2 register *******************/
    -
    4906#define CAN_F8R2_FB0_Pos (0U)
    -
    4907#define CAN_F8R2_FB0_Msk (0x1UL << CAN_F8R2_FB0_Pos)
    -
    4908#define CAN_F8R2_FB0 CAN_F8R2_FB0_Msk
    -
    4909#define CAN_F8R2_FB1_Pos (1U)
    -
    4910#define CAN_F8R2_FB1_Msk (0x1UL << CAN_F8R2_FB1_Pos)
    -
    4911#define CAN_F8R2_FB1 CAN_F8R2_FB1_Msk
    -
    4912#define CAN_F8R2_FB2_Pos (2U)
    -
    4913#define CAN_F8R2_FB2_Msk (0x1UL << CAN_F8R2_FB2_Pos)
    -
    4914#define CAN_F8R2_FB2 CAN_F8R2_FB2_Msk
    -
    4915#define CAN_F8R2_FB3_Pos (3U)
    -
    4916#define CAN_F8R2_FB3_Msk (0x1UL << CAN_F8R2_FB3_Pos)
    -
    4917#define CAN_F8R2_FB3 CAN_F8R2_FB3_Msk
    -
    4918#define CAN_F8R2_FB4_Pos (4U)
    -
    4919#define CAN_F8R2_FB4_Msk (0x1UL << CAN_F8R2_FB4_Pos)
    -
    4920#define CAN_F8R2_FB4 CAN_F8R2_FB4_Msk
    -
    4921#define CAN_F8R2_FB5_Pos (5U)
    -
    4922#define CAN_F8R2_FB5_Msk (0x1UL << CAN_F8R2_FB5_Pos)
    -
    4923#define CAN_F8R2_FB5 CAN_F8R2_FB5_Msk
    -
    4924#define CAN_F8R2_FB6_Pos (6U)
    -
    4925#define CAN_F8R2_FB6_Msk (0x1UL << CAN_F8R2_FB6_Pos)
    -
    4926#define CAN_F8R2_FB6 CAN_F8R2_FB6_Msk
    -
    4927#define CAN_F8R2_FB7_Pos (7U)
    -
    4928#define CAN_F8R2_FB7_Msk (0x1UL << CAN_F8R2_FB7_Pos)
    -
    4929#define CAN_F8R2_FB7 CAN_F8R2_FB7_Msk
    -
    4930#define CAN_F8R2_FB8_Pos (8U)
    -
    4931#define CAN_F8R2_FB8_Msk (0x1UL << CAN_F8R2_FB8_Pos)
    -
    4932#define CAN_F8R2_FB8 CAN_F8R2_FB8_Msk
    -
    4933#define CAN_F8R2_FB9_Pos (9U)
    -
    4934#define CAN_F8R2_FB9_Msk (0x1UL << CAN_F8R2_FB9_Pos)
    -
    4935#define CAN_F8R2_FB9 CAN_F8R2_FB9_Msk
    -
    4936#define CAN_F8R2_FB10_Pos (10U)
    -
    4937#define CAN_F8R2_FB10_Msk (0x1UL << CAN_F8R2_FB10_Pos)
    -
    4938#define CAN_F8R2_FB10 CAN_F8R2_FB10_Msk
    -
    4939#define CAN_F8R2_FB11_Pos (11U)
    -
    4940#define CAN_F8R2_FB11_Msk (0x1UL << CAN_F8R2_FB11_Pos)
    -
    4941#define CAN_F8R2_FB11 CAN_F8R2_FB11_Msk
    -
    4942#define CAN_F8R2_FB12_Pos (12U)
    -
    4943#define CAN_F8R2_FB12_Msk (0x1UL << CAN_F8R2_FB12_Pos)
    -
    4944#define CAN_F8R2_FB12 CAN_F8R2_FB12_Msk
    -
    4945#define CAN_F8R2_FB13_Pos (13U)
    -
    4946#define CAN_F8R2_FB13_Msk (0x1UL << CAN_F8R2_FB13_Pos)
    -
    4947#define CAN_F8R2_FB13 CAN_F8R2_FB13_Msk
    -
    4948#define CAN_F8R2_FB14_Pos (14U)
    -
    4949#define CAN_F8R2_FB14_Msk (0x1UL << CAN_F8R2_FB14_Pos)
    -
    4950#define CAN_F8R2_FB14 CAN_F8R2_FB14_Msk
    -
    4951#define CAN_F8R2_FB15_Pos (15U)
    -
    4952#define CAN_F8R2_FB15_Msk (0x1UL << CAN_F8R2_FB15_Pos)
    -
    4953#define CAN_F8R2_FB15 CAN_F8R2_FB15_Msk
    -
    4954#define CAN_F8R2_FB16_Pos (16U)
    -
    4955#define CAN_F8R2_FB16_Msk (0x1UL << CAN_F8R2_FB16_Pos)
    -
    4956#define CAN_F8R2_FB16 CAN_F8R2_FB16_Msk
    -
    4957#define CAN_F8R2_FB17_Pos (17U)
    -
    4958#define CAN_F8R2_FB17_Msk (0x1UL << CAN_F8R2_FB17_Pos)
    -
    4959#define CAN_F8R2_FB17 CAN_F8R2_FB17_Msk
    -
    4960#define CAN_F8R2_FB18_Pos (18U)
    -
    4961#define CAN_F8R2_FB18_Msk (0x1UL << CAN_F8R2_FB18_Pos)
    -
    4962#define CAN_F8R2_FB18 CAN_F8R2_FB18_Msk
    -
    4963#define CAN_F8R2_FB19_Pos (19U)
    -
    4964#define CAN_F8R2_FB19_Msk (0x1UL << CAN_F8R2_FB19_Pos)
    -
    4965#define CAN_F8R2_FB19 CAN_F8R2_FB19_Msk
    -
    4966#define CAN_F8R2_FB20_Pos (20U)
    -
    4967#define CAN_F8R2_FB20_Msk (0x1UL << CAN_F8R2_FB20_Pos)
    -
    4968#define CAN_F8R2_FB20 CAN_F8R2_FB20_Msk
    -
    4969#define CAN_F8R2_FB21_Pos (21U)
    -
    4970#define CAN_F8R2_FB21_Msk (0x1UL << CAN_F8R2_FB21_Pos)
    -
    4971#define CAN_F8R2_FB21 CAN_F8R2_FB21_Msk
    -
    4972#define CAN_F8R2_FB22_Pos (22U)
    -
    4973#define CAN_F8R2_FB22_Msk (0x1UL << CAN_F8R2_FB22_Pos)
    -
    4974#define CAN_F8R2_FB22 CAN_F8R2_FB22_Msk
    -
    4975#define CAN_F8R2_FB23_Pos (23U)
    -
    4976#define CAN_F8R2_FB23_Msk (0x1UL << CAN_F8R2_FB23_Pos)
    -
    4977#define CAN_F8R2_FB23 CAN_F8R2_FB23_Msk
    -
    4978#define CAN_F8R2_FB24_Pos (24U)
    -
    4979#define CAN_F8R2_FB24_Msk (0x1UL << CAN_F8R2_FB24_Pos)
    -
    4980#define CAN_F8R2_FB24 CAN_F8R2_FB24_Msk
    -
    4981#define CAN_F8R2_FB25_Pos (25U)
    -
    4982#define CAN_F8R2_FB25_Msk (0x1UL << CAN_F8R2_FB25_Pos)
    -
    4983#define CAN_F8R2_FB25 CAN_F8R2_FB25_Msk
    -
    4984#define CAN_F8R2_FB26_Pos (26U)
    -
    4985#define CAN_F8R2_FB26_Msk (0x1UL << CAN_F8R2_FB26_Pos)
    -
    4986#define CAN_F8R2_FB26 CAN_F8R2_FB26_Msk
    -
    4987#define CAN_F8R2_FB27_Pos (27U)
    -
    4988#define CAN_F8R2_FB27_Msk (0x1UL << CAN_F8R2_FB27_Pos)
    -
    4989#define CAN_F8R2_FB27 CAN_F8R2_FB27_Msk
    -
    4990#define CAN_F8R2_FB28_Pos (28U)
    -
    4991#define CAN_F8R2_FB28_Msk (0x1UL << CAN_F8R2_FB28_Pos)
    -
    4992#define CAN_F8R2_FB28 CAN_F8R2_FB28_Msk
    -
    4993#define CAN_F8R2_FB29_Pos (29U)
    -
    4994#define CAN_F8R2_FB29_Msk (0x1UL << CAN_F8R2_FB29_Pos)
    -
    4995#define CAN_F8R2_FB29 CAN_F8R2_FB29_Msk
    -
    4996#define CAN_F8R2_FB30_Pos (30U)
    -
    4997#define CAN_F8R2_FB30_Msk (0x1UL << CAN_F8R2_FB30_Pos)
    -
    4998#define CAN_F8R2_FB30 CAN_F8R2_FB30_Msk
    -
    4999#define CAN_F8R2_FB31_Pos (31U)
    -
    5000#define CAN_F8R2_FB31_Msk (0x1UL << CAN_F8R2_FB31_Pos)
    -
    5001#define CAN_F8R2_FB31 CAN_F8R2_FB31_Msk
    -
    5003/******************* Bit definition for CAN_F9R2 register *******************/
    -
    5004#define CAN_F9R2_FB0_Pos (0U)
    -
    5005#define CAN_F9R2_FB0_Msk (0x1UL << CAN_F9R2_FB0_Pos)
    -
    5006#define CAN_F9R2_FB0 CAN_F9R2_FB0_Msk
    -
    5007#define CAN_F9R2_FB1_Pos (1U)
    -
    5008#define CAN_F9R2_FB1_Msk (0x1UL << CAN_F9R2_FB1_Pos)
    -
    5009#define CAN_F9R2_FB1 CAN_F9R2_FB1_Msk
    -
    5010#define CAN_F9R2_FB2_Pos (2U)
    -
    5011#define CAN_F9R2_FB2_Msk (0x1UL << CAN_F9R2_FB2_Pos)
    -
    5012#define CAN_F9R2_FB2 CAN_F9R2_FB2_Msk
    -
    5013#define CAN_F9R2_FB3_Pos (3U)
    -
    5014#define CAN_F9R2_FB3_Msk (0x1UL << CAN_F9R2_FB3_Pos)
    -
    5015#define CAN_F9R2_FB3 CAN_F9R2_FB3_Msk
    -
    5016#define CAN_F9R2_FB4_Pos (4U)
    -
    5017#define CAN_F9R2_FB4_Msk (0x1UL << CAN_F9R2_FB4_Pos)
    -
    5018#define CAN_F9R2_FB4 CAN_F9R2_FB4_Msk
    -
    5019#define CAN_F9R2_FB5_Pos (5U)
    -
    5020#define CAN_F9R2_FB5_Msk (0x1UL << CAN_F9R2_FB5_Pos)
    -
    5021#define CAN_F9R2_FB5 CAN_F9R2_FB5_Msk
    -
    5022#define CAN_F9R2_FB6_Pos (6U)
    -
    5023#define CAN_F9R2_FB6_Msk (0x1UL << CAN_F9R2_FB6_Pos)
    -
    5024#define CAN_F9R2_FB6 CAN_F9R2_FB6_Msk
    -
    5025#define CAN_F9R2_FB7_Pos (7U)
    -
    5026#define CAN_F9R2_FB7_Msk (0x1UL << CAN_F9R2_FB7_Pos)
    -
    5027#define CAN_F9R2_FB7 CAN_F9R2_FB7_Msk
    -
    5028#define CAN_F9R2_FB8_Pos (8U)
    -
    5029#define CAN_F9R2_FB8_Msk (0x1UL << CAN_F9R2_FB8_Pos)
    -
    5030#define CAN_F9R2_FB8 CAN_F9R2_FB8_Msk
    -
    5031#define CAN_F9R2_FB9_Pos (9U)
    -
    5032#define CAN_F9R2_FB9_Msk (0x1UL << CAN_F9R2_FB9_Pos)
    -
    5033#define CAN_F9R2_FB9 CAN_F9R2_FB9_Msk
    -
    5034#define CAN_F9R2_FB10_Pos (10U)
    -
    5035#define CAN_F9R2_FB10_Msk (0x1UL << CAN_F9R2_FB10_Pos)
    -
    5036#define CAN_F9R2_FB10 CAN_F9R2_FB10_Msk
    -
    5037#define CAN_F9R2_FB11_Pos (11U)
    -
    5038#define CAN_F9R2_FB11_Msk (0x1UL << CAN_F9R2_FB11_Pos)
    -
    5039#define CAN_F9R2_FB11 CAN_F9R2_FB11_Msk
    -
    5040#define CAN_F9R2_FB12_Pos (12U)
    -
    5041#define CAN_F9R2_FB12_Msk (0x1UL << CAN_F9R2_FB12_Pos)
    -
    5042#define CAN_F9R2_FB12 CAN_F9R2_FB12_Msk
    -
    5043#define CAN_F9R2_FB13_Pos (13U)
    -
    5044#define CAN_F9R2_FB13_Msk (0x1UL << CAN_F9R2_FB13_Pos)
    -
    5045#define CAN_F9R2_FB13 CAN_F9R2_FB13_Msk
    -
    5046#define CAN_F9R2_FB14_Pos (14U)
    -
    5047#define CAN_F9R2_FB14_Msk (0x1UL << CAN_F9R2_FB14_Pos)
    -
    5048#define CAN_F9R2_FB14 CAN_F9R2_FB14_Msk
    -
    5049#define CAN_F9R2_FB15_Pos (15U)
    -
    5050#define CAN_F9R2_FB15_Msk (0x1UL << CAN_F9R2_FB15_Pos)
    -
    5051#define CAN_F9R2_FB15 CAN_F9R2_FB15_Msk
    -
    5052#define CAN_F9R2_FB16_Pos (16U)
    -
    5053#define CAN_F9R2_FB16_Msk (0x1UL << CAN_F9R2_FB16_Pos)
    -
    5054#define CAN_F9R2_FB16 CAN_F9R2_FB16_Msk
    -
    5055#define CAN_F9R2_FB17_Pos (17U)
    -
    5056#define CAN_F9R2_FB17_Msk (0x1UL << CAN_F9R2_FB17_Pos)
    -
    5057#define CAN_F9R2_FB17 CAN_F9R2_FB17_Msk
    -
    5058#define CAN_F9R2_FB18_Pos (18U)
    -
    5059#define CAN_F9R2_FB18_Msk (0x1UL << CAN_F9R2_FB18_Pos)
    -
    5060#define CAN_F9R2_FB18 CAN_F9R2_FB18_Msk
    -
    5061#define CAN_F9R2_FB19_Pos (19U)
    -
    5062#define CAN_F9R2_FB19_Msk (0x1UL << CAN_F9R2_FB19_Pos)
    -
    5063#define CAN_F9R2_FB19 CAN_F9R2_FB19_Msk
    -
    5064#define CAN_F9R2_FB20_Pos (20U)
    -
    5065#define CAN_F9R2_FB20_Msk (0x1UL << CAN_F9R2_FB20_Pos)
    -
    5066#define CAN_F9R2_FB20 CAN_F9R2_FB20_Msk
    -
    5067#define CAN_F9R2_FB21_Pos (21U)
    -
    5068#define CAN_F9R2_FB21_Msk (0x1UL << CAN_F9R2_FB21_Pos)
    -
    5069#define CAN_F9R2_FB21 CAN_F9R2_FB21_Msk
    -
    5070#define CAN_F9R2_FB22_Pos (22U)
    -
    5071#define CAN_F9R2_FB22_Msk (0x1UL << CAN_F9R2_FB22_Pos)
    -
    5072#define CAN_F9R2_FB22 CAN_F9R2_FB22_Msk
    -
    5073#define CAN_F9R2_FB23_Pos (23U)
    -
    5074#define CAN_F9R2_FB23_Msk (0x1UL << CAN_F9R2_FB23_Pos)
    -
    5075#define CAN_F9R2_FB23 CAN_F9R2_FB23_Msk
    -
    5076#define CAN_F9R2_FB24_Pos (24U)
    -
    5077#define CAN_F9R2_FB24_Msk (0x1UL << CAN_F9R2_FB24_Pos)
    -
    5078#define CAN_F9R2_FB24 CAN_F9R2_FB24_Msk
    -
    5079#define CAN_F9R2_FB25_Pos (25U)
    -
    5080#define CAN_F9R2_FB25_Msk (0x1UL << CAN_F9R2_FB25_Pos)
    -
    5081#define CAN_F9R2_FB25 CAN_F9R2_FB25_Msk
    -
    5082#define CAN_F9R2_FB26_Pos (26U)
    -
    5083#define CAN_F9R2_FB26_Msk (0x1UL << CAN_F9R2_FB26_Pos)
    -
    5084#define CAN_F9R2_FB26 CAN_F9R2_FB26_Msk
    -
    5085#define CAN_F9R2_FB27_Pos (27U)
    -
    5086#define CAN_F9R2_FB27_Msk (0x1UL << CAN_F9R2_FB27_Pos)
    -
    5087#define CAN_F9R2_FB27 CAN_F9R2_FB27_Msk
    -
    5088#define CAN_F9R2_FB28_Pos (28U)
    -
    5089#define CAN_F9R2_FB28_Msk (0x1UL << CAN_F9R2_FB28_Pos)
    -
    5090#define CAN_F9R2_FB28 CAN_F9R2_FB28_Msk
    -
    5091#define CAN_F9R2_FB29_Pos (29U)
    -
    5092#define CAN_F9R2_FB29_Msk (0x1UL << CAN_F9R2_FB29_Pos)
    -
    5093#define CAN_F9R2_FB29 CAN_F9R2_FB29_Msk
    -
    5094#define CAN_F9R2_FB30_Pos (30U)
    -
    5095#define CAN_F9R2_FB30_Msk (0x1UL << CAN_F9R2_FB30_Pos)
    -
    5096#define CAN_F9R2_FB30 CAN_F9R2_FB30_Msk
    -
    5097#define CAN_F9R2_FB31_Pos (31U)
    -
    5098#define CAN_F9R2_FB31_Msk (0x1UL << CAN_F9R2_FB31_Pos)
    -
    5099#define CAN_F9R2_FB31 CAN_F9R2_FB31_Msk
    -
    5101/******************* Bit definition for CAN_F10R2 register ******************/
    -
    5102#define CAN_F10R2_FB0_Pos (0U)
    -
    5103#define CAN_F10R2_FB0_Msk (0x1UL << CAN_F10R2_FB0_Pos)
    -
    5104#define CAN_F10R2_FB0 CAN_F10R2_FB0_Msk
    -
    5105#define CAN_F10R2_FB1_Pos (1U)
    -
    5106#define CAN_F10R2_FB1_Msk (0x1UL << CAN_F10R2_FB1_Pos)
    -
    5107#define CAN_F10R2_FB1 CAN_F10R2_FB1_Msk
    -
    5108#define CAN_F10R2_FB2_Pos (2U)
    -
    5109#define CAN_F10R2_FB2_Msk (0x1UL << CAN_F10R2_FB2_Pos)
    -
    5110#define CAN_F10R2_FB2 CAN_F10R2_FB2_Msk
    -
    5111#define CAN_F10R2_FB3_Pos (3U)
    -
    5112#define CAN_F10R2_FB3_Msk (0x1UL << CAN_F10R2_FB3_Pos)
    -
    5113#define CAN_F10R2_FB3 CAN_F10R2_FB3_Msk
    -
    5114#define CAN_F10R2_FB4_Pos (4U)
    -
    5115#define CAN_F10R2_FB4_Msk (0x1UL << CAN_F10R2_FB4_Pos)
    -
    5116#define CAN_F10R2_FB4 CAN_F10R2_FB4_Msk
    -
    5117#define CAN_F10R2_FB5_Pos (5U)
    -
    5118#define CAN_F10R2_FB5_Msk (0x1UL << CAN_F10R2_FB5_Pos)
    -
    5119#define CAN_F10R2_FB5 CAN_F10R2_FB5_Msk
    -
    5120#define CAN_F10R2_FB6_Pos (6U)
    -
    5121#define CAN_F10R2_FB6_Msk (0x1UL << CAN_F10R2_FB6_Pos)
    -
    5122#define CAN_F10R2_FB6 CAN_F10R2_FB6_Msk
    -
    5123#define CAN_F10R2_FB7_Pos (7U)
    -
    5124#define CAN_F10R2_FB7_Msk (0x1UL << CAN_F10R2_FB7_Pos)
    -
    5125#define CAN_F10R2_FB7 CAN_F10R2_FB7_Msk
    -
    5126#define CAN_F10R2_FB8_Pos (8U)
    -
    5127#define CAN_F10R2_FB8_Msk (0x1UL << CAN_F10R2_FB8_Pos)
    -
    5128#define CAN_F10R2_FB8 CAN_F10R2_FB8_Msk
    -
    5129#define CAN_F10R2_FB9_Pos (9U)
    -
    5130#define CAN_F10R2_FB9_Msk (0x1UL << CAN_F10R2_FB9_Pos)
    -
    5131#define CAN_F10R2_FB9 CAN_F10R2_FB9_Msk
    -
    5132#define CAN_F10R2_FB10_Pos (10U)
    -
    5133#define CAN_F10R2_FB10_Msk (0x1UL << CAN_F10R2_FB10_Pos)
    -
    5134#define CAN_F10R2_FB10 CAN_F10R2_FB10_Msk
    -
    5135#define CAN_F10R2_FB11_Pos (11U)
    -
    5136#define CAN_F10R2_FB11_Msk (0x1UL << CAN_F10R2_FB11_Pos)
    -
    5137#define CAN_F10R2_FB11 CAN_F10R2_FB11_Msk
    -
    5138#define CAN_F10R2_FB12_Pos (12U)
    -
    5139#define CAN_F10R2_FB12_Msk (0x1UL << CAN_F10R2_FB12_Pos)
    -
    5140#define CAN_F10R2_FB12 CAN_F10R2_FB12_Msk
    -
    5141#define CAN_F10R2_FB13_Pos (13U)
    -
    5142#define CAN_F10R2_FB13_Msk (0x1UL << CAN_F10R2_FB13_Pos)
    -
    5143#define CAN_F10R2_FB13 CAN_F10R2_FB13_Msk
    -
    5144#define CAN_F10R2_FB14_Pos (14U)
    -
    5145#define CAN_F10R2_FB14_Msk (0x1UL << CAN_F10R2_FB14_Pos)
    -
    5146#define CAN_F10R2_FB14 CAN_F10R2_FB14_Msk
    -
    5147#define CAN_F10R2_FB15_Pos (15U)
    -
    5148#define CAN_F10R2_FB15_Msk (0x1UL << CAN_F10R2_FB15_Pos)
    -
    5149#define CAN_F10R2_FB15 CAN_F10R2_FB15_Msk
    -
    5150#define CAN_F10R2_FB16_Pos (16U)
    -
    5151#define CAN_F10R2_FB16_Msk (0x1UL << CAN_F10R2_FB16_Pos)
    -
    5152#define CAN_F10R2_FB16 CAN_F10R2_FB16_Msk
    -
    5153#define CAN_F10R2_FB17_Pos (17U)
    -
    5154#define CAN_F10R2_FB17_Msk (0x1UL << CAN_F10R2_FB17_Pos)
    -
    5155#define CAN_F10R2_FB17 CAN_F10R2_FB17_Msk
    -
    5156#define CAN_F10R2_FB18_Pos (18U)
    -
    5157#define CAN_F10R2_FB18_Msk (0x1UL << CAN_F10R2_FB18_Pos)
    -
    5158#define CAN_F10R2_FB18 CAN_F10R2_FB18_Msk
    -
    5159#define CAN_F10R2_FB19_Pos (19U)
    -
    5160#define CAN_F10R2_FB19_Msk (0x1UL << CAN_F10R2_FB19_Pos)
    -
    5161#define CAN_F10R2_FB19 CAN_F10R2_FB19_Msk
    -
    5162#define CAN_F10R2_FB20_Pos (20U)
    -
    5163#define CAN_F10R2_FB20_Msk (0x1UL << CAN_F10R2_FB20_Pos)
    -
    5164#define CAN_F10R2_FB20 CAN_F10R2_FB20_Msk
    -
    5165#define CAN_F10R2_FB21_Pos (21U)
    -
    5166#define CAN_F10R2_FB21_Msk (0x1UL << CAN_F10R2_FB21_Pos)
    -
    5167#define CAN_F10R2_FB21 CAN_F10R2_FB21_Msk
    -
    5168#define CAN_F10R2_FB22_Pos (22U)
    -
    5169#define CAN_F10R2_FB22_Msk (0x1UL << CAN_F10R2_FB22_Pos)
    -
    5170#define CAN_F10R2_FB22 CAN_F10R2_FB22_Msk
    -
    5171#define CAN_F10R2_FB23_Pos (23U)
    -
    5172#define CAN_F10R2_FB23_Msk (0x1UL << CAN_F10R2_FB23_Pos)
    -
    5173#define CAN_F10R2_FB23 CAN_F10R2_FB23_Msk
    -
    5174#define CAN_F10R2_FB24_Pos (24U)
    -
    5175#define CAN_F10R2_FB24_Msk (0x1UL << CAN_F10R2_FB24_Pos)
    -
    5176#define CAN_F10R2_FB24 CAN_F10R2_FB24_Msk
    -
    5177#define CAN_F10R2_FB25_Pos (25U)
    -
    5178#define CAN_F10R2_FB25_Msk (0x1UL << CAN_F10R2_FB25_Pos)
    -
    5179#define CAN_F10R2_FB25 CAN_F10R2_FB25_Msk
    -
    5180#define CAN_F10R2_FB26_Pos (26U)
    -
    5181#define CAN_F10R2_FB26_Msk (0x1UL << CAN_F10R2_FB26_Pos)
    -
    5182#define CAN_F10R2_FB26 CAN_F10R2_FB26_Msk
    -
    5183#define CAN_F10R2_FB27_Pos (27U)
    -
    5184#define CAN_F10R2_FB27_Msk (0x1UL << CAN_F10R2_FB27_Pos)
    -
    5185#define CAN_F10R2_FB27 CAN_F10R2_FB27_Msk
    -
    5186#define CAN_F10R2_FB28_Pos (28U)
    -
    5187#define CAN_F10R2_FB28_Msk (0x1UL << CAN_F10R2_FB28_Pos)
    -
    5188#define CAN_F10R2_FB28 CAN_F10R2_FB28_Msk
    -
    5189#define CAN_F10R2_FB29_Pos (29U)
    -
    5190#define CAN_F10R2_FB29_Msk (0x1UL << CAN_F10R2_FB29_Pos)
    -
    5191#define CAN_F10R2_FB29 CAN_F10R2_FB29_Msk
    -
    5192#define CAN_F10R2_FB30_Pos (30U)
    -
    5193#define CAN_F10R2_FB30_Msk (0x1UL << CAN_F10R2_FB30_Pos)
    -
    5194#define CAN_F10R2_FB30 CAN_F10R2_FB30_Msk
    -
    5195#define CAN_F10R2_FB31_Pos (31U)
    -
    5196#define CAN_F10R2_FB31_Msk (0x1UL << CAN_F10R2_FB31_Pos)
    -
    5197#define CAN_F10R2_FB31 CAN_F10R2_FB31_Msk
    -
    5199/******************* Bit definition for CAN_F11R2 register ******************/
    -
    5200#define CAN_F11R2_FB0_Pos (0U)
    -
    5201#define CAN_F11R2_FB0_Msk (0x1UL << CAN_F11R2_FB0_Pos)
    -
    5202#define CAN_F11R2_FB0 CAN_F11R2_FB0_Msk
    -
    5203#define CAN_F11R2_FB1_Pos (1U)
    -
    5204#define CAN_F11R2_FB1_Msk (0x1UL << CAN_F11R2_FB1_Pos)
    -
    5205#define CAN_F11R2_FB1 CAN_F11R2_FB1_Msk
    -
    5206#define CAN_F11R2_FB2_Pos (2U)
    -
    5207#define CAN_F11R2_FB2_Msk (0x1UL << CAN_F11R2_FB2_Pos)
    -
    5208#define CAN_F11R2_FB2 CAN_F11R2_FB2_Msk
    -
    5209#define CAN_F11R2_FB3_Pos (3U)
    -
    5210#define CAN_F11R2_FB3_Msk (0x1UL << CAN_F11R2_FB3_Pos)
    -
    5211#define CAN_F11R2_FB3 CAN_F11R2_FB3_Msk
    -
    5212#define CAN_F11R2_FB4_Pos (4U)
    -
    5213#define CAN_F11R2_FB4_Msk (0x1UL << CAN_F11R2_FB4_Pos)
    -
    5214#define CAN_F11R2_FB4 CAN_F11R2_FB4_Msk
    -
    5215#define CAN_F11R2_FB5_Pos (5U)
    -
    5216#define CAN_F11R2_FB5_Msk (0x1UL << CAN_F11R2_FB5_Pos)
    -
    5217#define CAN_F11R2_FB5 CAN_F11R2_FB5_Msk
    -
    5218#define CAN_F11R2_FB6_Pos (6U)
    -
    5219#define CAN_F11R2_FB6_Msk (0x1UL << CAN_F11R2_FB6_Pos)
    -
    5220#define CAN_F11R2_FB6 CAN_F11R2_FB6_Msk
    -
    5221#define CAN_F11R2_FB7_Pos (7U)
    -
    5222#define CAN_F11R2_FB7_Msk (0x1UL << CAN_F11R2_FB7_Pos)
    -
    5223#define CAN_F11R2_FB7 CAN_F11R2_FB7_Msk
    -
    5224#define CAN_F11R2_FB8_Pos (8U)
    -
    5225#define CAN_F11R2_FB8_Msk (0x1UL << CAN_F11R2_FB8_Pos)
    -
    5226#define CAN_F11R2_FB8 CAN_F11R2_FB8_Msk
    -
    5227#define CAN_F11R2_FB9_Pos (9U)
    -
    5228#define CAN_F11R2_FB9_Msk (0x1UL << CAN_F11R2_FB9_Pos)
    -
    5229#define CAN_F11R2_FB9 CAN_F11R2_FB9_Msk
    -
    5230#define CAN_F11R2_FB10_Pos (10U)
    -
    5231#define CAN_F11R2_FB10_Msk (0x1UL << CAN_F11R2_FB10_Pos)
    -
    5232#define CAN_F11R2_FB10 CAN_F11R2_FB10_Msk
    -
    5233#define CAN_F11R2_FB11_Pos (11U)
    -
    5234#define CAN_F11R2_FB11_Msk (0x1UL << CAN_F11R2_FB11_Pos)
    -
    5235#define CAN_F11R2_FB11 CAN_F11R2_FB11_Msk
    -
    5236#define CAN_F11R2_FB12_Pos (12U)
    -
    5237#define CAN_F11R2_FB12_Msk (0x1UL << CAN_F11R2_FB12_Pos)
    -
    5238#define CAN_F11R2_FB12 CAN_F11R2_FB12_Msk
    -
    5239#define CAN_F11R2_FB13_Pos (13U)
    -
    5240#define CAN_F11R2_FB13_Msk (0x1UL << CAN_F11R2_FB13_Pos)
    -
    5241#define CAN_F11R2_FB13 CAN_F11R2_FB13_Msk
    -
    5242#define CAN_F11R2_FB14_Pos (14U)
    -
    5243#define CAN_F11R2_FB14_Msk (0x1UL << CAN_F11R2_FB14_Pos)
    -
    5244#define CAN_F11R2_FB14 CAN_F11R2_FB14_Msk
    -
    5245#define CAN_F11R2_FB15_Pos (15U)
    -
    5246#define CAN_F11R2_FB15_Msk (0x1UL << CAN_F11R2_FB15_Pos)
    -
    5247#define CAN_F11R2_FB15 CAN_F11R2_FB15_Msk
    -
    5248#define CAN_F11R2_FB16_Pos (16U)
    -
    5249#define CAN_F11R2_FB16_Msk (0x1UL << CAN_F11R2_FB16_Pos)
    -
    5250#define CAN_F11R2_FB16 CAN_F11R2_FB16_Msk
    -
    5251#define CAN_F11R2_FB17_Pos (17U)
    -
    5252#define CAN_F11R2_FB17_Msk (0x1UL << CAN_F11R2_FB17_Pos)
    -
    5253#define CAN_F11R2_FB17 CAN_F11R2_FB17_Msk
    -
    5254#define CAN_F11R2_FB18_Pos (18U)
    -
    5255#define CAN_F11R2_FB18_Msk (0x1UL << CAN_F11R2_FB18_Pos)
    -
    5256#define CAN_F11R2_FB18 CAN_F11R2_FB18_Msk
    -
    5257#define CAN_F11R2_FB19_Pos (19U)
    -
    5258#define CAN_F11R2_FB19_Msk (0x1UL << CAN_F11R2_FB19_Pos)
    -
    5259#define CAN_F11R2_FB19 CAN_F11R2_FB19_Msk
    -
    5260#define CAN_F11R2_FB20_Pos (20U)
    -
    5261#define CAN_F11R2_FB20_Msk (0x1UL << CAN_F11R2_FB20_Pos)
    -
    5262#define CAN_F11R2_FB20 CAN_F11R2_FB20_Msk
    -
    5263#define CAN_F11R2_FB21_Pos (21U)
    -
    5264#define CAN_F11R2_FB21_Msk (0x1UL << CAN_F11R2_FB21_Pos)
    -
    5265#define CAN_F11R2_FB21 CAN_F11R2_FB21_Msk
    -
    5266#define CAN_F11R2_FB22_Pos (22U)
    -
    5267#define CAN_F11R2_FB22_Msk (0x1UL << CAN_F11R2_FB22_Pos)
    -
    5268#define CAN_F11R2_FB22 CAN_F11R2_FB22_Msk
    -
    5269#define CAN_F11R2_FB23_Pos (23U)
    -
    5270#define CAN_F11R2_FB23_Msk (0x1UL << CAN_F11R2_FB23_Pos)
    -
    5271#define CAN_F11R2_FB23 CAN_F11R2_FB23_Msk
    -
    5272#define CAN_F11R2_FB24_Pos (24U)
    -
    5273#define CAN_F11R2_FB24_Msk (0x1UL << CAN_F11R2_FB24_Pos)
    -
    5274#define CAN_F11R2_FB24 CAN_F11R2_FB24_Msk
    -
    5275#define CAN_F11R2_FB25_Pos (25U)
    -
    5276#define CAN_F11R2_FB25_Msk (0x1UL << CAN_F11R2_FB25_Pos)
    -
    5277#define CAN_F11R2_FB25 CAN_F11R2_FB25_Msk
    -
    5278#define CAN_F11R2_FB26_Pos (26U)
    -
    5279#define CAN_F11R2_FB26_Msk (0x1UL << CAN_F11R2_FB26_Pos)
    -
    5280#define CAN_F11R2_FB26 CAN_F11R2_FB26_Msk
    -
    5281#define CAN_F11R2_FB27_Pos (27U)
    -
    5282#define CAN_F11R2_FB27_Msk (0x1UL << CAN_F11R2_FB27_Pos)
    -
    5283#define CAN_F11R2_FB27 CAN_F11R2_FB27_Msk
    -
    5284#define CAN_F11R2_FB28_Pos (28U)
    -
    5285#define CAN_F11R2_FB28_Msk (0x1UL << CAN_F11R2_FB28_Pos)
    -
    5286#define CAN_F11R2_FB28 CAN_F11R2_FB28_Msk
    -
    5287#define CAN_F11R2_FB29_Pos (29U)
    -
    5288#define CAN_F11R2_FB29_Msk (0x1UL << CAN_F11R2_FB29_Pos)
    -
    5289#define CAN_F11R2_FB29 CAN_F11R2_FB29_Msk
    -
    5290#define CAN_F11R2_FB30_Pos (30U)
    -
    5291#define CAN_F11R2_FB30_Msk (0x1UL << CAN_F11R2_FB30_Pos)
    -
    5292#define CAN_F11R2_FB30 CAN_F11R2_FB30_Msk
    -
    5293#define CAN_F11R2_FB31_Pos (31U)
    -
    5294#define CAN_F11R2_FB31_Msk (0x1UL << CAN_F11R2_FB31_Pos)
    -
    5295#define CAN_F11R2_FB31 CAN_F11R2_FB31_Msk
    -
    5297/******************* Bit definition for CAN_F12R2 register ******************/
    -
    5298#define CAN_F12R2_FB0_Pos (0U)
    -
    5299#define CAN_F12R2_FB0_Msk (0x1UL << CAN_F12R2_FB0_Pos)
    -
    5300#define CAN_F12R2_FB0 CAN_F12R2_FB0_Msk
    -
    5301#define CAN_F12R2_FB1_Pos (1U)
    -
    5302#define CAN_F12R2_FB1_Msk (0x1UL << CAN_F12R2_FB1_Pos)
    -
    5303#define CAN_F12R2_FB1 CAN_F12R2_FB1_Msk
    -
    5304#define CAN_F12R2_FB2_Pos (2U)
    -
    5305#define CAN_F12R2_FB2_Msk (0x1UL << CAN_F12R2_FB2_Pos)
    -
    5306#define CAN_F12R2_FB2 CAN_F12R2_FB2_Msk
    -
    5307#define CAN_F12R2_FB3_Pos (3U)
    -
    5308#define CAN_F12R2_FB3_Msk (0x1UL << CAN_F12R2_FB3_Pos)
    -
    5309#define CAN_F12R2_FB3 CAN_F12R2_FB3_Msk
    -
    5310#define CAN_F12R2_FB4_Pos (4U)
    -
    5311#define CAN_F12R2_FB4_Msk (0x1UL << CAN_F12R2_FB4_Pos)
    -
    5312#define CAN_F12R2_FB4 CAN_F12R2_FB4_Msk
    -
    5313#define CAN_F12R2_FB5_Pos (5U)
    -
    5314#define CAN_F12R2_FB5_Msk (0x1UL << CAN_F12R2_FB5_Pos)
    -
    5315#define CAN_F12R2_FB5 CAN_F12R2_FB5_Msk
    -
    5316#define CAN_F12R2_FB6_Pos (6U)
    -
    5317#define CAN_F12R2_FB6_Msk (0x1UL << CAN_F12R2_FB6_Pos)
    -
    5318#define CAN_F12R2_FB6 CAN_F12R2_FB6_Msk
    -
    5319#define CAN_F12R2_FB7_Pos (7U)
    -
    5320#define CAN_F12R2_FB7_Msk (0x1UL << CAN_F12R2_FB7_Pos)
    -
    5321#define CAN_F12R2_FB7 CAN_F12R2_FB7_Msk
    -
    5322#define CAN_F12R2_FB8_Pos (8U)
    -
    5323#define CAN_F12R2_FB8_Msk (0x1UL << CAN_F12R2_FB8_Pos)
    -
    5324#define CAN_F12R2_FB8 CAN_F12R2_FB8_Msk
    -
    5325#define CAN_F12R2_FB9_Pos (9U)
    -
    5326#define CAN_F12R2_FB9_Msk (0x1UL << CAN_F12R2_FB9_Pos)
    -
    5327#define CAN_F12R2_FB9 CAN_F12R2_FB9_Msk
    -
    5328#define CAN_F12R2_FB10_Pos (10U)
    -
    5329#define CAN_F12R2_FB10_Msk (0x1UL << CAN_F12R2_FB10_Pos)
    -
    5330#define CAN_F12R2_FB10 CAN_F12R2_FB10_Msk
    -
    5331#define CAN_F12R2_FB11_Pos (11U)
    -
    5332#define CAN_F12R2_FB11_Msk (0x1UL << CAN_F12R2_FB11_Pos)
    -
    5333#define CAN_F12R2_FB11 CAN_F12R2_FB11_Msk
    -
    5334#define CAN_F12R2_FB12_Pos (12U)
    -
    5335#define CAN_F12R2_FB12_Msk (0x1UL << CAN_F12R2_FB12_Pos)
    -
    5336#define CAN_F12R2_FB12 CAN_F12R2_FB12_Msk
    -
    5337#define CAN_F12R2_FB13_Pos (13U)
    -
    5338#define CAN_F12R2_FB13_Msk (0x1UL << CAN_F12R2_FB13_Pos)
    -
    5339#define CAN_F12R2_FB13 CAN_F12R2_FB13_Msk
    -
    5340#define CAN_F12R2_FB14_Pos (14U)
    -
    5341#define CAN_F12R2_FB14_Msk (0x1UL << CAN_F12R2_FB14_Pos)
    -
    5342#define CAN_F12R2_FB14 CAN_F12R2_FB14_Msk
    -
    5343#define CAN_F12R2_FB15_Pos (15U)
    -
    5344#define CAN_F12R2_FB15_Msk (0x1UL << CAN_F12R2_FB15_Pos)
    -
    5345#define CAN_F12R2_FB15 CAN_F12R2_FB15_Msk
    -
    5346#define CAN_F12R2_FB16_Pos (16U)
    -
    5347#define CAN_F12R2_FB16_Msk (0x1UL << CAN_F12R2_FB16_Pos)
    -
    5348#define CAN_F12R2_FB16 CAN_F12R2_FB16_Msk
    -
    5349#define CAN_F12R2_FB17_Pos (17U)
    -
    5350#define CAN_F12R2_FB17_Msk (0x1UL << CAN_F12R2_FB17_Pos)
    -
    5351#define CAN_F12R2_FB17 CAN_F12R2_FB17_Msk
    -
    5352#define CAN_F12R2_FB18_Pos (18U)
    -
    5353#define CAN_F12R2_FB18_Msk (0x1UL << CAN_F12R2_FB18_Pos)
    -
    5354#define CAN_F12R2_FB18 CAN_F12R2_FB18_Msk
    -
    5355#define CAN_F12R2_FB19_Pos (19U)
    -
    5356#define CAN_F12R2_FB19_Msk (0x1UL << CAN_F12R2_FB19_Pos)
    -
    5357#define CAN_F12R2_FB19 CAN_F12R2_FB19_Msk
    -
    5358#define CAN_F12R2_FB20_Pos (20U)
    -
    5359#define CAN_F12R2_FB20_Msk (0x1UL << CAN_F12R2_FB20_Pos)
    -
    5360#define CAN_F12R2_FB20 CAN_F12R2_FB20_Msk
    -
    5361#define CAN_F12R2_FB21_Pos (21U)
    -
    5362#define CAN_F12R2_FB21_Msk (0x1UL << CAN_F12R2_FB21_Pos)
    -
    5363#define CAN_F12R2_FB21 CAN_F12R2_FB21_Msk
    -
    5364#define CAN_F12R2_FB22_Pos (22U)
    -
    5365#define CAN_F12R2_FB22_Msk (0x1UL << CAN_F12R2_FB22_Pos)
    -
    5366#define CAN_F12R2_FB22 CAN_F12R2_FB22_Msk
    -
    5367#define CAN_F12R2_FB23_Pos (23U)
    -
    5368#define CAN_F12R2_FB23_Msk (0x1UL << CAN_F12R2_FB23_Pos)
    -
    5369#define CAN_F12R2_FB23 CAN_F12R2_FB23_Msk
    -
    5370#define CAN_F12R2_FB24_Pos (24U)
    -
    5371#define CAN_F12R2_FB24_Msk (0x1UL << CAN_F12R2_FB24_Pos)
    -
    5372#define CAN_F12R2_FB24 CAN_F12R2_FB24_Msk
    -
    5373#define CAN_F12R2_FB25_Pos (25U)
    -
    5374#define CAN_F12R2_FB25_Msk (0x1UL << CAN_F12R2_FB25_Pos)
    -
    5375#define CAN_F12R2_FB25 CAN_F12R2_FB25_Msk
    -
    5376#define CAN_F12R2_FB26_Pos (26U)
    -
    5377#define CAN_F12R2_FB26_Msk (0x1UL << CAN_F12R2_FB26_Pos)
    -
    5378#define CAN_F12R2_FB26 CAN_F12R2_FB26_Msk
    -
    5379#define CAN_F12R2_FB27_Pos (27U)
    -
    5380#define CAN_F12R2_FB27_Msk (0x1UL << CAN_F12R2_FB27_Pos)
    -
    5381#define CAN_F12R2_FB27 CAN_F12R2_FB27_Msk
    -
    5382#define CAN_F12R2_FB28_Pos (28U)
    -
    5383#define CAN_F12R2_FB28_Msk (0x1UL << CAN_F12R2_FB28_Pos)
    -
    5384#define CAN_F12R2_FB28 CAN_F12R2_FB28_Msk
    -
    5385#define CAN_F12R2_FB29_Pos (29U)
    -
    5386#define CAN_F12R2_FB29_Msk (0x1UL << CAN_F12R2_FB29_Pos)
    -
    5387#define CAN_F12R2_FB29 CAN_F12R2_FB29_Msk
    -
    5388#define CAN_F12R2_FB30_Pos (30U)
    -
    5389#define CAN_F12R2_FB30_Msk (0x1UL << CAN_F12R2_FB30_Pos)
    -
    5390#define CAN_F12R2_FB30 CAN_F12R2_FB30_Msk
    -
    5391#define CAN_F12R2_FB31_Pos (31U)
    -
    5392#define CAN_F12R2_FB31_Msk (0x1UL << CAN_F12R2_FB31_Pos)
    -
    5393#define CAN_F12R2_FB31 CAN_F12R2_FB31_Msk
    -
    5395/******************* Bit definition for CAN_F13R2 register ******************/
    -
    5396#define CAN_F13R2_FB0_Pos (0U)
    -
    5397#define CAN_F13R2_FB0_Msk (0x1UL << CAN_F13R2_FB0_Pos)
    -
    5398#define CAN_F13R2_FB0 CAN_F13R2_FB0_Msk
    -
    5399#define CAN_F13R2_FB1_Pos (1U)
    -
    5400#define CAN_F13R2_FB1_Msk (0x1UL << CAN_F13R2_FB1_Pos)
    -
    5401#define CAN_F13R2_FB1 CAN_F13R2_FB1_Msk
    -
    5402#define CAN_F13R2_FB2_Pos (2U)
    -
    5403#define CAN_F13R2_FB2_Msk (0x1UL << CAN_F13R2_FB2_Pos)
    -
    5404#define CAN_F13R2_FB2 CAN_F13R2_FB2_Msk
    -
    5405#define CAN_F13R2_FB3_Pos (3U)
    -
    5406#define CAN_F13R2_FB3_Msk (0x1UL << CAN_F13R2_FB3_Pos)
    -
    5407#define CAN_F13R2_FB3 CAN_F13R2_FB3_Msk
    -
    5408#define CAN_F13R2_FB4_Pos (4U)
    -
    5409#define CAN_F13R2_FB4_Msk (0x1UL << CAN_F13R2_FB4_Pos)
    -
    5410#define CAN_F13R2_FB4 CAN_F13R2_FB4_Msk
    -
    5411#define CAN_F13R2_FB5_Pos (5U)
    -
    5412#define CAN_F13R2_FB5_Msk (0x1UL << CAN_F13R2_FB5_Pos)
    -
    5413#define CAN_F13R2_FB5 CAN_F13R2_FB5_Msk
    -
    5414#define CAN_F13R2_FB6_Pos (6U)
    -
    5415#define CAN_F13R2_FB6_Msk (0x1UL << CAN_F13R2_FB6_Pos)
    -
    5416#define CAN_F13R2_FB6 CAN_F13R2_FB6_Msk
    -
    5417#define CAN_F13R2_FB7_Pos (7U)
    -
    5418#define CAN_F13R2_FB7_Msk (0x1UL << CAN_F13R2_FB7_Pos)
    -
    5419#define CAN_F13R2_FB7 CAN_F13R2_FB7_Msk
    -
    5420#define CAN_F13R2_FB8_Pos (8U)
    -
    5421#define CAN_F13R2_FB8_Msk (0x1UL << CAN_F13R2_FB8_Pos)
    -
    5422#define CAN_F13R2_FB8 CAN_F13R2_FB8_Msk
    -
    5423#define CAN_F13R2_FB9_Pos (9U)
    -
    5424#define CAN_F13R2_FB9_Msk (0x1UL << CAN_F13R2_FB9_Pos)
    -
    5425#define CAN_F13R2_FB9 CAN_F13R2_FB9_Msk
    -
    5426#define CAN_F13R2_FB10_Pos (10U)
    -
    5427#define CAN_F13R2_FB10_Msk (0x1UL << CAN_F13R2_FB10_Pos)
    -
    5428#define CAN_F13R2_FB10 CAN_F13R2_FB10_Msk
    -
    5429#define CAN_F13R2_FB11_Pos (11U)
    -
    5430#define CAN_F13R2_FB11_Msk (0x1UL << CAN_F13R2_FB11_Pos)
    -
    5431#define CAN_F13R2_FB11 CAN_F13R2_FB11_Msk
    -
    5432#define CAN_F13R2_FB12_Pos (12U)
    -
    5433#define CAN_F13R2_FB12_Msk (0x1UL << CAN_F13R2_FB12_Pos)
    -
    5434#define CAN_F13R2_FB12 CAN_F13R2_FB12_Msk
    -
    5435#define CAN_F13R2_FB13_Pos (13U)
    -
    5436#define CAN_F13R2_FB13_Msk (0x1UL << CAN_F13R2_FB13_Pos)
    -
    5437#define CAN_F13R2_FB13 CAN_F13R2_FB13_Msk
    -
    5438#define CAN_F13R2_FB14_Pos (14U)
    -
    5439#define CAN_F13R2_FB14_Msk (0x1UL << CAN_F13R2_FB14_Pos)
    -
    5440#define CAN_F13R2_FB14 CAN_F13R2_FB14_Msk
    -
    5441#define CAN_F13R2_FB15_Pos (15U)
    -
    5442#define CAN_F13R2_FB15_Msk (0x1UL << CAN_F13R2_FB15_Pos)
    -
    5443#define CAN_F13R2_FB15 CAN_F13R2_FB15_Msk
    -
    5444#define CAN_F13R2_FB16_Pos (16U)
    -
    5445#define CAN_F13R2_FB16_Msk (0x1UL << CAN_F13R2_FB16_Pos)
    -
    5446#define CAN_F13R2_FB16 CAN_F13R2_FB16_Msk
    -
    5447#define CAN_F13R2_FB17_Pos (17U)
    -
    5448#define CAN_F13R2_FB17_Msk (0x1UL << CAN_F13R2_FB17_Pos)
    -
    5449#define CAN_F13R2_FB17 CAN_F13R2_FB17_Msk
    -
    5450#define CAN_F13R2_FB18_Pos (18U)
    -
    5451#define CAN_F13R2_FB18_Msk (0x1UL << CAN_F13R2_FB18_Pos)
    -
    5452#define CAN_F13R2_FB18 CAN_F13R2_FB18_Msk
    -
    5453#define CAN_F13R2_FB19_Pos (19U)
    -
    5454#define CAN_F13R2_FB19_Msk (0x1UL << CAN_F13R2_FB19_Pos)
    -
    5455#define CAN_F13R2_FB19 CAN_F13R2_FB19_Msk
    -
    5456#define CAN_F13R2_FB20_Pos (20U)
    -
    5457#define CAN_F13R2_FB20_Msk (0x1UL << CAN_F13R2_FB20_Pos)
    -
    5458#define CAN_F13R2_FB20 CAN_F13R2_FB20_Msk
    -
    5459#define CAN_F13R2_FB21_Pos (21U)
    -
    5460#define CAN_F13R2_FB21_Msk (0x1UL << CAN_F13R2_FB21_Pos)
    -
    5461#define CAN_F13R2_FB21 CAN_F13R2_FB21_Msk
    -
    5462#define CAN_F13R2_FB22_Pos (22U)
    -
    5463#define CAN_F13R2_FB22_Msk (0x1UL << CAN_F13R2_FB22_Pos)
    -
    5464#define CAN_F13R2_FB22 CAN_F13R2_FB22_Msk
    -
    5465#define CAN_F13R2_FB23_Pos (23U)
    -
    5466#define CAN_F13R2_FB23_Msk (0x1UL << CAN_F13R2_FB23_Pos)
    -
    5467#define CAN_F13R2_FB23 CAN_F13R2_FB23_Msk
    -
    5468#define CAN_F13R2_FB24_Pos (24U)
    -
    5469#define CAN_F13R2_FB24_Msk (0x1UL << CAN_F13R2_FB24_Pos)
    -
    5470#define CAN_F13R2_FB24 CAN_F13R2_FB24_Msk
    -
    5471#define CAN_F13R2_FB25_Pos (25U)
    -
    5472#define CAN_F13R2_FB25_Msk (0x1UL << CAN_F13R2_FB25_Pos)
    -
    5473#define CAN_F13R2_FB25 CAN_F13R2_FB25_Msk
    -
    5474#define CAN_F13R2_FB26_Pos (26U)
    -
    5475#define CAN_F13R2_FB26_Msk (0x1UL << CAN_F13R2_FB26_Pos)
    -
    5476#define CAN_F13R2_FB26 CAN_F13R2_FB26_Msk
    -
    5477#define CAN_F13R2_FB27_Pos (27U)
    -
    5478#define CAN_F13R2_FB27_Msk (0x1UL << CAN_F13R2_FB27_Pos)
    -
    5479#define CAN_F13R2_FB27 CAN_F13R2_FB27_Msk
    -
    5480#define CAN_F13R2_FB28_Pos (28U)
    -
    5481#define CAN_F13R2_FB28_Msk (0x1UL << CAN_F13R2_FB28_Pos)
    -
    5482#define CAN_F13R2_FB28 CAN_F13R2_FB28_Msk
    -
    5483#define CAN_F13R2_FB29_Pos (29U)
    -
    5484#define CAN_F13R2_FB29_Msk (0x1UL << CAN_F13R2_FB29_Pos)
    -
    5485#define CAN_F13R2_FB29 CAN_F13R2_FB29_Msk
    -
    5486#define CAN_F13R2_FB30_Pos (30U)
    -
    5487#define CAN_F13R2_FB30_Msk (0x1UL << CAN_F13R2_FB30_Pos)
    -
    5488#define CAN_F13R2_FB30 CAN_F13R2_FB30_Msk
    -
    5489#define CAN_F13R2_FB31_Pos (31U)
    -
    5490#define CAN_F13R2_FB31_Msk (0x1UL << CAN_F13R2_FB31_Pos)
    -
    5491#define CAN_F13R2_FB31 CAN_F13R2_FB31_Msk
    -
    5493/******************************************************************************/
    -
    5494/* */
    -
    5495/* CRC calculation unit */
    -
    5496/* */
    -
    5497/******************************************************************************/
    -
    5498/******************* Bit definition for CRC_DR register *********************/
    -
    5499#define CRC_DR_DR_Pos (0U)
    -
    5500#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos)
    -
    5501#define CRC_DR_DR CRC_DR_DR_Msk
    -
    5504/******************* Bit definition for CRC_IDR register ********************/
    -
    5505#define CRC_IDR_IDR_Pos (0U)
    -
    5506#define CRC_IDR_IDR_Msk (0xFFUL << CRC_IDR_IDR_Pos)
    -
    5507#define CRC_IDR_IDR CRC_IDR_IDR_Msk
    -
    5510/******************** Bit definition for CRC_CR register ********************/
    -
    5511#define CRC_CR_RESET_Pos (0U)
    -
    5512#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos)
    -
    5513#define CRC_CR_RESET CRC_CR_RESET_Msk
    -
    5515/******************************************************************************/
    -
    5516/* */
    -
    5517/* Digital to Analog Converter */
    -
    5518/* */
    -
    5519/******************************************************************************/
    -
    5520/*
    -
    5521 * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
    -
    5522 */
    -
    5523#define DAC_CHANNEL2_SUPPORT
    -
    5524/******************** Bit definition for DAC_CR register ********************/
    -
    5525#define DAC_CR_EN1_Pos (0U)
    -
    5526#define DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos)
    -
    5527#define DAC_CR_EN1 DAC_CR_EN1_Msk
    -
    5528#define DAC_CR_BOFF1_Pos (1U)
    -
    5529#define DAC_CR_BOFF1_Msk (0x1UL << DAC_CR_BOFF1_Pos)
    -
    5530#define DAC_CR_BOFF1 DAC_CR_BOFF1_Msk
    -
    5531#define DAC_CR_TEN1_Pos (2U)
    -
    5532#define DAC_CR_TEN1_Msk (0x1UL << DAC_CR_TEN1_Pos)
    -
    5533#define DAC_CR_TEN1 DAC_CR_TEN1_Msk
    -
    5535#define DAC_CR_TSEL1_Pos (3U)
    -
    5536#define DAC_CR_TSEL1_Msk (0x7UL << DAC_CR_TSEL1_Pos)
    -
    5537#define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk
    -
    5538#define DAC_CR_TSEL1_0 (0x1UL << DAC_CR_TSEL1_Pos)
    -
    5539#define DAC_CR_TSEL1_1 (0x2UL << DAC_CR_TSEL1_Pos)
    -
    5540#define DAC_CR_TSEL1_2 (0x4UL << DAC_CR_TSEL1_Pos)
    -
    5542#define DAC_CR_WAVE1_Pos (6U)
    -
    5543#define DAC_CR_WAVE1_Msk (0x3UL << DAC_CR_WAVE1_Pos)
    -
    5544#define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk
    -
    5545#define DAC_CR_WAVE1_0 (0x1UL << DAC_CR_WAVE1_Pos)
    -
    5546#define DAC_CR_WAVE1_1 (0x2UL << DAC_CR_WAVE1_Pos)
    -
    5548#define DAC_CR_MAMP1_Pos (8U)
    -
    5549#define DAC_CR_MAMP1_Msk (0xFUL << DAC_CR_MAMP1_Pos)
    -
    5550#define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk
    -
    5551#define DAC_CR_MAMP1_0 (0x1UL << DAC_CR_MAMP1_Pos)
    -
    5552#define DAC_CR_MAMP1_1 (0x2UL << DAC_CR_MAMP1_Pos)
    -
    5553#define DAC_CR_MAMP1_2 (0x4UL << DAC_CR_MAMP1_Pos)
    -
    5554#define DAC_CR_MAMP1_3 (0x8UL << DAC_CR_MAMP1_Pos)
    -
    5556#define DAC_CR_DMAEN1_Pos (12U)
    -
    5557#define DAC_CR_DMAEN1_Msk (0x1UL << DAC_CR_DMAEN1_Pos)
    -
    5558#define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk
    -
    5559#define DAC_CR_DMAUDRIE1_Pos (13U)
    -
    5560#define DAC_CR_DMAUDRIE1_Msk (0x1UL << DAC_CR_DMAUDRIE1_Pos)
    -
    5561#define DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk
    -
    5562#define DAC_CR_EN2_Pos (16U)
    -
    5563#define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos)
    -
    5564#define DAC_CR_EN2 DAC_CR_EN2_Msk
    -
    5565#define DAC_CR_BOFF2_Pos (17U)
    -
    5566#define DAC_CR_BOFF2_Msk (0x1UL << DAC_CR_BOFF2_Pos)
    -
    5567#define DAC_CR_BOFF2 DAC_CR_BOFF2_Msk
    -
    5568#define DAC_CR_TEN2_Pos (18U)
    -
    5569#define DAC_CR_TEN2_Msk (0x1UL << DAC_CR_TEN2_Pos)
    -
    5570#define DAC_CR_TEN2 DAC_CR_TEN2_Msk
    -
    5572#define DAC_CR_TSEL2_Pos (19U)
    -
    5573#define DAC_CR_TSEL2_Msk (0x7UL << DAC_CR_TSEL2_Pos)
    -
    5574#define DAC_CR_TSEL2 DAC_CR_TSEL2_Msk
    -
    5575#define DAC_CR_TSEL2_0 (0x1UL << DAC_CR_TSEL2_Pos)
    -
    5576#define DAC_CR_TSEL2_1 (0x2UL << DAC_CR_TSEL2_Pos)
    -
    5577#define DAC_CR_TSEL2_2 (0x4UL << DAC_CR_TSEL2_Pos)
    -
    5579#define DAC_CR_WAVE2_Pos (22U)
    -
    5580#define DAC_CR_WAVE2_Msk (0x3UL << DAC_CR_WAVE2_Pos)
    -
    5581#define DAC_CR_WAVE2 DAC_CR_WAVE2_Msk
    -
    5582#define DAC_CR_WAVE2_0 (0x1UL << DAC_CR_WAVE2_Pos)
    -
    5583#define DAC_CR_WAVE2_1 (0x2UL << DAC_CR_WAVE2_Pos)
    -
    5585#define DAC_CR_MAMP2_Pos (24U)
    -
    5586#define DAC_CR_MAMP2_Msk (0xFUL << DAC_CR_MAMP2_Pos)
    -
    5587#define DAC_CR_MAMP2 DAC_CR_MAMP2_Msk
    -
    5588#define DAC_CR_MAMP2_0 (0x1UL << DAC_CR_MAMP2_Pos)
    -
    5589#define DAC_CR_MAMP2_1 (0x2UL << DAC_CR_MAMP2_Pos)
    -
    5590#define DAC_CR_MAMP2_2 (0x4UL << DAC_CR_MAMP2_Pos)
    -
    5591#define DAC_CR_MAMP2_3 (0x8UL << DAC_CR_MAMP2_Pos)
    -
    5593#define DAC_CR_DMAEN2_Pos (28U)
    -
    5594#define DAC_CR_DMAEN2_Msk (0x1UL << DAC_CR_DMAEN2_Pos)
    -
    5595#define DAC_CR_DMAEN2 DAC_CR_DMAEN2_Msk
    -
    5596#define DAC_CR_DMAUDRIE2_Pos (29U)
    -
    5597#define DAC_CR_DMAUDRIE2_Msk (0x1UL << DAC_CR_DMAUDRIE2_Pos)
    -
    5598#define DAC_CR_DMAUDRIE2 DAC_CR_DMAUDRIE2_Msk
    -
    5600/***************** Bit definition for DAC_SWTRIGR register ******************/
    -
    5601#define DAC_SWTRIGR_SWTRIG1_Pos (0U)
    -
    5602#define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos)
    -
    5603#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk
    -
    5604#define DAC_SWTRIGR_SWTRIG2_Pos (1U)
    -
    5605#define DAC_SWTRIGR_SWTRIG2_Msk (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos)
    -
    5606#define DAC_SWTRIGR_SWTRIG2 DAC_SWTRIGR_SWTRIG2_Msk
    -
    5608/***************** Bit definition for DAC_DHR12R1 register ******************/
    -
    5609#define DAC_DHR12R1_DACC1DHR_Pos (0U)
    -
    5610#define DAC_DHR12R1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos)
    -
    5611#define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk
    -
    5613/***************** Bit definition for DAC_DHR12L1 register ******************/
    -
    5614#define DAC_DHR12L1_DACC1DHR_Pos (4U)
    -
    5615#define DAC_DHR12L1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos)
    -
    5616#define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk
    -
    5618/****************** Bit definition for DAC_DHR8R1 register ******************/
    -
    5619#define DAC_DHR8R1_DACC1DHR_Pos (0U)
    -
    5620#define DAC_DHR8R1_DACC1DHR_Msk (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos)
    -
    5621#define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk
    -
    5623/***************** Bit definition for DAC_DHR12R2 register ******************/
    -
    5624#define DAC_DHR12R2_DACC2DHR_Pos (0U)
    -
    5625#define DAC_DHR12R2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos)
    -
    5626#define DAC_DHR12R2_DACC2DHR DAC_DHR12R2_DACC2DHR_Msk
    -
    5628/***************** Bit definition for DAC_DHR12L2 register ******************/
    -
    5629#define DAC_DHR12L2_DACC2DHR_Pos (4U)
    -
    5630#define DAC_DHR12L2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos)
    -
    5631#define DAC_DHR12L2_DACC2DHR DAC_DHR12L2_DACC2DHR_Msk
    -
    5633/****************** Bit definition for DAC_DHR8R2 register ******************/
    -
    5634#define DAC_DHR8R2_DACC2DHR_Pos (0U)
    -
    5635#define DAC_DHR8R2_DACC2DHR_Msk (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos)
    -
    5636#define DAC_DHR8R2_DACC2DHR DAC_DHR8R2_DACC2DHR_Msk
    -
    5638/***************** Bit definition for DAC_DHR12RD register ******************/
    -
    5639#define DAC_DHR12RD_DACC1DHR_Pos (0U)
    -
    5640#define DAC_DHR12RD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos)
    -
    5641#define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk
    -
    5642#define DAC_DHR12RD_DACC2DHR_Pos (16U)
    -
    5643#define DAC_DHR12RD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos)
    -
    5644#define DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk
    -
    5646/***************** Bit definition for DAC_DHR12LD register ******************/
    -
    5647#define DAC_DHR12LD_DACC1DHR_Pos (4U)
    -
    5648#define DAC_DHR12LD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos)
    -
    5649#define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk
    -
    5650#define DAC_DHR12LD_DACC2DHR_Pos (20U)
    -
    5651#define DAC_DHR12LD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos)
    -
    5652#define DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk
    -
    5654/****************** Bit definition for DAC_DHR8RD register ******************/
    -
    5655#define DAC_DHR8RD_DACC1DHR_Pos (0U)
    -
    5656#define DAC_DHR8RD_DACC1DHR_Msk (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos)
    -
    5657#define DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk
    -
    5658#define DAC_DHR8RD_DACC2DHR_Pos (8U)
    -
    5659#define DAC_DHR8RD_DACC2DHR_Msk (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos)
    -
    5660#define DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk
    -
    5662/******************* Bit definition for DAC_DOR1 register *******************/
    -
    5663#define DAC_DOR1_DACC1DOR_Pos (0U)
    -
    5664#define DAC_DOR1_DACC1DOR_Msk (0xFFFUL << DAC_DOR1_DACC1DOR_Pos)
    -
    5665#define DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk
    -
    5667/******************* Bit definition for DAC_DOR2 register *******************/
    -
    5668#define DAC_DOR2_DACC2DOR_Pos (0U)
    -
    5669#define DAC_DOR2_DACC2DOR_Msk (0xFFFUL << DAC_DOR2_DACC2DOR_Pos)
    -
    5670#define DAC_DOR2_DACC2DOR DAC_DOR2_DACC2DOR_Msk
    -
    5672/******************** Bit definition for DAC_SR register ********************/
    -
    5673#define DAC_SR_DMAUDR1_Pos (13U)
    -
    5674#define DAC_SR_DMAUDR1_Msk (0x1UL << DAC_SR_DMAUDR1_Pos)
    -
    5675#define DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk
    -
    5676#define DAC_SR_DMAUDR2_Pos (29U)
    -
    5677#define DAC_SR_DMAUDR2_Msk (0x1UL << DAC_SR_DMAUDR2_Pos)
    -
    5678#define DAC_SR_DMAUDR2 DAC_SR_DMAUDR2_Msk
    -
    5680/******************************************************************************/
    -
    5681/* */
    -
    5682/* DCMI */
    -
    5683/* */
    -
    5684/******************************************************************************/
    -
    5685/******************** Bits definition for DCMI_CR register ******************/
    -
    5686#define DCMI_CR_CAPTURE_Pos (0U)
    -
    5687#define DCMI_CR_CAPTURE_Msk (0x1UL << DCMI_CR_CAPTURE_Pos)
    -
    5688#define DCMI_CR_CAPTURE DCMI_CR_CAPTURE_Msk
    -
    5689#define DCMI_CR_CM_Pos (1U)
    -
    5690#define DCMI_CR_CM_Msk (0x1UL << DCMI_CR_CM_Pos)
    -
    5691#define DCMI_CR_CM DCMI_CR_CM_Msk
    -
    5692#define DCMI_CR_CROP_Pos (2U)
    -
    5693#define DCMI_CR_CROP_Msk (0x1UL << DCMI_CR_CROP_Pos)
    -
    5694#define DCMI_CR_CROP DCMI_CR_CROP_Msk
    -
    5695#define DCMI_CR_JPEG_Pos (3U)
    -
    5696#define DCMI_CR_JPEG_Msk (0x1UL << DCMI_CR_JPEG_Pos)
    -
    5697#define DCMI_CR_JPEG DCMI_CR_JPEG_Msk
    -
    5698#define DCMI_CR_ESS_Pos (4U)
    -
    5699#define DCMI_CR_ESS_Msk (0x1UL << DCMI_CR_ESS_Pos)
    -
    5700#define DCMI_CR_ESS DCMI_CR_ESS_Msk
    -
    5701#define DCMI_CR_PCKPOL_Pos (5U)
    -
    5702#define DCMI_CR_PCKPOL_Msk (0x1UL << DCMI_CR_PCKPOL_Pos)
    -
    5703#define DCMI_CR_PCKPOL DCMI_CR_PCKPOL_Msk
    -
    5704#define DCMI_CR_HSPOL_Pos (6U)
    -
    5705#define DCMI_CR_HSPOL_Msk (0x1UL << DCMI_CR_HSPOL_Pos)
    -
    5706#define DCMI_CR_HSPOL DCMI_CR_HSPOL_Msk
    -
    5707#define DCMI_CR_VSPOL_Pos (7U)
    -
    5708#define DCMI_CR_VSPOL_Msk (0x1UL << DCMI_CR_VSPOL_Pos)
    -
    5709#define DCMI_CR_VSPOL DCMI_CR_VSPOL_Msk
    -
    5710#define DCMI_CR_FCRC_0 0x00000100U
    -
    5711#define DCMI_CR_FCRC_1 0x00000200U
    -
    5712#define DCMI_CR_EDM_0 0x00000400U
    -
    5713#define DCMI_CR_EDM_1 0x00000800U
    -
    5714#define DCMI_CR_CRE_Pos (12U)
    -
    5715#define DCMI_CR_CRE_Msk (0x1UL << DCMI_CR_CRE_Pos)
    -
    5716#define DCMI_CR_CRE DCMI_CR_CRE_Msk
    -
    5717#define DCMI_CR_ENABLE_Pos (14U)
    -
    5718#define DCMI_CR_ENABLE_Msk (0x1UL << DCMI_CR_ENABLE_Pos)
    -
    5719#define DCMI_CR_ENABLE DCMI_CR_ENABLE_Msk
    -
    5720
    -
    5721/******************** Bits definition for DCMI_SR register ******************/
    -
    5722#define DCMI_SR_HSYNC_Pos (0U)
    -
    5723#define DCMI_SR_HSYNC_Msk (0x1UL << DCMI_SR_HSYNC_Pos)
    -
    5724#define DCMI_SR_HSYNC DCMI_SR_HSYNC_Msk
    -
    5725#define DCMI_SR_VSYNC_Pos (1U)
    -
    5726#define DCMI_SR_VSYNC_Msk (0x1UL << DCMI_SR_VSYNC_Pos)
    -
    5727#define DCMI_SR_VSYNC DCMI_SR_VSYNC_Msk
    -
    5728#define DCMI_SR_FNE_Pos (2U)
    -
    5729#define DCMI_SR_FNE_Msk (0x1UL << DCMI_SR_FNE_Pos)
    -
    5730#define DCMI_SR_FNE DCMI_SR_FNE_Msk
    -
    5731
    -
    5732/******************** Bits definition for DCMI_RIS register *****************/
    -
    5733#define DCMI_RIS_FRAME_RIS_Pos (0U)
    -
    5734#define DCMI_RIS_FRAME_RIS_Msk (0x1UL << DCMI_RIS_FRAME_RIS_Pos)
    -
    5735#define DCMI_RIS_FRAME_RIS DCMI_RIS_FRAME_RIS_Msk
    -
    5736#define DCMI_RIS_OVR_RIS_Pos (1U)
    -
    5737#define DCMI_RIS_OVR_RIS_Msk (0x1UL << DCMI_RIS_OVR_RIS_Pos)
    -
    5738#define DCMI_RIS_OVR_RIS DCMI_RIS_OVR_RIS_Msk
    -
    5739#define DCMI_RIS_ERR_RIS_Pos (2U)
    -
    5740#define DCMI_RIS_ERR_RIS_Msk (0x1UL << DCMI_RIS_ERR_RIS_Pos)
    -
    5741#define DCMI_RIS_ERR_RIS DCMI_RIS_ERR_RIS_Msk
    -
    5742#define DCMI_RIS_VSYNC_RIS_Pos (3U)
    -
    5743#define DCMI_RIS_VSYNC_RIS_Msk (0x1UL << DCMI_RIS_VSYNC_RIS_Pos)
    -
    5744#define DCMI_RIS_VSYNC_RIS DCMI_RIS_VSYNC_RIS_Msk
    -
    5745#define DCMI_RIS_LINE_RIS_Pos (4U)
    -
    5746#define DCMI_RIS_LINE_RIS_Msk (0x1UL << DCMI_RIS_LINE_RIS_Pos)
    -
    5747#define DCMI_RIS_LINE_RIS DCMI_RIS_LINE_RIS_Msk
    -
    5748/* Legacy defines */
    -
    5749#define DCMI_RISR_FRAME_RIS DCMI_RIS_FRAME_RIS
    -
    5750#define DCMI_RISR_OVR_RIS DCMI_RIS_OVR_RIS
    -
    5751#define DCMI_RISR_ERR_RIS DCMI_RIS_ERR_RIS
    -
    5752#define DCMI_RISR_VSYNC_RIS DCMI_RIS_VSYNC_RIS
    -
    5753#define DCMI_RISR_LINE_RIS DCMI_RIS_LINE_RIS
    -
    5754#define DCMI_RISR_OVF_RIS DCMI_RIS_OVR_RIS
    -
    5755
    -
    5756/******************** Bits definition for DCMI_IER register *****************/
    -
    5757#define DCMI_IER_FRAME_IE_Pos (0U)
    -
    5758#define DCMI_IER_FRAME_IE_Msk (0x1UL << DCMI_IER_FRAME_IE_Pos)
    -
    5759#define DCMI_IER_FRAME_IE DCMI_IER_FRAME_IE_Msk
    -
    5760#define DCMI_IER_OVR_IE_Pos (1U)
    -
    5761#define DCMI_IER_OVR_IE_Msk (0x1UL << DCMI_IER_OVR_IE_Pos)
    -
    5762#define DCMI_IER_OVR_IE DCMI_IER_OVR_IE_Msk
    -
    5763#define DCMI_IER_ERR_IE_Pos (2U)
    -
    5764#define DCMI_IER_ERR_IE_Msk (0x1UL << DCMI_IER_ERR_IE_Pos)
    -
    5765#define DCMI_IER_ERR_IE DCMI_IER_ERR_IE_Msk
    -
    5766#define DCMI_IER_VSYNC_IE_Pos (3U)
    -
    5767#define DCMI_IER_VSYNC_IE_Msk (0x1UL << DCMI_IER_VSYNC_IE_Pos)
    -
    5768#define DCMI_IER_VSYNC_IE DCMI_IER_VSYNC_IE_Msk
    -
    5769#define DCMI_IER_LINE_IE_Pos (4U)
    -
    5770#define DCMI_IER_LINE_IE_Msk (0x1UL << DCMI_IER_LINE_IE_Pos)
    -
    5771#define DCMI_IER_LINE_IE DCMI_IER_LINE_IE_Msk
    -
    5772/* Legacy defines */
    -
    5773#define DCMI_IER_OVF_IE DCMI_IER_OVR_IE
    -
    5774
    -
    5775/******************** Bits definition for DCMI_MIS register *****************/
    -
    5776#define DCMI_MIS_FRAME_MIS_Pos (0U)
    -
    5777#define DCMI_MIS_FRAME_MIS_Msk (0x1UL << DCMI_MIS_FRAME_MIS_Pos)
    -
    5778#define DCMI_MIS_FRAME_MIS DCMI_MIS_FRAME_MIS_Msk
    -
    5779#define DCMI_MIS_OVR_MIS_Pos (1U)
    -
    5780#define DCMI_MIS_OVR_MIS_Msk (0x1UL << DCMI_MIS_OVR_MIS_Pos)
    -
    5781#define DCMI_MIS_OVR_MIS DCMI_MIS_OVR_MIS_Msk
    -
    5782#define DCMI_MIS_ERR_MIS_Pos (2U)
    -
    5783#define DCMI_MIS_ERR_MIS_Msk (0x1UL << DCMI_MIS_ERR_MIS_Pos)
    -
    5784#define DCMI_MIS_ERR_MIS DCMI_MIS_ERR_MIS_Msk
    -
    5785#define DCMI_MIS_VSYNC_MIS_Pos (3U)
    -
    5786#define DCMI_MIS_VSYNC_MIS_Msk (0x1UL << DCMI_MIS_VSYNC_MIS_Pos)
    -
    5787#define DCMI_MIS_VSYNC_MIS DCMI_MIS_VSYNC_MIS_Msk
    -
    5788#define DCMI_MIS_LINE_MIS_Pos (4U)
    -
    5789#define DCMI_MIS_LINE_MIS_Msk (0x1UL << DCMI_MIS_LINE_MIS_Pos)
    -
    5790#define DCMI_MIS_LINE_MIS DCMI_MIS_LINE_MIS_Msk
    -
    5791
    -
    5792/* Legacy defines */
    -
    5793#define DCMI_MISR_FRAME_MIS DCMI_MIS_FRAME_MIS
    -
    5794#define DCMI_MISR_OVF_MIS DCMI_MIS_OVR_MIS
    -
    5795#define DCMI_MISR_ERR_MIS DCMI_MIS_ERR_MIS
    -
    5796#define DCMI_MISR_VSYNC_MIS DCMI_MIS_VSYNC_MIS
    -
    5797#define DCMI_MISR_LINE_MIS DCMI_MIS_LINE_MIS
    -
    5798
    -
    5799/******************** Bits definition for DCMI_ICR register *****************/
    -
    5800#define DCMI_ICR_FRAME_ISC_Pos (0U)
    -
    5801#define DCMI_ICR_FRAME_ISC_Msk (0x1UL << DCMI_ICR_FRAME_ISC_Pos)
    -
    5802#define DCMI_ICR_FRAME_ISC DCMI_ICR_FRAME_ISC_Msk
    -
    5803#define DCMI_ICR_OVR_ISC_Pos (1U)
    -
    5804#define DCMI_ICR_OVR_ISC_Msk (0x1UL << DCMI_ICR_OVR_ISC_Pos)
    -
    5805#define DCMI_ICR_OVR_ISC DCMI_ICR_OVR_ISC_Msk
    -
    5806#define DCMI_ICR_ERR_ISC_Pos (2U)
    -
    5807#define DCMI_ICR_ERR_ISC_Msk (0x1UL << DCMI_ICR_ERR_ISC_Pos)
    -
    5808#define DCMI_ICR_ERR_ISC DCMI_ICR_ERR_ISC_Msk
    -
    5809#define DCMI_ICR_VSYNC_ISC_Pos (3U)
    -
    5810#define DCMI_ICR_VSYNC_ISC_Msk (0x1UL << DCMI_ICR_VSYNC_ISC_Pos)
    -
    5811#define DCMI_ICR_VSYNC_ISC DCMI_ICR_VSYNC_ISC_Msk
    -
    5812#define DCMI_ICR_LINE_ISC_Pos (4U)
    -
    5813#define DCMI_ICR_LINE_ISC_Msk (0x1UL << DCMI_ICR_LINE_ISC_Pos)
    -
    5814#define DCMI_ICR_LINE_ISC DCMI_ICR_LINE_ISC_Msk
    -
    5815
    -
    5816/* Legacy defines */
    -
    5817#define DCMI_ICR_OVF_ISC DCMI_ICR_OVR_ISC
    -
    5818
    -
    5819/******************** Bits definition for DCMI_ESCR register ******************/
    -
    5820#define DCMI_ESCR_FSC_Pos (0U)
    -
    5821#define DCMI_ESCR_FSC_Msk (0xFFUL << DCMI_ESCR_FSC_Pos)
    -
    5822#define DCMI_ESCR_FSC DCMI_ESCR_FSC_Msk
    -
    5823#define DCMI_ESCR_LSC_Pos (8U)
    -
    5824#define DCMI_ESCR_LSC_Msk (0xFFUL << DCMI_ESCR_LSC_Pos)
    -
    5825#define DCMI_ESCR_LSC DCMI_ESCR_LSC_Msk
    -
    5826#define DCMI_ESCR_LEC_Pos (16U)
    -
    5827#define DCMI_ESCR_LEC_Msk (0xFFUL << DCMI_ESCR_LEC_Pos)
    -
    5828#define DCMI_ESCR_LEC DCMI_ESCR_LEC_Msk
    -
    5829#define DCMI_ESCR_FEC_Pos (24U)
    -
    5830#define DCMI_ESCR_FEC_Msk (0xFFUL << DCMI_ESCR_FEC_Pos)
    -
    5831#define DCMI_ESCR_FEC DCMI_ESCR_FEC_Msk
    -
    5832
    -
    5833/******************** Bits definition for DCMI_ESUR register ******************/
    -
    5834#define DCMI_ESUR_FSU_Pos (0U)
    -
    5835#define DCMI_ESUR_FSU_Msk (0xFFUL << DCMI_ESUR_FSU_Pos)
    -
    5836#define DCMI_ESUR_FSU DCMI_ESUR_FSU_Msk
    -
    5837#define DCMI_ESUR_LSU_Pos (8U)
    -
    5838#define DCMI_ESUR_LSU_Msk (0xFFUL << DCMI_ESUR_LSU_Pos)
    -
    5839#define DCMI_ESUR_LSU DCMI_ESUR_LSU_Msk
    -
    5840#define DCMI_ESUR_LEU_Pos (16U)
    -
    5841#define DCMI_ESUR_LEU_Msk (0xFFUL << DCMI_ESUR_LEU_Pos)
    -
    5842#define DCMI_ESUR_LEU DCMI_ESUR_LEU_Msk
    -
    5843#define DCMI_ESUR_FEU_Pos (24U)
    -
    5844#define DCMI_ESUR_FEU_Msk (0xFFUL << DCMI_ESUR_FEU_Pos)
    -
    5845#define DCMI_ESUR_FEU DCMI_ESUR_FEU_Msk
    -
    5846
    -
    5847/******************** Bits definition for DCMI_CWSTRT register ******************/
    -
    5848#define DCMI_CWSTRT_HOFFCNT_Pos (0U)
    -
    5849#define DCMI_CWSTRT_HOFFCNT_Msk (0x3FFFUL << DCMI_CWSTRT_HOFFCNT_Pos)
    -
    5850#define DCMI_CWSTRT_HOFFCNT DCMI_CWSTRT_HOFFCNT_Msk
    -
    5851#define DCMI_CWSTRT_VST_Pos (16U)
    -
    5852#define DCMI_CWSTRT_VST_Msk (0x1FFFUL << DCMI_CWSTRT_VST_Pos)
    -
    5853#define DCMI_CWSTRT_VST DCMI_CWSTRT_VST_Msk
    -
    5854
    -
    5855/******************** Bits definition for DCMI_CWSIZE register ******************/
    -
    5856#define DCMI_CWSIZE_CAPCNT_Pos (0U)
    -
    5857#define DCMI_CWSIZE_CAPCNT_Msk (0x3FFFUL << DCMI_CWSIZE_CAPCNT_Pos)
    -
    5858#define DCMI_CWSIZE_CAPCNT DCMI_CWSIZE_CAPCNT_Msk
    -
    5859#define DCMI_CWSIZE_VLINE_Pos (16U)
    -
    5860#define DCMI_CWSIZE_VLINE_Msk (0x3FFFUL << DCMI_CWSIZE_VLINE_Pos)
    -
    5861#define DCMI_CWSIZE_VLINE DCMI_CWSIZE_VLINE_Msk
    -
    5862
    -
    5863/******************** Bits definition for DCMI_DR register *********************/
    -
    5864#define DCMI_DR_BYTE0_Pos (0U)
    -
    5865#define DCMI_DR_BYTE0_Msk (0xFFUL << DCMI_DR_BYTE0_Pos)
    -
    5866#define DCMI_DR_BYTE0 DCMI_DR_BYTE0_Msk
    -
    5867#define DCMI_DR_BYTE1_Pos (8U)
    -
    5868#define DCMI_DR_BYTE1_Msk (0xFFUL << DCMI_DR_BYTE1_Pos)
    -
    5869#define DCMI_DR_BYTE1 DCMI_DR_BYTE1_Msk
    -
    5870#define DCMI_DR_BYTE2_Pos (16U)
    -
    5871#define DCMI_DR_BYTE2_Msk (0xFFUL << DCMI_DR_BYTE2_Pos)
    -
    5872#define DCMI_DR_BYTE2 DCMI_DR_BYTE2_Msk
    -
    5873#define DCMI_DR_BYTE3_Pos (24U)
    -
    5874#define DCMI_DR_BYTE3_Msk (0xFFUL << DCMI_DR_BYTE3_Pos)
    -
    5875#define DCMI_DR_BYTE3 DCMI_DR_BYTE3_Msk
    -
    5876
    -
    5877/******************************************************************************/
    -
    5878/* */
    -
    5879/* DMA Controller */
    -
    5880/* */
    -
    5881/******************************************************************************/
    -
    5882/******************** Bits definition for DMA_SxCR register *****************/
    -
    5883#define DMA_SxCR_CHSEL_Pos (25U)
    -
    5884#define DMA_SxCR_CHSEL_Msk (0x7UL << DMA_SxCR_CHSEL_Pos)
    -
    5885#define DMA_SxCR_CHSEL DMA_SxCR_CHSEL_Msk
    -
    5886#define DMA_SxCR_CHSEL_0 0x02000000U
    -
    5887#define DMA_SxCR_CHSEL_1 0x04000000U
    -
    5888#define DMA_SxCR_CHSEL_2 0x08000000U
    -
    5889#define DMA_SxCR_MBURST_Pos (23U)
    -
    5890#define DMA_SxCR_MBURST_Msk (0x3UL << DMA_SxCR_MBURST_Pos)
    -
    5891#define DMA_SxCR_MBURST DMA_SxCR_MBURST_Msk
    -
    5892#define DMA_SxCR_MBURST_0 (0x1UL << DMA_SxCR_MBURST_Pos)
    -
    5893#define DMA_SxCR_MBURST_1 (0x2UL << DMA_SxCR_MBURST_Pos)
    -
    5894#define DMA_SxCR_PBURST_Pos (21U)
    -
    5895#define DMA_SxCR_PBURST_Msk (0x3UL << DMA_SxCR_PBURST_Pos)
    -
    5896#define DMA_SxCR_PBURST DMA_SxCR_PBURST_Msk
    -
    5897#define DMA_SxCR_PBURST_0 (0x1UL << DMA_SxCR_PBURST_Pos)
    -
    5898#define DMA_SxCR_PBURST_1 (0x2UL << DMA_SxCR_PBURST_Pos)
    -
    5899#define DMA_SxCR_CT_Pos (19U)
    -
    5900#define DMA_SxCR_CT_Msk (0x1UL << DMA_SxCR_CT_Pos)
    -
    5901#define DMA_SxCR_CT DMA_SxCR_CT_Msk
    -
    5902#define DMA_SxCR_DBM_Pos (18U)
    -
    5903#define DMA_SxCR_DBM_Msk (0x1UL << DMA_SxCR_DBM_Pos)
    -
    5904#define DMA_SxCR_DBM DMA_SxCR_DBM_Msk
    -
    5905#define DMA_SxCR_PL_Pos (16U)
    -
    5906#define DMA_SxCR_PL_Msk (0x3UL << DMA_SxCR_PL_Pos)
    -
    5907#define DMA_SxCR_PL DMA_SxCR_PL_Msk
    -
    5908#define DMA_SxCR_PL_0 (0x1UL << DMA_SxCR_PL_Pos)
    -
    5909#define DMA_SxCR_PL_1 (0x2UL << DMA_SxCR_PL_Pos)
    -
    5910#define DMA_SxCR_PINCOS_Pos (15U)
    -
    5911#define DMA_SxCR_PINCOS_Msk (0x1UL << DMA_SxCR_PINCOS_Pos)
    -
    5912#define DMA_SxCR_PINCOS DMA_SxCR_PINCOS_Msk
    -
    5913#define DMA_SxCR_MSIZE_Pos (13U)
    -
    5914#define DMA_SxCR_MSIZE_Msk (0x3UL << DMA_SxCR_MSIZE_Pos)
    -
    5915#define DMA_SxCR_MSIZE DMA_SxCR_MSIZE_Msk
    -
    5916#define DMA_SxCR_MSIZE_0 (0x1UL << DMA_SxCR_MSIZE_Pos)
    -
    5917#define DMA_SxCR_MSIZE_1 (0x2UL << DMA_SxCR_MSIZE_Pos)
    -
    5918#define DMA_SxCR_PSIZE_Pos (11U)
    -
    5919#define DMA_SxCR_PSIZE_Msk (0x3UL << DMA_SxCR_PSIZE_Pos)
    -
    5920#define DMA_SxCR_PSIZE DMA_SxCR_PSIZE_Msk
    -
    5921#define DMA_SxCR_PSIZE_0 (0x1UL << DMA_SxCR_PSIZE_Pos)
    -
    5922#define DMA_SxCR_PSIZE_1 (0x2UL << DMA_SxCR_PSIZE_Pos)
    -
    5923#define DMA_SxCR_MINC_Pos (10U)
    -
    5924#define DMA_SxCR_MINC_Msk (0x1UL << DMA_SxCR_MINC_Pos)
    -
    5925#define DMA_SxCR_MINC DMA_SxCR_MINC_Msk
    -
    5926#define DMA_SxCR_PINC_Pos (9U)
    -
    5927#define DMA_SxCR_PINC_Msk (0x1UL << DMA_SxCR_PINC_Pos)
    -
    5928#define DMA_SxCR_PINC DMA_SxCR_PINC_Msk
    -
    5929#define DMA_SxCR_CIRC_Pos (8U)
    -
    5930#define DMA_SxCR_CIRC_Msk (0x1UL << DMA_SxCR_CIRC_Pos)
    -
    5931#define DMA_SxCR_CIRC DMA_SxCR_CIRC_Msk
    -
    5932#define DMA_SxCR_DIR_Pos (6U)
    -
    5933#define DMA_SxCR_DIR_Msk (0x3UL << DMA_SxCR_DIR_Pos)
    -
    5934#define DMA_SxCR_DIR DMA_SxCR_DIR_Msk
    -
    5935#define DMA_SxCR_DIR_0 (0x1UL << DMA_SxCR_DIR_Pos)
    -
    5936#define DMA_SxCR_DIR_1 (0x2UL << DMA_SxCR_DIR_Pos)
    -
    5937#define DMA_SxCR_PFCTRL_Pos (5U)
    -
    5938#define DMA_SxCR_PFCTRL_Msk (0x1UL << DMA_SxCR_PFCTRL_Pos)
    -
    5939#define DMA_SxCR_PFCTRL DMA_SxCR_PFCTRL_Msk
    -
    5940#define DMA_SxCR_TCIE_Pos (4U)
    -
    5941#define DMA_SxCR_TCIE_Msk (0x1UL << DMA_SxCR_TCIE_Pos)
    -
    5942#define DMA_SxCR_TCIE DMA_SxCR_TCIE_Msk
    -
    5943#define DMA_SxCR_HTIE_Pos (3U)
    -
    5944#define DMA_SxCR_HTIE_Msk (0x1UL << DMA_SxCR_HTIE_Pos)
    -
    5945#define DMA_SxCR_HTIE DMA_SxCR_HTIE_Msk
    -
    5946#define DMA_SxCR_TEIE_Pos (2U)
    -
    5947#define DMA_SxCR_TEIE_Msk (0x1UL << DMA_SxCR_TEIE_Pos)
    -
    5948#define DMA_SxCR_TEIE DMA_SxCR_TEIE_Msk
    -
    5949#define DMA_SxCR_DMEIE_Pos (1U)
    -
    5950#define DMA_SxCR_DMEIE_Msk (0x1UL << DMA_SxCR_DMEIE_Pos)
    -
    5951#define DMA_SxCR_DMEIE DMA_SxCR_DMEIE_Msk
    -
    5952#define DMA_SxCR_EN_Pos (0U)
    -
    5953#define DMA_SxCR_EN_Msk (0x1UL << DMA_SxCR_EN_Pos)
    -
    5954#define DMA_SxCR_EN DMA_SxCR_EN_Msk
    -
    5955
    -
    5956/* Legacy defines */
    -
    5957#define DMA_SxCR_ACK_Pos (20U)
    -
    5958#define DMA_SxCR_ACK_Msk (0x1UL << DMA_SxCR_ACK_Pos)
    -
    5959#define DMA_SxCR_ACK DMA_SxCR_ACK_Msk
    -
    5960
    -
    5961/******************** Bits definition for DMA_SxCNDTR register **************/
    -
    5962#define DMA_SxNDT_Pos (0U)
    -
    5963#define DMA_SxNDT_Msk (0xFFFFUL << DMA_SxNDT_Pos)
    -
    5964#define DMA_SxNDT DMA_SxNDT_Msk
    -
    5965#define DMA_SxNDT_0 (0x0001UL << DMA_SxNDT_Pos)
    -
    5966#define DMA_SxNDT_1 (0x0002UL << DMA_SxNDT_Pos)
    -
    5967#define DMA_SxNDT_2 (0x0004UL << DMA_SxNDT_Pos)
    -
    5968#define DMA_SxNDT_3 (0x0008UL << DMA_SxNDT_Pos)
    -
    5969#define DMA_SxNDT_4 (0x0010UL << DMA_SxNDT_Pos)
    -
    5970#define DMA_SxNDT_5 (0x0020UL << DMA_SxNDT_Pos)
    -
    5971#define DMA_SxNDT_6 (0x0040UL << DMA_SxNDT_Pos)
    -
    5972#define DMA_SxNDT_7 (0x0080UL << DMA_SxNDT_Pos)
    -
    5973#define DMA_SxNDT_8 (0x0100UL << DMA_SxNDT_Pos)
    -
    5974#define DMA_SxNDT_9 (0x0200UL << DMA_SxNDT_Pos)
    -
    5975#define DMA_SxNDT_10 (0x0400UL << DMA_SxNDT_Pos)
    -
    5976#define DMA_SxNDT_11 (0x0800UL << DMA_SxNDT_Pos)
    -
    5977#define DMA_SxNDT_12 (0x1000UL << DMA_SxNDT_Pos)
    -
    5978#define DMA_SxNDT_13 (0x2000UL << DMA_SxNDT_Pos)
    -
    5979#define DMA_SxNDT_14 (0x4000UL << DMA_SxNDT_Pos)
    -
    5980#define DMA_SxNDT_15 (0x8000UL << DMA_SxNDT_Pos)
    -
    5982/******************** Bits definition for DMA_SxFCR register ****************/
    -
    5983#define DMA_SxFCR_FEIE_Pos (7U)
    -
    5984#define DMA_SxFCR_FEIE_Msk (0x1UL << DMA_SxFCR_FEIE_Pos)
    -
    5985#define DMA_SxFCR_FEIE DMA_SxFCR_FEIE_Msk
    -
    5986#define DMA_SxFCR_FS_Pos (3U)
    -
    5987#define DMA_SxFCR_FS_Msk (0x7UL << DMA_SxFCR_FS_Pos)
    -
    5988#define DMA_SxFCR_FS DMA_SxFCR_FS_Msk
    -
    5989#define DMA_SxFCR_FS_0 (0x1UL << DMA_SxFCR_FS_Pos)
    -
    5990#define DMA_SxFCR_FS_1 (0x2UL << DMA_SxFCR_FS_Pos)
    -
    5991#define DMA_SxFCR_FS_2 (0x4UL << DMA_SxFCR_FS_Pos)
    -
    5992#define DMA_SxFCR_DMDIS_Pos (2U)
    -
    5993#define DMA_SxFCR_DMDIS_Msk (0x1UL << DMA_SxFCR_DMDIS_Pos)
    -
    5994#define DMA_SxFCR_DMDIS DMA_SxFCR_DMDIS_Msk
    -
    5995#define DMA_SxFCR_FTH_Pos (0U)
    -
    5996#define DMA_SxFCR_FTH_Msk (0x3UL << DMA_SxFCR_FTH_Pos)
    -
    5997#define DMA_SxFCR_FTH DMA_SxFCR_FTH_Msk
    -
    5998#define DMA_SxFCR_FTH_0 (0x1UL << DMA_SxFCR_FTH_Pos)
    -
    5999#define DMA_SxFCR_FTH_1 (0x2UL << DMA_SxFCR_FTH_Pos)
    -
    6001/******************** Bits definition for DMA_LISR register *****************/
    -
    6002#define DMA_LISR_TCIF3_Pos (27U)
    -
    6003#define DMA_LISR_TCIF3_Msk (0x1UL << DMA_LISR_TCIF3_Pos)
    -
    6004#define DMA_LISR_TCIF3 DMA_LISR_TCIF3_Msk
    -
    6005#define DMA_LISR_HTIF3_Pos (26U)
    -
    6006#define DMA_LISR_HTIF3_Msk (0x1UL << DMA_LISR_HTIF3_Pos)
    -
    6007#define DMA_LISR_HTIF3 DMA_LISR_HTIF3_Msk
    -
    6008#define DMA_LISR_TEIF3_Pos (25U)
    -
    6009#define DMA_LISR_TEIF3_Msk (0x1UL << DMA_LISR_TEIF3_Pos)
    -
    6010#define DMA_LISR_TEIF3 DMA_LISR_TEIF3_Msk
    -
    6011#define DMA_LISR_DMEIF3_Pos (24U)
    -
    6012#define DMA_LISR_DMEIF3_Msk (0x1UL << DMA_LISR_DMEIF3_Pos)
    -
    6013#define DMA_LISR_DMEIF3 DMA_LISR_DMEIF3_Msk
    -
    6014#define DMA_LISR_FEIF3_Pos (22U)
    -
    6015#define DMA_LISR_FEIF3_Msk (0x1UL << DMA_LISR_FEIF3_Pos)
    -
    6016#define DMA_LISR_FEIF3 DMA_LISR_FEIF3_Msk
    -
    6017#define DMA_LISR_TCIF2_Pos (21U)
    -
    6018#define DMA_LISR_TCIF2_Msk (0x1UL << DMA_LISR_TCIF2_Pos)
    -
    6019#define DMA_LISR_TCIF2 DMA_LISR_TCIF2_Msk
    -
    6020#define DMA_LISR_HTIF2_Pos (20U)
    -
    6021#define DMA_LISR_HTIF2_Msk (0x1UL << DMA_LISR_HTIF2_Pos)
    -
    6022#define DMA_LISR_HTIF2 DMA_LISR_HTIF2_Msk
    -
    6023#define DMA_LISR_TEIF2_Pos (19U)
    -
    6024#define DMA_LISR_TEIF2_Msk (0x1UL << DMA_LISR_TEIF2_Pos)
    -
    6025#define DMA_LISR_TEIF2 DMA_LISR_TEIF2_Msk
    -
    6026#define DMA_LISR_DMEIF2_Pos (18U)
    -
    6027#define DMA_LISR_DMEIF2_Msk (0x1UL << DMA_LISR_DMEIF2_Pos)
    -
    6028#define DMA_LISR_DMEIF2 DMA_LISR_DMEIF2_Msk
    -
    6029#define DMA_LISR_FEIF2_Pos (16U)
    -
    6030#define DMA_LISR_FEIF2_Msk (0x1UL << DMA_LISR_FEIF2_Pos)
    -
    6031#define DMA_LISR_FEIF2 DMA_LISR_FEIF2_Msk
    -
    6032#define DMA_LISR_TCIF1_Pos (11U)
    -
    6033#define DMA_LISR_TCIF1_Msk (0x1UL << DMA_LISR_TCIF1_Pos)
    -
    6034#define DMA_LISR_TCIF1 DMA_LISR_TCIF1_Msk
    -
    6035#define DMA_LISR_HTIF1_Pos (10U)
    -
    6036#define DMA_LISR_HTIF1_Msk (0x1UL << DMA_LISR_HTIF1_Pos)
    -
    6037#define DMA_LISR_HTIF1 DMA_LISR_HTIF1_Msk
    -
    6038#define DMA_LISR_TEIF1_Pos (9U)
    -
    6039#define DMA_LISR_TEIF1_Msk (0x1UL << DMA_LISR_TEIF1_Pos)
    -
    6040#define DMA_LISR_TEIF1 DMA_LISR_TEIF1_Msk
    -
    6041#define DMA_LISR_DMEIF1_Pos (8U)
    -
    6042#define DMA_LISR_DMEIF1_Msk (0x1UL << DMA_LISR_DMEIF1_Pos)
    -
    6043#define DMA_LISR_DMEIF1 DMA_LISR_DMEIF1_Msk
    -
    6044#define DMA_LISR_FEIF1_Pos (6U)
    -
    6045#define DMA_LISR_FEIF1_Msk (0x1UL << DMA_LISR_FEIF1_Pos)
    -
    6046#define DMA_LISR_FEIF1 DMA_LISR_FEIF1_Msk
    -
    6047#define DMA_LISR_TCIF0_Pos (5U)
    -
    6048#define DMA_LISR_TCIF0_Msk (0x1UL << DMA_LISR_TCIF0_Pos)
    -
    6049#define DMA_LISR_TCIF0 DMA_LISR_TCIF0_Msk
    -
    6050#define DMA_LISR_HTIF0_Pos (4U)
    -
    6051#define DMA_LISR_HTIF0_Msk (0x1UL << DMA_LISR_HTIF0_Pos)
    -
    6052#define DMA_LISR_HTIF0 DMA_LISR_HTIF0_Msk
    -
    6053#define DMA_LISR_TEIF0_Pos (3U)
    -
    6054#define DMA_LISR_TEIF0_Msk (0x1UL << DMA_LISR_TEIF0_Pos)
    -
    6055#define DMA_LISR_TEIF0 DMA_LISR_TEIF0_Msk
    -
    6056#define DMA_LISR_DMEIF0_Pos (2U)
    -
    6057#define DMA_LISR_DMEIF0_Msk (0x1UL << DMA_LISR_DMEIF0_Pos)
    -
    6058#define DMA_LISR_DMEIF0 DMA_LISR_DMEIF0_Msk
    -
    6059#define DMA_LISR_FEIF0_Pos (0U)
    -
    6060#define DMA_LISR_FEIF0_Msk (0x1UL << DMA_LISR_FEIF0_Pos)
    -
    6061#define DMA_LISR_FEIF0 DMA_LISR_FEIF0_Msk
    -
    6062
    -
    6063/******************** Bits definition for DMA_HISR register *****************/
    -
    6064#define DMA_HISR_TCIF7_Pos (27U)
    -
    6065#define DMA_HISR_TCIF7_Msk (0x1UL << DMA_HISR_TCIF7_Pos)
    -
    6066#define DMA_HISR_TCIF7 DMA_HISR_TCIF7_Msk
    -
    6067#define DMA_HISR_HTIF7_Pos (26U)
    -
    6068#define DMA_HISR_HTIF7_Msk (0x1UL << DMA_HISR_HTIF7_Pos)
    -
    6069#define DMA_HISR_HTIF7 DMA_HISR_HTIF7_Msk
    -
    6070#define DMA_HISR_TEIF7_Pos (25U)
    -
    6071#define DMA_HISR_TEIF7_Msk (0x1UL << DMA_HISR_TEIF7_Pos)
    -
    6072#define DMA_HISR_TEIF7 DMA_HISR_TEIF7_Msk
    -
    6073#define DMA_HISR_DMEIF7_Pos (24U)
    -
    6074#define DMA_HISR_DMEIF7_Msk (0x1UL << DMA_HISR_DMEIF7_Pos)
    -
    6075#define DMA_HISR_DMEIF7 DMA_HISR_DMEIF7_Msk
    -
    6076#define DMA_HISR_FEIF7_Pos (22U)
    -
    6077#define DMA_HISR_FEIF7_Msk (0x1UL << DMA_HISR_FEIF7_Pos)
    -
    6078#define DMA_HISR_FEIF7 DMA_HISR_FEIF7_Msk
    -
    6079#define DMA_HISR_TCIF6_Pos (21U)
    -
    6080#define DMA_HISR_TCIF6_Msk (0x1UL << DMA_HISR_TCIF6_Pos)
    -
    6081#define DMA_HISR_TCIF6 DMA_HISR_TCIF6_Msk
    -
    6082#define DMA_HISR_HTIF6_Pos (20U)
    -
    6083#define DMA_HISR_HTIF6_Msk (0x1UL << DMA_HISR_HTIF6_Pos)
    -
    6084#define DMA_HISR_HTIF6 DMA_HISR_HTIF6_Msk
    -
    6085#define DMA_HISR_TEIF6_Pos (19U)
    -
    6086#define DMA_HISR_TEIF6_Msk (0x1UL << DMA_HISR_TEIF6_Pos)
    -
    6087#define DMA_HISR_TEIF6 DMA_HISR_TEIF6_Msk
    -
    6088#define DMA_HISR_DMEIF6_Pos (18U)
    -
    6089#define DMA_HISR_DMEIF6_Msk (0x1UL << DMA_HISR_DMEIF6_Pos)
    -
    6090#define DMA_HISR_DMEIF6 DMA_HISR_DMEIF6_Msk
    -
    6091#define DMA_HISR_FEIF6_Pos (16U)
    -
    6092#define DMA_HISR_FEIF6_Msk (0x1UL << DMA_HISR_FEIF6_Pos)
    -
    6093#define DMA_HISR_FEIF6 DMA_HISR_FEIF6_Msk
    -
    6094#define DMA_HISR_TCIF5_Pos (11U)
    -
    6095#define DMA_HISR_TCIF5_Msk (0x1UL << DMA_HISR_TCIF5_Pos)
    -
    6096#define DMA_HISR_TCIF5 DMA_HISR_TCIF5_Msk
    -
    6097#define DMA_HISR_HTIF5_Pos (10U)
    -
    6098#define DMA_HISR_HTIF5_Msk (0x1UL << DMA_HISR_HTIF5_Pos)
    -
    6099#define DMA_HISR_HTIF5 DMA_HISR_HTIF5_Msk
    -
    6100#define DMA_HISR_TEIF5_Pos (9U)
    -
    6101#define DMA_HISR_TEIF5_Msk (0x1UL << DMA_HISR_TEIF5_Pos)
    -
    6102#define DMA_HISR_TEIF5 DMA_HISR_TEIF5_Msk
    -
    6103#define DMA_HISR_DMEIF5_Pos (8U)
    -
    6104#define DMA_HISR_DMEIF5_Msk (0x1UL << DMA_HISR_DMEIF5_Pos)
    -
    6105#define DMA_HISR_DMEIF5 DMA_HISR_DMEIF5_Msk
    -
    6106#define DMA_HISR_FEIF5_Pos (6U)
    -
    6107#define DMA_HISR_FEIF5_Msk (0x1UL << DMA_HISR_FEIF5_Pos)
    -
    6108#define DMA_HISR_FEIF5 DMA_HISR_FEIF5_Msk
    -
    6109#define DMA_HISR_TCIF4_Pos (5U)
    -
    6110#define DMA_HISR_TCIF4_Msk (0x1UL << DMA_HISR_TCIF4_Pos)
    -
    6111#define DMA_HISR_TCIF4 DMA_HISR_TCIF4_Msk
    -
    6112#define DMA_HISR_HTIF4_Pos (4U)
    -
    6113#define DMA_HISR_HTIF4_Msk (0x1UL << DMA_HISR_HTIF4_Pos)
    -
    6114#define DMA_HISR_HTIF4 DMA_HISR_HTIF4_Msk
    -
    6115#define DMA_HISR_TEIF4_Pos (3U)
    -
    6116#define DMA_HISR_TEIF4_Msk (0x1UL << DMA_HISR_TEIF4_Pos)
    -
    6117#define DMA_HISR_TEIF4 DMA_HISR_TEIF4_Msk
    -
    6118#define DMA_HISR_DMEIF4_Pos (2U)
    -
    6119#define DMA_HISR_DMEIF4_Msk (0x1UL << DMA_HISR_DMEIF4_Pos)
    -
    6120#define DMA_HISR_DMEIF4 DMA_HISR_DMEIF4_Msk
    -
    6121#define DMA_HISR_FEIF4_Pos (0U)
    -
    6122#define DMA_HISR_FEIF4_Msk (0x1UL << DMA_HISR_FEIF4_Pos)
    -
    6123#define DMA_HISR_FEIF4 DMA_HISR_FEIF4_Msk
    -
    6124
    -
    6125/******************** Bits definition for DMA_LIFCR register ****************/
    -
    6126#define DMA_LIFCR_CTCIF3_Pos (27U)
    -
    6127#define DMA_LIFCR_CTCIF3_Msk (0x1UL << DMA_LIFCR_CTCIF3_Pos)
    -
    6128#define DMA_LIFCR_CTCIF3 DMA_LIFCR_CTCIF3_Msk
    -
    6129#define DMA_LIFCR_CHTIF3_Pos (26U)
    -
    6130#define DMA_LIFCR_CHTIF3_Msk (0x1UL << DMA_LIFCR_CHTIF3_Pos)
    -
    6131#define DMA_LIFCR_CHTIF3 DMA_LIFCR_CHTIF3_Msk
    -
    6132#define DMA_LIFCR_CTEIF3_Pos (25U)
    -
    6133#define DMA_LIFCR_CTEIF3_Msk (0x1UL << DMA_LIFCR_CTEIF3_Pos)
    -
    6134#define DMA_LIFCR_CTEIF3 DMA_LIFCR_CTEIF3_Msk
    -
    6135#define DMA_LIFCR_CDMEIF3_Pos (24U)
    -
    6136#define DMA_LIFCR_CDMEIF3_Msk (0x1UL << DMA_LIFCR_CDMEIF3_Pos)
    -
    6137#define DMA_LIFCR_CDMEIF3 DMA_LIFCR_CDMEIF3_Msk
    -
    6138#define DMA_LIFCR_CFEIF3_Pos (22U)
    -
    6139#define DMA_LIFCR_CFEIF3_Msk (0x1UL << DMA_LIFCR_CFEIF3_Pos)
    -
    6140#define DMA_LIFCR_CFEIF3 DMA_LIFCR_CFEIF3_Msk
    -
    6141#define DMA_LIFCR_CTCIF2_Pos (21U)
    -
    6142#define DMA_LIFCR_CTCIF2_Msk (0x1UL << DMA_LIFCR_CTCIF2_Pos)
    -
    6143#define DMA_LIFCR_CTCIF2 DMA_LIFCR_CTCIF2_Msk
    -
    6144#define DMA_LIFCR_CHTIF2_Pos (20U)
    -
    6145#define DMA_LIFCR_CHTIF2_Msk (0x1UL << DMA_LIFCR_CHTIF2_Pos)
    -
    6146#define DMA_LIFCR_CHTIF2 DMA_LIFCR_CHTIF2_Msk
    -
    6147#define DMA_LIFCR_CTEIF2_Pos (19U)
    -
    6148#define DMA_LIFCR_CTEIF2_Msk (0x1UL << DMA_LIFCR_CTEIF2_Pos)
    -
    6149#define DMA_LIFCR_CTEIF2 DMA_LIFCR_CTEIF2_Msk
    -
    6150#define DMA_LIFCR_CDMEIF2_Pos (18U)
    -
    6151#define DMA_LIFCR_CDMEIF2_Msk (0x1UL << DMA_LIFCR_CDMEIF2_Pos)
    -
    6152#define DMA_LIFCR_CDMEIF2 DMA_LIFCR_CDMEIF2_Msk
    -
    6153#define DMA_LIFCR_CFEIF2_Pos (16U)
    -
    6154#define DMA_LIFCR_CFEIF2_Msk (0x1UL << DMA_LIFCR_CFEIF2_Pos)
    -
    6155#define DMA_LIFCR_CFEIF2 DMA_LIFCR_CFEIF2_Msk
    -
    6156#define DMA_LIFCR_CTCIF1_Pos (11U)
    -
    6157#define DMA_LIFCR_CTCIF1_Msk (0x1UL << DMA_LIFCR_CTCIF1_Pos)
    -
    6158#define DMA_LIFCR_CTCIF1 DMA_LIFCR_CTCIF1_Msk
    -
    6159#define DMA_LIFCR_CHTIF1_Pos (10U)
    -
    6160#define DMA_LIFCR_CHTIF1_Msk (0x1UL << DMA_LIFCR_CHTIF1_Pos)
    -
    6161#define DMA_LIFCR_CHTIF1 DMA_LIFCR_CHTIF1_Msk
    -
    6162#define DMA_LIFCR_CTEIF1_Pos (9U)
    -
    6163#define DMA_LIFCR_CTEIF1_Msk (0x1UL << DMA_LIFCR_CTEIF1_Pos)
    -
    6164#define DMA_LIFCR_CTEIF1 DMA_LIFCR_CTEIF1_Msk
    -
    6165#define DMA_LIFCR_CDMEIF1_Pos (8U)
    -
    6166#define DMA_LIFCR_CDMEIF1_Msk (0x1UL << DMA_LIFCR_CDMEIF1_Pos)
    -
    6167#define DMA_LIFCR_CDMEIF1 DMA_LIFCR_CDMEIF1_Msk
    -
    6168#define DMA_LIFCR_CFEIF1_Pos (6U)
    -
    6169#define DMA_LIFCR_CFEIF1_Msk (0x1UL << DMA_LIFCR_CFEIF1_Pos)
    -
    6170#define DMA_LIFCR_CFEIF1 DMA_LIFCR_CFEIF1_Msk
    -
    6171#define DMA_LIFCR_CTCIF0_Pos (5U)
    -
    6172#define DMA_LIFCR_CTCIF0_Msk (0x1UL << DMA_LIFCR_CTCIF0_Pos)
    -
    6173#define DMA_LIFCR_CTCIF0 DMA_LIFCR_CTCIF0_Msk
    -
    6174#define DMA_LIFCR_CHTIF0_Pos (4U)
    -
    6175#define DMA_LIFCR_CHTIF0_Msk (0x1UL << DMA_LIFCR_CHTIF0_Pos)
    -
    6176#define DMA_LIFCR_CHTIF0 DMA_LIFCR_CHTIF0_Msk
    -
    6177#define DMA_LIFCR_CTEIF0_Pos (3U)
    -
    6178#define DMA_LIFCR_CTEIF0_Msk (0x1UL << DMA_LIFCR_CTEIF0_Pos)
    -
    6179#define DMA_LIFCR_CTEIF0 DMA_LIFCR_CTEIF0_Msk
    -
    6180#define DMA_LIFCR_CDMEIF0_Pos (2U)
    -
    6181#define DMA_LIFCR_CDMEIF0_Msk (0x1UL << DMA_LIFCR_CDMEIF0_Pos)
    -
    6182#define DMA_LIFCR_CDMEIF0 DMA_LIFCR_CDMEIF0_Msk
    -
    6183#define DMA_LIFCR_CFEIF0_Pos (0U)
    -
    6184#define DMA_LIFCR_CFEIF0_Msk (0x1UL << DMA_LIFCR_CFEIF0_Pos)
    -
    6185#define DMA_LIFCR_CFEIF0 DMA_LIFCR_CFEIF0_Msk
    -
    6186
    -
    6187/******************** Bits definition for DMA_HIFCR register ****************/
    -
    6188#define DMA_HIFCR_CTCIF7_Pos (27U)
    -
    6189#define DMA_HIFCR_CTCIF7_Msk (0x1UL << DMA_HIFCR_CTCIF7_Pos)
    -
    6190#define DMA_HIFCR_CTCIF7 DMA_HIFCR_CTCIF7_Msk
    -
    6191#define DMA_HIFCR_CHTIF7_Pos (26U)
    -
    6192#define DMA_HIFCR_CHTIF7_Msk (0x1UL << DMA_HIFCR_CHTIF7_Pos)
    -
    6193#define DMA_HIFCR_CHTIF7 DMA_HIFCR_CHTIF7_Msk
    -
    6194#define DMA_HIFCR_CTEIF7_Pos (25U)
    -
    6195#define DMA_HIFCR_CTEIF7_Msk (0x1UL << DMA_HIFCR_CTEIF7_Pos)
    -
    6196#define DMA_HIFCR_CTEIF7 DMA_HIFCR_CTEIF7_Msk
    -
    6197#define DMA_HIFCR_CDMEIF7_Pos (24U)
    -
    6198#define DMA_HIFCR_CDMEIF7_Msk (0x1UL << DMA_HIFCR_CDMEIF7_Pos)
    -
    6199#define DMA_HIFCR_CDMEIF7 DMA_HIFCR_CDMEIF7_Msk
    -
    6200#define DMA_HIFCR_CFEIF7_Pos (22U)
    -
    6201#define DMA_HIFCR_CFEIF7_Msk (0x1UL << DMA_HIFCR_CFEIF7_Pos)
    -
    6202#define DMA_HIFCR_CFEIF7 DMA_HIFCR_CFEIF7_Msk
    -
    6203#define DMA_HIFCR_CTCIF6_Pos (21U)
    -
    6204#define DMA_HIFCR_CTCIF6_Msk (0x1UL << DMA_HIFCR_CTCIF6_Pos)
    -
    6205#define DMA_HIFCR_CTCIF6 DMA_HIFCR_CTCIF6_Msk
    -
    6206#define DMA_HIFCR_CHTIF6_Pos (20U)
    -
    6207#define DMA_HIFCR_CHTIF6_Msk (0x1UL << DMA_HIFCR_CHTIF6_Pos)
    -
    6208#define DMA_HIFCR_CHTIF6 DMA_HIFCR_CHTIF6_Msk
    -
    6209#define DMA_HIFCR_CTEIF6_Pos (19U)
    -
    6210#define DMA_HIFCR_CTEIF6_Msk (0x1UL << DMA_HIFCR_CTEIF6_Pos)
    -
    6211#define DMA_HIFCR_CTEIF6 DMA_HIFCR_CTEIF6_Msk
    -
    6212#define DMA_HIFCR_CDMEIF6_Pos (18U)
    -
    6213#define DMA_HIFCR_CDMEIF6_Msk (0x1UL << DMA_HIFCR_CDMEIF6_Pos)
    -
    6214#define DMA_HIFCR_CDMEIF6 DMA_HIFCR_CDMEIF6_Msk
    -
    6215#define DMA_HIFCR_CFEIF6_Pos (16U)
    -
    6216#define DMA_HIFCR_CFEIF6_Msk (0x1UL << DMA_HIFCR_CFEIF6_Pos)
    -
    6217#define DMA_HIFCR_CFEIF6 DMA_HIFCR_CFEIF6_Msk
    -
    6218#define DMA_HIFCR_CTCIF5_Pos (11U)
    -
    6219#define DMA_HIFCR_CTCIF5_Msk (0x1UL << DMA_HIFCR_CTCIF5_Pos)
    -
    6220#define DMA_HIFCR_CTCIF5 DMA_HIFCR_CTCIF5_Msk
    -
    6221#define DMA_HIFCR_CHTIF5_Pos (10U)
    -
    6222#define DMA_HIFCR_CHTIF5_Msk (0x1UL << DMA_HIFCR_CHTIF5_Pos)
    -
    6223#define DMA_HIFCR_CHTIF5 DMA_HIFCR_CHTIF5_Msk
    -
    6224#define DMA_HIFCR_CTEIF5_Pos (9U)
    -
    6225#define DMA_HIFCR_CTEIF5_Msk (0x1UL << DMA_HIFCR_CTEIF5_Pos)
    -
    6226#define DMA_HIFCR_CTEIF5 DMA_HIFCR_CTEIF5_Msk
    -
    6227#define DMA_HIFCR_CDMEIF5_Pos (8U)
    -
    6228#define DMA_HIFCR_CDMEIF5_Msk (0x1UL << DMA_HIFCR_CDMEIF5_Pos)
    -
    6229#define DMA_HIFCR_CDMEIF5 DMA_HIFCR_CDMEIF5_Msk
    -
    6230#define DMA_HIFCR_CFEIF5_Pos (6U)
    -
    6231#define DMA_HIFCR_CFEIF5_Msk (0x1UL << DMA_HIFCR_CFEIF5_Pos)
    -
    6232#define DMA_HIFCR_CFEIF5 DMA_HIFCR_CFEIF5_Msk
    -
    6233#define DMA_HIFCR_CTCIF4_Pos (5U)
    -
    6234#define DMA_HIFCR_CTCIF4_Msk (0x1UL << DMA_HIFCR_CTCIF4_Pos)
    -
    6235#define DMA_HIFCR_CTCIF4 DMA_HIFCR_CTCIF4_Msk
    -
    6236#define DMA_HIFCR_CHTIF4_Pos (4U)
    -
    6237#define DMA_HIFCR_CHTIF4_Msk (0x1UL << DMA_HIFCR_CHTIF4_Pos)
    -
    6238#define DMA_HIFCR_CHTIF4 DMA_HIFCR_CHTIF4_Msk
    -
    6239#define DMA_HIFCR_CTEIF4_Pos (3U)
    -
    6240#define DMA_HIFCR_CTEIF4_Msk (0x1UL << DMA_HIFCR_CTEIF4_Pos)
    -
    6241#define DMA_HIFCR_CTEIF4 DMA_HIFCR_CTEIF4_Msk
    -
    6242#define DMA_HIFCR_CDMEIF4_Pos (2U)
    -
    6243#define DMA_HIFCR_CDMEIF4_Msk (0x1UL << DMA_HIFCR_CDMEIF4_Pos)
    -
    6244#define DMA_HIFCR_CDMEIF4 DMA_HIFCR_CDMEIF4_Msk
    -
    6245#define DMA_HIFCR_CFEIF4_Pos (0U)
    -
    6246#define DMA_HIFCR_CFEIF4_Msk (0x1UL << DMA_HIFCR_CFEIF4_Pos)
    -
    6247#define DMA_HIFCR_CFEIF4 DMA_HIFCR_CFEIF4_Msk
    -
    6248
    -
    6249/****************** Bit definition for DMA_SxPAR register ********************/
    -
    6250#define DMA_SxPAR_PA_Pos (0U)
    -
    6251#define DMA_SxPAR_PA_Msk (0xFFFFFFFFUL << DMA_SxPAR_PA_Pos)
    -
    6252#define DMA_SxPAR_PA DMA_SxPAR_PA_Msk
    -
    6254/****************** Bit definition for DMA_SxM0AR register ********************/
    -
    6255#define DMA_SxM0AR_M0A_Pos (0U)
    -
    6256#define DMA_SxM0AR_M0A_Msk (0xFFFFFFFFUL << DMA_SxM0AR_M0A_Pos)
    -
    6257#define DMA_SxM0AR_M0A DMA_SxM0AR_M0A_Msk
    -
    6259/****************** Bit definition for DMA_SxM1AR register ********************/
    -
    6260#define DMA_SxM1AR_M1A_Pos (0U)
    -
    6261#define DMA_SxM1AR_M1A_Msk (0xFFFFFFFFUL << DMA_SxM1AR_M1A_Pos)
    -
    6262#define DMA_SxM1AR_M1A DMA_SxM1AR_M1A_Msk
    -
    6265/******************************************************************************/
    -
    6266/* */
    -
    6267/* External Interrupt/Event Controller */
    -
    6268/* */
    -
    6269/******************************************************************************/
    -
    6270/******************* Bit definition for EXTI_IMR register *******************/
    -
    6271#define EXTI_IMR_MR0_Pos (0U)
    -
    6272#define EXTI_IMR_MR0_Msk (0x1UL << EXTI_IMR_MR0_Pos)
    -
    6273#define EXTI_IMR_MR0 EXTI_IMR_MR0_Msk
    -
    6274#define EXTI_IMR_MR1_Pos (1U)
    -
    6275#define EXTI_IMR_MR1_Msk (0x1UL << EXTI_IMR_MR1_Pos)
    -
    6276#define EXTI_IMR_MR1 EXTI_IMR_MR1_Msk
    -
    6277#define EXTI_IMR_MR2_Pos (2U)
    -
    6278#define EXTI_IMR_MR2_Msk (0x1UL << EXTI_IMR_MR2_Pos)
    -
    6279#define EXTI_IMR_MR2 EXTI_IMR_MR2_Msk
    -
    6280#define EXTI_IMR_MR3_Pos (3U)
    -
    6281#define EXTI_IMR_MR3_Msk (0x1UL << EXTI_IMR_MR3_Pos)
    -
    6282#define EXTI_IMR_MR3 EXTI_IMR_MR3_Msk
    -
    6283#define EXTI_IMR_MR4_Pos (4U)
    -
    6284#define EXTI_IMR_MR4_Msk (0x1UL << EXTI_IMR_MR4_Pos)
    -
    6285#define EXTI_IMR_MR4 EXTI_IMR_MR4_Msk
    -
    6286#define EXTI_IMR_MR5_Pos (5U)
    -
    6287#define EXTI_IMR_MR5_Msk (0x1UL << EXTI_IMR_MR5_Pos)
    -
    6288#define EXTI_IMR_MR5 EXTI_IMR_MR5_Msk
    -
    6289#define EXTI_IMR_MR6_Pos (6U)
    -
    6290#define EXTI_IMR_MR6_Msk (0x1UL << EXTI_IMR_MR6_Pos)
    -
    6291#define EXTI_IMR_MR6 EXTI_IMR_MR6_Msk
    -
    6292#define EXTI_IMR_MR7_Pos (7U)
    -
    6293#define EXTI_IMR_MR7_Msk (0x1UL << EXTI_IMR_MR7_Pos)
    -
    6294#define EXTI_IMR_MR7 EXTI_IMR_MR7_Msk
    -
    6295#define EXTI_IMR_MR8_Pos (8U)
    -
    6296#define EXTI_IMR_MR8_Msk (0x1UL << EXTI_IMR_MR8_Pos)
    -
    6297#define EXTI_IMR_MR8 EXTI_IMR_MR8_Msk
    -
    6298#define EXTI_IMR_MR9_Pos (9U)
    -
    6299#define EXTI_IMR_MR9_Msk (0x1UL << EXTI_IMR_MR9_Pos)
    -
    6300#define EXTI_IMR_MR9 EXTI_IMR_MR9_Msk
    -
    6301#define EXTI_IMR_MR10_Pos (10U)
    -
    6302#define EXTI_IMR_MR10_Msk (0x1UL << EXTI_IMR_MR10_Pos)
    -
    6303#define EXTI_IMR_MR10 EXTI_IMR_MR10_Msk
    -
    6304#define EXTI_IMR_MR11_Pos (11U)
    -
    6305#define EXTI_IMR_MR11_Msk (0x1UL << EXTI_IMR_MR11_Pos)
    -
    6306#define EXTI_IMR_MR11 EXTI_IMR_MR11_Msk
    -
    6307#define EXTI_IMR_MR12_Pos (12U)
    -
    6308#define EXTI_IMR_MR12_Msk (0x1UL << EXTI_IMR_MR12_Pos)
    -
    6309#define EXTI_IMR_MR12 EXTI_IMR_MR12_Msk
    -
    6310#define EXTI_IMR_MR13_Pos (13U)
    -
    6311#define EXTI_IMR_MR13_Msk (0x1UL << EXTI_IMR_MR13_Pos)
    -
    6312#define EXTI_IMR_MR13 EXTI_IMR_MR13_Msk
    -
    6313#define EXTI_IMR_MR14_Pos (14U)
    -
    6314#define EXTI_IMR_MR14_Msk (0x1UL << EXTI_IMR_MR14_Pos)
    -
    6315#define EXTI_IMR_MR14 EXTI_IMR_MR14_Msk
    -
    6316#define EXTI_IMR_MR15_Pos (15U)
    -
    6317#define EXTI_IMR_MR15_Msk (0x1UL << EXTI_IMR_MR15_Pos)
    -
    6318#define EXTI_IMR_MR15 EXTI_IMR_MR15_Msk
    -
    6319#define EXTI_IMR_MR16_Pos (16U)
    -
    6320#define EXTI_IMR_MR16_Msk (0x1UL << EXTI_IMR_MR16_Pos)
    -
    6321#define EXTI_IMR_MR16 EXTI_IMR_MR16_Msk
    -
    6322#define EXTI_IMR_MR17_Pos (17U)
    -
    6323#define EXTI_IMR_MR17_Msk (0x1UL << EXTI_IMR_MR17_Pos)
    -
    6324#define EXTI_IMR_MR17 EXTI_IMR_MR17_Msk
    -
    6325#define EXTI_IMR_MR18_Pos (18U)
    -
    6326#define EXTI_IMR_MR18_Msk (0x1UL << EXTI_IMR_MR18_Pos)
    -
    6327#define EXTI_IMR_MR18 EXTI_IMR_MR18_Msk
    -
    6328#define EXTI_IMR_MR19_Pos (19U)
    -
    6329#define EXTI_IMR_MR19_Msk (0x1UL << EXTI_IMR_MR19_Pos)
    -
    6330#define EXTI_IMR_MR19 EXTI_IMR_MR19_Msk
    -
    6331#define EXTI_IMR_MR20_Pos (20U)
    -
    6332#define EXTI_IMR_MR20_Msk (0x1UL << EXTI_IMR_MR20_Pos)
    -
    6333#define EXTI_IMR_MR20 EXTI_IMR_MR20_Msk
    -
    6334#define EXTI_IMR_MR21_Pos (21U)
    -
    6335#define EXTI_IMR_MR21_Msk (0x1UL << EXTI_IMR_MR21_Pos)
    -
    6336#define EXTI_IMR_MR21 EXTI_IMR_MR21_Msk
    -
    6337#define EXTI_IMR_MR22_Pos (22U)
    -
    6338#define EXTI_IMR_MR22_Msk (0x1UL << EXTI_IMR_MR22_Pos)
    -
    6339#define EXTI_IMR_MR22 EXTI_IMR_MR22_Msk
    -
    6341/* Reference Defines */
    -
    6342#define EXTI_IMR_IM0 EXTI_IMR_MR0
    -
    6343#define EXTI_IMR_IM1 EXTI_IMR_MR1
    -
    6344#define EXTI_IMR_IM2 EXTI_IMR_MR2
    -
    6345#define EXTI_IMR_IM3 EXTI_IMR_MR3
    -
    6346#define EXTI_IMR_IM4 EXTI_IMR_MR4
    -
    6347#define EXTI_IMR_IM5 EXTI_IMR_MR5
    -
    6348#define EXTI_IMR_IM6 EXTI_IMR_MR6
    -
    6349#define EXTI_IMR_IM7 EXTI_IMR_MR7
    -
    6350#define EXTI_IMR_IM8 EXTI_IMR_MR8
    -
    6351#define EXTI_IMR_IM9 EXTI_IMR_MR9
    -
    6352#define EXTI_IMR_IM10 EXTI_IMR_MR10
    -
    6353#define EXTI_IMR_IM11 EXTI_IMR_MR11
    -
    6354#define EXTI_IMR_IM12 EXTI_IMR_MR12
    -
    6355#define EXTI_IMR_IM13 EXTI_IMR_MR13
    -
    6356#define EXTI_IMR_IM14 EXTI_IMR_MR14
    -
    6357#define EXTI_IMR_IM15 EXTI_IMR_MR15
    -
    6358#define EXTI_IMR_IM16 EXTI_IMR_MR16
    -
    6359#define EXTI_IMR_IM17 EXTI_IMR_MR17
    -
    6360#define EXTI_IMR_IM18 EXTI_IMR_MR18
    -
    6361#define EXTI_IMR_IM19 EXTI_IMR_MR19
    -
    6362#define EXTI_IMR_IM20 EXTI_IMR_MR20
    -
    6363#define EXTI_IMR_IM21 EXTI_IMR_MR21
    -
    6364#define EXTI_IMR_IM22 EXTI_IMR_MR22
    -
    6365#define EXTI_IMR_IM_Pos (0U)
    -
    6366#define EXTI_IMR_IM_Msk (0x7FFFFFUL << EXTI_IMR_IM_Pos)
    -
    6367#define EXTI_IMR_IM EXTI_IMR_IM_Msk
    -
    6369/******************* Bit definition for EXTI_EMR register *******************/
    -
    6370#define EXTI_EMR_MR0_Pos (0U)
    -
    6371#define EXTI_EMR_MR0_Msk (0x1UL << EXTI_EMR_MR0_Pos)
    -
    6372#define EXTI_EMR_MR0 EXTI_EMR_MR0_Msk
    -
    6373#define EXTI_EMR_MR1_Pos (1U)
    -
    6374#define EXTI_EMR_MR1_Msk (0x1UL << EXTI_EMR_MR1_Pos)
    -
    6375#define EXTI_EMR_MR1 EXTI_EMR_MR1_Msk
    -
    6376#define EXTI_EMR_MR2_Pos (2U)
    -
    6377#define EXTI_EMR_MR2_Msk (0x1UL << EXTI_EMR_MR2_Pos)
    -
    6378#define EXTI_EMR_MR2 EXTI_EMR_MR2_Msk
    -
    6379#define EXTI_EMR_MR3_Pos (3U)
    -
    6380#define EXTI_EMR_MR3_Msk (0x1UL << EXTI_EMR_MR3_Pos)
    -
    6381#define EXTI_EMR_MR3 EXTI_EMR_MR3_Msk
    -
    6382#define EXTI_EMR_MR4_Pos (4U)
    -
    6383#define EXTI_EMR_MR4_Msk (0x1UL << EXTI_EMR_MR4_Pos)
    -
    6384#define EXTI_EMR_MR4 EXTI_EMR_MR4_Msk
    -
    6385#define EXTI_EMR_MR5_Pos (5U)
    -
    6386#define EXTI_EMR_MR5_Msk (0x1UL << EXTI_EMR_MR5_Pos)
    -
    6387#define EXTI_EMR_MR5 EXTI_EMR_MR5_Msk
    -
    6388#define EXTI_EMR_MR6_Pos (6U)
    -
    6389#define EXTI_EMR_MR6_Msk (0x1UL << EXTI_EMR_MR6_Pos)
    -
    6390#define EXTI_EMR_MR6 EXTI_EMR_MR6_Msk
    -
    6391#define EXTI_EMR_MR7_Pos (7U)
    -
    6392#define EXTI_EMR_MR7_Msk (0x1UL << EXTI_EMR_MR7_Pos)
    -
    6393#define EXTI_EMR_MR7 EXTI_EMR_MR7_Msk
    -
    6394#define EXTI_EMR_MR8_Pos (8U)
    -
    6395#define EXTI_EMR_MR8_Msk (0x1UL << EXTI_EMR_MR8_Pos)
    -
    6396#define EXTI_EMR_MR8 EXTI_EMR_MR8_Msk
    -
    6397#define EXTI_EMR_MR9_Pos (9U)
    -
    6398#define EXTI_EMR_MR9_Msk (0x1UL << EXTI_EMR_MR9_Pos)
    -
    6399#define EXTI_EMR_MR9 EXTI_EMR_MR9_Msk
    -
    6400#define EXTI_EMR_MR10_Pos (10U)
    -
    6401#define EXTI_EMR_MR10_Msk (0x1UL << EXTI_EMR_MR10_Pos)
    -
    6402#define EXTI_EMR_MR10 EXTI_EMR_MR10_Msk
    -
    6403#define EXTI_EMR_MR11_Pos (11U)
    -
    6404#define EXTI_EMR_MR11_Msk (0x1UL << EXTI_EMR_MR11_Pos)
    -
    6405#define EXTI_EMR_MR11 EXTI_EMR_MR11_Msk
    -
    6406#define EXTI_EMR_MR12_Pos (12U)
    -
    6407#define EXTI_EMR_MR12_Msk (0x1UL << EXTI_EMR_MR12_Pos)
    -
    6408#define EXTI_EMR_MR12 EXTI_EMR_MR12_Msk
    -
    6409#define EXTI_EMR_MR13_Pos (13U)
    -
    6410#define EXTI_EMR_MR13_Msk (0x1UL << EXTI_EMR_MR13_Pos)
    -
    6411#define EXTI_EMR_MR13 EXTI_EMR_MR13_Msk
    -
    6412#define EXTI_EMR_MR14_Pos (14U)
    -
    6413#define EXTI_EMR_MR14_Msk (0x1UL << EXTI_EMR_MR14_Pos)
    -
    6414#define EXTI_EMR_MR14 EXTI_EMR_MR14_Msk
    -
    6415#define EXTI_EMR_MR15_Pos (15U)
    -
    6416#define EXTI_EMR_MR15_Msk (0x1UL << EXTI_EMR_MR15_Pos)
    -
    6417#define EXTI_EMR_MR15 EXTI_EMR_MR15_Msk
    -
    6418#define EXTI_EMR_MR16_Pos (16U)
    -
    6419#define EXTI_EMR_MR16_Msk (0x1UL << EXTI_EMR_MR16_Pos)
    -
    6420#define EXTI_EMR_MR16 EXTI_EMR_MR16_Msk
    -
    6421#define EXTI_EMR_MR17_Pos (17U)
    -
    6422#define EXTI_EMR_MR17_Msk (0x1UL << EXTI_EMR_MR17_Pos)
    -
    6423#define EXTI_EMR_MR17 EXTI_EMR_MR17_Msk
    -
    6424#define EXTI_EMR_MR18_Pos (18U)
    -
    6425#define EXTI_EMR_MR18_Msk (0x1UL << EXTI_EMR_MR18_Pos)
    -
    6426#define EXTI_EMR_MR18 EXTI_EMR_MR18_Msk
    -
    6427#define EXTI_EMR_MR19_Pos (19U)
    -
    6428#define EXTI_EMR_MR19_Msk (0x1UL << EXTI_EMR_MR19_Pos)
    -
    6429#define EXTI_EMR_MR19 EXTI_EMR_MR19_Msk
    -
    6430#define EXTI_EMR_MR20_Pos (20U)
    -
    6431#define EXTI_EMR_MR20_Msk (0x1UL << EXTI_EMR_MR20_Pos)
    -
    6432#define EXTI_EMR_MR20 EXTI_EMR_MR20_Msk
    -
    6433#define EXTI_EMR_MR21_Pos (21U)
    -
    6434#define EXTI_EMR_MR21_Msk (0x1UL << EXTI_EMR_MR21_Pos)
    -
    6435#define EXTI_EMR_MR21 EXTI_EMR_MR21_Msk
    -
    6436#define EXTI_EMR_MR22_Pos (22U)
    -
    6437#define EXTI_EMR_MR22_Msk (0x1UL << EXTI_EMR_MR22_Pos)
    -
    6438#define EXTI_EMR_MR22 EXTI_EMR_MR22_Msk
    -
    6440/* Reference Defines */
    -
    6441#define EXTI_EMR_EM0 EXTI_EMR_MR0
    -
    6442#define EXTI_EMR_EM1 EXTI_EMR_MR1
    -
    6443#define EXTI_EMR_EM2 EXTI_EMR_MR2
    -
    6444#define EXTI_EMR_EM3 EXTI_EMR_MR3
    -
    6445#define EXTI_EMR_EM4 EXTI_EMR_MR4
    -
    6446#define EXTI_EMR_EM5 EXTI_EMR_MR5
    -
    6447#define EXTI_EMR_EM6 EXTI_EMR_MR6
    -
    6448#define EXTI_EMR_EM7 EXTI_EMR_MR7
    -
    6449#define EXTI_EMR_EM8 EXTI_EMR_MR8
    -
    6450#define EXTI_EMR_EM9 EXTI_EMR_MR9
    -
    6451#define EXTI_EMR_EM10 EXTI_EMR_MR10
    -
    6452#define EXTI_EMR_EM11 EXTI_EMR_MR11
    -
    6453#define EXTI_EMR_EM12 EXTI_EMR_MR12
    -
    6454#define EXTI_EMR_EM13 EXTI_EMR_MR13
    -
    6455#define EXTI_EMR_EM14 EXTI_EMR_MR14
    -
    6456#define EXTI_EMR_EM15 EXTI_EMR_MR15
    -
    6457#define EXTI_EMR_EM16 EXTI_EMR_MR16
    -
    6458#define EXTI_EMR_EM17 EXTI_EMR_MR17
    -
    6459#define EXTI_EMR_EM18 EXTI_EMR_MR18
    -
    6460#define EXTI_EMR_EM19 EXTI_EMR_MR19
    -
    6461#define EXTI_EMR_EM20 EXTI_EMR_MR20
    -
    6462#define EXTI_EMR_EM21 EXTI_EMR_MR21
    -
    6463#define EXTI_EMR_EM22 EXTI_EMR_MR22
    -
    6464
    -
    6465/****************** Bit definition for EXTI_RTSR register *******************/
    -
    6466#define EXTI_RTSR_TR0_Pos (0U)
    -
    6467#define EXTI_RTSR_TR0_Msk (0x1UL << EXTI_RTSR_TR0_Pos)
    -
    6468#define EXTI_RTSR_TR0 EXTI_RTSR_TR0_Msk
    -
    6469#define EXTI_RTSR_TR1_Pos (1U)
    -
    6470#define EXTI_RTSR_TR1_Msk (0x1UL << EXTI_RTSR_TR1_Pos)
    -
    6471#define EXTI_RTSR_TR1 EXTI_RTSR_TR1_Msk
    -
    6472#define EXTI_RTSR_TR2_Pos (2U)
    -
    6473#define EXTI_RTSR_TR2_Msk (0x1UL << EXTI_RTSR_TR2_Pos)
    -
    6474#define EXTI_RTSR_TR2 EXTI_RTSR_TR2_Msk
    -
    6475#define EXTI_RTSR_TR3_Pos (3U)
    -
    6476#define EXTI_RTSR_TR3_Msk (0x1UL << EXTI_RTSR_TR3_Pos)
    -
    6477#define EXTI_RTSR_TR3 EXTI_RTSR_TR3_Msk
    -
    6478#define EXTI_RTSR_TR4_Pos (4U)
    -
    6479#define EXTI_RTSR_TR4_Msk (0x1UL << EXTI_RTSR_TR4_Pos)
    -
    6480#define EXTI_RTSR_TR4 EXTI_RTSR_TR4_Msk
    -
    6481#define EXTI_RTSR_TR5_Pos (5U)
    -
    6482#define EXTI_RTSR_TR5_Msk (0x1UL << EXTI_RTSR_TR5_Pos)
    -
    6483#define EXTI_RTSR_TR5 EXTI_RTSR_TR5_Msk
    -
    6484#define EXTI_RTSR_TR6_Pos (6U)
    -
    6485#define EXTI_RTSR_TR6_Msk (0x1UL << EXTI_RTSR_TR6_Pos)
    -
    6486#define EXTI_RTSR_TR6 EXTI_RTSR_TR6_Msk
    -
    6487#define EXTI_RTSR_TR7_Pos (7U)
    -
    6488#define EXTI_RTSR_TR7_Msk (0x1UL << EXTI_RTSR_TR7_Pos)
    -
    6489#define EXTI_RTSR_TR7 EXTI_RTSR_TR7_Msk
    -
    6490#define EXTI_RTSR_TR8_Pos (8U)
    -
    6491#define EXTI_RTSR_TR8_Msk (0x1UL << EXTI_RTSR_TR8_Pos)
    -
    6492#define EXTI_RTSR_TR8 EXTI_RTSR_TR8_Msk
    -
    6493#define EXTI_RTSR_TR9_Pos (9U)
    -
    6494#define EXTI_RTSR_TR9_Msk (0x1UL << EXTI_RTSR_TR9_Pos)
    -
    6495#define EXTI_RTSR_TR9 EXTI_RTSR_TR9_Msk
    -
    6496#define EXTI_RTSR_TR10_Pos (10U)
    -
    6497#define EXTI_RTSR_TR10_Msk (0x1UL << EXTI_RTSR_TR10_Pos)
    -
    6498#define EXTI_RTSR_TR10 EXTI_RTSR_TR10_Msk
    -
    6499#define EXTI_RTSR_TR11_Pos (11U)
    -
    6500#define EXTI_RTSR_TR11_Msk (0x1UL << EXTI_RTSR_TR11_Pos)
    -
    6501#define EXTI_RTSR_TR11 EXTI_RTSR_TR11_Msk
    -
    6502#define EXTI_RTSR_TR12_Pos (12U)
    -
    6503#define EXTI_RTSR_TR12_Msk (0x1UL << EXTI_RTSR_TR12_Pos)
    -
    6504#define EXTI_RTSR_TR12 EXTI_RTSR_TR12_Msk
    -
    6505#define EXTI_RTSR_TR13_Pos (13U)
    -
    6506#define EXTI_RTSR_TR13_Msk (0x1UL << EXTI_RTSR_TR13_Pos)
    -
    6507#define EXTI_RTSR_TR13 EXTI_RTSR_TR13_Msk
    -
    6508#define EXTI_RTSR_TR14_Pos (14U)
    -
    6509#define EXTI_RTSR_TR14_Msk (0x1UL << EXTI_RTSR_TR14_Pos)
    -
    6510#define EXTI_RTSR_TR14 EXTI_RTSR_TR14_Msk
    -
    6511#define EXTI_RTSR_TR15_Pos (15U)
    -
    6512#define EXTI_RTSR_TR15_Msk (0x1UL << EXTI_RTSR_TR15_Pos)
    -
    6513#define EXTI_RTSR_TR15 EXTI_RTSR_TR15_Msk
    -
    6514#define EXTI_RTSR_TR16_Pos (16U)
    -
    6515#define EXTI_RTSR_TR16_Msk (0x1UL << EXTI_RTSR_TR16_Pos)
    -
    6516#define EXTI_RTSR_TR16 EXTI_RTSR_TR16_Msk
    -
    6517#define EXTI_RTSR_TR17_Pos (17U)
    -
    6518#define EXTI_RTSR_TR17_Msk (0x1UL << EXTI_RTSR_TR17_Pos)
    -
    6519#define EXTI_RTSR_TR17 EXTI_RTSR_TR17_Msk
    -
    6520#define EXTI_RTSR_TR18_Pos (18U)
    -
    6521#define EXTI_RTSR_TR18_Msk (0x1UL << EXTI_RTSR_TR18_Pos)
    -
    6522#define EXTI_RTSR_TR18 EXTI_RTSR_TR18_Msk
    -
    6523#define EXTI_RTSR_TR19_Pos (19U)
    -
    6524#define EXTI_RTSR_TR19_Msk (0x1UL << EXTI_RTSR_TR19_Pos)
    -
    6525#define EXTI_RTSR_TR19 EXTI_RTSR_TR19_Msk
    -
    6526#define EXTI_RTSR_TR20_Pos (20U)
    -
    6527#define EXTI_RTSR_TR20_Msk (0x1UL << EXTI_RTSR_TR20_Pos)
    -
    6528#define EXTI_RTSR_TR20 EXTI_RTSR_TR20_Msk
    -
    6529#define EXTI_RTSR_TR21_Pos (21U)
    -
    6530#define EXTI_RTSR_TR21_Msk (0x1UL << EXTI_RTSR_TR21_Pos)
    -
    6531#define EXTI_RTSR_TR21 EXTI_RTSR_TR21_Msk
    -
    6532#define EXTI_RTSR_TR22_Pos (22U)
    -
    6533#define EXTI_RTSR_TR22_Msk (0x1UL << EXTI_RTSR_TR22_Pos)
    -
    6534#define EXTI_RTSR_TR22 EXTI_RTSR_TR22_Msk
    -
    6536/****************** Bit definition for EXTI_FTSR register *******************/
    -
    6537#define EXTI_FTSR_TR0_Pos (0U)
    -
    6538#define EXTI_FTSR_TR0_Msk (0x1UL << EXTI_FTSR_TR0_Pos)
    -
    6539#define EXTI_FTSR_TR0 EXTI_FTSR_TR0_Msk
    -
    6540#define EXTI_FTSR_TR1_Pos (1U)
    -
    6541#define EXTI_FTSR_TR1_Msk (0x1UL << EXTI_FTSR_TR1_Pos)
    -
    6542#define EXTI_FTSR_TR1 EXTI_FTSR_TR1_Msk
    -
    6543#define EXTI_FTSR_TR2_Pos (2U)
    -
    6544#define EXTI_FTSR_TR2_Msk (0x1UL << EXTI_FTSR_TR2_Pos)
    -
    6545#define EXTI_FTSR_TR2 EXTI_FTSR_TR2_Msk
    -
    6546#define EXTI_FTSR_TR3_Pos (3U)
    -
    6547#define EXTI_FTSR_TR3_Msk (0x1UL << EXTI_FTSR_TR3_Pos)
    -
    6548#define EXTI_FTSR_TR3 EXTI_FTSR_TR3_Msk
    -
    6549#define EXTI_FTSR_TR4_Pos (4U)
    -
    6550#define EXTI_FTSR_TR4_Msk (0x1UL << EXTI_FTSR_TR4_Pos)
    -
    6551#define EXTI_FTSR_TR4 EXTI_FTSR_TR4_Msk
    -
    6552#define EXTI_FTSR_TR5_Pos (5U)
    -
    6553#define EXTI_FTSR_TR5_Msk (0x1UL << EXTI_FTSR_TR5_Pos)
    -
    6554#define EXTI_FTSR_TR5 EXTI_FTSR_TR5_Msk
    -
    6555#define EXTI_FTSR_TR6_Pos (6U)
    -
    6556#define EXTI_FTSR_TR6_Msk (0x1UL << EXTI_FTSR_TR6_Pos)
    -
    6557#define EXTI_FTSR_TR6 EXTI_FTSR_TR6_Msk
    -
    6558#define EXTI_FTSR_TR7_Pos (7U)
    -
    6559#define EXTI_FTSR_TR7_Msk (0x1UL << EXTI_FTSR_TR7_Pos)
    -
    6560#define EXTI_FTSR_TR7 EXTI_FTSR_TR7_Msk
    -
    6561#define EXTI_FTSR_TR8_Pos (8U)
    -
    6562#define EXTI_FTSR_TR8_Msk (0x1UL << EXTI_FTSR_TR8_Pos)
    -
    6563#define EXTI_FTSR_TR8 EXTI_FTSR_TR8_Msk
    -
    6564#define EXTI_FTSR_TR9_Pos (9U)
    -
    6565#define EXTI_FTSR_TR9_Msk (0x1UL << EXTI_FTSR_TR9_Pos)
    -
    6566#define EXTI_FTSR_TR9 EXTI_FTSR_TR9_Msk
    -
    6567#define EXTI_FTSR_TR10_Pos (10U)
    -
    6568#define EXTI_FTSR_TR10_Msk (0x1UL << EXTI_FTSR_TR10_Pos)
    -
    6569#define EXTI_FTSR_TR10 EXTI_FTSR_TR10_Msk
    -
    6570#define EXTI_FTSR_TR11_Pos (11U)
    -
    6571#define EXTI_FTSR_TR11_Msk (0x1UL << EXTI_FTSR_TR11_Pos)
    -
    6572#define EXTI_FTSR_TR11 EXTI_FTSR_TR11_Msk
    -
    6573#define EXTI_FTSR_TR12_Pos (12U)
    -
    6574#define EXTI_FTSR_TR12_Msk (0x1UL << EXTI_FTSR_TR12_Pos)
    -
    6575#define EXTI_FTSR_TR12 EXTI_FTSR_TR12_Msk
    -
    6576#define EXTI_FTSR_TR13_Pos (13U)
    -
    6577#define EXTI_FTSR_TR13_Msk (0x1UL << EXTI_FTSR_TR13_Pos)
    -
    6578#define EXTI_FTSR_TR13 EXTI_FTSR_TR13_Msk
    -
    6579#define EXTI_FTSR_TR14_Pos (14U)
    -
    6580#define EXTI_FTSR_TR14_Msk (0x1UL << EXTI_FTSR_TR14_Pos)
    -
    6581#define EXTI_FTSR_TR14 EXTI_FTSR_TR14_Msk
    -
    6582#define EXTI_FTSR_TR15_Pos (15U)
    -
    6583#define EXTI_FTSR_TR15_Msk (0x1UL << EXTI_FTSR_TR15_Pos)
    -
    6584#define EXTI_FTSR_TR15 EXTI_FTSR_TR15_Msk
    -
    6585#define EXTI_FTSR_TR16_Pos (16U)
    -
    6586#define EXTI_FTSR_TR16_Msk (0x1UL << EXTI_FTSR_TR16_Pos)
    -
    6587#define EXTI_FTSR_TR16 EXTI_FTSR_TR16_Msk
    -
    6588#define EXTI_FTSR_TR17_Pos (17U)
    -
    6589#define EXTI_FTSR_TR17_Msk (0x1UL << EXTI_FTSR_TR17_Pos)
    -
    6590#define EXTI_FTSR_TR17 EXTI_FTSR_TR17_Msk
    -
    6591#define EXTI_FTSR_TR18_Pos (18U)
    -
    6592#define EXTI_FTSR_TR18_Msk (0x1UL << EXTI_FTSR_TR18_Pos)
    -
    6593#define EXTI_FTSR_TR18 EXTI_FTSR_TR18_Msk
    -
    6594#define EXTI_FTSR_TR19_Pos (19U)
    -
    6595#define EXTI_FTSR_TR19_Msk (0x1UL << EXTI_FTSR_TR19_Pos)
    -
    6596#define EXTI_FTSR_TR19 EXTI_FTSR_TR19_Msk
    -
    6597#define EXTI_FTSR_TR20_Pos (20U)
    -
    6598#define EXTI_FTSR_TR20_Msk (0x1UL << EXTI_FTSR_TR20_Pos)
    -
    6599#define EXTI_FTSR_TR20 EXTI_FTSR_TR20_Msk
    -
    6600#define EXTI_FTSR_TR21_Pos (21U)
    -
    6601#define EXTI_FTSR_TR21_Msk (0x1UL << EXTI_FTSR_TR21_Pos)
    -
    6602#define EXTI_FTSR_TR21 EXTI_FTSR_TR21_Msk
    -
    6603#define EXTI_FTSR_TR22_Pos (22U)
    -
    6604#define EXTI_FTSR_TR22_Msk (0x1UL << EXTI_FTSR_TR22_Pos)
    -
    6605#define EXTI_FTSR_TR22 EXTI_FTSR_TR22_Msk
    -
    6607/****************** Bit definition for EXTI_SWIER register ******************/
    -
    6608#define EXTI_SWIER_SWIER0_Pos (0U)
    -
    6609#define EXTI_SWIER_SWIER0_Msk (0x1UL << EXTI_SWIER_SWIER0_Pos)
    -
    6610#define EXTI_SWIER_SWIER0 EXTI_SWIER_SWIER0_Msk
    -
    6611#define EXTI_SWIER_SWIER1_Pos (1U)
    -
    6612#define EXTI_SWIER_SWIER1_Msk (0x1UL << EXTI_SWIER_SWIER1_Pos)
    -
    6613#define EXTI_SWIER_SWIER1 EXTI_SWIER_SWIER1_Msk
    -
    6614#define EXTI_SWIER_SWIER2_Pos (2U)
    -
    6615#define EXTI_SWIER_SWIER2_Msk (0x1UL << EXTI_SWIER_SWIER2_Pos)
    -
    6616#define EXTI_SWIER_SWIER2 EXTI_SWIER_SWIER2_Msk
    -
    6617#define EXTI_SWIER_SWIER3_Pos (3U)
    -
    6618#define EXTI_SWIER_SWIER3_Msk (0x1UL << EXTI_SWIER_SWIER3_Pos)
    -
    6619#define EXTI_SWIER_SWIER3 EXTI_SWIER_SWIER3_Msk
    -
    6620#define EXTI_SWIER_SWIER4_Pos (4U)
    -
    6621#define EXTI_SWIER_SWIER4_Msk (0x1UL << EXTI_SWIER_SWIER4_Pos)
    -
    6622#define EXTI_SWIER_SWIER4 EXTI_SWIER_SWIER4_Msk
    -
    6623#define EXTI_SWIER_SWIER5_Pos (5U)
    -
    6624#define EXTI_SWIER_SWIER5_Msk (0x1UL << EXTI_SWIER_SWIER5_Pos)
    -
    6625#define EXTI_SWIER_SWIER5 EXTI_SWIER_SWIER5_Msk
    -
    6626#define EXTI_SWIER_SWIER6_Pos (6U)
    -
    6627#define EXTI_SWIER_SWIER6_Msk (0x1UL << EXTI_SWIER_SWIER6_Pos)
    -
    6628#define EXTI_SWIER_SWIER6 EXTI_SWIER_SWIER6_Msk
    -
    6629#define EXTI_SWIER_SWIER7_Pos (7U)
    -
    6630#define EXTI_SWIER_SWIER7_Msk (0x1UL << EXTI_SWIER_SWIER7_Pos)
    -
    6631#define EXTI_SWIER_SWIER7 EXTI_SWIER_SWIER7_Msk
    -
    6632#define EXTI_SWIER_SWIER8_Pos (8U)
    -
    6633#define EXTI_SWIER_SWIER8_Msk (0x1UL << EXTI_SWIER_SWIER8_Pos)
    -
    6634#define EXTI_SWIER_SWIER8 EXTI_SWIER_SWIER8_Msk
    -
    6635#define EXTI_SWIER_SWIER9_Pos (9U)
    -
    6636#define EXTI_SWIER_SWIER9_Msk (0x1UL << EXTI_SWIER_SWIER9_Pos)
    -
    6637#define EXTI_SWIER_SWIER9 EXTI_SWIER_SWIER9_Msk
    -
    6638#define EXTI_SWIER_SWIER10_Pos (10U)
    -
    6639#define EXTI_SWIER_SWIER10_Msk (0x1UL << EXTI_SWIER_SWIER10_Pos)
    -
    6640#define EXTI_SWIER_SWIER10 EXTI_SWIER_SWIER10_Msk
    -
    6641#define EXTI_SWIER_SWIER11_Pos (11U)
    -
    6642#define EXTI_SWIER_SWIER11_Msk (0x1UL << EXTI_SWIER_SWIER11_Pos)
    -
    6643#define EXTI_SWIER_SWIER11 EXTI_SWIER_SWIER11_Msk
    -
    6644#define EXTI_SWIER_SWIER12_Pos (12U)
    -
    6645#define EXTI_SWIER_SWIER12_Msk (0x1UL << EXTI_SWIER_SWIER12_Pos)
    -
    6646#define EXTI_SWIER_SWIER12 EXTI_SWIER_SWIER12_Msk
    -
    6647#define EXTI_SWIER_SWIER13_Pos (13U)
    -
    6648#define EXTI_SWIER_SWIER13_Msk (0x1UL << EXTI_SWIER_SWIER13_Pos)
    -
    6649#define EXTI_SWIER_SWIER13 EXTI_SWIER_SWIER13_Msk
    -
    6650#define EXTI_SWIER_SWIER14_Pos (14U)
    -
    6651#define EXTI_SWIER_SWIER14_Msk (0x1UL << EXTI_SWIER_SWIER14_Pos)
    -
    6652#define EXTI_SWIER_SWIER14 EXTI_SWIER_SWIER14_Msk
    -
    6653#define EXTI_SWIER_SWIER15_Pos (15U)
    -
    6654#define EXTI_SWIER_SWIER15_Msk (0x1UL << EXTI_SWIER_SWIER15_Pos)
    -
    6655#define EXTI_SWIER_SWIER15 EXTI_SWIER_SWIER15_Msk
    -
    6656#define EXTI_SWIER_SWIER16_Pos (16U)
    -
    6657#define EXTI_SWIER_SWIER16_Msk (0x1UL << EXTI_SWIER_SWIER16_Pos)
    -
    6658#define EXTI_SWIER_SWIER16 EXTI_SWIER_SWIER16_Msk
    -
    6659#define EXTI_SWIER_SWIER17_Pos (17U)
    -
    6660#define EXTI_SWIER_SWIER17_Msk (0x1UL << EXTI_SWIER_SWIER17_Pos)
    -
    6661#define EXTI_SWIER_SWIER17 EXTI_SWIER_SWIER17_Msk
    -
    6662#define EXTI_SWIER_SWIER18_Pos (18U)
    -
    6663#define EXTI_SWIER_SWIER18_Msk (0x1UL << EXTI_SWIER_SWIER18_Pos)
    -
    6664#define EXTI_SWIER_SWIER18 EXTI_SWIER_SWIER18_Msk
    -
    6665#define EXTI_SWIER_SWIER19_Pos (19U)
    -
    6666#define EXTI_SWIER_SWIER19_Msk (0x1UL << EXTI_SWIER_SWIER19_Pos)
    -
    6667#define EXTI_SWIER_SWIER19 EXTI_SWIER_SWIER19_Msk
    -
    6668#define EXTI_SWIER_SWIER20_Pos (20U)
    -
    6669#define EXTI_SWIER_SWIER20_Msk (0x1UL << EXTI_SWIER_SWIER20_Pos)
    -
    6670#define EXTI_SWIER_SWIER20 EXTI_SWIER_SWIER20_Msk
    -
    6671#define EXTI_SWIER_SWIER21_Pos (21U)
    -
    6672#define EXTI_SWIER_SWIER21_Msk (0x1UL << EXTI_SWIER_SWIER21_Pos)
    -
    6673#define EXTI_SWIER_SWIER21 EXTI_SWIER_SWIER21_Msk
    -
    6674#define EXTI_SWIER_SWIER22_Pos (22U)
    -
    6675#define EXTI_SWIER_SWIER22_Msk (0x1UL << EXTI_SWIER_SWIER22_Pos)
    -
    6676#define EXTI_SWIER_SWIER22 EXTI_SWIER_SWIER22_Msk
    -
    6678/******************* Bit definition for EXTI_PR register ********************/
    -
    6679#define EXTI_PR_PR0_Pos (0U)
    -
    6680#define EXTI_PR_PR0_Msk (0x1UL << EXTI_PR_PR0_Pos)
    -
    6681#define EXTI_PR_PR0 EXTI_PR_PR0_Msk
    -
    6682#define EXTI_PR_PR1_Pos (1U)
    -
    6683#define EXTI_PR_PR1_Msk (0x1UL << EXTI_PR_PR1_Pos)
    -
    6684#define EXTI_PR_PR1 EXTI_PR_PR1_Msk
    -
    6685#define EXTI_PR_PR2_Pos (2U)
    -
    6686#define EXTI_PR_PR2_Msk (0x1UL << EXTI_PR_PR2_Pos)
    -
    6687#define EXTI_PR_PR2 EXTI_PR_PR2_Msk
    -
    6688#define EXTI_PR_PR3_Pos (3U)
    -
    6689#define EXTI_PR_PR3_Msk (0x1UL << EXTI_PR_PR3_Pos)
    -
    6690#define EXTI_PR_PR3 EXTI_PR_PR3_Msk
    -
    6691#define EXTI_PR_PR4_Pos (4U)
    -
    6692#define EXTI_PR_PR4_Msk (0x1UL << EXTI_PR_PR4_Pos)
    -
    6693#define EXTI_PR_PR4 EXTI_PR_PR4_Msk
    -
    6694#define EXTI_PR_PR5_Pos (5U)
    -
    6695#define EXTI_PR_PR5_Msk (0x1UL << EXTI_PR_PR5_Pos)
    -
    6696#define EXTI_PR_PR5 EXTI_PR_PR5_Msk
    -
    6697#define EXTI_PR_PR6_Pos (6U)
    -
    6698#define EXTI_PR_PR6_Msk (0x1UL << EXTI_PR_PR6_Pos)
    -
    6699#define EXTI_PR_PR6 EXTI_PR_PR6_Msk
    -
    6700#define EXTI_PR_PR7_Pos (7U)
    -
    6701#define EXTI_PR_PR7_Msk (0x1UL << EXTI_PR_PR7_Pos)
    -
    6702#define EXTI_PR_PR7 EXTI_PR_PR7_Msk
    -
    6703#define EXTI_PR_PR8_Pos (8U)
    -
    6704#define EXTI_PR_PR8_Msk (0x1UL << EXTI_PR_PR8_Pos)
    -
    6705#define EXTI_PR_PR8 EXTI_PR_PR8_Msk
    -
    6706#define EXTI_PR_PR9_Pos (9U)
    -
    6707#define EXTI_PR_PR9_Msk (0x1UL << EXTI_PR_PR9_Pos)
    -
    6708#define EXTI_PR_PR9 EXTI_PR_PR9_Msk
    -
    6709#define EXTI_PR_PR10_Pos (10U)
    -
    6710#define EXTI_PR_PR10_Msk (0x1UL << EXTI_PR_PR10_Pos)
    -
    6711#define EXTI_PR_PR10 EXTI_PR_PR10_Msk
    -
    6712#define EXTI_PR_PR11_Pos (11U)
    -
    6713#define EXTI_PR_PR11_Msk (0x1UL << EXTI_PR_PR11_Pos)
    -
    6714#define EXTI_PR_PR11 EXTI_PR_PR11_Msk
    -
    6715#define EXTI_PR_PR12_Pos (12U)
    -
    6716#define EXTI_PR_PR12_Msk (0x1UL << EXTI_PR_PR12_Pos)
    -
    6717#define EXTI_PR_PR12 EXTI_PR_PR12_Msk
    -
    6718#define EXTI_PR_PR13_Pos (13U)
    -
    6719#define EXTI_PR_PR13_Msk (0x1UL << EXTI_PR_PR13_Pos)
    -
    6720#define EXTI_PR_PR13 EXTI_PR_PR13_Msk
    -
    6721#define EXTI_PR_PR14_Pos (14U)
    -
    6722#define EXTI_PR_PR14_Msk (0x1UL << EXTI_PR_PR14_Pos)
    -
    6723#define EXTI_PR_PR14 EXTI_PR_PR14_Msk
    -
    6724#define EXTI_PR_PR15_Pos (15U)
    -
    6725#define EXTI_PR_PR15_Msk (0x1UL << EXTI_PR_PR15_Pos)
    -
    6726#define EXTI_PR_PR15 EXTI_PR_PR15_Msk
    -
    6727#define EXTI_PR_PR16_Pos (16U)
    -
    6728#define EXTI_PR_PR16_Msk (0x1UL << EXTI_PR_PR16_Pos)
    -
    6729#define EXTI_PR_PR16 EXTI_PR_PR16_Msk
    -
    6730#define EXTI_PR_PR17_Pos (17U)
    -
    6731#define EXTI_PR_PR17_Msk (0x1UL << EXTI_PR_PR17_Pos)
    -
    6732#define EXTI_PR_PR17 EXTI_PR_PR17_Msk
    -
    6733#define EXTI_PR_PR18_Pos (18U)
    -
    6734#define EXTI_PR_PR18_Msk (0x1UL << EXTI_PR_PR18_Pos)
    -
    6735#define EXTI_PR_PR18 EXTI_PR_PR18_Msk
    -
    6736#define EXTI_PR_PR19_Pos (19U)
    -
    6737#define EXTI_PR_PR19_Msk (0x1UL << EXTI_PR_PR19_Pos)
    -
    6738#define EXTI_PR_PR19 EXTI_PR_PR19_Msk
    -
    6739#define EXTI_PR_PR20_Pos (20U)
    -
    6740#define EXTI_PR_PR20_Msk (0x1UL << EXTI_PR_PR20_Pos)
    -
    6741#define EXTI_PR_PR20 EXTI_PR_PR20_Msk
    -
    6742#define EXTI_PR_PR21_Pos (21U)
    -
    6743#define EXTI_PR_PR21_Msk (0x1UL << EXTI_PR_PR21_Pos)
    -
    6744#define EXTI_PR_PR21 EXTI_PR_PR21_Msk
    -
    6745#define EXTI_PR_PR22_Pos (22U)
    -
    6746#define EXTI_PR_PR22_Msk (0x1UL << EXTI_PR_PR22_Pos)
    -
    6747#define EXTI_PR_PR22 EXTI_PR_PR22_Msk
    -
    6749/******************************************************************************/
    -
    6750/* */
    -
    6751/* FLASH */
    -
    6752/* */
    -
    6753/******************************************************************************/
    -
    6754/******************* Bits definition for FLASH_ACR register *****************/
    -
    6755#define FLASH_ACR_LATENCY_Pos (0U)
    -
    6756#define FLASH_ACR_LATENCY_Msk (0x7UL << FLASH_ACR_LATENCY_Pos)
    -
    6757#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk
    -
    6758#define FLASH_ACR_LATENCY_0WS 0x00000000U
    -
    6759#define FLASH_ACR_LATENCY_1WS 0x00000001U
    -
    6760#define FLASH_ACR_LATENCY_2WS 0x00000002U
    -
    6761#define FLASH_ACR_LATENCY_3WS 0x00000003U
    -
    6762#define FLASH_ACR_LATENCY_4WS 0x00000004U
    -
    6763#define FLASH_ACR_LATENCY_5WS 0x00000005U
    -
    6764#define FLASH_ACR_LATENCY_6WS 0x00000006U
    -
    6765#define FLASH_ACR_LATENCY_7WS 0x00000007U
    -
    6766
    -
    6767
    -
    6768#define FLASH_ACR_PRFTEN_Pos (8U)
    -
    6769#define FLASH_ACR_PRFTEN_Msk (0x1UL << FLASH_ACR_PRFTEN_Pos)
    -
    6770#define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk
    -
    6771#define FLASH_ACR_ICEN_Pos (9U)
    -
    6772#define FLASH_ACR_ICEN_Msk (0x1UL << FLASH_ACR_ICEN_Pos)
    -
    6773#define FLASH_ACR_ICEN FLASH_ACR_ICEN_Msk
    -
    6774#define FLASH_ACR_DCEN_Pos (10U)
    -
    6775#define FLASH_ACR_DCEN_Msk (0x1UL << FLASH_ACR_DCEN_Pos)
    -
    6776#define FLASH_ACR_DCEN FLASH_ACR_DCEN_Msk
    -
    6777#define FLASH_ACR_ICRST_Pos (11U)
    -
    6778#define FLASH_ACR_ICRST_Msk (0x1UL << FLASH_ACR_ICRST_Pos)
    -
    6779#define FLASH_ACR_ICRST FLASH_ACR_ICRST_Msk
    -
    6780#define FLASH_ACR_DCRST_Pos (12U)
    -
    6781#define FLASH_ACR_DCRST_Msk (0x1UL << FLASH_ACR_DCRST_Pos)
    -
    6782#define FLASH_ACR_DCRST FLASH_ACR_DCRST_Msk
    -
    6783#define FLASH_ACR_BYTE0_ADDRESS_Pos (10U)
    -
    6784#define FLASH_ACR_BYTE0_ADDRESS_Msk (0x10008FUL << FLASH_ACR_BYTE0_ADDRESS_Pos)
    -
    6785#define FLASH_ACR_BYTE0_ADDRESS FLASH_ACR_BYTE0_ADDRESS_Msk
    -
    6786#define FLASH_ACR_BYTE2_ADDRESS_Pos (0U)
    -
    6787#define FLASH_ACR_BYTE2_ADDRESS_Msk (0x40023C03UL << FLASH_ACR_BYTE2_ADDRESS_Pos)
    -
    6788#define FLASH_ACR_BYTE2_ADDRESS FLASH_ACR_BYTE2_ADDRESS_Msk
    -
    6789
    -
    6790/******************* Bits definition for FLASH_SR register ******************/
    -
    6791#define FLASH_SR_EOP_Pos (0U)
    -
    6792#define FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos)
    -
    6793#define FLASH_SR_EOP FLASH_SR_EOP_Msk
    -
    6794#define FLASH_SR_SOP_Pos (1U)
    -
    6795#define FLASH_SR_SOP_Msk (0x1UL << FLASH_SR_SOP_Pos)
    -
    6796#define FLASH_SR_SOP FLASH_SR_SOP_Msk
    -
    6797#define FLASH_SR_WRPERR_Pos (4U)
    -
    6798#define FLASH_SR_WRPERR_Msk (0x1UL << FLASH_SR_WRPERR_Pos)
    -
    6799#define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk
    -
    6800#define FLASH_SR_PGAERR_Pos (5U)
    -
    6801#define FLASH_SR_PGAERR_Msk (0x1UL << FLASH_SR_PGAERR_Pos)
    -
    6802#define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk
    -
    6803#define FLASH_SR_PGPERR_Pos (6U)
    -
    6804#define FLASH_SR_PGPERR_Msk (0x1UL << FLASH_SR_PGPERR_Pos)
    -
    6805#define FLASH_SR_PGPERR FLASH_SR_PGPERR_Msk
    -
    6806#define FLASH_SR_PGSERR_Pos (7U)
    -
    6807#define FLASH_SR_PGSERR_Msk (0x1UL << FLASH_SR_PGSERR_Pos)
    -
    6808#define FLASH_SR_PGSERR FLASH_SR_PGSERR_Msk
    -
    6809#define FLASH_SR_BSY_Pos (16U)
    -
    6810#define FLASH_SR_BSY_Msk (0x1UL << FLASH_SR_BSY_Pos)
    -
    6811#define FLASH_SR_BSY FLASH_SR_BSY_Msk
    -
    6812
    -
    6813/******************* Bits definition for FLASH_CR register ******************/
    -
    6814#define FLASH_CR_PG_Pos (0U)
    -
    6815#define FLASH_CR_PG_Msk (0x1UL << FLASH_CR_PG_Pos)
    -
    6816#define FLASH_CR_PG FLASH_CR_PG_Msk
    -
    6817#define FLASH_CR_SER_Pos (1U)
    -
    6818#define FLASH_CR_SER_Msk (0x1UL << FLASH_CR_SER_Pos)
    -
    6819#define FLASH_CR_SER FLASH_CR_SER_Msk
    -
    6820#define FLASH_CR_MER_Pos (2U)
    -
    6821#define FLASH_CR_MER_Msk (0x1UL << FLASH_CR_MER_Pos)
    -
    6822#define FLASH_CR_MER FLASH_CR_MER_Msk
    -
    6823#define FLASH_CR_SNB_Pos (3U)
    -
    6824#define FLASH_CR_SNB_Msk (0x1FUL << FLASH_CR_SNB_Pos)
    -
    6825#define FLASH_CR_SNB FLASH_CR_SNB_Msk
    -
    6826#define FLASH_CR_SNB_0 (0x01UL << FLASH_CR_SNB_Pos)
    -
    6827#define FLASH_CR_SNB_1 (0x02UL << FLASH_CR_SNB_Pos)
    -
    6828#define FLASH_CR_SNB_2 (0x04UL << FLASH_CR_SNB_Pos)
    -
    6829#define FLASH_CR_SNB_3 (0x08UL << FLASH_CR_SNB_Pos)
    -
    6830#define FLASH_CR_SNB_4 (0x10UL << FLASH_CR_SNB_Pos)
    -
    6831#define FLASH_CR_PSIZE_Pos (8U)
    -
    6832#define FLASH_CR_PSIZE_Msk (0x3UL << FLASH_CR_PSIZE_Pos)
    -
    6833#define FLASH_CR_PSIZE FLASH_CR_PSIZE_Msk
    -
    6834#define FLASH_CR_PSIZE_0 (0x1UL << FLASH_CR_PSIZE_Pos)
    -
    6835#define FLASH_CR_PSIZE_1 (0x2UL << FLASH_CR_PSIZE_Pos)
    -
    6836#define FLASH_CR_STRT_Pos (16U)
    -
    6837#define FLASH_CR_STRT_Msk (0x1UL << FLASH_CR_STRT_Pos)
    -
    6838#define FLASH_CR_STRT FLASH_CR_STRT_Msk
    -
    6839#define FLASH_CR_EOPIE_Pos (24U)
    -
    6840#define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos)
    -
    6841#define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk
    -
    6842#define FLASH_CR_ERRIE_Pos (25U)
    -
    6843#define FLASH_CR_ERRIE_Msk (0x1UL << FLASH_CR_ERRIE_Pos)
    -
    6844#define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk
    -
    6845#define FLASH_CR_LOCK_Pos (31U)
    -
    6846#define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos)
    -
    6847#define FLASH_CR_LOCK FLASH_CR_LOCK_Msk
    -
    6848
    -
    6849/******************* Bits definition for FLASH_OPTCR register ***************/
    -
    6850#define FLASH_OPTCR_OPTLOCK_Pos (0U)
    -
    6851#define FLASH_OPTCR_OPTLOCK_Msk (0x1UL << FLASH_OPTCR_OPTLOCK_Pos)
    -
    6852#define FLASH_OPTCR_OPTLOCK FLASH_OPTCR_OPTLOCK_Msk
    -
    6853#define FLASH_OPTCR_OPTSTRT_Pos (1U)
    -
    6854#define FLASH_OPTCR_OPTSTRT_Msk (0x1UL << FLASH_OPTCR_OPTSTRT_Pos)
    -
    6855#define FLASH_OPTCR_OPTSTRT FLASH_OPTCR_OPTSTRT_Msk
    -
    6856
    -
    6857#define FLASH_OPTCR_BOR_LEV_0 0x00000004U
    -
    6858#define FLASH_OPTCR_BOR_LEV_1 0x00000008U
    -
    6859#define FLASH_OPTCR_BOR_LEV_Pos (2U)
    -
    6860#define FLASH_OPTCR_BOR_LEV_Msk (0x3UL << FLASH_OPTCR_BOR_LEV_Pos)
    -
    6861#define FLASH_OPTCR_BOR_LEV FLASH_OPTCR_BOR_LEV_Msk
    -
    6862#define FLASH_OPTCR_WDG_SW_Pos (5U)
    -
    6863#define FLASH_OPTCR_WDG_SW_Msk (0x1UL << FLASH_OPTCR_WDG_SW_Pos)
    -
    6864#define FLASH_OPTCR_WDG_SW FLASH_OPTCR_WDG_SW_Msk
    -
    6865#define FLASH_OPTCR_nRST_STOP_Pos (6U)
    -
    6866#define FLASH_OPTCR_nRST_STOP_Msk (0x1UL << FLASH_OPTCR_nRST_STOP_Pos)
    -
    6867#define FLASH_OPTCR_nRST_STOP FLASH_OPTCR_nRST_STOP_Msk
    -
    6868#define FLASH_OPTCR_nRST_STDBY_Pos (7U)
    -
    6869#define FLASH_OPTCR_nRST_STDBY_Msk (0x1UL << FLASH_OPTCR_nRST_STDBY_Pos)
    -
    6870#define FLASH_OPTCR_nRST_STDBY FLASH_OPTCR_nRST_STDBY_Msk
    -
    6871#define FLASH_OPTCR_RDP_Pos (8U)
    -
    6872#define FLASH_OPTCR_RDP_Msk (0xFFUL << FLASH_OPTCR_RDP_Pos)
    -
    6873#define FLASH_OPTCR_RDP FLASH_OPTCR_RDP_Msk
    -
    6874#define FLASH_OPTCR_RDP_0 (0x01UL << FLASH_OPTCR_RDP_Pos)
    -
    6875#define FLASH_OPTCR_RDP_1 (0x02UL << FLASH_OPTCR_RDP_Pos)
    -
    6876#define FLASH_OPTCR_RDP_2 (0x04UL << FLASH_OPTCR_RDP_Pos)
    -
    6877#define FLASH_OPTCR_RDP_3 (0x08UL << FLASH_OPTCR_RDP_Pos)
    -
    6878#define FLASH_OPTCR_RDP_4 (0x10UL << FLASH_OPTCR_RDP_Pos)
    -
    6879#define FLASH_OPTCR_RDP_5 (0x20UL << FLASH_OPTCR_RDP_Pos)
    -
    6880#define FLASH_OPTCR_RDP_6 (0x40UL << FLASH_OPTCR_RDP_Pos)
    -
    6881#define FLASH_OPTCR_RDP_7 (0x80UL << FLASH_OPTCR_RDP_Pos)
    -
    6882#define FLASH_OPTCR_nWRP_Pos (16U)
    -
    6883#define FLASH_OPTCR_nWRP_Msk (0xFFFUL << FLASH_OPTCR_nWRP_Pos)
    -
    6884#define FLASH_OPTCR_nWRP FLASH_OPTCR_nWRP_Msk
    -
    6885#define FLASH_OPTCR_nWRP_0 0x00010000U
    -
    6886#define FLASH_OPTCR_nWRP_1 0x00020000U
    -
    6887#define FLASH_OPTCR_nWRP_2 0x00040000U
    -
    6888#define FLASH_OPTCR_nWRP_3 0x00080000U
    -
    6889#define FLASH_OPTCR_nWRP_4 0x00100000U
    -
    6890#define FLASH_OPTCR_nWRP_5 0x00200000U
    -
    6891#define FLASH_OPTCR_nWRP_6 0x00400000U
    -
    6892#define FLASH_OPTCR_nWRP_7 0x00800000U
    -
    6893#define FLASH_OPTCR_nWRP_8 0x01000000U
    -
    6894#define FLASH_OPTCR_nWRP_9 0x02000000U
    -
    6895#define FLASH_OPTCR_nWRP_10 0x04000000U
    -
    6896#define FLASH_OPTCR_nWRP_11 0x08000000U
    -
    6897
    -
    6898/****************** Bits definition for FLASH_OPTCR1 register ***************/
    -
    6899#define FLASH_OPTCR1_nWRP_Pos (16U)
    -
    6900#define FLASH_OPTCR1_nWRP_Msk (0xFFFUL << FLASH_OPTCR1_nWRP_Pos)
    -
    6901#define FLASH_OPTCR1_nWRP FLASH_OPTCR1_nWRP_Msk
    -
    6902#define FLASH_OPTCR1_nWRP_0 (0x001UL << FLASH_OPTCR1_nWRP_Pos)
    -
    6903#define FLASH_OPTCR1_nWRP_1 (0x002UL << FLASH_OPTCR1_nWRP_Pos)
    -
    6904#define FLASH_OPTCR1_nWRP_2 (0x004UL << FLASH_OPTCR1_nWRP_Pos)
    -
    6905#define FLASH_OPTCR1_nWRP_3 (0x008UL << FLASH_OPTCR1_nWRP_Pos)
    -
    6906#define FLASH_OPTCR1_nWRP_4 (0x010UL << FLASH_OPTCR1_nWRP_Pos)
    -
    6907#define FLASH_OPTCR1_nWRP_5 (0x020UL << FLASH_OPTCR1_nWRP_Pos)
    -
    6908#define FLASH_OPTCR1_nWRP_6 (0x040UL << FLASH_OPTCR1_nWRP_Pos)
    -
    6909#define FLASH_OPTCR1_nWRP_7 (0x080UL << FLASH_OPTCR1_nWRP_Pos)
    -
    6910#define FLASH_OPTCR1_nWRP_8 (0x100UL << FLASH_OPTCR1_nWRP_Pos)
    -
    6911#define FLASH_OPTCR1_nWRP_9 (0x200UL << FLASH_OPTCR1_nWRP_Pos)
    -
    6912#define FLASH_OPTCR1_nWRP_10 (0x400UL << FLASH_OPTCR1_nWRP_Pos)
    -
    6913#define FLASH_OPTCR1_nWRP_11 (0x800UL << FLASH_OPTCR1_nWRP_Pos)
    -
    6915/******************************************************************************/
    -
    6916/* */
    -
    6917/* Flexible Static Memory Controller */
    -
    6918/* */
    -
    6919/******************************************************************************/
    -
    6920/****************** Bit definition for FSMC_BCR1 register *******************/
    -
    6921#define FSMC_BCR1_MBKEN_Pos (0U)
    -
    6922#define FSMC_BCR1_MBKEN_Msk (0x1UL << FSMC_BCR1_MBKEN_Pos)
    -
    6923#define FSMC_BCR1_MBKEN FSMC_BCR1_MBKEN_Msk
    -
    6924#define FSMC_BCR1_MUXEN_Pos (1U)
    -
    6925#define FSMC_BCR1_MUXEN_Msk (0x1UL << FSMC_BCR1_MUXEN_Pos)
    -
    6926#define FSMC_BCR1_MUXEN FSMC_BCR1_MUXEN_Msk
    -
    6928#define FSMC_BCR1_MTYP_Pos (2U)
    -
    6929#define FSMC_BCR1_MTYP_Msk (0x3UL << FSMC_BCR1_MTYP_Pos)
    -
    6930#define FSMC_BCR1_MTYP FSMC_BCR1_MTYP_Msk
    -
    6931#define FSMC_BCR1_MTYP_0 (0x1UL << FSMC_BCR1_MTYP_Pos)
    -
    6932#define FSMC_BCR1_MTYP_1 (0x2UL << FSMC_BCR1_MTYP_Pos)
    -
    6934#define FSMC_BCR1_MWID_Pos (4U)
    -
    6935#define FSMC_BCR1_MWID_Msk (0x3UL << FSMC_BCR1_MWID_Pos)
    -
    6936#define FSMC_BCR1_MWID FSMC_BCR1_MWID_Msk
    -
    6937#define FSMC_BCR1_MWID_0 (0x1UL << FSMC_BCR1_MWID_Pos)
    -
    6938#define FSMC_BCR1_MWID_1 (0x2UL << FSMC_BCR1_MWID_Pos)
    -
    6940#define FSMC_BCR1_FACCEN_Pos (6U)
    -
    6941#define FSMC_BCR1_FACCEN_Msk (0x1UL << FSMC_BCR1_FACCEN_Pos)
    -
    6942#define FSMC_BCR1_FACCEN FSMC_BCR1_FACCEN_Msk
    -
    6943#define FSMC_BCR1_BURSTEN_Pos (8U)
    -
    6944#define FSMC_BCR1_BURSTEN_Msk (0x1UL << FSMC_BCR1_BURSTEN_Pos)
    -
    6945#define FSMC_BCR1_BURSTEN FSMC_BCR1_BURSTEN_Msk
    -
    6946#define FSMC_BCR1_WAITPOL_Pos (9U)
    -
    6947#define FSMC_BCR1_WAITPOL_Msk (0x1UL << FSMC_BCR1_WAITPOL_Pos)
    -
    6948#define FSMC_BCR1_WAITPOL FSMC_BCR1_WAITPOL_Msk
    -
    6949#define FSMC_BCR1_WRAPMOD_Pos (10U)
    -
    6950#define FSMC_BCR1_WRAPMOD_Msk (0x1UL << FSMC_BCR1_WRAPMOD_Pos)
    -
    6951#define FSMC_BCR1_WRAPMOD FSMC_BCR1_WRAPMOD_Msk
    -
    6952#define FSMC_BCR1_WAITCFG_Pos (11U)
    -
    6953#define FSMC_BCR1_WAITCFG_Msk (0x1UL << FSMC_BCR1_WAITCFG_Pos)
    -
    6954#define FSMC_BCR1_WAITCFG FSMC_BCR1_WAITCFG_Msk
    -
    6955#define FSMC_BCR1_WREN_Pos (12U)
    -
    6956#define FSMC_BCR1_WREN_Msk (0x1UL << FSMC_BCR1_WREN_Pos)
    -
    6957#define FSMC_BCR1_WREN FSMC_BCR1_WREN_Msk
    -
    6958#define FSMC_BCR1_WAITEN_Pos (13U)
    -
    6959#define FSMC_BCR1_WAITEN_Msk (0x1UL << FSMC_BCR1_WAITEN_Pos)
    -
    6960#define FSMC_BCR1_WAITEN FSMC_BCR1_WAITEN_Msk
    -
    6961#define FSMC_BCR1_EXTMOD_Pos (14U)
    -
    6962#define FSMC_BCR1_EXTMOD_Msk (0x1UL << FSMC_BCR1_EXTMOD_Pos)
    -
    6963#define FSMC_BCR1_EXTMOD FSMC_BCR1_EXTMOD_Msk
    -
    6964#define FSMC_BCR1_ASYNCWAIT_Pos (15U)
    -
    6965#define FSMC_BCR1_ASYNCWAIT_Msk (0x1UL << FSMC_BCR1_ASYNCWAIT_Pos)
    -
    6966#define FSMC_BCR1_ASYNCWAIT FSMC_BCR1_ASYNCWAIT_Msk
    -
    6967#define FSMC_BCR1_CPSIZE_Pos (16U)
    -
    6968#define FSMC_BCR1_CPSIZE_Msk (0x7UL << FSMC_BCR1_CPSIZE_Pos)
    -
    6969#define FSMC_BCR1_CPSIZE FSMC_BCR1_CPSIZE_Msk
    -
    6970#define FSMC_BCR1_CPSIZE_0 (0x1UL << FSMC_BCR1_CPSIZE_Pos)
    -
    6971#define FSMC_BCR1_CPSIZE_1 (0x2UL << FSMC_BCR1_CPSIZE_Pos)
    -
    6972#define FSMC_BCR1_CPSIZE_2 (0x4UL << FSMC_BCR1_CPSIZE_Pos)
    -
    6973#define FSMC_BCR1_CBURSTRW_Pos (19U)
    -
    6974#define FSMC_BCR1_CBURSTRW_Msk (0x1UL << FSMC_BCR1_CBURSTRW_Pos)
    -
    6975#define FSMC_BCR1_CBURSTRW FSMC_BCR1_CBURSTRW_Msk
    -
    6977/****************** Bit definition for FSMC_BCR2 register *******************/
    -
    6978#define FSMC_BCR2_MBKEN_Pos (0U)
    -
    6979#define FSMC_BCR2_MBKEN_Msk (0x1UL << FSMC_BCR2_MBKEN_Pos)
    -
    6980#define FSMC_BCR2_MBKEN FSMC_BCR2_MBKEN_Msk
    -
    6981#define FSMC_BCR2_MUXEN_Pos (1U)
    -
    6982#define FSMC_BCR2_MUXEN_Msk (0x1UL << FSMC_BCR2_MUXEN_Pos)
    -
    6983#define FSMC_BCR2_MUXEN FSMC_BCR2_MUXEN_Msk
    -
    6985#define FSMC_BCR2_MTYP_Pos (2U)
    -
    6986#define FSMC_BCR2_MTYP_Msk (0x3UL << FSMC_BCR2_MTYP_Pos)
    -
    6987#define FSMC_BCR2_MTYP FSMC_BCR2_MTYP_Msk
    -
    6988#define FSMC_BCR2_MTYP_0 (0x1UL << FSMC_BCR2_MTYP_Pos)
    -
    6989#define FSMC_BCR2_MTYP_1 (0x2UL << FSMC_BCR2_MTYP_Pos)
    -
    6991#define FSMC_BCR2_MWID_Pos (4U)
    -
    6992#define FSMC_BCR2_MWID_Msk (0x3UL << FSMC_BCR2_MWID_Pos)
    -
    6993#define FSMC_BCR2_MWID FSMC_BCR2_MWID_Msk
    -
    6994#define FSMC_BCR2_MWID_0 (0x1UL << FSMC_BCR2_MWID_Pos)
    -
    6995#define FSMC_BCR2_MWID_1 (0x2UL << FSMC_BCR2_MWID_Pos)
    -
    6997#define FSMC_BCR2_FACCEN_Pos (6U)
    -
    6998#define FSMC_BCR2_FACCEN_Msk (0x1UL << FSMC_BCR2_FACCEN_Pos)
    -
    6999#define FSMC_BCR2_FACCEN FSMC_BCR2_FACCEN_Msk
    -
    7000#define FSMC_BCR2_BURSTEN_Pos (8U)
    -
    7001#define FSMC_BCR2_BURSTEN_Msk (0x1UL << FSMC_BCR2_BURSTEN_Pos)
    -
    7002#define FSMC_BCR2_BURSTEN FSMC_BCR2_BURSTEN_Msk
    -
    7003#define FSMC_BCR2_WAITPOL_Pos (9U)
    -
    7004#define FSMC_BCR2_WAITPOL_Msk (0x1UL << FSMC_BCR2_WAITPOL_Pos)
    -
    7005#define FSMC_BCR2_WAITPOL FSMC_BCR2_WAITPOL_Msk
    -
    7006#define FSMC_BCR2_WRAPMOD_Pos (10U)
    -
    7007#define FSMC_BCR2_WRAPMOD_Msk (0x1UL << FSMC_BCR2_WRAPMOD_Pos)
    -
    7008#define FSMC_BCR2_WRAPMOD FSMC_BCR2_WRAPMOD_Msk
    -
    7009#define FSMC_BCR2_WAITCFG_Pos (11U)
    -
    7010#define FSMC_BCR2_WAITCFG_Msk (0x1UL << FSMC_BCR2_WAITCFG_Pos)
    -
    7011#define FSMC_BCR2_WAITCFG FSMC_BCR2_WAITCFG_Msk
    -
    7012#define FSMC_BCR2_WREN_Pos (12U)
    -
    7013#define FSMC_BCR2_WREN_Msk (0x1UL << FSMC_BCR2_WREN_Pos)
    -
    7014#define FSMC_BCR2_WREN FSMC_BCR2_WREN_Msk
    -
    7015#define FSMC_BCR2_WAITEN_Pos (13U)
    -
    7016#define FSMC_BCR2_WAITEN_Msk (0x1UL << FSMC_BCR2_WAITEN_Pos)
    -
    7017#define FSMC_BCR2_WAITEN FSMC_BCR2_WAITEN_Msk
    -
    7018#define FSMC_BCR2_EXTMOD_Pos (14U)
    -
    7019#define FSMC_BCR2_EXTMOD_Msk (0x1UL << FSMC_BCR2_EXTMOD_Pos)
    -
    7020#define FSMC_BCR2_EXTMOD FSMC_BCR2_EXTMOD_Msk
    -
    7021#define FSMC_BCR2_ASYNCWAIT_Pos (15U)
    -
    7022#define FSMC_BCR2_ASYNCWAIT_Msk (0x1UL << FSMC_BCR2_ASYNCWAIT_Pos)
    -
    7023#define FSMC_BCR2_ASYNCWAIT FSMC_BCR2_ASYNCWAIT_Msk
    -
    7024#define FSMC_BCR2_CPSIZE_Pos (16U)
    -
    7025#define FSMC_BCR2_CPSIZE_Msk (0x7UL << FSMC_BCR2_CPSIZE_Pos)
    -
    7026#define FSMC_BCR2_CPSIZE FSMC_BCR2_CPSIZE_Msk
    -
    7027#define FSMC_BCR2_CPSIZE_0 (0x1UL << FSMC_BCR2_CPSIZE_Pos)
    -
    7028#define FSMC_BCR2_CPSIZE_1 (0x2UL << FSMC_BCR2_CPSIZE_Pos)
    -
    7029#define FSMC_BCR2_CPSIZE_2 (0x4UL << FSMC_BCR2_CPSIZE_Pos)
    -
    7030#define FSMC_BCR2_CBURSTRW_Pos (19U)
    -
    7031#define FSMC_BCR2_CBURSTRW_Msk (0x1UL << FSMC_BCR2_CBURSTRW_Pos)
    -
    7032#define FSMC_BCR2_CBURSTRW FSMC_BCR2_CBURSTRW_Msk
    -
    7034/****************** Bit definition for FSMC_BCR3 register *******************/
    -
    7035#define FSMC_BCR3_MBKEN_Pos (0U)
    -
    7036#define FSMC_BCR3_MBKEN_Msk (0x1UL << FSMC_BCR3_MBKEN_Pos)
    -
    7037#define FSMC_BCR3_MBKEN FSMC_BCR3_MBKEN_Msk
    -
    7038#define FSMC_BCR3_MUXEN_Pos (1U)
    -
    7039#define FSMC_BCR3_MUXEN_Msk (0x1UL << FSMC_BCR3_MUXEN_Pos)
    -
    7040#define FSMC_BCR3_MUXEN FSMC_BCR3_MUXEN_Msk
    -
    7042#define FSMC_BCR3_MTYP_Pos (2U)
    -
    7043#define FSMC_BCR3_MTYP_Msk (0x3UL << FSMC_BCR3_MTYP_Pos)
    -
    7044#define FSMC_BCR3_MTYP FSMC_BCR3_MTYP_Msk
    -
    7045#define FSMC_BCR3_MTYP_0 (0x1UL << FSMC_BCR3_MTYP_Pos)
    -
    7046#define FSMC_BCR3_MTYP_1 (0x2UL << FSMC_BCR3_MTYP_Pos)
    -
    7048#define FSMC_BCR3_MWID_Pos (4U)
    -
    7049#define FSMC_BCR3_MWID_Msk (0x3UL << FSMC_BCR3_MWID_Pos)
    -
    7050#define FSMC_BCR3_MWID FSMC_BCR3_MWID_Msk
    -
    7051#define FSMC_BCR3_MWID_0 (0x1UL << FSMC_BCR3_MWID_Pos)
    -
    7052#define FSMC_BCR3_MWID_1 (0x2UL << FSMC_BCR3_MWID_Pos)
    -
    7054#define FSMC_BCR3_FACCEN_Pos (6U)
    -
    7055#define FSMC_BCR3_FACCEN_Msk (0x1UL << FSMC_BCR3_FACCEN_Pos)
    -
    7056#define FSMC_BCR3_FACCEN FSMC_BCR3_FACCEN_Msk
    -
    7057#define FSMC_BCR3_BURSTEN_Pos (8U)
    -
    7058#define FSMC_BCR3_BURSTEN_Msk (0x1UL << FSMC_BCR3_BURSTEN_Pos)
    -
    7059#define FSMC_BCR3_BURSTEN FSMC_BCR3_BURSTEN_Msk
    -
    7060#define FSMC_BCR3_WAITPOL_Pos (9U)
    -
    7061#define FSMC_BCR3_WAITPOL_Msk (0x1UL << FSMC_BCR3_WAITPOL_Pos)
    -
    7062#define FSMC_BCR3_WAITPOL FSMC_BCR3_WAITPOL_Msk
    -
    7063#define FSMC_BCR3_WRAPMOD_Pos (10U)
    -
    7064#define FSMC_BCR3_WRAPMOD_Msk (0x1UL << FSMC_BCR3_WRAPMOD_Pos)
    -
    7065#define FSMC_BCR3_WRAPMOD FSMC_BCR3_WRAPMOD_Msk
    -
    7066#define FSMC_BCR3_WAITCFG_Pos (11U)
    -
    7067#define FSMC_BCR3_WAITCFG_Msk (0x1UL << FSMC_BCR3_WAITCFG_Pos)
    -
    7068#define FSMC_BCR3_WAITCFG FSMC_BCR3_WAITCFG_Msk
    -
    7069#define FSMC_BCR3_WREN_Pos (12U)
    -
    7070#define FSMC_BCR3_WREN_Msk (0x1UL << FSMC_BCR3_WREN_Pos)
    -
    7071#define FSMC_BCR3_WREN FSMC_BCR3_WREN_Msk
    -
    7072#define FSMC_BCR3_WAITEN_Pos (13U)
    -
    7073#define FSMC_BCR3_WAITEN_Msk (0x1UL << FSMC_BCR3_WAITEN_Pos)
    -
    7074#define FSMC_BCR3_WAITEN FSMC_BCR3_WAITEN_Msk
    -
    7075#define FSMC_BCR3_EXTMOD_Pos (14U)
    -
    7076#define FSMC_BCR3_EXTMOD_Msk (0x1UL << FSMC_BCR3_EXTMOD_Pos)
    -
    7077#define FSMC_BCR3_EXTMOD FSMC_BCR3_EXTMOD_Msk
    -
    7078#define FSMC_BCR3_ASYNCWAIT_Pos (15U)
    -
    7079#define FSMC_BCR3_ASYNCWAIT_Msk (0x1UL << FSMC_BCR3_ASYNCWAIT_Pos)
    -
    7080#define FSMC_BCR3_ASYNCWAIT FSMC_BCR3_ASYNCWAIT_Msk
    -
    7081#define FSMC_BCR3_CPSIZE_Pos (16U)
    -
    7082#define FSMC_BCR3_CPSIZE_Msk (0x7UL << FSMC_BCR3_CPSIZE_Pos)
    -
    7083#define FSMC_BCR3_CPSIZE FSMC_BCR3_CPSIZE_Msk
    -
    7084#define FSMC_BCR3_CPSIZE_0 (0x1UL << FSMC_BCR3_CPSIZE_Pos)
    -
    7085#define FSMC_BCR3_CPSIZE_1 (0x2UL << FSMC_BCR3_CPSIZE_Pos)
    -
    7086#define FSMC_BCR3_CPSIZE_2 (0x4UL << FSMC_BCR3_CPSIZE_Pos)
    -
    7087#define FSMC_BCR3_CBURSTRW_Pos (19U)
    -
    7088#define FSMC_BCR3_CBURSTRW_Msk (0x1UL << FSMC_BCR3_CBURSTRW_Pos)
    -
    7089#define FSMC_BCR3_CBURSTRW FSMC_BCR3_CBURSTRW_Msk
    -
    7091/****************** Bit definition for FSMC_BCR4 register *******************/
    -
    7092#define FSMC_BCR4_MBKEN_Pos (0U)
    -
    7093#define FSMC_BCR4_MBKEN_Msk (0x1UL << FSMC_BCR4_MBKEN_Pos)
    -
    7094#define FSMC_BCR4_MBKEN FSMC_BCR4_MBKEN_Msk
    -
    7095#define FSMC_BCR4_MUXEN_Pos (1U)
    -
    7096#define FSMC_BCR4_MUXEN_Msk (0x1UL << FSMC_BCR4_MUXEN_Pos)
    -
    7097#define FSMC_BCR4_MUXEN FSMC_BCR4_MUXEN_Msk
    -
    7099#define FSMC_BCR4_MTYP_Pos (2U)
    -
    7100#define FSMC_BCR4_MTYP_Msk (0x3UL << FSMC_BCR4_MTYP_Pos)
    -
    7101#define FSMC_BCR4_MTYP FSMC_BCR4_MTYP_Msk
    -
    7102#define FSMC_BCR4_MTYP_0 (0x1UL << FSMC_BCR4_MTYP_Pos)
    -
    7103#define FSMC_BCR4_MTYP_1 (0x2UL << FSMC_BCR4_MTYP_Pos)
    -
    7105#define FSMC_BCR4_MWID_Pos (4U)
    -
    7106#define FSMC_BCR4_MWID_Msk (0x3UL << FSMC_BCR4_MWID_Pos)
    -
    7107#define FSMC_BCR4_MWID FSMC_BCR4_MWID_Msk
    -
    7108#define FSMC_BCR4_MWID_0 (0x1UL << FSMC_BCR4_MWID_Pos)
    -
    7109#define FSMC_BCR4_MWID_1 (0x2UL << FSMC_BCR4_MWID_Pos)
    -
    7111#define FSMC_BCR4_FACCEN_Pos (6U)
    -
    7112#define FSMC_BCR4_FACCEN_Msk (0x1UL << FSMC_BCR4_FACCEN_Pos)
    -
    7113#define FSMC_BCR4_FACCEN FSMC_BCR4_FACCEN_Msk
    -
    7114#define FSMC_BCR4_BURSTEN_Pos (8U)
    -
    7115#define FSMC_BCR4_BURSTEN_Msk (0x1UL << FSMC_BCR4_BURSTEN_Pos)
    -
    7116#define FSMC_BCR4_BURSTEN FSMC_BCR4_BURSTEN_Msk
    -
    7117#define FSMC_BCR4_WAITPOL_Pos (9U)
    -
    7118#define FSMC_BCR4_WAITPOL_Msk (0x1UL << FSMC_BCR4_WAITPOL_Pos)
    -
    7119#define FSMC_BCR4_WAITPOL FSMC_BCR4_WAITPOL_Msk
    -
    7120#define FSMC_BCR4_WRAPMOD_Pos (10U)
    -
    7121#define FSMC_BCR4_WRAPMOD_Msk (0x1UL << FSMC_BCR4_WRAPMOD_Pos)
    -
    7122#define FSMC_BCR4_WRAPMOD FSMC_BCR4_WRAPMOD_Msk
    -
    7123#define FSMC_BCR4_WAITCFG_Pos (11U)
    -
    7124#define FSMC_BCR4_WAITCFG_Msk (0x1UL << FSMC_BCR4_WAITCFG_Pos)
    -
    7125#define FSMC_BCR4_WAITCFG FSMC_BCR4_WAITCFG_Msk
    -
    7126#define FSMC_BCR4_WREN_Pos (12U)
    -
    7127#define FSMC_BCR4_WREN_Msk (0x1UL << FSMC_BCR4_WREN_Pos)
    -
    7128#define FSMC_BCR4_WREN FSMC_BCR4_WREN_Msk
    -
    7129#define FSMC_BCR4_WAITEN_Pos (13U)
    -
    7130#define FSMC_BCR4_WAITEN_Msk (0x1UL << FSMC_BCR4_WAITEN_Pos)
    -
    7131#define FSMC_BCR4_WAITEN FSMC_BCR4_WAITEN_Msk
    -
    7132#define FSMC_BCR4_EXTMOD_Pos (14U)
    -
    7133#define FSMC_BCR4_EXTMOD_Msk (0x1UL << FSMC_BCR4_EXTMOD_Pos)
    -
    7134#define FSMC_BCR4_EXTMOD FSMC_BCR4_EXTMOD_Msk
    -
    7135#define FSMC_BCR4_ASYNCWAIT_Pos (15U)
    -
    7136#define FSMC_BCR4_ASYNCWAIT_Msk (0x1UL << FSMC_BCR4_ASYNCWAIT_Pos)
    -
    7137#define FSMC_BCR4_ASYNCWAIT FSMC_BCR4_ASYNCWAIT_Msk
    -
    7138#define FSMC_BCR4_CPSIZE_Pos (16U)
    -
    7139#define FSMC_BCR4_CPSIZE_Msk (0x7UL << FSMC_BCR4_CPSIZE_Pos)
    -
    7140#define FSMC_BCR4_CPSIZE FSMC_BCR4_CPSIZE_Msk
    -
    7141#define FSMC_BCR4_CPSIZE_0 (0x1UL << FSMC_BCR4_CPSIZE_Pos)
    -
    7142#define FSMC_BCR4_CPSIZE_1 (0x2UL << FSMC_BCR4_CPSIZE_Pos)
    -
    7143#define FSMC_BCR4_CPSIZE_2 (0x4UL << FSMC_BCR4_CPSIZE_Pos)
    -
    7144#define FSMC_BCR4_CBURSTRW_Pos (19U)
    -
    7145#define FSMC_BCR4_CBURSTRW_Msk (0x1UL << FSMC_BCR4_CBURSTRW_Pos)
    -
    7146#define FSMC_BCR4_CBURSTRW FSMC_BCR4_CBURSTRW_Msk
    -
    7148/****************** Bit definition for FSMC_BTR1 register ******************/
    -
    7149#define FSMC_BTR1_ADDSET_Pos (0U)
    -
    7150#define FSMC_BTR1_ADDSET_Msk (0xFUL << FSMC_BTR1_ADDSET_Pos)
    -
    7151#define FSMC_BTR1_ADDSET FSMC_BTR1_ADDSET_Msk
    -
    7152#define FSMC_BTR1_ADDSET_0 (0x1UL << FSMC_BTR1_ADDSET_Pos)
    -
    7153#define FSMC_BTR1_ADDSET_1 (0x2UL << FSMC_BTR1_ADDSET_Pos)
    -
    7154#define FSMC_BTR1_ADDSET_2 (0x4UL << FSMC_BTR1_ADDSET_Pos)
    -
    7155#define FSMC_BTR1_ADDSET_3 (0x8UL << FSMC_BTR1_ADDSET_Pos)
    -
    7157#define FSMC_BTR1_ADDHLD_Pos (4U)
    -
    7158#define FSMC_BTR1_ADDHLD_Msk (0xFUL << FSMC_BTR1_ADDHLD_Pos)
    -
    7159#define FSMC_BTR1_ADDHLD FSMC_BTR1_ADDHLD_Msk
    -
    7160#define FSMC_BTR1_ADDHLD_0 (0x1UL << FSMC_BTR1_ADDHLD_Pos)
    -
    7161#define FSMC_BTR1_ADDHLD_1 (0x2UL << FSMC_BTR1_ADDHLD_Pos)
    -
    7162#define FSMC_BTR1_ADDHLD_2 (0x4UL << FSMC_BTR1_ADDHLD_Pos)
    -
    7163#define FSMC_BTR1_ADDHLD_3 (0x8UL << FSMC_BTR1_ADDHLD_Pos)
    -
    7165#define FSMC_BTR1_DATAST_Pos (8U)
    -
    7166#define FSMC_BTR1_DATAST_Msk (0xFFUL << FSMC_BTR1_DATAST_Pos)
    -
    7167#define FSMC_BTR1_DATAST FSMC_BTR1_DATAST_Msk
    -
    7168#define FSMC_BTR1_DATAST_0 (0x01UL << FSMC_BTR1_DATAST_Pos)
    -
    7169#define FSMC_BTR1_DATAST_1 (0x02UL << FSMC_BTR1_DATAST_Pos)
    -
    7170#define FSMC_BTR1_DATAST_2 (0x04UL << FSMC_BTR1_DATAST_Pos)
    -
    7171#define FSMC_BTR1_DATAST_3 (0x08UL << FSMC_BTR1_DATAST_Pos)
    -
    7172#define FSMC_BTR1_DATAST_4 (0x10UL << FSMC_BTR1_DATAST_Pos)
    -
    7173#define FSMC_BTR1_DATAST_5 (0x20UL << FSMC_BTR1_DATAST_Pos)
    -
    7174#define FSMC_BTR1_DATAST_6 (0x40UL << FSMC_BTR1_DATAST_Pos)
    -
    7175#define FSMC_BTR1_DATAST_7 (0x80UL << FSMC_BTR1_DATAST_Pos)
    -
    7177#define FSMC_BTR1_BUSTURN_Pos (16U)
    -
    7178#define FSMC_BTR1_BUSTURN_Msk (0xFUL << FSMC_BTR1_BUSTURN_Pos)
    -
    7179#define FSMC_BTR1_BUSTURN FSMC_BTR1_BUSTURN_Msk
    -
    7180#define FSMC_BTR1_BUSTURN_0 (0x1UL << FSMC_BTR1_BUSTURN_Pos)
    -
    7181#define FSMC_BTR1_BUSTURN_1 (0x2UL << FSMC_BTR1_BUSTURN_Pos)
    -
    7182#define FSMC_BTR1_BUSTURN_2 (0x4UL << FSMC_BTR1_BUSTURN_Pos)
    -
    7183#define FSMC_BTR1_BUSTURN_3 (0x8UL << FSMC_BTR1_BUSTURN_Pos)
    -
    7185#define FSMC_BTR1_CLKDIV_Pos (20U)
    -
    7186#define FSMC_BTR1_CLKDIV_Msk (0xFUL << FSMC_BTR1_CLKDIV_Pos)
    -
    7187#define FSMC_BTR1_CLKDIV FSMC_BTR1_CLKDIV_Msk
    -
    7188#define FSMC_BTR1_CLKDIV_0 (0x1UL << FSMC_BTR1_CLKDIV_Pos)
    -
    7189#define FSMC_BTR1_CLKDIV_1 (0x2UL << FSMC_BTR1_CLKDIV_Pos)
    -
    7190#define FSMC_BTR1_CLKDIV_2 (0x4UL << FSMC_BTR1_CLKDIV_Pos)
    -
    7191#define FSMC_BTR1_CLKDIV_3 (0x8UL << FSMC_BTR1_CLKDIV_Pos)
    -
    7193#define FSMC_BTR1_DATLAT_Pos (24U)
    -
    7194#define FSMC_BTR1_DATLAT_Msk (0xFUL << FSMC_BTR1_DATLAT_Pos)
    -
    7195#define FSMC_BTR1_DATLAT FSMC_BTR1_DATLAT_Msk
    -
    7196#define FSMC_BTR1_DATLAT_0 (0x1UL << FSMC_BTR1_DATLAT_Pos)
    -
    7197#define FSMC_BTR1_DATLAT_1 (0x2UL << FSMC_BTR1_DATLAT_Pos)
    -
    7198#define FSMC_BTR1_DATLAT_2 (0x4UL << FSMC_BTR1_DATLAT_Pos)
    -
    7199#define FSMC_BTR1_DATLAT_3 (0x8UL << FSMC_BTR1_DATLAT_Pos)
    -
    7201#define FSMC_BTR1_ACCMOD_Pos (28U)
    -
    7202#define FSMC_BTR1_ACCMOD_Msk (0x3UL << FSMC_BTR1_ACCMOD_Pos)
    -
    7203#define FSMC_BTR1_ACCMOD FSMC_BTR1_ACCMOD_Msk
    -
    7204#define FSMC_BTR1_ACCMOD_0 (0x1UL << FSMC_BTR1_ACCMOD_Pos)
    -
    7205#define FSMC_BTR1_ACCMOD_1 (0x2UL << FSMC_BTR1_ACCMOD_Pos)
    -
    7207/****************** Bit definition for FSMC_BTR2 register *******************/
    -
    7208#define FSMC_BTR2_ADDSET_Pos (0U)
    -
    7209#define FSMC_BTR2_ADDSET_Msk (0xFUL << FSMC_BTR2_ADDSET_Pos)
    -
    7210#define FSMC_BTR2_ADDSET FSMC_BTR2_ADDSET_Msk
    -
    7211#define FSMC_BTR2_ADDSET_0 (0x1UL << FSMC_BTR2_ADDSET_Pos)
    -
    7212#define FSMC_BTR2_ADDSET_1 (0x2UL << FSMC_BTR2_ADDSET_Pos)
    -
    7213#define FSMC_BTR2_ADDSET_2 (0x4UL << FSMC_BTR2_ADDSET_Pos)
    -
    7214#define FSMC_BTR2_ADDSET_3 (0x8UL << FSMC_BTR2_ADDSET_Pos)
    -
    7216#define FSMC_BTR2_ADDHLD_Pos (4U)
    -
    7217#define FSMC_BTR2_ADDHLD_Msk (0xFUL << FSMC_BTR2_ADDHLD_Pos)
    -
    7218#define FSMC_BTR2_ADDHLD FSMC_BTR2_ADDHLD_Msk
    -
    7219#define FSMC_BTR2_ADDHLD_0 (0x1UL << FSMC_BTR2_ADDHLD_Pos)
    -
    7220#define FSMC_BTR2_ADDHLD_1 (0x2UL << FSMC_BTR2_ADDHLD_Pos)
    -
    7221#define FSMC_BTR2_ADDHLD_2 (0x4UL << FSMC_BTR2_ADDHLD_Pos)
    -
    7222#define FSMC_BTR2_ADDHLD_3 (0x8UL << FSMC_BTR2_ADDHLD_Pos)
    -
    7224#define FSMC_BTR2_DATAST_Pos (8U)
    -
    7225#define FSMC_BTR2_DATAST_Msk (0xFFUL << FSMC_BTR2_DATAST_Pos)
    -
    7226#define FSMC_BTR2_DATAST FSMC_BTR2_DATAST_Msk
    -
    7227#define FSMC_BTR2_DATAST_0 (0x01UL << FSMC_BTR2_DATAST_Pos)
    -
    7228#define FSMC_BTR2_DATAST_1 (0x02UL << FSMC_BTR2_DATAST_Pos)
    -
    7229#define FSMC_BTR2_DATAST_2 (0x04UL << FSMC_BTR2_DATAST_Pos)
    -
    7230#define FSMC_BTR2_DATAST_3 (0x08UL << FSMC_BTR2_DATAST_Pos)
    -
    7231#define FSMC_BTR2_DATAST_4 (0x10UL << FSMC_BTR2_DATAST_Pos)
    -
    7232#define FSMC_BTR2_DATAST_5 (0x20UL << FSMC_BTR2_DATAST_Pos)
    -
    7233#define FSMC_BTR2_DATAST_6 (0x40UL << FSMC_BTR2_DATAST_Pos)
    -
    7234#define FSMC_BTR2_DATAST_7 (0x80UL << FSMC_BTR2_DATAST_Pos)
    -
    7236#define FSMC_BTR2_BUSTURN_Pos (16U)
    -
    7237#define FSMC_BTR2_BUSTURN_Msk (0xFUL << FSMC_BTR2_BUSTURN_Pos)
    -
    7238#define FSMC_BTR2_BUSTURN FSMC_BTR2_BUSTURN_Msk
    -
    7239#define FSMC_BTR2_BUSTURN_0 (0x1UL << FSMC_BTR2_BUSTURN_Pos)
    -
    7240#define FSMC_BTR2_BUSTURN_1 (0x2UL << FSMC_BTR2_BUSTURN_Pos)
    -
    7241#define FSMC_BTR2_BUSTURN_2 (0x4UL << FSMC_BTR2_BUSTURN_Pos)
    -
    7242#define FSMC_BTR2_BUSTURN_3 (0x8UL << FSMC_BTR2_BUSTURN_Pos)
    -
    7244#define FSMC_BTR2_CLKDIV_Pos (20U)
    -
    7245#define FSMC_BTR2_CLKDIV_Msk (0xFUL << FSMC_BTR2_CLKDIV_Pos)
    -
    7246#define FSMC_BTR2_CLKDIV FSMC_BTR2_CLKDIV_Msk
    -
    7247#define FSMC_BTR2_CLKDIV_0 (0x1UL << FSMC_BTR2_CLKDIV_Pos)
    -
    7248#define FSMC_BTR2_CLKDIV_1 (0x2UL << FSMC_BTR2_CLKDIV_Pos)
    -
    7249#define FSMC_BTR2_CLKDIV_2 (0x4UL << FSMC_BTR2_CLKDIV_Pos)
    -
    7250#define FSMC_BTR2_CLKDIV_3 (0x8UL << FSMC_BTR2_CLKDIV_Pos)
    -
    7252#define FSMC_BTR2_DATLAT_Pos (24U)
    -
    7253#define FSMC_BTR2_DATLAT_Msk (0xFUL << FSMC_BTR2_DATLAT_Pos)
    -
    7254#define FSMC_BTR2_DATLAT FSMC_BTR2_DATLAT_Msk
    -
    7255#define FSMC_BTR2_DATLAT_0 (0x1UL << FSMC_BTR2_DATLAT_Pos)
    -
    7256#define FSMC_BTR2_DATLAT_1 (0x2UL << FSMC_BTR2_DATLAT_Pos)
    -
    7257#define FSMC_BTR2_DATLAT_2 (0x4UL << FSMC_BTR2_DATLAT_Pos)
    -
    7258#define FSMC_BTR2_DATLAT_3 (0x8UL << FSMC_BTR2_DATLAT_Pos)
    -
    7260#define FSMC_BTR2_ACCMOD_Pos (28U)
    -
    7261#define FSMC_BTR2_ACCMOD_Msk (0x3UL << FSMC_BTR2_ACCMOD_Pos)
    -
    7262#define FSMC_BTR2_ACCMOD FSMC_BTR2_ACCMOD_Msk
    -
    7263#define FSMC_BTR2_ACCMOD_0 (0x1UL << FSMC_BTR2_ACCMOD_Pos)
    -
    7264#define FSMC_BTR2_ACCMOD_1 (0x2UL << FSMC_BTR2_ACCMOD_Pos)
    -
    7266/******************* Bit definition for FSMC_BTR3 register *******************/
    -
    7267#define FSMC_BTR3_ADDSET_Pos (0U)
    -
    7268#define FSMC_BTR3_ADDSET_Msk (0xFUL << FSMC_BTR3_ADDSET_Pos)
    -
    7269#define FSMC_BTR3_ADDSET FSMC_BTR3_ADDSET_Msk
    -
    7270#define FSMC_BTR3_ADDSET_0 (0x1UL << FSMC_BTR3_ADDSET_Pos)
    -
    7271#define FSMC_BTR3_ADDSET_1 (0x2UL << FSMC_BTR3_ADDSET_Pos)
    -
    7272#define FSMC_BTR3_ADDSET_2 (0x4UL << FSMC_BTR3_ADDSET_Pos)
    -
    7273#define FSMC_BTR3_ADDSET_3 (0x8UL << FSMC_BTR3_ADDSET_Pos)
    -
    7275#define FSMC_BTR3_ADDHLD_Pos (4U)
    -
    7276#define FSMC_BTR3_ADDHLD_Msk (0xFUL << FSMC_BTR3_ADDHLD_Pos)
    -
    7277#define FSMC_BTR3_ADDHLD FSMC_BTR3_ADDHLD_Msk
    -
    7278#define FSMC_BTR3_ADDHLD_0 (0x1UL << FSMC_BTR3_ADDHLD_Pos)
    -
    7279#define FSMC_BTR3_ADDHLD_1 (0x2UL << FSMC_BTR3_ADDHLD_Pos)
    -
    7280#define FSMC_BTR3_ADDHLD_2 (0x4UL << FSMC_BTR3_ADDHLD_Pos)
    -
    7281#define FSMC_BTR3_ADDHLD_3 (0x8UL << FSMC_BTR3_ADDHLD_Pos)
    -
    7283#define FSMC_BTR3_DATAST_Pos (8U)
    -
    7284#define FSMC_BTR3_DATAST_Msk (0xFFUL << FSMC_BTR3_DATAST_Pos)
    -
    7285#define FSMC_BTR3_DATAST FSMC_BTR3_DATAST_Msk
    -
    7286#define FSMC_BTR3_DATAST_0 (0x01UL << FSMC_BTR3_DATAST_Pos)
    -
    7287#define FSMC_BTR3_DATAST_1 (0x02UL << FSMC_BTR3_DATAST_Pos)
    -
    7288#define FSMC_BTR3_DATAST_2 (0x04UL << FSMC_BTR3_DATAST_Pos)
    -
    7289#define FSMC_BTR3_DATAST_3 (0x08UL << FSMC_BTR3_DATAST_Pos)
    -
    7290#define FSMC_BTR3_DATAST_4 (0x10UL << FSMC_BTR3_DATAST_Pos)
    -
    7291#define FSMC_BTR3_DATAST_5 (0x20UL << FSMC_BTR3_DATAST_Pos)
    -
    7292#define FSMC_BTR3_DATAST_6 (0x40UL << FSMC_BTR3_DATAST_Pos)
    -
    7293#define FSMC_BTR3_DATAST_7 (0x80UL << FSMC_BTR3_DATAST_Pos)
    -
    7295#define FSMC_BTR3_BUSTURN_Pos (16U)
    -
    7296#define FSMC_BTR3_BUSTURN_Msk (0xFUL << FSMC_BTR3_BUSTURN_Pos)
    -
    7297#define FSMC_BTR3_BUSTURN FSMC_BTR3_BUSTURN_Msk
    -
    7298#define FSMC_BTR3_BUSTURN_0 (0x1UL << FSMC_BTR3_BUSTURN_Pos)
    -
    7299#define FSMC_BTR3_BUSTURN_1 (0x2UL << FSMC_BTR3_BUSTURN_Pos)
    -
    7300#define FSMC_BTR3_BUSTURN_2 (0x4UL << FSMC_BTR3_BUSTURN_Pos)
    -
    7301#define FSMC_BTR3_BUSTURN_3 (0x8UL << FSMC_BTR3_BUSTURN_Pos)
    -
    7303#define FSMC_BTR3_CLKDIV_Pos (20U)
    -
    7304#define FSMC_BTR3_CLKDIV_Msk (0xFUL << FSMC_BTR3_CLKDIV_Pos)
    -
    7305#define FSMC_BTR3_CLKDIV FSMC_BTR3_CLKDIV_Msk
    -
    7306#define FSMC_BTR3_CLKDIV_0 (0x1UL << FSMC_BTR3_CLKDIV_Pos)
    -
    7307#define FSMC_BTR3_CLKDIV_1 (0x2UL << FSMC_BTR3_CLKDIV_Pos)
    -
    7308#define FSMC_BTR3_CLKDIV_2 (0x4UL << FSMC_BTR3_CLKDIV_Pos)
    -
    7309#define FSMC_BTR3_CLKDIV_3 (0x8UL << FSMC_BTR3_CLKDIV_Pos)
    -
    7311#define FSMC_BTR3_DATLAT_Pos (24U)
    -
    7312#define FSMC_BTR3_DATLAT_Msk (0xFUL << FSMC_BTR3_DATLAT_Pos)
    -
    7313#define FSMC_BTR3_DATLAT FSMC_BTR3_DATLAT_Msk
    -
    7314#define FSMC_BTR3_DATLAT_0 (0x1UL << FSMC_BTR3_DATLAT_Pos)
    -
    7315#define FSMC_BTR3_DATLAT_1 (0x2UL << FSMC_BTR3_DATLAT_Pos)
    -
    7316#define FSMC_BTR3_DATLAT_2 (0x4UL << FSMC_BTR3_DATLAT_Pos)
    -
    7317#define FSMC_BTR3_DATLAT_3 (0x8UL << FSMC_BTR3_DATLAT_Pos)
    -
    7319#define FSMC_BTR3_ACCMOD_Pos (28U)
    -
    7320#define FSMC_BTR3_ACCMOD_Msk (0x3UL << FSMC_BTR3_ACCMOD_Pos)
    -
    7321#define FSMC_BTR3_ACCMOD FSMC_BTR3_ACCMOD_Msk
    -
    7322#define FSMC_BTR3_ACCMOD_0 (0x1UL << FSMC_BTR3_ACCMOD_Pos)
    -
    7323#define FSMC_BTR3_ACCMOD_1 (0x2UL << FSMC_BTR3_ACCMOD_Pos)
    -
    7325/****************** Bit definition for FSMC_BTR4 register *******************/
    -
    7326#define FSMC_BTR4_ADDSET_Pos (0U)
    -
    7327#define FSMC_BTR4_ADDSET_Msk (0xFUL << FSMC_BTR4_ADDSET_Pos)
    -
    7328#define FSMC_BTR4_ADDSET FSMC_BTR4_ADDSET_Msk
    -
    7329#define FSMC_BTR4_ADDSET_0 (0x1UL << FSMC_BTR4_ADDSET_Pos)
    -
    7330#define FSMC_BTR4_ADDSET_1 (0x2UL << FSMC_BTR4_ADDSET_Pos)
    -
    7331#define FSMC_BTR4_ADDSET_2 (0x4UL << FSMC_BTR4_ADDSET_Pos)
    -
    7332#define FSMC_BTR4_ADDSET_3 (0x8UL << FSMC_BTR4_ADDSET_Pos)
    -
    7334#define FSMC_BTR4_ADDHLD_Pos (4U)
    -
    7335#define FSMC_BTR4_ADDHLD_Msk (0xFUL << FSMC_BTR4_ADDHLD_Pos)
    -
    7336#define FSMC_BTR4_ADDHLD FSMC_BTR4_ADDHLD_Msk
    -
    7337#define FSMC_BTR4_ADDHLD_0 (0x1UL << FSMC_BTR4_ADDHLD_Pos)
    -
    7338#define FSMC_BTR4_ADDHLD_1 (0x2UL << FSMC_BTR4_ADDHLD_Pos)
    -
    7339#define FSMC_BTR4_ADDHLD_2 (0x4UL << FSMC_BTR4_ADDHLD_Pos)
    -
    7340#define FSMC_BTR4_ADDHLD_3 (0x8UL << FSMC_BTR4_ADDHLD_Pos)
    -
    7342#define FSMC_BTR4_DATAST_Pos (8U)
    -
    7343#define FSMC_BTR4_DATAST_Msk (0xFFUL << FSMC_BTR4_DATAST_Pos)
    -
    7344#define FSMC_BTR4_DATAST FSMC_BTR4_DATAST_Msk
    -
    7345#define FSMC_BTR4_DATAST_0 (0x01UL << FSMC_BTR4_DATAST_Pos)
    -
    7346#define FSMC_BTR4_DATAST_1 (0x02UL << FSMC_BTR4_DATAST_Pos)
    -
    7347#define FSMC_BTR4_DATAST_2 (0x04UL << FSMC_BTR4_DATAST_Pos)
    -
    7348#define FSMC_BTR4_DATAST_3 (0x08UL << FSMC_BTR4_DATAST_Pos)
    -
    7349#define FSMC_BTR4_DATAST_4 (0x10UL << FSMC_BTR4_DATAST_Pos)
    -
    7350#define FSMC_BTR4_DATAST_5 (0x20UL << FSMC_BTR4_DATAST_Pos)
    -
    7351#define FSMC_BTR4_DATAST_6 (0x40UL << FSMC_BTR4_DATAST_Pos)
    -
    7352#define FSMC_BTR4_DATAST_7 (0x80UL << FSMC_BTR4_DATAST_Pos)
    -
    7354#define FSMC_BTR4_BUSTURN_Pos (16U)
    -
    7355#define FSMC_BTR4_BUSTURN_Msk (0xFUL << FSMC_BTR4_BUSTURN_Pos)
    -
    7356#define FSMC_BTR4_BUSTURN FSMC_BTR4_BUSTURN_Msk
    -
    7357#define FSMC_BTR4_BUSTURN_0 (0x1UL << FSMC_BTR4_BUSTURN_Pos)
    -
    7358#define FSMC_BTR4_BUSTURN_1 (0x2UL << FSMC_BTR4_BUSTURN_Pos)
    -
    7359#define FSMC_BTR4_BUSTURN_2 (0x4UL << FSMC_BTR4_BUSTURN_Pos)
    -
    7360#define FSMC_BTR4_BUSTURN_3 (0x8UL << FSMC_BTR4_BUSTURN_Pos)
    -
    7362#define FSMC_BTR4_CLKDIV_Pos (20U)
    -
    7363#define FSMC_BTR4_CLKDIV_Msk (0xFUL << FSMC_BTR4_CLKDIV_Pos)
    -
    7364#define FSMC_BTR4_CLKDIV FSMC_BTR4_CLKDIV_Msk
    -
    7365#define FSMC_BTR4_CLKDIV_0 (0x1UL << FSMC_BTR4_CLKDIV_Pos)
    -
    7366#define FSMC_BTR4_CLKDIV_1 (0x2UL << FSMC_BTR4_CLKDIV_Pos)
    -
    7367#define FSMC_BTR4_CLKDIV_2 (0x4UL << FSMC_BTR4_CLKDIV_Pos)
    -
    7368#define FSMC_BTR4_CLKDIV_3 (0x8UL << FSMC_BTR4_CLKDIV_Pos)
    -
    7370#define FSMC_BTR4_DATLAT_Pos (24U)
    -
    7371#define FSMC_BTR4_DATLAT_Msk (0xFUL << FSMC_BTR4_DATLAT_Pos)
    -
    7372#define FSMC_BTR4_DATLAT FSMC_BTR4_DATLAT_Msk
    -
    7373#define FSMC_BTR4_DATLAT_0 (0x1UL << FSMC_BTR4_DATLAT_Pos)
    -
    7374#define FSMC_BTR4_DATLAT_1 (0x2UL << FSMC_BTR4_DATLAT_Pos)
    -
    7375#define FSMC_BTR4_DATLAT_2 (0x4UL << FSMC_BTR4_DATLAT_Pos)
    -
    7376#define FSMC_BTR4_DATLAT_3 (0x8UL << FSMC_BTR4_DATLAT_Pos)
    -
    7378#define FSMC_BTR4_ACCMOD_Pos (28U)
    -
    7379#define FSMC_BTR4_ACCMOD_Msk (0x3UL << FSMC_BTR4_ACCMOD_Pos)
    -
    7380#define FSMC_BTR4_ACCMOD FSMC_BTR4_ACCMOD_Msk
    -
    7381#define FSMC_BTR4_ACCMOD_0 (0x1UL << FSMC_BTR4_ACCMOD_Pos)
    -
    7382#define FSMC_BTR4_ACCMOD_1 (0x2UL << FSMC_BTR4_ACCMOD_Pos)
    -
    7384/****************** Bit definition for FSMC_BWTR1 register ******************/
    -
    7385#define FSMC_BWTR1_ADDSET_Pos (0U)
    -
    7386#define FSMC_BWTR1_ADDSET_Msk (0xFUL << FSMC_BWTR1_ADDSET_Pos)
    -
    7387#define FSMC_BWTR1_ADDSET FSMC_BWTR1_ADDSET_Msk
    -
    7388#define FSMC_BWTR1_ADDSET_0 (0x1UL << FSMC_BWTR1_ADDSET_Pos)
    -
    7389#define FSMC_BWTR1_ADDSET_1 (0x2UL << FSMC_BWTR1_ADDSET_Pos)
    -
    7390#define FSMC_BWTR1_ADDSET_2 (0x4UL << FSMC_BWTR1_ADDSET_Pos)
    -
    7391#define FSMC_BWTR1_ADDSET_3 (0x8UL << FSMC_BWTR1_ADDSET_Pos)
    -
    7393#define FSMC_BWTR1_ADDHLD_Pos (4U)
    -
    7394#define FSMC_BWTR1_ADDHLD_Msk (0xFUL << FSMC_BWTR1_ADDHLD_Pos)
    -
    7395#define FSMC_BWTR1_ADDHLD FSMC_BWTR1_ADDHLD_Msk
    -
    7396#define FSMC_BWTR1_ADDHLD_0 (0x1UL << FSMC_BWTR1_ADDHLD_Pos)
    -
    7397#define FSMC_BWTR1_ADDHLD_1 (0x2UL << FSMC_BWTR1_ADDHLD_Pos)
    -
    7398#define FSMC_BWTR1_ADDHLD_2 (0x4UL << FSMC_BWTR1_ADDHLD_Pos)
    -
    7399#define FSMC_BWTR1_ADDHLD_3 (0x8UL << FSMC_BWTR1_ADDHLD_Pos)
    -
    7401#define FSMC_BWTR1_DATAST_Pos (8U)
    -
    7402#define FSMC_BWTR1_DATAST_Msk (0xFFUL << FSMC_BWTR1_DATAST_Pos)
    -
    7403#define FSMC_BWTR1_DATAST FSMC_BWTR1_DATAST_Msk
    -
    7404#define FSMC_BWTR1_DATAST_0 (0x01UL << FSMC_BWTR1_DATAST_Pos)
    -
    7405#define FSMC_BWTR1_DATAST_1 (0x02UL << FSMC_BWTR1_DATAST_Pos)
    -
    7406#define FSMC_BWTR1_DATAST_2 (0x04UL << FSMC_BWTR1_DATAST_Pos)
    -
    7407#define FSMC_BWTR1_DATAST_3 (0x08UL << FSMC_BWTR1_DATAST_Pos)
    -
    7408#define FSMC_BWTR1_DATAST_4 (0x10UL << FSMC_BWTR1_DATAST_Pos)
    -
    7409#define FSMC_BWTR1_DATAST_5 (0x20UL << FSMC_BWTR1_DATAST_Pos)
    -
    7410#define FSMC_BWTR1_DATAST_6 (0x40UL << FSMC_BWTR1_DATAST_Pos)
    -
    7411#define FSMC_BWTR1_DATAST_7 (0x80UL << FSMC_BWTR1_DATAST_Pos)
    -
    7413#define FSMC_BWTR1_BUSTURN_Pos (16U)
    -
    7414#define FSMC_BWTR1_BUSTURN_Msk (0xFUL << FSMC_BWTR1_BUSTURN_Pos)
    -
    7415#define FSMC_BWTR1_BUSTURN FSMC_BWTR1_BUSTURN_Msk
    -
    7416#define FSMC_BWTR1_BUSTURN_0 (0x1UL << FSMC_BWTR1_BUSTURN_Pos)
    -
    7417#define FSMC_BWTR1_BUSTURN_1 (0x2UL << FSMC_BWTR1_BUSTURN_Pos)
    -
    7418#define FSMC_BWTR1_BUSTURN_2 (0x4UL << FSMC_BWTR1_BUSTURN_Pos)
    -
    7419#define FSMC_BWTR1_BUSTURN_3 (0x8UL << FSMC_BWTR1_BUSTURN_Pos)
    -
    7421#define FSMC_BWTR1_ACCMOD_Pos (28U)
    -
    7422#define FSMC_BWTR1_ACCMOD_Msk (0x3UL << FSMC_BWTR1_ACCMOD_Pos)
    -
    7423#define FSMC_BWTR1_ACCMOD FSMC_BWTR1_ACCMOD_Msk
    -
    7424#define FSMC_BWTR1_ACCMOD_0 (0x1UL << FSMC_BWTR1_ACCMOD_Pos)
    -
    7425#define FSMC_BWTR1_ACCMOD_1 (0x2UL << FSMC_BWTR1_ACCMOD_Pos)
    -
    7427/****************** Bit definition for FSMC_BWTR2 register ******************/
    -
    7428#define FSMC_BWTR2_ADDSET_Pos (0U)
    -
    7429#define FSMC_BWTR2_ADDSET_Msk (0xFUL << FSMC_BWTR2_ADDSET_Pos)
    -
    7430#define FSMC_BWTR2_ADDSET FSMC_BWTR2_ADDSET_Msk
    -
    7431#define FSMC_BWTR2_ADDSET_0 (0x1UL << FSMC_BWTR2_ADDSET_Pos)
    -
    7432#define FSMC_BWTR2_ADDSET_1 (0x2UL << FSMC_BWTR2_ADDSET_Pos)
    -
    7433#define FSMC_BWTR2_ADDSET_2 (0x4UL << FSMC_BWTR2_ADDSET_Pos)
    -
    7434#define FSMC_BWTR2_ADDSET_3 (0x8UL << FSMC_BWTR2_ADDSET_Pos)
    -
    7436#define FSMC_BWTR2_ADDHLD_Pos (4U)
    -
    7437#define FSMC_BWTR2_ADDHLD_Msk (0xFUL << FSMC_BWTR2_ADDHLD_Pos)
    -
    7438#define FSMC_BWTR2_ADDHLD FSMC_BWTR2_ADDHLD_Msk
    -
    7439#define FSMC_BWTR2_ADDHLD_0 (0x1UL << FSMC_BWTR2_ADDHLD_Pos)
    -
    7440#define FSMC_BWTR2_ADDHLD_1 (0x2UL << FSMC_BWTR2_ADDHLD_Pos)
    -
    7441#define FSMC_BWTR2_ADDHLD_2 (0x4UL << FSMC_BWTR2_ADDHLD_Pos)
    -
    7442#define FSMC_BWTR2_ADDHLD_3 (0x8UL << FSMC_BWTR2_ADDHLD_Pos)
    -
    7444#define FSMC_BWTR2_DATAST_Pos (8U)
    -
    7445#define FSMC_BWTR2_DATAST_Msk (0xFFUL << FSMC_BWTR2_DATAST_Pos)
    -
    7446#define FSMC_BWTR2_DATAST FSMC_BWTR2_DATAST_Msk
    -
    7447#define FSMC_BWTR2_DATAST_0 (0x01UL << FSMC_BWTR2_DATAST_Pos)
    -
    7448#define FSMC_BWTR2_DATAST_1 (0x02UL << FSMC_BWTR2_DATAST_Pos)
    -
    7449#define FSMC_BWTR2_DATAST_2 (0x04UL << FSMC_BWTR2_DATAST_Pos)
    -
    7450#define FSMC_BWTR2_DATAST_3 (0x08UL << FSMC_BWTR2_DATAST_Pos)
    -
    7451#define FSMC_BWTR2_DATAST_4 (0x10UL << FSMC_BWTR2_DATAST_Pos)
    -
    7452#define FSMC_BWTR2_DATAST_5 (0x20UL << FSMC_BWTR2_DATAST_Pos)
    -
    7453#define FSMC_BWTR2_DATAST_6 (0x40UL << FSMC_BWTR2_DATAST_Pos)
    -
    7454#define FSMC_BWTR2_DATAST_7 (0x80UL << FSMC_BWTR2_DATAST_Pos)
    -
    7456#define FSMC_BWTR2_BUSTURN_Pos (16U)
    -
    7457#define FSMC_BWTR2_BUSTURN_Msk (0xFUL << FSMC_BWTR2_BUSTURN_Pos)
    -
    7458#define FSMC_BWTR2_BUSTURN FSMC_BWTR2_BUSTURN_Msk
    -
    7459#define FSMC_BWTR2_BUSTURN_0 (0x1UL << FSMC_BWTR2_BUSTURN_Pos)
    -
    7460#define FSMC_BWTR2_BUSTURN_1 (0x2UL << FSMC_BWTR2_BUSTURN_Pos)
    -
    7461#define FSMC_BWTR2_BUSTURN_2 (0x4UL << FSMC_BWTR2_BUSTURN_Pos)
    -
    7462#define FSMC_BWTR2_BUSTURN_3 (0x8UL << FSMC_BWTR2_BUSTURN_Pos)
    -
    7464#define FSMC_BWTR2_ACCMOD_Pos (28U)
    -
    7465#define FSMC_BWTR2_ACCMOD_Msk (0x3UL << FSMC_BWTR2_ACCMOD_Pos)
    -
    7466#define FSMC_BWTR2_ACCMOD FSMC_BWTR2_ACCMOD_Msk
    -
    7467#define FSMC_BWTR2_ACCMOD_0 (0x1UL << FSMC_BWTR2_ACCMOD_Pos)
    -
    7468#define FSMC_BWTR2_ACCMOD_1 (0x2UL << FSMC_BWTR2_ACCMOD_Pos)
    -
    7470/****************** Bit definition for FSMC_BWTR3 register ******************/
    -
    7471#define FSMC_BWTR3_ADDSET_Pos (0U)
    -
    7472#define FSMC_BWTR3_ADDSET_Msk (0xFUL << FSMC_BWTR3_ADDSET_Pos)
    -
    7473#define FSMC_BWTR3_ADDSET FSMC_BWTR3_ADDSET_Msk
    -
    7474#define FSMC_BWTR3_ADDSET_0 (0x1UL << FSMC_BWTR3_ADDSET_Pos)
    -
    7475#define FSMC_BWTR3_ADDSET_1 (0x2UL << FSMC_BWTR3_ADDSET_Pos)
    -
    7476#define FSMC_BWTR3_ADDSET_2 (0x4UL << FSMC_BWTR3_ADDSET_Pos)
    -
    7477#define FSMC_BWTR3_ADDSET_3 (0x8UL << FSMC_BWTR3_ADDSET_Pos)
    -
    7479#define FSMC_BWTR3_ADDHLD_Pos (4U)
    -
    7480#define FSMC_BWTR3_ADDHLD_Msk (0xFUL << FSMC_BWTR3_ADDHLD_Pos)
    -
    7481#define FSMC_BWTR3_ADDHLD FSMC_BWTR3_ADDHLD_Msk
    -
    7482#define FSMC_BWTR3_ADDHLD_0 (0x1UL << FSMC_BWTR3_ADDHLD_Pos)
    -
    7483#define FSMC_BWTR3_ADDHLD_1 (0x2UL << FSMC_BWTR3_ADDHLD_Pos)
    -
    7484#define FSMC_BWTR3_ADDHLD_2 (0x4UL << FSMC_BWTR3_ADDHLD_Pos)
    -
    7485#define FSMC_BWTR3_ADDHLD_3 (0x8UL << FSMC_BWTR3_ADDHLD_Pos)
    -
    7487#define FSMC_BWTR3_DATAST_Pos (8U)
    -
    7488#define FSMC_BWTR3_DATAST_Msk (0xFFUL << FSMC_BWTR3_DATAST_Pos)
    -
    7489#define FSMC_BWTR3_DATAST FSMC_BWTR3_DATAST_Msk
    -
    7490#define FSMC_BWTR3_DATAST_0 (0x01UL << FSMC_BWTR3_DATAST_Pos)
    -
    7491#define FSMC_BWTR3_DATAST_1 (0x02UL << FSMC_BWTR3_DATAST_Pos)
    -
    7492#define FSMC_BWTR3_DATAST_2 (0x04UL << FSMC_BWTR3_DATAST_Pos)
    -
    7493#define FSMC_BWTR3_DATAST_3 (0x08UL << FSMC_BWTR3_DATAST_Pos)
    -
    7494#define FSMC_BWTR3_DATAST_4 (0x10UL << FSMC_BWTR3_DATAST_Pos)
    -
    7495#define FSMC_BWTR3_DATAST_5 (0x20UL << FSMC_BWTR3_DATAST_Pos)
    -
    7496#define FSMC_BWTR3_DATAST_6 (0x40UL << FSMC_BWTR3_DATAST_Pos)
    -
    7497#define FSMC_BWTR3_DATAST_7 (0x80UL << FSMC_BWTR3_DATAST_Pos)
    -
    7499#define FSMC_BWTR3_BUSTURN_Pos (16U)
    -
    7500#define FSMC_BWTR3_BUSTURN_Msk (0xFUL << FSMC_BWTR3_BUSTURN_Pos)
    -
    7501#define FSMC_BWTR3_BUSTURN FSMC_BWTR3_BUSTURN_Msk
    -
    7502#define FSMC_BWTR3_BUSTURN_0 (0x1UL << FSMC_BWTR3_BUSTURN_Pos)
    -
    7503#define FSMC_BWTR3_BUSTURN_1 (0x2UL << FSMC_BWTR3_BUSTURN_Pos)
    -
    7504#define FSMC_BWTR3_BUSTURN_2 (0x4UL << FSMC_BWTR3_BUSTURN_Pos)
    -
    7505#define FSMC_BWTR3_BUSTURN_3 (0x8UL << FSMC_BWTR3_BUSTURN_Pos)
    -
    7507#define FSMC_BWTR3_ACCMOD_Pos (28U)
    -
    7508#define FSMC_BWTR3_ACCMOD_Msk (0x3UL << FSMC_BWTR3_ACCMOD_Pos)
    -
    7509#define FSMC_BWTR3_ACCMOD FSMC_BWTR3_ACCMOD_Msk
    -
    7510#define FSMC_BWTR3_ACCMOD_0 (0x1UL << FSMC_BWTR3_ACCMOD_Pos)
    -
    7511#define FSMC_BWTR3_ACCMOD_1 (0x2UL << FSMC_BWTR3_ACCMOD_Pos)
    -
    7513/****************** Bit definition for FSMC_BWTR4 register ******************/
    -
    7514#define FSMC_BWTR4_ADDSET_Pos (0U)
    -
    7515#define FSMC_BWTR4_ADDSET_Msk (0xFUL << FSMC_BWTR4_ADDSET_Pos)
    -
    7516#define FSMC_BWTR4_ADDSET FSMC_BWTR4_ADDSET_Msk
    -
    7517#define FSMC_BWTR4_ADDSET_0 (0x1UL << FSMC_BWTR4_ADDSET_Pos)
    -
    7518#define FSMC_BWTR4_ADDSET_1 (0x2UL << FSMC_BWTR4_ADDSET_Pos)
    -
    7519#define FSMC_BWTR4_ADDSET_2 (0x4UL << FSMC_BWTR4_ADDSET_Pos)
    -
    7520#define FSMC_BWTR4_ADDSET_3 (0x8UL << FSMC_BWTR4_ADDSET_Pos)
    -
    7522#define FSMC_BWTR4_ADDHLD_Pos (4U)
    -
    7523#define FSMC_BWTR4_ADDHLD_Msk (0xFUL << FSMC_BWTR4_ADDHLD_Pos)
    -
    7524#define FSMC_BWTR4_ADDHLD FSMC_BWTR4_ADDHLD_Msk
    -
    7525#define FSMC_BWTR4_ADDHLD_0 (0x1UL << FSMC_BWTR4_ADDHLD_Pos)
    -
    7526#define FSMC_BWTR4_ADDHLD_1 (0x2UL << FSMC_BWTR4_ADDHLD_Pos)
    -
    7527#define FSMC_BWTR4_ADDHLD_2 (0x4UL << FSMC_BWTR4_ADDHLD_Pos)
    -
    7528#define FSMC_BWTR4_ADDHLD_3 (0x8UL << FSMC_BWTR4_ADDHLD_Pos)
    -
    7530#define FSMC_BWTR4_DATAST_Pos (8U)
    -
    7531#define FSMC_BWTR4_DATAST_Msk (0xFFUL << FSMC_BWTR4_DATAST_Pos)
    -
    7532#define FSMC_BWTR4_DATAST FSMC_BWTR4_DATAST_Msk
    -
    7533#define FSMC_BWTR4_DATAST_0 0x00000100U
    -
    7534#define FSMC_BWTR4_DATAST_1 0x00000200U
    -
    7535#define FSMC_BWTR4_DATAST_2 0x00000400U
    -
    7536#define FSMC_BWTR4_DATAST_3 0x00000800U
    -
    7537#define FSMC_BWTR4_DATAST_4 0x00001000U
    -
    7538#define FSMC_BWTR4_DATAST_5 0x00002000U
    -
    7539#define FSMC_BWTR4_DATAST_6 0x00004000U
    -
    7540#define FSMC_BWTR4_DATAST_7 0x00008000U
    -
    7542#define FSMC_BWTR4_BUSTURN_Pos (16U)
    -
    7543#define FSMC_BWTR4_BUSTURN_Msk (0xFUL << FSMC_BWTR4_BUSTURN_Pos)
    -
    7544#define FSMC_BWTR4_BUSTURN FSMC_BWTR4_BUSTURN_Msk
    -
    7545#define FSMC_BWTR4_BUSTURN_0 (0x1UL << FSMC_BWTR4_BUSTURN_Pos)
    -
    7546#define FSMC_BWTR4_BUSTURN_1 (0x2UL << FSMC_BWTR4_BUSTURN_Pos)
    -
    7547#define FSMC_BWTR4_BUSTURN_2 (0x4UL << FSMC_BWTR4_BUSTURN_Pos)
    -
    7548#define FSMC_BWTR4_BUSTURN_3 (0x8UL << FSMC_BWTR4_BUSTURN_Pos)
    -
    7550#define FSMC_BWTR4_ACCMOD_Pos (28U)
    -
    7551#define FSMC_BWTR4_ACCMOD_Msk (0x3UL << FSMC_BWTR4_ACCMOD_Pos)
    -
    7552#define FSMC_BWTR4_ACCMOD FSMC_BWTR4_ACCMOD_Msk
    -
    7553#define FSMC_BWTR4_ACCMOD_0 (0x1UL << FSMC_BWTR4_ACCMOD_Pos)
    -
    7554#define FSMC_BWTR4_ACCMOD_1 (0x2UL << FSMC_BWTR4_ACCMOD_Pos)
    -
    7556/****************** Bit definition for FSMC_PCR2 register *******************/
    -
    7557#define FSMC_PCR2_PWAITEN_Pos (1U)
    -
    7558#define FSMC_PCR2_PWAITEN_Msk (0x1UL << FSMC_PCR2_PWAITEN_Pos)
    -
    7559#define FSMC_PCR2_PWAITEN FSMC_PCR2_PWAITEN_Msk
    -
    7560#define FSMC_PCR2_PBKEN_Pos (2U)
    -
    7561#define FSMC_PCR2_PBKEN_Msk (0x1UL << FSMC_PCR2_PBKEN_Pos)
    -
    7562#define FSMC_PCR2_PBKEN FSMC_PCR2_PBKEN_Msk
    -
    7563#define FSMC_PCR2_PTYP_Pos (3U)
    -
    7564#define FSMC_PCR2_PTYP_Msk (0x1UL << FSMC_PCR2_PTYP_Pos)
    -
    7565#define FSMC_PCR2_PTYP FSMC_PCR2_PTYP_Msk
    -
    7567#define FSMC_PCR2_PWID_Pos (4U)
    -
    7568#define FSMC_PCR2_PWID_Msk (0x3UL << FSMC_PCR2_PWID_Pos)
    -
    7569#define FSMC_PCR2_PWID FSMC_PCR2_PWID_Msk
    -
    7570#define FSMC_PCR2_PWID_0 (0x1UL << FSMC_PCR2_PWID_Pos)
    -
    7571#define FSMC_PCR2_PWID_1 (0x2UL << FSMC_PCR2_PWID_Pos)
    -
    7573#define FSMC_PCR2_ECCEN_Pos (6U)
    -
    7574#define FSMC_PCR2_ECCEN_Msk (0x1UL << FSMC_PCR2_ECCEN_Pos)
    -
    7575#define FSMC_PCR2_ECCEN FSMC_PCR2_ECCEN_Msk
    -
    7577#define FSMC_PCR2_TCLR_Pos (9U)
    -
    7578#define FSMC_PCR2_TCLR_Msk (0xFUL << FSMC_PCR2_TCLR_Pos)
    -
    7579#define FSMC_PCR2_TCLR FSMC_PCR2_TCLR_Msk
    -
    7580#define FSMC_PCR2_TCLR_0 (0x1UL << FSMC_PCR2_TCLR_Pos)
    -
    7581#define FSMC_PCR2_TCLR_1 (0x2UL << FSMC_PCR2_TCLR_Pos)
    -
    7582#define FSMC_PCR2_TCLR_2 (0x4UL << FSMC_PCR2_TCLR_Pos)
    -
    7583#define FSMC_PCR2_TCLR_3 (0x8UL << FSMC_PCR2_TCLR_Pos)
    -
    7585#define FSMC_PCR2_TAR_Pos (13U)
    -
    7586#define FSMC_PCR2_TAR_Msk (0xFUL << FSMC_PCR2_TAR_Pos)
    -
    7587#define FSMC_PCR2_TAR FSMC_PCR2_TAR_Msk
    -
    7588#define FSMC_PCR2_TAR_0 (0x1UL << FSMC_PCR2_TAR_Pos)
    -
    7589#define FSMC_PCR2_TAR_1 (0x2UL << FSMC_PCR2_TAR_Pos)
    -
    7590#define FSMC_PCR2_TAR_2 (0x4UL << FSMC_PCR2_TAR_Pos)
    -
    7591#define FSMC_PCR2_TAR_3 (0x8UL << FSMC_PCR2_TAR_Pos)
    -
    7593#define FSMC_PCR2_ECCPS_Pos (17U)
    -
    7594#define FSMC_PCR2_ECCPS_Msk (0x7UL << FSMC_PCR2_ECCPS_Pos)
    -
    7595#define FSMC_PCR2_ECCPS FSMC_PCR2_ECCPS_Msk
    -
    7596#define FSMC_PCR2_ECCPS_0 (0x1UL << FSMC_PCR2_ECCPS_Pos)
    -
    7597#define FSMC_PCR2_ECCPS_1 (0x2UL << FSMC_PCR2_ECCPS_Pos)
    -
    7598#define FSMC_PCR2_ECCPS_2 (0x4UL << FSMC_PCR2_ECCPS_Pos)
    -
    7600/****************** Bit definition for FSMC_PCR3 register *******************/
    -
    7601#define FSMC_PCR3_PWAITEN_Pos (1U)
    -
    7602#define FSMC_PCR3_PWAITEN_Msk (0x1UL << FSMC_PCR3_PWAITEN_Pos)
    -
    7603#define FSMC_PCR3_PWAITEN FSMC_PCR3_PWAITEN_Msk
    -
    7604#define FSMC_PCR3_PBKEN_Pos (2U)
    -
    7605#define FSMC_PCR3_PBKEN_Msk (0x1UL << FSMC_PCR3_PBKEN_Pos)
    -
    7606#define FSMC_PCR3_PBKEN FSMC_PCR3_PBKEN_Msk
    -
    7607#define FSMC_PCR3_PTYP_Pos (3U)
    -
    7608#define FSMC_PCR3_PTYP_Msk (0x1UL << FSMC_PCR3_PTYP_Pos)
    -
    7609#define FSMC_PCR3_PTYP FSMC_PCR3_PTYP_Msk
    -
    7611#define FSMC_PCR3_PWID_Pos (4U)
    -
    7612#define FSMC_PCR3_PWID_Msk (0x3UL << FSMC_PCR3_PWID_Pos)
    -
    7613#define FSMC_PCR3_PWID FSMC_PCR3_PWID_Msk
    -
    7614#define FSMC_PCR3_PWID_0 (0x1UL << FSMC_PCR3_PWID_Pos)
    -
    7615#define FSMC_PCR3_PWID_1 (0x2UL << FSMC_PCR3_PWID_Pos)
    -
    7617#define FSMC_PCR3_ECCEN_Pos (6U)
    -
    7618#define FSMC_PCR3_ECCEN_Msk (0x1UL << FSMC_PCR3_ECCEN_Pos)
    -
    7619#define FSMC_PCR3_ECCEN FSMC_PCR3_ECCEN_Msk
    -
    7621#define FSMC_PCR3_TCLR_Pos (9U)
    -
    7622#define FSMC_PCR3_TCLR_Msk (0xFUL << FSMC_PCR3_TCLR_Pos)
    -
    7623#define FSMC_PCR3_TCLR FSMC_PCR3_TCLR_Msk
    -
    7624#define FSMC_PCR3_TCLR_0 (0x1UL << FSMC_PCR3_TCLR_Pos)
    -
    7625#define FSMC_PCR3_TCLR_1 (0x2UL << FSMC_PCR3_TCLR_Pos)
    -
    7626#define FSMC_PCR3_TCLR_2 (0x4UL << FSMC_PCR3_TCLR_Pos)
    -
    7627#define FSMC_PCR3_TCLR_3 (0x8UL << FSMC_PCR3_TCLR_Pos)
    -
    7629#define FSMC_PCR3_TAR_Pos (13U)
    -
    7630#define FSMC_PCR3_TAR_Msk (0xFUL << FSMC_PCR3_TAR_Pos)
    -
    7631#define FSMC_PCR3_TAR FSMC_PCR3_TAR_Msk
    -
    7632#define FSMC_PCR3_TAR_0 (0x1UL << FSMC_PCR3_TAR_Pos)
    -
    7633#define FSMC_PCR3_TAR_1 (0x2UL << FSMC_PCR3_TAR_Pos)
    -
    7634#define FSMC_PCR3_TAR_2 (0x4UL << FSMC_PCR3_TAR_Pos)
    -
    7635#define FSMC_PCR3_TAR_3 (0x8UL << FSMC_PCR3_TAR_Pos)
    -
    7637#define FSMC_PCR3_ECCPS_Pos (17U)
    -
    7638#define FSMC_PCR3_ECCPS_Msk (0x7UL << FSMC_PCR3_ECCPS_Pos)
    -
    7639#define FSMC_PCR3_ECCPS FSMC_PCR3_ECCPS_Msk
    -
    7640#define FSMC_PCR3_ECCPS_0 (0x1UL << FSMC_PCR3_ECCPS_Pos)
    -
    7641#define FSMC_PCR3_ECCPS_1 (0x2UL << FSMC_PCR3_ECCPS_Pos)
    -
    7642#define FSMC_PCR3_ECCPS_2 (0x4UL << FSMC_PCR3_ECCPS_Pos)
    -
    7644/****************** Bit definition for FSMC_PCR4 register *******************/
    -
    7645#define FSMC_PCR4_PWAITEN_Pos (1U)
    -
    7646#define FSMC_PCR4_PWAITEN_Msk (0x1UL << FSMC_PCR4_PWAITEN_Pos)
    -
    7647#define FSMC_PCR4_PWAITEN FSMC_PCR4_PWAITEN_Msk
    -
    7648#define FSMC_PCR4_PBKEN_Pos (2U)
    -
    7649#define FSMC_PCR4_PBKEN_Msk (0x1UL << FSMC_PCR4_PBKEN_Pos)
    -
    7650#define FSMC_PCR4_PBKEN FSMC_PCR4_PBKEN_Msk
    -
    7651#define FSMC_PCR4_PTYP_Pos (3U)
    -
    7652#define FSMC_PCR4_PTYP_Msk (0x1UL << FSMC_PCR4_PTYP_Pos)
    -
    7653#define FSMC_PCR4_PTYP FSMC_PCR4_PTYP_Msk
    -
    7655#define FSMC_PCR4_PWID_Pos (4U)
    -
    7656#define FSMC_PCR4_PWID_Msk (0x3UL << FSMC_PCR4_PWID_Pos)
    -
    7657#define FSMC_PCR4_PWID FSMC_PCR4_PWID_Msk
    -
    7658#define FSMC_PCR4_PWID_0 (0x1UL << FSMC_PCR4_PWID_Pos)
    -
    7659#define FSMC_PCR4_PWID_1 (0x2UL << FSMC_PCR4_PWID_Pos)
    -
    7661#define FSMC_PCR4_ECCEN_Pos (6U)
    -
    7662#define FSMC_PCR4_ECCEN_Msk (0x1UL << FSMC_PCR4_ECCEN_Pos)
    -
    7663#define FSMC_PCR4_ECCEN FSMC_PCR4_ECCEN_Msk
    -
    7665#define FSMC_PCR4_TCLR_Pos (9U)
    -
    7666#define FSMC_PCR4_TCLR_Msk (0xFUL << FSMC_PCR4_TCLR_Pos)
    -
    7667#define FSMC_PCR4_TCLR FSMC_PCR4_TCLR_Msk
    -
    7668#define FSMC_PCR4_TCLR_0 (0x1UL << FSMC_PCR4_TCLR_Pos)
    -
    7669#define FSMC_PCR4_TCLR_1 (0x2UL << FSMC_PCR4_TCLR_Pos)
    -
    7670#define FSMC_PCR4_TCLR_2 (0x4UL << FSMC_PCR4_TCLR_Pos)
    -
    7671#define FSMC_PCR4_TCLR_3 (0x8UL << FSMC_PCR4_TCLR_Pos)
    -
    7673#define FSMC_PCR4_TAR_Pos (13U)
    -
    7674#define FSMC_PCR4_TAR_Msk (0xFUL << FSMC_PCR4_TAR_Pos)
    -
    7675#define FSMC_PCR4_TAR FSMC_PCR4_TAR_Msk
    -
    7676#define FSMC_PCR4_TAR_0 (0x1UL << FSMC_PCR4_TAR_Pos)
    -
    7677#define FSMC_PCR4_TAR_1 (0x2UL << FSMC_PCR4_TAR_Pos)
    -
    7678#define FSMC_PCR4_TAR_2 (0x4UL << FSMC_PCR4_TAR_Pos)
    -
    7679#define FSMC_PCR4_TAR_3 (0x8UL << FSMC_PCR4_TAR_Pos)
    -
    7681#define FSMC_PCR4_ECCPS_Pos (17U)
    -
    7682#define FSMC_PCR4_ECCPS_Msk (0x7UL << FSMC_PCR4_ECCPS_Pos)
    -
    7683#define FSMC_PCR4_ECCPS FSMC_PCR4_ECCPS_Msk
    -
    7684#define FSMC_PCR4_ECCPS_0 (0x1UL << FSMC_PCR4_ECCPS_Pos)
    -
    7685#define FSMC_PCR4_ECCPS_1 (0x2UL << FSMC_PCR4_ECCPS_Pos)
    -
    7686#define FSMC_PCR4_ECCPS_2 (0x4UL << FSMC_PCR4_ECCPS_Pos)
    -
    7688/******************* Bit definition for FSMC_SR2 register *******************/
    -
    7689#define FSMC_SR2_IRS_Pos (0U)
    -
    7690#define FSMC_SR2_IRS_Msk (0x1UL << FSMC_SR2_IRS_Pos)
    -
    7691#define FSMC_SR2_IRS FSMC_SR2_IRS_Msk
    -
    7692#define FSMC_SR2_ILS_Pos (1U)
    -
    7693#define FSMC_SR2_ILS_Msk (0x1UL << FSMC_SR2_ILS_Pos)
    -
    7694#define FSMC_SR2_ILS FSMC_SR2_ILS_Msk
    -
    7695#define FSMC_SR2_IFS_Pos (2U)
    -
    7696#define FSMC_SR2_IFS_Msk (0x1UL << FSMC_SR2_IFS_Pos)
    -
    7697#define FSMC_SR2_IFS FSMC_SR2_IFS_Msk
    -
    7698#define FSMC_SR2_IREN_Pos (3U)
    -
    7699#define FSMC_SR2_IREN_Msk (0x1UL << FSMC_SR2_IREN_Pos)
    -
    7700#define FSMC_SR2_IREN FSMC_SR2_IREN_Msk
    -
    7701#define FSMC_SR2_ILEN_Pos (4U)
    -
    7702#define FSMC_SR2_ILEN_Msk (0x1UL << FSMC_SR2_ILEN_Pos)
    -
    7703#define FSMC_SR2_ILEN FSMC_SR2_ILEN_Msk
    -
    7704#define FSMC_SR2_IFEN_Pos (5U)
    -
    7705#define FSMC_SR2_IFEN_Msk (0x1UL << FSMC_SR2_IFEN_Pos)
    -
    7706#define FSMC_SR2_IFEN FSMC_SR2_IFEN_Msk
    -
    7707#define FSMC_SR2_FEMPT_Pos (6U)
    -
    7708#define FSMC_SR2_FEMPT_Msk (0x1UL << FSMC_SR2_FEMPT_Pos)
    -
    7709#define FSMC_SR2_FEMPT FSMC_SR2_FEMPT_Msk
    -
    7711/******************* Bit definition for FSMC_SR3 register *******************/
    -
    7712#define FSMC_SR3_IRS_Pos (0U)
    -
    7713#define FSMC_SR3_IRS_Msk (0x1UL << FSMC_SR3_IRS_Pos)
    -
    7714#define FSMC_SR3_IRS FSMC_SR3_IRS_Msk
    -
    7715#define FSMC_SR3_ILS_Pos (1U)
    -
    7716#define FSMC_SR3_ILS_Msk (0x1UL << FSMC_SR3_ILS_Pos)
    -
    7717#define FSMC_SR3_ILS FSMC_SR3_ILS_Msk
    -
    7718#define FSMC_SR3_IFS_Pos (2U)
    -
    7719#define FSMC_SR3_IFS_Msk (0x1UL << FSMC_SR3_IFS_Pos)
    -
    7720#define FSMC_SR3_IFS FSMC_SR3_IFS_Msk
    -
    7721#define FSMC_SR3_IREN_Pos (3U)
    -
    7722#define FSMC_SR3_IREN_Msk (0x1UL << FSMC_SR3_IREN_Pos)
    -
    7723#define FSMC_SR3_IREN FSMC_SR3_IREN_Msk
    -
    7724#define FSMC_SR3_ILEN_Pos (4U)
    -
    7725#define FSMC_SR3_ILEN_Msk (0x1UL << FSMC_SR3_ILEN_Pos)
    -
    7726#define FSMC_SR3_ILEN FSMC_SR3_ILEN_Msk
    -
    7727#define FSMC_SR3_IFEN_Pos (5U)
    -
    7728#define FSMC_SR3_IFEN_Msk (0x1UL << FSMC_SR3_IFEN_Pos)
    -
    7729#define FSMC_SR3_IFEN FSMC_SR3_IFEN_Msk
    -
    7730#define FSMC_SR3_FEMPT_Pos (6U)
    -
    7731#define FSMC_SR3_FEMPT_Msk (0x1UL << FSMC_SR3_FEMPT_Pos)
    -
    7732#define FSMC_SR3_FEMPT FSMC_SR3_FEMPT_Msk
    -
    7734/******************* Bit definition for FSMC_SR4 register *******************/
    -
    7735#define FSMC_SR4_IRS_Pos (0U)
    -
    7736#define FSMC_SR4_IRS_Msk (0x1UL << FSMC_SR4_IRS_Pos)
    -
    7737#define FSMC_SR4_IRS FSMC_SR4_IRS_Msk
    -
    7738#define FSMC_SR4_ILS_Pos (1U)
    -
    7739#define FSMC_SR4_ILS_Msk (0x1UL << FSMC_SR4_ILS_Pos)
    -
    7740#define FSMC_SR4_ILS FSMC_SR4_ILS_Msk
    -
    7741#define FSMC_SR4_IFS_Pos (2U)
    -
    7742#define FSMC_SR4_IFS_Msk (0x1UL << FSMC_SR4_IFS_Pos)
    -
    7743#define FSMC_SR4_IFS FSMC_SR4_IFS_Msk
    -
    7744#define FSMC_SR4_IREN_Pos (3U)
    -
    7745#define FSMC_SR4_IREN_Msk (0x1UL << FSMC_SR4_IREN_Pos)
    -
    7746#define FSMC_SR4_IREN FSMC_SR4_IREN_Msk
    -
    7747#define FSMC_SR4_ILEN_Pos (4U)
    -
    7748#define FSMC_SR4_ILEN_Msk (0x1UL << FSMC_SR4_ILEN_Pos)
    -
    7749#define FSMC_SR4_ILEN FSMC_SR4_ILEN_Msk
    -
    7750#define FSMC_SR4_IFEN_Pos (5U)
    -
    7751#define FSMC_SR4_IFEN_Msk (0x1UL << FSMC_SR4_IFEN_Pos)
    -
    7752#define FSMC_SR4_IFEN FSMC_SR4_IFEN_Msk
    -
    7753#define FSMC_SR4_FEMPT_Pos (6U)
    -
    7754#define FSMC_SR4_FEMPT_Msk (0x1UL << FSMC_SR4_FEMPT_Pos)
    -
    7755#define FSMC_SR4_FEMPT FSMC_SR4_FEMPT_Msk
    -
    7757/****************** Bit definition for FSMC_PMEM2 register ******************/
    -
    7758#define FSMC_PMEM2_MEMSET2_Pos (0U)
    -
    7759#define FSMC_PMEM2_MEMSET2_Msk (0xFFUL << FSMC_PMEM2_MEMSET2_Pos)
    -
    7760#define FSMC_PMEM2_MEMSET2 FSMC_PMEM2_MEMSET2_Msk
    -
    7761#define FSMC_PMEM2_MEMSET2_0 (0x01UL << FSMC_PMEM2_MEMSET2_Pos)
    -
    7762#define FSMC_PMEM2_MEMSET2_1 (0x02UL << FSMC_PMEM2_MEMSET2_Pos)
    -
    7763#define FSMC_PMEM2_MEMSET2_2 (0x04UL << FSMC_PMEM2_MEMSET2_Pos)
    -
    7764#define FSMC_PMEM2_MEMSET2_3 (0x08UL << FSMC_PMEM2_MEMSET2_Pos)
    -
    7765#define FSMC_PMEM2_MEMSET2_4 (0x10UL << FSMC_PMEM2_MEMSET2_Pos)
    -
    7766#define FSMC_PMEM2_MEMSET2_5 (0x20UL << FSMC_PMEM2_MEMSET2_Pos)
    -
    7767#define FSMC_PMEM2_MEMSET2_6 (0x40UL << FSMC_PMEM2_MEMSET2_Pos)
    -
    7768#define FSMC_PMEM2_MEMSET2_7 (0x80UL << FSMC_PMEM2_MEMSET2_Pos)
    -
    7770#define FSMC_PMEM2_MEMWAIT2_Pos (8U)
    -
    7771#define FSMC_PMEM2_MEMWAIT2_Msk (0xFFUL << FSMC_PMEM2_MEMWAIT2_Pos)
    -
    7772#define FSMC_PMEM2_MEMWAIT2 FSMC_PMEM2_MEMWAIT2_Msk
    -
    7773#define FSMC_PMEM2_MEMWAIT2_0 (0x01UL << FSMC_PMEM2_MEMWAIT2_Pos)
    -
    7774#define FSMC_PMEM2_MEMWAIT2_1 (0x02UL << FSMC_PMEM2_MEMWAIT2_Pos)
    -
    7775#define FSMC_PMEM2_MEMWAIT2_2 (0x04UL << FSMC_PMEM2_MEMWAIT2_Pos)
    -
    7776#define FSMC_PMEM2_MEMWAIT2_3 (0x08UL << FSMC_PMEM2_MEMWAIT2_Pos)
    -
    7777#define FSMC_PMEM2_MEMWAIT2_4 (0x10UL << FSMC_PMEM2_MEMWAIT2_Pos)
    -
    7778#define FSMC_PMEM2_MEMWAIT2_5 (0x20UL << FSMC_PMEM2_MEMWAIT2_Pos)
    -
    7779#define FSMC_PMEM2_MEMWAIT2_6 (0x40UL << FSMC_PMEM2_MEMWAIT2_Pos)
    -
    7780#define FSMC_PMEM2_MEMWAIT2_7 (0x80UL << FSMC_PMEM2_MEMWAIT2_Pos)
    -
    7782#define FSMC_PMEM2_MEMHOLD2_Pos (16U)
    -
    7783#define FSMC_PMEM2_MEMHOLD2_Msk (0xFFUL << FSMC_PMEM2_MEMHOLD2_Pos)
    -
    7784#define FSMC_PMEM2_MEMHOLD2 FSMC_PMEM2_MEMHOLD2_Msk
    -
    7785#define FSMC_PMEM2_MEMHOLD2_0 (0x01UL << FSMC_PMEM2_MEMHOLD2_Pos)
    -
    7786#define FSMC_PMEM2_MEMHOLD2_1 (0x02UL << FSMC_PMEM2_MEMHOLD2_Pos)
    -
    7787#define FSMC_PMEM2_MEMHOLD2_2 (0x04UL << FSMC_PMEM2_MEMHOLD2_Pos)
    -
    7788#define FSMC_PMEM2_MEMHOLD2_3 (0x08UL << FSMC_PMEM2_MEMHOLD2_Pos)
    -
    7789#define FSMC_PMEM2_MEMHOLD2_4 (0x10UL << FSMC_PMEM2_MEMHOLD2_Pos)
    -
    7790#define FSMC_PMEM2_MEMHOLD2_5 (0x20UL << FSMC_PMEM2_MEMHOLD2_Pos)
    -
    7791#define FSMC_PMEM2_MEMHOLD2_6 (0x40UL << FSMC_PMEM2_MEMHOLD2_Pos)
    -
    7792#define FSMC_PMEM2_MEMHOLD2_7 (0x80UL << FSMC_PMEM2_MEMHOLD2_Pos)
    -
    7794#define FSMC_PMEM2_MEMHIZ2_Pos (24U)
    -
    7795#define FSMC_PMEM2_MEMHIZ2_Msk (0xFFUL << FSMC_PMEM2_MEMHIZ2_Pos)
    -
    7796#define FSMC_PMEM2_MEMHIZ2 FSMC_PMEM2_MEMHIZ2_Msk
    -
    7797#define FSMC_PMEM2_MEMHIZ2_0 (0x01UL << FSMC_PMEM2_MEMHIZ2_Pos)
    -
    7798#define FSMC_PMEM2_MEMHIZ2_1 (0x02UL << FSMC_PMEM2_MEMHIZ2_Pos)
    -
    7799#define FSMC_PMEM2_MEMHIZ2_2 (0x04UL << FSMC_PMEM2_MEMHIZ2_Pos)
    -
    7800#define FSMC_PMEM2_MEMHIZ2_3 (0x08UL << FSMC_PMEM2_MEMHIZ2_Pos)
    -
    7801#define FSMC_PMEM2_MEMHIZ2_4 (0x10UL << FSMC_PMEM2_MEMHIZ2_Pos)
    -
    7802#define FSMC_PMEM2_MEMHIZ2_5 (0x20UL << FSMC_PMEM2_MEMHIZ2_Pos)
    -
    7803#define FSMC_PMEM2_MEMHIZ2_6 (0x40UL << FSMC_PMEM2_MEMHIZ2_Pos)
    -
    7804#define FSMC_PMEM2_MEMHIZ2_7 (0x80UL << FSMC_PMEM2_MEMHIZ2_Pos)
    -
    7806/****************** Bit definition for FSMC_PMEM3 register ******************/
    -
    7807#define FSMC_PMEM3_MEMSET3_Pos (0U)
    -
    7808#define FSMC_PMEM3_MEMSET3_Msk (0xFFUL << FSMC_PMEM3_MEMSET3_Pos)
    -
    7809#define FSMC_PMEM3_MEMSET3 FSMC_PMEM3_MEMSET3_Msk
    -
    7810#define FSMC_PMEM3_MEMSET3_0 (0x01UL << FSMC_PMEM3_MEMSET3_Pos)
    -
    7811#define FSMC_PMEM3_MEMSET3_1 (0x02UL << FSMC_PMEM3_MEMSET3_Pos)
    -
    7812#define FSMC_PMEM3_MEMSET3_2 (0x04UL << FSMC_PMEM3_MEMSET3_Pos)
    -
    7813#define FSMC_PMEM3_MEMSET3_3 (0x08UL << FSMC_PMEM3_MEMSET3_Pos)
    -
    7814#define FSMC_PMEM3_MEMSET3_4 (0x10UL << FSMC_PMEM3_MEMSET3_Pos)
    -
    7815#define FSMC_PMEM3_MEMSET3_5 (0x20UL << FSMC_PMEM3_MEMSET3_Pos)
    -
    7816#define FSMC_PMEM3_MEMSET3_6 (0x40UL << FSMC_PMEM3_MEMSET3_Pos)
    -
    7817#define FSMC_PMEM3_MEMSET3_7 (0x80UL << FSMC_PMEM3_MEMSET3_Pos)
    -
    7819#define FSMC_PMEM3_MEMWAIT3_Pos (8U)
    -
    7820#define FSMC_PMEM3_MEMWAIT3_Msk (0xFFUL << FSMC_PMEM3_MEMWAIT3_Pos)
    -
    7821#define FSMC_PMEM3_MEMWAIT3 FSMC_PMEM3_MEMWAIT3_Msk
    -
    7822#define FSMC_PMEM3_MEMWAIT3_0 (0x01UL << FSMC_PMEM3_MEMWAIT3_Pos)
    -
    7823#define FSMC_PMEM3_MEMWAIT3_1 (0x02UL << FSMC_PMEM3_MEMWAIT3_Pos)
    -
    7824#define FSMC_PMEM3_MEMWAIT3_2 (0x04UL << FSMC_PMEM3_MEMWAIT3_Pos)
    -
    7825#define FSMC_PMEM3_MEMWAIT3_3 (0x08UL << FSMC_PMEM3_MEMWAIT3_Pos)
    -
    7826#define FSMC_PMEM3_MEMWAIT3_4 (0x10UL << FSMC_PMEM3_MEMWAIT3_Pos)
    -
    7827#define FSMC_PMEM3_MEMWAIT3_5 (0x20UL << FSMC_PMEM3_MEMWAIT3_Pos)
    -
    7828#define FSMC_PMEM3_MEMWAIT3_6 (0x40UL << FSMC_PMEM3_MEMWAIT3_Pos)
    -
    7829#define FSMC_PMEM3_MEMWAIT3_7 (0x80UL << FSMC_PMEM3_MEMWAIT3_Pos)
    -
    7831#define FSMC_PMEM3_MEMHOLD3_Pos (16U)
    -
    7832#define FSMC_PMEM3_MEMHOLD3_Msk (0xFFUL << FSMC_PMEM3_MEMHOLD3_Pos)
    -
    7833#define FSMC_PMEM3_MEMHOLD3 FSMC_PMEM3_MEMHOLD3_Msk
    -
    7834#define FSMC_PMEM3_MEMHOLD3_0 (0x01UL << FSMC_PMEM3_MEMHOLD3_Pos)
    -
    7835#define FSMC_PMEM3_MEMHOLD3_1 (0x02UL << FSMC_PMEM3_MEMHOLD3_Pos)
    -
    7836#define FSMC_PMEM3_MEMHOLD3_2 (0x04UL << FSMC_PMEM3_MEMHOLD3_Pos)
    -
    7837#define FSMC_PMEM3_MEMHOLD3_3 (0x08UL << FSMC_PMEM3_MEMHOLD3_Pos)
    -
    7838#define FSMC_PMEM3_MEMHOLD3_4 (0x10UL << FSMC_PMEM3_MEMHOLD3_Pos)
    -
    7839#define FSMC_PMEM3_MEMHOLD3_5 (0x20UL << FSMC_PMEM3_MEMHOLD3_Pos)
    -
    7840#define FSMC_PMEM3_MEMHOLD3_6 (0x40UL << FSMC_PMEM3_MEMHOLD3_Pos)
    -
    7841#define FSMC_PMEM3_MEMHOLD3_7 (0x80UL << FSMC_PMEM3_MEMHOLD3_Pos)
    -
    7843#define FSMC_PMEM3_MEMHIZ3_Pos (24U)
    -
    7844#define FSMC_PMEM3_MEMHIZ3_Msk (0xFFUL << FSMC_PMEM3_MEMHIZ3_Pos)
    -
    7845#define FSMC_PMEM3_MEMHIZ3 FSMC_PMEM3_MEMHIZ3_Msk
    -
    7846#define FSMC_PMEM3_MEMHIZ3_0 (0x01UL << FSMC_PMEM3_MEMHIZ3_Pos)
    -
    7847#define FSMC_PMEM3_MEMHIZ3_1 (0x02UL << FSMC_PMEM3_MEMHIZ3_Pos)
    -
    7848#define FSMC_PMEM3_MEMHIZ3_2 (0x04UL << FSMC_PMEM3_MEMHIZ3_Pos)
    -
    7849#define FSMC_PMEM3_MEMHIZ3_3 (0x08UL << FSMC_PMEM3_MEMHIZ3_Pos)
    -
    7850#define FSMC_PMEM3_MEMHIZ3_4 (0x10UL << FSMC_PMEM3_MEMHIZ3_Pos)
    -
    7851#define FSMC_PMEM3_MEMHIZ3_5 (0x20UL << FSMC_PMEM3_MEMHIZ3_Pos)
    -
    7852#define FSMC_PMEM3_MEMHIZ3_6 (0x40UL << FSMC_PMEM3_MEMHIZ3_Pos)
    -
    7853#define FSMC_PMEM3_MEMHIZ3_7 (0x80UL << FSMC_PMEM3_MEMHIZ3_Pos)
    -
    7855/****************** Bit definition for FSMC_PMEM4 register ******************/
    -
    7856#define FSMC_PMEM4_MEMSET4_Pos (0U)
    -
    7857#define FSMC_PMEM4_MEMSET4_Msk (0xFFUL << FSMC_PMEM4_MEMSET4_Pos)
    -
    7858#define FSMC_PMEM4_MEMSET4 FSMC_PMEM4_MEMSET4_Msk
    -
    7859#define FSMC_PMEM4_MEMSET4_0 (0x01UL << FSMC_PMEM4_MEMSET4_Pos)
    -
    7860#define FSMC_PMEM4_MEMSET4_1 (0x02UL << FSMC_PMEM4_MEMSET4_Pos)
    -
    7861#define FSMC_PMEM4_MEMSET4_2 (0x04UL << FSMC_PMEM4_MEMSET4_Pos)
    -
    7862#define FSMC_PMEM4_MEMSET4_3 (0x08UL << FSMC_PMEM4_MEMSET4_Pos)
    -
    7863#define FSMC_PMEM4_MEMSET4_4 (0x10UL << FSMC_PMEM4_MEMSET4_Pos)
    -
    7864#define FSMC_PMEM4_MEMSET4_5 (0x20UL << FSMC_PMEM4_MEMSET4_Pos)
    -
    7865#define FSMC_PMEM4_MEMSET4_6 (0x40UL << FSMC_PMEM4_MEMSET4_Pos)
    -
    7866#define FSMC_PMEM4_MEMSET4_7 (0x80UL << FSMC_PMEM4_MEMSET4_Pos)
    -
    7868#define FSMC_PMEM4_MEMWAIT4_Pos (8U)
    -
    7869#define FSMC_PMEM4_MEMWAIT4_Msk (0xFFUL << FSMC_PMEM4_MEMWAIT4_Pos)
    -
    7870#define FSMC_PMEM4_MEMWAIT4 FSMC_PMEM4_MEMWAIT4_Msk
    -
    7871#define FSMC_PMEM4_MEMWAIT4_0 (0x01UL << FSMC_PMEM4_MEMWAIT4_Pos)
    -
    7872#define FSMC_PMEM4_MEMWAIT4_1 (0x02UL << FSMC_PMEM4_MEMWAIT4_Pos)
    -
    7873#define FSMC_PMEM4_MEMWAIT4_2 (0x04UL << FSMC_PMEM4_MEMWAIT4_Pos)
    -
    7874#define FSMC_PMEM4_MEMWAIT4_3 (0x08UL << FSMC_PMEM4_MEMWAIT4_Pos)
    -
    7875#define FSMC_PMEM4_MEMWAIT4_4 (0x10UL << FSMC_PMEM4_MEMWAIT4_Pos)
    -
    7876#define FSMC_PMEM4_MEMWAIT4_5 (0x20UL << FSMC_PMEM4_MEMWAIT4_Pos)
    -
    7877#define FSMC_PMEM4_MEMWAIT4_6 (0x40UL << FSMC_PMEM4_MEMWAIT4_Pos)
    -
    7878#define FSMC_PMEM4_MEMWAIT4_7 (0x80UL << FSMC_PMEM4_MEMWAIT4_Pos)
    -
    7880#define FSMC_PMEM4_MEMHOLD4_Pos (16U)
    -
    7881#define FSMC_PMEM4_MEMHOLD4_Msk (0xFFUL << FSMC_PMEM4_MEMHOLD4_Pos)
    -
    7882#define FSMC_PMEM4_MEMHOLD4 FSMC_PMEM4_MEMHOLD4_Msk
    -
    7883#define FSMC_PMEM4_MEMHOLD4_0 (0x01UL << FSMC_PMEM4_MEMHOLD4_Pos)
    -
    7884#define FSMC_PMEM4_MEMHOLD4_1 (0x02UL << FSMC_PMEM4_MEMHOLD4_Pos)
    -
    7885#define FSMC_PMEM4_MEMHOLD4_2 (0x04UL << FSMC_PMEM4_MEMHOLD4_Pos)
    -
    7886#define FSMC_PMEM4_MEMHOLD4_3 (0x08UL << FSMC_PMEM4_MEMHOLD4_Pos)
    -
    7887#define FSMC_PMEM4_MEMHOLD4_4 (0x10UL << FSMC_PMEM4_MEMHOLD4_Pos)
    -
    7888#define FSMC_PMEM4_MEMHOLD4_5 (0x20UL << FSMC_PMEM4_MEMHOLD4_Pos)
    -
    7889#define FSMC_PMEM4_MEMHOLD4_6 (0x40UL << FSMC_PMEM4_MEMHOLD4_Pos)
    -
    7890#define FSMC_PMEM4_MEMHOLD4_7 (0x80UL << FSMC_PMEM4_MEMHOLD4_Pos)
    -
    7892#define FSMC_PMEM4_MEMHIZ4_Pos (24U)
    -
    7893#define FSMC_PMEM4_MEMHIZ4_Msk (0xFFUL << FSMC_PMEM4_MEMHIZ4_Pos)
    -
    7894#define FSMC_PMEM4_MEMHIZ4 FSMC_PMEM4_MEMHIZ4_Msk
    -
    7895#define FSMC_PMEM4_MEMHIZ4_0 (0x01UL << FSMC_PMEM4_MEMHIZ4_Pos)
    -
    7896#define FSMC_PMEM4_MEMHIZ4_1 (0x02UL << FSMC_PMEM4_MEMHIZ4_Pos)
    -
    7897#define FSMC_PMEM4_MEMHIZ4_2 (0x04UL << FSMC_PMEM4_MEMHIZ4_Pos)
    -
    7898#define FSMC_PMEM4_MEMHIZ4_3 (0x08UL << FSMC_PMEM4_MEMHIZ4_Pos)
    -
    7899#define FSMC_PMEM4_MEMHIZ4_4 (0x10UL << FSMC_PMEM4_MEMHIZ4_Pos)
    -
    7900#define FSMC_PMEM4_MEMHIZ4_5 (0x20UL << FSMC_PMEM4_MEMHIZ4_Pos)
    -
    7901#define FSMC_PMEM4_MEMHIZ4_6 (0x40UL << FSMC_PMEM4_MEMHIZ4_Pos)
    -
    7902#define FSMC_PMEM4_MEMHIZ4_7 (0x80UL << FSMC_PMEM4_MEMHIZ4_Pos)
    -
    7904/****************** Bit definition for FSMC_PATT2 register ******************/
    -
    7905#define FSMC_PATT2_ATTSET2_Pos (0U)
    -
    7906#define FSMC_PATT2_ATTSET2_Msk (0xFFUL << FSMC_PATT2_ATTSET2_Pos)
    -
    7907#define FSMC_PATT2_ATTSET2 FSMC_PATT2_ATTSET2_Msk
    -
    7908#define FSMC_PATT2_ATTSET2_0 (0x01UL << FSMC_PATT2_ATTSET2_Pos)
    -
    7909#define FSMC_PATT2_ATTSET2_1 (0x02UL << FSMC_PATT2_ATTSET2_Pos)
    -
    7910#define FSMC_PATT2_ATTSET2_2 (0x04UL << FSMC_PATT2_ATTSET2_Pos)
    -
    7911#define FSMC_PATT2_ATTSET2_3 (0x08UL << FSMC_PATT2_ATTSET2_Pos)
    -
    7912#define FSMC_PATT2_ATTSET2_4 (0x10UL << FSMC_PATT2_ATTSET2_Pos)
    -
    7913#define FSMC_PATT2_ATTSET2_5 (0x20UL << FSMC_PATT2_ATTSET2_Pos)
    -
    7914#define FSMC_PATT2_ATTSET2_6 (0x40UL << FSMC_PATT2_ATTSET2_Pos)
    -
    7915#define FSMC_PATT2_ATTSET2_7 (0x80UL << FSMC_PATT2_ATTSET2_Pos)
    -
    7917#define FSMC_PATT2_ATTWAIT2_Pos (8U)
    -
    7918#define FSMC_PATT2_ATTWAIT2_Msk (0xFFUL << FSMC_PATT2_ATTWAIT2_Pos)
    -
    7919#define FSMC_PATT2_ATTWAIT2 FSMC_PATT2_ATTWAIT2_Msk
    -
    7920#define FSMC_PATT2_ATTWAIT2_0 (0x01UL << FSMC_PATT2_ATTWAIT2_Pos)
    -
    7921#define FSMC_PATT2_ATTWAIT2_1 (0x02UL << FSMC_PATT2_ATTWAIT2_Pos)
    -
    7922#define FSMC_PATT2_ATTWAIT2_2 (0x04UL << FSMC_PATT2_ATTWAIT2_Pos)
    -
    7923#define FSMC_PATT2_ATTWAIT2_3 (0x08UL << FSMC_PATT2_ATTWAIT2_Pos)
    -
    7924#define FSMC_PATT2_ATTWAIT2_4 (0x10UL << FSMC_PATT2_ATTWAIT2_Pos)
    -
    7925#define FSMC_PATT2_ATTWAIT2_5 (0x20UL << FSMC_PATT2_ATTWAIT2_Pos)
    -
    7926#define FSMC_PATT2_ATTWAIT2_6 (0x40UL << FSMC_PATT2_ATTWAIT2_Pos)
    -
    7927#define FSMC_PATT2_ATTWAIT2_7 (0x80UL << FSMC_PATT2_ATTWAIT2_Pos)
    -
    7929#define FSMC_PATT2_ATTHOLD2_Pos (16U)
    -
    7930#define FSMC_PATT2_ATTHOLD2_Msk (0xFFUL << FSMC_PATT2_ATTHOLD2_Pos)
    -
    7931#define FSMC_PATT2_ATTHOLD2 FSMC_PATT2_ATTHOLD2_Msk
    -
    7932#define FSMC_PATT2_ATTHOLD2_0 (0x01UL << FSMC_PATT2_ATTHOLD2_Pos)
    -
    7933#define FSMC_PATT2_ATTHOLD2_1 (0x02UL << FSMC_PATT2_ATTHOLD2_Pos)
    -
    7934#define FSMC_PATT2_ATTHOLD2_2 (0x04UL << FSMC_PATT2_ATTHOLD2_Pos)
    -
    7935#define FSMC_PATT2_ATTHOLD2_3 (0x08UL << FSMC_PATT2_ATTHOLD2_Pos)
    -
    7936#define FSMC_PATT2_ATTHOLD2_4 (0x10UL << FSMC_PATT2_ATTHOLD2_Pos)
    -
    7937#define FSMC_PATT2_ATTHOLD2_5 (0x20UL << FSMC_PATT2_ATTHOLD2_Pos)
    -
    7938#define FSMC_PATT2_ATTHOLD2_6 (0x40UL << FSMC_PATT2_ATTHOLD2_Pos)
    -
    7939#define FSMC_PATT2_ATTHOLD2_7 (0x80UL << FSMC_PATT2_ATTHOLD2_Pos)
    -
    7941#define FSMC_PATT2_ATTHIZ2_Pos (24U)
    -
    7942#define FSMC_PATT2_ATTHIZ2_Msk (0xFFUL << FSMC_PATT2_ATTHIZ2_Pos)
    -
    7943#define FSMC_PATT2_ATTHIZ2 FSMC_PATT2_ATTHIZ2_Msk
    -
    7944#define FSMC_PATT2_ATTHIZ2_0 (0x01UL << FSMC_PATT2_ATTHIZ2_Pos)
    -
    7945#define FSMC_PATT2_ATTHIZ2_1 (0x02UL << FSMC_PATT2_ATTHIZ2_Pos)
    -
    7946#define FSMC_PATT2_ATTHIZ2_2 (0x04UL << FSMC_PATT2_ATTHIZ2_Pos)
    -
    7947#define FSMC_PATT2_ATTHIZ2_3 (0x08UL << FSMC_PATT2_ATTHIZ2_Pos)
    -
    7948#define FSMC_PATT2_ATTHIZ2_4 (0x10UL << FSMC_PATT2_ATTHIZ2_Pos)
    -
    7949#define FSMC_PATT2_ATTHIZ2_5 (0x20UL << FSMC_PATT2_ATTHIZ2_Pos)
    -
    7950#define FSMC_PATT2_ATTHIZ2_6 (0x40UL << FSMC_PATT2_ATTHIZ2_Pos)
    -
    7951#define FSMC_PATT2_ATTHIZ2_7 (0x80UL << FSMC_PATT2_ATTHIZ2_Pos)
    -
    7953/****************** Bit definition for FSMC_PATT3 register ******************/
    -
    7954#define FSMC_PATT3_ATTSET3_Pos (0U)
    -
    7955#define FSMC_PATT3_ATTSET3_Msk (0xFFUL << FSMC_PATT3_ATTSET3_Pos)
    -
    7956#define FSMC_PATT3_ATTSET3 FSMC_PATT3_ATTSET3_Msk
    -
    7957#define FSMC_PATT3_ATTSET3_0 (0x01UL << FSMC_PATT3_ATTSET3_Pos)
    -
    7958#define FSMC_PATT3_ATTSET3_1 (0x02UL << FSMC_PATT3_ATTSET3_Pos)
    -
    7959#define FSMC_PATT3_ATTSET3_2 (0x04UL << FSMC_PATT3_ATTSET3_Pos)
    -
    7960#define FSMC_PATT3_ATTSET3_3 (0x08UL << FSMC_PATT3_ATTSET3_Pos)
    -
    7961#define FSMC_PATT3_ATTSET3_4 (0x10UL << FSMC_PATT3_ATTSET3_Pos)
    -
    7962#define FSMC_PATT3_ATTSET3_5 (0x20UL << FSMC_PATT3_ATTSET3_Pos)
    -
    7963#define FSMC_PATT3_ATTSET3_6 (0x40UL << FSMC_PATT3_ATTSET3_Pos)
    -
    7964#define FSMC_PATT3_ATTSET3_7 (0x80UL << FSMC_PATT3_ATTSET3_Pos)
    -
    7966#define FSMC_PATT3_ATTWAIT3_Pos (8U)
    -
    7967#define FSMC_PATT3_ATTWAIT3_Msk (0xFFUL << FSMC_PATT3_ATTWAIT3_Pos)
    -
    7968#define FSMC_PATT3_ATTWAIT3 FSMC_PATT3_ATTWAIT3_Msk
    -
    7969#define FSMC_PATT3_ATTWAIT3_0 (0x01UL << FSMC_PATT3_ATTWAIT3_Pos)
    -
    7970#define FSMC_PATT3_ATTWAIT3_1 (0x02UL << FSMC_PATT3_ATTWAIT3_Pos)
    -
    7971#define FSMC_PATT3_ATTWAIT3_2 (0x04UL << FSMC_PATT3_ATTWAIT3_Pos)
    -
    7972#define FSMC_PATT3_ATTWAIT3_3 (0x08UL << FSMC_PATT3_ATTWAIT3_Pos)
    -
    7973#define FSMC_PATT3_ATTWAIT3_4 (0x10UL << FSMC_PATT3_ATTWAIT3_Pos)
    -
    7974#define FSMC_PATT3_ATTWAIT3_5 (0x20UL << FSMC_PATT3_ATTWAIT3_Pos)
    -
    7975#define FSMC_PATT3_ATTWAIT3_6 (0x40UL << FSMC_PATT3_ATTWAIT3_Pos)
    -
    7976#define FSMC_PATT3_ATTWAIT3_7 (0x80UL << FSMC_PATT3_ATTWAIT3_Pos)
    -
    7978#define FSMC_PATT3_ATTHOLD3_Pos (16U)
    -
    7979#define FSMC_PATT3_ATTHOLD3_Msk (0xFFUL << FSMC_PATT3_ATTHOLD3_Pos)
    -
    7980#define FSMC_PATT3_ATTHOLD3 FSMC_PATT3_ATTHOLD3_Msk
    -
    7981#define FSMC_PATT3_ATTHOLD3_0 (0x01UL << FSMC_PATT3_ATTHOLD3_Pos)
    -
    7982#define FSMC_PATT3_ATTHOLD3_1 (0x02UL << FSMC_PATT3_ATTHOLD3_Pos)
    -
    7983#define FSMC_PATT3_ATTHOLD3_2 (0x04UL << FSMC_PATT3_ATTHOLD3_Pos)
    -
    7984#define FSMC_PATT3_ATTHOLD3_3 (0x08UL << FSMC_PATT3_ATTHOLD3_Pos)
    -
    7985#define FSMC_PATT3_ATTHOLD3_4 (0x10UL << FSMC_PATT3_ATTHOLD3_Pos)
    -
    7986#define FSMC_PATT3_ATTHOLD3_5 (0x20UL << FSMC_PATT3_ATTHOLD3_Pos)
    -
    7987#define FSMC_PATT3_ATTHOLD3_6 (0x40UL << FSMC_PATT3_ATTHOLD3_Pos)
    -
    7988#define FSMC_PATT3_ATTHOLD3_7 (0x80UL << FSMC_PATT3_ATTHOLD3_Pos)
    -
    7990#define FSMC_PATT3_ATTHIZ3_Pos (24U)
    -
    7991#define FSMC_PATT3_ATTHIZ3_Msk (0xFFUL << FSMC_PATT3_ATTHIZ3_Pos)
    -
    7992#define FSMC_PATT3_ATTHIZ3 FSMC_PATT3_ATTHIZ3_Msk
    -
    7993#define FSMC_PATT3_ATTHIZ3_0 (0x01UL << FSMC_PATT3_ATTHIZ3_Pos)
    -
    7994#define FSMC_PATT3_ATTHIZ3_1 (0x02UL << FSMC_PATT3_ATTHIZ3_Pos)
    -
    7995#define FSMC_PATT3_ATTHIZ3_2 (0x04UL << FSMC_PATT3_ATTHIZ3_Pos)
    -
    7996#define FSMC_PATT3_ATTHIZ3_3 (0x08UL << FSMC_PATT3_ATTHIZ3_Pos)
    -
    7997#define FSMC_PATT3_ATTHIZ3_4 (0x10UL << FSMC_PATT3_ATTHIZ3_Pos)
    -
    7998#define FSMC_PATT3_ATTHIZ3_5 (0x20UL << FSMC_PATT3_ATTHIZ3_Pos)
    -
    7999#define FSMC_PATT3_ATTHIZ3_6 (0x40UL << FSMC_PATT3_ATTHIZ3_Pos)
    -
    8000#define FSMC_PATT3_ATTHIZ3_7 (0x80UL << FSMC_PATT3_ATTHIZ3_Pos)
    -
    8002/****************** Bit definition for FSMC_PATT4 register ******************/
    -
    8003#define FSMC_PATT4_ATTSET4_Pos (0U)
    -
    8004#define FSMC_PATT4_ATTSET4_Msk (0xFFUL << FSMC_PATT4_ATTSET4_Pos)
    -
    8005#define FSMC_PATT4_ATTSET4 FSMC_PATT4_ATTSET4_Msk
    -
    8006#define FSMC_PATT4_ATTSET4_0 (0x01UL << FSMC_PATT4_ATTSET4_Pos)
    -
    8007#define FSMC_PATT4_ATTSET4_1 (0x02UL << FSMC_PATT4_ATTSET4_Pos)
    -
    8008#define FSMC_PATT4_ATTSET4_2 (0x04UL << FSMC_PATT4_ATTSET4_Pos)
    -
    8009#define FSMC_PATT4_ATTSET4_3 (0x08UL << FSMC_PATT4_ATTSET4_Pos)
    -
    8010#define FSMC_PATT4_ATTSET4_4 (0x10UL << FSMC_PATT4_ATTSET4_Pos)
    -
    8011#define FSMC_PATT4_ATTSET4_5 (0x20UL << FSMC_PATT4_ATTSET4_Pos)
    -
    8012#define FSMC_PATT4_ATTSET4_6 (0x40UL << FSMC_PATT4_ATTSET4_Pos)
    -
    8013#define FSMC_PATT4_ATTSET4_7 (0x80UL << FSMC_PATT4_ATTSET4_Pos)
    -
    8015#define FSMC_PATT4_ATTWAIT4_Pos (8U)
    -
    8016#define FSMC_PATT4_ATTWAIT4_Msk (0xFFUL << FSMC_PATT4_ATTWAIT4_Pos)
    -
    8017#define FSMC_PATT4_ATTWAIT4 FSMC_PATT4_ATTWAIT4_Msk
    -
    8018#define FSMC_PATT4_ATTWAIT4_0 (0x01UL << FSMC_PATT4_ATTWAIT4_Pos)
    -
    8019#define FSMC_PATT4_ATTWAIT4_1 (0x02UL << FSMC_PATT4_ATTWAIT4_Pos)
    -
    8020#define FSMC_PATT4_ATTWAIT4_2 (0x04UL << FSMC_PATT4_ATTWAIT4_Pos)
    -
    8021#define FSMC_PATT4_ATTWAIT4_3 (0x08UL << FSMC_PATT4_ATTWAIT4_Pos)
    -
    8022#define FSMC_PATT4_ATTWAIT4_4 (0x10UL << FSMC_PATT4_ATTWAIT4_Pos)
    -
    8023#define FSMC_PATT4_ATTWAIT4_5 (0x20UL << FSMC_PATT4_ATTWAIT4_Pos)
    -
    8024#define FSMC_PATT4_ATTWAIT4_6 (0x40UL << FSMC_PATT4_ATTWAIT4_Pos)
    -
    8025#define FSMC_PATT4_ATTWAIT4_7 (0x80UL << FSMC_PATT4_ATTWAIT4_Pos)
    -
    8027#define FSMC_PATT4_ATTHOLD4_Pos (16U)
    -
    8028#define FSMC_PATT4_ATTHOLD4_Msk (0xFFUL << FSMC_PATT4_ATTHOLD4_Pos)
    -
    8029#define FSMC_PATT4_ATTHOLD4 FSMC_PATT4_ATTHOLD4_Msk
    -
    8030#define FSMC_PATT4_ATTHOLD4_0 (0x01UL << FSMC_PATT4_ATTHOLD4_Pos)
    -
    8031#define FSMC_PATT4_ATTHOLD4_1 (0x02UL << FSMC_PATT4_ATTHOLD4_Pos)
    -
    8032#define FSMC_PATT4_ATTHOLD4_2 (0x04UL << FSMC_PATT4_ATTHOLD4_Pos)
    -
    8033#define FSMC_PATT4_ATTHOLD4_3 (0x08UL << FSMC_PATT4_ATTHOLD4_Pos)
    -
    8034#define FSMC_PATT4_ATTHOLD4_4 (0x10UL << FSMC_PATT4_ATTHOLD4_Pos)
    -
    8035#define FSMC_PATT4_ATTHOLD4_5 (0x20UL << FSMC_PATT4_ATTHOLD4_Pos)
    -
    8036#define FSMC_PATT4_ATTHOLD4_6 (0x40UL << FSMC_PATT4_ATTHOLD4_Pos)
    -
    8037#define FSMC_PATT4_ATTHOLD4_7 (0x80UL << FSMC_PATT4_ATTHOLD4_Pos)
    -
    8039#define FSMC_PATT4_ATTHIZ4_Pos (24U)
    -
    8040#define FSMC_PATT4_ATTHIZ4_Msk (0xFFUL << FSMC_PATT4_ATTHIZ4_Pos)
    -
    8041#define FSMC_PATT4_ATTHIZ4 FSMC_PATT4_ATTHIZ4_Msk
    -
    8042#define FSMC_PATT4_ATTHIZ4_0 (0x01UL << FSMC_PATT4_ATTHIZ4_Pos)
    -
    8043#define FSMC_PATT4_ATTHIZ4_1 (0x02UL << FSMC_PATT4_ATTHIZ4_Pos)
    -
    8044#define FSMC_PATT4_ATTHIZ4_2 (0x04UL << FSMC_PATT4_ATTHIZ4_Pos)
    -
    8045#define FSMC_PATT4_ATTHIZ4_3 (0x08UL << FSMC_PATT4_ATTHIZ4_Pos)
    -
    8046#define FSMC_PATT4_ATTHIZ4_4 (0x10UL << FSMC_PATT4_ATTHIZ4_Pos)
    -
    8047#define FSMC_PATT4_ATTHIZ4_5 (0x20UL << FSMC_PATT4_ATTHIZ4_Pos)
    -
    8048#define FSMC_PATT4_ATTHIZ4_6 (0x40UL << FSMC_PATT4_ATTHIZ4_Pos)
    -
    8049#define FSMC_PATT4_ATTHIZ4_7 (0x80UL << FSMC_PATT4_ATTHIZ4_Pos)
    -
    8051/****************** Bit definition for FSMC_PIO4 register *******************/
    -
    8052#define FSMC_PIO4_IOSET4_Pos (0U)
    -
    8053#define FSMC_PIO4_IOSET4_Msk (0xFFUL << FSMC_PIO4_IOSET4_Pos)
    -
    8054#define FSMC_PIO4_IOSET4 FSMC_PIO4_IOSET4_Msk
    -
    8055#define FSMC_PIO4_IOSET4_0 (0x01UL << FSMC_PIO4_IOSET4_Pos)
    -
    8056#define FSMC_PIO4_IOSET4_1 (0x02UL << FSMC_PIO4_IOSET4_Pos)
    -
    8057#define FSMC_PIO4_IOSET4_2 (0x04UL << FSMC_PIO4_IOSET4_Pos)
    -
    8058#define FSMC_PIO4_IOSET4_3 (0x08UL << FSMC_PIO4_IOSET4_Pos)
    -
    8059#define FSMC_PIO4_IOSET4_4 (0x10UL << FSMC_PIO4_IOSET4_Pos)
    -
    8060#define FSMC_PIO4_IOSET4_5 (0x20UL << FSMC_PIO4_IOSET4_Pos)
    -
    8061#define FSMC_PIO4_IOSET4_6 (0x40UL << FSMC_PIO4_IOSET4_Pos)
    -
    8062#define FSMC_PIO4_IOSET4_7 (0x80UL << FSMC_PIO4_IOSET4_Pos)
    -
    8064#define FSMC_PIO4_IOWAIT4_Pos (8U)
    -
    8065#define FSMC_PIO4_IOWAIT4_Msk (0xFFUL << FSMC_PIO4_IOWAIT4_Pos)
    -
    8066#define FSMC_PIO4_IOWAIT4 FSMC_PIO4_IOWAIT4_Msk
    -
    8067#define FSMC_PIO4_IOWAIT4_0 (0x01UL << FSMC_PIO4_IOWAIT4_Pos)
    -
    8068#define FSMC_PIO4_IOWAIT4_1 (0x02UL << FSMC_PIO4_IOWAIT4_Pos)
    -
    8069#define FSMC_PIO4_IOWAIT4_2 (0x04UL << FSMC_PIO4_IOWAIT4_Pos)
    -
    8070#define FSMC_PIO4_IOWAIT4_3 (0x08UL << FSMC_PIO4_IOWAIT4_Pos)
    -
    8071#define FSMC_PIO4_IOWAIT4_4 (0x10UL << FSMC_PIO4_IOWAIT4_Pos)
    -
    8072#define FSMC_PIO4_IOWAIT4_5 (0x20UL << FSMC_PIO4_IOWAIT4_Pos)
    -
    8073#define FSMC_PIO4_IOWAIT4_6 (0x40UL << FSMC_PIO4_IOWAIT4_Pos)
    -
    8074#define FSMC_PIO4_IOWAIT4_7 (0x80UL << FSMC_PIO4_IOWAIT4_Pos)
    -
    8076#define FSMC_PIO4_IOHOLD4_Pos (16U)
    -
    8077#define FSMC_PIO4_IOHOLD4_Msk (0xFFUL << FSMC_PIO4_IOHOLD4_Pos)
    -
    8078#define FSMC_PIO4_IOHOLD4 FSMC_PIO4_IOHOLD4_Msk
    -
    8079#define FSMC_PIO4_IOHOLD4_0 (0x01UL << FSMC_PIO4_IOHOLD4_Pos)
    -
    8080#define FSMC_PIO4_IOHOLD4_1 (0x02UL << FSMC_PIO4_IOHOLD4_Pos)
    -
    8081#define FSMC_PIO4_IOHOLD4_2 (0x04UL << FSMC_PIO4_IOHOLD4_Pos)
    -
    8082#define FSMC_PIO4_IOHOLD4_3 (0x08UL << FSMC_PIO4_IOHOLD4_Pos)
    -
    8083#define FSMC_PIO4_IOHOLD4_4 (0x10UL << FSMC_PIO4_IOHOLD4_Pos)
    -
    8084#define FSMC_PIO4_IOHOLD4_5 (0x20UL << FSMC_PIO4_IOHOLD4_Pos)
    -
    8085#define FSMC_PIO4_IOHOLD4_6 (0x40UL << FSMC_PIO4_IOHOLD4_Pos)
    -
    8086#define FSMC_PIO4_IOHOLD4_7 (0x80UL << FSMC_PIO4_IOHOLD4_Pos)
    -
    8088#define FSMC_PIO4_IOHIZ4_Pos (24U)
    -
    8089#define FSMC_PIO4_IOHIZ4_Msk (0xFFUL << FSMC_PIO4_IOHIZ4_Pos)
    -
    8090#define FSMC_PIO4_IOHIZ4 FSMC_PIO4_IOHIZ4_Msk
    -
    8091#define FSMC_PIO4_IOHIZ4_0 (0x01UL << FSMC_PIO4_IOHIZ4_Pos)
    -
    8092#define FSMC_PIO4_IOHIZ4_1 (0x02UL << FSMC_PIO4_IOHIZ4_Pos)
    -
    8093#define FSMC_PIO4_IOHIZ4_2 (0x04UL << FSMC_PIO4_IOHIZ4_Pos)
    -
    8094#define FSMC_PIO4_IOHIZ4_3 (0x08UL << FSMC_PIO4_IOHIZ4_Pos)
    -
    8095#define FSMC_PIO4_IOHIZ4_4 (0x10UL << FSMC_PIO4_IOHIZ4_Pos)
    -
    8096#define FSMC_PIO4_IOHIZ4_5 (0x20UL << FSMC_PIO4_IOHIZ4_Pos)
    -
    8097#define FSMC_PIO4_IOHIZ4_6 (0x40UL << FSMC_PIO4_IOHIZ4_Pos)
    -
    8098#define FSMC_PIO4_IOHIZ4_7 (0x80UL << FSMC_PIO4_IOHIZ4_Pos)
    -
    8100/****************** Bit definition for FSMC_ECCR2 register ******************/
    -
    8101#define FSMC_ECCR2_ECC2_Pos (0U)
    -
    8102#define FSMC_ECCR2_ECC2_Msk (0xFFFFFFFFUL << FSMC_ECCR2_ECC2_Pos)
    -
    8103#define FSMC_ECCR2_ECC2 FSMC_ECCR2_ECC2_Msk
    -
    8105/****************** Bit definition for FSMC_ECCR3 register ******************/
    -
    8106#define FSMC_ECCR3_ECC3_Pos (0U)
    -
    8107#define FSMC_ECCR3_ECC3_Msk (0xFFFFFFFFUL << FSMC_ECCR3_ECC3_Pos)
    -
    8108#define FSMC_ECCR3_ECC3 FSMC_ECCR3_ECC3_Msk
    -
    8110/******************************************************************************/
    -
    8111/* */
    -
    8112/* General Purpose I/O */
    -
    8113/* */
    -
    8114/******************************************************************************/
    -
    8115/****************** Bits definition for GPIO_MODER register *****************/
    -
    8116#define GPIO_MODER_MODER0_Pos (0U)
    -
    8117#define GPIO_MODER_MODER0_Msk (0x3UL << GPIO_MODER_MODER0_Pos)
    -
    8118#define GPIO_MODER_MODER0 GPIO_MODER_MODER0_Msk
    -
    8119#define GPIO_MODER_MODER0_0 (0x1UL << GPIO_MODER_MODER0_Pos)
    -
    8120#define GPIO_MODER_MODER0_1 (0x2UL << GPIO_MODER_MODER0_Pos)
    -
    8121#define GPIO_MODER_MODER1_Pos (2U)
    -
    8122#define GPIO_MODER_MODER1_Msk (0x3UL << GPIO_MODER_MODER1_Pos)
    -
    8123#define GPIO_MODER_MODER1 GPIO_MODER_MODER1_Msk
    -
    8124#define GPIO_MODER_MODER1_0 (0x1UL << GPIO_MODER_MODER1_Pos)
    -
    8125#define GPIO_MODER_MODER1_1 (0x2UL << GPIO_MODER_MODER1_Pos)
    -
    8126#define GPIO_MODER_MODER2_Pos (4U)
    -
    8127#define GPIO_MODER_MODER2_Msk (0x3UL << GPIO_MODER_MODER2_Pos)
    -
    8128#define GPIO_MODER_MODER2 GPIO_MODER_MODER2_Msk
    -
    8129#define GPIO_MODER_MODER2_0 (0x1UL << GPIO_MODER_MODER2_Pos)
    -
    8130#define GPIO_MODER_MODER2_1 (0x2UL << GPIO_MODER_MODER2_Pos)
    -
    8131#define GPIO_MODER_MODER3_Pos (6U)
    -
    8132#define GPIO_MODER_MODER3_Msk (0x3UL << GPIO_MODER_MODER3_Pos)
    -
    8133#define GPIO_MODER_MODER3 GPIO_MODER_MODER3_Msk
    -
    8134#define GPIO_MODER_MODER3_0 (0x1UL << GPIO_MODER_MODER3_Pos)
    -
    8135#define GPIO_MODER_MODER3_1 (0x2UL << GPIO_MODER_MODER3_Pos)
    -
    8136#define GPIO_MODER_MODER4_Pos (8U)
    -
    8137#define GPIO_MODER_MODER4_Msk (0x3UL << GPIO_MODER_MODER4_Pos)
    -
    8138#define GPIO_MODER_MODER4 GPIO_MODER_MODER4_Msk
    -
    8139#define GPIO_MODER_MODER4_0 (0x1UL << GPIO_MODER_MODER4_Pos)
    -
    8140#define GPIO_MODER_MODER4_1 (0x2UL << GPIO_MODER_MODER4_Pos)
    -
    8141#define GPIO_MODER_MODER5_Pos (10U)
    -
    8142#define GPIO_MODER_MODER5_Msk (0x3UL << GPIO_MODER_MODER5_Pos)
    -
    8143#define GPIO_MODER_MODER5 GPIO_MODER_MODER5_Msk
    -
    8144#define GPIO_MODER_MODER5_0 (0x1UL << GPIO_MODER_MODER5_Pos)
    -
    8145#define GPIO_MODER_MODER5_1 (0x2UL << GPIO_MODER_MODER5_Pos)
    -
    8146#define GPIO_MODER_MODER6_Pos (12U)
    -
    8147#define GPIO_MODER_MODER6_Msk (0x3UL << GPIO_MODER_MODER6_Pos)
    -
    8148#define GPIO_MODER_MODER6 GPIO_MODER_MODER6_Msk
    -
    8149#define GPIO_MODER_MODER6_0 (0x1UL << GPIO_MODER_MODER6_Pos)
    -
    8150#define GPIO_MODER_MODER6_1 (0x2UL << GPIO_MODER_MODER6_Pos)
    -
    8151#define GPIO_MODER_MODER7_Pos (14U)
    -
    8152#define GPIO_MODER_MODER7_Msk (0x3UL << GPIO_MODER_MODER7_Pos)
    -
    8153#define GPIO_MODER_MODER7 GPIO_MODER_MODER7_Msk
    -
    8154#define GPIO_MODER_MODER7_0 (0x1UL << GPIO_MODER_MODER7_Pos)
    -
    8155#define GPIO_MODER_MODER7_1 (0x2UL << GPIO_MODER_MODER7_Pos)
    -
    8156#define GPIO_MODER_MODER8_Pos (16U)
    -
    8157#define GPIO_MODER_MODER8_Msk (0x3UL << GPIO_MODER_MODER8_Pos)
    -
    8158#define GPIO_MODER_MODER8 GPIO_MODER_MODER8_Msk
    -
    8159#define GPIO_MODER_MODER8_0 (0x1UL << GPIO_MODER_MODER8_Pos)
    -
    8160#define GPIO_MODER_MODER8_1 (0x2UL << GPIO_MODER_MODER8_Pos)
    -
    8161#define GPIO_MODER_MODER9_Pos (18U)
    -
    8162#define GPIO_MODER_MODER9_Msk (0x3UL << GPIO_MODER_MODER9_Pos)
    -
    8163#define GPIO_MODER_MODER9 GPIO_MODER_MODER9_Msk
    -
    8164#define GPIO_MODER_MODER9_0 (0x1UL << GPIO_MODER_MODER9_Pos)
    -
    8165#define GPIO_MODER_MODER9_1 (0x2UL << GPIO_MODER_MODER9_Pos)
    -
    8166#define GPIO_MODER_MODER10_Pos (20U)
    -
    8167#define GPIO_MODER_MODER10_Msk (0x3UL << GPIO_MODER_MODER10_Pos)
    -
    8168#define GPIO_MODER_MODER10 GPIO_MODER_MODER10_Msk
    -
    8169#define GPIO_MODER_MODER10_0 (0x1UL << GPIO_MODER_MODER10_Pos)
    -
    8170#define GPIO_MODER_MODER10_1 (0x2UL << GPIO_MODER_MODER10_Pos)
    -
    8171#define GPIO_MODER_MODER11_Pos (22U)
    -
    8172#define GPIO_MODER_MODER11_Msk (0x3UL << GPIO_MODER_MODER11_Pos)
    -
    8173#define GPIO_MODER_MODER11 GPIO_MODER_MODER11_Msk
    -
    8174#define GPIO_MODER_MODER11_0 (0x1UL << GPIO_MODER_MODER11_Pos)
    -
    8175#define GPIO_MODER_MODER11_1 (0x2UL << GPIO_MODER_MODER11_Pos)
    -
    8176#define GPIO_MODER_MODER12_Pos (24U)
    -
    8177#define GPIO_MODER_MODER12_Msk (0x3UL << GPIO_MODER_MODER12_Pos)
    -
    8178#define GPIO_MODER_MODER12 GPIO_MODER_MODER12_Msk
    -
    8179#define GPIO_MODER_MODER12_0 (0x1UL << GPIO_MODER_MODER12_Pos)
    -
    8180#define GPIO_MODER_MODER12_1 (0x2UL << GPIO_MODER_MODER12_Pos)
    -
    8181#define GPIO_MODER_MODER13_Pos (26U)
    -
    8182#define GPIO_MODER_MODER13_Msk (0x3UL << GPIO_MODER_MODER13_Pos)
    -
    8183#define GPIO_MODER_MODER13 GPIO_MODER_MODER13_Msk
    -
    8184#define GPIO_MODER_MODER13_0 (0x1UL << GPIO_MODER_MODER13_Pos)
    -
    8185#define GPIO_MODER_MODER13_1 (0x2UL << GPIO_MODER_MODER13_Pos)
    -
    8186#define GPIO_MODER_MODER14_Pos (28U)
    -
    8187#define GPIO_MODER_MODER14_Msk (0x3UL << GPIO_MODER_MODER14_Pos)
    -
    8188#define GPIO_MODER_MODER14 GPIO_MODER_MODER14_Msk
    -
    8189#define GPIO_MODER_MODER14_0 (0x1UL << GPIO_MODER_MODER14_Pos)
    -
    8190#define GPIO_MODER_MODER14_1 (0x2UL << GPIO_MODER_MODER14_Pos)
    -
    8191#define GPIO_MODER_MODER15_Pos (30U)
    -
    8192#define GPIO_MODER_MODER15_Msk (0x3UL << GPIO_MODER_MODER15_Pos)
    -
    8193#define GPIO_MODER_MODER15 GPIO_MODER_MODER15_Msk
    -
    8194#define GPIO_MODER_MODER15_0 (0x1UL << GPIO_MODER_MODER15_Pos)
    -
    8195#define GPIO_MODER_MODER15_1 (0x2UL << GPIO_MODER_MODER15_Pos)
    -
    8197/* Legacy defines */
    -
    8198#define GPIO_MODER_MODE0_Pos GPIO_MODER_MODER0_Pos
    -
    8199#define GPIO_MODER_MODE0_Msk GPIO_MODER_MODER0_Msk
    -
    8200#define GPIO_MODER_MODE0 GPIO_MODER_MODER0
    -
    8201#define GPIO_MODER_MODE0_0 GPIO_MODER_MODER0_0
    -
    8202#define GPIO_MODER_MODE0_1 GPIO_MODER_MODER0_1
    -
    8203#define GPIO_MODER_MODE1_Pos GPIO_MODER_MODER1_Pos
    -
    8204#define GPIO_MODER_MODE1_Msk GPIO_MODER_MODER1_Msk
    -
    8205#define GPIO_MODER_MODE1 GPIO_MODER_MODER1
    -
    8206#define GPIO_MODER_MODE1_0 GPIO_MODER_MODER1_0
    -
    8207#define GPIO_MODER_MODE1_1 GPIO_MODER_MODER1_1
    -
    8208#define GPIO_MODER_MODE2_Pos GPIO_MODER_MODER2_Pos
    -
    8209#define GPIO_MODER_MODE2_Msk GPIO_MODER_MODER2_Msk
    -
    8210#define GPIO_MODER_MODE2 GPIO_MODER_MODER2
    -
    8211#define GPIO_MODER_MODE2_0 GPIO_MODER_MODER2_0
    -
    8212#define GPIO_MODER_MODE2_1 GPIO_MODER_MODER2_1
    -
    8213#define GPIO_MODER_MODE3_Pos GPIO_MODER_MODER3_Pos
    -
    8214#define GPIO_MODER_MODE3_Msk GPIO_MODER_MODER3_Msk
    -
    8215#define GPIO_MODER_MODE3 GPIO_MODER_MODER3
    -
    8216#define GPIO_MODER_MODE3_0 GPIO_MODER_MODER3_0
    -
    8217#define GPIO_MODER_MODE3_1 GPIO_MODER_MODER3_1
    -
    8218#define GPIO_MODER_MODE4_Pos GPIO_MODER_MODER4_Pos
    -
    8219#define GPIO_MODER_MODE4_Msk GPIO_MODER_MODER4_Msk
    -
    8220#define GPIO_MODER_MODE4 GPIO_MODER_MODER4
    -
    8221#define GPIO_MODER_MODE4_0 GPIO_MODER_MODER4_0
    -
    8222#define GPIO_MODER_MODE4_1 GPIO_MODER_MODER4_1
    -
    8223#define GPIO_MODER_MODE5_Pos GPIO_MODER_MODER5_Pos
    -
    8224#define GPIO_MODER_MODE5_Msk GPIO_MODER_MODER5_Msk
    -
    8225#define GPIO_MODER_MODE5 GPIO_MODER_MODER5
    -
    8226#define GPIO_MODER_MODE5_0 GPIO_MODER_MODER5_0
    -
    8227#define GPIO_MODER_MODE5_1 GPIO_MODER_MODER5_1
    -
    8228#define GPIO_MODER_MODE6_Pos GPIO_MODER_MODER6_Pos
    -
    8229#define GPIO_MODER_MODE6_Msk GPIO_MODER_MODER6_Msk
    -
    8230#define GPIO_MODER_MODE6 GPIO_MODER_MODER6
    -
    8231#define GPIO_MODER_MODE6_0 GPIO_MODER_MODER6_0
    -
    8232#define GPIO_MODER_MODE6_1 GPIO_MODER_MODER6_1
    -
    8233#define GPIO_MODER_MODE7_Pos GPIO_MODER_MODER7_Pos
    -
    8234#define GPIO_MODER_MODE7_Msk GPIO_MODER_MODER7_Msk
    -
    8235#define GPIO_MODER_MODE7 GPIO_MODER_MODER7
    -
    8236#define GPIO_MODER_MODE7_0 GPIO_MODER_MODER7_0
    -
    8237#define GPIO_MODER_MODE7_1 GPIO_MODER_MODER7_1
    -
    8238#define GPIO_MODER_MODE8_Pos GPIO_MODER_MODER8_Pos
    -
    8239#define GPIO_MODER_MODE8_Msk GPIO_MODER_MODER8_Msk
    -
    8240#define GPIO_MODER_MODE8 GPIO_MODER_MODER8
    -
    8241#define GPIO_MODER_MODE8_0 GPIO_MODER_MODER8_0
    -
    8242#define GPIO_MODER_MODE8_1 GPIO_MODER_MODER8_1
    -
    8243#define GPIO_MODER_MODE9_Pos GPIO_MODER_MODER9_Pos
    -
    8244#define GPIO_MODER_MODE9_Msk GPIO_MODER_MODER9_Msk
    -
    8245#define GPIO_MODER_MODE9 GPIO_MODER_MODER9
    -
    8246#define GPIO_MODER_MODE9_0 GPIO_MODER_MODER9_0
    -
    8247#define GPIO_MODER_MODE9_1 GPIO_MODER_MODER9_1
    -
    8248#define GPIO_MODER_MODE10_Pos GPIO_MODER_MODER10_Pos
    -
    8249#define GPIO_MODER_MODE10_Msk GPIO_MODER_MODER10_Msk
    -
    8250#define GPIO_MODER_MODE10 GPIO_MODER_MODER10
    -
    8251#define GPIO_MODER_MODE10_0 GPIO_MODER_MODER10_0
    -
    8252#define GPIO_MODER_MODE10_1 GPIO_MODER_MODER10_1
    -
    8253#define GPIO_MODER_MODE11_Pos GPIO_MODER_MODER11_Pos
    -
    8254#define GPIO_MODER_MODE11_Msk GPIO_MODER_MODER11_Msk
    -
    8255#define GPIO_MODER_MODE11 GPIO_MODER_MODER11
    -
    8256#define GPIO_MODER_MODE11_0 GPIO_MODER_MODER11_0
    -
    8257#define GPIO_MODER_MODE11_1 GPIO_MODER_MODER11_1
    -
    8258#define GPIO_MODER_MODE12_Pos GPIO_MODER_MODER12_Pos
    -
    8259#define GPIO_MODER_MODE12_Msk GPIO_MODER_MODER12_Msk
    -
    8260#define GPIO_MODER_MODE12 GPIO_MODER_MODER12
    -
    8261#define GPIO_MODER_MODE12_0 GPIO_MODER_MODER12_0
    -
    8262#define GPIO_MODER_MODE12_1 GPIO_MODER_MODER12_1
    -
    8263#define GPIO_MODER_MODE13_Pos GPIO_MODER_MODER13_Pos
    -
    8264#define GPIO_MODER_MODE13_Msk GPIO_MODER_MODER13_Msk
    -
    8265#define GPIO_MODER_MODE13 GPIO_MODER_MODER13
    -
    8266#define GPIO_MODER_MODE13_0 GPIO_MODER_MODER13_0
    -
    8267#define GPIO_MODER_MODE13_1 GPIO_MODER_MODER13_1
    -
    8268#define GPIO_MODER_MODE14_Pos GPIO_MODER_MODER14_Pos
    -
    8269#define GPIO_MODER_MODE14_Msk GPIO_MODER_MODER14_Msk
    -
    8270#define GPIO_MODER_MODE14 GPIO_MODER_MODER14
    -
    8271#define GPIO_MODER_MODE14_0 GPIO_MODER_MODER14_0
    -
    8272#define GPIO_MODER_MODE14_1 GPIO_MODER_MODER14_1
    -
    8273#define GPIO_MODER_MODE15_Pos GPIO_MODER_MODER15_Pos
    -
    8274#define GPIO_MODER_MODE15_Msk GPIO_MODER_MODER15_Msk
    -
    8275#define GPIO_MODER_MODE15 GPIO_MODER_MODER15
    -
    8276#define GPIO_MODER_MODE15_0 GPIO_MODER_MODER15_0
    -
    8277#define GPIO_MODER_MODE15_1 GPIO_MODER_MODER15_1
    -
    8278
    -
    8279/****************** Bits definition for GPIO_OTYPER register ****************/
    -
    8280#define GPIO_OTYPER_OT0_Pos (0U)
    -
    8281#define GPIO_OTYPER_OT0_Msk (0x1UL << GPIO_OTYPER_OT0_Pos)
    -
    8282#define GPIO_OTYPER_OT0 GPIO_OTYPER_OT0_Msk
    -
    8283#define GPIO_OTYPER_OT1_Pos (1U)
    -
    8284#define GPIO_OTYPER_OT1_Msk (0x1UL << GPIO_OTYPER_OT1_Pos)
    -
    8285#define GPIO_OTYPER_OT1 GPIO_OTYPER_OT1_Msk
    -
    8286#define GPIO_OTYPER_OT2_Pos (2U)
    -
    8287#define GPIO_OTYPER_OT2_Msk (0x1UL << GPIO_OTYPER_OT2_Pos)
    -
    8288#define GPIO_OTYPER_OT2 GPIO_OTYPER_OT2_Msk
    -
    8289#define GPIO_OTYPER_OT3_Pos (3U)
    -
    8290#define GPIO_OTYPER_OT3_Msk (0x1UL << GPIO_OTYPER_OT3_Pos)
    -
    8291#define GPIO_OTYPER_OT3 GPIO_OTYPER_OT3_Msk
    -
    8292#define GPIO_OTYPER_OT4_Pos (4U)
    -
    8293#define GPIO_OTYPER_OT4_Msk (0x1UL << GPIO_OTYPER_OT4_Pos)
    -
    8294#define GPIO_OTYPER_OT4 GPIO_OTYPER_OT4_Msk
    -
    8295#define GPIO_OTYPER_OT5_Pos (5U)
    -
    8296#define GPIO_OTYPER_OT5_Msk (0x1UL << GPIO_OTYPER_OT5_Pos)
    -
    8297#define GPIO_OTYPER_OT5 GPIO_OTYPER_OT5_Msk
    -
    8298#define GPIO_OTYPER_OT6_Pos (6U)
    -
    8299#define GPIO_OTYPER_OT6_Msk (0x1UL << GPIO_OTYPER_OT6_Pos)
    -
    8300#define GPIO_OTYPER_OT6 GPIO_OTYPER_OT6_Msk
    -
    8301#define GPIO_OTYPER_OT7_Pos (7U)
    -
    8302#define GPIO_OTYPER_OT7_Msk (0x1UL << GPIO_OTYPER_OT7_Pos)
    -
    8303#define GPIO_OTYPER_OT7 GPIO_OTYPER_OT7_Msk
    -
    8304#define GPIO_OTYPER_OT8_Pos (8U)
    -
    8305#define GPIO_OTYPER_OT8_Msk (0x1UL << GPIO_OTYPER_OT8_Pos)
    -
    8306#define GPIO_OTYPER_OT8 GPIO_OTYPER_OT8_Msk
    -
    8307#define GPIO_OTYPER_OT9_Pos (9U)
    -
    8308#define GPIO_OTYPER_OT9_Msk (0x1UL << GPIO_OTYPER_OT9_Pos)
    -
    8309#define GPIO_OTYPER_OT9 GPIO_OTYPER_OT9_Msk
    -
    8310#define GPIO_OTYPER_OT10_Pos (10U)
    -
    8311#define GPIO_OTYPER_OT10_Msk (0x1UL << GPIO_OTYPER_OT10_Pos)
    -
    8312#define GPIO_OTYPER_OT10 GPIO_OTYPER_OT10_Msk
    -
    8313#define GPIO_OTYPER_OT11_Pos (11U)
    -
    8314#define GPIO_OTYPER_OT11_Msk (0x1UL << GPIO_OTYPER_OT11_Pos)
    -
    8315#define GPIO_OTYPER_OT11 GPIO_OTYPER_OT11_Msk
    -
    8316#define GPIO_OTYPER_OT12_Pos (12U)
    -
    8317#define GPIO_OTYPER_OT12_Msk (0x1UL << GPIO_OTYPER_OT12_Pos)
    -
    8318#define GPIO_OTYPER_OT12 GPIO_OTYPER_OT12_Msk
    -
    8319#define GPIO_OTYPER_OT13_Pos (13U)
    -
    8320#define GPIO_OTYPER_OT13_Msk (0x1UL << GPIO_OTYPER_OT13_Pos)
    -
    8321#define GPIO_OTYPER_OT13 GPIO_OTYPER_OT13_Msk
    -
    8322#define GPIO_OTYPER_OT14_Pos (14U)
    -
    8323#define GPIO_OTYPER_OT14_Msk (0x1UL << GPIO_OTYPER_OT14_Pos)
    -
    8324#define GPIO_OTYPER_OT14 GPIO_OTYPER_OT14_Msk
    -
    8325#define GPIO_OTYPER_OT15_Pos (15U)
    -
    8326#define GPIO_OTYPER_OT15_Msk (0x1UL << GPIO_OTYPER_OT15_Pos)
    -
    8327#define GPIO_OTYPER_OT15 GPIO_OTYPER_OT15_Msk
    -
    8328
    -
    8329/* Legacy defines */
    -
    8330#define GPIO_OTYPER_OT_0 GPIO_OTYPER_OT0
    -
    8331#define GPIO_OTYPER_OT_1 GPIO_OTYPER_OT1
    -
    8332#define GPIO_OTYPER_OT_2 GPIO_OTYPER_OT2
    -
    8333#define GPIO_OTYPER_OT_3 GPIO_OTYPER_OT3
    -
    8334#define GPIO_OTYPER_OT_4 GPIO_OTYPER_OT4
    -
    8335#define GPIO_OTYPER_OT_5 GPIO_OTYPER_OT5
    -
    8336#define GPIO_OTYPER_OT_6 GPIO_OTYPER_OT6
    -
    8337#define GPIO_OTYPER_OT_7 GPIO_OTYPER_OT7
    -
    8338#define GPIO_OTYPER_OT_8 GPIO_OTYPER_OT8
    -
    8339#define GPIO_OTYPER_OT_9 GPIO_OTYPER_OT9
    -
    8340#define GPIO_OTYPER_OT_10 GPIO_OTYPER_OT10
    -
    8341#define GPIO_OTYPER_OT_11 GPIO_OTYPER_OT11
    -
    8342#define GPIO_OTYPER_OT_12 GPIO_OTYPER_OT12
    -
    8343#define GPIO_OTYPER_OT_13 GPIO_OTYPER_OT13
    -
    8344#define GPIO_OTYPER_OT_14 GPIO_OTYPER_OT14
    -
    8345#define GPIO_OTYPER_OT_15 GPIO_OTYPER_OT15
    -
    8346
    -
    8347/****************** Bits definition for GPIO_OSPEEDR register ***************/
    -
    8348#define GPIO_OSPEEDR_OSPEED0_Pos (0U)
    -
    8349#define GPIO_OSPEEDR_OSPEED0_Msk (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos)
    -
    8350#define GPIO_OSPEEDR_OSPEED0 GPIO_OSPEEDR_OSPEED0_Msk
    -
    8351#define GPIO_OSPEEDR_OSPEED0_0 (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos)
    -
    8352#define GPIO_OSPEEDR_OSPEED0_1 (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos)
    -
    8353#define GPIO_OSPEEDR_OSPEED1_Pos (2U)
    -
    8354#define GPIO_OSPEEDR_OSPEED1_Msk (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos)
    -
    8355#define GPIO_OSPEEDR_OSPEED1 GPIO_OSPEEDR_OSPEED1_Msk
    -
    8356#define GPIO_OSPEEDR_OSPEED1_0 (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos)
    -
    8357#define GPIO_OSPEEDR_OSPEED1_1 (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos)
    -
    8358#define GPIO_OSPEEDR_OSPEED2_Pos (4U)
    -
    8359#define GPIO_OSPEEDR_OSPEED2_Msk (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos)
    -
    8360#define GPIO_OSPEEDR_OSPEED2 GPIO_OSPEEDR_OSPEED2_Msk
    -
    8361#define GPIO_OSPEEDR_OSPEED2_0 (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos)
    -
    8362#define GPIO_OSPEEDR_OSPEED2_1 (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos)
    -
    8363#define GPIO_OSPEEDR_OSPEED3_Pos (6U)
    -
    8364#define GPIO_OSPEEDR_OSPEED3_Msk (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos)
    -
    8365#define GPIO_OSPEEDR_OSPEED3 GPIO_OSPEEDR_OSPEED3_Msk
    -
    8366#define GPIO_OSPEEDR_OSPEED3_0 (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos)
    -
    8367#define GPIO_OSPEEDR_OSPEED3_1 (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos)
    -
    8368#define GPIO_OSPEEDR_OSPEED4_Pos (8U)
    -
    8369#define GPIO_OSPEEDR_OSPEED4_Msk (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos)
    -
    8370#define GPIO_OSPEEDR_OSPEED4 GPIO_OSPEEDR_OSPEED4_Msk
    -
    8371#define GPIO_OSPEEDR_OSPEED4_0 (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos)
    -
    8372#define GPIO_OSPEEDR_OSPEED4_1 (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos)
    -
    8373#define GPIO_OSPEEDR_OSPEED5_Pos (10U)
    -
    8374#define GPIO_OSPEEDR_OSPEED5_Msk (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos)
    -
    8375#define GPIO_OSPEEDR_OSPEED5 GPIO_OSPEEDR_OSPEED5_Msk
    -
    8376#define GPIO_OSPEEDR_OSPEED5_0 (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos)
    -
    8377#define GPIO_OSPEEDR_OSPEED5_1 (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos)
    -
    8378#define GPIO_OSPEEDR_OSPEED6_Pos (12U)
    -
    8379#define GPIO_OSPEEDR_OSPEED6_Msk (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos)
    -
    8380#define GPIO_OSPEEDR_OSPEED6 GPIO_OSPEEDR_OSPEED6_Msk
    -
    8381#define GPIO_OSPEEDR_OSPEED6_0 (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos)
    -
    8382#define GPIO_OSPEEDR_OSPEED6_1 (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos)
    -
    8383#define GPIO_OSPEEDR_OSPEED7_Pos (14U)
    -
    8384#define GPIO_OSPEEDR_OSPEED7_Msk (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos)
    -
    8385#define GPIO_OSPEEDR_OSPEED7 GPIO_OSPEEDR_OSPEED7_Msk
    -
    8386#define GPIO_OSPEEDR_OSPEED7_0 (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos)
    -
    8387#define GPIO_OSPEEDR_OSPEED7_1 (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos)
    -
    8388#define GPIO_OSPEEDR_OSPEED8_Pos (16U)
    -
    8389#define GPIO_OSPEEDR_OSPEED8_Msk (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos)
    -
    8390#define GPIO_OSPEEDR_OSPEED8 GPIO_OSPEEDR_OSPEED8_Msk
    -
    8391#define GPIO_OSPEEDR_OSPEED8_0 (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos)
    -
    8392#define GPIO_OSPEEDR_OSPEED8_1 (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos)
    -
    8393#define GPIO_OSPEEDR_OSPEED9_Pos (18U)
    -
    8394#define GPIO_OSPEEDR_OSPEED9_Msk (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos)
    -
    8395#define GPIO_OSPEEDR_OSPEED9 GPIO_OSPEEDR_OSPEED9_Msk
    -
    8396#define GPIO_OSPEEDR_OSPEED9_0 (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos)
    -
    8397#define GPIO_OSPEEDR_OSPEED9_1 (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos)
    -
    8398#define GPIO_OSPEEDR_OSPEED10_Pos (20U)
    -
    8399#define GPIO_OSPEEDR_OSPEED10_Msk (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos)
    -
    8400#define GPIO_OSPEEDR_OSPEED10 GPIO_OSPEEDR_OSPEED10_Msk
    -
    8401#define GPIO_OSPEEDR_OSPEED10_0 (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos)
    -
    8402#define GPIO_OSPEEDR_OSPEED10_1 (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos)
    -
    8403#define GPIO_OSPEEDR_OSPEED11_Pos (22U)
    -
    8404#define GPIO_OSPEEDR_OSPEED11_Msk (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos)
    -
    8405#define GPIO_OSPEEDR_OSPEED11 GPIO_OSPEEDR_OSPEED11_Msk
    -
    8406#define GPIO_OSPEEDR_OSPEED11_0 (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos)
    -
    8407#define GPIO_OSPEEDR_OSPEED11_1 (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos)
    -
    8408#define GPIO_OSPEEDR_OSPEED12_Pos (24U)
    -
    8409#define GPIO_OSPEEDR_OSPEED12_Msk (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos)
    -
    8410#define GPIO_OSPEEDR_OSPEED12 GPIO_OSPEEDR_OSPEED12_Msk
    -
    8411#define GPIO_OSPEEDR_OSPEED12_0 (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos)
    -
    8412#define GPIO_OSPEEDR_OSPEED12_1 (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos)
    -
    8413#define GPIO_OSPEEDR_OSPEED13_Pos (26U)
    -
    8414#define GPIO_OSPEEDR_OSPEED13_Msk (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos)
    -
    8415#define GPIO_OSPEEDR_OSPEED13 GPIO_OSPEEDR_OSPEED13_Msk
    -
    8416#define GPIO_OSPEEDR_OSPEED13_0 (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos)
    -
    8417#define GPIO_OSPEEDR_OSPEED13_1 (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos)
    -
    8418#define GPIO_OSPEEDR_OSPEED14_Pos (28U)
    -
    8419#define GPIO_OSPEEDR_OSPEED14_Msk (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos)
    -
    8420#define GPIO_OSPEEDR_OSPEED14 GPIO_OSPEEDR_OSPEED14_Msk
    -
    8421#define GPIO_OSPEEDR_OSPEED14_0 (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos)
    -
    8422#define GPIO_OSPEEDR_OSPEED14_1 (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos)
    -
    8423#define GPIO_OSPEEDR_OSPEED15_Pos (30U)
    -
    8424#define GPIO_OSPEEDR_OSPEED15_Msk (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos)
    -
    8425#define GPIO_OSPEEDR_OSPEED15 GPIO_OSPEEDR_OSPEED15_Msk
    -
    8426#define GPIO_OSPEEDR_OSPEED15_0 (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos)
    -
    8427#define GPIO_OSPEEDR_OSPEED15_1 (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos)
    -
    8429/* Legacy defines */
    -
    8430#define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDR_OSPEED0
    -
    8431#define GPIO_OSPEEDER_OSPEEDR0_0 GPIO_OSPEEDR_OSPEED0_0
    -
    8432#define GPIO_OSPEEDER_OSPEEDR0_1 GPIO_OSPEEDR_OSPEED0_1
    -
    8433#define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDR_OSPEED1
    -
    8434#define GPIO_OSPEEDER_OSPEEDR1_0 GPIO_OSPEEDR_OSPEED1_0
    -
    8435#define GPIO_OSPEEDER_OSPEEDR1_1 GPIO_OSPEEDR_OSPEED1_1
    -
    8436#define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDR_OSPEED2
    -
    8437#define GPIO_OSPEEDER_OSPEEDR2_0 GPIO_OSPEEDR_OSPEED2_0
    -
    8438#define GPIO_OSPEEDER_OSPEEDR2_1 GPIO_OSPEEDR_OSPEED2_1
    -
    8439#define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDR_OSPEED3
    -
    8440#define GPIO_OSPEEDER_OSPEEDR3_0 GPIO_OSPEEDR_OSPEED3_0
    -
    8441#define GPIO_OSPEEDER_OSPEEDR3_1 GPIO_OSPEEDR_OSPEED3_1
    -
    8442#define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDR_OSPEED4
    -
    8443#define GPIO_OSPEEDER_OSPEEDR4_0 GPIO_OSPEEDR_OSPEED4_0
    -
    8444#define GPIO_OSPEEDER_OSPEEDR4_1 GPIO_OSPEEDR_OSPEED4_1
    -
    8445#define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDR_OSPEED5
    -
    8446#define GPIO_OSPEEDER_OSPEEDR5_0 GPIO_OSPEEDR_OSPEED5_0
    -
    8447#define GPIO_OSPEEDER_OSPEEDR5_1 GPIO_OSPEEDR_OSPEED5_1
    -
    8448#define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDR_OSPEED6
    -
    8449#define GPIO_OSPEEDER_OSPEEDR6_0 GPIO_OSPEEDR_OSPEED6_0
    -
    8450#define GPIO_OSPEEDER_OSPEEDR6_1 GPIO_OSPEEDR_OSPEED6_1
    -
    8451#define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDR_OSPEED7
    -
    8452#define GPIO_OSPEEDER_OSPEEDR7_0 GPIO_OSPEEDR_OSPEED7_0
    -
    8453#define GPIO_OSPEEDER_OSPEEDR7_1 GPIO_OSPEEDR_OSPEED7_1
    -
    8454#define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDR_OSPEED8
    -
    8455#define GPIO_OSPEEDER_OSPEEDR8_0 GPIO_OSPEEDR_OSPEED8_0
    -
    8456#define GPIO_OSPEEDER_OSPEEDR8_1 GPIO_OSPEEDR_OSPEED8_1
    -
    8457#define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDR_OSPEED9
    -
    8458#define GPIO_OSPEEDER_OSPEEDR9_0 GPIO_OSPEEDR_OSPEED9_0
    -
    8459#define GPIO_OSPEEDER_OSPEEDR9_1 GPIO_OSPEEDR_OSPEED9_1
    -
    8460#define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDR_OSPEED10
    -
    8461#define GPIO_OSPEEDER_OSPEEDR10_0 GPIO_OSPEEDR_OSPEED10_0
    -
    8462#define GPIO_OSPEEDER_OSPEEDR10_1 GPIO_OSPEEDR_OSPEED10_1
    -
    8463#define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDR_OSPEED11
    -
    8464#define GPIO_OSPEEDER_OSPEEDR11_0 GPIO_OSPEEDR_OSPEED11_0
    -
    8465#define GPIO_OSPEEDER_OSPEEDR11_1 GPIO_OSPEEDR_OSPEED11_1
    -
    8466#define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDR_OSPEED12
    -
    8467#define GPIO_OSPEEDER_OSPEEDR12_0 GPIO_OSPEEDR_OSPEED12_0
    -
    8468#define GPIO_OSPEEDER_OSPEEDR12_1 GPIO_OSPEEDR_OSPEED12_1
    -
    8469#define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDR_OSPEED13
    -
    8470#define GPIO_OSPEEDER_OSPEEDR13_0 GPIO_OSPEEDR_OSPEED13_0
    -
    8471#define GPIO_OSPEEDER_OSPEEDR13_1 GPIO_OSPEEDR_OSPEED13_1
    -
    8472#define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDR_OSPEED14
    -
    8473#define GPIO_OSPEEDER_OSPEEDR14_0 GPIO_OSPEEDR_OSPEED14_0
    -
    8474#define GPIO_OSPEEDER_OSPEEDR14_1 GPIO_OSPEEDR_OSPEED14_1
    -
    8475#define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDR_OSPEED15
    -
    8476#define GPIO_OSPEEDER_OSPEEDR15_0 GPIO_OSPEEDR_OSPEED15_0
    -
    8477#define GPIO_OSPEEDER_OSPEEDR15_1 GPIO_OSPEEDR_OSPEED15_1
    -
    8478
    -
    8479/****************** Bits definition for GPIO_PUPDR register *****************/
    -
    8480#define GPIO_PUPDR_PUPD0_Pos (0U)
    -
    8481#define GPIO_PUPDR_PUPD0_Msk (0x3UL << GPIO_PUPDR_PUPD0_Pos)
    -
    8482#define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk
    -
    8483#define GPIO_PUPDR_PUPD0_0 (0x1UL << GPIO_PUPDR_PUPD0_Pos)
    -
    8484#define GPIO_PUPDR_PUPD0_1 (0x2UL << GPIO_PUPDR_PUPD0_Pos)
    -
    8485#define GPIO_PUPDR_PUPD1_Pos (2U)
    -
    8486#define GPIO_PUPDR_PUPD1_Msk (0x3UL << GPIO_PUPDR_PUPD1_Pos)
    -
    8487#define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk
    -
    8488#define GPIO_PUPDR_PUPD1_0 (0x1UL << GPIO_PUPDR_PUPD1_Pos)
    -
    8489#define GPIO_PUPDR_PUPD1_1 (0x2UL << GPIO_PUPDR_PUPD1_Pos)
    -
    8490#define GPIO_PUPDR_PUPD2_Pos (4U)
    -
    8491#define GPIO_PUPDR_PUPD2_Msk (0x3UL << GPIO_PUPDR_PUPD2_Pos)
    -
    8492#define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk
    -
    8493#define GPIO_PUPDR_PUPD2_0 (0x1UL << GPIO_PUPDR_PUPD2_Pos)
    -
    8494#define GPIO_PUPDR_PUPD2_1 (0x2UL << GPIO_PUPDR_PUPD2_Pos)
    -
    8495#define GPIO_PUPDR_PUPD3_Pos (6U)
    -
    8496#define GPIO_PUPDR_PUPD3_Msk (0x3UL << GPIO_PUPDR_PUPD3_Pos)
    -
    8497#define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk
    -
    8498#define GPIO_PUPDR_PUPD3_0 (0x1UL << GPIO_PUPDR_PUPD3_Pos)
    -
    8499#define GPIO_PUPDR_PUPD3_1 (0x2UL << GPIO_PUPDR_PUPD3_Pos)
    -
    8500#define GPIO_PUPDR_PUPD4_Pos (8U)
    -
    8501#define GPIO_PUPDR_PUPD4_Msk (0x3UL << GPIO_PUPDR_PUPD4_Pos)
    -
    8502#define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk
    -
    8503#define GPIO_PUPDR_PUPD4_0 (0x1UL << GPIO_PUPDR_PUPD4_Pos)
    -
    8504#define GPIO_PUPDR_PUPD4_1 (0x2UL << GPIO_PUPDR_PUPD4_Pos)
    -
    8505#define GPIO_PUPDR_PUPD5_Pos (10U)
    -
    8506#define GPIO_PUPDR_PUPD5_Msk (0x3UL << GPIO_PUPDR_PUPD5_Pos)
    -
    8507#define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk
    -
    8508#define GPIO_PUPDR_PUPD5_0 (0x1UL << GPIO_PUPDR_PUPD5_Pos)
    -
    8509#define GPIO_PUPDR_PUPD5_1 (0x2UL << GPIO_PUPDR_PUPD5_Pos)
    -
    8510#define GPIO_PUPDR_PUPD6_Pos (12U)
    -
    8511#define GPIO_PUPDR_PUPD6_Msk (0x3UL << GPIO_PUPDR_PUPD6_Pos)
    -
    8512#define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk
    -
    8513#define GPIO_PUPDR_PUPD6_0 (0x1UL << GPIO_PUPDR_PUPD6_Pos)
    -
    8514#define GPIO_PUPDR_PUPD6_1 (0x2UL << GPIO_PUPDR_PUPD6_Pos)
    -
    8515#define GPIO_PUPDR_PUPD7_Pos (14U)
    -
    8516#define GPIO_PUPDR_PUPD7_Msk (0x3UL << GPIO_PUPDR_PUPD7_Pos)
    -
    8517#define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk
    -
    8518#define GPIO_PUPDR_PUPD7_0 (0x1UL << GPIO_PUPDR_PUPD7_Pos)
    -
    8519#define GPIO_PUPDR_PUPD7_1 (0x2UL << GPIO_PUPDR_PUPD7_Pos)
    -
    8520#define GPIO_PUPDR_PUPD8_Pos (16U)
    -
    8521#define GPIO_PUPDR_PUPD8_Msk (0x3UL << GPIO_PUPDR_PUPD8_Pos)
    -
    8522#define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk
    -
    8523#define GPIO_PUPDR_PUPD8_0 (0x1UL << GPIO_PUPDR_PUPD8_Pos)
    -
    8524#define GPIO_PUPDR_PUPD8_1 (0x2UL << GPIO_PUPDR_PUPD8_Pos)
    -
    8525#define GPIO_PUPDR_PUPD9_Pos (18U)
    -
    8526#define GPIO_PUPDR_PUPD9_Msk (0x3UL << GPIO_PUPDR_PUPD9_Pos)
    -
    8527#define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk
    -
    8528#define GPIO_PUPDR_PUPD9_0 (0x1UL << GPIO_PUPDR_PUPD9_Pos)
    -
    8529#define GPIO_PUPDR_PUPD9_1 (0x2UL << GPIO_PUPDR_PUPD9_Pos)
    -
    8530#define GPIO_PUPDR_PUPD10_Pos (20U)
    -
    8531#define GPIO_PUPDR_PUPD10_Msk (0x3UL << GPIO_PUPDR_PUPD10_Pos)
    -
    8532#define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk
    -
    8533#define GPIO_PUPDR_PUPD10_0 (0x1UL << GPIO_PUPDR_PUPD10_Pos)
    -
    8534#define GPIO_PUPDR_PUPD10_1 (0x2UL << GPIO_PUPDR_PUPD10_Pos)
    -
    8535#define GPIO_PUPDR_PUPD11_Pos (22U)
    -
    8536#define GPIO_PUPDR_PUPD11_Msk (0x3UL << GPIO_PUPDR_PUPD11_Pos)
    -
    8537#define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk
    -
    8538#define GPIO_PUPDR_PUPD11_0 (0x1UL << GPIO_PUPDR_PUPD11_Pos)
    -
    8539#define GPIO_PUPDR_PUPD11_1 (0x2UL << GPIO_PUPDR_PUPD11_Pos)
    -
    8540#define GPIO_PUPDR_PUPD12_Pos (24U)
    -
    8541#define GPIO_PUPDR_PUPD12_Msk (0x3UL << GPIO_PUPDR_PUPD12_Pos)
    -
    8542#define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk
    -
    8543#define GPIO_PUPDR_PUPD12_0 (0x1UL << GPIO_PUPDR_PUPD12_Pos)
    -
    8544#define GPIO_PUPDR_PUPD12_1 (0x2UL << GPIO_PUPDR_PUPD12_Pos)
    -
    8545#define GPIO_PUPDR_PUPD13_Pos (26U)
    -
    8546#define GPIO_PUPDR_PUPD13_Msk (0x3UL << GPIO_PUPDR_PUPD13_Pos)
    -
    8547#define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk
    -
    8548#define GPIO_PUPDR_PUPD13_0 (0x1UL << GPIO_PUPDR_PUPD13_Pos)
    -
    8549#define GPIO_PUPDR_PUPD13_1 (0x2UL << GPIO_PUPDR_PUPD13_Pos)
    -
    8550#define GPIO_PUPDR_PUPD14_Pos (28U)
    -
    8551#define GPIO_PUPDR_PUPD14_Msk (0x3UL << GPIO_PUPDR_PUPD14_Pos)
    -
    8552#define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk
    -
    8553#define GPIO_PUPDR_PUPD14_0 (0x1UL << GPIO_PUPDR_PUPD14_Pos)
    -
    8554#define GPIO_PUPDR_PUPD14_1 (0x2UL << GPIO_PUPDR_PUPD14_Pos)
    -
    8555#define GPIO_PUPDR_PUPD15_Pos (30U)
    -
    8556#define GPIO_PUPDR_PUPD15_Msk (0x3UL << GPIO_PUPDR_PUPD15_Pos)
    -
    8557#define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk
    -
    8558#define GPIO_PUPDR_PUPD15_0 (0x1UL << GPIO_PUPDR_PUPD15_Pos)
    -
    8559#define GPIO_PUPDR_PUPD15_1 (0x2UL << GPIO_PUPDR_PUPD15_Pos)
    -
    8561/* Legacy defines */
    -
    8562#define GPIO_PUPDR_PUPDR0 GPIO_PUPDR_PUPD0
    -
    8563#define GPIO_PUPDR_PUPDR0_0 GPIO_PUPDR_PUPD0_0
    -
    8564#define GPIO_PUPDR_PUPDR0_1 GPIO_PUPDR_PUPD0_1
    -
    8565#define GPIO_PUPDR_PUPDR1 GPIO_PUPDR_PUPD1
    -
    8566#define GPIO_PUPDR_PUPDR1_0 GPIO_PUPDR_PUPD1_0
    -
    8567#define GPIO_PUPDR_PUPDR1_1 GPIO_PUPDR_PUPD1_1
    -
    8568#define GPIO_PUPDR_PUPDR2 GPIO_PUPDR_PUPD2
    -
    8569#define GPIO_PUPDR_PUPDR2_0 GPIO_PUPDR_PUPD2_0
    -
    8570#define GPIO_PUPDR_PUPDR2_1 GPIO_PUPDR_PUPD2_1
    -
    8571#define GPIO_PUPDR_PUPDR3 GPIO_PUPDR_PUPD3
    -
    8572#define GPIO_PUPDR_PUPDR3_0 GPIO_PUPDR_PUPD3_0
    -
    8573#define GPIO_PUPDR_PUPDR3_1 GPIO_PUPDR_PUPD3_1
    -
    8574#define GPIO_PUPDR_PUPDR4 GPIO_PUPDR_PUPD4
    -
    8575#define GPIO_PUPDR_PUPDR4_0 GPIO_PUPDR_PUPD4_0
    -
    8576#define GPIO_PUPDR_PUPDR4_1 GPIO_PUPDR_PUPD4_1
    -
    8577#define GPIO_PUPDR_PUPDR5 GPIO_PUPDR_PUPD5
    -
    8578#define GPIO_PUPDR_PUPDR5_0 GPIO_PUPDR_PUPD5_0
    -
    8579#define GPIO_PUPDR_PUPDR5_1 GPIO_PUPDR_PUPD5_1
    -
    8580#define GPIO_PUPDR_PUPDR6 GPIO_PUPDR_PUPD6
    -
    8581#define GPIO_PUPDR_PUPDR6_0 GPIO_PUPDR_PUPD6_0
    -
    8582#define GPIO_PUPDR_PUPDR6_1 GPIO_PUPDR_PUPD6_1
    -
    8583#define GPIO_PUPDR_PUPDR7 GPIO_PUPDR_PUPD7
    -
    8584#define GPIO_PUPDR_PUPDR7_0 GPIO_PUPDR_PUPD7_0
    -
    8585#define GPIO_PUPDR_PUPDR7_1 GPIO_PUPDR_PUPD7_1
    -
    8586#define GPIO_PUPDR_PUPDR8 GPIO_PUPDR_PUPD8
    -
    8587#define GPIO_PUPDR_PUPDR8_0 GPIO_PUPDR_PUPD8_0
    -
    8588#define GPIO_PUPDR_PUPDR8_1 GPIO_PUPDR_PUPD8_1
    -
    8589#define GPIO_PUPDR_PUPDR9 GPIO_PUPDR_PUPD9
    -
    8590#define GPIO_PUPDR_PUPDR9_0 GPIO_PUPDR_PUPD9_0
    -
    8591#define GPIO_PUPDR_PUPDR9_1 GPIO_PUPDR_PUPD9_1
    -
    8592#define GPIO_PUPDR_PUPDR10 GPIO_PUPDR_PUPD10
    -
    8593#define GPIO_PUPDR_PUPDR10_0 GPIO_PUPDR_PUPD10_0
    -
    8594#define GPIO_PUPDR_PUPDR10_1 GPIO_PUPDR_PUPD10_1
    -
    8595#define GPIO_PUPDR_PUPDR11 GPIO_PUPDR_PUPD11
    -
    8596#define GPIO_PUPDR_PUPDR11_0 GPIO_PUPDR_PUPD11_0
    -
    8597#define GPIO_PUPDR_PUPDR11_1 GPIO_PUPDR_PUPD11_1
    -
    8598#define GPIO_PUPDR_PUPDR12 GPIO_PUPDR_PUPD12
    -
    8599#define GPIO_PUPDR_PUPDR12_0 GPIO_PUPDR_PUPD12_0
    -
    8600#define GPIO_PUPDR_PUPDR12_1 GPIO_PUPDR_PUPD12_1
    -
    8601#define GPIO_PUPDR_PUPDR13 GPIO_PUPDR_PUPD13
    -
    8602#define GPIO_PUPDR_PUPDR13_0 GPIO_PUPDR_PUPD13_0
    -
    8603#define GPIO_PUPDR_PUPDR13_1 GPIO_PUPDR_PUPD13_1
    -
    8604#define GPIO_PUPDR_PUPDR14 GPIO_PUPDR_PUPD14
    -
    8605#define GPIO_PUPDR_PUPDR14_0 GPIO_PUPDR_PUPD14_0
    -
    8606#define GPIO_PUPDR_PUPDR14_1 GPIO_PUPDR_PUPD14_1
    -
    8607#define GPIO_PUPDR_PUPDR15 GPIO_PUPDR_PUPD15
    -
    8608#define GPIO_PUPDR_PUPDR15_0 GPIO_PUPDR_PUPD15_0
    -
    8609#define GPIO_PUPDR_PUPDR15_1 GPIO_PUPDR_PUPD15_1
    -
    8610
    -
    8611/****************** Bits definition for GPIO_IDR register *******************/
    -
    8612#define GPIO_IDR_ID0_Pos (0U)
    -
    8613#define GPIO_IDR_ID0_Msk (0x1UL << GPIO_IDR_ID0_Pos)
    -
    8614#define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk
    -
    8615#define GPIO_IDR_ID1_Pos (1U)
    -
    8616#define GPIO_IDR_ID1_Msk (0x1UL << GPIO_IDR_ID1_Pos)
    -
    8617#define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk
    -
    8618#define GPIO_IDR_ID2_Pos (2U)
    -
    8619#define GPIO_IDR_ID2_Msk (0x1UL << GPIO_IDR_ID2_Pos)
    -
    8620#define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk
    -
    8621#define GPIO_IDR_ID3_Pos (3U)
    -
    8622#define GPIO_IDR_ID3_Msk (0x1UL << GPIO_IDR_ID3_Pos)
    -
    8623#define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk
    -
    8624#define GPIO_IDR_ID4_Pos (4U)
    -
    8625#define GPIO_IDR_ID4_Msk (0x1UL << GPIO_IDR_ID4_Pos)
    -
    8626#define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk
    -
    8627#define GPIO_IDR_ID5_Pos (5U)
    -
    8628#define GPIO_IDR_ID5_Msk (0x1UL << GPIO_IDR_ID5_Pos)
    -
    8629#define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk
    -
    8630#define GPIO_IDR_ID6_Pos (6U)
    -
    8631#define GPIO_IDR_ID6_Msk (0x1UL << GPIO_IDR_ID6_Pos)
    -
    8632#define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk
    -
    8633#define GPIO_IDR_ID7_Pos (7U)
    -
    8634#define GPIO_IDR_ID7_Msk (0x1UL << GPIO_IDR_ID7_Pos)
    -
    8635#define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk
    -
    8636#define GPIO_IDR_ID8_Pos (8U)
    -
    8637#define GPIO_IDR_ID8_Msk (0x1UL << GPIO_IDR_ID8_Pos)
    -
    8638#define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk
    -
    8639#define GPIO_IDR_ID9_Pos (9U)
    -
    8640#define GPIO_IDR_ID9_Msk (0x1UL << GPIO_IDR_ID9_Pos)
    -
    8641#define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk
    -
    8642#define GPIO_IDR_ID10_Pos (10U)
    -
    8643#define GPIO_IDR_ID10_Msk (0x1UL << GPIO_IDR_ID10_Pos)
    -
    8644#define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk
    -
    8645#define GPIO_IDR_ID11_Pos (11U)
    -
    8646#define GPIO_IDR_ID11_Msk (0x1UL << GPIO_IDR_ID11_Pos)
    -
    8647#define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk
    -
    8648#define GPIO_IDR_ID12_Pos (12U)
    -
    8649#define GPIO_IDR_ID12_Msk (0x1UL << GPIO_IDR_ID12_Pos)
    -
    8650#define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk
    -
    8651#define GPIO_IDR_ID13_Pos (13U)
    -
    8652#define GPIO_IDR_ID13_Msk (0x1UL << GPIO_IDR_ID13_Pos)
    -
    8653#define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk
    -
    8654#define GPIO_IDR_ID14_Pos (14U)
    -
    8655#define GPIO_IDR_ID14_Msk (0x1UL << GPIO_IDR_ID14_Pos)
    -
    8656#define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk
    -
    8657#define GPIO_IDR_ID15_Pos (15U)
    -
    8658#define GPIO_IDR_ID15_Msk (0x1UL << GPIO_IDR_ID15_Pos)
    -
    8659#define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk
    -
    8660
    -
    8661/* Legacy defines */
    -
    8662#define GPIO_IDR_IDR_0 GPIO_IDR_ID0
    -
    8663#define GPIO_IDR_IDR_1 GPIO_IDR_ID1
    -
    8664#define GPIO_IDR_IDR_2 GPIO_IDR_ID2
    -
    8665#define GPIO_IDR_IDR_3 GPIO_IDR_ID3
    -
    8666#define GPIO_IDR_IDR_4 GPIO_IDR_ID4
    -
    8667#define GPIO_IDR_IDR_5 GPIO_IDR_ID5
    -
    8668#define GPIO_IDR_IDR_6 GPIO_IDR_ID6
    -
    8669#define GPIO_IDR_IDR_7 GPIO_IDR_ID7
    -
    8670#define GPIO_IDR_IDR_8 GPIO_IDR_ID8
    -
    8671#define GPIO_IDR_IDR_9 GPIO_IDR_ID9
    -
    8672#define GPIO_IDR_IDR_10 GPIO_IDR_ID10
    -
    8673#define GPIO_IDR_IDR_11 GPIO_IDR_ID11
    -
    8674#define GPIO_IDR_IDR_12 GPIO_IDR_ID12
    -
    8675#define GPIO_IDR_IDR_13 GPIO_IDR_ID13
    -
    8676#define GPIO_IDR_IDR_14 GPIO_IDR_ID14
    -
    8677#define GPIO_IDR_IDR_15 GPIO_IDR_ID15
    -
    8678
    -
    8679/****************** Bits definition for GPIO_ODR register *******************/
    -
    8680#define GPIO_ODR_OD0_Pos (0U)
    -
    8681#define GPIO_ODR_OD0_Msk (0x1UL << GPIO_ODR_OD0_Pos)
    -
    8682#define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk
    -
    8683#define GPIO_ODR_OD1_Pos (1U)
    -
    8684#define GPIO_ODR_OD1_Msk (0x1UL << GPIO_ODR_OD1_Pos)
    -
    8685#define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk
    -
    8686#define GPIO_ODR_OD2_Pos (2U)
    -
    8687#define GPIO_ODR_OD2_Msk (0x1UL << GPIO_ODR_OD2_Pos)
    -
    8688#define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk
    -
    8689#define GPIO_ODR_OD3_Pos (3U)
    -
    8690#define GPIO_ODR_OD3_Msk (0x1UL << GPIO_ODR_OD3_Pos)
    -
    8691#define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk
    -
    8692#define GPIO_ODR_OD4_Pos (4U)
    -
    8693#define GPIO_ODR_OD4_Msk (0x1UL << GPIO_ODR_OD4_Pos)
    -
    8694#define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk
    -
    8695#define GPIO_ODR_OD5_Pos (5U)
    -
    8696#define GPIO_ODR_OD5_Msk (0x1UL << GPIO_ODR_OD5_Pos)
    -
    8697#define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk
    -
    8698#define GPIO_ODR_OD6_Pos (6U)
    -
    8699#define GPIO_ODR_OD6_Msk (0x1UL << GPIO_ODR_OD6_Pos)
    -
    8700#define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk
    -
    8701#define GPIO_ODR_OD7_Pos (7U)
    -
    8702#define GPIO_ODR_OD7_Msk (0x1UL << GPIO_ODR_OD7_Pos)
    -
    8703#define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk
    -
    8704#define GPIO_ODR_OD8_Pos (8U)
    -
    8705#define GPIO_ODR_OD8_Msk (0x1UL << GPIO_ODR_OD8_Pos)
    -
    8706#define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk
    -
    8707#define GPIO_ODR_OD9_Pos (9U)
    -
    8708#define GPIO_ODR_OD9_Msk (0x1UL << GPIO_ODR_OD9_Pos)
    -
    8709#define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk
    -
    8710#define GPIO_ODR_OD10_Pos (10U)
    -
    8711#define GPIO_ODR_OD10_Msk (0x1UL << GPIO_ODR_OD10_Pos)
    -
    8712#define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk
    -
    8713#define GPIO_ODR_OD11_Pos (11U)
    -
    8714#define GPIO_ODR_OD11_Msk (0x1UL << GPIO_ODR_OD11_Pos)
    -
    8715#define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk
    -
    8716#define GPIO_ODR_OD12_Pos (12U)
    -
    8717#define GPIO_ODR_OD12_Msk (0x1UL << GPIO_ODR_OD12_Pos)
    -
    8718#define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk
    -
    8719#define GPIO_ODR_OD13_Pos (13U)
    -
    8720#define GPIO_ODR_OD13_Msk (0x1UL << GPIO_ODR_OD13_Pos)
    -
    8721#define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk
    -
    8722#define GPIO_ODR_OD14_Pos (14U)
    -
    8723#define GPIO_ODR_OD14_Msk (0x1UL << GPIO_ODR_OD14_Pos)
    -
    8724#define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk
    -
    8725#define GPIO_ODR_OD15_Pos (15U)
    -
    8726#define GPIO_ODR_OD15_Msk (0x1UL << GPIO_ODR_OD15_Pos)
    -
    8727#define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk
    -
    8728/* Legacy defines */
    -
    8729#define GPIO_ODR_ODR_0 GPIO_ODR_OD0
    -
    8730#define GPIO_ODR_ODR_1 GPIO_ODR_OD1
    -
    8731#define GPIO_ODR_ODR_2 GPIO_ODR_OD2
    -
    8732#define GPIO_ODR_ODR_3 GPIO_ODR_OD3
    -
    8733#define GPIO_ODR_ODR_4 GPIO_ODR_OD4
    -
    8734#define GPIO_ODR_ODR_5 GPIO_ODR_OD5
    -
    8735#define GPIO_ODR_ODR_6 GPIO_ODR_OD6
    -
    8736#define GPIO_ODR_ODR_7 GPIO_ODR_OD7
    -
    8737#define GPIO_ODR_ODR_8 GPIO_ODR_OD8
    -
    8738#define GPIO_ODR_ODR_9 GPIO_ODR_OD9
    -
    8739#define GPIO_ODR_ODR_10 GPIO_ODR_OD10
    -
    8740#define GPIO_ODR_ODR_11 GPIO_ODR_OD11
    -
    8741#define GPIO_ODR_ODR_12 GPIO_ODR_OD12
    -
    8742#define GPIO_ODR_ODR_13 GPIO_ODR_OD13
    -
    8743#define GPIO_ODR_ODR_14 GPIO_ODR_OD14
    -
    8744#define GPIO_ODR_ODR_15 GPIO_ODR_OD15
    -
    8745
    -
    8746/****************** Bits definition for GPIO_BSRR register ******************/
    -
    8747#define GPIO_BSRR_BS0_Pos (0U)
    -
    8748#define GPIO_BSRR_BS0_Msk (0x1UL << GPIO_BSRR_BS0_Pos)
    -
    8749#define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk
    -
    8750#define GPIO_BSRR_BS1_Pos (1U)
    -
    8751#define GPIO_BSRR_BS1_Msk (0x1UL << GPIO_BSRR_BS1_Pos)
    -
    8752#define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk
    -
    8753#define GPIO_BSRR_BS2_Pos (2U)
    -
    8754#define GPIO_BSRR_BS2_Msk (0x1UL << GPIO_BSRR_BS2_Pos)
    -
    8755#define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk
    -
    8756#define GPIO_BSRR_BS3_Pos (3U)
    -
    8757#define GPIO_BSRR_BS3_Msk (0x1UL << GPIO_BSRR_BS3_Pos)
    -
    8758#define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk
    -
    8759#define GPIO_BSRR_BS4_Pos (4U)
    -
    8760#define GPIO_BSRR_BS4_Msk (0x1UL << GPIO_BSRR_BS4_Pos)
    -
    8761#define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk
    -
    8762#define GPIO_BSRR_BS5_Pos (5U)
    -
    8763#define GPIO_BSRR_BS5_Msk (0x1UL << GPIO_BSRR_BS5_Pos)
    -
    8764#define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk
    -
    8765#define GPIO_BSRR_BS6_Pos (6U)
    -
    8766#define GPIO_BSRR_BS6_Msk (0x1UL << GPIO_BSRR_BS6_Pos)
    -
    8767#define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk
    -
    8768#define GPIO_BSRR_BS7_Pos (7U)
    -
    8769#define GPIO_BSRR_BS7_Msk (0x1UL << GPIO_BSRR_BS7_Pos)
    -
    8770#define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk
    -
    8771#define GPIO_BSRR_BS8_Pos (8U)
    -
    8772#define GPIO_BSRR_BS8_Msk (0x1UL << GPIO_BSRR_BS8_Pos)
    -
    8773#define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk
    -
    8774#define GPIO_BSRR_BS9_Pos (9U)
    -
    8775#define GPIO_BSRR_BS9_Msk (0x1UL << GPIO_BSRR_BS9_Pos)
    -
    8776#define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk
    -
    8777#define GPIO_BSRR_BS10_Pos (10U)
    -
    8778#define GPIO_BSRR_BS10_Msk (0x1UL << GPIO_BSRR_BS10_Pos)
    -
    8779#define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk
    -
    8780#define GPIO_BSRR_BS11_Pos (11U)
    -
    8781#define GPIO_BSRR_BS11_Msk (0x1UL << GPIO_BSRR_BS11_Pos)
    -
    8782#define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk
    -
    8783#define GPIO_BSRR_BS12_Pos (12U)
    -
    8784#define GPIO_BSRR_BS12_Msk (0x1UL << GPIO_BSRR_BS12_Pos)
    -
    8785#define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk
    -
    8786#define GPIO_BSRR_BS13_Pos (13U)
    -
    8787#define GPIO_BSRR_BS13_Msk (0x1UL << GPIO_BSRR_BS13_Pos)
    -
    8788#define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk
    -
    8789#define GPIO_BSRR_BS14_Pos (14U)
    -
    8790#define GPIO_BSRR_BS14_Msk (0x1UL << GPIO_BSRR_BS14_Pos)
    -
    8791#define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk
    -
    8792#define GPIO_BSRR_BS15_Pos (15U)
    -
    8793#define GPIO_BSRR_BS15_Msk (0x1UL << GPIO_BSRR_BS15_Pos)
    -
    8794#define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk
    -
    8795#define GPIO_BSRR_BR0_Pos (16U)
    -
    8796#define GPIO_BSRR_BR0_Msk (0x1UL << GPIO_BSRR_BR0_Pos)
    -
    8797#define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk
    -
    8798#define GPIO_BSRR_BR1_Pos (17U)
    -
    8799#define GPIO_BSRR_BR1_Msk (0x1UL << GPIO_BSRR_BR1_Pos)
    -
    8800#define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk
    -
    8801#define GPIO_BSRR_BR2_Pos (18U)
    -
    8802#define GPIO_BSRR_BR2_Msk (0x1UL << GPIO_BSRR_BR2_Pos)
    -
    8803#define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk
    -
    8804#define GPIO_BSRR_BR3_Pos (19U)
    -
    8805#define GPIO_BSRR_BR3_Msk (0x1UL << GPIO_BSRR_BR3_Pos)
    -
    8806#define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk
    -
    8807#define GPIO_BSRR_BR4_Pos (20U)
    -
    8808#define GPIO_BSRR_BR4_Msk (0x1UL << GPIO_BSRR_BR4_Pos)
    -
    8809#define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk
    -
    8810#define GPIO_BSRR_BR5_Pos (21U)
    -
    8811#define GPIO_BSRR_BR5_Msk (0x1UL << GPIO_BSRR_BR5_Pos)
    -
    8812#define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk
    -
    8813#define GPIO_BSRR_BR6_Pos (22U)
    -
    8814#define GPIO_BSRR_BR6_Msk (0x1UL << GPIO_BSRR_BR6_Pos)
    -
    8815#define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk
    -
    8816#define GPIO_BSRR_BR7_Pos (23U)
    -
    8817#define GPIO_BSRR_BR7_Msk (0x1UL << GPIO_BSRR_BR7_Pos)
    -
    8818#define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk
    -
    8819#define GPIO_BSRR_BR8_Pos (24U)
    -
    8820#define GPIO_BSRR_BR8_Msk (0x1UL << GPIO_BSRR_BR8_Pos)
    -
    8821#define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk
    -
    8822#define GPIO_BSRR_BR9_Pos (25U)
    -
    8823#define GPIO_BSRR_BR9_Msk (0x1UL << GPIO_BSRR_BR9_Pos)
    -
    8824#define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk
    -
    8825#define GPIO_BSRR_BR10_Pos (26U)
    -
    8826#define GPIO_BSRR_BR10_Msk (0x1UL << GPIO_BSRR_BR10_Pos)
    -
    8827#define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk
    -
    8828#define GPIO_BSRR_BR11_Pos (27U)
    -
    8829#define GPIO_BSRR_BR11_Msk (0x1UL << GPIO_BSRR_BR11_Pos)
    -
    8830#define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk
    -
    8831#define GPIO_BSRR_BR12_Pos (28U)
    -
    8832#define GPIO_BSRR_BR12_Msk (0x1UL << GPIO_BSRR_BR12_Pos)
    -
    8833#define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk
    -
    8834#define GPIO_BSRR_BR13_Pos (29U)
    -
    8835#define GPIO_BSRR_BR13_Msk (0x1UL << GPIO_BSRR_BR13_Pos)
    -
    8836#define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk
    -
    8837#define GPIO_BSRR_BR14_Pos (30U)
    -
    8838#define GPIO_BSRR_BR14_Msk (0x1UL << GPIO_BSRR_BR14_Pos)
    -
    8839#define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk
    -
    8840#define GPIO_BSRR_BR15_Pos (31U)
    -
    8841#define GPIO_BSRR_BR15_Msk (0x1UL << GPIO_BSRR_BR15_Pos)
    -
    8842#define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk
    -
    8843
    -
    8844/* Legacy defines */
    -
    8845#define GPIO_BSRR_BS_0 GPIO_BSRR_BS0
    -
    8846#define GPIO_BSRR_BS_1 GPIO_BSRR_BS1
    -
    8847#define GPIO_BSRR_BS_2 GPIO_BSRR_BS2
    -
    8848#define GPIO_BSRR_BS_3 GPIO_BSRR_BS3
    -
    8849#define GPIO_BSRR_BS_4 GPIO_BSRR_BS4
    -
    8850#define GPIO_BSRR_BS_5 GPIO_BSRR_BS5
    -
    8851#define GPIO_BSRR_BS_6 GPIO_BSRR_BS6
    -
    8852#define GPIO_BSRR_BS_7 GPIO_BSRR_BS7
    -
    8853#define GPIO_BSRR_BS_8 GPIO_BSRR_BS8
    -
    8854#define GPIO_BSRR_BS_9 GPIO_BSRR_BS9
    -
    8855#define GPIO_BSRR_BS_10 GPIO_BSRR_BS10
    -
    8856#define GPIO_BSRR_BS_11 GPIO_BSRR_BS11
    -
    8857#define GPIO_BSRR_BS_12 GPIO_BSRR_BS12
    -
    8858#define GPIO_BSRR_BS_13 GPIO_BSRR_BS13
    -
    8859#define GPIO_BSRR_BS_14 GPIO_BSRR_BS14
    -
    8860#define GPIO_BSRR_BS_15 GPIO_BSRR_BS15
    -
    8861#define GPIO_BSRR_BR_0 GPIO_BSRR_BR0
    -
    8862#define GPIO_BSRR_BR_1 GPIO_BSRR_BR1
    -
    8863#define GPIO_BSRR_BR_2 GPIO_BSRR_BR2
    -
    8864#define GPIO_BSRR_BR_3 GPIO_BSRR_BR3
    -
    8865#define GPIO_BSRR_BR_4 GPIO_BSRR_BR4
    -
    8866#define GPIO_BSRR_BR_5 GPIO_BSRR_BR5
    -
    8867#define GPIO_BSRR_BR_6 GPIO_BSRR_BR6
    -
    8868#define GPIO_BSRR_BR_7 GPIO_BSRR_BR7
    -
    8869#define GPIO_BSRR_BR_8 GPIO_BSRR_BR8
    -
    8870#define GPIO_BSRR_BR_9 GPIO_BSRR_BR9
    -
    8871#define GPIO_BSRR_BR_10 GPIO_BSRR_BR10
    -
    8872#define GPIO_BSRR_BR_11 GPIO_BSRR_BR11
    -
    8873#define GPIO_BSRR_BR_12 GPIO_BSRR_BR12
    -
    8874#define GPIO_BSRR_BR_13 GPIO_BSRR_BR13
    -
    8875#define GPIO_BSRR_BR_14 GPIO_BSRR_BR14
    -
    8876#define GPIO_BSRR_BR_15 GPIO_BSRR_BR15
    -
    8877#define GPIO_BRR_BR0 GPIO_BSRR_BR0
    -
    8878#define GPIO_BRR_BR0_Pos GPIO_BSRR_BR0_Pos
    -
    8879#define GPIO_BRR_BR0_Msk GPIO_BSRR_BR0_Msk
    -
    8880#define GPIO_BRR_BR1 GPIO_BSRR_BR1
    -
    8881#define GPIO_BRR_BR1_Pos GPIO_BSRR_BR1_Pos
    -
    8882#define GPIO_BRR_BR1_Msk GPIO_BSRR_BR1_Msk
    -
    8883#define GPIO_BRR_BR2 GPIO_BSRR_BR2
    -
    8884#define GPIO_BRR_BR2_Pos GPIO_BSRR_BR2_Pos
    -
    8885#define GPIO_BRR_BR2_Msk GPIO_BSRR_BR2_Msk
    -
    8886#define GPIO_BRR_BR3 GPIO_BSRR_BR3
    -
    8887#define GPIO_BRR_BR3_Pos GPIO_BSRR_BR3_Pos
    -
    8888#define GPIO_BRR_BR3_Msk GPIO_BSRR_BR3_Msk
    -
    8889#define GPIO_BRR_BR4 GPIO_BSRR_BR4
    -
    8890#define GPIO_BRR_BR4_Pos GPIO_BSRR_BR4_Pos
    -
    8891#define GPIO_BRR_BR4_Msk GPIO_BSRR_BR4_Msk
    -
    8892#define GPIO_BRR_BR5 GPIO_BSRR_BR5
    -
    8893#define GPIO_BRR_BR5_Pos GPIO_BSRR_BR5_Pos
    -
    8894#define GPIO_BRR_BR5_Msk GPIO_BSRR_BR5_Msk
    -
    8895#define GPIO_BRR_BR6 GPIO_BSRR_BR6
    -
    8896#define GPIO_BRR_BR6_Pos GPIO_BSRR_BR6_Pos
    -
    8897#define GPIO_BRR_BR6_Msk GPIO_BSRR_BR6_Msk
    -
    8898#define GPIO_BRR_BR7 GPIO_BSRR_BR7
    -
    8899#define GPIO_BRR_BR7_Pos GPIO_BSRR_BR7_Pos
    -
    8900#define GPIO_BRR_BR7_Msk GPIO_BSRR_BR7_Msk
    -
    8901#define GPIO_BRR_BR8 GPIO_BSRR_BR8
    -
    8902#define GPIO_BRR_BR8_Pos GPIO_BSRR_BR8_Pos
    -
    8903#define GPIO_BRR_BR8_Msk GPIO_BSRR_BR8_Msk
    -
    8904#define GPIO_BRR_BR9 GPIO_BSRR_BR9
    -
    8905#define GPIO_BRR_BR9_Pos GPIO_BSRR_BR9_Pos
    -
    8906#define GPIO_BRR_BR9_Msk GPIO_BSRR_BR9_Msk
    -
    8907#define GPIO_BRR_BR10 GPIO_BSRR_BR10
    -
    8908#define GPIO_BRR_BR10_Pos GPIO_BSRR_BR10_Pos
    -
    8909#define GPIO_BRR_BR10_Msk GPIO_BSRR_BR10_Msk
    -
    8910#define GPIO_BRR_BR11 GPIO_BSRR_BR11
    -
    8911#define GPIO_BRR_BR11_Pos GPIO_BSRR_BR11_Pos
    -
    8912#define GPIO_BRR_BR11_Msk GPIO_BSRR_BR11_Msk
    -
    8913#define GPIO_BRR_BR12 GPIO_BSRR_BR12
    -
    8914#define GPIO_BRR_BR12_Pos GPIO_BSRR_BR12_Pos
    -
    8915#define GPIO_BRR_BR12_Msk GPIO_BSRR_BR12_Msk
    -
    8916#define GPIO_BRR_BR13 GPIO_BSRR_BR13
    -
    8917#define GPIO_BRR_BR13_Pos GPIO_BSRR_BR13_Pos
    -
    8918#define GPIO_BRR_BR13_Msk GPIO_BSRR_BR13_Msk
    -
    8919#define GPIO_BRR_BR14 GPIO_BSRR_BR14
    -
    8920#define GPIO_BRR_BR14_Pos GPIO_BSRR_BR14_Pos
    -
    8921#define GPIO_BRR_BR14_Msk GPIO_BSRR_BR14_Msk
    -
    8922#define GPIO_BRR_BR15 GPIO_BSRR_BR15
    -
    8923#define GPIO_BRR_BR15_Pos GPIO_BSRR_BR15_Pos
    -
    8924#define GPIO_BRR_BR15_Msk GPIO_BSRR_BR15_Msk
    -
    8925/****************** Bit definition for GPIO_LCKR register *********************/
    -
    8926#define GPIO_LCKR_LCK0_Pos (0U)
    -
    8927#define GPIO_LCKR_LCK0_Msk (0x1UL << GPIO_LCKR_LCK0_Pos)
    -
    8928#define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk
    -
    8929#define GPIO_LCKR_LCK1_Pos (1U)
    -
    8930#define GPIO_LCKR_LCK1_Msk (0x1UL << GPIO_LCKR_LCK1_Pos)
    -
    8931#define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk
    -
    8932#define GPIO_LCKR_LCK2_Pos (2U)
    -
    8933#define GPIO_LCKR_LCK2_Msk (0x1UL << GPIO_LCKR_LCK2_Pos)
    -
    8934#define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk
    -
    8935#define GPIO_LCKR_LCK3_Pos (3U)
    -
    8936#define GPIO_LCKR_LCK3_Msk (0x1UL << GPIO_LCKR_LCK3_Pos)
    -
    8937#define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk
    -
    8938#define GPIO_LCKR_LCK4_Pos (4U)
    -
    8939#define GPIO_LCKR_LCK4_Msk (0x1UL << GPIO_LCKR_LCK4_Pos)
    -
    8940#define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk
    -
    8941#define GPIO_LCKR_LCK5_Pos (5U)
    -
    8942#define GPIO_LCKR_LCK5_Msk (0x1UL << GPIO_LCKR_LCK5_Pos)
    -
    8943#define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk
    -
    8944#define GPIO_LCKR_LCK6_Pos (6U)
    -
    8945#define GPIO_LCKR_LCK6_Msk (0x1UL << GPIO_LCKR_LCK6_Pos)
    -
    8946#define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk
    -
    8947#define GPIO_LCKR_LCK7_Pos (7U)
    -
    8948#define GPIO_LCKR_LCK7_Msk (0x1UL << GPIO_LCKR_LCK7_Pos)
    -
    8949#define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk
    -
    8950#define GPIO_LCKR_LCK8_Pos (8U)
    -
    8951#define GPIO_LCKR_LCK8_Msk (0x1UL << GPIO_LCKR_LCK8_Pos)
    -
    8952#define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk
    -
    8953#define GPIO_LCKR_LCK9_Pos (9U)
    -
    8954#define GPIO_LCKR_LCK9_Msk (0x1UL << GPIO_LCKR_LCK9_Pos)
    -
    8955#define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk
    -
    8956#define GPIO_LCKR_LCK10_Pos (10U)
    -
    8957#define GPIO_LCKR_LCK10_Msk (0x1UL << GPIO_LCKR_LCK10_Pos)
    -
    8958#define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk
    -
    8959#define GPIO_LCKR_LCK11_Pos (11U)
    -
    8960#define GPIO_LCKR_LCK11_Msk (0x1UL << GPIO_LCKR_LCK11_Pos)
    -
    8961#define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk
    -
    8962#define GPIO_LCKR_LCK12_Pos (12U)
    -
    8963#define GPIO_LCKR_LCK12_Msk (0x1UL << GPIO_LCKR_LCK12_Pos)
    -
    8964#define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk
    -
    8965#define GPIO_LCKR_LCK13_Pos (13U)
    -
    8966#define GPIO_LCKR_LCK13_Msk (0x1UL << GPIO_LCKR_LCK13_Pos)
    -
    8967#define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk
    -
    8968#define GPIO_LCKR_LCK14_Pos (14U)
    -
    8969#define GPIO_LCKR_LCK14_Msk (0x1UL << GPIO_LCKR_LCK14_Pos)
    -
    8970#define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk
    -
    8971#define GPIO_LCKR_LCK15_Pos (15U)
    -
    8972#define GPIO_LCKR_LCK15_Msk (0x1UL << GPIO_LCKR_LCK15_Pos)
    -
    8973#define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk
    -
    8974#define GPIO_LCKR_LCKK_Pos (16U)
    -
    8975#define GPIO_LCKR_LCKK_Msk (0x1UL << GPIO_LCKR_LCKK_Pos)
    -
    8976#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk
    -
    8977/****************** Bit definition for GPIO_AFRL register *********************/
    -
    8978#define GPIO_AFRL_AFSEL0_Pos (0U)
    -
    8979#define GPIO_AFRL_AFSEL0_Msk (0xFUL << GPIO_AFRL_AFSEL0_Pos)
    -
    8980#define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk
    -
    8981#define GPIO_AFRL_AFSEL0_0 (0x1UL << GPIO_AFRL_AFSEL0_Pos)
    -
    8982#define GPIO_AFRL_AFSEL0_1 (0x2UL << GPIO_AFRL_AFSEL0_Pos)
    -
    8983#define GPIO_AFRL_AFSEL0_2 (0x4UL << GPIO_AFRL_AFSEL0_Pos)
    -
    8984#define GPIO_AFRL_AFSEL0_3 (0x8UL << GPIO_AFRL_AFSEL0_Pos)
    -
    8985#define GPIO_AFRL_AFSEL1_Pos (4U)
    -
    8986#define GPIO_AFRL_AFSEL1_Msk (0xFUL << GPIO_AFRL_AFSEL1_Pos)
    -
    8987#define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk
    -
    8988#define GPIO_AFRL_AFSEL1_0 (0x1UL << GPIO_AFRL_AFSEL1_Pos)
    -
    8989#define GPIO_AFRL_AFSEL1_1 (0x2UL << GPIO_AFRL_AFSEL1_Pos)
    -
    8990#define GPIO_AFRL_AFSEL1_2 (0x4UL << GPIO_AFRL_AFSEL1_Pos)
    -
    8991#define GPIO_AFRL_AFSEL1_3 (0x8UL << GPIO_AFRL_AFSEL1_Pos)
    -
    8992#define GPIO_AFRL_AFSEL2_Pos (8U)
    -
    8993#define GPIO_AFRL_AFSEL2_Msk (0xFUL << GPIO_AFRL_AFSEL2_Pos)
    -
    8994#define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk
    -
    8995#define GPIO_AFRL_AFSEL2_0 (0x1UL << GPIO_AFRL_AFSEL2_Pos)
    -
    8996#define GPIO_AFRL_AFSEL2_1 (0x2UL << GPIO_AFRL_AFSEL2_Pos)
    -
    8997#define GPIO_AFRL_AFSEL2_2 (0x4UL << GPIO_AFRL_AFSEL2_Pos)
    -
    8998#define GPIO_AFRL_AFSEL2_3 (0x8UL << GPIO_AFRL_AFSEL2_Pos)
    -
    8999#define GPIO_AFRL_AFSEL3_Pos (12U)
    -
    9000#define GPIO_AFRL_AFSEL3_Msk (0xFUL << GPIO_AFRL_AFSEL3_Pos)
    -
    9001#define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk
    -
    9002#define GPIO_AFRL_AFSEL3_0 (0x1UL << GPIO_AFRL_AFSEL3_Pos)
    -
    9003#define GPIO_AFRL_AFSEL3_1 (0x2UL << GPIO_AFRL_AFSEL3_Pos)
    -
    9004#define GPIO_AFRL_AFSEL3_2 (0x4UL << GPIO_AFRL_AFSEL3_Pos)
    -
    9005#define GPIO_AFRL_AFSEL3_3 (0x8UL << GPIO_AFRL_AFSEL3_Pos)
    -
    9006#define GPIO_AFRL_AFSEL4_Pos (16U)
    -
    9007#define GPIO_AFRL_AFSEL4_Msk (0xFUL << GPIO_AFRL_AFSEL4_Pos)
    -
    9008#define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk
    -
    9009#define GPIO_AFRL_AFSEL4_0 (0x1UL << GPIO_AFRL_AFSEL4_Pos)
    -
    9010#define GPIO_AFRL_AFSEL4_1 (0x2UL << GPIO_AFRL_AFSEL4_Pos)
    -
    9011#define GPIO_AFRL_AFSEL4_2 (0x4UL << GPIO_AFRL_AFSEL4_Pos)
    -
    9012#define GPIO_AFRL_AFSEL4_3 (0x8UL << GPIO_AFRL_AFSEL4_Pos)
    -
    9013#define GPIO_AFRL_AFSEL5_Pos (20U)
    -
    9014#define GPIO_AFRL_AFSEL5_Msk (0xFUL << GPIO_AFRL_AFSEL5_Pos)
    -
    9015#define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk
    -
    9016#define GPIO_AFRL_AFSEL5_0 (0x1UL << GPIO_AFRL_AFSEL5_Pos)
    -
    9017#define GPIO_AFRL_AFSEL5_1 (0x2UL << GPIO_AFRL_AFSEL5_Pos)
    -
    9018#define GPIO_AFRL_AFSEL5_2 (0x4UL << GPIO_AFRL_AFSEL5_Pos)
    -
    9019#define GPIO_AFRL_AFSEL5_3 (0x8UL << GPIO_AFRL_AFSEL5_Pos)
    -
    9020#define GPIO_AFRL_AFSEL6_Pos (24U)
    -
    9021#define GPIO_AFRL_AFSEL6_Msk (0xFUL << GPIO_AFRL_AFSEL6_Pos)
    -
    9022#define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk
    -
    9023#define GPIO_AFRL_AFSEL6_0 (0x1UL << GPIO_AFRL_AFSEL6_Pos)
    -
    9024#define GPIO_AFRL_AFSEL6_1 (0x2UL << GPIO_AFRL_AFSEL6_Pos)
    -
    9025#define GPIO_AFRL_AFSEL6_2 (0x4UL << GPIO_AFRL_AFSEL6_Pos)
    -
    9026#define GPIO_AFRL_AFSEL6_3 (0x8UL << GPIO_AFRL_AFSEL6_Pos)
    -
    9027#define GPIO_AFRL_AFSEL7_Pos (28U)
    -
    9028#define GPIO_AFRL_AFSEL7_Msk (0xFUL << GPIO_AFRL_AFSEL7_Pos)
    -
    9029#define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk
    -
    9030#define GPIO_AFRL_AFSEL7_0 (0x1UL << GPIO_AFRL_AFSEL7_Pos)
    -
    9031#define GPIO_AFRL_AFSEL7_1 (0x2UL << GPIO_AFRL_AFSEL7_Pos)
    -
    9032#define GPIO_AFRL_AFSEL7_2 (0x4UL << GPIO_AFRL_AFSEL7_Pos)
    -
    9033#define GPIO_AFRL_AFSEL7_3 (0x8UL << GPIO_AFRL_AFSEL7_Pos)
    -
    9035/* Legacy defines */
    -
    9036#define GPIO_AFRL_AFRL0 GPIO_AFRL_AFSEL0
    -
    9037#define GPIO_AFRL_AFRL0_0 GPIO_AFRL_AFSEL0_0
    -
    9038#define GPIO_AFRL_AFRL0_1 GPIO_AFRL_AFSEL0_1
    -
    9039#define GPIO_AFRL_AFRL0_2 GPIO_AFRL_AFSEL0_2
    -
    9040#define GPIO_AFRL_AFRL0_3 GPIO_AFRL_AFSEL0_3
    -
    9041#define GPIO_AFRL_AFRL1 GPIO_AFRL_AFSEL1
    -
    9042#define GPIO_AFRL_AFRL1_0 GPIO_AFRL_AFSEL1_0
    -
    9043#define GPIO_AFRL_AFRL1_1 GPIO_AFRL_AFSEL1_1
    -
    9044#define GPIO_AFRL_AFRL1_2 GPIO_AFRL_AFSEL1_2
    -
    9045#define GPIO_AFRL_AFRL1_3 GPIO_AFRL_AFSEL1_3
    -
    9046#define GPIO_AFRL_AFRL2 GPIO_AFRL_AFSEL2
    -
    9047#define GPIO_AFRL_AFRL2_0 GPIO_AFRL_AFSEL2_0
    -
    9048#define GPIO_AFRL_AFRL2_1 GPIO_AFRL_AFSEL2_1
    -
    9049#define GPIO_AFRL_AFRL2_2 GPIO_AFRL_AFSEL2_2
    -
    9050#define GPIO_AFRL_AFRL2_3 GPIO_AFRL_AFSEL2_3
    -
    9051#define GPIO_AFRL_AFRL3 GPIO_AFRL_AFSEL3
    -
    9052#define GPIO_AFRL_AFRL3_0 GPIO_AFRL_AFSEL3_0
    -
    9053#define GPIO_AFRL_AFRL3_1 GPIO_AFRL_AFSEL3_1
    -
    9054#define GPIO_AFRL_AFRL3_2 GPIO_AFRL_AFSEL3_2
    -
    9055#define GPIO_AFRL_AFRL3_3 GPIO_AFRL_AFSEL3_3
    -
    9056#define GPIO_AFRL_AFRL4 GPIO_AFRL_AFSEL4
    -
    9057#define GPIO_AFRL_AFRL4_0 GPIO_AFRL_AFSEL4_0
    -
    9058#define GPIO_AFRL_AFRL4_1 GPIO_AFRL_AFSEL4_1
    -
    9059#define GPIO_AFRL_AFRL4_2 GPIO_AFRL_AFSEL4_2
    -
    9060#define GPIO_AFRL_AFRL4_3 GPIO_AFRL_AFSEL4_3
    -
    9061#define GPIO_AFRL_AFRL5 GPIO_AFRL_AFSEL5
    -
    9062#define GPIO_AFRL_AFRL5_0 GPIO_AFRL_AFSEL5_0
    -
    9063#define GPIO_AFRL_AFRL5_1 GPIO_AFRL_AFSEL5_1
    -
    9064#define GPIO_AFRL_AFRL5_2 GPIO_AFRL_AFSEL5_2
    -
    9065#define GPIO_AFRL_AFRL5_3 GPIO_AFRL_AFSEL5_3
    -
    9066#define GPIO_AFRL_AFRL6 GPIO_AFRL_AFSEL6
    -
    9067#define GPIO_AFRL_AFRL6_0 GPIO_AFRL_AFSEL6_0
    -
    9068#define GPIO_AFRL_AFRL6_1 GPIO_AFRL_AFSEL6_1
    -
    9069#define GPIO_AFRL_AFRL6_2 GPIO_AFRL_AFSEL6_2
    -
    9070#define GPIO_AFRL_AFRL6_3 GPIO_AFRL_AFSEL6_3
    -
    9071#define GPIO_AFRL_AFRL7 GPIO_AFRL_AFSEL7
    -
    9072#define GPIO_AFRL_AFRL7_0 GPIO_AFRL_AFSEL7_0
    -
    9073#define GPIO_AFRL_AFRL7_1 GPIO_AFRL_AFSEL7_1
    -
    9074#define GPIO_AFRL_AFRL7_2 GPIO_AFRL_AFSEL7_2
    -
    9075#define GPIO_AFRL_AFRL7_3 GPIO_AFRL_AFSEL7_3
    -
    9076
    -
    9077/****************** Bit definition for GPIO_AFRH register *********************/
    -
    9078#define GPIO_AFRH_AFSEL8_Pos (0U)
    -
    9079#define GPIO_AFRH_AFSEL8_Msk (0xFUL << GPIO_AFRH_AFSEL8_Pos)
    -
    9080#define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk
    -
    9081#define GPIO_AFRH_AFSEL8_0 (0x1UL << GPIO_AFRH_AFSEL8_Pos)
    -
    9082#define GPIO_AFRH_AFSEL8_1 (0x2UL << GPIO_AFRH_AFSEL8_Pos)
    -
    9083#define GPIO_AFRH_AFSEL8_2 (0x4UL << GPIO_AFRH_AFSEL8_Pos)
    -
    9084#define GPIO_AFRH_AFSEL8_3 (0x8UL << GPIO_AFRH_AFSEL8_Pos)
    -
    9085#define GPIO_AFRH_AFSEL9_Pos (4U)
    -
    9086#define GPIO_AFRH_AFSEL9_Msk (0xFUL << GPIO_AFRH_AFSEL9_Pos)
    -
    9087#define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk
    -
    9088#define GPIO_AFRH_AFSEL9_0 (0x1UL << GPIO_AFRH_AFSEL9_Pos)
    -
    9089#define GPIO_AFRH_AFSEL9_1 (0x2UL << GPIO_AFRH_AFSEL9_Pos)
    -
    9090#define GPIO_AFRH_AFSEL9_2 (0x4UL << GPIO_AFRH_AFSEL9_Pos)
    -
    9091#define GPIO_AFRH_AFSEL9_3 (0x8UL << GPIO_AFRH_AFSEL9_Pos)
    -
    9092#define GPIO_AFRH_AFSEL10_Pos (8U)
    -
    9093#define GPIO_AFRH_AFSEL10_Msk (0xFUL << GPIO_AFRH_AFSEL10_Pos)
    -
    9094#define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk
    -
    9095#define GPIO_AFRH_AFSEL10_0 (0x1UL << GPIO_AFRH_AFSEL10_Pos)
    -
    9096#define GPIO_AFRH_AFSEL10_1 (0x2UL << GPIO_AFRH_AFSEL10_Pos)
    -
    9097#define GPIO_AFRH_AFSEL10_2 (0x4UL << GPIO_AFRH_AFSEL10_Pos)
    -
    9098#define GPIO_AFRH_AFSEL10_3 (0x8UL << GPIO_AFRH_AFSEL10_Pos)
    -
    9099#define GPIO_AFRH_AFSEL11_Pos (12U)
    -
    9100#define GPIO_AFRH_AFSEL11_Msk (0xFUL << GPIO_AFRH_AFSEL11_Pos)
    -
    9101#define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk
    -
    9102#define GPIO_AFRH_AFSEL11_0 (0x1UL << GPIO_AFRH_AFSEL11_Pos)
    -
    9103#define GPIO_AFRH_AFSEL11_1 (0x2UL << GPIO_AFRH_AFSEL11_Pos)
    -
    9104#define GPIO_AFRH_AFSEL11_2 (0x4UL << GPIO_AFRH_AFSEL11_Pos)
    -
    9105#define GPIO_AFRH_AFSEL11_3 (0x8UL << GPIO_AFRH_AFSEL11_Pos)
    -
    9106#define GPIO_AFRH_AFSEL12_Pos (16U)
    -
    9107#define GPIO_AFRH_AFSEL12_Msk (0xFUL << GPIO_AFRH_AFSEL12_Pos)
    -
    9108#define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk
    -
    9109#define GPIO_AFRH_AFSEL12_0 (0x1UL << GPIO_AFRH_AFSEL12_Pos)
    -
    9110#define GPIO_AFRH_AFSEL12_1 (0x2UL << GPIO_AFRH_AFSEL12_Pos)
    -
    9111#define GPIO_AFRH_AFSEL12_2 (0x4UL << GPIO_AFRH_AFSEL12_Pos)
    -
    9112#define GPIO_AFRH_AFSEL12_3 (0x8UL << GPIO_AFRH_AFSEL12_Pos)
    -
    9113#define GPIO_AFRH_AFSEL13_Pos (20U)
    -
    9114#define GPIO_AFRH_AFSEL13_Msk (0xFUL << GPIO_AFRH_AFSEL13_Pos)
    -
    9115#define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk
    -
    9116#define GPIO_AFRH_AFSEL13_0 (0x1UL << GPIO_AFRH_AFSEL13_Pos)
    -
    9117#define GPIO_AFRH_AFSEL13_1 (0x2UL << GPIO_AFRH_AFSEL13_Pos)
    -
    9118#define GPIO_AFRH_AFSEL13_2 (0x4UL << GPIO_AFRH_AFSEL13_Pos)
    -
    9119#define GPIO_AFRH_AFSEL13_3 (0x8UL << GPIO_AFRH_AFSEL13_Pos)
    -
    9120#define GPIO_AFRH_AFSEL14_Pos (24U)
    -
    9121#define GPIO_AFRH_AFSEL14_Msk (0xFUL << GPIO_AFRH_AFSEL14_Pos)
    -
    9122#define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk
    -
    9123#define GPIO_AFRH_AFSEL14_0 (0x1UL << GPIO_AFRH_AFSEL14_Pos)
    -
    9124#define GPIO_AFRH_AFSEL14_1 (0x2UL << GPIO_AFRH_AFSEL14_Pos)
    -
    9125#define GPIO_AFRH_AFSEL14_2 (0x4UL << GPIO_AFRH_AFSEL14_Pos)
    -
    9126#define GPIO_AFRH_AFSEL14_3 (0x8UL << GPIO_AFRH_AFSEL14_Pos)
    -
    9127#define GPIO_AFRH_AFSEL15_Pos (28U)
    -
    9128#define GPIO_AFRH_AFSEL15_Msk (0xFUL << GPIO_AFRH_AFSEL15_Pos)
    -
    9129#define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk
    -
    9130#define GPIO_AFRH_AFSEL15_0 (0x1UL << GPIO_AFRH_AFSEL15_Pos)
    -
    9131#define GPIO_AFRH_AFSEL15_1 (0x2UL << GPIO_AFRH_AFSEL15_Pos)
    -
    9132#define GPIO_AFRH_AFSEL15_2 (0x4UL << GPIO_AFRH_AFSEL15_Pos)
    -
    9133#define GPIO_AFRH_AFSEL15_3 (0x8UL << GPIO_AFRH_AFSEL15_Pos)
    -
    9135/* Legacy defines */
    -
    9136#define GPIO_AFRH_AFRH0 GPIO_AFRH_AFSEL8
    -
    9137#define GPIO_AFRH_AFRH0_0 GPIO_AFRH_AFSEL8_0
    -
    9138#define GPIO_AFRH_AFRH0_1 GPIO_AFRH_AFSEL8_1
    -
    9139#define GPIO_AFRH_AFRH0_2 GPIO_AFRH_AFSEL8_2
    -
    9140#define GPIO_AFRH_AFRH0_3 GPIO_AFRH_AFSEL8_3
    -
    9141#define GPIO_AFRH_AFRH1 GPIO_AFRH_AFSEL9
    -
    9142#define GPIO_AFRH_AFRH1_0 GPIO_AFRH_AFSEL9_0
    -
    9143#define GPIO_AFRH_AFRH1_1 GPIO_AFRH_AFSEL9_1
    -
    9144#define GPIO_AFRH_AFRH1_2 GPIO_AFRH_AFSEL9_2
    -
    9145#define GPIO_AFRH_AFRH1_3 GPIO_AFRH_AFSEL9_3
    -
    9146#define GPIO_AFRH_AFRH2 GPIO_AFRH_AFSEL10
    -
    9147#define GPIO_AFRH_AFRH2_0 GPIO_AFRH_AFSEL10_0
    -
    9148#define GPIO_AFRH_AFRH2_1 GPIO_AFRH_AFSEL10_1
    -
    9149#define GPIO_AFRH_AFRH2_2 GPIO_AFRH_AFSEL10_2
    -
    9150#define GPIO_AFRH_AFRH2_3 GPIO_AFRH_AFSEL10_3
    -
    9151#define GPIO_AFRH_AFRH3 GPIO_AFRH_AFSEL11
    -
    9152#define GPIO_AFRH_AFRH3_0 GPIO_AFRH_AFSEL11_0
    -
    9153#define GPIO_AFRH_AFRH3_1 GPIO_AFRH_AFSEL11_1
    -
    9154#define GPIO_AFRH_AFRH3_2 GPIO_AFRH_AFSEL11_2
    -
    9155#define GPIO_AFRH_AFRH3_3 GPIO_AFRH_AFSEL11_3
    -
    9156#define GPIO_AFRH_AFRH4 GPIO_AFRH_AFSEL12
    -
    9157#define GPIO_AFRH_AFRH4_0 GPIO_AFRH_AFSEL12_0
    -
    9158#define GPIO_AFRH_AFRH4_1 GPIO_AFRH_AFSEL12_1
    -
    9159#define GPIO_AFRH_AFRH4_2 GPIO_AFRH_AFSEL12_2
    -
    9160#define GPIO_AFRH_AFRH4_3 GPIO_AFRH_AFSEL12_3
    -
    9161#define GPIO_AFRH_AFRH5 GPIO_AFRH_AFSEL13
    -
    9162#define GPIO_AFRH_AFRH5_0 GPIO_AFRH_AFSEL13_0
    -
    9163#define GPIO_AFRH_AFRH5_1 GPIO_AFRH_AFSEL13_1
    -
    9164#define GPIO_AFRH_AFRH5_2 GPIO_AFRH_AFSEL13_2
    -
    9165#define GPIO_AFRH_AFRH5_3 GPIO_AFRH_AFSEL13_3
    -
    9166#define GPIO_AFRH_AFRH6 GPIO_AFRH_AFSEL14
    -
    9167#define GPIO_AFRH_AFRH6_0 GPIO_AFRH_AFSEL14_0
    -
    9168#define GPIO_AFRH_AFRH6_1 GPIO_AFRH_AFSEL14_1
    -
    9169#define GPIO_AFRH_AFRH6_2 GPIO_AFRH_AFSEL14_2
    -
    9170#define GPIO_AFRH_AFRH6_3 GPIO_AFRH_AFSEL14_3
    -
    9171#define GPIO_AFRH_AFRH7 GPIO_AFRH_AFSEL15
    -
    9172#define GPIO_AFRH_AFRH7_0 GPIO_AFRH_AFSEL15_0
    -
    9173#define GPIO_AFRH_AFRH7_1 GPIO_AFRH_AFSEL15_1
    -
    9174#define GPIO_AFRH_AFRH7_2 GPIO_AFRH_AFSEL15_2
    -
    9175#define GPIO_AFRH_AFRH7_3 GPIO_AFRH_AFSEL15_3
    -
    9176
    -
    9177
    -
    9178/******************************************************************************/
    -
    9179/* */
    -
    9180/* Inter-integrated Circuit Interface */
    -
    9181/* */
    -
    9182/******************************************************************************/
    -
    9183/******************* Bit definition for I2C_CR1 register ********************/
    -
    9184#define I2C_CR1_PE_Pos (0U)
    -
    9185#define I2C_CR1_PE_Msk (0x1UL << I2C_CR1_PE_Pos)
    -
    9186#define I2C_CR1_PE I2C_CR1_PE_Msk
    -
    9187#define I2C_CR1_SMBUS_Pos (1U)
    -
    9188#define I2C_CR1_SMBUS_Msk (0x1UL << I2C_CR1_SMBUS_Pos)
    -
    9189#define I2C_CR1_SMBUS I2C_CR1_SMBUS_Msk
    -
    9190#define I2C_CR1_SMBTYPE_Pos (3U)
    -
    9191#define I2C_CR1_SMBTYPE_Msk (0x1UL << I2C_CR1_SMBTYPE_Pos)
    -
    9192#define I2C_CR1_SMBTYPE I2C_CR1_SMBTYPE_Msk
    -
    9193#define I2C_CR1_ENARP_Pos (4U)
    -
    9194#define I2C_CR1_ENARP_Msk (0x1UL << I2C_CR1_ENARP_Pos)
    -
    9195#define I2C_CR1_ENARP I2C_CR1_ENARP_Msk
    -
    9196#define I2C_CR1_ENPEC_Pos (5U)
    -
    9197#define I2C_CR1_ENPEC_Msk (0x1UL << I2C_CR1_ENPEC_Pos)
    -
    9198#define I2C_CR1_ENPEC I2C_CR1_ENPEC_Msk
    -
    9199#define I2C_CR1_ENGC_Pos (6U)
    -
    9200#define I2C_CR1_ENGC_Msk (0x1UL << I2C_CR1_ENGC_Pos)
    -
    9201#define I2C_CR1_ENGC I2C_CR1_ENGC_Msk
    -
    9202#define I2C_CR1_NOSTRETCH_Pos (7U)
    -
    9203#define I2C_CR1_NOSTRETCH_Msk (0x1UL << I2C_CR1_NOSTRETCH_Pos)
    -
    9204#define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk
    -
    9205#define I2C_CR1_START_Pos (8U)
    -
    9206#define I2C_CR1_START_Msk (0x1UL << I2C_CR1_START_Pos)
    -
    9207#define I2C_CR1_START I2C_CR1_START_Msk
    -
    9208#define I2C_CR1_STOP_Pos (9U)
    -
    9209#define I2C_CR1_STOP_Msk (0x1UL << I2C_CR1_STOP_Pos)
    -
    9210#define I2C_CR1_STOP I2C_CR1_STOP_Msk
    -
    9211#define I2C_CR1_ACK_Pos (10U)
    -
    9212#define I2C_CR1_ACK_Msk (0x1UL << I2C_CR1_ACK_Pos)
    -
    9213#define I2C_CR1_ACK I2C_CR1_ACK_Msk
    -
    9214#define I2C_CR1_POS_Pos (11U)
    -
    9215#define I2C_CR1_POS_Msk (0x1UL << I2C_CR1_POS_Pos)
    -
    9216#define I2C_CR1_POS I2C_CR1_POS_Msk
    -
    9217#define I2C_CR1_PEC_Pos (12U)
    -
    9218#define I2C_CR1_PEC_Msk (0x1UL << I2C_CR1_PEC_Pos)
    -
    9219#define I2C_CR1_PEC I2C_CR1_PEC_Msk
    -
    9220#define I2C_CR1_ALERT_Pos (13U)
    -
    9221#define I2C_CR1_ALERT_Msk (0x1UL << I2C_CR1_ALERT_Pos)
    -
    9222#define I2C_CR1_ALERT I2C_CR1_ALERT_Msk
    -
    9223#define I2C_CR1_SWRST_Pos (15U)
    -
    9224#define I2C_CR1_SWRST_Msk (0x1UL << I2C_CR1_SWRST_Pos)
    -
    9225#define I2C_CR1_SWRST I2C_CR1_SWRST_Msk
    -
    9227/******************* Bit definition for I2C_CR2 register ********************/
    -
    9228#define I2C_CR2_FREQ_Pos (0U)
    -
    9229#define I2C_CR2_FREQ_Msk (0x3FUL << I2C_CR2_FREQ_Pos)
    -
    9230#define I2C_CR2_FREQ I2C_CR2_FREQ_Msk
    -
    9231#define I2C_CR2_FREQ_0 (0x01UL << I2C_CR2_FREQ_Pos)
    -
    9232#define I2C_CR2_FREQ_1 (0x02UL << I2C_CR2_FREQ_Pos)
    -
    9233#define I2C_CR2_FREQ_2 (0x04UL << I2C_CR2_FREQ_Pos)
    -
    9234#define I2C_CR2_FREQ_3 (0x08UL << I2C_CR2_FREQ_Pos)
    -
    9235#define I2C_CR2_FREQ_4 (0x10UL << I2C_CR2_FREQ_Pos)
    -
    9236#define I2C_CR2_FREQ_5 (0x20UL << I2C_CR2_FREQ_Pos)
    -
    9238#define I2C_CR2_ITERREN_Pos (8U)
    -
    9239#define I2C_CR2_ITERREN_Msk (0x1UL << I2C_CR2_ITERREN_Pos)
    -
    9240#define I2C_CR2_ITERREN I2C_CR2_ITERREN_Msk
    -
    9241#define I2C_CR2_ITEVTEN_Pos (9U)
    -
    9242#define I2C_CR2_ITEVTEN_Msk (0x1UL << I2C_CR2_ITEVTEN_Pos)
    -
    9243#define I2C_CR2_ITEVTEN I2C_CR2_ITEVTEN_Msk
    -
    9244#define I2C_CR2_ITBUFEN_Pos (10U)
    -
    9245#define I2C_CR2_ITBUFEN_Msk (0x1UL << I2C_CR2_ITBUFEN_Pos)
    -
    9246#define I2C_CR2_ITBUFEN I2C_CR2_ITBUFEN_Msk
    -
    9247#define I2C_CR2_DMAEN_Pos (11U)
    -
    9248#define I2C_CR2_DMAEN_Msk (0x1UL << I2C_CR2_DMAEN_Pos)
    -
    9249#define I2C_CR2_DMAEN I2C_CR2_DMAEN_Msk
    -
    9250#define I2C_CR2_LAST_Pos (12U)
    -
    9251#define I2C_CR2_LAST_Msk (0x1UL << I2C_CR2_LAST_Pos)
    -
    9252#define I2C_CR2_LAST I2C_CR2_LAST_Msk
    -
    9254/******************* Bit definition for I2C_OAR1 register *******************/
    -
    9255#define I2C_OAR1_ADD1_7 0x000000FEU
    -
    9256#define I2C_OAR1_ADD8_9 0x00000300U
    -
    9258#define I2C_OAR1_ADD0_Pos (0U)
    -
    9259#define I2C_OAR1_ADD0_Msk (0x1UL << I2C_OAR1_ADD0_Pos)
    -
    9260#define I2C_OAR1_ADD0 I2C_OAR1_ADD0_Msk
    -
    9261#define I2C_OAR1_ADD1_Pos (1U)
    -
    9262#define I2C_OAR1_ADD1_Msk (0x1UL << I2C_OAR1_ADD1_Pos)
    -
    9263#define I2C_OAR1_ADD1 I2C_OAR1_ADD1_Msk
    -
    9264#define I2C_OAR1_ADD2_Pos (2U)
    -
    9265#define I2C_OAR1_ADD2_Msk (0x1UL << I2C_OAR1_ADD2_Pos)
    -
    9266#define I2C_OAR1_ADD2 I2C_OAR1_ADD2_Msk
    -
    9267#define I2C_OAR1_ADD3_Pos (3U)
    -
    9268#define I2C_OAR1_ADD3_Msk (0x1UL << I2C_OAR1_ADD3_Pos)
    -
    9269#define I2C_OAR1_ADD3 I2C_OAR1_ADD3_Msk
    -
    9270#define I2C_OAR1_ADD4_Pos (4U)
    -
    9271#define I2C_OAR1_ADD4_Msk (0x1UL << I2C_OAR1_ADD4_Pos)
    -
    9272#define I2C_OAR1_ADD4 I2C_OAR1_ADD4_Msk
    -
    9273#define I2C_OAR1_ADD5_Pos (5U)
    -
    9274#define I2C_OAR1_ADD5_Msk (0x1UL << I2C_OAR1_ADD5_Pos)
    -
    9275#define I2C_OAR1_ADD5 I2C_OAR1_ADD5_Msk
    -
    9276#define I2C_OAR1_ADD6_Pos (6U)
    -
    9277#define I2C_OAR1_ADD6_Msk (0x1UL << I2C_OAR1_ADD6_Pos)
    -
    9278#define I2C_OAR1_ADD6 I2C_OAR1_ADD6_Msk
    -
    9279#define I2C_OAR1_ADD7_Pos (7U)
    -
    9280#define I2C_OAR1_ADD7_Msk (0x1UL << I2C_OAR1_ADD7_Pos)
    -
    9281#define I2C_OAR1_ADD7 I2C_OAR1_ADD7_Msk
    -
    9282#define I2C_OAR1_ADD8_Pos (8U)
    -
    9283#define I2C_OAR1_ADD8_Msk (0x1UL << I2C_OAR1_ADD8_Pos)
    -
    9284#define I2C_OAR1_ADD8 I2C_OAR1_ADD8_Msk
    -
    9285#define I2C_OAR1_ADD9_Pos (9U)
    -
    9286#define I2C_OAR1_ADD9_Msk (0x1UL << I2C_OAR1_ADD9_Pos)
    -
    9287#define I2C_OAR1_ADD9 I2C_OAR1_ADD9_Msk
    -
    9289#define I2C_OAR1_ADDMODE_Pos (15U)
    -
    9290#define I2C_OAR1_ADDMODE_Msk (0x1UL << I2C_OAR1_ADDMODE_Pos)
    -
    9291#define I2C_OAR1_ADDMODE I2C_OAR1_ADDMODE_Msk
    -
    9293/******************* Bit definition for I2C_OAR2 register *******************/
    -
    9294#define I2C_OAR2_ENDUAL_Pos (0U)
    -
    9295#define I2C_OAR2_ENDUAL_Msk (0x1UL << I2C_OAR2_ENDUAL_Pos)
    -
    9296#define I2C_OAR2_ENDUAL I2C_OAR2_ENDUAL_Msk
    -
    9297#define I2C_OAR2_ADD2_Pos (1U)
    -
    9298#define I2C_OAR2_ADD2_Msk (0x7FUL << I2C_OAR2_ADD2_Pos)
    -
    9299#define I2C_OAR2_ADD2 I2C_OAR2_ADD2_Msk
    -
    9301/******************** Bit definition for I2C_DR register ********************/
    -
    9302#define I2C_DR_DR_Pos (0U)
    -
    9303#define I2C_DR_DR_Msk (0xFFUL << I2C_DR_DR_Pos)
    -
    9304#define I2C_DR_DR I2C_DR_DR_Msk
    -
    9306/******************* Bit definition for I2C_SR1 register ********************/
    -
    9307#define I2C_SR1_SB_Pos (0U)
    -
    9308#define I2C_SR1_SB_Msk (0x1UL << I2C_SR1_SB_Pos)
    -
    9309#define I2C_SR1_SB I2C_SR1_SB_Msk
    -
    9310#define I2C_SR1_ADDR_Pos (1U)
    -
    9311#define I2C_SR1_ADDR_Msk (0x1UL << I2C_SR1_ADDR_Pos)
    -
    9312#define I2C_SR1_ADDR I2C_SR1_ADDR_Msk
    -
    9313#define I2C_SR1_BTF_Pos (2U)
    -
    9314#define I2C_SR1_BTF_Msk (0x1UL << I2C_SR1_BTF_Pos)
    -
    9315#define I2C_SR1_BTF I2C_SR1_BTF_Msk
    -
    9316#define I2C_SR1_ADD10_Pos (3U)
    -
    9317#define I2C_SR1_ADD10_Msk (0x1UL << I2C_SR1_ADD10_Pos)
    -
    9318#define I2C_SR1_ADD10 I2C_SR1_ADD10_Msk
    -
    9319#define I2C_SR1_STOPF_Pos (4U)
    -
    9320#define I2C_SR1_STOPF_Msk (0x1UL << I2C_SR1_STOPF_Pos)
    -
    9321#define I2C_SR1_STOPF I2C_SR1_STOPF_Msk
    -
    9322#define I2C_SR1_RXNE_Pos (6U)
    -
    9323#define I2C_SR1_RXNE_Msk (0x1UL << I2C_SR1_RXNE_Pos)
    -
    9324#define I2C_SR1_RXNE I2C_SR1_RXNE_Msk
    -
    9325#define I2C_SR1_TXE_Pos (7U)
    -
    9326#define I2C_SR1_TXE_Msk (0x1UL << I2C_SR1_TXE_Pos)
    -
    9327#define I2C_SR1_TXE I2C_SR1_TXE_Msk
    -
    9328#define I2C_SR1_BERR_Pos (8U)
    -
    9329#define I2C_SR1_BERR_Msk (0x1UL << I2C_SR1_BERR_Pos)
    -
    9330#define I2C_SR1_BERR I2C_SR1_BERR_Msk
    -
    9331#define I2C_SR1_ARLO_Pos (9U)
    -
    9332#define I2C_SR1_ARLO_Msk (0x1UL << I2C_SR1_ARLO_Pos)
    -
    9333#define I2C_SR1_ARLO I2C_SR1_ARLO_Msk
    -
    9334#define I2C_SR1_AF_Pos (10U)
    -
    9335#define I2C_SR1_AF_Msk (0x1UL << I2C_SR1_AF_Pos)
    -
    9336#define I2C_SR1_AF I2C_SR1_AF_Msk
    -
    9337#define I2C_SR1_OVR_Pos (11U)
    -
    9338#define I2C_SR1_OVR_Msk (0x1UL << I2C_SR1_OVR_Pos)
    -
    9339#define I2C_SR1_OVR I2C_SR1_OVR_Msk
    -
    9340#define I2C_SR1_PECERR_Pos (12U)
    -
    9341#define I2C_SR1_PECERR_Msk (0x1UL << I2C_SR1_PECERR_Pos)
    -
    9342#define I2C_SR1_PECERR I2C_SR1_PECERR_Msk
    -
    9343#define I2C_SR1_TIMEOUT_Pos (14U)
    -
    9344#define I2C_SR1_TIMEOUT_Msk (0x1UL << I2C_SR1_TIMEOUT_Pos)
    -
    9345#define I2C_SR1_TIMEOUT I2C_SR1_TIMEOUT_Msk
    -
    9346#define I2C_SR1_SMBALERT_Pos (15U)
    -
    9347#define I2C_SR1_SMBALERT_Msk (0x1UL << I2C_SR1_SMBALERT_Pos)
    -
    9348#define I2C_SR1_SMBALERT I2C_SR1_SMBALERT_Msk
    -
    9350/******************* Bit definition for I2C_SR2 register ********************/
    -
    9351#define I2C_SR2_MSL_Pos (0U)
    -
    9352#define I2C_SR2_MSL_Msk (0x1UL << I2C_SR2_MSL_Pos)
    -
    9353#define I2C_SR2_MSL I2C_SR2_MSL_Msk
    -
    9354#define I2C_SR2_BUSY_Pos (1U)
    -
    9355#define I2C_SR2_BUSY_Msk (0x1UL << I2C_SR2_BUSY_Pos)
    -
    9356#define I2C_SR2_BUSY I2C_SR2_BUSY_Msk
    -
    9357#define I2C_SR2_TRA_Pos (2U)
    -
    9358#define I2C_SR2_TRA_Msk (0x1UL << I2C_SR2_TRA_Pos)
    -
    9359#define I2C_SR2_TRA I2C_SR2_TRA_Msk
    -
    9360#define I2C_SR2_GENCALL_Pos (4U)
    -
    9361#define I2C_SR2_GENCALL_Msk (0x1UL << I2C_SR2_GENCALL_Pos)
    -
    9362#define I2C_SR2_GENCALL I2C_SR2_GENCALL_Msk
    -
    9363#define I2C_SR2_SMBDEFAULT_Pos (5U)
    -
    9364#define I2C_SR2_SMBDEFAULT_Msk (0x1UL << I2C_SR2_SMBDEFAULT_Pos)
    -
    9365#define I2C_SR2_SMBDEFAULT I2C_SR2_SMBDEFAULT_Msk
    -
    9366#define I2C_SR2_SMBHOST_Pos (6U)
    -
    9367#define I2C_SR2_SMBHOST_Msk (0x1UL << I2C_SR2_SMBHOST_Pos)
    -
    9368#define I2C_SR2_SMBHOST I2C_SR2_SMBHOST_Msk
    -
    9369#define I2C_SR2_DUALF_Pos (7U)
    -
    9370#define I2C_SR2_DUALF_Msk (0x1UL << I2C_SR2_DUALF_Pos)
    -
    9371#define I2C_SR2_DUALF I2C_SR2_DUALF_Msk
    -
    9372#define I2C_SR2_PEC_Pos (8U)
    -
    9373#define I2C_SR2_PEC_Msk (0xFFUL << I2C_SR2_PEC_Pos)
    -
    9374#define I2C_SR2_PEC I2C_SR2_PEC_Msk
    -
    9376/******************* Bit definition for I2C_CCR register ********************/
    -
    9377#define I2C_CCR_CCR_Pos (0U)
    -
    9378#define I2C_CCR_CCR_Msk (0xFFFUL << I2C_CCR_CCR_Pos)
    -
    9379#define I2C_CCR_CCR I2C_CCR_CCR_Msk
    -
    9380#define I2C_CCR_DUTY_Pos (14U)
    -
    9381#define I2C_CCR_DUTY_Msk (0x1UL << I2C_CCR_DUTY_Pos)
    -
    9382#define I2C_CCR_DUTY I2C_CCR_DUTY_Msk
    -
    9383#define I2C_CCR_FS_Pos (15U)
    -
    9384#define I2C_CCR_FS_Msk (0x1UL << I2C_CCR_FS_Pos)
    -
    9385#define I2C_CCR_FS I2C_CCR_FS_Msk
    -
    9387/****************** Bit definition for I2C_TRISE register *******************/
    -
    9388#define I2C_TRISE_TRISE_Pos (0U)
    -
    9389#define I2C_TRISE_TRISE_Msk (0x3FUL << I2C_TRISE_TRISE_Pos)
    -
    9390#define I2C_TRISE_TRISE I2C_TRISE_TRISE_Msk
    -
    9393/******************************************************************************/
    -
    9394/* */
    -
    9395/* Independent WATCHDOG */
    -
    9396/* */
    -
    9397/******************************************************************************/
    -
    9398/******************* Bit definition for IWDG_KR register ********************/
    -
    9399#define IWDG_KR_KEY_Pos (0U)
    -
    9400#define IWDG_KR_KEY_Msk (0xFFFFUL << IWDG_KR_KEY_Pos)
    -
    9401#define IWDG_KR_KEY IWDG_KR_KEY_Msk
    -
    9403/******************* Bit definition for IWDG_PR register ********************/
    -
    9404#define IWDG_PR_PR_Pos (0U)
    -
    9405#define IWDG_PR_PR_Msk (0x7UL << IWDG_PR_PR_Pos)
    -
    9406#define IWDG_PR_PR IWDG_PR_PR_Msk
    -
    9407#define IWDG_PR_PR_0 (0x1UL << IWDG_PR_PR_Pos)
    -
    9408#define IWDG_PR_PR_1 (0x2UL << IWDG_PR_PR_Pos)
    -
    9409#define IWDG_PR_PR_2 (0x4UL << IWDG_PR_PR_Pos)
    -
    9411/******************* Bit definition for IWDG_RLR register *******************/
    -
    9412#define IWDG_RLR_RL_Pos (0U)
    -
    9413#define IWDG_RLR_RL_Msk (0xFFFUL << IWDG_RLR_RL_Pos)
    -
    9414#define IWDG_RLR_RL IWDG_RLR_RL_Msk
    -
    9416/******************* Bit definition for IWDG_SR register ********************/
    -
    9417#define IWDG_SR_PVU_Pos (0U)
    -
    9418#define IWDG_SR_PVU_Msk (0x1UL << IWDG_SR_PVU_Pos)
    -
    9419#define IWDG_SR_PVU IWDG_SR_PVU_Msk
    -
    9420#define IWDG_SR_RVU_Pos (1U)
    -
    9421#define IWDG_SR_RVU_Msk (0x1UL << IWDG_SR_RVU_Pos)
    -
    9422#define IWDG_SR_RVU IWDG_SR_RVU_Msk
    -
    9426/******************************************************************************/
    -
    9427/* */
    -
    9428/* Power Control */
    -
    9429/* */
    -
    9430/******************************************************************************/
    -
    9431/******************** Bit definition for PWR_CR register ********************/
    -
    9432#define PWR_CR_LPDS_Pos (0U)
    -
    9433#define PWR_CR_LPDS_Msk (0x1UL << PWR_CR_LPDS_Pos)
    -
    9434#define PWR_CR_LPDS PWR_CR_LPDS_Msk
    -
    9435#define PWR_CR_PDDS_Pos (1U)
    -
    9436#define PWR_CR_PDDS_Msk (0x1UL << PWR_CR_PDDS_Pos)
    -
    9437#define PWR_CR_PDDS PWR_CR_PDDS_Msk
    -
    9438#define PWR_CR_CWUF_Pos (2U)
    -
    9439#define PWR_CR_CWUF_Msk (0x1UL << PWR_CR_CWUF_Pos)
    -
    9440#define PWR_CR_CWUF PWR_CR_CWUF_Msk
    -
    9441#define PWR_CR_CSBF_Pos (3U)
    -
    9442#define PWR_CR_CSBF_Msk (0x1UL << PWR_CR_CSBF_Pos)
    -
    9443#define PWR_CR_CSBF PWR_CR_CSBF_Msk
    -
    9444#define PWR_CR_PVDE_Pos (4U)
    -
    9445#define PWR_CR_PVDE_Msk (0x1UL << PWR_CR_PVDE_Pos)
    -
    9446#define PWR_CR_PVDE PWR_CR_PVDE_Msk
    -
    9448#define PWR_CR_PLS_Pos (5U)
    -
    9449#define PWR_CR_PLS_Msk (0x7UL << PWR_CR_PLS_Pos)
    -
    9450#define PWR_CR_PLS PWR_CR_PLS_Msk
    -
    9451#define PWR_CR_PLS_0 (0x1UL << PWR_CR_PLS_Pos)
    -
    9452#define PWR_CR_PLS_1 (0x2UL << PWR_CR_PLS_Pos)
    -
    9453#define PWR_CR_PLS_2 (0x4UL << PWR_CR_PLS_Pos)
    -
    9456#define PWR_CR_PLS_LEV0 0x00000000U
    -
    9457#define PWR_CR_PLS_LEV1 0x00000020U
    -
    9458#define PWR_CR_PLS_LEV2 0x00000040U
    -
    9459#define PWR_CR_PLS_LEV3 0x00000060U
    -
    9460#define PWR_CR_PLS_LEV4 0x00000080U
    -
    9461#define PWR_CR_PLS_LEV5 0x000000A0U
    -
    9462#define PWR_CR_PLS_LEV6 0x000000C0U
    -
    9463#define PWR_CR_PLS_LEV7 0x000000E0U
    -
    9464#define PWR_CR_DBP_Pos (8U)
    -
    9465#define PWR_CR_DBP_Msk (0x1UL << PWR_CR_DBP_Pos)
    -
    9466#define PWR_CR_DBP PWR_CR_DBP_Msk
    -
    9467#define PWR_CR_FPDS_Pos (9U)
    -
    9468#define PWR_CR_FPDS_Msk (0x1UL << PWR_CR_FPDS_Pos)
    -
    9469#define PWR_CR_FPDS PWR_CR_FPDS_Msk
    -
    9470#define PWR_CR_VOS_Pos (14U)
    -
    9471#define PWR_CR_VOS_Msk (0x1UL << PWR_CR_VOS_Pos)
    -
    9472#define PWR_CR_VOS PWR_CR_VOS_Msk
    -
    9474/* Legacy define */
    -
    9475#define PWR_CR_PMODE PWR_CR_VOS
    -
    9476
    -
    9477/******************* Bit definition for PWR_CSR register ********************/
    -
    9478#define PWR_CSR_WUF_Pos (0U)
    -
    9479#define PWR_CSR_WUF_Msk (0x1UL << PWR_CSR_WUF_Pos)
    -
    9480#define PWR_CSR_WUF PWR_CSR_WUF_Msk
    -
    9481#define PWR_CSR_SBF_Pos (1U)
    -
    9482#define PWR_CSR_SBF_Msk (0x1UL << PWR_CSR_SBF_Pos)
    -
    9483#define PWR_CSR_SBF PWR_CSR_SBF_Msk
    -
    9484#define PWR_CSR_PVDO_Pos (2U)
    -
    9485#define PWR_CSR_PVDO_Msk (0x1UL << PWR_CSR_PVDO_Pos)
    -
    9486#define PWR_CSR_PVDO PWR_CSR_PVDO_Msk
    -
    9487#define PWR_CSR_BRR_Pos (3U)
    -
    9488#define PWR_CSR_BRR_Msk (0x1UL << PWR_CSR_BRR_Pos)
    -
    9489#define PWR_CSR_BRR PWR_CSR_BRR_Msk
    -
    9490#define PWR_CSR_EWUP_Pos (8U)
    -
    9491#define PWR_CSR_EWUP_Msk (0x1UL << PWR_CSR_EWUP_Pos)
    -
    9492#define PWR_CSR_EWUP PWR_CSR_EWUP_Msk
    -
    9493#define PWR_CSR_BRE_Pos (9U)
    -
    9494#define PWR_CSR_BRE_Msk (0x1UL << PWR_CSR_BRE_Pos)
    -
    9495#define PWR_CSR_BRE PWR_CSR_BRE_Msk
    -
    9496#define PWR_CSR_VOSRDY_Pos (14U)
    -
    9497#define PWR_CSR_VOSRDY_Msk (0x1UL << PWR_CSR_VOSRDY_Pos)
    -
    9498#define PWR_CSR_VOSRDY PWR_CSR_VOSRDY_Msk
    -
    9500/* Legacy define */
    -
    9501#define PWR_CSR_REGRDY PWR_CSR_VOSRDY
    -
    9502
    -
    9503/******************************************************************************/
    -
    9504/* */
    -
    9505/* Reset and Clock Control */
    -
    9506/* */
    -
    9507/******************************************************************************/
    -
    9508/******************** Bit definition for RCC_CR register ********************/
    -
    9509#define RCC_CR_HSION_Pos (0U)
    -
    9510#define RCC_CR_HSION_Msk (0x1UL << RCC_CR_HSION_Pos)
    -
    9511#define RCC_CR_HSION RCC_CR_HSION_Msk
    -
    9512#define RCC_CR_HSIRDY_Pos (1U)
    -
    9513#define RCC_CR_HSIRDY_Msk (0x1UL << RCC_CR_HSIRDY_Pos)
    -
    9514#define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk
    -
    9515
    -
    9516#define RCC_CR_HSITRIM_Pos (3U)
    -
    9517#define RCC_CR_HSITRIM_Msk (0x1FUL << RCC_CR_HSITRIM_Pos)
    -
    9518#define RCC_CR_HSITRIM RCC_CR_HSITRIM_Msk
    -
    9519#define RCC_CR_HSITRIM_0 (0x01UL << RCC_CR_HSITRIM_Pos)
    -
    9520#define RCC_CR_HSITRIM_1 (0x02UL << RCC_CR_HSITRIM_Pos)
    -
    9521#define RCC_CR_HSITRIM_2 (0x04UL << RCC_CR_HSITRIM_Pos)
    -
    9522#define RCC_CR_HSITRIM_3 (0x08UL << RCC_CR_HSITRIM_Pos)
    -
    9523#define RCC_CR_HSITRIM_4 (0x10UL << RCC_CR_HSITRIM_Pos)
    -
    9525#define RCC_CR_HSICAL_Pos (8U)
    -
    9526#define RCC_CR_HSICAL_Msk (0xFFUL << RCC_CR_HSICAL_Pos)
    -
    9527#define RCC_CR_HSICAL RCC_CR_HSICAL_Msk
    -
    9528#define RCC_CR_HSICAL_0 (0x01UL << RCC_CR_HSICAL_Pos)
    -
    9529#define RCC_CR_HSICAL_1 (0x02UL << RCC_CR_HSICAL_Pos)
    -
    9530#define RCC_CR_HSICAL_2 (0x04UL << RCC_CR_HSICAL_Pos)
    -
    9531#define RCC_CR_HSICAL_3 (0x08UL << RCC_CR_HSICAL_Pos)
    -
    9532#define RCC_CR_HSICAL_4 (0x10UL << RCC_CR_HSICAL_Pos)
    -
    9533#define RCC_CR_HSICAL_5 (0x20UL << RCC_CR_HSICAL_Pos)
    -
    9534#define RCC_CR_HSICAL_6 (0x40UL << RCC_CR_HSICAL_Pos)
    -
    9535#define RCC_CR_HSICAL_7 (0x80UL << RCC_CR_HSICAL_Pos)
    -
    9537#define RCC_CR_HSEON_Pos (16U)
    -
    9538#define RCC_CR_HSEON_Msk (0x1UL << RCC_CR_HSEON_Pos)
    -
    9539#define RCC_CR_HSEON RCC_CR_HSEON_Msk
    -
    9540#define RCC_CR_HSERDY_Pos (17U)
    -
    9541#define RCC_CR_HSERDY_Msk (0x1UL << RCC_CR_HSERDY_Pos)
    -
    9542#define RCC_CR_HSERDY RCC_CR_HSERDY_Msk
    -
    9543#define RCC_CR_HSEBYP_Pos (18U)
    -
    9544#define RCC_CR_HSEBYP_Msk (0x1UL << RCC_CR_HSEBYP_Pos)
    -
    9545#define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk
    -
    9546#define RCC_CR_CSSON_Pos (19U)
    -
    9547#define RCC_CR_CSSON_Msk (0x1UL << RCC_CR_CSSON_Pos)
    -
    9548#define RCC_CR_CSSON RCC_CR_CSSON_Msk
    -
    9549#define RCC_CR_PLLON_Pos (24U)
    -
    9550#define RCC_CR_PLLON_Msk (0x1UL << RCC_CR_PLLON_Pos)
    -
    9551#define RCC_CR_PLLON RCC_CR_PLLON_Msk
    -
    9552#define RCC_CR_PLLRDY_Pos (25U)
    -
    9553#define RCC_CR_PLLRDY_Msk (0x1UL << RCC_CR_PLLRDY_Pos)
    -
    9554#define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk
    -
    9555/*
    -
    9556 * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
    -
    9557 */
    -
    9558#define RCC_PLLI2S_SUPPORT
    -
    9560#define RCC_CR_PLLI2SON_Pos (26U)
    -
    9561#define RCC_CR_PLLI2SON_Msk (0x1UL << RCC_CR_PLLI2SON_Pos)
    -
    9562#define RCC_CR_PLLI2SON RCC_CR_PLLI2SON_Msk
    -
    9563#define RCC_CR_PLLI2SRDY_Pos (27U)
    -
    9564#define RCC_CR_PLLI2SRDY_Msk (0x1UL << RCC_CR_PLLI2SRDY_Pos)
    -
    9565#define RCC_CR_PLLI2SRDY RCC_CR_PLLI2SRDY_Msk
    -
    9566
    -
    9567/******************** Bit definition for RCC_PLLCFGR register ***************/
    -
    9568#define RCC_PLLCFGR_PLLM_Pos (0U)
    -
    9569#define RCC_PLLCFGR_PLLM_Msk (0x3FUL << RCC_PLLCFGR_PLLM_Pos)
    -
    9570#define RCC_PLLCFGR_PLLM RCC_PLLCFGR_PLLM_Msk
    -
    9571#define RCC_PLLCFGR_PLLM_0 (0x01UL << RCC_PLLCFGR_PLLM_Pos)
    -
    9572#define RCC_PLLCFGR_PLLM_1 (0x02UL << RCC_PLLCFGR_PLLM_Pos)
    -
    9573#define RCC_PLLCFGR_PLLM_2 (0x04UL << RCC_PLLCFGR_PLLM_Pos)
    -
    9574#define RCC_PLLCFGR_PLLM_3 (0x08UL << RCC_PLLCFGR_PLLM_Pos)
    -
    9575#define RCC_PLLCFGR_PLLM_4 (0x10UL << RCC_PLLCFGR_PLLM_Pos)
    -
    9576#define RCC_PLLCFGR_PLLM_5 (0x20UL << RCC_PLLCFGR_PLLM_Pos)
    -
    9578#define RCC_PLLCFGR_PLLN_Pos (6U)
    -
    9579#define RCC_PLLCFGR_PLLN_Msk (0x1FFUL << RCC_PLLCFGR_PLLN_Pos)
    -
    9580#define RCC_PLLCFGR_PLLN RCC_PLLCFGR_PLLN_Msk
    -
    9581#define RCC_PLLCFGR_PLLN_0 (0x001UL << RCC_PLLCFGR_PLLN_Pos)
    -
    9582#define RCC_PLLCFGR_PLLN_1 (0x002UL << RCC_PLLCFGR_PLLN_Pos)
    -
    9583#define RCC_PLLCFGR_PLLN_2 (0x004UL << RCC_PLLCFGR_PLLN_Pos)
    -
    9584#define RCC_PLLCFGR_PLLN_3 (0x008UL << RCC_PLLCFGR_PLLN_Pos)
    -
    9585#define RCC_PLLCFGR_PLLN_4 (0x010UL << RCC_PLLCFGR_PLLN_Pos)
    -
    9586#define RCC_PLLCFGR_PLLN_5 (0x020UL << RCC_PLLCFGR_PLLN_Pos)
    -
    9587#define RCC_PLLCFGR_PLLN_6 (0x040UL << RCC_PLLCFGR_PLLN_Pos)
    -
    9588#define RCC_PLLCFGR_PLLN_7 (0x080UL << RCC_PLLCFGR_PLLN_Pos)
    -
    9589#define RCC_PLLCFGR_PLLN_8 (0x100UL << RCC_PLLCFGR_PLLN_Pos)
    -
    9591#define RCC_PLLCFGR_PLLP_Pos (16U)
    -
    9592#define RCC_PLLCFGR_PLLP_Msk (0x3UL << RCC_PLLCFGR_PLLP_Pos)
    -
    9593#define RCC_PLLCFGR_PLLP RCC_PLLCFGR_PLLP_Msk
    -
    9594#define RCC_PLLCFGR_PLLP_0 (0x1UL << RCC_PLLCFGR_PLLP_Pos)
    -
    9595#define RCC_PLLCFGR_PLLP_1 (0x2UL << RCC_PLLCFGR_PLLP_Pos)
    -
    9597#define RCC_PLLCFGR_PLLSRC_Pos (22U)
    -
    9598#define RCC_PLLCFGR_PLLSRC_Msk (0x1UL << RCC_PLLCFGR_PLLSRC_Pos)
    -
    9599#define RCC_PLLCFGR_PLLSRC RCC_PLLCFGR_PLLSRC_Msk
    -
    9600#define RCC_PLLCFGR_PLLSRC_HSE_Pos (22U)
    -
    9601#define RCC_PLLCFGR_PLLSRC_HSE_Msk (0x1UL << RCC_PLLCFGR_PLLSRC_HSE_Pos)
    -
    9602#define RCC_PLLCFGR_PLLSRC_HSE RCC_PLLCFGR_PLLSRC_HSE_Msk
    -
    9603#define RCC_PLLCFGR_PLLSRC_HSI 0x00000000U
    -
    9604
    -
    9605#define RCC_PLLCFGR_PLLQ_Pos (24U)
    -
    9606#define RCC_PLLCFGR_PLLQ_Msk (0xFUL << RCC_PLLCFGR_PLLQ_Pos)
    -
    9607#define RCC_PLLCFGR_PLLQ RCC_PLLCFGR_PLLQ_Msk
    -
    9608#define RCC_PLLCFGR_PLLQ_0 (0x1UL << RCC_PLLCFGR_PLLQ_Pos)
    -
    9609#define RCC_PLLCFGR_PLLQ_1 (0x2UL << RCC_PLLCFGR_PLLQ_Pos)
    -
    9610#define RCC_PLLCFGR_PLLQ_2 (0x4UL << RCC_PLLCFGR_PLLQ_Pos)
    -
    9611#define RCC_PLLCFGR_PLLQ_3 (0x8UL << RCC_PLLCFGR_PLLQ_Pos)
    -
    9614/******************** Bit definition for RCC_CFGR register ******************/
    -
    9616#define RCC_CFGR_SW_Pos (0U)
    -
    9617#define RCC_CFGR_SW_Msk (0x3UL << RCC_CFGR_SW_Pos)
    -
    9618#define RCC_CFGR_SW RCC_CFGR_SW_Msk
    -
    9619#define RCC_CFGR_SW_0 (0x1UL << RCC_CFGR_SW_Pos)
    -
    9620#define RCC_CFGR_SW_1 (0x2UL << RCC_CFGR_SW_Pos)
    -
    9622#define RCC_CFGR_SW_HSI 0x00000000U
    -
    9623#define RCC_CFGR_SW_HSE 0x00000001U
    -
    9624#define RCC_CFGR_SW_PLL 0x00000002U
    -
    9627#define RCC_CFGR_SWS_Pos (2U)
    -
    9628#define RCC_CFGR_SWS_Msk (0x3UL << RCC_CFGR_SWS_Pos)
    -
    9629#define RCC_CFGR_SWS RCC_CFGR_SWS_Msk
    -
    9630#define RCC_CFGR_SWS_0 (0x1UL << RCC_CFGR_SWS_Pos)
    -
    9631#define RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos)
    -
    9633#define RCC_CFGR_SWS_HSI 0x00000000U
    -
    9634#define RCC_CFGR_SWS_HSE 0x00000004U
    -
    9635#define RCC_CFGR_SWS_PLL 0x00000008U
    -
    9638#define RCC_CFGR_HPRE_Pos (4U)
    -
    9639#define RCC_CFGR_HPRE_Msk (0xFUL << RCC_CFGR_HPRE_Pos)
    -
    9640#define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk
    -
    9641#define RCC_CFGR_HPRE_0 (0x1UL << RCC_CFGR_HPRE_Pos)
    -
    9642#define RCC_CFGR_HPRE_1 (0x2UL << RCC_CFGR_HPRE_Pos)
    -
    9643#define RCC_CFGR_HPRE_2 (0x4UL << RCC_CFGR_HPRE_Pos)
    -
    9644#define RCC_CFGR_HPRE_3 (0x8UL << RCC_CFGR_HPRE_Pos)
    -
    9646#define RCC_CFGR_HPRE_DIV1 0x00000000U
    -
    9647#define RCC_CFGR_HPRE_DIV2 0x00000080U
    -
    9648#define RCC_CFGR_HPRE_DIV4 0x00000090U
    -
    9649#define RCC_CFGR_HPRE_DIV8 0x000000A0U
    -
    9650#define RCC_CFGR_HPRE_DIV16 0x000000B0U
    -
    9651#define RCC_CFGR_HPRE_DIV64 0x000000C0U
    -
    9652#define RCC_CFGR_HPRE_DIV128 0x000000D0U
    -
    9653#define RCC_CFGR_HPRE_DIV256 0x000000E0U
    -
    9654#define RCC_CFGR_HPRE_DIV512 0x000000F0U
    -
    9657#define RCC_CFGR_PPRE1_Pos (10U)
    -
    9658#define RCC_CFGR_PPRE1_Msk (0x7UL << RCC_CFGR_PPRE1_Pos)
    -
    9659#define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk
    -
    9660#define RCC_CFGR_PPRE1_0 (0x1UL << RCC_CFGR_PPRE1_Pos)
    -
    9661#define RCC_CFGR_PPRE1_1 (0x2UL << RCC_CFGR_PPRE1_Pos)
    -
    9662#define RCC_CFGR_PPRE1_2 (0x4UL << RCC_CFGR_PPRE1_Pos)
    -
    9664#define RCC_CFGR_PPRE1_DIV1 0x00000000U
    -
    9665#define RCC_CFGR_PPRE1_DIV2 0x00001000U
    -
    9666#define RCC_CFGR_PPRE1_DIV4 0x00001400U
    -
    9667#define RCC_CFGR_PPRE1_DIV8 0x00001800U
    -
    9668#define RCC_CFGR_PPRE1_DIV16 0x00001C00U
    -
    9671#define RCC_CFGR_PPRE2_Pos (13U)
    -
    9672#define RCC_CFGR_PPRE2_Msk (0x7UL << RCC_CFGR_PPRE2_Pos)
    -
    9673#define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk
    -
    9674#define RCC_CFGR_PPRE2_0 (0x1UL << RCC_CFGR_PPRE2_Pos)
    -
    9675#define RCC_CFGR_PPRE2_1 (0x2UL << RCC_CFGR_PPRE2_Pos)
    -
    9676#define RCC_CFGR_PPRE2_2 (0x4UL << RCC_CFGR_PPRE2_Pos)
    -
    9678#define RCC_CFGR_PPRE2_DIV1 0x00000000U
    -
    9679#define RCC_CFGR_PPRE2_DIV2 0x00008000U
    -
    9680#define RCC_CFGR_PPRE2_DIV4 0x0000A000U
    -
    9681#define RCC_CFGR_PPRE2_DIV8 0x0000C000U
    -
    9682#define RCC_CFGR_PPRE2_DIV16 0x0000E000U
    -
    9685#define RCC_CFGR_RTCPRE_Pos (16U)
    -
    9686#define RCC_CFGR_RTCPRE_Msk (0x1FUL << RCC_CFGR_RTCPRE_Pos)
    -
    9687#define RCC_CFGR_RTCPRE RCC_CFGR_RTCPRE_Msk
    -
    9688#define RCC_CFGR_RTCPRE_0 (0x01UL << RCC_CFGR_RTCPRE_Pos)
    -
    9689#define RCC_CFGR_RTCPRE_1 (0x02UL << RCC_CFGR_RTCPRE_Pos)
    -
    9690#define RCC_CFGR_RTCPRE_2 (0x04UL << RCC_CFGR_RTCPRE_Pos)
    -
    9691#define RCC_CFGR_RTCPRE_3 (0x08UL << RCC_CFGR_RTCPRE_Pos)
    -
    9692#define RCC_CFGR_RTCPRE_4 (0x10UL << RCC_CFGR_RTCPRE_Pos)
    -
    9695#define RCC_CFGR_MCO1_Pos (21U)
    -
    9696#define RCC_CFGR_MCO1_Msk (0x3UL << RCC_CFGR_MCO1_Pos)
    -
    9697#define RCC_CFGR_MCO1 RCC_CFGR_MCO1_Msk
    -
    9698#define RCC_CFGR_MCO1_0 (0x1UL << RCC_CFGR_MCO1_Pos)
    -
    9699#define RCC_CFGR_MCO1_1 (0x2UL << RCC_CFGR_MCO1_Pos)
    -
    9701#define RCC_CFGR_I2SSRC_Pos (23U)
    -
    9702#define RCC_CFGR_I2SSRC_Msk (0x1UL << RCC_CFGR_I2SSRC_Pos)
    -
    9703#define RCC_CFGR_I2SSRC RCC_CFGR_I2SSRC_Msk
    -
    9704
    -
    9705#define RCC_CFGR_MCO1PRE_Pos (24U)
    -
    9706#define RCC_CFGR_MCO1PRE_Msk (0x7UL << RCC_CFGR_MCO1PRE_Pos)
    -
    9707#define RCC_CFGR_MCO1PRE RCC_CFGR_MCO1PRE_Msk
    -
    9708#define RCC_CFGR_MCO1PRE_0 (0x1UL << RCC_CFGR_MCO1PRE_Pos)
    -
    9709#define RCC_CFGR_MCO1PRE_1 (0x2UL << RCC_CFGR_MCO1PRE_Pos)
    -
    9710#define RCC_CFGR_MCO1PRE_2 (0x4UL << RCC_CFGR_MCO1PRE_Pos)
    -
    9712#define RCC_CFGR_MCO2PRE_Pos (27U)
    -
    9713#define RCC_CFGR_MCO2PRE_Msk (0x7UL << RCC_CFGR_MCO2PRE_Pos)
    -
    9714#define RCC_CFGR_MCO2PRE RCC_CFGR_MCO2PRE_Msk
    -
    9715#define RCC_CFGR_MCO2PRE_0 (0x1UL << RCC_CFGR_MCO2PRE_Pos)
    -
    9716#define RCC_CFGR_MCO2PRE_1 (0x2UL << RCC_CFGR_MCO2PRE_Pos)
    -
    9717#define RCC_CFGR_MCO2PRE_2 (0x4UL << RCC_CFGR_MCO2PRE_Pos)
    -
    9719#define RCC_CFGR_MCO2_Pos (30U)
    -
    9720#define RCC_CFGR_MCO2_Msk (0x3UL << RCC_CFGR_MCO2_Pos)
    -
    9721#define RCC_CFGR_MCO2 RCC_CFGR_MCO2_Msk
    -
    9722#define RCC_CFGR_MCO2_0 (0x1UL << RCC_CFGR_MCO2_Pos)
    -
    9723#define RCC_CFGR_MCO2_1 (0x2UL << RCC_CFGR_MCO2_Pos)
    -
    9725/******************** Bit definition for RCC_CIR register *******************/
    -
    9726#define RCC_CIR_LSIRDYF_Pos (0U)
    -
    9727#define RCC_CIR_LSIRDYF_Msk (0x1UL << RCC_CIR_LSIRDYF_Pos)
    -
    9728#define RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF_Msk
    -
    9729#define RCC_CIR_LSERDYF_Pos (1U)
    -
    9730#define RCC_CIR_LSERDYF_Msk (0x1UL << RCC_CIR_LSERDYF_Pos)
    -
    9731#define RCC_CIR_LSERDYF RCC_CIR_LSERDYF_Msk
    -
    9732#define RCC_CIR_HSIRDYF_Pos (2U)
    -
    9733#define RCC_CIR_HSIRDYF_Msk (0x1UL << RCC_CIR_HSIRDYF_Pos)
    -
    9734#define RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF_Msk
    -
    9735#define RCC_CIR_HSERDYF_Pos (3U)
    -
    9736#define RCC_CIR_HSERDYF_Msk (0x1UL << RCC_CIR_HSERDYF_Pos)
    -
    9737#define RCC_CIR_HSERDYF RCC_CIR_HSERDYF_Msk
    -
    9738#define RCC_CIR_PLLRDYF_Pos (4U)
    -
    9739#define RCC_CIR_PLLRDYF_Msk (0x1UL << RCC_CIR_PLLRDYF_Pos)
    -
    9740#define RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF_Msk
    -
    9741#define RCC_CIR_PLLI2SRDYF_Pos (5U)
    -
    9742#define RCC_CIR_PLLI2SRDYF_Msk (0x1UL << RCC_CIR_PLLI2SRDYF_Pos)
    -
    9743#define RCC_CIR_PLLI2SRDYF RCC_CIR_PLLI2SRDYF_Msk
    -
    9744
    -
    9745#define RCC_CIR_CSSF_Pos (7U)
    -
    9746#define RCC_CIR_CSSF_Msk (0x1UL << RCC_CIR_CSSF_Pos)
    -
    9747#define RCC_CIR_CSSF RCC_CIR_CSSF_Msk
    -
    9748#define RCC_CIR_LSIRDYIE_Pos (8U)
    -
    9749#define RCC_CIR_LSIRDYIE_Msk (0x1UL << RCC_CIR_LSIRDYIE_Pos)
    -
    9750#define RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE_Msk
    -
    9751#define RCC_CIR_LSERDYIE_Pos (9U)
    -
    9752#define RCC_CIR_LSERDYIE_Msk (0x1UL << RCC_CIR_LSERDYIE_Pos)
    -
    9753#define RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE_Msk
    -
    9754#define RCC_CIR_HSIRDYIE_Pos (10U)
    -
    9755#define RCC_CIR_HSIRDYIE_Msk (0x1UL << RCC_CIR_HSIRDYIE_Pos)
    -
    9756#define RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE_Msk
    -
    9757#define RCC_CIR_HSERDYIE_Pos (11U)
    -
    9758#define RCC_CIR_HSERDYIE_Msk (0x1UL << RCC_CIR_HSERDYIE_Pos)
    -
    9759#define RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE_Msk
    -
    9760#define RCC_CIR_PLLRDYIE_Pos (12U)
    -
    9761#define RCC_CIR_PLLRDYIE_Msk (0x1UL << RCC_CIR_PLLRDYIE_Pos)
    -
    9762#define RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE_Msk
    -
    9763#define RCC_CIR_PLLI2SRDYIE_Pos (13U)
    -
    9764#define RCC_CIR_PLLI2SRDYIE_Msk (0x1UL << RCC_CIR_PLLI2SRDYIE_Pos)
    -
    9765#define RCC_CIR_PLLI2SRDYIE RCC_CIR_PLLI2SRDYIE_Msk
    -
    9766
    -
    9767#define RCC_CIR_LSIRDYC_Pos (16U)
    -
    9768#define RCC_CIR_LSIRDYC_Msk (0x1UL << RCC_CIR_LSIRDYC_Pos)
    -
    9769#define RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC_Msk
    -
    9770#define RCC_CIR_LSERDYC_Pos (17U)
    -
    9771#define RCC_CIR_LSERDYC_Msk (0x1UL << RCC_CIR_LSERDYC_Pos)
    -
    9772#define RCC_CIR_LSERDYC RCC_CIR_LSERDYC_Msk
    -
    9773#define RCC_CIR_HSIRDYC_Pos (18U)
    -
    9774#define RCC_CIR_HSIRDYC_Msk (0x1UL << RCC_CIR_HSIRDYC_Pos)
    -
    9775#define RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC_Msk
    -
    9776#define RCC_CIR_HSERDYC_Pos (19U)
    -
    9777#define RCC_CIR_HSERDYC_Msk (0x1UL << RCC_CIR_HSERDYC_Pos)
    -
    9778#define RCC_CIR_HSERDYC RCC_CIR_HSERDYC_Msk
    -
    9779#define RCC_CIR_PLLRDYC_Pos (20U)
    -
    9780#define RCC_CIR_PLLRDYC_Msk (0x1UL << RCC_CIR_PLLRDYC_Pos)
    -
    9781#define RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC_Msk
    -
    9782#define RCC_CIR_PLLI2SRDYC_Pos (21U)
    -
    9783#define RCC_CIR_PLLI2SRDYC_Msk (0x1UL << RCC_CIR_PLLI2SRDYC_Pos)
    -
    9784#define RCC_CIR_PLLI2SRDYC RCC_CIR_PLLI2SRDYC_Msk
    -
    9785
    -
    9786#define RCC_CIR_CSSC_Pos (23U)
    -
    9787#define RCC_CIR_CSSC_Msk (0x1UL << RCC_CIR_CSSC_Pos)
    -
    9788#define RCC_CIR_CSSC RCC_CIR_CSSC_Msk
    -
    9789
    -
    9790/******************** Bit definition for RCC_AHB1RSTR register **************/
    -
    9791#define RCC_AHB1RSTR_GPIOARST_Pos (0U)
    -
    9792#define RCC_AHB1RSTR_GPIOARST_Msk (0x1UL << RCC_AHB1RSTR_GPIOARST_Pos)
    -
    9793#define RCC_AHB1RSTR_GPIOARST RCC_AHB1RSTR_GPIOARST_Msk
    -
    9794#define RCC_AHB1RSTR_GPIOBRST_Pos (1U)
    -
    9795#define RCC_AHB1RSTR_GPIOBRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOBRST_Pos)
    -
    9796#define RCC_AHB1RSTR_GPIOBRST RCC_AHB1RSTR_GPIOBRST_Msk
    -
    9797#define RCC_AHB1RSTR_GPIOCRST_Pos (2U)
    -
    9798#define RCC_AHB1RSTR_GPIOCRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOCRST_Pos)
    -
    9799#define RCC_AHB1RSTR_GPIOCRST RCC_AHB1RSTR_GPIOCRST_Msk
    -
    9800#define RCC_AHB1RSTR_GPIODRST_Pos (3U)
    -
    9801#define RCC_AHB1RSTR_GPIODRST_Msk (0x1UL << RCC_AHB1RSTR_GPIODRST_Pos)
    -
    9802#define RCC_AHB1RSTR_GPIODRST RCC_AHB1RSTR_GPIODRST_Msk
    -
    9803#define RCC_AHB1RSTR_GPIOERST_Pos (4U)
    -
    9804#define RCC_AHB1RSTR_GPIOERST_Msk (0x1UL << RCC_AHB1RSTR_GPIOERST_Pos)
    -
    9805#define RCC_AHB1RSTR_GPIOERST RCC_AHB1RSTR_GPIOERST_Msk
    -
    9806#define RCC_AHB1RSTR_GPIOFRST_Pos (5U)
    -
    9807#define RCC_AHB1RSTR_GPIOFRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOFRST_Pos)
    -
    9808#define RCC_AHB1RSTR_GPIOFRST RCC_AHB1RSTR_GPIOFRST_Msk
    -
    9809#define RCC_AHB1RSTR_GPIOGRST_Pos (6U)
    -
    9810#define RCC_AHB1RSTR_GPIOGRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOGRST_Pos)
    -
    9811#define RCC_AHB1RSTR_GPIOGRST RCC_AHB1RSTR_GPIOGRST_Msk
    -
    9812#define RCC_AHB1RSTR_GPIOHRST_Pos (7U)
    -
    9813#define RCC_AHB1RSTR_GPIOHRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOHRST_Pos)
    -
    9814#define RCC_AHB1RSTR_GPIOHRST RCC_AHB1RSTR_GPIOHRST_Msk
    -
    9815#define RCC_AHB1RSTR_GPIOIRST_Pos (8U)
    -
    9816#define RCC_AHB1RSTR_GPIOIRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOIRST_Pos)
    -
    9817#define RCC_AHB1RSTR_GPIOIRST RCC_AHB1RSTR_GPIOIRST_Msk
    -
    9818#define RCC_AHB1RSTR_CRCRST_Pos (12U)
    -
    9819#define RCC_AHB1RSTR_CRCRST_Msk (0x1UL << RCC_AHB1RSTR_CRCRST_Pos)
    -
    9820#define RCC_AHB1RSTR_CRCRST RCC_AHB1RSTR_CRCRST_Msk
    -
    9821#define RCC_AHB1RSTR_DMA1RST_Pos (21U)
    -
    9822#define RCC_AHB1RSTR_DMA1RST_Msk (0x1UL << RCC_AHB1RSTR_DMA1RST_Pos)
    -
    9823#define RCC_AHB1RSTR_DMA1RST RCC_AHB1RSTR_DMA1RST_Msk
    -
    9824#define RCC_AHB1RSTR_DMA2RST_Pos (22U)
    -
    9825#define RCC_AHB1RSTR_DMA2RST_Msk (0x1UL << RCC_AHB1RSTR_DMA2RST_Pos)
    -
    9826#define RCC_AHB1RSTR_DMA2RST RCC_AHB1RSTR_DMA2RST_Msk
    -
    9827#define RCC_AHB1RSTR_ETHMACRST_Pos (25U)
    -
    9828#define RCC_AHB1RSTR_ETHMACRST_Msk (0x1UL << RCC_AHB1RSTR_ETHMACRST_Pos)
    -
    9829#define RCC_AHB1RSTR_ETHMACRST RCC_AHB1RSTR_ETHMACRST_Msk
    -
    9830#define RCC_AHB1RSTR_OTGHRST_Pos (29U)
    -
    9831#define RCC_AHB1RSTR_OTGHRST_Msk (0x1UL << RCC_AHB1RSTR_OTGHRST_Pos)
    -
    9832#define RCC_AHB1RSTR_OTGHRST RCC_AHB1RSTR_OTGHRST_Msk
    -
    9833
    -
    9834/******************** Bit definition for RCC_AHB2RSTR register **************/
    -
    9835#define RCC_AHB2RSTR_DCMIRST_Pos (0U)
    -
    9836#define RCC_AHB2RSTR_DCMIRST_Msk (0x1UL << RCC_AHB2RSTR_DCMIRST_Pos)
    -
    9837#define RCC_AHB2RSTR_DCMIRST RCC_AHB2RSTR_DCMIRST_Msk
    -
    9838#define RCC_AHB2RSTR_RNGRST_Pos (6U)
    -
    9839#define RCC_AHB2RSTR_RNGRST_Msk (0x1UL << RCC_AHB2RSTR_RNGRST_Pos)
    -
    9840#define RCC_AHB2RSTR_RNGRST RCC_AHB2RSTR_RNGRST_Msk
    -
    9841#define RCC_AHB2RSTR_OTGFSRST_Pos (7U)
    -
    9842#define RCC_AHB2RSTR_OTGFSRST_Msk (0x1UL << RCC_AHB2RSTR_OTGFSRST_Pos)
    -
    9843#define RCC_AHB2RSTR_OTGFSRST RCC_AHB2RSTR_OTGFSRST_Msk
    -
    9844/******************** Bit definition for RCC_AHB3RSTR register **************/
    -
    9845#define RCC_AHB3RSTR_FSMCRST_Pos (0U)
    -
    9846#define RCC_AHB3RSTR_FSMCRST_Msk (0x1UL << RCC_AHB3RSTR_FSMCRST_Pos)
    -
    9847#define RCC_AHB3RSTR_FSMCRST RCC_AHB3RSTR_FSMCRST_Msk
    -
    9848
    -
    9849
    -
    9850/******************** Bit definition for RCC_APB1RSTR register **************/
    -
    9851#define RCC_APB1RSTR_TIM2RST_Pos (0U)
    -
    9852#define RCC_APB1RSTR_TIM2RST_Msk (0x1UL << RCC_APB1RSTR_TIM2RST_Pos)
    -
    9853#define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk
    -
    9854#define RCC_APB1RSTR_TIM3RST_Pos (1U)
    -
    9855#define RCC_APB1RSTR_TIM3RST_Msk (0x1UL << RCC_APB1RSTR_TIM3RST_Pos)
    -
    9856#define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk
    -
    9857#define RCC_APB1RSTR_TIM4RST_Pos (2U)
    -
    9858#define RCC_APB1RSTR_TIM4RST_Msk (0x1UL << RCC_APB1RSTR_TIM4RST_Pos)
    -
    9859#define RCC_APB1RSTR_TIM4RST RCC_APB1RSTR_TIM4RST_Msk
    -
    9860#define RCC_APB1RSTR_TIM5RST_Pos (3U)
    -
    9861#define RCC_APB1RSTR_TIM5RST_Msk (0x1UL << RCC_APB1RSTR_TIM5RST_Pos)
    -
    9862#define RCC_APB1RSTR_TIM5RST RCC_APB1RSTR_TIM5RST_Msk
    -
    9863#define RCC_APB1RSTR_TIM6RST_Pos (4U)
    -
    9864#define RCC_APB1RSTR_TIM6RST_Msk (0x1UL << RCC_APB1RSTR_TIM6RST_Pos)
    -
    9865#define RCC_APB1RSTR_TIM6RST RCC_APB1RSTR_TIM6RST_Msk
    -
    9866#define RCC_APB1RSTR_TIM7RST_Pos (5U)
    -
    9867#define RCC_APB1RSTR_TIM7RST_Msk (0x1UL << RCC_APB1RSTR_TIM7RST_Pos)
    -
    9868#define RCC_APB1RSTR_TIM7RST RCC_APB1RSTR_TIM7RST_Msk
    -
    9869#define RCC_APB1RSTR_TIM12RST_Pos (6U)
    -
    9870#define RCC_APB1RSTR_TIM12RST_Msk (0x1UL << RCC_APB1RSTR_TIM12RST_Pos)
    -
    9871#define RCC_APB1RSTR_TIM12RST RCC_APB1RSTR_TIM12RST_Msk
    -
    9872#define RCC_APB1RSTR_TIM13RST_Pos (7U)
    -
    9873#define RCC_APB1RSTR_TIM13RST_Msk (0x1UL << RCC_APB1RSTR_TIM13RST_Pos)
    -
    9874#define RCC_APB1RSTR_TIM13RST RCC_APB1RSTR_TIM13RST_Msk
    -
    9875#define RCC_APB1RSTR_TIM14RST_Pos (8U)
    -
    9876#define RCC_APB1RSTR_TIM14RST_Msk (0x1UL << RCC_APB1RSTR_TIM14RST_Pos)
    -
    9877#define RCC_APB1RSTR_TIM14RST RCC_APB1RSTR_TIM14RST_Msk
    -
    9878#define RCC_APB1RSTR_WWDGRST_Pos (11U)
    -
    9879#define RCC_APB1RSTR_WWDGRST_Msk (0x1UL << RCC_APB1RSTR_WWDGRST_Pos)
    -
    9880#define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk
    -
    9881#define RCC_APB1RSTR_SPI2RST_Pos (14U)
    -
    9882#define RCC_APB1RSTR_SPI2RST_Msk (0x1UL << RCC_APB1RSTR_SPI2RST_Pos)
    -
    9883#define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk
    -
    9884#define RCC_APB1RSTR_SPI3RST_Pos (15U)
    -
    9885#define RCC_APB1RSTR_SPI3RST_Msk (0x1UL << RCC_APB1RSTR_SPI3RST_Pos)
    -
    9886#define RCC_APB1RSTR_SPI3RST RCC_APB1RSTR_SPI3RST_Msk
    -
    9887#define RCC_APB1RSTR_USART2RST_Pos (17U)
    -
    9888#define RCC_APB1RSTR_USART2RST_Msk (0x1UL << RCC_APB1RSTR_USART2RST_Pos)
    -
    9889#define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk
    -
    9890#define RCC_APB1RSTR_USART3RST_Pos (18U)
    -
    9891#define RCC_APB1RSTR_USART3RST_Msk (0x1UL << RCC_APB1RSTR_USART3RST_Pos)
    -
    9892#define RCC_APB1RSTR_USART3RST RCC_APB1RSTR_USART3RST_Msk
    -
    9893#define RCC_APB1RSTR_UART4RST_Pos (19U)
    -
    9894#define RCC_APB1RSTR_UART4RST_Msk (0x1UL << RCC_APB1RSTR_UART4RST_Pos)
    -
    9895#define RCC_APB1RSTR_UART4RST RCC_APB1RSTR_UART4RST_Msk
    -
    9896#define RCC_APB1RSTR_UART5RST_Pos (20U)
    -
    9897#define RCC_APB1RSTR_UART5RST_Msk (0x1UL << RCC_APB1RSTR_UART5RST_Pos)
    -
    9898#define RCC_APB1RSTR_UART5RST RCC_APB1RSTR_UART5RST_Msk
    -
    9899#define RCC_APB1RSTR_I2C1RST_Pos (21U)
    -
    9900#define RCC_APB1RSTR_I2C1RST_Msk (0x1UL << RCC_APB1RSTR_I2C1RST_Pos)
    -
    9901#define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk
    -
    9902#define RCC_APB1RSTR_I2C2RST_Pos (22U)
    -
    9903#define RCC_APB1RSTR_I2C2RST_Msk (0x1UL << RCC_APB1RSTR_I2C2RST_Pos)
    -
    9904#define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk
    -
    9905#define RCC_APB1RSTR_I2C3RST_Pos (23U)
    -
    9906#define RCC_APB1RSTR_I2C3RST_Msk (0x1UL << RCC_APB1RSTR_I2C3RST_Pos)
    -
    9907#define RCC_APB1RSTR_I2C3RST RCC_APB1RSTR_I2C3RST_Msk
    -
    9908#define RCC_APB1RSTR_CAN1RST_Pos (25U)
    -
    9909#define RCC_APB1RSTR_CAN1RST_Msk (0x1UL << RCC_APB1RSTR_CAN1RST_Pos)
    -
    9910#define RCC_APB1RSTR_CAN1RST RCC_APB1RSTR_CAN1RST_Msk
    -
    9911#define RCC_APB1RSTR_CAN2RST_Pos (26U)
    -
    9912#define RCC_APB1RSTR_CAN2RST_Msk (0x1UL << RCC_APB1RSTR_CAN2RST_Pos)
    -
    9913#define RCC_APB1RSTR_CAN2RST RCC_APB1RSTR_CAN2RST_Msk
    -
    9914#define RCC_APB1RSTR_PWRRST_Pos (28U)
    -
    9915#define RCC_APB1RSTR_PWRRST_Msk (0x1UL << RCC_APB1RSTR_PWRRST_Pos)
    -
    9916#define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk
    -
    9917#define RCC_APB1RSTR_DACRST_Pos (29U)
    -
    9918#define RCC_APB1RSTR_DACRST_Msk (0x1UL << RCC_APB1RSTR_DACRST_Pos)
    -
    9919#define RCC_APB1RSTR_DACRST RCC_APB1RSTR_DACRST_Msk
    -
    9920
    -
    9921/******************** Bit definition for RCC_APB2RSTR register **************/
    -
    9922#define RCC_APB2RSTR_TIM1RST_Pos (0U)
    -
    9923#define RCC_APB2RSTR_TIM1RST_Msk (0x1UL << RCC_APB2RSTR_TIM1RST_Pos)
    -
    9924#define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk
    -
    9925#define RCC_APB2RSTR_TIM8RST_Pos (1U)
    -
    9926#define RCC_APB2RSTR_TIM8RST_Msk (0x1UL << RCC_APB2RSTR_TIM8RST_Pos)
    -
    9927#define RCC_APB2RSTR_TIM8RST RCC_APB2RSTR_TIM8RST_Msk
    -
    9928#define RCC_APB2RSTR_USART1RST_Pos (4U)
    -
    9929#define RCC_APB2RSTR_USART1RST_Msk (0x1UL << RCC_APB2RSTR_USART1RST_Pos)
    -
    9930#define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk
    -
    9931#define RCC_APB2RSTR_USART6RST_Pos (5U)
    -
    9932#define RCC_APB2RSTR_USART6RST_Msk (0x1UL << RCC_APB2RSTR_USART6RST_Pos)
    -
    9933#define RCC_APB2RSTR_USART6RST RCC_APB2RSTR_USART6RST_Msk
    -
    9934#define RCC_APB2RSTR_ADCRST_Pos (8U)
    -
    9935#define RCC_APB2RSTR_ADCRST_Msk (0x1UL << RCC_APB2RSTR_ADCRST_Pos)
    -
    9936#define RCC_APB2RSTR_ADCRST RCC_APB2RSTR_ADCRST_Msk
    -
    9937#define RCC_APB2RSTR_SDIORST_Pos (11U)
    -
    9938#define RCC_APB2RSTR_SDIORST_Msk (0x1UL << RCC_APB2RSTR_SDIORST_Pos)
    -
    9939#define RCC_APB2RSTR_SDIORST RCC_APB2RSTR_SDIORST_Msk
    -
    9940#define RCC_APB2RSTR_SPI1RST_Pos (12U)
    -
    9941#define RCC_APB2RSTR_SPI1RST_Msk (0x1UL << RCC_APB2RSTR_SPI1RST_Pos)
    -
    9942#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk
    -
    9943#define RCC_APB2RSTR_SYSCFGRST_Pos (14U)
    -
    9944#define RCC_APB2RSTR_SYSCFGRST_Msk (0x1UL << RCC_APB2RSTR_SYSCFGRST_Pos)
    -
    9945#define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk
    -
    9946#define RCC_APB2RSTR_TIM9RST_Pos (16U)
    -
    9947#define RCC_APB2RSTR_TIM9RST_Msk (0x1UL << RCC_APB2RSTR_TIM9RST_Pos)
    -
    9948#define RCC_APB2RSTR_TIM9RST RCC_APB2RSTR_TIM9RST_Msk
    -
    9949#define RCC_APB2RSTR_TIM10RST_Pos (17U)
    -
    9950#define RCC_APB2RSTR_TIM10RST_Msk (0x1UL << RCC_APB2RSTR_TIM10RST_Pos)
    -
    9951#define RCC_APB2RSTR_TIM10RST RCC_APB2RSTR_TIM10RST_Msk
    -
    9952#define RCC_APB2RSTR_TIM11RST_Pos (18U)
    -
    9953#define RCC_APB2RSTR_TIM11RST_Msk (0x1UL << RCC_APB2RSTR_TIM11RST_Pos)
    -
    9954#define RCC_APB2RSTR_TIM11RST RCC_APB2RSTR_TIM11RST_Msk
    -
    9955
    -
    9956/* Old SPI1RST bit definition, maintained for legacy purpose */
    -
    9957#define RCC_APB2RSTR_SPI1 RCC_APB2RSTR_SPI1RST
    -
    9958
    -
    9959/******************** Bit definition for RCC_AHB1ENR register ***************/
    -
    9960#define RCC_AHB1ENR_GPIOAEN_Pos (0U)
    -
    9961#define RCC_AHB1ENR_GPIOAEN_Msk (0x1UL << RCC_AHB1ENR_GPIOAEN_Pos)
    -
    9962#define RCC_AHB1ENR_GPIOAEN RCC_AHB1ENR_GPIOAEN_Msk
    -
    9963#define RCC_AHB1ENR_GPIOBEN_Pos (1U)
    -
    9964#define RCC_AHB1ENR_GPIOBEN_Msk (0x1UL << RCC_AHB1ENR_GPIOBEN_Pos)
    -
    9965#define RCC_AHB1ENR_GPIOBEN RCC_AHB1ENR_GPIOBEN_Msk
    -
    9966#define RCC_AHB1ENR_GPIOCEN_Pos (2U)
    -
    9967#define RCC_AHB1ENR_GPIOCEN_Msk (0x1UL << RCC_AHB1ENR_GPIOCEN_Pos)
    -
    9968#define RCC_AHB1ENR_GPIOCEN RCC_AHB1ENR_GPIOCEN_Msk
    -
    9969#define RCC_AHB1ENR_GPIODEN_Pos (3U)
    -
    9970#define RCC_AHB1ENR_GPIODEN_Msk (0x1UL << RCC_AHB1ENR_GPIODEN_Pos)
    -
    9971#define RCC_AHB1ENR_GPIODEN RCC_AHB1ENR_GPIODEN_Msk
    -
    9972#define RCC_AHB1ENR_GPIOEEN_Pos (4U)
    -
    9973#define RCC_AHB1ENR_GPIOEEN_Msk (0x1UL << RCC_AHB1ENR_GPIOEEN_Pos)
    -
    9974#define RCC_AHB1ENR_GPIOEEN RCC_AHB1ENR_GPIOEEN_Msk
    -
    9975#define RCC_AHB1ENR_GPIOFEN_Pos (5U)
    -
    9976#define RCC_AHB1ENR_GPIOFEN_Msk (0x1UL << RCC_AHB1ENR_GPIOFEN_Pos)
    -
    9977#define RCC_AHB1ENR_GPIOFEN RCC_AHB1ENR_GPIOFEN_Msk
    -
    9978#define RCC_AHB1ENR_GPIOGEN_Pos (6U)
    -
    9979#define RCC_AHB1ENR_GPIOGEN_Msk (0x1UL << RCC_AHB1ENR_GPIOGEN_Pos)
    -
    9980#define RCC_AHB1ENR_GPIOGEN RCC_AHB1ENR_GPIOGEN_Msk
    -
    9981#define RCC_AHB1ENR_GPIOHEN_Pos (7U)
    -
    9982#define RCC_AHB1ENR_GPIOHEN_Msk (0x1UL << RCC_AHB1ENR_GPIOHEN_Pos)
    -
    9983#define RCC_AHB1ENR_GPIOHEN RCC_AHB1ENR_GPIOHEN_Msk
    -
    9984#define RCC_AHB1ENR_GPIOIEN_Pos (8U)
    -
    9985#define RCC_AHB1ENR_GPIOIEN_Msk (0x1UL << RCC_AHB1ENR_GPIOIEN_Pos)
    -
    9986#define RCC_AHB1ENR_GPIOIEN RCC_AHB1ENR_GPIOIEN_Msk
    -
    9987#define RCC_AHB1ENR_CRCEN_Pos (12U)
    -
    9988#define RCC_AHB1ENR_CRCEN_Msk (0x1UL << RCC_AHB1ENR_CRCEN_Pos)
    -
    9989#define RCC_AHB1ENR_CRCEN RCC_AHB1ENR_CRCEN_Msk
    -
    9990#define RCC_AHB1ENR_BKPSRAMEN_Pos (18U)
    -
    9991#define RCC_AHB1ENR_BKPSRAMEN_Msk (0x1UL << RCC_AHB1ENR_BKPSRAMEN_Pos)
    -
    9992#define RCC_AHB1ENR_BKPSRAMEN RCC_AHB1ENR_BKPSRAMEN_Msk
    -
    9993#define RCC_AHB1ENR_CCMDATARAMEN_Pos (20U)
    -
    9994#define RCC_AHB1ENR_CCMDATARAMEN_Msk (0x1UL << RCC_AHB1ENR_CCMDATARAMEN_Pos)
    -
    9995#define RCC_AHB1ENR_CCMDATARAMEN RCC_AHB1ENR_CCMDATARAMEN_Msk
    -
    9996#define RCC_AHB1ENR_DMA1EN_Pos (21U)
    -
    9997#define RCC_AHB1ENR_DMA1EN_Msk (0x1UL << RCC_AHB1ENR_DMA1EN_Pos)
    -
    9998#define RCC_AHB1ENR_DMA1EN RCC_AHB1ENR_DMA1EN_Msk
    -
    9999#define RCC_AHB1ENR_DMA2EN_Pos (22U)
    -
    10000#define RCC_AHB1ENR_DMA2EN_Msk (0x1UL << RCC_AHB1ENR_DMA2EN_Pos)
    -
    10001#define RCC_AHB1ENR_DMA2EN RCC_AHB1ENR_DMA2EN_Msk
    -
    10002#define RCC_AHB1ENR_ETHMACEN_Pos (25U)
    -
    10003#define RCC_AHB1ENR_ETHMACEN_Msk (0x1UL << RCC_AHB1ENR_ETHMACEN_Pos)
    -
    10004#define RCC_AHB1ENR_ETHMACEN RCC_AHB1ENR_ETHMACEN_Msk
    -
    10005#define RCC_AHB1ENR_ETHMACTXEN_Pos (26U)
    -
    10006#define RCC_AHB1ENR_ETHMACTXEN_Msk (0x1UL << RCC_AHB1ENR_ETHMACTXEN_Pos)
    -
    10007#define RCC_AHB1ENR_ETHMACTXEN RCC_AHB1ENR_ETHMACTXEN_Msk
    -
    10008#define RCC_AHB1ENR_ETHMACRXEN_Pos (27U)
    -
    10009#define RCC_AHB1ENR_ETHMACRXEN_Msk (0x1UL << RCC_AHB1ENR_ETHMACRXEN_Pos)
    -
    10010#define RCC_AHB1ENR_ETHMACRXEN RCC_AHB1ENR_ETHMACRXEN_Msk
    -
    10011#define RCC_AHB1ENR_ETHMACPTPEN_Pos (28U)
    -
    10012#define RCC_AHB1ENR_ETHMACPTPEN_Msk (0x1UL << RCC_AHB1ENR_ETHMACPTPEN_Pos)
    -
    10013#define RCC_AHB1ENR_ETHMACPTPEN RCC_AHB1ENR_ETHMACPTPEN_Msk
    -
    10014#define RCC_AHB1ENR_OTGHSEN_Pos (29U)
    -
    10015#define RCC_AHB1ENR_OTGHSEN_Msk (0x1UL << RCC_AHB1ENR_OTGHSEN_Pos)
    -
    10016#define RCC_AHB1ENR_OTGHSEN RCC_AHB1ENR_OTGHSEN_Msk
    -
    10017#define RCC_AHB1ENR_OTGHSULPIEN_Pos (30U)
    -
    10018#define RCC_AHB1ENR_OTGHSULPIEN_Msk (0x1UL << RCC_AHB1ENR_OTGHSULPIEN_Pos)
    -
    10019#define RCC_AHB1ENR_OTGHSULPIEN RCC_AHB1ENR_OTGHSULPIEN_Msk
    -
    10020/******************** Bit definition for RCC_AHB2ENR register ***************/
    -
    10021/*
    -
    10022 * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
    -
    10023 */
    -
    10024#define RCC_AHB2_SUPPORT
    -
    10026#define RCC_AHB2ENR_DCMIEN_Pos (0U)
    -
    10027#define RCC_AHB2ENR_DCMIEN_Msk (0x1UL << RCC_AHB2ENR_DCMIEN_Pos)
    -
    10028#define RCC_AHB2ENR_DCMIEN RCC_AHB2ENR_DCMIEN_Msk
    -
    10029#define RCC_AHB2ENR_RNGEN_Pos (6U)
    -
    10030#define RCC_AHB2ENR_RNGEN_Msk (0x1UL << RCC_AHB2ENR_RNGEN_Pos)
    -
    10031#define RCC_AHB2ENR_RNGEN RCC_AHB2ENR_RNGEN_Msk
    -
    10032#define RCC_AHB2ENR_OTGFSEN_Pos (7U)
    -
    10033#define RCC_AHB2ENR_OTGFSEN_Msk (0x1UL << RCC_AHB2ENR_OTGFSEN_Pos)
    -
    10034#define RCC_AHB2ENR_OTGFSEN RCC_AHB2ENR_OTGFSEN_Msk
    -
    10035
    -
    10036/******************** Bit definition for RCC_AHB3ENR register ***************/
    -
    10037/*
    -
    10038 * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
    -
    10039 */
    -
    10040#define RCC_AHB3_SUPPORT
    -
    10042#define RCC_AHB3ENR_FSMCEN_Pos (0U)
    -
    10043#define RCC_AHB3ENR_FSMCEN_Msk (0x1UL << RCC_AHB3ENR_FSMCEN_Pos)
    -
    10044#define RCC_AHB3ENR_FSMCEN RCC_AHB3ENR_FSMCEN_Msk
    -
    10045
    -
    10046/******************** Bit definition for RCC_APB1ENR register ***************/
    -
    10047#define RCC_APB1ENR_TIM2EN_Pos (0U)
    -
    10048#define RCC_APB1ENR_TIM2EN_Msk (0x1UL << RCC_APB1ENR_TIM2EN_Pos)
    -
    10049#define RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk
    -
    10050#define RCC_APB1ENR_TIM3EN_Pos (1U)
    -
    10051#define RCC_APB1ENR_TIM3EN_Msk (0x1UL << RCC_APB1ENR_TIM3EN_Pos)
    -
    10052#define RCC_APB1ENR_TIM3EN RCC_APB1ENR_TIM3EN_Msk
    -
    10053#define RCC_APB1ENR_TIM4EN_Pos (2U)
    -
    10054#define RCC_APB1ENR_TIM4EN_Msk (0x1UL << RCC_APB1ENR_TIM4EN_Pos)
    -
    10055#define RCC_APB1ENR_TIM4EN RCC_APB1ENR_TIM4EN_Msk
    -
    10056#define RCC_APB1ENR_TIM5EN_Pos (3U)
    -
    10057#define RCC_APB1ENR_TIM5EN_Msk (0x1UL << RCC_APB1ENR_TIM5EN_Pos)
    -
    10058#define RCC_APB1ENR_TIM5EN RCC_APB1ENR_TIM5EN_Msk
    -
    10059#define RCC_APB1ENR_TIM6EN_Pos (4U)
    -
    10060#define RCC_APB1ENR_TIM6EN_Msk (0x1UL << RCC_APB1ENR_TIM6EN_Pos)
    -
    10061#define RCC_APB1ENR_TIM6EN RCC_APB1ENR_TIM6EN_Msk
    -
    10062#define RCC_APB1ENR_TIM7EN_Pos (5U)
    -
    10063#define RCC_APB1ENR_TIM7EN_Msk (0x1UL << RCC_APB1ENR_TIM7EN_Pos)
    -
    10064#define RCC_APB1ENR_TIM7EN RCC_APB1ENR_TIM7EN_Msk
    -
    10065#define RCC_APB1ENR_TIM12EN_Pos (6U)
    -
    10066#define RCC_APB1ENR_TIM12EN_Msk (0x1UL << RCC_APB1ENR_TIM12EN_Pos)
    -
    10067#define RCC_APB1ENR_TIM12EN RCC_APB1ENR_TIM12EN_Msk
    -
    10068#define RCC_APB1ENR_TIM13EN_Pos (7U)
    -
    10069#define RCC_APB1ENR_TIM13EN_Msk (0x1UL << RCC_APB1ENR_TIM13EN_Pos)
    -
    10070#define RCC_APB1ENR_TIM13EN RCC_APB1ENR_TIM13EN_Msk
    -
    10071#define RCC_APB1ENR_TIM14EN_Pos (8U)
    -
    10072#define RCC_APB1ENR_TIM14EN_Msk (0x1UL << RCC_APB1ENR_TIM14EN_Pos)
    -
    10073#define RCC_APB1ENR_TIM14EN RCC_APB1ENR_TIM14EN_Msk
    -
    10074#define RCC_APB1ENR_WWDGEN_Pos (11U)
    -
    10075#define RCC_APB1ENR_WWDGEN_Msk (0x1UL << RCC_APB1ENR_WWDGEN_Pos)
    -
    10076#define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk
    -
    10077#define RCC_APB1ENR_SPI2EN_Pos (14U)
    -
    10078#define RCC_APB1ENR_SPI2EN_Msk (0x1UL << RCC_APB1ENR_SPI2EN_Pos)
    -
    10079#define RCC_APB1ENR_SPI2EN RCC_APB1ENR_SPI2EN_Msk
    -
    10080#define RCC_APB1ENR_SPI3EN_Pos (15U)
    -
    10081#define RCC_APB1ENR_SPI3EN_Msk (0x1UL << RCC_APB1ENR_SPI3EN_Pos)
    -
    10082#define RCC_APB1ENR_SPI3EN RCC_APB1ENR_SPI3EN_Msk
    -
    10083#define RCC_APB1ENR_USART2EN_Pos (17U)
    -
    10084#define RCC_APB1ENR_USART2EN_Msk (0x1UL << RCC_APB1ENR_USART2EN_Pos)
    -
    10085#define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk
    -
    10086#define RCC_APB1ENR_USART3EN_Pos (18U)
    -
    10087#define RCC_APB1ENR_USART3EN_Msk (0x1UL << RCC_APB1ENR_USART3EN_Pos)
    -
    10088#define RCC_APB1ENR_USART3EN RCC_APB1ENR_USART3EN_Msk
    -
    10089#define RCC_APB1ENR_UART4EN_Pos (19U)
    -
    10090#define RCC_APB1ENR_UART4EN_Msk (0x1UL << RCC_APB1ENR_UART4EN_Pos)
    -
    10091#define RCC_APB1ENR_UART4EN RCC_APB1ENR_UART4EN_Msk
    -
    10092#define RCC_APB1ENR_UART5EN_Pos (20U)
    -
    10093#define RCC_APB1ENR_UART5EN_Msk (0x1UL << RCC_APB1ENR_UART5EN_Pos)
    -
    10094#define RCC_APB1ENR_UART5EN RCC_APB1ENR_UART5EN_Msk
    -
    10095#define RCC_APB1ENR_I2C1EN_Pos (21U)
    -
    10096#define RCC_APB1ENR_I2C1EN_Msk (0x1UL << RCC_APB1ENR_I2C1EN_Pos)
    -
    10097#define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk
    -
    10098#define RCC_APB1ENR_I2C2EN_Pos (22U)
    -
    10099#define RCC_APB1ENR_I2C2EN_Msk (0x1UL << RCC_APB1ENR_I2C2EN_Pos)
    -
    10100#define RCC_APB1ENR_I2C2EN RCC_APB1ENR_I2C2EN_Msk
    -
    10101#define RCC_APB1ENR_I2C3EN_Pos (23U)
    -
    10102#define RCC_APB1ENR_I2C3EN_Msk (0x1UL << RCC_APB1ENR_I2C3EN_Pos)
    -
    10103#define RCC_APB1ENR_I2C3EN RCC_APB1ENR_I2C3EN_Msk
    -
    10104#define RCC_APB1ENR_CAN1EN_Pos (25U)
    -
    10105#define RCC_APB1ENR_CAN1EN_Msk (0x1UL << RCC_APB1ENR_CAN1EN_Pos)
    -
    10106#define RCC_APB1ENR_CAN1EN RCC_APB1ENR_CAN1EN_Msk
    -
    10107#define RCC_APB1ENR_CAN2EN_Pos (26U)
    -
    10108#define RCC_APB1ENR_CAN2EN_Msk (0x1UL << RCC_APB1ENR_CAN2EN_Pos)
    -
    10109#define RCC_APB1ENR_CAN2EN RCC_APB1ENR_CAN2EN_Msk
    -
    10110#define RCC_APB1ENR_PWREN_Pos (28U)
    -
    10111#define RCC_APB1ENR_PWREN_Msk (0x1UL << RCC_APB1ENR_PWREN_Pos)
    -
    10112#define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk
    -
    10113#define RCC_APB1ENR_DACEN_Pos (29U)
    -
    10114#define RCC_APB1ENR_DACEN_Msk (0x1UL << RCC_APB1ENR_DACEN_Pos)
    -
    10115#define RCC_APB1ENR_DACEN RCC_APB1ENR_DACEN_Msk
    -
    10116
    -
    10117/******************** Bit definition for RCC_APB2ENR register ***************/
    -
    10118#define RCC_APB2ENR_TIM1EN_Pos (0U)
    -
    10119#define RCC_APB2ENR_TIM1EN_Msk (0x1UL << RCC_APB2ENR_TIM1EN_Pos)
    -
    10120#define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk
    -
    10121#define RCC_APB2ENR_TIM8EN_Pos (1U)
    -
    10122#define RCC_APB2ENR_TIM8EN_Msk (0x1UL << RCC_APB2ENR_TIM8EN_Pos)
    -
    10123#define RCC_APB2ENR_TIM8EN RCC_APB2ENR_TIM8EN_Msk
    -
    10124#define RCC_APB2ENR_USART1EN_Pos (4U)
    -
    10125#define RCC_APB2ENR_USART1EN_Msk (0x1UL << RCC_APB2ENR_USART1EN_Pos)
    -
    10126#define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk
    -
    10127#define RCC_APB2ENR_USART6EN_Pos (5U)
    -
    10128#define RCC_APB2ENR_USART6EN_Msk (0x1UL << RCC_APB2ENR_USART6EN_Pos)
    -
    10129#define RCC_APB2ENR_USART6EN RCC_APB2ENR_USART6EN_Msk
    -
    10130#define RCC_APB2ENR_ADC1EN_Pos (8U)
    -
    10131#define RCC_APB2ENR_ADC1EN_Msk (0x1UL << RCC_APB2ENR_ADC1EN_Pos)
    -
    10132#define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADC1EN_Msk
    -
    10133#define RCC_APB2ENR_ADC2EN_Pos (9U)
    -
    10134#define RCC_APB2ENR_ADC2EN_Msk (0x1UL << RCC_APB2ENR_ADC2EN_Pos)
    -
    10135#define RCC_APB2ENR_ADC2EN RCC_APB2ENR_ADC2EN_Msk
    -
    10136#define RCC_APB2ENR_ADC3EN_Pos (10U)
    -
    10137#define RCC_APB2ENR_ADC3EN_Msk (0x1UL << RCC_APB2ENR_ADC3EN_Pos)
    -
    10138#define RCC_APB2ENR_ADC3EN RCC_APB2ENR_ADC3EN_Msk
    -
    10139#define RCC_APB2ENR_SDIOEN_Pos (11U)
    -
    10140#define RCC_APB2ENR_SDIOEN_Msk (0x1UL << RCC_APB2ENR_SDIOEN_Pos)
    -
    10141#define RCC_APB2ENR_SDIOEN RCC_APB2ENR_SDIOEN_Msk
    -
    10142#define RCC_APB2ENR_SPI1EN_Pos (12U)
    -
    10143#define RCC_APB2ENR_SPI1EN_Msk (0x1UL << RCC_APB2ENR_SPI1EN_Pos)
    -
    10144#define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk
    -
    10145#define RCC_APB2ENR_SYSCFGEN_Pos (14U)
    -
    10146#define RCC_APB2ENR_SYSCFGEN_Msk (0x1UL << RCC_APB2ENR_SYSCFGEN_Pos)
    -
    10147#define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGEN_Msk
    -
    10148#define RCC_APB2ENR_TIM9EN_Pos (16U)
    -
    10149#define RCC_APB2ENR_TIM9EN_Msk (0x1UL << RCC_APB2ENR_TIM9EN_Pos)
    -
    10150#define RCC_APB2ENR_TIM9EN RCC_APB2ENR_TIM9EN_Msk
    -
    10151#define RCC_APB2ENR_TIM10EN_Pos (17U)
    -
    10152#define RCC_APB2ENR_TIM10EN_Msk (0x1UL << RCC_APB2ENR_TIM10EN_Pos)
    -
    10153#define RCC_APB2ENR_TIM10EN RCC_APB2ENR_TIM10EN_Msk
    -
    10154#define RCC_APB2ENR_TIM11EN_Pos (18U)
    -
    10155#define RCC_APB2ENR_TIM11EN_Msk (0x1UL << RCC_APB2ENR_TIM11EN_Pos)
    -
    10156#define RCC_APB2ENR_TIM11EN RCC_APB2ENR_TIM11EN_Msk
    -
    10157
    -
    10158/******************** Bit definition for RCC_AHB1LPENR register *************/
    -
    10159#define RCC_AHB1LPENR_GPIOALPEN_Pos (0U)
    -
    10160#define RCC_AHB1LPENR_GPIOALPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOALPEN_Pos)
    -
    10161#define RCC_AHB1LPENR_GPIOALPEN RCC_AHB1LPENR_GPIOALPEN_Msk
    -
    10162#define RCC_AHB1LPENR_GPIOBLPEN_Pos (1U)
    -
    10163#define RCC_AHB1LPENR_GPIOBLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOBLPEN_Pos)
    -
    10164#define RCC_AHB1LPENR_GPIOBLPEN RCC_AHB1LPENR_GPIOBLPEN_Msk
    -
    10165#define RCC_AHB1LPENR_GPIOCLPEN_Pos (2U)
    -
    10166#define RCC_AHB1LPENR_GPIOCLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOCLPEN_Pos)
    -
    10167#define RCC_AHB1LPENR_GPIOCLPEN RCC_AHB1LPENR_GPIOCLPEN_Msk
    -
    10168#define RCC_AHB1LPENR_GPIODLPEN_Pos (3U)
    -
    10169#define RCC_AHB1LPENR_GPIODLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIODLPEN_Pos)
    -
    10170#define RCC_AHB1LPENR_GPIODLPEN RCC_AHB1LPENR_GPIODLPEN_Msk
    -
    10171#define RCC_AHB1LPENR_GPIOELPEN_Pos (4U)
    -
    10172#define RCC_AHB1LPENR_GPIOELPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOELPEN_Pos)
    -
    10173#define RCC_AHB1LPENR_GPIOELPEN RCC_AHB1LPENR_GPIOELPEN_Msk
    -
    10174#define RCC_AHB1LPENR_GPIOFLPEN_Pos (5U)
    -
    10175#define RCC_AHB1LPENR_GPIOFLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOFLPEN_Pos)
    -
    10176#define RCC_AHB1LPENR_GPIOFLPEN RCC_AHB1LPENR_GPIOFLPEN_Msk
    -
    10177#define RCC_AHB1LPENR_GPIOGLPEN_Pos (6U)
    -
    10178#define RCC_AHB1LPENR_GPIOGLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOGLPEN_Pos)
    -
    10179#define RCC_AHB1LPENR_GPIOGLPEN RCC_AHB1LPENR_GPIOGLPEN_Msk
    -
    10180#define RCC_AHB1LPENR_GPIOHLPEN_Pos (7U)
    -
    10181#define RCC_AHB1LPENR_GPIOHLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOHLPEN_Pos)
    -
    10182#define RCC_AHB1LPENR_GPIOHLPEN RCC_AHB1LPENR_GPIOHLPEN_Msk
    -
    10183#define RCC_AHB1LPENR_GPIOILPEN_Pos (8U)
    -
    10184#define RCC_AHB1LPENR_GPIOILPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOILPEN_Pos)
    -
    10185#define RCC_AHB1LPENR_GPIOILPEN RCC_AHB1LPENR_GPIOILPEN_Msk
    -
    10186#define RCC_AHB1LPENR_CRCLPEN_Pos (12U)
    -
    10187#define RCC_AHB1LPENR_CRCLPEN_Msk (0x1UL << RCC_AHB1LPENR_CRCLPEN_Pos)
    -
    10188#define RCC_AHB1LPENR_CRCLPEN RCC_AHB1LPENR_CRCLPEN_Msk
    -
    10189#define RCC_AHB1LPENR_FLITFLPEN_Pos (15U)
    -
    10190#define RCC_AHB1LPENR_FLITFLPEN_Msk (0x1UL << RCC_AHB1LPENR_FLITFLPEN_Pos)
    -
    10191#define RCC_AHB1LPENR_FLITFLPEN RCC_AHB1LPENR_FLITFLPEN_Msk
    -
    10192#define RCC_AHB1LPENR_SRAM1LPEN_Pos (16U)
    -
    10193#define RCC_AHB1LPENR_SRAM1LPEN_Msk (0x1UL << RCC_AHB1LPENR_SRAM1LPEN_Pos)
    -
    10194#define RCC_AHB1LPENR_SRAM1LPEN RCC_AHB1LPENR_SRAM1LPEN_Msk
    -
    10195#define RCC_AHB1LPENR_SRAM2LPEN_Pos (17U)
    -
    10196#define RCC_AHB1LPENR_SRAM2LPEN_Msk (0x1UL << RCC_AHB1LPENR_SRAM2LPEN_Pos)
    -
    10197#define RCC_AHB1LPENR_SRAM2LPEN RCC_AHB1LPENR_SRAM2LPEN_Msk
    -
    10198#define RCC_AHB1LPENR_BKPSRAMLPEN_Pos (18U)
    -
    10199#define RCC_AHB1LPENR_BKPSRAMLPEN_Msk (0x1UL << RCC_AHB1LPENR_BKPSRAMLPEN_Pos)
    -
    10200#define RCC_AHB1LPENR_BKPSRAMLPEN RCC_AHB1LPENR_BKPSRAMLPEN_Msk
    -
    10201#define RCC_AHB1LPENR_DMA1LPEN_Pos (21U)
    -
    10202#define RCC_AHB1LPENR_DMA1LPEN_Msk (0x1UL << RCC_AHB1LPENR_DMA1LPEN_Pos)
    -
    10203#define RCC_AHB1LPENR_DMA1LPEN RCC_AHB1LPENR_DMA1LPEN_Msk
    -
    10204#define RCC_AHB1LPENR_DMA2LPEN_Pos (22U)
    -
    10205#define RCC_AHB1LPENR_DMA2LPEN_Msk (0x1UL << RCC_AHB1LPENR_DMA2LPEN_Pos)
    -
    10206#define RCC_AHB1LPENR_DMA2LPEN RCC_AHB1LPENR_DMA2LPEN_Msk
    -
    10207
    -
    10208#define RCC_AHB1LPENR_ETHMACLPEN_Pos (25U)
    -
    10209#define RCC_AHB1LPENR_ETHMACLPEN_Msk (0x1UL << RCC_AHB1LPENR_ETHMACLPEN_Pos)
    -
    10210#define RCC_AHB1LPENR_ETHMACLPEN RCC_AHB1LPENR_ETHMACLPEN_Msk
    -
    10211#define RCC_AHB1LPENR_ETHMACTXLPEN_Pos (26U)
    -
    10212#define RCC_AHB1LPENR_ETHMACTXLPEN_Msk (0x1UL << RCC_AHB1LPENR_ETHMACTXLPEN_Pos)
    -
    10213#define RCC_AHB1LPENR_ETHMACTXLPEN RCC_AHB1LPENR_ETHMACTXLPEN_Msk
    -
    10214#define RCC_AHB1LPENR_ETHMACRXLPEN_Pos (27U)
    -
    10215#define RCC_AHB1LPENR_ETHMACRXLPEN_Msk (0x1UL << RCC_AHB1LPENR_ETHMACRXLPEN_Pos)
    -
    10216#define RCC_AHB1LPENR_ETHMACRXLPEN RCC_AHB1LPENR_ETHMACRXLPEN_Msk
    -
    10217#define RCC_AHB1LPENR_ETHMACPTPLPEN_Pos (28U)
    -
    10218#define RCC_AHB1LPENR_ETHMACPTPLPEN_Msk (0x1UL << RCC_AHB1LPENR_ETHMACPTPLPEN_Pos)
    -
    10219#define RCC_AHB1LPENR_ETHMACPTPLPEN RCC_AHB1LPENR_ETHMACPTPLPEN_Msk
    -
    10220#define RCC_AHB1LPENR_OTGHSLPEN_Pos (29U)
    -
    10221#define RCC_AHB1LPENR_OTGHSLPEN_Msk (0x1UL << RCC_AHB1LPENR_OTGHSLPEN_Pos)
    -
    10222#define RCC_AHB1LPENR_OTGHSLPEN RCC_AHB1LPENR_OTGHSLPEN_Msk
    -
    10223#define RCC_AHB1LPENR_OTGHSULPILPEN_Pos (30U)
    -
    10224#define RCC_AHB1LPENR_OTGHSULPILPEN_Msk (0x1UL << RCC_AHB1LPENR_OTGHSULPILPEN_Pos)
    -
    10225#define RCC_AHB1LPENR_OTGHSULPILPEN RCC_AHB1LPENR_OTGHSULPILPEN_Msk
    -
    10226
    -
    10227/******************** Bit definition for RCC_AHB2LPENR register *************/
    -
    10228#define RCC_AHB2LPENR_DCMILPEN_Pos (0U)
    -
    10229#define RCC_AHB2LPENR_DCMILPEN_Msk (0x1UL << RCC_AHB2LPENR_DCMILPEN_Pos)
    -
    10230#define RCC_AHB2LPENR_DCMILPEN RCC_AHB2LPENR_DCMILPEN_Msk
    -
    10231#define RCC_AHB2LPENR_RNGLPEN_Pos (6U)
    -
    10232#define RCC_AHB2LPENR_RNGLPEN_Msk (0x1UL << RCC_AHB2LPENR_RNGLPEN_Pos)
    -
    10233#define RCC_AHB2LPENR_RNGLPEN RCC_AHB2LPENR_RNGLPEN_Msk
    -
    10234#define RCC_AHB2LPENR_OTGFSLPEN_Pos (7U)
    -
    10235#define RCC_AHB2LPENR_OTGFSLPEN_Msk (0x1UL << RCC_AHB2LPENR_OTGFSLPEN_Pos)
    -
    10236#define RCC_AHB2LPENR_OTGFSLPEN RCC_AHB2LPENR_OTGFSLPEN_Msk
    -
    10237
    -
    10238/******************** Bit definition for RCC_AHB3LPENR register *************/
    -
    10239#define RCC_AHB3LPENR_FSMCLPEN_Pos (0U)
    -
    10240#define RCC_AHB3LPENR_FSMCLPEN_Msk (0x1UL << RCC_AHB3LPENR_FSMCLPEN_Pos)
    -
    10241#define RCC_AHB3LPENR_FSMCLPEN RCC_AHB3LPENR_FSMCLPEN_Msk
    -
    10242
    -
    10243/******************** Bit definition for RCC_APB1LPENR register *************/
    -
    10244#define RCC_APB1LPENR_TIM2LPEN_Pos (0U)
    -
    10245#define RCC_APB1LPENR_TIM2LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM2LPEN_Pos)
    -
    10246#define RCC_APB1LPENR_TIM2LPEN RCC_APB1LPENR_TIM2LPEN_Msk
    -
    10247#define RCC_APB1LPENR_TIM3LPEN_Pos (1U)
    -
    10248#define RCC_APB1LPENR_TIM3LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM3LPEN_Pos)
    -
    10249#define RCC_APB1LPENR_TIM3LPEN RCC_APB1LPENR_TIM3LPEN_Msk
    -
    10250#define RCC_APB1LPENR_TIM4LPEN_Pos (2U)
    -
    10251#define RCC_APB1LPENR_TIM4LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM4LPEN_Pos)
    -
    10252#define RCC_APB1LPENR_TIM4LPEN RCC_APB1LPENR_TIM4LPEN_Msk
    -
    10253#define RCC_APB1LPENR_TIM5LPEN_Pos (3U)
    -
    10254#define RCC_APB1LPENR_TIM5LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM5LPEN_Pos)
    -
    10255#define RCC_APB1LPENR_TIM5LPEN RCC_APB1LPENR_TIM5LPEN_Msk
    -
    10256#define RCC_APB1LPENR_TIM6LPEN_Pos (4U)
    -
    10257#define RCC_APB1LPENR_TIM6LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM6LPEN_Pos)
    -
    10258#define RCC_APB1LPENR_TIM6LPEN RCC_APB1LPENR_TIM6LPEN_Msk
    -
    10259#define RCC_APB1LPENR_TIM7LPEN_Pos (5U)
    -
    10260#define RCC_APB1LPENR_TIM7LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM7LPEN_Pos)
    -
    10261#define RCC_APB1LPENR_TIM7LPEN RCC_APB1LPENR_TIM7LPEN_Msk
    -
    10262#define RCC_APB1LPENR_TIM12LPEN_Pos (6U)
    -
    10263#define RCC_APB1LPENR_TIM12LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM12LPEN_Pos)
    -
    10264#define RCC_APB1LPENR_TIM12LPEN RCC_APB1LPENR_TIM12LPEN_Msk
    -
    10265#define RCC_APB1LPENR_TIM13LPEN_Pos (7U)
    -
    10266#define RCC_APB1LPENR_TIM13LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM13LPEN_Pos)
    -
    10267#define RCC_APB1LPENR_TIM13LPEN RCC_APB1LPENR_TIM13LPEN_Msk
    -
    10268#define RCC_APB1LPENR_TIM14LPEN_Pos (8U)
    -
    10269#define RCC_APB1LPENR_TIM14LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM14LPEN_Pos)
    -
    10270#define RCC_APB1LPENR_TIM14LPEN RCC_APB1LPENR_TIM14LPEN_Msk
    -
    10271#define RCC_APB1LPENR_WWDGLPEN_Pos (11U)
    -
    10272#define RCC_APB1LPENR_WWDGLPEN_Msk (0x1UL << RCC_APB1LPENR_WWDGLPEN_Pos)
    -
    10273#define RCC_APB1LPENR_WWDGLPEN RCC_APB1LPENR_WWDGLPEN_Msk
    -
    10274#define RCC_APB1LPENR_SPI2LPEN_Pos (14U)
    -
    10275#define RCC_APB1LPENR_SPI2LPEN_Msk (0x1UL << RCC_APB1LPENR_SPI2LPEN_Pos)
    -
    10276#define RCC_APB1LPENR_SPI2LPEN RCC_APB1LPENR_SPI2LPEN_Msk
    -
    10277#define RCC_APB1LPENR_SPI3LPEN_Pos (15U)
    -
    10278#define RCC_APB1LPENR_SPI3LPEN_Msk (0x1UL << RCC_APB1LPENR_SPI3LPEN_Pos)
    -
    10279#define RCC_APB1LPENR_SPI3LPEN RCC_APB1LPENR_SPI3LPEN_Msk
    -
    10280#define RCC_APB1LPENR_USART2LPEN_Pos (17U)
    -
    10281#define RCC_APB1LPENR_USART2LPEN_Msk (0x1UL << RCC_APB1LPENR_USART2LPEN_Pos)
    -
    10282#define RCC_APB1LPENR_USART2LPEN RCC_APB1LPENR_USART2LPEN_Msk
    -
    10283#define RCC_APB1LPENR_USART3LPEN_Pos (18U)
    -
    10284#define RCC_APB1LPENR_USART3LPEN_Msk (0x1UL << RCC_APB1LPENR_USART3LPEN_Pos)
    -
    10285#define RCC_APB1LPENR_USART3LPEN RCC_APB1LPENR_USART3LPEN_Msk
    -
    10286#define RCC_APB1LPENR_UART4LPEN_Pos (19U)
    -
    10287#define RCC_APB1LPENR_UART4LPEN_Msk (0x1UL << RCC_APB1LPENR_UART4LPEN_Pos)
    -
    10288#define RCC_APB1LPENR_UART4LPEN RCC_APB1LPENR_UART4LPEN_Msk
    -
    10289#define RCC_APB1LPENR_UART5LPEN_Pos (20U)
    -
    10290#define RCC_APB1LPENR_UART5LPEN_Msk (0x1UL << RCC_APB1LPENR_UART5LPEN_Pos)
    -
    10291#define RCC_APB1LPENR_UART5LPEN RCC_APB1LPENR_UART5LPEN_Msk
    -
    10292#define RCC_APB1LPENR_I2C1LPEN_Pos (21U)
    -
    10293#define RCC_APB1LPENR_I2C1LPEN_Msk (0x1UL << RCC_APB1LPENR_I2C1LPEN_Pos)
    -
    10294#define RCC_APB1LPENR_I2C1LPEN RCC_APB1LPENR_I2C1LPEN_Msk
    -
    10295#define RCC_APB1LPENR_I2C2LPEN_Pos (22U)
    -
    10296#define RCC_APB1LPENR_I2C2LPEN_Msk (0x1UL << RCC_APB1LPENR_I2C2LPEN_Pos)
    -
    10297#define RCC_APB1LPENR_I2C2LPEN RCC_APB1LPENR_I2C2LPEN_Msk
    -
    10298#define RCC_APB1LPENR_I2C3LPEN_Pos (23U)
    -
    10299#define RCC_APB1LPENR_I2C3LPEN_Msk (0x1UL << RCC_APB1LPENR_I2C3LPEN_Pos)
    -
    10300#define RCC_APB1LPENR_I2C3LPEN RCC_APB1LPENR_I2C3LPEN_Msk
    -
    10301#define RCC_APB1LPENR_CAN1LPEN_Pos (25U)
    -
    10302#define RCC_APB1LPENR_CAN1LPEN_Msk (0x1UL << RCC_APB1LPENR_CAN1LPEN_Pos)
    -
    10303#define RCC_APB1LPENR_CAN1LPEN RCC_APB1LPENR_CAN1LPEN_Msk
    -
    10304#define RCC_APB1LPENR_CAN2LPEN_Pos (26U)
    -
    10305#define RCC_APB1LPENR_CAN2LPEN_Msk (0x1UL << RCC_APB1LPENR_CAN2LPEN_Pos)
    -
    10306#define RCC_APB1LPENR_CAN2LPEN RCC_APB1LPENR_CAN2LPEN_Msk
    -
    10307#define RCC_APB1LPENR_PWRLPEN_Pos (28U)
    -
    10308#define RCC_APB1LPENR_PWRLPEN_Msk (0x1UL << RCC_APB1LPENR_PWRLPEN_Pos)
    -
    10309#define RCC_APB1LPENR_PWRLPEN RCC_APB1LPENR_PWRLPEN_Msk
    -
    10310#define RCC_APB1LPENR_DACLPEN_Pos (29U)
    -
    10311#define RCC_APB1LPENR_DACLPEN_Msk (0x1UL << RCC_APB1LPENR_DACLPEN_Pos)
    -
    10312#define RCC_APB1LPENR_DACLPEN RCC_APB1LPENR_DACLPEN_Msk
    -
    10313
    -
    10314/******************** Bit definition for RCC_APB2LPENR register *************/
    -
    10315#define RCC_APB2LPENR_TIM1LPEN_Pos (0U)
    -
    10316#define RCC_APB2LPENR_TIM1LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM1LPEN_Pos)
    -
    10317#define RCC_APB2LPENR_TIM1LPEN RCC_APB2LPENR_TIM1LPEN_Msk
    -
    10318#define RCC_APB2LPENR_TIM8LPEN_Pos (1U)
    -
    10319#define RCC_APB2LPENR_TIM8LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM8LPEN_Pos)
    -
    10320#define RCC_APB2LPENR_TIM8LPEN RCC_APB2LPENR_TIM8LPEN_Msk
    -
    10321#define RCC_APB2LPENR_USART1LPEN_Pos (4U)
    -
    10322#define RCC_APB2LPENR_USART1LPEN_Msk (0x1UL << RCC_APB2LPENR_USART1LPEN_Pos)
    -
    10323#define RCC_APB2LPENR_USART1LPEN RCC_APB2LPENR_USART1LPEN_Msk
    -
    10324#define RCC_APB2LPENR_USART6LPEN_Pos (5U)
    -
    10325#define RCC_APB2LPENR_USART6LPEN_Msk (0x1UL << RCC_APB2LPENR_USART6LPEN_Pos)
    -
    10326#define RCC_APB2LPENR_USART6LPEN RCC_APB2LPENR_USART6LPEN_Msk
    -
    10327#define RCC_APB2LPENR_ADC1LPEN_Pos (8U)
    -
    10328#define RCC_APB2LPENR_ADC1LPEN_Msk (0x1UL << RCC_APB2LPENR_ADC1LPEN_Pos)
    -
    10329#define RCC_APB2LPENR_ADC1LPEN RCC_APB2LPENR_ADC1LPEN_Msk
    -
    10330#define RCC_APB2LPENR_ADC2LPEN_Pos (9U)
    -
    10331#define RCC_APB2LPENR_ADC2LPEN_Msk (0x1UL << RCC_APB2LPENR_ADC2LPEN_Pos)
    -
    10332#define RCC_APB2LPENR_ADC2LPEN RCC_APB2LPENR_ADC2LPEN_Msk
    -
    10333#define RCC_APB2LPENR_ADC3LPEN_Pos (10U)
    -
    10334#define RCC_APB2LPENR_ADC3LPEN_Msk (0x1UL << RCC_APB2LPENR_ADC3LPEN_Pos)
    -
    10335#define RCC_APB2LPENR_ADC3LPEN RCC_APB2LPENR_ADC3LPEN_Msk
    -
    10336#define RCC_APB2LPENR_SDIOLPEN_Pos (11U)
    -
    10337#define RCC_APB2LPENR_SDIOLPEN_Msk (0x1UL << RCC_APB2LPENR_SDIOLPEN_Pos)
    -
    10338#define RCC_APB2LPENR_SDIOLPEN RCC_APB2LPENR_SDIOLPEN_Msk
    -
    10339#define RCC_APB2LPENR_SPI1LPEN_Pos (12U)
    -
    10340#define RCC_APB2LPENR_SPI1LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI1LPEN_Pos)
    -
    10341#define RCC_APB2LPENR_SPI1LPEN RCC_APB2LPENR_SPI1LPEN_Msk
    -
    10342#define RCC_APB2LPENR_SYSCFGLPEN_Pos (14U)
    -
    10343#define RCC_APB2LPENR_SYSCFGLPEN_Msk (0x1UL << RCC_APB2LPENR_SYSCFGLPEN_Pos)
    -
    10344#define RCC_APB2LPENR_SYSCFGLPEN RCC_APB2LPENR_SYSCFGLPEN_Msk
    -
    10345#define RCC_APB2LPENR_TIM9LPEN_Pos (16U)
    -
    10346#define RCC_APB2LPENR_TIM9LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM9LPEN_Pos)
    -
    10347#define RCC_APB2LPENR_TIM9LPEN RCC_APB2LPENR_TIM9LPEN_Msk
    -
    10348#define RCC_APB2LPENR_TIM10LPEN_Pos (17U)
    -
    10349#define RCC_APB2LPENR_TIM10LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM10LPEN_Pos)
    -
    10350#define RCC_APB2LPENR_TIM10LPEN RCC_APB2LPENR_TIM10LPEN_Msk
    -
    10351#define RCC_APB2LPENR_TIM11LPEN_Pos (18U)
    -
    10352#define RCC_APB2LPENR_TIM11LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM11LPEN_Pos)
    -
    10353#define RCC_APB2LPENR_TIM11LPEN RCC_APB2LPENR_TIM11LPEN_Msk
    -
    10354
    -
    10355/******************** Bit definition for RCC_BDCR register ******************/
    -
    10356#define RCC_BDCR_LSEON_Pos (0U)
    -
    10357#define RCC_BDCR_LSEON_Msk (0x1UL << RCC_BDCR_LSEON_Pos)
    -
    10358#define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk
    -
    10359#define RCC_BDCR_LSERDY_Pos (1U)
    -
    10360#define RCC_BDCR_LSERDY_Msk (0x1UL << RCC_BDCR_LSERDY_Pos)
    -
    10361#define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk
    -
    10362#define RCC_BDCR_LSEBYP_Pos (2U)
    -
    10363#define RCC_BDCR_LSEBYP_Msk (0x1UL << RCC_BDCR_LSEBYP_Pos)
    -
    10364#define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk
    -
    10365
    -
    10366#define RCC_BDCR_RTCSEL_Pos (8U)
    -
    10367#define RCC_BDCR_RTCSEL_Msk (0x3UL << RCC_BDCR_RTCSEL_Pos)
    -
    10368#define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk
    -
    10369#define RCC_BDCR_RTCSEL_0 (0x1UL << RCC_BDCR_RTCSEL_Pos)
    -
    10370#define RCC_BDCR_RTCSEL_1 (0x2UL << RCC_BDCR_RTCSEL_Pos)
    -
    10372#define RCC_BDCR_RTCEN_Pos (15U)
    -
    10373#define RCC_BDCR_RTCEN_Msk (0x1UL << RCC_BDCR_RTCEN_Pos)
    -
    10374#define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk
    -
    10375#define RCC_BDCR_BDRST_Pos (16U)
    -
    10376#define RCC_BDCR_BDRST_Msk (0x1UL << RCC_BDCR_BDRST_Pos)
    -
    10377#define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk
    -
    10378
    -
    10379/******************** Bit definition for RCC_CSR register *******************/
    -
    10380#define RCC_CSR_LSION_Pos (0U)
    -
    10381#define RCC_CSR_LSION_Msk (0x1UL << RCC_CSR_LSION_Pos)
    -
    10382#define RCC_CSR_LSION RCC_CSR_LSION_Msk
    -
    10383#define RCC_CSR_LSIRDY_Pos (1U)
    -
    10384#define RCC_CSR_LSIRDY_Msk (0x1UL << RCC_CSR_LSIRDY_Pos)
    -
    10385#define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk
    -
    10386#define RCC_CSR_RMVF_Pos (24U)
    -
    10387#define RCC_CSR_RMVF_Msk (0x1UL << RCC_CSR_RMVF_Pos)
    -
    10388#define RCC_CSR_RMVF RCC_CSR_RMVF_Msk
    -
    10389#define RCC_CSR_BORRSTF_Pos (25U)
    -
    10390#define RCC_CSR_BORRSTF_Msk (0x1UL << RCC_CSR_BORRSTF_Pos)
    -
    10391#define RCC_CSR_BORRSTF RCC_CSR_BORRSTF_Msk
    -
    10392#define RCC_CSR_PINRSTF_Pos (26U)
    -
    10393#define RCC_CSR_PINRSTF_Msk (0x1UL << RCC_CSR_PINRSTF_Pos)
    -
    10394#define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk
    -
    10395#define RCC_CSR_PORRSTF_Pos (27U)
    -
    10396#define RCC_CSR_PORRSTF_Msk (0x1UL << RCC_CSR_PORRSTF_Pos)
    -
    10397#define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk
    -
    10398#define RCC_CSR_SFTRSTF_Pos (28U)
    -
    10399#define RCC_CSR_SFTRSTF_Msk (0x1UL << RCC_CSR_SFTRSTF_Pos)
    -
    10400#define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk
    -
    10401#define RCC_CSR_IWDGRSTF_Pos (29U)
    -
    10402#define RCC_CSR_IWDGRSTF_Msk (0x1UL << RCC_CSR_IWDGRSTF_Pos)
    -
    10403#define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk
    -
    10404#define RCC_CSR_WWDGRSTF_Pos (30U)
    -
    10405#define RCC_CSR_WWDGRSTF_Msk (0x1UL << RCC_CSR_WWDGRSTF_Pos)
    -
    10406#define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk
    -
    10407#define RCC_CSR_LPWRRSTF_Pos (31U)
    -
    10408#define RCC_CSR_LPWRRSTF_Msk (0x1UL << RCC_CSR_LPWRRSTF_Pos)
    -
    10409#define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk
    -
    10410/* Legacy defines */
    -
    10411#define RCC_CSR_PADRSTF RCC_CSR_PINRSTF
    -
    10412#define RCC_CSR_WDGRSTF RCC_CSR_IWDGRSTF
    -
    10413
    -
    10414/******************** Bit definition for RCC_SSCGR register *****************/
    -
    10415#define RCC_SSCGR_MODPER_Pos (0U)
    -
    10416#define RCC_SSCGR_MODPER_Msk (0x1FFFUL << RCC_SSCGR_MODPER_Pos)
    -
    10417#define RCC_SSCGR_MODPER RCC_SSCGR_MODPER_Msk
    -
    10418#define RCC_SSCGR_INCSTEP_Pos (13U)
    -
    10419#define RCC_SSCGR_INCSTEP_Msk (0x7FFFUL << RCC_SSCGR_INCSTEP_Pos)
    -
    10420#define RCC_SSCGR_INCSTEP RCC_SSCGR_INCSTEP_Msk
    -
    10421#define RCC_SSCGR_SPREADSEL_Pos (30U)
    -
    10422#define RCC_SSCGR_SPREADSEL_Msk (0x1UL << RCC_SSCGR_SPREADSEL_Pos)
    -
    10423#define RCC_SSCGR_SPREADSEL RCC_SSCGR_SPREADSEL_Msk
    -
    10424#define RCC_SSCGR_SSCGEN_Pos (31U)
    -
    10425#define RCC_SSCGR_SSCGEN_Msk (0x1UL << RCC_SSCGR_SSCGEN_Pos)
    -
    10426#define RCC_SSCGR_SSCGEN RCC_SSCGR_SSCGEN_Msk
    -
    10427
    -
    10428/******************** Bit definition for RCC_PLLI2SCFGR register ************/
    -
    10429#define RCC_PLLI2SCFGR_PLLI2SN_Pos (6U)
    -
    10430#define RCC_PLLI2SCFGR_PLLI2SN_Msk (0x1FFUL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
    -
    10431#define RCC_PLLI2SCFGR_PLLI2SN RCC_PLLI2SCFGR_PLLI2SN_Msk
    -
    10432#define RCC_PLLI2SCFGR_PLLI2SN_0 (0x001UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
    -
    10433#define RCC_PLLI2SCFGR_PLLI2SN_1 (0x002UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
    -
    10434#define RCC_PLLI2SCFGR_PLLI2SN_2 (0x004UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
    -
    10435#define RCC_PLLI2SCFGR_PLLI2SN_3 (0x008UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
    -
    10436#define RCC_PLLI2SCFGR_PLLI2SN_4 (0x010UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
    -
    10437#define RCC_PLLI2SCFGR_PLLI2SN_5 (0x020UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
    -
    10438#define RCC_PLLI2SCFGR_PLLI2SN_6 (0x040UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
    -
    10439#define RCC_PLLI2SCFGR_PLLI2SN_7 (0x080UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
    -
    10440#define RCC_PLLI2SCFGR_PLLI2SN_8 (0x100UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
    -
    10442#define RCC_PLLI2SCFGR_PLLI2SR_Pos (28U)
    -
    10443#define RCC_PLLI2SCFGR_PLLI2SR_Msk (0x7UL << RCC_PLLI2SCFGR_PLLI2SR_Pos)
    -
    10444#define RCC_PLLI2SCFGR_PLLI2SR RCC_PLLI2SCFGR_PLLI2SR_Msk
    -
    10445#define RCC_PLLI2SCFGR_PLLI2SR_0 (0x1UL << RCC_PLLI2SCFGR_PLLI2SR_Pos)
    -
    10446#define RCC_PLLI2SCFGR_PLLI2SR_1 (0x2UL << RCC_PLLI2SCFGR_PLLI2SR_Pos)
    -
    10447#define RCC_PLLI2SCFGR_PLLI2SR_2 (0x4UL << RCC_PLLI2SCFGR_PLLI2SR_Pos)
    -
    10450/******************************************************************************/
    -
    10451/* */
    -
    10452/* RNG */
    -
    10453/* */
    -
    10454/******************************************************************************/
    -
    10455/******************** Bits definition for RNG_CR register *******************/
    -
    10456#define RNG_CR_RNGEN_Pos (2U)
    -
    10457#define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos)
    -
    10458#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk
    -
    10459#define RNG_CR_IE_Pos (3U)
    -
    10460#define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos)
    -
    10461#define RNG_CR_IE RNG_CR_IE_Msk
    -
    10462
    -
    10463/******************** Bits definition for RNG_SR register *******************/
    -
    10464#define RNG_SR_DRDY_Pos (0U)
    -
    10465#define RNG_SR_DRDY_Msk (0x1UL << RNG_SR_DRDY_Pos)
    -
    10466#define RNG_SR_DRDY RNG_SR_DRDY_Msk
    -
    10467#define RNG_SR_CECS_Pos (1U)
    -
    10468#define RNG_SR_CECS_Msk (0x1UL << RNG_SR_CECS_Pos)
    -
    10469#define RNG_SR_CECS RNG_SR_CECS_Msk
    -
    10470#define RNG_SR_SECS_Pos (2U)
    -
    10471#define RNG_SR_SECS_Msk (0x1UL << RNG_SR_SECS_Pos)
    -
    10472#define RNG_SR_SECS RNG_SR_SECS_Msk
    -
    10473#define RNG_SR_CEIS_Pos (5U)
    -
    10474#define RNG_SR_CEIS_Msk (0x1UL << RNG_SR_CEIS_Pos)
    -
    10475#define RNG_SR_CEIS RNG_SR_CEIS_Msk
    -
    10476#define RNG_SR_SEIS_Pos (6U)
    -
    10477#define RNG_SR_SEIS_Msk (0x1UL << RNG_SR_SEIS_Pos)
    -
    10478#define RNG_SR_SEIS RNG_SR_SEIS_Msk
    -
    10479
    -
    10480/******************************************************************************/
    -
    10481/* */
    -
    10482/* Real-Time Clock (RTC) */
    -
    10483/* */
    -
    10484/******************************************************************************/
    -
    10485/*
    -
    10486 * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
    -
    10487 */
    -
    10488#define RTC_TAMPER2_SUPPORT
    -
    10489#define RTC_AF2_SUPPORT
    -
    10490/******************** Bits definition for RTC_TR register *******************/
    -
    10491#define RTC_TR_PM_Pos (22U)
    -
    10492#define RTC_TR_PM_Msk (0x1UL << RTC_TR_PM_Pos)
    -
    10493#define RTC_TR_PM RTC_TR_PM_Msk
    -
    10494#define RTC_TR_HT_Pos (20U)
    -
    10495#define RTC_TR_HT_Msk (0x3UL << RTC_TR_HT_Pos)
    -
    10496#define RTC_TR_HT RTC_TR_HT_Msk
    -
    10497#define RTC_TR_HT_0 (0x1UL << RTC_TR_HT_Pos)
    -
    10498#define RTC_TR_HT_1 (0x2UL << RTC_TR_HT_Pos)
    -
    10499#define RTC_TR_HU_Pos (16U)
    -
    10500#define RTC_TR_HU_Msk (0xFUL << RTC_TR_HU_Pos)
    -
    10501#define RTC_TR_HU RTC_TR_HU_Msk
    -
    10502#define RTC_TR_HU_0 (0x1UL << RTC_TR_HU_Pos)
    -
    10503#define RTC_TR_HU_1 (0x2UL << RTC_TR_HU_Pos)
    -
    10504#define RTC_TR_HU_2 (0x4UL << RTC_TR_HU_Pos)
    -
    10505#define RTC_TR_HU_3 (0x8UL << RTC_TR_HU_Pos)
    -
    10506#define RTC_TR_MNT_Pos (12U)
    -
    10507#define RTC_TR_MNT_Msk (0x7UL << RTC_TR_MNT_Pos)
    -
    10508#define RTC_TR_MNT RTC_TR_MNT_Msk
    -
    10509#define RTC_TR_MNT_0 (0x1UL << RTC_TR_MNT_Pos)
    -
    10510#define RTC_TR_MNT_1 (0x2UL << RTC_TR_MNT_Pos)
    -
    10511#define RTC_TR_MNT_2 (0x4UL << RTC_TR_MNT_Pos)
    -
    10512#define RTC_TR_MNU_Pos (8U)
    -
    10513#define RTC_TR_MNU_Msk (0xFUL << RTC_TR_MNU_Pos)
    -
    10514#define RTC_TR_MNU RTC_TR_MNU_Msk
    -
    10515#define RTC_TR_MNU_0 (0x1UL << RTC_TR_MNU_Pos)
    -
    10516#define RTC_TR_MNU_1 (0x2UL << RTC_TR_MNU_Pos)
    -
    10517#define RTC_TR_MNU_2 (0x4UL << RTC_TR_MNU_Pos)
    -
    10518#define RTC_TR_MNU_3 (0x8UL << RTC_TR_MNU_Pos)
    -
    10519#define RTC_TR_ST_Pos (4U)
    -
    10520#define RTC_TR_ST_Msk (0x7UL << RTC_TR_ST_Pos)
    -
    10521#define RTC_TR_ST RTC_TR_ST_Msk
    -
    10522#define RTC_TR_ST_0 (0x1UL << RTC_TR_ST_Pos)
    -
    10523#define RTC_TR_ST_1 (0x2UL << RTC_TR_ST_Pos)
    -
    10524#define RTC_TR_ST_2 (0x4UL << RTC_TR_ST_Pos)
    -
    10525#define RTC_TR_SU_Pos (0U)
    -
    10526#define RTC_TR_SU_Msk (0xFUL << RTC_TR_SU_Pos)
    -
    10527#define RTC_TR_SU RTC_TR_SU_Msk
    -
    10528#define RTC_TR_SU_0 (0x1UL << RTC_TR_SU_Pos)
    -
    10529#define RTC_TR_SU_1 (0x2UL << RTC_TR_SU_Pos)
    -
    10530#define RTC_TR_SU_2 (0x4UL << RTC_TR_SU_Pos)
    -
    10531#define RTC_TR_SU_3 (0x8UL << RTC_TR_SU_Pos)
    -
    10533/******************** Bits definition for RTC_DR register *******************/
    -
    10534#define RTC_DR_YT_Pos (20U)
    -
    10535#define RTC_DR_YT_Msk (0xFUL << RTC_DR_YT_Pos)
    -
    10536#define RTC_DR_YT RTC_DR_YT_Msk
    -
    10537#define RTC_DR_YT_0 (0x1UL << RTC_DR_YT_Pos)
    -
    10538#define RTC_DR_YT_1 (0x2UL << RTC_DR_YT_Pos)
    -
    10539#define RTC_DR_YT_2 (0x4UL << RTC_DR_YT_Pos)
    -
    10540#define RTC_DR_YT_3 (0x8UL << RTC_DR_YT_Pos)
    -
    10541#define RTC_DR_YU_Pos (16U)
    -
    10542#define RTC_DR_YU_Msk (0xFUL << RTC_DR_YU_Pos)
    -
    10543#define RTC_DR_YU RTC_DR_YU_Msk
    -
    10544#define RTC_DR_YU_0 (0x1UL << RTC_DR_YU_Pos)
    -
    10545#define RTC_DR_YU_1 (0x2UL << RTC_DR_YU_Pos)
    -
    10546#define RTC_DR_YU_2 (0x4UL << RTC_DR_YU_Pos)
    -
    10547#define RTC_DR_YU_3 (0x8UL << RTC_DR_YU_Pos)
    -
    10548#define RTC_DR_WDU_Pos (13U)
    -
    10549#define RTC_DR_WDU_Msk (0x7UL << RTC_DR_WDU_Pos)
    -
    10550#define RTC_DR_WDU RTC_DR_WDU_Msk
    -
    10551#define RTC_DR_WDU_0 (0x1UL << RTC_DR_WDU_Pos)
    -
    10552#define RTC_DR_WDU_1 (0x2UL << RTC_DR_WDU_Pos)
    -
    10553#define RTC_DR_WDU_2 (0x4UL << RTC_DR_WDU_Pos)
    -
    10554#define RTC_DR_MT_Pos (12U)
    -
    10555#define RTC_DR_MT_Msk (0x1UL << RTC_DR_MT_Pos)
    -
    10556#define RTC_DR_MT RTC_DR_MT_Msk
    -
    10557#define RTC_DR_MU_Pos (8U)
    -
    10558#define RTC_DR_MU_Msk (0xFUL << RTC_DR_MU_Pos)
    -
    10559#define RTC_DR_MU RTC_DR_MU_Msk
    -
    10560#define RTC_DR_MU_0 (0x1UL << RTC_DR_MU_Pos)
    -
    10561#define RTC_DR_MU_1 (0x2UL << RTC_DR_MU_Pos)
    -
    10562#define RTC_DR_MU_2 (0x4UL << RTC_DR_MU_Pos)
    -
    10563#define RTC_DR_MU_3 (0x8UL << RTC_DR_MU_Pos)
    -
    10564#define RTC_DR_DT_Pos (4U)
    -
    10565#define RTC_DR_DT_Msk (0x3UL << RTC_DR_DT_Pos)
    -
    10566#define RTC_DR_DT RTC_DR_DT_Msk
    -
    10567#define RTC_DR_DT_0 (0x1UL << RTC_DR_DT_Pos)
    -
    10568#define RTC_DR_DT_1 (0x2UL << RTC_DR_DT_Pos)
    -
    10569#define RTC_DR_DU_Pos (0U)
    -
    10570#define RTC_DR_DU_Msk (0xFUL << RTC_DR_DU_Pos)
    -
    10571#define RTC_DR_DU RTC_DR_DU_Msk
    -
    10572#define RTC_DR_DU_0 (0x1UL << RTC_DR_DU_Pos)
    -
    10573#define RTC_DR_DU_1 (0x2UL << RTC_DR_DU_Pos)
    -
    10574#define RTC_DR_DU_2 (0x4UL << RTC_DR_DU_Pos)
    -
    10575#define RTC_DR_DU_3 (0x8UL << RTC_DR_DU_Pos)
    -
    10577/******************** Bits definition for RTC_CR register *******************/
    -
    10578#define RTC_CR_COE_Pos (23U)
    -
    10579#define RTC_CR_COE_Msk (0x1UL << RTC_CR_COE_Pos)
    -
    10580#define RTC_CR_COE RTC_CR_COE_Msk
    -
    10581#define RTC_CR_OSEL_Pos (21U)
    -
    10582#define RTC_CR_OSEL_Msk (0x3UL << RTC_CR_OSEL_Pos)
    -
    10583#define RTC_CR_OSEL RTC_CR_OSEL_Msk
    -
    10584#define RTC_CR_OSEL_0 (0x1UL << RTC_CR_OSEL_Pos)
    -
    10585#define RTC_CR_OSEL_1 (0x2UL << RTC_CR_OSEL_Pos)
    -
    10586#define RTC_CR_POL_Pos (20U)
    -
    10587#define RTC_CR_POL_Msk (0x1UL << RTC_CR_POL_Pos)
    -
    10588#define RTC_CR_POL RTC_CR_POL_Msk
    -
    10589#define RTC_CR_COSEL_Pos (19U)
    -
    10590#define RTC_CR_COSEL_Msk (0x1UL << RTC_CR_COSEL_Pos)
    -
    10591#define RTC_CR_COSEL RTC_CR_COSEL_Msk
    -
    10592#define RTC_CR_BKP_Pos (18U)
    -
    10593#define RTC_CR_BKP_Msk (0x1UL << RTC_CR_BKP_Pos)
    -
    10594#define RTC_CR_BKP RTC_CR_BKP_Msk
    -
    10595#define RTC_CR_SUB1H_Pos (17U)
    -
    10596#define RTC_CR_SUB1H_Msk (0x1UL << RTC_CR_SUB1H_Pos)
    -
    10597#define RTC_CR_SUB1H RTC_CR_SUB1H_Msk
    -
    10598#define RTC_CR_ADD1H_Pos (16U)
    -
    10599#define RTC_CR_ADD1H_Msk (0x1UL << RTC_CR_ADD1H_Pos)
    -
    10600#define RTC_CR_ADD1H RTC_CR_ADD1H_Msk
    -
    10601#define RTC_CR_TSIE_Pos (15U)
    -
    10602#define RTC_CR_TSIE_Msk (0x1UL << RTC_CR_TSIE_Pos)
    -
    10603#define RTC_CR_TSIE RTC_CR_TSIE_Msk
    -
    10604#define RTC_CR_WUTIE_Pos (14U)
    -
    10605#define RTC_CR_WUTIE_Msk (0x1UL << RTC_CR_WUTIE_Pos)
    -
    10606#define RTC_CR_WUTIE RTC_CR_WUTIE_Msk
    -
    10607#define RTC_CR_ALRBIE_Pos (13U)
    -
    10608#define RTC_CR_ALRBIE_Msk (0x1UL << RTC_CR_ALRBIE_Pos)
    -
    10609#define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk
    -
    10610#define RTC_CR_ALRAIE_Pos (12U)
    -
    10611#define RTC_CR_ALRAIE_Msk (0x1UL << RTC_CR_ALRAIE_Pos)
    -
    10612#define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk
    -
    10613#define RTC_CR_TSE_Pos (11U)
    -
    10614#define RTC_CR_TSE_Msk (0x1UL << RTC_CR_TSE_Pos)
    -
    10615#define RTC_CR_TSE RTC_CR_TSE_Msk
    -
    10616#define RTC_CR_WUTE_Pos (10U)
    -
    10617#define RTC_CR_WUTE_Msk (0x1UL << RTC_CR_WUTE_Pos)
    -
    10618#define RTC_CR_WUTE RTC_CR_WUTE_Msk
    -
    10619#define RTC_CR_ALRBE_Pos (9U)
    -
    10620#define RTC_CR_ALRBE_Msk (0x1UL << RTC_CR_ALRBE_Pos)
    -
    10621#define RTC_CR_ALRBE RTC_CR_ALRBE_Msk
    -
    10622#define RTC_CR_ALRAE_Pos (8U)
    -
    10623#define RTC_CR_ALRAE_Msk (0x1UL << RTC_CR_ALRAE_Pos)
    -
    10624#define RTC_CR_ALRAE RTC_CR_ALRAE_Msk
    -
    10625#define RTC_CR_DCE_Pos (7U)
    -
    10626#define RTC_CR_DCE_Msk (0x1UL << RTC_CR_DCE_Pos)
    -
    10627#define RTC_CR_DCE RTC_CR_DCE_Msk
    -
    10628#define RTC_CR_FMT_Pos (6U)
    -
    10629#define RTC_CR_FMT_Msk (0x1UL << RTC_CR_FMT_Pos)
    -
    10630#define RTC_CR_FMT RTC_CR_FMT_Msk
    -
    10631#define RTC_CR_BYPSHAD_Pos (5U)
    -
    10632#define RTC_CR_BYPSHAD_Msk (0x1UL << RTC_CR_BYPSHAD_Pos)
    -
    10633#define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk
    -
    10634#define RTC_CR_REFCKON_Pos (4U)
    -
    10635#define RTC_CR_REFCKON_Msk (0x1UL << RTC_CR_REFCKON_Pos)
    -
    10636#define RTC_CR_REFCKON RTC_CR_REFCKON_Msk
    -
    10637#define RTC_CR_TSEDGE_Pos (3U)
    -
    10638#define RTC_CR_TSEDGE_Msk (0x1UL << RTC_CR_TSEDGE_Pos)
    -
    10639#define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk
    -
    10640#define RTC_CR_WUCKSEL_Pos (0U)
    -
    10641#define RTC_CR_WUCKSEL_Msk (0x7UL << RTC_CR_WUCKSEL_Pos)
    -
    10642#define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk
    -
    10643#define RTC_CR_WUCKSEL_0 (0x1UL << RTC_CR_WUCKSEL_Pos)
    -
    10644#define RTC_CR_WUCKSEL_1 (0x2UL << RTC_CR_WUCKSEL_Pos)
    -
    10645#define RTC_CR_WUCKSEL_2 (0x4UL << RTC_CR_WUCKSEL_Pos)
    -
    10647/* Legacy defines */
    -
    10648#define RTC_CR_BCK RTC_CR_BKP
    -
    10649
    -
    10650/******************** Bits definition for RTC_ISR register ******************/
    -
    10651#define RTC_ISR_RECALPF_Pos (16U)
    -
    10652#define RTC_ISR_RECALPF_Msk (0x1UL << RTC_ISR_RECALPF_Pos)
    -
    10653#define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk
    -
    10654#define RTC_ISR_TAMP1F_Pos (13U)
    -
    10655#define RTC_ISR_TAMP1F_Msk (0x1UL << RTC_ISR_TAMP1F_Pos)
    -
    10656#define RTC_ISR_TAMP1F RTC_ISR_TAMP1F_Msk
    -
    10657#define RTC_ISR_TAMP2F_Pos (14U)
    -
    10658#define RTC_ISR_TAMP2F_Msk (0x1UL << RTC_ISR_TAMP2F_Pos)
    -
    10659#define RTC_ISR_TAMP2F RTC_ISR_TAMP2F_Msk
    -
    10660#define RTC_ISR_TSOVF_Pos (12U)
    -
    10661#define RTC_ISR_TSOVF_Msk (0x1UL << RTC_ISR_TSOVF_Pos)
    -
    10662#define RTC_ISR_TSOVF RTC_ISR_TSOVF_Msk
    -
    10663#define RTC_ISR_TSF_Pos (11U)
    -
    10664#define RTC_ISR_TSF_Msk (0x1UL << RTC_ISR_TSF_Pos)
    -
    10665#define RTC_ISR_TSF RTC_ISR_TSF_Msk
    -
    10666#define RTC_ISR_WUTF_Pos (10U)
    -
    10667#define RTC_ISR_WUTF_Msk (0x1UL << RTC_ISR_WUTF_Pos)
    -
    10668#define RTC_ISR_WUTF RTC_ISR_WUTF_Msk
    -
    10669#define RTC_ISR_ALRBF_Pos (9U)
    -
    10670#define RTC_ISR_ALRBF_Msk (0x1UL << RTC_ISR_ALRBF_Pos)
    -
    10671#define RTC_ISR_ALRBF RTC_ISR_ALRBF_Msk
    -
    10672#define RTC_ISR_ALRAF_Pos (8U)
    -
    10673#define RTC_ISR_ALRAF_Msk (0x1UL << RTC_ISR_ALRAF_Pos)
    -
    10674#define RTC_ISR_ALRAF RTC_ISR_ALRAF_Msk
    -
    10675#define RTC_ISR_INIT_Pos (7U)
    -
    10676#define RTC_ISR_INIT_Msk (0x1UL << RTC_ISR_INIT_Pos)
    -
    10677#define RTC_ISR_INIT RTC_ISR_INIT_Msk
    -
    10678#define RTC_ISR_INITF_Pos (6U)
    -
    10679#define RTC_ISR_INITF_Msk (0x1UL << RTC_ISR_INITF_Pos)
    -
    10680#define RTC_ISR_INITF RTC_ISR_INITF_Msk
    -
    10681#define RTC_ISR_RSF_Pos (5U)
    -
    10682#define RTC_ISR_RSF_Msk (0x1UL << RTC_ISR_RSF_Pos)
    -
    10683#define RTC_ISR_RSF RTC_ISR_RSF_Msk
    -
    10684#define RTC_ISR_INITS_Pos (4U)
    -
    10685#define RTC_ISR_INITS_Msk (0x1UL << RTC_ISR_INITS_Pos)
    -
    10686#define RTC_ISR_INITS RTC_ISR_INITS_Msk
    -
    10687#define RTC_ISR_SHPF_Pos (3U)
    -
    10688#define RTC_ISR_SHPF_Msk (0x1UL << RTC_ISR_SHPF_Pos)
    -
    10689#define RTC_ISR_SHPF RTC_ISR_SHPF_Msk
    -
    10690#define RTC_ISR_WUTWF_Pos (2U)
    -
    10691#define RTC_ISR_WUTWF_Msk (0x1UL << RTC_ISR_WUTWF_Pos)
    -
    10692#define RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk
    -
    10693#define RTC_ISR_ALRBWF_Pos (1U)
    -
    10694#define RTC_ISR_ALRBWF_Msk (0x1UL << RTC_ISR_ALRBWF_Pos)
    -
    10695#define RTC_ISR_ALRBWF RTC_ISR_ALRBWF_Msk
    -
    10696#define RTC_ISR_ALRAWF_Pos (0U)
    -
    10697#define RTC_ISR_ALRAWF_Msk (0x1UL << RTC_ISR_ALRAWF_Pos)
    -
    10698#define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk
    -
    10699
    -
    10700/******************** Bits definition for RTC_PRER register *****************/
    -
    10701#define RTC_PRER_PREDIV_A_Pos (16U)
    -
    10702#define RTC_PRER_PREDIV_A_Msk (0x7FUL << RTC_PRER_PREDIV_A_Pos)
    -
    10703#define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk
    -
    10704#define RTC_PRER_PREDIV_S_Pos (0U)
    -
    10705#define RTC_PRER_PREDIV_S_Msk (0x7FFFUL << RTC_PRER_PREDIV_S_Pos)
    -
    10706#define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk
    -
    10707
    -
    10708/******************** Bits definition for RTC_WUTR register *****************/
    -
    10709#define RTC_WUTR_WUT_Pos (0U)
    -
    10710#define RTC_WUTR_WUT_Msk (0xFFFFUL << RTC_WUTR_WUT_Pos)
    -
    10711#define RTC_WUTR_WUT RTC_WUTR_WUT_Msk
    -
    10712
    -
    10713/******************** Bits definition for RTC_CALIBR register ***************/
    -
    10714#define RTC_CALIBR_DCS_Pos (7U)
    -
    10715#define RTC_CALIBR_DCS_Msk (0x1UL << RTC_CALIBR_DCS_Pos)
    -
    10716#define RTC_CALIBR_DCS RTC_CALIBR_DCS_Msk
    -
    10717#define RTC_CALIBR_DC_Pos (0U)
    -
    10718#define RTC_CALIBR_DC_Msk (0x1FUL << RTC_CALIBR_DC_Pos)
    -
    10719#define RTC_CALIBR_DC RTC_CALIBR_DC_Msk
    -
    10720
    -
    10721/******************** Bits definition for RTC_ALRMAR register ***************/
    -
    10722#define RTC_ALRMAR_MSK4_Pos (31U)
    -
    10723#define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos)
    -
    10724#define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk
    -
    10725#define RTC_ALRMAR_WDSEL_Pos (30U)
    -
    10726#define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos)
    -
    10727#define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk
    -
    10728#define RTC_ALRMAR_DT_Pos (28U)
    -
    10729#define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos)
    -
    10730#define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk
    -
    10731#define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos)
    -
    10732#define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos)
    -
    10733#define RTC_ALRMAR_DU_Pos (24U)
    -
    10734#define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos)
    -
    10735#define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk
    -
    10736#define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos)
    -
    10737#define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos)
    -
    10738#define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos)
    -
    10739#define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos)
    -
    10740#define RTC_ALRMAR_MSK3_Pos (23U)
    -
    10741#define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos)
    -
    10742#define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk
    -
    10743#define RTC_ALRMAR_PM_Pos (22U)
    -
    10744#define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos)
    -
    10745#define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk
    -
    10746#define RTC_ALRMAR_HT_Pos (20U)
    -
    10747#define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos)
    -
    10748#define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk
    -
    10749#define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos)
    -
    10750#define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos)
    -
    10751#define RTC_ALRMAR_HU_Pos (16U)
    -
    10752#define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos)
    -
    10753#define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk
    -
    10754#define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos)
    -
    10755#define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos)
    -
    10756#define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos)
    -
    10757#define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos)
    -
    10758#define RTC_ALRMAR_MSK2_Pos (15U)
    -
    10759#define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos)
    -
    10760#define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk
    -
    10761#define RTC_ALRMAR_MNT_Pos (12U)
    -
    10762#define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos)
    -
    10763#define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk
    -
    10764#define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos)
    -
    10765#define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos)
    -
    10766#define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos)
    -
    10767#define RTC_ALRMAR_MNU_Pos (8U)
    -
    10768#define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos)
    -
    10769#define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk
    -
    10770#define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos)
    -
    10771#define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos)
    -
    10772#define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos)
    -
    10773#define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos)
    -
    10774#define RTC_ALRMAR_MSK1_Pos (7U)
    -
    10775#define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos)
    -
    10776#define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk
    -
    10777#define RTC_ALRMAR_ST_Pos (4U)
    -
    10778#define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos)
    -
    10779#define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk
    -
    10780#define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos)
    -
    10781#define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos)
    -
    10782#define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos)
    -
    10783#define RTC_ALRMAR_SU_Pos (0U)
    -
    10784#define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos)
    -
    10785#define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk
    -
    10786#define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos)
    -
    10787#define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos)
    -
    10788#define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos)
    -
    10789#define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos)
    -
    10791/******************** Bits definition for RTC_ALRMBR register ***************/
    -
    10792#define RTC_ALRMBR_MSK4_Pos (31U)
    -
    10793#define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos)
    -
    10794#define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk
    -
    10795#define RTC_ALRMBR_WDSEL_Pos (30U)
    -
    10796#define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos)
    -
    10797#define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk
    -
    10798#define RTC_ALRMBR_DT_Pos (28U)
    -
    10799#define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos)
    -
    10800#define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk
    -
    10801#define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos)
    -
    10802#define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos)
    -
    10803#define RTC_ALRMBR_DU_Pos (24U)
    -
    10804#define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos)
    -
    10805#define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk
    -
    10806#define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos)
    -
    10807#define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos)
    -
    10808#define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos)
    -
    10809#define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos)
    -
    10810#define RTC_ALRMBR_MSK3_Pos (23U)
    -
    10811#define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos)
    -
    10812#define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk
    -
    10813#define RTC_ALRMBR_PM_Pos (22U)
    -
    10814#define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos)
    -
    10815#define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk
    -
    10816#define RTC_ALRMBR_HT_Pos (20U)
    -
    10817#define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos)
    -
    10818#define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk
    -
    10819#define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos)
    -
    10820#define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos)
    -
    10821#define RTC_ALRMBR_HU_Pos (16U)
    -
    10822#define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos)
    -
    10823#define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk
    -
    10824#define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos)
    -
    10825#define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos)
    -
    10826#define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos)
    -
    10827#define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos)
    -
    10828#define RTC_ALRMBR_MSK2_Pos (15U)
    -
    10829#define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos)
    -
    10830#define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk
    -
    10831#define RTC_ALRMBR_MNT_Pos (12U)
    -
    10832#define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos)
    -
    10833#define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk
    -
    10834#define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos)
    -
    10835#define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos)
    -
    10836#define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos)
    -
    10837#define RTC_ALRMBR_MNU_Pos (8U)
    -
    10838#define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos)
    -
    10839#define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk
    -
    10840#define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos)
    -
    10841#define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos)
    -
    10842#define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos)
    -
    10843#define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos)
    -
    10844#define RTC_ALRMBR_MSK1_Pos (7U)
    -
    10845#define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos)
    -
    10846#define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk
    -
    10847#define RTC_ALRMBR_ST_Pos (4U)
    -
    10848#define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos)
    -
    10849#define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk
    -
    10850#define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos)
    -
    10851#define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos)
    -
    10852#define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos)
    -
    10853#define RTC_ALRMBR_SU_Pos (0U)
    -
    10854#define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos)
    -
    10855#define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk
    -
    10856#define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos)
    -
    10857#define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos)
    -
    10858#define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos)
    -
    10859#define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos)
    -
    10861/******************** Bits definition for RTC_WPR register ******************/
    -
    10862#define RTC_WPR_KEY_Pos (0U)
    -
    10863#define RTC_WPR_KEY_Msk (0xFFUL << RTC_WPR_KEY_Pos)
    -
    10864#define RTC_WPR_KEY RTC_WPR_KEY_Msk
    -
    10865
    -
    10866/******************** Bits definition for RTC_SSR register ******************/
    -
    10867#define RTC_SSR_SS_Pos (0U)
    -
    10868#define RTC_SSR_SS_Msk (0xFFFFUL << RTC_SSR_SS_Pos)
    -
    10869#define RTC_SSR_SS RTC_SSR_SS_Msk
    -
    10870
    -
    10871/******************** Bits definition for RTC_SHIFTR register ***************/
    -
    10872#define RTC_SHIFTR_SUBFS_Pos (0U)
    -
    10873#define RTC_SHIFTR_SUBFS_Msk (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos)
    -
    10874#define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk
    -
    10875#define RTC_SHIFTR_ADD1S_Pos (31U)
    -
    10876#define RTC_SHIFTR_ADD1S_Msk (0x1UL << RTC_SHIFTR_ADD1S_Pos)
    -
    10877#define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk
    -
    10878
    -
    10879/******************** Bits definition for RTC_TSTR register *****************/
    -
    10880#define RTC_TSTR_PM_Pos (22U)
    -
    10881#define RTC_TSTR_PM_Msk (0x1UL << RTC_TSTR_PM_Pos)
    -
    10882#define RTC_TSTR_PM RTC_TSTR_PM_Msk
    -
    10883#define RTC_TSTR_HT_Pos (20U)
    -
    10884#define RTC_TSTR_HT_Msk (0x3UL << RTC_TSTR_HT_Pos)
    -
    10885#define RTC_TSTR_HT RTC_TSTR_HT_Msk
    -
    10886#define RTC_TSTR_HT_0 (0x1UL << RTC_TSTR_HT_Pos)
    -
    10887#define RTC_TSTR_HT_1 (0x2UL << RTC_TSTR_HT_Pos)
    -
    10888#define RTC_TSTR_HU_Pos (16U)
    -
    10889#define RTC_TSTR_HU_Msk (0xFUL << RTC_TSTR_HU_Pos)
    -
    10890#define RTC_TSTR_HU RTC_TSTR_HU_Msk
    -
    10891#define RTC_TSTR_HU_0 (0x1UL << RTC_TSTR_HU_Pos)
    -
    10892#define RTC_TSTR_HU_1 (0x2UL << RTC_TSTR_HU_Pos)
    -
    10893#define RTC_TSTR_HU_2 (0x4UL << RTC_TSTR_HU_Pos)
    -
    10894#define RTC_TSTR_HU_3 (0x8UL << RTC_TSTR_HU_Pos)
    -
    10895#define RTC_TSTR_MNT_Pos (12U)
    -
    10896#define RTC_TSTR_MNT_Msk (0x7UL << RTC_TSTR_MNT_Pos)
    -
    10897#define RTC_TSTR_MNT RTC_TSTR_MNT_Msk
    -
    10898#define RTC_TSTR_MNT_0 (0x1UL << RTC_TSTR_MNT_Pos)
    -
    10899#define RTC_TSTR_MNT_1 (0x2UL << RTC_TSTR_MNT_Pos)
    -
    10900#define RTC_TSTR_MNT_2 (0x4UL << RTC_TSTR_MNT_Pos)
    -
    10901#define RTC_TSTR_MNU_Pos (8U)
    -
    10902#define RTC_TSTR_MNU_Msk (0xFUL << RTC_TSTR_MNU_Pos)
    -
    10903#define RTC_TSTR_MNU RTC_TSTR_MNU_Msk
    -
    10904#define RTC_TSTR_MNU_0 (0x1UL << RTC_TSTR_MNU_Pos)
    -
    10905#define RTC_TSTR_MNU_1 (0x2UL << RTC_TSTR_MNU_Pos)
    -
    10906#define RTC_TSTR_MNU_2 (0x4UL << RTC_TSTR_MNU_Pos)
    -
    10907#define RTC_TSTR_MNU_3 (0x8UL << RTC_TSTR_MNU_Pos)
    -
    10908#define RTC_TSTR_ST_Pos (4U)
    -
    10909#define RTC_TSTR_ST_Msk (0x7UL << RTC_TSTR_ST_Pos)
    -
    10910#define RTC_TSTR_ST RTC_TSTR_ST_Msk
    -
    10911#define RTC_TSTR_ST_0 (0x1UL << RTC_TSTR_ST_Pos)
    -
    10912#define RTC_TSTR_ST_1 (0x2UL << RTC_TSTR_ST_Pos)
    -
    10913#define RTC_TSTR_ST_2 (0x4UL << RTC_TSTR_ST_Pos)
    -
    10914#define RTC_TSTR_SU_Pos (0U)
    -
    10915#define RTC_TSTR_SU_Msk (0xFUL << RTC_TSTR_SU_Pos)
    -
    10916#define RTC_TSTR_SU RTC_TSTR_SU_Msk
    -
    10917#define RTC_TSTR_SU_0 (0x1UL << RTC_TSTR_SU_Pos)
    -
    10918#define RTC_TSTR_SU_1 (0x2UL << RTC_TSTR_SU_Pos)
    -
    10919#define RTC_TSTR_SU_2 (0x4UL << RTC_TSTR_SU_Pos)
    -
    10920#define RTC_TSTR_SU_3 (0x8UL << RTC_TSTR_SU_Pos)
    -
    10922/******************** Bits definition for RTC_TSDR register *****************/
    -
    10923#define RTC_TSDR_WDU_Pos (13U)
    -
    10924#define RTC_TSDR_WDU_Msk (0x7UL << RTC_TSDR_WDU_Pos)
    -
    10925#define RTC_TSDR_WDU RTC_TSDR_WDU_Msk
    -
    10926#define RTC_TSDR_WDU_0 (0x1UL << RTC_TSDR_WDU_Pos)
    -
    10927#define RTC_TSDR_WDU_1 (0x2UL << RTC_TSDR_WDU_Pos)
    -
    10928#define RTC_TSDR_WDU_2 (0x4UL << RTC_TSDR_WDU_Pos)
    -
    10929#define RTC_TSDR_MT_Pos (12U)
    -
    10930#define RTC_TSDR_MT_Msk (0x1UL << RTC_TSDR_MT_Pos)
    -
    10931#define RTC_TSDR_MT RTC_TSDR_MT_Msk
    -
    10932#define RTC_TSDR_MU_Pos (8U)
    -
    10933#define RTC_TSDR_MU_Msk (0xFUL << RTC_TSDR_MU_Pos)
    -
    10934#define RTC_TSDR_MU RTC_TSDR_MU_Msk
    -
    10935#define RTC_TSDR_MU_0 (0x1UL << RTC_TSDR_MU_Pos)
    -
    10936#define RTC_TSDR_MU_1 (0x2UL << RTC_TSDR_MU_Pos)
    -
    10937#define RTC_TSDR_MU_2 (0x4UL << RTC_TSDR_MU_Pos)
    -
    10938#define RTC_TSDR_MU_3 (0x8UL << RTC_TSDR_MU_Pos)
    -
    10939#define RTC_TSDR_DT_Pos (4U)
    -
    10940#define RTC_TSDR_DT_Msk (0x3UL << RTC_TSDR_DT_Pos)
    -
    10941#define RTC_TSDR_DT RTC_TSDR_DT_Msk
    -
    10942#define RTC_TSDR_DT_0 (0x1UL << RTC_TSDR_DT_Pos)
    -
    10943#define RTC_TSDR_DT_1 (0x2UL << RTC_TSDR_DT_Pos)
    -
    10944#define RTC_TSDR_DU_Pos (0U)
    -
    10945#define RTC_TSDR_DU_Msk (0xFUL << RTC_TSDR_DU_Pos)
    -
    10946#define RTC_TSDR_DU RTC_TSDR_DU_Msk
    -
    10947#define RTC_TSDR_DU_0 (0x1UL << RTC_TSDR_DU_Pos)
    -
    10948#define RTC_TSDR_DU_1 (0x2UL << RTC_TSDR_DU_Pos)
    -
    10949#define RTC_TSDR_DU_2 (0x4UL << RTC_TSDR_DU_Pos)
    -
    10950#define RTC_TSDR_DU_3 (0x8UL << RTC_TSDR_DU_Pos)
    -
    10952/******************** Bits definition for RTC_TSSSR register ****************/
    -
    10953#define RTC_TSSSR_SS_Pos (0U)
    -
    10954#define RTC_TSSSR_SS_Msk (0xFFFFUL << RTC_TSSSR_SS_Pos)
    -
    10955#define RTC_TSSSR_SS RTC_TSSSR_SS_Msk
    -
    10956
    -
    10957/******************** Bits definition for RTC_CAL register *****************/
    -
    10958#define RTC_CALR_CALP_Pos (15U)
    -
    10959#define RTC_CALR_CALP_Msk (0x1UL << RTC_CALR_CALP_Pos)
    -
    10960#define RTC_CALR_CALP RTC_CALR_CALP_Msk
    -
    10961#define RTC_CALR_CALW8_Pos (14U)
    -
    10962#define RTC_CALR_CALW8_Msk (0x1UL << RTC_CALR_CALW8_Pos)
    -
    10963#define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk
    -
    10964#define RTC_CALR_CALW16_Pos (13U)
    -
    10965#define RTC_CALR_CALW16_Msk (0x1UL << RTC_CALR_CALW16_Pos)
    -
    10966#define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk
    -
    10967#define RTC_CALR_CALM_Pos (0U)
    -
    10968#define RTC_CALR_CALM_Msk (0x1FFUL << RTC_CALR_CALM_Pos)
    -
    10969#define RTC_CALR_CALM RTC_CALR_CALM_Msk
    -
    10970#define RTC_CALR_CALM_0 (0x001UL << RTC_CALR_CALM_Pos)
    -
    10971#define RTC_CALR_CALM_1 (0x002UL << RTC_CALR_CALM_Pos)
    -
    10972#define RTC_CALR_CALM_2 (0x004UL << RTC_CALR_CALM_Pos)
    -
    10973#define RTC_CALR_CALM_3 (0x008UL << RTC_CALR_CALM_Pos)
    -
    10974#define RTC_CALR_CALM_4 (0x010UL << RTC_CALR_CALM_Pos)
    -
    10975#define RTC_CALR_CALM_5 (0x020UL << RTC_CALR_CALM_Pos)
    -
    10976#define RTC_CALR_CALM_6 (0x040UL << RTC_CALR_CALM_Pos)
    -
    10977#define RTC_CALR_CALM_7 (0x080UL << RTC_CALR_CALM_Pos)
    -
    10978#define RTC_CALR_CALM_8 (0x100UL << RTC_CALR_CALM_Pos)
    -
    10980/******************** Bits definition for RTC_TAFCR register ****************/
    -
    10981#define RTC_TAFCR_ALARMOUTTYPE_Pos (18U)
    -
    10982#define RTC_TAFCR_ALARMOUTTYPE_Msk (0x1UL << RTC_TAFCR_ALARMOUTTYPE_Pos)
    -
    10983#define RTC_TAFCR_ALARMOUTTYPE RTC_TAFCR_ALARMOUTTYPE_Msk
    -
    10984#define RTC_TAFCR_TSINSEL_Pos (17U)
    -
    10985#define RTC_TAFCR_TSINSEL_Msk (0x1UL << RTC_TAFCR_TSINSEL_Pos)
    -
    10986#define RTC_TAFCR_TSINSEL RTC_TAFCR_TSINSEL_Msk
    -
    10987#define RTC_TAFCR_TAMP1INSEL_Pos (16U)
    -
    10988#define RTC_TAFCR_TAMP1INSEL_Msk (0x1UL << RTC_TAFCR_TAMP1INSEL_Pos)
    -
    10989#define RTC_TAFCR_TAMP1INSEL RTC_TAFCR_TAMP1INSEL_Msk
    -
    10990#define RTC_TAFCR_TAMPPUDIS_Pos (15U)
    -
    10991#define RTC_TAFCR_TAMPPUDIS_Msk (0x1UL << RTC_TAFCR_TAMPPUDIS_Pos)
    -
    10992#define RTC_TAFCR_TAMPPUDIS RTC_TAFCR_TAMPPUDIS_Msk
    -
    10993#define RTC_TAFCR_TAMPPRCH_Pos (13U)
    -
    10994#define RTC_TAFCR_TAMPPRCH_Msk (0x3UL << RTC_TAFCR_TAMPPRCH_Pos)
    -
    10995#define RTC_TAFCR_TAMPPRCH RTC_TAFCR_TAMPPRCH_Msk
    -
    10996#define RTC_TAFCR_TAMPPRCH_0 (0x1UL << RTC_TAFCR_TAMPPRCH_Pos)
    -
    10997#define RTC_TAFCR_TAMPPRCH_1 (0x2UL << RTC_TAFCR_TAMPPRCH_Pos)
    -
    10998#define RTC_TAFCR_TAMPFLT_Pos (11U)
    -
    10999#define RTC_TAFCR_TAMPFLT_Msk (0x3UL << RTC_TAFCR_TAMPFLT_Pos)
    -
    11000#define RTC_TAFCR_TAMPFLT RTC_TAFCR_TAMPFLT_Msk
    -
    11001#define RTC_TAFCR_TAMPFLT_0 (0x1UL << RTC_TAFCR_TAMPFLT_Pos)
    -
    11002#define RTC_TAFCR_TAMPFLT_1 (0x2UL << RTC_TAFCR_TAMPFLT_Pos)
    -
    11003#define RTC_TAFCR_TAMPFREQ_Pos (8U)
    -
    11004#define RTC_TAFCR_TAMPFREQ_Msk (0x7UL << RTC_TAFCR_TAMPFREQ_Pos)
    -
    11005#define RTC_TAFCR_TAMPFREQ RTC_TAFCR_TAMPFREQ_Msk
    -
    11006#define RTC_TAFCR_TAMPFREQ_0 (0x1UL << RTC_TAFCR_TAMPFREQ_Pos)
    -
    11007#define RTC_TAFCR_TAMPFREQ_1 (0x2UL << RTC_TAFCR_TAMPFREQ_Pos)
    -
    11008#define RTC_TAFCR_TAMPFREQ_2 (0x4UL << RTC_TAFCR_TAMPFREQ_Pos)
    -
    11009#define RTC_TAFCR_TAMPTS_Pos (7U)
    -
    11010#define RTC_TAFCR_TAMPTS_Msk (0x1UL << RTC_TAFCR_TAMPTS_Pos)
    -
    11011#define RTC_TAFCR_TAMPTS RTC_TAFCR_TAMPTS_Msk
    -
    11012#define RTC_TAFCR_TAMP2TRG_Pos (4U)
    -
    11013#define RTC_TAFCR_TAMP2TRG_Msk (0x1UL << RTC_TAFCR_TAMP2TRG_Pos)
    -
    11014#define RTC_TAFCR_TAMP2TRG RTC_TAFCR_TAMP2TRG_Msk
    -
    11015#define RTC_TAFCR_TAMP2E_Pos (3U)
    -
    11016#define RTC_TAFCR_TAMP2E_Msk (0x1UL << RTC_TAFCR_TAMP2E_Pos)
    -
    11017#define RTC_TAFCR_TAMP2E RTC_TAFCR_TAMP2E_Msk
    -
    11018#define RTC_TAFCR_TAMPIE_Pos (2U)
    -
    11019#define RTC_TAFCR_TAMPIE_Msk (0x1UL << RTC_TAFCR_TAMPIE_Pos)
    -
    11020#define RTC_TAFCR_TAMPIE RTC_TAFCR_TAMPIE_Msk
    -
    11021#define RTC_TAFCR_TAMP1TRG_Pos (1U)
    -
    11022#define RTC_TAFCR_TAMP1TRG_Msk (0x1UL << RTC_TAFCR_TAMP1TRG_Pos)
    -
    11023#define RTC_TAFCR_TAMP1TRG RTC_TAFCR_TAMP1TRG_Msk
    -
    11024#define RTC_TAFCR_TAMP1E_Pos (0U)
    -
    11025#define RTC_TAFCR_TAMP1E_Msk (0x1UL << RTC_TAFCR_TAMP1E_Pos)
    -
    11026#define RTC_TAFCR_TAMP1E RTC_TAFCR_TAMP1E_Msk
    -
    11027
    -
    11028/* Legacy defines */
    -
    11029#define RTC_TAFCR_TAMPINSEL RTC_TAFCR_TAMP1INSEL
    -
    11030
    -
    11031/******************** Bits definition for RTC_ALRMASSR register *************/
    -
    11032#define RTC_ALRMASSR_MASKSS_Pos (24U)
    -
    11033#define RTC_ALRMASSR_MASKSS_Msk (0xFUL << RTC_ALRMASSR_MASKSS_Pos)
    -
    11034#define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk
    -
    11035#define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos)
    -
    11036#define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos)
    -
    11037#define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos)
    -
    11038#define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos)
    -
    11039#define RTC_ALRMASSR_SS_Pos (0U)
    -
    11040#define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos)
    -
    11041#define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk
    -
    11042
    -
    11043/******************** Bits definition for RTC_ALRMBSSR register *************/
    -
    11044#define RTC_ALRMBSSR_MASKSS_Pos (24U)
    -
    11045#define RTC_ALRMBSSR_MASKSS_Msk (0xFUL << RTC_ALRMBSSR_MASKSS_Pos)
    -
    11046#define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk
    -
    11047#define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos)
    -
    11048#define RTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos)
    -
    11049#define RTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos)
    -
    11050#define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos)
    -
    11051#define RTC_ALRMBSSR_SS_Pos (0U)
    -
    11052#define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos)
    -
    11053#define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk
    -
    11054
    -
    11055/******************** Bits definition for RTC_BKP0R register ****************/
    -
    11056#define RTC_BKP0R_Pos (0U)
    -
    11057#define RTC_BKP0R_Msk (0xFFFFFFFFUL << RTC_BKP0R_Pos)
    -
    11058#define RTC_BKP0R RTC_BKP0R_Msk
    -
    11059
    -
    11060/******************** Bits definition for RTC_BKP1R register ****************/
    -
    11061#define RTC_BKP1R_Pos (0U)
    -
    11062#define RTC_BKP1R_Msk (0xFFFFFFFFUL << RTC_BKP1R_Pos)
    -
    11063#define RTC_BKP1R RTC_BKP1R_Msk
    -
    11064
    -
    11065/******************** Bits definition for RTC_BKP2R register ****************/
    -
    11066#define RTC_BKP2R_Pos (0U)
    -
    11067#define RTC_BKP2R_Msk (0xFFFFFFFFUL << RTC_BKP2R_Pos)
    -
    11068#define RTC_BKP2R RTC_BKP2R_Msk
    -
    11069
    -
    11070/******************** Bits definition for RTC_BKP3R register ****************/
    -
    11071#define RTC_BKP3R_Pos (0U)
    -
    11072#define RTC_BKP3R_Msk (0xFFFFFFFFUL << RTC_BKP3R_Pos)
    -
    11073#define RTC_BKP3R RTC_BKP3R_Msk
    -
    11074
    -
    11075/******************** Bits definition for RTC_BKP4R register ****************/
    -
    11076#define RTC_BKP4R_Pos (0U)
    -
    11077#define RTC_BKP4R_Msk (0xFFFFFFFFUL << RTC_BKP4R_Pos)
    -
    11078#define RTC_BKP4R RTC_BKP4R_Msk
    -
    11079
    -
    11080/******************** Bits definition for RTC_BKP5R register ****************/
    -
    11081#define RTC_BKP5R_Pos (0U)
    -
    11082#define RTC_BKP5R_Msk (0xFFFFFFFFUL << RTC_BKP5R_Pos)
    -
    11083#define RTC_BKP5R RTC_BKP5R_Msk
    -
    11084
    -
    11085/******************** Bits definition for RTC_BKP6R register ****************/
    -
    11086#define RTC_BKP6R_Pos (0U)
    -
    11087#define RTC_BKP6R_Msk (0xFFFFFFFFUL << RTC_BKP6R_Pos)
    -
    11088#define RTC_BKP6R RTC_BKP6R_Msk
    -
    11089
    -
    11090/******************** Bits definition for RTC_BKP7R register ****************/
    -
    11091#define RTC_BKP7R_Pos (0U)
    -
    11092#define RTC_BKP7R_Msk (0xFFFFFFFFUL << RTC_BKP7R_Pos)
    -
    11093#define RTC_BKP7R RTC_BKP7R_Msk
    -
    11094
    -
    11095/******************** Bits definition for RTC_BKP8R register ****************/
    -
    11096#define RTC_BKP8R_Pos (0U)
    -
    11097#define RTC_BKP8R_Msk (0xFFFFFFFFUL << RTC_BKP8R_Pos)
    -
    11098#define RTC_BKP8R RTC_BKP8R_Msk
    -
    11099
    -
    11100/******************** Bits definition for RTC_BKP9R register ****************/
    -
    11101#define RTC_BKP9R_Pos (0U)
    -
    11102#define RTC_BKP9R_Msk (0xFFFFFFFFUL << RTC_BKP9R_Pos)
    -
    11103#define RTC_BKP9R RTC_BKP9R_Msk
    -
    11104
    -
    11105/******************** Bits definition for RTC_BKP10R register ***************/
    -
    11106#define RTC_BKP10R_Pos (0U)
    -
    11107#define RTC_BKP10R_Msk (0xFFFFFFFFUL << RTC_BKP10R_Pos)
    -
    11108#define RTC_BKP10R RTC_BKP10R_Msk
    -
    11109
    -
    11110/******************** Bits definition for RTC_BKP11R register ***************/
    -
    11111#define RTC_BKP11R_Pos (0U)
    -
    11112#define RTC_BKP11R_Msk (0xFFFFFFFFUL << RTC_BKP11R_Pos)
    -
    11113#define RTC_BKP11R RTC_BKP11R_Msk
    -
    11114
    -
    11115/******************** Bits definition for RTC_BKP12R register ***************/
    -
    11116#define RTC_BKP12R_Pos (0U)
    -
    11117#define RTC_BKP12R_Msk (0xFFFFFFFFUL << RTC_BKP12R_Pos)
    -
    11118#define RTC_BKP12R RTC_BKP12R_Msk
    -
    11119
    -
    11120/******************** Bits definition for RTC_BKP13R register ***************/
    -
    11121#define RTC_BKP13R_Pos (0U)
    -
    11122#define RTC_BKP13R_Msk (0xFFFFFFFFUL << RTC_BKP13R_Pos)
    -
    11123#define RTC_BKP13R RTC_BKP13R_Msk
    -
    11124
    -
    11125/******************** Bits definition for RTC_BKP14R register ***************/
    -
    11126#define RTC_BKP14R_Pos (0U)
    -
    11127#define RTC_BKP14R_Msk (0xFFFFFFFFUL << RTC_BKP14R_Pos)
    -
    11128#define RTC_BKP14R RTC_BKP14R_Msk
    -
    11129
    -
    11130/******************** Bits definition for RTC_BKP15R register ***************/
    -
    11131#define RTC_BKP15R_Pos (0U)
    -
    11132#define RTC_BKP15R_Msk (0xFFFFFFFFUL << RTC_BKP15R_Pos)
    -
    11133#define RTC_BKP15R RTC_BKP15R_Msk
    -
    11134
    -
    11135/******************** Bits definition for RTC_BKP16R register ***************/
    -
    11136#define RTC_BKP16R_Pos (0U)
    -
    11137#define RTC_BKP16R_Msk (0xFFFFFFFFUL << RTC_BKP16R_Pos)
    -
    11138#define RTC_BKP16R RTC_BKP16R_Msk
    -
    11139
    -
    11140/******************** Bits definition for RTC_BKP17R register ***************/
    -
    11141#define RTC_BKP17R_Pos (0U)
    -
    11142#define RTC_BKP17R_Msk (0xFFFFFFFFUL << RTC_BKP17R_Pos)
    -
    11143#define RTC_BKP17R RTC_BKP17R_Msk
    -
    11144
    -
    11145/******************** Bits definition for RTC_BKP18R register ***************/
    -
    11146#define RTC_BKP18R_Pos (0U)
    -
    11147#define RTC_BKP18R_Msk (0xFFFFFFFFUL << RTC_BKP18R_Pos)
    -
    11148#define RTC_BKP18R RTC_BKP18R_Msk
    -
    11149
    -
    11150/******************** Bits definition for RTC_BKP19R register ***************/
    -
    11151#define RTC_BKP19R_Pos (0U)
    -
    11152#define RTC_BKP19R_Msk (0xFFFFFFFFUL << RTC_BKP19R_Pos)
    -
    11153#define RTC_BKP19R RTC_BKP19R_Msk
    -
    11154
    -
    11155/******************** Number of backup registers ******************************/
    -
    11156#define RTC_BKP_NUMBER 0x000000014U
    -
    11157
    -
    11158
    -
    11159/******************************************************************************/
    -
    11160/* */
    -
    11161/* SD host Interface */
    -
    11162/* */
    -
    11163/******************************************************************************/
    -
    11164/****************** Bit definition for SDIO_POWER register ******************/
    -
    11165#define SDIO_POWER_PWRCTRL_Pos (0U)
    -
    11166#define SDIO_POWER_PWRCTRL_Msk (0x3UL << SDIO_POWER_PWRCTRL_Pos)
    -
    11167#define SDIO_POWER_PWRCTRL SDIO_POWER_PWRCTRL_Msk
    -
    11168#define SDIO_POWER_PWRCTRL_0 (0x1UL << SDIO_POWER_PWRCTRL_Pos)
    -
    11169#define SDIO_POWER_PWRCTRL_1 (0x2UL << SDIO_POWER_PWRCTRL_Pos)
    -
    11171/****************** Bit definition for SDIO_CLKCR register ******************/
    -
    11172#define SDIO_CLKCR_CLKDIV_Pos (0U)
    -
    11173#define SDIO_CLKCR_CLKDIV_Msk (0xFFUL << SDIO_CLKCR_CLKDIV_Pos)
    -
    11174#define SDIO_CLKCR_CLKDIV SDIO_CLKCR_CLKDIV_Msk
    -
    11175#define SDIO_CLKCR_CLKEN_Pos (8U)
    -
    11176#define SDIO_CLKCR_CLKEN_Msk (0x1UL << SDIO_CLKCR_CLKEN_Pos)
    -
    11177#define SDIO_CLKCR_CLKEN SDIO_CLKCR_CLKEN_Msk
    -
    11178#define SDIO_CLKCR_PWRSAV_Pos (9U)
    -
    11179#define SDIO_CLKCR_PWRSAV_Msk (0x1UL << SDIO_CLKCR_PWRSAV_Pos)
    -
    11180#define SDIO_CLKCR_PWRSAV SDIO_CLKCR_PWRSAV_Msk
    -
    11181#define SDIO_CLKCR_BYPASS_Pos (10U)
    -
    11182#define SDIO_CLKCR_BYPASS_Msk (0x1UL << SDIO_CLKCR_BYPASS_Pos)
    -
    11183#define SDIO_CLKCR_BYPASS SDIO_CLKCR_BYPASS_Msk
    -
    11185#define SDIO_CLKCR_WIDBUS_Pos (11U)
    -
    11186#define SDIO_CLKCR_WIDBUS_Msk (0x3UL << SDIO_CLKCR_WIDBUS_Pos)
    -
    11187#define SDIO_CLKCR_WIDBUS SDIO_CLKCR_WIDBUS_Msk
    -
    11188#define SDIO_CLKCR_WIDBUS_0 (0x1UL << SDIO_CLKCR_WIDBUS_Pos)
    -
    11189#define SDIO_CLKCR_WIDBUS_1 (0x2UL << SDIO_CLKCR_WIDBUS_Pos)
    -
    11191#define SDIO_CLKCR_NEGEDGE_Pos (13U)
    -
    11192#define SDIO_CLKCR_NEGEDGE_Msk (0x1UL << SDIO_CLKCR_NEGEDGE_Pos)
    -
    11193#define SDIO_CLKCR_NEGEDGE SDIO_CLKCR_NEGEDGE_Msk
    -
    11194#define SDIO_CLKCR_HWFC_EN_Pos (14U)
    -
    11195#define SDIO_CLKCR_HWFC_EN_Msk (0x1UL << SDIO_CLKCR_HWFC_EN_Pos)
    -
    11196#define SDIO_CLKCR_HWFC_EN SDIO_CLKCR_HWFC_EN_Msk
    -
    11198/******************* Bit definition for SDIO_ARG register *******************/
    -
    11199#define SDIO_ARG_CMDARG_Pos (0U)
    -
    11200#define SDIO_ARG_CMDARG_Msk (0xFFFFFFFFUL << SDIO_ARG_CMDARG_Pos)
    -
    11201#define SDIO_ARG_CMDARG SDIO_ARG_CMDARG_Msk
    -
    11203/******************* Bit definition for SDIO_CMD register *******************/
    -
    11204#define SDIO_CMD_CMDINDEX_Pos (0U)
    -
    11205#define SDIO_CMD_CMDINDEX_Msk (0x3FUL << SDIO_CMD_CMDINDEX_Pos)
    -
    11206#define SDIO_CMD_CMDINDEX SDIO_CMD_CMDINDEX_Msk
    -
    11208#define SDIO_CMD_WAITRESP_Pos (6U)
    -
    11209#define SDIO_CMD_WAITRESP_Msk (0x3UL << SDIO_CMD_WAITRESP_Pos)
    -
    11210#define SDIO_CMD_WAITRESP SDIO_CMD_WAITRESP_Msk
    -
    11211#define SDIO_CMD_WAITRESP_0 (0x1UL << SDIO_CMD_WAITRESP_Pos)
    -
    11212#define SDIO_CMD_WAITRESP_1 (0x2UL << SDIO_CMD_WAITRESP_Pos)
    -
    11214#define SDIO_CMD_WAITINT_Pos (8U)
    -
    11215#define SDIO_CMD_WAITINT_Msk (0x1UL << SDIO_CMD_WAITINT_Pos)
    -
    11216#define SDIO_CMD_WAITINT SDIO_CMD_WAITINT_Msk
    -
    11217#define SDIO_CMD_WAITPEND_Pos (9U)
    -
    11218#define SDIO_CMD_WAITPEND_Msk (0x1UL << SDIO_CMD_WAITPEND_Pos)
    -
    11219#define SDIO_CMD_WAITPEND SDIO_CMD_WAITPEND_Msk
    -
    11220#define SDIO_CMD_CPSMEN_Pos (10U)
    -
    11221#define SDIO_CMD_CPSMEN_Msk (0x1UL << SDIO_CMD_CPSMEN_Pos)
    -
    11222#define SDIO_CMD_CPSMEN SDIO_CMD_CPSMEN_Msk
    -
    11223#define SDIO_CMD_SDIOSUSPEND_Pos (11U)
    -
    11224#define SDIO_CMD_SDIOSUSPEND_Msk (0x1UL << SDIO_CMD_SDIOSUSPEND_Pos)
    -
    11225#define SDIO_CMD_SDIOSUSPEND SDIO_CMD_SDIOSUSPEND_Msk
    -
    11226#define SDIO_CMD_ENCMDCOMPL_Pos (12U)
    -
    11227#define SDIO_CMD_ENCMDCOMPL_Msk (0x1UL << SDIO_CMD_ENCMDCOMPL_Pos)
    -
    11228#define SDIO_CMD_ENCMDCOMPL SDIO_CMD_ENCMDCOMPL_Msk
    -
    11229#define SDIO_CMD_NIEN_Pos (13U)
    -
    11230#define SDIO_CMD_NIEN_Msk (0x1UL << SDIO_CMD_NIEN_Pos)
    -
    11231#define SDIO_CMD_NIEN SDIO_CMD_NIEN_Msk
    -
    11232#define SDIO_CMD_CEATACMD_Pos (14U)
    -
    11233#define SDIO_CMD_CEATACMD_Msk (0x1UL << SDIO_CMD_CEATACMD_Pos)
    -
    11234#define SDIO_CMD_CEATACMD SDIO_CMD_CEATACMD_Msk
    -
    11236/***************** Bit definition for SDIO_RESPCMD register *****************/
    -
    11237#define SDIO_RESPCMD_RESPCMD_Pos (0U)
    -
    11238#define SDIO_RESPCMD_RESPCMD_Msk (0x3FUL << SDIO_RESPCMD_RESPCMD_Pos)
    -
    11239#define SDIO_RESPCMD_RESPCMD SDIO_RESPCMD_RESPCMD_Msk
    -
    11241/****************** Bit definition for SDIO_RESP0 register ******************/
    -
    11242#define SDIO_RESP0_CARDSTATUS0_Pos (0U)
    -
    11243#define SDIO_RESP0_CARDSTATUS0_Msk (0xFFFFFFFFUL << SDIO_RESP0_CARDSTATUS0_Pos)
    -
    11244#define SDIO_RESP0_CARDSTATUS0 SDIO_RESP0_CARDSTATUS0_Msk
    -
    11246/****************** Bit definition for SDIO_RESP1 register ******************/
    -
    11247#define SDIO_RESP1_CARDSTATUS1_Pos (0U)
    -
    11248#define SDIO_RESP1_CARDSTATUS1_Msk (0xFFFFFFFFUL << SDIO_RESP1_CARDSTATUS1_Pos)
    -
    11249#define SDIO_RESP1_CARDSTATUS1 SDIO_RESP1_CARDSTATUS1_Msk
    -
    11251/****************** Bit definition for SDIO_RESP2 register ******************/
    -
    11252#define SDIO_RESP2_CARDSTATUS2_Pos (0U)
    -
    11253#define SDIO_RESP2_CARDSTATUS2_Msk (0xFFFFFFFFUL << SDIO_RESP2_CARDSTATUS2_Pos)
    -
    11254#define SDIO_RESP2_CARDSTATUS2 SDIO_RESP2_CARDSTATUS2_Msk
    -
    11256/****************** Bit definition for SDIO_RESP3 register ******************/
    -
    11257#define SDIO_RESP3_CARDSTATUS3_Pos (0U)
    -
    11258#define SDIO_RESP3_CARDSTATUS3_Msk (0xFFFFFFFFUL << SDIO_RESP3_CARDSTATUS3_Pos)
    -
    11259#define SDIO_RESP3_CARDSTATUS3 SDIO_RESP3_CARDSTATUS3_Msk
    -
    11261/****************** Bit definition for SDIO_RESP4 register ******************/
    -
    11262#define SDIO_RESP4_CARDSTATUS4_Pos (0U)
    -
    11263#define SDIO_RESP4_CARDSTATUS4_Msk (0xFFFFFFFFUL << SDIO_RESP4_CARDSTATUS4_Pos)
    -
    11264#define SDIO_RESP4_CARDSTATUS4 SDIO_RESP4_CARDSTATUS4_Msk
    -
    11266/****************** Bit definition for SDIO_DTIMER register *****************/
    -
    11267#define SDIO_DTIMER_DATATIME_Pos (0U)
    -
    11268#define SDIO_DTIMER_DATATIME_Msk (0xFFFFFFFFUL << SDIO_DTIMER_DATATIME_Pos)
    -
    11269#define SDIO_DTIMER_DATATIME SDIO_DTIMER_DATATIME_Msk
    -
    11271/****************** Bit definition for SDIO_DLEN register *******************/
    -
    11272#define SDIO_DLEN_DATALENGTH_Pos (0U)
    -
    11273#define SDIO_DLEN_DATALENGTH_Msk (0x1FFFFFFUL << SDIO_DLEN_DATALENGTH_Pos)
    -
    11274#define SDIO_DLEN_DATALENGTH SDIO_DLEN_DATALENGTH_Msk
    -
    11276/****************** Bit definition for SDIO_DCTRL register ******************/
    -
    11277#define SDIO_DCTRL_DTEN_Pos (0U)
    -
    11278#define SDIO_DCTRL_DTEN_Msk (0x1UL << SDIO_DCTRL_DTEN_Pos)
    -
    11279#define SDIO_DCTRL_DTEN SDIO_DCTRL_DTEN_Msk
    -
    11280#define SDIO_DCTRL_DTDIR_Pos (1U)
    -
    11281#define SDIO_DCTRL_DTDIR_Msk (0x1UL << SDIO_DCTRL_DTDIR_Pos)
    -
    11282#define SDIO_DCTRL_DTDIR SDIO_DCTRL_DTDIR_Msk
    -
    11283#define SDIO_DCTRL_DTMODE_Pos (2U)
    -
    11284#define SDIO_DCTRL_DTMODE_Msk (0x1UL << SDIO_DCTRL_DTMODE_Pos)
    -
    11285#define SDIO_DCTRL_DTMODE SDIO_DCTRL_DTMODE_Msk
    -
    11286#define SDIO_DCTRL_DMAEN_Pos (3U)
    -
    11287#define SDIO_DCTRL_DMAEN_Msk (0x1UL << SDIO_DCTRL_DMAEN_Pos)
    -
    11288#define SDIO_DCTRL_DMAEN SDIO_DCTRL_DMAEN_Msk
    -
    11290#define SDIO_DCTRL_DBLOCKSIZE_Pos (4U)
    -
    11291#define SDIO_DCTRL_DBLOCKSIZE_Msk (0xFUL << SDIO_DCTRL_DBLOCKSIZE_Pos)
    -
    11292#define SDIO_DCTRL_DBLOCKSIZE SDIO_DCTRL_DBLOCKSIZE_Msk
    -
    11293#define SDIO_DCTRL_DBLOCKSIZE_0 (0x1UL << SDIO_DCTRL_DBLOCKSIZE_Pos)
    -
    11294#define SDIO_DCTRL_DBLOCKSIZE_1 (0x2UL << SDIO_DCTRL_DBLOCKSIZE_Pos)
    -
    11295#define SDIO_DCTRL_DBLOCKSIZE_2 (0x4UL << SDIO_DCTRL_DBLOCKSIZE_Pos)
    -
    11296#define SDIO_DCTRL_DBLOCKSIZE_3 (0x8UL << SDIO_DCTRL_DBLOCKSIZE_Pos)
    -
    11298#define SDIO_DCTRL_RWSTART_Pos (8U)
    -
    11299#define SDIO_DCTRL_RWSTART_Msk (0x1UL << SDIO_DCTRL_RWSTART_Pos)
    -
    11300#define SDIO_DCTRL_RWSTART SDIO_DCTRL_RWSTART_Msk
    -
    11301#define SDIO_DCTRL_RWSTOP_Pos (9U)
    -
    11302#define SDIO_DCTRL_RWSTOP_Msk (0x1UL << SDIO_DCTRL_RWSTOP_Pos)
    -
    11303#define SDIO_DCTRL_RWSTOP SDIO_DCTRL_RWSTOP_Msk
    -
    11304#define SDIO_DCTRL_RWMOD_Pos (10U)
    -
    11305#define SDIO_DCTRL_RWMOD_Msk (0x1UL << SDIO_DCTRL_RWMOD_Pos)
    -
    11306#define SDIO_DCTRL_RWMOD SDIO_DCTRL_RWMOD_Msk
    -
    11307#define SDIO_DCTRL_SDIOEN_Pos (11U)
    -
    11308#define SDIO_DCTRL_SDIOEN_Msk (0x1UL << SDIO_DCTRL_SDIOEN_Pos)
    -
    11309#define SDIO_DCTRL_SDIOEN SDIO_DCTRL_SDIOEN_Msk
    -
    11311/****************** Bit definition for SDIO_DCOUNT register *****************/
    -
    11312#define SDIO_DCOUNT_DATACOUNT_Pos (0U)
    -
    11313#define SDIO_DCOUNT_DATACOUNT_Msk (0x1FFFFFFUL << SDIO_DCOUNT_DATACOUNT_Pos)
    -
    11314#define SDIO_DCOUNT_DATACOUNT SDIO_DCOUNT_DATACOUNT_Msk
    -
    11316/****************** Bit definition for SDIO_STA register ********************/
    -
    11317#define SDIO_STA_CCRCFAIL_Pos (0U)
    -
    11318#define SDIO_STA_CCRCFAIL_Msk (0x1UL << SDIO_STA_CCRCFAIL_Pos)
    -
    11319#define SDIO_STA_CCRCFAIL SDIO_STA_CCRCFAIL_Msk
    -
    11320#define SDIO_STA_DCRCFAIL_Pos (1U)
    -
    11321#define SDIO_STA_DCRCFAIL_Msk (0x1UL << SDIO_STA_DCRCFAIL_Pos)
    -
    11322#define SDIO_STA_DCRCFAIL SDIO_STA_DCRCFAIL_Msk
    -
    11323#define SDIO_STA_CTIMEOUT_Pos (2U)
    -
    11324#define SDIO_STA_CTIMEOUT_Msk (0x1UL << SDIO_STA_CTIMEOUT_Pos)
    -
    11325#define SDIO_STA_CTIMEOUT SDIO_STA_CTIMEOUT_Msk
    -
    11326#define SDIO_STA_DTIMEOUT_Pos (3U)
    -
    11327#define SDIO_STA_DTIMEOUT_Msk (0x1UL << SDIO_STA_DTIMEOUT_Pos)
    -
    11328#define SDIO_STA_DTIMEOUT SDIO_STA_DTIMEOUT_Msk
    -
    11329#define SDIO_STA_TXUNDERR_Pos (4U)
    -
    11330#define SDIO_STA_TXUNDERR_Msk (0x1UL << SDIO_STA_TXUNDERR_Pos)
    -
    11331#define SDIO_STA_TXUNDERR SDIO_STA_TXUNDERR_Msk
    -
    11332#define SDIO_STA_RXOVERR_Pos (5U)
    -
    11333#define SDIO_STA_RXOVERR_Msk (0x1UL << SDIO_STA_RXOVERR_Pos)
    -
    11334#define SDIO_STA_RXOVERR SDIO_STA_RXOVERR_Msk
    -
    11335#define SDIO_STA_CMDREND_Pos (6U)
    -
    11336#define SDIO_STA_CMDREND_Msk (0x1UL << SDIO_STA_CMDREND_Pos)
    -
    11337#define SDIO_STA_CMDREND SDIO_STA_CMDREND_Msk
    -
    11338#define SDIO_STA_CMDSENT_Pos (7U)
    -
    11339#define SDIO_STA_CMDSENT_Msk (0x1UL << SDIO_STA_CMDSENT_Pos)
    -
    11340#define SDIO_STA_CMDSENT SDIO_STA_CMDSENT_Msk
    -
    11341#define SDIO_STA_DATAEND_Pos (8U)
    -
    11342#define SDIO_STA_DATAEND_Msk (0x1UL << SDIO_STA_DATAEND_Pos)
    -
    11343#define SDIO_STA_DATAEND SDIO_STA_DATAEND_Msk
    -
    11344#define SDIO_STA_STBITERR_Pos (9U)
    -
    11345#define SDIO_STA_STBITERR_Msk (0x1UL << SDIO_STA_STBITERR_Pos)
    -
    11346#define SDIO_STA_STBITERR SDIO_STA_STBITERR_Msk
    -
    11347#define SDIO_STA_DBCKEND_Pos (10U)
    -
    11348#define SDIO_STA_DBCKEND_Msk (0x1UL << SDIO_STA_DBCKEND_Pos)
    -
    11349#define SDIO_STA_DBCKEND SDIO_STA_DBCKEND_Msk
    -
    11350#define SDIO_STA_CMDACT_Pos (11U)
    -
    11351#define SDIO_STA_CMDACT_Msk (0x1UL << SDIO_STA_CMDACT_Pos)
    -
    11352#define SDIO_STA_CMDACT SDIO_STA_CMDACT_Msk
    -
    11353#define SDIO_STA_TXACT_Pos (12U)
    -
    11354#define SDIO_STA_TXACT_Msk (0x1UL << SDIO_STA_TXACT_Pos)
    -
    11355#define SDIO_STA_TXACT SDIO_STA_TXACT_Msk
    -
    11356#define SDIO_STA_RXACT_Pos (13U)
    -
    11357#define SDIO_STA_RXACT_Msk (0x1UL << SDIO_STA_RXACT_Pos)
    -
    11358#define SDIO_STA_RXACT SDIO_STA_RXACT_Msk
    -
    11359#define SDIO_STA_TXFIFOHE_Pos (14U)
    -
    11360#define SDIO_STA_TXFIFOHE_Msk (0x1UL << SDIO_STA_TXFIFOHE_Pos)
    -
    11361#define SDIO_STA_TXFIFOHE SDIO_STA_TXFIFOHE_Msk
    -
    11362#define SDIO_STA_RXFIFOHF_Pos (15U)
    -
    11363#define SDIO_STA_RXFIFOHF_Msk (0x1UL << SDIO_STA_RXFIFOHF_Pos)
    -
    11364#define SDIO_STA_RXFIFOHF SDIO_STA_RXFIFOHF_Msk
    -
    11365#define SDIO_STA_TXFIFOF_Pos (16U)
    -
    11366#define SDIO_STA_TXFIFOF_Msk (0x1UL << SDIO_STA_TXFIFOF_Pos)
    -
    11367#define SDIO_STA_TXFIFOF SDIO_STA_TXFIFOF_Msk
    -
    11368#define SDIO_STA_RXFIFOF_Pos (17U)
    -
    11369#define SDIO_STA_RXFIFOF_Msk (0x1UL << SDIO_STA_RXFIFOF_Pos)
    -
    11370#define SDIO_STA_RXFIFOF SDIO_STA_RXFIFOF_Msk
    -
    11371#define SDIO_STA_TXFIFOE_Pos (18U)
    -
    11372#define SDIO_STA_TXFIFOE_Msk (0x1UL << SDIO_STA_TXFIFOE_Pos)
    -
    11373#define SDIO_STA_TXFIFOE SDIO_STA_TXFIFOE_Msk
    -
    11374#define SDIO_STA_RXFIFOE_Pos (19U)
    -
    11375#define SDIO_STA_RXFIFOE_Msk (0x1UL << SDIO_STA_RXFIFOE_Pos)
    -
    11376#define SDIO_STA_RXFIFOE SDIO_STA_RXFIFOE_Msk
    -
    11377#define SDIO_STA_TXDAVL_Pos (20U)
    -
    11378#define SDIO_STA_TXDAVL_Msk (0x1UL << SDIO_STA_TXDAVL_Pos)
    -
    11379#define SDIO_STA_TXDAVL SDIO_STA_TXDAVL_Msk
    -
    11380#define SDIO_STA_RXDAVL_Pos (21U)
    -
    11381#define SDIO_STA_RXDAVL_Msk (0x1UL << SDIO_STA_RXDAVL_Pos)
    -
    11382#define SDIO_STA_RXDAVL SDIO_STA_RXDAVL_Msk
    -
    11383#define SDIO_STA_SDIOIT_Pos (22U)
    -
    11384#define SDIO_STA_SDIOIT_Msk (0x1UL << SDIO_STA_SDIOIT_Pos)
    -
    11385#define SDIO_STA_SDIOIT SDIO_STA_SDIOIT_Msk
    -
    11386#define SDIO_STA_CEATAEND_Pos (23U)
    -
    11387#define SDIO_STA_CEATAEND_Msk (0x1UL << SDIO_STA_CEATAEND_Pos)
    -
    11388#define SDIO_STA_CEATAEND SDIO_STA_CEATAEND_Msk
    -
    11390/******************* Bit definition for SDIO_ICR register *******************/
    -
    11391#define SDIO_ICR_CCRCFAILC_Pos (0U)
    -
    11392#define SDIO_ICR_CCRCFAILC_Msk (0x1UL << SDIO_ICR_CCRCFAILC_Pos)
    -
    11393#define SDIO_ICR_CCRCFAILC SDIO_ICR_CCRCFAILC_Msk
    -
    11394#define SDIO_ICR_DCRCFAILC_Pos (1U)
    -
    11395#define SDIO_ICR_DCRCFAILC_Msk (0x1UL << SDIO_ICR_DCRCFAILC_Pos)
    -
    11396#define SDIO_ICR_DCRCFAILC SDIO_ICR_DCRCFAILC_Msk
    -
    11397#define SDIO_ICR_CTIMEOUTC_Pos (2U)
    -
    11398#define SDIO_ICR_CTIMEOUTC_Msk (0x1UL << SDIO_ICR_CTIMEOUTC_Pos)
    -
    11399#define SDIO_ICR_CTIMEOUTC SDIO_ICR_CTIMEOUTC_Msk
    -
    11400#define SDIO_ICR_DTIMEOUTC_Pos (3U)
    -
    11401#define SDIO_ICR_DTIMEOUTC_Msk (0x1UL << SDIO_ICR_DTIMEOUTC_Pos)
    -
    11402#define SDIO_ICR_DTIMEOUTC SDIO_ICR_DTIMEOUTC_Msk
    -
    11403#define SDIO_ICR_TXUNDERRC_Pos (4U)
    -
    11404#define SDIO_ICR_TXUNDERRC_Msk (0x1UL << SDIO_ICR_TXUNDERRC_Pos)
    -
    11405#define SDIO_ICR_TXUNDERRC SDIO_ICR_TXUNDERRC_Msk
    -
    11406#define SDIO_ICR_RXOVERRC_Pos (5U)
    -
    11407#define SDIO_ICR_RXOVERRC_Msk (0x1UL << SDIO_ICR_RXOVERRC_Pos)
    -
    11408#define SDIO_ICR_RXOVERRC SDIO_ICR_RXOVERRC_Msk
    -
    11409#define SDIO_ICR_CMDRENDC_Pos (6U)
    -
    11410#define SDIO_ICR_CMDRENDC_Msk (0x1UL << SDIO_ICR_CMDRENDC_Pos)
    -
    11411#define SDIO_ICR_CMDRENDC SDIO_ICR_CMDRENDC_Msk
    -
    11412#define SDIO_ICR_CMDSENTC_Pos (7U)
    -
    11413#define SDIO_ICR_CMDSENTC_Msk (0x1UL << SDIO_ICR_CMDSENTC_Pos)
    -
    11414#define SDIO_ICR_CMDSENTC SDIO_ICR_CMDSENTC_Msk
    -
    11415#define SDIO_ICR_DATAENDC_Pos (8U)
    -
    11416#define SDIO_ICR_DATAENDC_Msk (0x1UL << SDIO_ICR_DATAENDC_Pos)
    -
    11417#define SDIO_ICR_DATAENDC SDIO_ICR_DATAENDC_Msk
    -
    11418#define SDIO_ICR_STBITERRC_Pos (9U)
    -
    11419#define SDIO_ICR_STBITERRC_Msk (0x1UL << SDIO_ICR_STBITERRC_Pos)
    -
    11420#define SDIO_ICR_STBITERRC SDIO_ICR_STBITERRC_Msk
    -
    11421#define SDIO_ICR_DBCKENDC_Pos (10U)
    -
    11422#define SDIO_ICR_DBCKENDC_Msk (0x1UL << SDIO_ICR_DBCKENDC_Pos)
    -
    11423#define SDIO_ICR_DBCKENDC SDIO_ICR_DBCKENDC_Msk
    -
    11424#define SDIO_ICR_SDIOITC_Pos (22U)
    -
    11425#define SDIO_ICR_SDIOITC_Msk (0x1UL << SDIO_ICR_SDIOITC_Pos)
    -
    11426#define SDIO_ICR_SDIOITC SDIO_ICR_SDIOITC_Msk
    -
    11427#define SDIO_ICR_CEATAENDC_Pos (23U)
    -
    11428#define SDIO_ICR_CEATAENDC_Msk (0x1UL << SDIO_ICR_CEATAENDC_Pos)
    -
    11429#define SDIO_ICR_CEATAENDC SDIO_ICR_CEATAENDC_Msk
    -
    11431/****************** Bit definition for SDIO_MASK register *******************/
    -
    11432#define SDIO_MASK_CCRCFAILIE_Pos (0U)
    -
    11433#define SDIO_MASK_CCRCFAILIE_Msk (0x1UL << SDIO_MASK_CCRCFAILIE_Pos)
    -
    11434#define SDIO_MASK_CCRCFAILIE SDIO_MASK_CCRCFAILIE_Msk
    -
    11435#define SDIO_MASK_DCRCFAILIE_Pos (1U)
    -
    11436#define SDIO_MASK_DCRCFAILIE_Msk (0x1UL << SDIO_MASK_DCRCFAILIE_Pos)
    -
    11437#define SDIO_MASK_DCRCFAILIE SDIO_MASK_DCRCFAILIE_Msk
    -
    11438#define SDIO_MASK_CTIMEOUTIE_Pos (2U)
    -
    11439#define SDIO_MASK_CTIMEOUTIE_Msk (0x1UL << SDIO_MASK_CTIMEOUTIE_Pos)
    -
    11440#define SDIO_MASK_CTIMEOUTIE SDIO_MASK_CTIMEOUTIE_Msk
    -
    11441#define SDIO_MASK_DTIMEOUTIE_Pos (3U)
    -
    11442#define SDIO_MASK_DTIMEOUTIE_Msk (0x1UL << SDIO_MASK_DTIMEOUTIE_Pos)
    -
    11443#define SDIO_MASK_DTIMEOUTIE SDIO_MASK_DTIMEOUTIE_Msk
    -
    11444#define SDIO_MASK_TXUNDERRIE_Pos (4U)
    -
    11445#define SDIO_MASK_TXUNDERRIE_Msk (0x1UL << SDIO_MASK_TXUNDERRIE_Pos)
    -
    11446#define SDIO_MASK_TXUNDERRIE SDIO_MASK_TXUNDERRIE_Msk
    -
    11447#define SDIO_MASK_RXOVERRIE_Pos (5U)
    -
    11448#define SDIO_MASK_RXOVERRIE_Msk (0x1UL << SDIO_MASK_RXOVERRIE_Pos)
    -
    11449#define SDIO_MASK_RXOVERRIE SDIO_MASK_RXOVERRIE_Msk
    -
    11450#define SDIO_MASK_CMDRENDIE_Pos (6U)
    -
    11451#define SDIO_MASK_CMDRENDIE_Msk (0x1UL << SDIO_MASK_CMDRENDIE_Pos)
    -
    11452#define SDIO_MASK_CMDRENDIE SDIO_MASK_CMDRENDIE_Msk
    -
    11453#define SDIO_MASK_CMDSENTIE_Pos (7U)
    -
    11454#define SDIO_MASK_CMDSENTIE_Msk (0x1UL << SDIO_MASK_CMDSENTIE_Pos)
    -
    11455#define SDIO_MASK_CMDSENTIE SDIO_MASK_CMDSENTIE_Msk
    -
    11456#define SDIO_MASK_DATAENDIE_Pos (8U)
    -
    11457#define SDIO_MASK_DATAENDIE_Msk (0x1UL << SDIO_MASK_DATAENDIE_Pos)
    -
    11458#define SDIO_MASK_DATAENDIE SDIO_MASK_DATAENDIE_Msk
    -
    11459#define SDIO_MASK_STBITERRIE_Pos (9U)
    -
    11460#define SDIO_MASK_STBITERRIE_Msk (0x1UL << SDIO_MASK_STBITERRIE_Pos)
    -
    11461#define SDIO_MASK_STBITERRIE SDIO_MASK_STBITERRIE_Msk
    -
    11462#define SDIO_MASK_DBCKENDIE_Pos (10U)
    -
    11463#define SDIO_MASK_DBCKENDIE_Msk (0x1UL << SDIO_MASK_DBCKENDIE_Pos)
    -
    11464#define SDIO_MASK_DBCKENDIE SDIO_MASK_DBCKENDIE_Msk
    -
    11465#define SDIO_MASK_CMDACTIE_Pos (11U)
    -
    11466#define SDIO_MASK_CMDACTIE_Msk (0x1UL << SDIO_MASK_CMDACTIE_Pos)
    -
    11467#define SDIO_MASK_CMDACTIE SDIO_MASK_CMDACTIE_Msk
    -
    11468#define SDIO_MASK_TXACTIE_Pos (12U)
    -
    11469#define SDIO_MASK_TXACTIE_Msk (0x1UL << SDIO_MASK_TXACTIE_Pos)
    -
    11470#define SDIO_MASK_TXACTIE SDIO_MASK_TXACTIE_Msk
    -
    11471#define SDIO_MASK_RXACTIE_Pos (13U)
    -
    11472#define SDIO_MASK_RXACTIE_Msk (0x1UL << SDIO_MASK_RXACTIE_Pos)
    -
    11473#define SDIO_MASK_RXACTIE SDIO_MASK_RXACTIE_Msk
    -
    11474#define SDIO_MASK_TXFIFOHEIE_Pos (14U)
    -
    11475#define SDIO_MASK_TXFIFOHEIE_Msk (0x1UL << SDIO_MASK_TXFIFOHEIE_Pos)
    -
    11476#define SDIO_MASK_TXFIFOHEIE SDIO_MASK_TXFIFOHEIE_Msk
    -
    11477#define SDIO_MASK_RXFIFOHFIE_Pos (15U)
    -
    11478#define SDIO_MASK_RXFIFOHFIE_Msk (0x1UL << SDIO_MASK_RXFIFOHFIE_Pos)
    -
    11479#define SDIO_MASK_RXFIFOHFIE SDIO_MASK_RXFIFOHFIE_Msk
    -
    11480#define SDIO_MASK_TXFIFOFIE_Pos (16U)
    -
    11481#define SDIO_MASK_TXFIFOFIE_Msk (0x1UL << SDIO_MASK_TXFIFOFIE_Pos)
    -
    11482#define SDIO_MASK_TXFIFOFIE SDIO_MASK_TXFIFOFIE_Msk
    -
    11483#define SDIO_MASK_RXFIFOFIE_Pos (17U)
    -
    11484#define SDIO_MASK_RXFIFOFIE_Msk (0x1UL << SDIO_MASK_RXFIFOFIE_Pos)
    -
    11485#define SDIO_MASK_RXFIFOFIE SDIO_MASK_RXFIFOFIE_Msk
    -
    11486#define SDIO_MASK_TXFIFOEIE_Pos (18U)
    -
    11487#define SDIO_MASK_TXFIFOEIE_Msk (0x1UL << SDIO_MASK_TXFIFOEIE_Pos)
    -
    11488#define SDIO_MASK_TXFIFOEIE SDIO_MASK_TXFIFOEIE_Msk
    -
    11489#define SDIO_MASK_RXFIFOEIE_Pos (19U)
    -
    11490#define SDIO_MASK_RXFIFOEIE_Msk (0x1UL << SDIO_MASK_RXFIFOEIE_Pos)
    -
    11491#define SDIO_MASK_RXFIFOEIE SDIO_MASK_RXFIFOEIE_Msk
    -
    11492#define SDIO_MASK_TXDAVLIE_Pos (20U)
    -
    11493#define SDIO_MASK_TXDAVLIE_Msk (0x1UL << SDIO_MASK_TXDAVLIE_Pos)
    -
    11494#define SDIO_MASK_TXDAVLIE SDIO_MASK_TXDAVLIE_Msk
    -
    11495#define SDIO_MASK_RXDAVLIE_Pos (21U)
    -
    11496#define SDIO_MASK_RXDAVLIE_Msk (0x1UL << SDIO_MASK_RXDAVLIE_Pos)
    -
    11497#define SDIO_MASK_RXDAVLIE SDIO_MASK_RXDAVLIE_Msk
    -
    11498#define SDIO_MASK_SDIOITIE_Pos (22U)
    -
    11499#define SDIO_MASK_SDIOITIE_Msk (0x1UL << SDIO_MASK_SDIOITIE_Pos)
    -
    11500#define SDIO_MASK_SDIOITIE SDIO_MASK_SDIOITIE_Msk
    -
    11501#define SDIO_MASK_CEATAENDIE_Pos (23U)
    -
    11502#define SDIO_MASK_CEATAENDIE_Msk (0x1UL << SDIO_MASK_CEATAENDIE_Pos)
    -
    11503#define SDIO_MASK_CEATAENDIE SDIO_MASK_CEATAENDIE_Msk
    -
    11505/***************** Bit definition for SDIO_FIFOCNT register *****************/
    -
    11506#define SDIO_FIFOCNT_FIFOCOUNT_Pos (0U)
    -
    11507#define SDIO_FIFOCNT_FIFOCOUNT_Msk (0xFFFFFFUL << SDIO_FIFOCNT_FIFOCOUNT_Pos)
    -
    11508#define SDIO_FIFOCNT_FIFOCOUNT SDIO_FIFOCNT_FIFOCOUNT_Msk
    -
    11510/****************** Bit definition for SDIO_FIFO register *******************/
    -
    11511#define SDIO_FIFO_FIFODATA_Pos (0U)
    -
    11512#define SDIO_FIFO_FIFODATA_Msk (0xFFFFFFFFUL << SDIO_FIFO_FIFODATA_Pos)
    -
    11513#define SDIO_FIFO_FIFODATA SDIO_FIFO_FIFODATA_Msk
    -
    11515/******************************************************************************/
    -
    11516/* */
    -
    11517/* Serial Peripheral Interface */
    -
    11518/* */
    -
    11519/******************************************************************************/
    -
    11520#define SPI_I2S_FULLDUPLEX_SUPPORT
    -
    11522/******************* Bit definition for SPI_CR1 register ********************/
    -
    11523#define SPI_CR1_CPHA_Pos (0U)
    -
    11524#define SPI_CR1_CPHA_Msk (0x1UL << SPI_CR1_CPHA_Pos)
    -
    11525#define SPI_CR1_CPHA SPI_CR1_CPHA_Msk
    -
    11526#define SPI_CR1_CPOL_Pos (1U)
    -
    11527#define SPI_CR1_CPOL_Msk (0x1UL << SPI_CR1_CPOL_Pos)
    -
    11528#define SPI_CR1_CPOL SPI_CR1_CPOL_Msk
    -
    11529#define SPI_CR1_MSTR_Pos (2U)
    -
    11530#define SPI_CR1_MSTR_Msk (0x1UL << SPI_CR1_MSTR_Pos)
    -
    11531#define SPI_CR1_MSTR SPI_CR1_MSTR_Msk
    -
    11533#define SPI_CR1_BR_Pos (3U)
    -
    11534#define SPI_CR1_BR_Msk (0x7UL << SPI_CR1_BR_Pos)
    -
    11535#define SPI_CR1_BR SPI_CR1_BR_Msk
    -
    11536#define SPI_CR1_BR_0 (0x1UL << SPI_CR1_BR_Pos)
    -
    11537#define SPI_CR1_BR_1 (0x2UL << SPI_CR1_BR_Pos)
    -
    11538#define SPI_CR1_BR_2 (0x4UL << SPI_CR1_BR_Pos)
    -
    11540#define SPI_CR1_SPE_Pos (6U)
    -
    11541#define SPI_CR1_SPE_Msk (0x1UL << SPI_CR1_SPE_Pos)
    -
    11542#define SPI_CR1_SPE SPI_CR1_SPE_Msk
    -
    11543#define SPI_CR1_LSBFIRST_Pos (7U)
    -
    11544#define SPI_CR1_LSBFIRST_Msk (0x1UL << SPI_CR1_LSBFIRST_Pos)
    -
    11545#define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk
    -
    11546#define SPI_CR1_SSI_Pos (8U)
    -
    11547#define SPI_CR1_SSI_Msk (0x1UL << SPI_CR1_SSI_Pos)
    -
    11548#define SPI_CR1_SSI SPI_CR1_SSI_Msk
    -
    11549#define SPI_CR1_SSM_Pos (9U)
    -
    11550#define SPI_CR1_SSM_Msk (0x1UL << SPI_CR1_SSM_Pos)
    -
    11551#define SPI_CR1_SSM SPI_CR1_SSM_Msk
    -
    11552#define SPI_CR1_RXONLY_Pos (10U)
    -
    11553#define SPI_CR1_RXONLY_Msk (0x1UL << SPI_CR1_RXONLY_Pos)
    -
    11554#define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk
    -
    11555#define SPI_CR1_DFF_Pos (11U)
    -
    11556#define SPI_CR1_DFF_Msk (0x1UL << SPI_CR1_DFF_Pos)
    -
    11557#define SPI_CR1_DFF SPI_CR1_DFF_Msk
    -
    11558#define SPI_CR1_CRCNEXT_Pos (12U)
    -
    11559#define SPI_CR1_CRCNEXT_Msk (0x1UL << SPI_CR1_CRCNEXT_Pos)
    -
    11560#define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk
    -
    11561#define SPI_CR1_CRCEN_Pos (13U)
    -
    11562#define SPI_CR1_CRCEN_Msk (0x1UL << SPI_CR1_CRCEN_Pos)
    -
    11563#define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk
    -
    11564#define SPI_CR1_BIDIOE_Pos (14U)
    -
    11565#define SPI_CR1_BIDIOE_Msk (0x1UL << SPI_CR1_BIDIOE_Pos)
    -
    11566#define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk
    -
    11567#define SPI_CR1_BIDIMODE_Pos (15U)
    -
    11568#define SPI_CR1_BIDIMODE_Msk (0x1UL << SPI_CR1_BIDIMODE_Pos)
    -
    11569#define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk
    -
    11571/******************* Bit definition for SPI_CR2 register ********************/
    -
    11572#define SPI_CR2_RXDMAEN_Pos (0U)
    -
    11573#define SPI_CR2_RXDMAEN_Msk (0x1UL << SPI_CR2_RXDMAEN_Pos)
    -
    11574#define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk
    -
    11575#define SPI_CR2_TXDMAEN_Pos (1U)
    -
    11576#define SPI_CR2_TXDMAEN_Msk (0x1UL << SPI_CR2_TXDMAEN_Pos)
    -
    11577#define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk
    -
    11578#define SPI_CR2_SSOE_Pos (2U)
    -
    11579#define SPI_CR2_SSOE_Msk (0x1UL << SPI_CR2_SSOE_Pos)
    -
    11580#define SPI_CR2_SSOE SPI_CR2_SSOE_Msk
    -
    11581#define SPI_CR2_FRF_Pos (4U)
    -
    11582#define SPI_CR2_FRF_Msk (0x1UL << SPI_CR2_FRF_Pos)
    -
    11583#define SPI_CR2_FRF SPI_CR2_FRF_Msk
    -
    11584#define SPI_CR2_ERRIE_Pos (5U)
    -
    11585#define SPI_CR2_ERRIE_Msk (0x1UL << SPI_CR2_ERRIE_Pos)
    -
    11586#define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk
    -
    11587#define SPI_CR2_RXNEIE_Pos (6U)
    -
    11588#define SPI_CR2_RXNEIE_Msk (0x1UL << SPI_CR2_RXNEIE_Pos)
    -
    11589#define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk
    -
    11590#define SPI_CR2_TXEIE_Pos (7U)
    -
    11591#define SPI_CR2_TXEIE_Msk (0x1UL << SPI_CR2_TXEIE_Pos)
    -
    11592#define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk
    -
    11594/******************** Bit definition for SPI_SR register ********************/
    -
    11595#define SPI_SR_RXNE_Pos (0U)
    -
    11596#define SPI_SR_RXNE_Msk (0x1UL << SPI_SR_RXNE_Pos)
    -
    11597#define SPI_SR_RXNE SPI_SR_RXNE_Msk
    -
    11598#define SPI_SR_TXE_Pos (1U)
    -
    11599#define SPI_SR_TXE_Msk (0x1UL << SPI_SR_TXE_Pos)
    -
    11600#define SPI_SR_TXE SPI_SR_TXE_Msk
    -
    11601#define SPI_SR_CHSIDE_Pos (2U)
    -
    11602#define SPI_SR_CHSIDE_Msk (0x1UL << SPI_SR_CHSIDE_Pos)
    -
    11603#define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk
    -
    11604#define SPI_SR_UDR_Pos (3U)
    -
    11605#define SPI_SR_UDR_Msk (0x1UL << SPI_SR_UDR_Pos)
    -
    11606#define SPI_SR_UDR SPI_SR_UDR_Msk
    -
    11607#define SPI_SR_CRCERR_Pos (4U)
    -
    11608#define SPI_SR_CRCERR_Msk (0x1UL << SPI_SR_CRCERR_Pos)
    -
    11609#define SPI_SR_CRCERR SPI_SR_CRCERR_Msk
    -
    11610#define SPI_SR_MODF_Pos (5U)
    -
    11611#define SPI_SR_MODF_Msk (0x1UL << SPI_SR_MODF_Pos)
    -
    11612#define SPI_SR_MODF SPI_SR_MODF_Msk
    -
    11613#define SPI_SR_OVR_Pos (6U)
    -
    11614#define SPI_SR_OVR_Msk (0x1UL << SPI_SR_OVR_Pos)
    -
    11615#define SPI_SR_OVR SPI_SR_OVR_Msk
    -
    11616#define SPI_SR_BSY_Pos (7U)
    -
    11617#define SPI_SR_BSY_Msk (0x1UL << SPI_SR_BSY_Pos)
    -
    11618#define SPI_SR_BSY SPI_SR_BSY_Msk
    -
    11619#define SPI_SR_FRE_Pos (8U)
    -
    11620#define SPI_SR_FRE_Msk (0x1UL << SPI_SR_FRE_Pos)
    -
    11621#define SPI_SR_FRE SPI_SR_FRE_Msk
    -
    11623/******************** Bit definition for SPI_DR register ********************/
    -
    11624#define SPI_DR_DR_Pos (0U)
    -
    11625#define SPI_DR_DR_Msk (0xFFFFUL << SPI_DR_DR_Pos)
    -
    11626#define SPI_DR_DR SPI_DR_DR_Msk
    -
    11628/******************* Bit definition for SPI_CRCPR register ******************/
    -
    11629#define SPI_CRCPR_CRCPOLY_Pos (0U)
    -
    11630#define SPI_CRCPR_CRCPOLY_Msk (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos)
    -
    11631#define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk
    -
    11633/****************** Bit definition for SPI_RXCRCR register ******************/
    -
    11634#define SPI_RXCRCR_RXCRC_Pos (0U)
    -
    11635#define SPI_RXCRCR_RXCRC_Msk (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos)
    -
    11636#define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk
    -
    11638/****************** Bit definition for SPI_TXCRCR register ******************/
    -
    11639#define SPI_TXCRCR_TXCRC_Pos (0U)
    -
    11640#define SPI_TXCRCR_TXCRC_Msk (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos)
    -
    11641#define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk
    -
    11643/****************** Bit definition for SPI_I2SCFGR register *****************/
    -
    11644#define SPI_I2SCFGR_CHLEN_Pos (0U)
    -
    11645#define SPI_I2SCFGR_CHLEN_Msk (0x1UL << SPI_I2SCFGR_CHLEN_Pos)
    -
    11646#define SPI_I2SCFGR_CHLEN SPI_I2SCFGR_CHLEN_Msk
    -
    11648#define SPI_I2SCFGR_DATLEN_Pos (1U)
    -
    11649#define SPI_I2SCFGR_DATLEN_Msk (0x3UL << SPI_I2SCFGR_DATLEN_Pos)
    -
    11650#define SPI_I2SCFGR_DATLEN SPI_I2SCFGR_DATLEN_Msk
    -
    11651#define SPI_I2SCFGR_DATLEN_0 (0x1UL << SPI_I2SCFGR_DATLEN_Pos)
    -
    11652#define SPI_I2SCFGR_DATLEN_1 (0x2UL << SPI_I2SCFGR_DATLEN_Pos)
    -
    11654#define SPI_I2SCFGR_CKPOL_Pos (3U)
    -
    11655#define SPI_I2SCFGR_CKPOL_Msk (0x1UL << SPI_I2SCFGR_CKPOL_Pos)
    -
    11656#define SPI_I2SCFGR_CKPOL SPI_I2SCFGR_CKPOL_Msk
    -
    11658#define SPI_I2SCFGR_I2SSTD_Pos (4U)
    -
    11659#define SPI_I2SCFGR_I2SSTD_Msk (0x3UL << SPI_I2SCFGR_I2SSTD_Pos)
    -
    11660#define SPI_I2SCFGR_I2SSTD SPI_I2SCFGR_I2SSTD_Msk
    -
    11661#define SPI_I2SCFGR_I2SSTD_0 (0x1UL << SPI_I2SCFGR_I2SSTD_Pos)
    -
    11662#define SPI_I2SCFGR_I2SSTD_1 (0x2UL << SPI_I2SCFGR_I2SSTD_Pos)
    -
    11664#define SPI_I2SCFGR_PCMSYNC_Pos (7U)
    -
    11665#define SPI_I2SCFGR_PCMSYNC_Msk (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos)
    -
    11666#define SPI_I2SCFGR_PCMSYNC SPI_I2SCFGR_PCMSYNC_Msk
    -
    11668#define SPI_I2SCFGR_I2SCFG_Pos (8U)
    -
    11669#define SPI_I2SCFGR_I2SCFG_Msk (0x3UL << SPI_I2SCFGR_I2SCFG_Pos)
    -
    11670#define SPI_I2SCFGR_I2SCFG SPI_I2SCFGR_I2SCFG_Msk
    -
    11671#define SPI_I2SCFGR_I2SCFG_0 (0x1UL << SPI_I2SCFGR_I2SCFG_Pos)
    -
    11672#define SPI_I2SCFGR_I2SCFG_1 (0x2UL << SPI_I2SCFGR_I2SCFG_Pos)
    -
    11674#define SPI_I2SCFGR_I2SE_Pos (10U)
    -
    11675#define SPI_I2SCFGR_I2SE_Msk (0x1UL << SPI_I2SCFGR_I2SE_Pos)
    -
    11676#define SPI_I2SCFGR_I2SE SPI_I2SCFGR_I2SE_Msk
    -
    11677#define SPI_I2SCFGR_I2SMOD_Pos (11U)
    -
    11678#define SPI_I2SCFGR_I2SMOD_Msk (0x1UL << SPI_I2SCFGR_I2SMOD_Pos)
    -
    11679#define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk
    -
    11681/****************** Bit definition for SPI_I2SPR register *******************/
    -
    11682#define SPI_I2SPR_I2SDIV_Pos (0U)
    -
    11683#define SPI_I2SPR_I2SDIV_Msk (0xFFUL << SPI_I2SPR_I2SDIV_Pos)
    -
    11684#define SPI_I2SPR_I2SDIV SPI_I2SPR_I2SDIV_Msk
    -
    11685#define SPI_I2SPR_ODD_Pos (8U)
    -
    11686#define SPI_I2SPR_ODD_Msk (0x1UL << SPI_I2SPR_ODD_Pos)
    -
    11687#define SPI_I2SPR_ODD SPI_I2SPR_ODD_Msk
    -
    11688#define SPI_I2SPR_MCKOE_Pos (9U)
    -
    11689#define SPI_I2SPR_MCKOE_Msk (0x1UL << SPI_I2SPR_MCKOE_Pos)
    -
    11690#define SPI_I2SPR_MCKOE SPI_I2SPR_MCKOE_Msk
    -
    11692/******************************************************************************/
    -
    11693/* */
    -
    11694/* SYSCFG */
    -
    11695/* */
    -
    11696/******************************************************************************/
    -
    11697/****************** Bit definition for SYSCFG_MEMRMP register ***************/
    -
    11698#define SYSCFG_MEMRMP_MEM_MODE_Pos (0U)
    -
    11699#define SYSCFG_MEMRMP_MEM_MODE_Msk (0x3UL << SYSCFG_MEMRMP_MEM_MODE_Pos)
    -
    11700#define SYSCFG_MEMRMP_MEM_MODE SYSCFG_MEMRMP_MEM_MODE_Msk
    -
    11701#define SYSCFG_MEMRMP_MEM_MODE_0 (0x1UL << SYSCFG_MEMRMP_MEM_MODE_Pos)
    -
    11702#define SYSCFG_MEMRMP_MEM_MODE_1 (0x2UL << SYSCFG_MEMRMP_MEM_MODE_Pos)
    -
    11703/****************** Bit definition for SYSCFG_PMC register ******************/
    -
    11704#define SYSCFG_PMC_MII_RMII_SEL_Pos (23U)
    -
    11705#define SYSCFG_PMC_MII_RMII_SEL_Msk (0x1UL << SYSCFG_PMC_MII_RMII_SEL_Pos)
    -
    11706#define SYSCFG_PMC_MII_RMII_SEL SYSCFG_PMC_MII_RMII_SEL_Msk
    -
    11707/* Old MII_RMII_SEL bit definition, maintained for legacy purpose */
    -
    11708#define SYSCFG_PMC_MII_RMII SYSCFG_PMC_MII_RMII_SEL
    -
    11709
    -
    11710/***************** Bit definition for SYSCFG_EXTICR1 register ***************/
    -
    11711#define SYSCFG_EXTICR1_EXTI0_Pos (0U)
    -
    11712#define SYSCFG_EXTICR1_EXTI0_Msk (0xFUL << SYSCFG_EXTICR1_EXTI0_Pos)
    -
    11713#define SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk
    -
    11714#define SYSCFG_EXTICR1_EXTI1_Pos (4U)
    -
    11715#define SYSCFG_EXTICR1_EXTI1_Msk (0xFUL << SYSCFG_EXTICR1_EXTI1_Pos)
    -
    11716#define SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk
    -
    11717#define SYSCFG_EXTICR1_EXTI2_Pos (8U)
    -
    11718#define SYSCFG_EXTICR1_EXTI2_Msk (0xFUL << SYSCFG_EXTICR1_EXTI2_Pos)
    -
    11719#define SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk
    -
    11720#define SYSCFG_EXTICR1_EXTI3_Pos (12U)
    -
    11721#define SYSCFG_EXTICR1_EXTI3_Msk (0xFUL << SYSCFG_EXTICR1_EXTI3_Pos)
    -
    11722#define SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk
    -
    11726#define SYSCFG_EXTICR1_EXTI0_PA 0x0000U
    -
    11727#define SYSCFG_EXTICR1_EXTI0_PB 0x0001U
    -
    11728#define SYSCFG_EXTICR1_EXTI0_PC 0x0002U
    -
    11729#define SYSCFG_EXTICR1_EXTI0_PD 0x0003U
    -
    11730#define SYSCFG_EXTICR1_EXTI0_PE 0x0004U
    -
    11731#define SYSCFG_EXTICR1_EXTI0_PF 0x0005U
    -
    11732#define SYSCFG_EXTICR1_EXTI0_PG 0x0006U
    -
    11733#define SYSCFG_EXTICR1_EXTI0_PH 0x0007U
    -
    11734#define SYSCFG_EXTICR1_EXTI0_PI 0x0008U
    -
    11739#define SYSCFG_EXTICR1_EXTI1_PA 0x0000U
    -
    11740#define SYSCFG_EXTICR1_EXTI1_PB 0x0010U
    -
    11741#define SYSCFG_EXTICR1_EXTI1_PC 0x0020U
    -
    11742#define SYSCFG_EXTICR1_EXTI1_PD 0x0030U
    -
    11743#define SYSCFG_EXTICR1_EXTI1_PE 0x0040U
    -
    11744#define SYSCFG_EXTICR1_EXTI1_PF 0x0050U
    -
    11745#define SYSCFG_EXTICR1_EXTI1_PG 0x0060U
    -
    11746#define SYSCFG_EXTICR1_EXTI1_PH 0x0070U
    -
    11747#define SYSCFG_EXTICR1_EXTI1_PI 0x0080U
    -
    11752#define SYSCFG_EXTICR1_EXTI2_PA 0x0000U
    -
    11753#define SYSCFG_EXTICR1_EXTI2_PB 0x0100U
    -
    11754#define SYSCFG_EXTICR1_EXTI2_PC 0x0200U
    -
    11755#define SYSCFG_EXTICR1_EXTI2_PD 0x0300U
    -
    11756#define SYSCFG_EXTICR1_EXTI2_PE 0x0400U
    -
    11757#define SYSCFG_EXTICR1_EXTI2_PF 0x0500U
    -
    11758#define SYSCFG_EXTICR1_EXTI2_PG 0x0600U
    -
    11759#define SYSCFG_EXTICR1_EXTI2_PH 0x0700U
    -
    11760#define SYSCFG_EXTICR1_EXTI2_PI 0x0800U
    -
    11765#define SYSCFG_EXTICR1_EXTI3_PA 0x0000U
    -
    11766#define SYSCFG_EXTICR1_EXTI3_PB 0x1000U
    -
    11767#define SYSCFG_EXTICR1_EXTI3_PC 0x2000U
    -
    11768#define SYSCFG_EXTICR1_EXTI3_PD 0x3000U
    -
    11769#define SYSCFG_EXTICR1_EXTI3_PE 0x4000U
    -
    11770#define SYSCFG_EXTICR1_EXTI3_PF 0x5000U
    -
    11771#define SYSCFG_EXTICR1_EXTI3_PG 0x6000U
    -
    11772#define SYSCFG_EXTICR1_EXTI3_PH 0x7000U
    -
    11773#define SYSCFG_EXTICR1_EXTI3_PI 0x8000U
    -
    11775/***************** Bit definition for SYSCFG_EXTICR2 register ***************/
    -
    11776#define SYSCFG_EXTICR2_EXTI4_Pos (0U)
    -
    11777#define SYSCFG_EXTICR2_EXTI4_Msk (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos)
    -
    11778#define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk
    -
    11779#define SYSCFG_EXTICR2_EXTI5_Pos (4U)
    -
    11780#define SYSCFG_EXTICR2_EXTI5_Msk (0xFUL << SYSCFG_EXTICR2_EXTI5_Pos)
    -
    11781#define SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk
    -
    11782#define SYSCFG_EXTICR2_EXTI6_Pos (8U)
    -
    11783#define SYSCFG_EXTICR2_EXTI6_Msk (0xFUL << SYSCFG_EXTICR2_EXTI6_Pos)
    -
    11784#define SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk
    -
    11785#define SYSCFG_EXTICR2_EXTI7_Pos (12U)
    -
    11786#define SYSCFG_EXTICR2_EXTI7_Msk (0xFUL << SYSCFG_EXTICR2_EXTI7_Pos)
    -
    11787#define SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk
    -
    11792#define SYSCFG_EXTICR2_EXTI4_PA 0x0000U
    -
    11793#define SYSCFG_EXTICR2_EXTI4_PB 0x0001U
    -
    11794#define SYSCFG_EXTICR2_EXTI4_PC 0x0002U
    -
    11795#define SYSCFG_EXTICR2_EXTI4_PD 0x0003U
    -
    11796#define SYSCFG_EXTICR2_EXTI4_PE 0x0004U
    -
    11797#define SYSCFG_EXTICR2_EXTI4_PF 0x0005U
    -
    11798#define SYSCFG_EXTICR2_EXTI4_PG 0x0006U
    -
    11799#define SYSCFG_EXTICR2_EXTI4_PH 0x0007U
    -
    11800#define SYSCFG_EXTICR2_EXTI4_PI 0x0008U
    -
    11805#define SYSCFG_EXTICR2_EXTI5_PA 0x0000U
    -
    11806#define SYSCFG_EXTICR2_EXTI5_PB 0x0010U
    -
    11807#define SYSCFG_EXTICR2_EXTI5_PC 0x0020U
    -
    11808#define SYSCFG_EXTICR2_EXTI5_PD 0x0030U
    -
    11809#define SYSCFG_EXTICR2_EXTI5_PE 0x0040U
    -
    11810#define SYSCFG_EXTICR2_EXTI5_PF 0x0050U
    -
    11811#define SYSCFG_EXTICR2_EXTI5_PG 0x0060U
    -
    11812#define SYSCFG_EXTICR2_EXTI5_PH 0x0070U
    -
    11813#define SYSCFG_EXTICR2_EXTI5_PI 0x0080U
    -
    11818#define SYSCFG_EXTICR2_EXTI6_PA 0x0000U
    -
    11819#define SYSCFG_EXTICR2_EXTI6_PB 0x0100U
    -
    11820#define SYSCFG_EXTICR2_EXTI6_PC 0x0200U
    -
    11821#define SYSCFG_EXTICR2_EXTI6_PD 0x0300U
    -
    11822#define SYSCFG_EXTICR2_EXTI6_PE 0x0400U
    -
    11823#define SYSCFG_EXTICR2_EXTI6_PF 0x0500U
    -
    11824#define SYSCFG_EXTICR2_EXTI6_PG 0x0600U
    -
    11825#define SYSCFG_EXTICR2_EXTI6_PH 0x0700U
    -
    11826#define SYSCFG_EXTICR2_EXTI6_PI 0x0800U
    -
    11831#define SYSCFG_EXTICR2_EXTI7_PA 0x0000U
    -
    11832#define SYSCFG_EXTICR2_EXTI7_PB 0x1000U
    -
    11833#define SYSCFG_EXTICR2_EXTI7_PC 0x2000U
    -
    11834#define SYSCFG_EXTICR2_EXTI7_PD 0x3000U
    -
    11835#define SYSCFG_EXTICR2_EXTI7_PE 0x4000U
    -
    11836#define SYSCFG_EXTICR2_EXTI7_PF 0x5000U
    -
    11837#define SYSCFG_EXTICR2_EXTI7_PG 0x6000U
    -
    11838#define SYSCFG_EXTICR2_EXTI7_PH 0x7000U
    -
    11839#define SYSCFG_EXTICR2_EXTI7_PI 0x8000U
    -
    11841/***************** Bit definition for SYSCFG_EXTICR3 register ***************/
    -
    11842#define SYSCFG_EXTICR3_EXTI8_Pos (0U)
    -
    11843#define SYSCFG_EXTICR3_EXTI8_Msk (0xFUL << SYSCFG_EXTICR3_EXTI8_Pos)
    -
    11844#define SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk
    -
    11845#define SYSCFG_EXTICR3_EXTI9_Pos (4U)
    -
    11846#define SYSCFG_EXTICR3_EXTI9_Msk (0xFUL << SYSCFG_EXTICR3_EXTI9_Pos)
    -
    11847#define SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk
    -
    11848#define SYSCFG_EXTICR3_EXTI10_Pos (8U)
    -
    11849#define SYSCFG_EXTICR3_EXTI10_Msk (0xFUL << SYSCFG_EXTICR3_EXTI10_Pos)
    -
    11850#define SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk
    -
    11851#define SYSCFG_EXTICR3_EXTI11_Pos (12U)
    -
    11852#define SYSCFG_EXTICR3_EXTI11_Msk (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos)
    -
    11853#define SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk
    -
    11858#define SYSCFG_EXTICR3_EXTI8_PA 0x0000U
    -
    11859#define SYSCFG_EXTICR3_EXTI8_PB 0x0001U
    -
    11860#define SYSCFG_EXTICR3_EXTI8_PC 0x0002U
    -
    11861#define SYSCFG_EXTICR3_EXTI8_PD 0x0003U
    -
    11862#define SYSCFG_EXTICR3_EXTI8_PE 0x0004U
    -
    11863#define SYSCFG_EXTICR3_EXTI8_PF 0x0005U
    -
    11864#define SYSCFG_EXTICR3_EXTI8_PG 0x0006U
    -
    11865#define SYSCFG_EXTICR3_EXTI8_PH 0x0007U
    -
    11866#define SYSCFG_EXTICR3_EXTI8_PI 0x0008U
    -
    11871#define SYSCFG_EXTICR3_EXTI9_PA 0x0000U
    -
    11872#define SYSCFG_EXTICR3_EXTI9_PB 0x0010U
    -
    11873#define SYSCFG_EXTICR3_EXTI9_PC 0x0020U
    -
    11874#define SYSCFG_EXTICR3_EXTI9_PD 0x0030U
    -
    11875#define SYSCFG_EXTICR3_EXTI9_PE 0x0040U
    -
    11876#define SYSCFG_EXTICR3_EXTI9_PF 0x0050U
    -
    11877#define SYSCFG_EXTICR3_EXTI9_PG 0x0060U
    -
    11878#define SYSCFG_EXTICR3_EXTI9_PH 0x0070U
    -
    11879#define SYSCFG_EXTICR3_EXTI9_PI 0x0080U
    -
    11884#define SYSCFG_EXTICR3_EXTI10_PA 0x0000U
    -
    11885#define SYSCFG_EXTICR3_EXTI10_PB 0x0100U
    -
    11886#define SYSCFG_EXTICR3_EXTI10_PC 0x0200U
    -
    11887#define SYSCFG_EXTICR3_EXTI10_PD 0x0300U
    -
    11888#define SYSCFG_EXTICR3_EXTI10_PE 0x0400U
    -
    11889#define SYSCFG_EXTICR3_EXTI10_PF 0x0500U
    -
    11890#define SYSCFG_EXTICR3_EXTI10_PG 0x0600U
    -
    11891#define SYSCFG_EXTICR3_EXTI10_PH 0x0700U
    -
    11892#define SYSCFG_EXTICR3_EXTI10_PI 0x0800U
    -
    11897#define SYSCFG_EXTICR3_EXTI11_PA 0x0000U
    -
    11898#define SYSCFG_EXTICR3_EXTI11_PB 0x1000U
    -
    11899#define SYSCFG_EXTICR3_EXTI11_PC 0x2000U
    -
    11900#define SYSCFG_EXTICR3_EXTI11_PD 0x3000U
    -
    11901#define SYSCFG_EXTICR3_EXTI11_PE 0x4000U
    -
    11902#define SYSCFG_EXTICR3_EXTI11_PF 0x5000U
    -
    11903#define SYSCFG_EXTICR3_EXTI11_PG 0x6000U
    -
    11904#define SYSCFG_EXTICR3_EXTI11_PH 0x7000U
    -
    11905#define SYSCFG_EXTICR3_EXTI11_PI 0x8000U
    -
    11907/***************** Bit definition for SYSCFG_EXTICR4 register ***************/
    -
    11908#define SYSCFG_EXTICR4_EXTI12_Pos (0U)
    -
    11909#define SYSCFG_EXTICR4_EXTI12_Msk (0xFUL << SYSCFG_EXTICR4_EXTI12_Pos)
    -
    11910#define SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk
    -
    11911#define SYSCFG_EXTICR4_EXTI13_Pos (4U)
    -
    11912#define SYSCFG_EXTICR4_EXTI13_Msk (0xFUL << SYSCFG_EXTICR4_EXTI13_Pos)
    -
    11913#define SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk
    -
    11914#define SYSCFG_EXTICR4_EXTI14_Pos (8U)
    -
    11915#define SYSCFG_EXTICR4_EXTI14_Msk (0xFUL << SYSCFG_EXTICR4_EXTI14_Pos)
    -
    11916#define SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk
    -
    11917#define SYSCFG_EXTICR4_EXTI15_Pos (12U)
    -
    11918#define SYSCFG_EXTICR4_EXTI15_Msk (0xFUL << SYSCFG_EXTICR4_EXTI15_Pos)
    -
    11919#define SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk
    -
    11924#define SYSCFG_EXTICR4_EXTI12_PA 0x0000U
    -
    11925#define SYSCFG_EXTICR4_EXTI12_PB 0x0001U
    -
    11926#define SYSCFG_EXTICR4_EXTI12_PC 0x0002U
    -
    11927#define SYSCFG_EXTICR4_EXTI12_PD 0x0003U
    -
    11928#define SYSCFG_EXTICR4_EXTI12_PE 0x0004U
    -
    11929#define SYSCFG_EXTICR4_EXTI12_PF 0x0005U
    -
    11930#define SYSCFG_EXTICR4_EXTI12_PG 0x0006U
    -
    11931#define SYSCFG_EXTICR4_EXTI12_PH 0x0007U
    -
    11936#define SYSCFG_EXTICR4_EXTI13_PA 0x0000U
    -
    11937#define SYSCFG_EXTICR4_EXTI13_PB 0x0010U
    -
    11938#define SYSCFG_EXTICR4_EXTI13_PC 0x0020U
    -
    11939#define SYSCFG_EXTICR4_EXTI13_PD 0x0030U
    -
    11940#define SYSCFG_EXTICR4_EXTI13_PE 0x0040U
    -
    11941#define SYSCFG_EXTICR4_EXTI13_PF 0x0050U
    -
    11942#define SYSCFG_EXTICR4_EXTI13_PG 0x0060U
    -
    11943#define SYSCFG_EXTICR4_EXTI13_PH 0x0070U
    -
    11948#define SYSCFG_EXTICR4_EXTI14_PA 0x0000U
    -
    11949#define SYSCFG_EXTICR4_EXTI14_PB 0x0100U
    -
    11950#define SYSCFG_EXTICR4_EXTI14_PC 0x0200U
    -
    11951#define SYSCFG_EXTICR4_EXTI14_PD 0x0300U
    -
    11952#define SYSCFG_EXTICR4_EXTI14_PE 0x0400U
    -
    11953#define SYSCFG_EXTICR4_EXTI14_PF 0x0500U
    -
    11954#define SYSCFG_EXTICR4_EXTI14_PG 0x0600U
    -
    11955#define SYSCFG_EXTICR4_EXTI14_PH 0x0700U
    -
    11960#define SYSCFG_EXTICR4_EXTI15_PA 0x0000U
    -
    11961#define SYSCFG_EXTICR4_EXTI15_PB 0x1000U
    -
    11962#define SYSCFG_EXTICR4_EXTI15_PC 0x2000U
    -
    11963#define SYSCFG_EXTICR4_EXTI15_PD 0x3000U
    -
    11964#define SYSCFG_EXTICR4_EXTI15_PE 0x4000U
    -
    11965#define SYSCFG_EXTICR4_EXTI15_PF 0x5000U
    -
    11966#define SYSCFG_EXTICR4_EXTI15_PG 0x6000U
    -
    11967#define SYSCFG_EXTICR4_EXTI15_PH 0x7000U
    -
    11969/****************** Bit definition for SYSCFG_CMPCR register ****************/
    -
    11970#define SYSCFG_CMPCR_CMP_PD_Pos (0U)
    -
    11971#define SYSCFG_CMPCR_CMP_PD_Msk (0x1UL << SYSCFG_CMPCR_CMP_PD_Pos)
    -
    11972#define SYSCFG_CMPCR_CMP_PD SYSCFG_CMPCR_CMP_PD_Msk
    -
    11973#define SYSCFG_CMPCR_READY_Pos (8U)
    -
    11974#define SYSCFG_CMPCR_READY_Msk (0x1UL << SYSCFG_CMPCR_READY_Pos)
    -
    11975#define SYSCFG_CMPCR_READY SYSCFG_CMPCR_READY_Msk
    -
    11977/******************************************************************************/
    -
    11978/* */
    -
    11979/* TIM */
    -
    11980/* */
    -
    11981/******************************************************************************/
    -
    11982/******************* Bit definition for TIM_CR1 register ********************/
    -
    11983#define TIM_CR1_CEN_Pos (0U)
    -
    11984#define TIM_CR1_CEN_Msk (0x1UL << TIM_CR1_CEN_Pos)
    -
    11985#define TIM_CR1_CEN TIM_CR1_CEN_Msk
    -
    11986#define TIM_CR1_UDIS_Pos (1U)
    -
    11987#define TIM_CR1_UDIS_Msk (0x1UL << TIM_CR1_UDIS_Pos)
    -
    11988#define TIM_CR1_UDIS TIM_CR1_UDIS_Msk
    -
    11989#define TIM_CR1_URS_Pos (2U)
    -
    11990#define TIM_CR1_URS_Msk (0x1UL << TIM_CR1_URS_Pos)
    -
    11991#define TIM_CR1_URS TIM_CR1_URS_Msk
    -
    11992#define TIM_CR1_OPM_Pos (3U)
    -
    11993#define TIM_CR1_OPM_Msk (0x1UL << TIM_CR1_OPM_Pos)
    -
    11994#define TIM_CR1_OPM TIM_CR1_OPM_Msk
    -
    11995#define TIM_CR1_DIR_Pos (4U)
    -
    11996#define TIM_CR1_DIR_Msk (0x1UL << TIM_CR1_DIR_Pos)
    -
    11997#define TIM_CR1_DIR TIM_CR1_DIR_Msk
    -
    11999#define TIM_CR1_CMS_Pos (5U)
    -
    12000#define TIM_CR1_CMS_Msk (0x3UL << TIM_CR1_CMS_Pos)
    -
    12001#define TIM_CR1_CMS TIM_CR1_CMS_Msk
    -
    12002#define TIM_CR1_CMS_0 (0x1UL << TIM_CR1_CMS_Pos)
    -
    12003#define TIM_CR1_CMS_1 (0x2UL << TIM_CR1_CMS_Pos)
    -
    12005#define TIM_CR1_ARPE_Pos (7U)
    -
    12006#define TIM_CR1_ARPE_Msk (0x1UL << TIM_CR1_ARPE_Pos)
    -
    12007#define TIM_CR1_ARPE TIM_CR1_ARPE_Msk
    -
    12009#define TIM_CR1_CKD_Pos (8U)
    -
    12010#define TIM_CR1_CKD_Msk (0x3UL << TIM_CR1_CKD_Pos)
    -
    12011#define TIM_CR1_CKD TIM_CR1_CKD_Msk
    -
    12012#define TIM_CR1_CKD_0 (0x1UL << TIM_CR1_CKD_Pos)
    -
    12013#define TIM_CR1_CKD_1 (0x2UL << TIM_CR1_CKD_Pos)
    -
    12015/******************* Bit definition for TIM_CR2 register ********************/
    -
    12016#define TIM_CR2_CCPC_Pos (0U)
    -
    12017#define TIM_CR2_CCPC_Msk (0x1UL << TIM_CR2_CCPC_Pos)
    -
    12018#define TIM_CR2_CCPC TIM_CR2_CCPC_Msk
    -
    12019#define TIM_CR2_CCUS_Pos (2U)
    -
    12020#define TIM_CR2_CCUS_Msk (0x1UL << TIM_CR2_CCUS_Pos)
    -
    12021#define TIM_CR2_CCUS TIM_CR2_CCUS_Msk
    -
    12022#define TIM_CR2_CCDS_Pos (3U)
    -
    12023#define TIM_CR2_CCDS_Msk (0x1UL << TIM_CR2_CCDS_Pos)
    -
    12024#define TIM_CR2_CCDS TIM_CR2_CCDS_Msk
    -
    12026#define TIM_CR2_MMS_Pos (4U)
    -
    12027#define TIM_CR2_MMS_Msk (0x7UL << TIM_CR2_MMS_Pos)
    -
    12028#define TIM_CR2_MMS TIM_CR2_MMS_Msk
    -
    12029#define TIM_CR2_MMS_0 (0x1UL << TIM_CR2_MMS_Pos)
    -
    12030#define TIM_CR2_MMS_1 (0x2UL << TIM_CR2_MMS_Pos)
    -
    12031#define TIM_CR2_MMS_2 (0x4UL << TIM_CR2_MMS_Pos)
    -
    12033#define TIM_CR2_TI1S_Pos (7U)
    -
    12034#define TIM_CR2_TI1S_Msk (0x1UL << TIM_CR2_TI1S_Pos)
    -
    12035#define TIM_CR2_TI1S TIM_CR2_TI1S_Msk
    -
    12036#define TIM_CR2_OIS1_Pos (8U)
    -
    12037#define TIM_CR2_OIS1_Msk (0x1UL << TIM_CR2_OIS1_Pos)
    -
    12038#define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk
    -
    12039#define TIM_CR2_OIS1N_Pos (9U)
    -
    12040#define TIM_CR2_OIS1N_Msk (0x1UL << TIM_CR2_OIS1N_Pos)
    -
    12041#define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk
    -
    12042#define TIM_CR2_OIS2_Pos (10U)
    -
    12043#define TIM_CR2_OIS2_Msk (0x1UL << TIM_CR2_OIS2_Pos)
    -
    12044#define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk
    -
    12045#define TIM_CR2_OIS2N_Pos (11U)
    -
    12046#define TIM_CR2_OIS2N_Msk (0x1UL << TIM_CR2_OIS2N_Pos)
    -
    12047#define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk
    -
    12048#define TIM_CR2_OIS3_Pos (12U)
    -
    12049#define TIM_CR2_OIS3_Msk (0x1UL << TIM_CR2_OIS3_Pos)
    -
    12050#define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk
    -
    12051#define TIM_CR2_OIS3N_Pos (13U)
    -
    12052#define TIM_CR2_OIS3N_Msk (0x1UL << TIM_CR2_OIS3N_Pos)
    -
    12053#define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk
    -
    12054#define TIM_CR2_OIS4_Pos (14U)
    -
    12055#define TIM_CR2_OIS4_Msk (0x1UL << TIM_CR2_OIS4_Pos)
    -
    12056#define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk
    -
    12058/******************* Bit definition for TIM_SMCR register *******************/
    -
    12059#define TIM_SMCR_SMS_Pos (0U)
    -
    12060#define TIM_SMCR_SMS_Msk (0x7UL << TIM_SMCR_SMS_Pos)
    -
    12061#define TIM_SMCR_SMS TIM_SMCR_SMS_Msk
    -
    12062#define TIM_SMCR_SMS_0 (0x1UL << TIM_SMCR_SMS_Pos)
    -
    12063#define TIM_SMCR_SMS_1 (0x2UL << TIM_SMCR_SMS_Pos)
    -
    12064#define TIM_SMCR_SMS_2 (0x4UL << TIM_SMCR_SMS_Pos)
    -
    12066#define TIM_SMCR_TS_Pos (4U)
    -
    12067#define TIM_SMCR_TS_Msk (0x7UL << TIM_SMCR_TS_Pos)
    -
    12068#define TIM_SMCR_TS TIM_SMCR_TS_Msk
    -
    12069#define TIM_SMCR_TS_0 (0x1UL << TIM_SMCR_TS_Pos)
    -
    12070#define TIM_SMCR_TS_1 (0x2UL << TIM_SMCR_TS_Pos)
    -
    12071#define TIM_SMCR_TS_2 (0x4UL << TIM_SMCR_TS_Pos)
    -
    12073#define TIM_SMCR_MSM_Pos (7U)
    -
    12074#define TIM_SMCR_MSM_Msk (0x1UL << TIM_SMCR_MSM_Pos)
    -
    12075#define TIM_SMCR_MSM TIM_SMCR_MSM_Msk
    -
    12077#define TIM_SMCR_ETF_Pos (8U)
    -
    12078#define TIM_SMCR_ETF_Msk (0xFUL << TIM_SMCR_ETF_Pos)
    -
    12079#define TIM_SMCR_ETF TIM_SMCR_ETF_Msk
    -
    12080#define TIM_SMCR_ETF_0 (0x1UL << TIM_SMCR_ETF_Pos)
    -
    12081#define TIM_SMCR_ETF_1 (0x2UL << TIM_SMCR_ETF_Pos)
    -
    12082#define TIM_SMCR_ETF_2 (0x4UL << TIM_SMCR_ETF_Pos)
    -
    12083#define TIM_SMCR_ETF_3 (0x8UL << TIM_SMCR_ETF_Pos)
    -
    12085#define TIM_SMCR_ETPS_Pos (12U)
    -
    12086#define TIM_SMCR_ETPS_Msk (0x3UL << TIM_SMCR_ETPS_Pos)
    -
    12087#define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk
    -
    12088#define TIM_SMCR_ETPS_0 (0x1UL << TIM_SMCR_ETPS_Pos)
    -
    12089#define TIM_SMCR_ETPS_1 (0x2UL << TIM_SMCR_ETPS_Pos)
    -
    12091#define TIM_SMCR_ECE_Pos (14U)
    -
    12092#define TIM_SMCR_ECE_Msk (0x1UL << TIM_SMCR_ECE_Pos)
    -
    12093#define TIM_SMCR_ECE TIM_SMCR_ECE_Msk
    -
    12094#define TIM_SMCR_ETP_Pos (15U)
    -
    12095#define TIM_SMCR_ETP_Msk (0x1UL << TIM_SMCR_ETP_Pos)
    -
    12096#define TIM_SMCR_ETP TIM_SMCR_ETP_Msk
    -
    12098/******************* Bit definition for TIM_DIER register *******************/
    -
    12099#define TIM_DIER_UIE_Pos (0U)
    -
    12100#define TIM_DIER_UIE_Msk (0x1UL << TIM_DIER_UIE_Pos)
    -
    12101#define TIM_DIER_UIE TIM_DIER_UIE_Msk
    -
    12102#define TIM_DIER_CC1IE_Pos (1U)
    -
    12103#define TIM_DIER_CC1IE_Msk (0x1UL << TIM_DIER_CC1IE_Pos)
    -
    12104#define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk
    -
    12105#define TIM_DIER_CC2IE_Pos (2U)
    -
    12106#define TIM_DIER_CC2IE_Msk (0x1UL << TIM_DIER_CC2IE_Pos)
    -
    12107#define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk
    -
    12108#define TIM_DIER_CC3IE_Pos (3U)
    -
    12109#define TIM_DIER_CC3IE_Msk (0x1UL << TIM_DIER_CC3IE_Pos)
    -
    12110#define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk
    -
    12111#define TIM_DIER_CC4IE_Pos (4U)
    -
    12112#define TIM_DIER_CC4IE_Msk (0x1UL << TIM_DIER_CC4IE_Pos)
    -
    12113#define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk
    -
    12114#define TIM_DIER_COMIE_Pos (5U)
    -
    12115#define TIM_DIER_COMIE_Msk (0x1UL << TIM_DIER_COMIE_Pos)
    -
    12116#define TIM_DIER_COMIE TIM_DIER_COMIE_Msk
    -
    12117#define TIM_DIER_TIE_Pos (6U)
    -
    12118#define TIM_DIER_TIE_Msk (0x1UL << TIM_DIER_TIE_Pos)
    -
    12119#define TIM_DIER_TIE TIM_DIER_TIE_Msk
    -
    12120#define TIM_DIER_BIE_Pos (7U)
    -
    12121#define TIM_DIER_BIE_Msk (0x1UL << TIM_DIER_BIE_Pos)
    -
    12122#define TIM_DIER_BIE TIM_DIER_BIE_Msk
    -
    12123#define TIM_DIER_UDE_Pos (8U)
    -
    12124#define TIM_DIER_UDE_Msk (0x1UL << TIM_DIER_UDE_Pos)
    -
    12125#define TIM_DIER_UDE TIM_DIER_UDE_Msk
    -
    12126#define TIM_DIER_CC1DE_Pos (9U)
    -
    12127#define TIM_DIER_CC1DE_Msk (0x1UL << TIM_DIER_CC1DE_Pos)
    -
    12128#define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk
    -
    12129#define TIM_DIER_CC2DE_Pos (10U)
    -
    12130#define TIM_DIER_CC2DE_Msk (0x1UL << TIM_DIER_CC2DE_Pos)
    -
    12131#define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk
    -
    12132#define TIM_DIER_CC3DE_Pos (11U)
    -
    12133#define TIM_DIER_CC3DE_Msk (0x1UL << TIM_DIER_CC3DE_Pos)
    -
    12134#define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk
    -
    12135#define TIM_DIER_CC4DE_Pos (12U)
    -
    12136#define TIM_DIER_CC4DE_Msk (0x1UL << TIM_DIER_CC4DE_Pos)
    -
    12137#define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk
    -
    12138#define TIM_DIER_COMDE_Pos (13U)
    -
    12139#define TIM_DIER_COMDE_Msk (0x1UL << TIM_DIER_COMDE_Pos)
    -
    12140#define TIM_DIER_COMDE TIM_DIER_COMDE_Msk
    -
    12141#define TIM_DIER_TDE_Pos (14U)
    -
    12142#define TIM_DIER_TDE_Msk (0x1UL << TIM_DIER_TDE_Pos)
    -
    12143#define TIM_DIER_TDE TIM_DIER_TDE_Msk
    -
    12145/******************** Bit definition for TIM_SR register ********************/
    -
    12146#define TIM_SR_UIF_Pos (0U)
    -
    12147#define TIM_SR_UIF_Msk (0x1UL << TIM_SR_UIF_Pos)
    -
    12148#define TIM_SR_UIF TIM_SR_UIF_Msk
    -
    12149#define TIM_SR_CC1IF_Pos (1U)
    -
    12150#define TIM_SR_CC1IF_Msk (0x1UL << TIM_SR_CC1IF_Pos)
    -
    12151#define TIM_SR_CC1IF TIM_SR_CC1IF_Msk
    -
    12152#define TIM_SR_CC2IF_Pos (2U)
    -
    12153#define TIM_SR_CC2IF_Msk (0x1UL << TIM_SR_CC2IF_Pos)
    -
    12154#define TIM_SR_CC2IF TIM_SR_CC2IF_Msk
    -
    12155#define TIM_SR_CC3IF_Pos (3U)
    -
    12156#define TIM_SR_CC3IF_Msk (0x1UL << TIM_SR_CC3IF_Pos)
    -
    12157#define TIM_SR_CC3IF TIM_SR_CC3IF_Msk
    -
    12158#define TIM_SR_CC4IF_Pos (4U)
    -
    12159#define TIM_SR_CC4IF_Msk (0x1UL << TIM_SR_CC4IF_Pos)
    -
    12160#define TIM_SR_CC4IF TIM_SR_CC4IF_Msk
    -
    12161#define TIM_SR_COMIF_Pos (5U)
    -
    12162#define TIM_SR_COMIF_Msk (0x1UL << TIM_SR_COMIF_Pos)
    -
    12163#define TIM_SR_COMIF TIM_SR_COMIF_Msk
    -
    12164#define TIM_SR_TIF_Pos (6U)
    -
    12165#define TIM_SR_TIF_Msk (0x1UL << TIM_SR_TIF_Pos)
    -
    12166#define TIM_SR_TIF TIM_SR_TIF_Msk
    -
    12167#define TIM_SR_BIF_Pos (7U)
    -
    12168#define TIM_SR_BIF_Msk (0x1UL << TIM_SR_BIF_Pos)
    -
    12169#define TIM_SR_BIF TIM_SR_BIF_Msk
    -
    12170#define TIM_SR_CC1OF_Pos (9U)
    -
    12171#define TIM_SR_CC1OF_Msk (0x1UL << TIM_SR_CC1OF_Pos)
    -
    12172#define TIM_SR_CC1OF TIM_SR_CC1OF_Msk
    -
    12173#define TIM_SR_CC2OF_Pos (10U)
    -
    12174#define TIM_SR_CC2OF_Msk (0x1UL << TIM_SR_CC2OF_Pos)
    -
    12175#define TIM_SR_CC2OF TIM_SR_CC2OF_Msk
    -
    12176#define TIM_SR_CC3OF_Pos (11U)
    -
    12177#define TIM_SR_CC3OF_Msk (0x1UL << TIM_SR_CC3OF_Pos)
    -
    12178#define TIM_SR_CC3OF TIM_SR_CC3OF_Msk
    -
    12179#define TIM_SR_CC4OF_Pos (12U)
    -
    12180#define TIM_SR_CC4OF_Msk (0x1UL << TIM_SR_CC4OF_Pos)
    -
    12181#define TIM_SR_CC4OF TIM_SR_CC4OF_Msk
    -
    12183/******************* Bit definition for TIM_EGR register ********************/
    -
    12184#define TIM_EGR_UG_Pos (0U)
    -
    12185#define TIM_EGR_UG_Msk (0x1UL << TIM_EGR_UG_Pos)
    -
    12186#define TIM_EGR_UG TIM_EGR_UG_Msk
    -
    12187#define TIM_EGR_CC1G_Pos (1U)
    -
    12188#define TIM_EGR_CC1G_Msk (0x1UL << TIM_EGR_CC1G_Pos)
    -
    12189#define TIM_EGR_CC1G TIM_EGR_CC1G_Msk
    -
    12190#define TIM_EGR_CC2G_Pos (2U)
    -
    12191#define TIM_EGR_CC2G_Msk (0x1UL << TIM_EGR_CC2G_Pos)
    -
    12192#define TIM_EGR_CC2G TIM_EGR_CC2G_Msk
    -
    12193#define TIM_EGR_CC3G_Pos (3U)
    -
    12194#define TIM_EGR_CC3G_Msk (0x1UL << TIM_EGR_CC3G_Pos)
    -
    12195#define TIM_EGR_CC3G TIM_EGR_CC3G_Msk
    -
    12196#define TIM_EGR_CC4G_Pos (4U)
    -
    12197#define TIM_EGR_CC4G_Msk (0x1UL << TIM_EGR_CC4G_Pos)
    -
    12198#define TIM_EGR_CC4G TIM_EGR_CC4G_Msk
    -
    12199#define TIM_EGR_COMG_Pos (5U)
    -
    12200#define TIM_EGR_COMG_Msk (0x1UL << TIM_EGR_COMG_Pos)
    -
    12201#define TIM_EGR_COMG TIM_EGR_COMG_Msk
    -
    12202#define TIM_EGR_TG_Pos (6U)
    -
    12203#define TIM_EGR_TG_Msk (0x1UL << TIM_EGR_TG_Pos)
    -
    12204#define TIM_EGR_TG TIM_EGR_TG_Msk
    -
    12205#define TIM_EGR_BG_Pos (7U)
    -
    12206#define TIM_EGR_BG_Msk (0x1UL << TIM_EGR_BG_Pos)
    -
    12207#define TIM_EGR_BG TIM_EGR_BG_Msk
    -
    12209/****************** Bit definition for TIM_CCMR1 register *******************/
    -
    12210#define TIM_CCMR1_CC1S_Pos (0U)
    -
    12211#define TIM_CCMR1_CC1S_Msk (0x3UL << TIM_CCMR1_CC1S_Pos)
    -
    12212#define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk
    -
    12213#define TIM_CCMR1_CC1S_0 (0x1UL << TIM_CCMR1_CC1S_Pos)
    -
    12214#define TIM_CCMR1_CC1S_1 (0x2UL << TIM_CCMR1_CC1S_Pos)
    -
    12216#define TIM_CCMR1_OC1FE_Pos (2U)
    -
    12217#define TIM_CCMR1_OC1FE_Msk (0x1UL << TIM_CCMR1_OC1FE_Pos)
    -
    12218#define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk
    -
    12219#define TIM_CCMR1_OC1PE_Pos (3U)
    -
    12220#define TIM_CCMR1_OC1PE_Msk (0x1UL << TIM_CCMR1_OC1PE_Pos)
    -
    12221#define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk
    -
    12223#define TIM_CCMR1_OC1M_Pos (4U)
    -
    12224#define TIM_CCMR1_OC1M_Msk (0x7UL << TIM_CCMR1_OC1M_Pos)
    -
    12225#define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk
    -
    12226#define TIM_CCMR1_OC1M_0 (0x1UL << TIM_CCMR1_OC1M_Pos)
    -
    12227#define TIM_CCMR1_OC1M_1 (0x2UL << TIM_CCMR1_OC1M_Pos)
    -
    12228#define TIM_CCMR1_OC1M_2 (0x4UL << TIM_CCMR1_OC1M_Pos)
    -
    12230#define TIM_CCMR1_OC1CE_Pos (7U)
    -
    12231#define TIM_CCMR1_OC1CE_Msk (0x1UL << TIM_CCMR1_OC1CE_Pos)
    -
    12232#define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk
    -
    12234#define TIM_CCMR1_CC2S_Pos (8U)
    -
    12235#define TIM_CCMR1_CC2S_Msk (0x3UL << TIM_CCMR1_CC2S_Pos)
    -
    12236#define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk
    -
    12237#define TIM_CCMR1_CC2S_0 (0x1UL << TIM_CCMR1_CC2S_Pos)
    -
    12238#define TIM_CCMR1_CC2S_1 (0x2UL << TIM_CCMR1_CC2S_Pos)
    -
    12240#define TIM_CCMR1_OC2FE_Pos (10U)
    -
    12241#define TIM_CCMR1_OC2FE_Msk (0x1UL << TIM_CCMR1_OC2FE_Pos)
    -
    12242#define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk
    -
    12243#define TIM_CCMR1_OC2PE_Pos (11U)
    -
    12244#define TIM_CCMR1_OC2PE_Msk (0x1UL << TIM_CCMR1_OC2PE_Pos)
    -
    12245#define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk
    -
    12247#define TIM_CCMR1_OC2M_Pos (12U)
    -
    12248#define TIM_CCMR1_OC2M_Msk (0x7UL << TIM_CCMR1_OC2M_Pos)
    -
    12249#define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk
    -
    12250#define TIM_CCMR1_OC2M_0 (0x1UL << TIM_CCMR1_OC2M_Pos)
    -
    12251#define TIM_CCMR1_OC2M_1 (0x2UL << TIM_CCMR1_OC2M_Pos)
    -
    12252#define TIM_CCMR1_OC2M_2 (0x4UL << TIM_CCMR1_OC2M_Pos)
    -
    12254#define TIM_CCMR1_OC2CE_Pos (15U)
    -
    12255#define TIM_CCMR1_OC2CE_Msk (0x1UL << TIM_CCMR1_OC2CE_Pos)
    -
    12256#define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk
    -
    12258/*----------------------------------------------------------------------------*/
    -
    12259
    -
    12260#define TIM_CCMR1_IC1PSC_Pos (2U)
    -
    12261#define TIM_CCMR1_IC1PSC_Msk (0x3UL << TIM_CCMR1_IC1PSC_Pos)
    -
    12262#define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk
    -
    12263#define TIM_CCMR1_IC1PSC_0 (0x1UL << TIM_CCMR1_IC1PSC_Pos)
    -
    12264#define TIM_CCMR1_IC1PSC_1 (0x2UL << TIM_CCMR1_IC1PSC_Pos)
    -
    12266#define TIM_CCMR1_IC1F_Pos (4U)
    -
    12267#define TIM_CCMR1_IC1F_Msk (0xFUL << TIM_CCMR1_IC1F_Pos)
    -
    12268#define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk
    -
    12269#define TIM_CCMR1_IC1F_0 (0x1UL << TIM_CCMR1_IC1F_Pos)
    -
    12270#define TIM_CCMR1_IC1F_1 (0x2UL << TIM_CCMR1_IC1F_Pos)
    -
    12271#define TIM_CCMR1_IC1F_2 (0x4UL << TIM_CCMR1_IC1F_Pos)
    -
    12272#define TIM_CCMR1_IC1F_3 (0x8UL << TIM_CCMR1_IC1F_Pos)
    -
    12274#define TIM_CCMR1_IC2PSC_Pos (10U)
    -
    12275#define TIM_CCMR1_IC2PSC_Msk (0x3UL << TIM_CCMR1_IC2PSC_Pos)
    -
    12276#define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk
    -
    12277#define TIM_CCMR1_IC2PSC_0 (0x1UL << TIM_CCMR1_IC2PSC_Pos)
    -
    12278#define TIM_CCMR1_IC2PSC_1 (0x2UL << TIM_CCMR1_IC2PSC_Pos)
    -
    12280#define TIM_CCMR1_IC2F_Pos (12U)
    -
    12281#define TIM_CCMR1_IC2F_Msk (0xFUL << TIM_CCMR1_IC2F_Pos)
    -
    12282#define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk
    -
    12283#define TIM_CCMR1_IC2F_0 (0x1UL << TIM_CCMR1_IC2F_Pos)
    -
    12284#define TIM_CCMR1_IC2F_1 (0x2UL << TIM_CCMR1_IC2F_Pos)
    -
    12285#define TIM_CCMR1_IC2F_2 (0x4UL << TIM_CCMR1_IC2F_Pos)
    -
    12286#define TIM_CCMR1_IC2F_3 (0x8UL << TIM_CCMR1_IC2F_Pos)
    -
    12288/****************** Bit definition for TIM_CCMR2 register *******************/
    -
    12289#define TIM_CCMR2_CC3S_Pos (0U)
    -
    12290#define TIM_CCMR2_CC3S_Msk (0x3UL << TIM_CCMR2_CC3S_Pos)
    -
    12291#define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk
    -
    12292#define TIM_CCMR2_CC3S_0 (0x1UL << TIM_CCMR2_CC3S_Pos)
    -
    12293#define TIM_CCMR2_CC3S_1 (0x2UL << TIM_CCMR2_CC3S_Pos)
    -
    12295#define TIM_CCMR2_OC3FE_Pos (2U)
    -
    12296#define TIM_CCMR2_OC3FE_Msk (0x1UL << TIM_CCMR2_OC3FE_Pos)
    -
    12297#define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk
    -
    12298#define TIM_CCMR2_OC3PE_Pos (3U)
    -
    12299#define TIM_CCMR2_OC3PE_Msk (0x1UL << TIM_CCMR2_OC3PE_Pos)
    -
    12300#define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk
    -
    12302#define TIM_CCMR2_OC3M_Pos (4U)
    -
    12303#define TIM_CCMR2_OC3M_Msk (0x7UL << TIM_CCMR2_OC3M_Pos)
    -
    12304#define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk
    -
    12305#define TIM_CCMR2_OC3M_0 (0x1UL << TIM_CCMR2_OC3M_Pos)
    -
    12306#define TIM_CCMR2_OC3M_1 (0x2UL << TIM_CCMR2_OC3M_Pos)
    -
    12307#define TIM_CCMR2_OC3M_2 (0x4UL << TIM_CCMR2_OC3M_Pos)
    -
    12309#define TIM_CCMR2_OC3CE_Pos (7U)
    -
    12310#define TIM_CCMR2_OC3CE_Msk (0x1UL << TIM_CCMR2_OC3CE_Pos)
    -
    12311#define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk
    -
    12313#define TIM_CCMR2_CC4S_Pos (8U)
    -
    12314#define TIM_CCMR2_CC4S_Msk (0x3UL << TIM_CCMR2_CC4S_Pos)
    -
    12315#define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk
    -
    12316#define TIM_CCMR2_CC4S_0 (0x1UL << TIM_CCMR2_CC4S_Pos)
    -
    12317#define TIM_CCMR2_CC4S_1 (0x2UL << TIM_CCMR2_CC4S_Pos)
    -
    12319#define TIM_CCMR2_OC4FE_Pos (10U)
    -
    12320#define TIM_CCMR2_OC4FE_Msk (0x1UL << TIM_CCMR2_OC4FE_Pos)
    -
    12321#define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk
    -
    12322#define TIM_CCMR2_OC4PE_Pos (11U)
    -
    12323#define TIM_CCMR2_OC4PE_Msk (0x1UL << TIM_CCMR2_OC4PE_Pos)
    -
    12324#define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk
    -
    12326#define TIM_CCMR2_OC4M_Pos (12U)
    -
    12327#define TIM_CCMR2_OC4M_Msk (0x7UL << TIM_CCMR2_OC4M_Pos)
    -
    12328#define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk
    -
    12329#define TIM_CCMR2_OC4M_0 (0x1UL << TIM_CCMR2_OC4M_Pos)
    -
    12330#define TIM_CCMR2_OC4M_1 (0x2UL << TIM_CCMR2_OC4M_Pos)
    -
    12331#define TIM_CCMR2_OC4M_2 (0x4UL << TIM_CCMR2_OC4M_Pos)
    -
    12333#define TIM_CCMR2_OC4CE_Pos (15U)
    -
    12334#define TIM_CCMR2_OC4CE_Msk (0x1UL << TIM_CCMR2_OC4CE_Pos)
    -
    12335#define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk
    -
    12337/*----------------------------------------------------------------------------*/
    -
    12338
    -
    12339#define TIM_CCMR2_IC3PSC_Pos (2U)
    -
    12340#define TIM_CCMR2_IC3PSC_Msk (0x3UL << TIM_CCMR2_IC3PSC_Pos)
    -
    12341#define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk
    -
    12342#define TIM_CCMR2_IC3PSC_0 (0x1UL << TIM_CCMR2_IC3PSC_Pos)
    -
    12343#define TIM_CCMR2_IC3PSC_1 (0x2UL << TIM_CCMR2_IC3PSC_Pos)
    -
    12345#define TIM_CCMR2_IC3F_Pos (4U)
    -
    12346#define TIM_CCMR2_IC3F_Msk (0xFUL << TIM_CCMR2_IC3F_Pos)
    -
    12347#define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk
    -
    12348#define TIM_CCMR2_IC3F_0 (0x1UL << TIM_CCMR2_IC3F_Pos)
    -
    12349#define TIM_CCMR2_IC3F_1 (0x2UL << TIM_CCMR2_IC3F_Pos)
    -
    12350#define TIM_CCMR2_IC3F_2 (0x4UL << TIM_CCMR2_IC3F_Pos)
    -
    12351#define TIM_CCMR2_IC3F_3 (0x8UL << TIM_CCMR2_IC3F_Pos)
    -
    12353#define TIM_CCMR2_IC4PSC_Pos (10U)
    -
    12354#define TIM_CCMR2_IC4PSC_Msk (0x3UL << TIM_CCMR2_IC4PSC_Pos)
    -
    12355#define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk
    -
    12356#define TIM_CCMR2_IC4PSC_0 (0x1UL << TIM_CCMR2_IC4PSC_Pos)
    -
    12357#define TIM_CCMR2_IC4PSC_1 (0x2UL << TIM_CCMR2_IC4PSC_Pos)
    -
    12359#define TIM_CCMR2_IC4F_Pos (12U)
    -
    12360#define TIM_CCMR2_IC4F_Msk (0xFUL << TIM_CCMR2_IC4F_Pos)
    -
    12361#define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk
    -
    12362#define TIM_CCMR2_IC4F_0 (0x1UL << TIM_CCMR2_IC4F_Pos)
    -
    12363#define TIM_CCMR2_IC4F_1 (0x2UL << TIM_CCMR2_IC4F_Pos)
    -
    12364#define TIM_CCMR2_IC4F_2 (0x4UL << TIM_CCMR2_IC4F_Pos)
    -
    12365#define TIM_CCMR2_IC4F_3 (0x8UL << TIM_CCMR2_IC4F_Pos)
    -
    12367/******************* Bit definition for TIM_CCER register *******************/
    -
    12368#define TIM_CCER_CC1E_Pos (0U)
    -
    12369#define TIM_CCER_CC1E_Msk (0x1UL << TIM_CCER_CC1E_Pos)
    -
    12370#define TIM_CCER_CC1E TIM_CCER_CC1E_Msk
    -
    12371#define TIM_CCER_CC1P_Pos (1U)
    -
    12372#define TIM_CCER_CC1P_Msk (0x1UL << TIM_CCER_CC1P_Pos)
    -
    12373#define TIM_CCER_CC1P TIM_CCER_CC1P_Msk
    -
    12374#define TIM_CCER_CC1NE_Pos (2U)
    -
    12375#define TIM_CCER_CC1NE_Msk (0x1UL << TIM_CCER_CC1NE_Pos)
    -
    12376#define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk
    -
    12377#define TIM_CCER_CC1NP_Pos (3U)
    -
    12378#define TIM_CCER_CC1NP_Msk (0x1UL << TIM_CCER_CC1NP_Pos)
    -
    12379#define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk
    -
    12380#define TIM_CCER_CC2E_Pos (4U)
    -
    12381#define TIM_CCER_CC2E_Msk (0x1UL << TIM_CCER_CC2E_Pos)
    -
    12382#define TIM_CCER_CC2E TIM_CCER_CC2E_Msk
    -
    12383#define TIM_CCER_CC2P_Pos (5U)
    -
    12384#define TIM_CCER_CC2P_Msk (0x1UL << TIM_CCER_CC2P_Pos)
    -
    12385#define TIM_CCER_CC2P TIM_CCER_CC2P_Msk
    -
    12386#define TIM_CCER_CC2NE_Pos (6U)
    -
    12387#define TIM_CCER_CC2NE_Msk (0x1UL << TIM_CCER_CC2NE_Pos)
    -
    12388#define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk
    -
    12389#define TIM_CCER_CC2NP_Pos (7U)
    -
    12390#define TIM_CCER_CC2NP_Msk (0x1UL << TIM_CCER_CC2NP_Pos)
    -
    12391#define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk
    -
    12392#define TIM_CCER_CC3E_Pos (8U)
    -
    12393#define TIM_CCER_CC3E_Msk (0x1UL << TIM_CCER_CC3E_Pos)
    -
    12394#define TIM_CCER_CC3E TIM_CCER_CC3E_Msk
    -
    12395#define TIM_CCER_CC3P_Pos (9U)
    -
    12396#define TIM_CCER_CC3P_Msk (0x1UL << TIM_CCER_CC3P_Pos)
    -
    12397#define TIM_CCER_CC3P TIM_CCER_CC3P_Msk
    -
    12398#define TIM_CCER_CC3NE_Pos (10U)
    -
    12399#define TIM_CCER_CC3NE_Msk (0x1UL << TIM_CCER_CC3NE_Pos)
    -
    12400#define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk
    -
    12401#define TIM_CCER_CC3NP_Pos (11U)
    -
    12402#define TIM_CCER_CC3NP_Msk (0x1UL << TIM_CCER_CC3NP_Pos)
    -
    12403#define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk
    -
    12404#define TIM_CCER_CC4E_Pos (12U)
    -
    12405#define TIM_CCER_CC4E_Msk (0x1UL << TIM_CCER_CC4E_Pos)
    -
    12406#define TIM_CCER_CC4E TIM_CCER_CC4E_Msk
    -
    12407#define TIM_CCER_CC4P_Pos (13U)
    -
    12408#define TIM_CCER_CC4P_Msk (0x1UL << TIM_CCER_CC4P_Pos)
    -
    12409#define TIM_CCER_CC4P TIM_CCER_CC4P_Msk
    -
    12410#define TIM_CCER_CC4NP_Pos (15U)
    -
    12411#define TIM_CCER_CC4NP_Msk (0x1UL << TIM_CCER_CC4NP_Pos)
    -
    12412#define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk
    -
    12414/******************* Bit definition for TIM_CNT register ********************/
    -
    12415#define TIM_CNT_CNT_Pos (0U)
    -
    12416#define TIM_CNT_CNT_Msk (0xFFFFFFFFUL << TIM_CNT_CNT_Pos)
    -
    12417#define TIM_CNT_CNT TIM_CNT_CNT_Msk
    -
    12419/******************* Bit definition for TIM_PSC register ********************/
    -
    12420#define TIM_PSC_PSC_Pos (0U)
    -
    12421#define TIM_PSC_PSC_Msk (0xFFFFUL << TIM_PSC_PSC_Pos)
    -
    12422#define TIM_PSC_PSC TIM_PSC_PSC_Msk
    -
    12424/******************* Bit definition for TIM_ARR register ********************/
    -
    12425#define TIM_ARR_ARR_Pos (0U)
    -
    12426#define TIM_ARR_ARR_Msk (0xFFFFFFFFUL << TIM_ARR_ARR_Pos)
    -
    12427#define TIM_ARR_ARR TIM_ARR_ARR_Msk
    -
    12429/******************* Bit definition for TIM_RCR register ********************/
    -
    12430#define TIM_RCR_REP_Pos (0U)
    -
    12431#define TIM_RCR_REP_Msk (0xFFUL << TIM_RCR_REP_Pos)
    -
    12432#define TIM_RCR_REP TIM_RCR_REP_Msk
    -
    12434/******************* Bit definition for TIM_CCR1 register *******************/
    -
    12435#define TIM_CCR1_CCR1_Pos (0U)
    -
    12436#define TIM_CCR1_CCR1_Msk (0xFFFFUL << TIM_CCR1_CCR1_Pos)
    -
    12437#define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk
    -
    12439/******************* Bit definition for TIM_CCR2 register *******************/
    -
    12440#define TIM_CCR2_CCR2_Pos (0U)
    -
    12441#define TIM_CCR2_CCR2_Msk (0xFFFFUL << TIM_CCR2_CCR2_Pos)
    -
    12442#define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk
    -
    12444/******************* Bit definition for TIM_CCR3 register *******************/
    -
    12445#define TIM_CCR3_CCR3_Pos (0U)
    -
    12446#define TIM_CCR3_CCR3_Msk (0xFFFFUL << TIM_CCR3_CCR3_Pos)
    -
    12447#define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk
    -
    12449/******************* Bit definition for TIM_CCR4 register *******************/
    -
    12450#define TIM_CCR4_CCR4_Pos (0U)
    -
    12451#define TIM_CCR4_CCR4_Msk (0xFFFFUL << TIM_CCR4_CCR4_Pos)
    -
    12452#define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk
    -
    12454/******************* Bit definition for TIM_BDTR register *******************/
    -
    12455#define TIM_BDTR_DTG_Pos (0U)
    -
    12456#define TIM_BDTR_DTG_Msk (0xFFUL << TIM_BDTR_DTG_Pos)
    -
    12457#define TIM_BDTR_DTG TIM_BDTR_DTG_Msk
    -
    12458#define TIM_BDTR_DTG_0 (0x01UL << TIM_BDTR_DTG_Pos)
    -
    12459#define TIM_BDTR_DTG_1 (0x02UL << TIM_BDTR_DTG_Pos)
    -
    12460#define TIM_BDTR_DTG_2 (0x04UL << TIM_BDTR_DTG_Pos)
    -
    12461#define TIM_BDTR_DTG_3 (0x08UL << TIM_BDTR_DTG_Pos)
    -
    12462#define TIM_BDTR_DTG_4 (0x10UL << TIM_BDTR_DTG_Pos)
    -
    12463#define TIM_BDTR_DTG_5 (0x20UL << TIM_BDTR_DTG_Pos)
    -
    12464#define TIM_BDTR_DTG_6 (0x40UL << TIM_BDTR_DTG_Pos)
    -
    12465#define TIM_BDTR_DTG_7 (0x80UL << TIM_BDTR_DTG_Pos)
    -
    12467#define TIM_BDTR_LOCK_Pos (8U)
    -
    12468#define TIM_BDTR_LOCK_Msk (0x3UL << TIM_BDTR_LOCK_Pos)
    -
    12469#define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk
    -
    12470#define TIM_BDTR_LOCK_0 (0x1UL << TIM_BDTR_LOCK_Pos)
    -
    12471#define TIM_BDTR_LOCK_1 (0x2UL << TIM_BDTR_LOCK_Pos)
    -
    12473#define TIM_BDTR_OSSI_Pos (10U)
    -
    12474#define TIM_BDTR_OSSI_Msk (0x1UL << TIM_BDTR_OSSI_Pos)
    -
    12475#define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk
    -
    12476#define TIM_BDTR_OSSR_Pos (11U)
    -
    12477#define TIM_BDTR_OSSR_Msk (0x1UL << TIM_BDTR_OSSR_Pos)
    -
    12478#define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk
    -
    12479#define TIM_BDTR_BKE_Pos (12U)
    -
    12480#define TIM_BDTR_BKE_Msk (0x1UL << TIM_BDTR_BKE_Pos)
    -
    12481#define TIM_BDTR_BKE TIM_BDTR_BKE_Msk
    -
    12482#define TIM_BDTR_BKP_Pos (13U)
    -
    12483#define TIM_BDTR_BKP_Msk (0x1UL << TIM_BDTR_BKP_Pos)
    -
    12484#define TIM_BDTR_BKP TIM_BDTR_BKP_Msk
    -
    12485#define TIM_BDTR_AOE_Pos (14U)
    -
    12486#define TIM_BDTR_AOE_Msk (0x1UL << TIM_BDTR_AOE_Pos)
    -
    12487#define TIM_BDTR_AOE TIM_BDTR_AOE_Msk
    -
    12488#define TIM_BDTR_MOE_Pos (15U)
    -
    12489#define TIM_BDTR_MOE_Msk (0x1UL << TIM_BDTR_MOE_Pos)
    -
    12490#define TIM_BDTR_MOE TIM_BDTR_MOE_Msk
    -
    12492/******************* Bit definition for TIM_DCR register ********************/
    -
    12493#define TIM_DCR_DBA_Pos (0U)
    -
    12494#define TIM_DCR_DBA_Msk (0x1FUL << TIM_DCR_DBA_Pos)
    -
    12495#define TIM_DCR_DBA TIM_DCR_DBA_Msk
    -
    12496#define TIM_DCR_DBA_0 (0x01UL << TIM_DCR_DBA_Pos)
    -
    12497#define TIM_DCR_DBA_1 (0x02UL << TIM_DCR_DBA_Pos)
    -
    12498#define TIM_DCR_DBA_2 (0x04UL << TIM_DCR_DBA_Pos)
    -
    12499#define TIM_DCR_DBA_3 (0x08UL << TIM_DCR_DBA_Pos)
    -
    12500#define TIM_DCR_DBA_4 (0x10UL << TIM_DCR_DBA_Pos)
    -
    12502#define TIM_DCR_DBL_Pos (8U)
    -
    12503#define TIM_DCR_DBL_Msk (0x1FUL << TIM_DCR_DBL_Pos)
    -
    12504#define TIM_DCR_DBL TIM_DCR_DBL_Msk
    -
    12505#define TIM_DCR_DBL_0 (0x01UL << TIM_DCR_DBL_Pos)
    -
    12506#define TIM_DCR_DBL_1 (0x02UL << TIM_DCR_DBL_Pos)
    -
    12507#define TIM_DCR_DBL_2 (0x04UL << TIM_DCR_DBL_Pos)
    -
    12508#define TIM_DCR_DBL_3 (0x08UL << TIM_DCR_DBL_Pos)
    -
    12509#define TIM_DCR_DBL_4 (0x10UL << TIM_DCR_DBL_Pos)
    -
    12511/******************* Bit definition for TIM_DMAR register *******************/
    -
    12512#define TIM_DMAR_DMAB_Pos (0U)
    -
    12513#define TIM_DMAR_DMAB_Msk (0xFFFFUL << TIM_DMAR_DMAB_Pos)
    -
    12514#define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk
    -
    12516/******************* Bit definition for TIM_OR register *********************/
    -
    12517#define TIM_OR_TI1_RMP_Pos (0U)
    -
    12518#define TIM_OR_TI1_RMP_Msk (0x3UL << TIM_OR_TI1_RMP_Pos)
    -
    12519#define TIM_OR_TI1_RMP TIM_OR_TI1_RMP_Msk
    -
    12520#define TIM_OR_TI1_RMP_0 (0x1UL << TIM_OR_TI1_RMP_Pos)
    -
    12521#define TIM_OR_TI1_RMP_1 (0x2UL << TIM_OR_TI1_RMP_Pos)
    -
    12523#define TIM_OR_TI4_RMP_Pos (6U)
    -
    12524#define TIM_OR_TI4_RMP_Msk (0x3UL << TIM_OR_TI4_RMP_Pos)
    -
    12525#define TIM_OR_TI4_RMP TIM_OR_TI4_RMP_Msk
    -
    12526#define TIM_OR_TI4_RMP_0 (0x1UL << TIM_OR_TI4_RMP_Pos)
    -
    12527#define TIM_OR_TI4_RMP_1 (0x2UL << TIM_OR_TI4_RMP_Pos)
    -
    12528#define TIM_OR_ITR1_RMP_Pos (10U)
    -
    12529#define TIM_OR_ITR1_RMP_Msk (0x3UL << TIM_OR_ITR1_RMP_Pos)
    -
    12530#define TIM_OR_ITR1_RMP TIM_OR_ITR1_RMP_Msk
    -
    12531#define TIM_OR_ITR1_RMP_0 (0x1UL << TIM_OR_ITR1_RMP_Pos)
    -
    12532#define TIM_OR_ITR1_RMP_1 (0x2UL << TIM_OR_ITR1_RMP_Pos)
    -
    12535/******************************************************************************/
    -
    12536/* */
    -
    12537/* Universal Synchronous Asynchronous Receiver Transmitter */
    -
    12538/* */
    -
    12539/******************************************************************************/
    -
    12540/******************* Bit definition for USART_SR register *******************/
    -
    12541#define USART_SR_PE_Pos (0U)
    -
    12542#define USART_SR_PE_Msk (0x1UL << USART_SR_PE_Pos)
    -
    12543#define USART_SR_PE USART_SR_PE_Msk
    -
    12544#define USART_SR_FE_Pos (1U)
    -
    12545#define USART_SR_FE_Msk (0x1UL << USART_SR_FE_Pos)
    -
    12546#define USART_SR_FE USART_SR_FE_Msk
    -
    12547#define USART_SR_NE_Pos (2U)
    -
    12548#define USART_SR_NE_Msk (0x1UL << USART_SR_NE_Pos)
    -
    12549#define USART_SR_NE USART_SR_NE_Msk
    -
    12550#define USART_SR_ORE_Pos (3U)
    -
    12551#define USART_SR_ORE_Msk (0x1UL << USART_SR_ORE_Pos)
    -
    12552#define USART_SR_ORE USART_SR_ORE_Msk
    -
    12553#define USART_SR_IDLE_Pos (4U)
    -
    12554#define USART_SR_IDLE_Msk (0x1UL << USART_SR_IDLE_Pos)
    -
    12555#define USART_SR_IDLE USART_SR_IDLE_Msk
    -
    12556#define USART_SR_RXNE_Pos (5U)
    -
    12557#define USART_SR_RXNE_Msk (0x1UL << USART_SR_RXNE_Pos)
    -
    12558#define USART_SR_RXNE USART_SR_RXNE_Msk
    -
    12559#define USART_SR_TC_Pos (6U)
    -
    12560#define USART_SR_TC_Msk (0x1UL << USART_SR_TC_Pos)
    -
    12561#define USART_SR_TC USART_SR_TC_Msk
    -
    12562#define USART_SR_TXE_Pos (7U)
    -
    12563#define USART_SR_TXE_Msk (0x1UL << USART_SR_TXE_Pos)
    -
    12564#define USART_SR_TXE USART_SR_TXE_Msk
    -
    12565#define USART_SR_LBD_Pos (8U)
    -
    12566#define USART_SR_LBD_Msk (0x1UL << USART_SR_LBD_Pos)
    -
    12567#define USART_SR_LBD USART_SR_LBD_Msk
    -
    12568#define USART_SR_CTS_Pos (9U)
    -
    12569#define USART_SR_CTS_Msk (0x1UL << USART_SR_CTS_Pos)
    -
    12570#define USART_SR_CTS USART_SR_CTS_Msk
    -
    12572/******************* Bit definition for USART_DR register *******************/
    -
    12573#define USART_DR_DR_Pos (0U)
    -
    12574#define USART_DR_DR_Msk (0x1FFUL << USART_DR_DR_Pos)
    -
    12575#define USART_DR_DR USART_DR_DR_Msk
    -
    12577/****************** Bit definition for USART_BRR register *******************/
    -
    12578#define USART_BRR_DIV_Fraction_Pos (0U)
    -
    12579#define USART_BRR_DIV_Fraction_Msk (0xFUL << USART_BRR_DIV_Fraction_Pos)
    -
    12580#define USART_BRR_DIV_Fraction USART_BRR_DIV_Fraction_Msk
    -
    12581#define USART_BRR_DIV_Mantissa_Pos (4U)
    -
    12582#define USART_BRR_DIV_Mantissa_Msk (0xFFFUL << USART_BRR_DIV_Mantissa_Pos)
    -
    12583#define USART_BRR_DIV_Mantissa USART_BRR_DIV_Mantissa_Msk
    -
    12585/****************** Bit definition for USART_CR1 register *******************/
    -
    12586#define USART_CR1_SBK_Pos (0U)
    -
    12587#define USART_CR1_SBK_Msk (0x1UL << USART_CR1_SBK_Pos)
    -
    12588#define USART_CR1_SBK USART_CR1_SBK_Msk
    -
    12589#define USART_CR1_RWU_Pos (1U)
    -
    12590#define USART_CR1_RWU_Msk (0x1UL << USART_CR1_RWU_Pos)
    -
    12591#define USART_CR1_RWU USART_CR1_RWU_Msk
    -
    12592#define USART_CR1_RE_Pos (2U)
    -
    12593#define USART_CR1_RE_Msk (0x1UL << USART_CR1_RE_Pos)
    -
    12594#define USART_CR1_RE USART_CR1_RE_Msk
    -
    12595#define USART_CR1_TE_Pos (3U)
    -
    12596#define USART_CR1_TE_Msk (0x1UL << USART_CR1_TE_Pos)
    -
    12597#define USART_CR1_TE USART_CR1_TE_Msk
    -
    12598#define USART_CR1_IDLEIE_Pos (4U)
    -
    12599#define USART_CR1_IDLEIE_Msk (0x1UL << USART_CR1_IDLEIE_Pos)
    -
    12600#define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk
    -
    12601#define USART_CR1_RXNEIE_Pos (5U)
    -
    12602#define USART_CR1_RXNEIE_Msk (0x1UL << USART_CR1_RXNEIE_Pos)
    -
    12603#define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk
    -
    12604#define USART_CR1_TCIE_Pos (6U)
    -
    12605#define USART_CR1_TCIE_Msk (0x1UL << USART_CR1_TCIE_Pos)
    -
    12606#define USART_CR1_TCIE USART_CR1_TCIE_Msk
    -
    12607#define USART_CR1_TXEIE_Pos (7U)
    -
    12608#define USART_CR1_TXEIE_Msk (0x1UL << USART_CR1_TXEIE_Pos)
    -
    12609#define USART_CR1_TXEIE USART_CR1_TXEIE_Msk
    -
    12610#define USART_CR1_PEIE_Pos (8U)
    -
    12611#define USART_CR1_PEIE_Msk (0x1UL << USART_CR1_PEIE_Pos)
    -
    12612#define USART_CR1_PEIE USART_CR1_PEIE_Msk
    -
    12613#define USART_CR1_PS_Pos (9U)
    -
    12614#define USART_CR1_PS_Msk (0x1UL << USART_CR1_PS_Pos)
    -
    12615#define USART_CR1_PS USART_CR1_PS_Msk
    -
    12616#define USART_CR1_PCE_Pos (10U)
    -
    12617#define USART_CR1_PCE_Msk (0x1UL << USART_CR1_PCE_Pos)
    -
    12618#define USART_CR1_PCE USART_CR1_PCE_Msk
    -
    12619#define USART_CR1_WAKE_Pos (11U)
    -
    12620#define USART_CR1_WAKE_Msk (0x1UL << USART_CR1_WAKE_Pos)
    -
    12621#define USART_CR1_WAKE USART_CR1_WAKE_Msk
    -
    12622#define USART_CR1_M_Pos (12U)
    -
    12623#define USART_CR1_M_Msk (0x1UL << USART_CR1_M_Pos)
    -
    12624#define USART_CR1_M USART_CR1_M_Msk
    -
    12625#define USART_CR1_UE_Pos (13U)
    -
    12626#define USART_CR1_UE_Msk (0x1UL << USART_CR1_UE_Pos)
    -
    12627#define USART_CR1_UE USART_CR1_UE_Msk
    -
    12628#define USART_CR1_OVER8_Pos (15U)
    -
    12629#define USART_CR1_OVER8_Msk (0x1UL << USART_CR1_OVER8_Pos)
    -
    12630#define USART_CR1_OVER8 USART_CR1_OVER8_Msk
    -
    12632/****************** Bit definition for USART_CR2 register *******************/
    -
    12633#define USART_CR2_ADD_Pos (0U)
    -
    12634#define USART_CR2_ADD_Msk (0xFUL << USART_CR2_ADD_Pos)
    -
    12635#define USART_CR2_ADD USART_CR2_ADD_Msk
    -
    12636#define USART_CR2_LBDL_Pos (5U)
    -
    12637#define USART_CR2_LBDL_Msk (0x1UL << USART_CR2_LBDL_Pos)
    -
    12638#define USART_CR2_LBDL USART_CR2_LBDL_Msk
    -
    12639#define USART_CR2_LBDIE_Pos (6U)
    -
    12640#define USART_CR2_LBDIE_Msk (0x1UL << USART_CR2_LBDIE_Pos)
    -
    12641#define USART_CR2_LBDIE USART_CR2_LBDIE_Msk
    -
    12642#define USART_CR2_LBCL_Pos (8U)
    -
    12643#define USART_CR2_LBCL_Msk (0x1UL << USART_CR2_LBCL_Pos)
    -
    12644#define USART_CR2_LBCL USART_CR2_LBCL_Msk
    -
    12645#define USART_CR2_CPHA_Pos (9U)
    -
    12646#define USART_CR2_CPHA_Msk (0x1UL << USART_CR2_CPHA_Pos)
    -
    12647#define USART_CR2_CPHA USART_CR2_CPHA_Msk
    -
    12648#define USART_CR2_CPOL_Pos (10U)
    -
    12649#define USART_CR2_CPOL_Msk (0x1UL << USART_CR2_CPOL_Pos)
    -
    12650#define USART_CR2_CPOL USART_CR2_CPOL_Msk
    -
    12651#define USART_CR2_CLKEN_Pos (11U)
    -
    12652#define USART_CR2_CLKEN_Msk (0x1UL << USART_CR2_CLKEN_Pos)
    -
    12653#define USART_CR2_CLKEN USART_CR2_CLKEN_Msk
    -
    12655#define USART_CR2_STOP_Pos (12U)
    -
    12656#define USART_CR2_STOP_Msk (0x3UL << USART_CR2_STOP_Pos)
    -
    12657#define USART_CR2_STOP USART_CR2_STOP_Msk
    -
    12658#define USART_CR2_STOP_0 (0x1UL << USART_CR2_STOP_Pos)
    -
    12659#define USART_CR2_STOP_1 (0x2UL << USART_CR2_STOP_Pos)
    -
    12661#define USART_CR2_LINEN_Pos (14U)
    -
    12662#define USART_CR2_LINEN_Msk (0x1UL << USART_CR2_LINEN_Pos)
    -
    12663#define USART_CR2_LINEN USART_CR2_LINEN_Msk
    -
    12665/****************** Bit definition for USART_CR3 register *******************/
    -
    12666#define USART_CR3_EIE_Pos (0U)
    -
    12667#define USART_CR3_EIE_Msk (0x1UL << USART_CR3_EIE_Pos)
    -
    12668#define USART_CR3_EIE USART_CR3_EIE_Msk
    -
    12669#define USART_CR3_IREN_Pos (1U)
    -
    12670#define USART_CR3_IREN_Msk (0x1UL << USART_CR3_IREN_Pos)
    -
    12671#define USART_CR3_IREN USART_CR3_IREN_Msk
    -
    12672#define USART_CR3_IRLP_Pos (2U)
    -
    12673#define USART_CR3_IRLP_Msk (0x1UL << USART_CR3_IRLP_Pos)
    -
    12674#define USART_CR3_IRLP USART_CR3_IRLP_Msk
    -
    12675#define USART_CR3_HDSEL_Pos (3U)
    -
    12676#define USART_CR3_HDSEL_Msk (0x1UL << USART_CR3_HDSEL_Pos)
    -
    12677#define USART_CR3_HDSEL USART_CR3_HDSEL_Msk
    -
    12678#define USART_CR3_NACK_Pos (4U)
    -
    12679#define USART_CR3_NACK_Msk (0x1UL << USART_CR3_NACK_Pos)
    -
    12680#define USART_CR3_NACK USART_CR3_NACK_Msk
    -
    12681#define USART_CR3_SCEN_Pos (5U)
    -
    12682#define USART_CR3_SCEN_Msk (0x1UL << USART_CR3_SCEN_Pos)
    -
    12683#define USART_CR3_SCEN USART_CR3_SCEN_Msk
    -
    12684#define USART_CR3_DMAR_Pos (6U)
    -
    12685#define USART_CR3_DMAR_Msk (0x1UL << USART_CR3_DMAR_Pos)
    -
    12686#define USART_CR3_DMAR USART_CR3_DMAR_Msk
    -
    12687#define USART_CR3_DMAT_Pos (7U)
    -
    12688#define USART_CR3_DMAT_Msk (0x1UL << USART_CR3_DMAT_Pos)
    -
    12689#define USART_CR3_DMAT USART_CR3_DMAT_Msk
    -
    12690#define USART_CR3_RTSE_Pos (8U)
    -
    12691#define USART_CR3_RTSE_Msk (0x1UL << USART_CR3_RTSE_Pos)
    -
    12692#define USART_CR3_RTSE USART_CR3_RTSE_Msk
    -
    12693#define USART_CR3_CTSE_Pos (9U)
    -
    12694#define USART_CR3_CTSE_Msk (0x1UL << USART_CR3_CTSE_Pos)
    -
    12695#define USART_CR3_CTSE USART_CR3_CTSE_Msk
    -
    12696#define USART_CR3_CTSIE_Pos (10U)
    -
    12697#define USART_CR3_CTSIE_Msk (0x1UL << USART_CR3_CTSIE_Pos)
    -
    12698#define USART_CR3_CTSIE USART_CR3_CTSIE_Msk
    -
    12699#define USART_CR3_ONEBIT_Pos (11U)
    -
    12700#define USART_CR3_ONEBIT_Msk (0x1UL << USART_CR3_ONEBIT_Pos)
    -
    12701#define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk
    -
    12703/****************** Bit definition for USART_GTPR register ******************/
    -
    12704#define USART_GTPR_PSC_Pos (0U)
    -
    12705#define USART_GTPR_PSC_Msk (0xFFUL << USART_GTPR_PSC_Pos)
    -
    12706#define USART_GTPR_PSC USART_GTPR_PSC_Msk
    -
    12707#define USART_GTPR_PSC_0 (0x01UL << USART_GTPR_PSC_Pos)
    -
    12708#define USART_GTPR_PSC_1 (0x02UL << USART_GTPR_PSC_Pos)
    -
    12709#define USART_GTPR_PSC_2 (0x04UL << USART_GTPR_PSC_Pos)
    -
    12710#define USART_GTPR_PSC_3 (0x08UL << USART_GTPR_PSC_Pos)
    -
    12711#define USART_GTPR_PSC_4 (0x10UL << USART_GTPR_PSC_Pos)
    -
    12712#define USART_GTPR_PSC_5 (0x20UL << USART_GTPR_PSC_Pos)
    -
    12713#define USART_GTPR_PSC_6 (0x40UL << USART_GTPR_PSC_Pos)
    -
    12714#define USART_GTPR_PSC_7 (0x80UL << USART_GTPR_PSC_Pos)
    -
    12716#define USART_GTPR_GT_Pos (8U)
    -
    12717#define USART_GTPR_GT_Msk (0xFFUL << USART_GTPR_GT_Pos)
    -
    12718#define USART_GTPR_GT USART_GTPR_GT_Msk
    -
    12720/******************************************************************************/
    -
    12721/* */
    -
    12722/* Window WATCHDOG */
    -
    12723/* */
    -
    12724/******************************************************************************/
    -
    12725/******************* Bit definition for WWDG_CR register ********************/
    -
    12726#define WWDG_CR_T_Pos (0U)
    -
    12727#define WWDG_CR_T_Msk (0x7FUL << WWDG_CR_T_Pos)
    -
    12728#define WWDG_CR_T WWDG_CR_T_Msk
    -
    12729#define WWDG_CR_T_0 (0x01UL << WWDG_CR_T_Pos)
    -
    12730#define WWDG_CR_T_1 (0x02UL << WWDG_CR_T_Pos)
    -
    12731#define WWDG_CR_T_2 (0x04UL << WWDG_CR_T_Pos)
    -
    12732#define WWDG_CR_T_3 (0x08UL << WWDG_CR_T_Pos)
    -
    12733#define WWDG_CR_T_4 (0x10UL << WWDG_CR_T_Pos)
    -
    12734#define WWDG_CR_T_5 (0x20UL << WWDG_CR_T_Pos)
    -
    12735#define WWDG_CR_T_6 (0x40UL << WWDG_CR_T_Pos)
    -
    12736/* Legacy defines */
    -
    12737#define WWDG_CR_T0 WWDG_CR_T_0
    -
    12738#define WWDG_CR_T1 WWDG_CR_T_1
    -
    12739#define WWDG_CR_T2 WWDG_CR_T_2
    -
    12740#define WWDG_CR_T3 WWDG_CR_T_3
    -
    12741#define WWDG_CR_T4 WWDG_CR_T_4
    -
    12742#define WWDG_CR_T5 WWDG_CR_T_5
    -
    12743#define WWDG_CR_T6 WWDG_CR_T_6
    -
    12744
    -
    12745#define WWDG_CR_WDGA_Pos (7U)
    -
    12746#define WWDG_CR_WDGA_Msk (0x1UL << WWDG_CR_WDGA_Pos)
    -
    12747#define WWDG_CR_WDGA WWDG_CR_WDGA_Msk
    -
    12749/******************* Bit definition for WWDG_CFR register *******************/
    -
    12750#define WWDG_CFR_W_Pos (0U)
    -
    12751#define WWDG_CFR_W_Msk (0x7FUL << WWDG_CFR_W_Pos)
    -
    12752#define WWDG_CFR_W WWDG_CFR_W_Msk
    -
    12753#define WWDG_CFR_W_0 (0x01UL << WWDG_CFR_W_Pos)
    -
    12754#define WWDG_CFR_W_1 (0x02UL << WWDG_CFR_W_Pos)
    -
    12755#define WWDG_CFR_W_2 (0x04UL << WWDG_CFR_W_Pos)
    -
    12756#define WWDG_CFR_W_3 (0x08UL << WWDG_CFR_W_Pos)
    -
    12757#define WWDG_CFR_W_4 (0x10UL << WWDG_CFR_W_Pos)
    -
    12758#define WWDG_CFR_W_5 (0x20UL << WWDG_CFR_W_Pos)
    -
    12759#define WWDG_CFR_W_6 (0x40UL << WWDG_CFR_W_Pos)
    -
    12760/* Legacy defines */
    -
    12761#define WWDG_CFR_W0 WWDG_CFR_W_0
    -
    12762#define WWDG_CFR_W1 WWDG_CFR_W_1
    -
    12763#define WWDG_CFR_W2 WWDG_CFR_W_2
    -
    12764#define WWDG_CFR_W3 WWDG_CFR_W_3
    -
    12765#define WWDG_CFR_W4 WWDG_CFR_W_4
    -
    12766#define WWDG_CFR_W5 WWDG_CFR_W_5
    -
    12767#define WWDG_CFR_W6 WWDG_CFR_W_6
    -
    12768
    -
    12769#define WWDG_CFR_WDGTB_Pos (7U)
    -
    12770#define WWDG_CFR_WDGTB_Msk (0x3UL << WWDG_CFR_WDGTB_Pos)
    -
    12771#define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk
    -
    12772#define WWDG_CFR_WDGTB_0 (0x1UL << WWDG_CFR_WDGTB_Pos)
    -
    12773#define WWDG_CFR_WDGTB_1 (0x2UL << WWDG_CFR_WDGTB_Pos)
    -
    12774/* Legacy defines */
    -
    12775#define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
    -
    12776#define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
    -
    12777
    -
    12778#define WWDG_CFR_EWI_Pos (9U)
    -
    12779#define WWDG_CFR_EWI_Msk (0x1UL << WWDG_CFR_EWI_Pos)
    -
    12780#define WWDG_CFR_EWI WWDG_CFR_EWI_Msk
    -
    12782/******************* Bit definition for WWDG_SR register ********************/
    -
    12783#define WWDG_SR_EWIF_Pos (0U)
    -
    12784#define WWDG_SR_EWIF_Msk (0x1UL << WWDG_SR_EWIF_Pos)
    -
    12785#define WWDG_SR_EWIF WWDG_SR_EWIF_Msk
    -
    12788/******************************************************************************/
    -
    12789/* */
    -
    12790/* DBG */
    -
    12791/* */
    -
    12792/******************************************************************************/
    -
    12793/******************** Bit definition for DBGMCU_IDCODE register *************/
    -
    12794#define DBGMCU_IDCODE_DEV_ID_Pos (0U)
    -
    12795#define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos)
    -
    12796#define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk
    -
    12797#define DBGMCU_IDCODE_REV_ID_Pos (16U)
    -
    12798#define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos)
    -
    12799#define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk
    -
    12800
    -
    12801/******************** Bit definition for DBGMCU_CR register *****************/
    -
    12802#define DBGMCU_CR_DBG_SLEEP_Pos (0U)
    -
    12803#define DBGMCU_CR_DBG_SLEEP_Msk (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos)
    -
    12804#define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk
    -
    12805#define DBGMCU_CR_DBG_STOP_Pos (1U)
    -
    12806#define DBGMCU_CR_DBG_STOP_Msk (0x1UL << DBGMCU_CR_DBG_STOP_Pos)
    -
    12807#define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk
    -
    12808#define DBGMCU_CR_DBG_STANDBY_Pos (2U)
    -
    12809#define DBGMCU_CR_DBG_STANDBY_Msk (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos)
    -
    12810#define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk
    -
    12811#define DBGMCU_CR_TRACE_IOEN_Pos (5U)
    -
    12812#define DBGMCU_CR_TRACE_IOEN_Msk (0x1UL << DBGMCU_CR_TRACE_IOEN_Pos)
    -
    12813#define DBGMCU_CR_TRACE_IOEN DBGMCU_CR_TRACE_IOEN_Msk
    -
    12814
    -
    12815#define DBGMCU_CR_TRACE_MODE_Pos (6U)
    -
    12816#define DBGMCU_CR_TRACE_MODE_Msk (0x3UL << DBGMCU_CR_TRACE_MODE_Pos)
    -
    12817#define DBGMCU_CR_TRACE_MODE DBGMCU_CR_TRACE_MODE_Msk
    -
    12818#define DBGMCU_CR_TRACE_MODE_0 (0x1UL << DBGMCU_CR_TRACE_MODE_Pos)
    -
    12819#define DBGMCU_CR_TRACE_MODE_1 (0x2UL << DBGMCU_CR_TRACE_MODE_Pos)
    -
    12821/******************** Bit definition for DBGMCU_APB1_FZ register ************/
    -
    12822#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos (0U)
    -
    12823#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos)
    -
    12824#define DBGMCU_APB1_FZ_DBG_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk
    -
    12825#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos (1U)
    -
    12826#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos)
    -
    12827#define DBGMCU_APB1_FZ_DBG_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk
    -
    12828#define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos (2U)
    -
    12829#define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos)
    -
    12830#define DBGMCU_APB1_FZ_DBG_TIM4_STOP DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk
    -
    12831#define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos (3U)
    -
    12832#define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos)
    -
    12833#define DBGMCU_APB1_FZ_DBG_TIM5_STOP DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk
    -
    12834#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos (4U)
    -
    12835#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos)
    -
    12836#define DBGMCU_APB1_FZ_DBG_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk
    -
    12837#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos (5U)
    -
    12838#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos)
    -
    12839#define DBGMCU_APB1_FZ_DBG_TIM7_STOP DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk
    -
    12840#define DBGMCU_APB1_FZ_DBG_TIM12_STOP_Pos (6U)
    -
    12841#define DBGMCU_APB1_FZ_DBG_TIM12_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM12_STOP_Pos)
    -
    12842#define DBGMCU_APB1_FZ_DBG_TIM12_STOP DBGMCU_APB1_FZ_DBG_TIM12_STOP_Msk
    -
    12843#define DBGMCU_APB1_FZ_DBG_TIM13_STOP_Pos (7U)
    -
    12844#define DBGMCU_APB1_FZ_DBG_TIM13_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM13_STOP_Pos)
    -
    12845#define DBGMCU_APB1_FZ_DBG_TIM13_STOP DBGMCU_APB1_FZ_DBG_TIM13_STOP_Msk
    -
    12846#define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos (8U)
    -
    12847#define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos)
    -
    12848#define DBGMCU_APB1_FZ_DBG_TIM14_STOP DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk
    -
    12849#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos (10U)
    -
    12850#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos)
    -
    12851#define DBGMCU_APB1_FZ_DBG_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk
    -
    12852#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos (11U)
    -
    12853#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos)
    -
    12854#define DBGMCU_APB1_FZ_DBG_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk
    -
    12855#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos (12U)
    -
    12856#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos)
    -
    12857#define DBGMCU_APB1_FZ_DBG_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk
    -
    12858#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos (21U)
    -
    12859#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos)
    -
    12860#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk
    -
    12861#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos (22U)
    -
    12862#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos)
    -
    12863#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk
    -
    12864#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos (23U)
    -
    12865#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos)
    -
    12866#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk
    -
    12867#define DBGMCU_APB1_FZ_DBG_CAN1_STOP_Pos (25U)
    -
    12868#define DBGMCU_APB1_FZ_DBG_CAN1_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_CAN1_STOP_Pos)
    -
    12869#define DBGMCU_APB1_FZ_DBG_CAN1_STOP DBGMCU_APB1_FZ_DBG_CAN1_STOP_Msk
    -
    12870#define DBGMCU_APB1_FZ_DBG_CAN2_STOP_Pos (26U)
    -
    12871#define DBGMCU_APB1_FZ_DBG_CAN2_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_CAN2_STOP_Pos)
    -
    12872#define DBGMCU_APB1_FZ_DBG_CAN2_STOP DBGMCU_APB1_FZ_DBG_CAN2_STOP_Msk
    -
    12873/* Old IWDGSTOP bit definition, maintained for legacy purpose */
    -
    12874#define DBGMCU_APB1_FZ_DBG_IWDEG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP
    -
    12875
    -
    12876/******************** Bit definition for DBGMCU_APB2_FZ register ************/
    -
    12877#define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos (0U)
    -
    12878#define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos)
    -
    12879#define DBGMCU_APB2_FZ_DBG_TIM1_STOP DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk
    -
    12880#define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos (1U)
    -
    12881#define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos)
    -
    12882#define DBGMCU_APB2_FZ_DBG_TIM8_STOP DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk
    -
    12883#define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos (16U)
    -
    12884#define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos)
    -
    12885#define DBGMCU_APB2_FZ_DBG_TIM9_STOP DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk
    -
    12886#define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos (17U)
    -
    12887#define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos)
    -
    12888#define DBGMCU_APB2_FZ_DBG_TIM10_STOP DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk
    -
    12889#define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos (18U)
    -
    12890#define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos)
    -
    12891#define DBGMCU_APB2_FZ_DBG_TIM11_STOP DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk
    -
    12892
    -
    12893/******************************************************************************/
    -
    12894/* */
    -
    12895/* Ethernet MAC Registers bits definitions */
    -
    12896/* */
    -
    12897/******************************************************************************/
    -
    12898/* Bit definition for Ethernet MAC Control Register register */
    -
    12899#define ETH_MACCR_WD_Pos (23U)
    -
    12900#define ETH_MACCR_WD_Msk (0x1UL << ETH_MACCR_WD_Pos)
    -
    12901#define ETH_MACCR_WD ETH_MACCR_WD_Msk /* Watchdog disable */
    -
    12902#define ETH_MACCR_JD_Pos (22U)
    -
    12903#define ETH_MACCR_JD_Msk (0x1UL << ETH_MACCR_JD_Pos)
    -
    12904#define ETH_MACCR_JD ETH_MACCR_JD_Msk /* Jabber disable */
    -
    12905#define ETH_MACCR_IFG_Pos (17U)
    -
    12906#define ETH_MACCR_IFG_Msk (0x7UL << ETH_MACCR_IFG_Pos)
    -
    12907#define ETH_MACCR_IFG ETH_MACCR_IFG_Msk /* Inter-frame gap */
    -
    12908#define ETH_MACCR_IFG_96Bit 0x00000000U /* Minimum IFG between frames during transmission is 96Bit */
    -
    12909#define ETH_MACCR_IFG_88Bit 0x00020000U /* Minimum IFG between frames during transmission is 88Bit */
    -
    12910#define ETH_MACCR_IFG_80Bit 0x00040000U /* Minimum IFG between frames during transmission is 80Bit */
    -
    12911#define ETH_MACCR_IFG_72Bit 0x00060000U /* Minimum IFG between frames during transmission is 72Bit */
    -
    12912#define ETH_MACCR_IFG_64Bit 0x00080000U /* Minimum IFG between frames during transmission is 64Bit */
    -
    12913#define ETH_MACCR_IFG_56Bit 0x000A0000U /* Minimum IFG between frames during transmission is 56Bit */
    -
    12914#define ETH_MACCR_IFG_48Bit 0x000C0000U /* Minimum IFG between frames during transmission is 48Bit */
    -
    12915#define ETH_MACCR_IFG_40Bit 0x000E0000U /* Minimum IFG between frames during transmission is 40Bit */
    -
    12916#define ETH_MACCR_CSD_Pos (16U)
    -
    12917#define ETH_MACCR_CSD_Msk (0x1UL << ETH_MACCR_CSD_Pos)
    -
    12918#define ETH_MACCR_CSD ETH_MACCR_CSD_Msk /* Carrier sense disable (during transmission) */
    -
    12919#define ETH_MACCR_FES_Pos (14U)
    -
    12920#define ETH_MACCR_FES_Msk (0x1UL << ETH_MACCR_FES_Pos)
    -
    12921#define ETH_MACCR_FES ETH_MACCR_FES_Msk /* Fast ethernet speed */
    -
    12922#define ETH_MACCR_ROD_Pos (13U)
    -
    12923#define ETH_MACCR_ROD_Msk (0x1UL << ETH_MACCR_ROD_Pos)
    -
    12924#define ETH_MACCR_ROD ETH_MACCR_ROD_Msk /* Receive own disable */
    -
    12925#define ETH_MACCR_LM_Pos (12U)
    -
    12926#define ETH_MACCR_LM_Msk (0x1UL << ETH_MACCR_LM_Pos)
    -
    12927#define ETH_MACCR_LM ETH_MACCR_LM_Msk /* loopback mode */
    -
    12928#define ETH_MACCR_DM_Pos (11U)
    -
    12929#define ETH_MACCR_DM_Msk (0x1UL << ETH_MACCR_DM_Pos)
    -
    12930#define ETH_MACCR_DM ETH_MACCR_DM_Msk /* Duplex mode */
    -
    12931#define ETH_MACCR_IPCO_Pos (10U)
    -
    12932#define ETH_MACCR_IPCO_Msk (0x1UL << ETH_MACCR_IPCO_Pos)
    -
    12933#define ETH_MACCR_IPCO ETH_MACCR_IPCO_Msk /* IP Checksum offload */
    -
    12934#define ETH_MACCR_RD_Pos (9U)
    -
    12935#define ETH_MACCR_RD_Msk (0x1UL << ETH_MACCR_RD_Pos)
    -
    12936#define ETH_MACCR_RD ETH_MACCR_RD_Msk /* Retry disable */
    -
    12937#define ETH_MACCR_APCS_Pos (7U)
    -
    12938#define ETH_MACCR_APCS_Msk (0x1UL << ETH_MACCR_APCS_Pos)
    -
    12939#define ETH_MACCR_APCS ETH_MACCR_APCS_Msk /* Automatic Pad/CRC stripping */
    -
    12940#define ETH_MACCR_BL_Pos (5U)
    -
    12941#define ETH_MACCR_BL_Msk (0x3UL << ETH_MACCR_BL_Pos)
    -
    12942#define ETH_MACCR_BL ETH_MACCR_BL_Msk /* Back-off limit: random integer number (r) of slot time delays before rescheduling
    -
    12943 a transmission attempt during retries after a collision: 0 =< r <2^k */
    -
    12944#define ETH_MACCR_BL_10 0x00000000U /* k = min (n, 10) */
    -
    12945#define ETH_MACCR_BL_8 0x00000020U /* k = min (n, 8) */
    -
    12946#define ETH_MACCR_BL_4 0x00000040U /* k = min (n, 4) */
    -
    12947#define ETH_MACCR_BL_1 0x00000060U /* k = min (n, 1) */
    -
    12948#define ETH_MACCR_DC_Pos (4U)
    -
    12949#define ETH_MACCR_DC_Msk (0x1UL << ETH_MACCR_DC_Pos)
    -
    12950#define ETH_MACCR_DC ETH_MACCR_DC_Msk /* Defferal check */
    -
    12951#define ETH_MACCR_TE_Pos (3U)
    -
    12952#define ETH_MACCR_TE_Msk (0x1UL << ETH_MACCR_TE_Pos)
    -
    12953#define ETH_MACCR_TE ETH_MACCR_TE_Msk /* Transmitter enable */
    -
    12954#define ETH_MACCR_RE_Pos (2U)
    -
    12955#define ETH_MACCR_RE_Msk (0x1UL << ETH_MACCR_RE_Pos)
    -
    12956#define ETH_MACCR_RE ETH_MACCR_RE_Msk /* Receiver enable */
    -
    12957
    -
    12958/* Bit definition for Ethernet MAC Frame Filter Register */
    -
    12959#define ETH_MACFFR_RA_Pos (31U)
    -
    12960#define ETH_MACFFR_RA_Msk (0x1UL << ETH_MACFFR_RA_Pos)
    -
    12961#define ETH_MACFFR_RA ETH_MACFFR_RA_Msk /* Receive all */
    -
    12962#define ETH_MACFFR_HPF_Pos (10U)
    -
    12963#define ETH_MACFFR_HPF_Msk (0x1UL << ETH_MACFFR_HPF_Pos)
    -
    12964#define ETH_MACFFR_HPF ETH_MACFFR_HPF_Msk /* Hash or perfect filter */
    -
    12965#define ETH_MACFFR_SAF_Pos (9U)
    -
    12966#define ETH_MACFFR_SAF_Msk (0x1UL << ETH_MACFFR_SAF_Pos)
    -
    12967#define ETH_MACFFR_SAF ETH_MACFFR_SAF_Msk /* Source address filter enable */
    -
    12968#define ETH_MACFFR_SAIF_Pos (8U)
    -
    12969#define ETH_MACFFR_SAIF_Msk (0x1UL << ETH_MACFFR_SAIF_Pos)
    -
    12970#define ETH_MACFFR_SAIF ETH_MACFFR_SAIF_Msk /* SA inverse filtering */
    -
    12971#define ETH_MACFFR_PCF_Pos (6U)
    -
    12972#define ETH_MACFFR_PCF_Msk (0x3UL << ETH_MACFFR_PCF_Pos)
    -
    12973#define ETH_MACFFR_PCF ETH_MACFFR_PCF_Msk /* Pass control frames: 3 cases */
    -
    12974#define ETH_MACFFR_PCF_BlockAll_Pos (6U)
    -
    12975#define ETH_MACFFR_PCF_BlockAll_Msk (0x1UL << ETH_MACFFR_PCF_BlockAll_Pos)
    -
    12976#define ETH_MACFFR_PCF_BlockAll ETH_MACFFR_PCF_BlockAll_Msk /* MAC filters all control frames from reaching the application */
    -
    12977#define ETH_MACFFR_PCF_ForwardAll_Pos (7U)
    -
    12978#define ETH_MACFFR_PCF_ForwardAll_Msk (0x1UL << ETH_MACFFR_PCF_ForwardAll_Pos)
    -
    12979#define ETH_MACFFR_PCF_ForwardAll ETH_MACFFR_PCF_ForwardAll_Msk /* MAC forwards all control frames to application even if they fail the Address Filter */
    -
    12980#define ETH_MACFFR_PCF_ForwardPassedAddrFilter_Pos (6U)
    -
    12981#define ETH_MACFFR_PCF_ForwardPassedAddrFilter_Msk (0x3UL << ETH_MACFFR_PCF_ForwardPassedAddrFilter_Pos)
    -
    12982#define ETH_MACFFR_PCF_ForwardPassedAddrFilter ETH_MACFFR_PCF_ForwardPassedAddrFilter_Msk /* MAC forwards control frames that pass the Address Filter. */
    -
    12983#define ETH_MACFFR_BFD_Pos (5U)
    -
    12984#define ETH_MACFFR_BFD_Msk (0x1UL << ETH_MACFFR_BFD_Pos)
    -
    12985#define ETH_MACFFR_BFD ETH_MACFFR_BFD_Msk /* Broadcast frame disable */
    -
    12986#define ETH_MACFFR_PAM_Pos (4U)
    -
    12987#define ETH_MACFFR_PAM_Msk (0x1UL << ETH_MACFFR_PAM_Pos)
    -
    12988#define ETH_MACFFR_PAM ETH_MACFFR_PAM_Msk /* Pass all mutlicast */
    -
    12989#define ETH_MACFFR_DAIF_Pos (3U)
    -
    12990#define ETH_MACFFR_DAIF_Msk (0x1UL << ETH_MACFFR_DAIF_Pos)
    -
    12991#define ETH_MACFFR_DAIF ETH_MACFFR_DAIF_Msk /* DA Inverse filtering */
    -
    12992#define ETH_MACFFR_HM_Pos (2U)
    -
    12993#define ETH_MACFFR_HM_Msk (0x1UL << ETH_MACFFR_HM_Pos)
    -
    12994#define ETH_MACFFR_HM ETH_MACFFR_HM_Msk /* Hash multicast */
    -
    12995#define ETH_MACFFR_HU_Pos (1U)
    -
    12996#define ETH_MACFFR_HU_Msk (0x1UL << ETH_MACFFR_HU_Pos)
    -
    12997#define ETH_MACFFR_HU ETH_MACFFR_HU_Msk /* Hash unicast */
    -
    12998#define ETH_MACFFR_PM_Pos (0U)
    -
    12999#define ETH_MACFFR_PM_Msk (0x1UL << ETH_MACFFR_PM_Pos)
    -
    13000#define ETH_MACFFR_PM ETH_MACFFR_PM_Msk /* Promiscuous mode */
    -
    13001
    -
    13002/* Bit definition for Ethernet MAC Hash Table High Register */
    -
    13003#define ETH_MACHTHR_HTH_Pos (0U)
    -
    13004#define ETH_MACHTHR_HTH_Msk (0xFFFFFFFFUL << ETH_MACHTHR_HTH_Pos)
    -
    13005#define ETH_MACHTHR_HTH ETH_MACHTHR_HTH_Msk /* Hash table high */
    -
    13006
    -
    13007/* Bit definition for Ethernet MAC Hash Table Low Register */
    -
    13008#define ETH_MACHTLR_HTL_Pos (0U)
    -
    13009#define ETH_MACHTLR_HTL_Msk (0xFFFFFFFFUL << ETH_MACHTLR_HTL_Pos)
    -
    13010#define ETH_MACHTLR_HTL ETH_MACHTLR_HTL_Msk /* Hash table low */
    -
    13011
    -
    13012/* Bit definition for Ethernet MAC MII Address Register */
    -
    13013#define ETH_MACMIIAR_PA_Pos (11U)
    -
    13014#define ETH_MACMIIAR_PA_Msk (0x1FUL << ETH_MACMIIAR_PA_Pos)
    -
    13015#define ETH_MACMIIAR_PA ETH_MACMIIAR_PA_Msk /* Physical layer address */
    -
    13016#define ETH_MACMIIAR_MR_Pos (6U)
    -
    13017#define ETH_MACMIIAR_MR_Msk (0x1FUL << ETH_MACMIIAR_MR_Pos)
    -
    13018#define ETH_MACMIIAR_MR ETH_MACMIIAR_MR_Msk /* MII register in the selected PHY */
    -
    13019#define ETH_MACMIIAR_CR_Pos (2U)
    -
    13020#define ETH_MACMIIAR_CR_Msk (0x7UL << ETH_MACMIIAR_CR_Pos)
    -
    13021#define ETH_MACMIIAR_CR ETH_MACMIIAR_CR_Msk /* CR clock range: 6 cases */
    -
    13022#define ETH_MACMIIAR_CR_Div42 0x00000000U /* HCLK:60-100 MHz; MDC clock= HCLK/42 */
    -
    13023#define ETH_MACMIIAR_CR_Div62_Pos (2U)
    -
    13024#define ETH_MACMIIAR_CR_Div62_Msk (0x1UL << ETH_MACMIIAR_CR_Div62_Pos)
    -
    13025#define ETH_MACMIIAR_CR_Div62 ETH_MACMIIAR_CR_Div62_Msk /* HCLK:100-150 MHz; MDC clock= HCLK/62 */
    -
    13026#define ETH_MACMIIAR_CR_Div16_Pos (3U)
    -
    13027#define ETH_MACMIIAR_CR_Div16_Msk (0x1UL << ETH_MACMIIAR_CR_Div16_Pos)
    -
    13028#define ETH_MACMIIAR_CR_Div16 ETH_MACMIIAR_CR_Div16_Msk /* HCLK:20-35 MHz; MDC clock= HCLK/16 */
    -
    13029#define ETH_MACMIIAR_CR_Div26_Pos (2U)
    -
    13030#define ETH_MACMIIAR_CR_Div26_Msk (0x3UL << ETH_MACMIIAR_CR_Div26_Pos)
    -
    13031#define ETH_MACMIIAR_CR_Div26 ETH_MACMIIAR_CR_Div26_Msk /* HCLK:35-60 MHz; MDC clock= HCLK/26 */
    -
    13032#define ETH_MACMIIAR_CR_Div102_Pos (4U)
    -
    13033#define ETH_MACMIIAR_CR_Div102_Msk (0x1UL << ETH_MACMIIAR_CR_Div102_Pos)
    -
    13034#define ETH_MACMIIAR_CR_Div102 ETH_MACMIIAR_CR_Div102_Msk /* HCLK:150-168 MHz; MDC clock= HCLK/102 */
    -
    13035#define ETH_MACMIIAR_MW_Pos (1U)
    -
    13036#define ETH_MACMIIAR_MW_Msk (0x1UL << ETH_MACMIIAR_MW_Pos)
    -
    13037#define ETH_MACMIIAR_MW ETH_MACMIIAR_MW_Msk /* MII write */
    -
    13038#define ETH_MACMIIAR_MB_Pos (0U)
    -
    13039#define ETH_MACMIIAR_MB_Msk (0x1UL << ETH_MACMIIAR_MB_Pos)
    -
    13040#define ETH_MACMIIAR_MB ETH_MACMIIAR_MB_Msk /* MII busy */
    -
    13041
    -
    13042/* Bit definition for Ethernet MAC MII Data Register */
    -
    13043#define ETH_MACMIIDR_MD_Pos (0U)
    -
    13044#define ETH_MACMIIDR_MD_Msk (0xFFFFUL << ETH_MACMIIDR_MD_Pos)
    -
    13045#define ETH_MACMIIDR_MD ETH_MACMIIDR_MD_Msk /* MII data: read/write data from/to PHY */
    -
    13046
    -
    13047/* Bit definition for Ethernet MAC Flow Control Register */
    -
    13048#define ETH_MACFCR_PT_Pos (16U)
    -
    13049#define ETH_MACFCR_PT_Msk (0xFFFFUL << ETH_MACFCR_PT_Pos)
    -
    13050#define ETH_MACFCR_PT ETH_MACFCR_PT_Msk /* Pause time */
    -
    13051#define ETH_MACFCR_ZQPD_Pos (7U)
    -
    13052#define ETH_MACFCR_ZQPD_Msk (0x1UL << ETH_MACFCR_ZQPD_Pos)
    -
    13053#define ETH_MACFCR_ZQPD ETH_MACFCR_ZQPD_Msk /* Zero-quanta pause disable */
    -
    13054#define ETH_MACFCR_PLT_Pos (4U)
    -
    13055#define ETH_MACFCR_PLT_Msk (0x3UL << ETH_MACFCR_PLT_Pos)
    -
    13056#define ETH_MACFCR_PLT ETH_MACFCR_PLT_Msk /* Pause low threshold: 4 cases */
    -
    13057#define ETH_MACFCR_PLT_Minus4 0x00000000U /* Pause time minus 4 slot times */
    -
    13058#define ETH_MACFCR_PLT_Minus28_Pos (4U)
    -
    13059#define ETH_MACFCR_PLT_Minus28_Msk (0x1UL << ETH_MACFCR_PLT_Minus28_Pos)
    -
    13060#define ETH_MACFCR_PLT_Minus28 ETH_MACFCR_PLT_Minus28_Msk /* Pause time minus 28 slot times */
    -
    13061#define ETH_MACFCR_PLT_Minus144_Pos (5U)
    -
    13062#define ETH_MACFCR_PLT_Minus144_Msk (0x1UL << ETH_MACFCR_PLT_Minus144_Pos)
    -
    13063#define ETH_MACFCR_PLT_Minus144 ETH_MACFCR_PLT_Minus144_Msk /* Pause time minus 144 slot times */
    -
    13064#define ETH_MACFCR_PLT_Minus256_Pos (4U)
    -
    13065#define ETH_MACFCR_PLT_Minus256_Msk (0x3UL << ETH_MACFCR_PLT_Minus256_Pos)
    -
    13066#define ETH_MACFCR_PLT_Minus256 ETH_MACFCR_PLT_Minus256_Msk /* Pause time minus 256 slot times */
    -
    13067#define ETH_MACFCR_UPFD_Pos (3U)
    -
    13068#define ETH_MACFCR_UPFD_Msk (0x1UL << ETH_MACFCR_UPFD_Pos)
    -
    13069#define ETH_MACFCR_UPFD ETH_MACFCR_UPFD_Msk /* Unicast pause frame detect */
    -
    13070#define ETH_MACFCR_RFCE_Pos (2U)
    -
    13071#define ETH_MACFCR_RFCE_Msk (0x1UL << ETH_MACFCR_RFCE_Pos)
    -
    13072#define ETH_MACFCR_RFCE ETH_MACFCR_RFCE_Msk /* Receive flow control enable */
    -
    13073#define ETH_MACFCR_TFCE_Pos (1U)
    -
    13074#define ETH_MACFCR_TFCE_Msk (0x1UL << ETH_MACFCR_TFCE_Pos)
    -
    13075#define ETH_MACFCR_TFCE ETH_MACFCR_TFCE_Msk /* Transmit flow control enable */
    -
    13076#define ETH_MACFCR_FCBBPA_Pos (0U)
    -
    13077#define ETH_MACFCR_FCBBPA_Msk (0x1UL << ETH_MACFCR_FCBBPA_Pos)
    -
    13078#define ETH_MACFCR_FCBBPA ETH_MACFCR_FCBBPA_Msk /* Flow control busy/backpressure activate */
    -
    13079
    -
    13080/* Bit definition for Ethernet MAC VLAN Tag Register */
    -
    13081#define ETH_MACVLANTR_VLANTC_Pos (16U)
    -
    13082#define ETH_MACVLANTR_VLANTC_Msk (0x1UL << ETH_MACVLANTR_VLANTC_Pos)
    -
    13083#define ETH_MACVLANTR_VLANTC ETH_MACVLANTR_VLANTC_Msk /* 12-bit VLAN tag comparison */
    -
    13084#define ETH_MACVLANTR_VLANTI_Pos (0U)
    -
    13085#define ETH_MACVLANTR_VLANTI_Msk (0xFFFFUL << ETH_MACVLANTR_VLANTI_Pos)
    -
    13086#define ETH_MACVLANTR_VLANTI ETH_MACVLANTR_VLANTI_Msk /* VLAN tag identifier (for receive frames) */
    -
    13087
    -
    13088/* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */
    -
    13089#define ETH_MACRWUFFR_D_Pos (0U)
    -
    13090#define ETH_MACRWUFFR_D_Msk (0xFFFFFFFFUL << ETH_MACRWUFFR_D_Pos)
    -
    13091#define ETH_MACRWUFFR_D ETH_MACRWUFFR_D_Msk /* Wake-up frame filter register data */
    -
    13092/* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers.
    -
    13093 Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */
    -
    13094/* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask
    -
    13095 Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask
    -
    13096 Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask
    -
    13097 Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask
    -
    13098 Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command -
    -
    13099 RSVD - Filter1 Command - RSVD - Filter0 Command
    -
    13100 Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset
    -
    13101 Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16
    -
    13102 Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */
    -
    13103
    -
    13104/* Bit definition for Ethernet MAC PMT Control and Status Register */
    -
    13105#define ETH_MACPMTCSR_WFFRPR_Pos (31U)
    -
    13106#define ETH_MACPMTCSR_WFFRPR_Msk (0x1UL << ETH_MACPMTCSR_WFFRPR_Pos)
    -
    13107#define ETH_MACPMTCSR_WFFRPR ETH_MACPMTCSR_WFFRPR_Msk /* Wake-Up Frame Filter Register Pointer Reset */
    -
    13108#define ETH_MACPMTCSR_GU_Pos (9U)
    -
    13109#define ETH_MACPMTCSR_GU_Msk (0x1UL << ETH_MACPMTCSR_GU_Pos)
    -
    13110#define ETH_MACPMTCSR_GU ETH_MACPMTCSR_GU_Msk /* Global Unicast */
    -
    13111#define ETH_MACPMTCSR_WFR_Pos (6U)
    -
    13112#define ETH_MACPMTCSR_WFR_Msk (0x1UL << ETH_MACPMTCSR_WFR_Pos)
    -
    13113#define ETH_MACPMTCSR_WFR ETH_MACPMTCSR_WFR_Msk /* Wake-Up Frame Received */
    -
    13114#define ETH_MACPMTCSR_MPR_Pos (5U)
    -
    13115#define ETH_MACPMTCSR_MPR_Msk (0x1UL << ETH_MACPMTCSR_MPR_Pos)
    -
    13116#define ETH_MACPMTCSR_MPR ETH_MACPMTCSR_MPR_Msk /* Magic Packet Received */
    -
    13117#define ETH_MACPMTCSR_WFE_Pos (2U)
    -
    13118#define ETH_MACPMTCSR_WFE_Msk (0x1UL << ETH_MACPMTCSR_WFE_Pos)
    -
    13119#define ETH_MACPMTCSR_WFE ETH_MACPMTCSR_WFE_Msk /* Wake-Up Frame Enable */
    -
    13120#define ETH_MACPMTCSR_MPE_Pos (1U)
    -
    13121#define ETH_MACPMTCSR_MPE_Msk (0x1UL << ETH_MACPMTCSR_MPE_Pos)
    -
    13122#define ETH_MACPMTCSR_MPE ETH_MACPMTCSR_MPE_Msk /* Magic Packet Enable */
    -
    13123#define ETH_MACPMTCSR_PD_Pos (0U)
    -
    13124#define ETH_MACPMTCSR_PD_Msk (0x1UL << ETH_MACPMTCSR_PD_Pos)
    -
    13125#define ETH_MACPMTCSR_PD ETH_MACPMTCSR_PD_Msk /* Power Down */
    -
    13126
    -
    13127/* Bit definition for Ethernet MAC debug Register */
    -
    13128#define ETH_MACDBGR_TFF_Pos (25U)
    -
    13129#define ETH_MACDBGR_TFF_Msk (0x1UL << ETH_MACDBGR_TFF_Pos)
    -
    13130#define ETH_MACDBGR_TFF ETH_MACDBGR_TFF_Msk /* Tx FIFO full */
    -
    13131#define ETH_MACDBGR_TFNE_Pos (24U)
    -
    13132#define ETH_MACDBGR_TFNE_Msk (0x1UL << ETH_MACDBGR_TFNE_Pos)
    -
    13133#define ETH_MACDBGR_TFNE ETH_MACDBGR_TFNE_Msk /* Tx FIFO not empty */
    -
    13134#define ETH_MACDBGR_TFWA_Pos (22U)
    -
    13135#define ETH_MACDBGR_TFWA_Msk (0x1UL << ETH_MACDBGR_TFWA_Pos)
    -
    13136#define ETH_MACDBGR_TFWA ETH_MACDBGR_TFWA_Msk /* Tx FIFO write active */
    -
    13137#define ETH_MACDBGR_TFRS_Pos (20U)
    -
    13138#define ETH_MACDBGR_TFRS_Msk (0x3UL << ETH_MACDBGR_TFRS_Pos)
    -
    13139#define ETH_MACDBGR_TFRS ETH_MACDBGR_TFRS_Msk /* Tx FIFO read status mask */
    -
    13140#define ETH_MACDBGR_TFRS_WRITING_Pos (20U)
    -
    13141#define ETH_MACDBGR_TFRS_WRITING_Msk (0x3UL << ETH_MACDBGR_TFRS_WRITING_Pos)
    -
    13142#define ETH_MACDBGR_TFRS_WRITING ETH_MACDBGR_TFRS_WRITING_Msk /* Writing the received TxStatus or flushing the TxFIFO */
    -
    13143#define ETH_MACDBGR_TFRS_WAITING_Pos (21U)
    -
    13144#define ETH_MACDBGR_TFRS_WAITING_Msk (0x1UL << ETH_MACDBGR_TFRS_WAITING_Pos)
    -
    13145#define ETH_MACDBGR_TFRS_WAITING ETH_MACDBGR_TFRS_WAITING_Msk /* Waiting for TxStatus from MAC transmitter */
    -
    13146#define ETH_MACDBGR_TFRS_READ_Pos (20U)
    -
    13147#define ETH_MACDBGR_TFRS_READ_Msk (0x1UL << ETH_MACDBGR_TFRS_READ_Pos)
    -
    13148#define ETH_MACDBGR_TFRS_READ ETH_MACDBGR_TFRS_READ_Msk /* Read state (transferring data to the MAC transmitter) */
    -
    13149#define ETH_MACDBGR_TFRS_IDLE 0x00000000U /* Idle state */
    -
    13150#define ETH_MACDBGR_MTP_Pos (19U)
    -
    13151#define ETH_MACDBGR_MTP_Msk (0x1UL << ETH_MACDBGR_MTP_Pos)
    -
    13152#define ETH_MACDBGR_MTP ETH_MACDBGR_MTP_Msk /* MAC transmitter in pause */
    -
    13153#define ETH_MACDBGR_MTFCS_Pos (17U)
    -
    13154#define ETH_MACDBGR_MTFCS_Msk (0x3UL << ETH_MACDBGR_MTFCS_Pos)
    -
    13155#define ETH_MACDBGR_MTFCS ETH_MACDBGR_MTFCS_Msk /* MAC transmit frame controller status mask */
    -
    13156#define ETH_MACDBGR_MTFCS_TRANSFERRING_Pos (17U)
    -
    13157#define ETH_MACDBGR_MTFCS_TRANSFERRING_Msk (0x3UL << ETH_MACDBGR_MTFCS_TRANSFERRING_Pos)
    -
    13158#define ETH_MACDBGR_MTFCS_TRANSFERRING ETH_MACDBGR_MTFCS_TRANSFERRING_Msk /* Transferring input frame for transmission */
    -
    13159#define ETH_MACDBGR_MTFCS_GENERATINGPCF_Pos (18U)
    -
    13160#define ETH_MACDBGR_MTFCS_GENERATINGPCF_Msk (0x1UL << ETH_MACDBGR_MTFCS_GENERATINGPCF_Pos)
    -
    13161#define ETH_MACDBGR_MTFCS_GENERATINGPCF ETH_MACDBGR_MTFCS_GENERATINGPCF_Msk /* Generating and transmitting a Pause control frame (in full duplex mode) */
    -
    13162#define ETH_MACDBGR_MTFCS_WAITING_Pos (17U)
    -
    13163#define ETH_MACDBGR_MTFCS_WAITING_Msk (0x1UL << ETH_MACDBGR_MTFCS_WAITING_Pos)
    -
    13164#define ETH_MACDBGR_MTFCS_WAITING ETH_MACDBGR_MTFCS_WAITING_Msk /* Waiting for Status of previous frame or IFG/backoff period to be over */
    -
    13165#define ETH_MACDBGR_MTFCS_IDLE 0x00000000U /* Idle */
    -
    13166#define ETH_MACDBGR_MMTEA_Pos (16U)
    -
    13167#define ETH_MACDBGR_MMTEA_Msk (0x1UL << ETH_MACDBGR_MMTEA_Pos)
    -
    13168#define ETH_MACDBGR_MMTEA ETH_MACDBGR_MMTEA_Msk /* MAC MII transmit engine active */
    -
    13169#define ETH_MACDBGR_RFFL_Pos (8U)
    -
    13170#define ETH_MACDBGR_RFFL_Msk (0x3UL << ETH_MACDBGR_RFFL_Pos)
    -
    13171#define ETH_MACDBGR_RFFL ETH_MACDBGR_RFFL_Msk /* Rx FIFO fill level mask */
    -
    13172#define ETH_MACDBGR_RFFL_FULL_Pos (8U)
    -
    13173#define ETH_MACDBGR_RFFL_FULL_Msk (0x3UL << ETH_MACDBGR_RFFL_FULL_Pos)
    -
    13174#define ETH_MACDBGR_RFFL_FULL ETH_MACDBGR_RFFL_FULL_Msk /* RxFIFO full */
    -
    13175#define ETH_MACDBGR_RFFL_ABOVEFCT_Pos (9U)
    -
    13176#define ETH_MACDBGR_RFFL_ABOVEFCT_Msk (0x1UL << ETH_MACDBGR_RFFL_ABOVEFCT_Pos)
    -
    13177#define ETH_MACDBGR_RFFL_ABOVEFCT ETH_MACDBGR_RFFL_ABOVEFCT_Msk /* RxFIFO fill-level above flow-control activate threshold */
    -
    13178#define ETH_MACDBGR_RFFL_BELOWFCT_Pos (8U)
    -
    13179#define ETH_MACDBGR_RFFL_BELOWFCT_Msk (0x1UL << ETH_MACDBGR_RFFL_BELOWFCT_Pos)
    -
    13180#define ETH_MACDBGR_RFFL_BELOWFCT ETH_MACDBGR_RFFL_BELOWFCT_Msk /* RxFIFO fill-level below flow-control de-activate threshold */
    -
    13181#define ETH_MACDBGR_RFFL_EMPTY 0x00000000U /* RxFIFO empty */
    -
    13182#define ETH_MACDBGR_RFRCS_Pos (5U)
    -
    13183#define ETH_MACDBGR_RFRCS_Msk (0x3UL << ETH_MACDBGR_RFRCS_Pos)
    -
    13184#define ETH_MACDBGR_RFRCS ETH_MACDBGR_RFRCS_Msk /* Rx FIFO read controller status mask */
    -
    13185#define ETH_MACDBGR_RFRCS_FLUSHING_Pos (5U)
    -
    13186#define ETH_MACDBGR_RFRCS_FLUSHING_Msk (0x3UL << ETH_MACDBGR_RFRCS_FLUSHING_Pos)
    -
    13187#define ETH_MACDBGR_RFRCS_FLUSHING ETH_MACDBGR_RFRCS_FLUSHING_Msk /* Flushing the frame data and status */
    -
    13188#define ETH_MACDBGR_RFRCS_STATUSREADING_Pos (6U)
    -
    13189#define ETH_MACDBGR_RFRCS_STATUSREADING_Msk (0x1UL << ETH_MACDBGR_RFRCS_STATUSREADING_Pos)
    -
    13190#define ETH_MACDBGR_RFRCS_STATUSREADING ETH_MACDBGR_RFRCS_STATUSREADING_Msk /* Reading frame status (or time-stamp) */
    -
    13191#define ETH_MACDBGR_RFRCS_DATAREADING_Pos (5U)
    -
    13192#define ETH_MACDBGR_RFRCS_DATAREADING_Msk (0x1UL << ETH_MACDBGR_RFRCS_DATAREADING_Pos)
    -
    13193#define ETH_MACDBGR_RFRCS_DATAREADING ETH_MACDBGR_RFRCS_DATAREADING_Msk /* Reading frame data */
    -
    13194#define ETH_MACDBGR_RFRCS_IDLE 0x00000000U /* IDLE state */
    -
    13195#define ETH_MACDBGR_RFWRA_Pos (4U)
    -
    13196#define ETH_MACDBGR_RFWRA_Msk (0x1UL << ETH_MACDBGR_RFWRA_Pos)
    -
    13197#define ETH_MACDBGR_RFWRA ETH_MACDBGR_RFWRA_Msk /* Rx FIFO write controller active */
    -
    13198#define ETH_MACDBGR_MSFRWCS_Pos (1U)
    -
    13199#define ETH_MACDBGR_MSFRWCS_Msk (0x3UL << ETH_MACDBGR_MSFRWCS_Pos)
    -
    13200#define ETH_MACDBGR_MSFRWCS ETH_MACDBGR_MSFRWCS_Msk /* MAC small FIFO read / write controllers status mask */
    -
    13201#define ETH_MACDBGR_MSFRWCS_1 (0x2UL << ETH_MACDBGR_MSFRWCS_Pos)
    -
    13202#define ETH_MACDBGR_MSFRWCS_0 (0x1UL << ETH_MACDBGR_MSFRWCS_Pos)
    -
    13203#define ETH_MACDBGR_MMRPEA_Pos (0U)
    -
    13204#define ETH_MACDBGR_MMRPEA_Msk (0x1UL << ETH_MACDBGR_MMRPEA_Pos)
    -
    13205#define ETH_MACDBGR_MMRPEA ETH_MACDBGR_MMRPEA_Msk /* MAC MII receive protocol engine active */
    -
    13206
    -
    13207/* Bit definition for Ethernet MAC Status Register */
    -
    13208#define ETH_MACSR_TSTS_Pos (9U)
    -
    13209#define ETH_MACSR_TSTS_Msk (0x1UL << ETH_MACSR_TSTS_Pos)
    -
    13210#define ETH_MACSR_TSTS ETH_MACSR_TSTS_Msk /* Time stamp trigger status */
    -
    13211#define ETH_MACSR_MMCTS_Pos (6U)
    -
    13212#define ETH_MACSR_MMCTS_Msk (0x1UL << ETH_MACSR_MMCTS_Pos)
    -
    13213#define ETH_MACSR_MMCTS ETH_MACSR_MMCTS_Msk /* MMC transmit status */
    -
    13214#define ETH_MACSR_MMMCRS_Pos (5U)
    -
    13215#define ETH_MACSR_MMMCRS_Msk (0x1UL << ETH_MACSR_MMMCRS_Pos)
    -
    13216#define ETH_MACSR_MMMCRS ETH_MACSR_MMMCRS_Msk /* MMC receive status */
    -
    13217#define ETH_MACSR_MMCS_Pos (4U)
    -
    13218#define ETH_MACSR_MMCS_Msk (0x1UL << ETH_MACSR_MMCS_Pos)
    -
    13219#define ETH_MACSR_MMCS ETH_MACSR_MMCS_Msk /* MMC status */
    -
    13220#define ETH_MACSR_PMTS_Pos (3U)
    -
    13221#define ETH_MACSR_PMTS_Msk (0x1UL << ETH_MACSR_PMTS_Pos)
    -
    13222#define ETH_MACSR_PMTS ETH_MACSR_PMTS_Msk /* PMT status */
    -
    13223
    -
    13224/* Bit definition for Ethernet MAC Interrupt Mask Register */
    -
    13225#define ETH_MACIMR_TSTIM_Pos (9U)
    -
    13226#define ETH_MACIMR_TSTIM_Msk (0x1UL << ETH_MACIMR_TSTIM_Pos)
    -
    13227#define ETH_MACIMR_TSTIM ETH_MACIMR_TSTIM_Msk /* Time stamp trigger interrupt mask */
    -
    13228#define ETH_MACIMR_PMTIM_Pos (3U)
    -
    13229#define ETH_MACIMR_PMTIM_Msk (0x1UL << ETH_MACIMR_PMTIM_Pos)
    -
    13230#define ETH_MACIMR_PMTIM ETH_MACIMR_PMTIM_Msk /* PMT interrupt mask */
    -
    13231
    -
    13232/* Bit definition for Ethernet MAC Address0 High Register */
    -
    13233#define ETH_MACA0HR_MACA0H_Pos (0U)
    -
    13234#define ETH_MACA0HR_MACA0H_Msk (0xFFFFUL << ETH_MACA0HR_MACA0H_Pos)
    -
    13235#define ETH_MACA0HR_MACA0H ETH_MACA0HR_MACA0H_Msk /* MAC address0 high */
    -
    13236
    -
    13237/* Bit definition for Ethernet MAC Address0 Low Register */
    -
    13238#define ETH_MACA0LR_MACA0L_Pos (0U)
    -
    13239#define ETH_MACA0LR_MACA0L_Msk (0xFFFFFFFFUL << ETH_MACA0LR_MACA0L_Pos)
    -
    13240#define ETH_MACA0LR_MACA0L ETH_MACA0LR_MACA0L_Msk /* MAC address0 low */
    -
    13241
    -
    13242/* Bit definition for Ethernet MAC Address1 High Register */
    -
    13243#define ETH_MACA1HR_AE_Pos (31U)
    -
    13244#define ETH_MACA1HR_AE_Msk (0x1UL << ETH_MACA1HR_AE_Pos)
    -
    13245#define ETH_MACA1HR_AE ETH_MACA1HR_AE_Msk /* Address enable */
    -
    13246#define ETH_MACA1HR_SA_Pos (30U)
    -
    13247#define ETH_MACA1HR_SA_Msk (0x1UL << ETH_MACA1HR_SA_Pos)
    -
    13248#define ETH_MACA1HR_SA ETH_MACA1HR_SA_Msk /* Source address */
    -
    13249#define ETH_MACA1HR_MBC_Pos (24U)
    -
    13250#define ETH_MACA1HR_MBC_Msk (0x3FUL << ETH_MACA1HR_MBC_Pos)
    -
    13251#define ETH_MACA1HR_MBC ETH_MACA1HR_MBC_Msk /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
    -
    13252#define ETH_MACA1HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
    -
    13253#define ETH_MACA1HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
    -
    13254#define ETH_MACA1HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
    -
    13255#define ETH_MACA1HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
    -
    13256#define ETH_MACA1HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
    -
    13257#define ETH_MACA1HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [7:0] */
    -
    13258#define ETH_MACA1HR_MACA1H_Pos (0U)
    -
    13259#define ETH_MACA1HR_MACA1H_Msk (0xFFFFUL << ETH_MACA1HR_MACA1H_Pos)
    -
    13260#define ETH_MACA1HR_MACA1H ETH_MACA1HR_MACA1H_Msk /* MAC address1 high */
    -
    13261
    -
    13262/* Bit definition for Ethernet MAC Address1 Low Register */
    -
    13263#define ETH_MACA1LR_MACA1L_Pos (0U)
    -
    13264#define ETH_MACA1LR_MACA1L_Msk (0xFFFFFFFFUL << ETH_MACA1LR_MACA1L_Pos)
    -
    13265#define ETH_MACA1LR_MACA1L ETH_MACA1LR_MACA1L_Msk /* MAC address1 low */
    -
    13266
    -
    13267/* Bit definition for Ethernet MAC Address2 High Register */
    -
    13268#define ETH_MACA2HR_AE_Pos (31U)
    -
    13269#define ETH_MACA2HR_AE_Msk (0x1UL << ETH_MACA2HR_AE_Pos)
    -
    13270#define ETH_MACA2HR_AE ETH_MACA2HR_AE_Msk /* Address enable */
    -
    13271#define ETH_MACA2HR_SA_Pos (30U)
    -
    13272#define ETH_MACA2HR_SA_Msk (0x1UL << ETH_MACA2HR_SA_Pos)
    -
    13273#define ETH_MACA2HR_SA ETH_MACA2HR_SA_Msk /* Source address */
    -
    13274#define ETH_MACA2HR_MBC_Pos (24U)
    -
    13275#define ETH_MACA2HR_MBC_Msk (0x3FUL << ETH_MACA2HR_MBC_Pos)
    -
    13276#define ETH_MACA2HR_MBC ETH_MACA2HR_MBC_Msk /* Mask byte control */
    -
    13277#define ETH_MACA2HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
    -
    13278#define ETH_MACA2HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
    -
    13279#define ETH_MACA2HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
    -
    13280#define ETH_MACA2HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
    -
    13281#define ETH_MACA2HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
    -
    13282#define ETH_MACA2HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [70] */
    -
    13283#define ETH_MACA2HR_MACA2H_Pos (0U)
    -
    13284#define ETH_MACA2HR_MACA2H_Msk (0xFFFFUL << ETH_MACA2HR_MACA2H_Pos)
    -
    13285#define ETH_MACA2HR_MACA2H ETH_MACA2HR_MACA2H_Msk /* MAC address1 high */
    -
    13286
    -
    13287/* Bit definition for Ethernet MAC Address2 Low Register */
    -
    13288#define ETH_MACA2LR_MACA2L_Pos (0U)
    -
    13289#define ETH_MACA2LR_MACA2L_Msk (0xFFFFFFFFUL << ETH_MACA2LR_MACA2L_Pos)
    -
    13290#define ETH_MACA2LR_MACA2L ETH_MACA2LR_MACA2L_Msk /* MAC address2 low */
    -
    13291
    -
    13292/* Bit definition for Ethernet MAC Address3 High Register */
    -
    13293#define ETH_MACA3HR_AE_Pos (31U)
    -
    13294#define ETH_MACA3HR_AE_Msk (0x1UL << ETH_MACA3HR_AE_Pos)
    -
    13295#define ETH_MACA3HR_AE ETH_MACA3HR_AE_Msk /* Address enable */
    -
    13296#define ETH_MACA3HR_SA_Pos (30U)
    -
    13297#define ETH_MACA3HR_SA_Msk (0x1UL << ETH_MACA3HR_SA_Pos)
    -
    13298#define ETH_MACA3HR_SA ETH_MACA3HR_SA_Msk /* Source address */
    -
    13299#define ETH_MACA3HR_MBC_Pos (24U)
    -
    13300#define ETH_MACA3HR_MBC_Msk (0x3FUL << ETH_MACA3HR_MBC_Pos)
    -
    13301#define ETH_MACA3HR_MBC ETH_MACA3HR_MBC_Msk /* Mask byte control */
    -
    13302#define ETH_MACA3HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
    -
    13303#define ETH_MACA3HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
    -
    13304#define ETH_MACA3HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
    -
    13305#define ETH_MACA3HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
    -
    13306#define ETH_MACA3HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
    -
    13307#define ETH_MACA3HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [70] */
    -
    13308#define ETH_MACA3HR_MACA3H_Pos (0U)
    -
    13309#define ETH_MACA3HR_MACA3H_Msk (0xFFFFUL << ETH_MACA3HR_MACA3H_Pos)
    -
    13310#define ETH_MACA3HR_MACA3H ETH_MACA3HR_MACA3H_Msk /* MAC address3 high */
    -
    13311
    -
    13312/* Bit definition for Ethernet MAC Address3 Low Register */
    -
    13313#define ETH_MACA3LR_MACA3L_Pos (0U)
    -
    13314#define ETH_MACA3LR_MACA3L_Msk (0xFFFFFFFFUL << ETH_MACA3LR_MACA3L_Pos)
    -
    13315#define ETH_MACA3LR_MACA3L ETH_MACA3LR_MACA3L_Msk /* MAC address3 low */
    -
    13316
    -
    13317/******************************************************************************/
    -
    13318/* Ethernet MMC Registers bits definition */
    -
    13319/******************************************************************************/
    -
    13320
    -
    13321/* Bit definition for Ethernet MMC Control Register */
    -
    13322#define ETH_MMCCR_MCFHP_Pos (5U)
    -
    13323#define ETH_MMCCR_MCFHP_Msk (0x1UL << ETH_MMCCR_MCFHP_Pos)
    -
    13324#define ETH_MMCCR_MCFHP ETH_MMCCR_MCFHP_Msk /* MMC counter Full-Half preset */
    -
    13325#define ETH_MMCCR_MCP_Pos (4U)
    -
    13326#define ETH_MMCCR_MCP_Msk (0x1UL << ETH_MMCCR_MCP_Pos)
    -
    13327#define ETH_MMCCR_MCP ETH_MMCCR_MCP_Msk /* MMC counter preset */
    -
    13328#define ETH_MMCCR_MCF_Pos (3U)
    -
    13329#define ETH_MMCCR_MCF_Msk (0x1UL << ETH_MMCCR_MCF_Pos)
    -
    13330#define ETH_MMCCR_MCF ETH_MMCCR_MCF_Msk /* MMC Counter Freeze */
    -
    13331#define ETH_MMCCR_ROR_Pos (2U)
    -
    13332#define ETH_MMCCR_ROR_Msk (0x1UL << ETH_MMCCR_ROR_Pos)
    -
    13333#define ETH_MMCCR_ROR ETH_MMCCR_ROR_Msk /* Reset on Read */
    -
    13334#define ETH_MMCCR_CSR_Pos (1U)
    -
    13335#define ETH_MMCCR_CSR_Msk (0x1UL << ETH_MMCCR_CSR_Pos)
    -
    13336#define ETH_MMCCR_CSR ETH_MMCCR_CSR_Msk /* Counter Stop Rollover */
    -
    13337#define ETH_MMCCR_CR_Pos (0U)
    -
    13338#define ETH_MMCCR_CR_Msk (0x1UL << ETH_MMCCR_CR_Pos)
    -
    13339#define ETH_MMCCR_CR ETH_MMCCR_CR_Msk /* Counters Reset */
    -
    13340
    -
    13341/* Bit definition for Ethernet MMC Receive Interrupt Register */
    -
    13342#define ETH_MMCRIR_RGUFS_Pos (17U)
    -
    13343#define ETH_MMCRIR_RGUFS_Msk (0x1UL << ETH_MMCRIR_RGUFS_Pos)
    -
    13344#define ETH_MMCRIR_RGUFS ETH_MMCRIR_RGUFS_Msk /* Set when Rx good unicast frames counter reaches half the maximum value */
    -
    13345#define ETH_MMCRIR_RFAES_Pos (6U)
    -
    13346#define ETH_MMCRIR_RFAES_Msk (0x1UL << ETH_MMCRIR_RFAES_Pos)
    -
    13347#define ETH_MMCRIR_RFAES ETH_MMCRIR_RFAES_Msk /* Set when Rx alignment error counter reaches half the maximum value */
    -
    13348#define ETH_MMCRIR_RFCES_Pos (5U)
    -
    13349#define ETH_MMCRIR_RFCES_Msk (0x1UL << ETH_MMCRIR_RFCES_Pos)
    -
    13350#define ETH_MMCRIR_RFCES ETH_MMCRIR_RFCES_Msk /* Set when Rx crc error counter reaches half the maximum value */
    -
    13351
    -
    13352/* Bit definition for Ethernet MMC Transmit Interrupt Register */
    -
    13353#define ETH_MMCTIR_TGFS_Pos (21U)
    -
    13354#define ETH_MMCTIR_TGFS_Msk (0x1UL << ETH_MMCTIR_TGFS_Pos)
    -
    13355#define ETH_MMCTIR_TGFS ETH_MMCTIR_TGFS_Msk /* Set when Tx good frame count counter reaches half the maximum value */
    -
    13356#define ETH_MMCTIR_TGFMSCS_Pos (15U)
    -
    13357#define ETH_MMCTIR_TGFMSCS_Msk (0x1UL << ETH_MMCTIR_TGFMSCS_Pos)
    -
    13358#define ETH_MMCTIR_TGFMSCS ETH_MMCTIR_TGFMSCS_Msk /* Set when Tx good multi col counter reaches half the maximum value */
    -
    13359#define ETH_MMCTIR_TGFSCS_Pos (14U)
    -
    13360#define ETH_MMCTIR_TGFSCS_Msk (0x1UL << ETH_MMCTIR_TGFSCS_Pos)
    -
    13361#define ETH_MMCTIR_TGFSCS ETH_MMCTIR_TGFSCS_Msk /* Set when Tx good single col counter reaches half the maximum value */
    -
    13362
    -
    13363/* Bit definition for Ethernet MMC Receive Interrupt Mask Register */
    -
    13364#define ETH_MMCRIMR_RGUFM_Pos (17U)
    -
    13365#define ETH_MMCRIMR_RGUFM_Msk (0x1UL << ETH_MMCRIMR_RGUFM_Pos)
    -
    13366#define ETH_MMCRIMR_RGUFM ETH_MMCRIMR_RGUFM_Msk /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */
    -
    13367#define ETH_MMCRIMR_RFAEM_Pos (6U)
    -
    13368#define ETH_MMCRIMR_RFAEM_Msk (0x1UL << ETH_MMCRIMR_RFAEM_Pos)
    -
    13369#define ETH_MMCRIMR_RFAEM ETH_MMCRIMR_RFAEM_Msk /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */
    -
    13370#define ETH_MMCRIMR_RFCEM_Pos (5U)
    -
    13371#define ETH_MMCRIMR_RFCEM_Msk (0x1UL << ETH_MMCRIMR_RFCEM_Pos)
    -
    13372#define ETH_MMCRIMR_RFCEM ETH_MMCRIMR_RFCEM_Msk /* Mask the interrupt when Rx crc error counter reaches half the maximum value */
    -
    13373
    -
    13374/* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */
    -
    13375#define ETH_MMCTIMR_TGFM_Pos (21U)
    -
    13376#define ETH_MMCTIMR_TGFM_Msk (0x1UL << ETH_MMCTIMR_TGFM_Pos)
    -
    13377#define ETH_MMCTIMR_TGFM ETH_MMCTIMR_TGFM_Msk /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */
    -
    13378#define ETH_MMCTIMR_TGFMSCM_Pos (15U)
    -
    13379#define ETH_MMCTIMR_TGFMSCM_Msk (0x1UL << ETH_MMCTIMR_TGFMSCM_Pos)
    -
    13380#define ETH_MMCTIMR_TGFMSCM ETH_MMCTIMR_TGFMSCM_Msk /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */
    -
    13381#define ETH_MMCTIMR_TGFSCM_Pos (14U)
    -
    13382#define ETH_MMCTIMR_TGFSCM_Msk (0x1UL << ETH_MMCTIMR_TGFSCM_Pos)
    -
    13383#define ETH_MMCTIMR_TGFSCM ETH_MMCTIMR_TGFSCM_Msk /* Mask the interrupt when Tx good single col counter reaches half the maximum value */
    -
    13384
    -
    13385/* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */
    -
    13386#define ETH_MMCTGFSCCR_TGFSCC_Pos (0U)
    -
    13387#define ETH_MMCTGFSCCR_TGFSCC_Msk (0xFFFFFFFFUL << ETH_MMCTGFSCCR_TGFSCC_Pos)
    -
    13388#define ETH_MMCTGFSCCR_TGFSCC ETH_MMCTGFSCCR_TGFSCC_Msk /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */
    -
    13389
    -
    13390/* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */
    -
    13391#define ETH_MMCTGFMSCCR_TGFMSCC_Pos (0U)
    -
    13392#define ETH_MMCTGFMSCCR_TGFMSCC_Msk (0xFFFFFFFFUL << ETH_MMCTGFMSCCR_TGFMSCC_Pos)
    -
    13393#define ETH_MMCTGFMSCCR_TGFMSCC ETH_MMCTGFMSCCR_TGFMSCC_Msk /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */
    -
    13394
    -
    13395/* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */
    -
    13396#define ETH_MMCTGFCR_TGFC_Pos (0U)
    -
    13397#define ETH_MMCTGFCR_TGFC_Msk (0xFFFFFFFFUL << ETH_MMCTGFCR_TGFC_Pos)
    -
    13398#define ETH_MMCTGFCR_TGFC ETH_MMCTGFCR_TGFC_Msk /* Number of good frames transmitted. */
    -
    13399
    -
    13400/* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */
    -
    13401#define ETH_MMCRFCECR_RFCEC_Pos (0U)
    -
    13402#define ETH_MMCRFCECR_RFCEC_Msk (0xFFFFFFFFUL << ETH_MMCRFCECR_RFCEC_Pos)
    -
    13403#define ETH_MMCRFCECR_RFCEC ETH_MMCRFCECR_RFCEC_Msk /* Number of frames received with CRC error. */
    -
    13404
    -
    13405/* Bit definition for Ethernet MMC Received Frames with Alignment Error Counter Register */
    -
    13406#define ETH_MMCRFAECR_RFAEC_Pos (0U)
    -
    13407#define ETH_MMCRFAECR_RFAEC_Msk (0xFFFFFFFFUL << ETH_MMCRFAECR_RFAEC_Pos)
    -
    13408#define ETH_MMCRFAECR_RFAEC ETH_MMCRFAECR_RFAEC_Msk /* Number of frames received with alignment (dribble) error */
    -
    13409
    -
    13410/* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */
    -
    13411#define ETH_MMCRGUFCR_RGUFC_Pos (0U)
    -
    13412#define ETH_MMCRGUFCR_RGUFC_Msk (0xFFFFFFFFUL << ETH_MMCRGUFCR_RGUFC_Pos)
    -
    13413#define ETH_MMCRGUFCR_RGUFC ETH_MMCRGUFCR_RGUFC_Msk /* Number of good unicast frames received. */
    -
    13414
    -
    13415/******************************************************************************/
    -
    13416/* Ethernet PTP Registers bits definition */
    -
    13417/******************************************************************************/
    -
    13418
    -
    13419/* Bit definition for Ethernet PTP Time Stamp Control Register */
    -
    13420#define ETH_PTPTSCR_TSPFFMAE_Pos (18U)
    -
    13421#define ETH_PTPTSCR_TSPFFMAE_Msk (0x1UL << ETH_PTPTSCR_TSPFFMAE_Pos)
    -
    13422#define ETH_PTPTSCR_TSPFFMAE ETH_PTPTSCR_TSPFFMAE_Msk /* Time stamp PTP frame filtering MAC address enable */
    -
    13423#define ETH_PTPTSCR_TSCNT_Pos (16U)
    -
    13424#define ETH_PTPTSCR_TSCNT_Msk (0x3UL << ETH_PTPTSCR_TSCNT_Pos)
    -
    13425#define ETH_PTPTSCR_TSCNT ETH_PTPTSCR_TSCNT_Msk /* Time stamp clock node type */
    -
    13426#define ETH_PTPTSCR_TSSMRME_Pos (15U)
    -
    13427#define ETH_PTPTSCR_TSSMRME_Msk (0x1UL << ETH_PTPTSCR_TSSMRME_Pos)
    -
    13428#define ETH_PTPTSCR_TSSMRME ETH_PTPTSCR_TSSMRME_Msk /* Time stamp snapshot for message relevant to master enable */
    -
    13429#define ETH_PTPTSCR_TSSEME_Pos (14U)
    -
    13430#define ETH_PTPTSCR_TSSEME_Msk (0x1UL << ETH_PTPTSCR_TSSEME_Pos)
    -
    13431#define ETH_PTPTSCR_TSSEME ETH_PTPTSCR_TSSEME_Msk /* Time stamp snapshot for event message enable */
    -
    13432#define ETH_PTPTSCR_TSSIPV4FE_Pos (13U)
    -
    13433#define ETH_PTPTSCR_TSSIPV4FE_Msk (0x1UL << ETH_PTPTSCR_TSSIPV4FE_Pos)
    -
    13434#define ETH_PTPTSCR_TSSIPV4FE ETH_PTPTSCR_TSSIPV4FE_Msk /* Time stamp snapshot for IPv4 frames enable */
    -
    13435#define ETH_PTPTSCR_TSSIPV6FE_Pos (12U)
    -
    13436#define ETH_PTPTSCR_TSSIPV6FE_Msk (0x1UL << ETH_PTPTSCR_TSSIPV6FE_Pos)
    -
    13437#define ETH_PTPTSCR_TSSIPV6FE ETH_PTPTSCR_TSSIPV6FE_Msk /* Time stamp snapshot for IPv6 frames enable */
    -
    13438#define ETH_PTPTSCR_TSSPTPOEFE_Pos (11U)
    -
    13439#define ETH_PTPTSCR_TSSPTPOEFE_Msk (0x1UL << ETH_PTPTSCR_TSSPTPOEFE_Pos)
    -
    13440#define ETH_PTPTSCR_TSSPTPOEFE ETH_PTPTSCR_TSSPTPOEFE_Msk /* Time stamp snapshot for PTP over ethernet frames enable */
    -
    13441#define ETH_PTPTSCR_TSPTPPSV2E_Pos (10U)
    -
    13442#define ETH_PTPTSCR_TSPTPPSV2E_Msk (0x1UL << ETH_PTPTSCR_TSPTPPSV2E_Pos)
    -
    13443#define ETH_PTPTSCR_TSPTPPSV2E ETH_PTPTSCR_TSPTPPSV2E_Msk /* Time stamp PTP packet snooping for version2 format enable */
    -
    13444#define ETH_PTPTSCR_TSSSR_Pos (9U)
    -
    13445#define ETH_PTPTSCR_TSSSR_Msk (0x1UL << ETH_PTPTSCR_TSSSR_Pos)
    -
    13446#define ETH_PTPTSCR_TSSSR ETH_PTPTSCR_TSSSR_Msk /* Time stamp Sub-seconds rollover */
    -
    13447#define ETH_PTPTSCR_TSSARFE_Pos (8U)
    -
    13448#define ETH_PTPTSCR_TSSARFE_Msk (0x1UL << ETH_PTPTSCR_TSSARFE_Pos)
    -
    13449#define ETH_PTPTSCR_TSSARFE ETH_PTPTSCR_TSSARFE_Msk /* Time stamp snapshot for all received frames enable */
    -
    13450
    -
    13451#define ETH_PTPTSCR_TSARU_Pos (5U)
    -
    13452#define ETH_PTPTSCR_TSARU_Msk (0x1UL << ETH_PTPTSCR_TSARU_Pos)
    -
    13453#define ETH_PTPTSCR_TSARU ETH_PTPTSCR_TSARU_Msk /* Addend register update */
    -
    13454#define ETH_PTPTSCR_TSITE_Pos (4U)
    -
    13455#define ETH_PTPTSCR_TSITE_Msk (0x1UL << ETH_PTPTSCR_TSITE_Pos)
    -
    13456#define ETH_PTPTSCR_TSITE ETH_PTPTSCR_TSITE_Msk /* Time stamp interrupt trigger enable */
    -
    13457#define ETH_PTPTSCR_TSSTU_Pos (3U)
    -
    13458#define ETH_PTPTSCR_TSSTU_Msk (0x1UL << ETH_PTPTSCR_TSSTU_Pos)
    -
    13459#define ETH_PTPTSCR_TSSTU ETH_PTPTSCR_TSSTU_Msk /* Time stamp update */
    -
    13460#define ETH_PTPTSCR_TSSTI_Pos (2U)
    -
    13461#define ETH_PTPTSCR_TSSTI_Msk (0x1UL << ETH_PTPTSCR_TSSTI_Pos)
    -
    13462#define ETH_PTPTSCR_TSSTI ETH_PTPTSCR_TSSTI_Msk /* Time stamp initialize */
    -
    13463#define ETH_PTPTSCR_TSFCU_Pos (1U)
    -
    13464#define ETH_PTPTSCR_TSFCU_Msk (0x1UL << ETH_PTPTSCR_TSFCU_Pos)
    -
    13465#define ETH_PTPTSCR_TSFCU ETH_PTPTSCR_TSFCU_Msk /* Time stamp fine or coarse update */
    -
    13466#define ETH_PTPTSCR_TSE_Pos (0U)
    -
    13467#define ETH_PTPTSCR_TSE_Msk (0x1UL << ETH_PTPTSCR_TSE_Pos)
    -
    13468#define ETH_PTPTSCR_TSE ETH_PTPTSCR_TSE_Msk /* Time stamp enable */
    -
    13469
    -
    13470/* Bit definition for Ethernet PTP Sub-Second Increment Register */
    -
    13471#define ETH_PTPSSIR_STSSI_Pos (0U)
    -
    13472#define ETH_PTPSSIR_STSSI_Msk (0xFFUL << ETH_PTPSSIR_STSSI_Pos)
    -
    13473#define ETH_PTPSSIR_STSSI ETH_PTPSSIR_STSSI_Msk /* System time Sub-second increment value */
    -
    13474
    -
    13475/* Bit definition for Ethernet PTP Time Stamp High Register */
    -
    13476#define ETH_PTPTSHR_STS_Pos (0U)
    -
    13477#define ETH_PTPTSHR_STS_Msk (0xFFFFFFFFUL << ETH_PTPTSHR_STS_Pos)
    -
    13478#define ETH_PTPTSHR_STS ETH_PTPTSHR_STS_Msk /* System Time second */
    -
    13479
    -
    13480/* Bit definition for Ethernet PTP Time Stamp Low Register */
    -
    13481#define ETH_PTPTSLR_STPNS_Pos (31U)
    -
    13482#define ETH_PTPTSLR_STPNS_Msk (0x1UL << ETH_PTPTSLR_STPNS_Pos)
    -
    13483#define ETH_PTPTSLR_STPNS ETH_PTPTSLR_STPNS_Msk /* System Time Positive or negative time */
    -
    13484#define ETH_PTPTSLR_STSS_Pos (0U)
    -
    13485#define ETH_PTPTSLR_STSS_Msk (0x7FFFFFFFUL << ETH_PTPTSLR_STSS_Pos)
    -
    13486#define ETH_PTPTSLR_STSS ETH_PTPTSLR_STSS_Msk /* System Time sub-seconds */
    -
    13487
    -
    13488/* Bit definition for Ethernet PTP Time Stamp High Update Register */
    -
    13489#define ETH_PTPTSHUR_TSUS_Pos (0U)
    -
    13490#define ETH_PTPTSHUR_TSUS_Msk (0xFFFFFFFFUL << ETH_PTPTSHUR_TSUS_Pos)
    -
    13491#define ETH_PTPTSHUR_TSUS ETH_PTPTSHUR_TSUS_Msk /* Time stamp update seconds */
    -
    13492
    -
    13493/* Bit definition for Ethernet PTP Time Stamp Low Update Register */
    -
    13494#define ETH_PTPTSLUR_TSUPNS_Pos (31U)
    -
    13495#define ETH_PTPTSLUR_TSUPNS_Msk (0x1UL << ETH_PTPTSLUR_TSUPNS_Pos)
    -
    13496#define ETH_PTPTSLUR_TSUPNS ETH_PTPTSLUR_TSUPNS_Msk /* Time stamp update Positive or negative time */
    -
    13497#define ETH_PTPTSLUR_TSUSS_Pos (0U)
    -
    13498#define ETH_PTPTSLUR_TSUSS_Msk (0x7FFFFFFFUL << ETH_PTPTSLUR_TSUSS_Pos)
    -
    13499#define ETH_PTPTSLUR_TSUSS ETH_PTPTSLUR_TSUSS_Msk /* Time stamp update sub-seconds */
    -
    13500
    -
    13501/* Bit definition for Ethernet PTP Time Stamp Addend Register */
    -
    13502#define ETH_PTPTSAR_TSA_Pos (0U)
    -
    13503#define ETH_PTPTSAR_TSA_Msk (0xFFFFFFFFUL << ETH_PTPTSAR_TSA_Pos)
    -
    13504#define ETH_PTPTSAR_TSA ETH_PTPTSAR_TSA_Msk /* Time stamp addend */
    -
    13505
    -
    13506/* Bit definition for Ethernet PTP Target Time High Register */
    -
    13507#define ETH_PTPTTHR_TTSH_Pos (0U)
    -
    13508#define ETH_PTPTTHR_TTSH_Msk (0xFFFFFFFFUL << ETH_PTPTTHR_TTSH_Pos)
    -
    13509#define ETH_PTPTTHR_TTSH ETH_PTPTTHR_TTSH_Msk /* Target time stamp high */
    -
    13510
    -
    13511/* Bit definition for Ethernet PTP Target Time Low Register */
    -
    13512#define ETH_PTPTTLR_TTSL_Pos (0U)
    -
    13513#define ETH_PTPTTLR_TTSL_Msk (0xFFFFFFFFUL << ETH_PTPTTLR_TTSL_Pos)
    -
    13514#define ETH_PTPTTLR_TTSL ETH_PTPTTLR_TTSL_Msk /* Target time stamp low */
    -
    13515
    -
    13516/* Bit definition for Ethernet PTP Time Stamp Status Register */
    -
    13517#define ETH_PTPTSSR_TSTTR_Pos (5U)
    -
    13518#define ETH_PTPTSSR_TSTTR_Msk (0x1UL << ETH_PTPTSSR_TSTTR_Pos)
    -
    13519#define ETH_PTPTSSR_TSTTR ETH_PTPTSSR_TSTTR_Msk /* Time stamp target time reached */
    -
    13520#define ETH_PTPTSSR_TSSO_Pos (4U)
    -
    13521#define ETH_PTPTSSR_TSSO_Msk (0x1UL << ETH_PTPTSSR_TSSO_Pos)
    -
    13522#define ETH_PTPTSSR_TSSO ETH_PTPTSSR_TSSO_Msk /* Time stamp seconds overflow */
    -
    13523
    -
    13524/******************************************************************************/
    -
    13525/* Ethernet DMA Registers bits definition */
    -
    13526/******************************************************************************/
    -
    13527
    -
    13528/* Bit definition for Ethernet DMA Bus Mode Register */
    -
    13529#define ETH_DMABMR_MB_Pos (26U)
    -
    13530#define ETH_DMABMR_MB_Msk (0x1UL << ETH_DMABMR_MB_Pos)
    -
    13531#define ETH_DMABMR_MB ETH_DMABMR_MB_Msk /* Mixed Burst */
    -
    13532#define ETH_DMABMR_AAB_Pos (25U)
    -
    13533#define ETH_DMABMR_AAB_Msk (0x1UL << ETH_DMABMR_AAB_Pos)
    -
    13534#define ETH_DMABMR_AAB ETH_DMABMR_AAB_Msk /* Address-Aligned beats */
    -
    13535#define ETH_DMABMR_FPM_Pos (24U)
    -
    13536#define ETH_DMABMR_FPM_Msk (0x1UL << ETH_DMABMR_FPM_Pos)
    -
    13537#define ETH_DMABMR_FPM ETH_DMABMR_FPM_Msk /* 4xPBL mode */
    -
    13538#define ETH_DMABMR_USP_Pos (23U)
    -
    13539#define ETH_DMABMR_USP_Msk (0x1UL << ETH_DMABMR_USP_Pos)
    -
    13540#define ETH_DMABMR_USP ETH_DMABMR_USP_Msk /* Use separate PBL */
    -
    13541#define ETH_DMABMR_RDP_Pos (17U)
    -
    13542#define ETH_DMABMR_RDP_Msk (0x3FUL << ETH_DMABMR_RDP_Pos)
    -
    13543#define ETH_DMABMR_RDP ETH_DMABMR_RDP_Msk /* RxDMA PBL */
    -
    13544#define ETH_DMABMR_RDP_1Beat 0x00020000U /* maximum number of beats to be transferred in one RxDMA transaction is 1 */
    -
    13545#define ETH_DMABMR_RDP_2Beat 0x00040000U /* maximum number of beats to be transferred in one RxDMA transaction is 2 */
    -
    13546#define ETH_DMABMR_RDP_4Beat 0x00080000U /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
    -
    13547#define ETH_DMABMR_RDP_8Beat 0x00100000U /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
    -
    13548#define ETH_DMABMR_RDP_16Beat 0x00200000U /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
    -
    13549#define ETH_DMABMR_RDP_32Beat 0x00400000U /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
    -
    13550#define ETH_DMABMR_RDP_4xPBL_4Beat 0x01020000U /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
    -
    13551#define ETH_DMABMR_RDP_4xPBL_8Beat 0x01040000U /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
    -
    13552#define ETH_DMABMR_RDP_4xPBL_16Beat 0x01080000U /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
    -
    13553#define ETH_DMABMR_RDP_4xPBL_32Beat 0x01100000U /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
    -
    13554#define ETH_DMABMR_RDP_4xPBL_64Beat 0x01200000U /* maximum number of beats to be transferred in one RxDMA transaction is 64 */
    -
    13555#define ETH_DMABMR_RDP_4xPBL_128Beat 0x01400000U /* maximum number of beats to be transferred in one RxDMA transaction is 128 */
    -
    13556#define ETH_DMABMR_FB_Pos (16U)
    -
    13557#define ETH_DMABMR_FB_Msk (0x1UL << ETH_DMABMR_FB_Pos)
    -
    13558#define ETH_DMABMR_FB ETH_DMABMR_FB_Msk /* Fixed Burst */
    -
    13559#define ETH_DMABMR_RTPR_Pos (14U)
    -
    13560#define ETH_DMABMR_RTPR_Msk (0x3UL << ETH_DMABMR_RTPR_Pos)
    -
    13561#define ETH_DMABMR_RTPR ETH_DMABMR_RTPR_Msk /* Rx Tx priority ratio */
    -
    13562#define ETH_DMABMR_RTPR_1_1 0x00000000U /* Rx Tx priority ratio */
    -
    13563#define ETH_DMABMR_RTPR_2_1 0x00004000U /* Rx Tx priority ratio */
    -
    13564#define ETH_DMABMR_RTPR_3_1 0x00008000U /* Rx Tx priority ratio */
    -
    13565#define ETH_DMABMR_RTPR_4_1 0x0000C000U /* Rx Tx priority ratio */
    -
    13566#define ETH_DMABMR_PBL_Pos (8U)
    -
    13567#define ETH_DMABMR_PBL_Msk (0x3FUL << ETH_DMABMR_PBL_Pos)
    -
    13568#define ETH_DMABMR_PBL ETH_DMABMR_PBL_Msk /* Programmable burst length */
    -
    13569#define ETH_DMABMR_PBL_1Beat 0x00000100U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
    -
    13570#define ETH_DMABMR_PBL_2Beat 0x00000200U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
    -
    13571#define ETH_DMABMR_PBL_4Beat 0x00000400U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
    -
    13572#define ETH_DMABMR_PBL_8Beat 0x00000800U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
    -
    13573#define ETH_DMABMR_PBL_16Beat 0x00001000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
    -
    13574#define ETH_DMABMR_PBL_32Beat 0x00002000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
    -
    13575#define ETH_DMABMR_PBL_4xPBL_4Beat 0x01000100U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
    -
    13576#define ETH_DMABMR_PBL_4xPBL_8Beat 0x01000200U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
    -
    13577#define ETH_DMABMR_PBL_4xPBL_16Beat 0x01000400U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
    -
    13578#define ETH_DMABMR_PBL_4xPBL_32Beat 0x01000800U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
    -
    13579#define ETH_DMABMR_PBL_4xPBL_64Beat 0x01001000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
    -
    13580#define ETH_DMABMR_PBL_4xPBL_128Beat 0x01002000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
    -
    13581#define ETH_DMABMR_EDE_Pos (7U)
    -
    13582#define ETH_DMABMR_EDE_Msk (0x1UL << ETH_DMABMR_EDE_Pos)
    -
    13583#define ETH_DMABMR_EDE ETH_DMABMR_EDE_Msk /* Enhanced Descriptor Enable */
    -
    13584#define ETH_DMABMR_DSL_Pos (2U)
    -
    13585#define ETH_DMABMR_DSL_Msk (0x1FUL << ETH_DMABMR_DSL_Pos)
    -
    13586#define ETH_DMABMR_DSL ETH_DMABMR_DSL_Msk /* Descriptor Skip Length */
    -
    13587#define ETH_DMABMR_DA_Pos (1U)
    -
    13588#define ETH_DMABMR_DA_Msk (0x1UL << ETH_DMABMR_DA_Pos)
    -
    13589#define ETH_DMABMR_DA ETH_DMABMR_DA_Msk /* DMA arbitration scheme */
    -
    13590#define ETH_DMABMR_SR_Pos (0U)
    -
    13591#define ETH_DMABMR_SR_Msk (0x1UL << ETH_DMABMR_SR_Pos)
    -
    13592#define ETH_DMABMR_SR ETH_DMABMR_SR_Msk /* Software reset */
    -
    13593
    -
    13594/* Bit definition for Ethernet DMA Transmit Poll Demand Register */
    -
    13595#define ETH_DMATPDR_TPD_Pos (0U)
    -
    13596#define ETH_DMATPDR_TPD_Msk (0xFFFFFFFFUL << ETH_DMATPDR_TPD_Pos)
    -
    13597#define ETH_DMATPDR_TPD ETH_DMATPDR_TPD_Msk /* Transmit poll demand */
    -
    13598
    -
    13599/* Bit definition for Ethernet DMA Receive Poll Demand Register */
    -
    13600#define ETH_DMARPDR_RPD_Pos (0U)
    -
    13601#define ETH_DMARPDR_RPD_Msk (0xFFFFFFFFUL << ETH_DMARPDR_RPD_Pos)
    -
    13602#define ETH_DMARPDR_RPD ETH_DMARPDR_RPD_Msk /* Receive poll demand */
    -
    13603
    -
    13604/* Bit definition for Ethernet DMA Receive Descriptor List Address Register */
    -
    13605#define ETH_DMARDLAR_SRL_Pos (0U)
    -
    13606#define ETH_DMARDLAR_SRL_Msk (0xFFFFFFFFUL << ETH_DMARDLAR_SRL_Pos)
    -
    13607#define ETH_DMARDLAR_SRL ETH_DMARDLAR_SRL_Msk /* Start of receive list */
    -
    13608
    -
    13609/* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */
    -
    13610#define ETH_DMATDLAR_STL_Pos (0U)
    -
    13611#define ETH_DMATDLAR_STL_Msk (0xFFFFFFFFUL << ETH_DMATDLAR_STL_Pos)
    -
    13612#define ETH_DMATDLAR_STL ETH_DMATDLAR_STL_Msk /* Start of transmit list */
    -
    13613
    -
    13614/* Bit definition for Ethernet DMA Status Register */
    -
    13615#define ETH_DMASR_TSTS_Pos (29U)
    -
    13616#define ETH_DMASR_TSTS_Msk (0x1UL << ETH_DMASR_TSTS_Pos)
    -
    13617#define ETH_DMASR_TSTS ETH_DMASR_TSTS_Msk /* Time-stamp trigger status */
    -
    13618#define ETH_DMASR_PMTS_Pos (28U)
    -
    13619#define ETH_DMASR_PMTS_Msk (0x1UL << ETH_DMASR_PMTS_Pos)
    -
    13620#define ETH_DMASR_PMTS ETH_DMASR_PMTS_Msk /* PMT status */
    -
    13621#define ETH_DMASR_MMCS_Pos (27U)
    -
    13622#define ETH_DMASR_MMCS_Msk (0x1UL << ETH_DMASR_MMCS_Pos)
    -
    13623#define ETH_DMASR_MMCS ETH_DMASR_MMCS_Msk /* MMC status */
    -
    13624#define ETH_DMASR_EBS_Pos (23U)
    -
    13625#define ETH_DMASR_EBS_Msk (0x7UL << ETH_DMASR_EBS_Pos)
    -
    13626#define ETH_DMASR_EBS ETH_DMASR_EBS_Msk /* Error bits status */
    -
    13627 /* combination with EBS[2:0] for GetFlagStatus function */
    -
    13628#define ETH_DMASR_EBS_DescAccess_Pos (25U)
    -
    13629#define ETH_DMASR_EBS_DescAccess_Msk (0x1UL << ETH_DMASR_EBS_DescAccess_Pos)
    -
    13630#define ETH_DMASR_EBS_DescAccess ETH_DMASR_EBS_DescAccess_Msk /* Error bits 0-data buffer, 1-desc. access */
    -
    13631#define ETH_DMASR_EBS_ReadTransf_Pos (24U)
    -
    13632#define ETH_DMASR_EBS_ReadTransf_Msk (0x1UL << ETH_DMASR_EBS_ReadTransf_Pos)
    -
    13633#define ETH_DMASR_EBS_ReadTransf ETH_DMASR_EBS_ReadTransf_Msk /* Error bits 0-write trnsf, 1-read transfr */
    -
    13634#define ETH_DMASR_EBS_DataTransfTx_Pos (23U)
    -
    13635#define ETH_DMASR_EBS_DataTransfTx_Msk (0x1UL << ETH_DMASR_EBS_DataTransfTx_Pos)
    -
    13636#define ETH_DMASR_EBS_DataTransfTx ETH_DMASR_EBS_DataTransfTx_Msk /* Error bits 0-Rx DMA, 1-Tx DMA */
    -
    13637#define ETH_DMASR_TPS_Pos (20U)
    -
    13638#define ETH_DMASR_TPS_Msk (0x7UL << ETH_DMASR_TPS_Pos)
    -
    13639#define ETH_DMASR_TPS ETH_DMASR_TPS_Msk /* Transmit process state */
    -
    13640#define ETH_DMASR_TPS_Stopped 0x00000000U /* Stopped - Reset or Stop Tx Command issued */
    -
    13641#define ETH_DMASR_TPS_Fetching_Pos (20U)
    -
    13642#define ETH_DMASR_TPS_Fetching_Msk (0x1UL << ETH_DMASR_TPS_Fetching_Pos)
    -
    13643#define ETH_DMASR_TPS_Fetching ETH_DMASR_TPS_Fetching_Msk /* Running - fetching the Tx descriptor */
    -
    13644#define ETH_DMASR_TPS_Waiting_Pos (21U)
    -
    13645#define ETH_DMASR_TPS_Waiting_Msk (0x1UL << ETH_DMASR_TPS_Waiting_Pos)
    -
    13646#define ETH_DMASR_TPS_Waiting ETH_DMASR_TPS_Waiting_Msk /* Running - waiting for status */
    -
    13647#define ETH_DMASR_TPS_Reading_Pos (20U)
    -
    13648#define ETH_DMASR_TPS_Reading_Msk (0x3UL << ETH_DMASR_TPS_Reading_Pos)
    -
    13649#define ETH_DMASR_TPS_Reading ETH_DMASR_TPS_Reading_Msk /* Running - reading the data from host memory */
    -
    13650#define ETH_DMASR_TPS_Suspended_Pos (21U)
    -
    13651#define ETH_DMASR_TPS_Suspended_Msk (0x3UL << ETH_DMASR_TPS_Suspended_Pos)
    -
    13652#define ETH_DMASR_TPS_Suspended ETH_DMASR_TPS_Suspended_Msk /* Suspended - Tx Descriptor unavailable */
    -
    13653#define ETH_DMASR_TPS_Closing_Pos (20U)
    -
    13654#define ETH_DMASR_TPS_Closing_Msk (0x7UL << ETH_DMASR_TPS_Closing_Pos)
    -
    13655#define ETH_DMASR_TPS_Closing ETH_DMASR_TPS_Closing_Msk /* Running - closing Rx descriptor */
    -
    13656#define ETH_DMASR_RPS_Pos (17U)
    -
    13657#define ETH_DMASR_RPS_Msk (0x7UL << ETH_DMASR_RPS_Pos)
    -
    13658#define ETH_DMASR_RPS ETH_DMASR_RPS_Msk /* Receive process state */
    -
    13659#define ETH_DMASR_RPS_Stopped 0x00000000U /* Stopped - Reset or Stop Rx Command issued */
    -
    13660#define ETH_DMASR_RPS_Fetching_Pos (17U)
    -
    13661#define ETH_DMASR_RPS_Fetching_Msk (0x1UL << ETH_DMASR_RPS_Fetching_Pos)
    -
    13662#define ETH_DMASR_RPS_Fetching ETH_DMASR_RPS_Fetching_Msk /* Running - fetching the Rx descriptor */
    -
    13663#define ETH_DMASR_RPS_Waiting_Pos (17U)
    -
    13664#define ETH_DMASR_RPS_Waiting_Msk (0x3UL << ETH_DMASR_RPS_Waiting_Pos)
    -
    13665#define ETH_DMASR_RPS_Waiting ETH_DMASR_RPS_Waiting_Msk /* Running - waiting for packet */
    -
    13666#define ETH_DMASR_RPS_Suspended_Pos (19U)
    -
    13667#define ETH_DMASR_RPS_Suspended_Msk (0x1UL << ETH_DMASR_RPS_Suspended_Pos)
    -
    13668#define ETH_DMASR_RPS_Suspended ETH_DMASR_RPS_Suspended_Msk /* Suspended - Rx Descriptor unavailable */
    -
    13669#define ETH_DMASR_RPS_Closing_Pos (17U)
    -
    13670#define ETH_DMASR_RPS_Closing_Msk (0x5UL << ETH_DMASR_RPS_Closing_Pos)
    -
    13671#define ETH_DMASR_RPS_Closing ETH_DMASR_RPS_Closing_Msk /* Running - closing descriptor */
    -
    13672#define ETH_DMASR_RPS_Queuing_Pos (17U)
    -
    13673#define ETH_DMASR_RPS_Queuing_Msk (0x7UL << ETH_DMASR_RPS_Queuing_Pos)
    -
    13674#define ETH_DMASR_RPS_Queuing ETH_DMASR_RPS_Queuing_Msk /* Running - queuing the receive frame into host memory */
    -
    13675#define ETH_DMASR_NIS_Pos (16U)
    -
    13676#define ETH_DMASR_NIS_Msk (0x1UL << ETH_DMASR_NIS_Pos)
    -
    13677#define ETH_DMASR_NIS ETH_DMASR_NIS_Msk /* Normal interrupt summary */
    -
    13678#define ETH_DMASR_AIS_Pos (15U)
    -
    13679#define ETH_DMASR_AIS_Msk (0x1UL << ETH_DMASR_AIS_Pos)
    -
    13680#define ETH_DMASR_AIS ETH_DMASR_AIS_Msk /* Abnormal interrupt summary */
    -
    13681#define ETH_DMASR_ERS_Pos (14U)
    -
    13682#define ETH_DMASR_ERS_Msk (0x1UL << ETH_DMASR_ERS_Pos)
    -
    13683#define ETH_DMASR_ERS ETH_DMASR_ERS_Msk /* Early receive status */
    -
    13684#define ETH_DMASR_FBES_Pos (13U)
    -
    13685#define ETH_DMASR_FBES_Msk (0x1UL << ETH_DMASR_FBES_Pos)
    -
    13686#define ETH_DMASR_FBES ETH_DMASR_FBES_Msk /* Fatal bus error status */
    -
    13687#define ETH_DMASR_ETS_Pos (10U)
    -
    13688#define ETH_DMASR_ETS_Msk (0x1UL << ETH_DMASR_ETS_Pos)
    -
    13689#define ETH_DMASR_ETS ETH_DMASR_ETS_Msk /* Early transmit status */
    -
    13690#define ETH_DMASR_RWTS_Pos (9U)
    -
    13691#define ETH_DMASR_RWTS_Msk (0x1UL << ETH_DMASR_RWTS_Pos)
    -
    13692#define ETH_DMASR_RWTS ETH_DMASR_RWTS_Msk /* Receive watchdog timeout status */
    -
    13693#define ETH_DMASR_RPSS_Pos (8U)
    -
    13694#define ETH_DMASR_RPSS_Msk (0x1UL << ETH_DMASR_RPSS_Pos)
    -
    13695#define ETH_DMASR_RPSS ETH_DMASR_RPSS_Msk /* Receive process stopped status */
    -
    13696#define ETH_DMASR_RBUS_Pos (7U)
    -
    13697#define ETH_DMASR_RBUS_Msk (0x1UL << ETH_DMASR_RBUS_Pos)
    -
    13698#define ETH_DMASR_RBUS ETH_DMASR_RBUS_Msk /* Receive buffer unavailable status */
    -
    13699#define ETH_DMASR_RS_Pos (6U)
    -
    13700#define ETH_DMASR_RS_Msk (0x1UL << ETH_DMASR_RS_Pos)
    -
    13701#define ETH_DMASR_RS ETH_DMASR_RS_Msk /* Receive status */
    -
    13702#define ETH_DMASR_TUS_Pos (5U)
    -
    13703#define ETH_DMASR_TUS_Msk (0x1UL << ETH_DMASR_TUS_Pos)
    -
    13704#define ETH_DMASR_TUS ETH_DMASR_TUS_Msk /* Transmit underflow status */
    -
    13705#define ETH_DMASR_ROS_Pos (4U)
    -
    13706#define ETH_DMASR_ROS_Msk (0x1UL << ETH_DMASR_ROS_Pos)
    -
    13707#define ETH_DMASR_ROS ETH_DMASR_ROS_Msk /* Receive overflow status */
    -
    13708#define ETH_DMASR_TJTS_Pos (3U)
    -
    13709#define ETH_DMASR_TJTS_Msk (0x1UL << ETH_DMASR_TJTS_Pos)
    -
    13710#define ETH_DMASR_TJTS ETH_DMASR_TJTS_Msk /* Transmit jabber timeout status */
    -
    13711#define ETH_DMASR_TBUS_Pos (2U)
    -
    13712#define ETH_DMASR_TBUS_Msk (0x1UL << ETH_DMASR_TBUS_Pos)
    -
    13713#define ETH_DMASR_TBUS ETH_DMASR_TBUS_Msk /* Transmit buffer unavailable status */
    -
    13714#define ETH_DMASR_TPSS_Pos (1U)
    -
    13715#define ETH_DMASR_TPSS_Msk (0x1UL << ETH_DMASR_TPSS_Pos)
    -
    13716#define ETH_DMASR_TPSS ETH_DMASR_TPSS_Msk /* Transmit process stopped status */
    -
    13717#define ETH_DMASR_TS_Pos (0U)
    -
    13718#define ETH_DMASR_TS_Msk (0x1UL << ETH_DMASR_TS_Pos)
    -
    13719#define ETH_DMASR_TS ETH_DMASR_TS_Msk /* Transmit status */
    -
    13720
    -
    13721/* Bit definition for Ethernet DMA Operation Mode Register */
    -
    13722#define ETH_DMAOMR_DTCEFD_Pos (26U)
    -
    13723#define ETH_DMAOMR_DTCEFD_Msk (0x1UL << ETH_DMAOMR_DTCEFD_Pos)
    -
    13724#define ETH_DMAOMR_DTCEFD ETH_DMAOMR_DTCEFD_Msk /* Disable Dropping of TCP/IP checksum error frames */
    -
    13725#define ETH_DMAOMR_RSF_Pos (25U)
    -
    13726#define ETH_DMAOMR_RSF_Msk (0x1UL << ETH_DMAOMR_RSF_Pos)
    -
    13727#define ETH_DMAOMR_RSF ETH_DMAOMR_RSF_Msk /* Receive store and forward */
    -
    13728#define ETH_DMAOMR_DFRF_Pos (24U)
    -
    13729#define ETH_DMAOMR_DFRF_Msk (0x1UL << ETH_DMAOMR_DFRF_Pos)
    -
    13730#define ETH_DMAOMR_DFRF ETH_DMAOMR_DFRF_Msk /* Disable flushing of received frames */
    -
    13731#define ETH_DMAOMR_TSF_Pos (21U)
    -
    13732#define ETH_DMAOMR_TSF_Msk (0x1UL << ETH_DMAOMR_TSF_Pos)
    -
    13733#define ETH_DMAOMR_TSF ETH_DMAOMR_TSF_Msk /* Transmit store and forward */
    -
    13734#define ETH_DMAOMR_FTF_Pos (20U)
    -
    13735#define ETH_DMAOMR_FTF_Msk (0x1UL << ETH_DMAOMR_FTF_Pos)
    -
    13736#define ETH_DMAOMR_FTF ETH_DMAOMR_FTF_Msk /* Flush transmit FIFO */
    -
    13737#define ETH_DMAOMR_TTC_Pos (14U)
    -
    13738#define ETH_DMAOMR_TTC_Msk (0x7UL << ETH_DMAOMR_TTC_Pos)
    -
    13739#define ETH_DMAOMR_TTC ETH_DMAOMR_TTC_Msk /* Transmit threshold control */
    -
    13740#define ETH_DMAOMR_TTC_64Bytes 0x00000000U /* threshold level of the MTL Transmit FIFO is 64 Bytes */
    -
    13741#define ETH_DMAOMR_TTC_128Bytes 0x00004000U /* threshold level of the MTL Transmit FIFO is 128 Bytes */
    -
    13742#define ETH_DMAOMR_TTC_192Bytes 0x00008000U /* threshold level of the MTL Transmit FIFO is 192 Bytes */
    -
    13743#define ETH_DMAOMR_TTC_256Bytes 0x0000C000U /* threshold level of the MTL Transmit FIFO is 256 Bytes */
    -
    13744#define ETH_DMAOMR_TTC_40Bytes 0x00010000U /* threshold level of the MTL Transmit FIFO is 40 Bytes */
    -
    13745#define ETH_DMAOMR_TTC_32Bytes 0x00014000U /* threshold level of the MTL Transmit FIFO is 32 Bytes */
    -
    13746#define ETH_DMAOMR_TTC_24Bytes 0x00018000U /* threshold level of the MTL Transmit FIFO is 24 Bytes */
    -
    13747#define ETH_DMAOMR_TTC_16Bytes 0x0001C000U /* threshold level of the MTL Transmit FIFO is 16 Bytes */
    -
    13748#define ETH_DMAOMR_ST_Pos (13U)
    -
    13749#define ETH_DMAOMR_ST_Msk (0x1UL << ETH_DMAOMR_ST_Pos)
    -
    13750#define ETH_DMAOMR_ST ETH_DMAOMR_ST_Msk /* Start/stop transmission command */
    -
    13751#define ETH_DMAOMR_FEF_Pos (7U)
    -
    13752#define ETH_DMAOMR_FEF_Msk (0x1UL << ETH_DMAOMR_FEF_Pos)
    -
    13753#define ETH_DMAOMR_FEF ETH_DMAOMR_FEF_Msk /* Forward error frames */
    -
    13754#define ETH_DMAOMR_FUGF_Pos (6U)
    -
    13755#define ETH_DMAOMR_FUGF_Msk (0x1UL << ETH_DMAOMR_FUGF_Pos)
    -
    13756#define ETH_DMAOMR_FUGF ETH_DMAOMR_FUGF_Msk /* Forward undersized good frames */
    -
    13757#define ETH_DMAOMR_RTC_Pos (3U)
    -
    13758#define ETH_DMAOMR_RTC_Msk (0x3UL << ETH_DMAOMR_RTC_Pos)
    -
    13759#define ETH_DMAOMR_RTC ETH_DMAOMR_RTC_Msk /* receive threshold control */
    -
    13760#define ETH_DMAOMR_RTC_64Bytes 0x00000000U /* threshold level of the MTL Receive FIFO is 64 Bytes */
    -
    13761#define ETH_DMAOMR_RTC_32Bytes 0x00000008U /* threshold level of the MTL Receive FIFO is 32 Bytes */
    -
    13762#define ETH_DMAOMR_RTC_96Bytes 0x00000010U /* threshold level of the MTL Receive FIFO is 96 Bytes */
    -
    13763#define ETH_DMAOMR_RTC_128Bytes 0x00000018U /* threshold level of the MTL Receive FIFO is 128 Bytes */
    -
    13764#define ETH_DMAOMR_OSF_Pos (2U)
    -
    13765#define ETH_DMAOMR_OSF_Msk (0x1UL << ETH_DMAOMR_OSF_Pos)
    -
    13766#define ETH_DMAOMR_OSF ETH_DMAOMR_OSF_Msk /* operate on second frame */
    -
    13767#define ETH_DMAOMR_SR_Pos (1U)
    -
    13768#define ETH_DMAOMR_SR_Msk (0x1UL << ETH_DMAOMR_SR_Pos)
    -
    13769#define ETH_DMAOMR_SR ETH_DMAOMR_SR_Msk /* Start/stop receive */
    -
    13770
    -
    13771/* Bit definition for Ethernet DMA Interrupt Enable Register */
    -
    13772#define ETH_DMAIER_NISE_Pos (16U)
    -
    13773#define ETH_DMAIER_NISE_Msk (0x1UL << ETH_DMAIER_NISE_Pos)
    -
    13774#define ETH_DMAIER_NISE ETH_DMAIER_NISE_Msk /* Normal interrupt summary enable */
    -
    13775#define ETH_DMAIER_AISE_Pos (15U)
    -
    13776#define ETH_DMAIER_AISE_Msk (0x1UL << ETH_DMAIER_AISE_Pos)
    -
    13777#define ETH_DMAIER_AISE ETH_DMAIER_AISE_Msk /* Abnormal interrupt summary enable */
    -
    13778#define ETH_DMAIER_ERIE_Pos (14U)
    -
    13779#define ETH_DMAIER_ERIE_Msk (0x1UL << ETH_DMAIER_ERIE_Pos)
    -
    13780#define ETH_DMAIER_ERIE ETH_DMAIER_ERIE_Msk /* Early receive interrupt enable */
    -
    13781#define ETH_DMAIER_FBEIE_Pos (13U)
    -
    13782#define ETH_DMAIER_FBEIE_Msk (0x1UL << ETH_DMAIER_FBEIE_Pos)
    -
    13783#define ETH_DMAIER_FBEIE ETH_DMAIER_FBEIE_Msk /* Fatal bus error interrupt enable */
    -
    13784#define ETH_DMAIER_ETIE_Pos (10U)
    -
    13785#define ETH_DMAIER_ETIE_Msk (0x1UL << ETH_DMAIER_ETIE_Pos)
    -
    13786#define ETH_DMAIER_ETIE ETH_DMAIER_ETIE_Msk /* Early transmit interrupt enable */
    -
    13787#define ETH_DMAIER_RWTIE_Pos (9U)
    -
    13788#define ETH_DMAIER_RWTIE_Msk (0x1UL << ETH_DMAIER_RWTIE_Pos)
    -
    13789#define ETH_DMAIER_RWTIE ETH_DMAIER_RWTIE_Msk /* Receive watchdog timeout interrupt enable */
    -
    13790#define ETH_DMAIER_RPSIE_Pos (8U)
    -
    13791#define ETH_DMAIER_RPSIE_Msk (0x1UL << ETH_DMAIER_RPSIE_Pos)
    -
    13792#define ETH_DMAIER_RPSIE ETH_DMAIER_RPSIE_Msk /* Receive process stopped interrupt enable */
    -
    13793#define ETH_DMAIER_RBUIE_Pos (7U)
    -
    13794#define ETH_DMAIER_RBUIE_Msk (0x1UL << ETH_DMAIER_RBUIE_Pos)
    -
    13795#define ETH_DMAIER_RBUIE ETH_DMAIER_RBUIE_Msk /* Receive buffer unavailable interrupt enable */
    -
    13796#define ETH_DMAIER_RIE_Pos (6U)
    -
    13797#define ETH_DMAIER_RIE_Msk (0x1UL << ETH_DMAIER_RIE_Pos)
    -
    13798#define ETH_DMAIER_RIE ETH_DMAIER_RIE_Msk /* Receive interrupt enable */
    -
    13799#define ETH_DMAIER_TUIE_Pos (5U)
    -
    13800#define ETH_DMAIER_TUIE_Msk (0x1UL << ETH_DMAIER_TUIE_Pos)
    -
    13801#define ETH_DMAIER_TUIE ETH_DMAIER_TUIE_Msk /* Transmit Underflow interrupt enable */
    -
    13802#define ETH_DMAIER_ROIE_Pos (4U)
    -
    13803#define ETH_DMAIER_ROIE_Msk (0x1UL << ETH_DMAIER_ROIE_Pos)
    -
    13804#define ETH_DMAIER_ROIE ETH_DMAIER_ROIE_Msk /* Receive Overflow interrupt enable */
    -
    13805#define ETH_DMAIER_TJTIE_Pos (3U)
    -
    13806#define ETH_DMAIER_TJTIE_Msk (0x1UL << ETH_DMAIER_TJTIE_Pos)
    -
    13807#define ETH_DMAIER_TJTIE ETH_DMAIER_TJTIE_Msk /* Transmit jabber timeout interrupt enable */
    -
    13808#define ETH_DMAIER_TBUIE_Pos (2U)
    -
    13809#define ETH_DMAIER_TBUIE_Msk (0x1UL << ETH_DMAIER_TBUIE_Pos)
    -
    13810#define ETH_DMAIER_TBUIE ETH_DMAIER_TBUIE_Msk /* Transmit buffer unavailable interrupt enable */
    -
    13811#define ETH_DMAIER_TPSIE_Pos (1U)
    -
    13812#define ETH_DMAIER_TPSIE_Msk (0x1UL << ETH_DMAIER_TPSIE_Pos)
    -
    13813#define ETH_DMAIER_TPSIE ETH_DMAIER_TPSIE_Msk /* Transmit process stopped interrupt enable */
    -
    13814#define ETH_DMAIER_TIE_Pos (0U)
    -
    13815#define ETH_DMAIER_TIE_Msk (0x1UL << ETH_DMAIER_TIE_Pos)
    -
    13816#define ETH_DMAIER_TIE ETH_DMAIER_TIE_Msk /* Transmit interrupt enable */
    -
    13817
    -
    13818/* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */
    -
    13819#define ETH_DMAMFBOCR_OFOC_Pos (28U)
    -
    13820#define ETH_DMAMFBOCR_OFOC_Msk (0x1UL << ETH_DMAMFBOCR_OFOC_Pos)
    -
    13821#define ETH_DMAMFBOCR_OFOC ETH_DMAMFBOCR_OFOC_Msk /* Overflow bit for FIFO overflow counter */
    -
    13822#define ETH_DMAMFBOCR_MFA_Pos (17U)
    -
    13823#define ETH_DMAMFBOCR_MFA_Msk (0x7FFUL << ETH_DMAMFBOCR_MFA_Pos)
    -
    13824#define ETH_DMAMFBOCR_MFA ETH_DMAMFBOCR_MFA_Msk /* Number of frames missed by the application */
    -
    13825#define ETH_DMAMFBOCR_OMFC_Pos (16U)
    -
    13826#define ETH_DMAMFBOCR_OMFC_Msk (0x1UL << ETH_DMAMFBOCR_OMFC_Pos)
    -
    13827#define ETH_DMAMFBOCR_OMFC ETH_DMAMFBOCR_OMFC_Msk /* Overflow bit for missed frame counter */
    -
    13828#define ETH_DMAMFBOCR_MFC_Pos (0U)
    -
    13829#define ETH_DMAMFBOCR_MFC_Msk (0xFFFFUL << ETH_DMAMFBOCR_MFC_Pos)
    -
    13830#define ETH_DMAMFBOCR_MFC ETH_DMAMFBOCR_MFC_Msk /* Number of frames missed by the controller */
    -
    13831
    -
    13832/* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */
    -
    13833#define ETH_DMACHTDR_HTDAP_Pos (0U)
    -
    13834#define ETH_DMACHTDR_HTDAP_Msk (0xFFFFFFFFUL << ETH_DMACHTDR_HTDAP_Pos)
    -
    13835#define ETH_DMACHTDR_HTDAP ETH_DMACHTDR_HTDAP_Msk /* Host transmit descriptor address pointer */
    -
    13836
    -
    13837/* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */
    -
    13838#define ETH_DMACHRDR_HRDAP_Pos (0U)
    -
    13839#define ETH_DMACHRDR_HRDAP_Msk (0xFFFFFFFFUL << ETH_DMACHRDR_HRDAP_Pos)
    -
    13840#define ETH_DMACHRDR_HRDAP ETH_DMACHRDR_HRDAP_Msk /* Host receive descriptor address pointer */
    -
    13841
    -
    13842/* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */
    -
    13843#define ETH_DMACHTBAR_HTBAP_Pos (0U)
    -
    13844#define ETH_DMACHTBAR_HTBAP_Msk (0xFFFFFFFFUL << ETH_DMACHTBAR_HTBAP_Pos)
    -
    13845#define ETH_DMACHTBAR_HTBAP ETH_DMACHTBAR_HTBAP_Msk /* Host transmit buffer address pointer */
    -
    13846
    -
    13847/* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */
    -
    13848#define ETH_DMACHRBAR_HRBAP_Pos (0U)
    -
    13849#define ETH_DMACHRBAR_HRBAP_Msk (0xFFFFFFFFUL << ETH_DMACHRBAR_HRBAP_Pos)
    -
    13850#define ETH_DMACHRBAR_HRBAP ETH_DMACHRBAR_HRBAP_Msk /* Host receive buffer address pointer */
    -
    13851
    -
    13852/******************************************************************************/
    -
    13853/* */
    -
    13854/* USB_OTG */
    -
    13855/* */
    -
    13856/******************************************************************************/
    -
    13857/******************** Bit definition for USB_OTG_GOTGCTL register ***********/
    -
    13858#define USB_OTG_GOTGCTL_SRQSCS_Pos (0U)
    -
    13859#define USB_OTG_GOTGCTL_SRQSCS_Msk (0x1UL << USB_OTG_GOTGCTL_SRQSCS_Pos)
    -
    13860#define USB_OTG_GOTGCTL_SRQSCS USB_OTG_GOTGCTL_SRQSCS_Msk
    -
    13861#define USB_OTG_GOTGCTL_SRQ_Pos (1U)
    -
    13862#define USB_OTG_GOTGCTL_SRQ_Msk (0x1UL << USB_OTG_GOTGCTL_SRQ_Pos)
    -
    13863#define USB_OTG_GOTGCTL_SRQ USB_OTG_GOTGCTL_SRQ_Msk
    -
    13864#define USB_OTG_GOTGCTL_HNGSCS_Pos (8U)
    -
    13865#define USB_OTG_GOTGCTL_HNGSCS_Msk (0x1UL << USB_OTG_GOTGCTL_HNGSCS_Pos)
    -
    13866#define USB_OTG_GOTGCTL_HNGSCS USB_OTG_GOTGCTL_HNGSCS_Msk
    -
    13867#define USB_OTG_GOTGCTL_HNPRQ_Pos (9U)
    -
    13868#define USB_OTG_GOTGCTL_HNPRQ_Msk (0x1UL << USB_OTG_GOTGCTL_HNPRQ_Pos)
    -
    13869#define USB_OTG_GOTGCTL_HNPRQ USB_OTG_GOTGCTL_HNPRQ_Msk
    -
    13870#define USB_OTG_GOTGCTL_HSHNPEN_Pos (10U)
    -
    13871#define USB_OTG_GOTGCTL_HSHNPEN_Msk (0x1UL << USB_OTG_GOTGCTL_HSHNPEN_Pos)
    -
    13872#define USB_OTG_GOTGCTL_HSHNPEN USB_OTG_GOTGCTL_HSHNPEN_Msk
    -
    13873#define USB_OTG_GOTGCTL_DHNPEN_Pos (11U)
    -
    13874#define USB_OTG_GOTGCTL_DHNPEN_Msk (0x1UL << USB_OTG_GOTGCTL_DHNPEN_Pos)
    -
    13875#define USB_OTG_GOTGCTL_DHNPEN USB_OTG_GOTGCTL_DHNPEN_Msk
    -
    13876#define USB_OTG_GOTGCTL_CIDSTS_Pos (16U)
    -
    13877#define USB_OTG_GOTGCTL_CIDSTS_Msk (0x1UL << USB_OTG_GOTGCTL_CIDSTS_Pos)
    -
    13878#define USB_OTG_GOTGCTL_CIDSTS USB_OTG_GOTGCTL_CIDSTS_Msk
    -
    13879#define USB_OTG_GOTGCTL_DBCT_Pos (17U)
    -
    13880#define USB_OTG_GOTGCTL_DBCT_Msk (0x1UL << USB_OTG_GOTGCTL_DBCT_Pos)
    -
    13881#define USB_OTG_GOTGCTL_DBCT USB_OTG_GOTGCTL_DBCT_Msk
    -
    13882#define USB_OTG_GOTGCTL_ASVLD_Pos (18U)
    -
    13883#define USB_OTG_GOTGCTL_ASVLD_Msk (0x1UL << USB_OTG_GOTGCTL_ASVLD_Pos)
    -
    13884#define USB_OTG_GOTGCTL_ASVLD USB_OTG_GOTGCTL_ASVLD_Msk
    -
    13885#define USB_OTG_GOTGCTL_BSVLD_Pos (19U)
    -
    13886#define USB_OTG_GOTGCTL_BSVLD_Msk (0x1UL << USB_OTG_GOTGCTL_BSVLD_Pos)
    -
    13887#define USB_OTG_GOTGCTL_BSVLD USB_OTG_GOTGCTL_BSVLD_Msk
    -
    13889/******************** Bit definition forUSB_OTG_HCFG register ********************/
    -
    13890
    -
    13891#define USB_OTG_HCFG_FSLSPCS_Pos (0U)
    -
    13892#define USB_OTG_HCFG_FSLSPCS_Msk (0x3UL << USB_OTG_HCFG_FSLSPCS_Pos)
    -
    13893#define USB_OTG_HCFG_FSLSPCS USB_OTG_HCFG_FSLSPCS_Msk
    -
    13894#define USB_OTG_HCFG_FSLSPCS_0 (0x1UL << USB_OTG_HCFG_FSLSPCS_Pos)
    -
    13895#define USB_OTG_HCFG_FSLSPCS_1 (0x2UL << USB_OTG_HCFG_FSLSPCS_Pos)
    -
    13896#define USB_OTG_HCFG_FSLSS_Pos (2U)
    -
    13897#define USB_OTG_HCFG_FSLSS_Msk (0x1UL << USB_OTG_HCFG_FSLSS_Pos)
    -
    13898#define USB_OTG_HCFG_FSLSS USB_OTG_HCFG_FSLSS_Msk
    -
    13900/******************** Bit definition for USB_OTG_DCFG register ********************/
    -
    13901
    -
    13902#define USB_OTG_DCFG_DSPD_Pos (0U)
    -
    13903#define USB_OTG_DCFG_DSPD_Msk (0x3UL << USB_OTG_DCFG_DSPD_Pos)
    -
    13904#define USB_OTG_DCFG_DSPD USB_OTG_DCFG_DSPD_Msk
    -
    13905#define USB_OTG_DCFG_DSPD_0 (0x1UL << USB_OTG_DCFG_DSPD_Pos)
    -
    13906#define USB_OTG_DCFG_DSPD_1 (0x2UL << USB_OTG_DCFG_DSPD_Pos)
    -
    13907#define USB_OTG_DCFG_NZLSOHSK_Pos (2U)
    -
    13908#define USB_OTG_DCFG_NZLSOHSK_Msk (0x1UL << USB_OTG_DCFG_NZLSOHSK_Pos)
    -
    13909#define USB_OTG_DCFG_NZLSOHSK USB_OTG_DCFG_NZLSOHSK_Msk
    -
    13911#define USB_OTG_DCFG_DAD_Pos (4U)
    -
    13912#define USB_OTG_DCFG_DAD_Msk (0x7FUL << USB_OTG_DCFG_DAD_Pos)
    -
    13913#define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk
    -
    13914#define USB_OTG_DCFG_DAD_0 (0x01UL << USB_OTG_DCFG_DAD_Pos)
    -
    13915#define USB_OTG_DCFG_DAD_1 (0x02UL << USB_OTG_DCFG_DAD_Pos)
    -
    13916#define USB_OTG_DCFG_DAD_2 (0x04UL << USB_OTG_DCFG_DAD_Pos)
    -
    13917#define USB_OTG_DCFG_DAD_3 (0x08UL << USB_OTG_DCFG_DAD_Pos)
    -
    13918#define USB_OTG_DCFG_DAD_4 (0x10UL << USB_OTG_DCFG_DAD_Pos)
    -
    13919#define USB_OTG_DCFG_DAD_5 (0x20UL << USB_OTG_DCFG_DAD_Pos)
    -
    13920#define USB_OTG_DCFG_DAD_6 (0x40UL << USB_OTG_DCFG_DAD_Pos)
    -
    13922#define USB_OTG_DCFG_PFIVL_Pos (11U)
    -
    13923#define USB_OTG_DCFG_PFIVL_Msk (0x3UL << USB_OTG_DCFG_PFIVL_Pos)
    -
    13924#define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk
    -
    13925#define USB_OTG_DCFG_PFIVL_0 (0x1UL << USB_OTG_DCFG_PFIVL_Pos)
    -
    13926#define USB_OTG_DCFG_PFIVL_1 (0x2UL << USB_OTG_DCFG_PFIVL_Pos)
    -
    13928#define USB_OTG_DCFG_XCVRDLY_Pos (14U)
    -
    13929#define USB_OTG_DCFG_XCVRDLY_Msk (0x1UL << USB_OTG_DCFG_XCVRDLY_Pos)
    -
    13930#define USB_OTG_DCFG_XCVRDLY USB_OTG_DCFG_XCVRDLY_Msk
    -
    13932#define USB_OTG_DCFG_ERRATIM_Pos (15U)
    -
    13933#define USB_OTG_DCFG_ERRATIM_Msk (0x1UL << USB_OTG_DCFG_ERRATIM_Pos)
    -
    13934#define USB_OTG_DCFG_ERRATIM USB_OTG_DCFG_ERRATIM_Msk
    -
    13936#define USB_OTG_DCFG_PERSCHIVL_Pos (24U)
    -
    13937#define USB_OTG_DCFG_PERSCHIVL_Msk (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos)
    -
    13938#define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk
    -
    13939#define USB_OTG_DCFG_PERSCHIVL_0 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos)
    -
    13940#define USB_OTG_DCFG_PERSCHIVL_1 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos)
    -
    13942/******************** Bit definition for USB_OTG_PCGCR register ********************/
    -
    13943#define USB_OTG_PCGCR_STPPCLK_Pos (0U)
    -
    13944#define USB_OTG_PCGCR_STPPCLK_Msk (0x1UL << USB_OTG_PCGCR_STPPCLK_Pos)
    -
    13945#define USB_OTG_PCGCR_STPPCLK USB_OTG_PCGCR_STPPCLK_Msk
    -
    13946#define USB_OTG_PCGCR_GATEHCLK_Pos (1U)
    -
    13947#define USB_OTG_PCGCR_GATEHCLK_Msk (0x1UL << USB_OTG_PCGCR_GATEHCLK_Pos)
    -
    13948#define USB_OTG_PCGCR_GATEHCLK USB_OTG_PCGCR_GATEHCLK_Msk
    -
    13949#define USB_OTG_PCGCR_PHYSUSP_Pos (4U)
    -
    13950#define USB_OTG_PCGCR_PHYSUSP_Msk (0x1UL << USB_OTG_PCGCR_PHYSUSP_Pos)
    -
    13951#define USB_OTG_PCGCR_PHYSUSP USB_OTG_PCGCR_PHYSUSP_Msk
    -
    13953/******************** Bit definition for USB_OTG_GOTGINT register ********************/
    -
    13954#define USB_OTG_GOTGINT_SEDET_Pos (2U)
    -
    13955#define USB_OTG_GOTGINT_SEDET_Msk (0x1UL << USB_OTG_GOTGINT_SEDET_Pos)
    -
    13956#define USB_OTG_GOTGINT_SEDET USB_OTG_GOTGINT_SEDET_Msk
    -
    13957#define USB_OTG_GOTGINT_SRSSCHG_Pos (8U)
    -
    13958#define USB_OTG_GOTGINT_SRSSCHG_Msk (0x1UL << USB_OTG_GOTGINT_SRSSCHG_Pos)
    -
    13959#define USB_OTG_GOTGINT_SRSSCHG USB_OTG_GOTGINT_SRSSCHG_Msk
    -
    13960#define USB_OTG_GOTGINT_HNSSCHG_Pos (9U)
    -
    13961#define USB_OTG_GOTGINT_HNSSCHG_Msk (0x1UL << USB_OTG_GOTGINT_HNSSCHG_Pos)
    -
    13962#define USB_OTG_GOTGINT_HNSSCHG USB_OTG_GOTGINT_HNSSCHG_Msk
    -
    13963#define USB_OTG_GOTGINT_HNGDET_Pos (17U)
    -
    13964#define USB_OTG_GOTGINT_HNGDET_Msk (0x1UL << USB_OTG_GOTGINT_HNGDET_Pos)
    -
    13965#define USB_OTG_GOTGINT_HNGDET USB_OTG_GOTGINT_HNGDET_Msk
    -
    13966#define USB_OTG_GOTGINT_ADTOCHG_Pos (18U)
    -
    13967#define USB_OTG_GOTGINT_ADTOCHG_Msk (0x1UL << USB_OTG_GOTGINT_ADTOCHG_Pos)
    -
    13968#define USB_OTG_GOTGINT_ADTOCHG USB_OTG_GOTGINT_ADTOCHG_Msk
    -
    13969#define USB_OTG_GOTGINT_DBCDNE_Pos (19U)
    -
    13970#define USB_OTG_GOTGINT_DBCDNE_Msk (0x1UL << USB_OTG_GOTGINT_DBCDNE_Pos)
    -
    13971#define USB_OTG_GOTGINT_DBCDNE USB_OTG_GOTGINT_DBCDNE_Msk
    -
    13973/******************** Bit definition for USB_OTG_DCTL register ********************/
    -
    13974#define USB_OTG_DCTL_RWUSIG_Pos (0U)
    -
    13975#define USB_OTG_DCTL_RWUSIG_Msk (0x1UL << USB_OTG_DCTL_RWUSIG_Pos)
    -
    13976#define USB_OTG_DCTL_RWUSIG USB_OTG_DCTL_RWUSIG_Msk
    -
    13977#define USB_OTG_DCTL_SDIS_Pos (1U)
    -
    13978#define USB_OTG_DCTL_SDIS_Msk (0x1UL << USB_OTG_DCTL_SDIS_Pos)
    -
    13979#define USB_OTG_DCTL_SDIS USB_OTG_DCTL_SDIS_Msk
    -
    13980#define USB_OTG_DCTL_GINSTS_Pos (2U)
    -
    13981#define USB_OTG_DCTL_GINSTS_Msk (0x1UL << USB_OTG_DCTL_GINSTS_Pos)
    -
    13982#define USB_OTG_DCTL_GINSTS USB_OTG_DCTL_GINSTS_Msk
    -
    13983#define USB_OTG_DCTL_GONSTS_Pos (3U)
    -
    13984#define USB_OTG_DCTL_GONSTS_Msk (0x1UL << USB_OTG_DCTL_GONSTS_Pos)
    -
    13985#define USB_OTG_DCTL_GONSTS USB_OTG_DCTL_GONSTS_Msk
    -
    13987#define USB_OTG_DCTL_TCTL_Pos (4U)
    -
    13988#define USB_OTG_DCTL_TCTL_Msk (0x7UL << USB_OTG_DCTL_TCTL_Pos)
    -
    13989#define USB_OTG_DCTL_TCTL USB_OTG_DCTL_TCTL_Msk
    -
    13990#define USB_OTG_DCTL_TCTL_0 (0x1UL << USB_OTG_DCTL_TCTL_Pos)
    -
    13991#define USB_OTG_DCTL_TCTL_1 (0x2UL << USB_OTG_DCTL_TCTL_Pos)
    -
    13992#define USB_OTG_DCTL_TCTL_2 (0x4UL << USB_OTG_DCTL_TCTL_Pos)
    -
    13993#define USB_OTG_DCTL_SGINAK_Pos (7U)
    -
    13994#define USB_OTG_DCTL_SGINAK_Msk (0x1UL << USB_OTG_DCTL_SGINAK_Pos)
    -
    13995#define USB_OTG_DCTL_SGINAK USB_OTG_DCTL_SGINAK_Msk
    -
    13996#define USB_OTG_DCTL_CGINAK_Pos (8U)
    -
    13997#define USB_OTG_DCTL_CGINAK_Msk (0x1UL << USB_OTG_DCTL_CGINAK_Pos)
    -
    13998#define USB_OTG_DCTL_CGINAK USB_OTG_DCTL_CGINAK_Msk
    -
    13999#define USB_OTG_DCTL_SGONAK_Pos (9U)
    -
    14000#define USB_OTG_DCTL_SGONAK_Msk (0x1UL << USB_OTG_DCTL_SGONAK_Pos)
    -
    14001#define USB_OTG_DCTL_SGONAK USB_OTG_DCTL_SGONAK_Msk
    -
    14002#define USB_OTG_DCTL_CGONAK_Pos (10U)
    -
    14003#define USB_OTG_DCTL_CGONAK_Msk (0x1UL << USB_OTG_DCTL_CGONAK_Pos)
    -
    14004#define USB_OTG_DCTL_CGONAK USB_OTG_DCTL_CGONAK_Msk
    -
    14005#define USB_OTG_DCTL_POPRGDNE_Pos (11U)
    -
    14006#define USB_OTG_DCTL_POPRGDNE_Msk (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos)
    -
    14007#define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk
    -
    14009/******************** Bit definition for USB_OTG_HFIR register ********************/
    -
    14010#define USB_OTG_HFIR_FRIVL_Pos (0U)
    -
    14011#define USB_OTG_HFIR_FRIVL_Msk (0xFFFFUL << USB_OTG_HFIR_FRIVL_Pos)
    -
    14012#define USB_OTG_HFIR_FRIVL USB_OTG_HFIR_FRIVL_Msk
    -
    14014/******************** Bit definition for USB_OTG_HFNUM register ********************/
    -
    14015#define USB_OTG_HFNUM_FRNUM_Pos (0U)
    -
    14016#define USB_OTG_HFNUM_FRNUM_Msk (0xFFFFUL << USB_OTG_HFNUM_FRNUM_Pos)
    -
    14017#define USB_OTG_HFNUM_FRNUM USB_OTG_HFNUM_FRNUM_Msk
    -
    14018#define USB_OTG_HFNUM_FTREM_Pos (16U)
    -
    14019#define USB_OTG_HFNUM_FTREM_Msk (0xFFFFUL << USB_OTG_HFNUM_FTREM_Pos)
    -
    14020#define USB_OTG_HFNUM_FTREM USB_OTG_HFNUM_FTREM_Msk
    -
    14022/******************** Bit definition for USB_OTG_DSTS register ********************/
    -
    14023#define USB_OTG_DSTS_SUSPSTS_Pos (0U)
    -
    14024#define USB_OTG_DSTS_SUSPSTS_Msk (0x1UL << USB_OTG_DSTS_SUSPSTS_Pos)
    -
    14025#define USB_OTG_DSTS_SUSPSTS USB_OTG_DSTS_SUSPSTS_Msk
    -
    14027#define USB_OTG_DSTS_ENUMSPD_Pos (1U)
    -
    14028#define USB_OTG_DSTS_ENUMSPD_Msk (0x3UL << USB_OTG_DSTS_ENUMSPD_Pos)
    -
    14029#define USB_OTG_DSTS_ENUMSPD USB_OTG_DSTS_ENUMSPD_Msk
    -
    14030#define USB_OTG_DSTS_ENUMSPD_0 (0x1UL << USB_OTG_DSTS_ENUMSPD_Pos)
    -
    14031#define USB_OTG_DSTS_ENUMSPD_1 (0x2UL << USB_OTG_DSTS_ENUMSPD_Pos)
    -
    14032#define USB_OTG_DSTS_EERR_Pos (3U)
    -
    14033#define USB_OTG_DSTS_EERR_Msk (0x1UL << USB_OTG_DSTS_EERR_Pos)
    -
    14034#define USB_OTG_DSTS_EERR USB_OTG_DSTS_EERR_Msk
    -
    14035#define USB_OTG_DSTS_FNSOF_Pos (8U)
    -
    14036#define USB_OTG_DSTS_FNSOF_Msk (0x3FFFUL << USB_OTG_DSTS_FNSOF_Pos)
    -
    14037#define USB_OTG_DSTS_FNSOF USB_OTG_DSTS_FNSOF_Msk
    -
    14039/******************** Bit definition for USB_OTG_GAHBCFG register ********************/
    -
    14040#define USB_OTG_GAHBCFG_GINT_Pos (0U)
    -
    14041#define USB_OTG_GAHBCFG_GINT_Msk (0x1UL << USB_OTG_GAHBCFG_GINT_Pos)
    -
    14042#define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINT_Msk
    -
    14043#define USB_OTG_GAHBCFG_HBSTLEN_Pos (1U)
    -
    14044#define USB_OTG_GAHBCFG_HBSTLEN_Msk (0xFUL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
    -
    14045#define USB_OTG_GAHBCFG_HBSTLEN USB_OTG_GAHBCFG_HBSTLEN_Msk
    -
    14046#define USB_OTG_GAHBCFG_HBSTLEN_0 (0x0UL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
    -
    14047#define USB_OTG_GAHBCFG_HBSTLEN_1 (0x1UL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
    -
    14048#define USB_OTG_GAHBCFG_HBSTLEN_2 (0x3UL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
    -
    14049#define USB_OTG_GAHBCFG_HBSTLEN_3 (0x5UL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
    -
    14050#define USB_OTG_GAHBCFG_HBSTLEN_4 (0x7UL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
    -
    14051#define USB_OTG_GAHBCFG_DMAEN_Pos (5U)
    -
    14052#define USB_OTG_GAHBCFG_DMAEN_Msk (0x1UL << USB_OTG_GAHBCFG_DMAEN_Pos)
    -
    14053#define USB_OTG_GAHBCFG_DMAEN USB_OTG_GAHBCFG_DMAEN_Msk
    -
    14054#define USB_OTG_GAHBCFG_TXFELVL_Pos (7U)
    -
    14055#define USB_OTG_GAHBCFG_TXFELVL_Msk (0x1UL << USB_OTG_GAHBCFG_TXFELVL_Pos)
    -
    14056#define USB_OTG_GAHBCFG_TXFELVL USB_OTG_GAHBCFG_TXFELVL_Msk
    -
    14057#define USB_OTG_GAHBCFG_PTXFELVL_Pos (8U)
    -
    14058#define USB_OTG_GAHBCFG_PTXFELVL_Msk (0x1UL << USB_OTG_GAHBCFG_PTXFELVL_Pos)
    -
    14059#define USB_OTG_GAHBCFG_PTXFELVL USB_OTG_GAHBCFG_PTXFELVL_Msk
    -
    14061/******************** Bit definition for USB_OTG_GUSBCFG register ********************/
    -
    14062
    -
    14063#define USB_OTG_GUSBCFG_TOCAL_Pos (0U)
    -
    14064#define USB_OTG_GUSBCFG_TOCAL_Msk (0x7UL << USB_OTG_GUSBCFG_TOCAL_Pos)
    -
    14065#define USB_OTG_GUSBCFG_TOCAL USB_OTG_GUSBCFG_TOCAL_Msk
    -
    14066#define USB_OTG_GUSBCFG_TOCAL_0 (0x1UL << USB_OTG_GUSBCFG_TOCAL_Pos)
    -
    14067#define USB_OTG_GUSBCFG_TOCAL_1 (0x2UL << USB_OTG_GUSBCFG_TOCAL_Pos)
    -
    14068#define USB_OTG_GUSBCFG_TOCAL_2 (0x4UL << USB_OTG_GUSBCFG_TOCAL_Pos)
    -
    14069#define USB_OTG_GUSBCFG_PHYSEL_Pos (6U)
    -
    14070#define USB_OTG_GUSBCFG_PHYSEL_Msk (0x1UL << USB_OTG_GUSBCFG_PHYSEL_Pos)
    -
    14071#define USB_OTG_GUSBCFG_PHYSEL USB_OTG_GUSBCFG_PHYSEL_Msk
    -
    14072#define USB_OTG_GUSBCFG_SRPCAP_Pos (8U)
    -
    14073#define USB_OTG_GUSBCFG_SRPCAP_Msk (0x1UL << USB_OTG_GUSBCFG_SRPCAP_Pos)
    -
    14074#define USB_OTG_GUSBCFG_SRPCAP USB_OTG_GUSBCFG_SRPCAP_Msk
    -
    14075#define USB_OTG_GUSBCFG_HNPCAP_Pos (9U)
    -
    14076#define USB_OTG_GUSBCFG_HNPCAP_Msk (0x1UL << USB_OTG_GUSBCFG_HNPCAP_Pos)
    -
    14077#define USB_OTG_GUSBCFG_HNPCAP USB_OTG_GUSBCFG_HNPCAP_Msk
    -
    14078#define USB_OTG_GUSBCFG_TRDT_Pos (10U)
    -
    14079#define USB_OTG_GUSBCFG_TRDT_Msk (0xFUL << USB_OTG_GUSBCFG_TRDT_Pos)
    -
    14080#define USB_OTG_GUSBCFG_TRDT USB_OTG_GUSBCFG_TRDT_Msk
    -
    14081#define USB_OTG_GUSBCFG_TRDT_0 (0x1UL << USB_OTG_GUSBCFG_TRDT_Pos)
    -
    14082#define USB_OTG_GUSBCFG_TRDT_1 (0x2UL << USB_OTG_GUSBCFG_TRDT_Pos)
    -
    14083#define USB_OTG_GUSBCFG_TRDT_2 (0x4UL << USB_OTG_GUSBCFG_TRDT_Pos)
    -
    14084#define USB_OTG_GUSBCFG_TRDT_3 (0x8UL << USB_OTG_GUSBCFG_TRDT_Pos)
    -
    14085#define USB_OTG_GUSBCFG_PHYLPCS_Pos (15U)
    -
    14086#define USB_OTG_GUSBCFG_PHYLPCS_Msk (0x1UL << USB_OTG_GUSBCFG_PHYLPCS_Pos)
    -
    14087#define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPCS_Msk
    -
    14088#define USB_OTG_GUSBCFG_ULPIFSLS_Pos (17U)
    -
    14089#define USB_OTG_GUSBCFG_ULPIFSLS_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIFSLS_Pos)
    -
    14090#define USB_OTG_GUSBCFG_ULPIFSLS USB_OTG_GUSBCFG_ULPIFSLS_Msk
    -
    14091#define USB_OTG_GUSBCFG_ULPIAR_Pos (18U)
    -
    14092#define USB_OTG_GUSBCFG_ULPIAR_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIAR_Pos)
    -
    14093#define USB_OTG_GUSBCFG_ULPIAR USB_OTG_GUSBCFG_ULPIAR_Msk
    -
    14094#define USB_OTG_GUSBCFG_ULPICSM_Pos (19U)
    -
    14095#define USB_OTG_GUSBCFG_ULPICSM_Msk (0x1UL << USB_OTG_GUSBCFG_ULPICSM_Pos)
    -
    14096#define USB_OTG_GUSBCFG_ULPICSM USB_OTG_GUSBCFG_ULPICSM_Msk
    -
    14097#define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos (20U)
    -
    14098#define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos)
    -
    14099#define USB_OTG_GUSBCFG_ULPIEVBUSD USB_OTG_GUSBCFG_ULPIEVBUSD_Msk
    -
    14100#define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos (21U)
    -
    14101#define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos)
    -
    14102#define USB_OTG_GUSBCFG_ULPIEVBUSI USB_OTG_GUSBCFG_ULPIEVBUSI_Msk
    -
    14103#define USB_OTG_GUSBCFG_TSDPS_Pos (22U)
    -
    14104#define USB_OTG_GUSBCFG_TSDPS_Msk (0x1UL << USB_OTG_GUSBCFG_TSDPS_Pos)
    -
    14105#define USB_OTG_GUSBCFG_TSDPS USB_OTG_GUSBCFG_TSDPS_Msk
    -
    14106#define USB_OTG_GUSBCFG_PCCI_Pos (23U)
    -
    14107#define USB_OTG_GUSBCFG_PCCI_Msk (0x1UL << USB_OTG_GUSBCFG_PCCI_Pos)
    -
    14108#define USB_OTG_GUSBCFG_PCCI USB_OTG_GUSBCFG_PCCI_Msk
    -
    14109#define USB_OTG_GUSBCFG_PTCI_Pos (24U)
    -
    14110#define USB_OTG_GUSBCFG_PTCI_Msk (0x1UL << USB_OTG_GUSBCFG_PTCI_Pos)
    -
    14111#define USB_OTG_GUSBCFG_PTCI USB_OTG_GUSBCFG_PTCI_Msk
    -
    14112#define USB_OTG_GUSBCFG_ULPIIPD_Pos (25U)
    -
    14113#define USB_OTG_GUSBCFG_ULPIIPD_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIIPD_Pos)
    -
    14114#define USB_OTG_GUSBCFG_ULPIIPD USB_OTG_GUSBCFG_ULPIIPD_Msk
    -
    14115#define USB_OTG_GUSBCFG_FHMOD_Pos (29U)
    -
    14116#define USB_OTG_GUSBCFG_FHMOD_Msk (0x1UL << USB_OTG_GUSBCFG_FHMOD_Pos)
    -
    14117#define USB_OTG_GUSBCFG_FHMOD USB_OTG_GUSBCFG_FHMOD_Msk
    -
    14118#define USB_OTG_GUSBCFG_FDMOD_Pos (30U)
    -
    14119#define USB_OTG_GUSBCFG_FDMOD_Msk (0x1UL << USB_OTG_GUSBCFG_FDMOD_Pos)
    -
    14120#define USB_OTG_GUSBCFG_FDMOD USB_OTG_GUSBCFG_FDMOD_Msk
    -
    14121#define USB_OTG_GUSBCFG_CTXPKT_Pos (31U)
    -
    14122#define USB_OTG_GUSBCFG_CTXPKT_Msk (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos)
    -
    14123#define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk
    -
    14125/******************** Bit definition for USB_OTG_GRSTCTL register ********************/
    -
    14126#define USB_OTG_GRSTCTL_CSRST_Pos (0U)
    -
    14127#define USB_OTG_GRSTCTL_CSRST_Msk (0x1UL << USB_OTG_GRSTCTL_CSRST_Pos)
    -
    14128#define USB_OTG_GRSTCTL_CSRST USB_OTG_GRSTCTL_CSRST_Msk
    -
    14129#define USB_OTG_GRSTCTL_HSRST_Pos (1U)
    -
    14130#define USB_OTG_GRSTCTL_HSRST_Msk (0x1UL << USB_OTG_GRSTCTL_HSRST_Pos)
    -
    14131#define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_HSRST_Msk
    -
    14132#define USB_OTG_GRSTCTL_FCRST_Pos (2U)
    -
    14133#define USB_OTG_GRSTCTL_FCRST_Msk (0x1UL << USB_OTG_GRSTCTL_FCRST_Pos)
    -
    14134#define USB_OTG_GRSTCTL_FCRST USB_OTG_GRSTCTL_FCRST_Msk
    -
    14135#define USB_OTG_GRSTCTL_RXFFLSH_Pos (4U)
    -
    14136#define USB_OTG_GRSTCTL_RXFFLSH_Msk (0x1UL << USB_OTG_GRSTCTL_RXFFLSH_Pos)
    -
    14137#define USB_OTG_GRSTCTL_RXFFLSH USB_OTG_GRSTCTL_RXFFLSH_Msk
    -
    14138#define USB_OTG_GRSTCTL_TXFFLSH_Pos (5U)
    -
    14139#define USB_OTG_GRSTCTL_TXFFLSH_Msk (0x1UL << USB_OTG_GRSTCTL_TXFFLSH_Pos)
    -
    14140#define USB_OTG_GRSTCTL_TXFFLSH USB_OTG_GRSTCTL_TXFFLSH_Msk
    -
    14143#define USB_OTG_GRSTCTL_TXFNUM_Pos (6U)
    -
    14144#define USB_OTG_GRSTCTL_TXFNUM_Msk (0x1FUL << USB_OTG_GRSTCTL_TXFNUM_Pos)
    -
    14145#define USB_OTG_GRSTCTL_TXFNUM USB_OTG_GRSTCTL_TXFNUM_Msk
    -
    14146#define USB_OTG_GRSTCTL_TXFNUM_0 (0x01UL << USB_OTG_GRSTCTL_TXFNUM_Pos)
    -
    14147#define USB_OTG_GRSTCTL_TXFNUM_1 (0x02UL << USB_OTG_GRSTCTL_TXFNUM_Pos)
    -
    14148#define USB_OTG_GRSTCTL_TXFNUM_2 (0x04UL << USB_OTG_GRSTCTL_TXFNUM_Pos)
    -
    14149#define USB_OTG_GRSTCTL_TXFNUM_3 (0x08UL << USB_OTG_GRSTCTL_TXFNUM_Pos)
    -
    14150#define USB_OTG_GRSTCTL_TXFNUM_4 (0x10UL << USB_OTG_GRSTCTL_TXFNUM_Pos)
    -
    14151#define USB_OTG_GRSTCTL_DMAREQ_Pos (30U)
    -
    14152#define USB_OTG_GRSTCTL_DMAREQ_Msk (0x1UL << USB_OTG_GRSTCTL_DMAREQ_Pos)
    -
    14153#define USB_OTG_GRSTCTL_DMAREQ USB_OTG_GRSTCTL_DMAREQ_Msk
    -
    14154#define USB_OTG_GRSTCTL_AHBIDL_Pos (31U)
    -
    14155#define USB_OTG_GRSTCTL_AHBIDL_Msk (0x1UL << USB_OTG_GRSTCTL_AHBIDL_Pos)
    -
    14156#define USB_OTG_GRSTCTL_AHBIDL USB_OTG_GRSTCTL_AHBIDL_Msk
    -
    14158/******************** Bit definition for USB_OTG_DIEPMSK register ********************/
    -
    14159#define USB_OTG_DIEPMSK_XFRCM_Pos (0U)
    -
    14160#define USB_OTG_DIEPMSK_XFRCM_Msk (0x1UL << USB_OTG_DIEPMSK_XFRCM_Pos)
    -
    14161#define USB_OTG_DIEPMSK_XFRCM USB_OTG_DIEPMSK_XFRCM_Msk
    -
    14162#define USB_OTG_DIEPMSK_EPDM_Pos (1U)
    -
    14163#define USB_OTG_DIEPMSK_EPDM_Msk (0x1UL << USB_OTG_DIEPMSK_EPDM_Pos)
    -
    14164#define USB_OTG_DIEPMSK_EPDM USB_OTG_DIEPMSK_EPDM_Msk
    -
    14165#define USB_OTG_DIEPMSK_TOM_Pos (3U)
    -
    14166#define USB_OTG_DIEPMSK_TOM_Msk (0x1UL << USB_OTG_DIEPMSK_TOM_Pos)
    -
    14167#define USB_OTG_DIEPMSK_TOM USB_OTG_DIEPMSK_TOM_Msk
    -
    14168#define USB_OTG_DIEPMSK_ITTXFEMSK_Pos (4U)
    -
    14169#define USB_OTG_DIEPMSK_ITTXFEMSK_Msk (0x1UL << USB_OTG_DIEPMSK_ITTXFEMSK_Pos)
    -
    14170#define USB_OTG_DIEPMSK_ITTXFEMSK USB_OTG_DIEPMSK_ITTXFEMSK_Msk
    -
    14171#define USB_OTG_DIEPMSK_INEPNMM_Pos (5U)
    -
    14172#define USB_OTG_DIEPMSK_INEPNMM_Msk (0x1UL << USB_OTG_DIEPMSK_INEPNMM_Pos)
    -
    14173#define USB_OTG_DIEPMSK_INEPNMM USB_OTG_DIEPMSK_INEPNMM_Msk
    -
    14174#define USB_OTG_DIEPMSK_INEPNEM_Pos (6U)
    -
    14175#define USB_OTG_DIEPMSK_INEPNEM_Msk (0x1UL << USB_OTG_DIEPMSK_INEPNEM_Pos)
    -
    14176#define USB_OTG_DIEPMSK_INEPNEM USB_OTG_DIEPMSK_INEPNEM_Msk
    -
    14177#define USB_OTG_DIEPMSK_TXFURM_Pos (8U)
    -
    14178#define USB_OTG_DIEPMSK_TXFURM_Msk (0x1UL << USB_OTG_DIEPMSK_TXFURM_Pos)
    -
    14179#define USB_OTG_DIEPMSK_TXFURM USB_OTG_DIEPMSK_TXFURM_Msk
    -
    14180#define USB_OTG_DIEPMSK_BIM_Pos (9U)
    -
    14181#define USB_OTG_DIEPMSK_BIM_Msk (0x1UL << USB_OTG_DIEPMSK_BIM_Pos)
    -
    14182#define USB_OTG_DIEPMSK_BIM USB_OTG_DIEPMSK_BIM_Msk
    -
    14184/******************** Bit definition for USB_OTG_HPTXSTS register ********************/
    -
    14185#define USB_OTG_HPTXSTS_PTXFSAVL_Pos (0U)
    -
    14186#define USB_OTG_HPTXSTS_PTXFSAVL_Msk (0xFFFFUL << USB_OTG_HPTXSTS_PTXFSAVL_Pos)
    -
    14187#define USB_OTG_HPTXSTS_PTXFSAVL USB_OTG_HPTXSTS_PTXFSAVL_Msk
    -
    14188#define USB_OTG_HPTXSTS_PTXQSAV_Pos (16U)
    -
    14189#define USB_OTG_HPTXSTS_PTXQSAV_Msk (0xFFUL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
    -
    14190#define USB_OTG_HPTXSTS_PTXQSAV USB_OTG_HPTXSTS_PTXQSAV_Msk
    -
    14191#define USB_OTG_HPTXSTS_PTXQSAV_0 (0x01UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
    -
    14192#define USB_OTG_HPTXSTS_PTXQSAV_1 (0x02UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
    -
    14193#define USB_OTG_HPTXSTS_PTXQSAV_2 (0x04UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
    -
    14194#define USB_OTG_HPTXSTS_PTXQSAV_3 (0x08UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
    -
    14195#define USB_OTG_HPTXSTS_PTXQSAV_4 (0x10UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
    -
    14196#define USB_OTG_HPTXSTS_PTXQSAV_5 (0x20UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
    -
    14197#define USB_OTG_HPTXSTS_PTXQSAV_6 (0x40UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
    -
    14198#define USB_OTG_HPTXSTS_PTXQSAV_7 (0x80UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
    -
    14200#define USB_OTG_HPTXSTS_PTXQTOP_Pos (24U)
    -
    14201#define USB_OTG_HPTXSTS_PTXQTOP_Msk (0xFFUL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
    -
    14202#define USB_OTG_HPTXSTS_PTXQTOP USB_OTG_HPTXSTS_PTXQTOP_Msk
    -
    14203#define USB_OTG_HPTXSTS_PTXQTOP_0 (0x01UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
    -
    14204#define USB_OTG_HPTXSTS_PTXQTOP_1 (0x02UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
    -
    14205#define USB_OTG_HPTXSTS_PTXQTOP_2 (0x04UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
    -
    14206#define USB_OTG_HPTXSTS_PTXQTOP_3 (0x08UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
    -
    14207#define USB_OTG_HPTXSTS_PTXQTOP_4 (0x10UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
    -
    14208#define USB_OTG_HPTXSTS_PTXQTOP_5 (0x20UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
    -
    14209#define USB_OTG_HPTXSTS_PTXQTOP_6 (0x40UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
    -
    14210#define USB_OTG_HPTXSTS_PTXQTOP_7 (0x80UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
    -
    14212/******************** Bit definition for USB_OTG_HAINT register ********************/
    -
    14213#define USB_OTG_HAINT_HAINT_Pos (0U)
    -
    14214#define USB_OTG_HAINT_HAINT_Msk (0xFFFFUL << USB_OTG_HAINT_HAINT_Pos)
    -
    14215#define USB_OTG_HAINT_HAINT USB_OTG_HAINT_HAINT_Msk
    -
    14217/******************** Bit definition for USB_OTG_DOEPMSK register ********************/
    -
    14218#define USB_OTG_DOEPMSK_XFRCM_Pos (0U)
    -
    14219#define USB_OTG_DOEPMSK_XFRCM_Msk (0x1UL << USB_OTG_DOEPMSK_XFRCM_Pos)
    -
    14220#define USB_OTG_DOEPMSK_XFRCM USB_OTG_DOEPMSK_XFRCM_Msk
    -
    14221#define USB_OTG_DOEPMSK_EPDM_Pos (1U)
    -
    14222#define USB_OTG_DOEPMSK_EPDM_Msk (0x1UL << USB_OTG_DOEPMSK_EPDM_Pos)
    -
    14223#define USB_OTG_DOEPMSK_EPDM USB_OTG_DOEPMSK_EPDM_Msk
    -
    14224#define USB_OTG_DOEPMSK_AHBERRM_Pos (2U)
    -
    14225#define USB_OTG_DOEPMSK_AHBERRM_Msk (0x1UL << USB_OTG_DOEPMSK_AHBERRM_Pos)
    -
    14226#define USB_OTG_DOEPMSK_AHBERRM USB_OTG_DOEPMSK_AHBERRM_Msk
    -
    14227#define USB_OTG_DOEPMSK_STUPM_Pos (3U)
    -
    14228#define USB_OTG_DOEPMSK_STUPM_Msk (0x1UL << USB_OTG_DOEPMSK_STUPM_Pos)
    -
    14229#define USB_OTG_DOEPMSK_STUPM USB_OTG_DOEPMSK_STUPM_Msk
    -
    14230#define USB_OTG_DOEPMSK_OTEPDM_Pos (4U)
    -
    14231#define USB_OTG_DOEPMSK_OTEPDM_Msk (0x1UL << USB_OTG_DOEPMSK_OTEPDM_Pos)
    -
    14232#define USB_OTG_DOEPMSK_OTEPDM USB_OTG_DOEPMSK_OTEPDM_Msk
    -
    14233#define USB_OTG_DOEPMSK_OTEPSPRM_Pos (5U)
    -
    14234#define USB_OTG_DOEPMSK_OTEPSPRM_Msk (0x1UL << USB_OTG_DOEPMSK_OTEPSPRM_Pos)
    -
    14235#define USB_OTG_DOEPMSK_OTEPSPRM USB_OTG_DOEPMSK_OTEPSPRM_Msk
    -
    14236#define USB_OTG_DOEPMSK_B2BSTUP_Pos (6U)
    -
    14237#define USB_OTG_DOEPMSK_B2BSTUP_Msk (0x1UL << USB_OTG_DOEPMSK_B2BSTUP_Pos)
    -
    14238#define USB_OTG_DOEPMSK_B2BSTUP USB_OTG_DOEPMSK_B2BSTUP_Msk
    -
    14239#define USB_OTG_DOEPMSK_OPEM_Pos (8U)
    -
    14240#define USB_OTG_DOEPMSK_OPEM_Msk (0x1UL << USB_OTG_DOEPMSK_OPEM_Pos)
    -
    14241#define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OPEM_Msk
    -
    14242#define USB_OTG_DOEPMSK_BOIM_Pos (9U)
    -
    14243#define USB_OTG_DOEPMSK_BOIM_Msk (0x1UL << USB_OTG_DOEPMSK_BOIM_Pos)
    -
    14244#define USB_OTG_DOEPMSK_BOIM USB_OTG_DOEPMSK_BOIM_Msk
    -
    14245#define USB_OTG_DOEPMSK_BERRM_Pos (12U)
    -
    14246#define USB_OTG_DOEPMSK_BERRM_Msk (0x1UL << USB_OTG_DOEPMSK_BERRM_Pos)
    -
    14247#define USB_OTG_DOEPMSK_BERRM USB_OTG_DOEPMSK_BERRM_Msk
    -
    14248#define USB_OTG_DOEPMSK_NAKM_Pos (13U)
    -
    14249#define USB_OTG_DOEPMSK_NAKM_Msk (0x1UL << USB_OTG_DOEPMSK_NAKM_Pos)
    -
    14250#define USB_OTG_DOEPMSK_NAKM USB_OTG_DOEPMSK_NAKM_Msk
    -
    14251#define USB_OTG_DOEPMSK_NYETM_Pos (14U)
    -
    14252#define USB_OTG_DOEPMSK_NYETM_Msk (0x1UL << USB_OTG_DOEPMSK_NYETM_Pos)
    -
    14253#define USB_OTG_DOEPMSK_NYETM USB_OTG_DOEPMSK_NYETM_Msk
    -
    14254/******************** Bit definition for USB_OTG_GINTSTS register ********************/
    -
    14255#define USB_OTG_GINTSTS_CMOD_Pos (0U)
    -
    14256#define USB_OTG_GINTSTS_CMOD_Msk (0x1UL << USB_OTG_GINTSTS_CMOD_Pos)
    -
    14257#define USB_OTG_GINTSTS_CMOD USB_OTG_GINTSTS_CMOD_Msk
    -
    14258#define USB_OTG_GINTSTS_MMIS_Pos (1U)
    -
    14259#define USB_OTG_GINTSTS_MMIS_Msk (0x1UL << USB_OTG_GINTSTS_MMIS_Pos)
    -
    14260#define USB_OTG_GINTSTS_MMIS USB_OTG_GINTSTS_MMIS_Msk
    -
    14261#define USB_OTG_GINTSTS_OTGINT_Pos (2U)
    -
    14262#define USB_OTG_GINTSTS_OTGINT_Msk (0x1UL << USB_OTG_GINTSTS_OTGINT_Pos)
    -
    14263#define USB_OTG_GINTSTS_OTGINT USB_OTG_GINTSTS_OTGINT_Msk
    -
    14264#define USB_OTG_GINTSTS_SOF_Pos (3U)
    -
    14265#define USB_OTG_GINTSTS_SOF_Msk (0x1UL << USB_OTG_GINTSTS_SOF_Pos)
    -
    14266#define USB_OTG_GINTSTS_SOF USB_OTG_GINTSTS_SOF_Msk
    -
    14267#define USB_OTG_GINTSTS_RXFLVL_Pos (4U)
    -
    14268#define USB_OTG_GINTSTS_RXFLVL_Msk (0x1UL << USB_OTG_GINTSTS_RXFLVL_Pos)
    -
    14269#define USB_OTG_GINTSTS_RXFLVL USB_OTG_GINTSTS_RXFLVL_Msk
    -
    14270#define USB_OTG_GINTSTS_NPTXFE_Pos (5U)
    -
    14271#define USB_OTG_GINTSTS_NPTXFE_Msk (0x1UL << USB_OTG_GINTSTS_NPTXFE_Pos)
    -
    14272#define USB_OTG_GINTSTS_NPTXFE USB_OTG_GINTSTS_NPTXFE_Msk
    -
    14273#define USB_OTG_GINTSTS_GINAKEFF_Pos (6U)
    -
    14274#define USB_OTG_GINTSTS_GINAKEFF_Msk (0x1UL << USB_OTG_GINTSTS_GINAKEFF_Pos)
    -
    14275#define USB_OTG_GINTSTS_GINAKEFF USB_OTG_GINTSTS_GINAKEFF_Msk
    -
    14276#define USB_OTG_GINTSTS_BOUTNAKEFF_Pos (7U)
    -
    14277#define USB_OTG_GINTSTS_BOUTNAKEFF_Msk (0x1UL << USB_OTG_GINTSTS_BOUTNAKEFF_Pos)
    -
    14278#define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_BOUTNAKEFF_Msk
    -
    14279#define USB_OTG_GINTSTS_ESUSP_Pos (10U)
    -
    14280#define USB_OTG_GINTSTS_ESUSP_Msk (0x1UL << USB_OTG_GINTSTS_ESUSP_Pos)
    -
    14281#define USB_OTG_GINTSTS_ESUSP USB_OTG_GINTSTS_ESUSP_Msk
    -
    14282#define USB_OTG_GINTSTS_USBSUSP_Pos (11U)
    -
    14283#define USB_OTG_GINTSTS_USBSUSP_Msk (0x1UL << USB_OTG_GINTSTS_USBSUSP_Pos)
    -
    14284#define USB_OTG_GINTSTS_USBSUSP USB_OTG_GINTSTS_USBSUSP_Msk
    -
    14285#define USB_OTG_GINTSTS_USBRST_Pos (12U)
    -
    14286#define USB_OTG_GINTSTS_USBRST_Msk (0x1UL << USB_OTG_GINTSTS_USBRST_Pos)
    -
    14287#define USB_OTG_GINTSTS_USBRST USB_OTG_GINTSTS_USBRST_Msk
    -
    14288#define USB_OTG_GINTSTS_ENUMDNE_Pos (13U)
    -
    14289#define USB_OTG_GINTSTS_ENUMDNE_Msk (0x1UL << USB_OTG_GINTSTS_ENUMDNE_Pos)
    -
    14290#define USB_OTG_GINTSTS_ENUMDNE USB_OTG_GINTSTS_ENUMDNE_Msk
    -
    14291#define USB_OTG_GINTSTS_ISOODRP_Pos (14U)
    -
    14292#define USB_OTG_GINTSTS_ISOODRP_Msk (0x1UL << USB_OTG_GINTSTS_ISOODRP_Pos)
    -
    14293#define USB_OTG_GINTSTS_ISOODRP USB_OTG_GINTSTS_ISOODRP_Msk
    -
    14294#define USB_OTG_GINTSTS_EOPF_Pos (15U)
    -
    14295#define USB_OTG_GINTSTS_EOPF_Msk (0x1UL << USB_OTG_GINTSTS_EOPF_Pos)
    -
    14296#define USB_OTG_GINTSTS_EOPF USB_OTG_GINTSTS_EOPF_Msk
    -
    14297#define USB_OTG_GINTSTS_IEPINT_Pos (18U)
    -
    14298#define USB_OTG_GINTSTS_IEPINT_Msk (0x1UL << USB_OTG_GINTSTS_IEPINT_Pos)
    -
    14299#define USB_OTG_GINTSTS_IEPINT USB_OTG_GINTSTS_IEPINT_Msk
    -
    14300#define USB_OTG_GINTSTS_OEPINT_Pos (19U)
    -
    14301#define USB_OTG_GINTSTS_OEPINT_Msk (0x1UL << USB_OTG_GINTSTS_OEPINT_Pos)
    -
    14302#define USB_OTG_GINTSTS_OEPINT USB_OTG_GINTSTS_OEPINT_Msk
    -
    14303#define USB_OTG_GINTSTS_IISOIXFR_Pos (20U)
    -
    14304#define USB_OTG_GINTSTS_IISOIXFR_Msk (0x1UL << USB_OTG_GINTSTS_IISOIXFR_Pos)
    -
    14305#define USB_OTG_GINTSTS_IISOIXFR USB_OTG_GINTSTS_IISOIXFR_Msk
    -
    14306#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos (21U)
    -
    14307#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk (0x1UL << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos)
    -
    14308#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk
    -
    14309#define USB_OTG_GINTSTS_DATAFSUSP_Pos (22U)
    -
    14310#define USB_OTG_GINTSTS_DATAFSUSP_Msk (0x1UL << USB_OTG_GINTSTS_DATAFSUSP_Pos)
    -
    14311#define USB_OTG_GINTSTS_DATAFSUSP USB_OTG_GINTSTS_DATAFSUSP_Msk
    -
    14312#define USB_OTG_GINTSTS_HPRTINT_Pos (24U)
    -
    14313#define USB_OTG_GINTSTS_HPRTINT_Msk (0x1UL << USB_OTG_GINTSTS_HPRTINT_Pos)
    -
    14314#define USB_OTG_GINTSTS_HPRTINT USB_OTG_GINTSTS_HPRTINT_Msk
    -
    14315#define USB_OTG_GINTSTS_HCINT_Pos (25U)
    -
    14316#define USB_OTG_GINTSTS_HCINT_Msk (0x1UL << USB_OTG_GINTSTS_HCINT_Pos)
    -
    14317#define USB_OTG_GINTSTS_HCINT USB_OTG_GINTSTS_HCINT_Msk
    -
    14318#define USB_OTG_GINTSTS_PTXFE_Pos (26U)
    -
    14319#define USB_OTG_GINTSTS_PTXFE_Msk (0x1UL << USB_OTG_GINTSTS_PTXFE_Pos)
    -
    14320#define USB_OTG_GINTSTS_PTXFE USB_OTG_GINTSTS_PTXFE_Msk
    -
    14321#define USB_OTG_GINTSTS_CIDSCHG_Pos (28U)
    -
    14322#define USB_OTG_GINTSTS_CIDSCHG_Msk (0x1UL << USB_OTG_GINTSTS_CIDSCHG_Pos)
    -
    14323#define USB_OTG_GINTSTS_CIDSCHG USB_OTG_GINTSTS_CIDSCHG_Msk
    -
    14324#define USB_OTG_GINTSTS_DISCINT_Pos (29U)
    -
    14325#define USB_OTG_GINTSTS_DISCINT_Msk (0x1UL << USB_OTG_GINTSTS_DISCINT_Pos)
    -
    14326#define USB_OTG_GINTSTS_DISCINT USB_OTG_GINTSTS_DISCINT_Msk
    -
    14327#define USB_OTG_GINTSTS_SRQINT_Pos (30U)
    -
    14328#define USB_OTG_GINTSTS_SRQINT_Msk (0x1UL << USB_OTG_GINTSTS_SRQINT_Pos)
    -
    14329#define USB_OTG_GINTSTS_SRQINT USB_OTG_GINTSTS_SRQINT_Msk
    -
    14330#define USB_OTG_GINTSTS_WKUINT_Pos (31U)
    -
    14331#define USB_OTG_GINTSTS_WKUINT_Msk (0x1UL << USB_OTG_GINTSTS_WKUINT_Pos)
    -
    14332#define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUINT_Msk
    -
    14334/******************** Bit definition for USB_OTG_GINTMSK register ********************/
    -
    14335#define USB_OTG_GINTMSK_MMISM_Pos (1U)
    -
    14336#define USB_OTG_GINTMSK_MMISM_Msk (0x1UL << USB_OTG_GINTMSK_MMISM_Pos)
    -
    14337#define USB_OTG_GINTMSK_MMISM USB_OTG_GINTMSK_MMISM_Msk
    -
    14338#define USB_OTG_GINTMSK_OTGINT_Pos (2U)
    -
    14339#define USB_OTG_GINTMSK_OTGINT_Msk (0x1UL << USB_OTG_GINTMSK_OTGINT_Pos)
    -
    14340#define USB_OTG_GINTMSK_OTGINT USB_OTG_GINTMSK_OTGINT_Msk
    -
    14341#define USB_OTG_GINTMSK_SOFM_Pos (3U)
    -
    14342#define USB_OTG_GINTMSK_SOFM_Msk (0x1UL << USB_OTG_GINTMSK_SOFM_Pos)
    -
    14343#define USB_OTG_GINTMSK_SOFM USB_OTG_GINTMSK_SOFM_Msk
    -
    14344#define USB_OTG_GINTMSK_RXFLVLM_Pos (4U)
    -
    14345#define USB_OTG_GINTMSK_RXFLVLM_Msk (0x1UL << USB_OTG_GINTMSK_RXFLVLM_Pos)
    -
    14346#define USB_OTG_GINTMSK_RXFLVLM USB_OTG_GINTMSK_RXFLVLM_Msk
    -
    14347#define USB_OTG_GINTMSK_NPTXFEM_Pos (5U)
    -
    14348#define USB_OTG_GINTMSK_NPTXFEM_Msk (0x1UL << USB_OTG_GINTMSK_NPTXFEM_Pos)
    -
    14349#define USB_OTG_GINTMSK_NPTXFEM USB_OTG_GINTMSK_NPTXFEM_Msk
    -
    14350#define USB_OTG_GINTMSK_GINAKEFFM_Pos (6U)
    -
    14351#define USB_OTG_GINTMSK_GINAKEFFM_Msk (0x1UL << USB_OTG_GINTMSK_GINAKEFFM_Pos)
    -
    14352#define USB_OTG_GINTMSK_GINAKEFFM USB_OTG_GINTMSK_GINAKEFFM_Msk
    -
    14353#define USB_OTG_GINTMSK_GONAKEFFM_Pos (7U)
    -
    14354#define USB_OTG_GINTMSK_GONAKEFFM_Msk (0x1UL << USB_OTG_GINTMSK_GONAKEFFM_Pos)
    -
    14355#define USB_OTG_GINTMSK_GONAKEFFM USB_OTG_GINTMSK_GONAKEFFM_Msk
    -
    14356#define USB_OTG_GINTMSK_ESUSPM_Pos (10U)
    -
    14357#define USB_OTG_GINTMSK_ESUSPM_Msk (0x1UL << USB_OTG_GINTMSK_ESUSPM_Pos)
    -
    14358#define USB_OTG_GINTMSK_ESUSPM USB_OTG_GINTMSK_ESUSPM_Msk
    -
    14359#define USB_OTG_GINTMSK_USBSUSPM_Pos (11U)
    -
    14360#define USB_OTG_GINTMSK_USBSUSPM_Msk (0x1UL << USB_OTG_GINTMSK_USBSUSPM_Pos)
    -
    14361#define USB_OTG_GINTMSK_USBSUSPM USB_OTG_GINTMSK_USBSUSPM_Msk
    -
    14362#define USB_OTG_GINTMSK_USBRST_Pos (12U)
    -
    14363#define USB_OTG_GINTMSK_USBRST_Msk (0x1UL << USB_OTG_GINTMSK_USBRST_Pos)
    -
    14364#define USB_OTG_GINTMSK_USBRST USB_OTG_GINTMSK_USBRST_Msk
    -
    14365#define USB_OTG_GINTMSK_ENUMDNEM_Pos (13U)
    -
    14366#define USB_OTG_GINTMSK_ENUMDNEM_Msk (0x1UL << USB_OTG_GINTMSK_ENUMDNEM_Pos)
    -
    14367#define USB_OTG_GINTMSK_ENUMDNEM USB_OTG_GINTMSK_ENUMDNEM_Msk
    -
    14368#define USB_OTG_GINTMSK_ISOODRPM_Pos (14U)
    -
    14369#define USB_OTG_GINTMSK_ISOODRPM_Msk (0x1UL << USB_OTG_GINTMSK_ISOODRPM_Pos)
    -
    14370#define USB_OTG_GINTMSK_ISOODRPM USB_OTG_GINTMSK_ISOODRPM_Msk
    -
    14371#define USB_OTG_GINTMSK_EOPFM_Pos (15U)
    -
    14372#define USB_OTG_GINTMSK_EOPFM_Msk (0x1UL << USB_OTG_GINTMSK_EOPFM_Pos)
    -
    14373#define USB_OTG_GINTMSK_EOPFM USB_OTG_GINTMSK_EOPFM_Msk
    -
    14374#define USB_OTG_GINTMSK_EPMISM_Pos (17U)
    -
    14375#define USB_OTG_GINTMSK_EPMISM_Msk (0x1UL << USB_OTG_GINTMSK_EPMISM_Pos)
    -
    14376#define USB_OTG_GINTMSK_EPMISM USB_OTG_GINTMSK_EPMISM_Msk
    -
    14377#define USB_OTG_GINTMSK_IEPINT_Pos (18U)
    -
    14378#define USB_OTG_GINTMSK_IEPINT_Msk (0x1UL << USB_OTG_GINTMSK_IEPINT_Pos)
    -
    14379#define USB_OTG_GINTMSK_IEPINT USB_OTG_GINTMSK_IEPINT_Msk
    -
    14380#define USB_OTG_GINTMSK_OEPINT_Pos (19U)
    -
    14381#define USB_OTG_GINTMSK_OEPINT_Msk (0x1UL << USB_OTG_GINTMSK_OEPINT_Pos)
    -
    14382#define USB_OTG_GINTMSK_OEPINT USB_OTG_GINTMSK_OEPINT_Msk
    -
    14383#define USB_OTG_GINTMSK_IISOIXFRM_Pos (20U)
    -
    14384#define USB_OTG_GINTMSK_IISOIXFRM_Msk (0x1UL << USB_OTG_GINTMSK_IISOIXFRM_Pos)
    -
    14385#define USB_OTG_GINTMSK_IISOIXFRM USB_OTG_GINTMSK_IISOIXFRM_Msk
    -
    14386#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos (21U)
    -
    14387#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk (0x1UL << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos)
    -
    14388#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk
    -
    14389#define USB_OTG_GINTMSK_FSUSPM_Pos (22U)
    -
    14390#define USB_OTG_GINTMSK_FSUSPM_Msk (0x1UL << USB_OTG_GINTMSK_FSUSPM_Pos)
    -
    14391#define USB_OTG_GINTMSK_FSUSPM USB_OTG_GINTMSK_FSUSPM_Msk
    -
    14392#define USB_OTG_GINTMSK_PRTIM_Pos (24U)
    -
    14393#define USB_OTG_GINTMSK_PRTIM_Msk (0x1UL << USB_OTG_GINTMSK_PRTIM_Pos)
    -
    14394#define USB_OTG_GINTMSK_PRTIM USB_OTG_GINTMSK_PRTIM_Msk
    -
    14395#define USB_OTG_GINTMSK_HCIM_Pos (25U)
    -
    14396#define USB_OTG_GINTMSK_HCIM_Msk (0x1UL << USB_OTG_GINTMSK_HCIM_Pos)
    -
    14397#define USB_OTG_GINTMSK_HCIM USB_OTG_GINTMSK_HCIM_Msk
    -
    14398#define USB_OTG_GINTMSK_PTXFEM_Pos (26U)
    -
    14399#define USB_OTG_GINTMSK_PTXFEM_Msk (0x1UL << USB_OTG_GINTMSK_PTXFEM_Pos)
    -
    14400#define USB_OTG_GINTMSK_PTXFEM USB_OTG_GINTMSK_PTXFEM_Msk
    -
    14401#define USB_OTG_GINTMSK_CIDSCHGM_Pos (28U)
    -
    14402#define USB_OTG_GINTMSK_CIDSCHGM_Msk (0x1UL << USB_OTG_GINTMSK_CIDSCHGM_Pos)
    -
    14403#define USB_OTG_GINTMSK_CIDSCHGM USB_OTG_GINTMSK_CIDSCHGM_Msk
    -
    14404#define USB_OTG_GINTMSK_DISCINT_Pos (29U)
    -
    14405#define USB_OTG_GINTMSK_DISCINT_Msk (0x1UL << USB_OTG_GINTMSK_DISCINT_Pos)
    -
    14406#define USB_OTG_GINTMSK_DISCINT USB_OTG_GINTMSK_DISCINT_Msk
    -
    14407#define USB_OTG_GINTMSK_SRQIM_Pos (30U)
    -
    14408#define USB_OTG_GINTMSK_SRQIM_Msk (0x1UL << USB_OTG_GINTMSK_SRQIM_Pos)
    -
    14409#define USB_OTG_GINTMSK_SRQIM USB_OTG_GINTMSK_SRQIM_Msk
    -
    14410#define USB_OTG_GINTMSK_WUIM_Pos (31U)
    -
    14411#define USB_OTG_GINTMSK_WUIM_Msk (0x1UL << USB_OTG_GINTMSK_WUIM_Pos)
    -
    14412#define USB_OTG_GINTMSK_WUIM USB_OTG_GINTMSK_WUIM_Msk
    -
    14414/******************** Bit definition for USB_OTG_DAINT register ********************/
    -
    14415#define USB_OTG_DAINT_IEPINT_Pos (0U)
    -
    14416#define USB_OTG_DAINT_IEPINT_Msk (0xFFFFUL << USB_OTG_DAINT_IEPINT_Pos)
    -
    14417#define USB_OTG_DAINT_IEPINT USB_OTG_DAINT_IEPINT_Msk
    -
    14418#define USB_OTG_DAINT_OEPINT_Pos (16U)
    -
    14419#define USB_OTG_DAINT_OEPINT_Msk (0xFFFFUL << USB_OTG_DAINT_OEPINT_Pos)
    -
    14420#define USB_OTG_DAINT_OEPINT USB_OTG_DAINT_OEPINT_Msk
    -
    14422/******************** Bit definition for USB_OTG_HAINTMSK register ********************/
    -
    14423#define USB_OTG_HAINTMSK_HAINTM_Pos (0U)
    -
    14424#define USB_OTG_HAINTMSK_HAINTM_Msk (0xFFFFUL << USB_OTG_HAINTMSK_HAINTM_Pos)
    -
    14425#define USB_OTG_HAINTMSK_HAINTM USB_OTG_HAINTMSK_HAINTM_Msk
    -
    14427/******************** Bit definition for USB_OTG_GRXSTSP register ********************/
    -
    14428#define USB_OTG_GRXSTSP_EPNUM_Pos (0U)
    -
    14429#define USB_OTG_GRXSTSP_EPNUM_Msk (0xFUL << USB_OTG_GRXSTSP_EPNUM_Pos)
    -
    14430#define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_Msk
    -
    14431#define USB_OTG_GRXSTSP_BCNT_Pos (4U)
    -
    14432#define USB_OTG_GRXSTSP_BCNT_Msk (0x7FFUL << USB_OTG_GRXSTSP_BCNT_Pos)
    -
    14433#define USB_OTG_GRXSTSP_BCNT USB_OTG_GRXSTSP_BCNT_Msk
    -
    14434#define USB_OTG_GRXSTSP_DPID_Pos (15U)
    -
    14435#define USB_OTG_GRXSTSP_DPID_Msk (0x3UL << USB_OTG_GRXSTSP_DPID_Pos)
    -
    14436#define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk
    -
    14437#define USB_OTG_GRXSTSP_PKTSTS_Pos (17U)
    -
    14438#define USB_OTG_GRXSTSP_PKTSTS_Msk (0xFUL << USB_OTG_GRXSTSP_PKTSTS_Pos)
    -
    14439#define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk
    -
    14441/******************** Bit definition for USB_OTG_DAINTMSK register ********************/
    -
    14442#define USB_OTG_DAINTMSK_IEPM_Pos (0U)
    -
    14443#define USB_OTG_DAINTMSK_IEPM_Msk (0xFFFFUL << USB_OTG_DAINTMSK_IEPM_Pos)
    -
    14444#define USB_OTG_DAINTMSK_IEPM USB_OTG_DAINTMSK_IEPM_Msk
    -
    14445#define USB_OTG_DAINTMSK_OEPM_Pos (16U)
    -
    14446#define USB_OTG_DAINTMSK_OEPM_Msk (0xFFFFUL << USB_OTG_DAINTMSK_OEPM_Pos)
    -
    14447#define USB_OTG_DAINTMSK_OEPM USB_OTG_DAINTMSK_OEPM_Msk
    -
    14449/******************** Bit definition for USB_OTG_GRXFSIZ register ********************/
    -
    14450#define USB_OTG_GRXFSIZ_RXFD_Pos (0U)
    -
    14451#define USB_OTG_GRXFSIZ_RXFD_Msk (0xFFFFUL << USB_OTG_GRXFSIZ_RXFD_Pos)
    -
    14452#define USB_OTG_GRXFSIZ_RXFD USB_OTG_GRXFSIZ_RXFD_Msk
    -
    14454/******************** Bit definition for USB_OTG_DVBUSDIS register ********************/
    -
    14455#define USB_OTG_DVBUSDIS_VBUSDT_Pos (0U)
    -
    14456#define USB_OTG_DVBUSDIS_VBUSDT_Msk (0xFFFFUL << USB_OTG_DVBUSDIS_VBUSDT_Pos)
    -
    14457#define USB_OTG_DVBUSDIS_VBUSDT USB_OTG_DVBUSDIS_VBUSDT_Msk
    -
    14459/******************** Bit definition for OTG register ********************/
    -
    14460#define USB_OTG_NPTXFSA_Pos (0U)
    -
    14461#define USB_OTG_NPTXFSA_Msk (0xFFFFUL << USB_OTG_NPTXFSA_Pos)
    -
    14462#define USB_OTG_NPTXFSA USB_OTG_NPTXFSA_Msk
    -
    14463#define USB_OTG_NPTXFD_Pos (16U)
    -
    14464#define USB_OTG_NPTXFD_Msk (0xFFFFUL << USB_OTG_NPTXFD_Pos)
    -
    14465#define USB_OTG_NPTXFD USB_OTG_NPTXFD_Msk
    -
    14466#define USB_OTG_TX0FSA_Pos (0U)
    -
    14467#define USB_OTG_TX0FSA_Msk (0xFFFFUL << USB_OTG_TX0FSA_Pos)
    -
    14468#define USB_OTG_TX0FSA USB_OTG_TX0FSA_Msk
    -
    14469#define USB_OTG_TX0FD_Pos (16U)
    -
    14470#define USB_OTG_TX0FD_Msk (0xFFFFUL << USB_OTG_TX0FD_Pos)
    -
    14471#define USB_OTG_TX0FD USB_OTG_TX0FD_Msk
    -
    14473/******************** Bit definition forUSB_OTG_DVBUSPULSE register ********************/
    -
    14474#define USB_OTG_DVBUSPULSE_DVBUSP_Pos (0U)
    -
    14475#define USB_OTG_DVBUSPULSE_DVBUSP_Msk (0xFFFUL << USB_OTG_DVBUSPULSE_DVBUSP_Pos)
    -
    14476#define USB_OTG_DVBUSPULSE_DVBUSP USB_OTG_DVBUSPULSE_DVBUSP_Msk
    -
    14478/******************** Bit definition for USB_OTG_GNPTXSTS register ********************/
    -
    14479#define USB_OTG_GNPTXSTS_NPTXFSAV_Pos (0U)
    -
    14480#define USB_OTG_GNPTXSTS_NPTXFSAV_Msk (0xFFFFUL << USB_OTG_GNPTXSTS_NPTXFSAV_Pos)
    -
    14481#define USB_OTG_GNPTXSTS_NPTXFSAV USB_OTG_GNPTXSTS_NPTXFSAV_Msk
    -
    14483#define USB_OTG_GNPTXSTS_NPTQXSAV_Pos (16U)
    -
    14484#define USB_OTG_GNPTXSTS_NPTQXSAV_Msk (0xFFUL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
    -
    14485#define USB_OTG_GNPTXSTS_NPTQXSAV USB_OTG_GNPTXSTS_NPTQXSAV_Msk
    -
    14486#define USB_OTG_GNPTXSTS_NPTQXSAV_0 (0x01UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
    -
    14487#define USB_OTG_GNPTXSTS_NPTQXSAV_1 (0x02UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
    -
    14488#define USB_OTG_GNPTXSTS_NPTQXSAV_2 (0x04UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
    -
    14489#define USB_OTG_GNPTXSTS_NPTQXSAV_3 (0x08UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
    -
    14490#define USB_OTG_GNPTXSTS_NPTQXSAV_4 (0x10UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
    -
    14491#define USB_OTG_GNPTXSTS_NPTQXSAV_5 (0x20UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
    -
    14492#define USB_OTG_GNPTXSTS_NPTQXSAV_6 (0x40UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
    -
    14493#define USB_OTG_GNPTXSTS_NPTQXSAV_7 (0x80UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
    -
    14495#define USB_OTG_GNPTXSTS_NPTXQTOP_Pos (24U)
    -
    14496#define USB_OTG_GNPTXSTS_NPTXQTOP_Msk (0x7FUL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
    -
    14497#define USB_OTG_GNPTXSTS_NPTXQTOP USB_OTG_GNPTXSTS_NPTXQTOP_Msk
    -
    14498#define USB_OTG_GNPTXSTS_NPTXQTOP_0 (0x01UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
    -
    14499#define USB_OTG_GNPTXSTS_NPTXQTOP_1 (0x02UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
    -
    14500#define USB_OTG_GNPTXSTS_NPTXQTOP_2 (0x04UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
    -
    14501#define USB_OTG_GNPTXSTS_NPTXQTOP_3 (0x08UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
    -
    14502#define USB_OTG_GNPTXSTS_NPTXQTOP_4 (0x10UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
    -
    14503#define USB_OTG_GNPTXSTS_NPTXQTOP_5 (0x20UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
    -
    14504#define USB_OTG_GNPTXSTS_NPTXQTOP_6 (0x40UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
    -
    14506/******************** Bit definition for USB_OTG_DTHRCTL register ********************/
    -
    14507#define USB_OTG_DTHRCTL_NONISOTHREN_Pos (0U)
    -
    14508#define USB_OTG_DTHRCTL_NONISOTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_NONISOTHREN_Pos)
    -
    14509#define USB_OTG_DTHRCTL_NONISOTHREN USB_OTG_DTHRCTL_NONISOTHREN_Msk
    -
    14510#define USB_OTG_DTHRCTL_ISOTHREN_Pos (1U)
    -
    14511#define USB_OTG_DTHRCTL_ISOTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_ISOTHREN_Pos)
    -
    14512#define USB_OTG_DTHRCTL_ISOTHREN USB_OTG_DTHRCTL_ISOTHREN_Msk
    -
    14514#define USB_OTG_DTHRCTL_TXTHRLEN_Pos (2U)
    -
    14515#define USB_OTG_DTHRCTL_TXTHRLEN_Msk (0x1FFUL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
    -
    14516#define USB_OTG_DTHRCTL_TXTHRLEN USB_OTG_DTHRCTL_TXTHRLEN_Msk
    -
    14517#define USB_OTG_DTHRCTL_TXTHRLEN_0 (0x001UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
    -
    14518#define USB_OTG_DTHRCTL_TXTHRLEN_1 (0x002UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
    -
    14519#define USB_OTG_DTHRCTL_TXTHRLEN_2 (0x004UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
    -
    14520#define USB_OTG_DTHRCTL_TXTHRLEN_3 (0x008UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
    -
    14521#define USB_OTG_DTHRCTL_TXTHRLEN_4 (0x010UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
    -
    14522#define USB_OTG_DTHRCTL_TXTHRLEN_5 (0x020UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
    -
    14523#define USB_OTG_DTHRCTL_TXTHRLEN_6 (0x040UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
    -
    14524#define USB_OTG_DTHRCTL_TXTHRLEN_7 (0x080UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
    -
    14525#define USB_OTG_DTHRCTL_TXTHRLEN_8 (0x100UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
    -
    14526#define USB_OTG_DTHRCTL_RXTHREN_Pos (16U)
    -
    14527#define USB_OTG_DTHRCTL_RXTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_RXTHREN_Pos)
    -
    14528#define USB_OTG_DTHRCTL_RXTHREN USB_OTG_DTHRCTL_RXTHREN_Msk
    -
    14530#define USB_OTG_DTHRCTL_RXTHRLEN_Pos (17U)
    -
    14531#define USB_OTG_DTHRCTL_RXTHRLEN_Msk (0x1FFUL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
    -
    14532#define USB_OTG_DTHRCTL_RXTHRLEN USB_OTG_DTHRCTL_RXTHRLEN_Msk
    -
    14533#define USB_OTG_DTHRCTL_RXTHRLEN_0 (0x001UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
    -
    14534#define USB_OTG_DTHRCTL_RXTHRLEN_1 (0x002UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
    -
    14535#define USB_OTG_DTHRCTL_RXTHRLEN_2 (0x004UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
    -
    14536#define USB_OTG_DTHRCTL_RXTHRLEN_3 (0x008UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
    -
    14537#define USB_OTG_DTHRCTL_RXTHRLEN_4 (0x010UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
    -
    14538#define USB_OTG_DTHRCTL_RXTHRLEN_5 (0x020UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
    -
    14539#define USB_OTG_DTHRCTL_RXTHRLEN_6 (0x040UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
    -
    14540#define USB_OTG_DTHRCTL_RXTHRLEN_7 (0x080UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
    -
    14541#define USB_OTG_DTHRCTL_RXTHRLEN_8 (0x100UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
    -
    14542#define USB_OTG_DTHRCTL_ARPEN_Pos (27U)
    -
    14543#define USB_OTG_DTHRCTL_ARPEN_Msk (0x1UL << USB_OTG_DTHRCTL_ARPEN_Pos)
    -
    14544#define USB_OTG_DTHRCTL_ARPEN USB_OTG_DTHRCTL_ARPEN_Msk
    -
    14546/******************** Bit definition for USB_OTG_DIEPEMPMSK register ********************/
    -
    14547#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos (0U)
    -
    14548#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk (0xFFFFUL << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos)
    -
    14549#define USB_OTG_DIEPEMPMSK_INEPTXFEM USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk
    -
    14551/******************** Bit definition for USB_OTG_DEACHINT register ********************/
    -
    14552#define USB_OTG_DEACHINT_IEP1INT_Pos (1U)
    -
    14553#define USB_OTG_DEACHINT_IEP1INT_Msk (0x1UL << USB_OTG_DEACHINT_IEP1INT_Pos)
    -
    14554#define USB_OTG_DEACHINT_IEP1INT USB_OTG_DEACHINT_IEP1INT_Msk
    -
    14555#define USB_OTG_DEACHINT_OEP1INT_Pos (17U)
    -
    14556#define USB_OTG_DEACHINT_OEP1INT_Msk (0x1UL << USB_OTG_DEACHINT_OEP1INT_Pos)
    -
    14557#define USB_OTG_DEACHINT_OEP1INT USB_OTG_DEACHINT_OEP1INT_Msk
    -
    14559/******************** Bit definition for USB_OTG_GCCFG register ********************/
    -
    14560#define USB_OTG_GCCFG_PWRDWN_Pos (16U)
    -
    14561#define USB_OTG_GCCFG_PWRDWN_Msk (0x1UL << USB_OTG_GCCFG_PWRDWN_Pos)
    -
    14562#define USB_OTG_GCCFG_PWRDWN USB_OTG_GCCFG_PWRDWN_Msk
    -
    14563#define USB_OTG_GCCFG_I2CPADEN_Pos (17U)
    -
    14564#define USB_OTG_GCCFG_I2CPADEN_Msk (0x1UL << USB_OTG_GCCFG_I2CPADEN_Pos)
    -
    14565#define USB_OTG_GCCFG_I2CPADEN USB_OTG_GCCFG_I2CPADEN_Msk
    -
    14566#define USB_OTG_GCCFG_VBUSASEN_Pos (18U)
    -
    14567#define USB_OTG_GCCFG_VBUSASEN_Msk (0x1UL << USB_OTG_GCCFG_VBUSASEN_Pos)
    -
    14568#define USB_OTG_GCCFG_VBUSASEN USB_OTG_GCCFG_VBUSASEN_Msk
    -
    14569#define USB_OTG_GCCFG_VBUSBSEN_Pos (19U)
    -
    14570#define USB_OTG_GCCFG_VBUSBSEN_Msk (0x1UL << USB_OTG_GCCFG_VBUSBSEN_Pos)
    -
    14571#define USB_OTG_GCCFG_VBUSBSEN USB_OTG_GCCFG_VBUSBSEN_Msk
    -
    14572#define USB_OTG_GCCFG_SOFOUTEN_Pos (20U)
    -
    14573#define USB_OTG_GCCFG_SOFOUTEN_Msk (0x1UL << USB_OTG_GCCFG_SOFOUTEN_Pos)
    -
    14574#define USB_OTG_GCCFG_SOFOUTEN USB_OTG_GCCFG_SOFOUTEN_Msk
    -
    14575#define USB_OTG_GCCFG_NOVBUSSENS_Pos (21U)
    -
    14576#define USB_OTG_GCCFG_NOVBUSSENS_Msk (0x1UL << USB_OTG_GCCFG_NOVBUSSENS_Pos)
    -
    14577#define USB_OTG_GCCFG_NOVBUSSENS USB_OTG_GCCFG_NOVBUSSENS_Msk
    -
    14579/******************** Bit definition forUSB_OTG_DEACHINTMSK register ********************/
    -
    14580#define USB_OTG_DEACHINTMSK_IEP1INTM_Pos (1U)
    -
    14581#define USB_OTG_DEACHINTMSK_IEP1INTM_Msk (0x1UL << USB_OTG_DEACHINTMSK_IEP1INTM_Pos)
    -
    14582#define USB_OTG_DEACHINTMSK_IEP1INTM USB_OTG_DEACHINTMSK_IEP1INTM_Msk
    -
    14583#define USB_OTG_DEACHINTMSK_OEP1INTM_Pos (17U)
    -
    14584#define USB_OTG_DEACHINTMSK_OEP1INTM_Msk (0x1UL << USB_OTG_DEACHINTMSK_OEP1INTM_Pos)
    -
    14585#define USB_OTG_DEACHINTMSK_OEP1INTM USB_OTG_DEACHINTMSK_OEP1INTM_Msk
    -
    14587/******************** Bit definition for USB_OTG_CID register ********************/
    -
    14588#define USB_OTG_CID_PRODUCT_ID_Pos (0U)
    -
    14589#define USB_OTG_CID_PRODUCT_ID_Msk (0xFFFFFFFFUL << USB_OTG_CID_PRODUCT_ID_Pos)
    -
    14590#define USB_OTG_CID_PRODUCT_ID USB_OTG_CID_PRODUCT_ID_Msk
    -
    14592/******************** Bit definition for USB_OTG_DIEPEACHMSK1 register ********************/
    -
    14593#define USB_OTG_DIEPEACHMSK1_XFRCM_Pos (0U)
    -
    14594#define USB_OTG_DIEPEACHMSK1_XFRCM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_XFRCM_Pos)
    -
    14595#define USB_OTG_DIEPEACHMSK1_XFRCM USB_OTG_DIEPEACHMSK1_XFRCM_Msk
    -
    14596#define USB_OTG_DIEPEACHMSK1_EPDM_Pos (1U)
    -
    14597#define USB_OTG_DIEPEACHMSK1_EPDM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_EPDM_Pos)
    -
    14598#define USB_OTG_DIEPEACHMSK1_EPDM USB_OTG_DIEPEACHMSK1_EPDM_Msk
    -
    14599#define USB_OTG_DIEPEACHMSK1_TOM_Pos (3U)
    -
    14600#define USB_OTG_DIEPEACHMSK1_TOM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_TOM_Pos)
    -
    14601#define USB_OTG_DIEPEACHMSK1_TOM USB_OTG_DIEPEACHMSK1_TOM_Msk
    -
    14602#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos (4U)
    -
    14603#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos)
    -
    14604#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk
    -
    14605#define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos (5U)
    -
    14606#define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos)
    -
    14607#define USB_OTG_DIEPEACHMSK1_INEPNMM USB_OTG_DIEPEACHMSK1_INEPNMM_Msk
    -
    14608#define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos (6U)
    -
    14609#define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos)
    -
    14610#define USB_OTG_DIEPEACHMSK1_INEPNEM USB_OTG_DIEPEACHMSK1_INEPNEM_Msk
    -
    14611#define USB_OTG_DIEPEACHMSK1_TXFURM_Pos (8U)
    -
    14612#define USB_OTG_DIEPEACHMSK1_TXFURM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_TXFURM_Pos)
    -
    14613#define USB_OTG_DIEPEACHMSK1_TXFURM USB_OTG_DIEPEACHMSK1_TXFURM_Msk
    -
    14614#define USB_OTG_DIEPEACHMSK1_BIM_Pos (9U)
    -
    14615#define USB_OTG_DIEPEACHMSK1_BIM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_BIM_Pos)
    -
    14616#define USB_OTG_DIEPEACHMSK1_BIM USB_OTG_DIEPEACHMSK1_BIM_Msk
    -
    14617#define USB_OTG_DIEPEACHMSK1_NAKM_Pos (13U)
    -
    14618#define USB_OTG_DIEPEACHMSK1_NAKM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_NAKM_Pos)
    -
    14619#define USB_OTG_DIEPEACHMSK1_NAKM USB_OTG_DIEPEACHMSK1_NAKM_Msk
    -
    14621/******************** Bit definition for USB_OTG_HPRT register ********************/
    -
    14622#define USB_OTG_HPRT_PCSTS_Pos (0U)
    -
    14623#define USB_OTG_HPRT_PCSTS_Msk (0x1UL << USB_OTG_HPRT_PCSTS_Pos)
    -
    14624#define USB_OTG_HPRT_PCSTS USB_OTG_HPRT_PCSTS_Msk
    -
    14625#define USB_OTG_HPRT_PCDET_Pos (1U)
    -
    14626#define USB_OTG_HPRT_PCDET_Msk (0x1UL << USB_OTG_HPRT_PCDET_Pos)
    -
    14627#define USB_OTG_HPRT_PCDET USB_OTG_HPRT_PCDET_Msk
    -
    14628#define USB_OTG_HPRT_PENA_Pos (2U)
    -
    14629#define USB_OTG_HPRT_PENA_Msk (0x1UL << USB_OTG_HPRT_PENA_Pos)
    -
    14630#define USB_OTG_HPRT_PENA USB_OTG_HPRT_PENA_Msk
    -
    14631#define USB_OTG_HPRT_PENCHNG_Pos (3U)
    -
    14632#define USB_OTG_HPRT_PENCHNG_Msk (0x1UL << USB_OTG_HPRT_PENCHNG_Pos)
    -
    14633#define USB_OTG_HPRT_PENCHNG USB_OTG_HPRT_PENCHNG_Msk
    -
    14634#define USB_OTG_HPRT_POCA_Pos (4U)
    -
    14635#define USB_OTG_HPRT_POCA_Msk (0x1UL << USB_OTG_HPRT_POCA_Pos)
    -
    14636#define USB_OTG_HPRT_POCA USB_OTG_HPRT_POCA_Msk
    -
    14637#define USB_OTG_HPRT_POCCHNG_Pos (5U)
    -
    14638#define USB_OTG_HPRT_POCCHNG_Msk (0x1UL << USB_OTG_HPRT_POCCHNG_Pos)
    -
    14639#define USB_OTG_HPRT_POCCHNG USB_OTG_HPRT_POCCHNG_Msk
    -
    14640#define USB_OTG_HPRT_PRES_Pos (6U)
    -
    14641#define USB_OTG_HPRT_PRES_Msk (0x1UL << USB_OTG_HPRT_PRES_Pos)
    -
    14642#define USB_OTG_HPRT_PRES USB_OTG_HPRT_PRES_Msk
    -
    14643#define USB_OTG_HPRT_PSUSP_Pos (7U)
    -
    14644#define USB_OTG_HPRT_PSUSP_Msk (0x1UL << USB_OTG_HPRT_PSUSP_Pos)
    -
    14645#define USB_OTG_HPRT_PSUSP USB_OTG_HPRT_PSUSP_Msk
    -
    14646#define USB_OTG_HPRT_PRST_Pos (8U)
    -
    14647#define USB_OTG_HPRT_PRST_Msk (0x1UL << USB_OTG_HPRT_PRST_Pos)
    -
    14648#define USB_OTG_HPRT_PRST USB_OTG_HPRT_PRST_Msk
    -
    14650#define USB_OTG_HPRT_PLSTS_Pos (10U)
    -
    14651#define USB_OTG_HPRT_PLSTS_Msk (0x3UL << USB_OTG_HPRT_PLSTS_Pos)
    -
    14652#define USB_OTG_HPRT_PLSTS USB_OTG_HPRT_PLSTS_Msk
    -
    14653#define USB_OTG_HPRT_PLSTS_0 (0x1UL << USB_OTG_HPRT_PLSTS_Pos)
    -
    14654#define USB_OTG_HPRT_PLSTS_1 (0x2UL << USB_OTG_HPRT_PLSTS_Pos)
    -
    14655#define USB_OTG_HPRT_PPWR_Pos (12U)
    -
    14656#define USB_OTG_HPRT_PPWR_Msk (0x1UL << USB_OTG_HPRT_PPWR_Pos)
    -
    14657#define USB_OTG_HPRT_PPWR USB_OTG_HPRT_PPWR_Msk
    -
    14659#define USB_OTG_HPRT_PTCTL_Pos (13U)
    -
    14660#define USB_OTG_HPRT_PTCTL_Msk (0xFUL << USB_OTG_HPRT_PTCTL_Pos)
    -
    14661#define USB_OTG_HPRT_PTCTL USB_OTG_HPRT_PTCTL_Msk
    -
    14662#define USB_OTG_HPRT_PTCTL_0 (0x1UL << USB_OTG_HPRT_PTCTL_Pos)
    -
    14663#define USB_OTG_HPRT_PTCTL_1 (0x2UL << USB_OTG_HPRT_PTCTL_Pos)
    -
    14664#define USB_OTG_HPRT_PTCTL_2 (0x4UL << USB_OTG_HPRT_PTCTL_Pos)
    -
    14665#define USB_OTG_HPRT_PTCTL_3 (0x8UL << USB_OTG_HPRT_PTCTL_Pos)
    -
    14667#define USB_OTG_HPRT_PSPD_Pos (17U)
    -
    14668#define USB_OTG_HPRT_PSPD_Msk (0x3UL << USB_OTG_HPRT_PSPD_Pos)
    -
    14669#define USB_OTG_HPRT_PSPD USB_OTG_HPRT_PSPD_Msk
    -
    14670#define USB_OTG_HPRT_PSPD_0 (0x1UL << USB_OTG_HPRT_PSPD_Pos)
    -
    14671#define USB_OTG_HPRT_PSPD_1 (0x2UL << USB_OTG_HPRT_PSPD_Pos)
    -
    14673/******************** Bit definition for USB_OTG_DOEPEACHMSK1 register ********************/
    -
    14674#define USB_OTG_DOEPEACHMSK1_XFRCM_Pos (0U)
    -
    14675#define USB_OTG_DOEPEACHMSK1_XFRCM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_XFRCM_Pos)
    -
    14676#define USB_OTG_DOEPEACHMSK1_XFRCM USB_OTG_DOEPEACHMSK1_XFRCM_Msk
    -
    14677#define USB_OTG_DOEPEACHMSK1_EPDM_Pos (1U)
    -
    14678#define USB_OTG_DOEPEACHMSK1_EPDM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_EPDM_Pos)
    -
    14679#define USB_OTG_DOEPEACHMSK1_EPDM USB_OTG_DOEPEACHMSK1_EPDM_Msk
    -
    14680#define USB_OTG_DOEPEACHMSK1_TOM_Pos (3U)
    -
    14681#define USB_OTG_DOEPEACHMSK1_TOM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_TOM_Pos)
    -
    14682#define USB_OTG_DOEPEACHMSK1_TOM USB_OTG_DOEPEACHMSK1_TOM_Msk
    -
    14683#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos (4U)
    -
    14684#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos)
    -
    14685#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk
    -
    14686#define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos (5U)
    -
    14687#define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos)
    -
    14688#define USB_OTG_DOEPEACHMSK1_INEPNMM USB_OTG_DOEPEACHMSK1_INEPNMM_Msk
    -
    14689#define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos (6U)
    -
    14690#define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos)
    -
    14691#define USB_OTG_DOEPEACHMSK1_INEPNEM USB_OTG_DOEPEACHMSK1_INEPNEM_Msk
    -
    14692#define USB_OTG_DOEPEACHMSK1_TXFURM_Pos (8U)
    -
    14693#define USB_OTG_DOEPEACHMSK1_TXFURM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_TXFURM_Pos)
    -
    14694#define USB_OTG_DOEPEACHMSK1_TXFURM USB_OTG_DOEPEACHMSK1_TXFURM_Msk
    -
    14695#define USB_OTG_DOEPEACHMSK1_BIM_Pos (9U)
    -
    14696#define USB_OTG_DOEPEACHMSK1_BIM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_BIM_Pos)
    -
    14697#define USB_OTG_DOEPEACHMSK1_BIM USB_OTG_DOEPEACHMSK1_BIM_Msk
    -
    14698#define USB_OTG_DOEPEACHMSK1_BERRM_Pos (12U)
    -
    14699#define USB_OTG_DOEPEACHMSK1_BERRM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_BERRM_Pos)
    -
    14700#define USB_OTG_DOEPEACHMSK1_BERRM USB_OTG_DOEPEACHMSK1_BERRM_Msk
    -
    14701#define USB_OTG_DOEPEACHMSK1_NAKM_Pos (13U)
    -
    14702#define USB_OTG_DOEPEACHMSK1_NAKM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_NAKM_Pos)
    -
    14703#define USB_OTG_DOEPEACHMSK1_NAKM USB_OTG_DOEPEACHMSK1_NAKM_Msk
    -
    14704#define USB_OTG_DOEPEACHMSK1_NYETM_Pos (14U)
    -
    14705#define USB_OTG_DOEPEACHMSK1_NYETM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_NYETM_Pos)
    -
    14706#define USB_OTG_DOEPEACHMSK1_NYETM USB_OTG_DOEPEACHMSK1_NYETM_Msk
    -
    14708/******************** Bit definition for USB_OTG_HPTXFSIZ register ********************/
    -
    14709#define USB_OTG_HPTXFSIZ_PTXSA_Pos (0U)
    -
    14710#define USB_OTG_HPTXFSIZ_PTXSA_Msk (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXSA_Pos)
    -
    14711#define USB_OTG_HPTXFSIZ_PTXSA USB_OTG_HPTXFSIZ_PTXSA_Msk
    -
    14712#define USB_OTG_HPTXFSIZ_PTXFD_Pos (16U)
    -
    14713#define USB_OTG_HPTXFSIZ_PTXFD_Msk (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXFD_Pos)
    -
    14714#define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFD_Msk
    -
    14716/******************** Bit definition for USB_OTG_DIEPCTL register ********************/
    -
    14717#define USB_OTG_DIEPCTL_MPSIZ_Pos (0U)
    -
    14718#define USB_OTG_DIEPCTL_MPSIZ_Msk (0x7FFUL << USB_OTG_DIEPCTL_MPSIZ_Pos)
    -
    14719#define USB_OTG_DIEPCTL_MPSIZ USB_OTG_DIEPCTL_MPSIZ_Msk
    -
    14720#define USB_OTG_DIEPCTL_USBAEP_Pos (15U)
    -
    14721#define USB_OTG_DIEPCTL_USBAEP_Msk (0x1UL << USB_OTG_DIEPCTL_USBAEP_Pos)
    -
    14722#define USB_OTG_DIEPCTL_USBAEP USB_OTG_DIEPCTL_USBAEP_Msk
    -
    14723#define USB_OTG_DIEPCTL_EONUM_DPID_Pos (16U)
    -
    14724#define USB_OTG_DIEPCTL_EONUM_DPID_Msk (0x1UL << USB_OTG_DIEPCTL_EONUM_DPID_Pos)
    -
    14725#define USB_OTG_DIEPCTL_EONUM_DPID USB_OTG_DIEPCTL_EONUM_DPID_Msk
    -
    14726#define USB_OTG_DIEPCTL_NAKSTS_Pos (17U)
    -
    14727#define USB_OTG_DIEPCTL_NAKSTS_Msk (0x1UL << USB_OTG_DIEPCTL_NAKSTS_Pos)
    -
    14728#define USB_OTG_DIEPCTL_NAKSTS USB_OTG_DIEPCTL_NAKSTS_Msk
    -
    14730#define USB_OTG_DIEPCTL_EPTYP_Pos (18U)
    -
    14731#define USB_OTG_DIEPCTL_EPTYP_Msk (0x3UL << USB_OTG_DIEPCTL_EPTYP_Pos)
    -
    14732#define USB_OTG_DIEPCTL_EPTYP USB_OTG_DIEPCTL_EPTYP_Msk
    -
    14733#define USB_OTG_DIEPCTL_EPTYP_0 (0x1UL << USB_OTG_DIEPCTL_EPTYP_Pos)
    -
    14734#define USB_OTG_DIEPCTL_EPTYP_1 (0x2UL << USB_OTG_DIEPCTL_EPTYP_Pos)
    -
    14735#define USB_OTG_DIEPCTL_STALL_Pos (21U)
    -
    14736#define USB_OTG_DIEPCTL_STALL_Msk (0x1UL << USB_OTG_DIEPCTL_STALL_Pos)
    -
    14737#define USB_OTG_DIEPCTL_STALL USB_OTG_DIEPCTL_STALL_Msk
    -
    14739#define USB_OTG_DIEPCTL_TXFNUM_Pos (22U)
    -
    14740#define USB_OTG_DIEPCTL_TXFNUM_Msk (0xFUL << USB_OTG_DIEPCTL_TXFNUM_Pos)
    -
    14741#define USB_OTG_DIEPCTL_TXFNUM USB_OTG_DIEPCTL_TXFNUM_Msk
    -
    14742#define USB_OTG_DIEPCTL_TXFNUM_0 (0x1UL << USB_OTG_DIEPCTL_TXFNUM_Pos)
    -
    14743#define USB_OTG_DIEPCTL_TXFNUM_1 (0x2UL << USB_OTG_DIEPCTL_TXFNUM_Pos)
    -
    14744#define USB_OTG_DIEPCTL_TXFNUM_2 (0x4UL << USB_OTG_DIEPCTL_TXFNUM_Pos)
    -
    14745#define USB_OTG_DIEPCTL_TXFNUM_3 (0x8UL << USB_OTG_DIEPCTL_TXFNUM_Pos)
    -
    14746#define USB_OTG_DIEPCTL_CNAK_Pos (26U)
    -
    14747#define USB_OTG_DIEPCTL_CNAK_Msk (0x1UL << USB_OTG_DIEPCTL_CNAK_Pos)
    -
    14748#define USB_OTG_DIEPCTL_CNAK USB_OTG_DIEPCTL_CNAK_Msk
    -
    14749#define USB_OTG_DIEPCTL_SNAK_Pos (27U)
    -
    14750#define USB_OTG_DIEPCTL_SNAK_Msk (0x1UL << USB_OTG_DIEPCTL_SNAK_Pos)
    -
    14751#define USB_OTG_DIEPCTL_SNAK USB_OTG_DIEPCTL_SNAK_Msk
    -
    14752#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos (28U)
    -
    14753#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk (0x1UL << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos)
    -
    14754#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk
    -
    14755#define USB_OTG_DIEPCTL_SODDFRM_Pos (29U)
    -
    14756#define USB_OTG_DIEPCTL_SODDFRM_Msk (0x1UL << USB_OTG_DIEPCTL_SODDFRM_Pos)
    -
    14757#define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SODDFRM_Msk
    -
    14758#define USB_OTG_DIEPCTL_EPDIS_Pos (30U)
    -
    14759#define USB_OTG_DIEPCTL_EPDIS_Msk (0x1UL << USB_OTG_DIEPCTL_EPDIS_Pos)
    -
    14760#define USB_OTG_DIEPCTL_EPDIS USB_OTG_DIEPCTL_EPDIS_Msk
    -
    14761#define USB_OTG_DIEPCTL_EPENA_Pos (31U)
    -
    14762#define USB_OTG_DIEPCTL_EPENA_Msk (0x1UL << USB_OTG_DIEPCTL_EPENA_Pos)
    -
    14763#define USB_OTG_DIEPCTL_EPENA USB_OTG_DIEPCTL_EPENA_Msk
    -
    14765/******************** Bit definition for USB_OTG_HCCHAR register ********************/
    -
    14766#define USB_OTG_HCCHAR_MPSIZ_Pos (0U)
    -
    14767#define USB_OTG_HCCHAR_MPSIZ_Msk (0x7FFUL << USB_OTG_HCCHAR_MPSIZ_Pos)
    -
    14768#define USB_OTG_HCCHAR_MPSIZ USB_OTG_HCCHAR_MPSIZ_Msk
    -
    14770#define USB_OTG_HCCHAR_EPNUM_Pos (11U)
    -
    14771#define USB_OTG_HCCHAR_EPNUM_Msk (0xFUL << USB_OTG_HCCHAR_EPNUM_Pos)
    -
    14772#define USB_OTG_HCCHAR_EPNUM USB_OTG_HCCHAR_EPNUM_Msk
    -
    14773#define USB_OTG_HCCHAR_EPNUM_0 (0x1UL << USB_OTG_HCCHAR_EPNUM_Pos)
    -
    14774#define USB_OTG_HCCHAR_EPNUM_1 (0x2UL << USB_OTG_HCCHAR_EPNUM_Pos)
    -
    14775#define USB_OTG_HCCHAR_EPNUM_2 (0x4UL << USB_OTG_HCCHAR_EPNUM_Pos)
    -
    14776#define USB_OTG_HCCHAR_EPNUM_3 (0x8UL << USB_OTG_HCCHAR_EPNUM_Pos)
    -
    14777#define USB_OTG_HCCHAR_EPDIR_Pos (15U)
    -
    14778#define USB_OTG_HCCHAR_EPDIR_Msk (0x1UL << USB_OTG_HCCHAR_EPDIR_Pos)
    -
    14779#define USB_OTG_HCCHAR_EPDIR USB_OTG_HCCHAR_EPDIR_Msk
    -
    14780#define USB_OTG_HCCHAR_LSDEV_Pos (17U)
    -
    14781#define USB_OTG_HCCHAR_LSDEV_Msk (0x1UL << USB_OTG_HCCHAR_LSDEV_Pos)
    -
    14782#define USB_OTG_HCCHAR_LSDEV USB_OTG_HCCHAR_LSDEV_Msk
    -
    14784#define USB_OTG_HCCHAR_EPTYP_Pos (18U)
    -
    14785#define USB_OTG_HCCHAR_EPTYP_Msk (0x3UL << USB_OTG_HCCHAR_EPTYP_Pos)
    -
    14786#define USB_OTG_HCCHAR_EPTYP USB_OTG_HCCHAR_EPTYP_Msk
    -
    14787#define USB_OTG_HCCHAR_EPTYP_0 (0x1UL << USB_OTG_HCCHAR_EPTYP_Pos)
    -
    14788#define USB_OTG_HCCHAR_EPTYP_1 (0x2UL << USB_OTG_HCCHAR_EPTYP_Pos)
    -
    14790#define USB_OTG_HCCHAR_MC_Pos (20U)
    -
    14791#define USB_OTG_HCCHAR_MC_Msk (0x3UL << USB_OTG_HCCHAR_MC_Pos)
    -
    14792#define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MC_Msk
    -
    14793#define USB_OTG_HCCHAR_MC_0 (0x1UL << USB_OTG_HCCHAR_MC_Pos)
    -
    14794#define USB_OTG_HCCHAR_MC_1 (0x2UL << USB_OTG_HCCHAR_MC_Pos)
    -
    14796#define USB_OTG_HCCHAR_DAD_Pos (22U)
    -
    14797#define USB_OTG_HCCHAR_DAD_Msk (0x7FUL << USB_OTG_HCCHAR_DAD_Pos)
    -
    14798#define USB_OTG_HCCHAR_DAD USB_OTG_HCCHAR_DAD_Msk
    -
    14799#define USB_OTG_HCCHAR_DAD_0 (0x01UL << USB_OTG_HCCHAR_DAD_Pos)
    -
    14800#define USB_OTG_HCCHAR_DAD_1 (0x02UL << USB_OTG_HCCHAR_DAD_Pos)
    -
    14801#define USB_OTG_HCCHAR_DAD_2 (0x04UL << USB_OTG_HCCHAR_DAD_Pos)
    -
    14802#define USB_OTG_HCCHAR_DAD_3 (0x08UL << USB_OTG_HCCHAR_DAD_Pos)
    -
    14803#define USB_OTG_HCCHAR_DAD_4 (0x10UL << USB_OTG_HCCHAR_DAD_Pos)
    -
    14804#define USB_OTG_HCCHAR_DAD_5 (0x20UL << USB_OTG_HCCHAR_DAD_Pos)
    -
    14805#define USB_OTG_HCCHAR_DAD_6 (0x40UL << USB_OTG_HCCHAR_DAD_Pos)
    -
    14806#define USB_OTG_HCCHAR_ODDFRM_Pos (29U)
    -
    14807#define USB_OTG_HCCHAR_ODDFRM_Msk (0x1UL << USB_OTG_HCCHAR_ODDFRM_Pos)
    -
    14808#define USB_OTG_HCCHAR_ODDFRM USB_OTG_HCCHAR_ODDFRM_Msk
    -
    14809#define USB_OTG_HCCHAR_CHDIS_Pos (30U)
    -
    14810#define USB_OTG_HCCHAR_CHDIS_Msk (0x1UL << USB_OTG_HCCHAR_CHDIS_Pos)
    -
    14811#define USB_OTG_HCCHAR_CHDIS USB_OTG_HCCHAR_CHDIS_Msk
    -
    14812#define USB_OTG_HCCHAR_CHENA_Pos (31U)
    -
    14813#define USB_OTG_HCCHAR_CHENA_Msk (0x1UL << USB_OTG_HCCHAR_CHENA_Pos)
    -
    14814#define USB_OTG_HCCHAR_CHENA USB_OTG_HCCHAR_CHENA_Msk
    -
    14816/******************** Bit definition for USB_OTG_HCSPLT register ********************/
    -
    14817
    -
    14818#define USB_OTG_HCSPLT_PRTADDR_Pos (0U)
    -
    14819#define USB_OTG_HCSPLT_PRTADDR_Msk (0x7FUL << USB_OTG_HCSPLT_PRTADDR_Pos)
    -
    14820#define USB_OTG_HCSPLT_PRTADDR USB_OTG_HCSPLT_PRTADDR_Msk
    -
    14821#define USB_OTG_HCSPLT_PRTADDR_0 (0x01UL << USB_OTG_HCSPLT_PRTADDR_Pos)
    -
    14822#define USB_OTG_HCSPLT_PRTADDR_1 (0x02UL << USB_OTG_HCSPLT_PRTADDR_Pos)
    -
    14823#define USB_OTG_HCSPLT_PRTADDR_2 (0x04UL << USB_OTG_HCSPLT_PRTADDR_Pos)
    -
    14824#define USB_OTG_HCSPLT_PRTADDR_3 (0x08UL << USB_OTG_HCSPLT_PRTADDR_Pos)
    -
    14825#define USB_OTG_HCSPLT_PRTADDR_4 (0x10UL << USB_OTG_HCSPLT_PRTADDR_Pos)
    -
    14826#define USB_OTG_HCSPLT_PRTADDR_5 (0x20UL << USB_OTG_HCSPLT_PRTADDR_Pos)
    -
    14827#define USB_OTG_HCSPLT_PRTADDR_6 (0x40UL << USB_OTG_HCSPLT_PRTADDR_Pos)
    -
    14829#define USB_OTG_HCSPLT_HUBADDR_Pos (7U)
    -
    14830#define USB_OTG_HCSPLT_HUBADDR_Msk (0x7FUL << USB_OTG_HCSPLT_HUBADDR_Pos)
    -
    14831#define USB_OTG_HCSPLT_HUBADDR USB_OTG_HCSPLT_HUBADDR_Msk
    -
    14832#define USB_OTG_HCSPLT_HUBADDR_0 (0x01UL << USB_OTG_HCSPLT_HUBADDR_Pos)
    -
    14833#define USB_OTG_HCSPLT_HUBADDR_1 (0x02UL << USB_OTG_HCSPLT_HUBADDR_Pos)
    -
    14834#define USB_OTG_HCSPLT_HUBADDR_2 (0x04UL << USB_OTG_HCSPLT_HUBADDR_Pos)
    -
    14835#define USB_OTG_HCSPLT_HUBADDR_3 (0x08UL << USB_OTG_HCSPLT_HUBADDR_Pos)
    -
    14836#define USB_OTG_HCSPLT_HUBADDR_4 (0x10UL << USB_OTG_HCSPLT_HUBADDR_Pos)
    -
    14837#define USB_OTG_HCSPLT_HUBADDR_5 (0x20UL << USB_OTG_HCSPLT_HUBADDR_Pos)
    -
    14838#define USB_OTG_HCSPLT_HUBADDR_6 (0x40UL << USB_OTG_HCSPLT_HUBADDR_Pos)
    -
    14840#define USB_OTG_HCSPLT_XACTPOS_Pos (14U)
    -
    14841#define USB_OTG_HCSPLT_XACTPOS_Msk (0x3UL << USB_OTG_HCSPLT_XACTPOS_Pos)
    -
    14842#define USB_OTG_HCSPLT_XACTPOS USB_OTG_HCSPLT_XACTPOS_Msk
    -
    14843#define USB_OTG_HCSPLT_XACTPOS_0 (0x1UL << USB_OTG_HCSPLT_XACTPOS_Pos)
    -
    14844#define USB_OTG_HCSPLT_XACTPOS_1 (0x2UL << USB_OTG_HCSPLT_XACTPOS_Pos)
    -
    14845#define USB_OTG_HCSPLT_COMPLSPLT_Pos (16U)
    -
    14846#define USB_OTG_HCSPLT_COMPLSPLT_Msk (0x1UL << USB_OTG_HCSPLT_COMPLSPLT_Pos)
    -
    14847#define USB_OTG_HCSPLT_COMPLSPLT USB_OTG_HCSPLT_COMPLSPLT_Msk
    -
    14848#define USB_OTG_HCSPLT_SPLITEN_Pos (31U)
    -
    14849#define USB_OTG_HCSPLT_SPLITEN_Msk (0x1UL << USB_OTG_HCSPLT_SPLITEN_Pos)
    -
    14850#define USB_OTG_HCSPLT_SPLITEN USB_OTG_HCSPLT_SPLITEN_Msk
    -
    14852/******************** Bit definition for USB_OTG_HCINT register ********************/
    -
    14853#define USB_OTG_HCINT_XFRC_Pos (0U)
    -
    14854#define USB_OTG_HCINT_XFRC_Msk (0x1UL << USB_OTG_HCINT_XFRC_Pos)
    -
    14855#define USB_OTG_HCINT_XFRC USB_OTG_HCINT_XFRC_Msk
    -
    14856#define USB_OTG_HCINT_CHH_Pos (1U)
    -
    14857#define USB_OTG_HCINT_CHH_Msk (0x1UL << USB_OTG_HCINT_CHH_Pos)
    -
    14858#define USB_OTG_HCINT_CHH USB_OTG_HCINT_CHH_Msk
    -
    14859#define USB_OTG_HCINT_AHBERR_Pos (2U)
    -
    14860#define USB_OTG_HCINT_AHBERR_Msk (0x1UL << USB_OTG_HCINT_AHBERR_Pos)
    -
    14861#define USB_OTG_HCINT_AHBERR USB_OTG_HCINT_AHBERR_Msk
    -
    14862#define USB_OTG_HCINT_STALL_Pos (3U)
    -
    14863#define USB_OTG_HCINT_STALL_Msk (0x1UL << USB_OTG_HCINT_STALL_Pos)
    -
    14864#define USB_OTG_HCINT_STALL USB_OTG_HCINT_STALL_Msk
    -
    14865#define USB_OTG_HCINT_NAK_Pos (4U)
    -
    14866#define USB_OTG_HCINT_NAK_Msk (0x1UL << USB_OTG_HCINT_NAK_Pos)
    -
    14867#define USB_OTG_HCINT_NAK USB_OTG_HCINT_NAK_Msk
    -
    14868#define USB_OTG_HCINT_ACK_Pos (5U)
    -
    14869#define USB_OTG_HCINT_ACK_Msk (0x1UL << USB_OTG_HCINT_ACK_Pos)
    -
    14870#define USB_OTG_HCINT_ACK USB_OTG_HCINT_ACK_Msk
    -
    14871#define USB_OTG_HCINT_NYET_Pos (6U)
    -
    14872#define USB_OTG_HCINT_NYET_Msk (0x1UL << USB_OTG_HCINT_NYET_Pos)
    -
    14873#define USB_OTG_HCINT_NYET USB_OTG_HCINT_NYET_Msk
    -
    14874#define USB_OTG_HCINT_TXERR_Pos (7U)
    -
    14875#define USB_OTG_HCINT_TXERR_Msk (0x1UL << USB_OTG_HCINT_TXERR_Pos)
    -
    14876#define USB_OTG_HCINT_TXERR USB_OTG_HCINT_TXERR_Msk
    -
    14877#define USB_OTG_HCINT_BBERR_Pos (8U)
    -
    14878#define USB_OTG_HCINT_BBERR_Msk (0x1UL << USB_OTG_HCINT_BBERR_Pos)
    -
    14879#define USB_OTG_HCINT_BBERR USB_OTG_HCINT_BBERR_Msk
    -
    14880#define USB_OTG_HCINT_FRMOR_Pos (9U)
    -
    14881#define USB_OTG_HCINT_FRMOR_Msk (0x1UL << USB_OTG_HCINT_FRMOR_Pos)
    -
    14882#define USB_OTG_HCINT_FRMOR USB_OTG_HCINT_FRMOR_Msk
    -
    14883#define USB_OTG_HCINT_DTERR_Pos (10U)
    -
    14884#define USB_OTG_HCINT_DTERR_Msk (0x1UL << USB_OTG_HCINT_DTERR_Pos)
    -
    14885#define USB_OTG_HCINT_DTERR USB_OTG_HCINT_DTERR_Msk
    -
    14887/******************** Bit definition for USB_OTG_DIEPINT register ********************/
    -
    14888#define USB_OTG_DIEPINT_XFRC_Pos (0U)
    -
    14889#define USB_OTG_DIEPINT_XFRC_Msk (0x1UL << USB_OTG_DIEPINT_XFRC_Pos)
    -
    14890#define USB_OTG_DIEPINT_XFRC USB_OTG_DIEPINT_XFRC_Msk
    -
    14891#define USB_OTG_DIEPINT_EPDISD_Pos (1U)
    -
    14892#define USB_OTG_DIEPINT_EPDISD_Msk (0x1UL << USB_OTG_DIEPINT_EPDISD_Pos)
    -
    14893#define USB_OTG_DIEPINT_EPDISD USB_OTG_DIEPINT_EPDISD_Msk
    -
    14894#define USB_OTG_DIEPINT_AHBERR_Pos (2U)
    -
    14895#define USB_OTG_DIEPINT_AHBERR_Msk (0x1UL << USB_OTG_DIEPINT_AHBERR_Pos)
    -
    14896#define USB_OTG_DIEPINT_AHBERR USB_OTG_DIEPINT_AHBERR_Msk
    -
    14897#define USB_OTG_DIEPINT_TOC_Pos (3U)
    -
    14898#define USB_OTG_DIEPINT_TOC_Msk (0x1UL << USB_OTG_DIEPINT_TOC_Pos)
    -
    14899#define USB_OTG_DIEPINT_TOC USB_OTG_DIEPINT_TOC_Msk
    -
    14900#define USB_OTG_DIEPINT_ITTXFE_Pos (4U)
    -
    14901#define USB_OTG_DIEPINT_ITTXFE_Msk (0x1UL << USB_OTG_DIEPINT_ITTXFE_Pos)
    -
    14902#define USB_OTG_DIEPINT_ITTXFE USB_OTG_DIEPINT_ITTXFE_Msk
    -
    14903#define USB_OTG_DIEPINT_INEPNM_Pos (5U)
    -
    14904#define USB_OTG_DIEPINT_INEPNM_Msk (0x1UL << USB_OTG_DIEPINT_INEPNM_Pos)
    -
    14905#define USB_OTG_DIEPINT_INEPNM USB_OTG_DIEPINT_INEPNM_Msk
    -
    14906#define USB_OTG_DIEPINT_INEPNE_Pos (6U)
    -
    14907#define USB_OTG_DIEPINT_INEPNE_Msk (0x1UL << USB_OTG_DIEPINT_INEPNE_Pos)
    -
    14908#define USB_OTG_DIEPINT_INEPNE USB_OTG_DIEPINT_INEPNE_Msk
    -
    14909#define USB_OTG_DIEPINT_TXFE_Pos (7U)
    -
    14910#define USB_OTG_DIEPINT_TXFE_Msk (0x1UL << USB_OTG_DIEPINT_TXFE_Pos)
    -
    14911#define USB_OTG_DIEPINT_TXFE USB_OTG_DIEPINT_TXFE_Msk
    -
    14912#define USB_OTG_DIEPINT_TXFIFOUDRN_Pos (8U)
    -
    14913#define USB_OTG_DIEPINT_TXFIFOUDRN_Msk (0x1UL << USB_OTG_DIEPINT_TXFIFOUDRN_Pos)
    -
    14914#define USB_OTG_DIEPINT_TXFIFOUDRN USB_OTG_DIEPINT_TXFIFOUDRN_Msk
    -
    14915#define USB_OTG_DIEPINT_BNA_Pos (9U)
    -
    14916#define USB_OTG_DIEPINT_BNA_Msk (0x1UL << USB_OTG_DIEPINT_BNA_Pos)
    -
    14917#define USB_OTG_DIEPINT_BNA USB_OTG_DIEPINT_BNA_Msk
    -
    14918#define USB_OTG_DIEPINT_PKTDRPSTS_Pos (11U)
    -
    14919#define USB_OTG_DIEPINT_PKTDRPSTS_Msk (0x1UL << USB_OTG_DIEPINT_PKTDRPSTS_Pos)
    -
    14920#define USB_OTG_DIEPINT_PKTDRPSTS USB_OTG_DIEPINT_PKTDRPSTS_Msk
    -
    14921#define USB_OTG_DIEPINT_BERR_Pos (12U)
    -
    14922#define USB_OTG_DIEPINT_BERR_Msk (0x1UL << USB_OTG_DIEPINT_BERR_Pos)
    -
    14923#define USB_OTG_DIEPINT_BERR USB_OTG_DIEPINT_BERR_Msk
    -
    14924#define USB_OTG_DIEPINT_NAK_Pos (13U)
    -
    14925#define USB_OTG_DIEPINT_NAK_Msk (0x1UL << USB_OTG_DIEPINT_NAK_Pos)
    -
    14926#define USB_OTG_DIEPINT_NAK USB_OTG_DIEPINT_NAK_Msk
    -
    14928/******************** Bit definition forUSB_OTG_HCINTMSK register ********************/
    -
    14929#define USB_OTG_HCINTMSK_XFRCM_Pos (0U)
    -
    14930#define USB_OTG_HCINTMSK_XFRCM_Msk (0x1UL << USB_OTG_HCINTMSK_XFRCM_Pos)
    -
    14931#define USB_OTG_HCINTMSK_XFRCM USB_OTG_HCINTMSK_XFRCM_Msk
    -
    14932#define USB_OTG_HCINTMSK_CHHM_Pos (1U)
    -
    14933#define USB_OTG_HCINTMSK_CHHM_Msk (0x1UL << USB_OTG_HCINTMSK_CHHM_Pos)
    -
    14934#define USB_OTG_HCINTMSK_CHHM USB_OTG_HCINTMSK_CHHM_Msk
    -
    14935#define USB_OTG_HCINTMSK_AHBERR_Pos (2U)
    -
    14936#define USB_OTG_HCINTMSK_AHBERR_Msk (0x1UL << USB_OTG_HCINTMSK_AHBERR_Pos)
    -
    14937#define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERR_Msk
    -
    14938#define USB_OTG_HCINTMSK_STALLM_Pos (3U)
    -
    14939#define USB_OTG_HCINTMSK_STALLM_Msk (0x1UL << USB_OTG_HCINTMSK_STALLM_Pos)
    -
    14940#define USB_OTG_HCINTMSK_STALLM USB_OTG_HCINTMSK_STALLM_Msk
    -
    14941#define USB_OTG_HCINTMSK_NAKM_Pos (4U)
    -
    14942#define USB_OTG_HCINTMSK_NAKM_Msk (0x1UL << USB_OTG_HCINTMSK_NAKM_Pos)
    -
    14943#define USB_OTG_HCINTMSK_NAKM USB_OTG_HCINTMSK_NAKM_Msk
    -
    14944#define USB_OTG_HCINTMSK_ACKM_Pos (5U)
    -
    14945#define USB_OTG_HCINTMSK_ACKM_Msk (0x1UL << USB_OTG_HCINTMSK_ACKM_Pos)
    -
    14946#define USB_OTG_HCINTMSK_ACKM USB_OTG_HCINTMSK_ACKM_Msk
    -
    14947#define USB_OTG_HCINTMSK_NYET_Pos (6U)
    -
    14948#define USB_OTG_HCINTMSK_NYET_Msk (0x1UL << USB_OTG_HCINTMSK_NYET_Pos)
    -
    14949#define USB_OTG_HCINTMSK_NYET USB_OTG_HCINTMSK_NYET_Msk
    -
    14950#define USB_OTG_HCINTMSK_TXERRM_Pos (7U)
    -
    14951#define USB_OTG_HCINTMSK_TXERRM_Msk (0x1UL << USB_OTG_HCINTMSK_TXERRM_Pos)
    -
    14952#define USB_OTG_HCINTMSK_TXERRM USB_OTG_HCINTMSK_TXERRM_Msk
    -
    14953#define USB_OTG_HCINTMSK_BBERRM_Pos (8U)
    -
    14954#define USB_OTG_HCINTMSK_BBERRM_Msk (0x1UL << USB_OTG_HCINTMSK_BBERRM_Pos)
    -
    14955#define USB_OTG_HCINTMSK_BBERRM USB_OTG_HCINTMSK_BBERRM_Msk
    -
    14956#define USB_OTG_HCINTMSK_FRMORM_Pos (9U)
    -
    14957#define USB_OTG_HCINTMSK_FRMORM_Msk (0x1UL << USB_OTG_HCINTMSK_FRMORM_Pos)
    -
    14958#define USB_OTG_HCINTMSK_FRMORM USB_OTG_HCINTMSK_FRMORM_Msk
    -
    14959#define USB_OTG_HCINTMSK_DTERRM_Pos (10U)
    -
    14960#define USB_OTG_HCINTMSK_DTERRM_Msk (0x1UL << USB_OTG_HCINTMSK_DTERRM_Pos)
    -
    14961#define USB_OTG_HCINTMSK_DTERRM USB_OTG_HCINTMSK_DTERRM_Msk
    -
    14963/******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/
    -
    14964
    -
    14965#define USB_OTG_DIEPTSIZ_XFRSIZ_Pos (0U)
    -
    14966#define USB_OTG_DIEPTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_DIEPTSIZ_XFRSIZ_Pos)
    -
    14967#define USB_OTG_DIEPTSIZ_XFRSIZ USB_OTG_DIEPTSIZ_XFRSIZ_Msk
    -
    14968#define USB_OTG_DIEPTSIZ_PKTCNT_Pos (19U)
    -
    14969#define USB_OTG_DIEPTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_DIEPTSIZ_PKTCNT_Pos)
    -
    14970#define USB_OTG_DIEPTSIZ_PKTCNT USB_OTG_DIEPTSIZ_PKTCNT_Msk
    -
    14971#define USB_OTG_DIEPTSIZ_MULCNT_Pos (29U)
    -
    14972#define USB_OTG_DIEPTSIZ_MULCNT_Msk (0x3UL << USB_OTG_DIEPTSIZ_MULCNT_Pos)
    -
    14973#define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MULCNT_Msk
    -
    14974/******************** Bit definition for USB_OTG_HCTSIZ register ********************/
    -
    14975#define USB_OTG_HCTSIZ_XFRSIZ_Pos (0U)
    -
    14976#define USB_OTG_HCTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_HCTSIZ_XFRSIZ_Pos)
    -
    14977#define USB_OTG_HCTSIZ_XFRSIZ USB_OTG_HCTSIZ_XFRSIZ_Msk
    -
    14978#define USB_OTG_HCTSIZ_PKTCNT_Pos (19U)
    -
    14979#define USB_OTG_HCTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_HCTSIZ_PKTCNT_Pos)
    -
    14980#define USB_OTG_HCTSIZ_PKTCNT USB_OTG_HCTSIZ_PKTCNT_Msk
    -
    14981#define USB_OTG_HCTSIZ_DOPING_Pos (31U)
    -
    14982#define USB_OTG_HCTSIZ_DOPING_Msk (0x1UL << USB_OTG_HCTSIZ_DOPING_Pos)
    -
    14983#define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPING_Msk
    -
    14984#define USB_OTG_HCTSIZ_DPID_Pos (29U)
    -
    14985#define USB_OTG_HCTSIZ_DPID_Msk (0x3UL << USB_OTG_HCTSIZ_DPID_Pos)
    -
    14986#define USB_OTG_HCTSIZ_DPID USB_OTG_HCTSIZ_DPID_Msk
    -
    14987#define USB_OTG_HCTSIZ_DPID_0 (0x1UL << USB_OTG_HCTSIZ_DPID_Pos)
    -
    14988#define USB_OTG_HCTSIZ_DPID_1 (0x2UL << USB_OTG_HCTSIZ_DPID_Pos)
    -
    14990/******************** Bit definition for USB_OTG_DIEPDMA register ********************/
    -
    14991#define USB_OTG_DIEPDMA_DMAADDR_Pos (0U)
    -
    14992#define USB_OTG_DIEPDMA_DMAADDR_Msk (0xFFFFFFFFUL << USB_OTG_DIEPDMA_DMAADDR_Pos)
    -
    14993#define USB_OTG_DIEPDMA_DMAADDR USB_OTG_DIEPDMA_DMAADDR_Msk
    -
    14995/******************** Bit definition for USB_OTG_HCDMA register ********************/
    -
    14996#define USB_OTG_HCDMA_DMAADDR_Pos (0U)
    -
    14997#define USB_OTG_HCDMA_DMAADDR_Msk (0xFFFFFFFFUL << USB_OTG_HCDMA_DMAADDR_Pos)
    -
    14998#define USB_OTG_HCDMA_DMAADDR USB_OTG_HCDMA_DMAADDR_Msk
    -
    15000/******************** Bit definition for USB_OTG_DTXFSTS register ********************/
    -
    15001#define USB_OTG_DTXFSTS_INEPTFSAV_Pos (0U)
    -
    15002#define USB_OTG_DTXFSTS_INEPTFSAV_Msk (0xFFFFUL << USB_OTG_DTXFSTS_INEPTFSAV_Pos)
    -
    15003#define USB_OTG_DTXFSTS_INEPTFSAV USB_OTG_DTXFSTS_INEPTFSAV_Msk
    -
    15005/******************** Bit definition for USB_OTG_DIEPTXF register ********************/
    -
    15006#define USB_OTG_DIEPTXF_INEPTXSA_Pos (0U)
    -
    15007#define USB_OTG_DIEPTXF_INEPTXSA_Msk (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXSA_Pos)
    -
    15008#define USB_OTG_DIEPTXF_INEPTXSA USB_OTG_DIEPTXF_INEPTXSA_Msk
    -
    15009#define USB_OTG_DIEPTXF_INEPTXFD_Pos (16U)
    -
    15010#define USB_OTG_DIEPTXF_INEPTXFD_Msk (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXFD_Pos)
    -
    15011#define USB_OTG_DIEPTXF_INEPTXFD USB_OTG_DIEPTXF_INEPTXFD_Msk
    -
    15013/******************** Bit definition for USB_OTG_DOEPCTL register ********************/
    -
    15014
    -
    15015#define USB_OTG_DOEPCTL_MPSIZ_Pos (0U)
    -
    15016#define USB_OTG_DOEPCTL_MPSIZ_Msk (0x7FFUL << USB_OTG_DOEPCTL_MPSIZ_Pos)
    -
    15017#define USB_OTG_DOEPCTL_MPSIZ USB_OTG_DOEPCTL_MPSIZ_Msk
    -
    15018#define USB_OTG_DOEPCTL_USBAEP_Pos (15U)
    -
    15019#define USB_OTG_DOEPCTL_USBAEP_Msk (0x1UL << USB_OTG_DOEPCTL_USBAEP_Pos)
    -
    15020#define USB_OTG_DOEPCTL_USBAEP USB_OTG_DOEPCTL_USBAEP_Msk
    -
    15021#define USB_OTG_DOEPCTL_NAKSTS_Pos (17U)
    -
    15022#define USB_OTG_DOEPCTL_NAKSTS_Msk (0x1UL << USB_OTG_DOEPCTL_NAKSTS_Pos)
    -
    15023#define USB_OTG_DOEPCTL_NAKSTS USB_OTG_DOEPCTL_NAKSTS_Msk
    -
    15024#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos (28U)
    -
    15025#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk (0x1UL << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos)
    -
    15026#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk
    -
    15027#define USB_OTG_DOEPCTL_SODDFRM_Pos (29U)
    -
    15028#define USB_OTG_DOEPCTL_SODDFRM_Msk (0x1UL << USB_OTG_DOEPCTL_SODDFRM_Pos)
    -
    15029#define USB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SODDFRM_Msk
    -
    15030#define USB_OTG_DOEPCTL_EPTYP_Pos (18U)
    -
    15031#define USB_OTG_DOEPCTL_EPTYP_Msk (0x3UL << USB_OTG_DOEPCTL_EPTYP_Pos)
    -
    15032#define USB_OTG_DOEPCTL_EPTYP USB_OTG_DOEPCTL_EPTYP_Msk
    -
    15033#define USB_OTG_DOEPCTL_EPTYP_0 (0x1UL << USB_OTG_DOEPCTL_EPTYP_Pos)
    -
    15034#define USB_OTG_DOEPCTL_EPTYP_1 (0x2UL << USB_OTG_DOEPCTL_EPTYP_Pos)
    -
    15035#define USB_OTG_DOEPCTL_SNPM_Pos (20U)
    -
    15036#define USB_OTG_DOEPCTL_SNPM_Msk (0x1UL << USB_OTG_DOEPCTL_SNPM_Pos)
    -
    15037#define USB_OTG_DOEPCTL_SNPM USB_OTG_DOEPCTL_SNPM_Msk
    -
    15038#define USB_OTG_DOEPCTL_STALL_Pos (21U)
    -
    15039#define USB_OTG_DOEPCTL_STALL_Msk (0x1UL << USB_OTG_DOEPCTL_STALL_Pos)
    -
    15040#define USB_OTG_DOEPCTL_STALL USB_OTG_DOEPCTL_STALL_Msk
    -
    15041#define USB_OTG_DOEPCTL_CNAK_Pos (26U)
    -
    15042#define USB_OTG_DOEPCTL_CNAK_Msk (0x1UL << USB_OTG_DOEPCTL_CNAK_Pos)
    -
    15043#define USB_OTG_DOEPCTL_CNAK USB_OTG_DOEPCTL_CNAK_Msk
    -
    15044#define USB_OTG_DOEPCTL_SNAK_Pos (27U)
    -
    15045#define USB_OTG_DOEPCTL_SNAK_Msk (0x1UL << USB_OTG_DOEPCTL_SNAK_Pos)
    -
    15046#define USB_OTG_DOEPCTL_SNAK USB_OTG_DOEPCTL_SNAK_Msk
    -
    15047#define USB_OTG_DOEPCTL_EPDIS_Pos (30U)
    -
    15048#define USB_OTG_DOEPCTL_EPDIS_Msk (0x1UL << USB_OTG_DOEPCTL_EPDIS_Pos)
    -
    15049#define USB_OTG_DOEPCTL_EPDIS USB_OTG_DOEPCTL_EPDIS_Msk
    -
    15050#define USB_OTG_DOEPCTL_EPENA_Pos (31U)
    -
    15051#define USB_OTG_DOEPCTL_EPENA_Msk (0x1UL << USB_OTG_DOEPCTL_EPENA_Pos)
    -
    15052#define USB_OTG_DOEPCTL_EPENA USB_OTG_DOEPCTL_EPENA_Msk
    -
    15054/******************** Bit definition for USB_OTG_DOEPINT register ********************/
    -
    15055#define USB_OTG_DOEPINT_XFRC_Pos (0U)
    -
    15056#define USB_OTG_DOEPINT_XFRC_Msk (0x1UL << USB_OTG_DOEPINT_XFRC_Pos)
    -
    15057#define USB_OTG_DOEPINT_XFRC USB_OTG_DOEPINT_XFRC_Msk
    -
    15058#define USB_OTG_DOEPINT_EPDISD_Pos (1U)
    -
    15059#define USB_OTG_DOEPINT_EPDISD_Msk (0x1UL << USB_OTG_DOEPINT_EPDISD_Pos)
    -
    15060#define USB_OTG_DOEPINT_EPDISD USB_OTG_DOEPINT_EPDISD_Msk
    -
    15061#define USB_OTG_DOEPINT_AHBERR_Pos (2U)
    -
    15062#define USB_OTG_DOEPINT_AHBERR_Msk (0x1UL << USB_OTG_DOEPINT_AHBERR_Pos)
    -
    15063#define USB_OTG_DOEPINT_AHBERR USB_OTG_DOEPINT_AHBERR_Msk
    -
    15064#define USB_OTG_DOEPINT_STUP_Pos (3U)
    -
    15065#define USB_OTG_DOEPINT_STUP_Msk (0x1UL << USB_OTG_DOEPINT_STUP_Pos)
    -
    15066#define USB_OTG_DOEPINT_STUP USB_OTG_DOEPINT_STUP_Msk
    -
    15067#define USB_OTG_DOEPINT_OTEPDIS_Pos (4U)
    -
    15068#define USB_OTG_DOEPINT_OTEPDIS_Msk (0x1UL << USB_OTG_DOEPINT_OTEPDIS_Pos)
    -
    15069#define USB_OTG_DOEPINT_OTEPDIS USB_OTG_DOEPINT_OTEPDIS_Msk
    -
    15070#define USB_OTG_DOEPINT_OTEPSPR_Pos (5U)
    -
    15071#define USB_OTG_DOEPINT_OTEPSPR_Msk (0x1UL << USB_OTG_DOEPINT_OTEPSPR_Pos)
    -
    15072#define USB_OTG_DOEPINT_OTEPSPR USB_OTG_DOEPINT_OTEPSPR_Msk
    -
    15073#define USB_OTG_DOEPINT_B2BSTUP_Pos (6U)
    -
    15074#define USB_OTG_DOEPINT_B2BSTUP_Msk (0x1UL << USB_OTG_DOEPINT_B2BSTUP_Pos)
    -
    15075#define USB_OTG_DOEPINT_B2BSTUP USB_OTG_DOEPINT_B2BSTUP_Msk
    -
    15076#define USB_OTG_DOEPINT_OUTPKTERR_Pos (8U)
    -
    15077#define USB_OTG_DOEPINT_OUTPKTERR_Msk (0x1UL << USB_OTG_DOEPINT_OUTPKTERR_Pos)
    -
    15078#define USB_OTG_DOEPINT_OUTPKTERR USB_OTG_DOEPINT_OUTPKTERR_Msk
    -
    15079#define USB_OTG_DOEPINT_NAK_Pos (13U)
    -
    15080#define USB_OTG_DOEPINT_NAK_Msk (0x1UL << USB_OTG_DOEPINT_NAK_Pos)
    -
    15081#define USB_OTG_DOEPINT_NAK USB_OTG_DOEPINT_NAK_Msk
    -
    15082#define USB_OTG_DOEPINT_NYET_Pos (14U)
    -
    15083#define USB_OTG_DOEPINT_NYET_Msk (0x1UL << USB_OTG_DOEPINT_NYET_Pos)
    -
    15084#define USB_OTG_DOEPINT_NYET USB_OTG_DOEPINT_NYET_Msk
    -
    15085#define USB_OTG_DOEPINT_STPKTRX_Pos (15U)
    -
    15086#define USB_OTG_DOEPINT_STPKTRX_Msk (0x1UL << USB_OTG_DOEPINT_STPKTRX_Pos)
    -
    15087#define USB_OTG_DOEPINT_STPKTRX USB_OTG_DOEPINT_STPKTRX_Msk
    -
    15088/******************** Bit definition for USB_OTG_DOEPTSIZ register ********************/
    -
    15089
    -
    15090#define USB_OTG_DOEPTSIZ_XFRSIZ_Pos (0U)
    -
    15091#define USB_OTG_DOEPTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_DOEPTSIZ_XFRSIZ_Pos)
    -
    15092#define USB_OTG_DOEPTSIZ_XFRSIZ USB_OTG_DOEPTSIZ_XFRSIZ_Msk
    -
    15093#define USB_OTG_DOEPTSIZ_PKTCNT_Pos (19U)
    -
    15094#define USB_OTG_DOEPTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_DOEPTSIZ_PKTCNT_Pos)
    -
    15095#define USB_OTG_DOEPTSIZ_PKTCNT USB_OTG_DOEPTSIZ_PKTCNT_Msk
    -
    15097#define USB_OTG_DOEPTSIZ_STUPCNT_Pos (29U)
    -
    15098#define USB_OTG_DOEPTSIZ_STUPCNT_Msk (0x3UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos)
    -
    15099#define USB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_STUPCNT_Msk
    -
    15100#define USB_OTG_DOEPTSIZ_STUPCNT_0 (0x1UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos)
    -
    15101#define USB_OTG_DOEPTSIZ_STUPCNT_1 (0x2UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos)
    -
    15103/******************** Bit definition for PCGCCTL register ********************/
    -
    15104#define USB_OTG_PCGCCTL_STOPCLK_Pos (0U)
    -
    15105#define USB_OTG_PCGCCTL_STOPCLK_Msk (0x1UL << USB_OTG_PCGCCTL_STOPCLK_Pos)
    -
    15106#define USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STOPCLK_Msk
    -
    15107#define USB_OTG_PCGCCTL_GATECLK_Pos (1U)
    -
    15108#define USB_OTG_PCGCCTL_GATECLK_Msk (0x1UL << USB_OTG_PCGCCTL_GATECLK_Pos)
    -
    15109#define USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATECLK_Msk
    -
    15110#define USB_OTG_PCGCCTL_PHYSUSP_Pos (4U)
    -
    15111#define USB_OTG_PCGCCTL_PHYSUSP_Msk (0x1UL << USB_OTG_PCGCCTL_PHYSUSP_Pos)
    -
    15112#define USB_OTG_PCGCCTL_PHYSUSP USB_OTG_PCGCCTL_PHYSUSP_Msk
    -
    15114/* Legacy define */
    -
    15115/******************** Bit definition for OTG register ********************/
    -
    15116#define USB_OTG_CHNUM_Pos (0U)
    -
    15117#define USB_OTG_CHNUM_Msk (0xFUL << USB_OTG_CHNUM_Pos)
    -
    15118#define USB_OTG_CHNUM USB_OTG_CHNUM_Msk
    -
    15119#define USB_OTG_CHNUM_0 (0x1UL << USB_OTG_CHNUM_Pos)
    -
    15120#define USB_OTG_CHNUM_1 (0x2UL << USB_OTG_CHNUM_Pos)
    -
    15121#define USB_OTG_CHNUM_2 (0x4UL << USB_OTG_CHNUM_Pos)
    -
    15122#define USB_OTG_CHNUM_3 (0x8UL << USB_OTG_CHNUM_Pos)
    -
    15123#define USB_OTG_BCNT_Pos (4U)
    -
    15124#define USB_OTG_BCNT_Msk (0x7FFUL << USB_OTG_BCNT_Pos)
    -
    15125#define USB_OTG_BCNT USB_OTG_BCNT_Msk
    -
    15127#define USB_OTG_DPID_Pos (15U)
    -
    15128#define USB_OTG_DPID_Msk (0x3UL << USB_OTG_DPID_Pos)
    -
    15129#define USB_OTG_DPID USB_OTG_DPID_Msk
    -
    15130#define USB_OTG_DPID_0 (0x1UL << USB_OTG_DPID_Pos)
    -
    15131#define USB_OTG_DPID_1 (0x2UL << USB_OTG_DPID_Pos)
    -
    15133#define USB_OTG_PKTSTS_Pos (17U)
    -
    15134#define USB_OTG_PKTSTS_Msk (0xFUL << USB_OTG_PKTSTS_Pos)
    -
    15135#define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk
    -
    15136#define USB_OTG_PKTSTS_0 (0x1UL << USB_OTG_PKTSTS_Pos)
    -
    15137#define USB_OTG_PKTSTS_1 (0x2UL << USB_OTG_PKTSTS_Pos)
    -
    15138#define USB_OTG_PKTSTS_2 (0x4UL << USB_OTG_PKTSTS_Pos)
    -
    15139#define USB_OTG_PKTSTS_3 (0x8UL << USB_OTG_PKTSTS_Pos)
    -
    15141#define USB_OTG_EPNUM_Pos (0U)
    -
    15142#define USB_OTG_EPNUM_Msk (0xFUL << USB_OTG_EPNUM_Pos)
    -
    15143#define USB_OTG_EPNUM USB_OTG_EPNUM_Msk
    -
    15144#define USB_OTG_EPNUM_0 (0x1UL << USB_OTG_EPNUM_Pos)
    -
    15145#define USB_OTG_EPNUM_1 (0x2UL << USB_OTG_EPNUM_Pos)
    -
    15146#define USB_OTG_EPNUM_2 (0x4UL << USB_OTG_EPNUM_Pos)
    -
    15147#define USB_OTG_EPNUM_3 (0x8UL << USB_OTG_EPNUM_Pos)
    -
    15149#define USB_OTG_FRMNUM_Pos (21U)
    -
    15150#define USB_OTG_FRMNUM_Msk (0xFUL << USB_OTG_FRMNUM_Pos)
    -
    15151#define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk
    -
    15152#define USB_OTG_FRMNUM_0 (0x1UL << USB_OTG_FRMNUM_Pos)
    -
    15153#define USB_OTG_FRMNUM_1 (0x2UL << USB_OTG_FRMNUM_Pos)
    -
    15154#define USB_OTG_FRMNUM_2 (0x4UL << USB_OTG_FRMNUM_Pos)
    -
    15155#define USB_OTG_FRMNUM_3 (0x8UL << USB_OTG_FRMNUM_Pos)
    -
    -
    15168/******************************* ADC Instances ********************************/
    -
    15169#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
    -
    15170 ((INSTANCE) == ADC2) || \
    -
    -
    15171 ((INSTANCE) == ADC3))
    -
    15172
    -
    15173#define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
    -
    15174
    -
    15175#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC123_COMMON)
    -
    15176
    -
    -
    15177/******************************* CAN Instances ********************************/
    -
    15178#define IS_CAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CAN1) || \
    -
    -
    15179 ((INSTANCE) == CAN2))
    -
    15180/******************************* CRC Instances ********************************/
    -
    15181#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
    -
    15182
    -
    15183/******************************* DAC Instances ********************************/
    -
    15184#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)
    -
    15185
    -
    15186/******************************* DCMI Instances *******************************/
    -
    15187#define IS_DCMI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DCMI)
    -
    15188
    -
    -
    15189/******************************** DMA Instances *******************************/
    -
    15190#define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
    -
    15191 ((INSTANCE) == DMA1_Stream1) || \
    -
    15192 ((INSTANCE) == DMA1_Stream2) || \
    -
    15193 ((INSTANCE) == DMA1_Stream3) || \
    -
    15194 ((INSTANCE) == DMA1_Stream4) || \
    -
    15195 ((INSTANCE) == DMA1_Stream5) || \
    -
    15196 ((INSTANCE) == DMA1_Stream6) || \
    -
    15197 ((INSTANCE) == DMA1_Stream7) || \
    -
    15198 ((INSTANCE) == DMA2_Stream0) || \
    -
    15199 ((INSTANCE) == DMA2_Stream1) || \
    -
    15200 ((INSTANCE) == DMA2_Stream2) || \
    -
    15201 ((INSTANCE) == DMA2_Stream3) || \
    -
    15202 ((INSTANCE) == DMA2_Stream4) || \
    -
    15203 ((INSTANCE) == DMA2_Stream5) || \
    -
    15204 ((INSTANCE) == DMA2_Stream6) || \
    -
    -
    15205 ((INSTANCE) == DMA2_Stream7))
    -
    15206
    -
    -
    15207/******************************* GPIO Instances *******************************/
    -
    15208#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
    -
    15209 ((INSTANCE) == GPIOB) || \
    -
    15210 ((INSTANCE) == GPIOC) || \
    -
    15211 ((INSTANCE) == GPIOD) || \
    -
    15212 ((INSTANCE) == GPIOE) || \
    -
    15213 ((INSTANCE) == GPIOF) || \
    -
    15214 ((INSTANCE) == GPIOG) || \
    -
    15215 ((INSTANCE) == GPIOH) || \
    -
    -
    15216 ((INSTANCE) == GPIOI))
    -
    15217
    -
    -
    15218/******************************** I2C Instances *******************************/
    -
    15219#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
    -
    15220 ((INSTANCE) == I2C2) || \
    -
    -
    15221 ((INSTANCE) == I2C3))
    -
    15222
    -
    15223/******************************* SMBUS Instances ******************************/
    -
    15224#define IS_SMBUS_ALL_INSTANCE IS_I2C_ALL_INSTANCE
    -
    15225
    -
    15226/******************************** I2S Instances *******************************/
    -
    -
    15227
    -
    15228#define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
    -
    -
    15229 ((INSTANCE) == SPI3))
    -
    15230
    -
    -
    15231/*************************** I2S Extended Instances ***************************/
    -
    15232#define IS_I2S_EXT_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2S2ext)|| \
    -
    -
    15233 ((INSTANCE) == I2S3ext))
    -
    15234/* Legacy Defines */
    -
    15235#define IS_I2S_ALL_INSTANCE_EXT IS_I2S_EXT_ALL_INSTANCE
    -
    15236
    -
    15237/******************************* RNG Instances ********************************/
    -
    15238#define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG)
    -
    15239
    -
    15240/****************************** RTC Instances *********************************/
    -
    15241#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
    -
    15242
    -
    15243
    -
    -
    15244/******************************** SPI Instances *******************************/
    -
    15245#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
    -
    15246 ((INSTANCE) == SPI2) || \
    -
    -
    15247 ((INSTANCE) == SPI3))
    -
    15248
    -
    15249
    -
    -
    15250/****************** TIM Instances : All supported instances *******************/
    -
    15251#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
    -
    15252 ((INSTANCE) == TIM2) || \
    -
    15253 ((INSTANCE) == TIM3) || \
    -
    15254 ((INSTANCE) == TIM4) || \
    -
    15255 ((INSTANCE) == TIM5) || \
    -
    15256 ((INSTANCE) == TIM6) || \
    -
    15257 ((INSTANCE) == TIM7) || \
    -
    15258 ((INSTANCE) == TIM8) || \
    -
    15259 ((INSTANCE) == TIM9) || \
    -
    15260 ((INSTANCE) == TIM10)|| \
    -
    15261 ((INSTANCE) == TIM11)|| \
    -
    15262 ((INSTANCE) == TIM12)|| \
    -
    15263 ((INSTANCE) == TIM13)|| \
    -
    -
    15264 ((INSTANCE) == TIM14))
    -
    15265
    -
    -
    15266/************* TIM Instances : at least 1 capture/compare channel *************/
    -
    15267#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
    -
    15268 ((INSTANCE) == TIM2) || \
    -
    15269 ((INSTANCE) == TIM3) || \
    -
    15270 ((INSTANCE) == TIM4) || \
    -
    15271 ((INSTANCE) == TIM5) || \
    -
    15272 ((INSTANCE) == TIM8) || \
    -
    15273 ((INSTANCE) == TIM9) || \
    -
    15274 ((INSTANCE) == TIM10) || \
    -
    15275 ((INSTANCE) == TIM11) || \
    -
    15276 ((INSTANCE) == TIM12) || \
    -
    15277 ((INSTANCE) == TIM13) || \
    -
    -
    15278 ((INSTANCE) == TIM14))
    -
    15279
    -
    -
    15280/************ TIM Instances : at least 2 capture/compare channels *************/
    -
    15281#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
    -
    15282 ((INSTANCE) == TIM2) || \
    -
    15283 ((INSTANCE) == TIM3) || \
    -
    15284 ((INSTANCE) == TIM4) || \
    -
    15285 ((INSTANCE) == TIM5) || \
    -
    15286 ((INSTANCE) == TIM8) || \
    -
    15287 ((INSTANCE) == TIM9) || \
    -
    -
    15288 ((INSTANCE) == TIM12))
    -
    15289
    -
    -
    15290/************ TIM Instances : at least 3 capture/compare channels *************/
    -
    15291#define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
    -
    15292 ((INSTANCE) == TIM2) || \
    -
    15293 ((INSTANCE) == TIM3) || \
    -
    15294 ((INSTANCE) == TIM4) || \
    -
    15295 ((INSTANCE) == TIM5) || \
    -
    -
    15296 ((INSTANCE) == TIM8))
    -
    15297
    -
    -
    15298/************ TIM Instances : at least 4 capture/compare channels *************/
    -
    15299#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
    -
    15300 ((INSTANCE) == TIM2) || \
    -
    15301 ((INSTANCE) == TIM3) || \
    -
    15302 ((INSTANCE) == TIM4) || \
    -
    15303 ((INSTANCE) == TIM5) || \
    -
    -
    15304 ((INSTANCE) == TIM8))
    -
    15305
    -
    -
    15306/******************** TIM Instances : Advanced-control timers *****************/
    -
    15307#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
    -
    -
    15308 ((INSTANCE) == TIM8))
    -
    15309
    -
    -
    15310/******************* TIM Instances : Timer input XOR function *****************/
    -
    15311#define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
    -
    15312 ((INSTANCE) == TIM2) || \
    -
    15313 ((INSTANCE) == TIM3) || \
    -
    15314 ((INSTANCE) == TIM4) || \
    -
    15315 ((INSTANCE) == TIM5) || \
    -
    -
    15316 ((INSTANCE) == TIM8))
    -
    15317
    -
    -
    15318/****************** TIM Instances : DMA requests generation (UDE) *************/
    -
    15319#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
    -
    15320 ((INSTANCE) == TIM2) || \
    -
    15321 ((INSTANCE) == TIM3) || \
    -
    15322 ((INSTANCE) == TIM4) || \
    -
    15323 ((INSTANCE) == TIM5) || \
    -
    15324 ((INSTANCE) == TIM6) || \
    -
    15325 ((INSTANCE) == TIM7) || \
    -
    -
    15326 ((INSTANCE) == TIM8))
    -
    15327
    -
    -
    15328/************ TIM Instances : DMA requests generation (CCxDE) *****************/
    -
    15329#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
    -
    15330 ((INSTANCE) == TIM2) || \
    -
    15331 ((INSTANCE) == TIM3) || \
    -
    15332 ((INSTANCE) == TIM4) || \
    -
    15333 ((INSTANCE) == TIM5) || \
    -
    -
    15334 ((INSTANCE) == TIM8))
    -
    15335
    -
    -
    15336/************ TIM Instances : DMA requests generation (COMDE) *****************/
    -
    15337#define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
    -
    15338 ((INSTANCE) == TIM2) || \
    -
    15339 ((INSTANCE) == TIM3) || \
    -
    15340 ((INSTANCE) == TIM4) || \
    -
    15341 ((INSTANCE) == TIM5) || \
    -
    -
    15342 ((INSTANCE) == TIM8))
    -
    15343
    -
    -
    15344/******************** TIM Instances : DMA burst feature ***********************/
    -
    15345#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
    -
    15346 ((INSTANCE) == TIM2) || \
    -
    15347 ((INSTANCE) == TIM3) || \
    -
    15348 ((INSTANCE) == TIM4) || \
    -
    15349 ((INSTANCE) == TIM5) || \
    -
    -
    15350 ((INSTANCE) == TIM8))
    -
    15351
    -
    -
    15352/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
    -
    15353#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
    -
    15354 ((INSTANCE) == TIM2) || \
    -
    15355 ((INSTANCE) == TIM3) || \
    -
    15356 ((INSTANCE) == TIM4) || \
    -
    15357 ((INSTANCE) == TIM5) || \
    -
    15358 ((INSTANCE) == TIM6) || \
    -
    15359 ((INSTANCE) == TIM7) || \
    -
    -
    15360 ((INSTANCE) == TIM8))
    -
    15361
    -
    -
    15362/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
    -
    15363#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
    -
    15364 ((INSTANCE) == TIM2) || \
    -
    15365 ((INSTANCE) == TIM3) || \
    -
    15366 ((INSTANCE) == TIM4) || \
    -
    15367 ((INSTANCE) == TIM5) || \
    -
    15368 ((INSTANCE) == TIM8) || \
    -
    15369 ((INSTANCE) == TIM9) || \
    -
    -
    15370 ((INSTANCE) == TIM12))
    -
    -
    15371/********************** TIM Instances : 32 bit Counter ************************/
    -
    15372#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \
    -
    -
    15373 ((INSTANCE) == TIM5))
    -
    15374
    -
    -
    15375/***************** TIM Instances : external trigger input available ************/
    -
    15376#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
    -
    15377 ((INSTANCE) == TIM2) || \
    -
    15378 ((INSTANCE) == TIM3) || \
    -
    15379 ((INSTANCE) == TIM4) || \
    -
    15380 ((INSTANCE) == TIM5) || \
    -
    -
    15381 ((INSTANCE) == TIM8))
    -
    15382
    -
    -
    15383/****************** TIM Instances : remapping capability **********************/
    -
    15384#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
    -
    15385 ((INSTANCE) == TIM5) || \
    -
    -
    15386 ((INSTANCE) == TIM11))
    -
    15387
    -
    -
    15388/******************* TIM Instances : output(s) available **********************/
    -
    15389#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
    -
    15390 ((((INSTANCE) == TIM1) && \
    -
    15391 (((CHANNEL) == TIM_CHANNEL_1) || \
    -
    15392 ((CHANNEL) == TIM_CHANNEL_2) || \
    -
    15393 ((CHANNEL) == TIM_CHANNEL_3) || \
    -
    15394 ((CHANNEL) == TIM_CHANNEL_4))) \
    -
    15395 || \
    -
    15396 (((INSTANCE) == TIM2) && \
    -
    15397 (((CHANNEL) == TIM_CHANNEL_1) || \
    -
    15398 ((CHANNEL) == TIM_CHANNEL_2) || \
    -
    15399 ((CHANNEL) == TIM_CHANNEL_3) || \
    -
    15400 ((CHANNEL) == TIM_CHANNEL_4))) \
    -
    15401 || \
    -
    15402 (((INSTANCE) == TIM3) && \
    -
    15403 (((CHANNEL) == TIM_CHANNEL_1) || \
    -
    15404 ((CHANNEL) == TIM_CHANNEL_2) || \
    -
    15405 ((CHANNEL) == TIM_CHANNEL_3) || \
    -
    15406 ((CHANNEL) == TIM_CHANNEL_4))) \
    -
    15407 || \
    -
    15408 (((INSTANCE) == TIM4) && \
    -
    15409 (((CHANNEL) == TIM_CHANNEL_1) || \
    -
    15410 ((CHANNEL) == TIM_CHANNEL_2) || \
    -
    15411 ((CHANNEL) == TIM_CHANNEL_3) || \
    -
    15412 ((CHANNEL) == TIM_CHANNEL_4))) \
    -
    15413 || \
    -
    15414 (((INSTANCE) == TIM5) && \
    -
    15415 (((CHANNEL) == TIM_CHANNEL_1) || \
    -
    15416 ((CHANNEL) == TIM_CHANNEL_2) || \
    -
    15417 ((CHANNEL) == TIM_CHANNEL_3) || \
    -
    15418 ((CHANNEL) == TIM_CHANNEL_4))) \
    -
    15419 || \
    -
    15420 (((INSTANCE) == TIM8) && \
    -
    15421 (((CHANNEL) == TIM_CHANNEL_1) || \
    -
    15422 ((CHANNEL) == TIM_CHANNEL_2) || \
    -
    15423 ((CHANNEL) == TIM_CHANNEL_3) || \
    -
    15424 ((CHANNEL) == TIM_CHANNEL_4))) \
    -
    15425 || \
    -
    15426 (((INSTANCE) == TIM9) && \
    -
    15427 (((CHANNEL) == TIM_CHANNEL_1) || \
    -
    15428 ((CHANNEL) == TIM_CHANNEL_2))) \
    -
    15429 || \
    -
    15430 (((INSTANCE) == TIM10) && \
    -
    15431 (((CHANNEL) == TIM_CHANNEL_1))) \
    -
    15432 || \
    -
    15433 (((INSTANCE) == TIM11) && \
    -
    15434 (((CHANNEL) == TIM_CHANNEL_1))) \
    -
    15435 || \
    -
    15436 (((INSTANCE) == TIM12) && \
    -
    15437 (((CHANNEL) == TIM_CHANNEL_1) || \
    -
    15438 ((CHANNEL) == TIM_CHANNEL_2))) \
    -
    15439 || \
    -
    15440 (((INSTANCE) == TIM13) && \
    -
    15441 (((CHANNEL) == TIM_CHANNEL_1))) \
    -
    15442 || \
    -
    15443 (((INSTANCE) == TIM14) && \
    -
    -
    15444 (((CHANNEL) == TIM_CHANNEL_1))))
    -
    15445
    -
    -
    15446/************ TIM Instances : complementary output(s) available ***************/
    -
    15447#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
    -
    15448 ((((INSTANCE) == TIM1) && \
    -
    15449 (((CHANNEL) == TIM_CHANNEL_1) || \
    -
    15450 ((CHANNEL) == TIM_CHANNEL_2) || \
    -
    15451 ((CHANNEL) == TIM_CHANNEL_3))) \
    -
    15452 || \
    -
    15453 (((INSTANCE) == TIM8) && \
    -
    15454 (((CHANNEL) == TIM_CHANNEL_1) || \
    -
    15455 ((CHANNEL) == TIM_CHANNEL_2) || \
    -
    -
    15456 ((CHANNEL) == TIM_CHANNEL_3))))
    -
    15457
    -
    -
    15458/****************** TIM Instances : supporting counting mode selection ********/
    -
    15459#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
    -
    15460 ((INSTANCE) == TIM2) || \
    -
    15461 ((INSTANCE) == TIM3) || \
    -
    15462 ((INSTANCE) == TIM4) || \
    -
    15463 ((INSTANCE) == TIM5) || \
    -
    -
    15464 ((INSTANCE) == TIM8))
    -
    15465
    -
    -
    15466/****************** TIM Instances : supporting clock division *****************/
    -
    15467#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
    -
    15468 ((INSTANCE) == TIM2) || \
    -
    15469 ((INSTANCE) == TIM3) || \
    -
    15470 ((INSTANCE) == TIM4) || \
    -
    15471 ((INSTANCE) == TIM5) || \
    -
    15472 ((INSTANCE) == TIM8) || \
    -
    15473 ((INSTANCE) == TIM9) || \
    -
    15474 ((INSTANCE) == TIM10)|| \
    -
    15475 ((INSTANCE) == TIM11)|| \
    -
    15476 ((INSTANCE) == TIM12)|| \
    -
    15477 ((INSTANCE) == TIM13)|| \
    -
    -
    15478 ((INSTANCE) == TIM14))
    -
    15479
    -
    -
    15480/****************** TIM Instances : supporting commutation event generation ***/
    -
    15481#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)|| \
    -
    -
    15482 ((INSTANCE) == TIM8))
    -
    15483
    -
    15484
    -
    -
    15485/****************** TIM Instances : supporting OCxREF clear *******************/
    -
    15486#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
    -
    15487 ((INSTANCE) == TIM2) || \
    -
    15488 ((INSTANCE) == TIM3) || \
    -
    15489 ((INSTANCE) == TIM4) || \
    -
    15490 ((INSTANCE) == TIM5) || \
    -
    -
    15491 ((INSTANCE) == TIM8))
    -
    15492
    -
    -
    15493/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
    -
    15494#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
    -
    15495 ((INSTANCE) == TIM2) || \
    -
    15496 ((INSTANCE) == TIM3) || \
    -
    15497 ((INSTANCE) == TIM4) || \
    -
    15498 ((INSTANCE) == TIM5) || \
    -
    15499 ((INSTANCE) == TIM8) || \
    -
    15500 ((INSTANCE) == TIM9) || \
    -
    -
    15501 ((INSTANCE) == TIM12))
    -
    15502
    -
    -
    15503/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
    -
    15504#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
    -
    15505 ((INSTANCE) == TIM2) || \
    -
    15506 ((INSTANCE) == TIM3) || \
    -
    15507 ((INSTANCE) == TIM4) || \
    -
    15508 ((INSTANCE) == TIM5) || \
    -
    -
    15509 ((INSTANCE) == TIM8))
    -
    15510
    -
    -
    15511/****** TIM Instances : supporting external clock mode 1 for TIX inputs ******/
    -
    15512#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
    -
    15513 ((INSTANCE) == TIM2) || \
    -
    15514 ((INSTANCE) == TIM3) || \
    -
    15515 ((INSTANCE) == TIM4) || \
    -
    15516 ((INSTANCE) == TIM5) || \
    -
    15517 ((INSTANCE) == TIM8) || \
    -
    15518 ((INSTANCE) == TIM9) || \
    -
    -
    15519 ((INSTANCE) == TIM12))
    -
    15520
    -
    -
    15521/********** TIM Instances : supporting internal trigger inputs(ITRX) *********/
    -
    15522#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
    -
    15523 ((INSTANCE) == TIM2) || \
    -
    15524 ((INSTANCE) == TIM3) || \
    -
    15525 ((INSTANCE) == TIM4) || \
    -
    15526 ((INSTANCE) == TIM5) || \
    -
    15527 ((INSTANCE) == TIM8) || \
    -
    15528 ((INSTANCE) == TIM9) || \
    -
    -
    15529 ((INSTANCE) == TIM12))
    -
    15530
    -
    -
    15531/****************** TIM Instances : supporting repetition counter *************/
    -
    15532#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
    -
    -
    15533 ((INSTANCE) == TIM8))
    -
    15534
    -
    -
    15535/****************** TIM Instances : supporting encoder interface **************/
    -
    15536#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
    -
    15537 ((INSTANCE) == TIM2) || \
    -
    15538 ((INSTANCE) == TIM3) || \
    -
    15539 ((INSTANCE) == TIM4) || \
    -
    15540 ((INSTANCE) == TIM5) || \
    -
    15541 ((INSTANCE) == TIM8) || \
    -
    15542 ((INSTANCE) == TIM9) || \
    -
    -
    15543 ((INSTANCE) == TIM12))
    -
    -
    15544/****************** TIM Instances : supporting Hall sensor interface **********/
    -
    15545#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
    -
    15546 ((INSTANCE) == TIM2) || \
    -
    15547 ((INSTANCE) == TIM3) || \
    -
    15548 ((INSTANCE) == TIM4) || \
    -
    15549 ((INSTANCE) == TIM5) || \
    -
    -
    15550 ((INSTANCE) == TIM8))
    -
    -
    15551/****************** TIM Instances : supporting the break function *************/
    -
    15552#define IS_TIM_BREAK_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
    -
    -
    15553 ((INSTANCE) == TIM8))
    -
    15554
    -
    -
    15555/******************** USART Instances : Synchronous mode **********************/
    -
    15556#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
    -
    15557 ((INSTANCE) == USART2) || \
    -
    15558 ((INSTANCE) == USART3) || \
    -
    -
    15559 ((INSTANCE) == USART6))
    -
    15560
    -
    -
    15561/******************** UART Instances : Half-Duplex mode **********************/
    -
    15562#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
    -
    15563 ((INSTANCE) == USART2) || \
    -
    15564 ((INSTANCE) == USART3) || \
    -
    15565 ((INSTANCE) == UART4) || \
    -
    15566 ((INSTANCE) == UART5) || \
    -
    -
    15567 ((INSTANCE) == USART6))
    -
    15568
    -
    15569/* Legacy defines */
    -
    15570#define IS_UART_INSTANCE IS_UART_HALFDUPLEX_INSTANCE
    -
    15571
    -
    -
    15572/****************** UART Instances : Hardware Flow control ********************/
    -
    15573#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
    -
    15574 ((INSTANCE) == USART2) || \
    -
    15575 ((INSTANCE) == USART3) || \
    -
    -
    15576 ((INSTANCE) == USART6))
    -
    15577/******************** UART Instances : LIN mode **********************/
    -
    15578#define IS_UART_LIN_INSTANCE IS_UART_HALFDUPLEX_INSTANCE
    -
    15579
    -
    -
    15580/********************* UART Instances : Smart card mode ***********************/
    -
    15581#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
    -
    15582 ((INSTANCE) == USART2) || \
    -
    15583 ((INSTANCE) == USART3) || \
    -
    -
    15584 ((INSTANCE) == USART6))
    -
    15585
    -
    -
    15586/*********************** UART Instances : IRDA mode ***************************/
    -
    15587#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
    -
    15588 ((INSTANCE) == USART2) || \
    -
    15589 ((INSTANCE) == USART3) || \
    -
    15590 ((INSTANCE) == UART4) || \
    -
    15591 ((INSTANCE) == UART5) || \
    -
    -
    15592 ((INSTANCE) == USART6))
    -
    15593
    -
    15594
    -
    -
    15595/*********************** PCD Instances ****************************************/
    -
    15596#define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
    -
    -
    15597 ((INSTANCE) == USB_OTG_HS))
    -
    15598
    -
    -
    15599/*********************** HCD Instances ****************************************/
    -
    15600#define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
    -
    -
    15601 ((INSTANCE) == USB_OTG_HS))
    -
    15602
    -
    15603/****************************** SDIO Instances ********************************/
    -
    15604#define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
    -
    15605
    -
    15606/****************************** IWDG Instances ********************************/
    -
    15607#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
    -
    15608
    -
    15609/****************************** WWDG Instances ********************************/
    -
    15610#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
    -
    15611
    -
    15612/****************************** USB Exported Constants ************************/
    -
    15613#define USB_OTG_FS_HOST_MAX_CHANNEL_NBR 8U
    -
    15614#define USB_OTG_FS_MAX_IN_ENDPOINTS 4U /* Including EP0 */
    -
    15615#define USB_OTG_FS_MAX_OUT_ENDPOINTS 4U /* Including EP0 */
    -
    15616#define USB_OTG_FS_TOTAL_FIFO_SIZE 1280U /* in Bytes */
    -
    15617
    -
    15618/*
    -
    15619 * @brief Specific devices reset values definitions
    -
    15620 */
    -
    15621#define RCC_PLLCFGR_RST_VALUE 0x24003010U
    -
    15622#define RCC_PLLI2SCFGR_RST_VALUE 0x20003000U
    -
    15623
    -
    15624#define RCC_MAX_FREQUENCY 168000000U
    -
    15625#define RCC_MAX_FREQUENCY_SCALE1 RCC_MAX_FREQUENCY
    -
    15626#define RCC_MAX_FREQUENCY_SCALE2 144000000U
    -
    15627#define RCC_PLLVCO_OUTPUT_MIN 100000000U
    -
    15628#define RCC_PLLVCO_INPUT_MIN 950000U
    -
    15629#define RCC_PLLVCO_INPUT_MAX 2100000U
    -
    15630#define RCC_PLLVCO_OUTPUT_MAX 432000000U
    -
    15632#define RCC_PLLN_MIN_VALUE 50U
    -
    15633#define RCC_PLLN_MAX_VALUE 432U
    -
    15634
    -
    15635#define FLASH_SCALE1_LATENCY1_FREQ 30000000U
    -
    15636#define FLASH_SCALE1_LATENCY2_FREQ 60000000U
    -
    15637#define FLASH_SCALE1_LATENCY3_FREQ 90000000U
    -
    15638#define FLASH_SCALE1_LATENCY4_FREQ 120000000U
    -
    15639#define FLASH_SCALE1_LATENCY5_FREQ 150000000U
    -
    15641#define FLASH_SCALE2_LATENCY1_FREQ 30000000U
    -
    15642#define FLASH_SCALE2_LATENCY2_FREQ 60000000U
    -
    15643#define FLASH_SCALE2_LATENCY3_FREQ 90000000U
    -
    15644#define FLASH_SCALE2_LATENCY4_FREQ 12000000U
    -
    15646#define USB_OTG_HS_HOST_MAX_CHANNEL_NBR 12U
    -
    15647#define USB_OTG_HS_MAX_IN_ENDPOINTS 6U /* Including EP0 */
    -
    15648#define USB_OTG_HS_MAX_OUT_ENDPOINTS 6U /* Including EP0 */
    -
    15649#define USB_OTG_HS_TOTAL_FIFO_SIZE 4096U /* in Bytes */
    -
    15650/******************************************************************************/
    -
    15651/* For a painless codes migration between the STM32F4xx device product */
    -
    15652/* lines, the aliases defined below are put in place to overcome the */
    -
    15653/* differences in the interrupt handlers and IRQn definitions. */
    -
    15654/* No need to update developed interrupt code when moving across */
    -
    15655/* product lines within the same STM32F4 Family */
    -
    15656/******************************************************************************/
    -
    15657/* Aliases for __IRQn */
    -
    15658#define FMC_IRQn FSMC_IRQn
    -
    15659
    -
    15660/* Aliases for __IRQHandler */
    -
    15661#define FMC_IRQHandler FSMC_IRQHandler
    -
    15662
    -
    15675#ifdef __cplusplus
    -
    15676}
    -
    15677#endif /* __cplusplus */
    -
    15678
    -
    15679#endif /* __STM32F407xx_H */
    -
    arm_defines.h
    -
    __IO
    #define __IO
    Definition arm_defines.h:8
    -
    core_cm4_matlab.h
    -
    SDIO_TypeDef::FIFOCNT
    __IO const uint32_t FIFOCNT
    Definition stm32f407xx_matlab.h:713
    -
    USB_OTG_DeviceTypeDef::DEACHMSK
    __IO uint32_t DEACHMSK
    Definition stm32f407xx_matlab.h:847
    -
    USB_OTG_GlobalTypeDef::GRXSTSP
    __IO uint32_t GRXSTSP
    Definition stm32f407xx_matlab.h:815
    -
    CAN_TypeDef::RF1R
    __IO uint32_t RF1R
    Definition stm32f407xx_matlab.h:267
    -
    RTC_TypeDef::TSTR
    __IO uint32_t TSTR
    Definition stm32f407xx_matlab.h:660
    -
    FSMC_Bank2_3_TypeDef::ECCR2
    __IO uint32_t ECCR2
    Definition stm32f407xx_matlab.h:510
    -
    USB_OTG_INEndpointTypeDef::DIEPDMA
    __IO uint32_t DIEPDMA
    Definition stm32f407xx_matlab.h:864
    -
    USB_OTG_GlobalTypeDef::GUSBCFG
    __IO uint32_t GUSBCFG
    Definition stm32f407xx_matlab.h:810
    -
    SDIO_TypeDef::STA
    __IO const uint32_t STA
    Definition stm32f407xx_matlab.h:709
    -
    SDIO_TypeDef::ARG
    __IO uint32_t ARG
    Definition stm32f407xx_matlab.h:698
    -
    TIM_TypeDef::DIER
    __IO uint32_t DIER
    Definition stm32f407xx_matlab.h:745
    -
    ADC_TypeDef::SR
    uint32_t SR
    Definition stm32f407xx_matlab.h:192
    -
    I2C_TypeDef::OAR1
    __IO uint32_t OAR1
    Definition stm32f407xx_matlab.h:572
    -
    SYSCFG_TypeDef::CMPCR
    __IO uint32_t CMPCR
    Definition stm32f407xx_matlab.h:561
    -
    TIM_TypeDef::CCMR2
    __IO uint32_t CCMR2
    Definition stm32f407xx_matlab.h:749
    -
    USART_TypeDef::BRR
    __IO uint32_t BRR
    Definition stm32f407xx_matlab.h:773
    -
    TIM_TypeDef::CCER
    __IO uint32_t CCER
    Definition stm32f407xx_matlab.h:750
    -
    USB_OTG_HostTypeDef::HFIR
    __IO uint32_t HFIR
    Definition stm32f407xx_matlab.h:889
    -
    DCMI_TypeDef::ICR
    __IO uint32_t ICR
    Definition stm32f407xx_matlab.h:345
    -
    CAN_FIFOMailBox_TypeDef::RIR
    __IO uint32_t RIR
    Definition stm32f407xx_matlab.h:241
    -
    RTC_TypeDef::BKP3R
    __IO uint32_t BKP3R
    Definition stm32f407xx_matlab.h:671
    -
    RCC_TypeDef::BDCR
    __IO uint32_t BDCR
    Definition stm32f407xx_matlab.h:635
    -
    EXTI_TypeDef::RTSR
    __IO uint32_t RTSR
    Definition stm32f407xx_matlab.h:458
    -
    USB_OTG_GlobalTypeDef::GRXFSIZ
    __IO uint32_t GRXFSIZ
    Definition stm32f407xx_matlab.h:816
    -
    ETH_TypeDef::MACSR
    __IO uint32_t MACSR
    Definition stm32f407xx_matlab.h:394
    -
    USB_OTG_DeviceTypeDef::DOEPMSK
    __IO uint32_t DOEPMSK
    Definition stm32f407xx_matlab.h:837
    -
    ADC_TypeDef::JOFR2
    __IO uint32_t JOFR2
    Definition stm32f407xx_matlab.h:198
    -
    ETH_TypeDef::MACHTHR
    __IO uint32_t MACHTHR
    Definition stm32f407xx_matlab.h:383
    -
    ETH_TypeDef::MACRWUFFR
    __IO uint32_t MACRWUFFR
    Definition stm32f407xx_matlab.h:390
    -
    ETH_TypeDef::DMAMFBOCR
    __IO uint32_t DMAMFBOCR
    Definition stm32f407xx_matlab.h:441
    -
    ETH_TypeDef::MACFCR
    __IO uint32_t MACFCR
    Definition stm32f407xx_matlab.h:387
    -
    RTC_TypeDef::TAFCR
    __IO uint32_t TAFCR
    Definition stm32f407xx_matlab.h:664
    -
    DAC_TypeDef::DHR12RD
    __IO uint32_t DHR12RD
    Definition stm32f407xx_matlab.h:314
    -
    USB_OTG_DeviceTypeDef::Reserved20
    uint32_t Reserved20
    Definition stm32f407xx_matlab.h:840
    -
    ETH_TypeDef::MMCTIMR
    __IO uint32_t MMCTIMR
    Definition stm32f407xx_matlab.h:409
    -
    SDIO_TypeDef::RESPCMD
    __IO const uint32_t RESPCMD
    Definition stm32f407xx_matlab.h:700
    -
    USB_OTG_DeviceTypeDef::DOUTEP1MSK
    __IO uint32_t DOUTEP1MSK
    Definition stm32f407xx_matlab.h:851
    -
    TIM_TypeDef::EGR
    __IO uint32_t EGR
    Definition stm32f407xx_matlab.h:747
    -
    USB_OTG_INEndpointTypeDef::DIEPTSIZ
    __IO uint32_t DIEPTSIZ
    Definition stm32f407xx_matlab.h:863
    -
    USB_OTG_DeviceTypeDef::Reserved0C
    uint32_t Reserved0C
    Definition stm32f407xx_matlab.h:835
    -
    SDIO_TypeDef::DCOUNT
    __IO const uint32_t DCOUNT
    Definition stm32f407xx_matlab.h:708
    -
    CAN_TypeDef::FMR
    __IO uint32_t FMR
    Definition stm32f407xx_matlab.h:275
    -
    ETH_TypeDef::MACHTLR
    __IO uint32_t MACHTLR
    Definition stm32f407xx_matlab.h:384
    -
    RTC_TypeDef::TSSSR
    __IO uint32_t TSSSR
    Definition stm32f407xx_matlab.h:662
    -
    RTC_TypeDef::BKP6R
    __IO uint32_t BKP6R
    Definition stm32f407xx_matlab.h:674
    -
    SDIO_TypeDef::DTIMER
    __IO uint32_t DTIMER
    Definition stm32f407xx_matlab.h:705
    -
    FLASH_TypeDef::OPTCR1
    __IO uint32_t OPTCR1
    Definition stm32f407xx_matlab.h:476
    -
    RCC_TypeDef::AHB1ENR
    __IO uint32_t AHB1ENR
    Definition stm32f407xx_matlab.h:621
    -
    ETH_TypeDef::PTPTSHR
    __IO uint32_t PTPTSHR
    Definition stm32f407xx_matlab.h:423
    -
    ETH_TypeDef::MACCR
    __IO uint32_t MACCR
    Definition stm32f407xx_matlab.h:381
    -
    SYSCFG_TypeDef::PMC
    __IO uint32_t PMC
    Definition stm32f407xx_matlab.h:558
    -
    ADC_TypeDef::JDR1
    __IO uint32_t JDR1
    Definition stm32f407xx_matlab.h:207
    -
    RTC_TypeDef::SHIFTR
    __IO uint32_t SHIFTR
    Definition stm32f407xx_matlab.h:659
    -
    ETH_TypeDef::MMCTGFSCCR
    __IO uint32_t MMCTGFSCCR
    Definition stm32f407xx_matlab.h:411
    -
    ADC_TypeDef::HTR
    __IO uint32_t HTR
    Definition stm32f407xx_matlab.h:201
    -
    DBGMCU_TypeDef::IDCODE
    __IO uint32_t IDCODE
    Definition stm32f407xx_matlab.h:328
    -
    GPIO_TypeDef::LCKR
    __IO uint32_t LCKR
    Definition stm32f407xx_matlab.h:547
    -
    RCC_TypeDef::CFGR
    __IO uint32_t CFGR
    Definition stm32f407xx_matlab.h:612
    -
    SDIO_TypeDef::RESP3
    __IO const uint32_t RESP3
    Definition stm32f407xx_matlab.h:703
    -
    TIM_TypeDef::CCR3
    __IO uint32_t CCR3
    Definition stm32f407xx_matlab.h:757
    -
    CAN_TypeDef::MCR
    __IO uint32_t MCR
    Definition stm32f407xx_matlab.h:263
    -
    RTC_TypeDef::BKP17R
    __IO uint32_t BKP17R
    Definition stm32f407xx_matlab.h:685
    -
    RCC_TypeDef::AHB3RSTR
    __IO uint32_t AHB3RSTR
    Definition stm32f407xx_matlab.h:616
    -
    TIM_TypeDef::SMCR
    __IO uint32_t SMCR
    Definition stm32f407xx_matlab.h:744
    -
    ETH_TypeDef::PTPTTLR
    __IO uint32_t PTPTTLR
    Definition stm32f407xx_matlab.h:429
    -
    RCC_TypeDef::AHB2LPENR
    __IO uint32_t AHB2LPENR
    Definition stm32f407xx_matlab.h:629
    -
    CAN_TypeDef::ESR
    __IO uint32_t ESR
    Definition stm32f407xx_matlab.h:269
    -
    GPIO_TypeDef::MODER
    __IO uint32_t MODER
    Definition stm32f407xx_matlab.h:540
    -
    ETH_TypeDef::MACA3LR
    __IO uint32_t MACA3LR
    Definition stm32f407xx_matlab.h:403
    -
    USB_OTG_DeviceTypeDef::DAINTMSK
    __IO uint32_t DAINTMSK
    Definition stm32f407xx_matlab.h:839
    -
    RTC_TypeDef::BKP7R
    __IO uint32_t BKP7R
    Definition stm32f407xx_matlab.h:675
    -
    RTC_TypeDef::CALR
    __IO uint32_t CALR
    Definition stm32f407xx_matlab.h:663
    -
    SPI_TypeDef::RXCRCR
    __IO uint32_t RXCRCR
    Definition stm32f407xx_matlab.h:729
    -
    RCC_TypeDef::PLLI2SCFGR
    __IO uint32_t PLLI2SCFGR
    Definition stm32f407xx_matlab.h:639
    -
    DAC_TypeDef::DHR12L2
    __IO uint32_t DHR12L2
    Definition stm32f407xx_matlab.h:312
    -
    FSMC_Bank2_3_TypeDef::PMEM2
    __IO uint32_t PMEM2
    Definition stm32f407xx_matlab.h:507
    -
    ETH_TypeDef::RESERVED8
    __IO uint32_t RESERVED8
    Definition stm32f407xx_matlab.h:430
    -
    FSMC_Bank4_TypeDef::PCR4
    __IO uint32_t PCR4
    Definition stm32f407xx_matlab.h:527
    -
    IWDG_TypeDef::KR
    __IO uint32_t KR
    Definition stm32f407xx_matlab.h:587
    -
    ADC_TypeDef::JOFR4
    __IO uint32_t JOFR4
    Definition stm32f407xx_matlab.h:200
    -
    RCC_TypeDef::AHB3LPENR
    __IO uint32_t AHB3LPENR
    Definition stm32f407xx_matlab.h:630
    -
    GPIO_TypeDef::OSPEEDR
    __IO uint32_t OSPEEDR
    Definition stm32f407xx_matlab.h:542
    -
    GPIO_TypeDef::IDR
    __IO uint32_t IDR
    Definition stm32f407xx_matlab.h:544
    -
    ADC_TypeDef::SQR1
    __IO uint32_t SQR1
    Definition stm32f407xx_matlab.h:203
    -
    USB_OTG_OUTEndpointTypeDef::DOEPTSIZ
    __IO uint32_t DOEPTSIZ
    Definition stm32f407xx_matlab.h:878
    -
    ETH_TypeDef::MACA2HR
    __IO uint32_t MACA2HR
    Definition stm32f407xx_matlab.h:400
    -
    USB_OTG_HostTypeDef::HPTXSTS
    __IO uint32_t HPTXSTS
    Definition stm32f407xx_matlab.h:892
    -
    ADC_TypeDef::JDR3
    __IO uint32_t JDR3
    Definition stm32f407xx_matlab.h:209
    -
    ETH_TypeDef::MACA1HR
    __IO uint32_t MACA1HR
    Definition stm32f407xx_matlab.h:398
    -
    ADC_TypeDef::DR
    __IO uint32_t DR
    Definition stm32f407xx_matlab.h:211
    -
    FSMC_Bank4_TypeDef::PMEM4
    __IO uint32_t PMEM4
    Definition stm32f407xx_matlab.h:529
    -
    ETH_TypeDef::MACA2LR
    __IO uint32_t MACA2LR
    Definition stm32f407xx_matlab.h:401
    -
    ADC_TypeDef::JOFR1
    __IO uint32_t JOFR1
    Definition stm32f407xx_matlab.h:197
    -
    USB_OTG_INEndpointTypeDef::DTXFSTS
    __IO uint32_t DTXFSTS
    Definition stm32f407xx_matlab.h:865
    -
    SDIO_TypeDef::RESP2
    __IO const uint32_t RESP2
    Definition stm32f407xx_matlab.h:702
    -
    ETH_TypeDef::MACA0LR
    __IO uint32_t MACA0LR
    Definition stm32f407xx_matlab.h:397
    -
    DBGMCU_TypeDef::APB2FZ
    __IO uint32_t APB2FZ
    Definition stm32f407xx_matlab.h:331
    -
    RCC_TypeDef::AHB1RSTR
    __IO uint32_t AHB1RSTR
    Definition stm32f407xx_matlab.h:614
    -
    TIM_TypeDef::BDTR
    __IO uint32_t BDTR
    Definition stm32f407xx_matlab.h:759
    -
    RTC_TypeDef::BKP0R
    __IO uint32_t BKP0R
    Definition stm32f407xx_matlab.h:668
    -
    USB_OTG_DeviceTypeDef::DIEPMSK
    __IO uint32_t DIEPMSK
    Definition stm32f407xx_matlab.h:836
    -
    DAC_TypeDef::DHR8R2
    __IO uint32_t DHR8R2
    Definition stm32f407xx_matlab.h:313
    -
    CAN_TypeDef::RESERVED2
    uint32_t RESERVED2
    Definition stm32f407xx_matlab.h:277
    -
    USB_OTG_HostTypeDef::HAINTMSK
    __IO uint32_t HAINTMSK
    Definition stm32f407xx_matlab.h:894
    -
    USB_OTG_DeviceTypeDef::DAINT
    __IO uint32_t DAINT
    Definition stm32f407xx_matlab.h:838
    -
    RTC_TypeDef::ALRMBR
    __IO uint32_t ALRMBR
    Definition stm32f407xx_matlab.h:656
    -
    RTC_TypeDef::BKP19R
    __IO uint32_t BKP19R
    Definition stm32f407xx_matlab.h:687
    -
    RTC_TypeDef::ALRMBSSR
    __IO uint32_t ALRMBSSR
    Definition stm32f407xx_matlab.h:666
    -
    USB_OTG_GlobalTypeDef::GOTGCTL
    __IO uint32_t GOTGCTL
    Definition stm32f407xx_matlab.h:807
    -
    ETH_TypeDef::MMCTGFMSCCR
    __IO uint32_t MMCTGFMSCCR
    Definition stm32f407xx_matlab.h:412
    -
    DCMI_TypeDef::MISR
    __IO uint32_t MISR
    Definition stm32f407xx_matlab.h:344
    -
    _memory::PERIPH_BASE
    uint8_t PERIPH_BASE[PERIPH_SIZE]
    Definition stm32f407xx_matlab.h:966
    -
    ETH_TypeDef::PTPTSLR
    __IO uint32_t PTPTSLR
    Definition stm32f407xx_matlab.h:424
    -
    _memory::SRAM2_BASE
    uint8_t SRAM2_BASE[SRAM2_SIZE]
    Definition stm32f407xx_matlab.h:963
    -
    ETH_TypeDef::DMARDLAR
    __IO uint32_t DMARDLAR
    Definition stm32f407xx_matlab.h:436
    -
    CAN_TypeDef::BTR
    __IO uint32_t BTR
    Definition stm32f407xx_matlab.h:270
    -
    SDIO_TypeDef::MASK
    __IO uint32_t MASK
    Definition stm32f407xx_matlab.h:711
    -
    DMA_TypeDef::LISR
    __IO uint32_t LISR
    Definition stm32f407xx_matlab.h:369
    -
    I2C_TypeDef::TRISE
    __IO uint32_t TRISE
    Definition stm32f407xx_matlab.h:578
    -
    DMA_Stream_TypeDef::FCR
    __IO uint32_t FCR
    Definition stm32f407xx_matlab.h:364
    -
    _memory::SRAM2_BB_BASE
    uint8_t SRAM2_BB_BASE[SRAM2_SIZE]
    Definition stm32f407xx_matlab.h:965
    -
    USB_OTG_DeviceTypeDef::Reserved9
    uint32_t Reserved9
    Definition stm32f407xx_matlab.h:841
    -
    USART_TypeDef::GTPR
    __IO uint32_t GTPR
    Definition stm32f407xx_matlab.h:777
    -
    ADC_Common_TypeDef::CCR
    __IO uint32_t CCR
    Definition stm32f407xx_matlab.h:217
    -
    RCC_TypeDef::AHB2ENR
    __IO uint32_t AHB2ENR
    Definition stm32f407xx_matlab.h:622
    -
    DBGMCU_TypeDef::APB1FZ
    __IO uint32_t APB1FZ
    Definition stm32f407xx_matlab.h:330
    -
    CRC_TypeDef::IDR
    __IO uint8_t IDR
    Definition stm32f407xx_matlab.h:294
    -
    EXTI_TypeDef::EMR
    __IO uint32_t EMR
    Definition stm32f407xx_matlab.h:457
    -
    FSMC_Bank2_3_TypeDef::ECCR3
    __IO uint32_t ECCR3
    Definition stm32f407xx_matlab.h:518
    -
    TIM_TypeDef::CNT
    __IO uint32_t CNT
    Definition stm32f407xx_matlab.h:751
    -
    RTC_TypeDef::ALRMASSR
    __IO uint32_t ALRMASSR
    Definition stm32f407xx_matlab.h:665
    -
    SDIO_TypeDef::DLEN
    __IO uint32_t DLEN
    Definition stm32f407xx_matlab.h:706
    -
    ADC_TypeDef::JOFR3
    __IO uint32_t JOFR3
    Definition stm32f407xx_matlab.h:199
    -
    ETH_TypeDef::MMCTIR
    __IO uint32_t MMCTIR
    Definition stm32f407xx_matlab.h:407
    -
    RTC_TypeDef::WPR
    __IO uint32_t WPR
    Definition stm32f407xx_matlab.h:657
    -
    ETH_TypeDef::MMCRIMR
    __IO uint32_t MMCRIMR
    Definition stm32f407xx_matlab.h:408
    -
    DMA_Stream_TypeDef::M0AR
    __IO uint32_t M0AR
    Definition stm32f407xx_matlab.h:362
    -
    RTC_TypeDef::TR
    __IO uint32_t TR
    Definition stm32f407xx_matlab.h:648
    -
    RTC_TypeDef::BKP18R
    __IO uint32_t BKP18R
    Definition stm32f407xx_matlab.h:686
    -
    ETH_TypeDef::PTPTSLUR
    __IO uint32_t PTPTSLUR
    Definition stm32f407xx_matlab.h:426
    -
    CAN_TypeDef::IER
    __IO uint32_t IER
    Definition stm32f407xx_matlab.h:268
    -
    ETH_TypeDef::MMCRFAECR
    __IO uint32_t MMCRFAECR
    Definition stm32f407xx_matlab.h:417
    -
    SDIO_TypeDef::POWER
    __IO uint32_t POWER
    Definition stm32f407xx_matlab.h:696
    -
    USB_OTG_INEndpointTypeDef::DIEPINT
    __IO uint32_t DIEPINT
    Definition stm32f407xx_matlab.h:861
    -
    SDIO_TypeDef::FIFO
    __IO uint32_t FIFO
    Definition stm32f407xx_matlab.h:715
    -
    CAN_TxMailBox_TypeDef::TIR
    __IO uint32_t TIR
    Definition stm32f407xx_matlab.h:229
    -
    USB_OTG_GlobalTypeDef::GINTMSK
    __IO uint32_t GINTMSK
    Definition stm32f407xx_matlab.h:813
    -
    USB_OTG_HostTypeDef::HFNUM
    __IO uint32_t HFNUM
    Definition stm32f407xx_matlab.h:890
    -
    ADC_TypeDef::SMPR2
    __IO uint32_t SMPR2
    Definition stm32f407xx_matlab.h:196
    -
    RTC_TypeDef::RESERVED7
    uint32_t RESERVED7
    Definition stm32f407xx_matlab.h:667
    -
    RTC_TypeDef::BKP9R
    __IO uint32_t BKP9R
    Definition stm32f407xx_matlab.h:677
    -
    RTC_TypeDef::BKP13R
    __IO uint32_t BKP13R
    Definition stm32f407xx_matlab.h:681
    -
    USB_OTG_GlobalTypeDef::CID
    __IO uint32_t CID
    Definition stm32f407xx_matlab.h:821
    -
    RTC_TypeDef::BKP12R
    __IO uint32_t BKP12R
    Definition stm32f407xx_matlab.h:680
    -
    DMA_TypeDef::HISR
    __IO uint32_t HISR
    Definition stm32f407xx_matlab.h:370
    -
    ETH_TypeDef::MMCRGUFCR
    __IO uint32_t MMCRGUFCR
    Definition stm32f407xx_matlab.h:419
    -
    USB_OTG_GlobalTypeDef::HNPTXSTS
    __IO uint32_t HNPTXSTS
    Definition stm32f407xx_matlab.h:818
    -
    IWDG_TypeDef::RLR
    __IO uint32_t RLR
    Definition stm32f407xx_matlab.h:589
    -
    USB_OTG_INEndpointTypeDef::Reserved18
    uint32_t Reserved18
    Definition stm32f407xx_matlab.h:866
    -
    ETH_TypeDef::MMCTGFCR
    __IO uint32_t MMCTGFCR
    Definition stm32f407xx_matlab.h:414
    -
    FSMC_Bank2_3_TypeDef::PCR3
    __IO uint32_t PCR3
    Definition stm32f407xx_matlab.h:513
    -
    TIM_TypeDef::OR
    __IO uint32_t OR
    Definition stm32f407xx_matlab.h:762
    -
    ADC_TypeDef::JSQR
    __IO uint32_t JSQR
    Definition stm32f407xx_matlab.h:206
    -
    ADC_Common_TypeDef::CDR
    __IO uint32_t CDR
    Definition stm32f407xx_matlab.h:218
    -
    USB_OTG_OUTEndpointTypeDef::DOEPDMA
    __IO uint32_t DOEPDMA
    Definition stm32f407xx_matlab.h:879
    -
    RCC_TypeDef::AHB2RSTR
    __IO uint32_t AHB2RSTR
    Definition stm32f407xx_matlab.h:615
    -
    RCC_TypeDef::APB1RSTR
    __IO uint32_t APB1RSTR
    Definition stm32f407xx_matlab.h:618
    -
    SDIO_TypeDef::RESP1
    __IO const uint32_t RESP1
    Definition stm32f407xx_matlab.h:701
    -
    ETH_TypeDef::DMATDLAR
    __IO uint32_t DMATDLAR
    Definition stm32f407xx_matlab.h:437
    -
    CAN_FIFOMailBox_TypeDef::RDHR
    __IO uint32_t RDHR
    Definition stm32f407xx_matlab.h:244
    -
    CAN_FilterRegister_TypeDef::FR2
    __IO uint32_t FR2
    Definition stm32f407xx_matlab.h:254
    -
    DAC_TypeDef::DHR12R2
    __IO uint32_t DHR12R2
    Definition stm32f407xx_matlab.h:311
    -
    FSMC_Bank4_TypeDef::SR4
    __IO uint32_t SR4
    Definition stm32f407xx_matlab.h:528
    -
    CRC_TypeDef::RESERVED1
    uint16_t RESERVED1
    Definition stm32f407xx_matlab.h:296
    -
    USB_OTG_HostChannelTypeDef::HCINT
    __IO uint32_t HCINT
    Definition stm32f407xx_matlab.h:904
    -
    USB_OTG_DeviceTypeDef::DSTS
    __IO uint32_t DSTS
    Definition stm32f407xx_matlab.h:834
    -
    USB_OTG_INEndpointTypeDef::DIEPCTL
    __IO uint32_t DIEPCTL
    Definition stm32f407xx_matlab.h:859
    -
    _memory::FLASH_BASE
    uint8_t FLASH_BASE[FLASH_SIZE]
    Definition stm32f407xx_matlab.h:959
    -
    FLASH_TypeDef::KEYR
    __IO uint32_t KEYR
    Definition stm32f407xx_matlab.h:471
    -
    TIM_TypeDef::CCR4
    __IO uint32_t CCR4
    Definition stm32f407xx_matlab.h:758
    -
    ADC_Common_TypeDef::CSR
    __IO uint32_t CSR
    Definition stm32f407xx_matlab.h:216
    -
    ETH_TypeDef::MACMIIDR
    __IO uint32_t MACMIIDR
    Definition stm32f407xx_matlab.h:386
    -
    CAN_TypeDef::TSR
    __IO uint32_t TSR
    Definition stm32f407xx_matlab.h:265
    -
    FSMC_Bank2_3_TypeDef::SR2
    __IO uint32_t SR2
    Definition stm32f407xx_matlab.h:506
    -
    DAC_TypeDef::SWTRIGR
    __IO uint32_t SWTRIGR
    Definition stm32f407xx_matlab.h:307
    -
    RTC_TypeDef::SSR
    __IO uint32_t SSR
    Definition stm32f407xx_matlab.h:658
    -
    ETH_TypeDef::MACFFR
    __IO uint32_t MACFFR
    Definition stm32f407xx_matlab.h:382
    -
    ETH_TypeDef::MACDBGR
    __IO uint32_t MACDBGR
    Definition stm32f407xx_matlab.h:393
    -
    ETH_TypeDef::PTPTSAR
    __IO uint32_t PTPTSAR
    Definition stm32f407xx_matlab.h:427
    -
    ETH_TypeDef::DMACHTBAR
    __IO uint32_t DMACHTBAR
    Definition stm32f407xx_matlab.h:446
    -
    USB_OTG_OUTEndpointTypeDef::DOEPCTL
    __IO uint32_t DOEPCTL
    Definition stm32f407xx_matlab.h:874
    -
    RCC_TypeDef::CIR
    __IO uint32_t CIR
    Definition stm32f407xx_matlab.h:613
    -
    _memory::BKPSRAM_BB_BASE
    uint8_t BKPSRAM_BB_BASE[BKPSRAM_SIZE]
    Definition stm32f407xx_matlab.h:969
    -
    CAN_TxMailBox_TypeDef::TDHR
    __IO uint32_t TDHR
    Definition stm32f407xx_matlab.h:232
    -
    DCMI_TypeDef::CWSTRTR
    __IO uint32_t CWSTRTR
    Definition stm32f407xx_matlab.h:348
    -
    CAN_FilterRegister_TypeDef::FR1
    __IO uint32_t FR1
    Definition stm32f407xx_matlab.h:253
    -
    ADC_TypeDef::JDR4
    __IO uint32_t JDR4
    Definition stm32f407xx_matlab.h:210
    -
    USB_OTG_GlobalTypeDef::HPTXFSIZ
    __IO uint32_t HPTXFSIZ
    Definition stm32f407xx_matlab.h:823
    -
    ETH_TypeDef::MACVLANTR
    __IO uint32_t MACVLANTR
    Definition stm32f407xx_matlab.h:388
    -
    USB_OTG_GlobalTypeDef::DIEPTXF0_HNPTXFSIZ
    __IO uint32_t DIEPTXF0_HNPTXFSIZ
    Definition stm32f407xx_matlab.h:817
    -
    GPIO_TypeDef::OTYPER
    __IO uint32_t OTYPER
    Definition stm32f407xx_matlab.h:541
    -
    FSMC_Bank4_TypeDef::PATT4
    __IO uint32_t PATT4
    Definition stm32f407xx_matlab.h:530
    -
    CAN_FIFOMailBox_TypeDef::RDTR
    __IO uint32_t RDTR
    Definition stm32f407xx_matlab.h:242
    -
    DAC_TypeDef::DHR8RD
    __IO uint32_t DHR8RD
    Definition stm32f407xx_matlab.h:316
    -
    SDIO_TypeDef::DCTRL
    __IO uint32_t DCTRL
    Definition stm32f407xx_matlab.h:707
    -
    ADC_TypeDef::SQR3
    __IO uint32_t SQR3
    Definition stm32f407xx_matlab.h:205
    -
    USB_OTG_GlobalTypeDef::GRXSTSR
    __IO uint32_t GRXSTSR
    Definition stm32f407xx_matlab.h:814
    -
    USB_OTG_GlobalTypeDef::GINTSTS
    __IO uint32_t GINTSTS
    Definition stm32f407xx_matlab.h:812
    -
    USB_OTG_DeviceTypeDef::DIEPEMPMSK
    __IO uint32_t DIEPEMPMSK
    Definition stm32f407xx_matlab.h:845
    -
    USB_OTG_DeviceTypeDef::DCFG
    __IO uint32_t DCFG
    Definition stm32f407xx_matlab.h:832
    -
    FSMC_Bank2_3_TypeDef::PATT2
    __IO uint32_t PATT2
    Definition stm32f407xx_matlab.h:508
    -
    ETH_TypeDef::DMACHRDR
    __IO uint32_t DMACHRDR
    Definition stm32f407xx_matlab.h:445
    -
    FLASH_TypeDef::ACR
    __IO uint32_t ACR
    Definition stm32f407xx_matlab.h:470
    -
    DCMI_TypeDef::ESCR
    __IO uint32_t ESCR
    Definition stm32f407xx_matlab.h:346
    -
    TIM_TypeDef::PSC
    __IO uint32_t PSC
    Definition stm32f407xx_matlab.h:752
    -
    USB_OTG_DeviceTypeDef::Reserved40
    uint32_t Reserved40
    Definition stm32f407xx_matlab.h:848
    -
    ETH_TypeDef::DMASR
    __IO uint32_t DMASR
    Definition stm32f407xx_matlab.h:438
    -
    ETH_TypeDef::MACMIIAR
    __IO uint32_t MACMIIAR
    Definition stm32f407xx_matlab.h:385
    -
    EXTI_TypeDef::SWIER
    __IO uint32_t SWIER
    Definition stm32f407xx_matlab.h:460
    -
    ADC_TypeDef::LTR
    __IO uint32_t LTR
    Definition stm32f407xx_matlab.h:202
    -
    USB_OTG_HostTypeDef::HAINT
    __IO uint32_t HAINT
    Definition stm32f407xx_matlab.h:893
    -
    _memory::PERIPH_BB_BASE
    uint8_t PERIPH_BB_BASE[PERIPH_BB_SIZE]
    Definition stm32f407xx_matlab.h:968
    -
    SPI_TypeDef::I2SCFGR
    __IO uint32_t I2SCFGR
    Definition stm32f407xx_matlab.h:731
    -
    EXTI_TypeDef::FTSR
    __IO uint32_t FTSR
    Definition stm32f407xx_matlab.h:459
    -
    ETH_TypeDef::DMAOMR
    __IO uint32_t DMAOMR
    Definition stm32f407xx_matlab.h:439
    -
    USB_OTG_HostTypeDef::HCFG
    __IO uint32_t HCFG
    Definition stm32f407xx_matlab.h:888
    -
    DCMI_TypeDef::RISR
    __IO uint32_t RISR
    Definition stm32f407xx_matlab.h:342
    -
    TIM_TypeDef::RCR
    __IO uint32_t RCR
    Definition stm32f407xx_matlab.h:754
    -
    DCMI_TypeDef::CWSIZER
    __IO uint32_t CWSIZER
    Definition stm32f407xx_matlab.h:349
    -
    ETH_TypeDef::PTPTSCR
    __IO uint32_t PTPTSCR
    Definition stm32f407xx_matlab.h:421
    -
    DAC_TypeDef::DOR1
    __IO uint32_t DOR1
    Definition stm32f407xx_matlab.h:317
    -
    SDIO_TypeDef::RESP4
    __IO const uint32_t RESP4
    Definition stm32f407xx_matlab.h:704
    -
    CRC_TypeDef::RESERVED0
    uint8_t RESERVED0
    Definition stm32f407xx_matlab.h:295
    -
    SDIO_TypeDef::CLKCR
    __IO uint32_t CLKCR
    Definition stm32f407xx_matlab.h:697
    -
    RTC_TypeDef::BKP2R
    __IO uint32_t BKP2R
    Definition stm32f407xx_matlab.h:670
    -
    CAN_TypeDef::FM1R
    __IO uint32_t FM1R
    Definition stm32f407xx_matlab.h:276
    -
    ADC_TypeDef::SQR2
    __IO uint32_t SQR2
    Definition stm32f407xx_matlab.h:204
    -
    ETH_TypeDef::DMARPDR
    __IO uint32_t DMARPDR
    Definition stm32f407xx_matlab.h:435
    -
    RTC_TypeDef::BKP10R
    __IO uint32_t BKP10R
    Definition stm32f407xx_matlab.h:678
    -
    ETH_TypeDef::MACA1LR
    __IO uint32_t MACA1LR
    Definition stm32f407xx_matlab.h:399
    -
    CAN_TypeDef::FS1R
    __IO uint32_t FS1R
    Definition stm32f407xx_matlab.h:278
    -
    RCC_TypeDef::AHB1LPENR
    __IO uint32_t AHB1LPENR
    Definition stm32f407xx_matlab.h:628
    -
    RCC_TypeDef::SSCGR
    __IO uint32_t SSCGR
    Definition stm32f407xx_matlab.h:638
    -
    CAN_TypeDef::FA1R
    __IO uint32_t FA1R
    Definition stm32f407xx_matlab.h:282
    -
    FSMC_Bank2_3_TypeDef::PCR2
    __IO uint32_t PCR2
    Definition stm32f407xx_matlab.h:505
    -
    ADC_TypeDef::CR1
    __IO uint32_t CR1
    Definition stm32f407xx_matlab.h:193
    -
    RTC_TypeDef::BKP4R
    __IO uint32_t BKP4R
    Definition stm32f407xx_matlab.h:672
    -
    RCC_TypeDef::APB2RSTR
    __IO uint32_t APB2RSTR
    Definition stm32f407xx_matlab.h:619
    -
    SYSCFG_TypeDef::MEMRMP
    __IO uint32_t MEMRMP
    Definition stm32f407xx_matlab.h:557
    -
    RTC_TypeDef::ISR
    __IO uint32_t ISR
    Definition stm32f407xx_matlab.h:651
    -
    CRC_TypeDef::CR
    __IO uint32_t CR
    Definition stm32f407xx_matlab.h:297
    -
    SPI_TypeDef::TXCRCR
    __IO uint32_t TXCRCR
    Definition stm32f407xx_matlab.h:730
    -
    ETH_TypeDef::DMACHTDR
    __IO uint32_t DMACHTDR
    Definition stm32f407xx_matlab.h:444
    -
    I2C_TypeDef::OAR2
    __IO uint32_t OAR2
    Definition stm32f407xx_matlab.h:573
    -
    USB_OTG_DeviceTypeDef::DINEP1MSK
    __IO uint32_t DINEP1MSK
    Definition stm32f407xx_matlab.h:849
    -
    RTC_TypeDef::BKP5R
    __IO uint32_t BKP5R
    Definition stm32f407xx_matlab.h:673
    -
    ETH_TypeDef::MACA0HR
    __IO uint32_t MACA0HR
    Definition stm32f407xx_matlab.h:396
    -
    TIM_TypeDef::DMAR
    __IO uint32_t DMAR
    Definition stm32f407xx_matlab.h:761
    -
    TIM_TypeDef::CCR2
    __IO uint32_t CCR2
    Definition stm32f407xx_matlab.h:756
    -
    RTC_TypeDef::CALIBR
    __IO uint32_t CALIBR
    Definition stm32f407xx_matlab.h:654
    -
    SPI_TypeDef::I2SPR
    __IO uint32_t I2SPR
    Definition stm32f407xx_matlab.h:732
    -
    FSMC_Bank2_3_TypeDef::PATT3
    __IO uint32_t PATT3
    Definition stm32f407xx_matlab.h:516
    -
    RCC_TypeDef::APB2LPENR
    __IO uint32_t APB2LPENR
    Definition stm32f407xx_matlab.h:633
    -
    FSMC_Bank2_3_TypeDef::PMEM3
    __IO uint32_t PMEM3
    Definition stm32f407xx_matlab.h:515
    -
    DAC_TypeDef::DOR2
    __IO uint32_t DOR2
    Definition stm32f407xx_matlab.h:318
    -
    ETH_TypeDef::MACPMTCSR
    __IO uint32_t MACPMTCSR
    Definition stm32f407xx_matlab.h:391
    -
    RTC_TypeDef::TSDR
    __IO uint32_t TSDR
    Definition stm32f407xx_matlab.h:661
    -
    GPIO_TypeDef::PUPDR
    __IO uint32_t PUPDR
    Definition stm32f407xx_matlab.h:543
    -
    GPIO_TypeDef::ODR
    __IO uint32_t ODR
    Definition stm32f407xx_matlab.h:545
    -
    CAN_TypeDef::RESERVED4
    uint32_t RESERVED4
    Definition stm32f407xx_matlab.h:281
    -
    RTC_TypeDef::ALRMAR
    __IO uint32_t ALRMAR
    Definition stm32f407xx_matlab.h:655
    -
    WWDG_TypeDef::CFR
    __IO uint32_t CFR
    Definition stm32f407xx_matlab.h:787
    -
    RTC_TypeDef::BKP8R
    __IO uint32_t BKP8R
    Definition stm32f407xx_matlab.h:676
    -
    USB_OTG_HostChannelTypeDef::HCCHAR
    __IO uint32_t HCCHAR
    Definition stm32f407xx_matlab.h:902
    -
    GPIO_TypeDef::BSRR
    __IO uint32_t BSRR
    Definition stm32f407xx_matlab.h:546
    -
    DAC_TypeDef::DHR12R1
    __IO uint32_t DHR12R1
    Definition stm32f407xx_matlab.h:308
    -
    USB_OTG_GlobalTypeDef::GAHBCFG
    __IO uint32_t GAHBCFG
    Definition stm32f407xx_matlab.h:809
    -
    ETH_TypeDef::MACIMR
    __IO uint32_t MACIMR
    Definition stm32f407xx_matlab.h:395
    -
    ETH_TypeDef::RESERVED1
    uint32_t RESERVED1
    Definition stm32f407xx_matlab.h:392
    -
    DMA_TypeDef::LIFCR
    __IO uint32_t LIFCR
    Definition stm32f407xx_matlab.h:371
    -
    FSMC_Bank4_TypeDef::PIO4
    __IO uint32_t PIO4
    Definition stm32f407xx_matlab.h:531
    -
    DMA_TypeDef::HIFCR
    __IO uint32_t HIFCR
    Definition stm32f407xx_matlab.h:372
    -
    RTC_TypeDef::WUTR
    __IO uint32_t WUTR
    Definition stm32f407xx_matlab.h:653
    -
    USB_OTG_DeviceTypeDef::DTHRCTL
    __IO uint32_t DTHRCTL
    Definition stm32f407xx_matlab.h:844
    -
    RTC_TypeDef::BKP14R
    __IO uint32_t BKP14R
    Definition stm32f407xx_matlab.h:682
    -
    RTC_TypeDef::BKP11R
    __IO uint32_t BKP11R
    Definition stm32f407xx_matlab.h:679
    -
    ETH_TypeDef::DMARSWTR
    __IO uint32_t DMARSWTR
    Definition stm32f407xx_matlab.h:442
    -
    _memory::SRAM1_BASE
    uint8_t SRAM1_BASE[SRAM1_SIZE]
    Definition stm32f407xx_matlab.h:962
    -
    RCC_TypeDef::APB1ENR
    __IO uint32_t APB1ENR
    Definition stm32f407xx_matlab.h:625
    -
    _memory::SRAM1_BB_BASE
    uint8_t SRAM1_BB_BASE[SRAM1_SIZE]
    Definition stm32f407xx_matlab.h:964
    -
    RTC_TypeDef::PRER
    __IO uint32_t PRER
    Definition stm32f407xx_matlab.h:652
    -
    DAC_TypeDef::DHR12LD
    __IO uint32_t DHR12LD
    Definition stm32f407xx_matlab.h:315
    -
    RCC_TypeDef::APB2ENR
    __IO uint32_t APB2ENR
    Definition stm32f407xx_matlab.h:626
    -
    USB_OTG_DeviceTypeDef::DVBUSPULSE
    __IO uint32_t DVBUSPULSE
    Definition stm32f407xx_matlab.h:843
    -
    CAN_TypeDef::RF0R
    __IO uint32_t RF0R
    Definition stm32f407xx_matlab.h:266
    -
    _memory::CCMDATARAM_BASE
    uint8_t CCMDATARAM_BASE[CCMDATARAM_SIZE]
    Definition stm32f407xx_matlab.h:960
    -
    RCC_TypeDef::AHB3ENR
    __IO uint32_t AHB3ENR
    Definition stm32f407xx_matlab.h:623
    -
    CAN_TypeDef::MSR
    __IO uint32_t MSR
    Definition stm32f407xx_matlab.h:264
    -
    SPI_TypeDef::CRCPR
    __IO uint32_t CRCPR
    Definition stm32f407xx_matlab.h:728
    -
    _memory::FLASH_OTP_BASE
    uint8_t FLASH_OTP_BASE[FLASH_OTP_SIZE]
    Definition stm32f407xx_matlab.h:961
    -
    I2C_TypeDef::SR1
    __IO uint32_t SR1
    Definition stm32f407xx_matlab.h:575
    -
    ETH_TypeDef::DMATPDR
    __IO uint32_t DMATPDR
    Definition stm32f407xx_matlab.h:434
    -
    ETH_TypeDef::DMACHRBAR
    __IO uint32_t DMACHRBAR
    Definition stm32f407xx_matlab.h:447
    -
    USB_OTG_INEndpointTypeDef::Reserved04
    uint32_t Reserved04
    Definition stm32f407xx_matlab.h:860
    -
    FLASH_TypeDef::OPTCR
    __IO uint32_t OPTCR
    Definition stm32f407xx_matlab.h:475
    -
    ETH_TypeDef::MACA3HR
    __IO uint32_t MACA3HR
    Definition stm32f407xx_matlab.h:402
    -
    DAC_TypeDef::DHR8R1
    __IO uint32_t DHR8R1
    Definition stm32f407xx_matlab.h:310
    -
    ETH_TypeDef::DMABMR
    __IO uint32_t DMABMR
    Definition stm32f407xx_matlab.h:433
    -
    RTC_TypeDef::BKP16R
    __IO uint32_t BKP16R
    Definition stm32f407xx_matlab.h:684
    -
    ETH_TypeDef::MMCCR
    __IO uint32_t MMCCR
    Definition stm32f407xx_matlab.h:405
    -
    USB_OTG_HostChannelTypeDef::HCSPLT
    __IO uint32_t HCSPLT
    Definition stm32f407xx_matlab.h:903
    -
    RCC_TypeDef::APB1LPENR
    __IO uint32_t APB1LPENR
    Definition stm32f407xx_matlab.h:632
    -
    TIM_TypeDef::CCR1
    __IO uint32_t CCR1
    Definition stm32f407xx_matlab.h:755
    -
    TIM_TypeDef::CCMR1
    __IO uint32_t CCMR1
    Definition stm32f407xx_matlab.h:748
    -
    USB_OTG_DeviceTypeDef::DCTL
    __IO uint32_t DCTL
    Definition stm32f407xx_matlab.h:833
    -
    ETH_TypeDef::PTPTSSR
    __IO uint32_t PTPTSSR
    Definition stm32f407xx_matlab.h:431
    -
    SDIO_TypeDef::CMD
    __IO uint32_t CMD
    Definition stm32f407xx_matlab.h:699
    -
    ETH_TypeDef::DMAIER
    __IO uint32_t DMAIER
    Definition stm32f407xx_matlab.h:440
    -
    USART_TypeDef::CR3
    __IO uint32_t CR3
    Definition stm32f407xx_matlab.h:776
    -
    USB_OTG_HostChannelTypeDef::HCTSIZ
    __IO uint32_t HCTSIZ
    Definition stm32f407xx_matlab.h:906
    -
    CAN_TxMailBox_TypeDef::TDLR
    __IO uint32_t TDLR
    Definition stm32f407xx_matlab.h:231
    -
    CAN_FIFOMailBox_TypeDef::RDLR
    __IO uint32_t RDLR
    Definition stm32f407xx_matlab.h:243
    -
    _memory::BKPSRAM_BASE
    uint8_t BKPSRAM_BASE[BKPSRAM_SIZE]
    Definition stm32f407xx_matlab.h:967
    -
    USB_OTG_HostChannelTypeDef::HCINTMSK
    __IO uint32_t HCINTMSK
    Definition stm32f407xx_matlab.h:905
    -
    RCC_TypeDef::PLLCFGR
    __IO uint32_t PLLCFGR
    Definition stm32f407xx_matlab.h:611
    -
    EXTI_TypeDef::IMR
    __IO uint32_t IMR
    Definition stm32f407xx_matlab.h:456
    -
    USB_OTG_DeviceTypeDef::DEACHINT
    __IO uint32_t DEACHINT
    Definition stm32f407xx_matlab.h:846
    -
    ETH_TypeDef::PTPTSHUR
    __IO uint32_t PTPTSHUR
    Definition stm32f407xx_matlab.h:425
    -
    DAC_TypeDef::DHR12L1
    __IO uint32_t DHR12L1
    Definition stm32f407xx_matlab.h:309
    -
    ADC_TypeDef::JDR2
    __IO uint32_t JDR2
    Definition stm32f407xx_matlab.h:208
    -
    ETH_TypeDef::MMCRIR
    __IO uint32_t MMCRIR
    Definition stm32f407xx_matlab.h:406
    -
    _memory::FSMC_R_BASE
    uint8_t FSMC_R_BASE[FSMC_R_SIZE]
    Definition stm32f407xx_matlab.h:970
    -
    USB_OTG_GlobalTypeDef::GRSTCTL
    __IO uint32_t GRSTCTL
    Definition stm32f407xx_matlab.h:811
    -
    CAN_TxMailBox_TypeDef::TDTR
    __IO uint32_t TDTR
    Definition stm32f407xx_matlab.h:230
    -
    DMA_Stream_TypeDef::M1AR
    __IO uint32_t M1AR
    Definition stm32f407xx_matlab.h:363
    -
    DMA_Stream_TypeDef::PAR
    __IO uint32_t PAR
    Definition stm32f407xx_matlab.h:361
    -
    USB_OTG_GlobalTypeDef::GOTGINT
    __IO uint32_t GOTGINT
    Definition stm32f407xx_matlab.h:808
    -
    USB_OTG_GlobalTypeDef::GCCFG
    __IO uint32_t GCCFG
    Definition stm32f407xx_matlab.h:820
    -
    USB_OTG_DeviceTypeDef::DVBUSDIS
    __IO uint32_t DVBUSDIS
    Definition stm32f407xx_matlab.h:842
    -
    CAN_TypeDef::FFA1R
    __IO uint32_t FFA1R
    Definition stm32f407xx_matlab.h:280
    -
    TIM_TypeDef::ARR
    __IO uint32_t ARR
    Definition stm32f407xx_matlab.h:753
    -
    USB_OTG_HostChannelTypeDef::HCDMA
    __IO uint32_t HCDMA
    Definition stm32f407xx_matlab.h:907
    -
    CAN_TypeDef::RESERVED3
    uint32_t RESERVED3
    Definition stm32f407xx_matlab.h:279
    -
    FSMC_Bank2_3_TypeDef::SR3
    __IO uint32_t SR3
    Definition stm32f407xx_matlab.h:514
    -
    ETH_TypeDef::PTPSSIR
    __IO uint32_t PTPSSIR
    Definition stm32f407xx_matlab.h:422
    -
    DMA_Stream_TypeDef::NDTR
    __IO uint32_t NDTR
    Definition stm32f407xx_matlab.h:360
    -
    TIM_TypeDef::DCR
    __IO uint32_t DCR
    Definition stm32f407xx_matlab.h:760
    -
    USB_OTG_HostTypeDef::Reserved40C
    uint32_t Reserved40C
    Definition stm32f407xx_matlab.h:891
    -
    DAC_TypeDef::SR
    __IO uint32_t SR
    Definition stm32f407xx_matlab.h:319
    -
    DCMI_TypeDef::ESUR
    __IO uint32_t ESUR
    Definition stm32f407xx_matlab.h:347
    -
    RTC_TypeDef::BKP1R
    __IO uint32_t BKP1R
    Definition stm32f407xx_matlab.h:669
    -
    FSMC_Bank2_3_TypeDef::RESERVED0
    uint32_t RESERVED0
    Definition stm32f407xx_matlab.h:509
    -
    EXTI_TypeDef::PR
    __IO uint32_t PR
    Definition stm32f407xx_matlab.h:461
    -
    ETH_TypeDef::PTPTTHR
    __IO uint32_t PTPTTHR
    Definition stm32f407xx_matlab.h:428
    -
    ADC_TypeDef::SMPR1
    __IO uint32_t SMPR1
    Definition stm32f407xx_matlab.h:195
    -
    RTC_TypeDef::BKP15R
    __IO uint32_t BKP15R
    Definition stm32f407xx_matlab.h:683
    -
    FLASH_TypeDef::OPTKEYR
    __IO uint32_t OPTKEYR
    Definition stm32f407xx_matlab.h:472
    -
    ADC_TypeDef::CR2
    __IO uint32_t CR2
    Definition stm32f407xx_matlab.h:194
    -
    ETH_TypeDef::MMCRFCECR
    __IO uint32_t MMCRFCECR
    Definition stm32f407xx_matlab.h:416
    -
    USB_OTG_OUTEndpointTypeDef::DOEPINT
    __IO uint32_t DOEPINT
    Definition stm32f407xx_matlab.h:876
    -
    IRQn_Type
    IRQn_Type
    STM32F4XX Interrupt Number Definition, according to the selected device in Library_configuration_sect...
    Definition stm32f407xx_matlab.h:77
    -
    PendSV_IRQn
    @ PendSV_IRQn
    Definition stm32f407xx_matlab.h:85
    -
    ETH_WKUP_IRQn
    @ ETH_WKUP_IRQn
    Definition stm32f407xx_matlab.h:150
    -
    EXTI2_IRQn
    @ EXTI2_IRQn
    Definition stm32f407xx_matlab.h:96
    -
    DMA1_Stream2_IRQn
    @ DMA1_Stream2_IRQn
    Definition stm32f407xx_matlab.h:101
    -
    CAN1_SCE_IRQn
    @ CAN1_SCE_IRQn
    Definition stm32f407xx_matlab.h:110
    -
    SDIO_IRQn
    @ SDIO_IRQn
    Definition stm32f407xx_matlab.h:137
    -
    RTC_WKUP_IRQn
    @ RTC_WKUP_IRQn
    Definition stm32f407xx_matlab.h:91
    -
    OTG_HS_EP1_IN_IRQn
    @ OTG_HS_EP1_IN_IRQn
    Definition stm32f407xx_matlab.h:163
    -
    DMA2_Stream0_IRQn
    @ DMA2_Stream0_IRQn
    Definition stm32f407xx_matlab.h:144
    -
    DMA2_Stream6_IRQn
    @ DMA2_Stream6_IRQn
    Definition stm32f407xx_matlab.h:157
    -
    I2C1_ER_IRQn
    @ I2C1_ER_IRQn
    Definition stm32f407xx_matlab.h:120
    -
    I2C2_EV_IRQn
    @ I2C2_EV_IRQn
    Definition stm32f407xx_matlab.h:121
    -
    MemoryManagement_IRQn
    @ MemoryManagement_IRQn
    Definition stm32f407xx_matlab.h:80
    -
    TIM4_IRQn
    @ TIM4_IRQn
    Definition stm32f407xx_matlab.h:118
    -
    TIM2_IRQn
    @ TIM2_IRQn
    Definition stm32f407xx_matlab.h:116
    -
    DMA2_Stream7_IRQn
    @ DMA2_Stream7_IRQn
    Definition stm32f407xx_matlab.h:158
    -
    TIM8_BRK_TIM12_IRQn
    @ TIM8_BRK_TIM12_IRQn
    Definition stm32f407xx_matlab.h:131
    -
    USART2_IRQn
    @ USART2_IRQn
    Definition stm32f407xx_matlab.h:126
    -
    DMA2_Stream3_IRQn
    @ DMA2_Stream3_IRQn
    Definition stm32f407xx_matlab.h:147
    -
    SVCall_IRQn
    @ SVCall_IRQn
    Definition stm32f407xx_matlab.h:83
    -
    ADC_IRQn
    @ ADC_IRQn
    Definition stm32f407xx_matlab.h:106
    -
    SPI3_IRQn
    @ SPI3_IRQn
    Definition stm32f407xx_matlab.h:139
    -
    SPI2_IRQn
    @ SPI2_IRQn
    Definition stm32f407xx_matlab.h:124
    -
    TIM7_IRQn
    @ TIM7_IRQn
    Definition stm32f407xx_matlab.h:143
    -
    CAN2_SCE_IRQn
    @ CAN2_SCE_IRQn
    Definition stm32f407xx_matlab.h:154
    -
    RCC_IRQn
    @ RCC_IRQn
    Definition stm32f407xx_matlab.h:93
    -
    TIM6_DAC_IRQn
    @ TIM6_DAC_IRQn
    Definition stm32f407xx_matlab.h:142
    -
    OTG_HS_EP1_OUT_IRQn
    @ OTG_HS_EP1_OUT_IRQn
    Definition stm32f407xx_matlab.h:162
    -
    I2C2_ER_IRQn
    @ I2C2_ER_IRQn
    Definition stm32f407xx_matlab.h:122
    -
    TIM8_CC_IRQn
    @ TIM8_CC_IRQn
    Definition stm32f407xx_matlab.h:134
    -
    UsageFault_IRQn
    @ UsageFault_IRQn
    Definition stm32f407xx_matlab.h:82
    -
    SysTick_IRQn
    @ SysTick_IRQn
    Definition stm32f407xx_matlab.h:86
    -
    I2C3_ER_IRQn
    @ I2C3_ER_IRQn
    Definition stm32f407xx_matlab.h:161
    -
    FSMC_IRQn
    @ FSMC_IRQn
    Definition stm32f407xx_matlab.h:136
    -
    I2C3_EV_IRQn
    @ I2C3_EV_IRQn
    Definition stm32f407xx_matlab.h:160
    -
    CAN2_RX0_IRQn
    @ CAN2_RX0_IRQn
    Definition stm32f407xx_matlab.h:152
    -
    BusFault_IRQn
    @ BusFault_IRQn
    Definition stm32f407xx_matlab.h:81
    -
    DebugMonitor_IRQn
    @ DebugMonitor_IRQn
    Definition stm32f407xx_matlab.h:84
    -
    RNG_IRQn
    @ RNG_IRQn
    Definition stm32f407xx_matlab.h:167
    -
    FLASH_IRQn
    @ FLASH_IRQn
    Definition stm32f407xx_matlab.h:92
    -
    DMA2_Stream5_IRQn
    @ DMA2_Stream5_IRQn
    Definition stm32f407xx_matlab.h:156
    -
    WWDG_IRQn
    @ WWDG_IRQn
    Definition stm32f407xx_matlab.h:88
    -
    I2C1_EV_IRQn
    @ I2C1_EV_IRQn
    Definition stm32f407xx_matlab.h:119
    -
    TIM3_IRQn
    @ TIM3_IRQn
    Definition stm32f407xx_matlab.h:117
    -
    DMA2_Stream1_IRQn
    @ DMA2_Stream1_IRQn
    Definition stm32f407xx_matlab.h:145
    -
    CAN1_TX_IRQn
    @ CAN1_TX_IRQn
    Definition stm32f407xx_matlab.h:107
    -
    OTG_HS_WKUP_IRQn
    @ OTG_HS_WKUP_IRQn
    Definition stm32f407xx_matlab.h:164
    -
    DMA1_Stream0_IRQn
    @ DMA1_Stream0_IRQn
    Definition stm32f407xx_matlab.h:99
    -
    EXTI15_10_IRQn
    @ EXTI15_10_IRQn
    Definition stm32f407xx_matlab.h:128
    -
    TIM1_UP_TIM10_IRQn
    @ TIM1_UP_TIM10_IRQn
    Definition stm32f407xx_matlab.h:113
    -
    EXTI9_5_IRQn
    @ EXTI9_5_IRQn
    Definition stm32f407xx_matlab.h:111
    -
    DMA1_Stream1_IRQn
    @ DMA1_Stream1_IRQn
    Definition stm32f407xx_matlab.h:100
    -
    OTG_FS_IRQn
    @ OTG_FS_IRQn
    Definition stm32f407xx_matlab.h:155
    -
    OTG_FS_WKUP_IRQn
    @ OTG_FS_WKUP_IRQn
    Definition stm32f407xx_matlab.h:130
    -
    FPU_IRQn
    @ FPU_IRQn
    Definition stm32f407xx_matlab.h:168
    -
    TIM8_UP_TIM13_IRQn
    @ TIM8_UP_TIM13_IRQn
    Definition stm32f407xx_matlab.h:132
    -
    USART6_IRQn
    @ USART6_IRQn
    Definition stm32f407xx_matlab.h:159
    -
    SPI1_IRQn
    @ SPI1_IRQn
    Definition stm32f407xx_matlab.h:123
    -
    OTG_HS_IRQn
    @ OTG_HS_IRQn
    Definition stm32f407xx_matlab.h:165
    -
    PVD_IRQn
    @ PVD_IRQn
    Definition stm32f407xx_matlab.h:89
    -
    TIM1_TRG_COM_TIM11_IRQn
    @ TIM1_TRG_COM_TIM11_IRQn
    Definition stm32f407xx_matlab.h:114
    -
    TIM1_BRK_TIM9_IRQn
    @ TIM1_BRK_TIM9_IRQn
    Definition stm32f407xx_matlab.h:112
    -
    CAN2_RX1_IRQn
    @ CAN2_RX1_IRQn
    Definition stm32f407xx_matlab.h:153
    -
    EXTI0_IRQn
    @ EXTI0_IRQn
    Definition stm32f407xx_matlab.h:94
    -
    CAN1_RX0_IRQn
    @ CAN1_RX0_IRQn
    Definition stm32f407xx_matlab.h:108
    -
    EXTI4_IRQn
    @ EXTI4_IRQn
    Definition stm32f407xx_matlab.h:98
    -
    DMA2_Stream2_IRQn
    @ DMA2_Stream2_IRQn
    Definition stm32f407xx_matlab.h:146
    -
    TAMP_STAMP_IRQn
    @ TAMP_STAMP_IRQn
    Definition stm32f407xx_matlab.h:90
    -
    UART5_IRQn
    @ UART5_IRQn
    Definition stm32f407xx_matlab.h:141
    -
    DMA1_Stream5_IRQn
    @ DMA1_Stream5_IRQn
    Definition stm32f407xx_matlab.h:104
    -
    DCMI_IRQn
    @ DCMI_IRQn
    Definition stm32f407xx_matlab.h:166
    -
    ETH_IRQn
    @ ETH_IRQn
    Definition stm32f407xx_matlab.h:149
    -
    USART1_IRQn
    @ USART1_IRQn
    Definition stm32f407xx_matlab.h:125
    -
    EXTI3_IRQn
    @ EXTI3_IRQn
    Definition stm32f407xx_matlab.h:97
    -
    NonMaskableInt_IRQn
    @ NonMaskableInt_IRQn
    Definition stm32f407xx_matlab.h:79
    -
    UART4_IRQn
    @ UART4_IRQn
    Definition stm32f407xx_matlab.h:140
    -
    TIM8_TRG_COM_TIM14_IRQn
    @ TIM8_TRG_COM_TIM14_IRQn
    Definition stm32f407xx_matlab.h:133
    -
    EXTI1_IRQn
    @ EXTI1_IRQn
    Definition stm32f407xx_matlab.h:95
    -
    DMA2_Stream4_IRQn
    @ DMA2_Stream4_IRQn
    Definition stm32f407xx_matlab.h:148
    -
    TIM5_IRQn
    @ TIM5_IRQn
    Definition stm32f407xx_matlab.h:138
    -
    DMA1_Stream7_IRQn
    @ DMA1_Stream7_IRQn
    Definition stm32f407xx_matlab.h:135
    -
    DMA1_Stream4_IRQn
    @ DMA1_Stream4_IRQn
    Definition stm32f407xx_matlab.h:103
    -
    DMA1_Stream6_IRQn
    @ DMA1_Stream6_IRQn
    Definition stm32f407xx_matlab.h:105
    -
    TIM1_CC_IRQn
    @ TIM1_CC_IRQn
    Definition stm32f407xx_matlab.h:115
    -
    CAN2_TX_IRQn
    @ CAN2_TX_IRQn
    Definition stm32f407xx_matlab.h:151
    -
    CAN1_RX1_IRQn
    @ CAN1_RX1_IRQn
    Definition stm32f407xx_matlab.h:109
    -
    DMA1_Stream3_IRQn
    @ DMA1_Stream3_IRQn
    Definition stm32f407xx_matlab.h:102
    -
    USART3_IRQn
    @ USART3_IRQn
    Definition stm32f407xx_matlab.h:127
    -
    RTC_Alarm_IRQn
    @ RTC_Alarm_IRQn
    Definition stm32f407xx_matlab.h:129
    -
    PERIPH_BB_SIZE
    #define PERIPH_BB_SIZE
    Definition stm32f407xx_matlab.h:950
    -
    MCU_MemoryTypeDef
    struct _memory MCU_MemoryTypeDef
    -
    FSMC_R_SIZE
    #define FSMC_R_SIZE
    Definition stm32f407xx_matlab.h:952
    -
    CCMDATARAM_SIZE
    #define CCMDATARAM_SIZE
    Definition stm32f407xx_matlab.h:936
    -
    DEBUG_MCU
    DBGMCU_TypeDef DEBUG_MCU
    Definition stm32f407xx_matlab.h:973
    -
    FLASH_OTP_SIZE
    #define FLASH_OTP_SIZE
    Definition stm32f407xx_matlab.h:943
    -
    SRAM1_SIZE
    #define SRAM1_SIZE
    Definition stm32f407xx_matlab.h:937
    -
    SRAM2_SIZE
    #define SRAM2_SIZE
    Definition stm32f407xx_matlab.h:938
    -
    FLASH_SIZE
    #define FLASH_SIZE
    Definition stm32f407xx_matlab.h:941
    -
    MCU_MEM
    MCU_MemoryTypeDef MCU_MEM
    Definition stm32f4xx_matlab_conf.c:8
    -
    PERIPH_SIZE
    #define PERIPH_SIZE
    Definition stm32f407xx_matlab.h:948
    -
    BKPSRAM_SIZE
    #define BKPSRAM_SIZE
    Definition stm32f407xx_matlab.h:939
    - -
    uint32_t
    unsigned int uint32_t
    Definition stdint.h:64
    -
    uint8_t
    unsigned char uint8_t
    Definition stdint.h:62
    -
    uint16_t
    unsigned short int uint16_t
    Definition stdint.h:63
    -
    _memory
    Definition stm32f407xx_matlab.h:956
    -
    ADC_Common_TypeDef
    Definition stm32f407xx_matlab.h:215
    -
    ADC_TypeDef
    Analog to Digital Converter
    Definition stm32f407xx_matlab.h:191
    -
    CAN_FIFOMailBox_TypeDef
    Controller Area Network FIFOMailBox.
    Definition stm32f407xx_matlab.h:240
    -
    CAN_FilterRegister_TypeDef
    Controller Area Network FilterRegister.
    Definition stm32f407xx_matlab.h:252
    -
    CAN_TxMailBox_TypeDef
    Controller Area Network TxMailBox.
    Definition stm32f407xx_matlab.h:228
    -
    CAN_TypeDef
    Controller Area Network.
    Definition stm32f407xx_matlab.h:262
    -
    CRC_TypeDef
    CRC calculation unit.
    Definition stm32f407xx_matlab.h:292
    -
    DAC_TypeDef
    Digital to Analog Converter.
    Definition stm32f407xx_matlab.h:305
    -
    DBGMCU_TypeDef
    Debug MCU.
    Definition stm32f407xx_matlab.h:327
    -
    DCMI_TypeDef
    DCMI.
    Definition stm32f407xx_matlab.h:339
    -
    DMA_Stream_TypeDef
    DMA Controller.
    Definition stm32f407xx_matlab.h:358
    -
    DMA_TypeDef
    Definition stm32f407xx_matlab.h:368
    -
    ETH_TypeDef
    Ethernet MAC.
    Definition stm32f407xx_matlab.h:380
    -
    EXTI_TypeDef
    External Interrupt/Event Controller.
    Definition stm32f407xx_matlab.h:455
    -
    FLASH_TypeDef
    FLASH Registers.
    Definition stm32f407xx_matlab.h:469
    -
    FSMC_Bank1_TypeDef
    Flexible Static Memory Controller.
    Definition stm32f407xx_matlab.h:486
    -
    FSMC_Bank1E_TypeDef
    Flexible Static Memory Controller Bank1E.
    Definition stm32f407xx_matlab.h:495
    -
    FSMC_Bank2_3_TypeDef
    Flexible Static Memory Controller Bank2.
    Definition stm32f407xx_matlab.h:504
    -
    FSMC_Bank4_TypeDef
    Flexible Static Memory Controller Bank4.
    Definition stm32f407xx_matlab.h:526
    -
    GPIO_TypeDef
    General Purpose I/O.
    Definition stm32f407xx_matlab.h:539
    -
    I2C_TypeDef
    Inter-integrated Circuit Interface.
    Definition stm32f407xx_matlab.h:569
    -
    IWDG_TypeDef
    Independent WATCHDOG.
    Definition stm32f407xx_matlab.h:586
    -
    PWR_TypeDef
    Power Control.
    Definition stm32f407xx_matlab.h:599
    -
    RCC_TypeDef
    Reset and Clock Control.
    Definition stm32f407xx_matlab.h:609
    -
    RNG_TypeDef
    RNG.
    Definition stm32f407xx_matlab.h:796
    -
    RTC_TypeDef
    Real-Time Clock.
    Definition stm32f407xx_matlab.h:647
    -
    SDIO_TypeDef
    SD host Interface.
    Definition stm32f407xx_matlab.h:695
    -
    SPI_TypeDef
    Serial Peripheral Interface.
    Definition stm32f407xx_matlab.h:723
    -
    SYSCFG_TypeDef
    System configuration controller.
    Definition stm32f407xx_matlab.h:556
    -
    TIM_TypeDef
    TIM.
    Definition stm32f407xx_matlab.h:741
    -
    USART_TypeDef
    Universal Synchronous Asynchronous Receiver Transmitter.
    Definition stm32f407xx_matlab.h:770
    -
    USB_OTG_DeviceTypeDef
    USB_OTG_device_Registers.
    Definition stm32f407xx_matlab.h:831
    -
    USB_OTG_GlobalTypeDef
    USB_OTG_Core_Registers.
    Definition stm32f407xx_matlab.h:806
    -
    USB_OTG_HostChannelTypeDef
    USB_OTG_Host_Channel_Specific_Registers.
    Definition stm32f407xx_matlab.h:901
    -
    USB_OTG_HostTypeDef
    USB_OTG_Host_Mode_Register_Structures.
    Definition stm32f407xx_matlab.h:887
    -
    USB_OTG_INEndpointTypeDef
    USB_OTG_IN_Endpoint-Specific_Register.
    Definition stm32f407xx_matlab.h:858
    -
    USB_OTG_OUTEndpointTypeDef
    USB_OTG_OUT_Endpoint-Specific_Registers.
    Definition stm32f407xx_matlab.h:873
    -
    WWDG_TypeDef
    Window WATCHDOG.
    Definition stm32f407xx_matlab.h:785
    -
    system_stm32f4xx.h
    CMSIS Cortex-M4 Device System Source File for STM32F4xx devices.
    -
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    Заголовочный файл Ð´Ð»Ñ Ð¾Ð¿Ñ€ÐµÐ´ÐµÐ»ÐµÐ½Ð¸Ñ Ð¿Ð°Ð¼Ñти МК STM32F4xx. +More...

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    + + + + + + +

    +Data Structures

    struct  _cortex_memory
     
    struct  _memory
     
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

    +Macros

    #define SCS_BASE_SHIFT   (0x0000E000UL)
     
    #define ITM_BASE_SHIFT   (0x00000000UL)
     
    #define DWT_BASE_SHIFT   (0x00001000UL)
     
    #define TPI_BASE_SHIFT   (0x00040000UL)
     
    #define CoreDebug_BASE_SHIFT   (0x0000EDF0UL)
     
    #define SCS_BASE   (MCU_CORTEX_MEM.CORTEX_PERIPH_BASE) + SCS_BASE_SHIFT
     
    #define ITM_BASE   (MCU_CORTEX_MEM.CORTEX_PERIPH_BASE) + SCS_BASE_SHIFT
     
    #define DWT_BASE   (MCU_CORTEX_MEM.CORTEX_PERIPH_BASE) + SCS_BASE_SHIFT
     
    #define TPI_BASE   (MCU_CORTEX_MEM.CORTEX_PERIPH_BASE) + SCS_BASE_SHIFT
     
    #define CoreDebug_BASE   (MCU_CORTEX_MEM.CORTEX_PERIPH_BASE) + SCS_BASE_SHIFT
     
    #define SysTick_BASE   (SCS_BASE + 0x0010UL)
     
    #define NVIC_BASE   (SCS_BASE + 0x0100UL)
     
    #define SCB_BASE   (SCS_BASE + 0x0D00UL)
     
    #define SCnSCB   ((SCnSCB_Type *) SCS_BASE )
     
    #define SCB   ((SCB_Type *) SCB_BASE )
     
    #define SysTick   ((SysTick_Type *) SysTick_BASE )
     
    #define NVIC   ((NVIC_Type *) NVIC_BASE )
     
    #define ITM   ((ITM_Type *) ITM_BASE )
     
    #define DWT   ((DWT_Type *) DWT_BASE )
     
    #define TPI   ((TPI_Type *) TPI_BASE )
     
    #define FPU_BASE   (SCS_BASE + 0x0F30UL)
     
    #define FPU   ((FPU_Type *) FPU_BASE )
     
    #define FLASH_BASE_SHIFT   0x08000000UL
     
    #define FLASH_END_SHIFT   0x080FFFFFUL
     
    #define CCMDATARAM_BASE_SHIFT   0x10000000UL
     
    #define CCMDATARAM_END_SHIFT   0x1000FFFFUL
     
    #define FLASH_OTP_BASE_SHIFT   0x1FFF7800UL
     
    #define FLASH_OTP_END_SHIFT   0x1FFF7A0FUL
     
    #define SRAM1_BASE_SHIFT   0x20000000UL
     
    #define SRAM2_BASE_SHIFT   0x2001C000UL
     
    #define SRAM1_BB_BASE_SHIFT   0x22000000UL
     
    #define SRAM2_BB_BASE_SHIFT   0x22380000UL
     
    #define PERIPH_BASE_SHIFT   0x40000000UL
     
    #define BKPSRAM_BASE_SHIFT   0x40024000UL
     
    #define PERIPH_BB_BASE_SHIFT   0x42000000UL
     
    #define BKPSRAM_BB_BASE_SHIFT   0x42480000UL
     
    #define FSMC_R_BASE_SHIFT   0xA0000000UL
     
    #define MCU_MEM_END   0xA0000FFFUL
     
    #define CCMDATARAM_SIZE   0x10000UL /* (64 KB) */
     
    #define SRAM1_SIZE   0x1C000UL /* (112 KB) */
     
    #define SRAM2_SIZE   0x4000UL /* (16 KB) */
     
    #define BKPSRAM_SIZE   0x1000UL /* (4 KB) */
     
    #define FLASH_SIZE   (CCMDATARAM_BASE_SHIFT - FLASH_BASE_SHIFT)
     
    #define FLASH_OTP_SIZE   (SRAM1_BASE_SHIFT - FLASH_OTP_BASE_SHIFT)
     
    #define SRAM1_BB_SIZE   (SRAM2_BB_BASE_SHIFT - SRAM1_BB_BASE_SHIFT)
     
    #define SRAM2_BB_SIZE   (PERIPH_BASE_SHIFT - SRAM2_BB_BASE_SHIFT)
     
    #define PERIPH_SIZE   (BKPSRAM_BASE_SHIFT - PERIPH_BASE_SHIFT)
     
    #define PERIPH_BB_SIZE   (BKPSRAM_BB_BASE_SHIFT - PERIPH_BB_BASE_SHIFT)
     
    #define FSMC_R_SIZE   (MCU_MEM_END - FSMC_R_BASE_SHIFT)
     
    #define DEBUG_MCU_SIZE   (2)
     
    #define FLASH_BASE   (MCU_MEM.CCMDATARAM_BASE)
     
    #define CCMDATARAM_BASE   (MCU_MEM.CCMDATARAM_BASE)
     
    #define SRAM1_BASE   (MCU_MEM.SRAM1_BASE)
     
    #define SRAM2_BASE   (MCU_MEM.SRAM2_BASE)
     
    #define PERIPH_BASE   (MCU_MEM.PERIPH_BASE)
     
    #define BKPSRAM_BASE   (MCU_MEM.BKPSRAM_BASE)
     
    #define FSMC_R_BASE   (MCU_MEM.FSMC_R_BASE)
     
    #define SRAM1_BB_BASE   (MCU_MEM.SRAM1_BB_BASE)
     
    #define SRAM2_BB_BASE   (MCU_MEM.SRAM2_BB_BASE)
     
    #define PERIPH_BB_BASE   (MCU_MEM.PERIPH_BB_BASE)
     
    #define BKPSRAM_BB_BASE   (MCU_MEM.BKPSRAM_BB_BASE)
     
    #define FLASH_END   (MCU_MEM.FLASH_END)
     
    #define FLASH_OTP_BASE   (MCU_MEM.FLASH_OTP_BASE)
     
    #define FLASH_OTP_END   (MCU_MEM.FLASH_OTP_END)
     
    #define CCMDATARAM_END   (MCU_MEM.CCMDATARAM_END)
     
    #define DBGMCU_BASE   (MCU_MEM.DEBUG_MCU_BASE)
     
    + + + + + +

    +Typedefs

    typedef struct _cortex_memory MCU_CortexMemoryTypeDef
     
    typedef struct _memory MCU_MemoryTypeDef
     
    + + + + + +

    +Variables

    MCU_CortexMemoryTypeDef MCU_CORTEX_MEM
     
    MCU_MemoryTypeDef MCU_MEM
     
    +

    Detailed Description

    +

    Заголовочный файл Ð´Ð»Ñ Ð¾Ð¿Ñ€ÐµÐ´ÐµÐ»ÐµÐ½Ð¸Ñ Ð¿Ð°Ð¼Ñти МК STM32F4xx.

    +

    Ð’ данном файле переопределÑÑŽÑ‚ÑÑ Ð´ÐµÑ„Ð°Ð¹Ð½Ñ‹ памÑти STM32 таким образом, чтобы к ним можно было обратитьÑÑ Ð² MATLAB.

    +

    Конкретно, ÑоздаетÑÑ Ñтруктуруа Ð¸Ð¼Ð¸Ñ‚Ð¸Ñ€ÑƒÑŽÑ‰Ð°Ñ Ð¿Ð°Ð¼ÑÑ‚ÑŒ, и далее дефайны определÑÑŽÑ‚ÑÑ Ñ‚Ð°Ðº, чтобы обращатьÑÑ Ðº Ñтой Ñтруктуре, а не по абÑолютному адреÑу.

    + +

    Definition in file stm32f407xx_matlab_memory.h.

    +
    + +
    +Generated by doxygen 1.10.0 +
    + + diff --git a/DOCS/html/stm32f407xx__matlab__memory_8h_source.html b/DOCS/html/stm32f407xx__matlab__memory_8h_source.html new file mode 100644 index 0000000..21d911c --- /dev/null +++ b/DOCS/html/stm32f407xx__matlab__memory_8h_source.html @@ -0,0 +1,273 @@ + + + + + + + +STM MATLAB Simulator: F:/Work/Projects/MATLAB/matlab_stm_emulate/MCU_STM32F4xx_Matlab/Drivers/CMSIS/stm32f407xx_matlab_memory.h Source File + + + + + + + + + + + + +
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    + + + + + + +
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    stm32f407xx_matlab_memory.h
    +
    +
    +Go to the documentation of this file.
    1/**
    +
    2**************************************************************************
    +
    3* @file stm32f407xx_matlab_memory.h
    +
    4* @brief Заголовочный файл Ð´Ð»Ñ Ð¾Ð¿Ñ€ÐµÐ´ÐµÐ»ÐµÐ½Ð¸Ñ Ð¿Ð°Ð¼Ñти МК STM32F4xx.
    +
    5**************************************************************************
    +
    6@details
    +
    7Ð’ данном файле переопределÑÑŽÑ‚ÑÑ Ð´ÐµÑ„Ð°Ð¹Ð½Ñ‹ памÑти STM32 таким образом, чтобы
    +
    8к ним можно было обратитьÑÑ Ð² MATLAB.
    +
    9
    +
    10Конкретно, ÑоздаетÑÑ Ñтруктуруа Ð¸Ð¼Ð¸Ñ‚Ð¸Ñ€ÑƒÑŽÑ‰Ð°Ñ Ð¿Ð°Ð¼ÑÑ‚ÑŒ, и далее дефайны определÑÑŽÑ‚ÑÑ
    +
    11так, чтобы обращатьÑÑ Ðº Ñтой Ñтруктуре, а не по абÑолютному адреÑу.
    +
    12**************************************************************************/
    +
    13/**
    +
    14 \defgroup CMSIS_core_base Core Definitions
    +
    15 \brief Definitions for base addresses, unions, and structures.
    +
    16 @{
    +
    17 */
    +
    18
    +
    19 /* Memory mapping of Core Hardware */
    +
    20#define SCS_BASE_SHIFT (0x0000E000UL) /*!< System Control Space Base Address */
    +
    21#define ITM_BASE_SHIFT (0x00000000UL) /*!< ITM Base Address */
    +
    22#define DWT_BASE_SHIFT (0x00001000UL) /*!< DWT Base Address */
    +
    23#define TPI_BASE_SHIFT (0x00040000UL) /*!< TPI Base Address */
    +
    24#define CoreDebug_BASE_SHIFT (0x0000EDF0UL) /*!< Core Debug Base Address */
    +
    25
    +
    +
    26typedef struct _cortex_memory
    +
    27{
    +
    28 uint8_t CORTEX_PERIPH_BASE[0xE0100000 - 0xE0000000];
    +
    29}MCU_CortexMemoryTypeDef;
    +
    +
    30extern MCU_CortexMemoryTypeDef MCU_CORTEX_MEM;
    +
    31
    +
    32#define SCS_BASE (MCU_CORTEX_MEM.CORTEX_PERIPH_BASE) + SCS_BASE_SHIFT /*!< System Control Space Base Address */
    +
    33#define ITM_BASE (MCU_CORTEX_MEM.CORTEX_PERIPH_BASE) + SCS_BASE_SHIFT /*!< ITM Base Address */
    +
    34#define DWT_BASE (MCU_CORTEX_MEM.CORTEX_PERIPH_BASE) + SCS_BASE_SHIFT /*!< DWT Base Address */
    +
    35#define TPI_BASE (MCU_CORTEX_MEM.CORTEX_PERIPH_BASE) + SCS_BASE_SHIFT /*!< TPI Base Address */
    +
    36#define CoreDebug_BASE (MCU_CORTEX_MEM.CORTEX_PERIPH_BASE) + SCS_BASE_SHIFT /*!< Core Debug Base Address */
    +
    37#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
    +
    38#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
    +
    39#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
    +
    40
    +
    41#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
    +
    42#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
    +
    43#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
    +
    44#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
    +
    45#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
    +
    46#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
    +
    47#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
    +
    48
    +
    49#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
    +
    50#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
    +
    51#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
    +
    52#endif
    +
    53
    +
    54#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
    +
    55#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
    +
    56
    +
    57/**
    +
    58 * @}
    +
    59 */
    +
    60
    +
    61
    +
    62
    +
    63/** @ingroup CMSIS_core_base
    +
    64 * @addtogroup Peripheral_memory_map Peripheral Memory Map
    +
    65 * @{
    +
    66 */
    +
    67
    +
    68#define FLASH_BASE_SHIFT 0x08000000UL /*!< FLASH(up to 1 MB) base address in the alias region */
    +
    69#define FLASH_END_SHIFT 0x080FFFFFUL /*!< FLASH end address */
    +
    70#define CCMDATARAM_BASE_SHIFT 0x10000000UL /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region */
    +
    71#define CCMDATARAM_END_SHIFT 0x1000FFFFUL /*!< CCM data RAM end address */
    +
    72#define FLASH_OTP_BASE_SHIFT 0x1FFF7800UL /*!< Base address of : (up to 528 Bytes) embedded FLASH OTP Area */
    +
    73#define FLASH_OTP_END_SHIFT 0x1FFF7A0FUL /*!< End address of : (up to 528 Bytes) embedded FLASH OTP Area */
    +
    74#define SRAM1_BASE_SHIFT 0x20000000UL /*!< SRAM1(112 KB) base address in the alias region */
    +
    75#define SRAM2_BASE_SHIFT 0x2001C000UL /*!< SRAM2(16 KB) base address in the alias region */
    +
    76#define SRAM1_BB_BASE_SHIFT 0x22000000UL /*!< SRAM1(112 KB) base address in the bit-band region */
    +
    77#define SRAM2_BB_BASE_SHIFT 0x22380000UL /*!< SRAM2(16 KB) base address in the bit-band region */
    +
    78#define PERIPH_BASE_SHIFT 0x40000000UL /*!< Peripheral base address in the alias region */
    +
    79#define BKPSRAM_BASE_SHIFT 0x40024000UL /*!< Backup SRAM(4 KB) base address in the alias region */
    +
    80#define PERIPH_BB_BASE_SHIFT 0x42000000UL /*!< Peripheral base address in the bit-band region */
    +
    81#define BKPSRAM_BB_BASE_SHIFT 0x42480000UL /*!< Backup SRAM(4 KB) base address in the bit-band region */
    +
    82#define FSMC_R_BASE_SHIFT 0xA0000000UL /*!< FSMC registers base address */
    +
    83
    +
    84#define MCU_MEM_END 0xA0000FFFUL /*!< CCM data RAM end address */
    +
    85
    +
    86#define CCMDATARAM_SIZE 0x10000UL /* (64 KB) */
    +
    87#define SRAM1_SIZE 0x1C000UL /* (112 KB) */
    +
    88#define SRAM2_SIZE 0x4000UL /* (16 KB) */
    +
    89#define BKPSRAM_SIZE 0x1000UL /* (4 KB) */
    +
    90
    +
    91#define FLASH_SIZE (CCMDATARAM_BASE_SHIFT - FLASH_BASE_SHIFT)
    +
    92 //#define CCMDATARAM_SIZE (FLASH_OTP_BASE_SHIFT - CCMDATARAM_BASE_SHIFT)
    +
    93#define FLASH_OTP_SIZE (SRAM1_BASE_SHIFT - FLASH_OTP_BASE_SHIFT)
    +
    94//#define SRAM1_SIZE (SRAM2_BASE_SHIFT - SRAM1_BASE_SHIFT)
    +
    95//#define SRAM2_SIZE (SRAM1_BB_BASE_SHIFT - SRAM2_BASE_SHIFT)
    +
    96#define SRAM1_BB_SIZE (SRAM2_BB_BASE_SHIFT - SRAM1_BB_BASE_SHIFT)
    +
    97#define SRAM2_BB_SIZE (PERIPH_BASE_SHIFT - SRAM2_BB_BASE_SHIFT)
    +
    98#define PERIPH_SIZE (BKPSRAM_BASE_SHIFT - PERIPH_BASE_SHIFT)
    +
    99//#define BKPSRAM_SIZE (PERIPH_BB_BASE_SHIFT - BKPSRAM_BASE_SHIFT)
    +
    100#define PERIPH_BB_SIZE (BKPSRAM_BB_BASE_SHIFT - PERIPH_BB_BASE_SHIFT)
    +
    101//#define BKPSRAM_BB_SIZE (FSMC_R_BASE_SHIFT - BKPSRAM_BB_BASE_SHIFT)
    +
    102#define FSMC_R_SIZE (MCU_MEM_END - FSMC_R_BASE_SHIFT)
    +
    103#define DEBUG_MCU_SIZE (2)
    +
    104
    +
    105
    + +
    124extern MCU_MemoryTypeDef MCU_MEM;
    +
    125
    +
    126#define FLASH_BASE (MCU_MEM.CCMDATARAM_BASE) /*!< FLASH(up to 1 MB) base address in the alias region */
    +
    127#define CCMDATARAM_BASE (MCU_MEM.CCMDATARAM_BASE) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region */
    +
    128#define SRAM1_BASE (MCU_MEM.SRAM1_BASE) /*!< SRAM1(112 KB) base address in the alias region */
    +
    129#define SRAM2_BASE (MCU_MEM.SRAM2_BASE) /*!< SRAM2(16 KB) base address in the alias region */
    +
    130#define PERIPH_BASE (MCU_MEM.PERIPH_BASE) /*!< Peripheral base address in the alias region */
    +
    131#define BKPSRAM_BASE (MCU_MEM.BKPSRAM_BASE) /*!< Backup SRAM(4 KB) base address in the alias region */
    +
    132#define FSMC_R_BASE (MCU_MEM.FSMC_R_BASE) /*!< FSMC registers base address */
    +
    133#define SRAM1_BB_BASE (MCU_MEM.SRAM1_BB_BASE) /*!< SRAM1(112 KB) base address in the bit-band region */
    +
    134#define SRAM2_BB_BASE (MCU_MEM.SRAM2_BB_BASE) /*!< SRAM2(16 KB) base address in the bit-band region */
    +
    135#define PERIPH_BB_BASE (MCU_MEM.PERIPH_BB_BASE) /*!< Peripheral base address in the bit-band region */
    +
    136#define BKPSRAM_BB_BASE (MCU_MEM.BKPSRAM_BB_BASE) /*!< Backup SRAM(4 KB) base address in the bit-band region */
    +
    137#define FLASH_END (MCU_MEM.FLASH_END) /*!< FLASH end address */
    +
    138#define FLASH_OTP_BASE (MCU_MEM.FLASH_OTP_BASE) /*!< Base address of : (up to 528 Bytes) embedded FLASH OTP Area */
    +
    139#define FLASH_OTP_END (MCU_MEM.FLASH_OTP_END) /*!< End address of : (up to 528 Bytes) embedded FLASH OTP Area */
    +
    140#define CCMDATARAM_END (MCU_MEM.CCMDATARAM_END) /*!< CCM data RAM end address */
    +
    141
    +
    142/*!< Debug MCU registers base address */
    +
    143#define DBGMCU_BASE (MCU_MEM.DEBUG_MCU_BASE)
    +
    144/**
    +
    145 * @}
    +
    146 */
    +
    MCU_CortexMemoryTypeDef
    struct _cortex_memory MCU_CortexMemoryTypeDef
    +
    MCU_CORTEX_MEM
    MCU_CortexMemoryTypeDef MCU_CORTEX_MEM
    Definition stm32f4xx_matlab_conf.c:14
    +
    PERIPH_BB_SIZE
    #define PERIPH_BB_SIZE
    Definition stm32f407xx_matlab_memory.h:100
    +
    MCU_MemoryTypeDef
    struct _memory MCU_MemoryTypeDef
    +
    FSMC_R_SIZE
    #define FSMC_R_SIZE
    Definition stm32f407xx_matlab_memory.h:102
    +
    DEBUG_MCU_SIZE
    #define DEBUG_MCU_SIZE
    Definition stm32f407xx_matlab_memory.h:103
    +
    CCMDATARAM_SIZE
    #define CCMDATARAM_SIZE
    Definition stm32f407xx_matlab_memory.h:86
    +
    FLASH_OTP_SIZE
    #define FLASH_OTP_SIZE
    Definition stm32f407xx_matlab_memory.h:93
    +
    SRAM1_SIZE
    #define SRAM1_SIZE
    Definition stm32f407xx_matlab_memory.h:87
    +
    SRAM2_SIZE
    #define SRAM2_SIZE
    Definition stm32f407xx_matlab_memory.h:88
    +
    FLASH_SIZE
    #define FLASH_SIZE
    Definition stm32f407xx_matlab_memory.h:91
    +
    MCU_MEM
    MCU_MemoryTypeDef MCU_MEM
    Definition stm32f4xx_matlab_conf.c:13
    +
    PERIPH_SIZE
    #define PERIPH_SIZE
    Definition stm32f407xx_matlab_memory.h:98
    +
    BKPSRAM_SIZE
    #define BKPSRAM_SIZE
    Definition stm32f407xx_matlab_memory.h:89
    +
    _cortex_memory
    Definition stm32f407xx_matlab_memory.h:27
    +
    _cortex_memory::CORTEX_PERIPH_BASE
    uint8_t CORTEX_PERIPH_BASE[0xE0100000 - 0xE0000000]
    Definition stm32f407xx_matlab_memory.h:28
    +
    _memory
    Definition stm32f407xx_matlab_memory.h:107
    +
    _memory::DEBUG_MCU_BASE
    uint8_t DEBUG_MCU_BASE[DEBUG_MCU_SIZE]
    Definition stm32f407xx_matlab_memory.h:122
    +
    _memory::PERIPH_BASE
    uint8_t PERIPH_BASE[PERIPH_SIZE]
    Definition stm32f407xx_matlab_memory.h:117
    +
    _memory::SRAM2_BASE
    uint8_t SRAM2_BASE[SRAM2_SIZE]
    Definition stm32f407xx_matlab_memory.h:114
    +
    _memory::SRAM2_BB_BASE
    uint8_t SRAM2_BB_BASE[SRAM2_SIZE]
    Definition stm32f407xx_matlab_memory.h:116
    +
    _memory::FLASH_BASE
    uint8_t FLASH_BASE[FLASH_SIZE]
    Definition stm32f407xx_matlab_memory.h:110
    +
    _memory::BKPSRAM_BB_BASE
    uint8_t BKPSRAM_BB_BASE[BKPSRAM_SIZE]
    Definition stm32f407xx_matlab_memory.h:120
    +
    _memory::PERIPH_BB_BASE
    uint8_t PERIPH_BB_BASE[PERIPH_BB_SIZE]
    Definition stm32f407xx_matlab_memory.h:119
    +
    _memory::SRAM1_BASE
    uint8_t SRAM1_BASE[SRAM1_SIZE]
    Definition stm32f407xx_matlab_memory.h:113
    +
    _memory::SRAM1_BB_BASE
    uint8_t SRAM1_BB_BASE[SRAM1_SIZE]
    Definition stm32f407xx_matlab_memory.h:115
    +
    _memory::CCMDATARAM_BASE
    uint8_t CCMDATARAM_BASE[CCMDATARAM_SIZE]
    Definition stm32f407xx_matlab_memory.h:111
    +
    _memory::FLASH_OTP_BASE
    uint8_t FLASH_OTP_BASE[FLASH_OTP_SIZE]
    Definition stm32f407xx_matlab_memory.h:112
    +
    _memory::BKPSRAM_BASE
    uint8_t BKPSRAM_BASE[BKPSRAM_SIZE]
    Definition stm32f407xx_matlab_memory.h:118
    +
    _memory::FSMC_R_BASE
    uint8_t FSMC_R_BASE[FSMC_R_SIZE]
    Definition stm32f407xx_matlab_memory.h:121
    +
    + +
    +Generated by doxygen 1.10.0 +
    + + diff --git a/DOCS/html/stm32f4xx_8h.html b/DOCS/html/stm32f4xx_8h.html deleted file mode 100644 index 6498073..0000000 --- a/DOCS/html/stm32f4xx_8h.html +++ /dev/null @@ -1,161 +0,0 @@ - - - - - - - -STM MATLAB Simulator: F:/Work/Projects/MATLAB/matlab_stm_emulate/MCU_STM32F4xx_Matlab/Drivers/CMSIS/stm32f4xx.h File Reference - - - - - - - - - - - -
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    #define STM32F4
     STM32 Family.
     
    #define __STM32F4xx_CMSIS_VERSION_MAIN   (0x02U)
     Comment the line below if you will not use the peripherals drivers. In this case, these drivers will not be included and the application code will be based on direct access to peripherals registers.
     
    #define __STM32F4xx_CMSIS_VERSION_SUB1   (0x06U)
     
    #define __STM32F4xx_CMSIS_VERSION_SUB2   (0x08U)
     
    #define __STM32F4xx_CMSIS_VERSION_RC   (0x00U)
     
    #define __STM32F4xx_CMSIS_VERSION
     
    #define IS_FUNCTIONAL_STATE(STATE)   (((STATE) == DISABLE) || ((STATE) == ENABLE))
     
    #define SET_BIT(REG, BIT)   ((REG) |= (BIT))
     
    #define CLEAR_BIT(REG, BIT)   ((REG) &= ~(BIT))
     
    #define READ_BIT(REG, BIT)   ((REG) & (BIT))
     
    #define CLEAR_REG(REG)   ((REG) = (0x0))
     
    #define WRITE_REG(REG, VAL)   ((REG) = (VAL))
     
    #define READ_REG(REG)   ((REG))
     
    #define MODIFY_REG(REG, CLEARMASK, SETMASK)   WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
     
    #define POSITION_VAL(VAL)   (__CLZ(__RBIT(VAL)))
     
    #define ATOMIC_SET_BIT(REG, BIT)
     
    #define ATOMIC_CLEAR_BIT(REG, BIT)
     
    #define ATOMIC_MODIFY_REG(REG, CLEARMSK, SETMASK)
     
    #define ATOMIC_SETH_BIT(REG, BIT)
     
    #define ATOMIC_CLEARH_BIT(REG, BIT)
     
    #define ATOMIC_MODIFYH_REG(REG, CLEARMSK, SETMASK)
     
    - - - -

    -Typedefs

    typedef enum FlagStatus ITStatus
     
    - - - - - - - -

    -Enumerations

    enum  FlagStatus { RESET = 0U -, SET = !RESET - }
     
    enum  FunctionalState { DISABLE = 0U -, ENABLE = !DISABLE - }
     
    enum  ErrorStatus { SUCCESS = 0U -, ERROR = !SUCCESS - }
     
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    1
    -
    37#ifndef __STM32F4xx_H
    -
    38#define __STM32F4xx_H
    -
    39
    -
    40#ifdef __cplusplus
    -
    41 extern "C" {
    -
    42#endif /* __cplusplus */
    -
    43
    -
    51#if !defined (STM32F4)
    -
    52#define STM32F4
    -
    53#endif /* STM32F4 */
    -
    54
    -
    55/* Uncomment the line below according to the target STM32 device used in your
    -
    56 application
    -
    57 */
    -
    58#if !defined (STM32F405xx) && !defined (STM32F415xx) && !defined (STM32F407xx) && !defined (STM32F417xx) && \
    -
    59 !defined (STM32F427xx) && !defined (STM32F437xx) && !defined (STM32F429xx) && !defined (STM32F439xx) && \
    -
    60 !defined (STM32F401xC) && !defined (STM32F401xE) && !defined (STM32F410Tx) && !defined (STM32F410Cx) && \
    -
    61 !defined (STM32F410Rx) && !defined (STM32F411xE) && !defined (STM32F446xx) && !defined (STM32F469xx) && \
    -
    62 !defined (STM32F479xx) && !defined (STM32F412Cx) && !defined (STM32F412Rx) && !defined (STM32F412Vx) && \
    -
    63 !defined (STM32F412Zx) && !defined (STM32F413xx) && !defined (STM32F423xx)
    -
    64 /* #define STM32F405xx */
    -
    65 /* #define STM32F415xx */
    -
    66 /* #define STM32F407xx */
    -
    67 /* #define STM32F417xx */
    -
    68 /* #define STM32F427xx */
    -
    69 /* #define STM32F437xx */
    -
    70 /* #define STM32F429xx */
    -
    72 /* #define STM32F439xx */
    -
    74 /* #define STM32F401xC */
    -
    75 /* #define STM32F401xE */
    -
    76 /* #define STM32F410Tx */
    -
    77 /* #define STM32F410Cx */
    -
    78 /* #define STM32F410Rx */
    -
    79 /* #define STM32F411xE */
    -
    80 /* #define STM32F446xx */
    -
    82 /* #define STM32F469xx */
    -
    84 /* #define STM32F479xx */
    -
    86 /* #define STM32F412Cx */
    -
    87 /* #define STM32F412Zx */
    -
    88 /* #define STM32F412Vx */
    -
    89 /* #define STM32F412Rx */
    -
    90 /* #define STM32F413xx */
    -
    92 /* #define STM32F423xx */
    -
    93#endif
    -
    94
    -
    95/* Tip: To avoid modifying this file each time you need to switch between these
    -
    96 devices, you can define the device in your toolchain compiler preprocessor.
    -
    97 */
    -
    98#if !defined (USE_HAL_DRIVER)
    -
    104 /*#define USE_HAL_DRIVER */
    -
    105#endif /* USE_HAL_DRIVER */
    -
    106
    -
    110#define __STM32F4xx_CMSIS_VERSION_MAIN (0x02U)
    -
    111#define __STM32F4xx_CMSIS_VERSION_SUB1 (0x06U)
    -
    112#define __STM32F4xx_CMSIS_VERSION_SUB2 (0x08U)
    -
    113#define __STM32F4xx_CMSIS_VERSION_RC (0x00U)
    -
    -
    114#define __STM32F4xx_CMSIS_VERSION ((__STM32F4xx_CMSIS_VERSION_MAIN << 24)\
    -
    115 |(__STM32F4xx_CMSIS_VERSION_SUB1 << 16)\
    -
    116 |(__STM32F4xx_CMSIS_VERSION_SUB2 << 8 )\
    -
    117 |(__STM32F4xx_CMSIS_VERSION_RC))
    -
    -
    118
    -
    127#if defined(STM32F405xx)
    -
    128 #include "stm32f405xx_matlab.h"
    -
    129#elif defined(STM32F415xx)
    -
    130 #include "stm32f415xx_matlab.h"
    -
    131#elif defined(STM32F407xx)
    -
    132 #include "stm32f407xx_matlab.h"
    -
    133#elif defined(STM32F417xx)
    -
    134 #include "stm32f417xx_matlab.h"
    -
    135#elif defined(STM32F427xx)
    -
    136 #include "stm32f427xx_matlab.h"
    -
    137#elif defined(STM32F437xx)
    -
    138 #include "stm32f437xx_matlab.h"
    -
    139#elif defined(STM32F429xx)
    -
    140 #include "stm32f429xx_matlab.h"
    -
    141#elif defined(STM32F439xx)
    -
    142 #include "stm32f439xx_matlab.h"
    -
    143#elif defined(STM32F401xC)
    -
    144 #include "stm32f401xc_matlab.h"
    -
    145#elif defined(STM32F401xE)
    -
    146 #include "stm32f401xe_matlab.h"
    -
    147#elif defined(STM32F410Tx)
    -
    148 #include "stm32f410tx_matlab.h"
    -
    149#elif defined(STM32F410Cx)
    -
    150 #include "stm32f410cx_matlab.h"
    -
    151#elif defined(STM32F410Rx)
    -
    152 #include "stm32f410rx_matlab.h"
    -
    153#elif defined(STM32F411xE)
    -
    154 #include "stm32f411xe_matlab.h"
    -
    155#elif defined(STM32F446xx)
    -
    156 #include "stm32f446xx_matlab.h"
    -
    157#elif defined(STM32F469xx)
    -
    158 #include "stm32f469xx_matlab.h"
    -
    159#elif defined(STM32F479xx)
    -
    160 #include "stm32f479xx_matlab.h"
    -
    161#elif defined(STM32F412Cx)
    -
    162 #include "stm32f412cx_matlab.h"
    -
    163#elif defined(STM32F412Zx)
    -
    164 #include "stm32f412zx_matlab.h"
    -
    165#elif defined(STM32F412Rx)
    -
    166 #include "stm32f412rx_matlab.h"
    -
    167#elif defined(STM32F412Vx)
    -
    168 #include "stm32f412vx_matlab.h"
    -
    169#elif defined(STM32F413xx)
    -
    170 #include "stm32f413xx_matlab.h"
    -
    171#elif defined(STM32F423xx)
    -
    172 #include "stm32f423xx_matlab.h"
    -
    173#else
    -
    174 #error "Please select first the target STM32F4xx device used in your application (in stm32f4xx_matlab.h file)"
    -
    175#endif
    -
    176
    -
    -
    184typedef enum
    -
    185{
    -
    186 RESET = 0U,
    -
    187 SET = !RESET
    -
    188} FlagStatus, ITStatus;
    -
    -
    189
    -
    -
    190typedef enum
    -
    191{
    -
    192 DISABLE = 0U,
    -
    193 ENABLE = !DISABLE
    -
    194} FunctionalState;
    -
    -
    195#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
    -
    196
    -
    -
    197typedef enum
    -
    198{
    -
    199 SUCCESS = 0U,
    -
    200 ERROR = !SUCCESS
    -
    201} ErrorStatus;
    -
    -
    202
    -
    211#define SET_BIT(REG, BIT) ((REG) |= (BIT))
    -
    212
    -
    213#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))
    -
    214
    -
    215#define READ_BIT(REG, BIT) ((REG) & (BIT))
    -
    216
    -
    217#define CLEAR_REG(REG) ((REG) = (0x0))
    -
    218
    -
    219#define WRITE_REG(REG, VAL) ((REG) = (VAL))
    -
    220
    -
    221#define READ_REG(REG) ((REG))
    -
    222
    -
    223#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
    -
    224
    -
    225#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL)))
    -
    226
    -
    227/* Use of CMSIS compiler intrinsics for register exclusive access */
    -
    228/* Atomic 32-bit register access macro to set one or several bits */
    -
    -
    229#define ATOMIC_SET_BIT(REG, BIT) \
    -
    230 do { \
    -
    231 uint32_t val; \
    -
    232 do { \
    -
    233 val = __LDREXW((__IO uint32_t *)&(REG)) | (BIT); \
    -
    234 } while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \
    -
    235 } while(0)
    -
    -
    236
    -
    237/* Atomic 32-bit register access macro to clear one or several bits */
    -
    -
    238#define ATOMIC_CLEAR_BIT(REG, BIT) \
    -
    239 do { \
    -
    240 uint32_t val; \
    -
    241 do { \
    -
    242 val = __LDREXW((__IO uint32_t *)&(REG)) & ~(BIT); \
    -
    243 } while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \
    -
    244 } while(0)
    -
    -
    245
    -
    246/* Atomic 32-bit register access macro to clear and set one or several bits */
    -
    -
    247#define ATOMIC_MODIFY_REG(REG, CLEARMSK, SETMASK) \
    -
    248 do { \
    -
    249 uint32_t val; \
    -
    250 do { \
    -
    251 val = (__LDREXW((__IO uint32_t *)&(REG)) & ~(CLEARMSK)) | (SETMASK); \
    -
    252 } while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \
    -
    253 } while(0)
    -
    -
    254
    -
    255/* Atomic 16-bit register access macro to set one or several bits */
    -
    -
    256#define ATOMIC_SETH_BIT(REG, BIT) \
    -
    257 do { \
    -
    258 uint16_t val; \
    -
    259 do { \
    -
    260 val = __LDREXH((__IO uint16_t *)&(REG)) | (BIT); \
    -
    261 } while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \
    -
    262 } while(0)
    -
    -
    263
    -
    264/* Atomic 16-bit register access macro to clear one or several bits */
    -
    -
    265#define ATOMIC_CLEARH_BIT(REG, BIT) \
    -
    266 do { \
    -
    267 uint16_t val; \
    -
    268 do { \
    -
    269 val = __LDREXH((__IO uint16_t *)&(REG)) & ~(BIT); \
    -
    270 } while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \
    -
    271 } while(0)
    -
    -
    272
    -
    273/* Atomic 16-bit register access macro to clear and set one or several bits */
    -
    -
    274#define ATOMIC_MODIFYH_REG(REG, CLEARMSK, SETMASK) \
    -
    275 do { \
    -
    276 uint16_t val; \
    -
    277 do { \
    -
    278 val = (__LDREXH((__IO uint16_t *)&(REG)) & ~(CLEARMSK)) | (SETMASK); \
    -
    279 } while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \
    -
    280 } while(0)
    -
    -
    281
    -
    286#if defined (USE_HAL_DRIVER)
    -
    287 #include "stm32f4xx_hal.h"
    -
    288#endif /* USE_HAL_DRIVER */
    -
    289
    -
    290#ifdef __cplusplus
    -
    291}
    -
    292#endif /* __cplusplus */
    -
    293
    -
    294#endif /* __STM32F4xx_H */
    -
    ITStatus
    enum FlagStatus ITStatus
    -
    ErrorStatus
    ErrorStatus
    Definition stm32f4xx.h:198
    -
    FlagStatus
    FlagStatus
    Definition stm32f4xx.h:185
    -
    FunctionalState
    FunctionalState
    Definition stm32f4xx.h:191
    -
    ERROR
    @ ERROR
    Definition stm32f4xx.h:200
    -
    SUCCESS
    @ SUCCESS
    Definition stm32f4xx.h:199
    -
    RESET
    @ RESET
    Definition stm32f4xx.h:186
    -
    SET
    @ SET
    Definition stm32f4xx.h:187
    -
    ENABLE
    @ ENABLE
    Definition stm32f4xx.h:193
    -
    DISABLE
    @ DISABLE
    Definition stm32f4xx.h:192
    -
    stm32f407xx_matlab.h
    -
    - -
    -Generated by doxygen 1.10.0 -
    - - diff --git a/DOCS/html/stm32f4xx__matlab__conf_8c.html b/DOCS/html/stm32f4xx__matlab__conf_8c.html index 8bc542e..5f181a1 100644 --- a/DOCS/html/stm32f4xx__matlab__conf_8c.html +++ b/DOCS/html/stm32f4xx__matlab__conf_8c.html @@ -14,6 +14,7 @@ + @@ -81,6 +82,9 @@ $(function() {
    stm32f4xx_matlab_conf.c File Reference
    + +

    ИÑходный код Ð´Ð»Ñ ÐºÐ¾Ð½Ñ„Ð¸Ð³ÑƒÑ€Ð°Ñ†Ð¸Ð¸ ÑимулÑтора МК. +More...

    #include "mcu_wrapper_conf.h"
    + Include dependency graph for stm32f4xx_matlab_conf.c:
    @@ -89,20 +93,20 @@ $(function() { -
    + +

    Go to the source code of this file.

    +
    + - - - - - - + + + + + + + + +

    Functions

    void Initialize_Periph_Sim (void)
     Ð˜Ð½Ð¸Ñ†Ð¸Ð°Ð»Ð¸Ð·Ð°Ñ†Ð¸Ñ периферии ÑимулÑтора МК.
     
    void deInitialize_Periph_Sim (void)
     
    void deInitialize_MCU (void)
     
    void Init_TIM_SIM (void)
     
    void deInitialize_Periph_Sim (void)
     Ð”ÐµÐ¸Ð½Ð¸Ñ†Ð¸Ð°Ð»Ð¸Ð·Ð°Ñ†Ð¸Ñ Ð¿ÐµÑ€Ð¸Ñ„ÐµÑ€Ð¸Ð¸ ÑимулÑтора МК.
     
    void deInitialize_MCU (void)
     Ð”ÐµÐ¸Ð½Ð¸Ñ†Ð¸Ð°Ð»Ð¸Ð·Ð°Ñ†Ð¸Ñ ÑимулÑтора МК.
     
    void Init_TIM_SIM (void)
     Ð˜Ð½Ð¸Ñ†Ð¸Ð°Ð»Ð¸Ð·Ð°Ñ†Ð¸Ñ таймеров ÑимулÑтора МК.
     
    @@ -133,9 +143,93 @@ Variables - +

    Variables

     
    MCU_CortexMemoryTypeDef MCU_CORTEX_MEM
     
    DBGMCU_TypeDef DEBUG_MCU
    DBGMCU_TypeDef DEBUG_MCU
     
    +

    Detailed Description

    +

    ИÑходный код Ð´Ð»Ñ ÐºÐ¾Ð½Ñ„Ð¸Ð³ÑƒÑ€Ð°Ñ†Ð¸Ð¸ ÑимулÑтора МК.

    +

    Данный файл наÑтраивает Ñтруктуры Ð´Ð»Ñ ÑимулÑции периферий, которые выбраны дефайнами в stm32f4xx_matlab_conf.h.

    + +

    Definition in file stm32f4xx_matlab_conf.c.

    +

    Function Documentation

    + +

    ◆ deInitialize_Periph_Sim()

    + +
    +
    + + + + + + + +
    void deInitialize_Periph_Sim (void )
    +
    + +

    Ð”ÐµÐ¸Ð½Ð¸Ñ†Ð¸Ð°Ð»Ð¸Ð·Ð°Ñ†Ð¸Ñ Ð¿ÐµÑ€Ð¸Ñ„ÐµÑ€Ð¸Ð¸ ÑимулÑтора МК.

    +

    Эта Ñ„ÑƒÐ½ÐºÑ†Ð¸Ñ Ð²Ñ‹Ð·Ñ‹Ð²Ð°ÐµÑ‚ функции деинициализации периферии Ð´Ð»Ñ Ð¿Ð¾Ñледующей ÑимулÑции

    + +

    Definition at line 31 of file stm32f4xx_matlab_conf.c.

    +
    + + Here is the call graph for this function:
    +
    +
    + + +
    +
    + +

    ◆ deInitialize_MCU()

    + +
    +
    + + + + + + + +
    void deInitialize_MCU (void )
    +
    + +

    Ð”ÐµÐ¸Ð½Ð¸Ñ†Ð¸Ð°Ð»Ð¸Ð·Ð°Ñ†Ð¸Ñ ÑимулÑтора МК.

    +

    Эта Ñ„ÑƒÐ½ÐºÑ†Ð¸Ñ Ð¾Ñ‡Ð¸Ñ‰Ð°ÐµÑ‚ памÑÑ‚ÑŒ ÑимулÑтора МК, чтобы в Ñледующей ÑимулÑции он запуÑкалÑÑ ÐºÐ°Ðº в первый раз.

    + +

    Definition at line 40 of file stm32f4xx_matlab_conf.c.

    + +
    +
    + +

    ◆ Init_TIM_SIM()

    + +
    +
    + + + + + + + +
    void Init_TIM_SIM (void )
    +
    + +

    Ð˜Ð½Ð¸Ñ†Ð¸Ð°Ð»Ð¸Ð·Ð°Ñ†Ð¸Ñ Ñ‚Ð°Ð¹Ð¼ÐµÑ€Ð¾Ð² ÑимулÑтора МК.

    +

    Эта Ñ„ÑƒÐ½ÐºÑ†Ð¸Ñ Ð¸Ð½Ð¸Ñ†Ð¸Ð°Ð»Ð¸Ð·Ð¸Ñ€ÑƒÐµÑ‚ Ñтруктуры Ð´Ð»Ñ ÑимулÑции таймеров. Таймеры Ð´Ð»Ñ ÑимулÑции выбираютÑÑ Ð´ÐµÑ„Ð°Ð¹Ð½Ð°Ð¼Ð¸ в stm32f4xx_matlab_conf.h.

    + +

    Definition at line 105 of file stm32f4xx_matlab_conf.c.

    + +
    +

    Variable Documentation

    ◆ DEBUG_MCU

    @@ -144,11 +238,13 @@ Variables
    - +
    DBGMCU_TypeDef DEBUG_MCUDBGMCU_TypeDef DEBUG_MCU
    +

    Definition at line 15 of file stm32f4xx_matlab_conf.c.

    +
    diff --git a/DOCS/html/stm32f4xx__matlab__conf_8c__incl.map b/DOCS/html/stm32f4xx__matlab__conf_8c__incl.map index 9bed1bb..c5dc718 100644 --- a/DOCS/html/stm32f4xx__matlab__conf_8c__incl.map +++ b/DOCS/html/stm32f4xx__matlab__conf_8c__incl.map @@ -1,18 +1,18 @@ - - + + - + - + - + - + diff --git a/DOCS/html/stm32f4xx__matlab__conf_8c__incl.md5 b/DOCS/html/stm32f4xx__matlab__conf_8c__incl.md5 index 38b4c0e..7e0669a 100644 --- a/DOCS/html/stm32f4xx__matlab__conf_8c__incl.md5 +++ b/DOCS/html/stm32f4xx__matlab__conf_8c__incl.md5 @@ -1 +1 @@ -5bdfea814003bc4b4123f3369772dd09 \ No newline at end of file +fb3bb20280aab79bd4b3097a2c2393be \ No newline at end of file diff --git a/DOCS/html/stm32f4xx__matlab__conf_8c_aff389f4df35953d82d9d30ae161a8cf9_cgraph.map b/DOCS/html/stm32f4xx__matlab__conf_8c_aff389f4df35953d82d9d30ae161a8cf9_cgraph.map new file mode 100644 index 0000000..769aa90 --- /dev/null +++ b/DOCS/html/stm32f4xx__matlab__conf_8c_aff389f4df35953d82d9d30ae161a8cf9_cgraph.map @@ -0,0 +1,5 @@ + + + + + diff --git a/DOCS/html/stm32f4xx__matlab__conf_8c_aff389f4df35953d82d9d30ae161a8cf9_cgraph.md5 b/DOCS/html/stm32f4xx__matlab__conf_8c_aff389f4df35953d82d9d30ae161a8cf9_cgraph.md5 new file mode 100644 index 0000000..b617db3 --- /dev/null +++ b/DOCS/html/stm32f4xx__matlab__conf_8c_aff389f4df35953d82d9d30ae161a8cf9_cgraph.md5 @@ -0,0 +1 @@ +27a35ea2023ea399c59ddc0ffc847116 \ No newline at end of file diff --git a/DOCS/html/group___m_a_i_n___s_i_m_u_l_a_t_o_r_gaff389f4df35953d82d9d30ae161a8cf9_cgraph.png b/DOCS/html/stm32f4xx__matlab__conf_8c_aff389f4df35953d82d9d30ae161a8cf9_cgraph.png similarity index 100% rename from DOCS/html/group___m_a_i_n___s_i_m_u_l_a_t_o_r_gaff389f4df35953d82d9d30ae161a8cf9_cgraph.png rename to DOCS/html/stm32f4xx__matlab__conf_8c_aff389f4df35953d82d9d30ae161a8cf9_cgraph.png diff --git a/DOCS/html/stm32f4xx__matlab__conf_8c_source.html b/DOCS/html/stm32f4xx__matlab__conf_8c_source.html new file mode 100644 index 0000000..9f16bfb --- /dev/null +++ b/DOCS/html/stm32f4xx__matlab__conf_8c_source.html @@ -0,0 +1,484 @@ + + + + + + + +STM MATLAB Simulator: F:/Work/Projects/MATLAB/matlab_stm_emulate/MCU_STM32F4xx_Matlab/stm32f4xx_matlab_conf.c Source File + + + + + + + + + + + + +
    +
    + + + + + + +
    +
    STM MATLAB Simulator +
    +
    +
    + + + + + + + + + +
    +
    + + +
    +
    +
    +
    +
    +
    Loading...
    +
    Searching...
    +
    No Matches
    +
    +
    +
    +
    + + +
    +
    +
    stm32f4xx_matlab_conf.c
    +
    +
    +Go to the documentation of this file.
    1/**
    +
    2**************************************************************************
    +
    3* @file stm32f4xx_matlab_conf.c
    +
    4* @brief ИÑходный код Ð´Ð»Ñ ÐºÐ¾Ð½Ñ„Ð¸Ð³ÑƒÑ€Ð°Ñ†Ð¸Ð¸ ÑимулÑтора МК.
    +
    5**************************************************************************
    +
    6@details
    +
    7Данный файл наÑтраивает Ñтруктуры Ð´Ð»Ñ ÑимулÑции периферий, которые выбраны
    +
    8дефайнами в stm32f4xx_matlab_conf.h.
    +
    9**************************************************************************/
    +
    10
    +
    11#include "mcu_wrapper_conf.h"
    +
    12
    +
    13MCU_MemoryTypeDef MCU_MEM;
    +
    14MCU_CortexMemoryTypeDef MCU_CORTEX_MEM;
    +
    15DBGMCU_TypeDef DEBUG_MCU;
    +
    16
    +
    17//-----------------------------------------------------------------------//
    +
    18/*------------------------------FUNCTIONS--------------------------------*/
    +
    19/**
    +
    20 * @brief Ð˜Ð½Ð¸Ñ†Ð¸Ð°Ð»Ð¸Ð·Ð°Ñ†Ð¸Ñ Ð¿ÐµÑ€Ð¸Ñ„ÐµÑ€Ð¸Ð¸ ÑимулÑтора МК.
    +
    21 * @details Эта Ñ„ÑƒÐ½ÐºÑ†Ð¸Ñ Ð²Ñ‹Ð·Ñ‹Ð²Ð°ÐµÑ‚ функции инициализации периферии Ð´Ð»Ñ ÑимулÑции
    +
    22 */
    +
    +
    23void Initialize_Periph_Sim(void)
    +
    24{
    +
    25 Init_TIM_SIM();
    +
    26}
    +
    +
    27/**
    +
    28 * @brief Ð”ÐµÐ¸Ð½Ð¸Ñ†Ð¸Ð°Ð»Ð¸Ð·Ð°Ñ†Ð¸Ñ Ð¿ÐµÑ€Ð¸Ñ„ÐµÑ€Ð¸Ð¸ ÑимулÑтора МК.
    +
    29 * @details Эта Ñ„ÑƒÐ½ÐºÑ†Ð¸Ñ Ð²Ñ‹Ð·Ñ‹Ð²Ð°ÐµÑ‚ функции деинициализации периферии Ð´Ð»Ñ Ð¿Ð¾Ñледующей ÑимулÑции
    +
    30 */
    +
    +
    31void deInitialize_Periph_Sim(void)
    +
    32{
    +
    33 TIM_SIM_DEINIT();
    +
    34}
    +
    +
    35/**
    +
    36 * @brief Ð”ÐµÐ¸Ð½Ð¸Ñ†Ð¸Ð°Ð»Ð¸Ð·Ð°Ñ†Ð¸Ñ ÑимулÑтора МК.
    +
    37 * @details Эта Ñ„ÑƒÐ½ÐºÑ†Ð¸Ñ Ð¾Ñ‡Ð¸Ñ‰Ð°ÐµÑ‚ памÑÑ‚ÑŒ ÑимулÑтора МК, чтобы в
    +
    38 Ñледующей ÑимулÑции он запуÑкалÑÑ ÐºÐ°Ðº в первый раз.
    +
    39 */
    +
    +
    40void deInitialize_MCU(void)
    +
    41{
    +
    42 // обнуление Ñтруктуры, управлÑющей программой МК
    +
    43 memset(&hmcu, 0, sizeof(hmcu));
    +
    44 // обнуление Ñтруктур, Ñимулирующих памÑÑ‚ÑŒ МК
    +
    45 memset(&MCU_MEM, 0, sizeof(MCU_MEM));
    +
    46 memset(&MCU_CORTEX_MEM, 0, sizeof(MCU_CORTEX_MEM));
    +
    47 memset(&DEBUG_MCU, 0, sizeof(DEBUG_MCU));
    +
    48}
    +
    +
    49
    +
    50
    +
    51/*------------------------------FUNCTIONS--------------------------------*/
    +
    52//-----------------------------------------------------------------------//
    +
    53
    +
    54//-----------------------------------------------------------------------//
    +
    55/*-------------------------------TIMERS----------------------------------*/
    +
    56// defines structure for simulate
    +
    57#ifdef USE_TIM1
    +
    58struct TIM_Sim tim1s;
    +
    59#endif
    +
    60#ifdef USE_TIM2
    +
    61struct TIM_Sim tim2s;
    +
    62#endif
    +
    63#ifdef USE_TIM3
    +
    64struct TIM_Sim tim3s;
    +
    65#endif
    +
    66#ifdef USE_TIM4
    +
    67struct TIM_Sim tim4s;
    +
    68#endif
    +
    69#ifdef USE_TIM5
    +
    70struct TIM_Sim tim5s;
    +
    71#endif
    +
    72#ifdef USE_TIM6
    +
    73struct TIM_Sim tim6s;
    +
    74#endif
    +
    75#ifdef USE_TIM7
    +
    76struct TIM_Sim tim7s;
    +
    77#endif
    +
    78#ifdef USE_TIM8
    +
    79struct TIM_Sim tim8s;
    +
    80#endif
    +
    81#ifdef USE_TIM9
    +
    82struct TIM_Sim tim9s;
    +
    83#endif
    +
    84#ifdef USE_TIM10
    +
    85struct TIM_Sim tim10s;
    +
    86#endif
    +
    87#ifdef USE_TIM11
    +
    88struct TIM_Sim tim11s;
    +
    89#endif
    +
    90#ifdef USE_TIM12
    +
    91struct TIM_Sim tim12s;
    +
    92#endif
    +
    93#ifdef USE_TIM13
    +
    94struct TIM_Sim tim13s;
    +
    95#endif
    +
    96#ifdef USE_TIM14
    +
    97struct TIM_Sim tim14s;
    +
    98#endif
    +
    99
    +
    100/**
    +
    101 * @brief Ð˜Ð½Ð¸Ñ†Ð¸Ð°Ð»Ð¸Ð·Ð°Ñ†Ð¸Ñ Ñ‚Ð°Ð¹Ð¼ÐµÑ€Ð¾Ð² ÑимулÑтора МК.
    +
    102 * @details Эта Ñ„ÑƒÐ½ÐºÑ†Ð¸Ñ Ð¸Ð½Ð¸Ñ†Ð¸Ð°Ð»Ð¸Ð·Ð¸Ñ€ÑƒÐµÑ‚ Ñтруктуры Ð´Ð»Ñ ÑимулÑции таймеров.
    +
    103 * Таймеры Ð´Ð»Ñ ÑимулÑции выбираютÑÑ Ð´ÐµÑ„Ð°Ð¹Ð½Ð°Ð¼Ð¸ в stm32f4xx_matlab_conf.h.
    +
    104 */
    +
    +
    105void Init_TIM_SIM(void)
    +
    106{
    +
    107#ifdef USE_TIM1
    +
    108 tim1s.tx_cnt = TIM1->CNT;
    +
    109 tim1s.tx_step = hmcu.SIM_Sample_Time * ABP2_TIMS_Value;
    +
    110
    +
    111 tim1s.Channels.OC1_GPIOx = GPIOE;
    +
    112 tim1s.Channels.OC1_PIN_SHIFT = 9;
    +
    113 tim1s.Channels.OC2_GPIOx = GPIOE;
    +
    114 tim1s.Channels.OC2_PIN_SHIFT = 11;
    +
    115 tim1s.Channels.OC3_GPIOx = GPIOE;
    +
    116 tim1s.Channels.OC3_PIN_SHIFT = 13;
    +
    117 tim1s.Channels.OC4_GPIOx = GPIOE;
    +
    118 tim1s.Channels.OC4_PIN_SHIFT = 14;
    +
    119 tim1s.Channels.OC1REF = 0;
    +
    120 tim1s.Channels.OC2REF = 0;
    +
    121 tim1s.Channels.OC3REF = 0;
    +
    122 tim1s.Channels.OC4REF = 0;
    +
    123#endif
    +
    124#ifdef USE_TIM2
    +
    125 tim2s.tx_cnt = TIM2->CNT;
    +
    126 tim2s.tx_step = hmcu.SIM_Sample_Time * ABP1_TIMS_Value;
    +
    127
    +
    128 tim2s.Channels.OC1_GPIOx = GPIOA;
    +
    129 tim2s.Channels.OC1_PIN_SHIFT = 5;
    +
    130 tim2s.Channels.OC2_GPIOx = GPIOA;
    +
    131 tim2s.Channels.OC2_PIN_SHIFT = 1;
    +
    132 tim2s.Channels.OC3_GPIOx = GPIOA;
    +
    133 tim2s.Channels.OC3_PIN_SHIFT = 2;
    +
    134 tim2s.Channels.OC4_GPIOx = GPIOA;
    +
    135 tim2s.Channels.OC4_PIN_SHIFT = 3;
    +
    136 tim2s.Channels.OC1REF = 0;
    +
    137 tim2s.Channels.OC2REF = 0;
    +
    138 tim2s.Channels.OC3REF = 0;
    +
    139 tim2s.Channels.OC4REF = 0;
    +
    140#endif
    +
    141#ifdef USE_TIM3
    +
    142 tim3s.tx_cnt = TIM3->CNT;
    +
    143 tim3s.tx_step = hmcu.SIM_Sample_Time * ABP1_TIMS_Value;
    +
    144
    +
    145 tim3s.Channels.OC1_GPIOx = GPIOA;
    +
    146 tim3s.Channels.OC1_PIN_SHIFT = 6;
    +
    147 tim3s.Channels.OC2_GPIOx = GPIOA;
    +
    148 tim3s.Channels.OC2_PIN_SHIFT = 7;
    +
    149 tim3s.Channels.OC3_GPIOx = GPIOB;
    +
    150 tim3s.Channels.OC3_PIN_SHIFT = 0;
    +
    151 tim3s.Channels.OC4_GPIOx = GPIOB;
    +
    152 tim3s.Channels.OC4_PIN_SHIFT = 1;
    +
    153 tim3s.Channels.OC1REF = 0;
    +
    154 tim3s.Channels.OC2REF = 0;
    +
    155 tim3s.Channels.OC3REF = 0;
    +
    156 tim3s.Channels.OC4REF = 0;
    +
    157#endif
    +
    158#ifdef USE_TIM4
    +
    159 tim4s.tx_cnt = TIM4->CNT;
    +
    160 tim4s.tx_step = hmcu.SIM_Sample_Time * ABP1_TIMS_Value;
    +
    161
    +
    162 tim4s.Channels.OC1_GPIOx = GPIOD;
    +
    163 tim4s.Channels.OC1_PIN_SHIFT = 12;
    +
    164 tim4s.Channels.OC2_GPIOx = GPIOD;
    +
    165 tim4s.Channels.OC2_PIN_SHIFT = 13;
    +
    166 tim4s.Channels.OC3_GPIOx = GPIOD;
    +
    167 tim4s.Channels.OC3_PIN_SHIFT = 14;
    +
    168 tim4s.Channels.OC4_GPIOx = GPIOD;
    +
    169 tim4s.Channels.OC4_PIN_SHIFT = 15;
    +
    170 tim4s.Channels.OC1REF = 0;
    +
    171 tim4s.Channels.OC2REF = 0;
    +
    172 tim4s.Channels.OC3REF = 0;
    +
    173 tim4s.Channels.OC4REF = 0;
    +
    174#endif
    +
    175#ifdef USE_TIM5
    +
    176 tim5s.tx_cnt = TIM5->CNT;
    +
    177 tim5s.tx_step = hmcu.SIM_Sample_Time * ABP1_TIMS_Value;
    +
    178
    +
    179 tim5s.Channels.OC1_GPIOx = GPIOA;
    +
    180 tim5s.Channels.OC1_PIN_SHIFT = 0;
    +
    181 tim5s.Channels.OC2_GPIOx = GPIOA;
    +
    182 tim5s.Channels.OC2_PIN_SHIFT = 1;
    +
    183 tim5s.Channels.OC3_GPIOx = GPIOA;
    +
    184 tim5s.Channels.OC3_PIN_SHIFT = 2;
    +
    185 tim5s.Channels.OC4_GPIOx = GPIOA;
    +
    186 tim5s.Channels.OC4_PIN_SHIFT = 3;
    +
    187 tim5s.Channels.OC1REF = 0;
    +
    188 tim5s.Channels.OC2REF = 0;
    +
    189 tim5s.Channels.OC3REF = 0;
    +
    190 tim5s.Channels.OC4REF = 0;
    +
    191#endif
    +
    192#ifdef USE_TIM6
    +
    193 tim6s.tx_cnt = TIM6->CNT;
    +
    194 tim6s.tx_step = hmcu.SIM_Sample_Time * ABP1_TIMS_Value;
    +
    195
    +
    196 tim6s.Channels.OC1_GPIOx = GPIOA;
    +
    197 tim6s.Channels.OC1_PIN_SHIFT = 6;
    +
    198 tim6s.Channels.OC2_GPIOx = GPIOA;
    +
    199 tim6s.Channels.OC2_PIN_SHIFT = 0;
    +
    200 tim6s.Channels.OC3_GPIOx = GPIOA;
    +
    201 tim6s.Channels.OC3_PIN_SHIFT = 0;
    +
    202 tim6s.Channels.OC4_GPIOx = GPIOA;
    +
    203 tim6s.Channels.OC4_PIN_SHIFT = 0;
    +
    204 tim6s.Channels.OC1REF = 0;
    +
    205 tim6s.Channels.OC2REF = 0;
    +
    206 tim6s.Channels.OC3REF = 0;
    +
    207 tim6s.Channels.OC4REF = 0;
    +
    208#endif
    +
    209#ifdef USE_TIM7
    +
    210 tim7s.tx_cnt = TIM7->CNT;
    +
    211 tim7s.tx_step = hmcu.SIM_Sample_Time * ABP1_TIMS_Value;
    +
    212
    +
    213 tim7s.Channels.OC1_GPIOx = GPIOA;
    +
    214 tim7s.Channels.OC1_PIN_SHIFT = 6;
    +
    215 tim7s.Channels.OC2_GPIOx = GPIOA;
    +
    216 tim7s.Channels.OC2_PIN_SHIFT = 0;
    +
    217 tim7s.Channels.OC3_GPIOx = GPIOA;
    +
    218 tim7s.Channels.OC3_PIN_SHIFT = 0;
    +
    219 tim7s.Channels.OC4_GPIOx = GPIOA;
    +
    220 tim7s.Channels.OC4_PIN_SHIFT = 0;
    +
    221 tim7s.Channels.OC1REF = 0;
    +
    222 tim7s.Channels.OC2REF = 0;
    +
    223 tim7s.Channels.OC3REF = 0;
    +
    224 tim7s.Channels.OC4REF = 0;
    +
    225#endif
    +
    226#ifdef USE_TIM8
    +
    227 tim8s.tx_cnt = TIM8->CNT;
    +
    228 tim8s.tx_step = hmcu.SIM_Sample_Time * ABP2_TIMS_Value;
    +
    229
    +
    230 tim8s.Channels.OC1_GPIOx = GPIOA;
    +
    231 tim8s.Channels.OC1_PIN_SHIFT = 6;
    +
    232 tim8s.Channels.OC2_GPIOx = GPIOA;
    +
    233 tim8s.Channels.OC2_PIN_SHIFT = 0;
    +
    234 tim8s.Channels.OC3_GPIOx = GPIOA;
    +
    235 tim8s.Channels.OC3_PIN_SHIFT = 0;
    +
    236 tim8s.Channels.OC4_GPIOx = GPIOA;
    +
    237 tim8s.Channels.OC4_PIN_SHIFT = 0;
    +
    238 tim8s.Channels.OC1REF = 0;
    +
    239 tim8s.Channels.OC2REF = 0;
    +
    240 tim8s.Channels.OC3REF = 0;
    +
    241 tim8s.Channels.OC4REF = 0;
    +
    242#endif
    +
    243#ifdef USE_TIM9
    +
    244 tim9s.tx_cnt = TIM9->CNT;
    +
    245 tim9s.tx_step = hmcu.SIM_Sample_Time * ABP2_TIMS_Value;
    +
    246
    +
    247 tim9s.Channels.OC1_GPIOx = GPIOA;
    +
    248 tim9s.Channels.OC1_PIN_SHIFT = 6;
    +
    249 tim9s.Channels.OC2_GPIOx = GPIOA;
    +
    250 tim9s.Channels.OC2_PIN_SHIFT = 0;
    +
    251 tim9s.Channels.OC3_GPIOx = GPIOA;
    +
    252 tim9s.Channels.OC3_PIN_SHIFT = 0;
    +
    253 tim9s.Channels.OC4_GPIOx = GPIOA;
    +
    254 tim9s.Channels.OC4_PIN_SHIFT = 0;
    +
    255 tim9s.Channels.OC1REF = 0;
    +
    256 tim9s.Channels.OC2REF = 0;
    +
    257 tim9s.Channels.OC3REF = 0;
    +
    258 tim9s.Channels.OC4REF = 0;
    +
    259#endif
    +
    260#ifdef USE_TIM10
    +
    261 tim10s.tx_cnt = TIM10->CNT;
    +
    262 tim10s.tx_step = hmcu.SIM_Sample_Time * ABP2_TIMS_Value;
    +
    263
    +
    264 tim10s.Channels.OC1_GPIOx = GPIOA;
    +
    265 tim10s.Channels.OC1_PIN_SHIFT = 6;
    +
    266 tim10s.Channels.OC2_GPIOx = GPIOA;
    +
    267 tim10s.Channels.OC2_PIN_SHIFT = 0;
    +
    268 tim10s.Channels.OC3_GPIOx = GPIOA;
    +
    269 tim10s.Channels.OC3_PIN_SHIFT = 0;
    +
    270 tim10s.Channels.OC4_GPIOx = GPIOA;
    +
    271 tim10s.Channels.OC4_PIN_SHIFT = 0;
    +
    272 tim10s.Channels.OC1REF = 0;
    +
    273 tim10s.Channels.OC2REF = 0;
    +
    274 tim10s.Channels.OC3REF = 0;
    +
    275 tim10s.Channels.OC4REF = 0;
    +
    276#endif
    +
    277#ifdef USE_TIM11
    +
    278 tim11s.tx_cnt = TIM11->CNT;
    +
    279 tim11s.tx_step = hmcu.SIM_Sample_Time * ABP2_TIMS_Value;
    +
    280
    +
    281 tim11s.Channels.OC1_GPIOx = GPIOA;
    +
    282 tim11s.Channels.OC1_PIN_SHIFT = 6;
    +
    283 tim11s.Channels.OC2_GPIOx = GPIOA;
    +
    284 tim11s.Channels.OC2_PIN_SHIFT = 0;
    +
    285 tim11s.Channels.OC3_GPIOx = GPIOA;
    +
    286 tim11s.Channels.OC3_PIN_SHIFT = 0;
    +
    287 tim11s.Channels.OC4_GPIOx = GPIOA;
    +
    288 tim11s.Channels.OC4_PIN_SHIFT = 0;
    +
    289 tim11s.Channels.OC1REF = 0;
    +
    290 tim11s.Channels.OC2REF = 0;
    +
    291 tim11s.Channels.OC3REF = 0;
    +
    292 tim11s.Channels.OC4REF = 0;
    +
    293#endif
    +
    294#ifdef USE_TIM12
    +
    295 tim12s.tx_cnt = TIM12->CNT;
    +
    296 tim12s.tx_step = hmcu.SIM_Sample_Time * ABP1_TIMS_Value;
    +
    297
    +
    298 tim12s.Channels.OC1_GPIOx = GPIOA;
    +
    299 tim12s.Channels.OC1_PIN_SHIFT = 6;
    +
    300 tim12s.Channels.OC2_GPIOx = GPIOA;
    +
    301 tim12s.Channels.OC2_PIN_SHIFT = 0;
    +
    302 tim12s.Channels.OC3_GPIOx = GPIOA;
    +
    303 tim12s.Channels.OC3_PIN_SHIFT = 0;
    +
    304 tim12s.Channels.OC4_GPIOx = GPIOA;
    +
    305 tim12s.Channels.OC4_PIN_SHIFT = 0;
    +
    306 tim12s.Channels.OC1REF = 0;
    +
    307 tim12s.Channels.OC2REF = 0;
    +
    308 tim12s.Channels.OC3REF = 0;
    +
    309 tim12s.Channels.OC4REF = 0;
    +
    310#endif
    +
    311#ifdef USE_TIM13
    +
    312 tim13s.tx_cnt = TIM13->CNT;
    +
    313 tim13s.tx_step = hmcu.SIM_Sample_Time * ABP1_TIMS_Value;
    +
    314
    +
    315 tim13s.Channels.OC1_GPIOx = GPIOA;
    +
    316 tim13s.Channels.OC1_PIN_SHIFT = 6;
    +
    317 tim13s.Channels.OC2_GPIOx = GPIOA;
    +
    318 tim13s.Channels.OC2_PIN_SHIFT = 0;
    +
    319 tim13s.Channels.OC3_GPIOx = GPIOA;
    +
    320 tim13s.Channels.OC3_PIN_SHIFT = 0;
    +
    321 tim13s.Channels.OC4_GPIOx = GPIOA;
    +
    322 tim13s.Channels.OC4_PIN_SHIFT = 0;
    +
    323 tim13s.Channels.OC1REF = 0;
    +
    324 tim13s.Channels.OC2REF = 0;
    +
    325 tim13s.Channels.OC3REF = 0;
    +
    326 tim13s.Channels.OC4REF = 0;
    +
    327#endif
    +
    328#ifdef USE_TIM14
    +
    329 tim14s.tx_cnt = TIM14->CNT;
    +
    330 tim14s.tx_step = hmcu.SIM_Sample_Time * ABP1_TIMS_Value;
    +
    331
    +
    332 tim14s.Channels.OC1_GPIOx = GPIOA;
    +
    333 tim14s.Channels.OC1_PIN_SHIFT = 6;
    +
    334 tim14s.Channels.OC2_GPIOx = GPIOA;
    +
    335 tim14s.Channels.OC2_PIN_SHIFT = 0;
    +
    336 tim14s.Channels.OC3_GPIOx = GPIOA;
    +
    337 tim14s.Channels.OC3_PIN_SHIFT = 0;
    +
    338 tim14s.Channels.OC4_GPIOx = GPIOA;
    +
    339 tim14s.Channels.OC4_PIN_SHIFT = 0;
    +
    340 tim14s.Channels.OC1REF = 0;
    +
    341 tim14s.Channels.OC2REF = 0;
    +
    342 tim14s.Channels.OC3REF = 0;
    +
    343 tim14s.Channels.OC4REF = 0;
    +
    344#endif
    +
    345}
    +
    +
    346/*-------------------------------TIMERS----------------------------------*/
    +
    347//-----------------------------------------------------------------------//
    +
    MCU_CORTEX_MEM
    MCU_CortexMemoryTypeDef MCU_CORTEX_MEM
    Definition stm32f4xx_matlab_conf.c:14
    +
    Initialize_Periph_Sim
    void Initialize_Periph_Sim(void)
    Ð˜Ð½Ð¸Ñ†Ð¸Ð°Ð»Ð¸Ð·Ð°Ñ†Ð¸Ñ Ð¿ÐµÑ€Ð¸Ñ„ÐµÑ€Ð¸Ð¸ ÑимулÑтора МК.
    Definition stm32f4xx_matlab_conf.c:23
    +
    MCU_MEM
    MCU_MemoryTypeDef MCU_MEM
    Definition stm32f4xx_matlab_conf.c:13
    +
    ABP1_TIMS_Value
    #define ABP1_TIMS_Value
    Definition stm32f4xx_matlab_rcc.h:30
    +
    ABP2_TIMS_Value
    #define ABP2_TIMS_Value
    Definition stm32f4xx_matlab_rcc.h:32
    +
    TIM_SIM_DEINIT
    void TIM_SIM_DEINIT(void)
    Деинициализирование выбранных таймеров.
    Definition stm32f4xx_matlab_tim.c:571
    +
    hmcu
    SIM__MCUHandleTypeDef hmcu
    Хендл Ð´Ð»Ñ ÑƒÐ¿Ñ€Ð°Ð²Ð»ÐµÐ½Ð¸Ñ Ð¿Ð¾Ñ‚Ð¾ÐºÐ¾Ð¼ программы МК
    Definition mcu_wrapper.c:16
    +
    mcu_wrapper_conf.h
    Заголовочный файл Ð´Ð»Ñ Ð¾Ð±Ð¾Ð»Ð¾Ñ‡ÐºÐ¸ МК.
    +
    Init_TIM_SIM
    void Init_TIM_SIM(void)
    Ð˜Ð½Ð¸Ñ†Ð¸Ð°Ð»Ð¸Ð·Ð°Ñ†Ð¸Ñ Ñ‚Ð°Ð¹Ð¼ÐµÑ€Ð¾Ð² ÑимулÑтора МК.
    Definition stm32f4xx_matlab_conf.c:105
    +
    DEBUG_MCU
    DBGMCU_TypeDef DEBUG_MCU
    Definition stm32f4xx_matlab_conf.c:15
    +
    deInitialize_MCU
    void deInitialize_MCU(void)
    Ð”ÐµÐ¸Ð½Ð¸Ñ†Ð¸Ð°Ð»Ð¸Ð·Ð°Ñ†Ð¸Ñ ÑимулÑтора МК.
    Definition stm32f4xx_matlab_conf.c:40
    +
    deInitialize_Periph_Sim
    void deInitialize_Periph_Sim(void)
    Ð”ÐµÐ¸Ð½Ð¸Ñ†Ð¸Ð°Ð»Ð¸Ð·Ð°Ñ†Ð¸Ñ Ð¿ÐµÑ€Ð¸Ñ„ÐµÑ€Ð¸Ð¸ ÑимулÑтора МК.
    Definition stm32f4xx_matlab_conf.c:31
    +
    tim1s
    struct TIM_Sim tim1s
    +
    tim4s
    struct TIM_Sim tim4s
    +
    tim12s
    struct TIM_Sim tim12s
    +
    tim3s
    struct TIM_Sim tim3s
    +
    tim7s
    struct TIM_Sim tim7s
    +
    _cortex_memory
    Definition stm32f407xx_matlab_memory.h:27
    +
    _memory
    Definition stm32f407xx_matlab_memory.h:107
    +
    Channels_Sim::OC2_GPIOx
    GPIO_TypeDef * OC2_GPIOx
    Порт второго канала
    Definition stm32f4xx_matlab_tim.h:88
    +
    Channels_Sim::OC4REF
    unsigned OC4REF
    Четвертый канал
    Definition stm32f4xx_matlab_tim.h:82
    +
    Channels_Sim::OC1_PIN_SHIFT
    uint32_t OC1_PIN_SHIFT
    Пин первого канала
    Definition stm32f4xx_matlab_tim.h:86
    +
    Channels_Sim::OC1_GPIOx
    GPIO_TypeDef * OC1_GPIOx
    Порт первого канала
    Definition stm32f4xx_matlab_tim.h:85
    +
    Channels_Sim::OC3_GPIOx
    GPIO_TypeDef * OC3_GPIOx
    Порт третьего канала
    Definition stm32f4xx_matlab_tim.h:91
    +
    Channels_Sim::OC4_GPIOx
    GPIO_TypeDef * OC4_GPIOx
    Порт четвертого канала
    Definition stm32f4xx_matlab_tim.h:94
    +
    Channels_Sim::OC2REF
    unsigned OC2REF
    Второй канал
    Definition stm32f4xx_matlab_tim.h:80
    +
    Channels_Sim::OC4_PIN_SHIFT
    uint32_t OC4_PIN_SHIFT
    Пин четвертого канала
    Definition stm32f4xx_matlab_tim.h:95
    +
    Channels_Sim::OC1REF
    unsigned OC1REF
    Первый канал
    Definition stm32f4xx_matlab_tim.h:79
    +
    Channels_Sim::OC3REF
    unsigned OC3REF
    Третьий канал
    Definition stm32f4xx_matlab_tim.h:81
    +
    Channels_Sim::OC3_PIN_SHIFT
    uint32_t OC3_PIN_SHIFT
    Пин третьего канала
    Definition stm32f4xx_matlab_tim.h:92
    +
    Channels_Sim::OC2_PIN_SHIFT
    uint32_t OC2_PIN_SHIFT
    Пин второго канала
    Definition stm32f4xx_matlab_tim.h:89
    +
    SIM__MCUHandleTypeDef::SIM_Sample_Time
    double SIM_Sample_Time
    sample time of simulation
    Definition mcu_wrapper_conf.h:83
    +
    TIM_Sim
    Структура Ð´Ð»Ñ Ð¼Ð¾Ð´ÐµÐ»Ð¸Ñ€Ð¾Ð²Ð°Ð½Ð¸Ñ Ñ‚Ð°Ð¹Ð¼ÐµÑ€Ð°
    Definition stm32f4xx_matlab_tim.h:103
    +
    TIM_Sim::tx_cnt
    double tx_cnt
    Счетчик таймера (double, Ñ‚.к. кол-во тактов за шаг ÑимулÑции может быть дробным)
    Definition stm32f4xx_matlab_tim.h:104
    +
    TIM_Sim::Channels
    struct Channels_Sim Channels
    Структура Ð´Ð»Ñ ÑимулÑции каналов
    Definition stm32f4xx_matlab_tim.h:107
    +
    TIM_Sim::tx_step
    double tx_step
    Шаг Ñчета за один шаг ÑимулÑции (double, Ñ‚.к. кол-во тактов за шаг ÑимулÑции может быть дробным)
    Definition stm32f4xx_matlab_tim.h:105
    +
    + +
    +Generated by doxygen 1.10.0 +
    + + diff --git a/DOCS/html/stm32f4xx__matlab__conf_8h.html b/DOCS/html/stm32f4xx__matlab__conf_8h.html index cdeb63b..33bcf7c 100644 --- a/DOCS/html/stm32f4xx__matlab__conf_8h.html +++ b/DOCS/html/stm32f4xx__matlab__conf_8h.html @@ -14,6 +14,7 @@ + @@ -76,12 +77,13 @@ $(function() {
    -Macros | -Functions | -Variables
    +Macros
    stm32f4xx_matlab_conf.h File Reference
    + +

    Заголовочный файл Ð´Ð»Ñ ÐºÐ¾Ð½Ñ„Ð¸Ð³ÑƒÑ€Ð°Ñ†Ð¸Ð¸ ÑимулÑтора МК. +More...

    #include "stm32f4xx_matlab_rcc.h"
    #include "stm32f4xx_matlab_gpio.h"
    #include "stm32f4xx_matlab_tim.h"
    @@ -92,14 +94,14 @@ $(function() { @@ -168,31 +170,224 @@ Macros   #define USE_TIM8_BRK_TIM12_HANDLER   - - + + + + + + + + + + + - - - - - - -

    -Functions

    struct TIM_Sim tim1s
     
    struct TIM_Sim tim3s
     
    struct TIM_Sim tim4s
     
    struct TIM_Sim tim7s
     
    struct TIM_Sim tim12s
     
    void Initialize_Periph_Sim (void)
     Ð˜Ð½Ð¸Ñ†Ð¸Ð°Ð»Ð¸Ð·Ð°Ñ†Ð¸Ñ периферии ÑимулÑтора МК.
     
    void deInitialize_Periph_Sim (void)
     
    void deInitialize_MCU (void)
     
    void Init_TIM_SIM (void)
     
    - - - - - - - - - - - + + + + + + + + +

    -Variables

    struct TIM_Sim tim1s
     
    struct TIM_Sim tim3s
     
    struct TIM_Sim tim4s
     
    struct TIM_Sim tim7s
     
    struct TIM_Sim tim12s
     
    void deInitialize_Periph_Sim (void)
     Ð”ÐµÐ¸Ð½Ð¸Ñ†Ð¸Ð°Ð»Ð¸Ð·Ð°Ñ†Ð¸Ñ Ð¿ÐµÑ€Ð¸Ñ„ÐµÑ€Ð¸Ð¸ ÑимулÑтора МК.
     
    void deInitialize_MCU (void)
     Ð”ÐµÐ¸Ð½Ð¸Ñ†Ð¸Ð°Ð»Ð¸Ð·Ð°Ñ†Ð¸Ñ ÑимулÑтора МК.
     
    void Init_TIM_SIM (void)
     Ð˜Ð½Ð¸Ñ†Ð¸Ð°Ð»Ð¸Ð·Ð°Ñ†Ð¸Ñ таймеров ÑимулÑтора МК.
     
    +

    Detailed Description

    +

    Заголовочный файл Ð´Ð»Ñ ÐºÐ¾Ð½Ñ„Ð¸Ð³ÑƒÑ€Ð°Ñ†Ð¸Ð¸ ÑимулÑтора МК.

    +

    ЗдеÑÑŒ задаётÑÑ Ð¸ÑÐ¿Ð¾Ð»ÑŒÐ·ÑƒÐµÐ¼Ð°Ñ Ð¿ÐµÑ€Ð¸Ñ„ÐµÑ€Ð¸Ñ Ð¸ подключаютÑÑ Ð±Ð¸Ð±Ð»Ð¸Ð¾Ñ‚ÐµÐºÐ¸ Ð´Ð»Ñ Ð¿ÐµÑ€Ð¸Ñ„ÐµÑ€Ð¸Ð¸.

    + +

    Definition in file stm32f4xx_matlab_conf.h.

    +

    Function Documentation

    + +

    ◆ deInitialize_Periph_Sim()

    + +
    +
    + + + + + + + +
    void deInitialize_Periph_Sim (void )
    +
    + +

    Ð”ÐµÐ¸Ð½Ð¸Ñ†Ð¸Ð°Ð»Ð¸Ð·Ð°Ñ†Ð¸Ñ Ð¿ÐµÑ€Ð¸Ñ„ÐµÑ€Ð¸Ð¸ ÑимулÑтора МК.

    +

    Эта Ñ„ÑƒÐ½ÐºÑ†Ð¸Ñ Ð²Ñ‹Ð·Ñ‹Ð²Ð°ÐµÑ‚ функции деинициализации периферии Ð´Ð»Ñ Ð¿Ð¾Ñледующей ÑимулÑции

    + +

    Definition at line 31 of file stm32f4xx_matlab_conf.c.

    +
    + + Here is the call graph for this function:
    +
    +
    + + +
    +
    + +

    ◆ deInitialize_MCU()

    + +
    +
    + + + + + + + +
    void deInitialize_MCU (void )
    +
    + +

    Ð”ÐµÐ¸Ð½Ð¸Ñ†Ð¸Ð°Ð»Ð¸Ð·Ð°Ñ†Ð¸Ñ ÑимулÑтора МК.

    +

    Эта Ñ„ÑƒÐ½ÐºÑ†Ð¸Ñ Ð¾Ñ‡Ð¸Ñ‰Ð°ÐµÑ‚ памÑÑ‚ÑŒ ÑимулÑтора МК, чтобы в Ñледующей ÑимулÑции он запуÑкалÑÑ ÐºÐ°Ðº в первый раз.

    + +

    Definition at line 40 of file stm32f4xx_matlab_conf.c.

    + +
    +
    + +

    ◆ Init_TIM_SIM()

    + +
    +
    + + + + + + + +
    void Init_TIM_SIM (void )
    +
    + +

    Ð˜Ð½Ð¸Ñ†Ð¸Ð°Ð»Ð¸Ð·Ð°Ñ†Ð¸Ñ Ñ‚Ð°Ð¹Ð¼ÐµÑ€Ð¾Ð² ÑимулÑтора МК.

    +

    Эта Ñ„ÑƒÐ½ÐºÑ†Ð¸Ñ Ð¸Ð½Ð¸Ñ†Ð¸Ð°Ð»Ð¸Ð·Ð¸Ñ€ÑƒÐµÑ‚ Ñтруктуры Ð´Ð»Ñ ÑимулÑции таймеров. Таймеры Ð´Ð»Ñ ÑимулÑции выбираютÑÑ Ð´ÐµÑ„Ð°Ð¹Ð½Ð°Ð¼Ð¸ в stm32f4xx_matlab_conf.h.

    + +

    Definition at line 105 of file stm32f4xx_matlab_conf.c.

    + +
    +
    +

    Variable Documentation

    + +

    ◆ tim1s

    + +
    +
    + + + + + +
    + + + + +
    struct TIM_Sim tim1s
    +     		+extern
    +
    + +
    +
    + +

    ◆ tim3s

    + +
    +
    + + + + + +
    + + + + +
    struct TIM_Sim tim3s
    +     		+extern
    +
    + +
    +
    + +

    ◆ tim4s

    + +
    +
    + + + + + +
    + + + + +
    struct TIM_Sim tim4s
    +     		+extern
    +
    + +
    +
    + +

    ◆ tim7s

    + +
    +
    + + + + + +
    + + + + +
    struct TIM_Sim tim7s
    +     		+extern
    +
    + +
    +
    + +

    ◆ tim12s

    + +
    +
    + + + + + +
    + + + + +
    struct TIM_Sim tim12s
    +     		+extern
    +
    + +
    +
    diff --git a/DOCS/html/stm32f4xx__matlab__conf_8h__dep__incl.map b/DOCS/html/stm32f4xx__matlab__conf_8h__dep__incl.map index 03f69fe..07e7172 100644 --- a/DOCS/html/stm32f4xx__matlab__conf_8h__dep__incl.map +++ b/DOCS/html/stm32f4xx__matlab__conf_8h__dep__incl.map @@ -1,24 +1,24 @@ - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + diff --git a/DOCS/html/stm32f4xx__matlab__conf_8h__dep__incl.md5 b/DOCS/html/stm32f4xx__matlab__conf_8h__dep__incl.md5 index f15c215..df334ed 100644 --- a/DOCS/html/stm32f4xx__matlab__conf_8h__dep__incl.md5 +++ b/DOCS/html/stm32f4xx__matlab__conf_8h__dep__incl.md5 @@ -1 +1 @@ -cd76fd9772e0f4f3445f12023b1b0603 \ No newline at end of file +fb92f06e8a41e16bf469dee7eff07933 \ No newline at end of file diff --git a/DOCS/html/stm32f4xx__matlab__conf_8h__dep__incl.png b/DOCS/html/stm32f4xx__matlab__conf_8h__dep__incl.png index a1bcb45499d6bdcdf2e81c5b500fe171a3b2855b..a0be312fb4ef0f9cb0316c4c568549137063656f 100644 GIT binary patch literal 35293 zcma%j2{@Gf`>*OPmC##~vSr^1*~S`)v2WRzvX3)YW=Gb3*;|p)o&+hUN|p_`!X%XIV=Vp!u=EK^pVaTc7(I-#ER* zRn`zclp8>E{Trz<)JpuVBL1UZwt{(VRDyx3Uy+<)GeKPRCw z;GGCQtK~FEJ@Bvj&3*0p4*qropKe-t27W55DyKb zE~+;B!R*5G%ZYvK5=4{AtLw(j3D9EOxE+oe>))<*I~sIzYpF{u>^wO;9MsE=nph&v z&~&(e5M_hB{`2&JiM#!QkAE&cRB(>h78mAozb+eR>{z zX4_LTP$`AfrhLx}_o9CJ^~d*@`!qDAiM?+kz3e5-;vH`l7_oPUezNP+-tj}hrIi;X zZoXEMrC$5k(Gk$qoz?RzmRf2|A3xw^yS0gNL9u!PXe~vDi_>CnLX0@67pfsdp}^lO z8JU?j9-f}1?Mw}Sif($izp8TUc#@1->Vo5=w7rFQ<-dp@@P-Pbr{pUWYt z7vh!26r>uPpRN72Xeyr&$PA!9jHZhfILG52odPA%Jki%uB+s6_zw8^Hm8FVWt#?`Q zjXO{;QVRke`a%6l@~h8mPDee`%UWfpn_*D{Z1;xyAMID)G^d_^Vvvfv-{D%UE<1hQ zUre~77eSGkgW+uZB*%6>A$@BPl*g1gL`@~Lbk}+q`KasCAk0o3EcTnrZ?ysW-2=U5 zj>99h`wF%L^5fwxNY%{mQUuXa`)NyDdS5{7)@`kWQ{#ND{utP`+4HHkTd|u*?xhK? zl}GEw;d8KfbtcT7idK^pgT-A&`x3oN^wg)Y(3t~Te<(9-RkxS@O%WQVQFeL2vF{pg zHmpbC)OwgsrSKsAp(vAo^S~>X9iyJ11}v%O-6-{bnw03Zn>2U7%~o8z(&&g~GM{CZ zZn5MLl>gJ0sIoCI_r&c$t$9slmyvp{QMM%@6qbQszwf49lgvE2;G5~0s&{bXV}B2! zBTjGUapm&E`pMU9w20+0jX2&@CA@OV1;T+pVSIet#KtDHHTIUYhq~LDuAyw@&`OtX zX6!+aOLwX_1M<}Uy3S8aP@hD7SyA=>!8!IG$44Wl8|qotsUJS~r^Xb)TUgKbTJKeL5dPHZCL+*@!@1By6 zIPu25O6*nz+hI7Ga0`4IUi0EiZqW#jKjkBRrD(kUK6SYn@O!-Mxze~z(sQrwVaLw7 zjCNS8W2f65a@j3C;owx*7oz}aKL2>DpusuNBm72P@m$4Uz0X#%_M5F|K0ef)ay zajX67%;n1?xkdR}V?n%F+l}9?Zyok-!!U`sbV#$_Y63rTgE8EDfwE@_RvMSNc~Eg0 zQDfNw;e7Z`FZS@Q@!5o}uur{YcHFPTE9nnCV((RRaYk|k|8Y;WeHa56j%9q(^5@Ht z-Mvw4cq*1O-=D)ymCLU!s)TOoelKH!j;4l<_CRo(FfNW*Ir~xD4a{x|c zLbcZ@cW@5YYqY#KcZ0e!HSA;b|4Li2%{0$1`Jk*CVlT6B?3}va^BzE+kN^2Z!_K;L z8ii@nC6E6rJ-?FyqWr%vwPC8Kq* zfsFT_?sRd%i~q;{*S~+gJe}*r8OeH1^3Q(1H|2lgPjKm;%3vvNM6+`zg3u^8zNU2$j+%B3?J3Lht@LCuG(X)Z zFEyC(zsqf1c&bUZr29Fr-K`~=*)7=?prYeUz2d7SRaHibZJ_NJet%Oxd9I@cSjT7i z^fqlKe^u%yH2l}vfY2&zT~K0){(R~d$sp>&!nm(3OOeO0uTL2<-LB2wh;tb(3*kJC zX>=Sv{#CC49kAth^>cG`sbgbfBCb8}jjw~~j4<0vqo2fVsyim!#BHj*0v430k1-Ob zCXjz$9k;1*!{rIeswGcpEY~*R)M4(j0RmLB5+t0h{-2*vxAyPr{{x+@eNX{Fkg~G! zP{eKvr+Pcf&6-y|gSk%0EJ-#$;6ne%$7^U&7kgg*01(0~B*52qbtgOGc&}ff?Z>r8 z%zcM{91e{0Ins95(!!VQB(@@P_ddcIinj;FtB|`7iYgCJ4CZLR_8~icYLaP zRd?Z2IMX|{995-;p+qy{R+K6kJK6L(8&mGyHgVM2f0`UWWLYi%kL|+$ToLH3R7cBU zDQ}U;{jQ8XbNsB6Q@ud%=GFssEpg@c%hqbL)d$z48;hz8q@CwpD_L;y5|2RXDgqYP zc-QpsDU1W3-cDnGftK!3#i_DlSb*NHR`5m?;~t?u*qJYUnV1QDRItStI3<{ zo{ex+|GbCZo{ipqRXVA@0T*tvurW()7|MRHWVMXIks}HSsE)i2y-?e_NmM=Gk#Njr zQQrJW^>e>dl{rzft6(iUFg#MrBMDlJlF+ZWI2ph@x=8j1O)ZBzbLR@!?z`JG!fROO z^{Nm0TwsMPd_i2IJvUx zYEttKKPIFIp5xqAx~8p~=2?#il~s{2VrlADh(hk(w9WMugA$Qp1^xX<)JDee-asqJ zO{FBuMFMr*;~gZyw)CLbt`MLTVoAle(XA*7*Yb#UKzT%VRUP3aoGTz znbQB;=+?T+(CBs+-_JV*#75t)^7`@Xb)QRc;_-Pko%g_)16IYu{Wi}1GcR~fgG%Im zz;rvT$|vRnEyy*l86tzUHWaU8JhoZ{ifQnN|IG8PskCI1io~XN1%_|1hd=IM+xv3J z7Wx2vK881K92EgkBv$L-V_@|WW6GfJJpKUqxW}fuQxYd2|Pg3A6dR;+wL0L9>nzn)+Gi!~(IiEqn{4t5P{UY8_yA3v9C!?Qrn4 zDV6yxAk-9;Tpd}FzXVuD;AZj0^>eMKh}!uv)i=5{fHQPLlTZ`lVvC%;ce(gXj~{{O ztA@$+QXAJgHe|q@@6A6od!)NG=5EYrNXLBLe6%9c$whrSb$%n1PY>^}V;M zxuC`B^^cLw0x_F|+8Nkll57-C`cC@#YTdn(5)z3SqhZFwr7QKi9ONW(`AsG?3QBpsay6gwUT_ExQ5f1iT{4@88 z%$0`L233@NW46%A9WVb@G`@8oJjsA``CNVB0E==!JHf@Fsqd^QOKyW6(3pA*ba4Kf z9jvxsV*VBGR7WYV057=%_OPFiNMGtV9N(e`Pmah9LrS)`i~6xKZ~PMop(MA$ zd1gN&U1j81z9Az!A1c*qm}u=w2t~<(>xlX_a_F$-??I~K(9_!P^It%iF`BZLefCId z_GUhhvLN}YG;+Y&*JAu`d!4$Qh^!pECoj}ocEkx-SE|H(GI0~NwIH2ak^E2fX!WNm zk_rT4#jjr)Q<+yVVWU!y^Hg`Es_J=kEU;hUk&nrJBcwbB?R`eD!|Kvcn>4~Gx*w}< zS^LeCuh9W*qwaRgpj(uZLcWlmK@BDv^FlYeS(oyoH3I!lv}604*~q!hT@;OZYSeii z9YbBz=wxxG+X<4S=f_5w8HUw6_J&aykYdS&K8=R>Gg5FlXlmk;zGneS-k?Ybnrc$M z38g?vYAB&F=s&1XzA8Wj-hdzKEu5CZcLz>W=Wh>>ouu)fuITF%Tdg<)xJz%CZWQi@ zwbbmS3}k&BrYHbS9pE)R{@=VH`J;1vGeO@$j?5Bp)c&@9%Qxjvc!+cWj&tGWYC>$cLlH!So5C3Sx$$-o=tCAf_2o7Ep zLp05xy9Eq~HT2o-*H!OQ4eGi7X$ATLg3L(-B&u7dgMTy_UJzU(Gvcc;FMOlw61?B; z5;puQNLO~BlXv%AFx8|?s$H7`Ylewc_IbAu;q#cSI3WjOB`$#hd75UrZUH#y@!8Cp zv7K}!D+}E^GrR;ZpABVs=Y>;BmU9=8FR*HuNUQGFY3@{?13}kMTSink#!uV;87gQ8 z?b>3GP4V9lm~8V;zIRnlJ>I_^@c8#15R{|h&ZMp9D7xOwf??1R{p)p#OzD;eU!w&E zP{AF|{vD=xXh6Y?}SC599h~^q^Z_-aw(;_0U<|D6txunJ0gaa~lO_>evzV!>9iT6zL z2Ce(6&RrIEBU4ed@u!%^u_(T8s0$^+)UoQy~p z(c7lSB1zSN2(;AQgtU%$Bz@jNKcG?p`#?rnP)+h{2ekygu11aPK!z!^6iVY**OnGc z)(XBKWtap_O>bfcbz5p;JbB@Qqf^ovz%nI))v^PhuJ;Buq9hEniw|xSk9z(SG?J-g zM!KiRjsm%oBb9v4A6{8Pnyc=uX3q^sd8xhs8Fh0<-xIzd>QvQWKbclJYMb^NXM#z^ zRi&lLS?VSaXU@Wg^_sQOVMFIBhhO?nYx)mNr>oX2$g0+sO{CS5gVI+D76)R7FW6iM zStv*n&VnZ!pTq~g#!0!luHYkTH`mY%sw&Vd|LP^%gPh?DMM-2OaKv>@*uC`iw>H*U zlM+-&_4Upn*Cm=Rqw<#dAPe#n>BdPrPLGm`J>B^+Oh2{@ya77VO*2TLr1o32QQqG^ zN<%G++ua6rKj^o1^Q_nREpM{wb|8gEhNtN55!L^7a1&}WbwQC0R6mwY5IVMa(!&A1 z(&i;x6^ijsj)yj(@8X1G&MaVNm9zwQs~_WKk^qr+yKkrv|!kXYWgC z(Ib2SGv#-`6+dE@emip**4Uj#XIogbGUS^HYOq>i2AvjmufB7>q51GbCO=Hay3QCM zvSN+)u^S7@US>cRWr`K3Iec&?Sj(v-tY9` zMn6j=GAM(H6@&aOa?1ReM(!yhQY)htRXQp4GU&r32>A)tz@OacO<(<9J>>AWB^|GF zQ^Wn{D@eYaI{nFal{Ix1IY1)ewpQr2cQ2}VdxKJfD7>^zq{Ju}!FxQ#&hYS-=O*l-Vdz1h!XL(9-8e*oUH;?G=dOH$jF}5Tyx@P%W?+^o8Xp zbAk-{!05xPa(3RBzFJDYaf(U>00nuW;?$)(Zc>v5jTmbK0Ar~c4h1$w)d11w22
    -Go to the documentation of this file.
    1/**************************************************************************
    -
    2Главный заголовочный файл Ð´Ð»Ñ Ð¼Ð°Ñ‚Ð»Ð°Ð±Ð°. Включает дейфайны Ð´Ð»Ñ S-Function,
    -
    3объÑвлÑет базовые функции Ð´Ð»Ñ ÑимулÑции МК и подключает базовые библиотеки:
    -
    4Ð´Ð»Ñ ÑимулÑции "stm32fxxx_matlab_conf.h"
    -
    5Ð´Ð»Ñ S-Function "simstruc.h"
    -
    6Ð´Ð»Ñ Ð¿Ð¾Ñ‚Ð¾ÐºÐ¾Ð² <process.h>
    -
    7
    -
    8**************************************************************************/
    -
    9#ifndef _CONTROLLER_H_
    -
    10#define _CONTROLLER_H_
    -
    11
    -
    12// Includes
    -
    13#include "stm32f4xx_matlab_conf.h" // For stm simulate functions
    -
    14#include "simstruc.h" // For S-Function variables
    -
    15#include <process.h> // For threads
    -
    16
    -
    17
    -
    31// Parametrs of MCU simulator
    -
    32#define CREATE_SUSPENDED 0x00000004
    -
    33
    -
    34#define DEKSTOP_CYCLES_FOR_MCU_APP 0xFFFF
    -
    35#define PORT_WIDTH 16
    -
    36#define PORT_NUMB 3
    -
    37
    -
    38// Parameters of S_Function
    -
    39#define NPARAMS 1
    -
    40#define IN_PORT_WIDTH (8)
    -
    41#define IN_PORT_NUMB 1
    -
    42#define OUT_PORT_WIDTH PORT_WIDTH
    -
    43#define OUT_PORT_NUMB PORT_NUMB
    -
    44#define DISC_STATES_WIDTH PORT_WIDTH*PORT_NUMB
    +Go to the documentation of this file.
    1/**
    +
    2**************************************************************************
    +
    3* @dir ../MCU_Wrapper
    +
    4* @brief <b> Папка Ñ Ð¸Ñходным кодом оболочки МК. </b>
    +
    5* @details
    +
    6Ð’ Ñтой папке ÑодержатьÑÑ Ð¾Ð±Ð¾Ð»Ð¾Ñ‡ÐºÐ°(англ. wrapper) Ð´Ð»Ñ Ð·Ð°Ð¿ÑƒÑка и контролÑ
    +
    7ÑмулÑции микроконтроллеров в MATLAB (любого МК, не только STM).
    +
    8Оболочка предÑтавлÑет Ñобой S-Function - блок в Simulink, который работает
    +
    9по Ñкомпилированому коду. КомпилÑÑ†Ð¸Ñ Ð¿Ñ€Ð¾Ð¸Ñходит Ñ Ð¿Ð¾Ð¼Ð¾Ñ‰ÑŒÑŽ MSVC-компилÑтора.
    +
    10**************************************************************************/
    +
    11
    +
    12/**
    +
    13**************************************************************************
    +
    14* @file mcu_wrapper_conf.h
    +
    15* @brief Заголовочный файл Ð´Ð»Ñ Ð¾Ð±Ð¾Ð»Ð¾Ñ‡ÐºÐ¸ МК.
    +
    16**************************************************************************
    +
    17@details
    +
    18Главный заголовочный файл Ð´Ð»Ñ Ð¼Ð°Ñ‚Ð»Ð°Ð±Ð°. Включает дейфайны Ð´Ð»Ñ S-Function,
    +
    19объÑвлÑет базовые функции Ð´Ð»Ñ ÑимулÑции МК и подключает базовые библиотеки:
    +
    20- Ð´Ð»Ñ ÑимулÑции "stm32fxxx_matlab_conf.h"
    +
    21- Ð´Ð»Ñ S-Function "simstruc.h"
    +
    22- Ð´Ð»Ñ Ð¿Ð¾Ñ‚Ð¾ÐºÐ¾Ð² <process.h>
    +
    23**************************************************************************/
    +
    24#ifndef _CONTROLLER_H_
    +
    25#define _CONTROLLER_H_
    +
    26
    +
    27// Includes
    +
    28#include "stm32f4xx_matlab_conf.h" // For stm simulate functions
    +
    29#include "simstruc.h" // For S-Function variables
    +
    30#include <process.h> // For threads
    +
    31
    +
    32
    +
    33/**
    +
    34 * @defgroup MCU_WRAPPER MCU Wrapper
    +
    35 * @brief Ð’ÑÑкое Ð´Ð»Ñ Ð¾Ð±Ð¾Ð»Ð¾Ñ‡ÐºÐ¸ МК
    +
    36 */
    +
    37
    +
    38/**
    +
    39 * @addtogroup WRAPPER_CONF Wrapper Configuration
    +
    40 * @ingroup MCU_WRAPPER
    +
    41 * @brief Параметры конфигурации Ð´Ð»Ñ Ð¾Ð±Ð¾Ð»Ð¾Ñ‡ÐºÐ¸ МК
    +
    42 * @details ЗдеÑÑŒ дефайнами задаетÑÑ Ð¿Ð°Ñ€Ð°Ð¼ÐµÑ‚Ñ€Ñ‹ оболочки, которые определÑÑŽÑ‚ как она будет работать
    +
    43 * @{
    +
    44 */
    45
    -
    57typedef void* HANDLE;
    -
    58
    -
    -
    63typedef struct {
    -
    64 // MCU Thread
    -
    65 HANDLE hMCUThread;
    -
    66 uint32_t idMCUThread;
    -
    67 // Flags
    -
    68 unsigned fMCU_Stop : 1;
    -
    69 double SIM_Sample_Time;
    +
    46// Parametrs of MCU simulator
    +
    47#define CREATE_SUSPENDED 0x00000004 ///< define from WinBase.h. We dont wanna include "Windows.h" or smth like this, because of HAL there are a lot of redefine errors.
    +
    48
    +
    49#define DEKSTOP_CYCLES_FOR_MCU_APP 0xFFFF ///< number of for() cycles after which MCU thread would be suspended
    +
    50#define PORT_WIDTH 16 ///< width of one port
    +
    51#define PORT_NUMB 3 ///< amount of ports
    +
    52
    +
    53// Parameters of S_Function
    +
    54#define NPARAMS 1 ///< number of input parametrs (only Ts)
    +
    55#define IN_PORT_WIDTH (8) ///< width of input ports
    +
    56#define IN_PORT_NUMB 1 ///< number of input ports
    +
    57#define OUT_PORT_WIDTH PORT_WIDTH ///< width of output ports
    +
    58#define OUT_PORT_NUMB PORT_NUMB ///< number of output ports
    +
    59#define DISC_STATES_WIDTH PORT_WIDTH*PORT_NUMB ///< width of discrete states array
    +
    60
    +
    61/** WRAPPER_CONF
    +
    62 * @}
    +
    63 */
    +
    64
    +
    65
    +
    66/**
    +
    67 * @addtogroup MCU_WRAPPER
    +
    68 * @{
    +
    69 */
    70
    -
    71}SIM__MCUHandleTypeDef;
    +
    71typedef void* HANDLE; ///< MCU handle typedef
    +
    72
    +
    73/**
    +
    74 * @brief MCU handle Structure definition.
    +
    75 * @note Prefixes: h - handle, s - settings, f - flag
    +
    76 */
    +
    +
    77typedef struct {
    +
    78 // MCU Thread
    +
    79 HANDLE hMCUThread; ///< Хендл Ð´Ð»Ñ Ð¿Ð¾Ñ‚Ð¾ÐºÐ° МК
    +
    80 uint32_t idMCUThread; ///< id потока МК (unused)
    +
    81 // Flags
    +
    82 unsigned fMCU_Stop : 1; ///< флаг Ð´Ð»Ñ Ð²Ñ‹Ñ…Ð¾Ð´Ð° из потока программы МК
    +
    83 double SIM_Sample_Time; ///< sample time of simulation
    +
    84
    +
    85}SIM__MCUHandleTypeDef;
    -
    72extern SIM__MCUHandleTypeDef hmcu;
    -
    73
    -
    74//-------------------------------------------------------------//
    -
    75//------------------ SIMULINK WHILE DEFINES -----------------//
    -
    76/* DEFINE TO WHILE WITH SIMULINK WHILE */
    -
    82#define while(_expression_) sim_while(_expression_)
    -
    83
    -
    84/* SIMULINK WHILE */
    -
    92#define sim_while(_expression_) while((_expression_)&&(hmcu.MCU_Stop == 0))
    -
    93
    -
    94/* DEFAULT WHILE */
    -
    100#define native_while(_expression_) for(; (_expression_); )
    -
    101 /***************************************************************/
    -
    102
    -
    103//------------------ SIMULINK WHILE DEFINES -----------------//
    -
    104//-------------------------------------------------------------//
    -
    105
    -
    106
    +
    86extern SIM__MCUHandleTypeDef hmcu; // extern Ð´Ð»Ñ Ð²Ð¸Ð´Ð¸Ð¼Ð¾Ñти переменной во вÑех файлах
    +
    87
    +
    88//-------------------------------------------------------------//
    +
    89//------------------ SIMULINK WHILE DEFINES -----------------//
    +
    90/* DEFINE TO WHILE WITH SIMULINK WHILE */
    +
    91/**
    +
    92 * @brief Redefine C while statement with sim_while() macro.
    +
    93 * @param _expression_ - expression for while.
    +
    94 * @details Это while который будет иÑпользоватьÑÑ Ð² Ñимулинке @ref sim_while Ð´Ð»Ñ Ð¿Ð¾Ð´Ñ€Ð¾Ð±Ð½Ð¾Ñтей.
    +
    95 */
    +
    96#define while(_expression_) sim_while(_expression_)
    +
    97
    +
    98/* SIMULINK WHILE */
    +
    99/**
    +
    100 * @brief While statement for emulate MCU code in Simulink.
    +
    101 * @param _expression_ - expression for while.
    +
    102 * @details Данный while необходим, чтобы в конце ÑимулÑции, завершить поток МК:
    +
    103 * При выÑтавлении флага Ð¾ÐºÐ¾Ð½Ñ‡Ð°Ð½Ð¸Ñ ÑимулÑции, вÑе while будут пропуÑкатьÑÑ
    +
    104 * и поток Ñможет дойти до конца функции main и завершить ÑебÑ.
    +
    105 */
    +
    106#define sim_while(_expression_) while((_expression_)&&(hmcu.fMCU_Stop == 0))
    107
    -
    108//-------------------------------------------------------------//
    -
    109//---------------- SIMULATE FUNCTIONS PROTOTYPES -------------//
    -
    110/* step simulation */
    -
    111void MCU_Step_Simulation(SimStruct *S, time_T time);
    -
    112
    -
    113/* MCU peripheral simulation */
    -
    114void MCU_Periph_Simulation(void);
    -
    115
    -
    116/* initialize MCU simulation */
    -
    117void SIM_Initialize_Simulation(void);
    -
    118
    -
    119/* deinitialize MCU simulation */
    -
    120void SIM_deInitialize_Simulation(void);
    +
    108/* DEFAULT WHILE */
    +
    109/**
    +
    110 * @brief Default/Native C while statement.
    +
    111 * @param _expression_ - expression for while.
    +
    112 * @details Данный while - аналог обычного while, без дополнительного функционала.
    +
    113 */
    +
    114#define native_while(_expression_) for(; (_expression_); )
    +
    115 /***************************************************************/
    +
    116
    +
    117//------------------ SIMULINK WHILE DEFINES -----------------//
    +
    118//-------------------------------------------------------------//
    +
    119
    +
    120
    121
    -
    122/* read inputs S-function */
    -
    123void MCU_readInputs(real_T* in);
    -
    124
    -
    125/* write outputs S-function (disc states) */
    -
    126void MCU_writeOutputs(real_T* disc);
    -
    127
    -
    128/* write outputs of block of S-Function*/
    -
    129void SIM_writeOutput(SimStruct* S);
    -
    130//---------------- SIMULATE FUNCTIONS PROTOTYPES -------------//
    -
    131//-------------------------------------------------------------//
    +
    122//-------------------------------------------------------------//
    +
    123//---------------- SIMULATE FUNCTIONS PROTOTYPES -------------//
    +
    124/* Step simulation */
    +
    125void MCU_Step_Simulation(SimStruct *S, time_T time);
    +
    126
    +
    127/* MCU peripheral simulation */
    +
    128void MCU_Periph_Simulation(void);
    +
    129
    +
    130/* Initialize MCU simulation */
    +
    131void SIM_Initialize_Simulation(void);
    132
    -
    136#endif // _CONTROLLER_H_
    -
    HANDLE
    void * HANDLE
    MCU handle typedef.
    Definition mcu_wrapper_conf.h:57
    -
    SIM_Initialize_Simulation
    void SIM_Initialize_Simulation(void)
    Initialize structures and variables for simulating MCU.
    Definition mcu_wrapper.c:129
    -
    SIM_deInitialize_Simulation
    void SIM_deInitialize_Simulation(void)
    Deinitialize structures and variables for simulating MCU.
    Definition mcu_wrapper.c:144
    -
    hmcu
    SIM__MCUHandleTypeDef hmcu
    extern Ð´Ð»Ñ Ð²Ð¸Ð´Ð¸Ð¼Ð¾Ñти переменной во вÑех файлах
    Definition mcu_wrapper.c:7
    -
    MCU_writeOutputs
    void MCU_writeOutputs(real_T *disc)
    -
    MCU_readInputs
    void MCU_readInputs(real_T *in)
    -
    MCU_Periph_Simulation
    void MCU_Periph_Simulation(void)
    Simulate peripheral of MCU.
    Definition mcu_wrapper.c:58
    -
    SIM_writeOutput
    void SIM_writeOutput(SimStruct *S)
    -
    MCU_Step_Simulation
    void MCU_Step_Simulation(SimStruct *S, time_T time)
    Read from simulink S-Block Inputs and write to MCU I/O ports.
    Definition mcu_wrapper.c:38
    -
    uint32_t
    unsigned int uint32_t
    Definition stdint.h:64
    -
    stm32f4xx_matlab_conf.h
    -
    SIM__MCUHandleTypeDef
    MCU handle Structure definition.
    Definition mcu_wrapper_conf.h:63
    -
    SIM__MCUHandleTypeDef::idMCUThread
    uint32_t idMCUThread
    id потока МК (unused)
    Definition mcu_wrapper_conf.h:66
    -
    SIM__MCUHandleTypeDef::SIM_Sample_Time
    double SIM_Sample_Time
    sample time of simulation
    Definition mcu_wrapper_conf.h:69
    -
    SIM__MCUHandleTypeDef::fMCU_Stop
    unsigned fMCU_Stop
    флаг Ð´Ð»Ñ Ð²Ñ‹Ñ…Ð¾Ð´Ð° из потока программы МК
    Definition mcu_wrapper_conf.h:68
    -
    SIM__MCUHandleTypeDef::hMCUThread
    HANDLE hMCUThread
    Хендл Ð´Ð»Ñ Ð¿Ð¾Ñ‚Ð¾ÐºÐ° МК
    Definition mcu_wrapper_conf.h:65
    +
    133/* Deinitialize MCU simulation */
    +
    134void SIM_deInitialize_Simulation(void);
    +
    135
    +
    136/* Read inputs S-function */
    +
    137void MCU_readInputs(SimStruct* S);
    +
    138
    +
    139/* Write pre-outputs S-function (out_buff states) */
    +
    140void MCU_writeOutputs(SimStruct* S);
    +
    141
    +
    142/* Write outputs of block of S-Function*/
    +
    143void SIM_writeOutput(SimStruct* S);
    +
    144//---------------- SIMULATE FUNCTIONS PROTOTYPES -------------//
    +
    145//-------------------------------------------------------------//
    +
    146
    +
    147/** MCU_WRAPPER
    +
    148 * @}
    +
    149 */
    +
    150#endif // _CONTROLLER_H_
    +
    151
    +
    152
    +
    153//-------------------------------------------------------------//
    +
    154//---------------------BAT FILE DESCRIBTION--------------------//
    +
    155/**
    +
    156 * @file run_mex.bat
    +
    157 * @brief Батник Ð´Ð»Ñ ÐºÐ¾Ð¼Ð¿Ð¸Ð»Ñции оболочки МК.
    +
    158 * @details
    +
    159 * ВызываетÑÑ Ð² матлабе из mexing.m.
    +
    160 *
    +
    161 * ИÑходный код батника:
    +
    162 * @include F:\Work\Projects\MATLAB\matlab_stm_emulate\MCU_Wrapper\run_mex.bat
    +
    163 */
    +
    MCU_readInputs
    void MCU_readInputs(SimStruct *S)
    Считывание входов S-Function в порты ввода-вывода.
    Definition mcu_wrapper.c:88
    +
    SIM_Initialize_Simulation
    void SIM_Initialize_Simulation(void)
    Ð˜Ð½Ð¸Ñ†Ð¸Ð°Ð»Ð¸Ð·Ð°Ñ†Ð¸Ñ ÑимулÑции МК.
    Definition mcu_wrapper.c:145
    +
    SIM_deInitialize_Simulation
    void SIM_deInitialize_Simulation(void)
    Ð”ÐµÐ¸Ð½Ð¸Ñ†Ð¸Ð°Ð»Ð¸Ð·Ð°Ñ†Ð¸Ñ ÑимулÑции МК.
    Definition mcu_wrapper.c:162
    +
    hmcu
    SIM__MCUHandleTypeDef hmcu
    Хендл Ð´Ð»Ñ ÑƒÐ¿Ñ€Ð°Ð²Ð»ÐµÐ½Ð¸Ñ Ð¿Ð¾Ñ‚Ð¾ÐºÐ¾Ð¼ программы МК
    Definition mcu_wrapper.c:16
    +
    HANDLE
    void * HANDLE
    MCU handle typedef.
    Definition mcu_wrapper_conf.h:71
    +
    MCU_Periph_Simulation
    void MCU_Periph_Simulation(void)
    СимулÑÑ†Ð¸Ñ Ð¿ÐµÑ€Ð¸Ñ„ÐµÑ€Ð¸Ð¸ МК
    Definition mcu_wrapper.c:73
    +
    SIM_writeOutput
    void SIM_writeOutput(SimStruct *S)
    +
    MCU_Step_Simulation
    void MCU_Step_Simulation(SimStruct *S, time_T time)
    СимулÑÑ†Ð¸Ñ ÐœÐš на один такт ÑимулÑции.
    Definition mcu_wrapper.c:53
    +
    MCU_writeOutputs
    void MCU_writeOutputs(SimStruct *S)
    ЗапиÑÑŒ портов ввода-вывода в буфер выхода S-Function.
    Definition mcu_wrapper.c:102
    +
    stm32f4xx_matlab_conf.h
    Заголовочный файл Ð´Ð»Ñ ÐºÐ¾Ð½Ñ„Ð¸Ð³ÑƒÑ€Ð°Ñ†Ð¸Ð¸ ÑимулÑтора МК.
    +
    SIM__MCUHandleTypeDef
    MCU handle Structure definition.
    Definition mcu_wrapper_conf.h:77
    +
    SIM__MCUHandleTypeDef::idMCUThread
    uint32_t idMCUThread
    id потока МК (unused)
    Definition mcu_wrapper_conf.h:80
    +
    SIM__MCUHandleTypeDef::SIM_Sample_Time
    double SIM_Sample_Time
    sample time of simulation
    Definition mcu_wrapper_conf.h:83
    +
    SIM__MCUHandleTypeDef::fMCU_Stop
    unsigned fMCU_Stop
    флаг Ð´Ð»Ñ Ð²Ñ‹Ñ…Ð¾Ð´Ð° из потока программы МК
    Definition mcu_wrapper_conf.h:82
    +
    SIM__MCUHandleTypeDef::hMCUThread
    HANDLE hMCUThread
    Хендл Ð´Ð»Ñ Ð¿Ð¾Ñ‚Ð¾ÐºÐ° МК
    Definition mcu_wrapper_conf.h:79
    diff --git a/DOCS/html/md__f_1_2_work_2_projects_2_m_a_t_l_a_b_2matlab__stm__emulate_2_r_e_a_d_m_e.html b/DOCS/html/md__f_1_2_work_2_projects_2_m_a_t_l_a_b_2matlab__stm__emulate_2_r_e_a_d_m_e.html deleted file mode 100644 index e7b1fc5..0000000 --- a/DOCS/html/md__f_1_2_work_2_projects_2_m_a_t_l_a_b_2matlab__stm__emulate_2_r_e_a_d_m_e.html +++ /dev/null @@ -1,228 +0,0 @@ - - - - - - - -STM MATLAB Simulator: MATLAB STM32 EMULATOR - - - - - - - - - - - -
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    MATLAB STM32 EMULATOR
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    СОДЕРЖÐÐИЕ

      -
    • ÐžÐ±Ñ‰Ð°Ñ Ñтруктура ÑмулÑтора
      • -
    • ОпиÑание Ñтуктуры ÑмулÑтора (пример Ð´Ð»Ñ STM32)
        -
      • Оболочка МК
        • -
      • ЭмулÑтор STM Ð´Ð»Ñ MATLAB
        • -
      • Код пользователÑ
        • -
      -
      • -
    • ИнÑтрукциÑ
        -
      • Портирование кода
        • -
      • Как Ñкомпилировать код
        • -
      • Как запуÑтить отладку
        • -
      • Ошибки при портировании
        • -
      -
      • -
    -

    -ÐžÐ±Ñ‰Ð°Ñ Ñтруктура ÑмулÑтора

    -

    ЭмулÑтор ÑоÑтоит из блух блоков:

      -
    • приложение МК
      • -
    • оболочка МК Ð´Ð»Ñ MATLAB, ÐºÐ¾Ñ‚Ð¾Ñ€Ð°Ñ Ð·Ð°Ð¿ÑƒÑкает приложение МК и Ñмулирует его периферию
      • -
    -

    Приложение МК в Ñвою очередь разделено еще на два блока:

      -
    • иÑходный код Ð¿Ð¾Ð»ÑŒÐ·Ð¾Ð²Ð°Ñ‚ÐµÐ»Ñ (код приложениÑ)
      • -
    • иÑходный код библиотек и драйверов
      • -
    -

    Ð”Ð»Ñ ÐºÐ°Ð¶Ð´Ð¾Ð³Ð¾ блока ÑÐ²Ð¾Ñ Ð¿Ð°Ð¿ÐºÐ°. Ð’Ñего три папки:

      -
    • Code (_код пользователÑ_)
      • -
    • MCU_STM32xxx_Matlab (_ÑмулÑтор STM Ð´Ð»Ñ MATLAB_)
      • -
    • MCU_Wrapper (_оболочка МК_) *в Ñкобочках ÑÑылки на подробное опиÑание папки
      • -
    -

    Далее приведена Ñтруктура ÑмулÑтора. ИнÑÑ‚Ñ€ÑƒÐºÑ†Ð¸Ñ Ð´Ð»Ñ Ð¿Ð¾Ñ€Ñ‚Ð¸Ñ€Ð¾Ð²Ð°Ð½Ð¸Ñ ÐºÐ¾Ð´Ð° в MATLAB приведена ниже

    -

    -ОпиÑание Ñтуктуры ÑмулÑтора (пример Ð´Ð»Ñ STM32)

    -

    ЗдеÑÑŒ ÑодержитьÑÑ Ð¾Ð¿Ð¸Ñание трех блоков ÑмулÑтора:

      -
    • Оболочка МК
      • -
    • ЭмулÑтор STM Ð´Ð»Ñ MATLAB
      • -
    • Код пользователÑ
      • -
    -

    -Оболочка МК

    -

    Ð’ Ñтой папке ÑодержатьÑÑ Ð¾Ð±Ð¾Ð»Ð¾Ñ‡ÐºÐ°(англ. wrapper) Ð´Ð»Ñ Ð·Ð°Ð¿ÑƒÑка и ÐºÐ¾Ð½Ñ‚Ñ€Ð¾Ð»Ñ ÑмулÑции микроконтроллеров в MATLAB (любого МК, не только STM). Оболочка предÑтавлÑет Ñобой S-Function - блок в Simulink, который работает по Ñкомпилированому коду. КомпилÑÑ†Ð¸Ñ Ð¿Ñ€Ð¾Ð¸Ñходит Ñ Ð¿Ð¾Ð¼Ð¾Ñ‰ÑŒÑŽ MSVC-компилÑтора.

    -

    S-Function работает оÑобым образом: на шаге n она запуÑкает Ñкомпилированный код и ждет пока Ñтот код выполнитьÑÑ. Только когда завершаетÑÑ Ð²Ñ‹Ð¿Ð¾Ð»Ð½ÐµÐ½Ð¸Ðµ кода, S-Function переходит на Ñледующий шаг n+1.

    -

    Ðо программа МК Ñто беÑконечный цикл, который никогда не завершаетÑÑ. ПоÑтому еÑÑ‚ÑŒ неÑколько оÑобенноÑтей в выполнении такого кода в виде S-Function:

      -
    • Ð”Ð»Ñ ÑмулÑции ÑоздаетÑÑ Ð¾Ñ‚Ð´ÐµÐ»ÑŒÐ½Ñ‹Ð¹ поток Ð´Ð»Ñ Ð¿Ñ€Ð¾Ð³Ñ€Ð°Ð¼Ð¼Ñ‹ МК. Этот поток запуÑкаетÑÑ Ð² начале текущего шага ÑимулÑции, выполнÑетÑÑ ÐºÐ°ÐºÐ¾Ðµ-то времÑ, а потом приоÑтанавливаетÑÑ. Это позволÑет коду S-Function завершитьÑÑ Ð¸ перейти на Ñледующий шаг.
      • -
    • Ðеобходимо закрыть поток программы МК в конце ÑимулÑции. Ð”Ð»Ñ Ñтого иÑпользуетÑÑ Ð¾Ñобый дефайн Ð´Ð»Ñ while. Этот дефайн помимо уÑÐ»Ð¾Ð²Ð¸Ñ while, проверÑет уÑловие Ð¾ÐºÐ¾Ð½Ñ‡Ð°Ð½Ð¸Ñ ÑимулÑции. И еÑли ÑимулÑцию надо завершить, вÑе беÑконечные циклы while() пропуÑкаютÑÑ Ð¸ поток доходит до конца функции main() и завершает ÑебÑ.
      • -
    -

    Ð’Ñего оболочка Ñодержит 4 файла:

      -
    • mcu_wrapper.c     - файл, который запуÑкает код МК и управлÑет его ходом. Ð’ нем ÑодержатьÑÑ Ñ„ÑƒÐ½ÐºÑ†Ð¸Ð¸ Ð´Ð»Ñ Ð·Ð°Ð¿ÑƒÑка/оÑтановки потока программы МК, Ñчитывании входов и запиÑÑŒ входов S-Function в ÑоответÑтвии Ñ I/O портами МК.
      • -
    • MCU.c          - базовый файл, который предÑтавлÑет Ñобой иÑходный код Ð´Ð»Ñ ÐºÐ¾Ð¼Ð¿Ð¸Ð»Ñции S-Function в MATLAB. Вызывает функции из "mcu_wrapper.c"
      • -
    • mcu_wrapper_conf.h   - общий Ð´Ð»Ñ mcu_wrapper.c и MCU.c заголовочный файл. Содержит наÑтройки Ð´Ð»Ñ Ð±Ð»Ð¾ÐºÐ° S-Function, а также дефайны Ð´Ð»Ñ ÑƒÐ¿Ñ€Ð°Ð²Ð»ÐµÐ½Ð¸Ñ Ñ…Ð¾Ð´Ð¾Ð¼ программы МК.
      • -
    • run_mex.bat       - Ñкрипт Ð´Ð»Ñ ÐºÐ¾Ð¼Ð¿Ð¸Ð»Ñции кода компилÑтором MSVC. Ð’ нем пропиÑываютÑÑ Ð¿ÑƒÑ‚Ð¸ Ð´Ð»Ñ Ð·Ð°Ð³Ð¾Ð»Ð¾Ð²Ð¾Ñ‡Ð½Ñ‹Ñ… файлов ".h", указываютÑÑ Ñ„Ð°Ð¹Ð»Ñ‹ иÑходного кода ".c" и пропиÑываютÑÑ Ð´ÐµÑ„Ð°Ð¹Ð½Ñ‹ Ð´Ð»Ñ ÐºÐ¾Ð¼Ð¿Ð¸Ð»Ñции.
      • -
    -

    -ЭмулÑтор STM Ð´Ð»Ñ MATLAB

    -

    Ð’ папке "_\MCU_STM32xxx_Matlab_" еÑÑ‚ÑŒ два файла "stm32fxxx_matlab_conf.c/.h".

    -

    Ð’ них задаётÑÑ Ð¸ÑÐ¿Ð¾Ð»ÑŒÐ·ÑƒÐµÐ¼Ð°Ñ Ð¿ÐµÑ€Ð¸Ñ„ÐµÑ€Ð¸Ñ Ð¸ подключаютÑÑ Ð±Ð¸Ð±Ð»Ð¸Ð¾Ñ‚ÐµÐºÐ¸ Ð´Ð»Ñ Ð¿ÐµÑ€Ð¸Ñ„ÐµÑ€Ð¸Ð¸. Также объÑвлÑÑŽÑ‚ÑÑ Ñ„ÑƒÐ½ÐºÐºÑ†Ð¸Ð¸ Ð´Ð»Ñ Ð¸Ð½Ð¸Ñ†Ð¸Ð°Ð»Ð¸Ð·Ð°Ñ†Ð¸Ð¸/деинициализации периферии МК и Ñтруктуры Ð´Ð»Ñ ÑмулÑции периферии.

    -

    Ð’ папке "_\MCU_STM32xxx_Matlab\Drivers_" находÑÑ‚ÑŒÑÑ Ñтандартные библиотеки Ð´Ð»Ñ STM/ARM, но переделанные под компилÑтор MSVC. Ð’Ñего там три папки: STM32F4xx_SIMULINK, CMSIS, STM32F4xx_HAL_Driver.

    -
    Папка STM32F4xx_SIMULINK
    -

    Ð’ Ñтой папке ÑодержатьÑÑ Ñ„Ð°Ð¹Ð»Ñ‹ Ð´Ð»Ñ ÑмулÑции периферии STM32 в MATLAB. Структура файлов Ñ‚Ð°ÐºÐ°Ñ Ð¶Ðµ, как в библиотеки HAL:

      -
    • название Ñерии МК, который ÑмулируетÑÑ (matlab),
      • -
    • идентификатор, что Ñто Ð´Ð»Ñ MATLAB (matlab),
      • -
    • перифериÑ, функции Ð´Ð»Ñ ÑмулÑции которой Ñодержит конкретный файл (gpio, tim). Пример: "stm32f4xx_matlab_tim.c/.h"
      • -
    -
    Папка CMSIS
    -

    "Порт" библиотеки CMSIS Ð´Ð»Ñ MSVC. Ðиже приведен перечень вÑех файлов и краткое опиÑание зачем они нужны:

      -
    • arm_defines.h Содержит ARM дефайны Ð´Ð»Ñ ÐºÐ¾Ð¼Ð¿Ð¸Ð»Ñции в MSVC.
      • -
    • core_cm4_matlab.h Данный файл ÑвлÑетÑÑ ÐºÐ¾Ð¿Ð¸ÐµÐ¹ "core_cm4.h" Ñ Ð½ÐµÐºÐ¾Ñ‚Ð¾Ñ€Ñ‹Ð¼Ð¸ изменениÑми
        -
      • удалены первые ~160 Ñтрок, которые определÑÑŽÑ‚ компилÑтор ARM.
        • -
      • добавлена Ñтруктура Ð¸Ð¼Ð¸Ñ‚Ð¸Ñ€ÑƒÑŽÑ‰Ð°Ñ Ð¿Ð°Ð¼ÑÑ‚ÑŒ Ñдра***. Ð”Ð»Ñ Ñ‚Ð¾Ð³Ð¾, чтобы при обращении по адреÑам региÑтров МК не было иÑключений при чтении по недоÑтупному адреÑу.
        • -
      -
      • -
    • **stdint.h Данный файл ÑвлÑетÑÑ ÐºÐ¾Ð¿Ð¸ÐµÐ¹ "stdint.h", из библиотеки Ð´Ð»Ñ STM32. (только вÑе дефайны uint32_t передалны как uint64_t. Т.к. в MATLAB вÑÑ‘ компилируетÑÑ Ð² 64-битном формате, то Ñохранении адреÑов в 32-битных переменных, адреÑа будут уÑекатьÑÑ Ð¸ будут ошибки.)
      • -
    • stm32f407xx_matlab.h Данный файл ÑвлÑетÑÑ ÐºÐ¾Ð¿Ð¸ÐµÐ¹ "stm32f407xx.h" Ñ Ð½ÐµÐºÐ¾Ñ‚Ð¾Ñ€Ñ‹Ð¼Ð¸ изменениÑми:
        -
      • добавлен каÑтомный "stdint.h" (через "", вмеÑто <>)
        • -
      • добавлен "arm_defines.h" Ñ ARM дефайнами Ð´Ð»Ñ MSVC
        • -
      • добавлен матлабовÑкий "cmsis_armcc_matlab.h" Ñ Ð²Ð¼ÐµÑто "cmsis_armcc.h"
        • -
      • добавлена Ñтруктура Ð¸Ð¼Ð¸Ñ‚Ð¸Ñ€ÑƒÑŽÑ‰Ð°Ñ Ð¿Ð°Ð¼ÑÑ‚ÑŒ Ñдра***. Ð”Ð»Ñ Ñ‚Ð¾Ð³Ð¾, чтобы при обращении по адреÑам региÑтров МК не было иÑключений при чтении по недоÑтупному адреÑу.
        • -
      -
      • -
    • **stm32f4xx.h - оригинальный файл "stm32f4xx.h".
      • -
    • system_stm32f4xx.h - оригинальный файл "system_stm32f4xx.h".
      • -
    -

    *памÑÑ‚ÑŒ Ñдра не имитируетÑÑ Ð² полной мере, потому что STM32 - Ñто 32-битный процеÑÑор, он имеет 4 Гб памÑти. Ð MATLAB/MSVC делает ограничение на иÑпользование не больше 4Гб оперативной памÑти. При Ñтом еще еÑÑ‚ÑŒ матлабовÑкие переменные которые тоже занимают меÑто. ПоÑтому памÑÑ‚ÑŒ ÑмулируетÑÑ Ð»Ð¸ÑˆÑŒ чаÑтично. Как имено - задаетÑÑ Ð² дефайнах и Ñтруктуруре stm32f407xx_matlab.h.

    -
    Папка STM32F4xx_HAL_Driver
    -

    Ð”Ð°Ð½Ð½Ð°Ñ Ð±Ð¸Ð±Ð»Ð¸Ð¾Ñ‚ÐµÐºÐ° ÑвлÑетÑÑ ÐºÐ¾Ð¿Ð¸ÐµÐ¹ HAL, за некоторыми иÑключениÑми. Ð’ оÑновном каÑаютÑÑ Ð¼Ð°ÐºÑ€Ð¾Ñов Ð´Ð»Ñ Ð¾Ð¶Ð¸Ð´Ð°Ð½Ð¸Ñ Ñ„Ð»Ð°Ð³Ð°. Т.к. веÑÑŒ МК реализован програмно, то надо Ñамому пиÑать код, который будет выÑтавлÑÑ‚ÑŒ флаги по определенным уÑловиÑм. Только тогда библиотека HAL будет Ñто Ñчитывать и выполнÑÑ‚ÑŒ Ñвои функции. Ðо далеко не вÑегда еÑÑ‚ÑŒ необходимоÑÑ‚ÑŒ так делать.

    -

    ПоÑтому, вмеÑто того, чтобы пользоватьÑÑ Ð¾Ñ€Ð¸Ð³Ð¸Ð°Ð»ÑŒÐ½Ñ‹Ð¼ HAL и пиÑать ÑмулÑтор Ð´Ð»Ñ Ð²Ñего 32-битного контроллера, можно перепиÑать макроÑÑ‹ или даже функции целиком под Ñвои нужды.

    -

    -Код пользователÑ

    -

    Ð”Ð°Ð½Ð½Ð°Ñ Ð¿Ð°Ð¿ÐºÐ° Ñодержит иÑходный код Ð¿Ñ€Ð¸Ð»Ð¾Ð¶ÐµÐ½Ð¸Ñ ÐœÐš. При Ñтом драйверы и Ñтандартные/HAL библиотеки, которые общие Ð´Ð»Ñ Ð²Ñех проектов Ñледует помещать в папку Ñ ÑмулÑтором МК. Чтобы не редактировать иÑходники общих библиотек (CMSIS/HAL) в каждом проекте.

    -

    -ИнÑтрукциÑ

    -

    Общий алгоритм Ð¿Ð¾Ñ€Ñ‚Ð¸Ñ€Ð¾Ð²Ð°Ð½Ð¸Ñ ÐºÐ¾Ð´Ð° Ð´Ð»Ñ ÑимулÑции в MATLAB приведен ниже. Ð’ инÑтрукции еÑÑ‚ÑŒ ÑÑылки на более подробное опиÑание дейÑтвий.

      -
    1. Портировать код Ð´Ð»Ñ MATLAB (можно начать Ñ Ð¿Ð¾Ñ€Ñ‚Ð¸Ñ€Ð¾Ð²Ð°Ð½Ð¸Ñ Ð±ÐµÐ· изменений и далее дейÑтвовать от шага 2)
      2. -
    2. Проверить компилируетьÑÑ Ð»Ð¸ код. Рдалее:
        -
      • еÑли еÑÑ‚ÑŒ ошибки при компилÑции, иÑправить их и вернутьÑÑ Ð½Ð° шаг 2.
        • -
      • еÑли ошибок нет, перейти на шаг 3.
        • -
      -
      3. -
    3. Проверить нормально ли запуÑкаетÑÑ Ð¸ работает ÑимулÑÑ†Ð¸Ñ Ñ ÐœÐš. Рдалее:
        -
      • еÑли ÑимулÑции вылетает, то необходимо иÑправить ошибки в режиме отладки и вернутьÑÑ Ð½Ð° шаг 3.
        • -
      • еÑли ÑимулÑÑ†Ð¸Ñ Ð½Ð¾Ñ€Ð¼Ð°Ð»ÑŒÐ½Ð¾ запуÑкаетÑÑ Ñ‚Ð¾Ð»ÑŒÐºÐ¾ один раз, и не завершаетÑÑ Ð¸Ð»Ð¸ не запуÑкаетÑÑ Ð²Ñ‚Ð¾Ñ€Ð¾Ð¹ раз, то необходимо иÑправить ошибки в режиме отладки и вернутьÑÑ Ð½Ð° шаг 3.
        • -
      • еÑли ÑимулÑÑ†Ð¸Ñ Ñ€Ð°Ð±Ð¾Ñ‚Ð°ÐµÑ‚ полноÑтью корректно, перейти на шаг. 4.
        • -
      -
      4. -
    4. Оценить результаты ÑимулÑции. Рдалее:
        -
      • еÑли ÑимулÑÑ†Ð¸Ñ ÑходитÑÑ Ñ Ñ€ÐµÐ°Ð»ÑŒÐ½Ð¾Ñтью - то вÑÑ‘ работает корректно.
        • -
      • еÑли нет - необходимо иÑправить ошибки в драйверах и перейти на шаг 2.
        • -
      -
      5. -
    -

    -Портирование кода

    -
    Код программы
    -

    Ð”Ð»Ñ Ð½Ð°Ñ‡Ð°Ð»Ð° необходимо веÑÑŒ пользовательÑкий код портировать в отдельную папку Ð´Ð»Ñ ÑƒÐ´Ð¾Ð±Ñтва. Ðапример в "_\Code_".

    -

    Далее в "[run_bat.mex](#оболочка-мк)" надо пропиÑать пути Ð´Ð»Ñ Ð·Ð°Ð³Ð¾Ð»Ð¾Ð²Ð¾Ñ‡Ð½Ñ‹Ñ… файлов (_\Includes_). Ð’Ñе файлы иÑходников "_*.c_" пропиÑывать не обÑзательно. Можно пропиÑать только папки Ñ Ð¸Ñходниками, как Ñ Ð·Ð°Ð³Ð¾Ð»Ð¾Ð²Ð¾Ñ‡Ð½Ñ‹Ð¼Ð¸ файлами. Далее Ñкрипт Ñам Ñканирует и ищет вÑе иÑходники.

    -
    ЭмулÑтор и библиотеки
    -

    ЭмулÑтор и библиотеки ÑвÑзаны в том плане, что необходимо выбрать через что будет реализована перифериÑ

      -
    • полноценный ÑмулÑтор, тогда функции библиотек оÑтаютÑÑ Ð±ÐµÐ· изменений и проÑто работает не Ñ Ñ€ÐµÐ°Ð»ÑŒÐ½Ð¾Ð¹ периферией, а Ñ ÐµÑ‘ ÑмулÑтором
      • -
    • упрощенный ÑмулÑтор, тогда функции библиотек тоже надо или упроÑтить или Ñделать их-dummy.
      • -
    • игнорирование периферии. ЕÑли Ð¿ÐµÑ€Ð¸Ñ„ÐµÑ€Ð¸Ñ Ð½Ðµ важна Ð´Ð»Ñ ÑимулÑции, можно проÑто в программе МК убрать вÑе выховы функций, ÑвÑзанные Ñ Ð½ÐµÐ¹ или Ñделать их dummy.
      • -
    -

    Скрипты Ð´Ð»Ñ ÑмулÑции периферии необходимо пропиÑывать вручную. Ð’ Ñлучае STM32 руководÑтвоватьÑÑ Ñледует только региÑтрами CMSIS, чтобы не привÑзыватьÑÑ Ðº HAL, и была возможноÑÑ‚ÑŒ ÑимулÑции кода без него. Или же пробовать делать универÑальный через дефайны, которые будут определÑÑ‚ÑŒ доÑтуп к конкретным региÑтрам конкретного МК.

    -
    Примеры ÑмулÑции периферии
    -

    Пример 1 (полноценный ÑмулÑтор): можно напиÑать полный ÑмулÑтор Ð´Ð»Ñ Ñ‚Ð°Ð¹Ð¼ÐµÑ€Ð¾Ð², Ñ‚.к. Ñто очень важна чаÑÑ‚ÑŒ МК. ÐŸÐ»ÑŽÑ Ð¾Ð½Ð° чаÑто корректируетÑÑ: разные режимы таймеров, Ñ€Ð°Ð·Ð½Ð°Ñ Ñ‡Ð°Ñтота, разные каналы. И удобно, еÑли вÑÑ‘ Ñто можно менÑÑ‚ÑŒ "на ходу", а не только во Ð²Ñ€ÐµÐ¼Ñ ÐºÐ¾Ð¼Ð¿Ð¸Ð»Ñциию.

    -

    Пример 2 (упрощенный ÑмулÑтор): Ð’ Ñлучае, еÑли не нужна ÑмулÑÑ†Ð¸Ñ Ð¿ÐµÑ€Ð¸Ñ„ÐµÑ€Ð¸Ð¸. Ðапример Ð´Ð»Ñ Ð¿Ñ€Ð¾Ñ‚Ð¾ÐºÐ¾Ð»Ð¾Ð² общениÑ, типа UART/MODBUS, можно проÑто Ñделать отдельные входы в S-Function, и напрÑмую брать Ð·Ð½Ð°Ñ‡ÐµÐ½Ð¸Ñ Ð¾Ñ‚Ñ‚ÑƒÐ´Ð° и запиÑывать в переменные программы, без приёма отдельных битов, парÑинга и прочего. Ðо тогда надо будет редактировать библиотеки и делать dummy-функции, чтобы они не ждали ответа от периферии, ÐºÐ¾Ñ‚Ð¾Ñ€Ð°Ñ Ð½Ðµ ÑмулируетÑÑ. Или же редактировать пользовательÑкий код.

    -

    Пример 3 (игнорирование периферии): CubeMX иÑпользует функции RCC_Config, которые наÑтраивают тактирование МК. Ð’ HAL'e в функции инициализации поÑтоÑнно иÑпользуютÑÑ bit-banding, который реализован аппаратно. Это некоторые адреÑÑа, которые могут переключать отдельные биты через приÑваивание (Ñродни BSRR у GPIO, только Ð´Ð»Ñ Ð²Ñей периферии). ÐŸÐ»ÑŽÑ ÐµÑ‰Ðµ HAL дополнительно проверÑет реально ли выÑтавилиÑÑŒ Ñти биты в региÑтрах, поÑтому Ñ Ñтим надо что-то Ñделать. Т.к. региÑтры RCC не важны Ð´Ð»Ñ ÑимулÑции большинÑтва программ, можно проÑто убрать единÑтвенный вызов Ñтой функции в main, или Ñделать её dummy - в HAL-библиотеке.

    -

    ПоÑле Ð¿Ð¾Ñ€Ñ‚Ð¸Ñ€Ð¾Ð²Ð°Ð½Ð¸Ñ ÐºÐ¾Ð´Ð° надо Ñкомпилировать код МК и далее уже Ñмотреть по ошибкам, что надо иÑправлÑÑ‚ÑŒ.

    -

    -Как Ñкомпилировать код

    -

    Ð”Ð»Ñ ÐºÐ¾Ð¼Ð¿Ð¸Ð»Ñции кода необходимо открыть файл mexing.m. Это MATLAB-Ñкрипт, который запуÑкает Ñкрипт "[run_bat.mex](#оболочка-мк)" Ð´Ð»Ñ ÐºÐ¾Ð¼Ð¿Ð¸Ð»Ñции. Также Ñтот файл задает Ð²Ñ€ÐµÐ¼Ñ Ð´Ð¸Ñкретизации Ð´Ð»Ñ ÑимулÑции и дает возможноÑÑ‚ÑŒ компилÑции кода Ð´Ð»Ñ Ð¾Ñ‚Ð»Ð°Ð´ÐºÐ¸

    -

    -Как запуÑтить отладку

    -

    Ð”Ð»Ñ Ð¾Ñ‚Ð»Ð°Ð´ÐºÐ¸ ÑимулÑции необходимо припиÑать в mexing.m в вызове "run_mex.bat" Ñлово debug, тогда код ÑкомпилируетÑÑ Ð´Ð»Ñ Ð´ÐµÐ±Ð°Ð³Ð°. ПоÑле Ñтого необходимо открыть любой(?) редактор кода, например Visual Studio. Открыть папку проекта (там должны быть вÑе иÑходники программы и ÑмулÑтора). И подключитьÑÑ Ðº MATLAB.exe.

    -

    Теперь можно поÑтавить точку в иÑходном коде ÑмулÑтора или программы МК и запуÑтить ÑимулÑцию. Когда MATLAB дойдет до Ñтого меÑта, ÑимулÑÑ†Ð¸Ñ Ð¾ÑтановитьÑÑ Ð¸ в Visual Studio можно будет поÑмотреть вÑе переменные, пройти код по Ñтрокам и в общем делать вÑÑ‘ то, что можно делать в режиме отладки. Ðо отладка рабоатет только один раз. При повторном запуÑке ÑимулÑции оÑтановки не произойдет. ПоÑтому перед каждой отладкой надо перекомпилировать код.

    -

    -Ошибки

    -

    -Ошибки при компилÑции

    -

    Самые раÑпроÑтраненые ошибки компилÑтора при портировании нового кода - Ñто ошибки переопределениÑ. СвÑзаны Ñ weak-фукнциÑми. Ð’ MSVC их нет как таковых. ПоÑтому необходимо закомментировать вÑе weak-функции в HAL или пользовательÑком коде, чтобы на веÑÑŒ код было только одно определение функции.

    -

    -Ошибки при ÑимулÑции

    -

    Обычно Ñто иÑÐºÐ»ÑŽÑ‡ÐµÐ½Ð¸Ñ Ð¿Ñ€Ð¸ чтении по недоÑтупному адреÑу. СвÑзано Ñ Ñ€Ð°Ð·Ð½Ñ‹Ð¼ адреÑным проÑтранÑтвом МК и ПК. ПоÑтому надо выÑÑнить на какой Ñтроке произошло иÑключение. И Ñмотреть по какому адреÑу произошла попытка Ñ‡Ñ‚ÐµÐ½Ð¸Ñ Ð¸ по какому адреÑу надо на Ñамом деле Ñчитывать. И поÑле Ñтого Ñкорректировать код так, чтобы Ð°Ð´Ñ€ÐµÑ Ð±Ñ€Ð°Ð»ÑÑ ÐºÐ¾Ñ€Ñ€ÐµÐºÑ‚Ð½Ñ‹Ð¹.

    -

    Из общих решений - Ñто может быть при попытки Ñ‡Ñ‚ÐµÐ½Ð¸Ñ Ð¿Ð¾ "ÑкзотичеÑким" адреÑам (bit-banding), Ð´Ð»Ñ ÐºÐ¾Ñ‚Ð¾Ñ€Ñ‹Ñ… не определено адреÑное проÑтранÑтво в ÑимулÑции.

    -
    -
    - -
    -Generated by doxygen 1.10.0 -
    - - diff --git a/DOCS/html/menudata.js b/DOCS/html/menudata.js index b1d9f54..2e4a085 100644 --- a/DOCS/html/menudata.js +++ b/DOCS/html/menudata.js @@ -24,64 +24,35 @@ */ var menudata={children:[ {text:"Main Page",url:"index.html"}, -{text:"Related Pages",url:"pages.html"}, {text:"Topics",url:"topics.html"}, {text:"Data Structures",url:"annotated.html",children:[ {text:"Data Structures",url:"annotated.html"}, {text:"Data Structure Index",url:"classes.html"}, {text:"Data Fields",url:"functions.html",children:[ {text:"All",url:"functions.html",children:[ -{text:"_",url:"functions.html#index__5F"}, -{text:"a",url:"functions_a.html#index_a"}, -{text:"b",url:"functions_b.html#index_b"}, -{text:"c",url:"functions_c.html#index_c"}, -{text:"d",url:"functions_d.html#index_d"}, -{text:"e",url:"functions_e.html#index_e"}, -{text:"f",url:"functions_f.html#index_f"}, -{text:"g",url:"functions_g.html#index_g"}, -{text:"h",url:"functions_h.html#index_h"}, -{text:"i",url:"functions_i.html#index_i"}, -{text:"j",url:"functions_j.html#index_j"}, -{text:"k",url:"functions_k.html#index_k"}, -{text:"l",url:"functions_l.html#index_l"}, -{text:"m",url:"functions_m.html#index_m"}, -{text:"n",url:"functions_n.html#index_n"}, -{text:"o",url:"functions_o.html#index_o"}, -{text:"p",url:"functions_p.html#index_p"}, -{text:"q",url:"functions_q.html#index_q"}, -{text:"r",url:"functions_r.html#index_r"}, -{text:"s",url:"functions_s.html#index_s"}, -{text:"t",url:"functions_t.html#index_t"}, -{text:"u",url:"functions_u.html#index_u"}, -{text:"v",url:"functions_v.html#index_v"}, -{text:"w",url:"functions_w.html#index_w"}, -{text:"z",url:"functions_z.html#index_z"}]}, +{text:"b",url:"functions.html#index_b"}, +{text:"c",url:"functions.html#index_c"}, +{text:"d",url:"functions.html#index_d"}, +{text:"f",url:"functions.html#index_f"}, +{text:"h",url:"functions.html#index_h"}, +{text:"i",url:"functions.html#index_i"}, +{text:"o",url:"functions.html#index_o"}, +{text:"p",url:"functions.html#index_p"}, +{text:"r",url:"functions.html#index_r"}, +{text:"s",url:"functions.html#index_s"}, +{text:"t",url:"functions.html#index_t"}]}, {text:"Variables",url:"functions_vars.html",children:[ -{text:"_",url:"functions_vars.html#index__5F"}, -{text:"a",url:"functions_vars_a.html#index_a"}, -{text:"b",url:"functions_vars_b.html#index_b"}, -{text:"c",url:"functions_vars_c.html#index_c"}, -{text:"d",url:"functions_vars_d.html#index_d"}, -{text:"e",url:"functions_vars_e.html#index_e"}, -{text:"f",url:"functions_vars_f.html#index_f"}, -{text:"g",url:"functions_vars_g.html#index_g"}, -{text:"h",url:"functions_vars_h.html#index_h"}, -{text:"i",url:"functions_vars_i.html#index_i"}, -{text:"j",url:"functions_vars_j.html#index_j"}, -{text:"k",url:"functions_vars_k.html#index_k"}, -{text:"l",url:"functions_vars_l.html#index_l"}, -{text:"m",url:"functions_vars_m.html#index_m"}, -{text:"n",url:"functions_vars_n.html#index_n"}, -{text:"o",url:"functions_vars_o.html#index_o"}, -{text:"p",url:"functions_vars_p.html#index_p"}, -{text:"q",url:"functions_vars_q.html#index_q"}, -{text:"r",url:"functions_vars_r.html#index_r"}, -{text:"s",url:"functions_vars_s.html#index_s"}, -{text:"t",url:"functions_vars_t.html#index_t"}, -{text:"u",url:"functions_vars_u.html#index_u"}, -{text:"v",url:"functions_vars_v.html#index_v"}, -{text:"w",url:"functions_vars_w.html#index_w"}, -{text:"z",url:"functions_vars_z.html#index_z"}]}]}]}, +{text:"b",url:"functions_vars.html#index_b"}, +{text:"c",url:"functions_vars.html#index_c"}, +{text:"d",url:"functions_vars.html#index_d"}, +{text:"f",url:"functions_vars.html#index_f"}, +{text:"h",url:"functions_vars.html#index_h"}, +{text:"i",url:"functions_vars.html#index_i"}, +{text:"o",url:"functions_vars.html#index_o"}, +{text:"p",url:"functions_vars.html#index_p"}, +{text:"r",url:"functions_vars.html#index_r"}, +{text:"s",url:"functions_vars.html#index_s"}, +{text:"t",url:"functions_vars.html#index_t"}]}]}]}, {text:"Files",url:"files.html",children:[ {text:"File List",url:"files.html"}, {text:"Globals",url:"globals.html",children:[ @@ -96,7 +67,6 @@ var menudata={children:[ {text:"g",url:"globals_g.html#index_g"}, {text:"h",url:"globals_h.html#index_h"}, {text:"i",url:"globals_i.html#index_i"}, -{text:"l",url:"globals_l.html#index_l"}, {text:"m",url:"globals_m.html#index_m"}, {text:"n",url:"globals_n.html#index_n"}, {text:"o",url:"globals_o.html#index_o"}, @@ -105,16 +75,13 @@ var menudata={children:[ {text:"s",url:"globals_s.html#index_s"}, {text:"t",url:"globals_t.html#index_t"}, {text:"u",url:"globals_u.html#index_u"}, -{text:"w",url:"globals_w.html#index_w"}, -{text:"x",url:"globals_x.html#index_x"}]}, +{text:"w",url:"globals_w.html#index_w"}]}, {text:"Functions",url:"globals_func.html",children:[ -{text:"_",url:"globals_func.html#index__5F"}, {text:"c",url:"globals_func.html#index_c"}, {text:"d",url:"globals_func.html#index_d"}, {text:"g",url:"globals_func.html#index_g"}, {text:"i",url:"globals_func.html#index_i"}, {text:"m",url:"globals_func.html#index_m"}, -{text:"n",url:"globals_func.html#index_n"}, {text:"o",url:"globals_func.html#index_o"}, {text:"s",url:"globals_func.html#index_s"}, {text:"t",url:"globals_func.html#index_t"}, @@ -135,48 +102,21 @@ var menudata={children:[ {text:"t",url:"globals_vars.html#index_t"}, {text:"u",url:"globals_vars.html#index_u"}, {text:"w",url:"globals_vars.html#index_w"}]}, -{text:"Typedefs",url:"globals_type.html",children:[ -{text:"h",url:"globals_type.html#index_h"}, -{text:"i",url:"globals_type.html#index_i"}, -{text:"m",url:"globals_type.html#index_m"}, -{text:"u",url:"globals_type.html#index_u"}]}, -{text:"Enumerations",url:"globals_enum.html"}, -{text:"Enumerator",url:"globals_eval.html",children:[ -{text:"a",url:"globals_eval.html#index_a"}, -{text:"b",url:"globals_eval.html#index_b"}, -{text:"c",url:"globals_eval.html#index_c"}, -{text:"d",url:"globals_eval.html#index_d"}, -{text:"e",url:"globals_eval.html#index_e"}, -{text:"f",url:"globals_eval.html#index_f"}, -{text:"i",url:"globals_eval.html#index_i"}, -{text:"m",url:"globals_eval.html#index_m"}, -{text:"n",url:"globals_eval.html#index_n"}, -{text:"o",url:"globals_eval.html#index_o"}, -{text:"p",url:"globals_eval.html#index_p"}, -{text:"r",url:"globals_eval.html#index_r"}, -{text:"s",url:"globals_eval.html#index_s"}, -{text:"t",url:"globals_eval.html#index_t"}, -{text:"u",url:"globals_eval.html#index_u"}, -{text:"w",url:"globals_eval.html#index_w"}]}, +{text:"Typedefs",url:"globals_type.html"}, {text:"Macros",url:"globals_defs.html",children:[ {text:"_",url:"globals_defs.html#index__5F"}, -{text:"a",url:"globals_defs_a.html#index_a"}, -{text:"b",url:"globals_defs_b.html#index_b"}, -{text:"c",url:"globals_defs_c.html#index_c"}, -{text:"d",url:"globals_defs_d.html#index_d"}, -{text:"e",url:"globals_defs_e.html#index_e"}, -{text:"f",url:"globals_defs_f.html#index_f"}, -{text:"g",url:"globals_defs_g.html#index_g"}, -{text:"h",url:"globals_defs_h.html#index_h"}, -{text:"i",url:"globals_defs_i.html#index_i"}, -{text:"l",url:"globals_defs_l.html#index_l"}, -{text:"m",url:"globals_defs_m.html#index_m"}, -{text:"n",url:"globals_defs_n.html#index_n"}, -{text:"o",url:"globals_defs_o.html#index_o"}, -{text:"p",url:"globals_defs_p.html#index_p"}, -{text:"r",url:"globals_defs_r.html#index_r"}, -{text:"s",url:"globals_defs_s.html#index_s"}, -{text:"t",url:"globals_defs_t.html#index_t"}, -{text:"u",url:"globals_defs_u.html#index_u"}, -{text:"w",url:"globals_defs_w.html#index_w"}, -{text:"x",url:"globals_defs_x.html#index_x"}]}]}]}]} +{text:"a",url:"globals_defs.html#index_a"}, +{text:"b",url:"globals_defs.html#index_b"}, +{text:"c",url:"globals_defs.html#index_c"}, +{text:"d",url:"globals_defs.html#index_d"}, +{text:"f",url:"globals_defs.html#index_f"}, +{text:"h",url:"globals_defs.html#index_h"}, +{text:"i",url:"globals_defs.html#index_i"}, +{text:"m",url:"globals_defs.html#index_m"}, +{text:"n",url:"globals_defs.html#index_n"}, +{text:"o",url:"globals_defs.html#index_o"}, +{text:"p",url:"globals_defs.html#index_p"}, +{text:"s",url:"globals_defs.html#index_s"}, +{text:"t",url:"globals_defs.html#index_t"}, +{text:"u",url:"globals_defs.html#index_u"}, +{text:"w",url:"globals_defs.html#index_w"}]}]}]}]} diff --git a/DOCS/html/mexing_8m.html b/DOCS/html/mexing_8m.html index a9ba67c..392234d 100644 --- a/DOCS/html/mexing_8m.html +++ b/DOCS/html/mexing_8m.html @@ -14,6 +14,7 @@ + @@ -77,6 +78,8 @@ $(function() {
    F:/Work/Projects/MATLAB/matlab_stm_emulate/mexing.m File Reference
    + +

    Go to the source code of this file.

    @@ -148,6 +151,8 @@ Variables

    Functions

    +

    Definition at line 6 of file mexing.m.

    +
    BAWY1H@JrM#RH>! z3uKu0ANWTvt#45*u`|4wky7F1`!B$IN2Ns7&h*+W9{~0er?rno*^#vcs7aBjt92`y zVbTzPFhj-9j&D5!KhzxQJ!=}3~go;A5%d7$J zk;DJteKy+p4e|}bZq}@>b&i6~lcp4Brx%$ajlnZ@TMv1=lC zC;ZRxbf@&#e8zu0qZrV^73S&#KOlXlk(q(>y?7G?dG?g&Q zsb41)RF!p_-%N!sbbWt;kW7PLPIUVC-km@#K+HgZQM2?+01;o|$$lJa+9hLX`0-m` zOhuZymd3VH$p)Xd>Rei#B7l*H?eZcdAtw4L!00dKUUj+>$(nd~Y$0mRwG((I%YmQ3faNq#bYndCk< zD^g-n6(|@!LQ63zm3N@oVcmI$tk%p7*%g@uVLgFO{?)J7pO(f2HK^Z2V%bzPL)x7h z6I$E!sQlHhEda!R_$a2c7rX4X;1dkD!xJ3BjPp$e)8r^34Xtycj^k&C0T?j3Vm>a&8WiCw?S8sx^dVxgQ`W5Errfm{jH zg2?PFU^O>B{jc0+8vGrqcR_I0wUv#?J!m3r7jO*9 zVf(teocv$203bujnRUrC#yMsc@<$bbtc# zu{yQZ1F~s`{P06?{a~VjYvB5iWK!NJg5k+#>qrTRn4JVoNf(EB?Z`#qsHRRMs1JZ= z{$fq`AUj4~?&lk4ArCwj!0S&q#k#%7FT*u~Cztua3 zSRd;B?z=Du7zp7g8nM`MROp{4B^qvpOvfMorK-mCC-!aO&RfR!_F6V}}1Zx7T7 z-N?3L2ceXxyyQHiw$M0i^4D{WQf#}0uMVgsbL@HGpykO+f3S}xU?X~~a)c-<9~q;t z?FAfEC5c(v!vQE2E+Sn%T1ijh6Di!_RiDNF@BJZdjvsg*%(772vLUK5)VOd*8t?{} z+3yUhO6lv5{Es^F>O%|f1%$kWOF+e6`F#Va>Y(`{FM&SkLw4ueFW>cAzV>Ppn6Wl<&Ez9^_H1Qgvz;newG=0x?u1r`Dp{f(<D5Hxq!I%&kNp6afmB4{ zMRJ1ro?Q{YP8-wqZPIOj>(?sn<*uoiwyAB_mBUe{RIF>~_U(3mTv)bKF+qN8hx(Mu z2`ODPI;8K!qYgB~Nw!{19VL{McYW-(U@{lh^945iX#ld338+?sfS)sHL*4ynK%oni zawY$No%mQzKn;jgubq(SSF-gKXKCaFkba1`iU}aAH_(B?GW1rTI&Er7Rt{O!qikmP z_y09kCJk{O=Jm44rxz{{gmFl-wyL;^&(ryxcG4PR0M(i#ovnG~tHcL0~PNU(KePNX$Bcm$)z734W)WE?{4W@jb)(mn;@A1eL zpsB(-C9?zm^4V?B%`XAq~;+vc^7rNr=Rm3cl1ba2BSE5>crb z^+oMyDb77*oa?R`z$pw*J6BA&?XlP6jXEKqX4IK{G89zs2qVpBxAXgLU5wuamblEhOeh5atUx_9Q94z@fAj|ue zUVjRg?e-f`5<0L4Wh4@)o#P^)`PF}tbA-wI;$l~jd5EeZNJzN`=e@!8kfNhxfCV#L z(3|zBEW3JrHcPN6mEL~qK@I6QrUD=!@rsV7RbV@gqKEuelkLjn6r`=9`YeFN)%Jh^ zDkCUBn#=i47Rjc&>eSU$m^wUZ6)I1;3-59A_AVj7b1Tg5Nv~Q_-WC>Z^`A-F>O+Xr zvlrOD7W5N}7xeGL>rH(~)LiGLSo%QB`D&obOJDk<+gnvEG^=WB?|Z@y zx^A>q7bFtDne?F8bi$0!0@m;T_HQhc7FrIVO*oxlvWTDz3YlctSNz_oj~N7n6q+tt z>hmlsNrnciCYk95PYI9et&p*j?s{a=^!Oxd0PoMQ!i^!=kDmlr!98B)_)m)-1T5&O z<=Gg!H7DQm1?ZEsyLN))L4?O_VOOPk$n$j3c$r?kw9dfyxpzl5cCM3zLoCLZRFSlQuUCE0(d2wgSLjzUKlGHlmYz=KWDu%&%CNZ(_m|*4+g< zumgOry5lr(bq8j%wza$TJ6<^1;K$8tY!D$~zYCbFS<@NjsK?GB*s%QI^u%7@EJ@ z)(8-f;)gGY)ThjxbK&39|=tTixNmX+ICpp^K5Z4+!gc?BWy9LakeHW7vtP@!n<{&SA)(StauHN zgQDh%xB-KQoWLfNF91#xLio3IE*uFg00;A4E3|>ddjnL)>~d!#tW;0yeI*Fksl5%d zN-i%fI@8Casby7s_GB(VC_xwNEI#WcsDGq7VkZJw1{hW4=vU%#c>%MFWyiF8A;or1 z3PIK9p#XwSXnYi<3n~WTe~v(F!BO@1hV-Ml15sFmMCf~Plx}(L$qBDwrG-$$Lo~a; zG7lM&mMulTl@?@;%I~TA6pRSMWVwX4`%{N()GIE!Ao`MWUJqu=m5>+9Jk3UfDpcIFBZ;QSg7gd>tuM~r(#l`f}_QS($^dP zm)}*I8lQ~BaTVo=-jM_k(0iB?@CqjR{08p4ruJo)a+W+2QDAr4H*vU1?5dR)$>Yf+Q z*`DcA>s=vMp#_j^qKbrLExcwuy=m9&D4B3d@_OfT~(qLrJLb_5sEp`nXf(J zdc}|AgT#Qfv~_;KTxK_X(y}X?%J(jT6?>|9QmeHv$O(vdPE&KX574-6tpx^qp7#S~ zN9-t-fUdM4WE5GUWwM9!Eqclj)>E&dzj2GbqllX~r$s?_7U~3WMo4^J;M4_G?^)5% zZ#=CCj4aTzPSf|3nl;QI-w*aqB_|3Fr$TEumLon}cCsoRe@ITSTC7db{O!{j2x=?Z zY7;EEJ`Qx=Zuuhx2Xo7KlN{5ygW+7zadol;Ja{vLzS-`rmLjhIZ)JS4@ZispK$M;q zIO8|wlOC+X#$j)X|B)7cTfDV1SyhaXB(?k$66!og#$V@O*3RE@uG#!iGiT{$EDn%3 zAD&as)%lSjA}5%V>7(o}-~1E=nU!CHw0sab?hdT0!>{T?;jQjnrkBbvX*OFqJ54`np-t&SYM4|H~)e z)8dau`xFnFS2%s@fjJcX8Cr6GhfM2%tD<3|r^iypwRF+~#tIQ11o3AASKWrsL>5+7 zE#C2VfYog=%{l_U)b<>}7zW}?e_BFq9ir`W-a+&YQ^c(UtCeqpZt`Q?5x9VYx*DCs zUms(`Dsb6A5f|cGS0tI&S0ytNs4q0Rf|o2E{ZiUrIP6*fqs4ijHI3xNpXBN5o6?l} znIu=*?0XBMq#<76B@FC22H`j9*(=bvlb(`?MZOwB8E3J95$CX@I8 zPP_qCBEFpL8D(`+dhmAM>DpLZEl_`7y$poDVm>0=K7sNOJh1{QEg^+7fv)qbBvgL2 zV?X@!@vu^61nBLY_)6OmM^>8s$>9{6vYT<$rQk-yHUARh;_fkARr^gbYcnb7Dq5Yv z+-8oIBQFvwEKB{ydmf~~U=@>z&}6&q%AjSR@#l{)fa5L7Yc-qYFcyP%!)K-TCQZCDOitFZYQiBtqN zjZ(c)&mlLMGzXJP<&YyJ8KVU1>$Y~Ym0=!0O?#69I`i*j`rSgHHcWi|p zkb?J54~bb1qE4yQP`r}FFCx!lZEC+U>Z}e)@R0wO&YKw%Gc8Wkaj_6h!ft-4S0Mr{ zqJ(qX)a6Dm4w&57x%syBcUUj`zB$|JkT(uZ9L{OW%9jE;D-sg|5}@!s*oY(l(KM?$ z{9{YA&2@^DoLxav%1H~xXeC(9v}^T^zRk>7@;h1fz)}vfD#zu|CsTO|TM_h>kHo`Y z*&h1AkivZqVR<`D0m3zdawNshT7PY5$RtokBpW!<6QBjeVoV(!+0+ki6eK7B9L{uq zx{(5`P{t5L%D7!7-1Mrd^4aEy;$~WOrGYsriHRa6g+z(77d3Hp^|hlrP{MM2_B$49 z4k_j+yOn))8>COF)vcb}G&;o7UQ{X_s6pm$%H+hRpLE`Y^s&MREljBG7$2k>oD-k- zV_W)Xy58PPAJ`rLqcNwWx{bcEan=1Znn8mHOCeivV;%B7R7NL1XV@&^o)`ihg8F28 z)SPONdaov;wPLIE*@`|oEDGfZ^|f$= zAD*{6f$1r6@~Zg4A69NM#RpV!(k}aQ?wKGL1nl{8f_qE()yjuXn1(gT`&Vbsx4~MOWR|TPxWO5a z>>_KGWUoFg7IjSfSw#YpX-jm5joT4FY7_OwvSpQndM02oLrVZR#th`~(pevUN>zuQ zL*gcs&2#v)mb3h<)GL&ONF~jp6JFs=3V;s0Spbrs5RGuv2I=E3t;FapniWUcj(Op4 z2YW9@Z+`9F+BQKuRp~TaSCTTF2r>61cIt$l;7iDr;x-`|<&@GTF5PeHv8flu9;~QO zw)-E6ws~qIk4#p4J(v0gcvSC*fHu5%BMvkZkGKS?z=MTKr(%A_2Q7;?7 zYSZ}G`N1pu>FMG=B^6N{aDAGGkLSGcg}{K>4jgf;DsA_%N%iI?hh5%eT&3rU#^ePK z`I?|#TWwn^kID@0K_bEVSV%VNgk9ITTtlL8f^%Ctb7qVwU3N8TxaCOtmGQ^@2uAs( zmh(2U&xYdd^_Q22Bom=ox`RE?*m^V=mVN(r1+o|yAxkeYgxVe@u}6k2t1PEx3gX_Q2q z6I@1$U2&MUx(b+eKm=*m1^lW42=lMm97r}zkQF+qcgqKS6I--Ds~yT}di>6o@j;?& zEBauEGNi%OJNxNmGQ}H+)0~AcY7{k8A5_AZ`Lh#M9j95+N&Ju|T~nphYj!45vl5>p zwkp91*vtHnbiUXg-88QVM00rLs|OyNa-1Eu1x7h zvz~5#CYclH!dL*4uw%jG(m_0gAGrYMTPKPRPaS10K_N+CPrEu!8C*Z54YeWrDn`jwM-{A)c$eM=w%vKzIFSo|I88Fz+?AEe^NG z-{e!it?O3&x#j?vu;LZ+w!Q-)3?x-@K~w#oQUz(DF5P2q6%ytMOLNsJlq|5pua>Mn zu|Ao@&lPeU!N|768{D1|A$jPalXsabDt~C;n)u16jBvax9#{TEAY| zd7;pYuQoDJMHmM*e0k6+zmWIuVjP?oHUa zbwji2KOU#x`gF%2`1sts04DNIG4uk>o#x1hC7I`!Jg1hA=N_N{ejFIBAUj z)O2+jKBYw%6=99mYaRjLDrDq*}T0vS*eAe7C(CO0a|ToBbHktvExCZ!u!vj0J=8=GVu+^ z0hp>n{17mvH-0*%_xi>yK~115Er&hER2j5)d40e62$-Mnu(58pw3fCP0^167-D`|U znx8E_Oj*@Wglwoll$8=WT!EpZIK**UD{OULA;_1jZ)jv?HI3|_bgYhkX`A7NflK*# zElOI53Qd`$*ftxQksEdU%Di9qSjvuzjpnMhp%XBlD;y%@uj@$7<|J9y51dx3hVaS5kk1YTr|qq4{tP5XALy zpl6b~VDc6PFh|$(Qfz}TM~1&FzkUHqMkHz#m>HSPt(dWqnvHr-c1|O46Tk@4$0phZ zeUr(hX)QgN5#HC4d_Q69G2da}%4t!lTaykgLo zf?Og!)G;*S!Gbbqp>BQ#bnye{@bWv)Bt6#Nsxo1GoBv@ZhhTB;M%KaGIkLZg+U5mt z(t+G^qGu?Y_M%ibFc+RkJ?scj(`k(jdEm{!7QinC$WezvKsWDZo<+oj?q*^X# zUFB6#!Nf_oKIgzm9|_ss`6w-9^29bDM0b{6@ZyF0n%nw!oK{L83mN~lmdcwzVY&WyA`JbpT>G4L?ayF{_w4G6K2Wh2xc?KeDvtwt#dyd$2@W#{~gUK!L65Z&kgd0G2&BH`bu$dRgF?r+~m2?sb6ikbjQ41#{F7LoJQu; zH+W2HdIbFS=YP#9HHOfwx^Fv%jpH~shaqic#*w(MRyLiS4Jbcbm4(4-zGqr2{zfc+ zaCc^|$}wDExIn_ibILf-aL5_nK(;(T33{fK{>yLT77sUfm4T*9;)Ow(nN>d)nr+GH zjUzWa;mR~#=ZLbr^{c@2+2z{s4--vn!AhgHbz{NACS;4cq4K>xbyr6=#)cP2&TP5g zU!D}drrpf@B0r%KZgx?XcEw<+S0P1sE{I`|M?UKDXlQcX)GJ%~uf{N);Aai??O*yT z-hEpW=`@a71>_h1zNPRIvgO!5YnEY9)Z)pg_BH?3uS)gkt|{RuJ9xM{wk&*YblW3qO$VO-ELA=JiA?;RK>ag+t`%^i9pvIS5QDo_ zm{rXOygtIhZ|}X?pluAa{wLz@{PnN?blBR6CS~?uTW;e(`h$ZBE0;_0OR6p5H-eQE zI1Zum1;jDAX{F*R5#dh(9foJk&jx#uda$#Lo!F-Zh7(S~$N0GJ7o#W`!p)ve;kkmt zN{(COtb5Jhz+%DU3JL6u%l7&P)A}GM5 zXs$SZj?b5~od3Aqxun$fgE0ozkt!BzwrD^H31b%tyTGO8DkRUzumn;WH8){o82|83 z#hW)jG^zUPSD0D;y7hI%H7vKem${uiNxKXb)zJ6r)p1a!)pE7;+w*g5>Dy}g^H*eF zwLQ#A{3~{|s?6A7M7YSQ!%&9huVbeVaq*pAtC*Cg(uA^$wO2+apIn{39neJA;OAKP zQ;3~}OmSGV4?V;Usk8|9#{LX!qjAP7N`F>wj>f&yJLMS%xMrxe#uXcIg^9F5J zbhg+Kx|6)zyNlhF;~-RcG3@%?3rY{Ib3-iVkA0!&0-)dU@Ba&ctMM+oAR1UwLwK2Q zFhlbXA#y;TMfc$3r}QP7YMKNmrT7h&0#0QPK!9behE-{fm+T)rxQ&SE;tupW-0msO z7+0B0;dtl8+T$@+8cS%~(^#U%DLExRRD8FAg zrL8S`Ohh3T)&uB|Ush7IUrNSuZq_RVv7$*=3}YX7Op$iLikfi~0cjbc=yu)N{3A^84A~Mci!0#`X@Bs| zx11U)$d}>+=3mjox66}|JkObbJ&JXBzj3GS+=^0dh%_T5Xm)H+VTSXZ&%No0otjaL z%lZ*}9}Gi>c4^us&sNY6JK3JBcZUfCoY>1R(f-BNTxPa2V{z8W-XU}1Q9&St3E6$r zeqkeM5uRBN_v}!a%=FE4x>WoyP<*52??2LVu75pOlw<6v&{Wiyo}sPx!z$Q){meSa zLBy#}LaUXp>-L+-(xt&133dwQeBVUnT&H@@lFsX$vxn9))=E4XmrI?o4`g_!)4^ua zGWB__zMN#>VOc7fB_I$vaM$Tm%LV#;E^h9<&!0t2+{8JykpQFcl!$r8?U|M-da0^Y^6r%CYNA_J;oQKXR?L~KCHrj zNAM^_^xNdqD)q&eB?muMkJUW4yp3GcGAF_!55>Ti^lUMHOKO=%Qbg!YhJBU$YP3(! zf06qGkBz{|H2%z|rjj062Ho#^SqiQ_F75A+`V?aS!fCq~LvGEAZ`r2lV8ia zYMx8J)ZHg857#Ye1 zbkeka96xmqcP5**$(zeU3vL9N|G=5^{yW{<`YSB(m!6M>il^Q@BaCuy+ERK> z9yshvn&8_xqp>o+jhVEtP_bB<$B<{!jhT$n^G2~6k__z%OwSY>g7UjeQSp6*Nc$Cc-1uGUDbKx4-3yQYYw|44FW)zFBe<^7^0p@7OU^tlIG^Rff#BL~cp}=Z z@y_+E@2!*FDv~Y7UBuI2F`t_G!sZJmVs53J$bFuQaL*;TO7)dUX zqJR#IbE{l7#-nF=6k6XWhKTD%kC!;TAAD|jJL|lXbDNBlDVE%3>g_o`1$NOtr2mor zQkrnq;Hlfq$8MbFhE{4z@wc?R=0KExl*4G}5dlJftAOT(V3TsdUeJ>MU> zhNTAc9xmB9%xw5;R*SjJHhQ_*;19j779tqeLFpOaOUSq5wP)Y|#`S(Br1ey2O~>mO zmQI^bA`2S2W7Amzo|5R6=y<{OS|6TB^9EgS%oOW1me)F~bw&#zEZ_Vjto-LyR|w=~7vO%))v>_7gQY!b z|Ey%p8f_N*#YsD|%BK46MpsO>{qt`(cW9eMb&=)!XN^-sGy*92m;bwL*CK|f`oJl0unFD479rtpyEg34bJH==mmT)m^a7XpzTWmnA z8>JA=1jXDAOd@1wuKCRFqvX0{P6(>>B;iFYb&_Np>@4t36s{Xx=C+(EN%`X`|B7J} zJ6#B6>je1`1H*xax?c7dmxmW(a~n7dNSGk!Ec&OtQJhzWW5HhK#V&Q?305iST|=UTwwPyCXn4EW&>%Kin{04`w!~>rW%Za<_;2I}lb+bMxoz z=0=v2?Z!uPHz!Doy7BC$i#p}ByV81Id4kH-g zjwk~#@1+}67jt;*JSb#rUn4m7oa-#&4t55?cV=Jj zYY;s*z!Jwk#_^;g&`Y z2X24}wVr(Y`~LJF?B|=)91I#1!0PWPcJ3w;%34f!$1(Af>0b16ZUKjhaYf$)eJM}E zRe6rW>Is%Gy=%pY{oDs^7Y-R-;N4D4J&GSloz{^t7RZw;@)_(9y2d+u;`sfS+MHe! z0Mp*8sMW*iO|UN8mV-Gz9tnq8O@HY8l#rgEZ{(Ci@nCHp zu(oVQf9GUORmHdS)86s8Ybuh;Gx4(`Ip<5d)Sr@3971d>k#I}}fwhN{w+5h-9gILXNSwOgR$bQS5P&vgghoF1fZu`(AM+axqY z%sc9RjGX0Vy4Z#39OdWBu-z{)EMB|&60n%Gq={6tL>p}zX_|@3u_a8e=y%#!A!b-i z*%k1y6}~uXEm2eauE2Ak&0LccAI}2$KYZ6MFTtoU%Sib&Ue0U?w5`xs)v-kG+(NnC zt}|ApT3C{TyEa+l6HJ$+a!BP2-^{cMMCj&@L4%ZiY_@j2hr(%tM*|cBY-_2m7OktK z;9?v4>cc^t%-N>o z+BrxmxJ*loxb=VW1?nJ5R7Gq~;jZ(`3LY`^OYuV=T7L{=u(?xJ28Q;c^33Z8JI^l9 z&Ja;Ji!)8hoosQ6tfZVrSHzrYBECkv!CJpO$xN$$`H0v`m@-PjYGwZqopxE zu(Ra~^*w6bvMYB{o-aq)R8%-t9q(jJ?Yyn|qyAtgGK_>{>_|)`y`K)2GEbx<@&<6f zCS4BbBed3y}yOk|iyRcj0AW?jajo zJ{&(F_yH{e@uf78($i@9JYeL5IQ4f%4WNg(!Yy~_s2Df44NRjtX%Yp#0Fu`LMjG9- z(*BE|)0KTQ`tSSu#5{MxMZ&8;hjU~&sC7{C4DoLVzeqO;qW5!Z_rB1ZJ5WSp{CZDg(SJR$XcKrPocjbk-4V*_2}(9$aPGh+8Kk+1KF z=u?_MX&xiK%-YS4foxD5)-p!ui8wp1oAon}ZykYx9|sCr7LVaz=HM4X@q6Wb5ukFB2o3tH<<7bFu5!`c^G>cgLFZ~bGY z_iDUx#vo&%H<~_;JlhLcP>v6Hf+#tkS&j0pnF#%vYf8o$H)!Q`Dc+}e8AB_~g`>}F z?`m}r<7Pl%WrzWYIyf!(96aXgeyKiEa1YAp(B6pEk@1$Nu}nNdPjG%p(xADu zcym!RVq>SNPZM_?B$9{ia2HBG7gi-CF!6a*H!HaGmBgm*GXGy)UDm3uXG!;{3GcR% zF7cW^=UIVwe`v!&c(r`~swh|hcna9Sv~rb{TuSWg1;=yV^CHcBrv{@*97_!0oo9xz zQnv=V=$Jk^3(5m>-DCWtulAO8P=|qX$Zt{vbCN^$nIU4N$!U=Y$;msVZ6JIP+B0a7 z;k?vhMx+?@9>$qD)h-pN8%yIp9jscYGq+)6V-wC;Feb`K8Mq@Y8O7UW>hqTltw==b zN41)Yy46_NC;*1|^BiSoaIh9}n$pLkqH+5aVtP=P;*JMpU~+c>>T+_tRp}*Qc+Xx}J9$RL|t$&x#21NN&M-v%R`Z zFi5z?BOwAtW5Sg#bFH+r)z*eRTBp@narj2Pz9Is-t#*eFHv_L!S#{M*!tpg*31$s4 zI*Xf@f}H(Hu-XCFgxDNxIyb#&*%~RP9o?gNL%4*kutJSX{jyN|h!~DXM1IdyhP;wD z4K9jWB8%4l0j#9tG>nNMz6=CqVkH=Kch-yOBoGaC>gLIk?}z4W6%X~N`V zLNmGT5W`3upxjskcM%Julwkq$1835Hshp8w%mohDO?@ z1y7R8J^%!d@7_PGU5kypFpTIoW8yr|;`JkUL*l3mSIN#yrPQIjV!#+Du`dtskS`2fSc$bc%b>|9j9NXgYRgl3E zJa!!(Wqq>&&39JI&S$nufr--rCNA$kCOD#%U&M()!EWKV-v)Luad42bM1>W5a9%{; zC0QGGTagHnY4I;zG1oZ3&0*GvY^(0Yn9n2+RQI)_(RVevB-K9Yy)ze=I58#?cthvTiD5BznBqJJ`YYZ_sq(&><+14;U&<1( zQMgbG0IG%594mkIv?*nKVK-rWJk@n5hc92hZ@UuC__aD9Y3zvnwuqCq4QIY%pF&&i zVjGi*2NTBdAuEw;Zb{@Tch27HtLM}GvHi2GYig#LFo=CKnSPz%b0*6vWmirLhy)2~ z$-c}TBnh@l;}Jo52TrLzBv%3uJO(U`zs||o|8Q9%flWZ|vipi>Uo$*&<+5q{=0r(z zW+RzPk6-|gO4{7K%I)jp=n)LL^BIn4d9-TKmh_A1YRAoXj#ml&TKoYskE$DzQ6p&0 zCxCY;k^I!F`wDyRW@5w6?(;HMZ;5&Rq7^J;mAlKI6f4~C!SW2%%yz-lCz5C5VN4Yf zt=N*d)F1Xq+)0I3cedu+eYO916P*Rs?CVel@`yf-XBzEnzh1BSraTXDr8K&fZ8~qi zf75r~uvr9e390gmq>r_ZeY1cw2gl>FE9C8yxY9<;yJ9>5{>T9q0Xq2EkdFwJTf?lf0}O5LXar282>Q-@o!h@?N6iKIankQlnkPYYiah9w1ZO^Ky6 zCaal-erwT0^sM;O3e(Ycm{W&tn3h(8As5}TwI6}V;L`oJWxS%fIvWf#qb_Zu-c`~f zHY%bgXK8II;eJNDOx|VQe>|3+%pV}5=p%fN!(&!XYt?7;=_mI+tQE-J7#~`iGTLV@WY2Nkbk(5TI?%pA9;B2p7ELF#hHFVP*2H zt*)wdz?a6o2?bD3dlYnRjAZ!z>4TifRyP_Ybt&T=GBy2w4#vn3{|&4=X-rB0pIVsG zdr{Ne;p9Q}tUI&h7C@}Ta66L0RrqHBA&n%LDFGZQW%}l3T5-Wt+;v0V3_n_zGx@%S z%f>IM(fSEl-4FJ^irGHUHY*-+q!{^gyAbDlohT$yh;WGCi-(I>q&MEGR?70PS`neZ zu41BiSNiwsrouB(nLPy?5?232c1T5L(_1!1(fxvXGwi%y*yVa5*vGU>JAcP$se|v5 z^O_IzaUYph%^#X50nDs0oE7wfNB$w+#o!t>O1CKOe+S^z^Hm0QVtDnbujJ1j*fOL>MKKplAMLLK25uCOOUtw zC5K~hSVFY{-R?xqCwup6+_ONC(bds*UIiXIt{e^QH;#OaX8jRNb0;TB#{Pq6STBqP z?oj)sUrW7|4~ThKl8>0fx&lh<=iZxp8`ZMNPx5Xf@rRJ`L27%RGa}~F)HL2Z_LLv0 z;2v4wnW4QJp>lm!JNH)2mKeTwrl*q7-^|pu(T0f$Mdw4FB-40k0U{`WYgL3Sap7}A zN!C169wa;jm$hPmM{VP684UxVfzxKzyp?Ld zOfo+-SDyvk2QCe=m}Kdt!F%QtD?%T$d*2CG-wG`ZpXZu130zLQdTuJVIIg>tvq5>R z`P<(BXX?J9$EHHzy_m7D!GPw{!q&|8sZ$p_L#MjBUJ5*?$fp)O zt4q{`^Fit2!-Mt*Li&nU80I4P5tGc=JB~RD>*?T+t{>lC0s~wkwg>n2yL{(kMN~ao zDY9ZC3oI)6Z`oZDeg4|v2J?Ew2a7MttkTt#BnN%S6_!<|H)LMiHBL%dE4So&1SnAi z5AQDDe$GLop*(fzOl9((^#`^B9Sk2$x^EoV`V6(l^2|lo0Y1p1%_NVm_dScZ9I1lm zogGnc!l>QXW6tf}?-tCAIcIo1S^}bR_S3(+IgvA&s}Z`ghnViDPC{-8o`{4Wa4Y!dxyNI98-8WCq7z^-+n<6Q)2!)BNr+*gWY0Cf#45Hizrh}n5VQ;;Lr6o_h@n=utb2I=kH5KL(26!0P z)migdw3X3)#jHAysYP+hL&@OLfe-kEca3@Ly58kbuwTsDG46`Ut(1QVq9gX$r1!^r zu}n<_1WxdFoz1~m?m-6iR+wl&({QK&H&D2>3->8WyMIktV-QGllirLSU|x#Zf+n;o z!;4%Qc;drn(|>OiHy&usQo1*3q`>K0Ns`2_ArDpyWZMn^%0F>6yvP{!;9M*gd;V|X za&}l0XV2sXa#q5rYvL=$z$os2Z>QB>((g$dO7$Rr08}}`MSbk^$)9kEz|>*sg8W8& z$g(vYBoJM>sk?!XtEB2KLW5K>C0YV;2+}%#m}^;6`6z_x(hx@I=tQ^#RAC~XO-H?A ziVuU&c*^nW#G*|H0Isb^H}I)71EAkA2Zxy?SZE!WTnB34N9yN*;SXdasqcCZy(8j>*7I|2J%Hs0dAIsy_!Rg4fC16; zf&`2%$-D#SKcjYh0@uIOBI?LoYrgK(^+H1x;}J$lh``fFAF7^?3A)_h$0{FrXCV?H zxam(nU^mRS$UXc!69Ztfe zBXXYiu&9gK?HA+WH4CnQW4+$5a?vh%;Ieq*q)R69{6~dlpXJ2nkNXiN&fR|UoAsJ4pz{lCm5~0JN%th2d9KyOF(V)yZmxks?I>o44J`wOoMl$Ba5@~9mNi=A3uL%hi zlBqjyP@ZHq97%@zQGcl7?xazZ`13zA)`T*pElvRv)b4hC@OjZ-&~Uml$C6=M;4@Sf zBc2F1R&Z+?ria9@SQx58J)Skvk zv^^9`aaQL^gf)=5jfDo2w z0z#UuUx z00wP*op&Eeu!QAYx{+z6(?OG{D2R!897O z9#)V|OK`yk$D!phqqlWYs8Vz*V`p=Bch9u7T#R~79t}AZZn{Tx!Efg$xckQDQ)A}j z*Rl41>>@W@&(E+|QHhpzH&7t7boW?yR{U{2llAI{Ed?Y34n@xzAU6G)t6knU2~! z$xJR4$-e~0`}`tZy2!*LKRLd#FlkaOx%X*lc&oH=ci%44l@Lue;NeFO`SNRn93Q(Z z$q9IinU2b0A7fqEf;lu&=XQQ0s2|^LqDsPPq7r%X*F#zti50UkSX zYl0!2i@UoHKjGto?=3AY>BjDWe)!z~5P033(qL0pnz(IsmFV&;L(F}VC(1-_N6>TV zCBD;)b>7=&UeS2&y}@R-UZc6Mi}h;?S9VyW1R6+I2>)jLPKlcJSx4tsHTewI+%8k-rMaj|R}&TI4&_haU&@5ZF@FmwcxfemY9nBYLw>Pb)*v zR$FlOQ8dBk)>gaP=6M*r)zF)iC-Iv*mN_92Br3w3SRd1FE+bIxjrhtZ;1 z5kD&r0~LJ=<$Zx2_`e(mb~B2f&N+);Iv!h{bAjfCuqUx6F>GxhxW8shx1Ua6H4NYb zE1aivD2g9M%qFH;4{CFGM2k8arC!mVEuTr<<`#Tu8eDc+G8ge%oarqxlJO;j&kX5~ zRtifQi1*2xKQzoHfRM(^W&dj0SenKg42IQmz8|RGnEN!EMpvo1q(wy@i3oVNh-89NGlvCgGt z4+<8```9ghzpgut8^~KIa{^u{s%<$WuoY1G(rw#(BaD4jXMiM#to(K=mWJmon7jtq z{~KIbC6>M4hQ;o9{qqQEIg7{tT%H4GG!asiHwvfU=n!yeVK_l}D;SK3N|$MQfP`9) z>XnK;lf&Yt^9ORe-QVunICw(X^OBrM;la{pX146yE`%3qbM-zm{7G-?5I z?4P2e)6QqWIOW)Xb|_EW>yEGktLExFFWltCzIeYios<7$aG_Sah|x%#e}Fimzu@Xk z3y-80Y6PqqTw8Y^4p;fl;4 ztg|?Z05KgjxtjX}^c#n=qKRiQ?|L?%)+=+#qA*_(vZSN0RGE%eM#yhB?p@#f*Z?K} zQ$y{)1|c2L3C;uC7oZn)sGl@9i+nVTdmpA;_n=mpG_OvMkG1Hfqetp4JmbCA->9iY zk)<%BSHl!ln#!^KR$uNXm=mq5`JKtDsSOIVJx=U?Uw1)tetu4x+p3fBvod+vct5R2 zbkW09FEJ5Z-wAzcaqhhnKVk`rA8|WBZ`-Qf>kychWOp@CaTA+dfhP8k6Q&Lbf5E(+D-Zn*ys)|Jf5{l-31})yDHr{oV zWwsbEd@Fv?K~nZn3YyWo;a8V+{kW`y?n1uN|3fwEaq{;xb&3e6#bD$9XTvAfZg1@h|X?}3CPp3fhezh}H~TzpG`{IEi{3E_5LF@ZuMHK1wT zO3v0d96`B#D7{kGp4v2(jb{82(()776-6zlY#nd>b4i6k)}kW5AOD> z@cu9?Cr#aOwwI!pVn7!CqYfGmj6_Pvp^OulU5Z5tSRh)jrbBx>FX`czs~Ok$Qjh{ix)noT8OJH_sKZ(45aBd7Amb2VT)pGy-0~3~OrnTj z;1r6f9|@~ZA3rX5TM1F((%)4Hqkz!zaZo6kq{aRfM?%Jng=oIG+LKx;5w$4nRSIYIi24$Tga=BY45;^%O zdWkx@g?-R9Eq2j8Z+uyN>o@w!P!_;)?}is1es6J6w@(Z`^vzkxPw*xK-s9H(;ByG> z@;KwJV1pbR){k38u^Cm#k1+(87>>?9uXBk+NhlKdt3mm7W~&ZMh+Y4l_9IPw^RlMeR|9Aiuy+^SM0x8) z{Ey4;mv3(WJL3D;s-M{+@M2XJXYCa9r%Gm7v&IZZp2m!-30?PMR%;SClRKlw9;rWf z5})my3vq#Kxy>f#cXJm+e^U^6LuJQTUGhAK*;97C zaMrGGc*(WviB&r9&;3Rhf&8#|L#Wmlc=GQQR2tx-%l>nvNLLUE7r9U)3{^pstU6^~ z`XJ%Q#EHJ?)r|t(Xj3*_clTxJ93C->_Hhq7ltvrKmMiJD>oRH_`%@1e9Rj(8&M? z-qXf3!)AdjmDDX)-aZb&1hd@K?FI$UvLtY{ZHw7TID^fD2zg{UJlRXaijD75uGA#P z`Rz>A+vU;3=(2P(zmiDek8!%8MqOsJ9MA|eFWo0q&0**u#@RCM&g)I40VR+O=(&$C z;(<~gAd254TMq-XHGSXsDrTCXU&_j6H?W<2Z#kCQChmufS$UQ?q?cXe1oiyd(@CBS1ihE2s^*C`^{X( zzVt!s>|MWffGHMP>YJCZH|uw;5O(^J>J;2Hk!UH zCaLlEGU%7@gG1=FfK-QcepHs3M10s|gisy?o~V4@+0(IQ!*c2sSJiCO#Y`N8Sz?M@ zm^J=yivR$F?l9JZyESSuA=w!t4ay49_f;xpIpI^XmFn;}@TBi)^vM{*!wf7AV2TmJ z_kf2P7!bT0%iO(a1<>vSPR;&(PeF4QXi0u;5`vP5>*%Q8!m4qHtJg)tB#ysV8Blr~ z*>0>-afydA2ct?m8on&th~Skx62K6ocP?mxuA)46{f4so6D7eF74K8ah{?zh4Og7A zLM#GCKX#0I432(siIvXcKD=wL=82=VE5bVY-(nUVYabWI%Mr z(pT02dOIj3t_5j)-5=|FZI#M=RK;>3q$7@M;^x~(D|jtx1xa;L2TgYB6qGq%-Mn9C zmv6Zr(bE)JHPB;MtFahHY`{ylFd`Di|Fb!=>NVm)NZ6rF^`sND;PRQ1y6@K$QMgb% z9ix#1*|%(goZTaD_eTPwykmA->=90I6|b}V|H71LyOCf4rM<@)Xwjpqe(TYj)S`65 zzWzz$A5&Q!8r!0zvz8U$CtgPR&4#m$Lqe*;>TA7eCQ`>wa-HRoD(9Cq-tZ2|OF2Qr zY)JgfnNu|@1L8*-J!bO0V&;*dEYX;}rzu|SsOs3G6u}6?S?%a-37O;#*xoXX0iIG5RA$aXtWE8)d*G(DID@fh$w`D zvxt!v^|LHG;q{>w8$nQcj{NvAc=D|ry1=)K3xHI+e=d#2&}NiRg@eUuin_###0N-v^s8=Db8TSh>dmoBmD2R|XD z5otSD-lOtpjzzxvH9Gxepm7n!tWxJV#M(z1*B0;54|K|)4G*>mi2TVQr8QkxWV!~c z)cc#_=#z>+Q>H8pR|=BNjBS>HBrY_xvLeomy?`t$~XIFH>YEYc*lO*DFD;?pI*$ zBO(vpw>Kg8zxLk`@y?7_UWdFeCbQw6^qw|G8bqErAx@q6hYzyT)b9;Iqp0E|X%NA$ zK0tlu@?EwCe0^DfTSL#S64q=oXQ8oGX`Lsq~Rt^Y^|q?F(II< zUAE&&jSt)3Cs4WSb#C{WNhZ#aOx81N0K=}BTNqW4wl%qIQz$zd#MQ>u+=BLPF6i(^ z|1;Tz0DevvT#>ZL6Ln*gLBF$#sEbMsh)nPO$}go-Y;wM3!`kH*@o^Dw z$ijPA5K*WO(IkZLrt>-XMg2_i7*w$pRg~n)?%HD4SHOfRL#YJZE-#)D$L}`r^`cIF zeCEWa!(8E?3aH+efXn2?-B#d4ZK{0*6OvJt+`v15Kpk4r;~&}7v|CJ^?qB`lMoljE zdlp`?LwH*absA3p7My6NIIYl9<)>Bar5K(qoAlv842O3`9?Be_Y`M}YdkU;pXl|i@ z5YJ{AUhwVuykKA;4lb0+=f1kKsg4IWj5zn}qfj`PlUeW7Z5ixk@@cLD2O5Iqlev9n zSaz&hOza05qEbU5Um(IEHWRm#$08M{S+%<=pJSefK9m6w)Q`_3I_))DChXyd+FW_4 zb8R@uoS5^@S|x93^?OYoo_w&3@Gw;NDLfB6f0fL2bmd)^#g#QR*!NVeVD{&jP@kYl z!Cs=MAOE&_&+9JDgB=ztfosWxCp2Q6wON-#XBWB}F56EQRkPNDAtefN(4XF=M=fr3 zWRp0p+O>WK6&9(01!t%!n2xe7pm|EC`5$nTP5XW;$KJB+s!tHin<-~x$wea9*^g$v zSk-5Rlmw3@=u4G4bJmWzL7L%{ZgG<}Ei^|12KQoj3k+F?mE30RM~Ypx6Xj=LrvyYE zjeKZS;vaG{rUVN|kE~Jt%pTgx&wN_dudiL^BwPfP#Gi;8H>R31e&|+w0!?;N*SnV` z@P98NJ(xg|yL`>dZ>7raCes$3<4x+CTpucpUWroX>=@#pJgDQEe50Dv5nn%Wm~K#0 zP16SgvljB@{zoS&N)&d0*C@H9S8`Vy#8W)Q{u=|v$U$d&`sm@t%{3!cdMl$}yIiSL ze8e{Y3(Ad@AI`&!RRRPjacV-7Taq>iI<;A@^NEgAw*zlRkkOmgW2+6i2$9{xhtK(v zMcC?T*d-jEJmqFXihYH=j@@GoO3swi^KID(wU*lC3zPU3nw&dzLeNRYC~2uO7Cd43_ANHT>IAFw?nUlY52p1jn+N&22kG)3z4g$CSu8%Z}sP9d3T*P z+D+EpY?_`Fq z#A`&?QKT2OWh0Koy(tu8E0!=~T;C~lDHr!XeuwNtUsYFqweO@z32OZJ#-2rsNu-G( z1SKANUiAJ)#=B0~BMX`=`$m={i;E`mjU(AaOcUN+(;6Dm zICPjQDC~b2c-X#Wo}UO{4HFAr<4s@Nlgl>_n+GD1mHmd92!loGtw$CTK#Q{>YyhS? z3Nz&N3+U5Q8T_e{m+FyTRC0XE3^hOB>bJ=0GFGgR$Q#KUOygd(3X%noXsr)Y?TZ1^ELXobxpIpS~7^Bb353RE)xPZ(*=m07~W|~ zlE0{SwQkBnHW@nQoRy@TbFg-y{<7=y7(2}*B4MeG%>5{#2Z!5^G#vcJdA);ssY}k9q9~JP*u3cZ^n*AjP1!sB>!@WxYJ zePX)mQ-#tN)vqU?>6Gk{Ai}0)IV`8U2vki}p>;<-+Jqam?N5)Gs>aZaw7nG5NWiVn z0F0ozZ?|L=fHdRivLF8u0jQ{Gkxl@y=M$i`dQO6}<|GV4(HgOmV5kV&0V02hFUvma zIIJ&Z!xkl7mEdKucFxCfaO>D-9UjG3(I8?0R)9qX{p0W`L`%Aa2Iw-K=nFYn*}|et zqD^JLRt@l4V@dUx$g3-2-9J@!CXd4Ag{EheTYZGCTI**b7$l(m-0Nsb_QYcp$9kAw z9C{>=Q-LEnlT2TJ-30|&9AbJG%`tA)GqEFul@5;iKfxO;eLO)#}@aVacUqgUnSlKe?RwoJdD~dC9&b zK2#YVJMVb(Si8>a5FW8h(ZGbQwM;dI@t( z3Pb;e1;cG_F13Ay8KP+BpWIll*)}c(c?iP4Y`$Xzz9aW%2ZgnIhuZ%NNN}A?k|DnR zA{&r-eGdrPkOoHG(S+R?4FOrgW`xQ>Rhu1}FPz!Ri3+f*0}yA+S4{g$$^9PM(fJADu4ZBKu|@u^VN+eb9&{xL`(s-ct}cw?0g8$K zjmeS~xgS6y_dc(tCZ2yK>=mYWvV}@=2@OwY-sab!GzT8&Xe#`P zFdRKqzDKF4d+Xe2$N~9?RI7KMq0ejY&DTHsa@&4Ym$}WxMkhBIjT$R_tbpFC>ruk3 zRB0sxgT4j?WN~K#68ZF|GwxdzW9+EkPcQm-iDwGR?Ha z9Uz;b^eF+Hrdi^FX+K3 z(9ah?$it;hFlGQeont5r+ws3twGV_ zxUF`wm6R*bk(=^SiH|Bnit*A8w zk=W;EEDUd-ep${N*e+X%lwr$4C?sNglUCKqME4HYU{v7OCOGgsNoni#xebh-;i=28 z92sD2z6w;3sEWMwRLq7K8`MT(OiMdPnMYIR@W$WjHB8;IjC?>Q@9kgzuRc{KKsY-3 zD_izY4N%1E<+Gwnc(TT#b%uk{!?t3^#rs z-D95DKE%bUE{wj|^9i1N&Yt-zY@13lAU)nr|A$COcJ8VF7XuO{_4KiuJ3T8D9Zz;# zqn_mgTd$clG->%ZpW|)j-0S~KA_lIdS95am68!t=)`cryoiP0ZTb9)#j-!!TXl12M z2y4d^EUclvcYP)t0X{YYgA;kgHf&@#rqc_&>S&oajN zJg3LRmY7cz_u1%YEUbHGO0qAtSPNKN87b^`x~7Z${%YG|%Kf9Haxj}b3+&;pGrE&= zm^`kcMw4uJoK)GE;Wgttrgr8~=jTB4ybsSmx#Nka837hnU8_Qq)I&){KY zyab+mqzN1whJJ1G&ymRfTV5Sxr~#--y?_QD)|8A2Fhgn4iM=?AmstL^nCWbz(EInR zX2!sQ!NB#VcuN^!G2g2Gs*i3yvWQ}uPI zMrlcEe)r3ThF6}_+7d%gFRsqfN650w7suRKU7%59fAS1pXcBOc+iuCMGJ@$l5~QE$ zxh<;n4C_8`CorGD*%CgCSy#Gko%MQpW55}ln8$BOzkb7#HiRY;TlYW$4z1k z$DldKv<92odJ0<->riY{Jm4{)F(Qdv&*RNQUfPS*O1*G5ijvKNMn3LQ-xKw!abl-< zpg^ibj-3w(j1KaTC}x=U4cq0}CiBy0>Q5Uuw+a%fViFflhpSqq!8raB9ZxW#V%pSh z!q$~56WPRt{92IAudpz7G8+xtr!*tr?Ucqe)O^SI`lr>9@A03X{Ndk|r@tg{-{@Vx zmN=T5iO(@j>CImM=I;i!ksq#lLl}VSjE0+EGds?R}g=OSKg^ z=UIPE3v#Wk-pX0k6!^qch)kV&sHe{lq8Fi7dWfSL%R@+Mai$)!p;cGju zGXhQNp!UBY(ToGr>E&UD!lPM~_)K_Xu_=syBZaUnoo8{*6xR6C;dXc&PZCh z9t6%Ev!nz%FPfkExW9HHQD2OkDUF#Tl`=Wy)pUEqoMY&Rfw7@6w?gVck4t{MHe^JS zS$Lj=ITqHRcfjf|i48@yq(ENX*@;1&m|bXsMIknpyBP+v@r|XH>C!-tDZCe|Ni^qf zFiq#sG-eBaC0`IO^mEtnlhC=ZL7qZnlJ>?wz2xn9;@7askB8;o{H3hG8(OoZ|LNF~ z=2wXzZhJJ3fotSun4^u&PW3>-mKh?ghbEI3OVR<-<@HGOaw8Jc5w9dk4bQT%KM{sY zi=vz6J_Fms&jp`r%SUmgIPIx$ps~T%`dEMIsb_=ZEh%eas?X0|MvbVQW02H4oY!=#*aUPD1^*wmQWNZ?$;N@r2 zSRFpI+B`ElLssH?(opK^w}n#kfMJatd1{(O{bzisTK+xR{j}m^HpFILJc}K=A&hkv zI|vgx2ezh70-q{d^t__F!o%`AoSu?z1y)Se|E8VndX*7?l4;FE9gMjZH_g=xS|ntM z{p>e}Ts69Kh||vcz0Cn<`b6pMYWnj(0!)QvDvhRLeHkF=k@L1}$fm`;Kl*+K7s{on z^ph=*Cr_H}rxQgJ3Xg2=4P+n%N1x98<*02IYF3YkU&G>=*uX`-dfGEh;QjG zmXMU*kbpvqpiu_BCN~emciXG3Yq5AzlB89lA*iIE+5PHZd@O%TjM&;Je5Nh2?07Zs zHO}#40rc12eThpTFuPX#2}7RGhc-Y%3B{b8-jE(SEcwpLQn3mbh2_B z3~nY~ZQ^*`;gy@_yciioj3!K~+Xn~Msi z^SN<%j@`!xAFKl(yWY+M%Ye1fgzf$prF!7DQX{bE3(h0tO=h+sYHzi02T%%6`b;ny z7wb*Gvc>Hmp`O5zY{2z5FE?#K|5*MPC@ zxIWcDudc2x(nI39+aGhAnd`c*>zs2v&pFR?=AE978p9>dOEfez3}E#q z`ZP4>d}wG+4PQ79yrbEgzzn>cx6)L5LUT<0``A#BKtpqb2K?mlbDs~(L_hxzwyDQ| z);6{9`q_Dj9@Tl(5!YGDFZdwpZ8Z~EolHhXi13#aTIz3Dc8kd9)#9cD7&I0qo?|(| z|NIKn%$wy-4{F5~dbY^)Q4CKxi%|7-(@Uj~Jl`+u9mZdLdlzhnOs%)SowZGtDYLW7 zT&QpAlU6_(tu9~%fQ9}4Ud0KamuYB*m+_hs&}*PGdJH*2;}upd5%MYv)N#Qc223Ct zn&;Be`+%O7|vE()UHtfBal_1<27S|x1x3)K9%;8q$p)&xAtvvGI~K#MrdvH0%+*H3O6rx zPCY0v`J+@}o15Z<)3%b#IfW00D%NGjo#Nac%S_bp8ZUFZeDy20W?mmZL;Zdyml!9_ z$8Vb~t6^ymaP6RI!u@KcOz+5u7RmTf2L7S(_3&42BoF3r62NxqG8jTdml*Hy#9vw@k&G zx9R87p2#wao7v|S&4aE2F%`+kccHIdNS4nj-?SgyI<7e;=W^%1Z=;$j&GXxUyn{b5 zj9j|;JVu$PAa3E_DE+vHk}UPZkL%^_oHWl1A>$Wj*AW#SiJf{aJ@KFACU@!K+~MPL z6SrJ;h2|?xbe|N-@tH>N@g=Ahw?q0rR?Lx}JyJtn&D?xu7QcSB(!H#1F=aKO?jyLO zS(%n5*l}cNXja<3cPLTVKv}KmRkr;_z7m&-T8Fi%1|{Pf$KhZ7CMRo{?9VxQ0PxQp zWqEDRHH&JlWv>Hg%+i7f zIY=C{vtV|wTSl{S;r-hC-5ANqji0St%LqpA=>0B3R8PT$ZpI7LwOTG0UgV~sxm$e{ z+R&I|alA0rxO)7#%=o_XfLrzs1mtXTM1abEXbWXq4eK<*`JUUZNLISzB;i27wh(1d@L z%|sb{ON(+%XuB6f*o12x8QPu9QqLp*eBxw%kK9cFn9%Dg?@mpVvej4=dekyr z>yo~;O56{5@ySr^a>j`&IvJ=IadLfB9smp_4wG%l&P*OTzG8iX9eS%&5Lsu<`KWRA z#2$hP)W!e3{vTlTYJi4@h2M;Kym91QJ*5!Z=)W6RdU>x&>9^0}cGp6K^MnmoneqCA z1!W$&td)oW?x%YuTR}<_&fD+1H@^NH)?@JERvIUbJBRwP=P{y!no&}-H z%0qTNh^4US>9;Gx&{?)O(OlGFAM2>k^@+~D^sakcw8V-nW>=J|f{)l|Kh6bTN^y%v zyUp7L||yNmd!IQb?~asy=K&Vmh#$ zPr()4*11sCy%0bh^@wz``lPO?ek+mI(PkFQ$bd#Z7hb)8YtP)YbJ!OC4re$Vqwe#I z@e@XKn!+n{BN!Ne3)VTnnwI=0ZN)zvQFdhy^Q0Xk(4xN8m4EE6v6;HCZj!uje`4|0 zEPx4HMsYemwXJX+<}D6)7M_)ktR9v24JQ|w35D*7sswpaR}#GZS1rz4){+sbayE55YuCO;5-pC`$2QlB!N{d_U-@#Gua>2k_RM+fT#hYhx$Nt*(`nELV5F*J8s^?sbANi20Py&O@0 z;)-dK!T@&|9HHkb?JLZAvX#zLfO-L-ce`2n#$ubpd7uKaMQ(CwG&#R2H{`c#c~yow z)uTpHAQC9F)7I8j^qkkyPL&dXF@LlIoQSsH_Uhr+;uoKQ$mB$5bJR!tz4WrFheD_@ z8!?#dx&KC^=i~$S2`WxpD%Ow8PD(pDnRjccc=Go;@gRS13-zde_2l}f3|RT!+u%zr zx14D7Z2BHMRfF+@-}9HVb<0lYyPAR5x+U`}ph8;l4_n z5c{X1=wH%`J`uX9zE6HNDQz?9ZYNp@Y}R?ktjjeWcfT66m-AgX%FK!S)4Gx0!W5gz zO!OR7QGF12b+_A_+ggUn@mB#4LUw%nJ6-n1?45`lc@=x=vVuKqvH@}4QLzs1i-JzS z)3V2s6G}I|;EP&g{04!gC{Hu;N@)vcZbh?13Z-l{ZN${AkJagem3qE^1j<4k5rVSs zp;V2+?QO=d@%Bqhu$pWhJUNkPD-BhzVZ(9jnv0*Ae z)n#ed53bA0Lu^p&6MPe!XNj^?DaKwxdpE~;FBD<`!G6(#uNK$*iAWHhw#%QGtP#i< z>9g>8%vcJwvK@~-v4b!4<}_bErpfMQD>y*y@fLNYw8K8~j8lrS(IO(jgXV@46vX~ zJ|)vC_65DzrdL(VUKHey)6_iyegXatC=-7}S6(cR!nZc??V8$&Sxwr z);PKJYA{{`>jX1(YRFSw=zK?3t`9Vh$d*!_&B9fGW}abDacWSM7-Y0v>V4_yNsuUT zduBEea$+$aPXTxQyE6Z>66uf5Ate6D9IpnbuFvhglOHfu3!WkHA5?-hp(l@X5IT({ z<+N%CJ}+t&6_TFD=(357l!c3}V{@J;YxneQjdL`e*oGz5-uXAhQORB|a3g00P;Si> z`f`Ra?>l2Q@VK<~KdVB+@AtRK`^clh>f|KHZe=svcXR!c?T#7?{jHWEEd{B={bJv( zPx$;3Rndn7n~ieUl-r-R={#;m4ZAuLF&1kO_?ts<82YO5EMBa~v!vkp88p;NA{7>b zOG`^{usYUuY52nP0=1n=s)=k#g`hdXYLLnfMu`AGBY=0%yR)T~OA|bxS-YP#0wbLQ zul;M?Q}i};sIsG4{l1_+XGsVrZ)C!R?EW*Fp^Uvy*diwa%aso8ppnDSzwit7daWzAHYI*VwKBEIk4d6iX}K|jGgL>o%^jlysBrzr9XMua@O1JJ-(X8A+{y0E8YTVLcjRb@LA*Z^PSR zZFM{u&sif4J%RvQ)ws*NVBMBXhOFjmXNx-he}u6vqJ52$?kma zucxZcQuHGb=)5R&&&@ipLWv>87?X-6Mk@f<84w@ zYhsf;EK%Pn(^`Rwsoof!c8X$x&W8H7ph4j9FPY2>87G!o zd==1q;Wesu7`U-5(CI{&wpH;I(bTPpG2_##No~9`=JyJRc?)2dY_eWE-Tlv$9ZRd= z`&%StPpBA4GvPKVr3-ZM;qQJwjst!;_)h=m&jq#kRT)yx?F@pcTb8kJGCaKZg;tmB zqBD4KcJJAu=%Kcfx>8)VCVnov>TRvpyM`gD>9oQ4DQA3U`(~9*r(2y(0xu8f#A!aK z0}g=R*JRhN5Tx*N4o+W+sEAgxuLa}|m{6!Xu=Ds@1i%L*AEhlA$7&Ml$@ob5gCG6A zonM!Hw_a;DWJnM!>Yf`-6MP(QQe0Mxh*2OI+8edt$5zv> zsP4T`3AgBRKJl;Y9MsJ|7AODaOW-zLK)a=pMfNiZI79Jrmu$}@(_15|$gS@8ALW(p zITA@u$f=>a$DS%`!fFJ<1aT0vxMH^#SDzdc3AeDuNnH4A({~uEB4|D;L&jI(6(j^W zBZ5LG-6-*oOjk|T+Uu!VA2@03N;;4XyYHkpfu zE1erF75~xlwYwo~G@X<9oH^l{D}V;ybGpnm@fqC*NxV zO#eDayZE|(qo^NsThb%f%Wq6WMJ>uvRMQwR{9!95&yOvf7 zd|DXw%=QeOC1UmPZwk%0RO~r)$PbC4BuwVWbZD>s#qlK<&z|QEs(5=Mg^_BADPBAB z$_rFf2tM&{o$)vUgTNP}L;=#dvH`P+rRDtoiq3x=;!{C@I@nayIFeIw6d5p^1o<~9 zd*=B+N%kh*P7MLVSIPIl^45eE0I|xQ8+fn&wZlX{s%q>w<#wNSTqfQjeVX6<)fj;A zo`6j7fQ%m0Syl1ga)>cf_6v&&u_oSd@Sfe%TNF*QnL9lJ1VJ0NfSu~*s5gQ04~pmQ z7W__P*~Rc<{!@=Qz+O9{Q@OPK8O*6ugTP53h*!WCA#*vOG}+XPwPB=@eiIKk08;k` z2?EesSe5SOi~@Z1$QV|9umfob-Xm}?ECnTS2bwNIPUI<0HEj;#&#i*@U^~MehkE+^ zJAV*e#h`r?VA|VWVo2CTXK1ZFEZP5a;z$kh;XqM-zsa3}X!w>gAb@XqW5{bB#KHcb zMskzOOe*$NZyelDg<5uU^3;+Wx@bUq71Rq!!E|HRLVKUbq}3u^5SYy5p-EFWqwwB@ zG8L3-Rl&G)Nb3BTc*p>QaYoFHQ?^vvT*-s@NC3vda`+%v?nCrdMNc&XGCg{p}V{ z=$R|0f$085a2{rF;N4qv$~^)kD{IR$ptgSOSATt{iPRiH1B3xgn-iE(2KBiI<*hZH zW3cm?E?07H&5Hz*?$Ixi(0v{7Gws|62k1mMiI=F9#&^z%LmAHl)`#nTug@VJcxIS)U>Z2o@mJ4h?`~sQ}Ej3*vX@Fa8Ko$u_;y3|t4Ik?;f*Uk}VgGb2C=mal` zA3F4u?<)Bg*w0R@pF6vXxsxIfk3@xA5ek&;i@ZLGmrvIWIb>>f*ze)uXwOPI(6y)yVRPpE_u+q!-d)aazy+SJuO?30&A?MqkGi3eRN#xiPT4edRlQ~9W@ zy(0(xai$XkhE6o>eV8WDEX)k44S8mon@{ z9g3=OFU(vlE~X5`$L!{X@ZOU=g6}bP(rkxZUd#-{C7B`s&dRJ+g}ZDx+b=?1 zG*`E4af`5xM`q_TH&e2lqEQxYk_|qZrM@wn)gu$b7fJkJC27K5SYnye_+s0C7P|Wp zpoydOtizk8p&|kb9IAVtUTiEIWlO(EpvICJ8HlI(U8dyaiR=w#O>5k7Ub?H+dmS?q z`=*N-_9c$$yVt>lw0lteLVhfvNw%*d^FLA4eX2+w2E1<2b$qqWvT8bmu6gI0q3VwL zjm5&=pvIr1xB`~*KK~FhokAg3Q*^VdqHJ9@Yaj5GN%w5N0Qbm)YHG5H(>#9-oIV^l zigDpKoqfr$1eA)cMlE2){i($-R63iS@B={LWxgod0$6|r82c4kP}_r<4(pX35imG< zn$q|Z{}4P4hLLjt>8$=;-wiI{1jdE5I6ahfKpyGf7x)kPZyxq^A|_ZsMm3J(OEn}S z!c^bWsR7Cj(yb6PpLzE#ff5XEaxTSaDlc%n%g@gb^4un6domAQT+ofxZTvx5Y^*Wc zZ0FVuiwWtpx05$SLv{!H9{^^n2c=Rf!5%4}hwX*3xda-t@dX8L14e1-0Dbu>jS8Ik z9d=j&ShBt`?mM1=`>4+&0GCZvvUpeJICj?GNh)0j9jN48AiGT_q9a@2rCQrhw{E8d0fCJIh%s9LWJZ9|p z^O5y0{(w7Dhq)-KCi(69GD}10*ur8?CFa4&BSpEnd?&S<=QjbiK3G(-Zc0!<{@`h9 zW0r~figN@`;Fl|s6-%1$f2QHEa!peW-G`%m4f9fxgz->a#3NfOB}Cs}H`TYPKJ89; zlE4b+#0*GLG?QKW$B_9Qo4Nfa8Y{bpds8UzULrUvvHISBhVEJeLv8N4ZKbt(xoxRq zaFl&cQq%|{0++`Mj^tO6Vzt*QgIYO&vr?ZtvwHd-n1~!I}o*e*B2Niv3Aeou~xZLhEN6oP^H%)p&=> z`d)`p%qQDaXoB{H&y zfasd$gx;?UqH)U)0LGT*l`2K08xoAKnpkcN~# zYL$yD%cl@K5Cx?_>=R5`3G)jmC*y-~kUn^!B%SXHu*hHy0Exc5$7ABsQUmV{1^|a} zL~42jK$If)1YQBs2X$+Vf=Uo@^1#5rVsF+mT+_UyzTItaM*SaMUOap~l4(x;_SFPS z{&SQ!3lD!wbCc{JPA-_XJ23(>e}0E5fvDEYS-ZvsM@Cdeq78t~K5FQk?U|k8O;!fe z=D51hXXHVipmjSbF*cn*h?{qv!m__E{A+W?AnN*X&Ui01O=5QfA|Q4qAl!e4Ta|Xu z*VVPVDU--HcuN{y0yvnk7=3ZW9*jjANe!tuJ-KYXG`(!q{q6d)?9tD0CT7Q{%U`z6 zs@QV4;=WFCEko8FUdELM>s)0AW)`xL0SK^1k}@t76+b+-7uEE7P-Z`i&<4b8=>GcO zjz-Q~Dj<28w!AK7dtv$bBd`N;d-MUoS1t9sUvjX#S`l=rVzkON+z%+K{Q;?(=dMEx>YNMQi=~CQJ~W(1 z$3J`<3v*f&oy!N@PYqb?87j!tbfJtcqabdb)FfYCM+i!Gs8zPC4G8O!ntZR)Ap2YL zb^8BHT@NVCJYqrk-js33O${7_<_?;Y#aKXW=h<+qU~F_|``GaNqcYs>))`8Cze#I^ zf5h8Rh^V+(48%-?KB??VTSs!~8sVr-{5yNgLuzWJ=K=`7@D7lq|BBIZA(^R{=JkqW zU!qqoX3&K=0eE=3Ck2R}MCX>w;9J#T3pha#2rAXWd!<s4-XU7Td-sFy|u~pak*pml$z5Az|f6A;Az= zHjRA|IK*7{XxaZT2!;yJ`N zgjWsIY`I{yCLW0LtNF2Mr1cSm zUyxIS0vCvFos9~Vcz_NK>(v)FU2@Jvr4!-sLBleJ4BF7gekbTfjZq${Isnm?1Hmu_ zfsePt42^a6r{2BvAE-=fb)q~2S0T0*EBj6K*jIJjsWJAKe*wZk?`m@CHXl;BX$(as z4q=0`rfLwG3fDnwPhCmpl^)|eD#-Ida-t37S>hx|&%>sCxT4H|@cq7M<@t}x|I7Y- zs0HD~V7H^p|0_=}dNNfMRQm^8S76wKRAdHGv4-XbJ&<<@nHizC|8yh<4WKT2A38%~ zdtc?%nQ61u!!$RplP_|kuGNTD9!dptqPl=AKnw`W6H}8~{zPWv;+Z!P6mGvd$;yUl z!Y7~dfQQz^~m^Ib?i5-6ig4Mh0s9Q3hNF1_G)rg4Ga>zw!-n$ zdN0FNjG$0KsR1lZ^#RLzr?6&4)YkP4;r1;tWx_T)9f2yK_H%$Anrk6)%75+{9KTbf zi8nJ*FWvLOh$q5sERD1Raxnp-zIiNOD+uYl-E<*C&?4ZRd=xj|VRzMvT0C`*MXGMb z7NP3eayYUnn82UE1O>>${r-Brv-zraOUCv6=Jeco_!`l2G32<-p6TFIrF*c<_@$tU zz+<53h?%j+y--RqJNB$^QJT(qi8fhRX!CFD_Ky0Q$tX8vN${(4nzX3B<)Wx+8Tbfz zAPrFA50)ALSRfpE0*Td18`O7GV#v7I;@)DXgsL*|gkVKs$#>Qnk*qBaGManpKScRP zn#u`A6!P)I3BqC4HVYlC$R0!OwB^i#{=;rLP4vQjq$J&gR`ovjx&`VJF2w>d+&`w+ zF-8r5rCZhLfb9b;9oQX%g~Lgw!8Py1iJTzKnpZ$|K;SS})5skAwGWUDTL{rZX=vl8 zIdAXleU_XnscY;lLV>J^C}rF0C8HBTtPpyeh@zm#VE;?Sd_=eVhp{HbzwC}BBcacGx3Ni}3F8V_NLHNlwn&J^U<6a!p=h$_4{6#v^EmZ_D{1JeW+{%Z4_R}etmIH4tEN;k|p z;mNR@Zq1Ae2^gT|CsC?doi&6DEmw(piRs9jc2k^q@lRLKayWcs@nQWu82iPlVM-g? z z9&Q3-`C*w>i%JHv6D4C1M8oA;i({9K9;8c?6*C*%FzYP>N82uB&8oJfeRDK>+%C#+ z!>-JCIk-2;Arnl8MM-N*fr(PlUCy;iHcx>SBnkq7Lxd~IPDyA9pJGKwk~+Mhpriel zK+699pW;#fv*IyrI%f;1xfJl;pFHkHyB8UU_hI>O&Wkk0PTF4L zlJl?76Y3US0%nS#+Zz4l9rmgYJ#Zu9Oh%f0z6w8FvpB#v*C+xfMH-`#1Q1Yfo+^Z5 zO@lzkNnG4Gy&QDX&|WUI_wC*P3Q>!pP7TDg<=-_GWG)~|$b!hX9RWr~1Ag~sWc24+ ztaS!&DyvUye*F+1_^5Mxt|nyFZQLN@J+Q?>Q2(}YT! z^8I+gSMj-Qdbt6qoq3F3v&0V1p(Sa-0IZyBz;v|!V7R*u}IOPybB*SKt~^!BITdG_x=cT^{rM)d8E z`A9(kOOp@jf?_98Axd&b&Y~NcO+6+$ueJIb)3&3 z7Ti}?t(LFgu_8;zY&`9LYb28mW$$Wgxv$}|4lGOP5}@%*cgB9QAz}@|3}ErP$ZtSKbBy8t!^w8@ai-TGm&*(J~s1y>?6)3MnyJGPWa6&6i_$B&@ zbD7xhm?!hJFcyn%5=Of(<2T|?E|SUJK36l9pscgsLq zRM^X*t-hg@Z+2YRA?4Nz%)yA+$!(gz<5cEY<9S?#@L#z`zVqD|kbe{laDt*BKpIfr zxQyp!b$Z-&+V3GuG%(wDum^<7T*?>9 z_t-le2I?XyuouleN5V?#nmwD(Qesjl&V^c3|E^Kb@}8~i&-ZMDd&7u(HG(5UPn6Z# zfItYOkIrQw3q`_e(_h-tZgO}oOYa^wqLb8%6)tb1HZ9)N`LrQAqvyuYDEd^h7 zQ(cRyFQ7=@DZtW`f`QELssj)>_=X#5rgbShvPS@kQ0nC;#Bp{|m+|nVv%7V;L;}n$ zM>8v)5(|j@c9yd11D4tIcNUxrue(G#H=&%;(ht*PvvLui26&b2J5}fR-xNs2zLWvD zT_zdOZEjL~Ax7c5qzCuS!DmY=!UwVmF&?B>-rS-Iw^GcbP&S=eo+L2Yg{{H>pMdnL zuNIL4%3nI<5d$g-@+(6Uh^LJK>CTpB6OTo!;>KO2GbZ%iyaD)=viqO%WdF0)N@{(| zI{Y{U*ErC>N|wg_V-)Hv?Z59@lVTo#3jln8uLQyRGTiC-%S;UH!`DoE=}E;iWhM_S z+ME}XSMKw55Vs!^oYGvna}cpPJHfT83ZP9Sym2iobn6M}yhNkcO}{48Gy}$E5EKOM zJIkG+P6l@I6P;U%x#Is8<&bLin_P-ve>f#jWT=t<*`VRvg5Z!m-;R4irWXMyoEePyY-5qq^GR<&9Bj;%i%CD#~96&(B9KUwwaAd%l-S^ zLzO~lH-9&ZJZ82_ZyyPkfB*o38sg_Ey1FNMvq@hCiHqnkLCXZGfHha%b36q3VGXF(H zHpjN13l#7(HR0qAYK7xZFEbG0cvBUIdKr=hG&>>5>h(vJ@Ww;6MJ=HqC=~lh-z7&A z6V`hgY{%p6V=#+7?g#I&fqCOmnXZTETEhYqR4^TujpEF+jcr>3*Y4-Cl6bs{Zu#NN zq_2y24;$ZyMjy4*9;sG;HDB|Sm>`632l21XA-bJIn|@}pfpm`#Y0ay$?K+bO;i4mf zx%K&>cNWd-r`npXkWlR~{bkTF%78y3Gw`Xjtw#H-2fU?W`jg<^%HFS~y-BvGTx5V3 zFxlJ^3w&L;LahttxN5(HwAI0uyXe}%ZSAlUZ~+chf}r~rU!OQ7CScHL)S&Q>Hx{Tj z>PWlvQ5dE;(!FXj%AiuY7C_Zkh)O(!0eUtqk-(9+GI=tLTrgodK30TV39h-@FL&!2 zd%feQZ25MxSj5hgEF<%xVl;#Ph#-sNvv*{4xRSt6A7I*M%+O1 zP&R|u&OIz8ECxjeKH#mIbmyk)YSY!?H#o|Y(1_I1@F^M9BHkXxGLw=tt)-&-JpQ#X z5EcF0{VhRWI`;8|4iu1x_sEh^tV~ayHE|Om-C$l3ljIPF@)XccaQa76Dh0`ncqTl3 z(;-DGwyS0kqN|R0nCzvB<{rGg*r8ExM)fHPGk<`H z(gDZX@`PvrT|ioGoiaTLws+~`UCeLu1}9-rh>0id+T#O7KvPA*EJ8UyLwx05EgS?f z3Dq5X&ojOMnP?oMeKv$n{+#As*o(s*m8CkO zvX7TjyF~Ht7*;Z$D{rp`=`ia57STO4Re5-KR2Hc8)V)iP*?i%06Vld-w!Ss^ZWU+( z!h)Fw#kJEYOUYL%oc#D#^oRCq9IG4bD!uyI*nvJ~pzS-@$N`{n$Q%U{6fx9@3s93d zx23!YDSTMr5RdW$`bHQ5U9nK-??`|t>zY>ak!p>x_v;_`b;y9x#wxn_W!Z!lJp7N( z;qN?}Kxa*jvOor-7JHeGe}{ zK9H}eaZDb%VSp&-t*m>_M~Jt>npRxy6+OQt4+eT_j3VG!kZmAYY>Q;&JXhuQ4lW#C zdqtbVr+^82lJv>0R zRRsYlcr=V@7l1)fe2H;{7UF9jZ4V3sDbU=j)C$U4F}}T7ml#J%zMtLXmhRMyHn+GC z!b0#cDR-`G`S!H(k+FE$g4D<>R!fngTQ>FP33>!cworDz!VQrjW#8rwN=*~Yq_Zp% zV$`)Mo{C3o{&Ga3RyiB?!|H1bUWV{Gp~qOAYSln3P_`~ur4~>o*ziz@+ub;f!>tyR z28h(E$+?SB$WBW6w3skC<9Q^($LiZzZiT=Pc6IllXa^~7L4rH-=)3ly0JlI2Rsbkb zKf+tDB0iVxke3cYF`J`rFCv!5A8fVZGj0OlbQUv0^b4!M`<{LI|~; zVpIIy20(uQtw_Nh6{yDRyvs8X8(HSg2c}1o{?v8l;k5R2Q+PDgy&D1}1BpPqFyD6^ zq-jb?JA<=|wP7VI3Q&HI_G0H8ut(n&Fl}!+k43nAvm}` z^RAoklTl5`zcQNnCJ_KEPbfny@uJ{x)%c;Y-EqS!cH`m%ugK~K`wz8AWFkQMMcFd@ zypcpxi&K21Tml(6Tar);P zyu%*)(S$0_K4Bw(!!C08l*Ou)+hw~~l5Q?&RGJ=kun(Kt-TI80kY)roRLKkK4A5(m zpL_OrIn-*hb!~Ex>H*)#vk7U=wgLZhYHx|)EG~~ zAMu{@DPGn_-TYi)-gl96Khy*ikh`0VQVN`@JVhjYE;XV|UK|1ftMli~E$M+~pY4J{ z)0?CsA$6w1-24U@O~!Q6V^88@ za%%K;!CpxBIy$h%+%ndD{3lymW-7ztxZt4uH3PVdBsdyCXj%YyK6OjUH?bg<$_wBG^ z9IFOM(MuI7lPY@!onbdV6?DE_6Zia62HznDXd$Kteu{DTJT*?0(E(`Uyj9Z|gSoN& z>5QS30Q>RLSg;M<1r*-TQfWL10a%(Q;Pw&x8LQ|)7AFt81T`pjT8oRB{3)JvM2IE0 zr7sxk-t;UfuHpsSpbEfl(u94W3UDko`{&fGgf!E-wKn;1Jd=~#uyDrCRN=sT{$|nk z6gN~lw>x1`;Cvq8vFt;Q-CS{nYrbpC)1x)e{1w`0f-HjO3{4zR zIr_q$ptU=ObVb4nwIYG`7UJuDnqBq(WQR|hMov+Q(rXtpe&R{2WO})bqZ}9#B7-!) zM|v~5DUvYqo^+J?2iug`aGA+qGt(zlwl&@qXmmB{9zE09+_#tUzuAROjTuSqT)T*y_a4AwB*`2sW=@T1!Ox_{FNlYLZi0QvHU1nI>aBDQI?2 zLm5l157^V5_gb=~wj4&MADmelAd;$GiAF` zUTqu|M3-^#k#9%s#|f77!?-iFu%}cgg*nczeVePe7uZ(6XDv0?lthU`;U?im{&BT- zb^)gY=)N+HpZ>MZyZ@3{lQvgj*Kto|D~0Z>r)?T(N`7Ciie}PllO<3()N=Thd_&MF znqlYP0uiU4hXTdOWQR}`RQ<Sp!4;B{^zU!a{toNdOCfBC`eWt^7Ua3>E}O@UIxG zb)!<~*ku&3IQ=ppRSWtC&5E|p2s-@d=l&n_z}>kf&4NL}#9Lf?Mc3YaZze#!iRsD< zLP`Gt;_7?2X~r+Ti4+i+xO6DLA^zg)bn1nLh@L=o!l|B!Jh>-1s?X#2oFj&Hn4Dgzj&JfzkxLYn(k zQB@?+`W8LkW4`gEKqsmJ^PVf+&TNf-Cs!(c*@GmWzyl*?7k@rCMnrO(ijWi>2or{V z7`3qR1K`((r3tWC;7VK1-$Q>CZAX5BcG^4A?!zOZv+j*KF+PCQFx~d+c^s~)>)fEa z9eBKIxqG@??s%6JcpPMS$hi4SCFa9NZ~ww)ti#6JbhyL3h3&;W`>cURLGOvo72L{h z+g5n*Xx|3#>y4!g+_zA`8mn?O1v}vR5PMS;2C?>!Yq-Xe_LjC1)N*l@|%058-zTkn$j*xD;Ie=6dQg~;=*FW18XbdVBNyCEjNO-E27(4Ax(X;V)3;?rimqecAc34&Mr^eEya37CreJO*3PH37~Fb^wsjFc zMf0c#;HQe!0hV}dpePo+_W_d5l%F>@NoE?(t7umGflj|h1R>^>CxHG7S!y?V;l`Ya zwSDKNAy}{&!%q2(@|&e%Io{!LX@@`}SU3C|2lQ9?C^y|D*#k|LeJVZrI{E$ykf1vT zDXEjz!=20w*bq&gj-KHmQ#UbzC{tEW{l@R8H5}zlEy9cmq$|wtw#i|bD-QwKpK<4j z_eB%Xih~zTK~~Zk(*P-I@U5=>@o~!?TSS4TTMDdPO3B}oup&i#mgN2HMqT4CHy{BX z!s!)5s)i=gNI$ym%2sx{$k}O}#4OSa2AW4;plnwB9q*;2_!9dJZ-P`DFfAw>)TGb* zudZiMWTNmqPrpN|iRGF7IYmK2NXdF;`t13j0;@v|<#-IYeg8qR)bUJK0RkBu7ko*y z62kl#-6;lPQoUz$`{F9JahSJmX^HWimR;DtImo&@=aH#b z=u^&KVY(uD>T~dwvut`d;x(lPHxG^$T^H{KWTDZG{?lcI&&XBmhk{~q(UKy3>AE=g zVr5_J)#ihjO2ZjRETY$}U~&dd>!wQ_TUo!lTTNu|Hcv5mKiot%vZBvSvmMR6vHMM(ie(Z@Ho1yMMKz6zj7P5@?t7iRzIc;1&HW>n z+t&wIeE3M7vCRqRo7{Iw^KkwbGNxU}y4{j9T_swvS8v_Idp!Rtf&$1M;>SF8=AwujMf!)$qvc4 z+7T3H>F66nH{QJA*b2FCwP^CQ>HGZ;E4)q9nP;9Z-gPVQLZi)IGuW&;PRmq83l5e( zS3}N>S^p8m`6`--vt87GDC4YF3A1b4{* z-{!Tv#^I?yuaE&8w#Ql)O_#${J%w5WKYJV^zFDfgcihAcybQtmU%47zp?9uKok`xQ zUUz(;ZZev&&V5V=teE{qo&PeOp^yD5`qYY`paO;KwkBgq^)HLztM2FhP=ZbRsa)k# z*CvORdXD5eea69kaY5(qPg^2_Qiz7z>qa}*8S6$K9&fYBOV z;Je9meF7@j`n9iYxmwVg!Fc@Jxvqe3nx|;%JoR2(cW%A;_Ii~2l`_iqzWtBDAAupX zD%N}#c_zIXg8F?mo;-?k zd^XVqy&T-T^X@zIjZ8bQaN9M+%Lq3L^jnz01n9Us*+ zt!c+KpJjm~VssF#tJdvQj8F2R@M;|@y56ksZY*{{Y1AR>lO0O~*?+RH=#X z{4DcQ>#|CWc#Z56Nb zfGk7Ko3dVYkSPAa;&98;XorjGH<1#2>$v#M5bA0-*VfFL1)Xp{THNxK{zieD{`I9( z32&@l-#(*8!xSv`Md7@6`0H2>?=|U6+952uf+D^_M9$O^e~!gmovMFb+n`65Lb(1u z{2UUSK6vKyt6n)w^h_nR_78zAO8d(y$xYJrsg%}c?%tqj+ki77?9h7NzXMa&eVrjX z@;q+Y$-R{|<(%A(*|*>tcHDYr;KiQZxbVqj#a_f4!8c{DQ{BonQ_dEtuEDSKe`pB| zv-Ds7;(5O5iwXG@xh=MQK4Ne=wQeS9>z@6)*lGAR+S>-u*z3&q!?AfsjLRP~SA>5A zdh?VA)BY0|z3RM}4=(vI+&z6Tk|D$H#8iIdwl*8MDM`4FHQIS>H+gvy z>nnX+PJwBTST!i91P05qrAjjHR6UqR4D2q+NV|9%j^=9Qd7VBF&w7(Y>neN~4+;}xrzGnSf;*{ux z46*YT+EK4fnB^o;^~{TX+j=)HK2$IM^l{U!WNiQP>VS;auVf-oz}}uouSben%KlaNGyq^AgxoOT&7tiP`gLC>F6~}U=FRDUrSIKsR?L*AF*VGp z=lkLYKEC2*f0!&bnb($`Zq}!frQELZgZ4~DH*Xiyxs9-cMHTMFr0vu zR+|3exxlc`!`IvPhAw!ar~cvMk0!QE$G%}DD~IO|Do0@`$p-<09uWm-c-g7i9|xB- ziFNb|lfJ`Res@-VRDUF`@+dFdjj}$ypcjrg9h8tc$MJBurMU~L5cRt&v}%QPe}?sH z{CeR(MyNM%#$Dm_MrUS%>(4-CnZ31caZvReGWHfi>gBe(eqp(F>&(YeZ~K6{Gi25* zD~T4)@+VeDW3qU)7A{Vro_p_r->84 z-jE+9#d_hGv=ImtdSK^Z=oRI+Vaq4Y7atpa{oUI$ zB?3S2Z*jZpR(B{`jIiNc4U6I;^2SQ&J}9fu_HIJ&W@~$vPpH_vdN3qj%4b z8&b|#a4uFhJ>f*%Yp6=zM_oMCcCL5mgP>_<+io6hNt+2T2qT{PGU(q2ka#1KImz#; zN8#6(t3^Ro*s;?--(EI+Js%$Zrs5^+As0-=;t4+w6}0Ydgdb|JLabZkR}aXKQUVlK z-=i9Aln`l0&p;fb(h9z~WOdfxw%)Rry-d76NNOI;Gwv#ZAYqb09|zBG^mu;t$olR7 zh2wnI>C3N;GhZtHS&zA#*N}`IL7`n#6_sjsviLTLmje0U}}dN&1)FFM`2; zThv_7VAQr!V)l_7vlN=erAv(z0RPlX5$*JR@KFZ`~Tu2ae(y zU*8)t3vX`BmZ(-O%elAlm%31+9`>L2H9fAkR-o>9ZlAuslhF+N0B0@lwfL3!b$dLy zyK=*5cX~%Cmg@i-lmcZV$g0n%GuC;>Kd`6tmGjz8=^Dkr6N;}-Fw~7?NYM9|(^}Kj zwg7=g-sNNG|HIvThc&f*?V=zGb_AujEs98&-UL*7m)=1|Kzb+iB3tPoT_Au+?@~h# zC{0RGdI?1!LbL=sk+Wz2WH;~jI&`Qf2}3FSfGlTWHY%q|ZRFWWovoL)KH9SfLH7@mcAM!Ugc?J44?36z86WAijb zy`__i)&|h36m)~qX^nFEKHxRELBB4mx;YfyND;A5l!fB{Y|&xmM7HnLYGcI8nr_`EhSf<~4d&?w-@j*PF$GZ3@3W8th7YD>!x`*2_k5IM?5=-S?VN;`PSz z^qy$H_x_D^eEX2;dHGvyLZ!M^OTwguB+6knBet_~ma| zDHnLR>$(>ZDH0PSWNGaO4J{GV@|g~!F$}iUjh2!h0TDi1{XVqd0N!uO4Bj7dS|K)r z0g_1Y4r-ux8@4&5QQd_hEF`V;welsN<8IkP9o`vqJulQ;(aV4SdXt;S9AQFUCTcl2 z2XWD~$bM(Z!FT#`SBDmT!($p|Uv*>nq$%v=a%d1K;-dM5ZuXcFYRGg9f7rMe_4UJ- zcTXgOztMP3y>D2u^>j};IEYB}hIbT(oCdR8R6f%&<54d6v_RiZYu^bGq_R{wN{8Ru zhTnugGF(DT^O!WKYKAHcrUARUVZP|1dSk`!dhs|WjO4b`{>HK7@Vw2e5&YZDligjN z^~xQ2Zq{K#5VKH*&b^co^QhR-h3n!A0QaE`C~aMeGZBBNT;l0;M1fFavC$MOBZuzi zR25kMJ(K%e`XxaBUkKp{3aqKvOjgDIQGTOG<#sVG4a2~NP4|Pow%dl)wp{aMb5vp@ zLLZC+ir_IN7h6Y%s++E?pkdJ&-8;u!cGDfm*yO z>oCl?+)$@Gp~@QbUn8{=uagJ@e$$msp-vI^<~F*P>fThm@_uMYFC6;yFpS~y0dm2^ga+a;EWN^qYvrHY>{f1{34tZ}uA!g4D3^r2yE0z# zGeoF{++wS8cDf_pno+rzf>tr1sgeJt_sxcxXwRIQihHkHk5p*l^>e|vmiW!QYfCy$ zs=$w6{#|Rb6sx=_O5m72G_lpXY@4oPJtSlW>@v}N?xKNNk2Za=;+sakO|7&xEp-1a zWQ07{W?2nP^;6ofYG&UKeYBiVYCYYp-Cy8*^@QlRoA=g>)bdD)Ij_R2bEHd7Qe5JL znVJlY_Fwvb>5!Ot86b0%kHv%PwoZoiHF_uF_`1uz?Y8UBR*~iUal->{&E8)=SU!rq z)J>A%y4lY>pdLyUsU%1k#DDV|Zr(P(e8A`uFDWCiWO^fSyp0fHDI_vxpvm+c2rX{Y z%SWa``@1@KDOUdTMDqaTn&d$^0}HX2i)H(-{$%NCNt+1v2OD2sg~G{W@PcBq`U-cd zKV6+uNNHO=&Tiikv!6YvHLh2M0?M+}y!mzc(ei6i4Uvx*)~}yjY3PbJNll@VxCc(9&y#l|!L2 zjQua4zU3f>{&t~sA-Z(|M*?ehmvrfQK?Aoh%kaurubYx65lNvlT-H<>7HkB7~{RMOt0qvl}j?lm7Hqz~wIRM06cfsAd1%r|< zlXNsfx<(8bEk>Am{pu|XnJFNy^z^1|=zkGISBh;5^;`VSsggI2u-K4<|DjY&cfH)D9g+E-s>R_T7|a-93Z!XgHdU=*LU!gVvnjhYXAU|B%OTMv+&IUr!>9&NsZYBQ!$ z`?!6dFRK@+iCH|*r(iJj)EQPfXi~Kd=Kjk@h4lWY+#}#iM!j3DBzuOdKyjcyJFzA) ztjRU1V=ZLW;Y~WjI4he6KvcRRic6dU*)E1GViZKLA-&4Dq~)32Cl>kJKy8SYl;G5xO8|fCZ~FYji!D7CJj`1p|TIr~*L@ za9~hu5KJDOJx&Y>2+>*qZhx^1b{}?qpjz?O4Utz;vTYPLZ(h6)c)V$tCsJ)fPLE{z zIstQ7NzX4d5g2|u>v;Ca!n1+sqv#K-`H0#Uk=(0uD|IjOS?DD2@At^t18!PO;WXMx z6@TSx4FYS*WOtQ&(Q-}f5}GORXggqF!R9VPwaLEX3TT(7#R~@h?OrK1m=z((TRewk z@E?*R>nSi<(Qy5Eb)D#>@*Cd;n}9cEQ`Kp8s+usGrC6BxO2r?N+jrqtWamKC)XcW& zo#z`6!0aFqZ}hi6sihkVbFza51X@v>n5gKyC%t;-Wl^qhLiG$i!{V6M4OO< z$|j^g1zm2Lw0|L;n%|*c(%!8UyV+((22oR~nKN2Q8LL+Bp2_0<1>rn0eT2ts%49dw zHJh0c*B&m`@~0rywtVE=$U=Y7KW;QvoJH$e?MkB0z$2Ucv$9IFoH zDa>05E#HUU9wEtL(p=;Jihg{0S&s-7#^;J&@N-lh_$88*br(MSE2M)L6DvtwtcLTH z{`ug?4gU+1|3$-ZZdd_*;O@4bXdAy+W?cQ=V3P6kOU{^8bJVfm*Dh-hl8k|d``%Ip z#jH=#2dBQZjWmqnzS!oS#eyh+?MvUwF^#)0`C+marO@C1#PALaYBypmuNM$iUOJ0( zuOusjeGtxZ-_sM^C~jDyitjE2Rl1rfy6)%TPI|p5xbn?kb=_V-P~gANv!vFMmhSvW zNN{{TfDBipS(db!+?M+8`ohWmmnR-CQ>FNWlJPNdyA2)l`;aM5*Pe$capy@K?G5qy zm}?<_GZ@4;Evd#F8LppDojnyLz0t<9-tC`hQVM+8xG>}$od5E{M{)FppbKY`;vvo; zz%`GQ6p6PZNJw9IS_H3)kG-JpK5MrKF$rcMG0fllSle`=+@GBEg0cTC8;ar^!1#4P z`Q>ZEK6JI~LlDf+m-awvuAlJB-C~H{jlDG&yK_@DfM10kc@0S~0gEL!^s_3IqJxyh z*v+}kOI`M+{KnMYNQR~mw7#$4efo6@`wYpi;yPREACzE9+y3^)6s4F!wCe7@wf9M# zUvDAZN$;AA&>*X}qr<^sNkXI~2D4$`>XC525!*7z=*2 zFnDKvOSDG5`oejIOXx*LZRmN>+dacA^&q?>q8$^0b`4CkMcFSk)CHxVIwN-?m0AE7 z)qW3vEbIkCYPvgdH+kaHs+oVJ6a&OGp`w@G%5FS!Q}!QpGVZ0{$LOaKL{<~nt{d)- zQ-k>34@4r3JC@HcAL?w$VK)f0S;@yu=;1Xii5E8(?oK^A~nGCsHZXe&VS(cNbJTq^XJ zz4i1;gC$i2LGcZG93q>5xMIx*5r$kY)^8)XEZhGx5^;>|PzcbZA?S+9^}q$xoU%Fb zj?UX1DemHeMVnmDUKE_EH>`3QZ8~d^UMHEMywXIS zWfy0ynJu%N?d3f$4G}Psd10;&DriIK_?IWS3@jw|X?ug8Lhvem!+~#A@1>UZPp4(7iu|eiY_F-(2@Y=3! zG)G#`AEmnIO}A|v-<17)!dN#^^Hq_b@?Al5;`IxGRXFdtxq;;H!7{*g)Y%388&h{q zW~nErU-!Am&bnWAzet_E_Csp9km02L#s#rT_y~13qun>HOU}n@W-HC_nEdb0;=G2T z&O)j*Jgmto7VHHt)gU%a9n9_7F7HEf;$4y6`$EU=NY}_w)dD^X(SkgN&K8o%I4C=# zV)u?9>b;UZh}3J#3E7fKeJ6+*J^M@It*xzE`@5$gL+}*3y5j${jmc!Y-zGEnY> zpqzJIl#BhoX0x`@&U;hy0)(!N-!hq0F3KGD1^xmNd+CAXwn0LR=Zh36?V*N?gn;sA zq4>x`VtdC;(FK23m-n+25C^SuX}|#`u~1IB)#crhS=a8(_-*p>aL3tEe6^I`cArsy z!0=6C7E)ePiQxVaz8fGBu^6LvUt-mL-gb49aqj8bB%I6;^`*p8)afTt*07Ur>TyQm zm4Zbzb$qu3?d8GA1s4XybUcNV?dVf)`Mk#jV;z%P&lX0HJh|{~)~6$Zk@_MdBYjjz z>g9ulb`KK<_aYw5$ynQ-s)_hrCD;#7;8>rGD^*#St!5);%ZFL3jQ(6d78Gly{;Wr7PM?=H;XP~$QyRHL+ zunZE*G*bISuk%p+?t+-=jn`sSmI9AL{y0Ah)mteW!;!_WfP31i&T<7*vo#7HQ+Nm} zAbse)Ngj#4yg*|f7!&Wz$;Kh$ukm;0dy1e?;o2*#j68ysZ0ot49LymT{TpLA@ zG`O_~BRlcdmr+{wp7@gOfX)SKQKybZPXc$g|HP`D#Oa;C0hL;pj0rmq4(QcUenC8e z)r66EQkayUJEJS&bW3-%EvRo2C$tARAtT)}-b?jdk{jO*Ns2||HL|0m*E}Z!8 zS!)>jHaV6C>2BnsN#}Tlhg6-l(pffnnsaA%m7SgR*il|@grC**q*8kKP$iv z)kw%sk3%CXc3ASv z&S{u4qy09*1A|Kp&J30zhKV7eO1m`#<#I=Xb9fF|fn&bSB%b`P46o}ldq__JSJ;iV ziTY9Y>XoEbS<%w{Z(6I$i76e!*;AQoAo-lQ2q1`JM+p?jXNZe zwnt*$n4`so;tgLL;|h*916Ya~{?dGjTu1CPU8&Hqyku*0uFmLyI8?(6{aTyEa_iz_ z>uo{Nz?92|t=qbOLMzYZrz3&IIeJw7X$3hWC$+ErV%QjGAde$|-?L{r3m6uHO zU}?HpdR;#zddX(v;IdEYDjil>Oy{q$EvL%{*S)4?x|j^OK&n-TpSOOrXdV)_z0Z@; zXuZ0c5-nM;@F-{!PmD(1nsY3!pzWqg3%GNzcCN-A&;#n7uYFF>v*0}k#`ti zqANjUdQ!*}1uE!?5Wvs4E*<=}{qluObi99Zt9A7IyJ0Xtj4ZJFI&*0m@obV<7sJi% zsnVwP%?8Wc5hlJ1BfMcow3+SpA@gF~f=h)N*_P!_KUA9gH@;2$V#*7&gd-nbUMc{y z3sjL+k+qZrXZ)KE8`ro;<+snD?Lj6;Nek~fjQ>^=JKK=Yr1*0Kv$qg`TTDP{Uk2-R z&D*a@_H>@ObkInOzS?((`&b8ArBVxMM%;im%l0$YWygOKsl`-z&gsyX+Z+o-VW=zU zy(sHRzQx$`G!Ri*e!Y)=<^LmkXBBpvh&1;uQe@IVXoTZ;}HSIrdivIRz z+l>UCw91x&{nvn-cU*oquQxrKGz_C~LBHM|e+cqU6NjBI9y^oAKrXpNev8j*8gB{< zX1Jlh@$t1|Geq@)fIjH86j2;$kp1V-{j?PGoA*eUuA949=7*VTzNOlb(00Oc&dVqX z@JJPPHV026ZrTjIpmND29kY`Gi6+RbSbsDQ2br#O?HO5bs@#hZ32|Du-R{(0x3=VV z{zWv}Bl;3)j}2^1_(0~=%*zbP-z`toqOCeBD?PYyt=*Nh^zvaXX)e{&+{w$JM9D2> z2x?p7#psKeZ~M$&YR!V|!%H!xM*CudC{E6$rIg8q`wbwWwB;gxOj{ueMzA?pW{&)3Yv{CL}PGIyM~7 zzThOIZ+cAoxb_SWAQ-Sx3bF{u(zCyQb?fEM91Ih3=dL~Dc7)t(yQ!dW@T@Dd@@9L- z#&lgcr#IVGLLH*0gNxrJUT zd()Frlos;ydO`e=xMNO@^+@K=!CB%n6bpgnQ8L>}vLEcU-Vd zaAoTqw=P0P80lKqL=ZaqYBoJ>wz|w|u5_n-gf zsJX>v)#8>^qLiXTUth@H&nhf*CVVi@94h5T_IIwZiQ~@`me7;|eC(A+C4L6O5}*6X=GlEi64cZ&=wA~Ns!?#ThNc{m2AdxNaGK7^fdbvQ}(>`IzJM5cKs7?s% z!o7B$6;qa2;4N*j&w;lT`aAa7ZE9}A=R;z0d1_JAJicRos}up6p1)szMBKu9cn?P> zQx6N$SC=G&{7k~L)_J%LjwkWq?bQ$YhCi;w6#HP|S*{bg=%8 z{pcds`^i<^>Veuw|1;0NGXFcwuy?+3kDL~*p5Cb=_3i8)B(T9suvBk~Ys2Z6gC8-i z3Z5TFIxnd7NGjOK$$w7a(0AyA^Ti6$hO@>&WJOE7m)@7Rklp3)`_Zy;eYJ0XvMNQB zuaF<}rzsjF6o)WI>%y+hd!dg4f)E>H*xb?+8e6sfq6Mw9D4_y{vV}of=t~GuO*2T5 z2ufcvl?-A7)00m6O+?&d0v)23CxS|5HSLJL@eP>$a#o|=VtXA+*P8fXM{VfCd~lV} zj_>=?n9$343_NBxOfzjMoV#t?9l|u#(mO4{42uVlitI;y)m$1iHm`0PEFDhu|o^^Aw6x^sU*xE>Sl@sPgklB(Kr@% zLA0O(m2Yh;hlVKMK3qR}3HR9AxsJ_zRfqX#nsuy1Wg}tFt9YDhi5t1+Ou+8L=N$=#M+pVS1bX?j!nvGeCwi2f|Y)Q?`;IE!3JE z#2)!Tk*{SF8--UIUsn(^9Nv zp3xuR_;EvD+5!R*A)76;F?#Lt%HCx*?<&(|)?3k)*vzF^oxFH%sabQz-?dhtbQ-Vz zmU=X&*uK=B3PxF(UvDay^&oD;gHv|x;S`_-dOHO;;(KoZ#gkNW3#qn;K-&7f(Ef?-T5y)U{3OhZQ_ZR6Blm zH1F-ifJ^0xWRB6=`&XOQY5OP>=X|SV!Jw+$5{{ab5)Mf}zlE`5Q9;c%+p*24s!g;4 z5~t0K3i3$8_u&-^PvT;CEe=`2An@babvXWvKgr+wx>e-poVw_2=T;E@c(M-;7}6zw zl7ntwzi)22+}!37RdfnN|vtFQ~hJ&pLR3%%9RgUV)SR2ZPokmZ)&HpN{_Mg zK|v2Rvlt4u9RFG z7dsrc;7rlxr%6xosZ7{k?t}5UnH+@6DIZ!qUU@c>gde_|gzvKC6$04H3gne3wVA8j zmr@WcSg?k}WA_y{N>eaG?2!lK8p?qmvoz&~kB+!6>Jyhr`?p$%3B=->3!7XfYm*fL zYJP5~)5Wn5KeQ9+O;2;grSg>Mi>ASmyPpG*d={A8XH`kJ-E(Zy1a?owxb)@>VO+7E zXl7Zvn9;|Co~o)aIh=3#&u@IJ+ALrO()Nqg0P8*Lx!>K~3mop$@LOMsLB4APXh^Y= z3h@daghYE#p&9=VD|W-TvP^-$5j_dpN&qWdK-M>sR5iZ3RRl~^OW3@dU7+8pt?8)M!O*o7 zZ5d%%Cc~KPD<{~;0@JE6$)iODdG2uF^Qj)i^4rs?R6-3lx_d znQI=IY%y4?J)`3wLv7+!b}ZB9sk*0imda~!$XBj%Xwl@4f`^CS8JU@xA@dj6eH-Y; zdnNc234SK`E`J-q7?|j;TfSrC@h?Cqrk`W>c@4iTJQ6(iET1s>QSEMFE8mEbKETZR zdoSi>Sm+)pU6h8o{QBCqF1n`OVS?e?Y2-2JGlSfbdDs_|Kk1)89$#tkRU6gyvaCF! zZx#PMJr1CR#l~(-ZGbit3cd@UMlskP--p||bME=jNX+e(!-lK-(%^Nq6%n?v=_et

    <30=+{lqTc|dgB zkq_Off|bufaYocIqPqWzQ9Z0YF*t+qfl`9DOYW^`;DS+BQkm>d7?(Q6-4T8H_3!27 z?}?U0Aa&o`!xGfOi(>TsowHsyVeZMHdf!gw@VjQh;hb}nw70w*IPwBN|2}T|@gy{# zbh}iKYj1r&DKdZ5|6KvqbjmC6=KRc}Oic@C2sqa`b@N32(`2p|>+m!nZX2qHd>ap7 zlvPOmhw_=Mc;ZZhj?vJJPJUHc5K&lAz@U?2v|4BJ}t z1;u0YPg1>fzVm0BG^U#UGALsGlF--f#sw)Ye;q9W=Q0WsPi`IC?D37N);0&%W`YTT zgyPB>tFX-q$Qh*>MpbaSHJcV$U7J}Cs+ni8rvpX|{!Y-4&t3DdHYd{n&zhKBW0tX# zP7ZZ#Oq&z%oKsn(Mz{ZQp-Ce#PsFzrsT5o9lp@Qljf*!p>RFl_mUE*53(>R45u1s? zBz!{7P{rv({3R8L)CZF^qgCIlbq72)bI&TdjBM(vbOq)OVXaUc=M>Gml+ybMwIX4cA>qb!xAQ z=o?$-TP69Lm9#uNZcb?4IW$(%P57XK9RCDt(T1<`#F?)z2o;3g?F*ua@77=SEJb>z zG}X&fsOH#vHBKOm{SAuIbvlc=EgaGoIkuo$@*=&)SPg_f(c$KsFa%i(u^2sRV-`j&`>hnr-tSu2sUKQ23*_?39`aH0FzpQ&af*w$4}s;kH^#E| z`pff5>Z|XsJuZ8FiqbU}?ynQ<>+4d;Zz*O%4RU>s6|JUjN$!RGkZ&}-n?`c~*i&lM zSJKYNywx%hn+w`Y^;r9i3&43^fSy}<#O}0dl)bs`JevS!Af}3%N*egHfHm8`nVUBqMWbYTWXwB(1`;X3uu3VjaCev0DVD=ktX;eYk zb#tMrCAMauY8_@b&&6J^qG37=hAOHxwnhyFmyz=8O>aLClmYfb?rV`Z6 zwe03o{BH2zBy_&FyfZiOn+;#{6&!bD>94Dy&bFvK)N{ICuH=*3VmsbK=T39uAGDdP zZr<&6s!KSQz?~v}YVbU|8abZST$TS%BWP3_ky4yDXl5?z1`unF3(HHtRy>)SRMckL zsZ|i(lD=z^7r=p+U%S`*iVsI|inN{b`QT$#B5zZycoLPYr7-|T<)(Khw_KDfz ztDUff3tKKmU&5mCSRX(DT%s??_EH~y?IAv&={4uhRXrq?L~Nf?#pEAt%mB>vPLD^i zK&hFg_+Ik#d|hNY)LT`LRFOiqxn$p!5hZM0Rwb195NCp|Yf9LnLiyJx`}f#e1BA$H z;V8>*dh^iJz{sv}G?nK@^#vwm;JWYe1>4_Ss^u9m9SRlb4Q7KSSEjU0)*62|b6)W*7P!Wfy5(8^s?u7@GD5HneV%&y{>bf%#W`PhfU@#~~^+_E@*9}yiUFH=DDrIvJ)IKxNJhYgV z=udmFpL0@~wF__ZOc7L{Ry9538ou1uxRUG+;HGZk<3nJy?Ee@oHuLTp!%+D%ADwfQ z_Ni%Y!gWZdOdlFYd|uahx1T+M?4q4r_Gd+aMPVPwf1U^=mTGK#ed-X9fxz0 zD4pxFxo#f;!?6|+hfG_z(Ec(bvi_KN{D7TDyX0lgC+iD#|WgK__ zkzg@yD8cKoCX}ZnUvq^iIsEPJFJ)O&Tei+H+$FuIJ%L10XTKXa+Vme(^3gE?h>vE7 zY9g;rISrKR>kGUubUY8DjMJRuz=N)WF%_(rf!mLy8dGdbmt2)a&4iv4Aemf0bwI!O zsQf1Y(>@ced?jk>HqYm|R4`im3d5~uo-a!CS-PTccExQxQObhH`NybTmRl+V#>S{} zsDeuPtMG$)i9H^gePI!cw6Tgp=%LES*2794RE5dJ>`9VnU&bp;tc3HLbg!}S9;(e^ z-Lnx>p~k=<+M6)8_rsh=7!KkMfyHB37s48kP0{-HoV+^Gsyy-Lij zf1srTZNm;EoTVy|z`#T3Zg1mz$GE2GaVZ!;SNln`?H+HOOn%&efE`Q!2%}uqEEq zvSMK@%#dkA)b^4@Y-#R)J-}?a^h@c=0UzvZxnaIl6=4(^T(S_KF?BS}PvL?+gOp)- zAZE$_DamT7-INAd5ki8fnB@{xmVfzgR-Y{eeceN{L=IhIhJCF5Ou!SKCZ_P*WG@9C ztUWS26UaK{#pM6Oc$xwRR-4|}ty|yGgkEPDgzcyvYsyodlFWiqxY|ZiwSV8%x z#GFk5yq0^)^Kba@lFD9-ZY=kx>*zyyn2K?{!fXOeH@m4$yL3okb4Wu@?*2_-#|{&_ z(eY;xrE7yGh<^-<&BAWYl?(#FQ<6Eb_=w=`Y247f#Ks^k-D(sU7vxbTa<%S*nTC`7(5n$UHoxX; zdj1B@rsCNKn}I_H#m2?H0V$yUHypUpiwcQ;YSih4qn=g6TS~*;#ybruE4nq*Em{G# zTvptfr>c&+Gn#rie4$!_P7>yyb55K=*rIhFdEL?34CJx-QLA0qZ>E?(Vo#-6cl>!; zz`oA3d@k;|rmV+?9aUUw<(s>Sx3lbrL67{M0yhFpRhNqFSz3~rxevkqaL1pxa24Lg z`XZKE2%7W;oK8NcI5D+dgzoQFB+lNIrsM}xgMyfJ`nz+NhYI3)erBKu7!wVJEm&dh zw9B|hU!ol8Ni8srapkF;c~>t>ubRs;ksJu;)YHhB=<4G|d**KSyy{oDn;`A&uIaLW zkfY`3(vs{CEZ2pi23YFsa3(b;z~S2D8Y1)SixYO*NY}^ z@~GNkLX`*WGuoqA^XBg*!$TG+6ds#|=ZJA(nEZz@HdYp6VcWD0_B( za??9zB;jM80=8LeJ@IBH@5K3fAAYwWB3#KfZST!WrGE8<(N=~_(*q?g<_Xs~xKlB} zV|{C%Jsh9T8U6lc`d~L8IOgQ(vsL}Ohk?&WkM>HJ6;-hAF=;NeP34?Si}{&0jn6CLJEgC`uSbm^C3T+1tFO2jHE^`$Df^rDt{A=!FO zmB3lbH_RS zu-lD^!_%pm6ciD0oZgrs!x4{w zE0ng5|L7Vtw&snq4((W~?8CF{Qwg1y#$|4z^KS3@_|Q)iqS+ufSM1dgG|jiffpb>YV&mwJ@ zbiLDTx*^QT4EZvAw6kVN+9cIY#0lBE6enYzS}pgv9&DH)*M`&UUeM%P~u(7eJ79aPX&+<`=H)ZpRxy_n{HgCz**laCEvb9;h{JfbHb}6vFUNmAOU%$Ls;#a3G?0{Ob-y1lVZe zTx>gU;W6;m%s}M61w)q`>+nYp-dhBVIcGR@QGaa`EmOse`W8M16o9f-L4rotI2Li6 z)pF!FLEi^Qj3SS>Wr`%d=O%gWv(OLcOt3DTZN7J^Ydl^un^c#AqbweAsjIKoEY8jR z^*TKd-afwhp9jPrf$54DRc<`dUiZww$5}P1=nB42tqbjqw)#XJZ~dbT{nl-_1!~*p zV{22MfUgVBhfWOBG6U_gLH3rd-H`OL1M)5*lLX$GY*8zBBn-9b2|^wQ{JR74A>h!y ztGBJ6V<-cOF@0*xx%n#2II6d_Zmsc&oQnPUW4rMNHs5PByt;}A!pZ6?R4saM##x@A zI?Xn7$61G4e13w)6H2fi%(adoXn}HaSFa78jDmGPZ$&7}J=I;j`Q-fD^B*PP9ij7v zBm9Ve0H##^zkbql`A`Q8bWHFjh3#Mej`8!8ZFw(odDHM1>kf(C*Cu^4>c9a|hY-4( zL{tFdBOE+Ae(!=FZ_K62qW ze&OYCZrR736_A@0+iUN@H#v1$m zZwa&h6q!e*)pXtlnfCkJO>YIoht_LI{QhLV%H5Ar11<6SGX^9Yz~hd!ugy^lx*E)> zSFu1iDgzuC3P=A(NdYpJKUh}#i(4X&!nfCG|B4d00c+vEH<;0;xxtg?TnBkvA7gQ= z+HXZlRAOLiHl}dE2NgdMT!>{Js`{sNjsIysFuQJM@qfHL3EC$9_kT{19+eLzlTJ{FMW%MTNs!!?~Jdxv~pECJdsqy{q?s-=LH9WpF_0in1=XaFjDT{r{-*}`3Dyis9YO~>n=k+W^NSJRZ*ekb z2N|~MfeoMeM{y_n&O!SJvnCpddsW3b62sgGtv?+T6r`f@0 zbp{a;J(I2wRU7&9O-Mbc5nL{MinEC8na3Y^KV}Z{Rh!>O3s%g_Fvr2oXD=^EcjEmh z@Xo3yWJC*+^Pby?xw$!n1KEe)BZZmAbkVmETAnC$xZ`}&)khDR z{=dE`iW9z?R>0A4dg%WklSaZRy`XHPNj$6q?Ca!F~Hhr5zpKWI&Au8A+M2j-XP zTV5q$i6Z&IvIB3~q$bqFTU}4Wn6W`~4{tYRO zPRB6^yNBa#tx%NsE^v*K=M?3Qy-+`g^A1W#w z($C|5c4dr;A;+zD&QsjaaZ1w3etx{Jv(M-n+mD1NM2Nr6dg5lL*+JEb#7lU7e$ik} zxgv+r67|c*)w2}CYd4bwo{iAyU?hFb>I!=cl9*Hs**+5m+{W*%QJ27oNvpQ2m zw^+~6smMv9m`|9cx(zxq%>62o zM|VwNmO?yRJ*HT5rkv9ep;mleR-!fy5tW}w`1YtKBu1n0NK%=a##7JC0V8FBk$XV6ZN zPul_5sRn&8S+al%Jw5pWKVdxbJM__@u4g`iA!bTs*nD~&Ro8@5MvZD>hwYKa*NN;G z;e>0TrG1y@euU!Z(5)MOSVU=j`11Hq*27{m#c~lRHotzY$CS^4{chtiV^d8xcUXvs zHcO{2&oMUY(8p!LtfacO%a-%7o}*=3>-EHhRwbMwwz+$A?uSr&3VNgQmC9mTuBqGB zOtK@%LK~s14+!nWAC~&2=qzET#mLMe3WeL`x-0NfJ4;)h``Xp2VuRy84dqj*xO zdNL$)lZfbGZI_~@KkNWXc9gW2(z8;}=3ySS{CT|g#}BDVNvEwq7_>Uw7^^p8P5ed` zn2e=W6lm)Yn=WKq`n!5ZKA5e0Xp~X_o!Y9ZRYlQWZvfY9%5XijlOebbjNt6bG97?J z!4odt5$C%o5>>b!Qr@tMRDbCptg;*_K^*LSZZ8P)l2Baa-zt=3L=%(*laZ{E1LG9z zP4vkF>}C#*>uX7D^v^Iq26bq3#)~ovI3&hg8-vW|0LKf+v3#~)m*74q+&?JpB>e!p zWs=K76s>$RbUqXs(;?eVQk_FH6UyV`Btd1+N&f!(ukGi#g*n7k`-D?dv}Wd7)y2tz zk8k1o3B&P8tO?K0TdK78Z+mXAxtQGZBl;w=gMUo0`akIEn{&v&xso11rMmb$iku8oNIGDedx&;xT~DXm#%BpAR~ zfC9$9tsbzE&lZ2z?js3&;}?~h&Y0{rn7_ekc5kbxFUl)n9ukWWM`(3se7eHhWBe ztPLkjoa`bOP>~$zJVVXT5CMYnw-c!=T_jj`~Jt zqG&ZnuBA4xV@w^>=0b9GlIuJXZJL;VcL188gSbc`qwHD4Dyx5KfVGwBRNqXD(k)P(1 zpY?B4S*|!%1=J*k?HWEa*0HNja-XA%y)T-N9)HZYf9$p&K>9oLz(U~!zVaB(!}{>{G2yxV%6r_=@Zx)$RRZuilHw%W5mqCXX3 zVh_$>>}U7{0JH5==^oqIln+UdmBPk7W{iV)JX)&){5T#D;l*R(ACkZVXwEqV0@4sFDq@_sa#%H#@7U{8Bt4vUZ=cb&N8d+r zQ+2Hlg$zvyP~4P_+Uhp~O=}*GKi;4KR}zds5W1TnOu#~-HT!Bgl9yGsQ3|d^?NaBM zr7GdAc|U?A7?2NO#5_j-)8pocLjKnjHk$tN>RbKv%`b)rz+0De6pjI}Q2bx=p)6<0 zl2f;u7%m*U`u}oR4=}0zd-(u-KdrGKQs zPoF>k{PXVG=%?>%`=)Nb{_MuTfSJ{AwQR*0+>CE+J`h)H3Dr7Ba8K`=$3OLScxI%P;N%yK1?r3KxtC12x#}&jl(tf?unw>ay(r?&u!H?Pu##}ll-(oF?Hid> zDaUX@93*l;a9YL-5C6sG+payx^-SVAu=@4O$OTI;-U2pwZH=40Cw=Djy;gsITb$FR zqI;iiNaaSpzptHKd*@eF(s8B(t6#i~R0xabGXxer=N30_Z`>_B3o4nfWko9xtak)%kV9!3ilkMJ2Jx)+8B^x$vcUYsm<@rU;>bGXKLJXJg ze2oN(OZ4;IV_K}{p!xP(WE>+y+|?C@g;&aev36VMB1j(to|gEnnv=JHtI}oy1HeiF z6w^IVck|ujm$&=#=jrL``)mLG`Puc2fzz($$A`~Xb3x6#_J5%CffXFk{%JqMQYYx> RW8plI0#8>zmvv4FO#p%YWn%yU diff --git a/DOCS/html/stm32f4xx__matlab__conf_8h__incl.map b/DOCS/html/stm32f4xx__matlab__conf_8h__incl.map index b2906d4..5c43c35 100644 --- a/DOCS/html/stm32f4xx__matlab__conf_8h__incl.map +++ b/DOCS/html/stm32f4xx__matlab__conf_8h__incl.map @@ -1,12 +1,12 @@ - - + + - + - + - + diff --git a/DOCS/html/stm32f4xx__matlab__conf_8h__incl.md5 b/DOCS/html/stm32f4xx__matlab__conf_8h__incl.md5 index 4020a09..b8232ea 100644 --- a/DOCS/html/stm32f4xx__matlab__conf_8h__incl.md5 +++ b/DOCS/html/stm32f4xx__matlab__conf_8h__incl.md5 @@ -1 +1 @@ -b5de47f69cfce3b110907fc4ff8cd2ca \ No newline at end of file +23d28cbca03fbde3a7b3702220258ee1 \ No newline at end of file diff --git a/DOCS/html/stm32f4xx__matlab__conf_8h_aff389f4df35953d82d9d30ae161a8cf9_cgraph.map b/DOCS/html/stm32f4xx__matlab__conf_8h_aff389f4df35953d82d9d30ae161a8cf9_cgraph.map new file mode 100644 index 0000000..769aa90 --- /dev/null +++ b/DOCS/html/stm32f4xx__matlab__conf_8h_aff389f4df35953d82d9d30ae161a8cf9_cgraph.map @@ -0,0 +1,5 @@ + + + + + diff --git a/DOCS/html/stm32f4xx__matlab__conf_8h_aff389f4df35953d82d9d30ae161a8cf9_cgraph.md5 b/DOCS/html/stm32f4xx__matlab__conf_8h_aff389f4df35953d82d9d30ae161a8cf9_cgraph.md5 new file mode 100644 index 0000000..b617db3 --- /dev/null +++ b/DOCS/html/stm32f4xx__matlab__conf_8h_aff389f4df35953d82d9d30ae161a8cf9_cgraph.md5 @@ -0,0 +1 @@ +27a35ea2023ea399c59ddc0ffc847116 \ No newline at end of file diff --git a/DOCS/html/stm32f4xx__matlab__conf_8h_aff389f4df35953d82d9d30ae161a8cf9_cgraph.png b/DOCS/html/stm32f4xx__matlab__conf_8h_aff389f4df35953d82d9d30ae161a8cf9_cgraph.png new file mode 100644 index 0000000000000000000000000000000000000000..348cac4b60b67a741e14f708e2f3596f52658a60 GIT binary patch literal 1304 zcmV+z1?T#SP)qj(Qdboi^$0k$ZM8A}lU0hE9WO7RT|}|Gy?cE<{8}9*Zjxkq0cUL_{92xDpY0 zz~V|o(#J17xcE^5I8P8?AyuL;G`aWhMwfcIgwV_we zf2-c_r4o_cuXLMipGjj@iC;99tJss`7PYfIK1J=y#Hk|pKG&v+7DM@DTS}ef_c3*S9Wg>XRW78WoQ;mxU=*?4!!b%r(7q z99JZYmh_Xx%C?Q;xNwYV*YH`dv-B9+2Koj1V^V0&^52;Q6s_~m* z+;NyDzoNFb-zyt0TP(}Ose0^_)0f|Ay}lge0VunR^BLPF$HS_YbFOtS6K&%aUDUBrcJ|jqL1v)a-+zT?U%gyU zuna*2;MBx+ie$Kz0N6AJH_d%~jr)H`9<%diRK%Jx+jF5Qv)5XRYn`*naZ6;IerZ1Q zZ^}%&3Cno%%f_AF+pm2QB6hp4FKAA2Re=hyufQ=;`~<;jl3?|d)AHx2O{deTE!QfV zP;_QR?Y~4&=S;r&N+=b$O2##NUMNV8@k`L2`wQeD2X0BuVdLQF1 zz}3yk%(dt|tIdUyGV*3x>3C(&|BkyNpT4)#NB&jE&c09Ax!B}%=qctP!`rbG+akE3 zz}m`^+zXwWD|tnyu0oxSofp^kf>yR|$O3yHauh{pMdTJAmfc)USi-wD7!07Q=X$+f zkiSIG?(0XYI0L~=W3bkHNq(NDf2Y$?J}i4S4Ih@h-s|?>mY47*M0i4y zoM3UaRCKzbiL=VXmT%pbm*kJoIk-@?4EDYB4;j0OSX?cIEJ#g!HUTw5$Rak21+)ks zIY>n00gEdUkq0cUL_{92xDpY0kb6OEdwaXiJctgxt*tE#27}OPP|bFBcE;{MP+W~M zyGfF)@9ph*Pl_nb7_%EX2V1JT&I!rvGRE8vodXdO5fKp)5fKs5QT8wVD30z3=Ar8V O0000 + @@ -83,128 +84,180 @@ $(function() { codefold.init(0); });

    stm32f4xx_matlab_conf.h
    -Go to the documentation of this file.
    1/**************************************************************************
    -
    2Данный файл необходим Ð´Ð»Ñ Ð¾Ð¿Ñ€ÐµÐ´ÐµÐ»ÐµÐ½Ð¸Ñ, какую периферию наобходимо будет
    -
    3Ñимулировать.
    -
    4
    -
    5**************************************************************************/
    -
    6#ifndef _MATLAB_CONF_H_
    -
    7#define _MATLAB_CONF_H_
    -
    29// DEFINES (UNCOMMENT WHAT YOU WILL SIMULATE)
    -
    30// TIMS
    -
    31#define USE_TIM1
    -
    32//#define USE_TIM2
    -
    33#define USE_TIM3
    -
    34#define USE_TIM4
    -
    35//#define USE_TIM5
    -
    36//#define USE_TIM6
    -
    37#define USE_TIM7
    -
    38//#define USE_TIM8
    -
    39//#define USE_TIM9
    -
    40//#define USE_TIM10
    -
    41//#define USE_TIM11
    -
    42#define USE_TIM12
    -
    43//#define USE_TIM13
    -
    44//#define USE_TIM14
    +Go to the documentation of this file.
    1/**
    +
    2**************************************************************************
    +
    3* @dir ../MCU_STM32F4xx_Matlab
    +
    4* @brief <b>
    +
    5* Папка Ñ Ð¸Ñходным кодом Ð´Ð»Ñ ÑимулÑции МК. </b>
    +
    6**************************************************************************
    +
    7@details
    +
    8Ð’ данной папке ÑодержатьÑÑ Ð¼Ð¾Ð´ÑƒÐ»Ð¸ Ð´Ð»Ñ ÑимулÑции МК в MATLAB:
    +
    9- Драйверы МК - они переделаны так, чтобы запуÑкатьÑÑ Ð¸ работать в MATLAB.
    +
    10- СимулÑтор МК - он моделирует работу нужной периферии в MATLAB
    +
    11**************************************************************************/
    +
    12
    +
    13
    +
    14/**
    +
    15**************************************************************************
    +
    16* @file stm32f4xx_matlab_conf.h
    +
    17* @brief Заголовочный файл Ð´Ð»Ñ ÐºÐ¾Ð½Ñ„Ð¸Ð³ÑƒÑ€Ð°Ñ†Ð¸Ð¸ ÑимулÑтора МК.
    +
    18**************************************************************************
    +
    19@details
    +
    20ЗдеÑÑŒ задаётÑÑ Ð¸ÑÐ¿Ð¾Ð»ÑŒÐ·ÑƒÐµÐ¼Ð°Ñ Ð¿ÐµÑ€Ð¸Ñ„ÐµÑ€Ð¸Ñ Ð¸ подключаютÑÑ Ð±Ð¸Ð±Ð»Ð¸Ð¾Ñ‚ÐµÐºÐ¸ Ð´Ð»Ñ Ð¿ÐµÑ€Ð¸Ñ„ÐµÑ€Ð¸Ð¸.
    +
    21**************************************************************************/
    +
    22
    +
    23#ifndef _MATLAB_CONF_H_
    +
    24#define _MATLAB_CONF_H_
    +
    25/**
    +
    26 * @addtogroup STM_SIMULATION STM32 Simulation
    +
    27 * @brief Ð’ÑÑкое Ð´Ð»Ñ ÑимулÑции STM32
    +
    28 */
    +
    29
    +
    30/**
    +
    31 * @addtogroup MAIN_SIMULATOR STM32 Simulator
    +
    32 * @ingroup STM_SIMULATION
    +
    33 * @brief Ð’ÑÑкое Ð´Ð»Ñ ÑимулÑтора STM32
    +
    34 * @details ЗдеÑÑŒ дефайнами задаетÑÑ Ð¸ÑÐ¿Ð¾Ð»ÑŒÐ·ÑƒÐµÐ¼Ð°Ñ Ð¿ÐµÑ€Ð¸Ñ„ÐµÑ€Ð¸Ñ Ð¸
    +
    35 подключаютÑÑ Ñ„Ð°Ð¹Ð»Ñ‹, необходимые Ð´Ð»Ñ ÐµÑ‘ ÑимулÑции
    +
    36 */
    +
    37
    +
    38/**
    +
    39 * @addtogroup SIMULATOR_CONF Simulator Configuration
    +
    40 * @ingroup MAIN_SIMULATOR
    +
    41 * @brief Параметры конфигурации Ð´Ð»Ñ ÑимулÑтора МК
    +
    42 * @details ЗдеÑÑŒ дефайнами задаетÑÑ Ð¿ÐµÑ€Ð¸Ñ„ÐµÑ€Ð¸Ñ Ð´Ð»Ñ ÑимулÑции
    +
    43 * @{
    +
    44 */
    45
    -
    46// TIM'S HANDLERS
    -
    47//#define USE_TIM1_UP_TIM10_HANDLER
    -
    48//#define USE_TIM2_HANDLER
    -
    49//#define USE_TIM3_HANDLER
    -
    50#define USE_TIM4_HANDLER
    -
    51//#define USE_TIM5_HANDLER
    -
    52//#define USE_TIM6_HANDLER
    -
    53#define USE_TIM7_HANDLER
    -
    54//#define USE_TIM8_UP_TIM13_HANDLER
    -
    55//#define USE_TIM1_BRK_TIM9_HANDLER
    -
    56//#define USE_TIM1_TRG_COM_TIM11_HANDLER
    -
    57#define USE_TIM8_BRK_TIM12_HANDLER
    -
    58//#define USE_TIM8_TRG_COM_TIM14_HANDLER
    -
    59
    -
    60
    -
    73//-----------------------------------------------------------------------//
    -
    74/*------------------------------FUNCTIONS--------------------------------*/
    -
    75// MCU PERIPH INIT
    -
    76void Initialize_Periph_Sim(void);
    -
    77// MCU PERIPH DEINIT
    -
    78void deInitialize_Periph_Sim(void);
    -
    79// MCU DEINIT
    -
    80void deInitialize_MCU(void);
    +
    46// DEFINES (UNCOMMENT WHAT YOU WILL SIMULATE)
    +
    47// TIMS
    +
    48#define USE_TIM1
    +
    49//#define USE_TIM2
    +
    50#define USE_TIM3
    +
    51#define USE_TIM4
    +
    52//#define USE_TIM5
    +
    53//#define USE_TIM6
    +
    54#define USE_TIM7
    +
    55//#define USE_TIM8
    +
    56//#define USE_TIM9
    +
    57//#define USE_TIM10
    +
    58//#define USE_TIM11
    +
    59#define USE_TIM12
    +
    60//#define USE_TIM13
    +
    61//#define USE_TIM14
    +
    62
    +
    63// TIM'S HANDLERS
    +
    64//#define USE_TIM1_UP_TIM10_HANDLER
    +
    65//#define USE_TIM2_HANDLER
    +
    66//#define USE_TIM3_HANDLER
    +
    67#define USE_TIM4_HANDLER
    +
    68//#define USE_TIM5_HANDLER
    +
    69//#define USE_TIM6_HANDLER
    +
    70#define USE_TIM7_HANDLER
    +
    71//#define USE_TIM8_UP_TIM13_HANDLER
    +
    72//#define USE_TIM1_BRK_TIM9_HANDLER
    +
    73//#define USE_TIM1_TRG_COM_TIM11_HANDLER
    +
    74#define USE_TIM8_BRK_TIM12_HANDLER
    +
    75//#define USE_TIM8_TRG_COM_TIM14_HANDLER
    +
    76
    +
    77
    +
    78/** SIMULATOR_CONF
    +
    79 * @}
    +
    80 */
    81
    -
    82
    -
    83#include "stm32f4xx_matlab_rcc.h"
    -
    84#include "stm32f4xx_matlab_gpio.h"
    -
    85
    -
    86
    -
    87//-----------------------------------------------------------------------//
    -
    88/*-------------------------------TIMERS----------------------------------*/
    -
    89//#if defined(USE_TIM1) || defined(USE_TIM2) || defined(USE_TIM3) || defined(USE_TIM4) || defined(USE_TIM5) || \
    -
    90// defined(USE_TIM6) || defined(USE_TIM7) || defined(USE_TIM8) || defined(USE_TIM9) || defined(USE_TIM10) || \
    -
    91// defined(USE_TIM11) || defined(USE_TIM12) || defined(USE_TIM13) || defined(USE_TIM14)
    -
    92#include "stm32f4xx_matlab_tim.h"
    -
    93
    -
    94// Init timersfor simulation
    -
    95void Init_TIM_SIM(void);
    +
    82
    +
    83/**
    +
    84* @ingroup MAIN_SIMULATOR
    +
    85* @{
    +
    86*/
    +
    87
    +
    88//-----------------------------------------------------------------------//
    +
    89/*------------------------------FUNCTIONS--------------------------------*/
    +
    90// MCU PERIPH INIT
    +
    91void Initialize_Periph_Sim(void);
    +
    92// MCU PERIPH DEINIT
    +
    93void deInitialize_Periph_Sim(void);
    +
    94// MCU DEINIT
    +
    95void deInitialize_MCU(void);
    96
    -
    97#ifdef USE_TIM1
    -
    98extern struct TIM_Sim tim1s;
    -
    99#endif
    -
    100#ifdef USE_TIM2
    -
    101extern struct TIM_Sim tim2s;
    -
    102#endif
    -
    103#ifdef USE_TIM3
    -
    104extern struct TIM_Sim tim3s;
    -
    105#endif
    -
    106#ifdef USE_TIM4
    -
    107extern struct TIM_Sim tim4s;
    -
    108#endif
    -
    109#ifdef USE_TIM5
    -
    110extern struct TIM_Sim tim5s;
    -
    111#endif
    -
    112#ifdef USE_TIM6
    -
    113extern struct TIM_Sim tim6s;
    +
    97
    +
    98#include "stm32f4xx_matlab_rcc.h"
    +
    99#include "stm32f4xx_matlab_gpio.h"
    +
    100
    +
    101
    +
    102//-----------------------------------------------------------------------//
    +
    103/*-------------------------------TIMERS----------------------------------*/
    +
    104//#if defined(USE_TIM1) || defined(USE_TIM2) || defined(USE_TIM3) || defined(USE_TIM4) || defined(USE_TIM5) || \
    +
    105// defined(USE_TIM6) || defined(USE_TIM7) || defined(USE_TIM8) || defined(USE_TIM9) || defined(USE_TIM10) || \
    +
    106// defined(USE_TIM11) || defined(USE_TIM12) || defined(USE_TIM13) || defined(USE_TIM14)
    +
    107#include "stm32f4xx_matlab_tim.h"
    +
    108
    +
    109// Init timersfor simulation
    +
    110void Init_TIM_SIM(void);
    +
    111
    +
    112#ifdef USE_TIM1
    +
    113extern struct TIM_Sim tim1s;
    114#endif
    -
    115#ifdef USE_TIM7
    -
    116extern struct TIM_Sim tim7s;
    +
    115#ifdef USE_TIM2
    +
    116extern struct TIM_Sim tim2s;
    117#endif
    -
    118#ifdef USE_TIM8
    -
    119extern struct TIM_Sim tim8s;
    +
    118#ifdef USE_TIM3
    +
    119extern struct TIM_Sim tim3s;
    120#endif
    -
    121#ifdef USE_TIM9
    -
    122extern struct TIM_Sim tim9s;
    +
    121#ifdef USE_TIM4
    +
    122extern struct TIM_Sim tim4s;
    123#endif
    -
    124#ifdef USE_TIM10
    -
    125extern struct TIM_Sim tim10s;
    +
    124#ifdef USE_TIM5
    +
    125extern struct TIM_Sim tim5s;
    126#endif
    -
    127#ifdef USE_TIM11
    -
    128extern struct TIM_Sim tim11s;
    +
    127#ifdef USE_TIM6
    +
    128extern struct TIM_Sim tim6s;
    129#endif
    -
    130#ifdef USE_TIM12
    -
    131extern struct TIM_Sim tim12s;
    +
    130#ifdef USE_TIM7
    +
    131extern struct TIM_Sim tim7s;
    132#endif
    -
    133#ifdef USE_TIM13
    -
    134extern struct TIM_Sim tim13s;
    +
    133#ifdef USE_TIM8
    +
    134extern struct TIM_Sim tim8s;
    135#endif
    -
    136#ifdef USE_TIM14
    -
    137extern struct TIM_Sim tim14s;
    +
    136#ifdef USE_TIM9
    +
    137extern struct TIM_Sim tim9s;
    138#endif
    -
    139/*-------------------------------TIMERS----------------------------------*/
    -
    140//-----------------------------------------------------------------------//
    -
    141
    -
    146#endif // _MATLAB_CONF_H_
    -
    Init_TIM_SIM
    void Init_TIM_SIM(void)
    Definition stm32f4xx_matlab_conf.c:86
    -
    Initialize_Periph_Sim
    void Initialize_Periph_Sim(void)
    Definition stm32f4xx_matlab_conf.c:15
    -
    tim1s
    struct TIM_Sim tim1s
    -
    tim4s
    struct TIM_Sim tim4s
    -
    tim12s
    struct TIM_Sim tim12s
    -
    deInitialize_MCU
    void deInitialize_MCU(void)
    Definition stm32f4xx_matlab_conf.c:25
    -
    tim3s
    struct TIM_Sim tim3s
    -
    tim7s
    struct TIM_Sim tim7s
    -
    deInitialize_Periph_Sim
    void deInitialize_Periph_Sim(void)
    Definition stm32f4xx_matlab_conf.c:20
    -
    stm32f4xx_matlab_gpio.h
    -
    stm32f4xx_matlab_rcc.h
    -
    stm32f4xx_matlab_tim.h
    -
    TIM_Sim
    Definition stm32f4xx_matlab_tim.h:80
    +
    139#ifdef USE_TIM10
    +
    140extern struct TIM_Sim tim10s;
    +
    141#endif
    +
    142#ifdef USE_TIM11
    +
    143extern struct TIM_Sim tim11s;
    +
    144#endif
    +
    145#ifdef USE_TIM12
    +
    146extern struct TIM_Sim tim12s;
    +
    147#endif
    +
    148#ifdef USE_TIM13
    +
    149extern struct TIM_Sim tim13s;
    +
    150#endif
    +
    151#ifdef USE_TIM14
    +
    152extern struct TIM_Sim tim14s;
    +
    153#endif
    +
    154/*-------------------------------TIMERS----------------------------------*/
    +
    155//-----------------------------------------------------------------------//
    +
    156
    +
    157/** MAIN_SIMULATOR
    +
    158 * @}
    +
    159 */
    +
    160
    +
    161#endif // _MATLAB_CONF_H_
    +
    Initialize_Periph_Sim
    void Initialize_Periph_Sim(void)
    Ð˜Ð½Ð¸Ñ†Ð¸Ð°Ð»Ð¸Ð·Ð°Ñ†Ð¸Ñ Ð¿ÐµÑ€Ð¸Ñ„ÐµÑ€Ð¸Ð¸ ÑимулÑтора МК.
    Definition stm32f4xx_matlab_conf.c:23
    +
    Init_TIM_SIM
    void Init_TIM_SIM(void)
    Ð˜Ð½Ð¸Ñ†Ð¸Ð°Ð»Ð¸Ð·Ð°Ñ†Ð¸Ñ Ñ‚Ð°Ð¹Ð¼ÐµÑ€Ð¾Ð² ÑимулÑтора МК.
    Definition stm32f4xx_matlab_conf.c:105
    +
    tim1s
    struct TIM_Sim tim1s
    +
    tim4s
    struct TIM_Sim tim4s
    +
    tim12s
    struct TIM_Sim tim12s
    +
    deInitialize_MCU
    void deInitialize_MCU(void)
    Ð”ÐµÐ¸Ð½Ð¸Ñ†Ð¸Ð°Ð»Ð¸Ð·Ð°Ñ†Ð¸Ñ ÑимулÑтора МК.
    Definition stm32f4xx_matlab_conf.c:40
    +
    tim3s
    struct TIM_Sim tim3s
    +
    tim7s
    struct TIM_Sim tim7s
    +
    deInitialize_Periph_Sim
    void deInitialize_Periph_Sim(void)
    Ð”ÐµÐ¸Ð½Ð¸Ñ†Ð¸Ð°Ð»Ð¸Ð·Ð°Ñ†Ð¸Ñ Ð¿ÐµÑ€Ð¸Ñ„ÐµÑ€Ð¸Ð¸ ÑимулÑтора МК.
    Definition stm32f4xx_matlab_conf.c:31
    +
    stm32f4xx_matlab_gpio.h
    Заголовочный файл Ð´Ð»Ñ ÑимулÑтора портов.
    +
    stm32f4xx_matlab_rcc.h
    Заголовочный файл Ð´Ð»Ñ ÑимулÑтора клока.
    +
    stm32f4xx_matlab_tim.h
    Заголовочный файл Ð´Ð»Ñ ÑимулÑтора таймеров.
    +
    TIM_Sim
    Структура Ð´Ð»Ñ Ð¼Ð¾Ð´ÐµÐ»Ð¸Ñ€Ð¾Ð²Ð°Ð½Ð¸Ñ Ñ‚Ð°Ð¹Ð¼ÐµÑ€Ð°
    Definition stm32f4xx_matlab_tim.h:103
    diff --git a/DOCS/html/stm32f4xx__matlab__gpio_8c.html b/DOCS/html/stm32f4xx__matlab__gpio_8c.html index 01e1937..39c75fc 100644 --- a/DOCS/html/stm32f4xx__matlab__gpio_8c.html +++ b/DOCS/html/stm32f4xx__matlab__gpio_8c.html @@ -5,7 +5,7 @@ -STM MATLAB Simulator: F:/Work/Projects/MATLAB/matlab_stm_emulate/MCU_STM32F4xx_Matlab/Drivers/STM32F4xx_SIMULINK/stm32f4xx_matlab_gpio.c File Reference +STM MATLAB Simulator: F:/Work/Projects/MATLAB/matlab_stm_emulate/MCU_STM32F4xx_Matlab/STM32F4xx_SIMULINK/stm32f4xx_matlab_gpio.c File Reference @@ -14,6 +14,7 @@ + @@ -71,7 +72,7 @@ $(function() {
    @@ -80,6 +81,9 @@ $(function() {
    stm32f4xx_matlab_gpio.c File Reference
    + +

    ИÑходный код ÑимулÑтора портов. +More...

    #include "stm32f4xx_matlab_gpio.h"
    #include "modbus.h"
    @@ -87,47 +91,54 @@ $(function() {
    -
    + +

    Go to the source code of this file.

    +
    - - + + - - - + + +

    Functions

    void GPIO_to_SFUNC (real_T *disc)
     Write S-Function disc ports from MCU GPIOs.
    void GPIO_to_SFUNC (real_T *out_buff)
     Ð—апиÑÑŒ буфера выходов S-Function из GPIO.
     
    void SFUNC_to_GPIO (real_T *in)
     Write S-Function inputs to MCU.
     
    void SFUNC_to_GPIO (real_T *in)
     Ð¡Ñ‡Ð¸Ñ‚ывание входов S-Function в МК.
     
    -
    +

    Detailed Description

    +

    ИÑходный код ÑимулÑтора портов.

    +

    Данный файл Ñодержит функции Ð´Ð»Ñ ÑимулÑции портов STM32F407xx.

    + +

    Definition in file stm32f4xx_matlab_gpio.c.

    +
    Generated by doxygen 1.10.0 diff --git a/DOCS/html/stm32f4xx__matlab__gpio_8c__incl.map b/DOCS/html/stm32f4xx__matlab__gpio_8c__incl.map index 880f0f3..e44c5de 100644 --- a/DOCS/html/stm32f4xx__matlab__gpio_8c__incl.map +++ b/DOCS/html/stm32f4xx__matlab__gpio_8c__incl.map @@ -1,28 +1,28 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/DOCS/html/stm32f4xx__matlab__gpio_8c__incl.md5 b/DOCS/html/stm32f4xx__matlab__gpio_8c__incl.md5 index 195e281..f89488c 100644 --- a/DOCS/html/stm32f4xx__matlab__gpio_8c__incl.md5 +++ b/DOCS/html/stm32f4xx__matlab__gpio_8c__incl.md5 @@ -1 +1 @@ -eee241c91ed69a0b4358ef2ad77b6176 \ No newline at end of file +30e6034fdafad4ef5e4c5034d87196e1 \ No newline at end of file diff --git a/DOCS/html/stm32f4xx__matlab__gpio_8c__incl.png b/DOCS/html/stm32f4xx__matlab__gpio_8c__incl.png index 0e31ac74bcc4f0e1fddbbb4a34a0b62f9a8a5790..522997e4efcb65fe212a9fd99212cbe82fd4314a 100644 GIT binary patch literal 29405 zcmagG1yoew*FH)}NGM1nf^;JxDWP->NOvehC^>*bgCJm#(%m_9!_b1%P=a(L3^ho1 z-ZTEb@2>TI_kZtQuBB_>%z5|O@80`;o@ejlH%$#CVggzM3=9ln6=ivC3=Awa3=GTx zd|cos)5v)x;2&H|H6?kBJM^Ed*1}i}jHehX@~?C~({>iTd`+PzcL!7O*n9^Z-c)5w z(U+7|1l3&nbHjN!uUL3Z)Fg!Nhs7z7YQDtUG{B@Hfj#dBsb#;^q0E1t{C=Rp$$_BJ zm$cy-V*45|-ETsFIlyzxA-&lMeI>1!+cAR_N7Y11Z%0tx03}|N4Wv z2mA$n8ZZ9VYPGjp^~aQ&i_RXQKc=;1z7KbB4l5t7c!UaXtH$C5L=q!j>UCWz+V%y^G+itxPo}<=uhUqyWLi z%ww=CcmUE9mp#P(10*B?ZY`h|FIK2)WdMWTqb&r_P|CsS-Hv2(BjVq$Tji`qN)CG( z_4q6rMn#;M3qG;U8x7UsE(#Z5o)JtFVC6pymb|ty-I>WcXrte|BBPO6s;Uw1d8ej7 z6Dc}+rnhPR%OO(A_`p^nT_FE0+DQIr^{KAc8Q^qXH*ptR6Aq+LC*SFP$;4G#9WmsU zctXlwBf*|0+zH_@7dTHV#nDgGugJdW0lSd23!2-zu6CJGflx08Fz78{Ehu8(BxX2H^99qs|x7-GgXHCoX2Zg8P zqa4FI=~98Us${9yF8CBEa`zD;Y6Tk+9^s>>E)k*`gdt61kVaSUk3G6VE>Aj=RL5p# zB@E>CHBv=}pmCua-lvG9A$q@KEnTR&t*vbXil;yl?Gs?PLAdoqw&9#G&{>O6Pm(J- zR0{G+l?8irX-z&0p~IoSBa{^#jY&kMhJpq1p$kInbE_tM84Xk~_F&LS zWil%`)S=Wm9%K=9c5@JZ)+C!Y?)D^?Iz&FZmqWMb!0Bt+mUvInAy`PQCl2m=R!r_4 z6;_fup5R@f!M8di%>=d!0um&yYBa$+^rGpY(a@a>xuaH|nL6OmlQdRkEd~xP`pzyk zB?Ln9hiM~-E*#{SuJ4ll*H{0F4!AR)%Zr9T23OmnZ(p^-{?k+=a;C-U+|6xBa26Hn zlEXJXW>KHGxN+!3hp-n~ZZ-_&4Nbh6<>bkYo8S%t&yp||>fB>FTE z1d$Q-&bDhe!-}zgrG60$)-&9{r{MFbA^#qcE^DqRV2i{= zX4&R^H8^H6;;Ltug(f3RdjGi2yl**^jK1ne9-Vt;rr(4|z$Eo~Xmk{-TQ6Zrpul>7cR*@_0lhN##pePE&{#p6}h4sIvsG<3|c1BpH|FNfsJhkz`8xZSz zN5^z-ChkJ@)OCqafr6L+JD)TDD@)N{XF}9Ybtf?O*kq;x^&RbW(wT2kGN*7FFyh<) z9W6j?{Hp+fA6BRLQ|lt#!IP%W@+n(v1s8Nea~qVaNg;xZ8!sloT?`C=uj089+qCj^ z`!iuMr+V9d>MsNfrj@$vso#zf{bzL{zGekiB@q+M@7CP7RPv8Sii5)oL}mtK1lVjZ z7Mm`xMm8+x)=^H<)C&lS$v-do8?++ORCW>WetZP#h35FZa!~2bKQ|5JgHUr0Gt097<~D z&}(tMqQ*>cF3r9aOgti;Vd^|2aDBmSk+@ZLV0A_BcC(}S;?~n*Zuyl*o0>c4qUA9FNXKXC-f^yXZ)=qXf-HJs`iVzSVx=)4R4$?-x0l=yoE?OEwATUK_x9;Ee;H0q{pzzSqmi*$d5r}=?&$C2#K?z!w(*G)g zoqReNE-V)}vLPcm*T*FC8yq5d?YFMYVtdrIGQumL5FHie5gtAA*dE)jTs)#b;r|e3 z6wI02+p1gtr+UN5VS+0((UY(e&Y1&Zk8r*EI~!-7e|tgwtbsQy*$#bluXO;wg-HWt zrw9EJjW+&2u!R}1Er>qD_fTbu)Go?1s|`iotw*>wnnZv;l*IQX_l%a#_B^-p6HS$1 z0!+7sd=jSSzK1v$j%N&Jg`A;f4Vh~n|EMW>x0{_%k4PPULW$M&9JSb*+43U?jPau?>gUF70B=A=E**u457@M3inB5h@*NkWWWu8v+ITXk^IwxPo8_`}FvYQ}5_u3Q7{0 zRiffwiZGBrS9}f=LSIHXQ(G=jz$5Q-B2S^u@w`{gwGbs~&AL$eXoV~Yo9+!UcLXOd z8o!89?M}4n8e;iQ5#(#-J=P~^d58X;6ab+FG}7U(8YoxzmcO-0x9v#0hO3H}N)FTN z)9QGmZB5(WvlXZm;#@CF;Z6mdZ97>xMlFg?S}`*9&5giVDP-O>o!2ZhL-pT!|G8)F z>GmsvCH1{0p&C0HG!sUn<1$u*kJa zxb%5Jqr>(jwT>X6&$03dSgI4JD$92Yno*p^6`Fw^Su zHGGcm0i~fMGDo?!58842=)a?*&dRV0!3Nj@0FAipciI~YkBV3FX2(+HqVqBsR5r5! z2iaIUcmod7EVKXcTBhTfo+0H!gn0SU_;d6lyh3A=f;a2zP;QwHvknIH#lA$-4VV|& z^Pm1%&L4rWe3KX_=saOMvnCN$1=vFV32jT7y!T1)zPI0A-`*E8@1{;puC$g?l?+#s zq42jYpW}ga-GIo-Y%rw?#G^4S$SK&}`TJ6^&xufKJB7yP7pavO_;(Z!RVxNOZ9bU2 zGJ?Y+X6lC~Q{oYvq9Qd`;r%Huh4`P!wZFUH z=>_xmkE)CxcgdkpMLN25snXaPUfkO^3&xP!_@ur)x+9h&VBL>4_%xVIbNh=Q`_sxN zmHB%|Zw;zIr`vC}^*L-$3;8Tpy6BuKz!h2k&`rUo z`8;3UwwiQzV&v&O*DnlbPVc2PFW*|XgzKiCqreyc85YVlgpZvo&EZLq(V0I&58C^5 zB9Z^|0EGMZaV_6i$<)_tiDP0&sn14`O*ZCLpDITuRhAO32d;~DmdrhC_R%pt(Jv_e|sm%GJstv z`YQ-4@6Lld1oNRusE~~qy3mAk&zH1gJRtWPSfat^s3?Ls0hgLt3tfC;Ie8aH-RaI; z4v~-FSY<3=I;^)uBpF))s5~j$cye>tvx|V$dQ(+&C8Oi1k8!qcvgIqIbUUlpzD`)j zLz&!9JDW|&=r;K?1gx!FhEjTxXg4NCcV4MxYXoD4Nb4D|GQ#JeB0>TK1q1DYlauDH za#EHYFSdSpy>$yhSV%;^0~w*22uLw!@Fc$JcrnjJC!$4W(JDk+c*`NiN)FrSs?(B! zJpWaEtX5qaZO||66I;=#2 zdKzuePa#0uSw&zrJ7TWSG4a_mR+4%;<0c?XQmh9!MG%2QJjvCR5sDrZ(R)q9S|uOC zJVX$vyKRs3TQ zX$((HnX07u+t&R~LVvD!F2qRp_yg_)kit7BC!0hwcb6w!NdjiB{jAu}TJ~kNdZ&H% zT4%gbWnmJEbr)N&KT7OhqAHpr-*Tm)aryryrvLvxU{hl{O!!#s=WxE7>({Pro!UCS zC$MzDbz!Te>a$bTTXbh0dJyi?eaVxY!o*Z$_sYEC!Y7%2;JHnHdfL&=j%wK>L0T|Z z*bom*YzT<`%?t6zU=Xy%vR^lUG~uVn-Id|eF!Rv65bpV1UJJRx^3@vP98B@=a z{@NxEp%i^2sk$s;hejN0!&i}9^24sRUKe&zQm3ACV>9p6Oj6r3x2izk2w%z6iryDa zd^F*lYybz>v$bNZzCbx74h9G${`#CLUz4mwYd`3aA#(^#rhojpeotU(#Hn^Q>I_;x zqco7Vbx;*L0)iik+px}nqoh2yVTFs=9?QHIQKx&r^(EhFQDQS|h;`^i_*)Po0MKFH ztLgiS($b4DbNheZK8L4$S7V(!OL8tZm06XgYp2e9n@^?09KplIW^5IHdMQiJxB8?j zlzBA;h^1no>hGM$`;{aingvE_zBci$)&{Z3mOki31=Xy(zjJ!%16RcjjHzW?2@M-w zIV%pNq9{B=zQ3QTqOK6C<4y!>f+>Jub)WzTrr%4Np?ubrcpxIvZkp(ic>ftT>#aK> zF<0cs74dJmML|>P8o}JZTD0&B&(dBu0RY<44bJA3i}MtzoPATdHek$|Ff z1+55#O0~ecDmp46ZUiM5VOs+#paXzSv3C9AB)1ERCG}DG@jHa|wP|RiY`9U;6p|@( zL}Y1b=fb}YY1cBe0C%{hM^$}u7#u!L3R%o^0!gDuhfab+@({HSpMy<*5Pkd@W8Y7d1&z1 zKGv^F;g+gVXw0Y=l%(iO;FQ{n-52gkqPN5cc&aa)oM^+OI&RLEEOr=+wMIYk64;&bwpo#y;Mz049FLgqb93HexM+WE&sBKmgqV&FZ60gH8rXqwh9?m`qHL>h6EHx7SpPvNVNqXmZ!hKGjq;5CjO;bhX z62^-s9$cZsjDvGEZLniC>17Rt`8%ErL?vvfCHGS6+@K|@pOmFjoF_r11Zmm(RB?o> z>aMS|BNs46q4uieYU%?xGfvr{tiJMLy-waZU zJxC&Uh}f^ZoL7+Y=&|jyFkJ&gGb#X^aYh4>Y4KyAkZvOpwdT8}vgq>DEkVN~fgBYn zb3c71PlD6{Lg1XJ*X(6LBfQuKByL<0zO6e>elGQ@l|6dV?E{zKT!m!3oqLjuh~gg@ z+zCT5GR=dw;V@GG8R}rI1P_y(^HnAi$P^u&+x3DtH(8xm%x_9NxFjXXwKQLg0jDZA zq4=erVm1W#s7e_A{c}O@Kq9% zomsBWCDfNV-)Ln~BGZkq%InH;_1Ny$82~BMiSG7{#RMtiGAX@VqM1~Pb9uB3tLNm> z78d#Zt9l3Z-5PM~XFkgvyi*i^^+st-NF&45O~9YNCu!Rfh;xNs)vp=|kKITieEU?( zgjL^JLIv~z7NKW^eUEzdod~kZ7M75ib6*N~MMN*g&o8akt~_ob|E7zOT}$Jh`%^Qq zixZv(DUF__QM9OmS=Uf%b@m-1;}7z{1U@_PviX{C@xVzT8*a{Q9o{O$M` zKU^RcNGVVt4`};GhAZ|yZ?0uHGFqu2p2#O0D$xGdz(W4 zSzuK0KK9~r%(=j!D`!t6+ll4UhUM#`DS_R+qO6>GQu`Qqe&6#1*Z1Z|_$zfyVdu{a z&%~babskC2e;Xx6nIk16Dr!zpq9S6MxQR(4`zf^ z5uK1cTD)93VhijxV-&9#pHbv$SdS0+l`!6l7ax0118WiQ+I(4LWJBLx;SJ~nEh9M; zsfxWa3@!;YpcoGOvZgUrH6|p=t&p@T_mVs_J0GszVE|@?BV2xp#)FR#vdYfyG9RW9 z><~#3%oEMi5%#yI0U|efFu)$dbFIt#pDrI^ziHw!bNF+u%?ppP_1A8&)66)0Th*~A z*=V>T$FV&6h!CM(F7&`)c!-<57|7l&{dbcE+Q^AWx3&C-2-6UXKeFkv7|g+3<` zOTc!C`LtJgQ2eGq5l!JD?uLWT3xhaTS2Rpo3KWhmdCqhUJJM%#b3Rly(|03W1K8Ra(H2e4uZ>7C!^;qvhzZ^jQvRW|9C z&3zwy9ZIl(4-1iYr5Nl6_1bb(c_HO%OD7)Qi^Jg{41h6R>&8dwGJEi*@;NsS+lB*C zF)pb0tvp{Z-Wl_bJiiW5D|RIGMVRj2+~2q3VW}~*|#0`WgXS#^Y%R2Ckx;`)-GYgjN? zmAksdnV=H zqbmX6>k0d%Ea=F|k#&e#pc2c=Jo|#{MQFLNeC%vKg8k}px@7)Rn!=a`)=MyNJT%08 zlmqav%zMT-k=U0wPU^2V#=c9gi=_+b0Sr`UVm7A9Llv$Pd_%#PartygZ<|NKn_<9$ zVmR_k-fw7zc2WL%{KdPOthotCOFl>f*HvtWBdx<5ul$`K{~?OSzdx3LxO%Xk$8p4c zBSJQsXI_T*q|59xKK8A0GR0t>d$uG~cZFw}dKpJcLh`MOlJf1Y1VGq_fz_dCC=e9H zv*4R=!n&(Y%enA#pN6z;h9b@x5O?hAW?KXq9Pj%jR-_elCU?~1%V_5_)5n~Y*U;#| zfKy+Ob*y9vUoGHcQST?!<}pW}E$*Lu8p72kWqb+~-bV;i-tEzzso;?!NO{LwtSCmF z0}&Usf0~zXkM1MDlX_xOuon+HBZ}!tR5t>8sfzO%)SKR}TF4uYQp6FOZn*RV55S%> z{=V&XD$&B=88Jn|z|$qzPagu>RY0I9_ybV38o}qO$Hg3kB`_`KmuMIxdfs`JfQvK& zd^V!wARK>|79Y&qg>YYa5aV~wuo6h^XaahMmP`HAKy-p?0 zM|0f(l^G=qpg3&SZX4UQ=h;fY=%^!TCl!Nnb9{t8DKTWa z?}u@2%fpfhP0u%tm~0XByKBkBi0E+h^J{4ztN6-Ozv;d34Rcs?#UaZ)#529O;e`!C z2-vaJ6u@DYJUgRLelqisJVK%#TdX7Ob}d^gm7nO1LAQ-d#a~RJx*njho&=f|eP>o{Fh@Fx^-zT9Fxr?S z4yYHmFYy}@&;(V1r;=r=3~~zE3tzu9VDRzy6(c5GvWR}lRZCLF+~{325oq7sJZ;4=*JC{s()~gyUm0{S62G1|~b!2%ch7pdNFZ@rX7tGXMRkz0U3hU|p zED)<xjJy zi6csHT+*O^>D4DPL^XMx=QNQePcut(s-fpZOScyKPx}XI1U?WM)g&659|GqBJ~GoW z5F%E~h2SJAn+Abyj~~xC9(?fX2JZX2TG8XdJuwQg*C9_74rr|F`*mc~)nj=4I=AbK zlpb3!Twb>qBOY`h0!ENeYLF^ZGvUej04*>nex%}xxeq1XJ&>eyN2~l``1dxy0Udlb z%UAGm;LZtcALkvk+Oi-l2#mvZ2OWZy*M5&@+EcDRz{jg!u}_?kjb?&v*bH1xYV7t}PwC!KTkNFnlU2C5xdz zVhk+T4{fuX1iBe>PHJIXRM;CytGlC9KvXPtk*hW-(1u&v<5Vg@?aXK>(7Y``|fyay^N!+!|ul*1^f-{qQjv? zi}fp!0b4|TU5O~`C{SNtPt*{IX~wUD)m`X5j6g>zK}`agp{6GPBmt6Uug69pT5*5OG$3#%iJE&@z7(;$My zoJ9$BmzeL@-Y&ni5Ub|43K=tG>Bi|0Y8HVMqIi1Zay^wN@#;5nnRp%{f9i&^GvAjg zgqsL0^3Np60u+ZFWM6@cE!{3ZT||$^ON{6O{8{olwkekg8rN3f*F@9=bU5JKK*Ou) z)0lu}FP@$urm2vZU=;7pD6^TZP+b=QBuJuz75!GsgC|T1&aHeCu7{unt|CQgtK83= z=lcYwjDS&z0o%U2?jYAlt}E;jANt2YsH&OBE+HjSVg5k;eN%B>!;e#pqr6svD2P<$4Ue+FWY^K)l+zcqL%%E~Vaz7RM>MK3X2 zOnX|`(!NNo__8r5qE;Sd?K9{Q4o&lQ-4HxA1SiDmxgk%=+1@`q-@&`C;Ii+!Z`KMN z1AxOOx&cFL63iFCI#159ef}JM^VIY z4*1(hk-Jn-N_rBUylBxj6Dq98Oa7*09f7L)Zu$v=@#%cOL|L{S4jfOwj>i88Wfdx3 zcOsUL`S3I?jN~75FHoHTXm%jbTwak-6NqSl`_xwS8s{K9?sKOSuP65mtRFZqJm&sb zuAp9@sZ$^z==g5r1f@y|9FjT=YY@_5tYP1w)dPrZVe_yxB9lUG-4TsM=KALe29@4L z;vm_klDUjj;Uwor<9P61C?(j=4CqIhz1pItUJmM5#X1Y|f%f-HNz6b+blQN!!nq2t zmi={s$=mu)t*Wf+U(f>8`ZslLkHzk$tXeGXjh|<0+Z2>T4FJ#fDy9relwtG?-%eBpVM~MMYG5_ zqDIf)!`Aaf0G4ee{X1$#v5Rd^Tg2Sx`}sN(1)9hKln;E1dkF^Kn3q4vUhg-w>m8f$ zvraB8F+kF@HOD--8@XbB5qDI_^@2z9{9*Q#>0hV$u4yg1wTVN^r_!%qO?q{fEV9}B zl-1{;7+Z4`d*GRQ59m=Pd^4`Ii$~!b{dO$u9KK@u2qHi2Fvqyo{mhP!|Gk&O;c^%I zd&Ec=_ub$N`hZ>Urw$hyo~Ma@sAuY%hB%tgjd(+4|IzAK5AlzGmm~f_Vpdz|Bix4) zHULnX|JJ@zc>OqUS1ii`0}Do;X$s6ctVrn80bRjYaT{Pp@kMBYF$o|N`bLG}tYbvs z;GW9^1kji<5}+L(BvA?n-+iH_8vvk6Z^h{Ck#hxW;28iyMlM@@HL(YBB_D0WL6q z4$G7kmydUD9@hQ~d_i6;yJTYZRUjvR@6S(kx<#@u>mVogPCu+UTW@o}08Xr_HQ$N2 zuNsb4O&m*DPT_1P*J5v$P5LE&+M$P&JhUc?PoVPdHDIQ>ze+^lyuF7cs4@KkYyaD7e z_QS35#gy?bUnJ!lH44g}ps^Rx*Fy_U-D{4?n1f2yXlSF!a68 zSc)#wx`SM6c-Jn*#MD->`z;VPXi)*@Gp)w%ckM{iNtV~}Vcm$F)=NeT|FX`sZy7s- zb0KKN!L9Y+6`Y}wXOiWN!aEHR;QHs}W#hWEBuR&N3Hph_QZgyys}r^q%gnxvlrgA7 zng#&Kq8_>i5wOD`H~O4>jQ~I1xKSKK`(o6hca(n6;GFyyUa6v?a9!XcAmodU3fLLV z*)6zM20DMO#$So-U>n{6q`VL51LO%5YI@~pWSnG~PE=OG07w()k07A(H#+$i21^_Qc_Y%g-2tRLBNjXgY_Dd zThEBrIYx%kwbU5M)P@qDpuG}E49C*axgb?}3U>u?g0KyT=5tM;Nsl8_HX?&Fia8P8 z02$UDV!Gc-FUD3WwWoGwBjEK8P(AT1*5m^#Fc@Ao>PYgTQaIb6ZFdwuG9QS@cr-yu z)utTaCm6w?u?_v>CLt?#X~Mbu$56REMLF-3*!avr#^PSN{0s?+v4rg5**7{j9`wA` zmx~UpWwQ>loKo6g>w1UG=Hs2^hz^+pad8n7f22fgGBtNXv8FfYTULI#l|D~p|5XVc zVUtSp!tsZPwHy{(b}@VKVV!UPq2g&zA)J*jAkADB&nAeJp2G}EMyR42EEwsi-+Tf2 zXfoY5!%XYgXHuh9CKfCsIWsa%8V`~}Qik+1$rH9F`!)WT@Vftw63Mch&he0`^w7`A zOv1#RV{&?;z%hL{LDhu}(#UaFhw3to9$EjWLtkoGEK>Z)OpP59vnMog%1Ca(lAVZc zD=bod^=Ioa6xd%Ybd!mGSyzt_$NiqZ;D-~V{#`BVzZ33Dt0g(ix6-;V_Y0-v{R(1D zYYp~vR&=`B+4+n1zjU0^X?{)aiS_y5nhS}*FDw2qN$hH#ZOjsGjlLn}8%k9n2%TnO z9#E>EXtFNOC{%!F zm#EAF2Rr#uY?EHlBOE@Af+E-0LQ|t{G5{Tp=r{6pEd}3&hOmJ5a^J}^7)*P_eZdXn z1{8kFPXc#B`r1(j*7sS>7Xfz2%jVpr#l=H{AIe_@c?NNNLvY{3d$`m(V%Nf;mq5>5 zXXU8AqUzAFN>_nNMT!B*ML{|JF+892??jE>`RBcwFT7ge&#svl6lw2cTj17fGnyCr z))@M@2-<8-P?G+!I``3Behu_yxPQAasodZpG{BN++EH=@aDi4}OV+P=43H$t)v$*y z>YRxlfC^UFsReWjGI4K-=SwOj>DQ#2AAR_Mu7e_TheJcWxZ1?EfP#JJo<3mJ3xq!D z)&v=elishTKsZJ|XO9LQ7ugiJZ3q3S4PJzw#%-0!zSvA{8b%YA!W; zW_VDa-_USn1W0au$HB_7S1Ut93(Uk=AJv5qvw@aZgl}~un;&wKY1wYs78^TlJ7;vK zGf(3rZk2kLPMX+LBc!>M;>YwDFKz->>b-T3kTu(Kq2vRgZs6qHziI3=e&fQ!V(}rp zP#+lgBd18f@jb1sC(1RM&V6w&c%%fv$Nv;T92DC)dEz`CokvgX8yXgc)Oc*b(OB3S^e$jsR_ai<=0<4a{uYwCMW;kd+uHzY0=K(|BST z(gz^<5=;kTisc`rG14z-XZB)2)5ZmKGF+Yvgab82^&*n^$Fz>>>m|bC&?|v3Yn^yXojCq~jaM$k$%IW)YH#yc?>~Ja^b(KP+OW zRonv@!S&fCPSNueq>Ql$znBg7r^9EQ7oG0F1_rerZ|x2>(0(;HU?ZiF=@v&oi}(nm_MR&EwGLYKi0 zN@sWM5K{wXf8DR(b>^7y8%=$T=0rE=Of;U83mt)tU!TDTXv~iB60yb{r3`vvQdd%%|J27!S)d7{BS(#(8g6!f@c{&)50a?A14* zVub;M`pb(CO9MMbFdSKF0MXv-48c;ue8}X>EE49!ebI1RAKb=`^O1BVtvu@k`Qh}I z#-*DjBTZS2M}PjAJ}dPdn7`|snf4jPM-L|u9F zfn9kW0=~NR{K#kkx@e=BvaIqnv((WIQmu^$wjID2p=4uKhRqVEPpjA}hPB`{H37 zfITSyt#0aR8nSDpuGYyyW9;m?4=!>WP!78OO}qbZ)cJO5lz`U{XTA{K1^iW`+SPMj zbtwr@-vmp#k4!+1SvsSaVA+o;&0^EKPusJG0u9(dX9LQ8pdJ)^UMnJTv4QP`-va(* z-|wxt@NI)pd8r|n+h{O-E)Xg!p0PY`z&Qalz0{aYQ|zo7?B?FhES4|Ud=bP$x-NGS zNO_u?_ocQc!~%+7V893&LA0lG0+oFl04c4D`j^YQX~9gCC+}A6=@YRnw2^$I8YSa1 zp$WuI=~E-N=dZax83at=mlTNnGEphx>4|NdJ+yhl22tVZn}~1msMH3kM$edm`Hl9< zx~KB6D_}~URL%*E%1b-@1$_)K;LaHb4C?srD`=3P6YOIKzqld)t7ba@bbu&y@(i5i z&Ns&uPr27sp3j$j3EdCi@}X+>Ig<|tT5Dtpu$V(XN}hCH8JG0;Oq8XQ9#d0plB#Y% zA#2x#$J*H`>}Q%APhm(A2k~70&^nAk8BPp_<_kjCaTl7}GcBGv?9BB=cN=r@uM(cw z$p17fg&%INu3|yy&_yZE34)Gec*!W_` zUuVtZ5@EOr32O?I0Tm-Tl;wjs$)ikc^u!7n|1$A;nyY zSTC@+1G%~02kpr#c%RS*n_0ekz|~D8muIj?8ug<*i_T!Dihwcg7Y>$a*7c7gad^t^ z1AYKSU@c1lX?uRc^Q_^)2HX&U2%eq1_)1t*#$*G3fSe%;@u^b?7V8w4a7}j44`n$q zjBA#hZWm%{cS~ny_}>`NUcvKHMED_g4VY0S&T>#$b_8=42;4U9OIJWTdPb`Mweq#F z`*$a2gT3S+aiS<2U}C7ip$+cb3Ym*|b@8!WXx(8mv57F??h&&7vr1YUFckDhLSMMb z5;mA8nkmiI83BxabwD$W0lIvH^{hwMH5|nQSGD*-h1*8tkT2V!abfeHb~IshuoK2M z&5<8B9ZcTB{4=j$*!WHA0*U1hy7dT`ToCy6+TpLS*PgI)4=ByjPB z!8T@BoowEfa~g*V4dsk@l^0Ead73~Zy}GS^i4{FO!F&jeCd!?hOude z+XuO=-eCkUdSwN3$H7#xa}o=a3~RU)8rmzDW!k2Y8;32A^pd3iNvoA`>X?)*Od%8y zdWak_ z%}~%syI_Vo|HR?gp}5@a=jU4y^SUo&^51CNk?m7@!u}9G!Mv+m$uEMrW6m_OZRB@0 z%P*I648QMLHx*X`P0{!(9uQv+>Nto<@O21Tpj2RCKzuO|@6_buEq^}`tQTPr;QgP; zh|?B8#WdYG3JtU1-~!&xwthNaQX(&w_xAfkBe1~PSi6ce4DlX0Ei9EXes(TR^{tY` zlfF@8qAvzO`ovQ+2=z<-S8tcG`OX}G6GSH1Yt#d4)`TFtAI@y zD=~2dFWa-W(FbE@F1E;IW)H3GF)f6?AxYr1k13ol@F_ue(^D_Mar$b+RYbJV{Cg?D zKft2ou<+dBqIRGZi3nxw9dpF8BoO+;IJ5lEW$j_VT3nd-cuyrh4$v-m&Cp#aiHxY< zA$=JkObDSrE)(U%KTEbm&tyZ{PNa&j>BVFyWA>T{AE|6whG4HUUL+0Bh1BxH@O%)w z1hLq%c|sg#PX49;nV8(*_)-M%ljN{%9yA648J2dh#m$WyYiVOLzXpjjMI#!9ZYgp;fbnSB#F^dzq9}=+P=4uc-zb;{q9)QR`ChBnx%m;MiQ7FAoZIzqOlaV4< zqZXAmoxv)m`^4Gv^WQB;KtiFT<~QF7Hn8QrwkH337Jwb|qh{kJQd(bEb&1{pkR_g+ zE5GqM-9t1i<}5O~y2@}hcxs#H08Ujzg**gWI}8_T zlXaJ*78eAFgN{26-?`Ad9bmqKSt^RSnC`K2jF0Jt%3iv+R{XkW?EGJe*VziO-Ys0f zxD1wsoKYl+vdm7dL!7ttG#UZ%+o%Y8peSP-RyZgq@$V^6>o!s~it~ra^WpfizzT~G zeI;2?gweb$`X15b3)=$faVpI8^e?~mesc9@>?x+y=MjITVn?0-n@oC!IpLAzrWquL+gvKy7zb8VLcm!0##k?}i9%kHElBzp?UzF;(RrJ;i?OhR;$D&0J!r z56e}qw^Eac**)@ay~aYBFI=^bMeOCeMGi+ys7*sN-j4G5>4q%nZmU=2a-VPzyA*bO zp>|L&rmbpZ$bUh}_~_@680{1`IUjXO=(6Op`m%or^2yuDh?5j~vdb57Iwa+xA;=dO zeYKu-!_@m;_>953=7dFAjOSm?QWt^A8te$}lkb{e3pEqEw~+(oM@g?n`C7?Wd>F-= zG;2&B3I|pw!f3X0UdCZcw(VX?K9%K$&?AC8=QX!~Q^w^K@ZD77PkF0oaOV4@Dy(`- z?Kf0?_3eNr$bNI*5|oq<+tueF)`?TIJaM%j4T}G+a6f&UGxH4ua=z6;N#URHp6gR~ zvjkCQZ>a0*cL6>17l*^1LOiA=c=`|bsUi4zUKPQZzPHrgnOA%}+Q9#ufIZr{h&@=Kc~)<$_6zj5@D=i~e-ow9nVWubyU{(wrgOMcTJ-N2K4w-Hy zS8(}Nk^JIxNs@1qST+^L$3l8ueUA7@zcXZP$0#;E4$b(&cs|2Hd~lx+uPQU_wQ}&D zhdhgA$k=&^tS^;kiACcNXo4=b@HOr97V$8?nHJ?@;g_&V5MJ|=BAM#teCwN#Npe=h zZzhkTWooC??0J}azwyh3)N%1VxR4}^Kr!UFv=Y1}Z8Fi)32{w3J~I4mCnYoG=QPuQ zc2Bxb!c99V zLPK6z;%l#8s9oG%KC{|4A-nN=H+TwerZNP+#>-(1U#!2NBw?T1ejbphDhz>t&la0Q zg&Q!TMy2KT3lc4O6GY8+Q$=hDTGgTy6TJOr4fbBY(+! zART_LWP~48l0s(e!s~GHOF|9TlJr}H(%KP$z|+5yb_5xpzPLI*f3*QbYTD50T-V`| zp?r?d)pbZmZ=l8-_V2pZXU?-+6EQ4wf5&jhBulFe1n%CbE&K}p)Qk&I+XV9;_ZFKEhYS; zW!%$8T_P#u5U1smkXNpH?t`CO%Lkqsl`kh9nsWAEA1%VafJk2Q!|!#BT$~NGQW7!} zY{~#>qrvK@?OY9YJe2QS;=}V zn`l*W_*MPfDwmX)d%zjuA|J@OhOII8g)uY4j$9^Fb-NzV?wMWzK3OMezp*-ZOut#7 z=Z!|Vp~CHqFVxx@W#%&8A-RFS1euU>mR3A04J{-3uQK$VGNT;TvoW1`FxtChySo;} z#ygy-D?uq|U6>#NPbWgyhBVNYWr4>47^C52n?!f!4;(%HZk7q5nag-;ewoSho09H6 zs(|F3(kIu$?lpEd(umvo))36$m0kY7$0M!($ir4f{OvX~7Xq%PU2jb?&65psgNNw? zzOo#w)dQ^?O88%fy@_r-S;*IZvrMv}CeD=%<3V(!pG8M~eZ4@HyG%VYzOU>mOQ6Dk zf|N<@vd#ita_kSCb{4$vURPWD2w^6kF_w#lYg^;?^6u|5g`1`JB@w$#Rbr--9!z3n zx?o|2j=GFr@L7Zs{rM$-*vCp&XmRa9(YK;Al+6xAj^TQC$3ylX?7E~WKs3g+R z{alsyuarO}(Imx`d2cU-sJU{bVr6eMbV<89_hlA^>dUe-fe<)uyAB^{CfKajPrkMs zY#Bmh1TIxcR(E>+xSClDnYYX#UVN?`-lLK`W1^6QojB@uW9lY4F*Ea5E#us-s7uzi zC83&r@d^tUlK}g33|!YXC>LbhW2REj4u_J~%RL?FrIu91@xfX(&0aNenXDkkDAh-<|5=eV}t(Za9$K!FRjmImiDs`n&*=QlgUYfrubaZ-%6W(Om%B>f!bv}$p| z=p&Unrh@S~N&4)Drpax`yJpV5=v;gfq1Mq7mixz#BTyULLjR|bFWEVTcSlKdUmrZp zM{%I9_bvYi*4G+KGgU6eDMEX~nP)n=qVtGq+u-+2?S9+!vNH#B_M>)mbLE+PyCON| z-DGCNvS{8%V&}coeRP15FYiT0tbcao_TnGS*qVd}vs$Le-l&-*>s?1m8Zw9;$)0AT zA?@~XZ})>!CY`98TFZ@##dqz%+;TfE;sQ@;xoE|L#os~ZuxdWPlEK~`FI7=Kr!Uof zReXG%bByZ&-pET@YHOy8c?&K|CDtb#r#76T7#8u_{KNou?%DBePbAb;Fgu4l3| zrR?3kNYQ9gvl68eFX}^!Y5`F&vPYLh%4<12m*$U0{ZmMx#ZtlJa~G&yvpjt;tRqLC z=j9l(toAR%n$W5e+@6B5BECoyvG?o2#fr};T}7E|>ypPDZN)-0$*8c6NtOIL%a7M+ z{Ac)tZ#1Q1MUZS!@ArW3!7pJkv2xWk?Qhv`|xZpi(hWyv? zp;jRiJ-^XsHwUMF+#RMd;3->DZs$}G)s2@uxY4gq-NIBx=O$GlwB5rAyPrN%D@Dy( z1FL_SP|suWoYA4#hOsQz12Ef6MQ3?RMh6WHoJ)vS)u&rC%5)7^xlW)%&`kg*LPv0v zpRZpM;(R6f*S;{o^7%|@Z3L@}`{FfDBs%Y$ak=QyU@~;x9|yyCG%evE z%v$4Uny^cB!4=p%z6!uq+!RvM;kz1zZT0oaoSe0qzIO;Kd)NAQJv4zZUp(Ji_oAqa zQgw%IjVG3SK!OzRzCFHE|6t-kLcJZs&56QF{J@chG*cG4m=0Gfk zv}?=|iK6F|@OBET?p~y#*p_8I(?MAfe@uTrg)hI1^%41RM5nV0Dm~wVKc-6?RX9jC(95f5Dpy+{-bCmM_PIr$Lu!|ITN|i1^rq%7G`h?X%eDfHXj7)3YWkY z-sdelrO_L~nFmb0qCdqdW(=~V%;f{u`FzElbcaTSy0e^2zQCE+NOD7an779ul`Nu-u|d)ST-&mrgOk5 z&O%>uZ@;it-&G(e=$Oy*R@wVXo)&26#hRD;JKr3b@dQg!Si z5OgU4k<|NcD=ixyzyFY!`EWTb(_az@cp zdf2xIUnjMwF-$4Cl2D;Sb0FtmIcB1h`qnsLMBCsP4QfMyF_IkOM>92!SbIHs(>*cL zpi*c^D{|^OP}e!%lN$7b^G9@!l5Q&0(KHtW8gu!sZaB>~v2f!HD*xj3 zVpE{A}X^!_zcsxOjY2t8vsLm2vdrpw23UKK8y81(iynpW~p?|<%b zTRLD!s_W#@5bI#&F$2VEUaM>Zrf1XbQ8sG$Rn}Z|rIE*?#dVNW*f%Kb(@x~z^WI*& zU?l};gOaWK3o-OYOh;X06G*F^;&!{RxqbL&#nCg!gM1vRi7|Q~C1=$<;67$b9((%h zV}9scu!Rw+)G+{zCI7~@H8s;G-iD2SMmJZdrw6VTe4-CTr*iS z?vEErpIM9#n|u763LBoc*6 zZm75i8_rvw9h2gFVt8=e{RhI z_m)*-?Q{<^6@R#jF#5E>JM(h8I2?U>eOyLKRSd{Gx$C+mlqzvhPS${ta!D) zokOGW35nUK@9~AWq0g%W*@eU3BrEGTjaakG75{w{z^l5=lgrQF!{YUQDn{HqHK`O~ zo|^duYA``Wa3?QMJpVXZuhjI-VX9%ehQa)Bn5t1-6&2ndTgVTP7DNu=1SCBdCticu zc?VATQV64?)7GR^=`4%MGVey$w*z| z70sEfWq!7riwr$&9C=_kAmQ?%K~UXD)D)*;$(ZfXYSjQ>1Nda6y1IAFH08frd(xPJbZtW&=7%g4R zt4k_{0yL6&8BR+ZHWoI(k zuiC%jpBe-MQNev4`Ic$QSV_+DgH^KC(zT~+EvtzO-w~`9SNGyZaJJ)n&d^g%XtFlG z(da15AX45EFg*{bs(Jbe4E;`LrH2P33|kx1K4m~w?E9F-;l~gvl@jP%yAv?E=iEb2 z1I$yIW;pqup!TxaD`D+T6~nI{%VVzTKyu6$Y$r~K;;Kd8d&wN~zLp0>Um@dIX(e9L zhvl5Y^Sj7*)_Y;U^A1(_XK${`jL=L8Y8BR-(Hn=)w+$r>%z5>TypZ_Lp~!_y*}js_ z1C$ZH_(QG|=V(eSCpLc)2y*dc(P_s+V5yWOq>xX?D7cvxCdNh z2bI-ZNC(dC+{w=girFg{&3{|ap*7D{J(oqGFX7OwO`su;`2jNOcA)tb;|Z7DU}&@d zWBBY9a}I?SV$<_E4~xYfcu3C9y{(I}3sq|4QJ?W58Q7FckMcN&%7{E)4+@<$4(-@| z&!(h+-5dkFmQ5U3ZUDETw_194>)wxs@IPF68{gw=j>wQjvp|FY*+Z6pBv*rG*wxrN zl$%Q|unP669;1iMM`#S9jXrNVjo65)uU-5a+%jS$1abqht7ARmU7+Fl6tLkTYxnea zBg+J)jn__i>VBM!fxUrw&Mn0y!vRdvTRc?Rs$VLwsLk9sI5@CFo+b$pf!K_s#W-8V z^Fgb{RtA$bZ`JvNz$D6H{czLzz(PAq9g%56+B6Pkv&GR=_Kg=sByso$g$tIhWQ@C# zffi0lba?<$Yz#1E5f6*!Y|}B!6UInJ;F*u7rKfIxsLwt4 z?B)jm6h&q)Ok;b_0;6;N6n?(~5i~vlotk)8*VU=VszA3fbRZS)3SvrlieFrbM?xm1 zYbBzB_rOJK&p_QL)6crV^JbOmUp0h-c@YHQb^itbrWds?IWE|4IBst0Tifj#@pu-h z`ra=e=igy3E?-fV4U}N>63?J-qN7Al9)avd{^b*4v@_>D=O#PuAERhY#ahLb#iV%o zy7{`qlqzwDKPQ@wQ`T$OCu)s}ofCImJHHdOF|SP-8n&A|fz1xKOIsU#l-I}qg+3sv z0Mn?{GGa(EAQ3?v=9fCtlxVG{X*f9XV!$VA6Ns*enkfmcPlDV-G-E7AbL7$Y7<9c5 z;`w-b*DeqbW;9FiecPlXXd_5quyP}wAI^!1>r&6FDN()Cj#88>gcykQo^8r3wzs8? zsPHmA!z_QPzy6ZI^S(ze(1*l|sN+e<>rxJ{33OD;;q>o6Oou&|dfFDY&u9PTT^zel z*b;>Z+H9Pcjyr#^zk+Sx7y(R|;p|uzRB!4U(!Nu6L0Xwf%F5{IDHzRQlV%P>4f)l^ z9SvMq@3|PAjpmn>HO;BDYQEZj3T}mjeb`?h#K0r~ygLsMpH%fU644Sb5ytZYm@N~-#Y1KHI^xMV7C*>OLVaM2sr!K-Y@uA!jdD^> zIvbx3(yy*bvQO*fkGMr&vjIURIhH;T(TN!TR+&t!1F#43*_Bc0b`si)bopHVMSYcq z8=9Gk!s%hpw({o}tcQ0LZuic-O+l>n*6q17`)Xp-!~*F@$!tq=U}!W9e~??G zDxBa2;mohe!b@|5EV%?oL(@t2880Aaob2r1GE#ZRK6yh@~HWIG+8+TjyP7PYO@LPHMh`a#t z+j)1_#46zdZaaS${ZW8!>Xi6Agjj)PGs!HK=^v6N(XhYS~Tp=FO{!!g9M31P{@m z{n}_vbucsXep(<^_gQUG64UNnVbw+?V4vB0(kS$2RK2B|Ud+Tpz zqG0a#kvU^5xd7j6?P*e{Zpz!l*sN*Bj}|R`HbR6K3d$$E1Jaz+oy~TnWpR1>x-R;7KE{W=f*zB7oP(F^S!y;+C;UGcZLo$tO)z$XC1M%YB~ zrUvnsJai@=%+=lAUm9uao_7GnMi4vjjjo?}a$)2;%I50WoJ~A9T}Vzr@Hz-FQR3ATGyqTPsK*;IQ znQj(ig)OZmw=GlqQ@F-lX=ML-y+!CS;O#8hchV6;+Tm5CtUdkO#oc}7)4?9}@&f+k zN;f{B;7PE7vR)lY28DJdduparTbkn`^(E8?>KTCD_#eBzVP%v-x;;E7_kkqTkQ4S z9LbhCo6gGP~eg5NH(fi9Jo1K&Ktt$h1Q720&54fQ?420!A z3@mzPW@dN4x>0Ja0voV2^IsXxaIP(xKOv&90-DVhE`GazTznmG+0!J|rrf-(fe324 zGD*dhi-A7fr9FoLlR{oqvz#OzIEAG9&aJkE ztgwjWN^j-jF|7_y1RwP6{#0mjf{}`QEn%J6kC(9OlO>vD<-B-U==qvvUWTR}h3a-Q z-t#aa^>f3W^^1SDpWSl5cYJNx`eMSLX*Xxzw?R`Ax`zlfZ$>uRtB3OVUIeT(gtYa- zI!De=9}FNvMr%i1nkC)@w9_?2hP5QKqHXct1>b$SwPKv({ji_(7hv#r>F=+leNDb2 zE~2uXa_7o(FI&f<32X~CLuYlW4L8+cqwK*Vz3GEjA~W8DO?5v;&ZScqE^>xX5N6O_ zzl46hs(7|F0l8p*O;7*bk&Ujbz00}lhyf(A0Sd@pA5PtM&LVDVb+?gj`1JF_ynXX3 zphec~`bzj4<(9QFuDjx05XeeF+rL%`rh5EE3=0$W+i{uc#7!MPc+Y~a`^#&$pBFNM ze(iM0nR3*s7`R-3OsLfUdqN?bf9?;*WMdRi9N3lTni5QyA<~K6{Cr(?5*h;Rgxx=a zaW%n1;IIR3^ZOa|tw%!Lu*+RKaZ(J;?Srs#ia8GOK-&xsOS!y|nX&Y?iDMh%RmHn^pfNQ>@am|H~o>$kWR-P}Wn}S?4x)z8NgM&i^FqRNl^gNW0J0)K{ zr>oQ)$YmLP(%@NUI-2P(V<9B9iT6NYX^r^c{^WfKuklB+WQ*XLtNY#>u zxhyW)i`ZFEEJK;~Hi1j^7tBAntHg&W{254ma+yW&LR%q!aX&zoeNbo-5NGCY?EZA0 zN_AnS7W$v!y)D&G^yOR2>e{lJr^~+CY{>=|p>=*ozq;Wz6r(b@-xCcwaiVdwS4aG9 z)aLNOCv=4sz!plslxBD8z`ZHDQ=a{udGM0(G~CH5bboV&SUPN$HTq{ljyLk_R9Wd! zbES!S>>lnnAgw4uZQT+9^djdtr!L$EG%VfW0707W{Ax`q4%i@_+NniY)cA{NQ)nw& zdq`9`!xHFT?=n5l8;hO)QFwpbc(=HOzLtd)rd#q}Zgk)_~#A!=nActwHzG zml%>9gFy?-4!$0l1R%QH@vwnskG1N%@B2IewN!G!39m~3F=^2%G@kawd^ReV$A2iI zVXhgV82zAo{ww&5W9pw!Hp;(8tG=`1k$FyaBR~Im$9HZ+u8RlOck0EDq47KzyWN{U z)K?)t$wuwYg@z#B~F6XrU7__%S%65MJlR=uJ2 z&tCFnzwAP?IzQ*>4KvdoG@u_`PaH47qD^ZtYXDd#Ge0Y?cr)2VI#+0HhSD)4?UgN= zK$?nND$olWfy#sthL}VzTxVbF^;4*XADrMlT;?l6bu0@ONnzF7;itP`ww`=-s$*oA znZ?X~X2ikF_kQ>z5!@SQETT~lsxhBBAILR;U>i75(3Ng4ZyZ!B(UhQibYZXxM4J|N zVUxaa!Baeuz6D@`ei#cxxPOpWDStxO2Anh5SJR3k5y$pT|^9= zaB?=7=IOYxO$i0@SLQIK;@-MWMS^pV&<)`Kg4S?%Gf!}XJyd;ASpPvG)GQCsG;Ewe zm=&FJP&lO5Xc6rVeg1`v{p8QlpL!1PRs>0(wUai}lbi6gS}07-cz?3(2GU+2V}YGR zB_>JraiHm<9AUmjHYg{sNj6;3yQ-WsvA@uigQnDQy*Fvdf4s$CxQ|of>7)+$c;8sVL_LrW16v( z5vlN#|Lt@h=rsuoCR`^a5g^f{yXzTWyh=LB+r9La+JFR&0rSm2j6hb}*-c-MMbya) zG&Vv6w$-+8i&b9rW* zzH(!xi!cY5oc?DRdyvJZ$xTea%3=I1kDs@`jxbw$uHn|}59 z*ma|Obd)#;I=)R|e6{f_Y-JBLb02i({?BrQP<?Sj3JER6%6J1M}*?b@xe0cM0yG|p7%QX5p@~Z-L zO0~-u?&YN=&oSG{R+_~uP(z%EMPetn<{myaR(eD5+9z!a_=^&}9}R0Ej<{IGip5$m z<8vuLCZsI=k3p5k`6s(O0V>hl3QhS9X*%Va150~Wa}h!Yc@g>Y_;R?iV)v+3@S=19 zA*6?fJRHgvzSnl`u+-ifjj$;4)jhm^q{u+Clr=V~HR77o=Pz90eWW72OzbJFLi5i_ zsNVpUXDhxp@_h8ePNMVR<9S@6E|6>Y?jEuOj`1;efn5ohszW1!QwKvu#lSD=ihTu9 z>UwPX9m9lkvkh-1=4GE^BF4;vb_&LCUvYC}3;sfw9T-!sFy%>DaCP zrMxo&e!@kJ5SqsC=NBESn*(LhBNV#hjbYEDbK~|e4&>HKKpM5hl7`xcWa&^gG>ay^ ziIf?oHdsIurm2GAPgssC&k`a)^)VWVE9mpE_!mg^O()r*J@;fmFs$)Q2~RB;=a`qlS~o z&a;3Stw+Eqv$1RPs-jqx5PzWpwx@YLI{Un*?U~J|tU_XL5OU(A3&MlVDtQON10%ry ze7M*Z`)wHmkXrh|Bd$u0QWdRTNwS6bG|X2yDo1|520&23U9a;CJC+M{r*%*EQ7g+b-oj_H_&yjIN{B=&gwN`bF@oO@RYXTk z9gJD?1XTDIVg8u4vxCvmKf@lwUlU(@{CL(9&Y^hWer8Bqeh?Z@mR8+-*nj`6CsBtm`HiH+SZ5J}v6O|VRAcD9UI==pV{rFiPmFv%{?F6@ zX8*AA{~neGxMje*z85U~Z|1?WQ2^)?yzY751q5}$&vY%I>jQq$2**WIt4x>ENX^033VK#BZ1(?d@Z! z<8$l&UPaehjgxg(W|{=w?4RP`u8Kl_yADkNb@m;_st<@gIL+;Wp^eT2lF@Z8;Qb#r zg3Ioy5!BovAM$r=GxHJHxC$?5?6dOsecw$}`AGIVz9buULfwF(7GMYojXgQ5UfWB! zb}zcIx3R6C+D`@v<80qLZN*vsM2qL2to|^j)G$7j*G`_oou8kl)jiwy5c|WD#Pvae zB_h`JCqOJ%Ru<~Li&`m;QMak0i%8a{MJ-xNWTYB{=JsA`#;wiU@oZjwt4>1GyHs}!X*ClcU?5p5IwpD@4F|~lVr_@=!-D^ ko09)*=l}MNEB%fbiW#No#I|w^&Z|UIR#aDj%UeeNKmPK}r~m)} literal 29971 zcmZ^~by$>L`z{QkAQFlo9XcXNcb5+#AObpq)BqwebPb&%(j}b(f*{h3G$_(Alz>AH zj4&wOjeE`W?sxCw`yKnkKRke&b+2`;E6(dYuZei3rAl#w@dg0_0foAnGL(SeiUt7z z;mmbn@RJ#l`C0HE@oNoLWrDx>e;-;46A1|J5~wTxqvMseKIiQ>tK0f_X9~_?Gw|~L zm98gL%Xz&^Z$D!~ClooZT}`fhF*YbllYc$(1BCt>-S=zCA8ONUY5K?B8r@5;U7n;M zRB4%KTk=?hs8!s#!}N~7ZxDB+T1c-boSr^7n4aE}6Gw70%@5v&lS_QR#fi(>lDZ4| zpI=ZZTIn}xt!Xlzj?|TiRc45A9z_%_-yaGVMO$s9RRYKXgfYe>v(Ms?45_3XN*AGg zdA)_-jj~9NJ4N{k=V`xQTY}B_rx4UVh*GK1m)L`~DODxh`)L|dmPg9U%J~^Z`nRd5 zsQUitN(c`RSEB@f1-@LLRk4GeBm_r30Kbf9u628(b{CFxpR6=(-|1%B^O&S<`?8Q__RXL*28GE%=uVVrB%5Ue5n|+Ll>28d+VcKm9rw_OFGww7RD^NA{vqENgKwZua>{32U-S6nfFcA8s?W zi;{ER9vLCq#YDL@`UXGtm7SjI84IX#z#(E6LrZrZoJzM!esq2~$?|Pj(pEvL*#JwB zTJt8BlbFh?HhrdbT||9(#(ntKc$3WQ9&WhMnfnk?Dmr9vn@i!221K}2F?7D)+l;@< z`PYb99rW;={PGA>5my)Enr)K9b4xp)RUhvIujgC5<1~@d2X*70G|5;BK80+yCY;tf&Ph*J znEpL}dyVXn0;ysf2Mmk9-4Vg8aGemC?|ek~yL_fjiqqq=koeO)a57>Fi61XeQ!yOhD_=bDHN9~$ zt7t_XKQ=CyrAAQD(h;(0Rvc=Q^u+3+738!&5OmA3i3k)@YlyEdi++u zw@WBziXy-<*C5o_Sc?Bg0psbw(d3z;{FW=F#)|LeGo_D^gMLMlTSatxD?`5ae|{8I zAjKUFS06%zzc;zB>9+@5V998Ce@eK~7RmkhiaMPk2`|dcid`wT-dVp;wqOTw%U*b^ zE8+%(s)*yiPyO$h2HzGzJBMZ%nikN`yK_Vi4Hx5~*&j#DJLTXFhy4Zbk6`_Kw7V@1 z!+i%Ad@8h5Tr9xDb*=NsmM|1BRo_i(T;D;~SGxVtNzMMFE2dm0Ex6ai&uzO()e98W z^LIg{38P}_i))j#+Dg2l)ZCv}u|t(^@R<~wtws6y`h*^OEc-a}hqT~oP||B%fuZ%u zB}0oQ60?%FCs{f+lFt-BsI(#ZVM;Zf2(S^3f33~9u# zr#K-_4qX=<$30{QT|nQD2Kg3VgdJO zePqt}LS8odrafuY8h=&b6E^|dj?f`G;EmA9t>QJ*kE{>ne`&DJz6m2X{S{`ik6__R z{<_utUS@UIdk%wJfyNHIZ#V7^<(Wyw&+@tv#QO+2&A0S?(n6k2+49OB%z@=cb3ZU!50~qXm zK3Q()23SNVVwC?wmx(e-pxhK<*Fe)Z)0KZ;|Fhy@)xeQ^vS5m0?$4=|UH6mAmUov~ zDo_3a{z@1!Yh9ma4wVLrNN4y(qM_r%QPG~jaf@L>&3(9LM)$^FGns<5UwEbvWMb22 zWue1G&qC}SsyA}Jnlhbl<(e{`9zgfcqie7DiJkj}(AhnBwzMzgHjaS$)iyaSiU^D#f7hS+|M28j$ZRW=^P4Tuxaae-jbNA z8l5iH>!eUw-phDG7jtsn^6nTsd<{e!q0UkT78V#1=TXHazJQ6^ub6`ihvQ8(@B7UiV60<$H(4WYaX6<8U{Jo@>g=!L0_!*uP)b7hNg_qEBY zfQ!=}I$r%sr&V64FYu^;K>%?0{NiQCj4{FJaGkdR5)|2Thbyy-Qgr^unLq_mR%Ryw zr+^;qwmwk!9ytYpUH~sqn=49&DDPD%+x{0w;D0zl@3>XD$a?eQbOc9vd8D@SYZ^F) zrnTzy7AWDOux>^14vIR1@?Nj}0wVBc^0}oe^d19IxiiN0po+hwzu)SZf4IlM&BTu= z$KKzVO6Ae38om=>^rT2Q=f{Kd`grM3Gx5xD-N_r6J zb^J~fLzyDEacjyJ=VPE6{%EoNW5#HMf=U%(sJR62k84hg$NR1ZI*E+szcd3|1xbS?0nTS8MMNEjnj`Jo`0am7F7*t>{flF-tt(t-H0w%Dy~*ThwxRh;Es zEK3ZB#=fvg_Z(74+VGeYa^1S4@NJw`T3b%Arce?7e)``#_>(odCiB!efK)c!K997< zMUVHp@5S9LQ+mH55v$ZN)P3P>8x$};k`yHo#KoHHE=&7_ppV1%DprItweH|}F?TOK z8ve)Nc6@Py+KCJ0LZ_4v+MY)dN7_F(?Q;_JH7HZK#T(7LM#iFUAq&OdV~lreTUcj| z6?>0=?$uW-)X|caa~@Q*A+h&`O~9Gr|6m+1wCGTK>6)-x(pq);BNlYADdQiTxO^{RH8z{%!fKQDEmaX$^l}PSJ(Nyf z$jB_YEx}KLRJD)=g%9$NjMX_94hI!Uawr> z*X(J^{R`O2$ybi>L0a%uo+YlotlKX!ntf>(_rXhj0D_<*&2ul?T5=YtgoZ%P@-Ena zo}L*EkcR8L0YOL#sZL)D>b@ktom=xGBcx|~L6|}7T5Q~rkI||u8et0zEZ9BSTaCl#&Eq1T0o;A=P|JYOfV>)>=N3K{S;wd*V1MOAWI$q%rjW-L* z(MCooXYYVD|0LssJ}s6q&g)%f(BGMn9ymC^JGz-f8}ZX=*Mk2hQZ@hITZ#1E6_mfm zyy^TWlG?$1RrcU6L(N}8c}m#Nl-+dT1V8TcvD}5+5#n49Q^o{%%Fj*MFI-0!&VTnk z7msF`?8uacPoLu77~zwmoWDM;cX~)XFxU{dMbaqkmhF?2{TmL4& zJ<=byIab2izpcko4!lFXh)Wr)3}nm-8c)*iYWa61uy?K!uYPk%c)AdP2Zt75Tcsja z3WRM-D2dy0m)-cMLhw&zO3k&&RMIyT)%0y%N5W;( zo*+cf-pb*r5Z(yVb3*qZ59qW{0twn(kFE3u`N@#*mM8nie2&b?T6^6ORA)@_FVw|H zOu`@iHHr>l%n?PijqdOF98X`fZV#&^JuuXIl<$S#QGWLHH@Y`Ob5eZGEMZq&FUZgI zzDo^ZE*x4jBsieFcq0ir$Xz;SMKSZQ+SV_CaIO4|4j_b?Z6`ODoDbo51i?Rbd!xi3 zF5*bMxfzMh8}a_N@JXTLPRFn?LrPu6{)Q6RkQn}b?7~DaTxF}6^UGDrc zklc8TA0KdALwx7cUCOu2=7QA;7I#=OL`uWaIV{sb-VsS`bihV@_#p9?`Z(pOwtxIv zsXcr3u$7!PV{gM^aFaA%b9eksO*35`=3KvOQfv_n)wy#+-DRiZG0(#D1! zd>(W^QU{M~6H>`VnaJsx+Y5qJXQ1-fqRxhq=p*GU5xp#HCM9^%=-jNuaHdO!Oqh1| zAgAHhPB5qTie3i{G5d%oAc{O!rC*s{V23sEhIz$$r>IuabsGf#S~NQKZD``#t``AS z40;WTLgA947B?>tr$kSGuU0-Cc>~c^22F`@@uA5=;IrJTx4H;OJgqo=&SP?`)fZRX z&NeAkC6$9ngKs=|V|;n;G0)1KsU`*mhWhwKNkmX^F!y11o1-j^_DL5DOZftqZaLqw z$VVzxp|psbGEJ3TADNAJUO{x9w*OSN(8*q;_xrv;NAc+Xc5)#lcJpLTzUu8LyEZUY z#L=+?`Aezw?#V5*GY7`+a{^kq7ztdzugJf^$*J47lDSa4pmNujkU$g<%9?w3B2)N5N8P0x2$(e&gb)WTr<{WuKQ(urqR`@{*_h~ zZJIdbQLDt$&G8}dU130FLZfnVI(~C~NONGDb}PY0p?}424t;6H!RTIp8fbFU>v~b! zmM)CM&wc=+fRYV^%YZeIgFQ8T2wh#HYSAbF{BhHifm0yX}VWqI?MmQoxi zP7wB3RpWa2n|c|lc&b_uNaGZ;QHzu~&o29aR-Zx{B3SUrW;)z_Y| zGoP}43EzSR^Qw)B-J`sOLo__c>~Hh!jfi)7?kN^9A(7cu_KKOqI#`cuoq-)4?zKYm zlai2V2-FC4{|R9*x>v?oD$0K{BOerLbW%h(oNdLoiSMr!te!BG4>`o`{dQpFUsH?Q z>w7=!J9tzxfOGF;5%`Xo`nBiJ#E-RZd=g*7=)lxA4bSm65qA@x9ht1Jz)7c+l;!s9 zdCN|Fll9$&YB7c;Hi^{ULLW*l+!J~A{a)=?x=}x$q{p@*Ik=nt#^vT8`;O#jPtg>f zm!qt>O#g<##@IL=zmS-DBpYoFvB1PCZ&Fz$o z?UUg^dAE1{;mT&;Vk>QwR@pnFL?6{sol3l{pVMn$T&ScR*w?F{`}UOAljvy9)3h=3 zv#RCaHnocvRqVPBWBKaZpb`6>KO)6_@8VP9g5w!;0C%Q@Jhi(2pQr~?zcaO@-aUJEUg4 zsw!I|dlx|w3kqBOgK*MEGu%0}F3`=Vv5Zyt+zCa>q#h=>%{;na^M*F~BZ0(mMCaUZ zQBPi}=}Tw?AgSd6L?_MnuiHXuA+9+~cL&qcal}<8MAy_7_?3T+p&v-l^mxpLY8*m) zp7GR+ZWCc1L70t-2SaMx8-vV;B#Gg)f}}XY=sOn|vyJ=uzD)_<%K4XgVx|&p=l29l zka`6!BO8lw(W|-mpo5D$I!&jHa#*|aQ_o!-tx_O;B)-?|zeGlrLO4W)%~#R%@GP3? z?UAzc@6pUmx7;>+MO%5lJ2-n$M$}br>Zz}+GCx(3001}K`4{(`24y?Zj((J@o~u87 zAxIVx`wuz}>^>J)hn-0te>Wp@cF`Lw=btzsu`}2l?UO;UXnl)DNN3ucNlo`nojc|n z`@K7Q#cYRC@6f?KN4z9gHmLvg@XWl|4+3olj-&I)s2|SgNA1|>V0a*27FgluE_5kpq*q)8zc zWxJrc6j7-ft3%)osQFl(3L&r%C)`I;j;WVF@X9EBs3Q zH_(AO-oBbGwW&3CsdYXS@v$?;SE0ijz&I|?%oAI1B&5fZGo%)iWnW2xW-SayAf(#Z zAW&1V^`w8+3>O|WrE3%7h~kLYw7YqAW9x6X2IR{e5j+p&70ry@ZhAtY@BkXX-0iTr ze|X>m+JLe@jvH(+$#lexN*VMwuJK;zkjw4(MbOi7<${hv_JDHbHEi*H1bwRG&quCZ z5h?ttzIeDQ@{%aVo-f7Z^^&qjQ$XlN3A4jZ&e4r9?|02ZUKX#e^a!Mz{Vmm*2?2Yi z=FnbI%c70OzUh-ZV&Y}%t%MCwh4+es8+~G-RndNb2}aUF)gaEeOjeMcDynZ3$3{78 z*L^jVD`^(}bHaWmwd5jxQ1c{+VU_TdSE&?{a?v=(a6_zphO_O~^201zjN~hlEZ+#{ zwNIi8#^M8~ig22EXJC=&=d#PqO*>Kulo*zi633Cb9`9N&^>23*)^SMw;vpfuESjN4 zFIA*RO_9&U;6|C9Kh#a5zK2x)iZb&g0T1J8BVw`YP!SUjftrEsM*bLGjOVgCf+9wLGKT(e#CJ_j-s)?f)mj@FxR=apKazTT58$C#ZZgTY^Kc=g^ zZQiv{x}W5VCZQ@a!LRpzF7MY&htX_9kfvY#nxt>}Z3j-Di-f148j!~y<0{)f24^DR z)o86!}&>Xxv{>EAut;58X@kADhkD0Cg7^imXkE4CCcS+>sH zl>*yF!7~sB#|h|F$bl-zwDPlMd@7j?rq{AP8$R$@d4|L$Z!|V`Mt>B!CC1q~ncK+M zVF@4~gXB_FvCB?Bv{%bofk=}2C-w0IXAx(Fu+`t|j9SW16uT079~$bN1dNhP5QxnF zwjiT>Y1``{3g17aq|V|Lc5eOZ1aXe&WOBKyXjk3mcmwHDX=~ErT56c$E80x+HJ!eP zhyl^2@hGk)}ybG5e(#j(#_e`J7)0TPfT`+Evyk3CN+th1|Ue zH8bEl7SDDZ>?eNmJRi*^*3&Mo1Z$JkH&0yilKW<4zGIh93j2CiVM1U zdTcl4E~Vp~iX*ehR-L3+x0 z8Y(|?S3TqJ=dKttJ7B!3)z$6Z#4QZ6gTX3`SX8o99R7P>-A`}eR=AD;z~=@#CJNNJ z%nk&)c{bpd^mzCz-~2!)eH?q{di01(r0zhJUaZQYV>h*nq0qcdx3s6D3*05VnMZ{k zpnKuXuB{zC-y|lASU2oUB8Rj3gQFKbk7buti98b*-~Zx0(_NJ{7qZ^zCko&GY6xp_ z<;CCEbGSIl{#6r$f(P8p2eM!w+$kP{;)HOgSjZy2eCJ+i+7o-#Dus~A+z87xU%sEc z%SJfNX)ey=mID1;*u@i-Y)o}|VO5J|zS)97vCvO>cCAkV8%M*z3NTwEY(+tiid75U zv5yagrEXWxPj=afgjE#&xQxd0*bk zOzvKihMa(jL21p_q29j4*b>SQbGN!xlbXZXu5P%By2u>>o=x}CgHQ#hm2t|{D>n_2 zym0Y{Gb4?WfN#+9oS&NNSu1gvD}+WJo$e5SncQ1SR&n`KZ!%9ZD0VDZiN;Kd@)|PN zgb@`|7ioaS%Il6!FKuufB9tBt7N-}m7bUGUXm8%XYtANmgR~*27o=F5o&MLgpTi))T%whjT5qa=dtb&ZCijPKZCw^=NdNHG0SOND>zKZG1`7H1<+(Ra;9OzT9rvBehtdEX(7i*Sx@yz(NqO;gASj?xM6O`@Zl65tGmlAHJt`UXj@Qzc9 zL3tW!jXFlho&NPpZ-pxyR{}TJunM*pvAwPur8`CYh7l9i&sHmBY}AglMIt` zkZ3n&qUPbyh?Lz|JeC{Ej3COnD^tPs$It9}%>~3wJpLJQOU>}3V-mrXD@2=FlN0s| z6v(34C9W-EkEh-1t$-_iJL!9l2_^QKOTVK0CiI`M9HK+@?sYb^v59Oz__|=6vR-ei zWA0|1g*#jBKHQvS7G!XO>&+18np}Y3EuwOAWWmdQ zra;%ixH1)J=ljkXLOMNp-3>#p&j+B*w-L4?Y2IU%$nHA%rzJHEkWS6!Wj8OPRsN*- zq~zPymG55U**JFnT)?!T()cKmMbM?z01=c?p+d($bxoJX2rxm-RJkN~6oe7<9Y{M~s_#VSsOKmuW@s6DgMifwH5nr(>D@iJ1JUXnKcK4~OTv;;-YX-Qx#HI}T#HCGfNlkt#J87udMi z?YTBRj&CefSUxNagD!>DP8+}J8(`DipzR3#>d>Jeqy@m!{alfdTiPd< z9VgVB)kg;+>!!JTKQbnL{f4cRM1sg>e|Bb(ckYX;Wc|#uS}XJWb}9~VpyTZ6iRlVz zvx8-nJjYaWfRzlXX~7G;O@EViYZ-!xvO2$e+YI&XzJt=L{ymE?PTp6r-4=<)jMCbC z1Dk9T16gr0%t7OEtv_dyx{s9>h$+i)?oEoe#%qa;;?zfFa+)uMXyKTs>6vG?fNm$X zI%LcllkDK@c#5g%ON&{X`Gw_Dpljepu83*G*0%$uTL8~Zex#EBBRCWNIQn6%SuKE{ zpGHpp7!0`PRPLc_n-HXe6ERF8M1BSe3s5_-*IN!H=g$TznXN0yIXzI-B#Q7GMV5`K zfZ#l$Zw0KKHK4{ngS;&J-mG4Vjp*>&q~(`?81y7=y&J)+AD1ZRddlI}Z!svfBms9+ z?Llr$#4n|;1RWS;na%x}xI5$WVU2sU5D;N#BpitkwY%2?LDsU{oSYmWfpklylOK7C z&FJRdkD&|p$&kOfejO%Z_J+qvvOAjssmV?UTtJ9#!2jE?J{U2+ittAD`aw-A>5EVA&jtp;!EJt6+9&N!Z7 zxt=c*1Dq321|~FA0PQw67E?+<>5hA6QR6S+_Q`g%zCUi4JS=ULReInVA0OX(^#Fga zxf(?yHdcoC^z_tKp3}DwmpY?&cJP~=j?vF?*J6bedf77r~hOJ@i zP8dTEEvsFiM)&%Qcu}YC-dC})UIGeQZf9oTB7i2uMdzup?-eHVr4gZFaYGf*iNo(= zbsYv9uOGYXQ6Gh(Ah)OUK5pDJ9-6$uOib?eE~m@)y#843^3Mp`!VfSwNwAqCf6ldK zT8Rwur9LYoX6YAVcm!qn<|bgoLz$E>`50<)h(thj8;>rD*bS>UF&(+JSiRF^UG}aZ z`vF(cq;6Y|=C6M+BhfC(@TVbTYP>@#9f`i0nDP+=<>KdhgOkdhSU#&k30#s}Mi0=u z^aosr8_lZKia|{?AId4^xOw4gMd_1Jn>Db zti7g>_E2J*SR#c`PcwV46VY@L4$gq5A0JR@dqd1;W2#)wM7P$Y`zJ$CIzz-+ah6#) zar;;5t6)Ir)$gZgzIuuNgUH~Z!uwQ{96skMhe_?iZsJ9O05sZHQ#S^wIKpydBhmj> zRCC=L5g&h&u$sZfmr>j51?kHsQC_v!Tz9dVtwf>B5SJ{bt*4!A)N=Eq)w7(@m$vas z0QKeJ)Ao)ouRHd3mbbCyp^&By>zp#2Rj{Z%o=Fi7lc6iM*MUs2ai^54033aYRLK4w!&tqt;R_| zz94|}0@5S@RheAda0>Azk%?;Pkq2G^d|LM!!=OcEq8@6e26~*pq7$eOX1jUR zlH0?bE|SB0zcmcjvnvO0lj<4k#+c7cGnZ|^wi+4vvMl2sn0t_SlTc7bOSVspWF;j4 z&s59nS@?NtvG9?!Ide*uW%~_ekyS$`10CaRitO|yjkJ~&dFyrDi(53iEwBoq!&677|j81m>8 zi^Mq^;GP;XbVPw!0SXG&kt!A~Ye4vdC-SXt;V3%p6Cc$d9LE&8pZyv^=lg(APfY{c z<df6#AH-;4(hDqYNOvrd%aN za>IBjvmGymoNB>BVv9~S`sGu4%)w@cD|(vbJnzDirl# zu}Gg0H$8c5H}0GxLlw7OZZUYt>GsJ-5C9LxtTohuVaJPnk69p0dUmg0!64(WH_s5X z#~vL^{jp?R(BX|S2O%6sQAvBO8c3w-#$ve!Fdv-&eOX7ja-+B#nCOE6-XiYlVp+!> zdc7Xs6BpkvTTIfa??!J)zj+rA6j`@`Su)2Uqq-RoN`( znlb{&pk|p8PO+h=XWZzy8|Bf3etebeEQ^cE6@k@z4{6Ol860E7BMV#}R&^Iz5$m%E zWyjf@SqXnqEK1_o`W_bK&)4sgTN6DId51?)wKsE1mgP|P)|r2CEoZFqy+qW`RU)Fu zhTtJn_v`hGHpf$^d04_@ldx}x&EHB*z>d^g2WKwXTHWjKMhv=xmA|m1 zL^wx$9qs5G4VZ7<*7wb&!DWwcG#kA;F&1jJ&&SoyV|^dzF)!SyxpoaXJGaz&PVYtL z93X6k>{_v3+tJS0;d(`fDU|$jDB)V@6RlBE)^k(BT&S{;fzDk#-4R1iA_})*P6taK z$^0c1eQXwbqhL&9|Mbj-5`kL-9@z}$FFcL<^?cr)QG9yEoNB-1P{5sJ2!w8{S-VQ3 za-7)X^w-Y1Up+O`Pxd1Q1#xyAZ-JfR02D%>PL^9W7gxl|F=xC{F!L*Od237wk z8@TSze9K(H5q)Vk?M1>iYdfBqqlA70IC%&x-M%`xz#f}b*M?0QIxp;;c_YAXe%KhF zEmJrX7p{Dq%W$;euCT>tRdCqYdWnigkX5!aA(}Eu;k+kcc*G;o(~85H80GS)+bl*( z<18C{21*g1xm3IT9nDeE#OjaPYrjM3 z#DN)&#}bzVF&}$;suEM}G)|t1@b^fOm*=^?1JgL2o*(@6mhG<{oou z!`l0&q}gUb-aYmbwwj_DcRaIQkP_)|cg*_JT_=;@xH@f6-?%D~;C?uF897A3%oHTT zJb!bakVoj{)0{`zJ>*REc1&1z^3`QyOxo{DFZLz3&d$ z&PcZfD8mykoPZ&V`If&tjt-WNTheTL@kx1>uPxGiw($qXf!J=W8%`&I4qmnfojV?J zYhma=5O(%CL#xq`vwmlTnUT3hV(Y7?A`J5_UMX^h_Mu*JUtaNE%@)V~Kv|t_y&gWO zE}d&jRXx70Mb_Os=p{|$8E>Wn1dv*tjc8SbZwr^XTebV!vn-3jCw_%NV6wX?7WpqR ztADM9J7dwG430Jjsj*~|b%E0sP>hr197dqWE?Wbf;EOPXC<+%OA>~HBxM!@2RAtt~|X;EEq8NCCIZ>a@2KBG4;hE?za`@8RkVF zN1N`SE3#G73mpWUjV?E~r7@%!N>5sV`nNRDlU}1ulb$v|zkivNoXB!=@`{c6cjf|@ zQ1zlprx09yekfo5thcfBH!6+TYK2gg&hQdfJFO&t6VsX1lvO;WR^e9+Q6QEkc$nbK zY}S%We#$%lqP~=(*=UBFRyph4&BmRsJm&W$7xgCX-NJ*NY40zfj16Gyi>K#y5nep0 zOV=hy#g@h}mXVns2AWIZ)BsD;L7qi8NNhqXYm15`)Xy_J`)27&LPxOH=WOVja>4D! z!2tLa_lGh`&Lo24i{a&I7t$c7i2KH9+c0CaSNuNJpxf?%HV-dEcw`Lr5vN|MAa?Y` zMJ4}PRNFt*lk4QHOkKFgya7LgA)YO9nG$CWVju&n+Bdf+q3bo0g;NVuE{-l~_K)*^ zB%(?1*MX;Km92$vIe zzgS{3MZXJz`SCRLqv*}ta{#Snoj1Qnw49zY99DqNxerKF4MP3to3I<}gtK2Kn}@mU zRn78xWQ3{sMc8)FMhNeVTo5uMjDOvh3#ee)VmlWLCJb9p@x;D|?u%yQ9f?sdU1$oa zLO}$3R{Y@hW8wcRk90l??zDZ?l^@}!s<7t$vngfLyF+j8#OAxy3o?UA4q!eGJUfW< zL&R>`*Kdw^|1k!UB|q1jGuT*OgO&ze;+_8x^;ey#1iO%#5Y%#V+k4PR%7)pwo^zb5 z3R_7{$v??IrwStqlM*F>Wk;jwy6N{891c!NH)qvC!aNQC%{NQ*5>`y2=|UK131@`c z4K4~f+@wz&+w4e(u;-x%_G8ABzON4NM7&ppX*i;Qspdez+!Fs9iMFi1%DB*nkEag( z7y3BHi2WFUevK(7#_=p?L?w!7#C^#aRf$~)CJtPUMz0}|obzjeU(=<(E!L_^mL^e; zgGO;aom^v1iu`zXpQNEUp;KljY3q;kQxC4UHwpe;-Sp6(2Ap3LwVM}cahs7ID?BqP z^lI84{QJny;H$6%Hee*kJeJdZ_RscCd73ec^sv`^RLe?5Fhl~4a z`)6!x0Pi+K{UOTUEbVnqeYsC7grO!;Ra)DF{_q6m(3luYujkRdo*+cR_S!M7ozHys z%6bsOqZ;if;LhX?S3e2btZi^%+-9?H{>a}iJQs5Y{a4>myCQ^%8s~Ivq$MeH)hTMJbd7Cu0QD!|LyyWOTq0Ki$N_iWWltB05KiGUJ!1mG2r7~jAc!!fLs07 zmHhMfpZ8qCUW8+g+o$xtp_iy=-GJEg*vJ1cwooDF=bJ?FPT|% z^)J{;ar_0R{JSn;1<;$+-*3rdps%n(G>L3ab_w}Px@Fr^wfC5AQ25PedAuUp9%_?s z)7>E31ARGv^bsNTP}(X3qu{Aa+k5+Zp2t3OSxIcSgG?z;6Nnh<`E5@GFbXa{ESr2s z!qC5}VTn;ZJlVT-l$p)1X@Mabf&49&PM#xdPPr}W z?Ct}RNO8^9YQ&@0X@YhMxK@5p@^5m4i#%n^ZMX@zM&_NmlJkcHBVd-L3j=qw535l! zWpgTb({`#?brN#UmolB*W=_@9a6+sZ=FrT2i$@n+2a4zyK9v!tS+VTDKL<8dy_W0e zzgjEo^|y+?qj}r~<(qEu=yB+Xj~5LSke+O7=J%&!ldmM(dUc7+Bh&!H6Y9|Rdo0Sm^%Hc~l z%d9SuSV+n4b^K?=>cZC{hbJhkHE6uqY8rcII9|zPxF7q5c1GF>PS!0Ky;pF(x;0oG z^LNZfi@z)H6O<7c@R{s#Dq-r<_x`H2reCz$C&rS#oS7RAxi#++R(B+tT<$q@Z_9*L z$WQfD+y3tA)$>4&vQezKciX#gq0)^ zY&+yNLi41uYba#Lkg?DvlamIRB|B^#Cz`dTqIAKH1A&xUIuVosDRjH+=J)g*`}#E{ z9D~!!Jhoy$`J{}26AVTm@xsci?&V7K9zz!Oo4>g214G_~diDHs;xGe$|Mf3R$}`a7 zz3vy6l~M{D_Vs&D+)=N|8Rv^4>iny_*23P100~RGamU!xkx?5#R3n#}Sob=^yEGrmdKO|_s=f+!T+o|p zv3AYXo$Ceq_M4`M_6!~CgMN{Bxv_@lHyh~noOyipU>=SWw_ioc6i$6(R0~dlNV5D) zU58$EoQ3vnI4eftd45N$wWEzB0ErdcKJ7f|g2wb}&7L>P{2i~9soIhL#0EX|-M)%C zY2>(=Oa!R=3j<3BiSy?DZ^_HEy>$ryTk=W70;7_0OsSLoTk-#BP-R_xYPrS|E@4FU#S;*qLD=Mp7L$dK3kHfFV{PKUD3rRO z6usp%t&C}uEpk7Kd$7i!HFrtdgR!0IoRw{xPXP7C3Kol?NBMW){@4V-JQ{E}|1%8O zH{9-C)gMTJNEB*r{DBjgo{Xu-HSK9){t^~WK?O7iT;n!H(;0|sg0MjwF07T;H6%VY zwoXs(a3}v~j)K4Y_^nbu=BY6Ww+7e-P(gI*aaI^(tj%m&hQ*Pn?`>R3pVgV`s;uRr z^7d{lr=A*{WH){y(8-!R&cmMlD_uVPJI+$BQS8)4)HW z_58vOdX3ZcQFv7^+H&PPJ=HPP|y2CoWx9UGf|RT%=S1!Dly zFvskgQgQ-eq};VW8EJPc5v&1vA7iN*#*+0(bz}$0T*F}_g_1Jlh@-;=*(OyO zN%QMTT4|L2;MQRT)5omesDcjG4weo&Tbs9A`k-8q(2pl*wv^qLBi~{D8>B+NYF~Xb zwYdyxt#M)>yyhH02hgZ5`@P{B_B!S@-)jR_ z?v&zZMtHOp;sR@({bXDM#4uTuC&YO>FYN-*La+bxS(MuyDjhVQj**h7abF;^&6-2O z9ivgX6U!eXDN5gNCKXPstq zG3#r;hckA9`JS)vBW(h2B1?XR@~Uj#dnFTG$Iy^Ioim34%=WzcT$ z=}7~NsQp_e2QMfuh7Wc&ebPjp4OH(D1}MMtW@b!K-^X5x~%gee=QhlHu>Bg_i>vCqgsQugN%Hs2yCs8wCdi7U%PtpL> zp&Ap{i`T5^j0CRz6tp!cVK=w}3zKA!G z4bx#e7seG3*FMd3+#t2lL5#@+hbT!A=q;E8jc|nHO57toVJo_@-uK2wxM4{VJO6>S z^|E6LqOdDDPsDf1V4in8fZA%i6~d+bx~@HlP|FodgK_Vm?qJ#EEuSoqs9rmmyS8rA zU4+!E_i4b@6`X5QFkIeQx)}-P^NViO9vt5gq0AKQV5+Os_d>U`vmtP$wlFcd(Y1;` zi{m5)#GAsPl5y%rmp<|t8fl}tKF2#hh}Y>{Q7>he+j|;#&=xtQ$+rvxjI$I`4~t7f zbd3yo!9nj5b8((36S$gT$#y-x&ag=T25!xlcI*5m>Wd5XxB8%oF!t{k&#fJo3HQq$(;S2=S5j!Es{l=7>45GBYpSc< z4)C$D2{yZ^$RFa=&>$5(x>5x_G=^J3AiSE}hJ#N<-&#K)YQ*9b9rhaSI~~IK>Non+ zSMKx|aD|BXWesn|u_tJ8_B|CAS!ndjj#FiQF9k<==cJEk4g0k(oUnS^VIFT>fnR&O zbq)3d#`E{Lv|Vo1>%QDe+Gx(82cwneQERfFoL<2_uQBPId`U4p`G^1LPJ|8p@?r7S z9?Gda{e^PQBIgI&1{j7ArZ4U;s#SwC*eC3tJPFx$7kVNz6AOAQQ<~B)KkjQ@@p;7M z&$E*!URFfg#`En#F>m?m@_=T|GE%KMfT)4^D^Zdx%3*ozj)UPv>@azfRL8YPA>X(^ zxWmMbXur*>9td5e9U`NgIB%bS+^Txh=7c)E!QG#!OB!2m5^HQw^((UYM~^{~vszxp zcqv(dpz`zq({;U5c~w!()Uw8D?YSq&dxSR$lJj8WFrJvcHCQ!Nf##v9>Iu!ZYRHyR zd{Xu`2cKBnXl_5Jk?k^F`QCmUayqX+3miJIe9ywjAEr>yU)Et7KvMHi2 zrzuT~T0aOHgyFKU*p_npAX#EJRdb7$H0!2pw6n1r@y(>~6p!{kv>Tc6^{)Vh6ozBC zWi!>Ib8K8RPa{*U822nk=9;{ssU5WILzmn`mQle)SJ}AxLUY=S=a)s-QAG1sSfA-n z-hMr#R-w*b9{5O#)aLn)q*GtK^2TkjbT*Y|}DYta&f zXi<|OIuX4_q!6QzZirq&bP}Biq6edd=$X++i#9qz5M7L3GlU5yM3gA+_WQqIp67Z# z;JVIn_St2Xd);g8eHLFVwAZBfg@xbh3E=rdhj+L*+i9-48o>aeer)YebFT@Vd4n>a zX6_G-TE)uEuF(jNNlghp>9k| zl9AYq_cPcC*}1MFOSz5!Tfpv6Q7Bh{qUZhMW|a8|CA{%#fUtVFQ>bVcjae66y^7PH zz}#J8vw*j(Fo$PTW<73U>=sLLqdaztXa2?Hkh;o$FJ*%7Ebqt;)(MDqQqHedot88i zvJ_g$K7HFSP;O|I&xv>8MuxJAC-$Tsozp7*Wz6IzvQLZe8X?xAko0K>Z2|g))(@y2T zV6Zfeh}{61QPX}6mxIF6a+Z1>mb_n3 zal)+5AbJ-0&nhd75vf2FMtpMe-&K)jq>c4dbVy36=P^jUtGfQ~_Mbn`-$rE?e(ST* z4T3>X5yGr2Me1%6Le=Y4fflzZKYdiy?1bWVQ1M@!T4hjc6EneHYQZx++2Xz30{%SvH1(qg+I&Z3%QcS1ndTc}yCsR60$2L~#%pm2 z9%vXCMk96kS~pTrB6nvrMa7|<6Ct`sQts9gLL<$?;_&lmHckqngy;96IlkGvOe{MX z#Q?!$zAl%|EVrMQZ#n3550&zGuh-|X8L97U*+Fdz{j-Lb84Re^Yz{cyZk&>x^@EAEiRRiZG1i2{BRj$vC!`6#Xril~=u;;a$ z+M3N#cMtv|nUW_=In{Nc^|;y0>fhpxBS)!PIQpcKqr^R)PnzB{p9KHcP%ccmN3;Uf z*qLcRC@*YfvOt$C`lQ=a?M~-2z9sq7^GS4~JvF-4 z`q92;Q5uKeCCuyV-`bf-2-PWRJU%MzxG{QoNIAWPTbKXf+5k5m)Z=(;ePXiwSNZ5? z^83?aACCQ;bCaA0%v2ug_3I%eZWH{k%k`$6N4sP8(3Gq?7Rs;3pi;$sk;*g59la`O zVU;nRRJD&X?#2a~&{!)^jGD#;>n)ZvZD5PssLH%|Z&~_ZzXwsUFZ@OGEjAMCinyzK$-(9Ymhi1@J%&?{39*ZV4=;7eRYjBf8W;51jVAv zRLM9a6{K4Y2e!=N<8G1PUFR~JVKsu5!pGzy%d?@2=Fp{=JGt{bhH;M36t=NA{cJR{bORmOdB{1^4(q zZ$~1L*Q;Jh)ib>N>Kwo>UE(}%#i_7&@Vv5=+?W2lvlyirD+|l&CWhw|MdP2F5q2%_Lcf;NJ(**vW*_llX)v%xz|2fbikOj z5o$AG{vc&8UP4k*F>5vGLjitd)76HX%vZ5LEL25nJztRiQLDD05O$Pl)n7Srk7s#K zv(^rR9+5wogqk$ETT!Rn6!*=}&K9z0nVvc4SuW}*GdGuzyDCOGG+}4Xjm-MV+Murw zHm4t{vis13A2^Qh33eppTwJsTuY!KQ_cfzcbVh9cpDl5VSFu?W%k=u8dn`_<7oMyJ zdqDG1RA))fXwfIzfnM(OmvyuINVrKgoa?|tQE!{#&6EjZ`9Jq)!0SJNdw1&di}`av*A?ZaLN_uju;-Bm@o#2$yA8=i0QKPOy-Z# z3{T8xNh*l8Yt79ACwy|sb*2c4B<3r3z1Vx0#T5k8YBW|@EH$e`_85}PgU8LKUi+2y z#TuYzu5L3&`HPaKF~lwk!^qew2c952ms%{@*h5JTKH}tJZ!Ug%mI4FGcx$C8n0rA+no zw!M}Q^`97)9*mo$xkh>?h%I15vNsT>Inmx|sVIN*r(V}=`ZJkISN$Z2Tfb90ZK<@@ zr8FjH69*o$DIxhPu`ngr{5D(RV}-BjOhlMsdTR0$is((BS^l)q4t_vdnRPnvT`xQN zPhqkqKls&|(#*D2%_pL^f-0v~nVtTP;FPOLo#vt?G4RerD%dTui=37U!p+ZoRCOcX zQ`*6c?t@R0cf{;ZW)ZXJYVAc?iYYHY)w-f9=NxO+A+|gh*S>vOo6pS=bwdxQT#fcn z&>tIWZo_-z_4wq#G9;YFm(adod)95y!9OxFns@th0_T+nFjmDcQP10zuzx3lsIFpz zYSIuw@4k3HU|@XbnS%36eTtsu5#=ly6#m}$sq-ni1Kmha6cAT9l)CBsF*eB7IV3`# zjmnS{lUO)U9>^v4h{H3R*Cv};xmEjiz`g?9Ld`#E^N2i+>s(aQeXn+&>xX+8su3w)HyhAUOE5cpCW(n z8Fy_OqMDBJ&S#Nqo-FfU!Jk|k$372yVkv|xSo#-ZKQMn3Zo1;sXg72JNCwKjueK20 zt>}hFf3SZRY*CLkz50^iRn1ANke*dS(Kk~CO$+yI-sh$p>UZcSo{vdKbkMN(^`ko% z#JTDS;*oDxfC-K7JZ11N=-7PtrVO^O_KLvkZhNAy zj`v+J3A>sLjhFsPhu<_7l+&)9L~2#I zWC|&w)@;p6ubQG0n~bH#^VaqFK8?%%)p#B?)|S()_)2JQX#Jn!5MYZ`+e8kGWLzvrwssjb^m*Pq{?Fvj&fuVjhKvP_dqG;IY!_&Z1BXrTHB>i0m^C zi5!K{799rX9att<`>dh%=o^Q#eI2V-bV&h`hOs3l9+Q{cZ*IR@`s;wSoK&C;p4bG8`AjNk{XO21z+!95Iu&>m`Yg4$UE*A(j5$3) zn&x3B-$@atiP1oVk{Hq$IF$U}rw5_2PonFGQ{Ungdg)U@T=DoQnJ@P_TQV7JgI_|R zT%^te(hDcba^QcIrPMXk(W&qL3ibDQdi!aFnOm!*QI_;DxsDt$ddVMG5jU0iQ=#%dhXMQ`3&mRlYitD65Mr=1`B<-m&Sbq&IBz;}_~ zhBCfR$j-8xewbEf`mnLjhcQJ-yIAMS0_#`e^4rW=8BmOk1+qdHD{|UN#=>0=u&8^zEq$b~9h3nX{u-*5|G`aCLuHFGWKLHytz_a5I9Wgyc+Nd5VGG^`oZ+$(l)x zB8gvod_y`dMp2FvTk-NutSeA~z%EL}x4Pj}S9p|58;=cT6a!>)FN65B6TKXhNUBfp z@S-vQ4TdebPPnc{=auI>m2kd)1@lJG?h`eQO3}%k56A2P!Euy@mE_zjr9XZLOZl+p8OC{WUl z0bhS#eudFu5^1!(vhPHd!P`};_A&m;A1%652|0+xx86391l-Y@ZH$R7UL8@=+>vrl951@$xNXTxE-+_g~oFu6br zz{8ZPH4oo}KziOZYL)8+SGaSiPg5f1qa(3?maPtJX>lIF1<)4j2zEV!6sg-c7)wVK zl90Ymdz>_`6-%l9DbcXN(!n+TZi;9ME$YUAZtyTCK#XflRh1(!0lq zn0T}My^?}ykz>=v9QPhEWQii*QRq8TB$%ih;b5Bykw4BI)z<(1xku6X@a;YcN8*>y zwMr-|pTo_!`8i9|#TG%Z_Q;y2dEL7!g+sTGA?FEsgff91S)W9|Qg@vXh-|1BkMPPkq^_xgn z%Eqqe^4DdZG1jPCNiOf+{)h!Z0rnf|YZ_HqniVWU+;6~#UYyiU!k*v!toFkLa)s$C z^>!8#Sh0F|2Ur>hg!zT|^_(4DSGu3N*!i?7g7nvPA>EGiOlP|A(4AV=|D1~B;i zF4>OCmjj`z$e@iT2FN4FOcArNyLp?*862FiVdVp<1#zl=L*XH*hZCFNWF@^R%kY+X zj{)>b{1+y8`?K2UI^wI zd2CGlQ6?mUR&W^wFaQS9kd~{%&jSl(qq zOaBai825n6(nf4j28toSq%=l8TletHxiZzMp$0H}~z0F11yuQo)x3w7}fSvlQ&v2gxy zr7Z0GzWkq9hJ|ki*sDZkTdN9OV&PpA9N7P)tm;BB+?j_o6EBu3TR-`h7iy%JTSK-9v1G{xW$clB?- z=oM{Q)rbnW)*em(x=e2A(^XCQT-(q`1oNbG!?Qw*zHCgcZzk7?`9X>XsPh;c%`d6h zJ(FcU%dw6;e71WZVE1w=g3@BAn#S3qH^cch#-xYB#qK5or*(xvDF&~DgFOR`Qm+;< zYpp&fh6`sjo{@M@O0el!4%rJ?q-QNPr0s4 z<%N_+Z-xSxQhoS@f$_RrWItVgjms`okwB76dYPvp{v%&XmNT|La61^Ehlg;E1_cOw zAcm0wSBR!=6ef2xxev7%G(uWqDawek&8!c;^>=W>HpGx0r+MMrNf|p)?w^?O891T4 z&H`h5&L(K!_|2GXB;9YgLyVX>`yKM(zlt^nv(Cc19&mTr8U$ZGE!(Ir5kVf#<>6O^ zbB1qpI8Qh7*z5so#hv3RcZ(rsVKM(L{QD<3)gdkiu-%+T3Orq}N7nv08n;c!8KKP` zSV#Zo3-9R;5%T5kTe5X6WT8zsqc;zH$_|K8;*4yx3_pKzHrU4Xa|xy;leo*_3x*h= za`XZ%_m8Du+{jwG)KiKhB6kBLCI{*q%bHQ4YytU#y75`Iv`vdQG<2ia0-yT(iHxIY zruypgSArKNe1_j#h6Xc6pPlM(e7*1+pk0chGE*j4bjc)Lu0zRfB$=u;`r2#d6@Cht z+raV1ZbB$y9r|mB>c*$P_mI)6ylyEU5RM*bd$Vy~sY5y8FGX7*7Ri^D=k}+Y<&nOI$(T_?-3 z!X zq=alBOyu)E?&=?VA6Pp{iLfOO?`lTN5MZr!|2}D|L?YdEUI)Pvy|cwc;gUq0ZN-|- zmq7;%*dogTe)17fU>bnpKP~dhJe8!wMClG&zM~;7CE<|Rke$sK0&ZMV5~kkKK#!(h zZ+P3-I`8^-{yBX;QH9U;$*Vg;1nXs<20QjJ|VWk?xfJ^$fKXqjhjb&y6VMvlv>;ctgIL@*I)hv~cjMM5ggn2eWj}NV6GlaXb zuWVVhq^>v8yP0vzme>e6WHr6uzlF+`98W`ECG(_;eyf>Ts=dRpK7f=gU z^Y8L2%H}#W$s5tCFHcY!fwxg)kF96lsurn8-UG?ECPTjXa(T6q z^S5(ek_n+m`3{gBZ0ROM~4@xFryl`xss!dCwqV#WhZZ77=QVIRKoj(U66)o zrQZ3q)8`SaXB-Jm0CrsrISw(;i$T$*T{Y#hLK8h3GRsS3nrDDoJ#qUb2>k&7{jMy>Yot>RyyvBu`a;dj9vxwJ>8?)? zg?@==)*!4|Hx;0{XD%yF5uC-I&k^n}5M$KKOyS+e1f!VDqCqrppi#F2^&+Hccgjnw zyv&;yO&e5r%lZ_;+E$<8bp%4^?ufOvRqI||-9=J5lL)58^+&xqQhiQNpV07Ioo7Qt zdl44{eeL?pIC%H|sHKlsHe>WYbC)@J$SCD`8^VxrHi%-s&IDg}8&} zNrnhVVo9<>R1(1(&+onbpNCCQ0W$Ae%0eYOR`!jy#4fS$7Fbta_cy$TLaB5Ijt1vb z3>ZO`lnLcC5hu(9&IYY+nc5}zM^iwy!7j69SVY zp5#0q8M!o7IYqqB=EW41xJH{-rt)F^ev}v%SdbIa??kE~d*NgPp6yz)w>b>NQm6Yd ze)%(r&RFCmPb94>>X;F>`oK;V9aNI1-13?^S4m>SzH{f9w2UGOseK;?P(mPKpi7)(PrcOhz7{zM1aBk*eP^Iu;|hf+?je` z)v|ULI9|^eUrbyEFDZsFu0kvRj0ZAQR8(I2J}4X;;#RS&cMIlV{BO&)`%?5;cw*qn zHNW5kIlmQ*C@p+g;#uhlc71(ab7s*sKX=!(&Is|2*R;+dLSLWqT;_Qz<#T~D#e=e- zBuZ_;Qo+{;o6@#(>!(`B?p+T!D%{)_MR1&+<3q3kPoK7|Rhz>|oR>t`1)4hP#}PPz z(A@p>cb^&Vxgi^TX`$6u^w-eMk9sVJ9t+hrWZDnTB$T<{$HuDC=I*whJ&?D|eH8X+ zzvbc}Nczjn#b<@x25;<2p!Ad87=)54u^=o;%@7KmsC8fIdV!IR^E<|-H?3znd!lLN zmo)Rg_8q&%Kxl(w22tnzSZdn3xsS{?abotb?4Aq7bB>IK^5R=A15}$heg$yJk3*H{ z#E?lUphgT_^M(HHNhXgXHglOJ01x$k()-&(cTd-{5O@8*Co~L&_@e|}+}XP?+l=Us z;mP28Aq;s$`+sHxYJK7&>a+D6HvXaZg4!G)`B<@@kr*B;Yn{~v_rkO8+jok$L>>^& zvACM-?YY=`@GSYI9HyV1d`Ox(R`Tyj!(;^VzOYvfl zzzwI}RvG5vFQW0*{02;&%i6sq9FSlI)?6Xzf9yR|wmuF~E3|NJlg$QQX)ZScsZ*Hv z)}IJC?CpPP6^D)2r;l^w9#wzbeY7o}jT-h;Sc*5p1~;d46a3^q54hmIu;Q2(e!rFY zce#)BJmcEAqMsS@`0-oCNu>#s2giQh!mQ8GeHok1=`a3qo#kl#1zCcW!dM zvv->X>-QBw%Ai?jVw)wUWKSgR?IVKiS*`ws3i<4-UT9p=KAAwu1K2U(@e`zskd+=% zwtH>yf9Cb9Hv)d=>=tgHd;i`YfmhauqHo9j3G_Y;c7=%_@Qk^xdU-YuMZ@1tM zI0{=Jr5W>lxHO(+W&V7^MXYV(Z_0>M{u*O1)`pma7XGREUT(oTYp39-1RLHP`W40k zPkTi^H%t}>NTX9Qn1d@eb*US=rZcZ|m^{t}Y=`%M6P7hI!9)d;7xQ2xF0o^sJM zyXQagFAI$2*%nNzZ?zMKT&l-S(-~?!^+^mO`#(b2Byw-oxzYe6eMf!bPG@k+)8_)y zd80M@z8lSANJsd~>Q7xt1rc+lpGqq_CQx2KdftZro$UAV@@{{2JLo+9!Jphl+!*ZF z(~+jFi7f+tKX#1pV9(#d&PIN9P53P^oL2IAJ!$-f zSItPSRH3*9cqIMT1`++ov;TXdUKk?q3){(x@`8thN)$hv4q>9A5_}3}Vp$e)(2&W5 zWJdR{GdlsE-o9`c85@-w*sI<@!qTq0Mb%^;D*T7g~ zATx{*$^gHvInZvwB@x<~GPsFlpVcwePa?Af)}8^$SYeAN`V#Aejn3zoMs64JTTu? zsm{_chEPCfiPB+aBqdLuMF>7=vKk3ZDR^ScM=11xzmib&za(^TMpCNX;P}xYbVy4F z!~jX(o|p6;4bbS?3n=7u$wIpHC{z4={e9W**gPd~!DMO&a zCAQ{r_mvPrcRFGpQFk*2xdLm{^m8+;)10BfBw>sDmVYP)UzE1#FE^wjh&0z|UVO z<)GY&PzDeWfp@^{OoXl|-DyQZ=@S4QoroEdq`=+}<0Zy^OEdMG_Cdi;Hjnr0xsjrd zON~4LpNjQfD-nw2nb0=aT7?P8H_;Z8pyp?LgaPBbB4=vBml#I1Ck12*q|pZ^0n0Do z5iE4?N+Vzq1wqL|EDq*}tu}-Un)h8Q+H|?GfH)u{in`jPJ!SFl`HCbk11Tu4rdx#B z0&K=$fh9-an*Zx5@W`pr0CGubtax=CKH1bQcBb%^k*m939WfXhLUvC1afyyGD@jiC zvY_;&5jD~FaIxZl)1zQ0#83@#L_l>^J7^068(y(tKsYTA+Ypcn8|M$V-?JD+?lR@} z^W6Xe(Y&1$Xn!X)uv!8D;2U@G3^cuE_q5=O;T(&Jp+ztwCa419K7N|a?q9tK66E7t zF-=hufR^J4L_PXYh!5p1ewo7~iXJwI6A4m2+}2$*Occkh`Bw@+L&J5i8O7yf#JQ1fO@qyOs0bhE`hlBm<*;-_e9< zda5S`^J~Zu9u#S+dPP+2Jtk}n@H|x5c~JQlQtTsQlHW(FBwhG6G?$ky&}UO<=3`$5 zk7}R@#^U^4ixC?S6i=Ts;vjO_s}dp8G?0&$CWM6M+&0wJz#vKV4MhG3}QP9K}xNcT`%5)|MP6!Mf)m3PI@(|db(}?wvfqigS1WnV-!}Kyy2c>RYRzo z*QHUosbknfr@TD&4Mp7g+>8w=p8l^q5to#Mzv_L2F@wjHs<&kg3faGsCqj`fs_6X8 z^6IaZy|i|J1e>j$o~Z?sDNyl^hL2_rx>jD=NddsTy~*D=*fc7^Z>qsYh7CAsn?cTr zsVg;Hn`pbvx*u4C+#12O6Upf7dHVi@?O(rZfkMo#fbpBS?{@9T0r(Ft2bZM%48Up8O`{6$I8o7^(GTP`8atnA=hfW6tLU-xCw&705s zNh!H3qXZIfpK3&0dD!uLu3iifn1i0F{ns8orf7t>1(38&${Eq2xWM@Nuh~hCj9VUT z`%5c(RlqW0w^glAv^x^X6hGg1tq#A?O|0vfMOBp7#(G+nfTCaga`Cz;MKj13iXrd8 zzfTf|U+J>eo_@eImjH52L`oH1A+M|Ir5|p5QZ&KH7(}+VMtW4rbxNZJ8@qg{FIU>8 zAq@el^qNY8Dnt;P9f;os z0bvRLW?21q12~{-|2ZpWn@FomWoNeecCXwR$S)9ur^B&`XDN5>w*80`sTy1wgS0Xw zoF@J5Ck@$f;G|-8Wpl*)|FI2vg7#(%s)Qk+28;9ieQ4XSkD#5Dt0sVuQVJ_N`K&Z) z)1Thm;#hSsrz+m)LF<4jt||}kL`6##5{qhqNZiVy(7JIjMO*Y0BBuPKCdQy zTyP)%@8kdnwQwhWAcgM>#_#sevAoy9b?E%la5($10s6$<-zPKw8_~S5QV(_c_3@@z znw}gJSc*|Qgt5BRIOom}?51z-wZms2jV~J;Gp^OOSO4I{UM8nrG{3V_=4K5O- zucTA|^-K<5PHWFC!5%#k5lXI?;tSe4;i6xOaZKt-dc#amc?U4r^sz18-SKvL&U-e* zbF8OJ`G2z#I%krbwIj`>Ov4kM8>gc5c6+P6?w$p~Pns-&P-rD{I=*<3SyuWgO64|_ zpGLx$HIM(v1a@YzK3lwpC;f7w;0158;p1Sf#E{p2*lvaDNzYF+<3z+tre!aC1*!>k zt75bI;h@f#8QN0LI(+%B_RRmee*jRr|8H4{yG`~QeELl`S5||f$_ogA20u%UvHxl` u@7{-QIKh8|xoqN6JpP}*WcM!!1xpX5BUY>(z*kNQo;}fej8d_D^Zx;-nNB_c diff --git a/DOCS/html/stm32f4xx__matlab__gpio_8c_source.html b/DOCS/html/stm32f4xx__matlab__gpio_8c_source.html new file mode 100644 index 0000000..e29c7ac --- /dev/null +++ b/DOCS/html/stm32f4xx__matlab__gpio_8c_source.html @@ -0,0 +1,182 @@ + + + + + + + +STM MATLAB Simulator: F:/Work/Projects/MATLAB/matlab_stm_emulate/MCU_STM32F4xx_Matlab/STM32F4xx_SIMULINK/stm32f4xx_matlab_gpio.c Source File + + + + + + + + + + + + +
    +
    + + + + + + +
    +
    STM MATLAB Simulator +
    +
    +
    + + + + + + + + + +
    +
    + + +
    +
    +
    +
    +
    +
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    +
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    +
    +
    +
    +
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    +
    +
    stm32f4xx_matlab_gpio.c
    +
    +
    +Go to the documentation of this file.
    1/**
    +
    2**************************************************************************
    +
    3* @file stm32f4xx_matlab_gpio.c
    +
    4* @brief ИÑходный код ÑимулÑтора портов.
    +
    5**************************************************************************
    +
    6@details
    +
    7Данный файл Ñодержит функции Ð´Ð»Ñ ÑимулÑции портов STM32F407xx.
    +
    8**************************************************************************/
    +
    9#include "stm32f4xx_matlab_gpio.h"
    +
    10#include "modbus.h"
    +
    11
    +
    12/**
    +
    13 * @brief ЗапиÑÑŒ буфера выходов S-Function из GPIO.
    +
    14 * @param out_buff - указатель на буфер выходов S-Function.
    +
    15 * @details Ð¤ÑƒÐ½ÐºÑ†Ð¸Ñ Ð´Ð»Ñ Ð·Ð°Ð¿Ð¸Ñи буфера выходов S-Function из GPIO.
    +
    16 ПоÑле в @ref SIM_writeOutputs() из out_buff формируютÑÑ Ð²Ñ‹Ñ…Ð¾Ð´Ñ‹ S-Function.
    +
    17
    +
    18 * @attention Тело функции пишетÑÑ Ð¿Ð¾Ð»ÑŒÐ·Ð¾Ð²Ð°Ñ‚ÐµÐ»ÐµÐ¼!
    +
    19 */
    +
    +
    20void GPIO_to_SFUNC(real_T* out_buff)
    +
    21{
    +
    22 for (int i = 0; i < PORT_WIDTH; i++)
    +
    23 {
    +
    24 if (GPIOB->ODR & (1 << i))
    +
    25 {
    +
    26 out_buff[i] = 1;
    +
    27 }
    +
    28
    +
    29 if (GPIOD->ODR & (1 << i))
    +
    30 {
    +
    31 out_buff[PORT_WIDTH + i] = 1;
    +
    32 }
    +
    33
    +
    34 if (GPIOE->ODR & (1 << i))
    +
    35 {
    +
    36 out_buff[2*PORT_WIDTH + i] = 1;
    +
    37 }
    +
    38 }
    +
    39}
    +
    +
    40
    +
    41/**
    +
    42 * @brief Считывание входов S-Function в МК.
    +
    43 * @param out_buff - указатель на буфер выходов S-Function.
    +
    44 * @details Ð¤ÑƒÐ½ÐºÑ†Ð¸Ñ Ð´Ð»Ñ ÑÑ‡Ð¸Ñ‚Ñ‹Ð²Ð°Ð½Ð¸Ñ Ð²Ñ…Ð¾Ð´Ð¾Ð² S-Function в МК.
    +
    45 Можно абÑтрагироватьÑÑ Ð¾Ñ‚ ÑÑ‡Ð¸Ñ‚Ñ‹Ð²Ð°Ð½Ð¸Ñ Ð² GPIO и запиÑывать напрÑмую в переменные МК.
    +
    46
    +
    47 * @attention Тело функции пишетÑÑ Ð¿Ð¾Ð»ÑŒÐ·Ð¾Ð²Ð°Ñ‚ÐµÐ»ÐµÐ¼!
    +
    48 */
    +
    +
    49void SFUNC_to_GPIO(real_T* in)
    +
    50{
    +
    51 // write pwm ctrl registers
    +
    52 for (int i = 0; i < 5; i++)
    +
    53 {
    +
    54 pwm_ctrl[i] = in[i];
    +
    55 }
    +
    56 // write pwm ctrl coils
    +
    57 if (in[5] > 0.5)
    +
    58 {
    +
    59 MB_Set_Coil_Local(coils_regs, COIL_PWM_DC_MODE);
    +
    60 }
    +
    61 else
    +
    62 {
    +
    63 MB_Reset_Coil_Local(coils_regs, COIL_PWM_DC_MODE);
    +
    64 }
    +
    65 if (in[6] > 0.5)
    +
    66 {
    +
    67 MB_Set_Coil_Local(coils_regs, COIL_PWM_CH_MODE);
    +
    68 }
    +
    69 else
    +
    70 {
    +
    71 MB_Reset_Coil_Local(coils_regs, COIL_PWM_CH_MODE);
    +
    72 }
    +
    73 if (in[7] > 0.5)
    +
    74 {
    +
    75 MB_Set_Coil_Local(coils_regs, COIL_PWM_PHASE_MODE);
    +
    76 }
    +
    77 else
    +
    78 {
    +
    79 MB_Reset_Coil_Local(coils_regs, COIL_PWM_PHASE_MODE);
    +
    80 }
    +
    81}
    +
    +
    SFUNC_to_GPIO
    void SFUNC_to_GPIO(real_T *in)
    Считывание входов S-Function в МК.
    Definition stm32f4xx_matlab_gpio.c:49
    +
    GPIO_to_SFUNC
    void GPIO_to_SFUNC(real_T *out_buff)
    ЗапиÑÑŒ буфера выходов S-Function из GPIO.
    Definition stm32f4xx_matlab_gpio.c:20
    +
    PORT_WIDTH
    #define PORT_WIDTH
    width of one port
    Definition mcu_wrapper_conf.h:50
    +
    stm32f4xx_matlab_gpio.h
    Заголовочный файл Ð´Ð»Ñ ÑимулÑтора портов.
    +
    + +
    +Generated by doxygen 1.10.0 +
    + + diff --git a/DOCS/html/stm32f4xx__matlab__gpio_8h.html b/DOCS/html/stm32f4xx__matlab__gpio_8h.html index 3664f28..c7c83e0 100644 --- a/DOCS/html/stm32f4xx__matlab__gpio_8h.html +++ b/DOCS/html/stm32f4xx__matlab__gpio_8h.html @@ -5,7 +5,7 @@ -STM MATLAB Simulator: F:/Work/Projects/MATLAB/matlab_stm_emulate/MCU_STM32F4xx_Matlab/Drivers/STM32F4xx_SIMULINK/stm32f4xx_matlab_gpio.h File Reference +STM MATLAB Simulator: F:/Work/Projects/MATLAB/matlab_stm_emulate/MCU_STM32F4xx_Matlab/STM32F4xx_SIMULINK/stm32f4xx_matlab_gpio.h File Reference @@ -14,6 +14,7 @@ + @@ -71,7 +72,7 @@ $(function() {
    @@ -80,6 +81,9 @@ $(function() {
    stm32f4xx_matlab_gpio.h File Reference
    + +

    Заголовочный файл Ð´Ð»Ñ ÑимулÑтора портов. +More...

    #include "stm32f4xx_hal.h"
    #include "simstruc.h"
    #include "mcu_wrapper_conf.h"
    @@ -88,30 +92,30 @@ $(function() {
    @@ -119,30 +123,30 @@ $(function() {
    @@ -150,14 +154,19 @@ $(function() { - - - + + + - +

    Functions

    void SFUNC_to_GPIO (real_T *disc)
     Write S-Function inputs to MCU.
     
    void SFUNC_to_GPIO (real_T *out_buff)
     Ð¡Ñ‡Ð¸Ñ‚ывание входов S-Function в МК.
     
    void GPIO_to_SFUNC (real_T *in)
     Write S-Function disc ports from MCU GPIOs.
     Ð—апиÑÑŒ буфера выходов S-Function из GPIO.
     
    -
    +

    Detailed Description

    +

    Заголовочный файл Ð´Ð»Ñ ÑимулÑтора портов.

    +

    Данный файл Ñодержит объÑÐ²Ð»ÐµÐ½Ð¸Ñ Ð²ÑÑкого Ð´Ð»Ñ ÑимулÑции портов STM32F407xx.

    + +

    Definition in file stm32f4xx_matlab_gpio.h.

    +
    Generated by doxygen 1.10.0 diff --git a/DOCS/html/stm32f4xx__matlab__gpio_8h__dep__incl.map b/DOCS/html/stm32f4xx__matlab__gpio_8h__dep__incl.map index cfae6fb..2124665 100644 --- a/DOCS/html/stm32f4xx__matlab__gpio_8h__dep__incl.map +++ b/DOCS/html/stm32f4xx__matlab__gpio_8h__dep__incl.map @@ -1,24 +1,24 @@ - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + diff --git a/DOCS/html/stm32f4xx__matlab__gpio_8h__dep__incl.md5 b/DOCS/html/stm32f4xx__matlab__gpio_8h__dep__incl.md5 index 6ca5b40..d1cded8 100644 --- a/DOCS/html/stm32f4xx__matlab__gpio_8h__dep__incl.md5 +++ b/DOCS/html/stm32f4xx__matlab__gpio_8h__dep__incl.md5 @@ -1 +1 @@ -ec798300b2ad245189f58e91a1c960a7 \ No newline at end of file +d4f916291d2c6de40eeed780258336b8 \ No newline at end of file diff --git a/DOCS/html/stm32f4xx__matlab__gpio_8h__dep__incl.png b/DOCS/html/stm32f4xx__matlab__gpio_8h__dep__incl.png index 825e29ce90f1d989f9ec1ef3d0f2ece57d386d25..ad55fa92eaaf6173b05ad192dafc9ada424bf71f 100644 GIT binary patch literal 34152 zcma%jc{r5c|M#@7XjRBkM2N~@YGkQ|v7}@PGgS6vMi|>@(4xh@B%!fnY{^KBF*BAn zk=;yoLlI`I9~l%4&lx`7>wEpK>-Rj@qdyw=+~>Z}d7tDW|JHz<*nB8|mvpR{8%jtMU>d5Ge>k_kwxg%Sl%7OQauu zb#~Fk8J4wiuaezc9i>{E%aw6AHr@76{W`t%SZ`{k+3CqiSsjn~mGPYNj-s0K8h6Pe zOWU~S>4ZmVGIkM1dwQOHdA;5JJ~>Il?97vc*Q74oOeD7OAZ94~%nKnkGU3?6_(Scu;+PJ6jWB9I1`jEId6x}~O23!t%_VuCQ z`pd%Jp4hWt?IZTwPTlousF;m=*FNbaXX|WU`_wk_-`nhbg`~VEI*SxFcnqUc(PTU7 zNN16)RTtMC{rRgmCns6GQqtFrE)ubrXS3`b>zy-vjQ6YiGpoxTZP}*<9v9|#O=@G? z0mMLkozflEOZzStxc9y8LdIUG+LGc^S6y~Pwd=lh4q7H?l0P$Z{X(`>C%4 z!wFSs{XBLVkN-{EkpoX4Wyt=GSF8G7@~)GL+)eA7$SlUxw+1s0s^Of%lo5IAnSxbV z_7nap!jzpMsjtemUqgnuE?n0pYjve+B`=7fHCogg{OTh529S%29OV%2aun(N<)gd6 z2vXV+I(cC=+!5R8GeE;2VVzkzn=>cA zF^k@$)IO1+^(Og?82#FjF;o+o*Gi6d#)yHNbR2*f+3@-5h^n4*3H?_Rmd#uHS{P+$ z@Ev5{Ab@h&yDC3UJdL^qljR_#f^T|$xS>& z0A2XXYDLzB@N(O%!L4zE*fV@(fp1L3?%1D z8^Y+wQ(;>);*d%pq_f|Jc1TYRIyYLKB#?J_reZvufeHwsf}^)=ormJ z?hCaX6w$__-*vuQW4^4eLI-@W^$v8V+trF>=XFkuM2;n6iUX@~qe-^8$lzwPRxLRy z3-`RxzyEm48UAye`POTmBR18;$$|ZoglQ;5=k=-Lqe;nZ}>(@*m)`R0!DH-^S#2bZ?2fQ=b^7x^g-gh0}N?QR& z1^+U2v+d|TNwK5;iT=JehI1Jxu#yFiIT(?~)9Wi#4>3`zWu-OvxxMb(qOc>UPieZ> z!ZexWo>7Q??A!l$?fo**8~27iSA<=?BMoc!_WC>=6?7eggKiB^FFd>4?@F?n=zv=8 z89NN-jj)xUw25zCAPx!K57t(7(mQ!;-xK$MYF}t&nnO2mZ zcRiISb4_ufO01PH&NlaTapozcde5OqMMKk9YD48xvMXL(wdv1SKP6wgjA~7LKlH|` z((~nlQJ!3p?b^6F)&D;gxw)HfhHGXI zf=7p8Z-e(Lk-@lk!&By|5-wGi`ANkh6SCBS$ujr3*W@0|mZ#L0#g^`mqrj`#g6A)6 zhMZ{r6lw$7gC^xylS6ZEOKsv;WMISFyH=6Wj?0cG4j0`C5StY3!VR8FRe?Rl^ zUGROG7xCI}zK{}W)sK$~o&=)8glI-|J@p-EaC(!Z`1Ix4gTUI_%yPohRSyLkT8zK4 zxRTx291_zf?x}8-gFfg|oRiK|L{(#}+~?e%(qrc(=stbL^VImc8wGI(^Th1Q$Y@W# zSv`qd(dTjLQ>&3&ccRa?74m9SLP0cD8 z=4#5MDC@T`wPvrG)W!<12rwlsY)D(Gi+;t#w|7hq>Zs z`Tl2O8hMQ0x*aqNHIIx4`ZF~~c+tQ-xIgTQ-o5QQwgvO%hKgHDNqOvRm7Y0g!V@e# z(!68!z4to#|0xqTXK-b%<=p1OM4a=Q2$CWcn@@f>pAhVHjnRwLC68K&J%f|n9lo36 z_T|S9+rKO-yJLm6GmBU(P5*fF<$Of4$uT3&Uz@%YC=!Zx6YNSR-kJ@(3py|`keq@l zz4PN^+qJOr_yt(h)c=l9zPg80zy!)P*6@-nHd3Z}`Cg|-*NlEq|ItA`KH|yT17801 zt4NWyAoguwJz-}57hMGR{tp*6D-4B{++AHB6cXRC{gYsI>jzCwevFj)6gZxIg~YFu zF|XKAAx-X8_KDdeKA+EvFTA{@y82JhQhT$|qZsCuH+e8=gjT8cPQr1MzaxeAZ=~(H z$mPx@uZi|;>Dvi%@+rp70c<{)83^&cky2Dt;OI&%E}ae>=B{JRk_hfbC@MJ&%s5Z=dE<{*!L88FG z3ZA8LcRg#L7+LZ|)TLsH+Vcf<_=IEPFFK_W7$09v=lJI_MQ_tKe#UrQN(@Poi5BSA zxafjND=q(X|Bnd1fk>fp5`!h%gVl@6@mYKWgdhO=OC>#$n3Od~?9i=2m%Xu5x?W5~Q7h-l4uX;Jjr?_$ z1(6RP;7CWjKJ=vDqW*Ag*5;RJQa#ZiS9`a(Z1b1rJ?PdaTu~T04trU7=1_6(&$)|Z ze7hgL57fbI0@ZhS#UWR+k^5$6B!2}+uN&Go2Qh9Hf<7yLD{t^sOHYwi366}WY6;EI zVY6jxwx=8HEXPZQS%X*#`7qxpuxa7J`a<;n*}ON*93IeMKX*f~s~-DMaJL@nwG^l1 zME3Cmk4K$Di!J5N{1-}%I-%KvLMa6(3;XE}PMl=b%n1liU)~`TSAt-6HzRWzyXrdkCes zo@yR}^TBG*wwfQC_cYZ%aq+oc?c-{wF+%G^3E2=6>$XjP>luoZnVM;r`>S)Sexz5C zIdMYpI5CrAouYhKwwc?)9N!b)+jAo$x}nTG*UBYtKKjE1uVP)8XZb-L)gtZgz|Dcy zo~j#^uk$nU*iadzR5m5aL2)vdF#=O2XMFX0YNXxz!VWgzGPoZ%Q5e47B;)LY9!gc^_Q*g3AFeiE=0EEtY^0U&6nigiplDN9nvo11TR9ja zaaL4jCvd(Hb`8{e8=#f{svW1Ii!!lJFZ^(E)8A5>47!teI%>M)*!-qPJmv%u# zP|xBYNp}rIO(Yn{YN^wjBz6!4w!KVSOjKcz&Nk{XJ~l2*jXJxGV=pDH;9z)52CFJJ zDPz2J+eH_?%{YT-KJG>Tvl?U4q9Kk>T$aJ#ZIy_|*r8*$#XQ;v1}&$z_ob_}`@NI- ziglQEjO21kHY_727=9$RKHlXXgFcy{59GU_!gx|^x~{_yem79jD+*57cw(sxYn-8d zM8n=H`eaE;ThAVQOalzT2+WwpEz6411~SH=4MwQWt0)%6(#Hfx4G61cKd@E~aL zRTSnqS0%Ycb5yqKHrNxhBO4pUY~8ixo4WQP0_YsYPuD{X*~VZUI;Oz8^hVJ~$|tZ0 z$vBS^B2Hs zXYSpRwrBngenoVNG6T6-q3(hMkHePmKH(T#Fx2F0Pt90 z@07cLJT@^^l;gC@Xj<_V)sh5Ee)kap_6cceVZ>4*a$vEZtOXkhpVeBXv{AuS+fcxS z0weeUen|x$inE!CR~!Y^q)YVD0 zg>p_cIbz$RRF9-AI3p!nxon5*#>x1$o-mB+fQw}Ph^C^O1BQ`3yI~o-wioQX2cCo} ztG!&@e~g1q7*OuQEA##gXo|8bdnJSj0&M?bJT4St*c#_He04xla)RQqE*BS&Fk(~s z)kBk1XeSZ|j&jtKed=1eEToM*WwGjzZ7F{$mNRyn6x8LIP%AUe40!!%E8$Cp3Z#O% zeTQM11YUO~nJb>WHMR<2b>!}YePLy1=FTkc^0^MzWsGLYhw^S@OzjlsXPyKQ#q76wn}Y+?EU31yZwZnP>L9bPv42rVpLj;MQUSjw{_p$4@X4^r@De=ngf`ho3!xQVZ-HXY)?o6th@=+X!6JQXK(fQJG=)( zZGkm}A>0GfdDN2jYpg|=_TFUXxnqKI&tP_Fcg435VYpb>s3-toL6bikC>rj>%&KOm zS918;Y!^VCz*X8qmKUB9rJM?&i3y--I7I^QiA~Ym2S#>^Oq6=~TwmE4fI6=_vZ~hU zLSM6conWy0W%qtmX6!-CBy#9 z6Iz4lu!UNw4xI=AuSKiTU)5(4suejhKyRA5BEKw8WylL|V4)p9A4?oK`gKR{aa^+oS8WiK zZv0ncMsvAnD#@?wfiUOi>;{dbp*>+|zbsAeLs+FwMD$y(&bI~eH97=TBepws$Yuom z-dKgEa1Z&2&oI=Jg;AYeu*WT1GkK1S6O|W>s|((!$3*>3h~FEzF2iMzBA0ddTn}NN z?}{U8CvuU9F2|iV)D=}a^o}Y7?TO9NRDZchxy)!;zS0?doQGeZq9mB2&CfUJYN_PK z#b#fYBFC$rdoGfjHq7%EtUU@r+!*wtR7^aWUi#-BVhtQC0VY`{1j-<(la=zJ)5gSI z{ag$}mXpBKTzVXBH01)Ih<&~;`?-gJ2YS6G%(#%wdP7hh&^QB8!J+=IdH;wFw)XQzSavUF+fs%a9934aprkp_9fdAN(HAoMc`uwj#dZX78ir*M z6bx1F&OY;7&UAf!eUBBf^D09rtjKvkL=OPJuazDAV8284TkXk+R}M{+MREkJ86zmH z<)1kv#;qlbs$U0d_QMU4u)({fuTJ!yERf&wYG7ah8gu?v{csF?Jm1+<;%UX|d;497 ze7sEyBv*ge;r{usZ6^LewvJ=_oq@;F91U&co0r7-W>Zjz3-edYJM#ooVw24UA@|5b zt7GB24!MssB$;?^W1HKSd$xc3Wb33 z9waO*wy=vYx&WKd!GTBsTt-npE>v(YAVSNW3o{PGg}|y9Kg&b5Lo z*EZJj%gVArlkpfNRMd+uQsIn!B+xjejIc6TYU?Eoh^+X9o6Nn#Pq3T`reZiW9hn*j>D!z`kiJ2LH@IHRJH&|Fm_PlTi?271Qu{^3)^VI zc8_4rCN%A(r0J9IB0TeuVr; zIos#J6G6j9ujh%hr=Fc&jcGyIeNE_1h~d=s8(Jh0&OXE{o3!6IsOspNRy|B=*m$i- zSzv_btePEpiH+IcfnkWISb2oL7O!)kXqkWXE~QT|;Ct$9<3i%gI<@RMJ}4S3MHsKj z{riB_jn^33ZOQ&A`7STxuUfxWvhonCO%Y=)TAqLjHzK=CnJZa-70!2>U9mjXDSJ^z zMP)Kb*Pwa-r82Z&Pwx+1uj(gR2*feI(+C%&JOfaL{~DWEzKynZ@1!Fb0mlU%udSrhBk0}JNjfX?Xp)^N-YaJKQc>zj4nW5rWA26bf^;92ZD^@qKne0@;=kS?V#eevqwO?Puh8%AgXpE-~AZw5^nGl$p41Exv*{35C$RB#LV4KVMfnd4^2Brqh)*avX>2#1N!J+)Eg@wrWEPL2IP1mUd|czDd$wm%s;(DI{*odL~N4QsFcI*0oPPb-FNDCd|^C+4(Jt?z+R(^ZDMRh z6v=%NB|76hV=@%mRv&VU13BoWgZZb$f{-cyX4gl0txo)swnmB*8O7MUs7boKzM>$r zYf>tu?;PBkR@zYTYQ3CU^`ZX2Bo7b&5OPrIP}HCHhO}@QjJmC#L&G^ev)@{3Bot6^ z*HGoLcYz`Mtb4z9tI$mt_=fT5|31(?$NfQt%6pG@&R+R8(Y{eKvv_xcvpw`|ax|3F zIL%)t1aAF$m+t(^d%J1MVv(|$xqC5^bau|Yz$K&5ue6}k`6cO0^olTHZSdTfHqIV2K6V_!U%Tz6ZqKN96iK*%;DZtw zYBDl(TYNf1I$IlBhbr#>>t6SO-%9B>`K{%*qLw|dU_`MkBH&t`itx&myLG5tDl|K@ znWOPn1lGK4b9}_ccw!!Fd(+6%XJ@tVTG8*NSYUYW4o@F0-O_H+f~6LA;>ehNM#&>b zq~-5sh;}IhUG$`MmW!TCo^P5_-QPGBf}jLHTHjEGq~bROUY5pBq3_ME!3)krM)Qr* zMM}FE+xdLfhjV%fK*aj>{x`0ICgnO8z(db%HaBTZ?dh=SQoq^*Dk&Kxl%SvX+Wh>5 zXXR%Oi~jjg^_wzF{!(~?QqwVdJgbbZSK6gWA*gabgHTN|a9k~|Cb|njuD@|?Jz;47ZKbOhnzDf`EV8WO@~*(^ZxO zW;0|CP_8ef4ZF`Jm{ktW_iwJVKGpJP=m>1}NWlJTQ&vE;!K<)uuYE

    KY$0CqqYQ z`tf$_&Lkl@^~{r@fo=;M5*9~p^`=~#`AhtziaRNah8E0=5(d~ytUEE+L3a&1N?P-{ZQ8B!+|sIX=!CJ;blb80Z;=yf0kXj_>0w zl!c$gur2Q{ihc6F#B{ox>ghcgo})H{FvY$hL-8$TbXCWZBNLyg+lQ z*}o~8X2JL*!g;p7_LHC!013OHr*~2X0%0&WtoIRoPa95hgDXJgoh|*FqHqy9-nnvU<*BA=-@@LL0Z}d#3$z{QugtrL4CNq^ zQ(NcVlV|+Zl1Na4jC2FKj8pa-JBc-akdPR$@ftni`e%haq<4P%{cFgM@@4@Mh!m-P z1527S*3h;F=!ry{j(OpoYa|`!&P|9HPmi!y1>1Xb+U&ZNf^b0Gcv*fDnM?WU zO*!;R@$$af40qE_s=v5bt3);Zv8@+-XIXkS6QiIioYJMK9K&FebEgS17?QaLU@EnC&LVDlbnU`ycS^h{@X!IQk3cl_G}-0fv9zfuTx;E0o8CIz zf~#$mjnBb`6rrCfTezjI!?&)(R1|;&B30<~5tqy^>h8{7 zw$8g~K`j=0p%9P3{?kW2lI%X!-l$-uZsLRWMCcS3RO(sS=b^EVoruy?jK8t^&xBIoP^v<8Bcwovp|Jt{s zn9N_EdZ+gB)5oy#HHyhqN@Q|(c0$NL#HpQY8KLhQ-$ZpBgQ$Bf2oxcVy2eft9b%w- zK-~evFq_xB`K2bmWKb*tp@VdjTim$cMCb9OO*)SwU*+Fn`E_w<6Qo_@Ib__Z(VS3n z$m~tF40}(HXZarZr<09rvG8AXY$!5Klf;HC4eT8H7LO4WahTa#t_Rs#NRwqNq#OCWwxlXeu|E&VeI> zcaoT}-Q7YLU0xrDjikwddZgv!7Bg6YSknX!T6KXDJ3?cW(wuKor*?}MB@#e^G4U&V zL-N4sb}x;KV|+XuKKx)iWS{zZ4j!|ViU>F`I`Pf_gdkZH3S+_%%QE7}IV@pLAGLBY zt#NtqP0zU8)+^od%C@((lejOCHS3@?`UoTwGOn%-U3%Nnk1QFF8WeTE{VX9!D6j>U zVpf9I2`ic4cf00Gl&j>@IzmTe@d3&+q1xQbp@{mI;;s~xwE(1-^>S;$R>+aJ?ujmk zPPPrwCaOl4{^<^je%SIYIwqw!v~p$#VT56X{b%rO;wa~R=n*B(YT$*L#t|OI7v&aD zvI$LPiJbOX_GNi6O0pb)cHYGB_j;7gZ`FL*h`++1H~R_KX5G@7Ycf|qI-k3kLuka(}Ie|LSxdAtvhY53h_PzXQ0&0{X)+xf0g16&dPd5l1JM;6qN zUZT}Ek{g?%dfoeI;?Hq4`2;Sj-D%;|^DUFAq~Kb94hKQ=lPp!&W=ri7DVB`eg`?St za$6@SvYcPaVf!D3!(epjYP{u)(snA~I>#{0%=Swxy0(*+GbxGS~IM%HU z-*s0x4Ddn+IjyeBk(NcdlWGWT%7^yL3*4biW)3v{L-LGl;_^?L_vx9!PqJv!L#Imgk88?0WV!=j z@CVH>$m@EOKaD#X(JJEc^6Y0NA)TLJ>kUD;q;TGRd_W6nwhRpkdoeY+;m`wfkl>a<`J1GtJacIp6awag7sds$ z6{kM5rJRP5TYiA$jW9fp^K49G{RPo;wMr44D@g4#YnbNh!Pk-Q53nSJs9M)x^rG9H zIrqLpaA6yVSA*5dy2Ql(d2}mV5tQ@}!>?<+-3>aPpzDR=_rBtUJ^X(k?Wt7uW!g6R zwRDG}_QLnu%rqP<*PpJ*NMnFv?{!SWA*V$*7TYlRB(}WFhqEE^%FZ=XY4kA2y5c~^ zPg@&WRNPR8%pE!KnD#OycCk;tiEKtDsioS`&ca=92x^9<*4yDxo{dV}XJW003+Xtf?AA z&YWgigT7Ucnl0~7mT!0)boKpy-3CBo0Aizqcs+A?M3xsF&-FuS#~dS^2MYbTPK0DJpI_GL1joDiJ@#-nf z;}*(O6cN13i5bve`{pUDsjx0wCBTe>BqTI0&nA?AO=@<=iaxm3CHG$^%#iP#{O1yG zfn(pVc7l^#*H09Rin?(C-h~8x`*LH&43+kIT#5w6V0G@N%=Mq7SfJ5|Y$W!9rTEO>-FB0G)QkGa_U&@>Og`;ad@ zC`N_p>Yt9o#BI+XPrOF*`wAY`b^^@THTXedwO)MnB&m2ZNY^X#?87q9R=d{9CMVdH z7wiA4yl%>0mgXg$m#%e$8!LB(#?1Gunxpuo#{wO|A6WLGWFaKaFr6?<-%19*rKDN) z4QDxQ7%@IcAzUL`8PQ;A9h9wdcoVj<0Ms{G-LTi*sX!!|KKECJ2ob8W8L zf!O8LPq^2sR^`cuC8)L@emJ4&T)lLhSDGTbRgT9XYgECoB)uDY$wseVvN{~%wfbm$ zlX$TUsB~`&FhXMyTK@ z9>F%A_u;7c9yH8LE4)ckyyOUi$u+9Bs~B}^#RdU0#MR@lzd+SR2`hV3S#NpLKcmyb z7z9&&zCob?%I4WgB(R6mSjN;tVA8szgz@tpw-jdbf6^x-qu%=ru~mSA;3 z6UvJ2#(j}imI_PC8h-HykV`%zjZil5R=-cZ=#{iAhuR;xp}z9VKV7~yv+cmxHVp8o z21Nnrxj)pYUUqKH9nQu9^G8=;>No9YHx2JIIix~62OIGMVchd{{8FW{>G^XVGKQR0H#e|G zfL`{+IP~4JBl_GbJk*knOgcb}PQV@i%2`{+bN)P%e#mR*#I;8!NR&tr?)L1Yt6^oO zo;?leJHheuA-pZtUp-gB0tHm_mJ%4JQCU+8F=w2yYpwe<4>AQQwXJj2a34H^(e-XQ z=(>m$!U12dNVktPrZJD@mv1V@4121*p&verGvOgaH7KoR{FMUsI zu#5&PyjZu9aT^3^f!w$Rz-S-l!D$*C%eN=hFBi8#+E|w8UqP+N%z5Ri zOQc3vpFSm;JY1`GrmABwb#_o#FXm$K+3AX5?iX0~8En*hyMu6u*?4;J zbbE3&H>d5)e-`irFs{yKw0A~v?m&6dOCt*zSVGP?JoYeWNTzb-hVcuc_QcFm-D7T$5Tg+uL;*cn8hY} z9CPEHfpNG`p`KpgezoSnosJ7TUNF$GWw%Vg_D#y^^hp}E=uLL-leZv2^!EaOrqpgA zh`1;5;sd^eWm+7@TjDO@y6k}|IVTApjo7uPIb=MK-(?tMgk+=ZdcJsi=f&d*6Cp_+ z^qxLttAAd_f%YSue>TEbJ+Mf!I@qSm0Eha*9i7MfqrfamaG0M)k(+9_JTMG@h>JMr z9eF8QSUwe1mhZCc9dS8YqR!I8`5IV>lmIZM7l~Q&s{#S&ByN+zQq`;${Tx;{lkopM zypl-(XNlV0^2w*uG)so*G3HR?l4k&THND_llA?Kx3?=cWmIdy<+*BWc9@j&=%>*)! zJ_uTU5H-=5P(7zh?7DX3qTCavfIb;)9XVnzt)@cCLZqqlcXG(@Y5Y@FHQbMLk0Yk00$g^leYlappo8w1?p64t(1Fqa~Uik z@9bt^Q+fPVzWRU&jU5!1{{>}r#P`XSVH3Vz z0n{dt&A-16h(kS}4zV+i6XZCX_HSBY-53i#mNv#YeUgE8(SI8 zK`4&*+ow+izCZ2&rk8G-JyzL|E4?gReF?}Y@yyn}5P?zN!Kx}6!puv(uy+4}$88^+ zGY+3Am0P9vk1;qojl!#_0)k=Rn@+o;N$+?6OFQqNHp09zr2mx=;FUnyIA8)OW#E<6 zIbsQzMrVN4v`?P5ZkD@VU845;jL;M;6hzH!ip`eionsP@Piv_&oD>x{}&%kC`q@AbVyr-qiiEWzyQL;gd@3;%~GK>*RPoFdL9M{hGB%TB3d#(d9 zK)!;##HQ@>|9#8Uc)}fF)XZHd38BjZ|5Vga)%-eTqJvRy%S`Yr?fK84AFL=K(j5}% zpFY(MD^ilJk{VuO&GQzf+ET)t4S(foaT9gjPFyWhxg`C-tuCnVMv+rPbL_Hnsp?B< zpgVeim_hs8My%v6mMMy#I5%zkcI}u)m32c=SJaTM8LM|l@EEFf z7UP^uujmu(-~(Ew2w%*A+!KwITxT0@v>Vds`YYtsVIhy%BAbOC`)=g{OopK>$WEHE~*T^fLx%miARudI9F z(J_9@jZZ^`H+}aH{lG1&mSPqwX6FnyPCfcp&p9B)XG@iODI}KVeaFo|8u^!>4W3;G zxL=PCr*pMncoPO8{14pk6NIl=09nohk{32COWt0Lx?;ijG8qr|x*IJ(y^%Q>LrgS=e?=9yKeIc^5yAK%o_}SdvwSzM zpBOAF;75N!q(Yhbl!-Thoe2j(%uEXYnE%^iwl+L<$Y~o(- z1ct-&(cv4I!3K0*e1B=iumsZw-Ra@@c=4~R%_(JrT~0QxB;Xw`%ZLvpq?MWG{;BET zn<5i*A)uw;7BDbNu=8kF^gygaMY#bk3)H)Wy1RhSrCp|8)Tai`pX_6+5C2U3c2%SK z`NHtou9Hd6qitWj?!0n7_XA>;8O3?CoICH6j5AiKKZqFTjhLxeUGvU=GSkKKQwIlc zdk=$}2ip06l*CR5ZV*rm`I!A%wvxf^2?7W37z<)+3){JktR+Xt3*<2zET`O3RK@F@ zi(ttP@WtB%j~P2&X`0qirYZJ2H8UzA;!;OfXRB<>+bZAPU>AC~gLDw>c!z$9Vvxon zL*criZ`T>?ZBr5S!#P1|Zgt+q1EU?5aa=EtfF+CeRxAm*YQ-qk{L&gK3(B7y`v8tG zlqKDzDZ(rgnrWZfMga&22N`{)$?j2n_c7EYV>)-Bn>yT$ z%-%NOd2We>Uh#@`nZH6^$soEIHdx-sxycCV$3CWBiQ@{Vr0+-AywzcX(y9_iFo2bE zhUJ#4;h8ag1TYoLU6X-E@|_H$h4tvyQk;>bYS-gBfOc{Dh7KRUL7$YESLa_t^QhGq zlsIP|By`(x&J->lZW+y&vn?Fd?P~FgUjDf=?YS!MgJ6w2&L&ibQ;fa&H!JV&c{b_3 zafUd^h?}n1mVSz5_v8(74eGvPUlR8>l{MvP`*+eLBh^4Pmw@q^P4a811J6j<>or8}BVun0LA3IZQI1!Ef)d6&_>*N$P)?tl<(XGD z8Y2riDU7>ECeB@nE^i-ywa!kFJU51uoFKFZH*qnGuV$aBjFSxl4i@{qHJT$m2u&aQ zJMq_=X-$ax%FdaFUtxGBSf+AarW;xkpEWMWn$V8>upDxO9cdk2G;dNhGKbrfN*{d)|-4_H5C z6lE7>?*EB%`w3TefVbo%`G`9~8TYsJCZ}}=MM`lj=u=XG1Rte$dH~z7UN8i-0=L^#)+x?k5P0Pu!{5lIG)HoIR7?OU=gD!>AB2`4 zXtkx+#&Uy}lme>GCWJH+2NSR~dJN1hL|qXC5!VqE`hVo_0$GZ@4p2OjtPl@JvdCp+LFZCgfVe+q;^X=(3;teI5d-F;}^|Fxta06`3%=6&T6Am>?^U7{kA* zY#V$#O6w4c@m19@Sokb9ul+Z87vw#t0))NimucPwp+<8lFD738hXLPvnOqXHm9o6+ z04GP5@SR~KB$&XHrKWp9%`k@FUmO?&q4L__1&BQ{6VQl_y}WIw!M`w3i4uUcp#h3+ zDC!w+Z8e_QrNYZKZme6H0;SFkkT!Wi!T0zY;zVR#MkqnsBeXas5-InBYZgF|;&`Um z9Y&;V*;S?uIj35&JB*cQ29vp($(SUrCX|)RvtXT})h}%875}@s zFs<1_qE#=hE|)GC?|c7H!}3J_HzP&!d*8z&li6_ysd(YTI(v6RshL70vCMRb&^!r` zUYp=v{a8(m4Zvd3s7fWFb7_Wg^+#`zrxig9yC#Ds9q^c#nb zGHy4UV1|sV#i*AyN2k?K=Vlneaf7OfjcW4p&k&;ufqx`V%c5{^-|}WcoJ_TQ(`=%q z-f#T+=}mV1m;OJ$p0eJ({ggo!(lSe3zQ0K}=vK^uXH>N}Qhv?&fuE%C!q^vX@(-T9 zVNIiAO*os=7zm##!&HeAwv4X{qlT%^CQ2A2_iZK|ZI^^=pw_#4pRP`66DR|5lM_~M z#AE0&ae_& z*@0kQ!tPnya7np!=RnitK5++CB7k}6p2xNa4x1o08+IJa+(8-`@(mSd+axMKEAw%E z%8K(d)+um4{$#5jkD!cic*PS)J?$22`6s-&%LyA1psS&i>vgEcVya@9OCWnFf4f1?!Ql|c zMPjuS$KqE0E|O-~bQ4@Q^Cg%kseh>W-Tf72<>;VP0CP&EDtOdHm-==|UHg{8w^|>R zEayOq>`!P>5fZjriLCf8`gHIn%2K37o6zxt#ye5Ck0?p_t#mE2f4qsaxIJU*m%CJ| zmNXN&xLs)mxpSk^V4Fu;+8&90ZIt%0Bjq}$i6w9CUqI=rOuNJQy7ebw}^7@ti@f__v zikD!Q$C-UjTOc1kLnXR=lCQddVJc4`YAIR;C1piP>%T}vXj^2~ge+JK_}Rb+2mAhx zgv+B7IE&`P$E9U81Fq(0!^z92bYyw$p(8R?4Vwrjy9yoQ*397};u@v(S5hPrCbUsY z<JP5kG8)c+g3Bg*r?H(Z$5C9jNhtm!e#u;pObVOuk4!wio7^>!U@_g-?qIunBHU_9qB3%&)TI(9-(-%J@d2R|O~S2eJCx zSojh~&cAjuMCS44y>a)GvO{u=CLEVOwz$ks$45?4tm`&^V;J0LM|f+$3%=;(S5RkM zm0)+0b1r#$yK$QAB{UsV08sI7L(z&b44uLAWc)Pt`RSF;%BkU$bxP(e)%|s+u6!k? z9HPkQzx(~r$X>$kwo&RqdpcWkK2(SZdloc-%IEl74JLB4vX0ZJi8il_j?8sPj1OxO zOims-%{-nwEx1t$Yeg}lY-5|y&E)7&;-0%4Z zUKo^^E_qxU12#t#Y!0G#HTRtmonwEc!fLfBF{Db*B{ETJypJ7zNvK19di)GHHU;y5 zf1UM13@b+mi05c1@@!Z@Lz^;+U7E0QCINX%xAw3Z0+CY_Pp8czacd&i>^;gfvT!gK zN%jvo$ZeP(>vm|4C`P>zopZ|axSn+RB6VX*wRG3x$Ip8WnD>pWS1q;sh^>v-e8IcY z-$?`wzh}gc_b+uwTV>?h$DQsXPGw;~rC+uG&83z@6W_OEJt)ClrVH$((qXai+;DXk zYU*>!<@D#Ka#0&OeYf%-(`4s$>;|80hXm;XldkWuy*ur-QNV~+pJVaKXmSal_E3J3 zlmbWHKZf{8hG)*GK&FivyPdzXEBszjNZ~dcg|51f)Fu0%VDZHW^vW-(Zx3X}i496m zF8cB)A95B>HAfYpEBfBQsFvgCT6l%4&Fwpl>O^>bqPsW6_DqPL;haQlNs&GOZT^!H z+G*CO5ccQ8brihS#Og)ajRZR23+~lO60mvMHSSEAG+TAZPagJlFv6V7Zc**zEV=yBS@2;zd}6;eOrZ*gr>E zB&hLtJGUl0A;f`Ug%pJ`f8Q*g%BNH&IfTSt)Jz#$cDmV=Oy}0_^une+o3Pag;E)Le zBc#2Xva8KVe(w}^yy9@%R$*nISE_^J)#}EVtAc;Y^RlS}rw|hP0f8mx!m_^+Qz19r z>U$-Bb1^IaKh?c=INSUGH?C8+j#FxDYt<}blqzb*9!14!sS%1Ap`s`~t*Y9a+FOKE z#E7B`C1!$H;nZvr~}`(B^>zV3hTcdzT5T*=#eKIh~0dOaS+SJFF$ zVtcbuwl~^7<$9Wban}gtZoRsDq;;&c^qh{ikHyvjBQ?eAEk5e^31DDb=FFFO+{hIo zXVfVcJrowoqm$mm|o3WkwW-*ddckSrfzb@WSbxY)9#9 zZ#b`9JK!8vYZrtKc$oRFqAXIqY^h|@zI89NSPYuXE7$hk&-;<5#_Qm;+t^(oKLXtD zRQk^9_h97sgth{wOHN?~e#;Q%R2n^qXemytK1wp=xZDd1&E{9WR-q;V_X>DXtm(@B zqryOCKk-z08*c`m^6HJyDDMrHK?mS2CohaGx?LIOxW~|F4A>Dtu5f?=@bR_Zl;f9k zNJ8)5cx%0^CA@TRKpAwd0KWc@Q^+N%lFHCqtM*%^8c?<@&mJQ;4_66JIiqLQ?c5Gd z;hA13D|Z*l!#|a@-}-uIMCwXH3r*xhYoL+qJNY5X=SPt~HGxPUbJg2X^;MrrNo?hTkkn$b9Iau`zL zvwG!=ZN0+&$D`VjN6IaBtsL)`B32oAK(i1DMv8c8UbH8R(t|eIq)y{xh!D|QbujWR zef^z-r0dIQ+FtpwHl!=K-P|%7#Eafs3DY^gX!wQO8(AQjOxCsV4=|tZbg3kQNPUqk zlC%iT3JcE^PoY}NZr}5$X18zrl-mvYq~O;ftXAD(%h5ejM*g@Um!yD$m@AnVy%FOb zp@k1Ev98lz3?h;Yj~^hS?367hh&?{xo<-^^@2`-8R+=|(63&NN3@>XO{MeD*Gw7;+ zINd>ve8^ArIwAG`)TT$k_eYZ>pFCI3^rhPVbeAJtIH-L21bzB*Ng$~$xF`%JKoYO8 zEp0qOpRga-o(MbK`O|R$CS|ai5wgy@rzSw|?FbmJjZYwiwd7_Rx z9I}GLxB2F-UM0WlZiX47su(AyDAHCM;gDnrWdnS2QUf+%`{*Va_w#mS({$Z9+l<8^ z)DHepZH!+P}>OYJtgYy_0J zY$-5!IzuWlW`#9n%7cU;Pnh&<KLI`TLK$REs!92 zOkVbl*5*H_NE}SX^lP!`Dr+w7W~< zr65#F#+Mn2TLwJ4MJH$lUvk}4*lnadZ@&75qJ1Tq^+(qf?NE}op8kwZp8weX)<^m< zQNsJo#&XGFT9Y%gh{T_Qs!U;=iBcn_hNF5YQh5p8jX|71DkD+M((o@7o^EHeD$} zpw9J@^-2qvGp%7j?F4H?ZD__&>2z9oc3ZLO?^P1e7c168SVV zIjOCzuy{x-pEdXi7hpyM?(VdZ;W%4O6(nK(%cPcwq7Vb$Mww(JGrl^0-p+T$#;#0M zv?MLR(25kjw(ZCAf=bjj>Y}<4Zx;KPkih&)N z;WZbz%+kFJg{1KK_P%)eJmU)>Aq%%U;D_Yu*d9KCHPS{*XcN-4FF9CXM?t)QwGDEY zfuj8f;K3)vz3DSo4kC*Tam*o#BT%(;vQ%>C0b(g+h5}yNK4v$?rpG8Z%)7EYl10a@ zDB46lJwT6VJQXH=!OxtOe%;=yoO}KDwZ-F_M_$K7AI=EBRbJlP`? zUU4&rQcAd|Y*}p~AIhtbFG}J|plW3Dy~@JJQTyxiTsS0I?t$XYbe8F@iib}2ASw*3 z*`!~a0Ao@nP>jO9SBu^hp>dDRy_WjOaFhOS{3%SFhcj4%zJDn8Coe+x%?^KA$2~5?{zVLletX~X2Z^rbjxyk7- z*MoRP$k5D&Y{(5Euhs@4-+;1l^g**$D{p#G6Z}arYiVhKjQzO@T#w9de#?#yo>CyB zkb$@!jFGkxwD&GG5bR5*I%Mh`!*@bji2FyX##W;awIFIU*?R)g?A$!VH|z7T^&g5` zNC*>RF<-u|448r!c_g9Uqj%thy<-CHIfA?bfOa|zI0oM&S}_Bj2`n6%l|(z~?`4&5 z)E-j9cfUght#`VkF0ds?wM~~lk+!r7n?cl1H|_*ve^QqEsCadeKb3mGuhrANg2cQy zMZ!qP>(VZ9#${+!uW(G2f#NqsE*o*)Ber;|E9|Wilp%e-Rn-dwg1?1CSSAh~y)^Hz zTMm}ciU@gKG5q2e_Cv#NdoIlBY6)LDa-Nb}f5)*=2L5KS#EUxc+O00Gj{U6GkbQGU z{HgsUK{Cb_c5Td4(S`RM7eS4(>yF<#KsdyW^ztA5dS~Lr%8i=8te1KPV|H%iHT*~- z1icFsIbyCSa0VT9v8|1IIYHhlaC7{o;L243X%V}`Y;vuB793&GJAJWzquuMv+CvM@ z+27p}Y`!2Zv%(r5Bc$qv50&!D^$Y!qE!lAIyxXZ0DVi1G6_$20Ru5@hdi)u3MXfIG z=+TUw?7zSq+5^N%MG4I7D$Vy131XpnkzJ-xW<4h2>ymDN*Z4!#ps?H}FgMPKL<(RD1vU zeknwXdLhF6UwwtQGOnyk7A8vGl;6&An#m^IB#`XSF^-`p_CdJ8tL+a_*!mpO5)f1T zbP*fypu($LS-2h~z#VhwQf~k^H8G&6I1dWw8jSo)Av->}W%B(ZL-wPEJ-?dv(5d3{ zNjsmvZ_zmFm6ierSK>Ax2~|@maxiudU={*Y9pTR9G^V_UbXkeLn~`ZdQ5 z%dk`ds0s-Yeg`{XwE5Hm8}Hl1A{c$}j9*bWD(@nJ!w~uYrX>G$V%RH$;iu6`Gqo!z zX?+3QAw|W_eyYn63OEco!E`sb%rO^wT6Lxe9af!vLx^l9XRkEo84m(0!X!70`Au2pZCJNk?I&q(V<2VfpEqdqB8gqm6BVZ(h zU+xU0Pm13A=Go3|XnP9zRC4F$>Ij-B-I#Ze*Ud`r^!ahM=i9nMq1dYhsB*<`OU$>G zOAgF*D8JI``{nwU*{Dpx4V2INxzbWvmt1#YouKMM^#Bxm_hIyEVx}AK<5F;Hl$?prCveP8M$UTY}FAzXB^U5e)4$+KpFCT`-u@QFGtf zpJO@fwG4q;_=Q@Q8o6@u+f}hXyqcjC={~{CRBy)tvY!&yzfCM1>AOpq$XnYHK{h0jC+9NCXT}7YPF$WIo1am4g_xD}O>`SJPN}E^7Q4Hv)WEBBO>b+lnhzWBOed!cfm~w<+&}VTGIP1F}%kB98u- z!JKgHT3~D_!)`JY@ydqEzmDpoOPi%32wPDhD_Ql<9*4GzcDVdWP7#Zs4nCRdxe0<{ zZ4h|&bwq^Qovbn2!9r@tas{|rS*utEbd};yP!Vdi!^cn2I@GakgsvRTC2>N}mlIIk z7gjnfVged}HppLH^Z^K-=U-i64$3}@MlN~DG#E7fl;msMZ2pT`pMQfmIb?+fE&S1> z+$1tiICiVJ^9%d8N8(-EPj6I+K(=vC@&yR;nBS&N8JT|_*Nbt$Z(CSk=dtU{ZoqLz zeHSwL`I}agXuZRBl34FV)nxDhM%(Ts1~eOrfJuUOmkVe%o%uJ*p5uEy83qyFbA1vy ztL1JW=accHx;Zy2Fuk9zc`Qstr3ScCJrt~n-=By7R^Y$#PQqEc7DTnrgPMpJEy#J8 z6oE6z4o?({ZGlW9QdaH4u}1fJJaE(*N~3MQBF?h>uTLq(D$mkxo5;<1G+-uMsb5tY z&x_fb$XV5w=`+n?rv1I#E31Cw#G`~+W>*d_e;#d5edk<5%se*iMz9|W(*@S~7V&}M zzY=BBbwtnwlnPa#`F}t*OzuykDMO?5kmh*nDMZl4LDlur`pYKLt1RDM96U3D?=jnz zOW&Cm41%wNdiy;9S?!uTW=FL z7r$g(uD-3=y3s8hH453D{CWE+098i(=xmahMDWf%xi73IFJM0uvx+QvfRKMb2*fH? zq3*&UJ!Kdu$`!%Xz?aac#)QV9<57}>Yb|7npd3lE5rF1EVpN<8h<}Q0xmvM8O`l92 z*Euc#2hJ2&y$5l#c`}G6yU$~3;gRZ&$pNh`t29;YL(p5M!t=`~f7S9YGvAe@8z57Q z9kT;!m;u!7{`1bh6P-T|p#EYKvSy-RzA*dtzLzK)Mk8a~bwU(wEnp8uoSV-eOllZL~BXja7N;u{XRr%7tK$ z??nteb5PZ4gygq^5H-npVf|vVRFL&%TeMX7yx;arP76&`I43$v+$gg3#e>C z8dAQJ9Z^_8)$&Yl=axW<)O1tgn+UVrH&EOo#=|w|((bFnrJ!BbuzFnrU&yElBWXdED@oUv4kYvKW@U39zHf#0N62%+4upb=@%(|z?ti7v@b$}|C<5oRr z1Qrr?{%yYHdiZm}i?-OX!JmheJxeEV#}^ZNLDCM{Kyc5+avC){wG4VZ>I zuY=sUZTvurxeis#pnWQ)zNe;56oDYoKcq(C$O=dS7U>32*%OlzRGvL&$Zi zl5f7HZL1u}{N5^G(Shf~-;d$a|qs z0FSgN%JEpa>F(H+Sn+D)f@T@Ns9QTwa+CvulFdD^LTlWk)Hpwc(p zxG&H*p;(<#HC_rPyaznkQt_^z-`^tMfy!C}Y66{@#nV5uVsolTKNX=me`d5+EB4TY z{abDD{2mM&`o+vu2wCcU0PD3^(QL=$lXr#0iIeSH6 z(L5gTS+f5T#4R2G=ics~9C%yqco|Ob?V^J>M3I<-4_A7H=_{2CbVEcS_5ofsp`aB_ zU;`Hf2%Wg0sHn8DJELFoG3YUh^p%W$Me?ycZ;h|ciljm&I1#`$15dDC8()rETNxcc zMiFn?Ws9Tp;I)P%AvUBk&khDzS; zrT4kzTWcgR0j|zE=K64Lp~hjRS4x4Tm=2(?#Frnmo>;~H$Sk1pLH&rC01}z5a;_u- z)K^LoEk_71&o}svIn$@`Ke{=0Hk8h`U=Y2T%$o!zTzvcpH z5(hB`%Mn#`RIUHfx){Z8K}cSPTr(JpAekoDDBs2%GgT=lcvz2Ac05}D-Hh&2wD*6{ zvu)E7l&rZ$0pmar@^%C{@?>knHDJ9C{{mkKXkne3-CqlqPg}}8T?ibT> zEj}4f#x-h!S~~YycLnpkfQy5*j6Ufa7(CVNa2c=}-FWR;rgPzrLNH2qTRRzl%@rnW z9bf!GXxp$fJc#I;tU&m)asA}WAG&=DPYjly*mRvG_OkqSImuYTVi&|KX2sr2-iIeb zkwJeWx1Nzmb~ zfb{w+(3!zrwpX9+NTH-llR5Bw^_UQcNOwR-)$Zx)=6dFYX|JPyH#u-Vx`wtk(?;Uk zoj3=;C#k7z@h4B7s8u)g{_bZa7$YtPnPK8YRjJr)_@f7}`9!_6Z*C8czvsw9L<$~K z!!Et9a*h^%G#PdH=iir2D2z_G-FUT)5m2t1pkA1(4SSAMT8coGuf%#aqTjy~06R|m zMDZYMXEr{go-BpEW8-;#Z~9Ge5z)@SZ=WPTv$uTrs8zevK*(Nz{2+bxq@AMCvx$eK z;ElTbg@<4!AZIIN;B86udiYCFX?cRr2h+{N5p7jhNIT2^47TZqCwRUDA1$;*S=rxr zRdhLX;&Es5mJqkX{juB1p#XvWLmvk)i&itdT{GW?diKJ^9}Cv!DXjHX)y+wUS@Tiv zJj6!WptoC*bQqN1*m=@RQuGs>s>24Y$VN9(VRlu-XY8-flc|d}Z8I%pxx-F?wo%y; ze=%wG0nu&An9SaJci*XcCscbeuKrVrwks0V5|>O9PwvztHoTQrcvxNX?ZB}?W3g6Q zJ3xWv>B_@$_Al4ItkB)ie>XoFa2ruxadNshD8e?^NGRJHM{fkCK0l0Q!o+twA+0F> z26906#<#>~O!`67{&ObR3)&f|_R8id2Epql9-ZXfii{c9HqwY$pvV!_)>iP?)S@=k z6z@U4&@g7Th5TDRhBEa;U~U*S_!V{_FJcav~l z*lW-ZP35QiLND8&!v=5rZ5efb-Y{>=hCRPj-(@Dt`t_$>#e%f%0Lwd!f8JWnY(D$@+#)4z zuW!$YPy!=x;IP+TdyG`ZY=(ZH^2nqmMEuC5I>#LZ zR~X|nFG7x>C36lYrY!T%l{=c_6Fzd_JSJbDhMZ4t8dx?vJ2IZu3`w`9HY5U;I?sZz z=MCtla{hAu30{O|y;p}eNu6YhtF%M~Fvw+YyoVE>1M&lSR~&Cen(qX>4BnR|Uy-&C zg4^DlsX585kdngzxt12{y8F<2i;l)C!$0n^*(I0^vyp+sipGwqVliN~1B+#b%dQ+P zgk+Uvjkkp_^i*z$TNf>)d6!v9VA4>K8hqQWN#hDX$HE_%o?G4AHVp;ZE9LxyqmT2BKm6uy9S zcgqiZZmmE+K-Y9IRs1NPjg7zpMi+>S>|rx9|MyunMrzxMk3Zg@p&xf>b%fw|X3w~7 znYH~h62g-m>w8d{gRbdU&cETg@bJt@1o+6!{J4+B-KF_qU+AmS&+xDUy~5_7%N&^5 z0ciQCVC#@99uU@vQlcix`4e=9Ph!jz!8~ajzeIt`VICEf(l4nNvUQWyjKbg%O4RpB z$>}hZ4|h2SLi6VeyHEQ_BM?5wts(o!#Nbn|_0Z~P-P1fAA5i{HQkS+vxnP|&sk2lN zHs%qc-AqF7ghu z4YSd!XY{wC=FJpM6^C2G#8({4^uA^EJ7n7k+9mVUiA9fbs~#RX+cc6Ujpk2!UN#zR z1Wt5dHPe0aMNEkBwx>YiK{K>~LHpoGlJW2XD{o}UfG?nAlkiRR445f0jPaKcLvx7q zixzf1-q7Aw2mc;}r_TJRZ2eW!aF{g&bSL8y@_haKdPfNzl)dFIPOY zQed9`0%otBzm7k$Jw1QC*7~(;N{?Y zY(C7!(o^8AE-oIL|6<~O&2()g;&b_^wjfzbf}Y0f!o7e^(~_(i+O8Z$3!%N1&?=&v zhHq+{-C#?(7d28MjjNYgAkP^4)UOSnba(Ns9>BBa%tqzuvuXSCy(zr$WpwLp>PG7Y zU|xKWsH$;&X|9ol=Y0nRqe5KUT|XKyX+~JoZC?X zFCmSw0S^X-)0RS>?FG%p4SxjPnW>-C^HYJYT9k|)LAQAc#)k;+1jaPZP$s=^6+XFD z)@otaI3vc|XjvS5-Q(mVE6HcD120PCGq`Fswgyx9{Wd8-=iXs4>Ep3CnshjE!qQD{ zO>PwXcFwKz+mX-J@INfpuKBns@Sr37v(<*#o=2`{sSTf8DI5JN8TwaDOO8HTq)@_^ z?ElJZl-uCd0vBmhlrYN^qfhOKmU~ey6Tr2~xtbZ+=5}_)NdeVFe&D-^GEe^7ukUFQ zL@f^AtK_{XF9a^vCXdbJ@UV30uANhi_@DcG{L?scB-O1t@)m= z-uB1M!Z5ws-g;bqn7W*qqM)_wgo~*nNYlc)`?Nl&5*%Po36!S3N^bj_q*-avy1eX* z!TI86w-mikxMCcSoOVO1%;v(4rsPIkrX$P0vjx9W zqnM3~J1BTdEQ}h=9oI28BH(zRz;GkV({P3Cc`R8_)*$Z|Z#Ur6TKBAwBgqKWiaof~d8 zu9v&e({MAVnDqtjm1xGri6seKahN)LId@@bf2|?q@E^Dj9|TU_TDw*=S}ScrG@ahy z$nhT#{08(Sz?M_fbX@zZ^ygHpP6}1wObNG6$|^fOAo%53An5ec)^$o2NJ3fumV`o$ zAg}f?f;&_{s9L-UL(Rx#2FZAqdWguP&n0MQvdk8Rv6!Ah9Qfx^2ivs{5*w~hoaj|J zS~G{i+TIestlw+q6pf9ir)1vaq^~-o2lUuCPiz{te6oxbjX5_K&2e%tx}2XSMU(XS zjriv2TRzquQkz_<#y-NzqOsY!`IL+aj;YH_CI;aR4Q zXaXOflB=u5x@9E^hy~>vY@JFwhf%xR-1fX=^0`XQl$v@)F@Hg z1e7G9e@SVe$(uryLTGX=DEdhyD|tU`8wVB5Or03-rYO*|;#LG&Rwce9qFCMZik40F z=vQO02GOsh$g9Sep9Su{G_T3NCO75E7#nmiZ&LC|y6)aN2-k<%+(qmZ`;r4mZ<`Gr zN?3=0l^Ilzwm9&N@L{=rymHBmT}?|Uk~OsWhf|9|9lQK44(9reDqGD~nW>}Vo6Qq}N?j|P zjQ3XWFq+#5&)($B8Gl3&ejqfbz8N%%S2$hs9dMbNdqr>73?51Hh37;`^c+ljulmF< z3*S*S#lM1-dR!hJfC}}kP-ul2+H5Dr*ACD-Ej?Sy9Vz-uF2qySISezkfSqgoa@E-k zi~(uzQ(%#|cz^RtIexSVD&(ZQ^^}}w8QJ-?_7BS|Uhouqs=@7vEnA;+i;%1v{&8l~ z)j0vCYCPrV27Jrruu$DJ#E0db^WolUf^nXsOQ%2)R(#{I85i4y*zzT|jpZ8|!c#8fZLisCCP@$EIRn9}wJ$pqx6wF1BD2_TN0O;j#2-O<*$An+8$n8@zA@-P)luKGVl<|SL*SFDRxVSiOCHuzB!wcNvl+pC9Q6V<=e*|f~6>9&&5Ob$eL zYOnASeWEAC%po2|A`WuFwz1XqBqXka)(jgryV1yC)&ejtZ;e~1TFqb{#rb{2;84K1 z7+^O?|J<~XUNL;~uhFIQ_1XJ%sTj|x;1LQDL2eKnu{555{ZMlCz0YNQ+6+D%HTUfL z-^w*?T_dfwnyii6R*lHxsn3vB}mo@xnI zfo;{OR10rMdr_=AXwF<9vr0GR(rg)K zOYNz$(m{XYj%6K(6Fr+o6~y~c4egkXi#=f=-vpF^vLGj0tP?I|y5?7xR}{FJ5sSh% zyl}1&@)mzSyI?>>Db%EuZ(Z0NOPvfu512W{*T(zy+oBPZ;Z0J+Di}- z>xW*lPFreAWN?;01BbTxNQ&-y{i-xxW7xa>QRj~ZDPwB#>_A`AN12+y>sep(9enEi zvrvto45UQqn5yNId`})=c`Q)^qFq@y{7Tr^mCz4s zWc^fjN)!e3oQ0kkMu9nJ$z+9s^cr1rx*jiYw++y+W9{wJUVL=Ttx+~iL+bD~UFx3s zVCi;s(BToi{*}g=YF?GVdrTNYmoK>Zic6JkqZHlmvFpRdOgFK9PY{lozF+%!RdM&9 zD79YY69Q%$r>C+P8^Y-*N3wN0!xE;=B3bnLpc%&d{Liz02DaXqkYBa>;HxFSf()(q zoYHe>aX7xhrI_^k?uTb>Rn9CE-B<+mMjGOTI#?(#FdK8Q5>BKR+0S{)^XLLAA?mht z#?E7?n89ja@Nxq%KW&+8X<$o`+QZ7gr)ywR<=$5UOTQ2)7M6Lt4vk6xG7)=~SnAJE zSXma9r<&`s8T-m-R!J>&fQvH0dBEWGA&q|?UU;UsHum~*%)@5w}{C5DrXJl zNP&mf`@AgFSXRXQ7#jG-ptb4H)V(j^Ugw)ZOw@BN&hI_;Ep*}@)(HZ@E2 z<(%^f9{sxa!{br)NKr>AMQe9+Q9?`YDQ4ddj&>NEvGDQNbSJuhGghd(xVzP!k@IWr z1wd`UHePth%-AphWm0ggF3-NU8fu^5Vz~E9zI=i}&(R=z2ifjkgtqXzy)Pf9-Q=j_ z`7*QE1uO5eOgbHqY_dA?b#L;_A6$ETxbLeM=y`I*-oyO1@_2Fg>NTuVOv2tT>Qn)Z zlmo8V_g=f-HMg3uQ}opnH}{BOSS0_Ha^>~DGwdi#-Wo|eT1x9Vxir3+^#_wm3$%JN z^#YU!-dMxZXt9{(lgF|3@O?}yk>zokW@Pz?Osf5{5kMe#Er7{24@Pok^iCuG64%{^ zK&4S5iGzkB{Sr*Rd=?hJa&an4LT)5gh|higadfquAha}u?Y6?OfuQPO)!5!XED4Db zGBZk77rE==em$c4Q+sq_;MaMcU+IkH@hdQseQ);!e?ca78QA>d_9}SrvilPSe%;om zYyT&!`+xpmHsn9$Jx5=idGOXG}9Q*J<3oMvpK1ua^z}xy@b*@Ho zb1VrgtG0VzsxnzlncIIj?*HW@w0zVT$^%%Pu`Rl=nkhe5c26Wmw(#TURm7U^WtXyo zhvAi}{PYVza0I{Od=BA=O11IY`gJbVXu;>j_xR_Fgq83KTIQ7#4YMA!3m=U>rKoI_ zbQkKJbKL`LnGz^0EJH4%9rrihwZm{g$h!Eme-_?vv3nn*#nfd1C&1l1QHY;c_kEvle(9od?IjPt@@YZs322PcWPFlD<))GX zxAPtX&yo=P@vIhF!nm;(l6(dlfDvDjO}lqIZ+2HYciNp3z9&Hqa*`Cs(ZZ%0Cli%l z#6KOulQ!aB0C)i#q;wAmJt_7Z2<=Wp{+sB>cUqQ1v08_Tmx3*6D1}`MD&kC8aZS~! zz49->X-;+o08Y@>i`BQq_k^rLqc6t9AfvvQ`#?}>b`?S6`gwEr>!xqdN)W%a>1MJo z-M$5rHhyKM6}#v9EX8HyJt|Cal0lfCj2@z{FEF*x^2FY0-B|^no2xthvX}aE|HXd| zAR5D8Jo}R;!X|v{vmxs;AniK6MyDmv%h?FKy4f}OUc$lhA)}j?i*t&zCF%%0(%Ejc3eDK=ts)H+ts8= zU~kFSr5a7mrMcYS`!W9-*Q!(6yk_XAWHhV*V<_ib?sj!$e77dB-!qo~JmM-<=a-T- zaE5!JvQ#>HTIAwsm)2RAxlVKMR!Gu0D8e&_k@a1vOQlaL$gDBPvQcgC$lr=V9Z)iF z)S4&09dw!6aRza91>gtC=LzVq8yckSDaC@b{70~^W|r8oALJ(KVm%jBF%Hs>*V_X^IxfeGNwBaS zT!Ct7+@f}5T6<^uEtClLGo`JSaF!~oXZIwa0ncS35};jAHkN64*6;dk3nL8{UYXDmxXnnN9r7!SL&0Dum8Hm;tI0lb1qACi4OXsdaLAhk5*+>FJD+$F)68> zb1S#&_hHkRUG-O*Yl`I*sp9)?^2;KnOw+92qSm}iMtAlAOZ^`JjY%W^{+p~{o%jfs zdlN0zoc{6jQbb$gLy9UpJuPz>NjI(u+P?nEdGA5Pv?;$MA5fW>pNcG>7?ZCrE`K@q zt4e}te>i$6iIdqgGk1S%rNLw}Wq$gPByR);5XaYd0ImH-^VEiiB)8lD*Q<*6i8Eof z-_2@&7of-ie?08y@8jyyHCX{s?LqdLinl>Vjr>}fCSoaGM>@+F`>IB;$Jy`-b7ysx zq8OV)b=|2=9zyr zwStzQ3wE56axmMJp}dZ%1xo0?&Qdv6%I&%9R^nEB2TDpqa@66qfb`^VP3u;sru78S zw64~l6pL$3Q`)k|K5CY-8o^>L&ms8deyLht(_c2*km(POIVZk%7`UD)AS1Yc_Okc> zqE!AAPmCSBm?>#pz9(r7(f*I#tz(?YlE}gWcW2tvt28dOfH5^i32pL1P0`?&pta7W znrUzA0ODS)lwUjC1*rR3*8z2ZVU@*{d?jb0pm$Gfjs^Ttq5j-~l4g?*`yLAUJ$sPq z-hsarF3dPtp)B>~4%dPC526kY_>7xS6sE7dt4JwYw&f8@_|`XkQaNcBaG8KwxD2#D z_SaR>vXux{lwuq*`M08VrQbs8sRTQC7*EIRRN>WMXi+EhgwDU(EBz;-#B+d93v6@` z(9@VLc5U04aQZg#yEP-1%Wwo)w2R4o}*Q8 zFv(+Y`}Ar3tk&wzd1(5*)5jkl?4A1X>-+!xe{a!u4?NHlO#U-FMxMDBRNGjq`sSU; F{{`E6w2=S+ literal 37545 zcmaI82UL?w*FPG&M-+~VZ~y@dNC%}#M-U-Y5d`TfHB^BB(gGGlsnP`uHS`jJ(3?l4 z_XLP^r6yF7BuF4|C-A=i@4I*1dvUG9L-Nebp515f-<)^%^)$|%VLt>M) zjz5P$jy^km5`6O8V}u#}I{8#v<1S>M{x7pBKOO?P0)gJWWAyyv%4E<-3%j8G{VfM+ z8D=e&#!^qiA!CLyYu-Bsch0u1xZQLbKJE_r+IPd?{n!Yiyxn43x1b!NPmB4U<3ldWixcz(JJVdhG8D9o|gAorB2aX&rHo$d8 z;qb{a`Y6-ElS*>V=VJ#?1M~d94!?xU{?BXesAG=ZdAez-&A}V3tod?fqlh$V*Deym zf*a;(5xCJRlA$3V#G17iI78JBh{`F8AT2w`Q!HkwkgRv+ z3$|7zK5W2WalVr~TIDWG!I=LFce>v1Os9r)JO}R7>l>4$Eu{0u}aSAq@nQ8^%`7oaZo-iXB3`?p;ZM~`RT`M<9sS#UJB(0Bd#dYi5%(s(oUAyH3$t6 zZheDkMH)w(RcGa_z+~io$1QoUNRIrVvvExA#VHm2ZgG*~j;E?zhQsXn7W1-S^7b5P zJF64}+i~y;1Q7+uO-~{lOsOw+R3a7n1-fz7T|?5~tB{~awrncxsFZsN3$$!cxR!-S zPNFMx@uDy1Y;^DMgvye-F;@=o;%E1#$HAWGEp=etsSnP#W@AieDB4arqxE;8w9xnX zi(N~J#9jJ~6_r4~3GHvrag3yl=5{BGF>&TDhjQ`0p29feMeBBm=G88vEOHFs-L6mp zGw=)iSVn`V_c@`3_adk0+Zuo}KZjh=VD_PZ`T8@n2>mxCL{#I&se`A?Zi633-beUw z$0JR4)E5cT>Q*tK)$vrv>L6U6Zp^M$fKF;NeFQ=s@JAq#c&}NXj(RZr(MM6}vlmlg@?@D+1Dr>y?l4q>%-74DQKJ3| zV_K1JGon;Ui6zMuwiGNQ;Ze&{LRedYqXt*#@*ewYgFP}=w%3OEnb)%CT{(?!vEpaB zJ4w>uWE~Dpow+k24C^mXRN7q08TQigKS!s+;-7zyWr`RWy3JVeHD&M+YZcC%H{IdS z{uArV?PnJ$NEwQm$vT)F&T{=Z88=G zwLUhK5t6AO?ehIoUyrC|bD$rAACmgL$~k$0MiK$?Wx3&@*X=wtXH$E zMKsM52nmvl6HXj{+V$12=mXW`qMQ9+9w&~4|Fx|p_~UNW3jO2zmw{2ri8}wAYx-{{ z&M*)gT>!iMkh#YFqwr!Q440>YkfL0|J5$AqBnegbuR8^CK7zeQs8_ZowRl*{bF7ZVV0&EP9$9+O~g$Q<3fB^g9Ip2O2^NoDFoHeKw%hy1Sy z0z}%OK0Es_N2{xIwf=-;UTyRLD9r=x^?432+a^6&pGa9RW`||a-pY*DJml_9QNpc( znf_)6MpdU(Pjn}@wd~PqgIJ~_#;dRN>iSvS5!8o8@R~+1zxD~|DCJ69^nkU9WuYa& zsQ0gdwvMql9apo+h%6vPhR$dj!_GYOo818#5n^=@I3^9-rWbC;w+Zm80;>g4Z3gNd zJNAk2X1iKF)7;*g1FafvG1;%&XlmQq{O1X-q(2m&)j|(spO4bF^w8$tESxjmmM8}6 zP2?vV`lssdgr`yBhwMj$?cUE@m`|b+;nt}{BZj){v7-KT)NsFe|2o};zJCq4RxQ~8 zb@h>$?22+3OZ#cevZvd{JhRX+ygVYJ{;GCR5L$SJ)3Zr5Y^$B z`qQ~@(>7|KYH@`oiCfeN$5lv2e};}*S>Z}5I%anskhbVuA^wFk2i(*;uAzmxD=xf};eLOK{bI>uCngUNVB(<4&g9gZh#62Q_7-aMH&AH{C73_R>a#-}y%y*Uz zKAn^L(-n5z)dQyBt^1-ngLD%H=I9BYLKxqsRexjVq<^rQ4U!d3mGg9ls>J@k=^gMH z11GRb{tBxIKUh_Z-Xc9h_;Uhv;?Hsu2>Dd~H~9NLBQVK>pZd$-n~uRR9cj90(zG`I zk8SvsJeg>Z`EEEpCIcNP$?bnS%tj;hJ?UDw1LPv3me_NBx)w&$ispL~7eZSO<;J>RXSap$qZ z&!Ue$t7E*r%0b;pBIBwKU;&jn5TqcVnT5fq%jb|9?FVbM#E0NhNEb-I zAhrXgp)rzmvm+yPs_wh}kC6Uv%%s2nzte{D4)G9;?Y*rQZn>iarpBXN#nP;D^!PJy z0mzEWpwMWoWY{UAVZC|h<-)J7nQ%o);VI|Qc*Y9uz*)D9jLpm!^&e;>Pqb-S8S8%` zb5;UdsW#3r+mn1}12^|~^0*ooe-8M~7zrlIt2uyaRkrC$M#Yc0Dm^3I@gLg_Nq5DT z+xu7J;U9H0pm7Z&dW_?XYKtrO!?69ucUJ=*5-!`->am(-u5!L8IMhTd*9TX>%~KBMfT$zWUSUsz3HQSbe^ow$1-oSmSIj! zl1#>AP6&0DpwR0Gl^k&!gL&zPXe`v;KaMAb2+fg@y9Lj46PLARt&`-(3v5PIZAMA# zy&gybvxMBH$G@c)lc^<|HJYh0qprqf`?r5Un&3Nf-W2p z4xSx8)N6_+*sRL3WsSUDwk!#{!Wn?m3I7nqTiV*IN#99HL>v1NwV#fL{rZwfd3-8| zTvCo~?#RVexgT-vta^l9mYyO+ygIq88lOM5S{Xq)n!F~B^BykV4LzK$_x_I~_dk&3 zX#-0MEz>%zP--HVVz`4<-l<9Nr4if;-;rw+R0G$DU>(;chkHF^N`p!M$?&0JB}CDr zytCOn*1L$9x|D!Ecc3Q+j(3f|q=rMFja`geEbK0J`cI?YNOQj3s*NXf^AZu$`J{o@ zXe8ZeaM?DM7PX~QnV4$D&2NC;`Ibrh{bJHT6s2uT)$#7?|Lb7Rf_B4)khvncS?4+G zd(`zwxPj}tJ^N*?olu@AogLmAO;*^abxw)lR?T(;WvA0>Yg`&9m_C}L0+zV6t=E4x z<+TSr9YBn3JXS=>&9A>F1~-t_IC^1$4T*WVk(^Q1@{Omteiz8mR)t5mv*ide45mEuzTd%t~ZGS4%J-*bYG?Z40% z0HG)I>>q7`kZPC4v6zn;_y%6&RouBt#8UH#x}6~&e(0w-}1kV$0){#nEicWLiKQv|#j zRijz2R_3d7cASEm?Hm88tz0oiVb1upUouS$V_X^5-%^$;7KmT4@Sg#e(ilJLKTJqK z8>?q*rZ(UH^&DB{7utJ+o37h)F(6kEH+`hyw|;H%8q5g$eQna;Cv_&8$6!LB?=x4E z8Q1=_cXE$qFt$*q$u01^Pfx$|qdeTg+MwOCuRo6H0VYuy1WKt{3PiN9J{VlPeBF)O z^Eo74`j+kbcyk}+P2WlA4$CKLXaLWu2i^+mwG+HHy5HRczxO#(aWQU~k{Ax_KwUh= zHNtvmbRbrR?0p3Z;kzQ-o&}WqJv>_{BMnUqcH^w(J{}z^XCogpXc<7#OFqdmC4rxv zFp|Q*PFwSv3xe(a%B6CQM0VmwaR>|b)Fjg6WJ8txj$8mgoF0NmOu*S*dx$3GNM`y% z<-S_VPm+{H*(%(_`ac3#Jq4)iHMqy7eRsc7~Zu%po{OSa^8b91ukm^+&-M- z6i9)dCjgITjHGNisnlrtms#ZNGmdi`P8^wuVjA}qx`Y(OZ5#`LkNU|6!U#HGWdaj0 ze}$*3($)`e>|KTZu+m(FRMc`sT8`L9ZIYbu-uqa2T&;L7Ze zTKjde2uDrT$#|&VAc?lQ@n*#}!_2io&EZ)6=r_TgH`>A1@Tqp)7}K?q0FX(9e7Wgz znPA9KMw&*8U>hdMPEfqDpjk5@jSnuGnXJP&DwSinCnyt?C6|+-tLe^gV4qFz&MT;7 z01c{>&Rnlw9`!^j-LlPpFmWXOmXeEn5BVf?-wW_j63#{E|BW-?Wyk7}-?7?c7nb`c z!)26QGGdok-Kb%M0>O3!dR>N~$oxFSs^(M3Z*f}wBNevO_D{c0*^~u8P|ql_nio5Z zq^CVip+}hpzTV5*-M%hCt=Gv&B$1C0iNcv@Uwi#IN0so^EzA>h`?%rorVsEjWa`d~ zQ-nL$4fi6KBHbl$-j|3bqMS0fY#m&=D(DQMj(-0z?6W??7Psd-Rb@j<+(R8W?Ewy; z*@|-|&b#HquwZmbvk<;gFi&b$jS>fZ$kxCpWTi3)sVI4~I2oGC`OkozbIo?#;Yb>N z123bO5b>sdH7MmwMBXovIPVV zue27++zsZTRiPpRW71`n9MfvhmD>Xwkh^J@tIa38lXM)6^8*bJndJtUB`PI1n{VWR zao#`LWzF#(;r_H^N_yKf;0jzCLeya#PwpX$rYJo?Zm@!(Ukwah_)FchwzuOoMIIC-}Uzq_2%apL!U4+)-oyO#(7j}c$ z!EOqL&u~IMH=jsYOd_CztQNJX(c1YsXGi-6>LBnbzLTrTITCyRzLviDzo=eN?!&BU zzP;t_(IdlRnJ#4}sl<=h%kW-&0&9>U*T4avPN@ZKfV9r`#z7d$+y$BO@te{MiSl{_ zY@65sUQU-Xrm6jqsT!bN%yJwdp0{UCHm&zv#5hfnHlmVue)l@Bm>h)g%tkO4{(bL6 zLW?W5wn4N;-JkmBQa-Q6($%?hgwnIe_ z1Ak10(>^DC6?SV^-#XHM{c?Y?{I2ZbkVY`%1V>$0hJyG!tBD}B%tF6pm^8C-HK6lb z<|LiC-}1lxU6Yniq6srq}RgogGtciyEkZSe=q&i&2X*FoJe^ zddD5IR%zGamP9-zN}DuI-Z4}?u$%2)%pzAba&QPN603eg(GsiSz)G~_RvunEhh$LM zl7D8kzWY!eZPECMRny=5K-KtJofm)5k2~t6#sLVcCn0W&`m$>q{$m3Ac;A|!euPK+ ztE^2;Y?6ri$eX^9oBz-7;5glZ$#B9BU&5t|yz)^$oHM5S-mf92szq*}?@!Q5R6@>X z*D-jD^;$wYDlMOQG?AcLPsJD~5S+*6k3jF?m!+lrQs(_gW zcMwL}bu2-H1tMF&(Z(SF{E6cfx%vn$c&c0@CrvuGS7rosu{3Z_b%e*TW7x$)_;{$l>=epk%O! zcaj>}=dVm@k^7upx4=SMoL`^(^yKT;tl2AOxevAnT3M}kdrR6^o2|Lct962j$NU>m zGR%L|izk-ZIVZRzoT<$X2c>oUBqFU=2|M>}E2%#R*&J~{SjmHy-_&M+SErJzpaEqb zL2XqreTBnL8XrcBW8~Lr2MqphZxK?QEpX7(2-SOedU}si^RRfhTD!~Q$7plkf<_*# zDXtB#zdgMY{Dsa1>iu?&Uvqxf)2mesUMqxadAQmQuSs>7-G}+CazrSuvNUFob!?91 z1c5UD8O|dFr`0_+Gt%uK`#r9v%BNIqsCysZB`{CDE)oC3wALerL-wM#&UsmXbu^L* zLMrYRav4D}eK4B5z1ni|K)1i}KYYRGdW6q8jiDu#d`U(%cM`!d4(*D=Sc3zz*E{EY zgUX}q>Q^8HMlWrttHfqme8!tTddcRdoYjv)F*!*V=5TiJi&97V(d2+Qs(w7L?m~g9 zhasvW8qwu%b#=^bm(k$u(Sh~qGE5k+<>NfBDR`*zjRSLpTeUMNkk!L55$t$wb7iw! z)2mmydl6$ZdP4zF^*7lOjHYAyl}dWW_;MV3i<%#63M7+bo6C|PhFA~jJ9nT3NRuJ~ zvn)G-3z9P zcVva8fDS^B`lr(FVi$Gg_ztulZd`aq!Ec|p$s_eaQk9>o-MewI!YFD_X?g%3Ccvxh zTKA+#zkwM;M$lW1T?PEhE@y+SYtj0GEHZn(`Fj$sWC=a0g=v_ORcT&~mj6`8!{$S4 zg6nB8C_sZd-G%LKUHP28=~r?@V$eBbI&r+(Nwk?hzNIGA@>pNhTRG7+iEwIS-l}o5 zy03ZdXus#h>4==|-y_b8udEwvtAbi}ri*KVAEY-Z)>>%Nsyok%gQw~?!#4I9o1LS5mQy}5^oZ9;w)-&HCWH@ zj2m*8IM9*(KnGZh=|=vjQmI9|p3S**Tl$&UlKMKOkB!4?&l))Jfm469xgjgbxtjOq z%})oysL9| zOgC%wPE;@r4%#jE-JrO)sk&iHt@#eE zK{4i|NpK|({H?X`J`tMg)sy`bWGHlb#BFo>KMO8_jMa`B5u8%N%!|%v$n|UK2z_dx zAfhZJ%NC_4mr4yC*-q6sp_j-)_I#k@m)`Yw6HI_8Ar6$4hlx)z$|}? z&Cv3P`xV?0PSzV@w=&B=#8x2-&MWukQBgsh!}f8)rWGr!zDfq`yq0*MGW8)3j|_t$ zw4`f|r;9R&^6=hxu9&u*#DR)33lUDIx1Eq$p4OLt$k#iRA!!&mw#_?yi*l{FZPPumi^9Jb2YsE`JR@kpf`BjH}zRfA}>#lCyy8t8! z5hrYT#w@Wa=9=5W@3rgbNGQX6+v+irTpnxIMWtJgEs{j>Te?79GxJYy{~NE)#o)P+ z<*|X)Bf>LGsSF;95D2lB#0G6Q0q3nl?Yvc=_ZfHlTmfM=?)8Vbp-y%6N~;<@hhq?w z%&*%)rdS&LfY5*5lr#R(>BX*BEc3_j(#fv-j|rrXEMtm3wTCs_#sl{oE8I4*mfcHe z%x-Bh9jX3;zT~Hf6@JTIrP!;wZ928Ck!JF}MBDHJJ=TR-4NF~r&d$o@#!P12mTb4P zBw#$kjVsj?HlO4$d+6H5a?ZPM6SUmcNS$U9f z3S)2};R?{j4(s+a3I+_T_Cb>?0(w!nmla(2E=+d8EY|j2z@$@#skMxA@$fQdqDV}? zLeZ+doRs?6)hq};*o@YLi~g=AcS?Ae5n6fdQj_F?+~?5F_kMv>4;kmPj?}HRa zP?G(UeyV_ypYYU_u=a>o&zQrAQk)eZnbo_gQW!I}hS56ny0q?Dt|C9NyH65yDMQll zzQ}(^D^Kj$B!qCNdM^`5}Hf!rMS@nIWJ3I7(Zz61A>Z;PNdh8 z9k3+^@ucLvTFQ(kk6omBZIz>GpKQNRkLh(Z$m;&Pn#|mo^p!3j2-6p_SHHa-WcS zY9lP-&aUtEu{CP~)vg`W{Zg zM;#Q)5@G5F?YW&7w(5tKDx2L#jEnK|g63Qqen#WHaHsG`HK3xhz`Ke`wYqS~IYa7E zeIXgktgxkgPJ@dwO~TrP*SlrgbzLKtC3@kQ#{8DMG?xi6-9CHQPyE6mh9 z(VG2myg};Ge%09Qc$o<@&CU{2l~_U!{a}x4#+I267Ey_AQ8=-s;5@~$QHnx@f+_mW z*hd&eJvhS5xwvB;`c`SM#i+v^y+aD9;Xe+I7wOH|cY9Ud-w{`cBQJuM=?IL>QwjF5^Y@~z zi>UH@W)0OIy%)PU?lf3pe(yZ0cl6QF>06fOUQM^*XX)yZBYFLKm$8bYclf}U z{#tLF?0aWhUAxt0F{tbq2B7=&vJJt(7>Cz2E8p-`zIkAL7_{Vx^v2exH_-YNcW-9h z${AHYhHIwxAeR*5__U*i@%(5nRHmVx$8tZ)H0MTd#%jT#-lff$VuTkzIy9J4gs5^D zs_6)5+ab_t@y(*J&fN>8rw^jrs*vuBe2>_9V-{t%d^Ak&{!86r#*d2^G<5o7wTc;T%5`?U5h# zSWf@uzZoj(h%tQYM6N8EPS;3ss|@B$m)DgO_|Kk+0N{b=bW8>k(#4mHA4S7;Wq1eF52vN0TI{aWoueU`PPUfS|&<9uQj)uDWplqEU-8++TX5J5Gk^<&zl#?y^> zy0F1E4IVUGns9ty-RRy`<%aC<&EC(GM0Q+hPyT1p-jR~GW(`MM+Pu}2VU64FRRi&q zH}YkU<(Z=!9>FYXlRxrh7mdBD75;@{3;ckTM(gnFfVvG!v@5sngKr3mY#8kqoY za|fO+&W@3q8Q5#2NTteLm9q9s;wTlm>Ig$)7|f-xXyo+C!4<6TM5Vb z8q0`U37ca~+M)H*2j>k;-t6_~sX)dQ1|e^$C?W}R0w;?{id;RiX+ zK>dTVf8*O*e)!bCPw*MKH(^xZqw$;v>CRSWXl$C7c2{>g!XG_KYEt+uO{x1OM{f#W zlRfY$@P^D2>7g&xtYq-8p{?ZHPqFqir2SHaU~gWKx~n$Mo)2wqRS`MU`Cy`OAHPj4 zFm9sZ&j>MjnufNle0l9`n@f} zs)1*8#*}7oXdJo&NA*X~TqvE;lrhKgI?)pC7s2qteydATx&p)xdaU)>Kx@@NWyqD{ z()>|Q`C;lO#VPa){=eGbQfcA_ltC6~j;dVwKVC`M>R3$0wQz2~AnW>#ofn>6 z6+RDBzD1P?nU5eG^3t3S+Mo3!+3%4WlXI*d$0kb9p@{5z#&fYb&3_L(dh~9bCI2G6 zv^=Judc1ScDV7gr&gIPGy|nY-+t#tBELNp;tJ`6S2VRprI4{*jU@a=nAP0QMAriN^ z;ej^qeLsIP7pbsH!s$g9P{!&+Vf`Y@FWXIPs=PSE|1`swc8)+yAL__7EDP7A_55K1 z8G}l)z%VF|46LS>HVmzJ&+bI+jO<4)@xiEuBLeq5T<^I?$WNoZ9QlOK`~W`TUk>!( z`K%nU@)h|r3cN{Z(9rAd^vV4U@;;x4s5 zQpiu^DU{B42t7Ehukim$xIg=)F$#3s_-l;w`K!keR;$%x_vC3C(^bF!5VTj7BxoG~ zJpw3{IaA*u4k0xdYn0v`JE8t7)h!9GL%0lR=!ibA0Qp;Ub|^nP=2%=U(HN?K=tM>h zeh>{zM>GF*>#?dA z;b{C!z`y8(q3qvUHHfWxDVdkG!;c)bykF2Ip;OGP?jIs2aGku zh5r{kwhgAG&V33(P_`Q66z61be&HBx71s%xbNUtaInqsvluvWy$#4r1 zUzwF7?7QXrnq}eXlF~gc&Dt6nyH#VG@K;dtB;jGoK_T9Yd`SY2na&N5KEp}xIugrI z>i@fxVKw}xxCc8IEtg!8!SOz95TFe0JbVceY z0TWyzH!Bt=UtH|l$0-F4O`yDa36w0~8+ecP`x380TMy$bmGwglX}Gx5Y4~pt(Q5^B=;WAD9^(QVT)NyMg-sR@~HVUJWQboKn?TQlHHq z3vO5r?yPbjcEZKc($aZ|rBcM5VOR?S-X@bSJA3K`!`N4gdh@dBzYc;s5gd0yBqvBN;>SWHA5%FG_jtzj(sR+~KQr!HRC_&BNTy`pD6xh1>nk-I+FzJ*Qq0s& z=5^mtj3^sMzSwZDMm(yp6E2c$6l*1+WV=7L@l4SLq31guGIz}X!9mE=3e=@zujRCdT=+-TT}A z-}Np1RSEQCvL=8&LRM;kBgHO~q@dcRc^CQKtW*!AeCq#}X(TZ`$_ap;-O5yG#N)Q;J&u({Rabz;sPDk8vi3~cpH{cQh0 zG)qQ^H)!&?AGA5YHuO)(x(SJBgHTG_^wv_^<9rD&R`X^1FQI$2#!cKY0d@!PybV;T+QfHewkW!y0 zdr+uxQw4PZYj))C;TyWzsqD``?%5vp?&oHK9dvIz^iQmtvdPoFXTSTh{MO>WFWa!- zA+3J}|2#3^doQ0h?^fTF8?5xSu~};J?&wxI%W7&=UIU2nMY6m>{e}Gy0N42 zOX0>rRRKi@vRktue@j?UKk8i62sCv62Sl4JiLBeeK1RcdF_Tp@A>qx{K*Hhx-D7ZT zH3?%&@9Q3hf=B?3YQ7~m>+Xqb=LvfDbfAwD^tA{&{8LGH8p@u^-N9yW`&qU;>55@O z7IF-sCgb28PoB;JREG*{CIA+R8RgRgeJ%NkNP6FLz;D2G_7x>KC`RuY%%qnz9Lp9Q zM9{IT2|gaP;B>gvBY;(k?(nX5o+b@!1`z2!xm7a zeGiQ{6N65qtLxF>>zN#M#b}st1#p#rb=Pke$^k`s9sT-KHRvt_1XxGUeka3PiBxP7~20Q(^AoT&}-g5 zvY*(t#2BmxHd+ycTumf>N@4u#;QZVPREZ$4xcV!%I|-JS@}>u4|Fk1d%|X@A)zYp; z%l`#x+-T4Qz@zN4BocejJ>QrC;5Bk)8;KrYtg``H+|*imNR^OD9q!4v6im0!w6JAu{e&gAVqJYCGX5YMdzI~aXd6G zy2J=R*~S)ZPteKw0MqY1^jXKidi5iONNz>td}Q20W40mPSpu%O|HECq&Zx%{v$gvG=~BkI zmdb{tc&Ry@c^s3*c$$+A(>suXT#iI@k!K3SJzkw*y_PH^#QCO_gTpmsU>#+iFkQ257tfT)YwL zTz3*NJj!I}YL<=n%M{An18`?OUEwTkY}>-@Qe!cjpHu(q2uLxVSI6`Gkk^Q^RjJL@ zh^}B6cpl^T*~25)8NgI{DDYz`b)ts4$(-dz=)Df7@r!a7sr>*eGv#FVv#jn2t|c0f zlqGQ~5`dq8-00{=Y_ZaHBvPsxyP)czx=-(ii&z%1LhJi-i;HmxAO`hY zu$V*tb^=I2%hh&lnxA+vPU-e7+r`KzQxW)$9{`H?1Hhobh$7E79M2CAwF~BY2k=nqzLwFRo&`}WouX{6n0TxuR zaC!d9cUL)l@dEa8eu(nsTlHU=fCsu%bxe|1py)Qh2D)p50FYEij6iAw!a^j$uJ~Df zi}kj{cxa_MIUqLt9Ec6!iT_IRhKfBSLe3GWgKXAZa)!p{CSza6WL`Q*`)J^q_)JEl zkWi4;g<$A2L;(oEW0Ih2EYU)u$^PlU4K;_O*wlY2#*_MpC#q82Jn$v}`W8NrBJLGr zT-JIkpht^+-H3kTL4iv)DgrKzgRI;YIvGBAwi~4!+?f8*zT>v!!Q`ZrN!@&inm-6mmV#pSaaSJ)!GF)3&Bw2BwiVp9b zd*3vw;||A-7vq%5ebU7KLJCEJHmz}9e_^MjNU{aCMK9f{##ad(93XMPRsKDcB7qoC zyJUHlXj@DidiP|1aB$s64Xms^5;KgqczH#D6ew?AbGj)M5ymu-~g12rTVJSphj2Zj! zzz$vQt3eE<|HMtlGbV4aeH_30X>;lC^Xj03sb6-Ho7oHZU}!44zdr6{{*O`)2P_WPIQ zF5X807)kmuXa9F7F-_`BM`Q-8oZ&|^-DE9)+sP}*Cws^nA+dmz_aVSSqS=ufIg7by zXwh?ZzKX{})K(4S@$`3hn(ko7d&xgz1zMiZMsaOv{(c-yO=`B!%NS`Q53HSntAA1f zQ)tpL`Ryy#!E?@Wh+8*{S#`@QxWQK72`Tz#M|XPQ^(lQH_EX9p(d$>7#e<;UHbG`v zP0N#7##XN`uVewF4Y&|NzjG0NJ76qk(=TY)vPRhgCr~o~0wJyBm{Dv*Qcc-={5Zz# z`?K7A1VJZif;%Ozs`e@M?g2LAEnU5S0>s$2aCm7$a|684IM}Ibl@a;Z>Hp?2s8deI z>ep5{5kS!78)5J!9c5{pKGS~Q9`8X_>l^4*X5POJisL$loEOC3?;_t5n@&6ovU~m z442OM2V>3U(PYI-{OV~bF1PA_4hg%XTaQ_w8XX=}?6ZzR2)Y1&XC@QWgL?NBjjxM@ z5E{?n5H7m)h1V3FyWdY$*u3>e(kTc2q3+k8Y% zSu;O^RtF?=%P2oEK20=%v@CiZC^Rw3r)lQUXr7Au%+B`52M zf89q9<`7yq(3YOQj~lNL^VCL*_J(C%;LLgt@Ofa>4S+CBp(AEReJtm(`-X*%ysezC zAKQy?<5#|iZp~EBr-+ob7*l%;g@W)I`V+EtO_b8cjOtZ!s{lZl&&`*oRGi#DZt(T2 z4Mw8)j8TTwB^7COcPB1Ux08d&pnSOINqT7|4~}FZZml2)7rK0;Os9B*Y&h$f6cS_i zc80O5_^rV|4A<|okBjQz$WD|l8}t3;M8X2xK1Yq~M{^t+t*g~3@@69a;suT}j$ z?9`|!@^*O}f?4k3z@xhbVpo_Imu?Wfu{*1zX{Tw}*dzWvjAz+uI=CSk;nraKZ@4PB z0!%OlvGLp3?b-g1zLu_7{Y7VX>L2zUQ-V%N!s@-ojfLjDH_AnSzt8>tzPc9Y6q`lJ zR!gGbm;=n3qLIe720(!`alpa9HJbd{pW@rAS)VJOnH~(h#-l+w{nL;xraFdYkvU! zuwTBwOJ-HI(&sNW$=d`}cDw}X8xsz0W9gSy86Ijbc#kqaKDH#Zr-Nvpo zg<5;;+-r(zHdO-3!58MLaDcZ2)lwiFTF2zQeD4=&eI77d z&kiLnxeN3KGra+*QmN7>jY&9dojtaaa1A~F^JGY#-bgL@KvV%SAq z#hRyPRRDtzV8M>3^rM!POA!mb(O$mIYJh@#U@U}V9B7K#0xMB4#aNRaRr|{7qEyj! zr-b$||1Hcecf?AL;%qzpqfK{u#x#-!^-Rlru~KC<_faqfCD*|>Ge8Roydc-}x9}cg zO3T0}=xB7ne;?owFW!Gm<=6>L+dI68BnP{zG2~%D%NO9X?Tw>cHYZB-E14;_qws(u zZ^0!v!jok*i7$mH=*y{a9|uh{8Q-FZ=f9=qZ>#}Z0=aj0&fl@1&kai6Td^i>1yA*Z zvfjP~4wT>k_{sIK2^)hADJ!g75Znou_XTN6f_ibp!a~z`w^`;Ky-R#@O^(l!_8txV z1NJXPA0a6|-~XP-4prVvJ=tzD-VZ!nSN5o6=Cv5@3s1Ek@M+Z9Ho0A`1nv?p0g^@k zo;NV%5gmEUdUI@H^8JZBF`b)v3M9>R@knE$?Hgm3S61}4HlJ?4R>MDD4H42niC=#^ z&6OGELN_&R0%{!=V?4b!sY2oIiL^p z)zS^#rk_mm^9}m_mV-nE*_bqd*zbHWokLqK(Jwyy1Q)RgPXUA!XBjVQsUTahDQVjy z1kvL8X2hMx3OGgL1Fq2$+`#Bh#5}~F;tN~p75~oyXgV-93#`754X~wVfK2%Xy#+rn z1u|iDN;LXIx|EXb`T>fP8DN43bSGR%f=&IF!9-96WE|5_1(%c(+DGMgH>5K!Ey!7w zEf!`k)-9Lc=*%_erI)fYHNb!CLmQ$ja+w;IEmHc@FJodtqmL&#+Q z7`E{?^;s;pg{@Q!q=blv3(iRzE*#ZLsl0kwd8IHcy62A{APc)`>7NQ+$ZJ|-e=m8z zX6Hyz@Uv7HTBpWG`WDbt9-v8DZs7b~;gTYni0KnDlTgy}IMspsGW&Iz`#Kldaf2FE z>7qSu|Df5Pt&(z)ELXNJiS9;l;;M04Yr;V_n;rf;t(*-)WvAxN1c=1EAl}RINd%b) z`Q8}c$*BjRc9kgv%$vU);F4c>MR=#6E*cFMbv~p-0jjNxl%M8#kaQ-NG2<1Olp7hS zB&vYfDB7mMG@GI;?)XqAP6N#b-8yB)6_WZkMsDtd)xDf^$a5l_8x|P0C$2&!i;+T(u0<0bFcx z?j_fVE6NrQ%$8-O5JTgp9!qiNrD9xCD4_UvN__GLzBJCw{Ezpy2eij7xxMoj079G@ z{EsB=tGd^J;jVOu$?Jg+?KWC9k|lSnz==T_=6yyte_U9;%%+^>j3Q``J21)KUG61| zCUX@p;Hm-#KaRLs*|fw_Xu^aOiVv&T9a`Zf4I>>SBWS%>%tDbNA}qxXUFRl) zTlJiDyEKW|r%{#1@uO;-3YLcn`hD>n{GW?keMCWMn5G!Im?!92jnxbBGMc>w+MZ9AC zamhQ!y;=VfSD{OQXu2M*;_LG!zJ?{?jPsloH4 ziG$`{cbQFs>laeEu43GWhco`|TTFB@%c#$fbRL@z>`7#6!{C6F^k1@zmtCJRKP!-5 zJc8EChbl+;)84*)dpzrSjOI&f+b-O*>P!~ub^@%X*qYX6mw;yv#>u~Tk3%`iGXFhp#9>$XEPZOS8sg(2ato>Rn()x4m zHulH!^zr4zCqJHqg+1s~OPYP5tkkMMl5R7~Q>}6LF3%aQUvGy@_X}FOf1ZiF9KfC?5oQ_0wx9Kt>BXs@ z@8O%DDXY6W@3;XKC+Slf?0>MH=?jKraIRG_@o@seL6A0m9CIY*h|Hq$bY+`E<6}m2 zm#hZcW!>Ts>zNR-v?*B7;r(2hiti@)&UyBS&_;dbz?7eIt3M9#HS8Xk@ z3&|8EjOo9@8KcR3@{}UEqjTb?w&6fn=UAeHN|rm`IfzX%X8;1u2?w& zH~CK3zH8s~IWbJIz8qIJKd5>YmeGXEEO?-|w9)`g8)5Dy}tprX=_ROwae zphr3a5_*kDZ=n-9C@LMKw*V?2MtUdoB8douUPBKMDWMZeD0fHC`;PbCF}^YG{e71| z)MRJvwdR`Zna?bH?R;8!oXeIZG0%5okF0Nlk;*h=JCbpnjf;Dmjg__QVIYh4O?Xzr ze%!WX*wV&c9AA~5Y8X4-(g+!cZoAAaVPjn@d)Gkr^xiqc+%EH(a;UN}TFXpy>utL1 z4P_?{6zIdo+XypNWm;)1uUCl2O}=x{f!pZ7a^0(*J$%j2{m8Q?8&sFF4;Ds(rhE-9 z5fR%>y!GqxhoQ+Ivl9<4)I#Yhir&iH%hAAyf=1wgtQrUjS^%LL^Go1z@mEZWa`IYX zO>}d#%N6t2yIK=QC*8wLA0|T^_FWd)HUi#sZCbu=PLz~zJy5AVjWfh1j_+Haydzik zpJ9}56_z0y9V^etg%Nd-fmR3?q@2uFzUaDEmm)taYs_;%fx@YZb^|N3OetYD$cblW z-X5LF3a@V1z9|sI3W`|OW9_t`G$HOdld+^Tt#^3)McZ3Rmb-%i z5dO7xH~GJtGA#$~W8HoD(T-`)PkL;2cJ~Twrf}#}>VqZF)WHtsDB`_uM0hx@4C~E$ z&r12=F@ciHv3>U_OMg`~kmP8PM3J5SD0{|5KGw@NyG}87oL%({vTiB1jUMzNA3bWGX&aElRzpsbC4;Xt zrgZf=hA6)#z9#k@2}&Kd)yQw3Lk@~zzcLvWab|-VBe0 z%Gzi$h2-pzzOBtqVriR17^kAShPbIsglB6;9`%!#I}JCuD}CAW6(!VF(jB4@qDKpJ z_a4VT@$ni<-KGple$J^*8JEeINWZ3hfjcbb?rhql(6vW`QHzL5;{P zwh&Fxvvu_8#>oZjjBYH;x|&C@^z#h?*1=T(Ip71Wobv3M){H-vqL1pGi^U@UrpTUg zlNU?2&hC(bL0&#aYcV0IkhbVoV!z&5Zl-~4(0`*xonoO?7}s3;)S`n^XaNEfV_>+n zTV!b}Hf0TltGiO!x%TVC!Ft#vt|l9@hwX|+w*VUj$Nt7xdzM_D8cPmp%zOC|jFysk zxNqxiC2hEld`C_h0@I>SHf=!F>C>-*dRnJvR$6dde6X#a>Bc$sxmLI$Gju$`y~Zb! z-yXM7lP#*DkVgS187TBjIQSjzE^2&*dpVA;3Qiu2AmwGQtHG-kI!MyJPy#mu0SFDao1W`1UTN$W3amiOikU2CJsc zmcmeuCvi_}@A)&1UM{S4u`HU#eAay|TN}3|(Wb-r&O^+VJ#ma8xOHNcyJpTwwIf9y zf_p%JA7W6}Ge?QbnI|7280E!j_L>$; z@EFM^CR%!(rcAlmUG3{X+`6{@X=ohYp^qhA6s>6N^)L;0yOvlxVIEiRy>VR$W1W^c zyaAxrN6RQFHMLBZvVSpZu}C;(`{?PJsl8C0Zo zG)pqYwE9O47gOSos)OjGsDnixwti7BUP#F7%K%i?KKWW$1HOyh(uuxXRL;)ei6fr62=+UOAP=}WSj<=hX;GHNA0&v*U-p74_G1i z3p@9fL^kL}j~y;$!nD<(sAOIWCQsdqT-+Ze2;KG#Rqs9e-Ui){P}W=^|48|(wF|K= z&NfY0%CmH4mvsz4!hr0iPurdcHRL5Ez%j3TCgY_KKZ)dc7ofN{cL+RlxYm)BW!`7I z_^>V|u42|;^Bj0y-<}oPXwKqGqTJTUHrZ7@9#&c^fCF4wW!kUosk@KOK#10TH49cu zvAX`-?84^D`eEQTS(i!lyab0?*CtON6ls(NHSrgx7_p zF``pumsxB4T^grZWO+v39^zQ!>^x-Y372L{7e#1`wX5b&pYERmCOMwb#a64L3zs<0 zsV~)JRC=@a>J{D@kE5g3GLC4Vigvdfm0-q_ar$R4(=c9G3<(pinVZTIX+B3ePZcr` zva-&T4Av7cvhQ;9r6QO=SFp5%9U{*%VRTG-wG^4H`U^(gBUU$NF`U)&pt7#g^s_ca z_VH@>AurQte)L2uz$9v{OUGRHQU}`1xP8`s3N*-m5@MJfUfid7Wkr<@ScneFqo=cX z!53#f3?~mfxP2oeDb=3oNF!ACb%!{UKsG(2#d+rZ-)TothDvm(XGJA%)OI|0{ z%#m%4d(Ce%<$!i3vGrAD@tg6sByd&&Bjw2gCS%&-1&BVR0j6iGbK&^X)z*7n?WFE{ zRnN4W0;BrX?IXX%0WH}~o14yfQuX+h;Uw=KajP{IT_(RIKbyKue+ha)+MB_}l*Cr) zEQp5n6Sn!@6*naMIJsQKMIT=PXQs6s>)DQ@-#$xvJOF^XNSpn*)dC8{xQUi)rG^n@ zI`6>v?Z+!BqKfO`A>mcLfR?JIsR2IA{3);vj`Fbaqc^++v)q&BA`JfUY59vRWM{q` zSpf(o%bM-W#7*(|C8v+5j|}56Zfs>zffw#kWySjeOCV~~ z5;B$t8^giIFpK>qY_F?2T&S8|(9?)p&~%SfPPaSp-XsV10d$Q8>p|TuO#Z&XiGAfm z9-?zXy?~L!XTf8|Citwx%(Qbct2~7YidoIGbfDMim`A=2W&n5(2a}d`z3UWBTKtl8 zHuj%roe-{R#2rJ~!CvQ8*$1k1B;t4=5bMu5Z`sH!aou%JnH-Anphq)#9Lxtz^F32A zjt3CL_e)Sb_+n#s^ln)FdIq5D%ZanF?xU#^T{eV z(OZ0EcYU85SH-$}G=)PtOPGL=P~e8P6k)uqAW>i$zU&ok-}4|~3ngst!K8|Rlq*|dlf#9WNv$akUUU`YJo2*@~DO%n0ZEn#L%K zK7S1{ky@4W_LR37bRprrH)+k#S&WWIin|31FzUv)T_)A%;f)R6_LppL+Iy;PsbCsj z_T-2UA<*+=-Q{+6@zd#^&j-`4`K|O^wMlUOqkKQCSm#4q3#Ja+W1Sm=@scSTQhe#F zzLH_rx2~%POKl!EEmc7)r{)hVcuGtNo7#ozIhjkw|2G`n}@AkQJMp zk@Ca`;^;?*4WA&ySA)V`GXjhUm!-JsF58;;y%Bd%QN;4NbCnc?FbDyWj<&CyP032t zo|S!S_(h4iMcv4uDam(T=5h_L8#T9Tu~R9%Zp7PB>rm37I|FW*y~*aiUHVP8$Cro& z6+K|Ycu14i+KDWM8a@pJ( zi2*cd8IZ#Q`Qt;2iCfT1wLMLV9-hQKWP!AsYUSGWud7BWIt=5Vfevhf~&Sv;r1tBfIkto-(vk6%41YT5j14 zn^rrbhp6QM=YK6xVyqT>_{>`1V^K-r%~&&+3xsDK^$K~hNptZvL-Na|uC{b#7@Zyl zAP@uS;_z6jl)Mn8?H=GJRfe3p2CZ_BVv8{4S(`<&C~qz%+v21-xaMY>pcsy!H4wq* zq6Z}|4~Q>sB8`?@yHsieC0Bgd8?AHC{KU~767+}abJVcXjg`e!UfcwoDvFDCc+O_? za6~h<`(D9wjhO%**BfOFSY{Yz8c}WeX47H8?Pf$It<0eQvG`H^;`k!EbjbhLC`EPP za}H_rccV9MB4wC4{jlvSw?JM(|BE+Vq@|-jWE4t}`=HKXKj=j9MG%`qCikn%E)RoD zj8*=&+mlr{cS#g|nIJq43mswduT%2iR~0puS{2mFml&D51se*Qi=qq)KV z&8FDSNf7JcI7vWm+Q>Mqw!2#$S(4~Rhj?c#Db9$#R;gKW=}>Y1SWzABI}N*_u-W_3 z^F_PUR!Zm^CRNluE)JhJne_}qORZO0l>xpf3Q#*e_u8}Th0}&_+*VyvWj}bTfHJcm zHTS_LU@ORXI*Fp^5nT=R=8}V*8X2X^86)|br$^FIH;}`Qrdfez@2Pkq+&ADlvKOI& zbG=ES2Iw(mQ*Kbky|vevS{I!2ed1I`YOw>1(4Mei6}FXUy` zru0DDwhhcdhz6?*C0q=O*`8jB$i(1@(cxqO=dNm;iO#Wbz3l4Y&50`kg2bFmi3+*4 zF$K1L%T}UjvgM0h7lPdny?+{}x{ntBszK3Fiwdi4>DGAWw(w+GGHuDY!yYyM*w6qZ ziX6rdZF(L)Lov_fJ&-N7T@~H9H1`iDZf)XH5qjw`V;P;GFH|=n%{<-fIGv7j&1kc4 zrA*7Ho3NP5!bq8aH@gqwWBmw>sjgWV{HBupaCs`d(SPfDCTYGJ`4kD#)Qc(JCkeml z1o%hyPL8^C=}+sfyg^Ufn5LkKnQitKyA(_lDnGaf*HB50eW1R3XMe{|_OfM=!YG2t zGGK$L@mVboL_=|TEq%W1reWccUtaQc2q9M4+pV#Ufl<>|WPbObmkh4FTUkk!M{&}1 z1=D@ota#E&Ib4SN+rp!cnxk{B7Kz-IJJdW=015fH0SvM|qRRR+er;ask5 z%CJyge#fm}ZP1+xZwTF~rQ94k_-=qB#yiDf+-7Z+VRtCK(PP0D&?-y7{%j8h$PQ|f zBA&k@7_rEey9HPP|H;PR?=p!)G$qApygXWB1LFyRY{ZJKErZn1M+)AYws)u-RvGrA zgqy!F(jU`s-TJHxA1CW-bqR^Vi#&CIbgXn*d3W>jp!J>Zg_E_de~94y$ijF4qV@o; zPPg@RE+?$v@M_?SbKvQ{mLC@1qocy=ofH9<6=?b=?1Om?y^OlpLe^YD5|c)s@-HD8 zT=1o<7h0foLv#9~$VXvuDr=xO${G4#q{~H3sA2Gr=VyL?hk5{Q`zzr7p)ChABaBm} zWO_Jjp+?tK2(^uu7<<0CFPE7f(EBo*;grqHTW?TU^>i=xxS;3o0=j+vowp8Y1WUbR zyO24-en2kdB)JqON(^#s_CKPrl}q$EJR!$QlVcHLShn5u0#y_b>j01y$QT^{-X*Rj z+w-a@%l|4)-ktWG^6(b&D&Q4@6Qi|%u91jU-~1k69SpBGUh^5WxQ<0eh^7BQvo-<%AC9)LFXQ)nwTx$bA z&$w~ePo(7}cr{yZt$Ai}94|~Zr$7isD`r#IPZSH>21%9%fT^yPrWsq&&|2a2bzizI zyzA&kh<$&k!QMkVF4d3qZ1%Ks5DoW!BW| z-OP2q<=g0aPCOi-i|gEITlc$T1FiZ{eXqM7J$#dg$y|i^T z+6_92vvKeECb}M{iW>h3to>z9%n#9=ZHNRqkZs!A$vu7~zG2_Ct|z8@>hR#%##|si zU`%MjH;af$6iP{} zB=fnlmDI*WjkSrU@iJOMoGau(0E_fxP<+|t0jl;VGlH6$h0(|^r`Y7BGl@4PPj=eh zRR?X=z#Gg@r?O&FUY!!0qgTd$`(6hH(S1JVw8JmkV`yqRrgZ6}k9KX^9iVr#s3uHF z6wK#X`BVcEeKCi5qoz9{R{4G(X|-3xC_^Y+&+Z>4N;`&(kU|E4BETEoNPB8%jh{#e z#a2>dzsy7YMdpPRCo=#Uiv7;MsLEVm)I7pGxm?%L$u?b6LH(&Z|Fu`poB~%=j|5#o zW|!(Q;414wo76_1AkRf8<1WEha8p|m(>+b@5vM$D{jbIv252hy#w-~f(3tmkCToHG z<$Z(Mw1b7~l6*`nHN1dfzi;rzbfpd8(BO+EuX&|oc*Rl^t8z~$GO3pBB~n!^Nt;^< z@E9^fOEXhtA(b}k-nQ@Voj)G7mM=63asK$*wMw}QTiN1#*$%LZeSdz?0$S)j$jnOAU$m)Qqj+>DaC0Y0OS>}Z^?<)lSpACuL@?3 zWtYy~^^@f0C4%VqIy!PMs!mh<+6V7Pvas%#%w=Q}*Qju`aA^*oJnlbmDr1HI1nDEF zr6qK{z7<@?cs`G8DfG7!^BeW?BRFZ+bRj&^mtx7XFFc<655eeC;_lqD2}qX&+f+1J zy*{`O#k?4F>&zF&x`@`%*6~XxdWiKUk}X4;EKRNZlYhFqOKbciP;Er=T%i@;V<@Ta zT*6EtIJ1`J4Ft+q*qL%v5&$(;6J2ho4C#{g?7bNDUf4krGF21Wn=z!u?g#h}I=>ip zp;*(l8PqyiqDQpTBkU}vjcfkKdr$-5y100gyAT*{Gu$3;C7hU~vxp?R&}3TxY>#`% ztYYS1cBsvTN$NVM6qk=%;mmTCAa?VL91i^g6?JHG`bNNFzi2yfc^%ce=;MZ#T!~a9 zGywa1IRQ#vV%=)-oN8We)53=o0(KZ31|7Vh&*TQyR$5BHuwm^J0V~j*p$e3rv zQH_Fp6=ncn_Syn5=N6fGoe;_%37TJ?<5uWo58G}2(`<>);KxqEJj`ty#|HVoB`|1bQg^B#Q}y{X>eO%g%l|Dc;j*jl^?yU?>%u$k{)z` zT%IR+;qgnSx+v%>>N33Zh#>&obIV1w?FzLEIWrWSF-7*Q@DAn_;N*jUec^KCMA7EJ zXy<(9`p9dgi~8=(Hh%7AR+Z9>w*evsVpU5F0n0XxWrX6haz!{^J1Y6js zrJmIb+nOE?1KIP7pSy7dA zB3^yXG#Pe$zGwu*HFG3AeAvp;x*~dLE@$s`v2eM-5MflsQY{}_c|NAm(_U1r+c`#$3tTFai->K(#G;Pf}lnlC@~m8fc^Yz zN=*H=XLAC+o+9lT=ZRS+MUXtY{APop8PNLj;ko_RxT$*?@e91*jfz=LV0-5R!8e1; zQ98(f!T|P|a$3_NE@Dt4}T&E4yHv`2S=bDKzG`dwU%GNs=Fb3I-W$&h)LbPP{E7f)!9X5 zzZ7WZ_9t017ZG{l_i~@$>}2R4YfVS3m-ir=uPW?y*y}!x+5OuEs5w!i!#*J6`pDLq zr&Cu+i0ApN9KEZwFba$DSc`gm*sdFi$$6|lACw(Lk>ZzjKXzw+iQ%N8Af{4? zT&M)d%`yY=RD&V=<|eix9uyEsKQ^_IAErme}|iGW=9$>;_!1Of`^jVV;V zGYytLK2gBQb9eBi{Aqt^-2tgQQPovfG)cXX$ZKlptdP*+ivN&>tNN@x6w+FmVd z$@Z+$OHC7e@@svEUx3WRy{Yx%0sXuW=`{Qm(qZ-ZK#$GEm(ZCxZV2iqe90%zW!MGZ zedvF6^ysx}7!U1jAo>P09z!5WAEGWKHz2>dsV2p2uf77d66efMQsfDOw&?>)|{`@*rmCJxf3)spT^xPIkIC z!wXNUapRCL%d1B91K^Q)zHUkS{Fs)_?!y>voVs9BltyT1N)#`7yv?IWwteESU8tRQ zPB|-J_(Ul77&*j!HY~mRADZ;+HU)nISzP+m z=5I(Wx@aMeLpQJ>;+5=a@u#)brddlrQ<3=uaNxAt3u3Bq+Qf(|s{hwu?TM(I2X&1j z%7A-FF0X0H9pM;~?KfQQ@cQ)b;mf}J=i}>=jh%C{l9qe%iH9WevhLdHS}SW5XQ+_T z3j`3U0Af%9&1JEY6iCaM3it>(2v=qp^`@lOghR%Lt~L|@B?jTsO@o-KLU(aFQ!vwEdD%Fqimcw87yP$><^S7 zNey}ITiNb_!Y;x(y4)PW$juFw-Pa^4GAJA=R`E#y15h-98RruYWJnuq<){RxGSLBW zsv|L0J1?!C-RF&Y>pOmr<5EMjrJzqGKsLagrxRq40F@?BrnoQN;_<#%9Q6dwReiqG zo$RN92P-HzRIgsgNDew109>HlrV*XR---jYZd7_T^}uC^jnr{`@kT`f;5G6B1q4Xg zw#eLUuaB}oZ%5$0mIiSwJpqU|1Dr^Nzk*EbOi_9MilS*ted_AP8zU!7$*VN9>L1e7 zoAe>!3ga_07PY()6_jxg%)%ejkc4gAtxu%C88PM=M>g1a=`iUYrA+tb`jL7SAp_3| zHsF5gKpK(5^-BkqoXul-tGikFyrn)WOYF@LTA3qyrl(wwdcor7W2>*|FIhCNUu~-6 z-8apTimnrsYENRZ3W|0(uxz@`{7f5cr4}%JmYYi`B?z+87LbCzK#HelN?Nk#6Yo`N z;gTRvarsS_{WbuMq7r`3Sr%2%G3||2spa3k6?Wk~(j#c{FoO0=Le=->Ie38(Jw>O0 z$meLbU;UBp+ltzn<>Oz@dj+Kp=V+Km3JO+4ahEqK`%&{A_`Z zz8}$N)ID<^w`qYY&55lNh^Mvb%}73Kr*AHkU3E_t1k2gt&{@;ksST+bmxs=4rJ!3B z*hcrW%!%_4>XpG~Lkj@NoaPt;FIXYW0hXMlC;0OQMYdYUUy)Q{;n;S*m8d57eS=-& zd^~q8OLwu!+F4wslf9h7dGeY8G1UgdqfKx1)ds%wIYXKE$Iei|uBiP`&sv{C?B1Pgi==!n z2rWrBWAZ}e=LLJwoUAgdc(oQuqF$it^YH<&H;;8v$+U*Sp4VEU-=$}=!3}@%8^EJM zy9r5!f)v$ftYD{8rAaw>>}1PiaP^w_AVJk$o5uP%&k?;M2ySX*F;Y*{&Z!%TCw}$2 zuI~rVojSlTC<^)wlxPL*B#I`+K4ZTYCrh}?a(;-iEX7rH3t&HnQb#s1$NL?QqvUGV zpe@8{kL)=1Hk}nRQy*cv8rVlLd890O)h$h=FovVYy&B^G0oT4B1zLL-AsYTsSOq{x z1K>}p(2n4gBmVTJ9%J!G01yBR((V|gngYOl-q}K$BYao^o6NZt`z_TdNHX~qyvh_l zrsk}kraBr$C96ZL0$f&I-O1j)uMdG-ylL<3a6SmRmiX6Gf4rWF0m9;$cJC}*-kHN1 zHAty^{`u3jLa&C;%&hczPE-T8Zr+S|Pb(wbpGq4~$R`NmIeUb`K5jX|ZD5|8H#jG5 zh#_>G6CP|3n7*9+-IYz+PWIHyK$RlNDPd)0<>&4xE0Rd0(7vw6%jkaFnkMrkcsHlC zI##0l4saC?h=l>OF$Rry!LYGxKixl1eF4eZ-EVTbdGqFkNnRo!DzKf}xVc$kogaOw zZ4c^p7uL<-6Df%h;b3++k5R>g?<;<=P}jcHiJ51i(*0P78#O<+uIieg@87ABKD@m8NzOZ+qlPlbzS{cF8f% zZ~?UTIE8r0$bQ0myoFYijfoC81lDx;jDuRcrFMi`Cz8$RmRO2=w;m6h{BqrUJH=0< zf<>L9E_ryzE7}`V{{# z`9Zz>BOKqRO8-f&m(m-e;<4kis1N)tP^c1!qt>)xgi$t|6Bv<qr7^-kM0etm6J^)9af_&VjXJB2QA}4!)GIBij&$F(zoqzy`z8j)PD@n z#z(lsuV~Sy&9-kN5ZdUhBWuO!-A5`DodS&}rB% z+N4rUc*VWpeHTz$`r=;qjc8Fs|JPy2=UngIqB^W|xN1tMXJ@2)6X*-ghZEHPjeTzg zBXE;tBH@pTV8!$HAUM$;9=C9fbX{sY`(0B{33Ek57fE7&s7U82~V$fqnD zTb#Ytsi#@_{YFj6$#ZMOK_kcj(az@#7YP;M>e430rA!7NF69Y-4_tq*diJw&VTvU` zsOdUwsL_(@PKS)(0EGx6>yKTxPHn-Z*lGv!!lkKu1lWBgm~|~(b*AlF+|Hxw%vJW8 zP_AIEw@3f5ST&tkcOXGdO%nGtbj=3eFh92-Kw;1H-=t&>m)(Q^w#n|+g{QTpc`bR% z|J@&N%zp2W7=hJ;kCS~H5(0j?60>iQg8F~pij4)OqKao#Fa|CT;tt{?B`gPo5!f8J z*R~!W3pxjP`&lGOhdBDetg@=tYaMbZX-(2-1ni$XoVPJ^85K;neAl4=g)f*qXv}W0 z>aOI$V?N^gKjPAbx>Nj2@xE*&yBft9^KOJ_00Oa= z9h7CAfQ!|rP~4AoxqkHL{QWH8+r9U9*;C3ecWcmPUb=p!@MaLPVNecjaJaU%cdWJ; z86G}tu<)#E6+V@kRM%|Eu3Zo=lRDX=61WH+$I(#m5sZVR(}GOl%F6i<{fhz5@gw>-cyYbT$D<@#)psf1m6)<^iFr4Bt zFTW1_1hkYKl?#eq;&h2NNpp^^m=fx~t$FF5%|A$?aup99B8?Uvobfb?eo6IU(f%#A zJX`o}F>gzgLA|9K!upLS(sV7a7i2nxN|QS;q{E&4aA~lx{7N9cC~Rs0wxufmOVzml zR+7{MEqRtb`bzhuBomusgnOw5r4;w8CbEfThwgCW{6GdPCVN?j^AR0ls(xzlO_t?1 zazFfzy5Gm-kNde*<$rzu?l$IXa!O%U3zo6sPStwe`(9Pom?Y1Cwe9_pxptkC^!luy zeO};%O8NJECX9wU)xfvC!UTnaQSi3H=Pv{>2{}74dgBzS>KsP7#)8ow6Q3GL!#!!e zMk{8&1q!G*S<~Ypmx;L#(;_o`3oFUNSe#okbLSb4N!{lGnUZFNy*ZglM znbg39Fs4P)h95SppVr4KPG4yrZh6;zC8E;sUUH3ULIDAsJ{i0u0U(+}d-wS|AK}Qz z=}1WuMHa)c{`h^ds1uV#GtJwHSqrppbx^9qfkN11%%sNIam*Ct)n;3w0zJlIjW=Mo z-5W2ElFxf!tb46H3s5gKXzjK?qu%;Rl8!pe4evpr1R!#YY1T+lE{%*srhn4zeC>uw)y*o7C|1LYjq5_Rg%zUDe{BKz#kK4b7)4 ztE;V@5`5=YWZ?1?3!51`ipzKVdWw364^EhD30K*>zr>h0Y#Y$jmu#`>n6m354QkMC zP*r;c9Z*xNo^IYb=hxRn6q!%mYk5`v9brz}zFw=p={@%RzVmtE=~y!m*arljFkpvE zW0%9O`7%>9%qB!@sObQ`q^Bq}s5&JqIV3l{__k-G-w-+-SlY6JTjl8Kw3wP$a6p;s z(~dlTyrcMSSQFnOL-ID1EN%LZ0O^-o^CW}6HM+a$MwaU~?Moorojj73-Wv&QoW8*O zr=RYIl6G&3Qd^uP-PXrWD&8PJKe!*GNLpllhx6V- zQ<2B=7RHbXwf}CVDACu(F%EPSPk(+*byzE1YKnf<(lv8`o>8Z$=ha$gU@X7BZS@kF zQOV$0>@JMH$|(yPMG^t%SIxfL8WPVj{zL@wEHijpYFD9gW$Jf(Qo@dWm(1^ zU-2zY@yU}LKI<6EC9o7xR|lu-_inR|L`b{k9f%k|mE&SqVx&{JHG8`qc?0@iye^)d z%}AfrC_|}^!o78jho}aC2XNw-ZxhsG{C7GoydhlYUf0uwOt=GLET31)_v6<$E*)P> zCM%XdN3`Q|e_7}_WUigg0A={>@MUJ1B~8ELw1JpNLT1$^Ce+A4P@?yXw7jpVax>?^ z5o%G`4Duv6wDC@IyZdff%e#97{SCKAOG)2a%1l36$y&^Imk}jb4m7iQBRq1^sKNDN zNZyNH3g)H=QcwCHv2{|DE`tJ*W@QE*Cs&*11X8OW9t0rL66#xNDtbqddiG5pDYA^a zsf_j04n%s^1`QJ&Y*~Asp_Eyhml3u9Y8RQ5fz2N$r1sAH+;;W zd9lf9??4lH0*N}FFvtD4Mhc7=i{z)P!Z;(!cP-3$Yo3=MFX%#AZbz}L2VJXhu8zjU zRrY+<^>18kF^8DH_69;H(trX7a~GS&Mb^DvWj{3!TT!HiYGtc=tSWGPI}iZ`qDF~{ zWjJc0lrqqP6GV&k2+Goqomk@x9lmE(JWM}Eg0}mDo2NvUwrv}P+`E&ppusYuko-u;&M~&#Ek(DI17Al>&Y5OoH`}6Z0Va%LZ zlD>(OK%E@kGF~y_Ui)^ih8g*zrkSu;{U0ypZ(-k4l0;8v&iU{8wY;SBel=QKe9jB zbv(ct1Mi=}%|$F2!2DP|pH^Aq+tAsV)n-w*~T5l=6+;O?UEo%F4ywNK}lz>(-DL z&@(vm7$TM%Lf1~lc2l_lRwMEgn+u4w@H91-Fe`;`8GILetKgIql-1sM^a>YV)~#=1 z!{#_zhtbPr8GG6S<_Mg6v=dZx&>R8yk$gX1fxi?^eE0}{AG%(p=0DHu~Iz;g%20Hz%8yh$&My5RV=xtHTTQ+=D2lvcJ;K}hRrrQq$6nvO5-jT zx|7T9M*Z$fOY$YD4+*|gDCJ7Kw^&2Ge2~MrzYZySV}M|xx(|OIFXU;eoSSuE$>*^p zHi?=y57N7u1K83_VC)NG>2tt^RPDEH91u9(q03~ge&{uG z4bxq&%PQNmW06vL%S0E4{ffpolcP`9KJv9@-$3#m{z%(-Z$Bt*ZbmK@7dusp9t)4HFG!zv>S7lU#0I; zYGT2V_h>OVJN4M9FIe`6YrLa%-fOvox zB?_o2Jk=#w4mwu=lSa_wJscA}sGGdozCLBV0ME}hUU;Zy&QIj{Rr7A*>PVx0cThOi z2R^nvU^jfmiz4|iv)_QoUY>q6OqnOJM%gV0UQ_ZAje43|nC}#!+`v3G5;V(OFjZbF8e)&PCyaZk|#C-VDC@;Y;O)w(aukE&f@gPBewKF&S zG5~vB+HVSCe|l*QrT!g13OGB1jn~2^+GZl+UY+Nh`$$=U1Q0q-O`!d&M?HV(D1ETz zb$<52JwNaljH_4$_3Cz zmtXiCz}v}`;Wdo^dP#NWh_UvE1hc15lEG7r1xkE@#-W?>5;28!mrv4dFuyzUob#So z3CQ{(T!#fHS=(#`0`7^_&)8|Dp&Lc&vcNe%)}uv6UT}4G21- zWl2MWJb>rJRZ$OUxuLUnED>WehjXEBw*(XJiu$9U76X#K)u6(YD#2}9y7fai-h^;ijrc4$amcQaJd%Pl{kkQ%S z-=F(LYtSuxIFwe#>qefs2LjhYS|f{}*LA|0ebl7wM+xBG{#Xg@%?R~M=EUCnwZNi$ zSEk4&AF_i^--tif2Ec)|Kn~n(Lr)^9yuv+X0e1&ja8d(B0jU`kw_^@)Uf?4?qM$*X zTqxl301v)=VwR!G+k!~HqgTu4WT&byKdX4ED17l7r}k}%F9VaoaH(tE+y@x|!33Jh z>BBa(U(B| zR6$`9DChx3aVew$yqlPF!oDJ;kYUb~T+g<07YL^To$BPe?`nwclnw#&Qem?n^&T#A zQ$Nu!F`WRCF25%LRIfS=7tufap9_G;)PW({*GHw0{sA6bto zTm&9B__x`+b8s0o1A4P|FDzW_1`v%QwfN;77?~DNvLAbDw^=0+hh<-gzdJ4`2wMpb zayJ-sQ}G1BhuPecff)1P_`<(J9h^HB33473{&Vwil>o7;T2Ur7194Yor1ney{j}AFV(%=2}az2s!Or|9tRL0%%+v$FLGgX5yA>y z=sAo!6V_Ch;{4w)dtlH@4O}c`r~x7VKcC0z=RJ_-clce^5H)*=h?8yN5Byuucv}jS zsB8L12CTHQ`*Zf%aT`__n+@Er!cIA}Uz-2(0APuvrt&;#&R&lj-7(%!5L?cbj6HeF z3hY8si%+u)*QdO1h$CuxZuyH6xOaBY)5zC_4eRjwtAGjl-O69kWZy~3Y@>}f>NNLA zn^@rk-s1Y78?yis_|S30{o{^*Z*-C5=C}X(ifX_?_)jhO5x=G_-1<5vqq)eGv(~8S z<3G2*84>2URh70UFcX^^3}))dYAG@JZ_k22&wWQgrTAp>L2bcYdAfbtzq+7O*ngw= zj>zwF&rTH6;80(>$47?1|-zFyc2PR1?ngRO*Sfoj7X#U1Z()ID2f1(P%h5Y|YJ^z2zz3n?K z(}3+xE}T2!fa_-T_m|7CdyE8R=usDcT!kZXBd;UgE)N9nGYdLeg0eG({Smy_``C6a zcf^#bs6TNV#gd~SLmP#fOEXxZa=v*m_v=g%t$fj!TF9otxM9BUJq&^}?$j2To<2Qr zgP&gN+sOQgF(xHoej^tNyW-h>{+^`V{zwrip%Aaj^KZhGBKZ}uS!hDXvAt0Dp7w_S z9~F)FP8h#Yyh3^4E^Djy-+U%X_khMzsQ!k_?h=<%`cQD^D$m%n{82y3Zul+r{3W#} zeFu}D$vR&RFKMX${cm5Rv=cXq+u8pKy7XYfTs)cCz^^&wxUg7So>m2z1(+}rJ{#C8vt|W&r z?#_6=YxmU=OFYTiPUfH0_BkGWlTHHC4|uvilegCe#Li>(_G(kEK4MX&8i;)|e(7l5aK&a5kRL^iqf7`*v=1zP^$bacB(N!)V>s?Q8`M5>~SN|iGylF8Y zX`)pB!R1fRaL-;;{jp31SurPtl0NnZPOcsZ7?4^qr@KQ^R zZQ@yuBPY>}Vm9=DckP=igcVbLC_4K)^!ddLt~5IOTZqnRBZRY{r}-bfUelaCwhqudHa9k&aTWYw5l$0~h<4 zJT_t)pHStItiI{d;O+!`^CWYK+gOxq$)I!*(czGsWqFsIJn)3?wAXPz(Kt#thkugv zE~T7>o!c_=?9I0S%(|QTKsF6QW5s_7^r%rfp7!|k?V6`oj7}2t>^*=>x7Z6V%OK{u ze|c{lh>q>s@srCM>mEnS^~ux@1oB(%9svh|T}ZS1X+V1Q!-YEZ61TB*GAK>Im=^I_ z3;1NNGC(&37a0=yH|dDXvJBu*M&J~zFgoCTtqT`?>iD^h;ZkDCt0485j7eNq2iDDh z-b)q*!sQ*Cee)8u3tW5XX>v*C(**B7N=3gK?t~Zxw&bp;XsKE{FyU_V z0w=azm~%)CR9xf9<^E^BPgj~Byf&Hsxq7FbcTYzA_xZ*F8K^+T!dnmFR~{;H5tU^# zw<F?Pl*WgGP6Jb z=I4O%1A;1@{e1QJExoIgQ4*ciko!=wAK*I&R z6cXs(Rj1|i?O#0$j6VXAKu!w@dUK?EyhPrdu7VJ zn%LCgu{t8vJhrxfDmX=d7Jbl3v@I%A-S>3@p9TRxY)!aTEHPKs;H{w*T%ExyX`!aY zgD*@X=r~qF`JnwCrMb9w+(G;+x~MvL=XaK+_fAdFz>9f+!h2h_5Uxk68X8}eIV*}2 z=i}R3s)fyjkC+1?S`_z_^b3cP(-jHu{gZ)%e4GUEgY^myMP5@cx8&Q2+aMuprH@P0 zeZ|VoMcdb4qXe6Lqy4n)=As}{*K=j;tsb=@-+w3onOF{kU=FXAe9LON;6mLDQ1_#T z%VzwW-M2SMn_&?~y|r%m?u9Y_Mdsgev4Yq67{_J!={>BM$`wJzjy_zq>WV&?AOV@zfK-3PhjdRuKuu_?iT%jjjb~4xR>kH=(knz zVS7OLR7@zgI&eAYOU1FTOW$5J{Nl6fe9vo-uYhDy>(?ke#1|e3b~~62Gw`|e-(iI9r}#GqtU^|P2`&h;E2`Ue^H{s`Nw}h zErYirbMn}IPt_fZLp>7ln*-aq{I`|rO(o$GbE zyRV#EcrE_C?bklg#lSDpS6l>OGGi8%D# z?l`_2big{p9Q6a6Bi2e3W?Fy$J@a+c)@}Ez-_0}x6>pi4+$ML9Yu;op)0B66f}XB? z3<|nBp$C>PS00?OyiXd)`{CIIJg$`Cz+q0%l?@Cwa~MFz!nrZqPJFt4{rb5=kfgy2 y_lD;C_Ketv$vo&@)W7yth+2T5Q6`M36y@BGuN_ioAp$$7f^xvX - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + diff --git a/DOCS/html/stm32f4xx__matlab__gpio_8h__incl.md5 b/DOCS/html/stm32f4xx__matlab__gpio_8h__incl.md5 index 3b60885..c0d2420 100644 --- a/DOCS/html/stm32f4xx__matlab__gpio_8h__incl.md5 +++ b/DOCS/html/stm32f4xx__matlab__gpio_8h__incl.md5 @@ -1 +1 @@ -9506a5279a94bc6aab880d8b248bbd69 \ No newline at end of file +5e58ad6b0c81ef0fbcb46d6dc1d943e4 \ No newline at end of file diff --git a/DOCS/html/stm32f4xx__matlab__gpio_8h__incl.png b/DOCS/html/stm32f4xx__matlab__gpio_8h__incl.png index 546c38071edbad7782650bf7408eddb2fc03ed4c..1733de019254948fbd8dffa1dfee484761667fde 100644 GIT binary patch literal 26311 zcmZ^K1yt10*DWDkA}OUHT?$A_C`xxXDBV4DDxfsd-3$&fbk~Ri0@BC;f`BwbBMtH{ z{@3@tx4!q@axGnq!!PdL=bXLwIX6;WRgMUs1|JO#jYvWMl_nY*h7uYYdI&By_@u*+ zbp!l^ZLTEu3hn0hPku*f5*pe=G=*0$w0*L-=Y0c=b*^s?kn5`Bl+_&9n&=;y)UC)Y zNi98I&JGt_y?=<$<7AzPVR#Tdz-p^cp?=0>_8FRC$5EK@7Pq8d*@%!=o3JKnYAiLTFiAgC>3_|2ZaU=IO`0K`;fgN_MQ*ASfS5vO$h$F zd4sBKvYxHCgIiEr;J?1UI2J#h^8i0+9f%{*|J`UHgF@-w{qF16Sl)h;6#D=DV0sdr z)rEkPoBH51nv!Q=EAUZ=Gk7G?Ysm?|+Ws2bvBLHd3+_JNh=TQ`&9fQPWltp5uNI-1 zTnDIy^=ubkZ!#uV>i2Z=Lul&GP$xCMM!wao9=z9&$el-3w)Nx-L1_(T{N{uOh_%SQ~Fo<&On1?3`MN26grgTR(UNF|hJ) zugTRbXnRpNb1L7HM*-J*5%G9OHo1^@wt2t--x68RjKr-O_~hA|DeWttryUh*x4F9ideS229Dw-_lZDX}_V z=}%J26mrT$u~Q5|P$_)xrmD|co3}eh;Xj=1c7kwE%b?i+NYp$KmatTb$o; zzSm9GwEkxE@M5t`AaJcHR(R0s;h8>846TK7fx%#+oB0M2Us{%h&>ro@tZ`k;pHB0+ zPXs@X({_qZTa5S2y_BrmT=YzedZ`8OxzQt%<5N>pSCiP(B<*hFxaj|gzbD`yd{V}6JhMY(@p4__=_FZp{4CFoWQyK2Ql@B&+J=3W0ss6)PF6yCR+8{R)2 zmQCEDv3*pTClv6Y#hG?f@DY8LzPsqU^saCk(yDd$bzTi0^a3nF6w|zl%?1X%sKcxN z+R|@maZlC=m#UW5OnXb=k=(QOfKv_mll!z5_Tk{-QNpto<4{-QhW2S2#~8PMu;rR9 zzorM?Y(_g8`9(B^S^7D#wqzf@#Ul87J+g0MCAKENM{DOVxh){nt4#~gDYInW5)}}i zX4kI7`m!xVcI%{nQbim05l`H+>FX4wCOv4LhXHCx(!ybhA8H5?9A#bnqVarAy|#nH zNdE1L-C%dmU*I4qWT$|VJ)0L%wm0_+8ynv-gwLElgHHS{GXSpEN_*!HB z-I@!;cU0kAugi+ZOIooLwt12Kf=b5CID-lYzWSd$NM2aLFX8c^0R_RJ-rn@X*E~v4 zCd&)#yg_4$7KXaJm;HLYm6SaI4LvQ$-{93@gdkNE%AY#5Q41G-j1#O^vfbz+$gtRm zg`CAoPBcp2_xsf%u8}%)8PO?}wM=poSny*D{2m9%Z?O=L2RuAHgKTQK0ps;{6UK62 zV-Xj}DBs&k!z4 z9(eK&Is!VDsUwa!ochOQ>$5_Ove#Eq=WGIU%5-syb(SVjWiWK8>sR5 z_5`(-@$Kf^-;Bsb4Yg;x5EnJr#*}0^o}DTJ}Q_auXKlEsB|$R7Fo{zh260&)<; z=M12xSUBE!e|_BkcNs%(-AK~>NMOsMa zyS#z2hHqGs+zDFd=F%hB~Y!c?CPhYGzssFl%P>x%z9cR;5*d^TKh{x zP?Eo^dW`&Cm~EIoP7wzJ8KfI1`#1$n54SZxBx5z}(ZXB1dZ+Mo>xUER8J;|^&W&#h zW+JF+G8!ocMvuOi$PcdtzBDuX!2P8uzA=8Osyx}*-oie%nfUd9oRZSuVSf@^-czU9 zr$~($81Cxd;@SU+F31;vq|}P6q4ZhH+fRxh>9JcPz+0Sc}yYY8gJ_JvO@Ybf)U}={dZ}(rNum z)9I<$+N03i@*ucNRaN@UsOL`!Hk8~t19PzHb(pyKP4rocM}I7zg-v`CjlkPfXQGSl zO2on|5%?qak(S}7+D2J^DB?H1`SGGVa)Uu3mO84&~cft@-AM^-{GvS2EgEV2nfPvbRsz zp~Jzz>lx4U_jg3Fr`LH3%&k3*#kBt3BkGUrXTD^*(h2yz)cjX$u2Qab*gA$o(!qeA zwdCA6hke-qgO0$MoTy(1E)dH+S4nU;2+c7n!jb^#dq^7RfZME>;$ac%UWpQKiSpcJ z?Ce8g#Yy`j^g25&Q?KSAycWuCAnpi9=PKKxU8$bPglUPrJrqD@$lg=kaAWtzVCe2D ze37v&rq#*hb{*CI1Gi7+U2QicHy})JbLq?&n~t%%_q6$;kQRei&LFjxK8To1sz_7~ z{-FBbPw1*~L&;rj!%q{}bo}zquI^Fe_%K~{JYwJT&T-(*Y=eBn%~N6(4cK%%FG7i* z+sC0iL%BlUk?UfM^O}llF+grFNqu|CA5%pTlwS*-h+aw$t#GaDd4KH;1pe_mYAOeF zANL6!W5UJp#8^VWH!FCJeV{%nsp=z|7mSMd?+bNPw;Vg}%w@6pcje?KFPkS&>xDga zt0Qoa`xd>upztIa>TM)jN;ILre-yw-lbnuH-mHgDDf9;gy{qO@m$IBF8cW#TH!?V_ND5*>|<(TZY8XMX{`;79-c3O`dv(>v}f9_!w+Rx=H)$JE4b#TRJN6IyRAvLBvwAP6s3?; zw1tHgkJZY$VtYgUSeOt<1!aax(j-U8@5y^Hade~$CdVsZkWv;D z&ez%9G>hJ$Xz%sDPRN)2Cg{UZIM{gqlqD%2kyR3-%ejN2Xl6#Q@;o@teZ8BPeost` zZ_X#Ios_7*BoMNVKNqtVWG}VH$FLUwe4!|=$wTaV-G?Hr3x8E7pT0nSPBMW ziHNQk=PFfhml1n9okdGW6V-No7nh0q1NN#lGNYGsuEhJ{ck+0*vOCmgiOc2grY!LC z)M!Psm%I-?{%9?|Fn;Tv*!_;l_%6}FW8-yxXe!{0Fq%peF_qprN|A3=k~&1;np&mK zp?x-Y;h*-F0}BJNd}uzEucel}7)$tyHB7dY=_(!Xl~YPCX8kR%@P+6M6*0wz%(*W! zygX~UwF>3fJIM+1iVk>AIVNs7Uuad{awP)1cb+ z9Wkwfu(o48pDPKP0+lA{I}Q%9fWlYbtxEp%fxXg2;@rhSY`Xy=wk_jEv-!GDrmbucZQ1mUeP# zbC8I^$V>KTcf!7u)u?0O{u#gX)HWn4xUg!}{s6DV6MNkj|IRf1nSp&AR4$Wjc0(+S z@5fj0LOt>l6!mmxS{<&&f+UATeaBP?uCW9l@s(Q2R&PTu67@c?8AC+(bu5WlWeOW> zEC(ytR|>}LQR`4=4PEC=k5__Jij{ctm}kwULe~B#P{qoS~DRW=sNI{t+<9?f~ z^s_Hq$C$Sd+z;qla>rU&kXEt_lQC&dzwq7u>aUKg1m36yTsG%v1YGEZxo$E&=Rbw8 z34QowyTCj`2jPVv$_jwDLsA`G!EP#A^dxc^spQburhh%vU}ECl#vM?B3sC$7p?H(p zCq@e2!yTZ2A8BLwOY_!2Rq2tVhztY^p}45`c?8i_6~*sf%Mn0h4KkBPD_Mp1wUR|~ z`;gKFclNDAl0y1BtG_~07038q{=Jj^*45CXDR)^+t;Hay)-f((<)TvzimtJ^6@mSC zI&rkf*hT=VsXv&=@yr9cAq2UedsL0X(D%w_023~dqR3ouiivvm*8MGtJB9TgvWnd} z*46kaJD2e~haL|XM7S$%P$SdvZZqEu;Lyn_Yl5xif5>pQwC!R92efW4;L)_p+nuMK zPEVlNgc48rmYXnW>e0l&+3g+rF4PFq_1EYzPAuPEHPB^3AhA$ii+|d$@>@zUvU#lm)t0HWq-H&{ZgFog9up|*E)+VD~rI_(HF4cQ4uQvNMB>SopC#b_%1X#xtF!$ zkX(EIv#@NRxnhN3)Fc;mU?epH^+co^7%`#Vs zL|f22+cV@%M!P~I2sT?C+iesnCX_K-snd}8&OGEqF`BpVw#}y(Q3-3If6+1zVNJ^vgUo%!o?@J%CKzA==uVn^ zzSpKLsvL&EeXPKmwB794*sgu(N@1%i-BhMGd=yqyR!c0>XDF>wSq-kp4+?j{OUxVu z2co9IlpS3;^Xmb|&q-e)3vb4Tiplw{B=Im;`Alg%jme|409c()nbF%rYi{O+hyBh7 zmk^4jW;h<3rwei>hC>Ks0Twsi_|DR%H2;u59Z}9Hc9Pa%ZQ^b>lXr)@^%`+*IVFa- zoJwMe1cRukU0cSd>=Cg!s}^WuPbvy|fOG6K2jo>MaW z>gC~2+XPJQ^v45TA)Z>Aj+9G(G_A{7ot%F6feim(WEWwMO}QD!o;|7t__8u1U_cz1 z0{2>-@@nzZ3F!dSnE-JbJ@vjp@|-4^qNJlpW7c>bW^MDUJjox^n5mm8gjrq6vkieV zI&%~bfVw2LeY2m}x;%dncAvfJ^!Vt9mE7P0D8tqjAUBftw5PNN=D9z3qJR?V#xJ=^ z4oF!J*_mt#o$v9Q&^R2?FAC^?|LzV0Rsj9DVCm>S^tFHv)pJ1NwCXk9meJt^RCMOD zWwjkURFXJce{vCm#sC$G4~I1DlH=|Z%b%Dgx+s!E2>+qf)`Cju`r&S z$R)g^Sc^VXv&?r;4P!R<;HA*4(Ab@+{@4*ZD060gD9Aw4C%7V(#&-_FMoayu6|#;t z_r96~ZQ|$4!(ed5EO}{fja9o)GBIg)kgOWm>5w8UBLMmc>|A;$=|3U!(cX@dP);T~+SHlSKAY>Tp&KEKF4 z^bbQ=H;AT16VFVK{Tf0;}aANPqcL2Lj=cP%$V7-d_-?`y}A{ z?4?|ulUs$KSBoF9$8Vp}5^J*j{_KeKEiDqwgwo#k=rlR`dGmeJ&aXA_r#g}rW7Yy`7pmE0-p=ht)G1!vpWzplb~_3tGwkc&e3L~Hnz zSRWsei3!fAkyJD4uwQ=x>zSrJj^A#0YPt)_=}C95`GY%?oS6=B3DuKWMGnokZcOsh zJ2^>NC;~B*R0p<<3Qg`hcua{1p08=qI9Wp|$x!M&H&)%mV7Fq)TUb3~EAs z5ID-XHw3(b986TpkNhH0;cer9kC*B6*D=H;hLA-Q-+dWctMld{FTFP{h(uRuy{Wx2zK?t`B0EI@DL5+q%UA#h(mWu7{zBrf5K|4I0@ zPRsM~D%H%dUwH5&zC(Dm{DGHJWN%VnSGc-jz8Xm%tcE@x=u zrH6GE3({$3SAcf&BuQ=8I4%cP4mbY#cD%!2n!r|X6$*9~%JAt4G#@~&Y+ zaue6`go-c5+XQRCG2sT@xKb`E8w_xdjIGx_iRVr7(o*HFg57$6&GZ27H1#CX0HOU@ zVG=?q(5h@=vRbc}G_xq?fsa$5yualA(b>rXSPdpN0x1B{n9qxiq$&r7@R2g_+;dRk z6eFcFDY^fghNATE5#BbyatqWoS5je#4qqV&J#|m7GKP2i_UoM=gX$5FGXB?R!3Cw7 zVizN*b;58Ml2bY^)9NXQoy$}a89E=X{$VQZGrXx_*}ayYHkm^X>exa!&U?q9WWe+m zw*>tu=x>7ah3_sd$xCo~ZWH?x{8 zgOF5rK~J=^{kPUuD~H=JZ9g1l1?`;`fOT@JK1k+&{OPGT0fE zTmnCfGnzt4umaMcT2@s`Fs;7OchK?E0$2YDU~gyXXFJDLrP=9bCn>sRPnQv(6D0Al({ct@vkZ&0(^) z?uljMGnr}DyRWBiQ-O(188(Wzfb=Y6awcZJH#uwC)7NXuFz)VBG@^UOL41-983>Zg z>PS=x&Eyo+)c$@F=0V1-R(H*TMb)F7{v3Z2E?hrocP5omMl%ANYiNjEAWc3A8IcPi z!f^QFCQ${`0(vLo(5gq1$j}=X`N6e*&%;r!=t>F{9vKJY1)T5Q*j`jU`|uV`aXZ}@ z(bR~&qRDkj?0P`0g&Y@g^NE^^3qo-mO<9xTzzPBFaE=I$zGuL%6tpX*CV0Sz;V2)s z&ISV2LbmD3QbG2md&-_i$lEmSAeTyIYi3>U9|`itQU&{%;e*d;R^Q*U#YUlH^32ez zGzP{j<8{7XOP79bU-Qxfy584Z6U;$Y;Mdr>Qte*>%B8c!hKS0U8ebDrYw%rCe~TFI zbP@2P)ry>rOZaOm4_9Or#kC61^kt?)J}$J!{1!u@)UY_o>y!|*OX~BcZrWI}XOW0- z`)^O8!C@FkN9k8QIXuCH%1f^`;OOvZW_^myaeA=A&NIqT9XLpSrrWEk;r(ZH0fXGW z6A-AqfJ=#U)qqCf)3#wv+cabMNEEK!#fFnDdHmA@xn;$iOLu}v^~XpPZ@lPBQ=bByM-pW- zxsp~3xMp$ceWh82Nz*^NheQRWlM^V+>V5$b! z6X#a+mMh8zFct&_fcSNrt-R!tm{LO)ko~IL{X?2`Wk_W}2Mmy*tQF_|v#0+JU zX0d_;4V$Jv=PLU?xHjQ$apc|Bxg#-aX`4^(0@e55I6r0Y`gVCo6Flsc>Ek{$6%58j zl|_cIRjt0Ud9ScP@yFB+pG4to_*ZB?UrsY@Jf?J{z-lRP8EsXCTs(j9ezxh`@5qX= zo%%co{zrZJ)Rtkb%FMl~Nd8>w#emm^_!?p5<^rpGJtC&e@FR-Cko+@@QkyLXrH-K2 zQ(jBq2~Cpk^zq`UF^3I2?Gt2mHAbxGpBNm*fF0zXtE76EO}nvt zt(#2w3z%O|J})aTis!3_vzUf(J%bJo_J~Y-r3xwNjtIzM%% zg$8N-ZIbLiwz%Jy6uaguA-l-t_6)TBj$@!28uY+b)31*H*F?n>Z4BR!TRPkHy zleLB7EFag5XUYP_<91!mse|b|Gc2(1g)cBh>=U-8L~!(R+c^eeP3e&hBMF64 z7aTd_{j-*7$gFs~7yZl?NKFrgYu5E~ZW<*kj{lYin1n}% zwuMaD%1^~x-!@_o{(d{+j)PYXAW#OoNN|0aB0CP3cLqJWUHa~*6Dc^4o{gQ8l2#d z+e=uh&?6JS509^u#d{0d9ngOe(NcF^S;uQi&)jM55y|DLOfyLhx> z%Uw6Xe+s*+$Q#LjnXu!vgZvhmaWY1Sl)FPr{U)jG$ur92U1`f4AnS32+{n6Zbei8R zqXKxeNcGrnEvYZeP)rZ?IIMth!9wnz)gRlGJ{F8WU8p3x-{*~8NfeBw2U&kp4O0@mO zd99AH;dv5CieHl4CHu1019}~{e1Y-g*o2ncEDX7IIa8FdT&el4tLt&M$Mtn~t7qd? zjrt|S5YQPbzr^CKUvs{def_Aq8_Gm&U>_Cg6|VPn{Yc2C6HLcwe+KqA@hTh4`n=ux zub?Om_4GA)!iNaU0+dLKC9tj7?k+kY)H%+ z-1gq1>EHup-$_7lM{5;Nk5ULURPQbEnVk>!63uP7JDP~V(~7d=7cr0R%s$PLIVD?6 zI641osf`V?2P^4_GET93uhRS6ags1R{msg&xy1Au!ry;YQny+HMr(|2EryVNgZ%r` zL}y%>gCpD=D~AFU4vR`tX(8o0=Q_bs9s&|iUk}6su(2Oc_RzfUJ6IN7?0vLCgv_v) z5rH=`20WxmeraOE;k~5e*L;!v81r4;O^CbI)35Za9kZ z1IMnEm37ECAGd6v9K)Y-S)mc+7VX9NxJKx2kP{KbQ*Bva5K_+)GNaJqvz`Iz;*DW_<>bl|PxOv+m3AULPg9Nl3gcE5dc#5foo7YcZ0FbInC) zu#+sh>HPD871t{m0!P*)optjpboMptyl_HH!^h8J>6JC6VjAp?#+?fOr~v^+nif=SY0&_e4FDHIEXQ zR#Uo2q)YT6%VH{6pTW-kR8WpMm6_pr>KiZ4HS0B;J#zqk@J1nDon2TjU7uJEwh8t@ zS`j6P0(O#5qm%^wG{_d&iB{>R?W%QA(!w(FEe_zbq2XiLct0ID9q$kxugudez}djT z;CwhBOKM7*_gGP?i`#1K-tH7@m<(cpLNyj>l@c*8)_>hYbZaQ(sRYBcbbjA^Bi5L8 zwg!D}aQ_1)Zfw(|rK6J&Ro^;u*xPL1D%D@ceMR^;k11Eu-8Y9n0TWU(bd-!}fXdj0 zgSPCRX^%#kF}G_1f+m0$7%UDZa)Y|ea5IhOuctFs)eVo@6-oNm>B4_nFm5Ve{t8{y zfXnKKj|2uDUsZJGjiBpcL#tH^rXYhd_8dt@A@4#OVGb?OY;1C2$QC6LnW$oT3&so5 zi@?=R!|bSsKVsX+(|HFds$5q1v)HP{LA-KcW8?n93aGD&yLOZ;83%o5QVc0tr_E@? zu_@@U)|VMPido%%@wqSuO8)g=XWTy;`dr*6b>6`pXld!}0x2>=Y6zJ*Dv>yl_jO%e zPsReY2x(}}I9>0%cKLnh>YFJBTIO+hk$8HMEA#&2MbmJrXO*iqtJ*6RLkXW35SYIO znt&s=A(ncs24MF=z9~o{97PW8lO6|Mi%PpVRQw&N%uDxb6gO|fZTWbus=cHcI#1q8 z-e~|c!G+zJnNWn7++y~o%h6&^DULm z8J^^zMeHFL@;r(sd$a>9sCYoNFneZ+VmUX5Z0r;%`_4$S?h z3-pEQYWWx`I(|{7RMlcMLb`Ns$LhVI5m`A*t4}5KtGEs?MkA)PnxAo_C-kZZ(pUpF z?>+|d`1s(n^oVa#rj`GJ^-|YB$&>qHS@qqplyMpn@ct8_JE3eLR_OY=-=+}miJ7iG zeAQ!Qsz!9lW^KdTs0w{fkD>Vs9#Tr|fD@-YmXYRRt>|vIK;uO!dPdO+NUCPW|KOfw zR@^f772|mnyOH55(c!;>k2vRF1pI|Ee4bV|(Al_NFHf{dVi2PE3`4AZhT&oa&dmnZ zx37s=Fv?7Acx5t2@K0a|x7qY)-p_h~#1z+$u6;7g9t|vLnWeCxd#me`0ri@lk?}G| z^I{sk6NK3$%G!)kt~#Q`#0=4E%|Ql>Mm@GVG~{t8GDMWE{4iJV-yecu680Ql&m;^T%X|XYd-x(n8k{S zb(MDcY!h!=L3Swr`6W6_gkb<)Sydc=D5i>;IXGFIoX+vseC{JtgkQvEfA+`F{o1!ha8i>U~quO`Y1>b5-Po?XQw z@mNr_Bjb^A(`Ybi{QcXnd%QSMY>cNy1uMPn4D&RrcMkNo#guC50pkD$OV;86#=f9N zr!YK^tjKlp1qV1|~eu^NlFtv4l zo?o#-2MsO>eI+Opt!fhJ=Jon6Lmn^JVGhjqBYl8Wvl?>CiL>t!BIeHJhW^iQq5!P3QN|6$<~PeQYcOQ-3Aanz>P3Y{A^d2vOj~crDl6buFp3+PL28USA4i=o zlRZMh5m|+E8$aAkzzydijpnxv3>-gS+3>xdx9$pj@jqG(*;taUUfxdFxXbay3+lea zAz$WW6VqaF&9SR6)I+KEGxrgE*AYR}FYPu-k)!~$#v_C_v@}Euc(1c=#hI^rG&Agg zfys(Gm)J+zCgeA8wt%g$C=JqI6k%H#3SL{m35KLB;tY64z(dU;3m$7DPb3~P=iHbRZ^SX?5|!OA$7c=`mwgP3rc0I=2wjgCvz39e{*>}qf*06YvYOE= zzv4&fhz5qhp43hjzr6&kE)T_RF*aK=aS`qzV~ah7j&#{PdiT#BbS#+y`zm9H|L5Sd z=Dao&-gOM;DNBk;s?fkuiHJ30@tRO8#k5TFW6!4pBqlbT^R zxtXP0bJ!jn>267eqM2bzl8D1xk5!k?$MzxL?R(mFE($_MmYD)-9><;F9oocdO4Bdo29p-lgWvYsdO;57pjs>bV|(FO*CXw7DmZ5T_jOxT_Cx&X4Hvz7kak z>kC+YMl0;<&=4chuO|ZcMsHK2ACXfuc@nYQiti&xlc=TSJ0~5<>>0r+jG0BcCj0J? z0GSbGXBzLkbL>utsYMzVA{^>}H&u;Z&buXO$rd%%N+s;}5uXavo28G;z%T4-5CXS< z0}>u?)g;N?MYqLTU`e^>lum^&U&y_7ddkcLue0O=m0vIK2+JBX_<0LI&2M7==ZiU! zGNHY;^1oT6f{aJBMA#@TFBPxF*St6VJ3{dkZO|9+l$U-c@t5@%351(pRw(S6W~!4EaT(3f#zlgL z1F&g?^p%~Mt9&3QqPEDMjI$3Mk7NqCM+%XSo$5Yqa%_#P=(tSSk+N>7&8s0W~dw#bXOaJ%=_jv~@;N@+W5at@ZBZ+BDN8}C>rSwYq z8pYDbgeRepq8k1PFdeslYtec~$5H%HduKgFJote&r`k-Oqkp4BT@CC>2N*?i* zKPN^y7-)mRaK%?sYkmFpbJ%FB&|5FJY)yqs{_$xC=r)TE%`~m zfp9b5hF9w(^V?v#bHjg}bKOLnr9G-hyG4KTVW{AlvE$J8BPAmBpnLi|txAG)$Y8cHH>g$zF=z5k+%ozo0|@|{MF-J?ZH1(1BZL28K8+$;M!yw?b^Cm*9UCM zGSIN(1$JhXE96GRi@gW&?cC(Tl+<}{Q#e3qVqnk7X{+*C@=Rep$97dUf4*^RvjzjF zSFhp}9g+Zx7Z>5Y!+0*0W&n0UE2SKu0h-x53o;R5wK9cSatnQ|yVP?JwKSj8;VYHLojOb;v^~c(4>b6W!y1)pulZLf$A* zCSy#Wvi2R{fN6#&G~i54TrtB=&>bKv5{Z$%gg}D&FM5w9ghdBdOoq&uF>S;5XY}R8 z-giMORXQLz9)2=VLrIjD^^U6-}hCrU0*0cwb-n8;*|! zx5iee%3RpK0fqC%JFZ@icqYf_d(St>Rtu2A`~8N#oOM7{fZ-d@*Te%gAyw6~$yT&N z?x%-IRvx^U4#3(!{&94b-uaa%$CW%tC1fvZL`?^VdAESX%1JIk&A@xEZAQA47~qZy zw;K2Cda^-#a*pc<=Xl9`w981dD;bY<5R{ncz;c1(b4vdlm65!qhaSf3@MmFcq|OvR z@+lqWjH0vnCEI5Mf`~35f(1wp*6RbubAf%mfNVnk$IueFZ(W74hobp9$@?OCY%=L@ z@1Z@1>4{kWel_ftRqvUa$L%8bu9gYRj`bbab#x;V6}sbTX?#RMF<%N}m4=KgMhP5B%2I$6G&q`S$**M2ZU1BQ zgB_uvSjvyf4=7IW6FoA`X%|IY`)o&QlH|Yj8#t(P$@d>;UW2)lVh%o;%l*?_k(w*Q z88)dY*mYN=^AWRm+pqxe5cxvwz%1$jB-I?x8-<0d7uT$z;OA<~cfYj2gsE2~7hdSY6`BWl2l!?!di20tJ)F>ry!UBn#I2P-?X9%?)lYtte zZ$G-Jg*!i%ua9Mhtr;Bi7d!g_QU47kN(8nWmG@{H4>Md-@tzOXT~gNb>S-l+m4^5O z_J~G?N+aapBlgEKv@9E9BkDtV5<1D#X9tcR%cO@9V0v`wpMCcCL#|8sJv~wbdTvjM-~-hHr|qolPhA zLxm+F9?X>lJZ09Cd0E?rNr21YSn}JD*KU3es3cv zL08mFF&S9WSXLCgZEm>ox$4-*s2eB*Hmc?S5O%gRc}&Gc_x0Pn*vlUU*<*?7MmO#s zdKi7hflDsz_?nG0j(q6_#jx(G-Qq+7&5fWu-iLkI(6P9fOUZ815Z|r8%igqPHCDvz zgNuv+cI%-?PMKwoCSGKpaHz0j$`&`KIlQTyHn7ylk0c+?Y}=09<-1z8K8yLPw0Qplnb$X z`9Kn8UEdU2yXkN%Tx*G24;qf<8NZ?mgM7X`BMJ6tVk;RP2(j zU~-8vcJo!)?S|e{*ih4+`O;IiZf$9Eyy5TXf8NGU1p$5se#;)vCjDx_j5@g=u;uhB zD(}LJ>UA|i5&rsb4(Q}dvM$Wr*ofkaHgCXX*e`|!CvVBRPEF(`5kA^a{_ zXK-_UO+tP4@(+La7xpHYJN>{+uB#`1znlw9MgQ} z1UY-O&0rpI#&&GwiE-~t-#;ru7~U~^GiWJQW4ISrzM1qmGPJ=vh-H+PsNcr8k8kh8 z*JIMfnz)2)(@%l9|Kws2bGK?)JDNC71({V2w$F=;a}>&DKe&NE$*rcLV*ENFZ=o=t zMRTeFDE1Nzk3z=YDyK|iChObX zYN^9suKiYt5-G}^ogLM`arMWx^U)nwz3)|k6+@OWh2&xb%^0oRzH6p!Lpzi!k750W z!fS7&DCeXWIL$g;ME#7nXT9*=^Lp0K<=8V(E5RSF{dxFQOmi731y5~}Cf=*x9+h{d z{L*f=$qP)q+-)0~IWU|4j>J0ImpCa;md0C*751qv2o(;r5+e`x&5=G7uL}C<)MVAR zv;Cscxc%yIu>Ej=t4MO?61C$qQssr$xoNA4iq)T>X7ilN{XH-#}?nV z$Ne_tydPrM=|0)9hEw!k9qtemjOAt;n>Hh}2f9?6_3(Q6T=t8!``- zdqNR!a@|`%4_G@X0=tuQpOmCKMNHi^SrCy-Ma)<}lNNh>&`F#5x5r26!c@I!A?T>4 z(zE(V*O}i5;-J;t3H_TYg;wSJWFCyweBS{6%3I)Y(VT_h=rs?UD>tNrk!%d~pbv-N z;+C5SAh|WR4rC7sxb3fK47n6V+ z*^XlGP5-`a*Nl;sH~LN^?p3Ale7ba`CyF~<;FT!Eu1I`OOzj2kDY{X|&H*2yQ~$nJ zZ-o^MA-<}Fcr+&KCXB8UB_HI075As}^MciE>Sj7qqBjFogw2qUzi7^~t-%0?1FMJL z#-&d4ef{x&Hd(1Ukl{2wxitD0#p65eN5k+(+Vz?yUFHmZQ6(5+;G_ZuTiIb3h{bUG z3mJrflK^xSj6{@Ity?de%?_rStaCgi-PNL9aZ;WEK558BvOowJ2P-Zvk0fcFjhXCD z+V%btZ1zDn!n0D1iQoKV3hdarg6G*xu0#ck7gaKj3f<|Sm==PFn5mb zaHY40v`F8mg5l*(NfywTBts~IAK$F!c(0wW=LI8gc-Ng;a^*_;SLfd62|xJ_k#8CS zp9g)tw(%z#T=l3;Ex|Boid+t*f2F^|-)Ae_w)9gDf}w*3UE9dR>ev&+^yW0aU$&DBHpst^16g7HQJo^=DKvbr&+v5g~&ym7Kg zgOL6cF>;h&>qRy|$Mdht1Z8tZTRLCgQ}LIypHmdx9hk&OR4dnnOzmyiDThwr~;0h}c#ZDM_dob9;BAuWWB_Jr4>Sx!IT)a#}@$O(Xt^o0_C z*rCEPZi`3|lsD77zcJcoqf5@u3<_@yXj`gHf&HwZ-V>Nn=0Fp6xGariO~(3JK|xUfj$H8p_ms08Wx_IWmZj zco9yF24e^7#SK)3!*mI%U8U7*b*lEMESMV~WX>+zC!(6iDuR4jo!}H0r!HB-gibh(^o%-wF-qWf;z}-9 z7abRkpOQ%51ZN4e98#C|xU}^gT8I`IZl?rf42oTSxtVj|N6CuY`ZLtKQwzV{nAHW3 zSGpE05$6B^=}nqVr{bxX1J}UIh^%`Uhg+dx z)rq3(;U6dB`MJqlJG|hI~$kWt?w-5}^cc+0Pfghi!nu!gX#*1l^3whTP zPiyuo;eJRKpiuf*lvWoa{A^)y_fyf=o>7J6muv}XW$r^JwlG4y)*1vR<*7SX)O=Gv~IK_@OJ4!)A}|;3_#b zy>Veo$-#G_CaM}e9z^Y$Y=^6A`F(5lYJz&f`>Zt8@bbl^ui^{b@=%jJiCmIbIWn&r zOU&)ErEM7Z9X)tX<#J?-vnOq?$OW8xnrj5@ZYUwSnq!88MTlsquM!iBT+g`3ce7o* zn2~4PU$}oIslMvX4=Q=EH%w2>WqlPzP&BNic_FD36amw}$02BFV@C&7TYmMvEYa#!neCBy>1kSnICk(-`rf+eUAgxTTY3#BtEe8TrCL$oK^;SvLvJF1 zD0@SF;yBl=VK%Tlq4kLf6_}y^rBjX1Yz53~*#%=SH-fb@oHVfXT!;TjdK;3bL+d}M z?(kUVV?oW>yW>6&oPC8wo$LqqMrqz3H8aAXK zB{S=u%0}y+Dq!Z~i^!m`72n3`` z6G9I)fD}PGBuFRpE-myL%Dedce|+;L*Oly^-I;UGIrq6|XZALeM67VsauV_P>G)U^!=;$-n_O5)HIx&b^%v#a+TciGRjAqA~XA|EJbttSm%uipXhFbrtyBm0j^o`jMk*BS70VMEf zu5vKWcKUTr*U5B}pZZ_(0GzOhkl8wDGg4SXsG?aTi+c`;rm?pSc2>g-Ms>+yWoWVf>v!Wqs`6+#& z)8C?1)~rL-rVa_>2^l zOw4Jkj5*0gX^us|6*Pv(<31`W;9N$Wq!*RNz@8gfww^)lGip}xi2FFdM~QZ1U6r1- z*{l#9v~Cv@)@LMx6nZuMVo&|mhX*a6N_Y6|*d_Q2ZmqenC)OH|YG2)*z}WaOZ-AI{ zOkX*eaIq1**CIQS$&l$R+_6ShZUCM#%MB@Y*}A$?Sny7BiWjLkGvu z(XUz8dxFKTT0LQ-O~>$bX+LtgPAYw=1n$+aTBSelsD@;kp!GQz=TA(DBVD|C= z6Xc&ml?TSRN(znFabB(8R@3kLcz#m%P$H?j7zfc^>xs>9BrT}VD?%T$xvzo2Zmm-9 z`wJ~+&h3SpA`=1&a#1W4RvUV~VJ_^uvK4e>vQK3?e-(DVZqcPJ@hlUY`&wOWCEERq zv;Z%TVB8&A1zg_34Z?U}vhF6a2Zs|&5SFzTI%Jrwt#=Q$LDDUnNF|^H1{4wLUa)MJ$5Q|L&##H5h34jG8>%HB71bDB9?bnv>e(eZ-5|zq z2(!n^`sy~Dkq5-44kWuVXMJL7q?`XmXtE!HVse~Hb#5`rNjX~d_4%v^L{z%Mnr01c zlsFVbFwx&GU3NLQoyNxVFUvI3&^r!0Q-xq$P7(XqEjofVK`O-#N=rS0pEetfg2DiR zoPK2HtBH{)(5zd#CXfOwSO(1+3~0V5snDbe`3MFi*S9ob;Iy7HY>G`xB)@t)rF zR6CeIf-aziY~j3U2C3Ur+)?Ao*#foz+Qt^FJj+2rMFq~ihp&v!4-y;oV+00c!I#f* z>i~pcs7lUrwveo}J(|D+&-n}6Rts$@feNZ6-qIR(t7-+a-hKs~Z);EMs9G0!#A}lF zn6?bEurillNi`4j5-SH`Bbakoo>9ym32(!|1o2itRrSqCwmFEC&Ugche%mUy#&z;E zCzhE)haKi@ZF`6($P{2K3k(c&b}ye5MANG55CXI!bXc-mD@|mw@kcT=%?VD!$g@NZ zuaTq#r-AnOqgEPHNIE7ck)9y5Cq>)$KmWJsnPqX%bF4E;r~VXdRAVAay9KF(I?GE~|+h z6LSCPPO;M|G?kv=6>?h#BnCnq!CFrAEY7kv4d)4@`c zvPhSfJ!!AKDoyvnPjq@zT7qHRx42{EuY@-0nWdeh0JPbN9#?W6=0fLj1!$s|45vc) zn(~)!aMj<7M&Gq-oPsyUh9I+3E?_pAtkI@feUb=X`OXCh*!*5!6mc?w+fT%>^uwZE z&1ovxd?Sm)TkESrV-u4--t?dEd;H4Su_&HY9bXm51hV~uJ^DpUo1mHiyVBLX!m9A! z@m?_5ii!a;Jj)aaV0l;=>_1vDM5fPJaa)k|RCdks%8c1d8CUnGPW@D@*^2p>Rd7I} z2oQ25NI~Gk!6800zuivrqV=S$cfR;`%eur-1kCB-D;_E^OJPu)pzZc_zZ4K*x3y!2 zsocWl>kTg1A6sPX;Q15dE9?3cUH*93sPC0(cNwS_xDwq@4l+-rYYj@M^GndD-s&`1mo;4L36Mq0R6~YT2@={G zC6Aq~xvi{%wcx~nul=}e{7hpj`Bf+-`aupOXF;vew#z`XAW0bZ3cJ*`@HPlNO zC_$g>-ar2cCVxe71R^oJa#q2UyY&=k@O|>ed;)dI_58WLpPgfp(Dk3mp1Zm1iJ_m1 zYS;|Ex}VWyY;CJqWb)g)egXx*NE094t58?Ey+#Qk` z$Vz6xQHI~Sx}TBb1t*~wL@4S&<4~q9&^MbnxeOb@V78F)()}imWn12j_AjBD7?FUq zfHeKD$DgYez~NP$F$cM^OcVlu$t@K$wAS)bg=R`(H{9HfmYZ$GYd>9KJpPJ-^ zl_wrBoe$KE-Aae9Dz=!1-Of7r;?jS^W=_Ud>pZ%@!iKjd3tePQ4jwb4^2dxN!XH(-BwF%GR=$u78kALi)mTet?|Kbc21A!+q`!DAqlZQ+1Pr)`Mu?C zXY>KUYnahbwf)Om&{Y=%s&}_OJ7$R}Ma`uuwR&y3}Wano-LKD@I{|f^dU(S<+rEUoiM58m&3IQw48$T( zg>h`7ZO55?AAMt5W5kjJHJzeF|A2EwRFJ^7MsPkZ{}X_;=&cv;%iv>R_kwZ3mo^X*WfN zifq&U>vqx=aa!+N+X;6%1>yN)kAK&w;_LFG`KzCAZ_sQC{?3SN7+yg6W1fF3T2@#9 zuVR)gZ5>mdx;>6Zsv`KLKhcwlP73y!)`gpN$nVa*8*mh;U$DHW^^6tMU)Ee2n)nO! z5qeU;L*t#8BgBfWt7Zh)sSKsfPD{sOn_+fR_dn*!zr^f9%5&rE2!LW21GQYVTO+)B zM?L%}xFJ8h%wEiM`~JINT=5hTzvdrP0*Xrcn; zrObw`(-Bi(+a(9C6Z{0=hxQw!5m14H)9Z%{ZsBM*^w^=;i}2>*^oykTorDI#Q}*=$QruJ!wj@6@05^ zWdGsr+OKh;=Z^X;k$gFt7^p)2WzlWXJ3ejEL^px;EuOT+@gChqx+Q;LQ43x+*#E{EW!QTd}()|0@?K zEp~s#t5~S-*&TXpC+{k~;GrMZe4snEs=_mNhW7o4-ALV;)wC|@PlGiynhbh`j zTFuxK*`=;k4M_r|;@Xw+Rl|wt7ht8UC#@0$0>>(|%?*$CJCue+r$$n%ZGd=udzZTAm$!!oCwm-7EO(C|POB28&|RnZo(`S$`A)F1 zN1CjIyq~U_knuSvKJKk)p74C~>2=vgWY6tYsz=tR>2-Si;C<~eDx6To_3@lk;+p3KeXaw~snikV+8V(d zmVlg#t`q&FjX2?;U=yY-Gd99pkA3oVrx4-HurN|v)2p`rV{)h@n7q9#=j;AM%-P%f z&oT5b+Z-bU|IX$wSh7ErxZjCC+nB_u58~L!8rTs~+1UT`D1)+TM%{Wx+_(JcWRX5Az3SOI=u8NhLx+Z`xYI_Wqc*%)zc` zTi>MkmKBP`21?dIUrDgT&g)(7C64*z&p_vzaA|WF08euX|GC>nWa!jEb!R3F)0h}( zS`B^0m0ERJE5$vaLqSd+ZwJ@)nqtDT!=$C9%?;RL0appu*l*mfZR+IY4B!nfB*d?woE zW8CP&ATYgcHXwS~kX;vd;+s}@f_zliM3$9ph{4I@`mG9iW4DcRsBk98v%aRzjHZ(Q zu!T@RZZbm@^xmx}PVy$ZVM^jH6>=CW@e@Y-C+y>@@|YAt&!P`3TFyAcRhAu+kNm?j~0~0wd%8zg}ytYD~^n0 zom&%}H8k^$VQbT!t^31ZpfEDqSJxB=J>`wO_NOpLaKWZ0=)y7?_@y%}yooQ^>3!;T zUo1v3jhAEgE_xY?_uNN|qax?mMOhQy)q9SV^!9 zfS+(WlrberiWL~PbBB1Oe;}?o*;DhTrfHl|*(EjM3R4248nzA4RPIAY!(2PwIkJPm zvxfx!gk`T~&O3}4MrPS$;dLi}UZh1mit>Ve;+jXRtxbH)B>_jT>1+(zk2k(Fzy8&IVHs<2edhN}dBi2NuxrJ}`(xDJY@H#zDb9hh{+Pzi zo6*jI@+dPZT5Bt8;itosGUiBD0L9-t5IcH26Mf%V00D!)e)VZ5r@5k7h~O0xg{wp8K1n6@agXhs#4E-4KWUauYQ2 z0sk!1d@PB|SD4v)@KCt?Mw11wuTc`kS~NlO?4A}VB0Ri%*HrA6NM5-Wnt=29~>Rk+Vw4L0>fX*dMEEwY?}5+xxZcFdi{99K+TG#)6B@o2y-gwyRo|h%iCsjgCX@j;&$|s=0As3k&GP@8de-?;(VEolX_1{1a|;^t?L28mz*5_ zVGpav<1UlX$npm{Ry+nhkePoF&4C5kDqt!lvBMdp!Bqh7`5k!&#+k5}B{HOMh6r+e&=Z(|9)r!0cJfsBv5uYr)1xo89u61lT0IU>ZaS2Umk zoZ|J#-=%p**5eV|63~xgl7YJKnPd_7thM}hO zUA9!z);6-1jphJS|8E?K0=CahjX*S8%P1IdJ70mE9Ja1e-|t;d>_M6`oLcQVQctM+ zP6TD{pVS^OC!HY&Ai}sLE|lO$k#4FWJQ|(GAJa91oJcPg5fRGC{}0$Kh^A%H=@a559Xw4v z;OISh3!jfM2S_?&Le9-CbIZ+io|lPuWPkBuk&gK)k${36p4dEb4B8gXfQtbOM6Dno zS{^^^u`^DfjtU#?><}2ifYsJ$6TY}dr*baI&u14d-3*Q>J4E%{U&>=dfMCc4h)<0{ zrH1itoOld~FO+F(m|)CqYNQ(;KNiq}u?k(^shS=+LW&RxH2j3 zRhJQIdj6tat(5@KxX9y&sHTL#gb4w&R74;;V6{U<;Xs@>)`Nl1+It3}eu|25YR@iderFE!;D zG@9?L?M_KXaEMoBgTc^RFNOkk)zDDi9dc%4U$@ zuJRkfT$eXCRxs53Cw)ov#;Yvhz+J1Zym<-R7!s#LGEAV;9d_moJueM6V}*6@uiyLE z4a*OwOyNV`Fk0>N_f5CPX?=zk>?@zAsZ?3zqO?BuL%L3VMuh&)Cp@{muXnAHp^ZL@ zx*hp?OFY3=1Z?#lu@*ol6p4N(Sla|Dz@e|zI{zCLY*@K=t&!V1nw@JF#h(2!Q3Lf2 zRS7IwFIQmOD@?79u|VPfuT{q&&v!ZMV|x0oaV-LA^NoiYPmaU1J6H#*wmS-4l7jOK zCOb7TSzRgjOCtVtMCR#ZFq2kb5)|R;-U&^AAMBq}Px{tsBA%A$<&#xowA~{h7=$^M*Q!p(>Cq=Nlw{j18{jo5` z1E}CQ5u z4IZ~f-~RO2k@MYO&4rX-1LU$#M{~5U0=e6dp0MEygfST#@r-{2x?Tu^96urQ{FO#UeYh$*j|VotUqf@5{DphK)F9L!p^{L{R_zvKmQ%jTgE4>S;Wa`j9f}*Vh@Nw zCqv}f2Vtfb6gOiz%@ocGDPJrxU)E}DZ0jju*UnsPK%xLG-12AA{Nk^=j4BMYwC~gn zdx7~blD3jErr%h&{%Fdu#3u5ip^}IPz?h>;1qSljUF7`<;pHD?0~sNVK{nl| z*@94F7mc^5F5-r&TVXY07@5+7DY_68CG_T-(Addaj%-sKni>222GQw&kxP60&sSbO zfA33T4H2!g?90j;kU3Vmp-^5Lx??wV!(Lgc(WwTLOLuK*!n7@l%dQ*l@IkH(Xh_Qh z6&O$?-u|4inO6;Q@@6`jyiv|FZf`B|FJiRsrxSP^ueM2A#xwPc25_CuUlS?Egx%CA zc`92#aS_J2d#vVkhcRe#Mmm9pZC*3Zd0hI_#b%qg4_b0H-i|{VVUkOar_Lqnr9W7AzSY`qTnr1=hSo$v>^qN7{(e)n#r$S(Toc-g;> z;YwiW9gy#NO!Yt<@S3C53w-YAsRuP#4bkW~OYF1t(!q4DjhAjRdjiCMmZ+pBSr6v- zB`v-#aAa7NryZ3;SAGH#_Z5ZHb08U!BLoGeE26dMQ&0mTLez#vm^kL;795+)iRtsd z26O9LVPOGo|G9bu9gk^jhe(=#K|snZAikjoGqQ$AO=)SYvs*_k_(y0kdoXnD=6-emWo*LMeluohm*uiL|q+ zkWx}Q9UFX`TsxIE+Nkn&r$>3+w<#~wxsCe*Mcup`VytxN{JiVgVogD&F!B1&@{^!G4`we!x+wDdYhYb<@v%bq- zhHsp8f&{B+YVMH7FS2_e_~Jv_TixpI`)bhH#xV8N#R<#M$8PMQKzx(yA#GnduNB(iWKySe`HUCo~o~-N_y&Y4T(C>maK`2lkyE(i11UHPdL))KM>( z)gdqPbZJlDik>`|sp7>#6>eWZXR0av&~QF`iC0mb z2J>=XKG2+prhlu7goLDz&1(wqaQ>H@zM)9k%1H!x8*~2mJT!?8@Ssf0AIJaodLH0( z+Pl8>J-YA#Ae3;Cv;(D5`0{sC1)zd@ewPY-bDB`$|A1lg`~K{=4?j|b^6(3Rqi>*y zFt;Sb%Zhmx^+@;H+n{i}Xdp3O5^(d(lLZ|_fQU{l%zCBNlOhKLyjOIgETU94=s|C z!h85V|L1w%^?u*CK3z+evxal-v+upH>)O}8&qr-d6=FgfLJSNHVl`DI9SjUC4Gav- zPx!dNCtX!6-oOuBD-9JTjJx~4UpmWDFfg8Bs42&t&h1d*RWc5Fi4c9+tOiL!G)bK&Pf_7e+QBNFFyFZ!vh z;{^WS|75O_qA)=_Qd>FRyMcj$3NUXf>j{%?pPh*_m?D+#M<+1ei;|kMGW*Zb3!9Qr z0&LapSOz@Qx)=sLS#iUe0v`rb*xM7{#!=h-yE^NXk&%H}Q|Z=8qcH!wm3kJr#(#Ho zG^(??|0E^y|K|rYQ<$aCDEQ5#*Va)MAwjQdXmnR;b3H=i96j=u@nyTFDj(vST#rBRI9??FJlLhebzAjSsGlsGT%**oUuZjUyU)8Z)=8A| z07O&*=AVh^3bk*z0}+;imj|pG1T^|Hbu9am%hhLnI?0cFauN@ItS&lTx?ECUosSI+ zyo*yfn5VKn9*$wvO{?$h>>QIghUY``bVdD!(Rqc&)Xrr~-?@tVaoc4(cU+71XDZaDv#u+35v73J3kl!&+kR$UJn5esP+f2Bm&_x& zY@77>sv{|94T3zrPZVb-r#Tg+yw3vGxGC&fzVu~PaJNpuG{^th{fw68=H}KBD-dhF zoA`aYWeQi(j$|^cwru7C|Cs=SE1+ztoGj3v%D)#Wbe|h)y)mr+^Gzc`9Q|zxZ^6ax z;l&f*2&i1YNvpV7WF5r=zA398K=vd6v8zg*P_9d@CsSwIRHONQR1k|ZzmW($0pR#|rWB9%3`!D^7KZw!`IK#3S{1Hal$7%YCrp5m6{!jH(Z8~jVxAY<1& zKn3hsLWW!2JZRLh_&s~}dt{8OHHfpe92+$Luv7I>zMsQIa}q@)y|ZKTxVhNekr4c` zeKzZ)_fK@@rSvPf+AYpx~(nnO97NAEAuTEvN@f z9!o5G#|f0C8V@CNs=*WV2hXV}4P&P$-c@Oe4m5Zw^=CR+1J5Aw9CAi>46*hc|E>3P zI>TjIEMpc3Bn}X+fQ(V1oIQ$C9S3DjyGSr@A<1p-fe@o}hjA(Pw*e{31uAQ=x4asq z8xK35*?D{Z+<++NXS=2+nHxqELAu&*1v}4Vv(MW9Eh`?2xZ?#awQ-T=D>#EBMlodclv)I zFj4C!zW!Zx-8ZtvPc#{XdP(c}uW|MIhwr@VDD{qiMDno2mUs88wELmNj_fkj2FMeu zdSK@k9VovS5Va=5J=@#7!~e)MB$APPQ9vbdQFZ?0 zt$*J5alB8*xK~1BV%^9ffPQsAN&E1nSN=Hj-{}`F5o*kKFNSscn1x-wm{@E5V3srM z<63$xX))_PJL>N>*UDiHYOXR8)Ql7UB$+{ER2reeMmaQ2;YJ@{8SBQjC7pM+;WaCp zch0;h83LzBo&M((H^>ge#{1H({D(3V<#+l@Dvnfedk(Usl4~-j`4A>x*8yBm+0be6 z8Qd3}_}{zYe>PqyGlBM1!b?fY`hey85DPJgBIZ*&eUt}`D6hf%IUm+TA~hk}KZ!g< zBMb^mGmj;-Cbcgm2Xy!@;sns&OwvK)@%9rvP&(%en>6^NHBI|%<=_itxy5EEb>PzM zf_%o{UZkv8u0ltR;(3}Q#eI3kWwbuBRJYL8os?xho{FOu%9IYM-xKf8d^=rZu{=LH z=^fzg>>Rtt)33+;f6BRS6|_`B``pUxSy99JFqO4>3b_W`pZ%UZ+IP!9{tE-Ubx%Ve z8h}Uc3%~g7qDSeM$Ynt}aGUFM8TLuE%EV%G-f(kLp3uY*p<|UJMZMWIPs-V1{j7cI zDDQXK6IRrpjDmTUZ2u`L-P`+62~6V%qhhzm1}0_LQ)V0S$h`^&Tx=T>%t~vxBag@k z;a#HnHAAP@eP`D$ah#8Uwc@OM70iO0vu>ze*T(B?bbfAT2X#|f_X9BE$(8YILnt@C zOmGS1ubuX1J z-92$p?cm+2QkH`G2(!$Myr_Mo4cI6t>%q${UT};uXJu+`KQ>;MELl0=*wmHg z;-8f4W-8g|zbr_vB%4PErvO>IYKVQ2((Stn=KK!)ZmIZp2!`&}=g*)2k|vee{mlHf zF_>aDAkhD?A^6|bQeIx(kSXv7Y%fsy8z|KkI}3}wl(dfHWC040^Ep}vG-JeL4Pvdc0xJK1FpKkj(ljyc&faPw zNyx!iw~CZzo3fp^aj0)&)5t5SvLr#f_KWJ+2(NenJ7G~ssDQE{G=RwRJDM+&A0lvZ zW;A3O_qT04Az#gKRyAwVmC?1j%Lnc?TPDy?meK@BCzf9Rs~w7#;ep$ere&WR{;9cO z05;VD{>Xe{zFrN4eiwe)P}k%s4D1TNFMQuXn!iUCp{vytF*KGC{JOS22=-@sSucA0|C4sahoaQ)j`}E%q$_J)GX#h@e4*HRHwj5z_!wF-i60ac z)TD_`rMn7T+gj&WJmNR4n41qh>zxxj?rHC9ydOfjAsdXNkoJU>BsE>9o!O}^$yc%$ zDj`QNoYq4Cw+5nmLR2d!Zp9jgOj7eqUIF5 zO82BMpX^Na;iD=%pgbJ8u#*j|Z(NHdrI9tUWB50(((XR~8u|e9rnWxr#r=|5@zl6T z1%rh7rolkGijJ@((wF#@9sc^QR)je!;F!~dABD}W1cwV0w6~9>#FBfXYw7}xd3vJ4 zhMA=wt2w;0Y3dq)h+6-=Fs`$yP;b?xT=TBsI)}J#tjiH1xnV-Kg|GzY2MOed<+WA> zU)r-9!nT6Y&EAqeg?rL)Cn99g_$Rt}4=h8MvGVOFja~acRC27oz}1E zO8Pd7Q10`sv!=0x7IKZE%0ppP-Wclvw4{5&Bpt(GBtS>`_=u4C_?N2P zrSD4!!%)_2u@jKBLbj>NRPZK^Zluf4KUFu$qs@)Tsl?;x)W1-9GobA#u$+ zpx21A=QA%RJ&kon*nlk8b^=$vtMs@YTXyhS(dujBA$B4fG~-yNY;ER*UAK;;kW_o4 zn~bza(lD->J1P!iJ-~)(dlx*`6-j`uwBiL9{i*rAC7)`>f*`H?nxeqxee109oG2bsM2+MXHG)UFZEj+|A5ycwe?q3gcrxuLJ*=dqP zUMU{iE^jF!h+f*Wz~t(VK>eu{?X)9$;ZyYPVi@^)4qO9L$!dx--YbNdfAzF zF6dQ(HOtjmzG;Ph2+GIK7*01dQ{gIB1uGI7671tb{TdFdX+Ipd?ScFCq@0ZfZEFIm zHG_JKp5k+cBkQyYmrHb~wsc-Ter3U8cvMkhOMpR|JElct+koFgh(U;|Q{A}S$eHpzS|*cU%}%A}SeV{)Hmm;U?QsV||PhJMK( zGm3~?ykkw1fgn_2Qs%cMJ!R5~y?eVCZF|xY(}KEJy6ahgL9gjaiP$e7t-2(Bxx<-G zw%yg4^}iMh{=5$Sj)^5(Fg<&mvj@7Y-*8*B^Cmto*iU$&jAvrNhT*U7;MmCmw&!V9 zH}VjpOnUV1F@qtt3YM4}@m32xH-GzxEl8v;omDrT+4G;r#Jc=Se%Gi9SGhLUcJ}uN zmhNXp$)Ngtb}-QmZAFc(qc$r~Yj*6mOTbO_+2)GF?=3h`pPXAFr*WKOKw{KCRoe!C zAwn0tWEA4|9IIi=BI$V3kR_Eqn#4Y@a4fgDxc?Pdc6brH2ZiY&-?zh~ac%X#BvKbb z@e+xa4*lyn3kLpM5uny}4SI5ENLN)5^#^Y0RXOZxs4T()fr4(`3w>b@d-#Zs69sJi z91j}&!NXgaBi}Q3Afo@#qP`3t_9ju4##K(cOSANE$qa!sB#>mHJ-LBh_=Xr6N{YwC zr~pFSHwq+YsZr3?T3h+crakGBuTLl!hLx?$fSSE>Vd&mD0p1C@O_tV z;Z(0i3e!f%rhz#y{cG|4rwL2O_1A!BaH!06;5S9MHhec=h3!9u=T&tdTM8vW+&k9AL;-bj#yigbBeL zfjum3NvC)-LUEBB2<4O1VDQKt%2c-mdMX={#=Y=z$O3auR^iXeQw0LcT{2CqX7#_i z^g=#~iY5H5+0}aq86kb|z1&{T7_O2-gQ)?CJ~7EX0BRRK0_bnG&-r7#>>MrFDqK)O ziev~(h+MH%_Ydh?U11jXwh?Ad2>R4hKw^Gx@dQ}w&w*Ve;qsAm zR~9sW`IY1u6%bKQ6(CoVCt5ZA_AAj_SnU6$5HEj+6cVQsXlP?M`xXhPKK4bkvm@ z_Gb26H2QBcNfsQ;SS7yJb_&3V=%?<#-U z0Awl8MESroFm{JZs=Jm!7i8F_9NG6do;n^7;r0}LXD?qL6Rq5Bqcfd&QZbVMZKL$~I=7%6&;m`rd9wmaWnFFM z^LPGGp|lo=$v{%J6p~VJ1-lWUNycHOdtR#&FXn+-=;6!V0FsvvkQXsr3*{<>3&bo~ z^8z(<1F!IfvH0C~ONW3b6o!6V+-#B*sgGatF2wHhJZ_ zBt&coS~9NSMC7Ziwe?J|3#E+!Ao(KRQwB*`l61y>5+;Tnbn_jO9#hQqk0Il0eNE5y z-gn|uEk>7vv2zM;6IKTzWPTA-79iXX1xD9r`@=%ePTV z$XDV_G4g>J))c?kCxH%5fuR?$rxKljMrj|>Q~xY^_SjNRtC|QlR(Mvg<20jz*Tsl= zvpT94Z++$CnWCRCy>4U8!?CsIjsIf&#Gm;IYRJ`%O;-(wPyl(t-fiAQ!C@sYlsom+ z8p*@`TSZfuZr|Jznnr*P2X@iA`1y}lMK*p{gUahb*QSOG7fSX+>yr#?9;C8FJOro5 zdVpXw+Y)4ByuaSlgQ?C3PY~<3N}5%F3D{MVuUxP7p2bABjp)7x9_yD}Smz;}>1@oj z8iW<}&&sba-cTdR%w8EGC`BTA2 zjV@OOkGeXb#_{H9b$ftSu1|LulnK>x91xv8Y4a_;8Gw}Pu-4+2G>EW-c;}XUR#trS z=jbx@>N|$*mw5NPA5KAu^EPP!*&jSQtxM!E#5UBdUSB<=k(mLCr{12H)J{TE)53>CyDy2>KnGN|2Py%{^dP!h^dy0X`|g(k z|2d9mgV>==_HergKuvyi&s4aSlq43jzyG0q>ZB{0S#S9?IxFYC5gKGU$24V2q3Z-> z=pv*vxs)sEL5R|&aijT&H@!Vie0+R+%nyB-H`$`*b(eWtyuR_;PV9Mvqk;be*;HI6Xkt^;XvD zpiMp7T|F4yuD*mU1y>DGH#g8W(0e=)t)0*GGm_9+a;eOqh)~pKyF4_qE^8K+D{Q(? z#~(ob)v4xi>l=UR8LSJ0FGKRY1jg6N5ZRwL2JYMS3M;0|-;HW?Fk}Q*PCmfyGs4)V zdVuLEIFUKV{~U^0z)6v+i3&ifRS+GF+{+R;;K_431JF4B2~2-DtCbe=P*doIT!CrZ zh+PFRlCT2-e4vdMj5sNj=ZwWfmJ~WR9T3o!V(z^cV$-c|K*Noqt#v0K<_O4Nx)$pu zdgc!4@dN2&0sxo%Gd5&j-6!b%GS~5WU8eB+c0Pf@yPRL~Az zR(>Lhg7E2@0R{D(ux3&Qn%Eu+b9{PHwI_|XJCH+xrH6I#^NRa3)d2$wn_Ni4!OLeK$Lzy zBbC>G!`lsKG^FFciw1OycH*(X%1*y#6RQ*G8$g9ir3Gf}?9P|e+T2ZaA=cXFe!1mz zyhdg7Sl%wI(c$^9DAwEV|7!1;8VbE=uImCc8mNomv(O~ZtlN-JeioIh9DHMB zb7rS)S6zP3vtGb}KUSuM0bP4*G99%Zn7jur6}(^H@mc}YA}vr_Gy2z11E3>C(4duR zXM1D_ScMZ**b_L|M-Xrexhvkf1 z%UC0^5yehz@r25$$_U2vku`agG01KL0!f>YeI2N=$2z`F(kRHZK#{OlaY)mY_GP%$ zxK0lZw40B6yjG%s#QrU*1vdrE8*N$Q?~gfaEJiD*4iBoJ)NP|)&gGo;Vx#E?Mx8tc ziJuU`YbQ$LuoHm3(Zew%T+?(Yze+FmLqy}po5Vfov}a?zA7AEPEbL2aNDQj%4Oyb* z$2=vn5{T6^o|`qh;5u%7XwtFe0|de8#eOA{9;-#P|Ezh+tfJrM{&K&@U@0jc?1xw3 z!Py#|i4>Se&9ldad(TQ-wlNM@afT0F`+f@QyiIevc9@^YwSdhMLgLi<5V)pUO88uK z=98n7N#S|hk{O(G20Z%D^|N$T$owrPtPdaqL)~DNiU;xZZQMNqza(2Gj6SrhTm?4r zRe;-T1*t9b4*auRMt$ZTE*p5A1cUM?=$|i!{&nf*Q*o6ymhvBI@@W~?1`s2IAly7%AqTsjFwL|{n8i+50;JgAgKkU zBPxHf#1yCkbpUGgZQg)M$czelM1UF{f#j*ze@!V0I}czOGP5t&>uukR@hmfD+BBl+ zO0>#P3A;xxQLBmHu_Zb3-z57X4)6r=>^x8W zU3Pc^dLR_mAiMu1Qt^9Y79^f6DpfWb33leVjeTbJO3^2W;y~H_}g8oGL$H$R62kwpA`HBa?## z!awz_ybsud(w?oYj>KbsWoYoPnQ~rUGm~{-3yFb1x2l4*bXVytB)BC_8T_;b;>`c| zS%BQKCj>lCS{op+j!nr}0X9E?dM+JFJRf?3%rd z^(V30qu|E^g` z#ERXeW$e&SorM3>lu^oSMX$ce7q%_q^@-~AOWta`P5s?2uw`zum9<)@+TsV&R<{&TVb??Ozu)e}fuf2%pVcgje$r%0v@;JY2XRw0Qb?2OUWJeR-AWT+r$EA@<7 z>S*Jyq1W&Y7Y7s~m6Pt#Ps&w2OYT&>KI^`0HMh=yW}mHk3!!IEP$bx5SW?kmny~y7 zP76`Hax7QzxY#i3BZpdra*y3ze9ZO=ucAGkU&R1_2(vZ9VF`CnjR>VvPiFvc4d;?4 z6@b;!o-G`6weybRfo8-~n0fs{1DGcHZ15u;F1W0R7${zTxM|CvuN**=f`Bj^*tPZa zVwPggi9Tf4hkf2S@)Czt_IR3Ew)AbW(IiK;w@bW?Am^&8Me9@~Hu30Zsw!+1F0l3( z13DOzTb8W67ARF4B+Me3Wk&i_YdigE>Z=tjOH+Nf!&D8zao!0k6#v&_dTG6&E~?6m zKkVE}I_!A0Qr_&NB#8a(-S#(@MfvBQJo%>Nn4|xBFQ$5)jX07=CC z{j3V^W;uLK-%3`-qxalWV`%*VS@z6@zngLNJFUm7wc(jH7{;op#vkkB7DjBg=)aFnbSYLqU)6-Ej; zXHeNCAerLXwbo4*O;Z*gc4&q3Q&gCC0=D_ri7zi0-;%62zA*?y#@`D;1-gc0KIH}zKKSmEoEx|Y>F$wsQ_Kr6O$?~RZ!=%c?HbuRn?+Iw;C z0;yBZEzB*9npm%D!(RRB0kv=LVTnGw0{FQvL*I&Zou1Y0#lVkIISTg&gCs42I2AvVlesk`e&vivB@)t!_ps@|)dZ$c zmp|HSHCi5>deHZ9a)BEhpKq0MuN{{FD1>^AHnNmO5`@;&YNnDeX17*SQ6tq9+con9 z(}t8K@LJX0UB;1Tphsg$1Sxi=Vjp+$$*Qyrr$+(&gS*-~^7NvPf8TC+AMOZv6Mu;) zqaWjnVi>xwo)iI!z}#+eWU5Ex>Na##5ux{rBUR`23GtxY&fljW_lOXUelFTjQuE5+ zTiBO$?rAi7H;SaU3(KQBLt8&mF6YjT(if`dPp4mGgq7p(hP_5`Wyh@KewGy3CK?K3 z(BCx82nuMhDhG-5pK(OIBOghO*tmwB=*6mnr7+_oiC8A4yE30*%DE9Cv(`1F_cI9=7Y*Hx z!%51$-U|O9iCJXruuMD9F&!E#FUL>7FxOf2g&NH1J;2uKWwCns_`*%L?EQ;AK$B2A znOEwjs0BwI&pSjv-H+1oEarO@B7f=AXl?-11K;QAZOpD?^3)V%f23hoLwR<#*^&S- zRlF;NQh&p9QVA+NZgA+#c`>)SsnRHVNz)m3)S#E9)whdI$iYthQljB(zQ4*$&WAP4 zmcnBqt8$w+YHj26w(Nl7u_k5@A`f9fWfW{@ENidNuTe448p);)!^(Sjk>ln^oeuO} zNNpAvcj%|7+M2}z9qHB9VC5Ae(~EuZK3|a+88D6fI+|f?d3fUfhA%d)~NLLP@-#MuvHTfY^s z(rXg`&gs29oWjq(3N;Crg)-o-T`W-LJ`dsiE|IfT07=2Rd5k{Q$$AsGt@of1N;5-& zmJd(s8s#0b8>-|xf!Ee*u;T42H{6PzK(~nE{^gpXA0>VmTao7MM_#s`waVQ}#(ByjOI`aVfGWOQwmPbJ^ja?e8!9^GS9sviQ z>emqr^J9DaFegf~W(F7{U!q^6xF%gT1x_V*YEym`_$O-Ye?Ro?&G1Z zMgO+d$;_h*Aq6sY>Mh1RwuQc}%52`d*u}P|)fs6lmyZv%!lD3WqN5Qjc_$Gv?6MON zOpb(Eh}zm`G0~H)?(Jsk~!CU7@BC8%X=eK7oUmkWt5oUYpO{gumM}mzTEO zEon=s70$~+X>)y*&R0zxEN0=YAoocxm|r%k{qsaoff+Ug;y%m~lpn~$Gu6|(PWo}L zoh;$pva3e`(H+)KZU732erIa(-7mLp3>Sr|=RbEYF0;Ic@%aW|(ud)w9fpa~r}%gL zG^sT}JLAesKwJc-+_ugDOta5>(tJ&gUt3nSHFZ|4!eq!L$-3Uah@wS(cenIfnK9no zdw-X6?kq4`ZCK*;(A}nUzQpFm3lE_e`f2?}oi{&i^L!{+eLj~#oqp&&;IBB;g&G)K z(J2oT{0psFh^uYkqI{+3)wBoN{0+drXSs3PAM8>eKku)@>88-6*4rnm?!P*6KtM<{ zbq30@C^6dwJWMZ2&`?u`0k!nm&>w*E(W|-#d-j(NGh)Nj`v-1KMHi z`;`DL`Qz0+{3xXlf)i$9rJ*_v(sJ3Ow%q?wL#AX}L0M5HbNb+NX!YwaggY$Fnp>Tr>bz z>bqH5)=w#qfBJ4_F9_6I*a9Dv|xL zMe0_OUT3x1?h^xIc?hM>EL0#{jnSc_lV$+G(|pA=!a<(~fbU5}1u(zRi~hF-(q|@+ z#RHck|K)kv!O6e%mNH+EX&2Q}7|pWZ6ziFs^m8wilahAvAL3a^ROhsJ4&{<-uvQ2Z zXy{#rkwm3ycn6daus52gCWO}d0bZhKZrLZzKVxlb3>u;Qm?B&}Cs<&Ek3!$eOosEY z-8gKR06G=HVss=Ll#h_?_YX&He_Qi@T3f_n57c;~nLSduf_(D8h0D{eRp_$dLps%9o|RSEDDW>EpA zz8nC+Np(k#RvZR=u}Hl$%-+~l&(m)eD6r5+4|R<)MC2$-ip<|?VFm3QRhTIOUTpwU zkB<`Vjfj8B?&T|?^%!oM>n6oCsJ7dH0f_MK&|ieyR`Lg&X(hh(A~y7h8caXXc3FAy zU1B;jce*-2Rel)Pz{uqe8E_07t@*|A1m%ax&y+(?to{>{2i2&K3}*0nblAp$3KRkV z3e0iw$*ulG;kz>(W}c_JidXjq+VE*Wo!9>#38|(l5%PD0^t68oVS5RJO?p$seh?cb z6mJL&X!AhFYGF8pcv!T0twlLy%&Nqj}K-D>IZ>^IGR^ZUI%rp$fs~EBJ{&#VV<1{Ms>xw`}_w-v+IB-Z??Uz zyms{ovF^%btg~$$Z@4bG_$KAMw%tdso&MKg9ZoS3;XVkXK8>C@wm*M)Uyyz)Cr$F5 zcP>9|tfbF7e#G&&(efPJoeUvhDXPGdcdx4qOM0h+y}6&D211u#Dc1jhq(dD*+Xu2x z^VB}Xa#&^ZQ+V(tXvZ_R+K2+O{WovGy8`^AGQ*v6J+pkx#ax)>4}bqr|L^V(-8C=$ zr9W-N{dbVT=yED^>;u&38ItoMDC&sA!&-3Ab!bcV3hk=iS1W(@Ak)H8>}@K|mNRbF zojTiP9#1?CD>A;P4LPcU^5T6lO6r)Gc`M z43iJ*R(EogB-T&+0CTCOR@aYvPGCS$sfYF^J&igo|EgB(tF=uNgH?M=!@)xr~_U%ZCqMSq7R>=~u~G)Y(gUij$W z*RAoAvByM%T7Xiu15V}eA{QJ!ou}`Gj{SeA!pItH174k!SQzDM1JD-pPJ8}G!?+h2 zJ@!Mc`=(BO6%;Gb@O;p=wP(pAE_1+O#LAZ76CwYm7Ft&O$jEqd;CIQw>)g)=>rn`5 zQFh%`pmoFoTF1@4Vd+vN5ipGg8Xpl2-ms%We8UzTv<@nu{#WBGlEbu`FF8Ctx?RV) zuNN1E>HHI7ebYi4k)SzykghDA&gotXo}8U5i58K2(-3iZ5KxA^hye|l`( zQf7S28f-a5BMDcm+>$FI6{qP7Myydb8Cf%ehW(5udy(9j{4RDMx!wh+jR5neIlz2o z4|SDEq&2f2d}R~QK$@_}wY(*edR~+>AsYM7n#uUhS%i*4BCh6x5pSP@c9m5ly`kfb z$>uLrXF-2eF6oh-Nv-BfH__8=Bl;ZoJ{a&Tq(p<@Gk=mp;#3*!gSoMx<=))DAV9hC zG>r;TB$KPzT7-9njus`gjsQ-1a_Ur+S-eim*E`IDCKJ1le6~s9Fay@dL~1|=gTkfG zRKxiR=n{`H7z~v@)FUCVn`$tp9f!Ah#HZ!fZKlKyD92|U3d zMh81JA9MPZ;>3oa1`Di(8x$8|0~?~dJZ_#QYQ=U)h}_6m%m?^_9D&1e0=T0SYGYWm zZLR#saxAG&pJQG+wf;Kuk}n^$cgIMec3j=)56`PYs)sGR>~9`A{i)Xi2E&H9n}Zh; zF_grfdhjKPzFLpxzfMG(gX#!p|It0pFoUK3p>mSlbm0HlawBwaOvq%5YbC#cI~vV{ zb>ni-Ty&@!d@xn0jH%+WScb8Vvy3_EOoHoBP<4I5y(su!4Ky%llnwO&+cPhGNQ|yk zgW9FeTXoJl-FtA7c7!~ZmT?OdSZ1;ds{DT9*$ciuazI$!hnDirs<+dbV~cNs%X-o; zIC>(0slX14H8pT9B1u(YROw?N10H`as}`X3elt6t;zJM4SHD>CfIIFTqi_r6{Sps# z9+uy|`I8fcOOc8aY7wzGfAzMtFCuxXq?@O%Vn#8R<0Ch$PywF}_VR*5?T^IkpQJyb zb^FSou*jCG}|&ZU@}!OkB4=$V7P=g6@3Wup}2n7%qI$*TH=J{ zaCwl{(t1>KW%Tc&XBF%#$>MVZQwUXDDeM-gQc-4Gn1BTm@XUa)&y-1NZ4MvGXxrfL zQi2?l+Jx$Nfvd76H3si};U$_)!58H6GPMLoX~TLCl3JGt_Wyi4(on3IMez(fLn`u% z^$Rc$!w{yl5wfZF*z=y2tWCk2vE&+$fO94iV>5=m=G+NsA@||mWcL{&KrWMYF%S)& z69rVU`t6BkV=qJvEEV&yaeXa=dRdF*>Xy}Or^QkkMXoj%53v678F(Xm4-urnOoxNb zpBB)PqhCD0)>walJt=}Ukf}Q@EdLOzXzqZz|nOj{Om|7XqO?YRztz0?;C?RDE^CGF(QAYAElWn4g zK@f1bHpZj#Ps3jQ?6FfpLdq`eLZWBsuz9&H1;HH}{o+?tiFvZS;T2V)g2T?lXW~xj znB#MY&Ie{&)Lc1Zlgb}o=lp0!jilZI$57o@A#G8oCoD*cBD3hQE$pCu3#5=0DlqfNN;FlvX=QgD zA(Tze>&mfXKv0uV!fRwtErl1v?A zm#Bqje?kqOXUYm#gV8$P#ykoa{UQw|C~qU4xHMvpAuVbOeH z(VtyBtL{g;0D?ko)fqvqvGs!yyhY7-HY*#Seh1a)b=^ig6Gpwzeq5sa!OK8b!PU5o zDLv8#@UblpfNlYQAo}nN;a0_Q2x5RrvKjv+LG`xHBY%Jjhr0ckd)x9lH%eLUqAGL$0N^;#{q+cM;#$p@0G_g|K7{p zRGX&daCVR~eF$-Vsj1G395D}#dY(J?V!G>ECcV-N6WPnffxUS5JXo`03S%ou>g@0+ zM~k&iKtnm%FSNQ){!t6#qmqJh-49)lGcbha5>l48yqC*Oeg5dbwGe(?P<(+O z^ia5gL^#oK1uPwr`nmjCU`1>EQ>xForqkS~kmwiPyc{jS1VEMeH%+Es1WD|GODY@@ z{ID^ZL!B54E8mr9kc3`^R}G-grQ!j`!5hik2Mnh{vT3iGWPxK0(_Bn%H1$@WVnH4* zK*UI2MlgN{4q{HTYrh2=+V_BZDnrt|v3oS);k*$0{mdZ3vF;OH(&)du|IDF<4_>to zL9b9X+T3^l?$RHaE6%)3miv169)UZ$9?=zin_RW3RU#;+ErIX1+oB|{;ylCeTXh3S z|2n0$EAEwY2h~?*hSg7a!PQc~9(*;-eEwK(M*WM}j`s=x7ma(+61ItQN+vMqFKUOl zkZ#$4zkBF!CNLm8QQ%i0$Uz{$ASrGD@jB*e%z%*2A@oj2uxiq-+&h2S0K{U}kd>i# z2^MB?y`1|42w$D- zcQ%Ug4nFdxG|vopEf0^dZruvXr~ZrVAy5X^iwX|?YO4w>2_V7}`FHzucms60Z^VA4 z)&_y`I7~yXCi7dj^4{gp-$e{V^;fXF1~Ab&9GEv-a?(bI1AARwJhfB6P5ko=+j}2L z)vhP_J~tIL55BZD4?w30xF7#W3*x&>I`9TyDOATg?U6wu>uiVHUUkdn$_ElYJs#`h ze*LByy(AY zswbJu6)1;m0MOS7ywLIa?~866^OF@LlyRJZHQ;4n(4cmg5a6((`}d}F?twTAL##l$ zZSMihBiCNq#N@lm_5`8n6>ufMxW;ryCJM9n3yRjiKVig))d?lZ%nKJ1G@dBfxCE9P zq#32@L*GZ0l1Hu)aDS`~y9{fYt86|ip3@dM-AOC1k=l@f8ae^qd5Hjq{^)E5M&JMa z^-Xr;haEIC38rTDq=T-6bxG!87e;NaI|-c35?h{c{ii_<850r-X(g%kr44}3Uf4s7 zsBaFuth;}ohIsG}bF^rh+;G=--c<}miZrQP>Q-PFh$)c<6`Rs2A&|`zUq)u zNbsbq5Zkhe$y8-E8h2%RZfMJFYfy~z;0^7DD`>F6iZgMy^pMliG_|8zB>m$zgX|;| z|5xu^F4iv{Y^kcx)RbQF)K4@m#kJV71F!g=b`EVop1Y2|Y70te=3Tr@fIM0sG~wZA z7{Nh|cX_;0hH0R^NqP$YdmDr!;>AVwty}x=zX{7%QEs$XGpeJII@iXN@>GM;@sXg5 zErC;buSNEttjcwc%Dm_t3U(*T81=u;0?4svf0N1&XJxK(%I4*#`2DGuFzH*3KIA*I z?Y8v?${z(5B+IBTAd}QrQg&>kjJIt*^Zm&?5_Z>1@r`$NT_eKpM6Z8rz_YsC;WoVK zs$jV)WFNkTF-59H`-m>S2*dd)XP6p;3TCC*7H9aP?|l4Le#kBT9Ut0tHctgUxVaFO zFZN>X`o)|q@cAX_dH&8jBd&bll{K`QQ(I^ebXA4VI}TDu3%q2;*HS>aloSUEgLq<& zoYHv@r~Q5hj<(*|^Doh(BmM=j-vc+igRH;Lmc4V!w1de~4VC;Wk_UK8+KteGOx)l1 z`seH=C{?TnH-iRGgE*$HcXqw&(@UT`_5?lorFSuqKI#2Kh0;vQZYY_;j>$_eM}4G$ zEZ(>58;4*e=YJs{w4WZH3Up8W;nL5Ctj)HT98pyd+1Bb?Z=ZNAVigye zz>-(O-|1c6^!#d@JeD~2LwO?Kl=43BZMUu8St=L4zk0A-H7y@Wa#IejOOnY#!&gGj zf{~5%6VSj5;(tOHMx0zt6s1nQ2xbDAr{Wq+Pl%DauoJQme~*d2boX1A?(sytFsalk z_$%RKS~^-O+II^=9*OrF59!F_lUkzhC1xFojDZ-KuUhbV{2Lls%fQCpvs9m5{fTti zTrUMrrBx)i>e}!oJKeUu8-@jMAeXyNyiJ%3y%ADp9;tiew_+5@zNmm0R^Rt7F+R6< ze-C72VQnLK7kl1pDX9v&O4<)%I0}FC5s@i(6!K#MGd(VBp-z+^a0`&~RIX z{&vQy#dPFct#5**33jIFJt8%Hp`%9~lZ%kf8+w{cCX*-fxxeA=h>TvhZnQjb!5?H3 zR5{oY`7|hA=VSCYT)&YxNtN=r(+Goo$eRVx>EcZjj^dbr zgY_VKwyQvjzSk*jRwa^D;uY0>MAmVRxB)+?H3&|-U1<-2uR8AdzmPv3HTEw1-Yuik0c%g$P;?HTht&W*I3d%4|Ik4GB*SEJ8lVzM|3%i}iLMI+2Qt`m#F6o<-j ztY+-9ZNT@3EuW9z&Ch}JhnUG<-Ep!zta52(HvCvY-ak?HrrVuVoV(PGu6;^c&|the zSr6_?8VTd*eBlT)Gk=Md<9iy~ETa8o#{a9W?+#}({QkB|TU1e7X^q-@C9&GlQc-Hp z))uu%BlhT^wOX4B+7hJ$5hFI$*h1AN#EROh4N7?*-|zeWuJ?Mc*FWUS^V~V^`<&1D zoX>qfC)@wdu20MSGN7_xnfF3s#$gegXuI&6US{j&SpoitPL(>4Y{{(Y{LD{p`&z}%gqB6v0Gw_s5}HO6=7 zD9f`qxyv(d*j7e>v6>c_Ga9DJ69^yH@}Nqz-MNZjbFJ~_EYDlXbt-BO)MGja9s+H>sPv1bV9 z4(45!q^Y0xKf$)$?w(6t4n1rbNmzeTqGVC|r1tbj(&q+K&Iuc8-9@xA>~Z5Xvo)#X zkBMH&y!B1C)}XA-ETZ+~r1ZMsM5%zk{5B%-9H`|!tWhj)XK#pSR_v2Ex=LhC47X=S zqEy6~S%`DAjeE$8t#S+P3UNReszlnoN$;M=qgS11@um*RU2&21MwOlFW;InxZgDvZ zQ+fTZRxzDJHVz}G9q{4P#?`#K(OE%=4e4W36RLh*cZvs5?CD7RQ43s#Xc|a_B)nvL zfKfJjA8>JdyRvSY1HmbgytGVyk@Vw_bW%}aH_%xGi)FiTNqIrz_9c1i0z#l4w6+#K zcHmV=0GX_ODd44ZWg5LfaWjd0;VJR0jE*n*8rN{^!_=Wt=i}|ONs+Rx|0iPtlNJHyn8}jLVavb9vO zfUbOT*#wpnaQ>ci#>8jkx5vEdYE){dfM)^XktsTrdw1pBw2sD6!w_EFDEW-q~bQ>0z>2# zb03z@o^upySWhOQKCgW`q+C6hcqr#Z>Nd!}5=po*`#FIA)Wt}O&}kul{}EC4gll}n zFI;|ATIhpwsYim^p)zBz9Q7Ii3=7Ks%Jw5%I3FL*pnh!bUfMSn`2`L5rGDd!rxB0^ zt{U%ct1Kn6J&5+Z^4GcYM)IIic>Y(}UctUF zIjt(-OZe-y@+Dt!pzj3B&sbDu2NACpwS|Af#R|>3H~hY+uB+kSzT=M`@rgo?~1eooooQi##vjd z;Wqrhz}Yf&s`mGfHAMJ%oZPC0P(X1$S_p+{b6D9{eZ~x|`33pZ;0-RQ4x+DC4+y3w zqdtvoPO|h|KRb*U29Wa%; zXNHyxD0E(DVw=8#;LM5UMPbdq)TlD@i0`UN&ny;vp270H~X{L!5-F4K$(noVD%V<09Kq#Yam}2Ez;v zu}SRJ`=c{Cm9@DFd@fhF@kBxxez}mKWz

    #bA~vU8(F9+P%1=ErIWOU>_{zfX8Y4dTahuw&;3J)&8Tvx+Fe_Pf>|`yyZQ|awWi53>nkY^s7qJD{9-j2W;Sf& z`t)|Hz)vR}<_qXYP-?-INcU0LIf7UW7EaA&s~OQMo7l4DSt+QOt6bcNN<6)CaJfQx z6(kgZcETwPw}nL$yZMp2d3SD<+~q_|S1;YKK`XgI6`H;87Vu2PX!=_!Bab-xi6{9$ zW2ICKYw*@Li)OtuM*$|vMPY{d_oCHshUDS{*jub}vGLbG9gnFuK!W(g9?J3o@YKdn zoO<_d68}4uyq&P<3@81u-9w7`_Y{}wtQFU@TqgT+8W{l%UjGV!F>Q02pqvtTm&o@6 z51g|~`Q8NQZiJ(p5*bnC?SCHw>ngu8llsS{{f(v4iNj_80LYp)b=f+RV0*RH0=6Y#K zxC2kUG@s44FxV1rFb83U+(@(hH%BQ1l(z%TRXbSg<=0kaQU%%i-4l@nBJG{8m>ACK z9!_*sS~0*~;Z+IQ&c4pj>A`z*(9r`vO;Q?n|LDNE72lQ- z8cX^HoPo}mS=abW?BY7#KaSIXPGL9B)}b&TeVd*vMN}Jo8euwjdsTW6g}&wEBT%Fi zDPY9X;fqXO$%f5J7eCuE)Z%#&ioSHXHwN3cKt_R`G8ai@8oT92QLBYIn< zIZCLl^J#R|Q9{}`_J$R22gj)!4dozPaOcTT>W;&*al{8Ve%&5JO=zJtu4gS~qU<`( z_MLM#(YA8tEhCOGn}@FPGvGE*1%)ttcTKgDTNXlj!mclSgV5iqy_Bl)mhkrzIdPzk zSRC3?O<;&O>9=Eh6&;T@=|gq@Xnn$nQvs&*G3HTvrRZ8Y6n0puK1<&`GSwTZMDS##11HQ!kGkjc_&_F`1dpn zfb2BRUU+-8&u+cm--9pe4%7nv*~E;>h7VnVf5O+!S<*<^VIzYHHtYWG-*E3l7qpq@ zdX__NnnF{WF5hYPd@$D8Undgb)XKmUEOV#Ga2Tu1yI@VSI>gpM5edX0>XpP67pP#1 zGHw`k`fFq9stJcdd$rnx;8|9LH}R7O7dw>b^OBNi)4pYW*{i*ihhbZKE!(Iv_yDCp z0VJv?*Z|*n$a6z#v6WjI@#xV%T3GEx2Y)TvV<9H6`(b#4*s8rS4@9CdBu~)s`p4WK zY_V0vO3getHe98Wo3UPQ)l(235u^^#l`}75T@*tKu27$mShH(4^xDzb=4)9CNHWU3 z1Dtn1{GBNydhY+CFH2%C{OFr6Y82m_lT(Dz`rq^#W%&b!g*s>^-UCzlZdDY%#aDY zVaGq|Pqo%mDWfR#D&TnKkYg8xeS}M-RT?4-Vpdv330AC4f_Lq=W(Nf6rHw4swcCy! zF-NW%g*j_SPHRnhHjnw20C>vqjgbED;aM=;Zub|K2aOu0HGEEqJFe(z z@KwjxUhCaFK6EAG`SGhjyc<36*=$VyMV+*#M z6JHA8#S%@}7a%HOM1s?1<5*t*=5dzFwyTWsMF*|fO@#%8IIszf^%Wxrv|Zzv#*dEo z{2?$`u20#H&zA_U+)$fNoDJ&3&ZdJ$o>x_e45D_Ff<^-525G`EwOI?0+;x}zo z=}-fZpkL83WC!Gf<9NRq!w&xsC3=l)SV`P6i*Gb*b7C+1ld0Qt2R|eq6CmC6 zgS@Hq6#R!K_L>ShZ55lfh#QP{VH!5W9Vj;-QS}?3_!h78^@E(|Bxi-sVBwwfWA10d zG1{Y(b4vm2+_SLf77av&)Z=SU_3zlF?g;-Rp0EpMcO6~!*R@K^8`B!A(c}O6Ng6sq zJiIr@Fc&WLJdb;fT(hGOAC-f`{+0X?mP(*mbRtxTcIx0NbtC}E$-># zW5uQp2fNMnLYul)0ou)<0I-CVSo3zwbq%UGluja40~ofK-;aSs{Og6{l|Mb{*uMw3 z3Eebf_+TPDGz?rO<;M4cVCe-RPZj1#*g@7*XGro~IEI6}4uY@IO3jtvg=cBSSvUpI zvE?%1y~r<{p^eTvY2kDo^gl)XQYuU8gzwx~n694L9*e%}jvD>p%Asj4>;i=yueHKL z0xFSPzu#Cbv1q@xUt`wN%v!W330-3d_X+J%lN5EZubLqpQCOsJy`fJIT(|{)qbk>pm0X3-Ly4oiK!Hg=^Vmp`(0k*@)JuH7@6Mi8AEikjS^{Sn(N6g9M=4=}NOeBDo4AjwIn za6omyel!BsON~zLPYu<09q<4?dwyA>g?N85- zS_alW8RhZ@=l8c}aJO6tT&>g0+fhqb9`{I0 zYUPt!(br6|EpmQ*{#m>K=4(itVcs*pWll%vr83zmqrE$(kY0C`pv&|Yfi>@bjmJcH zv2){XnMccU;Kl@2Ew27wo#Pu7z3*Nh3&Im)x=F|?*W;!o0>7$1mPanQ_0`f$tv>3P z2ktshaQk+g1BkQ$B2yHa$=}^dlcRX=Wb}1^O+)0MSOl#oMzxixF)Dr)yC?b+aIG zi?FO!GcH850VX(Ui$yt>V+iZ&&KM)7msiL+?q?a3v4xBwHpG%J0^>X1FHoZ%5F)ZB z33=+TKhWtV0Or)rd>vHZy;AvI{8XSVtoL7}9a)e%xov&HjTpd`{;3K2#{`pZl|_ zlb0{`mmXl!m#@cBvp8C=x5*0$39->iX72WZ`lMW&Q-KT2F9ACS^yNxAUbDcfE@+8$ z4;)0dJXZogyW7nKLx;k4@6%A)%%xwQyNY{(4$? zQ%XaVGivf|KT=LimwdO(&_lcWe||!s(dy-RM_97n2ZHHE_t>KYmR-J;fM;VI^9WGvFKxSs0%YwdIYa<>rq4yz2b;fMJiccK%rCB(uEY7aywrv$o%O(ep>zI1@Jua6z^=bZ)N@PD%4Y*O z4aN~R663zVRMjg-fN9TrOE^Y?we zbdIuB@2~o7v0pt&oIfr2o)s_JO1h~gkO1j)Ws0oO`>~QuSiV}SPcXh(5 z%4_xN{ce*mE*?P+=qCL-%SaRr(K(XUxY}83SnsW|!sK!C53)r1E|~dhY<5>gXRx4{ zna)Op^YF}_4mk>bh=*^2!NdOmK5TQN@QUCU7a#1nLyL~KBg2+MsbCFz#MM90hQ{HU zk9X0v`?rsNoPs4jjvH@Z`U{Gt3$`X|LffNWalR!%e)wD>ZhEw2i|wN2m8Z6^zr0<0 zKjZxXyl7ct)c@Z5PUa>*Oz}K;^zU=a>it)rt0-ENTCsi~2Ysq%W<*0JGgBL5FBiWU zA!6z9#=rOnmR=dLT^;z|x3k_d&hou9lwkG;=X{@Bo&77~bH?P+cZ!Kefl2K?rbfkL ztF9{;AIY7}&p@Sqdelxa1S(5i-J;#^&9H8gN-%<@4R7-P@M6ZXRHZE(TJ@=#Xzt~k zGG{K`=JhEe5Xo<`#^6&;&h)VGYA79@7HY>gTYn2y+14FaI2%S0A4y1UkEA!go2LW3 zmNZ*W5LKceTwtEaVY*sfm?mr5^bC`5qc3LLniO$9W zF&Q6Ng)EiD$Y$D(9rf8K|JAil!4DDDk(-Uad*ptTWpT#Y(=My$dUD}*^JQLJi``)b zGTlax_VdSrg?Pqkb3gqp>NW}7-w>UA@&yTO;=lVe? zEYs6=>PGq0P$vw~N`i1$oRXUqw9Xi*%7C7`n~}nCS)mR>LZ<4@M6By|C56D*L#hG2 zJkd*U#}27E154W&-Bt=Yhkxh<||KO6jvv8jMDMlTvj z_Px4!UT@C*CK>L11hX9=hC|L=5dYT$^e*LrCe%zc@6WlUr0Io@L$dV7#?mjsMagt3 zcVdrbYqI?C1JuixSHwm&q4Y^*`RIFgjRY3xbNkq|ZwF529jx;!WlWZN@7d+PSV=sc zBw4=`{vTt&eg5OTh-6Ph=;*%p`MOpeS(?Z#!co0x5PZ0Dwc63{)kOmKS1OFX0X|MUs|DpkV=+L(gDi3 z0r2ei99sJfWx}a%nkEmTEa1XQTgmL>#&bAfKza}|otS?peM=ay+Zhnd!WbHGpk);8 zwA*#DCw;ZR4u%TrLy1i&EM%0{z0modu5QQWEhmtNGN56SefxQ|g?}wPf*a8i3J`o- zC8M`5Tx)SY%40IzTEYFUooV;MxegU|ol9E=6FqOG)1%8+cEm_>Wf_fk zbX}P+8#V^yl7VwKpIR3fR;w(Ocef2)Hfo=^!tLiU>Wb9M`@GnP@|{h5oLUPw0q2zS zE4q99=ND|GtN&Z525!sUEN`DL3#n0DwO?|*`?|f?PvLHze<#`8-4<)dGGZfwS+U}MVV z{pU$6NVNC;?--%l#_pOTrREXT!UK$mkWk@EKg<;-ruL91pM7Z+SokG>uzv;EVXD1u zarbbP3sH8l50jQ%8xKK^JwP7?a~T+Z6sCf9_5T4>AS^8{Aar( z3RC5p)S{3@%4I@vQzSnxJWU2ubcgFcwZ*6TctI9k8z)!(rJ`bJJo}CS=RSJXyLoy* zS}+Fw8F(u9-0Gdo1PFiy`F}L|Zp)reI`#5bqu$!k=#FGXlt~URoDBWU2MGK2!A@iS z*?xm$I^b5Z)>oh~_XtZ;_>hyai{k+^sOOp??AVkFUK}@gneMo>uv<1sesg?UCU33~ z#xvj-Bq$n&;*3RCOATeTnm-8gkZ=7u% zBvUoNX&G-7cf;!B<%VYJ>WbXO58bK_WT*Z3m%HEh*;a)flQEN{u>BRUh%Bln_Qlx1TK9> z2n4D+#Za~u^P`ew+!BG%;P6b(QLkRYqB0l_Qgkg$(O);L|?*U+$|6XPtxWF5=vKK@uBcx|MQS^f>94+3i4=8pLZr%i| zQOaiH;tX)%~_2#$K};24zz z0_-+_X^rCZ6?q?k1`9G8DASFhc52yn3y)nlBNORpb)t;br>Uony4;Nifga47kK&mW zwXWX(;?W&gGX)h3OL(c@2qZfQF8_~R&`x3UA?263Ul?$}VwNPvt*+op@5`VX*Fj#o zUu^MSDkJB}R=bxi{Kl#{;4k1uHBa}EEk{J;xm(+Z;@{Gz%IceVSC5dt@BaxZFy2&a z4@dfjo?gsy_=nc($dM$ft zQ;-;SisOG%4SQ8HMb%iZJ0;Na)vlI}uFcc2r{$U#w%?o(rZ!?Q@t>PY+Wq|^*6ez7 zbPT-LM!%jBV?%_vp50~EQc;WsuhAK&ww44USy%VsfAWctX>`0OE0Bt4{!@0oyz=gh zMd%hq$3JR2dZTkGq<)~4rTB|AWbuv82?h2G z0h~gLByO*LoVPmGKjLq+Hymiwx6x~`H_S{CP#W@5need`uFm&XZtDsO|> zx!9;urbn_t2ejM>kn69kTMA9Ig&WxHBbF%p_fs8;la~iP%12ylY?6lEZ)Bk}C!fC5 zM@x01&=@UT-0Y+E?R)PX{=TST#b%?_#Ieh zh|jWp@36j3Z`M=Nl&qscxy804D}xlaWjV8I9su+>-FRYi`*g?V#+ZHme$5tc)N<=! znFX~Zo=oX7M?88FD(D%(t>;sG5HTEjws22WkK-v6%AL)VXFwlw@m>8_u2`GCbr+y( z`RC%$DNm&lbh^(i-6Bql^$+QQ?jV%$?!y4HRq4h4q#ypT5_Ns<>K28TTEC@=sOt_c z?FS-6j=3F>82)Fi0fpi0wsR%cY=9?7I1XQ!neeVbfs5!%fUEUoLV -STM MATLAB Simulator: F:/Work/Projects/MATLAB/matlab_stm_emulate/MCU_STM32F4xx_Matlab/Drivers/STM32F4xx_SIMULINK/stm32f4xx_matlab_gpio.h Source File +STM MATLAB Simulator: F:/Work/Projects/MATLAB/matlab_stm_emulate/MCU_STM32F4xx_Matlab/STM32F4xx_SIMULINK/stm32f4xx_matlab_gpio.h Source File @@ -14,6 +14,7 @@ + @@ -76,29 +77,48 @@ $(function() { codefold.init(0); });

    stm32f4xx_matlab_gpio.h
    -Go to the documentation of this file.
    1#ifndef _MATLAB_GPIO_H_
    -
    2#define _MATLAB_GPIO_H_
    -
    3
    -
    4#include "stm32f4xx_hal.h"
    -
    5#include "simstruc.h"
    -
    6#include "mcu_wrapper_conf.h"
    -
    7
    -
    16/* Ð¤ÑƒÐ½ÐºÑ†Ð¸Ñ Ð´Ð»Ñ Ð·Ð°Ð¿Ð¸Ñи диÑкретных выходов S-Function из GPIO */
    -
    17void SFUNC_to_GPIO(real_T* disc);
    -
    18/* Ð¤ÑƒÐ½ÐºÑ†Ð¸Ñ Ð´Ð»Ñ ÑÑ‡Ð¸Ñ‚Ñ‹Ð²Ð°Ð½Ð¸Ñ Ð²Ñ…Ð¾Ð´Ð¾Ð² S-Function в МК */
    -
    19void GPIO_to_SFUNC(real_T* in);
    -
    20
    -
    24#endif // _MATLAB_GPIO_H_
    -
    GPIO_to_SFUNC
    void GPIO_to_SFUNC(real_T *in)
    Write S-Function disc ports from MCU GPIOs.
    Definition stm32f4xx_matlab_gpio.c:10
    -
    SFUNC_to_GPIO
    void SFUNC_to_GPIO(real_T *disc)
    Write S-Function inputs to MCU.
    Definition stm32f4xx_matlab_gpio.c:37
    -
    mcu_wrapper_conf.h
    +Go to the documentation of this file.
    1/**
    +
    2**************************************************************************
    +
    3* @file stm32f4xx_matlab_gpio.h
    +
    4* @brief Заголовочный файл Ð´Ð»Ñ ÑимулÑтора портов.
    +
    5**************************************************************************
    +
    6@details
    +
    7Данный файл Ñодержит объÑÐ²Ð»ÐµÐ½Ð¸Ñ Ð²ÑÑкого Ð´Ð»Ñ ÑимулÑции портов STM32F407xx.
    +
    8**************************************************************************/
    +
    9#ifndef _MATLAB_GPIO_H_
    +
    10#define _MATLAB_GPIO_H_
    +
    11
    +
    12#include "stm32f4xx_hal.h"
    +
    13#include "simstruc.h"
    +
    14#include "mcu_wrapper_conf.h"
    +
    15
    +
    16/**
    +
    17 * @addtogroup GPIO_SIMULATOR GPIO Simulator
    +
    18 * @ingroup MAIN_SIMULATOR
    +
    19 * @brief СимулÑтор Ð´Ð»Ñ Ð¿Ð¾Ñ€Ñ‚Ð¾Ð² ввода-вывода
    +
    20 * @details ОпределÑет взаимодейÑтвие портов МК и оболочки (S-Function)
    +
    21 * @{
    +
    22 */
    +
    23
    +
    24/* Ð¤ÑƒÐ½ÐºÑ†Ð¸Ñ Ð´Ð»Ñ Ð·Ð°Ð¿Ð¸Ñи буфера выходов S-Function из GPIO */
    +
    25void SFUNC_to_GPIO(real_T* out_buff);
    +
    26/* Ð¤ÑƒÐ½ÐºÑ†Ð¸Ñ Ð´Ð»Ñ ÑÑ‡Ð¸Ñ‚Ñ‹Ð²Ð°Ð½Ð¸Ñ Ð²Ñ…Ð¾Ð´Ð¾Ð² S-Function в МК */
    +
    27void GPIO_to_SFUNC(real_T* in);
    +
    28
    +
    29/** GPIO_SIMULATOR
    +
    30 * @}
    +
    31 */
    +
    32#endif // _MATLAB_GPIO_H_
    +
    SFUNC_to_GPIO
    void SFUNC_to_GPIO(real_T *out_buff)
    Считывание входов S-Function в МК.
    Definition stm32f4xx_matlab_gpio.c:49
    +
    GPIO_to_SFUNC
    void GPIO_to_SFUNC(real_T *in)
    ЗапиÑÑŒ буфера выходов S-Function из GPIO.
    Definition stm32f4xx_matlab_gpio.c:20
    +
    mcu_wrapper_conf.h
    Заголовочный файл Ð´Ð»Ñ Ð¾Ð±Ð¾Ð»Ð¾Ñ‡ÐºÐ¸ МК.
    diff --git a/DOCS/html/stm32f4xx__matlab__rcc_8c.html b/DOCS/html/stm32f4xx__matlab__rcc_8c.html index 52c4b72..56b75c2 100644 --- a/DOCS/html/stm32f4xx__matlab__rcc_8c.html +++ b/DOCS/html/stm32f4xx__matlab__rcc_8c.html @@ -5,7 +5,7 @@ -STM MATLAB Simulator: F:/Work/Projects/MATLAB/matlab_stm_emulate/MCU_STM32F4xx_Matlab/Drivers/STM32F4xx_SIMULINK/stm32f4xx_matlab_rcc.c File Reference +STM MATLAB Simulator: F:/Work/Projects/MATLAB/matlab_stm_emulate/MCU_STM32F4xx_Matlab/STM32F4xx_SIMULINK/stm32f4xx_matlab_rcc.c File Reference @@ -14,6 +14,7 @@ + @@ -71,13 +72,15 @@ $(function() {
    stm32f4xx_matlab_rcc.c File Reference
    + +

    Go to the source code of this file.

    diff --git a/DOCS/html/dir_000001_000003.html b/DOCS/html/stm32f4xx__matlab__rcc_8c_source.html similarity index 60% rename from DOCS/html/dir_000001_000003.html rename to DOCS/html/stm32f4xx__matlab__rcc_8c_source.html index bf34aaa..10a1a25 100644 --- a/DOCS/html/dir_000001_000003.html +++ b/DOCS/html/stm32f4xx__matlab__rcc_8c_source.html @@ -5,7 +5,7 @@ -STM MATLAB Simulator: F:/Work/Projects/MATLAB/matlab_stm_emulate/MCU_STM32F4xx_Matlab/Drivers -> MCU_Wrapper Relation +STM MATLAB Simulator: F:/Work/Projects/MATLAB/matlab_stm_emulate/MCU_STM32F4xx_Matlab/STM32F4xx_SIMULINK/stm32f4xx_matlab_rcc.c Source File @@ -14,6 +14,7 @@ + @@ -48,6 +49,11 @@ $(function() { /* @license-end */ + +
    +
    stm32f4xx_matlab_rcc.c
    +
    -

    Drivers → MCU_Wrapper Relation

    File in MCU_STM32F4xx_Matlab/DriversIncludes file in MCU_Wrapper
    STM32F4xx_SIMULINK / stm32f4xx_matlab_gpio.hmcu_wrapper_conf.h
    STM32F4xx_SIMULINK / stm32f4xx_matlab_rcc.hmcu_wrapper_conf.h
    STM32F4xx_SIMULINK / stm32f4xx_matlab_tim.hmcu_wrapper_conf.h
    +Go to the documentation of this file.
    1/*
    +
    2**************************************************************************
    +
    3* @file stm32f4xx_matlab_rcc.c
    +
    4* @brief Èñõîäíûé êîä ñèìóëÿòîðà êëîêà.
    +
    5**************************************************************************
    +
    6@details
    +
    7Äàííûé ôàéë ñîäåðæèò ôóíêöèè äëÿ ñèìóëÿöèè êëîêà STM32F407xx.
    +
    8**************************************************************************/
    +
    Generated by doxygen 1.10.0 diff --git a/DOCS/html/stm32f4xx__matlab__rcc_8h.html b/DOCS/html/stm32f4xx__matlab__rcc_8h.html index 7e87d74..c0c10a4 100644 --- a/DOCS/html/stm32f4xx__matlab__rcc_8h.html +++ b/DOCS/html/stm32f4xx__matlab__rcc_8h.html @@ -5,7 +5,7 @@ -STM MATLAB Simulator: F:/Work/Projects/MATLAB/matlab_stm_emulate/MCU_STM32F4xx_Matlab/Drivers/STM32F4xx_SIMULINK/stm32f4xx_matlab_rcc.h File Reference +STM MATLAB Simulator: F:/Work/Projects/MATLAB/matlab_stm_emulate/MCU_STM32F4xx_Matlab/STM32F4xx_SIMULINK/stm32f4xx_matlab_rcc.h File Reference @@ -14,6 +14,7 @@ + @@ -71,7 +72,7 @@ $(function() {
    @@ -80,36 +81,39 @@ $(function() {
    stm32f4xx_matlab_rcc.h File Reference
    + +

    Заголовочный файл Ð´Ð»Ñ ÑимулÑтора клока. +More...

    #include "mcu_wrapper_conf.h"
    + Include dependency graph for stm32f4xx_matlab_rcc.h:
    @@ -117,30 +121,30 @@ $(function() {
    @@ -167,7 +171,12 @@ Macros #define Clear_Flag_If_Its_Expected(_flag_, _condition_)   if(_condition_) _RCC_SET_FLAG(_flag_)   -
    +

    Detailed Description

    +

    Заголовочный файл Ð´Ð»Ñ ÑимулÑтора клока.

    +

    Данный файл Ñодержит объÑÐ²Ð»ÐµÐ½Ð¸Ñ Ð²ÑÑкого Ð´Ð»Ñ ÑимулÑции клока STM32F407xx.

    + +

    Definition in file stm32f4xx_matlab_rcc.h.

    +
    Generated by doxygen 1.10.0 diff --git a/DOCS/html/stm32f4xx__matlab__rcc_8h__dep__incl.map b/DOCS/html/stm32f4xx__matlab__rcc_8h__dep__incl.map index ef290e8..b6e5b55 100644 --- a/DOCS/html/stm32f4xx__matlab__rcc_8h__dep__incl.map +++ b/DOCS/html/stm32f4xx__matlab__rcc_8h__dep__incl.map @@ -1,24 +1,24 @@ - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + diff --git a/DOCS/html/stm32f4xx__matlab__rcc_8h__dep__incl.md5 b/DOCS/html/stm32f4xx__matlab__rcc_8h__dep__incl.md5 index 0ba8904..048af80 100644 --- a/DOCS/html/stm32f4xx__matlab__rcc_8h__dep__incl.md5 +++ b/DOCS/html/stm32f4xx__matlab__rcc_8h__dep__incl.md5 @@ -1 +1 @@ -a91160b3158a19d150fe35619e34be93 \ No newline at end of file +b262fec234532d9c8ea1e105337df25d \ No newline at end of file diff --git a/DOCS/html/stm32f4xx__matlab__rcc_8h__dep__incl.png b/DOCS/html/stm32f4xx__matlab__rcc_8h__dep__incl.png index 123b969abf73082ef78e6365478c47e277310708..cd8915b14540514bc60309dc9641c0c76344836e 100644 GIT binary patch literal 32995 zcmZ^~c_38n`#-Kdl{QHcD*K)-8Cf0*!`Qd%WnV%V)L1K82pL<*mNAwx9y_C4qhT*z21l$e z^@h4DA3hY1DTz2v%;yp=x$!XYC-LB|%kM3UV*2V#z7F2r%YQA;);E@hl3H21Q;_<> zJv8M2uP^5*;pbhCv{N6Ns@%>0j(Mv0T%zPV;&M}1RGvmv{0G+_RfU!?_pu84&|&ul z@=WsqnXkr?E#rD%QU9+?!J}Xgo91hqy4!=L1qy5>Mi-O6My^d|_#e&L16F<%rgeZV z+RDX!iwm|Vns&_;S%eWT2m-Tx+*Ndft?&Iyl_15il{umuo5fA~K>1Lmi|*_haJw@3 zAm6|5T+;U1yZz5-H4~m)+yAv^Zy@)j5*52Ht)CgYwF&3%b#DJ zoiLg4$j%JeirEckikN8IRECoyGoov9i1|E1qZQ}0pdiDr$7rZ$2QJorRf^9M027w% z2NQqPl#XhYt!I=xwmoIp+GAOoss2#kAS=9Ay#5c3x!Uj*FgW@nLy^r>pX{bt zc|tulu~awF>WlX(5CB`(UT7No#v+rVnU|aGq2%75Gw&9y;X|VamCKVI z)*Yr&U~Bmfm()1eoX^+4_$(t#Q-hWC(ajcnCt3ZDO)rBcvpXyonC>X2+Fbq{J&nt0 zH&gAv8(y&M3$i`ApDAUO<8bkm1h<6vr4H$5WzsS<2Um;0&A>w#?>v{nN-QKM?*!68 zHWLeBa}v$Qq|Z6aaRFIvo4B`Q(`RK}fuN(-%K-+Rg5)h$MyiOd2u-xjElyvxXs>_M zN*w|BG%rZSaIhI-UW!{xy>+TMmtgkhQmMOL>ALvJxp+Ri_WEJVEFbI)gl7F)7-;9^ zhqJtkJ^KrzC6o;+H}rD^$6>}rIBu=-=1dv8mkY z7w9S!Y}_8jTdIc4H3YWCaT#cN01-XegDw6q5Fm{Auzl=cC`#&_g?_qa3gF=!TXhip z`^ka-4Et|b`S=mh5=gL`0ef>d@12p0STLh}u8#m%>D@>TL#R-8gQu}zCe8RbbCu)8 zQcQVr*c;5GO>=mo3;@$ix8(`)qY* z0hrX>GWLO=0Mvp)915}4=g14^c9+vGL^j3DoyUEstr9svxBh(a^U>4>}!1n`%oM&N2rzw z5?6T$>Bhnomz)dWzM=xalBe?;RYJ+!r}&8JqJct*(D!qhGH)OVU4mY7BSg*w4maru7+kl?5*`m=ib;7Z z3FAg8-c(H9qXgj{8)uFxxg7_?%isS`0PHfkUv5|L-ImB_jk{6l44;((0|VXxJ=?zK z?o++kqN`42H(OSC8DGFbySu3jRw6DhZ0bwles?k#`IStS4M=@UBF{8x6@qXG1S+0Oqu*PW2k65-s9dF4#y>r`hSUiA4 zVp7!d%{WP@ePH&-tC3`lMnRXjc{_yg>f7)&0Ia|Y%ekzz#LjvGPxvP=)4>F=$Kx)I z*EIzXMSE9R-&T9+Tvednf24gml zdlz5pcah-AlLM3ec%TH}{OLzsvw>2}SC0w~3(uVVxi50DIGYNOWHr8WQmJkKxs1iD z0i?L?2g*L^0RRcM>L61k4wvzVJyWm0MLUHlh8`OU^XRMRYbsF09uM;C7~W+4eTn#l=;XplQ#Q zxxs=$wvu-P<#x3$ZHbcBZ*EiyAx{Gpx^mM{5Ud|u+dw&PQdxWF#VhkO+Xk*g1K{M~ zlLv*ctIA+R{^pBZ$Y4R5_um}M@gU$c#wSEW!zw9jJ=Wgi`aL!a&CDwv<*BIV*g7}= z-qpxz3FWYn1v$Ta;PEUzAE1fPq@9|tF0#~O$7E+3bi~ps_}d14HBeXMd?iD=-6dt+ zf8B!&MKGj_CPCy_gChMjMW)Hz$SH9!ho=X0Br*DFXV>(z8De#PHU#4$5CH+HKQqNA)vJ`4KgaMxnDUgeRTb*jFj@1bn8Gz zuo{a;V3E!;PL-x!r6*>bat#vhWVSOZN9Lz;Uk~`e`^_6yZ}{T$^8%!M>^ghTfhYP4 z6?aFAkZuc#Nt|sp>rsn6ch553!*TAO;;WI@Aswg931H9==eD3~S+evstY=yfVx^`` zN36K3y}sF`fSGuxeAv7SNe9#8*+j(vatc?nCQ(~UytZ{sgk7@ z7BVZwCh>PL-D>`8R0N`=^n!69iZC_#eijX6MY}bv0ylk{@Uvvff6ZurN z+Sp9)d*t2|L4uel`bGf|3s2ChWM25McB0%+ZtqYrIYdo~AEtZV5%oL%6(#4_qmQeb zi_$z%A@azVA*p&omml|RPs~Ph9o%nRq_CMuRFMdtMnwg{CX$$mEYWQ@%XWi&kd0`D zQrLX2XX{TIAlgXO1}3X{V-ItZbbHS+A8OA46l;cob78BAxoCO z4>MQdkFs|PqmD|?nml&kfJWKzT7#jAdd zdj-p2dHE5LFVC`FWJY=hA~etpE5oSw4}ChnUG>3T|GWA~(OipAgvNK4*0x*lbOK5f zjjg@imsA@t>PI>U&p}U;8cur0`oCix2qh3gAGRnXAx~2y3b_b#egB^=iT2}ZrNhO# zXW&(%TfR+#H*2!aEK~}>S&!gOS3(J)u{{8I(JN3eV4zHM$DNm(aaIqd9Bj5dH%=pLMkt}8ho5)K> z8U@-%U2gaq$qj>IpP>VSz%>~bXiRKLs$jdPS(04qi`JMh+oDTo3{J*Dj5=7NEpQA% z8QXj;K*#YgkK4ZpB1Lo|KC1a)M{c4-{7sD+^x8@)CaHTzQti zYMUzKD4e^gy*o8jC^@r>u*Utqhxw7yR-DQ$A8`?~m;a77Z}_oyedA72PWJOeG+k7t z(IA(Q)C7CGuUSQ!GGy*cLgb~={aKfP)Binv2&9T>1*xOo;nK?OhA3OoN5D0$> ze0MU0=Tmcr&Bo&;8mT?MZ#K^_3NSMiVdjO*1l9xOCp9&i|BfKb6Otjk$X&)B9$`KZ zBdx8~Ii*+W^5m3$d1MxngIVlgW)f|nMGrxNgW-joC2Ke98NmApU zW#5a)+$)#J`$W3!>P$srdw{k_4}8os+Rf(d+s>2MKU&@-v~jngZ4(B@QF)pEa8&jA=pWEWNf>n=n88Q`BOtUp;-@q!bVo1LAOU`**)1N(Wc0eT zMt;IqUK8*AaKGZV<%?Z>L3O$@4B4An9RTtt(#Erg1J&f^44jVS2;;)d^3sv6<2pIV zVTYkT9tL|npN>-gZ6};l7Ng$a-8_FJM-=yndoW4ZVG$Q~bQ_}O+YnVX7`RJ9a2wzw zuei~*W}d2MY+923xD`g;-dPsk_Ohr812$+!Ixa}t!)w2wT3vh5qHd4#ckr?jJ_x&S zFbe8+q-cz6l2pz5?lvzTcf1Mdhuhga-klXencsOonN-DQ1=5Vx0WXmcqBI`(st)OZ zHk2r6`atOXsDmQ3n3`2&tG`7htDS%uo67|?%Ak=$XDO__M~RS%Peb9|lLMjVTHK9{ z56PTNCNUuE%cLVK3e8W~o82g=2209c+dja8P>W(X%!oZlRN+`o@mWZ_9C(oAL4$$c zV>`#v2#tF{-$-2aA+=;FUI}~!%%QPDwj2Hisd;piHM|3?5eQiC2c;tHNn=j~HVkH^ zx)-Wa)qaqaKR);h-uL1HBmxtU+YF5qs=Y#v#lmas-=#;(`L%Fqe4tU%5je8Bdvi-?$gnTqtL?|N7;W!cdrDD10SdD$(g zl`nmJIm_G>@&3FWOQ z@|o4&Zk_3#w{PE$$H?mo#*@x&J-R5Jw!S96y#E?7d73G}{~rH{7B)bByMN$O;x5JV z!!ivw|A1gYIxI?|Jb)_LDW6rZg)dM10$xbG2zmAB%a>BCRE0MF;S7(5637n7#c4KO zDi5ZZHCAIUfS>eV0oBQOKzNs9v`K|9iR~SK6ad0w^L4(Pyz#XtYzkot1!i7ASZp;X zQkuodC$S|!?eb3n;Ia)p$;6=R}$8~OyN*+$nz>jlE;CU@z)2nAl4X{i2?A2#&ywr#u%c1k=o5|NbWotZhJ zrsws1QN65NF2&=LFSa*7%S>i9H%No*tubMi=K~%$R|v`+P=OZArVs1@5sf_@qaSyl z>OxB{w5%E0sF75T&?O~D6sn7E1N$Se;n7&@q%Rj^v6s@avMgUGt2UZf$GM5uIu-cF zE)=1uc5C`7aYeuBFUk$k{N|X}ZQz}61`4Pc>+JKT&j)EzkgOl8pKO~ZJUAnsR`jw9 zBnid`BxkPHzO6Vu(^HQ%ZA!O$xP03lhY;Ek)+Hb;!vZw(Szu@M+{pryMicmb6Te#) zvjnr&>xB4c`aO9SCLQ(0O1+g|Zjfi!5cna4|6)te>fvpzUAhL2PQe1cWYW2husrpG zTK~Y1TfBBNq%wT`e8xtkeeY;TNU(Py=Hthhv42kjQgnAQnL;aXOPzinAtSZJ)u`Mi zONW358;&?tPAun+^}Gt~n5TFV)?_OC&_LXHmerfN{}4T@WaqNn8Nb6=(+m`dNC6JE zhofp`_6HVwT2>91mPoa(NCqd)b@h*h2~OG_^TxKdQ8%?Nd0CJoNoS)hw^i+l0N8$| zHH~|H)GYLm=>67Z$(a>2Rew_mC~RO^a0g)e8kS+dzVFvtJ8 zp_HCnv#7p4`-1ov*uinx?MW&NQa8*<1FjFmy}^%n)wjW%SJs3{$-T7lz;h!nUUO;clIOzoe6BvJiRJDTFX57m!Y|Y z$B?-SIa@;dVn??bRm}?3tzThE3ofN|p~i}G1M0$CjfGoJ7P+wF=t6)dVq^Q31Z|;c zj;c#8(rzx*i^Yl?avzM1i!mc-A9AP|>6&sCU*&(@=q_DhIoFb`o?_C>X?fliSCVvK&MDXda3nwOgILbFJiTSs+U`$Z*`>G- zo>@9ccgozi%<|S4Ps*LmPj=c|3d0`usectib%#IBYaDYrw{4XEflLZ1ko#_rWyx2u znFi-!gB%5jr$XvGR1YnuRy&o>IJ~|+H7RX*sb5fAfp&&cjvhg@#cUg-pFofwZ3|kT zOGe}@4mVYeS4=mIOmqUE23DO4bC_3xez)&eU(_1(UdrT#g{t>QrkBr>LI;n+L#uI+ zWfFqW^)p;qvY`IaQLyi5XwH0{s$!L?%^H%@mtTI#bi)n$pM3=n!RYf+V0cOL2-Pm( z#mcE4S)RV9sUq+k&Kwko9>D#B@j$cLu6lSTs|iu9-}pcw@%9U@PUEjTJAhY3hk#Hg zpUP#|Tl`WfO22%|d@j5-Fty{xEI#2zQVBW?H+4^PuwtyYV5nC>s)AJB90hIGKC1Y&=rsagWA!lNa_-}XC#3qPY16~erH z>1Hw}ufZGwQjNlZ1RJq0Fg{5q^=iMP>^QPE5Haqu;?y~4CD}OBotq07x7ftaReaX+ zDSYI@Jz=i5Mn!pUMZGEv4`uCoILc!dN*fP81|S1$`H(_?;@8jhI71amr|9@n>wv-` zOPBM$i2*r=*kAS0)F0$A~JjfI~5tpFj z^-(X)jNIiNVP7{V|MwT*v~qoBdvUgYctf+c$n{x{9cu+WW+-h$f2Y@lRo{=eq!ID1X4+x z?7|u@t?64}ZM*|_io?yx(^p&T`t?^LtbZl=Or6Uh_^VKQ>;08hM@o9-fyB(g>T#R*i;Q2fao`K+oZC@rmLZ$>m1PjnIYg5x$b(mXG~zq4^Lj|* zZ1p5hNx0XwQAPw`zUQoQAi0PT)OUjA)7ukwbqR0OXF76k=ZZYgBhEKbF(wN&Z?woY z*zw*`<@JhKoVhp6x~MQME~lDU=e%l1<9A1MS;}v8cEKMJ%#6X9yynI&_r%4ud; zHf)#yXgo6h5TErdE6rU-*`t!4hJT#tdYw5EoPnrFQ9TBUAYuEt$KuC8n6(CNC%~KNiQ=)4icL%Vp z4dVY=*HvI-CH^|WbLyyCv!%nC#2aFJ#COnz$frjN8%_{xp*Zf^o#a>gJA8o3qb><1-{-d&9T_2U9 zsI=xVfRAVN2-T_km$Z9#7H_TcrEw9V(HY!_op8rxyJpCi^$@;ltMxc`8^ND$f(jO! zm_bb#W*Z`!*+8Gz*rw!0MX8p1vR@{500H<$LkE;9d|_15Yhcer7UwoHXh|C4dyjt< z)mUpMp5W<3G%wz-5{=}8vD@le7s_7oNnhaQO%ZjdNMvcgzG?C3RZ@ED&|!~ z7wmapx`Ov8k=1|r1k~+huYTj;Q;uAT(oND}AZHOph~`!FiS;SN43WrRdBD4xmCnj; zE?H!s2^)wE_~5?b-npnXQ(7&Z@b;_l@_cEtY1G%E4?^WWleIt;#Ji_qKp<6{!IAG= zi*aa03ZfYBX`hIh9mzcnO*KeN+dvGMl2N-EC|rA;ba*5v&I!rg9xe3F#blpK~X>Y=}p$Dg+fl=XOR58unDx1)ybGcKtddnOx1sYT11W+b*q zxh2K)^!e@IFO~JeVrb*uR*r&#u&}TzOrONf$-W_yv&0*w5Xl9 zUzyTDIEhlsS$e;}?KX@L8zx-pV+ODUFcZy!tO?JRu#`nIp#r2ve<|l&t|9Jsoh}Hf zZEBZ^_~bBL^tSbj9~OgPR}L1jAHQvnpH{s4pw0j#;T#9jG)_NnDi(bf z7Ln6(oARPrlq@GAeFi>ABWC_RT((wcj#a1$voQTju+V%)&+j>+DOijNlrflKt8q&k z^?;1VkVk@l-ARg2M~YauhiiE>`eX>*!^A)09*XMddK@;lEF*n~8q;nR(Go>ah{HZf zWcN)IGQM=313)(olE_&WWnHoj#)yDFzD`orIX%>0pimHKEmh}a!1^1Z%vV*vDHk@Z zm*g8rz6y6qVIR%pXRgM;&qf_sD0hNq>0L4JgG6)|h$!`Mz+&ehJgea@$<*02wGfY4 zM9J6%4Pw6iBHs)Du<-1mj#S^gIg+YSc{1IO`poIdrEh=g<=gtIhZjz4J2cy~TY^W} zt}_x?q|d<*GyUL+^si~+!$8*V?l<4P`p&Ce2DYBqK9dd^jvV$|95Qv|YMU`AA%{uQoyGkv;eaCL zf?0d=gLvoRJ&3_Bha4*wqr35>-Dp&VazDK?4k_~S17NO!wc2dQtY&$6tv2H; zLkk7Yz^wJsiI?H+3x5B4KiWeufe@gIcQ^V4P`~%YB%Zas31XR;-)Cu+iw$&X`Fa23 zNRl#b@kow%YEOV~%6~z?5u+t06a(weR5Gn(+ z0I1_r{}e4&@u747egXnYu;?;DB#18E+IfsaLh03Lb!VJ02Xi(>ewo;KJW6n}PIM~L z8)YHzoDn=!8o(V zi5J6W_a%>Aptf`|x{;q`&zPcb(8(lkjC<*6IRkS z2edr2=)Y+fd3hHqBQts~kq^`fl>3m*=JCO-)f%aP!4Gtf?i5(&AweIeKFgcI)}pOM zj}hSy56>+TGl^M1|Ks2kJ7IzqDJjGEXQ7rySw;-~FSvup8;Ze>hu?nK>wmW&19eqx z3y4Iz7<~0QHk(v9#tSo7yOx78L8IZ@L`}^_ux)8Nq$Be#Lt<3L(44CyE_ugt*ymmD zRBkLh6|EuK=Vkbmgg$g?c1`F#l=C`0_s>Iq^r=SVo$c(bL=BpuG>Xs?_(pp?19?M; z;Nn`~zz5?T>V*L6S-{aiS97-=B2@SpI?-j1<-E2U$n^$AfDn}2oUl*0)i_F{#GfEA z8kM8Kf?~q<$~(f*>D9noB-oFqGw!(BzLj?y*7oqeOnug5V4#b-Z8$4c?mSq#NfRpt z<%6g8i@c7W$}v3_rND81XD8dIY-WfuisO*^*<(ItLhZuyTO&O<&a5SV5GMT8g@9!S ze6rUh{ym~zs4ZA3_QVh8R(MF1bw*-3wMpI$(2<_i5%d?ripE$aKh`VzEnRGjLa7}o zp7G}&PkEJs?)MLX^UD_j=U=lw6de4X1=geN{l|vhnD6HvRw!`UH7JwmZ_JTbQiN8Q zqLQi4nj?owS}q}Rfx+kU{XaAQM!?|?Xi(h>qPG262l+nn5131l5JU;HcG7VQBCol_ zJcQh4IF8&n1>=66k$G(O>vj2@^W;B9l=%qCnvZsyL|dQovB7h7HZ+4v{5tQ|!VGu8p`agr8-DOLF?7obyS{B+MWU3QK z%jshpG+FkX*Ds8yuW^6O`$lTrfDav;MS%5eaXo1$S0Upzu^wc&}lO$bbSA@^b;3lJ(DE zc6i=GL~t7B7@k^F5PSK&g6zHXL|5FE_mNv4Q*2#vhlL$-dwz3m=f*)(JoJ5_%&K8TwH4RO6 z%EcATjK@7`l7SIAX1W7*t4@H(RJVXipnV|!ioRi2_a$j=uJ4#VEepw~)aRo7xM#0o z$DNJ=LlK5M+(DnVGWIO*ILy2*nSZ?$vk1@nIZEfP%mtCZ=3&579Jh<${WB>>Dn~EC zMS@4lVplZ585fqrzC@1o7r7wtUoZ&Rgg{zTY>!emA}^)yg85^ER6KaSbPSNFRFOht zZuWq_ZO&Cq(Iu`iPYhBkEp80T^258_Sj7x{##m3pkm@sbt=Bvv%H&ldh+ zC(^2Ot`^xHy)w`;=A@ELR1yi+CH>e5MCPS(0z$p0dP(K%IYlovHzSYbTzGNqari=0 zQQr9Z;k6sHifCb>B&}ji{)Nb?I4;TbZ7v|oSeNR+mfxJ7z^Y8a`DX)L1w*-Y)Ir`R z;LlPUov3|`gHP~fA$7OOR}SToe9-v?iW#7z<`g)={B0X#>xSic>cDFH4uv2HPnpO3 zsFLaKY;M^8;|8H40lKr0Nqh=r{Fg?`{U07{p!53iT=lFrI*Yjk@C3@BAe#dvDG-;a zWqUKg+;GVXD^xLJmJ4I~&N zF0Zvcc9$hP>`%2j(pRYIS!?#He*p~6=K`Lzr14+v^3FU8y#JjJKcHP=x`d8gufZAI zYDq!(jBHww#kAHicKr3^)y7|H@gvE4VDX+15vf#ryHMclb=w)zL<+8O$Bpl}L4>Oexf> z*T;)y_63~Mc~VG4yReF1jQn#xtk0l1@WQxUQB^A5y>c}$DsZ(lG}*L$tyBDYSwvz& z`g-s2!UCYCuR(5Q!udbLf@pVh_|o%=h7z|#YMwVJj3}rXH{T{lb*qO;<4k*l0N14m zbxFNQ2K_6Q5eTQ`K3S^E2ep+oVrI0vCH28Dv&Xb^x$jqQTtuhsOQ?5@cpKovVtywM zU|}(ZAaVGt)dWL|b>xp#Gpyr#dzmiQQWGp)h_r4+qq)kfcHl78C zX3Ku~)}9hQfYStf%)2D_;&2B{dx*3Y#@?cJ`;n5a*VT^*`*R(H}XzmKYSec@|g)U*OE6g{Yu; zr1$F!D+B#TY7NMZKx}5>Pj2~RoOCc#W_O^I$D)RG=(zKBt>%eez7?1!V#)?Zt2d}h zk_4TFpfX0|e`+oZYN;^bf%5sl4v0H3HnJ9@jj+A+vML)KIgfDt&Ey*0@96c_!3u+f ztKydEQ%yQ5nVs$bM|01&M*3uO zY)CNhwbh?DLjE4PSlBnD(wf*gR!@>zOMI<+%aoSYp9>X^)fR2tBt`v8AC&S#K-YpM zy0(Rin!2GydC|uQU%b&sTsV@$?upTgHL9&Rys?2ue0{C)aENu&&(J46J(G==>y9de z65`9?X~NP|H8HXLGb1wi~% z#)jd|MvZc$A(-JKZ_x>2+5hE(>~HtRB<{W#L)Jhj&lWiHgsPp#a?!2z)2 z47w3LcWvjjQ5lT#5(5wW%TPGDS20Cv%0xXt#_h*TjwK}2I{28{D@g6_R+J4SxMfh? z%*Qk9CFO%fF8UtI2Ek}!h z{N*X8@_h58f@D{jd336xxjg;3%`{IE0uj8QE#D9vm?72ozfyQNq~lOALXxl*~N< zT4E`rzqtFnpOMpy?64Ac5e^%`>=P6}BzO~BrTf5j%h_>ugX+7s*-Tsmz5r}1jlIZ` z0yAD&YV3XUwIu6`S{sT_ImH7uv3v2$I{&I1p&yfEfYNW$hzr~jxRajA|H1~qfcOTK zQ4}-XcsD+akzg78c}Tum?*g^sFwW@Fs$$XBwU+^HL2n4jp~ER?^_-sHEq0h=4O9Wc ztSPrYE%~~5dBXcBH>_{6Pj+TqJF;H1cIvqu;~i)s<7fc6$8k1*)oVL+UIiSll-Y;= zzHj9&NGL)&mHA3f5Bc8m$#sd~Sp6y>#KEXoju%yB-hvCDUD2@Rd4ID>_6 zt;y2z>9VLYsY-2`6$|-;XlX1T@HyW9BOJ(yfkO6vOjjmB8rO8*s! z8tK)mObM|#2hnjtpZUu?7vbL0Asdf{n`Oh{C%ZP!~fbNYm|K@#iwH0zl`lz7VInn9tnj#15HVYQd* zo1jlsR;^IOK!{0;q4r*+_M;P@BdZVxuA%WwO6fhnt>CK$_;H6-J1vdH)CB?{)4OIx zz}i}YM|weXTC6x{Fw2vI7o_q@au4NzRFlni_)f>B9VrZOf>(n;Tr2AxykNQPTa0PK zM&`~uGu(WY=zuEHg;`*=g}c*`Z!>$)KH~v!>N5=yFP{~pvX1C3Hi&iCJR;4@bP;tJ zzfAr98OZ>ICtzAULt3#nl<0WH3$;I%Z?}e(4SaqY(uC;)J!`K|P(Y^2PZlU{QtQnu zjJ$J^^jes28vB70_hBS89ZBq)#W+x(jW6QDqzl5NNuw#)brHmBgtVKn@eBX%JkB9&e-(3Td4*D6yhPRO_EbmsZ&AhXNSd^uW$0Mt3?DSC&cz#Vjd73 z79M@Ru?gPqiig$sPTt)xa}WOp3PqrO z;$v(R(~ZF%8Zlz%q;|JjUGdUQ)7cxqb9}KVsCA>wG`2PzxO}heVG8UTr}_9Cb~HXv zmlTFTJr%()O8Ct`WzzPuX|h97df7DAl-uq3)zF|D*>h)`Dg}{`B2?P)&1N;KhYdpx z)dk*dD1^M*qufNeh(0+w%46*RbKVa>jBOs2jzg|GhEYYKq*QAJG$daDT6+IqT0{aK z)SU{_^91NJB}98(ec z)Mr~dq|@0FsrEx8rBZ40!W4KH!sFamlX|?5bBAh1s z<$|yWoX_FcwO{wLZx0;KYpD>P;&bRFFmMt6BvY#FbzGS4>7j^(C&N8eKrWa@cFK1d z!e6BL;*dcXSCSODSH@uJu`XNmZ}1@=Q4>_Ls+#Qb(ikU#BD_m<^IUC@4p~xS{6_i< z^vo{yx~IG**S6*PU6UX6NZv$w7Hl9$GxR(~$Nd0_6`{1>aI#rS9bnhM=K+Vr)o4yB zK3XIXKrnL`EcY2KhK4(Jlb&Q6mHzlyZ-8nNW?I2hb%L!tM=>*LaBSmgsv&yJgVa2c z8%70WKLis+$m3wX8zi!Chu{N zCHKNW_Ls+94FAAPDgW>2o^P5vPsmX*C8L>_gN^%^gASP@HsePVK+ z{Y8>RHZ=^B1@^Zt?5zN+|ctA6R(sfD4EE&2+nDJJR@&` zW%1gml{Wg#Ux{2VM9?$yIQ#fnXYkTbt#ysy#78_5CL-Wa)yNDk-I}WL$*8n`W8c;FEEZrs$>p4{{S~ zmfj^e0EGZ|J&R@TklTs}wmP=9g0TV08|KbhJ`kImVE9z$%$c7bKll&46e|$K>Iyef zgVBzKqlKKIaJ(+IX%a8_okevu3r%?GdF-*_QSeo!zF@u)>8yq^Xl~{Jr3#fl>;hTv z+9K0&=BAkdW!M4s9IG#=D0;$nfaVi& zSRNd*5cSd&cm>FTE7}P0*d&@P3I_ z7W#0@?VlQ3tjy}ms7Hv2I7U$B(bSqe`|%8~`QHt=x6YLtFod%rL@@qlzBn3>jl+Cq zhy?M;kk8F;s(q7dth-w8h^8kl#YFz8O;zKAsj{8t2Ns-%_v<9za2x1C-$3^WY;Mhi zkJ25$N9h~Aq1}^gFTU-nk@!|xe){TPSK0nL!OgFY zaSSW3r40GZ6UHm(9s9!gB3l+=8}1v;VH*SdHM#4-qR8e3cp+EzM#;XzwO=v9S**}3 z%!bJ5cT!BIh)yqgti*}^+}YJ*j|$X%u|&*ve~-X7r9+t*Mt)uiTp{s zTskG<@Qq}H&Ne!f`(M2P(*it!B8Il`q4w2o_YN^yu$ms8K zTWZQ1wf82+r}jh?7&*3dH4oRlgLM&)3LHhy2?3;%p~T``(l2RlJK@!LL#|UsdE@oQ zdC4`uh?%aerBBO@AGB)|{lgKCmb6mz#y)@rp_xrJpluFk7j} zJjFD`FOzY+d*((>!;@WX_XNH6y1Ft$qWWF)eMO{?6irc%42`{V*-a`l;)%F9;&k^? z-=K^%`|g}YT!uahfz1&yw7~F{i=cEue!CSuWQEIW{H1VpfufJMa9quplvrRbW~UE1 z)vCNntU}fImR`jQ=&{nCv`WZF6vLGu^--MEE_m$Ju*4O`C>t> z?3I5MDsx^|-j7Z5vL4T_vp19$JRaeq(2PQ2&0FrgRL#{Jm4ivP4JN&M`0FJ0ES^BC zWQKH*uX%pC=tz0k8SL}&b-O*3g!@!9$DR=Dm%-jA^;*QKFEaO<6}^(R4{KJ-^6#4!(ynJ2 zoH8Ov!p)6^a-^uW=xHw+pYN71nQ)q>eyparw>Dcyhz-e)226m?rw#D6hYyzT{Vs>P z$VN4DBtp|nn{%@x|CMlo&l+R>>9hf>vdK@*%Q?^I&vNHn>8pu39c%y9do79^wV76# z44aHdJJRm%Bb9-%r)Q-L_tX^=HB~TtY#4(#JIH;PZCG$X zUG3%!H)R*1Q#k&h1Za(@rr!1I`R2RH^hp!}UU965lFj&sdYwOwu^1T9X}HDTu*r;B z!~4&xT()r?VT=9*WbM^B{P~6YG*%;oTx^WD6PRv4jEs}4UthXU`(3u~<@ta@qg;p*#c9Bk*k_F@8=A$hBByb7~r5_@ANeHGuXO&``apAr8|)KB`qEY<=HA1z)#yCAG`sIFrtz9nY6u zq^yo2oxTlC++T^|n*UKW%tnk9N{EiJ@@Gy+1R<+2lq_mQ;hvB%V1<}nM^u8mp4vam zVm+PLZV4QqRM=7Se2fR|GBBozBffX-1<(wQDg2UVelq>QTtH0Y8vteE!MfYyyU7uGc^=_3!5*MtT;?ry7EBWGj29KA6)SK{qF%$<@R<{hsvF}Ei}%uo$_T` zY2Zi|LDqvtMquLTxL%@Bli|3ulT*f;`){^`5vpqdz=bvk3c#-s+}3en=v%b#pR-GL+DS!b@ex4 zIrSFP6#Yf+_l26|Ikk-NO9Cn5j`=Om%rBC~-ED>VSgX8Qw9Y^F>dY$N#uWxU%n@&} zx(s>-Kko-?$0i48P#o;+@u4{CMgI4?Uj`N!n*#hq-c#O<#vH1umLP1hhI7goG6ae% zitbTm;e~S?^FOV#K@WRdHg)4_(Tz7$C!2MHM)ih((sD^yu3r`EwSWVavgU{X2NNXB z%&t*L#Vsz9r4w@R>_s;qn`B>lpdu_UQeEK{DT>x4a^Obxfgw)4)kg&js-KwMep~(5 z*go$8YkO26=j28j*T*-?8%tKGwXJaRaiYw-pI7gKAAbG#rR6le&ZoCh)VBOF#eY4AFLHnJ@GmDBuu3p#ya(o4uO_HElA)}iha0GR43|ibXuAX6 zkd(eru=&)ttj-jjiS-(rW04PZuZ z@9?r^T?EYAoqnUJp3M!`Tg)zH4u77%d%5{I@#9_36+)$xeHsxSVucqx;LjDkM``7e z_E&VbW=S^k8w;Oy4O<`)CH}zL*pmc42M>NK3eoGuU&1N$zgH0rmxuosYi&}d$PlM)+*|0EEz7OnyQCtWy~!a3<*;F z4%dYB{59{lI_}OUwi_;(|EbJwBjHv_IXd@EgG@t6X+#D1fW`qgMC~1n(wwv#bH(%!>+W229<9(jO4eVidX8C0o zJd8DpDl(`J%0da~Cg7FAM2O>hJn4)K(FKygQc5r1r_o2B7&Z#!ij?bx2EJinRaIGg zN%@&a(VALk-;7XuIaa8(K)uP%jXh|_59;9Klkfs+;zMjxg}~oVr_ai=)jYtQxa13t zJ{x1KKlC;9Wu)?A=%@Uq{v#@?)}$a|wToU_xbo{qR16+qOyz;Ue|n#;1Fs06bQl`U z$AjZR{u_F#q>S<6d&U(#RpS%c%{2}YHA`7D#M%ioH zZJ4xy4#}=*avs|F|H^yMuqLywZnlkWyy4HWiGPA89^Sk{`=}I)tyZ$GA%j7 zy}n@bg_mnb8c>#xdYBD*x9Jh2n%)ZT#tqO9CkoMyGqM@oD~+IYBgT8n6hCx`;)&{& zbf?Yge8(@3OKX|liM}{v;xRGE(TCvNL-KBT!`qy@1~w-s%X0FhOUJ9Flw?Yn!!;1d z-ep*P+Uhk@mK^2%PM{jE&iS`Wx6F3_QVyNm)uOl-)Yeh&K|`YIE}T%MCL-hSsLe_r zL+i^M;}0%~qP4ye=EDo_YtRNX3wR82QjjkoM%y=E`lLfH9wyAm;w=bTDF_vkpFv|& zD^Wm-H^441BjmalUXNgBjEa8fnWW@ENR$Y+AT%2?Q*@XqjPOmvydMX`3@_wGmQAi! zq@Td`VqfLqex~0Xw?i6B)uxNM7>Q|`5iknDE%xKa(-HWuQBL3~bOR zyh3Yr@kCKz3`CAaps~swHFdA7#>d6MRbXR`?r+uk#bBSZge7ALpoc5O%_Rf!enPC zM^nvRI>yG?@NN#aOx8qzXPF=G<*QF9YI-Z*Jn)`6%iPi;{uaSSk63bO+sVhObR+xP ze%bLKlox3luHA;bi;^ut9a!>)j60EirXSKC1jU)06%-xlc{dZ1zfDi5DGv2S(*+>? zhGZ&1+o&OEJ=fp9c0x#2!HR?O3VR9_*%%wMwRPR-Nrcd>e4H@&m6Pipr2oWMKxJf5Q}JNH5R@g_^}^s%BW93 zhHI)CxBxb;NUZXqjL~%a&=+CIQMP<>ibEveMzN)U<)`O6-jWA-|H) z1mb~u+!NhKz#?R z$$x}4`2=%#;4;_+RFi@ ziRv#V&EiWW@!%4vkBg}ZStW-EPH3n&2tds!Gs~ILI*_%x?yc<%EmCPjMi>`1A{!ubNk|=nCfdKV zy0pR}piG+-a@VVl<4zd%lv+w7C#B?1lY=#w$(8@6>gD%yjhc}KFOe~Q301@%T)c?O zj}x)mM~$NdDwoh1^w`*NfB(kmD_vb#TFrZ5yKVNm=-u^Jd#31QXoM|WjoR4+$g6kB z;!5no_!bZhV|Lf)3ttlE(wSSQAzNwgMpCSqg7=%kha-=`dZLxgh-RW`$jHXk z=S&#u_}a!n6gNZ^`2kD|yuMrow!L_79IEN*+GCwYuSFxudx&=;g#2=r__vQcbE+mv zNDtI>J*2dG$Gbf1$?+@@ZY3xfsdhA)FhHf z@5WhwUmT#J=L2&C=v@}i@UApl?vU?RS;ab6d;C6O9R`sHI!!{Gy$6~skTE(|z}~=I z^<_xBvXv%2fwI^-k7$f((1S5WQM3*#6d44>bZOqfOO(Fd}NB@^Zs)yP~(Oy053_Y!`||1k8agfn-T z+|ZAlNEJY~hJb8cd|29OX0Os^(#+8-sPRlK*1P|uT1pb^*l5DXyU{?+hLm(L`W4_# z9X2&=G(k{l`TotOZx#aX>2*j7mL`jf-H&H=T@MVJ+GL3dc_7?U!FqLp1@5|DG zls>f5-avvP>Wzm!khQfohkN`DU-?Eg?5_fFOsm0rU^oA- zgn>N$nw?_^X1cMN@CvE1-0q3?RlspbY`&-%tY%iui2uN+~w~->YBelDyp)#J$*=R%3kgrJ=Iv%*Zg}j!|%>O;a6u{Y0?u&MFR3J0ReGH zp~p69Q9kWH45}P>^viAb{421cU2Bye{=u8R)NgQ<7K)RXZXNRKNc(R9lOdDW@oA6T z2@?k;?P<@Jn-Dvo-o4lR`Y!UD;BH8ozBq*_Y2S15^i!w5yLS~BOYRDq(>q8ZGlM7p z3++I~W49$}C*D)HBAJE#a#e+ZAY3EgIcz#C9j7aEBa=8^v{ zQqaZ%?60-HPi(cd>oKtL8weE}6yz(&0^~RQ^aPyV4nq$evnXzj*qRB~%7QYW*jmGM zQPM#L3amg~LYIP~-P?fleDe%Db!XOtq3r(eGF3CbQvF5%3YG^ zJ5Nt9^=JBS(nw2xS{{IXGV&zSyQ`fVTCm4_DfN$awtnbJ>FgvZ-7+|r_MLAVE0lml zVw?&>PiuHBS(#|w{8+}X*5Fj@U%0jRD92O`u>FfBHB>pp0r^2kMHEo)_#r6A;m)NubpH_TIDab0$f=wph~U7R144 zsVd_Loma@Bx1X(#y?0nJ=2o@4vUD5L?6p+-0(Nz#x3L@W9jvi%GJWw)Bb{IxEWgd> z2%gQmR)lx|h;oc6dK(HR69HVQ0d-_-J*nRvmXwFuir8sY9NR}Wb^DMX> zHT#jD0($%(L)OS8jqVRQF0OfnsN&&Pw*Y5j9Dn8=5RAp1x&sG7RtQz<-;FFOi0JB( zhgBF;v&$BbKyx$W+4x`NQTmZrwyPE`eWveb(YyDFx_!)eBI(>NDa(rXT_v(0RG#P% z%QXrlf@CaP7Y90#E1~oN$|TXzi1oDao3hov&u~b6kQw}v;9sMj;6nS zNIFyy%T_}3XO{J^>-HTHlldUzW0h7her|-Q9?||&`*)obj~o5F)r$|%7cOkQpJxU^ zw7-Yo1Bj=Cau-uMAh!FUymvrsmXbrW-t@09&d@Q30xi}&66~ooA+GlsXWY6AZc;jl zBpr$vVJNz~aLv=H!FN5k$%o<-RJZuxg+j(Vr3>fJtNz*3Cw=MMU%$2ssK{w-1VqwD z12&hZn(HJ}pGRa+&rPt(2L}g*mF-rej)nf28ID?@vr#d*MEdbW|9V`nu|r94WxU{26(LqONuuKC2ky5Hfi1d}{Mu zaytupno6qZpX;2tUuu>0#CfU@vl6%YImO6q_wH}ovWMP0f6ihu+%ad*UDyEe#i#3K zlj&E0wZC+PO62_c<%}2BsCMTIW{18xz%BlE50JskUu`w zU1dC9aTF#RLD$g})L$Bg4YZkqEN#}3S%z#aY@kVe$qv2iI-Hs_UCt|Ozsk${@jZ3Q zrCcU4nEA7MVJvh`Na?N*(d-O7W7m4;%64#wY1$U;B_5l2X zL@Wm~H`f8xvSTJJWCzki1*Q*mKVL3Hd8!aYxvw<5%Mm%ukqfeH9$cTSc4wLWtMG~i z=gJL%>V9fLNP)Rjl`I$SD>p22&#)DqM4S_IDo@Tqm*fM-duP#wariwfVm`yPreg+Ns5lz=V7WF|+)Zh<2v1K|acBNHM^alr4n#V0**{x{s0 zhoO)1c0Ha&PRS6HRSQCYu7t6$i_czErtXTwGSDLqTC43n$Nl`zx&BcQa&2C>{}6NT zJ6AKs#I7Z(1`6Cuwq6}NvcUU75z9=1?}d_Lc6;}J?&Rx&c+k1ZxhJInoI^7F_d3`L z8sRrcC~APw91-xh>~SQeikI?7ci4-TasY(gA#1VBt_J+wy@UM)vT(G(%qB-mU1NSK ziJJTeT|9(#p7Ihzr8xavEd_?rL;sjwhOQ|eT``c+urhkuFkzpQExc%<>!>9H>%K`e zAqqNk5X*4X#d(0=<`+g!MrX0dlR(?Ak<9YN?M{Uh5i zlWuykY#+6wQqWeZN@`}zmG5<)iAc>XhetI_RF_+XR&w?3H{t9&3tqQ+W4?}R)VEu# z=g%f2C#uVu&1yerld`4NoG$_piXD~9ZCB;od;amcY$*scau|&>BQSPqm+R@Q*%-P?WMvoMR$~2mzkvWj9SCY~w z@9*nhqrbe8Z0eksd+zzb{Kop=9!q5BN3eFcsBG^2)ezF+;^L|1)2R?bN6&@(=iKqA z?lhbHC3C;lH!TzkPlKy|3wfxZ{N?z@czzn+()Xq}jb-M3`tRcVZjUE4t!fM?=kg37 zuodduIDWjyiIypqs;yzu+V*D5BT_(tmH_KO;M`w3%Q8ok9>_vO71fD7O#>eFO_5u7 zxYzFIh~)&uAb*w~-05V67QU`IDK#oyQjbswB1m;>w|aZtT~GLG;$&$9sczs#Pu?9K z->Oy#Dx3VSd_}Z7IDS1B{@U8=9*z^oNr~|nh1x&{5d(ep+FYjlpsN!MkOZyNt|k&uJf*!K`=kbHA`c9@hqiAb5Rq=xxH9J`=w+MF^d_m z0q0o6NXc093H~~)Q{T^0YwMv}XxWIJooUsBbQzK>6a#;ArO*n`?}|8Jeip|$*nK_S zU_1<}-*^iD5EF<40c00rdm;*lCvRI$>CCcBpjG|71-17=$qh3}=4+p*b&To;dmHU8 z;ldS^%7=;9{#xXSr+!4`0p&1%Q5Xfs&#q$jeL}#6;a%^F-SDYJ{fnKw`V$$AIF<8( zQ%JGP+I_uHGHVp^IW$*&Q2A+O&9{#V?a?EHh^LYMGvMoSkgnP(S?NlZSbY3KpyJ!F zq6|e9*lW`!J1!Mp05 zN^;R$`a5$$UuZnqC2yFgW|HYd)_NLW^P)zC#{P=qqaC5?lNsH(V9LdAmZ~rG?Ax&3 zb(XbF>*TW5>pP43G7jU)PfwXu&7^~N&OB84(RC+^Dlz4IF%fHC#o_Mhj85hWa2d{+ zT=YdN5ZlmC>#b@v`*31A`GY9Pbc`tC#G)~q6mgt}QU2lJA4dItfZMdc*ZShGes=fr z0ZAE5H*^}*!p$bhS{h)+z;t&x*4@VBo$HNAeaaZJrJYPH`VVnI6i&R~JoY7xv2-y- zm}EltiJkYR%vMN3Us4c?k^++F!`yJ39O!(Cj?J+D$7!v@sWs(AdBWzpMwLQLbj|7w zry+jy>Dnf%+N*9ijG<0j)7S2mXFT=ur6kQXh`^G<5uPg?Slw}siY=`JuI>JL>S=LF>-`-jl%MLP%5HPmfw zPNZ1}4Y;^r9${N=cmmDY+CKz7h8?QJG06;XP)l$3rQARb7 zgSZievCr?TR@z91n+=7;*w$_yi^Z->H>P+|1j@C$0|B8VF(H_IGlH8_l(<|O!g1*E zh{qUow7J7HtuIC4E1Hjd1R1W7WyF3Ac$W;-F~PqGA|$v}_vy9_=|c=^trTYEaLSg} z(H1CYD)+77TLYvqWO6*khVWW@053_C_jK_W_&QU!DMUVki*lR{a#c|?stUFnA2hNx z#Yjp|OOOBG(hB7@HG*1TQITOBS=d_?^0`ipXJqlyH&pzY_Q2b!eV7i2VxYGpq#+hU zHMTVXtYg_7*PKC{abpN&8Tk-LqC+)MobZEiT?P}!`Ffw+P{CwCROG9*-(bU`qb|FP z)}iHFd&4;y!A3)_czs5DeW2k5qY1dNg-fy@meS^&^Fqm$AMAdttBR{im_jK&n?tGH zkEp5;NGO^V-gVB&F!7Y=oOuirFB6UD(W0tVMtvIWg)&saCra6H&BkAh(;&$QUdK}le3Pd2Mj^s@gdbkN#M9JSt5$bp{H;?kEsnEDe_UsrLrkv` zl;_~6w0H*En&}EGCmElLH?37{Nk=yGp65sLgR!-oARlRE7nBe8Kgbd0fz!~C>DKPj z3srv*;rR#oye^?(TIdS*p%tJ|>Bom3|{cQ5ND)+hZMY}bh z2NR-DEi%(5rd}%=i}v2_yzxnl(uVbuD8q~`I5V!3r+PQNtDVixwb?YMcvHM6mK6^3 z)PnEdV6-!SCpXC3dPB!9o+lsS0HTw_pk$S9$!+&RrDD=6+IcEhg}>m`eS^%@nby+* z{KTO&CqY>4r!kkO@oduNp<5D)UWb$5k|zdYUHRE7`T}ZIVUgtj+VNrUNcS|;(AGeR z^mN4UDX$|Y&dX1-fnUAb25`XgzR%RZ8dUF@iN^vS$Z_WC(#Iq#k~`Kv)v!?wVdH6# z%&1mZZf*B#@v}IyuNQHU^C$1dX^`9tUOyJ6JukVq6mnHTS*Z<_P{h2Z7RW#_DD`^( zp2wQr?II)mEf4JU34x5{VrvH|+QT<_PQpgkt=UMxQK>yJQ2?&{vq6nUWT^y)}^A7(J(Uieyq#hd|4bq9zjc zV-J*vq*+!uWxV65HXgcJnss)otD#U1?So{JKB!F!|>stl86jC9XrdRn;vhmvG=B@Df&mg4>uB zq-Ly#i&a{7wWJS49nQ!((tZx+HK}AUKEP@}*Xdk!I z6`H=#v3DQhoCe#uVy~;UK?+lDVqQMQ%()fbm%Kjnfu~UR3??JaG0joe7an@bpF#H@ zy3blfF+!_iFidC6rn9sg)T*SmaZ<~5GZi_68t!f@ZuUowpcv-@MEgK%(u`&K)$5rS zcoJgB=!!UH-e0ggKVC4-lJ(TOaFr?sp^=@`0~-e)sAQ5BHP~&WgT@Vl~+EM*W(%^E}G1RT94vBi-!c{}m)`QE1D6@_->*bgsN6Hy2R1BcGlWlg6M*Jsv@O33_InX0#G*qby|nM6O)RhiB?cXxB6 z!Mq+uh0#?@R&V5VHwj}#dUdOo%*5!<&La|?(0SKq$6l+$&&I}svfs*+98TV$|ClldN7H)AhH z^VtjsLGBMJ^mfHGdI&i=zaQI;MVVU-(M@?(Hb2yS@|Z*Z#+E|W~0m)H`bYD|{(NIwA!w`GNi5HpLz&MgmKO5jbE*idp7-3S)Ff%|v;pNaRYGuG zRli#?QaPro%@|~ha<00iq~)@>wcA2_nzfy2_5y06VOrXHO{>;^{Dp_#dZ6HaGd#T0 zVsPgZ@L_y|abknV9#+LY5L$os<7^lc2n`OYilV2Gs=4%Fk<|G$x6CE)f1M|QKXJ7YHK(#8Ah~&CJaxA2x?OEzd779je|`!EzWBK&&%DQcgJ1kx{`4IS ziLOFoKWIi@CWF2PLq8Y{&PPXN@+?|rlE$8d&SPX+h|7LZwEx4d=ZOO=c1=q0CD+r1 zYd_Rwy~S>9oCG4c?Hy9sMWoZ)y#}FzfdlK8umsnIKT(QS;2#d}BQ7lj5ELra%v7g> ztlzdby=x}voB^cAdn!O>wcQpTT4-Jv%%47+@mb8Q*fJE6BE1T%kLjAOJtuaDD+?Od@sfvD}xq(lM1GhT0{YP)ruK$^!3!*-Cg? zW|QWsfcg56;?I4=4jsldy+^bYnShUF|}KEZ88%mJe~{rc|@^Mu&+TC8BP1 zhU6Orf3A$)Qj)iEgJ=F^#^7Rcn9@$OS`C>iXz23?OHUW{OC7cr7kf1tzLJ#pAP~$^ zw!!#Ghct48v(reQrUU-(2)1MBrCHZ4m&4l zBTM^iwW&LyVE0B5!h#@ls)_(tn|5<@z}naF4=T520MV!l*Uj{s$t<+VIxba+&}=4V z*4p4^I@-dywTk?xBfNq~65dE=Kg*Y4c=hJ;u^ZsvKwiy0bYS4k?-%QKezXgdX5zJ> zNGTnIUw{8A@7f8^i7FSf!90$%-@u<_n2cm>euR_POpK|fw%YYog~!5|?i6MV_f9)Y zabj0Bn+Nd#)!6FHcjQp(1mNasGA@7dMwq{=Dy-GyP(E^bd$8C$<=D+g|Yu6_3I z&(_py4bQaM%hW+XUw`xfDcxak@(}mjgH1}j_HLa}=+7UYOLS~{R7=c`=9HZgJffD- zsC{{!(m04*4rND>>$S7Hn0w4(kn{OY1oyLLU1*N^c;;f`Br+QpcK7`&|yR0C=F~@T!rF#}F zW|8yCcKwBS=;J>h@7K)%N`EWwc9%%2FP9QK$MK#H9_H2eC38upif?1-llf2B^5?Dq z7||nk*d~cRk`}`$x%o&u;<$J5Ne3%zMrBo^^ zl_;^$GyGNW<)Pf?6G**tLO+t;iXB$K`>|t_PW>}HF3^QX1y?7W{SJv+H#de9h9z($ z^?XlZIiXDz6Nmd0VG0RWXHK$H=Y<^rRr|C!?v|n_FXm8AB|VkEKORnDk;Vo2!hAl3 z*h>(f;saOH9rb@_CsGx9D|}c_ zF+;epvr=(H=@E*$)2IrsIMsf)m{+*Xxd<0k|H(i@DNjFz0}lrI6#EvOFrSOCp|9lv z8$>ad8|4M;eh|sRMeZk>@EZn%u1q%m%yIV;OYdmdPkKFc^+k<<{GeZiSSNDp zRCffb9*d_%aq7HznT{EQfBh}ZAA%}EtuM=m{$Sn=!e)JAzs*5@^lU~O zqQ!Al*D=I<(3|~8imQdl{vTXjcl;kb1YF&Ci=Ek({iy=Sa`wOcAuYCV5&i$FSoE;z zgMUEp-H=m%=5m@scke(5!FIw@H%`xr{rbCExn1q*szw(S6k3aX{7hfS3G?uaV#t=# z&MJ+YY__@=IQZ#eC~$H;Fh{aCvQ*A4`51uEU7gp|0TLYb`e^;m;85sUnQ4xIJbcjB zl@l#8XdlRhSC5~yZRG6z+`>=uR&-#VC3U{AC%iFez9%VrMeX$LBH-Ku2f4osve#xA z`0vs`0ZiGy?U#!OX>|yPA5qo=S{(LIfRAW@(FRWbqx6Bh0sddFqEYDCSE)9XrB$K- z59m9aattpeV&5jwIG<0%nFv)b#^}F$XIZ*)5oYjVvZ;b5Rzo&NSn4P52+iFbKUwhs z%LaYGTVbDhl{Mh=5!%akKlQ1zrwnQV{C#sR58eSV%Kd%wvsxT>rgkO;*OL~?SdL=W zd>%%*cf-yaRn1-Kb;rq=&kdE3eiUrHt^{%xT0RKi5q5WI31i=JvmVR~C@5^zwFkH9M zrgtVxACvnalUeV?=GvFU3MlckwjiSh9=NW*D?is&-_M{qo!Sm*n58o$B5QW+SmzTd zQ(6LAx|vq7>&c*7Q9G(Ua(Qu_y@Mdr5fDwKAgDAp0(FMhAbIX-y$K`)Qf%yW5C$-# z{{pf(a<9Yp7`PiPV$;U`SL6KOET4IwM)C;C-*g;mU_g^IZf84T8i9?+h8Y0{3qAz5 z?nHf?fG-5DmJUqf`G3*qHGA3K<*T$@@C76v>mI&9Dke30ce-2YxXsk6;! zjs7?eca}Olm2eQiYV7B1=XcjHg10yr1N-A$6g%;6@&87aMgH0<-hB#ZV z?c9a1GQe*;`!707_)QPJTF-+6ByE2!&F`?V=4omi|6-`+yZoZT|Y!Wn`|;}53C;o3h>qL5sTd~jVrOzdY3y0T^$?sFRzHH~>HP2^7AeR)Hd zfBM8@L-N>bej@_h*w%%h2I$1f0mGtr2wRtu>Wv72VxI;8^6Sc9LMq&^rK?Q4;`dVZ zLyB3imivJ<#@sNL#F)F}4WeR~6PW8rRVtlPM79L<%%97N31OOG;;kj>}nt2f_j71Rkj6Lw8wP|G#+&plW5d5KVgCJR z#l2Xy`QAxYo~`$FWlb7g483c6_ET zE&mr1B+Z?9d%L`9^vu*-n!#+L;hvw2y9WXtz;b{|DRxlNzQ` zJ*PKXofS)lLAu`f9u!*8JkKaF_-Z+u5bZpksa)<%6%TCwbsu2E{sXXqaY)(Pq4hyt z8uhGNjb+4$cXv<_kt?XfvF^}*!P)SdZ-$g-?0Z$iKF{u&Vk+@1BE7vqj2-O@_~Te6 z|95@A`D!^3;3Os(_tqJYnoEMH2+bfYYl4Sk7dYW9ZySD`V{@KBH-OodMKMQeY$7kx zYVp-n+>YIh*p%f0%krjr4W2Jv-j);%-q8KYRA=nJqUW{~{js#L7E`|b?d0%YuR`3i z>1}wS#D5`4${v^8@XJm!Lk{YiK!n9Ko?^eB3^1jCTa5lll(tsaT=tz%K=<`u$;Rzm zf@j&3rTC-BjG%Al!Z##Lfcq7IcbX< zexiu#_a{cH$Ze*R)_VECs&=jQujTaiTh{`%gU*)Qc9woGkj?=}rF0<|yua&N2O+9+ z{Un<<&Hemsj~2X}d8ZfrIZ{HE9PwlX1D7f^ea*I}@R0!V=s}jC-9}DzgDr}@9R^$z z-~q=XFCfcwzX!{HJzcx8-V=W>a~@6G-qR<#6}tR@hvL;-wAur|Ty&GVOAxu}T`RxZ z6kP?yZ$li*v#iv$d%fMyy4SMJ|DxDD3vvXC+Nz3RJTWG4(NP)f`TIGmrBPNBZap7o zU#72nV;S;)1~A5&$a7TA{-_I^r^Q#5B`5)mF3(L>(-rR;`A%=6)9xyHK$^$Zhqb@&QTfu_^cCUs+K~3M&gm;HMl35QvTi(8xg5K5 z<2WSF4(-#h@1IIC_2ggHFD=TuPhGK&}1}VPoC`?Ssczf z>j_-w|G^-7cG3%aK?OR=;K~gA2gaBYWqEsW&7jD&}jwu5?SCbe4ml z9XwKVe=8_LZe8qSBdYJdDvuXB3j@M>qI8Ns^y-cX zBCV`74ZABQ_(6KP#|>X+JI2?$y!PG{Xi1-evXMnpZnaVA3rwG_W8B+c?aeE!@8H&I zwZknfpwZ;m0rrr` zuI;;~!PozbT~c5f=LCLth1|Yr`M=pHgztKz?js*yE&?2Ct&{j582io%j@+X?cP`ZL z*rR1HUp&ikKD8;r_tc?3C0njdpslyr1^ypCVXNzV2T_+IEtS1Q^4R4ddZxF_Z$0|` F{{YSgg2(^> literal 34816 zcmbTeXFyY1&@LSNQAF$r2&fbV1f)x-ii)9kG&B|I0s?_Rs20RRkx(Kf^ni2`0wy#Y zA{|1BbOj-VPy_;ze%FTcw)@`i&zJMVl)d*_Yv!4mXA0+qfu1J&0qz4Z7>pfp^O_M1 zw%Zp5+j-}oz2KXx)KHE+E>NpU*mPpb%;I_z11Z7V!rd%JKW*3|B%(}RayKE6PKE!WMpW~=%A{U zsQSdI=47uSTJr%V_nP6^Xt2HikJp6WNjMBv_Jo~BJ{jLM7XP$$M_N@&l7c%2eg`;0 zY)bnMSQ_tdPtveVDLM@Nc9!-l>`b^?Fx-Et|lDx?C)0$Tw@NJDRMwEEP#2uMnhU=PTe_U4zT6Ie#?#N%YHv z?8$2hE640!>K78ObX_E-*cR3oES>_|^r`ZsR`$tBnB-;U5_V^t*$soKn+yo^!V!()Y*_ydthsoBm0mmGGZx8DP<|_?-Q`t4d*i{EIpkHaqyknvd_VwL&W^F{ z0h5)QzR_-zeu>C)89lawhCyEg!#_yJi}@eWoHO_bGCq-TfRK|WvwdP7#l1$#b#HHv zT`Q%g>_oY4O|c2wLtI4w+JFS2;KGl9y-u>oxu3jIoS-~8jL{K%-Oy?3H=LG zPs;pHm!Z?KGX$nps1cJ&K5iG0=v;ALGN8scIJCce-ZGaO3%53MR-|2KSu`=`i*uP9 z-=ZOuUAO@$)oey1U}J6sOBmRUvd|cY~F64(;(SwO9b>}CaCyp3ikF&Nwh|{X>etBjS zaDqRdBBc#H)bi!yG!a~J*IeV+MPigQ4WJ`rsU9f6@%;!kgDX_0x<0?`hQ3g!@kcG) z)jV0ymvfRB=kzDHki zD~L8KQj_wBU9Ye2Y zr=$QDLdJnaLxf$3BGQX`M?}|3yMi(X3iA_;%di6yPmx7D#%0jL{E(AK$~TEM5xX$C z{w~#~E&EUTOv^=fXOS>0UxTrBBvL!!a%)MPwkWv#YuFKBaQDaDaQJIij3#e|8h<{p z87`xFSIW@R!~`QD5lXXa!dGNGF#p@9h5b+zy81FPbj!X6KmGs1&pk7zmSfrVvGv}N zvzXKbT9(QTf6GB-2Or<^Zyf@>>pKku2))#kAV>+m{k!zDPE^HwQZ6oA$`o$)%ZI28 zJ`f^tS5g>cNOuo<%nvnvY?y^;H`Ou=3hbu$ePw({EfdfeQusj|OU)Ce7}vr)yt|lX4)S_S#WuWD z&Hg&f+15qXOMTAnl3ExJ+gJwoPuzgaLimEj>BMRuUGe(-@^LN2P-Dy%vZizTR9#vq z2b>kD7#s7;b&`#!ynrIlRncZ^-RfDpWHl&4{uKh@_NIC+M=n8Chq`b@elqMA=Hy0U zyvWzESxm7-W$fO#8~G+pymo@dT~zAof>F}~xb5a4=vX124LQ>V=k8V+B^=f4pd6qU zp6q^qGV0?Ca_xug+ui3PQ*l|rs^D@m*Ou_|PaItgcr8K9)+Q~QYvJ7qv^?HYqd8z~w)25T~$jITdQ)RHi}X_`WzUcJbtVf5nR9s|%e!u-4(EcuK|} z;#g1D3kyp%$?3lfKtt__TTk}E64M64)&x~yIJnu|)yhSQEK9`QBLen&wu`t`#_L(B(Hr>0&J}6&T+jtR$UZlZTX)z&w7!HHm&+s zSfxg(Jl@(4h!m*vRUr1kc9%d<84y;naXuboGdUYN?A}*Kzup$tA55GTo6bSbyj?Bu z3CBSCgB=C22lnVV=c%y+5tvtz&iz6q!jADb%r7b4c zEz&RzK8N^x1^!IE-*GWox%*@Q6k@QS|A8)PlFYVTV^w*w9o-5Z5%yw3`UKjoYh2(G zkJ2svSYT5dR6kPpYPcFjr?eZwjw_-jUi10=J`xcTG3O8LcLE784X%fHBJ}QS5d|Yt zs4SOjFrYO zK04U2LmeIC?b}P)gPBbKl5Q*8XyZNeBB)Qu zy)0L4(1p}%IRQz1!V==ku-cz)Un;%vl_{rZD{BAY%`r6BS;odPR_#~*#H;eK;UR*H ze5HK1YxcaQ(sOsd zZK}mcs7T~c1MCSUuaAK{?$tvoy7a|=ZSgi;qBq)86RU$si)rLVOhy+;b?#TwcDc0u zXkkd*hrux{RC3(kF!L#rjd;a`4e^I%KOz?UkIitSsr_AASB>^;8+BTXCC%3j@BXk+WsjL$^2l z5fa46$%|d`F+KT>!M7e#(MqI&=&T23ROy$Hx;!A-A?P+#pgKj#u}h4TwV1!2eVg%7 z$?-(L&x`f%R-@x9PokBo6;M#(fZ7YmYebcGXtm*5ZJ_LV@i?a1;BV=c>Yvvo63{a% zN}=zI^tItqEZgey+Y;Woqw~RZ>60)H#uF?bju{)N^R1CDkW5u#9zxcYv;WA%mWvTK zCD1)zfRNR{KoZgQUYlDn(84&u2^DYXcuy5f*@U4ym3L2+U;+b-?5I~@qt$HHJzOf^ zmJ0hgL2x+Z!8pIJlQ3jUF|}=Sl}DwR&CdsSw_y2h<}CVet(6uCrHDsyaYb>c`gqlK zuZfF=_NXpT>;}bZw)S2l?&+3xmmns5v+LnENtw<)BAuFcUQzF~s)pXU0` z(7T$@dF#!Xn-UPF52a!7&}xAZT9;xRbj1QYUzX;_%I^PXnw=cIEuhiB+A= z7Sq(k2de>1rU|d@+z-3?m04C4FB@E>8O#UQuDoftXpW8NQ`X+KebQjVKdM24Q01QnUsV>-bS^l|Y(ABzd)>8WS0rbH6luy3-#MInw`ySnUK-h;r{O5{X^ zwo>*h=jdWLntr<3Y=Z*H4?vN2H@{-F#500i=ETsdR70icU6Q(EgF_XMm7U!(q%u{= z^uC;wXx9`H*IJwyO)o{g(Zvo``rsu0;RVziRu}=rve%pPW3}THO)Iib)Agm)^aT`l zDqtO-#gq~$+}`)U*C|p{6X?Aux7ST4F5>O`_bioJDl`!#wilC!78~4qe%)Jwoy06D zFxPTWmz8i$>(&#e9WzX{f@Ws%h39KosXm)(YNz3P=Me;> zV3Jd3_IkIqLhKw)3v-q7$G0|6b@@Jch9jp+I*2{`Bulp!3Dv7D?m=D?7aX%`ONjc( z`{EYgc=%)7gID_-$2^q;O~rk`txmVM$IiwvDg?KxO+Pt-=w$DIdB&bD0CO!I-{c@| zH0T6-EyvdWUI<*Wl+Fcfw7Ws9GDIGm(%mwXsGycpvn_TwBz8vu+x#h@=s&STC$@YU zavy*#Z2B8h-?Q3w(I=G?4iyTK5Y30V3MX}{A&?&)rVss#@$Ike`$JSj=}HpSGTWkq zf&;9tQ;%d8dI*?ZNRRrbU1?6u1;5R^rW;kvn?~azk1Wb9ru5bHzVDmRVj?w~!>j>m2o7inMJiY2}P&q(CPmmqQek%fN2=uBf&-!dw*!?39# zE*cU74BB6)pwxlP0ofGi&X^JIBgV=qxkmq49J4!MoVzpP=v(mtQF=0Kb`cl4wXb*3 zzDx;3V=T9~vDvMCY;R{%6Zm-31unow9oC5B^BA_v>%xCM!0+B2i2k4=VRal1 zd6CZ|9Baalo8SC8X;T5dt|Uw z^n}c!viWp?s8zjIzdZ7s5NTGA)vUiLj?j0&8$uLvF#Pd8^`_^m8Ub^%1Z25N)6gV);kmwbDVtr4Yv-ooDDLwh(vvU8WtR()uG>#a6+V=Xpu z^4Q|4=W0QA{6%6_5oI~nzo5_C^*1uMzlh>*G9%Vl!{{yN`9N>Nw%Sw=c5b{NOHOH-}LGMRI-t= zcZSaT3+cL?9?BW#cw}2ik8KYo+b)k|yjlJjjmzn}6iskEa2IeyCBe6o0ialP6iWS7s>`_tWa1MnV=o4qbclWzG(vYAd<3 z*@7qdWavjEiPjbN4jO(#nf*d7`fbj@n**6SLXKJY2u(H_qxQ4j^kCW5Pwi9D8jDpm zef}wu^`g2>uikH!1JQ{uUQOLa=)XGz?FLQX4>H`03)T|~llxXK^q;6H@3}}Q*Uqqf z>(h*39UJrRE<#)OX8evo?)7#d8Q-ae*a@s%_Z09AB8_p9M39k6=+$*Tb{;HBak@TM z{t8Q=uon4BduFw#^M@E#5*DXt{YZg0N`c6|>5owbU%Vm*zHlf&=-Au%k^zsTk{~^C+G$#li=P#Rnm)vO|7Y1Ks-iOG_Mk*VU`p$OEn8>+JiPrV zaNR31%N%`mE|ge{Oku5FP$OHWiK*Z??eNL=CwF@s*GXrKxbgBWX1M7yZS*_E8OkMI zXb*c)w`uknKd?Kp9wGGA?XJt#%SVMos&H`$^w#9Ei(4#PFbcR4?fgXzOzsf{1nyv6 zBX6-u(S-eG*V}C=V;u4Y6x1O|tDVBuO47n*wW^4$a4v_I0 zDn5vxwK4j-xI^{j=h1E>*!A1NIk85aVHwJtxDgTU(9U5{*CSiy((>c35l`3p*2YB| zGyHE)Cu>)${`NOlpyILCWQk1kZB*U|4%U&Yj(>w8j>!o6S!9Cz9oJVwSy4(?{i&%) z!+4qY7a^sNQ-kuS^HW&w<7xedZOJv_BK1;Ie6Ao=}KhQgC6GiwpO69;ke7ty?W5IVxs7w z%e+}rUxN=wuSv{60+VO^JX}Di?T_K)RunpM6&hc%z zgAfS27t8Nw3`#r$CWN)ox?=IQ(gBY=-QYa$;|7Glcz+Pk%#^}zywC7)BWq@xvj;Uq zactSw98}GIb3#wI5yu%ijKf&{@>&+r9m|%F>n|FZb7?s(=Rg=W-MUqkUN94VKPX)9 zf82@V9@C1%P_uK(txmfPb-jY+#(~N7AB;UbT1JKeVS0{3(3V8EyR|CEZ>(98Ee1rvuG2;#@5$arJm^FnxcRjj3n(c>bVlkxWe-Mf+L53a zqm&PoJ5h&$x?$v-S{QXo@j?B`-`f;~fBRecoPB~KIEvG@(p4diqM{4Mrt7gO(pwxG zb@b%zz3s0-74vE2;nxlNft6Do#o8oN`(5j=#?|jb&o`v{S;i-^^X@DBx)`EU%*G4W zgw26~X26Nwe3r#}+Ir+Ai!WwrVe`)}C9EC zSg%oAir{}1Y0NgOB0No7{{;7+QR8n3L{k+y+t&W{wkKdw%uRh=TM?Br4!gJX_v;Wh z%pemudrO}bpYMxHv5X3NjvpoyI)s9@zg&v+p;+d#mUSPS31uSr9sK!;N@22sKmkE(BHVQ@|N&cPqx_;4$DVbu70au?wk>bII!mf#{yM+}rN6=doD1E^7{ zg~hry>pN=frz>2uyf9~Q@h!6*E<%G`aBz4SH&hLLe&=CvYGPcCaIS&_9Os#%_zj#% zI?zCJjb+*wsUtNL=Mdu7D;C=1XK|!aSETf8@3>D;3a}25^Yr2iV9Q`FyOHSbG zZ<*L5f1Z9;-{U+0U5FkOlTRGfUs;|Zw`BRt7P8fw^~R*jcxU!1x}u!28=EjHLb%-X zLW2Xbcc!Ozv_WNRSQ^9*)VaQJ)i&$KNDL;bUfFdFcUyBfuQG1%UE_v;-O4TmNvl`} zcQI#}i&5HB=^FS-ioQbz!teHyLI?F$;5au=r?prmW=+YMnKR~a;>6f05s~el$21W~ zG?E$QxgGr-&6ciHS7gNFD!22OZvf!x(dpqfcG-nkRh15Rer{gk%gh_?r!zC-7m|D8 z0w{4_bQ-o?PR3Ztt5ahJ?(;B8@8Fi>ihvxKGMcCPZ;qhVDCOH+kZtjiO1G`0w;7X zO#iuSB}Tu3@bW}tTWXPi-=ZpF-DEq}4%w~sbr{lyJx=Hpv>(H!C{QWe{P=Rv@}Bm^ z8$K%@`y7};F+Ew9I5&DJkA}llKc$`@;gv-Xjgi76m(lSZt33{8eN5llh!170I{d1> z@orp=f3-DeuD9(a=y#zK9`J}DcWCdH9~ya8s?sM;y*-00@%xy4)#0l5v0ddhih(_r zqsMm1Z#<^0Og}4NSR#sXOm|TBYrZ7X|5@YSmQiX#k03%=*NLh**Lf6;myx=&3igAl zKb@H$(KbD zsyJPLmva8lS1YAtH>s$VH>M~D+}brx)+-W!5>w*@(sXKbxOm&*Yeez>E%yUyr``Km zPC&wV*)Tx^tW`m5JM^se>HVo&w!PxJJiF6gVNb0nJ|5|K233*)$bCZ%0QSoOuVehNM&Pg7xecPbNgR*n893vusYmjm0jhdFC_e zemb4Ne>kFn6D5BG^-HhLEbWSH{q~Pv?Uo))=s2dd;C`^i+o-pt1FvT{8+*q}Qi5Rm}mD`4xq?iWVQ6P)t1^!1tjVK+3zIpN24N-xX>tuie2 z#O{;RsNS?ce8GVew?2K~YxKwmowJZ~koTo|k^1j^Qxl?dE0lXv>_(P zC()hSCT;e~Y*?hr?7554DFQ4Jgv5|TRdaV}VPR*r0kHe(QJY{u}+V zo5%^v7HkY(T-kk8*D@ZQH7#PU>2yfs`?-@g$YWZ;hos{fPh~Y9&v}41IiKqqMh|*4MAz5>6W$94MJ8ha>e_6W4sa89T zQVMr>N#z9qn|7_|ZgS&#XP7YLlr6`0a)L*r0;3uEuotQz1bxRt$#ow@TFd2?>9k6Q ze9TNonZ#)eJADA}R;eKerBadV>y!Y3H|@?h$pd(ivr!_~w^F%Q0Iae?(B>J>M&R6Z zQ_~*3Xqp0HwcW4W>cMcTnvFveDhZJQ{GkvU?AWZR9^`(2bPhrH5&j>5q^(TtS?UyD zU*eMqRHxL3Wi#~!`~&VzSb9j&4XJF@pIk$X+L{fsVAr&pVApRA^(VkARz9=<9f_do zG6B98()=ILOH0y4g4K(7N^h?-PE@XK_K_(w9Qgc`0%(l;5~BKZ)-kVaV;#6*k(Ump z<<7U-1nFwaBAZ3UMPKCRMf&^p1OO%jUcj2mIR48cdo=RyzBJ^pDXo-0hCM_uBHQ{l z4)el|#VKl(;_pm%3DE0GMN{S6;5ON@2nRCbn%X>ni08}-W}*u0_W3ga4vSNRG?gdD z+zNCpnL_+T1p}BNi+ne3z1~C7>SuQ0OrPrIv0xQ)TmLupD)@MK0hW(*GH2 zr8unh#C7=`{mS2_*76HerR02(M_@RCbXDMf-##VJos+;N!i*5~U6r4m&4_pa8!i(>77)IXGF=@C(5o=Ra5Y{fYLN zY#wLiNP-qRfK2frx&lL=RR)fQvm4mO8Cq|$|sSCBorZ`M~~SLRKEiOx*B|H zb~Qs1bay+l$HT@=%x}F}cD%N|1ogZiqA2iDCs;h~5WrKS+x;AV^urrA(oVXK-t>6Y zN+|%#+czZNk>-Lb`*d+hE|*!cO9y8cZ8-3ZKc#(V>1ShVw(FJ7kSEOj-<)IT)i)ER zk{5Ek2EAXl(UTbNi_~Y$rM3}vElkdtZL4}a=0-h`<`r>&?Q6jnvF6m@Cf22 zbhMuZYIT7!Lv{420Y;8Jt;~X=(~6qu2~s)*KZb0Y?9L}Tc4V|mefDFJ+xNGBcB`8E zM*0%Q5e9`rkdMm_-)9KM(u{Lvfwi=}keL4~^VWmX+jQqsRjX zhT!O007{dFUt)r4D&1u0e7cO!QjH+N10IMMdelLOHE9K1Ewa#mp%eTTq6f-zXN~~& z(@IFP%ge#JJ97_Vf3 z#$=gC#&FR#hG66!V6|Hi4ES}NnzM-ZNTneMg=ei$QVAP;48|X1A8aWZx%pr_QpYOY ze3Q^!ZI$b~01Z;LK8TAnZ<87|X)9rC%b_TCW2PB?%9Aw~bA8~LvX4O~%MAr;<(M8l zL@^o))a7abCC6oAKx<>xumW*T^ZY~^GzjEq4z@WdkDWW_kQJVFeFpBZ?O|>>DQes9tQbsCOH8nTQFx`-E)q3%Ca_E5Ll%Ua3pRh*8Ojgi4u5{Du7 zH)CXZ^7zREh$wRIQXsLOM=_|nKJtB()|k!!&7`VWOX#-Is)XrfDQ;j@Wnw)bg)RM` z4k~lt%EB1ii#2nhI{q0p&6rrxom#HO;@U)8GfctX{J(Mt+#%wWnpUsztoMWRk<_y{ zxORYP8!*I}Cj8$u3_6eZfyd3yB?w+HmHwKLN%>rFxKLM;YScR)d~!x9(pHe<4isqy zW%JSO00Ov;D-_Po^Nxc*Jd@b*`yHirn=JX z0pGiI;JDs~--BQPFcfqblw(?Nav@%AaXa3B@Q}X*Tmg(*ok4Iz=1nL@OtvJn5(WV7 zw)^PnUyN&Xy!vJ->CA%GeyBa_0BAi7b`3Zx6zLa2ZP=Z-o%t_7}>BSlv zq1+4ok_QOZ@PcoMgxqC1!;;)Um=i)z%$JPG^T3Z86nkdE8zbhwt68u0eO7DY&FP62 zFnq7sV8l@D!89YI44WKtkVR;si{)Drgt7MiYghgO1QCrXsgJA;dsScbArDrSnxCg!A|X9J1Kr`vahvX;6Zkc*x^ES102% z9m~X^3x6m>IpuBBdAe`dl&!SjJ5Za3k^vSn1RMD$Inm zAIQ1h?a7(_-}@xbU68lB`opQ7)iKHMPkIlhXSaa8%7Px+gaMQYOeOnhCpILs4)(c2 zh#4^`3dm)xdIr1SuS8z6I!GS6PS7}A8qF}9wKaV2u?jM-_68$RGky-5&ytb# zD)|fLONKKL*woL16bat^Co6Tfs9%Sy*-3u*AWnq~eyqK)xnRotJTEj6_6w94C(b~X z6GHH7W*u`saywPrNxuC&S5-$6z;;3pxCHpu|LGE-1=9R4ft|xNxN5a1L~K#gL`6O{ zBvKan%W7jjncf^rXSZ0H9!*~WRsjw6Pd5+l%>gqJ{D5Ep7r_rd3Okc5=CfRkL^ic} zXIr|PYPow;n{=?+!#JpQq#gz;rhQ!#sgxuiz0^Ay)7Fi#>JDjD~A6`R|HT4MO|k+aw&zHl&x4s#R%NaW$( zBGNs&!gw4Y(xhQfq1cJMLOPcdYbIfUROIF-p#ob0)7Qp6@$-G|EhEajA9eQPFm zXlU`F)jr_tTpt|)+vb8YO`{u>b6YhLFl)6Fe&yHmgpm%JxSFUHOYzlktiF*|Jp!3; zQ-7m0*59=&+BPoo7{X1Wf-qbjIY19qU}X)7(T@q^r?6v9DF?<8E7R$S;LxmnDuw&v zC{Nn>D7H#Hx5~@U0R5f-?$PxgMAPw|ZU`BWqJpvuDC((;iLSk~`g@ihb}D7w zj-)v4NiRvcU3l6CN?3QJ-eYpwW&KkNBN=ZB0y;`Dm78Bahaw${qAHovaVbS(Dqct# zPc>ag(B-MJ~9x$gynvvnLkxWwt?Xi+{nwXo~1a5OU?wl2O);EQM6)u#V)Na
  • *C`J9xJhX9H6d-TQbC z#o$}&C3?-s{CT;|*^_*rNB}i3+dn_cUc=9<_#)7nT)<}bH@)F zX==o&)id>6oLapxr1|sxVqi$}yyxI7B`|cXt&I7RwmL;Rr4K^MX^{Ary#?9Hd8$25 z9`6~Zstk7~0YB>YTJqA%P3xKE3vDN6&*w^~Q#`cr+F0Z=yvGwisdD2xWny9?K|k3#uHhuc@%QqlQBbcNBAe@WizRyQS!r7qq@+pr~w(spe!cIekg)Wv^Oo zR<0(8zU5oZ`#l@FU>A>o_Yijk^(X|{jN%Ono!%45>Pn)lU+~7qb=@b~iX0yOybz_S zXePjRsh;?cN0-adN%)N;^(A6>8%s7jg%POqC$zrYXSGqWV1)6e)USf1IiC5aqZl9B zW~DkNN%yXX+hKHD7m*JLQM*W3v!tB@=x`+}|EmHyJ7J+*^4j}ysDi5f=p}ax3w3PW&Z6)-M*W83t z@dJqy-XEzwZ(QS9WULFIfk_46Jj+7jMR+v#nr2j2-G*Pp6`oPG2vg<5{=Y|^%~E70+B9=YdlNg2hu zi3J3J!fu7*BkLG1yc>l}i;g1oGS*e!14C) z;W+#egwv)LC!BWFVzcwu-z|!k#+R9y0{1Obs3SA!a4E5iK{#vlG-v(8#QdO437jIwOLyN=9qV2YGM*T;5aH)_|U<1RVl4 zZ&g^x3@|a--mNe#nZOiJ?Wz3sZwWyTm|A+cnvfGgN7&rV$V?a~GFHTgvwo@?dN2B&Ba-?g(rdI84Zoy-X!m27D@Usur&OSX$W% zCO~zH8xcN#F23Z4sh=8~6*zFlN5gnSkF;UEog8#1J%zov1?mKzlxh(=d(!H3O;)5# z@*IcOidgZw8uyw(HZeEpMv8Q)f6VtDpNm2Se*%f#jyOuowZ2`Xy?NyF>}9`MkM|}~ zT{5*y7s|r#T+R&}Q5M!_wQ6(RefW%1dQuIE7?oRH`1^WY6zUmC4@WnJ&nvOYvciH4 z*RoK!9PeQf8*1ip0OiYoVK`#{yZdRD^qM#x-<@I!AF0*1R7^0!Zg>nO_wZLAi|iWP z{B(D{aHG#Ms;9wwBiyMDa$}(GDu0>o(8Sb??+*JWSyF$M=9KNd8eoV)ZW>bva&8zB z0;fHn5^K#BEG;_%MtksH`}9!>(8z0 zjbpXRUKztfSVvVsw+o|^a`c0ew?;K7Jj|xxcvW$_8*T=XFk@zhZc{R21%W!h(}ymQ z{(;0%uwjdL#i))@!T@<+X^(DK!Cv%zCcR-KQ}~^)&4xvJ0Nd*~9?h@#>4=nVGnqY`VG?H-}KUNqcq4x3UX7C&lO7hZGUPGDGgQ z!)vj>0PKVlBw9GFgyf*9A7~%PAIjlT^ojm z5kFns1v?5d@UPG$u&;0-Ub=e7YWB@3D1lB_>PG%40K;in+1^D6PWpFhQVY|ID+_XC!6U7b@>Y;xwn#H;)Z z^&gvIN2+$8*!{U#@VVyFxL>Zn(pQz4+k-0ggDNv*;e>t=r!yJpx}ztR!P(+jR6lFc>o{c{&^>c`K7cs)5ykp)3-lrxuejM9)~~gl4Ge^_J$xz zMcZN8`mXpRH4GHEdq?UUP?@3_YYp?7yhX?l0+5#zxpJ;`IkQ5iJAI+bFZvc&}82o>QWsa zcM0A>HR``5m*2#E2(E3luKpSnkJeEye3Vn1!DgQaw|9H^yHl=zdUOY(-?FbK_>G&z zx^sW3*9R*H6val2-edM;oZPUQ2lr@sJ(%R-7+N}FuZAJ#%_fAwB}fib3H%TnJEs>~ zA<&>m4Ts2^d`Z+O&+A^pJy@W%rgm6VMBfuLpG40T<@=gl?CKuaI`Pa=OHpB9mVY-svzt2n}3R(cFHNr~p(4}M(9kxZJ;6fFXOTw#)J zEVMpgm5M713NS!3SFCKGyY>3m-0Ceh&x7~>5ukb`^0qJELHNt9{#aVoB@eHbjdFFa ztkk!bS1X3G!&E}S)^~xwzo@ZHjY9)y{rFtGwPK1*Jje9#f)6z;`!&Sp#M)fv0Nr_ABQ5 zJjR%Cb%rziQhWSH#4u$lvmgDzMRT)k#s=U6@6rxyuXFsl;~sa)A3J;GC?zj* zwuhhD7xVaa@v~3S`vk@F_)qt;oZh=Xik$f^MSt!9o#}q@#-}WF5~Db>N;8~Q3bqZ9KU%v$ipvngZ?xt<9|_Jlb+p&-+)NBRA;Qdi}SSN(!+IWL;je^R;!ZU z)anX-Y6AUQ!Vt;lW6cG`7lprP%hg#o;bz(HQy9zQd#@=uJPFKAaS)dlekXQJg?zHP zM1TB}z9zS;TygePWy1jaYhB_x`e{~JGtq;rpK6Vc4^*Q4Y1bWat$P}oAjK=$xj(VG zlj)0Si!+I1>L&Pn_qM4+%}Vl7ckxKRJMS661=D)Im+#C0G*1d;IDx4tQ5`1s=Vs@h zr<;*e4SVsOLgJU`J8;4Sa(>LKgS=f5bj-5x486GKL-q} z4x(C)t_J;>cl_DV`sZn?eKtcVa5xVs?NhGOhpH(I+I_z1(+%NuK2l0aFme}hJ+LlN z)qUI{QMyx`HQo8ba30oiaqwqg*y)TI8n?ehEb}xNc6G8H4hl^4$b4NcJXq;$yE27i zx*|XqvXV68yD_+;K>oh#qcH%<)i(@2FML*~SW!g**ZbTm+pFle5d>pz@dTG2x8L@P z(URbSPZimfdjXgX5&UQ>`+6ricE>d(8FHO|V({ylxjC6B+~RDM&We}dppX+wwUg1q z@uPVD#XI!H{uwqge_28L)g<1JgUw~vDGu2*mj$xS1O3*s8JY*(7i?t{xu6!zHEpY{>|PT zPcHA8I3WwtVl$l;_m-P6*hAjbkAGhWf>>yv>NG?+_H=Iwv&z3x&1=>=5Lv4K4O!#U z-b3RxE`Gx}RG~{zE8;C<(RlSG$@i1g&>P`HBc@j8Iz_O2UR0V;AwPc??|{l9<*f${ zTl2E+KZ&BtVXXxlgaVtg{0F?FEYZB)uWR^ZpYg(CA(60onZK;i>NA&Pw^X^K1ib#3 zK`<^-o0hn-;WEZ&w`r5D&tdGq206-zVoO z6!E;D9RniaPGExkR7M7`B7aAL#>-(}>oq{^(#2_E(w(EMa6Qpt7hdlAw%~ymrJG_` z1lQXMyeFuUdGw`?b#jbUH!PMNNZ?7w{^05)x7VoR+3uuoZKZ?2#71tHG;pM(TjN*8l|&;C&-|Er6sdMqjDX^!qz1yZiwM}Ei@C#uBq7%U_Z4M*4UHq+eBBb%-1*+hKv{o>8Htz;(;}t3 z?0)ntg%|RV^O2k|XJEeL2lf9-%M^Mzb$6f{9KLY2#)mk)!`!~`iU*aFQ^T233e_!H zYTP_!!CMPrT{i~&I?38a^{d&7aI(p9^O*lr-h2PE*}nhddb>*(?p7x?YL}ulTU%Qr zs8n0j2)CLs;x;0+sV>ys)F?434J~3MLZ_{WEkau}BGj&#?-_l)-rv{z@p*mzg3tBv zL*&YJUFUUP$9Nvk<2a8?+zWt<7 $*9Nh(tEY8v;J`QYJzj~%W%qnD3C2D1Fpa<| ze3vBtZkei6DSl3Ro0I>8s!^nSe^oEVzy0t(B?SD z4aBaS#ll!#c(J?>v}ZdXot93;+Ozt(0Y$DmWwoOte+uYob-}{GL51!!0?;4VhdDgg zgxz(E19XZzW2SswqNC6PZN3C+R62ECc#*^!Bz~af2#4CN$AXetVWT`X&N`s$S6;Bt zVthQdkT+;A|Hi5%WTwS87M*6W1%+6_M&!m7HX{#gLmEt)Zm>dw0CEaMjEKN(bK!@f ztdb2qkWj3lGJ&?({A?b&63hNwy0MiBDrSpNF6*kl$kSULzPTF2g-hFhV@n6@j*WkN z<`QoFCh)DC$isuHA8lqyrFfeXzkBRaj?Ra^WO_SOusvA4L`<7L`=(I-MVSCV=Nvh9Gk zEmNf+0~u8fAKy=~BwlCb3LyOk05EatY7|Y{?Ww!uVtRa8T~n;jl%-H_YvOu_FTs$! zWu)vo!N;TU^CpOpLM5mLiA~#_y@Y557p0Hqfa*d5at)p1xJIh$C$!a|8j*(hA)_+} zDlKTbDLj}F0&Bi+C{e%!Tn0MDnZ8lh#gKp}P6Xs`7Mk3#mJ-~%<(<&H!FtT*EM+#go{fN%pReLEidOAE{H>6J;}mRqmvs$&txzg=-->^slO4 z6?)!tkB#=Gn?dmRNx9{GRdJJi+z-5KdLUR-?}-d!nCjo-Evh2EPE_1q{~5!H6t~)U%s>L(TW6W}6uqnT4VBG4)cv0OYYSRak2E7n9D$vQ;Tnzsck%VN z`$I-U^nU(YU68Bqk9%91n&}&9*laj*kt#2L3hP+UpG;vs65qyH<=)p~(y7#YC_WLY zo?LLD(my`sd|fPu0F+pL@m~V43?^!gzu{Yv@inFDJ^&&iR8pE`(XCU1Mg0-$pI(0I z07jB7O`embVqBBZ&LzP7s+0L!RK-N>7nZ0f!fNjB_F4db)i<|pu{K&1mOs1{;HPhC zi=C5yk^Kbm)|;@QiH9~WmVIIJyYR%E!n*J**vNF5>K50ay6;6cK`=r5S5&6N@4>7@ z)JGd_o#oSE{y1L2I>u$nKs5U`sf87PdCmUKwZ%H$_!-D zNzRoS>`dH4(DQb6#+C$OF9suQD!dEL`PEIzeS4{L*)oIF#2j&|S6#z=k(E@LRWsWf zay>Xt84QGErSZM|b*5R@rS5aIuWxPppu8E&D^pu<&@`Y^6*i6buP$YB#9yK|Cswbw zv9x-5dsbkxG^%0b?Yu?0AYL z&5#k`ecSKf9N}(V(VDC2nKLFyy#r~61l%M!Gbiqi68|g1=&3E)#2hKAvkb+9M0Xl# zI;#Ozh=#Kl0v)e`uPgNv{OBZJSMwjw#Dg+225PJ3W(jNTqnWnu$KprpPAPBq$jfi# zJZdCUjAVIu-!3|xH2aqg)UYQ#P>zY^8Y%`bWcXap&&Dggfm1w|stz?E=%_GNw&^NN z47m$tjsGo}wT95d*tKDCU+GkuQD^M;75j_^cT%-$Zgq@oHKRqMm6 zm?2*d>ZPN++INOzF9zGXK`=y+h;Hok&uS0aduNjw)dVHO0KYHDvCInuWncoYpm;M# z#Uj~v6O0|dEsga#)aUriP~6Mh{OAK5z~2V@Hy=VfQrQ+&S8o$b5#7^+5S5$AILGpP z3UymXfg+3d4}8AC%GK6R(XE+d1enUEz4lz7z%v?z2cu!X{nFrBudsdIVhw(URixP2 zfi!Mk)QB<qfd^P2?nVc&(vGoX|IY;X~!D$^hSV3=i>sgLSS0oR_q#))<+VjkPu(TThkhnA z?M=~|Zk9*4KNekzCW}x?&Ush{#;U*cd`y|DkPdlRm@i-eRSFmYiz?L{({fHL%6<1t zqq=4wDDnlUpe=WD3K-=e)9-btQA7vhoKL$hF@gWsl?$N-Ry+FTvqGJI69G@q&qi@& z z!NPGE$=-EbMD^90_Z5?ff+T#~E%Q1m<9u-1UbYMudlJ?ZzPkV$Y2n`JHXI{Ta_gMSjT7OKb*cJW9*{;ks!UpS2An(;MsHCyW`Vu} zlB^&{UA#gS$WmPB^Fm33QQ|TV4iuz%Y&=OJs@y6PJw=uFffBcJ2-TK4St#|gi)HH$ z&JJy|ii5unY<@2-&Hs*LU2i>qqy6)jyL&GVk^)e`Bepj`bB6)!^iWrPXAO~=xcVIz z;b%Iwl=rY~^vBTaHT>Xcf2+nIdO z%;oSL0O1X0DCFIYz>QfuNY~*Iv-ruPb9G~C8V<@%r)TGpu%&Sk2}iK zfut!!jq6mns`PiwG#^)#CzBsENK2<>Cvqyn2?VnZzB1Y6JeJi`OO#B~X+ujP>Quh! znfPm9n36sb_8OO{-^7xNr{>bA#~}i_n%MpqTjT%Zr#oW{S9BrG23vJ#X>X6^;LP)y zU4ApXqM2Y7Sxrlo7ve8() z42*!mRtcdAV1&ThN3kWTh@TOs`AV%!`#tZ$#9_hJy9yv;mO(0X0rMtDe(H1L9y`iVdB2RPIuVwljfA*w-i zuwI;Cm$Cl3^a^G!w|0(aoKUo*yxtjGP}zr;S0rO+Fw-M%LSU+XMY~pCF9i~!=3if>kVftQ?n-fsG%D5)_*iHqRdlPj7w<*6 zwq8(gf72OghlN>xvbnJ7AfihiceL7>N{L#C zSHSscE&iSN(Dz5abc2hw&Wt%4c%BHf0G^7Ut7;m^wzut4)yO;K8li|O71dA`dB2pH zbD3(KreuC=&~~3f;FdTF1o_DCxad16&0%Y{2L*SXGQdppnPb6(E2< zBEUc@XTr5AH50kgX-(&PW6Zf`!?&dRCPOz~H+<_Wkm4F&(jW5@X|-kS9mRBAokvO5 zgwBT!PsFW`3Xa>Y2rO|xe?89_(8v4I^RQj2{JwF&;aB!Wcm{e!q%(chzpjj*x6fl# zkxdQY0uW;e5sgXLGWl9|bQ1YjhNF{|rH9I;)ovfW+TF|ZFjdwzBs>F_rFWU-qt`|a z)}qqsMkPGWeR-xUw|GS~TXREVrPSJ14x>0%)zF!;qj&MX)}%Pwytsce`^iowON#c9EV=-I@_gNV znl-+`7H_wfw|jZ!ukg{en#{MZ{iT;CSpFhSrP=OPZ9J{nyrP5^^_EVdp3LQi>XGzA za}oCeUBX|;xhx=2|rfGcij!}X!#I`kQGa#XGiH~Yf;E-e4s&@NRQ zK`v?Dhb$+_%b>E2kcy{T-=h7=WU-R08MWp4(lqvYa{$0t9C6--rfG_OEswQ#h*TxOQS2hrX4lB)!i_ zB1cB=){QAn;9VU^&dqc$4}L(u`G(#s2f$O})!cAs%^lJ^IrU4_=>F2N?RMKazp~{6 zTHZ=Fe?u=3TDt%dsh$$05ju5RGwH)@LJ`t=h#$f$>Ty2j=lGRg$3$JpGKP{0l}y0} z3?g7%i|Rj<>*|Na;N&*?-dJ|vs){o4^@D(7^hTT!)k^7mF0NGL6D57t4{%G4tF!91 zZyF}wplsA#HfH#au=rLYXNKZr$UklXE#JYxvqxno4K7z)9^{*11@;RQ;t^0_1eW)$ zci&ix0JnV4HdmtoaCfEJtKr6->WZMSvZiIXt>eA2CzS#z22Uwn$E#qhn1{0ht4ikXkc@;(TkRu`;?u6!`)MljxRLSdQd=)YF5q?gN zy0Sil#UdPC9iS#ADP*PPu`H~PQs;71L2l(;C4J$Y_VxteaS|2+u;#wS)}cy&dRCam*!ucY^yk*rKn4GVGOYpP=p3RM(7yS324By2;vM8j; z4Ykn!2_S&)Oq(Ah{AUy#m?JPV&VFD%LZqv`5{hWL;#oguTU zFTSn}7kdRS44&Hce)v&Y-%?YgAUE&;% zAHA)F>8ffLg$YwLzhgrln<*0?S9F9b#OMpMKr1!ox3>Bl6>lN+jX6$*LsCs9EwkYC+)*FaYphR_$!FDYtQ&b!GuTv!a4e$7gBG!HbFa97 zJOCQjK|S8&WE>1=FqE1McwLGQb|5YCW-p(TQri3gjK#@efWglSRJ3nogcuf`5|b{C zK`E+z53Sr03x$te`J>Z;^qzbDPZ`$?TxjRq5&U%uoES4z6G!QCKfc69V|Jrxh?pY05B z2iMT44tXDf^LwvR=htmxu1M4(F|PEIF~M8YE$DG&HEJ42+pMg_a+g5fgct9j3zi-W zVKEEX1r~kRomjuMXOW^t9oV9S$b{zs8#nsa+6v~If}eBuEDJJP8OH5mj01u&oa%|b z;_=i~Wha$(=T#1V9Oq-7wJ^H1s*Aud&QLbhx6Dve0Up#Nq%J2n#Yie1dUfc8+qc)6 z)I+Kz@ZE|vb4*tDp_|u+xB|Tg=ZJpd=is@%H!o^-{5tDZV?V&N@d^!oaQ^4L2e#E~kPAY7ym~*gY>I+!4R#MnX8^Rn?K|N-%r(6*cde-5gYS$D zxJRmhjaQ{WHtNN!w0cj)&``F};?=}U;;l$m#NnU_05%^KBG zRPXZo*6 zu4sE_!sSUuqY`v?8Z^rN)hRG-e_C8YIyVv@y@w{n4A@D z#YrPE4mF6ttOEZFopV{j<@X;=yP4}^ydaO}+HVw_Pi9HmqStPy0XYyrZ35e{C;nfAIF5XY{On7HkK) z83=!Y>vPRp@?(7{j!d%%zD9olSGL8#u>+!Qg0xP2PS2q~!HPdxq;_iMX@zP~*r~f$ zFsPs;^qA--i-2iUo+k1%iW}{E(KzqwRxTLX(P+NJ#08-7o`-kdYai|= zw1lo^N^A#BvYo3wHD4soMYono$l20Hp|Ovjfer9(|k zak9UD0@lw%uom@yc58QhYeN+)+*xse<$W*6tAIr`cltiO?2Q#}^-i=dHbZrvB!Xox z|K#0dw=mvjS9RY!fAzdXCs+V~yFKsh2*>G+0j&&u_Dx%(NzEuBBjx@)!ymj9a35F>XRb$YzVZlWYkd@jKE4vI%*lkUC_x;l~EzpcN0 zrx>W&>S4<^d20vXt2Or6d{*`0vc@5dIr=_{L{(wq)2hy@Ia4j0f03kN0=~PxC(Ho} zt@a{ZEbO^|QYkfWb0oz?z{e6+mDo)^;8r;mT@^wRY^7U}WmkSJ7<<~?eS zcy4Jt6jA83SQEfk*irlLW=450l552#*`vp`PQvTyaV56Nf<4u1^BX=q;}ev1ayRfB ztO?3gARiE`d{~t$kLO`bXk&l>s9DX;gRoPsD9qiL@8B@^eO6mk|fNH3eMwk$K<^|HK8{&K>PZ=x^5fzNC39mOs06p&-~ z02BM1KXiH?%AH(az}F(bY^p=%P+}cky2%AOWD$&glM5Xk%&&9G zaol}p53xq!-%!<@hq#U=6;`cWHrTW?wrpP}XE;q(J~c=t1Gut%_I<;xnLl2Uv(wZJxI>8#^I8(}l=OCQ_AGnna9G_Fm$pUho{D z_1Cu&!;6QdE#NYP#+EhDo?zuYOlquh-o4sRU`&Q`fSDw|HcgAI|Dj*;Qe^OTe>RJb zEH72iGe6DBHl(M0;bwEhC2>lebo&%ZviQ=Kn^;Ukq1>#zCkkV2FXe%e`}FnMPCTPk zh*8k>?16sZcns-RbTPV4-4aGT#vNg?t-V}OA2<1!%6WWxx9UfWL3hJxXG`(MY?IKt z1^SiqHrL10OhXfUTe2Q{H%1hP2;aPx$5m;)TW?|yueRoaB=t$d?NDGnm};ktlwJE* z4Eb1vHo!dEj!6un)M7+mfKHUCbat72_W?hGf1us=X&5P2dvtL@!8jo47ctU1==S6| z))=a?Z#dg|{BMkXhH22(Xtm+R{jKJsgV??CR&SF(>F=}azgB)VuC^N8`1twsRP@m= zH}{?eW;xh~dnxaiGRvLOkhJ|IgjTmi~`iS!mNu{=>0C1Rkd#uAHn(xXNPYk(R2J`pX z)PPcW*qPism5-m#i>1D$oh|+bc9I=06`Va^Uu{NzM3r zGZ^BLO-*29wnPoA`4lcz!CRfGk{I=lGUVc0cfIGG=N~=)ItZA@t3NnxhNyYZVt5E= z9g%`rs{tYwwgd0Lvf8ivrcrM24e#yDc3hHP8v0WCb6pC;zX`0k`qAnTKeZLUWyx`N z2$ADARU;`Y5$kt_jbkjmT7ve{q0VI5?fjo|ZDB7=9%$DkFnSUg5)mTMwv~pY;zQf^ zsZ0se7$>V=5p~IV8*v4t;v%1E7$`8Yt(l`xqZhoO8*^b{>2^(U!{n_i3Ch^Q5Oyd= zU~**Jt~~u<3bz83PRxTV+Og|&7^EX(t#nBv9^}jIdE4=fr3A*T-G~$Zkw?=U zCmgf0D4eIK*DEg9B!~td4Z<|WtUQUVv^Yl}IJ_y$AcMbV$R4Yf@7j2FXM<)|r)~0h z`rCImVa+8-U9521l2$UEZ%Vnm*Z#GQ=d7S-OV-v@^h@Q};~$cmrK`PYZaY8o$3`e` zQe<2#@9?x^i3oFN%v2`PSaSX9lZz&Nhgt!-_&t}^5Ea*Qo!5)*YPbmR9VoAErUC-6()>3I!Q zBX`|SvTx>cg7w_MxU~Z7Xk;_KWWg}geO-R3af0}~{(|RnBKdCB@`;V=@~y_sw!^Od zhJ-KW7MI{MY0o6cSh6QUDk&!RoK&; z*Wp@O9(SRifYT_)`~v$9hM1NjA^r?rbGn%xIBa}}c7HPIo^R|9moBhbI`&S`?K2A4 zVKsW2r>V{D^YjPqrkayvxwu-iE4E%+p&*@f}UD5{e>&r zI(mnWmu2tleb}tWw7KTGled7Uo?Sr-t!Ssx#=G*%wq!1>g(kfy*t-GW`593pS{Ons zm{+h%#pEjM^N?{3Z{EJ^)+xB(0&eT>WT^i^#ijw}bhb`%*~>hC*TsXkFp$avim|mE z!**>g2BTZ5o0pP?5La&>53$co8FsI$3boJbKUeee@(PYT2H%^0BAqo(nQq}-7Au*r zS`h=InCKXMGll7=y>+~qopVpkt43#3CCO4|cDHKaVn>zn4{fCu#_U==KrJ9Cqt7L?ycKJkdZ|Po> zw@OSF+FOSKMvyOUWc_z&qYC+GJ-cq_bhT5b25?TGZ5YVG1)?@y_xrYc{^@qI}&&pF_z3(g^C4;n{>jh&v3 zjjt-amhOOIORpMKMr^zi!ShXdrJ3D2K~`L3-U9jxXpIM6`PI`T9qCgs=02KkW?!#h zHJ%5Dlq{Y&g)_8#IhFZZRvgo%*5Pci$~;6tB!C@S+0eiCs7NtOeBPr*J9wtR$V~}a zxkWlzMalef9I5)mqQ-cOUTooX=f{HVT5m+tsaey>&>0{j0@#BTlLRyK?0QX_1S$a? zEDj}HK_({lIcID*KO4xO_DawsytP-vwdH0ahWUwacsJaV?@Gd|M(8bGTsyRJu1xXS z_Ua{~0#|0f!Pa}l#oAtLrPisB3$p&6GZli2i3^Msi`X3~6hjaoU3GCcGq)H1hrm{U zb#5cNX;%W+rMW=@FwCaT=~Htv9Ct%2{U_e|nB_W- zGnI6o6>6i3Ah2?wWf#tvo0+rH-Zi2lb{1iinvWh+%COUJL7KD3A-Q~GsANtpSqPC0 zkxuK|_76?92=Y55-nOWl0DX~EKcpqBwYjzx67!?Q_gIcd*$)R|?-P$0&w7lY%UH?B z^WBrg?EI+ZgZH=188*A)O&dJp&>u$vF_@=1Lz-=mcH;IyS>7OSYr%6}eSA*&6{YH} zV>OAo=#|(=#tyK4xwE>fGPh((2(Tn_ma2Bp@;#gL9DCypfJ>>FFS>vTj^Vx5mi7SCELSI~6lPk5E3@>lafN@>~FhAa8qFnwUHmo{_w#73o&H$&nmz^+`^_fXKi z8r2?cA9rQJoTkN1r^e$ZGci_92`P#THm2aJ^Gl{<+pq+{D3HYx*m9h-l~mJXD~0U1 zo_=z#^7DF{q3PjOV`X8?GlFwx`@%PE{PgWgGsQOFXz>()uS~;X6cD^S@qlmu8(K4> z7_Yn?idmj8I%?&F84nZM<3DrZsZCGJHZpkvBl6?5ZG%_V!6~zZYWu{Mri3;=wHQlW zkmJP|d_+Ti(ys@yAN`{9DJtx^M{FtP3>7Je`%2YDT!qBP5Tm`~xE;;Efbpgt!Mof> z%Y{n}l_&MIldq&)c^Fl_?8S+8qy6o~zSC$?*Eyisuh z*^U0n3=Y%T6D(Xef0C7b8)Tz&uEAgD)>xePud07a;ddO>Bx&uPVc#6*-;5JFOo%%} zN0&F)anIhwjAKhs*Q#ChR451^z`)# zI|sQI@7-;SKGSiIygkoEuRrPTUZ~HPs;!0)T-l$GZ-|srs+`2bOloeKZ5#4z>sbI- zthqT(*o+&%f3IA4iqt}tFf=^ZC^nkv9aV1|6Cj7I%+oh{R^-~(v?|)_ZQ1*|r-m+5 z?=KI<`p-B3L#1u250MdARY4pxQ9_6>`QCwwdsRu6C(%#%QS#j*uJ)=7bHe9kE$9L| zH}-1wWtgDIIFJY4zYtrsje!2x5JkWsJN(bG%abY+Vr?kp6a0$@BeM+sJ({nsiApDF zGh6z$mH3H*3T+z$Lh!MUV1+XGw6OzJP^8(#a{tGn3_77Qy`*I%;S*M|=j-!+j&ANco z2i<8z7PJ!8r~sq-MzJw_SpKO%%TJ#62D{cI{n^7F=ATz^0x{kc3sH>rk}H~UDr`C` zmDhjrygw(4R&{Meu}B4f$=i1g2x`)yWE~4Oap@Z`w9I&NHTs9%_ehri3sv%@9nCzg zQ)z!NC;uReRtTsL1>F-~QCQlw%OhlxKf`3Au0}wf#$Zg(Da<+850=4J%&?XzsIyu^ z>+{1&5OrQx?cKpge`EI+I+a@EAR9+JIn^kgb z-!!|ze#^7JW<&;<>7>;f(UX}>N=QywV0J9Fc&N==x8vPI9_+fStN#ms<6Iq z*ADfz$>U8{ocVN#T>9>!(Yc^A$<5L=qeA?R$3AaR7DJR5|6*ZL- z>UgW_vAk7~u>ggVpx1}G!cSib7wagY+)F8n2tiNB&TKy~c4YbW#ru^`ouqnu=2$@% z+PCD5xVB>qZ;O?MkGRpO9l@M=YZClSQDJVkz4s**d`dpQpPT`oM8P^X<~|m!R@`|9 z|Nc@_i>3p4S}mc>?5(&O>#-@0}V& zz7jFT1n7;uV`*XHX%?1MPM(MO3<4ZUx zgT#ywA76uFka`Ytk7t0rTAr`Mi=#7We2MFw4c#GUC<a6Ivu>O*{AL7;EyPFRv^D{^+V3wO0Rp2guYND8p9 z1OTH#Da}9XsPfZ*2oEhRjrNW@q-FN|US_&=Fh`m7tk4abvy)0m>!kX&(KD>TTU$r| zvtfM+zsL83Ge_oLcDbmWw7XJg;lUN_8HfKEeSUcH(K=rfolLk=r;+@0fb+nW11)U7 z=R^$eg3NFv?^*Nv!lwo+@+=>d2TCaSo(?+cDs$u={XMX_{AjZ?7IlfJ8Bd&-o`dy1Ok#zy~8KXD+Q z4>0;bUip0g^`bZlP&5O+0GmN9({caiHalgXZK}4-C8?bsyVNOz`@YP)whO_9HsIlK_|~_3N$V#{7YR8(BXOp>so5_ zhYffVuf9GeDOGA*qus|1I$Sm^Ih6NukC{1&)X@{9mo=>|OaPt8yqmww5P;fcU(h!H zY9*bdd!CXH(u9=A9jIOnmT5l1e#*hW9S;2C46b9O(Fu7F_G+POtjT-i3klI+)@zA1 zynQVuGh55&#PdrDj1McgOx=Cue=hV+#xh3y_?q}%a9gD32A;B=-6v49aM@9T_Vuso z2ID~~s*Idn8^Z5nTcpc1kYAb;W3+~X3kt&PUVP|%_>XPq`|-J(f^Dt3LrH|%|4Fg6 z+KkfE6`Q_E$THJwjJr|iWtmf|5UKd{q(w5~96ZNJq{p=IUAs=A`4EjU&^Qj~gQs#- z0i5*PEKLn^bEskQ*C$WuB~FRd8Jpx(-$hr13r>cvdehov1BSurSezX9PGT=p4t=c8 zH9K!{Sfwsf9^j!rJplC2;vn(pWI7fEwJ?h3px!+D21PJQ^X(F)-BMX*Ky}8ojiV_0p$J+KY@Lh2FuzW*wcriu$;Y6!ZpSLA!iAx@klO}C1 zcny;`RbU&J7j=eDV^gC~IG?q%*YaXMs{PAM%C5+O*B3B1eKY8>ikCP`bJj8gRzNK? zO+Y+5Gr1DU$4ss;f8(FWWHiC1)%yR-UZm1b->vjfbQ@GPwgTc4*w=U`J|yF>Sy10wQXqk*qq;vQ_bA7x;4!X={*xD&;OA+ zs3AA4WoDywt{p~)=czIot=;8)DUFZm<4>{){o7V`wmg(F&sZyW6F-XO+_I7$EZw^- z&SheMm=NnVXH*eeOB-5H>^`yy-50|aGa=MZ1=XMX0!Xj2l8NL_C_$pVmXnx7)zBPR zV=Ad3{+JlP11ev7g9#})J$&DN!?U$tb*T_mbpn0>Y9EAf2)=r7YR) zfTy=m4pT^T6OWTQY+*AMi>EBV;Go0-mf!8S7nA2h^%yMYsVz!v>eO0hJ0A05i@@%3 zY;}-ha!>eO9x!J2(AjEXH~?04hUqacOKqq=oa6dYaK8JQMOnyL$vXurnV6(#H2#SK znTOB(+Od$2z37 zv$f2BckrSe4?Yv`MA3MJj}&?JZgguw)&x)d z^WRLY_(afTG!TG@xfhkk_9t2)tyQqSlTALxr<-rx;bO;ukjjnTvwc-}?FOzPti76B zW*w}mq8gKu{>D$AVW=W%#D5S7iUi16|UOE z5gsxJC2aR9e>G^C1(-JE==)Et`fBdVzO3sL4~G!UUnlA^$w#pLCpbD09A!2!5zc$? z79iDbD?iP{&!t7n0d}`@&hRcl&p^59H^Y_(_}VPp3`iuQu@CCG9#W1XTwti`0YVs@ zP|NzYni!Fy9XiU&*xHDgeoX`fu~>(;fA?W{;>VmzIuYL?z#I44ded6@gx)XB1W`-D=d~j2M>tBY?4o%X*EIk&cy_3rC z8$@(GF`M(GdJfQqXR8^0j=C|0hw|UJjc(2nem$ldn?z$wE!N)EaQ|<53dJ0bpe8e2 zs;ckdcbRWSOKJYYKj~iTBVW!r?NxoDARMp358*8-G7Fbca*wk$7xqp#29ygjl5YHa zwm^QNv~eyoO@Xs1!ni2$YL6t7M}obHG5_`{HSL~qv_#^NEon@%E&tH=mCam@Wro(i z!LLX)V1@P=>;E{fugu%~s{hx~|Dld55l8G&Teog1ckCrL@0py|u@YZyJPV{|UukMp z5Z_vVNIG=)fAwQ;@tVMBzAKToUBzJS@b9Wr4ntI)maJ6s+!cm{Mx_5q5CN4!aHYNPZr}ZIIVt^A1DYUVrIX9W+wchGO19_qhc? zJk-KY&Hi9X=Dx;+r-FwSexB5?lsO8QVHdQWWEMz}0u!F$^_hbeZRS(s zJEC$?a=D*c(Zn%{eN)#fgTNax_f6@tLZ7t-oVYho8(yEHi2C@MuQ2cwbL9*+#YYt1KrE?HgE@spTp*epKUK650FtK`nhB|4g&GNzL1T!>5?C@_*m7 c&h3UCc=}A?F)Q~F^H&fZn+a diff --git a/DOCS/html/stm32f4xx__matlab__rcc_8h__incl.map b/DOCS/html/stm32f4xx__matlab__rcc_8h__incl.map index 63082ed..339c59d 100644 --- a/DOCS/html/stm32f4xx__matlab__rcc_8h__incl.map +++ b/DOCS/html/stm32f4xx__matlab__rcc_8h__incl.map @@ -1,24 +1,24 @@ - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + diff --git a/DOCS/html/stm32f4xx__matlab__rcc_8h__incl.md5 b/DOCS/html/stm32f4xx__matlab__rcc_8h__incl.md5 index 63dfbcc..78b6147 100644 --- a/DOCS/html/stm32f4xx__matlab__rcc_8h__incl.md5 +++ b/DOCS/html/stm32f4xx__matlab__rcc_8h__incl.md5 @@ -1 +1 @@ -9ed4d4613759950d27506a61b4b89950 \ No newline at end of file +5826a30ab1321efe5ef0519d2f3b1e9b \ No newline at end of file diff --git a/DOCS/html/stm32f4xx__matlab__rcc_8h__incl.png b/DOCS/html/stm32f4xx__matlab__rcc_8h__incl.png index 0e861f591b0f185ce2ed11eb71eccb3c315bd4eb..da12fa7b14bd3c9fff858cd4aecdc506e364f8a9 100644 GIT binary patch literal 22557 zcmZ5|1yqz@^zG0kB_)l3bVzqdmvl=bozfjjC@I}tQbTt-2na|B$k091(A~U`-+OPZ z_kYW!uJz4)b?-gr?6dd2^G#h<9vhPk69fWbD=NrnfdVSrQ0D15%WEr|pxyzvLTWr1S7}0^L?kt>;By{;GgtAk!aS!eVx#Sm43H zjzXlVZuj1%lv#W3BaucS)7SlcHbrYgOs2+TNyn@VyXb#4H2E~GA?k#4$l8+Rc$p0D z5z`%Z#h zzp^90x!;fFvTWc`mq%4~ENbeMGc3asVv#MOjOQwKtpX9hD@Ea0aKgEFX$_2>fsh^r zMLOG5u~~Mx6kE|zj@T}c+P8AP(xs2(GBeKiR??@^eoknTYk}JEoTEgN zMLK+2-_Z+uB7MCcQ6Hs#_mXXMh@aZ{r*sGJ*_;&l{mRdpcyH?P#bz!BZ(UHOWOK_N ziLktQOVYUI@Rsvm&3WJh0WSiT1gpvSX+!YvVGXvToO^cz{+W}QOQE=CXMXQp>nw-P z1^$7U_$E*^%}PH5)VWuRa7v{i=CZr4nQPJWZ{6j#RQF*mWmR(Ac)AiD7%90h9E$`z z>$Tt%Ux&6H7Z2AhEf+_^{pIA~(BPg$n&cV!-{j4p*q=H#3aQ3&m1^rF@cP<>kH6Bw zsluB6AJhG(NGg7Jc&i+Li#_~abRaVzpz(#}`#s|y7^AUVfmNW?T20}hmbpTt)<#z zi6ybkQCT+M{qdrZ8H@c>K*}r?s_UggcOUSz&=1 zzOAALnX?``f8{=BBYu?t=Zd>%;41AjzL?4uw7?DJ)#eXZOG&th+}F{oOZ=a ziLQF>T%xrwRGX1$wO66&Bf526CLKA*ff+J6E}Lo`FKwW(m~tas5G6S{tNJ@UwqG{Q zll*l>Mis?ExW=G=~8E#k~O31{cRf++!hQkR>$|*^DQW zl&=>vNP#r!XEgtgXx5kWKeDYC+LDb{+RlhV+V^%;v1{O%Ky>Fy(E;C)AKd=6MfL8% zhQjy_NsPr`2>iT|gj(_&#}z$fk1pn3iZrMGV8+!2MVqyfOZU9~k_7jXi ztY2=7I|QTWyEdFxfc`^mF_fFPDG-nTX`DOfg|=0{?7G1GCgoa$zZ4Icd~3P8(wtHK zddI7b_=8QBtQpyY51;!5FYWIs$u~X&E0uir!>8A(9DN54uHK8QPg^{Lt4Xklq$}Hz zQ>)`oHtvj83~=lq7lu3PTfc4{_|a^-RIQCQc3&=)T~1M;_CG z+W>h(exDoHnzTyC0lw5k%@IqMEMp|L+5lWzju{LKQOhyl~Gv}S>-ArME}clESI$)u*Qcr6_GQ>Y&BWxGr*3vEgP;4=`RE%V6GDJ zj7JlJIQQ9#m9CB89mftD9$>|v=6L{$<%N}_S%B*s${HL z^|`U186$V7L1T>_ZZuGZ1+wfwwmH=WzWJgk?!cJ8uH0e+juIVf%@Q-?b05d)KQP>l zTXzg>CIPeh>X1I?0HZxw4cW3ubYMzW$iugEVfd;EDm4tm_h`z2O?Ldj)|t1nN`XEC zTfN(zb=G@0ZIY$i9PQYkjrjbwMhquQn-`X$cOlo&M<@uZYEn(K&lAbIery%oVez~8 zEw;Cqb20o2o$)ryCKvYM>7SBlzJ-gJat~dQ@}hoql*J-j(x_tKvA=wKX_||r6VKGR zrE9{gd!IZ_?LGFNb?yDJ%qT#pnb8r&OA-J0+s^7fn&5y>;b0&hq4J`or$8Vjrcspq zO9S?U1^0Y?0BJz>T)@fD$F848lrGH$3#3j4ZAO@HQ-*Rg_+I!^<#WM?fMrr|Zk!L) z@QOsw(6}kvrOz`>mcth-@@-rE4CK0?!68*tYhKvxQIU~5c@p;j40~NrEZ2bc8`hBj z&R;_2`7E&P^QGtUq6Tc4?naMT0oKwkSzb1Q;;WF>Aqu`2KRbjU9+q}=EO-(&z?wZf zPmV^xmLHX_Fb^QfYKOFNj_VYicfe|$(@L?G`p~B+Ht(72C_`{tr=Tey|FV77li2dl zj$=EGmRlwi9+o+}SUk+tn_Kt&zTdOdF^s@30X;f!jZXRVX*OJRAboA_{oB&wKc;01 zDD5}C!6*K7#Krp@znn`NSvpsLUVs~3S;|?XOeDvoCI{6vM@EL0gP4LPi}%4r#yraH z|F)5n2Na~TjJCN3UW{YrGh-z1-R|-(Mh?bFRzs{Wu4CawZHC;+LCjJVYkLHGyUpOU zSC-2|nE9VL5+^yM$2rv*3a1g#kwszn(7A!WGeP4p4>k6*)-j71Uq)ceavnv*G*WF> zzGwI5mmr+@%<41-*oqkOSB%?Lg!L)rtO>_+Z5`}$sBipI%rSh5kT+Vx;{MYk9l9KA z?AT-hP9A;Ln;?_u$5`vFM?!7NrMK*nGx%z1&@iNQhgLBVnuTzP8b=AfM!2pmco{_< z;unB2+im`G#UrQx)fq8sNa+tlVNdU{m5NivRJcO;$}24yUC{f# zjp3X9A%iMm{=4K$X;g=Sm`w`4D+4P487KAVXgkJY_n7pL!(YOPg6wvfX#0$U|6+At59sSzoJ;Zp<;aPgPs+V8*0TO zYWl4o*KEVV2>m|R1nim9pKfo1G9mc4(Fm^2f$E&Z>tDEt!1UQq9JhT;kBN0_*xK|f zItA7Hos<84MGzSygX$(Bera)vyRh}pS)JU?XGWF2ZT#?+wlO^gU=@KN7c54;QcB*g zIfLo;RwxsMOBl>c@4{SG&%Ttzo}Tx@58mBeB%`HAX$M`cmhzgSE$?e^{P!eQ0zcCW zqe~m5Q&z3lz6hYedcbF`FBSJ3%~BZu*x?SdKz(D%`GMimkQMec6{RACUB}7Ye1nUE z!wK4@!qldrX9*5vBk<=(eGgzE!nDDZUL?xb&YqMdgxBJX2-r(Y0SiDpRKyZVYVrOJ z3qnZWVlGSG_~MLZzU%0VA&4c&mpy?5jC5(HKFJT}s8U$FtTa+EvAMCldLj5MnNa6j zu|Ad~b^4#_=JH9NE#ZOmPYuNR%u$L2LgYSaWtTEx-gti-2fxwo@Ag1;!5go%*a6J` zIofM)j3v8Z7{%$e?_bYc%|?$>(Q=QWT5rdxB$3Uj!?cWTm>EM& z#-x4w&)Ois$gpHIf!@ChJDU8aIgYy8tglc7vSv=4#`}(U?I^Es==OYpkH7_9U1Z}< zUrf7(!kJ)9#EHdBElfrWohB`$?VWaQsD>Z@JqE>+qTL~J`;sW`Q6ZWVt#w-QY!X3z zhyQIEs%rc=X}>vKh4v{vT>nBn^uGj&@3CZYrSt+BBaAh)XWvM^15N{ToO|IbyZR!O zpbsNwrqQSco$;JjgX-mV7}}JP4R2}o9G_&8-dgb(o<1w&Ph5VLXHMD6u%yiMFx+xA zP6&r2=nXsMfbzA_n5Veqa0>8Z%Z*?t*{;LGl6gO;1dt8+(Vx^|ffJ_pps)}~fodPA z))p{ZoxaXIj0paq?bb0(3|i(Kt%eLnnHxmVr0M-~eW1IPH@n|kOBR_}IH;6cCh?Xd z`7A`)^7TzLTohL2+jRKq`0E-E)=!&a&Wb2%JRH5G;`J{K}8-x=rLj*O#({Y&pQ5JspoFip=&ke3Jp{%OXo(einj*peBDy^8LE&k5a()Vjhgia%cZH}trBXm&u<=sS zmf)C_T2)rYc)Ogp&fwHl4g1bE(-dL1U_?hU42e>Pr*t3a3xym^Y6$RxLh2nA)u~)_ z$~4)tUe|P93iHU`fH9-iaoGs+sKy)MAp@Hb%={sP_X0MENqoI+z}?%4+}|wyWvWJ$ z|8|Ue?)?qZlb>oLeG$l142)-bd;Sg%zKAgYI=Qyrp1Jmuz;Z85$wTNsY(nfZ!A+Xq z`b{2JM5?6=q$)Q}y}o{?Ck3@yn;D`HAJnO8YHTFJ@(`G&ulWKdJvl6gfv8Pta+Si> zUW>-GVawqF%1pT&R5cB1$z!JpV+-dEL|TvKG5|uUesaDd7hSKSUVNF!yM0XSpA7FZ zQ`%Qora-L;Qpg?_HVjBW5FN*1B~x^$#EXr#FX^y#2@hmp6o?nCUpXuW31Z z?oYKs0NihhGVxJm?*{d4L20Be)IhHO>G6)oW{d*Lr9x`Z=Juvsd)V{EMhNgy3CF@q zu_mfIYk!)BPV0eKe#K+rMG!Oe_1sP9SbNmV=twx4Yhd$B6KFKOkXcMSrAYM6G{25q zX7b!C%i$>C@Q=(?2T<$F*2*r8eW`C;r55^F6EXJd^u(3*X=z)ppawBq40*sH%XzG` zEa@hng|g1ujGzMf^!YF-6WD~wEf##1zW0Xq$9zNT`$q$;i5DXTV7%+Tu`Bl?I2+L0pwA%k9^t9(Y~$geiBHY5 zJf^cImxreIOOnh>vRdwpe_4?*JFYKaPgXHxv#jR1-u@{RX-&aA;yUFrbGUE8cs1ADF| z`-pW`#?~MCLlvwe+dD36dR@@y0y~}QwOD-^NPu&mWT3kpO=<4x9QGncxt=+LF;#fp;`2+%rSm{EJr#)= z#nk?VuW>^S{``)B3;#iLkj=0M<{5;ef*p2|b!u$y= zvs(SG7HpWr2@I)>CIv19Jyo7ev3)l<-V;fMU*Pv9oFO3rbKbVbs(nmBN zCEDv;8GBYJwNbKKw?R6p@`Bz#F&y&DRoW<|AuP<|Us-qyunZ)&L|U+y;blk*C(_UB zsdN_T#Y!NGIXD!tZ!4WD&RfR-6xwgi-pexGXoQ5Q2ddn7r}*DN4&cU^?=xkhS*Uek z`p+j15V3~nZ2i({Kd^?0VCoH$!!V$}r$bi{=M_4Y`c3vJa3;%1?=EWJ3m4zz3Xsrp zF)fvCLS6u$uiEw1)OW8HBx-czNia|PdIO@q6+hIq`|}a>%ou8LTHVreMQ@e}r=ZiQ z;m^OLxMTL3ze3+*Jmd&&e;_~omD#gtx$sDw)Uui{JLu;f>|!^=N_~65c@v6pbUKq8 z{9e31X5dNYn#Zy2;Ii}aD7bEfvG2!9UuEzIa-RSg*~8$*6UX_Z{N%zy$KQY5u_F9s z>O|kb|8VUxS6BnyP$haneJlFcFWNo51@KpS&7!2rd;%o+wGKxIFSDRKxw+%^_*CCe ztel(Skx71yy_nRc92i4KrwMlSXPWIg)#HZvI27mg@ia{1(X|75FLO^f2cSM~{YJhG z-+fg)f!CF#ReTQ;@$%&I>^G|8$U}56sTP^>$_t1in)1w z!^qSGk$`-C3e+^6e7m+8KHg*b)ir&EIQN_~+Hxhqe)C>t#D-9bsNAiDyrA zMJ0@Di#s6bwi0NzOUKv0OJ)@zEBOb6(%*Vb#xjR*UtJSf7LZy>ri|)6n(yn>?_MyT zONQpHaqR{#MTAJj_hQ$5&*ohYlp*kIz|4E0Vtr&Wibwc( zu$%N)5NlSefFRyw&}R5c|8HBCq$Uun5vLJ)=gh&UZ$NP8muPw8mYr94u#bbbZ(Sp= z_o=Xk?mrXvBnK&mnSvH@ID$Zh$TGe()OWk#XCYS?-756d3nMb}MfdMgXdu>Rtv|og zPLTgt`^J2AW*#;kRbO;{&!0Hq4}`o%RaI#{5Y(UlKOhcc%bu`X|HM7K9cmL=$&W?( z4C2EVU8dZyd3le;R@n$iVVqv$`Ultcu;Gc2>Us69qc$GCYBZk`9Ymw|=lsY8c%_e#aLme>sC zzjm_*#jK|Jd*=>N@yJD8bGk#}P!fw(KQL`hdyS9Bb#2XyGlBn&%}1|-iWDEBATYze z$aS90@&K1$wuCS$5{Kl3jw78n?GfP>Mwp^-W-Qe1ldYEN(NDTF5yrN03p9%OH9G;XQ>SJ{owt5Av^FO}O_9l}Dwz$d0OdHQcHL9{0Ud zjehAgf2P!Qi!0gRGIlci=wMqJK=0V-l)W|~BhBYRPniaj*nxu+cii}Df@&#F$Q;YF z{U!W^KM+_$h=8T^A+-F%?Y@}n%eOAi5QKnSP<55f?C7xrjWcfaqYjs~#E|Us%2wG7 z67_Qsa944`POE&Y_fFQAWroS0(0&DY!ARHW?YiJQ72jg@J5m9iZ>9QG$APPM;Ts#T zZytKrpBv0R8C6+95+4-UAN`^#SCZLeMBw%xfoAVC#sAitHX#LAS1(DBpl5FqryD|! zuEp=zGv36%d%~ukz`3U-PDDXjXseLXyw_dp_fgm)bd>OYX;Rjq$f+En#*$5pJ9P0S zt%d$VtV^j9T?0Sp4W#^y@$CC|1_)Jn4^UAm$=O#}->_dCLV?M>LKQSfW}2vkXmXCe zp={Xnh0bx~zu&#nxhX;?@kECCe@V-kF28sp@?t;FiTj&O1s)~~m)>}7VEQ`{CJhXQ zO6G3?9YM9QynmN?r1P>A04myZCkl+WYPT|TEGYUtfDgPHZT56HB9wNY9BVkwX!{d; z=H!Ep5Xv>JEJbUsUSM@iQ}1QykP7?E^vAw$44&0e(rmvGO6GM$wFS$kP@EC?qsKo1 z&vu|TqMo9VXo<&xLKbr5vg=-AEc}B?7sM)g&5^@&;Rte$4ln-kB~4k;q0(=h^0#Ah z4H6n6F0;`?w_nhru(6-<_J}ThK{Q@aF%?>C?pghl>fFj}3QDYDHDl|cfzPT-%V+wi ze?Vi=C^tVR5W9W4oR_*X+%;6Se8}Rp)_JUAvwoGPSAldxTs1j~^e43X(3D^^4;F?% zbzSbv;H+>Hu8oWih2QW8mvpx@r^?IP!qJBfz-PTr&b9M4N@CQ^Wt@aS+7b(!!xq(id#SF@Pv9G1NGCW8JbfQIU#OC6)b&g-i^BNgfNU{j^vHri|mV~i#d$Wp33MzWzXhBSIr(e*O#^aZ1gqlV@c7eXid#m zruXV$Ove|0qkNxM=68Er@Tqk3tbuEyX1(Z85o^gv3K0u&H?m<4OKlPcC=e}%_v_`4 z2rE6xWjFd&8m0Z8>+9En2H&_(%B+;-uO@pCh+yv~6k^TvC^L66$*<$L9$T+)w-wU$ zHglR)owE7e1hD8VU$+V7Y!MVre>?6_&{VT?(h&(x6>>mGEqMIUApnwy3f~k3fN=RD zkk?r14ZUCYQis4TUNhft@~su;vbZL22AC-X( zh=0FLP|4Fm)yGTh(igr693XzDQ|1wew|(DAJ)RUa(@Mm0@vLxM53SA1eAHFTuL)u* zY(vNiO%$M0d%~&=Ch&E`WD-QzZaCWp5$=%Ns(Wvz4esjJ%!MJ(q(7SB7xcU6w+3R5 zgo-<#`js6{hYUlkN`oa&rF%aE9E2P2P%KW**&o9=#+B%JS6?A$Ls+epRxt;S?PPW1 z;I;3xXYNT9!#N(2E~3QBq|Ko|4+Owq>s*PjWzenp4VpO|JD-{?KX zAYrpAI4n@OS&HEEV%ZR+)@`MwN_1%(ONyP*y~q^_K?}99czpw~*Ee|Y_kLnl;vMeJ z|K`dtijHMCKVxZRz1Iq3$cm~B02BzigfRZsi(6P|92mn$KXtD{|F0JSh?L4iV9X1j z{3g33Y2Ica8IN6LR6f4js60v6Wi~Y{%<&8HqYt_3Xcx5aH=4`-DJ)Vss21`-s2UUb z(O@kp^8`?l8J-z-Nr7Ow8!KjsY!AT{ao~{?ii1c5-={nb-zZB87I;Ui18Cys7gN)T z@&%~RzIxnJ5f;HMhH2{un!37ZPH;NwZrzNXaSh+N%ep90H^$=2owYExY_|MNfKst4 zEY0Ex9U@ybf*NoWsqQqoYU*K%?)y?OL6~>_ybf%WXY4tHu(bT}T;m|SFr#~r%(d|G zZaA|T;%$2?P=HIfPg)w?IyZcT>|BypqTGrh3D^YRVtHjOYG-yQ7XTiof&z(R7kXN0 ztF&So*2*A1gUE*T(C|ex^t4OA$Y@h|+_u7g)h}+V#G_IeW*%O){*H`w&HWqw1&$eK z0GLsdb(o$8R237x$uxN4My$G%K)Z-wgoicc&23!sG=F%|>o04!XPazF$Wk+B)D{Z3{C(*&rGew{#j<3}AB~eF0AC{*mBTw@w zx>rdd2$^~8FyVQLHDo$@K|!OW6yCI!oU7fN{@){iS_`9Mf^=0-P`V_G7;lqS7(NG7 z;^cVYBD0j1yt=b@j!oz7c2Sphc>K4*7Y~}%#YhVcvO>$NJo-;`gWVOwF+N3$NheW( zQwupLMn9C~M=t}K7A2yUEKq90E>^6A@>ptsuC-R`(7{Bhr6T-^1XqbR=}PYx0W`X* zhxHDBwXE(tn+FgQnLyKLl1VO;j#In~Kcvu=yjBOuEl!j6d-&6bP9(wFvdD+D(S#nG zh9JRmd8|by*F2Kd^yWS*%h1A1HlXds@P7n#zt}(eX&1hzHe#5gUAD+xTMXc{*z;~6 z0sw}RKyj}|#~1IqR>}vcD*$)M!Wu;9;G|Pi8e!Gj)09=yHpXLO2SW*^O86U1jcIpn zc9KXW2WSfy7k`jU%BwdnftE@<>tf?|Ti;oF>G7IJrfCFpM-?T?z8=6_0OK|J4Rb}S zwYx~;QT@k5W7YIf5ND6nENu6LYHj5RdvqmZgI zRmI-s_ox-19HzG6?s(7SI|`(Lb^vbXaEH!e3Sh+udY3}1%R>;+T@O5bjS(rn)L#XQ zag2C9TxOhp^$S46JGpVKBd*#_Bu-s9v4K}qZyA|I8D2X zVM^T!>v-m0-`hHP3ylA8BRZCpoE4!;6iVUVX?s&pAZHfj6K^P}ZqDTh0`{nzc?FM5BfHD68hvBW(u-wyTPJbCR93+ebRNHs# zIqm-Q8yZAoF=((%seL*iPygIVLl;44`jS>&i=Ox3w0e7eArWwazZzdhh$FYy?;YNca4-BfS?*Q<+fB<5K0}5cfPixQqz@nUr%g? zq2zCbBdXIt3Bc;RwXnnR!3UoswxAHsVeH(&(2DHYfBkokKs0JwxnnDXYRV!w_3TfO zc7mlKh=h3s#)S}*j2HBrj9KAYp}{3nzubK}R-@WZt@TI-uZOD(7fFHeMEPnrpsw-6 z#QKiDAo6w9S+cr+QSoWlL%8D7LgWSFg8hnqwK?-X0q)SzS=W<2AjdHGT46>GO4l!Y z=30DZxL^t=LZ`Z&8RgnLS-w{B{b|)4fK~IieBC_{ozWW^)}GBjDWI}$zluzhx$&;; zO%L;^EkGPe8A2UmeT)zmb-u2Xm=tLd9TJgtT_cDUW@jEf=p}9ayVY2|W2*kAc@Gkn za!X_4(P$5STB3m2!Hm!-@bZ{(5!1>~A8gAGv!~=_c!@VZhEhklSqhe)on=kN3}BjJ z_y!R~>&%TPyX$thP%7>|5#*WP);8_^0JnZt6-$PQgxr;i_J#x0 z;s>Dng+zV{ce zclj~_VI z->W)YBM)PRMAoOlRl;2XMTgj&>#a!Q^qi23g3QKiA?Z~z9cMCVv&sNq)4^Or%oo6; zsYx=H*YbM-F_xsn!`soBRax1mly*WiK@P&DmwEL`y_3|$1KS2k{`H^gMhBC*sPXS* z(;GCQgGA!{!fFK`$gpj6){qfHs%b#ltjnJVDi3F&!-%m7ChfDGQgNUy<1_F?`kc| z^aOxX=C9+)BtQuaH4%Wek7+6(+OUeI24(d3>a@8iG&;29&Q3@oL5$b<{Pdrikievg<4cOG7U$$;)=oMmKIL$jDk1iM~Z#Yy-0O5d7LG$ zah;r;{44kJjI57KP}N4fAo(twhK)Zws|3QIwQTmRfaTy3wq3GuoUBv_V`(IB1g%gc z08ftiG}}Z7SYWxXLF#iWTSNmH_JrTf*}1rQQ-%U~kpF>uBoxYjQzEkLQqy&50SUtZ z`2Una>fp|njt-HctC{KJ2aimGX7t)u*N;Az9Ts3mXM=M2tC>@*(0>WVRIjjxDmUgz zearB%R;SCgqBHu^vy-I|RC@lvdc~ zQv;yyKQskOlQ!>Gn>&j)w*dG)S(OLv`kEYqeKT9?8%-o>>DK5Pd-!GIwX2ROy=u+7 z%t_Zk^~dtzaT)Y&hb(2A5$aG&{5V|3e+)l<(*gSWX1-O4>gCiT!o9O4iA~3trBWn1 zmzkk**!ib#6a$TIcs6jLg zpvJ4wSwkgUcD0DK=&>8Ky_P(o-i?K*oaFcOu1B7Aj>Q|y)(*8#%rt6<0M|f`$%r_8 z9vA~9%T}ZBHrqm zdx_HbcmrB+>@@q$`IK6Z)7&a8|9rh>;RFgVp`XMOgw%6*ZC;t&RlDFyPw|vL?qlO& zozzgHzteGWnKFZww%EQ|v~ZZJ}2D#`$1$ z4`vm%^B`x;;b1xpWnz3lyDfQ&%b6L;+DAWr0;1hp4GEMmHs@>^_wZnuH}- zylFF2uF(64Wo_=sQ^yx${Ea2R6h51k`Y6xzjT?%p1+Kg1tV!EVy4%~74;a!43NgfF zQpkzGU(sNgP+udm#eagj%Is-}!%}RlGaXZ24?!3S)1;e5jl4Vda`*-=McLpBQY>pr3+ z6;t;*#~rxkgOS+XfG1OiyLNw~)RBhdTdpyHxa-}Y$gg4?j19+d()5e{`> zFv*bdIjxrWCQL_i*YX-y%!MW)HH87Roe`YGo-0HFid;3I(p=k6DI%hY~*Hu+#UON&)zxZF~@(co&FNN4RkXWM?Kkq$fr{YWWYmU z2JHWBOxTm}IAi{(xjXr?e$pDf1nq6BP^r@E-m-Xt0XlfO61#(^W_v3Agk)yl1`iAc znxO)-H5eq!M}UoUTn0a9TGu*=0lQ*geDn(#;BF`vHr<ioyhhjD$`^p)GrydLoz-&$gNilO81dQRa6bxUSKsMvt=>H6 zj5o$$?y7WFmnc_+VF(}~kLtu}@~;c_qEQFbrVGU|x2C4FTeYYD>oq}G``(-{*e1R) zJi^)Y2VT>2C@g1i5-9O~qaqS?wZ)~R%I{1+Gtmnzj&wm71=z++d@M76e}67_?fCZU z-pbJT&My4ZOE~ZT$v-~g)!+1}HV{gm`7JRljVi5vL7%FuzD5u|`9%PxOD?Kn#LDQ= zT#2sj!CYaH$#(>vaMxCc9UE1aSS<(QD2lHeM6DjUkghfwXIQDq7JG$kR zJ^Nj7H}Nlgd1shR0p~*UEMKn$0Y6hfuV+l0oKRb3^bpfvB~8U5uieWU8O?Ul#7QA` zT>ENx%nhDFb%!nIQ{*JxvCwQ(9y2ddoc0?7%zoV4T-6$J5?WrsRsJj9AznwLKYL4*hEIR#j?pS&BVd?y=qs3b=GX`V;emw^ zheQnWM;HgS_}Q%=G+2FE@W{Y;M$}Unq9}h@{*BLTrz&V}Bh=-REjKtubgm1JnEsHq5it>0TW;1K`n@949D2-zkY1LSkSW6oB8wbVD&%WyF} z<(aAiz>mNB3S${=5+apuwJcYlZB)d2F+dywR1M}5G}j1%TOp#v-iqFj;!uA1W!Ib` z?MQ{PL#zO$Fb88BQdPLeu1+gii4cIE+s3pofqei5PnKS}n!`mP99t(MiDjm%U*uLA z?YZ7`0mShn+HKaK2PGhi#-xh2T2pS-?kQXVBPXLDikIakaW-G76ko|!is>6bmmlgL18v216E(FEDR_s(lEs8QnN$_Y%vSS?Kd6hHUNAUhWg4)Ng&&+>XG;Z>)H;; ztHTQfYwvaWL6IFe3AoB-Bf%k7z4bs>Qbi??bcQ@5rzu*-+@+O5o))(09X=cUA2oe1 zv-UQb(~EbwI(#;stLUWN;KliER_mN+YTY?%E5qtpiXt`z!XivKUU>%5gC=pB$<>PO z_b-da??(FR(_K1tn(2|X!AxY8!0K#Sb_{&nP|lfu z`*XtuQz9zz*Udg>#@AvGKBYi5dLAR2PeWjYb{a=eb7oIej*&cb^5u8Yd4T%SqB2v{ z!O=C(!Hh0RW2D3A0yGdU0PJ11IZMo!qx~5CLW_)ufK$6}V^ogoN{0922&gRv+^`!X zYzksPqkO)yVF(TYUMZ0fOtb}gsS+=Mo=O>*Fo$#*yb_FSQT3u)V*S5#i=VXAxigb_ z6DJr>S~XHkolk{kU@>>4?H8tZ{+O^+{h|Pmh1~ctP_SEB@}Z+7kj9}{U{&j8!N)J{KO$n6-Lm1 z{rI}~G0J>P*%;SZ$(6=7Ls4G~?av0T4&sgHRoEiV{H$dV3X%%EynA6?>Fx@DyYuTzG z#F6%nw%XD(-(EnsX$3Z|#Dyi@T52@M@eL<{8Z!Vbys;!tRNb1~zws*t35>G9(L zVPJfzloyp&v5WHBr#&}5b@&%_F6!9{`C##SZrqcY1h6yWtIdUI>yg+pr1B3>JxtXG z_I`=?IZlV@0Yo*4&W)`{PWOVRs@4+V5TXz?Ox7B1x<<%fMBo2VEzqZr;PLCq=jCj* zCY4CCOEtV{;E3GlNhrUlEKORcjk;CR|HhxU+yQXVQg}$`}CWT2S6n7UNKlmtAoZ?iqXrvsIb+ZhY z^v<`NY#Dop-HS~9BPsTXDhr^x=C0*DuELbSMpvG<8Kw)5a;lL3KT0mvxtHfB*Egd@ zq>6h_2%OrG`(JZE+8JEF&C%$H5?V;ommkr}zDTD#J^+LX{|B|v-?NGNqG(1aMtpCv z$=|N%sm9S?aB1kCLnZ+atOo+lPwmice)sO)Ws}T6*79qFA8tkH5{^K!IUhgzKvV@1 zriY+bbYk%)POD8`^)4BPNsD|w4c=I?_E(@np>lHicO-hpi~}jcxK;vn17?drbXGt6 z);2h4H<2cS#Z&Qz|(~z3$RhO08HEKz%O-S zDNPDhR!b>Mh_1tga=sJ7I zmutn3`m17f-&MSGO7!;`UPWrpfmDE{@B!%jRTzssA{C-kS6^yyWS@fa*gYKf0j>3+ z$8HvJzjy*MaH_V%VI?!78t{r@X7nZJ3B!cV>X{Oh*n=JpK{!<7^cS#!c1cQ1bn*ba zo(QoJiPkZ#7l4{NQ?!We5k39{Pk(boA|eeqpA#N!UX7WSA5~Yw(jQaT#sQV)Xf1h} z%ZH3#s|ye!kOLIM=>X2p7wU^yUK%OWp6blmOF?r8NN9k=SDMk&{(+q8=^$?z4)}I3 z%m1^WxFWbR91|RDg8UFpV3wAw@AF)-M#f=r4G0|{Tk3_xpsLq z1eOQBV@K{l-N~$f_hX^}uj1ur z=4NEg{cukQsL=aIK6Ypbbo4zsfqnQ!Maeb7`Aq#wbagerzt?ZZE;$IKAUX3M9|iFP zVP)~As()7{Q*0iC)&b7mfg|OM_DACjr-U}owrM% zxbp_xlqheP1FX?OthhI>@rdt`%n4u}TcDDuBr~#Bqr3ttxbSFSZyYTJpb7}3s8i_v zNf7`z(ZZ+O-*LU=*Zb2F*bC8XVatGzkT)x$IzU$Q)+%gD)<8eDA6GJ51m9Yq28sc0 zAk2Iy5GGc%M_2e-n{};nd1oClr);hys&CR_41B}Mp8rIesQZVKfBYcyxkUqZkTm|b zUkV2eB4CAdh1i6A=;A$5qTn?yr*$}=x(0eo19^pRU;_c`gSVVS8D!r_{UuPn5{Y^( zG*h-z#WgqT7^$e$t<>-@wXE_&ThOoPuYw=(u!g%2A=W^poRbuph_0uZVe;-6+mw33 zmN*N!>Gj{~@M>kt*%|=g>zkI{KMD}Ihrli@2>)>IMm%oFi=|r$An(5*_8g!OeFNSJ zxEpPB={ZS70O~B;>aMFLS2)#$!AqB9*?zV3oaYS_VthvBZ>iU|JSZ7;ri?z*0TSZT zoZ2V6w`ySQUBwkgk2&FM}PM&w&6 zJ|0{c)2-nRT*hGLg3P-*oi)qYrb>6M!=rGzfy!#3alEWLWtlN^LRwqDhHsxL@3k5L z@0fr+OX!SET4tzk=aGygh_HrSqEeX2pP`rw0ZH`4=h{NX-f#SM9@YSP$ZsMb?-!`n zA@SlGw^qsAK=k(#%wx1=@tJ4p;%v|~li(cX?J&7Zef-91@=l0uhDiWO4$rr+HL0e) zu)prw`I^@QKmrS9)rroxCGyw9*dgfIv-pV}Mm8*Ze^r+Z#Nvq4Yig;FvoXCZ+%^C* zcFeO|X=c7+xdF|!p%-7A!XocV1Sm0>vxHbfT)?bE0TmAj45GEOowwDJYeV|#N_$+2 z&q>Y%Mi$P1zn(j|``~V$Df-GMq5vWqwzQKMF=c4I5Az`<&^csg@M zpGdxwwQJ+mv|P&vpm;R|!;bcJqw*w#SwTtpNvf4!!Q0z4-*xj6_ikh88_VTyk|4Zc zMZ%w7Hm#?b0t#v)fK1Codvhx&svyEd#LAp%axeYV=*!DKax3?wl^U!~+DZj40wy6Q zxl1P^5-L?P5{*pQlAL(c-O&+4x;CN*)T8oTP?~2>u_Ed zSsbtjC)YEfhfr42@Aa?&)8HT(Oc&~_WK3T^j@jrPwuuNe!2D?#!r|Lk_=3_!8y-3Z z#|KbIY0upTK0ZVAcq1T3*RAUr0Xt5%LTz3-pRPQ<=o1cvlSTmFLd{nd!ZbI#j3Xlw zPrtkgt$8^y@oQ%vaJ-Dyw(gW{Bth!f1n=Sf-=!a*QqxTa2sSAlO zF}-IGsF5xJJ&)QkAQtO@|6!6FfPH#tTecS&@veBsg_teTZXvxvF61ACk5QBb1&9-) zDP_IDJuvTP2*%0x#*Q&94qC+r+Srw6M9*4 zh@On#Sd{7IIzU#e8YD;g8IFPg5yMQ15>QhzKbOg}g^W6QjJs+kF?l2O90y+Rp(|x! z4{%6S@bbvT$4SNd1x%=&{r;@_pz80Ce`O;r>K8ZaGDG zfNBx)EahXapd5=*F`qvI+ntF2hBc!GJTlc5F{(s|e|$_dIIWR7TG%xG*mU^0RwCnG zjI{|9I}`+`Rg5JTH$J%-w{RnuN{r^127`t#mNCDL_dRcV^h5FE(WlE-!k(Z~+-+jV-Lus? zO-XrXN1oLIp5yd6{Nx#v`#cbcr2YAK0h)mK5XBPB%UieI5>zWw&*K4 zbup0$JWX({JLo_-?j$4PtVGMOheikEEP6ZD)2v1Pk=Q36ovc0Mee}2sKiypNqP#nB zyZvBm2o8-veT;RpE*ZtT9g{!Vw4Ew_uO+kD9N<(#Hbk9zHCk)%<3PfTR@^0q^i;EmIYIO@ZsLYIs9CaQBKU5y4@g1ymGJE=7e`wWPQ@$D2V%aBq z{$T+P-{G3jr6TzG61V}_2>QHPwx~k!j9l`8_pWU$QSHA?jxiO%_5(Iz0Dlks+yFQ2 zy=qFJ@%HcMU3{-B2TDa_{yXiTTv#OjaxkzfVa78xp!_!?)9KSf#~qE(o^brek;}Mq zZk`W!@~f{j=sOtMi*|8Eyh^ikX2_y1SHHjVO2sye^w~Dh)GIkW87%ND`Kq7p=*9n< z49VakM$$`n!Ur9lO6{E`&h+>1%IFMA_1_~$56`b2(~W0UtgUTq{I&$d9s+fo-tdS` zJ!E8|BXH+vica+B**K{)({>CL88e70By$>!kpU7kn zDPfuJg)Cmj3=PhAmKSdSYCwFIZY0e^*J9$nlol9__aV3~RVY9Nnx+6AB;u)_ebL`J zV6oC+k(=gltIuPzk|x$QJRYyy<<0CEi7R!-RBjh6v zEL&~nHcpTF<_>55qGjp6ajBKbzPg##V{iO)yNurb^2K#6{;Qk0zgvX;K)3)pBZWs% zgjtwcmbVSuQlXi%V=kXtv`Y_7s0uAzLrYW!;Iz6~(eD zvx@a42wB8d|I|@y4F&#D^`pN-iux58gun-sJ($pZ(3STck8mocvCnv@gtWl7GZ!n% zjsRbZidP%149F5+X*rJbxlb(p<8Mb>!vKEB^If=@7zV5bdRc$vuTRtanQWnRJtI(# zV(T$jgpsjpaT$I=-@=#euzNN@V_0eSNdRQ{jDd_}nH}rY?>1zw)Fm{eJaFeUBGQr( z^Rus`29<3OU4@A@Ud#@q#1GpWMZ`#Y>FzBH zy1(8aU*FUKQVd{47HE_qIBl_y^5*B~_0lEouFYh|(dTsrEFA9dgYohEm=*mh+EB>O zk2v(6x(*&kMXjWvVljC}@`Dd$uvk>N&!R!0wA~in7k&AwFiU;jS zac95z#fLWA=**m2z<0PA-QQzYh6|+(vb(q5IS;OIeIDq__j}9){o=oRMDMH@uT;Mg zOi+=qNOX!)f4}+q$YXRQDUd8*G~(ukj0-`h$ds}AcieF6a}lIdhe67pGpQXGtUOkk ztFuK?3~lOg%$Ipf@Er64Y{OL&DE=Xip$o&=VHWLOxJ9q!Cp#=IRQs{i4W`5P4W6Rzt)*4IY59KgkCQ^9ZBGvkL<@~lO>`A<%d_1%%- zMU%q`5!pFA0n>N?K5zN^ln8<^%kkz5REQ!;s2~P?kov5no^V%b%3qn@i%gFC%zV1I zuEKIyPgb`{dgmFI1(@I!u?X_m$z zmkAvwfz`x}9XGO2xv=IHXZZPHMHA?$5TZ(aYt^R1q_a3Rg9g{|kfJ3h;GRT7y zsZ(l|^9asWP+=M5(c=|R6uuhC>(cRMx3q>n2nK75LBXSBn|-{4RPtqCFx6ad-q#|Z z`}>Cz=r(}<*^F7==3K+L@i$P!rbthvoCUWN^LR7tI)5wNSP0NvdqC0#FpkzpfyCx_hX@LF9X7phR z&|#~Oot^77lpQ>W__Sz6(K5=?@_d8MEX)=X-X?Qy17q#XkF=5XA4}s0dP={BME178 zs@qA~P4PU_Pj!GbYHI3|q?jE){Hp=VS7RBCR&!RdvqI(&K)GdbUN(QqZnflXU?VNE zd5y_Q95|=?lm{NI6J<%WYRvtne$-CIr6Zi>sbVMn75;)8%VmaX9g}3ju(3~Z-h4pS zmtOEUv;$?e`z!h7nU`qj_^1?%M?g8pAf?j<5v0 zO=?*d41chs1uM669VG}Y!uN^B?g*54xP{@1?1?K5rTun>nGBzN zAUZ`3lvRZL&L4#6E>>pOIMyymbFqRodM<&o*Fc4W03)QvCj1~#@yjm0Rj|NjY9|h0 zUV2w!)4N5+wAi*^bzQ_})f9eki|>Xsir4sLDmC}H>&pl>3IbuHY_fcOs#f(nARZMo z`h6{~jxL=QLwpq@+3+@pF>S~fGFoTKnoe*E*To1aThR+bve%{#TgP1BjlS23ufEy4 zfvjE1VgwE-W%|Oq=KOE|-FHPZs?rN(rwvqOk4`ENt};Z+V$TIWYwxWUqH=3cMJdH( zDpo!jfSN+LQN2p8bm$`g(jbtv=&wP5z`Tsj3Gl_BnXfR$m9ibyp%Zm+aUSCk-MMqn zpnso0TfVsqwe-D4*aBK7PRIL6=m9Caf<4fnu|YqvbRJdk5jmuB)5}oK`G8)m)8-NE z(}@HzxwwmS`wFIQ?3WHhNMvX3I%!A_Fo_>GJW^NNGM(JWM<_e5TQB|?z^Egub&K}A zIr`tlA0*6@{LHHx(5&Ld%#1I)Hse2kWSv1k8xpcX#g^02|5Rr4l`W;2j8Q|IN|!D4%0tu$bAB zOw{QoecVfW!4CY%v+OO9gOYJGHU7)8Q{B9Os-;N@5C@7>_*TH+N?pyoUU8N&jlvBP zSW!cIgzy;}10azY^DG+=vgyz&+JkV9R5eL`zEXA_7I}3FaK>u%o+{owt>$a#Jby^MAJ3xXCG(x;QP$d4k?WxZSq{@6$(HrNbg=u2Q?vjgMt6Srlj@ zZzA08ZJRhL)Tl+3Xe?}VENODkI(mc2HJ)%6ZyPT;8{Ja1j0Q^%$Zh4pn|O>**d=Z@ z3p3%`IEaofxr-6x;y^k}zy;-}u1!Q!1(JKedB5iIA-8Qzx)R73{t}}sU0L^dI79VQ z=7oNeVgs2;-PVQ5LsLvNx@f!larJ5nGP*@vo4#c zC*AsMIil*{@M^=F)>Wc%i~{<|Lu~W88a6%Ev$QhEfVf2p*|6&11{~Rdkzr z9Lru<9k7{Rde`c9j<9$0SjyUzVSexa4n_4^ysmyO)t4Am4ik%aBs#dATt`$jYmB#W z5%{S~FR~T1GI#+1bbR&zi@@}o7X?VgRIPOrQ9+2}UgWlxak^x~F*|u*p$N&&k`;h# zOsPw4mf(%fFIjSHM>;E$J!e#F;=l5*@|_e3W$;pA$o(oiARQcBSg=M*dEGW~DTRpt zT#+)ojG3+2Hpeqzxn6N})%isFg|0g6X5w7IDO&4yZPnn~Gy+3*ua<4&+sq(BpOMh^ zR$~uuiNs0VtK44OZ~)B8OmozAwkecJrB{LnNV*S`^y`X@Szg;KsrCaoLerw~Noioy zYJ&}NxI9`i*k5+=+hDT@hH{MTH@TP6WY<9|CnRUH>%Cg{tS&1^P1eTn5eXgQt&qsU zl26yCNn3QB9M% zl#jz4kl~fBWy8Kl5)`m%p*us3gSz;5_oau-TRmqTL$=hLY01r{mEWI zDt49%^cGd!E_ds5YpTrA277CoH^+GEFPsiC1cd=W>vh}VF3T+;d5zr3%^uyYDyNJq zg*UhVq85(va^_0hB28lJ|APxHyn(lv;V~o=$EP=VW3H(A*5ojDu}&x$qDVfoT@V)E z`_w*UyZEO9paGt)DoY+w;_oEHt33J~61r?LJrqaIy2$X}$C%nD+ds$zB;NGX8HRnZ zf&erPU=uNF#xb$Vh^aTwFIY~mim$ui=Ga2bDoO@S13G031*xwj!K6+JWcUiu#OGmmnqmoS5#<$k|ay&Is9JI;}whr~@{2Kjha5(IaJ74T2hHZW3&(Hr(X9 zo4^VN#n{6jy(n?ir@h^-wA>XK`#hYjV$lxRipb-CM2=6^CaDM=Z32yOf1wc zxNf*m<*04K6+%DXI`tk(Wg*+=^`&W;4n1=HZg2&g8Fcm#YXd$O%t$i2mm$@_K1a^1 z$jH~5%w?9RRP}wtD~t4%j2#2CjG!w`=y0=i37` zyGfojx3$C(zZaeKn-@q&_@$?wZV>!}-K_1Dg?l6BTF8ghT3USWhtay9{+#sj06)Fo zk>=Sox7co?g-c2uNi!8$41f5_=H%QO=WiL zr{UD|cdNm^)~i&ruVQd~hMb{EY7Y0FJbKkP zh-3X0OZkaop%KYCEVitQ(>CF!+bVmz;QBsv@p4LEZhr6Dv_edkMeQ$+@(|5&B8O}G z_aEZ){e~<@zIW2hS@Z4&1pWMzRKj^|VsnF7!2pId`K?bDV&$BC&(Hhf zL)u*r^`=S5{MW|s9&9gegEa1#?w7BBE0OZ~_4T>v&D$r{na_j?1!mAI4vU>(dxz7Q zhn3|Z2p9=kilTS*sQg;{g7&A(A^ijETlHw?q2wpeXv3$@92i%xx76$66K6nBQ3uU>z+!oJ*tZ+ zTA$wUqJkW6s2yv2zjfFX!rEIK5Lg-NDYys&k0};9ifr4|5-L9)u$f{eBvXWpDJ14x zy=@Qn>|?Wc!{i-~BixNdU1;gu1CMP?6cj4MI4gdjq-GuZcbkn>Vs%EF-fJ;-Es3Tk zHdXMx5zkPwnl1K-&f2I6kdu9Q-RH4B?`-Dqft6dLPy}{mpx-{0S@R-mGdMaXYlwwR zCdGwN-7sSIPk;3-&(X)HRWVu|S4`ffxHSYb%~_zXC6v)!UR!kOM$barDvuJf-=UaL z_;`jgPOK~B*cjzex2gc`Y(Z7~iZ}5M{g?98=w~SZ` z-M4;fa4NdT!j$RVsBBYqbW5nTu&@xeGLm6FL*e7TxI^KSCI(^MkiA+HdJI+CZYOTN zZuWOvd)=(!>h5l}1{$t`!{LXe8{XorYus&jyfQe0mlH1@#a<8dU!N={+}lQczflU9 z)k=u~vtVT6sy82l&?~lRld=QQ8$Oek;PYiRo0^vGudn5Q54Y%xJL&Unf%QN<1GYC` zJ!Tu;>SxIUAx_3)oTXwEwpH72tyy{%=R41`LAG{!A*YDm49M x?Q(m4XQ}4_pI*AHr>J}ueH}~m2K;_Wv>zL&SF72+{vWojFf;%F literal 22842 zcmZ5|1z1#F|LrjJ(A^-2bV!Ow35axeNO#B3senpKcbC)v(mmn}BOo0^NJ%pYI7oxu z!~5O;z2ChL5Ae*)nSJ)z`X@B z|2Wgn_JKUEtar0o7jY%y)`Qnv2I+4iA$ao3cD9iNIF^G=9E-7MAYmxi*XLL-#sg{h z;=Xo?U)}z3;;bllPTd*L__BKycoMmzd2~}Sxmsk746{UH57F8t2>sWeY!@~dW_tIG zmTa&0mslcJ$%^^X&ksN}CAm0|` ztB|IvoxJWO>jb)uCImBTxzYL!inbCQ1jD>Pi-0kP=n$=5S{;bqHlbR@5R@o1G|SE# z37p*}l}ZjcLTotp`K8t8*VuF{{ri=9KEW21yZpwD4;m27Ob@ddpRD-leLl98LY#j& zxk&qY*%>}m7AA1ASZi1Ji11BL&cWRRpJmxay+S)b>j+xZ-6WgrU4s(O>1BQN<6S~zhq8Y(f%oKK*aB-|9@m^R zO`lr5hC;rl+|cok8c#5|FFPGSS`Jql`HlT0u3V^fxJxcf7|s6d77Gt0uc2o9A( z2>xE^Jbb7ZU=2es9N+Nx)A$M8jO$O%=x_+cj>PV+esxL@|am6chwz3lX~RX?f& z%@>Dy&RslvDRiOt?IL|*rF6Rm_`u_kgBIblUpcz%-S3mG+Lji28F!B6BOYH(~7VmjcU-RYSC!aa3}f&v-+J zvVH6jCUw+~eQ-F;btCbtOMUrt ztWYg8bj`L8@$G`v_D*X4*C!3*0#pe7@zR@f>=D|C#mDc+>B4_7JQeWRYBNU;Fu4D< zy~{_bNUZU7_95hxOupGtUNa-E7islO>ah3TOm($<0*2YNr9(jnC3JQ}2xa3GnvypV z;P!_XvOQwX*fZH^Yks(}{$6X5jirc>*py#&L)f;jRJVYm`dK5`*g+WDe09~;)Uk)= zwddttn;5efw^jExp>ax~IxXMsdSpyoU!d#2wdGKt@mIj_=jV;(mq*XCo+;ET)9XpN zVr1rQaCU}j26py%T>74lrS3z+^F!n3e&(VczYdl0l-brL+d*wDussZY_J<+JGmqbw-SW52fF0`+X10bk{|XZ7rtKc ziwr}@N7Ya5lfJ*~TNak)ocVQ|IuRnU6Mh=BTDfa?^Vcka5AYM<>TJpiwqmsgq~?7Q zOImHagt98hVlY8unt$~cx{zSyWfPUK!*pDcPz5j_1Glhx6Pr)}MZoqGKzfk|>-p$vl( z#HfGbj5D=q`0x8r~4r8#*n`?s2DYd37M*dK}W^HB~#Q)66v^ z%QX6==#4n1%~wwYcS!i{ZUSZE-A=oxuOEHx>Ps9>q>@9#t(0;_7p0jdLtkISqcTKq zGhH?Fq?WU%OfdMGd{D1>S_nKY`$c|oW_4?*En*++qRhYU`Zfz_+X^@5S@D>+$qUcp z_e`d3RHB@}yme1Um*;Bz`rZA=_?vh17b=u=rZ3r(Au(W67XooqX*P`?;(nzGE>jc# zqV@fu*4APh)#%AZ!9+pXznk6sYtxshufe?8nC7EUS@RhPVTHn=*INZPS&!@g_*~1^ zPZqvSM^#gcyABE5V!V+r95_(}3;(|OpM(ArZs)NN%2L|@Ca1fbRqk#{ikY;Tot!Ra z?mx{*+O2AeP1t&dv==xH+G(CJFG3+?;wvWCvH)YuJA`NZIAAwo4M}oS2iq|I32fWl z66PJ{2qzYpFp@dV+_~=3rJWe=pF~ohLOcKTb^OUsq!UDe&)$y?ml7;G#5uMM6Az`1 z(xlrouhHm@0{f!>mG5uoxXX_$^Zv7Bw+x36kG`Sc{_T^e+q^~26XJIww@n*=nXeYU zBI2jy8QeKad@k=Ea~REIn}P)@%XoeV#%OMc^^EfAwY#uVSQ(*3UtNuFn|wWu4Jg^2 zw&>(WI^ED0hVjMx>F3)yek-(Tk3ET-^XHvNfg9vXVdBhA=W8OJt-X)856^Gk+VnJ+ zw)t`6PG4vI-RoQV2ut*$hk9p|fHrPygloWHa+*P#jb4JhK5>zm%+QGBC+sZLpSZci zoMfBZzRSBCYxO=L7RhxMG!i_Wvg@i8T{0j^w|sS3{(PT;?NgaGg-|CNCi(mVAiZ-a9rC5Cgk%}w=J=XP+}SfCH3DHdWW^Jit2dB(xT zVDcJ??a=5vCgU3*9H<8Y=A%(kM=(oktFG}$KzmcY&Eq)=EHZRC1}XL)ipv)odi4KV ziy=tE;43uyc_&eeK)ck?EIDsvC7a2{1e`)>rymr_llWQGlYPFY?7)=X==I)43I-NY#o z^_Fw?^jSRoP&SanR~% zEMnKfQD~?q14zUAuDV*f$r<2044#2amiF6g7~|LohfC;9MWzT;>8}&PoDxr%_6DxajsTGb>0Lm8{%niW*luMUM8d z53iyG3G(SR_hf(tx(`_NmS@OcG*Nlj({d4+Rh8mKfAnk21)$g_2`6Scu$OZliXuZ~ z_v5Km4)a>DUcIKVqS46|mRJZ|ch}M{?DdHKogq_#$;NXM6s=%Nk$)(ebYJZhbH7h2 z+wO#MTqSUt!&E`oIA$?~t;Dt0#FHsquhGSL@h2TV*2x~*lF34?UxCAOVx+qaOr0@c zR1z2)bPp;b;SV*xJZ%($U)8v^Sz}uI7Yt^b0{fY+ZppHXk%xPIrDT+LYq?$!3X&k$ zuv9%;!;qX#bw+c8l2}=+@#07Ir+XuIi2_`5%{k5!Gr8{q zBYaO%ZBf;ixUmhacLJB3nd?&(Jrm8!>!5BI`O)0^kZ!%Z>>RGN(ZDy2}s z%FKi$RH_L~F{ zt1fM99$JD{$+XSRIXy>m;4sVvD@(?NUnx{_dVZ%}P_rmOu#tcCmOV0vM?;i70;i96 z1i1r6wcXoMeH|#b^c38J+2BbD^Dn5-#lF6hJjvblt_I9epBJ$4k2?*MD>^&1=sC03 z=q_LuE>3Ov1d(3sB`p8W6xdlxgWwbDKeGJ+A|AjH(=Qazm}KGaeZoSzm)2^8UN}VP zS2_)NOJhk8OLT|T^n^{Br9ELXmk3zfCANXxpN9bm%5e$?11d)pd-1Vb%1G}T74~Xm zt&dGtlr*(gMg*p);2eHpVm^m9l8U^0-bEb)*n~K?)OGf#H#1(q7;_HtvNZUCQAD9s z#bPB0F>$oxdUwr27LhH)j$cm1L!mwe5oM{QAUpvrbfJ8Y0>_|UToQRbj$;di%a*Y& zjzeW^c~V+IV;veUTYhBzcvu|^&`cLm&T6yL!w0WHEEsklFEQMfKgqWT&`xB>0m(aI z)cImh970nZTD9pEG!BeQp>j}nEgC_cOh9)VQXeu(L3to`9zZ^x4KaFhu9rZ!G9)Pg zo_-bS**UJOL4Cew7#8MN#whUmU@wbToQ)CWmnB>zGzT}0thB0E31c~Vntq;CX5WjF zn%j!4MzfH?u&=Rn%cQkpu0Hqcb9s7SQcdgtGEz{8_zXcsCe+G* zwHlp-6boTDf}J43qS8pW=u`J$=D&WLS#M`ILF>t2I!+qWg>jE)A&v+jmpzX)jc_fU z>0Ab`nkG*`(4CUl;89X)_%a1$kL0;8=~#B01NP(=f9kAO+~YZl@fV5~yVcn3Slee# z?>4anFw(7yx(1X~d?TB^hV;4ao9~~}rf<<2>CYtJpm~u&E^+Vt#Z;cj*WzIkt}t%m zLl>ZOw&?pIw_{|eLESj%@#c=z22;iV%x>bXixpdbp81S{9?F(l(0Af++~|guik_qo z)Hi)t$S+E2t(#o|tCDYrf%Zk0`EyzS`W1|3t6KBRrHM2|31U#-9CUnxQe(zfjp}jX zLT<_7r-zcoLRY|2_y`Ad_PyNTGw5rw%kB9gnM_AXG+g^k+>3pHC{E+OgSre*k8H7% zBM0$V*4V}hkz*fZkU_%EuC6z2HJaW9Uvhq)f6tA${j~MJYTbVEK>cV09v zc2M7lKEnJ)wlTA9dJ8&0p_22Yg3vc>cSix;Nk7IZQP^Y1QNjLiT~JgZ4$vqA8N@*y zYy@`gu56x#W;QW;!7;w&ij6`E^`2)6T51aC_%VHv05;iMzu$+6-4e68LDBr?0%9{ndY8#Xa{ z)MFnI|2Y)MM#3&`TT)i84M}SExs+BGKtVixU3A+q$8|b-Tyt+%fIyh=>kXCMsrcOq zl5O_GTlE|!sL%Pc?c7H8bW)4;gv}n{Pq{xy){Nec0 zp6FJxHElzO68jRtTU7My+-81}<2wF}@u42;w=;s6_`gpo zeSoC_P3EpsQk|<+EKEQ%b?Jj_##+xFuNn@WP|rF2W&Rmx%k*sdT;4b92XymFy?)LS zVvRjHIbD|L%(6ym{p&{#`W;Hj!7aSSr*7NM1!&b2ijzfNEC^s*`W6f(@XwqL*fbiZ zSBv=*H4YW{CwpLq>SXZJU~dNjf%t_`-1yg{@lX%Z;mn6-ZRWl-wI5Aur_)7TG3Gn^ zf|qn~uBXj^N~%3&2=X2L>grP=HI>|>Vz<@Qyt4mvsm<-UVbU#}>B|syu1yoz_{%`; z*_|*POg7%(9{am%T+hXJ1(Y^HBs|!q!afr|6wHT2CbaUeAx>8!WDsA^{|ue}9nRhW zpr+Vi(30u zQCkt=|Mtcp1@&!9#$IMb{!WQw8kV5X-1~5c;}b)RPz#|? zc4>c?cSO*lQiocCt zoNYuGK4|14!WDoFAIGIQi~6Q^*@xvCurUfBZiv1v?s+gU(n5ZbUNzr8q&Mm?$`HOI z)H(*SBFgU9z0jx%(zf>JV-M&Y*W?Fa@&)uU0jB zy_62^+b@#4WcB3pY@}aqEonFf0XhQKJp0;9{^C8mpUMNcFHb(tNb4Q+kkK_2dyp?Y zrMxhYx+|(4G;6Ez`58qYJ88l{XCH008ODB8qdgBKAc4diV+4`cZGu~1H{Jnjxmr9U zTq)w;&x)#<08biukt#{B%@zHHw8>fOwv=as{UwGY zHtGrQJ9ZS%GXp#$4v4UFwhu{a(Fo%-(e81*#N4cd==X{Fd?zo~-*8=QdcW|Kytvd+ z9N>lG3Xb_ilhpQIVH<927%QJMP4t;A5*}NtJzvR*3d&tDmdm|72q#Wl>0;%`*_8Bb@YQ z^0RA{AW^vqC{#Zh@de+4`Bn8ilgrQ`#45uSFg{ju!tafNT~gbUTCGl~d5Zy+UJiqa zW_XNqhuZWZInnUYrq8YW*};T2KZhp3z`E1Mq^aQc~6f66@ofIe0Cz0G*|PE>f` z22io!A}{8Re=QuPz7qYqN;rwZ zD%RvX`@~1DG`P_&J9O0MP=uz5BSrLHTk2D z!~jl|K}yFejmiN+Ed!~K%NuFH)uS6gD#6fEXPa5)TTrFj+FlEMTnE_xqX9vk)dteS zY53992XkLF?N=A4m%c`*XABG`MEL|?KN=lotU7(@r$lu?89K2RK4FaW%**&r0r@9& z$8PEgK{14FfTmPqI@*iTtAqGNk-fyR@0^}QQ9)QEz50#T&TdM_ANKsoFx8x8eSvQL zN=Pe5t6GMYr(pN8+>hHUX)kFSpmMq}XOX3m5M4g?^V<48Vw1cU&;Gj>-g!0vdxEpg zGWh+%*fedaawHLgCq+r*1Fv+gQNY|6B;RmbZxU_spzmSP+!NIiP>=v^Xlk5Nb(;*? z+494AX1Y`_^tYRNLWkol!|&rky|?=@YSUz$p@!XHk(WBvq=GLT^i$8iSO89F0JCjm zc)S^%!}dEw`?nhrQ7A)TujSMJg&SryBW=k@!QplA?_HAqlD*909%k260{yGUjjL}g zU#14Doaz>k5)2zFZpF^S4+KF0QXtQ*8lM;=0>0*qNs{)S- zS2~1aD7up2PvOJx+S2bGO@*jT^)w@MN6dGAsPG?C8L@ZlU)JjIX1ZU0s#!p|YwYb( z_SHiV>GC+VXhQzlzW?WJ%PH-<%mIad1@zIWK_?_|TyF;|KJ01TcyoRA253xmtvC&+ z$<|$)_R+fUf8+tRb7NdIg`~lH71vCuhED@Z%AWreeulcE?RZ6aYP8o^4RV#<(<=#I zC@7Y+jtmI@OUr$&IPLD*D$|;T&^byLS5a%au;k*9v zM7;|fcv0iV?=^V+3ifH04AT%)s}#~5EXerH(;!G_i5&qXX_%_CS1)aDmP@fWo9hYf z$F;BTF`=PmF^dqMk(nuu#kmICmp_7q2iyx07zH!ito=zM9yQasb|nMba1lt+`s0Bds$vUk>4E?@_o(pMyH3bW-~cwPIsG9GCNjRFDaDsmCS8-P z(>t?gVUC@Xo00#7PxueU$)cjdcZ^$^j2&{>WDyUxC8|_ZYf@OG5%zpEMesr8*nL)+ z;^^c9b=RgUcJzu>%jWg#BE&+Hs@>+nb>RQ*QV$jyJ~FwlbdAbIiYPi`t6ni`GOMAg;Jy8R}vzxFgTUXs=L;H$>l%@~AFN5lAoL<#LsZdA_^AIV)sCvs-AWkOpOI@kQ`1vpk0)lx>BF1R&Q_`KlVZP? zBNJ11wqSJV`C%|{@Va7jZKTpVntvKVY)0#t3_-l#dpuU=PXkrg4`3hC1D<3|EG^H4 z{2_HHH3u<*r9OK73}Lu@expz4RUl}Y(jg$%@k*LFNh7OOpqX%m`{r3RMd|aarcu5t z+Upx*usWtd9M0AJS8!kB%l3oiuQ6Pf+JQL9BDOR36?y+urq_WCJCt=BUS4e}SzpAt ztWZt?NR-Q_l1%-`Q#ecj2S&5}efzrbI+&TFq>Pu#(ysvbLF(jkR9Ka0W5A=Z5+_fi z;~0ewxeWjGXCamk^Y;ZNPh7(KvwrXxBpF?n7$Iot%v!okFzT!}I*wQe9^zFgy&(sJ z;B0JtN4Vr<@rXNR&>+-^4gV*OKhf`IPXyl;;2kIZs1&V_pB~S%>mY;BRPRwbc%zY= zdfYOdft9!XGpDATk_s^lkt%XG>0;)Nwl1}4RB#Bj%3gBRN|orzhU&GF%qyThdh`+qNBb6xSW$#FfcyCr-<4F5GN~uZ9SZ- zzZO4%MvFw=7&zC)3L5SJz=h#QFLM&Ijc_X^QFeS}kSZ%9@(byBLv$1>hW_9>RFRdM zV7L=@n&1btH7KJ$grN`VQ-Ri7@7>JNl)LzR6QKm{hR7n!xsBrtlujHit<(2ulfKWk z{_}w~b|X2_xQ$PdoTVuH%dVu&DpkggSB;;$WxAs-&dxtsc8(j8YwjVjHF5pl$KIEe zkf}C96z-ql3q>bvfv<+&mP1;Ou4KkB`eIK)G-hmoF@b;scF!$%NW`)zN)g`bY*vw` z%WVpPlo{?(&vdzAzkR1nkgV0ON?2+L8jUwF;W7U1jc8y`9|PVfZ~HJAvp*r$t`H?PXt3C@y-Gz%+0yYaW>v(j{HGTgdYC`C2yO?*SJiFIy1j5Wc0EDC?@}E+TK{?& zisbQ*<+uNj764K|p#ER*h>eTJ0Y*x+0QXrO%Ko{5C|m;~SV8X;z{E+@aOQ(KqK3iq z_u?^iY6bikJb#yXXa1bIp5bRFkY66qr}B~#lUjcYmZE=;8m>@tjRU$vD!aWOcY5$d zAn|TVP6Qe(!_VYj{OBUxpkKG0`fxi0Ei`{YE{SWr^;xEXHRv0(@Rv&>ij0R3H@xdb z?xO7&-VD&{7D>Dxeeo2tqoO1#=81a7-*k?8ZXDi7D)!XL+Nh@t(}%&!g!=$Gs68j) z)vKKneFV9EwehU!L+Bi|Ftnw;_Tu()9d==2>{cK$D6T}TCdl}o^+T6Zvh&`)8kVM^4X~xIcz5lB+7Pu$|hm?%i z!$qRp_x%bUSpr@|k%ZES0!0{X=2!b9?(s~vgvBq#RjSM3E4@|@aj2W_!*&2elOt{jvR1{^d(o+DrNdsLwv>sY ze)P_D2uR6PKoCg=yJ96BLxxvir&}(Ua3~owcAt?uU_fHB)o&{^EV)8us8bm%cIlEe z`ily^+#I!!?wc6*!%YInZmo|+oeGan;z)_>Ywz@DrK~&Kl1HM9$jukV>?btQ6y2}U zM*YpX1I8G2pp@u8V88~FyT^qybLl%?6+cy3@p+97iK()Eo?Elw3(yY&RwUEkl_UMr zRpda%%tXW9Nt;xBj7ZxT9RwZh^r;QI*Igy9-2vcZvWm`HmGB)SB|QlgnBRA!gPDYJ z2j5;=yv{vCGmicDH&t`*-r0i;RHXYfw`t7}UmYryQ#C8WUmZ#r0U&5(@!?O2m5zUM zw>WF^AuS{;XSr!k%75}*)~$3>dFmjXXMQZUxnL85#ss1j_FuT^Z_6~$f6aG?%MEd1 zG&}$vR(h)(y#p)$z7N=J427h|IuDf$Uz{*ntu+o@oC)VW=l*AGDg{(3 zdky*~1cw#>Qv~bP5}*D|)#9D+z$opjNdS?&3s-~1BX_#dSjdMW*aZr8O!5pMc`*BlPHhHGa zoU;n|^3lMb@lk~Iv(PX1EL`VA>+_rL{9$YqFP~E6gQw#!se{AsQA%>>n)jEpVX!quNd>{QG zI24N%=tlq_UU-|$K>{?BghciD7v(&b@5P4O?<6%xAuD~bB<2_k?SrTmJS~3>M?pou zf8b~Qk@grH(@Dir8%C8bqN3f(BwmI97XjqV`{H8V4BkmM!J!K25L;sBuOQkfQZ~;c z%Z&4pzo$9+8d!3tPduzVqc%s}r#4N2s)Z1UX|x-gX61{%bys)=)WK83fgU{*568)6TeBJ050Rl=QHNW25dx_z! zuW;b(=lo~KIEs}unE-1*JW zZ6hPNxEyHhM1T_D?zO+Lg!&KDb^U)?oB9rJ4e@y}-$R8jq)F5g$mAb1uc~o*z6+)T zS9VvLZ*aJYOwFXaW?lD5KR4wL2U)Oonx*e^g~9)NB%xa*J)-FZ#4YB*MzuacuI)$0 zlbVX6^jm~c$M1c7B}#nb^QP@=0V@UKB>=I$J9#K85ce|m+FRxHRMf2^xAhWZcGFwc zOn%Mckg>HGa4!f}2SK3KNJHl=v``o2l3G-;;Z;mi!lGPuxG$N-(x&Vybn+>fQl_Z( zoj>+dvyEQT?lbO7^QLBf zX#UpeRgbkKKlVrG=7YtBq8&x7z!w9mZ?hDq*0YBFlD$V2=BlanMxQR-A* zY?$75ruWa$t#1%3I-sP^!=&N;J_~KRZOXp!&^UOH7l26-83~UZPm1rN$bli?$4ryF;$m>kf(J2i4@jj}r?|ba#{G4|X&tP>Pt}&ju zOyQ{i|C1$)U`MFsRh;JNdv$1FH-JqkBd_^l8&_giqbDWW|pOj;ta zXYKY*Gze|iw&cQ#6yh04(~`;AHw{u^dO3QntlM8?*f-f`-oSMHC??4Sy_QK8?Dhao zzmBL1Kuv{fBdER&r!o)C9Mpqyjn{U`6Y%KbH`ik<1Ep)83d#>HW!66(U&J z?H|w>T&N0419TM-(TIwp_{m3J8hq@U4bOAYUbfnQN=CF4@n~F&;vGjG!d38!@HuBW zK60@E1S@5+d#9#mRR_W4%Jr*pfPGIVAuEMjyRVqG#6*^{s=V_`foGg{oly)fdEWEl z>V-@5E@8po05)aGF?=AfC?Rvyud=7%F6(QU%*}C~Yp{Lul96QT=3RoqqFUe21+xOcm=gAdD%X<>F)FCNn26r7fV2+XazD z>yW$NOCJ=^!q?jl1Z_g$Cs5h$FLXv6?^nvHIo@eBm-5#jX_ zeoTtlQi^(J&>3{(5>~~6_=x?2H!{!ECNXwpX7Op;!&O$|89XXN;0#`~88st~RBk?OkJyST!dU+nsnf z^lBPgavtAp>%6J!+1ny@5js@){*UrpR0yA_QD0FL3xaF@*GTnxZ%obY6S*v&8}4tW zfYI(q>T=ujQpQk|$-a6rFQaCBvMRqGls;e>H=)y_azxdkl7TWaLUrFt8H(|!5_s8p z^K9eS(+={Rsa1TKx9p1xD*M1)sQkK?%z^h?Ld=#mGN@+CX(e?+>hzmg8{As8e zY=YO3r<{AL;2eNzXpEyzR`j~&E({%8xm0MJSnI3Qk+({#`oc@+p@b9SpDME4&6)@! zigH#@jV+oNUp=|)ymFws>av0QW-V(7JOmUxcm^JZmzsQBYu*KjiVcfI+tyjgKJ2%x znMo^720m9sKF6_?)%*^#C1#)Yz@{OeWtUvDbm7EA%&J7{1nod*Qjr!b_mEKhSyw2f z@E;$kBI^=h_t;cc%raOoWW$f?`}X*h>4x>yeZsyCwxuK|pEXa=ldAe7y+qj?VmE^^ z1~gJUEXWI3`vvEkcnubbqn}i!v+??IMq!=Y0N9Mb6JwSTw%!6U*S>jE6RA+T7*+?y z+)__$3IOn8)5<&u-ICp|)AhY^Kk^A9!8kIow|D^m)ppRv4cWH9ixAuwdNE6I5|o}C zZG_%WW$p$8a!UAD23Mt3J3SbWSbLGC#)1FYSsfORF1I`oUxSf3BhMGjU)EZ&^<;?( zreAm5V{&BFAzp*|2Ax8Q!2tVt6V07BVLT zy1#1U144~lU)6T;O5HlFHj0gRd+I^+P!2tdX=fQo`I_>k8%_x__=@=CINd9ymT-F< zQe4dqFbVNvQkj^~u%q`ao?q3X)GM!@a^FP0^vq-Jg$eWJ@q51W!XLT4$A@Yex7}vF zBVCa&etTluP-L5VyYgH!c;Vp##wjvNPNbu`NxKKr->ZoTbHqokeLqRpDxVmZp^EilPQEV3X;2Is{gZj*i^Evq|`7uZ?gSzOTA{JeCE|i2_Oa>kzWQfjb7E z`XuKNKI@oxdam`C7`OXc5k5>Mn3b z2A=?Fo*ZMKBj7V#<7p~(F-MA#X;DFNW_UCF=c_p5UG<=8_pa~JMh8);l?;LO**dVI z)@p&2=y8nFJ7`bHuqc4_6>hMp-0`Va;e{-$OuVVXHnuTEq=8Zek`1jmrgG43qU=UM zVS+(&j^ly5Q;B)YojQpCYWRNp7>{GgT_<4qqsu#KE;Wja9@byxkY6*7SZo{Kf-2S5 z#n-W8d@UTgX$(PXhrJiS2pgYE`}-C=q5<$5KKfKafG0|-VT6r@!DFI8f=WMvEnRh& zN1QRnz08x1STVj+WPkg`)V$RX6UkX3-JidUe52U$8JelSR5cPg(8|T165aO&kZ=J# zz(kY3?jbwa;nkhuiVw&9}$%@2BA;R7vtzenx5Ej}YDo!$T-r*2f=K;q|cQ z1p5bYXq0GC-t1Q)IDp}F0MaL1Hhg#NJ_aJ;CQ5#GnjOyHZ)!w&zda9>J?Y>Yoj&7x zuaQ<2@10Qcx|=aDtBMi1$llLC6rMPY;9gnk$U#_A!IESCxjGc=e8&#OR#gyXpD}mz z9)@9bJ&?k8dwRj_@5MAI2<&EEt;$l>ZSIQxQ}dWP9=>#p!nl9V`jq7-@{#q+)Lnn) zJ*17L=i^B6up}1Zio7dW;WUwQUqC>1d1Uk|*EOmPaC2*<2|)Q5WAgL*-N;2|Q6(kB zlp}za${E-(dQLJ$XB-*qS?)S;<{3f23VC`y$D_o5T1})p47Ya~rt`OahQjogV_|pF ziRhnBX`z5&m?OLgO(Tg3>!tc$wS*$T*Vc<}i?l=|XeZ?zoa;qm zd*Vnrzt?CR02Kp3kh#?|0Fka$m8hn9_`PK0A|&ML5HRg(Sn_G)Z=7vYqzRg>lxyu& zYUi6p{jnbtf~p&Ts6e(>e_s2Y4LyBPJE5_7Kx?0`d>n=7nECqA?oHs+{MlzJ&3yCh z7oR7gne0z6MRYU)`JjftDZ|WC{WG3?40GN0mjBR;+p1WyWX%&j#=V50qyzw={lksu zKXU2y08Leg;@d8N1bc=Xofe7Lm^VNHu8ksntP-6DfNOf~+=)@j^2b=`Dq<%kJ~@|? zmh~z>b?yH;DW3zk#9*Vq(0}v_6p zQ!q2zHeb$6l>cBPCj-ziX?x(D*Usfx0}A=n^FT;oL@VDjeK&xj%wlFVkC2+2lZB_$ z)L{rrVZ3tF*sJl9-;D*V6xN)(G!39iAAJgV0s!GxJ4$L(NYr)AGW|2^SL+a@_+gZ& z7Wk|hdblO2*6C~pODj5lh>_1t`aY)IeOPE(M3iXR9}iJ`A{eFVDe~u)yDM!jTD&^t zG>SVF_FARlg?@|~=}toMsR>mxc<-H?DOKsv5f+o0t1bzUwWt>WG6BFbOE;Ejv@(dM ziusap?9Zby+O&A9;y#T{(#J-`1L6cg+{^387?2i1J%8@MnH_Cu9ig}J__l6$Kdm`Z;PPGtXGMkvr>mh5F`q#Z7_ z8s;CnCA8jj?tgdfi|ftBJO7iQS=DyY&2G;$??YvWQYDd>hg86eag^uzIbq*~fv7!*!j4q$&9{TP)b z8ejauqzj@%W)`vmO9Pz__tKSZtnKINj%BR!bCOYE5+$;vfdQiIdO(J__a9b+LafRb zek8xSBX@;fT9*a8$`h{&t}M+fv7+DIV*V?H`!{Q%ZW#XBPH#RtFX*0mYJQpT(Z>wm zd7R<+8Xac!i7Um0KV0DmOw2ODewH!RCC3E8)2e(v4LyY1eg-1RJ3wj@zD-@MH67aH z8e7K=jRgdj(h9D$lE_Dh-Ua9TOfAjm5y7N8r%_&tpk^#^jhmu;{isZrVuW1N|`H&{6pCQGz zfV~)$h)}1hSvdY0y^RikOwj0Es8zh^+ap z$RC&esd`L?K+=uH)mKTdwr-i16iKe}cu!ndmNS=W^ko;s1OpCd1H-Ml zw;-GY6Jji<;$c8U2izk8O!!q*V+0>Ni*G?i_LAX#h#ogJ=37i7T#nO>B+QC6?>cWF zqUSx)+@hu0fndF$)$YLUcyyvkp7H0;w_;`U2F1&s@|=So^sTPIwNq{%PjOrUnxe}w z)5xUvX#Lh!5Rk<+D=wuQd+~5zDxfP|xQPG5QJaYSh1rFy^GzQ<2Btf@(XmRIgt8VV zGTV-0KWoO@eJ9*c9nTU8k(JM01ay3z<3FCXcKK;;NgB6@x{M=sSbOfEhikX~|2L zh<7;lvH{ko6e@e_#T2x1IW+F6Ar_84)_buhBY>6UGZtZ|-$TaO*#6Skajq*fv##p_?a)vKXZ20vw z=eLP_(K3MX8d(br)K}x@zf$wXPpSmK{axZ8+Ez(;oS0@MQV*EbR+YVP+(pWfP$iMQ z*>VqL!*`OpHLlQ7>R|q%>D)(82cNKf%{~(o)P7px!&*bQ-K@i!xdlT`a#K4<>13rB9^* zTsNLd?j;+3FVlveQ>DQ0H;J%s8_{<$QB2dLlN zO}{i+cDQb>#QjIf7!lX_^znlcmR`xEeF@V--;{pF7pcMABQ!cPfPQP)VwXDrNPL`= zi&UwARQcDNR*(hS=_TFM)sL%~Rmg`+AuS#sZ#G%UIMi~#*gSta6KCnn55THV>a9Ci z@8-n_Irs8hY1=NGnBZ93644sX0khR7QTn-W0Z~bL^AjBKbZ}`*h04IU( zH9*mf7{KpUjTVV*1w#iw$G3lk(1J8UJCFSSg8bMHRdPM+BNEkqir=Ay|8I#Gtq_%E z(4m+92Kzi>bYWV$8I;)G<=sgpPoPk04g)sQYW=A;~D4!5kz|1vanOi zJm3~jfQH@Dm!1Hdfj*wt@NqrMltSu=RX zmz#K0twE5+=NWQpcxFbInM4VGdUsS&#mpffl_O?Iun5w3woYJXijh3Kl#?7(xCewQ zRCbhrE=nqbR0!v7M*b{S`ZEj18hywGFXMsaTNdDs#wdo$kqF8@jP)R?t&3kks@(w; zY$WADidG?75VV zU@zXFZIL-VIq-%^g}f{mI5g9y8Eniko#%~t5~_OJiz%8qYm%5KRSDdcGpI)|(I~>z zk3P*Fa%A?Ub-N?NBiuTPi{ydIIkHzjX{n!c(?c7i10wYowhsd^XHK&J)uW3T^oU+y zCYpH+zk-!fnoW7UetP$NhT)0Z0x8e@AD5IP-{~my2~!_5>R=TSVSM3qE!=STvk!jk z(QAN|-rv%kArGl*Zax)~^*0yjKfP`eNwPn6U&W5xovRKE;qrg$c zqWbU(Q39=aXPoWkFV0GjX>yhz=WjR}h=<3B^?Hc$BP(kbsd~B{tE_nU%*35gcjMx> zZ{y>?zXb$e2N}3O5|N&{%gOPam|63@@cYuiJ=u&(@`0(b8q9W0c4|+*PnY4(Df(`V z@oo2f*>iU*O^Z0VZ75+WtM7Nks&vRmzuC-EPqjZr9YHd$IgNgyi}lU@Gak0KxwSx! zqOzqT=8pLPdC)`9TtyJQw(J=0|9yujKlc|E2|yvx+OjD{C)Sv+OTPT@@1r8?LzTAuO0?-vAw*bl62qu?RN3jpk(n)aN?YJ5m%#lM2l+sl{{5< zkIN+=&baQQUTFTYq?&e38z^&HTmS51|L36XJn_(AQWHS1pi2_*SKYd9j7E?z=u3|W zp*fvR06)2#ZOOeVzmU%eF+XkVAS(F&5n3#c@yXP@-ppibT3D! z6vrRnyR|S|$;FaP5QaCt;k9hD&M8S|3Jb6 zBTWVNc*JdG_9T@)6dUcM9WaTH_xP5~g=*yoD>LQyt-PqlJennfSs7xU4X<%+NAV<2 zL=CoXl-DHjUFm$5g#c*s36t`PbHO8*M-*86Dp9tP=| z=;q&}JhQgoTO>`FV9P2Ie?wyAiRFg!i9t%;t%?O(OYh;H%vJ?R2aPSZ+;*||E#Y1kSRaDjMpz5*&P8Nchu9Y3e{;-_j^+&4}?c#u7x$IP3Wukm3>~# ze28LjEx4oc)*RKvIjpHT2G~GbdNd9lS|t4qgLx7pu=j=xb78Ef2Hz2$l0fan0LICt zsGvDifE>B%?1~c_3*|*we~gN^cmYLKtr1P^LbwkH2w{3yjY;z`6Wkg5h3$2oC5{nq zLsyMH2CmrW{kv4m)!_gC8^dS`sm1!#R{|^xilcP0&BO!U83649LMRn291(dWR#c;a z`QL9Zu{dWy+aX=%ve1Cdzdn)1g;IpaC$J=hg@wrmd}%N9^u?OS69|!uc)V4X+>B$9 z(llrn*6${vX~ib45wKL2Z_a?GsNRfSN-a`?GW+Caq1Nx8^UeL-2mL0KxjF2e&y!Vq zmuo`i_9kn{oyZA&Q_boX zzrJ_#+{Gx)iIo7k9Ctv;r3%VZdJ%N&W5!bXGMXVGlWtt3W4}Qs4`f$w<5mZ-62Uk) zFC*k_JsJX>+UmBLG2mSn1jLx=J*-?X!x`&745oOgzoF>O1f}Hx$L6GP8@<~xFw%4s3l}OIw~~7gq!=HMJ1hHY{_VfZ|U>b z-~3FRLg50U4aS2@#;uWq-O+~0a0Jk2{o~%1x!`r730}G{ zyb?S+CaS`_%&?@KkXmGQ;%8;Z*`i*-p`uVwW%_~iYmkAT73ope^v$)qe_-0|dImvRDL&55enl1MWd{w^iPG7+ ze$9T(LA>rShx`UfmQcSYx*G^=oMY!5QZ&hme z0MS9uGf>MV3bJ;xduK_hI$CrFhx>4!(6Mn@g9y`OOHbg#V~!-lOHk}H++#j0KtdHK zK56$ee&=Cv$&}5bfT3;but_d!60C%t4Y|KAhq7qDx19D(9pG(quLEnN_jt>cz{M8d z+TKMViq*P}1Q*gH!AHL1D{UXdW0WUq_bggSwkcy@Q}=}t5<~rwTDVbo5_B$!m&V69 z@JE3Vv{lJqzRHa3^vEbiIh~BxQTq3e5?fS(^;zY2s9xzSYS4@Yrj#l=-AZo;oa*_? zWd80`uMj9RbjYJ;Jt*O(Syk}tH*r6sSNpyuTKG@DDU=u-9H*^N_T?4+Jv^Z$m5`TT zxY<4UZ>gZyshB*x*fem`IqPa%9%)lDINVt-+CCcC;*OgWwL2jt<2=6WeruGK!;{Sb zCw$Rji^(VbJid)2DAM`S@)AJSS`(zRW(nLVSmL-igH#`#MQrxQ~Pibvh!2KeF?~BSA zod48vH#4{2afzIN1aNSfzAaz4)dR0vQRo6W#EK(V@jViVpC{BvJV$_z3SGp_2~_5d zj?n(Z7Os$zhTLuCv7EkpFGK*~x#i6?(Rux@3N?>~3m~5`41^`08OPI$D`eYh2zr1- ze`r=P@CWc6(ys;8zcYqcfoxdqQJi}x0F1xZi%NpRS+OucMj|aaLoX671lq&%?O3>I z?DD%IN=z2uvrG%Bcvz1^mcjQ<-Fz!w&)AEWOb4_q)j&3^Uc?%$9s&WdW=D>(T^nHr z$MUl+bhJix$9{(Oa0SZMyZzw~?PRvx_IaZeVSXK`3vfNof$Vto#e+L4cCxD^I3gDApQaDP0G!SW$+yTZgn9%vUD)%1RUlfxP1+#AlU4 zti;MXW9Y{(buX$7WX`YQh)-zK%XADEYX_uW3dc7yNT85V!W~{HV8W5k>Ve^s?+yuT z*xx#aND3!ly<8(d?@CRe7+HT%64?cSAkZ6F;%$x_g!{x5%Eh1nE@87BbQd&@+qJsn9Ox1V! zrwQX!m15}3i{X;c=b}9NA$2OKd9VtH0Mq`{dZ!!--2yyOtT(hodaICs;vd4eMqf^~ zB)?L|_@bOXF|F`WPfLk7>DLn<--KZsP%n)EER?C@HmTg-ZO%iDQRg*IKcfMsd0t*Eo*hU8%Q zboJ+$q&D_1pr_LIb zeILlW<~fcDanxZHMkD+9gM~~SDWd{xEr?2u53&~#FB40pd2ufD!zr@rtY_e-k70Rt zzm8!hRV-gpq<>Ik3ncQ2csI+DusL!?AckJcK=J+8U=R8yzbJTt*u(GAa<_-LP>L^I zv*lp)2=;+K_skBme+4V1`NHxg>{Z6L$^8z=`2>OEA`8=* zTZzqO-eP}uG*HN(FH7T~VFrH@gz;U=F3t#~2`ug#1mb$DIO?fG=>*ylOPB1MAP3&) zX>inXnwvtYMCW&D*mAJ06276x5hz(*-BzMAete&;bR-xtrq_7IYI!kWYceI+-K#|C z{3TlC^bMFFd+ws*)X(7D!rH^)t`_q9fFo$m?z{5CPzT3hGsX8*yg?X)WJV4}Mqzx^ z9PtaPmg>}#D7Z`0N4FW{asQ>G*0#v;#xw5hmCeP1?zjj|q%Rb~Z>tDy76ytI+8sJ4 zRwS&NC$;N52K3})AZE3L$By8pFsEO;DZn#`1m0cy7^F}0bXpxhW{`k zx9|aSLeXHR!9jf5FSnz6brz2;(O%Ch>DF1`jwi){vcW1 z383sW5fD$(MvheLW6I)K9!QOl!R>h!`n4zQHfv`jZvV5?!JRfy%M%6bnnO`TxH09Hc7)H}LejQ#Ew)N+ zAl$m3?!{r0y2t=$krh0031_w!lMyiT%W3WX#wS4QP1jXsX7@lm<%Hu0tYCz?CZzlo zSS4@k6i)ek>^QFHQ?aYJZ;j3RNr8BL(xW;S7snX>y`56gM`yPQ)YpOP0E}TC#R&XT z)J=#=>e;fLS3efQHfh7lqKL=B<*K_?siue(3e@sSYwaa?kO%o0}Sooh3(kLKonOgK`H8-_{LS%h}LsD|xqLvaX z2a@y26|&8h9EEfKc+q-QKOqW$4NRx6k^Qr)bE zWX6*}L%a#Jmw#lB{p|haeQ|sOnN%IFrLD72?_{>G9#(#4)o786`RJB7K~A5kJZxlA zKCV@JB(Lc`8hvj#c$<^`C}$Dp!JCKU&be3gz{;?9^I}_-nOmbp><`sU6$0S+TLLbv z3?ZysyBJmhz1QaDSPsDD@nyMr2H%rj7BBL7iU_Kb<*EVr;3mT0dq15#&mZ%!ot)%B6T3`!j8E|3cV-;&s&~fNqdzE@7y85$b^c!g;wxN zmT}mSM-EByq5Et&X(&iDZk>@|x1D{p^p94U zaOpDQD_K52b@;nPz--kj4fgsz<)Y*)0kbuhbvr>m;r z(?3V}&0=CyG9EFU$f1df4W8qCS|z4XTAxaa3&ur?&-Om5jl(X>?TuT1FkZ>xoFe3ChwxA?1#DF_rr zfToB+;{~sD8Ic$NHTVCCqWk{-R+dvkDSre zzq)q#1~RApN3E|6kTrSgKi^72?&?1!o8a2U3>BuzaiD`=MUy%W3;!r#8)8$>qXyye zH?W7xsTi01&4=3`^CxxdC?0ZOSAIc4G^5DBrItH z+p~y$%XmiKFzm18^fjtFz3E~pWAwsmtO@E{{Xr!9?)*oCOx_PGPtJL;3X9Q#U<$f6 zyA)y_;(Cue+25P9i6h|VAYoyHT4jhsVb#kQG!Mn-R#PMv3Gp-XI`N!9Th~{)18#cI zPa%*konK`gWq7)Sn-w^>+pY-0SdCR|UT3Y@d%4Xi-g>Qhq!fX?s0C;NHhfirg9r|v zbLFgG!Q+Kst54?||Ir*T-}}%CEAhuXx>o3abTz!kdl*!a+e(Hsh1s^3zm=Hx9m~aa z)$$DHpqdw>kuE*QHk*4njnd`m1Oh?Tb1Xk7=RRxO36m3R_~?rpy--kJ|L;gC>pxLDVW0&EW?KJg@#WsZMDf-;(olUwXa$9ivm~DE5Kkf@G+2NMrd`USdzGo*6zt?37Nb)p4 zem`9&m%nt}(>n-DDQD)_>~j0k9yBwP*fa;D09FLp`TstQBhR(!ei&yZn~6mOV#pNt MbWL^Y?m8#_9~kSL$p8QV diff --git a/DOCS/html/stm32f4xx__matlab__rcc_8h_source.html b/DOCS/html/stm32f4xx__matlab__rcc_8h_source.html index 6d72153..a08dc5d 100644 --- a/DOCS/html/stm32f4xx__matlab__rcc_8h_source.html +++ b/DOCS/html/stm32f4xx__matlab__rcc_8h_source.html @@ -5,7 +5,7 @@ -STM MATLAB Simulator: F:/Work/Projects/MATLAB/matlab_stm_emulate/MCU_STM32F4xx_Matlab/Drivers/STM32F4xx_SIMULINK/stm32f4xx_matlab_rcc.h Source File +STM MATLAB Simulator: F:/Work/Projects/MATLAB/matlab_stm_emulate/MCU_STM32F4xx_Matlab/STM32F4xx_SIMULINK/stm32f4xx_matlab_rcc.h Source File @@ -14,6 +14,7 @@ + @@ -76,58 +77,80 @@ $(function() { codefold.init(0); });
  • MCU_STM32F4xx_Matlab
  • STM32F4xx_SIMULINK
    • stm32f4xx_matlab_rcc.h
    -Go to the documentation of this file.
    1#ifndef _MATLAB_RCC_H_
    -
    2#define _MATLAB_RCC_H_
    -
    3
    -
    4#include "mcu_wrapper_conf.h"
    -
    5
    -
    16//#define SYSLCK_Value ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)
    -
    17//#define AHB_Prescaler ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)
    -
    18//#define AHB_Prescaler ((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)
    -
    19
    -
    20#define HCLK_Value (double)72000000;
    -
    21#define ABP1_Value (double)72000000;
    -
    22#define ABP1_TIMS_Value (double)72000000;
    -
    23#define ABP2_Value (double)72000000;
    -
    24#define ABP2_TIMS_Value (double)72000000;
    -
    25
    -
    26/* Эти дефайны добавлены в код stm32f4xx_hal_rcc.c, чтобы не попаÑÑ‚ÑŒ в беÑконечный цикл */
    -
    27/* Мб перенеÑти в MCU_Periph_Simulation(), но чет не хочетÑÑ Ð½Ð°Ð³Ñ€ÑƒÐ¶Ð°Ñ‚ÑŒ ÑимулÑцию Ñтой херней*/
    -
    -
    28#define _RCC_SET_FLAG(__FLAG__) \
    -
    29if(((__FLAG__) >> 5U) == 1U) RCC->CR |= (1U << ((__FLAG__) & RCC_FLAG_MASK)); \
    -
    30else if(((__FLAG__) >> 5U) == 2U) RCC->BDCR |= (1U << ((__FLAG__) & RCC_FLAG_MASK)); \
    -
    31else if(((__FLAG__) >> 5U) == 3U) RCC->CSR |= (1U << ((__FLAG__) & RCC_FLAG_MASK)); \
    -
    32else RCC->CIR |= (1U << ((__FLAG__) & RCC_FLAG_MASK))
    -
    +Go to the documentation of this file.
    1/**
    +
    2**************************************************************************
    +
    3* @file stm32f4xx_matlab_rcc.h
    +
    4* @brief Заголовочный файл Ð´Ð»Ñ ÑимулÑтора клока.
    +
    5**************************************************************************
    +
    6@details
    +
    7Данный файл Ñодержит объÑÐ²Ð»ÐµÐ½Ð¸Ñ Ð²ÑÑкого Ð´Ð»Ñ ÑимулÑции клока STM32F407xx.
    +
    8**************************************************************************/
    +
    9#ifndef _MATLAB_RCC_H_
    +
    10#define _MATLAB_RCC_H_
    +
    11
    +
    12#include "mcu_wrapper_conf.h"
    +
    13
    +
    14/**
    +
    15 * @addtogroup RCC_SIMULATOR RCC Simulator
    +
    16 * @ingroup MAIN_SIMULATOR
    +
    17 * @brief СимулÑтор Ð´Ð»Ñ RCC и чаÑов таймера
    +
    18 * @details Определ¤ет параметры Ñ‚Ð°ÐºÑ‚Ð¸Ñ€Ð¾Ð²Ð°Ð½Ð¸Ñ ÐœÐš.
    +
    19 Содержит дефайны дл¤ Ñкипа беÑконечных циклов ожидающих выÑтавление флагов
    +
    20 * @{
    +
    21 */
    +
    22
    +
    23
    +
    24//#define SYSLCK_Value ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)
    +
    25//#define AHB_Prescaler ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)
    +
    26//#define AHB_Prescaler ((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)
    +
    27
    +
    28#define HCLK_Value (double)72000000;
    +
    29#define ABP1_Value (double)72000000;
    +
    30#define ABP1_TIMS_Value (double)72000000;
    +
    31#define ABP2_Value (double)72000000;
    +
    32#define ABP2_TIMS_Value (double)72000000;
    33
    -
    -
    34#define _RCC_CLEAR_FLAG(__FLAG__) \
    -
    35if(((__FLAG__) >> 5U) == 1U) RCC->CR &= ~(1U << ((__FLAG__) & RCC_FLAG_MASK)); \
    -
    36else if(((__FLAG__) >> 5U) == 2U) RCC->BDCR &= ~(1U << ((__FLAG__) & RCC_FLAG_MASK)); \
    -
    37else if(((__FLAG__) >> 5U) == 3U) RCC->CSR &= ~(1U << ((__FLAG__) & RCC_FLAG_MASK)); \
    -
    38else RCC->CIR &= ~(1U << ((__FLAG__) & RCC_FLAG_MASK))
    +
    34/* Эти дефайны добавлены в код stm32f4xx_hal_rcc.c, чтобы не попаÑÑ‚ÑŒ в беÑконечный цикл */
    +
    35/* Мб перенеÑти в MCU_Periph_Simulation(), но чет не хочетÑÑ Ð½Ð°Ð³Ñ€ÑƒÐ¶Ð°Ñ‚ÑŒ ÑимулÑцию Ñтой херней */
    +
    +
    36#define _RCC_SET_FLAG(__FLAG__) \
    +
    37if(((__FLAG__) >> 5U) == 1U) RCC->CR |= (1U << ((__FLAG__) & RCC_FLAG_MASK)); \
    +
    38else if(((__FLAG__) >> 5U) == 2U) RCC->BDCR |= (1U << ((__FLAG__) & RCC_FLAG_MASK)); \
    +
    39else if(((__FLAG__) >> 5U) == 3U) RCC->CSR |= (1U << ((__FLAG__) & RCC_FLAG_MASK)); \
    +
    40else RCC->CIR |= (1U << ((__FLAG__) & RCC_FLAG_MASK))
    -
    39
    -
    -
    40#define Set_Flag_If_Its_Expected(_flag_, _condition_) \
    -
    41if(_condition_) _RCC_CLEAR_FLAG(_flag_)
    +
    41
    +
    +
    42#define _RCC_CLEAR_FLAG(__FLAG__) \
    +
    43if(((__FLAG__) >> 5U) == 1U) RCC->CR &= ~(1U << ((__FLAG__) & RCC_FLAG_MASK)); \
    +
    44else if(((__FLAG__) >> 5U) == 2U) RCC->BDCR &= ~(1U << ((__FLAG__) & RCC_FLAG_MASK)); \
    +
    45else if(((__FLAG__) >> 5U) == 3U) RCC->CSR &= ~(1U << ((__FLAG__) & RCC_FLAG_MASK)); \
    +
    46else RCC->CIR &= ~(1U << ((__FLAG__) & RCC_FLAG_MASK))
    -
    42
    -
    -
    43#define Clear_Flag_If_Its_Expected(_flag_, _condition_) \
    -
    44if(_condition_) _RCC_SET_FLAG(_flag_)
    +
    47
    +
    +
    48#define Set_Flag_If_Its_Expected(_flag_, _condition_) \
    +
    49if(_condition_) _RCC_CLEAR_FLAG(_flag_)
    -
    45
    -
    50#endif // _MATLAB_RCC_H_
    -
    mcu_wrapper_conf.h
    +
    50
    +
    +
    51#define Clear_Flag_If_Its_Expected(_flag_, _condition_) \
    +
    52if(_condition_) _RCC_SET_FLAG(_flag_)
    +
    +
    53
    +
    54/** RCC_SIMULATOR
    +
    55 * @}
    +
    56 */
    +
    57
    +
    58#endif // _MATLAB_RCC_H_
    +
    mcu_wrapper_conf.h
    Заголовочный файл Ð´Ð»Ñ Ð¾Ð±Ð¾Ð»Ð¾Ñ‡ÐºÐ¸ МК.
    diff --git a/DOCS/html/stm32f4xx__matlab__tim_8c.html b/DOCS/html/stm32f4xx__matlab__tim_8c.html index b16bed0..3258d85 100644 --- a/DOCS/html/stm32f4xx__matlab__tim_8c.html +++ b/DOCS/html/stm32f4xx__matlab__tim_8c.html @@ -5,7 +5,7 @@ -STM MATLAB Simulator: F:/Work/Projects/MATLAB/matlab_stm_emulate/MCU_STM32F4xx_Matlab/Drivers/STM32F4xx_SIMULINK/stm32f4xx_matlab_tim.c File Reference +STM MATLAB Simulator: F:/Work/Projects/MATLAB/matlab_stm_emulate/MCU_STM32F4xx_Matlab/STM32F4xx_SIMULINK/stm32f4xx_matlab_tim.c File Reference @@ -14,6 +14,7 @@ + @@ -71,7 +72,7 @@ $(function() {
    @@ -81,68 +82,86 @@ $(function() {
    stm32f4xx_matlab_tim.c File Reference
    + +

    ИÑходный код ÑимулÑтора таймеров. +More...

    #include "stm32f4xx_matlab_tim.h"
    + Include dependency graph for stm32f4xx_matlab_tim.c:
    -
    + +

    Go to the source code of this file.

    +
    - + + - + + - + + - + + - + + - + + - + + - + + - + + - + + - - + + + + + @@ -168,7 +187,8 @@ Functions - + +

    Functions

    void TIM_Simulation (TIM_TypeDef *TIMx, struct TIM_Sim *TIMS)
    void TIM_Simulation (TIM_TypeDef *TIMx, struct TIM_Sim *TIMS)
     Ð¡Ð¸Ð¼ÑƒÐ»ÑÑ†Ð¸Ñ Ñ‚Ð°Ð¹Ð¼ÐµÑ€Ð° на один такт ÑимулÑции.
     
    void TIMx_Count (TIM_TypeDef *TIMx, struct TIM_Sim *TIMS)
    void TIMx_Count (TIM_TypeDef *TIMx, struct TIM_Sim *TIMS)
     Ð¡Ð¸Ð¼ÑƒÐ»ÑÑ†Ð¸Ñ Ñчетчика таймера на один такт ÑимулÑции.
     
    void Overflow_Check (TIM_TypeDef *TIMx, struct TIM_Sim *TIMS)
    void Overflow_Check (TIM_TypeDef *TIMx, struct TIM_Sim *TIMS)
     ÐŸÑ€Ð¾Ð²ÐµÑ€ÐºÐ° на переполнение и Ð´Ð°Ð»ÑŒÐ½ÐµÐ¹ÑˆÐ°Ñ ÐµÐ³Ð¾ обработка.
     
    void Channels_Simulation (TIM_TypeDef *TIMx, struct TIM_Sim *TIMS)
    void Channels_Simulation (TIM_TypeDef *TIMx, struct TIM_Sim *TIMS)
     Ð¡Ð¸Ð¼ÑƒÐ»ÑÑ†Ð¸Ñ ÐºÐ°Ð½Ð°Ð»Ð¾Ð² таймера.
     
    void CC_PWM_Ch1_Simulation (TIM_TypeDef *TIMx, struct TIM_Sim *TIMS)
    void CC_PWM_Ch1_Simulation (TIM_TypeDef *TIMx, struct TIM_Sim *TIMS)
     Ð’ыбор режима первого канала и его ÑимулÑциÑ.
     
    void CC_PWM_Ch2_Simulation (TIM_TypeDef *TIMx, struct TIM_Sim *TIMS)
    void CC_PWM_Ch2_Simulation (TIM_TypeDef *TIMx, struct TIM_Sim *TIMS)
     Ð’ыбор режима второго канала и его ÑимулÑциÑ.
     
    void CC_PWM_Ch3_Simulation (TIM_TypeDef *TIMx, struct TIM_Sim *TIMS)
    void CC_PWM_Ch3_Simulation (TIM_TypeDef *TIMx, struct TIM_Sim *TIMS)
     Ð’ыбор режима третьего канала и его ÑимулÑциÑ.
     
    void CC_PWM_Ch4_Simulation (TIM_TypeDef *TIMx, struct TIM_Sim *TIMS)
    void CC_PWM_Ch4_Simulation (TIM_TypeDef *TIMx, struct TIM_Sim *TIMS)
     Ð’ыбор режима четвертого канала и его ÑимулÑциÑ.
     
    void Write_OC_to_GPIO (TIM_TypeDef *TIMx, struct TIM_Sim *TIMS)
    void Write_OC_to_GPIO (TIM_TypeDef *TIMx, struct TIM_Sim *TIMS)
     Ð—апиÑÑŒ каналов таймера в порты GPIO.
     
    void Write_OC_to_TRGO (TIM_TypeDef *TIMx, struct TIM_Sim *TIMS)
    void Write_OC_to_TRGO (TIM_TypeDef *TIMx, struct TIM_Sim *TIMS)
     Ð—апиÑÑŒ каналов таймера в глабальную Ñтруктуру Ñ TRIGGER OUTPUT.
     
    void Slave_Mode_Check_Source (TIM_TypeDef *TIMx, struct TIM_Sim *TIMS)
     
    void Slave_Mode_Check_Source (TIM_TypeDef *TIMx)
     ÐžÐ¿Ñ€ÐµÐ´ÐµÐ»ÐµÐ½Ð¸Ðµ иÑточника Ð´Ð»Ñ Ð·Ð°Ð¿ÑƒÑка таймера в SLAVE MODE.
     
    void Simulate_TIMs (void)
     Ð¡Ð¸Ð¼ÑƒÐ»ÑÑ†Ð¸Ñ Ð²Ñ‹Ð±Ñ€Ð°Ð½Ð½Ñ‹Ñ… таймеров.
     
    void TIM_SIM_DEINIT (void)
     Ð”еинициализирование выбранных таймеров.
     
    void TIM1_UP_TIM10_IRQHandler (void)
     
     
    void TIM8_TRG_COM_TIM14_IRQHandler (void)
     
    void call_IRQHandller (TIM_TypeDef *TIMx)
    void call_IRQHandller (TIM_TypeDef *TIMx)
     Ð’ызов Ð¿Ñ€ÐµÑ€Ñ‹Ð²Ð°Ð½Ð¸Ñ Ñ‚Ð°Ð¹Ð¼ÐµÑ€Ð° TIMx.
     

    @@ -177,7 +197,12 @@ Variables

     Ñтруктура Ð´Ð»Ñ ÑвÑзи и Ñинхронизации таймеров
     
    -

    Function Documentation

    +

    Detailed Description

    +

    ИÑходный код ÑимулÑтора таймеров.

    +

    Данный файл Ñодержит функции Ð´Ð»Ñ ÑимулÑции таймеров STM32F407xx.

    + +

    Definition in file stm32f4xx_matlab_tim.c.

    +

    Function Documentation

    ◆ TIM1_UP_TIM10_IRQHandler()

    @@ -193,6 +218,8 @@ Variables
    +

    Definition at line 623 of file stm32f4xx_matlab_tim.c.

    +
    @@ -210,6 +237,8 @@ Variables
    +

    Definition at line 626 of file stm32f4xx_matlab_tim.c.

    +
    @@ -227,6 +256,8 @@ Variables
    +

    Definition at line 629 of file stm32f4xx_matlab_tim.c.

    +
    @@ -244,6 +275,8 @@ Variables
    +

    Definition at line 632 of file stm32f4xx_matlab_tim.c.

    +
    @@ -261,6 +294,8 @@ Variables
    +

    Definition at line 635 of file stm32f4xx_matlab_tim.c.

    +
    @@ -278,6 +313,8 @@ Variables
    +

    Definition at line 638 of file stm32f4xx_matlab_tim.c.

    +
    @@ -295,6 +332,8 @@ Variables
    +

    Definition at line 641 of file stm32f4xx_matlab_tim.c.

    +
    @@ -312,6 +351,8 @@ Variables
    +

    Definition at line 644 of file stm32f4xx_matlab_tim.c.

    +
    @@ -329,6 +370,8 @@ Variables
    +

    Definition at line 647 of file stm32f4xx_matlab_tim.c.

    +
    @@ -346,6 +389,8 @@ Variables
    +

    Definition at line 650 of file stm32f4xx_matlab_tim.c.

    +
    @@ -363,6 +408,8 @@ Variables
    +

    Definition at line 653 of file stm32f4xx_matlab_tim.c.

    +
    @@ -380,6 +427,8 @@ Variables
    +

    Definition at line 656 of file stm32f4xx_matlab_tim.c.

    +

    Variable Documentation

    @@ -397,6 +446,8 @@ Variables

    Ñтруктура Ð´Ð»Ñ ÑвÑзи и Ñинхронизации таймеров

    +

    Definition at line 13 of file stm32f4xx_matlab_tim.c.

    + diff --git a/DOCS/html/stm32f4xx__matlab__tim_8c__incl.map b/DOCS/html/stm32f4xx__matlab__tim_8c__incl.map index f3e1452..e54116b 100644 --- a/DOCS/html/stm32f4xx__matlab__tim_8c__incl.map +++ b/DOCS/html/stm32f4xx__matlab__tim_8c__incl.map @@ -1,26 +1,26 @@ - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/DOCS/html/stm32f4xx__matlab__tim_8c__incl.md5 b/DOCS/html/stm32f4xx__matlab__tim_8c__incl.md5 index 0ab8e18..d76a455 100644 --- a/DOCS/html/stm32f4xx__matlab__tim_8c__incl.md5 +++ b/DOCS/html/stm32f4xx__matlab__tim_8c__incl.md5 @@ -1 +1 @@ -f5d644ade931f341b1fb542234fb5e65 \ No newline at end of file +13e22a8267b7f1c5410b1912c2aece15 \ No newline at end of file diff --git a/DOCS/html/stm32f4xx__matlab__tim_8c__incl.png b/DOCS/html/stm32f4xx__matlab__tim_8c__incl.png index 8a2bf24961cf72d49db7289e83b10f24fc59d1ac..08824ce408a6d3e7242eed107905ec5a4f46dafc 100644 GIT binary patch literal 28973 zcmd42WmuHm-!@7phzJNMJ)lTPOM{e3NF$wsFm!iFi*yMR(l;#)!q6Rq)F9H03^2gZ zNY`H6|L1x3-tRu%_w$Ai!@6@EL{;xH6^8)^% zR}*Ma?MVED#i?VNCYQZDfrZsFt4Kn2SA$I2zfPw6vGiyCB!RD5WWi)D9h@mvk(yt& z*`%F%@7{NNjhUE`FUN~IzZ$tCnXYKg#Oty)*qjynmV+0SK8$+F%a7`}xJ&%M{KUl)4iZ3<(Ge3zN-GsK0$NeeMKq7WebrGClZ-%kGwz zl9HmA437kFN`(|iPS%eqi*TSWCJkJaUQe#R+^rc^X4|~-aeGA4%RgzLe&DN^w+*`PqD%6F@BZEpKXN#)3fD|A0j{q{(IZ7<8f zZPiBgn`KMx03}z_K7txOrE?Nrkv`(g7$R>kCB>@nUYhvD`5&Q!4xJ6H_ zF4)eS{-5JzYL>pFEfvll z+*nWXESP~i-!EpofSZ$EjVq!4=jTVGVj6v+roxSbG9Fh6)zYRbi_aFbEFp>P`ciph zEKYHFEbjgG`N-!M!mG`NCgybGYSZ-eFqt41wCvM)%HU?BBB5f&MaiZFC~{t!ArOvtfp4+t8vU{0kg4h zVNl7vecS89+hleAcf&Z8#LKvDQx-X0@APcPuQQ%eAt@9RDf>)aJMLc-HbyY09c*_n z(9<8Oghxt6kdP6_!3)aifz`twFmeK;lTZR9<@~mBepDSgB|G(=M-=~*Jq5ln(K^Gl42+x)70qdKdZ!RTFocZBQK_u zWC;ojy+NF0#0rWR{d(O@3fW?#Cn1B?k5$DH6`Ig$1RDq*%$Y#@+}< z;?DA5Y(m`U5GmaeA&v{Lti-ltfIuLJLt6zKqlKZ6h_FXiNO*Mp1)f3@yDqIeJAJg` zd+C1-vdJ3%jCd-wqFacmCPck)lclE>DfdeBtcUwvT{Rr2C*A zvwd!#dycLirn zCa_p)5zYzf#U_4f6|Msc{5vhgZBXJOF5uy|rHgOa_TT-~ocw7Y8RwtO8xu#=FhVr% z)7x*h;!DoUTlfVnlc_IzmAlAQCvz1e&7k-H2~&D{>6!l}L`Nye|BXVo$K#bg&}U-? z;sU<*AWjv+6$nNpYx&OSq@*^J8zVqQX5jgsbRAwFM}4+BQ&Taew0U6Xs4brooT(qq zGho&{>`@AR7K{2QQ5>P0T#$McE(`rdk$jKskE+>k)^}12 zN?O-uB$y}B;oTyQh(D9THJvNyA8fTH1;4!6|5mfDG#d0qMtlAB&W%kzXo)5-2^$l4 zdn`S*ekU)9GLmZ9+)}Hrm(bncQciRy8;q3X($#J!qVbMjDYV@7zu^m#krZ8E4t0;xf z;}_V^v_0gWPDX7le-C*>5@7)4g;U+|Oq_m|Ul{#ao~_oH6Vak9m8T(ZKsDvr)}sx5 z=)g^cj6=ono9EBL*{XjHLszOcEP5Mu;yG zAoF`dRsN(Ns?J3dQ8%Sp46XZ z-CSBsWy>-)pRG({?Tu3VkvcP|J+0EQb(!J@pG}bFK@NPSoGdP;r+=IWisgR_%KzJE z{|_w&$$w(te=5=cpT1~pjQfN{dYkelpzD&nd4mQs!0F^?9YK;u-PF){Byb5oe$Y+H zKDrBM!vB_h_)pv3)f2dOF-bz0EcUy|NZIgsO8Wv8SQy_O@c4|*$dCUB53_v5I#q@(6BAqAkvEW%PmrIY8$7+clpEXd zr+wI4Z@XjjEfc+38%PI=0bQ_H?td?Ef@-h60Yk)*kjLRUB4_QpZ;-y0^h*UVOh|}} zEWlNm{;{aNV#M+Ib7#11;|`98+i;acFhy#Z?0dCkdY;#`jt~Kp^vFM(OyKjkJpm~n z%YZX=O1;p7?lb$ar{Q5^9Jl{<9d|k&Zr8PV@$)#aF~!DW=BsfpBfVNISW7}+$I(u= z;{#+!B@$!~?U@qUyazZ@`f0}P?My0b7skEMfMdjK^K1(;jru{SoWjD!cwyjsk&R)X zaZ_%R#LvjcNN&8SsYHgojOFjeV4ot3@+e=iFi#`rGQ6y+L_Un0$t5GtZfH0=6+50n z1|+v#t{R8ZcN*QCYiD{chlgT-H6G9<)ZfDxEmX1CnQJf(ecIWd$ku1d1OB4tmmkdr z&F%jqll~vQvWU|B_>)91Ewz{EUpriFI-d9iL?m~7G5GClv(MM-rc4Ps)-f^KQ~_>x)k)3)A^4u3CJEs6UyQG4h& zddAK@FDF2bd%i-8f3DDBn4Ix^qSVf8#lT1rMuJMNL4tJ;gp#$Wc34}+!9yNnf-+z@f}wWXkL3(;D@(-@n&E1rryRa+saej z^|Lct1hU0weP90hUs{FelBwZ(nuxOnc$1b?o_~{eKHXWPUVmJ|ijCd#d|19t zzI)d9S+H5*kqO_wB*i(iOYe3*%A%CiB84SYyyGLmxsNBpi%Lsavy!HK9LxmN3K z-Tdx6my5F)Al1y((7bTC77y6bQea&@qlrTo1)XyNMRMK2v4vdTzI_4iSDqy+5)(L>M6+DLCE zl3veGT{FriC)zEcfffQi*Jpc>>sgq`ENPqXk9fDFfu*G-b>rSA^f0-!OxgDe$LHJ> zi!YEE9-LXCDUlWF#wy7MhVaGkYWRhh*YJLAe)qREV|GE**p60H>zEFFbbPhy?P7mi z_csfKT>FlY2ekAaR%?rEjF@3jqqG#Oba>=gK7#+c-!`3VdC*1YF)w1rzABVi&HODq zb`YmjuuC0p){5Q?c5=RI&;CQmVI$M5Ek#y0SjZ+?#ZLfXo9@+q5x^Ac)*fL8_o%R` zqFR?EC8o?GAunRfVDs($Cmet7RA}$sUYthfZ&D7yl;b)K2@H2ES~*7BHoP9MEJ2H` zrMK;feY`vZBw7 z%zB0_WThwb%w}F~xa{phB&UTUg4mNs4E3bE9Bpj${9rSr7T%dS3GWFkg_t9oOZ2yP zSD!bvOfCjEH90s~S#{z)XdRumE=81jV6hxTyP!JWbcv0fG!vht(8HUBo zMSX45-zspPXmEt>QpO&t2hBE-y1x+~;3OYXB#G1er(2rdc!bJdZm|9i6jR1w;`HZ_ z>EjFM$n>YO@;qf0uf&-LkL>XCCy__lUGB zm4d7mq{z{$Dajk;nZu6GO9I)3JPWC{k1fu!HI(R#s=#o- z#R-surk^Xa8gmt!vKLxh<_9_YFJ0CY27A1P^}ONzDwRh9%&kOO6*i|4s|0&d?(@=9mXlC;C4=vI?2)~K+7$!fdEqA+s)jY6(&d%{x zi{|hFr?nIp?4k5ovC(TXEzv$h2?C@wFU~yPsR#bxcF|{uW+KJ!Yo{d>5A(k@GqEMA z7Wr1@@nMPyB;y4lG$b<9$UCIAXWQ zwDh}GT>O0uBz+*iY|_XMUNL|6N~Pq=Xlnm~&A_Sdnt{1YPE*fBFhm7r2_8QRn6P-c zlwbUeGIt>AFrW!3gIXrLu$yvDNUVCB%eYrv z>2?EdM(#GPcX0pHLf^#NAFmukBQS;4T$wKiWXA_`YQ{cLq!0sJ42Eb`#kcs;!;hvZ zD&7ms`q84rF&24mxWp1- zTu6o3;m=OIFoBxhN3A5KIWA-*?>yWQ0O7%9l5MG$!d zQv(R41kb&CL^OHINTzjFqH!;us-y_#jYN7%kyaDOmS;cXG&qA!WVCvTx(qPF5B`RqyB zpip5`4_PQgg|TLSQ>3@x7ZPznd3ECiO~ducDIDh{U~YuxfTvn5?3NBdX}7l!Pm$)9 z(c&zvfvT4rc(a3s-h5Q($B4JN9O?$oz~-3hlDTI3p-EKUk?3NscJa|ag{V^7 zI_9c|XCz__Fe7jDXUHiG%-||GI6`ML4acZTXz}N-lc!@W+_d~ig?WzS{7NKCU9F)? zsuQC!&4tJ0FH3tN_`+@W8IMw_W$PWxtF7_xUW$ChlUV7XEp8n*lii&k2m-VTj;j-O zDDJ}PXN{j#GRaMc0U+pS5ps}Dc7ISFSKMCr*w7!_v4tA9V=6q7GDwJSLwQQDggj$K zZF4Zsv|=%KpNYn$-gSVC^E>KhHzF#pJO4E(ma{{rgiAQg9?V-YV7YnOX8UwFy!JmN?{-1bzt#gMG1vR^53lGV$8!)^Y47Lc6`)8>;+vI}oZ z!6#~f-=~Uhg5{rmr!>Nuz=%}CyLdZgtf}V>7nyIEgVOxE_nzT48#tDCd15!{8-056 zL51U+R@%XkB0ZcNCyOd2VdnVtq{_$i2Cy-$d-UW*qKupbdD~ix(*<9scBp193^_M9 ze|)%P%e7l@j#bI%cL<;>Aeo?a7aivrJ3n~3H1O(y;ji;}H&jigmO?OT#v|60V{J@2 zSE0ToehPi3f)yct{5yo(GY79XQ%I6=Mp_X@XkB|8!{xn>%+F;+A_dlR$LFF^)Eo$O zqs6oXNKZ5IR{n_{b#uZr&jkLulbyb9*%}>tPF8lLZh|=(?ez&8hqlr*3nEl)6GEWH z^)hZVEZRRp>b-YG*0Qc2mgole!kDZaJ_fv@{f6JgX|%a$W?WPK%@|vyN?}=u)chp+0Ali4;CPQQ#KeK@c^fro;di!v6?Z z2H%}O_o8Akuev>rrnu#duU+r#I-~M~Gk0fkcaSeX`Ti-f=B^?W5@rEC+Rziyy!7}sow$SFy6UGNcl#47|-%Nd4eXAPjxjG*d z)K`n9>~p!gHTbP5tXMhPi#gTR!hB}ZhnEbf=~f1NT(+kxyY4H1Jcd=F40HVHNj>Z4 z>Plm)Wt1jI2H(>mCF3)M8l?ET?=SbfPkinPUJmE43gi z^lMy5x1sm8X7=|y+Ii;z4ozKa|6#F{QW<`p*YXCeDpwiA$%CgNlq>d6(%cBqa?h=F zD;GR^&m5L)^m^Y&<+VO{3a>nl@>nj7?I1$V3OWB<%M0{=iT<2^brVpeS_5ll7hCWG+oe%K}Mz8f2y`MmmqyZlo^^k{+?YK+DMCW%dW_!~E~h^G0PaL;ckStI01X#Lth`Pu|i|@4B@% z;(LklAl^V(j&-ul$V^I|<-?o4HTD+s7KiBbI>UUTjuzHW21d?bXq625U2G@w{^@fw zeA*ikp8W;gX-N>@`MoC}hXeGBmF8NQT)fEdJ7lvI?uxKdyD~a!%(o(g#qRUwAx#oD zi|zP^sPkQeiV}!LtImC~x-lO7=xQ3LChym7s1oJ~8RolP6@qp%3B1M>XA65>A6L*L zW&~_``DUdr@rC{Wx}C*5)^``rl^}vWA17nvYBEsb$=7#(L7dP;xsQMKKh-R6-l|h9EH5hM%^6y zdNbn{v^C3HwfG9Nys-(gB04Ih+Ov2oiO_8h4z^`)$I|$u&Z#FT%(OzKKWmlH@QAqi z=c~3>6uRaubswZU94CLRGZe(%-wvU?_HN$iYFI{iC{hLK8N8VQG{#V<3yY(`UbseQ zD~Y?Js?$ff(aU@IPKekU^N3Z7x7>~T-+%4X`aDaFDESUiS&M z%H%x+)9*1rI5_xyGHbtpCiebjFy8cFFbpoPf& zK+kq6#->;`-#%lIM7ljzGW~##t!=UYZ!N(3Nyq^8*@?~(nTe@wZd339gbhZ>s63L} z&B$=eer$a$#fUke*xgC7v+0Uqkq;427ww8>E4RV3;O*JRStH|htTPDGc1h%2@D4WQ zU8piyZQ16@$D%vF#u0McxG!Do-ncfuG7UP(sV2FD6`+(}&)HIfeFxhP|y}B=dd>#(i^1AbLAzuJDLm=u2u(Bgbylj>OFJV zo-&X6l~NkHqK?{m+duM7d@)lxp}829>L-iaV{u~1JvNl+i$)LD*EIET-V@3E$X%1N z%tR!_1qhiChzf^p-{p7MqUL5U4-HQrXxun8dv@|VEO|F?L zcAosIc%dKQ9mrVp*^RKxe}XFO(l)BBowtfTlwEkjPjIC1mfcIM-M`EGl18gHs=7&k z>rZ$Rex+lOO8C*C`>c57#eBO>p#O(C^GZL*FS}eK6MSJ(3|I;E2_0d1tMMA0;>5rd zD`Qc+e0^Sb>O~VPBSHH|#=t9{95C?0&>W%d;n?cgLxZl6ec#eb1tr}3z-nAU>F56k zCyQhkC5$VGBx+6E5bK>yavqyrK<_#u)6BQ%gvbTAI~Z5(DXsK(al3yEK1grCsh$>B zUM+0@=%EGpM|JE?X@D4$@vPBDd6bc=ztxECtZu?OP{`S-y37+sR;gZVi5FomlwaEG zg=vw^^5yMwRTGPk?#vN=qh5Fftpjkh?XaJanr3b;*)Qh?5Md<6-z`&m-soqTiF$CUjR{s5h|F7_ozAxuNV^uo1^H%4dnbK<)LNq4wWY6SF=8ZQ z^uf}L5@usG=1cAKm}&Ftc{|h{iY!IOt%233Y%%18cl$U+^_=eS-E^Z3X&RB=evTNu zl!LCGoeYp_DYMi1y#`?9)asA`Ni~

    @(~w^8F!*}TXK%Fjkbb+u8ylC6!k2b*u96w@KydjWIX z!+^zJTwz;4yw{TKgDg6ow8|PqPVHm6!nbWL4`_|DaI(;pVU@ZNBWyOvgiRw%*6g_x z%NzX)I%D|Dpk4R6%6HX-tjsCL1cX;zZGR@4viC(Tu(J4(8|`PND)^JZ`wr|W$J7B{ zmrbx$uPXKmL+8?~ofUp@H~FY^Y%KyDCoR{y8C4_iT3$1q#CkJC}EGA|`IM z3=$*gNwCKNC*qse%WF=ke*|#F;u4%FkWMLWP_%48PZ-kTr}N=bf;VQvzA6Ib47M3w zzZ#L`G^YTOWR=Xp9&JQrVQ<@y%a@aM0HQG4VUK)^G(Boyj_<+Nn6R!R@=-

    !gq?e z6^mg3M_^qdT+$Z7p(*L`OdOv;vpqOgfXx^i_o~T7@`!V+`OpfD8*2)a8?b5W&m>c& zE5=NaMcJ+8HIll+Zwq*Hmj4>ZU>^x`T_bYdFxxQ@HJPx1g}~myngQ5Zk`c`g_Z%&& zdzm6XoIp~fcD9HvJ|`HB}j0o#A=M2QPuB3ZMjT`e6&FrOL|LzmM!bs6P1Zn zKN5OaZ#g4o@O#|sbv~M7V$anky@BE_Mqq({_yyhU) z*iB<$;uR-HIe#E>X+0hzYppbCCHM>>e+4KJYIX)~n}N2w`q=JiB)NDLHu#%%fDX*$QXhEws+f8?wz0k;Gh!0dr!5RrdCwf>yv#q#GX z08}>T_sk>O8|FFOHK+Cy)GgpfUkOfe;Ot8uZI&;0z=)|5NmctCIcl=^HvOBO5nDc` zbBs&JpY;wVzXj2sKR2dlr~HO69Cg{@9!Z0>S(;D(rq4{AXOlT{>^Zw2Htk{Pu8911 zNTs^kfL&`38)8OI;UWDUk*y#2ErEwKo=F}FP;6mJBc5$?5m(y{Xxrn%?FPWXgx*r& zS3|BTE=+p?A{IwAGxNs1{4+WH*YP^(U6AAI0N=1GE`&&c*pztX-?Oa8gjv=z@MT-x zSnLm?R+x(d$YD&M4y@y{VB9V6K@|24`67HnbwP=eBLfuQROGL7EtzZgW zG5$I~CSyBv?kje#%fhDm0rfZWF9E0SHT!F4Vi(hJ=$EUFhn5np>8fV0?sdm+dbc;> z1JCU!Z$gAKy1%8Q+IfJ+A{X$qxkBWVUFH#zqYV`pgigrf0*b7dWhURg8i{2`C6J2W zb@Q`?PM!d&EitN0Cj;%1-0`~AM26XMex)y+ay9Tc)t)0-F?`^jqzJLmCcH?D!(DP} zpD*Ii(4#77P>0kHQ zsTUs9Fx{v~U+v=vO>tp2M)sF6QS|yY$t3+Cufhla83S|KS7K#o zO!az*En>#oH-@?-w>HIuXS>4r^!yh^kY=FE#1F06NA3ozJPAHD@$yq~(nhmr2SFrZ z)a2y((s6drlKq`y_=X~E<`%XmfI&d(A%cc`EQ62q8=)wAFX&s9^M`=(qi@Y}S61uY zX8)N5&&5@rNd$15cQbdVRXfawvNK`S(<)iuROeK=FuC`{8 zGAIjhno&7i?scXip@C?1yo;NDy7ylHhH*2#5f93CsWIDX^zrm`V^UPA{rvsrdrEal z_blhSd*)|&=hht+MVHDVQB!nXghe9{917MQT~#^-K0{OtcajtjF{3Je_=-gjE2j+# zqW5vVQN9Z_qJ8SG+f&5KYD*J%z<>g8uT|rdwzQeMg8s~+L*<=Q8-aoFff!g0{6uOR zB-N;fH5#HVe9^$F*P~_m6MVMI@q?!*M{#?^){fSNF>vV|(-{Z&blrrYx?=ghASu#$ zN%nuH(#E}-ERxVxKNBZHR<|b>-tfXE7o$P1fq1P8xdv!y!ix1`GKHW{l;m8)3qU4+ zhNx438fvX8$;5f9UJ@A?5^DJmNB)dzL6I2HC=hKhqKce9jS{AFu3wCG` z!}fr#U@;DZ$>(jxKo!JMX~Ak-&8()ZKf}c%dwf)-Qs&zmY&m?&?qQFSc@IncpZ95X z75Buf8;{~%wROZoCVHdw$?K*Zx?49iANoT^rB&%dc~Ll$4N-;7!Y)qb_|e+cy|?zy(0Uv)LVe6T3L>9bP}7rJcGB`LVM$W+yI1bOc}PUEREF5C4>6 z8Is>oG#_BmN0=g-2$HQ zq-4bl?DmYJ&l$QQdv8Wy9ccn5F5Hfoj=n~8h2#BgvwA#mSF{C7D*_aI9mP>G>ts{JH zak9mr7BV{P*?wZE&djJ^a~Drg=qIMNqrsZc&X}Sk(C7Mp&{`UV%+NUB?;0)3(7c!% zc&|F+s$u;W$XkoE%O)4M9iQ$QGjjZ~CKMw0_Mek|H6Od)fJuJm z-&hYR-eR}0y#4*7Ma!gzxL?!xRw|+rQ4a*{6Ss`|2V&26UqE{cGndOY zlL@tN=RdArSKHKjXP%9h-wYC5=LD9equ{~q6?4K(h2wq(+d|fwJlkA2w7s7G#Xa^c z&;}F+z${f3Vpsl^9NQ4d3k|!U%4cuq;>QLP!FWkq^Is@+%Ib4*v3D3Bz;3i) zzH7mp=DvZQ;|sV_70YFr*ftu7Q#|!6+FovXGWxj9F8_|(M`EEa*4Wo?Tc()85ynwJ z_DWVV~O#8TIcxnxla13I+M$k4*q9?vZarA9lwc)DFyjh1I&>_b2OP|I#Y3{ zppfKv;(o#vc2MuFuB2graQ3!o@=SlcL-VQXpY$@#=$*e&ZLaNdfKEWzf=u>(wA<`f z8j_xcwK!UzH1jKSpRV!Hmets$Uv=R>@`-36Z%iXl;z*yxa_Q_g37VbN2-D%%3!>6N ze)SUGEZ6Rr@8j|(r(oIXze(v`say{X&GawvFq$TJQO8w&wV$WV%EjBoZD#|gwer5|G7 zj9EAx)$tnn&uyn6iA+V@5x0Sl1|Igw=pEH+NTR1M@hr@X$L-lX&i>6-sh)$;wV7m1 z*>kIt5!rXP{kiQa1Eg;|0}u=qGZPn>RqVW>1^UBSOt~8q1lc?AdfOe;SM%n+^sfmu zVd}D(DxJ_&;;}Kmlt;=_>qzA<6oKfQ!_umFUd3WQ5qWL zMmDr^%xQ)nRJ=r7hgU6NZI+i<=7ET_b&L{utK_^xr8gkO`j16{7@z3;%hv6?qh%68 zeDmj3&dPN=n+J{FhBBJ(Vf7E9E$U~ZUA%AUc%XzX%$2Z&hl2+FP-*}OK1|Z_tLEhD zC~pKQ_NvUvYOQkI_~T7yyoWr?n|cp(AGHN7LM>zkx!KqwC$eiE$+yFKf7mGitV-$lLs|4QNYe z38=`IL=VQ)FBhc-tcOqW+L>J#IdB5I7CnAC$HylvyOtlm56GQozJ{zKujWkP9}b_m zwK)Pok(lTQn(+NDohX=HOY4iRZ&Y%(qi0Y-gl$;j%ZS^Cb#4MZ$>8m~ zkV1Va9h_i==`!c#;F4qnx-S{C-B$-iY2Eq4OKMAufpHp>uk3`xkX+F{LXS`TrO4L- z&r>I25Q?&AbPc22y0(3=efmDHBLIn!#wRPSO|T=pP)?yyA*!Qg`T<1^1^Pr~wO30& zZRYz@_Xl*6&i++uxZ)GA98BNbqTD3|Y=gqQeD~XdJTje_mow`p(Z(%Y+9}0$H&4&I z+a3jB;y+AOL)-8jCS4G|>SUc$;=BYl}vslXJ~H-?N6SV z>~ULe;`8}5X9S> zCDoIt`YKj5&95-*BJ%QMF(kK^3C)MS%$?8k#O{hbwd%aBqYNmcSLzF-(ROR1W(XDq zJr4DZbt?61uAGnzP&@AF*jB!gQ?Tn3@52pD?oF#N9peFQK>3Y`)fqF~S4hGMb^XoB zAH;}3rX}^{FU97Q4?c~lM{vW=#x2szXZC}kaP)+}d#RYaHGGl3uc5>EJ4^0M(9$IgXv+3aWBISOUiLi zyFd2Vh{j*1x)b00R|*)v1_ZGY>pz=nbhA0%svh2J68KYREA{Ty3tjPYogn~-nO@WqEI2NybDzrTz5gS*qA8zCl$WkRdE~Q zpLE@>>>|9{^+Aa+hq}?J{{1_u;)2TXSQ8~{=w2Q1;|!z3g;z)OXQ<_sMiDN>0io&^ zH7i*T5UU>7R5&7~s6?GGWf`|-K|&3#GI5b;VxL=LCLC&yf5;&+L5n@p86#=P~2LSvaEc3)}f&(w|&2bh)TSSP>ttm~lN7aHh{%Jq(!$G!~IL6&XsBmtEo z7hJVHP+bv!JbZ;Dr8}Pk$&6$$fm=lq!R$b3A<+yRB{coFe~h^cz3WJ_Lm-SLlB^MV z^*gE#x@FC6Zv-?@z^l|0=;P|s0nx^bvT5g6(Az2pMn<3-c|D4D7l9T$!aCjJ&n0e%QQp0uoxC!BZwjk6~MDbGa=wIz=$mZd)35)IE!d7B`I1 z=_G-9x`2B9-HptVa4+`5ed#iP4XdgE2kK_mL#>$mB1w9#?<2)VCwmQovT!h|ZwWZC zX(R=y$_4^-%G8K#Lb~$MafU;&^_=5}36_*Iu;T|FoMo`1*C9y)Q(;9-mh5b6vo0cc zXmIDOFwrkRUR8o6;wcO<{fqkoxF{|iR61$zJqt0I7kH*G>)axEe&t;AVx`#S)UEt8 z^Q2cW4I5v`o1Lm(!{uMl&JZq{r}GX_U(WowE-90;gtgZQ-19=kKR^@GXLUh_u`6K{ zZR0k=ZNS}o?(x7=!qMVGspf%NR!Ec1@vKAJ&AL6Mm+gvo1A+hvP9dxB*ypAy8Q`Rz ziavaxyjE>ICeesCKgHxrf4;K$gVJkfeKL0#;)U>p7xONj;qVX`1&0=aa8;3Up!ye1sO8~J2q%>w-eUV+UiOpjb zSI4ulN@)UBR-*;!eFFtbY1hc+5tP=2PSpuFF@MUx9`TCV@%lf4vA}&gjojGSNe;dR zNxSB}oTds7_xuzUz?QL$5g@HG!8OlJUTSaU-m(% zjodvwv-(^^A^n~|Fb4wrh7eW8y(D*m)4Y0-;?*wps!6U)0{_4f$SRs-kZFBigB{V*~MC#3#iop@2 zjyy|ls}z-&@Rg~bue%bpc*B9Xip%|!VGlM| zbqomASAT+3BE8;k227Yt1h5obn~(%JkLi}9BUA@1v~3OYo6AGq)*Yzw8g9R6+e}nx zcfnlDAVK!qwtELSfC-&O={JYrjAl4$=OI*bPN&Wh)&{j4zzF|tAonVJH`s|?+e00Q zZA#1=BL+9HaD3Q|@W655=eJT)b04bHH~$g!_S6GC04AluymU_^_{$8NF<_Z|v@-Adyw#OP#y$2>E0 zKRE;{2SRdcI< zX5W;Ovn2nz;l_31#G;);*|(B{Q{k%opz`&@Pis4Nmz!Kvr}h=cer@G=)Ku)Z01aUA zEptb>+mljv<_MG;qV%gI*03uCYh&}rlR;4aY*9r9_nQUG)0@Gu8ZuBHjx^|6 z+S{-qCrZETjee~>T4TpT*bbjEcgDQUqv^DBa^e&?)m6b?#OEiBy9Z7oh2vPftl_e+ zS_HJdFt9InJBKBABOclwwu^zPKMX#OD!EXi=c;+FkFR}!4)jRd-?8S{_6PlfMlMy+ zeQYWhj2+qAx40Vv2mUj->hFWjnPS@EPoDd8q}jC*iDW(pN>qQq$R&ylfYTDsRB5pv zOJieW4-tv(y_zzX>aVqf3etoo)pw`Ww=X3tm{&LccIz>z8hZV3uGt9*m)F)r4SteT z_T%uM+LJBa9nQ9&A|KpLHNNrp_MoNH^xgHpJQDtT=N;ZezTW+Q%@UY3%o=ToAHmzv zV)xxJxO0%p@(qs2kwDHRQ(SkM?3pai=Yr;mm$9q(GV|dAF|4i=GTQNTok&3MK z)@OBi3t7I4H$#nXXaiJO`c6K_wbfla=E(PX`mUcoisI(+;OVZ@2Ti-X4II5#L>Uhw zp@+(GZw*#0E#El|jpW_oyd%!E_txl4TAEo5bG*-KGLy;Q zC4=Q&U;4G;2YIHa?nIgNvYaDT3zpaa$QzG6S3d1A^%`(vg4QN}<>uVn=l}3tpE}Z@ z#v!Ee-G}>oaNJ!acd{@QRrfHHsUg$T&`8I;iqd1zau$sP>mQn^iPgVPlFvSAwdt`@ zO7rf$UW#(&&w&4=ed3wyjUi`k4dom?zS}U8JvnYKBEAQd| z)z??XMfFAP(lH>QbW2EgH;8~rcMc#R-7z!>0xCHoEkiSONwVZD_^F47if<2t&LPM+^Qg=+(B&e!L z@l$BV93qLtm3DsM=bG)Adtj7>a){U^e5o zAzqW?F_=ES6GSaU?Wl21g}Tp{hvG1{IN&YFHsc`g95>SKR5r3Td*@8qI0<2Kc*Fja zB`a^(09TtQcxK^&WG|9xHKT$`5G#3VeNJ0dXrbR32XT3kL~EWpcC5x%o&|0;4D!qK zt(dHxFU07qzD_l6RzYp3th%nu1n_p2$*gExwy5~?m0xv?JB;baTDD(kGW%rJexrCi zKouL5czI_dkLQ#m*w$ zfC7HMmurCd6CD)p*D04Xm2+C%G6@-4Hk9poaM26OdPyl}f1a1^BQ6qIo+q;m$@H5F z?(AM8ajtH3c7~t6$(^LNL_auwhU@77T4XTIEt9d&l_jIo;STB=Hxx)Va&#~PGjP}a zdJ$Jigd~0mV(cV1o~fVcfe{#I80)?wz3v)-d4TJDKMsF7w4zs_Io|g(px7LC6hw63 zOijt&yxvn7BISbhcT{~q{4tBQ5+}ZN!oyDnoOAzTE$%}h(P|+J= z_%K{(IF;xsn59+I3(pmGktuJzMKpg}K02x+IXN*igqQBGNGI69p0V}KSXa0Q6BuDT zLGMPpm+iaeLNJa!-dqf)Ey#_sCSjEM21)mmw4+|Z&rI|=-lthw0vzWrr6&3pNdb0# zP=|ImeLfHl68&PyIh?9q9tX^Qs7&1~i`5?7@-aCi=xu_(mi%U#mpiso^td_fvCWFD z_4mB0aLtThF1C(`^YK+7K0pkp-+f6iu@iDVIWsN_=cy4Da*oGTzn>RV z=PbFT(np(M0t(E@9Bmu zq;Ig&ttiIptZN*=PkGJmLe+7nmq&=99MTNDC0bVBN0N2eG=&So>=iDEVPkSg6=nh& zleVpLmt}P3KmMA`em>G)1&hMK_>`e7$Etkg%FhI+dfs*&{Pa^KYiC6#YeF49mLY5t z=z40XKms^{O!AqrdjcCCHpvP+1Js}uy|(Qiz>=P_qEi$qxR2hrEXRCiYj#Y~ks(gL zmDsjN%#8Hpv};5AZ2(ST>;76tfUa5TQRv^+fO>BKP;8|j>>!$|>~L%F3?WT7sep`$ z4esF|57Ev(o%VuiebXu*hZ_*{7GQKm9AU76%(R(TGC*2!ERD$rn60iF_9&;iCliNA zroCrvZTa+DdB~ba%P=HgcjIL8aK-lXoyCo-g(xmMKr5qPWrO-(&M{eD5K*FO;--q5 zk9?^lCEf{VjH%6jYU*pbn+C_k06a1-#Yl!q@E<+zMn!R28rHu&ob&c^LqsU~W->9W zK@t8%pd+_1+%GhuN?m#8>a^)t&euco^Aj0HwD?>**fs8E!X$8l)YxNrAg8V=y{jzE zF|Rz_W)&7toqy-P6c{-nNQmNhGp}l@vt}X8_VbNXxz!16aEfoYiE81*d+=99Z1Xc!lM|A}{Us6~Z@mRi?XV^d0%NtJeh^7|$ z_DIfj)uGt5T`lzjhUc-|o_b~N91pa7&J4xA#n%YQWBM3BO7H2pALB!VHBh|kmahp| z@h`kHcdb1&RnbW5Qfai$i8c<-D@4wFt%9!VbhMml`zHbyY#2}=Eg-MpO6X;&atUeWJ`kJc$Jni!^+|&=y3-MR zzYZbRV>3i;SZQgaknTMm4)sB=Yi>+4t3$rEm{=WNP-R75e_z>{gvUcO37uBgi7#o0 zJ&QO^7Bd+Q#RoYImk7zJ(w@(#ae0&canAKdgOXXRSmEM*D6&V9|9D1tnt5QHmHL(^ z6FXO5X-#hQ*^l7T0G=_Nl;;~2LBLm}-GAEN_qcCO>brR8huTmqk^b{qpE;T))7^0( zyd)l3#fC+FX)GT(D!Sem<{GtH;y-5L8c3~DC`C-iY1%w*-CaBZDT=IKq)zo5e)kOg zUF_pXdBlTRAu@vlNN7*NX`Q&n=T8?XOPR1Gf|3d80BWeT4>Ii^(r}8nY8zggR_BC z-x`I0b*l>=R08?3N^uB;x{?T&TD8~(CLY=(1s0Dj`p^sgE`*Nj9h^J(QDd}mHOFunzo!7NDtg?LmBLnwfJQ+; zv`&>?yHl`9X$^$_j7*|(q5_zhS~ zVt7+)>`8gpjCKEIkGtO_bsy4cq;8n|yIq&ls?6yyR?haCW(?o3=@imqnla|Mhx?rlH2L~lqipW` zJ>a&x!$f|^^yyVMyNh^R>ym@y)A++`e+993Gg0n;P#>vNwpgY>`YZR8m>605yQ-E?`*C}9(c^Hl4o#gKw_5FulMe{Z+u{LkYA4A@ zFWnr#`2l(NZoNgkovGKNN7b`;zpPc7_5^VP9^pd43bz<^qU{htM{eT0N*cV#sXeeC zpm>HZM&$Q}=7Ox}6`*_7)vj7CyNxe(KO47clRuHQnJ#;bTgX>ws#uPZ)5BR&@2C<< zxM?EpScWv;3S(=U(YrrxGBu^$w44$faoDa)Di_bJvcH$$y#SG z6>}#HzanO0^Lg_4;_SLz&1=jwBJt1)Q-N!!a;i*lJk-&&s4HM78$oaZVCAgNaj^$* zzmM3ud`Z8)EV=K~QNAlId-D7Bk%r2GlsY@Yod+L#N5~S3Prr=snkg87!)8+{yis)rfLT2r3)ZrwvaC;J4zr4ZpHWd(UG~dG$>_n%9cf+Cg<^Ej~+q0h}Ma)qm z{zV$yxmG1?`PUZ*9Li~q{L0jeZlm@4sJR66N7qT23x%0p1jl z=PUEkZC!K~xx4Vt+N?_Bm}6D&V0{6I7e~~_P^~!oI4!*H)UbqZQ_HXC##zts*%iorF{Sl@~JZMp230QvObXw`o%{^{|#U3Rh_c6jaOCbn^q~V zLfBrvOEh(*f?k z4aTx72jx}nKWTp^GF7AF3+datQK;czG(oIBNUi$W;-)ZN6_P$oL8c+=3|#a3&u2}7 zjnWO9JB^QwIKJx;=OiG}Rg3q+34=xFs{F%lA42LU!bo4gH6-5O84ea{0Ym+1diQ9s z3Od@=pURGk3`ph;)JH$X7YYKrv;bHc-Vchx%PcZ0U!%Oy>{UOV9~?PtM<V{L`V|3%K`eiC)1Kw&THRXq(Sxy7aFI^N?!#8k1ZO+&@@CJ} zjJ#S0n-#}rNQP_JnAeXbBiWwj&W~I8o7m)uelBGiDafymt{sByG_8!~&#i!h2MDF+ z8I)?~F-Ol=6`S7U*@H}a8#w{U-QXWs-{H^dmX!!beBCgOo9>+@x#*04HDV!qAG5B)5FDtL``%uQ)uqUpMlE)nTa@DESq+Qp)P= z8e_#=KCd>-9$&b^{rDPWlBB*X=h9{^Ovy&f8ugOF04&N&4oqbJ9ktMp!ft{n%xH*j z$CB^I+A6EEt8&ZJ&&z+z6B{UIiL?RiT)``pY}y>lk%!{#!zMk5bY>Yyl03L>4g8cs zEW?0xT>fp3Cn!X!YeY7VmE-43+jj5W`lcAGVTUHO?=yXE)$xr#`be|~GJ%J^N}V6H z%y65Y2a16U(R?bXf3yJp*(m4wzP75LROBOYFEWk@)SNi+195c>)GmD5YfLi~cJ*IuKfH6fi;#_bHx#sTlL-V*&mI}*zO z%~Vk(mRk`D^+f9I?(Xfmn?OQEn{v)ShDHbSy|TW*}(L3{Mz}-Nk+w1RsNugQomtPErStn+?lRTBqv6GWY2Dk zW#oO{D772IrG5wnrFFlxuvxxY z|K-L+&Fn>-7PkV~MelI`;}*LlQ7+4`YuKx+iKe@{ zfD^lbYJ4o{vf2!6^f%rY&J!iR>)vv&K%PeSejYAytC;%|3H{g%q_b!yhkRksgr4>7RSpiVRLDScCc)sLufG zsAg0cm&gajVkPq*k9=i4-Gc;Oh1L9C8lJe=Xxhzz2P|^!MzFd)H0S~iTgqtE&1hv3;IFz zDt2M9{$T3k)~OP2V0S#SIe(x1`rOWQ_p8X2^OhdlCP~~D+1b6Tz%KHQj#~QNu*I2` zrI|>t!n3z&Ayx&fnssOoaZL}~3ul8x+P}TX{`q&4&NdlsinF3WHFV~PntfbheC}$& z^c&j`7wAW3$lM|dRxHgf^#7TYy|f~49u)a`F0%+;_$x0obQW{LoOuN&Tc9oO5+*%= zU_EiQc}9V@?lVOKcRQj(6K1r5o$3S1>Lr{M2^zC!dKY#?elje#9dqM@>_im3Enb}M zZHVx&C0cYj;Im1ZbF!;(yNY@W?>I^`A5A4`=IU}x!CwJfRSlURv-#^rjF?m>LFY@4WeKkPgxAgjUYsvUbmg2 zd`^}RRbmeRhSiz>B{Sa_Uh#S5Wkuje=9p_0*8AK2Z*SdK@@;iH;EpmTdqvC{Bibl) zklj^SVZ`05atZ%kU~}iFuCE|mMryltwa3~2MsfM-suxLq67kCU-Hl>zi`1KWn^yZDt=o~cl_{zH; zG9~LJ0t0md17T4dQlU#H=EaBTj4WfPq6fMV%ylK%+n`z>gAJhK*iePJptQBMvFiOCUQxb58~!Cf!@&uH|MI@L?KM1FxR*?fQO~aMjy5v5Bkf zyDqw2+^herKzPo3+1Q7pg(ChZpclwb-( zq2@T#b}XJ|BCtW1dG*Kg(ahRjn-=v9ulVjHN;k`z0n_Won)Q%i-=7RNO zr!wo!{;SE3ki728>!oY>X;35jn>2W9-lpU!)Q0hAtEa69+y%%2B;KfV&uBRl1_myz zZ>%NSt|Y*3-tVT#r2zHwE7Le6Z94GF7~gX?vA_d=cs_yzZ_!u%?T&0O95c)oY{>1i zu99f=wEw1`VCkS8Q0f=@2s8LyDQw|_rm08Oc7rDmHH_)#s?_ME3tZUX>HtHj3RWs7 z(vwFY)g6;QJ+QB>VtLAx9qlL8@H}JFJjs14j~&`R?wmBIM7w@^!;G+1zpya^N3P02 z<9qdmsj(~k7zap=g&%(~4fr@fD>JI+2@ zU4KJY2~&!05TnczZg){exY4?Mcu2N^nCKIIjn|AV*5r)d0{}#3Wy^n8oDwawN^jtG z#5a<86(-Gv*fn!^w8JIGVHEQ%n|d{uCHSY9T(VV5Ph%>PpkvTHD%;I)4U-A*A-cBQK^_TeZ$FuiSVH zT*X>bvmTxv8XFPyR?X!^+TZ{DyJE5^TNQGL5QO;*g1%gX+4TsP&BCaKcDf^VGZ=Xr zyf;fG_vx{)D0=Un5nvqh!z6{L!m94=rP60JmvJu69XUN-w>$OCfQe*`0v&!|4IRih z;jSI*RQvPCC&3!EIe1lCNxh=Z?WSBBuktu3>rIB`r`Ei!Xhw13jxm!ILsZ1s5f&!g ziqXi^x3xC6#W1LDb|4^K7W5WZ5BnJY8efNdR1S5S#A~+GEmbMD6yvb@XdQWH-t`(E z>}MM%eydua$hai#f@S*Kr@*tugI&MS_vGSHR2Ze`j4Fwtz^$1f z4)_;{k^@3ruH4q79YHw`1CTTT{5D3vtuC@;3_$wG;`qjWb4mb8xx&o)yG~zk?=Zb- zGbyq=_PQfXdnfJLV>MZhtzC3O_XafPfUcGiU;w&yFy7+I!(Ow z(eJfkUp$xw{ypD3d5S}u_`tg=waa>omwSgMuaIR6n-(i=n`OevWKid>uIlqJ8Oa)6VH1TG98VZzm^Kz(22?iqlH+(SXA0aqIj`K#2Hh1+G)=x5cyQm#MJ`TG{!+ru$EF>t^r(|`_7P>41K8PD zaH*=mkWCnIp6gcH56MscHL!3R!JP54%8$*54nw<|l`(L=_p5Q)SHVG3SFYa3qyyO9 zqQ^AV%Y|YE!X+-2u7>{L^`m5ZEi#r;+_z&G!eTbbf1)DjQ_y!*CbKm=m&mx&&4T`- zZ7@z4XlO2kIHi1gyzu7RlS<6G_5dg)=(FRM(DkK3Q4i#=59 z{PTuMZRP5pUMQWi!$^$T76}AA7M>+0V~ZGMfa{(n=!sJRKjFC~zAV|(9!j@CPZqO& zagapF<}kPh=5g}?^^Z-gd{n`F&qoB1515S`&M(E_#p@v2r~utpl|BPxN`yAzI`e?Dx2`jHLIWB>7dKx`e$E>Y9Ho0q zkCRbM?ne-X4NDFH9#B+1IrI*rN5P=F&c z05(_{6_QYS75XOv$GeTBpc&A0>H|Lw4Vj8}prV%BOe|^!zmx z;0l{jf@b4?p+a+Y)Uf|80-o3y*W`7DN9R21S^k;Sx?M7PghV zF5A<~lwK?o=P-E^6Y8GwON%|6HrSkBW<|*JqoGM-+$cZ?o5K~78zd;RNWfdXZ(df9 zQ=`Fgl#Rq8KOrn@ruEo8|3JpX{>(WcjG+r8wwCJk1Pr3Wgnk-H9tvQm;eOPD>}M;{>W8z_=I+dL7+ zNi?}IloCP#2}9E?!bTaa@5DPsGpn;I#7g7kR?_jG*iyhtzO+X4k5I-cBZQg7_S2t0 zE!mpYwceUD1=e;ELa{G7C-!I8xI=LfKnj^aImpITWEp2mHT?yK zTK;R!*b@Ko^KKQi9^>NrX{vxl?`x zbTu{5r>p~=i%Q~AaxZLG*Z?rWN=G{Bzo2^Lu|p9ftqll4nW`ZV1uNIc=TzxNhYDT0rIb+MRf%;VZ0vKhf9Y z4o|Qb@Cx@3oa7UJrO2F*vJuZdd_-3Vw30;DBk<=KLJ+#F6yv(7Oat;+YM?w3lX1ySZu=sH(ktrOjaTs=kPu^gB=#Zbfuf z?~x9kdL`EF$LAw&2gcJZ%fj68k%`59xw{5wit47^{(r^wo*BN-oRYAh4ipk^1UNEi zFpGFJXG8TJ3cO2r6=W{b3)}$PQ*|xvQwTzt27|qNddt9S)jm56+o8gm)UQ!j9j}js z?Vzuox4FfDR&e<6<*38stV-QgHapPz zoU=MDICXPFXNK*J(?+e(+qy~>G6WHFNZk7b7Y$;0sgcRxPgwGi@?wG6G2} zjMUv==seWC>zB_{Bh|7u8H3rqo#kEmP(x?~Ip#f4@~xBCp*+iII*&;uvdP&&)n;j4 ztLtA+J(d%$UOZ-_ti6UvsZvbdqq!v8nxhemDIEL6BIF8NQ|N807vMrgvt zI$^M7wCzw}$#UmzveuGT2kZX=l`~IJ7iEWJAKTqLFftI+J6=uwqG^wEb9uYKz4g1hhukUTD+j5B?+gedxX%t z7QCJn`j?Yhx=xbC@(rd-(@yVb7MswE9 zaYc~Fkujyr&osLd%xD5)?@l^u(N2~i%p1(Mf8Mr@cPc~Pj+Kq4z=>%d2>5#zz{dk_ za;3EO$`^{mOl4;MS7ued#8-NI=5KGRZ~cSOs#I_vwqXxw3{AzayNu_c*h6D%-3L&#?dB^(8*=G9QTXt}UoA~N zpyNnB<4Kfq@kLMm?up`q$E^oprOnmPb_}qn(5>c4xE}$umOw-4c<k{& z80}0QI9bP%DQ!|&fWdm}sGF*c_ak4l4!l@gLg9pE@+3F}AERV)sIzr47FCiF*J*kq zgMUaEXy>j@61B<}E-_a%Ovo~x{eX6706u)(uFx>IMX}0NSk?KF64&+Fvl1%2TX`CX z0*~aEKy%K@UvdUY!QY?)4SK?WcN5Vf7q6XEwe6aPuchXyqLKTFjRDn>2wI>{*z8eH zthZJK9~A$)zB1KEI+&WvCi9xy=xrqz9`;9X!7WcsPh~(O)c#lBxj#;H@yYXn^j4=7e^*FR&N)xG&h$W=|n9lC8cXN ztu8b`l_*RdY`M4w|84T?@`p{2t(uaVt?lPo2pMIB|JHcK1DQTZ3Xj3+Qk8W)^?W5p zn)2$i!%rjNk!zO?UtEUN5K)RkZ&^ZJvSqdVSRzggQ1`Xz|0vWS-TZ!~4D1p1c8@2u z)oV#^rruULow_|)bcsL!e75M16!FiFvOwD>c$Vh{Hm-dQ481yNv-lj@vqv|irfESs zE(x$TVI<{slw}FttN!Z>WWU!=!jp{yWB(j*{NA9XJ%_5(C><1_-e>v$k zREZ$;KT0%=zQW82IQfP~;ikun2YF9&RHf(1mx#}HrwsH)9=H*QZCe*2ur=M4ErP$1 zR%en6!pX#X240P`Z9LnTw{f&K+ifqlZ_JV7cWm0iu4sCGX7oH0V(;p9@deUTXXRXG z_KI;gkZ>VI6z*ZAbpAw9$ph(IZf?<*`HjvfJbIBi)Lq_dW$SIIg-c<~Kr55^fS7*R zLfRLycV%FYQTVE-Eb(0a)|cfvQK#Sp!}b#x`s7wgV30?XV9$VF*L!rvJgbr3^|g#f zyTT!z!y>OGbks-ql?Sw_S$yL3@b-vorUzVeE-?!iaX?s53=`1~Gdm<%snf$4zp}2> zdiqxoR_41e1MD+21Bc&o>>2tO-TjupB+)072zW6XMtr*D^!wlpl{jhJ_2h@V)k=Ow ze?DW~^6%=;=d-p#4#nex@Z$cnqW-g<{#N%Zxai^Y6+#9^#`5aj;$VeCb|~>PrGlsb z>t!^Q5yzX~!vYH;&gPs~BF-Vqk0$dY&Mfl74m-AXcX#(`UB@Ug_HhF4%q|*%FUH)t zcrWn#LT4(#$z`vaqs2%~VRvtN&BEFL|1Ltn1iPAduaC?50&x1?J*Sz>+^thq-aQ*~ zuSHYEU!ae+OQ3J=-el|j9n^g`?{3;o_4Mr?)_+(2f4pcE{v*#X#RNS0BP#|x{}AiB Mx~^KC>WkO^2byZGmH+?% literal 29386 zcmce-WmuGL7d8qapi%-#$Mc|ow1AY93MdWIT|*-sLx)HYAl;yJceli##LzHwjDW(> z(zP#q-*4}4fBQT3v43s&0Sx!t_jRqcuC>l}o@>IC72gp&pn8CTfk7Z6EvbTmafcHF z19R>k4tNE9Mf?l=z%h|~Cy8-$`~9V@APxiL9}F4E*J|$R=migNJ=eCI{b>s(D?Dk; z*WYBd+X|Omjo)`-$PAbG)y4X~yM6Ii9b8Crn8EWB*r9bhXFfx;xS_^m|8m5UoFWm~>TqJwfK zALGIaSXs>G?`uiP2UUN=g3I8tGt+CwqqEj(yo-==tjlgP2L9*2e#T8=*LE^OR)v1Y zn^1rH*Q@0WVWn@po`;1>LsV87V)8yoNt&*{*Npk=WD;@^0b%&SQ)=6MLb5YbItI!^ z!;n%14!qvyQ|2*~v(Ho|bE)DRrS(O>Y_cR;7r|e$=d_7CJ(1y%WM+tb6(-kXITRaK zFu&{Z^>M6}WVURW+^0yi7{%FhsxsYw43l1S>p$#u;fp_i&d#5xvRgIrQmzbAIt`iB zw0zQIvddz4z`dy72HyB){Oc3DpIB^A{kVC^89xDyjmPz9Id$2!30-&|Tm>zfsA|Eu z_3VVM&y$0JflE0;?h|b4kKwOdPn(r)vF`hG)J0i~Ot9&{%QK;|sTq8;5gPh}p{`N> zpS394!avEOmHf|3kC0I+o8yh7#4)SS98>-|aDAtC*j)8#luunqIE=*g zv6LhuJ-=~7>x9JC8xF`bi--Gr9YO6IkVqv~w}-p#xEJA}6R|paOrbGE1uArEy?O!% z^D2-ZP<=kS)P&7UR=1aqELl*#7DPCQaOsXPag2)g?ZJ&8=khfg7CjL$nys}m4q;#r zqVxIlp5K1)aygb!ju2m%jMyWfIUJnBr#!%ck2MR~@^thc8c(n=Fw_-*IOBv#zWxyw z`n~5%Im3Tl2fR!|xyfq%&l%j~=T1kQQkB=i&$(gd2AE3pnlQ7W&!kGfsAl!N3W8d! zVC1BMqzWAG0Fope?%8gupXXe(Dkuf_9b3i3t0m9&-$lf(KUaIZc+M5apS6*p1&DE|?)f)-Jy$&QD} z1$Bb6w@8-MSD%7@g`EkhXADOmBm;~881AhVuA7HJM3YMx(HV6mWk|s~mYmQ};BJA1 z4f*FzEv#>^(<;(U%(*73OA1q`gTBTOE9grxkl+v?5?UWHVn9UQ2Yf;aqRAaH`ts7d^oM@9{SY4x!(!Il^A*vB_ffU1c%n}OOpvKKkxXWZb2LWjp7@RJpDsLB| zEW9z{O?E$r8J%%?#GY7x^{_#I9S_N?c zl6ZOcz5WcG^pcS(?~O+-cm2K=HRjO_Ko#51i>*qFP z95SmWbV2}}6Zzz{hl$SetQO!NeJb)M+E(Wt#4*>P97b$c}1f-GB!f zy2VvH4Rm4!DhbuCH+$3HPk;+940bLOEQu*?*Va5w&mP8{e*rtdgUlQ`ZLvX%&SUiP z&YH9OXSBHc2PTu6rdagONku2kOY(sCppKTt!TtzEaqJLyR>k-0wR`yAuP7?MXt zl=4RA4I@dY=jpsGw?=6b2UBmNX3+gyn!odFDT$ zK=FWv-|KHXHE5V>SC92@w-p>HRO^)FWkz->WE8KH>RHhh0I^)J0ZL z(&u_~+a-)6&-biSsb+*{%DWZ+a%0Nu9GdkzUb3ULa(M>PF_n;q#KcA6rf|)tyzLAC^hr{s!2dr$xc{@d z|JO%<%gX;3?Dzlw8v!zve#9|&nzp*voZcWDe7#L|W=^(aIAwA&!Nfxx1D|^2hQaXu zk@K-bV}C|z@4etfx@(DLKMaw7%-@ROFn=P=3zbFzSR+lj>QzbT-VYO0JRH#+AJODh ztf6%LQc)3oWZcKbF!l`WKmO~M!<_k^t!wp<$(@m-K{{2F)p@slOzjc=J6!q0O*179ZU z=t;tNsbIFl9X$2Du(g$-Ck$ha;O;P0k>!`(Jtk3#HD*oRJ%6tyA&+s~Oob2`%@Z|J z6JC1%-ao#mM3E3%NrJ_*qO1cyu>TX`=!*OXzz-`}$m54lJBLtg?$tRQEn+tj5D5&} zbp==T$F)mjptoR%ly8xUP?N@(rnv19LSOKdp%`3TT=Z6V#=E1Q955*@v_I7M%i>q3 zVdnM9Eh*W8825pE^Nxe_jkEJ%m>0UL50lGlW}u5u>Ql${QH98U4=K?du$G@opuNB# z6h=Q^M`TdDQ81M1)P>74k%He;3SNLh_&@a;|L^e@(`;;hbD)l{is?ISqgU^R8x(n! zHaJO29*n-^RC#Y6?De~3aihiVwCzpbgGtIdT+5~`{k+W*vjql*HI;~niJ&(`3ZlvY z_a>8&v&gmErLEl1ZMV&zu#GarRv=cUduzLXM!42a_x30cijrN-Ja*P^N9DoOL2cT1 z>ab5Zr;7-M<(4zBXxphgzidX@(Hc$IWyTOSo9O7gEvZR9JakQX1VCRd(u@75WT4UHpIbUbk}4{Nbzjq`5>@`2?T8sURq{=A-m;b@d%mS^iQ!sQvEWgE^R>Ln zT927w%<_exrmRL}$hwvpS(-FHz%AEQz7=#uYf_TAE+Cu6Moy}$DcVTcr92s+wS^D4 zPe=T))n@sNR4m%P=t}TPMqHl^b7(N`ybrXO%1s2IUpt)ETc>}^3AZ+}8b_YxD2Ye4 zh{RQ6v)LqaqvqL(9&yaR%6~hF+Za~1l$Q~0V3OpsBaV4<8^8Y+6P*>pIT%zz|BGqC zi~pO(^IOxKhj(WtOEhadk2WhMideI1N%{BWk;eYL^?ulalVuit3tz2B{#?~HAE~_- zp&JgS4Gf)NX5{QzUS8Jj97p>C11#vGmptDOyRTBnIY`d2ps&NBJbQ!rNO8L61;3UZPOsGlC5;+{ zEF}$%H!GS#GFQxMoYczlhk-aDirSoJ8DSR3>^%CI7yY|>VBmDlVaijSYfEUfKAv)1 z1on76eQLpaI+1!n>!q;h@m`u>D#hWT5H^x_gATvfxX!f+k_CgKpjqkWvVAFmFpnL7Vz zff|IT;I>j*I%yG=&YOF0q>_~cioGC?sbT@8bF8W#ik~XD6d8@>cSkH%R?D+>jcNS) z?J{nsVrQ1h{W*I*$HlFo8Rk>sN@s6s`^{9F;V1#P$&l`fu>3*_>3p*Nhza~lxAk)B z=}vA7VS{a5I0z)Q+d}`8SB!kasXlu8OvRAi(9k260M;-swRL&)x-*)_jVBaKT#*r7 zhT>>|wC%5$Ex8b%s+~(j=5DfU%(4xCNAse41f3e@m8fXgbN>tAt zbRu9>DG+3T?*4eMl3JiI(oD``Znzr;zzR6-VWpFmJQ@W0&B+; zR7L+wadR&`#2$XDFE8hoUDY9*x)RT}Ar2y{SFqTCU`xz5NkWFB&X-@1p*s! z@)v9lJ1-ytHz##b^DxzBT{K*Fs>vvF_i^+gZ{S=r>2bSkqCU&tJG=sS=<2Gwj!kyt zhI_*nOZQ{eYPN|I$_s$`N$<|zZ=J|k_uimrEfY3w&}`nRuN{7_747U+JXv1oa+Z*r zBEvvJ22#t?d>Kc#6^Txj#hXgHMTz_`xcmZ`m230pGZWv|DQ@eN~2D z&Us!v<88mwicNvR6zR0dTlA@|Ftv&uaVm$q(%yNdt%SE5Y8?@Dy9hpj2Ag?Ih?|NC zv*tJKnpuT(E!pwLeJ$}3n2I=eoNzX%L`E_yHPwWpj_Z7L`x=LqKkj_;DVse~kGp+8 z?;<%9HM~uJ?|2!)3U3$hbESeKgLUn9Ti4u@jHuc|#tFo4kUF^hIAl#C*!= zxV3n>RK{dJFeHzGtlm=>i55mfOcC0-MUMFUqWQHq_uQGDD@J2`PZ(EG3LELASyzo) zlYDAn%beAMi+T#xwV?7MdOiA~JSZR0RvhY^viSmJ+>QAN?D+ z(jekgp1ZxBA@d&P1(TfR>g*P!#|t>Ar!0F$hV&e4O4T3AHp>}@B5J3HdJ^?7C7p~(C*e! zym69GlSs&m!u}>Fm?AF%dncTlR-fZ|t`gNhnRrYWm{YJc^sO#^NDX#u(82%QoESwQ zTC+V`i7NWLXk(CEHiO|XcC7rg{r#O8_M$#+yhF{ifwVM_kqllh9gfFtB29?-UtF`Z z!%8Ob^)_bi8s}hwU|LlQU_et7)l~-damNY)i>zfx=Z1evK)p3bg5muiwSENder`M$ zTv^7t-BHY0*fy8qD90WC##&+HtOvrGm0;)JdvbcDinBSkD|odCY3}L?UfFS$Hyv{O`{!!1_eMQzuYkEAeumZ5K$k$;Juz~DadXi4QPQPSF-!=pV)llnWx~!K8 zOH?0zDIzJ2`&5gMVI9L6_QHc(GDv7w6f-L@<{qY-+d-+Pv$p{zbd@#|)m5q@T1nODdIIaiZO`^C1bl$+oNRAPmEBz=^K@ znvt$5SQAjud$Qb-b3V`}x-IT{D#2>Z96~GCgwWZF%ZhZw9hsl*ivbb5(G|r~3|5eP z4I((U*5a~lhy9yJxZt5`&305JgmpUG!2Uk0mNEp|fK=*^vJi>2@ittY52@mrG>Pbr zDj>eKun(}X)LExa*2|ejB#dx56%z$3jK-4AzryV_Vl}Smj>;p6rOb+Oj_CfF`AMJF zO(aqhgzshu2|49>HjJM3t{w^=F=(k&hb*pyP*r@TO}ZhsFfX38BM{D%l{r3Vq@aD> zNu4xQWhm~~xe#k5wz8)m8OV|avdAYTV07!n2U)cPoO(YILY+hVw&{y})0y{#%Vog| zn3g-$@Iv^<8iS&|+Jr6yskx8$e4~B=^f0)z+#*2Wl<_*EyTFs=IH(f!;VuXP5<*7K zSj|2iafj#d1_A?H2RBgmf@oFqTuP6yYPfwZ;6D~P+*FbKYO}ZbTIfWmG#XoP9S-F_ z#za<403aM}oCYM3Io62}oc$B;E1*CMYy%(t$6WFDskx!-A;t(G|2@lSu>{ zw6+{@FZo85zLF4u>h5a|!}2np4g5D~YVX!9ATYiku9xl6x-ABAr8p-F%Qbvhc@oKA zSML+J`#bOh52|~CV+x$p$q~1RU7EBv(Zaj`p4_0|{6wc9Li9-#T}UIqQq(d@$T2ew zF;8%exM1~fDg4v^7T@cVis&n94i+rw@*{zVs1^#YJ}ZQCxbXZO$XQb&jrYrAdE;gU zPBXYFyy8iy+$y23lfF`3LL^mSfJ)A)ziD(?xImbdevrl8v+M6P^q^nt30pkj?Q%lPx+T|=)p1EHtthX zkQi7MzpED~i|hkotn(klkRG@%oq}Q(n#5?Pu6N zC|W81+P1sWg;2zUxAV+`7&x6My2Lp(W;Lb-X@pIpjEnwmJATiyp^jnoPWs}wb&*4M zoC#=nA1q%H7ErW4fUqIrMGDLVI=|}cib+3F1!kzNIMMVF(BCY0O!t@!T zZX6r(3~AdQxR_LSdE2zo5xY2M<{yfRENK}$47gC|36sg#ozJpJ`jhsw1|1l$e;LJ` zzaXOOwu*K|DTR~cxd(Q47Bb^su~>7@(t-Bj7FJOOF{$tZ!W*e=eNp|R4|50Wp(TenYs5lIL4-kH|Zxwwa5_WpS~>czJ;^bCp0a>Xywh< zAg|hGwFo^xL0*Y-FVecntE7w5_s%VNSXFIY9Di#Whd5q0h@y7OOe`7r@_OrT$o zlMkJZihDg&izhX1%j4|W^-Cir$95Vw_M_aI@sFUIEx>9{Y}UOz}=QFT=d z*-{aN+%}~{Pa`1irT6ie3?ONCpF08?IUkA$dA$tZz3U6FL|LjS z7~}qv;JE(Q@4a8JJ*M-}sS&iR93-RXbr#-!&_xL1QpF9GAz)9}veRtCClQC^jEWQ> zJU%*7Z_Au++i_K|kbv)AU+fYIe+n)DTduX;!#clc!bT2!Wt=pj?v7&lK)7+oZ_(=k zqiY^E?K*MG&oMKc=F_<5}wJRfNT@RVDT$2YwS(?(8c=xfVTOrn_pC0U%vN14>=Jha|%ub!vT4d}l z)0pg)?`X6zqLVje>QkgTqqH~DjQapblTZL?aP8z{365pX^o2nGCoQD1I&U}Ue<^gn z3!vNfWM>#l26VJ!^|Vsdw+xDoLB;h*&{$SWg(>Q-bAxPj{x#a2cw??TV7x4AEY3y!-oUTh}`to(o) zaQDfEeNEo#vLuLIE$q!B95P(vYB1Np@=A4-2QA7AU|Q|Dm*VqxqFj^Jx0;9Wp?=pL z0e&7CyB&vZ<*w;LCM?JEP6O=x2-%)(aY6f$|1k@&BQ>dCnE9+<;X$yW{cJ6Zeb@7Y zwv~{h@6%0Y1Z??vX0^miWamxaKx7NqbmRtaq-QoyVijF$ zQ(we38S8|#N+HZs31?G?|NW|pW~`MG2Ah8i%5mLwsJZ|o%f&hn_uikOsPufP({Rm5 z&X~8G=3&h%i9s~(YdihC>2@Xw$p8E zaX@}(LU;B}q8>MQI6+D@Xi5L2q$(+~6v5JUUZUo-|JjiD9^U)S(MpYYgGIyi)&hvQE(l1ENREc0A0rASTDCvW24x||-yy8ybE z&-iMr(4Y~enKN#hNN%a2J@aq{tXcW@lBNv6TM&@t4fcJPqVx$gU5_@!!mUeQJz0$VR59{Ozb^R&9U~{-#BCd>z409RXyd!u8=KmA z)Ud7)C1f}GFtQR-l>eOW=j1O$u?rPgK>6Zc&7-b{XsfHnagl4Ac47j4Y-qlwSlh;4x?|oL3 zS5+8))OOG}&aRAQk|D;$UZN}zXPs9?cf|`eXm1H(51@0FsJFiOa(#X6&avqM2xRN` zkL2A_o6)ouy>!@JEB_HF$}yhzWsSp+2ClK4AL=$Z8e$>bZ|S&JT+eWUY3#7DJ~ z1?8%0ud6~W(i?Q9SqG(W1Mp7PH6VSoG!CK)g57X0S20r58aYocWf!Hf5EGNKjzX zS`!3>Xi7)F;o|%td4MW`9V24q2`LP;4QQJ9>J{ z9?}_E0l3$_n^iZ(EKUt!+mmM>_$n9OuoT@;e#`FV+j@V4NfFwZz-JaXjz`=Fu(c{j z3wq8yB5diASA@%xolD$ye8}g5-%pb0?WrUgNHD=lj3mdL99fOC?g48!>A<0>KQHe$ zvL{sH0VGTZ*v2G(Iqu^Z8zsVmhOORFN1A!%28My$xTpH8#uZe)e&60^k?d{=;R>Ll z+Y`Dy6>B*X3TxV?mv-O+Lr8H4PV3pg2(|^DvHEXBp=K$Rg3biyH9qP6!~O(2r8_bX zAvhBew`4MEVrol}B&+<$p_#>=9^YzML9Ae3RKJ7-h&{?Hl0<%O7tMbJsPaV1>RZzFKLLG8i03k zewwAjZrbQjM*qRl*Q)&r`biiICyV-8n|`y)>)f!5Z$4e9=u;jWty1;$hOsv(g^M6q z=u(jj?U_sIfoQeDU}rL3ItDuU@JlyNM3rYB`&RL!0yD!Iiz7?-2>PpyqgYOEo@cDp zO^Q&*rd^#X=;Nnmd3}?Gld#@3j*q|iUSK_=o`^nrOtEX~)pd87aLbb<(SN(_)z#JI zR&wHY8K;sLseR$wY!A5gQkgg+DU-gH+Tkrnfxxit%D%qa%F*3HSJd5Q8>m8iC?WK5brpzF>9kGP>=O@kUvo({U z6}B0}_3WA^t;l7_lLD)06{pBu8--fIL2ut?zDp{twaVAyWm3fwVRH8Y6ZedFirTxN zB?vp!Rax{$t-Z@H`fI$7QG&<~A=1-QN+nzbvzJaI6D+IBbhZL(egBQkz@dq@LDL`i zi!0oz^9dI2141o6iXQEm1?$}k4cIM6{Xj}?>`kFXPC;v2?*>b^+jhwQR^rdh?fd2T z6hi{&E2OvEu5|=_?_FA+o32|OO>JsVY`wb+ze#n}gGQ*^8fJTrX6{24ng(H5^GzQP zOgWoPf<;A-6B4GYriccqI{FTFXtH{x^L5a=v|Bz&9}@k@p7j$THWiTqC6C!&UFe99 zLH=NH37}d5^;Z@m{%n^26qEnEULYyWB2G_0R$5IeMM<-Tv!Q4Y3yGAhUifD~ll#vF z7;aNIwBn%DHFYa0ULd(9t>1m3mE!|i@}J~GkL4F3lL>kbWqP(&hUR;i2etJ^A9$H3 zGb(w>KK#)~U0voF87n4I^nq2?vj*XbbmYr3J8(KMk0gRVu|(T~1)gfxHu*!%D?eWP z$@^8F;N!aXhQ3Bxq=*L(Z}+*Jdp57k!F6iqL@4Bmd{PD#mf&nC@&2A9TaPQ!hX}vaY};+jaeT zGuG4Z&+j6%Mauvtb6nGDoH8VdaL(=aC95RjKJN8ktHhndO%%In=~_`$nETbwe<+9n zk0Wzvqx8GKj7L^!FDhd64(207bZX#D9g$OO+w;+2se%QL9?jR?e4oKOb z$qij7)dDBdJ$@KOh2waj5|Vl^SU~l~>04-*7`dAWY7*!iA<;k8mQCiamv82QS6k`& z^k7UW$CHA(ZZ2ehx)%evkGUcA&euYMDfGP;O%xl!?Hrd5fQ6%-tvavR@oon!|9#+%!~m9Mc0U8Pg0|!j#7j^*eYo+ zK)#(rMW1}00zP=M9#Np(ndGm!Fhe1LFi5R545HN(3ZAk$!-a?C)hgGP9nO$_{s9-X zJo|7V!3SY~r#q{}(@5ezc4uAFrth~7mC(X$eRO0B&Ig<+tLC~FU^0}BIbMoV{9lLm zaL4x8#91oukE-|viis6~K^Dq1JmOz|v&<5L4Sep3bc}pA4(bja5s zt&ICriUAe*q7ffCogRT(u$Q;S`@sgRX?kR5gSXu@`V7*X8uO)=7R~?L2%&`jC7QH*ryaj4B4w=+h4(_28^gAiGTU}8lW3ywv@9?iHgpDoY zy{mx6C306UO%{1m;_Z^aXCJg%dC2MgBfTcTCOBU~)68PaGnRLu`LR23svQUMb4OBg zsLilLV7KGGzkus4GeKyTO}QvPx`NF7WQ#AH`Ei~jWxb8U(CosKDl0=Q#h!na>-d&O zcaJUj=noVkTMr?#r(Rbk%L_$!D?>b@-8I=V84Sz7r3-y;#YPC zBAM8S0Qk^WzD%feW~DHgbe-QC3XFFCO1U9CFKEU?``+Nttko%BcNp6M9{PJq>{auI z|(q-xH;GL`iTFZX6GD%D-VBus2CBxpx(%M z7a!>w*C2omILES#ACBGo0i6+q^P^qtxTs;*k$aX`Y#?LHpZTNziS_jQHrtyG`35nn zUjnC9-N68#YDQe~qXqM-6bgIRKti5-mF~rT{lbT*hT75l%_DsKd1`dd1}#oB%!q=1PyM?~{z)?exX>m{J@A(z`VE zAEHF*+~i5sy}%^rD=$&od_lj2j@G6Wt~&)(^RnqR%&TwoZ+rTE-)lPF#j4s~jp&9} z)7f3z9cf1N;Db-(;fTn^Khomlm>XEr$48EyZI|;?aqshW#Zi^-$IJ3!ndE_UkB5cR zNu3v|^1gkHGhOFTb;V2AlrC1RG3Re_}i`Si{ohib#LO&k`7w8I?oHT_9 z=hXf#oQT#!Voto#t?1}pxw9-GtJ5_}OG4sy}kSAIIzm)0PfRq5CIvH2l zoFyz!D$)xtmac3|M3(m^meg`sap_`$Yxrap!s6Kwmz?Suj0|p4dMw z(3$r8-!w?BG)Jr{$K+VikXGhN69LW2c_J+G~ko zu_{z|cH`va@SOnS4q|r;b&rwbrr#K6Ij;WwDCMgec7Z#>+pWA|vWe97nV&cqmo1k+ zyNio!H%@IqRe!t$m~%&kgJB!WVc1B^%)apFj9es@~lO|cEE;E2#ci7m9W3I7y zQvSwkN+;`5FWtU*9LJk+vJ0Ck=e>3Yb=&WiG8&;-m#t2%1>QM20wMXLfM7Yj;3>Vv zAsD%po}3Q_s1)gx2}p7vzb+Xk70vI!Z5&gFC}>^~8i>tZKYvmFTYkC5T!dCID_y!| zG1117HccEgC|@^QmcV)QH(ilNH;qn>n@p=WUwU%Kf4L%p4`EgA0c^m8PNq_y!x8@{ z(QJLhWlOu$^u>bb8_Py+&gegfGQ0-%2o_nLO$j6Kt`+9TGlOFb`8)E%4rA3<93q)( z{l_r+G@p-IDf?1JKXPSSiHVZK2d4yza>ogk zo=Mgsf_DFT_WM@{FY4zGS&LQc8YpDM2yCtE+&S1T0gm?vj}luddwo(Fp6xbsk?94K z-EtG!0?Z;?g;w-t%CTwPW)bc-<=e@*4PQolpyW!Wi6g$k*n*qZh9d5z>& zcq+=f{Y|Z_eKey|yVF3hK=AUxX{hiCm}OJetuRbLA9+~V{ULv>nvXr`xS>C!?F%vi zd$F3#y32nr%*Q22AmezrRQS`vM3XREtqxY;erfYdyq%|gEh($YH5YB2oUd9(ns!741i$-P@;0mjm&J8Qc#>!wxoXVvUK>E| z{!olFkKuo=H!w7MOAa6MQQ9}8^3$XT^}Yc^^-!UKPRI5F`lP~@*#^!9(N@&)Y`qf8 z)lL4)kaficG;AD%dM6)<&v!tN;YCn#qpJ5WV{hBgb%dvp1zcJOV-RVq!fVLV&>m(E z4iBcZRzgcyFoB{8UnTa2XkB52!Jpb$r*w^UZP4><-O8es5E8916F*SQCyU60t@`|v zJYi%o_4Pq+Epb=YXs`u|ha0?|%inE=LLoFXJ!icmn`_)%-Vo#iy=N8+} zc83SHd8yMDPCa?H1%|<(#k9!Y{bytPw}dt!q)ljd+pcamm^S*uZF7r&s+1j9ISt5w z!H5yD%UPq5NWmy$5!*dg=nglk{WYq6t>!cbE|8Efy1nGI(WzF_mS^sId`=^vVUdBw zwEAij+s3=X9i~o!OVL^brtU(3!n#un+kNrljCn+DPZE+Qq?F>kIi@i%!PFd9v?q`q zm65ogaqkz8R#9$VyJ^i|bCgwlKym-#$6vP9}kvtc%t zOpC(YV)_G~5H4e%G-M!GYunwPC=Zx-i)7d$d`z>PV#-|-JbJHPV z(Pzvt<7kAP-Jg21%L5K2$ISXCg;C$@8}YYGoMQPLrBCGN^nT4BA0M|3p?^^Y@voev za~Uqr)gSjx`K_m|>Dha=TQ{IzJ4e;DcYIjoIuSQjx^(L*OIhB5xnXDDijbOWoB(hri%}vcU$q2lAX!mXGLTe)=2Ij9dh|?c&A)O zDl+6$;=@$Tv~5_1gT7A{63l4a>#u9E{?x zp|&AT^EVU2R#5Fk+nPPzYgi(_nG40dB%8VP6j{VAEi}j8dCJ|cxs{8Jfx`I$0jSe` zhUUU`XsZHCLhi12BgZyTiZjTDTrzcg_g$e=#Lyai=JR6o9s47)uaMW~SY6l)6uSE%G_by*k}#%mD-Hc+=n%rMjOF0a?1Rs3izjAq^K z8-GKOFFV(NyBjjz_WSdbylKtaBrWr}aVaZ1HwS!r8ebtzeQd;XTG?dw zVmUrsn;F>N6sKO#gJP$|i|e&Ik8rqrOxgMXM=IK!-<$b+3sU}V_@jTM?bhWUNb2`h z^_e-NX=JDoD}?mcpC+H;iT=tyei&~_Ia_y(59KUsIC>qN$bZU`zmq*$D)J+9?%!p= zwBu=Y6i!Fq6K0C3oUmPW0{l9`>Bnz3f1aYRpPPK2w&kr3db;G*w5ypN^siw?cf}#2 z$QgodU8{=wk#lsfuUoHP(ylv8_-|k8ZD*DZIyk9K-3uZox)E`+2e(a(!CV7|`>?i+ zen~{s>VeQy2c*->U-%9rBQ^>CV!pQ;nB__rI`AFxWN83uN747TB}*1cJ!!kjGt#pW zVC2A)MUZnnU!JytJK~W2xnjWlXA>AZ7^d|=Xn_xKjGQ&;EBDe+%T=9dZCVISfsdmZ zS`YTES$hAES%6-+c450o2l-l$4u?b;heh*Y0-HH<{3{M`IELL_HxGUU8tAeX-9I9_ zqZ3+RlwTdsMJuH7SAkiG)*l1;3TfBdt@F+{KBW^E6w%G{dSv-m%3rVq?f)}D)`=u4 zo<~7k@gk3uso9F2@%=9RWU^Z|-za+pD|!D8e3Yf2ykq^f*zdjhdMzLM0EC5hgy@}l zE6iOy;Y3g98O_!b%W|8n0oAmF37DO58YtCZUz-w21P@w;GZLQU>NN6~QoOBaojB)O zmwn3Ey}!X$Fj6JUa#Dl0#cQu-OMQv49N1~$B;Z#ffFsbjj~M4^S4CD$w1AR&lh{tK zV-RcQ2SIYn)WW9Lc;{b&hv*cy^yC4NZ5uJS3imK3`p%JWmOBxIS72V8$LBQ?t41Q zT|L0uV3w;4Rc6tbnpDxeWue4=L~kdsv2zkmcb@Gb-@`~xopb84hD}m z%J!g28L}_QAXgs^{0{%l5b3G3$COb*BDpD3o6L=!RDH*Psc>*7 z%zA!uEOSNPC?A`>5h%gH(n70&-t@?q_jd0KCqC1eGKuc_GP$fi!(=zIo-nFX;>hrx z%yYFGj7NXk#}s&(^Zf92u7N9H?)l%p;B{HEk1GsS^ z@F!U8Tj)O{e$x?ZvcJR!U#H^*ENwfJFA;(nr^3{RE@m@`p8ej%>5d)+Ap7}VwEQaD zw(;4mgoG8Fakxcyw>Yd{-5l?Th!vkN-kfeZGu{6}QYv?(qFk<1_P9h{=R`+2`TmZr z#1ZQwbEenZb#Bwg^;El8u7~w)b@l3R%)hMS{AOTCp;WG#Vl}AZtTRYz4xkRNze`>{ zcy@U$JqCYq|KGus-Si(DXYN10rlh3rdUd784WDK1o_O)o45^nNQm8&t#7mM?WX7s{ zkRbXtQj^6S)wlmS>0lcyU5)6RvcS z2j6U?BMxrv(kZ?>iyWtcf6`*evB1+S{QLpdPg;KX=*=O!6|UVkvYa_%1wJQIhbq=3 zh4l%}j+7B+eoLDjSS}L3V&jF6!dM<)zFo(dUtBMrkRVR=&&r2X54vW) zQHjo5CCzG)6>oG87TJEOl$>XBP$Q{9q-^F`EoFG`kfQLpwY`0X_s^JjdVTj2qM`zX zqcR?I{vUmPWmFVz_%hj9eH1ygI93j_Q3soJ;S3A=vz?@8Q&xYqhQe{(@)T;|=aw?2iXYFBK0@HrsPU+Ru~bxM873 z!Pk-xB;9@TIDJ|(n@-AT8}s=6Qe4MwukG@`d*1shHvW#o`BcsLx8QN*3|I(j&(BT2jx3= zKVWUnRJUAla=NGZFfFnoiOt^cIOoB*|e&y_!|kcG=n2n73AIz{F9GOn127~uX*L)t{!oM{#f0#xIt?RbuxXK zKGrb$4LZEYhGw<=WKzeExe!aY%ti1CO$U?;Ls0na>o{biX=KNj9`7-X#lLlQyr9rs(qA?_(a!UOJKvXA&6(fC;*WokR~M*v$azoNc91=P;~G8FpreN2&9aqinS(vIY3 z7=eVL4vrv-lK{CYU%(3*%S{_vJ4wOgp=R6MED^#>E*~PzE7`=x{9H(JPmDS%}Jz#xhxe!GCHRxNG5o< zZ@$;~W%gN)ve?5kao|FtG^(4PGrr8?-4X4M9RjvX=U_rB3e7QspHc?-FM5~9^Mbew zbE8qP@Tpzq5s~`!1&S_JrW{W|L>eT?2o|I&3}9oFwFs_jU}%?NgHzZ$3G#$x-Yi5xwSK+{=L}} zkJK>YsLCvdW+N{kV71p{p`y^HyW9d#s1kir@$%_0l75oT)WoWM7Jxf;gfmgm(N$>~ zFnFW?IW00|j59CP%Lfqet8paIW2!iE@5Syoaa67UHO(^sEXUGuLm*{}FKoL4>M6s` z>9-I|Dv7`3KNGoR>BuXYST-oz34IR=^fxl|Xyy$DF2TX_qRJ?{ZA!m}a*3SXjSx~lvI&x&dtOh& z)o|t(=}{#jV99yhJZc9HjT>Lm&$K5)hU7=rq&`soE#8TxKuf>z`{TT)Z;&X~*d&6F zWu{akuhw3MaimOX3N~vk(ECLFwwH03lgbHi2p6q(TJ6QD*&JVRYkNH`vCuO4;U8wm zF(-ylJ@x@^;EJXMx*MrOh-$Imp1-3L)RLqsJswRZYFH0{-&pqgQwuNm#ICe*Mq8N2 zSK~T`{4t{4Y8E<`HXQEYa%yVs4sH1arv*ycRq$B4>4DqU1+I}qmO z_Y1jgG8@FjiT7c_R3V0+n!xyjP71dnFxrbzUpjhyQS3*b#NmZCQL6|<3^cd=DqT5o7dyllw2qxOM$e){mPJsO^{ z%D00oIo~)al)I4m*9683DkVsk$m8ccn=X|cPMlr}fvq>O>KAdgc80vgxl z`VNc|STc3ucgBktFFdGzi$rqgMnr`&`LLI`EayWY4yrb+i=koOu{*9JRaMl|@@|2x z=p|Em)&kjZ**!yWhXe>gMAv?YUqRK1XzR#TxV2lWIhjvyx*YoK^7TWUOtP>%fsloq zRIjo7?WOzcoPTm>ef@2`D&`9YzVv0ar^XFZnwigBZ!Za^V`G_hxatF59B(76zx?n4 za}>uDh14Sb4fIA$p$*6iTeDNC1SY2MnHno>8*|w>rke?)a>D3$nf3EB zN4>vJNcVz_4ZaAw*3NGO{K&q8WM3_Uvg#*6P*r^zJ+*0v;8+ps=H(e&I!~%8XMsI8 za%a^CQd@@%`3I79A_g@zc}K1DV{2Dm&HUpnpq7%&9`m-q2@?}o^_K{im7NXMWFY6K ziC7e3bFIjk-^UFJ*EU3G0k(Fi=1sA)UCB%)$D?d#HSt z61DVBV@M5D;L5?ZyNh&@=%9koh9Y|spAo^hyMEH6G}@{p)+7>VaD55Y-_3MRm?C8C z&_J%*1HXMQ8LE@Q^q$LDi}eHev&hRGCv_9{x-{Hw*()RC$0BAfk`!|xzk#R9eT@9P z-mmj>DlIwhC6VGlxmm-WAJ^p^UXfQrV};P430P^rAh{C0;~v?puZ+y$WHht5M9dyg zvD|0C`g)mwKxJQ>>RFN5c%+(DRd5l&bJvXju_P@;sR3#5?|JpD50(&qEj_p{=A6uU zx@NMz^D>&(Eu2Q=}^Z=!?GpX6j>e;xs@`!rXNwl6W@2j+_pml zCo6=%UpCM)9ivHGwaTZ&?;_~TM=bZMXlME&)?YTMHZx{1S(hwXsx$I}juyMZ$}ULB zH&atQxtcXq;oOAg`l6r1EihtJrAm}K9A%Cxd~h&^;V`D;_3{s6RC?2u)y+jfv}u~^ zi7&0GI>Wr!6pjz7ht0c`{Xu?Lbvx>x@BezU=ZrR0i|gYZ|M-MniaVub-j_vGgb2Mv z5RI2SBZk_Ebv$6Rd9!Vfsh3}=9kX0wv<%xbk7x`3HX-_IN;l*P030=28E{H^+c*$q zrI%r6Y9?^ZJBu0;5@to8R&+ zKFy>0Yiq{q3b6_Epr6(6YSvzPfw=j|KW~<%+1r7*6|0*y_7{g7XAGM z2*La+vbHOmgRd7yVs=b{xk{~a)c8LF==8N&oswY(+Aq*Myw8?{@0kgzRyb=Bj=}lPi zWA(ET%LrlR1tgtyds(!_B=Q-EJM;!nT<~!7Onzi$tCLBYQsnkFQIFj;IYy0Ua@6V|Mg1s zPs&H40Ue0BXJ~Bfw-2vB*%mTBQ!)dBSgD-`$m(A8YKrqsv1I zE~j~6-4q=c^^C6-k^W7 zbqWRHODUv$Q5xrlDcv2t#E0sGxDDR?>f}v;88r~-5goE2bn$%%z825DfvN*5fIFQYaM=E|Pnvs~dXZLMax zk6I%`EeYyft-+aRXwp!TpPlfXa(Pj}iC481sC7rbIktDN!IJucIX^*)x5lq05OInT z;(lStBtO0JAZRme+*d`Lg5l(!pj71qaSAqLuB^K-t%%XkkT)@;@^;ooQF~nrlkIeu zP>w3e^PTc;mBX0Q*No2EX;i$8#%FmQ=IecuDU3X=rx4}-J5LTEVnl*}Q491?>@v8ov82Nj?%dj#pp9`cL;ImD34 zj@Hn>$14xF%L6S(woe-+@#7Ao{}*h^oK(sLr#WdjlX#BKs2sbv2h)^21=2)m5Yg0< z{zntceFDVsn(68fdTfnGa;VVjB90fe({BT5`PD(+&CO4r1BM}vN^M^c>isEYDIuv^ z;`!H%n-8oGGh)kFm=w?Y8uDdJG<|bYaH0|juXtsx2BhhUPo$HP-A?3!jP)FLFH`#_@I?GDhwc_8`*!X=F~H8{Os+?YSvtS z+)#BA1$S&cUJPzu?g45o4rZjo;yU;I&_p59D?j1yd<&oNHiz2v<9t*i!S+I32DRl1 z!(dZmDsg@S%wkI>o>!;m&Zr@%H^4$8zwE#|o%A7rWQpD0I)^$Ln4>I>nz7@>z8rB7 z4K_E{McU^PJ^y9PmKeOELXFAHJUh%QiKLjw=&_ev%D@`epRfBcAq+W>0#Yf3lyb6W zlJKDlNh>iYA>~V#R;dX&%{>k=p2@z3fUI@7(u-RYOB_Am28qZie8lm7U6HF1?^{ik zO8v|+Cyrw2bag83;#_%8foPysnW39`U;;1)I#bWR4Zx*K-Vq>w`~_mG7)Ku^6ziug z+JI!G9bHg($0aG{BcoN%QKbJLg2f5?FaLNP8P%Fg884V%DvKh3m7d-PJcEvE$T7!0 zdnoXdPOwNL7{u*CC$AfRvo)>r?M?SizSH72l9n77kmvubOkv%T*YZ)kk zK-~3AaPcEgL?US?tBZ_!$ughZ`&j0v8a@KD*bqTMhb>E36L1HW&m-u=5Codv9j_ta z6(5}xaiaINDS<&Iga@(;&!65?$smfY4(S@$z1PerWv4PP&=#Q*aeYhsL*^8xg`+T* zGmH1_5Zz}a7fldMYtb5SHv&#xjA>T!(Th(CP?sYA$Wov~pu-mQ`AY`Ze>mqZ<^c)*~OICn`V znU_*&1oS(BRuEIzP8PQFBT}zr#52dO(!7F%TjXqE8|M1dgus>9p|ps3oF+q!&n%8J zd&0R}>CR?|BMWll(CwnhFFWbB6cb*&!_Yd9e}F{WfOI4)`{XnbP-`2q_U;W=b0m*& zY%qOq(z1=+t0aA}Z&(r-n)2J;EMvgQ4JZXJNp)iSrJv@=kpLml2*hprpiAGP6GcQy z))@P9?DG0;Yz%a$*>euw<962h@)Zrn!O&qEG40vwggQWc$tdaGha-HFg}E)>FfHxX zgY3>M_j}T5c3~sY@c6Q!1q;VjzL_HGzowVAzT!gcbLBhl$;!aZ$-(-cL?Ta!? z&$008KAd7$0naDH7E^Y0bZ|{R4U7mz9zZJ=SMKE#NYqu3IT5Sm7=*^5!&ZVv0eVZc zZpAd!7z1Kc_@8<)!kTTp=DTRXJ5n7O3+tbh50g`9G`e!FTG>H#o2zZBA^ytk(!AFD zzy(3MUCD}&O)_S&6w*NiM2!e_EXj=9Kn^vvw6uhXKW{$SCO7+{St1$W8fmlzd4V0J zH4`t@-*d}rKY%X!ze9gRNoQ&4bg>K7@>S6mYWC_X?jQ2`lm&4KmG3kF)d!E7gh3|( zW3KtwU{ny-^8NXlC8HmDZT;^SN8NFXs?$2}FY;ei3~q_cv*+0!06q4?;fr2jt!-jRnaSHm zEjZaHsPoO%SH5Ya&sty1+Ei9m$*!OZJos#KQV;ij2zmF?_7tf6?zGY9ty9=nP6K6j zPHNxbIgQ0D^&#>*;;v&My^v`V?#miS(`4Yn#K}B?K+;TP)XY<@?%&?u%U}ndX=aR> zLj26LAQ8sU&K-JTrD?V^IXrVq#8=ceus+7#fOe z6Ng;73G;QAWa4il7Rl(7`@{0AuB5J+AP@Q&?3C3`JCMS)cECTYp{o)7cnil_%>V5{ zs>*GVa9cO4`FrN|Mi|&c{zxrvPuyz1cw2}Pr@}n4M>?V2X zy&T6EEG7tK2yn|#vPP&L)^_n(Z*IeawXyGZ1M-Sx{T#+VT6yNufIGjU*t_g-=Rw^S z|E4>?q#Nr0?6l=7e}SbV)Pd*P{nCEUs8)HI-@Zxcpnx5Gj(mD;HJcV_KI?ywy>RQ7 z7Hp*MmRYk3sF}5Vz*v}Tz%SrnvvzBSJ&+>l(%0ZP#BE{wytC=prOCcff+R3_!TtE7 z+*g5T!O64dZL`y;yOUQ?5s&TtXM^IoZc)I{ulW`w>88r7SHo;743v^VVzu_jQU^VN&ru;mkat8~dF@c?wDN(Nz-p=S#MbXlzKu zx1-3NE%I+2D)a}PEu1Pa`noA^V6rYaVnhS)^!v4d`%rSv`ln4DX|K46g zQLRHCql@N#0Z&o7T9eK>ZGx;4X54#Crj9}cUMBxI^2wkZ(xoW6w6tR_=Y!Y%;8f}; z>-;mUbe(%Uf0O*1-MO;fMg&T>_8BnmolvT2g6mY1igV(52p&oON2|y4@8?MxH#=6W zT}ynLq<^vsib~DWlNF~QMQ*y4eLqh76E0~P{RBe;!;H6PlY~)JkanU=jtkqaD2l$# zq@24qY(H(uzdpKRN}8X2==9Sv6h*7CfFFN}eXxacLp>e+=<02bIu6!aKxdrbcd*?U zjQ($WVwd7=Kjr;wV_F;5aGa&O@P8MO)10S0Nu%s1{zKP(>{{E^9~ioDd>Y=ly?y6% zSO3?kKHb@M#AT0_d5lEB%|;kcS6feryObqv_AER6D)BsU1R6q#?LLacd>Pvh=G`DC zq}?KPdwi$h6ke5umvB@A75)ZEmzAvAlhso&O=tq2WK7O{6fP~~7@`VWD3x0SJg%&W zMlioWulpl_DG@IlCG`(B-!F^_p1qtg+H$j8c~Xk-`a?gIg6t1_?2*M=b7RjS4NU67 z&~}*i-t@Zub3$KK<{9hR$7Pn+nO}u<=g*aA^b~lJ9XBp}bELwvCcO2a0%sr>08wHU zh(VGO#kVA3BPp?NOqi7fH~&va*-f_u`7K8CCa0W>F?!naaP z44jdwsFpo$G}%kA;^3pN0;9k#LlWoohMRsEij)=T+4Dj@f#Tac&#`>X`|M-8h_P*c zHw%G(<@m4GNbED-*NMUy0CduJ(>I-MxGb3uCxOmD>VvroaVSeI@x92GUoGALR{6x8 zTxds@`alHz@*JgJXF3}mN)>gxrZF(bsAjuAW-ir@`|9N`#90c@I|CYQJi13du8S9d%BC zBQ73T5C=Wk_6(;LD1DbpBe=QAkKfn9m;1NqvQA_9K$C#JQYYw#3xNz!eXnqs6@qdSu-~o?5$%5rkZj*wBFn4BBLxT z&UNn)DE*mBD>#@NVwCYG&T%h*Y~|IwC=4)1FxU5`sWX7XV= zj2x8;M&iLw7x3<|WpOd*X0_5xO=Vg!LfY_ZO(u<3ag;1GO5E)8$3$G%0|2;98YbzZ zgO9uvcPw1^Cfq!m+&;9a`PVo((hUVga)vz)SJm(NdsES_2lb^_z0&>w$;S2wliTe% z0+lV?%cvReQGEd8PVaLPY9^gDe+vg*)f=AJSKOZ$lDxKTA{#gp;%h4ZJ$mLT0j!{# z$&iUN&`WcPW)+%;%JKpTMPr)Ug9uSNHLS! zN5Iek!iOvxK-}(2_paFUr&!4>9%(dIsBL-WmE}G%_jwbLOP)&!E((0=VMr@^^|G=Z zE0HIRxsUp{%5gzv@-A*r^=2(`?a)}q!zba zhl)+yT8Y_VG?WR$lA%igrTJ#MT3Zv;f^Az!(UK#DquL5u!csyOc=x3(Z*Tk$Ki&L( z_}^p0f!Mu{QYL3;p5v$HMTuZ*b*?X!7I@4Q7pyx!G;GJd=)p%k1(v7+w1_qU=R5N=c4x0oJ2oEdWFnB>d7)lR@4d&2JuP%zD-jtS(k)!gAO zDks>LkztQ~E;u@SctBqyQq%wI639^dIeI`IP}L{q#ARg0`|`TyGmv9`&P4||gt@Fd-Ub9V zEp(4fELj;lb7tI-T`gyJ_+{`@gl@7I_f8T>Gn|XFW>JDu{Tow_NmoWe{JW>80MAd? zJo-wlb{u2@`0L3WCo-Y5yxK3XjN!iYrBJ#ijl*y7dnl0mzHZGtFCbAMkfX4`oqwVq zNk>2I7cFJGZ~EshP-v<}ny!|=vTzjPG=D)W_*4Gd0PeDafmP_(eLzJGrPi#6LHdAe z0gmvFwMd!znZhAQE+K?{j*Q>=4>&#%|A{TFb&0|EGRBw_=t@!6#h5R*odyExJeK_T zGX-`7k|@?TN}Uc}8XEP`>;`2;UDLs|N{f`* zlxtwN-nAm=7x;GkKJ487kfMJDP$;s$|t{{@?8*n{}%YW)o~?n~z-c*)l#KOX*k zPLZt-NsT0b%28#EXPru>U?OOlez@K!(iM9LT6e-cC1zmdlQ&3X9Bg#WMcEMc=t=e# ze#b*vF-!mYc8o+GW5s_iMq^Ebk?nqF)&uu*o=C4u6|iu?`QSiU-U!-?^4x719ro{{ ztxqGoX|$jBFH-^flX(a6!PNuZSZEa}ah1nE{k+@9K<0)%Kb4CQrw(IPJzAW-=@aqf zw7*JTQLDgP{yhLYu$3?V6!g=S&0 z)O1|d%|M{V+j$)BA>O;JUc2v#c%_{T0YvdA2zU(`9Y(heTvgdmMdVPNOXR9oB7Gl| z6DhiEi#`QQiC2%s-E|9M0h*ADkwi^9CAUAM0-@-ybcaPc0+;a&Iq91Z!0-E*kj0O& z#Zn_%{H{@)of`e|DAz)YU#zfuCItKdBd=A40Xt0stsnaei3HJvit~fGJueG)WO|n_ zjo_CbjjvtBlVf&V0p;l+AZYlPXVAi1td?HOglZGqR9^WvOeQ$Wb@dVkh;kWvbA%8T z4(3^af@~Xb9MVMKci;%9B4{NF(RWG%Z%6Tkk%ui*d4;s9<@+%I$g(9@#Sj2uhR%W9 zG->V>O&WIJD1>)jSi8Hh~;xD`keT4qLCx!QI5(F){MTI3|{YVtv~enpl-@t->!1kfsAZg(AIc(Czk5bb0_ zzzQZCa)6?XFxtuGA#1N-5npAj7tEh3fGg+9P2@NX{eFoP;rs#6$8|Vik{H4^^0^8P zyH`5yx7Wk`8thV~^Gb)V@kpwmT9N(s)9Wrns?B7Xwc)kLg%EaFN5K!iYqO1Ap}_=+ z@*S;0{X&Bt<7U%VV#t+wrJB2-1B+Oc)>gp!apxsE!C(Xg-cD3~2@T+hyM`0Ub&oxhD+r%?3Ch zcO7H9IMY&c}HQzkhk$(QU+m&jRT8YMewidsmGIh8n$e#)Q(`3_nZ}D3-Ykf0P+n^>u5x!R2%5F_-A?Y9!;% z{CoimK^|%7zv{okH|;gO1Fwc{Zd5;o7d9!7I#}JCPl4^KA!!^As0PId4d!c~#mCPEqAf-i@r_o4%|D%?^Qppb~g^lF&t?GRq zSaVR&huZvvfu{&sTQ%WUb=+KSoAC;~WSgrBUvB*OkZ{vl1uxhC1ATJBi4V9N0^R~2 zdMf(4a@%pnKE}r4W<_^Rh;xp&{r~2kF8WO@D_+WLg*kOBdti;M!iC>!I%0@rp5a#wT%u)h9{C=(-vT4PA1B z494%=A2K!&A7}QVvm@gIxWdULi^U+D`#Xi*24oHYW+y5Np@;7Uf+_&rIKH5%-2(cd z6VZ`6b;3N2iZ!*0^wawtR$%12m*%3K(bYQO4CW;@#Ef&MjG0l5|MsOj$^RivRY1t( zI3%j{#WHg&`4oA5v=1S9M~@}3OW&UP;y`Wmp9$qS6L{YmHB|bEPu%-0&pcSc`y1F< zz;Dz`*uP}UQm-eklDQktZsp$mQU4AiUV$A!FPSG?(m#8osi9M;mLr?-EL^eZq$7Xr zK>npt(`MkK#;WJ5DI_$Q>E{t|b6$VyiKC--0OY!|o0dXF$PO`&S)t3FzQ^i;bH-g} z$GooxM1%oFmxIOS5;zpk9=zwTnfV!cp>5Rk0M!k+-8R{Z^H@FU~(9x7V_ zB#g1zDLh}(JClw#N0>{X5y)cSAgkd1Wf5yBIv8UQb(R@`9d3YwFlK>sB>=U}ikdNfK{o z`bX+~Odym|`S+9|NJ*5v=*e&TkOwHIMbUF4fA*Np8Pbw$s{O0e?w6|QDy@Tp&;_zJ z_^^PHww;FI^#uG`c_4JL1<<;SSk&=nl-(8o12K(N{g{e!Iimr$2L`W$K3Xo4@ECU1 zH;~ej+U>@YZcr4CA6nZO>)lGW)a4*u&{;m{jy1e!t64m=@|Bi1v}GJ(D13-P6uItU zXsN7dv3Jw8VC|&}h(IJahwG4kowMHE4;!PSeFvgd<)1%$zONMYr7G18s_33TvIqqu z?xQG=*Dg8sX3oye>}$QVcFgN+dZ@dVYP}<33AT+kwI400MRsKjC?@IYj20+fKcgsS zqy`ZlH8cDDvh5wVB{&-3Om0rH8H&NdGqyvo&u3f^9Tw`hza&18-23flo)=B(cnQj7cClmDQ4ZMmeOi~$&zIv_fB9xuGI0f=Atoq*?-4Eyq6IkJ)scS)oLyo6nSxbJLuPn@ zJ-1fQq({%h!g|!+oNmLNNm;SEWAkb&PCGKULeymvGi#Lh-0Jz<(*+Myr^9)PaIe9; z5Bx_0WC5L_SEsmh0fqp@>4t{mtIqAFfIB5+0Pz{Uch;#W`OABD{8*mi=qjr9PfwE_ zn0GcGb*Y<7DeE=I3z>Ga7wMz1V)KulpH7-RKK*D#$MmnTPM+lbOUCk!hl92xDh7g0 zIQ^ZY+=z{V{oeUnVFwtQe)B;t=HRN+giJ5}&UCRz?)-bV&w}=%nfx1H-WZTr$2*pjFOlVtlCzLJSZNyaF4&i-D}rPP;4 zw+D6xu<#K9#ZwBhSD3?flff>klqWMT%A0%A|3k;uS!*GU&`k=}ZP(yHBjP~!=7285 z)x2G3OTukg`ph`u*=XX~W8&G`&CI^$$HA;luCBQym72w4|KM6mB)RX_bS+2eV+5w+`UXs7W zJ=WDE00Veq7y09fiRX5nftQd!PjfPZb*H8J0GwvfTl{g zod?*ZIt%<$mUMzJ```1Be&9$z{ + + + + + + +STM MATLAB Simulator: F:/Work/Projects/MATLAB/matlab_stm_emulate/MCU_STM32F4xx_Matlab/STM32F4xx_SIMULINK/stm32f4xx_matlab_tim.c Source File + + + + + + + + + + + + + +
    +
    stm32f4xx_matlab_tim.c
    +
    +
    +Go to the documentation of this file.
    1/**
    +
    2**************************************************************************
    +
    3* @file stm32f4xx_matlab_tim.c
    +
    4* @brief ИÑходный код ÑимулÑтора таймеров.
    +
    5**************************************************************************
    +
    6@details
    +
    7Данный файл Ñодержит функции Ð´Ð»Ñ ÑимулÑции таймеров STM32F407xx.
    +
    8**************************************************************************/
    +
    9#include "stm32f4xx_matlab_tim.h"
    +
    10
    +
    11
    +
    12
    +
    13struct SlaveChannels Slave_Channels; ///< Ñтруктура Ð´Ð»Ñ ÑвÑзи и Ñинхронизации таймеров
    +
    14
    +
    15
    +
    16//----------------------TIMER BASE FUNCTIONS-----------------------//
    +
    17/**
    +
    18 * @brief СимулÑÑ†Ð¸Ñ Ñ‚Ð°Ð¹Ð¼ÐµÑ€Ð° на один такт ÑимулÑции.
    +
    19 * @param TIMx – таймер, каналы которого надо запиÑать.
    +
    20 * @param TIMS – Ñтруктура таймера Ð´Ð»Ñ ÑимулÑции.
    +
    21 * @details Это Ð±Ð°Ð·Ð¾Ð²Ð°Ñ Ñ„ÑƒÐ½ÐºÑ†Ð¸Ñ Ð´Ð»Ñ ÑимулÑции таймера: она вызываетÑÑ ÐºÐ°Ð¶Ð´Ñ‹Ð¹ шаг ÑимулÑции
    +
    22 * и вызывает вÑе другие функции, необходимые Ð´Ð»Ñ ÑимулÑции:
    +
    23 * - Overflow_Check()
    +
    24 * - Slave_Mode_Check_Source()
    +
    25 * - TIMx_Count()
    +
    26 * - Channels_Simulation()
    +
    27 */
    +
    +
    28void TIM_Simulation(TIM_TypeDef *TIMx, struct TIM_Sim *TIMS)
    +
    29{
    +
    30 Overflow_Check(TIMx, TIMS);
    +
    31
    +
    32
    +
    33
    +
    34 // Выбор режима работы таймера
    +
    35 switch (TIMx->SMCR & TIM_SMCR_SMS) // TIMER MODE
    +
    36 {
    +
    37 // обычный Ñчет
    +
    38 case(TIM_SLAVEMODE_DISABLE):// NORMAL MODE counting
    +
    39 TIMx_Count(TIMx, TIMS);
    +
    40 Channels_Simulation(TIMx, TIMS); // CaptureCompare and PWM channels simulation
    +
    41 break;
    +
    42
    +
    43
    +
    44 // включение Ñлейв таймера по ивенту
    +
    45 case(TIM_SLAVEMODE_TRIGGER): // SLAVE MODE: TRIGGER MODE
    +
    46 Slave_Mode_Check_Source(TIMx, TIMS);
    +
    47 TIMx_Count(TIMx, TIMS);
    +
    48 Channels_Simulation(TIMx, TIMS); // CaptureCompare and PWM channels simulation
    +
    49 break;
    +
    50 }
    +
    51
    +
    52}
    +
    +
    53/**
    +
    54 * @brief СимулÑÑ†Ð¸Ñ Ñчетчика таймера на один такт ÑимулÑции.
    +
    55 * @param TIMx – таймер, каналы которого надо запиÑать.
    +
    56 * @param TIMS – Ñтруктура таймера Ð´Ð»Ñ ÑимулÑции.
    +
    57 * @details Ð”Ð°Ð½Ð½Ð°Ñ Ñ„ÑƒÐ½ÐºÑ†Ð¸Ñ Ð¿Ñ€Ð¾Ð²ÐµÑ€Ñет направление таймера и увеличивает или уменьшает
    +
    58 * значение Ñчетчика на то чиÑло, на которое оно бы увеличилоÑÑŒ за шаг ÑимулÑции.
    +
    59 * @note Ð”Ð»Ñ Ñчетчика иÑпользуетÑÑ double формат, Ñ‚.к. кол-во Ñчетов за шаг ÑимулÑции
    +
    60 может быть дробным. ПоÑле в конце функции double Ñчетчик запиÑывает Ñ Ð¾ÐºÑ€ÑƒÐ³Ð»ÐµÐ½Ð¸ÐµÐ¼
    +
    61 в региÑÑ‚Ñ€ таймера CNT.
    +
    62 */
    +
    +
    63void TIMx_Count(TIM_TypeDef* TIMx, struct TIM_Sim* TIMS)
    +
    64{
    +
    65 if ((TIMx->CR1 & TIM_CR1_DIR) && TIMx->CR1) // up COUNTER and COUNTER ENABLE
    +
    66 TIMS->tx_cnt -= TIMS->tx_step / TIMx->PSC;
    +
    67 else if (((TIMx->CR1 & TIM_CR1_DIR) == 0) && TIMx->CR1) // down COUNTER and COUNTER ENABLE
    +
    68 TIMS->tx_cnt += TIMS->tx_step / TIMx->PSC;
    +
    69 TIMx->CNT = (uint32_t)TIMS->tx_cnt;
    +
    70}
    +
    +
    71
    +
    72/**
    +
    73 * @brief Проверка на переполнение и Ð´Ð°Ð»ÑŒÐ½ÐµÐ¹ÑˆÐ°Ñ ÐµÐ³Ð¾ обработка.
    +
    74 * @param TIMx – таймер, каналы которого надо запиÑать.
    +
    75 * @param TIMS – Ñтруктура таймера Ð´Ð»Ñ ÑимулÑции.
    +
    76 * @details Ð”Ð°Ð½Ð½Ð°Ñ Ñ„ÑƒÐ½ÐºÑ†Ð¸Ñ Ð¿Ñ€Ð¾Ð²ÐµÑ€Ñет когда таймер переполнитьÑÑ Ð¸ еÑли надо,
    +
    77 вызывает ÑоответÑтвующее прерывание:
    +
    78 - call_IRQHandller()
    +
    79 */
    +
    +
    80void Overflow_Check(TIM_TypeDef* TIMx, struct TIM_Sim* TIMS)
    +
    81{
    +
    82 // Переполнение таймера: ÑÐ±Ñ€Ð¾Ñ Ñ‚Ð°Ð¹Ð¼ÐµÑ€Ð° и вызов прерываниÑ
    +
    83 if ((TIMx->CR1 & TIM_CR1_UDIS) == 0) // UPDATE enable
    +
    84 {
    +
    85 if ((TIMx->CR1 & TIM_CR1_ARPE) == 0) TIMS->RELOAD = TIMx->ARR; // PRELOAD disable - update ARR every itteration
    +
    86 if (TIMS->tx_cnt > TIMS->RELOAD || TIMS->tx_cnt < 0) // OVERFLOW
    +
    87 {
    +
    88 TIMS->RELOAD = TIMx->ARR; // RELOAD ARR
    +
    89
    +
    90 if (TIMS->tx_cnt > TIMx->ARR) // reset COUNTER
    +
    91 TIMS->tx_cnt = 0;
    +
    92 else if (TIMS->tx_cnt < 0)
    +
    93 TIMS->tx_cnt = TIMx->ARR;
    +
    94
    +
    95 if(TIMx->DIER & TIM_DIER_UIE) // if update interrupt enable
    +
    96 call_IRQHandller(TIMx); // call HANDLER
    +
    97 }
    +
    98 }
    +
    99}
    +
    +
    100//-----------------------------------------------------------------//
    +
    101
    +
    102
    +
    103
    +
    104//----------------------------CHANNELS-----------------------------//
    +
    105/**
    +
    106 * @brief СимулÑÑ†Ð¸Ñ ÐºÐ°Ð½Ð°Ð»Ð¾Ð² таймера.
    +
    107 * @param TIMx – таймер, каналы которого надо запиÑать.
    +
    108 * @param TIMS – Ñтруктура таймера Ð´Ð»Ñ ÑимулÑции.
    +
    109 * @details Ð”Ð°Ð½Ð½Ð°Ñ Ñ„ÑƒÐ½ÐºÑ†Ð¸Ñ Ñимулирует работу вÑех каналов таймера.
    +
    110 * Она вызывает функции:
    +
    111 * - CC_PWM_Ch1_Simulation()
    +
    112 * - CC_PWM_Ch2_Simulation()
    +
    113 * - CC_PWM_Ch3_Simulation()
    +
    114 * - CC_PWM_Ch4_Simulation()
    +
    115 * - Write_OC_to_GPIO()
    +
    116 * - Write_OC_to_TRGO()
    +
    117 */
    +
    +
    118void Channels_Simulation(TIM_TypeDef* TIMx, struct TIM_Sim* TIMS)
    +
    119{
    +
    120 CC_PWM_Ch1_Simulation(TIMx, TIMS);
    +
    121 CC_PWM_Ch2_Simulation(TIMx, TIMS);
    +
    122 CC_PWM_Ch3_Simulation(TIMx, TIMS);
    +
    123 CC_PWM_Ch4_Simulation(TIMx, TIMS);
    +
    124
    +
    125 Write_OC_to_GPIO(TIMx, TIMS);
    +
    126
    +
    127 Write_OC_to_TRGO(TIMx, TIMS);
    +
    128}
    +
    +
    129//-----------------CAPTURE COPMARE & PWM FUNCTIONS------------------//
    +
    130/**
    +
    131 * @brief Выбор режима первого канала и его ÑимулÑциÑ.
    +
    132 * @param TIMx – таймер, каналы которого надо запиÑать.
    +
    133 * @param TIMS – Ñтруктура таймера Ð´Ð»Ñ ÑимулÑции.
    +
    134 * @details Ð”Ð°Ð½Ð½Ð°Ñ Ñ„ÑƒÐ½ÐºÑ†Ð¸Ñ Ð¿Ð¾ региÑтрам таймера проверÑет как наÑтроен
    +
    135 первый канал и ÑоответÑтвующе Ñимулирует его работу.
    +
    136 */
    +
    +
    137void CC_PWM_Ch1_Simulation(TIM_TypeDef *TIMx, struct TIM_Sim *TIMS)
    +
    138{ // определÑет режим канала
    +
    139switch (TIMx->CCMR1 & TIM_CCMR1_OC1M)
    +
    140{
    +
    141 case (TIM_OCMODE_ACTIVE): // ACTIVE mode
    +
    142 if (abs(TIMx->CNT - TIMx->CCR1) < 2*TIMS->tx_step)
    +
    143 TIMS->Channels.OC1REF = 1;
    +
    144 break;
    +
    145
    +
    146 case (TIM_OCMODE_INACTIVE): // INACTIVE mode
    +
    147 if (abs(TIMx->CNT - TIMx->CCR1) < 2*TIMS->tx_step)
    +
    148 TIMS->Channels.OC1REF = 0;
    +
    149 break;
    +
    150
    +
    151 case (TIM_OCMODE_TOGGLE): // TOOGLE mode
    +
    152 if (abs(TIMx->CNT - TIMx->CCR1) < 2*TIMS->tx_step)
    +
    153 TIMS->Channels.OC1REF = ~TIMS->Channels.OC1REF;
    +
    154 break;
    +
    155
    +
    156 case (TIM_OCMODE_PWM1): // PWM MODE 1 mode
    +
    157 if (TIMx->CNT < TIMx->CCR1)
    +
    158 TIMS->Channels.OC1REF = 1;
    +
    159 else
    +
    160 TIMS->Channels.OC1REF = 0;
    +
    161 break;
    +
    162
    +
    163 case (TIM_OCMODE_PWM2): // PWM MODE 2 mode
    +
    164 if (TIMx->CNT < TIMx->CCR1)
    +
    165 TIMS->Channels.OC1REF = 0;
    +
    166 else
    +
    167 TIMS->Channels.OC1REF = 1;
    +
    168 break;
    +
    169
    +
    170 case (TIM_OCMODE_FORCED_ACTIVE): // FORCED ACTIVE mode
    +
    171 TIMS->Channels.OC1REF = 1; break;
    +
    172
    +
    173 case (TIM_OCMODE_FORCED_INACTIVE): // FORCED INACTIVE mode
    +
    174 TIMS->Channels.OC1REF = 0; break;
    +
    175
    +
    176}
    +
    177}
    +
    +
    178/**
    +
    179 * @brief Выбор режима второго канала и его ÑимулÑциÑ.
    +
    180 * @param TIMx – таймер, каналы которого надо запиÑать.
    +
    181 * @param TIMS – Ñтруктура таймера Ð´Ð»Ñ ÑимулÑции.
    +
    182 * @details Ð”Ð°Ð½Ð½Ð°Ñ Ñ„ÑƒÐ½ÐºÑ†Ð¸Ñ Ð¿Ð¾ региÑтрам таймера проверÑет как наÑтроен
    +
    183 второй канал и ÑоответÑтвующе Ñимулирует его работу.
    +
    184 */
    +
    +
    185void CC_PWM_Ch2_Simulation(TIM_TypeDef *TIMx, struct TIM_Sim *TIMS)
    +
    186{ // определÑет режим канала
    +
    187switch (TIMx->CCMR1 & TIM_CCMR1_OC2M)
    +
    188{
    +
    189 case ((TIM_OCMODE_ACTIVE) << (TIM_OCMODE_SECOND_SHIFT)): // ACTIVE mode
    +
    190 if (abs(TIMx->CNT - TIMx->CCR2) < 2*TIMS->tx_step)
    +
    191 TIMS->Channels.OC2REF = 1;
    +
    192 break;
    +
    193
    +
    194 case ((TIM_OCMODE_INACTIVE) << (TIM_OCMODE_SECOND_SHIFT)): // INACTIVE mode
    +
    195 if (abs(TIMx->CNT - TIMx->CCR2) < 2*TIMS->tx_step)
    +
    196 TIMS->Channels.OC2REF = 0;
    +
    197 break;
    +
    198
    +
    199 case ((TIM_OCMODE_TOGGLE) << (TIM_OCMODE_SECOND_SHIFT)): // Toogle mode
    +
    200 if (abs(TIMx->CNT - TIMx->CCR2) < 2*TIMS->tx_step)
    +
    201 TIMS->Channels.OC2REF = ~TIMS->Channels.OC2REF;
    +
    202 break;
    +
    203
    +
    204 case ((TIM_OCMODE_PWM1) << (TIM_OCMODE_SECOND_SHIFT)): // PWM mode 1 mode
    +
    205 if (TIMx->CNT < TIMx->CCR2)
    +
    206 TIMS->Channels.OC2REF = 1;
    +
    207 else
    +
    208 TIMS->Channels.OC2REF = 0;
    +
    209 break;
    +
    210
    +
    211 case ((TIM_OCMODE_PWM2) << (TIM_OCMODE_SECOND_SHIFT)): // PWM mode 2 mode
    +
    212 if (TIMx->CNT < TIMx->CCR2)
    +
    213 TIMS->Channels.OC2REF = 0;
    +
    214 else
    +
    215 TIMS->Channels.OC2REF = 1;
    +
    216 break;
    +
    217
    +
    218 case ((TIM_OCMODE_FORCED_ACTIVE) << (TIM_OCMODE_SECOND_SHIFT)): // FORCED ACTIVE mode
    +
    219 TIMS->Channels.OC2REF = 1; break;
    +
    220
    +
    221 case ((TIM_OCMODE_FORCED_INACTIVE) << (TIM_OCMODE_SECOND_SHIFT)): // FORCED INACTIVE mode
    +
    222 TIMS->Channels.OC2REF = 0; break;
    +
    223
    +
    224}
    +
    225}
    +
    +
    226/**
    +
    227 * @brief Выбор режима третьего канала и его ÑимулÑциÑ.
    +
    228 * @param TIMx – таймер, каналы которого надо запиÑать.
    +
    229 * @param TIMS – Ñтруктура таймера Ð´Ð»Ñ ÑимулÑции.
    +
    230 * @details Ð”Ð°Ð½Ð½Ð°Ñ Ñ„ÑƒÐ½ÐºÑ†Ð¸Ñ Ð¿Ð¾ региÑтрам таймера проверÑет как наÑтроен
    +
    231 третий канал и ÑоответÑтвующе Ñимулирует его работу.
    +
    232 */
    +
    +
    233void CC_PWM_Ch3_Simulation(TIM_TypeDef *TIMx, struct TIM_Sim *TIMS)
    +
    234{ // определÑет режим канала
    +
    235switch (TIMx->CCMR2 & TIM_CCMR1_OC1M)
    +
    236{
    +
    237 case (TIM_OCMODE_ACTIVE): // ACTIVE mode
    +
    238 if (abs(TIMx->CNT - TIMx->CCR3) < 2*TIMS->tx_step)
    +
    239 TIMS->Channels.OC3REF = 1;
    +
    240 break;
    +
    241
    +
    242 case (TIM_OCMODE_INACTIVE): // INACTIVE mode
    +
    243 if (abs(TIMx->CNT - TIMx->CCR3) < 2*TIMS->tx_step)
    +
    244 TIMS->Channels.OC3REF = 0;
    +
    245 break;
    +
    246
    +
    247 case (TIM_OCMODE_TOGGLE): // Toogle mode
    +
    248 if (abs(TIMx->CNT - TIMx->CCR3) < 2*TIMS->tx_step)
    +
    249 TIMS->Channels.OC3REF = ~TIMS->Channels.OC3REF;
    +
    250 break;
    +
    251
    +
    252 case (TIM_OCMODE_PWM1): // PWM mode 1 mode
    +
    253 if (TIMx->CNT < TIMx->CCR3)
    +
    254 TIMS->Channels.OC3REF = 1;
    +
    255 else
    +
    256 TIMS->Channels.OC3REF = 0;
    +
    257 break;
    +
    258
    +
    259 case (TIM_OCMODE_PWM2): // PWM mode 2 mode
    +
    260 if (TIMx->CNT < TIMx->CCR3)
    +
    261 TIMS->Channels.OC3REF = 0;
    +
    262 else
    +
    263 TIMS->Channels.OC3REF = 1;
    +
    264 break;
    +
    265
    +
    266 case (TIM_OCMODE_FORCED_ACTIVE): // FORCED ACTIVE mode
    +
    267 TIMS->Channels.OC3REF = 1; break;
    +
    268
    +
    269 case (TIM_OCMODE_FORCED_INACTIVE): // FORCED INACTIVE mode
    +
    270 TIMS->Channels.OC3REF = 0; break;
    +
    271
    +
    272}
    +
    273}
    +
    +
    274/**
    +
    275 * @brief Выбор режима четвертого канала и его ÑимулÑциÑ.
    +
    276 * @param TIMx – таймер, каналы которого надо запиÑать.
    +
    277 * @param TIMS – Ñтруктура таймера Ð´Ð»Ñ ÑимулÑции.
    +
    278 * @details Ð”Ð°Ð½Ð½Ð°Ñ Ñ„ÑƒÐ½ÐºÑ†Ð¸Ñ Ð¿Ð¾ региÑтрам таймера проверÑет как наÑтроен
    +
    279 четвертый канал и ÑоответÑтвующе Ñимулирует его работу.
    +
    280 */
    +
    +
    281void CC_PWM_Ch4_Simulation(TIM_TypeDef *TIMx, struct TIM_Sim *TIMS)
    +
    282{ // определÑет режим канала
    +
    283switch (TIMx->CCMR2 & TIM_CCMR1_OC2M)
    +
    284{
    +
    285 case ((TIM_OCMODE_ACTIVE) << (TIM_OCMODE_SECOND_SHIFT)): // ACTIVE mode
    +
    286 if (abs(TIMx->CNT - TIMx->CCR4) < 2*TIMS->tx_step)
    +
    287 TIMS->Channels.OC4REF = 1;
    +
    288 break;
    +
    289
    +
    290 case ((TIM_OCMODE_INACTIVE) << (TIM_OCMODE_SECOND_SHIFT)): // INACTIVE mode
    +
    291 if (abs(TIMx->CNT - TIMx->CCR4) < 2*TIMS->tx_step)
    +
    292 TIMS->Channels.OC4REF = 0;
    +
    293 break;
    +
    294
    +
    295 case ((TIM_OCMODE_TOGGLE) << (TIM_OCMODE_SECOND_SHIFT)): // Toogle mode
    +
    296 if (abs(TIMx->CNT - TIMx->CCR4) < 2*TIMS->tx_step)
    +
    297 TIMS->Channels.OC4REF = ~TIMS->Channels.OC4REF;
    +
    298 break;
    +
    299
    +
    300 case ((TIM_OCMODE_PWM1) << (TIM_OCMODE_SECOND_SHIFT)): // PWM mode 1 mode
    +
    301 if (TIMx->CNT < TIMx->CCR4)
    +
    302 TIMS->Channels.OC4REF = 1;
    +
    303 else
    +
    304 TIMS->Channels.OC4REF = 0;
    +
    305 break;
    +
    306
    +
    307 case ((TIM_OCMODE_PWM2) << (TIM_OCMODE_SECOND_SHIFT)): // PWM mode 2 mode
    +
    308 if (TIMx->CNT < TIMx->CCR4)
    +
    309 TIMS->Channels.OC4REF = 0;
    +
    310 else
    +
    311 TIMS->Channels.OC4REF = 1;
    +
    312 break;
    +
    313
    +
    314 case ((TIM_OCMODE_FORCED_ACTIVE) << (TIM_OCMODE_SECOND_SHIFT)): // FORCED ACTIVE mode
    +
    315 TIMS->Channels.OC4REF = 1; break;
    +
    316
    +
    317 case ((TIM_OCMODE_FORCED_INACTIVE) << (TIM_OCMODE_SECOND_SHIFT)): // FORCED INACTIVE mode
    +
    318 TIMS->Channels.OC4REF = 0; break;
    +
    319
    +
    320}
    +
    321}
    +
    +
    322
    +
    323/**
    +
    324 * @brief ЗапиÑÑŒ каналов таймера в порты GPIO.
    +
    325 * @param TIMx – таймер, каналы которого надо запиÑать.
    +
    326 * @param TIMS – Ñтруктура того же таймера Ð´Ð»Ñ ÑимулÑции.
    +
    327 * @details Ð”Ð°Ð½Ð½Ð°Ñ Ñ„ÑƒÐ½ÐºÑ†Ð¸Ñ Ð·Ð°Ð¿Ð¸Ñывает каналы OC в порты GPIO, определенные в TIMS.
    +
    328 * ЗапиÑÑŒ проиÑходит только еÑли пин наÑтроен на альтернативную функцию.
    +
    329 */
    +
    +
    330void Write_OC_to_GPIO(TIM_TypeDef *TIMx, struct TIM_Sim *TIMS)
    +
    331{
    +
    332 // write gpio pin if need
    +
    333 if (Check_OC1_GPIO_Output(TIMS)) // check OC OUTPUT 4 enable (GPIO AF MODE)
    +
    334 {
    +
    335 uint32_t temp2 = ~(uint32_t)(1 << (TIMS->Channels.OC1_PIN_SHIFT));
    +
    336 if (TIMx->CCER & TIM_CCER_CC1P) // POLARITY check
    +
    337 { // low POLARITY
    +
    338 if (TIMS->Channels.OC1REF)
    +
    339 TIMS->Channels.OC1_GPIOx->ODR &= ~(uint32_t)(1 << (TIMS->Channels.OC1_PIN_SHIFT));
    +
    340 else
    +
    341 TIMS->Channels.OC1_GPIOx->ODR |= 1 << (TIMS->Channels.OC1_PIN_SHIFT);
    +
    342 }
    +
    343 else
    +
    344 { // high POLARITY
    +
    345 if (TIMS->Channels.OC1REF)
    +
    346 TIMS->Channels.OC1_GPIOx->ODR |= 1 << (TIMS->Channels.OC1_PIN_SHIFT);
    +
    347 else
    +
    348 TIMS->Channels.OC1_GPIOx->ODR &= ~(uint32_t)(1 << (TIMS->Channels.OC1_PIN_SHIFT));
    +
    349 }
    +
    350 }
    +
    351 if (Check_OC2_GPIO_Output(TIMS)) // check OC OUTPUT 4 enable (GPIO AF MODE)
    +
    352 {
    +
    353 if (TIMx->CCER & TIM_CCER_CC2P) // POLARITY check
    +
    354 { // low POLARITY
    +
    355 if (TIMS->Channels.OC2REF)
    +
    356 TIMS->Channels.OC2_GPIOx->ODR &= ~(uint32_t)(1 << (TIMS->Channels.OC2_PIN_SHIFT));
    +
    357 else
    +
    358 TIMS->Channels.OC2_GPIOx->ODR |= 1 << (TIMS->Channels.OC2_PIN_SHIFT);
    +
    359 }
    +
    360 else
    +
    361 { // high POLARITY
    +
    362 if (TIMS->Channels.OC2REF)
    +
    363 TIMS->Channels.OC2_GPIOx->ODR |= 1 << (TIMS->Channels.OC2_PIN_SHIFT);
    +
    364 else
    +
    365 TIMS->Channels.OC2_GPIOx->ODR &= ~(uint32_t)(1 << (TIMS->Channels.OC2_PIN_SHIFT));
    +
    366 }
    +
    367 }
    +
    368 if (Check_OC3_GPIO_Output(TIMS)) // check OC OUTPUT 4 enable (GPIO AF MODE)
    +
    369 {
    +
    370 if (TIMx->CCER & TIM_CCER_CC3P) // POLARITY check
    +
    371 { // low POLARITY
    +
    372 if (TIMS->Channels.OC3REF)
    +
    373 TIMS->Channels.OC3_GPIOx->ODR &= ~(uint32_t)(1 << (TIMS->Channels.OC3_PIN_SHIFT));
    +
    374 else
    +
    375 TIMS->Channels.OC3_GPIOx->ODR |= 1 << (TIMS->Channels.OC3_PIN_SHIFT);
    +
    376 }
    +
    377 else
    +
    378 { // high POLARITY
    +
    379 if (TIMS->Channels.OC3REF)
    +
    380 TIMS->Channels.OC3_GPIOx->ODR |= 1 << (TIMS->Channels.OC3_PIN_SHIFT);
    +
    381 else
    +
    382 TIMS->Channels.OC3_GPIOx->ODR &= ~(uint32_t)(1 << (TIMS->Channels.OC3_PIN_SHIFT));
    +
    383 }
    +
    384 }
    +
    385 if (Check_OC4_GPIO_Output(TIMS)) // check OC CHANNEL 4 enable (GPIO AF MODE)
    +
    386 {
    +
    387 if (TIMx->CCER & TIM_CCER_CC4P) // POLARITY check
    +
    388 { // low POLARITY
    +
    389 if (TIMS->Channels.OC4REF)
    +
    390 TIMS->Channels.OC4_GPIOx->ODR &= ~(uint32_t)(1 << (TIMS->Channels.OC4_PIN_SHIFT));
    +
    391 else
    +
    392 TIMS->Channels.OC4_GPIOx->ODR |= (1) << (TIMS->Channels.OC4_PIN_SHIFT);
    +
    393 }
    +
    394 else
    +
    395 { // high POLARITY
    +
    396 if (TIMS->Channels.OC4REF)
    +
    397 TIMS->Channels.OC4_GPIOx->ODR |= (1) << (TIMS->Channels.OC4_PIN_SHIFT);
    +
    398 else
    +
    399 TIMS->Channels.OC4_GPIOx->ODR &= ~(uint32_t)(1 << (TIMS->Channels.OC4_PIN_SHIFT));
    +
    400 }
    +
    401 }
    +
    402}
    +
    +
    403/** ЗапиÑÑŒ результата compare в глабальную Ñтруктуру Ñ TRIGGER OUTPUT */
    +
    404/**
    +
    405 * @brief ЗапиÑÑŒ каналов таймера в глабальную Ñтруктуру Ñ TRIGGER OUTPUT.
    +
    406 * @param TIMx – таймер, каналы которого надо запиÑать.
    +
    407 * @param TIMS – Ñтруктура того же таймера Ð´Ð»Ñ ÑимулÑции.
    +
    408 * @details Ð”Ð°Ð½Ð½Ð°Ñ Ñ„ÑƒÐ½ÐºÑ†Ð¸Ñ Ñчитывает каналы OC и запиÑывает их в внешний канал триггера TRGO.
    +
    409 */
    +
    +
    410void Write_OC_to_TRGO(TIM_TypeDef* TIMx, struct TIM_Sim* TIMS)
    +
    411{
    +
    412 // write trigger output from OCxREF pin if need
    +
    413 unsigned temp_trgo;
    +
    414 if ((TIMx->CR2 & TIM_CR2_MMS) == (0b100 << TIM_CR2_MMS_Pos))
    +
    415 {
    +
    416 temp_trgo = TIMS->Channels.OC1REF;
    +
    417 }
    +
    418 else if ((TIMx->CR2 & TIM_CR2_MMS) == (0b101 << TIM_CR2_MMS_Pos))
    +
    419 {
    +
    420 temp_trgo = TIMS->Channels.OC2REF;
    +
    421 }
    +
    422 else if ((TIMx->CR2 & TIM_CR2_MMS) == (0b110 << TIM_CR2_MMS_Pos))
    +
    423 {
    +
    424 temp_trgo = TIMS->Channels.OC3REF;
    +
    425 }
    +
    426 else if ((TIMx->CR2 & TIM_CR2_MMS) == (0b111 << TIM_CR2_MMS_Pos))
    +
    427 {
    +
    428 temp_trgo = TIMS->Channels.OC4REF;
    +
    429 }
    +
    430 // select TIMx TRGO
    +
    431 if (TIMx == TIM1)
    +
    432 Slave_Channels.TIM1_TRGO = temp_trgo;
    +
    433 else if (TIMx == TIM2)
    +
    434 Slave_Channels.TIM2_TRGO = temp_trgo;
    +
    435 else if (TIMx == TIM3)
    +
    436 Slave_Channels.TIM3_TRGO = temp_trgo;
    +
    437 else if (TIMx == TIM4)
    +
    438 Slave_Channels.TIM4_TRGO = temp_trgo;
    +
    439 else if (TIMx == TIM5)
    +
    440 Slave_Channels.TIM5_TRGO = temp_trgo;
    +
    441 else if (TIMx == TIM6)
    +
    442 Slave_Channels.TIM6_TRGO = temp_trgo;
    +
    443 else if (TIMx == TIM7)
    +
    444 Slave_Channels.TIM7_TRGO = temp_trgo;
    +
    445 else if (TIMx == TIM8)
    +
    446 Slave_Channels.TIM8_TRGO = temp_trgo;
    +
    447 temp_trgo = 0;
    +
    448}
    +
    +
    449//------------------------------------------------------------------//
    +
    450
    +
    451
    +
    452
    +
    453
    +
    454//--------------------MISC (temporary) FUNCTIONS--------------------//
    +
    455/** Определение иÑточника Ð´Ð»Ñ Ð·Ð°Ð¿ÑƒÑка таймера в SLAVE MODE */
    +
    456/**
    +
    457 * @brief Определение иÑточника Ð´Ð»Ñ Ð·Ð°Ð¿ÑƒÑка таймера в SLAVE MODE.
    +
    458 * @param TIMx – таймер, который надо включить.
    +
    459 * @param TIMx – таймер, прерываний которого надо вызвать.
    +
    460 * @details Ð”Ð°Ð½Ð½Ð°Ñ Ñ„ÑƒÐ½ÐºÑ†Ð¸Ñ Ð¿Ñ€Ð¾Ð²ÐµÑ€Ñет какой триггер выбран Ð´Ð»Ñ Ð·Ð°Ð¿ÑƒÑка таймера,
    +
    461 * поÑле запиÑывает значение канала триггера в бит Ð²ÐºÐ»ÑŽÑ‡ÐµÐ½Ð¸Ñ Ñ‚Ð°Ð¹Ð¼ÐµÑ€Ð°.
    +
    462 * Таким образом, при лог.1 в канале триггера - таймер включитьÑÑ.
    +
    463 */
    +
    +
    464void Slave_Mode_Check_Source(TIM_TypeDef* TIMx)
    +
    465{
    +
    466 if (TIMx == TIM2)
    +
    467 {
    +
    468 if ((TIMx->SMCR & TIM_SMCR_TS) == TIM_TS_ITR0)
    +
    469 TIMx->CR1 |= (Slave_Channels.TIM1_TRGO << TIM_CR1_CEN_Pos);
    +
    470 else if ((TIMx->SMCR & TIM_SMCR_TS) == TIM_TS_ITR1)
    +
    471 TIMx->CR1 |= (Slave_Channels.TIM1_TRGO << TIM_CR1_CEN_Pos);
    +
    472 else if ((TIMx->SMCR & TIM_SMCR_TS) == TIM_TS_ITR2)
    +
    473 TIMx->CR1 |= (Slave_Channels.TIM1_TRGO << TIM_CR1_CEN_Pos);
    +
    474 else if ((TIMx->SMCR & TIM_SMCR_TS) == TIM_TS_ITR3)
    +
    475 TIMx->CR1 |= (Slave_Channels.TIM8_TRGO << TIM_CR1_CEN_Pos);
    +
    476 }
    +
    477 else if (TIMx == TIM3)
    +
    478 {
    +
    479 if ((TIMx->SMCR & TIM_SMCR_TS) == TIM_TS_ITR0)
    +
    480 TIMx->CR1 |= (Slave_Channels.TIM8_TRGO << TIM_CR1_CEN_Pos);
    +
    481 else if ((TIMx->SMCR & TIM_SMCR_TS) == TIM_TS_ITR1)
    +
    482 TIMx->CR1 |= (Slave_Channels.TIM2_TRGO << TIM_CR1_CEN_Pos);
    +
    483 else if ((TIMx->SMCR & TIM_SMCR_TS) == TIM_TS_ITR2)
    +
    484 TIMx->CR1 |= (Slave_Channels.TIM2_TRGO << TIM_CR1_CEN_Pos);
    +
    485 else if ((TIMx->SMCR & TIM_SMCR_TS) == TIM_TS_ITR3)
    +
    486 TIMx->CR1 |= (Slave_Channels.TIM3_TRGO << TIM_CR1_CEN_Pos);
    +
    487 }
    +
    488 else if (TIMx == TIM4)
    +
    489 {
    +
    490 if ((TIMx->SMCR & TIM_SMCR_TS) == TIM_TS_ITR0)
    +
    491 TIMx->CR1 |= (Slave_Channels.TIM3_TRGO << TIM_CR1_CEN_Pos);
    +
    492 else if ((TIMx->SMCR & TIM_SMCR_TS) == TIM_TS_ITR1)
    +
    493 TIMx->CR1 |= (Slave_Channels.TIM5_TRGO << TIM_CR1_CEN_Pos);
    +
    494 else if ((TIMx->SMCR & TIM_SMCR_TS) == TIM_TS_ITR2)
    +
    495 TIMx->CR1 |= (Slave_Channels.TIM3_TRGO << TIM_CR1_CEN_Pos);
    +
    496 else if ((TIMx->SMCR & TIM_SMCR_TS) == TIM_TS_ITR3)
    +
    497 TIMx->CR1 |= (Slave_Channels.TIM4_TRGO << TIM_CR1_CEN_Pos);
    +
    498 }
    +
    499 else if (TIMx == TIM5)
    +
    500 {
    +
    501 if ((TIMx->SMCR & TIM_SMCR_TS) == TIM_TS_ITR0)
    +
    502 TIMx->CR1 |= (Slave_Channels.TIM4_TRGO << TIM_CR1_CEN_Pos);
    +
    503 else if ((TIMx->SMCR & TIM_SMCR_TS) == TIM_TS_ITR1)
    +
    504 TIMx->CR1 |= (Slave_Channels.TIM4_TRGO << TIM_CR1_CEN_Pos);
    +
    505 else if ((TIMx->SMCR & TIM_SMCR_TS) == TIM_TS_ITR2)
    +
    506 TIMx->CR1 |= (Slave_Channels.TIM7_TRGO << TIM_CR1_CEN_Pos);
    +
    507 else if ((TIMx->SMCR & TIM_SMCR_TS) == TIM_TS_ITR3)
    +
    508 TIMx->CR1 |= (Slave_Channels.TIM7_TRGO << TIM_CR1_CEN_Pos);
    +
    509 }
    +
    510}
    +
    +
    511//------------------------------------------------------------------//
    +
    512
    +
    513
    +
    514//------------------------SIMULINK FUNCTIONS------------------------//
    +
    515/** Симулирование выбранных через дефайн таймеров */
    +
    516/**
    +
    517 * @brief СимулÑÑ†Ð¸Ñ Ð²Ñ‹Ð±Ñ€Ð°Ð½Ð½Ñ‹Ñ… таймеров.
    +
    518 * @details Таймеры Ð´Ð»Ñ ÑимулÑции выбираютÑÑ Ñ‡ÐµÑ€ÐµÐ· дефайны в stm32f4xx_matlab_conf.h.
    +
    519 Ð¤ÑƒÐ½ÐºÑ†Ð¸Ñ Ð²Ñ‹Ð·Ñ‹Ð²Ð°ÐµÑ‚ÑÑ Ð½Ð° каждом шаге ÑимулÑции.
    +
    520 */
    +
    +
    521void Simulate_TIMs(void)
    +
    522{
    +
    523#ifdef USE_TIM1
    +
    524 TIM_Simulation(TIM1, &tim1s);
    +
    525#endif
    +
    526#ifdef USE_TIM2
    +
    527 TIM_Simulation(TIM2, &tim2s);
    +
    528#endif
    +
    529#ifdef USE_TIM3
    +
    530 TIM_Simulation(TIM3, &tim3s);
    +
    531#endif
    +
    532#ifdef USE_TIM4
    +
    533 TIM_Simulation(TIM4, &tim4s);
    +
    534#endif
    +
    535#ifdef USE_TIM5
    +
    536 TIM_Simulation(TIM5, &tim5s);
    +
    537#endif
    +
    538#ifdef USE_TIM6
    +
    539 TIM_Simulation(TIM6, &tim6s);
    +
    540#endif
    +
    541#ifdef USE_TIM7
    +
    542 TIM_Simulation(TIM7, &tim7s);
    +
    543#endif
    +
    544#ifdef USE_TIM8
    +
    545 TIM_Simulation(TIM8, &tim8s);
    +
    546#endif
    +
    547#ifdef USE_TIM9
    +
    548 TIM_Simulation(TIM9, &tim9s);
    +
    549#endif
    +
    550#ifdef USE_TIM10
    +
    551 TIM_Simulation(TIM10, &tim10s);
    +
    552#endif
    +
    553#ifdef USE_TIM11
    +
    554 TIM_Simulation(TIM11, &tim11s);
    +
    555#endif
    +
    556#ifdef USE_TIM12
    +
    557 TIM_Simulation(TIM12, &tim12s);
    +
    558#endif
    +
    559#ifdef USE_TIM13
    +
    560 TIM_Simulation(TIM13, &tim13s);
    +
    561#endif
    +
    562#ifdef USE_TIM14
    +
    563 TIM_Simulation(TIM14, &tim14s);
    +
    564#endif
    +
    565}
    +
    +
    566/**
    +
    567 * @brief Деинициализирование выбранных таймеров.
    +
    568 * @details Таймеры Ð´Ð»Ñ Ð´ÐµÐ¸Ð½Ð¸Ñ†Ð¸Ð°Ð»Ð¸Ð·Ð¸Ð·Ð°Ñ†Ð¸Ð¸ выбираютÑÑ Ñ‡ÐµÑ€ÐµÐ· дефайны в stm32f4xx_matlab_conf.h.
    +
    569 Ð¤ÑƒÐ½ÐºÑ†Ð¸Ñ Ð²Ñ‹Ð·Ñ‹Ð²Ð°ÐµÑ‚ÑÑ Ð² конце ÑимулÑции.
    +
    570 */
    +
    +
    571void TIM_SIM_DEINIT(void)
    +
    572{
    +
    573#ifdef USE_TIM1
    +
    574 memset(&tim1s, 0, sizeof(tim1s));
    +
    575#endif
    +
    576#ifdef USE_TIM2
    +
    577 memset(&tim2s, 0, sizeof(tim2s));
    +
    578#endif
    +
    579#ifdef USE_TIM3
    +
    580 memset(&tim3s, 0, sizeof(tim3s));
    +
    581#endif
    +
    582#ifdef USE_TIM4
    +
    583 memset(&tim4s, 0, sizeof(tim4s));
    +
    584#endif
    +
    585#ifdef USE_TIM5
    +
    586 memset(&tim5s, 0, sizeof(tim5s));
    +
    587#endif
    +
    588#ifdef USE_TIM6
    +
    589 memset(&tim6s, 0, sizeof(tim6s));
    +
    590#endif
    +
    591#ifdef USE_TIM7
    +
    592 memset(&tim7s, 0, sizeof(tim7s));
    +
    593#endif
    +
    594#ifdef USE_TIM8
    +
    595 memset(&tim8s, 0, sizeof(tim8s));
    +
    596#endif
    +
    597#ifdef USE_TIM9
    +
    598 memset(&tim9s, 0, sizeof(tim9s));
    +
    599#endif
    +
    600#ifdef USE_TIM10
    +
    601 memset(&tim10s, 0, sizeof(tim10s));
    +
    602#endif
    +
    603#ifdef USE_TIM11
    +
    604 memset(&tim11s, 0, sizeof(tim11s));
    +
    605#endif
    +
    606#ifdef USE_TIM12
    +
    607 memset(&tim12s, 0, sizeof(tim12s));
    +
    608#endif
    +
    609#ifdef USE_TIM13
    +
    610 memset(&tim13s, 0, sizeof(tim13s));
    +
    611#endif
    +
    612#ifdef USE_TIM14
    +
    613 memset(&tim14s, 0, sizeof(tim14s));
    +
    614#endif
    +
    615}
    +
    +
    616//------------------------------------------------------------------//
    +
    617
    +
    618//------------------TIM'S HANDLERS (BETA) FUNCTIONS-----------------//
    +
    619// Определение обработчиков, которые не иÑпользуютÑÑ
    +
    620// Т.к. в MSVC нет понÑÑ‚Ð¸Ñ weak function, необходимо объÑвить вÑе колбеки
    +
    621// И еÑли какой-то колбек не иÑпользуетÑÑ, его надо определить
    +
    622#ifndef USE_TIM1_UP_TIM10_HANDLER
    +
    623void TIM1_UP_TIM10_IRQHandler(void) {}
    +
    624#endif
    +
    625#ifndef USE_TIM2_HANDLER
    +
    626void TIM2_IRQHandler(void) {}
    +
    627#endif
    +
    628#ifndef USE_TIM3_HANDLER
    +
    629void TIM3_IRQHandler(void) {}
    +
    630#endif
    +
    631#ifndef USE_TIM4_HANDLER
    +
    632void TIM4_IRQHandler(void) {}
    +
    633#endif
    +
    634#ifndef USE_TIM5_HANDLER
    +
    635void TIM5_IRQHandler(void) {}
    +
    636#endif
    +
    637#ifndef USE_TIM6_HANDLER
    +
    638void TIM6_DAC_IRQHandler(void) {}
    +
    639#endif
    +
    640#ifndef USE_TIM7_HANDLER
    +
    641void TIM7_IRQHandler(void) {}
    +
    642#endif
    +
    643#ifndef USE_TIM8_UP_TIM13_HANDLER
    +
    644void TIM8_UP_TIM13_IRQHandler(void) {}
    +
    645#endif
    +
    646#ifndef USE_TIM1_BRK_TIM9_HANDLER
    +
    647void TIM1_BRK_TIM9_IRQHandler(void) {}
    +
    648#endif
    +
    649#ifndef USE_TIM1_TRG_COM_TIM11_HANDLER
    +
    650void TIM1_TRG_COM_TIM11_IRQHandler(void) {}
    +
    651#endif
    +
    652#ifndef USE_TIM8_BRK_TIM12_HANDLER
    +
    653void TIM8_BRK_TIM12_IRQHandler(void) {}
    +
    654#endif
    +
    655#ifndef USE_TIM8_TRG_COM_TIM14_HANDLER
    +
    656void TIM8_TRG_COM_TIM14_IRQHandler(void) {}
    +
    657#endif
    +
    658
    +
    659/**
    +
    660 * @brief Вызов Ð¿Ñ€ÐµÑ€Ñ‹Ð²Ð°Ð½Ð¸Ñ Ñ‚Ð°Ð¹Ð¼ÐµÑ€Ð° TIMx.
    +
    661 * @param TIMx – таймер, прерываний которого надо вызвать.
    +
    662 * @details Ð”Ð°Ð½Ð½Ð°Ñ Ñ„ÑƒÐ½ÐºÑ†Ð¸Ñ Ñимулирует аппаратный вызов прерываниÑ
    +
    663 таймера по какому-либо Ñобытию.
    +
    664 */
    +
    +
    665void call_IRQHandller(TIM_TypeDef* TIMx)
    +
    666{ // calling HANDLER
    +
    667 if ((TIMx == TIM1) || (TIMx == TIM10))
    +
    668 TIM1_UP_TIM10_IRQHandler();
    +
    669 else if (TIMx == TIM2)
    +
    670 TIM2_IRQHandler();
    +
    671 else if (TIMx == TIM3)
    +
    672 TIM3_IRQHandler();
    +
    673 else if (TIMx == TIM4)
    +
    674 TIM4_IRQHandler();
    +
    675 else if (TIMx == TIM5)
    +
    676 TIM5_IRQHandler();
    +
    677 else if (TIMx == TIM6)
    +
    678 TIM6_DAC_IRQHandler();
    +
    679 else if (TIMx == TIM7)
    +
    680 TIM7_IRQHandler();
    +
    681 else if ((TIMx == TIM8) || (TIMx == TIM13))
    +
    682 TIM8_UP_TIM13_IRQHandler();
    +
    683 else if ((TIMx == TIM1) || (TIMx == TIM9))
    +
    684 TIM1_BRK_TIM9_IRQHandler();
    +
    685 else if ((TIMx == TIM1) || (TIMx == TIM11))
    +
    686 TIM1_TRG_COM_TIM11_IRQHandler();
    +
    687 else if ((TIMx == TIM8) || (TIMx == TIM12))
    +
    688 TIM8_BRK_TIM12_IRQHandler();
    +
    689 else if ((TIMx == TIM8) || (TIMx == TIM14))
    +
    690 TIM8_TRG_COM_TIM14_IRQHandler();
    +
    691}
    +
    +
    692//------------------------------------------------------------------//
    +
    Overflow_Check
    void Overflow_Check(TIM_TypeDef *TIMx, struct TIM_Sim *TIMS)
    Проверка на переполнение и Ð´Ð°Ð»ÑŒÐ½ÐµÐ¹ÑˆÐ°Ñ ÐµÐ³Ð¾ обработка.
    Definition stm32f4xx_matlab_tim.c:80
    +
    Check_OC3_GPIO_Output
    #define Check_OC3_GPIO_Output(_tims_)
    Дефайн Ð´Ð»Ñ Ð¿Ñ€Ð¾Ð²ÐµÑ€ÐºÐ¸ выводить ли канал 3 на GPIO (наÑтроен ли GPIO на альтернативную функцию)
    Definition stm32f4xx_matlab_tim.h:46
    +
    Write_OC_to_GPIO
    void Write_OC_to_GPIO(TIM_TypeDef *TIMx, struct TIM_Sim *TIMS)
    ЗапиÑÑŒ каналов таймера в порты GPIO.
    Definition stm32f4xx_matlab_tim.c:330
    +
    Simulate_TIMs
    void Simulate_TIMs(void)
    СимулÑÑ†Ð¸Ñ Ð²Ñ‹Ð±Ñ€Ð°Ð½Ð½Ñ‹Ñ… таймеров.
    Definition stm32f4xx_matlab_tim.c:521
    +
    TIM_Simulation
    void TIM_Simulation(TIM_TypeDef *TIMx, struct TIM_Sim *TIMS)
    СимулÑÑ†Ð¸Ñ Ñ‚Ð°Ð¹Ð¼ÐµÑ€Ð° на один такт ÑимулÑции.
    Definition stm32f4xx_matlab_tim.c:28
    +
    Write_OC_to_TRGO
    void Write_OC_to_TRGO(TIM_TypeDef *TIMx, struct TIM_Sim *TIMS)
    ЗапиÑÑŒ каналов таймера в глабальную Ñтруктуру Ñ TRIGGER OUTPUT.
    Definition stm32f4xx_matlab_tim.c:410
    +
    TIM_SIM_DEINIT
    void TIM_SIM_DEINIT(void)
    Деинициализирование выбранных таймеров.
    Definition stm32f4xx_matlab_tim.c:571
    +
    TIMx_Count
    void TIMx_Count(TIM_TypeDef *TIMx, struct TIM_Sim *TIMS)
    СимулÑÑ†Ð¸Ñ Ñчетчика таймера на один такт ÑимулÑции.
    Definition stm32f4xx_matlab_tim.c:63
    +
    CC_PWM_Ch1_Simulation
    void CC_PWM_Ch1_Simulation(TIM_TypeDef *TIMx, struct TIM_Sim *TIMS)
    Выбор режима первого канала и его ÑимулÑциÑ.
    Definition stm32f4xx_matlab_tim.c:137
    +
    Slave_Mode_Check_Source
    void Slave_Mode_Check_Source(TIM_TypeDef *TIMx)
    Определение иÑточника Ð´Ð»Ñ Ð·Ð°Ð¿ÑƒÑка таймера в SLAVE MODE.
    Definition stm32f4xx_matlab_tim.c:464
    +
    Channels_Simulation
    void Channels_Simulation(TIM_TypeDef *TIMx, struct TIM_Sim *TIMS)
    СимулÑÑ†Ð¸Ñ ÐºÐ°Ð½Ð°Ð»Ð¾Ð² таймера.
    Definition stm32f4xx_matlab_tim.c:118
    +
    Check_OC1_GPIO_Output
    #define Check_OC1_GPIO_Output(_tims_)
    Дефайн Ð´Ð»Ñ Ð¿Ñ€Ð¾Ð²ÐµÑ€ÐºÐ¸ выводить ли канал 1 на GPIO (наÑтроен ли GPIO на альтернативную функцию)
    Definition stm32f4xx_matlab_tim.h:38
    +
    CC_PWM_Ch3_Simulation
    void CC_PWM_Ch3_Simulation(TIM_TypeDef *TIMx, struct TIM_Sim *TIMS)
    Выбор режима третьего канала и его ÑимулÑциÑ.
    Definition stm32f4xx_matlab_tim.c:233
    +
    call_IRQHandller
    void call_IRQHandller(TIM_TypeDef *TIMx)
    Вызов Ð¿Ñ€ÐµÑ€Ñ‹Ð²Ð°Ð½Ð¸Ñ Ñ‚Ð°Ð¹Ð¼ÐµÑ€Ð° TIMx.
    Definition stm32f4xx_matlab_tim.c:665
    +
    Check_OC2_GPIO_Output
    #define Check_OC2_GPIO_Output(_tims_)
    Дефайн Ð´Ð»Ñ Ð¿Ñ€Ð¾Ð²ÐµÑ€ÐºÐ¸ выводить ли канал 2 на GPIO (наÑтроен ли GPIO на альтернативную функцию)
    Definition stm32f4xx_matlab_tim.h:42
    +
    CC_PWM_Ch4_Simulation
    void CC_PWM_Ch4_Simulation(TIM_TypeDef *TIMx, struct TIM_Sim *TIMS)
    Выбор режима четвертого канала и его ÑимулÑциÑ.
    Definition stm32f4xx_matlab_tim.c:281
    +
    Check_OC4_GPIO_Output
    #define Check_OC4_GPIO_Output(_tims_)
    Дефайн Ð´Ð»Ñ Ð¿Ñ€Ð¾Ð²ÐµÑ€ÐºÐ¸ выводить ли канал 4 на GPIO (наÑтроен ли GPIO на альтернативную функцию)
    Definition stm32f4xx_matlab_tim.h:50
    +
    TIM_OCMODE_SECOND_SHIFT
    #define TIM_OCMODE_SECOND_SHIFT
    Дефайн Ð´Ð»Ñ Ñдвига между первой и второй половиной CCMRx региÑтров
    Definition stm32f4xx_matlab_tim.h:28
    +
    CC_PWM_Ch2_Simulation
    void CC_PWM_Ch2_Simulation(TIM_TypeDef *TIMx, struct TIM_Sim *TIMS)
    Выбор режима второго канала и его ÑимулÑциÑ.
    Definition stm32f4xx_matlab_tim.c:185
    +
    tim1s
    struct TIM_Sim tim1s
    +
    tim4s
    struct TIM_Sim tim4s
    +
    tim12s
    struct TIM_Sim tim12s
    +
    tim3s
    struct TIM_Sim tim3s
    +
    tim7s
    struct TIM_Sim tim7s
    +
    TIM6_DAC_IRQHandler
    void TIM6_DAC_IRQHandler(void)
    Definition stm32f4xx_matlab_tim.c:638
    +
    TIM1_TRG_COM_TIM11_IRQHandler
    void TIM1_TRG_COM_TIM11_IRQHandler(void)
    Definition stm32f4xx_matlab_tim.c:650
    +
    TIM8_BRK_TIM12_IRQHandler
    void TIM8_BRK_TIM12_IRQHandler(void)
    Definition stm32f4xx_matlab_tim.c:653
    +
    TIM2_IRQHandler
    void TIM2_IRQHandler(void)
    Definition stm32f4xx_matlab_tim.c:626
    +
    TIM1_BRK_TIM9_IRQHandler
    void TIM1_BRK_TIM9_IRQHandler(void)
    Definition stm32f4xx_matlab_tim.c:647
    +
    TIM8_TRG_COM_TIM14_IRQHandler
    void TIM8_TRG_COM_TIM14_IRQHandler(void)
    Definition stm32f4xx_matlab_tim.c:656
    +
    TIM5_IRQHandler
    void TIM5_IRQHandler(void)
    Definition stm32f4xx_matlab_tim.c:635
    +
    Slave_Channels
    struct SlaveChannels Slave_Channels
    Ñтруктура Ð´Ð»Ñ ÑвÑзи и Ñинхронизации таймеров
    Definition stm32f4xx_matlab_tim.c:13
    +
    TIM4_IRQHandler
    void TIM4_IRQHandler(void)
    Definition stm32f4xx_matlab_tim.c:632
    +
    TIM8_UP_TIM13_IRQHandler
    void TIM8_UP_TIM13_IRQHandler(void)
    Definition stm32f4xx_matlab_tim.c:644
    +
    TIM7_IRQHandler
    void TIM7_IRQHandler(void)
    Definition stm32f4xx_matlab_tim.c:641
    +
    TIM3_IRQHandler
    void TIM3_IRQHandler(void)
    Definition stm32f4xx_matlab_tim.c:629
    +
    TIM1_UP_TIM10_IRQHandler
    void TIM1_UP_TIM10_IRQHandler(void)
    Definition stm32f4xx_matlab_tim.c:623
    +
    stm32f4xx_matlab_tim.h
    Заголовочный файл Ð´Ð»Ñ ÑимулÑтора таймеров.
    +
    Channels_Sim::OC2_GPIOx
    GPIO_TypeDef * OC2_GPIOx
    Порт второго канала
    Definition stm32f4xx_matlab_tim.h:88
    +
    Channels_Sim::OC4REF
    unsigned OC4REF
    Четвертый канал
    Definition stm32f4xx_matlab_tim.h:82
    +
    Channels_Sim::OC1_PIN_SHIFT
    uint32_t OC1_PIN_SHIFT
    Пин первого канала
    Definition stm32f4xx_matlab_tim.h:86
    +
    Channels_Sim::OC1_GPIOx
    GPIO_TypeDef * OC1_GPIOx
    Порт первого канала
    Definition stm32f4xx_matlab_tim.h:85
    +
    Channels_Sim::OC3_GPIOx
    GPIO_TypeDef * OC3_GPIOx
    Порт третьего канала
    Definition stm32f4xx_matlab_tim.h:91
    +
    Channels_Sim::OC4_GPIOx
    GPIO_TypeDef * OC4_GPIOx
    Порт четвертого канала
    Definition stm32f4xx_matlab_tim.h:94
    +
    Channels_Sim::OC2REF
    unsigned OC2REF
    Второй канал
    Definition stm32f4xx_matlab_tim.h:80
    +
    Channels_Sim::OC4_PIN_SHIFT
    uint32_t OC4_PIN_SHIFT
    Пин четвертого канала
    Definition stm32f4xx_matlab_tim.h:95
    +
    Channels_Sim::OC1REF
    unsigned OC1REF
    Первый канал
    Definition stm32f4xx_matlab_tim.h:79
    +
    Channels_Sim::OC3REF
    unsigned OC3REF
    Третьий канал
    Definition stm32f4xx_matlab_tim.h:81
    +
    Channels_Sim::OC3_PIN_SHIFT
    uint32_t OC3_PIN_SHIFT
    Пин третьего канала
    Definition stm32f4xx_matlab_tim.h:92
    +
    Channels_Sim::OC2_PIN_SHIFT
    uint32_t OC2_PIN_SHIFT
    Пин второго канала
    Definition stm32f4xx_matlab_tim.h:89
    +
    SlaveChannels
    Структура Ð´Ð»Ñ ÑƒÐ¿Ñ€Ð°Ð²Ð»ÐµÐ½Ð¸Ñ Ð¡Ð»ÐµÐ¹Ð² Таймерами
    Definition stm32f4xx_matlab_tim.h:61
    +
    SlaveChannels::TIM1_TRGO
    unsigned TIM1_TRGO
    Синган Ñинхронизации таймера 1.
    Definition stm32f4xx_matlab_tim.h:62
    +
    SlaveChannels::TIM6_TRGO
    unsigned TIM6_TRGO
    Синган Ñинхронизации таймера 6.
    Definition stm32f4xx_matlab_tim.h:67
    +
    SlaveChannels::TIM8_TRGO
    unsigned TIM8_TRGO
    Синган Ñинхронизации таймера 8
    Definition stm32f4xx_matlab_tim.h:69
    +
    SlaveChannels::TIM2_TRGO
    unsigned TIM2_TRGO
    Синган Ñинхронизации таймера 2.
    Definition stm32f4xx_matlab_tim.h:63
    +
    SlaveChannels::TIM7_TRGO
    unsigned TIM7_TRGO
    Синган Ñинхронизации таймера 7.
    Definition stm32f4xx_matlab_tim.h:68
    +
    SlaveChannels::TIM5_TRGO
    unsigned TIM5_TRGO
    Синган Ñинхронизации таймера 5.
    Definition stm32f4xx_matlab_tim.h:66
    +
    SlaveChannels::TIM3_TRGO
    unsigned TIM3_TRGO
    Синган Ñинхронизации таймера 3.
    Definition stm32f4xx_matlab_tim.h:64
    +
    SlaveChannels::TIM4_TRGO
    unsigned TIM4_TRGO
    Синган Ñинхронизации таймера 4.
    Definition stm32f4xx_matlab_tim.h:65
    +
    TIM_Sim
    Структура Ð´Ð»Ñ Ð¼Ð¾Ð´ÐµÐ»Ð¸Ñ€Ð¾Ð²Ð°Ð½Ð¸Ñ Ñ‚Ð°Ð¹Ð¼ÐµÑ€Ð°
    Definition stm32f4xx_matlab_tim.h:103
    +
    TIM_Sim::RELOAD
    int RELOAD
    Буфер Ð´Ð»Ñ Ð¿ÐµÑ€Ð¸Ð¾Ð´Ð° таймера (Ð´Ð»Ñ Ñ€ÐµÐ°Ð»Ð¸Ð·Ð°Ñ†Ð¸Ð¸ функции PRELOAD)
    Definition stm32f4xx_matlab_tim.h:106
    +
    TIM_Sim::tx_cnt
    double tx_cnt
    Счетчик таймера (double, Ñ‚.к. кол-во тактов за шаг ÑимулÑции может быть дробным)
    Definition stm32f4xx_matlab_tim.h:104
    +
    TIM_Sim::Channels
    struct Channels_Sim Channels
    Структура Ð´Ð»Ñ ÑимулÑции каналов
    Definition stm32f4xx_matlab_tim.h:107
    +
    TIM_Sim::tx_step
    double tx_step
    Шаг Ñчета за один шаг ÑимулÑции (double, Ñ‚.к. кол-во тактов за шаг ÑимулÑции может быть дробным)
    Definition stm32f4xx_matlab_tim.h:105
    +
    + +
    +Generated by doxygen 1.10.0 +
    + + diff --git a/DOCS/html/stm32f4xx__matlab__tim_8h.html b/DOCS/html/stm32f4xx__matlab__tim_8h.html index 3a47f6f..00cf748 100644 --- a/DOCS/html/stm32f4xx__matlab__tim_8h.html +++ b/DOCS/html/stm32f4xx__matlab__tim_8h.html @@ -5,7 +5,7 @@ -STM MATLAB Simulator: F:/Work/Projects/MATLAB/matlab_stm_emulate/MCU_STM32F4xx_Matlab/Drivers/STM32F4xx_SIMULINK/stm32f4xx_matlab_tim.h File Reference +STM MATLAB Simulator: F:/Work/Projects/MATLAB/matlab_stm_emulate/MCU_STM32F4xx_Matlab/STM32F4xx_SIMULINK/stm32f4xx_matlab_tim.h File Reference @@ -14,6 +14,7 @@ + @@ -71,7 +72,7 @@ $(function() {
    @@ -82,6 +83,9 @@ $(function() {
    stm32f4xx_matlab_tim.h File Reference
    + +

    Заголовочный файл Ð´Ð»Ñ ÑимулÑтора таймеров. +More...

    #include "stm32f4xx_hal.h"
    #include "stm32f4xx_it.h"
    #include "mcu_wrapper_conf.h"
    @@ -90,30 +94,30 @@ $(function() {
    @@ -121,30 +125,30 @@ $(function() {
    @@ -153,59 +157,87 @@ $(function() {

    Data Structures

    struct  SlaveChannels + Ð¡Ñ‚руктура Ð´Ð»Ñ ÑƒÐ¿Ñ€Ð°Ð²Ð»ÐµÐ½Ð¸Ñ Ð¡Ð»ÐµÐ¹Ð² Таймерами More...
      struct  Channels_Sim + Ð¡Ñ‚руктура Ð´Ð»Ñ Ð¼Ð¾Ð´ÐµÐ»Ð¸Ñ€Ð¾Ð²Ð°Ð½Ð¸Ñ ÐºÐ°Ð½Ð°Ð»Ð¾Ð² таймера More...
      struct  TIM_Sim + Ð¡Ñ‚руктура Ð´Ð»Ñ Ð¼Ð¾Ð´ÐµÐ»Ð¸Ñ€Ð¾Ð²Ð°Ð½Ð¸Ñ Ñ‚Ð°Ð¹Ð¼ÐµÑ€Ð° More...
      - + + + + + + +

    Macros

    #define TIM_OCMODE_SECOND_SHIFT   (TIM_CCMR1_OC2M_Pos - TIM_CCMR1_OC1M_Pos)
    #define TIM_OCMODE_SECOND_SHIFT   (TIM_CCMR1_OC2M_Pos - TIM_CCMR1_OC1M_Pos)
     Ð”ефайн Ð´Ð»Ñ Ñдвига между первой и второй половиной CCMRx региÑтров
     
    #define Check_OCx_GPIO_Output(_tims_, _OCx_GPIOx_, _OCx_PIN_SHIFT_)   (_tims_->Channels._OCx_GPIOx_->MODER & (0b11<<(2*_tims_->Channels._OCx_PIN_SHIFT_))) == (0b10<<(2*_tims_->Channels._OCx_PIN_SHIFT_))
     Ð”ефайн Ð´Ð»Ñ Ð¿Ñ€Ð¾Ð²ÐµÑ€ÐºÐ¸ выводить ли канал таймера на GPIO.
     
    #define Check_OC1_GPIO_Output(_tims_)   Check_OCx_GPIO_Output(_tims_, OC1_GPIOx, OC1_PIN_SHIFT)
     Ð”ефайн Ð´Ð»Ñ Ð¿Ñ€Ð¾Ð²ÐµÑ€ÐºÐ¸ выводить ли канал 1 на GPIO (наÑтроен ли GPIO на альтернативную функцию)
     
    #define Check_OC2_GPIO_Output(_tims_)   Check_OCx_GPIO_Output(_tims_, OC2_GPIOx, OC2_PIN_SHIFT)
     Ð”ефайн Ð´Ð»Ñ Ð¿Ñ€Ð¾Ð²ÐµÑ€ÐºÐ¸ выводить ли канал 2 на GPIO (наÑтроен ли GPIO на альтернативную функцию)
     
    #define Check_OC3_GPIO_Output(_tims_)   Check_OCx_GPIO_Output(_tims_, OC3_GPIOx, OC3_PIN_SHIFT)
     Ð”ефайн Ð´Ð»Ñ Ð¿Ñ€Ð¾Ð²ÐµÑ€ÐºÐ¸ выводить ли канал 3 на GPIO (наÑтроен ли GPIO на альтернативную функцию)
     
    #define Check_OC4_GPIO_Output(_tims_)   Check_OCx_GPIO_Output(_tims_, OC4_GPIOx, OC4_PIN_SHIFT)
     Ð”ефайн Ð´Ð»Ñ Ð¿Ñ€Ð¾Ð²ÐµÑ€ÐºÐ¸ выводить ли канал 4 на GPIO (наÑтроен ли GPIO на альтернативную функцию)
     
    - + + - + + - + + - + + - + + - + + - + + - + + - + + - + + - + + - - + + + + +

    Functions

    void TIM_Simulation (TIM_TypeDef *TIMx, struct TIM_Sim *TIMS)
    void TIM_Simulation (TIM_TypeDef *TIMx, struct TIM_Sim *TIMS)
     Ð¡Ð¸Ð¼ÑƒÐ»ÑÑ†Ð¸Ñ Ñ‚Ð°Ð¹Ð¼ÐµÑ€Ð° на один такт ÑимулÑции.
     
    void TIMx_Count (TIM_TypeDef *TIMx, struct TIM_Sim *TIMS)
    void TIMx_Count (TIM_TypeDef *TIMx, struct TIM_Sim *TIMS)
     Ð¡Ð¸Ð¼ÑƒÐ»ÑÑ†Ð¸Ñ Ñчетчика таймера на один такт ÑимулÑции.
     
    void Overflow_Check (TIM_TypeDef *TIMx, struct TIM_Sim *TIMS)
    void Overflow_Check (TIM_TypeDef *TIMx, struct TIM_Sim *TIMS)
     ÐŸÑ€Ð¾Ð²ÐµÑ€ÐºÐ° на переполнение и Ð´Ð°Ð»ÑŒÐ½ÐµÐ¹ÑˆÐ°Ñ ÐµÐ³Ð¾ обработка.
     
    void call_IRQHandller (TIM_TypeDef *TIMx)
    void call_IRQHandller (TIM_TypeDef *TIMx)
     Ð’ызов Ð¿Ñ€ÐµÑ€Ñ‹Ð²Ð°Ð½Ð¸Ñ Ñ‚Ð°Ð¹Ð¼ÐµÑ€Ð° TIMx.
     
    void Channels_Simulation (TIM_TypeDef *TIMx, struct TIM_Sim *TIMS)
    void Channels_Simulation (TIM_TypeDef *TIMx, struct TIM_Sim *TIMS)
     Ð¡Ð¸Ð¼ÑƒÐ»ÑÑ†Ð¸Ñ ÐºÐ°Ð½Ð°Ð»Ð¾Ð² таймера.
     
    void CC_PWM_Ch1_Simulation (TIM_TypeDef *TIMx, struct TIM_Sim *TIMS)
    void CC_PWM_Ch1_Simulation (TIM_TypeDef *TIMx, struct TIM_Sim *TIMS)
     Ð’ыбор режима первого канала и его ÑимулÑциÑ.
     
    void CC_PWM_Ch2_Simulation (TIM_TypeDef *TIMx, struct TIM_Sim *TIMS)
    void CC_PWM_Ch2_Simulation (TIM_TypeDef *TIMx, struct TIM_Sim *TIMS)
     Ð’ыбор режима второго канала и его ÑимулÑциÑ.
     
    void CC_PWM_Ch3_Simulation (TIM_TypeDef *TIMx, struct TIM_Sim *TIMS)
    void CC_PWM_Ch3_Simulation (TIM_TypeDef *TIMx, struct TIM_Sim *TIMS)
     Ð’ыбор режима третьего канала и его ÑимулÑциÑ.
     
    void CC_PWM_Ch4_Simulation (TIM_TypeDef *TIMx, struct TIM_Sim *TIMS)
    void CC_PWM_Ch4_Simulation (TIM_TypeDef *TIMx, struct TIM_Sim *TIMS)
     Ð’ыбор режима четвертого канала и его ÑимулÑциÑ.
     
    void Write_OC_to_GPIO (TIM_TypeDef *TIMx, struct TIM_Sim *TIMS)
    void Write_OC_to_GPIO (TIM_TypeDef *TIMx, struct TIM_Sim *TIMS)
     Ð—апиÑÑŒ каналов таймера в порты GPIO.
     
    void Write_OC_to_TRGO (TIM_TypeDef *TIMx, struct TIM_Sim *TIMS)
    void Write_OC_to_TRGO (TIM_TypeDef *TIMx, struct TIM_Sim *TIMS)
     Ð—апиÑÑŒ каналов таймера в глабальную Ñтруктуру Ñ TRIGGER OUTPUT.
     
    void Slave_Mode_Check_Source (TIM_TypeDef *TIMx, struct TIM_Sim *TIMS)
     
    void Slave_Mode_Check_Source (TIM_TypeDef *TIMx)
     ÐžÐ¿Ñ€ÐµÐ´ÐµÐ»ÐµÐ½Ð¸Ðµ иÑточника Ð´Ð»Ñ Ð·Ð°Ð¿ÑƒÑка таймера в SLAVE MODE.
     
    void Simulate_TIMs (void)
     Ð¡Ð¸Ð¼ÑƒÐ»ÑÑ†Ð¸Ñ Ð²Ñ‹Ð±Ñ€Ð°Ð½Ð½Ñ‹Ñ… таймеров.
     
    void TIM_SIM_DEINIT (void)
     Ð”еинициализирование выбранных таймеров.
     
    -
    +

    Detailed Description

    +

    Заголовочный файл Ð´Ð»Ñ ÑимулÑтора таймеров.

    +

    Данный файл Ñодержит объÑÐ²Ð»ÐµÐ½Ð¸Ñ Ð²ÑÑкого Ð´Ð»Ñ ÑимулÑции таймеров STM32F407xx.

    + +

    Definition in file stm32f4xx_matlab_tim.h.

    +
    Generated by doxygen 1.10.0 diff --git a/DOCS/html/stm32f4xx__matlab__tim_8h__dep__incl.map b/DOCS/html/stm32f4xx__matlab__tim_8h__dep__incl.map index d65dc26..fbf3b7d 100644 --- a/DOCS/html/stm32f4xx__matlab__tim_8h__dep__incl.map +++ b/DOCS/html/stm32f4xx__matlab__tim_8h__dep__incl.map @@ -1,24 +1,24 @@ - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + diff --git a/DOCS/html/stm32f4xx__matlab__tim_8h__dep__incl.md5 b/DOCS/html/stm32f4xx__matlab__tim_8h__dep__incl.md5 index 0a3e34f..ad75e9f 100644 --- a/DOCS/html/stm32f4xx__matlab__tim_8h__dep__incl.md5 +++ b/DOCS/html/stm32f4xx__matlab__tim_8h__dep__incl.md5 @@ -1 +1 @@ -fd7617bb288ec96edb90424c3f62e3e6 \ No newline at end of file +01ea3a86c552ae3c96130f5b44485259 \ No newline at end of file diff --git a/DOCS/html/stm32f4xx__matlab__tim_8h__dep__incl.png b/DOCS/html/stm32f4xx__matlab__tim_8h__dep__incl.png index 7287fa7ea259b8fd30ba76405d5c730c209e7994..cf8ae7e69428f4da89322500f3928677c8cbd251 100644 GIT binary patch literal 34284 zcmZ_#c|6o_)IW|-dy%wK*2+#OYo;u35;L|ek-d^VBMd^8-i1o2u{HK>>`U2)P*k#v zWek(O$TG%|%#hLWy5t}NUe|W6=Q-zjme=zehB_Q)M9 z8x4c)zIbpy_zSy!3J(0Y|E`|SHP{yPFS9W}4hB05LtOjE>|yG{Sa7P1Z}8gInzNHK z`$-e;Qyzk&h0hZrTW&6CPA^*UoLfL$bdz`-rT5Rbp|OKp?@CX}R$EwDmm`A)il6PP z7#jPjX`JF>tbEV;AKg<&OEf&nz1`2|3-LorgPrG+zD!G%(#*V`GfFYPt zF*FQDlgQ}VdW}uvg&zn@HdfdTgK21=jE0dGezkIvF(P`JZLp)QtF)17U+Q4*B`~aa zzeyG}9DL3Oi1X~){`MUP#%zBcz+PP6`F0tmEwuBEFD(1m&bK4IC*ZKK#kYZsdCXF| zWu++54>xGt80cHFCdD`=(w3~~?lvA9$V5f7unI|`BnO+tI^C^+``L@`I5nwiPB2U6 zJFut=_WJm!j&z`cmJr*`gy9#(;|@n_bxr5LadW?#m(EUb&w1S@03OzGJZ!Y*)vcA! zVMwDt@gsR>RN&hAG-#TznM{|xXOCrbg-_O~Y?&67BaMip5l^ox0~Kc0<)ane8zzNm zcX2PgPbNZJzj&2Hqw^%UC|lHVLI}KInCiAf?hh>u)^W`t-6$(y4K&zC3kaOX(M+^2 zzOaT?_PL?3yH}2(Z)kh#nz)6{Gt&>xtS%N+Kj>S~yq>z6bMlp&YE0>uR7hAFRPZe9 zGcRVaYqz#g1mzT`vir|Cjqt4tkDABTl82PQGhxHq&um%!ahi3xcO`l>|MEmdVr~s2 z|4(h#zQK-*bsQ}cUs9IRDK?XQL#ikl-ZX>9B-BK&(EPl721a%!Sn_%MF=;jfhJX>fLdQM?Jg~BG{x&SvoNsPyV01Yd_||hb!PdEXM>d>F0tIMk@-2JVB{Kw9XzPv3lLUS zEqv+#CLU)wKh}0xJAI(o!kv(;D7%SnUET+t!92}A7M6&W-JKak3hdVN(D`u?{MAJo zAo5>vz6!Hj2gQ|77LqRF#9Py|4|~3_e)cR`WKr!4O&%pUU}r%sA6+ipQ41nZUDqpo>;?=n`LXg3;6`Rn)mk z=;mDnBJy{+)L$Q;iwv0*KV&peC8s5Q!mnqmlBiOyBzTi_sFIp?ix)hp5pdOY@7ZNG z_B~!N_8Qkn*(jqDO-2-RZub?O^D=I(Q0rbs%{*u<@QCD*gQSLrv-86=f_ToH8LD&X z%l1jSV0j$Q7IwPEbE2%&y4LN{qtpp#2RDwj_JjYx=K&1tMdLBDwKiFCLE>5l^tT%v zzy^pP&DPbr15K)N{L)np=q$CQm2>d07ji{2dFt%HcD9gyYX3>F^wWgRhzn|t*=Q+r*K!l zAxavr;s=#@p8FgI4_66-ea%TGuZv2=LipjlE%+76` z@mC^5E{|BB@M&lkK&$zW>8J%xP0z!^EkOEm8yKSD4YsfG;B$DG`AL`?t(^Gia>B_Y z(UOXMMZ{l)*Tqq_4{qH`{c#)Ix?7~r=-=(-6?lLMp5Jhjo3uie+PUj+6>f0$*&!qJq_k}kp&nRHY9m=y5%|1ZA%OK7g(jfx@PhbCSEZ>*kL~%4257H zMLa^1tWXQ=v->5Ljc)wtzckIfKlo0ZFNVv%z+8GH!A%SSU*0+6m$>UNxFJpqUUZ7x zE%({TNqqwBu{_Pl%tQ^?0I~%LC z;d{NPxyQr2sRqaFyYUn2T@og6`qyaUdT9oyR#!e9F+n=l(B< z0CVx`V6jEH+V}j20XQ;lxVQ$Ds+3bU@=}QxH@qxeTk;^FaBbu!X(4*JEw>t)*Q^!T z)_)=2(!L(l(J1KHU|x_|er80;y8*&UG0C~%lM5ay;}|KNGC z)$6=7lGO&6pm{VTpi42YzI(ke+n_i@^tqHnnXSgrpwCOnlZZ@{;O^#_-*jW# zoqxR|Beloc3fg2k{BVhF1e?Eh%fGF9taG{{Io~(}RAsM)&0mCfU;Zup4_h3me*7=B zK&ySmC&9h=VvwTOYWYK!No%Df$Ma(0d9^R9ez@WCRXB20eB<=&`Kff$~ zp`@!kgLIzVh!3(9j5`l`!oGK$vPrfi6)MD+4DwZT#S}>wD=hn(;h0kCPw}I_FSAvi z;$D%Ic8_miy)?b>vcmR9y|Ln5!4bzdqF@SmZ1@parfT%dm-lU|T>9{Oi5Cv>@6$Lu zQtL?`EVWitQ|n#=kHHF_{cwf;hruqxfXo$aap$ZLH~iBOqBg7uf$Zoh2y<;53X-nm z9-W36$SY;veaHiifWeLcS?zrLA4clG9oCzJycz^Q+Ayw7Am{@6aAvqZCh~}JQt-xV zcnla8rUV%l1Cv71n2(Q7a!Lw2KkfpRVz6HRe&Os^g1!1Dzs))Bz)gyML^nw(kkin8 zN!BOJLHIc?=tAv6PJVuk`exPQ)?Y15tv>_WM?s6`0a%z-$?$i|6V5?TI(_a|T#PwV zCx!a$J^E#?1(teCnUzdy?hd{)YiL`wd^P9babrJm|wzVV}) zK*yzBp`+NY_u0Px%!%xwSE9$0qfp%Vl-pR~>n*Mm$qAowp}`{QT`M z;feFCZ@KKkX<`&|qbMVfYmPrlUS#M~X0Tcsnb&sMIdADm4-=myzdeU0G{>#x zF25AIGDcEW<=V#r!vp#Bjo++^5{gVuK4Y;Li$OgKSM|G}VfY$d+MslV@F%%1s8Ja$ z1NM+?lTEgMgD-`W>tPU zi-yz541cV9bnb??N?P;g{SCyNKA1?O6j&>byS7b38xa*D#*1fEg~<%L;1QcpvBElW zu&Z6;SE#beWQydQdp4M*xDa)-JU{sXPvv@aQEpCPAbRO*Nyc&b2{6?SDZr18&sIo> zxQJ3M7LXLLxIrY-4_;0-Jn~JOQl%#9T6Wu)?K($=Z26W`;T}<5qX0YZeTPVSdHWaa z{bm`W{=s5POeZinq8sw*q zaD3UA|Eohr{mcHi%{A$Z~bJ#l;dG^ugE5nUx2 zXUU?74Pstx^x8=44rB&^<>>Wpt=uenPv7MejSMs=PUNl4Cod<|NTF*`3GK{QOiXc= zp<4MAx%BM;>yw33FAX=2;qAtRDG%k-uJn1<^bwy>+GByPp}b-rnId6n~#cB;OQhadUA(-&FxG>C8(t7}gPCA1mmv0;oOMRsAWzBwZcS{ir&DJA=C9A3Lnd~;+^RMS{H!;Q zF2zs;5F>08h7Dz>1>XwR%Gu}hq%Zq7xDs<^`N#4PYny?&gdwKLVR7R^V2X{u1g==L zhbWq!=OTzLY0#TB;`kQPYY86$>kru4`%+SRXrut%o=RXsA;5J(v?%%q3TtVPZD*=F z)wkM2-3#3KnVF_EOodTPA#+iKL!H3k}2chklxY7?D%0h zCPgOOFfGT?#Hi2bVW&#@tCnU~;I_m`8$`z{*~*>8<<`!BryQpyZA?yYaBgH7of9F z#HYET-ehXt{`=GQyBgHdYMHjB0RG-8tQh^CX%lAK>lBvaHjXkIfTum$?r8nDSAVel zTLN)vk@>R0>35z8xc)v;rs{FHVDF*93=j2o2E|{5^)(26W!vwb6$Xn+29llZ-?TFm ze0%~;i1u}q&UE5r;Xl@mWfL_wJzyFas7XVWlq%**S-!V~#~EgX?2&D-j6DYq0wXiD zAj_M+{O*Yf7_1{)nm~V17}9We{z8!CgR7Z2(XzGt>uPBtWFwD^n!`QJ;%y(Gu?7_C zyU2AXa(x33XW@CV(-*5bA;#}m+nPQjB@^)@E@lI zT5}e`lg_Z<0GMI>0b(V{%{bk#dX=fV(>GO8*BtD4g3u0iy1?Jw1;{quTf za1a<=Z{sv*^z|NVzrU(mSpr5amD=wGB*plH961FfMH?)An_(H-9baV;Fy`0p6l%F` zR_BhKj1H4gjAxJ`9kbawPl=XsjG^?qgDuZ9I`8|>J%Vlaf5NWzSD_>DT)8I60%@yS zJLjDRU_xVoGI)qn`$bumxf9+LjKg9dHGls?#5>0tS+p7q7tQ%Cw!f^>Ch%sN1@D)d zhekWg-v8Tj2>l$4CFna~x?fRcaP*k=$|{7D0Gv0><%`8P2O;^*n)j}qoPN|L;nJPU zNdsYKnBmNSz}~+L9cgo*-FN1{VZU1G*V`o3zt5@TUPXxG+*JU;IU8`mBMM40gH&OKzkmsNk@Za`VrFA;lx6+b9{9l^Er=#*1Odnhe*;!c zQa1Q(QombV$UJfD8{Twk$F}W18xYf^6UuxNM|bL^O6Bx#&MYUa>Tg5F#U5PbUSPKl zc?W;B<$hCTKun1I>B~}-x-WxPg0(9uIj!p{ZG(3|aANe+L@+IurJ5)I9f~S=TrK_uCTo4W=%Z9nNh0gAZaQa)7 zRbn)|Qg2TT_5EMira9U+2e;*_C!q&^z1%Y2hMS8K$PDe~NnY;nQV^va#xI&6m)=~} zOF3=0JJU{QBF6}I1>syzVdwT-#sL!q$P-wt*A8$S7l^YmJM;&e9rCXHgzJ{ciyfd< z0c7Ug-kW*s%a;oo-R`nUQZLHIMzKwiu)2xwrP}7Z~5^LYoVm>6~f#$!3ziYapAcHukb6GBPq& zsdB6TWli7Z^|*;O(V&IZ(p9>aI%nFxY3xwM^73-gRx^L{@>CaH72yD^)J^tmKuI$9 zD0rN|FMq{lq zpUZrbJjgj;H7h`Qqs2u%eO*ChU=QcjR~acOK^i6l*^sxuV3&!3WyZR^K(MZw&RE zFK=E^VGXo|*B8`Ugo;pX33?!s3N!o&Wi`={qi2T%uxi4TW@jgszve7Bk;ZQ*!P9 z9Vg3{2IU;vp~PaCOxzXSj92%9g6JQ6Ex})30rLiooE+rNFq^|TDToDg?hJ^3ll>Z- z@b`JWE#A>(D~cp`^Lw_dx+EIPQ41Sozqsy2m^k}s{c~tYiqp@z zlW8^TbA~p8$vOS2`6JU@b8tk@g}J_j9hn3S=edwxHt$d3&A#C=r=7DYXMdHRZIb9l zO|Ujc*-sws5%=vULa_taGue?`+8ZGzOUPuzM~k*~U4c z%d!Ih9&?t7yJ0C=YEc^9(p9|}Bo&{$gd3;DRfW17DdPli8dF1Ta1WC#SL1E$(UjPq zhSg9qv|WPd=Emp7Kl{Z|SEkdiiYvZ6H&6BUFh3!tm&%Z&8R6H8_{o7W+IX5|T8_86 z@o<@=b=3iA!aB982t-CA`me6Jb9gtjn_tIGp~U(f;DDR!-2wNuoP%PfgR$AhnwQYK zHB@W_d-V(BzlfC9xeUj$r9oNqJH`q~@d!hhcqDaCvTNHB5O>V7bIna|E7VagK+9pj zvLRhYWcXM(-S1jgg=|yQa_3oa`-l9a^#Z3k4g0V=SCIPYR5TCEcc8jvVu6pAhi!9c zqPYdfTiMZyYp0rG?@cjZ>Dvgxdw>Z#PcfWU*wLsKgiT*TABNr;im6c0YXr$IQB=tJ z@9P<;%S|pN!of~Z&L5mMt=cKDEy$TQo%IB4{On5ry+2Bsi>6c+*=l~}h_q;+V?UTj z%>&Du&by*A+;8rjUdUKGM>AaOI9q6+tTHK+bn&TpD^K=e`)5Hp#}xHOgI|s~kE#_l zmJQnDr)+7bxg~uaxM#n-&ert*&iug0dJt5`Nx0NR^uto!7wgZWxxm^_Uw_MfO(*`? zx1xLs7r_(H8*wr8$&JP9S;N1=y;<4>J`p`qa0#yG`l>NiP43!WLJQEJJ;^;LOpJcM z&DE*$!`reiO?s1UT-eNI5oAkaxfOYkpEV=fXgOy>4|$>mqdRUb9(vr8(stSCSf-Cx zu!~IwVetu7%lVyse@QM);?gw$pG;nnJQuU_%UXOq?`&1VLrXoU?FrUn&Z(Q4e4Lp_ z$p9z?gg+)DQWU|i)7ij0_eR6BUCge2${HHEdE#!J_MHsEW@pgo)ZqMmjdKvH*ecJd zB{hjtqFZa3?pn@}*>)Gnb|HN|x4(M)q{6(@`9sPeX#Y1Wkx`tsvd%k?)QZX0f5z*p zD$Gre`~uW7v=Oy7Y8b3Xj8$zrst90-ihGuA-1tK5fwcMJ7m*IXghUJXN|GO;?oRQb zb1ChbW%=+j%B)5_pmWG8*CM8#G*QYkduC)2&Q%YhK zbAJ#_fqKx>Y-9b;t@2ivO3r~o$0RVZhBIZZ2v2@yvLM&CldyUMIkW;d`|>;yMlP32 zz|O=R(D=+E-tMZcSJd?P6pwAS$y5x~Jn*cD^p|g?RkkRYwelC95aE7OMiy26py6^S zvedMw+39&@PxO7|?!bhYhEFQj6(0Fby4O;*`6(1%{f~Q%3~P0=!osq{Gba6 z4rW3R$!<#g#WntsO4lP$j2H7tf3Zx039{u?_wC{Xw5?SB@rVyDtB$@t$(LjP$j^-| zLymN!+xOrv*o;5BKofRkMl{6m;D_u_Y@aE)9F)>Z%_y>;_*vvBm?ld*-RGs%@{ntq zlfB^Oq-qtn$D0UZ_amfp#I`k>ai?Y*kJ>Njv8I~`!lS%d2_2^#EkTwWPqOgk-kfes zb+cc#?IDNy#28DdT^XqEXPk4}3ST z*63!`NGZu^)W^~zL$7qgYile86-OW3W*|`QKe-qj4s)dLPQh$@f_QVTMSUOE!fgY& zlJK-%;#oyc^-NKXZFNffq_0X_!M=>N;p$GtM@+7J~>Hyo_RgWTP7}KF}bD7pk7NNjSK!?=ZrR|$Tkdw zc$G6`TW}G$s^7AmUYp6bRDvFfX0>d=KwWKfd5QYFAk1R+zWf)N)9pCt!~K#fgEs^W zyX>zj@G+Uz^ruITYU7(*l%}{>0IJqZ7t6m!e>Hyi#N^Q)3s=jWlZ*a^4mUhpv~e^x zax^h?c_VtTbmu;rs9J^DCZoZq0sP_M#bi-j!%z5M9WhEZM&KYnMDGZF!0||oD-T=? zXeLq%JU-cu7hJ6th_c$aPx7m7vZt<&J&1WHn348}h3;Tv8E+iJm5X;aOgC@vU!gaK zvombQeUl;b2t!{GkODKlyMMLE8?%YXGu_er72!!l4$?=js^8wuI(jMs^t}_Od~}k2lx)*bsL;;U>YU%!=terN&tD_}UaB0q z1O4st=G}%xk5wOh4H9CdF!)UXgRX_JjLGQ)yCk>r;d-y(m-Q(5;rsD!ZMCBnEz`Jh zPYdHpWjDc*^;_rgRxA}%yf-<1-BEXc(qa-luU7@k(#z*ztRPp3S@HfPaacQ`xo@80 z9Fk!@;9Tf%b;2Cy__>q!wMe}Atn^|m-l_K>ZFRy{V!BL1H{A@m_8iou!9L8bPeu>l zjBhcQz_DGg=6ao7L{d^l!NTMg(VEO6rkZ z0cpGD_53MR^OC6+Oo$jAfb+>Ns$Ez014ZTPtEidDwHHZb@9`o>?cY^XvzL)60}&_5 z6`YKF+72`XH3WfV%th}Qz2)I-7X|yju5G+eFB|cGmN=cjBdOHvfzOX;i*>-C3kh#i zK_&v)Z`J(pn{~Y7z_qcqy0)@mziDQyH=iVf+c{&>N!z=6WVX&KrJByoNH)7W1GSvKqV(72}HqWy!JY|YJltX=9|IB}xeR5aF^WUFtk{D63KKT6b?2}il zB<9rylcg3fp`Kozl{UPhTW0u&ugx_lee;iv*fXmAn6KvCc7^tR%|l|rtp=8_N_X5j z;|!BSjGs4!*fbN^9+rwP4g@X?GhCI?qH1lrY)JyIw%cjuu7UfSr>CTNYgH9_^v_RP z#@{t83_x~pAS9Hx5b|q<59{TQ3CXSpm?}nDq&{W z1szdGP3-6c`dF(&~WO~h_vh^VtDpVkM-KSs!aovrL4&L9afzA z4v5+8DxXyMHA3~OvFrJv$&Aavp9rRUgI1_vB>&X9UsQ%bk+X~5orY;qf^>C>@e8rj zG705_G`DpdrMrSrBhQ$Y*Ef*F**fBEsd0ujn{j(htp%rEhvkcNPzaEg2P`M?vC&(z zl#5D>)Je5$C-F4}1Ja@U#Rf=z5j~v8BwwU=TP-m}XDISA%fhPmSa4UfjPH0hUjuUF zGyiYX!sfsjYcJ8NNIw=IwI<3zA}6tAB`E{LLPOw)Gs93D2)cz8Kz(k^jK2)?{nVcy0ndT=+_uO z*3~L^R8=CrNtQAI^1sg}q`;HCr~i5bQ!&q2T7>_JY%UejIsmbssqNaI?@&_zng}A# z;=nfV-@i>9<|{x&=6UYy@4Sf}LKm$C)eaR}np2=^GN_L#Fh=?Z%WR9Q-N{fy?J++k zxb<-EV5y_1`hxCIw_v#8zukS@aE)_uO|l?w1%g*`11TQ-#yY``SHlNqQs_Z&+sJ%! zWVj}1ZLzFg?cqeZ%&&g+huDzmXXLff&35&#OMiaIYC0E*t_6_|hXy@ulbGX4O}ubD zoAn7++{*olQCZrAXM?qRz;|qKK=Q)l-d!_z`cr)O;WVJ>uxJO+=%XRVo3<+C-B^zx zE<3^fvnNoTX%a8=2gh(L`TOr{&0X+vM6FtgmmU!2pDYV9CC-}WMNjQno$4KeTY}0$ z9OVSaT3p+~?BN-O-C?5bATx!x3$`c|k}fqJ!QCb;iuTlqi3FQru&#wEYK=YgoUW1y zm3YQljNujSXi;4peGj5piLR)AVdt**gTTY(-yfFtGUPNF)qxaZ`-x6kRxh@`{nFYT zPh68bQ4QhhgSE;3${4aK4@t%@H^^HyPhtq06}^^MK92_nnqb~rfTlMnF8TtQV-BTw z#xeh~3lb?y{b$H)BmG(Oz9~=+u~TAd6SLKW#S$?la%tiePZJ52a2#VKvLd7pN+W7` zU1_l!u~(?5vOBg-gm@rwr|`9iBfT4{W|dwdZzV5~_ibme@bv@CO4?RCT|%BF_3kpO z#Ryq8afw|2#Dr-nN}ZC98M=hBxpPH?_V#@Y$2O;dI#FOe-$4OxuB85qw-h$O6{E*9P4jwWJpSO<~~9)`>UTQjU?aW?_iw3hN$l71|;Qz*00i=5#x4a zQzrJ^zLTHA#*V>H*tvlMuZXLOW4e-@Yeqwb&O~YReUFMG@x=aga;H`sK#qn3P>e7h zj-Ed%>+csa^c(O}Q!?l9i7ff7DzufLf@_1#dbW0eza_l1xa~{H!!wiKs?s3i2^38N z>|KLH&a%11fLCPfjhd!&EGQy?f$x{6YlLKN^IEo+ur@?HWsml0Ums9e+|T|^B|Y)K zPkglX8`o0%J(d+BREQ!Jw?_%yL|TpL4xa}#NhwU8<8Ww`4Td^d7?LJJaloj7vQTtR ze~9jfHy(sl?&vrDkZx*0+kYlA_A{!6K;c4g*Hcs5cQr_&ML$*gXUO=H1rWdAm!3C`xQC-3=bY^2$T^;Ra2eS& zHANSD&a^|zV{eHe!jva+!PIY07-Hd_pxP6al88+1#Gyl-1}DylI&L8G>4~{xDm!Fv zH*}+)L46jZM?uBS{LYITCc-{x4QV%yO)5E&VC|_^*ELr_t#b)8V zOS4-E$1Gz*BoT$GJA`9b^T9nD`&uhQLdJblu#5Uj0}{}vIsJm3Z*Qi>4%`pIPeY(> z-^F{WKS+f2qb5!Kg?ALzLUav>hdU< zZe44(<%XYV;jwq^S@>4C3t`cqprSD4Ztn4GUzU$Zf}RmCl&=Vjfm%51USSz0yc?Ni zHab>T`G%kbm?eMij8eKYzJ1rmTST*S-U_!s-bf^BSx9RZd43A9JrYtzVNjp*#xJ5N zh2!yt>9N-PFHljGj|l|LIEfOz-&QLRcNu^ z(nM(@U%qUqHebtG)7yY!SV%2DZj@o*PjG_DF#3m9-siSzMnW3I0&yQK>;~9Ay(OHP zo6Cu%o;b0GS=V(HEh9WZy0V~x&j3=}5MeE4l{ANxyZ!_@tf=0hf8|xh^0zhV5Yz`? zQ4gvl^}jBH)Xg4L{e!!`U&K$JS>*=p>?Y9dv(8~xz>po2R8K+S7aL z|1cWz1{~iwRLHIvJ1I(rj?>>yy;v(sxJvZG0Z&r-jssupz1b!>v=~qYjqwGFQRQJ+t6Se| zI}3^>H-Sb5y#zIOzeQ3ez6|4j*X0Wtbm_2b&ble}Py-MqU>LaL24M0sg`!cbB0j3j zn%t@1M2hK?RYotiHyFYqu=GCUD+Kf=u>BS@PNCX!HUAAh>;ix&%9Zm1Jc2k2&RC=@0T{ z+b1OadAO3+*QAyv+^^mdPq@cI;%m1AJ@prfc<)k-dqQq)^RG?bF?8U^o@1bF1d2rL z02yf?$0D2`b=lgZ`~UR$Q%ASE94=(`R(CF}w^yQ@aygOA6@7F2x(9A0g@a%gk0oF&lv4+0NB@7Vg$BY&P35*lCpu5RGthSJ$i#d(2Y<1- z=@Y+NJtH%l_JJvtV7%gUFio#G0C!b&pR4*^3*^Luel~fA5q-oL)Q62h@uBuYInF6? z(1+Q5V=z=5oo9u!*|H#x%SGAdZ9p`|8VhwwFrbU`aCBllwJC3sBEL=?EIh&T3!2l{ z;5#9;5E=QC-hi@lCVtT$RIhe>lCL%ULTZ|snwu^c<+E7-E@8X8bQ;0nKGpVzEl9s?LpXtlD|vBftJDkZ#6=#OCM~NZwvOtA z73`4nKk01Y=r&x>~b&*$2b=`WmqEdR1oG)AoJafcN-oM{_@kKz-Xqbwb zVdX8m@%Yt~J2OH3chCL%ssyW@4JYC$_u>+b7`#R@nK>RHO5b453Czz;VCSBX=^|{t z0CRYew+Q+1iNbNe6UnvP?Q64u)oFMD|Ds#<+WId?V`F_At|^uJ>G`e(A+%`bP0uZkp=Y!(q2OCZ=e^&=Xb!E2qg<`m0t!m zA35)~@?cr6vH>oNy&w!CoeS9?#elw|s`m~l)e<%*D{x*9s~?g>_XKThl( z^X@j`F5rZO>Gi*@(=LSkkmp3jdtle@+c8%`nOPB?mvqqwJ2>lIFM&P@BtQ~-?Q2#JuI?FoZa;?_raQMxov~r%{e~cR#+e}1cO1=s+(~$F1;hg(2DFiqUo%;ae3;c zeAUC{$=*vXD$lK89SyXa5&AcW*l;LiIeZcv;~(I7*8|9b@`T*gxv@AY4~sc{7uhIo z*+C*s50K8|l%|bEc7E`9)g=&S9F1rI?DI`S(_G$i&e9-$YTFRO&R&9?Vkgub7lIwg zP3czd-w@rP)$jD+z+^$`P(v>oG+8y6YzI8^8FRHD#S92$`l_ZWp}+9;8x{}C`rkU$3I%dkA&4(784RAM|~jq;MZL8JV~ zdI?b1ct50hATNbL2+EPgMEBFZumN*6b9PRmYkvg)k&nyWQCmwKWJma5?sOc>PY0N>lLX1tE~)zsLq;44 zZp~JSZrD!glu%j2E1!}4QIle?!BV|e0N@HFC_s2**Dpi+iZ`^`cG-JRO3G-QI@^2gb|ux2!f|h}Uud8s)4N)|Dc|Yn`fXi=KTpH3gVBap{;+Sj3tCsc9w`HIEax zRc1mZC1g&YRAZPF)!lGQakDI9SW+4%GbVkLZNEP24~gGxQrh-z;Dx%@RSruWKS3Y4IIOTRkl`ynQ;L3J7#n z2lOJ`NO~tdUg=?&@mfI=iW>lC^)(t^T>0Tw>7!7Qc74$l=V__uJpztSivV|;Y+K*X z?UB-NA)Gc>=99OdMg>xiHt{%kvoPy++MiO_1ZKITWi_kN*ZWssZ0OEH7C>gCd+178 zte$Hef_;TZq3)+`_F}^V73(kFxJoui#m8tm7FO9+D|HZ7%nF;2&Ifxx10Az4jap!( z&(^%QR2P|L7D29Ftdv>{Jozr;YwN>n;#70VI#N9fPxcxvQ3U0|`LQ+erOzr{(=}0X z@-GU`fNjGMow&2-nd8I3o}LDje196H5gz_8;30rOi2@>??N$5ZjGzyhdrTpOJ_h%H z1d_A->>9M0=5sIeoxxK#*Z|Kn^IdmZ+Hf?FL%}EXmr@pLslX_L5Jww4PyoGU^Wu6w z>zS>@c8?p2NU5OjJNTx zr<-{q#Y`_kN*A^W0R3TCM1|U9S&E3`N-%ti84?5scKmf$Ng++!qq$EddBCYyVWp1X zDX+fnkM}J~>ogfLcLU8SnQ1`1K1BU*3jIccn?Kx>ovK!yzG5N5tz+ZUz0Ix*4UL zNny<9g^)Ai|KqKpONQs5#C#uc1NEc-ho&j${nwjB;zo@mDU={Vyg;Eo_PXN*3k}H& zYR30~5XGaPzkMvD^gp>Z?)F|YC3R!((L*urV`Zu9nmR%wFS7@NzkmYHGFWg94K=%g z2Gsw5UDB;+`C;reyQ|2t!HsR?{>`l1w>?hk*b{4Y)o}1Gk%sc^hdjNGfK2z)s03dp z7Hm5#K!%klp5eab1HO5BfNU zmGaAV;eCKha}1M#^&Qq;u6=TfTds(ZX6o9|;ydLeQEe;F#x=k!sZJB8-n=p%-N7Z| zS-sm-UJmU3Db!hZ9CBPX$P|66H%W%}$}Yfh?X5Dw|7%!U-pLA59r=9Bw`I{vZ1YH; zvua!E;9B;*DAO+Bx95brT=$|MLwc4(91|r#dd8c18>A)xz5y%f{So2J`um=$BtM27 zFE$a$?q*3^?3NDZIq#{94#1J+s$w9+5kH1Z`dv?Kdzp% z{-{X@JTmMaXiv@D^Z)WjG|+?Jd*}b5PQ$>rXFjW%FNFj&|s zFzjN9%7kL7~jC_CWW>|Y`2^p+ zt09JfOShJduU=(tPTrXRtd_gavBnRvB~Y#fY=(r%fW@v?3ZPfYIB14$fXIIX zQfwLj9=lQABK8lPXIE#VdUFY>Imx{_(b0J1!cF~x)%v~wwpv*=r-bw(1kvmMpdW*; zzn=Y}deFVd9*RQTW`6E$^_JN+7XO3C*z^Kfa0f0H;QhQREJSA4-{;v5zxGM1+i8XT z5E9-RhZ%Judhzjkg4Y{TbJct9v6e2BuQgDN^sT-h3*n}}Z%V~3ixKD##~F24fh5X5 zM%2d+OQaJH4vC&0!HWlBFktsQ?mhg{(>}{kLHOhPtrYR2eowpi-flK&ea(|KB3d(Z zSqVfF9!UyHa9Rd|G5-X!c>{x(m#%I?1Q=0NXRI!ez2q8=i2>gHsEu3?F;@#wD(ILC z#tZmTjFnX}-oabpO~5+vg0QLTIcQRTK2w=#9gY@K>) z@2UgO8Vn?GNV(>75J>jPW3Gz?gErDKwzNYZ9=~YjFRuG;Oi5|%kd{K_Tkd;-WW^6B zIU#?0z4S?SqvZ^Q7d$_;s)bl;e)vT_O)1!n_$oKm?%{87&%ip89~4N-P@1?yl(=Mg z>p#bu*_G>IxfM5^h3oZ;M5$Gd}aA&vPCIR4+C>>*Ob+Bgj!%w@b^(XnJS>nM1@(8~i(HAj+ z`kMT0;yiu+IF>u<-i%k{MfGuAr@?Y1vV9%h4=XHdt59?gbZ8@qrk|JW!D~B28J3e| zDLGfa8JlD$MA?g&{ffS3M{EgC25)3sLc}5iNw%?8$cd!{fhG`Kmbr@oq1^`_;wcYE zc+Qv%-y^oXM>FgH0d4A{Fb!uw3PR)P-5}vth*y)KOz;k@G97EIiNMj#ipY#lMy@UN z9q(~}rynK4FH1QrZ!1Z@6C?sIsU)|JEwW)5eH;*3ptri2{|DQll@X5?`=up`<{Dm2 zPpdPkPKI|bCXhk_D{j>jDYFQt znWwCtjS|#iXn``x6wvj-4R2)+y*wmJscBi0omdENFb(t_XTalPERf}K?l&Y@ULC%_ zcB?PL1MmE2FTm}^+yl0O8mfVh<_~)$oDt)Lg-HVVA%37*Em_!x&HR)yl^GQ42S~zd zwe5zTeQqc2qWY_)Co0Y>)?+zc@F%)twec4LHLNb-Zx@)4kR_{0$QL^&_(s(4g53Za zxU;)tz)qUG+=vFVDU@Kq=WQXUP?ZDv%#DasvVR}tJQ%{IJnFNtYRfkXwCz)FXq1!1 zamkRzyIy+w^gmf`QEr%C3H+7$gx&~6s^?Zg9`Y5~gWSrSK1rd~#P`jd+Zq$|o|z$_t>1P};LJoU$W>W}eMfzu#QyLSkH+zJq+ zqc@*m(#qAIeiqI+#?wxQVP z2j=@e^fiq>`6vG>A3U%8(FL=(_q@>Q-hbZojv?aDq-LyKX;X2Iz?HhEDkk|{Ro8JA zMu=TI?R0V1$>VX0y~F|=IfvcZyQc~=_wPL=#2qd?R^8mJUVp``h+5%4FkVgl9a5UG zuiCT6AE2I9IvcR+gYh%mypma0oMI!^K^IkK8Q%`nRufl6nYo+r3Uuq*l#A9XlUf{4n(9b|5QC5U@soztW z_PVOA_4$^6#vkQ2dP=apEe`b63U@Zbl85_^)YE(qN|%~g)Q;0as#@CrsWT8m1jgk? z83ZC^#26gwaTtNB_NN#<&h8HC$M!)(aN|#ZFD34Kl{|jV{ti(cQ7@vd*Qwl9+i2Og z_vAdUw?75LP_4OCDi;{}_k0{mQhvmdM_J;qt&@r2iLJbaIC}f2h1&1h-$w*w$9Ma# zZl<8WcIM88ruhm}*z0pg^$Xn-uYToM=yVeB`&E$`=TCtD>T@Qn=Z%lA4fQfIsN5r* zJjYOCQhdr1@rG1nUGCoG@8m*rLQ$I$kZ5ly+ z1$UTwy-ER-+jM85@W#sdzlt4tY@>|uR+}w{-#1729d3Vk(l(yubFcmrjuQ!Qv5j?a z9>1)@rPpTlZft@pqTWbGnPT7O!=y)OueO#3VJ<^E2x_7T5wzwGY-+d$g!jq6s+3jF@o?`)la;`F*0{~&bm zRTH_`IK9;7vbLr~$7h6W|F53P6jizC6scKa^db}8;P-icY{oeSl)+?QD+sknI(P@) z8N0i&60fE8Z-;Q)xFqFQyLS3T%Ew;%jkBt!BLa0d7#jIvm|d{;^R9by@Bg;=MZl!D zH*`xiXm(Gb7brC)vB`>q{JV{I;9nY zX-Evuvx|#KP{@07VvmDNuw!tnEynnnLB9Xj*%Y+S$J|TGzF4%LVSS)MEz8;IBkt#m z(vbM+s&*S^>i6X)q&FE0kl4s^kVAs!^sn#E&eZC}j7M=PXyQFNO7tT98b*&j{&?fc)@^k7L>zB$wm;;$HZN*e!s zER#fiXkc^_ff@Zd6WCo(Kk$Tofjc_3DgXetb{cNE@6btqnnmUrQ4e2#O zNZ)TzWjHEJxr1#IBd_fy?^#c6sttL~x;pZ87mN@C3>2p6+?G5dBcV#hKX>z~{hwZ> zn*k3a_K#Gs{%l><2mM(+@YZknz54##W7E~uf3m7QQzk@RpX;mOe?A_ysh#;!l|9zB zaQgJG+iR3z8H%c8oVesqQHz3cMwEw^&?LxLj{Mb3LdmQUoSH|j{nibzZA3jEoB00A zWT1gC!TSdF$~7^lPw^g)X@Ot|x++)bXT46IfrCRmr5?BXQ0Z8X@&4{|UjY?Lqs_Emz%3C;Nt29n*8NROS$!)OVxzzvl`}r{oiu7Yv>*ni=q*=nrep_|nbJ+Knau@OlGc=t}mbmQmlCJ7pW`J+7~9I>9SyL_Yjtf@|D?;cHQG z-4(z6)bBpB@jS9S?X=r(15{ou<+FK)QC*eP1DZGG;|F?gvH#qi{U!&(y0wT0b$fqO z(IC8XU93m5?lwqM--KD2A$b@vf2j9u^bFt=xJnU%TJN+z&oYbWh5Tl3N9iW>QKlfC z!YgCz=TS>DL_1q)OuX7EOxf&vKRGeY!ru@pv%IU0x^-JR&p%~tU!J0!nyZ=1NM(;3 zB`-=kBk(py#UqmQ?CN|JCQ+~squ+e1R<~SIU%{?=!1Y zBqTkGvl+MDa%bJ$h}<7JU}C;VKeL`smq#>P+Q)LEYeyzeskv zN|N^sbM$s>aLH&zr%tdRs+lVhd3HKC+C6aL`4{aNCsI&x&mku&rzRO8M_~UiZ{_`6 z8s$x6)8`bx{D0-WXH-+&*Ds3tSP`+KAfOLTNA1PDc`hEP-p2nd`N{GW5*@s9V5aqs85{a{G;-fQl)XZ@`;=Ok|^ zH#M(2T$W+FdYKpGSCw2^mrx^{^X=S{ge)~Do^|FXN^f2BnqTmPR_n-Xo`ZG&LUY|9 zUpzeeq_csL>3*VpfqNY+(ya3P8ExbsYj=fx<0o2&od<#32Pe@yOs66rI$# zf(BqdKeR$pT$94;;NPpNI1}nKYpnoPJ*Yyv2LETEFnCxDNj@ThU|y%Gxh9UTg2`_l zRG2Db{$+WZkZ2HPC}~9!8$%UCc>-XcWklXPRYX;A!oa)U>0XO=w0uC465WZ#$fYbi zoIL^Qg+Cjw67E;AQeP=mYICF_^{;$pt5r?jmGHHn=baSg{+VRE!L?MFci1-XA2f=p zIWZA#j2m632;%sT`LO0#JMoZYrAmeHH$3!=1)F~iaYx728a~j|?Hp;@p_|ef4r5Fq zzkp0vdRFgV3nb}hKI)&3t~2M(ojq*Xa=~h+;KLfOy*drjr~W4A5UhKwl8{)Pe=TFT zG$`UIfbKcEP%U2{*5&yQv*~V)&ivM#cHC-uHopEdLJc7psJ2Vy-)RZGXoanRLFmz6 z?Oc2H(S2L5^;%WD1IJEGt(Nmg`-9X#^r=|aqsMvG2bHJFOl&-2X^>_AisXsKbC7sP z=%_Gx14b~!ZjXEKd1Uta%D~*j>^WsXy7-wpam7_zC2V@MG4EH&O7g=9TZZq44mDcY z8nH=t$F9<+tQhRktB!UiBKL3s*t3~NlNn*7u=j&KEC&Ne@+SY0gUQzPa%H5DWo9yC z)&!w-UUvS6AeW{$f4pmY*jZ_XOGc|QuZi{C%AKh7LcPF9Ic^cbGf+yV-83|gW0emhQT-Ly;O^CzjZ$yI$J&m#EL{C3`UEVDjx43El>4V;fv1ftvlHl6Yw8#OmnB zEDBTaW5D2V&D_^{RwcaOU}Tc1JI}^_w1&hFjL^KIo+XHtfGaYBe7w8@s9ch2g*_FoeD>!lO4D?ys za&J-LbLTzjy@FJwd0e!_yT^e-d@-Ny>~$PcauKH=kztk+lkBQ^^%HF)CAWP%$w!|L zeJlScS?rxwc?28NC?}NXYFOig;5h5l*%PI@^K4ZonaZm?E4Y(aNPpTzoj`OcOsy6j zzx-BuyC#gB?xY-94nb>Dzc&odJ7b4ZsjPgk23*@N4(J5wtxkP5%I=XcvYEfuA5;ge zXGn~+clQ?7aPnQS9&V3^oQbn?+ee?X^RH70Ao2@WAXk>Dslg zdi~qZPoqm%BK*mA+jO%RmJ8>`yA2X&(2YFs=Db)O4?WWI$POPozJ3A`^fcK$);m5~ zNkzEDO~27$X=Qfn3!$Y-p7waOy`wA0xlwn%mg*UIQD@;MTrwWF(m@^agj@*)aM^;F zQ}TpyjJCWHDV47)el5*1N#_CrE z{>kSjlvET*EY*N@6ZpCyi=K&@r4$fHdk;I?{w?QjWki4rY}JmD7~1i zus?UvxJ3LDSTrmXb!*9av!IE0IDbRO(vkEpbeXh-mR@3}n@)7RylRwRfqt>z};(m5xT+GsJ~E(>tz;g z{oOjeF{(+L>IaVt3Q2rjr=p|IA96pWVhTjy=KtXR??H zni5iXzB~%s?aHfg*os4qS1Hln-mwIxwiL4m(k6x=RU8#j`RAV4ziINeO-gk6H*^3Z zsGOieQVMj~IlOM&dMzhizdq(G-7~#JMSzGZ=O;XF@_g9H6-y1080Xg6@Uu~X@*enZ z0%$t>Kl%Ji#RbHXf1z6EedJP;$zRxdswX9H@}o8BwGY1-9>=8e9p?I;Lx1DuG$fw= z^wrTX!SVPG*otk_uscy6W1xEQIB@&xxDns%&$gf9MMq_(?c9ad&5XiBeY!98cWdq; zj)aH+#&}&ayzIfOhDcn~n?UV`wXDaL*r^88dJeEoR@<&B4s1GF@`8Q(K~AIw(a7i7 z(zbQYTpc$x(VCSs&R@hs{Zh*Wuelo0+3Xw*J>IBYsIl#Rf-|BT(GG|hkeLzlqCU~* zkLi@;A~cG^`xh+;vzhZ0kBX=>>3Pi|louZE0iW_b&G2(=1}zpUNXM6sC?fbitSb3QDR)AH3i#7qDy*SdrXHxCTEzX=)WX zv>MuYwa}0>$z7)w+%BAH6~PF^*d-t`o8tY^7?_;j$Rhz%$I58-*TU_Vh?je5FLrLS<+`=Ouh~ zj;IqeUxPa799nZ`G)*I^LROo-#jE8VH%E;-dhLiW1iXnx5E&J80WZF;r#DHDaNRq- zy0J~OBI@`#vBTfl$$mnyD(n*DooaIB(sKBZh3@jExVwDmMTH-$^1}I+B;igI_|+fv zjjNk{Rbu@i2d@5$*8KkXQ0_!!K<2IyNe3ES2{fH3?QO6BK2tCEQ*T0~$j15+p^vhN z$;p~W>Ja8bNKFmWb;2%U7uUPy5SP*Ug7B#8>^2f`jZ&OPL!AMMJ1jfVx~{n~7Nz&N z52%}&-zOn`_6MP)prqv(e4(qJ%+C`j$u|s)qIS-rz%Lta^U;dZ%D0n*fjJV0*1k>t z;apghP>7>C=@{qIUu8*X*UPV^86Q#BFmWKH&GL?y@h^E^JPOS{#^3s3vj)>sgGYAa zpAMZ`vb%}&eui1qx9ns-lhO|~Z;YrHbsW7;@D8uVDGZ=EO67V@#t@rJTOOe_Noanu zcZ#(~9B^wS_yes-!P;BVDqGP~itFmwp9e#<*|VROjxCgNv*KGYwb}T!QLZ{MFhOIl z32Bg+HDf5qf`<4a#Nk8&7bOmr1_hFC@z>e0gtBQ9QZBw;g3p5G;$R&asJzT0h;`j? zV>(LjI@qDKyKq@zEvPoJ-5ZN>;zcCF`zv~!YfR&QJ9~h4LjSFl9+NcJj!I1KX2fX` zfscDtC=zYn<`TY$qrDk`GM>`^;$AjXQGA>@&!zM@d=45u32K!1q+4B+`( zq$(x*wPy22VT}A5D1ZKu82^`A&~DfKRtDiVqM0e@gmagsx=BEs^W3rNi?1Ij52->V z`uWfXaci#7>M!(Jr_BEJRMDy@t=A4Z&?gqWB=34a9@|kyQogTeB!R8hb-YWSWZY-# zNvsBEh-9p!Y8#b%U3aYVqaNky&emx=?)y5gM4jffQv|8kps6r+Igx>C`ESI_&|K11 z_@9GGxHwvXT>nkNDetg$ndv|c62&2<2}fznMCrYBpIr*FRw~=LfL9siffwtgMx_@b z4y__?(JqC$;4ZD(bqUnr_5UcClD?rclDso@_e7}^KgE}7+zS;m97@2>GANJtDPI~l zNnm{KxJ=+~O#of|$d%@fYr%sx_+GtvBAp8=7PrQn+z2OWJCBw#B4C;^uKPEGq zgD>5Il<-W^2QegmjU(<=E&^@vE^Urg6dw+BLuK8=;>@=auq!E|?_Y`A`_xf|d1HEu z{z~{DrBl)nTQTFGgvpiMtdjN}=j$JrgOf+O0&Y;858zLrHJt2#C>WNCJfAw}> zBH4oLyBo8VA-38zhqe=XyGpGe)}vTl_t%*g3z-9vFQU|Ac#@awSgT4SZT=A&yPO!@ z6)eW~J^dym0k2LX!nX2~8y}Fq?Cxx_@9fwDOETHp{9Au;MzI%}PJ)#M51SKct2ZM% zuk?pMwqwDT)Q?AB>Y@3>1@-97pYoyPTC_c%InNsd>JiYLL1YZRBfVVMa_!4hsATYe4Vr z4s&klwkoT=pUvGxk10iJ%NzTp*Dc@Lh65Jx12c-bL(n_77nQgcQ!D*~)KqHgru;?r z*3~n7mOSY~@I-zqo@DQ&y5*o{xt*ian+MVX7;R|=ypdRIaw^{Y(R&0WjjS*uthXfq zt)6j$%fX^YduG@+SMyPFahf8%iGTFQyZxfE9$#!7v9>kE#h)Jf`IcHX4G&3)ygRAa zm_FwiXAnb;CZj0k;LUf@0ODqH`uizp#jV~t`Me7@0{ckYN^kNBe5W;tz7&B`A6pZn z`7df&v>oGh`0GFC3k_J@1Y7X+pkfJYR;kXfynWyHEBfEwz%_lyAj(=Z3G%?7Cwk8o za5n~L23^t7YRAhQLv4M1xV;Rld#ZwYX6zc$E71R)R%Q+g8t|R_r}@^~ZX`T3xtrW9 z*4Tum8pLVFlZQU?t=}6$RuxTLw0*Vlx$joLT?l!P+%vIc&0mG zEBG3WjIUFVo_xoGmjQAG4g9<-O6>+GshE4P)dtN68AtI2mtqEv}Fg7_tJ zhm`KpX31w&8snM6rU?=^A`frVm%+D%K%>}+P`=m7d3m?mGh>v|Yd0By(_Mqn8f;s} z7kSOAEIT~AIz2SW+HN$>jetL}^agN8_g}0ioUcpvMxW$dcB_NG=rPpCuV*Q-u;&G) zD=(Y6TPp`Jt1wW=YY~_n%$douYbm$$r^_EGyJ2a9(26(nwKHg?-Y5@a8i=ljMG!G- zHc<02+WRJ=EHA!*5tXMlUhDU=gZcNMm>0=F+H1s@%y``U22yFe$y4au5>F z#v92$GrP6*eh=4j(vrfibZfEf5;F>?%luSjzLqwK&OpNlFtPRcrBQcEIw~za$0OAP zuM+&df2FixTVKlt#H&Q!ckv}x)@5d3)!Op^-hfyE^0Ysz z#~97}KPZv`f6Rmc^>nSz7rfv}dKp>ty{!W$PYf1dgh9W2($CL$0~?Q~i9p+Q+2inc zNiuwa!b$xw*NdYP$w!#8fS2Yh80Vo*vGF-z?u>2XTzuc;a{u1T0=Fay>H#l=QC3&m zSn)P=%ON-Ti`X%JTXE&@9-rT0^noyuN~Uzwz{7{=Jwq?|K-v0V`~#(Kr!;BG1*%~M zo|IkelRvx9WYN7(+y5cGKs%;Nvg?pnnCXKYiNh5@6eU0XD%)I{J=oBHC>?PQin(hd zDQbLr;Z$qEKPkYj;v*6i0yTHdw+xeP?6B5(4qbScca$MXA?bMXU)bm?>0s?e*PPnj zP*Ep<89jO6eu@!E*Lnf`&g+z(cRObF_2ix5B7oz%ZYb?kVwxV2Q*gO!`K|_)?@Ojt z11uWHgO%A943dIw1|$;p{2F(pfd_VlVH5$g_2?(1;YqayBDc8t6H^&j!x>hyB-^B$GJ~6aLpYqIJnQpLvsllb%8AtYwJ1aI#!^4W&F;f=0(cttR{p3Dcc5XA_8xz22kZuj|F)3a(cn!FQZ`SJHwR(d?&^o zx>@)S=`Ga}ciB5dSZn7;!?w5ojaU_VVxF&y=OaY&@=bWNwQt$dkXrq*!_HR#7aV8E zB{!J|eF{?DIV1e>P*Rm^&f$-VK9745J`A6+qCtLKZ{9VBIMSZt?D7YoOi7wisd)-V z=O~Y{q5q^17reP(y9@1j!U;DT3px9oc@BP-);&=mV!<{spNz|HwS59g)MQdz~ts zgtM3|E$i2lQUq>b?51c}=AviSJ<@x05RH@`3YXaFqUZu~E79YQTbp^Wu(n{v`S!_X zK~MKmKUiH={ToP*6m35p8mb;NG|MW}9Ys19Y{bf{n(SEZTw?VGO91?~Ob-=0{`X!0 zyInj6auXr%gRSa&&6W-^NBg!VbOF1Ne(@y<8O@h7*Y4_p&YGS>Wff2Y{?Gg zk*s9QU6Y!EgS^E#n1kb6?@Ya7+b=ZDBXYi2HYrN(geUJlct=snK;5dm=U2xqlR?(!Z%}%)(>K~8od&QTH$bm9D;`E# zYU?KP-CE?q?XM@+PngFrymT6{ETxQqVMzR-MatIh0`4&Ol{y+TB6R7T;4w+OWA=^+ z?Ov#vDwyZe;4fv5;0>7kS%UP9QY(rbt0Skmg3yBJ5Crc2AgSVy+qgk>Mt7ggjPkLA zuyV$77wz5@*viy0x5WlkUKNGmgF+QSY#hS-HzImh7Z#OT%8Hg%E!}FID>E_(mQ4n7 zr57De>N-&g4~$;M(xvX)d?hLVZhdCMDtVcUyPsTUABl$4P}cbS~KT~sDGA&dcJ=BYB!iz_g}Cj2vrIlH1?-Y1$ui0c&f6Ie7Nd`W zMBh5`$R!)ppsCl!@;D`~waO|X^Y?_zCP(6*7a4zcn+|V0dEh$qGb`^_4JaWDS55<9 zu;Iyruqjdtf5UB(VHaL}h47ORq&|}k#d?ptdp}Ek!XzIo&%E4;rIFcqj$R1TVrZo@&X`i#8m5a=n}|z4-St8jVThMf1d865<0r> zfwJ2?(@ZfTrp0EQYqbpE%9j%;@^9)%6;cwb?3+`Y>#4F1X`UT|{T&B-Q+$@k3PFZ6 z)}~uPc@xSRxYk#gbO>KuT-NA6Sr$YuE+Uq$yg$kdlHc)60C8N&(EZrc&sx=NUg}Ct74Z0=b{YEsE?U&D3UhQ{S-uknsk_kY;GtkslJsCr# z8;9QFAH3gDC%Hh2lMriabDe`00H2~7s!=__n-o|cbq}q&wH*-#r$?Jv zjb-~~U6uE&H!bDGy55lZAtXRI!9C@Ni%g5VkA41e4@zpn#bX-KxQ(Q}-MJsE7c<<& z0>&*;6gPIX7Wck&37eG+$2*j$Twyd#dE4r<{a35J$yeU}tuvyJ#)RwnU%%xzQT&vg zAtja;uvjP^u&nXG=E2_J-bU{FoA97?O>32gv7L;MA3r{uIQv$c^rf@o!Xy9UVLl;($5~f+{0#S0f$beqOmk9)4rRZK$_BG(p`Gm?hq4K= z`q`@3nfF?&S?({ZN^1%@3OGhD(>3vk7LA764My#P`Dr;oyd5}?#Jo&b@O4=ltt?Ec z0G(Y1h)nExW0N6SACXsX(8KFUWyskfC{L76pZoT+Zng24C?5)U)@iz?{3s$AY#4pQ z0%h0OImqUldUsDJ!IWxV=1+u77*yUXf|$G8)CLyfK_iw%l~umeT~7(wzdUE>jATIJ zc@GmC+}N!J7Lc;=rkRj`A^6qxKL=yi#ry`9%u{U)H!Bl49XRq*U|Nu}i5(q+U~oJl zY3ox5Ti=k@_~|mYg(C|`?szmqQvIL#A7To@+uy_*{p8;Gr2Kof@mTX_`58J9R%&~b zv`aeUv~AS5IOufK?5A^*%ObAB-)snR4Q~t-~*jglH7)? zMD?@!3;B(h3qb~|d5$!CV(eU1sQ(=q6RmNkD-r&=@(iL!wX}F6JETUsg`#+?<7Si+ zwoP#()hq+A3DB8{m;eaLFj zl40KTJ^1*P?X_tgFN(9+0E<{+=FF{yBY260NH(IOCl~!lk$44qF9!$aGL6A<1ijL2 zBf}B+b@IWoG0#D4l7i?9qQ*E`$ARB((dxj4{*ps}=r%tg3@@p(MKmexD(wGVen~1( zhiFRCe9#G(;xkljU~?;^r^5GQz(@;WAioQ{qh@F10a%m}B(Y?xp#AHy0W8Ua_kP@! zJ)u{_G{qwcX9)?3VmJ=;%luJ4{a?e?Czey4DX-sb^N+h;jl~#MGQDZ)Y#uilcxLM2 zU)zJMvTzkaCKmfn=IXui66q*q6X?F4(;70QKCS}(h13+tF#e6+{idcra5PPl>-i`| zkilQikdv6)@pS(OrP){u##m%9QCOyItg)FIW<2)v zkxL*~Oe*(={_Jc=*K{M)R_o;Rap${iSJ*Cxs1C3&P326eR0suqcs+XJ-B7s@YNueJ zl9!4T`^#Shj5>qAiUv6OOA)>gWsH|oA3JzWO11^6k**(JvKcv0z=Ar&ptrYV$~v`$ zRp|w*+AJ4(>efq*z#pab10qY?H@eqzZyh5827`1x*Ql6kgr3^ydP9mz!Z7l7LaNT> zyXvQ~T0*^LgqEe_?B9fa+Pi2_RvjT(9l7>s(u7>N!NSO0XJSI|EPwb2Z;PGrL67Bo zLN2BRQnZh5=>J)|=-xC^4U1Mk`pF<5JjcE1@+mh7=;~t=4)s#wlY>VDbY1UDOLC#q zymH)CByuO54F)(~3hS81T<`CHoogfnbFJ(wu2N2jvdcrgv2t!sn5$Aa4oI98kc-~N zO6!l4uG8M&??|+u6a6>dlUU3UBL=dK+6EFZv99yFmIWNWr&6evF4%h{)rP(iw9?T^ zA1UbcZFv`wgv8>iNaN{26JarCy3!ZT%WU~^k0u{Y0zMkuPP#{Wsoa~MKjby>Wl^@g z&2Q<}080VeeEsSj4}79aTh;H|V#_`qmG54byZv8TrZ=j_qsGIM-U!79jK+VOYk86U z&a*2_S4uF7q%Nm(ccvz}zTkZ`s4e8s3dtRvcbQF4m>7&gW*h6zPd$Otnw7cI!w8{- z>_>qMN7QdKR9}q}9k5npg5?JOlk(!-;5BCDq^-SAJ%d4fLe)04zjB}Wz2w-h|JTV& zEI@G=2Oe>`4Y-!6nV~rkNLEa3A6G$*$&~WMCTiyG{xILRM)*r1Q^E&@+%Lnee?XIB zO(JF+7ccDI{KBSsM~2tjanu2r0E;^we?NLKox`H@m~y5Y;hg&7r+vn-WIE2=;9F8$ zVNYbtS`e>=O|IRc6Gk$3WSEc)u>@Q+V-Kp}3|h-|(Tm!1sNOshCCF&2#P``1jI;Ez z-BnBmI0iWG7J!|t+M46z{pdfrY4oyZT|b!b@z}kzG8^EZ8f=ZazDuthlgjIsBFL0g$;eLsYXGu)kMt~ z!OhcuZbz5fd@D!V30B&$+lr!H8f_LXnONaQe;QQ40|yXJgZ11ax$ar+1$e~5k$6?c zl*1_l99?C}XZ;xb1iC+Y(vkvxbmh<;1e~#UBYN*KdFNJA32~aUjZX%*YRC4-6*gBA z8l4AL<%l$b-FBC@FGbo1j3CH%LDKUv=Y*bXI5x>k~M1T*FOmFIlAUDL_laa)N z^;%26*(l#iJL>{V=Fit@zBiXSmQz2`Q#Tvi>jNx#Oyys}Isb@s{BxT1uQCXEc0pskCc$;$iC-J# z?rHIX%1KO2_QLMf@&07t{F+qlT&^+nL^Lna)!Xf5)OOf5zcBCqIg;vyxGQj+x&Fm* z9rlr;tIJ5@P3icyz|Vmad~dd~*Pyw^M{8?(9taw3UrSv0e6K#TW>p7rx2PTu8Yl5q zb2!!Nw820{L3v#2?*fjTq`{*3O9@E*7P1Rnlifuz>BXw9{z~)K)%Klk!mPSP+Gowy z(;GD!OGu+N4i6y3cJ~Blqx|COCz2vL zbPMUEnz`Zx3z|=ki22fEfeTjgkBb$r=bup%o^JfsScqT3ucTHjWSBwX!e{L1EwTG! zNS;C+8a+%lna0389*M@8E`P)i^(3H6D{*XEdExK;0arOPa?IdH58uSaJA=2j&uAO^ zez#q$aQ`kFw6qss`4-CbTbfMFEUVD6+is3WcP}KF7Iqrb5>jlLyTx5TqV95{)V4G2 znm!WtpDaMQfP>7Wj9(*BHD8JK8ky(kkeu4_^XAV7WFTAgw~l_btxY zQ?%48Mk84TUE^`55`1G2!@dI()SlJxjTffgjV zB!B&5=c%ndV+y3QDPfK;`yJIMEwC8XU`&DYgF8@+DmaUM>fH-CP7OuP*YrzLkZx_R zLNtFh(rpTSKrY%-G<9d}08>m@=aEl1(>z;v(asqhot*wjOzbXA=9hVnY?EHz4(&cq z&^21KSHu=-3Z*vw=+R~ZenC!?ApbMPW!;}A^0|)j{7sry_^*!i>6-r3+qKW_YiD2Q zU*MO@EjgDbVxODdZ70zdw!p4*+UMJvX1wXJcf*e+Xsgk0huq)9dwG6P!Lb$Nwk%5t zst)afC`aC(DJqmU;58Oi14u^?6avy8>7#5KjD!l$`(|>WM8QnR-g`jAnSmXy=+PEp z)vuu3dY>9xpFd*^2=Rhp*_zyf^i;Q@P=;l+2B;`jX;a$o3TryoEneg9A{f5^iiD<9 zUfUYf4RAo0wBpNiI`fsBxsY5rshbb#hK6-YwH{{EQCq0UxjxVFePx%$m1mipK$|eF zaZB?vs$SUKQMJIy7wda-!y-kbHbA zQmt;9y^N)eB|U=H1j;F9NzW2an{8h~*`y()E6gJ6?n-T=VD%8FR6<;pqf%6)k~B&n zvfzfx=l_1?*RQx+FIex)Vhy{5>3g$Pw#51ZipWN*?okYu_ei;rl(uP}LlHt^p&afeAvhT2kr!Gnr0-#BWam*8=mu*4X#z9e z>)d52Ghk^WoXN~vW>L1{(lIEdVx2%pZiZ$x?@-KF8q6V8Evq5J^f;rzIFfHzrm|$r* z;aV!afFtFuaP!N#ej&0is2RrU%=+SZf^mDo)TYtg1rLEPS49^KqeS6GF^*bpZ8Kq8 zazck-r5LQW(nBN{e&l2;OC2btw7WhjML#uj{iPs(F+TFr|Tz6|Uor81OK zr%U0@d?hXTgF8Y)o|(DLryaO+x$3S1WyWn1fGPiZl}X>k2oM-cE&)-V&Kf`n9wR=Cj}n&;ijTpzaN*TrL1C+y1j z-QT?WH2a2JELoOPuzhJ`IAJuXvIqGv`m9y_uW7gHbP!tE0F5L?3o{lsPq7s}u9e=m zYq_%(#qN~nkUPMPTsev_(}Aktj^l-JG<)Q&{=S%HcpjI{lv0i4YSMF;reA|3lhUz2 z1(erYH_rM7v4ftDrN|b=R;ZgyyVpcFBls194+1A}XUg?zq}^}{Sy{-HPE%NxMiUHb zClo*(jK+*6vI?IyxxM4xWuIG7E$m8Iqv9QQ_W7jx>)R%OPWOGWi`nnE#{QGZ*0tX| z1uvt_h@L=Tn3awU1QA{d23%4X{6O%@F(G=fXD#YPs)LMb{L!kyd!0JbZALZeI^&|G z(fm(yi%2ddR~Rcb$NhT4DU{li0TyQ`>q!7P>n5{2=QORfEznhb$-DE$CoMevlLIkQ z4UKo9MEKu2(PV7^nJlrDOx-ajyNsjnC@+L96mXDi#g?UO_l%+)361?@?iC5gK}A5< z-zvi|`ul})jeTP+rwi!c-i_89vqmAK_4AMt9hD~vW`DD_n*I4;1Gh0gu_0lgdbPv< z1#yVO>ZgxTmumv<9vpaZx1tHx2#!S@MTm;WL6wN}V&ry|X1>c1t?qF{0UaULvK=?z z0}>4p44oFgiBu*VYmP0oS>T5J=vTrEC?x{jva@ZQ2UFCOp`~o5W3D#}y(WOd%<0N? zcTOi<>mV56?k+^E58=qZ5HjK{T^9ZGdv3G~ePPfd`~dG1H9yl`TW(C^`#&t)$2gcm zd^B{gGL>FG_B3E)aU@qUU>$&By=R|Z9p()CreEi?)FFTVs?qJ!i=r83zN7-<>XVJK zxu#{&KyxKOI%xzgw&5O}!V0rs)*Bl88qLaVc1B9^`!J#q@cDL<+`XKpNPl0x` z{|V@rnDp-YTwMg+C}nP*VuDQdX>sQTF^x8ZRI%|GPie#`W~9PN1|yQiskpsZAyEzr zsq`iTQ24(*(7#+vs1r}``@W_$`u1cfj#fAsT54ojbjtGPzi0bp5gs};x7?#mpng2c z-6?-QYc~0^49Lu63RwjCW_!MaW|;{nP}PNrsr>U>O#niOaMMT7xW`KQEfyei5pbLW zgXW{u(Xv&(E-5Oh#116+GsSSC87J4!jFZP;x&a<^Ig2*N(_ZD+KiirxIIm;*Z&I=( z&)Y&~uwVs#QjrE=BGV~Z-d>GguVh>a#LsC;@hFhg2!_55z`#c;*J1o|x@bK)=E|>( z#rufQjPYX*fRUJ>r10>a3v=@3#<=_C(YkC77tVp-LKYc_pEkNxE%3v^7aDPgSW$lb z2N?8yIS&Hn5Z-qEr0{RIOCxv%W2l^rEkG47_et?#kTS3#6V+iBmjs>jZXak%`P zQ7!+f8siDdMFX|5KaE$%q(18fk9~g&eqgc(i|kA)%LF~#Wj-eZyrMi6?3sATW4BKw z*pkfD`we6{Sn;Ocad`j!YA;{p%cI~b6|bxCf0#JC4+UQR^iYBqVkpO`%fqCP5vGCv zE;CE1g-UZuc2(+OInh3B1~zgtWtRPRhLSfK-F(0y`Ks~S#>BNIS(+^4Py6s?Mr9*# zybaq&55OlZNDSEjDg@4WF2-@6oiS^Sz&_GT1!c+d;GL}F^ymqLX;@aK#n9caV3YCdgVWX?l2Bw0VCVd0QN0WyFI$T5)-Ak zhLZQO8H&BCVW_-==klA0E%^+tQHcZDa90zjqm^yI(ou)}Nv7k&wO#`I=uCVI5TO0z z|NER%JLEw@8e*r8f$xSkEy1$8^Pzs3iDta)Si{^-LH?rT`DMerU%6beGMMo+CvXBK z6AJBB@-8a<@#WPu!|pk*_~vYk7_hE^u?oOfn=y5GVFvwomp&>jqz(x2S-Zfh#^z-yB~pp9#KF21BP^pz&(NE5PUns6!0Aje zT!j4pEsJ0bm1laWiX1wlUU7&SSS?~=e{R1I{+X$6NHWd`mH;ei|NYd@c%=k?+uDqQ z_5P^bL5$xmY!$3D!g#f7@k3JqO?)cK$>^yFD|UIIolpt z0n zWpkMh9H^ji{_U16$rva8#JNLA^gl*J!q(F6B6&l)JP%?`l4=UdN}|2$`xkL+D2fH@ zGDEk@9|s~{cs;4NknUBxSLW0pn{#RyM*A>n5uYsaL4=9vFcPYM+r**=S&XubAD-e} z1s5@4{)@6s1l($qw`>KkbZpPrw|X!4xjab&9oEdKFdE{h^*?YzuOf?zqfR7EVh|zR z@m6`z24yST^f=%JtpzkMNH(6$v0z;B>#y)QhtWAY)d9p4f zRNaLq7s3xe zH6Q&6XOu@!GhI+hcs{js(TDj>KW7PPUWfASN`5e-ARJ>C^1+y7<7a2czwUF=zuoG% zB%g=P7yseikhADjiZrzn>mF9yCnyUAPVGIP(+CmPhsVPpg>mb1a$F zly4ZKEBtLy-t|-*_!^Ak1`8yT36n#*CyTEE?FbmJCd-1M1x}p3Qu(chp-7xB0_J9% z%k5By z0*wpPq3}Z)v}7^dixizod(A?OenmC^D|XvL+{3$jw(gcc*LW=tCJ1>gc*PHCB@m9c zE^%E%{hzo|>zlk$w^iY#;ucd{Ik=I^6^6vVnwl|`5D0wDfF*QFiTZ(2qX}+8I8TaD zL_><~wt4-NpZ*DRrsq)H(_D4Nl(O~O#MOJEwHNZ3@8{LHz!>J`C2-C{I^%WRn)O{I zSJgZ#FN)H=xrH;hQC84szJ&db+1AKtB!nW?c!Z=B*5%JA%9ACv&sS4b-@jOHeCriyN z5aYNY`(X?Nw)7m#waJfn5jvLit(WqT9+%P>K5*Cb|Cg@mkxxfX69YHK^Z%|cgG-sN yIslEMe(|4=PM>d##s3XR7~lV2j*y`rdxsLIUfuCxvc1hX2dZJ9j#It=^nU?zOBVY8 literal 37534 zcmagFdpy(c|3AL!)lsEhiE=E5oI*L)98(TsPC4bcO2!<+oaWe35i+OH9Osl!%(>A? zN{$#@11!Jz~E2Otp0A(-Kn zs}RUPArQ#U+xzx_Zx;Oqc)*`MH;oOhKsGtQxy0gR2;>w5cIA>)$n&|8i06*35u2MU zZmMcLMmlfG{Vn@!xTpw;OBR<7w$AyS^63A^7xJO&OxdZLa(3hoTSgt-)}dz9YPQl4 zJ0dYI_qbKyRFl9{D~o@OU+Vp-<@s3_ee?L0ox0c&T=zoaEkD7j=NH|ko;P%Lyva^% z(@M(-=n5ouXFQ$?_jjTsfwlc#er8N~p^)hD6T-q;!yV4N(7n;_^N}CEefvht3jkem zukqeL49UIFG3Sa53Y`&z+{B$m8P6O6kED1HXh5>B(@2GRVvrJ-=`I}j3wq=lIFq_R*~uN9<{B!N zP0&e-IU8%_=Uv!8t77P2UK-5sjMFUVeUnf9yh!D=B|eh2hfsYsK56>=g!i2f{W-%s z5~Rgh5w_s%u2Z%!t_!H4=bNPz+u?nwHf!bH#TIG$YkJ;s(DeEskAB%)i+^^4#*N1; z2@t}|+DGP2I-kS(ObRIRqrQck$Td@vK9L58t$DKERAq~%;~ALUvIi_c4;_E7U&71O z2Z?3Ae+mxlK*b({#i@7lo?MiN;!)bL*TsYMZ$2;IaTZB<2sTuahP1cIZoPlD=taM2 zL%aWd6V}4)iUUKeyOtxtb$%dRCpkvJo29NKS9QB=%gkc$T6Lr;2%P!KCN6l8lmd8gmApWU==L-i>Mxi`$SmfiON(%wj zfP_aMVxOI6-b?$WE^aWQ6qHK{qT~0{q0T2h!>JifBlTE7oo6g`XH3-;Ow0k3*@6KLy8Yis`^>j9{{&}nh|w> zecepK5dj{b^5uxyYvZ91v0$+K&8QzwDEKyd06_0)=`2dUUyWfw_M0{7hbgiozwqP` z^zPy9NZBq_E%I{jOklxAenoJBr(?Nu(ixMZk9M90oqPC&lMkN?=vP}_Qe*d5(%Hc* z`rn(E`b?tw{4Cg#(!%&oEK@Lxru0=SQ?pIKlCw%4E-|nSagTPBVY>c;8fm8f?17`G zwa*2Ak^)8ST%X7+TP2R?o%#nfCGdf!|MbsMW$h{lud26}IJG_ws?a*X<6!mUtPuS35 z74O5K`OK9qBXOtg$G+-%H}#XpNbs<@Fr4)=l8Ta$q_2Zsx#{Kr zh-H|#lWGBE9N`-F=bo0)wa~L3!!N|AhrKG0l+UP1`zw>ah5J7BX@CybMS#tvo}nK- z-TAp-L4WtNH{ErEG(((Xyfmuoh}b94BsxErBM!YRQSuy5-s~8Q3R@&p1ex}>FV!C* zIjR8(gNbcl1G|uL)K&^*mFvEYjEdCEnr&;Wt9E}{bRlKMFkAT|iPyF2LYpXGDQC<# z=kM;-@yQoX#~IwgJ0ton-@k}*%P43(XW>xtXecdpcFA<) zz`u}N@xX3x{Rk!OgG_=-apvN?*9Y)n->9Y*hs2i1Ik90W}-!k53HH-MWGE&8OD*bLB{*Iuuz!LetX}be}$>B)>j_?1669t2aeSbgC&TF8(oNh4r_1j+I4d#~oE= ztv-(uT3zEPddJq5`gsMZ#2}N*4gT_me+w~2W<(Uij~vNglc8#S6n~L|Tq(;QPrn82 z53eYxeNnAOnsdvTT-kDk_c^YxuL)KjtTfUQ??uY`f#lurPLclD8C*>%w~XE6S76OQ zX{v~orfqaaB1m2wTTJB$*WX%mRy0M!=hH;2v>lIq?ClYfdrD2vKc=MRs!U|6KJQri zn-&q!T1O7RQPG-k_llAli8X+JY#&uP`uCH!XP;Z$3pEqzFXtKZXoYT;DeM2E54l`T(W*c$|hXINB8@mk#Gcx!5#?p}zwAbp_R!3CMF;MAy$=79vx4L4ZM zM}8_Y$*R5I1)4?Qyz$R}>1dKG#Qo|p4_;LJ@Egkj4oDyAgD@boue9~4X(vb5Px1e^ z2l-zj1J5A;Gh#ejb@2QC$Y1wF?k7M9>8ZIx`@9cd$VN^)cOf{N}@SdCw!bmPg)5$E zw~Ty-m%}>CmuhHT&*2i}xFEwP9Mx6QU=)95t)w!bpWrPun+)QM60_Qtr`3rt`?Kjk zUzFgv`wOek)7z~%R@C(%#&2YjB z9Wf0(E*&3UIa2U&V9NUM@dR4#kv0c=a9H_(mlW*|r z=!VV&?r#s|ak4ap`OwnlR~ts!=g{(CwA`aWWBdbt`-gori7Je+e8r!U#O!q9_PmBX z`(ikMF$j07$juO&k$qmH{Mco;S@C1Lf*u>Q{c(zQ=IW!W3^OhqXSa_y-nv3~wD2(& z-Gpy=HiG=Qnz-w556yw{Z8XT0j-0|I<0B{})2NTu`QU z|7R3{7M+UPiq{RX^vhS-C_5}tg1zFX$L3S0GoYR*_l%$awObyS7r}MSxZ(kJ^vwnm zaYFgp-pmXA^O<(J=?&b^> zp!+UA_&{!MCK%LxRTiiDhMP)yj*+XD&o|&3uxRSX+!0|JPg@yUr();&r?8@ot9ris zQ%WWx8pk48zvPKFq(a4rW)0f(!>tusO_a(2i=Dk}?H>UrCHXYss|=&6LmSvvu@8&Z zuO^R*qVgP5ufi$^`+RL5m<&4&AZUBLZ4OibEjZ;x>97bMt12#!#0SGo%+P9@WhY);6{wdQG7W|c!{rl1ob*6r)?(ewS zOM>QK$vI8W;6Hg0VXSJlS?7zdc)Rp$Ev@S@O{0y*C^FNDy6Gu-aZjJ?}cQ{3nD&QkNUOly) zohb7nGID`(+%q_2gyshZ(HRBtj^RrUM%mOnC90l&%x5(mk&~^YbzOwo_-XlJ*B;m! z?<-YUm^j0a;tZ=^i&_}mbU{Luu79cspc$=Uz9?TOJ&tH%rLt^S@8l@~tC+iT4ruV@ zN$IH9_(VgfMUg_6HB(!So65bbO*geysQLS-CZ^IjVre0RF6|?e)wYV1Vgy>m@@0jDzp zEhD}38f(Of*U8Z%yihZR6WL5{G&#_p@myV}a`4S?&=$(0N8bXOnVDxVegKB&5{niD zQ%Ivfd30}Yncs^VlHKA!+C1>2M=8NtHdV~JolOi2$%j%&Jw zzm>m<<2^-uof=eN#GgVK&nB)8&&rKbew_lna(DBDL<_6E=`@ovqhT_dbFo1lrfpAv zam#T+HR-zTf)4&Uu$E>VB}#cAVN9@?e;Ee6XY}wnFToiLdd2cs<=LLK5!N0UCDq8j z5%nNK0WF`K1wZ($=0oxZMlGU2qdX_km~TrxqvwGJ<+cF;Inu~-^O!tGH!x8tPjGbj zlS5S10HQT%QxJ&p5RT)ZM;`Cw?h%`n%MJf|llXLZ%ANK2L)7U>OkLK-jSv!o56W@8 zjoiD1bB8(sB(H2r^P2Cu3-pZp89m1e82TahWZn{Ii%lR7X#CcLZ$Z1;kEPJKu+4*# zn(1J~+lO0VQBxH#Yi25oys_THIX(Ai0(?5TyOVNkvzO(Njd|jlvn0QXT|vvAb~GuV zRddth6YK#{aMHAvDaWA!XGZtFEt5TR2dr1Gt9c;DF?*3alg8WNY_3?&FYwCNs>q*)h2(Myr%?8V_Txzm6QL4~*}8 zkg)d@$8^qDRJ%gUG-zVma;OG*0chVZLeACffi5B4XRunS<8FYtp@ z+fJ5NhL%P4vhDpY5W+-v>4CMKqZhOPPNK%fD=IUX(GAWYced+H^9%HZNkmvz$bA@E z|Ftc;3?Mq8o9xt$lsr_6dlxIBAwh+La@n=~0svhC%pi9zV5}fOT=RPb6|v8`F}+y~Y|+!tcfpZx&Os+MC~1Q_jn2j|G@#r6L^Jl` zxOCPyZc9aj;p;~^w33~xozCp-$pEV}4`2U!>WDdOXZsWem(is;u1^fPJASx_{Aty@ z*s(x9;`#_)L}Y8%v57}DbRY!<&W&sT;4Vr=n3LX3tt#86P)h|UoH-0|8-@FwgJ{Gp9uNg(z zY&mf$;q3g~x7bltp$Aire9IXdOY@riX=vE?#`o~r?SbUp^AaYAcpz>}6E7ov-`my3 zk>w>|AHnhCY-WF$iG9f~Cf{~?^8`RYIQ(gaHfl;yVmevro|VgP+g9P%)}uQ?nlBTL zF|T~@Y(Td%WcNAQ@94vXz;Xq!7~>g*~p}7)!z8<(6?CAhjMwf4=b^1yg+V}AgaW;1F6j%@s|7b z%x+|5M3a*{SE{yJXk#Ub$26%$2$wT)F|$jL>Dn}vghqK%Wu*xzAfB#N5kW93yn69{ z$LQ^0zqSVncP~W7G2awqO9~x_?iUSTX&SRGygDc&9eBr$&YvZaxyWtA@1RbLs@~l1 zz?t!qx5&HX$@mb`PCel&DVf%qRGTu&Dep^#qcxRs%LMyhu^wVyJrf7O85W$?&;*;! zgK{CUTH3)aqYjGfLVWP8WKK;5SM|5;i*1NI`SnggW)4=z zsmRmb*->&HZkr>r^AU%vJB+CqYSentBxs}c6aeg58OF2{D$`@*-rll!cagN+kt3Q1#SZE@_ zyXH}f+mKWO#!?_Tyw-2cwZ+fGy6=*f&6w=GiV=~6Wk@3`$uHm_cy31v1ZfC282de}NRW=7> z>fd$y%ay$34eXxyqu)AC-5e?1fM>Cv2t-u8{BXSTYOkaO@s@j&0vC=`Bw&yScA6Em z{G{+Ik!p{rj2Dj{(kD?Yyj8Jhj5FEeU6QjzeM(KL=g~mNVK*LDGM<4<&~wXb88izx zHWpv-w`#z9`W~VQT^KO}A5&-;<=vKbu{p?eGix>UZ(NDz@l@87E<1X@hMYWJrA$@u zaOi8mpOmnzjMhI|5)i7FZiop8ZRh^adM@3OJXOS($Jc7o{nfM2q;Fp?av;m2Xj9w{ zdnqfU+@Q7aON`oc+@O|+!5%dHt-!aH$J)i$T&xp+)z-^wMhZKf(h9m?S-rr zO8@(_f!B)HEGAO{bBmo)I=j<6aLA6CEKiH6k%I_@N#s#<@lCx7yFNkg~T%X zHbq^(7~7cf87)R;bG7D&RBeQN7E2e}Wl374)wB6)EN~5j0lqO9I$sSYJgKYF(1?p= z2iq%u@mg`rmSTq25Z``4d<-+I&IuisI)pCLAG=4rsZR~c*I)0;noVW~T4lxKzhIFq z^-GU2mA!%9AS*7!w{lXCEsko+a0wgyR=PYUA7MhW+XCq+#3h4YeexxC>_}266jrn$ zo-s~tZ#mWG3JXg>t-*&3K$UJau5lE#A<+zKJB*nF5FJGcirX!IK@gq_Z}09{c&rVJ z=lN{ja*bYeNhvgb!?mH8C#Pfsi!{Yb&@QTy-O?hI!xG>HJ2O8pMF}6WvCZPBx^9oa zZ9$tkaA{ar`iwiPVOo-uEe~X-)+TEBOjXT`l|6~)ZI2(?I}-#~&{YoyF^?c_U&mnS(98 zZdwSzxU97FTU&J@{k2Ip+oZboc%)o6J?Yk^^%4e*x7}(_CmM31KIAd{n)J*D2VvXR)Th2Dd@(+*)YXc$+*@b`v33!^V<6c+Dq(yKjrvlSU8EP;xGN!r&v7h$hIoN!uIGHF&|n(tQT?oiB15oz3mR=DAG&VCTG()qn^Qiqh1)7{Aki@> z!R<*|`A>zgHv&`$o2v6dr>OF%Q)o_-`c|3w?(BM&8}_9Ic}9Wl$7r2&PdV@NW8h8U z#p$y{Ce;YW&R3|-!knyz`KOc0&)>9A7#_uzipokiJvM@e|2J~xRYr?F#f7xC(rO%A zK4^CY`u0sp%M;s8S^t6vftq7=-Rog~LsJqBDEF04+kya}+W40$jkU0ZOTI6hX4Ghh zBCr!LR!p)ANBu(ALp}Q3su|*gmA$Mk83*heSlp%c1$}~3OJBTk+RUX?f-Z@%6c9Qdd<81R}f69G37J5{qIn?-*$if8wWI&^kRcXZ`-b<2lWmht8Dmg z&YG+lHTvjPzbJ0%H*G1|z%lDFL)B*&@x(o_fHQ-9L^+T0a*YGIaLPRwcb4)(2z699o2&5C@pFqBW5_rpPBHcrs*9R0 ztkw&`B+wdT>8W`xpgE8%P;@NtO8GeOdK61cMmX+6>1%N^N($An z%_vgUR-S3A;2-!v`qwQvA7yw!)?cJSZ=b9@q52dS`H%UiSSabIVL*Hp)ZhTLm8Wh4 zj#cr%t`8=7D99TWJn^&CSW26EUhSpU85xR*L27^H)aDj~s!3`Ra+wZz*X`JYGkl+X z)o{mnTRGEOQ^IQ_cp&b%&5EVEhq#Y}&5LezlOM8Q{9xLZ8royj?wa0A_0Xv9r=|?U z*O<6F6kfA}fp@VU+7*>l7H(WWM8Zz87`OZG*#q!AF8*?!{7m-QvO2e9UW?DGe z^uU(+ESK%$*MRv}P4JqSu0l})s5-aQ;z7?|uN*tzf+C%#Q*JrPhW12c{ym&`F_h2z z?^%ZllG-Hn{Fb5-D$aobBsZI&Mq}v@6T(t#NEZHn|gu-S{#anx$#3WpyElEjYNF3?0z0pxdBHi2IknH|E*)nPz#$ zAd6`#Yi_ScnR((vRaezrOEIestOY!%Q;(JyrW9>bgCI*9t{F*SzCOS84W_M)ZFey6Ue3?wS)KiJ zef{E|Hwsa877m@^X{g%Zf)Bo=a;&hjix4=pMVoT+pAS-QT`?S8tpAatU0kvgKC1T+ zX#jIQ-zf7@syx)rkySKZPj(|uG?C_qF4QI-jaWQe9K2+`rqJpa1vB$M#ur$9H1M+3 znsc@q9Hr9e(|Mr2)_4vI+2({9pW;Cef`_}Y2r`u(sK+bMuf)Y`sm^Qhn6 zu6bs+3I=IhumiX4Cf5GdXGq1Cc;cAsdWr?R@9WdrZ$n<$^%2!GE*pWwqcZVb)xCbO zO3OaCEc|8(B{V#Z@n(zk+v#@yZ6fA3zlQKP`DR?>@JCEa4< zFfZa{0PjK1+n9t@uXL~>JsF2t4wr6F{?3+)_qWg)2)5HBndrj5%~x0_>!Jq667yfM zmHJA@egsW4<_W#Q<3I%y94x)SQI=D_CZ6|QE|Q>i-X`kmP@glh<*m&AQ@@@jO9f+- z;II|nhaO5I<|MJika<1zI%nphA2s{m2+M#L#mIwQLDn$wGVmXHuZ8j1v!zs8REJ5BXRB zoi)jjT6K@pFVLmFJ`s?auUCL_4dv0UT5U#;uk30~K{8&5J{GXECA=hd!RxHI!>yOQ zPpc<3e(9drQ}2veVqb}W`B~H;@N{nNtAFd{Ow}tKyhSX$>#zlbqGko&b}y6qDi(}| z$GFikK7Zac{Sd^!S_8}A3I}lDNCD|Yfk4oQV3^j{M)Xm=oGFlEvq&JB$zIH-dQLWq zYt|9Cgo{T8+5>?WkSaj+9dE5TGF4GM>7zIibsG!-h3A1BNwlf0??@r0(sQhGq;56X zN;|$tyAZeYI0e~PTfgLuK3slF@33Q?5j2Ed0~G~TVF(0oaHlx>g)iPC3c`b6B!AD( zK4{C1WYy}^RrG}T`lF~Fuz*jjbaZDavPx8h%Pp`>+#1QcyJa1o3h&O|`NHX0T~LxU zq;+79rxiKW{bB?;5I+-dLsDmQW2wAG3@P^>ZndJG~mcBj#a6)PW0sWe+uq9=0IX4ntp8l2SvMc#?o3^AUw$F+{tkr{( z`o#lhjhFV5PfsBzLzNf@VpMOUM@wxdhOI^_X;J3%I-(oc`+B+fGgL*5>IrJIMypBJ z+)skc|HQ9n%)2nCYu;e#!T5x)F0of^$mgCl-w~bZTewj?rGF&&1eYAZ4q8zE7y1=) zb9Z)B!(Pah^Ay}X#&pXH8^-K3i+O=-22uqaukR8ga^$2f>gXw<0~$`bgGm=~s&|XY zi#v5B{V5~Z>;_H=bt_N>G)r=x2jAI>_`O&YkV52E@0&7H#q((S=xxak!EM1XO{b8V`+Sw z(P~LrIc}7h9pJ--lYAUV7Fg)-l|&#yANwex$oZ{Q%vRRDBKzi4=3xddKzwmy`0pO)Y!{8h0m`d z{22~4RD$~^sN-X7^;R#1w)=unSZ*e3m)_kCI-fqDOb^!GQauh6_SF7h0cu5J6J6mJ z)GdEZ>nQZ9n))JyU69H|V5dA(<<6zU?5B=L_$Sd@V$MW-=)vclIEAG6(~AG)P(-3l zK@A_m4~j)=?c~gJl%b9qW({woy;K zE=z^4z%aA3a>9XZpylT0Cnnl89wPP8+tr(?w2R22DsIJDC2}}g4fPM7^_guofSdQnAcXZy>SbdjHH4-Va zl5wa$unVGB1xOILgYqh#qVF2npMU+n87#80)G*2!YZ^EF?&opJOZ>ae;*$>^JxM{b z$VNGRZmUAuR&Af$@eoz7Z@;`@V_i~Q5S~vB>g#pE3j?-rj74i-6zxEhG`h$cjcOUO z%x1QvqO1aoJR9&>=BL*?)>dj`=r;qZ8@pG<7syK6sUk%VyI5ruq%~39!cLw=E>lzJ z#X>euur9QRbt7Xwa=p}k3GP#&IYkwcvZrKnl94o9iDK~HAwAN-GwG!M@MP1%_+}7< zg`{CgZ>`Q|kqcM5*FG8ziP3OteAd}&vJ^Ks_3C*ir|d;8-AVdQ?Eo4o?=lC)CxI@$ z8Uv=%FsGk|<#o`L1Y8kZp3;q+-;qsMNhxq8EK+>r+X_!=+n%{{?5G57;UReOt632@ zdU8iTvZC=Hblbo{I*I^3I;0-Fwy%%rSPG%e%wDUOG!HWWX16ys#BcatglD>kk)^y$8 zABzVobM9>#QMo->x~#*heY|6B`YKEzow?qux!MJ$Rxt1IS>y@^TLO0AE+~j+s}e@i zQ;k+1X3X~pv;Dk(Kw1^gyNhI>APmvHhY0VRrzLQwD3_6qoFeVuRESe6ey{ld=+05s zYkG)e^u%Ru)a}jWdp+;Y*nBfvPGcG=MU0q`FDEyvqKiyjO#$p7xyhWRCqI;oD1=#J z&#YzVYY%SM=Li3wTi70651f4~xS!EToO&a=@9$<)ij2heWcOQs?VP#z!E%FN&FKe8 zTjcdMw=RW&IQg4Xpynk*$?B-t$WEVauk%`x$a4wAvc*EOdA8Lb@NIL851OrJ$VXTd z{T6F3uS<}x8|=w=n)Cb8n(h~7+q`{{4vbRS@+t8kuGBIG-Xtz(Pi&2n-Kv2o1J0LD z_lfM~x+a<>Rtq}nI}HlP66iBOeF3w>ToHE)^=|mNk0YRw#B}xTmm$f+pg+%@Uj(e5 z++CdA9s}&BJ5BOw%+cRFn$Cgp5#?G78!=XJ%#mt$KElPFI`%KrvX>$9u3(U3=zxU) zYylmLKsM6?Ci0Z&2Ix*LyV@?DI#&5QMr5>*V$}HAF-P9)@7_tDyny5Vjwr+(w>y^K zInl&F0AOf^U;#ktx=jv)%OrAt)5{Y({j%KC%LmW~l*vQl?ABj|=C}MxEV&Rb#2tg< zLV_1K^^AW33pZDm!xx)G#W$cUGDa_`UQd76b$|Q>y)GUJ?JPWQe7HC817($b*-a*M z?+Rat45&T=P)l-p(m|Fr?y%N1#8aj|tnwtiPJz=E{PmnN!n}4gTeKT-9GwDjU8x~p zFA=dpS+woAqlZIsaGG5AZVvhKulIR!bcPLpu+@D^q0Iw#sPi$uJM+u*001`V?q!$i{r&Gwyd;oeGmB zjrW`e+wA$qspg*I+9K1~QqR!b1Bi>H9iWzd2A#krCv{1i{aq1{c&Rbj%?OL_8UdL^ zT{kYT#Q&Hz5b5{)eptyWUU144^4AQgz$bs&BR!vc5zq;evP{zn$oWX8;4alDj~V!# z?LJ31DJ{~hn8&mlo@xCatJgqnt`7Vc>wN0{70J;&|Rw9 zpPa^0m~k1qF|8jDtifjBGx7p^=b9T@p@WV?!z!A<2|wuKc`K|YbOg%D{PA;`zY_<| z)<{=jh;;O{4@CqK^g{Cp^jIT#YO*%WOUDg{Ni@zmk+~cPI4sRQ4b)bdAB2OIP6R};e8#YBhfNKbuG1L(|c5m4P zrVv1buxOutpb-2}OZ%+!As>doJEdby1$2XBvU5|*cn%TmDrbaGfNG@n#wqI-v>Wa# zxKQ`FCnFmFY42QDYc;XoUGb4nYu< z{ilZmi(sCgRvB@C@`Z|6M2G$QysK}4glwn)%qu{nAkBou)*4ffSAX4!DCw?|<*2J z|BD2h{;@R3b}gABOb)B_E+_eod5JF*$9WycLABfwfG76({k0bF6oL_no-X*3zD?ki z-mesK2{W!NH?+ch*~u{DaD2ppita-)4r`;6==|x!f|!>t$4Q%oQ^L z*BcXV{oL`OD{5K!{}^H1o4i2)u9*+kEz?Om4&vekAdk=!3v~`_ zNc0=H_VUFMtL#Oxu3Kz1AOgV}9Z92qSKyg}sXc_sunlPX7E}|#A_?kSJ%~h z&6=4VgF3zLI0`WcZoi*kfEyxGQEl!`}y?x0iguqeDCZRC1Pge1_}& zl+mC_We(>8RQH~U_GGQ`qBx0&5U;oL2XT9GH(0a%P-f42O>>!Om&x+jxsx4(ag(LUX6i97fz;5RPv`KZJXpS!I0PqJctm6tUnFHzbv7L@d#&{3z#%o7CPZ89>1_@vlgQY5K1E`$Lrg#9~En0rk0rsk+t z8<4Tt;LtNjcn{vee#7>TpYvvaK+5`OQh@+^=r7nlT1FqN1r)qDyPnWJv4=XgORh*I z1S9n&6Dq4jz)t#jkG|mA7n<0JVm9`!l{3e@#$eQE3SG(p73JBs#O5WRCg*ptx*%sY zV+B;_qrEnxJ14-&h15MI!(Z=}%GN-i(J=}Za}EnYM0^mj-e+j(WoSQ)s{Q;lxc9Wl z8Z1_`)446^Yqb;raE}id;))EQe|0t#NsKtpl4*eIXAW$dq@j|WZ1+uFUdw)uVn^4D z?~7K0S!?CXpsWv;ug9t2InmFs|HPtcnU{Ak#cw%?jQF~OrcN!gAx z#}}++v7pjeQSKO5GBK`IP?96=trh?n6FNyCITtOC3ZYV(=*d&7#jhiYmh4YBPN@=t z-UqM%xNl=WDvZT}_VsL7>HF=S5l8Zd$8&BW-RCec{eb@HkhB}=3T=Dm-UD_bzKtmg z9)dE}jP<;#ayhs0suGM26y+>hoHMFU06;tO^T@+ubW&DVAjDP&d@T z*}K*_o8rCk?C*oZf@KubZa`hNLKAe%cLD4|u`NQqTu-_(VhFK#q0aZ5BVP z*%>*-N(cyUz6{)H*}1!WXLisle_x*Bb#H=y6=zuvU#fe|-+xr4-DQJKjVOyUU?m6r zG{nxqs_>d^goq-BSf_ijGNq|kr9u^fFV)mS^*$U20-QMmEJ>pyAhu*>k@0YY&*;UF zmJxpFv8OS!0&9P>HfAZTji%MWf}=tfZF;O6e8^K(V^V-uQTN$3_hmr=BCt_9%0MD~ z4q-LgAK*hHfwvKQlHQIeZLsvux_v2G^_)A;_+CFd9#PVAlEH5=x>i;D3G2C1c^-=+ zz?l)jwd|h4cH1?JS#r&BiWj)UHa!Z$oP777-r<*gL*=-eeHG(Zn)nWxl0~@q0l1W7 zI3&G?XV{^NPO`LVXN%2mMr)x!b1eSPS6^{Y^wRFgbAmz@@?nsOLC+TQ1oyaBy^-eD z#1`)>u%>3@Wwho_N3}&v#TU6rI6Z0T*UJKCNtZ+U)Eh8a{e2vDm9$c0P$?W0uPF#U zX0F_?_8a9hlPqXU^rfCd!eov&TTIADj`cgAu+u9h3KdHbeQ#e{SkHWcR-}UvQJ-Km*J%v5@G)D*rQa zc(QftuG@??01A{tGQCaPrO5979l2%*+<5djCla=Wx23}sP6)hO*`l&8UIIENKCk-5 zNyMLmXr$qev6mnBBtampe&DqBf`!UxNJytk$j~I_F;y^s+F=+lg^(E#@J5^d@VPw1 z@(adEk}rZ@r9DZ}`RA)8UtUt$bRMo1mGM{Auqf!3P3&Hh8w&q2j!kQ?d1*z8lOXmv zb(5NXf{g9O$FzmUB-BPSP+&jiQee!(ueQD6GrU@sXXm$Qr=#EnUa@%a924uPBkiwx zelHUT?K?+>|}x6s*#J9tdI|5cL5sc53AJIbEmIw0}|w zAij%`1@WDLb>g#9AhGF|Rd3mlEpOKK6MV3{|L5^{Q)kt)j z=AnYK^x6VDDB*c-EZ)ucr(@j98%C!|$<|SgX$sH!GvmwVEKp;c-5qE9s)_k-UzgeP z83}xaZE8Ff2g$*mmZuyLCMunv-loGWMtic=0YyVhM%Qj2q z!PEqBgFjb?V+^&*JjJbF<{xVVhi2e&aZ)}9EHZ1%@_E0~-|$(Tt*h z5)JRo2rSvUcQ^Y|UPKKeiNGXgjx7 zN`+$K{3a{ef74fdek(AjUk)f~9n?6XH(1vF3ioywIV#NVb+4PYN?f{qT7h4J|FY4> zn_*nv*=+KXTh@nN=wHdbYD<FI9U^3$IgG=UCQRZYAbi_oPo-Izn%zeU*tj2*v7Bk2&-eRl<_#Q={siG zExj%0WLsq?Di)UFy!n15(^^=6E1k~Gchk|%8H&!S0f+Y{yuEPv0_D2)nY^gyLfOA# zIzm1d{d<+$#B{O8aUzE78u#dt;Yp)kkHla4Cb!6^i@AJaHzya`qKA@UZQ`P$ zv#N1VHr2>W>leI?Pjb6gh#WnNGT^N2*7Xj)UAF3uIa*J-1_Fn&@h<~` zqhKF}RwBIyR&qBwBb9?T_IWm%ZB7;|5?AcQ`{TpPNswUlMui zrr$Ux25SQgC&}yc4HmpDcx&>vd!>S9r|_(;4B&f@LGrlN^CiCo$knB(*Tvcs+V4Z& z`deNmUj0<7J@@^RMC6q#_$2Tuu1c~`ZoX2_K~H}u&|J>IPaJ*xzUOJNuvUh{j?cdx zp0wSOydBA{apPCmJ;`WEe^u77Azuq+olle`HGp$zy0f=vbD&cL@$8S^gp?ZQPE?19 zL}bv4naQs=w&T-+xE?Im(rp8Q%wS1$Vg4IVbH3`yWb?{Rl}g&lBc zLy}gS+xm>)aL!#9o4}!6e*H>Mf4A(^n*I@`9P-b^dSCxNz$#|@eH=ia-AyxnHk^tU zf4yWSndV8(+S^6tTNvgu4%BIz8~=)T`%y~FvYHQ7aGq$x1@HdiTx3tKn^W-p ze(Ih3BQhvRTnt!T;z7ybL8DvI-T4)}d9xbb7)SYGz4f?7O>ck7bh-VvUjx#}Bp=qA zjMMbyZGRd$ieFd^L<+qByq`PQ)y}PZq&CdnS!~;<)OC_?e7X@ud$ga8D9AI`zPPuh z>q*R4*h3|hwz|SZG|iS7Cb!I9J9XT<;%c1qV-R;ys+DK)R+x4A>aDo}U2*Yt6+bDO z`%RW!v%HdxQSm0#I4%o1pgI3a?AGRf1aA**bNX%fETUleLl$ zuKy3h2V*gnbJ%Euv1pp(jI$ZX_1=J}F>;4(#N}TLJQPn^aAf^HG`BhO-kIX+VykY} z+>xkZxRT*S#x4;F*_NBb1qOU)({zo}*Ml4-M|>Q;GOu}VcTF@{CQ3&H3ku@m0B}gf zQ#*g$?`)4_mrQJm=Q5@6M1vq$EEOyLDy-#KSO9+>lQFYBGN+ZMGtm6>z=t<4+?c6h ztNf*rIU~w>=viJ~n0GFn<)?3wvQyH8GIqNr{7X^}rdC}g+Ud1H(3)vB$1 z?R_KG5%`;XF{_?-@AvCqMcDKgz6UlDGI{(xOEA7t1IAs>go445j6`Uu;4%MfiX3#i z*A@XMS*4|-0#GFWr%C(bw80t5V&^&Vr>?OVB`-i{4pF9ab)Rr|Z@J_fPrG*?n{56; zw(s^GLiv7{-AJM1#tL|N_v4FxyM*E*+RrA=OYT1Aru5sl=dsEB$}tx<3`J7!f-$K4zG+Vs8IQB2eB+dnIS=^d|Ui@l92lnPfw*)g4)ggNG6K9=T zJl{rrpdMiA(;QVKq90DQP}q4Se&?-Y9xChw(pN9gt}=B(v_&rsWO&2>6ui6Fcp_#O)tRk<>-?b~+< zuLv?e5bpR{h1@G7nu?5$kfE{iGo5;x5i{LsejhvWOmIFdjju*PK9QZhF{nXK;cSX` zbpiIcl#_k~qidnRC2g>JrtD)|xc6lC?hDR=J4g5IWBFTXN)#qNP?B*sQ|-gT+s@Y$}~ z*r73N?lWnB?Fawu7Qud9o5ps=3{!GMW)$nWy{@0-zi-~8yPtfZ=;F`+LB*e%VR&&U zT_a47KN@nzdj@?r5wlEt@6D}FrUZpQuW*|COe1XfsDy5Z6v zDi1EO-I_d>+tImUCW>9}Ee57qdwoR(JeiD(lyZKmd2FnNc3q11?#9z+{2q2fPNH7c zMQ&C@-{=a6TM4e85n6YkJWokZ2VPFKXe63(F~9^e?uTA41|zZw%hs;s}4@MY~Z zxLGoS*C^Z0K7LuSL-#26V&%r(*Yz2GS^l!_q6oxkO(vfqwmq(X8Q0&pWyG(z^H^$$ z42P_H)Ttd%Mz@e+KJAgRLp(v(w{IH7#YtkoaNgCMWl_e-mJ=g~gwq@$<*gJ-0(4QH zoLK3OAr2M%xM}HRr;fRwy=L#o^T|7s{p@Fgn0gT4)~o>5fzzsxL)Y)rF~YB?GiJ0< z=wOCpYFA0gk%TZ^{n(r^TW5rsSMz4su-;_^Zg)j-$6kkH*eD@R>k8n2zIuF(TLd<{ zqQN@P4C$-!{*2D|4UZgRrgiz2FdgOXQ;FeP5k_--@da3Eg1&ja9_*-HGM5wwm$S~< z(tW_|_F@3x{2HSO;X>`J4roK&*%j|mxFAXN`^|W3z^M)FShhEw*unlgmq3&c&d&X9zqyq) z*Jj4Mrfn|WWMiMM4ozP*+6_X3s-A%D;5Et56Vlv)i+` z=Y1`EW+#OFqU-Ze2g)w!+GAvq&d;&>uZ5)_p_GnD>}Pn(WHMLeUHVe)c!9+_7Ady&M2XDbDvbICy~!;nZ;hn<)p%3rZf7n9!q0yayh`<=6@Q_#CSbdb1l zA~llIlb+J&gr)?u-WNADmDGoO+8QD&FfKXVFmBqP0x$hY)F*^oyuaGTE7h=BjP-ef z1CSgu7k969R@>6s-uHEk&6|Z9e|dkgavWydLmnn6p7qJErrx74q+7d#_iVOUFNcb1 z=q

    ug&bDyfZV^3GW|+M?dTlTWjlT~jO$O?_xim`jK8VWl37ONPc=)=$X(C+12ou-M z-G%HhzTBZ`pA2!(=sB6EtagZWmktg3goZWOv~R>|2Vk50<2LT`v?xlsdl8;8?wlW)kB~dM#}bNlcgA#p1&H&FW9> zR%RnH6QaIR+^(~gj*$mDmsil{M~$7SBcDAs=d%%3+yE%gI)hVRhv+#B+|#>lb*E(K zv87|6bgJccnMhbvMrY(%=R6v3)BOlbH}n+KJoq{Wu!TFvxutC9L$bHPZc&zLWbqa=qn_ zuI0iij&%y&Us&UNHwI7A_y%VHAY2p+e@@7Vn>*gCxS9_7*_17wAs__4ou00Ee8+=6~9>5 z6IglKMp!xzOHb#G^tml^_hSD-@Fd?`CPHK36QxDW>@82zEAj&ipNYXmlLcFj-l=~} z#dym|5%={K&M-Jg1gH;3(Z1w$t5k-+bdbNarr?{d)NS*?g=e0FsSWlFC@!R;!ZI_} z)@#7qU!!pzNcoH84JA>$BQnV`royYmD2AN8YEb?MR)8Md~JjwsNT#|uos zxUvSkC)H7C>(BoV+PBi}{sY19$De4HZocgTo#n)$L>#sn_}&rasvSuagxX}Z;2p1- z5K|3@0Q2eQybQgNUDP#66`eKKpeK*v%DB)Iz%?Z$yCw7yn$;#A+vM1z>_<=Wmkc89 zg4(nL8@2>x;G;J8yDoKHnoYVOI4)B@bmU5c8)(x{cEKRJReIkW*HhTKNN>s*kB&60 zs$nhNv{Z>d?@7`iQjgcBb1IpmnRC`yRDn+iKPnkm2}iL@@nCWdC8UkNcX4*frhyee zup7;oTpk&%YbI~mkka1ciR9gsZZgwiRCxw1xoQJI0l05ua=B}5FAqI=q`cQ^?Z`$~ z!^Z?phZ(2$#nn{dhNY*Tsj451K633Oc8teXa+}T$mj}*p)6C$c8{>hmE0TQx*3k;;^kfhS_1Szoz7Cj>@r4-e{w4SNmOY6JKI#M!JqJMWjG@Cm28lAHU`SAh7GzM z2YcN<_-eezq{m?^gMg*lv_^AV$7Bh0nY1&;=)EVA9<2eEG` z{cVvHUUb3IO+ZVqHa}~(<}539DbsiScuBLCNJEScT^s8fZ@u>`zspBB>FYRQrj+-Mna@KHn*cAr2Mo&(2Zgka6qKV zd)>eOnOdrtTW5brb*?=jC2i1{hkkXgd;_P|+w6Tp&}bBa(6BRbrza?&5_*K( z%L)ZDu~GCHiOx2ri6Gw{BL=&tWt0O-LY? z35eo#n+2gW_~jg5Avr7YRy7+fdE}=W&pya@mm4nfwh!)X#D1J`nvPTFZ4aTf6LCM1 z>1Fbk*={I5B6h7iMd=>yZD*s|aEBDZ8b|p(as?q)DrFGxO!u^!h(?p8%$>e-$D0%Q zRvo$a0iMJs$F6wanRIsfRTNK&WhVuR?9L|;haKO_xFGF%%$zOHh4nsi^tDQ zu~i+Mjfh$oa-e6eZ4KM^^?FqOTVDZAQ8KP0Hyjope%hJZet%T~N!}qoZl{ifQTRwmc*IC(q;) z9SR4Qs0d=g+C4q%y5QpE!Km4qY@6Xas^flA7w$%H7s*d5UGD9Q?@}`o;0yY3V0sbI z%H6s#%kNVKF9Dpspud7egdP@3ii116HKHxIKqvas{(wa1kDbuYtDP~c5d8iL>V6x$ zrftEgwq27{i!uy^n#<8G?||L3q~Mg9t@E&;yMVM*H8zK37}yEhsXFr@OGG-H>BwWm zvs{YvkOM0pI0x=N#h}OVaXeA)d7oiFUb$y>jw>bs$>(6(E!pQ~j26nu~VH zZRV}miRrad2JLCuf_gvFNK}}qzJfm00p&nPtly#eS84%E!mGOWyU&Gvf<97#<31B0oGk347KMm><{JspnfBzbb=;x=zb}+@KMY96AkJ$ z-HkQ3{S*4dH?5+Pj=L^r!!u|1IlQAf@`;H63+(~Ec2;ZG)KXO$Q*&qge#9N`Tb>H& zX-Y|o{AF-!;QB5uhBwkKu#Lq;-VB#AYCPv|Bv?EHyofqJe$Q zHM@Clb;FH!$JDHu!u$@J<*vw(t*N^F(ekbQQo!%&9lmSrAFPucJaq3UCfn#qlo^0y z1#|c1-zmA2ChX%tCE2GG3BJDPNr3RD);%hf>3X?x2!v?|B-H(3JRkEdy?a7SuOgrw zACmi?U~ldMGR*@dX#AZXmC}a&m>~+mqKFsVpFTo;0t88YFI5Mo3f(t7fd4zK+FT+$ z@4b)qQ{~=u^H&JE0i?kG ztYp8gZ`oR&)?@ze#Vy1Jf9>)fYXj%fj<{isVb@m%dQsDwq1)`HMngp5;~CVa-^gu`&Y{1)l~;eaY-N?SwVQ zBbm!H=t&JMiD&-=8mnFe5oBx^Fqi7Vet5q}mJxt(cDuEf43V3rIq$Y&I1}Y4A6?XT z=&fHJGXwQbOY87!=bz0M#<4o^7w$Zj$3X~?Os)>B<06>Qs_CZ=!h+DY!#j2Vs{M~z zfadKF^m*B-BZ(yAhmyIghYgsCc8RX`m<#Gkyir{@-ToM6>*R_vcr@RQwDGj6>J?Gn zuKlgq%jsPu*kqH6m5OmeVbq?6Q#Ym4a`xyP9r{%Od(9}|+3PcHB#m&`Hme~|(fQ!? z+vW~2s}n+n_v-S?jGK?(0=N7TPuW!D0dozp6$xsYJb6KGZ>4`?1h4VeVlG(`AW0jJ zaA9-$?YZT_g}Ts~SMkY}k6rKW#I|kW5}L?Aa?xC=yB5#3L0iDED9ZK)oVS;v4i}e_ zWUG8|l%%fID{`S}I*0gr8!nbma-NVOhLd>k6DU zu=$SNb?H`V5H2W}8)#Lc2so(F9iuBc-mZ^IK>f@CK}opje?+hK9-j}^#ZVfoHF=1l zffg9TddVWLE+-+6=zaOcB6uw{dnR3)Pd=&|NUvPs-(DyQdlDSq2~@q}`GtY9+cm2x z{{F_y+T5;*l5eWpkaOV2nu$epv-N7xh;C^#cjB(-U_14{7OVWcp7y-^rSC0T;CNlguuc84OaC*c|>A<0SrhQbVqIPlbA^G4DGavFUjrLw)hb?sp?9%V>M*qMi%+0jpQ`ttw1f(gC4yPOGvR zUxM@;VB`wl&^u*6Ld*fz$)j4My^0Js`=n{*1dsPhckWHr(BHtfLZLs$;i(8TJEXqpmYrmJ-LR?8OIfmKa;O^WhKAVzL1PQYMgf< z?!ImTGkwhn&2N>I8*itVo2&ix6>}0bFt)~ZU1t&HB?>rM^k~MeMsoSDGzs~+ZgrIJ#)dhcKLu$ z$~7TpJ`gyz&OIZyHD@HRjr8cw_ENHuFFA^e*3$1^pEHPfEG1qu=HB?+v6UiU!)QV-n!k znq{@TG;YK)Vo>d<)AQXY48#IHxxk!qK+LQ{4v4`LPT2WZ!36$V1sv`=sszL}h*YX+ z$+bCCnsGL7$nLGH-*&1!??w5$4+|3}OQR!{EpCAEgap(mx^HgCzzK8E>74QJ}qh2_iIE<%RITwy+ukAdhlV+w!Lkn@l^lCjrd@offlel~dN8iJW&-4b zFX}`h_)QC0ZG51%1caJ3k|*GSa#v-$ck z#d^Yd&IFp=u)rfEbRnIC&eXov4;C~{8tNRC*`shM86=s2%y$Z(w!AI8tf3HH-GWbD zYAnP!k}2=;dYv@R?&Eqot;Y{uhgx4t%qZ-US6#{-o^>@YguQERkgB&l54YeBrLWkK9|bu~9E&k1_>}!E3c25#CCWOUEJl$hAGsJGIf^h=Qkj{lbrG%w5sX z^mK0pnK<=M<}Ni=TkUyWp?a~F_9hH_;#|(uY47PG%Sa8!;F4#r6U6VBzIiO8BUM1e+OS#S-t~g&magY+=b&4OZ95)J zCVu(AFm-uke+}c3+`L4)?pJkS!J92eHv1FHYl6r(sKqytseRx0Hb7Q4@6XX10cUgQ}HP4!?%D_`0>(Px~gz z%L}*t$!NLC-OOjK$!IxN)pDt5o-4)MbB zKo7an9!}b}L^}7J4V`cBH&Mw2>f`Y0l#^g3Nh^!CN)k0>{dDIc!>E2lJ?uir;dr?nFFNgEOD_`Ab zFPXL#rPvxg(HJ&wuC@PmNd=sjq#FP+*6f4Xp!1NA?20sI*RA1TeMXTS3yU1s3EcJF8n^68W<^TTZ|BC7V4*r67Ggx!-=ogVL-whVGF{xH$A7za@!yFfi%AyB9^VGFgUf3vqg4YDZh5-2l8D)q`&Kq1}!%K8I>zy^&ba@Z(& z;Kde$hR-iAkiTiIJg56p9bZ_fb2?l*dR15|h--1Jg3Z~$xb}=h_iWXt%XF~AS@`rx zPZgfIZJiFv;%g0sQ!&Uh+!g`4@3jF+Xx?xqJ(c}vN9MxyIRau|>j_v{z7#W6KZqY@ zaCL6!4ApewRge+ME7^!lX6#wl=>WP!va_N?2B#{3g?3#H&MR9PO7FStEEuM*~ zNb6W^68pR1dGn58={WYhim`azc24u?m4Dom`018uAA)!`$iRl)aea2jKjvBqy3WMl z1kGZPrjaK1@!OUO=u(g21AfoPCwW)U77E0IpqQ}ObG5i{R86CWN^!889rGxw1IQKi7X4#NAO&SY)WtGeq7=o|!c>o*HPDtb@4 zritCO@zIG3=X?|>gYoIwUhh2#01}`2Ff^nuh`BAsXGqyq41b~&mE(>f&g~()Czxw#iW^Hd7$W9fRD<>{HZWF# zz7^f09qAe`cQ~#dR_fYLV%wiaw~I`l+3Ql2A$|Dsin~fz5>mfp6!s_juVM9*0skhl zor|%dWQ8@>sHjn)5wBJ-lPI&MFW=h+z~7D%B@s}h|CDS-lqlPTcYo+IIq8hhgAiBd(j*2JoCe> zhUFfv3zEs^!ilky`V!Gx&4$1R#3y?woV7wK&*P9RIpdX=D^Uwb-sGXn2xQ@#O`RfH)?nyjMiN3S{(QXt-02`p5@Ho#uJx$GRX1N1l_*zulkUVH0} zczka;`6=Ouav0ykyFhrj?rA7VX(dQwIjr_|dtU8lEZ{rUF{u|N);J&sQ2D)cy{m0W z*V-|HC!etN>UR1!eSUgW`kW!6S9%k!Gv05+J0G=ve^*HH(E@?0jYjEQ(d^Dt86>?P&-B;2qRIV{Jv^3@+Vq=_QR{Up%mBv7~I za?3Vj-;)MR5dC6%Xj0kA-Aj(Qo2M#~9kH6$%m(p=PBZ>OL?)0}EjIa7vAf}7BnhA| z;NPbxpCvuZ?a2IPvwJr{Kt-UZEnfl3ey9$K;5u?SbR?x*A6?X%`u2JY9?Rvd$Tq24 zXt&E(=vna7ZK-;m;H;V`{$Sd&bh^F=hcv|ED*gGPhPKNW zju0Hvhgy*0nJ0(;)IB%049W$C23)a=!5^DrgR0nIKIXgz5vT2;=NH&lD#5<5x<7yI zPP2%41g+Ty{v>mx)g3)4Dg){!Weh$WcP7aP8Rly(eJOnDG5PyC<=V5@ z>4#=DxJxJjRA7K=$mn*(RWcVc<#@ssp15_fkw56l)t~cJX&?AegwDVA4m%BOp{PjN z7_IowZ^Iv=pbD`JyKm2JF}P7JQ!*d-?CinwrXw~=CTf`5y5FfB*QZ6z2I)?kJgPwp$D&P~2Lt9s2r-!@>C zeDm0$xuj)=P(2aI9;;oV zLVU^&=N4yr2=g{zsrII}hA;)$`wWmJ$ap$S@k3Nc2}`BwymLO;ESbJ}ysPF80m2?L zEJfcqAjg?-oBbb6zq~QhS|JVCwp;ljiPvpu2BmG?bLDfQ{0oWFS4sHQsb3-SA;OS# zXd*{pIBlOj%*NvjvVAjDWg{S%Gw3V3G{>H3jK8-Ce3yUT0{K~ehGHsZT0uz5+GF|Y z+CRm_0lMvb8El7^HU+H8E8b7OkB${2+q@Ms!fFUN*m$HZl>?7kXM(kKIMOqXuL#Kd zt94l8SX^6NpKhQrk*m54S^U*lU7)5DU#`Hx`Im#~C!qoD8;r6ILHm3FTQn4OZ=cT#z3?~cTrFHcN^Dt*Z z8Na;AE;V!Py0AJb?F99w@5cS_Q_>E zbg+8r?VWIDReHoJ`bWY7MkEKV=>TS1XJ!qoA+^#&p%bF~X0tRXcEdt+n1WUYaOmqtpoyp>H4AAe6{xtTV(g6Cclv(; zTJHkmgV=bVhU+=ASfqd8Ux!*9>admAC)0i|b6PQF>}^8E)%QFxF_()YcI20dnD(gx zP|rpm{sLvhE5E0a{sejT@^HiW%d0jYGq@DJ+t*@24wNBB zUoA5?q~*^EY5T;M7R;&9?@|bz3clzgI(xpc!bZvyZ@AGpWR|%e{q#WpVPy+~tb(9w zGy8MDv=@4VOkmR9YVo4Iq~-o!{;_%EAJ&e_Etq58&T!}uY3C_j-?6`>i0zpBkR}>g zo846#lp6}1FKcT`SMMqngqB)RCY)Vsjbmrc-qPts&}{V1SQdo+KH7_^b5UAY7|JW3`_50f5odus_`8NTv&sTSemsR^;{divfX|Aix>2q<` zFhce)Zh9f^2-@5ZftZeKP=QD*yP1G8^PSR4bM}wJ6{=tXiQjdjR}$;g*X<%c()#5S zdoyi)2w7nPMx0#+4XH1QfX6tJ78Y>!2z;ND#L0?QSD#E5&*p%otPZJTrPJU_bKj2Y z`g+7h(4_LlrboEsz?0UXURQ(3iX2*Xn7nvZz7QRrd?a8pI_CZ5Pfh2Y!?acGi_eip4Z2odi<)zBCb z;^RlHj~Yj>Tm+xVDm;5{o+P`Hz*wq77H7!J>t;0DZsicW@>#RQj^O7jLXOYD63Hpk zKCS>yA7wVaRH~;}q9%(x40~avd%D#$Os?9)Lg>h`szq-dzq~Bcb#Mwv<2#n}p1~n~ z16v5x+PZw#U@mXLo6|Y(pEru-wtD)tB{7aEZ z8`2xf=cVb>Emidwp(n414#dWLAv{*ho#UZdEE3$zMUx`=RXRDB z+1c8E(U`sOIHcWp#^8Efj(V$CGK7|OYtlx`B1k<45=SEdy9%Kv;D%kF0pxr+U(&8v ztHan$GUje@H|t>u1_}=w)EejoMr}rI z_9kq9I}>`~rPI_;s%t}*Qi!T8UCNnt>n1W)-lKqdImK(0P9pLROLJ4TmcuMF zd1bxGgdFBmAX&!-g_2Xtj4}|YEt%54J*cdT8elgt!m1A+8znX-AG66Ca68O%&T<}k zw9X-3Xh;84geW)lIgy;$e3ju~LMTH4uP9g*QjMHLKkt)KEz@G6wv~8W*!`I>5RBy= zL3ESE^kR;p)y|)o-xV8h6B{TnQ1gfgu8iQD{xIq!{=}$m`w{edXOwZ&CbN(e1qOAb ze$4M`(LEqR8&S`s>)YAXwBpSWX4K@4O@i!e9`Iofe*>Z!i)&TjOyZdnFOiAaB8UyI zl1HkL%2fDF)O7f?f(k)HsJhDct)sYW+j9FJFV>Cf`JPT=olT zuo;=`jGQn+Rc1Ex1rwi3`nA3CjUzC$K*? zNy%d7?X!n&2U;xjUQC1vFGOTE)=Jk)y{2vq{Ocy7((g!`b!?K_DJXM#9@Xn`sx$=0 zPb-|PSSTOM#P4U6O6i`ydA)ZX&Jl6Jo3qo;cC4kgS0mUbM);xW!nilssAV`f4WjC)~JPA%1>Ms$tE>zAC_(7$L9)1;}4LDhQ?2| z*-#Ev} zD*tvG3E_w>i;Y6(#HBu-)oaq8mIDWVrFePuQFk%bI-YL@{kw`n)9&h$Lz)>&OMYpMK`lHiH6 zv=;ZqlNg9%)BOJPZR4yK7XawcpejtI^766Mo+fpxq_1-}z2Rwi`&#A3A!9^&_UFa# z$qbHFzgQO<&w8gCOXf@?Xs-|L_a9a>qz|CStu`dsa=#4{WlXrJh$ zLXz7<&O$ARq3}AJ*o}L_deQTP{jaxL1T3z*i}H>rGgO)=mrsV@7nQWr*yY^Sg>r;QImKRV87LPYs~BBJTbRq5W^VCri30*mL90;W_v} zqF}5#HmlHr`n`;lsmRWHZDdP&i#-2WbAmDjC74!#W@NDIar5gqR>y3NJ!tEV|gH7mR3N=PnianCLp*AOL9$3{)Z3LuU&6nlEkq1*o%#F1nl^4^7T{@jBW zI=685O1#PGGpVcfKlt#V-V+9wOPrVq0CaftYV0aSroq++R<$55n^D6^`!n>?r(mzp zjm0b}XW&-2tBB2~XVVhEDh!$-68K72X94F$Ix`m8m(Nxz#)5J%mANgIcJ`UaBK zTaA=PN&b05Jk7~$!<;kvCLWhQ<@TZ0wsjMXV^iNBau$kJPt0YU7EWAY**DTaJ-I?9 zXXs$pfICrca^vF{SgkrZuCg(n8jlNNl{)xUEkn~jIWI(V)4Q(kGJU9n2r_v+QzwO# z^Oi*|NatS^+LdF6>qr5nFsOYnzk$#WHQZK?<2m2$W>yToU7fYHw-G@6zWg=S1duW4KC1)ff3a#noZ? zBBcj)6V1_{+lXg$RJXz1@#3?^wUpQ(xeO4LAj*P1dNj=jsO;J5Hv~FJ{OjaDIeZfU zl<~V0WCbt^6cgFP!?TB$@y(xxPp^(?i)GhJT9V3C@xvSdVxOttrPF;2ekd_5S6Ovx z5~Q51_i$U}UE<=)u@e8HgchsG_YWtSjdZo$Q?-5{<|6YKqejmHfN_T?PC z{p6X0xACLi3zY$_&em$Ko_mc?oN5I%W5j&Cj!EJAJYrdbz{q5fKR<4Zzj|9W@2L8K?tHDq(B`8@oq zW@Lv+xHg!fWl-wsZ(h}412AE9RRTR}G!JEWxW3psX#OZq52BH?)H!~z$sD1p#hXT5FY--p{Os;*-1EC`0tF{`$vRlrKDhXP?NSs{JseKwLoNA3p_Q4BXrENpcb!=>d6E_wwWHVEQsQe$)i zCCVU1J6HD0lU!NNG5Z~w1BOat-aqZk*r{vd8dnwhu2B7uj@%zOP>>p^XC>j@ka!EG zG`h;fT2Krerqd{UGh~uTR3>;2@#Y%-4XVZeyUgwXS~2?jT>O764gG~=oo<u4t5o%@l|6yw9{Gnep&N$1{nZ;bW~|mRsc6x zQRlxefj6Ple7Z_y1n%EFGdKfHUCfnxc~8q*wezl@p#K{66jZqcNr&1ag?x1)TOh9&l8tEDMkWxvSPrgTP|PZxeeckA8OP*;*q7J`l-`?zda(cf z!=!yh{o~O)M|>o?H$xxp88wE8XLmjVZvzFo?2_tVH|Evk;r*6CzjGBGB6l;yna^>u(E!>{ct--od0OM#%hqFenHK zlE#MeiQbzsEKQ2yM(X~rk6vhjJ{e9u^$~ODZE0I$hK03dcgRWBZw0$|frA0SwX1>$ zrs`?beCN#WUd9IQ>HuV%iSDM?1pw{D#kJt4@`ru1amO`zi{(k?iD(iXBwaZ44-5F( z-zv~fIN31gV3NaE(#zGb+T8}z^uW!w$~s4M#V4KC-x)|o&j5>sTUX>j+a&{^$-5fi zFOF!H6*vJUdJ6tt|BrT+dLzl++^?W`BjTdJ5JiU`{ohME2Bd3mrUZa&_g~ya-~a#0 zZ2$k+yr~T4bE;NGl5F1BoU z{JkbCz8>+VMR;W$uRc<4i^$b^;qKhHy;D5XU)*6tTZF~al>paYcO}R&r5WS?%cOpi zE%$;XZWeGaz55>a^0?{7rUi$AO&2sIVISKIo5~gwN|6<3j#d9PDL-^ehEKRY5?1#m zwHP|ZZG2O)YzkOW3&|MCjzX+ZEo^y5D+r75zJOu`Vk z%dv6t>@dTQB)@Tu4QB~qaaQT6P6BmV@nH0q&}G~~qebz-k^5{Xa&8DaO*-U0u`=WP6sEnq*BqT z3XrU*{Cn4t`aBelZ_KZ3qng-Y&8;$pUN2k$(C%R?35MDV-O?pTXJhR!JFha_@!D~xfT{g#IH#=Dc{_E{KVRq7PaQ2efYb)GruZm|4_%Iwii z<0?s?&2FXubeW6)5a4|9ufDg`hqCDA@T1(paRTBruVpvULkf~6;1d6fx&JqQ9wj~M zp0b(W6Db&BLWsOdWN1(!@6_Y1G`;dGAj zSA7t{O~}n1wP^Ib3YPdfKd;{UJ=dy)Akl4+>C#Wto|ZRfW%?|68p`PxG|!{{iL!DgaSX0A zNf@z=|KJuzs~$L9E`cP?!}utb1sXh5VrO_f%PG8-Ldo9B_bBmN@n^p8cGQ^(Y~iXT=qjc+@dsl%jGz`_mUP#WCy|X;t75NRe=S zp;qJegp+ilvv@?im&bXufQ>}$t3u|YLr#S7v4?TD)<#_^V+uGBiJo8wqr-lw_m4g5 zm=k_zmiEZqQDu#3TF7Am{O;jFKXT+2hCVAT`nMu5@J#RG?cmGO$`?uo>kQFhVC*E_ z6>62LrFx6M3_fmnIRuV-!f@rgg+Al8wS!^kcD!u=8;4j{Sf8@$xsY3}un5FeXRvxy zq~J(>t!_05xiz&tnRjrUHbevt8VmQud{1{w;8PU&CVm#%XH6)_tNkCUnyp_XvYW&9 z{aMJwVrN_J2ylAZfO6)&#sC%l=kke#PZxhn9)ag=JaF~ha=(+HreD_ZBhN`(LFjva zm95MmcZ*)>f)7+Xhes8jQ$6_4G5th~nn#^??tpRw7=o*YY?ZI^@)tv?=bY1e<`L=9 zWp|n19lc{DOnD(<`~GTN^+;VSee5`DKXon7%^L&bgyuGde!=L6E^4;9Vgs38Y;TLp z5Sj2ni@H^CK-)l+!>ZozGatIUs>xs_ufgoj^ikk*7)s2*FiZ{)BjTxrbHWN>85&{F z!0b2tvxCt)TP$u;CI0dvNkFN0qTV^)tXK&3Q21CO7#w<>(L>YQY82}it@SVaS%puZ zDWUhcm#Nt=Lfm4C?vatm`L`xr-1Ge4SYO{UaJE-`w->92#J|xNOw3r=J_DOl&*XoI zNtn+tFF751x)rX}+ATysIp!A9u!O{#-NM-E2J5FH49T+4glO3aOKl%%UJ^GEWmyjh zlvH_-al@=q_}92FFoe5>x`63MGt&Tn z@1K1F8>M0mXH1ONG0-VBSi;p1(Y2kId4`d$`OLSKoW{q}{i7uD2V^xJNp?mDlSy!x z2%E-&DF#M9u!dCUu?L@3QY6(jp`WOmv~Jf<39(^dG;-d;E0fs9c4Xw6B&UHzOb1Cl zi96bQ*DxgsmzHWC~8g$id^zM3)qLu>R8yf`OCqs9>^J539&eDClu)i*v zF#aIBr&-om6y|Vrw1Vqi;^f#;_Mb^VV9O2=TqQt~>UGXvOtKK>3yUbdc!D%%J( zTSYNj2Q}gK_?cs8@9`fm4_ULfB*iKlF1^yZ68^aRX zV~NFj$x+&oS`Y+2UokS}oynL{*M7wrIGxlt(HApu-R9$upP`NxiV3q9Oa&V()`hUs z5*1@v7WgJ^y;gbxQ~H0M=x`2u{W9D+zv+485!<7u5r}P(>CBuk>%$Ly!rvrn!A}>Y zO_>O@DS3(jC-7Nayp`M2^t;scmLlwlQk9@Ul)cQeyFc1w&9%ED&c_9!_LIEBJ`2ID zb7bPQx7_vAg}@P*Z>bk=eTK=q3n5O1_sl5W^}Y`tAms&3&!PkulFo7TyP#H#7+q&!6ih8^tCat5ec&C2cGp1Ae@dk=L^fBg01 zzK7>ytalbqyS4hO?bWh(vw~{Ze9bP22bM8s(l0Tpfuen>w|j-4-ts#B>GgGW|87jP zuFu_BGB0Yr_wC^4FvaIMIK+w~6tk1ez~4wU2Wou;mt z4J`AVfbQyEa%xJL9MBhg^nsZSWYi}dgpz5-)lpo%Fi=7m$q5~j}q+%X1*yNKw}O| z9%R0-P^9HfrHj|v`(Dd{x$Gv34TJ1FshTZcb}!!pyZ~T_IJBr%2VEq9D2t&XdJb5c z$nV>~fBid9Ni7S^XzS - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + diff --git a/DOCS/html/stm32f4xx__matlab__tim_8h__incl.md5 b/DOCS/html/stm32f4xx__matlab__tim_8h__incl.md5 index 0e577cb..3a1e84a 100644 --- a/DOCS/html/stm32f4xx__matlab__tim_8h__incl.md5 +++ b/DOCS/html/stm32f4xx__matlab__tim_8h__incl.md5 @@ -1 +1 @@ -8d822c24e6da5fb522a79a20f431aaa7 \ No newline at end of file +cdaaa82d7fe4a2d08567f560fcc7775b \ No newline at end of file diff --git a/DOCS/html/stm32f4xx__matlab__tim_8h__incl.png b/DOCS/html/stm32f4xx__matlab__tim_8h__incl.png index 3ec992617a5bae9f3a2825b1fa1b4da0ad941e26..ae4eaf38216fcde9856a4914fff5e1a6a2d354b1 100644 GIT binary patch literal 27974 zcma&N1yodD*glFN(jZ7k2+|GGjY>%O&;zKXQbTtsAuXK)(gHFx%+P{#gOua|!vG^8 zNQ2&kzyEjFy5G9%uDe*vk>Q-P_u2c6=Y8I1N9$^1bp0kt)ZfX_4oGYQ+rto7S>}dHKpeu-`t^eZrl%?L_3dZ!tBBa!0o5a^1a8OWrZs}! z4qs|x@;?_07sM`cm*om?Zp>K*IGa_|@A{SHx~soPEPKleWw`xr_P|=y8Qs%$mQr!! z`E&y*Pjh}?pRymIHDgzCOmD5pUE5u9ck>84Wj{iK$z6}HMB2FY#TBiM85i-%0-3<; z7v=*bJ_+F9)4qor$s|;11%HV2EAkSMmMMu0sKTX{M4`S^7GAJAxFtfZ6#etB2*|wL zpYp}x{@QU|s%nHw-O;MG)eq8OT!ejc#g?|nC)=Wg-R(+k^0y#L|%EXML5BUz#KG_p0Vjpf_WDm znRf1fJYzDQp7tx$O9}L4x&tdlo2D5Vb>x>c())2?tsozK`hocRpsQbH@rC@jbDU7` z03nSCPnN*KDDYN!oEZn)DKjd)o-V-hii=A%#}$j@CXH=e4C!%|3;bAMpx?PEzGN_H z7f&&?%G#paL&OV}nwTbPL=SrAXUt+=4zRmX=VVXs}#oSu3f#`2MYpSaU}Xa(cy($dnFbgWR?NMy{dVHpTJeI7_n z1)aSV27dYT1tP@WOGs@USMDSZviaZkz|OK7;BMni^XAy<;#&4aOSx?YG3zp)u$9D+ zXkTVveRqih)iiEJX5FTS{OK#&{a;}c$qn(_aYCp*!VHR+0qLMTr%rUax2ia>YA+)+ zqG=@qpB%mxU8?EQRlK)D{JdD?`^TN$C(C?U9sQb%BMtFM9gOAeAPEJ{GdU8&z_?S` z3NXtUCn-+?I^VB!ZPkNo){4ubkm9|IsDNe2UYUp9h^R)(fl!XP$HI%I1GnPpc%eSx zQGamE62#(fc?aXpucWx&Enx6V5ocB=niFtyQe_)U8?n_RyLq@qe!Szg-yc2A9u% zjPDORMN&Nv21UN#1m4SMowin#v;Ta0#GZ1NJA7<+)CS6znLnFSX8lX@iJIzAHJJZb5IL7 zlL=BkQn-D9vgh<*=QNafpIP-}2_)<{4#bTi^N@SZX%(XdmJ;88IsF^1-0Ab@aKwC_ z+~TSJXrij^+LK;g#Ruh)!tSp=({rAZP1*>HrtD%g_vLI>tuYrurBlG}tVd=)&KiBX zzhn7$D$77O&)b@7u`ceeG%Nb zK&rE8ZPN4KpFP0pCbjWr_8xAulEyZ0KUSOof=EXZtNh-sf&$GbtvbJDT{Jfb>Re8| zFO?eOCgiGilH<$~5N7kkPGBshN;5cT+-F>ac_n~77+4NeFJSuOORfbMa4zDR*{)Zy zVSh($6T)Z^Uul*>{qDAFS7SD|+S1kZ=S!YHn67f ztU*xiQ_mG^j@9NQOLO%Q`#2%laAXa-9%o%Q$sb}A27B%Ec8|G~!m{=bqe)sHS`!X# z!BcD8J6{rufs@A^?~%GuDoEq@>UxMo=KK|2x=sn~C<{|mTp(7qy_B|&8%(DXpmHi+ zT_+NXmPm>H)rBUNuxFopA#LB1-`^D*@b@_OM8Q=~urKqq9pJT2@YrB^qF7Lm^upFa zlP~R#i9otG+04pXbV1Lf@o!yD?}>)~v#OEems)5qoctUZxUFBGR#>dh<^>qWJkJFZf`CEiDgN6!P~jav)s?!83`>^+1uz(-#yF)#T4q!)J>j*i?( zDh9u|hbT1P6WR@29$nL25-K~sxOw%b>hHyP2v~)i^lEl*=RnTd>R>;1wicD6_O) z=ylJU2fCN*NCD&o<4lh17bTJXKiYdz!>!T#$1#3R%2Up5~&fJM0ToVt8 z22WrjCq(^Tk=yk18-ueVOY3X5h|@oVg@lMSDMf++Ak&uI{T>Y4D_2OFoAme&*w$rF7{xKG1S2 z(E^on_h$Th^LKT9UU`ABuo>t!Qk1G=WHzJ-wo|@7g%Uxn!hk%qRNvi8snnpTqg$XH zz6$z!&HntN45N8Ny<8$=>?ixBd+gb>R9b#7_i79nCt{;Te@!l>|1hbPb_ye{!<_pa z)@UuKjnhFIXUJT7cw_s#){mnP^u(Oh`KSVTuOxV|aYPOX@pUoGv=`Lyy?F=zjEZ;0 zTIDg;8lLZ{+ZUhv=Y)qH=oW(3F?}wHv7|8*)s8v-p9Hy_LuIn4a#e7K%G`D^>=>A6 z4I@p81kv0ssaX5c7s$iz^4d?=-@Ho0va`Q0{uT-rP=Jz}yyCngKOwA<=b7cqH3_%e z>WMbIb6Wn*k13wa(d$4X_c4U@FgU_{9NnERRkz|LZmo$lNsJwgg@DOE@1rCLul$F| zdyN{foTNVtlW%Q*a=s($yKGnrst7(b!3h{W&-@Ig7`s+djX{p7A#8F;(dPJEwC z6`ZM1NRt^}DUW0lz6_bv8dHAY-^L@fMqXanVO!d^Ej|5m5}sE+bQX0we__uzLa9BdniNU~y?MzPGMzWB-sUe38OGP?X=P;WuaftM7W>X1paI&}s(G2O3%O^nm`M9cJA|xdRie$edta!c; ztmTK`QZck4D^di^a_u&pWFvuUt!Oy>-mM>E9DFw8q4W zD6}1*WSt6r&nqNrOk&d`9KG<=>Wn_6zlx#8B9C$Z;7}8KXt?%1htw_!!`J&6Sj>5S zPA&7mQ!D}O!kKp22in`H*ay-JUh>wOrvQ90jpb<2OO?_4AtNDD`H&NNTDgzp3j0+7 zA|P%J%W-%^DWLKGNM+3|HCFrWoY|aTOxhlln_shI5{aX zHnYLC(x$an?|)Ww^F_#n6?e-R=c&30L@=sr38HZfH)O}Wp(XPcOsR9$%m~>h(d|@) zU7}h?Q4p~4i$$*%OkiK;?*#^$l%#2+ozrE*FIc6Ob)OowU3{S2^hkK{i#4OL3{Y11 z1P-W3maZ}-v1Kd+1_5{SLEQ8g4qBuawxxB-9p37@PJbQ29aGLqIKpCFjUBZ!6w(*T)sR`l4ja1HD__5>i2A!;o&bc%q+@esa@Je!sWp zEuZvJN&v~B#~{riN}T%}2yS=eug!N-i2Lku#gGMKQ~2duB4T8=`BNE)%NPgsWE6saimwG>HDv z-`m#nrqc83hZzM|e~h~(f|4IAZvso!$VHjx*%Ug^u&G>c%pF>i`|mYqZZX~it?d91 zLL=OaJi#T8ztaoKZG6dz;>k7D?wx;@6dtU#hP`LoIS=*&g0%bh^BSYGj&B6mXsiQc zhqFKdrz}>Cg}q2A1+de88f-AU@}tKSipe`DPy-go`4#gg3wa5|Sh66r+C73N2Ok1> z2Fw(F#9)koAhl4(kKkZpiJ*?gxQ4BMQsCa#R@6DiyO(14 z(klMHVvc&!2^^FOM6IY@OC#*7&%)J>+Kir1?o}YTQu?w{Cw~Cm2Uyz$mcZfTd7m9V zzge$5^=4q~?_7FonlJ6w>-{ogGyXTn_hQ##vYPH;3mNtzyI~M zX=J?o>B)GS<_aG%F29Y^b@m}rJkJ^w6G2GQ)RSe#d{}C9Hd4m(T^!PHjUE^kC7q}- z8NO1fuB9&}gq87_0WY*p-iR|wGQr+=(ejB3PG@8L%Q)KX6L=~jGMq79MFyhd&eso8 zpTvGF#&@4tcUq%Y5N}`2o$*P#`Z-Z|tc=dtS#e*`N(n(Qnps>{i^*pAu0h|9*Q|ZtPGrtzITB|Q{FmzIpe=Rax(m2NVP(Y zZ78r6sC;lQ>Hb5=qIeTztSec18|v;)7QdRbXz@tvFJIWlorYxWPs;)Yl!If86PJU zuX)77Wq#Lm7mIQH1&U_Q3W|7)ZCAuIYey(}S2~%fta{oxYy$v;(y_cjo$*X}W$}q+ zl(=+puXPICvwkj1sz_TiUsyKRa6SllcaEsCy4PUu$AvM=ew#bOsvHX^i~ zG=qVfnj?GmjUn4t62dYT1{xx@Sd1pjX=mMryaELO>P4OLn%U2$S0w<7?dnCbEeNxkv_4?PRYnbpi47_AtgMyBvTNA!Df zWE8qBV_g@pv*mk0OSp*PSsaSjP~+$Qv$_E%#D1gCrA5@Ww051PGZ9?~u4z5Su8n}g z+)oe&-Q_b76Z6j3vYhvIL$7SCU)&bLJ}+7m{CbK=&f%OR<=>?q-E>!aWuITaNb51j zYz6~KTul;2QpmS+W&XEm#pst5Twh{`mlFveqm;xu4}aHT?UJ${yLL5X@1)SgZ72=` zbyKr>=19mH-HEzVsF{kT#!43Dx~>)bh65|2%$fZt8t_CVLg3y=0Qt5d5-Vy_Goc~U z#+i>zL>WHw-p2*Z=_`L%HZdOvlV9F{=!*l;6nlkRy!IC(qpQPLdI@0a)F`mM``&M_ zmMZ*wTv*ja8i@5REamRdS8T!937oa}>kC7L?rv`td_bs_7O(Xa8T=0l&t57wC_c5= z4(y8qiaYl02E&#hVKs%9)mRKO`kb8}(DH|#J{~MjN-N6hI8h13Vr+@bn#Q)Q6Rf)N z!lPaSDfDt}jjO|llzQx+x?@zqI((YK*6uyP@_7IQ{e-Ps0@3Dh>!a+xr2eFC{=IN2 z4fLP}te&zp{gbT4^l*RZ3D#TlzZnrJKN^ivMa~bxmq2$9bzzAdzt3e=L^$jL!(=8h z-gS{13hFYkl9Z)R?ra$Y@pZe&VZEZ8_$jSX4&QRP828OL<&uaM76_C$aDxuUjhQ6& zP>Ev;lDWa@w_hJF(R?*Pl|mGBhC&pqUyKL$@Q~j=b7p3V$df%~q|F7^wkB;L6b)qM z2-@1mR}0ta#3%e2r^wn_X~eP@Lkj(gvswL~l6S?sK{Z<%odvB3i!cklQmoeUeu2U` zOn@2%GX>F*&QgiEosAJZHB{MWXDkfsj7yb@p;46WF9cei$)~z4E;e*r5!l+O9h^BT zRXDl5&*E+ht4~W6Y83PI@@`Ggi%}|e-kB=lJ#yP;*GOmh>9=Bh?B)_`SzTID>EG&R zUcnK!ciNX2aE1x-?-)9OeWtJ5%09SyDtq$XfXNeD1SXNfEK!p2n!PY8%EgK^L|rnu+RmW7 zMQ&HYwnOYZbk$4Dp139>;J)9!IH;N9KrnSuN7a*gpF2A8EPR&5@RBr3&bK5w7mlk# z;xAQPmGBr|n(w8)qp_^fyAG@$L?{o%r2kfu`Q6j?yilBb4j}l#fWmwL__Dm8yUT!| zIT#5rynUJ103kc@n}$EsURmSqiL*2*N-3PZDR}_6;r*x^H%q+RGCRQ;cDsIWf5uoU zjfFjrUE>3(JGOyhKy?h1^O~bM z3Z(vBAag5?7vW?+R#Px)h;y2>xMWV^)QQa=!1!2Qa&4NBYgF!A&frCv^JzX}+cu1#RJ zQ!kj0GA99aUvMe@$hhc>{(L_X#0JQ>KfFrybyrI_LQ_HyeiVa6D0nqj1Qv;ob*nKU zd^5EmXHo(0BU?zAZG_qzphQl(6t60W4peagnYai5xy2aGlGojL6Y!cyKHg{}0H(LN zW!{|mdP2|PFKNAyytd#3+L%xIDduteMnINjqGf>Z}g!S|Dz|Ac(5#(OG%KCfz3 z_ErX3jkl#Kp;6jDC1)=kDWfBf5P1^-7uT3c0}ubjG{FTYYk^@Y7$6XOvgyt0=#FmLt zQ?i%)zo^@D7DDxG!6{YQU{+XT6q4-J$*o{CxAKFx<#=z!x^%$y+_pGTdhQF;PY!cY zEARCPFQX#w(Fk3n?myA|8={i^R~WPp>esXd;1U*#n;bbDyoTXtHr)csFA4{&eFrH2 zc6Xl+^SdF0F~~$7%7J#4lrG!mP-AzI-%|d>e51%QK``M5b3(3NdtK*P3=BEU)$lRUZug_h;57)-R?FCJ-%&1SBbm42C{jh_kX%oG=Tcr8 zr4asN4KZ3>_XB8k#0l*Ky_p0hia@;cFZdqj3P&*!;0Oln^ z(q%D>9$Y1wS!?dR*;5cpqmd5Avl*^j%NSD-U-nknJjrs{=&O6^^N`M|6WO2bC7$p87=eY zNw!C&@uP{Nu~vpopZYVK0HP3!tM3lSyLbA>XO~M~90piz#D_fP5PW)qAJTyq@;g}= zEt2ygOhjY8u^jP!@(dB@)m=Rs*^FMsXVdr>^D$xZ8$otfQYtNAdmc`ps-#5LL!p|r z7yRV_6Get1Tw5*-49RtO69{2seRQc95dfewU{-WYv%8xbZI8Pf0H7h4eJp5JbwI?1 zAbdp)QT!BDEdb>djNi&dHnwDB*pya}Jjlca;Ur=^8k)|~t>0OsoXVWCiO`_dwklin z_Htu-(o~wESS@AtXG7XR3LwU^2^yUg;4NZYvngV6ec}6ymDj2-#UYBqgQjz%X*BK& zedPqpwJLru(wG`&2PH0x@p;)ZY+Kt;F*6$WgOx?j{SOTuii1)MN;yu%z1-w#D)I5mCzAsj zADoNUD0WqTfx1sOIzU~}UdMaI?k!!`c_j)Yj{l-id_gtuQ3(k@WCEIbE@Mul`KjpCh}3 zG<0cFxu|n6PZf|cf1!Nktf4C&ciR5Y`l#O@EKI4k?V~$(8f3?x!`cafmN7)g{B{YO zv-Ubtn=_43Gf43t*GAi{>4#w*LdUdWLvy-6x*J;*4U@GB<8YcZ8GFM2EE@Bfm09Ch zv@M*0sF241sOK zpRlY6fakEWrzSx;_c*jSS#dQW&mSxyJ3VBY7H${0QK~59xWE7FssLbLe!~xRhw#+%VN@#I!C$PO<36N z_*Op;4BvpuH&SMZ+sKS5d`rrraNOGi<=V`AsPcJ3b#NqpgMOvma_a~uYp%)0mXuWu z-S8qkg|54)o#p*JscD8O=e<*Jrcw?V`ZAmAyV*$qThp)0w!#U?k&XPgyeIV(Ac*{j z#Q43YHi61IsM1>-PXJ4rYRnNJbrc$zw6~jOQ8_p5{4BpK#&xW{>h8aMuFzbrXG#CN zjxlVtwSeSLX|*1Pvc9AbO~#0Z(qv7L{Ii* z7MLQ1-}OZ`{`f252wD)C=m{&bD18%2lYj{f%TKnc{>M!*8UwkE8-l<;_=-+msST81 zI+ls_&~KehIGMluy<;!*Nb`$!X_q-KW~Ejz=2lBYGAjYm_ zWz_EPyMy1Sn~&Q$hMj%psysAV5YAC?LNp3pyowmc2Uw;me9p%V`X2-?)v4n#bP+Is z#rB5wMyP^UV9Mgy&(tHlIK%NoUR$-YhU&7@w0uA6suT9Ni`K zReJq=aIuPxg+LCwgm#_)Sy{Wl=V8e85BEb-FB$gyMhtD6!-lJxxuWUO0~7gaLLAmc z@Z$S>6M_|xES`Ki_(l3)JHW(f_+P|!m6<1}68^5#IzVYcDTBurztMby{R$q&BUoTP7%zn7%V(3S6T{*!y-OzFv4_*3Lvi@e<_X1#4{xF~h9t2k^jdXTM}IDn;q z24&STerI@Vpz|n8>IZCkrif}jrHX#eA{&q$xEHvUXsa6u^`x8Ar^pz=i3?n*dRV(| zY9F778$qqKFb!`FXvTRO8X`9X=llo@T+@C~brp2Q&vehF-$msMh@70fbW+F?-RvYL z#6JV*zF!>(4p!%m%)9%TpEgDv#vk~B2vXSuNgzaHV^SECFm}UMM+==5+I(2VLqBjZI5G{+T|27@yupijtGQ`A5%|Q7B1^hJB2Sut~u1T}*Xi zoUL9>R6?{JKVo80g)I)y1QI8tX}Ay0O*^k51qzEQ4`-z*BSu00@uwjo-v(rTA;1xh zd;Ip1EVAft+i~mYHtjMy`Oq+yjwXV#J^-pI7X|((!jZcPxGQAW^hic?7w3^hzy+U) z!uq+E5^5x=Q}clq3qc`4P$Ex=AqxJl>dgxT$|gxx$w3yyFrRvFSPI$D=F? zqu~k1NtrKNYU!nceP6DqL_Cx^P(EPi}bw(7EBK zsLGU?Yqd0Ux$~WUGPhL`yxRBZUv2oD4R=vSa|d@W{e?M>EcC{n!KqN+O;q(s+^C>{ zQ`%ydGA+Vr!e)R?0s(q0UrYxt8P?RoAan2G;%oNp9G&09HGF`jw~VFm0&IYR`S6=A zpHLdTvG|!m!a0O6mDctFXy-%3=FhMFyNjYVH^o(#>$HqHXv&)+v6a?ah$UZym-9adYQ;Qt^8E>&=)?NZ z@vHQ)q%tsiFhW%UjXY)zhbki)CR$gv)K~fOEHSMEWpdvr_9s5z8{=aC1Uo%gq^X+T zt7w9x5pq^cEp7ao!Ms1Z9H{2Ayp4l6P4%eR(j~({B*o5z!F`w!a(niZC$Rr&K*P-V z&`goS9ctS^w?7qh%_E?gRa8^K(}j+GCDP!eOwsam=zvOoiY~c-D#&70c!!3Pj>u22 zKoh9&ZKz<_e_)W;90%2zB(+QaJcp6pa(Ok$Y_?uzY7-+|;nM-^B z!~I73zHEI^ZG^_EojKVZC=|+&bwE-#vKX=9ANI`pB}IycyFRQU`~lznb4Fbp@WjHP zA?nEEyTqHzc@tIn%pFHopg22MYplt^Xr1W4x$TU3j$sKXn`ZpJ03!sX_N`pvpXj7o z&$kR8c9QSw+0JBI8d-WY#5ELr5>hUBO_ZSuuD+-Jcu530y>@aijAtCGcD(M2q^+56Ixzpu?ZRJ!EYcF?a`6JZSdU){2 zF@oR~z0O5$<&_duGJmsp$rl!)42S|o389giVz#?k20I32H=hoN1-)jzsKm(bn8A&F zKC8QTaOKk=gMq;IkJ#g7>UIkvM+H=Q9rZX_GDTxXyR>URjtsapv^ju_9;CGMJ(skM z;H~stb7Wt5kQtGbZtf`YYu4JPej~H5tz?}rW7}+5Ex?Z$&U@Q%kWJ&Fm@|B)#m5E| z{%R_#b$jDDtJFv_E2-v8@AlEgj@7>W?v0vxC%?xz9!j^Zo^gNwdFu<=ivXC&mWCvZ z2p4vbk?cIzM4)ncYUX?KiU;2D(~1#>nxz)=wcv=xJII8R=NCno+|oKj5OV7Ff@w9b zHkHO&-=ifG&l#KrGe_mC!jm2hrfA0Fzs8+#nhg3Sven- zAsk@KF)ZM1q9{S4Aw^)33xRfF`QgPc`Bs|aKNLZ@v&voA5r&{&C9_#a5_1SbW{No` z0)`ce-6(Ld(*n zSA8;`1QME zeH(m+;?YNG`YX0#^hx3J__6>iiB|E*izFqvRABJ6;vTi79Y3DopmA6)$9 z&7L^Jst3{|x9GT6sDcULfOlOekzdEOgV&^WN-CfO3@_cMShu8yby*0Y#^%EhcmhfC zHTtds;Zrf`0EjbN!!mra%!*hv**7{b>%Iotcoc|nN!$y6gS|m;2=Q%9|JL?J!GU0C zn*X^e9nsMBn6@`4v!vT>?QWP@PRqFpTY)nYE+Ffi=5ioi&CNtLxj~_}ov4>^u!F?H z40)EhTG#yoEYlNe`|1B#YM}txk?Q|p<*@@F)10+Me>-_gPU=W76y=dLo;E$V(_~@p z@IsOiZgb>6=6p-%z+Q_vAWr%hE;Z@^*OAgY1;WDSP^+GH+|1x8u%{J&)DSGW-zief z!RWB6#p!_MK=ah;uzp!&?CA50Gz?e(C~GQN0=$9JQ(@)&nUB>EDfzi z3?KwZ<26Kd_HBf}UU^wby3p4pOIK%|+zVj;&o==^q*LQyx^PvwfW= z95z>U57r*rF|n!!(d(8B{Q?~M(=9>x0W}+iWdWoyo5C+ZTmV;7oI42*{z?0BVnuw} zWb`)&-;jt6)kewqDkqdk$V0jR~?%Hx(<`!SGz4(-jKJmJSBfz_G9li--eEeJFnNC5F8Ognp}JCmb6BRV;n}Hi$O2j!*2!H%D1UG zq1BNa(wpv!5U@Rm)p|1vm~Y5-P^fJ@CLLLRNU+e7D|QxcemBAO?Nr^B1SfTBS|J1J z&(d~T2Ft2xfcC(<8Ll!{6t1pM@o9HPG#(CXP5ae`AWjOsTA-M=QpgajpS{kEtQRe> zCqJjpDFMWXokF)8s|Z2%{+cT<5gQF)C!;ZEx*etO@Y^14zdHD{x5MfdB-pLYbwXGf zh>FAP+E~MW2&mk){90Rl5eElaW3IAvKr`=6GUwd{2ZBLCkDx!VYXFUd?)2~|Vbq;? zpbL8-ZGfP2LwMPzWhI9G=`CFdw<}j_SBC zNwj!S^7x-_h?CNe)WoG-FKq_fu|KY4D7?v1xtrmX%@7 z1GhugkGM7c>Wl-3l(G&+sFlr!+HEe8ZR^qo><`}}8u86_8FfvRlk@EZ79)X>gz34{ zTSsQd&YRO+a*zN^qt_7@M1i1#rrVV?B5%`c&hSG4ddc zv6LTRp-_eG>U#fZblC%fjK;gD){D1g)d7F2cgf#E`74iSv}->!VLVUZB)-bwh=0Ja zRQ+Fb%}4=Z;_^sqTdD#a=icsp?6)X74n4}`D&vs{6I{D^*t>9sW&h-B(eN=sIpi+| zJ_Xj$Sh$NW)%oE%+NgkVUc@wBD{f@s8v%nrP0@izfc)Z4YwM}&;f0g@A~!X^hfREFlK+E)GR@dgEEf=MV07v*4;3p&>N|_>EPDu{cZ70(ALN8d!74Inbms!0L5X z*Vkt!H9C~ZTsn9hzwRvRum&N+Ed_@302IWv>a0w0NtIf<`Otd^WwZCX=~l^beogsG ze2As>MAZ$ydZxXNP2>syx34js`~Z!IC)g|xYokh{cqJEUMV?HtKo{&mMZBRkN?uQB7`|4p1Lb`G?VAMQ~mVX;!7KZmSgiCzjhdo}6d!Yq;y2<@90sL zewq{V=%**0a#rb+D)7FfIcY=GlWt5HV{rPO6o4^|SJAJ-sk&H$lT})fdRL>O&4q6A zudNJRcZTO@+_)gn#18S`T&<68MHnY5D&OigX42C#5x^$2`Ihxs(P2*%M24$O99WT-q(}T%K{U<&Rr_F zTWOfR`|75}icE^$?`e>jKN~BL`eNLCl~ui_T*C|dHr0SxGa_g ztW66cd=tBDisW!0OzN+e766^dPea)bQF%bI(To_gZ8G!B*pKVCv!vSoW?hf=iRzD|oo+qoxJutVnN8z2Z#pb{dh=$$n*Hp# zIEUwIv3pF{&MhgP)#m*}bTMayvQvRlV33UnD@Y_dMNZi)F=;dj?v0gS@{WimlIVyfa~y6-;nS4YlRm33f+DH@#yQKY76})yI~wXEfWTB~RJWi0sEN=R z+}lV71>?(3E({9KnZ|LydKDpFb{yHXzvB+_tlHn?Q%nK`*U7by%RU^1aPd#V6D04t zXqNDlce76w3#Jr!EfKpv~f>=CFkw|-Sm>TfDMpJ(sC!{B*pZP;z#lAPH+Q~ zixdFy7^6hG*6qtY6gPUZFTH8{Kp&I2z|;U+K$%SmbIRil@rL$i>Ql{kzX`q9ww`&P zSLP#@b#b5++p1%fZF_pq(!(Z^)MioTG(5Z_>Q?` z((vLl%wb9PVx+leuO$&6)ZU*|M`|3G3AvWrUW-d7TrqEZ-u!C?O@g+ zPNj25UH177#?u^_6YU_-z&`TcFBAkPGd{ihrzt?oEp9L|a`(`OL)B{}bF#v9I<#9N zl-_)6zyo$n+;H`NiAc6ujb4CGTLXHnjm>bUt-3PSo7Ym4op-mJonel)i&GB8t0hw0 zJh69nW=A}8EVN|(o@u<-b+zYY=)=HAT%8Kb_{me>;w#4Ko1as_nVWu*q}|+}M;a%= zD*j|egV}-)nogU3qSz7hUg=-6v%eW5jUpZZ{b4))`b{+g2&H*!1}U%QkU@w}?``{i z(oyJezN!5VLt$6eBR`K=$Nsm&&;(;LH<=@{{p_fDvUvYc7&}UXP z_d31TJn-c0*?JnYb}w)QYjCVGcIQ>6f)cZWy;<8`;HM&^xh`X%y^^c;0S?EG@6B(X zt%27r3!zK<9`#)vNI2t~w7QTZKu6sRr|k-;^5wQNDAjzm(HHNu1a}))w*~%p;JdPh zroJ>O1x`)IG(r5lrO6}60x0{B&`AQI_lb$3e4`BYA}~|4%pDwDm%sh?Qxb zvj>~9Dg3sAqJlq5b<9>gIv=PWXb)>AjQA5TMWd`1@~2=dW!D5|bG3lD92qtY%1KZ} zJo^N6;sKG62p>7F3pr8=w3qYr-JRay72(L+T`i5IKiWBXH2B+unF^>JW_pdooGWDi z0HuJZ{|k41=)2dSFKBv5JcuQ#S@RFx9NyRLu(FRdmI)IH^Eu(TXu|NZ{*raMcZ%Pi zwJ)u~z0GTxfPI=yhw&52qLthff!njqKy*12l`r%?BQ!SDp?7nm-3OCDT~8Y(1cJX$ zo4&}|&&~KsbN;%00`0!zD*)2h(FP()I3yi^b+2{USm!lBYo#g)qAHtT~EF@ z#Xm?BT0#Isuos|hvXm!$2SPK*CbH*vQ0h-E+bvda$wu&ddLV`w-UqNn=ETWldyvW= zK;$?VDA{o8Nf@csz4(mp>DX!ch=Kkc-qNfm4qjGW-S9+Yx~8UE3f!^$)q)uDO7$$C z;20`DarQ4=Ruz-GEoqY{vbZ|&J>4{>rElV54Kq1>?w#7jiT2yP6cRc_M97OnrXU?u zhDZv8#u-RbE48{WAqgm>i)AiEQ>yEs6WN1|PqG^F)$V+Z756x4(X=^Qu+8SpsU~6u z3TKdM=;2Pu@n-xxyn$pc32ZIkM2g!QBcLo$=Hm+a@U4*)9$+9boSpsK> z{&C-0Ab~_|DRo~;#1N#YOtFT&b}=^E03Um;Sq?ZiT`K!CfLY6L9ZQKeQT@Yn_~FNH zVce}SIMrHjS3=8Y(b`#4o=OWj1++AIa_-@TkbSju7w6(uL?NmQ}3N z$AfQR^)`w~>NPkZ#Bqa`eE+t)>0+pjrA^d-0_Y#&2BQkO!GTEgu8ovAk9t70>u?yp zs&Be%P=PpRZ!;^4c4vfGI>BT&q;?YAk_ zJyudT)uR*u^pZGS`FilKKHK=gu|h9tqd*wWek?Ac+bhor=qGZdTD|g#8#8lMO~+c* zN7gwgIH#p^^C|;TShfRK7SZnyi2Qpq^$i;%G(wjHU%9PDx|C?ZX;GPgqy;UlUJfwp z*lQ{kV5Vrt0WU^t_g+6_9o*vSCrB>7*6iYIP48~En>a!%Ecs48t{gC$mVXsZ{c`DB z^oSRCp^_B3ui9n!yeWE`eWeM!3bNA zO)Km(VDa@RCM(o(vA^`7(eZmN%@|ccYd9SQrdz*!9^&Xa{3~MH+3y?~b-Wxdgxd%} z`@4ZI2It4(@>Xt8&Wu2m9XaeRKu7`*&KQtd8)}rP=>S@axmkDD>i!C4%2zhFaU$*m%Y|QEp56#R8;hLD{!)pGRJYHJ6%5y|R*lBPeLKzOzyVpfA37 zrxlf}wF8Mastdekn(A07_gdh<8KodukP$oep??J6MFF`^;D>J~q@SdzlciwwsqcH; zZa(9k-5Gw(EY$;SRvpqQA@)3w;9RFJvhHC@^}a02GMidU7dcH+2kdF-=ceX%+vN802 zVDcau^8h$;wR5XG#l&3zC9fM{#^(mL{9L_Sy+a`O3r-Gdvx4?45tRzv*Q zU`=m_QyC=W1jIzKX5?o0yrwz^W4egb)?0rqr+F0f8gcTPDY}2g2hO~)L-dSkLdbl! z80M-n{n{2#b=ZTmR&WR1p3C$VWIfyDJ#uWquU6{w+ zG=?Ae^SS>5(3nFe3En}I`EGm}R$mMpCn2fwa#wdJZoPvh8d16kDpov5^mGW?=rP-q zwr*mnJkbqXBsc14L9`j&FJW6EW~haf>~Be{FWjFT(=KF@jd4e>dk5WGb8+Qb#IW~+ za-7rqs3C=B=Q>XFsOXjXwk)gGvE+nX>jY4n`~~w$*%P8fGb3DSe zGNjy@kRk8uSI{R<;Tl$EgGt~#ux2jzfU=w4DqF=2ML$ENpO7O-4bz+MAzCw=2VDPC zAlzZ3JMj3K<}u{B;2{kNw(tF#Ll?v+B>vT=Ne9jQp@|4nF@+o@S)V2X(Vo7&(Uab3{0>@MW=4kO^0k&cl z%@|>2{B{z1javeT2}55eDn&^&!~`;*wvqkU)#}4|!_vf8A$*X5j(N3$Uz~Sl6gYn;G zpCV$(2wrX+GWbx}S=2k13U1wh=`+r|*IlA9XR~4h;y8z-@`T(KSZ3JjH7Q!jb@<)` zw!iy9Vi!GQUEZC)`esW*5jgYo(6G0iu$o&F$O{Z5j+-uF`Ja|P4(#dy;;!k8cT@r= zC%fF=bnVDcI1p~ah=+J>?QX0gUQqT`I~CL~&-h#_LLv2V*H}m!q0TpvOB24LX|UE- zyuFujw;b15xDRresB|Dez@0MovUW<~P-c8gfN&&_%%i-U$?#&i!M3Fy2*JNgUq%dP zThrqGEc(a?%HeSByK|Oy96k|AP$xv26bTAfq~v(~g<2J5X|E+)WIW41(@vPio<8}8 z%Ljji_6Fa8J|VqHq0!=dxL*Z>v`7(?$DC27`g;$ zC6$hup@vSC?oJt`kp^jyE&=Iu5Rs5BsbT1r4ypU{Tld3V>woXMU-&T0ntA7(=Q(FT zd!J{Y67<|EhJLSydWQpx(`YC2IYAZy4@kj}J*W{GQW!%246?A>^oUtnd%C2+b?Rqq zjO>*rak&J?i45(?R_{^F-RsV|a;I@;mclObW+V8?gvfD+h0H`hE-Cb~s(V|OGG5-; zHBqW^;DUrNo_|aeh&?qg;G0b5hV;$!mc8I_N7mvug^9ey#dBfB^H+*=mT?aIdlGaM zBa`~;z45+3eW%ELw5@yBZ}U4Ip#7t-gr!a(Z_66^NQ`L_jLcT2^Fj%Cn=An1cvopNh%PbLu)Vh@Viua}wuB`j5(ESEQk8hL} zHPE2ZlUk~vn+s`vNs&;~GOTj|1W|iq3iczec4M(=jgc4CSWBw~^w?X>UP>zBB-V5m zU2RnjW>IT8qz36R1CO9Y1(rJhdMWnX2`VYXo``*qO8tJ4;sa{PmLFq(b!J&4&8DU& zHj3R!C*ws@0r)9cGGTO7?*)pC4=i@uN7hW>)R z&QPyO>vi+6ej;KB)6-xEv1$C88jptMI0l3SqY|kNq= zZK8`Azwv{zkUQBbc^B)BX&|dg+HW}BAMcy9HmbgRU^4R9;?sWm%?aG48|&z9p?b6Y@>N7vw%kLFgs1myFvF&@4}_x0srMVQPh?J z**YdwX_i|-dt%f8w2*Ow6_1qBki-#bj%}j${C&Wp++wfnO(Lnz2Kqc)l*}XBx-^|W zp#hJI*@y&I@EXY1@Zwh^Tq;&)&ybsQ?y)zT55Hu`h|}#ucUqEm%OG&dIq~hJviI}S zCvv6pb6D%e{A2Oq{wv*TW|CoT(06ZMTN?;Os=}lS)w?UoN@qje;RRfgJgVfL`1^=4 z&(s9YZ{5B|#k>>QP-;aS7^LEddk$_f#r{pdN2-pXL&gE!$d(ZWWm(;Gy?)sb23TIh z3RkbWxRAf0LMr)0>xCGqWYoqvzuqrq7%cKd+!U#xJk5?<)LT1tdE~<*SSHc08@q-T zt5?(WIldyEEew;QD(__F4lu}CZt3v9_Ylj2v1#R-{itZ z)5LBJAd8rNax35*Y&*lTGvyQAAhcBa^3e5$-kjJ}jL(?Wc2Pq4^9TEj;)wQX@eD6h zcqCUl+?22Eyvy_A1rDRd%|ELhTR)tx3c?vT_X79lJ#l4h(o z5Xe`FoT)2d8{)TO*fhNAz!48i0&?%YM9p-z(&eAYUI669Q`3afa)oMltI9ecAK7H# z5HCJS@G{2cWEZB|zB{Vq(`g2qV~NY8Mh$50_NlZD8kLn+swu9wvHC0JXXOuoLW+RJ zn|@^LO5S|@{XaIJ*C|Sq;n8$0PjQHek1%Ishek=(B>4QI>iD|%Gabn7CjC}oB{*`% zge5;lp#3bL6VOf@u7?L6e7uw#`1nWzh*Q^E-g56-ws-1Nze3$1GQ5bf@&)3X=7t7K zAt$MdkIlnROXEb0e?CjyKBz7v5P8@^5ya3IvwtkolO7DSCG`nCDw6ZHg37M4EOtVlq>_GGP9Mo?2Xx=#o^|4SAM>A`hzw zUJTilXAT?}kQHr>6V(UMQk8hB3(I7_Keabu`Y!&9p}1d$GgrsYa;9L1S8vLd;=Ho0 zK~W+*E-W_&aIy)~cR=NwT=UA;Xs&1P5lQ)SEK{S?F<=A(F1n_R706aq!=)oID%HA6 zl7<3^r-m){@DakHyJP2Q3dlff)@MPTJ&m+l%831k zo7_f5ed{zMufZ||789z45W8krf=&YXu*=(3I=3aFIW@nN^T|M84Oi0`u7weHsEs)4 zt@j!|JA)IFGjZ$xn*suboptnl*}`sRB(R9I7PabWj+{t$K3;=dIa=Vl z84Wwlo-p5`RnBA)Qnd*ACE9DDZ1Ip>>-n$2?Z9A?mj_QXH98#k>6z>v5%tQ81q|zR zUNO{fs~b|-O?pcWBDD@6>sLl`JymAgA0j-}H=ywyA-U1cN_>4MkuiJ#M0eF284$nN z(#Xc|f|E!=i>n>1BP+~9|M?zCe!SCg8|&O2{k&@X%F%7s*I4ZiO9ZkO{m8Anp`Vdd z^z?9*jzO=e;5aQ5d!Vqsz7@t(k>*p?4nh!i7vg*@vHRjV90?pAx>8Z}EvVE~TrZEM zr9P=id6&|*YLF9ad%7}Bg3Mc0`^Lw-ENt>DNJ6rrt>stDh*SusCAIW|@^v_jL%AMj z290W1zp@Re;|5d(lHB0x<&df287&}!t`edSDOIX>8{I2W$Nr8_(%^pSQm2CFJI$HZA!tD3{(8#v?DO$!)# z-KX7?KZa24JwbCMr2W}|2V?~muuTl8YPlJSqSx(K)7w&Iuskckxi>6Spct7Lr(*%q z_^399kKjs*dw^~EI$u;KEAH1-zp@3l*ydPe~L%qUe{I)TE>5>Nz;=M0qMiD31E~ zYuYmzkKgZDRK;1J?s+TSvm$5e($E$3vn$r{ zW?UWvA+O0^_qp;|pToHUQHaN=sc7wAr$p%$xGIVs#XsJG#nK)WIEanQY?gkxKn6sc zEMjbo`;incq743i!e46>y5WS@DMMZjal~US?Qh9MQ>b$0^xQcSQW^eu&$Gc?P!`=F zkucS&pp=Fge>qSR!aaxBONmqAp-q79jkW zA(?iYy0G-!;DOZNL(bW~$sb?grA>=2JwBAEF|dkC>wX-<9d$Ojte_hYOwMm8!!D#n z7Y@ZE8`l;GQKVFC#8I^|=;nJ2(f%Q}hJ$vsmb9-f*!~_Uyu}vvN)^}Z1)?XQgubLS0t}kzF9E;J0|;;S#g13gC-m$XqyI@ zTgnHQgwA>@@8R=0vGO|gWYWKA`)S*H|5KvP@F(+=%M~k>A`<bxej!>oERGrzWWOW1FVtim&pm)}FE+!cGRIQXX(rG$4I46LALZ@a=a*FP@ODw0pVl9|9O-K+&zak6U7V2ZEa@X$ z>kP4Z`pb@P%kRaf%`^A=>Dgm(%&U&G|R0hUZ)vB zxQzkU9>ULof@w{T2b&A=_vnaeetW#5t<~=1o`l%>qB^4KLG&V1D8$no+`9Rk7E-4nnW`?w?ZLZ&GA#@6UG?ss>xLaya z33(>q3&)MTT-#9FYsB(wCy7+ZzQ6a32NC!)2EUPl&m;4pKL(4uhm9Cwp9tNvnqR^g zMjJhcx<(&g%TVszHaXSb)(0@ZjCyA}JLehY|B`x}6X@+mBo}w%Q!VocH*)6UwB{cy zu1c%FT9|h5%mvMyAszNvmR#F9)LVDAJN>t1%xg>hKLjjItF6)f61{Hgy0&b6S^bN6 z%f}peB8rL5Q9atlCa^{BRR`2yRU(X2J%ox6fZ4c}k7TIbVTX54Zqm2@gY&?M?t5w? zN&No#1UV3V>&Th=yIXtpws04CF&O)J>FliiyLoWHWQ1*?Z_)wI-qv?~EW63%6uHyp;A19dIoUa(XEiuo^fZ>oYzqVVXise5 zz^3z@qS*Q9Ek;~Lc1;id_!7xj2don^{C11qE2xL=r@LPDwOqzOwnLSkN45DZ!XSX* zniH)jD5W#_U4lQhq%{V+@UOkkXMA%I;^{++x!%E_ObcJtV(@s#*HCgkH;zGxWpU!4 zlm*g2F87uk2v(u}jQ;eHI@JgQ3UrK%GJ$HXeZaz#ldpv^3vDm>>nwmyTk&+8FGs^% zPl1ZcxKtEaLCA?Iit(g!Vt$=e*Qbv|f!=26p^o4eELOHu)Rse9ZZ^72WMaKk8vsI3 zfi-Ip{-)=50{G7tNLxDRkyp7h3kyarC%<1{rw=tVzw%LgW&iFS=NrjJ{&Wk$^pP8Z zTwxNfIr$s*;5RlnocbsXCd3nXQZPRDWpat3q2Ymkr@zmqS{39+B4kEK{34h^UAnC0 ze5K~G=d7EgG-^I~VkXCgqvCT;+RT0Jn8z1?ttlqckNfz=TLh=VrlvJZhA3G1P`0GW z5{^U~rxTVj57TsMU$k@38?jPmmJ#y0eOHkV?F(F7V$Ap#FNA%*lXL##u4V`7vAN-v zZUQsSW%RH~o6CJ((pvl)YOu{ptYNf(X37VEm8{&AD*i@cABW#<5`V~aSWe7ARk!FW z;!&&nQTpJq=(o!oTTZ~+>7ioh;!2AROb;Mu$Kc1gaZNvV1vp4cYWn#11~uK*Lt5I% zFXmzQI?anwlu5)`_p2m>ZwJ zv?(ri6?G0n2xGW$h5dPf<;tQ7E!%kc-O7!YG|q!7idcAj!d_!#u26R6$WhHYc0(_7)K zs@0(s-Bo3!{u4k+%77;Uc{FOGOga0M$jvu@o{#FNGLTkG6?N*$ZHSggYLEi}zZR8q z1#v<&)OkbIf0*7|>B5a}?5QwX3*H^}TYPx)5D;oISwpN5wrA|gBVP)R1*!Ja>b#XS zA00et7Nbu2&x48DfPSB|1alM34|7oQ?OQm^L9Rxymm_tGMw>FyRi#epz!|6*i8cpPSn3N`CTcPz{1Jskj ztqZJ9iuac8Jyw6#xL$LL0VJc7!+KzzkY0bu-m62|$V!Iw>&ZxG8m+Rg3dt>^`7`MV z0P3kM`yWwfX0Z_il-YphcaBX@?OcQI2qU=q_`YgDhi_HY&F47yT<2Rw)scsRuTH3U zP1y@~4abJ!Gx^jlu8PVcZT5Ou)c# z@#O8-e$-FL7g57Ak2c)>Et00SYN1+caf>Fr7YRKN-Ql!0PNH#C5+e zq1lq&`Q`!#E(Q&2=K6@CiRmWq@a2Ka0t_9&?Vx#r%wIdNjclJ6>;DGowMNbhbc!9p;V4QlXxPta+0;$kkpMnh zV;)-RlHHdA(ERPb*atnfFHFU!r&&1LTPqpT!Nr&pA;wq-C#Y1f&jw%3qS`k_vjuze z>r2*6@^qwS(sDq6pPP{U#}fvs;8DICJnugvE+M--!=(ei-s^y_xz*|ldSk;Qq>`cr zyfQPXi%7Ilyde+|kzLDJUpN0+29!jhAYZR=t7+!3ZJvt%PlGWFyeg2d5!wp1G~=ZU z&N*$Aaokbm-P84XkVqL#%ZvxZiIWHQtrk%+I z?~XP}?+4bpa^T?X7UyS#wQrIx-0%w9*_MlI6PScIwMyB12z%0D6{RoVJs2k1fEm!h zlEcA&;B%X2Hdr%UDeWftqnv36Fk3Ug;~f2x)xsJ1WpDAQg7uX~D4TVA=#m-u9~Oo% z1*MmTUm?poRuDd56bXhN_Nr}{I&53680=|`F6KUdFvmbN5FJUHM@rIEC<&;JAM{A1 zEhgNhtQ0S;weK6tg#etkVj756z_C^8v`+B5Z$c+cxSiQE4$ym0F}`uuAJ?N4&_r;^SD}E$Mq67kul+rjPA~ES5lfA zO2_(^PfmmX(9j5G9_|Q0FP?oyR~7s8ATF0cSsp_`)&p z1aQ<-fj%+V0QoB?uO^8AJ~VIG#r|XL!Zp!tqnsZv{|PezR|2}rjSlxqolAzpiVd6L zhO=n3TFwCk7E{hxTkx%to~yUG`Xg1VQyuuA6l%?Y6maZf0E>C3dSD|rA!ixkhwqlf zwH;3oUp^iqqKn0T(43)#!K6?m%bA|xg`B#Iu;z!CNbiad8{8o_EyGE~fZn9oY`olV z1p&HB`gM+4|y_>yTCpY1j--JMzXPUPXC~iVy8bse=|3Oe*uy_@%O; z@g{ZY|9}iaML<3tJY5!zVFq*!X)%RmzU2Z@>j0KQ)zw%-7=UeN#MND*ZO_6Mc5f(}$x-6~&2Oz3%?W)r zwu%8@k>2iji1>pPt>HAzRRhnBI`jyMPSkFhQ?9OD`Xb}Be}PdECcdg7^~sP-x&;8I8fRM4I50mJl5O zm3)++Ia-KkSIRx;RA&dkNzmkPo|WNq;m17Ud@Mhl{zE7QpL~W!&uVZx zk~$gw03U?y_6Mu(hNlySr& z4}@ zU2(mxlYweviz9?_LJ;{b0Z1qjSMYFDo3nO`cPeeL8~HasP1P4Q#RYY*^9y=~eV;iq zOOxxAm*Q{@VD;0qRBL6#Y^z`3cCb|HtCz}r}tc!QMF1654!_9c%QqV*Rs)pj*O04MRzV0Ol;&I`dKbuEWL*VUjiY zqOVWb7v9}F=hE(tBgRRQ@&cd1KO(~RIr>5j6Q~nJ<#>e!nl8nT=p)wBAVa-_s{)Gj zmOz~#7W8ztdFV4J=r`0goqr)B&z+$6^b0R}K`}|j^fv)zc=ombr_o}BUqR(6(#)F0*X56neWV6?E{xRk74oG* zVQAFIhcX&*nJqft?U)K%V(DG+avBnN2uXhw2F!anIdnVPJzgsUtQb+@3Oal)FatI@ zMKwCUj`B210&zUETO%e~NiEXX?c$bsdDX3LpmlatkCTg`n`b2Wk95PS#W7h>URjxf z4^5bIw>n1vJ3sv3D#ZviG%RaE460T0nh~95X53TM*3!Ic3m4-M(Y~XDJhlu41h!RD z3k+~D7b&CxmQa1Ug5qY=A-zh;{9-K!U7@a4x@4E8PoiMVS43rbeQucw&;G5Y=L*M1 zD^Ju%s6nfX3TFy;^U4dd5-SrVL*Gl}j74KrkMjD#!bG)2IgO?lhWPioEe2%$6AsiP zprkRwRzA_rOz*uncL!NY4`bz6AbD^Ml;ZH~5WgvYe8_74y(|t6Gq$ z6;slMWwa^JnbzDb^FI+p;~bLkQa^pJq~6OZcYW!y|Bzv^lG`Gn$Fh z{*K7>f)zn@eS8Rd4-_|2puMKV-Q>W6eBgsHZG)$7tQCG@Ll_%ShXX32N?!)-?~EYb zX=68SH+Sb@T}gX2V)wG0kD(@VBpR;ipyqPb-Bgz8*t#t?a>D0M%5J(;eRHTG*;pOK zojbn(sXaMgaT+EZ={PZwX@b4!{A=oV{>S#^n#4y=$<|ZiI3^rGt4tZZ{k0Z2PRI=p9Nqq0@8c z(g=gHlSYuAMeKB~6tFBCk%4}ByNRzCDHj(5XD~{*1Ka8k0-7G~D5xv*n0U`^7(?A` z@-d3&<;|hoh5))B@JU9m1*~o2rO(Zf0T&+hg7_0gE$wnVz2ni!TW_E=O~}Gk5`%Q_WjHqkj@xv*`VRIU4onW8LP{ z=k^n4_Z_#D*CQumtmEKJ<0kBJ{0Z>%k|Qyjs%ek@2cM2B-`p6^Z=K-*ZTI)D;)y?q zAGmkbG|j{6YyJejQ$wv;mzMfzk9zp!^+>#`>5+ml5Ii2A7>8wI`uJaLo_UxC`O>!T z?03wiI?#ak8aLctj;{7J(s>=HG<2x}u9WyzajHR*ju+S15Z zQADwk{co+qX@A^5sn_@&#+F0NYeml6|HA9n_vQLuYme*2519GF{#hCi*p%X~JVhNh z1Ey~rPSSiI=CG#qsQN)$bf(SB>ey0wc(qcmHFESKcnX3@J!=3^jBk zb$)!`J?GwY?ppVcyIe~JanFu-zwh%t&$DB+G!zN(Xza;JYK>Oo zEIRsMaywG8QR}&^Z+cp|+3)rSUy(i4)_S8y0IOza{Gc_a7R!ytQ8+D}<%DnLC8O{( z>>n;I4n58<^>$9_ViyOAtS=*N1yTkF1qW`Mq2??;_QNMxPQTzMuGsPXy;L^;=WiVD ztKx51Osg$ro__bq?WPi}AdI8r(||p(iVsvxL!qT{KgGEjy|`@yZNBU!7&>VUM+tM0@ zuc($zJ0IeqdPnNL9>FEbao6E|Wn#hEk(yE0ggE}Ewp4 zsY|6Oy&J5#^!eLf+r%p?g0R2a;#2a5I3KU~kN_q#U z+6EB;oO$m#cd6vpTM^ABxmsXYPGFCXb`E8BdK_U^5d~2M0@VNfvi<&IF3zghxHdF# zrZLNnmMK(9CwSXEGIKkartFdmW!CnQzgTbDdy6C^=m$+}RsXV$+`=o*Z+lnK!3&;y z4&K^>!m7mwUa#CXYCryN?@MYI?xi}RKzVVz=my`GTnByYQxq6Od3!|+HGT{M{qb3N z3l&K4tsC?m0aovAE5%E0Tkk{bEydO~K}div)x?y2?z$Mm-)q~8mx0Is$5UR~LWG1; zjtR1x_UqioCu<0}95ICCX&*r5uAqxnGPwiU7lQHjBuAY~+jm2XpYv0xpGZN$Mp;09QW*Rv|o4F$eb!sDf&X>bfHnl8J482+i zKBcr!;PJYXZn2uzvmPqJU;m%y$htX3ShVhf)1{CN+*-U5JjxUwUOY@L4d6}-Olu|m z?{`^PPw#Ei=S}|0I|;e|(>zJJg%O8Cv05qNKR!{;d=|BVBXCI%;St&ZjppzrknO|0 zvxKN-QSGm$2KjU(1w!s|7Gj; zZ2_ddZ`&LUF)Gj<5Rq zj*Y*y9Q<*Nlb~gM)k}r}Oi&LR{+{7u$RfAbH+-LVSbLpcyWQt;cZ6fSR}Wr>fVQjI z+1F=fO1Ht^Pi$+0Ni1k#KM5SOGjGhetV-3S*m-Rns`$CcZbpR}WuNThR>9!O-T zDP^_tp24@**L>8a42z9{4W(L(g+0;gr{D!${#ox&DN)Z7=mC@23_eFqR@&VDJ=5ef zsdsEfaRcf7e;xQkeERy}Rb+<+oWrSY)B=Hhk)KxZ^WF6k1n#`GoWlQ}{in6GacNo! z0;+xcqJlJvO%F>2UiczTV6bV5$TkH=rF^`{>zxS$FADFiQ3XpE{wj zYo4eP4$~RegV%>_XElF1uwM&b9)V6j5Hy{5^M`~3S@S)x?w6Ev(8R{J-|qVP;`J~8 z9F9A>R~RAYCLDsR3VuuSfxq*oSmj25x^uaNu9eXw*^x>;-l**$%D0GI6gMIZGwDL;kO8JSReEF3DOzHMhm|T>%X{&<}ZdBt>|>c?#W7g#{a41!y1*n z^zzTOy1(l;;eiRQZkDXp;!#Wx>k=Pt`|EiAo*}#p673I5G~>5^;$uX2zc*CdET6Qt zPlrnk+lulmr3BQ$sY;~%VPahH^zwrYotwLtz3Ul6UL024X069Z??b;gVrh=j?LD6N z)#3Aek00gRH^%XEGkyE>cc)4-roliT-D-vD?)uxdSbttYGqd>!TR zf5VPqR|2p_c0oJ+&E@iD@tqV%V%uFQb7%-J+SvmpnblfSvjHR~YlndXbz|yQq{Pd0 zio^F!;S3>)NMF-aqO<0eSq7(Rwv@^(!BEYt*2$=Xc>bc{Ads3db%>RQKhsZ8&TGTX zp^coGdMijQfAPFgVqB@w*Jsi-R={+<`hb#_6h*Vzzlj2h;Cd7xc~-206d$lI@d{6V zawkijT~AVjXf73jK(pqx?tTSgTSzK@G06u2mAS5TK{VC#Bm-wtIdnma{JjLV?hE3R zRTlTBg$i-SEyLCTLOc7v5ZClNNLOHt5JGlRyQDMZ2AugX;G+dp&KNDq;6Tx%n)yG| z_x}s4rT9F%Ub?^QqxEQA5q}#NgT2$Dp?&;H>pgReS)b=yjI~d;nm=aeS_6H4%nJ0{ z4&zZqhb(nme-v4quB^b%Xy!1ziVodpT3lMwJUqoff%>Qu66T6c{+b{3@QtCP%&y&0 z;g=POfkYrM(S4|W3Q82y(2P_GtAqYnxH8z7zT*V)>B<1IAd$LO!>2a_Gl9B5Q*TCkj5u8g^v`f>MlDYgwf9b_&$n@B3 zQ>g@Q91>}ty2j`w^%I;Y>*7xF+JH~hKlsC~mWKQl+Mz8oR3zFE^=j%Wo*!Z(#mlL~=x(yWrm{{dI5$dihzrfED!yWyiq z-UAk{%v_*YIA7(dXR6c;+Vra2wyHe0u$T6%;gl%z)=e9oCrJ)(8Mcq_C*lIBY2+*v z2zlV}lWRO(shIpy4;xO^(3QPV=Ip?3#FC6WtNF6KE^f$L=w()fh%{=W+ZR`@ade&X z0)q#2k+g4e@%Z^V{Y@MYK~ppF{BS!+9Ce*wI?AtY;s%t4@ovrLMNA7YA~SUE>y5Uh zVVa2HWaUSQt$)c60W$Ma?3j^*2zbq>3eVh<%zr2H__BgC18olNHO*8XxdRV== zc`bM8M6X0tlb|bpn|~tRr8HvDEgm(ZLp3Kouha$C$@_lC^V`^##}0ny+4}Qd|Els0 zk@6Fs^Fqw$SBz6}p3`3nF(Z;^XNE4WVmYs&w@=BNUWt=7Jw`SdDM3q1tu&YC-spbG zE-B2Nov&9xfi?wuCST9j@Tweig!ep&n6@x<_1SHNgRL(a`_!8 z%rTEUPoMcSM~B^n(JS};@t##I#Zwjc@QZdHQf>c(;Fv&Y9a&4Gjjb*>v*D=$zga3u z@3QdEp&m1o@>L`1@k2Of)zMR?)Z8toc0?ay67xC}B9Kr)JI1jBhM#L9=xe^2)@Gsm zZZ4k^DaGfEAZtOnoopCwyAuM2=Ki@QdaroKmHVCBALmpamUUjF2!VXY2{_>BlbI?H zQO@*nPuzVk8b-LHmYSkk02aPdxo$%`o^Ah^bjq|W)Zc%FeU|NRt z3;5_o7H745q{rjtt6*m6=0gBLPpJP*%+$Y2aTl5!(_4rWD6HHo%-#KSIdoTjqz`!` z>uFawii~0NuN2L-kkNRQVa0MTW}6&Bsx<38MoPTQ{fnG8bg&z6Vuu3h?4S7}KT;E$ z*iYoVtd$ReIe}1FetMKOL6fQvteuG>nU7g&kx6=q*veAkvi;8{&ZT)wC8r89aTBjI z`*{vZT(#8M?bGJ$Ki(S8JA?ILrfDuyekX~Jve`6qLd)X$4=qk#4?#HxRD$irlRu>- zuH_jW@Znb!ANOd!=l(+CY%(%y%m0n@X9%08NUlc3eqDWF@FQWW#yA;LkM9N;AK z=I9_0vnU65&GUjzj9T zPq##li&kMEqNiJr@AM~B zdO34O>lEN)l;`FosSVJR)Re1d&H0;NFAk}R^R)6kdS&O02Std5ia|hrTC@*~4*PQg zY}4zp?iyshjA6ZQcIZlcnewhl0&SyEBMLSfbA!2(XQcEQSi53UWIGXz3MsnmmFm&A zV^@j-_3Dvufd;d?a{uCvtoc1(6iG-KaMr}vkNJ7U=4n`A-o7iY(HMXCZcbunH z@j89FHro^^rZY}dWzkJj0`Xx(DK5R?6g;>77}6AWF(_`xD8)MO@Zt=U4Q2K{9;^Z-7Ya>}OgHij z$N-Ta%KCabbFQBK)t>U=R5oq9;iO3ZN@maT=Wo}+S1&Vi^{ohK9knhmz*eB=0vE0d zw<&h?xr&WTn=g?1HIra>8mZy+lLH*UU^+0}17a%>H?tyaSf{khE0+Udhl9;offEoC z`fmmX^`;7-yh>j>_-zYU1^dPxdTD0r?<)-a18b)gl`oCAD%4{P!Ms#rhQ63G=F~S; zGU(euT0&;%)s8~%sFWRpVY*9ez`}|Uz{19WG%D<$f_6@dw26CvOgoiz%!7Lp5x#dW z(F}6ns5epyORS}X6~c}8?!nQsvbD`ZzhrRw3U_(BQj#JYM@&nD;luW7r8Nxp zW-|e0S;rQ;|2x$^*asE%ixLKcIu^s@SA5pNLnn~%;WA75s)rc}{iYDki9RUksXYO(| z!G>2=xY@%gkR>=v&iiAWQ-K7pMB*6AGm2WIeulBsH|&5hCH0G#unX17F738<1K zyR1Gv%J3{%q%tqn1I|t5*1KG!=zyH?6!z_Z$T2qDN5KQm$b2AGVcA9J|*9;hT8dz^} zA#SM1qvm&p6Pv#pXKIJR#j-n)@pmGv()-@IMN|QvrJQpUlgArFluTX=(j-${J3Cvx zSwpVBy+55cVinnSV-?4EHsUCz z{T@E7=lDBP8hV&*q(#v@tixT1+oqFtB_woXp(%nN0()cW5=mI|#T6xvC(vpoZ5VC3@PHbf3hH{iBVP?ojNXmDm1*2b>`0mycl5#@$Gfp-+Y&2f=mer&x+LoD=cMbI^hiQ7&?Tz7!0Fbtrvb{1L-vml7rzVgnO+j= zUn>+x@;H5>w0Qy73OUzV+3ZAC1>d;kcniv!A#}@$&v#1g?JnJOw>Yc#zuG}maq;|j zg0&3d4s8=XPkCelhrq0xdJ3t!nC@<3N)^n*<5nw94fKIvcHGb7wn zW%4?YJPy8=VLdh0$D+iCWx?p<*HK5 zqFa5K0=+QjaMx(Ii(G9u3P3+OguO}4>~vl>CjP6FH;L~$8R7l*P~Hj8|2UK~>tlba{-gpo z$<$s%aD>~>O`A%>9@9)&Y$*ufcvNu6!;RHg7mkn% z73HKz?Pwm>tC&33BHAT8go_z&y1KgBB2qcv;<=@07T2>=K^7rLJ*`c3_jlKuZG?h; zz-a%VaO_4{Hz`Q2P4W{UqnPRQmGC{I$+K~K6l^%ad&l1ewkkp*W`G*QrD?j1ti^OfH&bU_5^698c&d>?qvZdWj$6= z4>(V!`im|R)?$@&w>^Y-B5eE8D$MTGW=3!mV5G(1!i^iu!@PCJ>28KvF zRFP5&nN@H~gus3QL-1Fr_Kgq4bRs_x_-vBfENa*em}i$A+@upHy}1(-hif zKlC|1p@^Pg=jcZw(nQ#ej4_d#mJ3AZxHGz~oR7pI+BNBxY(aB?It%9OSrrC7WP1)m zgUr?iN4`P1HuvQkfPZTcgH88m{J=~nXDu3vip6sU(r4!BmR>-kJssPtkx%VO7Is+Q zUs}9a6gHg%W~|1d>|fI)+ewy8&WlL~L@bu%>bp&S{waf>wrsNnE$E7Y3IZJdmX|W} zi#G@VF=jSQp}EjKwRVl6ET?qWM7yA2H3I*<-|NH0dn>ct`nn|=p(mODdf&=_B^1&p*sZ`m8bA|mvp%+CnnCn(wzhngtz1d zMwObD0W3k_Ihe}&P%`#MpH4Ivo>WMZdb(P^#H^3~XF*E1zR=gk@dn*kEJ{oa3kUHE z3<8P4lpy|*ZzXmxVZp$=<*6cx^gZ}E^-Z8rqK;P$eTJ+S`8|sX@sn=0fN|HWXp|C* zqCS~4m*)Tx?Kc1{J$ldQnPq<18)QWXd){qIIs3zcXlhZ(twch4b{-P2U?e@R!>9LF zU<~4ac$5?c(TV#~5bs;VcW(V9vyK|5h#x%vIpECsF!t2tlOhnJ3cp1e^sSnSMBu|Z zPmcMSbu_xUi`+f6wSVDz@x~_mN-=%ibK^&L2Z4^cKaUDN9>&}N@G|{Wpvq)=o9W#& zMRFfVkpo=X%?{snQj&6jUs$I8qZahmn`hiAGonNB^SyxHzHgtJU3C{rB89KBR+@`8 zZvteU4QSfR09Zl`(Nv~h(Bh|TBYnT=VJn_*^Nnu1)=uz;Fl7a$gYU7IHp6yK*7-l* zDD*H!nife@2x&PHDVScNRYd+@=Be?I+<>VVU!)Um_6D}4?uO>*Yhoxvi)FOm?R6?UC2JvCZM z##Z-Q5W{`exn^4G_EN+E?*ub!5uh8qb6F;oNPX(EVA4fo-=BpXSWaF{oZ=QP9og*wnjacGVOV(zyUgM)^`~ly(cL z+f$ETOvYnW5R6Y}z#ZHKTz{{DAdvU>2NJO1=JB-PwwF=GuOJ+iB!=hQUCoBVwX@)K zSyhn`y|OlRo!BW0cpJt6xX zhaV^%Rp%Z0#0INw^;<2lMyB79c?Afu!jR$y^L?M(5<1BxIh<)~WZ!>T=*bUeq3-|b z1rY9I!3O%Q0))^TAE2iG0q1$IaGfXwJf}zw|1Tqn8m$PtJrM_&bw2B?HTvWMBphB1 z(@F_6pZfT7cR+d*^fQ3P|Hv|HR!{5WivUY?IW_Kz`Ir3_CEu!~?i&F)JgBUat_cH< zr79OHvs%TDI5N^@`qNmmk34!_DFt{2Iwyd1VZVkM?~?_3wr!tzn<)Z=c8 zkk)gO@A=uJ2~~1Ui^Nw4<8TRwAR&k&bCMESA+=3x9y#wT3^*dYv2hk#F=lC)z$E8wEXJ=3AOvki-SIQWRuAHE+<>c`6BPk zRLZHjah=yP|5+Kv?s#>TWZ*@9pSL^kRnQ;9svie)>$gQ;)54))&J}^+ds2H8FZSER zYjfmT21Cld^chZg#|8h);cjtFp2SDCW3V;x6`@x1Qa1Vb`=!D4m<1eLvclZI9OV1* zVoU~nBETlPcX_pGSQ>Euk`}%Zu2quVECk{2vLh~7*)x#dYu!pEVHPXxjX_t)P8)S1 z7w|EQ`O}pzlV2nS(@!2cPt0Uc^h^3URm-sE;^4HCcSq=o-=y2e zg@2*mbz!4Raied1Y^Vgf=pob?HpW5-Da?7VAjDY)Gyo)gmV@o>D)V#kbO=Az8O2tcPw2ol``;gaGrH700qvapbBD2 z5LCG&@9@RpTW07I3G5AakbUTr4?@4bRwL~T8yZ^gHd4~Q;Ru?@9a}tDKDojnxA(BLM8JDxL4A|6+)nx(wOtJrahDouza)j zV}ZOO%C;l%3y$K~$agX9n&o}osdoA)uny$&?IHgsHiL7tj7Z+V34e!;DA2#m9?`o*%r-sKx+5>oD6O`e+S+$ttl^7&lTReF;nK4J1i$d; zP}&^Wwh9j41Wyp(@iIy1W|`bsC@UY(d3O7w z>&eBySx^bNW;oK^|{$C0NG$( zfrREQ{Ke=1Z(8GEYxrU>*p)inX|Xbjfsk9w@5Own1;vU$BX?66ErdSepjY;|p;+G} zL+uz*%|`N9%ltI-++yrG--e)1y&RE#qOc`VBjA8p0J(xP@PYN{)W%Xj9Kd`{m))m3 zhF^(zk_}c&1tEJ$R*QhD_8uK&BB#TDVPjma^Lp9CnB#OzZJD339wvyYmdCX{~Bl}-tH_&S>{Q6s5Qpq4PZn?>AAsl zo+e>dkqS?0W|}DpvV`vx(#wBkb#ON-|Foe?hhxxKKWJVl9!W6wsxA?EG1V2~kBeWR`;oe$NTKfrtpZS+0Jo{JvMZ+To-zHIP2>I{YkB7q8*s_dgm^)0F9G z!5=)sP_7i@DCQa9p2?Nra1Ms}z=b4nxpj@)1}Z;3L_f#h%?56g7k?fEjT60plw>=Y zJZGZ_ceRJxOfgy(&ndA&@hBTH;YCKgWhc$PA(nz8jJr4lr%(dr#(DU)*s@!2DLXSJ zdRgl`MG0xuxgDfoV8Y!K2Y<&QT6#*Z9HI(?M5Q@bW5X@FnFnr&)aB|!r`od7vQ*~) z&c&>^i_IcH5`~>e_`V)lBSL@eNZ4;^wpsdkXlSQWDpd%*DfPrbxk!kr|L@m1n*00v;pmoZZV*ad_LtjTy}&o&5YrnvzfZP#gp@PX4_m7 zJz9uRrgLAYgAnii!6G+!92si*&#~cDpm*gx1y;tR5}f&zQ?U{~gVa|*?rlt$i0J3M zQ3~+BC^;G9sZ%pwTTo-hrdF}$tv&n} zMrvop&Ac52i`Cfic9{_nvB#^XH*y-NRA;H}!u-&Ch6Mo>%P&IgBd}pzj;`Ehy~ut* z1l$%^<^5L;F&Rc{$E{F=vjZx!*(So^RY79;7&U%B=KDmTC|I^Q1-y^DaReE1xPE}F z!@5|W83z;%pQj4zqZi7Xpo+S|#lKaW=1tIVYQgC@J>a)C$EB9(Sl`e4;a~L=u5?~Wpl1Jf}H)vLD+U=%WW*$C8_vsi_=N9XN^wzlk&hn8c^hbV( z3-#x9LRG3wm9v9j&YTLws(GT12QI>esiQW4(8OJea(Xh|G~3(oH)P-@a({y(T-JyN zA0ayx$f;bf`?{*jzdk#6E+NU^^_hh;Ma5{_EhqG?la`S=`ErHzG=W<^z|S!t?sYHU zm@3f^oPuu$zFBBFa;~>U)&ggys|R}$V7{{Mx@f^qYYjh(=tSXN1a%1{`#!K}P#+pW z19DT?D}Sen*`fJpttKy~XtHkGE*0S3f5l5|gfQ=l4;bZq9<6i<& zOu>5rwTP|M^Ta@U&i0x%7=R%$TIBf3a_z?-^~X6Eq_Wm2mY*&U)I5L9+0+jOu(oqr z-|ii9^2`-Jevv&;>0h-Xoss>FM$iQKe0lLR7aR)(QBjK2*Db@k$^fhkBc~@7t+nMl zE+f(KEbAoi6kQ(sNDGI8(tQ=z{<=YIY+eLX z5-M#9RZYN7H)R?mM^ZKJ3fu^EwUu#KZQINcDh?>o;?d}man^dq_-SBhAg4dM{?YU33wgP*1TIIhRG8Lu`HF-SejmJn6xo z^u4Rte+UTP(1kysASlz zeX;^feZP+jozf;*u8kr+|G|4*F&n|Bk7&eU;%SQ<0hpXbVRiPA5;yZ1w9Xblpw#G7=)vXHABI9I=fkge z^E0p4-tf&e0;pEeC!tQFegm9HNyf|3urhrYs^gCBw`cJrECZzmeZbaID>mIcO^dLI zpJQu9eP9h;W6omFZ3h2)QiO%|*)c9~U9|5tYVUU}{+R{9zxeMb3;I&+7&&FtIh?~z z*&LcJ!}>UYF!yHp!{jGA(cTm8N9P|Q>!WlET$#Ooxmu=u6YT1p6A{WFBMv#mZYS5N z&Yv-Kldp4LrSJ??TIg;aN7_kARj?N=3h6eNfw0+Ao%0WvT(eJ|05L~L-_VPu+R7!r z#ms?P!=^>!d-gBPfSklygH*8^l0`ePUL+Am{8hq4o_7o1PeASw1X|GzMw5b5kHqSi zIiuJL@R|dbgbx*?z0-7887NoiX;tR6{yoEkg!B?WvlO8}F)>dSQw|i(Ktp0FUcgwR z!xG^w%i-Q;&fDd68`rsGq%`c8Ysa1xIjjJunAT1`P}kxuuQyZ7rk`}aw-dfZbk(>& zpPDbyAMrbp^i(fZ|EV#NIvSch8@|MvI8r~9o(2^p&jyfLBBmdbD~o7d%+3o$>1Si64o_&&;>Dw+$D0x=@8fEMcTsz>JPBMQU|kvIbp zx7W_esSWo)#F9suwD&KTL*wL*<#`2~$4Zh+_vfLy-DL_1MaVfnFA-e z9Cy>*%TWMps0$++|IG>JCzmOmxjk%WF)lewu@D{?4shd(pII)gnWVng zgS8{pR;^p&YPfE*G1|Gi0xM;l`X>Ury>9b5Yigbcrwtsw85hX?V>nca&Y+8|Xbb{m zFum9f|E+{oZN9GG>~#_1sU;IOVu)IG+Q3er%KQL6KZf~Kg54ozBzQ03ySu{b-*=p- zxt*fl`ccKO{rQqtaZmM;(nq3w``TxIzhU$Rhi^I^MnLYZ!Y@7ENyBFV8 zZC;3Zz&8K09Ep;`$fmy^PSiltIShYmxEWZPb2IDugzhVW?xBYRjh{j|rZ)X5!-Zxm zJJ)o2y#CWAkd~J4hN{6d9>`z-*1mfs_tLHZO)smGA?pbE9mvJqKog?S$<%V2paA4P z@v20e>aeM!bzfX3;0)JN^U*e=0Fh8@1h)@tf6Q{n++|k?%B`^C<1&dV>FQH3%FRf@ z_s7W@ov*OF5M-lBwJW51v|AV|Ne39MfX#hk^8Q%OMayJXR=|JlZKGjkk!kyDO_G%# z4bipI$)o20&HWIm&BHEuCA&eOzlI8+jUSJY)v*PsXZ}T1+Q>$Lc2MCRc@~2rXSdLi zc|3_7lqFp)75abnHvM+j$c;hXh2oa%``F`|$)GDI=m>*Z(Y13j8)kwlVgGx$bU44L zTf_cKXyP3C6YS4`7pMnZ>@BqFjrwx)8~irqwVggp-e8OV@ns#mVZ)?q9ZE8dmt^Yc zDD~6xA*4!#BWSaHO!#ntYjm^QPQMMbZ|K#IN6B7+%Wh!=;)?+_m<|IjDGY8^)~w_z zDOVsDfmVJPX$>R#uHt0=^92ffN;fX4%E+%aOCkEm?Tfja%)cU3A|`~^wp+uZT6e@t z`g4ytK_t!Sb~^^r*m|=GB|Yo_;MbdBG2n~d+{sCbq~}0LmFX3QU2rlh1mN1`;4Mvu z(uqv_t!1H>4z_NAmV({F4G?ydIw}3ityJLmbCINfsfj4cy)9~^QanDtsDcga;YOLb z^K{v#T5xf*_4BrS4_H!H%{p+{hi^Ng!pQDDSv)&vduXn;OPy zsQ{De#TY__^y4y#?d^Y4Yuex6R=@~I|J0V`h)IH@&~j6Es%FJnnry19qUIR77l*t{ zo10gzCHMQY;hmd5LmG9tO=#B(7R{ev311`RPDnpDEpiLiE67}Fnku;`U?MLUoHM^6 zh;dXEfbODf*5r;h0aXi_th%_sDzhnW+ds64HIk2RX6~dGIO6Ct9A!Jo5DLsQRmlg7 zCTajl^Of_S&w%fwHwaoB-Ozl%Vt`MFrAKrv|03pC&64DLCX6NvpY4=JJ0TXbet*1R zz+7M<@1!yL@~W7+R%~gH{Jkz|^O7&>$9yFdLPbXe*h}7+ZwAh zhYEg|Cg3aF6;GKN!w{{W7atus$CDusBg~oanEwljKu$_cgd{gv@L}NO;aQYdt`!_Q z=WcAd>3vH+@QV3)=9l_DWi8O7=myJhm(lC?(P50yr)`^sRjIL33zv&Xj1tRQ{!=>$ zra#%Zb({G{pn&nX!lrQC5PA%ie(VR-GsI*REJQn za?SH`JTOB6Kxp8B^mV(}RY1iw%3C$;O$9g3bz=dh?_GU!`w6P!?1_<^g6dJG(E!LY`VG0wY=Pf{k&3GcVcOGxJ`!~Jsp>|1 zImt_z9=_suwUjAm$f^HAhRM_Lg-4jt#6WJpGjwle5cGUAdx5+Kpj2wU=)T^-A7Bl* zDRWArUl35u1LqD9Fm=BAO&m)>b*X$7Q#N!XR;#1=VJO{VQ^KT(bEd1PF6VR-KYd>5LcLnDj>}l4BT&vmV88@{cFl-u#^MfbqA` z>X;U|VX~aUZE)m`T%?hU)-c2N6+Q*GsQFJ}Le9sz^&*#{zryqVo)vv7-N6N3__>cb z&?ZGL{!{BOEs{&C@qn4RvHSqpr~~5OVFYk%ZWs&mm~_uyHi0~%wGaSCr|P<1@_KVb zocxaOojW`aE5HRw%s79)7=FL{yR!NI1o96iuOQ=bdvS4b(?WX*b1>*}JM>csld^#i zI|aAVrz)k5XVUxPZ~9GI1H2aJ98HSA{ml6!D{+AyuIvjppx!#A6{9ah%2AA-;{<_4 zHD+=R;Q2B{nPW-bya}H_9MH!zn`HgFY-kYSnCAM^I5$K{a!KJ2$7Nku`ohm$b&&dz z>YZ2-9|K&EZ}L3V)zz1zuXlBmr%VlnJr)O-?#`QDB&N+{Q=3%)El$9cP_$UN;{sz$_nCF zauU_JyX~##+o0i>UZBJch(|TgOX7}sQYRfjBR;wPnb!I`5LJNlB3~KDv1q&{il@$X zlqGsB%}y@{kN)Gx(pN_ipnmP>oAuT4gX6u~UdQ*t1trjl-x9lxim@^|FK38mB)02S z9sk!7mB*Jr41ES%O+$s;a$IYR3RyrFq=5u>1}4GGm*y*2&U|JwL%6c;Uohs*emJzU zxJ(9~_N0~pj}3S{@nrAV#%$k6x+`8Dwrb?=h^z8D;r9=fh0tW)?-tC@o>mukEI|0l zzcJ%w^!h!EK6G22Y@9i+Mo9uAblMN2y;>&ki!_>vczkFB7Ux(MamMgOC`HC+@b<(X7 zpUa@>BWMz_BSdBn$}C-bc-ZoW+wFkU@oUf7F}AieZ`XCo#Lto4F*lHdfITxHTo28` z&|(D^4Z{uaKy3wO~rKdB(&+_aYYK3xcGhf*-{2%e`QjIW;kL?XvPz zIsYVmqS}&8alRRA741%d@K~-7%w~J>K5}s*7?S}h zjvT&o7z#f+^CR#_-xR!rSt^Czbz-_4y6EO-|IJAvn6hu)EHSs#waD0?RuTYSNrw3` zwYkI2>xOcihJE+!{(A6#uDBYThCYgjduK{9lGGtVC`gw-hj|WQ)9@+nSYyBytNJGM z(JnBdtIy(KPM66FtD(Y{CJ*og%Fq(R@AA7;2%mY|CszVzgKwl#~dPi-g_RvKj!Ee@GULqj-^bg zT!{+73R0|Y32?ASeGccJf7$1GB7S_8heh;b{Tgf^ z&_F6iG~LeE&jPKB|9Jv?HZ4WBsWoM+A`^b(P4?2P*LWnZUt{Of$Z}qiZ@0`00Xb6j zh@7{qu&e1^3&6-WL9N%<3iJ8}X4N)Z3EDd;Q4r}2)jpqsz2YIT|9&u)j+TFo|afdB!Q;_?FE@zIV?-H^Z~nCX_* z0nrokHU89#TB5otx_Z|1gG(|=} zNdskTtLWT5{#74yL#9%wdqHB62F-9&Atwlcs$aT99=p5X_uD{EY{jo$WmhRm6bNNY zS=Kte&PIPu>9(;0p82&=Hy}La*v=cNB%7#*)Qi+?05}+YddpOKIH4o7eC=yz8{l?` zHPX7Hi*b?i9GRt0e|aCC!h#hzql&tWO6Q#tEIs2KhRE4Z~_IhPr-(5)Y{3^R|J4fEk6cB z($ld55dbPrY5weRm~U-R20wAKerEB=kFB2?IPa*gXPsVv|7sX;w~>}-1nY_6iZann z#ep{YSs7xBJ&%Hno_9UbS7@D*7vs4Yoc*6(09whFCOw0TROkH=;4#H}`76%D32S(h zVPnWjNoQk2!yv%kkTpyUjDQCc)|L|db~ep6`DZx(NG9nRkU<7!o|!NquFC4`BiEOp zCsewz4|dZdI4A}wgB;&H#!L&}^_Lm*ua!q3_^9kO7(@VqiS&<&#N8~uf(02!@j&<=we)wvu=YxNT zxSfEz9Z(hln>BwCJKdCK`Jvcy1&fR^N_@oVO4=WdbY~}XO!H<{F^Gqae`R`yZP`+ zK{r~%|5<-#jdydRD)4qHHzWohbJhg^WzykFG{dkzX)oCy;3X*SMT>5|1l3%o+m=fPI?uxSyVobi1O3z~j-Av6W&j5)ZDpfqRyJ5(Nr z*ci%=mfEQIJhE7S9BC%hkAygS9If_19E)2gG$KCUW6f(6jJCb6-o{*q++&+$UAsQ; z_w(t5bAHLp*tebuzQ9W;)w_T&imeUBQ00V2?tZx?seo@}(J>ZPqkI`^Dd_*of17U3 ztjV*vrKOxcc(;|4~*`~#yi`CsO( zFY~u2U_ALeYTSvP(sf~G_j2YanGW;xlv9H*d1z?031Z7zE#fKB71)NDRg#_S_R8HB zFfEW@3(8~9CtdmD&13R+;nAQ;=BPjXiO!Ss$aP|E4UFOV-ZSp0z<6px;GJbvP6?t- zRrdHpIRUFgyC>P<=)aCxis@RZ5N>8lcVrztf}?Dgv6_=)ijB!jY7?LjdcnORA6QRC zAzb=b-Y#1EzPW7qL6I#H`{wzYfKQy)1cl@!<~4w^k{Fsc*r_C>bOD;iMgP6W!Q$FC zZq$8ZhxEm6?K||pXGR}Z3yxDa3jPS-KL+T#N|4&qf3mEkQnS*Hv*1@}rn3j-p%bsn z?6JC(A_d6jb04K5P9jv)wMiwP2B7I0$fYm9Uw6FrYx0~iOSjv<{+x9y$v{LeE+Kev zmbU;uxEchTU4XkqiJ)G;+qY>Wv^jhHS6XO$RehRGC~U2dsfiQxkzvbhLqioYB0D@W zIrRJDHU&TH#NVcwD!}=5dF+-3*BI5n;@>!F66vIb2(dx z{z_D`#X=oJQse(9>#O6Mj^4Im2oeg?C^B?POG`Hr3ZopOQ;-yCVK7RWf|QgD>F$BV zXqZ#Flny0?F+v)o@%{39o;Nz&mW1v#_=vYG-nVlj{>Asj9p@`7acsDJaz?H#S(ph0(fP_J ze*O~AjDqwBXx_BefpprV%q|Y1lvDCLv~yo$1*NSW&R4pW7S#JJr~E=S`3EkG1)4N~ zsd*9iH?l>0#2|HY7$2NFO6IAD*qKX2z@tu{4vVv_^Ni+^`g>Fjx5Jl~2Gy8LAnCaC_VcfLhq*A3Ba?c#wl}=U74Hxu% z6Qq%y&ee+nX*0+e-LDSlX^iqQp13KeExEGOHWWl1cm1zS#rdO_xt$~g&U53@$HLHI zgX1)QSg1Xu$P?JuQy=wdQvCBWNp4e3YI$(kn~}XE3q)8svkGy@a_<#B6B~bLXLx+i zV``b&>T=zCG!*c@8lh@=ndM+@CNQ!-QutsZm)zz^c@yprv&{ucka%H&el%xHgid?i zIM0kObY}R>BBY-rQ>!cg{_+#FWISbFn4jc}`APt?PM4$4WMG1hnviR(3v!V3Vtis` zxg!10nxSzbf>9RN~01TBRcf}#jKdI-SOH13tja9-nlbV z2D61~1S4Z;Y0J=A)$~I-%=x@8Lsh@;NBsz=E_}oc0>`mB4A|gxA{vbik=wF$>+nC_U zdwZi0J`WT%t9>cq6lKJGI!Ns>iW`l9fdBSTW>@{XwL?uB+?vdiKVY6{PH{8)jaGUa{2U znJhmI*?TJ%vBf2-`K=?#CsO*5wbT1yl&@Hd`NVRVgmOpkJb2Qzlx17%NS)`T_-P7zDF_gp$$}9>B zVvvAEKtjpKtHTDVY+>hDFy!3o;mJMaLQfvL3>Y~&7HdJuQjU5parnnHJkL9O%y<^G z^{*_0I4`<(CeNZm2W|<67#>CPSeU1cya8Yj#hq=cmpkRL3=P7Sf0UZdtZ17QVA4C~ zR(E@seClqm09d0WwK6{EE1Phy6tgac5vb%N_0!}EUN_E`yio07(Z)gNNrvS9RT%YQ zQQodEa7SAH600!z)lUXWp546dUPNS{0Bw23W62JqjB1m>1{(Lyw_fCO)Y;@NjTo4s z-}jinX-R{xT0EWVb;Y@a<%K1dJFUuDr@ng%tA`2zyVcJ(FJA%zg-K6ZcNG9&hw+T< zvqv><7&jwI?mH{?>*fM1_uT&cV<@owjtjYk)Enu!K(+jTsD38(JG*VDa{Q6Cds1ox zt~&jslm16mD@30&nW%Q$MxCNNwCai3LthAf|IeOOkr{8ROUWEalcp+mI;ilNqVFka zn)rVA;T?^cTlB;hXf&!BsGOanT9WlPFUI(+Uq!JZh&SpnP4v zFob%)JlEfd_5H3@liA?4Y7UsmhQMCm}PcQza(!6`d z)h!8KaGoh?GMnnny7a?fDQhny%Lfe>!0?YtWzzY=W%Gkzo)F-L1s?Oi6&TG$s@Xgd zE9*;?smMqe$#~suUCQ+GD)*&928w>>ZWx4{&Ev)oEdI#Gu7-dFEDEJoz@^t%0cE3D z$~@+avp(VO8B9&mYc-=HLu|Eb_>WAHyBvwDHJUwga@7MNM@-{4m@%N4V+-iB?9x}!~o-cw#@5x_`i>B5qRX%^J zq%uyX4gWK(Zp&_PNx1rh+dVQm_JzMN3-#LK)}=HF1KHCeC|2uoP71~4se{NS-{3b! zT(=J1S!K50{j)*C1001vjf(|*-LKqZd(!}mO=rkfgrA|TuXwqftY%dCsY(Cc)v4gm zPtjMu{o(IiC}roWXzQB75gB4!PpFlwW-7s0m6;VwdyBx!zmXdDnR&odcf}svS^Eh>u_Q5DQW}^?p zDj#UD5pe%nE^Boyb@)Krq$VAudrg5wGy!l_O=P*%cTVmK2i;^pxU-sDLwCG(=zA6V z;1$`3RZfr`hiv?qraoB9xKCZB&h{0w#efw^7-}$9*c<@vw8-+dYxcvUpUDfI#J7TuG7rGcjIXUUR?EXPp%WxT88Te7(< zo25PSaTTX#)NVf28%6Dyn?5)CjVG$rDeNC~dB9lo_E9{JEvbkx=0rKyz||$|yVk@_ z8bPHGC|rAO@-5(W=3QqmzM2`W*3jw80=odMdX@yK3hb>Ttivk{b9ZO%OpC|~{V1-F z6fsaT!C^u4%*v*BKahXSw@dI%6tgc)==PGukKwFv*W)RbDmVq$Ei~85nq&{G6f%E6 zfFpI&pAo%CBQ^M5YYN%;cxm4V`B%@lFA~7BnmZZ_D&be*(p-$m8o(MJQ|EUT5OiLV zLXOJmo}Ctoj4tZHWruzgX9q>{g*^(3V(Ja4E-L+2bCSIDEK{xFI`HNd6JmP~wHlqm z=yaFeoNbj1*1{T!T9}5`@cu?!*|%2sr){_AUxn-GxsJwP4w>qLU~AA$ay{AOJK^>Z zV-m^~V^c=OsJxhCdV5s<=sOskplNdOk}(Cv!vCT);l-#hkJlO8rVa1iHblRQ?!N>t zm__F4{};Qieo+qNio7krVA{HLiQddocY3?dOahkl-OJS5CH&Z`0Ei?mD${A;4c}?^;pZX8HvlACh z6%pVLc?D>4nTj5J7n%*ms<8>-{nVrlP&|yLL6FR`l9^Baa(Mn{)G2@gg-@5}9OuaA>1)+^c>i$3l=xDg_FX+%qI3XDcaIh5AADAD^ z7%CY_=3l}auLitHI2^Qk7GR}ge^5Hj)#PqGw5QNUy97VB@)E7F9CV)~+Fp>9kF{K9 zZ4`5DDTgf(spo_UIhwGR*D@Tk!$u7+Fo53LvtsXbY8{7k6t~AwHLyya&;h)FN zAd{)l2un`cMa0&=F1QMr7ELu)_)B)77hbcAu+nnyeF74tm+c34I zDYXOhmI|;(?wlubBkHGxI^LOCWXA){ke`(Du^#q?W-c$n%4hrjFYY}Hd~QbAREs4tnzrW4;H8}97%LtD ziYvw)S%W>RnL=WV;(GJ*{zh>=!)>;k{>}^wX7jnL*PGq}muJhBrwvEJ=6Zdh%h*Pt zLg|9MmKY!nOwi4>p(Tk^xd-z}&h2yX{mhYdv!oQY#v8VoN4Jw=d-lDoWF(zvxOm!T)8{%;rd=tk^Rwo6_9*NPHkbgu84-1CURFH&bc?y`rLn%$ai z_e>+<+Wc{TB^T)t+&3OhDWZ&I>0pB({lu_UYEXB2ble}JE{&GXMw8);jfd8f77~MjUwQC=d zbYHrY#GG5Mf-oj1CAP>h<}gqGv|6^{7+Ur9^}V%}ygD-tUj_xzv3C+*zwGmIA7n#l z+hTcHrzE1Gcdtl#3dWE5sU5xK=RXMg)fs(LoR*AMz~;e7BpA{8`J^A;9#Fv^_^E6@ zJme@v=}XtMxs;DFmDQW5K*Zm}!@jo@7X(>jKMLC0=+=d|?4MpwzIyV9=FO{$;V;c} z&$cmd3S3t1w7U?$SdHn*Id^2Mn2CDaNQS@R60`ZR1*iQx8@$SA8od5hMYA_#A*6DD z*6biu9tr!`(1hp?IL*{s_6dPo-FWU&YW9-mUK*dZic!1k&hd8a3uQHz&_0@^E+3W5 zPjeSa9e%s&_8qGGbv*GQm}yotEmXKOokP-X+DCdDdSgZ?GRSsBuDj50KFdu?uG3NW zU&nN_nZ`Yaqu=(-he+1%ad)15Wg=bK2vlTFPGK-T&j>&=R^dDTd;mZ@r($g$`;=Xr z!l%lX-QH5wD`MP~t`itSm(qpj{KjOP&3kq0**(Z;nU{ODLEK|_ABz4XjhEf76l08Kq_P2rLE7{LB;CY7M zh@Ta`+eZv|OP#5t zK;VyNOq(!*+Jp>rmAc$x>X6imLh}94T>$W03cW?_7E@-`GRNpxlN&XRjz!Y7+|S7ktx5yZ6#h(1PW;t6cBhw|VO1R=zdEQHR1*GHUy7Oj)9`CdrLC;%V7YD9VP(Me&&C!;YG{4!V&gNxJ7CXm zoqrMQ#SC#2tqICmzgAEy>~nZHo%wTSx-IYUObIuBEEdGL&uo@L7C%lMOWVLMK11L;Pj}to$|(x%U3f&ZSud zO*!y=4zhJEXb|=Z&QPc`c(!#M!uN;iRbHX|6|;u?++Bw4w>-C5?d5(=jjL4bozJXM zZ*9DL?uR{8Hm7V2iU}I1Yi(ateW4UFXWK~UJK3h+bgF9oZsql?lwZVlCZOwk!rLA7 z0F=GmfGc|a^6KQ8@~!1q(+Dz8&5KRN@;8c;hX>}yGW+^T>@%#dqBm&1JmvaLg#Z@c znL41Dk`6rbftq#YSN#{&^#PUIGSR=AO$mXwz*K7zzMBrTCkSqTtnhve@NbNhJ?}yq z2W_=r^Qfq;9bOT!M#DquriweX_N^Q|vmXWNoMz;fIkC@9uv5RTrmUuJ(4Y*Ur})2E z*wSgw4L!t=FD2~LYheq1#5Mh%y`JouX|G{RrXi}!~mN@3O6c?c1H!x+`y&qLV}oR$|!hJ)`~*AGURlz-ew+n($;0xt0Uu#K4+V1uP63=?IfO*JU4;OU8(HGSM+})0{P)dx>=J zKXC$RVy;8d*?CGH)L7x==ZbI@$x)?m($oO>pg=IarxAC_8$inRP8IXQ)LVnBU@#a# zu>L25jo9K_5`w6x=SZPWPOaVPYd)4B#1P%K3{6h81W?`)VSf_;otl+|o<$&?+G4b? zNWR8-q)_gour=7eeE2Zuo}XR&;$eK(h@Nv>-BDSX?dhLslrMZ>N2!`f2<*tNq(gJgwdrzCWD@}<7IyT`n@^dCTrC0;seh|=4i zNU)S~1^Trl`JLVDz&)$@n_h!I zn#_vjh(JQ9Q!^q0@dk>qYOAn5^hNH=RHHj*_4o~=TC^(V`PaLdW6_lF^7Fh@C*4vK zo1U9}Zc3$?_pp|JX=G^BJXm|LP;kVOUsBv4**i3kDU%Ux$=BZ`!|&cS=or141`ygY z9zoxT-%oa`hXLGwqAF~WV5$ILi2ca&H$z-yJp5O1<74{+Zu-KK-D4jp7|5>wkRYSb z`K}}vO7SWltF18_$JV{IuJNP{&__bgmRJ@y69r63`*pgO%mHF+_r{t&y|OE_jLjo; z@=?X|cUb0OCY=zFO9Rlns@9 z=u;zrjBjc^L4FQ4L4wJxUbsM-Y;s?`%IK-{W?jVyCXW_-fj#b5fsT^55>o+wTPD^K z+HPoEG`q%V65-|F_Wqt@T!J5vwnFGIT>z+gx+`rQ&bDgjSEg3@HTk67Q#XJ9>_1nA zx4qY!3A1tSNe3^Uj=uNc)-R|sNs_sorUzGb0JBHfQM497b_2m_0?&R=Bgd#Cw}`a0 zbD~e+Q{y5lZ}Ij*w;Zgn*^l8mL&J}b06&9d4$Ms_d{GXc`S&?B1@J8R|3fJLKzpUU z7zL^|43FP33v%=7vL0*M`_g(C%5ro1rRJfzYEHaS-tr4esRoEkNer&{mu}O_Z-VR|I?P;pU4p%0cNoG94n!{%gkTrxI)fWkwq)((M(z&& z!z3hhK9@ZLPUwXIDv)gyAURvHG&~n>RYMcyPE@*G;j@L@f7MbUy%=7<>m1XPIZ~-3 z=a!BS3r%#~zblv}orY>1u(_#6QAO>6S&t4aV$&e>w56N^l}&?-S_4RqhdykF3pGWR zx7}Ui!z(3=t`d`-aSv_i!cLJ52fw&kfZ*L$vyLOw(`n1Ok+t|~+>j$+=O20tkj zdVv}>3oZMDY!-rwP4-bVHn$_Zf;Yf|1RydrBt}!G)kF^LK1yJY2QO+cU*AX1&q|(cAZ{Pxw$MoPZTM<5Rn(>z7{*_7K%q`&?FJ zxPLB8ZbVcDNSPMtVE6q*S)(Q`$DAAhoV-IU`n%lCh&vAq3ltd%R%vney{0V&?Yww5 zUb+74skZ*-QztdTa@%=jC{YFxRJ|jibKc5xGQm zAE)FlXE4-&jjWs^_)(^Hp+&jPZr{oFz;PrYw|6KR*Vn%JW%RsgUt&;D+e2QDAZw=jS)>&-(){x|>(_?` z<*htt8a7RoDFwN^N*M8*Fhdkgt>wBZYKmcDvE*|#-ZwKFcp=ufuej!T7Ts#D6>V!^ zl|_8m3~Z=-Q$qdVrlB4H9jphK?*6~Umbs_Pdk;uxS)TuwY3pI*#p4Swx~*efHMdO? zV|!RFh*YY9Lr-a?mHDLyxf_zR{*I{?k%)(qg%Kd5r)doX%M|Emz(L>P|4H3)Ye%Lv zxTPG(%th0x8#j;uG|?Xa16Z7sL;3?C*CE@GE7cB*Pf?Q*g$wF6#@fGz0rsn`YscB< zJ*6XQrp}5)M=5YMo#mx+3LrU;;4ntw)QNiGB-8T+(1-3dOPtERQt9e+?$=y30jYRG zrpI)D@dK}nuJEE)k+ge3gZfz|lv$)!HwcoIuc0AU{y&)B`R4^+TQJg-zJ2sDW5MY? z{0EEBj>b8fQcnP>z?hf{D0Zj<^yH0~tkO!%iR{1)yV>8pW~&G#Wx!!TeTF4*f4*b@ z!Of_3WFe;k!2dZEdkI!OP2wA8eDU5C_%M=4jaC+0mweP4?epH&%Rs}?nL)N9bK*s_ zYSnS*9(%1z-nKe(A+;gdx*>Y2KH*c)d-)C7EIxN2D3da$ReIif*sh~<);$<5-hnBm zNdd?+wNif;lTWcdJ`;!&7qh(BXi8vnymWc?+7dD8!!?zCTHIwn|H39@nrEMu4d?#y z7S|SV8}vp36eUt8+%+_$R7?UUNY@2qxKiCA12B^8bsnkw1ZjaW44d{Lj0*IH=%NuREw zTUMkq`5=*jK1z|>;;2Z<>xit%ASbaIx8Yg`dCU;K|ipjde&iG$ogu$3Rd6lz}=o4N91r3sF3@hf;-&~%(j4bFl zS~x37X3(A8@V`zN_NjZ|kIt zm5abfj8c<)gN5n9BoZu21CJ5Q+0n_mjd1-i;dcu66T8LHssp^b3Ebzcj|q6=*s=fG0|K=DbC3TW9aeO^6EfRUIMSh z@0b%VJ#>NFBe7&l`F!5#H$v;#Q*!*@+!OK_%n!nc+H%J|& zo+|$APWxP@w)1_jfKLNs)W-5fW4X71pfy23K`4Gqk5nngt!+esI%RsSTSrD<6R!?u zka>A!5dM8oK`^5wKDKApR$bfvfPWs+#G7wuKyR2t0~_-SGD(eI)g@B3LdxNU2{V-- zhv@RP)yAEIfY93ATwDeFC$#NX+AmR#zPUX8>QhTndkdJiUtGNdJir)b8IA=5c<_hF z9x+x#3>D0iRR|Z|aY8lc*oM0(HQY~<<#Le0<`b#d~(E>J$qu!yjzDoQIeTPB2AX zp0qK$1nQBnAbl`PoD86(3jhwuSHVai`Vd{ zA~al;{Dz7&?SgQfjKbtE0bc9K@?f&!tMW{w5Pk~_aqD|MTmg@Pd#W6VEYO}=I@2aJ%5X{+OnN|xqFM*5P2EUic}#!w)dsKQLtfiK}wBq7NFePM$xz} z$iS!zf8_;gLelT5swT&g4S~Gn3Cx@?*M0Jx$R*!<0leD9{GFGk?}__?zxPHeVtZeg z4!waOZ<&O75h65G+X+nuo%=jo@CFhnfP>_1B~>Ld_5_X}lQ)wi6tb6|{?ax#dGq2| zRBm?Wu2hW2%YbxwHbV-#*G%rCjP$=jjA3DrVwWO_A`oc@^S6jT< z7HpE`7Er`&Kj(gG}F zFDd|u!v4;e1I_cznFPtVudg;)I=D*g`QpCk^lPH=*w_v?8Vf5nT`{}&=FTia8&Bs;{(YB;jfBVzwtOwMa1{lGf^#p{uLj^xKZ+&9 z0XZ+NafVAnCqXoYxH-NI(x378E(dZatvtoMW>#CF4vxxM$=fh?m<9Gk(syq_ zDr+7wt1g6R>Xn0Y&ibY-*SWKLrLhb6&6u7I9IG7r%?U5P`nq&_QAbSo9{h^&Mi0Y* zgVIdruyVKZ-*U(Ppw-EmouMbE_d$>L&`Y}jpzht`N!^}?1n{;EHV;e(qW07{Kgs&Kuzz^!49(%C5aDq|9J zO!kJ?lLF$wgmu?m3wdn?(gm7TtEU(exZI!m<4f}Gs=YxuGL97awc3@{!7K@Uxx3fyXy*~XDscJVq37-Q_m zO2NX+&!boKmw1S`E}MJ(16b()uOY{OH+Z^i5CrY{-w)&gs3-oOX7K-^a>2E2*dHT% z_-?monu4=gA;O=_N|KZ_P8qNJ!tG~XDwz{IHJO|1B|385Y%t`B7jp7r8`uwMW>M)B zXb~X0GD+G44858~ZPef+@nU4>->>uXy&;+(_lDtV9QA=CG$Ziw&6kJV+InA2f)K5! z6NQ_M*vz*-q5jljhNF$VD-FM9Y&o)LY%>MvC|XyY zS1|*#@@;#20Zs1aP3%o;n|^ioW*!z!x(%JS)pxz)klAG7U&o5ww4)aOAR{z0?I|}m zH)ET#NlQKBZ9}E)x3Te&5;g$kYyHZSq8t&sUeg<0 zl&oDGcG2eKsp;(B-fdyAQ!{T2yU>1J?Xg+RWS8c6;WwLs%LbcW08dg*ZX1$utz|&4 zeg-bAWxVmX^W&84Vfns~wYA%EQ&T{UB|)rkw2_T}&6#t}d2Zdg8EbuOG1KQlB`D}z z4c@A7E2gR24wTSGxDhYz;_6BSs&};J`cuV?!5%o$tGE5NAF?>8^|wD_|WcUv^h;YFZ;qZ*#6IsLI1N~oJM`3 zw|AojS_bI*q6Xg+ZaabiKe_9?TzYD|7;!e37M9;aZRzg(wX3F3-1I+eClgR9A=d93 qA@=!;FUjTjms|9I{6g*hBdsoA#7TE4@c~`?NS>(cs$o=ZUjHw4sB6yv diff --git a/DOCS/html/stm32f4xx__matlab__tim_8h_source.html b/DOCS/html/stm32f4xx__matlab__tim_8h_source.html index 59099ce..2404e20 100644 --- a/DOCS/html/stm32f4xx__matlab__tim_8h_source.html +++ b/DOCS/html/stm32f4xx__matlab__tim_8h_source.html @@ -5,7 +5,7 @@ -STM MATLAB Simulator: F:/Work/Projects/MATLAB/matlab_stm_emulate/MCU_STM32F4xx_Matlab/Drivers/STM32F4xx_SIMULINK/stm32f4xx_matlab_tim.h Source File +STM MATLAB Simulator: F:/Work/Projects/MATLAB/matlab_stm_emulate/MCU_STM32F4xx_Matlab/STM32F4xx_SIMULINK/stm32f4xx_matlab_tim.h Source File @@ -14,6 +14,7 @@ + @@ -76,176 +77,219 @@ $(function() { codefold.init(0); });

    stm32f4xx_matlab_tim.h
    -Go to the documentation of this file.
    1/**************************************************************************
    -
    2Данный файл Ñодержит объÑÐ²Ð»ÐµÐ½Ð¸Ñ Ð²ÑÑкого Ð´Ð»Ñ ÑимулÑции таймеров STM32F407xx.
    -
    3
    -
    4**************************************************************************/
    -
    5#ifndef _MATLAB_TIM_H_
    -
    6#define _MATLAB_TIM_H_
    -
    7
    -
    8#include "stm32f4xx_hal.h"
    -
    9#include "stm32f4xx_it.h"
    -
    10#include "mcu_wrapper_conf.h"
    +Go to the documentation of this file.
    1/**
    +
    2**************************************************************************
    +
    3* @file stm32f4xx_matlab_tim.h
    +
    4* @brief Заголовочный файл Ð´Ð»Ñ ÑимулÑтора таймеров.
    +
    5**************************************************************************
    +
    6@details
    +
    7Данный файл Ñодержит объÑÐ²Ð»ÐµÐ½Ð¸Ñ Ð²ÑÑкого Ð´Ð»Ñ ÑимулÑции таймеров STM32F407xx.
    +
    8**************************************************************************/
    +
    9#ifndef _MATLAB_TIM_H_
    +
    10#define _MATLAB_TIM_H_
    11
    -
    21
    -
    22#define TIM_OCMODE_SECOND_SHIFT (TIM_CCMR1_OC2M_Pos - TIM_CCMR1_OC1M_Pos)
    -
    23
    -
    25#define Check_OCx_GPIO_Output(_tims_, _OCx_GPIOx_, _OCx_PIN_SHIFT_) (_tims_->Channels._OCx_GPIOx_->MODER & (0b11<<(2*_tims_->Channels._OCx_PIN_SHIFT_))) == (0b10<<(2*_tims_->Channels._OCx_PIN_SHIFT_))
    -
    27#define Check_OC1_GPIO_Output(_tims_) Check_OCx_GPIO_Output(_tims_, OC1_GPIOx, OC1_PIN_SHIFT)
    -
    29#define Check_OC2_GPIO_Output(_tims_) Check_OCx_GPIO_Output(_tims_, OC2_GPIOx, OC2_PIN_SHIFT)
    -
    31#define Check_OC3_GPIO_Output(_tims_) Check_OCx_GPIO_Output(_tims_, OC3_GPIOx, OC3_PIN_SHIFT)
    -
    33#define Check_OC4_GPIO_Output(_tims_) Check_OCx_GPIO_Output(_tims_, OC4_GPIOx, OC4_PIN_SHIFT)
    -
    34
    -
    36
    -
    37
    -
    38
    -
    40
    -
    -
    41struct SlaveChannels
    -
    42{
    -
    43 unsigned TIM1_TRGO : 1;
    -
    44 unsigned TIM2_TRGO : 1;
    -
    45 unsigned TIM3_TRGO : 1;
    -
    46 unsigned TIM4_TRGO : 1;
    -
    47 unsigned TIM5_TRGO : 1;
    -
    48 unsigned TIM6_TRGO : 1;
    -
    49 unsigned TIM7_TRGO : 1;
    -
    50 unsigned TIM8_TRGO : 1;
    -
    51
    -
    52};
    -
    -
    53
    -
    -
    55struct Channels_Sim
    -
    56{
    -
    57 // Каналы таймера
    -
    58 unsigned OC1REF:1;
    -
    59 unsigned OC2REF:1;
    -
    60 unsigned OC3REF:1;
    -
    61 unsigned OC4REF:1;
    -
    62
    -
    63 // ÑвÑзанные Ñ ÐºÐ°Ð½Ð°Ð»Ð°Ð¼Ð¸ GPIO порты и пины
    -
    64 GPIO_TypeDef *OC1_GPIOx;
    -
    65 uint32_t OC1_PIN_SHIFT;
    -
    66
    -
    67 GPIO_TypeDef *OC2_GPIOx;
    -
    68 uint32_t OC2_PIN_SHIFT;
    -
    69
    -
    70 GPIO_TypeDef *OC3_GPIOx;
    -
    71 uint32_t OC3_PIN_SHIFT;
    -
    72
    -
    73 GPIO_TypeDef *OC4_GPIOx;
    -
    74 uint32_t OC4_PIN_SHIFT;
    -
    75
    -
    76};
    -
    -
    77
    -
    -
    79struct TIM_Sim
    -
    80{
    -
    81 double tx_cnt;
    -
    82 double tx_step;
    -
    83 int RELOAD;
    -
    84 struct Channels_Sim Channels;
    -
    85};
    +
    12#include "stm32f4xx_hal.h"
    +
    13#include "stm32f4xx_it.h"
    +
    14#include "mcu_wrapper_conf.h"
    +
    15
    +
    16/**
    +
    17 * @addtogroup TIM_SIMULATOR TIM Simulator
    +
    18 * @ingroup MAIN_SIMULATOR
    +
    19 * @brief СимулÑтор Ð´Ð»Ñ Ñ‚Ð°Ð¹Ð¼ÐµÑ€Ð¾Ð²
    +
    20 * @details Дефайны и функции Ð´Ð»Ñ ÑимулÑции таймеров.
    +
    21 * @{
    +
    22 */
    +
    23
    +
    24/////////////////////////////---DEFINES---/////////////////////////////
    +
    25/**
    +
    26 * @brief Дефайн Ð´Ð»Ñ Ñдвига между первой и второй половиной CCMRx региÑтров
    +
    27 */
    +
    28#define TIM_OCMODE_SECOND_SHIFT (TIM_CCMR1_OC2M_Pos - TIM_CCMR1_OC1M_Pos)
    +
    29
    +
    30/**
    +
    31 * @brief Дефайн Ð´Ð»Ñ Ð¿Ñ€Ð¾Ð²ÐµÑ€ÐºÐ¸ выводить ли канал таймера на GPIO
    +
    32 * @details Данный дефайн проверÑет, наÑтроен ли пин GPIO на альтернативную функцию. ЕÑли да - то таймер выводитьÑÑ Ð½Ð° Ñтот пин
    +
    33 */
    +
    34#define Check_OCx_GPIO_Output(_tims_, _OCx_GPIOx_, _OCx_PIN_SHIFT_) (_tims_->Channels._OCx_GPIOx_->MODER & (0b11<<(2*_tims_->Channels._OCx_PIN_SHIFT_))) == (0b10<<(2*_tims_->Channels._OCx_PIN_SHIFT_))
    +
    35/**
    +
    36 * @brief Дефайн Ð´Ð»Ñ Ð¿Ñ€Ð¾Ð²ÐµÑ€ÐºÐ¸ выводить ли канал 1 на GPIO (наÑтроен ли GPIO на альтернативную функцию)
    +
    37 */
    +
    38#define Check_OC1_GPIO_Output(_tims_) Check_OCx_GPIO_Output(_tims_, OC1_GPIOx, OC1_PIN_SHIFT)
    +
    39/**
    +
    40 * @brief Дефайн Ð´Ð»Ñ Ð¿Ñ€Ð¾Ð²ÐµÑ€ÐºÐ¸ выводить ли канал 2 на GPIO (наÑтроен ли GPIO на альтернативную функцию)
    +
    41 */
    +
    42#define Check_OC2_GPIO_Output(_tims_) Check_OCx_GPIO_Output(_tims_, OC2_GPIOx, OC2_PIN_SHIFT)
    +
    43/**
    +
    44 * @brief Дефайн Ð´Ð»Ñ Ð¿Ñ€Ð¾Ð²ÐµÑ€ÐºÐ¸ выводить ли канал 3 на GPIO (наÑтроен ли GPIO на альтернативную функцию)
    +
    45 */
    +
    46#define Check_OC3_GPIO_Output(_tims_) Check_OCx_GPIO_Output(_tims_, OC3_GPIOx, OC3_PIN_SHIFT)
    +
    47/**
    +
    48 * @brief Дефайн Ð´Ð»Ñ Ð¿Ñ€Ð¾Ð²ÐµÑ€ÐºÐ¸ выводить ли канал 4 на GPIO (наÑтроен ли GPIO на альтернативную функцию)
    +
    49 */
    +
    50#define Check_OC4_GPIO_Output(_tims_) Check_OCx_GPIO_Output(_tims_, OC4_GPIOx, OC4_PIN_SHIFT)
    +
    51
    +
    52/////////////////////////////////////////////////////////////////////
    +
    53
    +
    54
    +
    55
    +
    56///////////////////////////---STRUCTURES---//////////////////////////
    +
    57/**
    +
    58 * @brief Структура Ð´Ð»Ñ ÑƒÐ¿Ñ€Ð°Ð²Ð»ÐµÐ½Ð¸Ñ Ð¡Ð»ÐµÐ¹Ð² Таймерами
    +
    59 */
    +
    +
    60struct SlaveChannels
    +
    61{
    +
    62 unsigned TIM1_TRGO : 1; ///< Синган Ñинхронизации таймера 1
    +
    63 unsigned TIM2_TRGO : 1; ///< Синган Ñинхронизации таймера 2
    +
    64 unsigned TIM3_TRGO : 1; ///< Синган Ñинхронизации таймера 3
    +
    65 unsigned TIM4_TRGO : 1; ///< Синган Ñинхронизации таймера 4
    +
    66 unsigned TIM5_TRGO : 1; ///< Синган Ñинхронизации таймера 5
    +
    67 unsigned TIM6_TRGO : 1; ///< Синган Ñинхронизации таймера 6
    +
    68 unsigned TIM7_TRGO : 1; ///< Синган Ñинхронизации таймера 7
    +
    69 unsigned TIM8_TRGO : 1; ///< Синган Ñинхронизации таймера 8
    +
    70
    +
    71};
    +
    72
    +
    73/**
    +
    74 * @brief Структура Ð´Ð»Ñ Ð¼Ð¾Ð´ÐµÐ»Ð¸Ñ€Ð¾Ð²Ð°Ð½Ð¸Ñ ÐºÐ°Ð½Ð°Ð»Ð¾Ð² таймера
    +
    75 */
    +
    +
    76struct Channels_Sim
    +
    77{
    +
    78 // Каналы таймера
    +
    79 unsigned OC1REF:1; ///< Первый канал
    +
    80 unsigned OC2REF:1; ///< Второй канал
    +
    81 unsigned OC3REF:1; ///< Третьий канал
    +
    82 unsigned OC4REF:1; ///< Четвертый канал
    +
    83
    +
    84 // ÑвÑзанные Ñ ÐºÐ°Ð½Ð°Ð»Ð°Ð¼Ð¸ GPIO порты и пины
    +
    85 GPIO_TypeDef *OC1_GPIOx; ///< Порт первого канала
    +
    86 uint32_t OC1_PIN_SHIFT; ///< Пин первого канала
    87
    -
    88
    -
    89
    -
    91
    -
    92//----------------------TIMER BASE FUNCTIONS-----------------------//
    -
    93/* Ð‘Ð°Ð·Ð¾Ð²Ð°Ñ Ñ„ÑƒÐ½ÐºÑ†Ð¸Ñ Ð´Ð»Ñ ÑимулÑции таймера: она вызываетÑÑ ÐºÐ°Ð¶Ð´Ñ‹Ð¹ шаг ÑимулÑции */
    -
    94void TIM_Simulation(TIM_TypeDef *TIMx, struct TIM_Sim *TIMS);
    -
    95/* Счет таймера за один такт */
    -
    96void TIMx_Count(TIM_TypeDef* TIMx, struct TIM_Sim* TIMS);
    -
    97/* Проверка на переполнение и Ð´Ð°Ð»ÑŒÐ½ÐµÐ¹ÑˆÐ°Ñ ÐµÐ³Ð¾ обработка */
    -
    98void Overflow_Check(TIM_TypeDef* TIMx, struct TIM_Sim* TIMS);
    -
    99/* Вызов Ð¿Ñ€ÐµÑ€Ñ‹Ð²Ð°Ð½Ð¸Ñ */
    -
    100void call_IRQHandller(TIM_TypeDef *TIMx);
    -
    101//-----------------------------------------------------------------//
    -
    102
    -
    103
    -
    104//------------------------CHANNELS FUNCTIONS-----------------------//
    -
    105/* СимулÑÑ†Ð¸Ñ ÐºÐ°Ð½Ð°Ð»Ð¾Ð² таймера */
    -
    106void Channels_Simulation(TIM_TypeDef *TIMx, struct TIM_Sim *TIMS);
    -
    107/*---------------- - CAPTURE COPMARE & PWM FUNCTIONS------------------*/
    -
    108/* Выбор режима CaptureCompare или PWM и ÑимулÑÑ†Ð¸Ñ Ð´Ð»Ñ ÐºÐ°Ð¶Ð´Ð¾Ð³Ð¾ канала */
    -
    109void CC_PWM_Ch1_Simulation(TIM_TypeDef* TIMx, struct TIM_Sim* TIMS);
    -
    110void CC_PWM_Ch2_Simulation(TIM_TypeDef* TIMx, struct TIM_Sim* TIMS);
    -
    111void CC_PWM_Ch3_Simulation(TIM_TypeDef* TIMx, struct TIM_Sim* TIMS);
    -
    112void CC_PWM_Ch4_Simulation(TIM_TypeDef* TIMx, struct TIM_Sim* TIMS);
    -
    113/* ЗапиÑÑŒ каналов таймера в порты GPIO */
    -
    114void Write_OC_to_GPIO(TIM_TypeDef* TIMx, struct TIM_Sim* TIMS);
    -
    115/* ЗапиÑÑŒ результата compare в глабальную Ñтруктуру Ñ TRIGGER OUTPUT */
    -
    116void Write_OC_to_TRGO(TIM_TypeDef* TIMx, struct TIM_Sim* TIMS);
    -
    117//------------------------------------------------------------------//
    -
    118
    -
    119
    -
    120//--------------------MISC (temporary) FUNCTIONS--------------------//
    -
    121/* Определение иÑточника Ð´Ð»Ñ Ð·Ð°Ð¿ÑƒÑка таймера в SLAVE MODE */
    -
    122void Slave_Mode_Check_Source(TIM_TypeDef* TIMx, struct TIM_Sim* TIMS);
    -
    123//------------------------------------------------------------------//
    -
    124
    +
    88 GPIO_TypeDef *OC2_GPIOx; ///< Порт второго канала
    +
    89 uint32_t OC2_PIN_SHIFT; ///< Пин второго канала
    +
    90
    +
    91 GPIO_TypeDef *OC3_GPIOx; ///< Порт третьего канала
    +
    92 uint32_t OC3_PIN_SHIFT; ///< Пин третьего канала
    +
    93
    +
    94 GPIO_TypeDef *OC4_GPIOx; ///< Порт четвертого канала
    +
    95 uint32_t OC4_PIN_SHIFT; ///< Пин четвертого канала
    +
    96
    +
    97};
    +
    +
    98
    +
    99/**
    +
    100 * @brief Структура Ð´Ð»Ñ Ð¼Ð¾Ð´ÐµÐ»Ð¸Ñ€Ð¾Ð²Ð°Ð½Ð¸Ñ Ñ‚Ð°Ð¹Ð¼ÐµÑ€Ð°
    +
    101 */
    +
    +
    102struct TIM_Sim
    +
    103{
    +
    104 double tx_cnt; ///< Счетчик таймера (double, Ñ‚.к. кол-во тактов за шаг ÑимулÑции может быть дробным)
    +
    105 double tx_step; ///< Шаг Ñчета за один шаг ÑимулÑции (double, Ñ‚.к. кол-во тактов за шаг ÑимулÑции может быть дробным)
    +
    106 int RELOAD; ///< Буфер Ð´Ð»Ñ Ð¿ÐµÑ€Ð¸Ð¾Ð´Ð° таймера (Ð´Ð»Ñ Ñ€ÐµÐ°Ð»Ð¸Ð·Ð°Ñ†Ð¸Ð¸ функции PRELOAD)
    +
    107 struct Channels_Sim Channels; ///< Структура Ð´Ð»Ñ ÑимулÑции каналов
    +
    108};
    +
    +
    109/////////////////////////////////////////////////////////////////////
    +
    110
    +
    111
    +
    112
    +
    113///////////////////////////---FUNCTIONS---///////////////////////////
    +
    114
    +
    115//----------------------TIMER BASE FUNCTIONS-----------------------//
    +
    116/* Ð‘Ð°Ð·Ð¾Ð²Ð°Ñ Ñ„ÑƒÐ½ÐºÑ†Ð¸Ñ Ð´Ð»Ñ ÑимулÑции таймера: она вызываетÑÑ ÐºÐ°Ð¶Ð´Ñ‹Ð¹ шаг ÑимулÑции */
    +
    117void TIM_Simulation(TIM_TypeDef *TIMx, struct TIM_Sim *TIMS);
    +
    118/* Счет таймера за один такт */
    +
    119void TIMx_Count(TIM_TypeDef* TIMx, struct TIM_Sim* TIMS);
    +
    120/* Проверка на переполнение и Ð´Ð°Ð»ÑŒÐ½ÐµÐ¹ÑˆÐ°Ñ ÐµÐ³Ð¾ обработка */
    +
    121void Overflow_Check(TIM_TypeDef* TIMx, struct TIM_Sim* TIMS);
    +
    122/* Вызов Ð¿Ñ€ÐµÑ€Ñ‹Ð²Ð°Ð½Ð¸Ñ */
    +
    123void call_IRQHandller(TIM_TypeDef *TIMx);
    +
    124//-----------------------------------------------------------------//
    125
    -
    126//------------------------SIMULINK FUNCTIONS------------------------//
    -
    127// Симулирование выбранных таймеров
    -
    128void Simulate_TIMs(void);
    -
    129// Деинициализирование выбранных таймеров (вызываетÑÑ Ð² конце ÑимулÑции)
    -
    130void TIM_SIM_DEINIT(void);
    -
    131//------------------------------------------------------------------//
    -
    135#endif // _MATLAB_TIM_H_
    -
    Overflow_Check
    void Overflow_Check(TIM_TypeDef *TIMx, struct TIM_Sim *TIMS)
    Definition stm32f4xx_matlab_tim.c:49
    -
    Write_OC_to_GPIO
    void Write_OC_to_GPIO(TIM_TypeDef *TIMx, struct TIM_Sim *TIMS)
    Definition stm32f4xx_matlab_tim.c:255
    -
    Simulate_TIMs
    void Simulate_TIMs(void)
    Definition stm32f4xx_matlab_tim.c:427
    -
    TIM_Simulation
    void TIM_Simulation(TIM_TypeDef *TIMx, struct TIM_Sim *TIMS)
    Definition stm32f4xx_matlab_tim.c:14
    -
    Write_OC_to_TRGO
    void Write_OC_to_TRGO(TIM_TypeDef *TIMx, struct TIM_Sim *TIMS)
    Definition stm32f4xx_matlab_tim.c:329
    -
    TIM_SIM_DEINIT
    void TIM_SIM_DEINIT(void)
    Definition stm32f4xx_matlab_tim.c:473
    -
    TIMx_Count
    void TIMx_Count(TIM_TypeDef *TIMx, struct TIM_Sim *TIMS)
    Definition stm32f4xx_matlab_tim.c:40
    -
    CC_PWM_Ch1_Simulation
    void CC_PWM_Ch1_Simulation(TIM_TypeDef *TIMx, struct TIM_Sim *TIMS)
    Definition stm32f4xx_matlab_tim.c:87
    -
    Channels_Simulation
    void Channels_Simulation(TIM_TypeDef *TIMx, struct TIM_Sim *TIMS)
    Definition stm32f4xx_matlab_tim.c:74
    -
    Slave_Mode_Check_Source
    void Slave_Mode_Check_Source(TIM_TypeDef *TIMx, struct TIM_Sim *TIMS)
    Definition stm32f4xx_matlab_tim.c:375
    -
    CC_PWM_Ch3_Simulation
    void CC_PWM_Ch3_Simulation(TIM_TypeDef *TIMx, struct TIM_Sim *TIMS)
    Definition stm32f4xx_matlab_tim.c:171
    -
    call_IRQHandller
    void call_IRQHandller(TIM_TypeDef *TIMx)
    Definition stm32f4xx_matlab_tim.c:562
    -
    CC_PWM_Ch4_Simulation
    void CC_PWM_Ch4_Simulation(TIM_TypeDef *TIMx, struct TIM_Sim *TIMS)
    Definition stm32f4xx_matlab_tim.c:213
    -
    CC_PWM_Ch2_Simulation
    void CC_PWM_Ch2_Simulation(TIM_TypeDef *TIMx, struct TIM_Sim *TIMS)
    Definition stm32f4xx_matlab_tim.c:129
    -
    mcu_wrapper_conf.h
    -
    uint32_t
    unsigned int uint32_t
    Definition stdint.h:64
    -
    Channels_Sim
    Definition stm32f4xx_matlab_tim.h:56
    -
    Channels_Sim::OC2_GPIOx
    GPIO_TypeDef * OC2_GPIOx
    Порт второго канала
    Definition stm32f4xx_matlab_tim.h:67
    -
    Channels_Sim::OC4REF
    unsigned OC4REF
    Четвертый канал
    Definition stm32f4xx_matlab_tim.h:61
    -
    Channels_Sim::OC1_PIN_SHIFT
    uint32_t OC1_PIN_SHIFT
    Пин первого канала
    Definition stm32f4xx_matlab_tim.h:65
    -
    Channels_Sim::OC1_GPIOx
    GPIO_TypeDef * OC1_GPIOx
    Порт первого канала
    Definition stm32f4xx_matlab_tim.h:64
    -
    Channels_Sim::OC3_GPIOx
    GPIO_TypeDef * OC3_GPIOx
    Порт третьего канала
    Definition stm32f4xx_matlab_tim.h:70
    -
    Channels_Sim::OC4_GPIOx
    GPIO_TypeDef * OC4_GPIOx
    Порт четвертого канала
    Definition stm32f4xx_matlab_tim.h:73
    -
    Channels_Sim::OC2REF
    unsigned OC2REF
    Второй канал
    Definition stm32f4xx_matlab_tim.h:59
    -
    Channels_Sim::OC4_PIN_SHIFT
    uint32_t OC4_PIN_SHIFT
    Пин четвертого канала
    Definition stm32f4xx_matlab_tim.h:74
    -
    Channels_Sim::OC1REF
    unsigned OC1REF
    Первый канал
    Definition stm32f4xx_matlab_tim.h:58
    -
    Channels_Sim::OC3REF
    unsigned OC3REF
    Третьий канал
    Definition stm32f4xx_matlab_tim.h:60
    -
    Channels_Sim::OC3_PIN_SHIFT
    uint32_t OC3_PIN_SHIFT
    Пин третьего канала
    Definition stm32f4xx_matlab_tim.h:71
    -
    Channels_Sim::OC2_PIN_SHIFT
    uint32_t OC2_PIN_SHIFT
    Пин второго канала
    Definition stm32f4xx_matlab_tim.h:68
    -
    GPIO_TypeDef
    General Purpose I/O.
    Definition stm32f407xx_matlab.h:539
    -
    SlaveChannels
    Definition stm32f4xx_matlab_tim.h:42
    -
    SlaveChannels::TIM1_TRGO
    unsigned TIM1_TRGO
    Синган Ñинхронизации таймера 1.
    Definition stm32f4xx_matlab_tim.h:43
    -
    SlaveChannels::TIM6_TRGO
    unsigned TIM6_TRGO
    Синган Ñинхронизации таймера 6.
    Definition stm32f4xx_matlab_tim.h:48
    -
    SlaveChannels::TIM8_TRGO
    unsigned TIM8_TRGO
    Синган Ñинхронизации таймера 8
    Definition stm32f4xx_matlab_tim.h:50
    -
    SlaveChannels::TIM2_TRGO
    unsigned TIM2_TRGO
    Синган Ñинхронизации таймера 2.
    Definition stm32f4xx_matlab_tim.h:44
    -
    SlaveChannels::TIM7_TRGO
    unsigned TIM7_TRGO
    Синган Ñинхронизации таймера 7.
    Definition stm32f4xx_matlab_tim.h:49
    -
    SlaveChannels::TIM5_TRGO
    unsigned TIM5_TRGO
    Синган Ñинхронизации таймера 5.
    Definition stm32f4xx_matlab_tim.h:47
    -
    SlaveChannels::TIM3_TRGO
    unsigned TIM3_TRGO
    Синган Ñинхронизации таймера 3.
    Definition stm32f4xx_matlab_tim.h:45
    -
    SlaveChannels::TIM4_TRGO
    unsigned TIM4_TRGO
    Синган Ñинхронизации таймера 4.
    Definition stm32f4xx_matlab_tim.h:46
    -
    TIM_Sim
    Definition stm32f4xx_matlab_tim.h:80
    -
    TIM_Sim::RELOAD
    int RELOAD
    Буфер, еÑли PRELOAD = 1.
    Definition stm32f4xx_matlab_tim.h:83
    -
    TIM_Sim::tx_cnt
    double tx_cnt
    Счетчик таймера
    Definition stm32f4xx_matlab_tim.h:81
    -
    TIM_Sim::Channels
    struct Channels_Sim Channels
    Структура Ð´Ð»Ñ ÑимулÑции каналов
    Definition stm32f4xx_matlab_tim.h:84
    -
    TIM_Sim::tx_step
    double tx_step
    Шаг Ñчета за один шаг ÑимулÑции
    Definition stm32f4xx_matlab_tim.h:82
    -
    TIM_TypeDef
    TIM.
    Definition stm32f407xx_matlab.h:741
    +
    126
    +
    127//------------------------CHANNELS FUNCTIONS-----------------------//
    +
    128/* СимулÑÑ†Ð¸Ñ ÐºÐ°Ð½Ð°Ð»Ð¾Ð² таймера */
    +
    129void Channels_Simulation(TIM_TypeDef *TIMx, struct TIM_Sim *TIMS);
    +
    130/*---------------- - CAPTURE COPMARE & PWM FUNCTIONS------------------*/
    +
    131/* Выбор режима CaptureCompare или PWM и ÑимулÑÑ†Ð¸Ñ Ð´Ð»Ñ ÐºÐ°Ð¶Ð´Ð¾Ð³Ð¾ канала */
    +
    132void CC_PWM_Ch1_Simulation(TIM_TypeDef* TIMx, struct TIM_Sim* TIMS);
    +
    133void CC_PWM_Ch2_Simulation(TIM_TypeDef* TIMx, struct TIM_Sim* TIMS);
    +
    134void CC_PWM_Ch3_Simulation(TIM_TypeDef* TIMx, struct TIM_Sim* TIMS);
    +
    135void CC_PWM_Ch4_Simulation(TIM_TypeDef* TIMx, struct TIM_Sim* TIMS);
    +
    136/* ЗапиÑÑŒ каналов таймера в порты GPIO */
    +
    137void Write_OC_to_GPIO(TIM_TypeDef* TIMx, struct TIM_Sim* TIMS);
    +
    138/* ЗапиÑÑŒ результата compare в глабальную Ñтруктуру Ñ TRIGGER OUTPUT */
    +
    139void Write_OC_to_TRGO(TIM_TypeDef* TIMx, struct TIM_Sim* TIMS);
    +
    140//------------------------------------------------------------------//
    +
    141
    +
    142
    +
    143//--------------------MISC (temporary) FUNCTIONS--------------------//
    +
    144/* Определение иÑточника Ð´Ð»Ñ Ð·Ð°Ð¿ÑƒÑка таймера в SLAVE MODE */
    +
    145void Slave_Mode_Check_Source(TIM_TypeDef* TIMx);
    +
    146//------------------------------------------------------------------//
    +
    147
    +
    148
    +
    149//------------------------SIMULINK FUNCTIONS------------------------//
    +
    150// Симулирование выбранных таймеров
    +
    151void Simulate_TIMs(void);
    +
    152// Деинициализирование выбранных таймеров (вызываетÑÑ Ð² конце ÑимулÑции)
    +
    153void TIM_SIM_DEINIT(void);
    +
    154//------------------------------------------------------------------//
    +
    155/** TIM_SIMULATOR
    +
    156 * @}
    +
    157 */
    +
    158#endif // _MATLAB_TIM_H_
    +
    Overflow_Check
    void Overflow_Check(TIM_TypeDef *TIMx, struct TIM_Sim *TIMS)
    Проверка на переполнение и Ð´Ð°Ð»ÑŒÐ½ÐµÐ¹ÑˆÐ°Ñ ÐµÐ³Ð¾ обработка.
    Definition stm32f4xx_matlab_tim.c:80
    +
    Write_OC_to_GPIO
    void Write_OC_to_GPIO(TIM_TypeDef *TIMx, struct TIM_Sim *TIMS)
    ЗапиÑÑŒ каналов таймера в порты GPIO.
    Definition stm32f4xx_matlab_tim.c:330
    +
    Simulate_TIMs
    void Simulate_TIMs(void)
    СимулÑÑ†Ð¸Ñ Ð²Ñ‹Ð±Ñ€Ð°Ð½Ð½Ñ‹Ñ… таймеров.
    Definition stm32f4xx_matlab_tim.c:521
    +
    TIM_Simulation
    void TIM_Simulation(TIM_TypeDef *TIMx, struct TIM_Sim *TIMS)
    СимулÑÑ†Ð¸Ñ Ñ‚Ð°Ð¹Ð¼ÐµÑ€Ð° на один такт ÑимулÑции.
    Definition stm32f4xx_matlab_tim.c:28
    +
    Write_OC_to_TRGO
    void Write_OC_to_TRGO(TIM_TypeDef *TIMx, struct TIM_Sim *TIMS)
    ЗапиÑÑŒ каналов таймера в глабальную Ñтруктуру Ñ TRIGGER OUTPUT.
    Definition stm32f4xx_matlab_tim.c:410
    +
    TIM_SIM_DEINIT
    void TIM_SIM_DEINIT(void)
    Деинициализирование выбранных таймеров.
    Definition stm32f4xx_matlab_tim.c:571
    +
    TIMx_Count
    void TIMx_Count(TIM_TypeDef *TIMx, struct TIM_Sim *TIMS)
    СимулÑÑ†Ð¸Ñ Ñчетчика таймера на один такт ÑимулÑции.
    Definition stm32f4xx_matlab_tim.c:63
    +
    CC_PWM_Ch1_Simulation
    void CC_PWM_Ch1_Simulation(TIM_TypeDef *TIMx, struct TIM_Sim *TIMS)
    Выбор режима первого канала и его ÑимулÑциÑ.
    Definition stm32f4xx_matlab_tim.c:137
    +
    Slave_Mode_Check_Source
    void Slave_Mode_Check_Source(TIM_TypeDef *TIMx)
    Определение иÑточника Ð´Ð»Ñ Ð·Ð°Ð¿ÑƒÑка таймера в SLAVE MODE.
    Definition stm32f4xx_matlab_tim.c:464
    +
    Channels_Simulation
    void Channels_Simulation(TIM_TypeDef *TIMx, struct TIM_Sim *TIMS)
    СимулÑÑ†Ð¸Ñ ÐºÐ°Ð½Ð°Ð»Ð¾Ð² таймера.
    Definition stm32f4xx_matlab_tim.c:118
    +
    CC_PWM_Ch3_Simulation
    void CC_PWM_Ch3_Simulation(TIM_TypeDef *TIMx, struct TIM_Sim *TIMS)
    Выбор режима третьего канала и его ÑимулÑциÑ.
    Definition stm32f4xx_matlab_tim.c:233
    +
    call_IRQHandller
    void call_IRQHandller(TIM_TypeDef *TIMx)
    Вызов Ð¿Ñ€ÐµÑ€Ñ‹Ð²Ð°Ð½Ð¸Ñ Ñ‚Ð°Ð¹Ð¼ÐµÑ€Ð° TIMx.
    Definition stm32f4xx_matlab_tim.c:665
    +
    CC_PWM_Ch4_Simulation
    void CC_PWM_Ch4_Simulation(TIM_TypeDef *TIMx, struct TIM_Sim *TIMS)
    Выбор режима четвертого канала и его ÑимулÑциÑ.
    Definition stm32f4xx_matlab_tim.c:281
    +
    CC_PWM_Ch2_Simulation
    void CC_PWM_Ch2_Simulation(TIM_TypeDef *TIMx, struct TIM_Sim *TIMS)
    Выбор режима второго канала и его ÑимулÑциÑ.
    Definition stm32f4xx_matlab_tim.c:185
    +
    mcu_wrapper_conf.h
    Заголовочный файл Ð´Ð»Ñ Ð¾Ð±Ð¾Ð»Ð¾Ñ‡ÐºÐ¸ МК.
    +
    Channels_Sim
    Структура Ð´Ð»Ñ Ð¼Ð¾Ð´ÐµÐ»Ð¸Ñ€Ð¾Ð²Ð°Ð½Ð¸Ñ ÐºÐ°Ð½Ð°Ð»Ð¾Ð² таймера
    Definition stm32f4xx_matlab_tim.h:77
    +
    Channels_Sim::OC2_GPIOx
    GPIO_TypeDef * OC2_GPIOx
    Порт второго канала
    Definition stm32f4xx_matlab_tim.h:88
    +
    Channels_Sim::OC4REF
    unsigned OC4REF
    Четвертый канал
    Definition stm32f4xx_matlab_tim.h:82
    +
    Channels_Sim::OC1_PIN_SHIFT
    uint32_t OC1_PIN_SHIFT
    Пин первого канала
    Definition stm32f4xx_matlab_tim.h:86
    +
    Channels_Sim::OC1_GPIOx
    GPIO_TypeDef * OC1_GPIOx
    Порт первого канала
    Definition stm32f4xx_matlab_tim.h:85
    +
    Channels_Sim::OC3_GPIOx
    GPIO_TypeDef * OC3_GPIOx
    Порт третьего канала
    Definition stm32f4xx_matlab_tim.h:91
    +
    Channels_Sim::OC4_GPIOx
    GPIO_TypeDef * OC4_GPIOx
    Порт четвертого канала
    Definition stm32f4xx_matlab_tim.h:94
    +
    Channels_Sim::OC2REF
    unsigned OC2REF
    Второй канал
    Definition stm32f4xx_matlab_tim.h:80
    +
    Channels_Sim::OC4_PIN_SHIFT
    uint32_t OC4_PIN_SHIFT
    Пин четвертого канала
    Definition stm32f4xx_matlab_tim.h:95
    +
    Channels_Sim::OC1REF
    unsigned OC1REF
    Первый канал
    Definition stm32f4xx_matlab_tim.h:79
    +
    Channels_Sim::OC3REF
    unsigned OC3REF
    Третьий канал
    Definition stm32f4xx_matlab_tim.h:81
    +
    Channels_Sim::OC3_PIN_SHIFT
    uint32_t OC3_PIN_SHIFT
    Пин третьего канала
    Definition stm32f4xx_matlab_tim.h:92
    +
    Channels_Sim::OC2_PIN_SHIFT
    uint32_t OC2_PIN_SHIFT
    Пин второго канала
    Definition stm32f4xx_matlab_tim.h:89
    +
    SlaveChannels
    Структура Ð´Ð»Ñ ÑƒÐ¿Ñ€Ð°Ð²Ð»ÐµÐ½Ð¸Ñ Ð¡Ð»ÐµÐ¹Ð² Таймерами
    Definition stm32f4xx_matlab_tim.h:61
    +
    SlaveChannels::TIM1_TRGO
    unsigned TIM1_TRGO
    Синган Ñинхронизации таймера 1.
    Definition stm32f4xx_matlab_tim.h:62
    +
    SlaveChannels::TIM6_TRGO
    unsigned TIM6_TRGO
    Синган Ñинхронизации таймера 6.
    Definition stm32f4xx_matlab_tim.h:67
    +
    SlaveChannels::TIM8_TRGO
    unsigned TIM8_TRGO
    Синган Ñинхронизации таймера 8
    Definition stm32f4xx_matlab_tim.h:69
    +
    SlaveChannels::TIM2_TRGO
    unsigned TIM2_TRGO
    Синган Ñинхронизации таймера 2.
    Definition stm32f4xx_matlab_tim.h:63
    +
    SlaveChannels::TIM7_TRGO
    unsigned TIM7_TRGO
    Синган Ñинхронизации таймера 7.
    Definition stm32f4xx_matlab_tim.h:68
    +
    SlaveChannels::TIM5_TRGO
    unsigned TIM5_TRGO
    Синган Ñинхронизации таймера 5.
    Definition stm32f4xx_matlab_tim.h:66
    +
    SlaveChannels::TIM3_TRGO
    unsigned TIM3_TRGO
    Синган Ñинхронизации таймера 3.
    Definition stm32f4xx_matlab_tim.h:64
    +
    SlaveChannels::TIM4_TRGO
    unsigned TIM4_TRGO
    Синган Ñинхронизации таймера 4.
    Definition stm32f4xx_matlab_tim.h:65
    +
    TIM_Sim
    Структура Ð´Ð»Ñ Ð¼Ð¾Ð´ÐµÐ»Ð¸Ñ€Ð¾Ð²Ð°Ð½Ð¸Ñ Ñ‚Ð°Ð¹Ð¼ÐµÑ€Ð°
    Definition stm32f4xx_matlab_tim.h:103
    +
    TIM_Sim::RELOAD
    int RELOAD
    Буфер Ð´Ð»Ñ Ð¿ÐµÑ€Ð¸Ð¾Ð´Ð° таймера (Ð´Ð»Ñ Ñ€ÐµÐ°Ð»Ð¸Ð·Ð°Ñ†Ð¸Ð¸ функции PRELOAD)
    Definition stm32f4xx_matlab_tim.h:106
    +
    TIM_Sim::tx_cnt
    double tx_cnt
    Счетчик таймера (double, Ñ‚.к. кол-во тактов за шаг ÑимулÑции может быть дробным)
    Definition stm32f4xx_matlab_tim.h:104
    +
    TIM_Sim::Channels
    struct Channels_Sim Channels
    Структура Ð´Ð»Ñ ÑимулÑции каналов
    Definition stm32f4xx_matlab_tim.h:107
    +
    TIM_Sim::tx_step
    double tx_step
    Шаг Ñчета за один шаг ÑимулÑции (double, Ñ‚.к. кол-во тактов за шаг ÑимулÑции может быть дробным)
    Definition stm32f4xx_matlab_tim.h:105
    diff --git a/DOCS/html/stm32f4xx__periph__registers_8c.html b/DOCS/html/stm32f4xx__periph__registers_8c.html index ea489af..8d17599 100644 --- a/DOCS/html/stm32f4xx__periph__registers_8c.html +++ b/DOCS/html/stm32f4xx__periph__registers_8c.html @@ -5,7 +5,7 @@ -STM MATLAB Simulator: F:/Work/Projects/MATLAB/matlab_stm_emulate/MCU_STM32F4xx_Matlab/Drivers/STM32F4xx_SIMULINK/stm32f4xx_periph_registers.c File Reference +STM MATLAB Simulator: F:/Work/Projects/MATLAB/matlab_stm_emulate/MCU_STM32F4xx_Matlab/STM32F4xx_SIMULINK/stm32f4xx_periph_registers.c File Reference @@ -14,6 +14,7 @@ + @@ -71,7 +72,7 @@ $(function() {
    @@ -80,200 +81,203 @@ $(function() {
    stm32f4xx_periph_registers.c File Reference
    -
    #include "stm32f407xx_matlab.h"
    + +

    ИÑходный код Ñ Ð¿ÐµÑ€ÐµÐ¼ÐµÐ½Ð½Ñ‹Ð¼Ð¸ региÑтров периферии. +More...

    +
    #include "stm32f407xx_matlab.h"
    + Include dependency graph for stm32f4xx_periph_registers.c:
    -
    + +

    Go to the source code of this file.

    +
    - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - +

    Variables

    TIM_TypeDef * tim2 = TIM2
    TIM_TypeDef * tim2 = TIM2
     
    TIM_TypeDef * tim3 = TIM3
    TIM_TypeDef * tim3 = TIM3
     
    TIM_TypeDef * tim4 = TIM4
    TIM_TypeDef * tim4 = TIM4
     
    TIM_TypeDef * tim5 = TIM5
    TIM_TypeDef * tim5 = TIM5
     
    TIM_TypeDef * tim6 = TIM6
    TIM_TypeDef * tim6 = TIM6
     
    TIM_TypeDef * tim7 = TIM7
    TIM_TypeDef * tim7 = TIM7
     
    TIM_TypeDef * tim12 = TIM12
    TIM_TypeDef * tim12 = TIM12
     
    TIM_TypeDef * tim13 = TIM13
    TIM_TypeDef * tim13 = TIM13
     
    TIM_TypeDef * tim14 = TIM14
    TIM_TypeDef * tim14 = TIM14
     
    RTC_TypeDef * rtc = RTC
    RTC_TypeDef * rtc = RTC
     
    WWDG_TypeDef * wwdg = WWDG
    WWDG_TypeDef * wwdg = WWDG
     
    IWDG_TypeDef * iwdg = IWDG
    IWDG_TypeDef * iwdg = IWDG
     
    SPI_TypeDef * i2s2ext = I2S2ext
    SPI_TypeDef * i2s2ext = I2S2ext
     
    SPI_TypeDef * spi2 = SPI2
    SPI_TypeDef * spi2 = SPI2
     
    SPI_TypeDef * spi3 = SPI3
    SPI_TypeDef * spi3 = SPI3
     
    SPI_TypeDef * i2s3ext = I2S3ext
    SPI_TypeDef * i2s3ext = I2S3ext
     
    USART_TypeDef * usart2 = USART2
    USART_TypeDef * usart2 = USART2
     
    USART_TypeDef * usart3 = USART3
    USART_TypeDef * usart3 = USART3
     
    USART_TypeDef * uart4 = UART4
    USART_TypeDef * uart4 = UART4
     
    USART_TypeDef * uart5 = UART5
    USART_TypeDef * uart5 = UART5
     
    I2C_TypeDef * i2c1 = I2C1
    I2C_TypeDef * i2c1 = I2C1
     
    I2C_TypeDef * i2c2 = I2C2
    I2C_TypeDef * i2c2 = I2C2
     
    I2C_TypeDef * i2c3 = I2C3
    I2C_TypeDef * i2c3 = I2C3
     
    CAN_TypeDef * can1 = CAN1
    CAN_TypeDef * can1 = CAN1
     
    CAN_TypeDef * can2 = CAN2
    CAN_TypeDef * can2 = CAN2
     
    PWR_TypeDef * pwr = PWR
    PWR_TypeDef * pwr = PWR
     
    DAC_TypeDef * dac1 = DAC1
    DAC_TypeDef * dac1 = DAC1
     
    DAC_TypeDef * dac = DAC
    DAC_TypeDef * dac = DAC
     
    TIM_TypeDef * tim1 = TIM1
    TIM_TypeDef * tim1 = TIM1
     
    TIM_TypeDef * tim8 = TIM8
    TIM_TypeDef * tim8 = TIM8
     
    USART_TypeDef * usart1 = USART1
    USART_TypeDef * usart1 = USART1
     
    USART_TypeDef * usart6 = USART6
    USART_TypeDef * usart6 = USART6
     
    ADC_TypeDef * adc1 = ADC1
    ADC_TypeDef * adc1 = ADC1
     
    ADC_TypeDef * adc2 = ADC2
    ADC_TypeDef * adc2 = ADC2
     
    ADC_TypeDef * adc3 = ADC3
    ADC_TypeDef * adc3 = ADC3
     
    ADC_Common_TypeDef * adc123_common = ADC123_COMMON
    ADC_Common_TypeDef * adc123_common = ADC123_COMMON
     
    ADC_Common_TypeDef * adc = ADC123_COMMON
    ADC_Common_TypeDef * adc = ADC123_COMMON
     
    SDIO_TypeDef * sdio = SDIO
    SDIO_TypeDef * sdio = SDIO
     
    SPI_TypeDef * spi1 = SPI1
    SPI_TypeDef * spi1 = SPI1
     
    SYSCFG_TypeDef * syscfg = SYSCFG
    SYSCFG_TypeDef * syscfg = SYSCFG
     
    EXTI_TypeDef * exti = EXTI
    EXTI_TypeDef * exti = EXTI
     
    TIM_TypeDef * tim9 = TIM9
    TIM_TypeDef * tim9 = TIM9
     
    TIM_TypeDef * tim10 = TIM10
    TIM_TypeDef * tim10 = TIM10
     
    TIM_TypeDef * tim11 = TIM11
    TIM_TypeDef * tim11 = TIM11
     
    GPIO_TypeDef * gpioa = GPIOA
    GPIO_TypeDef * gpioa = GPIOA
     
    GPIO_TypeDef * gpiob = GPIOB
    GPIO_TypeDef * gpiob = GPIOB
     
    GPIO_TypeDef * gpioc = GPIOC
    GPIO_TypeDef * gpioc = GPIOC
     
    GPIO_TypeDef * gpiod = GPIOD
    GPIO_TypeDef * gpiod = GPIOD
     
    GPIO_TypeDef * gpioe = GPIOE
    GPIO_TypeDef * gpioe = GPIOE
     
    GPIO_TypeDef * gpiof = GPIOF
    GPIO_TypeDef * gpiof = GPIOF
     
    GPIO_TypeDef * gpiog = GPIOG
    GPIO_TypeDef * gpiog = GPIOG
     
    GPIO_TypeDef * gpioh = GPIOH
    GPIO_TypeDef * gpioh = GPIOH
     
    GPIO_TypeDef * gpioi = GPIOI
    GPIO_TypeDef * gpioi = GPIOI
     
    CRC_TypeDef * crc = CRC
    CRC_TypeDef * crc = CRC
     
    RCC_TypeDef * rcc = RCC
    RCC_TypeDef * rcc = RCC
     
    FLASH_TypeDef * flash_r = FLASH
    FLASH_TypeDef * flash_r = FLASH
     
    DMA_TypeDef * dma1 = DMA1
    DMA_TypeDef * dma1 = DMA1
     
    DMA_Stream_TypeDef * dma1_stream0 = DMA1_Stream0
    DMA_Stream_TypeDef * dma1_stream0 = DMA1_Stream0
     
    DMA_Stream_TypeDef * dma1_stream1 = DMA1_Stream1
    DMA_Stream_TypeDef * dma1_stream1 = DMA1_Stream1
     
    DMA_Stream_TypeDef * dma1_stream2 = DMA1_Stream2
    DMA_Stream_TypeDef * dma1_stream2 = DMA1_Stream2
     
    DMA_Stream_TypeDef * dma1_stream3 = DMA1_Stream3
    DMA_Stream_TypeDef * dma1_stream3 = DMA1_Stream3
     
    DMA_Stream_TypeDef * dma1_stream4 = DMA1_Stream4
    DMA_Stream_TypeDef * dma1_stream4 = DMA1_Stream4
     
    DMA_Stream_TypeDef * dma1_stream5 = DMA1_Stream5
    DMA_Stream_TypeDef * dma1_stream5 = DMA1_Stream5
     
    DMA_Stream_TypeDef * dma1_stream6 = DMA1_Stream6
    DMA_Stream_TypeDef * dma1_stream6 = DMA1_Stream6
     
    DMA_Stream_TypeDef * dma1_stream7 = DMA1_Stream7
    DMA_Stream_TypeDef * dma1_stream7 = DMA1_Stream7
     
    DMA_TypeDef * dma2 = DMA2
    DMA_TypeDef * dma2 = DMA2
     
    DMA_Stream_TypeDef * dma2_stream0 = DMA2_Stream0
    DMA_Stream_TypeDef * dma2_stream0 = DMA2_Stream0
     
    DMA_Stream_TypeDef * dma2_stream1 = DMA2_Stream1
    DMA_Stream_TypeDef * dma2_stream1 = DMA2_Stream1
     
    DMA_Stream_TypeDef * dma2_stream2 = DMA2_Stream2
    DMA_Stream_TypeDef * dma2_stream2 = DMA2_Stream2
     
    DMA_Stream_TypeDef * dma2_stream3 = DMA2_Stream3
    DMA_Stream_TypeDef * dma2_stream3 = DMA2_Stream3
     
    DMA_Stream_TypeDef * dma2_stream4 = DMA2_Stream4
    DMA_Stream_TypeDef * dma2_stream4 = DMA2_Stream4
     
    DMA_Stream_TypeDef * dma2_stream5 = DMA2_Stream5
    DMA_Stream_TypeDef * dma2_stream5 = DMA2_Stream5
     
    DMA_Stream_TypeDef * dma2_stream6 = DMA2_Stream6
    DMA_Stream_TypeDef * dma2_stream6 = DMA2_Stream6
     
    DMA_Stream_TypeDef * dma2_stream7 = DMA2_Stream7
    DMA_Stream_TypeDef * dma2_stream7 = DMA2_Stream7
     
    ETH_TypeDef * eth = ETH
    ETH_TypeDef * eth = ETH
     
    DCMI_TypeDef * dcmi = DCMI
    DCMI_TypeDef * dcmi = DCMI
     
    RNG_TypeDef * rng = RNG
    RNG_TypeDef * rng = RNG
     
    FSMC_Bank1_TypeDef * fsmc_bank1_r = FSMC_Bank1
    FSMC_Bank1_TypeDef * fsmc_bank1_r = FSMC_Bank1
     
    FSMC_Bank1E_TypeDef * fsmc_bank1e_r = FSMC_Bank1E
    FSMC_Bank1E_TypeDef * fsmc_bank1e_r = FSMC_Bank1E
     
    FSMC_Bank2_3_TypeDef * fsmc_bank2_3_r = FSMC_Bank2_3
    FSMC_Bank2_3_TypeDef * fsmc_bank2_3_r = FSMC_Bank2_3
     
    FSMC_Bank4_TypeDef * fsmc_bank4_r = FSMC_Bank4
    FSMC_Bank4_TypeDef * fsmc_bank4_r = FSMC_Bank4
     
    DBGMCU_TypeDef * dbgmcu = DBGMCU
    DBGMCU_TypeDef * dbgmcu = DBGMCU
     
    USB_OTG_GlobalTypeDef * usb_otg_fs_periph = USB_OTG_FS
    USB_OTG_GlobalTypeDef * usb_otg_fs_periph = USB_OTG_FS
     
    USB_OTG_GlobalTypeDef * usb_otg_hs_periph = USB_OTG_HS
    USB_OTG_GlobalTypeDef * usb_otg_hs_periph = USB_OTG_HS
     
    -
    +

    Detailed Description

    +

    ИÑходный код Ñ Ð¿ÐµÑ€ÐµÐ¼ÐµÐ½Ð½Ñ‹Ð¼Ð¸ региÑтров периферии.

    +

    Данный файл необходим Ð´Ð»Ñ Ð¾Ð±ÑŠÑÐ²Ð»ÐµÐ½Ð¸Ñ Ñтруктур Ð´Ð»Ñ Ð¾Ñ‚Ð¾Ð±Ñ€Ð°Ð¶ÐµÐ½Ð¸Ñ Ð¸Ñ… в watch Ð’ оригинальном stm32f407xx они объÑвлены дефайнами, которые не видны в watch. ПоÑтому дополнительно объÑвлены данные Ñтруктуры.

    +

    ÐазываютÑÑ Ñ‚Ð°ÐºÐ¶Ðµ, как CMSISные, только в нижнем региÑтре.

    + +

    Definition in file stm32f4xx_periph_registers.c.

    +
    Generated by doxygen 1.10.0 diff --git a/DOCS/html/stm32f4xx__periph__registers_8c__incl.map b/DOCS/html/stm32f4xx__periph__registers_8c__incl.map index dc49d0a..18ba612 100644 --- a/DOCS/html/stm32f4xx__periph__registers_8c__incl.map +++ b/DOCS/html/stm32f4xx__periph__registers_8c__incl.map @@ -1,13 +1,5 @@ - - - - - - - - - - - - + + + + diff --git a/DOCS/html/stm32f4xx__periph__registers_8c__incl.md5 b/DOCS/html/stm32f4xx__periph__registers_8c__incl.md5 index e0d51d5..f237a63 100644 --- a/DOCS/html/stm32f4xx__periph__registers_8c__incl.md5 +++ b/DOCS/html/stm32f4xx__periph__registers_8c__incl.md5 @@ -1 +1 @@ -b322804b999550efe94ad0696ab6e2fb \ No newline at end of file +efb1640eaf6f6ba2af86409c27389bdc \ No newline at end of file diff --git a/DOCS/html/stm32f4xx__periph__registers_8c__incl.png b/DOCS/html/stm32f4xx__periph__registers_8c__incl.png index dddc63d70897b0edad47cddaaea3918793998a58..4ab0c28662ef138c340bef6fee4f31d9dcd0a8cd 100644 GIT binary patch literal 3126 zcmb`JcTf{b9>=2(6>Jm>0!oQb1rd1EP=gObRX_=ff)ObiT7nV@5C}m~0VxtXBoOgQ zFw%rTFbNp(X%vM7=_K?P1VWb60#`0nj-2^Su;9d>(Nuz>)!ezj-y#pwXRz9~D%pDtlUVIS+MqK(|U zd3e9cp~k9*Qp)Et;?rRkk6_oIKU2|+pRkn#!+txk1sGC#W?>vLeiI696c~=Q&k#@YiimI>)%##?qb`w07UCt z#5H89yB2`hH(q@^b_=TSu-H%&&;_2>?lD!03x-?gl> z6p-dO$Z6FY~lSiuR zTujKr3~gxVTFR#oMVN?P=kOHK)m@d1Oe@e0RenK6pW10wtx+zFyxm>!H}*$I>XbuR zHhF}=)7`q*I5RT?O4bh2>A}?T>UGD5=H@Qtk;B&p2L~xQi3gQ6(as9<7QX)F+JB!{ zjiCZ!WQJ#NOMN#=i@;B#qUnotFiV8-q?_MV!< zE_VpziHewu-hz~cvCV2P^P>A&_FJK>O-2hn$#P5tj_X&hL`ayiGmKH4cudk;uB!S4 zu2Ba04Oo;VT3!Bn@6gB2%fswum`y@s+s_4N{T~fP$B)Vn+u_N*T-BQ0nNB}Tk3f~U z4}Q2vI=WA~1e=rO{dzO%FHDD*^w1nY#%0an76B{IJslJe>$s3wA|Bk;;xY2>6#KiK<5SxGHkmShuUMsB0mw`tQ~KR=p4=L zT(>S$Cb^k?Jq;W2Z;*=s>hB-hD{NdJSSm-ryi&r0oVdj9qg`RdVLwFjkSpZ}y}vITh=SEK;VM26s!m4HE$LDVNxFJ17~5t&PH2-i zdxTuNl5bLePcdE6LL6)2>fE?v+Oh$<9tMR{WVFoRu)`1I#@iRhOEQCZGPy`g?!CSs zQK9jL{6wU@0%5pl8m?}WUUXxm=fD68Yx!~G>QQ%iO0e_CNcHTQKZ^~Q9qQNy=`5*9 zP15snqd z2-D>#L|X4T19Fz%p4bNbv!GDyVyGr>cm}D)=)uc<*UP2}L&6m*3m8t>)mgF_}jj70$!FP`B<;GJUSWm$ni&&oIN#;)6pVG)xl2bT{a`3ns$-WWe62B z`l+JMY|PD?ejBWU5lQ#)Y@*7t`{%`J=5s(=?N>Yk`Hy+_LHPsIn-v*!`&^G>x<{Jzwe-eOlSI1# zTD%R{2%kYPK%et_bpxd&(Ns5Kq%KF;%|5u-=|r{DyAI2{SJOtwPwmv85$BydFt!0l zj!kw%a*6aQ_3N6$-%wWv?N5jnrBF@#lI^a*_{$NOod>IOxRm35V+-0O)M?uT-+*P! z$^xR5vsJY?XMgY>sT~s1t#0Qv{?n5@#7`(GIrSU_m~q7f{xuBh&58j=#0oNbS^4rJ zMT_XCi4~}i$12qa&1{a{6fP@swl}qTEH{a(G_}nzn`OIzIJbnz?}JrqDBD{Z>I?Qq{%BjaZkPMS;MSs|{bTM}!H>K^)%%N=_{W1pN||-PuW45h!e^=>VZ-Z{fr?fPid=rv00#oH4&iG; zVy!#xXn;JhjT<4nEEU-p6uT2xVTNH;|Ir$ccRhoUssb9qr|EkZvPwq_5&6=7kWpa* z;bD?EM@}@~we2no1=8W`aG8^moxs_ftia9d6u-~WgGBoFshv;zTfx^mKX-na%RO6=`5riGYYSpfI#}AgjS2QdBXQ$VuGD| zz>2SKj%J&8zvu=36`Y>Bqk#@^C*eI3KeHf^B>dB>q|5;qq>PTTq3qzK70N5APIKX< zY(3^1adr7Yl$gLm&pPTf5NO^1viGo$#a+!0KPnnUz~IG417DkYh(8tmi<5-2vs*34 z7A=J6rpBL85*W2Us+P6Frc-NcSL%7f*FEKZ(JCb!lM2O7Byi|>Q!dXTH<#Oi zd>7cu40W0rVBs!6#5vdC+=9$S0k;de`{?BA>NR8^;|fzQHf;P~Q1xHG$z?0!c>{;T zfs%p--kzu~XZF)fUl2DJ3Nho)a82H|iGAo41E3*P>p6mj&JD;f;Y7Wof0^G^a|h*L za`i>c!E!>Pf@G1#S;J5?dULCoSt<&}UB|6mIxELdiOLrW+Mg*-dd7j7ookbRTL+Cm zg#uF_bN+gZf#402ckXmqjoGIfil^<~v%pw2zm@lKVqKT==^<0!y9926Ll~qNmtGb* z0QcZ~)A9))#o(k_;E%32@@q@b`6h?M0h0vHrQR1bwPoHY4~;x}h$yTLSy^=PkMd?> zC~BCw_WQvJe!j>=2}k^EMa|k&Od$7Gp>UrN52Hj-P($`x7p80djxJif{IF{|Qx4Ns z%k>nJ&^>7_vE#Kl1#Q`#O)}1 zG%|TO^5`}|t@hGUf}Fr)XGJI4+ZrabWZ|^?MYnzDn!Q@x9^Nw>K{$Ug+#@DB?>8m))h6c%>>{_i$6HZ_EpUAk=3(!R$k{;^QV+km7sAEEWFdGM>gU&IXn akeAJyB^s=X2WzkVl6F>(kaCM#G5-MCSwF1+ literal 8423 zcmc(FcT`hfw{1WK=~6_cNDBe!)e@@oKxiTzM5GxYAYD2ZP&$NWKzi@eYrq21q=nv< z9;yfgBnIx$-~Gn>-gn2l|Gs35oa7{XpS9OqYo58*PK3U$1}zmU6$k{Pg=wnZ2Z2bL zfcJz;a6-w~E*e%EtzKmDRQbO;RwmsvGKiymgo4|H0OAdNV9`L2McnE&H z^3oX9YeRzyoO(9-7Q(ZB_o$^)6bdH~O)2p+Z@&`V_kAfd?z?Pbb z_*tnvjm(z*%X3-9r-=>jjXntvk?HvaRwKs;zd)D6>>evI|0>9;lM+^8poBj#L#!fS z)@Asb&iX=F{1VGt?U|?Xpm6F@c9qh3m}<-=ui3)rJLFy2JMukFYuh3TsHod0}^_iSph2Q-Y&8O#nMryXU#kX!qi%E#C~4$_H<4N%l0nr-Rc zSD#8!!k+%zH5nO&!}{p7V>SK%&dT-k9rN{V%NB1a0@{!tp*lfVu}vqc^9#lpRlYOj z{7#C5O9(}oBswsrj^;377?sZ$Wl@V|Cp)KY&uWa7>?a3B*pbS|<9~M5EDO}U<2k-L zV8rPy$OgJY;@Jbf9;x>;*v$P<>w!j^z1iHEYQ61P1ER74#%8imLy{en5W%hQ)t%v8 z+!5UgMhF{hbtNsz0J&2(DxQrvJxNogPcv;g$w+fXkJk0QUd(Zw|G^MlAFZeZ~lcTO?=JX_4qYh z?lU9w4#V-I`r>O#H%yHuKF@$?ZlEZ=jEZ#gbgPpJq6w;A0g5N$Qmzj#a*3fLNIuG6 z3D=t#lH1fR0>xkK?F3QL1yRVpaaEbI`8*E`A4;T2EZWINeL?wfj!vK(Vw)!2kJRL& zg>VXCd}MxEcq$O=DPkj(%7-W8*lNR)1^=zI$->%qw$g$KgO=7+gXg=2y;;mOCW4{^ zXhGf|dpbcIw_G@mpu5C7?z2}$a0L~4(XkC1(8xeLzp)Fmxf3Lzxe}7kzk05!4ON>Q zU9NbTB@|z%FlY-Jrq_goTTbcwqi4HH9-DTgb}WoGSR_}IDBXv99yasHhL&mwZ2k~x zOO>#@YfwjY8*{wj+pdjek~zp6rhN2FTvB4?1&4atAaAeFNAJ-uj15-TIm`?Ug@C7wX}pEMC>Z11M#P)rOh}w5W2g&%jhmDy$K7u*i4`u9UY}8jlEb*U3m9T z0>M4A9dipw`dAgJa&QJSBzPkJwCFhJG&R&?fwT z`K_QFvz?6v^VrAfGy7#lX6NFo2Pqjse*(~c`#CpO{H6u!=8${@?icu|`@YsN+T1wl zTX0b`DfkcKc}XLcA8SxwK1oxEzx&IuB_$;l4h~Wc|A$H8o;2};+B~vqBGeZA zxSfhTQEhmwuuI1K(>`Y3>&O{LJ+NQ9dYWWnrG+|Lt=GSeEY-JF;(Dl4Je(%Gi4Nk- z&lITWlmYh5a}hdF*GCli#cE=A{JHfs(!6JR8nyk~9?TDdT5Qv7l^*=!Di`k8f9HA| z5|s#^7GmwD7Jmz5hGt69JqRY<)(myVy7L$NiY8)(iflph+QjtE`HQ`a=R1K_2Sgrq zx|aES^>p17pu)T4_pdZc51Ly~%qmg5?)qG)TO&7DmgROa13%4bHbJeM$cIKf=^n2r zf3)ph6P%)UgA>%ki@pZ3v3_G?J!jS~ofy3DaQCLTXrW;HMs0&dhnK!V$EW2bT}kCc zFJgJOcG@b)|1~0(`|@uYvt-HklRW4y5A+CHXTj=T?Gq~u7O5&OiIk4K^RQ1r0n`?0 z_ZT!@anS#>fa4a$BC=i1B_uDUYy58Ur|{E6m(i_!!QTD*UHc^2vZx4!$tY_RgN~)8 z_UPI#SGPN7W+#azcBqo<8oe?2=sohu9UnT?kx1yn)BO_=`So?c(XJd?*R30DyuCAD zrT!BnMYT+E<}3wQcTx_)LvrqRIs!{6Y8g+_52|8QC1dG9^Je2D-|P$x4J`&-&QDIB zjpu+aRlk4F<=bK7?|-T^UJX#1GzAFM6NaFpi7Czr32!Fhl0{L{(Ei~7iht*TUb1j4 ztTv>q9c?gvbU}#~%ydnV=&_)Ry#s@S#z=Yr1<(^_M;gSvZAO#P|2f5b!APP>uJUV> zy}SFDt_ibXQx^k!Rry37m_=vTgov@a3dm~-tA7~d+NiqQ#^Euy1-Abp($DBPrvSbw zb^_ft9!5NLL>4u9lhAOgLxykH_&hY2wYN&CZ|7;~C72$S+JeNNT|<9RDn1wvSeQa7 zunQxD5d9ZJT{R)%mpA7aSQsqQZibih(!i}iJ&_2y!x+h3hLJ6Xm|`aRQP;$xcFF#W z;(^!DN{g51`YA&0tzWO)Gj=e@eY{oPYC*x#81j)JOd82h@47B<(U1p}Yx^xc32tm^v5 z`*x&2t}6eV%y}xKp(9T`95s3k@H7vYNoMqkbnviKy@K!I#z?8kJ(Ax?S22TCzkgKC z+GhQZo!R<3yh4tvz|bm<#J>E{9h8YN|#AOC7%xdH%|X? zz5gkz{$c)q!TSH<=K#fp-mBiS;S5@P<+}NdAm>ZWK`V&jG@pL_RaWOVX*98I^$Mg< zhoa0@nq4Eh`(g&*{jeAPmXe8InYXBjiIf|6d?kqSI-^fGb&B^Yb6=oup&U3TZM z?8zqM)d@1FOnteB_WIo9YXKC2MV*ilQA|w>P)+b2h+Ye08U&jlNt2*>j;m zT1!~RaqLuIl!WKJk-H{Hp9&ZN=3U<)femS+(6KTL*%U&5Ou8pYl4N%bwU8clELb&& zoZoVhaAgB+Xn>iNBIdjr!M$F3T{$2n1mGFQ9jmG;P5+e_RhtQ=wj`l7KQ4LX*VuN) z>NOEA8g-B8ZGWY&)xXK#VnYSc}_g&rxrpcHbQjV)m4?)p2=Ube-P zFMw8*aw~?0w(oD(4sABCXA)w;fQ@?baIX6OeRt$^O~IzPc(#LsgS4Wewf8m9{crF7 zs*wLR7J+~d>fK%;R5S45C=bDgVL-!1=^`H5MtOo1K;GIM4 zrZ+#j4q5Xh3155D$qGb_vm-5VI%lP8-%S<_VbF*nJ$(EMymd%A$_T3ALM!1=(Ok?T zF!}kxS%Ibdyy2qC3_=;3XOkDE$ z{Vp9(yI634$MzDW;`m=SGqwe$mpQ}mK)r5>t& zl&-4H41BwG z4%%@1cg68f?e-7J@IT^7HZH4|mX$4=o}MmMfqj7oPo&!^2AK;kfxC^0VEhkztaYt6 z&Au1CyIJ9f*)9qZDLGBNr=hN%QW{I5VESPp#;K4wZJmqW_-0)Hjq zJMfAR&E-id8W);iZodOM@(Q}Leu)JicJ_EK2G5;)?80P&w^hY9_r_dq#Tglhg}OA6 zD3bT#{W#s~>+(j13G?+El>zGNhb6cpe2m=cg7hBSz>%L+(Aw`Rr|wFt2|>ZN$)}A- z`i(>nWGXHk!-NmRZc;Vj-djJ`K_)ogFBJOfWm&0Vm39(bqIz3}wa839C0zT)l4 za@MqIDI01`G=&l-0iNxaEJMZc0LC+7?5;d=%kP7pd{D)L=qQV)l^9MA7P3=GQJyos z9)~#lW?W_mB~y}*hi6wM$pd2$z?j5WxyVUTH#yI+h0>IUCPZz%J50kKx?MRv!Z6=R zU|kNRc+>-o5IcO#%u~z~p=vR}7@56u5L}(_Y+fk>(b073Ig&v;q_DOe#~$Gyj7yLT zaQ2cpm8IrgzE`gWo^g7oUx!RTs9k9>FBCylj{h`LTuhQ)uAB~HJ1qWM+Of;5^j#C8 zFN?VmcB#~!XJmqcQf+pHg!3-Z%PJ=vGT@z&Pi=Kt4LgwJu&m9eaGkg7E{kPSk^sg~ z8^tJ-jYAWjY~{V;dEzuE<_rV8#50^z}KKoWa;UkkgmS*Ds>F~k(v zz#-M{fJm;yr`$@%nZwrmjyT+&7+0c4JP#Lrt7^MSm&q>209CqSs==G=b~t#39Gvqc zUG5vN zu>DxmTu4;*qSH$|(y)>P0o7q8K1QTUynbEK4;#e-cgsD~X3Vi03~G%%o|75c!8`}F zK38K)oH7}$9nZ)uRZ6vCKwqp?_9o8;bm(BCMCIqi2cosCn~kxAVf(j z2I*nI(0B+la<+Zt>U1&0*mV!{5UWYRFYp!;eDtOoOJfXHGk*2i7m0AR{TMo&QsSggqECQx87syrlhrd(!hEfM z$mr0jQ79|BqwqTzq@Uml6qc&xuZ!hwb}-J$RXINrB&gLJkP@TpNUe^xfHmtw7?EIR zt9minV5U2;jz5d`<{42}W^nF~&KhMOg-9V&ob&Q!%$qTd|0I`D_oXq8 zUNSHSN@Y{Hm@>BAZSaPRF#^OG*$JUPDJiNNp9Me#7Vd{?->Rgj$eB*4mFWiD3IKZT z@s7bI7^lyqMV%y7wNtXf?9f3sn2}pk;QnlVKiiOHPGjZVLco7!nyj(+J0%XF0?T=C zaLIGN!8eiUH(tG}#>4RZ6;J9v8D|UxQvBExYoC^}VT^BiV-c{ZVyfQG_-kW-?IY6^ zpsGd=4xzR-0UWJ`a5U}#ZZr}=WqZ2^$VV{a&3Jw0(xB-Q)->r!H?5Wr1)S;9Vxu2r zwEe$L==ij4-gz#W0F)*+K;-iz^n||3l{WMYHq)LFo@7B+CLN-*>1E(j1BLC+y4|Me z%VHS>Sb-+Z^_0ICXV(2ZYKCYtU7&wrQ0>y?=gRT$!)6<{ zKT`{UDAk6x-|ow3mwDAU)=k4FwV=m<$*m5emK9=qEq!T5-IR9sBu9$E-I;mbsOBnx zndNW$eb5-Zqmo)>=>xrqGvOnu7QUX731}-2o2&25tb*!t-2@6T$*+G`%Ey&c`~Zkb z2+{{EV;9-n3Klxyz7~o>C_po{UP#!fA z*{^Hh3CMJr^1REp7xtX>5F3NzW!|>y!6?l`CAf06?Uza67~EjN_>51t5x%zc6FUoM z;FKPMeNxtL1{=SyRoTIZ3)oF-40p&^kvy{%B9G3LlVT&)O&TUWraf{pWtDv&YYZ7vr5GrxN)pV})1$DEu z1Oe5e^tInv>4)7Ybug^3Fuw?F#lxSl(X6D*jk}2!O?LLOM;Kx|=2}0Vd4@4O?jo!c z>x{6it7%DfYFIRY)(rL|^*KClzwspyT`PwA@?M# za%VyY`z?6AH$8!E8M^g3i{Vx1Tx4 z5*~SEDAZ{1@A4eL@Z1cr|eTT=W?Y zF*F#o~@J9kJo)}bNr-FL&T-%ow)d^&{v>b+kkt)+(CvCG9I2^M~n~Y)Hz42 z+P^=rKy3v`ifFYwD6B#|``Q{1?k;0mtyv_R=bnFjS1oXgK( zS9W#qUUAB*wDIuHzoa#ea+t5z-Sp>~DT6Co)aHAlN8=ia@opZYsibZqedF)LcU|ib z_wdL%Hxm|iWn|WIl!XY9T53l+vAGI-Mbu9v9j`N$6RDya0YDN^oKZeEemMPuzo#4k?^uS5&&RzW&?dym^vR&0ryn%KAL6FpwX zc$G6WAg~Jg_jB$?!@VSA_DmY`#d^IRraThU+U44|s@m)&Q`N_@p9!~S#xYS1=PrsX zdmf{oUHyA48)u3Ys@FNE<4R+xaW0D69oss@%5+zW$&$4ery+HM$GCgWGsD-v_Zs1d zAq$V@OsD4HgVFTu^a8SQb4|Q+K#xn-@s>s9JWBoR(QQf0Hdfo=G@|t(3b(!sh2ZRA zVm;n)T8s;p+6m_;g#r88p51wYQ&~H0%0I91eMzj_d>TKXMS2nd5J245BL=hr7}tO0 zbr_>Cx}p5{sY~CAM}7XPb$)x`U?OhCGb`n4`kCwJ!y}~U*$~h*kjF${#~h?3MEukL z?TCD|+4;jC67GS-#Qc>Ngl<=Mu0pV_J;qcf$Dv%DhB zfn|U14|Is}qmzTiHk0->7sS4O$#{~Cb&6O$%gWW*M;Ln=)G+6fpL>J7*74KE>Y;Ln?IA-ij+JtZ#?7Xw@tcYH&ji(6m zzNJK{Z}qjBI6Kc@RZm8H%?4i?4|lJcMZRkg$yF$l&hoWvo?p^x5!T@#3hK?SAiBZ! z;p5x|iVN7z%SIX#wo-bsU%H?@-PS2POQ&H?lWKuQU0sO{gWr7ZP^Kunt<9FN>(zQ; zxLLR3%~5s)Yw;V8$b|-1Y=hz4R_@lGx0(Ho+eEH`v*ZyLv$#e%YfIRcKbW+&i}|Rh|!r_rEE!K(kwSmCU+7 z2rnnxp+P39O>}hB%_h&E83o5NCkUv<$mMh31XQ?tUwQqcFg((wO)KWEFFjnk>egt_ zZar-@?mE9#5EaY6wW!5${$&%qwP>BT<4-JWGg;(?72SAo9*(>!lbqm?mM0tr_x$mC zQr6pLt48DIX48<7V5z+SFKUH5G;?P)LImwNhRDaA^%@T-OpG&#_Z_ftbW=`i8$vRd#Rs;^yRH8;O}0$zId3B-M3!YMifx5; zEY&zn?1R<|yL8I_Y|(|qz_UA4b&_fNs&0Y}kE->(i9MAEXVgYZcS>2(SNvFjc1!%9 z{{jG-ekqO`X~aowG#R(Oc{n|OGsUL!|IuFdk|#OX@8;aIXIEM8N#Lz>r{%cok?#m3 zT^`dvNw=K_hwJI3GScK16clvvXFgNbliODv&*4(d8!;8G4O9qG{eGg7ksK5Vw66dC cK@)RM|9z$sO$%dK|8pLurmI@1{OHAh0XA?ChyVZp diff --git a/DOCS/html/stm32f4xx__periph__registers_8c_source.html b/DOCS/html/stm32f4xx__periph__registers_8c_source.html new file mode 100644 index 0000000..125d2fc --- /dev/null +++ b/DOCS/html/stm32f4xx__periph__registers_8c_source.html @@ -0,0 +1,303 @@ + + + + + + + +STM MATLAB Simulator: F:/Work/Projects/MATLAB/matlab_stm_emulate/MCU_STM32F4xx_Matlab/STM32F4xx_SIMULINK/stm32f4xx_periph_registers.c Source File + + + + + + + + + + + + +
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    stm32f4xx_periph_registers.c
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    +Go to the documentation of this file.
    1/**
    +
    2**************************************************************************
    +
    3* @dir ../MCU_STM32F4xx_Matlab/STM32F4xx_SIMULINK
    +
    4* @brief <b>
    +
    5* Папка Ñ Ð¸Ñходным кодом ÑимулÑтора МК. </b>
    +
    6* @details
    +
    7Ð’ Ñтой папке ÑодержатьÑÑ Ñ„Ð°Ð¹Ð»Ñ‹ Ð´Ð»Ñ ÑмулÑции периферии STM32 в MATLAB.
    +
    8Структура файлов Ñ‚Ð°ÐºÐ°Ñ Ð¶Ðµ, как в библиотеке HAL:
    +
    9- название Ñерии МК, который ÑмулируетÑÑ (stm32f4xx),
    +
    10- идентификатор, что Ñто Ð´Ð»Ñ MATLAB (matlab),
    +
    11- перифериÑ, функции Ð´Ð»Ñ ÑмулÑции которой Ñодержит конкретный файл (gpio, tim).
    +
    12
    +
    13Пример: "stm32f4xx_matlab_tim.c/.h"
    +
    14**************************************************************************/
    +
    15
    +
    16/**
    +
    17**************************************************************************
    +
    18* @file stm32f4xx_periph_registers.c
    +
    19* @brief ИÑходный код Ñ Ð¿ÐµÑ€ÐµÐ¼ÐµÐ½Ð½Ñ‹Ð¼Ð¸ региÑтров периферии.
    +
    20**************************************************************************
    +
    21@details
    +
    22Данный файл необходим Ð´Ð»Ñ Ð¾Ð±ÑŠÑÐ²Ð»ÐµÐ½Ð¸Ñ Ñтруктур Ð´Ð»Ñ Ð¾Ñ‚Ð¾Ð±Ñ€Ð°Ð¶ÐµÐ½Ð¸Ñ Ð¸Ñ… в watch
    +
    23Ð’ оригинальном stm32f407xx они объÑвлены дефайнами, которые не видны в watch.
    +
    24ПоÑтому дополнительно объÑвлены данные Ñтруктуры.
    +
    25
    +
    26ÐазываютÑÑ Ñ‚Ð°ÐºÐ¶Ðµ, как CMSISные, только в нижнем региÑтре.
    +
    27**************************************************************************/
    +
    28#include "stm32f407xx_matlab.h"
    +
    29
    +
    30/**
    +
    31 * @addtogroup PERIPH_VARS_FOR_DEBUG Periphs Variables for Debugging
    +
    32 * @ingroup STM_SIMULATION
    +
    33 * @brief Переменные Ð´Ð»Ñ Ð´Ð¾Ñтупа к периферии в дебаге
    +
    34 * @{
    +
    35 */
    +
    36
    +
    37
    +
    38TIM_TypeDef* tim2 = TIM2;
    +
    39TIM_TypeDef* tim3 = TIM3;
    +
    40TIM_TypeDef* tim4 = TIM4;
    +
    41TIM_TypeDef* tim5 = TIM5;
    +
    42TIM_TypeDef* tim6 = TIM6;
    +
    43TIM_TypeDef* tim7 = TIM7;
    +
    44TIM_TypeDef* tim12 = TIM12;
    +
    45TIM_TypeDef* tim13 = TIM13;
    +
    46TIM_TypeDef* tim14 = TIM14;
    +
    47RTC_TypeDef* rtc = RTC;
    +
    48WWDG_TypeDef* wwdg = WWDG;
    +
    49IWDG_TypeDef* iwdg = IWDG;
    +
    50SPI_TypeDef* i2s2ext = I2S2ext;
    +
    51SPI_TypeDef* spi2 = SPI2;
    +
    52SPI_TypeDef* spi3 = SPI3;
    +
    53SPI_TypeDef* i2s3ext = I2S3ext;
    +
    54USART_TypeDef* usart2 = USART2;
    +
    55USART_TypeDef* usart3 = USART3;
    +
    56USART_TypeDef* uart4 = UART4;
    +
    57USART_TypeDef* uart5 = UART5;
    +
    58I2C_TypeDef* i2c1 = I2C1;
    +
    59I2C_TypeDef* i2c2 = I2C2;
    +
    60I2C_TypeDef* i2c3 = I2C3;
    +
    61CAN_TypeDef* can1 = CAN1;
    +
    62CAN_TypeDef* can2 = CAN2;
    +
    63PWR_TypeDef* pwr = PWR;
    +
    64DAC_TypeDef* dac1 = DAC1;
    +
    65DAC_TypeDef* dac = DAC; /* Kept for legacy purpose = DAC */
    +
    66TIM_TypeDef* tim1 = TIM1;
    +
    67TIM_TypeDef* tim8 = TIM8;
    +
    68USART_TypeDef* usart1 = USART1;
    +
    69USART_TypeDef* usart6 = USART6;
    +
    70ADC_TypeDef* adc1 = ADC1;
    +
    71ADC_TypeDef* adc2 = ADC2;
    +
    72ADC_TypeDef* adc3 = ADC3;
    +
    73ADC_Common_TypeDef* adc123_common = ADC123_COMMON; /* Legacy define */
    +
    74ADC_Common_TypeDef* adc = ADC123_COMMON;
    +
    75SDIO_TypeDef* sdio = SDIO;
    +
    76SPI_TypeDef* spi1 = SPI1;
    +
    77SYSCFG_TypeDef* syscfg = SYSCFG;
    +
    78EXTI_TypeDef* exti = EXTI;
    +
    79TIM_TypeDef* tim9 = TIM9;
    +
    80TIM_TypeDef* tim10 = TIM10;
    +
    81TIM_TypeDef* tim11 = TIM11;
    +
    82GPIO_TypeDef* gpioa = GPIOA;
    +
    83GPIO_TypeDef* gpiob = GPIOB;
    +
    84GPIO_TypeDef* gpioc = GPIOC;
    +
    85GPIO_TypeDef* gpiod = GPIOD;
    +
    86GPIO_TypeDef* gpioe = GPIOE;
    +
    87GPIO_TypeDef* gpiof = GPIOF;
    +
    88GPIO_TypeDef* gpiog = GPIOG;
    +
    89GPIO_TypeDef* gpioh = GPIOH;
    +
    90GPIO_TypeDef* gpioi = GPIOI;
    +
    91CRC_TypeDef* crc = CRC;
    +
    92RCC_TypeDef* rcc = RCC;
    +
    93FLASH_TypeDef* flash_r = FLASH;
    +
    94DMA_TypeDef* dma1 = DMA1;
    +
    95DMA_Stream_TypeDef* dma1_stream0 = DMA1_Stream0;
    +
    96DMA_Stream_TypeDef* dma1_stream1 = DMA1_Stream1;
    +
    97DMA_Stream_TypeDef* dma1_stream2 = DMA1_Stream2;
    +
    98DMA_Stream_TypeDef* dma1_stream3 = DMA1_Stream3;
    +
    99DMA_Stream_TypeDef* dma1_stream4 = DMA1_Stream4;
    +
    100DMA_Stream_TypeDef* dma1_stream5 = DMA1_Stream5;
    +
    101DMA_Stream_TypeDef* dma1_stream6 = DMA1_Stream6;
    +
    102DMA_Stream_TypeDef* dma1_stream7 = DMA1_Stream7;
    +
    103DMA_TypeDef* dma2 = DMA2;
    +
    104DMA_Stream_TypeDef* dma2_stream0 = DMA2_Stream0;
    +
    105DMA_Stream_TypeDef* dma2_stream1 = DMA2_Stream1;
    +
    106DMA_Stream_TypeDef* dma2_stream2 = DMA2_Stream2;
    +
    107DMA_Stream_TypeDef* dma2_stream3 = DMA2_Stream3;
    +
    108DMA_Stream_TypeDef* dma2_stream4 = DMA2_Stream4;
    +
    109DMA_Stream_TypeDef* dma2_stream5 = DMA2_Stream5;
    +
    110DMA_Stream_TypeDef* dma2_stream6 = DMA2_Stream6;
    +
    111DMA_Stream_TypeDef* dma2_stream7 = DMA2_Stream7;
    +
    112ETH_TypeDef* eth = ETH;
    +
    113DCMI_TypeDef* dcmi = DCMI;
    +
    114RNG_TypeDef* rng = RNG;
    +
    115FSMC_Bank1_TypeDef* fsmc_bank1_r = FSMC_Bank1;
    +
    116FSMC_Bank1E_TypeDef* fsmc_bank1e_r = FSMC_Bank1E;
    +
    117FSMC_Bank2_3_TypeDef* fsmc_bank2_3_r = FSMC_Bank2_3;
    +
    118FSMC_Bank4_TypeDef* fsmc_bank4_r = FSMC_Bank4;
    +
    119DBGMCU_TypeDef* dbgmcu = DBGMCU;
    +
    120USB_OTG_GlobalTypeDef* usb_otg_fs_periph = USB_OTG_FS;
    +
    121USB_OTG_GlobalTypeDef* usb_otg_hs_periph = USB_OTG_HS;
    +
    122
    +
    123
    +
    124/** PERIPH_VARS_FOR_DEBUG
    +
    125 * @}
    +
    126 */
    +
    can1
    CAN_TypeDef * can1
    Definition stm32f4xx_periph_registers.c:61
    +
    spi3
    SPI_TypeDef * spi3
    Definition stm32f4xx_periph_registers.c:52
    +
    i2s2ext
    SPI_TypeDef * i2s2ext
    Definition stm32f4xx_periph_registers.c:50
    +
    crc
    CRC_TypeDef * crc
    Definition stm32f4xx_periph_registers.c:91
    +
    dma1_stream4
    DMA_Stream_TypeDef * dma1_stream4
    Definition stm32f4xx_periph_registers.c:99
    +
    dma2_stream1
    DMA_Stream_TypeDef * dma2_stream1
    Definition stm32f4xx_periph_registers.c:105
    +
    dma2_stream4
    DMA_Stream_TypeDef * dma2_stream4
    Definition stm32f4xx_periph_registers.c:108
    +
    dma1_stream5
    DMA_Stream_TypeDef * dma1_stream5
    Definition stm32f4xx_periph_registers.c:100
    +
    gpioe
    GPIO_TypeDef * gpioe
    Definition stm32f4xx_periph_registers.c:86
    +
    dma2_stream7
    DMA_Stream_TypeDef * dma2_stream7
    Definition stm32f4xx_periph_registers.c:111
    +
    gpioc
    GPIO_TypeDef * gpioc
    Definition stm32f4xx_periph_registers.c:84
    +
    dma1_stream0
    DMA_Stream_TypeDef * dma1_stream0
    Definition stm32f4xx_periph_registers.c:95
    +
    uart5
    USART_TypeDef * uart5
    Definition stm32f4xx_periph_registers.c:57
    +
    fsmc_bank2_3_r
    FSMC_Bank2_3_TypeDef * fsmc_bank2_3_r
    Definition stm32f4xx_periph_registers.c:117
    +
    dma2_stream2
    DMA_Stream_TypeDef * dma2_stream2
    Definition stm32f4xx_periph_registers.c:106
    +
    rcc
    RCC_TypeDef * rcc
    Definition stm32f4xx_periph_registers.c:92
    +
    usart3
    USART_TypeDef * usart3
    Definition stm32f4xx_periph_registers.c:55
    +
    tim9
    TIM_TypeDef * tim9
    Definition stm32f4xx_periph_registers.c:79
    +
    rtc
    RTC_TypeDef * rtc
    Definition stm32f4xx_periph_registers.c:47
    +
    usb_otg_hs_periph
    USB_OTG_GlobalTypeDef * usb_otg_hs_periph
    Definition stm32f4xx_periph_registers.c:121
    +
    gpioi
    GPIO_TypeDef * gpioi
    Definition stm32f4xx_periph_registers.c:90
    +
    dma1_stream6
    DMA_Stream_TypeDef * dma1_stream6
    Definition stm32f4xx_periph_registers.c:101
    +
    tim13
    TIM_TypeDef * tim13
    Definition stm32f4xx_periph_registers.c:45
    +
    exti
    EXTI_TypeDef * exti
    Definition stm32f4xx_periph_registers.c:78
    +
    tim10
    TIM_TypeDef * tim10
    Definition stm32f4xx_periph_registers.c:80
    +
    usart1
    USART_TypeDef * usart1
    Definition stm32f4xx_periph_registers.c:68
    +
    gpiof
    GPIO_TypeDef * gpiof
    Definition stm32f4xx_periph_registers.c:87
    +
    usart2
    USART_TypeDef * usart2
    Definition stm32f4xx_periph_registers.c:54
    +
    dma1_stream3
    DMA_Stream_TypeDef * dma1_stream3
    Definition stm32f4xx_periph_registers.c:98
    +
    adc3
    ADC_TypeDef * adc3
    Definition stm32f4xx_periph_registers.c:72
    +
    i2c1
    I2C_TypeDef * i2c1
    Definition stm32f4xx_periph_registers.c:58
    +
    tim11
    TIM_TypeDef * tim11
    Definition stm32f4xx_periph_registers.c:81
    +
    dma2
    DMA_TypeDef * dma2
    Definition stm32f4xx_periph_registers.c:103
    +
    dcmi
    DCMI_TypeDef * dcmi
    Definition stm32f4xx_periph_registers.c:113
    +
    tim8
    TIM_TypeDef * tim8
    Definition stm32f4xx_periph_registers.c:67
    +
    tim5
    TIM_TypeDef * tim5
    Definition stm32f4xx_periph_registers.c:41
    +
    fsmc_bank4_r
    FSMC_Bank4_TypeDef * fsmc_bank4_r
    Definition stm32f4xx_periph_registers.c:118
    +
    wwdg
    WWDG_TypeDef * wwdg
    Definition stm32f4xx_periph_registers.c:48
    +
    tim3
    TIM_TypeDef * tim3
    Definition stm32f4xx_periph_registers.c:39
    +
    tim14
    TIM_TypeDef * tim14
    Definition stm32f4xx_periph_registers.c:46
    +
    eth
    ETH_TypeDef * eth
    Definition stm32f4xx_periph_registers.c:112
    +
    sdio
    SDIO_TypeDef * sdio
    Definition stm32f4xx_periph_registers.c:75
    +
    spi1
    SPI_TypeDef * spi1
    Definition stm32f4xx_periph_registers.c:76
    +
    dma2_stream6
    DMA_Stream_TypeDef * dma2_stream6
    Definition stm32f4xx_periph_registers.c:110
    +
    dma2_stream5
    DMA_Stream_TypeDef * dma2_stream5
    Definition stm32f4xx_periph_registers.c:109
    +
    flash_r
    FLASH_TypeDef * flash_r
    Definition stm32f4xx_periph_registers.c:93
    +
    dma1_stream1
    DMA_Stream_TypeDef * dma1_stream1
    Definition stm32f4xx_periph_registers.c:96
    +
    syscfg
    SYSCFG_TypeDef * syscfg
    Definition stm32f4xx_periph_registers.c:77
    +
    gpioh
    GPIO_TypeDef * gpioh
    Definition stm32f4xx_periph_registers.c:89
    +
    iwdg
    IWDG_TypeDef * iwdg
    Definition stm32f4xx_periph_registers.c:49
    +
    adc2
    ADC_TypeDef * adc2
    Definition stm32f4xx_periph_registers.c:71
    +
    spi2
    SPI_TypeDef * spi2
    Definition stm32f4xx_periph_registers.c:51
    +
    tim4
    TIM_TypeDef * tim4
    Definition stm32f4xx_periph_registers.c:40
    +
    usb_otg_fs_periph
    USB_OTG_GlobalTypeDef * usb_otg_fs_periph
    Definition stm32f4xx_periph_registers.c:120
    +
    pwr
    PWR_TypeDef * pwr
    Definition stm32f4xx_periph_registers.c:63
    +
    fsmc_bank1_r
    FSMC_Bank1_TypeDef * fsmc_bank1_r
    Definition stm32f4xx_periph_registers.c:115
    +
    dac1
    DAC_TypeDef * dac1
    Definition stm32f4xx_periph_registers.c:64
    +
    fsmc_bank1e_r
    FSMC_Bank1E_TypeDef * fsmc_bank1e_r
    Definition stm32f4xx_periph_registers.c:116
    +
    i2c3
    I2C_TypeDef * i2c3
    Definition stm32f4xx_periph_registers.c:60
    +
    adc
    ADC_Common_TypeDef * adc
    Definition stm32f4xx_periph_registers.c:74
    +
    tim6
    TIM_TypeDef * tim6
    Definition stm32f4xx_periph_registers.c:42
    +
    usart6
    USART_TypeDef * usart6
    Definition stm32f4xx_periph_registers.c:69
    +
    dbgmcu
    DBGMCU_TypeDef * dbgmcu
    Definition stm32f4xx_periph_registers.c:119
    +
    tim2
    TIM_TypeDef * tim2
    Definition stm32f4xx_periph_registers.c:38
    +
    tim7
    TIM_TypeDef * tim7
    Definition stm32f4xx_periph_registers.c:43
    +
    gpiod
    GPIO_TypeDef * gpiod
    Definition stm32f4xx_periph_registers.c:85
    +
    dma1
    DMA_TypeDef * dma1
    Definition stm32f4xx_periph_registers.c:94
    +
    dac
    DAC_TypeDef * dac
    Definition stm32f4xx_periph_registers.c:65
    +
    adc123_common
    ADC_Common_TypeDef * adc123_common
    Definition stm32f4xx_periph_registers.c:73
    +
    i2s3ext
    SPI_TypeDef * i2s3ext
    Definition stm32f4xx_periph_registers.c:53
    +
    dma2_stream3
    DMA_Stream_TypeDef * dma2_stream3
    Definition stm32f4xx_periph_registers.c:107
    +
    gpiob
    GPIO_TypeDef * gpiob
    Definition stm32f4xx_periph_registers.c:83
    +
    can2
    CAN_TypeDef * can2
    Definition stm32f4xx_periph_registers.c:62
    +
    rng
    RNG_TypeDef * rng
    Definition stm32f4xx_periph_registers.c:114
    +
    uart4
    USART_TypeDef * uart4
    Definition stm32f4xx_periph_registers.c:56
    +
    dma1_stream7
    DMA_Stream_TypeDef * dma1_stream7
    Definition stm32f4xx_periph_registers.c:102
    +
    gpiog
    GPIO_TypeDef * gpiog
    Definition stm32f4xx_periph_registers.c:88
    +
    tim1
    TIM_TypeDef * tim1
    Definition stm32f4xx_periph_registers.c:66
    +
    dma2_stream0
    DMA_Stream_TypeDef * dma2_stream0
    Definition stm32f4xx_periph_registers.c:104
    +
    adc1
    ADC_TypeDef * adc1
    Definition stm32f4xx_periph_registers.c:70
    +
    dma1_stream2
    DMA_Stream_TypeDef * dma1_stream2
    Definition stm32f4xx_periph_registers.c:97
    +
    i2c2
    I2C_TypeDef * i2c2
    Definition stm32f4xx_periph_registers.c:59
    +
    tim12
    TIM_TypeDef * tim12
    Definition stm32f4xx_periph_registers.c:44
    +
    gpioa
    GPIO_TypeDef * gpioa
    Definition stm32f4xx_periph_registers.c:82
    +
    + +
    +Generated by doxygen 1.10.0 +
    + + diff --git a/DOCS/html/struct__cortex__memory.html b/DOCS/html/struct__cortex__memory.html index 4392bfc..bfe9f89 100644 --- a/DOCS/html/struct__cortex__memory.html +++ b/DOCS/html/struct__cortex__memory.html @@ -14,6 +14,7 @@ + @@ -73,19 +74,39 @@ $(function() {
    Data Fields
    -
    _cortex_memory Struct Reference
    Defines and Type Definitions » Status and Control Registers » Nested Vectored Interrupt Controller (NVIC) » System Control Block (SCB) » System Controls not in SCB (SCnSCB) » System Tick Timer (SysTick) » Instrumentation Trace Macrocell (ITM) » Data Watchpoint and Trace (DWT) » Trace Port Interface (TPI) » Floating Point Unit (FPU) » Core Debug Registers (CoreDebug) » Core register bit field macros » Core Definitions
    +
    _cortex_memory Struct Reference
    Core Definitions
    -

    #include <core_cm4_matlab.h>

    +

    #include <stm32f407xx_matlab_memory.h>

    - - + +

    Data Fields

    uint8_t CORTEX_PERIPH_BASE [0xE0100000 - 0xE0000000]
     
    uint8_t CORTEX_PERIPH_BASE [0xE0100000 - 0xE0000000]
     
    +

    Detailed Description

    +
    +

    Definition at line 26 of file stm32f407xx_matlab_memory.h.

    +

    Field Documentation

    + +

    ◆ CORTEX_PERIPH_BASE

    + +
    +
    + + + + +
    uint8_t CORTEX_PERIPH_BASE[0xE0100000 - 0xE0000000]
    +
    + +

    Definition at line 28 of file stm32f407xx_matlab_memory.h.

    + +
    +
    The documentation for this struct was generated from the following file:
    diff --git a/DOCS/html/struct__memory.html b/DOCS/html/struct__memory.html index 30e5996..041e850 100644 --- a/DOCS/html/struct__memory.html +++ b/DOCS/html/struct__memory.html @@ -14,6 +14,7 @@ + @@ -73,41 +74,255 @@ $(function() {
    Data Fields
    -
    _memory Struct Reference
    CMSIS_Device » Stm32f407xx » Peripheral_memory_map
    +
    _memory Struct Reference
    Core Definitions » Peripheral Memory Map
    -

    #include <stm32f407xx_matlab.h>

    +

    #include <stm32f407xx_matlab_memory.h>

    - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + +

    Data Fields

    uint8_t FLASH_BASE [FLASH_SIZE]
     
    uint8_t CCMDATARAM_BASE [CCMDATARAM_SIZE]
     
    uint8_t FLASH_OTP_BASE [FLASH_OTP_SIZE]
     
    uint8_t SRAM1_BASE [SRAM1_SIZE]
     
    uint8_t SRAM2_BASE [SRAM2_SIZE]
     
    uint8_t SRAM1_BB_BASE [SRAM1_SIZE]
     
    uint8_t SRAM2_BB_BASE [SRAM2_SIZE]
     
    uint8_t PERIPH_BASE [PERIPH_SIZE]
     
    uint8_t BKPSRAM_BASE [BKPSRAM_SIZE]
     
    uint8_t PERIPH_BB_BASE [PERIPH_BB_SIZE]
     
    uint8_t BKPSRAM_BB_BASE [BKPSRAM_SIZE]
     
    uint8_t FSMC_R_BASE [FSMC_R_SIZE]
     
    uint8_t FLASH_BASE [FLASH_SIZE]
     
    uint8_t CCMDATARAM_BASE [CCMDATARAM_SIZE]
     
    uint8_t FLASH_OTP_BASE [FLASH_OTP_SIZE]
     
    uint8_t SRAM1_BASE [SRAM1_SIZE]
     
    uint8_t SRAM2_BASE [SRAM2_SIZE]
     
    uint8_t SRAM1_BB_BASE [SRAM1_SIZE]
     
    uint8_t SRAM2_BB_BASE [SRAM2_SIZE]
     
    uint8_t PERIPH_BASE [PERIPH_SIZE]
     
    uint8_t BKPSRAM_BASE [BKPSRAM_SIZE]
     
    uint8_t PERIPH_BB_BASE [PERIPH_BB_SIZE]
     
    uint8_t BKPSRAM_BB_BASE [BKPSRAM_SIZE]
     
    uint8_t FSMC_R_BASE [FSMC_R_SIZE]
     
    uint8_t DEBUG_MCU_BASE [DEBUG_MCU_SIZE]
     
    +

    Detailed Description

    +
    +

    Definition at line 106 of file stm32f407xx_matlab_memory.h.

    +

    Field Documentation

    + +

    ◆ FLASH_BASE

    + +
    +
    + + + + +
    uint8_t FLASH_BASE[FLASH_SIZE]
    +
    + +

    Definition at line 110 of file stm32f407xx_matlab_memory.h.

    + +
    +
    + +

    ◆ CCMDATARAM_BASE

    + +
    +
    + + + + +
    uint8_t CCMDATARAM_BASE[CCMDATARAM_SIZE]
    +
    + +

    Definition at line 111 of file stm32f407xx_matlab_memory.h.

    + +
    +
    + +

    ◆ FLASH_OTP_BASE

    + +
    +
    + + + + +
    uint8_t FLASH_OTP_BASE[FLASH_OTP_SIZE]
    +
    + +

    Definition at line 112 of file stm32f407xx_matlab_memory.h.

    + +
    +
    + +

    ◆ SRAM1_BASE

    + +
    +
    + + + + +
    uint8_t SRAM1_BASE[SRAM1_SIZE]
    +
    + +

    Definition at line 113 of file stm32f407xx_matlab_memory.h.

    + +
    +
    + +

    ◆ SRAM2_BASE

    + +
    +
    + + + + +
    uint8_t SRAM2_BASE[SRAM2_SIZE]
    +
    + +

    Definition at line 114 of file stm32f407xx_matlab_memory.h.

    + +
    +
    + +

    ◆ SRAM1_BB_BASE

    + +
    +
    + + + + +
    uint8_t SRAM1_BB_BASE[SRAM1_SIZE]
    +
    + +

    Definition at line 115 of file stm32f407xx_matlab_memory.h.

    + +
    +
    + +

    ◆ SRAM2_BB_BASE

    + +
    +
    + + + + +
    uint8_t SRAM2_BB_BASE[SRAM2_SIZE]
    +
    + +

    Definition at line 116 of file stm32f407xx_matlab_memory.h.

    + +
    +
    + +

    ◆ PERIPH_BASE

    + +
    +
    + + + + +
    uint8_t PERIPH_BASE[PERIPH_SIZE]
    +
    + +

    Definition at line 117 of file stm32f407xx_matlab_memory.h.

    + +
    +
    + +

    ◆ BKPSRAM_BASE

    + +
    +
    + + + + +
    uint8_t BKPSRAM_BASE[BKPSRAM_SIZE]
    +
    + +

    Definition at line 118 of file stm32f407xx_matlab_memory.h.

    + +
    +
    + +

    ◆ PERIPH_BB_BASE

    + +
    +
    + + + + +
    uint8_t PERIPH_BB_BASE[PERIPH_BB_SIZE]
    +
    + +

    Definition at line 119 of file stm32f407xx_matlab_memory.h.

    + +
    +
    + +

    ◆ BKPSRAM_BB_BASE

    + +
    +
    + + + + +
    uint8_t BKPSRAM_BB_BASE[BKPSRAM_SIZE]
    +
    + +

    Definition at line 120 of file stm32f407xx_matlab_memory.h.

    + +
    +
    + +

    ◆ FSMC_R_BASE

    + +
    +
    + + + + +
    uint8_t FSMC_R_BASE[FSMC_R_SIZE]
    +
    + +

    Definition at line 121 of file stm32f407xx_matlab_memory.h.

    + +
    +
    + +

    ◆ DEBUG_MCU_BASE

    + +
    +
    + + + + +
    uint8_t DEBUG_MCU_BASE[DEBUG_MCU_SIZE]
    +
    + +

    Definition at line 122 of file stm32f407xx_matlab_memory.h.

    + +
    +
    The documentation for this struct was generated from the following file:
    diff --git a/DOCS/html/struct_a_d_c___common___type_def.html b/DOCS/html/struct_a_d_c___common___type_def.html deleted file mode 100644 index f9644c2..0000000 --- a/DOCS/html/struct_a_d_c___common___type_def.html +++ /dev/null @@ -1,100 +0,0 @@ - - - - - - - -STM MATLAB Simulator: ADC_Common_TypeDef Struct Reference - - - - - - - - - - - -
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    CMSIS_Device » Stm32f407xx » Peripheral_registers_structures
    -
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    #include <stm32f407xx_matlab.h>

    - - - - - - - - -

    -Data Fields

    __IO uint32_t CSR
     
    __IO uint32_t CCR
     
    __IO uint32_t CDR
     
    -
    The documentation for this struct was generated from the following file:
      -
    • F:/Work/Projects/MATLAB/matlab_stm_emulate/MCU_STM32F4xx_Matlab/Drivers/CMSIS/stm32f407xx_matlab.h
      • -
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    Analog to Digital Converter
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    #include <stm32f407xx_matlab.h>

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    -Data Fields

    uint32_t SR
     
    __IO uint32_t CR1
     
    __IO uint32_t CR2
     
    __IO uint32_t SMPR1
     
    __IO uint32_t SMPR2
     
    __IO uint32_t JOFR1
     
    __IO uint32_t JOFR2
     
    __IO uint32_t JOFR3
     
    __IO uint32_t JOFR4
     
    __IO uint32_t HTR
     
    __IO uint32_t LTR
     
    __IO uint32_t SQR1
     
    __IO uint32_t SQR2
     
    __IO uint32_t SQR3
     
    __IO uint32_t JSQR
     
    __IO uint32_t JDR1
     
    __IO uint32_t JDR2
     
    __IO uint32_t JDR3
     
    __IO uint32_t JDR4
     
    __IO uint32_t DR
     
    -

    Detailed Description

    -

    Analog to Digital Converter
    -

    -
    The documentation for this struct was generated from the following file:
      -
    • F:/Work/Projects/MATLAB/matlab_stm_emulate/MCU_STM32F4xx_Matlab/Drivers/CMSIS/stm32f407xx_matlab.h
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    CMSIS_Device » Stm32f407xx » Peripheral_registers_structures
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    Controller Area Network FIFOMailBox. - More...

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    #include <stm32f407xx_matlab.h>

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    -Data Fields

    __IO uint32_t RIR
     
    __IO uint32_t RDTR
     
    __IO uint32_t RDLR
     
    __IO uint32_t RDHR
     
    -

    Detailed Description

    -

    Controller Area Network FIFOMailBox.

    -
    The documentation for this struct was generated from the following file:
      -
    • F:/Work/Projects/MATLAB/matlab_stm_emulate/MCU_STM32F4xx_Matlab/Drivers/CMSIS/stm32f407xx_matlab.h
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    - - diff --git a/DOCS/html/struct_c_a_n___filter_register___type_def.html b/DOCS/html/struct_c_a_n___filter_register___type_def.html deleted file mode 100644 index 27e9571..0000000 --- a/DOCS/html/struct_c_a_n___filter_register___type_def.html +++ /dev/null @@ -1,103 +0,0 @@ - - - - - - - -STM MATLAB Simulator: CAN_FilterRegister_TypeDef Struct Reference - - - - - - - - - - - -
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    #include <stm32f407xx_matlab.h>

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    -Data Fields

    __IO uint32_t FR1
     
    __IO uint32_t FR2
     
    -

    Detailed Description

    -

    Controller Area Network FilterRegister.

    -
    The documentation for this struct was generated from the following file:
      -
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    __IO uint32_t TIR
     
    __IO uint32_t TDTR
     
    __IO uint32_t TDLR
     
    __IO uint32_t TDHR
     
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    -Data Fields

    __IO uint32_t MCR
     
    __IO uint32_t MSR
     
    __IO uint32_t TSR
     
    __IO uint32_t RF0R
     
    __IO uint32_t RF1R
     
    __IO uint32_t IER
     
    __IO uint32_t ESR
     
    __IO uint32_t BTR
     
    uint32_t RESERVED0 [88]
     
    CAN_TxMailBox_TypeDef sTxMailBox [3]
     
    CAN_FIFOMailBox_TypeDef sFIFOMailBox [2]
     
    uint32_t RESERVED1 [12]
     
    __IO uint32_t FMR
     
    __IO uint32_t FM1R
     
    uint32_t RESERVED2
     
    __IO uint32_t FS1R
     
    uint32_t RESERVED3
     
    __IO uint32_t FFA1R
     
    uint32_t RESERVED4
     
    __IO uint32_t FA1R
     
    uint32_t RESERVED5 [8]
     
    CAN_FilterRegister_TypeDef sFilterRegister [28]
     
    -

    Detailed Description

    -

    Controller Area Network.

    -
    The documentation for this struct was generated from the following file:
      -
    • F:/Work/Projects/MATLAB/matlab_stm_emulate/MCU_STM32F4xx_Matlab/Drivers/CMSIS/stm32f407xx_matlab.h
      • -
    -
    - -
    -Generated by doxygen 1.10.0 -
    - - diff --git a/DOCS/html/struct_c_a_n___type_def__coll__graph.map b/DOCS/html/struct_c_a_n___type_def__coll__graph.map deleted file mode 100644 index 4e58ebb..0000000 --- a/DOCS/html/struct_c_a_n___type_def__coll__graph.map +++ /dev/null @@ -1,9 +0,0 @@ - - - - - - - - - diff --git a/DOCS/html/struct_c_a_n___type_def__coll__graph.md5 b/DOCS/html/struct_c_a_n___type_def__coll__graph.md5 deleted file mode 100644 index 2b9594f..0000000 --- a/DOCS/html/struct_c_a_n___type_def__coll__graph.md5 +++ /dev/null @@ -1 +0,0 @@ -0b0802d2e614887777a61a784367203a \ No newline at end of file diff --git a/DOCS/html/struct_c_a_n___type_def__coll__graph.png b/DOCS/html/struct_c_a_n___type_def__coll__graph.png deleted file mode 100644 index 3762e0c68189de1f5bafd55048d38c22547160d9..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 6214 zcmZWuc|4Tw*M2A|$}TBOktN$`u?-Ri$vWAxm+WiyeM>S%wq!S!@x|DNvhPx|g=C8{ zLoy8pV_!nv$M5@l|9RhMKA(B!kNdfwbFOpFb)R!htiGYdpQp%g7tc%RCAq zj$XTG&+D4#v0Pd26%am4bM_|Hos>+h|H(r^A82Ul8g{v=?C=1Ul9JgTvSa9LGKrhr zGrIHu_J1xmhz%5AX5Ohc6!Fbny2xgkW~Z1tXivG-Q8{aPg^!O9U`nQB4m}tl1`>h* zQrhg7`Dg^6X$8w{LF{@^J#l*o~0;O776J z%=$$E%*iQ%LyFxqcL4HBcOM&@`S=+bOiU=xgMW}5$tKvEva(CO=Bu{{2?Sw{rc6?L z!?yfpk$Tfh3wwPvjl0p=v3xP!RtSW!aT&Ly12V<9cFW>U)TvXx z(HI7AL(w<(?&Ym|u-%ibt$>b!stNmp&{Vg>zVSX^%x5J=5N^xz*7Rb+H+b9OkwnRd zwxBZcs;SxI-(}(lMv+0YTPLDL&&8jW(fEKVqWP_C}%lU62XxJj8z z1+zLuiz$oqv6Fq5m%Ir5H6;hX==guFFk=lYSClB5UX?2~dRJGTS&*m879M#S0+%JV z6SBWkw#bUuOs>H@Fm}S7 zV9yR`JFHqE$%Mc`^K6@X{E+Jczs3_q(@1s*T#j@f5vyF;+PLGj-vs%J?UxkPl4_YT zPIGHMlop0h$=KgJJTgX#cQg#n@W3vwnf&z`2peC~SC@B-DV=^bzsWU-*`0z{4Q?JT zS9%v(C}X3nBiSHz&C6zZO|<0N!;j?d$vWI#yznshB70kFC62RMSm{Uo=8Y_abD(L_|+;dFZG%AT&|m8R32lEvGt;E;-JiT zN6TN^uZzE!acVGnP0dtUHRa70WLuXvV$C(;(#ii54EpP_N$k7jeb7Og01@M#%z z#3B2hC^|?*-0CO{C;2`lTFQ0o0&0zb6+#fRt!P=%tsWU)j**A#aQ;Z`A3JxMs|d6z zb)>^4i0fcTQupz70}sn%ta)M2!Bm>(Y(i?Y@2umykHb*Uj`^_hOZ`IXCV$BbcW_QZ z3Do4k3*Pg3-*~@=38_n`lxMz)7rZ=yOH;P61&T`+y2^n+(#P>2{huFQO_> z?gd|Llv69;1Vs?*KdcCEOV;y$dsY~94LzbRax&*gJQ!3cvGNZs#D;VX?`(N1R@!=$ z;PW?YKjd7u-ohaJ+kg6-4%Xw{TV|@JTNEp#h3}*9EKJ=hup)uvfJryHCXGF6npoFi zQq>=y#`wN`kn?%daLHYf)Xu%?n&NCZ$)-0W^RoLG*=0;He@rGhcgW!U4k-9gOvweDcaS-q-MSF;pccay^v{0Q5fYq7B(EnD`!PD|aE+wNL> ztDUOtK%Zh~niw;JEo%p!9`El5Tp2Vt6EzxhacwC)FmZ{i?GbGMOG&RRCZNy0W)F~^ zd~lggdFYnK#nf8SDtud?-~?l}a>q+Mdr{ma$q zuR|&zfPldmhozUPO3^82)|~(&dml|+m;;sU3vF{M_RzP{^lFiNn>TowpVpi0zgiN5 z+497t^CXKvT?)MJv*kXxns&$+L1Qr+>k5m<6!CH(%9b-AYDIc#jAAxw zLiu;j&RGF6_f2cVKdZdf?weY($B2Ctr5L0x{go-I7Z2)kl%&&!q9zWuNWa!UG0Jd9 z^VuKnt_G|%ktRr62WN)17pBw|MScl-3=1H6jYoKuX$~1LzH|zhka7;ZrbeU#8V2j) z5{dt;dz|t1vxCe8{CPFCFsAiE_ot42D>vHCy4Ke0@DYh>zwG@}Hen;nlV1MBj0Ddl zleXh4B1w$FE2g8SL78@@dxnHBx#>LVHTb>r>(BA#y=H*l?jS*tGU|_NrUy3b zgLA0!XkOfpaJc@byEePE&(?mKy9u`8%-&|jaD*<3Af!tOa&XeCTi)t;L00g1x@?)& z&q>$H@xZ#TW`*6HB{6eIoz`YUrB_H}wla68gYGL!D&(J@6*5E6*RIN~+VDS*sH}9^ zQ7$?Q{}57Y@SZ?V!L)->DW!6$GA?{{Lw`(4UAOsg94hBhN=INZw4!bhcyq zaac$_O07^GJegCj{k!;2K-s<31{)l@1Q+;sy8C$y$#swRU}5ol1Roq?a9~^4Wv4VE z;H;{M4iEC&Dk4*iBDk&m#LMViM!v z);qQKJ7+b_mi-;&wzC0(I^Y7WbXv~ zy{c2_$#nyMz2+ekD%W#9WfRYRC<^IPoH7Tq+;7yy=U-XU4JwzI22aqAnzNW|lhBI; z0?0g*k;(K~!3S59-Dse2u2+3IkX95o1RXUMwsO~HBc+K^ z1mWZ=0FNtaNCe7WUWlFsjdDqm>r={ggB9TXIrqXPQBjDXI2F5_w|Dzk)};VQXUZO? zD4cQb-b!{WSy@d%G=H@jsynp`4i57Bnh zoVhW2JV2E>EmPurHK}gt_Mv(4)?@D{t@<~=;^lI{n$4d0u@=D)5Wm>TJYVy&8@^NZ`7DH$PL`*b571syGfL()r0#V%cE)}YAQl;=ZP|LzyQLv8#>w~%(C{X-=J7k-~Z`P6<9$ZWCog; z9w7ww(0u40{X$66LQdDEV(%n5E@||S7CE^;#-p4F;gHif<<;QxFpE$OSGVSITO6z3 zt%-@7NKGvtw$5S0?JsY#XP!b?nQ27HZ0F84UJ;p8-PRngk!W}P`Zs#X!j=Jau&u&C z*2oZhZe5w?i&$zEuiy5kSvgAm)}!JYW_U2jG+D^7Ga_5;`VtmTZD z2-!pTa$3fa>c;6xCnkq?T^uq| zgk8_T%1@uc_n3Xraeu^tVk}*ZrB*0LyPRw<9?^Qm&I{={6go~ddKOApHgD(uj4#qk zr(+b1uQZpupW#iHo(>BaM^iXb=|`XME|sEd27RQFyq6&`;Ewwy!DmEHOO4}!T?*3g zh>e`-K^){ce{JWwp?u>6lxed6+uFw|kCxSK3ANIQ#a%Z-#khvjJ+fYn;95+-lIV+H zojI00|9n|F+1#4R-;LYEIq#&6PfIIzKn6UjCPfV^<8`sB?{=~o9sqa zl~z_y?p%gtr}ElVa`{Bb24pUp?Pe=l`VcJ1O~j6vy*wYu-R_+Q)YjMPFaEK;|Oe0a25`d|l66LKYz z6GKiDC|O4-?`q^gL!<8Rit%o1k8HnR(pB$HllgsI2TQ7X<>Oi9w&$yo?{&JK*jGwl z8w|V<6o`KX_Ne0hjeRmGJ0@`b*eYB#AQ!^pAt+jgLul=-hNpS0g?N|FW>&$}8 z_xtMJz;dN|%apvLtD##i>8Ueb8JWS;n*$Hk{1;i3u!4ipPf@ayoZVrz6jF%Y{eOa^88It z1VIR$r^B8$^9*WY(d~x0EAnGYg)J$x#MIgbN(+DTLHF4M-#-$VRt%csh~VpPNwc9% zLb6^K{Wy2-=JNGu1f*;4)6~aMhS$v6J_7ICnn>09Dx!*%G^iQpY3$I^A zgvtF9j4R&ytSJFkP(8Odlis}dxp^|^270ZhCLRHOXebQ?#9E7ET#CJE*xK(ba@XOp62MTU_H) z2=X6`NIG4$O7S5IJOcDGhG2&DU`#nBy|Z>6dfoe3YEjfVh~9()6d6=}kk-Vl){mPN z!84LsKK$F-c>rQowQ;W4$_2`}lOPq>lki@QA|foIKSE;L z=YrKNMN}nev7G};n>lH^-cdecwb)zVqZha4MCZXDp~2o5@*;pF^Pl!{$pRMU*(Cwj zUU1u!9p%KxuUsJnGDdhaoNQ?%46>ob=sA$rbbkmSBP$F7vN5h_s;NXy-d@!@s-47g ze7evAyB7s!)9obBl)cqM)g*}W_HL`?OjZNlClNIfBxD#6&%wJ%-!OFTJ-$$fbe)bq z*a~4|Zw>is1l$+ttl>%G-ma*!ZWP!M8lCE`n3;c{GQMd{_d+_tqaGghSv+meROKblvlq6u-iIk304V zoCiK>J6uQdg|YH4Q@LDDVsqvuhRFQA>hN@h;Y!Tn3e3YgUq_Pp1)3IRkbRHuXP+Yb+#E$SD&2AFUMAA zH{k6636pM3fX8@Fi{Nt-j{Q-;=mb2>j@Mw*1Q{#nTl-HmBy&g^FiZh0APhsR>3gb)N^-w=xkj8v}D{93qo?Jz#B>0>cpi#PL$|(~VT$091oEIRm zxkvP;0)BD*(BaMYOg~hM>_M6^7x+~3*G=L8DYkdA%XxP5PvxZIF^5OcZf}g=%2K$K zNCnXl`uAha?8f0_qT>D$bK?EcQoBFC3pG9M&+_lN%qD@{zroX560H z@h_|ARBMgd!4@Q$3r~ zxVd#?Y-s+km{*YltK|TLO#R}8C%o!MMpG4DrRZu0=S$ - - - - - - -STM MATLAB Simulator: CRC_TypeDef Struct Reference - - - - - - - - - - - -
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    -Data Fields
    -
    CRC_TypeDef Struct Reference
    CMSIS_Device » Stm32f407xx » Peripheral_registers_structures
    -
    -
    - -

    CRC calculation unit. - More...

    - -

    #include <stm32f407xx_matlab.h>

    - - - - - - - - - - - - -

    -Data Fields

    __IO uint32_t DR
     
    __IO uint8_t IDR
     
    uint8_t RESERVED0
     
    uint16_t RESERVED1
     
    __IO uint32_t CR
     
    -

    Detailed Description

    -

    CRC calculation unit.

    -
    The documentation for this struct was generated from the following file:
      -
    • F:/Work/Projects/MATLAB/matlab_stm_emulate/MCU_STM32F4xx_Matlab/Drivers/CMSIS/stm32f407xx_matlab.h
      • -
    -
    - -
    -Generated by doxygen 1.10.0 -
    - - diff --git a/DOCS/html/struct_channels___sim.html b/DOCS/html/struct_channels___sim.html index accf020..65fd33f 100644 --- a/DOCS/html/struct_channels___sim.html +++ b/DOCS/html/struct_channels___sim.html @@ -14,6 +14,7 @@ + @@ -73,23 +74,14 @@ $(function() {
    Data Fields
    -
    Channels_Sim Struct Reference
    STM_SIMULATION » MAIN_SIMULATOR » TIM_SIMULATOR
    +
    Channels_Sim Struct Reference
    STM32 Simulation » STM32 Simulator » TIM Simulator
    +

    Структура Ð´Ð»Ñ Ð¼Ð¾Ð´ÐµÐ»Ð¸Ñ€Ð¾Ð²Ð°Ð½Ð¸Ñ ÐºÐ°Ð½Ð°Ð»Ð¾Ð² таймера + More...

    +

    #include <stm32f4xx_matlab_tim.h>

    -
    - + Collaboration diagram for Channels_Sim:
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    -
    - @@ -105,33 +97,35 @@ Data Fields - + - + - + - + - + - + - + - +

    Data Fields

    unsigned OC4REF:1
     Ð§ÐµÑ‚вертый канал
     
    GPIO_TypeDef * OC1_GPIOx
    GPIO_TypeDef * OC1_GPIOx
     ÐŸÐ¾Ñ€Ñ‚ первого канала
     
    uint32_t OC1_PIN_SHIFT
    uint32_t OC1_PIN_SHIFT
     ÐŸÐ¸Ð½ первого канала
     
    GPIO_TypeDef * OC2_GPIOx
    GPIO_TypeDef * OC2_GPIOx
     ÐŸÐ¾Ñ€Ñ‚ второго канала
     
    uint32_t OC2_PIN_SHIFT
    uint32_t OC2_PIN_SHIFT
     ÐŸÐ¸Ð½ второго канала
     
    GPIO_TypeDef * OC3_GPIOx
    GPIO_TypeDef * OC3_GPIOx
     ÐŸÐ¾Ñ€Ñ‚ третьего канала
     
    uint32_t OC3_PIN_SHIFT
    uint32_t OC3_PIN_SHIFT
     ÐŸÐ¸Ð½ третьего канала
     
    GPIO_TypeDef * OC4_GPIOx
    GPIO_TypeDef * OC4_GPIOx
     ÐŸÐ¾Ñ€Ñ‚ четвертого канала
     
    uint32_t OC4_PIN_SHIFT
    uint32_t OC4_PIN_SHIFT
     ÐŸÐ¸Ð½ четвертого канала
     

    Detailed Description

    Структура Ð´Ð»Ñ Ð¼Ð¾Ð´ÐµÐ»Ð¸Ñ€Ð¾Ð²Ð°Ð½Ð¸Ñ ÐºÐ°Ð½Ð°Ð»Ð¾Ð² таймера

    + +

    Definition at line 76 of file stm32f4xx_matlab_tim.h.

    Field Documentation

    ◆ OC1REF

    @@ -147,6 +141,8 @@ Data Fields

    Первый канал

    +

    Definition at line 79 of file stm32f4xx_matlab_tim.h.

    + @@ -163,6 +159,8 @@ Data Fields

    Второй канал

    +

    Definition at line 80 of file stm32f4xx_matlab_tim.h.

    + @@ -179,6 +177,8 @@ Data Fields

    Третьий канал

    +

    Definition at line 81 of file stm32f4xx_matlab_tim.h.

    + @@ -195,6 +195,8 @@ Data Fields

    Четвертый канал

    +

    Definition at line 82 of file stm32f4xx_matlab_tim.h.

    + @@ -204,13 +206,15 @@ Data Fields
    - +
    GPIO_TypeDef* OC1_GPIOxGPIO_TypeDef* OC1_GPIOx

    Порт первого канала

    +

    Definition at line 85 of file stm32f4xx_matlab_tim.h.

    +
    @@ -220,13 +224,15 @@ Data Fields
    - +
    uint32_t OC1_PIN_SHIFTuint32_t OC1_PIN_SHIFT

    Пин первого канала

    +

    Definition at line 86 of file stm32f4xx_matlab_tim.h.

    +
    @@ -236,13 +242,15 @@ Data Fields
    - +
    GPIO_TypeDef* OC2_GPIOxGPIO_TypeDef* OC2_GPIOx

    Порт второго канала

    +

    Definition at line 88 of file stm32f4xx_matlab_tim.h.

    +
    @@ -252,13 +260,15 @@ Data Fields
    - +
    uint32_t OC2_PIN_SHIFTuint32_t OC2_PIN_SHIFT

    Пин второго канала

    +

    Definition at line 89 of file stm32f4xx_matlab_tim.h.

    +
    @@ -268,13 +278,15 @@ Data Fields
    - +
    GPIO_TypeDef* OC3_GPIOxGPIO_TypeDef* OC3_GPIOx

    Порт третьего канала

    +

    Definition at line 91 of file stm32f4xx_matlab_tim.h.

    +
    @@ -284,13 +296,15 @@ Data Fields
    - +
    uint32_t OC3_PIN_SHIFTuint32_t OC3_PIN_SHIFT

    Пин третьего канала

    +

    Definition at line 92 of file stm32f4xx_matlab_tim.h.

    +
    @@ -300,13 +314,15 @@ Data Fields
    - +
    GPIO_TypeDef* OC4_GPIOxGPIO_TypeDef* OC4_GPIOx

    Порт четвертого канала

    +

    Definition at line 94 of file stm32f4xx_matlab_tim.h.

    +
    @@ -316,17 +332,19 @@ Data Fields
    - +
    uint32_t OC4_PIN_SHIFTuint32_t OC4_PIN_SHIFT

    Пин четвертого канала

    +

    Definition at line 95 of file stm32f4xx_matlab_tim.h.

    +
    The documentation for this struct was generated from the following file:
      -
    • F:/Work/Projects/MATLAB/matlab_stm_emulate/MCU_STM32F4xx_Matlab/Drivers/STM32F4xx_SIMULINK/stm32f4xx_matlab_tim.h
      • +
    • F:/Work/Projects/MATLAB/matlab_stm_emulate/MCU_STM32F4xx_Matlab/STM32F4xx_SIMULINK/stm32f4xx_matlab_tim.h
    diff --git a/DOCS/html/struct_channels___sim__coll__graph.map b/DOCS/html/struct_channels___sim__coll__graph.map deleted file mode 100644 index c57f2d9..0000000 --- a/DOCS/html/struct_channels___sim__coll__graph.map +++ /dev/null @@ -1,5 +0,0 @@ - - - - - diff --git a/DOCS/html/struct_channels___sim__coll__graph.md5 b/DOCS/html/struct_channels___sim__coll__graph.md5 deleted file mode 100644 index 9b49ee2..0000000 --- a/DOCS/html/struct_channels___sim__coll__graph.md5 +++ /dev/null @@ -1 +0,0 @@ -86a1655870cc95e79ab1b11a2ce76a52 \ No newline at end of file diff --git a/DOCS/html/struct_channels___sim__coll__graph.png b/DOCS/html/struct_channels___sim__coll__graph.png deleted file mode 100644 index 8bfe3088524da2c43d06940be61ad196465b4b3c..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 2136 zcmZWqc{Cg77Dqy&MGR@Et!b#Ow8YlNmK4v@2ujA*u~iy$)Jzv5r9^9M6txr+Mye&H z$W$vd5R8__mou>%EZmQ1BD6@>z{1Z0mTe9o>ftP9HSs&&%Af&!u3&7C< znBBB2IPj00DC_0>yv`a=Mhlz4e#BtZT2>VQdm>21&{|6=wp%JgK@K2JmK(kX zWWXut{VL$6|AEu9(MbpU2SQ7rr=}ZAxVdEzj#qW8ptSF)Pf`5RvP|z6l;aIG<3>kDx_hB_SHshlpXs8|De6xC7(;cezM86kf#gN%cQ3<8zp%UtAKsBlU7$#qdhJWYjvKy zuqf8^4(Vup>V(Cb$ClRo6}FEbCgKf#JzjL@#>aXK1=VFzaV%rg``JzrK`8bU#ZE;< z{s=5sh~nF}-eOT#D&{S;`5bDEaS3AVgvP;&j@j7MDz%+k?JYmPCrl6#!^VzG#a1=B zpz;%0!_OuJ8JnJ-v(7S~=C?R&h}zjss9aD!nl393{01oj;2SOj^sUetUGJWr8*gE0x?*_HHPXhGlkoZYIyI zgUHVtOV9r4B4bXaV(k(y9$eCcvjhCGjXz!Aw|Ot6%|_eQ9_sA+P7HiIm7-*yxIQ+1 zIZvGRTJ}vIdg^)T-vM9;lVCOQoc6&4$0qH<)8$@pSWMFuNx|_1;aD@Q)TvyDLY`Vo6m1RkI=`^Ya(H~8@IpBb9N3z&E(?&gM-j2AZVyIDo_|3XN2$+$STZY7Q+}|rnT*S&FRP4X9~$+$IyKL&cH+Ou^g{6~+jrI%dP4Vm zq-+-2`dTA@*QhR##2^fbONX7Oak)ZwL`>32*N_gsGLt342k$^NW`MJ{h1rF!GnWrj zKCUM^8f}{vadE4(7-X(~^MU|+*Of&fXj*Th_`caOTKMJ)tYLAj!jT5Ltgm|13+QXMu_Mw4eh78ZV$G#Sv?@J# z(G!UG6{kkH!QoY+t7vm(BVe>1^zNDaXaMtMpNXKnWDM3?WUD{#khbQ}#Ag-cA zf*iS*Ba*G4d*9#1!&dYVO?|5`YlP}IatJOCnf|_|IkhNy{cR>nqq#xJaJcUt%VY>p zmU#|7DB6aezd_w|rShOk=bstFNo%uMFnyd9a6ioM!8kbtnw1X z&zc@pY5SHo86NzzpTK&K0;TKp+GznOu+I!LO>f9FcnBaZ2|yyLFF9<7@a0{#+5OCm zgq5%4qb8&$EhE9TwlIGQe_=ZR)0Ovn^uJl{>I&B8t)joZAyJC?fe=e|1z~p8$6sED z(K&E%yS7qhLhKrCJu}@0+F-W4J~Kn0EurPx+S;HlZ(-kA8Bii#<{fJJ4ip9M{EgMl zWfx1&9{#^EaKzEfN?l0%^t3`WRk3qAWP2~%Rdn?x) zBGmn(pY*#G2ylN8gH@f1i-E>XhY9>F`MT|rvW_ITB9nhXstClhD9x5SKwo|Q`*^AM zz#dolcr<+dx^Ib;-#KH=Yu}eU - - - - - - -STM MATLAB Simulator: CoreDebug_Type Struct Reference - - - - - - - - - - - -
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    CoreDebug_Type Struct Reference
    Defines and Type Definitions » Status and Control Registers » Nested Vectored Interrupt Controller (NVIC) » System Control Block (SCB) » System Controls not in SCB (SCnSCB) » System Tick Timer (SysTick) » Instrumentation Trace Macrocell (ITM) » Data Watchpoint and Trace (DWT) » Trace Port Interface (TPI) » Floating Point Unit (FPU) » Core Debug Registers (CoreDebug)
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    __IOM uint32_t DHCSR
     
    __OM uint32_t DCRSR
     
    __IOM uint32_t DCRDR
     
    __IOM uint32_t DEMCR
     
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    Structure type to access the Core Debug Register (CoreDebug).

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    __IO uint32_t CR
     
    __IO uint32_t SWTRIGR
     
    __IO uint32_t DHR12R1
     
    __IO uint32_t DHR12L1
     
    __IO uint32_t DHR8R1
     
    __IO uint32_t DHR12R2
     
    __IO uint32_t DHR12L2
     
    __IO uint32_t DHR8R2
     
    __IO uint32_t DHR12RD
     
    __IO uint32_t DHR12LD
     
    __IO uint32_t DHR8RD
     
    __IO uint32_t DOR1
     
    __IO uint32_t DOR2
     
    __IO uint32_t SR
     
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    Digital to Analog Converter.

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    __IO uint32_t IDCODE
     
    __IO uint32_t CR
     
    __IO uint32_t APB1FZ
     
    __IO uint32_t APB2FZ
     
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    Debug MCU.

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    __IO uint32_t CR
     
    __IO uint32_t SR
     
    __IO uint32_t RISR
     
    __IO uint32_t IER
     
    __IO uint32_t MISR
     
    __IO uint32_t ICR
     
    __IO uint32_t ESCR
     
    __IO uint32_t ESUR
     
    __IO uint32_t CWSTRTR
     
    __IO uint32_t CWSIZER
     
    __IO uint32_t DR
     
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    DCMI.

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    __IO uint32_t CR
     
    __IO uint32_t NDTR
     
    __IO uint32_t PAR
     
    __IO uint32_t M0AR
     
    __IO uint32_t M1AR
     
    __IO uint32_t FCR
     
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    DMA Controller.

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    __IO uint32_t LISR
     
    __IO uint32_t HISR
     
    __IO uint32_t LIFCR
     
    __IO uint32_t HIFCR
     
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    Defines and Type Definitions » Status and Control Registers » Nested Vectored Interrupt Controller (NVIC) » System Control Block (SCB) » System Controls not in SCB (SCnSCB) » System Tick Timer (SysTick) » Instrumentation Trace Macrocell (ITM) » Data Watchpoint and Trace (DWT)
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    __IOM uint32_t CTRL
     
    __IOM uint32_t CYCCNT
     
    __IOM uint32_t CPICNT
     
    __IOM uint32_t EXCCNT
     
    __IOM uint32_t SLEEPCNT
     
    __IOM uint32_t LSUCNT
     
    __IOM uint32_t FOLDCNT
     
    __IM uint32_t PCSR
     
    __IOM uint32_t COMP0
     
    __IOM uint32_t MASK0
     
    __IOM uint32_t FUNCTION0
     
    uint32_t RESERVED0 [1U]
     
    __IOM uint32_t COMP1
     
    __IOM uint32_t MASK1
     
    __IOM uint32_t FUNCTION1
     
    uint32_t RESERVED1 [1U]
     
    __IOM uint32_t COMP2
     
    __IOM uint32_t MASK2
     
    __IOM uint32_t FUNCTION2
     
    uint32_t RESERVED2 [1U]
     
    __IOM uint32_t COMP3
     
    __IOM uint32_t MASK3
     
    __IOM uint32_t FUNCTION3
     
    -

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    Structure type to access the Data Watchpoint and Trace Register (DWT).

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      -
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    Ethernet MAC. - More...

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    __IO uint32_t MACCR
     
    __IO uint32_t MACFFR
     
    __IO uint32_t MACHTHR
     
    __IO uint32_t MACHTLR
     
    __IO uint32_t MACMIIAR
     
    __IO uint32_t MACMIIDR
     
    __IO uint32_t MACFCR
     
    __IO uint32_t MACVLANTR
     
    uint32_t RESERVED0 [2]
     
    __IO uint32_t MACRWUFFR
     
    __IO uint32_t MACPMTCSR
     
    uint32_t RESERVED1
     
    __IO uint32_t MACDBGR
     
    __IO uint32_t MACSR
     
    __IO uint32_t MACIMR
     
    __IO uint32_t MACA0HR
     
    __IO uint32_t MACA0LR
     
    __IO uint32_t MACA1HR
     
    __IO uint32_t MACA1LR
     
    __IO uint32_t MACA2HR
     
    __IO uint32_t MACA2LR
     
    __IO uint32_t MACA3HR
     
    __IO uint32_t MACA3LR
     
    uint32_t RESERVED2 [40]
     
    __IO uint32_t MMCCR
     
    __IO uint32_t MMCRIR
     
    __IO uint32_t MMCTIR
     
    __IO uint32_t MMCRIMR
     
    __IO uint32_t MMCTIMR
     
    uint32_t RESERVED3 [14]
     
    __IO uint32_t MMCTGFSCCR
     
    __IO uint32_t MMCTGFMSCCR
     
    uint32_t RESERVED4 [5]
     
    __IO uint32_t MMCTGFCR
     
    uint32_t RESERVED5 [10]
     
    __IO uint32_t MMCRFCECR
     
    __IO uint32_t MMCRFAECR
     
    uint32_t RESERVED6 [10]
     
    __IO uint32_t MMCRGUFCR
     
    uint32_t RESERVED7 [334]
     
    __IO uint32_t PTPTSCR
     
    __IO uint32_t PTPSSIR
     
    __IO uint32_t PTPTSHR
     
    __IO uint32_t PTPTSLR
     
    __IO uint32_t PTPTSHUR
     
    __IO uint32_t PTPTSLUR
     
    __IO uint32_t PTPTSAR
     
    __IO uint32_t PTPTTHR
     
    __IO uint32_t PTPTTLR
     
    __IO uint32_t RESERVED8
     
    __IO uint32_t PTPTSSR
     
    uint32_t RESERVED9 [565]
     
    __IO uint32_t DMABMR
     
    __IO uint32_t DMATPDR
     
    __IO uint32_t DMARPDR
     
    __IO uint32_t DMARDLAR
     
    __IO uint32_t DMATDLAR
     
    __IO uint32_t DMASR
     
    __IO uint32_t DMAOMR
     
    __IO uint32_t DMAIER
     
    __IO uint32_t DMAMFBOCR
     
    __IO uint32_t DMARSWTR
     
    uint32_t RESERVED10 [8]
     
    __IO uint32_t DMACHTDR
     
    __IO uint32_t DMACHRDR
     
    __IO uint32_t DMACHTBAR
     
    __IO uint32_t DMACHRBAR
     
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    Ethernet MAC.

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    __IO uint32_t IMR
     
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    __IO uint32_t RTSR
     
    __IO uint32_t FTSR
     
    __IO uint32_t SWIER
     
    __IO uint32_t PR
     
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    External Interrupt/Event Controller.

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    __IO uint32_t ACR
     
    __IO uint32_t KEYR
     
    __IO uint32_t OPTKEYR
     
    __IO uint32_t SR
     
    __IO uint32_t CR
     
    __IO uint32_t OPTCR
     
    __IO uint32_t OPTCR1
     
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    FLASH Registers.

    -
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    Defines and Type Definitions » Status and Control Registers » Nested Vectored Interrupt Controller (NVIC) » System Control Block (SCB) » System Controls not in SCB (SCnSCB) » System Tick Timer (SysTick) » Instrumentation Trace Macrocell (ITM) » Data Watchpoint and Trace (DWT) » Trace Port Interface (TPI) » Floating Point Unit (FPU)
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    uint32_t RESERVED0 [1U]
     
    __IOM uint32_t FPCCR
     
    __IOM uint32_t FPCAR
     
    __IOM uint32_t FPDSCR
     
    __IM uint32_t MVFR0
     
    __IM uint32_t MVFR1
     
    -

    Detailed Description

    -

    Structure type to access the Floating Point Unit (FPU).

    -
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      -
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    CMSIS_Device » Stm32f407xx » Peripheral_registers_structures
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    __IO uint32_t BTCR [8]
     
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    Flexible Static Memory Controller.

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    __IO uint32_t BWTR [7]
     
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    Flexible Static Memory Controller Bank1E.

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    __IO uint32_t PCR2
     
    __IO uint32_t SR2
     
    __IO uint32_t PMEM2
     
    __IO uint32_t PATT2
     
    uint32_t RESERVED0
     
    __IO uint32_t ECCR2
     
    uint32_t RESERVED1
     
    uint32_t RESERVED2
     
    __IO uint32_t PCR3
     
    __IO uint32_t SR3
     
    __IO uint32_t PMEM3
     
    __IO uint32_t PATT3
     
    uint32_t RESERVED3
     
    __IO uint32_t ECCR3
     
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    Flexible Static Memory Controller Bank2.

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    __IO uint32_t PCR4
     
    __IO uint32_t SR4
     
    __IO uint32_t PMEM4
     
    __IO uint32_t PATT4
     
    __IO uint32_t PIO4
     
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    Flexible Static Memory Controller Bank4.

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    __IO uint32_t MODER
     
    __IO uint32_t OTYPER
     
    __IO uint32_t OSPEEDR
     
    __IO uint32_t PUPDR
     
    __IO uint32_t IDR
     
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    __IO uint32_t BSRR
     
    __IO uint32_t LCKR
     
    __IO uint32_t AFR [2]
     
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    General Purpose I/O.

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    __IO uint32_t CR1
     
    __IO uint32_t CR2
     
    __IO uint32_t OAR1
     
    __IO uint32_t OAR2
     
    __IO uint32_t DR
     
    __IO uint32_t SR1
     
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    __IO uint32_t CCR
     
    __IO uint32_t TRISE
     
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    Inter-integrated Circuit Interface.

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    Defines and Type Definitions » Status and Control Registers » Nested Vectored Interrupt Controller (NVIC) » System Control Block (SCB) » System Controls not in SCB (SCnSCB) » System Tick Timer (SysTick) » Instrumentation Trace Macrocell (ITM)
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    union { 
     
       __OM uint8_t   u8 
     
       __OM uint16_t   u16 
     
       __OM uint32_t   u32 
     
    } PORT [32U] 
     
    uint32_t RESERVED0 [864U]
     
    __IOM uint32_t TER
     
    uint32_t RESERVED1 [15U]
     
    __IOM uint32_t TPR
     
    uint32_t RESERVED2 [15U]
     
    __IOM uint32_t TCR
     
    uint32_t RESERVED3 [29U]
     
    __OM uint32_t IWR
     
    __IM uint32_t IRR
     
    __IOM uint32_t IMCR
     
    uint32_t RESERVED4 [43U]
     
    __OM uint32_t LAR
     
    __IM uint32_t LSR
     
    uint32_t RESERVED5 [6U]
     
    __IM uint32_t PID4
     
    __IM uint32_t PID5
     
    __IM uint32_t PID6
     
    __IM uint32_t PID7
     
    __IM uint32_t PID0
     
    __IM uint32_t PID1
     
    __IM uint32_t PID2
     
    __IM uint32_t PID3
     
    __IM uint32_t CID0
     
    __IM uint32_t CID1
     
    __IM uint32_t CID2
     
    __IM uint32_t CID3
     
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    Structure type to access the Instrumentation Trace Macrocell Register (ITM).

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    __IO uint32_t KR
     
    __IO uint32_t PR
     
    __IO uint32_t RLR
     
    __IO uint32_t SR
     
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    Independent WATCHDOG.

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    Defines and Type Definitions » Status and Control Registers » Nested Vectored Interrupt Controller (NVIC)
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    __IOM uint32_t ISER [8U]
     
    uint32_t RESERVED0 [24U]
     
    __IOM uint32_t ICER [8U]
     
    uint32_t RSERVED1 [24U]
     
    __IOM uint32_t ISPR [8U]
     
    uint32_t RESERVED2 [24U]
     
    __IOM uint32_t ICPR [8U]
     
    uint32_t RESERVED3 [24U]
     
    __IOM uint32_t IABR [8U]
     
    uint32_t RESERVED4 [56U]
     
    __IOM uint8_t IP [240U]
     
    uint32_t RESERVED5 [644U]
     
    __OM uint32_t STIR
     
    -

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    -

    Structure type to access the Nested Vectored Interrupt Controller (NVIC).

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      -
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    __IO uint32_t CR
     
    __IO uint32_t CSR
     
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    Power Control.

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    __IO uint32_t CR
     
    __IO uint32_t PLLCFGR
     
    __IO uint32_t CFGR
     
    __IO uint32_t CIR
     
    __IO uint32_t AHB1RSTR
     
    __IO uint32_t AHB2RSTR
     
    __IO uint32_t AHB3RSTR
     
    uint32_t RESERVED0
     
    __IO uint32_t APB1RSTR
     
    __IO uint32_t APB2RSTR
     
    uint32_t RESERVED1 [2]
     
    __IO uint32_t AHB1ENR
     
    __IO uint32_t AHB2ENR
     
    __IO uint32_t AHB3ENR
     
    uint32_t RESERVED2
     
    __IO uint32_t APB1ENR
     
    __IO uint32_t APB2ENR
     
    uint32_t RESERVED3 [2]
     
    __IO uint32_t AHB1LPENR
     
    __IO uint32_t AHB2LPENR
     
    __IO uint32_t AHB3LPENR
     
    uint32_t RESERVED4
     
    __IO uint32_t APB1LPENR
     
    __IO uint32_t APB2LPENR
     
    uint32_t RESERVED5 [2]
     
    __IO uint32_t BDCR
     
    __IO uint32_t CSR
     
    uint32_t RESERVED6 [2]
     
    __IO uint32_t SSCGR
     
    __IO uint32_t PLLI2SCFGR
     
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    Reset and Clock Control.

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    __IO uint32_t CR
     
    __IO uint32_t SR
     
    __IO uint32_t DR
     
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    RNG.

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    CMSIS_Device » Stm32f407xx » Peripheral_registers_structures
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    Real-Time Clock. - More...

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    - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

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    __IO uint32_t TR
     
    __IO uint32_t DR
     
    __IO uint32_t CR
     
    __IO uint32_t ISR
     
    __IO uint32_t PRER
     
    __IO uint32_t WUTR
     
    __IO uint32_t CALIBR
     
    __IO uint32_t ALRMAR
     
    __IO uint32_t ALRMBR
     
    __IO uint32_t WPR
     
    __IO uint32_t SSR
     
    __IO uint32_t SHIFTR
     
    __IO uint32_t TSTR
     
    __IO uint32_t TSDR
     
    __IO uint32_t TSSSR
     
    __IO uint32_t CALR
     
    __IO uint32_t TAFCR
     
    __IO uint32_t ALRMASSR
     
    __IO uint32_t ALRMBSSR
     
    uint32_t RESERVED7
     
    __IO uint32_t BKP0R
     
    __IO uint32_t BKP1R
     
    __IO uint32_t BKP2R
     
    __IO uint32_t BKP3R
     
    __IO uint32_t BKP4R
     
    __IO uint32_t BKP5R
     
    __IO uint32_t BKP6R
     
    __IO uint32_t BKP7R
     
    __IO uint32_t BKP8R
     
    __IO uint32_t BKP9R
     
    __IO uint32_t BKP10R
     
    __IO uint32_t BKP11R
     
    __IO uint32_t BKP12R
     
    __IO uint32_t BKP13R
     
    __IO uint32_t BKP14R
     
    __IO uint32_t BKP15R
     
    __IO uint32_t BKP16R
     
    __IO uint32_t BKP17R
     
    __IO uint32_t BKP18R
     
    __IO uint32_t BKP19R
     
    -

    Detailed Description

    -

    Real-Time Clock.

    -
    The documentation for this struct was generated from the following file:
      -
    • F:/Work/Projects/MATLAB/matlab_stm_emulate/MCU_STM32F4xx_Matlab/Drivers/CMSIS/stm32f407xx_matlab.h
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    SCB_Type Struct Reference
    Defines and Type Definitions » Status and Control Registers » Nested Vectored Interrupt Controller (NVIC) » System Control Block (SCB)
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    Structure type to access the System Control Block (SCB). - More...

    - -

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    -Data Fields

    __IM uint32_t CPUID
     
    __IOM uint32_t ICSR
     
    __IOM uint32_t VTOR
     
    __IOM uint32_t AIRCR
     
    __IOM uint32_t SCR
     
    __IOM uint32_t CCR
     
    __IOM uint8_t SHP [12U]
     
    __IOM uint32_t SHCSR
     
    __IOM uint32_t CFSR
     
    __IOM uint32_t HFSR
     
    __IOM uint32_t DFSR
     
    __IOM uint32_t MMFAR
     
    __IOM uint32_t BFAR
     
    __IOM uint32_t AFSR
     
    __IM uint32_t PFR [2U]
     
    __IM uint32_t DFR
     
    __IM uint32_t ADR
     
    __IM uint32_t MMFR [4U]
     
    __IM uint32_t ISAR [5U]
     
    uint32_t RESERVED0 [5U]
     
    __IOM uint32_t CPACR
     
    -

    Detailed Description

    -

    Structure type to access the System Control Block (SCB).

    -
    The documentation for this struct was generated from the following file:
      -
    • F:/Work/Projects/MATLAB/matlab_stm_emulate/MCU_STM32F4xx_Matlab/Drivers/CMSIS/core_cm4_matlab.h
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    Defines and Type Definitions » Status and Control Registers » Nested Vectored Interrupt Controller (NVIC) » System Control Block (SCB) » System Controls not in SCB (SCnSCB)
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    Structure type to access the System Control and ID Register not in the SCB. - More...

    - -

    #include <core_cm4_matlab.h>

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    uint32_t RESERVED0 [1U]
     
    __IM uint32_t ICTR
     
    __IOM uint32_t ACTLR
     
    -

    Detailed Description

    -

    Structure type to access the System Control and ID Register not in the SCB.

    -
    The documentation for this struct was generated from the following file:
      -
    • F:/Work/Projects/MATLAB/matlab_stm_emulate/MCU_STM32F4xx_Matlab/Drivers/CMSIS/core_cm4_matlab.h
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    CMSIS_Device » Stm32f407xx » Peripheral_registers_structures
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    SD host Interface. - More...

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    -Data Fields

    __IO uint32_t POWER
     
    __IO uint32_t CLKCR
     
    __IO uint32_t ARG
     
    __IO uint32_t CMD
     
    __IO const uint32_t RESPCMD
     
    __IO const uint32_t RESP1
     
    __IO const uint32_t RESP2
     
    __IO const uint32_t RESP3
     
    __IO const uint32_t RESP4
     
    __IO uint32_t DTIMER
     
    __IO uint32_t DLEN
     
    __IO uint32_t DCTRL
     
    __IO const uint32_t DCOUNT
     
    __IO const uint32_t STA
     
    __IO uint32_t ICR
     
    __IO uint32_t MASK
     
    uint32_t RESERVED0 [2]
     
    __IO const uint32_t FIFOCNT
     
    uint32_t RESERVED1 [13]
     
    __IO uint32_t FIFO
     
    -

    Detailed Description

    -

    SD host Interface.

    -
    The documentation for this struct was generated from the following file:
      -
    • F:/Work/Projects/MATLAB/matlab_stm_emulate/MCU_STM32F4xx_Matlab/Drivers/CMSIS/stm32f407xx_matlab.h
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    -Generated by doxygen 1.10.0 -
    - - diff --git a/DOCS/html/struct_s_i_m_____m_c_u_handle_type_def.html b/DOCS/html/struct_s_i_m_____m_c_u_handle_type_def.html index e459b53..ba5a011 100644 --- a/DOCS/html/struct_s_i_m_____m_c_u_handle_type_def.html +++ b/DOCS/html/struct_s_i_m_____m_c_u_handle_type_def.html @@ -14,6 +14,7 @@ + @@ -73,7 +74,7 @@ $(function() {
    Data Fields
    -
    SIM__MCUHandleTypeDef Struct Reference
    +
    SIM__MCUHandleTypeDef Struct Reference
    MCU Wrapper
    @@ -87,7 +88,7 @@ Data Fields HANDLE hMCUThread  Ð¥ÐµÐ½Ð´Ð» Ð´Ð»Ñ Ð¿Ð¾Ñ‚Ð¾ÐºÐ° МК
      -uint32_t idMCUThread +uint32_t idMCUThread  id потока МК (unused)
      unsigned fMCU_Stop: 1 @@ -100,6 +101,8 @@ Data Fields

    Detailed Description

    MCU handle Structure definition.

    Note
    Prefixes: h - handle, s - settings, f - flag
    + +

    Definition at line 77 of file mcu_wrapper_conf.h.

    Field Documentation

    ◆ hMCUThread

    @@ -115,6 +118,8 @@ Data Fields

    Хендл Ð´Ð»Ñ Ð¿Ð¾Ñ‚Ð¾ÐºÐ° МК

    +

    Definition at line 79 of file mcu_wrapper_conf.h.

    +
    @@ -124,13 +129,15 @@ Data Fields
    - +
    uint32_t idMCUThreaduint32_t idMCUThread

    id потока МК (unused)

    +

    Definition at line 80 of file mcu_wrapper_conf.h.

    +
    @@ -147,6 +154,8 @@ Data Fields

    флаг Ð´Ð»Ñ Ð²Ñ‹Ñ…Ð¾Ð´Ð° из потока программы МК

    +

    Definition at line 82 of file mcu_wrapper_conf.h.

    + @@ -163,6 +172,8 @@ Data Fields

    sample time of simulation

    +

    Definition at line 83 of file mcu_wrapper_conf.h.

    +
    The documentation for this struct was generated from the following file:
      diff --git a/DOCS/html/struct_s_p_i___type_def.html b/DOCS/html/struct_s_p_i___type_def.html deleted file mode 100644 index 712de9a..0000000 --- a/DOCS/html/struct_s_p_i___type_def.html +++ /dev/null @@ -1,117 +0,0 @@ - - - - - - - -STM MATLAB Simulator: SPI_TypeDef Struct Reference - - - - - - - - - - - -
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      CMSIS_Device » Stm32f407xx » Peripheral_registers_structures
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      Serial Peripheral Interface. - More...

      - -

      #include <stm32f407xx_matlab.h>

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      __IO uint32_t CR1
       
      __IO uint32_t CR2
       
      __IO uint32_t SR
       
      __IO uint32_t DR
       
      __IO uint32_t CRCPR
       
      __IO uint32_t RXCRCR
       
      __IO uint32_t TXCRCR
       
      __IO uint32_t I2SCFGR
       
      __IO uint32_t I2SPR
       
      -

      Detailed Description

      -

      Serial Peripheral Interface.

      -
      The documentation for this struct was generated from the following file:
        -
      • F:/Work/Projects/MATLAB/matlab_stm_emulate/MCU_STM32F4xx_Matlab/Drivers/CMSIS/stm32f407xx_matlab.h
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      CMSIS_Device » Stm32f407xx » Peripheral_registers_structures
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      System configuration controller. - More...

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      __IO uint32_t MEMRMP
       
      __IO uint32_t PMC
       
      __IO uint32_t EXTICR [4]
       
      uint32_t RESERVED [2]
       
      __IO uint32_t CMPCR
       
      -

      Detailed Description

      -

      System configuration controller.

      -
      The documentation for this struct was generated from the following file:
        -
      • F:/Work/Projects/MATLAB/matlab_stm_emulate/MCU_STM32F4xx_Matlab/Drivers/CMSIS/stm32f407xx_matlab.h
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      - - diff --git a/DOCS/html/struct_slave_channels.html b/DOCS/html/struct_slave_channels.html index 1e66eb3..2d7b16f 100644 --- a/DOCS/html/struct_slave_channels.html +++ b/DOCS/html/struct_slave_channels.html @@ -14,6 +14,7 @@ + @@ -73,10 +74,13 @@ $(function() {
      Data Fields
      -
      SlaveChannels Struct Reference
      STM_SIMULATION » MAIN_SIMULATOR » TIM_SIMULATOR
      +
      SlaveChannels Struct Reference
      STM32 Simulation » STM32 Simulator » TIM Simulator
      +

      Структура Ð´Ð»Ñ ÑƒÐ¿Ñ€Ð°Ð²Ð»ÐµÐ½Ð¸Ñ Ð¡Ð»ÐµÐ¹Ð² Таймерами + More...

      +

      #include <stm32f4xx_matlab_tim.h>

      @@ -109,6 +113,8 @@ Data Fields

      Detailed Description

      Структура Ð´Ð»Ñ ÑƒÐ¿Ñ€Ð°Ð²Ð»ÐµÐ½Ð¸Ñ Ð¡Ð»ÐµÐ¹Ð² Таймерами

      + +

      Definition at line 60 of file stm32f4xx_matlab_tim.h.

      Field Documentation

      ◆ TIM1_TRGO

      @@ -124,6 +130,8 @@ Data Fields

      Синган Ñинхронизации таймера 1.

      +

      Definition at line 62 of file stm32f4xx_matlab_tim.h.

      +
      @@ -140,6 +148,8 @@ Data Fields

      Синган Ñинхронизации таймера 2.

      +

      Definition at line 63 of file stm32f4xx_matlab_tim.h.

      + @@ -156,6 +166,8 @@ Data Fields

      Синган Ñинхронизации таймера 3.

      +

      Definition at line 64 of file stm32f4xx_matlab_tim.h.

      + @@ -172,6 +184,8 @@ Data Fields

      Синган Ñинхронизации таймера 4.

      +

      Definition at line 65 of file stm32f4xx_matlab_tim.h.

      + @@ -188,6 +202,8 @@ Data Fields

      Синган Ñинхронизации таймера 5.

      +

      Definition at line 66 of file stm32f4xx_matlab_tim.h.

      + @@ -204,6 +220,8 @@ Data Fields

      Синган Ñинхронизации таймера 6.

      +

      Definition at line 67 of file stm32f4xx_matlab_tim.h.

      + @@ -220,6 +238,8 @@ Data Fields

      Синган Ñинхронизации таймера 7.

      +

      Definition at line 68 of file stm32f4xx_matlab_tim.h.

      + @@ -237,10 +257,12 @@ Data Fields

      Синган Ñинхронизации таймера 8

      +

      Definition at line 69 of file stm32f4xx_matlab_tim.h.

      +
      The documentation for this struct was generated from the following file:
        -
      • F:/Work/Projects/MATLAB/matlab_stm_emulate/MCU_STM32F4xx_Matlab/Drivers/STM32F4xx_SIMULINK/stm32f4xx_matlab_tim.h
        • +
      • F:/Work/Projects/MATLAB/matlab_stm_emulate/MCU_STM32F4xx_Matlab/STM32F4xx_SIMULINK/stm32f4xx_matlab_tim.h
      diff --git a/DOCS/html/struct_sys_tick___type.html b/DOCS/html/struct_sys_tick___type.html deleted file mode 100644 index 4711122..0000000 --- a/DOCS/html/struct_sys_tick___type.html +++ /dev/null @@ -1,107 +0,0 @@ - - - - - - - -STM MATLAB Simulator: SysTick_Type Struct Reference - - - - - - - - - - - -
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      SysTick_Type Struct Reference
      Defines and Type Definitions » Status and Control Registers » Nested Vectored Interrupt Controller (NVIC) » System Control Block (SCB) » System Controls not in SCB (SCnSCB) » System Tick Timer (SysTick)
      -
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      Structure type to access the System Timer (SysTick). - More...

      - -

      #include <core_cm4_matlab.h>

      - - - - - - - - - - -

      -Data Fields

      __IOM uint32_t CTRL
       
      __IOM uint32_t LOAD
       
      __IOM uint32_t VAL
       
      __IM uint32_t CALIB
       
      -

      Detailed Description

      -

      Structure type to access the System Timer (SysTick).

      -
      The documentation for this struct was generated from the following file:
        -
      • F:/Work/Projects/MATLAB/matlab_stm_emulate/MCU_STM32F4xx_Matlab/Drivers/CMSIS/core_cm4_matlab.h
        • -
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      -Generated by doxygen 1.10.0 -
      - - diff --git a/DOCS/html/struct_t_i_m___sim.html b/DOCS/html/struct_t_i_m___sim.html index e3bee8d..a512f08 100644 --- a/DOCS/html/struct_t_i_m___sim.html +++ b/DOCS/html/struct_t_i_m___sim.html @@ -14,6 +14,7 @@ + @@ -73,10 +74,13 @@ $(function() {
      Data Fields
      -
      TIM_Sim Struct Reference
      STM_SIMULATION » MAIN_SIMULATOR » TIM_SIMULATOR
      +
      TIM_Sim Struct Reference
      STM32 Simulation » STM32 Simulator » TIM Simulator
      +

      Структура Ð´Ð»Ñ Ð¼Ð¾Ð´ÐµÐ»Ð¸Ñ€Ð¾Ð²Ð°Ð½Ð¸Ñ Ñ‚Ð°Ð¹Ð¼ÐµÑ€Ð° + More...

      +

      #include <stm32f4xx_matlab_tim.h>

      + Collaboration diagram for TIM_Sim:
      @@ -85,24 +89,22 @@ $(function() { - + - + - + @@ -110,6 +112,8 @@ Data Fields

      Data Fields

      double tx_cnt
       Ð¡Ñ‡ÐµÑ‚чик таймера
       Ð¡Ñ‡ÐµÑ‚чик таймера (double, Ñ‚.к. кол-во тактов за шаг ÑимулÑции может быть дробным)
       
      double tx_step
       Ð¨Ð°Ð³ Ñчета за один шаг ÑимулÑции
       Ð¨Ð°Ð³ Ñчета за один шаг ÑимулÑции (double, Ñ‚.к. кол-во тактов за шаг ÑимулÑции может быть дробным)
       
      int RELOAD
       Ð‘уфер, еÑли PRELOAD = 1.
       Ð‘уфер Ð´Ð»Ñ Ð¿ÐµÑ€Ð¸Ð¾Ð´Ð° таймера (Ð´Ð»Ñ Ñ€ÐµÐ°Ð»Ð¸Ð·Ð°Ñ†Ð¸Ð¸ функции PRELOAD)
       
      struct Channels_Sim Channels
       Ð¡Ñ‚руктура Ð´Ð»Ñ ÑимулÑции каналов

      Detailed Description

      Структура Ð´Ð»Ñ Ð¼Ð¾Ð´ÐµÐ»Ð¸Ñ€Ð¾Ð²Ð°Ð½Ð¸Ñ Ñ‚Ð°Ð¹Ð¼ÐµÑ€Ð°

      + +

      Definition at line 102 of file stm32f4xx_matlab_tim.h.

      Field Documentation

      ◆ tx_cnt

      @@ -123,7 +127,9 @@ Data Fields
      -

      Счетчик таймера

      +

      Счетчик таймера (double, Ñ‚.к. кол-во тактов за шаг ÑимулÑции может быть дробным)

      + +

      Definition at line 104 of file stm32f4xx_matlab_tim.h.

      @@ -139,7 +145,9 @@ Data Fields
      -

      Шаг Ñчета за один шаг ÑимулÑции

      +

      Шаг Ñчета за один шаг ÑимулÑции (double, Ñ‚.к. кол-во тактов за шаг ÑимулÑции может быть дробным)

      + +

      Definition at line 105 of file stm32f4xx_matlab_tim.h.

      @@ -155,7 +163,9 @@ Data Fields
      -

      Буфер, еÑли PRELOAD = 1.

      +

      Буфер Ð´Ð»Ñ Ð¿ÐµÑ€Ð¸Ð¾Ð´Ð° таймера (Ð´Ð»Ñ Ñ€ÐµÐ°Ð»Ð¸Ð·Ð°Ñ†Ð¸Ð¸ функции PRELOAD)

      + +

      Definition at line 106 of file stm32f4xx_matlab_tim.h.

      @@ -173,10 +183,12 @@ Data Fields

      Структура Ð´Ð»Ñ ÑимулÑции каналов

      +

      Definition at line 107 of file stm32f4xx_matlab_tim.h.

      +
      The documentation for this struct was generated from the following file:
        -
      • F:/Work/Projects/MATLAB/matlab_stm_emulate/MCU_STM32F4xx_Matlab/Drivers/STM32F4xx_SIMULINK/stm32f4xx_matlab_tim.h
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      • F:/Work/Projects/MATLAB/matlab_stm_emulate/MCU_STM32F4xx_Matlab/STM32F4xx_SIMULINK/stm32f4xx_matlab_tim.h
      diff --git a/DOCS/html/struct_t_i_m___sim__coll__graph.map b/DOCS/html/struct_t_i_m___sim__coll__graph.map index 43ab85e..4a472b0 100644 --- a/DOCS/html/struct_t_i_m___sim__coll__graph.map +++ b/DOCS/html/struct_t_i_m___sim__coll__graph.map @@ -1,7 +1,5 @@ - - - - - + + + diff --git a/DOCS/html/struct_t_i_m___sim__coll__graph.md5 b/DOCS/html/struct_t_i_m___sim__coll__graph.md5 index 1dcc092..51f582d 100644 --- a/DOCS/html/struct_t_i_m___sim__coll__graph.md5 +++ b/DOCS/html/struct_t_i_m___sim__coll__graph.md5 @@ -1 +1 @@ -4c654ad6e7aca7d6178ce839f5e50108 \ No newline at end of file +591b789452c2012997410c0ee6727dad \ No newline at end of file diff --git a/DOCS/html/struct_t_i_m___sim__coll__graph.png b/DOCS/html/struct_t_i_m___sim__coll__graph.png index e7183194843adff7ff5e214fe33a54a3691524bb..8e2d0afdd443d66e188f8835118702ad425ad1ab 100644 GIT binary patch literal 1581 zcmZ8hdsNZ~6lOKe$21=cO-l<~7U(hsGOZc*^EH*4&(JcZBr%0ZAu%7B<}^}QTJlg_ z%A`nP;e$%lVrdU6d?W}BO|Ued8K-P@km=dZPG|Ri_w~m;=bn4dcZ>I<1I$e9Oh6!z zSx_JlwiHh<*%>3lB@ep<{%t83VuJ$!kbYTzZReJQKnCg{02Pr@HB;R~Sm*a`q4dqo zYE$EroTEoj$U=jHSU0s5(kZIQ0GpTERT_W9!;0pTv4VZ(yRZlTSl0H{+f9vp-A3(( z=msX<7Ok~Ko(}sQ!4y_hn?N(kXM5?LF|&LgfANN%7d~j?3@l9mvR&oL{#_`1XX|nJ z=0?Mc0D#aa5a=+_}XTK5ZbS_4JGy?+^o9G?OY+n z?G8hA{X4xIqdn5F0Y(EF>S&Ha+~5`98eNc4&@+%cDW=+1H_=stFj4t-ay<&CjNt_I}>q=~v?c~Y{6mVpL5JE0>_Z^rtmMS>s zFoD0}D)H%ITM(!|ZJAX!D>>QDADk2fo6{UD;(=lK_sO@9yCH>T_9k@?Sa(ukJbc6q z-izg>EGe89(i$3c%`@&)3^T;F;&C%IqOtyN6Uh&rj2MOs>o3(8PP)WX3^hqfU?a`> zGm3w4*U@;3x=6tuSDBrCNz3UZ?%kKz`~i(NccvJ&lIh)Aaa$__UfR+l@)0%OLqdl^ z4edj@KNjUA)^ekXQXMX~%r(NLw;=INyoQ&!HL5S6_3dc@ki6?ibw!efQ*vk9qUjUr zd$V2dD?73kybUx@BGUBmcWPC>N|o^Py4foPqOL))UHU zM$bqm3b4UG8rLhbYEx0Ai?uWFah#@+E~$;OToAzt=U>)Ow& z=XPf)@HAzs8x-M=jeZquq{vbpB1KyL5ogR8?k zH#2P1W)Ou*I3uaIdaf0W1Q$}C%V_0klq!3v{zP%iABU5MGGFIA9=>&CX|Gk^Xf~{+ zHyZtiH8_ztKDda`ERKhD!k5{>3>3)Am+lUag$MN+z3aTy||8M?MwQoT8+J#mPu@G7RUS71aL&SGt%^ zIC;{|$2NqJ^--JVq&m(mVT$`IE)z31y&mLBrj57JEg`uQ(+&tkvpR}LAD}&7TWu)O zHN1m9`99dQrZh}eG4Cg>X*Lgp-B6S8cJmie5zi((BO8^pVZ_+goTHUy=P(bP$!sX% z@*p33y;OSX!%yqGTfS;qb5)WemM*`bW!Y~Hb*N-!)Xc1aI`DwuW6~iR)_M&tKl@8g zFXa*Rk_E*-Eg(>`B&-oLY1rw{vb_?Vdar3S$jYA3wLOZ^ObZCAXm6vXqg9vJ2SojXNAt)i0{i7vdv0m9W1Ao=PEo(TH9>5WHL|bD;UKC- z!DlkNhgjKF7W|T%?548dn1_@Wjji4VPbQP|7{q5!pECH$ou70+6hBlel`*1HZArH6 zsxFe(1sm!t-#|kPNstIvpb&KmoC5nd;5*hQ2Yb{;1@85nc0Rtn;UUT5v551e@#h6 z$l+BXDgxe~moKH?#3{}~o)_w$_xh6aQ&~josLf%uL@l*AT0RkT)12sgY_osMGkMcJ@x{h73Ae~dJW?~{kCH~NyRVO{&EWUPi5_HB{fM6k4W;WeivAy%@BHT)!eU>FZFshsk&WPg{@{E zR0|@jMzQtI+mn%g{iI}L>kH)&XMd>x4gNHTK%w%x4MbjA4zv3npk#KtdP>>03JK!c zXT}U`%FD@Z@e3bMaJ_^*-B-uj+Eo}D8Y+F&Ufb(>-D7wca|0z;6qXlS!;~%~)du($ zGNteQ7}WVp-KIy07?X8BkUlUS?~L1G<0gN;lrgEO74tC=Ra8O>8=Zw6R`-Z22oE~q z-H`>*&@7A0Pjbcthtd|D-zO;aQ=75?i;T*5X0XFB8N^tNb`ef=K}DU8z?`?&OSJN%*I%|c+g{EQC|kgN%!h6jf&7!N zPw}Gir9wwl>mWG}3W^fOR_X(_D2lGz_<$SDRg{RYOvYENkSE?pwCZLqRX#8r`xd_T zu^Ct>?k-G>Ak5bWr5Wt#9eGwK69dw!atO4gtj zhs#5P$d-7YpuB~hArCL;%}!_JW0y1aXAbZ2W}qpEvE^tThX}Vr6&e@aeX&2(P?PALMj@{}fn|GU_MYNm6&VXdvl*k4EUm-hz;j7J1)= zl}v^D7uF4jV|)23#7*92eQ7&;6>V)rH`#m(-I(axTN$B89~9eJ!H2rv=(Dlc5@*SnTT>&K}fFGmgU># zq6SNRixVn!1N{SrWn?0s%|AcvBUeNh1gdq}BpfX#aG#Y_Z5FbBQ5{QFgEylBe(zN` zmvq%pya(v*eUZJ{CSx*#qons;^JxMP6$(~eK#QW%^uVgv1)Nw~puHU}+?0bGl&HFQ znt(-&aitq7T%1&P6J>B5c*bXQZ5e0#IzS&OZv!~{loNr_Dt+uBpZY`sJp8rJ-~%KX z=r=2nF=O<=+A$-&(+l&6OwE`KmxBu+1A}|GEYQnUYv-+UfMTAmSFejPxMuJ!iZ(yC zh3t7`rhYGPw~Wh{7hxw^31)DaA)kWdHcZng7{zw@L|1Ca`Ab=-z2JB9uDu3g-iue!Wb#AEobY_UX>se=z9*yWRh;K=j0VP)Q&=|%dL1VZ8f49 zG?;!~VUIG@{K~23lR47&%Pe?p^7N1UN%kwT){^;=n%pW$L$TAfCp6RbX@eYYSL&=z zVavJZps7r4p{T}+*MPS}w$*C|Mo!b|_xX|G;JAVLBO|?4n&l8DU{(0dpngXdh(<9r z*XW}#A- zk)d?w!XW04zI~xiemUxFJo7;CrUUeN30Ypo0L5SJGZ>MZv^FQbdh<0|;<|yjqO#FB zSS#fSQL|N|mmj&Xt`(|(z9Cw)|D^IJra~XRJIj2uTFUY^@<0<7J^C8WDb}LGZvsM> z0=8uAXs%oyoUN4NcsC2!;k-Y8Y!nkKKJmc$kq5y}GtdT|^%5b}?gtxB7kGWHhrcYw z2I=)+3I-mO3w_9U`B?q^too#>4|aA|qyS~ppBpAgnj*?eNhEbVrc8knRkO$Fwf9-# z4eZ9B`#R=n-MCvte7#c@LoK@%3I5sRTW{4JHESUe?MF4XziV#)#@JLHlW@+Fmw3JV zZqZhr2WS?$#_J<%C9yGRev>lyxbyA3FVN4y%mxkEKy^E)AC~wq)9#6H znP93`@I8<2@Y^p)S~;{1MH3%<<)lkjIk3jrNaQAjGIqPqS!C=~pL(>w>xlWnZ<#5t zWv%DRZyodD67yJWdeAVK9c4K%)EMg5h#@l3cW$i;@i3JBTja2sNzo(TR#6)R#Mk1RnyNDcP!=MebTc&NvOD;vEfz8XPjMV@c@j8v6++iv{M1Kv z4+HVfvnmd;Q|>%wV0?7R!3o((-l?5Xllzw6#(uZvFY<3GzstSFlq`5SX8jz9hM^=A z^UP{P-63lt#gAWTpMjPFT! z9TE~~Eo<*Xm-R@S#ARvA3cBFWf92y)e&$zE$2yiJfy$ - - - - - - -STM MATLAB Simulator: TIM_TypeDef Struct Reference - - - - - - - - - - - -
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      TIM_TypeDef Struct Reference
      CMSIS_Device » Stm32f407xx » Peripheral_registers_structures
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      TIM. - More...

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      #include <stm32f407xx_matlab.h>

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      __IO uint32_t CR1
       
      __IO uint32_t CR2
       
      __IO uint32_t SMCR
       
      __IO uint32_t DIER
       
      __IO uint32_t SR
       
      __IO uint32_t EGR
       
      __IO uint32_t CCMR1
       
      __IO uint32_t CCMR2
       
      __IO uint32_t CCER
       
      __IO uint32_t CNT
       
      __IO uint32_t PSC
       
      __IO uint32_t ARR
       
      __IO uint32_t RCR
       
      __IO uint32_t CCR1
       
      __IO uint32_t CCR2
       
      __IO uint32_t CCR3
       
      __IO uint32_t CCR4
       
      __IO uint32_t BDTR
       
      __IO uint32_t DCR
       
      __IO uint32_t DMAR
       
      __IO uint32_t OR
       
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      TIM.

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      TPI_Type Struct Reference
      Defines and Type Definitions » Status and Control Registers » Nested Vectored Interrupt Controller (NVIC) » System Control Block (SCB) » System Controls not in SCB (SCnSCB) » System Tick Timer (SysTick) » Instrumentation Trace Macrocell (ITM) » Data Watchpoint and Trace (DWT) » Trace Port Interface (TPI)
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      Structure type to access the Trace Port Interface Register (TPI). - More...

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      #include <core_cm4_matlab.h>

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      __IM uint32_t SSPSR
       
      __IOM uint32_t CSPSR
       
      uint32_t RESERVED0 [2U]
       
      __IOM uint32_t ACPR
       
      uint32_t RESERVED1 [55U]
       
      __IOM uint32_t SPPR
       
      uint32_t RESERVED2 [131U]
       
      __IM uint32_t FFSR
       
      __IOM uint32_t FFCR
       
      __IM uint32_t FSCR
       
      uint32_t RESERVED3 [759U]
       
      __IM uint32_t TRIGGER
       
      __IM uint32_t FIFO0
       
      __IM uint32_t ITATBCTR2
       
      uint32_t RESERVED4 [1U]
       
      __IM uint32_t ITATBCTR0
       
      __IM uint32_t FIFO1
       
      __IOM uint32_t ITCTRL
       
      uint32_t RESERVED5 [39U]
       
      __IOM uint32_t CLAIMSET
       
      __IOM uint32_t CLAIMCLR
       
      uint32_t RESERVED7 [8U]
       
      __IM uint32_t DEVID
       
      __IM uint32_t DEVTYPE
       
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      Detailed Description

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      Structure type to access the Trace Port Interface Register (TPI).

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      The documentation for this struct was generated from the following file:
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      • F:/Work/Projects/MATLAB/matlab_stm_emulate/MCU_STM32F4xx_Matlab/Drivers/CMSIS/core_cm4_matlab.h
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      __IO uint32_t SR
       
      __IO uint32_t DR
       
      __IO uint32_t BRR
       
      __IO uint32_t CR1
       
      __IO uint32_t CR2
       
      __IO uint32_t CR3
       
      __IO uint32_t GTPR
       
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      Universal Synchronous Asynchronous Receiver Transmitter.

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      __IO uint32_t DCFG
       
      __IO uint32_t DCTL
       
      __IO uint32_t DSTS
       
      uint32_t Reserved0C
       
      __IO uint32_t DIEPMSK
       
      __IO uint32_t DOEPMSK
       
      __IO uint32_t DAINT
       
      __IO uint32_t DAINTMSK
       
      uint32_t Reserved20
       
      uint32_t Reserved9
       
      __IO uint32_t DVBUSDIS
       
      __IO uint32_t DVBUSPULSE
       
      __IO uint32_t DTHRCTL
       
      __IO uint32_t DIEPEMPMSK
       
      __IO uint32_t DEACHINT
       
      __IO uint32_t DEACHMSK
       
      uint32_t Reserved40
       
      __IO uint32_t DINEP1MSK
       
      uint32_t Reserved44 [15]
       
      __IO uint32_t DOUTEP1MSK
       
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      USB_OTG_device_Registers.

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      __IO uint32_t GOTGCTL
       
      __IO uint32_t GOTGINT
       
      __IO uint32_t GAHBCFG
       
      __IO uint32_t GUSBCFG
       
      __IO uint32_t GRSTCTL
       
      __IO uint32_t GINTSTS
       
      __IO uint32_t GINTMSK
       
      __IO uint32_t GRXSTSR
       
      __IO uint32_t GRXSTSP
       
      __IO uint32_t GRXFSIZ
       
      __IO uint32_t DIEPTXF0_HNPTXFSIZ
       
      __IO uint32_t HNPTXSTS
       
      uint32_t Reserved30 [2]
       
      __IO uint32_t GCCFG
       
      __IO uint32_t CID
       
      uint32_t Reserved40 [48]
       
      __IO uint32_t HPTXFSIZ
       
      __IO uint32_t DIEPTXF [0x0F]
       
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      USB_OTG_Core_Registers.

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      __IO uint32_t HCCHAR
       
      __IO uint32_t HCSPLT
       
      __IO uint32_t HCINT
       
      __IO uint32_t HCINTMSK
       
      __IO uint32_t HCTSIZ
       
      __IO uint32_t HCDMA
       
      uint32_t Reserved [2]
       
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      USB_OTG_Host_Channel_Specific_Registers.

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      USB_OTG_HostTypeDef Struct Reference
      CMSIS_Device » Stm32f407xx » Peripheral_registers_structures
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      USB_OTG_Host_Mode_Register_Structures. - More...

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      #include <stm32f407xx_matlab.h>

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      __IO uint32_t HCFG
       
      __IO uint32_t HFIR
       
      __IO uint32_t HFNUM
       
      uint32_t Reserved40C
       
      __IO uint32_t HPTXSTS
       
      __IO uint32_t HAINT
       
      __IO uint32_t HAINTMSK
       
      -

      Detailed Description

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      USB_OTG_Host_Mode_Register_Structures.

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      The documentation for this struct was generated from the following file:
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      • F:/Work/Projects/MATLAB/matlab_stm_emulate/MCU_STM32F4xx_Matlab/Drivers/CMSIS/stm32f407xx_matlab.h
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      #include <stm32f407xx_matlab.h>

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      __IO uint32_t DIEPCTL
       
      uint32_t Reserved04
       
      __IO uint32_t DIEPINT
       
      uint32_t Reserved0C
       
      __IO uint32_t DIEPTSIZ
       
      __IO uint32_t DIEPDMA
       
      __IO uint32_t DTXFSTS
       
      uint32_t Reserved18
       
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      Detailed Description

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      USB_OTG_IN_Endpoint-Specific_Register.

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      __IO uint32_t DOEPCTL
       
      uint32_t Reserved04
       
      __IO uint32_t DOEPINT
       
      uint32_t Reserved0C
       
      __IO uint32_t DOEPTSIZ
       
      __IO uint32_t DOEPDMA
       
      uint32_t Reserved18 [2]
       
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      Detailed Description

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      USB_OTG_OUT_Endpoint-Specific_Registers.

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      __IO uint32_t CR
       
      __IO uint32_t CFR
       
      __IO uint32_t SR
       
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      Window WATCHDOG.

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      CMSIS Cortex-M4 Device System Source File for STM32F4xx devices.
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      void SystemInit (void)
       
      void SystemCoreClockUpdate (void)
       
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      -Variables

      uint32_t SystemCoreClock
       
      const uint8_t AHBPrescTable [16]
       
      const uint8_t APBPrescTable [8]
       
      -

      Detailed Description

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      CMSIS Cortex-M4 Device System Source File for STM32F4xx devices.
      -

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      Author
      MCD Application Team
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      Attention
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      Copyright (c) 2017 STMicroelectronics. All rights reserved.

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      This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

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      - - diff --git a/DOCS/html/system__stm32f4xx_8h__dep__incl.map b/DOCS/html/system__stm32f4xx_8h__dep__incl.map deleted file mode 100644 index 128b064..0000000 --- a/DOCS/html/system__stm32f4xx_8h__dep__incl.map +++ /dev/null @@ -1,7 +0,0 @@ - - - - - - - diff --git a/DOCS/html/system__stm32f4xx_8h__dep__incl.md5 b/DOCS/html/system__stm32f4xx_8h__dep__incl.md5 deleted file mode 100644 index 4ffc1c0..0000000 --- a/DOCS/html/system__stm32f4xx_8h__dep__incl.md5 +++ /dev/null @@ -1 +0,0 @@ -755c954ae1d0bf074a7963e89813df6e \ No newline at end of file diff --git a/DOCS/html/system__stm32f4xx_8h__dep__incl.png b/DOCS/html/system__stm32f4xx_8h__dep__incl.png deleted file mode 100644 index fcd56fa72997f3ee64e6caf215af8cb9bf15f25e..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 6624 zcmc(kcQjnv+s6k%5=4p4=v{^g5sVgu=q=?kT67tsjS{0v1krn$(Gn%%Y8i$hNRbFe zPcRH2jM0Xhj1v8odw;*X-g|$)xBT<2_nfu%KI@#b&f4dB_I{qv^WBLSW(G{>dCvm? z04BqmdRC`B1puIeoTWRx0t~jEJ#FcnjSchwCqK{9j;bsGfG5XL@A|C=C~}c$y?c*k z&zgFO`&S|EbBWx&FXL`Lx|D!^jbXXa;KYhzq84*rFj-fbyq0&h#7UFNxZAHI!O0B? zeESl8?}pR-x5s*Cg=K{dY`8^|sMw(n#qJ6eS48ST#f$cuc5{uB5~Vh{LtA^B`HA`6 z-IcbypTqg%5at}fIYw-MHpp|^d+N>u@TMgZLL9=#&4Ql9sOz#WB2V3HI$JOGuNArh z8ib1_pI&Raa+iY=Q&o(3VW0po>EB+P_}o8Pod*CcQ+G2)vkJKbk^u@dPG=H$0HWGB z0C!n`mGn6e505vLi8_0i3Wk}G;9v>05}AiCJ6!JQ_;28( z9nV7WU{SqvSChAyfN)+m!~xb}YYtZljdw5`cT}@}f_1m-i)w9*ms|P8PB<@EihMz$ zw?uS(GX>b;u8VehRrTAwTsY)pX#Pwff}$G*k(T?d(#vynu**` z5mtzE-%+H zA7#LtCK8TLOZij`2ZReP^~NMnakb(B+*HnVug{J>u{l7NiM5?47@#!*VnEV-0aT*4 zZ>}gR)aFAJ$8?dsoFJvni#>w}Z^U|Dg}NFkEFf3ES?=Sk!AGen((l(7+8xSTzYHG{ zewnpv8xE=_^FzvmvU8V@z>WZW#O`NEAL+LUI>~ zXAkDs4mIl2Dr^ZRMOGc)huwcZpJQFP5CZn|*JGzE7|lclb1rgq{`4Jr%d1y<)khmM*=y?h6}43bp* z7=(&>qA#2_fY%?gkuzD@d@qQdDN+}`=@YQ&tY2fCuAl$YjHd?HrF__qTwoz+d@MWa zUsEri(Aj;|H>P7n%H1>C028thognWG+-p% z9iP9-FDg?H2r5i8#o|RV3pu%Yh1ONS&HPATD-PI(2qjuBl`{ZaUUrC;@Pa)`@_dbO zdh>CWnRH9%A5t#6@Ey1$ud<`mCe}%EScfsr>WG~R`BxzGdSyxXl5yXCHYFN~fTG(; zBdi`%eq@5J(}&7#btKYyb!ksachB$6Kv)~Ta7ACps|AF`OK`q6GE5Yi;4v0lzjwS6 zWweIBE+$V+W^E&e+%LHkgxZT^ceWOV4^+l-y47CG%9abL_zgVYW?fm={I|9u`? zWAU2Rre_JD9KxZ_-Unsx@=-q+Rfu6kY+pq26Bv=)T;Q%>$$@4LdDkw+W+?MEQ;8Qh zUTs9q*zj36bKe`5WdN-VM8lcoFrlt=?iZ(j^;Rvtcc+qFF`gh-PQ&J(<1=KEkyK;~ ztRH(HTukgcOB9XZ2_SpfxZ_fT3gTVr?tZ}L%0!LFxL))Lh8kg3a?0n;m|ItLar2GYI`=dMk{lr+ivHJZhslq&ePD^{9jIy0!~L5~U%_wLjFn(Tyjt_uZ-dl~o3`lBmW z5NSpoYFZQ9+fk24{qOXG&LUpWUf$@tS_L2atyk)rbEVoZDZpBu49VR+;L=8XR6M-r zqlEs_xR1m77$=F=GOIENNe<+ii&Fp_G8gb_bx6f=m98r!=q4Z5}3>i!Vwk&4`&wZeL zZ<&!VT3>P8Twng?do=jn_ZgWA;Y5W~0UJ1qKP9@F%O_)Km#G!_Jp8vrSTo>T+anl& zy^#C6@CDee7;8jof~U7J{8Ehc0@)W73x466%Kz(=m3Jcn@&LIdq zHIl?IA}%6gyPOH%`u@4*!Vp2~L4*EYn&Y!CA_iJrYDWdk#bsakomnjCot67G9y$1J z6emTLK$@!RFDRUS{%{jVx3|>3@wMor{N!nz9KGC^R{w{ZlqGn-?XuH?ldE#V0jq{F zJNuQ4XZ?BdV|n|wXAl4dKG&`)*`{ZZGHAa}3zxxN#Ppf17$hv&_qg_;dYWs+fMG;8 zaaywzJ3Mr>jqX1QQe=GoFaythz_1mjw^hApnkr{MHMY6acy^20S@|(!xi6E_65KSb z*z(&4>kY~2ZMMew94;Of`)Ka7bcAoWZ>$rA4zanJVyQ6h-L#vwKhWBavNESqV#Ql$g`+kK0f?Wscjv zLH&bP{`GeXqY5({F3oGm4yxX18;SY*5hV~sIXa6&|=~EoQ;^X79d0Ab& zl-3(!oA>!et&{#oc0tbj?6kf6QFJ3rX#hwXoXB>xRhCRkH|_(~V;pL$R8g;V<*Qu6 zR~WhA15dM0{9KsrM;lvpSwy z>xk0q=D7r8O;C;b8@oVUR%tH_rpkU)t#>n!w*q1pZR<3vgH0-O!eQxCw~;NkD+LN5 z3{{^#e|n(c2Q!?>>lbZGO_%jOQ`^b@19z*-fsq4V_XaCFEiIfq%LmR~w7H+O*g4e( zA2gg2$u)D9q_1P@>2@c01GEdPXVzUrn@Rl9{45kb?e0>#Kj)!!!oQ~%v|`-9(95Ly zccFLh)e#09%jPSJ=HxA!iwXFikPaRHuCfDc<11`n*_zd~D(2>z6v*0Ee?#T2gA8{p zq-tu?i;*s*U}Nl)nnRux|8FcwLj$mmt2X`D|%HpL($PXJ{FxkU4i$LZA+0p^c_<0WK=5`Gt9gr}RJ-^HjIPzLOT&^zuRtn{izZ%NB-!@U zzOhl^y~YPvW8^EahG*Ay317Y59>Z;YG$oWyPo{HzJ#Y%{KjUk@^Hp&3xtR8fOr)dK zm&wN|w|MJ7&E=Xii<)cQnAb~F9!EAl1Dy5|DVqc|>{5XaPLsg2NnjEh-Ky}iYBK4; zE9A;#jcG={zLA7Tb~46boLiAaYtfAZqKc(6_l!DAVi(+6^Hmpvg@Ne_HGyI7Pb}2E zy`wNuCu$L(MtkU0dBMS3Vz+uG{a>KonVU`fO`}eIQUs+i(hLUv6N3^>nOo%=9a96D zgx$M#mdSZ&Ir$(Eeak7N3-oD)T(T+QAx|-Lz+przP(qBcS9!pq5Jet^l@eYVktnqW zZl-$+-_@=hId=ybiVP=bzq-n3`?2`;poz)vt?{uYtd_DYV_ zE@ZV^kGm{UA`lH}uW8JPp~OBn9Q(=#`j~TWX*r&=Dl3O! z@V$Yz*)g2WNd}qkD<-$u4q8d#Jrzk>YzM|Aaos*E`+B{N<>5YUywix&(J2Cih5~(* z8%*z~sv%sb)mRjl&!4HGKMit!tB?1nC-HcjwM$e0#==Cr>Ml?O(Rn+v6u8lw7wHnZ zS$}-52{@NU7&E=N?rlPQz3vrJPOIrzl$L6l<6*x%=tN^mppm!a93;VtCMx~6+bi+MRKz>-dA;Bn6-#yq$r6&<2%=ooM0-3VL3Vj zfB9Nsu_I@Io*qL+J8>C1qD-Z6id2`v5MGOZq&>oEuyx1_+>67-0`@F0(PwYCeDu}WwjZ$V7 z^i>pO1IB{o#x7(+mfZp_B$a%K&QI~*hany(2$;?;E@x;(A|pG}Zj^GdpcOW1?|d=* zqIUp%^BF^D2ht5EGKG9s%v*_P7c1CGR>z#j^PQn2En@CF_s_XSiZS+h%Weeug%8F&OmkXF|36UAU(}QEujXyV|ETyylc~;M0zYM7W}P|C|424~(D2Tq!j2CQ z51CE~agzg8RaN_(RDf<&NeTUs!TZClG4mQ88i16fggdU_zhbwt#QZ$s#W3^96&){T zlGTLmRIW_@X@#DhO`edvE$KC#haxR$xJ>(|+!Lj|ytIfCCGj7`07pG1@6kfHslwY5 zY!=7}ZkzE?XxhuNL-^mMmKMW6`uyyF)mrF9LiocQ!aF%ejA-1Gr?u*J8IoL zng1ZrR_@{-XE#;W1kM+WN^LNnZoF0~Kj%_fknf@Y)fO6z;v7q9o+bn=Zbj{rp#8%* zJ_1Rqn;-6BfFHS1k{k3SB^ga(+8B+vid;A!FbKtuB;7KQ!{*kQzW`c$i97O@2Y+5- z5-9KgNU&9@sH^;t6azJ0?X(jp3wmT1D(bmi@!F$uf57ab0*M#Z{<4ToXQiXj#jv;n zb91An7ED5wgPd2yf&=EJ0NWK>J~3KksEON2i7neD6~Ix9+QR=_tK|ITckIg)|oCGYkl- z)3o@zg!ns@uR7;;m*?tf?M+yPF7;)ttFJXSKD(`yFIH%T5Nv^67c@!1VeJh|fdqS} zQo(oKmpCREAqURH3jMCpjEtLiJPeZqq#kF!VsO%#Z_01ZFB42m6Vpq zAE#-kOry6NTASW21s{z|h2Uqe&>>w&3S{EO_aasH3hU9=cK7@Q+`V0*k}Zp3tx1JP z1n~*zlt}YX=T=<&%4hpFUtX`HO8M)GP9hUF&D=o$N~VcHmkT%xE{eC0Sv8V$!br^G zwb5_=DWq8NwqAjpjJd*V@Y0rxYA!1eHE>$YCl^Qv;ZRo3v|%=IIkmUtPu!RabOca_ zcBT45){aU*`a`@bd=C08S?s;z1Nrf+;1woW>JI-@oI zJRuY_cz4vZO!XJQ7o)n5hWLX)iy4$T5@ zYGoO7#42)(I7np$TAa*I^0!{C-S1C6de%>!AJu7KvvwnW^hO=~v94p1R1oM!TJVD0 z%g>XRGRuVKPqAEi4o5ehMJ-w|G^MLQ7~K2hU(J+B_iJNSC5jj9y!W|@p~a^n$&vuQ zN-iC7L~N(APY#}oW=&l+Z%dURB2tTeW5_fLA!lM~3;)E#KPq)~X$YPP!vRjC`a^~{ zasKx5czd{cyY8ul9aJV=o7a^^R?;H`hq)zCtoIUC;pbifghVSV0`g?(i8ya^mUty3UtJk(%8PA>&F-=LZ{mi9vEXG~Hr+{9& z3+20}qH9~Ma3}ywdqCw&z+Fpdlu3O)hxL - - - - - - -STM MATLAB Simulator: F:/Work/Projects/MATLAB/matlab_stm_emulate/MCU_STM32F4xx_Matlab/Drivers/CMSIS/system_stm32f4xx.h Source File - - - - - - - - - - - -
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      1
      -
      30#ifndef __SYSTEM_STM32F4XX_H
      -
      31#define __SYSTEM_STM32F4XX_H
      -
      32
      -
      33#ifdef __cplusplus
      -
      34 extern "C" {
      -
      35#endif
      -
      36
      -
      49 /* This variable is updated in three ways:
      -
      50 1) by calling CMSIS function SystemCoreClockUpdate()
      -
      51 2) by calling HAL API function HAL_RCC_GetSysClockFreq()
      -
      52 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
      -
      53 Note: If you use this function to configure the system clock; then there
      -
      54 is no need to call the 2 first functions listed above, since SystemCoreClock
      -
      55 variable is updated automatically.
      -
      56 */
      -
      57extern uint32_t SystemCoreClock;
      -
      59extern const uint8_t AHBPrescTable[16];
      -
      60extern const uint8_t APBPrescTable[8];
      -
      86extern void SystemInit(void);
      -
      87extern void SystemCoreClockUpdate(void);
      -
      92#ifdef __cplusplus
      -
      93}
      -
      94#endif
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      95
      -
      96#endif /*__SYSTEM_STM32F4XX_H */
      -
      97
      -
      SystemInit
      void SystemInit(void)
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      - - diff --git a/DOCS/html/topics.html b/DOCS/html/topics.html index 9beda92..705b7f1 100644 --- a/DOCS/html/topics.html +++ b/DOCS/html/topics.html @@ -14,6 +14,7 @@ + @@ -75,62 +76,19 @@ $(function() {
      Here is a list of all topics with brief descriptions:
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      [detail level 123]
       CMSIS Global Defines
       ▼Defines and Type DefinitionsType definitions and defines for Cortex-M processor based devices
       ▼Status and Control RegistersCore Register type definitions
       ▼Nested Vectored Interrupt Controller (NVIC)Type definitions for the NVIC Registers
       ▼System Control Block (SCB)Type definitions for the System Control Block Registers
       ▼System Controls not in SCB (SCnSCB)Type definitions for the System Control and ID Register not in the SCB
       ▼System Tick Timer (SysTick)Type definitions for the System Timer Registers
       ▼Instrumentation Trace Macrocell (ITM)Type definitions for the Instrumentation Trace Macrocell (ITM)
       ▼Data Watchpoint and Trace (DWT)Type definitions for the Data Watchpoint and Trace (DWT)
       ▼Trace Port Interface (TPI)Type definitions for the Trace Port Interface (TPI)
       ▼Floating Point Unit (FPU)Type definitions for the Floating Point Unit (FPU)
       ▼Core Debug Registers (CoreDebug)Type definitions for the Core Debug Registers
       ▼Core register bit field macrosMacros for use with bit field definitions (xxx_Pos, xxx_Msk)
       ▼Core DefinitionsDefinitions for base addresses, unions, and structures
       ▼Functions and Instructions Reference
       ▼NVIC FunctionsFunctions that manage interrupts and exceptions via the NVIC
       ▼FPU FunctionsFunction that provides FPU type
       ▼SysTick FunctionsFunctions that configure the System
       ITM FunctionsFunctions that access the ITM debug interface
       ▼NVIC FunctionsFunctions that manage interrupts and exceptions via the NVIC
       ▼FPU FunctionsFunction that provides FPU type
       ▼SysTick FunctionsFunctions that configure the System
       ITM FunctionsFunctions that access the ITM debug interface
       ▼MCU_WRAPPERStuff for running MCU app in MATLAB
       WRAPPER_CONFConfigurations for wrapper to simulating MCU
       ▼STM_SIMULATIONStuff for simulating STM32 in MATLAB
       ▼MAIN_SIMULATORStuff for configuring, initializing and deinitializing simulator
       SIMULATOR_CONFConfigurations for simulator to simulating MCU
       GPIO_SIMULATORSimulator for GPIO
       RCC_SIMULATORSimulator for RCC and Clocks
       TIM_SIMULATORSimulator for TIM
       PERIPH_VARS_FOR_DEBUGVarables of peripheral registers for debug watches
       ▼CMSIS_Device
       ▼Stm32f407xx
       Configuration_section_for_CMSIS
       Peripheral_interrupt_number_definition
       Peripheral_registers_structures
       ▼Peripheral_memory_map
       Peripheral_declaration
       ▼Exported_constants
       Hardware_Constant_Definition
       Peripheral_Registers_Bits_Definition
       Exported_macros
       ▼CMSIS
       ▼Stm32f4xx
       Library_configuration_section
       Device_Included
       Exported_types
       Exported_macro
       ▼Stm32f4xx_system
       STM32F4xx_System_IncludesDefine to prevent recursive inclusion
       STM32F4xx_System_Exported_types
       STM32F4xx_System_Exported_Constants
       STM32F4xx_System_Exported_Macros
       STM32F4xx_System_Exported_Functions
      + + + + + + + + + + + +
       ▼MCU WrapperÐ’ÑÑкое Ð´Ð»Ñ Ð¾Ð±Ð¾Ð»Ð¾Ñ‡ÐºÐ¸ МК
       S-Function funtionsДефайны и функции блока S-Function
       Wrapper ConfigurationПараметры конфигурации Ð´Ð»Ñ Ð¾Ð±Ð¾Ð»Ð¾Ñ‡ÐºÐ¸ МК
       ▼Core DefinitionsDefinitions for base addresses, unions, and structures
       Peripheral Memory Map
       ▼STM32 SimulationÐ’ÑÑкое Ð´Ð»Ñ ÑимулÑции STM32
       ▼STM32 SimulatorÐ’ÑÑкое Ð´Ð»Ñ ÑимулÑтора STM32
       Simulator ConfigurationПараметры конфигурации Ð´Ð»Ñ ÑимулÑтора МК
       GPIO SimulatorСимулÑтор Ð´Ð»Ñ Ð¿Ð¾Ñ€Ñ‚Ð¾Ð² ввода-вывода
       RCC SimulatorСимулÑтор Ð´Ð»Ñ RCC и чаÑов таймера
       TIM SimulatorСимулÑтор Ð´Ð»Ñ Ñ‚Ð°Ð¹Ð¼ÐµÑ€Ð¾Ð²
       Periphs Variables for DebuggingПеременные Ð´Ð»Ñ Ð´Ð¾Ñтупа к периферии в дебаге
      diff --git a/DOCS/html/union_a_p_s_r___type.html b/DOCS/html/union_a_p_s_r___type.html deleted file mode 100644 index aa2d511..0000000 --- a/DOCS/html/union_a_p_s_r___type.html +++ /dev/null @@ -1,121 +0,0 @@ - - - - - - - -STM MATLAB Simulator: APSR_Type Union Reference - - - - - - - - - - - -
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      - - diff --git a/MCU_STM32F4xx_Matlab/Drivers/CMSIS/arm_defines.h b/MCU_STM32F4xx_Matlab/Drivers/CMSIS/arm_defines.h index 7f03a94..008e633 100644 --- a/MCU_STM32F4xx_Matlab/Drivers/CMSIS/arm_defines.h +++ b/MCU_STM32F4xx_Matlab/Drivers/CMSIS/arm_defines.h @@ -1,13 +1,23 @@ +/** +************************************************************************** +* @file arm_defines.h +* @brief Çàãîëîâî÷íûé ôàéë ïîðòèðóþùèé ARM äåôàéíû. +************************************************************************** +@details +Äàííûé ôàéë ïåðåîïðåäåëÿåò ARM äåôàéíû òàê, ÷òîáû îíè êîìïèëèðîâàëèñü +MSVC. Äåôàéíû ïðåäñòàâëÿþò ñîáîé èëè çàãëóøêó èëè çàìåíåíû âûðàæåíèåì +ñ àíàëîãè÷íûì ARM êîìïèëÿòîðó ôóíêöèîíàëîì. +**************************************************************************/ + #define __disable_irq() +/* CMSIS compiler specific defines */ + + #ifndef __ASM #define __ASM __asm #endif -#ifndef __IO - #define __IO volatile -#endif - #ifndef __inline #define __inline inline #endif @@ -31,11 +41,13 @@ #define __USED __attribute__((used)) #endif - #ifndef __WEAK #define __WEAK __declspec(selectany) -// #define __weak __WEAK #endif +#ifndef __weak +#define __weak +#endif + #ifndef __PACKED #define __PACKED __attribute__((packed)) @@ -76,21 +88,8 @@ #ifndef __RESTRICT #define __RESTRICT __restrict #endif - -#ifndef __weak - #define __weak -#endif -//#define __ASM() -//#define __DSB() -//#define __ISB() -//#define __NOP() -//#define __WFI() -//#define __SEV() -//#define __WFE() -//#define __DMB() - - +/* ########################## Core Instruction Access ######################### */ /** \brief No Operation \details No Operation does nothing. This instruction can be used for code alignment purposes. diff --git a/MCU_STM32F4xx_Matlab/Drivers/CMSIS/core_cm4_matlab.h b/MCU_STM32F4xx_Matlab/Drivers/CMSIS/core_cm4_matlab.h index dd327cf..5a8ed1e 100644 --- a/MCU_STM32F4xx_Matlab/Drivers/CMSIS/core_cm4_matlab.h +++ b/MCU_STM32F4xx_Matlab/Drivers/CMSIS/core_cm4_matlab.h @@ -1,10 +1,18 @@ -/************************************************************************ +/** +************************************************************************** +* @file core_cm4_matlab.h +* @brief Заголовочный файл Ñдра Core CM4 Ð´Ð»Ñ MATLAB. +************************************************************************** +@details Данный файл ÑвлÑетÑÑ ÐºÐ¾Ð¿Ð¸ÐµÐ¹ core_cm4.h, только первые ~160 Ñтрок, которые определÑÑŽÑ‚ компилÑтор ÐРМ, удалены. + ÐœÐТЛÐБ компилирует через код через комплилÑтор MSVC Ð´Ð»Ñ Ð±Ð»Ð¾ÐºÐ° S-Function -Также добавлена Ñтруктура Ð¸Ð¼Ð¸Ñ‚Ð¸Ñ€ÑƒÑŽÑ‰Ð°Ñ Ð¿Ð°Ð¼ÑÑ‚ÑŒ Ñдра (~1360) + +Также добавлена инклюд Ñ Ð¸Ð¼Ð¸Ñ‚Ð¸Ñ€Ð°Ñ†Ð¸ÐµÐ¹ памÑти Ñдра (~10) **************************************************************************/ #ifndef __CMSIS_GENERIC +#include "stm32f407xx_matlab_memory.h" /* IO definitions (access restrictions to peripheral registers) */ /** \defgroup CMSIS_glob_defs CMSIS Global Defines @@ -1344,52 +1352,7 @@ typedef struct /*@} end of group CMSIS_core_bitfield */ -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ -/* Memory mapping of Core Hardware */ -#define SCS_BASE_SHIFT (0x0000E000UL) /*!< System Control Space Base Address */ -#define ITM_BASE_SHIFT (0x00000000UL) /*!< ITM Base Address */ -#define DWT_BASE_SHIFT (0x00001000UL) /*!< DWT Base Address */ -#define TPI_BASE_SHIFT (0x00040000UL) /*!< TPI Base Address */ -#define CoreDebug_BASE_SHIFT (0x0000EDF0UL) /*!< Core Debug Base Address */ - -typedef struct _cortex_memory -{ - uint8_t CORTEX_PERIPH_BASE[0xE0100000 - 0xE0000000]; -}MCU_CortexMemoryTypeDef; -extern MCU_CortexMemoryTypeDef MCU_CORTEX_MEM; - -#define SCS_BASE (MCU_CORTEX_MEM.CORTEX_PERIPH_BASE) + SCS_BASE_SHIFT /*!< System Control Space Base Address */ -#define ITM_BASE (MCU_CORTEX_MEM.CORTEX_PERIPH_BASE) + SCS_BASE_SHIFT /*!< ITM Base Address */ -#define DWT_BASE (MCU_CORTEX_MEM.CORTEX_PERIPH_BASE) + SCS_BASE_SHIFT /*!< DWT Base Address */ -#define TPI_BASE (MCU_CORTEX_MEM.CORTEX_PERIPH_BASE) + SCS_BASE_SHIFT /*!< TPI Base Address */ -#define CoreDebug_BASE (MCU_CORTEX_MEM.CORTEX_PERIPH_BASE) + SCS_BASE_SHIFT /*!< Core Debug Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ -#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ -#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ -#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) -#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ -#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ -#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ - -/*@} */ /*@} */ diff --git a/MCU_STM32F4xx_Matlab/Drivers/CMSIS/stm32f407xx_matlab.h b/MCU_STM32F4xx_Matlab/Drivers/CMSIS/stm32f407xx_matlab.h index f38a428..9130124 100644 --- a/MCU_STM32F4xx_Matlab/Drivers/CMSIS/stm32f407xx_matlab.h +++ b/MCU_STM32F4xx_Matlab/Drivers/CMSIS/stm32f407xx_matlab.h @@ -1,37 +1,20 @@ -/************************************************************************ +/** +************************************************************************** +* @file stm32f4xx_matlab.h +* @brief Заголовочный файл Ð´Ð»Ñ Ñ€Ð°Ð±Ð¾Ñ‚Ñ‹ Ñ STM32F4xx в MATLAB. +************************************************************************** +@details Данный файл ÑвлÑетÑÑ ÐºÐ¾Ð¿Ð¸ÐµÐ¹ stm32f407xx.h Ñ Ð½ÐµÐºÐ¾Ñ‚Ð¾Ñ€Ñ‹Ð¼Ð¸ изменениÑми: - добавлен кейловÑкий stdint.h (через "", вмеÑто <>) (~170) - добавлен cmsis_armcc_matlab.h Ñ Ð´ÐµÑ„Ð°Ð¹Ð½Ð°Ð¼Ð¸ из оригинального cmsis_armcc.h (~170) - добавлен core_cm4.h Ñ Ð´ÐµÑ„Ð°Ð¹Ð½Ð°Ð¼Ð¸ из оригинального core_cm4.h (~170) - добавлена Ñтруктура Ð¸Ð¼Ð¸Ñ‚Ð¸Ñ€ÑƒÑŽÑ‰Ð°Ñ Ð¿Ð°Ð¼ÑÑ‚ÑŒ МК (Ð´Ð»Ñ Ñ€Ð°Ð±Ð¾Ñ‚Ñ‹ дефайнов адреÑов региÑтров) (~950) (надо допилить) + Ðеобходимо допилить поддержку вÑех дефайнов, которые объÑвлÑÑŽÑ‚ÑÑ Ð² arm_acle.h, arm_compat.h, cmsis_armclang.h, cmsis_compiler.h, cmsis_version.h, core_cm4.h, mpu_armv7.h, stddef **************************************************************************/ -/** - ****************************************************************************** - * @file stm32f407xx.h - * @author MCD Application Team - * @brief CMSIS STM32F407xx Device Peripheral Access Layer Header File. - * - * This file contains: - * - Data structures and the address mapping for all peripherals - * - peripherals registers declarations and bits definition - * - Macros to access peripheral’s registers hardware - * - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ /** @addtogroup CMSIS_Device * @{ @@ -912,84 +895,9 @@ typedef struct * @} */ -/** @addtogroup Peripheral_memory_map - * @{ - */ -#define FLASH_BASE_SHIFT 0x08000000UL /*!< FLASH(up to 1 MB) base address in the alias region */ -#define FLASH_END_SHIFT 0x080FFFFFUL /*!< FLASH end address */ -#define CCMDATARAM_BASE_SHIFT 0x10000000UL /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region */ -#define CCMDATARAM_END_SHIFT 0x1000FFFFUL /*!< CCM data RAM end address */ -#define FLASH_OTP_BASE_SHIFT 0x1FFF7800UL /*!< Base address of : (up to 528 Bytes) embedded FLASH OTP Area */ -#define FLASH_OTP_END_SHIFT 0x1FFF7A0FUL /*!< End address of : (up to 528 Bytes) embedded FLASH OTP Area */ -#define SRAM1_BASE_SHIFT 0x20000000UL /*!< SRAM1(112 KB) base address in the alias region */ -#define SRAM2_BASE_SHIFT 0x2001C000UL /*!< SRAM2(16 KB) base address in the alias region */ -#define SRAM1_BB_BASE_SHIFT 0x22000000UL /*!< SRAM1(112 KB) base address in the bit-band region */ -#define SRAM2_BB_BASE_SHIFT 0x22380000UL /*!< SRAM2(16 KB) base address in the bit-band region */ -#define PERIPH_BASE_SHIFT 0x40000000UL /*!< Peripheral base address in the alias region */ -#define BKPSRAM_BASE_SHIFT 0x40024000UL /*!< Backup SRAM(4 KB) base address in the alias region */ -#define PERIPH_BB_BASE_SHIFT 0x42000000UL /*!< Peripheral base address in the bit-band region */ -#define BKPSRAM_BB_BASE_SHIFT 0x42480000UL /*!< Backup SRAM(4 KB) base address in the bit-band region */ -#define FSMC_R_BASE_SHIFT 0xA0000000UL /*!< FSMC registers base address */ - -#define MCU_MEM_END 0xA0000FFFUL /*!< CCM data RAM end address */ - -#define CCMDATARAM_SIZE 0x10000UL /* (64 KB) */ -#define SRAM1_SIZE 0x1C000UL /* (112 KB) */ -#define SRAM2_SIZE 0x4000UL /* (16 KB) */ -#define BKPSRAM_SIZE 0x1000UL /* (4 KB) */ - -#define FLASH_SIZE (CCMDATARAM_BASE_SHIFT - FLASH_BASE_SHIFT) -//#define CCMDATARAM_SIZE (FLASH_OTP_BASE_SHIFT - CCMDATARAM_BASE_SHIFT) -#define FLASH_OTP_SIZE (SRAM1_BASE_SHIFT - FLASH_OTP_BASE_SHIFT) -//#define SRAM1_SIZE (SRAM2_BASE_SHIFT - SRAM1_BASE_SHIFT) -//#define SRAM2_SIZE (SRAM1_BB_BASE_SHIFT - SRAM2_BASE_SHIFT) -#define SRAM1_BB_SIZE (SRAM2_BB_BASE_SHIFT - SRAM1_BB_BASE_SHIFT) -#define SRAM2_BB_SIZE (PERIPH_BASE_SHIFT - SRAM2_BB_BASE_SHIFT) -#define PERIPH_SIZE (BKPSRAM_BASE_SHIFT - PERIPH_BASE_SHIFT) -//#define BKPSRAM_SIZE (PERIPH_BB_BASE_SHIFT - BKPSRAM_BASE_SHIFT) -#define PERIPH_BB_SIZE (BKPSRAM_BB_BASE_SHIFT - PERIPH_BB_BASE_SHIFT) -//#define BKPSRAM_BB_SIZE (FSMC_R_BASE_SHIFT - BKPSRAM_BB_BASE_SHIFT) -#define FSMC_R_SIZE (MCU_MEM_END - FSMC_R_BASE_SHIFT) - - -typedef struct _memory -{ - //uint8_t RESERVED[FLASH_BASE_SHIFT]; - - uint8_t FLASH_BASE[FLASH_SIZE]; - uint8_t CCMDATARAM_BASE[CCMDATARAM_SIZE]; - uint8_t FLASH_OTP_BASE[FLASH_OTP_SIZE]; - uint8_t SRAM1_BASE[SRAM1_SIZE]; - uint8_t SRAM2_BASE[SRAM2_SIZE]; - uint8_t SRAM1_BB_BASE[SRAM1_SIZE]; - uint8_t SRAM2_BB_BASE[SRAM2_SIZE]; - uint8_t PERIPH_BASE[PERIPH_SIZE]; - uint8_t BKPSRAM_BASE[BKPSRAM_SIZE]; - uint8_t PERIPH_BB_BASE[PERIPH_BB_SIZE]; - uint8_t BKPSRAM_BB_BASE[BKPSRAM_SIZE]; - uint8_t FSMC_R_BASE[FSMC_R_SIZE]; -}MCU_MemoryTypeDef; -extern MCU_MemoryTypeDef MCU_MEM; -DBGMCU_TypeDef DEBUG_MCU; - /** @addtogroup Peripheral_memory_map * @{ */ -#define FLASH_BASE (MCU_MEM.CCMDATARAM_BASE) /*!< FLASH(up to 1 MB) base address in the alias region */ -#define CCMDATARAM_BASE (MCU_MEM.CCMDATARAM_BASE) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region */ -#define SRAM1_BASE (MCU_MEM.SRAM1_BASE) /*!< SRAM1(112 KB) base address in the alias region */ -#define SRAM2_BASE (MCU_MEM.SRAM2_BASE) /*!< SRAM2(16 KB) base address in the alias region */ -#define PERIPH_BASE (MCU_MEM.PERIPH_BASE) /*!< Peripheral base address in the alias region */ -#define BKPSRAM_BASE (MCU_MEM.BKPSRAM_BASE) /*!< Backup SRAM(4 KB) base address in the alias region */ -#define FSMC_R_BASE (MCU_MEM.FSMC_R_BASE) /*!< FSMC registers base address */ -#define SRAM1_BB_BASE (MCU_MEM.SRAM1_BB_BASE) /*!< SRAM1(112 KB) base address in the bit-band region */ -#define SRAM2_BB_BASE (MCU_MEM.SRAM2_BB_BASE) /*!< SRAM2(16 KB) base address in the bit-band region */ -#define PERIPH_BB_BASE (MCU_MEM.PERIPH_BB_BASE) /*!< Peripheral base address in the bit-band region */ -#define BKPSRAM_BB_BASE (MCU_MEM.BKPSRAM_BB_BASE) /*!< Backup SRAM(4 KB) base address in the bit-band region */ -#define FLASH_END (MCU_MEM.FLASH_END) /*!< FLASH end address */ -#define FLASH_OTP_BASE (MCU_MEM.FLASH_OTP_BASE) /*!< Base address of : (up to 528 Bytes) embedded FLASH OTP Area */ -#define FLASH_OTP_END (MCU_MEM.FLASH_OTP_END) /*!< End address of : (up to 528 Bytes) embedded FLASH OTP Area */ -#define CCMDATARAM_END (MCU_MEM.CCMDATARAM_END) /*!< CCM data RAM end address */ /* Legacy defines */ #define SRAM_BASE SRAM1_BASE @@ -1097,8 +1005,6 @@ DBGMCU_TypeDef DEBUG_MCU; #define FSMC_Bank4_R_BASE (FSMC_R_BASE + 0x00A0UL) -/*!< Debug MCU registers base address */ -#define DBGMCU_BASE (&DEBUG_MCU) /*!< USB registers base address */ #define USB_OTG_HS_PERIPH_BASE 0x40040000UL #define USB_OTG_FS_PERIPH_BASE 0x50000000UL diff --git a/MCU_STM32F4xx_Matlab/Drivers/CMSIS/stm32f407xx_matlab_memory.h b/MCU_STM32F4xx_Matlab/Drivers/CMSIS/stm32f407xx_matlab_memory.h new file mode 100644 index 0000000..d76a1f9 --- /dev/null +++ b/MCU_STM32F4xx_Matlab/Drivers/CMSIS/stm32f407xx_matlab_memory.h @@ -0,0 +1,146 @@ +/** +************************************************************************** +* @file stm32f407xx_matlab_memory.h +* @brief Заголовочный файл Ð´Ð»Ñ Ð¾Ð¿Ñ€ÐµÐ´ÐµÐ»ÐµÐ½Ð¸Ñ Ð¿Ð°Ð¼Ñти МК STM32F4xx. +************************************************************************** +@details +Ð’ данном файле переопределÑÑŽÑ‚ÑÑ Ð´ÐµÑ„Ð°Ð¹Ð½Ñ‹ памÑти STM32 таким образом, чтобы +к ним можно было обратитьÑÑ Ð² MATLAB. + +Конкретно, ÑоздаетÑÑ Ñтруктуруа Ð¸Ð¼Ð¸Ñ‚Ð¸Ñ€ÑƒÑŽÑ‰Ð°Ñ Ð¿Ð°Ð¼ÑÑ‚ÑŒ, и далее дефайны определÑÑŽÑ‚ÑÑ +так, чтобы обращатьÑÑ Ðº Ñтой Ñтруктуре, а не по абÑолютному адреÑу. +**************************************************************************/ +/** + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + + /* Memory mapping of Core Hardware */ +#define SCS_BASE_SHIFT (0x0000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE_SHIFT (0x00000000UL) /*!< ITM Base Address */ +#define DWT_BASE_SHIFT (0x00001000UL) /*!< DWT Base Address */ +#define TPI_BASE_SHIFT (0x00040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE_SHIFT (0x0000EDF0UL) /*!< Core Debug Base Address */ + +typedef struct _cortex_memory +{ + uint8_t CORTEX_PERIPH_BASE[0xE0100000 - 0xE0000000]; +}MCU_CortexMemoryTypeDef; +extern MCU_CortexMemoryTypeDef MCU_CORTEX_MEM; + +#define SCS_BASE (MCU_CORTEX_MEM.CORTEX_PERIPH_BASE) + SCS_BASE_SHIFT /*!< System Control Space Base Address */ +#define ITM_BASE (MCU_CORTEX_MEM.CORTEX_PERIPH_BASE) + SCS_BASE_SHIFT /*!< ITM Base Address */ +#define DWT_BASE (MCU_CORTEX_MEM.CORTEX_PERIPH_BASE) + SCS_BASE_SHIFT /*!< DWT Base Address */ +#define TPI_BASE (MCU_CORTEX_MEM.CORTEX_PERIPH_BASE) + SCS_BASE_SHIFT /*!< TPI Base Address */ +#define CoreDebug_BASE (MCU_CORTEX_MEM.CORTEX_PERIPH_BASE) + SCS_BASE_SHIFT /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ +#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ +#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +/** + * @} + */ + + + +/** @ingroup CMSIS_core_base + * @addtogroup Peripheral_memory_map Peripheral Memory Map + * @{ + */ + +#define FLASH_BASE_SHIFT 0x08000000UL /*!< FLASH(up to 1 MB) base address in the alias region */ +#define FLASH_END_SHIFT 0x080FFFFFUL /*!< FLASH end address */ +#define CCMDATARAM_BASE_SHIFT 0x10000000UL /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region */ +#define CCMDATARAM_END_SHIFT 0x1000FFFFUL /*!< CCM data RAM end address */ +#define FLASH_OTP_BASE_SHIFT 0x1FFF7800UL /*!< Base address of : (up to 528 Bytes) embedded FLASH OTP Area */ +#define FLASH_OTP_END_SHIFT 0x1FFF7A0FUL /*!< End address of : (up to 528 Bytes) embedded FLASH OTP Area */ +#define SRAM1_BASE_SHIFT 0x20000000UL /*!< SRAM1(112 KB) base address in the alias region */ +#define SRAM2_BASE_SHIFT 0x2001C000UL /*!< SRAM2(16 KB) base address in the alias region */ +#define SRAM1_BB_BASE_SHIFT 0x22000000UL /*!< SRAM1(112 KB) base address in the bit-band region */ +#define SRAM2_BB_BASE_SHIFT 0x22380000UL /*!< SRAM2(16 KB) base address in the bit-band region */ +#define PERIPH_BASE_SHIFT 0x40000000UL /*!< Peripheral base address in the alias region */ +#define BKPSRAM_BASE_SHIFT 0x40024000UL /*!< Backup SRAM(4 KB) base address in the alias region */ +#define PERIPH_BB_BASE_SHIFT 0x42000000UL /*!< Peripheral base address in the bit-band region */ +#define BKPSRAM_BB_BASE_SHIFT 0x42480000UL /*!< Backup SRAM(4 KB) base address in the bit-band region */ +#define FSMC_R_BASE_SHIFT 0xA0000000UL /*!< FSMC registers base address */ + +#define MCU_MEM_END 0xA0000FFFUL /*!< CCM data RAM end address */ + +#define CCMDATARAM_SIZE 0x10000UL /* (64 KB) */ +#define SRAM1_SIZE 0x1C000UL /* (112 KB) */ +#define SRAM2_SIZE 0x4000UL /* (16 KB) */ +#define BKPSRAM_SIZE 0x1000UL /* (4 KB) */ + +#define FLASH_SIZE (CCMDATARAM_BASE_SHIFT - FLASH_BASE_SHIFT) + //#define CCMDATARAM_SIZE (FLASH_OTP_BASE_SHIFT - CCMDATARAM_BASE_SHIFT) +#define FLASH_OTP_SIZE (SRAM1_BASE_SHIFT - FLASH_OTP_BASE_SHIFT) +//#define SRAM1_SIZE (SRAM2_BASE_SHIFT - SRAM1_BASE_SHIFT) +//#define SRAM2_SIZE (SRAM1_BB_BASE_SHIFT - SRAM2_BASE_SHIFT) +#define SRAM1_BB_SIZE (SRAM2_BB_BASE_SHIFT - SRAM1_BB_BASE_SHIFT) +#define SRAM2_BB_SIZE (PERIPH_BASE_SHIFT - SRAM2_BB_BASE_SHIFT) +#define PERIPH_SIZE (BKPSRAM_BASE_SHIFT - PERIPH_BASE_SHIFT) +//#define BKPSRAM_SIZE (PERIPH_BB_BASE_SHIFT - BKPSRAM_BASE_SHIFT) +#define PERIPH_BB_SIZE (BKPSRAM_BB_BASE_SHIFT - PERIPH_BB_BASE_SHIFT) +//#define BKPSRAM_BB_SIZE (FSMC_R_BASE_SHIFT - BKPSRAM_BB_BASE_SHIFT) +#define FSMC_R_SIZE (MCU_MEM_END - FSMC_R_BASE_SHIFT) +#define DEBUG_MCU_SIZE (2) + + +typedef struct _memory +{ + //uint8_t RESERVED[FLASH_BASE_SHIFT]; + + uint8_t FLASH_BASE[FLASH_SIZE]; + uint8_t CCMDATARAM_BASE[CCMDATARAM_SIZE]; + uint8_t FLASH_OTP_BASE[FLASH_OTP_SIZE]; + uint8_t SRAM1_BASE[SRAM1_SIZE]; + uint8_t SRAM2_BASE[SRAM2_SIZE]; + uint8_t SRAM1_BB_BASE[SRAM1_SIZE]; + uint8_t SRAM2_BB_BASE[SRAM2_SIZE]; + uint8_t PERIPH_BASE[PERIPH_SIZE]; + uint8_t BKPSRAM_BASE[BKPSRAM_SIZE]; + uint8_t PERIPH_BB_BASE[PERIPH_BB_SIZE]; + uint8_t BKPSRAM_BB_BASE[BKPSRAM_SIZE]; + uint8_t FSMC_R_BASE[FSMC_R_SIZE]; + uint8_t DEBUG_MCU_BASE[DEBUG_MCU_SIZE]; +}MCU_MemoryTypeDef; +extern MCU_MemoryTypeDef MCU_MEM; + +#define FLASH_BASE (MCU_MEM.CCMDATARAM_BASE) /*!< FLASH(up to 1 MB) base address in the alias region */ +#define CCMDATARAM_BASE (MCU_MEM.CCMDATARAM_BASE) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region */ +#define SRAM1_BASE (MCU_MEM.SRAM1_BASE) /*!< SRAM1(112 KB) base address in the alias region */ +#define SRAM2_BASE (MCU_MEM.SRAM2_BASE) /*!< SRAM2(16 KB) base address in the alias region */ +#define PERIPH_BASE (MCU_MEM.PERIPH_BASE) /*!< Peripheral base address in the alias region */ +#define BKPSRAM_BASE (MCU_MEM.BKPSRAM_BASE) /*!< Backup SRAM(4 KB) base address in the alias region */ +#define FSMC_R_BASE (MCU_MEM.FSMC_R_BASE) /*!< FSMC registers base address */ +#define SRAM1_BB_BASE (MCU_MEM.SRAM1_BB_BASE) /*!< SRAM1(112 KB) base address in the bit-band region */ +#define SRAM2_BB_BASE (MCU_MEM.SRAM2_BB_BASE) /*!< SRAM2(16 KB) base address in the bit-band region */ +#define PERIPH_BB_BASE (MCU_MEM.PERIPH_BB_BASE) /*!< Peripheral base address in the bit-band region */ +#define BKPSRAM_BB_BASE (MCU_MEM.BKPSRAM_BB_BASE) /*!< Backup SRAM(4 KB) base address in the bit-band region */ +#define FLASH_END (MCU_MEM.FLASH_END) /*!< FLASH end address */ +#define FLASH_OTP_BASE (MCU_MEM.FLASH_OTP_BASE) /*!< Base address of : (up to 528 Bytes) embedded FLASH OTP Area */ +#define FLASH_OTP_END (MCU_MEM.FLASH_OTP_END) /*!< End address of : (up to 528 Bytes) embedded FLASH OTP Area */ +#define CCMDATARAM_END (MCU_MEM.CCMDATARAM_END) /*!< CCM data RAM end address */ + +/*!< Debug MCU registers base address */ +#define DBGMCU_BASE (MCU_MEM.DEBUG_MCU_BASE) +/** + * @} + */ \ No newline at end of file diff --git a/MCU_STM32F4xx_Matlab/Drivers/STM32F4xx_SIMULINK/stm32f4xx_matlab_gpio.c b/MCU_STM32F4xx_Matlab/Drivers/STM32F4xx_SIMULINK/stm32f4xx_matlab_gpio.c deleted file mode 100644 index 51d77fc..0000000 --- a/MCU_STM32F4xx_Matlab/Drivers/STM32F4xx_SIMULINK/stm32f4xx_matlab_gpio.c +++ /dev/null @@ -1,69 +0,0 @@ -#include "stm32f4xx_matlab_gpio.h" -#include "modbus.h" - -/** - * @brief Write S-Function disc ports from MCU GPIOs. - * @param disc - discrete array of S-Function. Outputs would be written from disc. - * @details Ð¤ÑƒÐ½ÐºÑ†Ð¸Ñ Ð´Ð»Ñ Ð·Ð°Ð¿Ð¸Ñи диÑкретных выходов S-Function из GPIO. - ПоÑле в @ref SIM_writeOutputs из disc формируютÑÑ Ð²Ñ‹Ñ…Ð¾Ð´Ñ‹ S-Function. - */ -void GPIO_to_SFUNC(real_T* disc) -{ - for (int i = 0; i < PORT_WIDTH; i++) - { - if (GPIOB->ODR & (1 << i)) - { - disc[i] = 1; - } - - if (GPIOD->ODR & (1 << i)) - { - disc[PORT_WIDTH + i] = 1; - } - - if (GPIOE->ODR & (1 << i)) - { - disc[2*PORT_WIDTH + i] = 1; - } - } -} - -/** - * @brief Write S-Function inputs to MCU. - * @param disc - discrete array of S-Function. Outputs would be written from disc. - * @details Ð¤ÑƒÐ½ÐºÑ†Ð¸Ñ Ð´Ð»Ñ ÑÑ‡Ð¸Ñ‚Ñ‹Ð²Ð°Ð½Ð¸Ñ Ð²Ñ…Ð¾Ð´Ð¾Ð² S-Function в МК. - Можно абÑтрагироватьÑÑ Ð¾Ñ‚ ÑÑ‡Ð¸Ñ‚Ñ‹Ð²Ð°Ð½Ð¸Ñ Ð² GPIO и запиÑывать напрÑмую в переменные МК. - */ -void SFUNC_to_GPIO(real_T* in) -{ - // write pwm ctrl registers - for (int i = 0; i < 5; i++) - { - pwm_ctrl[i] = in[i]; - } - // write pwm ctrl coils - if (in[5] > 0.5) - { - MB_Set_Coil_Local(coils_regs, COIL_PWM_DC_MODE); - } - else - { - MB_Reset_Coil_Local(coils_regs, COIL_PWM_DC_MODE); - } - if (in[6] > 0.5) - { - MB_Set_Coil_Local(coils_regs, COIL_PWM_CH_MODE); - } - else - { - MB_Reset_Coil_Local(coils_regs, COIL_PWM_CH_MODE); - } - if (in[7] > 0.5) - { - MB_Set_Coil_Local(coils_regs, COIL_PWM_PHASE_MODE); - } - else - { - MB_Reset_Coil_Local(coils_regs, COIL_PWM_PHASE_MODE); - } -} \ No newline at end of file diff --git a/MCU_STM32F4xx_Matlab/Drivers/STM32F4xx_SIMULINK/stm32f4xx_matlab_gpio.h b/MCU_STM32F4xx_Matlab/Drivers/STM32F4xx_SIMULINK/stm32f4xx_matlab_gpio.h deleted file mode 100644 index b28e59b..0000000 --- a/MCU_STM32F4xx_Matlab/Drivers/STM32F4xx_SIMULINK/stm32f4xx_matlab_gpio.h +++ /dev/null @@ -1,24 +0,0 @@ -#ifndef _MATLAB_GPIO_H_ -#define _MATLAB_GPIO_H_ - -#include "stm32f4xx_hal.h" -#include "simstruc.h" -#include "mcu_wrapper_conf.h" - -/** - * @addtogroup GPIO_SIMULATOR - * @ingroup MAIN_SIMULATOR - * @brief Simulator for GPIO - * @details ОпределÑет взаимодейÑтвие портов МК и оболочки (S-Function) - * @{ - */ - -/* Ð¤ÑƒÐ½ÐºÑ†Ð¸Ñ Ð´Ð»Ñ Ð·Ð°Ð¿Ð¸Ñи диÑкретных выходов S-Function из GPIO */ -void SFUNC_to_GPIO(real_T* disc); -/* Ð¤ÑƒÐ½ÐºÑ†Ð¸Ñ Ð´Ð»Ñ ÑÑ‡Ð¸Ñ‚Ñ‹Ð²Ð°Ð½Ð¸Ñ Ð²Ñ…Ð¾Ð´Ð¾Ð² S-Function в МК */ -void GPIO_to_SFUNC(real_T* in); - -/** GPIO_SIMULATOR - * @} - */ -#endif // _MATLAB_GPIO_H_ \ No newline at end of file diff --git a/MCU_STM32F4xx_Matlab/Drivers/STM32F4xx_SIMULINK/stm32f4xx_matlab_rcc.c b/MCU_STM32F4xx_Matlab/Drivers/STM32F4xx_SIMULINK/stm32f4xx_matlab_rcc.c deleted file mode 100644 index e69de29..0000000 diff --git a/MCU_STM32F4xx_Matlab/STM32F4xx_SIMULINK/stm32f4xx_matlab_gpio.c b/MCU_STM32F4xx_Matlab/STM32F4xx_SIMULINK/stm32f4xx_matlab_gpio.c new file mode 100644 index 0000000..a2bd1b6 --- /dev/null +++ b/MCU_STM32F4xx_Matlab/STM32F4xx_SIMULINK/stm32f4xx_matlab_gpio.c @@ -0,0 +1,81 @@ +/** +************************************************************************** +* @file stm32f4xx_matlab_gpio.c +* @brief ИÑходный код ÑимулÑтора портов. +************************************************************************** +@details +Данный файл Ñодержит функции Ð´Ð»Ñ ÑимулÑции портов STM32F407xx. +**************************************************************************/ +#include "stm32f4xx_matlab_gpio.h" +#include "modbus.h" + +/** + * @brief ЗапиÑÑŒ буфера выходов S-Function из GPIO. + * @param out_buff - указатель на буфер выходов S-Function. + * @details Ð¤ÑƒÐ½ÐºÑ†Ð¸Ñ Ð´Ð»Ñ Ð·Ð°Ð¿Ð¸Ñи буфера выходов S-Function из GPIO. + ПоÑле в @ref SIM_writeOutputs() из out_buff формируютÑÑ Ð²Ñ‹Ñ…Ð¾Ð´Ñ‹ S-Function. + + * @attention Тело функции пишетÑÑ Ð¿Ð¾Ð»ÑŒÐ·Ð¾Ð²Ð°Ñ‚ÐµÐ»ÐµÐ¼! + */ +void GPIO_to_SFUNC(real_T* out_buff) +{ + for (int i = 0; i < PORT_WIDTH; i++) + { + if (GPIOB->ODR & (1 << i)) + { + out_buff[i] = 1; + } + + if (GPIOD->ODR & (1 << i)) + { + out_buff[PORT_WIDTH + i] = 1; + } + + if (GPIOE->ODR & (1 << i)) + { + out_buff[2*PORT_WIDTH + i] = 1; + } + } +} + +/** + * @brief Считывание входов S-Function в МК. + * @param out_buff - указатель на буфер выходов S-Function. + * @details Ð¤ÑƒÐ½ÐºÑ†Ð¸Ñ Ð´Ð»Ñ ÑÑ‡Ð¸Ñ‚Ñ‹Ð²Ð°Ð½Ð¸Ñ Ð²Ñ…Ð¾Ð´Ð¾Ð² S-Function в МК. + Можно абÑтрагироватьÑÑ Ð¾Ñ‚ ÑÑ‡Ð¸Ñ‚Ñ‹Ð²Ð°Ð½Ð¸Ñ Ð² GPIO и запиÑывать напрÑмую в переменные МК. + + * @attention Тело функции пишетÑÑ Ð¿Ð¾Ð»ÑŒÐ·Ð¾Ð²Ð°Ñ‚ÐµÐ»ÐµÐ¼! + */ +void SFUNC_to_GPIO(real_T* in) +{ + // write pwm ctrl registers + for (int i = 0; i < 5; i++) + { + pwm_ctrl[i] = in[i]; + } + // write pwm ctrl coils + if (in[5] > 0.5) + { + MB_Set_Coil_Local(coils_regs, COIL_PWM_DC_MODE); + } + else + { + MB_Reset_Coil_Local(coils_regs, COIL_PWM_DC_MODE); + } + if (in[6] > 0.5) + { + MB_Set_Coil_Local(coils_regs, COIL_PWM_CH_MODE); + } + else + { + MB_Reset_Coil_Local(coils_regs, COIL_PWM_CH_MODE); + } + if (in[7] > 0.5) + { + MB_Set_Coil_Local(coils_regs, COIL_PWM_PHASE_MODE); + } + else + { + MB_Reset_Coil_Local(coils_regs, COIL_PWM_PHASE_MODE); + } +} \ No newline at end of file diff --git a/MCU_STM32F4xx_Matlab/STM32F4xx_SIMULINK/stm32f4xx_matlab_gpio.h b/MCU_STM32F4xx_Matlab/STM32F4xx_SIMULINK/stm32f4xx_matlab_gpio.h new file mode 100644 index 0000000..10f7784 --- /dev/null +++ b/MCU_STM32F4xx_Matlab/STM32F4xx_SIMULINK/stm32f4xx_matlab_gpio.h @@ -0,0 +1,32 @@ +/** +************************************************************************** +* @file stm32f4xx_matlab_gpio.h +* @brief Заголовочный файл Ð´Ð»Ñ ÑимулÑтора портов. +************************************************************************** +@details +Данный файл Ñодержит объÑÐ²Ð»ÐµÐ½Ð¸Ñ Ð²ÑÑкого Ð´Ð»Ñ ÑимулÑции портов STM32F407xx. +**************************************************************************/ +#ifndef _MATLAB_GPIO_H_ +#define _MATLAB_GPIO_H_ + +#include "stm32f4xx_hal.h" +#include "simstruc.h" +#include "mcu_wrapper_conf.h" + +/** + * @addtogroup GPIO_SIMULATOR GPIO Simulator + * @ingroup MAIN_SIMULATOR + * @brief СимулÑтор Ð´Ð»Ñ Ð¿Ð¾Ñ€Ñ‚Ð¾Ð² ввода-вывода + * @details ОпределÑет взаимодейÑтвие портов МК и оболочки (S-Function) + * @{ + */ + +/* Ð¤ÑƒÐ½ÐºÑ†Ð¸Ñ Ð´Ð»Ñ Ð·Ð°Ð¿Ð¸Ñи буфера выходов S-Function из GPIO */ +void SFUNC_to_GPIO(real_T* out_buff); +/* Ð¤ÑƒÐ½ÐºÑ†Ð¸Ñ Ð´Ð»Ñ ÑÑ‡Ð¸Ñ‚Ñ‹Ð²Ð°Ð½Ð¸Ñ Ð²Ñ…Ð¾Ð´Ð¾Ð² S-Function в МК */ +void GPIO_to_SFUNC(real_T* in); + +/** GPIO_SIMULATOR + * @} + */ +#endif // _MATLAB_GPIO_H_ \ No newline at end of file diff --git a/MCU_STM32F4xx_Matlab/STM32F4xx_SIMULINK/stm32f4xx_matlab_rcc.c b/MCU_STM32F4xx_Matlab/STM32F4xx_SIMULINK/stm32f4xx_matlab_rcc.c new file mode 100644 index 0000000..405822f --- /dev/null +++ b/MCU_STM32F4xx_Matlab/STM32F4xx_SIMULINK/stm32f4xx_matlab_rcc.c @@ -0,0 +1,8 @@ +/* +************************************************************************** +* @file stm32f4xx_matlab_rcc.c +* @brief Èñõîäíûé êîä ñèìóëÿòîðà êëîêà. +************************************************************************** +@details +Äàííûé ôàéë ñîäåðæèò ôóíêöèè äëÿ ñèìóëÿöèè êëîêà STM32F407xx. +**************************************************************************/ diff --git a/MCU_STM32F4xx_Matlab/Drivers/STM32F4xx_SIMULINK/stm32f4xx_matlab_rcc.h b/MCU_STM32F4xx_Matlab/STM32F4xx_SIMULINK/stm32f4xx_matlab_rcc.h similarity index 75% rename from MCU_STM32F4xx_Matlab/Drivers/STM32F4xx_SIMULINK/stm32f4xx_matlab_rcc.h rename to MCU_STM32F4xx_Matlab/STM32F4xx_SIMULINK/stm32f4xx_matlab_rcc.h index 08ed34e..bb7974e 100644 --- a/MCU_STM32F4xx_Matlab/Drivers/STM32F4xx_SIMULINK/stm32f4xx_matlab_rcc.h +++ b/MCU_STM32F4xx_Matlab/STM32F4xx_SIMULINK/stm32f4xx_matlab_rcc.h @@ -1,12 +1,20 @@ +/** +************************************************************************** +* @file stm32f4xx_matlab_rcc.h +* @brief Заголовочный файл Ð´Ð»Ñ ÑимулÑтора клока. +************************************************************************** +@details +Данный файл Ñодержит объÑÐ²Ð»ÐµÐ½Ð¸Ñ Ð²ÑÑкого Ð´Ð»Ñ ÑимулÑции клока STM32F407xx. +**************************************************************************/ #ifndef _MATLAB_RCC_H_ #define _MATLAB_RCC_H_ #include "mcu_wrapper_conf.h" /** - * @addtogroup RCC_SIMULATOR + * @addtogroup RCC_SIMULATOR RCC Simulator * @ingroup MAIN_SIMULATOR - * @brief Simulator for RCC and Clocks + * @brief СимулÑтор Ð´Ð»Ñ RCC и чаÑов таймера * @details Определ¤ет параметры Ñ‚Ð°ÐºÑ‚Ð¸Ñ€Ð¾Ð²Ð°Ð½Ð¸Ñ ÐœÐš. Содержит дефайны дл¤ Ñкипа беÑконечных циклов ожидающих выÑтавление флагов * @{ @@ -24,7 +32,7 @@ #define ABP2_TIMS_Value (double)72000000; /* Эти дефайны добавлены в код stm32f4xx_hal_rcc.c, чтобы не попаÑÑ‚ÑŒ в беÑконечный цикл */ -/* Мб перенеÑти в MCU_Periph_Simulation(), но чет не хочетÑÑ Ð½Ð°Ð³Ñ€ÑƒÐ¶Ð°Ñ‚ÑŒ ÑимулÑцию Ñтой херней*/ +/* Мб перенеÑти в MCU_Periph_Simulation(), но чет не хочетÑÑ Ð½Ð°Ð³Ñ€ÑƒÐ¶Ð°Ñ‚ÑŒ ÑимулÑцию Ñтой херней */ #define _RCC_SET_FLAG(__FLAG__) \ if(((__FLAG__) >> 5U) == 1U) RCC->CR |= (1U << ((__FLAG__) & RCC_FLAG_MASK)); \ else if(((__FLAG__) >> 5U) == 2U) RCC->BDCR |= (1U << ((__FLAG__) & RCC_FLAG_MASK)); \ diff --git a/MCU_STM32F4xx_Matlab/Drivers/STM32F4xx_SIMULINK/stm32f4xx_matlab_tim.c b/MCU_STM32F4xx_Matlab/STM32F4xx_SIMULINK/stm32f4xx_matlab_tim.c similarity index 68% rename from MCU_STM32F4xx_Matlab/Drivers/STM32F4xx_SIMULINK/stm32f4xx_matlab_tim.c rename to MCU_STM32F4xx_Matlab/STM32F4xx_SIMULINK/stm32f4xx_matlab_tim.c index c688aa2..f85a6c3 100644 --- a/MCU_STM32F4xx_Matlab/Drivers/STM32F4xx_SIMULINK/stm32f4xx_matlab_tim.c +++ b/MCU_STM32F4xx_Matlab/STM32F4xx_SIMULINK/stm32f4xx_matlab_tim.c @@ -1,6 +1,10 @@ -/************************************************************************** +/** +************************************************************************** +* @file stm32f4xx_matlab_tim.c +* @brief ИÑходный код ÑимулÑтора таймеров. +************************************************************************** +@details Данный файл Ñодержит функции Ð´Ð»Ñ ÑимулÑции таймеров STM32F407xx. - **************************************************************************/ #include "stm32f4xx_matlab_tim.h" @@ -10,7 +14,17 @@ struct SlaveChannels Slave_Channels; ///< Ñтруктура Ð´Ð»Ñ ÑвÑзи //----------------------TIMER BASE FUNCTIONS-----------------------// -/** Ð‘Ð°Ð·Ð¾Ð²Ð°Ñ Ñ„ÑƒÐ½ÐºÑ†Ð¸Ñ Ð´Ð»Ñ ÑимулÑции таймера: она вызываетÑÑ ÐºÐ°Ð¶Ð´Ñ‹Ð¹ шаг ÑимулÑции */ +/** + * @brief СимулÑÑ†Ð¸Ñ Ñ‚Ð°Ð¹Ð¼ÐµÑ€Ð° на один такт ÑимулÑции. + * @param TIMx – таймер, каналы которого надо запиÑать. + * @param TIMS – Ñтруктура таймера Ð´Ð»Ñ ÑимулÑции. + * @details Это Ð±Ð°Ð·Ð¾Ð²Ð°Ñ Ñ„ÑƒÐ½ÐºÑ†Ð¸Ñ Ð´Ð»Ñ ÑимулÑции таймера: она вызываетÑÑ ÐºÐ°Ð¶Ð´Ñ‹Ð¹ шаг ÑимулÑции + * и вызывает вÑе другие функции, необходимые Ð´Ð»Ñ ÑимулÑции: + * - Overflow_Check() + * - Slave_Mode_Check_Source() + * - TIMx_Count() + * - Channels_Simulation() + */ void TIM_Simulation(TIM_TypeDef *TIMx, struct TIM_Sim *TIMS) { Overflow_Check(TIMx, TIMS); @@ -18,25 +32,34 @@ void TIM_Simulation(TIM_TypeDef *TIMx, struct TIM_Sim *TIMS) // Выбор режима работы таймера -switch (TIMx->SMCR & TIM_SMCR_SMS) // TIMER MODE -{ - // обычный Ñчет - case(TIM_SLAVEMODE_DISABLE):// NORMAL MODE counting - TIMx_Count(TIMx, TIMS); - Channels_Simulation(TIMx, TIMS); // CaptureCompare and PWM channels simulation - break; + switch (TIMx->SMCR & TIM_SMCR_SMS) // TIMER MODE + { + // обычный Ñчет + case(TIM_SLAVEMODE_DISABLE):// NORMAL MODE counting + TIMx_Count(TIMx, TIMS); + Channels_Simulation(TIMx, TIMS); // CaptureCompare and PWM channels simulation + break; - // включение Ñлейв таймера по ивенту - case(TIM_SLAVEMODE_TRIGGER): // SLAVE MODE: TRIGGER MODE - Slave_Mode_Check_Source(TIMx, TIMS); - TIMx_Count(TIMx, TIMS); - Channels_Simulation(TIMx, TIMS); // CaptureCompare and PWM channels simulation - break; -} + // включение Ñлейв таймера по ивенту + case(TIM_SLAVEMODE_TRIGGER): // SLAVE MODE: TRIGGER MODE + Slave_Mode_Check_Source(TIMx, TIMS); + TIMx_Count(TIMx, TIMS); + Channels_Simulation(TIMx, TIMS); // CaptureCompare and PWM channels simulation + break; + } } -/** Счет таймера за один такт */ +/** + * @brief СимулÑÑ†Ð¸Ñ Ñчетчика таймера на один такт ÑимулÑции. + * @param TIMx – таймер, каналы которого надо запиÑать. + * @param TIMS – Ñтруктура таймера Ð´Ð»Ñ ÑимулÑции. + * @details Ð”Ð°Ð½Ð½Ð°Ñ Ñ„ÑƒÐ½ÐºÑ†Ð¸Ñ Ð¿Ñ€Ð¾Ð²ÐµÑ€Ñет направление таймера и увеличивает или уменьшает + * значение Ñчетчика на то чиÑло, на которое оно бы увеличилоÑÑŒ за шаг ÑимулÑции. + * @note Ð”Ð»Ñ Ñчетчика иÑпользуетÑÑ double формат, Ñ‚.к. кол-во Ñчетов за шаг ÑимулÑции + может быть дробным. ПоÑле в конце функции double Ñчетчик запиÑывает Ñ Ð¾ÐºÑ€ÑƒÐ³Ð»ÐµÐ½Ð¸ÐµÐ¼ + в региÑÑ‚Ñ€ таймера CNT. + */ void TIMx_Count(TIM_TypeDef* TIMx, struct TIM_Sim* TIMS) { if ((TIMx->CR1 & TIM_CR1_DIR) && TIMx->CR1) // up COUNTER and COUNTER ENABLE @@ -45,7 +68,15 @@ void TIMx_Count(TIM_TypeDef* TIMx, struct TIM_Sim* TIMS) TIMS->tx_cnt += TIMS->tx_step / TIMx->PSC; TIMx->CNT = (uint32_t)TIMS->tx_cnt; } -/** Проверка на переполнение и Ð´Ð°Ð»ÑŒÐ½ÐµÐ¹ÑˆÐ°Ñ ÐµÐ³Ð¾ обработка */ + +/** + * @brief Проверка на переполнение и Ð´Ð°Ð»ÑŒÐ½ÐµÐ¹ÑˆÐ°Ñ ÐµÐ³Ð¾ обработка. + * @param TIMx – таймер, каналы которого надо запиÑать. + * @param TIMS – Ñтруктура таймера Ð´Ð»Ñ ÑимулÑции. + * @details Ð”Ð°Ð½Ð½Ð°Ñ Ñ„ÑƒÐ½ÐºÑ†Ð¸Ñ Ð¿Ñ€Ð¾Ð²ÐµÑ€Ñет когда таймер переполнитьÑÑ Ð¸ еÑли надо, + вызывает ÑоответÑтвующее прерывание: + - call_IRQHandller() + */ void Overflow_Check(TIM_TypeDef* TIMx, struct TIM_Sim* TIMS) { // Переполнение таймера: ÑÐ±Ñ€Ð¾Ñ Ñ‚Ð°Ð¹Ð¼ÐµÑ€Ð° и вызов Ð¿Ñ€ÐµÑ€Ñ‹Ð²Ð°Ð½Ð¸Ñ @@ -61,7 +92,8 @@ void Overflow_Check(TIM_TypeDef* TIMx, struct TIM_Sim* TIMS) else if (TIMS->tx_cnt < 0) TIMS->tx_cnt = TIMx->ARR; - call_IRQHandller(TIMx); // call HANDLER + if(TIMx->DIER & TIM_DIER_UIE) // if update interrupt enable + call_IRQHandller(TIMx); // call HANDLER } } } @@ -70,7 +102,19 @@ void Overflow_Check(TIM_TypeDef* TIMx, struct TIM_Sim* TIMS) //----------------------------CHANNELS-----------------------------// -/** СимулÑÑ†Ð¸Ñ ÐºÐ°Ð½Ð°Ð»Ð¾Ð² таймера */ +/** + * @brief СимулÑÑ†Ð¸Ñ ÐºÐ°Ð½Ð°Ð»Ð¾Ð² таймера. + * @param TIMx – таймер, каналы которого надо запиÑать. + * @param TIMS – Ñтруктура таймера Ð´Ð»Ñ ÑимулÑции. + * @details Ð”Ð°Ð½Ð½Ð°Ñ Ñ„ÑƒÐ½ÐºÑ†Ð¸Ñ Ñимулирует работу вÑех каналов таймера. + * Она вызывает функции: + * - CC_PWM_Ch1_Simulation() + * - CC_PWM_Ch2_Simulation() + * - CC_PWM_Ch3_Simulation() + * - CC_PWM_Ch4_Simulation() + * - Write_OC_to_GPIO() + * - Write_OC_to_TRGO() + */ void Channels_Simulation(TIM_TypeDef* TIMx, struct TIM_Sim* TIMS) { CC_PWM_Ch1_Simulation(TIMx, TIMS); @@ -83,7 +127,13 @@ void Channels_Simulation(TIM_TypeDef* TIMx, struct TIM_Sim* TIMS) Write_OC_to_TRGO(TIMx, TIMS); } //-----------------CAPTURE COPMARE & PWM FUNCTIONS------------------// -/** Выбор режима CaptureCompare или PWM и ÑимулÑÑ†Ð¸Ñ Ð´Ð»Ñ Ð¿ÐµÑ€Ð²Ð¾Ð³Ð¾ канала */ +/** + * @brief Выбор режима первого канала и его ÑимулÑциÑ. + * @param TIMx – таймер, каналы которого надо запиÑать. + * @param TIMS – Ñтруктура таймера Ð´Ð»Ñ ÑимулÑции. + * @details Ð”Ð°Ð½Ð½Ð°Ñ Ñ„ÑƒÐ½ÐºÑ†Ð¸Ñ Ð¿Ð¾ региÑтрам таймера проверÑет как наÑтроен + первый канал и ÑоответÑтвующе Ñимулирует его работу. + */ void CC_PWM_Ch1_Simulation(TIM_TypeDef *TIMx, struct TIM_Sim *TIMS) { // определÑет режим канала switch (TIMx->CCMR1 & TIM_CCMR1_OC1M) @@ -125,7 +175,13 @@ switch (TIMx->CCMR1 & TIM_CCMR1_OC1M) } } -/** Выбор режима CaptureCompare или PWM и ÑимулÑÑ†Ð¸Ñ Ð´Ð»Ñ Ð²Ñ‚Ð¾Ñ€Ð¾Ð³Ð¾ канала */ +/** + * @brief Выбор режима второго канала и его ÑимулÑциÑ. + * @param TIMx – таймер, каналы которого надо запиÑать. + * @param TIMS – Ñтруктура таймера Ð´Ð»Ñ ÑимулÑции. + * @details Ð”Ð°Ð½Ð½Ð°Ñ Ñ„ÑƒÐ½ÐºÑ†Ð¸Ñ Ð¿Ð¾ региÑтрам таймера проверÑет как наÑтроен + второй канал и ÑоответÑтвующе Ñимулирует его работу. + */ void CC_PWM_Ch2_Simulation(TIM_TypeDef *TIMx, struct TIM_Sim *TIMS) { // определÑет режим канала switch (TIMx->CCMR1 & TIM_CCMR1_OC2M) @@ -167,7 +223,13 @@ switch (TIMx->CCMR1 & TIM_CCMR1_OC2M) } } -/** Выбор режима CaptureCompare или PWM и ÑимулÑÑ†Ð¸Ñ Ð´Ð»Ñ Ñ‚Ñ€ÐµÑ‚ÑŒÐµÐ³Ð¾ канала */ +/** + * @brief Выбор режима третьего канала и его ÑимулÑциÑ. + * @param TIMx – таймер, каналы которого надо запиÑать. + * @param TIMS – Ñтруктура таймера Ð´Ð»Ñ ÑимулÑции. + * @details Ð”Ð°Ð½Ð½Ð°Ñ Ñ„ÑƒÐ½ÐºÑ†Ð¸Ñ Ð¿Ð¾ региÑтрам таймера проверÑет как наÑтроен + третий канал и ÑоответÑтвующе Ñимулирует его работу. + */ void CC_PWM_Ch3_Simulation(TIM_TypeDef *TIMx, struct TIM_Sim *TIMS) { // определÑет режим канала switch (TIMx->CCMR2 & TIM_CCMR1_OC1M) @@ -209,7 +271,13 @@ switch (TIMx->CCMR2 & TIM_CCMR1_OC1M) } } -/** Выбор режима CaptureCompare или PWM и ÑимулÑÑ†Ð¸Ñ Ð´Ð»Ñ Ñ‡ÐµÑ‚Ð²ÐµÑ€Ñ‚Ð¾Ð³Ð¾ канала */ +/** + * @brief Выбор режима четвертого канала и его ÑимулÑциÑ. + * @param TIMx – таймер, каналы которого надо запиÑать. + * @param TIMS – Ñтруктура таймера Ð´Ð»Ñ ÑимулÑции. + * @details Ð”Ð°Ð½Ð½Ð°Ñ Ñ„ÑƒÐ½ÐºÑ†Ð¸Ñ Ð¿Ð¾ региÑтрам таймера проверÑет как наÑтроен + четвертый канал и ÑоответÑтвующе Ñимулирует его работу. + */ void CC_PWM_Ch4_Simulation(TIM_TypeDef *TIMx, struct TIM_Sim *TIMS) { // определÑет режим канала switch (TIMx->CCMR2 & TIM_CCMR1_OC2M) @@ -251,7 +319,14 @@ switch (TIMx->CCMR2 & TIM_CCMR1_OC2M) } } -/** ЗапиÑÑŒ каналов таймера в порты GPIO */ + +/** + * @brief ЗапиÑÑŒ каналов таймера в порты GPIO. + * @param TIMx – таймер, каналы которого надо запиÑать. + * @param TIMS – Ñтруктура того же таймера Ð´Ð»Ñ ÑимулÑции. + * @details Ð”Ð°Ð½Ð½Ð°Ñ Ñ„ÑƒÐ½ÐºÑ†Ð¸Ñ Ð·Ð°Ð¿Ð¸Ñывает каналы OC в порты GPIO, определенные в TIMS. + * ЗапиÑÑŒ проиÑходит только еÑли пин наÑтроен на альтернативную функцию. + */ void Write_OC_to_GPIO(TIM_TypeDef *TIMx, struct TIM_Sim *TIMS) { // write gpio pin if need @@ -326,6 +401,12 @@ void Write_OC_to_GPIO(TIM_TypeDef *TIMx, struct TIM_Sim *TIMS) } } /** ЗапиÑÑŒ результата compare в глабальную Ñтруктуру Ñ TRIGGER OUTPUT */ +/** + * @brief ЗапиÑÑŒ каналов таймера в глабальную Ñтруктуру Ñ TRIGGER OUTPUT. + * @param TIMx – таймер, каналы которого надо запиÑать. + * @param TIMS – Ñтруктура того же таймера Ð´Ð»Ñ ÑимулÑции. + * @details Ð”Ð°Ð½Ð½Ð°Ñ Ñ„ÑƒÐ½ÐºÑ†Ð¸Ñ Ñчитывает каналы OC и запиÑывает их в внешний канал триггера TRGO. + */ void Write_OC_to_TRGO(TIM_TypeDef* TIMx, struct TIM_Sim* TIMS) { // write trigger output from OCxREF pin if need @@ -372,7 +453,15 @@ void Write_OC_to_TRGO(TIM_TypeDef* TIMx, struct TIM_Sim* TIMS) //--------------------MISC (temporary) FUNCTIONS--------------------// /** Определение иÑточника Ð´Ð»Ñ Ð·Ð°Ð¿ÑƒÑка таймера в SLAVE MODE */ -void Slave_Mode_Check_Source(TIM_TypeDef* TIMx, struct TIM_Sim* TIMS) +/** + * @brief Определение иÑточника Ð´Ð»Ñ Ð·Ð°Ð¿ÑƒÑка таймера в SLAVE MODE. + * @param TIMx – таймер, который надо включить. + * @param TIMx – таймер, прерываний которого надо вызвать. + * @details Ð”Ð°Ð½Ð½Ð°Ñ Ñ„ÑƒÐ½ÐºÑ†Ð¸Ñ Ð¿Ñ€Ð¾Ð²ÐµÑ€Ñет какой триггер выбран Ð´Ð»Ñ Ð·Ð°Ð¿ÑƒÑка таймера, + * поÑле запиÑывает значение канала триггера в бит Ð²ÐºÐ»ÑŽÑ‡ÐµÐ½Ð¸Ñ Ñ‚Ð°Ð¹Ð¼ÐµÑ€Ð°. + * Таким образом, при лог.1 в канале триггера - таймер включитьÑÑ. + */ +void Slave_Mode_Check_Source(TIM_TypeDef* TIMx) { if (TIMx == TIM2) { @@ -424,6 +513,11 @@ void Slave_Mode_Check_Source(TIM_TypeDef* TIMx, struct TIM_Sim* TIMS) //------------------------SIMULINK FUNCTIONS------------------------// /** Симулирование выбранных через дефайн таймеров */ +/** + * @brief СимулÑÑ†Ð¸Ñ Ð²Ñ‹Ð±Ñ€Ð°Ð½Ð½Ñ‹Ñ… таймеров. + * @details Таймеры Ð´Ð»Ñ ÑимулÑции выбираютÑÑ Ñ‡ÐµÑ€ÐµÐ· дефайны в stm32f4xx_matlab_conf.h. + Ð¤ÑƒÐ½ÐºÑ†Ð¸Ñ Ð²Ñ‹Ð·Ñ‹Ð²Ð°ÐµÑ‚ÑÑ Ð½Ð° каждом шаге ÑимулÑции. + */ void Simulate_TIMs(void) { #ifdef USE_TIM1 @@ -469,7 +563,11 @@ void Simulate_TIMs(void) TIM_Simulation(TIM14, &tim14s); #endif } -/* Деинициализирование выбранных через дефайн таймеров (вызываетÑÑ Ð² конце ÑимулÑции) */ +/** + * @brief Деинициализирование выбранных таймеров. + * @details Таймеры Ð´Ð»Ñ Ð´ÐµÐ¸Ð½Ð¸Ñ†Ð¸Ð°Ð»Ð¸Ð·Ð¸Ð·Ð°Ñ†Ð¸Ð¸ выбираютÑÑ Ñ‡ÐµÑ€ÐµÐ· дефайны в stm32f4xx_matlab_conf.h. + Ð¤ÑƒÐ½ÐºÑ†Ð¸Ñ Ð²Ñ‹Ð·Ñ‹Ð²Ð°ÐµÑ‚ÑÑ Ð² конце ÑимулÑции. + */ void TIM_SIM_DEINIT(void) { #ifdef USE_TIM1 @@ -558,7 +656,12 @@ void TIM8_BRK_TIM12_IRQHandler(void) {} void TIM8_TRG_COM_TIM14_IRQHandler(void) {} #endif -/** Вызов Ð¿Ñ€ÐµÑ€Ñ‹Ð²Ð°Ð½Ð¸Ñ */ +/** + * @brief Вызов Ð¿Ñ€ÐµÑ€Ñ‹Ð²Ð°Ð½Ð¸Ñ Ñ‚Ð°Ð¹Ð¼ÐµÑ€Ð° TIMx. + * @param TIMx – таймер, прерываний которого надо вызвать. + * @details Ð”Ð°Ð½Ð½Ð°Ñ Ñ„ÑƒÐ½ÐºÑ†Ð¸Ñ Ñимулирует аппаратный вызов Ð¿Ñ€ÐµÑ€Ñ‹Ð²Ð°Ð½Ð¸Ñ + таймера по какому-либо Ñобытию. + */ void call_IRQHandller(TIM_TypeDef* TIMx) { // calling HANDLER if ((TIMx == TIM1) || (TIMx == TIM10)) diff --git a/MCU_STM32F4xx_Matlab/Drivers/STM32F4xx_SIMULINK/stm32f4xx_matlab_tim.h b/MCU_STM32F4xx_Matlab/STM32F4xx_SIMULINK/stm32f4xx_matlab_tim.h similarity index 72% rename from MCU_STM32F4xx_Matlab/Drivers/STM32F4xx_SIMULINK/stm32f4xx_matlab_tim.h rename to MCU_STM32F4xx_Matlab/STM32F4xx_SIMULINK/stm32f4xx_matlab_tim.h index 97699cb..9b200f8 100644 --- a/MCU_STM32F4xx_Matlab/Drivers/STM32F4xx_SIMULINK/stm32f4xx_matlab_tim.h +++ b/MCU_STM32F4xx_Matlab/STM32F4xx_SIMULINK/stm32f4xx_matlab_tim.h @@ -1,6 +1,10 @@ -/************************************************************************** +/** +************************************************************************** +* @file stm32f4xx_matlab_tim.h +* @brief Заголовочный файл Ð´Ð»Ñ ÑимулÑтора таймеров. +************************************************************************** +@details Данный файл Ñодержит объÑÐ²Ð»ÐµÐ½Ð¸Ñ Ð²ÑÑкого Ð´Ð»Ñ ÑимулÑции таймеров STM32F407xx. - **************************************************************************/ #ifndef _MATLAB_TIM_H_ #define _MATLAB_TIM_H_ @@ -10,26 +14,39 @@ #include "mcu_wrapper_conf.h" /** - * @addtogroup TIM_SIMULATOR + * @addtogroup TIM_SIMULATOR TIM Simulator * @ingroup MAIN_SIMULATOR - * @brief Simulator for TIM + * @brief СимулÑтор Ð´Ð»Ñ Ñ‚Ð°Ð¹Ð¼ÐµÑ€Ð¾Ð² * @details Дефайны и функции Ð´Ð»Ñ ÑимулÑции таймеров. * @{ */ /////////////////////////////---DEFINES---///////////////////////////// -/** Дефайн Ð´Ð»Ñ Ñдвига между первой и второй половиной CCMRx региÑтров */ +/** + * @brief Дефайн Ð´Ð»Ñ Ñдвига между первой и второй половиной CCMRx региÑтров + */ #define TIM_OCMODE_SECOND_SHIFT (TIM_CCMR1_OC2M_Pos - TIM_CCMR1_OC1M_Pos) -/** Дефайн Ð´Ð»Ñ Ð¿Ñ€Ð¾Ð²ÐµÑ€ÐºÐ¸ выводить ли канал на GPIO (наÑтроен ли GPIO на альтернативную функцию) */ +/** + * @brief Дефайн Ð´Ð»Ñ Ð¿Ñ€Ð¾Ð²ÐµÑ€ÐºÐ¸ выводить ли канал таймера на GPIO + * @details Данный дефайн проверÑет, наÑтроен ли пин GPIO на альтернативную функцию. ЕÑли да - то таймер выводитьÑÑ Ð½Ð° Ñтот пин + */ #define Check_OCx_GPIO_Output(_tims_, _OCx_GPIOx_, _OCx_PIN_SHIFT_) (_tims_->Channels._OCx_GPIOx_->MODER & (0b11<<(2*_tims_->Channels._OCx_PIN_SHIFT_))) == (0b10<<(2*_tims_->Channels._OCx_PIN_SHIFT_)) -/** Дефайн Ð´Ð»Ñ Ð¿Ñ€Ð¾Ð²ÐµÑ€ÐºÐ¸ выводить ли канал 1 на GPIO (наÑтроен ли GPIO на альтернативную функцию) */ +/** + * @brief Дефайн Ð´Ð»Ñ Ð¿Ñ€Ð¾Ð²ÐµÑ€ÐºÐ¸ выводить ли канал 1 на GPIO (наÑтроен ли GPIO на альтернативную функцию) + */ #define Check_OC1_GPIO_Output(_tims_) Check_OCx_GPIO_Output(_tims_, OC1_GPIOx, OC1_PIN_SHIFT) -/** Дефайн Ð´Ð»Ñ Ð¿Ñ€Ð¾Ð²ÐµÑ€ÐºÐ¸ выводить ли канал 2 на GPIO (наÑтроен ли GPIO на альтернативную функцию) */ +/** + * @brief Дефайн Ð´Ð»Ñ Ð¿Ñ€Ð¾Ð²ÐµÑ€ÐºÐ¸ выводить ли канал 2 на GPIO (наÑтроен ли GPIO на альтернативную функцию) + */ #define Check_OC2_GPIO_Output(_tims_) Check_OCx_GPIO_Output(_tims_, OC2_GPIOx, OC2_PIN_SHIFT) -/** Дефайн Ð´Ð»Ñ Ð¿Ñ€Ð¾Ð²ÐµÑ€ÐºÐ¸ выводить ли канал 3 на GPIO (наÑтроен ли GPIO на альтернативную функцию) */ +/** + * @brief Дефайн Ð´Ð»Ñ Ð¿Ñ€Ð¾Ð²ÐµÑ€ÐºÐ¸ выводить ли канал 3 на GPIO (наÑтроен ли GPIO на альтернативную функцию) + */ #define Check_OC3_GPIO_Output(_tims_) Check_OCx_GPIO_Output(_tims_, OC3_GPIOx, OC3_PIN_SHIFT) -/** Дефайн Ð´Ð»Ñ Ð¿Ñ€Ð¾Ð²ÐµÑ€ÐºÐ¸ выводить ли канал 4 на GPIO (наÑтроен ли GPIO на альтернативную функцию) */ +/** + * @brief Дефайн Ð´Ð»Ñ Ð¿Ñ€Ð¾Ð²ÐµÑ€ÐºÐ¸ выводить ли канал 4 на GPIO (наÑтроен ли GPIO на альтернативную функцию) + */ #define Check_OC4_GPIO_Output(_tims_) Check_OCx_GPIO_Output(_tims_, OC4_GPIOx, OC4_PIN_SHIFT) ///////////////////////////////////////////////////////////////////// @@ -37,7 +54,9 @@ ///////////////////////////---STRUCTURES---////////////////////////// -/** Структура Ð´Ð»Ñ ÑƒÐ¿Ñ€Ð°Ð²Ð»ÐµÐ½Ð¸Ñ Ð¡Ð»ÐµÐ¹Ð² Таймерами */ +/** + * @brief Структура Ð´Ð»Ñ ÑƒÐ¿Ñ€Ð°Ð²Ð»ÐµÐ½Ð¸Ñ Ð¡Ð»ÐµÐ¹Ð² Таймерами + */ struct SlaveChannels { unsigned TIM1_TRGO : 1; ///< Синган Ñинхронизации таймера 1 @@ -51,7 +70,9 @@ struct SlaveChannels }; -/** Структура Ð´Ð»Ñ Ð¼Ð¾Ð´ÐµÐ»Ð¸Ñ€Ð¾Ð²Ð°Ð½Ð¸Ñ ÐºÐ°Ð½Ð°Ð»Ð¾Ð² таймера */ +/** + * @brief Структура Ð´Ð»Ñ Ð¼Ð¾Ð´ÐµÐ»Ð¸Ñ€Ð¾Ð²Ð°Ð½Ð¸Ñ ÐºÐ°Ð½Ð°Ð»Ð¾Ð² таймера + */ struct Channels_Sim { // Каналы таймера @@ -75,12 +96,14 @@ struct Channels_Sim }; -/** Структура Ð´Ð»Ñ Ð¼Ð¾Ð´ÐµÐ»Ð¸Ñ€Ð¾Ð²Ð°Ð½Ð¸Ñ Ñ‚Ð°Ð¹Ð¼ÐµÑ€Ð° */ +/** + * @brief Структура Ð´Ð»Ñ Ð¼Ð¾Ð´ÐµÐ»Ð¸Ñ€Ð¾Ð²Ð°Ð½Ð¸Ñ Ñ‚Ð°Ð¹Ð¼ÐµÑ€Ð° + */ struct TIM_Sim { - double tx_cnt; ///< Счетчик таймера - double tx_step; ///< Шаг Ñчета за один шаг ÑимулÑции - int RELOAD; ///< Буфер, еÑли PRELOAD = 1 + double tx_cnt; ///< Счетчик таймера (double, Ñ‚.к. кол-во тактов за шаг ÑимулÑции может быть дробным) + double tx_step; ///< Шаг Ñчета за один шаг ÑимулÑции (double, Ñ‚.к. кол-во тактов за шаг ÑимулÑции может быть дробным) + int RELOAD; ///< Буфер Ð´Ð»Ñ Ð¿ÐµÑ€Ð¸Ð¾Ð´Ð° таймера (Ð´Ð»Ñ Ñ€ÐµÐ°Ð»Ð¸Ð·Ð°Ñ†Ð¸Ð¸ функции PRELOAD) struct Channels_Sim Channels; ///< Структура Ð´Ð»Ñ ÑимулÑции каналов }; ///////////////////////////////////////////////////////////////////// @@ -119,7 +142,7 @@ void Write_OC_to_TRGO(TIM_TypeDef* TIMx, struct TIM_Sim* TIMS); //--------------------MISC (temporary) FUNCTIONS--------------------// /* Определение иÑточника Ð´Ð»Ñ Ð·Ð°Ð¿ÑƒÑка таймера в SLAVE MODE */ -void Slave_Mode_Check_Source(TIM_TypeDef* TIMx, struct TIM_Sim* TIMS); +void Slave_Mode_Check_Source(TIM_TypeDef* TIMx); //------------------------------------------------------------------// diff --git a/MCU_STM32F4xx_Matlab/Drivers/STM32F4xx_SIMULINK/stm32f4xx_periph_registers.c b/MCU_STM32F4xx_Matlab/STM32F4xx_SIMULINK/stm32f4xx_periph_registers.c similarity index 74% rename from MCU_STM32F4xx_Matlab/Drivers/STM32F4xx_SIMULINK/stm32f4xx_periph_registers.c rename to MCU_STM32F4xx_Matlab/STM32F4xx_SIMULINK/stm32f4xx_periph_registers.c index 69074cb..cef125e 100644 --- a/MCU_STM32F4xx_Matlab/Drivers/STM32F4xx_SIMULINK/stm32f4xx_periph_registers.c +++ b/MCU_STM32F4xx_Matlab/STM32F4xx_SIMULINK/stm32f4xx_periph_registers.c @@ -1,16 +1,36 @@ -/************************************************************************** +/** +************************************************************************** +* @dir ../MCU_STM32F4xx_Matlab/STM32F4xx_SIMULINK +* @brief +* Папка Ñ Ð¸Ñходным кодом ÑимулÑтора МК. +* @details +Ð’ Ñтой папке ÑодержатьÑÑ Ñ„Ð°Ð¹Ð»Ñ‹ Ð´Ð»Ñ ÑмулÑции периферии STM32 в MATLAB. +Структура файлов Ñ‚Ð°ÐºÐ°Ñ Ð¶Ðµ, как в библиотеке HAL: +- название Ñерии МК, который ÑмулируетÑÑ (stm32f4xx), +- идентификатор, что Ñто Ð´Ð»Ñ MATLAB (matlab), +- перифериÑ, функции Ð´Ð»Ñ ÑмулÑции которой Ñодержит конкретный файл (gpio, tim). + +Пример: "stm32f4xx_matlab_tim.c/.h" +**************************************************************************/ + +/** +************************************************************************** +* @file stm32f4xx_periph_registers.c +* @brief ИÑходный код Ñ Ð¿ÐµÑ€ÐµÐ¼ÐµÐ½Ð½Ñ‹Ð¼Ð¸ региÑтров периферии. +************************************************************************** +@details Данный файл необходим Ð´Ð»Ñ Ð¾Ð±ÑŠÑÐ²Ð»ÐµÐ½Ð¸Ñ Ñтруктур Ð´Ð»Ñ Ð¾Ñ‚Ð¾Ð±Ñ€Ð°Ð¶ÐµÐ½Ð¸Ñ Ð¸Ñ… в watch Ð’ оригинальном stm32f407xx они объÑвлены дефайнами, которые не видны в watch. ПоÑтому дополнительно объÑвлены данные Ñтруктуры. -ÐазываютÑÑ Ñ‚Ð°ÐºÐ¶Ðµ, как CMSISные, только в нижнем региÑтре +ÐазываютÑÑ Ñ‚Ð°ÐºÐ¶Ðµ, как CMSISные, только в нижнем региÑтре. **************************************************************************/ #include "stm32f407xx_matlab.h" /** - * @addtogroup PERIPH_VARS_FOR_DEBUG + * @addtogroup PERIPH_VARS_FOR_DEBUG Periphs Variables for Debugging * @ingroup STM_SIMULATION - * @brief Varables of peripheral registers for debug watches + * @brief Переменные Ð´Ð»Ñ Ð´Ð¾Ñтупа к периферии в дебаге * @{ */ diff --git a/MCU_STM32F4xx_Matlab/stm32f4xx_matlab_conf.c b/MCU_STM32F4xx_Matlab/stm32f4xx_matlab_conf.c index 283c779..79f336a 100644 --- a/MCU_STM32F4xx_Matlab/stm32f4xx_matlab_conf.c +++ b/MCU_STM32F4xx_Matlab/stm32f4xx_matlab_conf.c @@ -1,8 +1,13 @@ -/************************************************************************** -Данный файл наÑтраивает Ñтруктуры Ð´Ð»Ñ ÑимулÑции периферий, которые выбраны +/** +************************************************************************** +* @file stm32f4xx_matlab_conf.c +* @brief ИÑходный код Ð´Ð»Ñ ÐºÐ¾Ð½Ñ„Ð¸Ð³ÑƒÑ€Ð°Ñ†Ð¸Ð¸ ÑимулÑтора МК. +************************************************************************** +@details +Данный файл наÑтраивает Ñтруктуры Ð´Ð»Ñ ÑимулÑции периферий, которые выбраны дефайнами в stm32f4xx_matlab_conf.h. - **************************************************************************/ + #include "mcu_wrapper_conf.h" MCU_MemoryTypeDef MCU_MEM; @@ -11,17 +16,27 @@ DBGMCU_TypeDef DEBUG_MCU; //-----------------------------------------------------------------------// /*------------------------------FUNCTIONS--------------------------------*/ -// MCU PERIPH INIT +/** + * @brief Ð˜Ð½Ð¸Ñ†Ð¸Ð°Ð»Ð¸Ð·Ð°Ñ†Ð¸Ñ Ð¿ÐµÑ€Ð¸Ñ„ÐµÑ€Ð¸Ð¸ ÑимулÑтора МК. + * @details Эта Ñ„ÑƒÐ½ÐºÑ†Ð¸Ñ Ð²Ñ‹Ð·Ñ‹Ð²Ð°ÐµÑ‚ функции инициализации периферии Ð´Ð»Ñ ÑимулÑции + */ void Initialize_Periph_Sim(void) { Init_TIM_SIM(); } -// MCU PERIPH DEINIT +/** + * @brief Ð”ÐµÐ¸Ð½Ð¸Ñ†Ð¸Ð°Ð»Ð¸Ð·Ð°Ñ†Ð¸Ñ Ð¿ÐµÑ€Ð¸Ñ„ÐµÑ€Ð¸Ð¸ ÑимулÑтора МК. + * @details Эта Ñ„ÑƒÐ½ÐºÑ†Ð¸Ñ Ð²Ñ‹Ð·Ñ‹Ð²Ð°ÐµÑ‚ функции деинициализации периферии Ð´Ð»Ñ Ð¿Ð¾Ñледующей ÑимулÑции + */ void deInitialize_Periph_Sim(void) { TIM_SIM_DEINIT(); } -// MCU DEINIT +/** + * @brief Ð”ÐµÐ¸Ð½Ð¸Ñ†Ð¸Ð°Ð»Ð¸Ð·Ð°Ñ†Ð¸Ñ ÑимулÑтора МК. + * @details Эта Ñ„ÑƒÐ½ÐºÑ†Ð¸Ñ Ð¾Ñ‡Ð¸Ñ‰Ð°ÐµÑ‚ памÑÑ‚ÑŒ ÑимулÑтора МК, чтобы в + Ñледующей ÑимулÑции он запуÑкалÑÑ ÐºÐ°Ðº в первый раз. + */ void deInitialize_MCU(void) { // обнуление Ñтруктуры, управлÑющей программой МК @@ -82,7 +97,11 @@ struct TIM_Sim tim13s; struct TIM_Sim tim14s; #endif -// defines function for filling structure for simulate +/** + * @brief Ð˜Ð½Ð¸Ñ†Ð¸Ð°Ð»Ð¸Ð·Ð°Ñ†Ð¸Ñ Ñ‚Ð°Ð¹Ð¼ÐµÑ€Ð¾Ð² ÑимулÑтора МК. + * @details Эта Ñ„ÑƒÐ½ÐºÑ†Ð¸Ñ Ð¸Ð½Ð¸Ñ†Ð¸Ð°Ð»Ð¸Ð·Ð¸Ñ€ÑƒÐµÑ‚ Ñтруктуры Ð´Ð»Ñ ÑимулÑции таймеров. + * Таймеры Ð´Ð»Ñ ÑимулÑции выбираютÑÑ Ð´ÐµÑ„Ð°Ð¹Ð½Ð°Ð¼Ð¸ в stm32f4xx_matlab_conf.h. + */ void Init_TIM_SIM(void) { #ifdef USE_TIM1 diff --git a/MCU_STM32F4xx_Matlab/stm32f4xx_matlab_conf.h b/MCU_STM32F4xx_Matlab/stm32f4xx_matlab_conf.h index a2617ed..37e1439 100644 --- a/MCU_STM32F4xx_Matlab/stm32f4xx_matlab_conf.h +++ b/MCU_STM32F4xx_Matlab/stm32f4xx_matlab_conf.h @@ -1,27 +1,44 @@ -/************************************************************************** -Данный файл необходим Ð´Ð»Ñ Ð¾Ð¿Ñ€ÐµÐ´ÐµÐ»ÐµÐ½Ð¸Ñ, какую периферию наобходимо будет -Ñимулировать. - +/** +************************************************************************** +* @dir ../MCU_STM32F4xx_Matlab +* @brief +* Папка Ñ Ð¸Ñходным кодом Ð´Ð»Ñ ÑимулÑции МК. +************************************************************************** +@details +Ð’ данной папке ÑодержатьÑÑ Ð¼Ð¾Ð´ÑƒÐ»Ð¸ Ð´Ð»Ñ ÑимулÑции МК в MATLAB: +- Драйверы МК - они переделаны так, чтобы запуÑкатьÑÑ Ð¸ работать в MATLAB. +- СимулÑтор МК - он моделирует работу нужной периферии в MATLAB **************************************************************************/ + + +/** +************************************************************************** +* @file stm32f4xx_matlab_conf.h +* @brief Заголовочный файл Ð´Ð»Ñ ÐºÐ¾Ð½Ñ„Ð¸Ð³ÑƒÑ€Ð°Ñ†Ð¸Ð¸ ÑимулÑтора МК. +************************************************************************** +@details +ЗдеÑÑŒ задаётÑÑ Ð¸ÑÐ¿Ð¾Ð»ÑŒÐ·ÑƒÐµÐ¼Ð°Ñ Ð¿ÐµÑ€Ð¸Ñ„ÐµÑ€Ð¸Ñ Ð¸ подключаютÑÑ Ð±Ð¸Ð±Ð»Ð¸Ð¾Ñ‚ÐµÐºÐ¸ Ð´Ð»Ñ Ð¿ÐµÑ€Ð¸Ñ„ÐµÑ€Ð¸Ð¸. +**************************************************************************/ + #ifndef _MATLAB_CONF_H_ #define _MATLAB_CONF_H_ /** - * @addtogroup STM_SIMULATION - * @brief Stuff for simulating STM32 in MATLAB + * @addtogroup STM_SIMULATION STM32 Simulation + * @brief Ð’ÑÑкое Ð´Ð»Ñ ÑимулÑции STM32 */ /** - * @addtogroup MAIN_SIMULATOR + * @addtogroup MAIN_SIMULATOR STM32 Simulator * @ingroup STM_SIMULATION - * @brief Stuff for configuring, initializing and deinitializing simulator + * @brief Ð’ÑÑкое Ð´Ð»Ñ ÑимулÑтора STM32 * @details ЗдеÑÑŒ дефайнами задаетÑÑ Ð¸ÑÐ¿Ð¾Ð»ÑŒÐ·ÑƒÐµÐ¼Ð°Ñ Ð¿ÐµÑ€Ð¸Ñ„ÐµÑ€Ð¸Ñ Ð¸ подключаютÑÑ Ñ„Ð°Ð¹Ð»Ñ‹, необходимые Ð´Ð»Ñ ÐµÑ‘ ÑимулÑции */ /** - * @addtogroup SIMULATOR_CONF + * @addtogroup SIMULATOR_CONF Simulator Configuration * @ingroup MAIN_SIMULATOR - * @brief Configurations for simulator to simulating MCU + * @brief Параметры конфигурации Ð´Ð»Ñ ÑимулÑтора МК * @details ЗдеÑÑŒ дефайнами задаетÑÑ Ð¿ÐµÑ€Ð¸Ñ„ÐµÑ€Ð¸Ñ Ð´Ð»Ñ ÑимулÑции * @{ */ @@ -64,12 +81,10 @@ /** -* @addtogroup MAIN_SIMULATOR +* @ingroup MAIN_SIMULATOR * @{ */ - - //-----------------------------------------------------------------------// /*------------------------------FUNCTIONS--------------------------------*/ // MCU PERIPH INIT diff --git a/MCU_Wrapper/MCU.c b/MCU_Wrapper/MCU.c index b5d0b09..bf22c5b 100644 --- a/MCU_Wrapper/MCU.c +++ b/MCU_Wrapper/MCU.c @@ -1,17 +1,40 @@ +/** +************************************************************************** +* @file MCU.c +* @brief ИÑходный код S-Function. +************************************************************************** +@details +Данный файл Ñодержит функции S-Function, который вызывает MATLAB. +************************************************************************** +@note +ОпиÑание функций по большей чаÑти Ñгенерировано MATLAB'ом, поÑтому на английÑком +**************************************************************************/ + +/** + * @addtogroup WRAPPER_SFUNC S-Function funtions + * @ingroup MCU_WRAPPER + * @brief Дефайны и функции блока S-Function + * @details ЗдеÑÑŒ Ñобраны функции, Ñ ÐºÐ¾Ñ‚Ð¾Ñ€Ñ‹Ð¼Ð¸ непоÑредÑтвенно работает S-Function + * @note ОпиÑание функций по большей чаÑти Ñгенерировано MATLAB'ом, поÑтому на английÑком + * @{ + */ + #define S_FUNCTION_NAME MCU #define S_FUNCTION_LEVEL 2 #include "mcu_wrapper_conf.h" -#define MDL_UPDATE -/* Function: mdlUpdate ==================================================== - * Abstract: +#define MDL_UPDATE ///< Ð´Ð»Ñ Ð¿Ð¾Ð´ÐºÐ»ÑŽÑ‡ÐµÐ½Ð¸Ñ mdlUpdate() +/** + * @brief Update S-Function at every step of simulation + * @param S - pointer to S-Function (library struct from "simstruc.h") + * @details Abstract: * This function is called once for every major integration time step. * Discrete states are typically updated here, but this function is useful * for performing any tasks that should only take place once per * integration step. */ -static void mdlUpdate(SimStruct *S, int_T tid) +static void mdlUpdate(SimStruct *S) { // get time of simulation time_T TIME = ssGetT(S); @@ -21,13 +44,15 @@ static void mdlUpdate(SimStruct *S, int_T tid) //------------------------------------------ }//end mdlUpdate -/* Function: mdlOutputs =================================================== - * Abstract: +/** + * @brief Writting outputs of S-Function + * @param S - pointer to S-Function (library struct from "simstruc.h") + * @details Abstract: * In this function, you compute the outputs of your S-function * block. Generally outputs are placed in the output vector(s), * ssGetOutputPortSignal. */ -static void mdlOutputs(SimStruct *S, int_T tid) +static void mdlOutputs(SimStruct *S) { SIM_writeOutputs(S); }//end mdlOutputs @@ -117,8 +142,10 @@ static void mdlInitializeSizes(SimStruct *S) #define MDL_START /* Change to #undef to remove function */ #if defined(MDL_START) -/* Function: mdlStart ===================================================== - * Abstract: +/** + * @brief Initialize S-Function at start of simulation + * @param S - pointer to S-Function (library struct from "simstruc.h") + * @details Abstract: * This function is called once at start of model execution. If you * have states that should be initialized once, this is the place * to do it. @@ -129,8 +156,10 @@ static void mdlStart(SimStruct *S) } #endif // MDL_START -/* Function: mdlInitializeSampleTimes ========================================= - * Abstract: +/** + * @brief Initialize Sample Time of Simulation + * @param S - pointer to S-Function (library struct from "simstruc.h") + * @details Abstract: * This function is used to specify the sample time(s) for your * S-function. You must register the same number of sample times as * specified in ssSetNumSampleTimes. @@ -145,20 +174,28 @@ static void mdlInitializeSampleTimes(SimStruct *S) ssSetOffsetTime(S, 0, 0.0); } -/* Function: mdlTerminate ===================================================== - * Abstract: +/** + * @brief Terminate S-Function at the end of simulation + * @param S - pointer to S-Function (library struct from "simstruc.h") + * @details Abstract: * In this function, you should perform any actions that are necessary * at the termination of a simulation. For example, if memory was * allocated in mdlStart, this is the place to free it. */ static void mdlTerminate(SimStruct *S) { - hmcu.MCU_Stop = 1; + hmcu.fMCU_Stop = 1; ResumeThread(hmcu.hMCUThread); WaitForSingleObject(hmcu.hMCUThread, 10000); SIM_deInitialize_Simulation(); mexUnlock(); } + + +/** WRAPPER_SFUNC + * @} + */ + #ifdef MATLAB_MEX_FILE /* Is this file being compiled as a MEX-file? */ #include "simulink.c" /* MEX-file interface mechanism */ diff --git a/MCU_Wrapper/mcu_wrapper.c b/MCU_Wrapper/mcu_wrapper.c index 49856e2..e6bbebb 100644 --- a/MCU_Wrapper/mcu_wrapper.c +++ b/MCU_Wrapper/mcu_wrapper.c @@ -1,25 +1,37 @@ -/************************************************************************** +/** +************************************************************************** +* @file mcu_wrapper.c +* @brief ИÑходный код оболочки МК. +************************************************************************** +@details Данный файл Ñодержит функции Ð´Ð»Ñ ÑимулÑции МК в Simulink (S-Function). - **************************************************************************/ #include "mcu_wrapper_conf.h" -SIM__MCUHandleTypeDef hmcu; // Ð´Ð»Ñ ÑƒÐ¿Ñ€Ð°Ð²Ð»ÐµÐ½Ð¸Ñ ÐºÐ¾Ð½Ñ‚ÐµÐºÑтом программы МК +/** + * @addtogroup WRAPPER_CONF + * @{ + */ -double SystemClockDouble = 0; // Ð´Ð»Ñ ÑимулÑции ÑиÑтемных тиков, прока проÑто по приколу -double SystemClock_step = 0; // Ð´Ð»Ñ ÑимулÑции ÑиÑтемных тиков, прока проÑто по приколу -uint64_t SystemClock; // Ð´Ð»Ñ ÑимулÑции ÑиÑтемных тиков, прока проÑто по приколу +SIM__MCUHandleTypeDef hmcu; ///< Хендл Ð´Ð»Ñ ÑƒÐ¿Ñ€Ð°Ð²Ð»ÐµÐ½Ð¸Ñ Ð¿Ð¾Ñ‚Ð¾ÐºÐ¾Ð¼ программы МК +double SystemClockDouble = 0; ///< Счетчик в формате double Ð´Ð»Ñ Ñ‚Ð¾Ñ‡Ð½Ð¾Ð¹ ÑимулÑции ÑиÑтемных тиков С промежуточными значений +uint64_t SystemClock; ///< Счетчик тактов Ð´Ð»Ñ ÑимулÑции ÑиÑтемных тиков (в целочиÑленном формате) +double SystemClock_step = 0; ///< Шаг тиков Ð´Ð»Ñ Ð¸Ñ… ÑимулÑции, в формате double + +/** MCU_WRAPPER + * @} + */ //-------------------------------------------------------------// //-----------------CONTROLLER SIMULATE FUNCTIONS---------------// +/* THREAD FOR MCU APP */ /** - * @brief Main function of MCU app. + * @brief Ð“Ð»Ð°Ð²Ð½Ð°Ñ Ñ„ÑƒÐ½ÐºÑ†Ð¸Ñ Ð¿Ñ€Ð¸Ð»Ð¾Ð¶ÐµÐ½Ð¸Ñ ÐœÐš. * @details Ð¤ÑƒÐ½ÐºÑ†Ð¸Ñ Ñ ÐºÐ¾Ñ‚Ð¾Ñ€Ð¾Ð¹ начинаетÑÑ Ð²Ñ‹Ð¿Ð¾Ð»Ð½ÐµÐ½Ð¸Ðµ кода МК. Выход из данной функции проиÑходит только в конце ÑимулÑции @ref mdlTerminate */ extern int main(void); // extern while from main.c -/** THREAD FOR MCU APP */ /** - * @brief Thread that run MCU code. + * @brief Поток Ð¿Ñ€Ð¸Ð»Ð¾Ð¶ÐµÐ½Ð¸Ñ ÐœÐš. * @details Поток, который запуÑкает и выполнÑет код МК (@ref main). */ unsigned __stdcall MCU_App_Thread(void) { @@ -27,13 +39,16 @@ unsigned __stdcall MCU_App_Thread(void) { return 0; // end thread // note: this return will reached only at the end of simulation, when all whiles will be skipped due to @ref sim_while } -/** SIMULATE MCU FOR ONE SIMULATION STEP */ +/* SIMULATE MCU FOR ONE SIMULATION STEP */ /** - * @brief Read from simulink S-Block Inputs and write to MCU I/O ports. - * @param time - current time of simulation (in second). + * @brief СимулÑÑ†Ð¸Ñ ÐœÐš на один такт ÑимулÑции. + * @param S - указатель на Ñтруктуру S-Function из "simstruc.h" + * @param time - текущее Ð²Ñ€ÐµÐ¼Ñ ÑимулÑции. * @details ЗапуÑкает поток, который выполнÑет код МК и управлÑет ходом потока: * ЕÑли прошел таймаут, поток прерываетÑÑ, ÑимулируетÑÑ Ð¿ÐµÑ€Ð¸Ñ„ÐµÑ€Ð¸Ñ * и на Ñледующем шаге поток возобнавлÑетÑÑ. + * + * ВызываетÑÑ Ð¸Ð· mdlUpdate() */ void MCU_Step_Simulation(SimStruct* S, time_T time) { @@ -50,9 +65,9 @@ void MCU_Step_Simulation(SimStruct* S, time_T time) MCU_writeOutputs(S); // запиÑÑŒ портов (по факту запиÑÑŒ в буфер. запиÑÑŒ в порты в mdlOutputs) } -/** SIMULATE MCU PERIPHERAL */ +/* SIMULATE MCU PERIPHERAL */ /** - * @brief Simulate peripheral of MCU + * @brief СимулÑÑ†Ð¸Ñ Ð¿ÐµÑ€Ð¸Ñ„ÐµÑ€Ð¸Ð¸ МК * @details ПользовательÑкий код, который Ñимулирует работу периферии МК. */ void MCU_Periph_Simulation(void) @@ -64,11 +79,11 @@ void MCU_Periph_Simulation(void) Simulate_TIMs(); } -/** READ INPUTS S-FUNCTION TO MCU REGS */ +/* READ INPUTS S-FUNCTION TO MCU REGS */ /** - * @brief Read from simulink S-Block Inputs and write to MCU I/O ports. - * @param in - inputs of S-Function. - * @details ПользовательÑкий код, который запиÑывает в порты ввода-вывода из disc. + * @brief Считывание входов S-Function в порты ввода-вывода. + * @param S - указатель на Ñтруктуру S-Function из "simstruc.h" + * @details ПользовательÑкий код, который запиÑывает порты ввода-вывода из входов S-Function. */ void MCU_readInputs(SimStruct* S) { @@ -78,18 +93,18 @@ void MCU_readInputs(SimStruct* S) SFUNC_to_GPIO(IN); } -/** WRITE OUTPUTS BUFFER S-FUNCTION FROM MCU REGS*/ +/* WRITE OUTPUTS BUFFER S-FUNCTION FROM MCU REGS*/ /** - * @brief Read from MCU I/O ports and write to simulink S-Block Outputs. - * @param disc - discrete array of S-Function. Outputs would be written from disc. - * @details ПользовательÑкий код, который запиÑывает в disc порты ввода-вывода. + * @brief ЗапиÑÑŒ портов ввода-вывода в буфер выхода S-Function + * @param S - указатель на Ñтруктуру S-Function из "simstruc.h" + * @details ПользовательÑкий код, который запиÑывает буфер выходов S-Function из портов ввода-вывода. */ void MCU_writeOutputs(SimStruct* S) { /* Get S-Function descrete array */ - real_T* DISC = ssGetDiscStates(S); + real_T* Out_Buff = ssGetDiscStates(S); - GPIO_to_SFUNC(DISC); + GPIO_to_SFUNC(Out_Buff); } //-----------------CONTROLLER SIMULATE FUNCTIONS---------------// //-------------------------------------------------------------// @@ -98,16 +113,16 @@ void MCU_writeOutputs(SimStruct* S) //-------------------------------------------------------------// //----------------------SIMULINK FUNCTIONS---------------------// -/** WRITE OUTPUTS OF S-BLOCK */ +/* WRITE OUTPUTS OF S-BLOCK */ /** - * @brief Write S-Function Output ports to inputs. - * @param disc - discrete array of S-Function. Outputs would be written from disc. - * @details ПользовательÑкий код, который запиÑывает выходы S-Function. + * @brief Формирование выходов S-Function. + * @param S - указатель на Ñтруктуру S-Function из "simstruc.h" + * @details ПользовательÑкий код, который запиÑывает выходы S-Function из буфера. */ void SIM_writeOutputs(SimStruct* S) { real_T* GPIO; - real_T* DISC = ssGetDiscStates(S); + real_T* Out_Buff = ssGetDiscStates(S); //-------------WRITTING GPIOS--------------- for (int j = 0; j < PORT_NUMB; j++) @@ -115,30 +130,33 @@ void SIM_writeOutputs(SimStruct* S) GPIO = ssGetOutputPortRealSignal(S, j); for (int i = 0; i < PORT_WIDTH; i++) { - GPIO[i] = DISC[j * PORT_WIDTH + i]; - DISC[j * PORT_WIDTH + i] = 0; + GPIO[i] = Out_Buff[j * PORT_WIDTH + i]; + Out_Buff[j * PORT_WIDTH + i] = 0; } } //------------------------------------------ } -/** MCU WRAPPER DEINITIALIZATION */ +/* MCU WRAPPER DEINITIALIZATION */ /** - * @brief Initialize structures and variables for simulating MCU. - * @details ПользовательÑкий код, который будет наÑтраивать вÑе Ñтруктуры Ð´Ð»Ñ ÑимулÑции. + * @brief Ð˜Ð½Ð¸Ñ†Ð¸Ð°Ð»Ð¸Ð·Ð°Ñ†Ð¸Ñ ÑимулÑции МК. + * @details ПользовательÑкий код, который Ñоздает поток Ð´Ð»Ñ Ð¿Ñ€Ð¸Ð»Ð¾Ð¶ÐµÐ½Ð¸Ñ ÐœÐš + и наÑтраивает ÑимулÑтор МК Ð´Ð»Ñ ÑимулÑции. */ void SIM_Initialize_Simulation(void) { + // Ð¸Ð½Ð¸Ñ†Ð¸Ð°Ð»Ð¸Ð·Ð°Ñ†Ð¸Ñ Ð¿Ð¾Ñ‚Ð¾ÐºÐ°, который будет выполнÑÑ‚ÑŒ код МК + hmcu.hMCUThread = (HANDLE)CreateThread(NULL, 0, MCU_App_Thread, 0, CREATE_SUSPENDED, &hmcu.idMCUThread); + + /* user initialization */ Initialize_Periph_Sim(); /* wrapper initialization */ SystemClock_step = SystemCoreClock * hmcu.SIM_Sample_Time; // set system clock step - // Ð¸Ð½Ð¸Ñ†Ð¸Ð°Ð»Ð¸Ð·Ð°Ñ†Ð¸Ñ Ð¿Ð¾Ñ‚Ð¾ÐºÐ°, который будет выполнÑÑ‚ÑŒ код МК - hmcu.hMCUThread = (HANDLE)CreateThread(NULL, 0, MCU_App_Thread, 0, CREATE_SUSPENDED, &hmcu.idMCUThread); } -/** MCU WRAPPER DEINITIALIZATION */ +/* MCU WRAPPER DEINITIALIZATION */ /** - * @brief Deinitialize structures and variables for simulating MCU. + * @brief Ð”ÐµÐ¸Ð½Ð¸Ñ†Ð¸Ð°Ð»Ð¸Ð·Ð°Ñ†Ð¸Ñ ÑимулÑции МК. * @details ПользовательÑкий код, который будет очищать вÑе Ñтруктуры поÑле Ð¾ÐºÐ¾Ð½Ñ‡Ð°Ð½Ð¸Ñ ÑимулÑции. */ void SIM_deInitialize_Simulation(void) @@ -149,12 +167,3 @@ void SIM_deInitialize_Simulation(void) deInitialize_MCU(); } //-------------------------------------------------------------// - -////-----------INIT WRAPPER----------- -//if (hmcu.MCU_Start) // еÑли надо получть указатель на "начало" Ñтека -//{ // ÑÐ±Ñ€Ð¾Ñ Ñ„Ð»Ð°ÑˆÐ°, чтобы Ñюда больше не попадать -// hmcu.MCU_Start = 0; -// // Ð¸Ð½Ð¸Ñ†Ð¸Ð°Ð»Ð¸Ð·Ð°Ñ†Ð¸Ñ Ð¿Ð¾Ñ‚Ð¾ÐºÐ°, который будет выполнÑÑ‚ÑŒ код МК -// hmcu.hMCUThread = (HANDLE)_beginthreadex(NULL, 0, MCU_App_Thread, 0, 0x00000004, &hmcu.idMCUThread); /* 0x00000004 - CREATE_SUSPENDED */ -//} -////---------------------------------- \ No newline at end of file diff --git a/MCU_Wrapper/mcu_wrapper_conf.h b/MCU_Wrapper/mcu_wrapper_conf.h index f004dc8..2e127b3 100644 --- a/MCU_Wrapper/mcu_wrapper_conf.h +++ b/MCU_Wrapper/mcu_wrapper_conf.h @@ -1,10 +1,25 @@ -/************************************************************************** +/** +************************************************************************** +* @dir ../MCU_Wrapper +* @brief Папка Ñ Ð¸Ñходным кодом оболочки МК. +* @details +Ð’ Ñтой папке ÑодержатьÑÑ Ð¾Ð±Ð¾Ð»Ð¾Ñ‡ÐºÐ°(англ. wrapper) Ð´Ð»Ñ Ð·Ð°Ð¿ÑƒÑка и ÐºÐ¾Ð½Ñ‚Ñ€Ð¾Ð»Ñ +ÑмулÑции микроконтроллеров в MATLAB (любого МК, не только STM). +Оболочка предÑтавлÑет Ñобой S-Function - блок в Simulink, который работает +по Ñкомпилированому коду. КомпилÑÑ†Ð¸Ñ Ð¿Ñ€Ð¾Ð¸Ñходит Ñ Ð¿Ð¾Ð¼Ð¾Ñ‰ÑŒÑŽ MSVC-компилÑтора. +**************************************************************************/ + +/** +************************************************************************** +* @file mcu_wrapper_conf.h +* @brief Заголовочный файл Ð´Ð»Ñ Ð¾Ð±Ð¾Ð»Ð¾Ñ‡ÐºÐ¸ МК. +************************************************************************** +@details Главный заголовочный файл Ð´Ð»Ñ Ð¼Ð°Ñ‚Ð»Ð°Ð±Ð°. Включает дейфайны Ð´Ð»Ñ S-Function, объÑвлÑет базовые функции Ð´Ð»Ñ ÑимулÑции МК и подключает базовые библиотеки: -Ð´Ð»Ñ ÑимулÑции "stm32fxxx_matlab_conf.h" -Ð´Ð»Ñ S-Function "simstruc.h" -Ð´Ð»Ñ Ð¿Ð¾Ñ‚Ð¾ÐºÐ¾Ð² - +- Ð´Ð»Ñ ÑимулÑции "stm32fxxx_matlab_conf.h" +- Ð´Ð»Ñ S-Function "simstruc.h" +- Ð´Ð»Ñ Ð¿Ð¾Ñ‚Ð¾ÐºÐ¾Ð² **************************************************************************/ #ifndef _CONTROLLER_H_ #define _CONTROLLER_H_ @@ -16,15 +31,15 @@ /** - * @addtogroup MCU_WRAPPER - * @brief Stuff for running MCU app in MATLAB + * @defgroup MCU_WRAPPER MCU Wrapper + * @brief Ð’ÑÑкое Ð´Ð»Ñ Ð¾Ð±Ð¾Ð»Ð¾Ñ‡ÐºÐ¸ МК */ /** - * @addtogroup WRAPPER_CONF + * @addtogroup WRAPPER_CONF Wrapper Configuration * @ingroup MCU_WRAPPER - * @brief Configurations for wrapper to simulating MCU - * @details ЗдеÑÑŒ дефайнами задаетÑÑ Ð¿Ð°Ñ€Ð°Ð¼ÐµÑ‚Ñ€Ñ‹ оболочки, ÐºÐ¾Ñ‚Ð¾Ñ€Ð°Ñ ÑƒÐ¿Ñ€Ð°Ð²Ð»Ñет кодом МК + * @brief Параметры конфигурации Ð´Ð»Ñ Ð¾Ð±Ð¾Ð»Ð¾Ñ‡ÐºÐ¸ МК + * @details ЗдеÑÑŒ дефайнами задаетÑÑ Ð¿Ð°Ñ€Ð°Ð¼ÐµÑ‚Ñ€Ñ‹ оболочки, которые определÑÑŽÑ‚ как она будет работать * @{ */ @@ -49,11 +64,10 @@ /** - * @ingroup MCU_WRAPPER + * @addtogroup MCU_WRAPPER * @{ */ - typedef void* HANDLE; ///< MCU handle typedef /** @@ -69,7 +83,7 @@ typedef struct { double SIM_Sample_Time; ///< sample time of simulation }SIM__MCUHandleTypeDef; -extern SIM__MCUHandleTypeDef hmcu; ///< extern Ð´Ð»Ñ Ð²Ð¸Ð´Ð¸Ð¼Ð¾Ñти переменной во вÑех файлах +extern SIM__MCUHandleTypeDef hmcu; // extern Ð´Ð»Ñ Ð²Ð¸Ð´Ð¸Ð¼Ð¾Ñти переменной во вÑех файлах //-------------------------------------------------------------// //------------------ SIMULINK WHILE DEFINES -----------------// @@ -89,7 +103,7 @@ extern SIM__MCUHandleTypeDef hmcu; ///< extern Ð´Ð»Ñ Ð²Ð¸Ð´Ð¸Ð¼Ð¾ * При выÑтавлении флага Ð¾ÐºÐ¾Ð½Ñ‡Ð°Ð½Ð¸Ñ ÑимулÑции, вÑе while будут пропуÑкатьÑÑ * и поток Ñможет дойти до конца функции main и завершить ÑебÑ. */ -#define sim_while(_expression_) while((_expression_)&&(hmcu.MCU_Stop == 0)) +#define sim_while(_expression_) while((_expression_)&&(hmcu.fMCU_Stop == 0)) /* DEFAULT WHILE */ /** @@ -107,25 +121,25 @@ extern SIM__MCUHandleTypeDef hmcu; ///< extern Ð´Ð»Ñ Ð²Ð¸Ð´Ð¸Ð¼Ð¾ //-------------------------------------------------------------// //---------------- SIMULATE FUNCTIONS PROTOTYPES -------------// -/* step simulation */ +/* Step simulation */ void MCU_Step_Simulation(SimStruct *S, time_T time); /* MCU peripheral simulation */ void MCU_Periph_Simulation(void); -/* initialize MCU simulation */ +/* Initialize MCU simulation */ void SIM_Initialize_Simulation(void); -/* deinitialize MCU simulation */ +/* Deinitialize MCU simulation */ void SIM_deInitialize_Simulation(void); -/* read inputs S-function */ -void MCU_readInputs(real_T* in); +/* Read inputs S-function */ +void MCU_readInputs(SimStruct* S); -/* write outputs S-function (disc states) */ -void MCU_writeOutputs(real_T* disc); +/* Write pre-outputs S-function (out_buff states) */ +void MCU_writeOutputs(SimStruct* S); -/* write outputs of block of S-Function*/ +/* Write outputs of block of S-Function*/ void SIM_writeOutput(SimStruct* S); //---------------- SIMULATE FUNCTIONS PROTOTYPES -------------// //-------------------------------------------------------------// @@ -133,4 +147,17 @@ void SIM_writeOutput(SimStruct* S); /** MCU_WRAPPER * @} */ -#endif // _CONTROLLER_H_ \ No newline at end of file +#endif // _CONTROLLER_H_ + + +//-------------------------------------------------------------// +//---------------------BAT FILE DESCRIBTION--------------------// +/** + * @file run_mex.bat + * @brief Батник Ð´Ð»Ñ ÐºÐ¾Ð¼Ð¿Ð¸Ð»Ñции оболочки МК. + * @details + * ВызываетÑÑ Ð² матлабе из mexing.m. + * + * ИÑходный код батника: + * @include F:\Work\Projects\MATLAB\matlab_stm_emulate\MCU_Wrapper\run_mex.bat + */ \ No newline at end of file diff --git a/MCU_Wrapper/run_mex.bat b/MCU_Wrapper/run_mex.bat index ca4419e..e28cade 100644 --- a/MCU_Wrapper/run_mex.bat +++ b/MCU_Wrapper/run_mex.bat @@ -35,7 +35,7 @@ for %%f in (.\Code\PWM\*.c) do ( :: -----MCU LIBRARIES STUFF---- :: заголовочные файлы set includes_MCU= -I".\MCU_STM32F4xx_Matlab"^ - -I".\MCU_STM32F4xx_Matlab\Drivers\STM32F4xx_SIMULINK"^ + -I".\MCU_STM32F4xx_Matlab\STM32F4xx_SIMULINK"^ -I".\MCU_STM32F4xx_Matlab\Drivers\CMSIS"^ -I".\MCU_STM32F4xx_Matlab\Drivers\STM32F4xx_HAL_Driver\Inc"^ -I".\MCU_STM32F4xx_Matlab\Drivers\STM32F4xx_HAL_Driver\Inc\Legacy" @@ -62,9 +62,9 @@ set code_MCU=.\MCU_STM32F4xx_Matlab\Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_h :: --------MCU SIMULATOR------- :: код, ÐºÐ¾Ñ‚Ð¾Ñ€Ð°Ñ Ð±ÑƒÐ´ÐµÑ‚ Ñимулировать перефирию МК в Ñимулинке set code_MCU_Sim= .\MCU_STM32F4xx_Matlab\stm32f4xx_matlab_conf.c^ - .\MCU_STM32F4xx_Matlab\Drivers\STM32F4xx_SIMULINK\stm32f4xx_matlab_gpio.c^ - .\MCU_STM32F4xx_Matlab\Drivers\STM32F4xx_SIMULINK\stm32f4xx_matlab_tim.c^ - .\MCU_STM32F4xx_Matlab\Drivers\STM32F4xx_SIMULINK\stm32f4xx_periph_registers.c + .\MCU_STM32F4xx_Matlab\STM32F4xx_SIMULINK\stm32f4xx_matlab_gpio.c^ + .\MCU_STM32F4xx_Matlab\STM32F4xx_SIMULINK\stm32f4xx_matlab_tim.c^ + .\MCU_STM32F4xx_Matlab\STM32F4xx_SIMULINK\stm32f4xx_periph_registers.c ::------------------------------------------------------------------------- diff --git a/README.md b/README.md index bb55dc6..de1d399 100644 --- a/README.md +++ b/README.md @@ -53,11 +53,12 @@ S-Function работает оÑобым образом: на шаге _n_ он Ð’ папке "_\MCU_STM32xxx_Matlab_" еÑÑ‚ÑŒ два файла "stm32fxxx_matlab_conf.c/.h". Ð’ них задаётÑÑ Ð¸ÑÐ¿Ð¾Ð»ÑŒÐ·ÑƒÐµÐ¼Ð°Ñ Ð¿ÐµÑ€Ð¸Ñ„ÐµÑ€Ð¸Ñ Ð¸ подключаютÑÑ Ð±Ð¸Ð±Ð»Ð¸Ð¾Ñ‚ÐµÐºÐ¸ Ð´Ð»Ñ Ð¿ÐµÑ€Ð¸Ñ„ÐµÑ€Ð¸Ð¸. Также объÑвлÑÑŽÑ‚ÑÑ Ñ„ÑƒÐ½ÐºÐºÑ†Ð¸Ð¸ Ð´Ð»Ñ Ð¸Ð½Ð¸Ñ†Ð¸Ð°Ð»Ð¸Ð·Ð°Ñ†Ð¸Ð¸/деинициализации периферии МК и Ñтруктуры Ð´Ð»Ñ ÑмулÑции периферии. +СимулÑтор МК находитÑÑ Ð² папке [STM32F4xx_SIMULINK](#папка-stm32f4xx_simulink). -Ð’ папке "_\MCU_STM32xxx_Matlab\Drivers_" находÑÑ‚ÑŒÑÑ Ñтандартные библиотеки Ð´Ð»Ñ STM/ARM, но переделанные под компилÑтор MSVC. Ð’Ñего там три папки: [STM32F4xx_SIMULINK](#папка-stm32f4xx_simulink), [CMSIS](#папка-cmsis), [STM32F4xx_HAL_Driver](#папка-stm32f4xx_hal_driver). +Ð’ папке "_\MCU_STM32xxx_Matlab\Drivers_" находÑÑ‚ÑŒÑÑ Ñтандартные библиотеки Ð´Ð»Ñ STM/ARM, но переделанные под компилÑтор MSVC. Ð’Ñего там две папки: [CMSIS](#папка-cmsis), [STM32F4xx_HAL_Driver](#папка-stm32f4xx_hal_driver). ###### Папка STM32F4xx_SIMULINK -Ð’ Ñтой папке ÑодержатьÑÑ Ñ„Ð°Ð¹Ð»Ñ‹ Ð´Ð»Ñ ÑмулÑции периферии STM32 в MATLAB. Структура файлов Ñ‚Ð°ÐºÐ°Ñ Ð¶Ðµ, как в библиотеки HAL: +Ð’ Ñтой папке ÑодержатьÑÑ Ñ„Ð°Ð¹Ð»Ñ‹ Ð´Ð»Ñ ÑмулÑции периферии STM32 в MATLAB. Структура файлов Ñ‚Ð°ÐºÐ°Ñ Ð¶Ðµ, как в библиотеке HAL: - название Ñерии МК, который ÑмулируетÑÑ (matlab), - идентификатор, что Ñто Ð´Ð»Ñ MATLAB (matlab), - перифериÑ, функции Ð´Ð»Ñ ÑмулÑции которой Ñодержит конкретный файл (gpio, tim). @@ -70,7 +71,7 @@ S-Function работает оÑобым образом: на шаге _n_ он - **core_cm4_matlab.h** Данный файл ÑвлÑетÑÑ ÐºÐ¾Ð¿Ð¸ÐµÐ¹ "core_cm4.h" Ñ Ð½ÐµÐºÐ¾Ñ‚Ð¾Ñ€Ñ‹Ð¼Ð¸ изменениÑми - удалены первые ~160 Ñтрок, которые определÑÑŽÑ‚ компилÑтор ARM. - - добавлена Ñтруктура **Ð¸Ð¼Ð¸Ñ‚Ð¸Ñ€ÑƒÑŽÑ‰Ð°Ñ Ð¿Ð°Ð¼ÑÑ‚ÑŒ Ñдра***. Ð”Ð»Ñ Ñ‚Ð¾Ð³Ð¾, чтобы при обращении по адреÑам региÑтров МК не было иÑключений при чтении по недоÑтупному адреÑу. + - добавлена Ñтруктура **Ð¸Ð¼Ð¸Ñ‚Ð¸Ñ€ÑƒÑŽÑ‰Ð°Ñ Ð¿Ð°Ð¼ÑÑ‚ÑŒ Ñдра** *. Ð”Ð»Ñ Ñ‚Ð¾Ð³Ð¾, чтобы при обращении по адреÑам региÑтров МК не было иÑключений при чтении по недоÑтупному адреÑу. - **stdint.h** Данный файл ÑвлÑетÑÑ ÐºÐ¾Ð¿Ð¸ÐµÐ¹ "stdint.h", из библиотеки Ð´Ð»Ñ STM32. (_только вÑе дефайны uint32_t передалны как uint64_t. Т.к. в MATLAB вÑÑ‘ компилируетÑÑ Ð² 64-битном формате, то Ñохранении адреÑов в 32-битных переменных, адреÑа будут уÑекатьÑÑ Ð¸ будут ошибки._) - **stm32f407xx_matlab.h** @@ -78,7 +79,7 @@ S-Function работает оÑобым образом: на шаге _n_ он - добавлен каÑтомный "stdint.h" (через "", вмеÑто <>) - добавлен "arm_defines.h" Ñ ARM дефайнами Ð´Ð»Ñ MSVC - добавлен матлабовÑкий "cmsis_armcc_matlab.h" Ñ Ð²Ð¼ÐµÑто "cmsis_armcc.h" - - добавлена Ñтруктура **Ð¸Ð¼Ð¸Ñ‚Ð¸Ñ€ÑƒÑŽÑ‰Ð°Ñ Ð¿Ð°Ð¼ÑÑ‚ÑŒ Ñдра***. Ð”Ð»Ñ Ñ‚Ð¾Ð³Ð¾, чтобы при обращении по адреÑам региÑтров МК не было иÑключений при чтении по недоÑтупному адреÑу. + - добавлена Ñтруктура **Ð¸Ð¼Ð¸Ñ‚Ð¸Ñ€ÑƒÑŽÑ‰Ð°Ñ Ð¿Ð°Ð¼ÑÑ‚ÑŒ Ñдра** *. Ð”Ð»Ñ Ñ‚Ð¾Ð³Ð¾, чтобы при обращении по адреÑам региÑтров МК не было иÑключений при чтении по недоÑтупному адреÑу. - **stm32f4xx.h** - оригинальный файл "stm32f4xx.h". - **system_stm32f4xx.h** - оригинальный файл "system_stm32f4xx.h". diff --git a/mcu_test_r2021a.slx b/mcu_test_r2021a.slx index ddb0e2478a4592a8d5cba22a94153df64b551217..85db8b97a39da249d606acd80e38d219fe8fb146 100644 GIT binary patch delta 32671 zcmV)KK)S#1`2vsn0<2xs5D6dnrv$m!f8@>a>|^Zjl_%)(abCKIZFD#7Pc zi}V2~*Wl#Bch}HU{GszaxxUF)D2rmFcp600fL!F!f<_ZMo4zLa$NAp#R4Sd_w!~QV znJQ-N+WqjRgyO1cncw1hHqp!fg(Fcw<~fP!Y(dH5EZkr)1kkWA+kMO8aN1oy3O&&8 zWA@;D$ylWz+jfAv>Y-}lCgs3_7PAt@># z-JODTcXxMpiJ%}UAl)F%q2bUW(w&D!y1Vn-#pgZl5BE>FV|;&L95|b^_u6aD`ON3F z_BuZlS$97Jf zGhXhogBuBhiwia}y0IxOM4XDoMiC!r@PvdEUZXT$a-a?j9Af-=_M0=HWAobM>Sq%7 zCa->%h@mY1Gzq5gOY+Z4f0CIf;H_700~o-8k6)fOfVZ;{ zu(!a$AVi7(JNSPG|L@@cKM!i4y1f8zzohWE-G@3lIW^b~t1Bq9Da-Slw$T6Y6K7AU zsHiw>rX3d24?8dfZCtg#&wm4-c>YreADp5z@ac=9>6+rNcXwihM6x7y2^mWx#TTYM zy5RJ6f9QREgqls$0mFif#%C5NI=b{9895cSt^W=WhyMP}BP>#*)9_n7pA{R+uzzpH zZNW}Ias-?_WcMwt^f2d=%D=sm_EE)-(VWSxb4nUoG?`Qj5kJ4DV($x7C{Ip_3Lxwk z1-{(E{|&@E{msJ8#aM1+fl8(l`-0y(ZrP!~e_NZ$&GN&674DX*s;Y{r>Sb1=(FZ42 z*H6Whh$AB-LW+vVZ!aZKaqaBvG_zhZjH0`S~Ti{*Ky@FWAmAGSNJh; zX8Mn120_6n&P9(n$yi~eMp}pkTe2J(Bc06$dRcK{Vfy%Z8oP$xXj=8N0+pXJO5FoV zZeVgA?ly%F>boNpbG$f0>=qlcvaqD3e`)>Tx2;vyu-5Y0DeTv;Wt^P&($fX%>LcD! zZoFMyuIlaY7tSy4={(#`)X9HkdF@?bgAXX)>gAj8sR4`tyg$>cvrVk9R^I9qZZ}Wf7O3_ zd%txAUuI3tGC6PftgISS)6*NR_p$pNcZy$KKd*3DR?5z~L@c)$l|}G5YS-6n_Ts0K z`577WqN4gKo&#ql`|Zg#qn;dtl4cDlL5^s#JMB0fF6%RHlbeD$7&hDNi_ zff|Q0$jH<*qN)mIecd!DcsRSZe-_EyTwO{kl!*ZKH9r2z_O`63=o>pbQV?ciTL{UQ zB{5VA`=(>*qM{1hRB-H7I9{_E@OiK!`U0s;#^pF0ohu`!pmHMW0izsV^? z#Z7ac5D~GHlE$yCvuCP__%{Ct3eqwguI=b8JY__tuOWi#={??NmkCRff1pp`*RQ=p zLk4}nw!;b6KdGuxP+dMQMN#J>R-|cvygUzE$ z;^{dP^!@wl{=T%IA9`FIF37V4o9UUE<$wR4C4R}fOwlXbyt}Tty16lC*QSJ;C%X4;NgRE-e)j}e@RK|$QT*l^7Ao9N4=3>5)6;#ya><>*ZuLyoQ;r~5Y2)O zk01i6%G&zqk}Mc{sWD;2USFRyF`<$LgE?=HJx6@njYGg?Sl-AW_EB719Q@-G zg+i4H7z{c?NmJxXQ6KVBTcs$E{4($U-#7fO%!AHf=Wb8=IXQ7&f4rb7Dxy&=o@8TV zGhkwKo9+ohj^*;b;R*=A;c{nqBQ9=UQc?mE@aCaIE1Zom;`#M;{WGMQfl^CPn-XMbj7h}i5I zf=gos!)P1XxzDBFR(iG}?<>7V1y|RMtdaCjrw?Cn5yUR@^LksdL zzxZieXD1pNnIIb>ij>r=2b%4QD7Ml>}w>_BMHf1RQ_CDirxqaq^EE-o%~ z(c3#PHv6>GSr26sMP3Au;?|(&jD~1I%x0^THf~dbdHMN$kD4~l)P&kR5D=eI8L%XQ zscs`a4X!58#ADEz-KlMbbDiEAO%{y5c5TFv+ge+;^oi;GMCI#IW}nwnkT(V(k)d-LnHhb_03__lFXZu|7%Z&>rlW{dvS z&e?S>Ew%R7E_#=p)_xD`3`>C4mt8N_Ufb*I`>W94=7@W{T?t^Nd7lm@AfxQw=(xDJ zumQm`r=we2DTv%U_X3GwX=C$uVIeI!IeC}Iv#i7ae~qhs>pP)hxQef(_($o}+m%_2 zg;Iea?;G+3GO``zJelRwVL|)Lit}Aq?5|&JA8l=CDsv}|Q0e31<5}z%o9v+M#Jabn zR@e5BHKyU7x`7JgrInSH*=3IP^*Ed9BZ;UvbaZsX@jSF&zkVsGs7xGikdu>RuPrDj zD13>Hf5kyVLz|eGP|((v7864f%ZcvliWIN+-tCK{h1m7C{v^Qs@gu+9i#<)-zS$22 z_bh){5T5$;=S7qj&#TSd(W#|}3(kidSnGua8S|a0%CAbN^%(ReaRf4-k=y8`)6HQV zZ0xToDcX%u#VRxc_hYXUSbvGCje<)*n`J@*3UK9uprgB$J+9JC!zunn& z-Ewh#{d$ert6InJ!)NbgDpGf|Jq_u-y*+NvlV|XU%U0x9uZ;SBQE%Ko;jZESJUuse z>77zvU+>}R>1wV0coG_#zVh1IpTFq|GxOMG{l?q>?p>=}No%DHvf)YlGv6;@BAoJ;yUE}HNzilC5 zVejeb2l*6-=H^n)&Rn{p$mETT-eF;3fwqO}?(UwNn(E+szkC+@tbstKKYoGbt%%J1 zb}RhWP%Mg6*4LN6J1XNJtko}__t57He=cpqgTsCa7_KPEeO<1)qBkrAJ^cywT)y6DV_+aTr2k; zes1nJ5n>{`x+E{q_YS5`^YSQ98kg?zv9O$Hs<%t^F7;jXRaJ4pufq2WZFS>3kWyu2$12NGJdqQu0h z<&|S6cc-nCY%YWdDV+8j-~;=$f9%+lozxL>>e7mediir87)sjOBE~uK4Glb}Ounbl zo;Egg(b3TsHCkqaS|gB6NO7?-2;KFzy#FUTIYN-lsa%eTRQVT-ta?>qZxTMCQ-U~{ z4JLnsKp@wwdtF5K&kSZNO*e`;TOMw#yCO;YyCR6Z`3iLqbx}h|cm<3ne+rljRA|m_ zyu>01Wfc{laB$SFZJ1#JC!ncGtp$ny`ju~ff&b_nt!-{D0jTcI?rtFj(r&?)IXSDO zsQ4XBMs02F*7^CwcO@j<8&yDsMIrDVT zLX2|)VyRX=)}rwTZ9BV2e|J>1XJ%&RJvU>4mL|@HMnygUiR{=h-{Q*)F2%f5T3np_ z`}fbXmK_h_xp;aaWR#SF%?$spLgjpoItOy3z$bz2UqDmF5WHiejQxQ_h3(+ru%{-d zR@#(SP>?q+%*}0yFp$pQ*slZiEUtb7f9^j!JKO7?7<0PTmA-hKSo zv%WQYpQeZAv zRcw&K^FF79E!P`@I`uJ;H8t^-mDobxv=&^@%PsZshce{znwnlyQQ>b4Sl(cUMJ|TL z#-cbnRRTHqzEguTvfv@Q*rogZqLN3$*!U?kvp8=m@r07P zYX=b#(T^Y8e|=k{x{Q)Kii(Tdt716;IpR^#ad8W#+Q6vk+P(jdU!%ouP~4-bG3~19 zMUbqf^egKoOBPW#1P_l+V`?84F(*6E?dGaP6NQ@Evh~+Sja_~2X-*j!iGtD!jM4T- zwE50I)g_51$~U*7a>8h05Yd+|B|c)qX;{f4XQOEYF^Wcbl+8$Hes1Ikqoo zHA(3B0|u%#u!XFT<+7DPY9?U21;xdtKrBJ2Iy~HIQpzSvnQfTv?CfYXxR~bKYHDhx z%vDxYPzVa*`@v_A+R+g7%X1yl44spZ7nIl2LuY1wF%ZU8*XXUFk+@`; z>7EbS5Pm;7smjIU)_hk?z@42vg;;K*InF*LolyE2qLxCHSDR{~rK$NzM~5ylQf>pe z1SY4%P8jj)*K5ZU6I2xZ#gM?j92q$h#1A9E<$wQv=HurFC_q6$@oiv0hM0t;e|K<@ zLO=kt5o>|_YD*SrOH1n9+}x|HD^#blVCZNLzb5p6^j|Qt`)b!WCOaL8;Hr~gZEaz; zR{dnS-J33O&Cj2!8T@^0HHs&#fTSZ*u? z15+>t8Rdr$L0}-lA|ky51Ak3ee+&%`Kbe_r7`S^+D;KKlliHq9vISdd8(CObj6jQs zsXpuXVBKKWy4j91&E!N0%+-JmDkvkQ@v$iz@QKOZ^ud05_p1Q$~SM1}c((wVmef4outtO4`h z=3?);&HUBdV)Zhzy;7ILDz8%`i=QA5TpIEO17&lqydz~_jtU|oc434u;dcZ+yJ0$- zTN3Cf(IhDgnn-VI(s}nTp2>2o`pHflrf^8sXGC9uL{@W-6b{!WLS^r<@$q_>!c(Vg z;g=ql3+l(0m-{X$Fnxc(f7FzY=R2w#_I^$M9J@RJ;%Kvqv^H%!o#FD&;OO_4X$Jbr|+x!|2-lPUoNt2{5%lmzj|Of1H7fK2}GAOF+FdKInnsdV00jTFP-!o!6)4KSB~awnp_-)YKHT zw8G`o%}XD7*1^rKeZ0yxI?;Bnw!-(;4dLYE3Sn2mB+PcxU3^V z-%r@kP~dXDs(#oOnVFc4gCiz2HN3S|use#3>izqiNnj%mfA$s{@u{e&Vq#*n_}#Wf z$RF-D1*=?lr$`0u0jUEk2c)aklkWZdr=Vgk4wr^skomN&bcPK^iHeCiU7wiR*w{=r zdvnH8$=lVGWn_@Ky1FVMc?3lZ*^~3~1_B9tg>ot>DfzpkzV3ww)f3zwqOOwfl`x+1n3d&#=PV0nj2Y0FE z_XC|`+tn2#KnBg-WgWe-;xo1TjC-@^_NYiAQJ45ef0?QLDQ(|S3N6@@{VW;Zy$cBs z@AtXghYlpM2IK4dVDa+u+BNQTr29X3+O^bMMjZFXQdM~z8-Zy90TC;Mo%ZWL#K;R= zKg$`F5D|GQ9z|;UaCg1nckmsFA3)mcVD$avDeaW+(@>ik36nLndH1C#;DGWP8j`E4 z+0y-Pe=JFTjy~!69E$?f14iYum{_I#l7Nqo4`^3Lw-@_OH#^0z@$rq#&ASi%E_waH ztzGu-e)#?Z`3x^y?0rp*Z2xmD4GrwquLriryP1>1LH|Vfx4qplkaSA@vB!9-ls)$@x* zifgv3Z(vjzK4Uu znwp!JTTMpYxY{}hwn|UW%s6fgyg6uv`=xtsyirnCuD@LL=62nA4XEJ5hYyKRc(>p~ zfBX9=zOT8t6#BmBxB&qH2!OZFw>;_TA$7Z@;vQGa`Nx-JFWMkbJJ6%#M=jWX#m55{ z{gWjUTu@eKzS}%H2 z6-_!cO69K1*Z)R`l36HaXoj+gQ;^m9dS^%< zi~r?<`&LUC()n_*e|NvMsHv%Ef3cvQ-4Mi1U0vO^QQpqZuIcCxN{MbGm}w(tf475q zNkc>O<5`O6zLBi`+Znwab zNlgF;6rW5szU@MQid1Vm*HvlSKi%lgh=7NOM-b7aw*R-Yv$jE3S9f8jf8}DM*X8fh zQU)M2PzxYIHW=YRhqlhWzJC2$UQv-%TZ?BQP%x6*YEli$FjFtfW3`>71LEu2C}^}5 zEkuUowm04W4F%t;S{{f%bTkxIAu5P~*wwYhR@nJ1xS6S@>CrO3bJ|6}TU$^&0IxN) zwNIn`?{WsYcj&ci6a8C2f5u&%jR)G!^1IS}4<^+DxW)d$RZb4Q%6u5e@bc zhQL*(C!&588j)XJ{K7Ef&-wXC{NP7xBP;7#c0=(U9r?`A;CyFNiCPZz4VnKPXRSRv zBv)F!!n7X+c3$7#A9ibMS{eAF)o?hy%wwl8<0&RSzPOzo19X1ue?t1G$@8?Jpy1zh zh4J+Cbh+RCjh;UG#@fX3=bH1~gp&znMnu_!(f!$)Fpz;*cz9D*yf0q7;INq%0;ZbQ9)N&%2I`RAy*1|H`<4OCY1+SYJ;_q#**17m6Fegdtm6pyr*ms(@7 zcU(fk(LPk)(A0Ete|Hm!%m0B6e(7)T46K!QEuS2iPhi0J?HXOSmEsw6`}!GMQSZu2 z9Nle~9-=+%BBdsei%h$t#AAOt#M~ath0EcK%F3dFkJutEjE+Xb^t>a0iF5|diu6+a zV*>CXD-F)BuD0wS=5H#VPEUVGDI2ug21MJ{7Y8*ohe4$)e|>z6kWo|HlG#(Z9RBG) zd-lx0-hL^cgExEBVxYBO@ZmV$&7bkh#KZ?u-!m#=-dZxC)qH$>vqANkY0*N5S&4~H z0XVN53Zl!)ld-Tc7}`PrJ0$eRb^s^%XK*l()m#o6n#$juO^v|C^+#ryEwoT0RvI+{m z{QSuTP7jiV1nCA4#G^WDHoDP^ii+ASwWR(2{UP1^fP2yBRQA*jz>7}3Q$=^{DzHbr z+V=Mtf9?zCAu6FbB*1C96z2>U6-lwMGOq3twRMISUfm!8BR}|CGWI1Z>IVQ1!08#< z+slKNn82w2xWGC7P73Da{ z+q2fzOpMH7Y&M+!57_hbVj#yO<-K9Sw$9HjYB(Mj zsX=IbAImI`7UuHicM6B?%4(EgUPVQ8<3U3hbjdG;vE?dTH4_Hg^>RtGt^y5uJa6!E zxlU5X2F`*{o(ymRI4&7aPwK@*V{W%S-p8duuQN>U3t!d$cQ1gZrn;kxiwXSUo*+W3 zf3m6yuu|LLU<6>Lv9Yl)d9!P7Zf=2N@R*nrJBSz_CMKeb{W^=bcCg-M_taF@Tyc)= z!i^KOmYzBqx$=F$GcOEwbsqo&cW3#GDTf#+D2Fb$@xUL6iUdB~_RHN3Om0n;wZfWY z&Er;*gPA~woK(APeYn|$*xlaTuzH@Hf64i!Ts(gkzWEK`?`a#^!^rAF=S$%4K51(H zsQ;7IZt#}Pg>Z6ma&1kAl7Rs|upLAT|8boY+j*{P zJaVl{lSu>jPpHb+TY*BL$5<=sYirfc7^sC-K@aaozY%zXm@IE_yt2@JsB39Se+Lw< zQDr7uOcRP=+!ap#?%hhmrRqzH*s(I<5I<*I2X~hY%xris)(z9+B1mFlBI$l?baX&Y z4!q4p;wAatpYH<%P`A!+NC%%Gwdm();%Q?(&1X!2#Kp&-OdCg`nOp`DI0CE-I6B%M zNZ~9KzxD9&kl0pd&b)D&ne8U?e;)uhm1|Onc`t#e`*M`3x!wknnF+9%D>O6|2T?Q`CA3=DR!adAP;;Sdvt>XmT{x;y7`0X+iVSVCHwoQn(9+Ip9i9x|Ol zNO-29bpcVUCE)gQo|y%-6j4cC4;L=7t_`S~S92-ys z>=w3HGd8x;e(;rmT`aMlFX-13=a>Vo;?ev0uqIRAulBr z`tsGQjrn?$%$EF_M+`6MkZ``5K2Ty2uN5<6mpGX z@7o+{{U!qG%!|b8{3waL)um8JouM=e3u_C3CXP^hj_mtcJfr@gI9YSYAm@^t#THw3 z_LS3Fj~`IAA5~Q-e*nEIs;at2N0SByXcJ|`ii&8y&uJ@))@5NT=6zx;4Xf21V1+SmK>U!tZOw3Ia_ zKxC8I3On4u+v=f5(RoB&c%Uz?K>>{q@z=>AygEOn?eIlU3eLtpslGAO5KTuKWK!xyyU1T1sk5*DLzkV~FzC`Ohr~M!le-jZHkk^pP%CCR_D*M`P?o3L9 z4i%c8;fM8w-}}O0Pva}-*dig%ZkWo=hoNhmo0k?D+1bK*^7<@7{Ma3xone~_g?$z_ zHox=o@?iU1-0f5uP2w(RdVY7S<{sO*8CawYr?f!?QjY?$-mhM6IsUzr(}tX%Uzetn zI;7Wxe?{NXz;Lt*UQ0ni;d6g(heyA2zpjjnn|rr{@4vR_4F#=I-DbWHE3U5=wvSAH zlL72Whmg)ZGpUaQ+Tx_j!Tbt11K7#qO*46gFB?Bh5N}Cz_ zfBV_e;9y$78&%3L(wLKEmJ*QZ&2}aV0fjO7-nc}P2}ZWI3UYIETd>JK;kF$6prfO6 z)vsTx2s)ynA?cFODOzNt+`QY|(}Kw~{q$*Ed3kxUDAMswmWXL?{9e1^PpI?zFydWcIs@xZU|d;U?LJ-& z9@*YeC}!X2wrjL~KcaHu3M=);A!)|{0#YXY&1ytk9J^4NbSvWB24`#g;2@-<+gqFZ z;O`HDTH9Nc$3?HoxRo<6e#+P%)6*I|yStJyGA6)$?=3VYTwQs9#{3ckqkC~Ne?2@L z6}0U7)kt2ToqS~eKGFBLm$9kyDl3q0D3Y5UiSZQ8Nnn>jo6@6`L zBCgh=H#N=O=q|-2CYF+uqa0E3e=Tijz|Mr_>OYZ7<@%(kh{d@u@qp=MPun>;HFfkC zM|-B}I)C2#u#fa`DFYSh>G}Ej^y~xElYSGHB=~>NQY0iK{{8)d1F(R}apiMSadAa; z_203v80XEQq^EPUv*^6M+CDya+@2>NtZE4LmxT8AZ{29xIy=!76xGxgfAZaEX!|W} zCRYFb3kAeIHFeQ+J|*tqeS31yXn#?-|G;6|hl=b>{vGqbyKx=O&U$Qs)i zE8E|e-iC25dgM^)9@a(>krDrN^WL4c@}Y?<5-nVq18`2KS^0bN&s+L?K#H93y+grt z)nX2ZCEs$>el_44n9ai7e=}~c7QI`$V6X&j`~A7URSS(!$LkZ(jlssGk&(iAcm47E zFge7az%JZoG z1&}xISx>R7*VtRx%3*j5Z4l^%pVRzI74q~P@4v$(7oIF&J5NrWzy}*^TH6hng1w|c zIBK+H9UYlBhcnE_e|}4vn3!N)j90@fh{c+i1(0giTFtqh@KTsf~aiy}EvW*&t8C?Y!|C zfEcU$LAIa0_g@ym>+y_-px9U(MMXuMxmq+pNx+74c^tjHf4w|32UP-bD}+GS?=P1& z7u=UjJ411SxrwD!FJ*Gu(;y@yeB@AA>jQi1&14x5>e_I)ywqADJhe^4|9kwl%hM+h zvMy)%2oqCNf2UL0@F;d`4y-ra8O7>lF+YE{(L-GhrN8!?0C>rk&E(|uymP+?Ss=c{OWGeaejq6Qlx#Q~nf8G)tmoVbFnwl;C^>)t-G9Mwp z`tkAJo-04_9bNVo@e2mA_A?xzFtFHJ2oXHEG!HK85vn7g(Kn-$~;z(5uZNwJfBnt|Gt`H zpWKI-5Qm#JJ{g_p(a`art|F0DlqHAgOP~R@yU$b&t*Wm6Gc<$_6j*GWLn2wAjc`EZ zFB%$J!K4*iavn5Z3u69oM=|evne!S?@6Y&ne=IO??pN*kuw7nM`#7m@T97UaHX~Eh zZ@nhjSy{joBiPv308hjwmV*Uk--U++L}Wv{IQe$A(*C~l&r0yJBQ32pTXG9(0;ds6 zfS7TBR4#~L==tuU>BZhRV*UpFSV>d6R=^6NoVvo_h*(-84-GM>sQmI5>=u%>wT-xb ze;ug>**VSigjtd9msf1xo?l8i9R1@g(W%et=tlc4#>d|b$m`GIV!ID~GsAzV!Ig;V zIg*l{b$=Fyz`ss>{k1?00fXHs2p|0JbZ@#MP`A;|v7a7#bPm%$JsX$LQ7SBlLc77; zLKnSIKq-od1YS4mtE&g+Qg~iU? zIpFWe+W-b0RYk?`YQ?5Qsp|u&^_hdKGc#|R?k~tZfE_@XZaBxM)2g2Jd8VXa)-kJv z(pIXAZ)sy=vi#>8$@f|<$ib8sY;bcD)IY|T#ztN&EUbNW_a%S${e~~%Q>qHDfAc)M zyN!j*5s~w~>0|EF(gQ%Xp#o_2hf8qg1P0x=EKX=RRC3I%en1^T)~z0r^%zGrBeqo- z2Qv{6N=kBffEkdH>U;C*)d}dR9{&Q!s{G+FI&HTX`hM4>0s^aA-z5AcWcUV${U2WZ z=`cUHZtRGIUTSnjplrLOr13^Uf9n}JVL@Ri7BzzNP@~RQ52qRMa;J5vma7#MBV*$v zPJ7a+si}c<{uGEdw07k8h7y*?yTSTdH^7EU&UA>3eusJvu+9qNWC1`z0YE z>iXs2pFh}CROWbe8eimK_l7qIp&^Oy4F!Za?B;taP5T|(+%|y9iI%~hI&2Ii$+aE{ zoDQ%ydkJuIx>wV;Dux(Je_{ocjUgP0a8g+(}3Jx!K+&VZo{23knQCW!%(q8g^k2pCVM|VMLU5akblJxjEh}X?0 zGDH9E#RdAa=g*zbw%oVQ&*?PEe|`O`qog#%uzqm^5oK9p$cVR=JfSRIXOEImfioyCnE>7z)Eqz z_crk-%uEbsDnG8Qe;}PWK^LPwhYZb3PygH9Mfn1R>DmtiBdUETh5!kK6CuOzh8lsH znb~HsDe1jgo50#Sy}fq`jgX#9+g{ZU-Z3-Db^^Q38k?RDfj~&=>t{^N&6QMs4F@5|GX3wNkjpF?K0bb5e}7?7(Vx!FZvct= z%DDYO9Z<8dl)Buy+r&pZ&hR~f2%f`!dOK^6oXy_e+^npxiwX-P0^!HNzyQ{IboYFE zZVqTEe?aw2U~+bLXj~dvRGo=F0=n8@z zr~sx9w4JhPJhASJo`K)Lf0r|N4=bIVXuC8Y3EE;8edgurI_@7r=HhBH!xvp-KFo?K ze=Z68ey#9teVzC1zFY>Wq%8{DwsBZo3Do};13CJ^)uY_;6_ z4W(fEW`_uICLx(!RBq{y=MV26KRzf<0w9-~D)S2E^bNZen-&BuJzW5FN7wpyX-dEo zo^%oUi>%HPX+x={{%?}e=gvXKYNAjlBJ{XJIOY4yw*#=Ve3T@A@;Z( zmzX%UXK09kIe-+C3H0zR$Li8?_M;(Qc(B^;2SbLxnArtF@Y^MLTb-kE<2(a3^$*?y z51Z+rPnLy|?u*ye;f&M`;F&gjfq5sy{f3dNc z6Jn{16WJ_j9+!#$iw@ep2EQc=`Xe74z%G^Y=InMetPj3n-b*V62mmi+7bii&>*n#y zv#Q4WkZ6wqH945n%D>Xs8;2~8lARq{TAEf$It+l??M%h0^U0|*(AN)KT)#?6Xkq*V z-!MfIvJrJZYWE|kdnJmDul+43f2bkmbqnbTzBDv84opa3BqcQ-*+z1A%EC0-dV?LX z$X2b<9YewCyw>CQxEs%6i_ORgz0#l^JCZC)ELSP(e+zU{Mk|(g_uYyrDh8zu9K=&m zc-d6R_#KIy_KuD3v7H{YUXG6ae0g?q!m=@_J-~a|)V>d0vTXT9%fUfNe@ja{l*%nC z)W(%3^W$Gzz{2B-G@v};$932pEpv1-0T~mMweu_0*ULFki_0hLD0~;w&LDut&CyKn zMu~F70y#se+Gs;I@w|r;5vXwI)DRhyqWFkVpA(CFD1OqrW+wHU25 zWbMEAa&~eu1U6F93yY6%K%S;@KP_M*o-a^D0l1kjG`#o`lE^x(`{W;RJ{0Zk z0lIeXCu@@FJ|_uWJUs68`?O_uiS^En5BJ#E*q#s9>W%XUJCiPMdskHC2Rt{J?V)}QjnE6j(}IWCvH51R+lc%j3Fe~Ww>`P$)PTSnE#Z2?dD zj{o974!p0HgMn%eB#p!2`G8t2ZT8x&RE;E*R5Gb3D2`H=boQMZ2L@0D zbK~Ps%KTgO=2Xzqk}@XxQs~B_v+bsBXdswQB3l z2KNEC<#cfHfAjGpT%bE&Rd;kQInQ(Col_sF-GWJ2)C1d9kU^eDo~ zWj~&@$eo?q{tYuTvz4{Azh9rDH256!^mOu_^oa0Xubr0YczPFiU+mBI4yD0`A!=EZ zwP{sM?gyU*9@sOQkNZ&$8v4VEzM&|vvz3oEuQD2M4y76Q$J5&$ z=+{``f@!AHUp#NZGB@Xxl45JRnC0c-;;QwcZY0w-fM!^j}Z(e|x^md1u|yI}1z8A8Bc1=jUh(TKpAF zO~3m3`apz5Qh<1c+jw92Ocs5e&6Tz!<|MTdf#GPz9B$+K z*LA&5RN&TzNL4lNvna&EJtMxdvT{JMyR$PU-LG^IOGi$Q();otv${I*1=;+xY0CSV ze{4}sX6q@$5=afmZcg1`(ka&f5_5C&)U>&DG0*ilb&s3v{KwaZRF}CK*DZ2#!=NA+ zKKb_ketasbm*}J@3j}Bm&dwc+E$5%Rx=Fpmfwco|4tOzz1lzMUp0n%I1O?@Bw`U@# zjM!Vk%tgh;SEEq}EK4mO$HdC{Lnhl}e{p*=B-4Ka_W!Y81nR-0ZuAY&03*Qg^RcGXN=SL-q?KSmA_b& zGKmw6x%wI2rT0l~=EIafqa8gnfBhy6ZQ&2Pcl-AKYw_Asv^zR>pkym5D)!Nv5pAYN z&hNsk7aY4ubmc;MJx^p>Yc%!r1m0Gqe#7ioawT(uR#oNK)+URF*{vKc`+`s^tEqhj z0};z%PH=sG139zyZff#zbSLA-Y+Whe+}rCbQWad;&eva?F()I~J2=zQf0=g#wcEKd zD9FA9(809RytmD_^}9Q6BtS*tu(9yc6}YcHtQz#cor4S{;Yb?%yYjPEe#v~I z0~7K;8_lS0@ZC(q0FJG!#M=LtpRHzM7KOUH`{Q$NMeX;GrzTPoncAo;2vJqwrknk8#`MMd z157vSXe}1wvOeRzq@`tkLdIqBM*o6$anY*=$5D~i==!+#!#}Sl4&)U2LzQ9O4j9f~ z_V!RWhV?^pb8#^Qu0C`}?jJa(prc0)BvpmfJL6ZG4N?L!&~LUYe=aEr3JKv3`YyM+ z(&=ooaH9=o?Wd$8KWpmH%Qq3&l|}|=aCtj&9wt|-X8?hAU>vZrRw&4ZtC?ZFC&@IO z$mE~xscA-5SBwe^dJdf$QScec{q9#QXJ=n30T+3D=?yQh|t zl%%O^_w;dtbBaBBe@ybMYdLIcr(rS=(`ZdWB{TTjw<=F(n7BeP2ANoKO(Qx#wn%51 zd#$c8l%MnbUr}{8nSWtIvt>qpJ_ZIK)5%U13i(ZNHsZqUY=ib(p^BAgDiz*>vcgYk zB_(13frsho>6ODJ$2f>`ek6;t8BBcZF$Xg;!h(aTaH!-Ce~!j_H)c^5>izgBHxOK1 zYXE`b5O8I6>|nw~zZv@||Ey#MhL*~*IWuIPx)#9SDqodHW3`ax+s7aTf5fBk$F#TxqhUJ;X|AvF@+)3BU~ z0X79!!td-9{oCEmVyE-c%a^~f@CO(?0Liws-tp^$l8o721O)uu$GrfJ_S(7(Go(aB z+K+b3xEp{u3W|z8=UNptD`;wtnvyj)`TPjg>TmIFM0i|> z=?vRUf8_TjcXX_Hjk}%$gMkA7lO^K)xUb=HN1}&o5T?{fu@JPzmIuyf+{LHoy^jyv zJtAV4u`Psxc9+J|lKSfE%JIVHYkiFNDb`@2vbdyNWPVfAYk&A#mj)gk-Gz^gjJZus z6HSaG`%;c+U{Vf_v|L6XH=R-Oy7`#t<=WI)f7esqR+=gz%=?_$7ED?>+XkkS?u&^+ zo*OJSbs}8dMzKO`e6AtBR#o*;2-dL0h+Y$`$;G>C&YsbF%|l&TWtDB%#_8gxPdMdJ_qDNHw)qAAp5bBksAq#|b5;HG$-~~a zw^1GA5E-kgWUA+TvCQ;WdoMe)TZQIVow(U%8+k9gC ziEZ09CQc@{Z9DnreeYL)-S2i)SD)&0dUyA(u0E&sT6^t{rW_S&)c_l$?S4jt7f(0& zQ1#lfL@xodsi>|lR*%YiS2Ccc`}tUytTwQ2Y&OoLAUpq7dS=l^;P!G~OFnjeVEP-N z32)6})l`XLO7q~`P*#TF8>auQ%;NGE6wP!v)6N#V!q-56OKt=GOL}Q#XF_*xmxHeU z=rmo!%*;CJNy5j_GAhOPTSk8fsxpBRVyq4J~&n?iEp#O{I}6Cfjf%h%A5it z;$x#tEn*F{bc0h_^wkN01k#GOwsSp)ZF2E~)z?=P-!=`ryf#_yZ|w(G(9JFYRluq{ zHIg+=0Y3Jk)YM?g>Tr}jex#UX*O%!$PE5Io{3EQJp0i<*s*k&yXES!tBp6_Pl;OXkpG!ZWBK#3iFbA0dr#x_4mw4oe7P|ubp&ZjWesix^+!=wZGx>~esYS2 z1bKRpk4cvuj-z86?^d&PfMf|qDkNFHp<&&%#nJ@>#;p-Dyzv$I{4@tD@8_%KS(>r>q#4My~jWZeKSfhO|sD{Y7_Ay+i|MR+I_}qJ$`1C z8W43q%6n!qcyhR6%zNTFtL8YKDZH@Ve|zguch0rsBkdOuu(0{?+BddrpW5G0!$P@B z4BnOrV3pR#6(su;%|@ZStzw)AjY*axYZV)YkszD&_I%>C;m#{bEAvFM=8>aNBsl z^=f&v>&gw-G8+;ixTT@M!ThqzQ!S<6OCs!oyXa3%u%1p=Q=d_kfLFGd0?<>-06eg6Ji`#vf zp{_1_2uGs9gSdkGwZzYm$xITHl$O@I{(_f_+*IB@J16AufEFR_O3?2gpSMUsw_RPn zdH+o3Fj_97Zv>I1H&DltMQnJEd|o?BoYc1Zmst5M;sO`|%yn&3DnxiL8jBj5*yHlZNi+t(cDs8s;_2{`hJB#*x=rjF%E%~t4Odc@D z_tg0s*dwh3#t|00LD#w(h);qQ1gv3N1y>w^WP$!CtdQ*d&I$*oLY|@4XxT0QBVy7( zRqvgxu8|pF`F@US>pr}(F&!H8lVk`ZwAL^kA7w9L2vt7^{H~~nGdenMMx?d(v(euD z$$w5&vy6)N{bs}6xG!VV=MUti+$2kMY5OzY&+TF&XFrQ`S$Pbz+-JG8w3p2lulc9% zChMnf*((5EuE)gAYdmyigH5~`x7aQASBexKkKKSp zJr@h<0N1$f`hlHGp*S-~W~S-WC+GLz>+ZXUPwnXb+pd>D&H0;7?#%J0Uw6*+=sr$l z1*wsG#q47#sGzdo&mHfqNnG(t3O%KI{cVOwsyKXWE~k3Ray8q z<4;J)ZMHv$3gZD{PsWwFGJ@92VvYCHYc;j{`Iw0wIulZN6K?{=Mk`mrbDUOCmgF{# z{Rt{BGn+BTRZO{FxApZDIa>?YuZ(tO0R%Z+fNMPsU+<0Fec7L+mCdzEIE^f&XC`KV zP&g_s>UgQjdE;y`M@eadXhsB`kb)bDE~<73?VhoqX=y|+Pfud`+^4%6T&O{qSYIr7 z9D*YX1{Z21C8ao1<S|2ln{NmwbLf5ceDI0Q2y3Vy)I zq%>ESF*i3i9aiqnQ3`-Yg_LR-sq-h;xAeOaiex;myR zHyQGCKJN5mvy_uHW+ z>N3^#No!9J=l*q~y1i?c)`C=??dBQ)>szY(Tq#lMal*ajhLG1U19p%(GIADx%i)!x zp+-DwA&;!9w{zh$I~l#nJy{(|s?^hZLN_)xXN%H@u(q20=$weNIW_6S&^~ul)X=b$ z*%9|I58>k?ykg=7L%0K>L}WIHi<uHdVNK35~19?uCb_7Go%wmz43E{^y_@x z2?t)`u|1bLy-O3&$8ro_`J|NdRxD|W9ktDxjv+Uo50Fi?J%BZV<^}*t7^Ybb_AxrZ z$ei&9OMqISnMOtr!YA@So11B5#5+ABI0$(+NsJnFp0qeqKy+b~0Q20ay&gpbwh|dv znN2?P*>QgZglR2U*TW}LKR4|o5pgt<+@pRskAN|LA=8VaU_=lL&@b1%$0}_7MiM7B z*1A|slJPw`kZX2|)3 z+<5SX>@TLy;lCMozKaN|`-SD$Ymx}_{0sxxlaQUNk%8#^LXlv7Qp0asO@WK| ziChNOd-F0)+=6aSZ!JQs2XUr)r=zZ==NM0_GrrQ&pWsk_I)4uEimO^H3ds$y&*tZw zC7xyV;kzNryJT36W8sY0@dYq#4}zf1aA5^-a{+-iAv+#80cvgh8{hyMS67o7V)$r7oOWvjwqAdLC`a( z@QH3ifrgU4G(O=oh*Uw4qxCb7n8%ce*c0a~wHR&Es>{$wlbtb_OuJ`1)G>6_d)SXO zx(3@i24ns{H;`kWx)oJ-p?V5$4-qqG(<;WrMV_mzGF=5|9LSH*Eai1xI3m)!cFWwt zZmV<;XF*(P#)&sJ!l;hzIsq=9)9l8CXOxFJ%pFqFaem>r%62Z;&_tu^qN1Ta1W#Pn zqy#>j9UowA8P?f|tSbZ-91MkdTX*RsP)pIRLuea;;xSDFd)~p`crGfl>d{m5gHRiK z^<<}qOz#1uBheWTg75t{m0{D(3oq7B@)}Pf8YrVq#Dxi(Cip#uE>S_6cRX z9Tq~d$uA8$B{!pLu_E;_ZZn_lMlq;yKXCU-V>X?a@Tf? zUga{~@tkCIwP&j&8gqI((cx;{B(oOt@wxTEQzMdK+sf%ru@(PPdMrQ@zUu5*TIpF0 zswZEl1>`W=K@FGu`QmhVpdwmiqQrIcfr{^|Uzp&*gFe09wr9IdnqZ$nafI`l?Q0fk zYXtzXf1bBLT%eZ|VuchuR6iGhz}i6#YUP89+~tP6UamKqe{-gIO!heTG-9c2Fj+Zh z()%tu5?TF)qFZcfIx?9*3l34Rv*|J1ds%Ux*%t|h23KPIC=;qrt+mfByZ&MLwO1?l zFdL^qg-i-i&jO7?#)#eh$wt*`!+CYPM1cYrHCPBHjCT$TePCKIy&~`!c|{8Cd#W1g ztChA9@|CBbnWOh7>hkeqUQy<7;`A#y!u2pH+{akNr#d_*w6}nMUrF$!$a$iInby12 zy`!xJS!&0G4t|X@9-kE7Zh6YLu@asty%O(jVZUcuic1~Me7$hl~7<8rOut# zEfwMiF2ZmV)jbLovBAZS(iST2$j1U~bRQ*qjn<5bkG?*8rQpI24t>jAX{I`tTU$ub z&adqeeP-^PDy;!&s4LpM{CNn|e%zX(U3(zye!a78iSho8fyi^EDGwb{kq*+2BAtJO zu^*6apQJ>R#5+DR@5Rd*$aKB=YQOO=!36CGan(!V4VWGh6A2GV5PQ+(-_HQjQ-(|q z%Y*ul8TZMeaIT{m%YP()BGJ;9e?BI%%!&9%IBC@++d<6Ij_JGkN~3VT4Dd*wE( ziR>ey#*!x{XwGe?1fl5K+B5-kGOGd(-t7+ph>}i=s9G|qXsve5xsl4w?S*oZ$HjD7 zxBb+*+5imyFYe84#d#PPXK(D5hBgBZhlbjr(*NjgSww;=Z8!Fu+;WOTfY?@v4!Kkm z&nP#(@wKF9f5a^iB=(S^!3JDN(yE4L1?emY7g3k<2oqIwihV2Bc>y|2WJ z4k0ssPEhbJ-14k01Xi_Fuc;&;ogJMc{xumW#{SCCnQC@)eq#f4oTX0xz(3V^%pCj& z(PM7?4aWHV8nktww_5LbR@CgBX=O}%v{fVm|*V~31E*{q((VuSu4XY+VUSq(~5;i+Fz$?a8c%tQ{c%TR}sn2Cvp zoxO$qP`iuTpdr)>gO-V!+A@_iAFf~U&b&=VxPZ`~1qLOAgaSajuxqe!k8yNF;P33c zetnKu%Iefk926AvheCP(V_@Lsr0t%aB4ZJcDhFqm!Md=y!apWA=DV5W<+dN z?ogV+{xVJ1cN$2I%vZw z!oE|mvLO~E%GB{n{v!MU+yIzXsuYzOBU+;(1Q&(+cJWTH&eadSuHFEkiZVaI(Lg{z zp#JT|AgUd!$3S>(N`Rd6IuTO$v4)4sC=oc6tBq-i)cPs?JlQdvu*{?=Awj@;QE!iA zi^+s5C0`RJYbS5_rf+B8*;{iB#&*7Qi|vw97ug&b&SpxBr=CO{Vs1io&3$EZ<;T-$ zyUO|$HD@e_cCr4#FJ8B$>cW`kbwn(l?ttI))`uJdYgfbct^n=*H6-4;1-377=$NQd zKXQ^IQ8KdeT8t>-$%dLiM0`5?wUNO}{g+nyszMpQN_dZ9f zw^!r62K?<(iT>Ei`&{};$P~l8_*YK)zKVcRi7p>BgwZ??_u=rmys;v;j&re_IOgi)Tkmg9;i9+;LmL~ zWuNAd&_{ovEl+ArSTN-n8JOmV;VMr0=5T&kLT)^yD^myQiwqXTTVDgurriX~`ek-K z<%1i8(+{&s!`2M^3HCUazI0qeP`c@rAG@%WV~=|S<^~Lir8SYI97ZmO)wM`s)&u`k zsIYjW(RDm&(JFcY92K)d}d27BjeSg15EltlQ(`IR5W7WvUfa5R!o%GJNOtbkEB&eC#Q14?EMun8>r zG@^NF=uWOjx~iH5$bDJ}LZ?G_sw7dOclRRl=ji(Q{SYqX0x=C7v&LSU{dF+teGOjX z1agH`a%3xD(q7jK<*aDrAmVdv zLUfE1n&&Wc(3?yQcX^RPBFUwhl3lXI0p|uS#CCr1gw>xg$(zyK%6jZ+q*%Pc_}9XH zKL+mi!hR6ZH!vC30wn$3Iq#n7lMwtTx6Q%S7)ven!>D1{;(z$N4E#}Uvqz5-@r5yI zI_Ab_GfAJp4;IY}ZqUT>|3Q$kq9-B6Vt_&UEDgQ6Pn7Bv8^=H*G*D*Fe*z<=T9r|;wx&-lX+-HK-aw!Oa~=Q4+X?&1VATCiVOYt8wwo~X(9{l z=`<9F&|`||YL|vcrsac$W`Rg%ekf(Gj$ZTiQhxNLM#m@(ztXzExzkiDMx-f{>>ILT z0JQsVS6$NkUSAIb9d?6uq997DF=TD%WCerWW}^XKbXsmuhrQFo^0&-F-*;+*f3rA) zAQV(hSxn^ODS)+myFsB8u2g36DZN%ua+t)8jesCCk$w^*?U7A;w zj)Ib4D>MvQW;*)L*zdl{%J9webKFFgPFH((A8J*)m$#g8a@G;~ddsLn zq(;-O=QMtPG@$*)M`38ZZYnbSG!t6e@n5RX&E*b=m$E9Iy1!e34%d9b+vPIS&BpOK zzxD*9_gmgWx%IW$XXEvR_bH~}>s>`{sr>=wow4*dY6L&QLnfEpp@pw7VF5IL|h{YHdPXfROZMyzmO zNC*OS6^bKZMjSOjP9c~HDfIfCHlsbY#pfar^r3LgQEN0Z4 z<$f}=mDg`2pnG@k&9X{R3 zTm~@GGaf}DX4*3cdv6!?P_$f#3~4)I2!qsxSQz_}@_&16h@9t!_up~}T@?fbI2iv8 z;1y`wGHUPCt?H3?U%qm>lDJa!)Sm7|sF3i^p5GlltI@F!a|OTOoc8(Etynq;jk}iG zw5Ok(88Ts$7;7WmF6A(Asgly()%2)WV-Hi9Y?`j(preb2Q5bo6l{v5MJD8Prpg8H( z$t<1b>m4A|I`q3-A`82^oN0zBAJx$VFv-skSMj)apL)3~mD*V?m5n^~cS)$w@%tg+ z=DG9GH97TYLt+^>=hMyA@zv`A>HLK_O~7t1Vj|qJozhM?n&)ZgaHwqn)m=6^(`ygL zXk!wUgM4I)&+(VhMg*mueDs8PP9Lh3f&MVF)flt=lu}geYelTmMC|KXtP*S-;FTs$ zNha>qDo$t^Gdz39FzmT6b|;11ctVo71u7#id{QC|5`gDrLiX@S@+2W)mXtJKLR>g5 zI+y?(nvVs=%Y^RXkLF3j+$?F~zYdYO=uiS|c)mO8*+J`vv{fs_CzA-%IHr@aiwinr zJh7RVo1Hk3xX54vbZ9;r6fac(*+ZG+iBiIBAxXZ3m~dQV2mv}Q9}SL|D(gd;#fj3~ zY+*sZ1RsRg2)vh7_J~SUUikA!7!-?d{ z+&^>w9&_|xM+gBvJRdiXmkaB|iN(p>KXZd~r0$s<=SF7s#*4cZfMlN56ZWej1*<=S z^I?k|-oX%RY>)$2PayX>XBaESRsUkG?C!0N?-QM$!!_pCCy)A(k4D}-45*jBPE$Bb?%P`T<~-X9zotZba?OlZ&A7f#|5oQvZAt;J_=9*hwQ29;)t6`p^G|;& zzX>R``enGBAGOq<0DzZXpL#1U8t2a^C({%Hx*et#9i$lcW=Qh?(ms!tFF0+z`1N&dO4e6f0Bs-UYE_ldeyy0`G9B5c zNr>L8H4Fkistl`K4HBd?lYg=u?oGp(aP!{@IF%w?q*+9zQdaJyM4yb}BhF5-bmJzS zEYemUC`8jc{w3l{c$B?FAdhO|-oOgYa2rx$F=Xpd+-7DAv76Dhepe3NTAlA*;9*25CSn!;eFQ~CygX4`HtZi8`;`!58Zt$et`iQCJ{3ufV~Fp(RDB(m}y$%cE6QG^G+i z`y2;ps6y39%B20j@C%xNs)0tDQzeAWZQEjZ%`IP1IUV(a9!gn5+3LLuBC9BjvO`6m(n_w81Uc3YhH4 z%Zi7^;W#vGlHxa#2b^fj78n0qO4k5!b97A>V5~yeoH|FUfwg}Ckt-vLBDOvcoa3w%AaN}AIaD`YyZ6Y=i!K! zHd_beE#Y(s=f$VXO1p;3TQ94YEa7mcDutg)m;bCUuVGj|te{=^;iBnuoFvP_{w=zR@{Ovh8 z%UbO~#)V@Pr5j;*zh&4o;%ha&`_|Km!OH8u>h@c6t*&&cuXs{A90>n(RlIaYKZ@9d zfr{9U+D{r^-n5)#Qr)%0^UgrC4AC@h-8wBBpxk_NCq@H`XQ+xpqW3(gTf^Hb;{cpj zu(MTjcyOB648p3Jn_bj*qpq7*464IXCr_#dFq^Hb^W_yu5qJt4VR|7ntl?c(aD>#v zCD42HbgbbalEryxn?9K(ty|5>FCFGqgpr#rxvJ1Ta5Qd&6GrG@AE;>!o%ntbuQXWL z9FkwlFqs^Nv`{LLstk594#t-g+X7k(M=;>?=@0%5`y%p~Q#6hWoh@Yz9(#NU*%1?o zkwwbioD;I@qznhuX2oUm|J$-;gk<)4 ze-rReL+R?sqwo5Zg;e>T*ayk;vHJJ;ng2IlF-S170l|p@0s;=?Os59C+OKmq_CD7l z>2w*r$BQgf%Vi=;T{M9@b+2@{P{9nFq2#w5EY4AMzI;7PC@0Zrk&&-jW;Sh*Mob}( zadG`3lVJRE=EZ9GE&U~3(6T$5b!6p)18h`Jdr~zX#h(LRRH5rtET)ytjb?TmJGsK6t zi$XGSl~JdWG#h9x84(Yzw@@QXERIc#y^=-TxIoXyQKvIGUx6Hj?#@O}_N8LXdV=17 zgj_uFUAk*a;tu!)>;Y;#jj=+y9@3_Icmhih;r0Ml29lT>OQ>0~CT152QCziJj+|m> zVapSJ$St&(*Rv16NmZ|yADC_7hZJS*(^#o*^9N`=;*UGSofH8OMI0pJC0zvCv{yifgUiTpHXE>j@^ly;X5BBWO0uIY3 z+g5V|JH&OdB>@|7*hgm_KUHmhgQ~MPF_Co72d|lR^d+7FC>Ad@R9j8$ivfy`YX0jd z6G~ z&fyd4LI`XCs^`Rg8$hr;i7k)6#X4#KQP}sXW#?EayzAX$J8D;mQ%E5P5i?Ih6l=8Z znp{tAi&6Yqe#ZuCG|ZBTALhd(nD=>$;qf$y_F#ef*TP{^F=wiy0gOE9bO@g}{Kj(ahcZf$~-e`R;P#Wan8#)Y=pr zB%Vh=bl*!)_S-IJ7UoD;uoW6|OaP=DXn0JNvC-rO{BXa=?+y@=%mAYFSqFsCujJf( zE?E+RHa)ViRwFnR`Hcc129tjRhuRk2TrChl6*9xo;gXP^jKF7tIFu~E^@^NzAZocj zr!64gZP`pJD@iWXpV~22`cKC@^Xo5YhHRg^9*Bl za$JLQiyjqifk*()JJsR$kE*8>c%MC8jh+&3nyP?Qq4Rx$L2E2or1B3L!t~Tm>3uC) z#n+cFwF8ASllQ)_Hy<1di;sKUrli>=+M(Dk&ufek$X(WGi**S#p>IE+XAT8u9562@ zfvt66+sxML`a{Y|q*pAM6*eZk2d!(y55giu=PwT2FHsDCzf0b2iL!?(2UuKzED$4<5)UAbJ{P0fWV2v=e)uCj zU#NnRJ{}KYf(k9(`hkPJ=<0AQ_ z{>g6}dC>+!_@~wl7|h87fQ~rBhC>%OpF&vTr~)^MMvH@~U~&eT9foUttZ-z^(of0x zm7yi=CHrf345)-y_*q`1;mM^T>&}w-caSp8C6LSW^fz_jD4ye-wKWNWTe9 zs$eTMjs$*sMEQO>&gpo4U>&ncZV$F|hzs#nhV^B}3FGxP;ur=3RD^EZ!Y&6F1wVo6v%nzS`T&OARw9!nNw|hDB%MkQit_Dq-f1-Q=Hy9GH zfU@R%DMdm5J`5Dqz<(a25h65c$-z)FC@r{;ge?$vBgtTIxS##!rqGg@3mZOL6Z3OR zQXXvu+||{$u1P>}Jd_a%wB^v)(s8vgjbp>3XXWJ5goTQDCX3ehP2!{Vv9s-A<~nTPIPH4e<@ggs0u!KZj84WiKn;n7mLETlLZHov zP3_u)vB~Ar2@Y0>)~e)W?X$ebtX$Rgu?kBh=!^vhReCYGf>sT4Ox`O!d1FcqbC^rj zR99STMc7!YvydFU*1Sa}u#B{oB8$q*MM`UGkO%TQ04Gr>eeCeVO!@SCU#oB@{kTo%{*mXE6tM&*2Fvb zkZ#h;ILrwnPmM1M_|Vb^_nmH-?*#kTGDduje9?u?AD)dt%)CPw+92(u3x{F<463!p z4w5V?S?Z8G*|xq3hEA6`Wdw1wp)3fzZEXWZMg%Zb&+5XQ0vFKjPIq3MKQqH1{)&ub z=gZ!Wt)U#c*k3QC9-^ko@sEiS%OdKv={1XG6Ej|!CR!X)pvF8s&XsxZPRSL~ZrY5a z{xfwUX$0qoYPFWBYADlK5WB#BUd$2+kQj08&qArJ?|2Yw4nJCaqGy~aE{C9c+Vae@krG6TY!uDE2?D%hXZM+ykXNLN7FnQ!Dc=?W3j(@-(W$^&*)s znf-cV@yM?G`uxM}_J40VzB|10og|?5-MkWKd;vvwIchoVmqoo5XI%8bb1{k?Zx%dJj&K!M`1NKdBwOYFhx(xm%oU7z}G810RpE!7%t&GIPHsy9}+brQz{CZ0M# zofUNl6stY>RADB)zWZQFSi(N(I<=9(fX5(`*QW zDYo3HhyW8IHvrStQf(54U|`Y55{96h`emxy{#4~#zV-)+Ra=W=+`k-&DWo2&(ju6oLoiyF9H@!Na3ORqOJl-q7FMgV1*Etq%a1(|db@ zP4y71EBa)%J@YI2^2pf3X%;pydvs_(u5WSBnvjfLeNc(w%9w~DW)r8y7}SL+6`jbg zM3>#yG_}boYgpW}CBt@HVtw6$b@_5{xLz%wT}gbfxAAFWww>&i#f71AW(F=hAn=E| zj2JV;i%`J*-SEWj+$qR*mnvXvaY8$=P#aa{5aF4KZv0yTpAfCuW zB_sUok|m7m=4K);%8{LZTCg={{~&B&bzha%JU3LRJnt<-?bBIdTe?9Ns73AVN$0W}C2~M16 zXWrTKatW=;I8-a-h@1n#XfqKm}(0}C>DUSW5WFnhZhfnJm5(uIO9oo2;_?X;|N-zjo0X$LUGTU zk08UDsjy4m*t^UB!SmSbHBV03b_K(a*xP@?{TRhFt>bE|s4y=i-5#NDXSCaDe^Nlc z=Avb;G)*cX3b1K2-V)SW+W0ozJl9nIgU3-7`nqkjDPp27eD{O~ajILPv)5Df#K(TA zeXy^=lNW8dn=Jp&dT63HHZ3Tcuvb;^+QQ~Dv`UT`TVy<7>0(yy-jI;Pj> zz951{5>U#d{DpOinDgrpwb7M8{&k~m%H=gVwU1x){#cl#xSN<}*phHq)K5#Um8OAR zDiS1I&9q|e=A&#z?aZDu8m#ep+3*FTR%OGJSi|=WayCklkcnmwyaWeAattQkBPA$Z*94r~F)-f#Z_MnBa<03by5X@Y^R_Fg0yIaZ6m0$>Hmu(BjA z1Aj2Y(R23p$YpDQ2B7*4cAjp88DG=tll1(ZkMG{>tvfX5SCD5RBIDW^#;pnqBki#w z(@QeJ(AhM4V(P(FFq|CAQqCr~FWB|hDefN{r0YA!_eSOvrSQ96I;Lep0S*pJ55T6S z0@Pv9{5*g>(^U*+RMD7C3M@k%U45vz_J+aX6W4B)!`c*s_@t#0C-1yk0jEqj&u+H& zmT44#hK>GN#0HKYODcXkzFcyOGiBjpBTj}WEHQUZH*lWulB1QfZT!R_u&da>XTFt; z`M89$)e#i|su|}_-nb(vE;-=Z0z}~tz~BMmw-JvyZWQ1ZjWxTzRnB9lA{a9I$jA@m zBs(oHQ`YB~G>Ym2I(2!b8!0($EpIiveXaDEENaCv_A7V(X|(ioh`efutrTVSznoDY z1xP;&hFn5H*JWheDbtz)^w72vf5N~yp4%U+w?VfxqYNJgbJFN`mVRj^_dNFfG+iOv z`4h8vodhALrC*X$v@PU!zN+s%0IUKw=HO({i$0_TTx%EI`YG{>bm2nc8|U9}Gj5IJ zcXcVhtbWl!MI>bay|1{VNLOjp>(gz`hnWB_>J0Yk#dA%uh4oG=CaigGdHrUn z$Pe=Kf7>0wV1U7*g7QcN(`TG`=ja|zp~~WIhR6CZ8&RUXb{ca@M0fH zvTQhYIkPHjh^Q&zQtTQpPg@exDegBUs4?rD)Q8a@s%ksMPbuQQlSE0LC(cgJVfOB$ z#Vft^fAZjw@mXK05W{>a0q}I8cQ_~9oTEyKpy-j#8Jw#p)oq2gUDqgmS##ArX8O{jKV`5n%G^HYlKD+E*9!eQj4FLK3eiRf0!oo1Y+NKT`CtY>bw>sRE+gg&bGeXXfy6qJ>hi8 zMj9OUlR{)8>~?AWH$eKCC*7*>@XQc;v= zwo?M356^9ZwLsaHg@HfeTdTtz&f79amhlkyPPTxQ9p|MXcx@pQJVnuO5CZ!soxV{S zkz33^Fbs8O{&CRNi$Vf0$Ah@`D1OE>4*fwF9*LMj*NqxJWBSsrG4*SBp+YPV-~AHI z7^~sKNO(2Nb^t*$9f9r66&`FF;gZZ1^iglrlEa;XJw*Rwt^jr(#XL86`a+N%*;zr5 zO{ZHqr=}{LgAvMm93cr5G%Wuotc4mlB{+mFqHrL`sCQvuqsrmfFMIZFr5vIq1V|XS zRU=}z6e(AnGR;o8MNbg8uj1qk!!r$Kt4{SVBGmAHG@wl_3M0>bb^@H;!F$x@u5MP} z>J{)C@_(b0VRB|7XpkTvbA%uuSRlZ@E*!w7mah9ACyMX2e*dl^p&5?Rn7$Lm7+!j< zgM6AG)F$v^719{oakO5`#sSFpzFjI!(eIxP`ggOl^wA(dSFOYKTpDBV;<;AA&yv_I z0rTgvsj}KQIda?XA6SaxLr>nCy1Q#k!fAf*ek$1lHzou|{v>Jhyo>fhr_?qIr9s~%Lba;QW+IBIxb)xVV8VawsM)L} zHe$L%G(B@tKOOekWA%H8%qchV?<;3rjq(l_ebA=EdZ_e28V4%IN0q(ELrwqa<^K!fXh#1(HB-hu5T^Vykcf}lRK$@%fw4v;C zZl5-CL=x&%cN3{wz6xvH#W03&c!obW+j;rXnXNCW_c)Hic2QnyMYqK3Lu#EVC>uq| z%)M|w4yLEAPRo-weMsAQ<7tQE+xW0Mr)XJ_G9sAM_HQ$k;u0M+J}7N^qx1u;roW8L zZmSw}ON-2N2zZHGbnLQsnFhbMJALj%!4#Q*)fwGIuDJ5GL&7g&$Th;|3+@;Ny4x^$ zXr8P+BP8L4o8>YtB|9!`=`CE^92?hzH|3{o|Cngt%H)&EUynl4dm@iTuECKjKL3BIEC46dmL3j=M* zze1ggj(IW<&O}g6?ANL{c*`+VU3kF4LGZ7K%a7+d1{Gu##G3oJF{!_uVW8UlLimE#XVDdtA$av`;tzUlG6jsfxD0Xu%} z4R^bUCoCd;Wp11B1rGm$P=Ss?L*;FuURL1_h$f)lI-V52XF;axqW<<8HO{U+;kRB74K}C<_ zmwV8$o0wm_gnuYNom2jcI&TC9|A~8j-I-bSd1*T8x5E5j^E@sy#xLYHqlE__r8a|0 z3yVt)ulagKp^z>gS_s{bW5Vy8uv>d$&z&^@6lx!xLR#TNzvbF+W4ok)@1$d&tB?Nu zd7u6gUz%oO0(@=#z65RSw;$E`$9jeLvCI3n&_)o*7C9tW6Jl!E3G0 zrr&Vd6MpaRQ(!CihSY_C=Xt`mGtW*nD4}CbQOYB#jr9!oVC6}_n0;w$hXt~R1~P|pD%CKzzGDyL_E&)$mew|ex<*Y^{9gPgNvKsQ2Y@ZEXHCmHX!btDie0Pz)@ ztARB7_`wEof8+6jyw~TT8~TBML?YrdnyVAFXXvFBkIQDz{T=jDY^KH#5wG&2A!wi8 zv+)PsDtLQn8|>D}&V8D`)5S5CJtyb}+ejE+pA#2g2S9OyKic1uI#GRa8N1%9340Ut zg7S=K?ac?u|MwPc2;KvJE2)dO_$7dFXCJ{D(TxLjlC=MLCft}Pcf0sS#Yexc_gJxc z1b-w(*@qej8bP2H^((TmRor{P^wYMym?AoL1%C_gCX?Vs6Y7)P|Kv91|qcY$nr{2yTm?ZJ%*syp8>J?jhlcJ2L zyiz-7$(Zcc>}9%zjR4*`3=4S#1fKFw#DWXp_dbCU);P}KMuM}5QKgg(YA55dyHQx5 zr!TP6=Dh33{d4*wPv5}TwEH*A4B`C;@B8!G6MJ(Mz(%4T>-Ln@Yc+o<_}czLELs20 zn_5Tn0K(DMQ-Lk=o+hbCC6c);Ee>ucx*3!bGreI&G|HgkaxVe<^8NCT8y{nxOw$~R z$BBBGcvU3(-^uZK?0uL;-Q~rwl%GGUz-k9`vTZ&%zA+p7TEap9r#QV_n;w`c6wn`v z5IEUJ17-*PuZaspZRY^fhWT&PyqysD|F5d92?FvDh5WxZEnt2-HTZw|)YI)4ps&Eg zc5%=nAYF$f7?>fD$PgPC*MWrlU!E!i2*@b`2nhE7Tn+l)BRa67gAV*Z3@zYU$I|~W zu7*3s!2d%(0wQ!_fR)Ar`ON2b92ow*UYD delta 32700 zcmV)EK)}C``U3Fz0 znao+GBrH$^26@YLGUqkrO2dOzHE3Ic@tl)1l-CQiwYH`h8@>g>OyCIVnj57Bv#x*C z1+E$YUsr`N*?BkAe`3Zhq-#>Lv^-I~#iUUd~p4W|tStyilQlWCF=J-@< zkv;(B8l0Sa?izZGKXhK=o7-%K(kNk!rhYi}$z>K^(J-d7>DwItI^TO9OQqAhmKdu( zQ^ky3yC2?^kY6_~^H)60CVKhbaETw0EKDd#=xlZpZZH@EXxNqQzNJwRcbAVs5A^$( zK006W-XViDInMCM=B1M_vth`{y%!KNU9zcy!?}>@oGJ(wzgKcdLR znT_)`oQLmMi* z=Bmmf_hlJ*czA?G3^b->HDbe7R~f9W)#mMg#3oY-za}v@=H@aBqxWb^5WOo8Y1lvh zJYRcc;@!#H_zkfI1@-iL~1%LSRvZr&s z>HNG<0v|`j>gtNP6rk$B!S^fdn~Vflp6O z9dBk0|BjAsWv!WiZ@sH;Iu!DpnHkl}$_fRQ5zJh9MaAE)E>bcwUOd`Ge@UZ%;bi_` zX<6Cyf`a5~E4ww(d-w2f-w0w^v}C}^NU>~9$lu)Hx7a(=cI%f%eEn7qQ$;%g!GZx< zSzNxpbi0eUc2L_}%%h`n7VRoeac|M-irrlnk?YN3?*mO8o$lW+nG-l)Qt9Xj>gp}z z<>xbSIV5jhg>|$;`yDvoo-?Dm*$o{5v#+Cnz}h=7!sl+x_+|F2A&t zcFR_`t*@`3dxKF4O3y4O^(6zDjEtF+(|KZ&qP#|PWzFP+LpgFarMC9K3r1cJyHt8M zHsP9C<+!7R6|TsF0;~bk%C$k>7cZi}f7dk~h##zV(4Ux|R#sQ{?KS>?+twDiyUWGL zZ;`;w6z%8dp{?y4>)KJx_{N^dZ0JwM_*+$7-FIKVzG!Z~i;jMxqNy1?JMY@>mz707 zG{p9e!W`1Hb>=aYDjeG4^Nc|i_J<&<*LXHJ?-eaRKKt+Aif@c0qt~kA_Rh}7!bwn6Azf3pPZKzQO(=5}JBg`;esP(N zjaurJS664%^4%x#S~(PhEXn!vCjeaZtA|HqYO1vM9Mg094aa?52FvQiwf^akdV0U~ zOS7`GJBb!mbACppr3EJ?p@Vuz7IJ?Q+LikIw-^x-o~nUC|8gfYpX=_&T%&6Qy5sf) zhoj>VF#&O)Ac5!T9U$al1yrPJrzCHtGs8=aWTSu_M(c~gaDItL=ncs@~AmE|);hoh3v$GV;%*?yHyKg8%W9uY;ge_V$7LO9I-u$s8dVj~HG~?qW z8@uZj>0D4Fsl6sSKgZMc@d{Z(?35ayzf+s=>~DrQrwTM2b?G1pG?8kS=vvK+ys=kl zLFj2}4%*azEPO94v?_%)-=6z7RjIdkh4ONI`TLX3yf7B`sqKq5Z_1{jcjq;!FiPfF zRvoWSqrH3Ro(}?no~e>gF1pwNn-1KZy}vsM78gJDW)5)zj>g-@U2AGy;$dGh2lH>HECt7Pf)_{>bt)yW1&f_yvC zK0iNye@b(l4;=@KimH;smI@Cq-1Cg|HMwkq+W`Yh(N1OTK8njT8<&gA$;~)&K_CyG z8eAp9OXJ+&)bl+d8if*tldf0Evf0b+_@WeQi0SVxJ5!@`bCy^37TlDqSrdCs-~7fv z0ttAr`?C2-$OYr2lq8Ie8Fq!o!NPxT$|5>{R#N4Y&3|NN5i=@MZNTsEc=kBaKKJzWysj#KR8LM?T|GH7JL|NsyB?2mda(!zKHF&#d|~5t z*al}gd4#r;6@J&YJ;{qNqhojqv}^5b+NXDS_5`w^k*z{VLlf50;*)!YGBq_-1$7mF zwWwnT5~HfEJ+UVAm_vw&n7FsEuVQ{~eP>6`)s-iTQHkO0+nBt(S7FqGe!01fY;0_` z4L%Te2^77Mya(lvrOU}UtxOYcy*yg6u&|&Lx#MfOS>u}bMtBuzjU$q*lx$wUe0ee^ zr{vg84L581eutaia(6vEYMx$RP8cJ9E8*dR#@=|y=eBtD?B74pO}CbgO;gTN8x)iy6RN6I^VAC1{O8BV$AKnf*3~7TqMx5`)g~n5->mZv6OvSa6Wp(LYP}`% z(ljs#Z~F|0f-*+-m%l$cxcKGefw&CRz0JAhw*+D&U2 zm~bbpO=)Rq*N4-Fd!uCd`1p>-)9%98q7Lg_cCO!ES>Ie9f!-1j#TZpq>9jO!<}>(5 zM%BY+=UB#}q(oatxZ2nxrF(Yvv5pSzu+WLz-*z+HJOe}L@vX#HOuYvVN!Ql`fNCsk zCP(JyttoQsM7fltrJo51P=-o>w$IlEBb?{g*G)A_n-dt*Zuo!w(t4+(9KG+izq7qP zQ@K%icWa+XtfZv0K9myt#)Ma&fdAW=$o18DJCYCUs58LHTqFoJ0v%k?C$P={pIy_6cATA zIcy+O@$!<~l;|MU9qjEvV?u6f{wdp4(`X{HOf0Azy^XgpeTva+(|A3=mG?BI%E zI#}U5&I)Sk>W5bw3rgmHkjsCp;^OifE8(KctG!VyS{0A7MgvC8J9>Kq(P_RSRn86^ zt@QEZShvn=qyEALV^hj)s|^jKM1?mBNsX=!nkmm8dY zD?U)aldP+uJpNr1-(b29v26p|47BvA*>H}ks_L)c;HM`WHBEt?UHhG#ouM5a zk8u1*85D7H8XJFhb$R4Vzv_Ac$jaIVQpx~IXQs}HHzC2SVS#~ug}YD#*W{q%6Frch z&L9$Als8@;PewFitMwqiYR)Zx#w7_u^y8*`Vaz11o@_6FUZ{;emiSqrr2|W!JlBu0 z?+V$87jTgbhlxup@Tn~j8AXFhYxZ-THF)A7HXUoNA)= zGU?c(ZOfg1h1ZQ@pXCPzXwuRI-7sTf*1Rlta*{km5Q!Ws00w#pih^VpPoN|E~BLMcWNpufvfaGq07I+e_k^)GxqE9Km~+zl^8*DYW;<6 z24FjX9*|2{=+ohBIkH;Nw-1lEz385Ec)l2sVuC=*DxY57DJY~*-8!dNy z{{5Ti6*F@ifNB7Jim5_qoKg)RnCGo@ zT+c9v>4arU-O_NdsdxSs&Q>28E0-%nQ9@8OUmGCN(o-t*avgPulzXuwrBtK(XQC zx{%`>`*Dpu3_?d|rh13Cv9Xa{)LTejU;j@|&KT&-K_tx5ii)PAnG#e&Un6>Yq>oR3 zPMBC(LDv7ObJ`di;~W!hn^`@e6$h@MuU`%W1A~silzw*B%)!B7tMw@-V9MC2SC=o}o--;m<~bpWXYCTfdg1Tm%o$%ypxyB1NXBAO11j}JwP z4RQv-mnhcIVaRb!HrLkFlruC$(Jl^uHbL20i&9fyAO<;^%tr_e#q`Qf&;%@k=>&QzFSo0yoauC0MjlrlGe<&RIxz`_zTF`@Riy}h@;zulV0$i_xNUw={B z4Kkpbucnu3gY$x0%1X!3`3?DL%Ij`S4su67kszD-86Nrbkq`JT9-c?bB|C5NyA59% z_%xxXlmyl}#V!Biu$QHbHMZU`>XrcrCD&n-P@cGIO^LBYWRLE3G9RTh=`K<=-{j2reJx$Hk?ZJaRw$QD24lLH8 z-K!p4H?7^uxw}oXsd3uypSe&8*gF{(?d@xDZ_t*g7Jz0H=p^1MeV;pT}N z?mn!A=#Dceo^C+kJN%x12Td1>Y`T2m!NGE+FqFo#sn$~7LbX$mkZA*-U&+Z-Ak+b2 z`aMNj!r>iFCt+H-;#;)J7xR@#oIe+7IeX59mKzsBEa1@Klw^9zGP3k94 zR>wv@Drsq9Qc&arz%#V6lG4yX^Y*r3)=S}!>MGK50xH!G+N<~7%l?zAEBqz78g_B-yR@<@k;gBHc?Ctpl4)E0_o16fJHATi2Y{V6{ZD)XJs!VPs|ur;e|*8G6yFQ?eacg z@380h5=d~`-~&yeNv8#Cj3Cq{&-%UgS<7k z<)Sx-q?uW9PQ$`*I$_}yKR>jJii)qxfsD2HcZi28Dd($+OGyz^Qx7(KAr4PY+JU|* ziQYzQ>bw663c{kIroI}q^KQ5ELBQy)gagapqcovL^@^*i!W@04rg(n-{OP!@CS+O} z2wEq9Qe)F?JeL_E@ZbX}4e`;@#IYMYJ3AxhyBrB2o~NUtBbIs=*4C|~qk&~*P^FRk z%kHPO4Ggpu6wzgCP&HL@Pp6#Pad&)& zu*pHXonDh#+wAc{cor(WG&PEYwz%g@RPyZ$g{z(&Nq|=FO{etWUf)-;hKx#7C zw%ocJ8X1)XOJ3}FzB_BqO&KCd4~lAk-o70dDOtpe641HJw97qReO{iE#d@6+nawwKobAX{eRTglzRU^&>3|!m?4K?Zx)A}nSDw z__6k|poz|7GuM&8WhM|~atEBssFy14w!!_isHdme#N?#&b=IVS+jVnBM)R=O@!=t` zQ)wnEU7>1fYM-tvoi-Hv`ue10WtUs-Z%a)O^ip9TRaJjfSHA^F(Xgx3En56RU0)@H zoc{xvSU~^oO!*ImBpzg&w#&GGmYdGwWX0Teb8b+3t{TPKor_Hn&Oma1wzE?LW^u$@C8ON4XR|-7bgHOMTykj7$){tJ-d6Yq@-E*L=mm5ETd<^aBe3CH3xnyX{ZwJ#&1P;wIALPfOF7x$x(Y5sN{y={qk= z{O!Mg#elr}&suj4599mz`0Tgbd-p$TcCA@B-)q`MMs9mT;&Kn^2UKHZ)c)=Ir6m4C zKfJv@Q(;mJp*(20*A%&bJr&j{(d}->7lo*Y>uG6yZ%dcT+RBdBX2+ws`Ci(5o!m`( z&x8~h82E&Q#9>@P(;Gv-)}F4qx|&MR6$dmQ9=k=MC0N_;9(9A4?a6wK(B0+9JD81g zgX^B**dG~jadGFlq1o94m~BI7LBVT~hwZ9L!kxghp-<3eun=v3iUoK(xVf#(l!H{- z@}Ph>U!J7hhcrN@*JQ`X6r)m7;A`9ZfQfb&8c?lvm=9q4;gx1eC&NC?y@A9ILN|w5 zY8o29)6(E;Pyl4cYke_|m&?JeHT{$qleuZlW(i3~HpSbnlNA7~e@7|V4-4yzZW)?e zTfYz$y$^afZCTxac)eYiEDVVSX?@lpDpvRK1BYfxLjxq2?%&Wbb?c(Yf}@?Q)cwsy z+NUNDVMRr@9|Fy31}JT9s$ifIBO^mNo-3uI79H;I zPsYT=h=H9nv^Cz#Cm_IKJO3592Tc65&IB$CAc~w`*Vb|*brBIChtfnpynnCrtDvkb zz?N}f9%#8Wyg6lB9})^|v#y?AV0idOhChwrWP$pRI|?o?)uY2h!<(-MpaDl0Ha1pu zzpapy4dU~ExnrUA{<_AqxQGg|nS}`&nY^v7bTTg-B_MeVKfVP4EA1<*mK?wJ_p^a{ z+gxd9tKjzDn>g4+zB|YTp%%L6Pu*Z@$Bzw}FU3kp!Aq!`D>h#cH5 z{(vW%nrgvz7&r8dl!H>|;Ty@0r znH3d(=e%u1=lBHW%E=yl6r#7gJ1ssQN>K)47SCZswYb>))6Y-!Q@nqc5sdLrB3NVT zA4eD%20$VlG~kblzj}BaO=_k^B_wqD;p&X+=zt!l)$EB&>vMyb=6y{AaAM9TViAPO z^J* zoNVQ$?Vny&4!fp0>>kkeoNiS@E-mUwpKvFbrQMPswIK9b+{mWMm6X^E3Yl3+@Ioc& z|NW~pH#bi&JA4i#2lPyk-AdBZ7^=B{irHml5!8aN_S1T9%F4>Vl3dQ&x(KWO*wJc? z(IAo?$$D(Vkl*iUku9s|RD!RM$13(DD^!xB##@KkI;y(?>(bDyd>dK|*U{FFf79l# zW7kxzN+R(MlbC^kgv4bM@%rcQ(1l=Su>j?bb| zR?K7nRp7->0>g>OceJRd9$qbG=g{I&mSEO^e_Zjfse*!nuK;%aDj{OJPA^8fzxDLY zvgp>986W@+%WP?K6rnl6<`4%h!&fI8*~a+7M27bDTrhPaUt3{Fm!|ABr!fRxM2Vwsuis(N~u-xR0iB_t@`zmFQ- z(E&iT+!4qJ@@RQ|{k^+8lZO{}M#jI*Gmrjq7;~pP1OduM9$<1t2I0(q?ChD9MQ4Wb zo6Yj_a_UH<;BvEPHN|_2O;16Ua&mIo+uJXVWy{5SY+PMk0TU9L;&mQmq@`0>=e+ed zU~zrQ0Duzx!efWfS_YJ+^k?BG8(d(>bSy02`}(ke$YJ2%(1BqkB;bUr9Gfq&;=nti$4Wd;OiC)N9FIuz39PTD?62>c)~ksa z7QM$16cjWa2v~0Q6`q)y`V{7MzH34G^r^k8D;+a)yJKTwVgU`RUha5gN{WJ$6W7a^ zFZD`@-hMo2Mrel7+$N^otaj2_slJ+iXRFfyUIcAF_5c?R73~Lqa_g~gO}0e$+8m9Y zDT_j~L7mDzGnr=hTf$AG*D;jn{&xPS8m0Qf05dy7c^AdLUa}Y(@;I*cc%SdV0)c4) zY63W3tkC5pJ3D&ithkpK>j>#0daPUWRvh{!|7XTfz{rOHRVUGwuKMycM5KE*g z)}fDDT0{A&M__(`xO}{;)@DGwii^>j@2=&(e`ol@nb6bUU#^zCqllo8{qlvbv$Ipr zHYz^;ouZ;^i;pH5Te1;o5Fmj-MvfM*uCC}dehph%Vv6m)_J9E=JYH{8Q&jXjC@6=` zio2tm*03+yo+;zCI2lO87Ed}qS70Hq4sG7nyp${HHs;KK&?wYu{Q43}GHaCc$&BrI zP6La9lvK^6qMgrp{aP%nlur?Y*t2mHa)o5qo^Q;BPpf9vx)Kr+3YT;}A$gld!Bw(T zozj1G_1N+LR`kV-7tv=s8)pz72b*{v8#E>1vu6N9NZ-HLG;>T!Gk6AtI`T^gl;{%s zF4D%qXi3@F$nipc*)IXQhW? zduCygTf0-@uT`@zNWVZr_Xr@!D{VbJ*8F@%^o5~pIWlP({$64wA^cWN1Fz0#S|oePEBcmv_hW`3&!?5Y=Z}cF7)Gj zAJXf8{l_RS*>{8WKZ_A(+i&L`x^0^5X5PEHLe+v)2`Xo;>sDIl>V58Qn3ysSMIF86K;6BXF&EC7SQ8T4p zK-fNiHGU;=n?D+fINO-iG%z_@&erwuA{x&frm1lKMS#la%T|(jv54TJq1mUOLzj|r zi)E?%(gUl8LjSh4d5`SnO}=&(pbiZ^ixak$aCfIbM)v(7()BTcgFcAN;D&>}`4WQZ zLMMrgdFs9W>HMvT2q}9h=FeXWx#`cyvdSlakCP>hhC#<>%{Bn`JwZhH_jqoUg{9>S zKsiy2O4Mpw(-9E_H@CN7KqC=%A?WztzN0gJ1?nF(z3^K5`%@bBx8d18QsW2L?fQOd zym4BW{~Z;TAPnI-IywUFS>@BGfS4E(ft0X^#=XAYm3CK^Qc!>eXya-*m>t;1nX-R> zA`{!Gc1pXUadBkC3}5l<2Xg)WpW@<9PE4q&sH?Yua-6h4jvnm*VpFZH;O@R9?PfCI z4IOCg6PC>VPEUEPk>_Mv_UF#*42>>O zA`(4*V-kCoS68Ew+iz)p+ZxYx(|L)1ho;Z8e|f|QwYw+ACS!YA9kYDuA#7Ti@bl** zZEbC71qBm;-~eai{``3XXfYrpmv7LunM(5WBWdsKpX$_z^e(uS?p@q{=r!ja8yoxnqrHZ>>|w7$ zIDj<<2EWx+<1kv$u%;&Ahi09Bk%0`nGhjkKr}dDRWqZ3+K3fYVO2!nv;wWn2%i9zi_MhbX$D)ouL%YUG+dHj! zbTl${n6pNut*mxP5DD^s4Dt-bAYieTXXi$z>YBkmIBG^l^p77e7~E|Z9v@>3n4ZLc zI)E8dro%Z^K}WC#{2Tie%%Jm-}d&pi$#e0Mv9w2s75smlol`+JOD65 zp7MqrA3FlN&(F_qv*yVfHGf#KsoN=OsOQW4h=u7qnw2dV=X5fEh?+*_cJ0ims5tZp z4XUSTZex?3lY^$IIW4kh$4$wau^6dcELp6f3cz!=(ky|;hO(}%?$P7Nkx5Cx+Qm5_ zj$r1jZEPHzoIo&Y41D35gM$h$7;~4Fm*@6gy*B_|K7E?^%bO}z)_S)CyjWHp+*UdE zCUHGI)t0%!A{MiM`@7pmkAC9SDlN#!@XL65vS5?4P#;4}wHSzfF57ACK{kT)*@M-r zY;H<}c7={lV+_tIGH7WYXH!s6XgnDbY`i^(6=_xa@jIMd>l^VmMD8ObSSF1*fY5QIn%~@ckHA)wMxi^gr>Z3pC>aw`O7sSQ> zrZT7UCJols3mgK+gzU*hy9Dp(x-e+r`U~vx+y>|jx91dd4A&zHfYK< zH8rLA$fE(|_vqYQU)tR%BXGY1&0dICOiUSdbqSlB=2TQvGYxL+meq;HIyH{_x|BXQ zM%PF_Pxa(~q@|a3N?Xuc=d=|*e_r|q<4hQcA7nV+zm4!hh^%%5stTP9v|G=X1eAM;#{%`mXh{$s#H9 zD=)@?8Sp*|&b2VlGwTX@)xY9{fZ1ua+>v4#;uFPx$NFXD2R6=W-<_5E5K>bQhEWUV z<>h_u3?cypWoFJziAN)Z@vX3s8SuiUvw)bGSXoU?ZeHF4K?MZ`**iJW^YbTYRhmY| z#&+TRTz>fe;|CBP%~xz}>%r`EeJGmhF`46A(h9b4-FVI*y#~`zR~ISB z?V_T8qOyv5PU*SDR-Boc8Klo|$UhcNe$uLLs+zDA4kj&Lg1{jG6&2WDArPnY-C0}s zC1C8Df5j^K;C=D(3?L6Vk_G`51HTQv+{Q${DtNWAscCe}xe5x^wk@_iuQD1-PCnj-T zK|#mlWa!*nqTM=q9%x%tx_^}m)qganf~tVj=HRWtlFwD>Co zkvUnvw7P2TezOuTYC4_+dxMUyy0X-o;Rav3+DO}2aD$t`pf(RHwGYccdJV1);|jcg z<&X>8)UV5!YOhHY6&1l~Pk?s?vIvqocG??YsCMzxalNSL8mNOz( zQ(z*adS_OQ=Tp~F0!QDY=$+<4p${7aZmtRwxXg}7hRL3+9?!rWFR=qB64{FMcy1Q!|AQhfhiSKdi4qz8Fv$I+(2F-zGWm~au0~Hk%TwGkx zqECA0*^%vcXXrw@G=TR2qJ-YlBb`xIMV?ZUfY?VMBQ6e1CkqaaXU%-thwW5!-Abe) zor_yVgu1%=M;)DUtNYH)oPc+KZuaJgaf9OGkMvp6!mruc8M(NeS`lu^^ON4VUS%PY zSth@A5ftX#+8e?YesY^Lb93bmD;Iu$ivRw7uC1d}USkJ&?{;&W!taD8)jgC!Mb3xm zbN_B^jEI9W^z!mjYiOjX*anCkpfONZUbHy}g?V{bMCJSi;Jlh6`WH=TH^;RR3eQJJLsyk$$+&E3`Uxzs?1i+JRLKu4{d zl?SblpPye`Ts$HsrV|Kw@9?lxvBvn!jCsP7>9MiD0|{KdU!+fe>C|*|lz_iCA-`Yl zbb5rYwB-o>I$X?VX(#{`MWXmYlvm z-r}P76Vi3%j}dZz>gtb4NK9sCEy}8^+uJhsv<;0{g%;g6hC%2-0K{BeUeeI4Jb3N- zI-Ku6az7gxeQNdfD9xoO^gKx9Ct_}9yr zwrVDd(8_&x@KsRLXLt65$*%bd;(hqT%->m~w%3?)tj~#mAu4cSKprHRJ7TXUFffn~ zfCPvxz;n<(Tie=vKltMT59K>*{wMue(jLr!x%! z?20e9*Mq|Qg7IJOe8+ZlO0GG65iF?6r~CW+N5#c;UmmUS+b%i;B#20kORM- zr}kQ&fnGr&bQe|=Jf%VJ(UiKr&H%>XU~m5?FYnv;??Qe3a`Budl>hlbXpRPP0-Em; zxc}SQl97;j4ETC!*yoOmz2&CDBnhDG>iYWW#x%x%JKKGU{zp|A+-e{8_iWz74i@2X zT5tpIfFnU3*x*qBr23`Zy}g(*vcK9sr&m|U0K@ED??<=Q{;{yAsLFGRiJ3X0qT&%F zBcpTu6d~sBqOtLxGCTMXUFj9zIP%U%*FeE-uj-q&wWX*F3#v7Z5DX^>@nVgWg#)NU z$@bQNV6`Z=1=zo!dVe*1?tK7H0h0yj-mgd)Nwfv(aiO81@vt&}WmjoE%ZUVz#Pe}PA9!x;)9tl? zOyo4dqo7~{B^92)#}V-TyDrGGkUm)lF0-M3f5kQW-Jjo_@-^t3mXs4Z*GKOEBHsZS zkBe(_PuDyNOE5u*7u->s@eTcE!#^2q?e6yZG?yYQm^e1J{>7r9G&5@&=W702hV#{P zmIXagT3j4Is1A;a>FJUe*M>sCdu8$Tq``JBh!#%qY$e$#B(1jghkP21%$F}TCMGX` z0e8}bcG1|`iCS6}Li8dPndax`-EYrYGN5+55@4cs^s2dV5^SBd#5-b3@ zJQzv076`kbtEaq-4BgO>w%CVuAZT^lU)X+>abp&DgW@G z$Pfs`)AI(X<2Oa#iYV+~1X;s*7^l#TPE(Dd+DLk-b1vKYuMgX3$lM}2gEa|gX@h06 z#Y*kyxVe)jCRBlXXEruYsJIk=dpQu$MQ3_(gaB!D;eSpyUHXfFIyC5AX@0)xzrQAp zXHz@#j{SSFI(0-uhQOb`e7W}G{rjkRVB}HJ&&xcoC?7WSxVU6zZ)+>D={HK-+aFF| zDnI$xbg{S$bXVxOXS~Udr6kDei@4#lu29sS!c(@XIjprcR5-lTJCniJq6amk@dc~9+1Q&d92NGg8EZzCi2ubKP#U0&0$v)kd(E{2DO;+j^@ zJ`8{(xFlJ`>pJLNc&N?OzfUy#dZbMd=c19Rsoa0EwSN(a;iM@OZsLnv?qR*B_9vY# znr%&d`?TJ(q!hTSo$1nlmgS>tInB@nt$od;;NYi)8l4ZLnkr43KDd>W4Kg>+qxDM- zypxrcZS9v6sl{?&B`5J+R95m8j`$))QLx)$(yxJUd4GDkBA-GjE*H$Q$T8;WRSi5v zriNgsv*u5NcI%19_2h`6qKQvBI!>4NDF6ON(l4Y~rN+cyM=?r&g*fv{ssYU!7CONJ zoDCNc_CDQI=CPR**Vm_+(%dohq!qf}%(8|-2P-s?zbWR@3kfAZ>|_v^k_!KP&|&`8 zL%&T-+0xQ-rfSPOGjl!MSrh4Uh1P(9yXqn^l2I{vsk~cXve0GE1s11&jf_otdUx`Y zG52_YtMs&fAzN;L7Bp}CzkhSizrdc;cplCrRpm|ZurlvyRZV;Ce<^;PqS&oz;N{Y} z0xSeCXd2|s@ioI6Tf|YA9u)jSK=4Ix{^1J>pSPmor%&%Bi27{aD^)|GV{>!ilLZ}l zfAZcb$;qv2w$xATxVpR7&AUv8dn_o1*idii$|rFCYB<<`Z`vHGbx8HHbsEj=^gMtx z)#R(3-N1{Cl4=$`u$|UVo5dF4_lqrkzOqMuvBQsmvXcl3;=-V}@wW*4^!pnwZU$oi z?$8}q(G*3g5A8Ai>+5T4|CX2kE_Vh)gk7CaIl;IPLgzDFfVkyyH_rE9y+bK!0F+0} zOOh+gKDViVE&ALObi;k(evy!Pu5UB03|87wR;)O|f7 zqM+EiS!1U?t-n3+x#y$|6*lmSnc0CFo~o#&562VsHeH9nQ+_KKhy0nZX78kRoc|o(fdG1eh;VPfvyN$wsg{O0Q5S-ylky5sdLY@rM1}%7I z8&Gd&H)xI9!J?uZvVql9NmER^Hb z7wbrgi$5yVyb!SiX5>eoEHmimtjQ_WDXG}Fq0d;X1(JB-<7)*W5)xM(9rJ%1-IZtb z8+%-Tn&u@N3_G!cf`bD?Zq9#CdR;7Z13~$Ey_E~myBh840&t3?t&QWQEnJ?H6I5Sc zuU|u)m6VC1rwePo-ab(znPAiHc~~V^Q&+d|riRlqGWwU5?Z;hnlb29A-fU+1I18-w z_3{r((c0uTH;2W?ziomhL`4~032<=u?(TAbX(qRkkgk`z9pDudyawFQs&}5X&=J^F zs-A8v7q{3tUl&|nIi5aQ4_)x58HM;#1Mbz;D{Txp9+P7~>L6A+1dnF|zR+C6Nc-RC z7}z`Bso%rHMcLR0COuK*$2SrAO!brn^mt%^nQ78EjL^{Ws5Z|+E-abZ z*qWC)08O~=&TwpBzm^OyB-(uF2k+j0y}`vj<9_>=h>$QaC50Mr(F04?xTV+DMgZ~$ zF3MFKwITgk944`+a^YmG&GL%T|A4iJ@cDuFgh(u9xP^5iU-ZypobX*%JPhm9ZdyBGEB1 zZ_I|C|Nc!>28BNCetg({1rTei3hi9a&1UWLh#nxGZM_BY!vQk()b3&SbfxZnwgIIy zMF!rB<%ru5*$SU~w!7=;>DsNF!JvXCWTd2B|JwbJj<-F2RTS&g;N=Zgnhm>N>1t_F zjE;^b^F@x8^3Zy0X4t~!YaQr+bCuHe-9^tq{{=w+*X;iOIdnEz!pmzf{d#p}B|LZI^8LNF?CSRR zP`wNMUm#=ZMt<)8)2)4+Plkp6XQ=o2yaaEYOxpeQvF4V6ySpboEZ^D7V0qPOh!2+wIdfd6MTh zye)&_c9!KfG%&7oL-6aVU(VH^F=iF?biGUFj~Z(GVQ|=TkFa{!LP6tm)4S-l-Pv+? z=JVp^%fo;E_n)Ure4H+S7T{0qbz)-Hb{B7Hb#-+E!^77?dGGuM4?H8fX&|3RZX09O z)X%;mt|Ba37QE88cQVQy%&*7DD&F*0n~B4#5st#rvNif%M#2Ngz*lKinZM-WfzJEf z8&L^D%|>hl1g(H@GXZs90V%PxQz}YfuQNFrBQ7xrq=*!Foi8wdsKLt0iobl&PFlIM zM33?B2$FWI-4-Y8(a;30tWUM}TM^JY_mhPWb2P0=-p52E8cd29bZD~5zNzu??`&*j zN?|F2ZefE-v@w%YC3G<{ZyQe(4{8!pM18_~qaZC1lxNI4o@sLf{rv~35LZ{q=F8=0 z2?B^xY%x)SOjtkZx1X{hbqEzb7gzjkx(FwG1p!>Zcb^X9?N2TFucDO#^D z-*3|2Sm3P2MjYV$fsAHmWYDCP)G7I_^^*4Jl=;VmeJ@sj*w zx*%Vbo=@|B{jbLB?O_n#M~@Y{{<~2V7~{he?1xPFuOBz!&*FDKeg#bB#Dp3lIr(?R z>5zs7^tW%-!E>$i$I{XPol{e>z+i&UFa&Xb#iN>O2h+jleS-lmE{vxTFs6U;tFl|zhEjj zwL-WYL_{$0@mti{(_t$qv4av}p??n`@_?u2d}qnVFtB ziYcR|JZ}3pkH9Hi;TK)z+{^zs!kjjLIFC+Gfe~pNW?u?=tpAh1u+?|58ATnTCDHKI z_R}yfZxK4Es+ibrSWOcDi2%~gEvn$288>AqxrlD1>4)5m;gW(b+=;R5!c}Ost$YH} zP`J+xmymGNrxx!;X*aW;s&FEJ4-fxd)nAmzQA$(L)_x9!LjUA4o(Yb?N+DK%)g?e# z0X`U-n3z!T0Hd?*mTqR6v%I#Z@Zp2->zE)AO>!I$Hod+aDAaGVa9S=MRQMaqzOu75 z?R2%!1_3a*uw1ig?0B4Ny#|rhesRMZeCl#O_qJYnxqt1CS@dv*y^gZQGt5@7T6&&u?t(*tU0U+qP}n zx9`1+yZc{7baYi@S9V85M`TszmtWrdvw&&a3e zU^0^US$>I2VpB>NJ|bXc64Y+$X-j2#4p=}%MjS^$Lm5^iw2SJ(|e@6@tM`r3V*dJJkI}b9Kslc#s$6R*jm%`c&_3 zI9raj;XS+Hv5oySHvIqrwDBK=Ecf$1Mzz3HrYC`PBC)w}jgW zo&N5gN48K=P#K!+%LkVptE*A`%iS<-dC(-cpm+Mrfgy;V9xi9tR|FgYBvjk$H7KwT zP2b7CA|^m__jF(jZuok4K+F6UAI_Tb{{A6f z>cVzoRTVhWLb2L4aWr@LLV2KNr(^a~e}YqMLso=TBO`u(&TK}0!7e+#PO#21i))I2 z5VOXQDiM&>)s|nrN=NN8vAyHQ`vDLC!Dt)LIFP(kdY5~8xip~etsKk*=6@~EQ*7QN ziM&XshSD|F)r~~}pym_-Sbsb6IaTszsSO>xV>c;OA438(asH+$u-5w{OD{qx6
    • pkBCs}0iUlTX4vB4&?Kp^NHUDM4X zSq*lKFxDEfslR!sr^@W&-ssp*hpq%US@TgY9rQ+qtxMAp`v<}nctUIW{~mTa(ttgE=|esQ)!2a z#0aG!1GLoG=bRz+5sz+jS6c&)dTZI=TS&vvw>yMbfSxvQw*~Uw`iwxkkGaGYW=6AW zPm$bvnj9NA`Jb;4dY^ptn=Hi1g!k>=Z;;s7*f&MdR*MgT{rxn#A076K{HK&)(}IQS z>dL0*w*1Y*$7T|Z$m=O7ZhAj|8x%aF@0&{_6IE1**~59WaW?8`qF_%<9ovgd-9j3* z^(cE^0YmSy>*8C6iHg!BZxmm3EIm@1O+S+}7clzO;!8J4Y`+&*u@zw3$62k>VpbRF z4qYG;HLIV7h?H-g9m@mNI9L+mKhx6Q2cQf?ILM@2$khL~{sL>ZHBO}~8^c+dN$Oz_ zyWUr#SL)oO%PZ`FSY78}XtSBPyQcc=BuCB-2K@QcsBu#8&CP!qYY(sc$N~qOsV3^F zl5}{EfMQ}O5D2A`7jtoX4r2MmqBvNo$CAXt8!%zxO``8wvsMWl7s-gvCaAWx9#<@T z5^*tLS=Vm);xDCI4gO&H>Knf zJt;|tC+F(Y#Yrl&${4MF2Kgo-&PgJW6gHLR6dTfM+p&Ux(0l@Mu&5IWJU}G+9CB|t z&|7btgceaRDAr#HoLf@@-*TB@fbdh^1JGwp7RXzo$>lt@*~XYs-me#HJ&<|kqT@Vj zsc93?yMO0CS3c!JH^<5IQE`h=Nr|=m;oDNoCnw_}I!YS&Gd?gG$sH4;Ev+Jnkj^rK zx2z@S90^r^D8A0tAPb$zJ`%%WHsdPzGw`+l=5u{9^tAudrl+&=;{Meg7Dp%m2Qa@8 z1XSk?6V@w#J2a)}TGH3#5KysM7e_`dI32$)3)8vlC3axR06pF`RE);<$4Rf3EJ+;-!h<`ipiWy-`Z?A8Ea`K0qZd4tHPMK z_o(MGJ+FvZwpU*vgGASdmxpF-Fv$-L$}RJF2#L7@eX*;SZWkSJ+s@39vAE#^EyiJ6 z5tE#>#tBi-&|^E4%xXQxUJG}13;7!D9DNJz^-MZRF?y~9cd3o*K|PVI2R>x@rGPk# zu|93yGo#E}xEu{TtfO}nz{}Of3Q*dakA$M1pQ)u~xj4C;l(1oNbY5*OpOdD*ynJW< zrj?1!W_TVUx`Vh<+~*oNBaK{_GiC5Y8{?XYp;6>!Sq-RIZlvDE-t`&w{n^;DGeZ#U z7bOsOFx2P>gRUO0!Pkwj491-?E)(W-uLL0jV3N)%Y=q7`7Pn+a zP%z8b!rblafI&lxlW)&XeE9{~>0o~TrmL$fcv;O}Tst>Deh$lN&HZyV^v|@$i7e!e%Lo2-G|$`gtIPiE>$@7D6i)dpwUPOD7<7*ixqeMDK=L=}H- z&_$c!@2No!kC=CHfItUxtMD`7kW)lPAdGV9@{JLVl+rRW(Rm~oy;4~<2f|Iurf@H$ zMdvPzClf0=k)a-A;JxU`o$vA)a29nR(~ zD$+wT;^y|4QF6MBKQpFtiO);XwH7S3I;o#|4(y8n%Gkv1v zsw;VwK^t$E=`H%lgd62Y_C-x%D9cGZHuVGT9P^d=!%tZgZ%V9;j;D~S5MG9du^(E= z38IV2Wm}Y4(-8KQ&b4x$j`!Dc2paG)lE#O{}FhkFzIIf{v)B0#`1^I+uK{TE6OfEKah`}PT<*Y8vCH42AFU0e2`&!_T!Gd4oT5jW`r+gpNC(&5x zX$l-dmjHdM9`6@8mD`~Z{ZTE!u5k_eWvYzeJ8aM_o@LHv*wWCD5Xp)=*I`(^@`lf3WK=$xQW2XaTS`lq9W$u5(l zLjbqC0_ZSr9S|nLZ5iTWz}Q|Xp~)Y7(K+b4Db@|FzZ?YVw68ctpBGI}!z`#B&5^9I z)TJoCiz#GbM7W6jYxkKl8OVbvsuW$X`5YIp(>fv^1!A|sf=#VD(vRHFdsge@?k~K& zO-);Td}iR7V1ZP#D?|y@dXLsh*wf~O{~Vr3KU$X@ENI8HXW^X|jT={D+&=YAit6FfFR6S4a&r@30`cCfYrO+Mn%69} zAzI(Pc0I^I)BLTF60&t4PR5_w|_)ncSvTy87`%qnX zt7MzWr~;2#{X`Km+-RQlwydhE3IHY}f#&cMcY8ZRP@v{u+;GoqStTViG+cSYp;4DL zxCxM>?_cInDZMv?S#v+u-C^I?sI(5Za!P(5-(+Ay-t`S$A8Kbwzm2UeEKF{cP8`0| z{J?e62bg@S+@-;F3&F_X^c-3ForIl_Ey}Z)@Oo_XCYY9J?S6ZU_$+_$TtG(uD(H|? zSChx`cO&NQ?}*5C30vB1X5*!x$f5mz$)uVz4gPi@0bNbe8C`G)ZEYPlwgoqghrp)5 zCG(q;RTbUT*&({lyccY_jmGw~*R2SA^GN@LeLI6Q|sO?P1P@?aWkQSdI+^E2*%J1A&sH}Q>E6s*r_cI(# zBWgmJ)l*f@q5+D7pana=`wOR};cC)#dY+CbV1LE-EU2m{ZB#~cs|?R zF2IXQ%{x!>etnXbmm@$v2IA5BF1g6XfTXs;(>?UIP>3zdGP~H{)G5<M3D#GGAQl4y|U%tPDYhTi1N~ zIL*I4O>(2=6DHiM-5Ph}zjtp#h4RvE@{<}R;^_5_k=us&R@+R>6vBiByr$x9Odgpz zZ%)g5dxd7G-*?M;*rRzPb)JT7Z;Fb5A15_TXsX)V`8he=4*^x{*$7DK1lOSiUpQd# zKlpG+WIzd3U{VPQEx|%2FMo-Vs*8-ydP>t=7=^HvauYJfeKCT_n?|(lHMxlpB^^zo z>g)R>)k;6E_U)9y91Kw7)Bu;(vjpkY>z*^JPuJr^_St21*zd>G^b>@#2`D?EX9riRe(mn_KKv?cnODDj~jL0dyD|YzVr1i=s;EuX3yUz)YTSa9RglOii&y+ zs6Rv#c9Jmn_Ti!vJCCD1JzR_0dWwo$o14GWcWP?%mgXGmm2GR=|D}M+L41$HLl{rj zJ^&%VEM`e7Jn2&I8UmE%G)Ukw@I~PqfSspwqJf zk`j&)viXhe7ZmuF3n8Nld-Ez58msc%3hZj)kVYTH<4sk>87J`j^Ap>OdM+FG)AE&7 zLwJ~vgM?1o&?RbW0{@s)jO|g#KQzC-zT&)VonGlHIzR|(Rz^jhr}eKQ(s4P-6s)Mg zX!VLX%Vma8vkY~ZcZ<0ay zS)r1kE=1b$U$qY$PCsZr)Zc;_u6WMx^unm>i@oc1i)i9dw|GctXsWQ$Z!cajaa z(m4r#BPKShPtMU4u9NGVj(XJ1tmg{HMKIlh32=;MwKc)Y*w>bMQNqN&(NX1JZ;#7I zJ6`Zale&dtDZzfOvKd{L_gT`1c`do1A8z;lTMIA?&Q^U@$Yi&q-sqpRV9Y)6t<*fPnw59x$QG_nFu zvjPrEs@NoxSon9H{WHO3_OrZxHRCAE3_c{12Il%T$0^XsJiv>eKxTH*fk~Z!wxD z3>1q95~c{TDYXO(D8git7IpfrafiqJ&D>Ix?I|~RYQsyMCloT>gk&TbDefROa8U#r zRgmmIni+V*!zTL&dx=Q-fIUxj?gJ6U^Kl6V`DZ8#fD8N(dyMjB?;gRYl>mk|hf%Wza`-V zWurdQfCs6&#}{CH6I^tklnML9t#EiLinL#zR{Q=In_Bd$IJ}(cb>wA9b=axQf9*0j zY9u;eL+2@u@yypNu3!e!i!6stf(iJX7u7!ERIPJ9<3rWGW1TTFcBLV89aSxFvfBby zn_Z9BJr{)iTkXq#d#A{cdWPr3Z{Vj1#?R+=aa%T+(Z``zl>6IVMt>>q_Es zJls$6u{OXx3h+U6yUBZ;GOw>>Higz8N2XuQx$4Iaj-Q?rLYQ~a9-{z6)T1FK{mY)M z6-^yVEX%_?1259uVnF6s5`Pk>&3OP_V^}^H>!T8eX_3L-5Q78j*%y#@Ue%??y}N&$ z(J(Iq2I=Bw?GE5S36OVIn(8o-GKQWK+ZG^vJq2BtSMKol-+_?0=UAdeg#-0;w*g9@ z9mNyasHS6j{C&yby7HtO6Zx!PzJr1Al=)y3bLTf7%yij5ST#3KHE z0~&qFE%)Kx$bjF{+Jrto)0lvpuy});<^3+0BQ?`#FmA20hbw#SF6}aAi9CZs#C5k0 z%j}jJZFIlz+@`gFT576=-if(TP;HvlIbCObD99w5QvFe$%{6l zLq$Vj0Ozr3^%wPC!xNJW2bj57f&m<+JY0+!@bjIsfjvqmP}ITi;ac#+dW$pA0l?=Q zT*keLl4@^oXrM$rQN)FZb>!!KUh^XQ?U|L5vL%g2)|j~eb7|V8MpC3k(W|*tRhO6Q z&iTZQMT;?z}32hBG5k1l;KHLLk1RNPLSb?(S6(dByzbmD^h!_tqgBH?iS5dMv zj6I%v)(>iy^c8WpJ8qwFDMtOs2}|GrRb(!Ye=NhBWEtz}AQiyvUlp}72nN8%UN|Bx zv(?}ri)b~zX6>%UCQoLss0b`-tDQ9?jVjiFpm)WN7Rrg^r$Z(tSc!a}b}6cgpn@{; z)Ew4Q50^U)b&Q8p#lx%M+xoR{3InYJ*#PhO5cFwrrCxSvwith3--p+?OMK~p2||FB zgDHpyWEmfV?F|sS-x!JSvCnq_GWixjE%V}*{owhnSQdZ>RD>#?((hZTfp@M5UD{Eky_1ge{qGR(Cr zy9-!>+b5_2sW+KmEEIvSXOp$ThTjNG-nn*(z8)tJU8`%S;AzoLS>pOtDR~dbqrsb{ zCA14^1~RN-b&n1^)@4hSjh>1PS)v zja)C&$OgzQe9(Wmj61Ze*yg^$1gp>)QHpHeb5-va7~%3b-f`&sHlROYGc6nx9Wrv- z-?R0=sym#d5^*x5r{!wwc)yeUDa9f(&ejQgC3_Ofu?00eh0lA7 zEiFcbcVV9P774trN{vXZ`$$WXk$gOia8L44A9a=nC|7JNje{9Si*$&V`L%^w@JFtA zvhD!Swm+8yOtvRDpZrahHpo%qRvX6F!4mcymS#w6mExEhz`EKmY8EUJ{7zO?k`ZwChO*t#-$a&7N$OLZ1>DjnZ&`gT>|U%$vgU{rHI^5U%`O}lYB&O8g@!IxW|?Jh$9 zso12`F-vqYVI7wZM77JUpFAqAesS_u#;T^9$O=3--~WrHO6R_lm2!@IJV+L1w7e0c z*nhbJtJ6-tEX}_^X(1cp848^pJ^(O&zB5#)#?0-pL6mRbw3R)NCQ4~Wz=`=NjSKGC zp|7p%WIGXP-@d(Usf?OfDGbvXLG1fD#6;pEg9*@~`DswRROlYdG)@)gW(y1c2}I)}LkZB~ z`Om3mS?y*Qtk;cCc<5v{>IZ@Z5%_sfyj;j0PbE+1{^|SonGzy#vB3oR z(EL0YUM_TxrxvGk|I`)!6Ntveh7#b%60~h}YGSf_<5nW51FARM#9ACFeU(HpvIMHS z*GTEgD!7r{S|HP2R9boojE5AR>e@Q8xAeEK7~S}_MQeYQsxUVmT-#joGkAmKh00ds zldPBjc7IG~2yVRjWmpp2f3cxXa7?_(r`kRJI+M$AdBNU1+tx}CYphp$gOcU^Gymh+ z{>CoztkZ|XCJDaB$UEt^E*{MEG-sREwp!`TG9o+=h3b8WH z+F+9(HZ$4y!k`N;YBJte*PWFtSDS-NYlvZO5u;?V!I&9kTkU z>7-uA<~W(sm>@91FdF&nX5cz8QEV%?f<1`HhuRvPJ=K6Z2wY0O{!F7;V0 zbaZ{&D|8y0j_1emG!wrL&Sc~bUW3|t>5Y&sQcfV2t{+U1C#lB_`mG{Aa_VK0B04Zw z!bv>7DEkA>(=R$CAI&xGM7lt8%qRRo`&Zqh7Df7aW2oXZ5-d9HX|t31(z9*j8w5`c z*Ew109pF=E6`O& z1)wndL#Kn_x%&t11Cd)*j$!Q*=+jGfYmvy(5(oJo$jT^Wqzq=LiBJH)u+a-!X`$eP zm|!?;>Ox0$B!t(=jZ*ElHejHc(<4*<`NQ4oNJ&H`CqyDL28ZM!Yg&}iFC7U76pO1S z%v^;ctP1jYgH)Vdgn~9e!(4HnQ*>TZ0mxHC*9O`3)jR?gy0s8XQS;DObFHa{nqQCn z^_%tvx>9b2hUx+crJ<^mva+4Nl1Ni6!tzRrR>$hElFfR*_kM-NS%?IlT}ngVTA{06&S_U3GS<*ccpRXn>>N8avXC_qWr zaDiT!zERvRb;Hd`^s8B9GaxTRw6u8wf6+*EE1;i6rYTIWlCrMPQ*0R$Y>9}cS{D|q zX?YeMBxKS=sY296tD}VF-?%MWEXPY!~a#ZuqR)8}_v)fvn`x(YX8-C)?%f8hh5WL&X(?X54ZgP}rQydMZ_+@R7Rc^?oN;JAjQqjsLXjlxAWp}VoCLbSS#u9;ej3|+5erY*ZE=g1wMF7QAZ=j!wCH|w zu51Z{*CwXCxB*7rr*;U!S}e;z+#J2TOxGITH4w*f6+2t?mA+NWx@=$>s)B{5;`V7@ z%bKc;ZC^A0Do$9dgP+ziENU1dGS7C#u)24lH4rnB%}g^-UK2X;0voC?Ma-C%(NjN= zn3l1T-xDVt=hzoJ^f$aEpaY-1*#gRz7%}nU4ze#Q6i1saSfH5rcTFiH7$c6ANg&i! zEP~PozcAct!CDz`Qu7xFlLKx~_Nu%?1w7{k+q#=HDj&T6_j?;XELL7jRbx5?8R;pa zvXv^^Ph3+`x68e2k%X3f>{gi1H|&3!Vm{FkV;B|;ARyp-ARr>3#Q07Uz!m?8{RT%% z&r2KJxnb=r@m{LM^v($K# zjPXPGq33;;=>6#v;Mz?22t&M%5TfU$H)UPffC+)p&*96PQMQI7dmG@U-$}4N0-bf$ zt&p^GGG5LZ)bkQMP?wqqDD~<9*n&(rawN$<3ckatEWAB>eRP6kyE*`mKnJR~sNC;_ zlDt{#=xoH>xo7F`m$|zIWu2Q=(Cp9OUsx|p*_b}E_++{v)t3o^tMaRl;JstxmbR+ z=x-r0@W>)T@5n;4cs1iX`2mO%*sczU+9 zDEnkj5u84)Nk~PP#2!U6uc0`lgx)$m!Vk?e*|pOT%2sj`fIpzc9W7?Q`|;&^y_i4P zRLL+J@%w?23UWvHYi=)yxZswt1}k&bBuHrbNLU!-^34MUJAqp2{KC;)K+21JJK;rrf~||cCCUk0CCYzTy@3)DLL3hC(gT3<*oZ`E zK3t&}7F^t+>l;p8yyvVRfV47!AK4*hGa*;iS59{<<^(kg z0S#?G0UhE$YEj?7hyku_@P}rjOzJD_c}5E`f9rwKiMkeo*Uj2{6V3q?OIO?#8}%*o zf@Q5Vy|yl@(VMEma#0T4=2dGt>cwCW+nFU$@=a4LzQDBx!9J!MA}79FvYpmta06`p z@YqJ}1FVFr8}wh`F>>%kWV5bDN=#BN3us!X$$O2+WDNbm2_Rfns7)k?T`Z%nm-^y* zEn7zg=gogpYw(t3_2^DBe;mhK#aE?5>6mq-hUp>)CZUoj|j69I!W)n{a zz)z8phnX+EBh(XLqUOR-xp4dM3~{34Km@UgXS!Nse0h#wxLwELT)9oDWsdgf&i%7< zhZe@sDfG_H3V}j!E&4Rh_M90-^a~KQ;$kQ=dx^N?cB>J45I_JoPB4_@xh)`_oSE`p zWJ7$wG_bp1UXD0@*kr4@p~4Yk8xvL9%JNaJ+xs;Sv{W<*m6C8EE;e;^q84?MgS4uu z73T+PON2F*TKSdBpyw4Gv#PS^6^p9nl~e6n566(+zNRiNEDCqJ{UX;{}7jGV+`qT)!?DxA~&o5$2)N7s2W-#(U&Q=Ovcw z^Lsl?-0*Ex*F%}!lAnCHb+LrsJ)UQ9v3f@{X>MXqSEK+*{pz^7?W2>@VFdM%`_hzz zpHOm61&vpyU4*6EjsN0;MG3{bGFykrVl)@BUx3}~Iv}D&NI% zlM}whcXYI6KA#7&hw|qpAEV#zJ~$K>pAWc=NwdqegRz~SHweR!du-7b8~PQ2-#&@X zITXOTi5WTZ>^+M+X0}#@pHfbuJz~LZurcA?Xq_|P(6caYMeJB+;dDS>>z++>IHb@t z!nw4kfFGG2Ps~JvTyo%z#L!$e4t>is(cH>bsO_|1+P0+5al%3bEM2qfkF~cb9g8B~ z(4YA0)tRfN zg;MUOany{8fQdkz>Rl%=i?kjjdCtq?9wWeK;tbiiEccv2zNYy zo<8Y%*9!^Z2{dy^ndeq%gvQEsA65D8h#&Derk{%;h1JtqG-s1t~AL2=3Y#^7^P;?BOq@L`g|fIj1775Lz4b z1StxMB0-8T=5&0|=rv?NLUiwhU!zojp+^L8SRh8jkiLR!iUYRDf$+6GLP$d_+0R~? zNL56AVzvO=^H59B1*SiPRBP&?H8>f^8L`$KZNGg?TpZ4`Nz`&M)_;YT$~XZB4>Cf& z?r!y0GG*Ya9Ban<#pnCsihm1^YGA6>P6FU=2|hj#3fdlDnWruPbcZ?HM+bTU)DQzW z2}8L2%-Q?FN(1+u8Ow^&RUkG}40|iptxLK&0!%xkbH3`I~DcJVrhFuvC`5~!#q5E#RQcxm8yD0jfyTA z@0qDu9;do4+Oa~iD>k?ZY>equY>LWaKl-@;fgKe``AuGfO8crTI9yYkKcJL};>Z`e z?gnKXJ9-^u{Hjf40-F{vYV@@oHFlGWoU@T_t(S$DO>=S+8wOhZb8Ter;^L-7@7GtR z*r4*+KN+P@v_VSeXSj^Zi`D~FU7?><{Io2X({gR{swwr<`Ou_dzJrQ;NU298y1aeh>t3Djkf zu_hy#ub&(9c$~jOW!u?QYeGRaLM(iJMs)#Aln}Z@67l?nTHLUK^`hkv84W#JwY0n1 z^ja2xYfNgAzJKX2OKTAb`!ZIZ)f7!3ORy9{;~O%hZ6k&!oae0g_I^r)yyrBw4FKW_eyNo|+Gdi-S!`b8SDYzDHWcoDXxsd#thusLI-p%tI+$OI2fZLL#h zc?^t9IlxKjr-BB0WZO55!k17AcAJf!LFYUQHWe*FT3Zt!{QXXb2-3t2RkUDTAPX7b z)QT6NrONs^vZMlDW|gTd6dmn;qAWClYkNW{moyO7_e0&&{pDQOH7t3{Xj^MJ^qfJx zt!Hd<%WG4M9fc|4B3XFA?i<(n>=dsEN%OK_v8)h2)sLx8Z!J0|UC(YKGNxoh@BK$z zy%?1t`_>$A9P5KfiC2}-lgQ0ezM@o{8=+U5?Y-jn4l6SAJD*U=xotQ<+pMPS`GU%2 zg3P}J2zw8(0!8R3x#r?RhE)-???YxnzwaXs)~5GWLPzxdTVF(@(Xy^cNkeQM(6-?ZmIj)p>A$+4j4Xe>KgmyOxNiD6Hw;apO`T^CWXnDGk@Rgndjp8vG;P`ClXb$p8aA47C?ZkU!}Z-7l(%VX8!8)ckb zWj`I@C1o7vj`Sr(MQp^$JUyeJB{H~Ys(W7eDv!LyO<0-g@-Y7|tQKCQ3D`3WT1x&c zsvalc7_HtVW1#ecEwz?+OheqqfmGByZ?|_% zNiiC_TY0zB=g!H)Jwn;}{(CWC≧K-cH|YeWUB%NgRLx(}@KsSLtC%B=MVdFnrBg&DJ(dqxzmBR@$&i2ak~IBOWu_-f7du?#s5x z`^#3R1EUp7iBe^5&>Tc1S(P79e7=V52h|0~t0USGTHl)BW_`N^Yeh)v2`j$snnek4 z7XTpau7JB8v5Z^^H>{aS>fo{R2GtQRfQ;q+evtN5j7AFym`qp{O?w@&Y8rMbh9ra9 zPNFFA>XrrAxpFM9tR5J)b*X-`uhyc8~YBS$T5W>b2A9JMj5+J&zs~> zEE+TpQb+cCQfCqmw5-d<3x>jmH#BA;j%4^W*pKtv z9(p53A+PrkHuJJV5~JM4cXWVL``{&$y8GC^PJP*2M(o;3M66n#U?Tv8Q6E#AJ87&# zi5cP*9#J1_v2k@no68DegU(5NyRq{K>;@{H|(KWvjI zaf;{%3va~k=r;un;;IMrEa(t%`FmJfgc=OD*&qy@(a%9ngKB!4m55trz4kqKbAI11 zMNy0sW%obfkULC+Df~?eM&^4CVhjffw+4pkc~wjXz?NU8>RRcYgh2sF@ftphze~Q%DvD$B zP-aIgJ*KYq;;Q0hUo&rMw`ETR@Vr}mB3g?}iM=}jMiVnWIaww`l1{BroEnIT5=i+K^6?zuCLaQ zCzxdYjN5|p2~8Ls78HCmyaZ%^FBS(+4>{;yFh^cHTtc}e$xhWN_VAKHf^Xu3-+2FJ zFC`>hYKTeoQ^+}S^CXx`bjqM;Du)$^3>_oIew>pVyGCXH4jb(ZV^(0t_Z+b#pu5F8JwKI_cec;`dQFE1Yz^3 zpa&n2CSd{k3A$lL>shBsLNzX!gZpN{MIBHICMxn-)MKKFg>)r^A2DD+TmnLYmb|dg z^GlV*=nU~t&-+mzBrxgfmSX9USF57QE6>BPSuo>SnpRQ)TCS=>wn51S*Fv_#%pHO2 zC390mZ6ra5Rpx&()NN!AKgym(nSWUuLD4>}1`q>CIG0b`jWT0YSVP1`cTXCza<0sh zj|}O}7tJ(aM5H!7QK{J}Up8GaB64px-jvSg<8$l|62YQ(`bUs*0pN)zo*7nU^K_p^o@9xFGDuVV|$kmS0>zHzNtS}AOr>QvZjvg)p&G*?ef^e|~btR#30a>$o z5869r{hmAckQQQfXcMx9d`f+(Iz!)ySbDnM&s%qf$JMSh9LNbMVPu-e<3p6ymgBTz zbaWb`E@v#QE@_00_K^!6&V^E5$D$Krt#l@82yIu(oDY)1*)bMPP{VDK11m&gH%JFm zM&T59_2u~%zUhSZ9y#=4h=De5g+R(2o@0q)(+mXJpo{OZxgWUo_TRC4`Z1dMU69uq zFWOmD9=keU{<;_j;RSL-GYASvwRfx&gBc!aP87h#Skb44i?VpnTsKl4^1@oECRwOn zOM=39PldZf8rHVArrxqQsfbCb3?m2N{Q%Q7ZjFgJn}%6OU4_n$I}rT#*M#jC$#5B< zl0s#YZA9y^Nv2n+Jg#lre?|d!Dczb^s2a;Ob>0pfl0_Ao*Tdw12+_ITZ^Y2nc#%IF zwCR?R^xUNrPBN><1Tz$g)jNbNv92|my8Lip!okn(#;z|aB9iHVYw=s zkBa%-UJXXoeC2r+1_1k=?(~gmpX%>8#3G~mBYu;$?KOrWcgFU!rTwu2_UNQ{0w!dH zAF?N+ZSBnf7NBTUgZ!e(LbUIcdQIjZ07tApkkSL|n$f!>2T(7uFXMU*5MjUn>=t50 z*$f&%A*@()60z3g-soOt!=VF+7i2FZ54xZioE#MIBzhmRgfj7|6goOm6oK?9EQtK= z+FmKRwbbC94iY_M@<^d!;Do&4tkgrPARup$2FE%My5{EA%J26v?KyT7^@x@cAYt6r zjELP*q+D^zG&*FLJi*}nmZhg|K=(`87rI zHeH6FL(VI}bLrWMVo91~+fr!Ms+fSwF)JPZv($4pEG}Vdbi;VEpp2YZ%5id%2NOx; znI>J4(#&q3@pb&66XzG|j%(m~h?Cp=26IoO4kfU(-ei}B0F1}eK7d_}Q&!4PzdWL{ zK)e0a6#sqazRs=wOq>Am5}Rz$e1p1ti2AD4Cng6l@IDvkJNRs6#{D6FDDYgcx-&ZC z>tMDNMJpf|nJw_9cYkYi6&4{~ftjIW<1_X(CR$(XI)R8Hu+iKc8Pnl+D)=_Dxgp|* ze_Sp&7EaG7_AtQ~Zsudg%bT1xl)U=P)r`cux@vPw_b|&R7-2>`^{-4TF43R{$Kq|S zN2?Z~SrFTkuhM3P+OlmfXk{>EqM8-wX!WOgLL#>m2%L4TVr`|-uJ8<9|2B`VU-i%f z)Vz;3rW(j8UE)Eee}HUTw=2?Yyj4e5gj4+@^urg8zX=bsY&#-P@)xc1zXEy2IhS(M zaH<77OY|}ngG_KTL0h7VY-0+hGOQ+I9B49tCFwml9fEt@D${Ti0)F62rC+6K-8Gsh zYgzW%sbW0yh)ar=0sl&GLOdvTMkA`ly9P(QNNCgSk_WD;q7VQ1nYnqOdb`ocih?I7Kx2vu>gB@anrb)U zI9V%w0Y_-Xcwz5B2r?bWC70;~jE1hPLhmPU5Z;Wl*n`I>zV00Y)gy2Re=ai@$;p&b z3q%x|m5Z*u?K1^`?cTy`Z)xvbRT?H{?XMpwgv(*cbK7ZoU%XeEA7$2f=U@ULO))pV zo6g(%0)H+J8yxw*u3|i5Fn{K-$a=rkgdncShO7trX;E|Q*iAq09OIV(cbQvJbsvKn zz8un5GgbHvapnA`R{|aKSN^)snw+);QD3!ESPR|8oRfNg-BP*Bzi6!m>%Gmw zs`yO^jGfHZxcZu(ZPGlBd|NHDFG~rueu1E58n~P8x^mSqYOf! zSqU0XUkB4Of76R1@ZN6u33+d~T&#kQ&~#kx`^YSxgGe+7>WFTFTe~^(8K%O0a1Z0k z0=aLQ6bcx$;nnLazs5co>@Xgx-MWojYFB~33i||j$2N8401>VMd|37&I(e+2^>SD~ zdl7FP!Uevb;c4hq&Z&SM(Q3@kJ zq)%aAMg1#^eedD+Em;-<;@q%g0pmk+GMCJP>);wYO*KUM-Ko25duu*4=P)ehVIcU@ z(TG_WwF3botO%Teb!2N%gGyK%RBxhXcPoirPvgW6pNnq5q5IeHXP&-+uUOYQ3vJHB zC*Kd^`m?bW;!k%h>UG^2+xL60)`{@nJ35-5qAGhKZQe_VYx|qklmf1l(uIuuXsMVC z;})~?tQEK@+zKhQEyopm#LSO38HWxnAeJw_|b|3VhjCmh?~gL#tEVY z^WWXjHbUJ0Q%79`2#8ZUzAYn*3*KvH!Oe_`mNTiD2#Gz^92a z?UEp1hKU4**oigmNO=E^Qw0YCIwSc1Ct#W=$JH+t* zF9rz+=-<@;ZvXS5@<0Egpg4*8ofx?P6&?M*!O{QsA>zb8ove8OXH!531cdb;O5$r1 S>uPZl-#U>XdYk`C^1lEpqc`dR