308 lines
9.9 KiB
ArmAsm
308 lines
9.9 KiB
ArmAsm
/**
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******************************************************************************
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* @file startup_MCP.s
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* @author Vector / NIIET
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* @version V1.0.0
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* @date 28 - September - 2014
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* @brief NIIET MC01 vector table for Sourcery Codebench.
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* This module performs:
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* - Set the initial SP
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* - Set the initial PC == Reset_Handler,
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* - Set the vector table entries with the exceptions ISR address
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* - Branches to main in the C library (which eventually
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* calls main()).
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* - enables FPU (COMING SOON!)
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* After Reset the Cortex-M4 processor is in Thread mode,
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* priority is Privileged, and the Stack is set to Main.
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*/
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.syntax unified
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.cpu cortex-m3
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.fpu vfpv4
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.thumb
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.global g_pfnVectors
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.global Default_Handler
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/* start address for the initialization values of the .data section.
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defined in linker script */
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.word _sidata
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/* start address for the .data section. defined in linker script */
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.word _sdata
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/* end address for the .data section. defined in linker script */
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.word _edata
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/* start address for the .bss section. defined in linker script */
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.word _sbss
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/* end address for the .bss section. defined in linker script */
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.word _ebss
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/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
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/**
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* @brief This is the code that gets called when the processor first
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* starts execution following a reset event. Only the absolutely
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* necessary set is performed, after which the application
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* supplied main() routine is called.
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* @param None
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* @retval : None
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*/
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.section .text.Reset_Handler
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.weak Reset_Handler
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.type Reset_Handler, %function
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Reset_Handler:
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/* Copy the data segment initializers from flash to SRAM */
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movs r1, #0
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b LoopCopyDataInit
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CopyDataInit:
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ldr r3, =_sidata
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ldr r3, [r3, r1]
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str r3, [r0, r1]
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adds r1, r1, #4
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LoopCopyDataInit:
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ldr r0, =_sdata
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ldr r3, =_edata
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adds r2, r0, r1
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cmp r2, r3
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bcc CopyDataInit
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ldr r2, =_sbss
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b LoopFillZerobss
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/* Zero fill the bss segment. */
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FillZerobss:
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movs r3, #0
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str r3, [r2], #4
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LoopFillZerobss:
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ldr r3, = _ebss
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cmp r2, r3
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bcc FillZerobss
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/* <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>*/
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ldr.w R0, =0xE000ED88
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ldr R1, [R0]
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orr R1, R1, #(0xF << 20)
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str R1, [R0]
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dsb
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isb /*reset pipeline now the FPU is enabled*/
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ldr r0, = _estack /* <EFBFBD><EFBFBD><EFBFBD> <EFBFBD><EFBFBD><EFBFBD> <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> - <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> SP <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> 2000<EFBFBD>000 <EFBFBD> <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>, <EFBFBD><EFBFBD><EFBFBD><EFBFBD> <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>. <EFBFBD><EFBFBD><EFBFBD><EFBFBD> <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <EFBFBD><EFBFBD> <EFBFBD><EFBFBD><EFBFBD><EFBFBD> - <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>.*/
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msr msp, r0 /* ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^*/
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bl main
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bx lr
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.size Reset_Handler, .-Reset_Handler
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/**
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* @brief This is the code that gets called when the processor receives an
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* unexpected interrupt. This simply enters an infinite loop, preserving
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* the system state for examination by a debugger.
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* @param None
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* @retval None
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*/
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.section .text.Default_Handler,"ax",%progbits
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Default_Handler:
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Infinite_Loop:
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b Infinite_Loop
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.size Default_Handler, .-Default_Handler
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/******************************************************************************
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*
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* The minimal vector table for a Cortex M3. Note that the proper constructs
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* must be placed on this to ensure that it ends up at physical address
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* 0x0000.0000.
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*
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*******************************************************************************/
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.section .isr_vector,"a",%progbits
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.type g_pfnVectors, %object
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.size g_pfnVectors, .-g_pfnVectors
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g_pfnVectors:
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.word _estack
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.word Reset_Handler
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.word NMI_Handler
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.word HardFault_Handler
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.word MemManage_Handler
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.word BusFault_Handler
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.word UsageFault_Handler
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.word 0
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.word 0
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.word 0
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.word 0
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.word SVC_Handler
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.word DebugMon_Handler
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.word 0
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.word PendSV_Handler
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.word SysTick_Handler
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.word WDT_IRQHandler
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.word RCU_IRQHandler
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.word MFLASH_IRQHandler
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.word GPIOA_IRQHandler
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.word GPIOB_IRQHandler
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.word DMA_CH0_IRQHandler
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.word DMA_CH1_IRQHandler
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.word DMA_CH2_IRQHandler
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.word DMA_CH3_IRQHandler
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.word DMA_CH4_IRQHandler
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.word DMA_CH5_IRQHandler
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.word DMA_CH6_IRQHandler
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.word DMA_CH7_IRQHandler
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.word DMA_CH8_IRQHandler
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.word DMA_CH9_IRQHandler
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.word DMA_CH10_IRQHandler
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.word DMA_CH11_IRQHandler
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.word DMA_CH12_IRQHandler
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.word DMA_CH13_IRQHandler
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.word DMA_CH14_IRQHandler
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.word DMA_CH15_IRQHandler
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.word TMR0_IRQHandler
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.word TMR1_IRQHandler
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.word TMR2_IRQHandler
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.word TMR3_IRQHandler
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.word UART0_TD_IRQHandler
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.word UART0_RX_IRQHandler
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.word UART0_TX_IRQHandler
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.word UART0_E_RT_IRQHandler
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.word UART1_TD_IRQHandler
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.word UART1_RX_IRQHandler
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.word UART1_TX_IRQHandler
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.word UART1_E_RT_IRQHandler
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.word SPI_RO_RT_IRQHandler
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.word SPI_RX_IRQHandler
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.word SPI_TX_IRQHandler
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.word I2C_IRQHandler
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.word ECAP0_IRQHandler
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.word ECAP1_IRQHandler
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.word ECAP2_IRQHandler
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.word PWM0_IRQHandler
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.word PWM0_HD_IRQHandler
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.word PWM0_TZ_IRQHandler
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.word PWM1_IRQHandler
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.word PWM1_HD_IRQHandler
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.word PWM1_TZ_IRQHandler
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.word PWM2_IRQHandler
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.word PWM2_HD_IRQHandler
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.word PWM2_TZ_IRQHandler
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.word QEP_IRQHandler
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.word ADC_SEQ0_IRQHandler
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.word ADC_SEQ1_IRQHandler
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.word ADC_DC_IRQHandler
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.word CAN0_IRQHandler
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.word CAN1_IRQHandler
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.word CAN2_IRQHandler
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.word CAN3_IRQHandler
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.word CAN4_IRQHandler
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.word CAN5_IRQHandler
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.word CAN6_IRQHandler
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.word CAN7_IRQHandler
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.word CAN8_IRQHandler
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.word CAN9_IRQHandler
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.word CAN10_IRQHandler
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.word CAN11_IRQHandler
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.word CAN12_IRQHandler
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.word CAN13_IRQHandler
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.word CAN14_IRQHandler
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.word CAN15_IRQHandler
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.word FPU_IRQHandler
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/*******************************************************************************
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*
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* Provide weak aliases for each Exception handler to the Default_Handler.
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* As they are weak aliases, any function with the same name will override
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* this definition.
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*
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*******************************************************************************/
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/* Macro to define default handlers. Default handler
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* will be weak symbol and just dead loops. They can be
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* overwritten by other handlers */
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.macro def_irq_handler handler_name
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.weak \handler_name
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.thumb_set \handler_name, Default_Handler
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.endm
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def_irq_handler NMI_Handler
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def_irq_handler HardFault_Handler
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def_irq_handler MemManage_Handler
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def_irq_handler BusFault_Handler
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def_irq_handler UsageFault_Handler
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def_irq_handler SVC_Handler
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def_irq_handler DebugMon_Handler
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def_irq_handler PendSV_Handler
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def_irq_handler SysTick_Handler
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/* External Interrupt Handlers */
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def_irq_handler WDT_IRQHandler
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def_irq_handler RCU_IRQHandler
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def_irq_handler MFLASH_IRQHandler
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def_irq_handler GPIOA_IRQHandler
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def_irq_handler GPIOB_IRQHandler
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def_irq_handler DMA_CH0_IRQHandler
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def_irq_handler DMA_CH1_IRQHandler
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def_irq_handler DMA_CH2_IRQHandler
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def_irq_handler DMA_CH3_IRQHandler
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def_irq_handler DMA_CH4_IRQHandler
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def_irq_handler DMA_CH5_IRQHandler
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def_irq_handler DMA_CH6_IRQHandler
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def_irq_handler DMA_CH7_IRQHandler
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def_irq_handler DMA_CH8_IRQHandler
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def_irq_handler DMA_CH9_IRQHandler
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def_irq_handler DMA_CH10_IRQHandler
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def_irq_handler DMA_CH11_IRQHandler
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def_irq_handler DMA_CH12_IRQHandler
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def_irq_handler DMA_CH13_IRQHandler
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def_irq_handler DMA_CH14_IRQHandler
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def_irq_handler DMA_CH15_IRQHandler
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def_irq_handler TMR0_IRQHandler
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def_irq_handler TMR1_IRQHandler
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def_irq_handler TMR2_IRQHandler
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def_irq_handler TMR3_IRQHandler
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def_irq_handler UART0_TD_IRQHandler
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def_irq_handler UART0_RX_IRQHandler
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def_irq_handler UART0_TX_IRQHandler
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def_irq_handler UART0_E_RT_IRQHandler
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def_irq_handler UART1_TD_IRQHandler
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def_irq_handler UART1_RX_IRQHandler
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def_irq_handler UART1_TX_IRQHandler
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def_irq_handler UART1_E_RT_IRQHandler
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def_irq_handler SPI_RO_RT_IRQHandler
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def_irq_handler SPI_RX_IRQHandler
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def_irq_handler SPI_TX_IRQHandler
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def_irq_handler I2C_IRQHandler
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def_irq_handler ECAP0_IRQHandler
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def_irq_handler ECAP1_IRQHandler
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def_irq_handler ECAP2_IRQHandler
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def_irq_handler PWM0_IRQHandler
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def_irq_handler PWM0_HD_IRQHandler
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def_irq_handler PWM0_TZ_IRQHandler
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def_irq_handler PWM1_IRQHandler
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def_irq_handler PWM1_HD_IRQHandler
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def_irq_handler PWM1_TZ_IRQHandler
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def_irq_handler PWM2_IRQHandler
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def_irq_handler PWM2_HD_IRQHandler
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def_irq_handler PWM2_TZ_IRQHandler
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def_irq_handler QEP_IRQHandler
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def_irq_handler ADC_SEQ0_IRQHandler
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def_irq_handler ADC_SEQ1_IRQHandler
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def_irq_handler ADC_DC_IRQHandler
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def_irq_handler CAN0_IRQHandler
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def_irq_handler CAN1_IRQHandler
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def_irq_handler CAN2_IRQHandler
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def_irq_handler CAN3_IRQHandler
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def_irq_handler CAN4_IRQHandler
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def_irq_handler CAN5_IRQHandler
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def_irq_handler CAN6_IRQHandler
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def_irq_handler CAN7_IRQHandler
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def_irq_handler CAN8_IRQHandler
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def_irq_handler CAN9_IRQHandler
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def_irq_handler CAN10_IRQHandler
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def_irq_handler CAN11_IRQHandler
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def_irq_handler CAN12_IRQHandler
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def_irq_handler CAN13_IRQHandler
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def_irq_handler CAN14_IRQHandler
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def_irq_handler CAN15_IRQHandler
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def_irq_handler FPU_IRQHandler
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