230 lines
6.8 KiB
C
230 lines
6.8 KiB
C
/**
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******************************************************************************
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* @file py32f002b_ll_utils.c
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* @author MCU Application Team
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* @brief UTILS LL module driver.
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******************************************************************************
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* @attention
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*
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* <h2><center>© Copyright (c) Puya Semiconductor Co.
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* All rights reserved.</center></h2>
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*
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* <h2><center>© Copyright (c) 2016 STMicroelectronics.
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* All rights reserved.</center></h2>
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*
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* This software component is licensed by ST under BSD 3-Clause license,
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* the "License"; You may not use this file except in compliance with the
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* License. You may obtain a copy of the License at:
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* opensource.org/licenses/BSD-3-Clause
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*
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******************************************************************************
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*/
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/* Includes ------------------------------------------------------------------*/
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#include "py32f002b_ll_utils.h"
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#include "py32f002b_ll_rcc.h"
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#include "py32f002b_ll_system.h"
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#ifdef USE_FULL_ASSERT
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#include "py32_assert.h"
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#else
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#define assert_param(expr) ((void)0U)
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#endif /* USE_FULL_ASSERT */
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/** @addtogroup PY32F002B_LL_Driver
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* @{
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*/
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/** @addtogroup UTILS_LL
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* @{
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*/
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/* Private types -------------------------------------------------------------*/
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/* Private variables ---------------------------------------------------------*/
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/* Private constants ---------------------------------------------------------*/
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/** @addtogroup UTILS_LL_Private_Constants
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* @{
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*/
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/* Defines used for FLASH latency according to HCLK Frequency */
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#define UTILS_SCALE1_LATENCY1_FREQ 24000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 1 */
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#define UTILS_SCALE1_LATENCY2_FREQ 48000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 1 */
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/**
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* @}
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*/
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/* Private macros ------------------------------------------------------------*/
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/** @addtogroup UTILS_LL_Private_Macros
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* @{
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*/
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#define IS_LL_UTILS_SYSCLK_DIV(__VALUE__) (((__VALUE__) == LL_RCC_SYSCLK_DIV_1) \
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|| ((__VALUE__) == LL_RCC_SYSCLK_DIV_2) \
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|| ((__VALUE__) == LL_RCC_SYSCLK_DIV_4) \
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|| ((__VALUE__) == LL_RCC_SYSCLK_DIV_8) \
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|| ((__VALUE__) == LL_RCC_SYSCLK_DIV_16) \
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|| ((__VALUE__) == LL_RCC_SYSCLK_DIV_64) \
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|| ((__VALUE__) == LL_RCC_SYSCLK_DIV_128) \
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|| ((__VALUE__) == LL_RCC_SYSCLK_DIV_256) \
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|| ((__VALUE__) == LL_RCC_SYSCLK_DIV_512))
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#define IS_LL_UTILS_APB1_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB1_DIV_1) \
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|| ((__VALUE__) == LL_RCC_APB1_DIV_2) \
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|| ((__VALUE__) == LL_RCC_APB1_DIV_4) \
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|| ((__VALUE__) == LL_RCC_APB1_DIV_8) \
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|| ((__VALUE__) == LL_RCC_APB1_DIV_16))
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#define IS_LL_UTILS_HSE_BYPASS(__STATE__) (((__STATE__) == LL_UTILS_HSEBYPASS_ON) \
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|| ((__STATE__) == LL_UTILS_HSEBYPASS_OFF))
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/**
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* @}
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*/
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/* Exported functions --------------------------------------------------------*/
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/** @addtogroup UTILS_LL_Exported_Functions
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* @{
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*/
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/** @addtogroup UTILS_LL_EF_DELAY
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* @{
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*/
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/**
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* @brief This function configures the Cortex-M SysTick source to have 1ms time base.
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* @note When a RTOS is used, it is recommended to avoid changing the Systick
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* configuration by calling this function, for a delay use rather osDelay RTOS service.
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* @param HCLKFrequency HCLK frequency in Hz
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* @note HCLK frequency can be calculated thanks to RCC helper macro or function @ref LL_RCC_GetSystemClocksFreq
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* @retval None
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*/
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void LL_Init1msTick(uint32_t HCLKFrequency)
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{
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/* Use frequency provided in argument */
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LL_InitTick(HCLKFrequency, 1000U);
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}
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/**
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* @brief This function provides accurate delay (in milliseconds) based
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* on SysTick counter flag
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* @note When a RTOS is used, it is recommended to avoid using blocking delay
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* and use rather osDelay service.
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* @note To respect 1ms timebase, user should call @ref LL_Init1msTick function which
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* will configure Systick to 1ms
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* @param Delay specifies the delay time length, in milliseconds.
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* @retval None
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*/
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void LL_mDelay(uint32_t Delay)
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{
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__IO uint32_t tmp = SysTick->CTRL; /* Clear the COUNTFLAG first */
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uint32_t tmpDelay; /* MISRAC2012-Rule-17.8 */
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/* Add this code to indicate that local variable is not used */
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((void)tmp);
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tmpDelay = Delay;
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/* Add a period to guaranty minimum wait */
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if (tmpDelay < LL_MAX_DELAY)
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{
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tmpDelay ++;
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}
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while (tmpDelay != 0U)
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{
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if ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) != 0U)
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{
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tmpDelay --;
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}
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}
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}
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/**
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* @}
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*/
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/**
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* @brief This function sets directly SystemCoreClock CMSIS variable.
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* @note Variable can be calculated also through SystemCoreClockUpdate function.
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* @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro)
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* @retval None
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*/
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void LL_SetSystemCoreClock(uint32_t HCLKFrequency)
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{
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/* HCLK clock frequency */
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SystemCoreClock = HCLKFrequency;
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}
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/**
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* @brief Update number of Flash wait states in line with new frequency and current
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* voltage range.
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* @param HCLKFrequency HCLK frequency
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* @retval An ErrorStatus enumeration value:
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* - SUCCESS: Latency has been modified
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* - ERROR: Latency cannot be modified
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*/
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ErrorStatus LL_SetFlashLatency(uint32_t HCLKFrequency)
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{
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uint32_t timeout;
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uint32_t getlatency;
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uint32_t latency;
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ErrorStatus status;
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/* Frequency cannot be equal to 0 or greater than max clock */
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if ((HCLKFrequency == 0U) || (HCLKFrequency > UTILS_SCALE1_LATENCY2_FREQ))
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{
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status = ERROR;
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}
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else
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{
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if (HCLKFrequency > UTILS_SCALE1_LATENCY1_FREQ)
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{
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/* 24 < HCLK <= 48 => 1WS (2 CPU cycles) */
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latency = LL_FLASH_LATENCY_1;
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}
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else
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{
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/* else HCLKFrequency < 24MHz default LL_FLASH_LATENCY_0 0WS */
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latency = LL_FLASH_LATENCY_0;
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}
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}
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LL_FLASH_SetLatency(latency);
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/* Check that the new number of wait states is taken into account to access the Flash
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memory by reading the FLASH_ACR register */
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timeout = 2u;
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do
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{
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/* Wait for Flash latency to be updated */
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getlatency = LL_FLASH_GetLatency();
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timeout--;
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}
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while ((getlatency != latency) && (timeout > 0u));
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if (getlatency != latency)
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{
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status = ERROR;
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}
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else
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{
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status = SUCCESS;
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}
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return status;
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}
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/**
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* @}
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*/
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/**
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* @}
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*/
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/**
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* @}
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*/
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/**
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* @}
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*/
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/************************ (C) COPYRIGHT Puya *****END OF FILE****/
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