401 lines
14 KiB
C
401 lines
14 KiB
C
/**
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******************************************************************************
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* @file py32f002b_hal_pwr.c
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* @author MCU Application Team
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* @brief PWR HAL module driver.
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* This file provides firmware functions to manage the following
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* functionalities of the Power Controller (PWR) peripheral:
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* + Initialization/de-initialization functions
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* + Peripheral Control functions
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*
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******************************************************************************
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* @attention
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*
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* <h2><center>© Copyright (c) Puya Semiconductor Co.
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* All rights reserved.</center></h2>
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*
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* <h2><center>© Copyright (c) 2016 STMicroelectronics.
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* All rights reserved.</center></h2>
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*
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* This software component is licensed by ST under BSD 3-Clause license,
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* the "License"; You may not use this file except in compliance with the
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* License. You may obtain a copy of the License at:
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* opensource.org/licenses/BSD-3-Clause
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*
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******************************************************************************
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*/
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/* Includes ------------------------------------------------------------------*/
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#include "py32f0xx_hal.h"
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/** @addtogroup PY32F002B_HAL_Driver
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* @{
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*/
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/** @addtogroup PWR
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* @{
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*/
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#ifdef HAL_PWR_MODULE_ENABLED
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/* Private typedef -----------------------------------------------------------*/
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/* Private define ------------------------------------------------------------*/
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/* Private macro -------------------------------------------------------------*/
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/* Private variables ---------------------------------------------------------*/
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/* Private function prototypes -----------------------------------------------*/
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/* Exported functions --------------------------------------------------------*/
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/** @addtogroup PWR_Exported_Functions PWR Exported Functions
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* @{
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*/
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/** @addtogroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions
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* @brief Initialization and de-initialization functions
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*
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@verbatim
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===============================================================================
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##### Initialization and de-initialization functions #####
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===============================================================================
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[..]
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@endverbatim
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* @{
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*/
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/**
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* @brief Deinitialize the HAL PWR peripheral registers to their default reset
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values.
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* @retval None
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*/
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void HAL_PWR_DeInit(void)
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{
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__HAL_RCC_PWR_FORCE_RESET();
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__HAL_RCC_PWR_RELEASE_RESET();
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}
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/**
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* @}
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*/
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/** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control functions
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* @brief Low Power modes configuration functions
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*
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@verbatim
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===============================================================================
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##### Peripheral Control functions #####
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===============================================================================
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[..]
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*** PVD configuration ***
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=========================
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[..]
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(+) The PVD is used to monitor the VDD power supply by comparing it to a
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threshold selected by the PVD Level (PVDT[2:0]bits in PWR CR2 register).
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(+) PVDO flag is available to indicate if VDD/VDDA is higher or lower
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than the PVD threshold. This event is internally connected to the EXTI
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line 16 and can generate an interrupt if enabled.
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(+) The PVD is stopped in Standby mode.
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*** WakeUp pin configuration ***
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================================
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[..]
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(+) WakeUp pins are used to wakeup the system from Standby mode or
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Shutdown mode. WakeUp pins polarity can be set to configure event
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detection on high level (rising edge) or low level (falling edge).
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*** Low Power mode configuration ***
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=====================================
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[..]
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The devices feature 7 low-power modes:
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(+) Low-power run mode: core and peripherals are running at low frequency.
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Regulator is in low power mode.
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(+) Sleep mode: Cortex-M0+ core stopped, peripherals kept running,
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regulator is main mode.
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(+) Low-power Sleep mode: Cortex-M0+ core stopped, peripherals kept running
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and regulator in low power mode.
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(+) Stop 0 mode: all clocks are stopped except LSI and LSE, regulator is
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main mode.
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(+) Stop 1 mode: all clocks are stopped except LSI and LSE, main regulator
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off, low power regulator on.
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*** Low-power run mode ***
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==========================
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[..]
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(+) Entry: (from main run mode)
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(++) set LPR bit with HAL_PWREx_EnableLowPowerRunMode() API after
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having decreased the system clock below 2 MHz.
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(+) Exit:
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(++) clear LPR bit then wait for REGLPF bit to be reset with
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HAL_PWREx_DisableLowPowerRunMode() API. Only then can the
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system clock frequency be increased above 2 MHz.
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*** Sleep mode / Low-power sleep mode ***
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=========================================
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[..]
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(+) Entry:
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The Sleep & Low-power Sleep modes are entered through
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HAL_PWR_EnterSLEEPMode() API specifying whether or not the regulator
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is forced to low-power mode and if exit is interrupt or event
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triggered.
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(++) PWR_MAINREGULATOR_ON: Sleep mode (regulator in main mode).
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(++) PWR_LOWPOWERREGULATOR_ON: Low-power Sleep mode (regulator in low
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power mode). In this case, the system clock frequency must have
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been decreased below 2 MHz beforehand.
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(++) PWR_SLEEPENTRY_WFI: Core enters sleep mode with WFI instruction
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(++) PWR_SLEEPENTRY_WFE: Core enters sleep mode with WFE instruction
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(+) WFI Exit:
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(++) Any interrupt enabled in nested vectored interrupt controller (NVIC)
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(+) WFE Exit:
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(++) Any wakeup event if cortex is configured with SEVONPEND = 0
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(++) Interrupt even when disabled in NVIC if cortex is configured with
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SEVONPEND = 1
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[..] When exiting the Low-power Sleep mode by issuing an interrupt or a wakeup event,
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the MCU is in Low-power Run mode.
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*** Stop 0 & Stop 1 modes ***
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=============================
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[..]
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(+) Entry:
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The Stop modes are entered through the following APIs:
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(++) HAL_PWR_EnterSTOPMode() with following settings:
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(+++) PWR_MAINREGULATOR_ON to enter STOP0 mode.
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(+++) PWR_LOWPOWERREGULATOR_ON to enter STOP1 mode.
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(+) Exit (interrupt or event-triggered, specified when entering STOP mode):
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(++) PWR_STOPENTRY_WFI: enter Stop mode with WFI instruction
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(++) PWR_STOPENTRY_WFE: enter Stop mode with WFE instruction
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(+) WFI Exit:
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(++) Any EXTI line (internal or external) configured in interrupt mode
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with corresponding interrupt enable in NVIC
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(+) WFE Exit:
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(++) Any EXTI line (internal or external) configured in event mode if
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cortex is configured with SEVONPEND = 0
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(++) Any EXTI line configured in interrupt mode (even if the
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corresponding EXTI Interrupt vector is disabled in the NVIC) if
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cortex is configured with SEVONPEND = 0. The interrupt source can
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be external interrupts or peripherals with wakeup capability.
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[..] When exiting Stop, the MCU is either in Run mode or in Low-power Run mode
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depending on the LPR bit setting.
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@endverbatim
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* @{
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*/
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/**
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* @brief Configure LPR voltage,sram retention voltage,and wakeup correlation
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timing in Sto mode.
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* @param sStopModeConfig pointer to a PWR_StopModeConfigTypeDef structure that
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contains the Stop mode configuration information.
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* @retval HAL_OK
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*/
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HAL_StatusTypeDef HAL_PWR_ConfigStopMode(PWR_StopModeConfigTypeDef *sStopModeConfig)
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{
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/* Check the parameters */
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assert_param(IS_PWR_WAKEUP_HSIEN_TIMING(sStopModeConfig->WakeUpHsiEnableTime));
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#if defined(PWR_DEEPSTOP_SUPPORT)
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assert_param(IS_PWR_SRAM_RETENTION_VOLT(sStopModeConfig->SramRetentionVoltDlp));
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#endif /* PWR_DEEPSTOP_SUPPORT */
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assert_param(IS_PWR_SRAM_RETENTION_VOLT(sStopModeConfig->SramRetentionVolt));
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assert_param(IS_PWR_WAKEUP_FLASH_DELAY(sStopModeConfig->FlashDelay));
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/* Set the STOP mode and STOP wake-up timing related configurations */
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#if defined(PWR_DEEPSTOP_SUPPORT)
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MODIFY_REG(PWR->CR1, PWR_CR1_SRAM_RETV_DLP, (sStopModeConfig->SramRetentionVoltDlp << PWR_CR1_SRAM_RETV_DLP_Pos));
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#endif /* PWR_DEEPSTOP_SUPPORT */
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MODIFY_REG(PWR->CR1, (PWR_CR1_HSION_CTRL | PWR_CR1_SRAM_RETV | PWR_CR1_FLS_SLPTIME),
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(sStopModeConfig->WakeUpHsiEnableTime) | \
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(sStopModeConfig->SramRetentionVolt << PWR_CR1_SRAM_RETV_Pos) | \
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(sStopModeConfig->FlashDelay));
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return HAL_OK;
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}
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/**
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* @brief Configure the bias current load source and bias current values.
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* @param sBIASConfig pointer to a PWR_BIASConfigTypeDef structure that
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contains the bias current configuration information.
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* @retval HAL_OK
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*/
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HAL_StatusTypeDef HAL_PWR_ConfigBIAS(PWR_BIASConfigTypeDef *sBIASConfig)
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{
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/* Check the parameters */
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assert_param(IS_BIAS_CURRENTS_SOURCE(sBIASConfig->BiasCurrentSource));
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if(((sBIASConfig->BiasCurrentSource) & PWR_BIAS_CURRENTS_FROM_BIAS_CR) == PWR_BIAS_CURRENTS_FROM_BIAS_CR)
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{
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/* Set the bias currents load source and bias currents value*/
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MODIFY_REG(PWR->CR1, (PWR_CR1_BIAS_CR_SEL) | (PWR_CR1_BIAS_CR), (sBIASConfig->BiasCurrentSource) | \
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(sBIASConfig->BiasCurrentValue));
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}
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else
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{
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/* Set the bias currents load source */
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MODIFY_REG(PWR->CR1, PWR_CR1_BIAS_CR_SEL, (sBIASConfig->BiasCurrentSource));
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}
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return HAL_OK;
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}
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/**
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* @brief Enter Sleep or Low-power Sleep mode.
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* @note In Sleep/Low-power Sleep mode, all I/O pins keep the same state as
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* in Run mode.
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* @param SLEEPEntry Specifies if Sleep mode is entered with WFI or WFE
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* instruction. This parameter can be one of the following values:
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* @arg @ref PWR_SLEEPENTRY_WFI enter Sleep or Low-power Sleep
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* mode with WFI instruction
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* @arg @ref PWR_SLEEPENTRY_WFE enter Sleep or Low-power Sleep
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* mode with WFE instruction
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* @note When WFI entry is used, tick interrupt have to be disabled if not
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* desired as the interrupt wake up source.
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* @retval None
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*/
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void HAL_PWR_EnterSLEEPMode(uint8_t SLEEPEntry)
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{
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/* Check the parameters */
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assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry));
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/* Clear SLEEPDEEP bit of Cortex System Control Register */
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CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
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/* Select SLEEP mode entry -------------------------------------------------*/
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if(SLEEPEntry == PWR_SLEEPENTRY_WFI)
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{
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/* Request Wait For Interrupt */
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__WFI();
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}
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else
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{
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/* Request Wait For Event */
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__SEV();
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__WFE();
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__WFE();
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}
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}
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/**
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* @brief Enter Stop mode
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* @param Regulator Specifies the regulator state in Stop mode
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* This parameter can be one of the following values:
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* @arg @ref PWR_MAINREGULATOR_ON Stop 0 mode (main regulator ON)
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* @arg @ref PWR_LOWPOWERREGULATOR_ON Stop 1 mode (low power regulator ON)
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* @arg @ref PWR_DEEPLOWPOWERREGULATOR_ON Stop 2 mode (deep low power regulator ON)
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* @param STOPEntry Specifies Stop 0 、Stop 1 or Stop 2 mode is entered with WFI or
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* WFE instruction. This parameter can be one of the following values:
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* @arg @ref PWR_STOPENTRY_WFI Enter Stop 0 、Stop 1 or Stop 2 mode with WFI
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* instruction.
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* @arg @ref PWR_STOPENTRY_WFE Enter Stop 0 、Stop 1 or Stop 2 mode with WFE
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* instruction.
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* @note Depending on devices and packages, some Stop modes may not be available.
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* Refer to device datasheet for Stop modes availability.
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* @retval None
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*/
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void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry)
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{
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/* Check the parameters */
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assert_param(IS_PWR_REGULATOR(Regulator));
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assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
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/* Config Regulator */
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MODIFY_REG(PWR->CR1, PWR_CR1_LPR, Regulator);
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/* Set SLEEPDEEP bit of Cortex System Control Register */
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SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
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/* Select Stop mode entry --------------------------------------------------*/
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if(STOPEntry == PWR_STOPENTRY_WFI)
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{
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/* Request Wait For Interrupt */
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__WFI();
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}
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else
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{
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/* Request Wait For Event */
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__SEV();
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__WFE();
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__WFE();
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}
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/* Reset SLEEPDEEP bit of Cortex System Control Register */
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CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
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}
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/**
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* @brief Enable Sleep-On-Exit Cortex feature
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* @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the
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* processor enters SLEEP or DEEPSLEEP mode when an interruption
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* handling is over returning to thread mode. Setting this bit is
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* useful when the processor is expected to run only on interruptions
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* handling.
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* @retval None
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*/
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void HAL_PWR_EnableSleepOnExit(void)
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{
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/* Set SLEEPONEXIT bit of Cortex System Control Register */
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SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
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}
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/**
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* @brief Disable Sleep-On-Exit Cortex feature
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* @note Clear SLEEPONEXIT bit of SCR register. When this bit is set, the
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* processor enters SLEEP or DEEPSLEEP mode when an interruption
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* handling is over.
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* @retval None
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*/
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void HAL_PWR_DisableSleepOnExit(void)
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{
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/* Clear SLEEPONEXIT bit of Cortex System Control Register */
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CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
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}
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/**
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* @brief Enable Cortex Sev On Pending feature.
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* @note Set SEVONPEND bit of SCR register. When this bit is set, enabled
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* events and all interrupts, including disabled ones can wakeup
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* processor from WFE.
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* @retval None
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*/
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void HAL_PWR_EnableSEVOnPend(void)
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{
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/* Set SEVONPEND bit of Cortex System Control Register */
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SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
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}
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/**
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* @brief Disable Cortex Sev On Pending feature.
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* @note Clear SEVONPEND bit of SCR register. When this bit is clear, only
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* enable interrupts or events can wakeup processor from WFE
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* @retval None
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*/
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void HAL_PWR_DisableSEVOnPend(void)
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{
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/* Clear SEVONPEND bit of Cortex System Control Register */
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CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
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}
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/**
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* @}
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*/
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/**
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* @}
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*/
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#endif /* HAL_PWR_MODULE_ENABLED */
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/**
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* @}
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*/
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/**
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* @}
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*/
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/************************ (C) COPYRIGHT Puya *****END OF FILE****/
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