1267 lines
62 KiB
C
1267 lines
62 KiB
C
/**
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******************************************************************************
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* @file py32f002b_hal_rcc.h
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* @author MCU Application Team
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* @brief Header file of RCC HAL module.
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******************************************************************************
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* @attention
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*
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* <h2><center>© Copyright (c) Puya Semiconductor Co.
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* All rights reserved.</center></h2>
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*
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* <h2><center>© Copyright (c) 2016 STMicroelectronics.
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* All rights reserved.</center></h2>
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*
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* This software component is licensed by ST under BSD 3-Clause license,
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* the "License"; You may not use this file except in compliance with the
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* License. You may obtain a copy of the License at:
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* opensource.org/licenses/BSD-3-Clause
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*
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******************************************************************************
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*/
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/* Define to prevent recursive inclusion -------------------------------------*/
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#ifndef __PY32F002B_HAL_RCC_H
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#define __PY32F002B_HAL_RCC_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Includes ------------------------------------------------------------------*/
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#include "py32f002b_hal_def.h"
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/** @addtogroup PY32F002B_HAL_Driver
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* @{
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*/
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/** @addtogroup RCC
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* @{
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*/
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/* Private constants ---------------------------------------------------------*/
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/** @addtogroup RCC_Private_Constants
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* @{
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*/
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/* Defines used for Flags */
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#define CR_REG_INDEX 1U
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#define BDCR_REG_INDEX 2U
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#define CSR_REG_INDEX 3U
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#define RCC_FLAG_MASK 0x1FU
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/* Define used for IS_RCC_CLOCKTYPE() */
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#define RCC_CLOCKTYPE_ALL (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1) /*!< All clocktype to configure */
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/**
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* @}
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*/
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/* Private macros ------------------------------------------------------------*/
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/** @addtogroup RCC_Private_Macros
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* @{
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*/
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#define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE) || \
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(((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \
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(((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \
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(((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \
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(((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE))
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#define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_BYPASS_ENABLE) || ((__HSE__) == RCC_HSE_BYPASS_DISABLE))
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#define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || \
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((__LSE__) == RCC_LSE_BYPASS))
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#define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON))
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#if defined(RCC_HSI48M_SUPPORT)
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#define IS_RCC_HSI_CALIBRATION_VALUE(__VALUE__) (((__VALUE__) == RCC_HSICALIBRATION_24MHz) || \
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((__VALUE__) == RCC_HSICALIBRATION_48MHz))
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#else
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#define IS_RCC_HSI_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) == RCC_HSICALIBRATION_24MHz)
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#endif
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#define IS_RCC_HSIDIV(__DIV__) (((__DIV__) == RCC_HSI_DIV1) || ((__DIV__) == RCC_HSI_DIV2) || \
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((__DIV__) == RCC_HSI_DIV4) || ((__DIV__) == RCC_HSI_DIV8) || \
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((__DIV__) == RCC_HSI_DIV16) || ((__DIV__) == RCC_HSI_DIV32)|| \
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((__DIV__) == RCC_HSI_DIV64) || ((__DIV__) == RCC_HSI_DIV128))
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#define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON))
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#define IS_RCC_CLOCKTYPE(__CLK__) ((((__CLK__) & RCC_CLOCKTYPE_ALL) != 0x00UL) && (((__CLK__) & ~RCC_CLOCKTYPE_ALL) == 0x00UL))
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#define IS_RCC_SYSCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_HSISYS) || \
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((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) || \
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((__SOURCE__) == RCC_SYSCLKSOURCE_LSE) || \
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((__SOURCE__) == RCC_SYSCLKSOURCE_LSI))
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#define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) || ((__HCLK__) == RCC_SYSCLK_DIV2) || \
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((__HCLK__) == RCC_SYSCLK_DIV4) || ((__HCLK__) == RCC_SYSCLK_DIV8) || \
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((__HCLK__) == RCC_SYSCLK_DIV16) || ((__HCLK__) == RCC_SYSCLK_DIV64) || \
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((__HCLK__) == RCC_SYSCLK_DIV128) || ((__HCLK__) == RCC_SYSCLK_DIV256) || \
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((__HCLK__) == RCC_SYSCLK_DIV512))
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#define IS_RCC_PCLK(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) || ((__PCLK__) == RCC_HCLK_DIV2) || \
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((__PCLK__) == RCC_HCLK_DIV4) || ((__PCLK__) == RCC_HCLK_DIV8) || \
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((__PCLK__) == RCC_HCLK_DIV16))
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#define IS_RCC_MCO(__MCOX__) (((__MCOX__) == RCC_MCO1) || ((__MCOX__) == RCC_MCO2))
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#define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK) || \
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((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || \
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((__SOURCE__) == RCC_MCO1SOURCE_HSI) || \
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((__SOURCE__) == RCC_MCO1SOURCE_HSE) || \
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((__SOURCE__) == RCC_MCO1SOURCE_LSI) || \
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((__SOURCE__) == RCC_MCO1SOURCE_LSE))
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#define IS_RCC_MCODIV(__DIV__) (((__DIV__) == RCC_MCODIV_1) || ((__DIV__) == RCC_MCODIV_2) || \
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((__DIV__) == RCC_MCODIV_4) || ((__DIV__) == RCC_MCODIV_8) || \
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((__DIV__) == RCC_MCODIV_16)|| ((__DIV__) == RCC_MCODIV_32) || \
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((__DIV__) == RCC_MCODIV_64)|| ((__DIV__) == RCC_MCODIV_128))
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#define IS_RCC_LSE_DRIVE(__DRIVE__) (((__DRIVE__) == RCC_LSEDRIVE_LOWEST) || \
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((__DRIVE__) == RCC_LSEDRIVE_LOW) || \
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((__DRIVE__) == RCC_LSEDRIVE_MEDIUM) || \
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((__DRIVE__) == RCC_LSEDRIVE_HIGH))
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/**
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* @}
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*/
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/* Exported types ------------------------------------------------------------*/
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/** @defgroup RCC_Exported_Types RCC Exported Types
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* @{
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*/
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/**
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* @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition
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*/
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typedef struct
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{
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uint32_t OscillatorType; /*!< The oscillators to be configured.
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This parameter can be a value of @ref RCC_Oscillator_Type */
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uint32_t HSEState; /*!< The new state of the HSE.
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This parameter can be a value of @ref RCC_HSE_Config */
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uint32_t LSEState; /*!< The new state of the LSE.
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This parameter can be a value of @ref RCC_LSE_Config */
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uint32_t LSEDriver; /*!< The driver factor of the LSE.
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This parameter can be a value of @ref RCC_LSE_Driver */
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uint32_t HSIState; /*!< The new state of the HSI.
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This parameter can be a value of @ref RCC_HSI_Config */
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uint32_t HSIDiv; /*!< The division factor of the HSI.
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This parameter can be a value of @ref RCC_HSI_Div */
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uint32_t HSICalibrationValue; /*!< The calibration trimming value.
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This parameter can be a value of @ref RCC_HSI_Calibration */
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uint32_t LSIState; /*!< The new state of the LSI.
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This parameter can be a value of @ref RCC_LSI_Config */
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uint32_t LSICalibrationValue; /*!< The calibration trimming value.
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This parameter can be a value of @ref RCC_LSI_Calibration */
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} RCC_OscInitTypeDef;
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/**
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* @brief RCC System, AHB and APB busses clock configuration structure definition
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*/
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typedef struct
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{
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uint32_t ClockType; /*!< The clock to be configured.
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This parameter can be a combination of @ref RCC_System_Clock_Type */
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uint32_t SYSCLKSource; /*!< The clock source used as system clock (SYSCLK).
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This parameter can be a value of @ref RCC_System_Clock_Source */
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uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
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This parameter can be a value of @ref RCC_AHB_Clock_Source */
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uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
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This parameter can be a value of @ref RCC_APB1_Clock_Source */
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} RCC_ClkInitTypeDef;
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/**
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* @}
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*/
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/* Exported constants --------------------------------------------------------*/
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/** @defgroup RCC_Exported_Constants RCC Exported Constants
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* @{
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*/
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/** @defgroup RCC_Timeout_Value Timeout Values
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* @{
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*/
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#define RCC_DBP_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */
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#define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT /* LSE timeout in ms */
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/**
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* @}
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*/
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/** @defgroup RCC_Oscillator_Type Oscillator Type
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* @{
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*/
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#define RCC_OSCILLATORTYPE_NONE 0x00000000U /*!< Oscillator configuration unchanged */
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#define RCC_OSCILLATORTYPE_HSE 0x00000001U /*!< HSE to configure */
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#define RCC_OSCILLATORTYPE_HSI 0x00000002U /*!< HSI to configure */
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#define RCC_OSCILLATORTYPE_LSE 0x00000004U /*!< LSE to configure */
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#define RCC_OSCILLATORTYPE_LSI 0x00000008U /*!< LSI to configure */
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/**
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* @}
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*/
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/** @defgroup RCC_HSE_Config HSE Config
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* @{
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*/
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#define RCC_HSE_BYPASS_DISABLE 0x00000000U /*!< Disable external clock source for HSE clock */
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#define RCC_HSE_BYPASS_ENABLE ((uint32_t)(RCC_CR_HSEEN)) /*!< Enable external clock source for HSE clock */
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/**
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* @}
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*/
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/** @defgroup RCC_LSE_Config LSE Config
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* @{
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*/
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#define RCC_LSE_OFF 0x00000000U /*!< LSE clock deactivation */
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#define RCC_LSE_ON RCC_BDCR_LSEON /*!< LSE clock activation */
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#define RCC_LSE_BYPASS ((uint32_t)(RCC_BDCR_LSEBYP | RCC_BDCR_LSEON)) /*!< External clock source for LSE clock */
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/**
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* @}
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*/
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/** @defgroup RCC_LSE_Driver LSE Config
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* @{
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*/
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#define RCC_LSEDRIVE_LOWEST 0x00000000 /*!< LSE lowest driving capability */
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#define RCC_LSEDRIVE_LOW RCC_ECSCR_LSE_DRIVER_0 /*!< LSE low drive capability */
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#define RCC_LSEDRIVE_MEDIUM RCC_ECSCR_LSE_DRIVER_1 /*!< LSE medium drive capability */
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#define RCC_LSEDRIVE_HIGH (RCC_ECSCR_LSE_DRIVER_0 | RCC_ECSCR_LSE_DRIVER_1) /*!< LSE high drive capability */
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/**
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* @}
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*/
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/** @defgroup RCC_LSE_STARTUP LSE settling time Config
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* @{
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*/
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#define RCC_LSE_STARTUP_NONE (RCC_ECSCR_LSE_STARTUP_1 | RCC_ECSCR_LSE_STARTUP_0)
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#define RCC_LSE_STARTUP_LOW RCC_ECSCR_LSE_STARTUP_0
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#define RCC_LSE_STARTUP_MEDIUM 0x00000000U
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#define RCC_LSE_STARTUP_HIGH RCC_ECSCR_LSE_STARTUP_1
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/**
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* @}
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*/
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/** @defgroup RCC_HSI_Config HSI Config
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* @{
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*/
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#define RCC_HSI_OFF 0x00000000U /*!< HSI clock deactivation */
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#define RCC_HSI_ON RCC_CR_HSION /*!< HSI clock activation */
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/**
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* @}
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*/
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/** @defgroup RCC_HSI_Calibration HSI Calibration
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* @{
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*/
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#define RCC_HSICALIBRATION_24MHz ((*(uint32_t *)(0x1FFF0100)) & 0xFFFF) /*!< 24MHz HSI calibration trimming value */
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#if defined(RCC_HSI48M_SUPPORT)
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#define RCC_HSICALIBRATION_48MHz ((*(uint32_t *)(0x1FFF0104)) & 0xFFFF) /*!< 48MHz HSI calibration trimming value */
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#endif
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/**
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* @}
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*/
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/** @defgroup RCC_HSI_Div HSI Div
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* @{
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*/
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#define RCC_HSI_DIV1 0x00000000U /*!< HSI clock is not divided */
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#define RCC_HSI_DIV2 RCC_CR_HSIDIV_0 /*!< HSI clock is divided by 2 */
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#define RCC_HSI_DIV4 RCC_CR_HSIDIV_1 /*!< HSI clock is divided by 4 */
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#define RCC_HSI_DIV8 (RCC_CR_HSIDIV_1|RCC_CR_HSIDIV_0) /*!< HSI clock is divided by 8 */
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#define RCC_HSI_DIV16 RCC_CR_HSIDIV_2 /*!< HSI clock is divided by 16 */
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#define RCC_HSI_DIV32 (RCC_CR_HSIDIV_2|RCC_CR_HSIDIV_0) /*!< HSI clock is divided by 32 */
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#define RCC_HSI_DIV64 (RCC_CR_HSIDIV_2|RCC_CR_HSIDIV_1) /*!< HSI clock is divided by 64 */
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#define RCC_HSI_DIV128 (RCC_CR_HSIDIV_2|RCC_CR_HSIDIV_1|RCC_CR_HSIDIV_0) /*!< HSI clock is divided by 128 */
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/**
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* @}
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*/
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/** @defgroup RCC_LSI_Config LSI Config
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* @{
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*/
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#define RCC_LSI_OFF 0x00000000U /*!< LSI clock deactivation */
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#define RCC_LSI_ON RCC_CSR_LSION /*!< LSI clock activation */
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/**
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* @}
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*/
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/** @defgroup RCC_LSI_Calibration LSI Calibration
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* @{
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*/
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#define RCC_LSICALIBRATION_32768Hz ((*(uint32_t *)(0x1FFF0144)) & 0x1FF) /*!< 32.768KHz LSI calibration trimming value */
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#define RCC_LSICALIBRATION_38400Hz ((*(uint32_t *)(0x1FFF0148)) & 0x1FF) /*!< 38.4KHz LSI calibration trimming value */
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/**
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* @}
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*/
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/** @defgroup RCC_System_Clock_Type System Clock Type
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* @{
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*/
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#define RCC_CLOCKTYPE_SYSCLK 0x00000001U /*!< SYSCLK to configure */
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#define RCC_CLOCKTYPE_HCLK 0x00000002U /*!< HCLK to configure */
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#define RCC_CLOCKTYPE_PCLK1 0x00000004U /*!< PCLK1 to configure */
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/**
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* @}
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*/
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/** @defgroup RCC_System_Clock_Source System Clock Source
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* @{
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*/
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#define RCC_SYSCLKSOURCE_HSISYS 0x00000000U /*!< HSISYS selection as system clock */
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#define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_0 /*!< HSE selection as system clock */
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#define RCC_SYSCLKSOURCE_LSI (RCC_CFGR_SW_1 | RCC_CFGR_SW_0) /*!< LSI selection as system clock */
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#define RCC_SYSCLKSOURCE_LSE RCC_CFGR_SW_2 /*!< LSE selection as system clock */
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/**
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* @}
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*/
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/** @defgroup RCC_System_Clock_Source_Status System Clock Source Status
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* @{
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*/
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#define RCC_SYSCLKSOURCE_STATUS_HSISYS 0x00000000U /*!< HSISYS used as system clock */
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#define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_0 /*!< HSE used as system clock */
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#define RCC_SYSCLKSOURCE_STATUS_LSI (RCC_CFGR_SWS_1 | RCC_CFGR_SWS_0) /*!< LSI used as system clock */
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#define RCC_SYSCLKSOURCE_STATUS_LSE RCC_CFGR_SWS_2 /*!< LSE used as system clock */
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/**
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* @}
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*/
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/** @defgroup RCC_AHB_Clock_Source AHB Clock Source
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* @{
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*/
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#define RCC_SYSCLK_DIV1 0x00000000U /*!< SYSCLK not divided */
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#define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_3 /*!< SYSCLK divided by 2 */
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#define RCC_SYSCLK_DIV4 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_0) /*!< SYSCLK divided by 4 */
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#define RCC_SYSCLK_DIV8 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_1) /*!< SYSCLK divided by 8 */
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#define RCC_SYSCLK_DIV16 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_1 | RCC_CFGR_HPRE_0) /*!< SYSCLK divided by 16 */
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#define RCC_SYSCLK_DIV64 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_2) /*!< SYSCLK divided by 64 */
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#define RCC_SYSCLK_DIV128 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_2 | RCC_CFGR_HPRE_0) /*!< SYSCLK divided by 128 */
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#define RCC_SYSCLK_DIV256 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_2 | RCC_CFGR_HPRE_1) /*!< SYSCLK divided by 256 */
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#define RCC_SYSCLK_DIV512 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_2 | RCC_CFGR_HPRE_1 | RCC_CFGR_HPRE_0) /*!< SYSCLK divided by 512 */
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/**
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* @}
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*/
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/** @defgroup RCC_APB1_Clock_Source APB Clock Source
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* @{
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*/
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#define RCC_HCLK_DIV1 0x00000000U /*!< HCLK not divided */
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#define RCC_HCLK_DIV2 RCC_CFGR_PPRE_2 /*!< HCLK divided by 2 */
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#define RCC_HCLK_DIV4 (RCC_CFGR_PPRE_2 | RCC_CFGR_PPRE_0) /*!< HCLK divided by 4 */
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#define RCC_HCLK_DIV8 (RCC_CFGR_PPRE_2 | RCC_CFGR_PPRE_1) /*!< HCLK divided by 8 */
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#define RCC_HCLK_DIV16 (RCC_CFGR_PPRE_2 | RCC_CFGR_PPRE_1 | RCC_CFGR_PPRE_0) /*!< HCLK divided by 16 */
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/**
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* @}
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*/
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/** @defgroup RCC_MCO_Index MCO Index
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* @{
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*/
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#define RCC_MCO 0x00000000U
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#define RCC_MCO1 RCC_MCO /*!< Configure PA07 as the clock output.*/
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#define RCC_MCO2 0x00000001U /*!< Configure PB01 as the clock output. */
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/**
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* @}
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*/
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/** @defgroup RCC_MCO_Clock_Source MCO Clock Source
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* @{
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*/
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#define RCC_MCOSOURCE_NOCLOCK 0x00000000U /*!< MCO output disabled, no clock on MCO */
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#define RCC_MCOSOURCE_SYSCLK RCC_CFGR_MCOSEL_0 /*!< SYSCLK selection as MCO source */
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#define RCC_MCOSOURCE_HSI (RCC_CFGR_MCOSEL_0| RCC_CFGR_MCOSEL_1) /*!< HSI selection as MCO source */
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#define RCC_MCOSOURCE_HSE RCC_CFGR_MCOSEL_2 /*!< HSE selection as MCO source */
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#define RCC_MCOSOURCE_LSI (RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2) /*!< LSI selection as MCO source */
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#define RCC_MCOSOURCE_LSE (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2) /*!< LSE selection as MCO source */
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/**
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* @}
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*/
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/** @defgroup RCC_MCOx_Clock_Prescaler MCO1 Clock Prescaler
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* @{
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*/
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#define RCC_MCODIV_1 0x00000000U /*!< MCO not divided */
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#define RCC_MCODIV_2 RCC_CFGR_MCOPRE_0 /*!< MCO divided by 2 */
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#define RCC_MCODIV_4 RCC_CFGR_MCOPRE_1 /*!< MCO divided by 4 */
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#define RCC_MCODIV_8 (RCC_CFGR_MCOPRE_1 | RCC_CFGR_MCOPRE_0) /*!< MCO divided by 8 */
|
|
#define RCC_MCODIV_16 RCC_CFGR_MCOPRE_2 /*!< MCO divided by 16 */
|
|
#define RCC_MCODIV_32 (RCC_CFGR_MCOPRE_2 | RCC_CFGR_MCOPRE_0) /*!< MCO divided by 32 */
|
|
#define RCC_MCODIV_64 (RCC_CFGR_MCOPRE_2 | RCC_CFGR_MCOPRE_1) /*!< MCO divided by 64 */
|
|
#define RCC_MCODIV_128 (RCC_CFGR_MCOPRE_2 | RCC_CFGR_MCOPRE_1 | RCC_CFGR_MCOPRE_0) /*!< MCO divided by 128 */
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup RCC_Interrupt Interrupts
|
|
* @{
|
|
*/
|
|
#define RCC_IT_LSIRDY RCC_CIFR_LSIRDYF /*!< LSI Ready Interrupt flag */
|
|
#define RCC_IT_LSERDY RCC_CIFR_LSERDYF /*!< LSE Ready Interrupt flag */
|
|
#define RCC_IT_LSECSS RCC_CIFR_LSECSSF /*!< LSE Clock Security System Interrupt flag */
|
|
#define RCC_IT_HSIRDY RCC_CIFR_HSIRDYF /*!< HSI Ready Interrupt flag */
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup RCC_Flag Flags
|
|
* Elements values convention: XXXYYYYYb
|
|
* - YYYYY : Flag position in the register
|
|
* - XXX : Register index
|
|
* - 001: CR register
|
|
* - 010: BDCR register
|
|
* - 011: CSR register
|
|
* @{
|
|
*/
|
|
/* Flags in the CR register */
|
|
#define RCC_FLAG_HSIRDY ((CR_REG_INDEX << 5U) | RCC_CR_HSIRDY_Pos) /*!< HSI Ready flag */
|
|
|
|
/* Flags in the BDCR register */
|
|
#define RCC_FLAG_LSERDY ((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSERDY_Pos) /*!< LSE Ready flag */
|
|
|
|
/* Flags in the CSR register */
|
|
#define RCC_FLAG_LSIRDY ((CSR_REG_INDEX << 5U) | RCC_CSR_LSIRDY_Pos) /*!< LSI Ready flag */
|
|
#define RCC_FLAG_OBLRST ((CSR_REG_INDEX << 5U) | RCC_CSR_OBLRSTF_Pos) /*!< Option Byte Loader reset flag */
|
|
#define RCC_FLAG_PINRST ((CSR_REG_INDEX << 5U) | RCC_CSR_PINRSTF_Pos) /*!< PIN reset flag */
|
|
#define RCC_FLAG_PWRRST ((CSR_REG_INDEX << 5U) | RCC_CSR_PWRRSTF_Pos) /*!< BOR or POR/PDR reset flag */
|
|
#define RCC_FLAG_SFTRST ((CSR_REG_INDEX << 5U) | RCC_CSR_SFTRSTF_Pos) /*!< Software Reset flag */
|
|
#define RCC_FLAG_IWDGRST ((CSR_REG_INDEX << 5U) | RCC_CSR_IWDGRSTF_Pos) /*!< Independent Watchdog reset flag */
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/* Exported macros -----------------------------------------------------------*/
|
|
|
|
/** @defgroup RCC_Exported_Macros RCC Exported Macros
|
|
* @{
|
|
*/
|
|
|
|
/** @defgroup RCC_AHB_Peripheral_Clock_Enable_Disable AHB Peripheral Clock Enable Disable
|
|
* @brief Enable or disable the AHB peripheral clock.
|
|
* @note After reset, the peripheral clock (used for registers read/write access)
|
|
* is disabled and the application software has to enable this clock before
|
|
* using it.
|
|
* @{
|
|
*/
|
|
#define __HAL_RCC_FLASH_CLK_ENABLE() do { \
|
|
__IO uint32_t tmpreg; \
|
|
SET_BIT(RCC->AHBENR, RCC_AHBENR_FLASHEN); \
|
|
/* Delay after an RCC peripheral clock enabling */ \
|
|
tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FLASHEN); \
|
|
UNUSED(tmpreg); \
|
|
} while(0U)
|
|
|
|
#define __HAL_RCC_SRAM_CLK_ENABLE() do { \
|
|
__IO uint32_t tmpreg; \
|
|
SET_BIT(RCC->AHBENR, RCC_AHBENR_SRAMEN); \
|
|
/* Delay after an RCC peripheral clock enabling */ \
|
|
tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_SRAMEN); \
|
|
UNUSED(tmpreg); \
|
|
} while(0U)
|
|
#define __HAL_RCC_CRC_CLK_ENABLE() do { \
|
|
__IO uint32_t tmpreg; \
|
|
SET_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN); \
|
|
/* Delay after an RCC peripheral clock enabling */ \
|
|
tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN); \
|
|
UNUSED(tmpreg); \
|
|
} while(0U)
|
|
|
|
#define __HAL_RCC_FLASH_CLK_DISABLE() CLEAR_BIT(RCC->AHBENR, RCC_AHBENR_FLASHEN)
|
|
#define __HAL_RCC_SRAM_CLK_DISABLE() CLEAR_BIT(RCC->AHBENR, RCC_AHBENR_SRAMEN)
|
|
#define __HAL_RCC_CRC_CLK_DISABLE() CLEAR_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN)
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup RCC_IOPORT_Clock_Enable_Disable IOPORT Clock Enable Disable
|
|
* @brief Enable or disable the IO Ports clock.
|
|
* @note After reset, the IO ports clock (used for registers read/write access)
|
|
* is disabled and the application software has to enable this clock before
|
|
* using it.
|
|
* @{
|
|
*/
|
|
|
|
#define __HAL_RCC_GPIOA_CLK_ENABLE() do { \
|
|
__IO uint32_t tmpreg; \
|
|
SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIOAEN); \
|
|
/* Delay after an RCC peripheral clock enabling */ \
|
|
tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOAEN); \
|
|
UNUSED(tmpreg); \
|
|
} while(0U)
|
|
|
|
#define __HAL_RCC_GPIOB_CLK_ENABLE() do { \
|
|
__IO uint32_t tmpreg; \
|
|
SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIOBEN); \
|
|
/* Delay after an RCC peripheral clock enabling */ \
|
|
tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOBEN); \
|
|
UNUSED(tmpreg); \
|
|
} while(0U)
|
|
|
|
#define __HAL_RCC_GPIOC_CLK_ENABLE() do { \
|
|
__IO uint32_t tmpreg; \
|
|
SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIOCEN); \
|
|
/* Delay after an RCC peripheral clock enabling */ \
|
|
tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOCEN); \
|
|
UNUSED(tmpreg); \
|
|
} while(0U)
|
|
|
|
#define __HAL_RCC_GPIOA_CLK_DISABLE() CLEAR_BIT(RCC->IOPENR, RCC_IOPENR_GPIOAEN)
|
|
#define __HAL_RCC_GPIOB_CLK_DISABLE() CLEAR_BIT(RCC->IOPENR, RCC_IOPENR_GPIOBEN)
|
|
#define __HAL_RCC_GPIOC_CLK_DISABLE() CLEAR_BIT(RCC->IOPENR, RCC_IOPENR_GPIOCEN)
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
|
|
* @brief Enable or disable the APB1 peripheral clock.
|
|
* @note After reset, the peripheral clock (used for registers read/write access)
|
|
* is disabled and the application software has to enable this clock before
|
|
* using it.
|
|
* @{
|
|
*/
|
|
#define __HAL_RCC_I2C_CLK_ENABLE() do { \
|
|
__IO uint32_t tmpreg; \
|
|
SET_BIT(RCC->APBENR1, RCC_APBENR1_I2CEN); \
|
|
/* Delay after an RCC peripheral clock enabling */ \
|
|
tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_I2CEN); \
|
|
UNUSED(tmpreg); \
|
|
} while(0U)
|
|
|
|
#define __HAL_RCC_DBGMCU_CLK_ENABLE() do { \
|
|
__IO uint32_t tmpreg; \
|
|
SET_BIT(RCC->APBENR1, RCC_APBENR1_DBGEN); \
|
|
/* Delay after an RCC peripheral clock enabling */ \
|
|
tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_DBGEN); \
|
|
UNUSED(tmpreg); \
|
|
} while(0U)
|
|
|
|
#define __HAL_RCC_PWR_CLK_ENABLE() do { \
|
|
__IO uint32_t tmpreg; \
|
|
SET_BIT(RCC->APBENR1, RCC_APBENR1_PWREN); \
|
|
/* Delay after an RCC peripheral clock enabling */ \
|
|
tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_PWREN); \
|
|
UNUSED(tmpreg); \
|
|
} while(0U)
|
|
|
|
#define __HAL_RCC_LPTIM_CLK_ENABLE() do { \
|
|
__IO uint32_t tmpreg; \
|
|
SET_BIT(RCC->APBENR1, RCC_APBENR1_LPTIMEN); \
|
|
/* Delay after an RCC peripheral clock enabling */ \
|
|
tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_LPTIMEN); \
|
|
UNUSED(tmpreg); \
|
|
} while(0U)
|
|
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
|
|
* @brief Enable or disable the APB2 peripheral clock.
|
|
* @note After reset, the peripheral clock (used for registers read/write access)
|
|
* is disabled and the application software has to enable this clock before
|
|
* using it.
|
|
* @{
|
|
*/
|
|
|
|
#define __HAL_RCC_SYSCFG_CLK_ENABLE() do { \
|
|
__IO uint32_t tmpreg; \
|
|
SET_BIT(RCC->APBENR2, RCC_APBENR2_SYSCFGEN); \
|
|
/* Delay after an RCC peripheral clock enabling */ \
|
|
tmpreg = READ_BIT(RCC->APBENR2, RCC_APBENR2_SYSCFGEN); \
|
|
UNUSED(tmpreg); \
|
|
} while(0U)
|
|
|
|
#define __HAL_RCC_TIM1_CLK_ENABLE() do { \
|
|
__IO uint32_t tmpreg; \
|
|
SET_BIT(RCC->APBENR2, RCC_APBENR2_TIM1EN); \
|
|
/* Delay after an RCC peripheral clock enabling */ \
|
|
tmpreg = READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM1EN); \
|
|
UNUSED(tmpreg); \
|
|
} while(0U)
|
|
|
|
#define __HAL_RCC_SPI1_CLK_ENABLE() do { \
|
|
__IO uint32_t tmpreg; \
|
|
SET_BIT(RCC->APBENR2, RCC_APBENR2_SPI1EN); \
|
|
/* Delay after an RCC peripheral clock enabling */ \
|
|
tmpreg = READ_BIT(RCC->APBENR2, RCC_APBENR2_SPI1EN); \
|
|
UNUSED(tmpreg); \
|
|
} while(0U)
|
|
|
|
#define __HAL_RCC_USART1_CLK_ENABLE() do { \
|
|
__IO uint32_t tmpreg; \
|
|
SET_BIT(RCC->APBENR2, RCC_APBENR2_USART1EN); \
|
|
/* Delay after an RCC peripheral clock enabling */ \
|
|
tmpreg = READ_BIT(RCC->APBENR2, RCC_APBENR2_USART1EN); \
|
|
UNUSED(tmpreg); \
|
|
} while(0U)
|
|
|
|
#define __HAL_RCC_TIM14_CLK_ENABLE() do { \
|
|
__IO uint32_t tmpreg; \
|
|
SET_BIT(RCC->APBENR2, RCC_APBENR2_TIM14EN); \
|
|
/* Delay after an RCC peripheral clock enabling */ \
|
|
tmpreg = READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM14EN); \
|
|
UNUSED(tmpreg); \
|
|
} while(0U)
|
|
|
|
#define __HAL_RCC_ADC_CLK_ENABLE() do { \
|
|
__IO uint32_t tmpreg; \
|
|
SET_BIT(RCC->APBENR2, RCC_APBENR2_ADCEN); \
|
|
/* Delay after an RCC peripheral clock enabling */ \
|
|
tmpreg = READ_BIT(RCC->APBENR2, RCC_APBENR2_ADCEN); \
|
|
UNUSED(tmpreg); \
|
|
} while(0U)
|
|
#if defined(COMP1)
|
|
#define __HAL_RCC_COMP1_CLK_ENABLE() do { \
|
|
__IO uint32_t tmpreg; \
|
|
SET_BIT(RCC->APBENR2, RCC_APBENR2_COMP1EN); \
|
|
/* Delay after an RCC peripheral clock enabling */ \
|
|
tmpreg = READ_BIT(RCC->APBENR2, RCC_APBENR2_COMP1EN); \
|
|
UNUSED(tmpreg); \
|
|
} while(0U)
|
|
#endif
|
|
|
|
#if defined(COMP2)
|
|
#define __HAL_RCC_COMP2_CLK_ENABLE() do { \
|
|
__IO uint32_t tmpreg; \
|
|
SET_BIT(RCC->APBENR2, RCC_APBENR2_COMP2EN); \
|
|
/* Delay after an RCC peripheral clock enabling */ \
|
|
tmpreg = READ_BIT(RCC->APBENR2, RCC_APBENR2_COMP2EN); \
|
|
UNUSED(tmpreg); \
|
|
} while(0U)
|
|
#endif
|
|
|
|
#define __HAL_RCC_I2C_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_I2CEN)
|
|
#define __HAL_RCC_DBGMCU_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_DBGEN)
|
|
#define __HAL_RCC_PWR_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_PWREN)
|
|
#define __HAL_RCC_LPTIM_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_LPTIMEN)
|
|
|
|
#define __HAL_RCC_SYSCFG_CLK_DISABLE() CLEAR_BIT(RCC->APBENR2, RCC_APBENR2_SYSCFGEN)
|
|
#define __HAL_RCC_TIM1_CLK_DISABLE() CLEAR_BIT(RCC->APBENR2, RCC_APBENR2_TIM1EN)
|
|
#define __HAL_RCC_SPI1_CLK_DISABLE() CLEAR_BIT(RCC->APBENR2, RCC_APBENR2_SPI1EN)
|
|
#define __HAL_RCC_USART1_CLK_DISABLE() CLEAR_BIT(RCC->APBENR2, RCC_APBENR2_USART1EN)
|
|
#if defined(TIM14)
|
|
#define __HAL_RCC_TIM14_CLK_DISABLE() CLEAR_BIT(RCC->APBENR2, RCC_APBENR2_TIM14EN)
|
|
#endif
|
|
#define __HAL_RCC_ADC_CLK_DISABLE() CLEAR_BIT(RCC->APBENR2, RCC_APBENR2_ADCEN)
|
|
#if defined(COMP1)
|
|
#define __HAL_RCC_COMP1_CLK_DISABLE() CLEAR_BIT(RCC->APBENR2, RCC_APBENR2_COMP1EN)
|
|
#endif
|
|
#if defined(COMP2)
|
|
#define __HAL_RCC_COMP2_CLK_DISABLE() CLEAR_BIT(RCC->APBENR2, RCC_APBENR2_COMP2EN)
|
|
#endif
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup RCC_AHB_Peripheral_Clock_Enabled_Disabled_Status AHB Peripheral Clock Enabled or Disabled Status
|
|
* @brief Check whether the AHB peripheral clock is enabled or not.
|
|
* @note After reset, the peripheral clock (used for registers read/write access)
|
|
* is disabled and the application software has to enable this clock before
|
|
* using it.
|
|
* @{
|
|
*/
|
|
#define __HAL_RCC_FLASH_IS_CLK_ENABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_FLASHEN) != RESET)
|
|
#define __HAL_RCC_CRC_IS_CLK_ENABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN) != RESET)
|
|
|
|
#define __HAL_RCC_FLASH_IS_CLK_DISABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_FLASHEN) == RESET)
|
|
#define __HAL_RCC_CRC_IS_CLK_DISABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN) == RESET)
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup RCC_IOPORT_Clock_Enabled_Disabled_Status IOPORT Clock Enabled or Disabled Status
|
|
* @brief Check whether the IO Port clock is enabled or not.
|
|
* @note After reset, the peripheral clock (used for registers read/write access)
|
|
* is disabled and the application software has to enable this clock before
|
|
* using it.
|
|
* @{
|
|
*/
|
|
#define __HAL_RCC_GPIOA_IS_CLK_ENABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOAEN) != RESET)
|
|
#define __HAL_RCC_GPIOB_IS_CLK_ENABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOBEN) != RESET)
|
|
#define __HAL_RCC_GPIOC_IS_CLK_ENABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOCEN) != RESET)
|
|
|
|
#define __HAL_RCC_GPIOA_IS_CLK_DISABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOAEN) == RESET)
|
|
#define __HAL_RCC_GPIOB_IS_CLK_DISABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOBEN) == RESET)
|
|
#define __HAL_RCC_GPIOC_IS_CLK_DISABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOCEN) == RESET)
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup RCC_APB1_Clock_Enabled_Disabled_Status APB1 Peripheral Clock Enabled or Disabled Status
|
|
* @brief Check whether the APB1 peripheral clock is enabled or not.
|
|
* @note After reset, the peripheral clock (used for registers read/write access)
|
|
* is disabled and the application software has to enable this clock before
|
|
* using it.
|
|
* @{
|
|
*/
|
|
#define __HAL_RCC_I2C_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_I2CEN) != 0U)
|
|
#define __HAL_RCC_DBGMCU_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_DBGEN) != 0U)
|
|
#define __HAL_RCC_PWR_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_PWREN) != 0U)
|
|
#define __HAL_RCC_LPTIM_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_LPTIMEN) != 0U)
|
|
|
|
#define __HAL_RCC_I2C1_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_I2CEN) == 0U)
|
|
#define __HAL_RCC_DBGMCU_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_DBGEN) == 0U)
|
|
#define __HAL_RCC_PWR_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_PWREN) == 0U)
|
|
#define __HAL_RCC_LPTIM_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_LPTIMEN) == 0U)
|
|
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup RCC_APB2_Clock_Enabled_Disabled_Status APB2 Peripheral Clock Enabled or Disabled Status
|
|
* @brief Check whether the APB2 peripheral clock is enabled or not.
|
|
* @note After reset, the peripheral clock (used for registers read/write access)
|
|
* is disabled and the application software has to enable this clock before
|
|
* using it.
|
|
* @{
|
|
*/
|
|
|
|
#define __HAL_RCC_SYSCFG_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_SYSCFGEN) != 0U)
|
|
#define __HAL_RCC_TIM1_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM1EN) != 0U)
|
|
#define __HAL_RCC_SPI1_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_SPI1EN) != 0U)
|
|
#define __HAL_RCC_USART1_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_USART1EN) != 0U)
|
|
#if defined(TIM14)
|
|
#define __HAL_RCC_TIM14_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM14EN) != 0U)
|
|
#endif
|
|
#define __HAL_RCC_ADC_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_ADCEN) != 0U)
|
|
#if defined(COMP1)
|
|
#define __HAL_RCC_COMP1_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_COMP1EN) != 0U)
|
|
#endif
|
|
#if defined(COMP2)
|
|
#define __HAL_RCC_COMP2_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_COMP2EN) != 0U)
|
|
#endif
|
|
|
|
#define __HAL_RCC_SYSCFG_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_SYSCFGEN) == 0U)
|
|
#define __HAL_RCC_TIM1_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM1EN) == 0U)
|
|
#define __HAL_RCC_SPI1_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_SPI1EN) == 0U)
|
|
#define __HAL_RCC_USART1_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_USART1EN) == 0U)
|
|
#if defined(TIM14)
|
|
#define __HAL_RCC_TIM14_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM14EN) == 0U)
|
|
#endif
|
|
#define __HAL_RCC_ADC_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_ADCEN) == 0U)
|
|
#if defined(COMP1)
|
|
#define __HAL_RCC_COMP1_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_COMP1EN) == 0U)
|
|
#endif
|
|
#if defined(COMP2)
|
|
#define __HAL_RCC_COMP2_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_COMP2EN) == 0U)
|
|
#endif
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup RCC_AHB_Force_Release_Reset AHB Peripheral Force Release Reset
|
|
* @brief Force or release AHB1 peripheral reset.
|
|
* @{
|
|
*/
|
|
#define __HAL_RCC_AHB_FORCE_RESET() WRITE_REG(RCC->AHBRSTR, 0xFFFFFFFFU)
|
|
#define __HAL_RCC_FLASH_FORCE_RESET() SET_BIT(RCC->AHBRSTR, RCC_AHBRSTR_FLASHRST)
|
|
#define __HAL_RCC_CRC_FORCE_RESET() SET_BIT(RCC->AHBRSTR, RCC_AHBRSTR_CRCRST)
|
|
|
|
#define __HAL_RCC_AHB_RELEASE_RESET() WRITE_REG(RCC->AHBRSTR, 0x00000000U)
|
|
#define __HAL_RCC_FLASH_RELEASE_RESET() CLEAR_BIT(RCC->AHBRSTR, RCC_AHBRSTR_FLASHRST)
|
|
#define __HAL_RCC_CRC_RELEASE_RESET() CLEAR_BIT(RCC->AHBRSTR, RCC_AHBRSTR_CRCRST)
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup RCC_IOPORT_Force_Release_Reset IOPORT Force Release Reset
|
|
* @brief Force or release IO Port reset.
|
|
* @{
|
|
*/
|
|
#define __HAL_RCC_IOP_FORCE_RESET() WRITE_REG(RCC->IOPRSTR, 0xFFFFFFFFU)
|
|
#define __HAL_RCC_GPIOA_FORCE_RESET() SET_BIT(RCC->IOPRSTR, RCC_IOPRSTR_GPIOARST)
|
|
#define __HAL_RCC_GPIOB_FORCE_RESET() SET_BIT(RCC->IOPRSTR, RCC_IOPRSTR_GPIOBRST)
|
|
#define __HAL_RCC_GPIOC_FORCE_RESET() SET_BIT(RCC->IOPRSTR, RCC_IOPRSTR_GPIOCRST)
|
|
|
|
#define __HAL_RCC_IOP_RELEASE_RESET() WRITE_REG(RCC->IOPRSTR, 0x00000000U)
|
|
#define __HAL_RCC_GPIOA_RELEASE_RESET() CLEAR_BIT(RCC->IOPRSTR, RCC_IOPRSTR_GPIOARST)
|
|
#define __HAL_RCC_GPIOB_RELEASE_RESET() CLEAR_BIT(RCC->IOPRSTR, RCC_IOPRSTR_GPIOBRST)
|
|
#define __HAL_RCC_GPIOC_RELEASE_RESET() CLEAR_BIT(RCC->IOPRSTR, RCC_IOPRSTR_GPIOCRST)
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup RCC_APB1_Force_Release_Reset APB1 Peripheral Force Release Reset
|
|
* @brief Force or release APB1 peripheral reset.
|
|
* @{
|
|
*/
|
|
#define __HAL_RCC_APB1_FORCE_RESET() WRITE_REG(RCC->APBRSTR1, 0xFFFFFFFFU)
|
|
#define __HAL_RCC_I2C_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_I2CRST)
|
|
#define __HAL_RCC_DBGMCU_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_DBGRST)
|
|
#define __HAL_RCC_PWR_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_PWRRST)
|
|
#define __HAL_RCC_LPTIM_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_LPTIMRST)
|
|
|
|
#define __HAL_RCC_APB1_RELEASE_RESET() WRITE_REG(RCC->APBRSTR1, 0x00000000U)
|
|
#define __HAL_RCC_I2C_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_I2CRST)
|
|
#define __HAL_RCC_DBGMCU_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_DBGRST)
|
|
#define __HAL_RCC_PWR_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_PWRRST)
|
|
#define __HAL_RCC_LPTIM_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_LPTIMRST)
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup RCC_APB2_Force_Release_Reset APB2 Peripheral Force Release Reset
|
|
* @brief Force or release APB2 peripheral reset.
|
|
* @{
|
|
*/
|
|
#define __HAL_RCC_APB2_FORCE_RESET() WRITE_REG(RCC->APBRSTR2, 0xFFFFFFFFU)
|
|
#define __HAL_RCC_SYSCFG_FORCE_RESET() SET_BIT(RCC->APBRSTR2, RCC_APBRSTR2_SYSCFGRST)
|
|
#define __HAL_RCC_TIM1_FORCE_RESET() SET_BIT(RCC->APBRSTR2, RCC_APBRSTR2_TIM1RST)
|
|
#define __HAL_RCC_SPI1_FORCE_RESET() SET_BIT(RCC->APBRSTR2, RCC_APBRSTR2_SPI1RST)
|
|
#define __HAL_RCC_USART1_FORCE_RESET() SET_BIT(RCC->APBRSTR2, RCC_APBRSTR2_USART1RST)
|
|
#define __HAL_RCC_TIM14_FORCE_RESET() SET_BIT(RCC->APBRSTR2, RCC_APBRSTR2_TIM14RST)
|
|
#define __HAL_RCC_ADC_FORCE_RESET() SET_BIT(RCC->APBRSTR2, RCC_APBRSTR2_ADCRST)
|
|
#if defined(COMP1)
|
|
#define __HAL_RCC_COMP1_FORCE_RESET() SET_BIT(RCC->APBRSTR2, RCC_APBRSTR2_COMP1RST)
|
|
#endif
|
|
#if defined(COMP2)
|
|
#define __HAL_RCC_COMP2_FORCE_RESET() SET_BIT(RCC->APBRSTR2, RCC_APBRSTR2_COMP2RST)
|
|
#endif
|
|
|
|
#define __HAL_RCC_APB2_RELEASE_RESET() WRITE_REG(RCC->APBRSTR2, 0x00U)
|
|
#define __HAL_RCC_SYSCFG_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR2, RCC_APBRSTR2_SYSCFGRST)
|
|
#define __HAL_RCC_TIM1_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR2, RCC_APBRSTR2_TIM1RST)
|
|
#define __HAL_RCC_SPI1_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR2, RCC_APBRSTR2_SPI1RST)
|
|
#define __HAL_RCC_USART1_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR2, RCC_APBRSTR2_USART1RST)
|
|
#define __HAL_RCC_TIM14_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR2, RCC_APBRSTR2_TIM14RST)
|
|
#define __HAL_RCC_ADC_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR2, RCC_APBRSTR2_ADCRST)
|
|
#if defined(COMP1)
|
|
#define __HAL_RCC_COMP1_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR2, RCC_APBRSTR2_COMP1RST)
|
|
#endif
|
|
#if defined(COMP2)
|
|
#define __HAL_RCC_COMP2_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR2, RCC_APBRSTR2_COMP2RST)
|
|
#endif
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup RCC_Clock_Configuration RCC Clock Configuration
|
|
* @{
|
|
*/
|
|
|
|
/** @brief Macros to enable the Internal High Speed oscillator (HSI).
|
|
* @note The HSI is stopped by hardware when entering STOP and STANDBY modes.
|
|
* It is used (enabled by hardware) as system clock source after startup
|
|
* from Reset, wakeup from STOP and STANDBY mode, or in case of failure
|
|
* of the HSE used directly or indirectly as system clock (if the Clock
|
|
* Security System CSS is enabled).
|
|
* @note After enabling the HSI, the application software should wait on HSIRDY
|
|
* flag to be set indicating that HSI clock is stable and can be used as
|
|
* system clock source.
|
|
* This parameter can be: ENABLE or DISABLE.
|
|
* @retval None
|
|
*/
|
|
#define __HAL_RCC_HSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSION)
|
|
|
|
/** @brief Macros to disable the Internal High Speed oscillator (HSI).
|
|
* @note HSI can not be stopped if it is used as system clock source. In this case,
|
|
* you have to select another source of the system clock then stop the HSI.
|
|
* @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
|
|
* clock cycles.
|
|
* @retval None
|
|
*/
|
|
#define __HAL_RCC_HSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSION)
|
|
|
|
/** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value.
|
|
* @note The calibration is used to compensate for the variations in voltage
|
|
* and temperature that influence the frequency of the internal HSI RC.
|
|
* @param __HSICALIBRATIONVALUE__ specifies the calibration trimming value
|
|
* (default is RCC_HSICALIBRATION_DEFAULT).
|
|
* This parameter must be a number between 0 and 127.
|
|
* @retval None
|
|
*/
|
|
#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICALIBRATIONVALUE__) \
|
|
MODIFY_REG(RCC->ICSCR, (RCC_ICSCR_HSI_FS_Msk|RCC_ICSCR_HSI_TRIM), (uint32_t)(__HSICALIBRATIONVALUE__) << RCC_ICSCR_HSI_TRIM_Pos)
|
|
|
|
/** @brief Macro to configure the HSISYS clock.
|
|
* @param __HSIDIV__ specifies the HSI division factor.
|
|
* This parameter can be one of the following values:
|
|
* @arg @ref RCC_HSI_DIV1 HSI clock source is divided by 1
|
|
* @arg @ref RCC_HSI_DIV2 HSI clock source is divided by 2
|
|
* @arg @ref RCC_HSI_DIV4 HSI clock source is divided by 4
|
|
* @arg @ref RCC_HSI_DIV8 HSI clock source is divided by 8
|
|
* @arg @ref RCC_HSI_DIV16 HSI clock source is divided by 16
|
|
* @arg @ref RCC_HSI_DIV32 HSI clock source is divided by 32
|
|
* @arg @ref RCC_HSI_DIV64 HSI clock source is divided by 64
|
|
* @arg @ref RCC_HSI_DIV128 HSI clock source is divided by 128
|
|
*/
|
|
#define __HAL_RCC_HSI_CONFIG(__HSIDIV__) \
|
|
MODIFY_REG(RCC->CR, RCC_CR_HSIDIV, (__HSIDIV__))
|
|
|
|
/** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI).
|
|
* @note After enabling the LSI, the application software should wait on
|
|
* LSIRDY flag to be set indicating that LSI clock is stable and can
|
|
* be used to clock the IWDG.
|
|
* @note LSI can not be disabled if the IWDG is running.
|
|
* @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
|
|
* clock cycles.
|
|
* @retval None
|
|
*/
|
|
#define __HAL_RCC_LSI_ENABLE() SET_BIT(RCC->CSR, RCC_CSR_LSION)
|
|
|
|
#define __HAL_RCC_LSI_DISABLE() CLEAR_BIT(RCC->CSR, RCC_CSR_LSION)
|
|
|
|
/** @brief Macro to adjust the Internal Low Speed oscillator (LSI) calibration value.
|
|
* @param __LSICALIBRATIONVALUE__ specifies the calibration trimming value.
|
|
* This parameter can be one of the following values:
|
|
* @arg @ref RCC_LSICALIBRATION_32768Hz
|
|
* @arg @ref RCC_LSICALIBRATION_38400Hz
|
|
* @retval None
|
|
*/
|
|
#define __HAL_RCC_LSI_CALIBRATIONVALUE_ADJUST(__LSICALIBRATIONVALUE__) \
|
|
MODIFY_REG(RCC->ICSCR, RCC_ICSCR_LSI_TRIM, (__LSICALIBRATIONVALUE__ << RCC_ICSCR_LSI_TRIM_Pos))
|
|
|
|
/**
|
|
* @brief Macro to configure the External High Speed oscillator (HSE).
|
|
* @param __STATE__ specifies the new state of the HSE.
|
|
* This parameter can be one of the following values:
|
|
* @arg @ref RCC_HSE_BYPASS_DISABLE Disable HSE oscillator bypassed with external clock.
|
|
* @arg @ref RCC_HSE_BYPASS_ENABLE Enable HSE oscillator bypassed with external clock.
|
|
* @retval None
|
|
*/
|
|
#define __HAL_RCC_HSE_CONFIG(__STATE__) \
|
|
do { \
|
|
if((__STATE__) == RCC_HSE_BYPASS_ENABLE) \
|
|
{ \
|
|
SET_BIT(RCC->CR, RCC_CR_HSEEN); \
|
|
} \
|
|
else \
|
|
{ \
|
|
CLEAR_BIT(RCC->CR, RCC_CR_HSEEN); \
|
|
} \
|
|
} while(0U)
|
|
|
|
/**
|
|
* @brief Macro to configure the External Low Speed oscillator (LSE).
|
|
* @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not
|
|
* supported by this macro. User should request a transition to LSE Off
|
|
* first and then LSE On or LSE Bypass.
|
|
* @note As the LSE is in the Backup domain and write access is denied to
|
|
* this domain after reset, you have to enable write access using
|
|
* HAL_PWR_EnableBkUpAccess() function before to configure the LSE
|
|
* (to be done once after reset).
|
|
* @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application
|
|
* software should wait on LSERDY flag to be set indicating that LSE clock
|
|
* is stable.
|
|
* @param __STATE__ specifies the new state of the LSE.
|
|
* This parameter can be one of the following values:
|
|
* @arg @ref RCC_LSE_OFF Turn OFF the LSE oscillator, LSERDY flag goes low after
|
|
* 6 LSE oscillator clock cycles.
|
|
* @arg @ref RCC_LSE_ON Turn ON the LSE oscillator.
|
|
* @arg @ref RCC_LSE_BYPASS LSE oscillator bypassed with external clock.
|
|
* @retval None
|
|
*/
|
|
#define __HAL_RCC_LSE_CONFIG(__STATE__) \
|
|
do { \
|
|
if((__STATE__) == RCC_LSE_ON) \
|
|
{ \
|
|
SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
|
|
} \
|
|
else if((__STATE__) == RCC_LSE_BYPASS) \
|
|
{ \
|
|
SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
|
|
SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
|
|
} \
|
|
else \
|
|
{ \
|
|
CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
|
|
CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
|
|
} \
|
|
} while(0U)
|
|
|
|
/** @brief Macro to configure the LSE settling time.
|
|
* @param __TIME__ specifies the LSE settling time.
|
|
* This parameter can be one of the following values:
|
|
* @arg @ref RCC_LSE_STARTUP_NONE Direct output regardless of stabilization time.
|
|
* @arg @ref RCC_LSE_STARTUP_LOW It is output after 2048 LSE clock cycles.
|
|
If LSEBYP is set, it is output after 1024 clock cycles.
|
|
* @arg @ref RCC_LSE_STARTUP_MEDIUM It is output after 4096 LSE clock cycles.
|
|
If LSEBYP is set, it is output after 2048 clock cycles.
|
|
* @arg @ref RCC_LSE_STARTUP_HIGH It is output after 8192 LSE clock cycles.
|
|
If LSEBYP is set, it is output after 4096 clock cycles.
|
|
*/
|
|
#define __HAL_RCC_LSE_STARTUP_DELAY(__TIME__) MODIFY_REG(RCC->ECSCR, RCC_ECSCR_LSE_STARTUP ,(__TIME__))
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/**
|
|
* @brief Macro to configure the system clock source.
|
|
* @param __SYSCLKSOURCE__ specifies the system clock source.
|
|
* This parameter can be one of the following values:
|
|
* @arg @ref RCC_SYSCLKSOURCE_HSISYS HSISYS oscillator is used as system clock source.
|
|
* @arg @ref RCC_SYSCLKSOURCE_HSE HSE oscillator is used as system clock source.
|
|
* @arg @ref RCC_SYSCLKSOURCE_LSI LSI oscillator is used as system clock source.
|
|
* @arg @ref RCC_SYSCLKSOURCE_LSE LSE oscillator is used as system clock source.
|
|
* @note Depending on devices and packages, some clocks may not be available.
|
|
* Refer to device datasheet for clocks availability.
|
|
* @retval None
|
|
*/
|
|
#define __HAL_RCC_SYSCLK_CONFIG(__SYSCLKSOURCE__) \
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__SYSCLKSOURCE__))
|
|
|
|
/** @brief Macro to get the clock source used as system clock.
|
|
* @retval The clock source used as system clock. The returned value can be one
|
|
* of the following:
|
|
* @arg @ref RCC_SYSCLKSOURCE_STATUS_HSISYS HSISYS used as system clock.
|
|
* @arg @ref RCC_SYSCLKSOURCE_STATUS_HSE HSE used as system clock.
|
|
* @arg @ref RCC_SYSCLKSOURCE_STATUS_LSI LSI used as system clock source.
|
|
* @arg @ref RCC_SYSCLKSOURCE_STATUS_LSE LSE used as system clock source.
|
|
* @note Depending on devices and packages, some clocks may not be available.
|
|
* Refer to device datasheet for clocks availability.
|
|
*/
|
|
#define __HAL_RCC_GET_SYSCLK_SOURCE() (RCC->CFGR & RCC_CFGR_SWS)
|
|
|
|
/**
|
|
* @brief Macro to configure the External Low Speed oscillator (LSE) drive capability.
|
|
* @note As the LSE is in the Backup domain and write access is denied to
|
|
* this domain after reset, you have to enable write access using
|
|
* HAL_PWR_EnableBkUpAccess() function before to configure the LSE
|
|
* (to be done once after reset).
|
|
* @param __LSEDRIVE__ specifies the new state of the LSE drive capability.
|
|
* This parameter can be one of the following values:
|
|
* @arg @ref RCC_LSEDRIVE_LOWEST LSE oscillator lowest drive capability.
|
|
* @arg @ref RCC_LSEDRIVE_LOW LSE oscillator low drive capability.
|
|
* @arg @ref RCC_LSEDRIVE_MEDIUM LSE oscillator medium low drive capability.
|
|
* @arg @ref RCC_LSEDRIVE_HIGH LSE oscillator high drive capability.
|
|
* @retval None
|
|
*/
|
|
#define __HAL_RCC_LSEDRIVE_CONFIG(__LSEDRIVE__) \
|
|
MODIFY_REG(RCC->ECSCR, RCC_ECSCR_LSE_DRIVER, (uint32_t)(__LSEDRIVE__))
|
|
|
|
/** @brief Macro to configure the MCO clock.
|
|
* @param __MCOCLKSOURCE__ specifies the MCO clock source.
|
|
* This parameter can be one of the following values:
|
|
* @arg @ref RCC_MCO1SOURCE_NOCLOCK MCO output disabled
|
|
* @arg @ref RCC_MCO1SOURCE_SYSCLK System clock selected as MCO source
|
|
* @arg @ref RCC_MCO1SOURCE_HSI HSI clock selected as MCO source
|
|
* @arg @ref RCC_MCO1SOURCE_HSE HSE clock selected as MCO sourcee
|
|
* @arg @ref RCC_MCO1SOURCE_LSI LSI clock selected as MCO source
|
|
* @arg @ref RCC_MCO1SOURCE_LSE LSE clock selected as MCO source
|
|
* @note Depending on devices and packages, some clocks may not be available.
|
|
* Refer to device datasheet for clocks availability.
|
|
* @param __MCODIV__ specifies the MCO clock prescaler.
|
|
* This parameter can be one of the following values:
|
|
* @arg @ref RCC_MCODIV_1 MCO clock source is divided by 1
|
|
* @arg @ref RCC_MCODIV_2 MCO clock source is divided by 2
|
|
* @arg @ref RCC_MCODIV_4 MCO clock source is divided by 4
|
|
* @arg @ref RCC_MCODIV_8 MCO clock source is divided by 8
|
|
* @arg @ref RCC_MCODIV_16 MCO clock source is divided by 16
|
|
* @arg @ref RCC_MCODIV_32 MCO clock source is divided by 32
|
|
* @arg @ref RCC_MCODIV_64 MCO clock source is divided by 64
|
|
* @arg @ref RCC_MCODIV_128 MCO clock source is divided by 128
|
|
*/
|
|
#define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
|
|
MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE), ((__MCOCLKSOURCE__) | (__MCODIV__)))
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management
|
|
* @brief macros to manage the specified RCC Flags and interrupts.
|
|
* @{
|
|
*/
|
|
|
|
/** @brief Enable RCC interrupt.
|
|
* @param __INTERRUPT__ specifies the RCC interrupt sources to be enabled.
|
|
* This parameter can be any combination of the following values:
|
|
* @arg @ref RCC_IT_LSIRDY LSI ready interrupt
|
|
* @arg @ref RCC_IT_LSERDY LSE ready interrupt
|
|
* @arg @ref RCC_IT_HSIRDY HSI ready interrupt
|
|
* @note Depending on devices and packages, some clocks may not be available.
|
|
* Refer to device datasheet for clocks availability.
|
|
* @retval None
|
|
*/
|
|
#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) SET_BIT(RCC->CIER, (__INTERRUPT__))
|
|
|
|
/** @brief Disable RCC interrupt.
|
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* @param __INTERRUPT__ specifies the RCC interrupt sources to be disabled.
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* This parameter can be any combination of the following values:
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* @arg @ref RCC_IT_LSIRDY LSI ready interrupt
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* @arg @ref RCC_IT_LSERDY LSE ready interrupt
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* @arg @ref RCC_IT_HSIRDY HSI ready interrupt
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* @note Depending on devices and packages, some clocks may not be available.
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* Refer to device datasheet for clocks availability.
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* @retval None
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*/
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#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(RCC->CIER, (__INTERRUPT__))
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/** @brief Clear RCC interrupt pending bits.
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* @param __INTERRUPT__ specifies the interrupt pending bit to clear.
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* This parameter can be any combination of the following values:
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* @arg @ref RCC_IT_LSIRDY LSI ready interrupt
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* @arg @ref RCC_IT_LSERDY LSE ready interrupt
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* @arg @ref RCC_IT_HSIRDY HSI ready interrupt
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* @arg @ref RCC_IT_LSECSS LSE Clock security system interrupt
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* @note Depending on devices and packages, some clocks may not be available.
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* Refer to device datasheet for clocks availability.
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* @retval None
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*/
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#define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (RCC->CICR = (__INTERRUPT__))
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/** @brief Check whether the RCC interrupt has occurred or not.
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* @param __INTERRUPT__ specifies the RCC interrupt source to check.
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* This parameter can be one of the following values:
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* @arg @ref RCC_IT_LSIRDY LSI ready interrupt
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* @arg @ref RCC_IT_LSERDY LSE ready interrupt
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* @arg @ref RCC_IT_HSIRDY HSI ready interrupt
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* @arg @ref RCC_IT_LSECSS LSE Clock security system interrupt
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* @note Depending on devices and packages, some clocks may not be available.
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* Refer to device datasheet for clocks availability.
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* @retval The new state of __INTERRUPT__ (TRUE or FALSE).
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*/
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#define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIFR & (__INTERRUPT__)) == (__INTERRUPT__))
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/** @brief Set RMVF bit to clear the reset flags.
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* The reset flags are: RCC_FLAG_OBLRST, RCC_FLAG_PINRST, RCC_FLAG_PWRRST,
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* RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST.
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* @note Depending on the device and software package, some flag bits may not be available.
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* Refer to the device data sheet for flag bit availability.
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* @retval None
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*/
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#define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR |= RCC_CSR_RMVF)
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/** @brief Check whether the selected RCC flag is set or not.
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* @param __FLAG__ specifies the flag to check.
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* This parameter can be one of the following values:
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* @arg @ref RCC_FLAG_HSIRDY HSI oscillator clock ready
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* @arg @ref RCC_FLAG_LSERDY LSE oscillator clock ready
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* @arg @ref RCC_FLAG_LSIRDY LSI oscillator clock ready
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* @arg @ref RCC_FLAG_PWRRST BOR or POR/PDR reset
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* @arg @ref RCC_FLAG_OBLRST OBLRST reset
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* @arg @ref RCC_FLAG_PINRST Pin reset
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* @arg @ref RCC_FLAG_SFTRST Software reset
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* @arg @ref RCC_FLAG_IWDGRST Independent Watchdog reset
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* @note Depending on the device and software package, some flag bits may not be available.
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* Refer to the device data sheet for flag bit availability.
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* @retval The new state of __FLAG__ (TRUE or FALSE).
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*/
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#define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == CR_REG_INDEX) ? RCC->CR : \
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((((__FLAG__) >> 5U) == BDCR_REG_INDEX) ? RCC->BDCR : \
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((((__FLAG__) >> 5U) == CSR_REG_INDEX) ? RCC->CSR : RCC->CIFR))) & \
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(1U << ((__FLAG__) & RCC_FLAG_MASK))) != RESET) \
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? 1U : 0U)
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/**
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* @}
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*/
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/**
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* @}
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*/
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/* Include RCC HAL Extended module */
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#include "py32f002b_hal_rcc_ex.h"
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/* Exported functions --------------------------------------------------------*/
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/** @addtogroup RCC_Exported_Functions
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* @{
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*/
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/** @addtogroup RCC_Exported_Functions_Group1
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* @{
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*/
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/* Initialization and de-initialization functions ******************************/
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HAL_StatusTypeDef HAL_RCC_DeInit(void);
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HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
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HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);
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/**
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* @}
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*/
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/** @addtogroup RCC_Exported_Functions_Group2
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* @{
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*/
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/* Peripheral Control functions ************************************************/
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void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
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void HAL_RCC_EnableLSECSS(void);
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void HAL_RCC_DisableLSECSS(void);
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void HAL_RCC_LSECSSCallback(void);
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uint32_t HAL_RCC_GetSysClockFreq(void);
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uint32_t HAL_RCC_GetHCLKFreq(void);
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uint32_t HAL_RCC_GetPCLK1Freq(void);
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void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
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void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency);
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/* LSE & HSE CSS NMI IRQ handler */
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void HAL_RCC_NMI_IRQHandler(void);
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/* User Callbacks in non blocking mode (IT mode) */
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void HAL_RCC_CSSCallback(void);
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/**
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* @}
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*/
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/**
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* @}
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*/
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/**
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* @}
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*/
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/**
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* @}
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*/
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#ifdef __cplusplus
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}
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#endif
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#endif /* __PY32F002B_HAL_RCC_H */
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/************************ (C) COPYRIGHT Puya *****END OF FILE****/
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