From bef05f2773bf142ae0c5c69c8d575f34a69d3cdc Mon Sep 17 00:00:00 2001 From: Razvalyaev Date: Thu, 6 Mar 2025 16:13:41 +0300 Subject: [PATCH] =?UTF-8?q?=D0=98=D1=81=D0=BF=D1=80=D0=B0=D0=B2=D0=BB?= =?UTF-8?q?=D0=B5=D0=BD=D0=BE,=20=D1=80=D0=B0=D0=B1=D0=BE=D1=82=D0=B0?= =?UTF-8?q?=D0=B5=D1=82=20=D0=B4=D0=BB=D1=8F=20002B.=20=D0=91=D1=8B=D0=BB?= =?UTF-8?q?=D0=BE=20=D0=BB=D0=B8=D1=88=D0=BD=D0=B5=D0=B5=20=D0=B7=D0=B0?= =?UTF-8?q?=D0=B4=D0=B0=D0=BD=D0=B8=D0=B5=20=D0=B2=D1=8B=D1=81=D0=BE=D0=BA?= =?UTF-8?q?=D0=BE=D0=B3=D0=BE=20=D0=BF=D1=80=D0=B8=D0=BE=D1=80=D0=B8=D1=82?= =?UTF-8?q?=D0=B5=D1=82=D0=B0=20=D1=82=D0=B0=D0=B9=D0=BC=D0=B5=D1=80=D0=B0?= =?UTF-8?q?=20=D0=BC=D0=BE=D0=B4=D0=B1=D0=B0=D1=81,=20=D1=82=D0=B0=D0=BA?= =?UTF-8?q?=D0=B6=D0=B5=20=D0=B1=D1=8B=D0=BB=D0=B0=20=D0=BF=D0=B5=D1=80?= =?UTF-8?q?=D0=B5=D0=B8=D0=BC=D0=B5=D0=BD=D0=BE=D0=B2=D0=B0=D0=BD=D0=B0=20?= =?UTF-8?q?=D1=84=D1=83=D0=BD=D0=BA=D1=86=D0=B8=D1=8F=20=D0=BF=D1=80=D0=B5?= =?UTF-8?q?=D1=80=D1=8B=D0=B2=D0=B0=D0=BD=D0=B8=D1=8F=20=D1=82=D0=B0=D0=B9?= =?UTF-8?q?=D0=BC=D0=B5=D1=80=D0=B0=20=D0=BC=D0=BE=D0=B4=D0=B1=D0=B0=D1=81?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- py_project/Core/Modbus/interface_config.h | 4 ++-- py_project/Core/Src/tim.c | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/py_project/Core/Modbus/interface_config.h b/py_project/Core/Modbus/interface_config.h index ae088d1..058de92 100644 --- a/py_project/Core/Modbus/interface_config.h +++ b/py_project/Core/Modbus/interface_config.h @@ -40,8 +40,8 @@ #define rs_huart huart1 #define rs_htim htim14 -//#define RS_EnableReceive() GPIOB->ODR |= GPIO_PIN_3 -//#define RS_EnableTransmit() GPIOB->ODR &= ~GPIO_PIN_3 +#define RS_EnableReceive() GPIOB->ODR |= GPIO_PIN_3 +#define RS_EnableTransmit() GPIOB->ODR &= ~GPIO_PIN_3 /** * @brief Поменять комманды 0x03 и 0x04 местами (для LabView терминалки от двигателей) * @details Терминалка от двигателей использует для чтения регистров комманду R_HOLD_REGS вместо R_IN_REGS diff --git a/py_project/Core/Src/tim.c b/py_project/Core/Src/tim.c index 8145b7f..b1c080b 100644 --- a/py_project/Core/Src/tim.c +++ b/py_project/Core/Src/tim.c @@ -128,8 +128,8 @@ void MX_TIMMB_Init(void) // Отключение режима Master/Slave TIM_MB->SMCR &= ~TIM_SMCR_MSM; - HAL_NVIC_SetPriority(TIM_MB_IRQn, 0, 0); - HAL_NVIC_EnableIRQ(TIM_MB_IRQn); +// HAL_NVIC_SetPriority(TIM_MB_IRQn, 0, 0); +// HAL_NVIC_EnableIRQ(TIM_MB_IRQn); // /* USER CODE BEGIN TIM2_Init 0 */ // /* USER CODE END TIM2_Init 0 */