diff --git a/PY32F002A_Pins.xlsx b/PY32F002A_Pins.xlsx index 5934109..26496c4 100644 Binary files a/PY32F002A_Pins.xlsx and b/PY32F002A_Pins.xlsx differ diff --git a/py_project/Core/Modbus/modbus.c b/py_project/Core/Modbus/modbus.c index eb8e672..3d42716 100644 --- a/py_project/Core/Modbus/modbus.c +++ b/py_project/Core/Modbus/modbus.c @@ -81,7 +81,6 @@ EXAMPLE: INIT SLAVE RECEIVE *************************************************************************/ #include "rs_message.h" -uint32_t dbg_temp, dbg_temp2, dbg_temp3; // for debug /* MODBUS HANDLES */ #ifdef INCLUDE_GENERAL_PERIPH_LIBS UART_SettingsTypeDef modbus1_suart; diff --git a/py_project/Core/Modbus/rs_message.h b/py_project/Core/Modbus/rs_message.h index 835f532..623c24b 100644 --- a/py_project/Core/Modbus/rs_message.h +++ b/py_project/Core/Modbus/rs_message.h @@ -28,7 +28,6 @@ #include "modbus.h" #include "crc_algs.h" -#include "string.h" ///////////////////////////////////////////////////////////////////// @@ -44,7 +43,7 @@ /* Clear message-uart buffer */ -#define RS_Clear_Buff(_buff_) memset(_buff_, 0, MSG_SIZE_MAX) +#define RS_Clear_Buff(_buff_) for(int i=0; if.RS_Busy = 0 diff --git a/py_project/Core/PY32Module/PY32module_main.c b/py_project/Core/PY32Module/PY32module_main.c index f1e7181..f09e9f1 100644 --- a/py_project/Core/PY32Module/PY32module_main.c +++ b/py_project/Core/PY32Module/PY32module_main.c @@ -27,6 +27,14 @@ void PYModule_main(void) { if(DS18B20_WaitForEndConvertion_NonBlocking(hdallas1.onewire) == HAL_OK) { + PCHSens_ModuleReadTemperature(&pchsens.module1); +// PCHSens_ModuleReadTemperature(&pchsens.module2); +// PCHSens_ModuleReadTemperature(&pchsens.module3); +// PCHSens_ModuleReadTemperature(&pchsens.module4); +// PCHSens_ModuleReadTemperature(&pchsens.module5); +// PCHSens_ModuleReadTemperature(&pchsens.module6); + + PYModule_StoreModbus(&pchsens); PCHSens_StartCovert(&DallasBus); GPIOA->ODR ^= GPIO_LED_2; } @@ -37,7 +45,6 @@ void PYModule_main(void) PYModule_ReadSensor(&hdallas1, &pchsens); MB_DATA.Coils.ReadSensor = 0; } - // if(MB_DATA.Coils.ScanSensors) // { // PYModule_ScanSensor(&DallasBus); @@ -60,22 +67,7 @@ void PYModule_main(void) } PYModule_CheckLosted(&pchsens); - - if(MB_DATA.Coils.RunConvertions) - { - if(DS18B20_WaitForEndConvertion_NonBlocking(hdallas1.onewire) == HAL_OK) - { - PCHSens_ModuleReadTemperature(&pchsens.module1); -// PCHSens_ModuleReadTemperature(&pchsens.module2); -// PCHSens_ModuleReadTemperature(&pchsens.module3); -// PCHSens_ModuleReadTemperature(&pchsens.module4); -// PCHSens_ModuleReadTemperature(&pchsens.module5); -// PCHSens_ModuleReadTemperature(&pchsens.module6); - - PYModule_StoreModbus(&pchsens); - } - } - + } diff --git a/py_project/Core/Src/system_py32f0xx.c b/py_project/Core/Src/system_py32f0xx.c new file mode 100644 index 0000000..b79d2be --- /dev/null +++ b/py_project/Core/Src/system_py32f0xx.c @@ -0,0 +1,173 @@ +/** + ****************************************************************************** + * @file system_py32f0xx.c + * @author MCU Application Team + * @Version V1.0.0 + * @Date 2020-10-19 + * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer System Source File. + ****************************************************************************** + */ + +#include "py32f0xx.h" + +#if !defined (HSE_VALUE) +#define HSE_VALUE 24000000U /*!< Value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (HSI_VALUE) +#define HSI_VALUE 8000000U /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + +#if !defined (LSI_VALUE) +#define LSI_VALUE 32768U /*!< Value of LSI in Hz*/ +#endif /* LSI_VALUE */ + +#if !defined (LSE_VALUE) +#define LSE_VALUE 32768U /*!< Value of LSE in Hz*/ +#endif /* LSE_VALUE */ + + +/************************* Miscellaneous Configuration ************************/ +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define FORBID_VECT_TAB_MIGRATION */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. + This value must be a multiple of 0x100. */ +/******************************************************************************/ +/*---------------------------------------------------------------------------- + Clock Variable definitions + *----------------------------------------------------------------------------*/ +/* This variable is updated in three ways: + 1) by calling CMSIS function SystemCoreClockUpdate() + 2) by calling HAL API function HAL_RCC_GetHCLKFreq() + 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency + Note: If you use this function to configure the system clock; then there + is no need to call the 2 first functions listed above, since SystemCoreClock + variable is updated automatically. +*/ +uint32_t SystemCoreClock = HSI_VALUE; + +const uint32_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; +const uint32_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4}; +const uint32_t HSIFreqTable[8] = {4000000U, 8000000U, 16000000U, 22120000U, 24000000U, 4000000U, 4000000U, 4000000U}; + +/*---------------------------------------------------------------------------- + Clock functions + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate(void) /* Get Core Clock Frequency */ +{ + uint32_t tmp; + uint32_t hsidiv; + uint32_t hsifs; + + /* Get SYSCLK source -------------------------------------------------------*/ + switch (RCC->CFGR & RCC_CFGR_SWS) + { + case RCC_CFGR_SWS_0: /* HSE used as system clock */ + SystemCoreClock = HSE_VALUE; + break; + + case (RCC_CFGR_SWS_1 | RCC_CFGR_SWS_0): /* LSI used as system clock */ + SystemCoreClock = LSI_VALUE; + break; +#if defined(RCC_LSE_SUPPORT) + case RCC_CFGR_SWS_2: /* LSE used as system clock */ + SystemCoreClock = LSE_VALUE; + break; +#endif +#if defined(RCC_PLL_SUPPORT) + case RCC_CFGR_SWS_1: /* PLL used as system clock */ + if ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI) /* HSI used as PLL clock source */ + { + hsifs = ((READ_BIT(RCC->ICSCR, RCC_ICSCR_HSI_FS)) >> RCC_ICSCR_HSI_FS_Pos); + SystemCoreClock = 2 * (HSIFreqTable[hsifs]); + } + else /* HSE used as PLL clock source */ + { + SystemCoreClock = 2 * HSE_VALUE; + } + break; +#endif + case 0x00000000U: /* HSI used as system clock */ + default: /* HSI used as system clock */ + hsifs = ((READ_BIT(RCC->ICSCR, RCC_ICSCR_HSI_FS)) >> RCC_ICSCR_HSI_FS_Pos); + hsidiv = (1UL << ((READ_BIT(RCC->CR, RCC_CR_HSIDIV)) >> RCC_CR_HSIDIV_Pos)); + SystemCoreClock = (HSIFreqTable[hsifs] / hsidiv); + break; + } + /* Compute HCLK clock frequency --------------------------------------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)]; + /* HCLK clock frequency */ + SystemCoreClock >>= tmp; +} + +/** + * Initialize the system + * + * @param none + * @return none + * + * @brief Setup the microcontroller system. + * Initialize the System. + */ +void SystemInit(void) +{ + //Set the HSI clock to 8MHz by default + RCC->ICSCR = (RCC->ICSCR & 0xFFFF0000) | (0x1 << 13) | *(uint32_t *)(0x1fff0f04); + + /* Configure the Vector Table location add offset address ------------------*/ +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ +#endif +} + +#ifndef FORBID_VECT_TAB_MIGRATION +#ifndef VECT_TAB_SRAM +#if (defined (__CC_ARM)) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) +extern int32_t $Super$$main(void); +uint32_t VECT_SRAM_TAB[48]__attribute__((section(".ARM.__at_0x20000000"))); + +/* re-define main function */ +int $Sub$$main(void) +{ + uint8_t i; + uint32_t *pFmcVect = (uint32_t *)(FLASH_BASE | VECT_TAB_OFFSET); + for (i = 0; i < 48; i++) + { + VECT_SRAM_TAB[i] = pFmcVect[i]; + } + + SCB->VTOR = SRAM_BASE; + + $Super$$main(); + return 0; +} +#elif defined(__ICCARM__) +extern int32_t main(void); +/* __low_level_init will auto called by IAR cstartup */ +extern void __iar_data_init3(void); +uint32_t VECT_SRAM_TAB[48] @SRAM_BASE; +int __low_level_init(void) +{ + uint8_t i; + uint32_t *pFmcVect = (uint32_t *)(FLASH_BASE | VECT_TAB_OFFSET); + // call IAR table copy function. + __iar_data_init3(); + + for (i = 0; i < 48; i++) + { + VECT_SRAM_TAB[i] = pFmcVect[i]; + } + + SCB->VTOR = SRAM_BASE; + + main(); + return 0; +} +#endif +#endif +#endif diff --git a/py_project/MDK-ARM/DebugConfig/PY32F002Ax5_Project_PY32F002Ax5.dbgconf b/py_project/MDK-ARM/DebugConfig/PY32F002Ax5_Project_PY32F002Ax5.dbgconf new file mode 100644 index 0000000..ba6c6a7 --- /dev/null +++ b/py_project/MDK-ARM/DebugConfig/PY32F002Ax5_Project_PY32F002Ax5.dbgconf @@ -0,0 +1,25 @@ +// File: PY32F002Axx.dbgconf +// Version: 1.0.0 + +// <<< Use Configuration Wizard in Context Menu >>> + +// Debug MCU configuration register (DBGMCU_CR) +// DBG_STOP Debug stop mode +// +DbgMCU_CR = 0x00000002; + +// Debug MCU APB freeze1 register (DBG_APB_FZ1) +// Reserved bits must be kept at reset value +// DBG_LPTIM_STOP LPTIM stopped when core is halted +// DBG_IWDG_STOP Independent watchdog stopped when core is halted +// +DbgMCU_APB_Fz1 = 0x00000000; + +// Debug MCU APB freeze2 register (DBG_APB_FZ2) +// Reserved bits must be kept at reset value +// DBG_TIM16_STOP TIM16 counter stopped when core is halted +// DBG_TIM1_STOP TIM1 counter stopped when core is halted +// +DbgMCU_APB_Fz2 = 0x00000000; + +// <<< end of configuration section >>> diff --git a/py_project/MDK-ARM/JLinkSettings.ini b/py_project/MDK-ARM/JLinkSettings.ini new file mode 100644 index 0000000..c975f30 --- /dev/null +++ b/py_project/MDK-ARM/JLinkSettings.ini @@ -0,0 +1,44 @@ +[BREAKPOINTS] +ForceImpTypeAny = 0 +ShowInfoWin = 1 +EnableFlashBP = 2 +BPDuringExecution = 0 +[CFI] +CFISize = 0x00 +CFIAddr = 0x00 +[CPU] +MonModeVTableAddr = 0xFFFFFFFF +MonModeDebug = 0 +MaxNumAPs = 0 +LowPowerHandlingMode = 0 +OverrideMemMap = 0 +AllowSimulation = 1 +ScriptFile="" +[FLASH] +RMWThreshold = 0x400 +Loaders="" +EraseType = 0x00 +CacheExcludeSize = 0x00 +CacheExcludeAddr = 0x00 +MinNumBytesFlashDL = 0 +SkipProgOnCRCMatch = 1 +VerifyDownload = 1 +AllowCaching = 1 +EnableFlashDL = 2 +Override = 0 +Device="ARM7" +[GENERAL] +WorkRAMSize = 0xC00 +WorkRAMAddr = 0x20000000 +RAMUsageLimit = 0x00 +[SWO] +SWOLogFile="" +[MEM] +RdOverrideOrMask = 0x00 +RdOverrideAndMask = 0xFFFFFFFF +RdOverrideAddr = 0xFFFFFFFF +WrOverrideOrMask = 0x00 +WrOverrideAndMask = 0xFFFFFFFF +WrOverrideAddr = 0xFFFFFFFF +[RAM] +VerifyDownload = 0x00 diff --git a/py_project/MDK-ARM/PY32Dallas.uvoptx b/py_project/MDK-ARM/PY32Dallas.uvoptx index 6068466..82e1213 100644 --- a/py_project/MDK-ARM/PY32Dallas.uvoptx +++ b/py_project/MDK-ARM/PY32Dallas.uvoptx @@ -103,7 +103,7 @@ 1 0 0 - 6 + 4 @@ -114,9 +114,14 @@ - STLink\ST-LINKIII-KEIL_SWO.dll + Segger\JL2CM3.dll + + 0 + JL2CM3 + -U60145543 -O2126 -S1 -ZTIFSpeedSel10000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST3 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO7 -FD20000000 -FC800 -FN1 -FF0PY32F002Bxx_24.FLM -FS08000000 -FL06000 -FP0($$Device:PY32F002Bx5$CMSIS\Flash\PY32F002Bxx_24.FLM) + 0 ST-LINKIII-KEIL_SWO @@ -150,7 +155,7 @@ 0 DLGUARM - (105=-1,-1,-1,-1,0) + @@ -284,6 +289,10 @@ + + System Viewer\GPIOA + 35902 + System Viewer\TIM1 35903 @@ -389,7 +398,7 @@ 1 0 0 - 6 + 0 @@ -400,23 +409,18 @@ - STLink\ST-LINKIII-KEIL_SWO.dll + BIN\UL2CM3.DLL - - 0 - ST-LINKIII-KEIL_SWO - -U53FF72064980555724221187 -O1230 -SF1000 -C0 -A0 -I0 -HNlocalhost -HP7184 -P1 -N00("ARM CoreSight SW-DP (ARM Core") -D00(0BC11477) -L00(0) -TO131090 -TC10000000 -TT10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC800 -FN1 -FF0PY32F002Bxx_24.FLM -FS08000000 -FL06000 -FP0($$Device:PY32F002Bx5$CMSIS\Flash\PY32F002Bxx_24.FLM) -WA0 -WE0 -WVCE4 -WS2710 -WM0 -WP2 - 0 UL2CM3 - UL2CM3(-S0 -C0 -P0 ) -FN1 -FC800 -FD20000000 -FF0PY32F002Bxx_24 -FL06000 -FS08000000 -FP0($$Device:PY32F002Bx5$CMSIS\Flash\PY32F002Bxx_24.FLM) + UL2CM3(-S0 -C0 -P0 ) -FN1 -FC800 -FD20000000 -FF0PY32F0xx_20 -FL05000 -FS08000000 -FP0($$Device:PY32F002Ax5$CMSIS\Flash\PY32F0xx_20.FLM) 0 - CMSIS_AGDI - -X"" -O206 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC800 -FN1 -FF0PY32F002Bxx_24.FLM -FS08000000 -FL06000 -FP0($$Device:PY32F002Bx5$CMSIS\Flash\PY32F002Bxx_24.FLM) + JL2CM3 + -U11111118 -O2118 -S5 -ZTIFSpeedSel1000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST3 -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO7 -FD20000000 -FC800 -FN1 -FF0PY32F002Bxx_24.FLM -FS08000000 -FL06000 -FP0($$Device:PY32F002Bx5$CMSIS\Flash\PY32F002Bxx_24.FLM) 0 @@ -622,6 +626,30 @@ 1 3 + 2 + 0 + 0 + 0 + .\startup_py32f002ax5.s + startup_py32f002ax5.s + 0 + 0 + + + 1 + 4 + 1 + 0 + 0 + 0 + ..\Core\Src\system_py32f0xx.c + system_py32f0xx.c + 0 + 0 + + + 1 + 5 5 0 0 @@ -633,7 +661,7 @@ 1 - 4 + 6 5 0 0 @@ -645,7 +673,7 @@ 1 - 5 + 7 5 0 0 @@ -665,7 +693,7 @@ 0 2 - 6 + 8 1 0 0 @@ -677,7 +705,7 @@ 2 - 7 + 9 5 0 0 @@ -689,7 +717,7 @@ 2 - 8 + 10 1 0 0 @@ -701,7 +729,7 @@ 2 - 9 + 11 5 0 0 @@ -721,7 +749,7 @@ 0 3 - 10 + 12 1 0 0 @@ -733,7 +761,7 @@ 3 - 11 + 13 5 0 0 @@ -745,7 +773,7 @@ 3 - 12 + 14 1 0 0 @@ -757,7 +785,7 @@ 3 - 13 + 15 5 0 0 @@ -769,7 +797,7 @@ 3 - 14 + 16 1 0 0 @@ -781,7 +809,7 @@ 3 - 15 + 17 5 0 0 @@ -793,7 +821,7 @@ 3 - 16 + 18 1 0 0 @@ -805,7 +833,7 @@ 3 - 17 + 19 5 0 0 @@ -825,7 +853,7 @@ 0 4 - 18 + 20 1 0 0 @@ -837,7 +865,7 @@ 4 - 19 + 21 5 0 0 @@ -849,7 +877,7 @@ 4 - 20 + 22 1 0 0 @@ -861,7 +889,7 @@ 4 - 21 + 23 5 0 0 @@ -873,7 +901,7 @@ 4 - 22 + 24 1 0 0 @@ -885,7 +913,7 @@ 4 - 23 + 25 5 0 0 @@ -905,7 +933,7 @@ 0 5 - 24 + 26 1 0 0 @@ -917,7 +945,7 @@ 5 - 25 + 27 1 0 0 @@ -929,7 +957,7 @@ 5 - 26 + 28 1 0 0 @@ -941,7 +969,7 @@ 5 - 27 + 29 1 0 0 @@ -953,7 +981,7 @@ 5 - 28 + 30 1 0 0 @@ -965,7 +993,7 @@ 5 - 29 + 31 1 0 0 @@ -977,7 +1005,7 @@ 5 - 30 + 32 1 0 0 @@ -991,13 +1019,13 @@ Drivers/PY32F002B_HAL_Driver - 1 + 0 0 0 0 6 - 31 + 33 1 0 0 @@ -1009,7 +1037,7 @@ 6 - 32 + 34 1 0 0 @@ -1021,7 +1049,7 @@ 6 - 33 + 35 1 0 0 @@ -1033,7 +1061,7 @@ 6 - 34 + 36 1 0 0 @@ -1045,7 +1073,7 @@ 6 - 35 + 37 1 0 0 @@ -1057,7 +1085,7 @@ 6 - 36 + 38 1 0 0 @@ -1077,7 +1105,7 @@ 0 7 - 37 + 39 1 0 0 @@ -1089,7 +1117,7 @@ 7 - 38 + 40 1 0 0 @@ -1101,7 +1129,7 @@ 7 - 39 + 41 1 0 0 @@ -1113,7 +1141,7 @@ 7 - 40 + 42 1 0 0 @@ -1125,7 +1153,7 @@ 7 - 41 + 43 1 0 0 @@ -1137,7 +1165,7 @@ 7 - 42 + 44 1 0 0 diff --git a/py_project/MDK-ARM/PY32Dallas.uvprojx b/py_project/MDK-ARM/PY32Dallas.uvprojx index fb7187c..851ef52 100644 --- a/py_project/MDK-ARM/PY32Dallas.uvprojx +++ b/py_project/MDK-ARM/PY32Dallas.uvprojx @@ -395,6 +395,105 @@ 1 ..\Core\Src\system_py32f002b.c + + startup_py32f002ax5.s + 2 + .\startup_py32f002ax5.s + + + 2 + 0 + 0 + 0 + 0 + 0 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + + + + + + + + + + + + system_py32f0xx.c + 1 + ..\Core\Src\system_py32f0xx.c + + + 2 + 0 + 0 + 0 + 0 + 0 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + + interface_config.h 5 @@ -710,16 +809,16 @@ 1 - PY32F002Bx5 + PY32F002Ax5 Puya Puya.PY32F0xx_DFP.1.2.2 https://www.puyasemi.com/uploadfiles/ - IRAM(0x20000000,0x00000C00) IROM(0x08000000,0x00006000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + IRAM(0x20000000,0x00000C00) IROM(0x08000000,0x00005000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE - UL2CM3(-S0 -C0 -P0 -FD20000000 -FC800 -FN1 -FF0PY32F002Bxx_24 -FS08000000 -FL06000 -FP0($$Device:PY32F002Bx5$Flash\PY32F002Bxx_24.FLM)) + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC800 -FN1 -FF0PY32F0xx_20 -FS08000000 -FL05000 -FP0($$Device:PY32F002Ax5$CMSIS\Flash\PY32F0xx_20.FLM)) 0 - $$Device:PY32F002Bx5$Device\Include\py32f0xx.h + $$Device:PY32F002Ax5$Drivers\CMSIS\Device\PY32F0xx\Include\py32f0xx.h @@ -729,7 +828,7 @@ - $$Device:PY32F002Bx5$SVD\py32f002bxx.svd + $$Device:PY32F002Ax5$CMSIS\SVD\PY32F002Axx.svd 0 0 @@ -834,7 +933,7 @@ 1 BIN\UL2CM3.DLL - "" () + @@ -948,7 +1047,7 @@ 1 0x8000000 - 0x6000 + 0x5000 0 @@ -1084,11 +1183,110 @@ startup_py32f002bxx.s 2 .\startup_py32f002bxx.s + + + 2 + 0 + 0 + 0 + 0 + 0 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + + + + + + + + + system_py32f002b.c 1 ..\Core\Src\system_py32f002b.c + + + 2 + 0 + 0 + 0 + 0 + 0 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + + + + startup_py32f002ax5.s + 2 + .\startup_py32f002ax5.s + + + system_py32f0xx.c + 1 + ..\Core\Src\system_py32f0xx.c interface_config.h diff --git a/py_project/MDK-ARM/startup_py32f002ax5.s b/py_project/MDK-ARM/startup_py32f002ax5.s new file mode 100644 index 0000000..3f73080 --- /dev/null +++ b/py_project/MDK-ARM/startup_py32f002ax5.s @@ -0,0 +1,233 @@ +;****************************************************************************** +;* @file : startup_py32f002ax5.s +;* @brief : PY32F002Axx devices vector table for MDK-ARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM0+ processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;****************************************************************************** +;* @attention +;* +;* Copyright (c) 2021, Puya Semiconductor Inc. +;* +;* All rights reserved. +;* +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of the copyright holder nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +;* +;****************************************************************************** + +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000000 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD 0 ; 0Reserved + DCD 0 ; 1Reserved + DCD 0 ; 2Reserved + DCD FLASH_IRQHandler ; 3FLASH + DCD RCC_IRQHandler ; 4RCC + DCD EXTI0_1_IRQHandler ; 5EXTI Line 0 and 1 + DCD EXTI2_3_IRQHandler ; 6EXTI Line 2 and 3 + DCD EXTI4_15_IRQHandler ; 7EXTI Line 4 to 15 + DCD 0 ; 8Reserved + DCD 0 ; 9Reserved + DCD 0 ; 10Reserved + DCD 0 ; 11Reserved + DCD ADC_IRQHandler ; 12ADC + DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; 13TIM1 Break, Update, Trigger and Commutation + DCD TIM1_CC_IRQHandler ; 14TIM1 Capture Compare + DCD 0 ; 15Reserved + DCD 0 ; 16Reserved + DCD LPTIM1_IRQHandler ; 17LPTIM1 + DCD 0 ; 18Reserved + DCD 0 ; 19Reserved + DCD 0 ; 20Reserved + DCD TIM16_IRQHandler ; 21TIM16 + DCD 0 ; 22Reserved + DCD I2C1_IRQHandler ; 23I2C1 + DCD 0 ; 24Reserved + DCD SPI1_IRQHandler ; 25SPI1 + DCD 0 ; 26Reserved + DCD USART1_IRQHandler ; 27USART1 + DCD 0 ; 28Reserved + DCD 0 ; 29Reserved + DCD 0 ; 30Reserved + DCD 0 ; 31Reserved +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_15_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT TIM1_BRK_UP_TRG_COM_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT LPTIM1_IRQHandler [WEAK] + EXPORT TIM16_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +ADC_IRQHandler +TIM1_BRK_UP_TRG_COM_IRQHandler +TIM1_CC_IRQHandler +LPTIM1_IRQHandler +TIM16_IRQHandler +I2C1_IRQHandler +SPI1_IRQHandler +USART1_IRQHandler + B . + ENDP + + ALIGN + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END